Patent ID: 8354862

Claim:
A circuit comprising: a first circuit (PD 1 ) configured to receive an input signal (IN) and a first phase (CLK 0 ), a third phase (CLK 90 ) and a fifth phase (CLK 180 ) clocks of a clock, and generate a first early signal (EARLY A) indicating the clock is earlier than the input signal and a first late signal (LATE A) indicating the clock is later than the input signal; a second circuit (PD 2 ) configured to receive an input signal (IN) and a second phase (CLK 45 ), a fourth phase (CLK 135 ) and a sixth phase (CLK 225 ) clocks of the clock, and generate a second early signal (EARLY B) indicating the clock is earlier than the input signal and a second late signal (LATE B) indicating the clock is later than the input signal; a third circuit (B 1 ) configured to receive a first input being the first late signal (LATE A), a second input being the second late signal (LATE B), a third input being the first late signal (LATE A), a fourth input being the second early signal (EARLY B), and a fifth input being the first phase clock (CLK 0 ), and generate a first increase signal (UP 1 ); and a fourth circuit (B 2 ) configured to receive a first input being the first early signal (EARLY A), a second input being the second late signal (LATE B), a third input being the first early signal (EARLY A), a fourth input being the second late signal (LATE B), and a fifth input being the first phase clock (CLK 0 ), and generate a first decrease signal (DN 1 ).