Patent ID: 7827383

Claim:
A processor comprising: execution circuitry configured to execute a store instruction having one or more address operands and a data operand, wherein the execution circuitry is configured to generate a virtual address from the one or more address operands during execution of the store instruction, and wherein the execution circuitry is configured to transmit the virtual address and the data operand to a translation lookaside buffer (TLB); and the TLB coupled to receive the virtual address and configured to translate the virtual address to a first physical address, and wherein the TLB is further coupled to receive the data operand and to translate the data operand to a second physical address responsive to the store instruction targeting a hardware accelerator, and wherein the processor is configured to transmit the first physical address and the second physical address as the address and data of a store operation to the hardware accelerator targeted by the store instruction, and wherein the processor is configured to transmit the first physical address and the data operand as the address and data of the store operation to a memory controller to access memory responsive to the store instruction targeting memory instead of the hardware accelerator.