Patent ID: 8615634

Claim:
A method of data processing in a data processing system including a processor core, a multi-level cache memory hierarchy including a lowest level cache, a memory controller, and a system memory, wherein the lowest level cache includes a cache controller that controls read and write access to a cache array of the lowest level cache and updates a cache directory of the lowest level cache to maintain coherence, wherein the lowest level cache includes a virtual write queue into which the memory controller has visibility, and wherein the virtual write queue is formed of only a subset of a cache array of the lowest level cache, said method comprising: the memory controller controlling read and write access to the system memory, wherein the system memory forms a lowest level of storage addressable by a real address space of the processor core, wherein the memory controller includes a physical write queue from which the memory controller write data received from the lowest level cache to the system memory, and wherein the controlling includes: the memory controller determining addresses of data present in the physical write queue of the memory controller; in response to the determining, the memory controller initiating cleaning accesses to the lowest level cache to place into the physical write queue copies of selected cachelines of data from the virtual write queue having spatial locality with the data present in the physical write queue without removing the selected cachelines from the lowest level cache; and in response to receipt of the copies of the selected cachelines of data, the memory controller placing the copies of the selected cachelines of data in the physical write queue and thereafter writing at least some of the copies of the selected cachelines and the data present in the physical write queue to the system memory in a write burst operation.