Patent ID: 8330745

Claim:
A pulse output circuit for sequentially outputting pulses from different output terminals, the pulse output circuit comprising: a shift register including a plurality of latch stages, connected in series, which have flip-flops for generating first pulses serving as source pulses of the pulses outputted from the output terminals, respectively; and a delay trimming circuit for (i) generating second pulses from the first pulses, respectively, each of the second pulses having: start timing obtained by a delay of start timing of a first pulse; and end timing generated using start timing of an input pulse to a flip-flop in a first latch stage existing immediately after a second latch stage in which the first pulse is generated, the input pulse not having passed through the flip-flop of the first latch stage existing immediately after the second latch stage and (ii) outputting the second pulse as a pulse to be outputted from a corresponding one of the output terminals, wherein: the first latch stage existing immediately after the second latch stage includes a hazard preventing circuit for outputting an output signal as an enable signal by a delay of the output signal of the flip-flop of the second latch stage, and a level shifter for (i) carrying out a level-shifting operation with use of the enable signal inputted from the hazard preventing circuit and (ii) generating the input pulse to the flip-flop of the first latch stage existing immediately after the second latch stage; the hazard preventing circuit of the first latch stage existing immediately after the second latch stage delays the output signal of the flip-flop of the second latch stage so that end timing of the input pulse to the flip-flop, which input pulse is generated by the level shifter, is later than timing obtained by a delay of end timing of the first pulse of the second latch stage.