Patent ID: 7913018

Claim:
A method comprising halting at least one processing core of a computer system including a processor comprising a plurality of processing cores and a plurality of interrupt controllers, each interrupt controller associated with one of the plurality of processing cores and each interrupt controller to receive a system management interrupt comprising interrupt information and a core identifier of a system management interrupt configuration register to store an interrupt vector and a core identifier for a system management interrupt, to halt the associated processing core if the associated processing core does not correspond to the core identifier of the system management interrupt, and to cause the associated processing core to execute a handler associated with the interrupt vector of the system management interrupt if the associated processing core corresponds to the core identifier of the system management interrupt, in response to the system management interrupt, and in response to halting the at least one processing core, setting a corresponding bit of a halt status register that comprises a bit for each processing core of the computer system, and handling the system management interrupt with at least one other processing core of the computer system in response to determining that the at least one processing core is halted, including starting the handling of the system management interrupt with the at least one other processing core in response to the halt status register indicating all processing cores besides the at least one other processing core have been halted, wherein the handling is to cause the at least one other processing core to wait for the halt status register to indicate that the at least one processing core has halted before proceeding with the system management interrupt handling.