Patent ID: 7915931

Claim:
A power sequencing circuit, comprising: a voltage (V 1 ) coupled at a first node to an emitter of a PNP transistor (Q 1 ); a first resistor (R 1 ) coupled between the first node and a base of (Q 1 ); a second resistor (R 2 ) coupled between the base and a grounded node; a third resistor (R 3 ) coupled between the grounded node and a collector of Q 1 ; a logic enabled regulator (U 1 ) having an enable pin (P 1 ) coupled to and driven by the collector; a voltage divider ratio of R 1 to R 1 plus R 2 which maintains an output voltage (V 2 ) of U 1 in an off condition until V 1 rises above a first threshold (V 1 thresh); a base-emitter voltage (Vbe) of Q 1 metered to V 1 by the voltage divider and thereby maintained below a Q 1 turn-on voltage (Von) until V 1 rises above V 1 thresh; and an enable voltage (Venable) associated with P 1 , wherein U 1 does not regulate V 2 until a voltage at P 1 reaches the enable voltage.