Patent ID: 7020018

Claim:
A structure of nonvolatile memory, comprising: a plurality of doped region lines, formed in a semiconductor substrate to serve as a plurality of bit lines; a dual-bit memory cell between adjacent two of the bit lines, further comprising: a selection transistor, formed over the substrate between the two bit lines, wherein the selection transistor is provided by a selection gate line; two memory transistors, respective formed between the selection transistor and the two bit lines, wherein each of the memory transistors has a charge-storage stacked dielectric layer as a gate insulating layer with capacity of storing charges; and two control transistors, also respectively formed between the selection transistor and the two bit lines, wherein the memory transistors, the control transistors and the selection transistor coupled in series to serving as the dual-bit memory cell; a plurality of word lines over the substrate, crossing over the bit lines, wherein each of the word lines electrically coupled with gate electrodes of the memory transistors and the control transistors; and an insulating structure layer, for insulation the word lines from the bit lines and the selection gate electrode of the selection transistor.