Patent ID: 8728936

Claim:
An method for forming an interconnect structure, comprising: depositing a sacrificial layer overlying a semiconductor substrate having a conductive region and covering the conductive region; depositing a hard mask layer overlying the sacrificial layer; patterning the hard mask layer and etching through the hard mask layer and the sacrificial layer to form a first feature defined by an opening in the sacrificial layer; depositing a metal layer overlying the first feature and filling the opening to form a metal body therein, the metal body defined by a lower portion of the metal layer; patterning and etching an upper portion of the metal layer to form a second feature having first recesses in an upper portion of the metal layer and defined by a vertical projection extending from the metal body; removing the sacrificial layer to expose opposing sidewalls of the metal body and form second recesses about opposing sidewalls; depositing a low-k dielectric material overlying an upper surface of the vertical projection and filling first and second recesses; and removing excess dielectric layer and exposing an upper surface of the vertical projection.