Patent ID: 6901573

Claim:
A method for creating a logic circuit with an optimized number of AND/OR switches to evaluate a logic function FUNC(x,y), comprising steps of: (a) defining said logic function FUNC(x,y) in terms of control inputs x 1 , x 2 , . . . , x n , n>1, data inputs y 1 , y 2 , . . . , y m , m>1, and at least one operator OP i , i={overscore (1, N)}, {overscore (1, N)}=1, 2, 3, . . . , N, each of said at least one operator OP i being an IF-operator, an EQ-operator, or a SEQ-operator; (b) evaluating dependency relationship among said at least one operator OP i ; and (c) creating said logic circuit based on said dependency relationship; wherein said step (b) comprises: (b1) evaluating Term i (x) for said each of said at least one operator OP i , wherein Term i (x)=1 when OP par(i) is a SEQ-operator, Term i (x)=x j when OP par(1) is an IF-operator with control input x j and OP i is a positive child, and Term i (x)= x j if OP par(i) is an IF-operator with control input x j and OP i is a negative child; (b2) evaluating a set AllParents( 1 )={par 0 ( 1 ), par 1 ( 1 ), . . . , par d(1) ()} for said each of said at least one operator OP i ; (b3) evaluating a set AllParentsBeforeSeq( 1 )={par 0 ( 1 ), par 1 ( 1 ), . . . , par seq(1)−1 ( 1 )} for said each of said at least one operator OP i ; (b4) evaluating a set AllSeqParents( 1 )={par seq(1) ( 1 ), par seq(seq(1)) ( 1 ), . . . , par d(i) (i)} for said each of said at least one operator OP i ; and (b5) evaluating a set common(i,s)=par d(i,s) (s) for said each of said at least one operator OP i and OP s .