Patent ID: 8397107

Claim:
A data storage device comprising: a non-volatile memory comprising a plurality of memory segments; and control circuitry operable to: receive a write command comprising a logical block address (LBA) and user data; map the LBA to a physical block address (PBA) for addressing one of the memory segments; generate first error code redundancy in response to the LBA; generate second error code redundancy in response to the PBA; write user data and the first and second error code redundancy to the memory segment addressed by the PBA; write the LBA to the memory segment addressed by the PBA; read the user data, the LBA, and the first and second error code redundancy from the memory segment addressed by the PBA; generate a first error syndrome in response to the PBA and the LBA, the user data, and the first and second error code redundancy read from the memory segment; correct at least one error in the LBA read from the memory segment to generate a corrected LBA; generate a second error syndrome in response to the corrected LBA; and detect an error in response to the second error syndrome.