Patent ID: 8607131

Claim:
A decoder comprising: a log likelihood ratio calculation section that calculates first log likelihood ratio sequence using second coded sequence formed by removing bits in first coded sequence s, the first coded sequence s satisfying equation 1-1, equation 1-2 and equation 1-3, and being made up of z×n b bits from a first bit to a z×n b -th bit, the equation 1-1, equation 1-2 and equation 1-3 being generated for first bit information bit sequence u, the second coded sequence being formed by removing the bits from a z×y+1-th bit to a z×(y+1)-th bit (y is an integer between 0 and (n b −1)) in the first coded sequence s based on a y-th puncturing pattern, and the y-th puncturing pattern corresponding to the number of columns z ranging from z×y+1 columns to z×(y+1) columns and having a cycle of divisors of the number of columns z; an insertion section that generates second log likelihood ratio sequence in which a predetermined log likelihood ratio is inserted to the first log likelihood ratio sequence based on the y-th puncturing pattern; and a BP decoding section that decodes the second log likelihood ratio sequence based on the parity check matrix H and outputs the first information bit sequence u: GH T =0 (Equation 1-1) s T =Gu T (Equation 1-2) Hs= 0 (Equation 1-3) where H is a parity check matrix of an low density parity check code of (z×m b ) rows and (z×n b ) columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 1-1 with the parity check matrix H of the low density parity check code and the first coded sequence s is a coded sequence made up of z×n b bits.