Patent ID: 8364862

Claim:
An apparatus comprising: a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect; a coherent interconnect coupled to the core; the IO interconnect coupled to the coherent interconnect, the IO interconnect including a poll table having a plurality of entries each having a register address field to store a register address received in a registration message, a destination address field to store a destination address in a system memory received in the registration message, and an initial value field to store an initial value associated with the register address received in the registration message; and at least one device coupled to the IO interconnect to perform an operation for an application executing on the core and including at least one status register, the IO interconnect to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from the initial value, the IO interconnect further including a poll delegation logic to issue a read request to the at least one device at a predetermined interval to perform the poll.