Patent ID: 8482038

Claim:
A semiconductor device comprising: a core area surrounded by a plurality of I/O areas; a first one of said plurality of I/O areas configured to receive a first supply voltage; a second one of said plurality of I/O areas configured to receive a second supply voltage which is lower than the first supply voltage; a first I/O circuit included in the first one of said plurality of I/O areas; a second I/O circuit included in the second one of said plurality of I/O areas; first and second signal wires; and first and second shield wires each running parallel to the first and the second signal wires, wherein the first I/O circuit receives a first and a second signal outputted from the second I/O circuit via the first and the second signal wires, and outputs a level shifted signal from the second supply voltage to the first supply voltage, wherein the second signal is inverted with respect to the first signal, wherein the first and the second signal wires pass over a plurality of I/O cells included in the plurality of I/O areas, and wherein a length of the first signal wire portion which passes over top surfaces of the plurality of I/O cells is equal to a length of the second signal wire portion which passes over the top surfaces of the plurality of I/O cells.