Patent ID: 7080269

Claim:
A synchronous circuit core, comprising: a sleep controller coupled to receive a sleep request signal and configured to produce a sleep acknowledge signal in response to the sleep request signal; a primary clock domain and a secondary clock domain, wherein the primary clock domain is coupled to the sleep controller; synchronization logic coupled between the primary and secondary clock domains and configured to synchronize signals between the primary and secondary clock domains; wherein the primary clock domain comprises a primary-side idle timer coupled to receive an idle signal from the primary clock domain and another idle signal from the secondary clock domain, and configured to use the idle signals to determine whether the primary and secondary clock domains have been idle for a programmable period of time, and wherein the primary clock domain is configured to produce the sleep request signal in the event the primary and secondary clock domains have been idle for the programmable period of time; wherein the primary clock domain is configured to receive the sleep acknowledge signal from the sleep controller, and to provide the sleep acknowledge signal to the secondary clock domain via the synchronization logic; wherein the sleep acknowledge signal experiences a synchronization delay time in propagating through the synchronization logic; and wherein the secondary clock domain comprises a secondary-side idle timer having a time delay, and wherein the secondary clock domain is configured to produce the idle signal from the secondary clock domain after the secondary clock domain has remained idle for the time delay of the secondary-side idle timer, and wherein the time delay of the secondary-side idle timer is greater than or equal to the synchronization delay time.