Patent ID: 8446813

Claim:
A method comprising: directly solving control bits for a butterfly network of switches iteratively for each successive functional column of the switches so as to route data values in parallel according to a multiple access scheme through the butterfly network of switches to a plurality of memory spaces by: for each of the data values, generating an address of one of the memory spaces with an appended bus index leading into the butterfly network of switches based on the multiple access scheme; detecting a switch in a functional column of the butterfly network in a linear order access having an unsolved control bit; determining a bus index j and a physical address k for the switch in input of the butterfly network in a linear order access; applying the solved control bits to the switches of the butterfly network so as to solve control bits to a next functional column of the butterfly network of switches in a linear order access and in an interleaved order access by starting from the bus index j and the physical address k; and moving from the butterfly network of switches in the linear order to the butterfly network of switches in the interleaved order by a reduced turbo de-interleaver and from the butterfly network of switches in the interleaved order to the butterfly network of switches in the linear order by a reduced turbo interleaver until a sequence of control bits related to the start bus index j and the start physical address k has been solved.