Patent ID: 7840786

Claim:
A memory subsystem, comprising: a first memory configured to store instruction bytes of a fetch window, wherein the first memory is further configured to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window; a second memory configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory, wherein the second memory is further configured to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window; a first compressor coupled between the first memory and the second memory, wherein the first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information without compressing the instruction bytes of the fetch window; and a first decompressor coupled between the second memory and a third memory, wherein the first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information for storage in the third memory, wherein the second predecode information corresponds to an uncompressed version of the first predecode information.