Patent ID: 7043672

Claim:
In a memory device having at least two memory sub-arrays of memory cells arranged in rows and columns, each memory sub-array having redundant row and column memory and redundant row and column memory addresses associated therewith identifying memory locations of the respective memory sub-arrays to be remapped to the redundant rows and columns of memory, all respectively, a method for accessing the memory device comprising: receiving a memory command and a memory address having row and column addresses to access a location in memory corresponding to the memory address; selecting the redundant row and column addresses of one of the two memory sub-arrays to be coupled to a comparison circuit for comparison to the memory addresses based on the memory address received; selecting the redundant row addresses of the selected memory sub-array to be coupled to the comparison circuit during a first time for comparison to the row address; selecting the redundant column addresses of the selected memory sub-array to be coupled to the comparison circuit during a second time for comparison to the column address; and in response to the row or column addresses of the memory address matching any of the redundant row or column addresses of the selected memory sub-array, accessing the redundant row or column of memory associated with the matching redundant row or column address, or accessing the memory location in the selected memory sub-array corresponding to the memory address otherwise.