Patent ID: 7329602

Claim:
A method for fabricating a wiring structure for an integrated circuit, the method comprising steps of: forming a plurality of features in a first and a second layer of dielectric material, each of the features having sidewalls and a bottom, said bottom and a portion of said sidewalls being formed in said first layer of dielectric material, said dielectric material of said bottom and said portion of said sidewalls being a same dielectric material; forming spacers on the sidewalls; forming conductors in the features, the conductors being separated from the sidewalls by the spacers; removing the spacers, thereby forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps; and forming a third layer of dielectric material, having a dielectric constant less than that of said second layer of dielectric material, overlying said second layer of dielectric material and said conductors.