Patent ID: 7595973

Claim:
A multilayer chip capacitor comprising: a capacitor body having a plurality of dielectric layers laminated therein, the capacitor body comprising first and second capacitor units disposed in a laminated direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first and third outer electrodes have identical polarity to each other and the second and fourth outer electrodes have identical polarity to each other but different polarities from the first outer electrode; and at least one connecting conductor line connecting the first outer electrode and the third outer electrode to each other and the second outer electrode and the fourth outer electrode to each other, wherein the first capacitor body comprises first and second inner electrodes of different polarities disposed to oppose each other while interposing a corresponding one of the dielectric layers, the second capacitor unit comprises a plurality of third and fourth inner electrodes arranged alternately to oppose each other, while interposing corresponding ones of the dielectric layers, respectively the first to fourth outer electrodes are connected to the first to fourth inner electrodes, respectively, and an equivalent series resistance of the first capacitor unit and a combined equivalent series resistance of the second capacitor and the connecting conductor line satisfy the following Equation: 0.7( R 1)≦ R 2′≦1.3( R 1) Equation, where R 2 ′ is the combined equivalent series resistance of the second capacitor and the connecting conductor and R 1 is the equivalent series resistance of the first capacitor unit.