Patent ID: 8799726

Claim:
A method of testing a plurality of stacked memory device dice coupled to a logic circuit die and being configured for access according to a plurality of vaults, the method comprising: receiving, at the logic circuit die, a write command signal from a first unidirectional interface, a first address signal from a second unidirectional interface, and write data from a bidirectional interface; combining the write command, the first address signal, and the write data into a write packet; broadcasting the write packet to the plurality of the vaults; writing the write data to a location corresponding to the first address signal in each of the plurality of the vaults; receiving at the logic circuit die a read command signal and a second address signal from the respective separate interfaces; combining at least the read command and the second address signal into a read packet; broadcasting the read packet to the plurality of the vaults; receiving read data corresponding to the second address signal from each of the plurality of the vaults; reformatting the read data in a manner expected by a tester; and outputting the reformatted data to the bidirectional interface including an indication of whether any of the vaults provided read data differing from read data provided by any of the other plurality of vaults.