Patent ID: 7556976

Claim:
A method of fabricating a semiconductor device comprising the steps of: providing a series of layers formed on a substrate, said layers including a first plurality of layers comprising n-type dopant material, a second plurality of layers that form a p-type modulation doped quantum well structure, and a third plurality of layers including at least one layer comprising n-type dopant material, wherein said first plurality of layers includes an n-type ohmic contact layer and a first etch stop layer formed above said n-type ohmic contact layer for contacting said n-type ohmic contact layer; performing an etching operation that automatically stops at said first etch stop layer; removing remaining portions of said first etch stop layer to expose first areas of said n-type ohmic contact layer; depositing a first metal layer on said first areas of said n-type ohmic contact layer to form an emitter terminal electrode of a first-type transistor device; and depositing a second metal layer that is electrically coupled to said p-type modulation doped quantum well structure to form a base terminal electrode of said first-type transistor device; and depositing a third metal layer that is operably coupled to said third plurality of layers to form a collector terminal electrode of said first-type transistor device.