Patent ID: 8213184

Claim:
A method, comprising: temporarily physically and electrically contacting an integrated circuit chip to a first array of pads of an interposer of a temporary chip attach carrier, said carrier comprising: a carrier substrate, a first array of interconnects disposed on a bottom surface of said carrier substrate and a second array of interconnects disposed on a top surface of said carrier substrate, corresponding interconnects of said first and second arrays of interconnects electrically connected by wires in said carrier substrate; said interposer, said interposer having a flat top surface and an opposite and flat bottom surface, said interposer comprising said first array of pads, a second array of pads and a semiconductor interposer substrate, said first array of interposer pads disposed on or embedded in said top surface of said interposer and each pad of said second array of pads disposed on said bottom surface of said interposer substrate, corresponding pads of said first array of pads and pads of said second arrays of pads electrically connected by electrically conductive through vias passing through said interposer substrate, said through vias electrically isolated from said interposer substrate, said interposer substrate comprising a same material as a substrate of said integrated circuit chip; pads of said second array of pads electrically connected to corresponding interconnects of said first array of interconnects by solder bumps; wherein the spacing between interconnects of said first array of interconnects is greater than the spacing between interconnects of said second array of interconnects which is greater than the spacing between pads of said first array of pads; and connecting interconnects of said first array of interconnects to a tester; and testing said one or more integrated circuit chips, said testing comprising at least one of functional testing and reliability testing.