Patent ID: 6885328

Claim:
A digitally-switched impedance for an n-bit digital input signal, comprising: high and low reference nodes; one “type B” stage and at least two “type A” stages, each of said type A stages comprising an upper stage and a lower stage, each of which has an input node and an output node, and said type B stage having first and second input nodes and a final output node; said type A stages coupled between said high and low reference nodes and said type B stage such that: the upper and lower input nodes of a first type A stage are connected to said high and low reference nodes, respectively, and the upper and lower output nodes of each type A stage are connected to the upper and lower input nodes, respectively, of a following type A stage, except for the last type A stage, the upper and lower output nodes of which are connected to the first and second input nodes, respectively, of said type B stage; each of said upper and lower stages comprising: a string of predetermined series-connected impedances, and a switch network arranged to connect a selected number of said string's series-connected impedances between said stage's input node and output node; said type B stage comprising: a string of predetermined impedances series-connected between said first and second input nodes, and a switch network connected to said string to provide a selectable tap from said string to said final output node; and a decoder which responds to an n-bit digital input signal by controlling said switch networks to switch selectable portions of the strings in said type A stages into a series connection with said type B stage's string, said decoder further controlling said type B stage's switch network to tap said type B stage's string at a location to provide a impedance corresponding to said n-bit digital input signal between said final output node and at least one of said high and low reference nodes, the selected portions having a substantially constant aggregate series impedance Z total between said high and low reference nodes over the switching ranges of said type A stages, the number and impedance values of the impedances in said stages arranged such that each stage provides a portion of the digitally-switched impedance's n-bit resolution and that the sum of the bits of resolution provided by each stage equals the total n-bit resolution.