Patent ID: 6963103

Claim:
A memory cell, comprising: a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the NMOS transistors includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; and a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al 2 O 3 ), wherein the low tunnel barrier intergate insulator includes a further transition metal oxide; and a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes.