Patent ID: 8344930

Claim:
A successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a first capacitor array comprising a plurality of first switched capacitors therein with varying weights, wherein each of the first switched capacitors has one node selectively connected to a first signal or a first default voltage, and has another node connected to a first common node; a first input capacitor, coupled between the first common node and a first output node; a first switch module, arranged for selectively coupling the first common node to a common voltage and selectively coupling the first output node to a second signal; a second capacitor array comprising a plurality of second switched capacitors therein with varying weights, wherein each of the second switched capacitors has one node selectively connected to a second signal or a second default voltage, and has another node connected to a second common node; a second input capacitor, coupled between the second common node and a second output node; a second switch module, arranged for selectively coupling the second common node to the common voltage and selectively coupling the second output node to the first signal; a comparator, coupled to the first input capacitor and the second input capacitor, for comparing voltages at the first output node and the second output node to generate a comparing result; and a SAR controller, coupled to the comparator, for controlling the first capacitor array and the second capacitor array according to the comparing result.