Patent ID: 8531221

Claim:
A delay lock loop circuit comprising: a voltage controlled delay line (VCDL) comprising: a plurality of delay units for generating a plurality of specific phase differential signals according to an input clock source and a control voltage; and a phase selector for receiving the one of the plurality of specific phase differential signals to output an inversion signal of the one of the plurality of specific phase differential signals as a feedback signal; a detector for comparing at least one of phases and frequencies of the input clock source and the feedback signal to generate at least one detection signal; a charge pump for generating the control voltage according to the at least one detection signal; and a phase selection buffer for generating an output clock source according to the plurality of specific phase differential signals; wherein each of the plurality of specific phase differential signals comprises at least a non-inversion signal and an inversion signal, and the feedback signal is the inversion signal of one of the plurality of specific phase differential signals.