Patent ID: 7821812

Claim:
A dynamic random access memory, comprising: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode most significant bits (MSB bits) of the column address to locally enable a part of a page area corresponding to the row address; and a column decoder configured to decode the column address, wherein the address latch comprises: a latch configured to latch an address bit in response to an internal clock; a first logic unit configured to perform an AND operation on the latched address bit and the RAS signal in outputting the row address; at least one flip-flop configured to delay the latched address bit by an additive latency; and a second logic unit configured to perform an AND operation on an output signal of the at least one flip-flop and the CAS signal in outputting the column address.