Patent ID: 7538018

Claim:
A method for fabricating a gate structure, comprising: sequentially forming a pad oxide layer, a pad conductive layer and a dielectric layer over a substrate; removing a portion of the dielectric layer to form an opening exposing a portion of the pad conductive layer; forming a liner conductive layer to cover the dielectric layer and the pad conductive layer; removing a portion of the liner conductive layer and a portion of the pad conductive layer to expose a surface of the pad oxide layer to form a conductive spacer at a sidewall of the opening; removing the pad oxide layer at a bottom of the opening; forming a gate oxide layer over the substrate; sequentially forming a first gate conductive layer and a second gate conductive layer over the gate oxide layer at a bottom of the opening, wherein an upper surface of the second gate conductive layer is lower than an upper surface of the dielectric layer; removing a portion of the gate oxide layer until an upper surface of the gate oxide layer is lower than an upper surface of the second gate conductive layer; and forming a cap layer to fill up the opening.