Patent ID: 8193062

Claim:
A method of making a memory cell comprising: doping a first region of a semiconductor substrate with at least one of an n-type and a p-type dopant and doping a second region of the semiconductor substrate with at least one of the n-type and the p-type dopant; forming over the first region a pair of symmetric access transistors; forming over the first region at least one pair of pull-down transistors that are at least one of symmetric and asymmetric; forming over the second region at least one pair of pull-up transistors that are at least one of symmetric and asymmetric; coupling the pair of pull-down transistors and the pair of pull-up transistors between the pair of access transistors to form a memory cell; and performing an asymmetric halo implant on at least one of the pair of pull-down transistors and the pair of the pull-up transistors, wherein the asymmetric halo implant includes performing a single-sided halo implant on the at least one of the pair of pull-down transistors and the pair of the pull-up transistors and a dual sided halo implant on the other of the at least one of the pair of pull-down transistors and the pair of the pull-up transistors.