Patent ID: 7483332

Claim:
Circuitry for writing to and reading from an SRAM cell core, comprising: a write circuit coupled to said SRAM cell core and including at least one write transistor having an electrical characteristic; and a read circuit coupled to said SRAM cell core and including at least one read transistor having an electrical characteristic that differs from said electrical characteristic of said at least one write transistor, wherein said at least one write transistor and said at least one read transistor have a common gate signal, wherein said SRAM cell core comprises: a first inverter comprising a first load transistor and a first driver transistor, said first inverter having an input and an output; and a second inverter, cross-coupled with said first inverter, comprising a second load transistor and a second driver transistor, said second inverter having an input and an output, and wherein said read circuit further includes at least one read drive transistor, a gate of said read drive transistor coupled to the output of said second inverter, and a drain of said read drive transistor coupled to a source of said at least one read transistor.