Patent ID: 8379468

Claim:
A memory comprising: an address decoder configured to receive an address and select a word line as a selected word line from a plurality of word lines; a word line driver coupled to the address decoder and configured to activate the selected word line; a read only memory (ROM) coupled to the word line driver and having N bit positions, wherein each row of the ROM is coupled to a corresponding word line from the word line driver and stores an unique N bit value, wherein N is an integer value greater than or equal to one; and detection logic coupled to the ROM, wherein the detection logic is configured to: for each bit position of the N bit positions, determine whether a value of a first bit line of the bit position is at a same logic state as a value of a second bit line of the bit position when the word line driver activates the selected word line, and provide a first indicator indicative of a multiple word line fault based on whether the first bit line is at the same logic state as the second bit line for any of the N bit positions.