Patent ID: 7020135

Claim:
A rearrangeable, non-blocking switch, comprising: a first stage including a plurality of first switch circuits, each of said plurality of first switch circuits including a plurality of inputs and a plurality of outputs; a second stage including a plurality of second switch circuits, each of said plurality of second switch circuits including a plurality of inputs, each of which being respectively coupled to one of said plurality of outputs of each of said plurality of first switch circuits, and a plurality of outputs, a number of said plurality of second switch circuits equaling N, where N is an integer other than a power of 2; and a third stage including a plurality of third switch circuits, each of said plurality of third switch circuits including a plurality of inputs and a plurality of outputs, each of said plurality of inputs of each of said plurality of third switch circuits being coupled to a respective one of said plurality of outputs of each of said plurality of second switch circuits, wherein at least some of said plurality of second switch circuits are each configured as a plurality of logical switch circuits, wherein a Looping Algorithm is used as a control algorithm for the switch.