Patent ID: 8916875

Claim:
A semiconductor package, comprising: a first semiconductor chip mounted on a first package substrate; a chip package stacked on the first semiconductor chip, the chip package comprising a second package substrate and a second semiconductor chip mounted on the second package substrate; and a first terminal connecting the chip package directly and electrically to the first semiconductor chip, wherein the second package substrate comprises: a first pad coupled to the first terminal; a second pad electrically connected to the first pad and electrically spaced apart from the first terminal; a third pad electrically connected to the second semiconductor and electrically connected to the first pad via the second pad; and a fourth pad electrically connected to the second semiconductor chip via the third pad, and electrically connected to the first pad via the second pad, wherein: the third and fourth pads are disposed on an upper surface of the second package substrate on which the second semiconductor chip is mounted, the first and second pads are placed on a lower surface of the second package substrate opposite the upper surface, and the fourth pad is fully covered by an upper insulating layer on the upper surface of the second package substrate, wherein the second pad is not directly coupled to the first terminal.