Patent ID: 8793630

Claim:
A method for clock tree planning for an application specific integrated circuit (ASIC), the method comprising: determining a netlist and a timing constraint file of the ASIC; using a processor, creating a sequential device undirected graph for the sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; using a processor, grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group; and wherein the creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file comprises: creating a connection undirected graph for the sequential devices in the netlist according to the connection relationships of the sequential devices in the netlist; creating a timing undirected graph for the sequential devices in the netlist according to the timing constraint relationships of the sequential devices in the timing constraint file; and combining the connection undirected graph and the timing undirected graph to obtain the sequential device undirected graph.