Patent ID: 7599974

Claim:
A data processing apparatus for comparing first and second floating point operands to produce a comparison result, each first and second floating point operand having a sign component, an exponent component and a fraction component, the data processing apparatus comprising: first processing logic circuitry configured to receive, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, said predetermined number being less than the total number of bits constituting the fraction component, the first processing logic circuitry being further configured to receive the sign components and the exponent components of the first and second floating point operands, to compare the sign components, the exponent components and the first components of the first and second floating point operands, and to produce a plurality of signals indicative of the comparison; evaluation logic circuitry configured to evaluate whether the comparison result is determinable from the plurality of signals, and if so, to determine the comparison result; second processing logic circuitry configured, in the event that the evaluation logic circuitry determines that the comparison result is not determinable from the plurality of signals, to receive, for each floating point operand, a second component derived from at least the bits of the fraction component of that floating point operand other than said predetermined number of most significant bits, and to compare the second components of the first and second floating point operands in order to produce at least one further signal indicative of said comparison; and the evaluation logic circuitry being further configured to determine the comparison result from said plurality of signals and said at least one further signal.