Patent ID: 7254677

Claim:
A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device comprising: a FIFO memory array embedded in the programmable logic device having a data output port; an output register coupled to the data output port of the FIFO memory array; a first-word detection circuit prefetching a first word written through the FIFO memory array when the FIFO memory array is empty, and asserting a DATA VALID signal if the first word is available to be read from the output register; and an empty logic circuit asserting an empty flag when a read pointer is equal to a write pointer after the FIFO memory array is determined to be almost empty and the DATA VALID signal is not asserted, and de-asserting the empty flag when the DATA VALID signal is asserted, wherein the first word written through the FIFO memory array is available on an output of the output register when the empty flag is de-asserted before a read enable signal is asserted.