Patent ID: 8611158

Claim:
A method comprising performing an erase operation on a memory stack that includes first and second selector transistors and a plurality of memory cell transistors connected in series between the first and second selector transistors, the memory cell transistors including a first memory transistor adjacent to the first selector transistor and a second memory cell transistor adjacent to the second selector transistor, the performing the erase operation comprising: applying a bias voltage to a gate of each of the first and second selector transistors to release the gate of each of the first and second selector transistors from an electrically floating condition; applying an erase voltage to a gate of each of the first and second memory transistors, applying an additional erase voltage to a semiconductor region in which the memory cell transistors are formed; and after applying the bias voltage, the erase voltage, and the additional erase voltage respectively to the gate of each of the first and second selector transistors, the gate of each of the first and second memory transistors, and the semiconductor region, programming each of the first and second selector transistors.