Patent ID: 7490121

Claim:
A method of implementing binary multiplication in a processing device, the method comprising: inputting a multiplicand and a multiplier from a storage device into a modular binary multiplier device, the modular binary multiplier device further having an input merge register to receive the multiplicand and recording logic configured to receive the multiplier; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning data bits of the multiplicand into first and second multiplicand subgroups and at least one of zeroing out of bits of the second multiplicand subgroup and sign-extending the second multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the first and second multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the first and second multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples, and outputting at least the first modular product to combinational logic, the first modular product for use in a processor architecture.