Patent ID: 7274235

Claim:
Electronic circuitry comprising a plurality of successive stages, alternately odd and even stages, each stage comprising at least one combinatory logic circuit having at least one output connected to the input of an associated first latch, a clock signal being applied to a clock input of each first latch, the clock signal successively taking, during a clock cycle, a high level between a rising front and a descending front, and a low level from said descending front until the rising front of the next clock cycle, first and second clock signals being respectively applied to the clock input of the first latches of the odd stages and of the first latches of the even stages, the first and second clock signals being offset without overlapping of their high levels, and the circuitry comprising means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, the means for detecting comprising, in each stage, monitoring means which compare: an output value, present on the output of the first latch of the stage considered at an observation time comprised between the descending front of each cycle of the corresponding clock signal and the rising front of the next cycle of said clock signal, with an input value, present on the input of said first latch at an observation time comprised between a first time, that follows the previous descending front of the other clock signal by a first time interval that corresponds to a maximum propagation time of the combinatory logic circuit of said stage and a second time, that follows the next rising front of said other clock signal by a second time interval, that is equal to the sum of a minimum propagation time of the first latch of the previous stage and of a minimum propagation time of the combinatory logic circuit of the stage considered.