Patent ID: 7749824

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact layer; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist layer on the passivation layer, wherein the first photoresist layer does not cover at least a portion of the passivation layer and the gate insulating layer; etching the passivation layer and the gate insulating layer which are not covered by the first photoresist layer; exposing a portion of the substrate; transforming the first photoresist layer into a second photoresist layer, wherein the second photoresist layer does not cover at least a portion of the passivation layer; etching the passivation layer which is not covered by the second photoresist layer; exposing a portion of the drain electrode; depositing a conductive film on the drain electrode and on the second photoresist layer, the conductive film including a first portion disposed on the second photoresist layer and a second portion at least partially separated from the first portion by gaps, the gaps exposing at least a portion of lateral sides of the second photoresist layer; removing the second photoresist layer and the first portion of the conductive film; and forming a pixel electrode on the portion of the drain electrode.