Patent ID: 7274217

Claim:
A hybrid orientation technology digital CMOS circuit, comprising: a silicon substrate; first and second FETs, each of the FETs including a source region, a drain region and a gate region, the first FET including a silicon channel region connecting the source and drain regions of the first FET and in direct contact with the substrate, the second FET including a silicon channel region connecting the source and drain regions of the second FET, and wherein one of the FETs is a PFET and the other of the FETs is an NFET; an insulator region separating the second FET from the silicon substrate, wherein said second FET is a silicon-on-oxide layer; and a high-VTH thick oxide header PFET on the substrate and connected in series with the first and second FETs, said header PFET including a source, a drain a gate, and a silicon header channel region connecting the source and the drain of the PFET header to reduce the standby gate leakage of the PFET header.