Patent ID: 8916950

Claim:
A method of forming a semiconductor device, the method comprising: forming a pad oxide layer on a substrate; forming a pad nitride layer on the pad oxide layer; forming one or more trenches through the pad nitride layer, the pad oxide layer, and into the substrate; forming a liner oxide layer on the pad nitride layer, and on and adjacent to the one or more trenches; forming a first layer of high density plasma (HDP) oxide on and adjacent to the liner oxide layer; forming a nitride layer on and adjacent to the HDP oxide in at least one of the one or more trenches; removing a portion of the nitride layer, which forms one or more nitride plugs that remain on and adjacent to the HDP oxide in the at least one of the one or more trenches, wherein at least one of the one or more trenches contain at least two nitride plugs; forming a second layer of the HDP oxide on the one or more nitride plugs, wherein the one or more nitride plugs are encapsulated in the second layer of the HDP oxide; planarizing a portion of the second layer of the HDP oxide and a portion of the liner oxide layer, wherein the second layer of the HDP oxide, the liner oxide layer, and the one or more nitride plugs remain in the at least one of the one or more trenches; removing the pad nitride layer, the pad oxide layer, a portion of the liner oxide layer, and a portion of the HDP oxide thereby forming a shallow trench isolation structure is formed in the at least one of the one or more trenches; forming one or more gates on the substrate, wherein the one or more gates are spaced at a distance from each other; and forming a dielectric layer on and adjacent to the substrate, the one or more gates, and the shallow trench isolation structure.