Patent ID: 7787325

Claim:
A memory device, comprising: a plurality of memory cells arranged in a matrix of rows and columns, each memory cell adapted to store information, each memory cell includes an input signal path for selecting the memory cell, and each memory cell includes an input/output signal path for reading information from, or writing information to, the memory cell when selected; a plurality of wordline signal paths each coupled to the input signal path of the memory cells in a corresponding row of the matrix; a plurality of row decode drivers each associated with a corresponding row of the matrix, wherein each row decode driver includes an input coupled to a row address signal path, wherein each row decode driver includes an output coupled to the wordline signal path coupled to the corresponding row, wherein each row decode driver is adapted to activate its corresponding wordline signal path by applying a signal to its output in response to receipt of a row address applied to its input that identifies the corresponding row; and control logic adapted to apply a row address along the row address signal path to the plurality of row decode drivers to identify a row of the matrix to be selected by the wordline signal path activated by the row decode driver corresponding to the identified row, wherein each row decode driver includes a circuit design attribute that varies as a function of physical proximity of the row decode driver to the control logic, and wherein the variation of the circuit design attribute of a row decode driver is operable to reduce a leakage power of the row decode driver.