Patent ID: 7813170

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix; a first control circuit which controls the potentials of the word lines and bit lines; and a data storage circuit which is connected to the bit lines and stores write data for setting 2 k threshold voltages (k is a natural number) in memory cells in the memory cell array and which includes a k number of latch circuits each storing at least 1-bit data, wherein the data storage circuit includes a first latch circuit for storing 1-bit data and a second latch circuit to a k-th latch circuit which set the threshold voltages of the memory cells at a first threshold voltage and a second threshold to a 2 k -th threshold voltage by a write operation, the first latch circuit stores data for differentiating a 2 (k-1) -th threshold voltage or less or a (2 (k-1) +1)-th threshold voltage or more, the second latch circuit stores data for differentiating at least 2 (k-1) -th+2 (k-2) -th threshold voltage or less or a (2 (k-1)+ 2 (k-2) +1)-th threshold voltage or more, and the k-th latch circuit stores data for differentiating at least (2 k −1)-th threshold voltage or less or a 2 k -th threshold voltage or more.