Patent ID: 7054184

Claim:
A set associative SRAM cache memory circuit for generating an output signal indicating the state of an addressed memory cell in a memory cell set selected from a plurality of memory cell sets ( FIGS. 1 and 3 ) comprising in combination: a multiplexer with a set input (seta, setb, setc, setd) from each of said plurality of memory cell sets and a sense input (stoa, b, c, d or scoa, b, c, d) from a sense amplifier in each of said plurality of memory cell sets; said set input from each of said memory cell sets having a select state and said sense input from said sense amplifier in each of said memory sets having an active state and a standby state (seta-setd; sto/sco FIG. 4 ); a plurality of logic circuits, one for each of said memory cell sets, each of said logic circuits having one set input and one sense input (transistors with sto/sco inputs and transistors with set inputs FIG. 3 ) and each having its output coupled to a common node precharged high (c or t FIG. 3 ; node t/c FIG. 4 ); each of said plurality of logic circuits responsive to said set input in said select state occurring in conjunction with said sense input in said active state to pull down said common node from its precharged high state ( FIG. 4 ); a circuit to restore said common node to said precharged high state in response to a sense input from said sense amplifier in each of said memory cell sets in its standby state (P 126 , P 127 , P 115 , P 116 , P 41 , P 43 , P 44 , P 47 FIG. 3 ); and a circuit responsive to a state of said node for generating said output signal (N 7 -P 38 FIG. 3 ).