Patent ID: 7304521

Claim:
A digitally programmable delay circuit comprising a plurality of circuit stages connected in series with each other, a first circuit stage being coupled to a line carrying a signal having edges to be delayed, each circuit stage comprising a plurality of P-type transistors of connected in parallel with each other, and a plurality of N-type transistors connected in parallel with each other, and a selector circuit that is responsive to a delay control signal and selects one or more of the plurality of P-type transistors in each circuit stage to delay a rising edge of the signal and one or more of the plurality of N-type transistors in each circuit stage to delay a falling edge of the signal, an N-type transistor connected in parallel with the plurality of P-type transistors that discharges voltage across the plurality of P-type transistors during a low portion of the signal, and a P-type transistor connected in parallel with the plurality of N-type transistors that discharges voltage across the plurality of N-type transistors during a high portion of the signal, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented.