Patent ID: 8516321

Claim:
An integrated circuit comprising: A. test access port domains, each domain having a TDI input, a TDO output, a TCK input, and a TMS input; and B. an addressable test access port domain selection circuitry including i. linking circuitry having a separate set of domain leads coupled with each TAP domain, each set of domain leads including a TDI output connected to a TDI input, a TDO input connected to a TDO output, a TCK output connected to a TCK input, and a TMS output connected to a TMS input, the linking circuitry having a set of internal leads including a TDI internal lead, a TDO internal lead, and a TMS internal lead, and the linking circuitry having a control input; ii. interface circuitry including a TDI input buffer having an output connected to the TDI internal lead, a TDO buffer having an input connected to the TDO internal lead, and a TMS input buffer having an output connected to the TMS internal lead, the TDI input buffer, the TDO output buffer and the TMS input buffer being separate from one another; iii. address circuitry having an input connected to the TDI input buffer output, an address clock input, and an address match output; iv. instruction circuitry having an input connected to the TDI input buffer output, an instruction clock input, and a control output connected to the linking circuitry control input; and v. controller circuitry having a clock input, a TMS input connected to the TMS input buffer output, an instruction clock output connected to the instruction clock input, an address clock output connected to the address clock input, and an address match input connected to the address match output.