Patent ID: 7824983

Claim:
A method of isolating gates in a semiconductor structure, comprising: forming a plurality of first trenches through a plurality of materials overlying a substrate, the plurality of materials comprising a nitride material, an oxide pillar material, an etch stop material, and a polysilicon material; forming a spacer material on sidewalls of the plurality of the first trenches and overlying the nitride material, the oxide pillar material, the etch stop material, and the polysilicon material; extending the plurality of the first trenches at least partially into the substrate to form a plurality of isolation trenches, the spacer material remaining on the sidewalls of the plurality of the first trenches adjacent to the polysilicon material, the etch stop material, the oxide pillar material, and the nitride material; filling the plurality of isolation trenches with a fill material; removing the spacer material to form a gap adjacent to vertical edges of the polysilicon material, the etch stop material, the oxide pillar material, and the nitride material; enlarging the gap by removing the polysilicon material and the etch stop material and a portion of the oxide pillar material to form a plurality of second trenches and a plurality of oxide pillars; and extending the plurality of the second trenches into the substrate to form a plurality of recessed access device trenches.