Patent ID: 8329513

Claim:
A method of forming a memory array, comprising: forming a source line; forming a first string of serially-coupled memory cells on a first side of at least one conductive pillar and over the source line; forming a second string of serially-coupled memory cells on a second side of the at least one conductive pillar and over the source line; forming a data line over the first string of serially-coupled memory cells and the second string of serially-coupled memory cells; and forming a single select transistor so that the single select transistor selectively couples the first string of serially-coupled memory cells on the first side of at least one conductive pillar to the source line and so that the single select transistor also selectively couples the second string of serially-coupled memory cells on the second side of the at least one conductive pillar to the source line; wherein forming the first string of memory cells comprises forming at least a first control gate on the first side of the at least one conductive pillar and interposing at least a first charge trap between the first side of the at least one conductive pillar and the first control gate; wherein forming the second string of memory cells comprises forming at least a second control gate on the second side of the at least one conductive pillar and interposing at least a second charge trap between the second side of the at least one conductive pillar and the second control gate; and wherein the first and second charge traps are electrically isolated from each other and the first and second control gates are electrically isolated from each other.