Patent ID: 7936002

Claim:
A multiple-layered memory device, comprising: a first memory device layer comprising: a first substrate including a first memory cell region, the first memory cell region including a first well positioned in an upper region thereof and a second well positioned in the first well, the first substrate comprising a semiconducting material doped with impurity of a first type, the first well comprising a semiconducting material doped with impurity of a second type opposite the first type, and the second well comprising a semiconducting material doped with impurity of the first type, a first active region of the first substrate being defined by the second well; and multiple first cell strings arranged on the first substrate in the first active region; and a second memory device layer on the first memory device layer comprising: a second substrate including a second memory cell region, the second substrate including only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of the first type and second type, the single well defining a second active region in the second memory cell region of the second substrate; and multiple second cell strings arranged on the second substrate in the second active region.