Patent ID: 8648635

Claim:
An apparatus, comprising: a memory array; a read/write circuit coupled to the memory array and configured to read data from and write data to the memory array; a buffer coupled to the read/write circuit and configured to be clocked according to an output clock signal; and a clock generator circuit coupled to the buffer and configured to provide the output clock signal, the clock generator circuit comprising: a forward clock path configured to delay an input clock signal by an adjustable delay adjusted based at least in part on a feedback clock signal and further configured to provide the output clock signal; a duty cycle correction circuit configured to adjust a duty cycle of a clock signal of the forward clock path based at least in part on a duty cycle control signal; and a feedback clock path coupled to the forward clock path and configured to receive the output clock signal, the feedback clock path configured to provide a first feedback clock signal having a frequency lower than a frequency of the output clock signal and on which the adjustable delay of the forward clock path is based at least in part, and the feedback clock path further configured to provide a second feedback clock signal based at least in part on the output clock signal and having a same clock frequency as the output clock signal and configured to provide the duty cycle control signal to the duty cycle correction circuit, the duty cycle control signal based at least in part on the second feedback clock signal.