Patent ID: 7928441

Claim:
A method of fabricating a TFT array panel, comprising: depositing an aluminum layer having a first thickness directly on a substrate; depositing a top molybdenum layer on the aluminum layer, the top molybdenum layer having a second thickness about 20% to about 27% the first thickness; forming a wiring by patterning the aluminum layer and the top molybdenum layer and forming an insulating layer, a semiconductor layer, and an ohmic contact layer in sequence on the wiring, wherein the aluminum layer has a standard reduction potential of −1.76V, and the top molybdenum layer has a standard reduction potential of −0.2V and further wherein the aluminum layer has a taper shape, and wherein the forming an insulating layer, a semiconductor layer, and an ohmic contact layer in sequence further comprises forming at least one of the insulating layer, the semiconductor layer, and the ohmic contact layer using a plasma-enhanced chemical vapor deposition process.