Patent ID: 7153737

Claim:
A DRAM cell comprising: a deep trench extending into a surface of a substrate; a cell capacitor formed at a bottom portion of the deep trench; a collar disposed in the deep trench above the cell capacitor; a node conductor disposed in the trench extending from the cell capacitor, through the collar towards the surface of the substrate; an oxide formed at an upper portion of the trench atop the node conductor; a first gate electrode disposed atop the oxide; a second gate electrode disposed on the surface of the substrate on a one side of the deep trench; sidewall spacers disposed on sides of the first and second gate electrodes; a gap between the sidewall spacers of the first and second gate electrodes wherein the surface of the substrate is exposed in the gap; and a diffusion region extending from a top portion of the deep trench to the second gate electrode; wherein: the oxide extends beyond the trench towards the second gate electrode, within the surface of the substrate, spanning the gap between one of the spacers of the first gate electrode and one of the spacers of the second gate electrode; and silicide structures formed on exposed surfaces of the gate electrodes, as well as on exposed areas of the substrate whereat the exposed areas of the substrate comprise silicon.