Patent ID: 7687392

Claim:
A method for fabricating a semiconductor device, comprising: forming a first metal wiring in a semiconductor substrate; forming an inter-metal dielectric (IMD) layer on the semiconductor substrate having the first metal wiring formed therein, the IMD layer including a first IMD layer and a second IMD layer; forming a via hole in the IMD layer to expose the first metal wiring; forming an ion barrier layer on the semiconductor substrate having the IMD layer formed thereon, in which the via hole has been formed; performing a break through (BT) process to the ion barrier layer, such that the ion barrier layer remains only on sidewalls of the via hole; forming a diffusion barrier layer on the semiconductor substrate, on which the ion barrier layer has been formed and the BT process has been performed; forming a metal layer on the semiconductor substrate, on which the diffusion barrier layer has been formed; polishing the top surface of the semiconductor substrate until the IMD layer is exposed, such that the metal layer only remains in the via hole; and forming a second metal wiring on the semiconductor substrate, the second metal wiring contacting the metal layer remained in the via hole.