Patent ID: 8563980

Claim:
An array substrate, comprising: a base substrate, a data line and a gate line crossed with each other on the base substrate so as to define a pixel unit, and a pixel electrode and a thin film transistor (TFT) arranged in the pixel unit, wherein the TFT comprises a gate electrode, an active layer, a source electrode and a drain electrode, the data line and the gate line are formed in the same layer, and the data line is discontinuously disposed so as to be separated from the gate line or the gate line is discontinuously disposed so as to be separated from the data line; bridge via holes and a source electrode via hole are formed in a gate insulating layer covering the data line, the gate line and the gate electrode, and the bridge via holes are located at positions respectively corresponding to adjacent discontinuous sections of the data line or adjacent discontinuous sections of the gate line, and the source electrode via hole corresponds to the data line; and the source electrode, the drain electrode, the pixel electrode and the bridge line are formed in the same layer, and the drain electrode and the pixel electrode are formed integrally, and the source electrode is connected with the data line through the source electrode via hole and the bridge line connects the adjacent discontinuous sections of the data line or the adjacent discontinuous sections of the gate line through the bridge via holes.