Patent ID: 7138843

Claim:
A timer circuit comprising: a current mirror receiving a reference current as an input current, the current mirror providing a first output current on a first output node and a second output current on a second output node, the second output current being N times the first output current; a capacitor coupled between the first output node and a first power supply voltage, the capacitor receiving the first output current when being charged; a first switch coupled between the first output node and the first power supply voltage, the first switch being controlled by a first control signal to be in a first position for discharging the capacitor to the first power supply voltage and in a second position to allow the capacitor to be charged by the first output current; a resistor coupled between the second output node and the first power supply voltage, the resistor being biased by the second output current to develop a reference voltage across the resistor; and a comparator having a first input terminal coupled to the first output node and a second input terminal coupled to the second output node, the comparator providing an output signal having a first state when the voltage across the capacitor at the first output node is less than the reference voltage and providing an output signal having a second state when the voltage across the capacitor is equal to or greater than the reference voltage; a reference voltage circuit for generating a second reference voltage; and a second switch coupled to the second input terminal of the comparator and being controlled by a second control signal, the second switch being in a first position for connecting the reference voltage across the resistor to the second input terminal of the comparator and being in a second position for connecting the second reference voltage from the reference voltage circuit to the second input terminal of the comparator, wherein the comparator receives either the reference voltage or the second reference voltage as a comparison reference voltage, the comparator providing an output signal having a first state when the voltage across the capacitor at the first output node is less than the comparison reference voltage and providing an output signal having a second state when the voltage across the capacitor is equal to or greater than the comparison reference voltage.