Patent ID: 8841765

Claim:
A microelectronic assembly, comprising: an interconnection substrate having a first surface, a second surface remote from the first surface in a vertical direction, conductive structure thereon, and terminals exposed at the second surface for connection with a component; at least two logic chips overlying the first surface of the substrate, each logic chip having a plurality of signal contacts at a front surface thereof confronting the first surface of the interconnection substrate, the signal contacts of each logic chip being directly electrically connected to the signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips, the signals representing at least one of data or instructions, the logic chips being adapted to simultaneously execute a set of instructions of a given thread of a process, and each logic chip having a rear surface opposite the front surface; and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting the rear surface of each of the at least two logic chips, the contacts of the memory chip being directly electrically connected to the signal contacts of at least one of the at least two logic chips through the conductive structure of the substrate.