Patent ID: 8233311

Claim:
A variable resistance nonvolatile storage device comprising: a semiconductor substrate; a nonvolatile storage element including a first electrode, a second electrode, and a variable resistance layer in which a resistance value reversibly varies based on electrical signals each having a different polarity, said variable resistance layer being interposed between said first and second electrodes and provided in contact with said first and second electrodes, and the electrical signals being applied between said first and second electrodes; and a MOS transistor formed on a main surface of said semiconductor substrate; wherein said first electrode is arranged as a lower electrode that is closer than said second electrode to the main surface of said semiconductor substrate; wherein said second electrode is arranged as an upper electrode that is farther than said first electrode from the main surface of said semiconductor substrate; and in a memory cell, said MOS transistor has (i) a gate connected to a word line, (ii) one of a drain and a source electrically connected to said lower electrode, and (iii) the other of the drain and the source connected to a source line, the source line is formed of wiring layers that are arranged in parallel and are connected through one or more vias to each other, said nonvolatile storage element is arranged farther from the main surface of said semiconductor substrate than any of the wiring layers, and a bit line is arranged on a side farther from the main surface of said semiconductor substrate with respect to said nonvolatile storage element, and is connected to said upper electrode of said nonvolatile storage element.