Patent ID: 7830172

Claim:
An integrated circuit (IC), comprising: an array of programmable resources and interconnect resources, wherein at least one memory of the IC is initialized with instructions, and a portion of the programmable resources and interconnect resources is configured to implement an access interface, multiplexer logic, and a user design including a plurality of user registers; and a processor coupled to the programmable resources and interconnect resources, the processor adapted to execute the instructions from the at least one memory, causing the processor to perform operations including: receiving an access command that includes an identifier of one of the user registers from an external user interface via the access interface; in response to the access command being a read command, reading a read value from the one of the user registers and transmitting the read value to the external user interface via the access interface; and in response to the access command being a write command, writing a write value that is included in the access command to the one of the user registers via the multiplexer logic, wherein the processor and the user design are both coupled to write to the user registers via the multiplexer logic; wherein the portion of the programmable resources and interconnect resources of the array is configured to implement the access interface as a serial interface; the receiving of the access command includes loading each of a plurality of bits of the access command from a 1-bit receiver of the serial interface; and the transmitting of the read value includes storing each of at least one bit of the read value in a 1-bit transmitter of the serial interface.