Patent ID: 8898356

Claim:
A combined power and input/output system, comprising: a host system; a target system operably coupled to the host system via a combined power and I/O line; wherein the host system is configured to charge a power supply capacitor in the target system in a first mode via the combined power and I/O line and communicate via the combined power and I/O line in a second mode, wherein the target system comprises a pass transistor interposed between the host system and the power supply capacitor on the combined power and I/O line, a switching system operable in cooperation with the pass transistor to charge and discharge the power supply capacitor during communication in the second mode, wherein during an input phase of the second mode in which data is transmitted from the host to the target system, the pass transistor is asserted for a predetermined period after a rising edge of a data bit and wherein during an output phase of the second mode in which data is transmitted from the target system to the host system, the pass transistor is asserted for an entirety of a high portion of a data bit.