Patent ID: 7586927

Claim:
An arbiter, comprising: a plurality of comparators each receiving a first enable input, a first priority input, a second enable input and a second priority input, the comparators comparing the first priority input with the second priority input and outputting one of the first priority input and second priority input as priority outputs according to the comparison and the first and second enable inputs; the comparators generating output flags that indicate whether the first priority input and the second priority input were selected as the priority output; the comparators arranged in multiple comparator stages each including one or more of the comparators, each subsequent comparator stage using the output flags from the preceding comparator stage at the first and second enable input and using the priority outputs from the preceding comparator stages as the first and second priority input; and a win register, coupled through logic circuitry to the output flags of the comparators in the comparator stages, that identifies winning priority inputs.