Patent ID: 7598786

Claim:
A duty cycle correction circuit, comprising a frequency divider receiving a first clock signal and dividing frequency of the first clock signal to generate a second clock signal; a duty cycle detector receiving the second clock signal and a correction clock signal and generating a control signal according to the second clock signal and the correction clock signal, wherein the duty cycle detector comprises: a first fixed current source generating a first current; a second fixed current source generating a second current, wherein the second current is double the first current; a first switch coupled to the first fixed current source and turned on or off according to the second clock signal; a second switch coupled to the second fixed current source and turned on or off according to the correction clock signal; a third switch coupled between the first switch and a ground and turned on or off according to an inverting correction clock signal; a fourth switch coupled between the second switch and the ground and turned on or off according to the inverting correction clock signal; and a comparator receiving the first current and the second current, respectively converting the first current and the second current to a first voltage and a second voltage, and comparing the first voltage and the second voltage to generate an output signal through a fifth switch to charge a capacitor to generate the control signal; and a delay circuit receiving the first clock signal and the control signal and adjusting a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.