Patent ID: 8106685

Claim:
A signal receiver, comprising: a first input signal terminal, for receiving a reference voltage; a second input signal terminal; a first transistor, including a gate electrode coupled to the first input signal terminal and a first electrode and a second electrode; a second transistor, including a gate electrode coupled to the second input signal terminal and a first electrode and a second electrode; a first variable load, coupled in cascode to the first electrode of the first transistor and having an adjustable resistance to keep a DC level at an output node of the signal receiver a constant value; and a control signal generator, for generating a first control signal by directly comparing a voltage level of the reference voltage with a predetermined voltage level, and utilizing the first control signal to adjust the resistance of the first variable load; wherein the first transistor is an N-type metal-oxide semiconductor (NMOS) transistor, and the control signal generator utilizes the first control signal to increase the resistance of the first variable load when the voltage level of the reference voltage is decreased, and to decrease the resistance of the first variable load when the voltage level of the reference voltage is increased.