Patent ID: 8171259

Claim:
A dynamic reconfigurable circuit that includes a plurality of clusters each including at least one sequencer and a group of reconfigurable processing elements and that is capable of dynamically changing a configuration of the plurality of clusters according to a context including a description of processing of the processing elements and of connection between the processing elements, wherein a first cluster among the clusters comprises: a signal generating circuit that, when an instruction to change the context is received by the sequencer, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster after the instruction to change the context is received by the sequencer; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.