Patent ID: 8044712

Claim:
An apparatus comprising: a resistive element; a capacitive array having a first terminal and an second terminal, wherein the resistive element is coupled to the first terminal of the capacitive array, and wherein the capacitive array includes: a first set of binarily weighted capacitive elements, wherein each capacitive element from the first set of capacitive elements is coupled to the first terminal of the capacitive array; a first set of switches, wherein each switch from the first set of switches is associated with at least one of the capacitive elements from the first set of capacitive elements, and wherein each switch is coupled between its capacitive element and the second terminal of the capacitive array, and wherein the first set of switches is controlled by a first binary control word having N bits; a second set of binarily weighted capacitive elements, wherein each capacitive element from the second set of capacitive elements is coupled to the first terminal of the capacitive array; and a second set of switches, wherein each switch from the second set of switches is associated with at least one of the capacitive elements from the second set of capacitive elements, and wherein each switch is coupled between its capacitive element and the second terminal of the capacitive array, and wherein the second set of switches is controlled by a second control word having N−1 bits; and logic circuitry having a plurality of AND-gates that are arranged to receive the first binary control word and to generate the second binary control word from the first binary control word, wherein the plurality of AND-gates includes a set of N−1 AND-gates that are each associated with at least one of the switches from the second set of switches and that each receive the Nth bit from the first binary control word.