Patent ID: 8546952

Claim:
A three-dimensional (3D) integrated circuit, comprising: a first wafer comprising a first conductive pattern; and a second wafer comprising a second conductive pattern, and electrically connected to the first conductive pattern, wherein a displacement between the first wafer and the second wafer is determined according to a resistance of the first conductive pattern and the second conductive pattern, wherein the first conductive pattern comprises: a plurality of directional conductive patterns, wherein at least one of the directional conductive patterns is electrically connected to the second conductive pattern; and a first central conductive pattern disposed among the directional conductive patterns, and electrically connected to the second conductive pattern; wherein displacements of the first wafer and the second wafer in different directions are determined according to resistances of the first central conductive pattern, the corresponding directional conductive pattern and the second conductive pattern.