Patent ID: 7235451

Claim:
A method of fabricating a drain-extended MOS transistor in a semiconductor device, comprising: forming a gate structure over a semiconductor body, the gate structure having first and second opposite ends; providing first dopants to a floating region in the semiconductor body proximate the first end of the gate structure, the floating region being self-aligned with the first end of the gate structure; providing second dopants to first and second source/drains of the semiconductor body, the first source/drain being laterally spaced from the first end of the gate structure, the second source/drain being proximate to or spaced from the second end of the gate structure, wherein one of the first and second dopants are p-type and the other of the first and second dopants are n-type; and providing first dopants to a resurf region extending between the floating region and the first source/drain in the semiconductor body, wherein providing first dopants to the floating region comprises performing a first implantation process to implant p-type dopants into the floating region using a first implantation dose of about 2E12 cm −2 or more and wherein the first dopants are p-type and the second dopants are n-type; wherein providing first dopants to the resurf region comprises performing the first implantation process to implant p-type dopants into the floating region and the resurf region using the first implantation dose, further comprising performing a second implantation process to implant n-type dopants into the resurf region using a second implantation dose, the second implantation dose being less than the first implantation dose.