Patent ID: 8228105

Claim:
A method comprising: generating by a correction circuit two or more clock signals having a clock frequency, each of the clock signals having a respective clock phase and a respective clock duty cycle; sequentially selecting by a selector circuit each one of the clock signals; and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle, the adjustment of the respective clock duty cycle of the selected one of the clock signals comprising: generating by a detection circuit a control signal based on the respective clock duty cycle of the selected one of the clock signals; generating by a feedback control circuit a duty-cycle-distortion (DCD) correction signal based on the control signal; adjusting by the correction circuit the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal; and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.