Patent ID: 6967523

Claim:
A charge pump power supply for a DRAM, comprising a charge pump circuit comprising a first and a second pump cascade coupled in parallel to an output node, each pump cascade having a plurality of pump stages coupled in series, the output node receiving charge pumped by the first and the second pump cascades and providing an output supply voltage that is greater in magnitude than a power supply voltage; each pump stage having a FET configured as a diode and a FET configured as a capacitor, the FETs of a first pump stage of each pump cascade having a first oxide thickness and the FETs of a last pump stage of each pump cascade having a second oxide thickness, the second oxide thickness being greater than the first oxide thickness; each (2n)th pump stage of the first pump cascade is coupled to a first non-overlapping clock signal and each (2n)th pump stage of the first pump cascade is coupled to a non-overlapping second clock signal, n being an integer greater than or equal to zero: each (2n)th pump stage of the second pump cascade is coupled to the second non-overlapping clock signal and each (2n+1)th pump stage of the second pump cascade is coupled to the first non-overlapping clock signal, n being an integer greater than or equal to zero; and a non-overlapping clock signal generator for supplying the first and second non-overlapping clock signals, comprising a system clock input node; a clock input stage; a latch coupled to the clock input stage having intermediate latch outputs and complementary latch outputs; clock output driving stages coupled to the complementary latch outputs and having non-overlapping clock signal outputs; and an equalization stage coupled between the clock output driving stages and receiving as inputs the intermediate latch outputs.