Patent ID: 7247556

Claim:
A method of fabricating an integrated circuit, comprising forming on a wafer an interconnect structure having more than one interconnect levels, wherein forming each interconnect level comprises forming a dielectric layer, forming a conducting layer over said dielectric layer, and forming a service layer over said conducting layer, wherein: each service layer has one or more sub-layers and comprises silicon oxynitride; at least two of said sub-layers in the interconnect structure have at least one of different compositions and different lattice mismatches with the corresponding one or more conducting layers; the at least one of the different compositions and the different lattice mismatches with the corresponding one or more conducting layers result in different intrinsic stresses in the at least two sub-layers; the at least two sub-layers belong to service layers corresponding to different interconnect levels; for each interconnect level, the method comprises the steps of: (a) depositing the dielectric layer over the wafer; (b) depositing the conducting layer over the dielectric layer; (c) depositing the service layer over the conducting layer; (d) depositing a photo-resist layer over the service layer; (e) exposing the photo-resist layer to irradiation through a lithographic mask to imprint a desired pattern; (f) removing portions of the photo-resist layer to develop the imprinted pattern; (g) removing portions of the conducting and service layers to transfer the developed pattern onto said conducting and service layers; and (h) removing remaining portions of the photo-resist layer; for each instance of step (e), the respective service layer serves as an anti-reflective coating; and the method further comprises: selecting a bow value; and forming the interconnect structure such that the different intrinsic stresses in the at least two sub-layers cause bow of the wafer to be below said selected bow value.