Patent ID: 7494861

Claim:
A method for manufacturing a MOSFET device, comprising: forming a ground plane of a monocrystalline Si based material, and selecting dopant impurities in said ground plane to be of a first type with a concentration of between about 1×10 18 /cm 3 and 1×10 20 /cm 3 ; depositing by selective epitaxy a body layer of between about 2 nm and 7 nm thickness over said ground plane, whereby creating an interface between said ground plane and said body layer, in-situ doping said body layer with impurities of a second type to a concentration of between about 5×10 18 /cm 3 and 5×10 19 /cm 3 , and keeping a region of transition between said first type and said second type of dopant impurities to a width across said interface of between about 2.5 nm and 0.5 nm, wherein said depositing of said body layer is carried out by a process of ultra-high-vacuum-chemical-vapor-deposition (UHV-CVD), in a temperature range of between about 500° C. and 650° C.; disposing a gate insulator layer over said body layer; disposing a gate over said gate insulator layer, wherein said gate comprises a mid-gap workfunction metal which is in direct contact with said gate insulator layer, and patterning said gate to a length of less than about 40 nm; and forming a source and a drain, selecting dopant impurities in said source and said drain to be of said second type with a concentration of between about 5×10 19 /cm 3 and 2×10 20 /cm 3 , and keeping the junction depths of said source and said drain to less than about 7 nm.