Patent ID: 7506226

Claim:
A data path circuit, comprising: an input logic circuit receiving input data, the input logic circuit being structured to generate input test data having a value corresponding to a value of a subset of bits of the input data; a first selector coupled to receive the input data and the input test data, the first selector being structured to select the input data in a normal operating mode and the test data in a test mode; an ECC encoder receiving the selected data from the first selector and being operable to generate ECC check bits having a value corresponding to the value of the selected data, the ECC encoder outputting the selected data and the ECC check bits as data path output data, the ECC encoder being structured to generate the ECC check bits so that the ECC check bits have a pattern corresponding to the value of the selected data; an ECC decoder receiving data path input data containing data and ECC check bits, the ECC decoder being structured to check and correct the received data based on the received ECC check bits and to output corrected data; and an output logic circuit receiving the data path input data, the output logic circuit being structured to determine if bits of the data path input data have a pattern that corresponds to the value of the subset of bits of the input data and to generate test results data indicative of whether the data path input data has a pattern that corresponds to the value of the subset of bits of the input data; and a second selector coupled to receive the corrected data and the test results data, the second selector being structured to select the corrected data in the normal operating mode and the test results data in the test mode, the second selector outputting the selected data from the data path circuit.