Patent ID: 7177176

Claim:
An apparatus, comprising: a static random access memory (SRAM) cell having a first p-channel metal oxide semiconductor (PMOS) device and a second p-channel metal oxide semiconductor (PMOS) device, the first and the second p-channel metal oxide semiconductor (PMOS) devices being operated at a first current level in a read mode of the static random access memory (SRAM) cell and being operated at a second lower current level in a write mode of the static random access memory (SRAM) cell; and a first and a second n-channel metal oxide semiconductor (NMOS) devices corresponding to the first and the second p-channel metal oxide semiconductor (PMOS) devices, wherein the first and the second p-channel metal oxide semiconductor (PMOS) devices are forward body biased in the read mode and sources of the n-channel metal oxide semiconductor (NMOS) devices are coupled to ground via a first control device and a second control device, respectively, wherein the first and the second p-channel metal oxide semiconductor (PMOS) devices are reverse body biased in the write mode or sources of the n-channel metal oxide semiconductor (NMOS) devices are coupled to a virtual ground via the first and the second control devices.