Patent ID: 7139968

Claim:
A digital signal processor, comprising: an arithmetic logic unit configured to perform register—register arithmetic logic operations; a plurality of registers configured to store data, wherein the arithmetic logic unit is used to compare a first data with a second data and to output one of the first data and the second data based on a result of the comparison of the first data and the second data, in parallel with a comparison of a third data with a fourth data and an output of one of the third data and the fourth data based on a result of the comparison of the third data and the fourth data, wherein the output one of the first data and the second data is provided as a first part of a processing data and the output one of the third data and the fourth data is provided as a second part of the processing data lower than the first part, and wherein at least one of the plurality of registers stores the result of the comparison of the first data and the second data and the result of the comparison of the third data and the fourth data.