Patent ID: 7251304

Claim:
A bit synchronizing circuit that synchronizes serial data by a clock signal when transmitting bit data, comprising: a phase comparison clock generation unit for generating a plurality of clock signals based on a predetermined reference clock signal, each of the clock signals having a unique phase different from other clock signals, a plurality of edge detection units, each unit being for generating an edge signal that indicates an edge position of the serial data, wherein each of the detection units is supplied with a group of the clock signals, the group of the clock signals consisting of every predetermined number of the clock signals generated by the phase comparison clock generation unit, a clock judging unit for generating a synchronous timing signal based on the edge signal generated by each of the edge detection units, and a clock selection unit for selecting a clock signal for writing that is suitable for a clock signal for synchronizing the serial data, the selection being made from the clock signals, each of which is in a different phase, based on the synchronous timing signal generated by the clock judging unit, wherein, when the clock selection unit detects an abnormality in any one of the edge signals generated by the edge detection units, said selected clock signal for writing is re-selected, instead of the synchronous timing signal generated by the clock judging unit relative to the abnormal edge signal.