Patent ID: 8094504

Claim:
A buffered DRAM, comprising: a first DRAM memory cell; a buffer coupled to the first DRAM memory cell and further coupled to receive and transmit data lines and strobe signals, the buffer further coupled to receive and transmit address and command signals, and wherein if data access is directed to a DRAM coupled to the buffered DRAM, the buffer couples the data and strobe signals out of the buffered DRAM for access by the DRAM coupled to the buffered DRAM and if data access is directed to the buffered DRAM the buffer couples the data and strobe signals for access by the first DRAM memory cell; further wherein the first DRAM memory cell and the buffer comprise a single DRAM circuit; further wherein only the buffered DRAM is coupled to data lines connected to a dual in line memory module (DIMM) connector.