Patent ID: 7505305

Claim:
A semiconductor device comprising a memory array, said memory array including a plurality of magnetic memory cells arranged in a first direction and a second direction that is different from said first direction to form a matrix, a plurality of word lines each arranged to extend along said first direction of said plurality of magnetic memory cells arranged to form the matrix, and a plurality of bit lines each formed in a first wiring layer and arranged to extend along said second direction, and transmitting a data read current in a data read operation; wherein each of said plurality of magnetic memory cells includes a magnetic resistive element having a resistance value that varies according to a level of storage data, and a memory cell selection transistor connected between one of said plurality of bit lines and one end of said magnetic resistive element, and having a gate connected to one of said plurality of word lines, wherein the other end of said magnetic resistive element is connected to a second wiring layer fixed to a constant voltage, and said second wiring layer is formed in a layer above said first wiring layer.