Patent ID: 8264897

Claim:
A static random access memory comprising: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit connected with said pair of bit lines and configured to precharge said pair of bit lines with a precharge voltage; and a voltage reducing circuit connected between said precharge circuit and said first power supply, wherein said voltage reducing circuit comprises: a control circuit comprising a differential amplifier circuit which is configured to amplify a difference input of a reference voltage generated through resistance division of said power supply voltage and said precharge voltage supplied to a node to output a control signal; and a voltage reduction control transistor connected between said node and said first power supply and configured to generate said precharge voltage in response to said control signal, and wherein said precharge circuit comprises: precharge transistors connected between said bit lines and said node and configured to control supply of the precharge voltage to said bit lines in response to a first precharge control signal.