Patent ID: 8853791

Claim:
A memory cell comprising: a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region formed in a substrate, wherein each of the diffusion regions extends along a vertical direction in a layout view of the cell, and wherein the diffusion regions are at a substrate level, and wherein the diffusion regions are separated from each other by isolation regions at the substrate level; a first gate electrode structure disposed within a gate electrode level, the first gate electrode structure comprising a gate electrode overlying a gate dielectric layer, the gate electrode level being over the substrate level and having a height defined by a cross-sectional thickness of the gate electrode and the gate dielectric layer, wherein the first gate electrode structure extends from a first source/drain region of the second diffusion region toward the third diffusion region in an oblique direction, turns to a horizontal direction, extends over and crosses the third diffusion region in the horizontal direction, and extends over and crosses the fourth diffusion region in the horizontal direction, wherein the first gate electrode structure turns to the horizontal direction before overlapping with the third diffusion region, wherein the horizontal direction is substantially orthogonal to the vertical direction, and wherein the oblique direction is at an oblique angle relative to the horizontal direction and having a positive slope with respect to the horizontal direction; and a first contact structure being at least partially located at a contact level, the contact level being above the gate electrode level and the substrate level.