Patent ID: 8524547

Claim:
A method of manufacturing a fin-type field effect transistor, said method comprising: etching a semiconductor layer to form, on a top surface of an insulator layer, source region, a drain region parallel to said source region, and a semiconductor fin that extends laterally from said source region to said drain region; forming a gate conductor adjacent said semiconductor fin between said source region and said drain region; and adjusting dimensions of said semiconductor fin between said gate conductor and said source region and between said gate conductor and said drain region in order to optimize resistance so that said transistor is operable at a predetermined maximum voltage, said adjusting of said dimensions being performed by design such that said fin-type field effect transistor is asymmetric and such that a first resistance of a first portion of said semiconductor fin between said source region and said gate conductor is less than a second resistance of a second portion of said semiconductor fin between said gate conductor and said drain region.