Patent ID: 7411277

Claim:
A semiconductor integrated circuit comprising: a plurality of regions with a wiring pattern provided in a wiring layer above a semiconductor substrate; a target region to be shielded provided in the wiring layer; an external connection terminal provided near a boundary of the target region, and for transmitting and receiving a signal between the target region and other regions than the target region; and a shield wiring which is arranged on an entire boundary of the target region while avoiding the external connection terminal or a wiring which is electrically connected to the external connection terminal from the other region, wherein the shield wiring is electrically connected through a contact section to a terminal of the target region to be shielded, which terminal is provided on a layer different from a layer on which the shield wiring is provided and to which terminal a fixed potential is applied, or to a wiring connected to the terminal of the target region to be shielded; and wherein the shield wiring is free of openings from conductive elements contacting the target region; and said shield wiring having a laminated structure and being comprised of a plurality of wiring layers with an insulating layer between each of the wiring layers and contact sections connecting the wiring layers to each other.