Patent ID: 7592248

Claim:
A method comprising: forming a conducting via at a first level of a workpiece, wherein the workpiece is an electronic semiconductor device workpiece; forming a first layer comprising a plurality of dielectric nanotubes at the first level using a composite catalyst, wherein the composite catalyst comprises a material having a plurality of composite portions including a catalyst and a dielectric material, and at least a majority of the dielectric nanotubes are upright dielectric nanotubes; forming at the first level a first dielectric layer of a first dielectric material, wherein the first dielectric layer is formed prior to formation of the plurality of dielectric nanotubes; and forming at the first level a second dielectric layer of a second dielectric material, wherein the second dielectric layer is formed prior to formation of the plurality of dielectric nanotubes, and the second dielectric layer is at least partially removed prior to forming the plurality of dielectric nanotubes, and the first dielectric layer remains after at least partially removing the second dielectric layer.