Patent ID: 8013442

Claim:
A semiconductor device comprising: a pad electrode formed on a semiconductor substrate; an insulating layer formed on the semiconductor substrate so as to cover the pad electrode and having a plurality of openings over the pad electrode; a metal layer formed on the insulating layer so as to be connected to the pad electrode through the openings, the metal layer not filling the openings fully so as to form a concave portion at each of the openings; a plating metal layer formed on the metal layer so that a portion of the plating metal layer disposed in each of the concave portions becomes thinner than other portions of the plating metal layer; and an electrode formed on the plating metal layer so that part of the electrode and part of the metal layer are alloyed through the thinner portion of the plating metal layer, wherein the plating metal layer comprises chromium, the plating metal layer has an area without crystal grains in the thinner portion, and a chromium alloy is formed in the area without crystal grains.