Patent ID: 7979811

Claim:
A computer-implemented method of performing resolution enhancement of a layout for an integrated circuit, the method comprising the steps of: receiving a first intermediate resolution enhancement state layout including a plurality of first fragments and a plurality of first biases associated with the first fragments, receiving a second intermediate resolution enhancement state layout including a plurality of second fragments and a plurality of second biases associated with the second fragments; assembling the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout; and by a computer, reconverging the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout by adjusting resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement to generate a third intermediate resolution enhancement state layout; wherein the step of reconverging comprises determining an interacting neighborhood in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout, and adjusting the resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout only within the interacting neighborhood; wherein the first intermediate resolution enhancement state layout includes an area of modification to the integrated circuit and the step of determining an interacting neighborhood comprises determining an area in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout within a halo radius from a center of the area of modification.