Patent ID: 7126841

Claim:
A non-volatile RAM memory array comprising: a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, whereby the select line and the data line are perpendicular to each other, and having a single transistor that controls current flow through the memory cell depending on a voltage applied to the select line; a memory element including a perovskite that changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the memory element; changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the memory element, the second voltage pulse across the memory element being of opposite polarity to the first voltage pulse; and maintains the resistive state even if power ceases to be supplied to the memory cell; wherein the resistive state of the memory cell determines the information stored in the memory cell.