Patent ID: 8139411

Claim:
An integrated circuit comprising one or more columns of memory cells, each column comprising: one or more memory cells, each memory cell comprising: a set of floating-gate transistors, each floating-gate transistor comprising a first source connected to a first signal line for receiving a first signal to enable a read operation of each memory cell, a first drain, a first well electrode connected to a second signal line for receiving a second signal applying a voltage to a well region in each of the floating-gate transistor, and a floating gate separated from the first drain and the first source by a gate oxide; and a set of cell readout transistors, each cell readout transistor comprising a second source connected to the first drain of one of the floating-gate transistors, a second drain, a second well electrode connected to the second signal line, a first non-floating gate connected to a third signal line for receiving a third signal, the third signal in combination with the first and the second signals controlling an operation mode of the memory cell; and a set of column readout transistors, each column readout transistor comprising a first node connected to the second drain of one of the cell readout transistors, a second non-floating gate connected to a fourth signal line for receiving an inverted version of the third signal, and a second node connected to a data line for reading out data stored in the memory cell.