Patent ID: 6967536

Claim:
A phase-locked loop circuit comprising: a DLL circuit having phase difference detecting unit for detecting a phase difference between a reference clock signal and a synchronous clock signal to be supplied to an electronic circuit which operates in synchronization with said synchronous clock signal, and a phase difference changing unit for increasing the phase difference between the reference clock signal and the synchronous clock signal as compared to the detected phase difference, if a phase difference between the reference clock signal and the synchronous clock signal is detected by said phase difference detecting unit, wherein said phase difference changing unit outputs a reference clock delay signal and a synchronous clock delay signal having a phase difference equal to the sum of the detected phase difference and a predetermined phase difference; and an analog PLL circuit being supplied with said reference clock delay signal and said synchronous clock delay signal from said phase difference changing unit, controlling the phase of an output control signal to synchronize said synchronous clock delay signal with said reference clock delay signal, and supplying the output control signal as said synchronous clock signal to said electronic circuit.