Patent ID: 7869284

Claim:
An erasing method for a nonvolatile memory, wherein the nonvolatile memory is a flash type nonvolatile memory including a body, a gate, a source, a drain, a storage layer formed between the gate and the body, and a heavy doped body contact, the method comprising the steps of: (a) providing a first voltage to the gate; (b) providing a second voltage to the source; (c) providing a third voltage to the drain; and (d) providing a fourth voltage to the body contact, wherein a forward bias between the drain/source region and the body contact is used to erase the nonvolatile memory, and with N-channel, the first voltage is a negative voltage, the second and the third voltage are grounded, and the fourth voltage is a positive voltage, the forward bias between the source/drain region and the body contact injects majority carriers into the body, and the electric field between the body and the gate accelerates and energizes the majority carriers to overcome an oxide barrier and to reach the storage layer to finish erasing.