Patent ID: 8065493

Claim:
A memory controller for coupling a memory to a network having a network interface, wherein the network interface comprises network interface buffers for implementing a flow control across the network, and wherein the memory comprises a Dynamic Random Access Memory (DRAM) for being accessed in bursts via pre-fetch buffers and write-back buffers, the memory controller comprising: a buffer managing unit for managing a buffering of data for the exchange of data between the network and the memory in bursts, the buffer managing unit further comprising: a data control unit for monitoring the network interface buffers to determine whether sufficient data are present in the network interface buffers such that a burst of data can be written to the memory; and a space control unit for monitoring whether sufficient space is available in the network interface buffers such that a burst of data from the memory can be buffered in the network interface buffers, wherein the data control unit and the space control unit control an access to and from the memory according to the data and the space in the network interface buffers and the pre-fetch buffers and the write-back buffers are entirely implemented in the network interface buffers.