Patent ID: 7229915

Claim:
A method for manufacturing a semiconductor device having a multi-layer wiring structure, comprising: forming a first insulating film on a lower-layer wiring that is on a semiconductor substrate; forming a second insulating film having a large etching selection ratio relative to said first insulating film, and having a relative dielectric constant not exceeding 3.0, on said first insulating film; forming a third insulating film as a cap film on said second insulating film; forming a first resist film having a predetermined pattern on said third insulating film; dry etching said third insulating film and said second insulating film, using said first resist film as a mask, to form an opening extending to said first insulating film; removing said first resist film by ashing using at least one of hydrogen and an inert gas; dry etching said first insulating film, using said third insulating film as a mask, to form a wiring trench extending to said lower-layer wiring; forming a copper layer filling said wiring trench; and planarizing by chemical mechanical polishing (CMP), leaving said copper layer only in said wiring trench, to form a trench wiring electrically connected to said lower wiring, wherein dry etching of said third and second insulating films and dry etching of said first insulating film use a fluorine-containing gas at a pressure of 0.1 Pa to 4 Pa.