Patent ID: 8413013

Claim:
A memory system comprising: a memory device; an error detecting and correcting system installed in the memory device so as to generate a warning signal in case there are uncorrectable errors in the memory device; an address generating circuit configured to generate internal addresses in place of bad area addresses in accordance with the warning signal, progressing of the internal addresses being selected in such a manner as to avoid address collision with the address progressing of the memory device at least at the beginning of it; and a content addressable memory configured to store the internal addresses as substitutive area addresses, the content addressable memory being referred to at an access time of the memory device so as to generate the substitutive area addresses in place of the bad area addresses in accordance with the warning signal, wherein the content addressable memory comprises: a content data part configured to store the substitutive area addresses in a non-volatile manner; first and second key address parts configured to store key addresses corresponding to the bad area addresses in a non-volatile manner, the first and second key address parts serving as column and row decoders, respectively, used for reading the substitutive area addresses in the content data part; and a selector configured to select a corresponding substitutive area address when an externally supplied address is matched with one of the key addresses defined in the first and second key address parts, and output the externally supplied address as it is when the address matching is not detected.