Patent ID: 7782326

Claim:
An apparatus for videoprocessing comprising: a system bus; and at least one videoprocessing path, each videoprocessing path including: a DMA memory reader, configured to receive a set of input pixels corresponding to non-columnar pixel data across the system bus, a parallel video processor, configured to receive each one of the set of input pixels, and generate corresponding output videocodes (VCODEs), and a video signal generator, configured to receive the output VCODEs in parallel, and generate an image corresponding to the output VCODEs; wherein the parallel video processor comprises a series of 3N 2 bits per pixel input registers, wherein N is an integer, N≧1, wherein a lower third series of the input registers is configured to selectively receive a lower half of the set of input pixels or an output from one or more of the series of input registers, wherein a middle third series of the input registers is configured to selectively receive a lower half of the set of input pixels, an upper half of the set of input pixels, or an output from one or more of the series of input registers, and wherein a top third series of the input registers is configured to either receive an upper half of the set of input pixels or have the content of the top third series of the input registers cleared.