Patent ID: 8822292

Claim:
A method for forming and controlling a molecular level SiO 2 interface layer for a CMOS metal gate/high-K dielectric layer device, comprising: 1) a cleansing step including, after completing local oxide isolation or shallow trench isolation in Gate-First process or removing replaced gate in Gate-Last process and before forming an interface oxide layer, cleansing a wafer and immersing the wafer in HF/isopropyl alcohol/water solution at room temperature, rinsing the wafer with deionized water, spinning the wafer and then putting the wafer into a furnace immediately, wherein a volume ratio of HF:isopropyl alcohol:water is 0.15-1.5%:0.01-0.10%:1%; 2) forming the molecular level SiO 2 interface layer by performing rapid thermal annealing on the wafer for 30-90 seconds in N 2 at 500-600° C. in the Gate-Last process or at 600-800° C. in the Gate-First process; 3) forming a high-K gate dielectric film by forming the high-K gate dielectric film by physical vapor deposition or atom layer deposition, the high-K gate dielectric film comprising one of various high-K gate dielectric films; 4) performing rapid thermal annealing, whereby the rapid thermal annealing is conducted at 500-600° C. for 30-90 seconds in the Gate-Last process or at 800-1000° C. for 20-40 seconds in the Gate-First process; 5) forming the CMOS metal gate by depositing a metal nitride gate on the high-K dielectric film by reactive magnetic sputtering utilizing physical vapor deposition; 6) depositing a barrier layer on the CMOS metal gate by reactive magnetic sputtering; 7) on the barrier layer, depositing a polysilicon film by low-pressure chemical vapor deposition in the Gate-First process or depositing low-resistance metal by magnetic sputtering in the gate-Last process; 8) etching a product of the step 7) by plasma etching with Cl-base gas, F-base gas, or a mixture thereof, using a mask having a gate photolithography pattern, to form a polysilicon film/CMOS metal gate/high-K dielectric film/molecular level SiO 2 interface layer gate stack structure or a CMOS metal gate/high-K dielectric film/molecular level SiO 2 interface layer gate stack structure, respectively; 9) depositing silicon nitride on a product of the step 8) by plasma chemical vapor deposition at 300-400° C., the silicon nitride having a thickness of 200-600 Å; 10) etching the silicon nitride by anisotropic plasma etching to form a first silicon nitride spacer; 11) after source/drain extension implantation and forming a second spacer, performing source/drain implantation to form source/drain regions; 12) activating the source/drain regions by rapid thermal annealing: the rapid thermal annealing is performed at 950-1050° C. in N 2 for 1-15 seconds; and 13) forming contacts and metalizing by performing alloying annealing in N 2 or N 2 +10% H 2 in an alloying furnace at 380-450° C.