Patent ID: 7969191

Claim:
A CMOS input circuit comprising: a first power terminal (VDD, VSS); CMOS input stage (Inv 1 ) comprising a first switching transistor (M 1 , M 2 ), the first switching transistor (M 1 , M 2 ) comprising: a first gate for receiving an input voltage (Vin), a first drain for supplying an output voltage (Vout 1 ), and a first source, wherein a first main current path (CP) is arranged between the first source and the first drain; and a leveling circuit (LC) comprising a leveling transistor (M 3 ) having a leveling circuit main current path (MCP) and a gate electrode (GE), the leveling circuit (LC) being arranged for receiving the input voltage (Vin) and a second voltage associated with the output voltage (Vout 1 ), the leveling circuit main current path (MCP) of the leveling transistor (M 3 ) being electrically connected between the first main current path (CP) of the first switching transistor (M 1 , M 2 ) and the first power terminal (VDD, VSS), and wherein the first source is connected to a junction of the first main current path (CP) of the first switching transistor (M 1 , M 2 ) and the leveling circuit main current path (MCP) of the leveling transistor (M 3 ), and the leveling circuit (LC) is constructed for arranging, under control of the second voltage, the leveling transistor (M 3 ) (i) as a forward-biased diode-connected transistor for regulating a voltage (V 1 ) on the first source, for reducing a gate-source voltage of the first switching transistor (M 1 , M 2 ) when the input voltage (Vin) assumes a level associated with a first logical level causing the first switching transistor (M 1 , M 2 ) to be switched off, and (ii) as a conductive path when the input voltage (Vin) assumes a level associated with a second logical level causing the first switching transistor (M 1 , M 2 ) to be switched on.