Patent ID: 7425842

Claim:
A logic basic cell for processing a first and a second data signal, comprising: a multiplex device for multiplexing the first and second data signals in a multiplex operating state; a logic device for forming a logic combination of the first and second data signals in accordance with a selectable logic function in a logic function operating state, wherein an output signal is one of the first and second data signals during the multiplex operating state, and is the logic combination of the first and second data signals in accordance with the selected logic function during the logic function operating state; and a control unit, which predetermines, based on a control signal, whether the logic basic cell operates in the multiplex operating state or in the logic function operating state, and further comprising: first, second, third, and fourth data signal inputs, to which the first and second data signals and a logically complementary data signals thereof are applied; a first logic selection element connected between the first data signal input and the second data signal input; a second logic selection element connected between the first data signal input and the fourth data signal input; a third logic selection element connected between the second data signal input and the third data signal input; and a fourth logic selection element connected between the third data signal input and the fourth data signal input, wherein the first logic selection element is a first logic transistor, which can be controlled by means of a first logic selection signal; the second logic selection element is a second logic transistor, which can be controlled by means of a second logic selection signal; the third logic selection element is a third logic transistor, which can be controlled by means of a third logic selection signal; and the fourth logic selection element is a fourth logic transistor, which can be controlled by means of a fourth logic selection signal.