Patent ID: 7587012

Claim:
A clock recovery circuit comprising: (a) a data signal input; (b) a clock signal input; (c) first and second phase shifters, the phase shifters being connected in series to a reference clock signal input for providing as a recovered clock signal a phase-shifted replica of an input clock signal applied at the clock signal input; (d) one or more phase detectors operative to detect a phase difference between a data signal applied at the data signal input and the recovered clock signal and provide one or more phase difference signals representing the phase difference; and (e) first and second filters connected to the phase detector, the first and second loop filters being responsive to the one or more phase difference signals and operating to provide one or more control signals concomitantly to the first and second phase shifters, respectively, for effecting additive phase shifting, the phase shifters being responsive to the one or more control signals.