Patent ID: 7900055

Claim:
An apparatus for performing cryptographic operations, comprising: an x86-compatible microprocessor, comprising: fetch logic, configured to receive a single, atomic cryptographic instruction, wherein said single, atomic cryptographic instruction is one of the instructions in an application program, wherein said application program is executed by said x86-compatible microprocessor, and wherein said single, atomic cryptographic instruction prescribes an encryption operation, and wherein said single, atomic cryptographic instruction prescribes one of a plurality of cryptographic algorithms; algorithm logic, operatively coupled to said single, atomic cryptographic instruction, configured to direct said x86-compatible microprocessor to execute said encryption operation according to said one of a plurality of cryptographic algorithms; and execution logic, operatively coupled to said algorithm logic, configured to execute said encryption operation, wherein said execution logic comprises: a cryptography unit for executing a plurality of cryptographic rounds required to complete said encryption operation, wherein said cryptography unit executes a first plurality of micro instructions generated by translation of said single, atomic cryptographic instruction; and an x86 integer unit, wherein said cryptography unit operates in parallel with said x86 integer unit to accomplish said encryption operation, and wherein said x86 integer unit executes a second plurality of micro instructions generated by translation of said single, atomic cryptographic instruction to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of said encryption operation.