Patent ID: 7847386

Claim:
A semiconductor package, comprising: a bulk layer defining opposed, generally planar first and second surfaces and a side surface, the bulk layer having at least one first bond pad formed therein, the first bond pad defining opposed, generally planar first and second surfaces with the first surface of the first bond pad being exposed in and extending in generally co-planar relation to the first surface of the bulk layer, and the second surface of the first bond pad extending in generally co-planar relation to the second surface of the bulk layer; at least one active layer defining a side surface, the active layer being formed on the bulk layer and electrically connected to the first bond pad; at least one second bond pad formed on the active layer and electrically connected thereto, the second bond pad defining a generally planar first surface and being separated from the first bond pad by the active layer; and a protection layer defining a side surface and generally planar first surface which extends in generally co-planar relation to the first surface of the second bond pad, the protection layer being formed on the active layer and at least partially encapsulating the second bond pad formed thereon; the side surfaces of the bulk layer, the active layer and the protection layer extending in generally co-planar relation to each other.