Patent ID: 6986109

Claim:
A method of modifying a hierarchical integrated circuit layout to satisfy objectives, said method comprising: representing locations of layout elements in said hierarchical integrated circuit layout as layout formulae having layout variables to produce a formula-based hierarchical layout, wherein each of said layout variables represents a location of a given layout element in a single dimension; determining constant values to be substituted for assigned variables of said layout variables to produce a partial solution to said layout formulae; substituting said constant values for said assigned variables in said layout formulae to produce simplified formulae from said layout formulae, wherein after said substituting process each of said simplified formulae contains no more than two remaining variables of said layout variables; representing said objectives as a single objective function using at least one of said remaining variables; optimizing said objective function by substituting optimized values for said remaining variables in said objective function to produce an optimized objective function, wherein said optimized values one of minimize and maximize a result of said objective function, and wherein said optimized values comprise legal values that, when substituted for said remaining values in said simplified formulae, obey inequality restrictions in said simplified formulae; combining said simplified formulae and said optimized objective function to produce a total solution; and outputting integrated circuit modification values from said total solution, wherein said modification values are used to produce a modified hierarchical integrated circuit layout.