Patent ID: 8310471

Claim:
A display apparatus, comprising: a substrate; a first scanning line formed on the substrate and disposed in a first direction; a second scanning line disposed on the substrate in parallel with the first scanning line to accompany the first scanning line; a first signal line disposed on the substrate so as to cross the first and second scanning lines; a first switching element formed on the substrate, the first switching element having: a first gate electrode; a gate insulating film covering said first gate electrode; a first semiconductor layer formed on the gate insulating film; and a first source electrode and a first drain electrode formed on the first semiconductor layer, one of the first source electrode and the first drain electrode being connected to said first signal line, the first gate electrode being connected to said first scanning line; a second switching element formed on the substrate, the second switching element having: a second gate electrode; said gate insulating film covering said second gate electrode; a second semiconductor layer formed on the gate insulating film; and a second source electrode and a second drain electrode formed on the second semiconductor layer, one of the second source electrode and the second drain electrode being connected to the other one of the first source electrode and the first drain electrode of said first switching element, the second gate electrode being connected to said second scanning line; a first pixel electrode connected to said other one of the first source electrode and the first drain electrode of said first switching element so that the first pixel electrode is applied with a gray scale signal that is supplied to the first signal line under control of the first switching element; and a second pixel electrode connected to the other one of the second source electrode and the second drain electrode of said second switching element so that the second pixel electrode is applied with a gray scale signal that is applied to the first signal line through said first pixel electrode under control of the first switching element and the second switching element; a first auxiliary capacitance line formed on the substrate opposite to said first pixel electrode; a second auxiliary capacitance line formed on the substrate opposite to said second pixel electrode; an interconnection line that connects said other one of the first source electrode and the first drain electrode of said first switching element to said one of the second source electrode and the second drain electrode of said second switching element, wherein said first auxiliary capacitance line and said second auxiliary capacitance line are formed in a same layer as said first and second gate electrodes, and are covered by said gate insulating film, and wherein said interconnection line is formed on said gate insulating film so as to overlap said first auxiliary capacitance line and said second auxiliary capacitance line through said gate insulting film.