Patent ID: 7718503

Claim:
A method for fabricating a semiconductor on insulator (SOI) device comprising a semiconductor substrate, a buried insulator layer overlying the semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the method comprising the steps of: forming a MOS capacitor coupled between a first voltage bus and a second voltage bus, the MOS capacitor having a gate electrode material forming a first plate of the MOS capacitor and coupled to the first voltage bus, an impurity doped region in the monocrystalline semiconductor layer beneath the gate electrode material forming a second plate of the MOS capacitor and coupled to the second voltage bus, a first contact region electrically in series with the impurity doped region, and a second contact region electrically in series with the impurity doped region, wherein the gate electrode material, impurity doped region, first contact region, and second contact region each have the same conductivity type; forming a first electrical discharge path coupling the first plate of the MOS capacitor to a diode formed in the semiconductor substrate, wherein the first voltage bus is coupled to an n-type impurity doped region of the diode; and forming a second electrical discharge path coupling the second plate of the MOS capacitor to the semiconductor substrate, wherein the second electrical discharge path comprises conductors without any intermediate device included in the second electrical discharge path.