Patent ID: 7126505

Claim:
A method for implementing an L:M Fractional Sample Rate Converter (F-SRC), for controlled and direct insertion/cancellation of samples in a processed data stream, the method comprising: receiving an input data stream with an input block, processing L signal samples (x(m)) having an input data rate (f in ), in a predetermined time interval (T s ); generating an interpolated data stream upsampled times a factor P (P<M), by the input block providing signal samples (x 1 ( h )) having a data rate Pf in ; generating an intermediate data stream with a rate adapting stage receiving the signal samples from the input block, and providing signal samples (y 1 ( k )) adapted to an intermediate data rate (Pf out ); delivering an output data stream with a low pass and P:1 decimation filter receiving the signal samples from the rate adapting stage, including M signal samples having a desired output data rate (f out =M/T s ); generating an up-sampled weighted stream in the rate adapting stage by weighting the signal samples (x 1 ( h )) of the interpolated data stream; and adapting the input data rate in the rate adapting stage to the output data rate by a direct insertion of zero-padded samples into the up-sampled weighted stream when L<M, and by a direct cancellation of samples when L>M.