Patent ID: 7275129

Claim:
A system comprising: write data fan-out circuitry, having a CPU side configured to be coupled to a subset of bus lines of a CPU data bus and having a RAM side configured to be coupled to a plurality of RAM data buses configured to fan out a subset of the data bus lines of a coupled CPU data bus to provide a copy of data carried on the subset of bus lines to each of a plurality of coupled RAM data buses; address fan-out circuitry, having a CPU side configured to be coupled to a CPU side address bus to receive read and write addresses from the coupled CPU and having a RAM side configured to be coupled to a plurality of RAM address buses configured to fan out a coupled CPU address bus to provide a copy of the address data to each of a plurality of coupled RAM address buses; control signal fan-out circuitry, having a CPU side configured to be coupled to a CPU read/write control line and having a RAM side configured to be coupled to a plurality of RAM control lines configured to fan out a coupled CPU control signal line to provide a copy of a control signal to each of a plurality of coupled RAM control lines; and concatenating circuitry, having a CPU side configured to be coupled to a plurality of subsets of bus lines of a CPU side data bus and having a RAM side configured to be coupled to a plurality of RAM data buses configured to concatenate data fields read from the same storage location received on different coupled RAM data buses onto subsets of bus lines of a coupled CPU data bus, with data from each of the plurality of RAM data buses transferred to an associated subset of bus lines of a coupled CPU data bus; and acknowledge signal generating circuitry, having a CPU side configured to be coupled to a CPU acknowledge line, having a RAM side configured to be coupled to a plurality of RAM acknowledge lines, and configured to generate a CPU acknowledge signal when RAM acknowledge signals are received on all coupled RAM acknowledge lines.