Patent ID: 8418095

Claim:
A method of compiling a hardware description language (HDL) specification for simulation of a circuit design, the method comprising using one or more processors to perform operations including: elaborating the circuit design from the HDL specification; determining non-blocking assignments in the elaborated circuit design; for each net to which one or more of the non-blocking assignments are sensitive, creating a corresponding data structure indicating each non-blocking assignment sensitive to the net; and generating simulation code that models the circuit design, the simulation code configured and arranged during runtime to: for each net to which one or more of the non-blocking assignments are sensitive, in response to the net being updated in a cycle of simulation, add the data structure corresponding to the net to a list; and in response to completing the cycle of simulation, for each data structure in the list: perform each non-blocking assignment indicated by the data structure; and remove the data structure from the list.