Patent ID: 7383427

Claim:
A method of executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit, comprising: a) detecting a plurality of sequences of instructions adapted for parallel execution from instructions being provided to said processor, each sequence of said plurality of sequences adapted for execution by a subset of said plurality of execution units, b) storing information in a register representing a stall status of said execution units; c) for each unexecuted sequence of said plurality of sequences: i) stalling all of said plurality of execution units other than said subset which corresponds to said unexecuted sequence and setting a current stall status for said stalled execution units; ii) executing said sequence of instructions by said corresponding subset; d) determining whether the current stall status of said plurality of execution units matches the stall status represented by said stored information; and e) when there is no match, repeating said steps b) through d) until there is a match in which the current stall status matches said stored information.