Patent ID: 8285394

Claim:
A demultiplexer circuit formed on a semiconductor substrate, comprising: a power supply having an energy storage capacitor and a bridge rectifier both formed on the semiconductor substrate, with the power supply receiving an alternating-current (ac) input voltage to generate therefrom all direct-current (dc) electrical power to operate the demultiplexer circuit; a plurality of latches formed on the semiconductor substrate, with each latch having an ac-coupled input wherein a digital addressing signal is received one bit at a time, with each bit of the digital addressing signal being stored in that latch and provided to an output thereof until such time as a subsequent bit of the digital addressing signal is received at the ac-coupled input of that latch, the ac-coupled input to each latch: including a coupling capacitor formed from a plurality of metal layers which are stacked up with a dielectric layer separating each adjacent pair of the metal layers; and one of the plurality of metal layers forming a bond pad for the ac-coupled input to that latch; and at least one 1:2 N demultiplexer formed on the semiconductor substrate, with each 1:2 N demultiplexer having a neural stimulation signal input and an integer number N of addressing inputs, and with the N addressing inputs being connected to the outputs of a set of N of the plurality of latches to receive N bits of the digital addressing signal stored in the set of N latches to program that 1:2 N demultiplexer and thereby connect the neural stimulation signal input to one of 2N outputs for that 1:2 N demultiplexer.