Patent ID: 7352058

Claim:
A method for forming a multiple die integrated circuit package comprising the steps of: providing an insulator layer having a first surface and a second opposing surface; forming one or more through-hole vias in said insulator layer at desired locations; providing a first leadframe having a plurality of leads at least partially overlying said first surface; providing a second leadframe having a plurality of leads at least partially overlying said second surface; coupling a first integrated circuit die to at least one lead of said first leadframe; coupling a second integrated circuit die to at least one lead of said second leadframe; deforming a lead of the first leadframe, at a position covering a through-hole via, into the through-hole via; electrically connecting the lead deformed into the via to a corresponding lead of the second leadframe through the through-hole via in said insulator; whereby the first and second integrated circuit dies are electrically coupled to one another.