Patent ID: 8198163

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a plurality of gate structures on a semiconductor substrate; forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, wherein forming each of the impurity regions includes: forming a lightly doped region at a side of a channel region below the gate structures, and forming a heavily doped region at a side of the gate structures in the semiconductor substrate so that the lightly doped region is between the heavily doped region and the channel region; forming a dielectric layer on the semiconductor substrate having the gate structures; forming contact holes in the dielectric layer to expose parts of the impurity regions at sides of the gate structures; directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and wherein directly implanting impurity ions takes place after forming the heavily doped region; annealing the impurity regions after directly implanting impurity ions; and forming conductive plugs in the contact holes after annealing the impurity regions.