Patent ID: 7822196

Claim:
A data transformation apparatus comprising: a data processing unit configured to receive input data and key data, and perform at least one of encryption decryption of the input data using the key data, wherein the data processing unit comprises a non-linear transformation unit configured to receive at least part of the input data as data to be transformed, and perform a non-linear transformation of the data to be transformed, wherein the non-linear transformation unit includes: a first transformation unit configured to: receive a part of the data to be transformed as first partial data, transform the first partial data by performing a lookup of a transformation table based on a value of the first partial data to obtain a transformed value of the first partial data, and output the transformed value of the first partial data; a second transformation unit configured to: receive at least another part of the data to be transformed as second partial data, transform the second partial data by performing a lookup of the transformation table based on a value of the second partial data to obtain a corresponding value of the second partial data, and performing an operation on the corresponding value of the second partial data to obtain a transformed value of the second partial data, and output the transformed value of the second partial data; and a third transformation unit configured to: receive a part of the data to be transformed, which is different from the first and second partial data, as third partial data, transform the third partial data by performing an operation on a value of the third partial data to obtain a corresponding value of the third partial data, and performing a lookup of the transformation table based on the corresponding value of the third partial data, to obtain a transformed value of the third partial data, and output the transformed value of the third partial data, wherein the non-linear transformation unit is implemented using at least one of a computer processor and a logical operation circuit.