Patent ID: 7542368

Claim:
A semiconductor memory device for storing information on a memory cell using a potential change in a word line and a bit line, the semiconductor memory device comprising: a memory cell having a circuit configuration in which a potential supplied to a source of a load transistor included in a latch section is different from at least one of a potential supplied to the word line and a potential supplied to the bit line; a first control circuit for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin; and a second control circuit for controlling the potential supplied to the source of the load transistor to be lower than at least one of the potential supplied to the word line and the potential supplied to the bit line, during an arbitrary period of at least a read operation in the test mode, wherein the second control circuit includes a plurality of transistors connected with each other in series between a power supply and a ground potential, the plurality of transistors includes at least a first transistor and a second transistor, and a connecting point, at which the first transistor connects with the second transistor, connects with the source of the load transistor.