Patent ID: 8202795

Claim:
A method of fabricating a semiconductor device, the method comprising: forming gate patterns over a substrate; forming a recess in the substrate between the gate patterns, thereby forming a first resultant structure including the recess; forming a gate spacer layer on an entire surface of the first resultant structure including the gate patterns; etching the gate spacer layer at a bottom of the recess; forming a plug on the recess through an epitaxial growth process, thereby forming a second resultant structure including the plug; forming a cell spacer layer on an entire surface of the second resultant structure; forming an insulation layer on the cell spacer layer to fill in spaces between the gate patterns; etching the insulation layer until the cell spacer layer on the gate patterns is exposed; exposing the plug by etching the insulation layer and the cell spacer layer between the gate patterns; forming a conductive layer over the plug; and planarizing the conductive layer to form a landing plug contact.