Patent ID: 6864541

Claim:
A semiconductor device provided with a memory cell including a first driver transistor, a second driver transistor, a first transfer transistor, a second transfer transistor, a first load transistor and a second load transistor, the semiconductor device comprising: a first gate-gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor, a second gate-gate electrode layer including a gate electrode of the second load transistor and a gate electrode of the second driver transistor, a first drain-drain wiring layer which forms a part of a connection layer that electrically connects a drain region of the first load transistor and a drain region of the first driver transistor; a second drain-drain wiring layer which forms a part of a connection layer that electrically connects a drain region of the second load transistor and a drain region of the second driver transistor; a first drain-gate wiring layer which forms a part of a connection layer that electrically connects the first gate-gate electrode layer and the second drain-drain wiring layer; a second drain-gate wiring layer which forms a part of a connection layer that electrically connects the second gate-gate electrode layer and the first drain-drain wiring layer; and a first active region in which the first load transistor is provided, wherein the first drain-gate wiring layer and the second drain-gate wiring layer are located in different layer levels, respectively, and wherein a first protruded active region is provided in a manner to protrude from an end portion of the first active region, and wherein the second drain-gate wiring layer includes a lower layer of the second drain-gate wiring layer and an upper layer of the second drain-gate wiring layer; and wherein the upper layer is located in a layer over the lower layer, and electrically connected to the lower layer; and wherein the first gate-gate electrode layer, the second gate-gate electrode layer and the first drain-gate wiring layer are located in a first conductive layer level; and wherein the first drain-drain wiring layer, the second drain-drain wiring layer and the lower layer are located in a second conductive layer level; and wherein the upper layer is located in a third conductive layer level.