Patent ID: 7923294

Claim:
A method for manufacturing a semiconductor package, comprising the steps of: forming a semiconductor chip having a passivation layer pattern which expose bonding pads; forming a first insulation layer pattern on the passivation layer pattern in which the first insulation layer pattern having first openings exposing the bonding pads; forming redistribution line patterns on the first insulation layer pattern in which the redistribution line patterns are electrically connected with the bonding pads; forming a second insulation layer pattern covering the redistribution line patterns and having second openings which have first open areas exposing portions of the redistribution line patterns and second open areas extending away from the first open areas to edges of the semiconductor chip, wherein the second open areas expose portions of the first insulation layer pattern; and connecting conductive balls to the portions of the redistribution line patterns exposed through the first open areas of the second insulation layer pattern.