Patent ID: 7509459

Claim:
A microprocessor coupled to a system memory, comprising: a plurality of stream prefetch engines, each configured to prefetch a respective data stream from the system memory into a cache memory of the microprocessor; and an instruction decoder, coupled to said plurality of stream prefetch engines, configured to decode instructions of an instruction set of the microprocessor, said instruction set comprising: a stream prefetch instruction, that specifies a data stream and a fetch-ahead distance and returns a stream identifier that uniquely associates said specified data stream with one of said plurality of stream prefetch engines; and a load instruction, that specifies an address of data to be read from the system memory into the microprocessor, and that further specifies a stream identifier returned from a previous execution of one of said stream prefetch instructions; wherein each stream prefetch engine is configured to prefetch a portion of said respective data stream in response to said instruction decoder decoding one of said load instructions whose stream identifier identifies said stream prefetch engine, and wherein each stream prefetch engine is further configured to suspend prefetching of said data stream once a difference between a current prefetch address associated with said respective stream prefetch engine and said address specified by the load instruction is greater than said fetch-ahead distance, and is further configured to resume prefetching of said data stream once said difference is less than said fetch-ahead distance.