Patent ID: 7911006

Claim:
An integrated circuit structure comprising: a semiconductor layer having a major surface formed along a plane having first and second areas; a first doped region of a first conductivity type in the first area of the surface; multiple layers over the first doped region in the first area and over the second area, wherein the multiple layers have a first window therein extending to the first doped region and a second window in the second area, the second window comprising sidewall and bottom surfaces; a second doped region of a second conductivity type in the window formed in the first area; a third doped region of the first conductivity type over the second doped region in the first area; a gate oxide adjacent the second doped region in the first area; a first conductive layer with first and second electrically continuous portions, each of which is laterally disposed in the respective first and second areas, wherein the first electrically continuous portion is adjacent the gate oxide in the first area; within the second window a second conductive layer substantially conformal with the sidewall surfaces and the bottom surfaces in the window and electrically connected to the second electrically continuous portion of the first conductive layer; a conformal dielectric layer within the second window and over the second conductive layer; and a third conductive layer over the dielectric layer, such that the third conductive layer, the dielectric layer and the second conductive layer form a capacitor.