Patent ID: 6845030

Claim:
A nonvolatile ferroelectric memory device, comprising: a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks including a first plurality of unit cells; a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks including a second plurality of unit cells; a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells; and a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions, said main bit lines being formed in a plurality of layers that are disposed on a plurality of parallel planes.