Patent ID: 7542347

Claim:
A semiconductor device comprising: a plurality of word lines; a plurality of first memory cells being arranged at points of intersection of the plurality of word lines and a plurality of first data lines and storing a first information or a second information; a plurality of first dummy cells being arranged at points of intersection of the plurality of word lines and a first dummy data line and storing the first information; a plurality of second dummy cells being arranged at points of intersection of the plurality of word lines and a second dummy data line and storing the second information; a first multiplexer supplying a first potential to the plurality of first data lines; a second multiplexer connected between the plurality of first data lines and a first writing circuit; a third multiplexer supplying the first potential to the first dummy data line and the second dummy data line; and a fourth multiplexer connected between the first dummy data line and the second dummy data line, wherein a first writing circuit supplies the first potential to one of the plurality of the first data lines when the first information is written in one of the plurality of first memory cells and supplies a second potential higher than the first potential to one of the plurality of first data lines when the second information is written in one of the plurality of first memory cells, wherein the fourth multiplexer supplies the first potential to the first dummy data line and supplies the second potential to the second dummy data line when the first information is written in the plurality of first dummy cells and the second information is written in the plurality of second dummy cells.