Patent ID: 8601315

Claim:
A device configured to enable debugging of a return by the device from a low power mode state, the device comprising: a first set of components that process instructions and performs functional operations of the device; a second set of components that facilitates debugging operations of the device and which maintain one or more current debug states while receiving power; a power management module (PMM) having PMM logic that in response to receiving an input to activate a return of the device from a low power state in which power was removed from the first set of components and the second set of components: determines a type of low power mode from which the device is returning, where the type is one of a plurality of different types of low power modes; and in response to the device returning from a first type low power mode in which the current debug states of the second set of components are lost, prevents one or more of the first set of components from resuming processing operations until the second set of components have been re-configured to their respective current debug states; wherein the PMM logic further: detects an entry of the device into the low power mode; automatically asserts a reset signal to the first set of components in response to detecting the device's entry into the low power mode; continues to assert the reset signal in response to the device returning from the first type low power mode; receives an input indicating an assertion of the reset signal is no longer required; and automatically negates the reset signal to enable the first set of components to resume processing, in response to receiving the input indicating the assertion of the reset signal is no longer required.