Patent ID: 8553027

Claim:
A gate driver comprising: a decoder that decodes gate line selection data and that generates a gate line selection signal; and a gate driving circuit that generates a gate driving signal in a pre-charging phase and in a driving phase in response to the gate line selection signal and a pre-charging control signal that controls an off-state of non-selected gate lines, wherein in a time period of the driving phase in which a gate line is not selected, a node that has been in a floating state is held at a target voltage level in response to a hold control signal, wherein the hold control signal is generated based upon a timing relationship between the gate line selection signal and the pre-charging control signal, wherein the gate driving circuit comprises: a first switching circuit that generates a gate driving signal in response to the gate line selection signal and the pre-charging control signal at each of a first node and a second node, wherein the first node is coupled to an input of the first switching circuit and the second node is determined based upon a voltage of the first node, wherein a second switching circuit electrically connects the first node to a first voltage supply terminal for a time period in which the first node is in a floating state based upon the hold control signal and the voltage level of second node, wherein the second switching circuit comprises: a first switching device that switches according to the voltage level of the hold control signal; and a second switching device that switches according to the voltage level of the second node, and wherein the first switching device and the second switching device are connected and arranged in series between the first node and the first voltage supply terminal.