Patent ID: 8219775

Claim:
A memory system comprising: a nonvolatile memory including a plurality of memory cells arranged among a plurality of physical memory blocks and within respective arrays, wherein each physical memory block is of a predetermined size; and a memory control module in communication with the nonvolatile memory, wherein the memory control module includes a write path module, wherein in response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module is configured to modify the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks, the second format of the data includes logical data structures, the logical data structures include a first logical data structure and a second logical data structure, the logical data structures are not evenly distributable among the plurality of physical memory blocks, the write path module is configured to store (i) a first portion of the first logical data structure in a first row of a first one of the arrays, and (ii) a second portion of the first logical data structure in a second row of a second one of the arrays, and the first one of the arrays is separate from the second one of the arrays, and a read path module configured to read the data from the nonvolatile memory in accordance with the second format.