Patent ID: 8072064

Claim:
A semiconductor package, comprising: a first chip, comprising: a first active surface; a first back surface; a first top metal layer, disposed adjacent to the first active surface, and spaced apart from the first active surface by a first distance; at least one first non-top metal layer, disposed adjacent to the first active surface, and spaced apart from the first active surface by a second distance, wherein the second distance is greater than the first distance; a plurality of first signal coupling pads, disposed on the first non-top metal layer; a plurality of second signal coupling pads, disposed adjacent to the first back surface and electrically connected to the first signal coupling pads; at least one first power pad, disposed adjacent to the first active surface; at least one first ground pad, disposed adjacent to the first active surface; at least one second power pad, disposed adjacent to the first back surface; at least one second ground pad, disposed adjacent to the first back surface; and at least one first through-chip via, electrically connecting the first power pad and the second power pad; at least one second through-chip via, electrically connecting the first ground pad and the second ground pad; and a second chip, electrically connected to the first chip, and the second chip comprising: a second active surface; facing the first active surface of the first chip; a second top metal layer, disposed adjacent to the second active surface, and spaced apart from the second active surface by a third distance; at least one second non-top metal layer, disposed adjacent to the second active surface, and spaced apart from the second active surface by a fourth distance, wherein the fourth distance is greater than the third distance; a plurality of third signal coupling pads, disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip; at least one third power pad, disposed adjacent to the second active surface and electrically connected to the first power pad of the first chip; and at least one third ground pad, disposed adjacent to the second active surface and electrically connected to the first ground pad of the first chip.