Patent ID: 8627190

Claim:
A memory device electrically connectable to a host circuit, comprising: a nonvolatile data memory section including a first memory area and a second memory area related to the first memory area; a data reception section that receives, from the host circuit, data including a first actual data to be written into the first memory area; a parity acquisition section that acquires first parity data associated with the first actual data; a data copy section that generates second actual data that is a copy of the first actual data, and second parity that is a copy of the first parity data; a read/write control section that writes the first actual data and the first parity data into the first memory area, and writes the second actual data and the second parity data into the second memory area; and a data transmission section that reads the first actual data, the first parity data, the second actual data, and the second parity data from the data memory section for transmission to the host circuit; wherein the first memory area has a first actual data area for writing of the first actual data, and a first parity area for writing of the first parity data, the read/write control section includes a first detection section that detects defects in the first memory area by determining consistency between actual data previously stored in the first actual data area and parity data previously stored in the first parity area, and the read/write control section writes the first actual data area and the first parity data into the first memory area when no defect is detected in the first memory area, wherein if a defect is detected in the first memory area, the read/write control section writes again to the first memory area the actual data and the parity data which were previously stored in the first memory area and which were read out from the first memory area; and wherein the memory device is electrically connected to the host circuit with a single data line and transmits and receives a data signal to and from the host circuit via the single data line.