Patent ID: 8772876

Claim:
A high-voltage transistor, comprising: a gate channel formed in a silicon-on-insulator (SOI) layer of a substrate, wherein the substrate includes a bulk silicon layer that is below an insulator layer that is below the SOI layer; a first transistor node coupled to the gate channel; and a second transistor node coupled to the gate channel; wherein: the first transistor node includes a first diffusion region of the transistor, and a portion of the first transistor node is formed in the SOI layer; a portion of the first transistor node includes a first epitaxial silicon layer formed on the first diffusion region, and the first diffusion region and the first epitaxial silicon layer have a combined first resistance sufficient to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V; the second transistor node includes a second diffusion region of the transistor, and a portion of the second transistor node is formed in the SOI layer; and a portion of the second transistor node includes a second epitaxial silicon layer formed on the second diffusion region, and the second diffusion region and the second epitaxial silicon layer have a combined second resistance lower than the first resistance such that a negligible voltage drop occurs across the second transistor node.