Patent ID: 8171446

Claim:
A method for designing a semiconductor device comprising: setting a given region in a core region of the semiconductor device; computing a current consumption value of the given region based on a current consumption value of a cell included in the given region; computing an amount of a first power supply voltage drop from a power source for supplying the cell with a power supply voltage to a first position corresponding to the given region of a first power supply line based on the current consumption value and a resistance value of the first power supply line included in a first wiring layer of the semiconductor device; computing a contact resistance value corresponding to a second position based on the current consumption value, the first power supply voltage drop, and an allowable power supply voltage drop set for the second position corresponding to the given region of a second power supply line included in a second wiring layer different from the first wiring layer, the allowable power supply voltage drop being set based on a voltage of the power supply source; and computing, by using a computer, a number of vias for the given region based on a result of a comparison between a resistance value of a via coupling the first power supply line and the second power supply line, and the contact resistance value.