Patent ID: 7571405

Claim:
A method of performing design rule checking on a netlist representation of an electronic design using an electronic design automation (EDA) computer system, the method comprising: (a) receiving a plurality of design rules specifying constraints on the properties of particular nodes in a netlist, wherein each rule specifies a logical combination of constraints on properties of particular nodes in the netlist, without including functionality for extracting said properties from the netlist; (b) at a first node of the netlist, employing a generic routine to execute a first design rule from the plurality of design rules and determine whether properties of the first node violate the first design rule; and (c) at the first node of the netlist, employing the generic routine to execute a second design rule from the plurality of design rules and determine whether properties of the first node violate the second design rule, wherein the generic routine is operable to execute a plurality of different design rules that follow a format generic to the rules, said format including a rule name and at least one a sub-rule and at least one a sub-rule element.