Patent ID: 7808265

Claim:
A circuit inside a wafer, the circuit having a plurality of output lines, the circuit comprising: a first stack having a plurality of first inputs coupled to a plurality of test structures located within the wafer; wherein the first stack is coupled to a source of a first voltage in the wafer; a second stack having a plurality of second inputs coupled to a plurality of reference devices located within the wafer; wherein the second stack is coupled to a source of a reference voltage in the wafer; each of the first stack and the second stack comprising a first-type device and at least two second-type devices; wherein the first-type device is one of a p-channel device or an n-channel device; wherein each second-type device is the other of the p-channel device or the n-channel device; wherein each stack is coupled to an output line of the circuit; and wherein at least one characteristic of a test structure has a predetermined relationship with a corresponding characteristic of at least one reference device.