Patent ID: 6927145

Claim:
A method of manufacturing a semiconductor device, the method comprising the steps of: forming a charge trapping layer over a substrate; forming a hard mask with openings of a width dimension less than achievable at a resolution limit of lithography including: forming a hard mask layer over the charge trapping layer; depositing and patterning a photoresist layer over the hard mask layer to form a pattern in the photoresist; and transferring the pattern from the photoresist to the hard mask layer; forming buried bitlines in the substrate; and forming a doped region adjacent at least one of the buried bitlines, wherein the doped region adjacent the at least one of the buried bitlines inhibits a leakage current between the buried bitlines, and wherein forming the doped region and the buried bitlines respectively include: implanting the substrate through apertures in the hard mask to form the doped region adjacent the at least one of the buried bitlines with a first dopant type; and implanting the substrate through the apertures in the hard mask to form the buried bitlines of a second dopant type opposite the first dopant type.