Patent ID: 8451306

Claim:
A reference voltage generation circuit comprising: a first current-mirror circuit including a first MOS transistor of a first conductive type connected to a first power source and a second MOS transistor of the first conductive type connected to the first power source; a second current-mirror circuit including a third MOS transistor of a second conductive type and a fourth MOS transistor of the second conductive type, said second current-mirror circuit being disposed between the first current-mirror circuit, and a first node and a second node, and being vertically connected to the first current-mirror circuit; a first resistor having one end portion connected to the first node; a first bipolar transistor having a collector connected to the other end portion of the first resistor, an emitter connected to a second power source having a potential different from that of the first power source, and a base connected to the first node; a second bipolar transistor having a collector directly connected to the second node or connected to the second node through a second resistor, an emitter connected to the second power source, and a base connected to the collector of the first bipolar transistor; a fifth MOS transistor connected between the first power source and an output terminal for outputting a reference voltage so that a conductive state of the fifth MOS transistor is controlled according to an output voltage of the first current-mirror circuit; a third resistor connected in series between the output terminal and the second power source; a third current-mirror circuit including a seventh MOS transistor of the first conductive type connected to the first power source and an eighth MOS transistor of the first conductive type connected to the first power source; a fourth current-mirror circuit including a ninth MOS transistor of the second conductive type and a tenth MOS transistor of the second conductive type, said second current-mirror circuit being disposed between the third current-mirror circuit, and a third node and a fourth node, and being vertically connected to the third current-mirror circuit; a third bipolar transistor having a collector and a base connected to the third node and an emitter connected to the second power source; a fourth resistor connected in series between the fourth node and the second power source; an eleventh MOS transistor connected between the first power source and a fifth node so that a conductive state of the eleventh MOS transistor is controlled according to an output voltage of the third current-mirror circuit; and a fifth current-mirror circuit including a twelfth MOS transistor of the second conductive disposed between the fifth node and the out terminal and connected in series to the eleventh MOS transistor, and a thirteenth MOS transistor of the second conductive type connected in parallel to the third resistor.