Patent ID: 8295111

Claim:
A semiconductor memory device comprising: a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are formed in order from a first side to a second side; first and second bit lines coupled to a plurality of memory cells formed in the first cell array region; first and second complementary bit lines coupled to a plurality of memory cells formed in the second cell array region, wherein the first and second complementary bit lines are complementary to the respective first and second bit lines; a first column selector formed in the first sense circuit region and coupled to the first bit line and the first complementary bit line; and a second column selector formed in the second sense circuit region and coupled to the second bit line and the second complementary bit line, wherein: the first column selector and the second column selector are formed directly adjacent to each other; a first sense amplifier of a first conductivity type, a first equalizer, a second sense amplifier of a second conductivity type, and the first column selector are positioned in the first sense circuit region in order from the first side to the second side; and the second column selector, a third sense amplifier of the second conductivity type, a second equalizer, and a fourth sense amplifier of the first conductivity type are positioned in the second sense circuit region in order from the first side to the second side.