Patent ID: 8664989

Claim:
In a fractional phase-locked loop, a delta-sigma modulator providing increased frequency resolution, comprising: an input receiving a feedback divide ratio value; a subtractor receiving the feedback divide ratio value and a feedback factor and outputting the difference of the feedback divide ratio value and the feedback factor; an integrator averaging the difference between the divide ratio value and the feedback factor and outputting an averaged value; a quantizer receiving the averaged value from the integrator and outputting a quantized value controlling a feedback divider in the fractional phase-locked loop; and a feedback amplifier multiplying the value quantized value by a predetermined gain factor that is used to modify a gain factor of the feedback amplifier to provide improved modulator stability and the increased frequency resolution and outputting the feedback factor to the subtractor, wherein the predetermined gain factor is determined by: determining an initial gain factor for which the value of the feedback divide ratio can be represented precisely in a binary format, determining the a value having a closest power of two larger than the initial gain factor, to be used as the denominator in the gain factor, and dividing the initial gain factor by a value having the closest power of two larger than the initial gain factor, to produce the predetermined gain factor.