Patent ID: 8742831

Claim:
A method for digital programmable optimization of a mixed-signal circuit, the method comprising: dividing up one or more transistor devices of the mixed-signal circuit into a plurality of transistor segments, with each transistor segment including a body tie bias terminal, and with each transistor segment coupled directly to a same voltage source bus, a same voltage drain bus, and a same voltage gate bus; coupling a first body tie bias terminal of a first transistor segment to a first voltage bias by: coupling the first body tie bias terminal in signal communication with a first bias node in the mixed-signal circuit; or coupling the first body tie bias terminal in signal communication with a first non-precision bias voltage source in the mixed-signal circuit; coupling a second body tie bias terminal of a second transistor segment to a second, different voltage bias by: coupling the second body tie bias terminal in signal communication with a second, different bias node that is different from the first bias node in the mixed-signal circuit; or coupling the second body tie bias terminal in signal communication with a second, different non-precision bias voltage source that is different from the first non-precision bias voltage source in the mixed-signal circuit; and arranging each body tie bias terminal to be coupled to a separate one of one or more digital programmable storage elements.