Patent ID: 8301870

Claim:
An apparatus, comprising: an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other as two concurrent co-routine threads, wherein said two concurrent co-routine threads result because a synchronization of said at least two threads is achieved by monitoring addresses of instructions in at least one of said at least two threads without modifying, changing, or altering the threads, said monitoring of addresses being controlled by an occurrence of an instruction in an execution of a first thread that is monitoring a second thread, wherein two of said at least two threads comprise: a main program thread of a main program; and an associated meta-program thread, wherein said meta-program thread monitors addresses of said main program thread, as controlled by a specific instruction in said meta-program thread, and said meta-program thread comprises a thread in a meta-program that fetches and stores meta-program information of executing the main program, wherein an execution of said meta-program does not alter an original binary code of said main program, wherein said out-of-order processor comprises an instruction decoder having a meta-program control unit (MPCU) that generates a meta-program instruction tag for each meta-program instruction to be processed, said meta-program instruction tag comprising a plurality of portions, wherein: one of the portions identifies a main program instruction associated with said meta-program instruction to be processed; and another of the portions provides an identification scheme of all meta-program instructions to be processed with the associated main program instruction, said out-of-order processor further comprising: a storage structure to store meta-program instructions; and a completion unit to: track an oldest meta-program instruction in said storage structure that can one of control and monitor a main program instruction; and retire instructions completely executed from both threads in an interleaved order specified by the meta-program control instruction.