Patent ID: 7882467

Claim:
A test pattern evaluation method for evaluating a test pattern for verifying a semiconductor integrated circuit comprising a plurality of cells for implementing a specific function with a transistor, wherein it is assumed that each possible internal state of the cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of the transistor determined by a voltage between terminals of the transistor is a transistor state, the method comprising: using a computer for: a step for verifying operation of the semiconductor integrated circuit at a gate level or higher using design data of the semiconductor integrated circuit and the test pattern; a step for acquiring the cell state continuously appearing in the cell for a predetermined time or more in the step for verifying the operation as an appearance cell state, with respect to each cell constituting the semiconductor integrated circuit; a step for acquiring the transistor state appearing in the transistor in the step for verifying the operation as an appearance transistor state, using the appearance cell state of the cell including the transistor, with respect to each transistor constituting the cell; and a step for calculating a test activity ratio of the transistor using the corresponding appearance transistor state, with respect to each transistor.