Patent ID: 7710755

Claim:
A dynamic random access memory (DRAM), comprising: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column; a differential amplifier adapted to amplify an input voltage difference (V P −V N ) between a pair of bit lines, wherein a first one of the bit lines is charged to the voltage V P and a second one of the bit lines is charged to the voltage V N , the differential amplifier amplifying the input voltage difference according to a gain G so as to drive an output voltage difference (V PO −V NO ) between a pair of output nodes, wherein a first one of the output nodes is charged to the voltage V PO and a second one of the output nodes is charged to the voltage V NO , the differential amplifier having a non-zero offset bias voltage (ΔV) such that if the input voltage difference is zero, the output voltage difference is non-zero; and a self-bias generation circuit adapted to couple the first output node to the second bit line such that the output voltage V PO equals the input voltage V N and to couple the second output node to the first bit line such that the output voltage V NO equals the input voltage V P , the offset bias voltage ΔV thereby being reduced responsive to the gain G.