Patent ID: 8516228

Claim:
A computer processing system for executing an instruction for performing a first operation and a second operation, the system comprising: a first datastore; a first stage of a processor pipeline coupled to the first datastore; and a second stage of the pipeline, coupled to the first stage of the processor pipeline, the system configured to perform a method comprising: storing, by the processor pipeline, a subset of information to the first datastore based on execution progress of the instruction; and based on a rejection event of the second operation following a successful completion of the first operation initiating, by the second stage of the processor pipeline, a partial reprocessing, the partial reprocessing comprising using the subset of information stored in the first datastore to continue processing the instruction, at the first stage of the pipeline, with the second operation; based on a rejection event of a first occurring operation of the instruction initiating by the second stage of the processor pipeline, full reprocessing, the full reprocessing comprising processing the instruction, at the first stage of the pipeline as a new instruction.