Patent ID: 8903882

Claim:
A method for calculating at least one multiply-sum of two carry-less multiplications of two input operands, the method comprising: using input data busses for said input operands and an output data bus for an overall calculation result, each bus comprising a width of 2n bits, where n is an integer greater than one; calculating, via multiplier circuitry, said carry-less multiplications of said two input operands for a lower level of a hierarchical structure; calculating said at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the hierarchical structure based on said carry-less multiplications of the lower level; in a top level of said hierarchical structure, calculating and outputting a first multiply-sum of two carry-less multiplications of two input operands each comprising a width of n bits by using a bit-wise exclusive OR function; in a first mode of operation, outputting said first multiply-sum as overall calculation result, and in an at least one further mode of operation: calculating 2 k intermediate multiply-sums of two carry-less multiplications of two input operands each comprising a width of n/2 k bits, with k=1, 2, . . . , depending on said further mode of operation, by using exclusive OR functions in sub-levels of said hierarchical structure for summing said multiplications; and outputting said 2 k intermediate multiply-sum results as said overall calculation result.