Patent ID: 8900997

Claim:
A method of forming a dual damascene structure of a semiconductor device, the method comprising: sequentially forming a first insulation layer and a second insulation layer on a substrate; forming a resist mask having a pattern for forming a via hole on the second insulation layer; forming a via hole down to a lower end of the first insulation layer; forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method; forming a resist mask having a pattern for forming a trench hole on the hardmask layer; forming a first trench hole through the resist mask having the pattern for forming the trench hole, the first trench hole being formed down to a lower end of the second insulation layer; respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer; forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole; removing the hardmask layer remaining in the via hole and on the second insulation layer; and forming an upper wire by filling the via hole and the second trench hole with a conductive material.