Patent ID: 7313014

Claim:
A semiconductor integrated circuit device comprising: a plurality of circuit blocks each including a memory cell array in which a plurality of magnetic memory cells is arranged, wherein each of said magnetic memory cells has a magnetic memory element having a plurality of magnetic layers at least one of which is magnetized in the direction in accordance with storage data, and said plurality of magnetic memory cells is arranged so that the easy axis of said magnetic memory element in each of said magnetic memory cell is oriented in the same direction relative to said plurality of circuit blocks; and wherein each of said plurality of circuit blocks includes: a plurality of first data write lines for selectively applying a data write magnetic field along the hard axis of said magnetic memory elements to said plurality of magnetic memory cells; a plurality of second data write lines arranged in the direction crossing said plurality of first data write lines for selectively applying a data write magnetic field along said easy axis to said plurality of magnetic memory cells; a first decoder circuit for making a selection from among said first data write lines; and a second decoder circuit for making a selection from among said second data write lines, and each of said plurality of first data write lines and each of said plurality of second data write lines, respectively, are arranged in the same direction relative to said plurality of circuit blocks; and wherein said magnetic memory element has a form which is point symmetric but is not line symmetric, a first write current flowing in different directions in accordance with a level of write data is selectively supplied to said plurality of first data write lines, a second write current flowing in the fixed direction regardless of said level of write data is selectively supplied to said plurality of second data write lines, and said first and second decoder circuits are arranged so that the direction of said second write current relative to the direction of said first write current at each of said level of write data is oriented to be the same relative to said plurality of circuit blocks.