Patent ID: 8374032

Claim:
A reading method of a non-volatile semiconductor memory device, the memory device including a NAND string which has a plurality of memory cells disposed in series and first and second select gate transistors disposed on the both ends of the memory cells; a plurality of word lines coupled to the respective memory cells; and first and second select gate lines coupled to the first and second select gate transistors, respectively, the method comprising: applying a read voltage to a selected word line; applying a first read pass voltage to one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side of the selected word line while applying a second read pass voltage lower than the first read pass voltage to the others; applying a third read pass voltage higher than the first read voltage to second unselected word lines disposed on the second select gate line side of the selected word line, wherein the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell; and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein the method further comprises applying the second read pass voltage to the first dummy word line while applying the third read pass voltage to the second dummy word line.