Patent ID: 7861197

Claim:
A method of verifying a logic circuit design for a semiconductor device having first, second and third circuit blocks, the first and the second circuit blocks continuously receiving power from a first power supply conductor, and the third circuit block being supplied with power from a second power supply conductor, the power supplied to the third circuit block from the second power supply conductor being turned on/off in response to operation modes of the semiconductor device, comprising: a first process for retrieving a first boundary cell from a storage device and for placing the first boundary cell between the first and the third circuit blocks, the first boundary cell receiving a first signal and outputting a second signal having the same logic level as the first signal to the third circuit block when the power supplied by second power supply is turned on, or outputting the second signal having a low level to the third circuit block when the power supplied by the second power supply conductor is turned off; a second process for retrieving a second boundary cell from the storage device and for placing the second boundary cell between the third and second blocks, the second boundary cell receiving a third signal and outputting a fourth signal to the second circuit block, the fourth signal having the same logic level as the third signal when the power supplied by the second power supply conductor is turned on and a fifth signal having a high level from the second circuit block is applied to the second boundary cell, the fourth signal having a low level when the power supplied by the second power supply conductor is turned off or the fifth signal that is applied to the second boundary cell from the second circuit block has a low level; and a third process for performing a logical simulation of the semiconductor device including the first and second boundary cells among the first through third circuit blocks, respectively, by the first and the second process.