Patent ID: 7050336

Claim:
A nonvolatile semiconductor memory device comprising: a memory block including a plurality of memory transistors arranged in rows and columns, and each having a control gate and a floating gate, a plurality of word lines arranged corresponding to rows of said plurality of memory transistors, respectively, and a plurality of bit lines arranged corresponding to the columns of said plurality of memory cells, respectively; a select circuit selecting an application target of an erase pulse in said memory block; and a write erase control portion controlling data erasing in said memory block when information held by said memory block is to be collectively erased, wherein said collective erasing provides states including: a first erased state attained at a midpoint in a course of the collective erasing, and a second erased state attained after said first erased state, said first and second erased states exhibit a distribution of threshold voltages of said plurality of memory transistors lower than predetermined first and second threshold voltages, respectively, and said write erase control portion instructs said select circuit, to select collectively the memory transistors in said memory block for repetitively applying a first erase pulse until said memory block enters said first erased state, to perform selection such that a write pulse weaker than a write pulse for usual writing is applied to the memory transistor in said memory block after said memory block enters said first erased state, and to perform selection such that said memory block is divided into a plurality of regions, and said regions are successively selected to apply a second erase pulse collectively to each of said regions until said memory block enters said second erased state.