Patent ID: 6917070

Claim:
A structure of single-poly EPROM which is suitable for using as memory cell in a substrate, comprising: an isolation region disposed in the substrate to define a striped active area; a deep well of first conductive type located under the isolation region and the striped active area; a gate oxide layer disposed on the striped active area on the substrate; a pair of selective gates disposed on the gate oxide layer and the isolation region, wherein the pair of selective gates are striped and perpendicular to the striped active area; a pair of floating gates disposed on the gate oxide layer, and are corresponding to the active area, wherein a gap is formed between the pair of floating gates and the pair of selective gates; a well of second conductive type disposed in the deep well of first conductive type below the pair of selective gates and the pair of floating gates; a pair of sources disposed on both sides of the well of second conductive type, the pair of sources connected to each other via the deep well of first conductive type; and a drain disposed in the well of second conductive type between the pair of selective gates.