Patent ID: 8495308

Claim:
A method of data processing in a multiprocessor data processing system including at least first and second coherency domains, wherein the first coherency domain includes at least one processing unit, a system memory and a cache memory, the method comprising: buffering a cache line in a data array of the cache memory; and setting a state field in a cache directory of the cache memory to a coherency state to indicate that: the cache line is valid in the data array, the cache line is held in the cache memory non-exclusively and is unmodified with respect to a corresponding memory block in the system memory, another cache in said second coherency domain may hold a copy of the cache line, and a domain indicator in the first coherency domain, which has a first state indicative of a first scope of coherency communication for the cache line that excludes the second coherency domain and a second state indicative of a second scope of coherency communication for the cache line that includes the second coherency domain, will have to be updated to the second state.