Patent ID: 7694091

Claim:
A non-volatile memory system comprising: flash memory configured as block-accessible non-volatile memory (“NVM”), where the NVM being randomly accessible; random access memory (“RAM”), arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor; the RAM including a first RAM and a second RAM where the processor is configured to treat the first RAM as non-volatile memory; logic separate from the processor and interposed between the block-accessible non-volatile memory and the random access memory without being interposed between the processor and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory; and wherein the logic is arranged to monitor processor writes to the random access memory, and maintain a list of sections of the RAM that have been written to by the processor and not yet written to the NVM, each section constituting a dirty block, and the logic arranged to write a dirty block to the NVM when the number of dirty blocks exceeds a predetermined limit, the predetermined limit being based on the number of sections of the RAM that may be written to the NVM when a power supply to the NVM is lost.