Patent ID: 8258059

Claim:
A method for manufacturing a high voltage-resistant semiconductor device, the method comprising: preparing a silicon substrate having a plurality of transistor forming regions; forming a plurality of transistors by: forming channel regions in a superficial layer region on the transistor forming regions of the semiconductor substrate, forming gate insulating films having film thicknesses greater than about 350 Å on the channel regions, forming gate electrodes on the gate insulating films, and forming source regions and drain regions on both sides of the channel regions; providing contacts on the gate electrodes of the plurality of transistors; and providing multilayer wiring on the contacts; wherein an area ratio, Sc/Sg, associated with at least one of the plurality of transistors differs from area ratios, Sc/Sg, associated with at least another of the plurality of transistors, where Sc is a total opening area of the contacts provided on the gate electrodes of the respective transistor when viewed from a gate electrode side of the respective transistor, and where Sg is a contact area between the gate electrodes and the gate insulating film of the respective transistor.