Patent ID: 8716093

Claim:
A method of manufacturing a semiconductor device comprising: forming a first gate electrode including a gate insulating pattern and a gate conductive pattern that are sequentially stacked on a semiconductor substrate; forming a low dielectric constant layer on a sidewall of the first gate electrode; forming a first impurity junction region on the semiconductor substrate adjacent to a sidewall of the first gate electrode; forming a first spacer on a lower sidewall of the first gate electrode by etching the low dielectric constant layer using the first impurity junction region as an etch stop layer to remove a portion of the low dielectric constant layer to expose an upper part of the sidewall of the first gate electrode; forming a high dielectric constant layer, that is greater than the low dielectric constant, on a top surface of the first spacer and on the upper part of the sidewall of the first gate electrode; and forming a second spacer on the upper part of the sidewall of the first gate electrode by patterning the high dielectric constant layer.