Patent ID: 6922094

Claim:
A data retaining circuit, comprising: a data retaining section that retains the data to be put out; a pull-up path that takes in and retains input data as a pull-up control signal in synchronization with a clock and pulls up the data retained in the data retaining section when the pull-up control signal is one of the values; a pull-down path that takes in and retains input data as a pull-down control signal in synchronization with the clock and pulls down the data retained in the data retaining section when the pull-down control signal is the other value; a pull-up correcting circuit that controls the pull-up control signal according to the pull-down control signal and the data retained in the data retaining section; and a pull-down correcting circuit that controls the pull-down control signal according to the pull-up control signal and the data retained in the data retaining section, wherein the pull-up path is configured so that an error in which the pull-up control signal changes from the other value to the one of the values does not occur, the pull-down path is configured so that an error in which the pull-down control signal changes from the one of the values to the other value does not occur, the pull-up correcting circuit is configured so that the control is terminated when an error occurs in the pull-down control signal or the data retained in the data retaining section, and the pull-down correcting circuit is configured so that the control is terminated when an error occurs in the pull-up control signal or the data retained in the data retaining section.