Patent ID: 7707386

Claim:
A design apparatus for designing a configurable processor for an application, comprising: an analysis unit configured to analyze content of a program to be executed by the configurable processor statically and dynamically in order to output static analysis information as a performance of the target configurable processor using syntax analysis information obtained from program compiled results and dynamic analysis information using profile information generated by a simulation; and an extension instruction definition unit configured to search the program for a part of the program allowing use of an extension instruction by determining whether the performance of the target configurable processor reaches a predetermined target performance by comparing the performance of the target configurable processor with the predetermined target performance of the target configurable processor in accordance with analysis results output by the analysis unit, and to generate a definition of the extension instruction for at least one of the searched part and a user-given part allowing use of the extension instruction by optimizing the instructions described in the program for carrying out a same operation as the program of an extended instruction into a machine language script corresponding to the extended instruction, and the extension instruction definition unit comprising, an extension instruction use determination unit, which determines whether to generate for an extension instruction use candidate block in the program, an extension instruction for a processing equivalent to processing for that block, and an instruction description generation unit, which generates an extension instruction description, which is generated as an instruction set of the configurable processor, for a processing equivalent to processing for that block in accordance with the determination results by the extension instruction use determination unit when the performance of the target configurable processor reaches the predetermined target performance.