Patent ID: 7446748

Claim:
A driving circuit for a flat panel display device, comprising: first and second generation units generating m-phase circulation enable control clocks and n-phase circulation from generation clocks; a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks, each of shift register stages comprising: an input terminal receiving at least one of the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the at least one of the m-phase circulation enable control clocks; a first transistor coupled to the first node and receiving one of the n-phase circulation form generation clocks; a second transistor coupled to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals; and a ground terminal and a voltage source terminal, wherein each of the shift register stages further includes third to at least seventh transistors each having a gate electrode, a source electrode and a drain electrode; wherein the drain electrode of the first transistor receives one of the n-phase circulation form generation clocks and the source electrode of the first transistor is coupled to the drain electrode of the second transistor; the source electrode of the second transistor is connected to the ground terminal; and the gate electrode of the third transistor is coupled to the drain electrode of the fifth transistor, the source electrode of a ninth transistor, the drain electrode of a tenth transistor, the gate electrode of a twelfth transistor and the gate electrode of the second transistor, and the drain electrode of the third transistor is coupled to the ground terminal.