Patent ID: 8488075

Claim:
An active matrix substrate comprising: a plurality of gate lines and a plurality of data lines arranged in a matrix manner: a plurality of pixel electrodes each of which has a first side and a second side, the first side extending in parallel with the plurality of gate lines, the second side extending in parallel with the plurality of data lines and being shorter than the first side; a plurality of storage capacitor lines which are arranged in parallel with the plurality of gate lines; and a plurality of connection lines which are electrically connected with respective of the plurality of pixel electrodes, part of each of the plurality of connection lines overlapping part of each of the plurality of storage capacitor lines via an insulating film so as to form a storage capacitor element, wherein the part of the plurality of storage capacitor lines and the part of each of the plurality of connection lines serve as respective electrodes of the storage capacitor element, the number of the plurality of storage capacitor lines is smaller than that of the plurality of gate lines, each of the plurality of storage capacitor lines overlap some of the plurality of connection lines via the insulating film, the some of the plurality of connection lines are respectively electrically connected with corresponding ones of the plurality of pixel electrodes which are arranged along the plurality of data lines, one of the electrodes included in the storage capacitor element is disposed at least partially on a layer on which a semiconductor layer of each of a plurality of transistors is disposed, the plurality of transistors being provided for respective ones of the plurality of pixel electrodes, the plurality of connection lines are electrically connected with respective drain electrodes of the plurality of transistors which are provided for respective ones of the plurality of pixel electrodes arranged along the plurality of data lines, and a wiring between each of the drain electrodes and the storage capacitor element is at least partially disposed on a layer on which the semiconductor layer is disposed.