Patent ID: 7709299

Claim:
A method of forming a DRAM memory array comprising: providing a plurality of memory cells, providing including: providing two devices for each of the plurality of memory cells, each of said plurality of memory cells having two of said device organized in a row representing a plurality of words and a bit column representing bits of said plurality of words, each said bit column having a true bit line, and a complement bit line, said true bit line and said complement bit line being balanced and connected in a hierarchical bit line structure, said hierarchical bit line structure comprising a local bit line true, a local bit line complement, a global bit line true, a global bit line complement, and a sensing circuit, said sensing circuit connected to said global bit line true and said global bit line complement effectuating detecting of a differential voltage transition on either line during a read access and providing a sensing strobe signal, wherein said two devices are a transistor, nFET, or pFET and wherein said true bit line of a plurality of said bit column are connected directly to said local bit line true, and said complement bit line of a plurality of said bit column are directly connected to said local bit line complement.