Patent ID: 8339861

Claim:
A memory apparatus, comprising: a plurality of memory cells; a plurality of word lines accessing the plurality of memory cells, the plurality of word lines divided into a plurality of erase groups, an erase group from the plurality of erase groups selected by control circuitry responsive to an erase command, the word lines in the erase group including: outer word lines accessing outer memory cells in the erase group; and inner word lines accessing inner memory cells in the erase group, the inner memory cells bounded by the outer memory cells of the erase group from memory cells accessed by word lines of unselected erase groups of the plurality of erase groups, wherein at least one of the outer word lines is adjacent to at least one of the word lines of the unselected erase groups, said at least one of the word lines accessing memory cells storing data in regular operation of the memory apparatus; and the control circuitry performing an erase operation on memory cells accessed by word lines in the erase group, wherein the erase operation includes a first erase verify sub-operation performed on the inner word lines in the erase group, prior to a second erase verify sub-operation performed on the outer word lines in the erase group.