Patent ID: 7233542

Claim:
Circuitry for generating a common address signal for multi-port memory arrays, the multi-port memory array including a first sub-array and a second sub-array, the circuitry comprising: a clock generation circuit, the clock generation circuit generating a write sample clock to enable a write to both the first sub-array and the second sub-array, a first read sample clock to enable a read from the first sub-array and a second read sample clock to enable a read from the second sub-array, the clock generation circuit excluding generation of the first read sample clock and the second read sample clock when the write sample clock is active; and one or more first level decoding circuits including: first decoding circuitry receiving the write sample clock, a write address, the first read sample clock and a read address, the first decoding circuit generating a write address on a first address line for both the first sub-array and the second sub-array when the write sample clock is enabled, the first decoding circuit generating a read address on the first address line for one of the first sub-array and the second sub-array when the read sample clock is enabled.