Patent ID: 7184291

Claim:
A memory array architecture comprising: a substrate having a first polarity and including a plurality of shallow trench isolation areas arranged substantially continuously along a first direction; a plurality of conductive word lines arranged along a second direction transverse to said first direction, said word lines being isolated from the substrate at least partially by a trapping dielectric, wherein regions of said substrate between adjacent word lines are implanted with an impurity having a second polarity, thereby producing a plurality of source/drain regions bounded by said trench isolations in said second direction, said source/drain regions being arranged in alternating odd and even numbered columns along said first direction and in alternating odd and even numbered rows along said second direction; a plurality of conductive jumper connections substantially above said trench isolation areas electrically connecting pairs of said source/drain regions, each pair of source/drain regions in an even-numbered row connecting a source/drain region in an even-numbered column and an adjacent source/drain region in a subsequent odd-numbered column, and each pair of source/drain regions in an odd-numbered row connecting a source/drain region in an odd-numbered column and an adjacent source/drain region in a subsequent even-numbered column; and a plurality of conductive bit lines arranged along said first direction above said jumper connections, each of said bit lines connecting a plurality of jumper connections in either even-numbered or odd-numbered of said rows.