Patent ID: 7158600

Claim:
A phase locked loop circuit, comprising: a phase detector receiving two clock signals and outputting a control signal indicative of a frequency mismatch between the two clock signals; an active filter for generating an output responsive to a change on an input node; a charge pump sinking or sourcing current to the input node responsive to the control signal from said phase detector; a voltage controlled oscillator for generating an output frequency responsive to an output of said active filter; and wherein said charge pump includes: a transmission gate for selectively providing either a high impedance state to prevent the charge pump from charging the input node or a low impedance state to allow the charge pump to charge the input node; and control circuitry for controlling the state of the transmission gate responsive to the control signal such that the transmission gate is in a high impedance state to electrically isolate the charge pump from said filter during periods when the control signal is inactive and not causing the charge pump to sink or source current to the input node.