Patent ID: 7692997

Claim:
A semiconductor integrated circuit device having a first operating mode, a second operating mode and a third operating mode comprising; an external terminal to receive a supply voltage; a first step down circuit to generate an internal voltage lower than the supply voltage, and to output the internal voltage to an output terminal during the first, the second and the third operating modes; a second step down circuit to receive the supply voltage through the external terminal, to generate the internal voltage, to output the internal voltage to the output terminal during the first and the second operating modes, and not to supply the internal voltage to the output terminal during the third operating mode; a third step down circuit to receive the supply voltage through the external terminal, to generate the internal voltage, to output the internal voltage to the output terminal during the first operating mode, and not to supply the internal voltage to the output terminal during the second and the third operating modes; and a CPU coupled to the output terminal, wherein the CPU executes a program in the first operating mode and the CPU executes a first sleep instruction to transfer to the second operating mode, wherein a consumption current of the semiconductor integrated circuit device in the first operating mode is higher than a consumption current in the second operating mode, and wherein the consumption current of the semiconductor integrated circuit device in the second operating mode is higher than a consumption current in the third operating mode.