Patent ID: 8324040

Claim:
A method for fabricating a semiconductor device comprising: forming an n-channel MISFET including source/drain regions formed in a semiconductor substrate and a first gate electrode of a polycrystalline silicon formed over the silicon substrate; forming a first insulating film over the semiconductor substrate and the n-channel MISFET, wherein thickness of the first insulating film on the first gate electrode is thinner than thickness of the first insulating film on the source/drain regions; etching the first insulating film to expose the gate electrode, while the first insulating film remains on the source/drain regions; substituting the polycrystalline silicon forming the first gate electrode into a metal silicide; and forming a second insulating film over the first gate electrode from side walls of the first gate electrode to an upper surface of the first gate electrode and having a tensile stress from 1.0 to 2.0 GPa.