Patent ID: 7256530

Claim:
A drive circuit for a piezoelectric transformer having a pair of primary electrodes and a secondary electrode for stepping up an AC voltage applied to the pair of primary electrodes and outputting a resultant voltage from the secondary electrode, the drive circuit comprising: a first power supply side transistor and a first ground side transistor connected in series between an input power supply and ground potential and arranged to output a voltage that is applied to a first primary electrode of the pair of primary electrodes of the piezoelectric transformer; a second power supply side transistor and a second ground side transistor connected in series between the input power supply and ground potential and arranged to output a voltage that is applied to a second primary electrode of the pair of primary electrodes of the piezoelectric transformer; an inductor interposed between the first primary electrode and a mid-point between the first power supply side transistor and the first ground side transistor; a tube current detection circuit that is arranged to detect a signal indicating a condition of a load that is connected to the secondary electrode; a first error amplifier that is arranged to compare an output voltage of the tube current detection circuit and a first error reference voltage; a voltage controlled oscillator that is arranged to be controlled by an output voltage of the first error amplifier and that outputs an oscillation clock of a reference period and a triangular wave signal synchronized therewith; an applied voltage detector that is arranged to produce a voltage corresponding to an amplitude of the voltage that is applied to at least one of the pair of primary electrodes; a second error amplifier that is arranged to compare the voltage output by the applied voltage detector and a second error reference voltage; a PWM comparator that is arranged to compare an output voltage of the second error amplifier and the triangular wave signal to output a PWM signal; and a frequency divider that outputs a signal having a polarity that is changed every reference period; wherein an on time of the PWM signal is a time during which both the first power supply side transistor and the second ground side transistor are on or a time during which both the second power supply side transistor and the first ground side transistor are on; and the first power supply side transistor, the first ground side transistor, the second power supply side transistor and the second ground side transistor are arranged to be controlled by the output signal of the frequency divider such that the time during which both the first power supply side transistor and the second ground side transistor are on and the time during which both the second power supply side transistor and the first ground side transistor are on are generated alternately in each period of the reference period.