Patent ID: 8878829

Claim:
A common electrode drive circuit for driving a liquid crystal display in a Multi-Level Gate method, comprising: a plurality of output terminals connected to a plurality of common voltage input terminals of a common electrode layer of the liquid crystal display and adapted for inputting common voltages into the plurality of common voltage input terminals, the common electrode layer driving liquid crystal together with pixel electrodes of the liquid crystal display, wherein the common voltages input by the plurality of output terminals decrease gradually from a data-line beginning end for data signal input to a data-line tail end for data signal input of the liquid crystal display; wherein the plurality of output terminals comprise: a first output terminal connected to a first common voltage input terminal of the common electrode layer and applying a first common voltage to the first common voltage input terminal, wherein the first common voltage input terminal is adjacent to a crossing point of the data-line beginning end for data signal input and the gate-line tail end for gate signal input; a second output terminal connected to a second common voltage input terminal of the common electrode layer and applying a second common voltage to the second common voltage input terminal that is smaller than the first common voltage, wherein the second common voltage input terminal is adjacent to a crossing point of the data-line tail end for data signal input and the gate-line beginning end for gate signal input; a third output terminal connected to a third common voltage input terminal of the common electrode layer and applying a third common voltage to the third common voltage input terminal, wherein the third common voltage input terminal is adjacent to a crossing point of the data-line beginning end for data signal input and the gate-line beginning end for gate signal input; a fourth output terminal connected to a fourth common voltage input terminal of the common electrode layer and applying a fourth common voltage to the fourth common voltage input terminal, wherein the fourth common voltage input terminal is adjacent to a crossing point of the data-line tail end for data signal input and the gate-line tail end for gate signal input; and wherein the third common voltage and the fourth common voltage are both larger than the second common voltage and smaller than the first common voltage, and the third common voltage is smaller than the fourth common voltage.