Patent ID: 8492826

Claim:
A non-volatile semiconductor device having a memory cell formed on an n type well formed in a semiconductor substrate, comprising: a first p-type diffusion region formed on a surface of the n type well; a second p-type diffusion region formed on the surface of the n type well, a channel region being interposed between the first p-type diffusion region and the second p-type diffusion region; a tunnel insulation film formed on the channel region; a floating gate formed on the tunnel insulation film; an insulation film formed on the floating gate; a gate electrode formed on the insulation film; and a metal wire connected to the first p-type diffusion region, the metal wire intersecting with an extension of the gate electrode; wherein the first p-type diffusion region and the second p-type diffusion region are asymmetrically arranged such that (i) a junction depth of the first p-type diffusion region and a junction depth of the second p-type diffusion region are different; or (ii) a first shape of the first p-type diffusion region and a second shape of the second p-type diffusion region are different; and such that a first resistivity of the first p-type diffusion region is lower than a second resistivity of the second p-type diffusion region; and wherein the device is configured such that a gate read voltage Vgr is applied to the gate electrode when the memory cell is selected for reading during a read operation, and an unselected gate read voltage uVgr is applied to the gate electrode when the memory cell is not selected for the reading during the read operation, and Vgr is lower than uVgr.