Patent ID: 8667441

Claim:
A method, in a data processing system, for clock optimization with local clock buffer control optimization, the method comprising: receiving, by the data processing system, an integrated circuit design, wherein the integrated circuit design has at least one local clock buffer and wherein local clock buffer control signals to the at least one local clock buffer are hidden in the integrated circuit design; cloning, by the data processing system, the at least one local clock buffer in the integrated circuit design to generate a plurality of local clock buffers in the integrated circuit design; performing, by the data processing system, latch clustering to associate latches in the integrated circuit design with respective ones of the plurality of local clock buffers; responsive to performing latch clustering, exposing, by the data processing system, the local clock buffer control signals in the integrated circuit design; and performing, by the data processing system, local clock buffer control optimization to optimize paths of the local clock buffer control signals that drive the plurality of local clock buffers in the integrated circuit design to form an optimized integrated circuit design.