Patent ID: 8877638

Claim:
A method for fabricating an integrated circuit, comprising the steps of: providing a semiconductor substrate; forming a TSV passing through the substrate, the substrate having an exclusion zone laterally adjacent to the TSV; forming first, second and third diffusion regions simultaneously in the substrate, the first diffusion region being disposed at least partially within the exclusion zone and the second and third diffusion regions being disposed outside the exclusion zone, the first, second and third diffusion regions being doped to exhibit a first conductivity type, the substrate in at least a region adjacent to the first region being doped to exhibit a second conductivity type opposite the first conductivity type; forming a gate dielectric over the substrate and a gate conductor over the gate dielectric, the second and third diffusion regions, the gate conductor and the gate dielectric all forming parts of a transistor; and forming an M1 layer conductor interconnecting the TSV, the first diffusion region, and the gate conductor.