Patent ID: 7822881

Claim:
A method of processing data in a packet-wise manner using (a) an array of elements configurable with respect to function and interconnection, said array being at least two dimensional and having at least some elements that comprise arithmetic-logic units, and (b) a memory arrangement comprising at least one reading pointer separate from at least one writing pointer, said method comprising the steps of: processing, with a plurality of said configurable elements, data comprising at least a first packet of data to ascertain a first packet of result data; writing the first packet of result data into a memory block, said memory block being part of the memory arrangement and said at least one writing pointer being positioned so as to allow writing into a memory area of said memory block; and subsequent to the processing: reconfiguring at least one of a first group of at least some of the plurality of said configurable elements, wherein the reconfiguring includes using a configuration data from the memory arrangement, the configuration data being provided only for said first group of at least some of the plurality of said configurable elements, while retaining a configuration of at least one other of the plurality of said configurable elements; reading out result data of the first packet of result data from the memory after reconfiguration of said at least some of the plurality of said configurable elements in accordance with the position of the reading pointer, said reading pointer being positioned so as to allow reading undisturbed by writing of packet data into said memory arrangement; and using the reconfigured at least some of the plurality of said configurable elements to process the result data of the first packet of result data in order to obtain second result data.