Patent ID: 7506290

Claim:
A system for performing verification of a design, said system comprising: a processor; and data storage that contains program code and that is coupled to the processor, wherein the program code, when conveyed to and processed by the processor, causes the system to: receive a design; determine a number of simulation cycles necessary to simulate said design for verification; build for said design an intermediate binary decision diagram set containing one or more nodes representing one or more variables; initialize a plurality of registers associated with said design with initial values responsive to building said intermediate binary decision set; create a binary decision diagram variable for each input to said design; perform verification of said design by evaluating a property of said intermediate binary decision diagram; build for said design a subsequent intermediate binary decision diagram set containing one or more nodes representing one or more variables; updated said plurality of registers with a set of next state function values; case split upon a first fattest variable from among said one or more variables represented by said one or more nodes by setting said first fattest variable to a first value; first cofactor said intermediate binary decision diagram set with respect to said one or more nodes using an inverse of said first value to generate a first cofactored binary decision diagram set; second cofactor said intermediate binary decision diagram set with respect to said one or more nodes using said first value to generate a second cofactored binary decision diagram set; repeat said building for said design said subsequent intermediate binary decision diagram set responsive to determining at least one simulation cycle remains; and output results of said verification responsive to determining that at least one simulation cycle does not remain.