Patent ID: 8431968

Claim:
A semiconductor integrated circuit comprising: a plurality of standard cells having substantially the same size in at least one dimension and arranged in a plurality of substantially parallel rows; said standard cells comprising first standard cells, and target standard cells that operate at higher power consumption levels than said first standard cells; power and ground wires disposed over said standard cells; lower conductive lines formed of a lower metal layer and extending along respective boundaries between adjacent rows of said plurality of substantially parallel rows and coupling each of said standard cells to said power and ground wires; and upper conductive lines formed of an upper metal layer, each said target standard cell further coupled to said power and ground wires by at least one said upper conductive line, said upper conductive lines not present in regions between said power and ground wires that do not contain at least one said target standard cell; said lower and upper metal layers separated from one another by at least a dielectric.