Patent ID: 8139370

Claim:
An electronic system comprising: a plurality of field effect transistor (FET) cells, each FET cell further comprising: a plurality of FETs, each comprising terminals, wherein the plurality of FETs are located on a semiconductor substrate; a direct current (DC) block on the semiconductor substrate; a gate interconnect bump on the semiconductor substrate; a source interconnect bump on the semiconductor substrate; a drain interconnect bump on the semiconductor substrate, wherein the gate, source and drain interconnect bumps are configured to flip-chip connect the plurality of FET cells to a printed circuit board (PCB) substrate; and a stability circuit, wherein the stability circuit is in communication with each of the gate, and drain interconnect bumps; wherein the stability circuit further comprises a gate stability circuit; the PCB substrate comprising a matching structure in communication with at least one of the gate interconnect bump or drain interconnect bump, wherein the matching structure on the PCB substrate comprises distributed matching elements; and wherein at least two of the plurality of FET cells are connected in parallel to form parallel FET cells, and wherein the parallel FET cells comprise daisy chained gate bias interconnections between the two FET cells.