Patent ID: 6957403

Claim:
A method of performing scan synthesis for inserting scan cells and test points at RTL (register-transfer level) in an integrated circuit modeled at RTL, the integrated circuit having a plurality of clock domains and each domain having one scan clock; said method comprising computer-implemented steps of: (a) compiling HDL (hardware description language) code that represents said integrated circuit at RTL into a design database; (b) receiving scan constraints from an external source, said scan constraints further comprising a list of scan clocks to be minimized and ordered; (c) performing RTL testability analysis for checking whether said design database contains any scan rule violation; (d) performing clock-domain minimization for generating an optimal number of scan clocks to test said integrated circuit; (e) performing scan selection for selecting a plurality of storage elements according to said scan clocks and scan constraints; (f) performing test point selection for selecting a plurality of test points according to said scan clocks and said scan constraints; (g) performing scan repair for repairing all said scan rule violations and inserting said selected test points into said design database; (h) performing scan replacement and scan stitching for replacing said selected storage elements and said selected test points with scan cells and stitching said scan cells together as a plurality of scan chains according to said scan clocks and said scan constraints; (i) generating scan HDL code at RTL; and (j) generating HDL test benches for verifying the correctness of said scan HDL code.