Patent ID: 7259467

Claim:
A semiconductor integrated circuit device comprising: a semiconductor chip having first wire bonding pads arranged at a periphery of a semiconductor integrated circuit unit; and a package encapsulating the semiconductor chip and having second wire bonding pads connected via bonding wires to the first wire bonding pads, wherein the first wire bonding pads comprise signal pads and power supply pads, and are arranged in a plurality of rows along a periphery of the semiconductor chip, and power supply pads of the first wire bonding pads for supplying power to the semiconductor integrated circuit unit are disposed in the innermost of the plurality of rows, and wherein the second wire bonding pads comprise signal pads and power supply pads, and are arranged in a plurality of rows along a periphery of the package, and power supply pads of the second wire bonding pads for supplying power to the semiconductor chip are disposed in the innermost of the plurality of rows, wherein each of the first and second wire bonding pads are arranged in the plurality of rows in a staggered manner, and wherein the power supply pads on the semiconductor chip are disposed adjacent to each other, and an outer edge of an NC pad not connected to any line is disposed outwardly with respect to an outer edge of the power supply pads of the semiconductor chip between two adjacent power supply pads.