Patent ID: 7514954

Claim:
A memory device, comprising: a memory array; at least one adjustable output driver coupled between the memory array and at least one interface terminal; and an output driver calibration circuit configured to adjust an impedance of the at least one adjustable output driver, the output driver calibration circuit including: a pull-up calibration circuit including a first comparator configured to compare a reference voltage to a first voltage at a calibration terminal when an external load is connected thereto, the pull-up calibration circuit further comprising a first reconfigurable counter configured to generate a first variable count in response to the comparator and a first variable pull-up impedance circuit responsive to the first variable count, the first variable pull-up impedance coupled to the calibration terminal; and a pull-down calibration circuit including a second variable pull-up impedance circuit concurrently responsive to the first variable count and a variable pull-down impedance circuit serially coupled at a reference node to the second variable pull-up impedance circuit, the pull-down calibration circuit further including a second comparator configured to compare the reference voltage to a second voltage at the reference node and a second reconfigurable counter configured to generate a second variable count in response to the second comparator, the variable pull-down impedance circuit responsive to the second variable count.