Patent ID: 7504695

Claim:
An SRAM memory cell comprising: first and second memory nodes, each formed between complementary transistors of cross-coupled inverters; a first bit line; a first transistor, wherein the source and drain of the first transistor are connected to the first bit line and the first memory node, respectively, such that a larger leakage current flows from the first bit line to the first memory node across the first transistor when a first logic state is stored in the first memory node than when a second logic state is stored in the first memory node; a second transistor, wherein the source and drain of the second transistor are connected to the first bit line and the second memory node respectively, such that a smaller leakage current flows from the first bit line to the second memory node across the second transistor when a first logic state is stored in the second memory node than when a second logic state is stored in the second memory mode; and a third transistor, wherein a source and drain of the third transistor are connected to a second bit line and the second memory node of the memory cell, respectively, wherein the second bit line is complementary to the first bit line, and wherein a gate of the third transistor is connected to a second word line, and wherein the memory cell is capable of performing differential writes using the first transistor and the third transistor.