Patent ID: 8145852

Claim:
A digital processing device, comprising: n processors, n being a natural number and the same as or larger than 2; and a shared memory, coupled to the n processors through separate buses, respectively, having a storage area including m common sections, m being a natural number, and generating and outputting access status information related to whether an arbitrary processor accesses at least one of the m common sections, the access status information identifying what type of access is being performed by the arbitrary processor, wherein a common section refers to the storage area that can be individually accessed by k processors during a non-coinciding period of time, k being a natural number and 2≦k≦n, the processors comprise a main processor and n−1 application processors, coupled to the main processor through separate control buses, respectively, each application processor performing a process according to a control signal inputted through a control bus, a first application processor of the n−1 application processors which has received the control signal, reads data which had been written by the main processor in a first common section of the m common sections, the shared memory comprises at least one access status information pin independently corresponding to each processor, and the access status information is outputted through the at least one access status information pin, the access status information comprises at least one of reading status information and writing status information, and the writing status information indicating that the first application processor is accessing the first common section to write data, and the reading status information indicating that the first application processor is accessing the first common section to read data.