Patent ID: 8812921

Claim:
An integrated circuit comprising: scan test circuitry; and additional circuitry subject to testing utilizing the scan test circuitry; the scan test circuitry comprising at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, wherein the plurality of sub-chains are connected in series with each other; the scan test circuitry further comprising clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains; wherein the scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode; wherein the clock domain bypass circuitry is configured to bypass one or more of the sub-chains that are determined to be inactive in a capture phase of a particular test pattern; and wherein a given sub-chain is determined to be inactive if its corresponding clock domain remains inactive during the capture phase.