Patent ID: 7360185

Claim:
A method for verifying a design model of an integrated circuit, comprising: performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit; unfolding the simplified sequential model for N time steps to produce a combinational model of the integrated circuit; performing a sequence of at least one combinational transformation on the combinational model to produce a simplified combinational model; and performing an exhaustive search of states of the simplified combinational model, wherein performing the exhaustive search comprises performing an exhaustive satisfiability search, and wherein the exhaustive satisfiability search includes propagating a binary decision diagram (BDD) through a net list; and storing a result of the verifying process in response to i) performing a predetermined number of iterations of the verifying process, or else ii) the verifying process encountering a cheekstop or not new states.