Patent ID: 7570094

Claim:
A duty cycle correcting circuit comprising: a duty cycle adjuster circuit having a clock input, a pull-down bias input, a pull-up bias input, and a compensated output; a first dual-slope integrator having a clock input and a bias output coupled to the pull-up bias input of the duty cycle adjuster circuit; a second dual-slope integrator having a clock input and a bias output coupled to the pull-down bias input of the duty cycle adjuster circuit; and an output inverter circuit having an input coupled to the compensated output of the duty cycle adjuster circuit, a first output coupled to the clock input of the first dual-slope integrator circuit, and a second output coupled to the clock input of the second dual-slope integrator circuit and for providing a duty cycle compensated output clock signal, wherein the duty cycle adjust circuit comprises: a first transistor having a gate coupled to the pull-up bias input, and a current path; a second transistor having a gate coupled to the pull-up bias input, and a current path; a third transistor having a gate coupled to the clock input, and a current path; a fourth transistor having a gate coupled to the pull-down bias input, and a current path; a fifth transistor having a gate and drain coupled to the drain of the first transistor, and a current path; a sixth transistor having a gate coupled to the gate of the fifth transistor and the drain of the first transistor, and a current path; and an inverter having an input coupled to the drains of the third and sixth transistors, and an output coupled to the compensated output, wherein the current paths of the first and second transistors are coupled between the drain of the fifth transistor and ground, and the current paths of the third and fourth transistors are coupled between the drain of the sixth transistor and ground.