Patent ID: 8595538

Claim:
A clock generator circuit comprising: a phase locked loop (PLL) responsive to a reference frequency and operative to generate a final output based on the reference frequency, the PLL further being operative to generate a single clock frequency, the final output having a frequency that is a fraction of the frequency of said single clock frequency, said PLL including a single voltage controlled oscillator (VCO) that generates said single clock frequency; and a plurality of dividers, a first divider of which is responsive to said single clock frequency and operative to generate multiple clock frequencies, each clock frequency, of the multiple clock frequencies, being a unique frequency relative to the other clock frequencies of the multiple clock frequencies, a fourth divider of the plurality of dividers operative to generate the final output that is substantially synchronized in at least frequency with said reference frequency, wherein said plurality of dividers includes the first divider responsive to said single clock frequency and operative to divide the same by a first integer value to generate a first divider output, and further includes a second divider responsive to said first divider output and operative to divide the same by a second integer value to generate a second divider output, and further includes a third divider responsive to said second divider output and operative to divide the same by a third integer value to generate a quadrature and in-phase output effectively equivalent to dividing said single clock frequency by an integer value, further wherein said first divider is responsive to said single clock frequency and operative to generate a clock signal quadrature output frequency and a clock signal in-phase output frequency.