Patent ID: 8495542

Claim:
A method comprising: issuing, via a design verification tool, a request to perform a verification run on a component of an electric circuit design; receiving, at said design verification tool and in response to an issuance of said request, configuration data specifying a list of waivers extracted from a plurality of waivers applicable to said electric circuit design as a whole, wherein said list of waivers is extracted based upon waiver validity period data specifying at least one of a waiver expiration date and a waiver grant date, and said list of waivers is applicable to said component of said electric circuit design rather than said electric circuit design as a whole; identifying, utilizing said design verification tool, a potential design defect of said component of said electric circuit design; and generating a verification run result including a set of design defects of said component of said electric circuit design, wherein said set of design defects includes said potential design defect in response to a determination that no waiver of said list of waivers is applicable to said potential design defect, and said set of design defects excludes said potential design defect in response to a determination that at least one waiver of said list of waivers is applicable to said potential design defect.