Patent ID: 6845040

Claim:
A nonvolatile memory comprising: a decoding circuit for selecting one of a plurality of word lines by decoding an address signal; a memory cell array provided with nonvolatile memory cells in each location of intersection between said plurality of word lines and intersecting bit lines for holding storage data by electrical charge accumulated in a floating gate; a high voltage application circuit for supplying a high voltage during rewriting of the stored data in the nonvolatile memory cells; and a storage circuit for storing set information for each of said plurality of word lines indicative of whether or not the nonvolatile memory cells which are connected to each of the word lines may be rewritten, said high voltage application circuit comprising a latch portion for holding information for each of said plurality of word lines indicative of whether or not the nonvolatile memory cells which are connected to each of the word lines are to be rewritten, a setting portion, wherein when a selection signal is outputted from said decoding circuit to a word line for which set information indicating that rewriting is permissible has been set in said storage circuit, sets the information in the latch portion which corresponds to the word line, and when a security write signal is applied, the information is settable in the latch portion corresponding to the word line selected in said decoding circuit regardless of the set information in said storage circuit, and an output portion for supplying a high voltage to the nonvolatile memory cells connected to said word line in accordance with the information held in said latch portion during rewriting of said nonvolatile memory cells.