Patent ID: 8261042

Claim:
A coarse grain reconfigurable signal processing device adapted for simultaneous processing of at least two process threads in a multiprocessing manner, the device comprising: a plurality of functional units capable of executing word- and subword-level operations on data; routing resources for interconnecting the plurality of functional units, the routing resources supporting a plurality of dynamically switchable interconnect arrangements, at least one of the interconnect arrangements interconnecting the plurality of functional units into at least two non-overlapping partitions each with a pre-determined topology, each of the partitions or a combination of partitions being configured to process a respective one of the process threads, each of the partitions comprising two or more of the functional units; a plurality of configurations being stored in the coarse grain reconfigurable signal processing device, wherein the configurations control the behavior of the coarse grain reconfigurable signal processing device by selecting operations and by controlling the routing resources, wherein each of the dynamically switchable interconnect arrangements is selectable by loading a corresponding one of the configurations; and at least two control modules, each control module being assigned to one of the partitions for control thereof.