Patent ID: 8581890

Claim:
A flat display, comprising: a first pixel row and a second pixel row disposed adjacent to each other, wherein the first pixel row comprises a first pixel and a second pixel, and the second pixel row comprises a third pixel and a fourth pixel; a first gate line and a second gate line disposed adjacent to each other, wherein the first pixel row is disposed between the first gate line and the second gate line, the first gate line is electrically coupled to the first pixel in the first pixel row, and the second gate line is electrically coupled to the second pixel in the first pixel row; a third gate line and a fourth gate line disposed adjacent to each other, wherein the third gate line is electrically coupled to the third pixel in the second pixel row, the fourth gate line is electrically coupled to the fourth pixel in the second pixel row, and the second gate line is disposed between the first gate line and the third gate line; and a gate driving circuit comprising sequentially a first stage, a second stage, a third stage and a fourth stage of cascade coupling, wherein the first stage has a first output line connecting to the first gate line, the second stage has a second output line connecting to the third gate line, the third stage has a third output line connecting to the second gate line, and the fourth stage has a fourth output line connecting to the fourth gate line, wherein the first stage generates a first gate driving pulse during a first time slot and a second time slot, the second stage generates a third gate driving pulse during the second time slot and a third time slot, the third stage generates a second gate driving pulse during the third time slot and a fourth time slot, the fourth stage generates a fourth gate driving pulse during the fourth time slot and a fifth time slot, and the first time slot, the second time slot, the third time slot, the fourth time slot and the fifth time slot are sequential and consecutive.