Patent ID: 7075472

Claim:
An averaging analog-to-digital converter comprising: one or more first stage comparators for generating 2 K first stage comparator digital outputs, and 2 K first stage comparator analog outputs upon comparing a voltage input with a set of voltage references; a switch network for selectively controlling the first stage comparator analog outputs to pass; a ratio capacitor network shared by the first stage comparators for receiving the first stage comparator analog outputs and providing 2 L number of intermediate analog outputs for identifying a predetermined level of the voltage input among 2 L of intermediate voltage levels between two predetermined voltage references; 2 L number of second stage comparators for outputting 2 L number of second stage comparator digital outputs; and a decoder subsystem for receiving the second stage comparator digital outputs to produce L bits of least significant bits (LSB), wherein more than two first stage comparators are grouped to share the ratio capacitor network.