Patent ID: 7928435

Claim:
An interposer chip comprising: an insulating substrate; a plurality of conductive patterns on the insulating substrate and configured to connect to a plurality of conductive wires; and a test pattern connected to the plurality of conductive patterns to allow a test current to flow from at least one of the conductive patterns among the plurality of conductive patterns through the test pattern, wherein each of the conductive patterns among the plurality of conductive patterns comprises a pair of contact pads on the insulating substrate, each contact pad being configured to connect to a conductive wire, and a conductive line connecting the pair of contact pads, the plurality of conductive patterns includes a first contact pad and a second contact pad and a first conductive line connecting the first contact pad to the second contact pad, and the test pattern includes a test line connected to the first conductive line, the test line connecting to the first conductive line in a region of the first conductive line between the first contact pad and the second contact pad, the test line being configured to connect to a tester.