Patent ID: 7042263

Claim:
An integrated circuit comprising: a phase-locked loop configured to provide a first synchronizing signal, the first synchronizing signal having a first frequency; a counter configured to receive the first synchronizing signal and provide a plurality of synchronizing signals, each of the signals in the plurality of synchronizing signals having a frequency; a first synthesizer circuit configured to receive the plurality of synchronizing signals and provide a second synchronizing signal, the second synchronizing signal having a second frequency; and a second synthesizer circuit configured to receive the plurality of synchronizing signals and provide a third synchronizing signal, the third synchronizing signal having a frequency switchable between the second frequency and a third frequency; and wherein the first synthesis circuit comprises: a first storage circuit configured to receive a first input; a second storage circuit configured to receive a second input; and a selection circuit configured to select between an output of the first storage circuit and an output of the second storage circuit and further configured to provide the second synchronizing signal.