Patent ID: 8339836

Claim:
A semiconductor device comprising: a plurality of source-bit lines extended in a first direction; a plurality of first signal lines extended in the first direction; a plurality of second signal lines extended in a second direction; a plurality of word lines extended in the second direction; a plurality of memory cells connected in parallel between the plurality of source-bit lines; a first driver circuit electrically connected to the plurality of source-bit lines; a second driver circuit electrically connected to the plurality of first signal lines; a third driver circuit electrically connected to the plurality of second signal lines; and a fourth driver circuit electrically connected to the plurality of word lines, wherein one of the plurality of memory cells comprises: a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode; a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and a capacitor, wherein the second transistor includes an oxide semiconductor material, wherein the first gate electrode, one of the second source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another, wherein one of the plurality of source-bit lines and the first source electrode are electrically connected to each other, wherein another of the plurality of source-bit lines adjacent to the one of the plurality of source-bit lines and the first drain electrode are electrically connected to each other, wherein one of the plurality of first signal lines and the other of the second source and drain electrodes are electrically connected to each other, wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, and wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other.