Patent ID: 7227187

Claim:
A semiconductor device, comprising: an insulating substrate; first and second islands-shaped polycrystalline silicon layers provided above the insulating substrate and having relatively large grain sizes; a third islands-shaped polycrystalline silicon layer provided above the insulating substrate and having relatively small grain sizes; a first gate insulating film provided on the first islands-shaped polycrystalline silicon layer and having a first thickness; a second gate insulating film provided on the second islands-shaped polycrystalline silicon layer and having a second thickness which is greater than the first thickness; a third gate insulating film provided on the third islands-shaped polycrystalline silicon layer and having a third thickness which is greater than the first thickness; first, second, and third gate electrodes provided on the first, second, and third gate insulating films to define first, second, and third channel regions therebelow; first, second, and third n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside the first, second, and third channel regions; and second and third n-type low-concentration source/drain regions provided between the second and third channel regions and the second and third n-type high-concentration source/drain regions, the second and third n-type low-concentration source/drain regions having a lower n-type impurity dose than the n-type high-concentration source/drain regions, wherein the third n-type low-concentration source/drain regions have a higher n-type impurity dose than the second n-type low-concentration source/drain regions.