Patent ID: 6898723

Claim:
A method for verifying a clock signal frequency of a sound interface installed in a computer system, the computer system comprises a main memory for storing sound data, a Direct Memory Access (DMA) controller having at least one DMA channel for performing a DMA data transfer which transfers the sound data from the main memory to the sound interface, a status register having a terminal count bit, and a clock signal generator for supplying a clock signal to the sound interface, the method comprising the following steps: (a) initializing and setting the Direct Memory Access controller of the computer system and the sound interface to start the DMA data transfer; (b) resetting a time out counter; (c) incrementing the time out counter to get a current count during the DMA data transfer; (d) checking whether the DMA channel of the Direct Memory Access controller reaches a terminal count condition by checking the terminal count bit of the status register of the Direct Memory Access controller; (e) if negative in step (d), further checking if the DMA data transfer is time out, and going back to step (c) if it is not time out, otherwise issuing a time out message if it is time out; and (f) if positive in step (d), further checking if the current count recorded in the time out counter is between a maximum tolerable count and a minimum tolerable count, and issuing a message indicating the clock signal frequency is correct if the current count is between the maximum tolerable count and the minimum tolerable count, otherwise issuing a message indicating the clock signal frequency is incorrect if the current count is not between the maximum tolerable count and the minimum tolerable count.