Patent ID: 8263440

Claim:
A method for fabricating one side contact of a vertical transistor, comprising: forming wall bodies on a semiconductor substrate, wherein each wall body comprises an active region, with a first trench in between adjacent wall bodies; forming a first liner on wall surfaces of the wall bodies; filling the first trench with a sacrificial layer; forming a second trench by recessing the first liner and the sacrificial layer, so that an upper portion of the first liner is exposed to a bottom edge portion of the second trench; forming an etching barrier by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein a first of two bottom edge portions of the trench is selectively covered by the etching barrier, and wherein the deposition is performed such that a second of the two bottom edge portions is not covered by the etching barrier due to a shadow effect by upper portions of the wall bodies; removing the first liner positioned at the edge portion not covered by the etching barrier; partially exposing the active region by selectively etching lower sidewalls of the wall bodies to form a groove, which is formed between the sacrificial and the wall bodies by the removal of the first liner, as a passage; and forming a bit line contacting the exposed active region.