Patent ID: 8839058

Claim:
A memory testing apparatus comprising: an input to receive data from one or more memory devices of a plurality of memory devices, each memory device of the plurality of memory devices having: a differential serializer output including a first serializer node and a second serializer node, and a differential deserializer input including a first deserializer node and a second deserializer node, wherein the first serializer node of a first memory device is coupled to the first deserializer node of a second memory device, the second serializer node of the first memory device is coupled to the first deserializer node of the first memory device, the first serializer node of the second memory device is coupled to the second deserializer node of the second memory device, and the second serializer node of the second memory device is coupled to the second deserializer node of the first memory device; and an error checker to check the data from the one or more memory devices for errors, the error checker having a first test mode for testing a first aspect of the plurality of memory devices and a second test mode for testing a second aspect of the plurality of memory devices, wherein the first test mode is a serial IO (input-output) test mode and the second test mode is a memory interface test mode; wherein the serial IO test mode is separated from the memory interface test mode; and wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated by a test generator for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.