Patent ID: 8106402

Claim:
A flat panel display apparatus comprising: a substrate; an active layer of a thin film transistor (TFT), comprising: a channel region; a source region; and a drain region, wherein the channel region, the source region and the drain region are formed on the same layer on the substrate; a first bottom electrode of a capacitor formed apart from the active layer on the same layer as the active layer and formed of a same material as the active layer and a first top electrode of a capacitor formed on the first bottom electrode; a first insulation layer formed on the substrate, the active layer, and the first top electrode; a gate bottom electrode and a gate top electrode sequentially formed on a portion of the first insulation layer corresponding to the channel region; a second bottom electrode and a second top electrode of the capacitor formed of the same material used to form the gate bottom electrode and the gate top electrode, wherein the second bottom electrode and the second top electrode are sequentially formed on a portion of the first insulation layer corresponding to the first top electrode of the capacitor; a pixel bottom electrode formed of the same material used to form the gate bottom electrode and the second bottom electrode of the capacitor and formed on the first insulation layer; a pixel top electrode formed of the same material as that used to form the gate top electrode and the second top electrode of the capacitor and formed on the edge of the top surface of the pixel bottom electrode to expose the pixel bottom electrode; a second insulation layer formed on the gate electrode, the second electrode of the capacitor, and the pixel top electrode and penetrated by a contact hole exposing the source region and the drain region of the active layer and a via hole partially exposing the edges of the pixel top electrode; and a source electrode and a drain electrode formed on the second insulation layer and connected to the source region, the drain region, and the pixel top electrode via the contact hole and the via hole.