Patent ID: 8345497

Claim:
An output control circuit for a memory array, comprising: a latched output node that is precharged to a first logic state prior to a read operation and prior to a write operation; first logic configured to selectively couple memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic configured to internally bypass the memory read path during the write operation by decoupling the memory read path from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node through the second logic, the second logic also controlled by the timing signal; wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of a transition of the output node from the first logic state to a second logic state during the read operation; and wherein the first logic is further controlled by a read enable signal and the second logic is further controlled by a separate write enable signal.