Patent ID: 8896070

Claim:
An apparatus comprising a multi-layer structure of semiconductor material formed by steps comprising: providing a first semiconductor wafer with a first facing surface on which a first conductive layer is formed, the first semiconductor wafer comprises an embedded silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor and a memory element layer is provided on the silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor and the memory element layer separates the first conductive layer from the silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor; attaching the first semiconductor wafer to a second semiconductor wafer to form the multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive layer is formed, wherein the first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure; removing portions of the embedded combined conductive wafer to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure; further comprising a plurality of spaced apart stacked pillars of semiconductor material formed by removing material from the first semiconductor wafer, the pillars arranged into rows and columns, and wherein respective rows or columns of the pillars are contactingly supported by the respective control lines; wherein each of the pillars comprise a non-volatile memory element electrically between and separating the metal oxide semiconductor field effect transistor and the respective control line; and wherein the multi-wafer structure is characterized as a solid state memory comprising individual memory cells coupled to said plurality of control lines, wherein the individual memory cells are formed in the first semiconductor wafer after the spaced apart control lines are formed, and wherein control circuitry coupled to said memory elements is formed in the second semiconductor wafer prior to the formation of the spaced apart control lines.