Patent ID: 8466720

Claim:
Circuitry for dividing a frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer, the circuitry comprising: a flip flop configured to be clocked on a first type of edge of the input clock signal, and configured to provide an output for use as a divided clock signal; and feedback circuitry configured to be clocked on the first type of edge of the input clock signal and configured to: receive the output of the flip flop; provide a signal to a data input of the flip flop based on the output of the flip flop; and receive at least one control signal which determines a mode of the circuitry, wherein in a first mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop so that each first type of edge causes the signal provided to the data input of the flip flop to toggle such that the output of the flip flop has a frequency which is substantially half of the frequency of the input clock signal, and wherein in a second mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop with the exception that toggling of the signal provided to the data input of the flip flop is selectively prevented despite toggling of the output of the flip flop on an edge of the first type such that the output of the flip flop has a frequency which is at most a third of the frequency of the input clock signal, wherein the feedback circuitry is arranged to operate independently from a second type of edge of the input clock signal in providing the signal to the data input of the flip flop, the second type of edge being the opposite of the first type of edge of the input clock signal, such that the output of the flip flop is independent from the duty cycle of the input clock signal, and wherein the feedback circuitry is arranged to provide a block output signal and comprises a divide-by-two block for dividing the block output signal by two to thereby provide a final output signal.