Patent ID: 8885429

Claim:
A memory device comprising: an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated word line, and each column of memory cells being coupled to an associated at least one bit line; decoder circuitry configured to be responsive to a write operation to decode an address indication associated with the write operation in order to determine the row containing addressed memory cells for the write operation, and to issue, in dependence on a clock signal, an asserted word line signal on the associated word line for the determined row; and write circuitry configured to be responsive to said write operation to control a voltage level of the associated at least one bit line for each of said addressed memory cells to cause write data to be written into said addressed memory cells; the decoder circuitry being configured to be responsive to an asserted erase signal to issue, independently of said clock signal, said asserted word line signal on the word line associated with each row in a predetermined erase region of the array; and the write circuitry being configured to be responsive to said asserted erase signal to control the voltage level of the associated at least one bit line for each memory cell in said predetermined erase region, in order to cause erase write data to be written into the memory cells of said predetermined erase region; whereby the memory device is responsive to said asserted erase signal to trigger a forced write operation in respect of each memory cell within said predetermined erase region.