Patent ID: 8630139

Claim:
A dual power supply memory array comprising: a memory cell; a pair of complementary bitlines connected to said memory cell; a first power supply rail having a first supply voltage; a second power supply rail having a second supply voltage; a voltage comparator comparing said first supply voltage to said second supply voltage and outputting a voltage difference signal, said voltage difference signal having a first value when said first supply voltage is any of equal to said second supply voltage and less than said second supply voltage and said voltage difference signal having a second value when said first supply voltage is greater than said second supply voltage; and a control circuit performing the following: receiving said voltage difference signal; when said voltage difference signal has said first value, pre-charging said complementary bitlines to said first supply voltage by electrically connecting said complementary bitlines to said first power supply rail; and when said voltage difference signal has said second value, pre-charging said complementary bitlines to said second supply voltage by electrically connecting said complementary bitlines to said second power supply rail.