Patent ID: 7482278

Claim:
A method of filling gaps between a pattern of interconnect lines forming a wiring structure on a semiconductor substrate, said interconnect lines having a top surface further having sidewalls, comprising the steps of: providing a semiconductor substrate said substrate having a surface; creating a network of interconnect lines on said surface of said substrate whereby said interconnect lines are separated by holes having bottoms between said interconnect lines thereby leaving said surface of said substrate partially exposed over said bottoms of said holes between said interconnect lines; depositing a first layer of dielectric having a surface over said interconnect lines wiring structure thereby including said exposed surface of said semiconductor substrate; performing an etch back of said first layer of dielectric thereby forming deposits of said first layer of dielectric on the top surface of the interconnect lines; depositing a second layer of dielectric having a surface over said etched back first layer of dielectric; etching said second layer of dielectric thereby creating exposed portions of said first layer of dielectric; and depositing a layer of oxide over said etched second layer of dielectric thereby including said exposed portions of said first layer of dielectric.