Patent ID: 8117570

Claim:
An integrated circuit design system for designing, in a design layout stage, a real integrated circuit based on circuit data describing a logic circuit by a hierarchical structure in which a lower level hierarchical block is included in an upper level hierarchical block, comprising: a first circuit data generating means for receiving input circuit data sufficient to generate RTL data from a source, said first circuit data including an RTL generation unit describing a first hierarchical block to which a supply of power should be cut off in response to a control signal as a first hierarchical block and a switch power cell, and a second circuit data generating means, including a net list generation unit, for generating second circuit data describing a second hierarchical block with a lower level comprised by said first hierarchical block and a virtual power switch cell to which said control signal is input so that said virtual power switch cell of said second circuit data corresponds to at least one power switch cell in said real integrated circuit when implemented; and means for storing said first and second circuit data in a non-transitory storage medium capable of implementing said real integrated circuit from said design layout stage.