Patent ID: 7061278

Claim:
A differential peak detector comprising: a first transistor having a gate, a drain connected to a first voltage source, and a source connected to a first node; a first current source connected between the first node and a second voltage source; a second transistor having a gate and a drain connected to a bias voltage, and a source connected to a second node; a second current source connected between the second node and the second voltage source; a first capacitor connected between a first input terminal of the differential peak detector and the gate of the first transistor; a second capacitor connected between a second input terminal of the differential peak detector and the first node; a first resistor connected between the gates of the first transistor and the second transistor; a second resistor connected between the first node and a third node; and a third capacitor connected between the third node and the second voltage source, wherein the second node is connected to an output terminal providing a reference voltage, the third node is connected to another output terminal providing a detected voltage, and a difference between the detected voltage and the reference voltage is a peak voltage.