Patent ID: 7749851

Claim:
A method for fabricating a semiconductor device, comprising: forming a gate electrode over a surface of a first conductive type semiconductor substrate via a gate insulator; at least forming a post-oxide film on the side-wall of the gate electrode; forming a silicon film to cover the post-oxide film and the surface of the semiconductor substrate; ion-implanting impurities from perpendicular direction to the surface of the semiconductor substrate surface to lower an etching rate by an etching solution at the ion-implanted silicon film as compared with the etching rate by the etching solution at the silicon film of the side-wall of the gate electrode; removing the silicon film of the side-wall of the gate electrode to form a mask on the gate electrode, the mask including a space under the mask, the space being formed at the removed area after removing the silicon film of the side-wall; ion-implanting a first conductive impurity into the surface of the semiconductor substrate through the space from a direction inclined with a prescribed angles for perpendicular to the surface of the semiconductor substrate to form the first conductive impurity region, the first conductive impurity region being buried in the semiconductor substrate, the first conductive impurity region being extended at both sides of an extend plane, the extend plane being extended from both the side-wall sides of the gate electrode into the semiconductor substrate; and ion-implanting a second conductive impurity into the surface of the semiconductor substrate using the gate electrode as a mask to form a source/drain region, the source/drain region being extended from an end of the gate electrode at the semiconductor substrate to an outer region in the semiconductor substrate and the source/drain region being partially overlapped with the first conductive impurity region.