Patent ID: 7803639

Claim:
A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a metallization level to a first and a second feature, the first and second features each occupying different levels in the integrated circuit that are lower than the metallization level, the method comprising the steps of: forming a first etch stop layer overlying at least a portion of the first feature; forming a second etch stop layer overlying at least a portion of the second feature; forming an interlayer dielectric layer overlying the first and second etch stop layers; forming a photolithographic mask overlying the interlayer dielectric layer, the photolithographic mask defining a first opening over the first feature and a second opening over the second feature; performing a first etch process with the photolithographic mask, the first etch process operative to etch a first hole in the interlayer dielectric layer through the first opening in the photolithographic mask, the first hole landing on the first etch stop layer upon completion of the first etch process, and to etch a second hole in the interlayer dielectric layer through the second opening in the photolithographic mask, the second hole landing on the second etch stop layer upon completion of the first etch process; performing a second etch process, the second etch process being at least operative to further etch the first hole so that it lands on the first feature; and filling the first and second holes with one or more electrically conductive materials; wherein the first feature comprises a first metal interconnect and the second feature comprises a magnetic tunnel junction overlying a second metal interconnect, the first and second metal interconnects being distinct structures both occupying a given level in the integrated circuit.