Patent ID: 6918099

Claim:
A system for verification of a microelectronic device design, the system comprising: a simulation engine operable to generate stimuli to apply to the microelectronic device design, the stimuli generated according to one or more predetermined factors; a test engine operable to apply the stimuli to the microelectronic device design to produce a response; a results engine operable to compare the test engine response to an expected stimuli response to detect microelectronic device errors; a communication interface operable to communicate stimuli from the simulation engine to the test engine and to communicate test engine responses to the stimuli from the test engine to the results engine; an entropy estimator interfaced with the communication interface, the entropy estimator operable to estimate an entropy associated with the communication interface; and an entropy feed back engine interfaced with the entropy estimator and the simulation engine, the entropy feed back engine operable to alter the predetermined factors based on the estimated entropy to generate a desired stimulus.