Patent ID: 8650466

Claim:
A method for incrementally generating an error locator polynomial, including: obtaining an initial dataword which includes: (1) a first symbol X i which includes a first bit pattern of Y i and (2) a second symbol X j which includes a second bit pattern Y j ; obtaining an initial error locator polynomial associated with the initial dataword; and using a processor to: modify the initial dataword to obtain a first test error pattern, including by flipping the first bit pattern of Y i in the first symbol X i in the initial dataword; modify the first test error pattern to obtain a second test error pattern, including by flipping the second bit pattern of Y j in the second symbol X j in the first test error pattern; generate a first error locator polynomial associated with the first test error pattern based at least in part on an initial error locator polynomial associated with the initial dataword; and generate a second error locator polynomial associated with the second test error pattern based at least in part on the first error locator polynomial associated with the first test error pattern.