Patent ID: 7144761

Claim:
A method for fabricating a semiconductor device comprising the steps of: depositing a first metal film on a semiconductor substrate with an insulating film sandwiched therebetween; depositing a second metal film on said first metal film; forming an interlayer insulating film on said second metal film; forming a via hole in said interlayer insulating film; forming an adhesive layer on said via hole; then, removing a part of said adhesive layer present on a bottom of said via hole selectively so as to expose a surface of said second metal film only at the bottom of said via hole; forming a plug of a third metal film selectively grown on the exposed surface of said second metal film within said via hole; forming a patterned interlayer insulating film by patterning said interlayer insulating film into the shape of interconnects; and forming metal interconnects from a multi-layer film composed of said first metal film and said second metal film by etching said multi-layer film with said plug and said patterned interlayer insulating film used as a mask, wherein said first metal film is an interconnected layer and said second metal film is a seed layer, and said plug is in contact with said seed layer only at the bottom of said via hole.