Patent ID: 7911841

Claim:
A non-volatile memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a flag cell array having a plurality of flag cells and a redundancy flag cell that may replace one of the plurality of flag cells, wherein each flag cell is arranged in the memory cell array interspersed among the plurality of memory cells, all cells of a given row being connected to a same word line and all cells of a given column being connected to a same bit line, each flag cell corresponding to one row of the rows; a page buffer configured to buffer data input to or output from one of the rows; and a circuit configured to determine a MSB status of one of the rows, the circuit including, a selection signal generation unit configured to output a plurality of selection signals based on whether the corresponding flag cell is normally operated, a selection circuit including a plurality of selectors configured to receive data of the corresponding flag cell and the redundancy flag cell and selectively output the data of the corresponding flag cell or the redundancy flag cell in response to the selection signals, and a determination unit configured to determine MSB status of the one row based on output signals of the plurality of selectors.