Patent ID: 7781851

Claim:
A semiconductor device comprising: a chip-sized substrate including at least one of a plurality of circuit devices and a plurality of interconnect patterns at an upper surface thereof; a first layer of material extending over substantially the entire upper surface of the substrate, and a second layer of material disposed directly on the first layer of material; wherein a stress-relieving pattern exists in the first layer and traverses the first layer so as to partition the first layer into at least two discrete sections, whereby stress otherwise applied to the substrate by the first layer is mitigated by the stress-relieving pattern, wherein the stress-relieving pattern is a wall of a second material comprising an epoxy that is different from the material of the first layer, wherein the wall constituting the stress-relieving pattern is of the same material as the second layer, and wherein the second layer extends over substantially the entire surface of the first layer, and a stress-relieving pattern exists in and traverses the second layer so as to partition the second layer into at least two discrete sections.