Patent ID: 8659136

Claim:
A memory module, comprising: a first multichip package, the first multichip package including a first master chip and a first plurality of slave chips; a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips; a first through via, the first through via passing through the first master chip and electrically connected to the first master chip to provide a supply voltage to the first master chip; a second through via, the second through via passing through the first master chip without being electrically connected to provide a supply voltage to the first master chip; a first set of additional through vias, each additional through via passing through a respective one of the first plurality of slave chips and electrically connected to the respective one of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias; a third through via, the third through via passing through the second master chip and electrically connected to the second master chip to provide the supply voltage to the second master chip; a fourth through via, the fourth through via passing through the second master chip without being electrically connected to provide a supply voltage to the second master chip; a second set of additional through vias, each additional through via passing through a respective one of the second plurality of slave chips and electrically connected to the respective one of the second plurality of slave chips, wherein the fourth through via and second set of additional through vias are aligned to form a second stack of through vias; a first port electrically connected to the first and third through vias for providing the supply voltage to the first master chip and the second master chip; and a second port electrically connected to the first and second stacks of through vias for providing the supply voltage to the first plurality of slave chips and the second plurality of slave chips.