Patent ID: 8006021

Claim:
A bridge, comprising: a slave processor local bus interface; a crossbar switch coupled to the slave processor local bus interface; a master processor local bus interface coupled to the crossbar switch; the slave processor local bus interface, the crossbar switch, and the master processor local bus interface all being part of an embedded core of a host integrated circuit having a core; the slave processor local bus interface having a slave-side portion coupled to a first portion of the core; the slave processor local bus interface further having a master-side portion coupled to the crossbar switch; the master processor local bus interface having a slave-side portion coupled to the crossbar switch; the master processor local bus interface further having a master-side portion coupled to a second portion of the core; the slave processor local bus interface and the master processor local bus interface coupled to one another via the crossbar switch for bidirectional communication between the first portion of the core and the second portion of the core to provide the bridge; the master-side portion of the slave processor local bus interface, the crossbar switch, and the slave-side portion of the master processor local bus interface configured to operate at a first frequency of operation; the master-side portion of the master processor local bus interface configured to operate at a second frequency of operation that is a first fraction of the first frequency of operation; and the slave-side portion of the slave processor local bus interface configured to operate at a third frequency of operation that is a second fraction of the first frequency of operation; wherein the bridge provides rate adaptation for bridging for use of the first frequency of operation which is substantially greater than both the second frequency of operation and the third frequency of operation.