Patent ID: 6864182

Claim:
A method for producing a large-area membrane mask upon a multi-layered wafer having a semiconductor layer, a semiconductor carrier layer, a rear side, a center region, and an edge region, the method which comprises: structuring the semiconductor layer by forming mask openings; subsequently removing the wafer underneath the mask openings from the rear side by at least one dry-etching step to produce a membrane formed by the structured semiconductor layer and held by a carrying ring; and covering the wafer in a region of the carrying ring with a masking layer during the at least one dry etching step, thereby causing irregularity of etching conditions between the center region and the edge region of the etched portion of the wafer, and counteracting such irregularity by providing an approximately homogeneous etching removal over an entire area of the wafer to be etched by one of: for an existing wafer, providing an additional layer construction compensating for the etching irregularity to at least one of a masking region and an open area of the semiconductor carrier layer to be etched; for an existing wafer, moving a mechanical etching diaphragm in front of the semiconductor carrier layer to expose the edge region to etching attack for a shorter time than the center region; and during a production of the wafer, providing at least two insulator etching stop layers one on top of the other and separated by an inner semiconductor carrier layer, the inner semiconductor carrier layer being thinner than the semiconductor carrier layer etched in a first partial etching step.