Patent ID: 7213092

Claim:
Apparatus for processing data, said apparatus comprising: at least one bus master operable to generate data access transactions; at least one bus slave operable to receive said data access transactions; and a communication bus coupling said at least one bus master to said at least one bus slave, data access transactions passing via said communication bus between said at least one bus master and said at least one bus slave; wherein said communication bus has separate signal lines providing respective independently and concurrently operable communication channels including: (i) a write data channel operable to transfer write data from said at least one bus master to said at least one bus slave; (ii) a read data channel operable to transfer read data from said at least one bus slave to said at least one bus master; and (iii) a write response channel operable to transfer a write response indicative of an outcome of a write transaction from said at least one bus slave to said at least one bus master, wherein a write transaction issued from a bus master is one of a bufferable write transaction subject to an optional buffering delay: and a non-bufferable write transaction not subject to any optional buffering delay, wherein said write response channel transfers write responses in respect of only non-bufferable write transactions.