Patent ID: 7391080

Claim:
An LDMOS transistor device, comprising: a semiconductor substrate, an LDMOS gate region on top of said substrate, which comprises: first and second gate insulation layer regions, a centrally located insulation layer region provided between said first and second gate insulation layer regions, and a first and a second gate conducting layer region, each of which being provided on top of a respective one of said first and second gate insulation layer regions, each being a spacer formed adjacent to a respective sidewall of said centrally located insulation layer region, and each having a length which is less than a length of said centrally located insulation layer region, said first and said second gate conducting layer regions being provided with individual contacts for electric connection; LDMOS source and drain regions, and a channel region arranged in said substrate beneath said LDMOS gate region, wherein said channel region is located at least partly directly beneath one of said first and second gate conducting layer regions, and a drain drift region is located at least partly directly beneath another one of said first and said second gate conducting layer region, said channel region interconnecting said LDMOS source and drain regions.