Patent ID: 8437410

Claim:
An apparatus, comprising: a receive logic to receive a clipping instruction, where the clipping instruction when executed clips filtered values in a video image de-blocking operation; and an execution logic to execute the clipping instruction in one clock cycle, where the execution logic includes: a decoder logic to: retrieve a pixel value, where the pixel value is comprised of a plurality of pixel bits and a pixel sign bit; and retrieve a clipping value, where the clipping value is comprised of a plurality of magnitude bits and a magnitude sign bit; a magnitude logic to: invert the plurality of pixel bits to generate a plurality of inverted pixel bits; establish a plurality of pixel magnitude bits by selecting one of, the plurality of pixel bits, and the plurality of inverted pixel bits, based on the pixel sign bit; invert the plurality of magnitude bits to generate a plurality of inverted magnitude bits; and establish a plurality of clipping magnitude bits by selecting one of, the plurality of magnitude bits, and the plurality of inverted magnitude bits, based on the magnitude sign bit; a comparator logic to compare a value of the plurality of pixel magnitude bits with a value of the plurality of clipping magnitude bits to produce a comparison signal; and a selector logic to: establish a result value as one of, the plurality of pixel magnitude bits, and the plurality of clipping magnitude bits based on the comparison signal; and generate a result sign bit.