Patent ID: 8188796

Claim:
A clock system, comprising: a digital phase/frequency detector (DPFD) having a first input for a reference clock, a second input for a feedback clock, the DPFD generating an output representing a difference between the reference clock and the feedback clock; a buffer coupled to the DPFD for storing the difference signal over time and outputting a control word (F); a digitally-controlled oscillator (DCO) comprising: a sigma-delta modulator (SDM) having a control input coupled to the buffer, an adder having inputs coupled to the SDM and a source of an integer control word (N), and a first frequency divider having (1) a clock input for receiving an external source clock signal and (2) a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external source clock signal divided by (N+F/M), wherein M is a modulus of the SDM; and a second frequency divider coupled to the DCO output clock signal outputting the feedback clock to the DPFD.