Patent ID: 7102410

Claim:
A circuit for converting an input signal at a first voltage level to an output signal at a second voltage level, the circuit comprising: a first unit operating at a first power supply voltage, the first unit receiving the input signal, wherein the first unit includes, a first NMOS transistor having a gate connected to the input signal, a source connected to a reference voltage, and a drain; a second NMOS transistor having a source connected to the reference voltage and a drain; and an inverter having an input connected to the input signal and an output connected to a gate of the second NMOS transistor; a second unit operating at a second power supply voltage, wherein the second unit includes, a first PMOS transistor having a source connected to the second power supply voltage; and a second PMOS transistor having a gate connected to a drain of the first PMOS transistor, a drain connected to a gate of the first PMOS transistor and a source connected to the second power supply voltage; and a third unit coupling the first unit to the second unit, the third unit enabling generation of the output signal, wherein the third unit includes, a third NMOS transistor having a source connected to the first unit and a gate connected to the first power supply voltage; a fourth NMOS transistor having a source connected to the first unit and a gate connected to the first power supply voltage; a third PMOS transistor having a gate connected to the first power supply voltage, a source connected to the second unit and a drain connected to a drain of the third NMOS transistor; a fourth PMOS transistor having a gate connected to the first power supply voltage, a source connected to the second unit and a drain connected to a drain of the fourth NMOS transistor, wherein the output signal is generated at the drains of the third and fourth NMOS transistors; a fifth PMOS transistor having a source connected to the first power supply voltage, a drain connected to the source of the third PMOS transistor, a bulk connected to its drain, and a gate connected to the drain of the third NMOS transistor; and a sixth PMOS transistor having a source connected to the first power supply voltage, a drain connected to the source of the fourth PMOS transistor, a bulk connected to its drain, and a gate connected to the drain of the fourth NMOS transistor; and wherein each of the first, second and third units consists essentially of thin oxide transistors.