Patent ID: 7430268

Claim:
A dynamic shift register comprising a plurality of dynamic shift register stages connected in serial, {S N }, N=1, 2, . . . , M, M being a nonzero positive integer, wherein the N-th dynamic shift register stage, S N , comprises: (i). an input electrically connected to an output of the (N−1)-th dynamic shift register stage, S N−1 ; (ii). an output electrically connected to an input of (N+1)-th dynamic shift register stage, S N+1 ; (iii). a first reference line for receiving a first supply voltage, and a second reference line for receiving a second supply voltage; (iv). a dynamic shift register unit having a first input coupled to the input of the dynamic shift register stage S N for receiving an input pulsed signal, a second input for receiving a control signal, and an output coupled to the output of the dynamic shift register stage S N ; (v). a disable circuit having a first input coupled to the first input of the dynamic shift register unit, a second input coupled to the output of the dynamic shift register unit, and an output coupled to the second input of the dynamic shift register unit, wherein the disable circuit further comprises: a. a first transistor having a gate, a drain and a source, wherein the gate is coupled to the drain, and the drain is coupled to the first reference line; b. a second transistor having a gate, a drain and a source, wherein the gate is coupled to the first input of the disable circuit, the drain is coupled to the source of the first transistor, and the source is coupled to the second reference line; c. a third transistor having a gate, a drain and a source, wherein the gate is coupled to the source of the first transistor and the drain of the second transistor, and the source is coupled to the output of the disable circuit; d. a fourth transistor having a gate, a drain and a source, wherein the gate is coupled to the first input of the disable circuit, the drain is coupled to the source of the third transistor and coupled to the output of the disable circuit, and the source is coupled to the second reference line; e. a fifth transistor having a gate, a drain and a source, wherein the gate is coupled to the drain, and the drain is coupled to the first reference line and the source is coupled to the drain of the third transistor; and f. a sixth transistor having a gate, a drain and a source, wherein the gate is coupled to the second input of the disable circuit, the drain is coupled to the drain of the third transistor and the source of the fifth transistor, and the source is coupled to the second reference line.