Patent ID: 7603640

Claim:
A method for generating a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the method comprising the steps of: a. partitioning a floorspace to be occupied by the integrated circuit into regions and allocating all of the modules among those regions using a floorplanner running on a computer, b. iteratively partitioning the regions into progressively smaller regions using the floorplanner, wherein modules previously allocated to any region before being partitioned are allocated among the smaller regions into which said any region was partitioned; until each region of the floorspace has been allocated no more than a predetermined maximum number of modules, c. after step b, generating a separate floorplan for each region, d. iteratively merging neighboring regions until only a single region remains, wherein upon merging any neighboring regions to form a merged region, floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.