Patent ID: 7961885

Claim:
An electronic system contained within an enclosure, the electronic system comprising: JTAG circuitry that implements at least a portion of a JTAG protocol, wherein the JTAG circuitry supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK) line; a debug interface to communicatively couple the JTAG circuitry to a debug device external to the enclosure, wherein the debug interface comprises a transmit (TX) line, a receive (RX) line, and a clock (CLK) line; wherein the system transmits data output by the JTAG circuitry on the TDI input on the RX line of the debug interface and receives data from the debug device on the TX line of the debug interface and provides the received data to the JTAG circuitry on the TDO line, the TR line and the TMS line, wherein the debug interface encrypts data transmitted on the debug interface to the debug device and decrypts data received on the debug interface from the debug device.