Patent ID: 8049706

Claim:
A gate driving circuit for providing a plurality of gate signals to a plurality of gate lines, the gate driving circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals to a high voltage level according to a driving control voltage and a first clock; a buffer unit for receiving an input signal; an energy-store unit, electrically connected to the pull-up unit and the buffer unit, for providing the driving control voltage to the pull-up unit through performing a charging process based on the input signal; a discharging unit, electrically connected to the energy-store unit, for pulling down the driving control voltage to a low power voltage according to a control signal or a (N+1)th gate signal generated by a (N+1)th shift register stage of the shift register stages; a pull-down unit, electrically connected to the Nth gate line, for pulling down the Nth gate signal to the low power voltage according to the control signal; a control unit, electrically connected to the discharging unit and the pull-down unit, for generating the control signal based on the input signal and a second clock having a phase opposite to the first clock; and a signal switching unit, electrically connected to the control unit, for switching the control signal to the low power voltage according to the first clock.