Patent ID: 8713295

Claim:
A server comprising: a physical serial bus; a plurality of Processor Memory Boards (PMBs), each PMB comprising a plurality of physically paritionable symmetric multiprocessors, wherein each of the plurality of PMBs is dividable into a pair of symmetric multiprocessor complexes; and an Input/Output Module (IOM) comprising a pluggable module implementing a plurality of Input/Output Sub-Modules (IOSMs), each IOSM providing an Input/Output chain of a plurality of different interfaces including a Southbridge interface, wherein each Southbridge interface of each IOSM is coupled with a virtual access controller, wherein the virtual access controller provides a physical serial interface to the physical serial bus, wherein each pair of symmetric multiprocessor complexes is coupled to a different one of the IOSMs, and wherein each of the physically partitionable symmetric multiprocessors is enabled to boot from a device accessible through the IOM.