Patent ID: 8838946

Claim:
A processor comprising: a plurality of registers; a decoder coupled with the plurality of the registers, the decoder to decode a first instruction, the first instruction to have a first field to specify a first source register that is to have a first plurality of packed signed 16-bit integers and a second field to specify a second source register that is to have a second plurality of packed signed 16-bit integers; and a functional unit coupled with the decoder, the functional unit to generate a result according to the first instruction that is to be stored in a destination register that is to be specified by a third field of the first instruction, the result to include a third plurality of packed 8-bit integers, the third plurality of the packed 8-bit integers to include an 8-bit integer for each 16-bit integer in the first plurality of the packed signed 16-bit integers, and an 8-bit integer for each 16-bit integer in the second plurality of the packed signed 16-bit integers, the 8-bit integers that are to correspond to the first plurality of the packed signed 16-bit integers to be in a highest order half of the result, and the 8-bit integers that are to correspond to the second plurality of the packed signed 16-bit integers to be in a lowest order half of the result, a highest order 8-bit integer of the result to correspond to a highest order 16-bit integer of the first plurality of the packed signed 16-bit integers, and a lowest order 8-bit integer of the result to correspond to a lowest order 16-bit integer of the second plurality of the packed signed 16-bit integers, and each 8-bit integer of the third plurality of the packed 8-bit integers to include one of (a) a low order 8-bits of a corresponding 16-bit integer and (2) a saturation value.