Patent ID: 6940120

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines comprised of an impurity-diffused layer formed in the surficial portion of said semiconductor substrate; and a plurality of word lines comprised of a conductive layer formed above said semiconductor substrate and arranged so as to cross with said plurality of bit lines in a plan view; a first insulating film formed on said word lines; and a sidewall formed along said word lines; wherein between every adjacent word lines, a groove is formed only in the surficial portion of said semiconductor substrate within each area horizontally defined, in a plan view, by the first insulating film formed on said adjacent word lines and by adjacent bit lines so as to be effectively aligned with an edge of said sidewall, said groove not overlapping said first insulating film in plan view; a channel stop impurity-diffused layer is formed at the bottom of said groove; and an insulating film is filled in said groove.