Patent ID: 7999318

Claim:
A transistor comprising: a source including a p-doped p-body, a p-doped p+ region overlapping the p-body, a first n-doped n+ region overlapping the p-body in proximity to the p-doped p+region, and a n-doped source, heavily double-diffused (SHDD) region only in the source of the transistor, the SHDD region overlapping the p-body, the SHDD region having a depth about equal to that of the first n-doped n+ region and overlapping the first n-doped n+ region; a drain including a second n-doped n+ region, and an n-doped shallow drain overlapping the second n-doped n+ region; and a gate to control a depletion region between the source and the drain, the gate including a gate oxide and a conductive material over the gate oxide, the SHDD region extending further laterally than the first n-doped n+ region beneath the gate oxide, the first n-doped n+ region extending further laterally than the SHDD region toward the source; wherein the SHDD region is implanted using a dopant concentration greater than that used in the implant of the n-doped shallow drain but less than that used in the implant of the first n-doped n+ region.