Patent ID: 7781319

Claim:
A method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, comprising: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and second gate electrode by patterning said silicon layer, said first gate electrode being a gate electrode of said NMOS transistor, and said second gate electrode being a gate electrode of said PMOS transistor; forming an interlayer film covering said first and said second gate electrodes; planarizing said interlayer film; removing an upper portion of said planarized interlayer film to expose said silicon layer of said first and said second gate electrodes; simultaneously introducing impurity for controlling composition of a silicide phase, into said exposed upper portion of said silicon layer of said first and said second gate electrode respectively; selectively removing said exposed upper portion of said second gate electrode having the introduced impurity, out of said first and said second gate electrodes; forming a metallic layer formed of a metal capable of forming a silicide over said silicon layer of said selectively removed second gate electrode and said silicon layer of said first gate electrode; performing a heat treatment such that a silicide layer of said metallic layer is formed; and removing an unreacted portion of said metallic layer after said heat treatment process.