Patent ID: 7825472

Claim:
A semiconductor device, comprising: a lower insulating layer on a semiconductor substrate; an upper channel body pattern on the lower insulating layer; a source region and a drain region within the upper channel body pattern; a non-metal transfer gate electrode on the upper channel body pattern between the source and drain regions; an intermediate insulating layer covering the non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer; a metal word line within the intermediate insulating layer and contacting at least an upper surface of the non-metal transfer gate electrode; an insulating spacer covering a sidewall of the metal word line; and a metal node plug within the intermediate insulating layer and the lower insulating layer and in contact with the source region of the upper channel body pattern, wherein a combined width of the insulating spacer and the metal word line is greater than a width of the non-metal transfer gate electrode, and wherein the metal word line contacts the upper surface and at least one sidewall of the non-metal transfer gate electrode.