Patent ID: 7515455

Claim:
A memory device comprising: a first bit line in a first conducting layer; a second bit line parallel to the first bit line, the second bit line in a second conducting layer; a third bit line parallel to the first bit line, the third bit line in the first conducting layer; a first MOS select transistor; a second MOS select transistor sharing a source with the first MOS select transistor; a third MOS select transistor sharing a drain with the first MOS select transistor; a word line coupled to a gate of the first MOS select transistor, the word line at an angle with respect to the first bit line and the second bit line; a first resistive memory element coupled between the shared source of the first MOS select transistor and the second bit line; a second resistive memory element coupled between the shared drain of the first MOS select transistor and the third bit line; and a third resistive memory element coupled between a drain of the second MOS select transistor and the first bit line.