Patent ID: 8065572

Claim:
An integrated circuit comprising: a scan chain having a plurality of serially coupled scan elements, wherein at least a subset of the plurality of scan elements are coupled to provide signals to a memory array, and wherein each of the subset of the plurality of scan elements includes: a flip flop having a data input, and a data output coupled to a corresponding input of the memory array; and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output, wherein the selection circuitry includes: a first selection circuit having a first output coupled to the data input and a first select input coupled to receive a scan enable signal; a second selection circuit having a second output coupled to the first selection circuit and a second select input coupled to receive a hold enable signal; and a third selection circuit having a third output coupled to the second selection circuit and a third select input coupled to receive an invert enable signal.