Patent ID: 7818707

Claim:
A computer implemented method for using pattern matching with an electronic circuit layout, comprising: using a computer system which comprises at least one processor and is programmed or configured for: identifying one or more situations for the electronic circuit layout, wherein at least one of the one or more situations comprises one or more shapes or cell instances which are arranged to represent one or more circuit features in the electronic circuit layout; identifying or determining one or more sets of situation, data from pre-lithography enhancement design data of the at least one of the one or more situations with respect to a pattern; determining whether the one or more sets of situation data meet one or more match criteria by comparing at least the one or more sets of situation data from the pre-lithography enhancement design data with one or more sets of target data; and reporting the at least one of the one or more situations associated with the one or more sets of situation data that meet the one or more match criteria.