Patent ID: 7426707

Claim:
A layout design method for a semiconductor integrated circuit, comprising the steps of: providing a cell layout library which stores structure information of functional cells and a plurality of groups of filler cells, each filler cell acting to fill space between the functional cells, at least one of the plurality of groups of filler cells containing an upper-layer metal and a lower-layer metal having a first portion which is not connected to the upper-layer metal, the lower-layer metal having a second portion which is connected to the upper-layer metal through a via; arranging the functional cells on a layout based on the structural information from the layout library; and arranging the filler cells of any of the plurality of groups selectively based on the structural information from the layout library so that the filler cells are arranged in channel regions where the functional cells are not located on the layout, each channel region being located at a predetermined distance from signal lines on the layout.