Patent ID: 7323901

Claim:
A semiconductor integrated circuit device, comprising: a plurality of sets of output circuits each of which varies an output impedance in accordance with a first impedance code; a first impedance control circuit which generates the first impedance code in association with a first resistive element connected to a first external terminal and includes an first encoder which coverts the first impedance code to serial data; a plurality of sets of terminating circuits each of which varies a terminal impedance in accordance with a second impedance code; a second impedance control circuit which generates the second impedance code in association with a second resistive element connected to a second external terminal and which includes a second encoder which converts the second impedance code to serial data; and a third external terminal (DQ) which is coupled both of the plurality of sets of output circuits and the plurality of sets of terminating circuits, wherein each of the plurality of sets of output circuits includes a decoder which reproduces the first impedance code in response to the serial data, wherein the plurality of sets of terminating circuits respectively include decoders each of which reproduces the second impedance code in response to the serial data, wherein the each of the plurality of sets of output circuits are enable and the plurality of sets of terminating circuits are disable while output data is outputting, and wherein the each of the plurality of sets of output circuits are disable and the plurality of sets of terminating circuits are enable while input data is inputting.