Patent ID: 7875921

Claim:
A non-volatile memory device for 2-bit operation comprising: an active region extending in a word line direction on a semiconductor substrate; a gate extending in the word line direction on the semiconductor substrate, and crossing with the active region repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed at an interface between the charge storage layer and the gate; a tunnel dielectric layer formed at an interface between the charge storage layer and the active region; first and second source/drain regions formed at an exposed portion out of both sides of the gate in the active region; and first and second bit lines connected to the first and second source/drain regions respectively, and formed to extend in a bit line direction crossing the word line direction, wherein one of the active region and the gate is formed in a zigzag pattern, and another of the active region and the gate is formed in a straight pattern.