Patent ID: 8537598

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate and including a plurality of first wirings, a plurality of second wirings formed so as to cross the first wirings, and memory cells disposed at intersections of the first wirings and the second wirings and each having a variable resistive element connected in series; and a control circuit configured to selectively drive the first wirings and the second wirings, the control circuit executing a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state, and at a time of executing the resetting operation, the control circuit increasing a pulse voltage to be applied to the variable resistive element to a first voltage, keeping the pulse voltage at the first voltage from a beginning time of the resetting operation to a first time, decreasing the pulse voltage to a second voltage from the first time, and setting the pulse voltage to the second voltage from the first time to an ending time of the resetting operation, the second voltage being lower than the first voltage and higher than ground voltage, and being lower than a set value at which the variable resistive element changes from the high resistance state to the low resistance state.