Patent ID: 7782107

Claim:
An event tolerant circuit comprising: an input coupled with a storage node that maintains a storage voltage level; a feedback loop coupled with the storage node, the feedback loop configured to reinforce a first voltage level at the storage node; and the feedback loop including a C-element having at least one input and at least one output, the feedback loop further including a delay element connected with the at least one input, the at least one output in communication with the storage node, the C-element configured to pass a first voltage level from the at least one input to the at least one output when the first voltage level at the at least one input to the C-element maintains the first voltage level for at least a delay time T, provided by the delay element, to reinforce the storage voltage level of the storage node, and to not pass the first voltage level from the at least one input to the at least one output when the first voltage level at the at least one input to the C-element does not maintain the first voltage level for at least the delay time T to prevent a glitch from altering the storage voltage level at the storage node, wherein the delay element is configured to sample the storage voltage of the storage node.