Patent ID: 8502299

Claim:
A semiconductor device comprising: a semiconductor body; a NVM device disposed on the semiconductor body, the NVM device comprising: a gate stack overlying the semiconductor body, the gate stack comprising a NVM gate dielectric over the semiconductor body, a floating gate over the NVM gate dielectric, a control gate over the floating gate and an inter-gate dielectric between the floating gate and the control gate, wherein the NVM gate dielectric comprises a stressed NVM gate dielectric having an energy gap that is greater than a band gap of a relaxed NVM gate dielectric of the same material; a doped extension region within the semiconductor body; a NVM source/drain region within the semiconductor body adjacent the doped extension region; a spacer at a sidewall of the gate stack; and a stress liner disposed on the spacer; and a logic transistor disposed on the semiconductor body and spaced from the NVM device, the logic transistor comprising: a gate dielectric disposed the semiconductor body; a gate electrode disposed the gate dielectric; a source/drain region disposed in the semiconductor body; and the stress liner disposed on the gate electrode.