Patent ID: 7571399

Claim:
A process for checking a quality of metallization of a printed circuit ( 2 ; 4 a - 4 d ), comprising: providing a checking circuit ( 1 ) comprising n through openings ( 7 - 1 . . . 7 - 6 , 8 - 1 . . . 11 - 6 ), called vias, with n a whole number greater than or equal to one, the vias being provided with an internal peripheral wall adapted to be clad with a metallized layer ( 12 ) during a metallization step of the printed circuit, the vias being connected electrically in series between two electrical terminals ( 16 - 18 , 20 - 22 ), such that an electrical current applied between said electrical terminals passes in a direction of a height (h) along each of the vias ( 7 - 1 . . . 7 - 6 , 8 - 1 . . . 11 - 6 ); applying a current of predetermined intensity between the two electrical terminals ( 16 - 18 , 20 - 22 ) of the checking circuit ( 1 ) by a computer processor; measuring a corresponding voltage difference between the two electric terminals by said computer processor; and comparing the measured value with a threshold value representative of the voltage difference obtained for a metallized layer of minimum predetermined thickness deposited on the peripheral wall of each via ( 7 - 1 . . . 7 - 6 , 8 - 1 . . . 11 - 6 ), so as to validate the printed circuit when the measured value is less than the threshold value by said computer processor.