Patent ID: 7123510

Claim:
A non-volatile semiconductor memory device having a matrix-shaped memory cell area including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, the memory cell area being divided into a plurality of sectors each containing a predetermined number of rows, comprising: a column selection circuit for selecting a column in the memory cell area; a row selection circuit for selecting a row in the memory cell area; a plurality of word lines connected to the row selection circuit, each word line being provided corresponding to each row of memory cells; a plurality of main bit lines connected to the column selection circuit, each main bit line extending in the direction of the columns; a plurality of sub-bit lines provided in each sector, each sub-bit line extending in the direction of the columns; a plurality of selection transistors each provided corresponding to each sub-bit line, each selection transistor being capable of electrically conducting or not electrically conducting between the sub-bit line and a corresponding one of the plurality of main bit lines; and a plurality of selection lines extending in the direction of the rows and connected to the row selection circuit, each selection line applying a voltage to control electrodes of corresponding ones of the plurality of selection transistors for switching the selection transistors between a conducting state and a non-conducting state, wherein, each memory cell is connected between two adjacent sub-bit lines, the row selection circuit selects a word line connected to a memory cell to be read, the column selection circuit includes: a first selection portion for selecting a first pair of main bit lines and two of the plurality of selection lines, thereby selecting the memory cell to be read; and a second selection portion for selecting a second pair of main bit lines and two other of the plurality of selection lines, thereby selecting a line for reading a reference voltage to be used for data determination, wherein the second pair of main bit lines is different from the first pair of main bit lines, and the two other selection lines are to be used for selecting a sector different from a sector to which the memory cell to be read belongs, and the first and second selection portions perform the respective selections simultaneously and independently of each other.