Patent ID: 7648877

Claim:
A method of forming a FET, comprising: forming a trench in a silicon region; forming a silicon nitride layer over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom; forming an oxide layer over the silicon nitride layer such that the oxide layer is thicker along the surface of the silicon region adjacent the trench than along the trench bottom; uniformly etching back the oxide layer such that a portion of the silicon nitride layer extending along the trench bottom and along at least a portion of the trench sidewalls becomes exposed while portions of the silicon nitride layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the oxide layer; removing the exposed portion of the silicon nitride layer along the trench bottom using an anisotropic etch process; removing the remaining portions of the oxide layer; and thereafter forming a dielectric layer along the trench bottom using a local oxidation of silicon (LOCOS) process.