Patent ID: 7865669

Claim:
A system for dynamically adjusting the fetch paths in a multi-level cache, the system comprising: a main memory including data; a first-level cache included in the multi-level cache and connected to the main memory by a first path; a second-level cache larger than the first-level cache, included in the multi-level cache and connected to the first-level cache and the main memory by the first path; a central processing unit (CPU) for fetching data from at least one of: the first-level cache, the second level cache, or the main memory; a hit/miss rate tracker connected to the first path, the first-level cache and the second-level cache, the hit/miss rate tracker for tracking cache misses on the second-level cache associated with a type of application; and a bypass path connected to the hit/miss rate tracker, the first-level cache and the main memory, to bypass the second-level cache and fetch the data from the main memory in response to the miss rate exceeding a prespecified application-specific threshold.