Patent ID: 8507317

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having an interconnect located thereover; creating a solder bump support opening in a first passivation layer located over the interconnect; depositing a lithographic resist layer in the solder bump support opening and over the passivation layer; patterning the lithographic resist layer to form spaced apart sacrificial posts within the solder bump support opening; depositing a conductive material between the spaced apart sacrificial posts and within the solder bump support opening; removing the lithographic resist layer, thereby leaving the conductive material within the solder bump support opening to form support pillars within the solder bump support opening, wherein removing the lithographic resist layer includes leaving a space between at least one of the support pillars and the sidewall of the solder bump support opening; and depositing a second passivation layer over the first passivation layer and between the support pillars; removing a portion of the second passivation layer from between the support pillars, such that the second passivation layer remains within the space between at least one of the support pillars and the sidewall of the solder bump support opening; forming an under bump metallization (UBM) layer over and between the solder bump support pillars.