Patent ID: 8208329

Claim:
A memory circuit comprising: a memory cell; a word line connected to the memory cell; local bit lines connected to the memory cell, wherein the local bit lines comprise a first local bit line and a second local bit line; global bit lines comprising a first global bit line and a second global bit line; a multiplexer (MUX) coupled between the local bit lines and the global bit lines, the MUX being configured to connect the local bit lines and the global bit lines when activated, and disconnect the local bit lines and the global bit lines when deactivated; an equalization circuit coupled between the first and the second local bit lines, the equalization circuit being configured to equalize voltages on the first and the second local bit lines; and a signal generator configured to generate a sequence of signals comprising: a MUX activation signal for activating the MUX; an equalization enable signal for enabling the equalization circuit; and an equalization disable signal for disabling the equalization circuit, wherein the MUX activation signal is later in time than the equalization enable signal, and earlier in time than the equalization disable signal.