Patent ID: 7948799

Claim:
An integrated circuit, comprising: a semiconductor body; a plurality of AND device structures, comprising: a first plurality of parallel structures over the semiconductor body, respective parallel structures in the first plurality of parallel structures including a sub-gate positioned to create an inversion layer in the semiconductor body under the respective parallel structure in the first plurality of parallel structures; and a second plurality of parallel structures over the semiconductor body, the second plurality of parallel structures having a substantially perpendicular orientation relative to the first plurality of parallel structures, respective parallel structures in the second plurality of parallel structures including: a tunneling dielectric layer on the semiconductor body, wherein the tunneling dielectric layer includes a first silicon oxide layer adjacent the semiconductor body and having a thickness of 30 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less; a charge trapping layer on the tunnel dielectric layer, wherein the charge trapping layer comprises silicon nitride having a thickness of 50 Å or more; a blocking dielectric layer on the charge trapping layer; and a control gate on the blocking dielectric layer.