Patent ID: 7586801

Claim:
A semiconductor memory device, comprising: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; and a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; a plurality of banks configured to perform a parallel I/O data communication with the ports; a first data bus configured to transmit a first signal from the ports to the banks; a second data bus configured to transmit a second signal from the banks to the ports; and a plurality of pads configured to provide the test signal to the test I/O controller, wherein the banks include an output driver being a high impedance state in response to the test mode enable signal for preventing the second signal from being transmitted to the second data bus during the port test mode.