Patent ID: 7930666

Claim:
A computer-implemented method of implementing a user integrated circuit (IC) design in a physical IC that has a memory comprising a single physical port, said method comprising: mapping memory accesses in the user design to the memory by using a plurality of logical ports for the memory that has a particular port hierarchy with at least a first logical port that has a higher priority in the particular port hierarchy than a second logical port with a lower priority, wherein the plurality of logical ports for the memory are emulated in a user design clock cycle by accessing the single physical port of the memory a plurality of times in the user design clock cycle; and resolving conflicts resulting from mapping a first memory access and a second memory access in the user design to a particular user design clock cycle by assigning the first memory access to the higher-priority first logical port of the memory while assigning the second memory access to the lower-priority second logical port of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are performed by a design automation tool implemented on a computer.