Patent ID: 7032148

Claim:
A method for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an output-mask controller, and an output-mask network embedded on the scan data input path of second selected scan cells, each scan chain comprising multiple scan cells coupled in series; said method comprising: (a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation; (b) capturing a test response to all said scan cells during a selected capture operation; (c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said unknown (‘x’) captured scan data in said first selected scan cells from propagating through said scan chains by using said output-mask controller to control said output-mask network to prevent said unknown (‘x’) captured scan data from propagating through said second selected scan cells by injecting a predetermined constant logic value, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and (d) repeating steps (b) to (c) until a limiting criteria is reached.