Patent ID: 7814359

Claim:
A high-speed interface semiconductor device comprising: a clock signal generation circuit configured to generate a first clock signal and a second clock signal that have a phase difference of 90 degrees there-between; a first group data transmission circuit configured to multiplex and transmit first group data in response to the first and second clock signals; a second group data transmission circuit configured to multiplex and transmit second group data in response to the first and second clock signals; a first strobe signal transmission circuit configured to transmit a first strobe signal based on the first clock signal; and a second strobe signal transmission circuit configured to transmit a second strobe signal based on the second clock signal, wherein at least one of the first strobe signal transmission circuit is configured to adjust phase of the first strobe signal based on first phase-error information fed back from a receiver and then to transmit the phase-adjusted first strobe signal to the receiver.