Patent ID: 8228106

Claim:
A circuit arrangement comprising: a launching flip-flop configured to output a state transition from a first state to a second, different state based upon a state transition at an input thereof; a programmable delay line coupled to the launching flip-flop, the programmable delay line comprising a configuration unit, wherein the programmable delay line is configured to propagate the state transition from the launching flip-flop therethrough, and wherein a time to propagate the state transition therethrough is associated with a delay time of the programmable delay line; a time-to-digital converter coupled to the programmable delay line, the time-to-digital converter comprising at least one delay element coupled to a respective sampling flip-flop, wherein the time-to-digital converter is configured to measure the delay time of the programmable delay line; and a feedback loop circuit coupled to the time-to-digital converter and to the configuration unit, wherein the feedback loop circuit is adapted to compare the measured delay time to a predetermined target value and provide at least one input signal to the configuration unit based on a result of the comparison.