Patent ID: 6982600

Claim:
An output stage for a Class-G amplifier, comprising: a first current mirror (CmpL) powered by a first low voltage supply (VspL); a second current mirror (Cmph) powered by a first high voltage supply (Vsph); a third current mirror (CmmL) powered by a second low voltage supply (VsmL); a fourth current mirror (Cmmh) powered by a second high voltage supply (Vsmh); each said current mirror including an input and an output, said outputs of said current mirrors connected together to form an output of the output stage; a buffer ( 10 ) including an input (node G) and an output (node X), said buffer ( 10 ) also including a first transistor ( 19 ) and a second transistor ( 27 ) connected in an emitter follower configuration, said input of said buffer forming an input of the output stage; a first switch ( 69 ) to connect a collector of said first transistor ( 19 ) to either said input to said first current mirror (CmpL) or said input to said second current mirror (Cmph); a first comparator ( 68 ) receiving said input (node G) to said buffer ( 10 ), receiving a first reference voltage (refp), and providing an output, wherein said output of said first comparator ( 68 ) controls whether said first switch ( 69 ) connects said collector of said first transistor ( 19 ) to either said input to said first current mirror (CmpL) or said input to said second current mirror (Cmph); a second switch ( 84 ) to connect a collector of said second transistor ( 27 ) to either said input to said third current mirror (CmmL) or said input to said fourth current mirror (Cmmh); and a second comparator ( 82 ) receiving said input (node G) to said buffer ( 10 ), receiving a second reference voltage (refm), and providing an output, wherein said output of said second comparator ( 82 ) controls whether said second switch ( 84 ) connects said collector of said second transistor ( 27 ) to either said input to said third current mirror (CmmL) or said input to said fourth current mirror (Cmmh).