Patent ID: 7426154

Claim:
A logic circuit for executing a plurality of programs relating to a plurality of tasks, each of said tasks being stored in memory at a location that is accessible via an execution address, said logic circuit comprising: a plurality of program counters, each of said program counters holding a count value corresponding to a whole execution address of a corresponding one of said tasks, wherein at least one of said program counters is always counted, only upward, in all execution steps, including both time periods when the corresponding task is executed, and time periods when the corresponding task is not executed; an address generator for generating an address signal for a program storage holding said programs for said tasks, based on the count value of one of said program counters; an operation unit and accumulator, including arithmetic and logic operations and an accumulator, for executing, for all tasks, program instructions accessed from said program storage, and a control unit for generating a control signal for controlling execution and stopping of counting of said plurality of program counters; wherein, said control unit executes said count corresponding to at least one of said plurality of program counters by continuing the count of another of said plurality of program counters, while executing tasks corresponding to the other of said plurality of program counters; and when said at least one of said plurality of program counters reaches a maximum value, it is reset to a minimum value.