Patent ID: 8143131

Claim:
A method of fabricating a semiconductor device, comprising: providing a silicon substrate having a shallow trench isolation (STI) formed thereon; forming a gate stack over the silicon substrate; forming dummy spacers on sidewalls of the gate stack; forming a recess region in the silicon substrate, wherein the recess region is interposed between the gate stack and the STI, and wherein the recess region is partially defined by a sidewall of the STI; epi-growing a semiconductor material in the recess region to partially fill the recess region, wherein the semiconductor material is different from the silicon substrate, and wherein no semiconductor material is formed on the sidewall of the STI; removing the dummy spacers; forming a first silicon oxide layer over the gate stack and the semiconductor material; forming a silicon nitride layer over the first silicon oxide layer; forming a second silicon oxide layer over the silicon nitride layer; performing a first dry etching process to remove a portion of the second silicon oxide layer; performing a second dry etching process to completely remove a portion of the silicon nitride layer disposed over the semiconductor material and unprotected by a remaining portion of the first oxide layer; and performing a third dry etching process to completely remove a portion of the first silicon oxide layer formed on the semiconductor material, thereby forming a gate spacer on a sidewall of the gate stack, wherein the gate spacer includes remaining portions of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer.