Patent ID: 8145848

Claim:
A processor, comprising: a hardware writeback cache configured to store data retrieved from a lower-level memory and further configured to perform a first writeback operation to store corresponding writeback data back to the lower-level memory upon eviction of the writeback data from the writeback cache; and a hardware writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory; wherein after the writeback data has been sent from the writeback buffer to the lower-level memory and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache is further configured to perform a second writeback operation to store different writeback data, corresponding to the second writeback operation, in the writeback buffer in response to eviction of the different writeback data from the writeback cache, such that for at least some set of concurrently at least some set of outstanding write back operations, a total size of writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing.