Patent ID: 7701278

Claim:
A TOP level shifter for use in a drive circuit useful for transmitting an input signal IN from drive logic to a TOP driver, the TOP level shifter comprising: a pulse generating circuit; an UP level shifter coupled to receive pulses generated by said pulse generating circuit; a DOWN level shifter coupled to receive pulses generated by said pulse generating circuit, said DOWN level shifter being in parallel with said UP level shifter; a signal evaluation circuit coupled to receive outputs of said UP level shifter and said DOWN level shifter; and means for receiving first and second supply voltages; wherein said pulse generating circuit generates ON and OFF signals; wherein said UP level shifter includes first and second paths, said first path of said UP level shifter being formed of first and second n-channel transistors, connected in cascode, the drain of said first transistor being coupled to the source of said second transistor; wherein the gate of said first transistor is coupled to receive said ON signal from said pulse generating circuit; wherein the source of the first transistor is coupled to a first ground potential through a first resistor; wherein the junction of said drain of said first transistor and the gate of said second transistor is adapted to receive said first supply voltage through a second resistor; wherein the gate of said second transistor is also adapted to receive said first supply voltage; wherein the drain of said second transistor is coupled to a cathode of a first diode; wherein the anode of said first diode serves as the ON output of said UP level shifter path and is coupled to receive said second supply voltage through a third resistor; said second path of said UP level shifter being formed of third and fourth n-channel transistors, connected in cascode, the drain of said third transistor being coupled to the source of said fourth transistor; wherein the gate of said third transistor is coupled to receive said OFF signal from said pulse generating circuit; wherein the source of the third transistor is coupled to said first ground potential through a fourth resistor; wherein the junction of said drain of said third transistor and the gate of said fourth transistor is adapted to receive said first supply voltage through a fifth resistor; wherein the gate of said fourth transistor is also adapted to receive said first supply voltage; wherein the drain of said fourth transistor is coupled to a cathode of a second diode; and wherein the anode of said second diode serves as the OFF output of said UP level shifter path and is coupled to receive said second supply voltage through a sixth resistor.