Patent ID: 7733182

Claim:
A follower circuit comprising: an input node for receiving an input voltage signal; an output node for driving a capacitive load based on the input voltage signal; a transistor M 1 having a gate terminal connected to the input node for receiving the input voltage signal, a source terminal connected to the output node, and a drain terminal; a feedback loop comprising a second transistor M 2 , a third transistor M 3 and a fourth transistor M 4 , wherein: the gate and source terminals of the second transistor M 2 are connected to a current source I 2 , and the drain terminal of the second transistor M 2 is connected to the output node; the source terminal of the third transistor M 3 is connected to the current source I 2 and the drain terminal of the third transistor M 3 is connected to a current source I 0 ; the gate terminal of the fourth transistor M 4 is connected to the drain terminal of the third transistor M 3 , the drain terminal of the fourth transistor M 4 is connected to the output node, and the source terminal of the fourth transistor M 4 is connected to a ground; and a replica bias circuit for providing a voltage bias signal to the gate terminal of the third transistor.