Patent ID: 8024735

Claim:
An apparatus comprising: logic circuitry to determine fairness of execution of a first thread relative to execution of a second thread based on a single value stored in a fairness counter, wherein the fairness counter is to be incremented in response to execution of one of the first thread or second thread and is to be decremented in response to execution of another one of the first thread or second thread, wherein the fairness counter is to be incremented or decremented in response to an execution event corresponding to the first thread or second thread, the event comprising: processor cycles, weighted processor cycles, or weighted instruction counts, logic circuitry to identify a next thread for execution based on the determined fairness and an execution information signal that indicates information about currently executing threads, wherein the logic circuitry to identify the next thread is to cause generation of a next thread signal to cause a processor to execute the next thread; and logic to determine forward progress of a plurality of executing threads based on values stored in respective forward progress counters and a switch stimulus type from a plurality of switch stimulus types, wherein a value of a forward progress counter is to indicate whether to permit a voluntary switching out of a corresponding thread, and wherein the first thread and the second thread are distinct.