Patent ID: 7964974

Claim:
An electronic chip package comprising: an electronic chip comprising a top surface having a first contact pad and a second contact pad formed thereon so as to be free of an intervening contact pad therebetween; a first dielectric layer coupled to the electronic chip; a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween; a first and a second cover pad at a first and second position, respectively, along the dielectric boundary; a first metal interconnect formed along a first multi-layer via and coupled to the first cover pad and the first contact pad, the first multi-layer via extending through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad; and a second metal interconnect formed along a second multi-layer via and coupled to the second cover pad and the second contact pad, the second multi-layer via extending through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.