Patent ID: 7750710

Claim:
A circuit comprising: a PLL circuit generating an oscillating signal; and a delay circuit receiving the oscillating signal and generating a delayed signal from the inputted oscillating signal; the PLL circuit including a frequency variable oscillator including a first delay element of which delay time as a concomitant of signal propagation is controlled by the delay time control signal and a phase inverting element inverting a phase of the oscillating signal, the delay circuit including: a series of second delay elements delaying the oscillating signal supplied with the delay time control signal from the frequency variable oscillator; an adjusting element, connected in series to the series of the second delay elements, to which the oscillating signal is propagated; and a current source supplying a drive current of the adjusting element; wherein the delay time as the concomitant of the signal propagation in the adjusting element is controlled by an adjusting signal different from the delay time control signal, the adjusting signal sets a value of the drive current supplied from the current source to a current value determined from the current value for driving the phase inverting element and from a ratio of the number of the second delay elements included in the delay circuit to the number of the first delay elements included in the frequency variable oscillator.