Patent ID: 6861313

Claim:
A fabrication method of a semiconductor memory device comprising the steps of: providing a silicon substrate including a gate that extends in a first direction and contact pads; forming a second inter-insulation layer on the silicon substrate; etching the second inter-insulation layer to form a storage node contact exposing a first one of the contact pads, a cross-sectional length of the bottom of the storage node contact in the first direction and in a second direction is longer than a cross-sectional length of the first contact pad in the first direction and in the second direction, respectively; forming a contact plug in the storage node contact that is connected to the first one of the contact pads; etching the second inter-insulation layer to form a bit-line pattern with a groove shape; etching the second inter-insulation layer to form a bit-line contact exposing a second one of the contact pads; and forming a damascene bit-line within the bit-line pattern that crosses the gate in the second direction, the bit line connected with the second one of the contact pads through the bit-line contact.