Patent ID: 7279947

Claim:
A pulse width modulation (PWM) buffer circuit comprising: a duty cycle converting circuit for receiving a first PWM signal and then generating a duty cycle reference voltage based on a first duty cycle of the first PWM signal, wherein the duty cycle reference voltage is a one-to-one mapping function of the first duty cycle, wherein the duty cycle converting circuit comprises: a transistor having a gate for receiving the first PWM signal and a source coupled to ground; a first resistor connected between a drain of the transistor and a voltage source; a diode having a P electrode connected to the drain of the transistor; a second resistor connected between an N electrode of the diode and the ground; a first capacitor connected between the N electrode of the diode and the ground; a first operational amplifier having a non-inverting input terminal connected to the N electrode of the diode; a third resistor connected between an inverting input terminal of the first operational amplifier and the ground; a fourth resistor connected between the inverting input terminal of the first operational amplifier and an output terminal of the first operational amplifier; and a fifth resistor connected between the output terminal of the first operational amplifier and the frequency-fixed PWM signal generating circuit; and a frequency-fixed PWM signal generating circuit, coupled to the fifth resistor, for receiving the duty cycle reference voltage and then outputting a second PWM signal having a fixed frequency, wherein the second PWM signal has a second duty cycle determined on the basis of the duty cycle reference voltage, and the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.