Patent ID: 7028209

Claim:
A method of transferring clock signals between buses, comprising the sequential operations of: a) detecting that a first external device has driven a first clock line of a first bus connected to said first external device from a first logic state to a second logic state; b) driving said first clock line and a second clock line of a second bus connected to a second external device to said second logic state by a control circuit; c) releasing said second clock line of said second bus by said control circuit after a predetermined time period; d) monitoring said second clock line; e) holding said first clock line of said first bus at said second logic state by said control circuit as long as said second clock line of said second bus is held at said second logic state by a second external device; and f) releasing said first clock line of said first bus by said control circuit when said second clock line of said second bus is released by said second external device.