Patent ID: 8908418

Claim:
A semiconductor device comprising a first memory module and a second memory module, wherein the first memory module includes: a plurality of first word lines extending in parallel in a first direction; a plurality of first bit lines extending in parallel in a second direction crossing the first direction; and a plurality of first SRAM memory cells located at the intersections of the first word lines and the first bit lines, wherein the second memory module includes: a plurality of second word lines extending in parallel in a third direction; a plurality of second bit lines extending in parallel in a fourth direction crossing the third direction; and a plurality of second SRAM memory cells located at the intersections of the second word lines and the second bit lines, wherein the first memory module further includes: a plurality of first memory cell power supply lines extending in parallel in the second direction to supply power to the first SRAM memory cells; and a first write assist circuit for discharging the electric charge of the first memory cell power supply line corresponding to the first SRAM memory cell to be written in the write operation for a first period, wherein the second memory module further includes: a plurality of second memory cell power supply lines extending in parallel in the fourth direction to supply power to the second SRAM memory cells; and a second write assist circuit for discharging the electric charge of the second memory cell power supply line corresponding to the second SRAM memory cell to be written in the write operation for a second period, wherein the number of the first word lines is greater than the number of the second word lines, and wherein the first period is longer than the second period.