Patent ID: 8218391

Claim:
An integrated circuit memory comprising: a clock signal input configured to receive a clock signal; a chip enable signal input configured to receive a chip enable signal; memory circuitry configured to store data values; clock control circuitry coupled to said memory circuitry, said clock signal input and said chip enable signal input and configured such that: (i) when said chip enable signal has a first value, said clock control circuitry is responsive to said clock signal to generate one or more control signals for controlling an access operation for accessing one or more data values stored within said memory circuitry; and (ii) when said chip enable signal has a second value, said clock control circuitry blocks generation of said one or more control signals in response to said clock signal; and power control circuitry coupled to said memory circuitry and said chip enable signal input and configured such that: (i) when said chip enable signal has said second value, said power control circuitry controls power supply circuitry of at least a portion of said memory circuitry to switch said portion of said memory circuitry to a low power state in which said portion of said memory circuitry is not able to operate; and (ii) when said chip enable signal has said first value, said power control circuitry controls said power supply circuitry of said portion of said memory circuitry to switch said portion of said memory circuitry to an operating state in which said portion of said memory circuitry is able to operate and having a higher power consumption than said low power state.