Patent ID: 8533565

Claim:
A cache memory controller comprising: a data detecting unit that detects a write address of a cache memory into which store data is to be stored including first store data to be stored in the cache memory and second store data not to be stored in the cache memory, the data detecting unit holding the first store data in a store buffer, when the store data is transmitted from an execution unit; a data determining unit that determines whether first existing data to be overwritten by the first store data and second existing data not to be overwritten by the second store data exist in the write address of the cache memory; an existing data obtaining unit that obtains the second existing data, and holds the obtained second existing data in a fetch register when the data determining unit determines that the second existing data exists in the write address of the cache memory; a store data writing unit that concatenates the first store data held in the store buffer and the second existing data held in the fetch register to generate concatenated store data, stores the generated concatenated store data in a write buffer and writes the concatenated store data stored in the write buffer into the write address of the cache memory; and an ECC generating unit that generates an error correcting code of the concatenated store data written in the write address of the cache memory.