Patent ID: 7136771

Claim:
A testing circuit comprising: m (m is an integer of 2 or more) block test units, each of which compares a first data of n (n is a positive integer) bits with a reference data of said n bits for each corresponding bit, and outputs a comparison result as a test circuit output signal based on a output control signal, wherein said first data is outputted from corresponding one of m object circuits for a test; and a first logical processing unit which judges whether or not said all of m said test circuit output signals indicate that said first data is coincident with said reference data, and outputs a judgment result as a total judgment result signal based on said m test circuit output signals, wherein each of said m block test units includes: a block judging unit which compares said first data with said reference data for each corresponding bit to judge whether said first data is coincident with said reference data, and outputs a comparison result as a block judgment result signal, and a block output selecting unit which outputs one of said block judgment result signal and a predetermined standard signal as said test circuit output signal, wherein a determination which one of said block judgment result signal and said predetermined standard signal to use as said test circuit output signal is based on said output control signal.