Patent ID: 7613960

Claim:
A semiconductor device test apparatus comprising: a test processor which applies a test signal to a semiconductor memory device under test and obtains information about defective memory cells from a response signal; and a repair analysis computing unit which performs repair analysis of the defective memory cell information to determine whether the defective memory cells are repairable; wherein the repair analysis computing unit comprises: a general-purpose repair analysis part; and a fail memory storing the defective memory cell information; and wherein the general-purpose repair analysis part comprises: (1) a memory repair analysis program storage storing a general-purpose memory repair analysis program which is designed to perform, based on regular repair conditions, repair analysis of the defective memory cell information for regular type memory devices that have no specific redundancy structure and have said regular repair conditions, said memory repair analysis program comprising operations constituting a process of the repair analysis for the regular type memory devices and including user function insertion points between the individual operations; (2) a user analysis program storage storing a user analysis program which is designed to perform, based on specific repair conditions, repair analysis of the defective memory cell information for a specific type memory device other than the regular type memory devices that has a specific redundancy structure and has the specific repair conditions, said user analysis program comprising user functions that are to be inserted to the user function insertion points of the memory repair analysis pro gram to obtain analysis data from the respective user function insertion points and to make a change to the thus obtained analysis data so as to perform the repair analysis based on the specific repair conditions; (3) a data storage storing data necessary for executing the memory repair analysis program; and (4) an analysis control part, wherein the analysis control part comprises: (a) means for performing, when a regular type memory device is subjected to repair analysis, repair analysis for the regular type memory device in accordance with the memory repair analysis program based on the regular repair conditions, and (b) means for performing, when the specific type memory device is subjected to repair analysis, repair analysis for the specific type memory device in accordance with the memory repair analysis program based on the regular repair conditions, and the user functions of the user analysis program which are inserted to the user function insertion points of the memory repair analysis program based on the specific repair conditions.