Patent ID: 7271085

Claim:
A method of fabricating a semiconductor interconnect structure, the method comprising: forming a first metal plug in contact with a silicide layer of a substrate assembly and in a first opening defined by a first layer of photoresist, wherein the silicide layer comprises at least one of the group consisting of a platinum silicide, a palladium silicide, a cobalt silicide and a tungsten silicide, and wherein the first metal plug is formed to include a planar top surface having a first cross-sectional area; forming a first metal layer in contact with the first metal plug and in a second opening defined by a second layer of photoresist; forming a second metal plug in contact with the first metal layer and in a third opening defined by a third layer of photoresist, wherein the second metal plug is formed to include a planar top surface having a cross-sectional area that is greater than the first cross-sectional area; forming a second metal layer in contact with the second metal plug and on the third layer of photoresist; and removing the first, second and third layers of photoresist.