Patent ID: 7825846

Claim:
An apparatus comprising: a current source; a first input transistor having a first passive electrode, a second passive electrode and a control electrode, wherein the first input transistor receives a first input voltage through its control electrode and that is coupled to the current source at its first passive electrode; a second input transistor having a first passive electrode, a second passive electrode and a control electrode, wherein the second transistor receives a second input voltage through its control electrode and that is coupled to the current source at its first passive electrode; a first output transistor that is coupled to the second passive electrode of the first input transistor at its control electrode; a second output transistor that is coupled to second passive electrode of the second input transistor at its control electrode; a bias transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the bias transistor is coupled to the second passive electrode of the first output transistor and the second passive electrode of the second output transistor; an error correction transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the error correction transistor is coupled to the control electrode first output transistor, and wherein the second passive electrode of the error correction transistor is coupled to the second passive electrode of the bias transistor; and a resistor that is coupled between the second passive electrode of the bias electrode and ground, wherein the resistor has a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.