Patent ID: 7051309

Claim:
A system, comprising: (a) at least one interfacing module for digitizing a multi-channel data stream into a plurality of multi-channel data sets, wherein each multi-channel data set in the plurality of multi-channel data sets represents a discrete time interval; each multi-channel data set in the plurality of multi-channel data sets comprises a plurality of data signals; said at least one interfacing module is configured to assign a time stamp to each data signal in each multi-channel data set; and said at least one interfacing module is configured to determine a property, other than said time stamp, of each data signal in each multi-channel data set; (b) a processor complex in electrical communication with said at least one interfacing module such that said processor complex receives ones of said multi-channel data sets in said plurality of multi-channel data sets from said at least one interfacing module at said discrete time interval, the processor complex comprising a plurality of channels, each channel in said plurality of channels adapted to receive one or more signals in said multi-channel data set, each channel comprising: at least a first processor and a second processor; wherein said first processor and said second processor each respectively have an input port and an output port; said first processor is associated with a bypass switch and a bypass register, said bypass switch having (i) a first state that causes a signal in said multi-channel data set to bypass said first processor and be stored in said bypass register and (ii) a second state that causes a signal in said multi-channel data set to be input into said first processor; and the input port of the second processor is adapted to receive data corresponding to one of said plurality of signals from the output port of the first processor; and (c) at least one decision module adapted to receive and analyze processed data from all or a portion of the channels in said plurality of channels.