Patent ID: 8693277

Claim:
A semiconductor device comprising: a first chip outputting a bank address signal and an active signal; and a plurality of second chips stacked on the first chip, each of the second chips including a plurality of memory banks each selected based on the bank address signal, selected one or ones of the memory banks being brought into an active state in response to the active signal, wherein each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state, and the first chip activates a bank active signal when at least one of the local bank active signals is activated, wherein each of the second chips includes a substrate and a plurality of penetration electrodes penetrating through the substrate, the penetration electrodes including a plurality of first penetration electrodes and a plurality of second penetration electrodes, the bank address signal and the active signal are supplied from the first chip to the second chips via the first penetration electrodes, and the local bank active signals are supplied from the second chips to the first chip via the second penetration electrodes.