Patent ID: 7646657

Claim:
A semiconductor memory device comprising: a memory cell array which has a plurality of memory cells arrayed in row and column directions; a word line which is connected to the plurality of memory cells arrayed in the column direction; a row decoder which is connected to the word line; a bit line which is connected to the plurality of memory cells arrayed in the row direction; a sense amplifier which is connected to the bit line; a dummy cell array which has a plurality of dummy cells arrayed in the row direction and is arranged between the row decoder and the memory cell array; a dummy bit line which is connected to the plurality of dummy cells arrayed in the row direction; a sense amplifier activation circuit which outputs a sense start signal for setting a sense start timing of the sense amplifier in accordance with an output from the dummy bit line; and a signal interconnection which is arranged between the sense amplifier activation circuit and the sense amplifier to transmit the sense start signal, wherein a signal delay of the word line is set to be equal to a signal delay of the signal interconnection which transmits the sense start signal.