Patent ID: 8184764

Claim:
A shift register comprising a plurality of shift register stages {S N }, N=1, 2, . . . , M, M being a nonzero positive integer, wherein each of the plurality of shift register stages, S N , comprises: (a) a first input; (b) a second input; (c) a third input for receiving a first clock signal, CK; (d) a fourth input for receiving a second clock signal, XCK; (e) a fifth input for receiving a first supply voltage, VDD; (f) a sixth input for receiving a second supply voltage, VSS; (g) an output for providing an output signal, OUT(N), therefrom; (h) a first transistor T 1 having a gate electrically connected to the first input, a drain, and a source electrically connected to the gate; (i) a second transistor T 2 having a gate electrically connected to the third input, a drain, and a source electrically connected to the drain of the first transistor T 1 ; (j) a third transistor T 3 having a gate electrically connected to the drain of the second transistor T 2 , a drain electrically connected to the fifth input, and a source electrically connected to the output; (k) a fourth transistor T 4 having a gate electrically connected to the second input, a drain electrically connected to the drain of the first transistor T 1 , and a source electrically connected to the sixth input; (l) a fifth transistor T 5 having a gate, a drain electrically connected to the drain of the second transistor T 2 , and a source electrically connected to the sixth input; (m) a sixth transistor T 6 having a gate electrically connected to the gate of the fifth transistor T 5 , a drain electrically connected to the output OUT, and a source electrically connected to the sixth input; (n) a seventh transistor T 7 having a gate electrically connected to the fourth input, a drain electrically connected to gate of the fifth transistor T 5 , and a source electrically connected to the source of the fifth transistor T 5 ; and (o) an eighth transistor T 8 having a gate, a drain electrically connected to the source of the seventh transistor T 7 , and a source electrically connected to the gate and the fifth input (p) a first capacitor C 1 electrically connected between the source of the second transistor T 2 and the output; and (q) a second capacitor C 2 electrically connected between the gate of the third transistor T 3 and the output.