Patent ID: 8707225

Claim:
A method of designing an integrated circuit including a subtraction arithmetic function, the method comprising: generating, with a processor, a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector, including generating a netlist of a reduced full subtractor cell, the netlist of the reduced full subtractor cell including an exclusive-NOR gate evaluating a shared Boolean expression for generation of a sum bit output and a carry bit output; replicating the netlist of the reduced full subtractor cell for all bits of the area-efficient subtractor but for the least significant bit; and selecting one of a plurality of differing netlists of different subtractor cells for the least significant bit of the area-efficient subtractor in response to a value of a flex bit; wherein each of the plurality of differing netlists of the different subtractor cells has a different combination of Boolean logical gates, and the value of the flex bit is further subtracted from the second input vector.