Patent ID: 8855399

Claim:
A system of inspecting wafer area using a reference wafer area, the system comprising: a first input interface to obtain: calibration information including respective reference displacements of multiple frames comprised in the reference wafer area, and a target database including, for each out of multiple targets in each of the multiple frames, a target image of a given target and location information determined in design data coordinates with respect to the frame in which the given target is included, wherein the inspected wafer area and the reference wafer area are characterized by the same targets in corresponding frames; a second input interface to obtain a scanned image of the inspected wafer area; a correlator to define a search window in the scanned image for each out of multiple targets of the database, each search window defined based on the reference displacement of the frame in which the target is included; to calculate, for each out of the multiple targets, a target run-time displacement based on a correlation of the target image of a given target to at least a portion of an area of the scanned image which is defined by the search window corresponding to the given target, the target run-time displacement indicative of displacement of the corresponding scanned image in the design data coordinates; and to determine a frame run-time displacement in the inspected wafer area for each of multiple run-time frames based on the target run-time displacements determined for multiple targets in the respective run-time frame; and a processor to generate inspection results for the inspected wafer area, based on the frame run-time displacements, thereby positioning inspection data in the design data coordinates independently for each frame.