Patent ID: 8916466

Claim:
A method for manufacturing a semiconductor device, said method comprising: forming grooves and vias in order to form a plurality of dual damascene wirings in a prescribed area within an insulating film formed above a semiconductor substrate; forming a diffusion prevention layer on a surface of the grooves and vias; forming a lower-layer copper or copper alloy film on the diffusion prevention layer to a thickness that is less than a thickness allowing for a complete filling of all vias connected to a wiring of said wirings, disposed in the grooves, that is five or more times as wide as a via diameter, and is equal to or greater than a thickness allowing for a complete filling of all vias connected to another wiring of said wirings, disposed in the grooves, that is less than five times as wide as the via diameter; forming on the lower-layer copper or the copper alloy film another copper alloy film comprising a copper alloy that comprises an added metallic element in a concentration that is higher than that of the added metallic element in the copper or the copper alloy film, the another copper alloy film filling a remaining part of the grooves above the wiring and extending below an upper surface of the lower-layer copper or the copper alloy film above said another wiring; and heating the added metallic element contained in the another copper alloy film to diffuse throughout the lower-layer copper or the copper alloy film.