Patent ID: 7432583

Claim:
A semiconductor package comprising: a die having top and bottom surfaces, the die including a plurality of bonding pads on the top surface of the die; a first leadframe having a first plurality of contacts, at least some of the first plurality of contacts have a first surface substantially formed in one plane to form a first mounting plane for mounting of electrical components thereon; conductive wires electrically connecting the first plurality of contacts to the plurality of bonding pads on the top surface of the die; a first encapsulant material formed over the top die surface, the conductive wires, and at least a portion of the first plurality of contacts thereby encapsulating the bonding wires while leaving the first surface of the first plurality of contacts exposed, to thereby form an internal package; at least one electrical component mounted on the first mounting plane, the electrical component being electrically connected to at least some of the first plurality of contacts; a second leadframe having a second plurality of contacts, the electrical component being electrically connected to at least some of the second plurality of contacts; and a second encapsulant material that encapsulates at least portions of the electrical component, the second leadframe and the internal package.