Patent ID: 7446050

Claim:
A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching including notching in a polysilicon gate electrode etching process comprising the steps of: providing a semiconductor process water comprising a gate dielectric formed over a silicon substrate and a polysilicon layer formed over the gate dielectric; providing a hardmask layer over the polysilicon layer; carrying out a first reactive ion etch (RIE) step to etch through a thickness of the hardmask layer to expose the polysilicon layer to form a patterned hard mask for forming a gate electrode; carrying out a second RIE step to etch through a first thickness portion of the polysilicon layer including an RF source power and an RF bias power; carrying out a third RIE step to etch through a second thickness portion of the polysilicon layer to endpoint detection to expose portions of an underlying gate dielectric including using lower RF power compared to the second RIE step, said lover RF power selected from the group consisting of a lower RF source power and a lower RF bias power; and, then plasma treating the exposed gate dielectric and polysilicon layer in-situ with a plasma consisting of inert gas to neutralize an electrical charge imbalance.