Patent ID: 7076683

Claim:
A clock control circuit of a data transfer control device having a state controller which controls switching between states of a host and a peripheral on the basis of state transition of a first device which operates as a host in a default state or state transition of a second device which operates as a peripheral in a default state, the clock control circuit comprising: an oscillation circuit which generates a reference clock signal for a clock signal supplied to each section of the data transfer control device, a clock output control circuit which generates an output control signal which controls an oscillation output of the oscillation circuit, and an activation circuit which activates the oscillation circuit based on a resume trigger signal generated based on a line state which is a state of a data signal line connected with a connection partner when data transfer from the connection partner is suspended in the state transition of the first device operating as a peripheral, wherein the clock output control circuit performs oscillation control to suspend an oscillation operation of the oscillation circuit based on the output control signal when data transfer from a connection partner is suspended in the state transition of the second device operating as a peripheral, and omits the oscillation control of the oscillation circuit in a suspend state of the first device.