Patent ID: 7911001

Claim:
A method for forming a self-aligned, dual stress liner for complementary metal oxide semiconductor (CMOS) devices, the method comprising: providing a semiconductor substrate comprising first and second device regions formed on an active surface of the semiconductor substrate and separated by an isolation region, the first and second device regions including respective first type and second type transistor devices; forming a first stress liner layer over the first and second device regions conformally covering the first and second type transistor devices; forming a first insulating layer over the first stress liner layer; patterning the first insulating layer and first stress liner layer to remove portions of the first insulating layer and first stress liner layer over the second device region and thereby form a step structure defined by remaining portions of the first stress liner layer and first insulation layer stacked over the first device region, wherein the step structure comprise a substantially vertical sidewall disposed over the isolation region, which is defined by a patterned sidewall of the first insulating layer and a patterned sidewall of the first stress liner layer; forming a second stress liner layer over the first and second device regions to conformally cover the second type transistors in the second device region and cover an upper surface and the vertical sidewall of the step structure, wherein a portion of the second stress liner layer that abuts the patterned sidewall of the first insulating layer defines a sacrificial vertical pillar and wherein a portion of the second stress liner layer that abuts the patterned sidewall of the first stress liner layer defines a gapless interface between the first and second stress liner layers; forming a second insulating layer over the first and second device regions covering the second stress liner layer, wherein the second insulating layer does not contact the first insulating layer; planarizing the semiconductor substrate surface to a level above the first and second transistor devices that is sufficient to remove the sacrificial vertical pillar overlying the gapless interface between the first and second stress liner layers disposed in the isolation region, wherein planarizing the semiconductor substrate surface comprises: performing an unselective chemical mechanical polishing (CMP) process to recess the first and second insulating layers and the sacrificial vertical pillar to a level below a portion of the second stress liner layer overlaying the upper surface of the step structure, such that the height of the first and second insulating layers over the semiconductor substrate is uniform across the first and second device regions.