Patent ID: 8823101

Claim:
An ESD protection semiconductor device comprising: a substrate; fins formed on the substrate, each of the fins being a semiconductor layer, the fins being located separately from one another; a gate insulating film formed on side surfaces of the fins; a gate electrode formed on the gate insulating film, the gate electrode including a gate contact portion to supply an electric signal, the gate electrode extending to cross over the fins; first drain regions and first source regions formed in the respective fins, each of the first drain regions and the corresponding one of the first source regions being provided so as to sandwich each of portions of the fins located below the gate electrode, the first drain regions being electrically connected to one another, the first source regions being electrically connected to one another; a drain contact portion formed on the substrate to supply an electric current to the first drain regions; a source contact portion formed on the substrate to connect the first source regions to a power supply; and a terminal to connect with outside and an internal circuit, wherein the fins, the gate insulating film, the gate electrode, the first drain regions and the first source regions constitute insulated-gate field-effect transistors respectively, and a width of first one of the fins is larger than that of second one of the fins, the second one of the fins being more distant from the gate contact portion and the drain contact portion than the first one of the fins, wherein the gate contact portion and the drain contact portion are connected to the terminal, and wherein the fins have the same height and length substantially.