Patent ID: 7694042

Claim:
A digital logic processing device comprising: a first processing element and at least one subsequent processing element, wherein each processing element of the at least one subsequent processing element includes: an input FIFO for storing data, a processing unit for processing data from the input FIFO, and a clock controller circuit for controlling a clock signal supplied to the input FIFO and the processing unit, wherein the clock controller circuit includes a detector for detecting an entry into a clock-off state indicating a state of interrupting the clock signal, and for detecting an entry into a clock-on state indicating a state of supplying the clock signal; a first flip-flop for latching an output of the detector in synchronization with the clock signal; a second flip-flop for latching an inverted output signal of the first flip-flop in synchronization with an inversion of the clock signal; and an AND gate for receiving the clock signal and for outputting the clock signal to the input FIFO and the processing unit based on an output of the second flip-flop.