Patent ID: 8725935

Claim:
A method of operating a non-volatile memory system including a controller circuit and a memory circuit having an array of non-volatile memory cells, comprising: receiving a sequence of data from a host, where the host structures the said data as allocation units; writing the received sequence of data into a first section of the array in a series of binary format pages, wherein a size of allocation unit corresponds to multiple binary pages; folding said data written in binary format pages into the array in a multi-state format, wherein the folding includes: reading data from N of the binary format pages into registers associated with the array, where N is an integer greater than one; and subsequently performing a N-state per cell programming operation of the N pages from the registers into a second section of the array, wherein the N-state per cell programming operation includes a first phase and a second phase, and balancing by the controller circuit of the writing in binary format pages and subsequent folding of the sequence of data, including selectively interleaving first and second phases of the N-state per cell programming operation between writing in binary format pages, to provide uniform performance across different allocation units of the sequence of data.