Patent ID: 6839889

Claim:
A method of implementing a scaleable architecture for a communications system based on minimizing a total gate count for the communications system, the method comprising the steps of: (a) dividing a communications transmission process into a set of N individual transmission tasks (T 1 , T 2 , . . . TN); (b) determining a computational complexity (M 1 , M 2 , . . . MN) for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; (c) determining a number of gates and/or transistors required to implement each of said N individual transmission tasks using a hardware based computing circuit; and (d) determining a number of gates and/or transistors required to implement each of said N individual transmission tasks using a software based computing circuit; (e) determining a first effective number of MIPs per gate and/or transistor achievable with said hardware based computing circuit when performing each of said N individual transmission tasks; (f) determining a second effective number of MIPs per gate and/or transistor achievable with said software based computing circuit; (g) allocating X individual transmission tasks to said software based computing circuit, where 1>=X>N, so that said X individual transmission tasks are performed in software; and (h) allocating all remaining N-X individual transmission tasks to said hardware based computing circuit so that said N-X individual transmission tasks are performed using dedicated hardware logic; wherein steps (g) and (h) are performed by comparing said first effective number of MIPs with said second effective number of MIPs.