Patent ID: 7710791

Claim:
A non-volatile semiconductor memory device, comprising: a memory cell array including a plurality of memory transistors; an input circuit configured to control a voltage level of an internal reference voltage in response to a first Mode Register Set (MRS) trim code or a first electric fuse trim code and/or control a delay time of an internal clock signal in response to a second MRS trim code or a second electric fuse trim code, and configured to generate a first buffered input signal; a colunm gate configured to gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier configured to amplify an output signal of the memory cell array to output to the column gate, and configured to receive an output signal of the column gate to output to the memory cell array, wherein the input circuit includes an input buffer configured to buffer an input signal in response to the internal reference voltage, and configured to generate a second buffered input signal; a sampler configured to sample the second buffered input signal in response to the internal clock signal, and configured to generate the first buffered input signal; a reference voltage generating circuit configured to generate the internal reference voltage in response to the first MRS trim code or the first electric fuse trim code; and a first trim code generating circuit configured to generate the first MRS trim code and the first electric fuse trim code.