Patent ID: 8904367

Claim:
A method comprising: generating an intermediate representation (IR) of a program specification, the IR having a plurality of interconnected nodes forming a plurality of paths through the IR; storing the IR in a memory; scheduling, by a processor coupled to the memory, an execution order of at least some of the plurality of interconnected nodes across pipeline stages, the scheduling including: applying a scheduling algorithm bounded by an input time threshold, the applying performed at least twice, producing a final scheduled execution order of the at least some of the plurality of interconnected nodes of the IR, and specifying one or more pipeline registers based on the scheduling; inserting the one or more pipeline registers specified during the scheduling along one or more of the plurality of paths of the IR, the one or more pipeline registers inserted between adjacent ones of the pipeline stages; and generating hardware description language (HDL) code for the program specification based on the final scheduled execution order and the one or more pipeline registers.