Patent ID: 7302627

Claim:
A SIMD processor core for performing vector operations comprising: a) a set of vector registers wherein each vector register comprises N elements wherein the N elements comprising parts of one-dimensional vector and a two dimensional array and said set of vector registers are grouped together and are operably coupled to a plurality of read ports and plurality of write ports for accessing said set of vector registers at substantially the same time; and b) a plurality of arithmetic and logic processing units, each having one or two data inputs, wherein the inputs of each processing unit is operably coupled to read ports of said vector register file, and the output of these processing units are coupled to a write port of the vector register file; and c) Plurality of accumulator registers, the input of which are operably coupled to the output of processing units, and wherein the output of the accumulator registers are operably coupled to a write port of the vector register file, Wherein the SIMD processor executes one or more instructions conditionally based on a bit or combination of bits of a register Wherein certain SIMD instructions could process one or two inputs using the arithmetic and logic processing units, and these interim results accumulated to the plurality of accumulator registers using additive, subtractive or exclusive-OR logic type of operations, Whereby conditional vector execution and vector exclusive-OR operations of said SIMD processor is used to implement leap-forward LFSR calculations with substantially close to N times acceleration over a scalar processor calculation of the same.