Patent ID: 6846736

Claim:
A process for forming electrical interconnects for integrated circuits formed on a substrate having at least one surface for forming integrated circuits thereon, said process comprising: forming spaced adjacent conductive strips on said at least one surface of said substrate; depositing a doped glass layer over said spaced adjacent conductive strips and said at least one substrate surface to a thickness proportional to a spacing for forming coated strips and coated surfaces of said substrate, said doped glass layer selected from the group consisting of borophosphosilicate glass, borosilicate glass, phosphosilicate glass, and silicon dioxide; merging at least portions of opposing contoured surfaces of said deposited doped glass layer around at least portions of said spaced adjacent conductive strips and over at least portions of said coated surfaces of said substrate for forming at least one elongated passageway running coextensive with at least a portion of a length of said coated strips; reflowing said deposited doped glass layer for smoothing said deposited doped glass layer and for positioning said at least one elongated passageway; forming at least one opening in said at least one elongated passageway; and filling at least a portion of said at least one elongated passageway with a conductive material through said at least one opening and along at least a portion of said length of said coated strips for producing at least one electrical interconnect between at least two regions of at least one integrated circuit of said integrated circuits.