Patent ID: 6996645

Claim:
A multiprocessing system, comprising: a bus; a plurality of multiprocessors coupled to the bus with access to a common memory pool and adapted to provide cache line requests; and a cache memory arrangement; a control circuit coupled to the bus and to the cache memory arrangement, the control circuit adapted to determine whether a cache line referenced by a cache line request is present in the cache memory arrangement, generate an invalidate request in response to a cache line in a cache line request being absent from the cache memory arrangement, generate a defer request responsive to each cache line request, wherein a defer request indicates that the control circuit owns the cache line referenced by a cache line request, and combine each defer request and invalidate request that reference a common cache line into a single output request; a queue coupled to the control circuit and adapted to store each output request from the control circuit in a single queue entry; and; and a queue control circuit coupled to the queue and to the bus, the queue control circuit adapted to output to the bus at least one bus request for each queue entry, and in response to an output request in the queue being a combination of a defer request and an invalidate request, output to the bus an invalidate bus request and a respective defer bus request to each of the plurality of request generation units that provided a cache line request with the common cache line.