Patent ID: 8630110

Claim:
A semiconductor memory device comprising: a memory circuit, the memory circuit comprising: a first transistor, the first transistor comprising: a first terminal electrically connected to a data input line; a second terminal; a gate electrically connected to a clock signal line; and a semiconductor layer comprising an oxide semiconductor, a first capacitor comprising an electrode electrically connected to the second terminal of the first transistor; and a second transistor comprising a gate electrically connected to the second terminal of the first transistor and to the electrode of the first capacitor, a second capacitor configured to store electric charge for reading data retained in the memory circuit; a charge storage circuit electrically connected to a supply potential line, the charge storage circuit controlling storage of electric charge in the second capacitor; a data detection circuit configured to control conduction or non-conduction between an electrode of the second capacitor and a first terminal of the second transistor, a timing control circuit configured to cause the charge storage circuit and the data detection circuit to be alternately brought into a conductive state in accordance with toggling of a clock signal in a first period in which the clock signal is supplied to the clock signal line, and to generate a first signal that controls storage of electric charge in the second capacitor, the storage being conducted with the charge storage circuit, the first signal being generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a second period immediately after the supply voltage is supplied to the supply potential line; and an inverter circuit configured to output a potential obtained by inverting a potential of the electrode of the second capacitor.