Patent ID: 8039387

Claim:
A method comprising: forming a first dielectric layer over a semiconductor substrate; and then forming lower metal wiring over the first dielectric layer; and then forming a second dielectric layer over the entire surface of the first dielectric layer including the lower metal wiring; and then forming a via pattern including a plurality of via holes penetrating through the second dielectric layer and a plurality of via slits to space neighboring via holes apart from each other; and then forming metal plugs in the via holes, wherein the plurality of via slits are arranged in a zigzag pattern such that the plurality of via slits alternate with each other, wherein the via pattern is formed in a matrix, the matrix has a rectangular cross section, the width of each via slit is equal to a total combined width of at least five via holes, and a height of each via slit is equal to a total combined length of at least one via hole.