Patent ID: 7797467

Claim:
An apparatus comprising: a first circuit having inputs receiving a plurality of input signals, said first circuit encodes a priority of said plurality of input signals, wherein a first group of said plurality of input signals comprises a plurality of respective port priority signals, each of said plurality of respective port priority signals corresponding to a respective one of a plurality of ports, and a second group of said plurality of input signals comprises respective port request signals for said plurality of ports; and a second circuit having inputs receiving (i) one or more device priority signals and (ii) a control signal received from each of a plurality of master devices coupled to said plurality of ports, said second circuit generates said plurality of respective port priority signals in response to (i) said one or more device priority signals and (ii) said control signal received from each of said plurality of master devices coupled to said plurality of ports, wherein a priority represented by each of the respective port priority signals dynamically varies in response to the respective control signals from the plurality of master devices coupled to said plurality of ports, wherein said second circuit comprises a bank selection circuit to generate a bank selection signal in response to a configuration signal and an address signal, a bank inhibit circuit to generate an inhibit signal in response to said bank selection signal and a status signal, and a first logic circuit to generate one of said respective port request signals in response to said inhibit signal and a device request signal received from one of said master devices coupled to said plurality of ports.