Patent ID: 6909141

Claim:
A method for producing a multi-pillar vertical semiconductor transistor, the method which comprises; producing a series of layers on a substrate such that the series of layers includes layers of different electrical conductivities; forming a statistical mask with statistically distributed mask structures aver the series of layers; forming vertical pillar structures statistically distributed over the substrate from the series of layers by using the statistical mask to cause the vertical pillar structures to define a vertical direction and have respective layer zones with respective different electrical conductivities disposed along the vertical direction; forming a first electrical contact commonly electrically connected to the vertical pillar structures at base sides of the vertical pillar structures; producing insulation layers on circumferential wall regions of the vertical pillar structures for circumferentially insulating the vertical pillar structures; depositing an electrically conductive material between the vertical pillar structures provided with the insulation layers such that the electrically conductive material forms a second electrical contact; and depositing an electrically conductive contact material for realizing a third electrical contact such that the electrically conductive contact material electrically contacts capping sides of the vertical pillar structures.