Patent ID: 8067289

Claim:
A method comprising: forming an epitaxial layer over a semiconductor substrate; forming a first well region within said epitaxial layer; forming a first isolation layer and a third isolation layer at opposite sides of said first well region; forming a second isolation layer within said first well region between said first and third isolation layers; forming a second well region within said first well region between said third isolation layer and said second isolation layer; forming a first ion-implanted region within said second well region; forming a second ion-implanted region between said first ion-implanted region and said second isolation layer; forming a third ion-implanted region between said second isolation layer and said first isolation layer; diffusing said second well region including said first and second ion-implanted regions using a thermal treatment; and forming an accumulation channel between said diffused second well region and a region where a gate is to be formed, wherein said accumulation channel is formed in a process comprising at least one of a lower implant dose and a lower ion implantation energy than for said second ion-implanted region.