Patent ID: 7348595

Claim:
A semiconductor device comprising: a semiconductor wiring substrate, said semiconductor wiring substrate being composed of a semiconductor material, having a wiring layer; a plurality of chip IPs mounted on said semiconductor wiring substrate by being bonded thereto; a boundary scan test circuit provided in each of said chip IPs; an internal scan chain for an internal scan test provided in each of said chip IPs, a logic circuit which is a test object (DUT) in said chip IPs to be tested by said internal scan test; and wherein the boundary scan test circuit and the internal scan chain for an internal scan test are formed so as to be capable of performing an internal scan test simultaneously with each other for testing said test object (DUT), using test data for an internal scan test which is input from outside, and the boundary scan test circuit performs a boundary scan test in a boundary scan test mode and an internal scan test in an internal scan test mode.