Patent ID: 8543843

Claim:
A system adapted for use with a computer processor having a bus unit and one or more physical processor cores, the system comprising: a memory component adapted to store one or more virtual cores; and a virtual core management component adapted to map the one or more virtual cores to at least one of the physical cores to enable an execution of one or more programs, wherein the virtual core management component is configured to unmap one or more virtual cores from one or more physical cores in response to one or more virtual cores being put into a sleep state, wherein the one or more virtual cores include one or more logical states associated with the execution of the one or more programs, wherein the mapping comprises transferring the one or more logical states of the one or more virtual cores from the memory component to the at least one physical core, and wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and the bus unit based on the mapping of the virtual core.