Patent ID: 7733139

Claim:
A delay locked loop circuit, comprising: a phase-frequency detector outputting a difference signal by detecting a phase difference between an input clock signal and a feedback clock signal; a sampler outputting a sampled signal having a lower frequency than a frequency of the difference signal by delaying the difference signal output from the phase-frequency detector in accordance with the input clock signal, wherein the sampler comprises: a first flip-flop delaying the difference signal output from the phase-frequency detector in accordance with the input clock signal to output a first delay signal, a second flip-flop delaying the first delay signal output from the first flip-flop in accordance with the input clock signal to output a second delay signal, and an XNOR gate receiving the difference signal, the first delay signal and the second delay signal to output a logic signal as the sampled signal; a charge pump for generating a control voltage in accordance with the sampled signal output from the sampler; a bias generator for generating a bias voltage in accordance with the control voltage generated by the charge pump; and a voltage-controlled element controlled with the bias voltage generated by the bias generator to generate an output clock signal and to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal.