Patent ID: 8466007

Claim:
A method for fabricating a power semiconductor module comprising: providing an adhesive coated first dielectric layer having a plurality of first vias extending therethrough; mounting semiconductor devices while aligning contact pads of the semiconductor devices with the first vias; applying first metallization on the first dielectric layer, the first vias, and at least portions of the contact pads; patterning the first metallization; providing an adhesive coated second dielectric layer having a plurality of second vias extending therethrough, some of the second vias in the second dielectric layer corresponding to some of the first vias in the first dielectric layer; laminating the adhesive-coated surface of the second dielectric layer to the first dielectric layer; applying second metallization on the second dielectric layer, the second vias, and the first metallization to a combined thickness of at least twenty five microns; and patterning the second metallization.