Patent ID: 7737767

Claim:
A control circuit for a charge pump circuit including at least a single flying capacitor and at least a single output capacitor, comprising: a first group of switches including at least a single switch provided on a path which charges said flying capacitor using an input voltage; a second group of switches including at least a single switch provided on a path which charges said output capacitor using the electric charge accumulated in said flying capacitor; a pulse modulator which generates a pulse signal having a fixed duty ratio and a frequency which is adjusted such that a feedback voltage corresponding to the output voltage of said charge pump circuit is coincident with a predetermined first reference voltage; and a driver which receives said pulse signal and turns on one of said first and second groups of switches during the time periods corresponding to the high time periods of said pulse signal and turns on the other one of said first and second groups of switches during the time periods corresponding to the low time periods of said pulse signal; wherein said pulse modulator comprises: an error amplifier which amplifies the error between said feedback voltage and said first reference voltage and generates an error voltage; a charging/discharging capacitor which is fixed in electric potential at its one end; an electric current source which generates a variable electric current corresponding to said error voltage; a charging/discharging circuit which charges said charging/discharging capacitor with a charging current proportional to said variable current in a charging state and discharges said charging/discharging capacitor with a discharging current proportional to said variable current in a discharging state; and a charging/discharging controller which compares the capacitor voltage generated at the other end of said charging/discharging capacitor with a predetermined upper limit voltage and a predetermined lower limit voltage and puts said charging/discharging circuit into said discharging state if said capacitor voltage reaches said upper limit voltage and puts said charging/discharging circuit into said charging state if said capacitor voltage drops to said lower limit voltage; wherein the level of said pulse signal is changed at the timing of the transition between said charging state and said discharging state.