Patent ID: 7195980

Claim:
A method of manufacturing a semiconductor device exhibiting a high breakdown voltage, the method comprising the steps of: selectively forming a second region of a second conductivity type and a third region of a first conductivity type in the surface portion of a first region of the first conductivity type, the second region and the third region being spaced apart from each other; selectively forming a fourth region of the first conductivity type in the surface portion of the second region; selectively forming a fifth region of the second conductivity type in the surface portion of the first region between the second region and the third region; forming a first insulation film on the fifth region; forming a gate electrode above the extended portion of the second region extending between the fourth region and the first region, with a gate insulation film interposed between the extended portion of the second region and the gate electrode; forming a first main electrode on the fourth region; and forming a second main electrode on the third region; wherein the step of selectively forming the fifth region comprises: (1) introducing a predetermined amount of an impurity of the second conductivity type in the portion of the first region in which it is intended to form the fifth region; (2) dividing the intended portion of the first region into a plurality of sub-regions; (3) adding a further amount of the impurity of the second conductivity type to the sub-region nearer to the second region; and (4) thermally driving the impurity in the sub-regions collectively.