Patent ID: 7961512

Claim:
A method of operating a non-volatile memory including a memory array having addressable pages of memory cells and a plurality of data latches, where each memory cell of an addressed page has a set of corresponding data latches having capacity for latching a predetermined number of bits, the method comprising: performing a first operation on a designated group of one or more addressed pages using a first data set stored in the corresponding set of data latches; receiving a request for a second operation using ones of the corresponding set of data latches with data related to one or more subsequent memory operations on the memory array; during the first operation, determining that at least one latch of each set of data latches is available for the second operation; subsequently determining whether or not there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; and in response to determining that there are not a sufficient number of the corresponding set of data latches to perform the second operation during the first operation, delaying the second operation.