Patent ID: 7256622

Claim:
A logic circuit having an output for performing logical operations without a power supply and without complementary input signals, comprising: (a) a first type MOS transistor having a source, a drain and a gate, the source of the said first MOS transistor is coupled to a first input terminal, the source of the said first MOS transistor is also coupled to the gate of the said first MOS transistor, the gate of the said first MOS transistor is coupled to a gate of a second type MOS transistor, the drain of the said first MOS transistor is coupled to the output of the logic circuit and (b) a second type MOS transistor having a source, a drain and a gate, the source of the said second MOS transistor is coupled to a second input terminal, the gate of the said second MOS transistor is coupled to the gate of the said first MOS transistor, the drain of the said second MOS transistor is coupled to the output of the logic circuit. whereby logical operation of the two input signals applied to the said first and said second input terminals is performed.