Patent ID: 6996012

Claim:
A method for driving a non-volatile memory device including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein each memory cell includes a tunnel oxide layer, a floating gate pattern, a control gate pattern connected with the word line, first and second block oxide layers formed between the floating gate pattern and the control gate pattern, and first and second impurity diffusion layers formed in a semiconductor substrate at both sides of the floating gate pattern and connected with a common line and the bit line, comprising: floating the bit lines and the common line, applying a negative (−) voltage to the word lines, and applying a first voltage to the semiconductor substrate, to erase electrons injected to the floating gate patterns to the semiconductor substrate, and to induce some of electrons stored in the control gate patterns to the floating gate patterns by modified tunneling; applying a positive (+) voltage to the word line and the bit line of the selected memory cell, and applying a second voltage to the remaining word lines and bit lines, the common line and the semiconductor substrate, to program the electrons in the selected memory cell; and applying a reference voltage to the word line of the selected memory cell, applying a second positive voltage to the bit line of the selected memory cell, and applying the second voltage to the remaining word lines and bit lines, the common line and the semiconductor substrate, to read a program state of the selected memory cell.