Patent ID: 7285487

Claim:
A method of providing connections between a plurality of processing elements comprising: providing a plurality of first dimension interconnect paths, wherein some of the first dimension interconnect paths are coupled to processing elements; providing a plurality of first dimension interconnect switches, the plurality of first dimension interconnect switches connecting selected first dimension interconnect paths to other selected first dimension interconnect paths; configuring the plurality of first dimension interconnect paths and the plurality of first dimension interconnect switches to form one or more first dimension trees, each first dimension tree having one or more levels of first dimension parent-child hierarchy, wherein at least one processing element is connected to at least one first dimension child at a lowest level of the first dimension parent-child hierarchy and at least one first dimension child has a plurality of first dimension parents; providing a plurality of second dimension interconnect paths, wherein some of the second dimension interconnect paths are coupled to processing elements; providing a plurality of second dimension interconnect switches, the plurality of second dimension interconnect switches connecting selected second dimension interconnect paths to other selected second dimension interconnect paths; and configuring the plurality of second dimension interconnect paths and the plurality of second dimension interconnect switches to form one or more second dimension trees, each second dimension tree having one or more levels of second dimension parent-child hierarchy, wherein at least one processing element is connected to at least one second dimension child at a lowest level of the second dimension parent-child hierarchy and at least one second dimension child has a plurality of second dimension parents.