Patent ID: 7977720

Claim:
A semiconductor device comprising: a transistor that includes a gate, a source, and a drain; a first insulator disposed on the transistor; a first plug disposed in a first contact hole of the first insulator, the first contact hole being disposed on the source or the drain; a lower wiring disposed on the first plug; a second insulator disposed on the first insulator; a first layer disposed on the second insulator, the first layer including silicon and nitrogen; a second plug disposed in a second contact hole of the second insulator and in a third contact hole of the first layer, the second contact hole and the third contact hole being disposed continuously on the lower wiring; a lower electrode disposed on the second plug; a ferroelectric layer disposed on the lower electrode; an upper electrode disposed on the ferroelectric layer; a second layer disposed on a side of the lower electrode, the ferroelectric layer, and the upper electrode, and on a surface of the upper electrode, the second layer including alumina; a third insulator disposed on the second layer; a fourth contact hole of the second layer and a fifth contact hole of the third insulator being disposed continuously on the upper electrode; an upper wiring disposed on the third insulator and in the fourth contact hole and the fifth contact hole; a third layer disposed above the upper wiring, the third layer including alumina, TiAlN, TiAl, or TiN; a fourth insulator disposed on the third layer; and a plate line disposed on the fourth insulator, the plate line being connected to the upper wiring electrically.