Patent ID: 8627050

Claim:
A computer implemented method for performing a perform floating point operation (PFPO) instruction for converting any one of a Binary Floating-Point operand, a Hexadecimal Floating-Point operand or a Decimal Floating-Point operand, the method comprising: obtaining said PFPO instruction defined for a computer architecture, the PFPO instruction consisting of an operation code, the instruction having implied operands consisting of general register 0 (GR 0 ) and general register 1 (GR 1 ); and executing, by a processor, the obtained PFPO instruction, the executing comprising: responsive to a Test (T) bit of GR 0 being a 0, performing a) and b): a) performing a floating-point conversion function specified by a plurality of function fields of GR 0 to produce a result, wherein the function fields of GR 0 comprise a PFPO operation type code, a PFPO operand format code for operand 1 , a PFPO operand format code for operand 2 , an Inexact suppression control, an Alternate exception action control and a PFPO rounding method, wherein the floating-point conversion function specified is one of a plurality of specifiable floating-point conversion functions, wherein the computer is configured to execute installed floating-point conversion functions of the plurality of specifiable floating-point conversion functions; b) storing the result in GR 1 and setting a condition code, the condition code indicating whether the performing the floating-point conversion function specified encountered an exceptional condition; responsive to the T bit of GR 0 being a 1, performing c) and d): c) determining whether the floating-point conversion function specified by the plurality of function fields of GR 0 is an installed specifiable floating-point conversion function; and d) setting a condition code without storing a result, the condition code indicating whether the floating-point conversion function specified is an installed specifiable floating-point conversion function.