Patent ID: 8171230

Claim:
A method of changing a translation control entry (TCE) used by one or more input/output (I/O) device adaptors of a computer system to address system memory, comprising: receiving a request to change a selected one of a plurality of TCEs in a TCE table of the system memory, wherein each TCE in the TCE table has a respective change-in-progress control bit and each TCE in the TCE table has a respective non-cacheable control bit to indicate when caching of a corresponding TCE is to be prevented during TCE invalidation; writing a new TCE value to the selected TCE in the TCE table of the system memory; activating the change-in-progress control bit of the selected TCE in the TCE table of the system memory; refusing address translation services requests to retrieve translation information from the selected TCE while its change-in-progress control bit is in an active state regardless of the state of its non-cacheable control bit; after said writing and said activating, invalidating any copies of the selected TCE stored in address translation caches of the I/O device adaptors; and after said invalidating, deactivating the change-in-progress control bit of the selected TCE in the TCE table.