Patent ID: 7306991

Claim:
A method of fabricating a non-volatile memory cell, comprising: forming a charge trapping dielectric layer on a semiconductor substrate; forming a first sacrificial layer over the charge trapping dielectric layer; applying a mask to the first sacrificial layer to define lateral boundaries of a groove; removing that portion of the first sacrificial layer within the lateral boundaries defined by the mask to form the groove, the groove having a lower boundary that is substantially the upper surface of the charge trapping dielectric layer; forming a second sacrificial layer over the first sacrificial layer and the exposed charge trapping dielectric layer; forming a pair of spacers within the groove by anisotropically removing a portion of the second sacrificial layer, the pair of spacers being positioned against the respective lateral edges of the groove and defining therebetween lateral boundaries of a trench within the groove; removing the material of the charge trapping layer between the lateral boundaries defined by the spacers to form the trench, the trench having a lower boundary that is substantially the upper surface of the semiconductor substrate; depositing a gate dielectric layer in the trench; removing the spacers from the groove; forming a control gate layer overlying the charge trapping dielectric layer and the gate dielectric layer within the groove formed in the first sacrificial layer; and patterning the control gate layer and the remainder of the charge trapping layer that extends beyond lateral edges of the control gate layer.