Patent ID: 8724440

Claim:
A circuit comprising: a converter configured to sample a signal read from a storage medium to generate a sample, wherein the signal includes a physical address of data read from a track on the storage medium; a timing control device configured to generate a clock signal based on a deviation of the track from a reference line; a first scaling device configured to generate a first scale factor based on the clock signal; a first multiplier configured to multiply the sample by the first scale factor to generate a first scaled sample; a first integrator configured to integrate the first scaled sample over a period of the clock signal to generate a first resultant value; a comparator configured to compare the first resultant value to a threshold to generate an output, wherein the output indicates whether no phase imperfection exists in the first scaled sample; and a decoder configured to, based on the output of the comparator, decode the first resultant value to obtain the physical address of the data.