Patent ID: 6971083

Claim:
For use with a programmable logic device including one or more specialized multiplier blocks, each said specialized multiplier block comprising at least one multiplier and at least one other arithmetic element, a method of programming such a programmable logic device with a user design, said user design comprising a plurality of logic elements to be programmed, said method comprising: parsing a list of said logic elements to be programmed for said user design; identifying, in said list of logic elements to be programmed for said user design, logic elements to be programmed that are related to said specialized multiplier blocks; and preprocessing said logic elements to be programmed that are related to said specialized multiplier blocks prior to processing said list of logic elements to be programmed for said programmable logic device, to make a preliminary assignment, to said one or more specialized multiplier blocks, of said logic elements to be programmed that are related to said specialized multiplier blocks; wherein: said preprocessing comprises creating a subset within said list of logic elements to be programmed, said subset comprising preprocessed logic elements to be programmed specifying functions to be performed within said specialized multiplier blocks; and when said specialized blocks include input registers adapted to create input shift register chains, said preprocessing further comprises: recognizing, among said identified logic elements to be programmed, a group of first logic elements to be programmed each of which relates to a respective specialized multiplier function, and a group of second logic elements to be programmed each of which relates to a respective register, for forming an input shift register chain for said specialized multiplier functions recognized by said group of first logic elements to be programmed, and combining each logic element to be programmed in said group of first logic elements to be programmed with a respective logic element to be programmed in said group of second logic elements to be programmed to create a group of third logic elements to be programmed each of which represents a respective specialized multiplier function combined with an input register for chaining to a respective other input register.