Patent ID: 8234483

Claim:
An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising: at least one memory device; and at least one packet processor uniquely associated with each of the at least one memory device, and the at least one packet processor adapted to provide an external device read and write access to the at least one memory device via at least one high-speed packet switched serial interface, by decapsulating address, data and control information, contained in a packet conforming to a predefined serial protocol format received from the external device, and encapsulating data including the decapsulated address and control information into another packet conforming to the said serial protocol format for transmission to the said external device, in response to the received packet, and wherein the at least one memory device and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible, such that the high-speed packet switched serial interface receives the said packet from and transmits the said packet to the said external device.