Patent ID: 7047272

Claim:
A digital system, comprising a processing engine with an arithmetic unit, wherein the arithmetic unit comprises: arithmetic circuitry for performing an arithmetic operation to generate an arithmetic result of two or more operands; zero anticipation circuitry for anticipating a logical zero on N least significant bits of the result by encoding a portion of the two or more operands, such that the zero anticipation circuitry operates on the two or more operands in parallel with the arithmetic circuitry; and unbiased rounding circuitry for forcing a predetermined logic value on the (N+1)th least significant bit of the result, the unbiased rounding circuitry being responsive to a zero anticipation output signal from the zero anticipation circuitry, such that if a logical zero is not anticipated on the N least significant bits of the result then the (N+1)th least significant bit of the result is not modified.