Patent ID: 8599984

Claim:
A memory device comprising: a delay locked loop; and an input for receiving an external clock signal for routing to the delay locked loop, the delay locked loop being configured to synchronize an internal clock signal with the external clock signal, the delay locked loop comprising: a digital delay circuit configured to enable digital delay elements of the digital delay circuit in providing coarse phase adjustment in the delay locked loop, the digital delay circuit providing a coarse delayed differential clock signal; an analog delay circuit configured to provide fine phase adjustment in the delay locked loop in response to a control signal, the analog delay circuit receiving the coarse delayed differential clock signal and producing a fine delayed clock signal, the analog delay circuit comprising parallel symmetric loads to cause the fine delay, the control signal being operative to vary an effective resistance of the symmetric loads; circuitry to provide the fine delayed clock signal as the internal clock signal; a phase detector circuit configured to compare the external clock signal and the internal clock signal; and a lock detector circuit in communication with the phase detector circuit and the analog delay circuit, the lock detector circuit being configured to: i) hold the digital delay circuit at a fixed delay; and ii) provide the control signal to the analog delay circuit.