Patent ID: 7561999

Claim:
An apparatus for verifying hardware and software for controlling the hardware, the apparatus comprising: a computer including a processor and memory storing a program of instructions for; a hardware model and an expected value calculation model of the hardware, the hardware model being verified by the computer; a logic simulator performing a simulation on the computer by using the hardware model and generating an expected value by using the expected value calculation model; an equivalence verification section verifying an equivalence of a result of the simulation and the expected value using the computer; and a software debugger debugging the software at different verification levels by using the expected value calculation model through an interface section, if the simulation result and the expected value match; wherein the expected value calculation model includes pieces of timing information, and wherein each of the pieces corresponds to a verification level of the software, and the verification level is one of a function accurate level, a transaction accurate level, or a cycle accurate level.