Patent ID: 7075510

Claim:
A semiconductor device comprising: a shift register having a plurality of register circuits; a scan direction switching circuit including a plurality of switching circuits, the scan direction switching circuit connected with the shift register via signal lines; and a plurality of NAND circuits, wherein each of the plurality of the register circuits having: an input terminal; a first inverter circuit electrically connected to the input terminal; a second inverter circuit electrically connected to the first inverter circuit; and an output terminal electrically connected to the second inverter circuit, wherein the first inverter circuit is clocked inverter circuit, wherein each of the plurality of register circuits outputs a timing pulse to one of right and left adjacent register circuits and a signal line of the register circuit, wherein the scan direction switching circuit controls that timing pulses are sequentially outputted to which of right and left adjacent register circuits according to a scan direction switching signal, and wherein each of the plurality of NAND circuits has: a first input terminal electrically connected to the output terminal of corresponding one of the plurality of the register circuits; and a second input terminal electrically connected to the output terminal of adjacent one of the corresponding one of the plurality of the register circuits.