Patent ID: 8284582

Claim:
A content addressable memory comprising: a memory array including a plurality of memory cells arranged in a matrix and each memory cell row of the memory array storing entry data to be retrieved; entry selecting means for selecting a corresponding entry in the memory array in accordance with a given entry designation signal; pre-search means for generating an entry designation signal for designating a corresponding entry in the memory array in accordance with search data and supplying the entry designation signal to the entry selecting means; a plurality of sense amplifier circuits for detecting and amplifying data stored in an entry selected by the entry selecting means on a sub-entry unit basis, each sense amplifier circuit being arranged for a respective column of said memory array; and a comparing/logic processing circuit for receiving the search data and output data having a predetermined bit width of the sense amplifier circuit, comparing the search data and the output data having the predetermined bit width of the sense amplifier circuit, and generating a signal indicative of a result of the comparison.