Patent ID: 7067382

Claim:
A method for fabricating a semiconductor device, comprising the steps of: a) forming a gate insulating film over an active region of a substrate; b) forming a silicon film over the gate insulating film; c) patterning the silicon film, thereby forming a gate electrode; d) performing ion implantation of an impurity using at least the gate electrode as a mask, thereby forming a source/drain region including a heavily doped impurity region; e) performing first thermal treatment for activating the impurity introduced into the gate electrode; and f) performing second thermal treatment for activating the impurity introduced into the gate electrode and the source/drain region at a higher temperature for a shorter time than the first thermal treatment is performed, wherein the active region includes an NMISFET formation region and a PMISFET formation region, wherein in the step c), a gate electrode of the NMISFET and a gate electrode of the PMISFET are formed, wherein in the step d), an n-type impurity and a p-type impurity are separately ion-implanted into the NMISFET formation region and the PMISFET formation region, respectively, wherein after the step b) and before the step c), an n-type impurity is ion-implanted into part of the silicon film located in the NMISFET formation region while introduction of an impurity is not performed to part of the silicon film located in the PMISFET formation region, and a p-type impurity is introduced into the gate electrode of the PMISFET.