Patent ID: 7700425

Claim:
An improvement in a method of forming a MOSFET device, said MOSFET device including a semiconductor substrate with a silicon surface, with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on said silicon surface, with the gate electrode stack comprising a gate electrode formed of gate polysilicon formed over a gate dielectric layer formed on said silicon surface, said gate polysilicon having a top; said method comprising the steps preformed in the sequence as follows: forming a cap layer composed of amorphous silicon on said top of said gate electrode layer; forming a patterned mask for patterning said gate electrode stack over said cap layer with said mask covering a portion of said cap layer; performing an etching process undercutting said cap layer peripherally under said mask thereby forming a notch in said cap layer below said mask with said notch having notch sidewalls; passivating said notch sidewalls; patterning said gate electrode stack in said pattern of said mask with an etching process; filling said notch with dielectric plugs formed of sidewall spacer material on sidewalls of said gate polysilicon with said dielectric plugs and sidewall spacers covering sidewalls of said gate with forming said sidewall spacers reaching along the sidewalls of the gate electrode stack to above the level where said plugs contact said gate polysilicon; and forming raised source/drain regions on top of said silicon surface aside from said sidewall spacers, whereby formation of spurious epitaxial growth of silicon nodules on said sidewalls of said gate dielectric during the formation of raised source/drain regions is avoided.