Patent ID: 7884466

Claim:
A semiconductor device having a double-sided electrode structure in which a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion; a resin is charged, for sealing, around and on the LSI chip to a height equal to that of the uppermost surface of the package substrate, the LSI chip being mounted in the recess portion of the package substrate and being connected to the multilayer wiring; wiring traces are formed on an upper surface of the charged resin such that the wiring traces are connected to terminal wiring traces connected to the multilayer wiring on a front face of the package substrate, and are connected to front-face bump electrodes for external connection on the upper surface of the resin; and on the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.