Patent ID: 6911847

Claim:
A logic circuit for performing a logic operation on n logic inputs expressed by n respective input differential signal pairs, where n is a plural integer, the logic circuit comprising: a control signal generating circuit section for converting said n pairs of input differential signals to n sets of differential control signal pairs, each of said sets formed of n differential control signal pairs which correspond in common to a specific input differential signal pair and having respective ones of n different level ranges, a current switching section including a pair of resistive elements each having a first terminal thereof connected to a first potential of a DC power source, and a plurality of current sources connected to a second potential of said DC power source for controlling current flow levels though respective current paths, and a multi-stage connection network connected to said current sources and connected at a pair of connection points to respective second terminals of said resistive elements for performing switching of said current paths to thereby generate a differential signal pair at said connection points, said network formed of a plurality of transistor pairs each having respective first terminals thereof connected together and respective second terminals thereof connected to one of said differential control signal pairs, and an output signal generating circuit section coupled to said connection points, for generating an output differential signal pair corresponding to said differential signal pair generated by said current switching section; wherein said transistor pairs are interconnected as n switching stages each comprising a plurality of said transistor pairs, said switching stages being connected in series between said connection points and said second potential of the power source, said switching stages being interconnected such that each of said current paths extends from one of said connection points through one transistor in each of said switching stages, wherein all transistor pairs of each said switching stage are controlled by respective differential control signal pairs each having a level range that is specific to said switching stage, wherein in each said transistor pair of an n th one of said switching stages respective common connections of said first terminals of said transistor pairs are coupled via corresponding ones of said current sources to said second potential, and wherein a third terminal of a first transistor of each of said transistor pairs of a first one of said switching stages is connected to a first one of said connection points and a third terminal of a second transistor of said each transistor pair of the first switching stage is connected to a second one of said connection points.