Patent ID: 7716424

Claim:
A processor-based system for aiding in the prefetching between a first level cache and a second level cache, comprising: a first level cache; a second level cache; a directory extension maintaining a plurality of entries for pages of the first level cache from which a plurality of lines have been ejected, and further maintains for each entry, a vector indicating which of the plurality of ejected lines of a corresponding page are prefetchable from the second level cache; and a prefetch score for each prefetchable ejected line indicating whether the prefetchable ejected line was referenced in a most recent access of the first level cache, wherein each prefetchable ejected line referenced in a most recent read-only access of the first level cache is assigned the prefetch score 1 and assigned the prefetch score 0 otherwise, wherein each page includes a plurality of lines, and wherein if the recently ejected line is ejected from the first level cache in a castout, the prefetch score indicates that the ejected line was referenced in the most recent read-only access of the first level cache, and the directory extension excludes the entry and a new entry is created in the directory extension for the associated page in a level within an equivalence class of the ejected line.