Patent ID: 7712002

Claim:
A test circuit for testing a basic logic block having at least two input terminals and at least two output terminals and at least one additional logic block having at least two input terminals and at least two output terminals, said basic logic block for receiving test data through said at least two input terminals thereof and outputting resultant data respectively through said at least two output terminal thereof in synchronism with a clock signal, and said at least one additional logic block for receiving test data through said at least two input terminals thereof and outputting resultant data through said at least two input terminals thereof in synchronism with said clock signal, said test circuit comprising: at least two basic bit holding and relaying units whose output terminals are connected to said at least two input terminals of said basic logic block, respectively; and at least two additional bit holding and relaying units whose output terminals are connected to said at least two input terminals of said additional logic block, respectively, wherein both of said basic and additional bit holding and relaying units operate in synchronism with said clock signal, each of said basic and additional bit holding and relaying units has a data input terminal, a scanning input terminal and a mode switching terminal, receives a data bit by bit selected from said test data or resultant data respectively supplied to said data input terminal and said scanning input terminal in accordance with a mode designation signal supplied to said mode switching terminal thereby to hold said data and then relay said data to said output terminal thereof, one of said basic bit holding and relaying units receives at said scanning input terminal thereof basic output data generated from the other of said basic bit holding and relaying units while an output data from said one of the basic bit holding and relaying units is supplied to said scanning input terminal of one of said additional bit holding and relaying units, an additional output data from said one of the additional bit holding and relaying units is supplied to said scanning input terminal of the other of said additional bit holding and relaying units, an external input data is supplied to said scanning input terminal of said other of the basic bit holding and relaying units, an output terminal of said other of the additional bit holding and relaying units is a test data output terminal, and said basic and additional bit holding and relaying units are respectively provided with signal delay circuits at a front stage thereof, said signal delay circuits respectively delaying said basic and additional input data.