Patent ID: 7892956

Claim:
A method of forming a vertical Field Effect Transistor (FET) comprising: forming an FET device comprising an FET channel region located between a doped source region and a doped drain region in a vertical semiconductor nanowire with said doped source region and said doped drain region formed in distal ends of said vertical semiconductor nanowire aside from said channel region by the following steps: forming a bottom source/drain electrode on a substrate; forming a bottom spacer layer composed of a dielectric or insulating material on said bottom source/drain electrode; forming a gate electrode layer or layers over said bottom spacer layer; forming an upper spacer layer composed of a dielectric or insulating material over said gate electrode layer or layers with said upper spacer layer having a top surface; creating a columnar pore extending down from said top surface through said upper spacer layer, said gate electrode layer or layers, and said bottom spacer layer to said bottom source/drain electrode; then etching through said columnar pore to form a recessed notch or pocket in said gate electrode layer or layers; then forming a conformal gate dielectric layer on surfaces of said columnar pore including said recessed pocket; then etching back said conformal gate dielectric layer from said surfaces of said columnar pore, leaving said gate dielectric layer in said recessed notch or pocket in said gate electrode layer; then filling said columnar pore with a semiconductor material by plating to form said vertical semiconductor nanowire therein having a bottom end formed on said bottom source/drain electrode; and then forming a top source/drain electrode in contact with a top end of said vertical semiconductor nanowire.