Patent ID: 8806414

Claim:
A method comprising: (a) generating a layout of an integrated circuit (IC) design using an electronic design automation (EDA) tool, the layout having a network of routing paths connecting at least two active layer devices of the IC design; (b) computing estimated parasitic capacitances of the routing paths of the network; (c) performing a first device level simulation of the network based on the at least two active layer devices and the estimated parasitic capacitances; (d) using the EDA tool to revise the layout or a device of the IC design if a result of the first device level simulation fails to satisfy an IC specification; wherein steps (b), (c) and (d) are performed one or more times before performing design rule checks and before performing layout-versus-schematic checks, until a result of the first device level simulation satisfies the IC specification; and (e) outputting the revised layout of the IC design to a non-transitory, machine readable storage medium after completion of steps (b) to (d), to be accessed by the EDA tool to perform design verification.