Patent ID: 7768327

Claim:
A delay locked loop (DLL) of a semiconductor device, comprising: a first delay line for delaying a first clock signal in synchronization with a first edge of an external clock signal to output a first delayed clock signal; a second delay line for delaying a second clock signal in synchronization with a second edge of the external clock to output a second delayed clock signal; a duty cycle corrector (DCC) for mixing phases of the first and second delayed clock signals to output a DLL clock signal with a corrected duty cycle, wherein the DCC includes a first phase mixer for mixing the phases of the first and second delayed clock signals to output the DLL clock signal and a second phase mixer for mixing the phases of the first and second delayed clock signals to output a second phase mixer clock signal; and a DCC controller for receiving the first and second delayed clock signals and for disabling both the mixing of the phases of the first and second delayed clock signals by the first phase mixer and the mixing of the phases of the first and second delayed clock signals by the second phase mixer in response to a determination that a phase difference between the first and second delayed clock signals is greater than a preset time.