Patent ID: 7688612

Claim:
A nonvolatile memory array of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns wherein the dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping of dual-sided charge-trapping nonvolatile memory cells that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor connected to the NAND series string, the nonvolatile memory array comprising: a plurality of braided bit lines connected such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with one pair of braided bit lines, such that a source/drain of the top select transistor is connected through a first conductive segment to a first bit line of the pair of braided bit lines and a source/drain of the bottom select transistor is connected to a second bit line of the pair of braided bit lines.