Patent ID: 8080472

Claim:
A metal line of a semiconductor device, comprising: an insulation stack layer on a semiconductor substrate that defines a metal line forming region which exposes a portion of the semiconductor substrate, wherein the insulation stack layer comprises: a first insulation layer formed directly on the semiconductor substrate; an etch stop layer formed directly on the first insulation layer; and a second insulation layer formed directly on the etch stop layer; a diffusion barrier on the metal line forming region of the insulation stack layer, the diffusion barrier having a stack structure including an Mo x Si y layer directly formed so as to cover a bottom of the metal line forming region and directly formed on sidewalls of the metal line forming region of the insulation stack layer and an Mo layer entirely stacked on the Mo x Si y layer such that the Mo layer is directly formed on the Mo x Si y layer in the bottom of the metal line forming region and directly formed on the sidewalls of the Mo x Si y layer in the metal line forming region; and a metal layer on the Mo layer of the diffusion barrier filling in the metal line forming region of the insulation stack layer without a seed layer interposed between the metal layer and the metal line forming region.