Patent ID: 7369629

Claim:
A demodulation circuit for demodulating an FSK signal which comprises a long bit having a long bit pulse length and a short bit having a short bit pulse length, the demodulation circuit comprising: a bit boundary detection section for detecting a bit boundary timing of each bit; and a bit determination section for making determination for each bit such that a relevant bit is determined to be a long bit when a threshold time period has passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit, and a relevant bit is determined to be a short bit when a threshold time period has not passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit, wherein the bit determination section includes an excess period signal generation section for generating an excess period signal which remains effective during a period within each bit, namely the period from a point at which the threshold time period has passed to the bit boundary timing at the trailing end of the bit, and determines if the bit is a long bit or a short bit based on presence or absence of a period when the excess period signal associated with the bit remains effective, and the excess period signal generation section includes a counter for counting a number of pulses of a clock signal with a reference timing at the bit boundary timing at the leading end of the bit, and a generator which generates, as the excess period signal, a signal which is effective in a period from a timing when a counting of a predetermined number of counts is completed to the bit boundary timing at the trailing end of the bit.