Patent ID: 8910004

Claim:
An information processing apparatus comprising: a bit inverting unit that inverts specific three bits of first data stored in a first storage area of a memory when the first storage area is secured as a heap area and inverts the specific three bits of second data stored in a second storage area of a memory when the second storage area is secured as the heap area, an information adding unit that adds first information to the first data by storing the first data in which the specific three bits are inverted by the bit inverting unit in the first storage area and adds second information to the second data by storing the second data in which the specific three bits are inverted by the bit inverting unit in the second storage area, the first information and the second information being the data in which a predetermined error is detected by performing an error detecting process of the first data and the second data respectively; a removing unit that removes the second information added to the second data by rewriting the second information with the error detecting information of the second data without rewriting the first information added to the first data when the second storage area out of the first storage area and the second storage area is configured to be usable; and an error detecting unit that performs an error detecting process of read-out data using information that is added to the read-out data in a case where the first data or the second data stored in the memory is read out and that determines a storage area which stores the read-out data in which the predetermined error is detected as an unusable area when the predetermined error is detected by the error detecting process of the read-out data.