Patent ID: 7386851

Claim:
A system executing on a microprocessor architectures for implementing dynamic lifetime reliability extension of said microprocessor architectures, the system comprising: a plurality of primary resources; a secondary resource pool having one or more secondary resources; a resource operational mode controller configured to selectively switch each of the primary and secondary resources between an operational mode and a non-operational mode, wherein the operational mode corresponds to performance of one or more tasks for which a given resource is designed to execute with respect to a microprocessor system and wherein the non-operational mode corresponds to a temporary lifetime extension process for at least one of suspending the aging of resources and extending the aging of resources; a resource mapper associated with the secondary resource pool and in communication with the resource operational mode controller, the resource mapper configured to map a secondary resource placed into the operational mode to a corresponding primary resource placed into the non-operational mode, and to un-map a secondary resource from a corresponding primary resource in the event the corresponding primary resource is placed back into the operational mode; and a transaction decoder configured to receive incoming transaction requests and, responsive to the resource operational mode controller, direct the requests to one of a primary resource in the operational mode and a secondary resource in the operational mode, the secondary resource mapped to an associated primary resource placed in the non-operational mode.