Patent ID: 7286377

Claim:
A dynamic random access memory (DRAM) device comprising: an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column; and a refresh circuit for controlling a data refresh rate of the DRAM cells corresponding to a basic time period in a self-refresh mode, the refresh circuit comprising: a mode detection circuit for detecting an entry into and an exit from the self-refresh mode to provide a self-refresh mode signal; an oscillation circuit for producing an oscillation signal in response to the self-refresh mode signal to provide the basic time period; and a refresh time change circuit for changing the basic time period in response to one of two refresh time change factors, the factors including a process variation factor relating to the DRAM device and a temperature change factor relating to the DRAM device to provide a changed time period and further changing the changed time period in response to the other refresh time change factor, to provide a further changed time period for self-refreshing.