Patent ID: 8090897

Claim:
A sub-system, comprising: an interface circuit operable for receiving, from a system, write data to be stored on a first memory circuit and for communicating the write data to the first memory circuit, the first memory circuit having a first latency for the write data, wherein the interface circuit is further operable to: cause the first memory circuit to appear to the system as a second memory circuit having a second latency for the write data, the second latency being different than the first latency; and time shift communication of the write data to the first memory circuit by an amount of time equal to a difference between the first latency and the second latency, where the difference between the first latency and the second latency is equal to or greater than one clock cycle, and where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC.