Patent ID: 7180105

Claim:
A normally off JFET comprising: a die of silicon having a top and bottom surface; said die having a substrate extending from said bottom surface, and an epitaxial layer of one conductivity type atop said substrate and extending to said top surface; said top surface having at least one shallow source contact implant region of said one conductivity type, and a first shallow gate implant region of the other conductivity type and a second shallow gate implant region of the other conductivity type each laterally spaced from said shallow source contact implant region whereby said shallow source contact implant region is disposed between said first and said second shallow gate implant regions; at least one shallow implanted island of said other conductivity type formed beneath each said shallow gate implant and spaced therefrom to form at least a first lateral conduction channel which extends to a drain drift region; and at least one implanted base of said other conductivity type extending beneath said shallow implanted islands and said shallow source contact implant region, said at least one implanted region being adjacent to second lateral conduction channels, each disposed beneath and parallel to a respective said first lateral conduction channel, the dimensions of said first and second channels and the concentration of impurities in said first and second channels being configured so that said first and second channels are fully depleted when the gate voltage is zero relative to said source region.