Patent ID: 7853419

Claim:
A signal processing circuit, comprising: a high frequency (HF) receiver for receiving a frequency modulated HF input signal and for generating an intermediate frequency (IF) signal having an intermediate frequency from the frequency modulated HF input signal, wherein the intermediate frequency is smaller than a frequency of the frequency modulated HF input signal; a frequency divider for generating a signal from the IF signal or a signal derived from the IF signal, the generated signal having a reduced frequency that is smaller than the intermediate frequency; and a sampler for sampling the generated signal with the reduced frequency by a sampling frequency, wherein the sampling frequency is smaller than twice the intermediate frequency; wherein the frequency divider divides the intermediate frequency such that the reduced frequency and the sampling frequency are spaced from one another in terms of frequency such that a sampling theorem is fulfilled at least for the first odd-numbered harmonic of the generated signal with the reduced frequency.