Patent ID: 7662671

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: preparing a laminated structure comprising a substrate and a plurality of chips stacked on the substrate, the plurality of chips collectively forming multiple layers on the substrate, each chip forming one of the multiple layers, one of the chips being formed on an adjacent one of the chips; and dividing the laminated structure into a plurality of sub-laminated structures, wherein the step of dividing comprises the steps of: cutting the plurality of chips with a first cutting width; providing an overmold resin for covering the plurality of sub-laminated structures laminated on the substrate and filling gaps between adjacent sub-laminated structures of the plurality of the sub-laminated structures; and cutting the substrate and the overmold resin that fills the gaps between the adjacent sub-laminated structures of the plurality of the sub-laminated structures with a second cutting width that is smaller than the first cutting width.