Patent ID: 7972948

Claim:
A method for forming a semiconductor device, the method comprising: forming a plurality of memory cells, including: forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer, and forming masks over portions of the first dielectric layer and the charge storage layer; and forming a plurality of bit lines, each of the bit lines acting as a source region or a drain region for a portion of the plurality of memory cells, where forming the plurality of bit lines comprises: etching a trench in the charge storage layer and the first dielectric layer, the trench extending to the substrate, where the masks prevent removal of portions of the first dielectric layer and the charge storage layer during etching of the trench, after etching the trench, implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width, where implanting the n-type impurities includes removing a portion of the masks to cause the first width of the n-type region to be greater than a width of the trench, and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width, where the second depth is greater than the first depth and the second width is greater than the first width.