Patent ID: 7177385

Claim:
A shift register cell operable to safely provide a configuration bit, the shift register cell comprising: (a) a master latch connected to a serial data input of the shift register cell via a first controllable switch, the master latch operable to buffer store a master latch data bit; (b) a first slave latch connected to an output of the master latch via a second controllable switch, the first slave latch operable to buffer store a first slave latch data bit; (c) at least one second slave latch connected via at least one third controllable switch to the output of the master latch, the at least one second slave latch operable to buffer store at least one second slave latch data bit; and (d) an evaluation logic unit operable to output the configuration bit on the basis of the master latch data bit stored in the master latch, the first slave latch data bit stored in the first slave latch, and the at least one second slave latch data bit stored in the at least one second slave latch.