Patent ID: 7134108

Claim:
A method for checking an IC layout, the IC layout comprising a first metal layer and a second metal layer, the first meal layer coupling to the second metal layer through at least a via, both of the first and second metal layers coupling to a power source, the first metal layer comprising a first wire and the second metal layer comprising a second wire, the first and second wires respectively comprising a plurality of wire segments, the method comprising steps of: checking the plurality of wire segments of the first and the second wires according to a predetermined width, so as to determine at least one unfit wire segment having a width narrower than the predetermined width; removing the unfit wire segment for reducing a wire resistance of the IC layout; and after removing the unfit wire segment, checking a plurality of remaining wire segments of the first and the second wires, so as to determine whether at least one non-coupling wire segment exists; wherein the non-coupling wire segment is not coupled to the power source.