Patent ID: 8754496

Claim:
An apparatus comprising: a transistor including a channel layer, a barrier layer formed over the channel layer, a source electrode over the barrier layer, a drain electrode over the barrier layer, and a t-gate, wherein the t-gate includes a gate electrode and a first field plate coupled with the gate electrode such that the gate electrode and the first field plate are disposed substantially equidistant from the source electrode and the drain electrode and the first field plate is configured to reduce an electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode; a second field plate separated from the first field plate by a dielectric layer and disposed substantially equidistant from the source electrode and the drain electrode, and configured to further reduce the electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode; and a ground pad coupled with the second field plate by an interconnect for providing a ground voltage to the second field plate, and the second field plate is electrically decoupled from the source electrode and the drain electrode.