Patent ID: 7725793

Claim:
A test apparatus for testing a device under test, comprising: a main instruction storing section that stores thereon a main test instruction sequence; a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed; a pattern generating section that sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction from the main test instruction sequence and (II) timing set information designating a combination of timings for output of the test pattern; and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information, wherein when the subroutine call instruction included in the main test instruction sequence is executed, the pattern generating section sequentially reads and executes an instruction from the sub test instruction sequence designated by the subroutine call instruction and outputs (1) a test pattern associated with the executed instruction from the sub test instruction sequence and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence.