Patent ID: 8270193

Claim:
A non-volatile memory device, comprising: a plurality of pass gates; an array including a plurality of vertically stacked memory layers, resistive memory elements, word lines, and subsets including a plurality of local bit lines, each local bit line comprised of electrically coupled horizontal and vertical segments, the vertical segment electrically coupled with a different one of the plurality of pass gates, each memory element having exactly two terminals with one terminal electrically coupled with only one of the word lines and another terminal electrically coupled with the horizontal segment of only one of the plurality of local bit lines in the subset the memory element is positioned in, and the horizontal segment of each local bit line is electrically coupled only with memory elements positioned in a subset of the plurality of vertically stacked memory layers, each memory element is electrically in series with its respective word line and local bit line, the subsets of local bit lines configured to electrically couple with global bit lines via the plurality of pass gates; and a plurality of local bit line decoders configured to turn on a subset of the pass gates to electrically couple a subset of resistive memory elements with a group of the global bit lines, wherein the plurality of pass gates are disposed in a different plane of a semiconductor die than the subset of resistive memory elements.