Patent ID: 7053438

Claim:
An integrated circuit comprising: a semiconductor substrate comprising two source/drain regions of a nonvolatile memory cell and a channel region of the nonvolatile memory cell, the source/drain regions having a first conductivity type, the channel region having a second conductivity type, the channel region extending between the source/drain regions and bordering on the source/drain regions; a dielectric (“select gate dielectric”) on the semiconductor substrate; a select gate of the nonvolatile memory cell on the select gate dielectric over a first portion of the channel region, the select gate controlling the conductivity of the first portion of the channel region; two floating gates of the nonvolatile memory cell over respective second and third portions of the channel region, the floating gates controlling the conductivity of the respective second and third portions of the channel region; two control gates of the nonvolatile memory cell, wherein each of the control gates overlies a respective one of the floating gates; a first peripheral transistor for accessing the memory cell, the first peripheral transistor comprising: a first peripheral transistor gate dielectric on the semiconductor substrate; and a gate on the first peripheral transistor gate dielectric; wherein the first peripheral transistor gate dielectric has the same thickness as the select gate dielectric; wherein the floating gates are adjacent to respective two opposite sidewalls of the select gate and are insulated from the select gate; wherein the floating gates are adjacent to respective two opposite sidewalls of the select gate and are insulated from the select gate, and a top of each of the control gates is higher than the select gate; wherein the integrated circuit further comprises a second peripheral transistor comprising a second peripheral transistor gate dielectric on the semiconductor substrate and a gate on the second peripheral transistor gate dielectric, wherein the second peripheral transistor gate dielectric is made of the same material as the select gate transistor gate dielectric and the first peripheral transistor gate dielectric but the second peripheral transistor gate dielectric is thinner than the first peripheral transistor gate dielectric; wherein the select gate dielectric as at least as thick as a gate dielectric of any peripheral transistor in said memory; wherein the select gate is provided by a conductive line which provides select gates to a plurality of nonvolatile memory cells, the conductive line passing over a plurality of substrate isolation regions formed in recesses in the semiconductor substrate and protruding upward from the semiconductor substrate.