Patent ID: 7488643

Claim:
A method, comprising: forming one or more copper lower interconnects in a first interlevel dielectric layer; forming a first intermediate dielectric layer on a top of said first interlevel dielectric layer; forming a trench in said first intermediate dielectric layer, top surfaces of said one or more said lower interconnects exposed in a bottom of said trench; forming an electrically conductive spreader plate in and completely filling said trench, a bottom surface of said spreader plate in physical and electrical contact with said one or more copper lower interconnects; forming a MIM dielectric block over a top surface of said spreader plate; forming an electrically conductive upper plate on a top surface of said MIM dielectric block, sidewalls of said upper plate and said MIM dielectric plate essentially co-planer; forming a second intermediate dielectric layer on top of said first intermediate dielectric layer, a top surface of said second intermediate dielectric layer coplanar with a top surface of said upper plate; forming a second interlevel dielectric layer on said top surfaces of said second intermediate dielectric layer and said upper plate; and forming one or more copper upper interconnects in said second interlevel dielectric layer, said one or more upper interconnects in physical and electrical contact with said top surface of said upper plate.