Patent ID: 8124472

Claim:
A manufacturing method of a semiconductor device comprising: forming a first pMISFET region, second pMISFET region and nMISFET region which are electrically isolated from one another by forming an element isolation region on a well on an Si substrate, forming a first mask which covers the second pMISFET region and nMISFET region, selectively embedding and forming first SiGe layers which apply first compression strain to an Si channel of the first pMISFET region in the first pMISFET region by the use of the first mask, removing the first mask after formation of the first SiGe layers, forming a second mask which covers the first pMISFET region and nMISFET region after removing the first mask, and selectively embedding and forming second SiGe layers which apply second compression strain different from the first compression strain to an Si channel of the second pMISFET region in the second pMISFET region by the use of the second mask.