Patent ID: 8498166

Claim:
A circuit for protecting integrated circuitry comprising: an integrated circuit including a power supply node and a common node; a resistor coupled to the power supply node of the integrated circuit; a capacitor coupled to the resistor to form a first node, wherein the capacitor is also coupled to the common node of the integrated circuit; a first PFET including a gate, a source coupled to the power supply node, and a drain coupled to the first node; an inverter including an inverter input and an inverter output, wherein the inverter input is in communication with the first node and the inverter output is in communication with the gate of the first PFET; and an NFET including a gate in communication with the inverter output, a drain coupled to the power supply node, and a source coupled to the common node, wherein the drain of the first PFET is directly coupled to the first node.