Patent ID: 7446424

Claim:
A packaged semiconductor device, comprising: a singulated integrated circuit die comprising a semiconductor substrate having top and bottom surfaces, said substrate comprising an integrated circuit formed in a device region at said top surface; a plurality of trench openings formed through said substrate from said bottom surface, at least one of said trench openings connecting to said device region; a layer of conductive material deposited in said trench openings and partially filling said trench openings; a conductive leadframe coupled to a bottom surface of said substrate with a substantially continuous layer of conductive adhesive, said layer of conductive adhesive formed over said layer of conductive material and filling a remaining portion of said trench openings, said layer of conductive adhesive forming a substantially continuous adhesion interface between the bottom surface of said substrate and an opposing mating surface of said conductive leadframe; and a packaging material overmolded onto said singulated integrated circuit die and leadframe.