Patent ID: 8809188

Claim:
A method of manufacturing a through substrate via (TSV) in a semiconductor chip, the method comprising: providing the semiconductor chip, the chip comprising: a substrate with a front-end-of-line (FEOL) comprising at least one device of the chip and further comprising a shallow trench isolation (STI) formed in the substrate, a back-end-of-line (BEOL) comprising a metal one layer formed over the FEOL, a pre-metal dielectric interposed between the substrate and the metal one layer, wherein the pre-metal dielectric comprises a portion interposed between the STI and the metal one layer, at least one first contact to the at least one device, and at least one second metal contact plug extending through the portion of the pre-metal dielectric interposed between the STI and the metal one layer, such that the at least one second metal contact plug electrically contacts the metal one layer at an upper portion and contacts the STI at a lower portion, wherein the at least one first contact and the at least one second metal contact plug are formed in a single contact formation process and comprise a same metal material; subsequent to providing the semiconductor chip, forming a TSV hole through a backside of the substrate to expose at least a part of the lower portion of the at least one second metal contact plug, the TSV hole not extending up to the metal one layer of the BEOL; and after forming the TSV hole, filling the TSV hole with a metallic material such that an electrical connection between the metallic material and the metal one layer is realized via the at least one second metal contact plug in contact with the metallic material and in contact with the metal one layer.