Patent ID: 8587084

Claim:
A method for forming an integrated circuit comprising: forming a first gate oxide on a substrate, the substrate including a sensor array region, a core logic region, and an input/output (I/O) region; depositing a first polysilicon over the first gate oxide; patterning the first polysilicon to have a tapered profile edge at an interface between the sensor array region, and the core logic region; forming a second gate oxide over the first polysilicon and the substrate; patterning the second gate oxide to remove the second gate oxide from the core region; forming a third gate oxide over the second gate oxide and over the substrate in the core region; depositing a second polysilicon over the third gate oxide and removing the second polysilicon over the sensor array region, wherein the second polysilicon is formed over the tapered profile edge of the first polysilicon, and removing the second gate oxide and the third gate oxide over the sensor array region; depositing an amorphous carbon layer over the second polysilicon, wherein the amorphous carbon layer is void free at the interface between the sensor array region and the core logic region; and patterning the amorphous carbon layer and patterning the first polysilicon and the second polysilicon using the patterned amorphous carbon layer as a hard mask.