Patent ID: 7415087

Claim:
A system comprising: A. a first circuit having a serial data input, a serial data output, a clock input, and a mode select input, the first circuit including state circuitry responsive to signals received on the clock input and mode select input for the first circuit to remain in an idle state where no data communication occurs and to enter a communication state where data is communicated between the serial data input and serial data output, with the serial data input, or with the serial data output; B. a second circuit having a serial data input, a serial data output, a clock input, and a mode select input, the second circuit including state circuitry responsive to signals received on the clock input and mode select input for the second circuit to remain in an idle state where no data communication occurs and to enter a communication state where data is communicated between the serial data input and serial data output, with the serial data input, or with the serial data output; C. a first lead connected to the clock input of the first circuit and the mode select input of the second circuit; and D. a second lead connected to the clock input of the second circuit and the mode select lead of the first circuit.