Patent ID: 7886199

Claim:
A data processing system comprising: a plurality of processing units, wherein at least one of said plurality of processing units further includes a plurality of components including: two or more processor cores; a cache array; a processor core master, coupled to at least one processor core among said two or more processor cores, for servicing data access requests issued by said at least one processor core; a cache snooper, coupled to said cache array, for servicing other data access requests, wherein said processor core master and said cache snooper contend for access to said cache array; and a master hang manager that issues at least one hang packet; a local hang manager that, responsive to receipt of a hang packet, determines whether at least one component among said plurality of components has entered into a hang condition, wherein said local hang manager further includes: a throttling manager for throttling down processing unit performance in response to said local hang manager determining said at least one component among said plurality of components has entered into a hang condition; wherein at least one of said plurality of processing units includes the master hang manager for issuing at least one hang packet to said local hang manager, wherein in response to receiving said at least one hang packet, said local hang manager determines whether at least one component among said plurality of components has entered into said hang condition.