Patent ID: 7127530

Claim:
A command issuing apparatus as an initiator in a high-speed serial interface for issuing a command to a target by using a packet, comprising: a sequence control circuit activated by a central processing unit (CPU) for controlling a command issue sequence; a packet processing circuit for assembling operation request blocks (ORB) to be issued into a transmission packet and extracting a status from a received packet; a command ORB transmission buffer for storing a command ORB provided by said CPU; a management ORB transmission buffer for storing a management ORB provided by said CPU; a status reception buffer for management for storing a status received for an issued management ORB and providing the status to said CPU; and a status reception buffer for command for storing a status received for an issued command ORB and providing the status to said CPU, wherein said command ORB transmission buffer has a capacity for storing a plurality of command ORBs at a time, and wherein said command ORB transmission buffer automatically assigns and rewrites an address into a next_ORB field so that a plurality of ORBs to be stored are linked even if the next_ORB field is null.