Patent ID: 6949765

Claim:
A test structure to measure critical dimension in a conductive layer of an integrated circuit device, said test structure comprising: a line comprising a conductive layer overlying a substrate wherein said line is coupled to ground; and a plurality of rectangles comprising said conductive layer wherein said rectangles are not connected to said line or to other said rectangles, wherein near edges of said rectangles and of said line are parallel, wherein said rectangles are floating, wherein the spaces between said near edges of said rectangles and said line vary over a range of values including the critical dimension value for a process step, and wherein any said rectangle that is shorted to said line will be detected distinctly at said shorted rectangle location by exposing an electron beam to said line and then capturing emitted secondary electrons from said line and said rectangles such that said line and said shorted rectangle have a common emission level while nearby rectangles have a differing said emission level.