Patent ID: 7551484

Claim:
In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes tied together into a combined source line, and each memory cell having a drain electrode coupled to an associated bit line, a method of sensing comprising: (a) providing a predetermined demarcation current value to discriminate between two memory states; (b) providing a pulldown circuit for each associated bit line; (c) sensing the plurality of memory cells in parallel; (d) identifying those memory cells having conduction currents higher than said predetermined demarcation current value; (e) turning off the conduction currents of those higher current memory cells by enabling the associated pulldown circuits to ground the associated bit lines; (f) repeating (c) to (e) for a predetermined number of times; and (g) sensing the plurality of memory cells in parallel in a final pass.