Patent ID: 7871874

Claim:
A method of fabricating a transistor of a semiconductor device, comprising steps of: sequentially forming a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer on a semi-insulating substrate, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; forming a source electrode and a drain electrode extending to the first Si planar doping layer by first forming a metal thin layer over the second conductive layer, and after forming the metal thin layer over the second conductive layer, then causing the metal thin layer over the second conductive layer to diffuse to and within the first Si planar doping layer to a predetermined depth such that the metal thin layer is alloyed with the second conductive layer, the second Si planar doping layer, the first conductive layer and the first Si planar doping layer and forms an ohmic contact; etching a portion of the second conductive layer to a predetermined depth; and forming a gate electrode on the etched second conductive layer.