Patent ID: 8411492

Claim:
A memory base cell configured to store at least one bit of information, comprising: a writing data line and a reading data line; a bistable element comprising an input node operatively coupled to the writing data line, an output node operatively coupled to the reading data line, and a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node; an input transfer element operatively coupled between the writing data line and the input node of the bistable element configured to transfer a bit of information from the writing data line to the bistable element, the input transfer element comprising a first control terminal configured to receive a writing enabling logic signal, and a second control terminal configured to receive a writing enabling denied logic signal; the second inverter of the bistable element comprising a first writing enabling terminal configured to receive the writing enabling logic signal and a second writing enabling terminal configured to receive the writing enabling denied logic signal so that the second inverter of the bistable element is disabled for writing when the input transfer element is enabled for writing the bit of information.