Patent ID: 8253199

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a plurality of word lines formed on the semiconductor substrate at predetermined intervals, each of the word lines having a first insulating film, a charge accumulating layer, a second insulating film, and a controlling gate electrode stacked in sequence; selecting transistors arranged on at least one side of the plurality of word lines; an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors; a first cavity portion located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film; a second cavity portion located at a first side wall portion of a word line adjacent to the selecting transistors and covered by the interlayer insulating film, the first side wall portion facing the selecting transistors; and a third cavity portion located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film, wherein the first, second, and third cavity portions are filled with air.