Patent ID: 7339233

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array having nonvolatile semiconductor memory elements arranged in a matrix in a word line direction and a bit line direction, each nonvolatile semiconductor memory element including a gate insulating film including a charge tapping layer formed on a substrate, a gate electrode formed on the gate insulating film, and a pair of diffusion layers formed in a surface layer of the substrate with the gate electrode interposed therebetween and functioning as a source or a drain; first conductors for electrically connecting adjacent diffusion layers of adjacent nonvolatile semiconductor memory elements of the word line direction; and bit lines for electrically connecting a plurality of the first conductors arranged in the bit line direction, wherein ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are partially covered by the first conductor when viewed two-dimensionally.