Patent ID: 7571296

Claim:
A method of determining 1 T and 2 T timing for a memory interface signal in a memory interface, the method comprising: receiving a number of memory circuits to be driven by the interface signal; receiving a frequency of operation of the memory interface; if the number of memory circuits is at or below a first number and the frequency of operation of the memory interface is less than a first frequency, then using 1 T timing for the memory interface signal; if the number of memory circuits is above the first number and the frequency of operation is less than a second frequency, then using 1 T timing for the memory interface signal; and if the number of memory circuits is at or below the first number and the frequency of operation of the memory interface is greater than the first frequency, then using 2 T timing for the memory interface signal, wherein the first frequency is greater then the second frequency, else using 2 T timing for the memory interface signal, wherein when 1 T timing is used for the memory interface signal, the memory interface signal rate is twice the rate as when 2 T timing is used.