Patent ID: 8717079

Claim:
A flip-flop, powered by a first voltage source and receiving a low swing clock signal inverted according to a second voltage source lower than the first voltage source to obtain an inverted low swing clock signal, comprising: a first NMOS transistor, coupled between a receiving node and a first node and having a gate coupled to the inverted low swing clock signal, the first NMOS transistor passing a data signal from the receiving node to the first node when the inverted low swing clock signal is at a logic high level; a first latch circuit, coupled between the first node and a second node to receive the data signal and to generate a processed data signal on the second node based on the low swing clock signal, the inverted low swing clock signal and at least one control signal of the flip-flop; a second NMOS transistor, coupled between the second node and a third node and having a gate coupled to the low swing clock signal, the second NMOS transistor passing the processed data signal from the second node to the third node when the low swing clock signal is at the logic high level; and a second latch circuit, coupled between the third node and a fourth node to receive the processed data signal and to generate an output signal on the fourth node based on the low swing clock signal, the inverted low swing clock signal and at least one control signal of the flip-flop, wherein the flip-flop is controlled by control signals including a reset bar signal and a set bar signal for resetting and setting the flip-flop.