Patent ID: 7734003

Claim:
A shift register array comprising a plurality of shift registers connected in serial, wherein each of the shift registers comprises: a first transistor having a first gate coupled to a first input terminal, a first terminal coupled to the first input terminal and a second terminal coupled to a first node; a second transistor having a second gate coupled to the first node, a third terminal coupled to a first clock input terminal and a fourth terminal coupled to an output terminal; a first pull-up unit, comprising: a third transistor coupled between the first node and a ground, having a third gate coupled to a second node; a first capacitor coupled between the first clock input terminal and the second node; and a fourth transistor coupled between the second node and the ground, having a fourth gate coupled to the first node; a fifth transistor, coupled between the output terminal and the ground, having a fifth gate coupled to a second clock input terminal; and a sixth transistor, coupled between the output terminal and the ground, having a sixth gate coupled to a third clock input terminal.