Patent ID: 8253445

Claim:
An output circuit comprising: first and second input terminals; first and second output terminals; a main buffer that receives differential input signals from the first and second input terminals and outputs differential output signals to the first and second output terminals; a pre-emphasis buffer that applies pre-emphasis to the differential output signals at a time of a transition of the differential input signals; and a de-emphasis-level control buffer including: a differential circuit that turns on a path between one of the first and second output terminals and one of first and second power supplies to reinforce the pre-emphasis operation on the differential output signals at a time of the pre-emphasis by the pre-emphasis buffer, and that, at a time of de-emphasis, turns off the path through which the pre-emphasis has been reinforced and turns on another path between the first and second power supplies, wherein the differential circuit includes two differential pairs of transistors having a current value reduced only during the time of de-emphasis.