Patent ID: 8506030

Claim:
An element substrate having a plurality of heaters, and a plurality of switching elements corresponding to the plurality of heaters, the substrate comprising: an inverter which receives a print data signal, inverts logic of the print data signal, and outputs an inverted signal; a voltage conversion circuit which receives the inverted signal, inverts logic of the inverted signal, converts a voltage of the logic-inverted signal, and outputs the voltage-converted signal; a block selection circuit which outputs a block selection signal for time-divisionally driving the plurality of heaters for each block; and heater selection circuits, arranged in correspondence with the plurality of switching elements, which receive the signal output from said voltage conversion circuit, the block selection signal, and the print data signal, and output signals for performing switching by the plurality of switching elements, wherein said voltage conversion circuit includes: an NMOS transistor having a gate connected to an input terminal of the inverted signal, and a source grounded; and a PMOS transistor, series-connected to said NMOS transistor, which has a source connected to a power supply for outputting a voltage for driving the plurality of switching elements, and a gate and drain short-circuited, and each of said heater selection circuits includes: a NAND circuit including: a PMOS transistor having a gate connected to an input terminal of the signal output from said voltage conversion circuit, and a source connected to the power supply for outputting a voltage for driving the plurality of switching elements; a PMOS transistor, parallel-connected to said PMOS transistor, which has a gate connected to an input terminal of the block selection signal; an NMOS transistor having a drain connected to drains of said two PMOS transistors, and a gate connected to the input terminal of the block selection signal; and an NMOS transistor, series-connected to said NMOS transistor, which has a gate connected to an input terminal of the print data signal, and a source grounded; and an inverter including: a PMOS transistor which has a gate connected to a drain of said NMOS transistor having the drain connected to the drains of said two PMOS transistors of said NAND circuit and the gate connected to the input terminal of the block selection signal, and has a source connected to the power supply for outputting the voltage for driving the plurality of switching elements; and an NMOS transistor, series-connected to said PMOS transistor, which has a gate connected to the drain of said NMOS transistor having the drain connected to the drains of said two PMOS transistors of said NAND circuit and the gate connected to the input terminal of the block selection signal, and has a source grounded.