Patent ID: 8400784

Claim:
An apparatus, comprising: a) a monolithic voltage regulator having first and second transistors each arranged as a plurality of parallel transistor devices; b) a plurality of bumps on said monolithic voltage regulator to form connections to said first and second transistors at a supply node, a switching node, and a ground node; c) a single layer lead frame having a plurality of interleaving lead fingers, wherein each said interleaving lead finger comprises a first portion with a first thickness and a second portion with a second thickness, wherein said first thickness is greater than said second thickness, wherein at least one of said interleaving lead fingers comprises two first portions separated by one second portion, said single layer lead frame being coupled to said monolithic voltage regulator via said plurality of bumps, said single layer lead frame comprising first and second surfaces, wherein said first surface comprises a first pattern to form connections to said plurality of bumps, and wherein said second surface comprises a second pattern that is different from said first pattern; and d) a flip-chip package encapsulating said monolithic voltage regulator, said plurality of bumps, and said single layer lead frame, said flip-chip package having external connectors of said monolithic voltage regulator at said second surface of said single layer lead frame.