Patent ID: 7055117

Claim:
A method for debugging a system-on-a chip (SoC), the SoC comprising system components to include at least a first functional block and a second functional block, said first function block being controlled by a first block clock and a first clock control unit and said second function block being controlled by a second block clock and a second clock control unit, the method comprising steps of: setting a first breakpoint on a first specific event occurring on said first functional block; monitoring events occurring on the SoC; recognizing occurrence of the first specific event on said first functional block; providing, responsive to said recognizing, a debug trigger signal to both said first and second clock control units; halting, responsive to said debug tringer signal, both said first and second block clocks; determining states of one or more of said system components using a scan clock; and, utilizing said states to debug the SoC.