Patent ID: 7330039

Claim:
A system for exercising an integrated circuit comprising: a socket including, a board; an interconnect structure manufactured to be inserted into said socket, said interconnect structure being coupled to said board, said interconnect structure including, a substrate, first and second pads coupled to said substrate and coupled to each other through vias running through said substrate, said second pads coupling said interconnect structure to said board, and resilient contacts coupled to said first pads, each said resilient contact comprising: an elongate, resilient body coupled at a first end to one of said first pads, and a plurality of tips extending from a base coupled to a second end of said body, said plurality of tips spaced in sufficient proximity one to another such that each tip contacts a same one of a terminal of said integrated circuit; and a support structure that secures contact between the integrated circuit and said resilient contacts during the testing.