Patent ID: 7561474

Claim:
A program verifying method of a flash memory device, the flash memory device comprising a selected first bit line and an unselected second bit line of which each bit line includes a plurality of memory cells, the program verifying method comprising: precharging the first bit line; applying a first verify voltage to word lines of first selected memory cells, and a pass voltage (Vpass) to word lines of the other memory cells that are not selected; evaluating the memory cells during a first time period; sensing programmed states of the first selected memory cells during a second time period to determine whether charges accumulated in the first bit line are discharged; precharging the first bit line after sensing the programmed states of the first selected memory cells; selecting at least one second selected memory cell from the first selected memory cells, the second selected memory cell being a cell that has a threshold voltage that does not exceed the first verify voltage; applying a second verify voltage to a word line of the second selected memory cell while applying the pass voltage to word lines of the other memory cells; evaluating the memory cells during a third time period; and sensing a programmed state of the second selected memory cell during a fourth time period to determine whether charges accumulated in the precharged first bit line are discharged.