Patent ID: 7424695

Claim:
A method for manufacturing a semiconductor integrated circuit using layout data designed by a sequence of processes, the sequence of processes comprising: disposing a lower-layer wiring pattern on a lower-layer wiring layer implemented in a graphics image space, and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an upper-layer wiring layer implemented in the graphics image space; providing a detour pattern including a first detour pattern connected to the upper-layer wiring pattern in a direction perpendicular to a longitudinal direction of the upper-layer wiring pattern and a second detour pattern connected to the first detour pattern in a direction perpendicular to a longitudinal direction of the first detour pattern; providing a plurality of via patterns connecting the lower-layer and upper-layer wiring patterns at an intersection of the lower-layer and upper-layer wiring patterns on the detour pattern; and forming a via cell pattern based on the detour pattern and the via patterns, wherein the sequence of processes further comprises: forming a terminal end correction pattern on a terminal end of the detour pattern in a direction parallel to a preferential direction defined in one of the lower-layer and upper-layer wiring patterns.