Patent ID: 8359433

Claim:
An apparatus comprising: a cache memory having a plurality of cache memory lines; an array to store one or more of the plurality of cache memory lines; and logic coupled with the cache memory and the array to: obtain contents of a first cache memory line of the plurality of cache memory lines; merge at least in part, the obtained contents of the first cache memory line with contents of one of the one or more cache memory lines stored in the array; replace the contents of the one cache memory line stored in the array with the obtained contents of the first cache memory line in response to merging at least in part, the obtained contents of the first cache memory line with the contents of the one cache memory line stored in the array; receive a request to access the contents of the first cache memory line and a second cache memory line, wherein the second cache memory line is stored in the array as the one cache memory line; and a plurality of processing streams, wherein the request comprises a load instruction having an indication of which one of the plurality of processor streams is associated with the array.