Patent ID: 7030425

Claim:
A memory cell comprising: a thyristor body having first and second end portions, each end portion having a base region and an emitter region, at least one of the end portions being in a substrate; a filled trench in the substrate laterally adjacent to said base region of the end portion in the substrate, the filled trench having an insulative liner material on a sidewall thereof; a current shunt in the filled trench, the current shunt being configured and arranged to provide a current-shunting path between the emitter region of the thyristor body end portion in the substrate and a circuit node near the upper portion of the current shunt, the insulative liner material being adapted to electrically insulate the current shunt from the thyristor body; a transistor having first and second source/drain regions separated by a channel and a gate adapted for controlling current flow in the pass device, the first source/drain region being coupled in series with the thyristor via an emitter regions of the first thyristor end portion, the gate being part of a first word line; a thyristor control port in the lined trench, over the lower portion and laterally adjacent to the upper portion of the current shunt, the control port being part of a second word line and adapted for capacitively coupling to the thyristor body via a dielectric material for controlling current in the thyristor body; a bit line electrically coupled to the second source/drain region of the pass device; a reference voltage line coupled to the emitter region of the second thyristor end portion; and an access controller configured and arranged for controlling the first and second word lines, the bit line and the reference voltage line for storage and manipulation of data at the emitter region of the first thyristor end portion.