Patent ID: 7724860

Claim:
An auto-adaptive digital phase locked loop (DPLL) comprising: (a) a phase detector including: (i) an edge detector having an input that receives an input clock, and an output that outputs a reference event generated from a reference edge of the input clock, (ii) a programmable first counter that counts down at a generated clock rate, the first counter having a first input that is programmed with an integer value M, a second input that receives the generated clock, and an output that outputs a counter state based on the generated clock and the integer value M, and (iii) a first register having a first input that receives the reference event, a second input that receives the counter state, and an output that outputs a sample value N(t), wherein the register stores the counter state as the sampled value N(t) that represents a code for a phase between the reference event and the counter state; and (b) a frequency synthesizer coupled to the phase detector, the frequency synthesizer outputting, to at least the phase detector, the generated clock at a frequency proportional to the sample value N(t).