Patent ID: 8492825

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a gate insulator disposed on the semiconductor substrate; a plurality of memory cells, each of the memory cells being arranged along a first direction and including a floating gate electrode above the semiconductor substrate via the gate insulator, a control gate electrode above the floating gate electrode via a first inter-gate insulator, first diffusion layers formed in the semiconductor substrate to sandwich a portion immediately beneath the floating gate electrode, each of the first diffusion layers having a reverse impurity type to the semiconductor substrate; a contact electrode portion including a bottom electrode with a first opening and a top electrode on the bottom electrode, the bottom electrode being arranged on the gate insulator having the first opening, the top electrode being electrically connected to the semiconductor substrate via the first opening, and a second inter-gate insulator disposed between the bottom electrode and the top electrode; a connection diffusion layer formed in the semiconductor substrate below the first opening and the connection diffusion layer having the reverse impurity type to the semiconductor substrate; and a connection electrode in the first opening, and the top electrode being electrically connected to the semiconductor substrate via the connection electrode; wherein a height of an upper surface of the connection electrode is lower than a height of an upper surface of the second inter-gate insulator.