Patent ID: 7764530

Claim:
A memory circuit arrangement comprising: a cell array substrate, which has an integrated memory cell array contained in a memory circuit, the integrated memory cell array including memory cells; a logic circuit substrate, which has an integrated logic circuit that controls access to the memory cells, the logic circuit substrate being a different substrate than the cell array substrate; a main area of the cell array substrate and a main area of the logic circuit substrate lie in two planes parallel to one another and overlapping one another in a direction normal to the main area; wherein the logic circuit includes at least one of: a control circuit contained in the memory circuit, the control circuit controlling sequences when at least one of reading, writing or reading and writing content of a memory cell of the memory cell array, or a decoding circuit contained in the memory circuit, the decoding circuit selects, in a manner dependent on an address datum, a word line or a bit line connected to a plurality of memory cells of the memory cell array; the number of connections between the substrates depends on the number of word lines and/or bitlines; the number of connections is greater than 1000; and the cell array substrate has an analog circuit.