Patent ID: 7002545

Claim:
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising: first and second clocked inverters that each outputs a signal in sync with a clock pulse and an inverted clock pulse obtained by inverting the polarity of the clock pulse; and means for inputting to the second clocked inverter a signal obtained by inverting the polarity of an output signal from the first clocked inverter, wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially, wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages, wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter, wherein, in a k-th (k is a natural number equal to or larger than 3, and equal to or smaller than r) stage, a wiring line kept at a first power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first n-channel TFT and a second n-channel TFT connected in series to the first n-channel TFT, wherein a signal obtained by inverting the polarity of a signal outputted from the first clocked inverter of the (k−1)-th stage is inputted to a gate electrode of the first n-channel TFT, wherein the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second n-channel TFT, and wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.