Patent ID: 6931466

Claim:
A method of implementing a plurality of interfaces between a chip or board and external devices or buses, said method comprising the steps of: (a) providing in said chip or board a reprogrammable I/O system having a plurality of reprogrammable pin groups of I/O pins for implementing said plurality of interfaces, each of said reprogrammable pin groups having a pin state machine and a data FIFO coupled together, each of said pin state machines having first chain connections to two neighbor pin state machines, each of said data FIFOs having second chain connections to two neighbor data FIFOs, said interfaces including high speed interfaces and low speed interfaces, each of said high speed interfaces having high speed signals and low speed signals, said high speed signals including control signals, address signals, and data signals, each of said low speed interfaces having only low speed signals; (b) for each of said high speed interfaces, assigning said control signals of said high speed interface to the I/O pins of a first pin group, if there are unassigned control signals of said high speed interface due to the number of said control signals exceeding the number of I/O pins in said first pin group, assigning said unassigned control signals to the I/O pins of a second pin group; assigning said address signals and data signals of said high speed interface to a third pin group; assigning said low speed signals of said high speed interface to the unassigned I/O pins of said first, second, and third pin groups; assigning a first pin state machine of said first pin group to said high speed interface, said pin state machine directly controlling the transmission of said address and data signals of said high speed interface; assigning a second pin state machine of said second pin group to said high speed interface and using said first chain connections between said first and second pin state machines to establish a master-slave relationship between them, said first and second pin state machines together controlling the transmission of said address and data signals of said high speed interface; and (c) for each of said low speed interfaces, assigning said low speed signals of said low speed interface to the remaining unassigned I/O pins of said plurality of reprogrammable pin groups.