Patent ID: 8837241

Claim:
A semiconductor memory device comprising: a memory core; a correction bit generation circuit that generates a correction bit from data having a predetermined bit width; a data set generation section; a late write register that temporarily stores a late write address and late write data; and a control section that exercises control in compliance with a write command for write data having a bit width less than the predetermined bit width in order to perform a dummy read operation, a data set generation process, a correction bit generation process, a late write operation, and a late write data storage process; wherein the dummy read operation is performed to output data corresponding to a write address of the write command from the memory core; wherein the data set generation process is performed by the data set generation section to generate a data set having the predetermined bit width by using the data output from the memory core during the dummy read operation to add bits in order to compensate for the shortfall in the write data; wherein the correction bit generation process is performed by the correction bit generation circuit to generate the correction bit from the data set; wherein the late write operation is performed in parallel with the generation of the data set and of the correction bit to write the late write data stored in the late write register into a memory cell of the memory core that corresponds to the late write address; and wherein the late write data storage process is performed to handle the write address as a new late write address and store the data set and the correction bit into the late write register as new late write data.