Patent ID: 7342990

Claim:
A wake-up circuit comprising: a counter; a register circuit including a data terminal and a clock terminal, wherein said clock terminal receives a standby signal; a first logic circuit, connected to one of two output terminals of said register circuit, receiving a wake-up signal; an oscillator, controlled by an output signal of said first logic circuit, including an output terminal connected to said counter; a flip flop, including another data terminal, another clock terminal and a further output terminal, wherein said data terminal of said flip flop receives another output signal of a highest bit register in said counter, said clock terminal of said flip flop receives an output signal of said oscillator, and said output terminal connects to preset terminals of said register circuit; and a second logic circuit, including a one-more input terminal and a one-more output terminal, wherein said input terminal of said second logic circuit connects to the output terminal of said first logic circuit, the output terminal of said flip flop, and another one of the two output terminals of said register circuit, said output terminal of said second logic circuit coupling to preset said counter; whereby said wake-up circuit receives the standby signal to stop said oscillator working and then waits for the wake-up signal to reactivate said oscillator again; when the duration of the wake-up signal is smaller than an expected time of said counter, said oscillator stopping working again and entering a saving mode; when the duration of the wake-up signal is longer than the expected time of said counter, said counter controlling said flip flop to output a preset signal to said register circuit, said first logic circuit operating to have said oscillator working even the wake-up signal is removed, and then said second logic circuit operating to set said counter returning to a normal state and waiting for a next standby signal to feed in.