Patent ID: 7439787

Claim:
A pulse width modulation circuit comprising: a first delay-locked loop (DLL) circuit coupled to a first multiplexer and having a first set of delay stages, wherein the first DLL circuit is configured to receive an input clock signal and, through the first multiplexer, produce a first stage delay signal associated with the first set of delay stages, wherein the first stage delay signal leads the input clock signal by a first duration; and a second DLL circuit coupled to a second multiplexer and having a second set of delay stages, wherein the second DLL circuit is configured to receive the input clock signal and, through the second multiplexer, produce a second stage delay signal associated with the second set of delay stages, wherein the second stage delay signal lags the first stage delay signal by a second duration; wherein the first DLL circuit and second DLL circuit are operatively coupled to produce an output signal having a pulse width equal to the difference between the first duration and the second duration.