Patent ID: 8134882

Claim:
A semiconductor device comprising: a first power supply of a high potential; a second power supply of a low potential; a third power supply of a potential higher than said first power supply; a fourth power supply of a potential lower than said second power supply; an anti-fuse element having a node at one end thereof and having another node at the other end thereof; said other end being connected to said fourth power supply; a driver transistor whose source is connected to said third power supply, whose gate is connected to a control node and whose drain is connected to said one end of said anti-fuse element; a decoding circuit including a load transistor connected between said third power supply and said control node and at least one selection transistor connected between said second power supply and said control node; and a decision circuit connected to said first and second power supplies; so as to decide a resistance value of said anti-fuse element; wherein said anti-fuse element is rendered electrically conductive in response to activation of said driver transistor as selected by said decoding circuit, and said decision circuit makes a decision as to whether or not said anti-fuse element has been rendered electrically conductive.