Patent ID: 7230810

Claim:
An integrated circuit comprising: a transistor device implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage; and over-voltage protection circuitry adapted to apply gate and tub voltages to the gate and tub nodes, respectively, wherein: if at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device; if the transistor device is to be turned on, then the over-voltage protection circuitry sets the gate voltage to the specified maximum voltage; if the transistor device is to be turned off, then the over-voltage protection circuitry sets the gate voltage to the tub voltage; the over-voltage protection circuitry is adapted to be programmably controlled to operate in either a normal operating mode or an over-voltage protection mode; in the normal operating mode, the over-voltage protection circuitry sets the tub voltage to a ground voltage; and in the over-voltage protection mode: if the channel voltage is less than a threshold voltage, then the over-voltage protection circuitry sets the tub voltage to the ground voltage; and if the channel voltage is greater than the threshold voltage, then the over-voltage protection circuitry sets the tub voltage to a first voltage less than the specified maximum voltage.