Patent ID: 7735028

Claim:
A logic circuit redesign program used for a computer that performs redesign of a logic circuit comprising a plurality of blocks, the logic circuit redesign program allowing the computer to: execute an information acquisition process that acquires pin information related to pins used in respective ports provided in each of the blocks and connection information that indicates connection relationships between the ports; execute a multiplexer disposition process that, based on the pin information and the connection information, classifies a plurality of pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group; and execute a demultiplexer disposition process that, based on the pin information and the connection information, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each of the demultiplexed signals to input ports of respective input destination blocks.