Patent ID: 7228367

Claim:
A direct memory access controller for carrying out a direct memory access transfer between an internal bus and an external bus, comprising: a determination unit determining whether or not a burst access can be utilized in a first device connected to the external bus based on an address in an access to a second device connected to the internal bus; and a control unit carrying out the direct memory access transfer by utilizing said burst access when said determination unit determines that the burst access can be utilized in the first device connected to the external bus, wherein said determination unit includes: an address table where an address region in the internal bus in which a burst access is available in the external bus is set in accordance with a direction of a data transfer; and an access determination unit determining whether or not a burst access can be utilized in the external bus by comparing an address in an access to the internal bus and the address region set in said address table and by comparing an actual data transfer direction and the data transfer direction set in said address table.