Patent ID: 8610200

Claim:
A semiconductor device, comprising: a substrate having first and second diffusion regions therein; a dielectric layer defined over the substrate and the first and second diffusion regions; a first gate having a first polysilicon layer defined over and connecting a first portion of the dielectric layer between the first and second diffusion regions, the first gate having a first side and a second side, the first gate extending a length between the first and second diffusion regions such that each of the first side and the second side of the first gate is above an approximate interface of the first and second diffusion regions, wherein the first gate is at a memory region of the semiconductor device; first and second oxide regions positioned respectively beside the first side and the second side of the first gate and over the dielectric layer; a word line having a second portion of a second polysilicon layer over and connecting the first polysilicon layer of the first gate and the first and second oxide regions; and a second gate having the first polysilicon layer and a first portion of the second polysilicon layer, wherein the second gate is at a peripheral region of the semiconductor device.