Patent ID: 8832353

Claim:
A method comprising: receiving, by a memory system, data from a host communicatively coupled to the memory system, the memory system including a memory controller and one or more non-volatile memory arrays; temporarily storing, by the controller, the received data in a volatile memory of the controller; retrieving, by the controller, the data from the volatile memory; temporarily storing, by the controller, the data retrieved from the volatile memory in an on-chip memory cache; and when a stop-transmission command is received from the host, and the data stored in the cache includes a partial-page and a complete-page, the complete-page in a first portion of the cache associated with a first plane of the one or more non-volatile memory arrays, the partial-page in a second portion of the cache associated with a second plane of the one or more non-volatile memory arrays, wherein the first plane includes a first logical area and a second logic area, the first logical area of the first plane dedicated to storing complete-pages, the second logical area of the first plane dedicated to storing partial-pages, and the second plane includes a third logical area, the third logical area of the second plane dedicated to storing complete-pages, then retrieving, by the controller, the data from the cache; storing, by the controller, the complete-page retrieved from the first portion of the cache in the first logical area in the first plane; transferring the partial-page from the second portion of the cache to the first portion of the cache; and storing, by the controller, the partial-page transferred from the second portion of the cache in the second logical area of the first plane.