Patent ID: 8304307

Claim:
A method of forming a gate oxide structure in an integrated circuit, comprising the steps of: forming a first gate oxide layer above at least a first voltage area of a substrate; forming a first polysilicon layer above at least the first voltage area and the first gate oxide layer; removing a portion of the first gate oxide layer and a portion of the first polysilicon layer from at least a second voltage area and a memory area of the substrate; forming a second gate oxide layer above at least the second voltage area, the second gate oxide layer having a thickness greater than the first gate oxide layer; removing the second gate oxide layer from at least above the memory area forming a third gate oxide layer above at least the memory area, the third gate oxide layer having a thickness between that of the first and the second gate oxide layers; and forming a second polysilicon layer above at least the second voltage area and the memory area to form a floating gate for memory array transistors.