Patent ID: 6977942

Claim:
A device for timing the processing of data packets, comprising a memory for storing a data packet that arrives in the device as part of a data burst, a clock for determining the course of time, and processing means for processing the data packet that exits the memory, wherein the device further comprises calculating means for calculating a value for a play-out delay with which value only m successive data packets would have failed to be received of n temporally most recent data packets if the initiation of the processing of data bursts comprising the data packets in question had been delayed for the period of said play-out delay, where n and m are natural numbers, and transferring means for transferring the packets from the memory to the processing means on the basis of a response obtained from the clock of the reaching of said play-out delay value from the moment the data packet was received, wherein the device further comprises a maximum value determined for the play-out delay and when the value of said play-out delay is higher than the maximum value determined for the play-out delay, the device is arranged to use the maximum value of the play-out delay as the value of the play-out delay.