Patent ID: 7934188

Claim:
A method of legalizing a placement of logic cells in an integrated circuit design, comprising: receiving an input placement having a plurality of blockages and a plurality of movable logic cells, by executing first program instructions in a computer system; selectively classifying the blockages into at least two different sets based on size, wherein blockages in a first set of the at least two different sets are larger than blockages in a second set of the at least two different sets, by executing second program instructions in the computer system; relocating one or more of the movable logic cells to coarse regions defined between adjacent blockages in the first set to remove overlaps among the movable logic cells and the blockages in the first set without regard to the blockages in the second set, by executing third program instructions in the computer system; and thereafter relocating one or more of the movable logic cells to fine regions defined between adjacent blockages in the second set to remove all cell overlaps, by executing fourth program instructions in the computer system.