Patent ID: 7146583

Claim:
A method of implementing a user integrated circuit design, comprising the steps of: introducing a plurality of tree representations for the user integrated circuit design in a partitioned manner including at least one sub-design to form a design abstraction of the user design; wherein at least one node in one of the plurality of tree representations represents one of a sub-design module and a user floor-planned partition, at least one node in one of the plurality of tree representations represents a plurality of sub-design modules, at least one node in one of the plurality of tree representations represents a set of circuit primitives, and a dependency relationship between a pair of nodes in a tree is represented by a parent-child connection between the pair of nodes; traversing at least one of the plurality of tree representations in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for the at least one sub-design; and traversing at least one of the plurality of tree representations in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs.