Patent ID: 8316208

Claim:
A memory controller for controlling access to one or more flash memories, in which data erasing is performed in physical blocks and data writing is performed in physical pages, based on an access request from a host system, comprising: a block management unit which manages information relating to a relationship between logical blocks each composed of plural logical sectors and physical blocks; a physical page identifying unit which identifies a physical page having the smallest page number among free pages in a physical block or a physical page having the largest page number among physical pages storing data in a physical block; a logical block information holding unit which holds a predetermined number of pieces of logical block information each of which is information, relating to a logical block, including information for identifying a physical block corresponding to the logical block and a physical page having the smallest page number among free pages in the physical block; a priority order management unit which manages priority order about the predetermined number of the pieces of logical block information; a logical block identifying unit which identifies a logical block including a logical sector designated by the access request; a control unit which controls access to a physical block corresponding to the logical block identified by the logical block identifying unit, by referring to the logical block information; wherein when the logical block identifying unit identifies a logical block, the priority order management unit gives the highest priority to a first piece of logical block information which is a piece of logical block information corresponding to the identified logical block, and the logical block information holding unit holds the first piece of logical block information instead of a piece of logical block information having the lowest priority when not holding the first piece of logical block information.