Patent ID: 8347119

Claim:
A system for efficient power management, comprising: a processor having a plurality of possible idle states, the processor coupled to system memory and firmware memory store, wherein transitioning to and from an idle state takes a measured amount of time; an operating system configured to execute on the processor, the operating system comprising a power management service to control the plurality of idle states of the processor, wherein the power management service is configured to select a processor idle state based on a calculated utilization ratio and a predetermined ratio threshold policy, and wherein the calculated utilization ratio is determined by a sum of non-idle time, idle state transition times and idle state latency times for a pre-determined period of time, wherein the utilization ratio is calculated as equal to a ratio of busy time to the period, which is busy time divided by period, where busy time is calculated as a sum of: (time in a non-idle state in the period), (a quantity of first idle state transitions multiplied by a latency time for the first idle state) and (a quantity of second idle state transitions multiplied by latency time for the second idle state), and wherein the busy time further comprises adding additional idle states and additional idle state transition times, when transition time for the additional idle states in not insignificant.