Patent ID: 7649393

Claim:
A semiconductor integrated circuit having an active mode and a sleep mode, the semiconductor integrated circuit comprising: a plurality of combinational logic circuits and a plurality of flip-flops that are connected alternately with each other, electric power being supplied to the combinational logic circuits and the flip-flops during the active mode so that the flip-flops hold data output from the combinational logic circuits; the plurality of flip-flops comprising: a retention flip-flop, the supply of the electric power to the retention flip-flop being maintained during the sleep mode so that the retention flip-flop retains the data during the sleep mode; and a non-retention flip-flop, the non-retention flip-flop including a switch through which the electric power is supplied to the non-retention flip-flop and an initializing circuit, wherein: the switch includes a control terminal that receives a control signal, the control signal changes from a first level to a second level so that the switch turns from an OFF state to an ON state when the semiconductor integrated circuit switches from the sleep mode to the active mode; and the initializing circuit detects the change of the level of the control signal from the first level to the second level and initializes the non-retention flip-flop.