Patent ID: 8015462

Claim:
A test circuit including TAP (test access port) controllers specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port, the test circuit comprising: a first controller including a first selecting circuit and a first TAP controller of the TAP controllers, the first selecting circuit generating an internal TMS (test mode select) signal in accordance with a TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing a corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection; and a second controller including a second TAP controller of the TAP controllers changing internal state based on the internal TMS signal and testing a corresponding test target block in accordance with the instruction code for test, wherein the selection signal comprises a first selection signal, the internal TMS signal comprises a first internal TMS signal and, the test circuit further comprises a third controller including a second selecting circuit and a third TAP controller, the second selecting circuit generating a second internal TMS signal in accordance with the first internal TMS signal and selections an output destination of the second internal TMS signal in accordance with a second selection signal, and the third TAP controller changing internal state based on the second internal TMS signal and generating the second selection signal based on the instruction code for selection.