Patent ID: 6992608

Claim:
A digital-to-analog converter (DAC) coupled to receive at least one digital input signal and a clock signal, comprising: a current cell driving circuit for generating first and second synchronous control signals, wherein the current cell driving circuit includes a decoder to decode the digital input signal into a first and second code sequence signal, and a latch for latching the first and second code sequence signal depending upon the clock signal and for providing the first and second synchronous control signal, wherein the latch includes a plurality of transistors; and a current cell, having a plurality of output current source transistors, to operate as a current source depending upon the first and second synchronous control signals; wherein the latch reduces the drain to source voltage variation of the plurality of output current source transistors and reduces the coupling of unwanted injection of the digital input signal and the clock signal by maintaining the plurality of transistors of the latch in the off position during code transitions without compromising the DAC update speed.