Patent ID: 7584372

Claim:
An apparatus for reducing power consumption in a system operating in a power saving mode, comprising: a controller providing a first control signal and a second control signal; an oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal; and a voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal; wherein the controller further calculates an estimated total current consumption of the system corresponding to different settings, wherein the calculation is performed according to the following equation: the estimated total current consumption= A*x+B*y+C*z, wherein A is a duration of the power saving mode of the system, B is a duration of a stable time of the oscillator circuit, C is a duration of a normal mode, x is current consumption of the system in the power saving mode, y is current consumption of the duration of the stable time of the oscillator circuit, and z is current consumption of the duration in normal mode.