Patent ID: 8872686

Claim:
A digital-to-analog converter (DAC), comprising: an array comprising 2 m unit cells; a timing encoder configured to bisect an m-bit input digital signal into a most significant bit (MSB) signal comprising m/2 high-order bits, and a least significant bit (LSB) signal comprising m/2 low-order bits; a first column decoder configured to control a first subset of the 2 m unit cells with a first column control signal derived from the LSB signal; a second column decoder configured to control a second subset of the 2 m unit cells with a second column control signal derived from the LSB signal; and a row decoder configured to control the 2 m unit cells with a row control signal derived from the MSB signal; wherein a unit cell of the 2 m unit cells is activated by the first column control signal and the row control signal or the second column control signal and the row control signal.