Patent ID: 7719090

Claim:
A semiconductor device comprising: a semiconductor substrate having a p-channel type transistor region; an element isolation region formed in a surface portion of said semiconductor substrate, said element isolation region defining a p-channel type active region in said p-channel type transistor region; a p-channel type gate electrode structure formed above said semiconductor substrate, traversing said p-channel type active region and defining a p-channel region under said p-channel type gate electrode structure; a first tensile stress film selectively formed above said element isolation region in said p-channel type transistor region; and an insulating film selectively formed above said p-channel type active region and covering said p-channel type gate electrode structure, said insulating film being made of a same film as said first tensile stress film and releasing stress in said insulating film, wherein said first tensile stress film above said element isolation region in said p-channel type transistor region exerts a tensile stress on said p-channel region along a gate width direction.