Patent ID: 7936181

Claim:
A driver adjustment circuit, comprising: a counter circuit operable to receive a drive adjustment signal that comprises a four-bit word representing bits of data and configured to develop a drive adjustment count responsive to the drive adjustment signal, the counter circuit having a current value of a drive count set therein, wherein the counter circuit is set with a programmable value from a control circuit, the counter circuit comprising: a pull-up counter circuit configured to receive selected bits of the drive adjustment signal, and operable to develop a pull-up drive count responsive to the selected bits; a pull-down counter circuit configured to receive selected bits of the drive adjustment signal, and operable to develop a pull-down drive count responsive to the selected bits; and an output driver circuit coupled to the counter circuit configured to receive the drive adjustment count and being adapted to receive a data signal, the output driver circuit operable to develop an output signal responsive to the data signal and adjust a drive strength as a function of the drive adjustment count.