Patent ID: 8555000

Claim:
A data storage device comprising: a plurality of first main memories coupled to a plurality of channels; a plurality of second main memories coupled to the plurality of channels; a buffer memory configured to store data to be programmed to the first and the second main memories, wherein the data to be programmed comprises victim cache lines data including at least one of first victim cache line data, second victim cache line data, third victim cache line data, and fourth victim cache line data; and a controller configured to: set a threshold value in consideration of at least two factors including; a size of the buffer memory, a number of the plurality of channels, a Direct Memory Access (DMA) time, a program type for the first main memory, a program type for the second main memory, a program time for the first main memory, a program time for the second main memory, a number of banks in the first main memory, and a number of banks in the second main memory, determine whether buffer memory usage exceeds the threshold value, and upon determining that buffer memory usage exceeds the threshold value, determine a maximum cost for each one of the victim cache lines data, select the first victim cache line data from the victim cache lines data based on the maximum cost, and program the victim cache lines data to the second main memories while programming the first victim cache line data to the first main memories.