Patent ID: 6998927

Claim:
An apparatus comprising: a first transistor device including first, second, and third terminals; a second transistor device including first, second, and third terminals; a first impedance device to couple the second terminal of the second transistor device to the first terminal of the first transistor device; and a second impedance device to couple the second terminal of the first transistor device to the first terminal of the second transistor device, wherein the first and second impedance devices include capacitive and resistive impedance characteristics, wherein the first impedance device comprises a capacitive element and a resistive element, wherein each of the capacitive element and the resistive element includes first and second terminals, wherein the first terminal of the capacitive element and the first terminal of the resistive element are each coupled to the second terminal of the second transistor device, and wherein the second terminal of the capacitive element and the second terminal of the resistive element are each coupled to the first terminal of the first transistor device, and the second impedance device comprises a capacitive element and a resistive element, wherein each of the capacitive element and the resistive element includes first and second terminals, wherein the first terminal of the capacitive element and the first terminal of the resistive element are each coupled to the second terminal of the first transistor device, and wherein the second terminal of the capacitive element and the second terminal of the resistive element are each coupled to the first terminal of the second transistor device.