Patent ID: 7444565

Claim:
A method of mitigating logic upsets, comprising: providing an input to each of a plurality of programmable logic components; processing the input in each of the plurality of programmable logic components; providing an output from each of the plurality of programmable logic components to a fixed logic component; examining, in the fixed logic component, the outputs from the plurality of programmable logic components; determining, in the fixed logic component, a validated output from among the outputs from the plurality of programmable logic components; transferring from at least one of the programmable logic components a fail detect signal along with the output from the at least one of the programmable logic components; detecting at the fixed logic component, using the fail detect signal, that the at least one of the plurality of programmable logic components has failed; and initiating, from the fixed logic component, a re-programming function for the at least one of the plurality of programmable logic components that has failed.