Patent ID: 8023313

Claim:
A resistance change memory device comprising: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the bit line that is selected and the reference cell on the reference bit line; and a current mirror circuit configured to reduce a cell current of the reference cell to a reference current value between cell current values of the memory cell in a low resistance state and a high resistance state to provide a reference input of the sense amplifier, wherein a memory cell on the reference bit line is the reference cell to which a low resistance state is fixedly written, and the reference bit line is located at the center of respective mats in the cell array.