Patent ID: 7385849

Claim:
A semiconductor integrated circuit device comprising: a power-on checking circuit which detects power-on; a memory cell array in which memory cell arrays are integrated; an initialization counter which sequentially counts addresses of the memory cell arrays and which initializes data in the memory cells integrated in the memory cell array in accordance with the counter; an I/O buffer to which N-bit data is input and which outputs N-bit data (N is a natural number equal to or larger than 1); a read/write buffer configured to hold M×N-bit data and to which the I/O buffer inputs N-bit data at a time and which outputs N-bit data to the I/O buffer at a time, the memory cell array inputting up to M×N-bit data to the read/write buffer, the read/write buffer outputting up to M×N-bit data to the memory cell array, the read/write buffer writing a variable number of bits to the memory cell array (M is a natural number equal to or larger than 2); an error checking and correcting circuit which checks whether or not an error is detected in the M×N-bit data from the memory cell array and which, when an error is detected, corrects the detected error; and an initialization checking circuit which, after the power-on checking circuit detects power-on, determines whether or not the initialization counter has initialized the data in all the memory cells.