Patent ID: 7229876

Claim:
A fabricating method of a memory, comprising: providing a substrate which is divided into at least a memory cell area and a peripheral circuit area, wherein at least a memory array is formed on the memory cell area and at least a first active area and a second active area are formed in the peripheral circuit area, and a plurality of gate structures are formed on the two active areas; forming a pad oxide layer on the substrate to cover the gate structure; forming a dielectric layer over the pad oxide layer and covering the gate structures; forming a first patterned photoresist layer on the substrate and covering the memory cell area and the second active area; removing a portion of the dielectric layer from the first active area and forming a first spacer on the side walls of the gate structures in the first active area; forming a first source region and a first drain region in the substrate and beside the side walls of the gate structures in the first active area; removing the first patterned photoresist layer; forming a second patterned photoresist layer and the second patterned photoresist layer covering the memory cell area and the first active area; removing a portion of the dielectric layer from the second active area and forming a second spacer on the side walls of the gate structures in the second active area, forming a second source region and a second drain region in the substrate beside the side walls of the gate structures in the second active area; and removing the second patterned photoresist.