Patent ID: 7137035

Claim:
A fault diagnosis apparatus which diagnoses a fault of a parallel processor system, said parallel processor system having a plurality of arithmetic units each having a packet transmission and receiving function; and a network for interconnecting said plurality of arithmetic units; said fault diagnosis apparatus comprising: a determining unit which determines a plurality of pairs of said arithmetic units by combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit); a packet producing unit which produces packets with an identifier attached to data for identifying each of said pairs; a storing unit which stores the test information including the identifier, the information on the arithmetic units constituting the source of said packet with the identifier and the information on said arithmetic units constituting the destination of said packet with the identifier; a transmitting unit which transmits the packets with the identifier from said plurality of source arithmetic units to the corresponding destination arithmetic units, respectively, in the same pair; and an information collecting unit which collects an information on the receiving condition of the packets with the identifier in each of said destination arithmetic units; and a diagnosing unit which diagnoses a fault by accessing the test information using the identifier in the information collected by said information collecting unit as a key.