Patent ID: 7779322

Claim:
An apparatus using a compactor driven by unknown (X) values for compacting test responses at the scan chain outputs of N internal scan chains in a scan-based integrated circuit to generate compacted test responses at M external scan outputs, where N>M, said apparatus comprising: (a) a chain-switching matrix block for receiving said test responses on the scan chain outputs of said N internal scan chains in said scan-based integrated circuit, and to switch said test responses controlled by one or more selection signals of said chain-switching matrix block, wherein said chain-switching matrix block comprises at least one combinational logic gate or switching component other than an XOR logic gate; and (b) a space compaction logic block connected to said chain-switching matrix block for compacting the outputs of said chain-switching matrix block to generate said compacted test responses at said M external scan outputs; wherein X-induced masking and aliasing is minimized, thus allowing fault effects to be observed and fault coverage increases accordingly, and wherein said selection signals are set to control values being determined algorithmically based on the relation between said unknown (X) values and fault effects coming from said N internal scan chain outputs for the purpose of minimizing X-induced masking and error masking.