Patent ID: 8165199

Claim:
A method of clock generation in a compressed video decoder comprising the steps of: receiving a mixed data stream including video data and program clock reference signals; stripping the program clock reference signals from the mixed data stream; determining a time difference between a time indicated by the program clock reference signals and elapsed real time; generating digital control word corresponding to the determined time difference; adjusting the frequency of a decoder clock signal according to the digital control word in a flying-adder frequency synthesizer including receiving a stable frequency signal, detecting a phase difference between the stable frequency signal and a locally generated reference signal, controlling the frequency of a locally generated reference signal corresponding to said detected phase difference, generating a plurality of local clock signals having the same frequency and respective differing phases evenly disbursed over one cycle, periodically adding the digital control word to an accumulated digital word, periodically selecting one of the plural local reference signals according to a current accumulated digital word, and generating the adjusted frequency decoder clock signal by toggling between digital states for each predetermined digital transition in the selected local clock signal; and decoding the video data in the mixed data stream according to the adjusted frequency decoder clock signal.