Patent ID: 8166345

Claim:
A data processing system including a simultaneous multi-threaded (SMT) processor for executing a plurality of threads simultaneously, said system comprising: said SMT processor for simultaneously executing said plurality of threads, wherein said plurality of threads access a first portion of a real memory space included within said system during execution; said SMT processor is for permitting apparently exclusive use of said first portion by a first one of said plurality of threads and simultaneously permitting apparently exclusive use of said first portion by a second one of said plurality of threads, wherein said first and second ones of said plurality of threads simultaneously appear to have exclusive use of said first portion and may simultaneously access said first portion; said plurality of threads being tested simultaneously in response to executing a test program; particular features of said processor being disabled; said test program being executed a first time while said particular features are disabled, said test program generating first results in response to said executing said first time; said particular features being re-enabled; said test program being executed a second time while said particular features are enabled, said test program generating second results in response to said executing said second time; and said SMT processor executing code for comparing said first and second results to determine whether said plurality of threads passed said test.