Patent ID: 6845423

Claim:
A conflict-free memory system, which can reduce access time to a memory system of a Single-Instruction Multiple-Data stream processor having pq units of processing elements, which comprises m units of memory modules where m>pq; an address calculation and routing circuitry, which computes m units of addresses of data elements and routes these values to m units of memory modules; a memory module selection circuitry, which selects pq units of memory modules to be accessed; a data register, which stores designated subarray types, base coordinates, and interval information required for the subarray types; a data routing circuitry, which routes the data in said data register to m units of said memory modules; wherein said conflict-free memory system supports simultaneous access to pq units of data elements of subarray types of four-directional rectangular blocks of South-East Block, South-West Block, North-West Block, and North-East Block, or eight-directional lines of East Line, South-East Line, South Line, South-West Line, West Line, North-West Line, North Line, and North-East Line, each of which is a subarrary located anywhere within a data array, wherein the data elements are related by a constant interval of a positive integer.