Patent ID: 8339298

Claim:
A circuit operable for demultiplexing a digital data stream into a plurality of analog signals, said digital data stream comprising a plurality of data frames with each data frame comprising a plurality of words wherein each word comprises at least sixteen bits, at least one word comprising a header word, which is repeated for each data frame, said circuit comprising: a data bus to carry said data stream comprising at least one data line for each of said at least sixteen bits; a plurality of digital to analog converters operably connected to said data bus, each of said plurality of digital to analog converters comprising a counter input whereby each of said plurality of digital to analog converters is responsive to a count signal on said counter input to produce an analog output responsive to a currently present word on said data bus; a counter element being operably connected to said counter input of each of said plurality of digital to analog converters, said counter element comprising a clock input and being operable to produce said count signal for each of said plurality of digital to analog converters in a known sequence in response to receiving a clock signal on said clock input, said counter element comprising a reset input which resets said known sequence to a known starting point; a memory element operably connected to said data bus, said memory element being responsive to said header word on said data bus to produce a header detect signal; a clock control circuit operably connected to said memory element for receipt of said header detect signal, said clock control circuit comprising a clock operate input to receive a clock operate signal, whereby said clock control is operable to produce said clock signal for said clock input of said counter element responsively to said header detect signal and said operate signal; and a reset/operate switch being operably connected to said clock operate input and to said reset input of said counter element.