Patent ID: 7524759

Claim:
A method for fabricating a chip, comprising: providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and a passivation layer over said dielectric layer; and forming a clock bus over said passivation layer, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said clock bus and said second interconnecting structure, and wherein said forming said clock bus comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.