Patent ID: 8097941

Claim:
A semiconductor device manufacturing method comprising: forming a plurality of wiring lines on one side of a semiconductor substrate; forming, on the wiring lines and said one side of the semiconductor substrate, an overcoat film having openings in parts respectively corresponding to connection pad portions of the wiring lines; forming foundation metal layers each having an edge part, on inner surfaces of the openings of the overcoat film, on parts of the wiring lines in the openings, and on the overcoat film around the openings, the edge parts being located on the overcoat film around the openings; forming, by electrolytic plating, projecting electrodes on the foundation metal layers in the openings of the overcoat film and on the edge parts of the foundation metal lavers, each of the projecting electrodes including a lower projecting electrode portion and an upper projecting electrode portion that has an edge part formed on the edge part of one of the foundation metal lavers, wherein the upper projecting electrode portion is formed on the lower projecting electrode portion and on the edge part; and forming solder balls, such that solder balls cover upper surfaces of the upper projecting electrode portions and side surfaces of the edge parts of the foundation metal lavers.