Patent ID: 8095769

Claim:
A method for address comparison, the method comprising: receiving an input address; determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; wherein a comparison between the input address and a memory segment boundary comprises: applying, by a comparison circuit, a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.