Patent ID: 7184335

Claim:
Electronic memory apparatus for storing data, having: a) a memory cell array which has memory cells arranged in rows and columns; b) a column address decoding unit for decoding a column addressing signal and for actuating an addressed bit line in the memory cell array; c) a column redundancy activation unit for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus; d) a row address decoding unit for decoding a row addressing signal and for actuating an addressed word line in the memory cell array; and e) a row redundancy activation unit for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus, wherein the electronic memory apparatus also has: f) a column deactivation unit for deactivating unused, redundant bit lines and those bit lines which have been determined to be faulty during testing of the memory apparatus; and g) a row deactivation unit for deactivating unused, redundant word lines and those word lines which have been determined to be faulty during testing of the memory apparatus.