Patent ID: 7724084

Claim:
An electronic circuit for reducing harmonics of output signals from a power amplifier in a radio frequency transmission circuit for a wireless communication device, comprising: a printed circuit board (PCB); a power amplifier for generating an output signal for said communication device through an output terminal; and a circuit implemented on the PCB, said circuit connected to said output terminal and comprising: a filtering stage connected to said output terminal; locations for components for a low pass filter, said low pass filter located after said filtering stage; a harmonic filter located after said locations for said low pass filter and having a frequency cut-off point that attenuates first order harmonics of said output signal; and a delay element populated in one location of said locations for components of said low pass filter, said one location providing a connection between said filtering stage and said harmonic filter, said delay element providing a timing delay for the output signal and comprising a 0 ohm rated component, wherein components for said low pass filter are not populated in the remaining locations of said locations for components of said low pass filter.