Patent ID: 7633792

Claim:
A digital image sensor, comprising: an active pixel sensor array; an analog processing circuit coupled to the active pixel sensor array; an analog-to-digital converter (ADC) circuit coupled to the analog processing circuit; a control circuit coupled to the active pixel sensor array, the analog processing circuit, and the ADC circuit; a control register coupled to the control circuit; and a dual port memory coupled to the analog processing circuit and the control circuit, the dual port memory comprising: an input bus; an output bus; an input/output circuit coupled to the input and output busses and configured to write data received on the input bus during a write operation and provide read data to the output bus during a read operation, the input/output circuit comprising a plurality of amplifier circuits each coupled to one of a plurality of digit lines, each amplifier circuit having a first pair of series coupled tri-state inverters coupled between the input bus and a respective digit line and a second pair of series coupled tri-state inverters coupled between the respective signal digit and the output bus; control circuitry coupled to the input/output circuit and configured to control the input/output circuits during write and read operations; a memory array coupled to the input/output circuit, the memory array having a plurality of memory cells, each of the memory cells coupled to one of the plurality of digit lines, each memory cell comprising: a first inverter having a first input node and a first output node; a second inverter having a second input node, a second output node, and a control node at which a control signal is applied, the second inverter configured to be disabled in response to an active control signal, the second output node coupled to the first input node and the first output node coupled to the second input node; and an access switch having a first node coupled to the second output node, having a second node coupled to the digit line, and further having a switch node to which a switch signal is applied, the access switch configured to couple the first and second nodes in response to an active switch signal; and wherein the control circuitry is operable to generate the control signal and the switch signal, the control circuitry operable to execute a write operation by coupling the active switch signal to the access switch while applying the active control signal to the second inverter, then coupling an inactive switch signal to the access switch while applying an inactive control signal to the second inverter, activating the second inverter.