Patent ID: 7859049

Claim:
A semiconductor device, comprising: a first conductivity type well region disposed on a surface of a semiconductor substrate at a predetermined depth; a plurality of trench regions disposed at a depth smaller than the predetermined depth of the first conductivity type well region; a gate electrode disposed on a side surface of each of the plurality of trench regions via a gate insulating film and brought into contact with the gate insulating film; a second conductivity type drain region disposed at a part of a bottom of each of the plurality of trench regions, wherein a width of the drain region is less than a width of the trench region and lateral sides of the drain region are apart from corresponding sides of the trench region by at least a thickness of the gate insulating film; a second conductivity type source region disposed in a region formed between the plurality of trench regions, and disposed on the surface of the semiconductor substrate along the gate insulating film; and a first conductivity type high concentration region disposed in a region formed between the plurality of trench regions, and disposed on the surface of the semiconductor substrate to be brought into contact with the second conductivity type source region.