Patent ID: 8566682

Claim:
A computer implemented method for detecting bus failures, the method comprising: receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus, the bus comprising a plurality of lanes and protected by the error detection code, each of the lanes having an associated running counters storing values; performing for each of the syndromes: performing for each of the lanes: decoding the syndrome under an assumption that the lane is a failing lane, the syndrome indicating multiple possible failing lanes for a single error, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode, the voting comprising incrementing the running counter associated with the lane, wherein the incrementing is repeated for each of the possible failing lanes for the single error; and identifying a failing lane from the possible failing lanes in response to the voting, the identifying comprises comparing the values in the running counters relative to each other to select the failing lane, the failing lane characterized by having more votes than at least one other lane on the bus.