Patent ID: 7613208

Claim:
A communication interface between a first and a second communication bus using respectively a first and a second protocol, each protocol having specifications suitable for the coding of data, said communication interface comprising: a memory comprising a first and a second access port, each of the ports being controllable independently of one another; a first transcoding circuit supporting the first protocol, and being coupled to the first access port of the memory, the first transcoding circuit making it possible to encode data situated in the memory so as to transmit them to the first bus according to the specifications of the first protocol, and/or making it possible to decode data received from the first bus according to the specifications of the first protocol so as to store them in the memory; a second transcoding circuit supporting the second protocol, and being coupled to the second access port of the memory, the second transcoding circuit making it possible to encode data situated in the memory so as to transmit them to the second bus according to the specifications of the second protocol, and/or making it possible to decode data received from the second bus according to the specifications of the second protocol so as to store them in the memory; and a control circuit coupled to the first and second transcoding circuits for ensuring synchronization between the transcoding circuits, so that the second transcoding circuit triggers the data encoding only after the first transcoding circuit has stored in the memory the data sufficient for a formatting according to the second protocol.