Patent ID: 8362757

Claim:
A low power voltage regulator for supplying operating voltage to circuits required to maintain data and/or be operational during an integrated circuit device low power sleep mode, comprising: a first constant current source connected to a supply voltage source; a first N-channel field effect transistor (FET) having a source, a drain and a gate, wherein the drain of the first N-channel FET is connected to the supply voltage, the gate of the first N-channel FET is connected to the first constant current source and the first constant current source is connected between the gate and drain of the first N-channel FET; a second N-channel FET having a source, a drain and a gate, wherein the drain of the second N-channel FET is connected to the gate of the first N-channel FET and the first constant current source, and the source of the second N-channel FET is connected to a supply voltage common; a second constant current source connected to the supply voltage common and the gate of the second N-channel FET; a first P-channel FET having a source, a drain and a gate, wherein the drain and gate of the first P-channel FET are connected to the gate of the second N-channel FET and the second constant current source, and the source of the first P-channel FET is connected to the source of the first N-channel FET; the first and second N Channel FETs, the first P channel FET and the first and second constant current sources comprise a low power secondary voltage regulator having an output, wherein the output of the low power secondary voltage regulator is the connected sources of the first P channel FET and the first N channel FET; and a maintained voltage core logic of an integrated circuit device connected to the output of the low power secondary voltage regulator; a second P-channel FET having a source, a drain and a gate, wherein the drain of the second P-channel FET is connected to the sources of the first N-channel and first P channel FETs, the gate of the second P-channel FET is connected to the drain of the second N-channel FET and the first constant current source, and the source of the second P-channel FET is connected to an output from a primary voltage regulator; wherein the maintained voltage core logic is coupled to and receives its operating voltage from the primary voltage regulator through the second P channel FET when the integrated circuit device is in an operational mode.