Patent ID: 7939406

Claim:
A method for manufacturing a semiconductor device in a selective gate region which is provided with a selective transistor formed adjacent to a memory cell array region, the method comprising: forming a first insulating film on a semiconductor layer; forming a first electrode layer on the first insulating film; forming an element isolating region including an element isolating insulating film extending through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, and isolating an element region by the element isolating region; removing an upper portion of the element isolating insulating film after the forming the element isolating region to position a surface of the element isolating insulating film whose upper portion is removed below a surface of the first electrode layer; forming a second insulating film on the element isolating region and the first electrode layer; removing the second insulating film selectively to form an opening through which a surface of the first electrode layer is exposed; forming a second electrode layer on the second insulating film and the exposed surface of the first electrode layer; and removing the first electrode layer, the second insulating film, and the second electrode layer selectively to form a gate electrode.