Patent ID: 8571049

Claim:
A device comprising: a first line card including: a memory including different space allocations for queuing of header cells of packets associated with different queues; and a processor to: identify, among the queues, a queue for which an initial maximum size of the space allocation set for the queuing of the header cells of packets associated with the identified queue is to be modified, modify the initial maximum size of the space allocation for the queuing of the header cells of packets associated with the identified queue, receive a packet, set an initial maximum size of a packet buffer provided for the queuing of the packet, increase the initial maximum size of the packet buffer based on an average size of the packets associated with the identified queue, and a maximum number of header cells that the space allocations for the different queues can store, insert a header cell, associated with the packet, in the space allocation for the identified queue, identify a second line card from which the packet is to be sent to another device in a network, remove the header cell from the space allocation for the identified queue, and forward the header cell to the second line card; and the second line card to: receive the header cell from the first line card, and send the packet to the other device in the network.