Patent ID: 7704814

Claim:
A method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor, comprising the steps of: simultaneously forming a first well in a low-voltage MOS transistor region of a semiconductor substrate and a second well in a high-voltage MOS transistor region of the substrate by implanting first ions at a high implantation energy into an entire surface of the substrate; forming a first gate oxide layer and a first gate electrode in the low-voltage MOS transistor region and forming a second gate oxide layer and a second gate electrode in the high-voltage MOS transistor region; forming a first photoresist pattern to expose the low-voltage MOS transistor region; forming a first LDD region in the low-voltage MOS transistor region by implanting second ions at a low implantation energy using the first photoresist pattern and the first gate electrode as masks; removing the first photoresist pattern; forming a second photoresist pattern to expose the high-voltage MOS transistor region; forming a second LDD region in the high-voltage MOS transistor region by implanting third ions at a low implantation energy using the second photoresist pattern and the second gate electrode as masks; forming a high voltage well for the high voltage MOS transistor by implanting fourth ions at a high implantation energy into the second well in the high-voltage MOS transistor region using the second photoresist and the second gate electrode as masks after forming the second LDD region; and removing the second photoresist pattern.