Patent ID: 7002175

Claim:
A double barrier resonant tunneling diode (RTD) integrated with a CMOS/BJT/SiGe device and circuitry level by means of metal-to-metal bonding to form a three-dimensional (3-D) electrically interconnected architecture, comprising: a substrate having a substantially horizontal planar upper surface, said substrate including an embedded level of CMOS/BJT/SiGe devices, structures and circuitry; a first metal barrier layer formed on said planar upper surface; a first metal bonding layer formed on said first metal barrier layer; a horizontally layered, patterned RTD formed above the substrate, said RTD having an upper layer that is a collection electrode and a lower layer that is an injection electrode and said RTD having substantially vertical etched lateral edges against which are formed lateral isolation layers; a second metal barrier layer formed on a lower surface of said injection electrode; a second metal bonding layer formed on said second metal barrier layer, said second metal bonding layer being bonded to said first metal bonding layer by a process of metal-to-metal bonding, thereby joining the RTD to said substrate; conducting interconnects electrically connecting the RTD to said CMOS/BJT/SiGe devices, structures and circuitry; and electrical connections formed on said injection and collection electrodes.