Patent ID: 7351627

Claim:
A method of manufacturing a semiconductor device, comprising: forming a gate stack over a semiconductor substrate; performing ion implantation for formation of wells, ion implantation for control of threshold voltage and junction ion implantation for formation of source/drain regions, in cell regions, utilizing a cell-open mask, on the entire surface of the semiconductor substrate having the gate stack formed thereon; sequentially performing first ion implantation for formation of wells, second ion implantation for control of threshold voltage, and third ion implantation for formation of source/drain regions, in an NMOS region of a peripheral circuit region, utilizing an NMOS-open mask, on the entire surface of the gate stack and the semiconductor substrate within the NMOS region; and sequentially performing fourth ion implantation for formation of wells, fifth ion implantation for control of threshold voltage, and sixth ion implantation for formation of source/drain regions, in a PMOS region of the peripheral circuit region, utilizing a PMOS-open mask, on the entire surface of the gate stack and the semiconductor substrate within the PMOS region.