Patent ID: 7871831

Claim:
A computer-implemented method for implementing flip chip connections, comprising: generating a first projection that includes a bump sequence, wherein the bump sequence comprises ordered representations of bumps arranged over a core of a flip chip, wherein the act of generating the first projection comprises drawing a line through a bump between a location within a first ring of the flip chip and an outer portion of the flip chip; generating a second projection that includes a pad sequence, wherein the pad sequence comprises ordered representations of I/O pads arranged around the core; determining locations for placement of the bumps or I/O pads of the flip chip based at least in part upon the ordered representations of the bumps or I/O pads, wherein the first projection comprises the bump sequence of at least one bump representation of the first ring and at least one bump representation of a second ring, the first ring and the second ring are different rings of the flip chip, the first ring being an inner ring to the second ring determining connections between the bumps and I/O pads based at least in part upon connections between bump and I/O pad representations of respective first and second projections; and implementing the connections between the bumps and I/O pads based at least in part upon the determined connections.