Patent ID: 7696044

Claim:
A method of making an array of non-volatile memory cells on a semiconductor substrate, comprising: forming a first set of trenches in a surface of the substrate that are spaced apart in a first direction and elongated in a second direction across the substrate surface, the first and second directions being orthogonal with each other, forming source and drain regions in at least bottom surfaces of the first set of trenches along their lengths, isotropically depositing first material over and into the first set of trenches, anisotropically removing the deposited first material in a manner to leave spacers along opposite side walls of the first set of trenches with spaces therebetween in the first direction, wherein the spacers become charge storage elements of the array of memory cells, and forming conductive first control gates that extend in the second direction in the spaces in the first set of trenches between the spacers and conductive first control gate lines that extend in the second direction over the first control gates to which they are electrically connected.