Patent ID: 8924450

Claim:
A time-division (TD) decimation filter bank, comprising: a half decimation filter unit, operated at a system clock for receiving an input data string, and taking 2 N clock periods as an operation-period unit for the half decimation filter unit, N=4, wherein the half decimation filter unit receives the input data string and receives a plurality of feedback data of the half decimation filter unit by TD, so as to distribute the received data into the 2 N clock periods for filtering and decimation and outputting by TD, wherein in the half decimation filter unit so that 16 clock periods are taken as the operation-period unit, wherein the 16 clock periods are respectively numbered as 0-15 shown in a following table, wherein I represents a first part data of each of the data, Q represents a second part data of each of the data, I2, Q2 represent an output of a second stage filtering and decimation operation, I3, Q3 represent an output of a third stage filtering and decimation operation, and I4, Q4 represent an output of a fourth stage filtering and decimation operation, and the table is: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I2 I2 I2 I2 Q2 Q2 Q2 Q2 I3 I3 Q3 Q3 I4 Q4 or 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I2 I2 I2 I2 Q2 Q2 Q2 Q2 I3 I3 Q3 Q3 I4 Q4 or 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I2 I2 I2 I2 Q2 Q2 Q2 Q2 I3 I3 Q3 Q3 I4 Q4 .