Patent ID: 8497539

Claim:
A semiconductor device comprising: a plural memory cells that respectively include a capacitor structure formed above a semiconductor substrate and constituted by sandwiching a dielectric film with a lower electrode and an upper electrode, and a transistor for selecting the capacitor structure, wherein the capacitor structure of the respective memory cells is respectively formed in either one layer of at least two layers of interlayer insulating films having different heights from a surface of the semiconductor substrate; wherein between two layers of the interlayer insulating films having been laminated adjacently, a first protective film is formed between a first connecting plug and the lower electrode, a second protective film is formed between the upper electrode and a second connecting plug, and a third protective film is formed between a third connecting plug and a fourth connecting plug, wherein the first protective film, the second protective film, and the third protective film are formed in an insulating film provided between the two layers of the interlayer insulating films, and wherein a surface of the first protective film, a surface of the second protective film, a surface of the third protective film, and a surface of the insulating film have the same height from the surface of the semiconductor substrate.