Patent ID: 7227220

Claim:
A semiconductor device, comprising: a semiconductor substrate having a first conductivity type and having an upper portion; a pair of bit lines extending in a first direction, the pair of bit lines doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate; a first line formed between the pair of bit lines and extending parallel to the bit lines, the first line comprising a plurality of alternating channel regions and recessed device isolation regions, each of the channel regions contacting each bit line of the pair of bit lines, wherein the recessed device isolation regions isolate the pair of bit lines from one another; and a plurality of word lines formed at right angles to the bit lines and covering the channel regions; wherein each of the channel regions includes an upper surface proximate a word line of the plurality of word lines and a sidewall extending from the upper surface toward the substrate, the device further comprising an ONO layer on the sidewall and the upper surface of the channel regions, wherein the word lines are formed on the ONO layer.