Patent ID: 6883123

Claim:
A microprocessor runaway monitoring control circuit, for a microprocessor which controls an electrical load and generates a first watchdog clearing signal and a second watchdog clearing signal for monitoring runaway of the microprocessor, comprising: a first watchdog timer for receiving the first watchdog clearing signal and generating a first reset signal if this first watchdog clearing signal is abnormal; a second watchdog timer for receiving the second watchdog clearing signal and generating a second reset signal if this second watchdog clearing signal is abnormal; a logical connector circuit for resetting the microprocessor by outputting an effective resetting signal when the first and second reset signals are both generated; and failure diagnosing means for inputting the first and second reset signals respectively as first and second monitor signals to the microprocessor, wherein at different timing to each other, the microprocessor intentionally renders abnormal the first and second watchdog clearing signals and checks whichever of the first and second monitor signals corresponds to one of the first and second watchdog clearing signals intentionally rendered abnormal and thereby checks the operation of whichever of the first and second watchdog timers corresponding to one of the first and second watchdog clearing signals rendered abnormal.