Patent ID: 6862678

Claim:
An apparatus for processing data, said apparatus comprising: A special register bank of N-bit data processing registers; A general register bank of N-bit data processing registers; A selector, coupled to the special register bank and the general register bank, for selecting one of the special and general register banks and outputting a selected N-bit result from the selected register bank in according to a class signal received by the selector, wherein the selected N-bit result and a N-bit data form a 2N-bit addition operand, wherein the class signal is used for indicating either a first class of instruction or a second class of instruction; A multiplier for performing multiply operation upon a first operand and a second operand and outputting an 2N-bit multiplied result; One accumulator, coupled to the multiplier, the selector and the general register bank, for performing accumulate operation upon the 2N-bit multiplied result and the 2N-bit addition operand and outputting a 2N-bit accumulated result.