Patent ID: 7989284

Claim:
A method for forming a memory device, the method comprising: providing a substrate comprising a surface region; forming a well structure within the substrate; forming isolation regions within the well structure; providing a protective layer overlying the surface region, the surface region extending over the well structure; depositing a photo resist layer overlying the protective layer; patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region; implanting impurities for threshold voltage adjustment into the first region using the patterned photo resist as a mask; maintaining the second region substantially free of the impurities for threshold voltage adjustment; removing the photo resist mask; providing a gate dielectric layer overlying the surface region; forming a gate stack over the gate dielectric layer, the gate stack comprising a silicide layer overlying a polysilicon layer; implanting impurities into the substrate using the gate stack as a mask to form lightly doped drain (LDD) structures; providing spacers on sides of the gate stack; forming a source region and a drain region; providing a contact structure over the source region, a junction region between the contact structure and the source region being substantially within the second region; and providing a charge storage capacitor, the capacitor being in electrical contact with the source region via the contact structure.