Patent ID: 7750963

Claim:
A timing signal generating circuit comprising a memory and a pulse generator, wherein: the memory stores information related to a timing signal, said timing signal comprising a number of pulses, said information comprising (i) pulse count data indicating the number of pulses of said timing signal, (ii) rising edge position data of the timing signal, and (iii) falling edge position data of the timing signal, and the pulse generator produces said timing signal corresponding to the stored information, said pulse generator comprising a first circuit for generating rising edge signals corresponding to respective pieces of said rising edge position data, a second circuit for generating falling edge signals corresponding to respective pieces of said falling edge position data, an active control circuit for setting in an active state: (i) rising edge signals generated by a first circuit, and (ii) falling edge signals generated by said second circuit, and a third circuit for generating said timing signal corresponding to the active state rising edge signals and the active state falling edge signals, wherein, said active control circuit performs setting in an active state responsive only to a single one of (i) pulse count data indicating the number of pulses of said timing signal, (ii) rising edge position data of the timing signal, and (iii) falling edge position data of the timing signal.