Patent ID: 7562258

Claim:
A data processing apparatus comprising: a device operable to perform a sequence of operations including memory operations on data values having associated data addresses, for at least some of the memory operations the data address being determined relative to an architectural state value of an item of architectural state of the device; and trace logic operable to receive indications of the sequence of operations being performed by the device, and to generate from said indications a stream of trace elements; when for a memory operation the data address is determined to have been determined relative to an architectural state value of said item of architectural state, the trace logic being operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation, wherein: the trace logic is operable to reference an enable field associated with said item of architectural state, the enable field being settable by a user to an enable state or a disable state; and when for a memory operation the data address is determined to have been determined relative to an architectural state value of said item of architectural state, the trace logic is operable dependent on that item of architectural state and the state of the enable field to determine whether to omit at least one of the data address indication and data value indication from the stream of trace elements.