Patent ID: 7732838

Claim:
A semiconductor device comprising: a first gate line formed on a semiconductor substrate; a first thin insulating layer formed on the sidewalls of the first gate line; a second gate line of a spacer shape formed on the first thin insulating layer at one sidewall of the first gate line; a third gate line of a spacer shape formed on the first thin insulating layer at the other sidewall of the first gate line; a first contact electrode vertically connected with the first gate line; first dummy gates formed on the semiconductor substrate adjacent a first side of the first gate line; a second thin insulating layer formed on the sidewalls of the first dummy gates; a second gate pad of a spacer shape formed on the second thin insulating layer filling gaps between the first dummy gates, wherein the second gate pad is electrically connected with the second gate line; second dummy gates formed on the semiconductor substrate adjacent a second side of the first gate line; a third thin insulating layer formed on the sidewalls of the second dummy gates; a third gate pad of a spacer shape formed on the third thin insulating layer filling gaps between the second dummy gates, wherein the third gate pad is electrically connected to the third gate line; a second contact electrode vertically connected with one or more of the first dummy gates and the second gate pad; and a third contact electrode vertically connected with one or more of the second dummy gates and the third gate pad.