Patent ID: 6911397

Claim:
A method of forming a dual damascene interconnection, comprising: sequentially forming a lower insulating layer, an upper etch-stop layer, an upper insulating layer, and a hard mask layer on a semiconductor substrate where a lower conductive layer is formed; patterning the hard mask layer and the upper insulating layer to form an interconnection groove in the upper insulating layer, the interconnection groove exposing a portion of the upper etch-stop layer; forming a spacer on a sidewall of the interconnection groove; forming a photoresist pattern having an opening that exposes the interconnection groove and the portion of the upper etch-stop layer; successively etching the upper etch-stop layer and the lower insulating layer to form a hole in the lower insulating layer, the hole exposing a portion of the lower conductive layer; removing the patterned hard mask layer and the spacer; and forming an interconnection to fill the interconnection groove and the hole.