Patent ID: 8054607

Claim:
A multilayer chip capacitor comprising: a capacitor body including a plurality of dielectric layers that are stacked; first and second outer electrodes formed on an outer surface of the capacitor body and having opposite polarity; first and second inner electrodes opposing each other, interleaved with the dielectric layers in the capacitor body, and each including an electrode plate forming capacitance and a lead extending from the electrode plate, the lead of the first inner electrode and the lead of the second electrode being respectively connected to the first and second outer electrodes; and third inner electrodes interposed between the first and second inner electrodes, wherein at least one of the third inner electrodes adjacent to the first inner electrode includes a conductive pattern having the same shape as the lead of the first inner electrode and is connected to the first outer electrode, and at least one of the third inner electrodes adjacent to the second inner electrode includes a conductive pattern having the same shape as the lead of the second inner electrode and is connected to the second outer electrode.