Patent ID: 7701250

Claim:
A logic module and flip-flop arrangement comprising: a first input multiplexer having a plurality of data inputs coupled to routing resources, and an output; second through nth input multiplexers, each having a plurality of data inputs coupled to routing resources, and an output; a clock multiplexer having a plurality of inputs coupled to clock resources, and an output; an input-select multiplexer having a plurality of inputs and an output, a first input of the input-select multiplexer coupled to the output of the first input multiplexer; a flip-flop having a clock input coupled to the output of the clock multiplexer, a data output coupled to a second input of the input-select multiplexer, and a data input; a logic module having a plurality of data inputs and an output, one data input of the logic module coupled to the output of the input select multiplexer, the other data inputs of the logic module each coupled to the output of a different one of the second through nth input multiplexers; and a flip-flop/routing multiplexer having an output coupled to the data input of the flip-flop, a first input coupled to the output of the first input multiplexer, a second input coupled to the data output of the logic module, and at least one input coupled to routing resources.