Patent ID: 8099688

Claim:
A design process including inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, using a computer to translate the circuit design into a netlist, wherein the netlist comprises a representation of a plurality of wires, transistors, and logic gates, and wherein the netlist is stored in the non-transitory computer-readable medium; and when executed by the computer, produces the circuit design comprising: a static random access memory (“SRAM”), including a plurality of SRAM cells arranged in an array, said array including a plurality of rows and a plurality of columns; and a plurality of column voltage control circuits corresponding to respective ones of said plurality of columns of said array, each of said plurality of voltage control circuits coupled to an output of a power supply, each said voltage control circuit being operable to temporarily reduce a voltage upon arrival of a bit select signal provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of said plurality of columns, said selected column being selected during a write operation in which a bit is written to one of said plurality of SRAM cells belonging to said selected column, wherein each said column voltage control circuit includes an n-type field effect transistor (“NFET”) and a pair of p-type field effect transistors (“PFET”) wherein one of the PFETs is configured such that its gate is connected to its drain, each of said NFET and said pair of PFETs having a conduction path directly connected between the output of the power supply and said power supply inputs of said plurality of SRAM cells.