Patent ID: 8140925

Claim:
An apparatus for evaluating a logic state of an integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, each said IC supporting multiple synchronous frequency clock domains, said apparatus comprising: a first circuit means for generating a synchronized set of enable signals in correspondence with multiple IC sub-units for starting operation of multiple IC sub-units according to a determined timing configuration; and a second circuit means responsive to one signal of said synchronized set of enable signals to start counting a number of clock cycles of a fastest processor clock operating on said chip and, upon attaining a pre-specified clock cycle number, generating a stop signal for each unique frequency clock domain associated with a different clock frequency of said multiple synchronous frequency clock domains, said stop signals output in parallel to synchronously stop a respective functional clock operating at said different clock frequency for each respective synchronous frequency clock domain, wherein all on-chip functional clocks are synchronously stopped on all frequency clock domains in a deterministic fashion to place said IC in a state for scanning out IC logic state data values for debugging a logic design flaw from said IC.