Patent ID: 8082398

Claim:
A data processor comprising: a central processing unit performing instructions; a memory storing instructions and data; and a buffer maintaining part of instructions and data stored in the memory, wherein the central processing unit has a register, into which an intended value is set in accordance with execution of an instruction, and executes a specified instruction that generates an effective address of data by adding an offset to a value set to the register, wherein the buffer includes: an instruction cache storing a stream of instructions executed by the central processing unit; a data cache storing a stream of data used for the central processing unit to execute instructions; and an address generator circuit generating a data prefetch address, the data prefetch address being used for the data cache that stores a data stream containing data corresponding to an effective address designated by the specified instruction contained in a new instruction stream stored in the instruction cache, wherein the instruction cache includes: a line address latch latching a line address for one cache line in accordance with an address generated by the central processing unit for accessing the memory; and a line instruction latch maintaining an instruction on a cache line selected by the access address, wherein the address generator circuit generates an instruction prefetch address corresponding to an address of a line next to a line address latched by the line address latch, acquires a cache line address of a data cache corresponding to an offset designated by the specified instruction contained in an instruction stream latched by the line instruction latch, sequentially maintains cached line addresses, and adds a value of the register to a maintained cache line address to output a data prefetch address.