Patent ID: 7838363

Claim:
A method of forming a split gate memory cell comprising: providing a semiconductor substrate; providing a first dielectric layer overlying the semiconductor substrate; providing a layer of select gate material overlying the first dielectric layer; providing a second dielectric layer overlying the layer of select gate material; providing a third dielectric layer overlying the second dielectric layer; providing a patterned mask material overlying the third dielectric layer to mask a select gate region and expose an immediately adjacent control gate region, the patterned mask material defining a region for a source and a drain in the semiconductor substrate; removing the first dielectric layer, the layer of select gate material, the second dielectric layer and the third dielectric layer in the control gate region; forming a charge storage layer on exposed surfaces; forming a layer of control gate material; planarizing the layer of control gate material to expose the third dielectric region in the select gate region and thereby remove the charge storage layer from an upper surface of the select gate region to expose the select gate material and the control gate material; removing a portion of the control gate material to recess a height of the control gate material and forming a differential in height between the control gate material and the select gate material, said removing causing the select gate material to have a greater height than the control gate material; removing a second portion of the charge storage layer to leave the charge storage layer between the control gate material and both the select gate material and the semiconductor substrate; and forming a source and a drain in the semiconductor substrate by removing layers directly overlying the semiconductor substrate in source and drain regions adjacent the control gate material and the select gate material and performing an ion implant to complete formation of the split gate memory cell.