Patent ID: 8164375

Claim:
A clock generator, comprising: a delay circuit configured to delay a first clock signal of a first clock domain by an amount to produce an output clock signal and couple the output clock signal to a downstream circuit, the delay circuit further configured to receive a control signal indicative of a change in the amount; a synchronizer circuit configured to synchronize a second clock signal of a second clock domain with the first clock signal of the first clock domain; a first switching element configured to decouple the delay circuit from the downstream circuit responsive in part to the control signal indicative of the change in the amount; a second switching element configured to decouple the first clock signal from the delay circuit at a time after the delay circuit was decoupled from the downstream circuit; and a phase storage element coupled to the delay circuit and configured to store a phase relationship between the first and second clock signals during a time when the first clock signal is decoupled from the delay circuit, wherein the first switching element comprises a multiplexer having two inputs, a first input coupled to receive an input clock signal and a second input coupled to ground.