Patent ID: 7047023

Claim:
A GPS RF front end integrated circuit, comprising: input means for accepting a 13 MHz reference signal; a voltage controlled oscillator (VCO having an input, the VCO providing a Local Oscillator (LO) signal of approximately 1536 fo, a divide-by-4 prescaler, having an input coupled to the VCO output; a Programmable Modulus (PM) divider, having an input; an accumulator, having an addend input and an output sum, the accumulator being coupled to the input of the PM divider, comprising an overflow bit which controls the selectable divider, wherein the overflow bit is used to provide a time averaged divide ratio of 30.21875; a first register coupled to the addend input of the accumulator; a second register coupled to the output sum of the accumulator; a first mixer and a second mixer for providing an image reject mixer function; a first IF filter and a second IF filter, each having a center frequency of 4 fo and each having high attenuation near dc; an IF combiner circuit to effect image rejection by phase shifting and summation; a divide-by-8 counter to synthesize a CLKGPS signal; a divide-by-3 counter to synthesize a CLKACQ signal; a linear AGC function; and an A/D converter which provides a sampled, digital representation of the IF signal.