Patent ID: 8321697

Claim:
A memory device connectable to a host device comprising: a non-volatile memory section; a first I/O cell that can transmit and receive a command signal, response signal, clock signal and data signal to/from the host device via a command signal line, response signal line, clock signal line or data signal line respectively at any one signal voltage selected from a first voltage and a second voltage which is lower than the first voltage; a first regulator that can output the first voltage and the second voltage; and a memory controller that sends, upon receiving the command signal requesting switching of the signal voltage from the first voltage to the second voltage from the host device, information indicating that the signal voltage will be switched to the host device using the response signal, switches a voltage outputted by the first regulator from the first voltage to the second voltage, applies, upon detecting that a voltage other than a ground level is applied to the clock signal line after a lapse of a predetermined time, the second voltage to the response signal line and the data signal line of the ground level, and starts transmission/reception at the signal voltage of the second voltage.