Patent ID: 8730721

Claim:
A FLASH memory device comprising: a plurality of FLASH memory cells configured to store data received from a source external to the flash memory device, the plurality of FLASH memory cells organized into a plurality of blocks, each block comprising a plurality of pages, and each page defining an individually addressable physical memory location; at least one modified memory cell associated with each block, the at least one modified memory cell configured in such a manner that it is more susceptible to a read disturb error than the plurality of FLASH memory cells; a controller operatively coupled to the FLASH memory cells and configured to: access a logical-to-physical translation table that associates a logical address provided in a WRITE request with a physical address corresponding to a page within a first block; accumulate a Block READ Count corresponding to the number of times any of the FLASH memory cells in the first block, including at least one modified memory cell associated with the first block, have been read; and respond to a plurality of READ requests for pages within the first block received after the Block READ Count has reached a predetermined number and no read disturb error has been detected for the at least one modified memory cell associated with the first block, such response comprising: moving data associated with a requested page to a page in a second block that is different from the first block, without moving data associated with other pages in the first block to a different block, and modifying the logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.