Patent ID: 8312334

Claim:
A semiconductor test apparatus that sorts addresses corresponding to memory cells in memory in a tested device, sorts failure data obtained as a result of testing the memory cells, and stores the sorted addresses and failure data in acquisition memory using burst access, comprising: an address generator configured to generate a burst target signal, which indicates that the addresses and failure data are target data for burst access, and to generate a burst stop signal, which indicates the end of the target data for burst access; and a sort circuit configured to sort the addresses and failure data in order of continuous addresses suitable for burst access, on the basis of the burst target signal and the burst stop signal, wherein in the case where the addresses and failure data to be sorted on the basis of the burst target signal do not satisfy the number of data blocks required for burst access with respect to the acquisition memory, the sort circuit appends one or more dummy addresses and dummy failure data making the result of testing as pass to the addresses and failure data.