Patent ID: 7685439

Claim:
A method for functional control of execution of a program and/or data flow in a Single Instruction Multiple Data signal processor, the signal processor having parallel arithmetic and logic functional units (“ALUs”) and/or data paths (DPs) for the execution of program instructions and/or data flow, wherein each ALU and/or DP has at least a gated clock cell input for receiving a clock pulse supply, the signal processor further including a program control unit (PCU), an interrupt processing unit, and data and program memories, the method comprising: receiving at least one of a hardware-related signal, which is applied externally to the signal processor, and a software-related state output, which is generated from internal flow of the program in the signal processor; and in response to the hardware-related signal, switching off the clock supply of all ALUs and/or DPs of the signal processor that are not being used for the program execution and/or data flow for the duration of their non-use, and in response to the software-related state output, switching off the clock supply of particular ALUs and/or DPs of the signal processor that are not being used for the program execution and/or data flow for the duration of their non-use.