Patent ID: 8003511

Claim:
A memory cell formation method, comprising: forming a bottom electrode in a first layer of an electrically conductive material using a first mask to pattern the first layer of the electrically conductive material and using an etchant to etch the first layer of the electrically conductive material at a first temperature and a first pressure; forming one or more layers of unetched conductive metal oxide (CMO) by depositing one or more layers of CMO over the bottom electrode in a plane that is substantially parallel to another plane associated with the first layer of the electrically conductive material, wherein portions of the one or more layers of CMO that are positioned above the bottom electrode are components of a memory element without etching the one or more layers of CMO; and ion implanting the one or more layers of CMO using one or more other layers of material that are positioned above the one or more layers of CMO as an implantation mask, the ion implanting operative to form electrically non-conductive insulating metal oxide (IMO) regions in the one or more layers of CMO that are not protected by the implantation mask and the IMO regions are positioned substantially adjacent to electrically conductive CMO regions that are positioned above the bottom electrode, are protected by the implantation mask, and comprise the components of the memory element.