Patent ID: 6882661

Claim:
A system for transferring a data stream comprising data packets separated by non-packet words from a first clock domain to a second clock domain, the clock domains having similar but not necessarily identical clock frequencies, comprising: an elasticity buffer consisting of at least three and not more than five storage locations: means for writing the data stream into the elasticity buffer in a cyclic sequence of said storage locations by means of a write pointer under the control of a write clock in the first clock domain, means for reading the data stream out of said storage locations of the elasticity buffer in said cyclic sequence by means of a read pointer under the control of a read clock in the second domain; a slip detector for monitoring the write and read pointers to determine the relative cyclic phase of said two pointers, said slip detector: (i) providing an anticipatory signal by monitoring proximity of a reading sequence to a writing sequence indicating that the read clock is too late when the write pointer denotes a first one of said storage locations and the read pointer denotes the next one of said storage locations in said cyclic sequence; (ii) by monitoring proximity of the reading sequence to a beginning of the buffer indicating that said read clock is too early when the write pointer denotes said first one of said storage locations and the read pointer denotes said first one of said storage locations in said cyclic sequence; means in the first clock domain for inserting in response to said anticipatory signal indicating that the read clock is too late, non-packet word into said data stream; and means in the second clock domain for detecting the existence of the inserted non-packet word and for causing the buffer to advance the read cycle thereby to discard the inserted non-packet word.