Patent ID: 7502889

Claim:
A system comprising: a plurality of processor nodes that share distributed memory, each processor node including a processor core; at least one interconnect interface, each interconnect interface to provide a path from a respective processor node to at least one other processor node of said plurality of processor nodes; and a cache to store copies of data used by the processor core, the cache to write-back a cache entry selected for eviction from the cache to a memory of the distributed memory from which the cache entry originated, wherein the cache is to store with each cache entry a cache bit vector, wherein the cache bit vector comprises a t-bit cost metric and one Least Recent Used (LRU) bit, the t-bit cost metric represents a relative distance between said cache and the originating memory of a cache entry, where t>1, and the LRU bit is set if the cache entry is accessed and reset if all LRU bits are set and another cache entry is accessed, said cache to select which cache entry to evict based on the a cost value determined by the cache bit vector.