Patent ID: 7301828

Claim:
A memory circuit, comprising: a plurality of bit line structures, each of said bit line structures comprising at least three bit lines; a plurality of word lines, said word lines intersecting with said bit line structures at a plurality of sites; a plurality of switching devices, individual ones of said switching devices being located at selected ones of said sites and being connected between an adjacent one of said word lines and a selected one of said bit lines of an adjacent one of said bit line structures for selective electrical conduction therebetween upon activation by said adjacent one of said word lines; and a plurality of column sense logic units, each of said column sense logic units being associated with a corresponding one of said bit line structures, each of said column sense logic units in turn comprising: a first logic gate having a first input electrically interconnected with a first one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with a second one of said bit lines in said corresponding one of said bit line structures; and a second logic gate having a first input electrically interconnected with a third one of said bit lines in said corresponding one of said bit line structures and a second input electrically interconnected with said second one of said bit lines in said corresponding one of said bit line structures.