Patent ID: 7605409

Claim:
A semiconductor device comprising: first and second active regions in a semiconductor substrate; a plurality of first unit circuits in the first active region, wherein each of the plurality of first unit circuits includes a plurality of first transistors, wherein each of the plurality of first transistors includes a first gate structure; a plurality of second unit circuits in the second active region, wherein each of the plurality of second unit circuits includes a plurality of second transistors, wherein each of the plurality of second transistors includes a second gate structure; a third transistor, wherein the plurality of first unit circuits are electrically isolated from each other by the third transistor; a fourth transistor, wherein the plurality of second unit circuits are electrically isolated from each other by the fourth transistor; an insulation layer overlying the plurality of first unit circuits, the plurality of second unit circuits, the third transistor and the fourth transistor; a plurality of first plugs in the insulation layer, wherein the first plugs are electrically connected to the first gate structure of one of the plurality of first transistors, and the second gate structure of one of the plurality of second transistors; a plurality of second plugs in the insulation layer, wherein the second plugs are electrically connected to a first source region and a first drain region of the one of the plurality of first transistors, and a second source region and a second drain region of the one of the plurality of second transistors; and a wiring electrically connected to some of the plurality of first and second plugs, wherein contact areas of the plurality of second plugs are substantially the same even if misalignments of the plurality of second plugs occur, so that contact resistances of the plurality of second plugs are substantially the same, wherein the wiring includes a bit line and a bit line bar, and wherein the bit line is electrically connected to the first gate structure of the one of the plurality of first transistors and the second source region and the bit line bar is electrically connected to the second gate structure of the one of the plurality of second transistors and the first source region.