Patent ID: 7134036

Claim:
A processor, comprising: a cache capable of storing data; a control logic capable of controlling a flow of data; and at least one core coupled to the cache and the control logic, the at least one core comprising: an instruction cache capable of storing data; an instruction fetch unit capable of fetching data; a plurality of integer execution units coupled to the instruction fetch unit, each integer execution unit generating, in response to the data, an output signal at a first frequency, the first frequency being a frequency of the CPU clock signal; a plurality of latches, each latch connected to receive the output signals from the integer execution units; a merge unit, the merge unit generating a merged signal containing the output signals at a second frequency, the second frequency being a multiple of the first frequency; and a floating point graphics unit, the floating point graphics unit comprising logic for processing the merged signal at the second frequency, the processing comprising performing floating point arithmetic operations.