Patent ID: 7774727

Claim:
A layout making equipment of a semiconductor integrated circuit, comprising: a logic circuit schematic design section that designs a logic circuit diagram, based on specification data on the semiconductor integrated circuit; a layout data creation section that creates layout data having devices and connections between the devices, based on the logic circuit diagram; a logic connection verification section that extracts data about the devices and the connections between the devices from the created layout data, verifies whether or not data in the logic circuit diagram matches the data about the devices and the connections between the devices, further extracts data of potentials inputted in nodes of the devices and nodes of the connections between the devices, based on the data in the logic circuit diagram, and collates and confirms whether or not the data of the potentials matches the data in the logic circuit diagram, thereby to create collation results; a layout data verification section that verifies whether or not the created layout data violates a design rule extracted from the specification data on the semiconductor integrated circuit, based on the data about the devices and the connections between the devices and the data of the potentials inputted in the nodes of the devices and the nodes of the connections between the devices extracted in the logic connection verification section, thereby to create verification results; and a data output section that outputs the layout data created by the layout data creation section.