Patent ID: 8082138

Claim:
A computer implemented method comprising: partitioning a design into a hierarchy of partitions having a top-level partition and lower partitions, the lower partitions including a bottom-level partition, the top-level partition having top-level constraints; synthesizing the lower partitions from the bottom-level partition to create lower partition netlists based on the top-level constraints, wherein the synthesizing comprises: compiling the lower partitions separately to create register transfer level (RTL) netlists; mapping the RTL netlists to gate-level netlists associated with the lower partitions using the lower partition constraints; and optimizing the gate-level netlists based on the lower partition constraints; and optimizing a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints and compile points at lower level partitions to satisfy corresponding partition constraints, wherein optimizing the compile points includes boundary optimizations across the compile points where required, the boundary optimizations being modifications either outside or inside of a boundary of the lower partitions, without changing the boundary of the lower partitions, wherein the boundary is where ports of one or more logic blocks within one partition connect to other logic blocks outside that partition.