Patent ID: 8671329

Claim:
An electronic circuit comprising: a memory accessible by a memory read; a parity memory; a bus connected to said memory and said parity memory; an accessing circuit coupled to said memory via said bus to obtain data by a memory read; an error correcting code encoder coupled to said bus and said encoder including a write buffer operable to hold write data and having a pipelined write to said parity memory; an error correcting code decoder coupled to said memory; and a read-access circuit that is operable to cause a read to said parity memory regardless of whether the read is simultaneous with the occurrence of the pipelined write to said parity memory whereby said read-access circuit is pipeline-unaware; wherein said parity memory is dual-ported so that, on a read caused by said pipeline-unaware read-access circuit, said parity memory is operable to read out parity bits for data that is read from said memory and said encoder is concurrently operable to write other parity bits to said parity memory by said pipelined write.