Patent ID: 7871871

Claim:
A manufacturing method for a semiconductor integrated circuit device, the semiconductor integrated circuit device comprising: (x1) a semiconductor substrate having a first main surface; (x2) a first CMIS integrated circuit provided in a chip region of the first main surface of the semiconductor substrate, and having a first operating voltage; (x3) a first group of n-channel MISFETs provided in the first CMIS integrated circuit; and (x4) a first group of p-channel MISFETs provided in the first CMIS integrated circuit, the method comprising the steps of: (a) forming respective gate electrodes for the first group of n-channel MISFETs and the first group of p-channel MISFETs over the first main surface of the semiconductor substrate; (b) measuring a gate length corresponding to the gate electrode over the first main surface of the semiconductor substrate; (c) forming a first insulating film serving as an offset spacer insulating film, over the first main surface of the semiconductor substrate including an upper surface and both sides of the gate electrode; (d) applying anisotropic dry etching to the first insulating film formed so as to leave the offset spacer insulating film at both sides of the gate electrode; (e) measuring a thickness of the first insulating film corresponding to a thickness of the offset spacer insulating film, over the first main surface of the semiconductor substrate; (f) performing ion implantation for forming a p-halo region made of p-type impurities, into the first group of n-channel MISFETs according to a dose amount defined in response to the gate length and the thickness measured; and (g) performing ion implantation for forming an n-halo region made of n-type impurities into the first group of p-channel MISFETs according to the dose amount defined in response to the gate length and the thickness measured.