Patent ID: 7403045

Claim:
A comparator circuit, comprising: a differential amplifier including a current mirror load circuit and a differential transistor pair, for receiving a pair of input signals and generating a pair of output signals responsive to the pair of input signals; a latch circuit including a pair of cross-coupled inverting amplifiers, for receiving and amplifying the pair of output signals from the differential amplifier; an equalizing transistor having a control electrode, for equalizing the pair of output signals from the differential amplifier; a control signal generating circuit that receives a clock signal, generates a control signal, and inputs the control signal to the control electrode of the equalizing transistor; and a control transistor that receives the clock signal and activates the latch circuit; wherein the clock signal has a first high-level potential and the control signal has a second high-level potential lower than the first high-level potential; and the control signal generating circuit includes a first constant current source generating a first constant current, a resistive circuit generating the control signal by conducting the first constant current, thereby generating a voltage drop, the resistive circuit including a second constant current source generating a second constant current; a first transistor having a source connected to ground, and a mutually interconnected gate and drain; a second transistor having a source connected to the gate and drain of the first transistor, and having a mutually interconnected gate and drain receiving the first constant current from the first constant current source; a third transistor having a source connected to ground, a gate receiving the second constant current from the second constant current source, and a drain connected to the drain of the second transistor and to the control electrode of the equalizing transistor; and a fourth transistor having a source connected to ground, a drain connected to the gate of the third transistor, and a gate receiving the clock signal.