Patent ID: 7821919

Claim:
A data processing apparatus that has a plurality of reception interface sections which receive same data from a same data sender and processes data, received by said plurality of reception interface sections, in parallel, comprising: a frequency divider which generates a sync signal by dividing a frequency of a predetermined clock signal and sends said generated sync signal to each of said reception interface sections and said data sender, wherein each of said reception interface sections receives data, which is divided by said data sender to data of a data length shorter than one period length of said sync signal supplied from said frequency divider, from said data sender according to said sync signal, wherein each of said reception interface sections includes a communication error processing section which, upon occurrence of an error in said received data by one of said reception interface sections, stops receiving said data, sends a communication error signal to all other of said reception interface sections to stop data reception from said data sender, and requests said data sender to resend data, wherein each of said reception interface sections includes an arithmetic operation unit, an I/O unit, and a memory bridge that provides data from said arithmetic operation unit to said I/O unit of the respective reception interface section, wherein said error in said received data is detected by said memory bridge of said one of said reception interface sections, and wherein said memory bridge of said one of said reception interface sections sends the communication error signal to said other memory bridges of said other reception interface sections, and further comprising: a transaction layer that receives the communication error signal output from the communication error processing section; an internal circuit section; and a synchronization buffer that exchanges data between the transaction layer and the internal circuit section, wherein the internal circuit section acquires data held in the synchronization buffer at a timing synchronous with said sync signal and sends the acquired data to a processor external to the data processing apparatus.