Patent ID: 8583902

Claim:
A processor, comprising: a control unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); a general-purpose register file including a plurality of registers; and an instruction execution unit configured to receive instructions issued by the control unit, wherein the received instructions include a first instance of a Montgomery-multiply instruction defined within the ISA, wherein the Montgomery-multiply instruction is executable by the processor to operate on at least operands A, B, and N residing in respective portions of the general-purpose register file, wherein at least one of operands A, B, N spans at least two of the plurality of registers, and wherein a size of the respective portions is indicated by a size parameter, and wherein the instruction execution unit is configured to calculate P mod N in response to receiving the first instance of the Montgomery-multiply instruction, wherein P is the product of at least operand A, operand B, and R^−1, wherein R is a value based on the size parameter.