Patent ID: 7290159

Claim:
A synchronous input to output protocol translator system for use in chip crossing and protocol translation, comprising: a first register coupled to a first circuit for data being transferred from a first circuit to a second circuit, a second register for said second circuit for receiving data being transferred from said first circuit to said second circuit, configurable delay circuitry including providing a coupling with a plurality of connecting wires forming part of said configurable delay circuitry and capture circuits at said second register, and transfer circuits coupling a synchronizing signal from a non-delayed clock domain to a delayed clock domain, wherein said transfer circuit is clocked by a reference clock providing reference oscillator periods from a source other than said first and said second circuits for configurably delaying a second clock (osc 1 ) relative to a first clock (osc 1 ) by an absolute value, and wherein said translator system provides a constant, minimal chip-crossing time for received data over a range of reference oscillator frequencies as data is input over input data lines via said first circuit for data and each of a plurality of data lines coupled to said first register outputs its data over two or more wires for each of said input data lines, with each of two or more data bits for the data input over said input data lines being stretched over two or more of said reference oscillator periods, and wherein said two or more wires contain the same data offset by one reference oscillator period.