Patent ID: 7984319

Claim:
A type of memory bus shared system comprising: a first memory that performs data write/read in synchronization with a clock, a second memory that performs data write/read asynchronously and independent of a clock, a controller that accesses said first and second memories and controls data write/read, a first address bus that connects said controller and said first memory for address assignment, a first data bus that connects said controller and said first memory for data transfer, a first control line that connects said controller and said first memory for memory control, a second address bus that connects said controller and said second memory for address assignment, a second data bus that connects said controller and said second memory for data transfer, and a second control line that connects said controller and said second memory for memory control; while a portion or all of the address terminals of said controller are connected commonly to said first and second address buses, a portion or all of the data terminals of said controller are connected commonly to said first and second data buses; said controller performs the following operation: when access to said first memory and access to said second memory compete with each other, after a first address sent to said first address bus is fetched to said first memory, a second address is sent to said second address bus; on said first data bus, data transfer with said first memory is terminated; and, after establishment of the input of second address in said second memory, data transfer is performed with said second memory on said second data bus.