Patent ID: 7990800

Claim:
A circuit for controlling a column-command address corresponding to a specific column of a dynamic random access memory (DRAM) array, comprising: a control unit having a clock signal, setting at least one of a read latency and a write latency to determine a period number, and synchronously producing an input pointer and an output pointer according to the period number and the clock signal, wherein the output pointer is lagged behind the input pointer by the period number associated with the clock signal, and a time that the output pointer is reset is lagged behind a time that the input pointer is reset by the period number associated with the clock signal; and a first-in first-out (FIFO) register having plural sequential latch units including a specific latch unit, receiving the column-command address and the input and the output pointers, writing the column-command address into the specific latch unit when the input pointer is pointed at the specific latch unit, and reading the specific latch unit to output the column-command address by using the output pointer.