Patent ID: 7956636

Claim:
A method that generates a test bench for verifying an electrical design module in semiconductor manufacturing against an electrical reference model containing within its hierarchy a sub-circuit that matches the electrical design module, comprising: providing a description of an electrical design module that includes a plurality of ports; providing a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of ports and a plurality of internal wires; providing or creating one or more implicit defines for said reference modules that appear in said hierarchy of said electrical reference model where each said implicit define comprises a path through said hierarchy of said electrical reference model to said module so defined; providing a description file that includes one or more instance definitions, wherein each said instance definition contains a plurality of port definitions, each said port definition contains the name of a port of said electrical design module and a reference connection, said reference connection contains the name of a single implicit define being also the name of a module within said electrical reference model, hence rendering said reference connection independent of its path within said electrical reference model, and the name of said port on said module within said electrical reference model; parsing the hierarchy of said electrical design model; processing said description file; and writing the test bench containing logic to drive each input port of said electrical design module with said port of said reference module to which said output port maps and to check at each clock cycle each output port of said electrical design module against said port of said reference module to which it maps and to record in the test bench that each said plurality of ports of said electrical design module matches its corresponding port of said reference module.