Patent ID: 8276120

Claim:
An architecture template of a reconfigurable coprocessor, specialized in computing nested loops of expressions containing arithmetic and logic operations, comprising: a linear array of unspecified number and type of reconfigurable, pipelined or not, functional units, which are to be chosen according to the application domain; a linear array of unspecified number and type of embedded memories to store intermediate data and address calculations; a reconfigurable address generator block to compute complex sequences of addresses for the embedded memories; a partial and reconfigurable read crossbar, defined at pre-synthesis time, to connect system inputs, memory data output ports, and programmed constants to the functional unit inputs; a partial and reconfigurable write crossbar, defined at pre-synthesis time, to connect functional unit outputs to system outputs or memory data input ports; a register file containing control, status, and configuration registers, where the configuration registers store the configuration of the reconfigurable functional units, reconfigurable address generator block, partial and reconfigurable connection crossbars and further stores constants used in the data and address calculations.