Patent ID: 8837181

Claim:
A control circuit for a switching regulator configured to receive an input voltage via its input terminal, and to output a stepped-down output voltage via its output terminal, wherein the switching regulator comprises: a switching transistor, a detection resistor, and an inductor, sequentially arranged in series between the input terminal and the output terminal; a rectifier diode arranged between a ground terminal and a connection node that connects the switching transistor and the detection resistor; and an output capacitor arranged between the output terminal and the ground terminal, and wherein the control circuit comprises: a switching terminal to be connected to a control terminal of the switching transistor; a current detection terminal to be connected to the connection node that connects the switching transistor and the detection resistor; a ground terminal to be connected to a connection node that connects the detection resistor and the inductor; a feedback terminal via which a feedback voltage that corresponds to the output voltage is to be input; a current limiting comparator configured to generate a current limiting signal which is asserted when a detection voltage at the detection terminal is higher than a predetermined threshold voltage; an oscillator configured to generate a set signal which is asserted for every predetermined period; a mask signal generating unit configured to generate a mask signal which is asserted after a predetermined delay time elapses after the switching transistor is turned on; a reset signal generating unit configured to generate a reset signal which is asserted at a timing that is adjusted according to the feedback voltage; a pulse signal generating unit configured to generate a pulse signal which is set to a first level during a period in which the switching transistor is to be turned on, and which is set to a second level during a period in which the switching transistor is to be turned off, and to have: a function (a) in which, when the set signal is asserted in a period in which the current limiting signal is negated, the pulse signal is switched to the first level; and a function (b) in which, when the reset signal is asserted, or when the current limiting signal is asserted in a period in which the mask signal is negated, the pulse signal is switched to the second level; and a driver configured to output a switching signal that corresponds to the pulse signal, to the control terminal of the switching transistor via the switching terminal.