Patent ID: 8836556

Claim:
An Analog to Digital Converter (ADC), comprising: an input adjustment buffer stage; a sub-ADC; and a sample switch coupled between an output node of the input adjustment buffer stage and an input node of the sub-ADC; wherein when the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and when the input adjustment buffer stage switches to the second work state, the input adjustment buffer stage adjusts an input voltage signal of the input adjustment buffer stage to generate an adjusted voltage signal, wherein the input voltage signal is sampled during the first work state; when the sample switch is closed, the input adjustment buffer stage is configured to provide the adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal.