Patent ID: 7986290

Claim:
An output stage adapted to be used in a source chip, comprising: an odd output channel and an even output channel; a first output circuit for providing a first output signal at a first node according to a first input signal; a second output circuit for providing a second output signal at a second node according to a second input signal; and a plurality of first-type transistors and second-type transistors; wherein one of the first-type transistors is coupled between the first node and the odd output channel so that the first output signal is transmitted to the odd output channel via the first-type transistor without passing through any of the second-type transistors; another one of the first-type transistors is coupled between the first node and the even output channel so that the first output signal is transmitted to the even output channel via the first-type transistor without passing through any of the second-type transistors; one of the second-type transistors is coupled between the second node and the odd output channel so that the second output signal is transmitted to the odd output channel via the second-type transistor without passing through any of the first-type transistors; and another one of the second-type transistors is coupled between the second node and the even output channel so that the second output signal is transmitted to the even output channel via the second-type transistor without passing through any of the first-type transistors.