Patent ID: 7599224

Claim:
A non-volatile memory system, comprising: a set of non-volatile storage elements; managing circuitry in communication with the set of storage elements, the managing circuitry applies one or more programming pulses to the set to program one or more storage elements of the set to a particular state; after applying each programming pulse, the managing circuitry verifies programming of the one or more storage elements to an intermediate verify level corresponding to the particular state by applying a first voltage to the set of storage elements and comparing a bit line voltage of each of the one or more storage elements to a first reference potential; after applying each programming pulse, the managing circuitry verifies programming of the one or more storage elements to a final verify level corresponding to the particular state by applying a second voltage to the set of storage elements and comparing the bit line voltage of each of the one or more storage elements to a second reference potential, the second reference potential compensating for a decrease in the bit line voltage of each of the one or more storage elements resulting from the verifying programming to the intermediate verify level, the first voltage is different from the second voltage, the first reference potential is different from the second reference potential.