Patent ID: 8421507

Claim:
A calibration method for a phase-locked loop (PLL) that comprises a charge pump and a frequency divider, the method comprising: measuring a voltage associated with an output frequency of the PLL to generate a first reference voltage by providing a predetermined current amount at the charge pump and providing a predetermined frequency dividing amount at the frequency divider; measuring the voltage to generate a second reference voltage by providing a test current amount at the charge pump and providing the predetermined frequency dividing amount at the frequency divider; measuring the voltage to generate a third reference voltage by providing the predetermined current amount at the charge pump and providing a test frequency dividing amount at the frequency divider, wherein the test frequency dividing value is a predetermined value; estimating a loop gain of the PLL according to the predetermined current amount, the predetermined frequency dividing amount, the test current amount, the test frequency dividing amount, the first reference voltage, the second reference voltage, the third reference voltage, and a reference frequency; and calibrating the PLL according to the loop gain.