Patent ID: 7462909

Claim:
A semiconductor device, comprising: a first semiconductor layer of a first conduction type; a first pillar layer including first semiconductor pillar layers of said first conduction type and second semiconductor pillar layers of a second conduction type arranged on said first semiconductor layer laterally, periodically and alternately at a first period; a second pillar layer including third semiconductor pillar layers of said first conduction type and fourth semiconductor pillar layers of said second conduction type arranged on said first pillar layer laterally, periodically and alternately at a second period smaller than said first period, said third semiconductor pillar layer being arranged so as to contact with the first semiconductor pillar layer; a first main electrode electrically connected to said first semiconductor layer; a semiconductor base layer of said second conduction type selectively formed on a surface of said fourth semiconductor pillar layer; a semiconductor diffused layer of said first conduction type selectively formed on a surface of said semiconductor base layer; a second main electrode formed in contact with said semiconductor base layer and said semiconductor diffused layer; and a control electrode formed adjacent via an insulation film to said semiconductor base layer, said semiconductor diffused layer, and said third semiconductor pillar layer.