Patent ID: 7518922

Claim:
A NAND type flash memory comprising: a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape; a sense amplifier circuit provided with a plurality of sense amplifiers; a selection circuit which selects only one of two bit lines of the memory cell array based on a selection data and connects one of the two bit lines to one of the sense amplifiers; a data counter which counts the number of “1” data and the number of “0” data of a data sent to a plurality of memory cells within a simultaneous data program unit and generates a “1” data counter value and a “0” data counter value; a comparator which compares a difference between the “1” data counter value and the “0” data counter value and generates a comparison result; and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the comparison result between the “1” data counter value and the “0” data counter value when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.