Patent ID: 7074712

Claim:
A method of manufacturing a semiconductor device including multilevel interconnections, comprising the steps of: forming a first metal interconnection layer on a semiconductor substrate; forming an intermetal insulating film on the first metal interconnection layer; forming an insulative hard mask pattern having vertical sidewalls, which extend vertically with respect to the semiconductor substrate, on the intermetal insulating film, the vertical sidewalls of the hard mask pattern defining an upper hole, wherein the upper hole exposes an upper surface portion of the intermetal insulating film; forming a via hole penetrating the intermetal insulating film by etching a portion of the exposed intermetal insulating film, wherein an upper portion of the via hole has a first cross-sectional area that is greater than a second cross-sectional area of a bottom portion of the via hole; forming a contact stud composed of a first portion filling the via hole and a second portion filling the upper hole and having vertical sidewalls that extend vertically with respect to the semiconductor substrate and an upper surface that is extended parallel to the semiconductor substrate, wherein the contact stud comprises a barrier film covering inner walls of the via hole and the vertical sidewalls of the hard mask pattern, and a metal film completely filling the via hole and the upper hole; removing the hard mask pattern; removing the barrier film from the vertical sidewalls of the second portion of the contact stud after removing the hard mask pattern; and forming a second metal interconnection layer covering the metal film on the vertical sidewalls and the upper surface of the second portion of the contact stud.