Patent ID: 7257699

Claim:
A method for selectively executing deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution, comprising: issuing instructions for execution in program order during a normal-execution mode; when a long-latency operation is encountered, recording the long-latency operation in a long-latency scoreboard wherein each position in the long-latency scoreboard includes a deferred buffer start index; upon encountering an unresolved data dependency during execution of an instruction, performing a checkpointing operation and executing subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order, upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, updating the deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction; and when a long-latency operation returns, executing instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.