Patent ID: 8664048

Claim:
A method for fabricating a semiconductor device with minimized current flow differences comprising: forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, wherein the second layer is on top of the first layer; forming a plurality of mesas in the semiconductor layer stack; and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, wherein the plurality of gates is formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device by increasing the spacing between each of the gates and wherein the forming a plurality of gates includes: masking the plurality of mesas with a plurality of masks that are each wider than each mesa, wherein the masks cover and protect the plurality of mesas from dopant implantation and increase the spacing of the gates between each other by masking an area greater in width than the plurality of mesas and narrowing the area available for implantation; implanting the semiconductor layer stack; and removing the masks.