Patent ID: 7821057

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a pair of a source diffusion region and a drain diffusion region of a second conductivity type oppositely formed on a surface of the semiconductor substrate; and a plurality of stacked structures, each having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source diffusion region and the drain diffusion region, an edge of the stacked structure in the vicinity of the source region being formed away from a junction position between the source diffusion region and the channel region, wherein a highly-doped impurity region of the first conductivity type, whose impurity concentration is higher than that of the substrate, is formed in the channel region adjacent to the source diffusion region around an edge of the stacked structure, and a distance between the stacked structures at the drain diffusion region is shorter than a distance between the structures at source diffusion region.