Patent ID: 8180822

Claim:
A computer system for computing a binary operation involving a first term multiplied by a second term to obtain a product, wherein the product is conditionally added to a third term in a central processing unit, wherein the central processing unit comprises: a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result; and a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero; and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term, wherein the shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation, wherein the plurality of partial products are reduced using Booth's Encoding Algorithm, and wherein the third term to be aligned is a 33 rd partial product resulting from an application of Booth's Encoding Algorithm, and wherein the 33 rd partial product is output by multiplexer, shifted by the alignment shifter, and added to the first partial result and the second partial result.