Patent ID: 8415744

Claim:
A semiconductor structure comprising: a first complementary metal-oxide-semiconductor (CMOS) circuit located on a semiconductor-on-insulator (SOI) substrate, said first CMOS circuit including a first n-channel field effect transistor (n-FET) and a first p-channel field effect transistor (p-FET); a second CMOS circuit located on said SOI substrate, said second CMOS circuit including a second n-FET and a second p-FET; a buried insulator layer located within said SOI substrate and underlying said first n-FET, said first p-FET, said second n-FET, and said second p-FET; and a layer underlying said buried insulator layer and including: a doped base semiconductor layer having a doping of a first conductivity type, a first well having a doping of a second conductivity, embedded in said doped base semiconductor layer, and underlying said first CMOS circuit, wherein said second conductivity type is the opposite of said first conductivity type, and a second well having a doping of said second conductivity, embedded in said doped base semiconductor layer, and underlying said second CMOS circuit.