Patent ID: 8278214

Claim:
A method of forming an integrated circuit chip package comprising: forming a first interconnect layer on and touching a molded polymer block, wherein the first interconnect layer comprises a first plurality of interconnects through a first polymer layer and to the block, wherein forming the first interconnect layer comprises: laminating the first surface with a first resist; etching the first resist to form contact openings; forming a selective polymer layer in each of the contact openings; removing the first resist; laminating a first blanket layer of polymer over the block and over the selective polymer layers; forming first vias in the blanket layer of polymer and to the selective polymer layers; forming a first layer of first conductive interconnect material in the first vias and to the selective polymer layers; and forming at least one second interconnect layer on and touching the first interconnect layer, wherein the second interconnect layer comprises a second plurality of interconnects through a second polymer layer and to the first plurality of interconnects of the first interconnect layer.