Patent ID: 7202548

Claim:
An embedded capacitor with interdigitated structure for a substrate, comprising: a plurality of stacked conductive layers, the conductive layer has at least one first conductive pattern, the first conductive pattern comprises a first electrode and a second electrode, the first electrode comprises a plurality of first strips parallel to each other, a first connecting line respectively electrically connected to one end of the first strips and a first extending line, the second electrode comprises a plurality of second strips interdigitated with the first strips and a second connecting line respectively electrically connected to one end of the second strips; at least one first via connecting structure, electrically connected with the first electrode and at least one another conductive layer, wherein the first via connecting structure has at least one first via pad disposed in the conductive layer, a diameter of the first via pad being larger than a width of the first extending line; and at least one second via connecting structure, electrically connected with the second electrode and at least one another conductive layer; wherein the first extending line is extended from the first via connecting structure and is adjacent to the second electrode.