Patent ID: 7772648

Claim:
A silicon-on-insulator wafer comprising: a silicon handle wafer section having a handle wafer section resistivity greater than about 100 ohm•centimeters; an insulator layer over the handle wafer section having an insulator layer thickness greater than about 500 nanometers; and a silicon device layer over the insulator layer comprising: a first isolation area implanted into the silicon device layer over and approximately adjacent to the insulator layer, a device body of a first field effect transistor (FET) over the first isolation area; an FET source of the first FET substantially over the first FET device body; an FET drain of the first FET substantially over the first FET device body; and at least one isolation sidewall implanted into the silicon device layer down to the first isolation area to isolate the first FET, wherein the silicon device layer has a silicon device layer thickness greater than about 400 nanometers.