Patent ID: 8487677

Claim:
A phase locked loop, comprising: a voltage controlled oscillator generating an output frequency signal based on a control voltage, a feedback circuit which converts said output frequency signal to a feedback frequency signal, and a phase detector which generates at least one adjust signal based on comparing frequencies of said feedback frequency signal and a reference frequency signal; a first charge pump receiving said at least one adjust signal, having at least one current control input, and having an output coupled to an intermediate node; a second charge pump receiving said at least one adjust signal, having at least one current control input, and having an output coupled to a control node developing said control voltage; a capacitor coupled between said intermediate node and a reference node; a voltage buffer having a first input coupled to said intermediate node, having at least one bias input, and having a second input and an output coupled together and to said control node; and a bias generator which converts said control voltage to a converter bias current based on said control voltage, and which has at least one bias output which is based on said converter bias current and which is provided to said current control inputs of said first and second charge pumps and to said at least one bias input of said voltage buffer.