Patent ID: 8871636

Claim:
A method of forming a metal interconnect structure comprising: forming an underlying metal line embedded in an underlying dielectric layer on a substrate; forming a dielectric cap layer directly on said underlying metal line and said underlying dielectric layer; forming a fluorosilicate glass (FSG) layer directly on said dielectric cap layer, wherein said FSG layer has a first fluorine atomic concentration; patterning a line trough and a via cavity within said FSG layer; forming a single continuous fluorine depleted silicate glass layer, having an upper horizontal portion overlying a topmost horizontal surface of said FSG layer, and having a second fluorine atomic concentration on said fluorosilicate glass (FSG) layer, wherein said second fluorine atomic concentration is about 10% of, or less than 10% of, said first fluorine atomic concentration; applying a photoresist over said single continuous fluorine depleted silicate glass layer, wherein a portion of said single continuous fluorine depleted silicate glass layer within said via cavity is exposed; removing said exposed portion of said fluorine depleted silicate glass layer and a portion of said dielectric cap layer underneath said exposed portion of said fluorine depleted silicate glass layer employing said photoresist as an etch mask, wherein a top surface of said underlying metal line is exposed; and forming a metal line and a metal via directly on said fluorine depleted silicate glass layer, wherein said metal line and said metal via are spaced from said FSG layer by said fluorine depleted silicate glass layer, and said metal via is in direct contact with said underlying metal line.