Patent ID: 8054279

Claim:
A display device comprising a pixel and a driver circuit, the driver circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein one of a source and a drain of the first transistor is directly connected to a fourth wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring; wherein one of a source and a drain of the second transistor is electrically connected to a seventh wiring, the other of the source and the drain of the second transistor is electrically connected to the third wiring, and a gate of the second transistor is electrically connected to a fifth wiring; wherein one of a source and a drain of the third transistor is electrically connected to a sixth wiring, the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor, and a gate of the third transistor is directly connected to the fourth wiring; wherein one of a source and a drain of the fourth transistor is electrically connected to the seventh wiring, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor, and a gate of the fourth transistor is electrically connected to the fifth wiring; wherein one of a source and a drain of the fifth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring; wherein one of a source and a drain of the sixth transistor is electrically connected to the seventh wiring, and the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor; wherein one of a source and a drain of the seventh transistor is electrically connected to the seventh wiring, the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring; and wherein one of a source and a drain of the eighth transistor is electrically connected to the seventh wiring, the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor, and a gate of the eighth transistor is electrically connected to the gate of the first transistor.