Patent ID: 8824185

Claim:
A NOR-type ROM with hierarchical-BL structure, dynamic segmentation shielding, and source programming, the NOR-type ROM comprising: a plurality of bitcells, each of which is an N-typed metal-oxide-semiconductor (NMOS) and an NOR-type ROM bitcell with source programming and forms a plurality of cell arrays, each of which is formed of a plurality of bitcells arranged in interleaving rows and columns; a plurality of word lines (WLs) electrically connected to gates of the bitcells in a way that one WL corresponds to the bitcell in one row; a plurality of local bit lines (LBLs) electrically connected with drains of the bitcells in a way that one LBL corresponds to the bitcell in one column; a plurality of odd/even selection circuits electrically connected with the LBLs to which the bitcells in one of the cell arrays correspond, in a way that one odd/even selection circuit corresponds to one of the cell arrays, for selecting the bitcells in odd or even columns; a plurality of global bit lines (GBLs) electrically connected with the odd/even selection circuits to which the bitcells in columns correspond in a way that one GBL corresponds to one bitcell in column in at least one of the cell arrays; and a plurality of odd/even precharge circuits electrically connected with the GBLs, in a way that one odd/even precharge circuit corresponds to at least one of the cell arrays, for passing through the odd/even selection circuits to precharge the bitcells in odd or even columns with electricity; wherein the sources of the bitcells are selectively grounded or floating according to a code-pattern.