Patent ID: 7087500

Claim:
A method of forming an array of memory cells, the method comprising: forming a masking layer over a top surface of a semiconductor body; patterning the masking layer to expose portions of the top surface that will serve as isolation regions for separating a plurality of remaining web portions of said semiconductor body, each of said web portions for forming the source regions, channel regions, and drain regions of transistors such that the longitudinal direction of the channel region extending between the source and drain runs parallel to a first direction and the channel width is transverse to said first direction; etching the semiconductor body to form trenches at the exposed portions of the top surface; narrowing remaining portions of the masking layer; thermally growing an oxide layer over exposed portions of the semiconductor body to a selected thickness, said steps of narrowing and thermally growing operating to form a top side on said web portions extending between pairs of trenches, said top side defining the channel width, and said top side including a bulge or curved portion; filling the trenches with an insulating material to form the isolation regions; depositing a storage layer sequence over the semiconductor body between the isolation regions; depositing a conductive layer over the storage layer sequence; and patterning the storage layer sequence and the conductive layer.