Patent ID: 8621309

Claim:
A processor comprising: a secondary cache memory configured to store data; an instruction execution unit including a primary cache memory configured to store data read out from the secondary cache memory based on a load request and is configured to execute processes based on the data stored in the primary cache memory, wherein the primary cache memory includes: a data memory configured to store data read out from the secondary cache memory based on the load request; a tag memory configured to store address information for checking cache hit/miss of the data read out from the data memory; an error detection unit configured to detect an occurrence of error in data read out from the data memory; a rerun request generation unit configured to generate a rerun request when the error detection unit detects the occurrence of error in the data read out from the data memory by the load request, wherein the rerun request causes a reissuing of the load request for the data in which the error is detected; and a permission information generation unit configured to output to the instruction execution unit, a usage permission information for the data stored in the secondary cache memory by checking cache hit/miss of the data read out from the data memory based on the address information stored in the tag memory, wherein the generation of the rerun request by the rerun request generation unit and the output of the usage permission information by the permission information generation unit are executed at the same cycle in which the error detection unit detects the occurrence of the error, and wherein the instruction execution unit is configured to retransmit a load request to the primary cache memory when receiving the rerun request.