Patent ID: 8909979

Claim:
A computer system for implementing fault tolerance, comprising: a first CPU; a second CPU; a first CPU interconnect device that comprises a first quick path interconnect (QPI) interface and a first serial deserial (SerDes) interface that are connected to each other; and a second CPU interconnect device that comprises a second QPI interface and a second SerDes interface that are connected to each other; wherein: the first CPU and the second CPU implement interconnection through a first connection link, a second connection link and a third connection link; the first connection link is established between a QPI interface of the first CPU and the first QPI interface to transmit data sent or received by the first CPU; the third connection link is established between a QPI interface of the second CPU and the second QPI interface to transmit data sent or received by the second CPU; the second connection link is established between the first SerDes interface and the second SerDes interface to transmit data between the first CPU and the second CPU; a fourth data channel is additionally established between the first SerDes interface and the second SerDes interface, the fourth data channel is configured to transmit a link state and a link control signal; wherein the computer system is configured to monitor the link state of any one of the first connection link, the second connection link and the third connection link, transmit the link state through the fourth data channel between the first CPU interconnect device and the second CPU interconnect device, recover any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.