Patent ID: 7133968

Claim:
A single-issue in-order pipelined microprocessor for accessing data stored in a memory coupled to the microprocessor by a bus, the microprocessor comprising: a plurality of buffers, configured to receive data from the memory on the bus; a data cache, coupled to said plurality of buffers; control logic, coupled to said data cache and said plurality of buffers, configured to determine whether one or more instructions following a stalled instruction in the microprocessor pipeline specify data missing in the data cache; and a plurality of descriptors, coupled to said control logic, for specifying memory-mapped I/O regions of a memory address space of the microprocessor; wherein said control logic is further configured to allocate one or more of said plurality of buffers to receive said missing data and to issue one or more requests on the bus for said missing data during resolution of said stalled instruction; wherein said control logic is further configured to issue said one or more requests on the bus for said missing data only if said stalled instruction does not access a memory-mapped I/O region of said memory address space.