Patent ID: 7405603

Claim:
A DLL circuit comprising: a first buffer that receives a power-down mode signal and a first external clock signal; a second buffer that receives the power-down mode signal and an inverted signal of the first clock signal; a first delay line that receives an output signal of the first buffer and which delays the output signal of the first buffer for a predetermined period of time; a second delay line that receives an output signal of the second buffer and which delays the output signal of the second buffer for a predetermined period of time; an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit that delays an output of the second delay line; a phase comparator that compares phase differences between the output signal of the second buffer and an output signal of the replica delay unit; a delay line controller that controls delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator; a controller that controls an enable/disable state of the phase comparator based on a state of the power-down mode signal, wherein the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.