Patent ID: 8106808

Claim:
A successive time-to-digital converter (STDC) comprising: a frequency detector having an input to accept a reference clock, input to accept a frequency synthesizer clock from a frequency synthesizer, and an output to supply a count of the number of frequency synthesizer clock cycles per reference clock cycle; a first TDC having an input to accept the reference clock, and input to accept the frequency synthesizer clock, the first TDC measuring a first difference between an edge of a reference clock period and a corresponding edge of a frequency synthesizer clock period, providing the first difference measurement at an output, and providing the frequency synthesizer clock delayed a full cycle; a phase interpolator having an input to accept the reference clock, an input to accept the frequency synthesizer clock, and an input to accept the first difference measurement, the phase interpolator supplying the reference clock delayed to create a second difference between the edge of the delayed reference clock period and the corresponding edge of the frequency synthesizer clock period, where the second difference is less than the first difference; a second TDC having an input to accept the delayed reference clock period, and input to accept the delayed frequency synthesizer clock, the second TDC measuring a third difference between the edge of the delayed reference clock period and the corresponding edge of the delayed frequency synthesizer clock period, and providing the third difference measurement as a time duration; and, a digital signal processor (DSP) having an input to accept the third difference measurement, an input to accept the first difference measurement, an input to accept the count from the frequency detector, and an output to supply a digital error signal to the frequency synthesizer.