Patent ID: 8281195

Claim:
An integrated circuit that supports scan chain based testing of combinational logic within the integrated circuit, the integrated circuit comprising: a plurality of combinational logic circuits; at least one input latch array configured to control a passage of an input data value to one of the combinational logic circuits; a plurality of scan latches, each scan latch comprising: a passthrough switch that controls a passage of an output data value received from one of the combinational logic circuits and that opens and closes based on a value of a slave phase clock signal; a scanning control circuit that passes one of a scan test input data value and a scan test output data value based on a value of a scan clock signal; and an output storage circuit that receives one of a data value from the passthrough switch and a data value from the scanning control circuit, the output storage circuit including a first transistor configured to open and close based on a value of the scan clock signal and a second transistor configured to open and close based on an inverted value of the slave phase clock signal, and a connection between the output storage circuit and a low signal source is open when one of the first transistor and the second transistor is open.