Patent ID: 7962320

Claim:
A method of creating a power pin model of a semiconductor integrated circuit, said model comprising a combination of cells that are divided to have a cell size in accordance with a size of the semiconductor integrated circuit, each cell comprising one layer of a power supply circuit network including wires with capacitive components and ground, an internal active section existing between said power supply circuit network and ground and performing an operation in said semiconductor integrated circuit, and an internal capacitive section existing between said power supply circuit network and ground and being inoperative in said semiconductor integrated circuit, said method comprising: calculating λmin 1 in accordance with the following equation: λ min ⁢ ⁢ 1 = η n * λ min ⁢ ⁢ 0 ( Cline ⁢ ⁢ 1 + Cin ⁢ ⁢ 1 ) / Cline ⁢ ⁢ 1 where ηn is the value of a wavelength shortening derived from a dielectric material contained in the wires in a power supply circuit network layer, Cline 1 a total value of wiring capacitances appearing between the wires in the power supply circuit network layer and ground, Cinl is a total value of internal capacitances added between the wires and ground, and λmin 0 is the wavelength in vacuum corresponding to an upper limit frequency Fmax, determining length lcell 1 of one side of each cell which takes a value that is electrically sufficiently shorter than the value of λminn 1 ; creating, from power supply circuit network wiring structure information of the semiconductor integrated circuit and the value of lcell 1 , a model of the power supply circuit network of each cell, including wire models existing in a reticular pattern, a terminal at a center of each cell connected to the internal active section and to the internal capacitance section, connection terminals on outer sides for coupling with adjacent cells, and inserting a model of the internal active section and a model of the internal capacitance section into each cell at a proportion based on element arrangement information of the semiconductor integrated circuit, an entire power pin model of the semiconductor integrated circuit, and the value of lcell 1 , for connection with the model of the power supply circuit network; coupling said model of the power supply circuit network, said model of the internal active section, and said model of the internal capacitance section through the respective connection terminals with the adjacent cells to derive a power pin model of an overall semiconductor integrated circuit having only one power supply circuit network layer; and outputting a derived power pin model.