Patent ID: 8053824

Claim:
An integrated circuit device structure comprising: a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom, the first metal line being significantly thicker along a direction of extension of the first set of metal fingers than each of the first set of metal fingers along a direction perpendicular to the extension thereof; a second metal line implemented on the metallization layer, the second metal line being electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers being capacitively coupled, and the second metal line also being significantly thicker along a direction of extension of the second set of metal fingers than each of the second set of metal fingers along a direction perpendicular to the extension thereof; and a via array provided respectively on the first metal line and the second metal line to enable coupling of the metallization layer to another metallization layer in a direction perpendicular to a plane including the first metal line, wherein the via array is only at one end portion of the first metal line and the second metal line, respectively, the first set of metal fingers, the second metal line and the second set of metal fingers.