Patent ID: 7356650

Claim:
A data processing system, comprising: at least one processor that issues memory requests responsive to instruction execution, the memory requests including a first memory request; a first-level cache coupled to the at least one processor, wherein the first-level cache bypasses storing data for the first memory request responsive to a do-not-cache attribute associated with the first memory request; a second-level cache coupled to the first-level cache, wherein the second-level cache bypasses updating of least-recently-used indicators of the second-level cache responsive to the do-not-cache attribute associated with the first memory request and stores the data for the first memory request, wherein the second-level cache stores the data for the first memory request responsive to absence of a do-not-cache attribute associated with the first memory request, stores the data for the first memory request responsive to a mode for the second-level cache having a first value and independent of presence or absence of the do-not-cache attribute, and bypasses storing the data for the first memory request responsive to the do-not-cache attribute associated with the memory request and the mode for the second-level cache having a second value; and a memory arrangement coupled to the second-level cache.