Patent ID: 8658518

Claim:
A method of fabricating a nanowire field effect transistor (FET) device, comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer comprising a SOI layer over a buried oxide (BOX); etching nanowires and pads in the SOI layer, wherein the pads are attached at opposite ends of the nanowires in a ladder-like configuration, and wherein the nanowires etched in the SOI layer have a pitch comprising at least a first pitch, and at least a second pitch that is different from the first pitch; suspending the nanowires over the BOX; forming an interfacial oxide surrounding each of the nanowires; depositing a conformal gate dielectric on the interfacial oxide, surrounding each of the nanowires; depositing a conformal first gate material on the conformal gate dielectric, surrounding each of the nanowires; depositing a work function setting material on the conformal first gate material, at least partially surrounding the nanowires; depositing a second gate material on the work function setting material, surrounding each of the nanowires to form gate stacks over the nanowires, such that at least a first one of the gate stacks corresponding to at least one first nanowire FET is formed over the nanowires having the first pitch and at least a second one of the gate stacks corresponding to at least one second nanowire FET is formed over the nanowires having the second pitch, wherein a volume of the conformal first gate material and a volume of the work function setting material in the gate stacks are proportional to the pitch of the nanowires, wherein the work function setting material is configured to change threshold voltages of the device, and wherein, by way of the volume of the work function setting material in the gate stacks being proportional to the pitch of the nanowires, the first nanowire FET comprising the first one of the gate stacks formed over the nanowires having the first pitch has a different threshold voltage from the second nanowire FET comprising the second one of the gate stacks formed over the nanowires having the second pitch.