Patent ID: 8406049

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array configured by a plurality of memory strings each including memory cells connected in series, the memory cells being capable of storing data by retaining a first threshold voltage distribution having a negative upper limit value and representing an erased state after data is erased, and a second threshold voltage distribution having a lower limit value higher than the upper limit value of the first threshold voltage distribution and representing a written state after data is written; a plurality of word lines each provided to be connected commonly to the memory cells in the plurality of memory strings; a plurality of bit lines connected to first ends of the memory strings respectively; a source line connected to second ends of the memory strings; and a control circuit configured to control the memory cells through the word lines, the bit lines, and the source line, the control circuit being configured to, in executing a writing operation for giving the second threshold voltage distribution to a plurality of memory cells formed along one word line, perform a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution, while executing a voltage applying operation in memory cells to be maintained in the erased state, thereby moving the first threshold voltage distribution in a positive direction to obtain a third threshold voltage distribution representing the erased state, wherein the control circuit is configured to execute, in memory cells to be given the second threshold voltage distribution, a foggy writing process for moving a threshold voltage distribution in a positive direction using a first verify voltage lower than the lower limit value of the second threshold voltage distribution, the control circuit is configured to execute, in memory cells to be given the second threshold voltage distribution, a fine writing process for moving a threshold voltage distribution after the foggy writing process further in a positive direction using a second verify voltage equal to the lower limit value of the second threshold voltage distribution, in the foggy writing process, the control circuit moves a threshold voltage distribution of memory cells to be maintained in the erased state in a positive direction using a third verify voltage lower than a lower limit value of the third threshold voltage distribution, and in the fine writing process, the control circuit moves a threshold voltage distribution of the memory cells to be maintained in the erased state after the foggy writing process further in a positive direction by using a fourth verify voltage equal to the lower limit value of the third threshold voltage distribution.