Patent ID: 7460600

Claim:
An MPEG video decoding system, comprising: a buffer configured to store an MPEG-formatted video signal or a DV-formatted video signal and to output a corresponding buffer output signal; a VLD/IQ (Variable Length Decoder/Inverse Quantized) device configured to perform a variable length decoding and an inverse quantization to the buffer output signal so as to generate a VLD/IQ output signal; an IDCT (Inverse Discrete Cosine Transform) device configured to generate an IDCT transformed signal by performing an 8×8 IDCT transform on the VLD/IQ output signal if the VLD/IQ output signal is the MPEG-formatted video signal, and performing an 8×8 IDCT or a 4×8 IDCT transform on VLD/IQ output signal if VLD/IQ output signal is the DV-formatted video signal; an adder; and a motion compensator, wherein if the IDCT transformed signal is an MPEG-formatted I-picture or a DV format signal, the adder is configured to bypass and store the IDCT transformed signal into an external memory, and if the IDCT transformed signal is an MPEG-formatted P-picture or an MPEG-formatted B-picture the motion compensator is configured to generate a motion compensated signal by performing motion compensation on a current frame based on motion information and a previous frame stored in the external memory, and output the motion compensated signal to the adder, and the adder is configured to add the IDCT transformed signal and the motion compensated signal, and store the added signal into the external memory.