Patent ID: 6931514

Claim:
A detector for detecting at least one kind of address dependence between a first instruction and a second subsequent instruction executed by at least a processor, said detector comprising: means for, if said at least one kind of address dependence is present in fact, detecting said presence in fact of said at least one kind of address dependence, and if said at least one kind of address dependence is not present in fact, detecting a pseudo presence of said at least one kind of address dependence; and means for causing a recovery process to be executed by said processor when said processor executes said second instruction and either said means for detecting detects said presence in fact of said at least one kind of address dependence or said means for detecting detects said pseudo presence of said at least one kind of address dependence; wherein said first instruction comprises a memory access instruction for access to a memory; wherein said means for detecting comprises: an execution history storing unit including a plurality of entries which stores an instruction execution information of whether said memory access instruction has been executed; and an address converter for converting an address of said memory access instruction into an entry number of said plurality of entries of said execution history storing unit, so that said execution history storing unit stores said instruction execution information into an entry of said plurality of entries that is designated by said entry number; and wherein said address converter is adopted to convert same address of different memory access instructions into entry numbers that are the same and said address converter may convert different addresses of different memory access instructions into entry numbers that are the same, whereby if said at least one kind of address dependence is not present in fact, then said means for detecting may detect a pseudo presence of said at least one kind of address dependence.