Patent ID: 7821313

Claim:
A Delay Locked Loop (DLL) circuit comprising: an input circuit configured to receive an input signal, and to generate a synchronization reference signal on the basis of the input signal; a first delay module configured to delay the synchronization reference signal in order to generate a plurality of delayed versions of the synchronization reference signal and to select one of the delayed versions of the synchronization reference signal as an output; a timing offset circuit configured to adjust a synchronization position of the selected delayed version of the synchronization reference signal in order to generate a signal to be synchronized; a phase comparison circuit configured to compare the phase of the synchronization reference signal with the phase of a selected one of a plurality of delayed versions of the signal to be synchronized; a first controller configured to control the selection of one of the plurality of delayed versions of the synchronization reference signal as the output signal of the first delay module on the basis of a comparison result of the phase comparison circuit; a second delay module connected to the timing offset circuit and configured to delay the signal to be synchronized in order to generate the plurality of delayed versions of the signal to be synchronized; a configuration information memory configured to store configuration information indicative of an output signal of the second delay module to be selected when the DLL is in an unlocked state; and a second controller connected to the configuration information memory and configured to select one of the plurality of delayed versions of the signal to be synchronized as the output signal of the second delay module based on the configuration information stored in the configuration information memory in the case where the comparison result of the phase comparison circuit is within a predetermined range.