Patent ID: 7440469

Claim:
In an integrated circuit multichannel packet transfer device, an apparatus for transferring a plurality of data packets, comprising: a first interface circuit for receiving packet data on a first channel; a memory; a packet manager circuit coupled between the first interface circuit and the memory to receive data on the first channel from the first interface circuit, wherein the packet manager circuit is configured to write at least a first data packet fragment to the memory under control of a first descriptor, and is configured to write additional data packet fragments to the memory under control of corresponding additional descriptors; a register for storing a minimum descriptor count; a timer for generating a first time-out signal at a predetermined time after the first descriptor is ready for transfer; and a controller for controlling descriptor write back operations to memory in either read-modify-write mode or write-invalidate mode, wherein the controller writes a plurality of descriptors together to memory in a single write-invalidate operation only if the plurality of descriptors that are ready for transfer meets or exceeds the minimum descriptor count and if the plurality of descriptors that are ready for transfer meets or exceeds the minimum descriptor count before the first time-out signal is generated.