Patent ID: 7761720

Claim:
A processor comprising: interrupt handling logic coupled to a first set of signal lines to receive an interrupt request, said first set of signal lines coupled to one or more devices that can generate interrupt requests; evaluation logic coupled to said interrupt handling logic, wherein when said interrupt handling logic receives said interrupt requests, said evaluation logic is to evaluate power state information and task priority information for a first processing component and a second processing component to determine which of said first and second processing components to service said interrupt requests; and selection logic coupled to said evaluation logic to select either said first processing component or said second processing component to be a destination processing component to service said interrupt requests based on said power state information and said task priority information, wherein said task priority information includes a task priority value being assigned to individual processing components based on power state of each processing component, the task priority value having a lower task priority value or a higher task priority value, wherein said destination processing component comprises a processing component with the lower task priority value being more preferably selected to be said destination processing component to service said interrupt request than another processing component with the higher task priority value.