Patent ID: 7203886

Claim:
A method of operating a data processing system having a processor and an integrated circuit memory device, each coupled to a bus, said method comprising: generating a read request at the processor; transmitting the read request from the processor to the memory device via the bus; reading multiple ferroelectric cells disposed in separate memory blocks of the memory device to obtain first data in response to the read request; processing the first data using an error correction algorithm that is operative with a codeblock, or codeword, comprising a plurality of symbols, the algorithm being implemented with an error correction device, the processing comprising: determining corrupt bits of the first data; correcting corrupt bits of the first data if determined by the determining, to provide second data; writing the multiple cells with the second data using the second data in symbol data groups of a codeblock of the error correction algorithm; distributing the symbols in interleaved format across an address space of a plurality of isolated, fault tolerance architected memory cells or arrays of memory cells in a plurality of the memory blocks; and transmitting at a least a portion of the second data on the bus to the processor to fulfill the read request, wherein the error correction algorithm is operative with a codeblock of length n and comprises an error correction capability for correcting up to t errors, the memory cells define at least Z memory blocks of the plurality, wherein n/Z is less than t, and the writing distributes the symbols in the interleaved format across the Z memory block.