Patent ID: 8258833

Claim:
A phase locked loop (PLL) circuit for receiving an input clock signal and generating an output clock signal according to a plurality of internal clock signals with phase shifting which are generated according to the input clock signal, the PLL circuit comprising: a selector for receiving the internal clock signals and outputting a selection clock signal, wherein the selector selects one of the internal clock signals to serve as the selection clock signal according to an enable signal; a first dividing unit for receiving the selection clock signal and performing dividing operations to the selection clock signal to generate the output clock signal and a first feedback clock signal; a converter for receiving the feedback clock signal and a reference clock signal and detecting phase difference between the first feedback clock signal and the reference clock signal to generate a detection signal; a first low pass filter for receiving the detection signal and performing a filtering operation to the detection signal to generate a filtering signal; and a modulator for receiving and modulating the filtering signal to generate the enable signal.