Patent ID: 7838991

Claim:
An integrated circuit wafer comprising a multiplicity of dice, the dice each including a multiplicity of integrated circuits and a plurality of contact pads that are exposed through contact pad openings formed in a top wafer fabrication passivation layer that constitutes an uppermost inorganic passivation layer formed on the wafer, the wafer further including: a patterned copper layer that extends over the top surface of the top wafer fabrication passivation layer, wherein the patterned copper layer is electrically coupled to at least some of the contact pads through the contact pad openings; a first titanium metallization layer that overlies at least portions of the patterned copper layer; a first aluminum metallization layer that overlies at least portions of the first titanium metallization layer; an electrically insulating organic protective layer that overlies the first aluminum metallization layer and the top wafer fabrication passivation layer, there being a plurality of contact openings in the protective layer; and a plurality of underbump metallization stacks, each underbump metallization stack being electrically connected to the first aluminum metallization layer through an associated contact opening in the protective layer, wherein peripheral portions of the underbump metallization stacks extend over at least some adjacent portions of the protective layer.