Patent ID: 8871579

Claim:
A manufacturing method for a semiconductor transistor that includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and a semiconductor layer, the manufacturing method comprising: forming a resist layer containing resist material on a base layer that includes a substrate; patterning areas of the resist layer and thereby forming a plurality of apertures; forming a metal layer containing metallic material so as to cover the resist layer and to fill the apertures formed in the resist layer, the metallic material being for forming a source electrode and a drain electrode; removing a metal oxide layer by performing cleaning with use of a liquid for cleaning, the metal oxide layer being formed by oxidation of a top surface of the metal layer; forming, after the removing of the metal oxide layer, the source electrode and the drain electrode by removing the resist layer by use of a liquid for dissolution different from the liquid for cleaning, the source electrode and the drain electrode constituted of the metallic material having been disposed in the apertures; and forming a semiconductor layer so as to cover the source electrode and the drain electrode.