Patent ID: 8669621

Claim:
A semiconductor device comprising: a semiconductor substrate having a main surface; a first insulated gate field effect transistor including a pair of first source/drain regions formed on said main surface, and a first gate electrode formed on said main surface between said pair of first source/drain regions; a second insulated gate field effect transistor including a pair of second source/drain regions formed on said main surface, and a second gate electrode formed on said main surface between said pair of second source/drain regions; a bipolar transistor including an emitter region formed on said main surface, a base region formed on said main surface to form a pn junction with said emitter region, and a collector region formed on said main surface opposite to said emitter region relative to said base region to form a pn junction with said base region; a first element isolation structure formed on said main surface above the pn junction formed between said emitter region and said base region; a second element isolation structure formed on said main surface above the pn junction formed between said base region and said collector region; and a third element isolation structure formed on said main surface opposite to said second element isolation structure relative to said collector region, wherein said pair of first source/drain regions, said emitter region, said base region and said collector region each have a silicided surface, and said pair of second source/drain regions and said second gate electrode each have a non-silicided surface, and said semiconductor device further comprises a first dummy gate electrode which is formed on at least one of said first element isolation structure, said second element isolation structure and said third element isolation structure, and which is not used as a circuit.