Patent ID: 8709893

Claim:
A method for making a low-Rdson vertical power MOSFET device in an epitaxial layer of a first conductivity type supported on a substrate with a bottom of the epitaxial layer configured as a bottom electrode of the vertical power MOSFET device comprises the following steps: depositing an epitaxial layer on top of a substrate; etching a first type trench and a second type trench into the epitaxial layer on top of the substrate; depositing a polysilicon layer within the first type trench to form a polysilicon gate; depositing a polysilicon layer within the second type trench to form a polysilicon gate runner; depositing a bottom passivation layer covering a bottom surface of the substrate; forming a plurality of openings in the bottom passivation layer; etching the bottom of the substrate through the openings on the bottom passivation layer forming a plurality of grooves, each being tapered with slant side walls, penetrating the bottom of the substrate and exposing portions of the bottom surface of the epitaxial layer; implanting dopant of the first conductivity type from the bottom of the substrate forming a plurality of heavily doped regions at the exposed portions of the bottom of the epitaxial layer corresponding to the grooves; and depositing a metal layer covering the bottom surface of the substrate and sidewalls of the grooves and the exposed portions of the bottom surface of the epitaxial layer wherein, the metal layer forming a bottom metal electrode of the vertical power MOSFET.