Patent ID: 7105388

Claim:
A method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated circuitry comprising: forming a transistor device supported by a silicon-containing layer, the transistor device comprising a gate elevationally above the silicon-containing layer and a pair of source/drain regions extending into the silicon-containing layer; the silicon-containing layer being formed to be elevationally above and laterally surrounded by electrically insulative material; forming a first conductive material laterally adjacent the silicon-containing layer and spaced from the silicon-containing layer by the electrically insulative material, at least a portion of the first conductive material being elevationally below the source/drain region; and forming a second conductive material electrically connecting the first conducive material to one of the source/drain regions of the pair of source/drain regions, the second conductive material being formed to be elevationally above both the first conductive material and said one of the source/drain regions, and being formed in physical contact with both the first conductive material and said one of the source/drain regions.