Patent ID: 8704581

Claim:
A switched capacitor circuit comprising: a pair of differential first circuit inputs configured to receive a first signal, the pair of differential first circuit inputs comprising a first positive circuit input and a first negative circuit input; a pair of differential second circuit inputs configured to receive a second signal, the pair of differential second circuit inputs comprising a second positive circuit input and a second negative circuit input; an operational amplifier (OA) comprising a pair of differential OA inputs and a pair of differential OA outputs, the pair of differential OA inputs comprising a positive OA input and a negative OA input, the pair of differential OA outputs comprising a positive OA output and a negative OA output; a first integration capacitor coupled between the positive OA input and the negative OA output; a second integration capacitor coupled between the negative OA input and the positive OA output; a first integration branch coupled between the first positive circuit input and the positive OA input, wherein the first integration branch comprises a first integration capacitor comprising a first terminal of the first integration capacitor and a second terminal of the first integration capacitor, a first switch coupled between the first positive circuit input and the first terminal of the first integration capacitor, a second switch coupled between the first terminal of the first integration capacitor and a first common mode voltage, a third switch coupled between the second terminal of the first integration capacitor and a second common mode voltage, and a fourth switch coupled between the second terminal of the first integration capacitor and the positive OA input; a second integration branch coupled between the first negative circuit input and the negative OA input; a first summing branch coupled between the first negative circuit input and the positive OA input; a second summing branch coupled between the first positive circuit input and the negative OA input; a third summing branch coupled between the second negative circuit input and the positive OA input; and a fourth summing branch coupled between the second positive circuit input and the negative OA input; wherein the first integration branch, the second integration branch, the first summing branch, the second summing branch, the third summing branch, and the fourth summing branch are configured using switched capacitor technique so that the pair of differential OA outputs provides an output signal that is a sum of (1) a product of the first signal, (2) a product of the second signal, and (3) a product of an integral of the first signal.