Patent ID: 7020768

Claim:
Apparatus for processing data and operable to access a memory, comprising: a processing circuit having an operating system associated therewith and being operable to execute sequences of processing instructions, the processing circuit having multiple states of operation, the manner of access to an address space of said memory being dependent upon a state of operation, each state of operation having a non-zero number of said sequences associated therewith, with each state of operation being assigned a context identifier by the operating system to identify the state of operation; and logic for facilitating debugging of said sequences of processing instructions executed by the processing circuit including: control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging; and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit, the triggering logic comprising at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier.