Patent ID: 8848458

Claim:
A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received, the circuit comprising: a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input; a first control input driven by the clock pulse; a second control input driven by the flip-flop; a third control input, where the second and third control inputs are maintained high prior to receipt of the clock pulse, and become complementary upon receipt of the clock pulse; and selection logic configured to receive the first and second data inputs and the first, second and third control inputs, the selection logic configured to drive the output of the memory circuit to the level of the first data input or the level of the second data input depending on the first, second and third control inputs, and where the output of the memory circuit is driven to the level of the first data input only when both the first and second control inputs are high.