Patent ID: 7319603

Claim:
A semiconductor storage device comprising: a plurality of bit-line pairs extending in a first direction; a first word line extending in a second direction that intersects the first direction; a first plurality of memory cells provided at intersection points formed by the plurality of bit-line pairs and the first word line; a plurality of P well areas extending in the first direction; a plurality of N well areas extending in the first direction; a plurality of P areas for well tap that are P type, and that have impurity concentration higher than that of the P well areas, said plurality of P areas for well tap being used to supply well potential to the plurality of P well areas; and a plurality of N areas for well tap that are N type, and that have impurity concentration higher than that of the N well areas, said plurality of N areas for well tap being used to supply well potential to the plurality of N well areas; wherein: each of the first plurality of memory cells includes first and second PMOS transistors, and first, second, third, and fourth NMOS transistors, said first and second NMOS transistors are formed in one of the plurality of P well areas, said third and fourth NMOS transistors are formed in another one of the plurality of P well areas, said first and second PMOS transistors are formed in one of the plurality of N well areas, said one of the plurality of N well areas is located between said one of the plurality of P well areas and said another one of plurality of P well areas, among the first plurality of memory cells, different addresses are assigned to first memory cells that are adjacent to each other in the second direction, and a P well supply line for supplying power to the plurality of P areas for well tap and a N well tap supply line for supplying power to the plurality of N areas for well tap extend in the second direction.