Patent ID: 7577025

Claim:
A semiconductor memory device, comprising: a first memory cell configured to store a first bit of data and comprising a floating body, a gate connected to a word line, a first electrode connected to a bit line, and a second electrode connected to a first source line; a second memory cell configured to store a second bit of data having an inverted logic state relative to the first bit of data and comprising a floating body, a gate connected to the word line, a first electrode connected to an inverted bit line, and a second electrode connected to a second source; a first transmission gate configured to turn on in response to a voltage applied to a common source line or a voltage applied to the bit line to connect the common source line with the first source line; a second transmission gate configured to turn on in response to the voltage applied to the common source line or a voltage applied to the inverted bit line to connect the common source line with the second source line; a bit line isolation gate configured to connect the bit line and the inverted bit line with a sense bit line and an inverted sense bit line, respectively, during a write operation, and further configured to connect the bit line and the inverted bit line with the inverted sense bit line and the sense bit line, respectively, and then to connect the bit line and the inverted bit line with the sense bit line and the inverted sense bit line, respectively, during a read operation, wherein the connections of the bit line and inverted bit line with the sense bit line and the inverted sense bit line are controlled by a bit line isolation control signal; and a precharge circuit configured to precharge the sense bit line and the inverted sense bit line to a precharge voltage level in response to a precharge control signal.