Patent ID: 8039341

Claim:
A fabrication process for forming a semiconductor integrated circuit, comprising: forming a first gate structure overlying a first active region of a semiconductor on insulator (SOI) wafer; forming a second gate structure overlying a second active region of the SOI wafer, wherein the first and second active regions exhibit biaxial tensile stress, and wherein the first active region comprises an NMOS region and the second active region comprises a PMOS region; forming a mask over the first active region and the second active region; patterning the mask to cover the first active region and expose the SOI wafer in the second active region; forming recesses in source/drain regions of the second active region after patterning the mask, wherein forming recesses in source/drain regions includes: creating shallow recesses with a first active layer etch process; performing an amorphizing implant to create an amorphous layer below a surface of the shallow recesses after creating the shallow recesses; recrystallizing the amorphous layer with a neutral ambient anneal; and performing a second active layer etch process to deepen the relatively shallow recesses after recrystallizing the amorphous layer to complete a creation of the source/drain recesses; and selectively reducing a channel axis stress in the second active region by promoting migration of silicon in the second active region.