Patent ID: 8001171

Claim:
A pipeline Fast Fourier Transform architecture, comprising: a first Radix-2 butterfly stage coupled to receive a first input and configured to provide a first output responsive to the first input, the first Radix-2 butterfly stage configured to truncate at least one Least Significant Bit of the first output for a Fast Fourier Transform; a first delay and swap stage coupled to receive the first output and configured to provide a second output; a second Radix-2 butterfly stage coupled to receive the second output, the second Radix-2 butterfly stage configured to provide a third output responsive to the second output, the second Radix-2 butterfly stage configured to truncate at least one Most Significant Bit of the third output for the Fast Fourier Transform, wherein the at least one Most Significant Bit of the third output is a sign bit; and the first Radix-2 butterfly stage and the second Radix-2 butterfly stage being implemented in digital signal processing circuits; wherein, for a Single-Instruction Multiple Data operation, pad bits are used to block intra-segment ripple carry between an imaginary segment and a real segment as associated with complex numbers.