Patent ID: 7109776

Claim:
A clock gating circuit comprising: a first input to receive a clock signal; a second input to receive a gating signal; an output to output a gated clock signal to a dual edge-triggered-clocked circuit; an evaluation circuit to determine if the clock signal is in a first state or a second state in response to a transition of the gating signal from inactive to active, and to determine if the clock signal matches a held value of the gated clock signal in response to a transition of the gating signal from active to inactive; and an output circuit to hold the gated clock signal at a first value representing the first state if the clock signal is active during the transition of the gating signal from inactive to active, to hold the gated clock signal at a second value representing the second state if the clock signal is inactive during the transition of the gating signal from inactive to active, and to generate the gated clock signal so as to represent the clock signal only if the clock signal is determined to match the held value of the gated clock signal.