Patent ID: 8723094

Claim:
A method of timing a photodiode imager device to function in a global shutter mode, wherein the photodiode imager device includes a plurality of transistor pixel devices arranged into a plurality of rows, wherein each transistor pixel device further includes: a photodiode coupled to a floating diffusion region, a storage node, and a power supply, wherein the floating diffusion region is coupled between the photodiode and the power supply; a first global transfer transistor coupled between the photodiode and the floating diffusion region for gating between the photodiode and the floating diffusion region; a second global transfer transistor coupled between the floating diffusion region and the storage node for gating between the floating diffusion region and the storage node; a global reset select transistor coupled between the floating diffusion region and the power supply, wherein an open state of the global reset select transistor prevents accumulation of electrical charge at the photodiodes: and a source follower transistor coupled to the floating diffusion region and to the power supply, the source follower being operable to receive electrical signal from the floating diffusion region; wherein the first global transfer transistors from the plurality of transistor pixel devices are electrically coupled together, the second global transfer transistors from the plurality of transistor pixel devices are electrically coupled together, and the global reset select transistors from the plurality of transistor pixel devices are electrically coupled together, and wherein each transistor pixel device is a five transistor pixel device including a row select transistor coupled to the source follower transistor, comprising: pulsing first global transfer transistors and global reset select transistors to a high state then to a low state to reset the photodiodes and start integration; terminating integration by pulsing global reset select transistors to a high state then to a low state and setting second global transfer transistors to a high state to reset the storage node to a first voltage level corresponding to a low power supply setting; setting first global transfer transistors to a high state while second global transfer transistors are set to high substantially at the same time to globally transfer electrical charge from the floating diffusion regions to the storage nodes; and reading out the electrical charge in each of the plurality of rows using the row select transistor.