Patent ID: 8421127

Claim:
A semiconductor device, comprising: a well of a first conductive type, disposed in a substrate; a plurality of first doped regions of a second conductive type, disposed in the well, wherein the first doped regions extend along a first direction and are arranged in parallel; a plurality of gates of the second conductive type, disposed on the substrate, wherein the gates extend along a second direction different from the first direction and are arranged in parallel, and one of the first doped regions is electrically connected to one of the gates; a dielectric layer disposed on the substrate, wherein the dielectric layer has at least an opening correspondingly disposed at an electrically connected junction of the first doped regions and the gates, so that the first doped regions directly contact the corresponding gates; a plurality of second doped regions of the first conductive type, wherein each of the second doped regions is disposed in the first doped regions between two adjacent gates respectively; and a plurality of isolation structures, wherein each of the isolation structures is disposed in the substrate between two adjacent first doped regions respectively.