Patent ID: 8169807

Claim:
A content addressable memory device comprising: a first memory cell connected to a first match line and a first search line and having a first storage element and a first comparator circuit, the first storage element storing first data, the first comparator circuit comparing first search data inputted via the first search line with the first data, generating a first signal indicating a result of the comparison, and outputting the first signal to the first match line; and a second memory cell connected to a second match line and a second search line and having a second storage element and a second comparator circuit, the second storage element storing second data, the second comparator circuit comparing second search data inputted via the second search line with the second data, generating a second signal indicating a result of the comparison, and outputting the second signal to the second match line, wherein the content addressable memory device further comprises: a match line equalizer circuit having a first switch connected between the first match line and a power source, a second switch connected between the second match line and a ground, and a third switch connected between the first and second match lines; and a controller for, before the comparisons by the first and second comparator circuits, controlling the first and second switches to be turned on and the third switch to be turned off, and then controlling the first and second switches to be turned off and the third switch to be turned on, so that electric potentials of the first and second match lines are the same as each other.