Patent ID: 8790994

Claim:
A method for manufacturing a semiconductor device comprising the steps of: forming a peeling layer over a substrate; forming a first insulating layer over the peeling layer; forming at least a first semiconductor layer and a second semiconductor layer over the first insulating layer; forming a gate insulating layer over the first semiconductor layer and the second semiconductor layer; forming at least a first gate electrode and a second gate electrode over the first semiconductor layer and the second semiconductor layer with the gate insulating layer interposed therebetween; forming a first n-type impurity region by adding an impurity element into the first semiconductor layer, using the first gate electrode as a mask; forming a first p-type impurity region by adding an impurity element into the second semiconductor layer, using the second gate electrode as a mask; forming a sidewall insulating layer in contact with a side surface of the first gate electrode and overlapped with a part of the first n-type impurity region; forming a second n-type impurity region and a third n-type impurity region by adding an impurity element into the first n-type impurity region, using the sidewall insulating layer as a mask; forming a second insulating layer over the first gate electrode; forming a conductive layer being over the second insulating layer and functioning as at least one wiring electrically connected to one of the first semiconductor layer and the second semiconductor layer; forming a third insulating layer to cover the conductive layer; forming an opening by etching the first insulating layer, the gate insulating layer, the second insulating layer, and the third insulating layer to expose the peeling layer; and removing the peeling layer by introducing etchant to the opening so as to separate an integrated circuit from the substrate, the integrated circuit including the first semiconductor layer, the second semiconductor layer, the gate insulating layer, the first gate electrode and the second gate electrode.