Patent ID: 7254724

Claim:
A power management system for use in a computer system comprising: a computer system including, a non-volatile memory; and a controller coupled to the non-volatile memory representing the logical characteristics of a disc storage device to a host including a system manager for generating a plurality of clock signals to components of the controller and for further generating control signals to control activity within the controller by monitoring the operational activity levels within at least some of the components of the controller and arranged, in response to the monitored levels, to vary the power consumed by selected components of the controller and including an event monitor receptive to event sources indicative of the occurrence of significant system events and in response thereto varying power consumption, wherein the power management system is capable of entering various power modes one of which is a low-power mode, the event monitor being the only active part of the system manager, the event monitor outputing a WAKEUP signal to the rest of the system manager components, which causes the rest of the system manager to exit from a low-power mode, the system manager further including a system clock control module that generates an OSC_CLK clock for the controller having a frequency determined by external components to the controller, the system manager further including a phase locked loop (PLL) block responsive to the OSC_CLK clock for generating a PLL_CLK that is a factor of magnitude, in frequency, of that of the frequency of the OSC_CLK clock.