Patent ID: 8507386

Claim:
A method of fabricating an integrated circuit at a silicon surface of a substrate, comprising the steps of: forming isolation dielectric structures at selected locations of the surface, the isolation dielectric structures defining active regions of the silicon surface therebetween; forming gate electrode structures overlying selected locations of active regions of the silicon surface; etching recesses into a plurality of the active regions at locations adjacent to the gate electrode structures, and undercutting edges of the adjacent gate electrode structures, by a sequence of steps comprising: providing a source gas comprised of the mixture of a primary reactant species, the primary reactant species selected from the group consisting of fluorine-based reactants and chlorine-based reactants, with a diluent gas and with hydrogen bromine gas, the hydrogen bromine gas having a flow rate about the same as a flow rate of the primary reactant species; and exciting the source gas with RF energy to create a plasma; and exposing the silicon surface to the excited source gas; and then epitaxially forming a silicon alloy in the recesses.