Patent ID: 8542048

Claim:
A dual edge triggered flip flop circuit, comprising: a single storage element; a first latch circuit and a second latch circuit coupled to alternate input to the single storage element between a first feedback path and a second feedback path on rising and falling edges of a first clock signal; and a clock signal generator configured to receive the first clock signal and to output a plurality of clock signals including a first inverted clock signal, a second clock signal, and a second inverted clock signal, wherein the plurality of clock signals are delayed from one another and from the first clock signal by respective specified intervals; and wherein: the first latch circuit is in a conducting state and the second latch circuit is in a non-conducting state for a first window of time at the rising edge of the first clock signal; and the second latch circuit is in a conducting state and the first latch circuit is in a non-conducting state for a second window of time at the falling edge of the first clock signal.