Patent ID: 8448103

Claim:
A method of varying design feature depth in a semiconductor wafer comprising: choosing a via process for forming vias in the semiconductor wafer; selecting vias for placement with respect to a design feature, the vias being placed with respect to a location where the design feature is to be formed, wherein the design feature is a trench or via having a controlled depth in the semiconductor wafer when the design feature is formed; forming the vias in the semiconductor wafer; causing the formed vias in the semiconductor wafer to undergo an ashing process; applying an organic planarizing layer to the semiconductor wafer; forming the design feature having the controlled depth; measuring a depth of the design feature; documenting the depth of the design feature versus distance between design feature and vias to form a document of depth of design feature versus distance between design feature and vias; and choosing a via placement from the document that meets the design requirements for the design feature.