Patent ID: 7644263

Claim:
A start-up control system, comprising; a processor having a register arranged to store an address; a logic device connected to said processor, including an address buffer, an address conversion circuit connected to the address buffer, a read buffer, and data checking hardware; first and second start-up memories arranged to store start-up data required for starting up said processor and protection data including start-up protection code constituting protection code for said start-up data; and a local memory; wherein: the processor is arranged so that upon powering on the processor, the processor resets the register, writes the address into the reset register, and outputs the address from the register to the logic device; the address buffer is arranged to receive and store therein the address output from the register; the address conversion circuit is arranged to receive the address from the address buffer and to generate, from the received address, a first address specifying a first location in the first start-up memory and a second address specifying a second location in the second start-up memory; the read buffer is arranged to receive first data read from the first address in the first start-up memory and second data read from the second address in the second start-up memory; the data checking circuit is arranged to receive the first and second data from the read buffer and to check the validity of the received first and second data; if a result of the validity checks of the first and second data performed by the data checking circuit are both positive, indicating validity of both the first and second data, the first and second data are transferred to the processor and then expanded into the local memory as an operating system start-up program; and if either result of the validity checks of the first and second data performed by the data checking circuit is negative, indicating invalidity of either the first data or the second data, the data checking circuit performs error processing on the invalid data, outputs neither of the first or second data to the processor, and resets the processor.