Patent ID: 7315056

Claim:
An electrically programmable and erasable memory device, comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween; an electrically conductive floating gate having a first portion disposed over and insulated from the channel region, and a second portion disposed over and insulated from the first region and including a sharpened edge; an electrically conductive P/E gate having a first portion disposed over and insulated from the first region, and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material; and an electrically conductive select gate disposed laterally adjacent to and insulated from the floating gate and disposed over and insulated from the channel region; wherein the sharpened edge is formed at an intersection of a sloping upper surface of the floating gate and a side surface of the floating gate; wherein: the select gate is insulated from the channel region by a second layer of insulation material; the floating gate is insulated from the channel region and the first region by a third layer of insulation material; and the P/E gate first portion is insulated from the first region by the first and third layers of insulation material.