Patent ID: 7821441

Claim:
A successive approximation register (SAR) analog-to-digital converter (ADC), comprising a capacitor array including a plurality of switched capacitors therein with varying weights each having a common plate connected to a common node and a switched plate; at least one comparator for comparing the voltage on the common node of the capacitor array with a reference voltage, the at least one comparator having a first bias current applied thereto; a SAR controller for sampling an input voltage on said capacitor array in a sampling phase, and redistributing the charge stored thereon in a conversion phase by selectively changing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm; wherein the first bias current operates at first levels responsive to a first mode of operation of the SAR ADC and operates at second levels responsive to a second mode of operation of the SAR ADC; and wherein the common node is connected to a common mode voltage, and the switched plate is connectable to the input voltage during the sampling phase, and during the conversion phase, the switched plate of each of said array capacitors are connectable to the reference voltage to redistribute the charge thereon to the array and change the voltage on the common node.