Patent ID: 8085573

Claim:
A ferroelectric memory comprising a plurality of units, each unit comprising a ferroelectric capacitor and a transistor connected in parallel, the memory comprising: first and second memory cell arrays; first and second bit lines in the first and second memory cell arrays, respectively; first and second blocks connected to the first bit line, and comprising N 1 units and N 2 units, respectively, where N 1 and N 2 are positive integers; a first plate line in the first memory cell array, and connected to the first and second blocks in common; third and fourth bit lines in the first and second memory cell arrays, respectively; third and fourth blocks connected to the third bit line, and comprising N 3 units and N 4 units, respectively, where N 3 and N 4 are positive integers; a second plate line in the first memory cell array, and connected to the third and fourth blocks in common; a first redundant block connected to the first bit line, comprising N 1 units, and configured to be used for repairing the first block; a second redundant block connected to the second bit line, comprising N 2 units, and configured to be used for repairing the second block; a third redundant block connected to the third bit line, comprising N 3 units, and configured to be used for repairing the third block; a fourth redundant block connected to the fourth bit line, comprising N 4 units, and configured to be used for repairing the fourth block; first to fourth redundant plate lines connected to the first to fourth redundant blocks, respectively; and a sense amplifier selectively connectable to one of the first and second bit lines, and selectively connectable to one of the third and fourth bit lines, wherein: if N 1 is smaller than N 3 , the ferroelectric memory comprises (N 3 −N 1 ) dummy units connected to the first redundant block, if N 1 is greater than N 3 , the ferroelectric memory comprises (N 1 −N 3 ) dummy units connected to the third redundant block, if N 2 is smaller than N 4 , the ferroelectric memory comprises (N 4 −N 2 ) dummy units connected to the second redundant block, and if N 2 is greater than N 4 , the ferroelectric memory comprises (N 2 −N 4 ) dummy units connected to the fourth redundant block.