Patent ID: 7206985

Claim:
A calibratable test system for an integrated circuit, comprising: a pattern generator having a plurality of internal signal paths for generating sub-patterns, each of said internal signal paths including a sequence generator for generating a logical pulse stream and a timing format generator arranged thereafter, a node to which said plurality of internal signal paths are connected so that the sub-patterns generated by the signal paths are put together by superimposing in order to form a test signal as a pattern of sequent raising and falling signal edges; and a control connected to said pattern generator to select one or more of said plurality of internal signal paths so as to provide different test signals by different superimposed sub-patterns, said control constructed to provide an information signal for a measurement device of said test system which indicates for each individual signal edge of at least one sub-pattern generated by an internal signal path the internal signal path which generated the at least one sub-pattern, wherein said control provides said information signal for said measurement device synchronously to each signal edge.