Patent ID: 7229921

Claim:
A method of manufacturing a semiconductor device, comprising: forming a first wiring line composed of a copper containing metal film on or above a semiconductor substrate; changing a surface portion of said first wiring line into an amorphous layer; forming a first interlayer insulating film on a whole surface of said semiconductor substrate to cover said first wiring line; selectively removing said first interlayer insulating film to form a connection hole reaching said amorphous surface portion of said first wiring line; forming a barrier metal film to cover an inner surface of said connection hole and directly contact said amorphous surface portion of said first wiring line, and then forming a copper containing metal film to fill said connection hole; removing said copper containing metal film formed outside said connection hole; forming a second interlayer insulating film on a whole surface of said semiconductor substrate to cover said copper containing metal film formed in said connection hole; selectively removing said second interlayer insulating film to form a wiring line groove such that said copper containing metal film formed in said connection hole is exposed at a bottom; forming a barrier metal film to cover an inside of said wiring line groove and then forming a copper containing metal film to fill said wiring line groove; and removing said copper containing metal film outside said wiring line groove to form a second wiring line wherein said step of forming said first wiring line comprises the steps of: forming a first copper containing metal film by a plating method; forming a second copper containing metal film by a sputtering method on a surface of said semiconductor substrate to cover said first copper containing metal film; and carrying out thermal treatment to said first copper containing metal film and said second copper containing metal film.