Patent ID: 7595526

Claim:
A capacitor in a semiconductor device, comprising: a semiconductor substrate provided with conductive regions; an interlayer dielectric layer formed on the semiconductor substrate; a contact plug formed through the interlayer dielectric layer and connected to the conductive regions; an etch barrier layer formed on the interlayer dielectric layer; a first electrode formed on the contact plug and portions of the interlayer dielectric layer; first meta-stable polysilicon (MPS) grains formed along a predetermined portion of inside walls of the first electrode without covering an inner bottom surface of the first electrode; second MPS grains formed along the inside walls of the first electrode except the predetermined portion of the inside walls, an average size of the second MPS grains being smaller than that of the first MPS grains; a dielectric layer formed on the first electrode, the first MPS grains, and the second MPS grains; and a second electrode formed on the dielectric layer.