Patent ID: 7151704

Claim:
A semiconductor memory device comprising: a plurality of memory cell blocks including a redundant memory cell block; selecting means for selecting one memory cell from each of said memory cell blocks depending on an inputted address; plural pieces of amplifying means each provided in correspondence to each of said memory cell blocks so as to read data of the memory cell selected by said selecting means; a plurality of data buses each connected to each of plural pieces of said amplifying means; read data outputting means for outputting plural pieces of read data through a plurality of said data buses to the outside; and redundancy discrimination signal inputting means for inputting a redundancy discrimination signal for discriminating a memory cell block serving as an object of redundancy replacement among a plurality of said memory cell blocks, wherein in response to said redundancy discrimination signal, in case of redundancy replacement, said read data outputting means outputs read data excluding the read data of said memory cell block serving as an object of redundancy replacement, while in case of no redundancy replacement, said read data outputting means outputs read data excluding the read data of said redundant memory cell block among a plurality of said memory cell blocks, and wherein the read data excluded by said read data outputting means is used as a memory control signal.