Patent ID: 7218006

Claim:
A multi-chip stack package, comprising: a substrate having an upper surface and a plurality of connecting pads formed on the upper surface; a first chip disposed on the upper surface of the substrate, and having a first active surface and a plurality of first bonding pads formed on the first active surface; a redistribution structure having a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads, wherein the first intermediate pads, the second intermediate pads and the external pads are formed on the first active surface of the first chip, the first intermediate pads and the second intermediate pads are electrically connected to each other, and the external pads are electrically connected to the first bonding pads of the first chip; at least one second chip disposed on the redistribution structure and having a second active surface and a plurality of second bonding pads formed on the second active surface, the second bonding pads of the second chip electrically connected to the first intermediate pads; a plurality of first bonding wires for connecting the second intermediate pads of the redistribution structure and the connecting pads of the substrate; and a plurality of second bonding wires for connecting the external pads of the redistribution structure and the connecting pads of the substrate.