Patent ID: 7327626

Claim:
An apparatus for controlling a voltage used in a semiconductor memory device, comprising: a first voltage supplying block for supplying a first voltage to the semiconductor memory device in response to an inputted control signal; a second voltage supplying block for supplying a second voltage to the semiconductor memory device in response to the inputted control signal; and a signal generating block for receiving the inputted control signal, an internal self refresh signal and an external self refresh signal to generate a self refresh signal so as not to start a self refresh operation at once, even if the external self refresh signal is activated; wherein the first and the second voltages are used as a bulk voltage of a transistor included in the semiconductor memory device to increase a threshold voltage level of the transistor during the self refresh operation, and wherein the signal generating block includes a first logic block for inactivating the external self refresh signal during the inputted control signal is activated, and a second logic block for receiving an output of the first logic block and the internal self refresh signal to generate the self refresh signal.