Patent ID: 8294606

Claim:
A system comprising: a time-interleaving analog to digital conversion system comprising: an input configured to receive an analog signal; a plurality of analog to digital converters configured to generate a plurality of digital signals, wherein each of the plurality of analog to digital converters is configured to convert at least a portion of the analog signal to generate one of the plurality of digital signals; a plurality of sub-channel outputs configured to carry the plurality of digital signals; a direct current offset compensation system configured to (i) receive the plurality of digital signals from sub-channel outputs, and (ii) remove a bias offset from the plurality of digital signals to create compensated signals, wherein the direct current offset compensation system comprises a subtractor configured to remove the bias offset from one of the plurality of digital signals to generate one of the compensated signals, a multiplier configured to multiply the one of the compensated signals by a control value to generate a scaled digital signal, and an accumulator configured to (i) receive the scaled digital signal, and (ii) generate the bias offset based on the scaled digital signal; and a multiplexer configured to generate a first output signal based on the compensated signals.