Patent ID: 7783936

Claim:
A memory arbitrator for a parallel turbo decoder for resolving subdecoder access contention to a shared interleaver memory having multiple banks comprising: a plurality of N subdecoders configured for parallel sub-block decoding of a turbo code; a plurality of N buffer memories, each buffer memory associated with a different one of the plurality of subdecoders and having a depth M so as to buffer a plurality of M access attempts to the shared interleaver memory by the associated subdecoder; a multiplexer coupled between the plurality of N buffer memories and the shared interleaver memory and configured to enable access to the shared interleaver memory by the plurality of buffer memories; and a scheduler coupled to the plurality of subdecoders and configured to reschedule the accesses to the shared interleaver memory based on an interleaver pattern of the turbo decoder to avoid simultaneous access to at least one of the multiple banks of the shared interleaver memory.