Patent ID: 7884406

Claim:
A semiconductor device comprising: a semiconductor substrate; a MOS transistor comprising a gate electrode formed above said semiconductor substrate and current input/output regions formed in said semiconductor substrate on both sides of said gate electrode; a lower interlevel insulating film formed on the semiconductor substrate, covering said MOS transistor; a ferroelectric capacitor formed above said lower interlevel insulating film comprising: a capacitor lower electrode; an oxide ferroelectric film formed on said capacitor lower electrode; a first capacitor upper electrode formed on said oxide ferroelectric film and made of conductive oxide having a stoichiometric composition AO x1 and an actual composition AO x2 ; a second capacitor upper electrode formed on said first capacitor upper electrode and made of conductive oxide having a stoichiometric composition BO y1 and an actual composition BO y2 , where y2/y1>x2/x1; and a third capacitor upper electrode formed on said second capacitor upper electrode and having a composition containing metal of the platinum group; a multilayer wiring structure formed above said lower interlevel insulating film, covering said ferroelectric capacitor and including interlevel insulating films and wirings, wherein said third capacitor upper electrode is made of conductive oxide having a stoichiometric composition CO z1 and an actual composition CO z2 , where y2/y1>z2/z1; wherein said A, B, and C are ones selected from the group consisting from platinum, iridium, ruthenium, rhodium, rhenium, osmium and palladium; a first via hole formed through said lower interlevel insulating film, and exposing one of said current input/output regions of said MOS transistor; a conductive plug filling said first via hole; an underlying conductive layer formed on said lower interlevel insulating film and said conductive plug, and having oxygen blocking function; wherein said capacitor lower electrode is formed above said underlying conductive layer.