Patent ID: 7898845

Claim:
A resistance change memory comprising: a first memory cell array and a second memory cell array aligned in a first direction, each of the first memory cell array and the second memory cell array comprising a matrix of a plurality of memory cells, and each of the memory cells comprising a resistance change material and a selection transistor; a first reference cell array corresponding with the first memory cell array; a second reference cell array corresponding with the second memory cell array; a first sense amplifier between the first memory cell array and the second memory cell array, connected to the first memory cell array and the second memory cell array; a first data bus configured to transfer data of a first readout cell in the first memory cell array to the first sense amplifier; and a second data bus configured to transfer data of a first reference cell in the first reference cell array to the first sense amplifier, the first reference cell corresponding with the first readout cell, wherein the first data bus and the second data bus on both sides of the first sense amplifier are configured to extend in a second direction perpendicular to the first direction and to cross each other.