Patent ID: 8909995

Claim:
A microcomputer comprising: a central processing unit (CPU) that, when operating normally, repeatedly generates a clear signal; a watchdog timer-counter that receives the clear signal from the CPU and, if no clear signal is received for a predetermined length of time, asserts an overflow reset signal for a first interval, thereby resetting the CPU; a register in which a length of time of a second interval longer than the first interval is stored; a counter that receives a clock, begins counting the clock when an external reset signal is asserted, thereby generating an interval count; a comparator that compares the interval count with the length of time of the second interval, and generates an equality signal when the interval count matches the length of time of the second interval; a set-reset flip-flop that receives the overflow reset signal as one input and the equality signal as another input and generates an external reset signal for asserting an external peripheral device controlled by the CPU, the external reset signal being supplied to the counter; and a reset output terminal for external output of the external reset signal; wherein the set-reset flip-flop asserts the external reset signal when the overflow reset signal output from the watchdog timer-counter is input, and ceases to assert the external reset signal when the equality signal is input.