Patent ID: 7713822

Claim:
A method of forming a monolithically integrated trench FET and Schottky diode, the method comprising: forming a pair of trenches extending through an upper silicon layer and terminating within a lower silicon layer, the upper and lower silicon layers having a first conductivity type, the upper silicon layer extending over the lower silicon layer; forming first and second silicon regions of a second conductivity type in the upper silicon layer between the pair of trenches; forming a third silicon region of the first conductivity type extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer; performing a silicon etch to form a contact opening extending through the third silicon region such that outer portions of the third silicon region remain, the outer portions of the third silicon region forming source regions; and forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.