Patent ID: 7528019

Claim:
A method of fabricating a thin film transistor, comprising: providing a substrate; forming a first patterned dielectric layer having at least one first opening over the substrate; forming a first metallic layer to cover the first patterned dielectric layer and the first opening; planarizing the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate; forming a gate insulating layer over the first patterned dielectric layer and the gate; forming a semiconductor layer over the gate insulating layer above the gate; forming a second patterned dielectric layer over the gate insulating layer; forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; performing a planarization process to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form a source and a drain in the second openings; and after forming the source and the drain, removing the second patterned dielectric layer.