Patent ID: 7337424

Claim:
A computer-implemented method of identifying a shape in an integrated circuit layout for resolution enhancement, the method comprising: identifying a first edge satisfying a first minimum length condition in the layout; identifying a second edge satisfying a second minimum length condition and an edge transition angle condition in relation to the first edge in the layout; identifying one or more first transition edges satisfying a first maximum length condition and connected between the first edge and the second edge in the layout, a first variation of the shape including the first edge, the second edge, and the first transition edges; identifying a third edge satisfying a third minimum length condition in the layout; identifying a fourth edge satisfying a fourth minimum length condition and the edge transition angle condition in relation to the third edge in the layout; and identifying one or more second transition edges satisfying a second maximum length condition and connected between the third edge and the fourth edge in the layout, a second variation of the shape including the third edge, the fourth edge, and the second transition edges, wherein the first transition edges are different from the second transition edges but both the first variation of the shape and the second variation of the shape being identified as having the same shape.