Patent ID: 8865548

Claim:
A method of making a non-volatile double-gate memory cell comprising a control transistor comprising a gate and a memory transistor comprising a control gate adjacent to the gate of the control transistor, wherein the method comprises the steps of: forming at least partly the gate of the control transistor, comprising obtaining a relief of a semiconductor material on a substrate; forming the control gate of the memory transistor, comprising the steps of: forming on at least one sidewall of the relief of a semiconductor material and at least one part of the substrate of a stack of layers configured to store electrical charges; depositing a first layer of a semiconductor material so as to at least cover the stack of layers; etching of the first layer so as to form a first pattern, juxtaposed on the relief of a semiconductor material of the gate of the control transistor; wherein said forming of the control gate of the memory transistor additionally comprises the following steps of: forming a second layer of a semiconductor material, at least on the first pattern; etching of the second layer so as to form on the first pattern a second pattern having a substantially plane upper face configured to permit defining a contact area on the control gate of the memory transistor.