Patent ID: 8443141

Claim:
In a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, a system for write caching for sequential tracks, comprising: a processor device operable in the computing storage environment, wherein the processor device is adapted for performing at least one of: examining a plurality of tracks in a plurality of strides for determining if a temporal bit is set on any one of the plurality of tracks; and resetting the temporal bit on each one of the plurality of tracks if the temporal bit is set on any one of the plurality of tracks, wherein: if a first track is determined to be sequential, and an earlier track is also determined to be sequential, clearing the temporal bit associated with the earlier track to allow for destage of data of the earlier track; and if the temporal bit for one of the plurality of tracks in one of the plurality of strides in a modified cache is determined to be not set, selecting a stride associated with the one of the plurality of tracks for a destage operation, wherein if the NVS exceeds a predetermined storage threshold, selecting a predetermined one of the plurality of strides for the destage operation.