Patent ID: 8035219

Claim:
A package for a semiconductor device for a plurality of spaced transistors formed in a surface portion of a semiconductor wafer, comprising: a first lithographically processable, etchable material disposed on and in contact with the surface portion of the semiconductor wafer having a plurality of openings in the first lithographically processable, etchable material, each one a first portion of the openings exposing a corresponding single one of the plurality of spaced transistors and each one of a second portion of the openings in the first lithographically processable, etchable material exposing electrical contacts pads for the transistors; and a support; a rigid dielectric layer comprising a second lithographically processable material disposed on a selected region of the support and absent from other regions of the support, the second lithographically processable material being suspended over openings in the first lithographically processable, etchable material to expose the devices; and wherein said other regions of the support are disposed over the opening to expose the electrical contacts pads.