Patent ID: 8883594

Claim:
A method for forming a field effect transistor (FET), the method comprising: providing a substrate; etching the substrate to form a protrusion on a surface of the substrate; forming isolation feature on the substrate in a first area and a second area, wherein in the first area each protrusion is isolated by the isolation feature, wherein in the second area, there are more than one protrusions between adjacent isolation features; doping a portion of the substrate adjacent to the protrusion to form a drain region between isolation features, including extending to a lower portion of the protrusion to form a raised drain region; forming a first isolation dielectric layer over the drain region; forming gate stack having a planar portion over the drain region, which is parallel to the surface of substrate, and a gating surface, which wraps around a middle portion of the protrusion, including overlapping with the raised drain region, wherein in the first area each gate stack is isolated to each other, wherein in the second area gate stacks are connected to each other; forming a second isolation dielectric layer over the planar portion of the gate stack and the drain region; recessing a portion of the gating surface of the gate stack to expose a top portion of the protrusion; forming a source region on the top portion of the protrusion with a different dope type than the drain region, including overlapping with the gating surface of the gate stack; forming a third isolation dielectric layer over the source region, the gate stack and the second isolation dielectric layer; forming a source contact, a gate contact and a drain contact; and by utilizing a conductive line (including through contacts of source, gate and drain) forming a series connection in the first area and a parallel connection in the second area.