Patent ID: 8572334

Claim:
An improved integrated circuit configured to facilitate communication between a microprocessor and a non-volatile memory, the improvement comprising: a lock register comprising a plurality of lock bits, each of the lock bits associated with a unit of storage in the non-volatile memory, the lock bits representing whether or not the unit of storage in the non-volatile memory has been locked, a state of the lock bits capable of being modified; a sticky-lock register comprising a plurality of sticky-lock bits, each of the sticky-lock bits associated with a unit of storage in the non-volatile memory, the sticky-lock bits representing whether or not the unit of storage in the non-volatile memory has been sticky-locked, a state of the sticky-lock bits capable of being modified only upon a reboot; a lock status register comprising a plurality of lock status bits, each of the lock status bits associated with a unit of storage in the non-volatile memory, the lock status bits representing whether or not the unit of storage in the non-volatile memory has been locked, wherein the lock status bits of the lock status register are set by logically ORing the sticky-lock bits of the sticky-lock register with corresponding lock bits of the lock register; a control register configured to store configurable control information, the configurable control information including sizing information defining a size of the unit of storage; and a memory controller receiving the configurable control information and configured to: receive a modification request to modify data in the non-volatile memory; determine a target unit of storage in the non-volatile memory based on a target memory address associated with the modification request; determine from one of the lock register, the sticky-lock register, and the lock status register whether the target unit of storage has been locked; and implement the modification request only if the target unit storage has not been locked.