Patent ID: 8193863

Claim:
An output circuit comprising: a first transistor connected between a first power supply rail and an output unit; a second transistor connected between the output unit and a second power supply rail; a gm amplifier comprising an input unit and first and second output terminals, the gm amplifier being configured to amplify a difference between a signal input to the input unit and a reference voltage; a first current mirror circuit and a second current mirror circuit connected in series between the first power supply rail and the first output terminal of the gm amplifier, and connected to a gate of the second transistor, the second current mirror circuit comprising a first drain/collector terminal and a second drain/collector terminal through which a current flows in accordance with a current flowing through the first drain/collector terminal; and a third current mirror circuit and a fourth current mirror circuit connected in series between the second power supply rail and the second output terminal of the gm amplifier, and connected to a gate of the first transistor, the fourth current mirror circuit comprising a third drain/collector terminal and a fourth drain/collector terminal through which a current flows in accordance with a current flowing through the third drain/collector terminal, wherein the gate of the first transistor is connected to a node between the first current mirror circuit and the second current mirror circuit; the gate of the second transistor is connected to a node between the third current mirror circuit and the fourth current mirror circuit; the first output terminal of the gm amplifier is connected to the first drain/collector terminal of the second current mirror circuit; and the second output terminal of the gm amplifier is connected to the third drain/collector terminal of the fourth current mirror circuit.