Patent ID: 8368150

Claim:
An integrated circuit device comprising: a semiconductor substrate comprising a base surface and an active surface vertically spaced apart from and opposing said base surface, said active surface extending in a horizontal direction and having at least one active device therein; multiple metal and dielectric layers over said semiconductor substrate; a first contact pad over said active surface of said semiconductor substrate; a second contact pad over said active surface of said semiconductor substrate; a passivation layer over said multiple metal and dielectric layers, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact area of said first contact pad, and said first contact area is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact area of said second contact pad, and said second contact area is at a bottom of said second opening; a power metal pad over said passivation layer and covered by a post-passivation layer comprising a polymer, said power metal pad having a first region and a second region, said second region being directly vertically over said first contact area, wherein said power metal pad is connected to said first contact area through said first opening, and said first region is not directly vertically over, and is horizontally offset from, said first opening and said first contact area such that said first region is directly attached to a wirebond through an opening in said post-passivation layer for connection made to a next level of packaging; a ground metal pad over said passivation layer and covered by said post-passivation layer, said ground metal pad having a third region and a fourth region, said fourth region being directly vertically over said second contact area, wherein said ground metal pad is connected to said second contact area through said second opening, and the third region is not directly vertically over, and is horizontally offset from, said second opening and said second contact area such that said third region is directly attached to a wirebond through an opening in the post-passivation layer for connection made to said next level of packaging; a capacitor over said post-passivation layer and said power and ground metal pads, said capacitor comprising a first terminal and a second terminal, said first terminal directly vertically over and connected through an opening in said post-passivation layer by a first solder joint to said second region, and said second terminal directly vertically over and connected through an opening in said post-passivation layer by a second solder joint to said fourth region.