Patent ID: 7496862

Claim:
A method for automatically adjusting a layout of one type of metal-oxide-semiconductor (MOS) integrated circuit (IC) cells, the method comprising the following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer; expanding the one or more MOS transistor ODs in a predetermined direction by a first predetermined amount; shifting the one or more power ODs in the predetermined direction by a second predetermined amount; expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount; shifting one or more power OD contacts in the predetermined direction by the second predetermined amount; and stretching one or more metal areas (M 1 s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined new width, wherein a cell height and a transistor width of the MOS IC layout are automatically and independently adjusted.