Patent ID: 8667198

Claim:
A data processing system, comprising: a processing unit; an interrupt controller coupled to the processing unit, wherein the interrupt controller is configured to transmit a first interrupt signal to the processing unit, the first-priority interrupt signal to cause at least the processing unit to be powered up from a reduced power state; and a timer circuit coupled to the interrupt controller; wherein the processing unit is configured to: maintain a list, wherein the list includes a plurality of entries of time-related events for a plurality of application programs, wherein the plurality of entries include a respective scheduled time for each time-related event to be performed; select an entry of the plurality of entries of the list for a given one of the time-related events; determine a time latency value for the processing unit to power up from a reduced power state; determine a wake up time for the given one of the time-related events dependent upon the determined time latency value and the respective scheduled time included in the selected entry of the plurality of entries; store a value into the timer circuit, the value representing the determined wake up time for the time-related event to be performed; and enter the reduced power state; wherein the timer circuit is configured to initiate an assertion of the first-priority interrupt signal for the time-related event to be performed as scheduled in response to reaching the determined wake up time while the processing unit is in the reduced power state; and wherein the processing unit is further configured to: power up from the reduced power state in response to the assertion of the first interrupt signal; and execute an application program corresponding to the selected entry for the given one of the time-related events.