Patent ID: 8072463

Claim:
A graphics system, comprising: a partitioned graphics memory having a plurality of independently addressable partitions each including at least one dynamic random access memory (DRAM), with a total number of operative DRAMs being a non power of two number, and at least one of said partitions including multiple DRAMs; a graphics processing unit coupled to said partitioned graphics memory; an address translation module in said graphics processing unit performing an address translation mapping virtual addresses to physical addresses and determining individual partitions associated with memory accesses for individual units of virtual memory allocation, said address translation module configured to perform a first modulo operation to select an individual partition in said partitioned graphics memory, said address translation module configured to perform a second modulo operation to select an individual DRAM included in said selected partition; said graphics system performing partition interleaving in which data for an individual unit of virtual memory allocation is assigned to one partition and different individual units of virtual memory allocation are assigned to different partitions; said graphics system performing a partition swizzling operation to adjust the partition numbers associated with said individual units of virtual memory allocation on particular virtual memory pages to achieve a selected partition interleaving pattern.