Patent ID: 8064256

Claim:
A non-volatile FIFO, comprising: a front-end-of-the-line (FEOL) portion including a substrate, the substrate including active circuitry and an interconnect structure, at least a portion of the active circuitry and interconnect structure are configured for FIFO data operations; and a back-end-of-the-line (BEOL) portion in contact with the FEOL portion and fabricated above and positioned above the FEOL portion, the BEOL portion including a plurality of two-terminal non-volatile memory cells configured to store data as a plurality of conductivity profiles that are retained in the absence of power, the interconnect structure and the active circuitry operative to electrically couple each memory cell with a write word line, a read word line, a pair of write bit lines, and a pair of read bit lines, the BEOL portion further including at least one two-terminal non-volatile resistive reference cell operative to generate a reference signal during a read operation, wherein data is written to each memory cell by enabling the write word line connected with the memory cell and applying a write voltage across the pair of write bit lines connected with the memory cell, and wherein data is read from each memory cell by enabling the read word line connected with the memory cell and applying a read voltage across the pair of read bit lines connected with the memory cell.