Patent ID: 7934074

Claim:
A plane-interleaved flash-memory system comprising: flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block; wherein the flash memory is further arranged into a plurality of planes, that are plane-interleaved and accessible in parallel; a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the flash memory; wherein the mapping entry further comprises a plane number and a page number; a binary counter having a least-significant bit (LSB), a second LSB having a higher significance than the LSB, and middle bits having a higher significance than the second LSB; a physical sequential address register, coupled to the binary counter, for storing a generated block number, wherein the middle bits have a higher significance than the second LSB in the generated block number, the second LSB being shifted to a higher bit position in the generated block number; a page counter indicating the page number in the physical block in the flash memory; an interleave incrementer for incrementing the LSB and the second LSB and not incrementing the middle bits when host data is to be written to a new page and all pages in a physical block of a fourth plane have not been yet filled; a page incrementer for incrementing the page counter when host data is to be written to a new page and when the LSB and the second LSB indicate the fourth plane and when empty pages are available in the physical block; and a block incrementer for incrementing the middle bits when the LSB and the second LSB indicate the fourth plane and no empty pages are available in the physical block; wherein the LSB and the second LSB are written to the mapping entry as the plane number, and the page counter is written to the mapping entry as the page number when host data is written to the physical block corresponding to the mapping entry; wherein the generated block number is written to the mapping entry as the physical block address, the generated block number having the second LSB shifted to a most-significant bit (MSB) of the physical block address, whereby flash memory is plane-interleaved to different physical blocks using the second LSB as a most-significant bit (MSB) of the physical block address.