Patent ID: 8141013

Claim:
A computer implemented method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models, the method comprising: recognizing, by a computing device, a passive device; interpreting, by said computing device, data obtained from the recognizing of the passive device; breaking the passive device, by said computing device, into a plurality of sections, the plurality of sections comprising a terminal of a model call; extracting, by said computing device, parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction; connecting the terminal, by said computing device, to a distributed pre-layout passive model network by selecting low and high resistive netlist paths through the parameters of the passive device depending on if crossing lines are present or not present in one of the plurality of sections; and coupling the crossing lines, by said computing device, to the terminal via capacitors produced in an extracted netlist, with the passive device having distributed coupling to a plurality of crossing lines, wherein the distributed pre-layout passive models comprise a plurality of terminals to which post-layout extracted parasitics are attached to correctly model effects of a varying density of the plurality of crossing lines within the layout of the passive device.