Patent ID: 8488362

Claim:
A memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells located between the word lines and bit lines, memory cells in the plurality of memory cells comprising a diode, a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode and the metal-oxide memory element arranged in electrical series along a current path between a corresponding word line in the plurality of word lines and a corresponding bit line in the plurality of bit lines, and a conductive element underlying the memory element and electrically coupling the memory element to the diode, wherein the metal-oxide memory element comprises a metal oxide body that has an oxygen content which increases with distance from the conductive element; and bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells, the bias arrangements including: a first bias arrangement to forward-bias the diode of the selected memory cell and change the resistance state of the memory element of the selected memory cell from the first resistance state to the second resistance state; and a second bias arrangement to forward-bias the diode of the selected memory cell and change the resistance state of the memory element of the selected memory cell from the second resistance state to the first resistance state.