Patent ID: 7284174

Claim:
A Joint Test Action Group (JTAG) interface for a logic device comprising a plurality of input/output (I/O) ports, the JTAG interface comprising: a respective boundary scan data cell coupled to each I/O port of the logic device for selectively routing input data to the I/O port during a normal mode of operation and boundary scan input data during a JTAG mode of operation, each boundary scan data cell comprising a multiplexing arrangement for selectively routing a JTAG clock signal to the respective I/O port during the normal mode of operation; and a control cell associated with each boundary scan data cell to selectively enable the normal mode of operation and the JTAG mode of operation, each control cell also selectively enabling/disabling routing of the JTAG clock signal in a respective boundary scan data cell; each boundary scan data cell and associated control cell being responsive to a set of JTAG instructions for selecting a respective I/O port for routing of the JTAG clock signal thereto.