Patent ID: 8397009

Claim:
An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each interconnection sub-network comprising: at least one addressing bus and one information transfer bus connecting one of the m first circuits to all the n second circuits, the information transfer bus comprising a plurality of portions of signal transmission lines connected to each other through signal repeater devices, and means for controlling the signal repeater devices, at least one of the signal repeater devices is controlled to be active depending on a value of an addressing signal to be sent to the addressing bus by said one of the m first circuits to the means for controlling, the at least one of the signal repeater devices controlled to be active forms a communication path in the information transfer bus for data signals between said one of the m first circuits and at least one of the n second circuits and/or between at least a first one of the n second circuits and at least a second one of the n second circuits, where m and n are integer numbers greater than 1.