Patent ID: 8198149

Claim:
A method for fabricating an active device array substrate, comprising: forming a first patterned semiconductor layer, a gate insulator, a first patterned conductive layer, and a first dielectric layer on a substrate, wherein the gate insulator covers the first patterned semiconductor layer, the first patterned conductive layer is disposed on the gate insulator, and the first dielectric layer is disposed on the gate insulator to cover the first patterned conductive layer; forming a plurality of first contact holes exposing the first patterned semiconductor layer in the first dielectric layer and the gate insulator; forming a second patterned conductive layer on the first dielectric layer and a second patterned semiconductor layer disposed on the second patterned semiconductor layer simultaneously, wherein the second patterned conductive layer comprises a plurality of contact conductors and a bottom electrode, and the second patterned semiconductor layer comprises an active layer disposed on the bottom electrode; forming a second dielectric layer on the first dielectric layer; forming a plurality of second contact holes in the second dielectric layer, wherein a portion of the second contact holes exposes the active layer; and forming a third patterned conductive layer on the second dielectric layer, wherein a portion of the third patterned conductive layer is electrically connected to the active layer through a portion of the second contact holes.