Patent ID: 8476701

Claim:
A semiconductor device comprising: a substrate that includes an element forming region that is partitioned by an element isolation insulating film; and a transistor that includes: a trench formed in said element forming region of said substrate; a gate insulating film formed on side faces and a bottom face of said trench; a gate electrode formed on said gate insulating film so as to bury said trench and on said substrate outside said trench so as to be exposed; a source region formed on one side of said gate electrode, which is disposed on a surface of said substrate, in a gate longitude direction; and a drain region formed on another side of said gate electrode in said gate longitude direction, wherein a longer direction of said trench is abreast of said gate longitude direction, wherein at least both ends of an edge of an opening of said trench in said gate longitude direction are covered with said exposed part of said gate electrode, wherein said gate electrode has at least one concave portion having a depth reaching a surface of said substrate, wherein said concave portion extends in a direction which intersects said gate longitude direction in a planar view, wherein said concave portion overlaps with a part of said trench, a part of said edge of said opening, and a part of said surface of said substrate located along said part of said edge in a planar view, and wherein said part of said edge and said part of said surface are not covered with said gate electrode.