Patent ID: 7588983

Claim:
A method of manufacturing an EEPROM cell, the method comprising: preparing a semiconductor substrate that has a first region in which a first EEPROM device will be formed, a second region in which a second EEPROM device will be formed, and a common source region disposed between the first region and the second region; forming a first gate stack for a first select transistor and a second gate stack for a first memory transistor in the first region of the semiconductor substrate and forming a third gate stack for a second select transistor and a fourth gate stack for a second memory transistor in the second region of the semiconductor substrate; forming first impurity regions with a first dopant concentration respectively in a drain region and a floating region of the first region, in a drain region and a floating region of the second region, and in the common source region by performing a first ion implantation process on the semiconductor substrate on which the first, second, third, and fourth gate stacks are formed; forming second impurity regions with a second dopant concentration respectively in the first impurity regions of the common source region by performing a second ion implantation process on the semiconductor substrate in which the first impurity regions are formed, wherein the second dopant concentration is higher than the first dopant concentration; and forming third impurity regions with a third dopant concentration respectively in the drain region of the first region, in the drain region of the second region, and in the common source region by performing a third ion implantation process on the semiconductor substrate in which the first and second impurity regions are formed, wherein in the common source region, the third impurity region is surrounded by the second impurity region in a horizontal direction but formed to have a greater junction depth than the second impurity region.