Patent ID: 8223566

Claim:
A memory device, comprising: an address receiver, for receiving and converting external address information to generate internal address information; a command receiver, for receiving and converting an external command to generate an internal command; a command controller, for generating a row latch control signal or generating a column latch control signal according to the internal command; a row address generator, for receiving the internal address information and deciding how to convert the internal address according to the row latch control signal so as to generate a latched row address; a column address generator, for receiving the internal address information and deciding how to convert the internal address according to the column latch control signal so as to generate a latched column address; and a shared redundancy decision circuit, for receiving the internal address information and then either generating a row redundancy start signal according to the internal address information and the row latch control signal or generating a column redundancy start signal according to the internal address information and the column latch control signal; wherein, when the row redundancy start signal or column redundancy start signal generated by the shared redundancy decision circuit is at a first voltage level, the memory device starts a normal word line circuit of the corresponding latched row address or starts a normal bit switch circuit of the corresponding latched column address; and, when the row redundancy start signal or column redundancy start signal generated by the shared redundancy decision circuit is at a second voltage level, the memory device starts a redundancy word line circuit of the corresponding latched row address or starts a redundancy bit switch circuit of the corresponding latched column address.