Patent ID: 7675791

Claim:
A synchronous memory device, comprising: a clock recovery circuit generating a data output clock signal in response to an external clock signal and a feedback clock signal; a first replica circuit receiving the data output clock signal, providing a plurality of first transfer signals whose time differences with respect to the data output clock signal are shorter than a period that it takes a data output buffer to output data received from a memory cell array, and providing a feedback clock signal whose time difference with respect to the data output clock signal is substantially identical to a period that it takes the data output buffer to output data received from the memory cell array; a second replica circuit receiving the feedback clock signal and providing a second transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that a it takes a read command buffer to provide a read signal; and a latency circuit receiving the read signal, and providing latency signals in response to the second transfer signal and the plurality of first transfer signals.