Patent ID: 7903470

Claim:
An integrated circuit, comprising: a memory device, comprising; a memory cell; a well voltage line coupled to a well of the memory device; a first voltage line coupled to a first first node of the memory cell; and a first supplier supplying a first voltage to the well voltage line and coupling a coupled voltage on the first voltage line during an erasing period, wherein the first voltage is high enough to erase data stored in the memory cell; and a discharge circuit discharging the well voltage line and the first voltage line after the end of the erasing period, comprising: a first switch circuit coupled between the well voltage line, the first voltage line and a second supplier, wherein the second supplier supplies a second voltage smaller than the first voltage and the coupled voltage; a second switch circuit coupled between the first switch circuit and a reference voltage, wherein the reference voltage is smaller than the first voltage; a first control voltage supplier coupled to the first switch circuit and supplying a first control voltage to turn on the first switch circuit during a first discharge period so as to couple the well voltage line and the first voltage line to the second supplier; and a second control voltage supplier coupled to the second switch circuit and supplying a second control voltage to turn on the second switch circuit during a second discharge period so as to couple the well voltage line and the first voltage line to the reference voltage.