Patent ID: 8040449

Claim:
A thin film transistor array panel comprising: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate; a gate insulating layer disposed on the data line and the gate electrode, the gate insulating layer having a first contact hole exposing the gate electrode and a second contact hole exposing the data line; a gate line disposed on the gate insulating layer, the gate line intersecting the data line and electrically connected to the gate electrode through the first contact hole; a semiconductor disposed on the gate insulating layer, the semiconductor including a channel of a thin film transistor; a source electrode disposed on the semiconductor, the source electrode electrically connected to the data line through the second contact hole; a drain electrode disposed opposite to the source electrode with respect to the channel on the semiconductor; a passivation layer disposed on the gate line, the source electrode, the drain electrode, and the channel of the semiconductor, the passivation layer having a third contact hole exposing the drain electrode; and a pixel electrode formed on the passivation layer, the pixel electrode electrically connected to the drain electrode through the third contact hole.