Patent ID: 7240269

Claim:
A semiconductor testing device comprising: a pattern generator which produces a test pattern and an expected value pattern; a waveform formatter which formats a waveform of the test pattern to supply the formatted pattern to a device under test; a pattern comparison unit which compares a test result from the device under test with the expected value pattern from the pattern generator to judge whether or not the device under test is satisfactory; and a timing generator which supplies a timing pulse signal to the waveform formatter to take a test timing, wherein the timing generator comprises: a delay time calculation means for calculating a delay time given to the reference signal; and a signal input/output circuit which delays the reference signal in accordance with the delay time calculated by the delay time calculation means, wherein the signal input/output circuit includes a data holding circuit which inputs the reference signal and which outputs the reference signal based on an input timing of a delayed clock signal, and a clock signal delaying circuit which delays the clock signal supplied to the data holding circuit based on the delay time.