Patent ID: 6944251

Claim:
A digital phase locked loop circuit for generating sampling clock signals used with respect to a plurality of channels for sampling reproduced information simultaneously from a plurality of tracks of a recording medium, comprising: an average frequency computing circuit for calculating an average frequency of the phase locked sampling clock signals in selected channels and feeding back the calculated average to the phase locked loop; wherein the average frequency computing circuit outputs a frequency error signal with respect to any channel in which the frequency of the sampling clock signals is outside an allowable frequency range; wherein the average frequency computing circuit comprises a comparator for comparing the frequency of the sampling clock signals in each channel with the allowable frequency range and for outputting the frequency error signal for any channel in which the frequency of the sampling clock signals is outside the allowable frequency range; and wherein the digital phase locked loop circuit further comprises a gate circuit for masking the frequency error signal in an operational mode other than a tracking mode.