Patent ID: 7710772

Claim:
A memory device having an array of singularly addressable cells with k levels, and organized into pages of a number of words, each to store a string of a number of bits, the device comprising: a coding circuit to be input with strings of N bits to be stored, and to generate corresponding k-level strings according to a code; a program circuit to be input with the k-level strings and to store them in respective groups of c cells with k levels; a read circuit to read data stored in groups of c cells with k levels and to generate corresponding k-level strings; a read decoding circuit to be input with k-level strings read from groups of c cells with k levels to generate, according to the code, corresponding strings of N bits; the words of each page being grouped in groups of a number of words, each word comprising a number of groups of c cells with k levels, and at least one remaining bit of the word being stored, together with corresponding remaining bits of other words of the page, in a respective group of c cells with k levels.