Patent ID: 7085180

Claim:
A memory device configured to perform multi-bank operations comprising a plurality of memory banks including at least a first and second memory bank respectively controlled by a first and a second redundancy replacement means, said memory device comprising: a redundancy allocation means for allocating redundancy elements by way of performing a comparison of data bits read out from said first memory bank against corresponding expected data, said data bit comparison occurring only when said first bank is addressed during a multi-bank operation, said comparison being performed by a dynamic exclusive OR circuit comprising: a first transistor having a gate, source, and drain respectively coupled to said data to a first node and to a second node, a second transistor having a gate, source, and drain respectively coupled to the complement of said expected data, to a first voltage source, and to said first node; a third transistor having a gate, source, and drain respectively coupled to the complement of said data, to a third node, and to said second node, and a fourth transistor having a gate, source, and drain respectively coupled to said expected data, to said first voltage source, and to said third node, such that said second node follows said first voltage source only if no match of said data to said expected data occurs.