Patent ID: 8022465

Claim:
A memory cell comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises: a top insulating layer disposed under the gate, a bottom insulating layer disposed between the semiconductor substrate and the top insulating layer; a second charge-trapping layer consisting of a single layer disposed under and contacting the top insulating layer, and a first charge-trapping layer disposed between the bottom insulating layer and the second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a plurality of interfacial traps and a hydrogen concentration of less than about 3×10 11 /cm 2 , and a hydrogen concentration of the first charge-trapping layer is lower than a hydrogen concentration of the second charge-trapping layer and the first charge-trapping layer is in contact with the second charge-trapping layer.