Patent ID: 6881664

Claim:
A process for planarizing an integrated circuit structure comprising at least one dielectric layer on a silicon substrate, said dielectric layer having openings therein lined with a layer of electrically conductive barrier material and filled with copper filler material, said process consisting essentially of: a) removing, by a chemical mechanical polish (CMP) process step, a portion of the excess copper filler material over the portion of an electrically conductive barrier layer lying on the upper surface of said dielectric layer; b) removing, by an electropolishing process step, the remainder of said excess copper filler material over said portion of said electrically conductive barrier layer lying on said upper surface of said dielectric layer to thereby expose said underlying electrically conductive barrier layer on said upper surface of said dielectric layer; and c) then removing exposed portions of said electrically conductive barrier layer on said upper surface of said dielectric layer in a dry etch reactor using a plasma etching process selective to said copper and said dielectric layer until all of said portions of said electrically conductive barrier layer over said upper surface of said dielectric layer are removed; whereby said integrated circuit structure may be planarized by removal of all of said copper layer and said electrically conductive barrier layer from said upper surface of said dielectric layer while inhibiting dishing and/or erosion of the surface of said copper filler material in said openings dielectric layer.