Patent ID: 7512728

Claim:
An apparatus for inter-chip communication in a logic verification system, comprising: a reconfigurable hardware accelerator configured to evaluate a hardware model of a user design, the reconfigurable hardware accelerator including a first chip configured with a first portion of the hardware model and a second chip configured with a second portion of the hardware model, the first and second chips being coupled through an M-bit wide conductive element; event detection logic in the first chip for detecting at least one changed N-bit signal group of a plurality of N-bit signal groups that changed in value in the first portion of the hardware model and at least one idle N-bit signal group of the plurality of N-bit signal groups that did not change in value in the first portion of the hardware model; transmission logic in the first chip for transmitting, M bits at a time across the M-bit conductive element, only the at least one changed N-bit signal group to the exclusion of the at least one idle N-bit signal group; and reception logic in the second chip for receiving the at least one changed N-bit signal group to the second portion of the hardware model.