Patent ID: 8384163

Claim:
A layout design tool comprising: a pattern storage that stores first to third cell patterns, the first cell pattern having both first n-type and p-type transistors, the second cell pattern having both second n-type and p-type transistors and a deep well below the second n-type and p-type transistors, and the third cell pattern having a cell layout including a well wall that reaches the deep well from a surface of a semiconductor substrate; and a pattern layout unit configured to provide a pattern layout by placing the first and second cell patterns on the semiconductor substrate, placing the first cell pattern in a substrate potential region of the semiconductor substrate, placing the second cell pattern in a plurality of separating well regions of the semiconductor substrate, and placing the third cell pattern in a peripheral region peripheral to the plurality of separating well regions of the semiconductor substrate, wherein the third cell pattern is configured such that a space between at least one of the plurality of separating well regions and the substrate potential region or at least one of the plurality of separating well regions and another of the plurality of separating well regions is formed, wherein the separating well regions have a potential different from the potential of the substrate potential region.