Patent ID: 8531873

Claim:
An SRAM cell comprising: a latch having a supply node, a ground node connected to ground, a storage node Q, and a storage node QB; a gating device with a control node, the gating device being connected to a voltage supply and to the supply node of the latch; and a feedback loop connecting the storage node Q with the control node of the gating device, wherein each one of the storage nodes is connected separately to a respective write circuitry, wherein the feedback loop controls the gating device responsive to writing to the storage node Q and the storage node QB via the write circuitries, such that write contention is weakened; wherein the latch comprises a first inverter comprising an nMOS device and a first pMOS device, the first inverter having a ground node connected to ground and a supply node; and a second inverter, comprising a second nMOS device and a second pMOS device, the second inverter being cross-coupled with the first inverter and having a supply node connected to the supply node of the first inverter, and a ground node connected to ground, wherein both of the inverters have a common storage node Q and a common storage node QB; and wherein the gating device and the feedback loop comprises a pMOS gating device having a gate connected to the Q node of the inverters, a source node connected to the supply nodes of the inverters, and a drain node connected to a supply voltage, wherein in holding a logic ‘0’ at the Q node, the pMOS gating device is configured to conduct such that a voltage level on the supply nodes of the inverters essentially equals the supply voltage, and wherein in holding a logic ‘1’ at the storage node Q, the pMOS gating device is cut-off, such that the voltage level on the supply nodes of the inverters reaches a steady stage voltage of the supply voltage.