Patent ID: 8902902

Claim:
A circuit comprising: a storage device that stores a plurality of multi-bit node control values (NCVs) and a plurality of multi-bit result values (RVs); and a hardware trie structure that receives a multi-bit input value (IV) and that outputs one of the plurality of RVs, wherein the hardware trie structure includes no sequential logic element, and wherein the hardware trie structure comprises: a set of input leads, wherein the hardware trie structure receives the IV in parallel on the set of input leads; a plurality of internal node circuits, wherein each of the internal node circuits receives from the storage device a corresponding respective one of the plurality of NCVs, wherein each of the internal node circuits also receives at least some of the bits of the IV; a plurality of leaf node circuits, wherein each of the leaf node circuits receives from the storage device a corresponding respective one of the RVs; and a set of output leads, wherein the hardware trie structure outputs said one of the plurality of RVs in parallel onto the set of output leads.