Patent ID: 8713239

Claim:
A device that executes split transactions, the device comprising: a host microprocessor; a system memory connected to the host microprocessor, wherein the host microprocessor transfers data to the system memory over a peripheral bus; a Universal Serial Bus (USB) host controller connected to the host microprocessor and the system memory, wherein the USB host controller retrieves the data from the system memory and comprises: an on-chip RAM connected to an interface, the on-chip RAM storing transfer descriptors sent from the host microprocessor, registers that support the RAM, and a host controller logic unit connected by an internal bus to the registers, wherein the USB host controller executes a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across the interface and the transfer involves an amount of data specified by the single transfer descriptor without intervention by the host microprocessor; wherein the single transfer descriptor handles both Start Split (SS) and Complete Split (CS) transactions.