Patent ID: 7943419

Claim:
A method of fabricating a device, comprising the steps of: (a) depositing a first insulating layer onto a first electrode; (b) depositing an electrically conductive layer onto the first insulating layer; (c) creating a patterned mask on top of the first electrically conductive layer by a method comprising the steps of: (i) depositing a monolayer of substantially close-packed particles; (ii) exposing the particles to a process that reduces their size, thereby creating gaps between the particles; (iii) depositing a mask material into the gaps between the particles; and (iv) removing the particles and any mask material deposited thereon; (d) etching the electrically conductive layer and the first insulating layer through the mask to form holes of an average diameter or width of less than about 100 nm to expose portions of the first electrode; (e) depositing an organic semiconductor layer over the exposed portions of the first electrode, first insulating layer, and first electrically conductive layer; and (f) depositing a second electrode over the organic semiconductor layer.