Patent ID: 7415584

Claim:
An interleaver memory configured to interleave an input sequence, the input sequence comprising a set of data samples, the set of data samples including a first subset and second subset of data samples, and to output a sequence of the set of data samples in a permuted order, the interleaver memory comprising: a plurality of memory elements, each element having a storage address for storing a data sample from the set of data samples, wherein the number of memory elements is less than the number of data samples in the set of data samples; and an interleaver controller for, selecting the storage addresses of the plurality of memory elements for storing the set of data samples, transferring the first subset of data samples to the memory elements associated with the determined storage addresses, identifying a first storage address of a memory element which stores a first data sample of the first subset of data samples, reading the first data sample from the first storage address and then writing a data sample belonging to the second subset of data samples to the first storage address, identifying a second storage address of a memory element which stores a second data sample of the first subset of data samples, reading the second data sample from the second storage address and then writing a data sample belonging to the second subset of data samples to the second storage address.