Patent ID: 7115954

Claim:
A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on said one main surface of the semiconductor substrate, which second region is different from the first region, wherein insulating films for self align contact are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof, and wherein the insulating film for self align contact covering the gate electrode of the n channel conductivity type field effect transistor generates a tensile stress in the channel formation region of the n channel conductivity type field effect transistor, while the insulating film for self align contact covering the gate electrode of the p channel conductivity type field effect transistor generates a compressive stress in the channel formation region of the p channel conductivity type field effect transistor.