Patent ID: 8009213

Claim:
An image sensing apparatus comprising: a pixel; and a driving unit which drives the pixel, wherein the pixel includes a photoelectric conversion unit, a charge-voltage converter which converts a signal based on an electric charge accumulated by the photoelectric conversion unit into a voltage, and a transfer MOS transistor which transfers the electric charge accumulated by the photoelectric conversion unit to the charge-voltage converter, wherein the driving unit includes a buffer circuit configured to supply a transfer signal to a transfer control line connected to a gate of the transfer MOS transistor, wherein the buffer circuit includes a first PMOS transistor having a drain connected to the transfer control line, and a source supplied with a power supply voltage V 1 , a first NMOS transistor having a drain connected to the transfer control line and the drain of the first PMOS transistor, and a source supplied with a reference voltage V 2 with a sign opposite to a sign of the power supply voltage V 1 , a second PMOS transistor having a drain connected to the source of the first PMOS transistor, and a source supplied with the power supply voltage V 1 , and a second NMOS transistor having a drain connected to the source of the first NMOS transistor, and a source supplied with the reference voltage V 2 , wherein V 3 is a voltage supplied to a gate of the first NMOS transistor to supply a transfer signal for turning off the transfer MOS transistor to the transfer control line, wherein V 4 is a voltage supplied to a gate of the first PMOS transistor to supply a transfer signal for turning on the transfer MOS transistor to the transfer control line, wherein Vthp 1 is a threshold voltage of the first PMOS transistor, wherein Vthn 1 is a threshold voltage of the first NMOS transistor, wherein V 6 and V 8 are voltages supplied to gates of the second PMOS transistor and the second NMOS transistor to supply a transfer signal for turning off the transfer MOS transistor to the transfer control line, wherein V 5 and V 7 are voltages supplied to gates of the second PMOS transistor and the second NMOS transistor to supply a transfer signal for turning on the transfer MOS transistor to the transfer control line, wherein Vthp 2 is a threshold voltage of the second PMOS transistor, wherein Vthn 2 is a threshold voltage of the second NMOS transistor, and wherein ( V 2+ Vthn 1)< V 3 <V 1 V 2< V 4<( V 1+ Vthp 1) V 2< V 5<( V 1+ Vthp 2)< V 6 and V 7<( V 2+ Vthn 2)< V 8< V 1.