Patent ID: 8549202

Claim:
A method of data processing in a data processing system having a processor core, system memory, and an input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number, the method comprising: the I/O host bridge receiving a message signaled interrupt (MSI) at the I/O host bridge, the MSI including a message address and message data; the I/O host bridge determining, from the message address, a system memory address of a particular entry among a plurality of entries in an interrupt data structure in system memory external to the I/O host bridge, wherein each of the plurality of entries in the data structure is associated with a respective one of a plurality of interrupts, wherein the determining includes: determining an offset by combining bits of the message address and bits of the message data utilizing a logical operation; combining the offset with a base address to obtain the system memory address: the I/O host bridge accessing the particular entry in the system memory external to the I/O host bridge utilizing the system memory address and, based upon contents of the particular entry: validating authorization of an interrupt source to issue the MSI; and presenting an interrupt associated with the particular entry for service.