Patent ID: 8250511

Claim:
A designing apparatus for a semiconductor integrated circuit, the designing apparatus comprising: an initial estimating portion for estimating general values of consumed current and on-chip capacitance of the semiconductor integrated circuit to be designed for placement; a general power supply noise analyzing portion for conducting a power supply noise analysis of the semiconductor integrated circuit as a lumped constant circuit model created based on the estimated general values, setting a total amount of on-chip capacitance so that a power supply noise becomes a value within a predetermined range, and computing a current-capacitance ratio indicating a ratio of the consumed current to the on-chip capacitance based on the estimated general values and the total amount of on-chip capacitance; a layout designing portion for performing placements of a primitive cell and a decoupling capacitance cell in each predetermined region of a plurality of predetermined regions obtained by dividing a placement region of the semiconductor integrated circuit, based on the current-capacitance ratio; a detail estimating portion for estimating detail values of the consumed current and the on-chip capacitance of each of the predetermined regions by creating a lumped constant circuit model of each of the predetermined regions, based on a result of the placements of the primitive cell and the decoupling capacitance cell; a detail power supply noise analyzing portion for conducting a detail power supply noise analysis based on the estimated detail values; and a layout adjusting portion for performing an adjustment of the placements of the primitive cell and the decoupling capacitance cell based on a result of the detail power supply noise analysis.