Patent ID: 7257045

Claim:
An address decoder configured to decode an n-bit address, the address decoder comprising: a plurality of decoder circuits each representing an address slice, wherein each of the decoder circuits includes: a first stage, wherein the first stage includes a first logic circuit having n−1 inputs, wherein the logic circuit is configured to provide a first output signal; and a second stage, wherein the second stage includes a second logic circuit having an input coupled to receive the first output signal and a third logic circuit having an input coupled to receive the first output signal, wherein the second logic circuit is further coupled to receive one of the n−1 bits, and wherein the third logic circuit is further coupled to receive a complement of the one of the n−1 bits, wherein the second logic circuit is configured to provide a second output signal and the third logic circuit is configured to provide a third output signal; wherein the address decoder is configured to assert one of a plurality of address selection outputs by asserting one of the second or third output signals of one of the plurality of decoder circuits, wherein the address selection output corresponds to the n-bit address.