Patent ID: 8081097

Claim:
An analog-to-digital converter for saving power consumption, comprising: a sample and hold unit, coupled to an external differential input signal, for sampling, maintaining and outputting a differential sampling signal according to a sampling frequency signal; a successive control unit, coupled to a calibrating comparator, for outputting a memory address according to a comparing result of the calibrating comparator, and outputting a conversion result upon the completion of the analog-to-digital conversion process; a look-up memory, coupled to the calibrating comparator and the successive control unit, for outputting a digital data to a data port of the calibrating comparator; and a calibrating comparator, comprising: a positive input end, for receiving a positive polarity signal of the differential sampling signal; a negative input end, for receiving a negative polarity signal of the differential sampling signal; a timing signal input end, for receiving a clock signal; a data port, for receiving a digital data; a latch unit, comprising a first comparing end, a second comparing end, a first output end and a second output end, and is utilized to compare the magnitude of a circuit parameter observed respectively in the first comparing end and the second comparing end, such that the state values of the first output end and the second output end can both be determined; an enable switch, comprising a first end, a second end coupled to the timing signal input end, and a third end coupled to a ground end, for controlling the conductions between the first end and the third end according to the magnitude of the clock signal; a first controllable resistor, coupled to the positive input end, the first comparing end of the latch unit and the first end of the enable switch, for regulating the resistance of the first controllable resistor according to the positive polarity signal of the differential sampling signal; a second controllable resistor, coupled to the negative input end, the second comparing end of the latch unit and the first end of the enable switch, for regulating the resistance of the second controllable resistor according to the negative polarity signal of the differential sampling signal; a reset switch assembly, coupled to the timing signal input end and the latch unit, for resetting the state of the latch unit according to the clock signal; a controllable capacitive device, coupled to the first comparing end and the second comparing end of the latch unit and the ground end, for controlling the observed capacitance in the first comparing end and the second comparing end; and an output end, coupled to the first output end of the latch unit, for outputting a comparing result.