Patent ID: 7589945

Claim:
An integrated circuit comprising: a first voltage reference bus comprising a first terminating end and a second terminating end; a second voltage reference bus; a plurality of input/output (I/O) cells distributed along a length of the first voltage reference bus and comprising: a first subset of I/O cells disposed proximal to one of the first terminating end or the second terminating end of the first voltage reference bus; and a second subset of I/O cells disposed distal from the first terminating end and the second terminating end of the first voltage reference bus; and wherein each of the first subset of the I/O cells comprises a first electrostatic discharge (ESD) clamp transistor device, the first ESD clamp transistor device comprising a current electrode coupled to the first voltage reference bus and a current electrode coupled to the second voltage reference bus, wherein the first ESD clamp transistor device comprises a first channel width; and wherein each of the second subset of the I/O cells comprises a second ESD clamp transistor device comprising a current electrode coupled to the first voltage reference bus and a current electrode coupled to the second voltage reference bus, wherein the second ESD clamp transistor device comprises a second channel width, and wherein the second channel width is less than the first channel width.