Patent ID: 7656237

Claim:
An apparatus, comprising: a system logic unit coupled to receive a clock (CLK) signal and a power save mode acknowledge (PSM_ACK) signal, wherein the PSM_ACK signal is asserted in a power saving mode, and wherein the system logic unit is configured to perform a function dependent upon the CLK signal and to produce a phased lock loop disable (PLL_DISABLE) signal in response to the PSM_ACK signal; enable logic coupled to receive the PSM_ACK signal and the PLL_DISABLE signal, and configured to produce a phased lock loop enable (PLL_EN) signal dependent upon the PSM_ACK signal and the PLL_DISABLE signal; a phased locked loop (PLL) unit coupled to receive the PLL_EN signal and a reference clock (REF_CLK) signal, and configured to use the REF_CLK signal to produce a phased lock loop output (PLL_OUT) signal responsive to the PLL_EN signal; a lock detector unit coupled to receive the PLL_OUT signal and configured to produce a LOCK signal dependent upon the PLL_OUT signal; and transmission logic coupled to receive the LOCK signal and the PLL_OUT signal, and configured to produce the PLL_OUT signal as the CLK signal dependent upon the LOCK signal.