Patent ID: 8432191

Claim:
A dual-path phase-locked loop (PLL), comprising: PLL loop circuitry comprising proportional path circuitry and integrating path circuitry, the proportional path circuitry operating in response to a first Up signal and a first Down signal, the integrating path circuitry operating in response to a second Up signal and a second Down signal, the PLL loop circuitry providing a PLL output signal and a feedback signal in response to an output of the proportional path circuitry and an output of the integrating path circuitry; and a phase-frequency detector (PFD) providing the first Up signal, first Down signal, second Up signal and second Down signal in response to a reference clock signal and the feedback signal; wherein the first Up signal is defined by a first Up pulse having a first Up starting edge triggered by a reference clock signal edge and having a first Up ending edge triggered by a combination of the Up signal asserted and the Down signal asserted, and the first Down signal is defined by a first Down pulse having a first Down starting edge triggered by a feedback signal edge and having a first Down ending edge triggered by a combination of the Up signal asserted and the Down signal asserted; and wherein when the reference clock signal edge leads the feedback signal edge the second Up signal is defined by a second Up pulse having a second Up starting edge triggered by the reference clock signal edge and having a second Up ending edge triggered by another feedback signal edge following the feedback signal edge, and when the feedback signal edge leads the reference clock signal edge the second Down signal is defined by a second Down pulse having a second Down starting edge triggered by the feedback signal edge and having a second Down ending edge triggered by another reference clock signal edge following the reference clock signal edge.