Patent ID: 7902589

Claim:
An array of memory cells arranged in columns and at least one row on a semiconductor substrate, the array comprising: each memory cell having a drain region, a source region and only two gates consisted of a first gate and a second gate located between the drain region and the source region and a separation is located between the first gate and the second gate; a plurality of gate control lines, each of which corresponds to one of the columns of the array of memory cells, wherein each control line connects to the first gate of the memory cell in the corresponding column in each of the at least one row; and at least one word line, each of which corresponds to one of the at least one row of the memory cells, each word line connected to the second gate of each of the memory cells in the corresponding row, wherein the first gate is above and contacts a first dielectric layer, the first dielectric layer is above and contacts a first charge storage region on the substrate, the second gate is above and contacts a second dielectric layer, the second dielectric layer on the substrate is above and contacts a second charge storage region.