Patent ID: 8298889

Claim:
A process of forming an electronic device comprising: providing a workpiece including a first layer, a well region, and a buried doped region, wherein: the first layer has a primary surface; the well region lies adjacent to the primary surface; and the buried doped region is spaced apart from the primary surface and the well region; forming a first insulating layer over the primary surface; forming a second insulating layer over the first insulating layer, wherein the second insulating layer has a different composition as compared to the first insulating layer; forming a trench extending through the well region and towards the buried doped region, wherein: forming the trench is performed after forming the first and second insulating layers; and a portion of the well region and a portion of the first layer lie along a sidewall of the trench; doping the portion of the first layer along the sidewall of the trench after forming the trench to form a sidewall doped region along the sidewall and below the well region, wherein: a dopant for the sidewall doped region is introduced into the first layer along the sidewall of the trench, wherein the dopant has a conductivity type that is the same as the well region and opposite that of the first layer; doping the portion of the first layer along the sidewall of the trench is performed using the dopant; and doping the portion of the first layer comprises performing a tilt angle implant; and forming an insulating sidewall spacer along the sidewall of the trench; forming a conductive structure within the trench after forming the insulating sidewall spacer, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region, wherein the electronic device comprises a transistor that includes a channel region within the well region.