Patent ID: 7586806

Claim:
A method of controlling a voltage level supplied to a static random access memory (“SRAM”), comprising: a) supplying power to cells of the SRAM at a power supply voltage level through a first transistor having a conduction path between a power supply input and a power supply output; b) selecting a column of the SRAM for writing; c) operating a second transistor to reduce a voltage at the power supply output to cells belonging to the selected column to a lower voltage level lower than the power supply voltage level, wherein a rate of reduction of the voltage at the power supply output slows as that voltage approaches a voltage at which the second transistor turns off; d) while supplying the power at the lower voltage level, writing a cell belonging to the selected column; and e) operating the first and second transistors to again supply the power at the power supply voltage level to the cells belonging to the first column.