Patent ID: 6996515

Claim:
A method for verifying a minimal level sensitive timing abstraction model, comprising: extracting a plurality of parameters from a modeled circuit that includes sequential elements controlled by internally generated clock signals; creating an echo-circuit that represents the plurality of parameters with nodes and time arcs, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and is used in any static timing analysis (STA) tools, wherein the echo-circuit includes a dummy latch node that is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from an input port to an output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port; identifying relevant timing paths in the echo-circuit, wherein the relevant timing paths are associated with the plurality of parameters; identifying paths in the modeled circuit that connect sequential elements and correspond to the relevant timing paths in the echo-circuit; and comparing the relevant timing paths in the echo-circuit with the corresponding paths in the modeled circuit.