Patent ID: 8748256

Claim:
A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor), comprising: forming an dielectric isolation region in a top semiconductor surface of a substrate; forming a polysilicon layer including a patterned polysilicon resistor disposed entirely on said dielectric isolation region and gate polysilicon on a gate dielectric on said top semiconductor surface; implanting using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting said patterned polysilicon resistor and said gate polysilicon of a MOS transistor with at least a first dopant; then, patterning said gate polysilicon to form a polysilicon transistor gate; then, implanting using a second shared MOS/resistor polysilicon implant level for simultaneously implanting said patterned polysilicon resistor, said gate polysilicon, and source and drain regions of said MOS transistor with at least a second dopant, and forming a metal silicide on a first and second portion of a top surface of said patterned polysilicon resistor to form said SIBLK poly resistor.