Patent ID: 8705552

Claim:
An apparatus configured to reduce delay jitter of a stream of packets passing through the apparatus, the apparatus comprising: a packet ingress interface configured to ingress the stream of packets into the apparatus; a timestamp module configured to respectively generate a timestamp for each packet of the stream of packets, wherein the timestamp for each packet corresponds to a time that the packet ingressed the apparatus through the packet ingress interface; a packet egress interface configured to egress the stream of packets from the apparatus; an eligible egress time module configured to set a predetermined time interval to hold each packet of the stream of packets to a difference between (i) a first amount of time required by the apparatus to receive a maximum-sized packet and (ii) a second amount of time required by the apparatus to receive a minimum-sized packet, wherein the predetermined time interval to hold each packet of the stream of packets remains constant for each packet of the stream of packets, and reduce the delay jitter among the stream of packets by determining a respective eligible time for each packet of the stream of packets to egress from the apparatus via the packet egress interface, wherein the respective eligible time for each packet to egress from the apparatus is based on (i) the time that the packet ingressed the apparatus through the packet ingress interface as indicated by the timestamp corresponding to the packet, and (ii) the predetermined time interval set to hold the packet; and an egress module to prevent each packet from egressing the packet egress interface until occurrence of the respective eligible time determined for the packet.