Patent ID: 7045420

Claim:
A method of fabricating a semiconductor device including a memory cell region and a peripheral circuit region, comprising steps of: forming an insulating film having an upper surface on a major surface of a semiconductor substrate to extend from said memory cell region to said peripheral circuit region; partially removing said insulating film by etching in said memory cell region thereby forming an opening; forming a capacitor lower electrode in said opening on said major surface of said semiconductor substrate; and forming a capacitor upper electrode on said capacitor lower electrode through a dielectric film to extend onto said upper surface of said insulating film, wherein said step of forming said capacitor lower electrode includes a step of forming a capacitor lower electrode part upwardly extending in opposition to said capacitor upper electrode and having a top surface and a bottom surface, said step of forming said insulating film includes a step of locating said upper surface of said insulating film between said top surface and said bottom surface of said capacitor lower electrode part, said step of forming said insulating film includes steps of: forming a lower insulating film, and forming an upper insulating film being different in etching rate from said lower insulating film on said lower insulating film, and said step of locating said upper surface of said insulating film between said top surface and said bottom surface of said capacitor lower electrode part includes a step of removing said upper insulating film.