Patent ID: 7855442

Claim:
A silicon based package (SBP) comprising: an ultra thin silicon wafer (UTSW) composed of silicon and having a first surface of silicon and a reverse surface; metal capture structures each having a first surface formed directly on the first surface of silicon of the UTSW and an exposed surface; an interconnection structure formed over the first surface of the UTSW and the exposed surface of the metal capture structures; vertical sidewall through via (VSTV) holes formed in the SBP with hole sidewalls that extend from the reverse surface through the UTSW to the first surface of the metal capture structures; a layer of dielectric material covering at least the sidewalls of the VSTV holes leaving at least a portion of the first surface of the metal capture structures exposed; and ball limiting metallurgy (BLM) comprising a layer of metal covering the exposed portion of the metal capture structures and the layer of dielectric material on the sidewalls of the VSTV holes to form metal lined sidewalls in the VSTV holes which metal lined sidewalls extend through the UTSW into contact with the layer of metal covering the exposed portion of the metal capture structures to form a metal lined recessed via pad structure in the UTSW extending to the metal capture structures to allow solder ball contact with the metal lined sidewalls and the layer of metal covering the exposed portion of the metal capture structures.