Patent ID: 8174883

Claim:
A semiconductor memory device comprising: a memory cell array connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number of 4 or more) in one memory cell are arrayed in a matrix; and a control circuit configured to control a potential of the word line and the bit line in accordance with input data, and writing data in the memory cell, wherein the control circuit performs a operation which applies a write voltage corresponding to data written to the memory cell, for every write data, and wherein the control circuit executes a verify operation for each write data after a write voltage application operation ends with respect to all n levels or to data of a predetermined unit, and wherein the control circuit writes first and second write data (first write data<second write data) lower than a target level, and thereafter, simultaneously writes third write data (third write data<first write data) and the first and second write data, and executes a verify operation for each third, first and second write data after the write operation ends.