Patent ID: 7564664

Claim:
An ESD protection circuit, coupled to at least a first and a second signal transmission line and a positive and a negative supply voltage of an integrated circuit, comprising: at least a first and a second high-frequency transmission line, the first high-frequency transmission line having a first end connected to the first signal transmission line and the second high-frequency transmission line having a first end coupled to the second signal transmission line; and at least one ESD-element connected between second ends of the first and second high-frequency transmission lines and either one of the positive or negative supply voltages such that the first and second high-frequency transmission lines are each connected in series with the ESD-element and dimensioned in such a way that, at a predetermined high-frequency of a signal of the integrated circuit, an impedance of a current-path formed by the first high-frequency transmission line and the at least one ESD-element and a current path formed by the second high-frequency transmission line and the ESD-element are transformed compared with a system impedance, from a low impedance to a very high impedance.