Patent ID: 6970336

Claim:
An integrated circuit comprising: a first bus; a second bus; a third bus; a fourth bus; a shunting circuit including a plurality of transistors in a stacked configuration, the shunting circuit having a plurality of control terminals, a first current terminal coupled to the first bus, a second current terminal coupled to the second bus, and an intermediate terminal coupled to the fourth bus, wherein the shunting circuit is made conductive to provide a discharge path from the first bus to the second bus for current from an electrostatic discharge (ESD) event; a trigger circuit having a first output coupled to a first control terminal of the plurality of control terminals of the shunting circuit to provide a first control signal and having a second output coupled to a second control terminal of the plurality of control terminals of the shunting circuit to provide a second control signal, the trigger circuit is coupled to the third bus; and a pad, the pad coupled to the first bus, the second bus, and the third bus.