Patent ID: 7236387

Claim:
A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising: applying a ground potential to a first word line coupled to a control gate of the selected memory cell; applying a fraction of a programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell; and applying the fraction of the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.