Patent ID: 8782570

Claim:
A computer implemented method for implementing a physical electronic circuit design with multiple-patterning techniques, comprising: using at least one processor or at least one processor core to perform a process the process comprising: identifying a constraint for multiple mask designs of a multiple-patterning lithography process for manufacturing the electronic design; coloring a first plurality of routing tracks in the electronic design with a first number of colors; coloring one or more fixed objects in the electronic design with at least one color of the first number of colors based at least in part upon a result of coloring the first plurality of routing tacks with the first number of colors; and improving or resolving a color conflict in the electronic design based at least in part upon a characteristic of at least a part of an object that exhibits the color conflict with at least one of another object, wherein the characteristic comprises a one-dimensional size or a two-dimensional size of the at least the part of the object.