Patent ID: 7656221

Claim:
A booster circuit comprising: a pump circuit having a plurality of charge pump circuits that boost a voltage supplied from a power supply and output the boosted voltage to a first output terminal and having a clock adjusting circuit that generates a second clock signal for operating said charge pump circuits from a first clock signal; a pump controlling circuit that outputs the first clock signal for operating said pump circuit to control the operation of said pump circuit; a first variable resistor connected to said first output terminal at one end thereof; a second variable resistor connected to the other end of said first variable resistor at one end thereof; a third variable resistor connected to the other end of said second variable resistor at one end thereof; a limiter circuit that is connected between the other end of said third variable resistor and a ground potential, composed of a variable resistor, and capable of adjusting a current flowing through said first variable resistor, said second variable resistor and said third variable resistor; a first comparator that receives a first monitor voltage at said the other end of said first variable resistor at the inverting input terminal thereof and a reference voltage at the non-inverting input terminal thereof, and outputs a first output signal; a second comparator that receives a second monitor voltage at said the other end of said second variable resistor at the inverting input terminal thereof and said reference voltage at the non-inverting input terminal thereof, and outputs a second output signal; and a third comparator that receives a third monitor voltage at said the other end of said third variable resistor at the inverting input terminal thereof and said reference voltage at the non-inverting input terminal thereof, and outputs a third output signal; wherein said pump controlling circuit: controls said pump circuit to reduce number of active charge pump circuits according to the first output signal of said first comparator when said first comparator determines that the first monitor voltage is higher than said reference voltage, controls said pump circuit to reduce a frequency of the second clock signal for operating the active charge pump circuits by reducing a frequency of said first clock signal according to the second output signal of said second comparator when said second comparator determines that the second monitor voltage is higher than said reference voltage, and brings said pump circuit into the inactive state according to the third output signal of said third comparator when said third comparator determines that the third monitor voltage is higher than said reference voltage.