Patent ID: 8381159

Claim:
A design method of a semiconductor integrated circuit for arranging a repeater between a start point logic cell and an end point logic cell, the method comprising a processor programmed to: setting an area having apices of opposing corners of a position of the start point logic cell and a position of the end point logic cell to a repeater search area; adding free area information of a free area where a repeater can be arranged to the repeater search area; setting a drive boundary in the repeater search area based on a drive ability of the start point logic cell, the drive boundary being a boundary of an area in which the start point logic cell is able to drive a wiring load; searching a repeater candidate that can be arranged in an area of the drive boundary based on the free area information; calculating a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched; determining a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated; setting the position of the repeater candidate that is searched to a start point; resetting an area having apices of opposing corners of the position of the start point and the position of the end point logic cell to a repeater search area; adding again free area information of a free area where a repeater can be arranged to the repeater search area that is reset; resetting a drive boundary in the repeater search area that is reset based on a drive ability of the repeater candidate which is the start point, the drive boundary being a boundary of an area in which the repeater candidate which is the start point is able to drive a wiring load; and searching again a repeater candidate that can be arranged in the area of the drive boundary that is reset based on the free area information.