Patent ID: 7612419

Claim:
A wafer comprising: a plurality of scribe lines comprising: a plurality of first scribe lines extending in a first direction having a first width; a plurality of second scribe lines extending in the first direction having a second width greater than the first width; a plurality of third scribe lines extending in a second direction different from the first direction having the first width; a plurality of fourth scribe lines extending in the second direction having the second width; and semiconductor chips each of which is formed in an area defined by the plurality of scribe lines; wherein: the semiconductor chips are arranged in a plurality of unit cells, each unit cell containing only one of the second scribe lines and only one of the fourth scribe lines, wherein the relative position of each semiconductor chip within the unit cell is uniquely defined by the shapes of the scribe lines on the periphery of each semiconductor chip, the second scribe lines comprise at least either a first alignment mark or a first TEG (Test Element Group) comprising at least one first check transistor and the fourth scribe lines comprise at least either a second alignment mark or a second TEG (Test Element Group) comprising at least one second check transistor, the at least one first transistor has a rectangular shape and is arranged in a way such that the length direction of the first check transistor is substantially parallel to the first direction, and the at least one second check transistor has a rectangular shape and is arranged in a way such that the longer side length direction of the second check transistor is orthogonal to the first direction.