Patent ID: 8310852

Claim:
A content addressable memory comprising: a plurality of entries each having a plurality of content addressable memory cells; a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry; a search data bus coupled in parallel to the entries and transferring search data in parallel to the entries; and a plurality of match amplifiers, arranged corresponding to the respective match lines, each including (i) a precharge circuit for precharging a reference voltage node and a corresponding match line to a precharge voltage level, (ii) an amplifier circuit having a first node receiving a voltage on the corresponding match line and a second node coupled to said reference voltage node, comparing the voltages on the first and second nodes, and producing a signal indicating a result of comparison, (iii) an isolation gate for isolating the corresponding match line and said reference voltage node from the first and second nodes of said amplifier circuit before activation of said amplifier circuit, respectively, and (iv) a capacitance element for boosting said first node according to a boost instructing signal before the activation of said amplifier circuit after isolation by said isolation gate.