Patent ID: 7639227

Claim:
A reduced swing differential signaling circuit for providing odd output voltages simultaneously, comprising: a first PMOS transistor having a source coupled to a power line and a drain coupled to a first bias end of a first inversion unit; a second PMOS transistor having a source coupled to the power line and a drain coupled to a first bias end of a second inversion unit; a third PMOS transistor having a source coupled to the power line and a drain coupled to a first bias end of a third inversion unit; a first NMOS transistor having a source coupled to a ground line, a drain coupled to a second bias end of the first inversion unit and to a gate of the third PMOS transistor, and a gate coupled to the drain of the third PMOS transistor; a second NMOS transistor having a source coupled to the ground line, a drain coupled to a second bias end of the second inversion unit and to a gate of the second PMOS transistor, and a gate coupled to the drain of the second PMOS transistor; and a third NMOS transistor having a source coupled to the ground line, a drain coupled to a second bias end of the third inversion unit and to a gate of the first PMOS transistor, and a gate coupled to the drain of the first PMOS transistor; wherein the first, second, and third inversion units provide the odd output voltages at corresponding output ends.