Patent ID: 7551985

Claim:
A method of optimizing power consumption for a design of an integrated circuit including a plurality of power domains, comprising: obtaining estimates of timing slack of respective paths internal to respective power domains of the integrated circuit design, based on respective initial power domain power supply voltages; obtaining estimates of timing slack of respective paths external to the respective power domains of the integrated circuit design, based on the respective initial power domain power supply voltages, such paths going from respective first power domains to respective second power domains; obtaining a model of changes in the timing slack estimates as a first function of incremental changes in the power domain power supply voltages; wherein the model of changes includes respective estimates of changes of timing slack of the respective internal paths of the respective power domains as a second function of the incremental changes in such respective power domain power supply voltages; and wherein the model further includes respective estimates of changes of timing slack of the respective external paths, as a third function of incremental changes in respective power domain power supply voltages of respective first power domains and respective second power domains at opposite ends of such respective external paths; and using the module to arrive at assignments of power domain power supply voltages the provide optimal overall power consumption of the integrated circuit and that meet timing requirements.