Patent ID: 8446196

Claim:
An input interface circuit comprising: an input first stage circuit that is connected to a signal terminal, the signal terminal receiving external data; and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, the latch timing signal being output to a latch circuit included in the input first stage circuit, wherein the phase adjustment circuit adjusts a delay time of the latch timing signal that passes through a clock tree circuit and is supplied to the latch circuit in response to a comparison result between the external input clock and an output from a replica delay circuit which is replicated from the external input clock, wherein the phase adjustment circuit comprises: a delay adjustment circuit that adjusts a delay time of the external input clock; a replica clock tree circuit that receives the external input clock having the delay time adjusted by the delay adjustment circuit, the replica clock tree circuit being a replica of the clock tree circuit; a phase comparator that compares an output result from the replica clock tree circuit and a phase of the external input clock; a delay adjustment control circuit that adjusts an amount of delay of the delay adjustment circuit in response to a comparison result by the phase comparator; and a multiplexer that receives the external input clock and an inverted signal of the external input clock, and outputs a selected signal to the delay adjustment circuit, and wherein the delay adjustment control circuit controls the multiplexer in response to the comparison result by the phase comparator.