Patent ID: 8860207

Claim:
A semiconductor package, comprising: a portion of a reconstituted wafer, including a molding compound layer and a semiconductor die having a plurality of circuit pads positioned on a face of the semiconductor die, the semiconductor die being substantially embedded in the molding compound layer with the face of the semiconductor die lying coplanar with a face of the molding compound layer; and a redistribution layer positioned on the face of the portion of the reconstituted wafer and having: a plurality of electrical traces in electrical contact with respective ones of the plurality of circuit pads, a plurality of contact lands defined on a face of the wafer portion, each electrically coupled to a respective one of the plurality of circuit pads via a corresponding one of the plurality of electrical traces, and a heat spreader positioned over the semiconductor die and lying in a same layer of the redistribution layer as the plurality of electrical traces, the heat spreader being electrically isolated from the semiconductor die and substantially covering a majority of the face of the semiconductor die.