Patent ID: 8533522

Claim:
An integrated circuit comprising: an edge detector circuit configured to receive a first clock signal and provide a second clock signal having a frequency twice a frequency of the first clock signal to an edge detector output; a multiplexer circuit in communication with the edge detector and configured to: receive rising edge data having a data rate corresponding to the frequency of the first clock signal at a first input, receive falling edge data having a data rate corresponding to the frequency of the first clock signal at a second input, and selectively provide one of the data received at the first input and the second input to a multiplexer output based on a selection signal received at a selection input; and an edge triggered flip-flop including: a data input in communication with the multiplexer output, a clock input in communication with the edge detector output, and a flip-flop output; the edge triggered flip-flop configured to provide data received at the data input and latched on edges of a clock received at the clock input on the flip-flop output.