Patent ID: 7741210

Claim:
A method of forming conductive interconnects in integrated circuitry comprising multilevel metal routing layers, comprising: forming a node of a circuit component on a substrate; forming a conductive metal line at a first metal routing level that is elevationally outward of the circuit component; depositing insulative material above the first metal routing level over the conductive metal line and the circuit component; etching a first opening through the insulative material to the conductive metal line and etching a second opening through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line, the etching of the first and second openings using at least one shared masking step wherein outlines of both of the first and second openings are being defined; concurrently depositing conductive material to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component; and forming a first metal line at a second metal routing level that is above the first metal routing level in conductive connection with the conductive material in the first opening and forming a second metal line at the second metal routing level in conductive connection with the conductive material in the second opening.