Patent ID: 7776633

Claim:
A method of manufacturing a thin film transistor array panel, comprising: forming gate lines including pads provided so as to be connected to another layer or an external device on a substrate; forming a gate insulating layer on the gate lines; forming semiconductor layers on the gate insulating layer; forming data lines including pads for connection to another layer or an external device, and drain electrodes on the semiconductor layers; depositing a passivation layer on the data lines and the drain electrodes; forming a first photoresist layer including a first portion and a second portion that is thinner than the first portion on the passivation layer; forming a first preliminary contact hole exposing the data lines by etching the passivation layer by using the first photoresist layer as a mask; removing the second portion of the first photoresist; forming a first contact hole by expanding the first preliminary contact hole and opening portions by etching the passivation layer by using the first portion of the first photoresist layer as a mask; depositing a conductor layer; and forming pixel electrodes in the opening portions and a first contact assistant member in the first contact hole by removing the first photoresist layer and the conductor layer located thereon.