Patent ID: 8378429

Claim:
A memory cell comprising: N transistors comprising at least one pair of access transistors, at least one pair of pull-down transistors, and at least one pair of pull-up transistors, said N transistors arranged to form a memory cell, wherein N is an integer at least equal to six; wherein each of the said access transistors and each of the said pull-down transistors is a same one of an n-type or a p-type transistor, and each of the said pull-up transistors is the other of an n-type or a p-type transistor; wherein each of the said access transistors comprises a floating body device and each of the said pull-down transistors comprises a non-floating body device; wherein each of said pull-up transistors comprises a floating body device; and wherein each of the access transistors comprises a first partially-depleted silicon layer body having thickness about 50 nm or more that overlies an insulating layer, and each of the pull-down transistors comprises a second fully-depleted silicon layer body having thickness about 25 nm or less that overlies the insulating layer.