Patent ID: 8081538

Claim:
A circuit for generating an output enable signal, comprising: a reset signal generation section configured to synchronize an output enable reset signal with a first clock signal and generate a DLL clock counter reset signal; a DLL clock counting section configured to be reset in response to the DLL clock counter rest signal and count the first clock signal starting from an initial counting value; a delay model section configured to delay the DLL clock counter reset signal by a modeled time and output an external clock counter reset signal in sync with a second clock signal; an external clock counting section configured to be reset in response to the external clock counter reset signal and count the second clock signal; a latching section configured to latch an output value of the external clock counting section in response to a read command; a comparison section configured to compare an output value of the DLL clock counting section and an output value of the latching section and output an output enable signal; and a clock control section configured to be inputted with a DLL clock signal and an external clock signal and inactivate the first clock signal corresponding to the DLL clock signal and the second clock signal corresponding to the external clock signal in response to an activation signal that is activated in a write operation.