Patent ID: 8411812

Claim:
A memory device comprising: a delay locked loop; and an input pad capable of receiving an external clock signal for routing to the delay locked loop, and the delay locked loop being configured to synchronize an internal clock signal with the external clock signal, the delay locked loop comprising: a digital delay circuit configured to enable digital delay elements of the digital delay circuit in providing coarse phase adjustment in the delay locked loop; an analog delay circuit configured to provide fine phase adjustment in the delay locked loop in response to a control signal; a phase detector circuit configured to compare the external clock signal and the internal clock signal; and a lock detector circuit in communication with the phase detector circuit and the analog delay circuit, the lock detector circuit being configured to detect a condition signal resulting from an internal clock signal rising edge occurring after a rising edge of the external clock signal, and the lock detector circuit being further configured to detect another condition signal resulting from the internal clock signal rising edge occurring after a falling edge of the external clock signal, and in response to the lock detector circuit detecting that the condition signal and the another conditional signal are present, the lock detector circuit being further configured to: i) hold the digital delay circuit at a fixed delay; and ii) provide the control signal to the analog delay circuit.