Patent ID: 7420278

Claim:
A semiconductor device comprising: a semiconductor substrate; a first layer on the semiconductor substrate, wherein the first layer includes a first insulation film and a gate electrode; a plurality of second layers on the first layer, wherein each of the second layers includes a second insulation film, a first dummy metal wiring and a plurality of first dummy metal via patterns, wherein the second insulation film has a dielectric constant of less than 2.7, wherein the first dummy metal wiring and the plurality of first dummy metal via patterns are formed in the second insulation film and wherein each of the first dummy metal via patterns has a top which contacts with a bottom of the first dummy metal wiring; a third layer on the plurality of second layers, wherein the third layer includes a third insulation film, a first metal wiring and a plurality of first metal via patterns, wherein the third insulation film has a dielectric constant of more than 2.7, wherein the first metal wiring and the plurality of first metal via patterns are formed in the third insulation film, and wherein each of the first metal via patterns has a top which contacts with a bottom of the first metal wiring; and a fourth layer on the third layer, wherein the fourth layer includes a pad electrode, a passivation film and an opening, wherein the pad electrode includes an aluminum material and electrically connects to the first metal wiring, wherein the passivation film includes SiN and covers over the pad electrode and the third layer, and wherein the opening opens the passivation film to expose a part of the pad electrode, wherein the first dummy metal wiring, the plurality of first dummy metal via patterns, the first metal wiring and the plurality of the first metal via patterns are formed below the pad electrode in cross sectional view, and wherein each of the plurality of the first metal dummy via patterns is formed in a stripe shape along in first direction in plan view.