Patent ID: 8890289

Claim:
A semiconductor device comprising: a substrate; a multilayer wiring layer which is located over the substrate and in which a plurality of wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has at least one capacitance element and a peripheral circuit embedded in a concave part located in the multilayer wiring layer in a plan view; a logic circuit which is formed in a logic circuit region in the substrate being a different region from the memory circuit region in a plan view; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode in the concave part, wherein the concave part is configured by a hole in which the capacitance element is embedded, and a wiring groove which is continuously located outside of the hole and in which the upper part coupling wiring is embedded, the upper part coupling wiring contacting the upper electrode part both in the wiring groove and in a lower region of the hole; and a cap layer which is located so as to contact to an upper surface of the wiring configuring the logic circuit located in a top layer among the wiring layers in which the capacitance element is embedded; wherein an upper surface of the upper part coupling wiring and an upper surface of the cap layer configure the same plane.