Patent ID: 7091795

Claim:
An integrated circuit, comprising: a terminal that receives a first clock signal of a first frequency; a processor having a clock input lead; and a frequency-locked-loop (FLL) circuit that receives the first clock signal from the terminal and generates therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the FLL circuit comprises a digital filter and a ramp generator, wherein the FLL circuit locks a first signal to a second signal, wherein the ramp generator generates a ramp signal that has a first slope beginning at a first edge of the first signal, wherein at a first edge of the second signal the FLL circuit determines a first digital value indicative of a first magnitude of the ramp signal, wherein the ramp signal has a second slope beginning at a second edge of the first signal, wherein at a second edge of the second signal the FLL circuit determines a second digital value indicative of a second magnitude of the ramp signal, wherein the first digital value and the second digital value are used to generate a third digital value, and wherein the third digital value is supplied to the digital filter.