Patent ID: 7843239

Claim:
A phase locked loop (PLL) comprising: a selection signal generator configured to output a selection signal varying in response to a first clock signal; a first dividing circuit configured to divide an input clock signal by first division ratio and output a first division signal, the first dividing circuit configured to select one of a plurality of edges of the input clock signal applied during at least one cycle of the first division signal in response to the selection signal, and to synchronize and generate the first division signal on the basis of the selected edge of the input clock signal; a second dividing circuit configured to receive an output clock signal, divide the output clock signal by second division ratio, and output a second division signal, the second dividing circuit configured to select one of the edges of the output clock signal applied during at least one cycle of the second division signal in response to the selection signal, and to synchronize and generate the second division signal on the basis of the selected edge of the output clock signal; and a synchronous signal output portion configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage.