Patent ID: 8418100

Claim:
A method for performing a robust scan synthesis for soft-error resilience or soft-error correction on a design for generating a robust scan design in a system; the design modeled selectively at a register-transfer level (RTL) or a gate level; the design including at least a sequential element or a scan cell for mapping to a robust scan cell; the method comprising the computer-implemented steps of: (a) compiling, by using a computer, the design modeled at the RTL or the gate level into a design database; (b) accepting a given control information file from an external source; (c) performing a scan replacement on the design database based on the given control information file for replacing the sequential element or the scan cell with the robust scan cell; (d) performing a scan stitching on the design database based on the given control information file for stitching the robust scan cell on the design database; (e) performing a scan verification after the scan stitching for generating testbenches to verify whether the robust scan design meets the design's functional and timing requirements; and (f) generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.