Patent ID: 6928025

Claim:
A synchronous integrated memory for holding data and to be connected to an external clock producing an external clock signal, the memory comprising: a data connection; an output control connection carrying an output control signal having output levels including a given level; a control unit outputting a first internal clock signal to lead an external clock signal by a given phase shift, said first internal clock signal having first signal levels including said given level; a clock generator generating a second internal clock signal synchronized to the external clock signal and having second levels including said given level; a counting unit having an activation connection carrying an activation signal defining an activated state; said counting unit starting a counting process for recording a number of successively following given levels of said first internal clock signal as soon as said second internal clock signal for a first time assumes said given level while said output control signal is at said given level, an output circuit connected to said activation connection, said activated state starting an output process for reading data out of the memory in synchronism with said first internal clock signal; said output circuit outputting the data at said data connection with said given phase shift with respect to said first internal clock signal and in synchronism with the external clock signal; and said counting unit activating said output circuit through said activation connection as soon as said number of successively following given levels of said first internal clock signal has reached a predetermined value.