Patent ID: 7317363

Claim:
A frequency synthesizer comprising: a phase locked loop circuit which receives a reference signal having a reference frequency and a first signal having a first frequency, compares phases of the reference signal and the first signal, applies a control voltage based on a phase comparison result to an input terminal of a voltage controlled oscillator to generate a second signal having an oscillation frequency, outputs the second signal from an output terminal, and supplies the second signal to a divider to divide the oscillation frequency of the second signal and output the first signal; a controller which generates and supplies a control signal to the voltage controlled oscillator; a voltage comparator which receives a reference voltage, compares the reference voltage with the control voltage applied to the voltage controlled oscillation circuit, and supplies a voltage comparison result to the controller, wherein on the basis of the voltage comparison result, the controller generates the control signal such that the control voltage and reference voltage are equal, and supplies the control signal to the voltage controlled oscillator; and wherein the voltage controlled oscillator has an arrangement in which a coil and variable capacitance are connected in parallel between the input terminal and output terminal, one of a plurality of capacitances is selectively connected between the input terminal and output terminal by a switch in parallel with the variable capacitance, between the input terminal and output terminal, the coil having two ends connected in series, the variable capacitance having two ends connected in series, and, as the plurality of capacitances and the switch: a first capacitance unit in which a first capacitance and first switch are connected in series, a second capacitance unit in which a second capacitance and second switch are connected in series, and . . . an nth (n is an integer of not less than 2) capacitance unit in which an nth capacitance and nth switch are connected in series, wherein the first capacitance unit, the second capacitance unit, . . . and the nth capacitance unit are connected in parallel with each other, ON/OFF of each of the first, second, . . . , nth switches is controlled by the control signal, and each of the first, second, . . . , nth capacitances is formed by a gate capacitance present between a gate terminal of a MIS transistor and a terminal to which a source and drain of the MIS transistor are shortcircuited.