Patent ID: 8381223

Claim:
An apparatus comprising: a plurality of homogeneous processors in an integrated circuit coupled to a bus in the integrated circuit; an input/output interface coupled to the bus; a plurality of input/output devices coupled to the input/output interface, the plurality of processors configured to process program code configured to perform a plurality of tasks, the program code comprising: program code configured to cause a first portion of the plurality of processors to interact with a first input/output device of the plurality of input/output devices; program code configured to cause a second portion of the plurality of processors to interact with a second input/output device of the plurality of input/output devices; program code configured to convert a task of the plurality of tasks expressed using a first instruction set to an equivalent task expressed using a second instruction set, wherein the second portion of the plurality of processors implements the second instruction set; wherein the first portion of the plurality of processors provides functionality as found in a first application-specific subsystem and wherein the first input/output device is the first application-specific subsystem; wherein the second portion of the plurality of processors provide functionality as found in a second application-specific subsystem and wherein the second input/output device is the second application-specific subsystem; wherein the second portion of the plurality of processors are configured to execute a first instruction of the first instruction set and a second instruction of the second instruction set; and kernel program code configured to dynamically allocate the processing of the program code among the plurality of processors without regard to a processor mode.