Patent ID: 8410969

Claim:
A charge balancing capacitive-to-digital converter comprising: a sensor capacitor switched according to a first clock signal of a first clock schedule; an offset capacitor switched according to a second clock signal of a second clock schedule, the second clock schedule comprising a higher switching frequency than the first clock schedule; a reference capacitor for charge balancing, and switched according to a return signal from an output of the charge balancing capacitance-to-digital converter; an integrator circuit, the integrator circuit comprising an integrator capacitor, and comprising a first input node and a second input node, the sensor capacitor, offset capacitor, and reference capacitor each being switched to the first input node or the second input node based on the respective first clock schedule, second clock schedule or return signal; and a demodulation circuit receiving and converting output of the integrator circuit into a clocked digital output, wherein the second clock schedule being of higher switching frequency than the first clock schedule allows a reduction in capacitance in at least one of the offset capacitor, reference capacitor, or integrator capacitor.