Patent ID: 7552313

Claim:
A digital signal processor comprising: a program memory including a plurality of banks storing a plurality of programs, each of the programs including a plurality of instructions; a plurality of address counters storing addresses at which ones of the instructions are stored, said ones of the instructions to be executed in a next instruction execution cycle, and said addresses being correlated with said plurality of banks; a fetch block configured to fetch the instructions stored at the addresses stored by at least two of the address counters, from the banks corresponding to the addresses stored by said at least two of the address counters, a first one of the fetched instructions corresponding to a first program of the programs and a second one of the fetched instructions corresponding to a second program of the programs, and to combine said fetched instructions to generate a reallocated instruction; a plurality of register files; and an instruction executing section configured to receive said reallocated instruction and to execute said reallocated instruction in said next instruction executing cycle, wherein said fetch block is configured to, when one of said plurality of register files includes both a first register described in said instructions of said first program and a second register described in said instructions of said second program, rewrite said fetched instructions so as to replace said first register with a third register which is not incorporated within said one of said plurality of register files, and to generate said reallocated instruction by combining said rewritten instructions.