Patent ID: 8883587

Claim:
A method of manufacturing a semiconductor device, comprising: etching a semiconductor substrate to form first and second silicon line patterns, each of the first and second silicon line patterns having first and second sidewalls; forming an insulating layer over the first and second sidewalls of each of the first and second silicon line patterns; forming a conductive pattern at a lower portion between the first sidewall of the second silicon line pattern and the second sidewall of the first silicon line pattern; forming a spacer over the first and second sidewalls of each of the first and second silicon line patterns and the conductive pattern; forming an interlayer insulating layer filled between the silicon line patterns; removing at least a portion of the spacer provided over the first sidewall of the second silicon line pattern to expose a portion of the conductive pattern proximate to the first sidewall of the second silicon pattern; removing the interlayer insulating layer to expose a portion of the first sidewall of the second silicon line pattern to form a bit line contact open region; removing a portion of the spacer remaining at an opposite side of the silicon line pattern to the bit line contact open region; forming a first doped polysilicon layer over the conductive pattern and the interlayer insulating layer; performing a plasma doping (PLAD) process on a surface of the first doped polysilicon layer; forming a second doped polysilicon layer over the first doped polysilicon layer; performing an etch back process for the second and first doped polysilicon layers to form a polysilicon pattern over the conductive pattern and cover the bit line contact open region, the polysilicon pattern including dopants; and diffusing the dopants from the polysilicon pattern into the second silicon line pattern through the bit line contact open region to form a junction region.