Patent ID: 7821075

Claim:
A CMOS device comprising: a P-type semiconductor substrate, the P-type semiconductor substrate having a top surface and a bottom surface; a first isolation region, the first isolation region extending a first distance into the P-type semiconductor substrate from the top surface of the P-type semiconductor substrate; an NMOS active region including: a buried N-well located on the P-type semiconductor substrate; a P-well located on the buried N-well; and at least one Schottky barrier NMOS device located on the P-well; a PMOS active region including: an N-well located on the P-type semiconductor substrate; and at least one Schottky barrier PMOS device located on the N-well; wherein the buried N-well of the NMOS active region is not electrically contacted via ohmic contacts; wherein the buried N-well of the NMOS active region forms a metallurgical junction with the P-type semiconductor substrate, the metallurgical junction located a second distance into the P-type semiconductor substrate from the surface of the P-type substrate, wherein the second distance is less than the first distance; and wherein the NMOS active region and the PMOS active region are electrically insulated from one another by the first isolation region.