Patent ID: 8281079

Claim:
A multi-processor system that conforms to a cache coherency protocol, the system comprising: a pre-fetch buffer that retrieves data from at least one of a main memory of the multi-processor system and a cache associated with a processor of the multi-processor system as an uncached fill, such that the cache coherency state of the data remains unaltered; and a source processor that processes the data from the pre-fetch buffer in response to a source request, the source processor processes the data as a speculative data fill until a coherent signal is received, the coherent signal indicating whether the speculative data fill is coherent, wherein the speculative fill is a copy of the data that has an undetermined coherency state, and the source processor continues to execute program instructions with the speculative data fill, the source processor having a request engine that sends the source request to obtain at least one data fill from the multi-processor system, the request engine generating a miss address file (MAF) entry associated with the source request, the MAF entry having a field for storing the at least one data fill and a coherent flag that indicates if the coherent signal has been received by the source processor.