Patent ID: 7550802

Claim:
A process for producing a nonvolatile semiconductor memory device comprising: forming a source region and a drain region on a surface of a semiconductor substrate; forming a tunnel insulating film on the semiconductor substrate, the tunnel insulating film being in contact with a channel forming region of the semiconductor substrate between the source and drain regions; forming a charge retention layer adjacent the tunnel insulating film; forming a gate insulating film adjacent the charge retention layer; and forming a control gate adjacent the gate insulating film, wherein the charge retention layer is an insulating matrix containing a plurality of nano-particles which are made of at least one type of single-element substance or at least one type of chemical compound, each nano-particle configured to function as a floating gate and having a particle size of at most 5 nm and which are independently dispersed with a density of from 10 12 to 10 14 particles per square centimeter of the charge retention layer, and the charge retention layer is formed by a sputtering method employing inductively coupled plasma or electromagnetic wave coupled plasma, and a target is constituted by employing materials to form a dispersed phase as a nano-particle phase and materials to form a matrix phase as an insulating matrix phase.