Patent ID: 7793059

Claim:
A system for processing data using interleaved memory, the system comprising: a plurality of memory elements; a memory controller adapted to selectively control an interleaving ratio for concurrently accessing the plurality of memory elements, wherein the interleaving ratio defines a number of the plurality of memory elements concurrently accessed, and wherein accessing the plurality of memory elements is selected from the group consisting of reading from the plurality of flash memory elements and writing to the plurality of flash memory elements; and, a processor adapted to receive instructions that, when executed, cause the processor to perform operations including: receiving a request to access the memory elements, wherein the request to access the memory elements includes a request to read from a plurality of memory cells included in the memory elements, wherein the plurality of memory cells store data written using a selected write interleaving ratio; identifying a type of a power source operatively coupled to the plurality of memory elements for use in accessing the plurality of memory elements; selecting a first interleaving ratio at which to perform the read request for the plurality of memory cells if the power source is identified as a first type of power source; selecting a second interleaving ratio, different from the first interleaving ratio, at which to perform the read request for the plurality of memory cells if the power source is identified as a second type of power source, wherein the second interleaving ratio for reading from the plurality of memory cells is selected independently of the selected write interleaving ratio used to write the data to the plurality of memory cells; and identifying the selected interleaving ratio to the memory controller.