Patent ID: 8656128

Claim:
An aggregate symmetric multiprocessor (SMP) data processing system, comprising: multiple SMP computers including a first SMP computer having at least first and second processing units and a first system memory pool, a second SMP computer having at least third and fourth processing units and a second system memory pool, and a third SMP computer having at least fifth and sixth processing units and third, fourth and fifth system memory pools, wherein: the third system memory pool is accessible to both the fifth and sixth processing units; the fourth system memory pool is a restricted access memory pool inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units; the fifth system memory pool is a restricted access memory pool inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units; and an interconnect fabric including a first interconnect coupling the second processing unit in the first SMP computer to the fourth system memory pool in the third SMP computer and a second interconnect coupling the fourth processing unit in the second SMP computer to the fifth system memory pool in the third SMP computer, wherein the second processing unit makes load-store coherent, ordered access to the fourth system memory pool via the first interconnect and the fourth processing unit makes load-store coherent, ordered access to the fifth system memory pool via the second interconnect, wherein the second processing unit in the first SMP computer and the fourth system memory pool in the third SMP computer form a synthetic fourth SMP computer and the fourth processing unit in the second SMP computer and the fifth system memory pool in the third SMP computer form a synthetic fifth SMP computer.