Patent ID: 8166356

Claim:
A memory system comprising: a redundancy coding circuit that performs redundancy coding process for write data; an inverter circuit provided with data that has resulted from the redundancy coding process performed by the redundancy coding circuit to invert values of individual bits of the data that has resulted from the redundancy coding process; a selector provided with the data that has resulted from the redundancy coding process and data that has been inverted by the inverter circuit to make a selection of either one of the data based on a selecting signal; a memory that stores the data selected by the selector; a comparator that compares data read from the memory with either one of the data that has resulted from the redundancy coding process and the data inverted by the inverter circuit to output a comparison result signal indicative of comparison results; a write control circuit that controls writing of the memory, while being provided with the comparison result signal to produce and output the selecting signal based on the comparison results indicated by the comparison result signal; and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.