Patent ID: 7340573

Claim:
A data processing apparatus, comprising: a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, wherein when the processor is in the secure domain, a program executed by the processor has access to secure data which is not accessible from the non-secure domain; a memory unit comprising a plurality of entries and operable to store data required by the processor, each entry being operable to store one orone or more data items including either secure data or non-secure data, the allocation of data as either secure or non-secure data being performed in the secure domain, and a flag being associated with each entry in the memory unit to store a value indicating whether the one or more data items stored in the associated entry are said secure data or said non-secure data; wherein when the processor is operating in said at least one non-secure mode of the non-secure domain, the memory unit is operable, upon receipt of a memory access request issued by the processor when access to an item of data is required, to prevent access to any data item within an entry of the memory unit that the associated flag indicates has secure data stored therein.