Patent ID: 7764263

Claim:
A driver circuit of a display apparatus, comprising: a writing circuit having a plurality of first switches respectively provided for signal supply lines of the display apparatus, said writing circuit being provided for inputting a write signal into each of said signal supply lines by conducting each of said plurality of first switches; a shift register having flip-flops of plural stages, said shift register being provided for sequentially outputting a timing pulse from each of said flip-flops of plural stages to conduct each of said first switches; a pre-charge circuit having a plurality of second switches respectively provided for the signal supply lines, said pre-charge circuit being provided for pre-charging each of said signal supply lines by conducting each of said plurality of second switches, wherein said shift register includes a plurality of pulse signal supply circuits provided corresponding to said signal supply lines to be pre-charged while an input operation of the write signal is being carried out, and each of said pulse signal supply circuits receives a clock signal different from the timing pulse, in response to an input of the timing pulse as outputted from each of said flip-flops, and outputs as a pre-charge pulse, a pulse signal in sync with the clock signal to a second switch corresponding to a prescribed signal supply line to which the input operation of the write signal is not being carried out to conduct said second switches; and a superimposition preventing section including, a pulse front edge cut-off circuit provided for each output line of the pre-charge pulse, said pulse front edge cut-off circuit being provided for cutting off a front edge of the pre-charge pulse to be supplied to the output line, a buffer circuit which amplifies a current of the pre-charge pulse as input from said pulse front edge cut-off circuit, and a superimposition removing circuit for removing from the timing pulses to be supplied from said flip-flops to said first switches, an overlapped part which is overlapped with the pre-charge pulse to be supplied from said buffer circuit to said second switches, wherein overlapping of the pre-charge pulse and the liming pulse is prevented, and overlapping of the timing pulses is prevented.