Patent ID: 8120208

Claim:
A circuit block comprising: logic circuitry coupled between a first power supply connection and a second power supply connection to the circuit block; and a plurality of power switches coupled between the first power supply connection and a first external power supply connection, wherein the plurality of power switches are coupled to receive an enable for the circuit block and are configured to electrically connect the first power supply connection to the first external power supply connection responsive to assertion of the enable, and wherein the plurality of power switches are configured to electrically isolate the first power supply connection from the first external power supply connection responsive to a deassertion of the enable; wherein the plurality of power switches are physically distributed to a plurality of locations over an integrated circuit area occupied by the circuit block and a subset of the plurality of power switches are in a first location of the plurality of locations, wherein the first location is proximate an edge of the circuit block; and wherein a number of the plurality of power switches in the subset provides an approximately equal total impedance from the first external power supply connection to each worst case impedance point within the area occupied by the circuit block, wherein each worst case impedance point is a point of largest impedance among points between adjacent ones of the plurality of locations.