Patent ID: 8504978

Claim:
A method for integrated circuit design and analysis, the method comprising: reading an automatically generated timing budgeting file including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a first time budgeting debug window on a first display device, the first time budgeting debug window including a first button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu; graphically displaying a first timing budget analyzer window on the first display device in response to selection of a first selected signal path in the path list window pane, the first timing budget analyzer window to graphically display timing budgets and timing delays of the first selected path for visual comparison; and wherein one or more of the reading, the graphically displaying of the first time budgeting debug window, and the graphically displaying of the first timing budget analyzer window are performed with a processor.