Patent ID: 7624209

Claim:
A method of enabling variable latency data transfers in an integrated circuit having a plurality of peripheral devices transmitting data within said integrated circuit, said method comprising the steps of: coupling a memory controller between a processor of said integrated circuit and a peripheral device, said memory controller controlling the transfer of data to and from said processor; providing said peripheral device implementing a function in a configurable resource of said integrated circuit; providing an address for a data transfer between said memory controller and said peripheral device; coupling an address valid signal to said peripheral device; transferring said data between said processor and said peripheral device by way of said memory controller during a single clock cycle of said peripheral device after a latency period which is unknown to said processor, said latency period comprising a number of clock cycles of a clock driving said peripheral device based upon a requirement of said function implemented in said peripheral device; generating, by said peripheral device, a data transfer complete signal associated with the completion of the step of transferring said data between said processor and said peripheral device by way of said memory controller, wherein said data transfer complete signal defines said latency period; and receiving said data transfer complete signal at said memory controller from said peripheral device after said latency period based upon said requirement of said function implemented in said configurable resource of said peripheral device, wherein said data transferred between said processor and said peripheral device is available at said memory controller during a read and at said peripheral device during a write during the same clock cycle that said data transfer complete signal is received by said memory controller.