Patent ID: 7941634

Claim:
An array of a plurality of digital processing elements, wherein a digital processing element is a hardware structure for processing digital input data and providing digital output data and wherein the array may have one, two or three dimensions, and wherein the array of digital processing elements is suitable for simultaneously comparing one of a plurality of search blocks of reference input data with a block of current input data, wherein each digital processing element has associated with it a plurality of local first registers for holding the reference input data and at least one local second register for holding the current input data, wherein one of the first registers in each digital processing element holds reference input data of a first search block, and at least some of the remaining first registers in each digital processing element hold reference input data of further search blocks that have, for each of the at least some of the remaining first registers, specified positions relative to the first search block, and wherein the reference input data can be loaded in a load mode from a data source being external to the array; each of the plurality of first registers but not the second register of each digital processing element is connected through switchable connections to the corresponding first registers of two neighboring digital processing elements in each dimension of the array, wherein corresponding first registers are those that hold data of a same search block, and wherein first registers associated with digital processing elements that are on the border of the array are directly connected, through a single switching element each, to non-corresponding first registers of digital processing elements on the opposite border of the array, and wherein the switchable connections can switch at least some of the first registers into a shift-register mode of operation; wherein said array is operated by a clock signal, and said processing by the digital processing elements is performed in the same clock cycle as the shifting in said shift-register mode, and wherein the first registers associated with a digital processing element are distinguishable, and a first register holds data of a first search block, a second and a third register hold data of second and third search blocks adjacent to the first search block, and a fourth register holds data of a fourth search block adjacent to the second and third search block.