Patent ID: 7716269

Claim:
An apparatus for performing parallel integer multiply accumulate operations on packed data comprising: a) a number of multipliers for multiplying two z-bit words inputted into the apparatus, the two z-bit words each having a number of m-bit operands; b) a number of j-bit accumulators, each of the number of j-bit accumulators combining the result of at least one multiplier and a value stored in the j-bit accumulator, each of the number of j-bit accumulators coupled to at least one of the first number of multipliers; c) a number of n-bit accumulator registers for accessing results of operation performed by the j-bit accumulators, each of the number of n-bit accumulator registers coupled to at least one of the number of j-bit accumulators; d) means for receiving an input command specifying a mode of operation for the apparatus, the means coupled to the number of multipliers, the mode of operation indicating a number of m-bit operands contained in each z-bit word and an m×m mode of each multiplier, wherein if m is less than z, products of each m-bit operand of a first z-bit word multiplied by each m-bit operand of a second z-bit word are obtained, wherein the number of n-bit accumulator registers is sufficient to store each product regardless of the mode of operation.