Patent ID: 7506297

Claim:
An automated software tool for implementing a functional task in a hybrid FPGA network that includes a plurality of network nodes, wherein at least two nodes include a processor and an FPGA board, each FPGA board having at least one field programmable gate array and at least one memory, the automated software tool adapted to carry out the steps of: scheduling portions of the functional task in a time sequence, wherein at least some of the task portions are intended to be managed by separate processors, wherein the processor at one of the network nodes is a master processor on which the automated software tool is installed; partitioning a plurality of elements of the hybrid FPGA network, including field programmable gate arrays and memories located on a plurality of FPGA boards, and further including a plurality of embedded processors, by allocating or assigning network resources to the scheduled portions of the functional task; mapping the partitioned elements into a physical hardware design, including field programmable gate arrays and memories located on a plurality of FPGA boards, and further including the plurality of embedded processors, for implementing the functional task on the plurality of elements of the hybrid FPGA network; and iteratively repeating the scheduling, partitioning and mapping steps to reach an optimal physical hardware design, wherein the design elements include the field programmable gate arrays, the embedded processors, and the memories; and thereafter, after removal of at least one of the design elements from the hybrid FPGA network, iteratively repeating the scheduling, partitioning and mapping steps to reach a new optimal physical hardware design.