Patent ID: 8229907

Claim:
A method in a computer system to implement a hardware assisted transactional memory system comprising at a single thread: beginning execution of a first transaction; then performing a data write access, from within the first transaction, wherein the data write access, comprising establishing a software visible indication that the data is being written correlated to the data that is being written and performing a write to memory; then, beginning execution of a second transaction, comprising executing processor level instructions to establish a hardware transactional execution mode on the thread, and wherein beginning execution of a second transaction comprises selecting a hardware transactional execution mode from among a set of hardware transactional execution modes and software transactional execution modes based on: reference to a one or more statically defined indicators, wherein the one or more statically defined indicators are a function of a given transaction begin site, the function depending on the particular site or the caller of that site; reference to a one or more dynamically computed indicators, wherein the one or more dynamically computed indicators are a function of the history of past transactional execution modes and outcomes, for a given site, wherein the history is generated by a transactional memory system, the history of past transactional execution modes and outcomes being used as feedback; and reference to at least one of system load or transactional memory system throughput statistics; then performing a second memory access from within the second transaction, including executing processor level instructions to establish at least one of hardware conflict detection or speculative write buffering on the data; then committing the second transaction, including executing processor level instructions to exit the transaction and commit speculatively buffered writes to become permanent and globally observed; then committing the first transaction.