Patent ID: 7126206

Claim:
A capacitor structure in an integrated circuit, comprising: a semiconductor substrate; a capacitor region defined within the boundaries of said semiconductor substrate; an active circuit layer formed on the surface of said semiconductor substrate with a portion thereof formed in the surface of said semiconductor substrate and a portion thereof formed over the surface of said semiconductor substrate, in which is formed active circuitry and interconnects; a planarization layer of metal disposed over said active circuit layer and electrically isolated therefrom in at least said capacitor region; a metal capacitor layer formed over said planarization layer within said capacitor region and having the bottom plates of a plurality of capacitors defined therein; a layer of dielectric formed on said bottom plates of said plurality of capacitors of a predetermined thickness; a top plate formed on said dielectric for each of said plurality of capacitors to define each of said plurality of capacitors, such that a portion of each of said bottom plates extends outside of the boundaries of said associated top plate; and a plurality of vias connected to said portion of select ones of said bottom plates and to structures beneath said planarization layer, and wherein vias are not formed within the region beneath said top plate and above said planarization layer.