Patent ID: 8572349

Claim:
A processor comprising: a plurality of clients; translation configuration circuitry comprising a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients; address translation circuitry coupled to the translation configuration circuitry, the address translation circuitry being configured to utilize the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client; and memory controller circuitry coupled to the address translation circuitry, the memory controller circuitry being configured to access a memory utilizing the physical address; wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.