Patent ID: 8384185

Claim:
A semiconductor device comprising: a semiconductor chip having an integrated circuit over a main surface thereof in which there is defined a first circuit region including a plurality of input-output circuits arranged along a peripheral edge of said semiconductor chip and a second circuit region including a first portion arranged between adjacent input-output circuits of said first circuit region; and bump electrodes formed over said second circuit region and electrically coupled to said integrated circuit, wherein a third circuit region closer to a center of said semiconductor chip than said first and second regions is defined, wherein a second portion of said second circuit region and a second plurality of said bump electrodes are arranged between said first circuit region and said third circuit region, and wherein the second plurality of bump electrodes are arranged in the second portion of said second circuit region and a first plurality of bump electrodes are arranged in the first portion of said second circuit region, said first and second pluralities of bump electrodes being arranged in two lines parallel to the peripheral edge of said semiconductor chip at positions defining vertices of contiguous equilateral triangles.