Patent ID: 8785245

Claim:
A method of manufacturing a stack type semiconductor package, comprising: providing a lower semiconductor package comprising a circuit board on which a semiconductor chip and electrode pads are formed; fixing a plurality of metal pins respectively to the electrode pads of the circuit board of the lower semiconductor package by using a jig comprising a metal plate comprising an upper surface, a lower surface, and a plurality of holes formed in the metal plate, wherein the plurality of holes are positioned to correspond to a same arrangement by which the electrode pads of the circuit board are positioned, positioning the metal pins in the holes with the metal pins protruding from the upper surface of the metal plate, stacking the jig including the metal pins on the circuit board, and separating the metal plate from the metal pins and the circuit board, wherein the protruding metal pins pass through the upper and lower surfaces of the metal plate as the jig is separated, and wherein the plurality of metal pins comprise a plating layer formed at a lower portion of the metal pins, the plating layer being formed prior to fixing the plurality of metal pins; and vertically stacking an upper semiconductor package on the lower semiconductor package via the metal pins.