Patent ID: 7777318

Claim:
A wafer-level package comprising: a substrate wafer; a cover wafer mounted to the substrate wafer to form a hermetically sealed cavity; a plurality of integrated circuits formed on the substrate wafer or the cover wafer; a plurality of traces formed on the substrate wafer on which the plurality of integrated circuits are formed or the cover wafer on which the plurality of integrated circuits are formed; and a plurality of hydrogen getters interspersed within and among the plurality of integrated circuits, wherein the plurality of hydrogen getters are integrated hydrogen getters formed on the substrate wafer or the cover wafer when the integrated circuits are formed on the substrate wafer or the cover wafer, and wherein the plurality of hydrogen getters include a plurality of layers formed on a parallel plane with respect to the substrate wafer or the cover wafer and wherein the plurality of hydrogen getters are formed among the plurality of traces.