Patent ID: 7514770

Claim:
A stack structure of a carrier board embedded with semiconductor components, the stack structure comprising: a first carrier board and a second carrier board, both of which are provided with a through hole; a first semiconductor component and a second semiconductor component disposed in the through holes of the first and second semiconductor components respectively, each of the first and second semiconductor components having an inactive surface and an active surface opposed to the inactive surface and formed with a plurality of electrode pads; a dielectric layer structure clamped between the first carrier board and the second carrier board and comprising a first dielectric layer formed on the first carrier board and the inactive surface of the first semiconductor component and filled in gaps between the first carrier board and the first semiconductor component, a second dielectric layer formed on the second carrier board and the inactive of the second semiconductor component and filled in gaps between the second carrier board and the second semiconductor component, and a bonding layer clamped between the first dielectric layer and the second dielectric layer; a first build-up structure and a second build-up structure formed on external surfaces of the first and second carrier boards respectively, both of the first and second build-up structures comprising a dielectric layer, a circuit layer stacked on the dielectric layer, and a plurality of conductive vias formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the semiconductor components; and a plurality of plated through holes penetrating the first and second carrier boards, the dielectric layer structure, and the first and second build-up structures and electrically connected to the first and second build-up structures, wherein both of the first and second dielectric layers comprises a coarsened surface for disposition of the bonding layer.