Patent ID: 8236659

Claim:
A method comprising: providing a substrate having a first region and a second region; forming a first gate stack and a second gate stack over the substrate in the first and second regions, respectively; forming first and second lightly doped source and drain (LDD) regions in the first and second regions, respectively, such that the first gate stack interposes the first LDD regions and the second gate stack interposes the second LDD regions, wherein first LDD regions include a first type dopant and the second LDD regions include a second type dopant opposite the first type dopant; forming offset spacers along sidewalls of the first and second gate stacks, wherein the offset spacers are disposed over a portion of the first and second LDD regions; after forming the offset spacers, forming doped regions in the substrate in the second region, such that the doped regions are interposed by the second gate stack, wherein the doped regions include the first type dopant; forming first source and drain recesses in the substrate, such that the first gate stack interposes the first source and drain recesses; epitaxially (epi) growing a first semiconductor material to fill the first source and drain recesses; forming main spacers disposed adjacent to the offset spacers; forming second source and drain recesses in the substrate, such that the second gate stack interposes the second source and drain recesses; and epitaxially (epi) growing a second semiconductor material to fill the second source and drain recesses, the second semiconductor material being different than the first semiconductor material, wherein the forming the doped regions includes performing a tilt-angle ion implantation process.