Patent ID: 8107275

Claim:
A nonvolatile memory device comprising: at least a first nonvolatile memory cell and a second nonvolatile memory cell; a word line coupled to the first nonvolatile memory cell and to the second nonvolatile memory cell; a first bit line coupled to the first nonvolatile memory cell; a second bit line coupled to the second nonvolatile memory cell; and a read circuit that reads a resistance level of the first nonvolatile memory cell and a resistance level of the second nonvolatile memory cell by providing a first read bias current and second read bias current of different levels to the first bit line and to the second bit line, respectively, wherein: the word line includes a first sub word line and a second sub word line connected to each other through a strapping node, the first nonvolatile memory cell is nearer to the strapping node than the second nonvolatile memory cell, and a level of the first read bias current is lower than a level of the second read bias current.