Patent ID: 7598564

Claim:
A non-volatile memory device, comprising: field oxides disposed in a semiconductor substrate to define active regions; a string selection line crossing over the active regions; a ground selection line crossing over the active regions; a plurality of wordlines crossing over the active regions; each of the string selection line and the ground selection line including: a first gate insulator on one of the active regions, a first floating gate, the first floating gate being on the first gate insulator and including a first sidewall and a second sidewall, a first intergate dielectric pattern on the first floating gate, a first control gate on the first intergate dielectric pattern and on the first floating gate and being in contact with the first floating gate and the first intergate dielectric pattern, and a first mask pattern on the first control gate; each of the wordlines including: a second gate insulator on one of the active regions, a second floating gate, the second floating gate being on the second gate insulator and including a first sidewall and a second sidewall, a second intergate dielectric pattern on the second floating gate, a second control gate on the second intergate dielectric pattern, and a second mask pattern on the second control gate; a thermal oxide layer covering the first sidewall and the second sidewall of the second floating gate and the second sidewall of the first floating gate; first barrier spacers, wherein: each of the first barrier spacers covers a combination of a first sidewall of the first mask patterns, a first sidewall of the first control gates and the first sidewall of the first floating gates defining a same side of the respective string or ground selection line, each of the first barrier spacers includes an oxide layer and a nitride layer, the oxide layer being between the nitride layer and the first sidewall of the corresponding first control gate, and the first barrier spacers expose the second sidewall of the first floating gate, the exposed second sidewall of the first floating gate being covered by the thermal oxide layer; and second barrier spacers, wherein: each of the second barrier spacers covers at least one of a combination of a second sidewall of the first mask pattern and a second sidewall of the first control gate, a combination of a first sidewall of the second mask pattern and a first sidewall of the second control gate, and a combination of a second sidewall of the second mask pattern and a second sidewall of the second control gate, each of the second barrier spacers includes an oxide layer and a nitride layer, the oxide layer being between the nitride layer and the sidewall of the corresponding second control gate, and the second barrier spacers expose the first and second sidewalls of the second floating gate, the exposed first and second sidewalls of the second floating gate being covered by the thermal oxide layer, wherein the oxide layer of the first and second barrier spacers is a substantially L-shaped layer.