Patent ID: 7293198

Claim:
A data storage system, comprising: a first storage processor; a second storage processor; and a communications subsystem having (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit, the controller being configured to: enable operation of the interfacing portion to provide communications between the first and second storage processors; sense a failure within the clock circuit; and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation; wherein the controller of the communications subsystem includes: a watchdog stage which is configured to generate an error signal in response to loss of a clock signal from the clock circuit within a predetermined timeout period; wherein the interfacing portion of the communications subsystem includes a first interface device coupled to the first storage processor, a second interface device coupled to the second storage processor, and a communications bus connecting the first and second interface devices together; wherein the controller of the communications subsystem further includes: an output stage coupled to the watchdog stage, the output stage being configured to provide a reset signal to the first interface device in response to the error signal, the reset signal enabling the second storage processor to continue operation; wherein (i) the first interface device is disposed at one end of the communications bus and (ii) the second interface device is disposed at another end of the communications bus to form a communications pathway between the first and second storage processors; and wherein the controller, when enabling operation of the interfacing portion, is configured to: direct the first interface device coupled to the first storage processor and the second interface device coupled to the second storage processor to concurrently operate as communications end points of the communications pathway formed between the first and second storage processors to exchange cached data between the first and second storage processors through the first interface device, the second interface device and the communications bus.