Patent ID: 7209979

Claim:
A storage processor, comprising: at least one switch connecting a front end interface connectable to host and a back end interface connectable to a data store, said front and back ends each having a channel connecting it to said at least one switch, each said front end and back end channels having respective bandwidths; at least two memory interfaces each with a respective channel permitting simultaneous read and writes to memories connected thereto; a data translator connected to transfer data to and from said memories through each of said two memory interfaces; said at least one switch being configured to provide for transfer of write data from said front end to said back end by storing said write data in a selected subset of said memories, generating translated data responsively to said write data stored in said selected subset, storing store data responsive to said translated data and said write data in said selected subset or another subset of said memories; said at least one switch being further configured such that a rate of transfer of said write data through said front end channel is substantially equal to said bandwidth of said front end channel; wherein said at least one switch, when generating translated data, is configured to perform an error-checking process on the write data stored in said selected subset of said memories to generate error-checking data and, when storing store data, is configured to store said store data responsive to said error-checking data and said write data in said selected subset or another subset of said memories; wherein data is transferred through the switch by writing to selected ones of said memories and reading from said selected ones of said memories in a single hop between said front end and said back end such that a load on said memories is balanced.