Patent ID: 6919245

Claim:
A fabrication method for a dynamic random access memory cell layout, comprising the steps of: providing a semiconductor silicon substrate having an array area and a support area; forming a pad layer overlying the semiconductor silicon substrate, in which the pad layer comprises a predetermined deep trench pattern; forming a first deep trench and a second deep trench in the semiconductor silicon substrate within the array area; forming a first deep trench capacitor and a second deep trench capacitor at the lower portions of the first deep trench and the second deep trench, respectively; forming a collar dielectric layer on the sidewalls of the first deep trench and the second deep trench, respectively, in which the collar dielectric layer is disposed over the first deep trench capacitor and the second deep trench capacitor; forming a polysilicon layer in the first deep trench and the second deep trench, in which the polysilicon layer is surrounded by the collar dielectric layer; forming a first buried strap out-diffusion region and a second buried strap out-diffusion region in the semiconductor silicon substrate adjacent to the sidewalls of the first deep trench and the second deep trench, respectively, in which the first buried strap out-diffusion region and the second buried strap out-diffusion region are adjacent to the polysilicon layer in the first deep trench and the second deep trench, respectively; forming a top isolating layer to cover the top of the polysilicon layer in the first deep trench and the second deep trench; forming two first shallow trenches in the semiconductor silicon substrate within the array area to separate the active area from other areas, in which the first shallow trenches are outside the first deep trench and the second deep trench is within the array area; forming a second shallow trench in the semiconductor silicon substrate within the support area; forming a liner on the substrate; forming a first isolating layer in the first shallow trenches and the second shallow trench, in which the top of the first isolating layer is leveled off with the top of the liner; forming a photoresist layer to cover the support area; removing the first isolating layer formed in the first shallow trenches within the array area; removing the photoresist layer, the exposed liner and the pad layer, in which the semiconductor silicon substrate within the active area of the array area protrude from the top isolating layer; forming a gate oxide layer on the exposed surface of the semiconductor silicon substrate; forming a gate conductive structure on the active area between the first deep trench and the second deep trench; forming a second isolating layer to fill the first shallow trenches, in which the top of the second isolating layer is leveled with the top of the gate conductive structure; and forming a first contact hole penetrating the gate conductive structure and the gate oxide layer to expose the semiconductor silicon substrate.