Patent ID: 7933156

Claim:
An apparatus for adjusting a digital delay function of a data memory unit, the apparatus comprising: a data memory unit having a plurality of memory cells to store corresponding data elements; an elastic store register; a read clock function and a write clock function configured to control read and write operations; a read counter associated with the read clock function, and a write counter associated with the write clock function; wherein the data memory unit is configured to: operate in series with the elastic store register such that data elements passing through the apparatus are arranged in a parallel structure, and pass through the data memory unit before passing through the elastic storage register; selectively change an output position from a first memory cell to a second memory cell; and deliver two subsequent data elements to the elastic store register from two logically neighboring memory cells; and wherein the elastic store register is configured to write the two subsequent data elements output from the data memory unit at every cycle of the write clock, such that: if the write counter is increased by one at a cycle of the write clock, the output position in the data memory unit is unchanged; if the write counter is increased by two at a cycle of the write clock, the output position in the data memory unit is moved backward by one data element; and if the write counter is unchanged at a cycle of the write clock, the output position in the data memory unit is moved forward by one data element.