Patent ID: 7430100

Claim:
A buffer circuit having overvoltage protection, comprising: core buffer circuitry couplable to a first voltage source having a first voltage level, the core buffer circuitry being configured to receive a first signal and to generate a second signal which is a function of the first signal; and a protection circuit coupled between the core buffer circuitry and a signal pad, the protection circuit being operative: (i) to clamp the first signal to about the first voltage level and to interrupt a current path between the signal pad and a current return of the protection circuit when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level; wherein the protection circuit comprises: at least one complementary pass gate including a first transistor of a first polarity type and a second transistor of a second polarity type connected in parallel with the first transistor, the first transistor being biased to the first voltage level; and a bias circuit for biasing the second transistor, the bias circuit being selectively operable in one of at least two modes as a function of a voltage level of the third signal, wherein in a first mode the bias circuit is operative to turn on the second transistor, and in a second mode the bias circuit is operative to turn off the second transistor; wherein the bias circuit comprises: a PMOS transistor device including a first source/drain connecting to the signal pad, a second source/drain connected to the second transistor, a gate connecting to the first voltage source, and a bulk terminal connecting to a second voltage source having a second voltage level; at least a first NMOS transistor device including a first source/drain coupled to the second transistor, a second source/drain connecting to the current return of the protection circuit, and a gate for receiving a control signal, the control signal enabling the first NMOS device in the first mode and disabling the first NMOS device in the second mode; and a comparator operative to generate the control signal as a function of a difference between a voltage level of the third signal and the first voltage level.