Patent ID: 7460420

Claim:
A semiconductor storage device comprising: a plurality of selection lines (WL); a spare selection line (SWL); a program circuit ( 24 ) which programs a defective address and generates a defective address signal (DRA) indicating a defective address has been programmed; an address comparison circuit ( 26 ) which compares a plurality of bits comprising an address signal (RA) with a plurality of corresponding bits of the defective address signal (DRA); if the bits of the address signal (RA) and the defective address signal (DRA) match, activating a first match signal (DIS), or if the bits of the address signal and the defective address signal do not match, deactivating the first match signal (DIS); a decoder ( 14 ) which is activated in accordance with the deactivation of the first match signal (DIS) and drives the plurality of selection lines (WL) in accordance with the address signal (RA); and a spare decoder ( 20 ), for driving the spare selection line (SWL) in accordance with the activation of the first match signal (DIS).