Patent ID: 7948089

Claim:
A chip stack package, comprising: a substrate having a plurality of circuit patterns arranged on a surface thereof; a unit semiconductor chip mounted on the substrate, the unit semiconductor chip including a plurality of semiconductor chips each having a plurality of pads on an active surface; a plurality of connection members for electrically connecting the semiconductor chips of the unit semiconductor chip to the circuit patterns of the substrate; and an encapsulant that encapsulates the unit semiconductor chip and the connection members, wherein a first semiconductor chip of the plurality of semiconductor chips includes a first homogeneous substrate comprising a first portion of a wafer and having a first size, and a second semiconductor chip of the plurality of semiconductor chips includes a second homogeneous substrate comprising a second portion of the wafer and having a second size larger than the first size, wherein the first and second homogeneous substrates include first and second respective chip regions having the same size, and the second homogeneous substrate includes an additional scribe region not included in the first semiconductor chip; and wherein the first semiconductor chip includes a plurality of first redistribution pads disposed in the first chip region on the first homogeneous substrate and the second semiconductor chip includes a plurality of second redistribution pads disposed in the scribe region on the second homogeneous substrate.