Patent ID: 8867684

Claim:
An apparatus for synchronizing an incoming signal with a clock signal, said apparatus comprising: two or more synchronizer circuits, wherein each synchronizer circuit receives said incoming signal and said clock signal, wherein each synchronizer circuit generates a synchronized signal, wherein a state of each synchronized signal respectively changes on a different point in time of said clock signal in response to a change of a state of said incoming signal, wherein each synchronizer comprises; a first flip-flop which receives said clock signal and said incoming signal, wherein said first flip-flop generates a first latched signal, wherein a state of said first latched signal changes on a predetermined first phase of said clock signal in response to said change of the state of said incoming signal; and a second flip-flop which receives said clock signal and said first latched signal of the first flip-flop, wherein said second flip-flop generates the synchronized signal of the synchronizer circuit, wherein the state of said synchronized signal changes on a predetermined second phase of said clock signal in response to a change of the state of said first latched signal, wherein said predetermined first phase of one synchronizer circuit differs from a predetermined first phase of another synchronizer circuit, and wherein said predetermined second phase of each synchronizer circuit differs from a predetermined second phase of another synchronizer circuit; and a decision mechanism circuit which receives said two or more synchronized signals generated by the synchronizer circuits, and determines an output signal in response to said two or more synchronized signals generated by the synchronized circuits; the decision mechanism circuit further comprising a memory element which comprises a RS-flip-flop having a state which is set according to a previously detected state of said incoming signal, wherein said output signal is determined according to a state of the memory element.