Patent ID: 8456199

Claim:
An integrated circuit comprising: a semiconductor device for handling data; a power source for powering said semiconductor device, said power source comprising a two voltages sources, a high voltage source for supplying a high voltage level and a low voltage source for supplying a low voltage level; a plurality of switching devices arranged between at least one of said two voltage sources and said semiconductor device; a control device for controlling a first set of said plurality of switching devices to connect one of said two voltage sources to said semiconductor device and for controlling a second set of said plurality of switching devices to connect said one of said two voltage sources to said semiconductor device; wherein at least some of said first set of said plurality of switching devices have a higher resistance when closed and providing a connection than at least some of said second set of said plurality of switching devices such that when said first set of said plurality of switching devices connect said semiconductor device to said one of said two voltage sources said semiconductor device operates with a lower performance than when said second set of said plurality of switching devices connect said semiconductor device to said one of said two voltage sources; wherein said integrated circuit is configured to operate in one of three modes, an inactive mode where said semiconductor device is isolated from at least one of said voltage sources, a low performance mode where said semiconductor device is connected to said one of said high or low voltage sources by said first set of switching devices and is clocked at a first frequency, and a high performance mode where said semiconductor device is connected to said one of said high or low voltage sources by at least said second set of switching devices and is clocked at a second frequency, said second frequency is higher than said first frequency.