Patent ID: 7263120

Claim:
A semiconductor device having a plurality of data transmitter-receiver circuits using clock signals of prescribed frequencies as transmit/receive clock signals, wherein an oscillator circuit and a clock generator circuit are provided for each data transmitter-receiver circuit, wherein a supply of clock signals to the data transmitter-receiver circuits are stopped by shutting off power supply to the oscillator circuits and the clock generator circuits inside the plurality of data transmitter-receiver circuits individually with respect to each data transmitter-receiver circuit, and wherein the clock generator circuits have a circuit generating a clock frequency necessary in internal circuits of the semiconductor device by multiplying and dividing clock signals input from an external clock input terminal using a PLL circuit, supply master clock signals input from the external clock input terminal to the internal circuits of the semiconductor device during external reset, and supply clock signals generated by said PLL circuit or a frequency divider circuit to each of the internal circuits of the semiconductor device after releasing the external reset.