Patent ID: 7003024

Claim:
A semiconductor device formed on a single semiconductor chip, comprising: a digital-signal-processing circuit; a CPU controlling said digital-signal-processing circuit: and an interface circuit inputting a digital signal synchronously with a first clock signal and supplying said input digital signal to said digital-signal-processing circuit and outputting digital data processed by said digital-signal-processing circuit synchronously with said first clock signal, wherein said interface circuit includes: an input circuit inputting said digital signal synchronously with said first clock signal and supplying said input digital signal to said digital-signal-processing circuit; a gain-adjusting circuit adjusting a gain of said digital signal supplied to said input circuit; and an output circuit adding said digital signal with said gain thereof adjusted to a digital signal supplied from said digital-signal-processing circuit and outputting a resulting digital signal synchronously with said first clock signal; wherein said input circuit comprises: an input shift register inputting and shifting the digital signal synchronously with said first clock signal; and an input register latching the digital signal shifted in said input shift register synchronously with a second clock signal.