Patent ID: 8917547

Claim:
A method for fabricating a memory array, the method comprising: receiving a semiconductor-on-insulator (SOI) substrate; constructing a first set of lateral bipolar transistors on the SOI substrate; coupling the first set of lateral bipolar transistors to form a first inverter having a first output terminal configured to invert a first input signal at a first input terminal; constructing a second set of lateral bipolar transistors on the SOI substrate; coupling the second set of lateral bipolar transistors to form a second inverter having a second output terminal configured to invert a second input signal at a second input terminal; and cross coupling the first inverter to the second inverter such that the first input terminal is electrically coupled to the second output terminal and the second input terminal is electrically coupled to the first output terminal constructing a read circuit configured to output the binary state of the second output terminal, the read circuit including (a) a high impedance read input electrically coupled to the second output terminal, (b) a read enable input electrically coupled to a read word line, and (c) a read output electrically coupled to a read bit line; and constructing a power supply configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.