Patent ID: 7269065

Claim:
A semiconductor storage apparatus comprising: a memory cell array having a plurality of data cells arranged in a plurality of rows and a plurality of columns, the plurality of data cells including a plurality of MOS transistors having different types of operating characteristics to store data according to said types, said MOS transistors in each column being connected to each other in series such that a source of one said MOS transistor is coupled to a drain of next said MOS transistor; a plurality of bit lines, each said bit line being defined by said MOS transistors in each said column, a cell current flowing in each said bit line; a readout circuit for reading said data from one of said data cells based on a cell current occurring in one of said bit lines; a reference bit line, a current-limiting current flowing in the reference bit line; and a current adjustment circuit for adjusting, in accordance with the current-limiting current in said reference bit line, the cell current flowing in one of the plurality of bit lines.