Patent ID: 7110017

Claim:
A circuit for controlling signals to form an image, said circuit comprising: a delay chain section, including a plurality of delay stages cascaded for delaying a reference clock signal step by step, to generate a plurality of delayed clock signals which are outputted from plurality of delay stages, respectively; a synchronized signal detecting section to detect a number of delay stages, a total delay time of which is equivalent to a single period of said reference clock signal, based on delayed clock signals which are synchronized with an index signal inputted into the synchronized signal detection section and selected from said plurality of delayed clock signals, said index signal serving as a leading edge reference signal of each scanning line of said image; an index signal counting section to count index signals inputted thereto so as to output a count number of said index signals; a phase shift calculating section to calculate a phase shift amount with respect to said reference clock signal, based on said number of delay stages detected by said synchronized-signal detecting section, said count number counted by said index signal counting section, and a phase shift controlling signal inputted into said phase shift calculating section; a delayed clock selecting section to select a specific delayed clock signal out of said plurality of delayed clock signals in an alternative way, based on said phase shift amount calculated by said phase shift calculating section, so as to output said specific delayed clock signal as a pixel clock signal; and a signal generating section to generate an image leading edge signal that is synchronized with the pixel clock signal outputted from the delayed clock selecting section.