Patent ID: 7254663

Claim:
An apparatus, comprising: a plurality of Fully Buffered Dual Inline Memory Module (FB-DIMM) modules, each including a buffer device and a plurality of DRAM devices; a memory controller; a unidirectional differential serial read data channel coupling the plurality of FB-DIMM modules to the memory controller in a daisy chain arrangement; a unidirectional differential serial write data channel coupling the plurality of FB-DIMM modules to the memory controller in a reverse daisy chain arrangement with respect to that for the read data channel; and a control circuit configured to, in response to an error detected in a faulty FB-DIMM module, selectively configure each of the read and write data channels to operate in a bidirectional mode such that both read and write data are communicated from and to each non-faulty FB-DIMM module over the read and write data channels, wherein read data is exclusively communicated over the read data channel and write data is exclusively communicated over the write data channel when the read and write data channels are configured in a unidirectional mode.