Patent ID: 8400435

Claim:
A circuit arrangement for controlling a display device which can be operated in a partial mode, the circuit arrangement comprising: a row drive circuit for driving n rows of the display device sequentially from 1 to n, the row drive circuit responsive to a row enable signal that is provided to each row from 1 to n; and a column drive circuit for driving m columns of the display device by supplying column voltages to the m columns, the column voltages corresponding to picture data to be displayed as pixels of the controlled row, characterized in that a logic function is included in the row drive circuit in front of row outputs, the logic function configured and arranged to respond to a first control signal having one or more pulses indicative of whether or not the partial mode is to be implemented, by preventing one or more of the row outputs from driving one or more of the rows in response to the row enable signal; wherein the row drive circuit comprises a shift register which has n stages and n outputs, and in that a second control signal can be supplied to the shift register at an input thereof for controlling the consecutive rows 1 to n, which second control signal activates the outputs of the shift register consecutively in dependence on pulses of a clock signal, and wherein the logic function is connected between the n outputs of the shift register and n amplifiers, wherein each amplifier is coupled to one of the n rows of the display, the logic function configured to prevent the n outputs of the shift register from driving any of the n rows of the display responsive to and during the one or more pulses of the first control signal; wherein a frequency of the pulses of the clock signal increases during the one or more pulses of the first control signal, thereby increasing the refresh rate of the display.