Patent ID: 6898124

Claim:
A sensing circuit for a target memory cell, said sensing circuit comprising: said target memory cell having a drain capable of being connected to a first node through a selection circuit during a read operation involving said target memory cell, said target memory cell drawing a target memory cell current when activated during said read operation; a first transistor being connected to said first node; a decouple circuit being connected to said first transistor, said decouple circuit including a second transistor having a gate width greater than a gate width of said first transistor, a gate of said second transistor being coupled to a gate of said first transistor, said decouple circuit further having a decouple coefficient (N) greater than 1, a drain of said second transistor being connected at a second node to a reference voltage through a bias resistor, said drain of said second transistor generating a sense amp input voltage at said second node such that said sense amp input voltage is decoupled from said first node.