Patent ID: 7190025

Claim:
A pull-up transistor array for a high voltage output circuit comprising: a semiconductor substrate; an epitaxial layer disposed on the semiconductor substrate; N double diffused MOS transistors (DMOS transistor) laterally arranged in the epitaxial layer, each DMOS transistor having a source and a drain, wherein one of the source and drain surrounds the other of the source and drain, wherein one of the source or drain of each double diffused MOS transistor is formed unique to each transistor, and wherein the N DMOS transistors share in common the other of the source or drain; at least one electrode for the one of the source or drain commonly shared among the N DMOS transistors; and at least one unique electrode for the one of the source or drain of each of the double diffused MOS transistors that is formed unique to each of the DMOS transistors.