Patent ID: 7882416

Claim:
A decoder that is operable to perform parallel decoding of a turbo coded signal having a block length L that includes a plurality of sub-blocks each having length M, the decoder comprising: a plurality of turbo decoders that includes C turbo decoders; a plurality of memories that includes C memories; and a processing module that is operable to perform contention-free memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal; and wherein: the plurality of turbo decoders is operable to read from and write to the plurality of memories; q is a smallest positive integer for which the term, (q·M)/C, results in an integer; C f is C/q; a set, η, has a same number of elements as C f , and each element η i within the set, η, corresponds to only one distinct value between 0 and C f −1; a symbol having an index, x, of the turbo coded signal is mapped into a memory of the plurality of memories that has an index of ( x + η ⌊ x qM ⌋ ) mod C; and the plurality of turbo decoders is operable to generate a best estimate of at least one bit that has been encoded into the turbo coded signal.