Patent ID: 7484041

Claim:
A system comprising: a plurality of processors, each of which has a corresponding cache memory; and a bus coupled to each of the processors; wherein at least a first one of the processors is configured to issue a preload command to the bus, wherein the preload command directs a target one of the processors which is different from the first one of the processors to load data into the cache memory corresponding to the target processor; wherein the first one of the processors is configured to issue the preload command in response to data being cast out of the cache memory corresponding to the first processor, wherein the data cast out of the cache memory corresponding to the first processor is the data preloaded into the cache memory corresponding to the target processor; and wherein the first one of the processors is configured to retrieve the data preloaded into the cache memory corresponding to the target processor and to perform an operation on the data retrieved from the cache memory corresponding to the target processor.