Patent ID: 8432210

Claim:
An apparatus for controlling clock skew in an integrated circuit, comprising: timing circuitry operative to generate a clock signal for distribution in the integrated circuit; and at least one buffer circuit operative to receive the clock signal and to generate a delayed version of the clock signal as an output thereof, the buffer circuit including at least first and second inverter stages and a resistive-capacitive (RC) loading structure, an output of the first inverter stage being connected to an input of the second inverter stage via the RC loading structure, the buffer circuit having a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure; wherein clock skew in the integrated circuit is controlled as a function of the delay of the at least one buffer circuit; wherein the second inverter stage comprises a first plurality of transistors and a second plurality of transistors, the first plurality of transistors being of opposite conductivity relative to the second plurality of transistors, the RC loading structure being connected to the first and second plurality of transistors and completing an electrical path between the first plurality of transistors and the second plurality of transistors.