Patent ID: 7913123

Claim:
An apparatus in a processor for concurrently sharing system memory between a tracing process and non-tracing processes, said processor including a plurality of processing units coupled together utilizing a system bus, said plurality of processing units including a memory controller that controls a system memory, said apparatus comprising: a hardware trace facility for capturing hardware trace data in said processor, said hardware trace facility included within said processor; said system bus for transmitting said hardware trace data to said system memory that is controlled by said memory controller, said system bus capable of being utilized by said plurality of processing units while said hardware trace data is being transmitted to said system bus; said memory controller for storing said trace data in said system memory; said memory controller capable of being accessed by processing units in said processor other than said hardware trace facility while said memory controller is being utilized to store said trace data; a plurality of write buffers that are controlled by said memory controller for temporarily storing all data that is to be stored in said system memory first in one of said plurality of write buffers; said hardware trace facility determining a number of said plurality of write buffers that are needed to optimize said transmission of said hardware trace data; said hardware trace facility requesting said number of said plurality of write buffers; said memory controller temporarily allocating said number of said plurality of write buffers to said hardware trace facility; a control routine determining a type of said trace data to be captured; said control routine determining a typical bandwidth of said type; said control routine determining a particular number of said plurality of write buffers needed to optimize a transfer of said typical bandwidth; and said control routine setting said number of said plurality of write buffers equal to said particular number.