Patent ID: 8141012

Claim:
A method, performed on a computer system, for performing timing closure of a digital integrated circuit design on multiple selective corners in a single timing that covers a full parameter space, comprising: using the computer system to perform the following: identifying the full parameter space for performing a statistical timing analysis of all circuit paths of the digital integrated circuit design, wherein the full parameter space is defined by parameters P 1 , P 2 , . . . , P n , wherein P n ∈ (min n , max n ); identifying all corners of the parameters that model variation in a static timing analysis of the digital integrated circuit design; performing the statistical timing analysis for all of the circuit paths of the digital integrated circuit design across the full parameter space; selecting a subset of k corners for each circuit path from the parameters P 1 , P 2 , . . . , P j , wherein j ∈ (1, n), wherein the selected subset of k corners are arranged as: C 1( P 1 =p 1 1 , P 2= p 2 1 , . . . , Pj=p j 1 ) C 2( P 1= p 1 2 , P 2= p 2 2 , . . . , Pj=p j 2 ) Ck ( P 1 =p 1 k , P 2= p 2 k , . . . , Pj=p j k ); projecting timing results to a deterministic value using a distribution input from the statistical timing analysis at each of the selected subset of k corners of parameters P 1 , P 2 , . . . , P j plus the sub-space of the remaining parameters P j+1 , P j+2 , . . . , P n for each circuit path; determining the worst slacks from the projected timing results for the selected subset of k corners of parameters P 1 , P 2 , . . . , P j plus the sub-space of the remaining parameters P j+1 , P j+2 , . . . , P n ; and closing the timing of the digital integrated circuit design on each circuit path according to the corners having the worst slacks.