Patent ID: 8214808

Claim:
A computer implemented method to provide speculative assistance to a thread in a heterogeneous processing environment, the method comprising: compiling a source code into a first executable representation, wherein the source code comprises a plurality of instructions; enabling profiling of memory stalls in the first executable representation; executing the first executable representation in response to enabling the profiling; storing memory stall data related to the first executable representation; in response to the storing, identifying a first set of instructions included in the source code, wherein the identified first set of instructions is delinquent code, and wherein the identifying is based on the stored memory stall data; in further response to the storing, identifying a second set of instructions included in the source code, wherein the second set of instructions is needed to prevent a stall of the identified first set of instructions; analyzing processing requirements for the identified second set of instructions, wherein the analyzing is based on one or more processing facilities used to execute the identified second set of instructions; determining a processor type to execute the identified second set of instructions based on the analysis, wherein the processor type is selected from a plurality of processor types included in the heterogeneous processing environment, the heterogeneous processing environment including a plurality of heterogeneous processing cores in a single silicon substrate, and wherein a first type of processing core included in the heterogeneous processing cores uses a first instruction set and wherein a second type of processing core included in the heterogeneous processing cores uses a second instruction set; and generating a second object code representation for the identified second set of instructions, wherein the second object code representation is adapted to execute on the determined processor type.