Patent ID: 7202872

Claim:
An apparatus for compressing a plurality of input signals comprising: a plurality of multiplexers arranged in a plurality of rows, wherein multiplexers in a first row have inputs connected to signals defining bits to be compressed and multiplexers of successive rows have inputs connected to outputs of the multiplexers of the preceding row, wherein each successive row of multiplexers comprises fewer multiplexers than the previous row, wherein a first row of multiplexers is arranged so that each multiplexer in the first row has two inputs, which inputs are coupled to adjacent bit positions of the plurality of input signals, and wherein a second row of multiplexers is arranged so that each multiplexer in the second row has two inputs, in which a first of the inputs is coupled to an output of a first aligned multiplexer in the first row and a second of the inputs is coupled to an output of a second multiplexer in the first row, the second multiplexer being two multiplexers away from the first aligned multiplexer, and wherein a third row of multiplexers is arranged so that each multiplexer in the third row has two inputs, in which a first of the inputs is coupled to an output of a second aligned multiplexer in the second row and a second of the inputs is coupled to an output of a second multiplexer in the second row, the second multiplexer in the second row being four multiplexers away from the second aligned multiplexer; and control logic for controlling data select input signals for individual select inputs of the plurality of multiplexers such that individual bits of the plurality of bits are shifted varying amounts, the shift amount and the individual select inputs being determined by a mask.