Patent ID: 8104007

Claim:
A method for performing thermal analysis of an integrated circuit (“IC”) design layout, the method comprising: dividing the IC design layout into a set of elements comprising a plurality of nodes, each node located on a vertex of an element; for each element, computing a first set of entry values for each node of the element based on a dielectric area in the element, each entry value representing an effect on heat flow at a particular node of an element by a temperature change at another node on the element; for each element having a wire, computing a second set of entry values for each node based on the wire; calculating a plurality of sets of conductivity values based on the first and second sets of entry values computed for each element; and at a computer, identifying a temperature distribution for the IC design layout based on the plurality of sets of conductivity values by solving a heat flow equation that is a set of temperature values corresponding to the temperature values of each node on the set of elements.