Patent ID: 8912638

Claim:
A device comprising: a chip comprising a first main surface, a second main surface and side surfaces connecting the first main surface and the second main surface; a structure arranged over the first main surface of the chip wherein the structure comprises a first planar main surface, a second planar main surface, and side surfaces connecting the first planar main surface and the second planar main surface; a hollow space arranged over the first main surface of the chip, wherein the entire hollow space is arranged between the first main surface of the chip and the first planar main surface of the structure, and wherein the entire hollow space is arranged between the side surfaces of the structure; an encapsulant embedding the chip, wherein the encapsulant comprises a main surface and is disposed on the side surfaces of the chip, wherein the main surface of the encapsulant and the first planar main surface of the structure are arranged in a common plane; and one or more dielectric layers with conductor tracks and external contact elements arranged over the main surface of the encapsulant, wherein at least one of the external contact elements is arranged completely outside of a contour of the first main surface of the chip.