Patent ID: 8238158

Claim:
An integrated circuit comprising: a programmable solid-state memory array including a plurality of memory cells arranged in rows and columns, each memory cell including a metal-oxide-semiconductor (MOS) transistor having a gate and a source/drain path; a plurality of word lines, each coupled to the gate of the MOS transistor in memory cells in an associated row of the memory array; word line drive circuitry, for energizing the word line associated with a selected row of the memory array; a plurality of bit lines, each associated with memory cells in an associated column of the memory array; at least one programming bit line driver for driving programming current to one or more of the plurality of bit lines in a programming operation; and programming logic, comprising: switch circuitry, for selectively opening and closing a circuit through which the programming current is conducted via the bit line associated with a selected column of the memory array in the programming operation; and circuitry, having a first input coupled to the bit line of the selected column and having a second input coupled to receive a reference current, for controlling the switch circuitry responsive to a remainder current, the remainder current corresponding to a portion of the programming current not conducted by a memory cell in the selected column and the selected row.