Patent ID: 7376199

Claim:
For sending digital data representing a data set, using multiple serial links, a circuit arrangement for aligning the phases of the digital data at a transmission end of the multiple serial links, comprising: a reference clock signal; for each of the multiple serial links, a transmit-data module communicatively coupled to the reference clock signal and including a data driver adapted to load digital data in response to a phase-adjusted clock-load signal and send the digital data in response to a clock-load signal, and a clock-load circuit adapted to provide the clock-load signal and the phase-adjusted clock-load signal, the clock-load signal having phases that are adjusted relative to misalignment between the clock-load signal and the reference clock signal, wherein the transmit-data module further includes a clock source adapted to provide a fast-clock signal having a clock rate and related period, the fast-clock signal being used by the clock-load circuit to adjust the phases of the clock-load signal by delaying the clock-load signal as a function of the related period of the fast-clock signal, wherein the clock-load circuit is further adapted to adjust the phase of the clock-load signal by delaying the clock-load signal for one period of the fast-clock signal for each cycle of the reference clock signal when the reference clock signal and the clock-load signal are misaligned.