Patent ID: 8543736

Claim:
A data processing circuit, comprising: a decoder, for decoding data; and at least three-stage circuits for receiving input data from at least a memory to output the generated output data to the decoder wherein the input data comprise a first set of data, a second set of data, and a third set of data; and the at least three-stage circuits comprise: a first-stage circuit, for sorting the input data according to the values of the input data and outputting the data with the same value to the decoder according to their order wherein the first-stage circuit outputs the first set of data having the first priority to the decoder and then the decoder generates a first data length according to the first set of data; the first-stage circuit outputs the second set of data having the second priority to the decoder according to the first data length and then the decoder generates a second data length according to the second set of data; the first-stage circuit outputs the third set of data having the third priority to the decoder according to the second data length and then the decoder generates a third data length according to the third set of data; and the decoder calculates the sum of the first data length, the second data length, and the third data length to generate a total effective bit length; a second-stage circuit, for replenishing data having a bit length equal to the total effective bit length from a third-stage circuit to the first-stage circuit according to the total effective bit length; and the third-stage circuit, for supplying data to the second-stage circuit to replenish data to reach a bit length equal to the total effective bit length and determining whether the third-stage circuit stores enough data to supply to the second-stage circuit according to the total effective bit length and determining whether the third-stage circuit receives data from the memory.