Patent ID: 7564714

Claim:
A NAND flash memory device comprising: a memory cell array including memory cells, wherein each memory cell is connected to bit lines and word lines; a page buffer unit including page buffer circuits disposed corresponding to the bit lines and configured to program data into selected memory cells or read data from the memory cells; a plurality of program cell decision units respectively connected to the page buffer circuits and configured to output cell program confirmation signals corresponding to program states of the memory cells; a X decoder and a Y decoder for selecting a word line of the memory cell array according to an input address; an IO controller configured to control data input to and output from the page buffer unit through the Y decoder, and including a detecting circuit configured to output a detection signal in the event that one or more of the memory cells are identified as programmed based on the cell program confirmation signals; and a voltage providing unit for changing a step of a program voltage according to the detection signal, wherein the voltage providing unit provides a program voltage.