Patent ID: 8693235

Claim:
An integrated circuit, comprising: a first single port SRAM array of a plurality of first bit cells arranged in rows and columns, each bit cell having a y pitch of distance Y 1 and an x pitch of distance X 1 , the ratio of X 1 to Y 1 being greater than or equal to 2, each of the plurality of bit cells forming a 6T SRAM cell of single fin finFET transistors and each of the first bit cells receiving a cell positive voltage supply CVdd from a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells arranged in rows and columns, each second bit cell having a y pitch of distance Y 2 and an x pitch of distance X 2 , the ratio of X 2 to Y 2 being greater than or equal to 3, each of the plurality of second bit cells further comprising a 6T SRAM cell including multiple fin finFET transistors and each of the second bit cells receiving a second cell positive voltage supply CVdd from a second voltage control circuit; wherein the ratio of X 2 to X 1 is greater than about 1.1.