Patent ID: 7361539

Claim:
A method of fabricating a semiconductor device structure, comprising: forming first and second field effect transistors (“FETs”), said first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying said first channel region, said second FET having a second channel region, a second source region, a second drain region and a second gate conductor overlying said second channel region, said first and second gate conductors being portions of a single elongated conductive member extending over both said first and second channel regions; forming a first stressed film to overlie said first and second FETs, said first stressed film for applying a stress having a first value; forming a stop layer to overlie said first stressed film; removing a portion of said first stressed film which overlies said second FET; forming a second stressed film to overlie said second FET, said second stressed film for applying a stress having a second value; planarizing said first and second stressed films at least until said stop layer is exposed; and forming an interlevel dielectric layer (“ILD”) overlying said first and second stressed films, such that said first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at said common boundary.