Patent ID: 8725950

Claim:
A processor comprising: a first processor core unit including a first processor core adapted to process first data, and a first cache memory adapted to store the first data; and a second processor core unit including a second processor core adapted to process second data, and a second cache memory adapted to store the second data; wherein the processor includes logic adapted to: (i) receive a selection of a first victim line from the first cache memory; (ii) identify a candidate line in the second cache memory by: (a) identifying a set of potential candidate lines for the first victim line, (b) evaluating a cache priority rule, in response to the receiving a selection of the first victim line, to prioritize the potential candidate lines for the first victim line, and (c) selecting the candidate line from the set of potential candidate lines based on the prioritization of the potential candidate lines; and (iii) store the first victim line in the candidate line in the second cache memory.