Patent ID: 7620126

Claim:
A frequency synthesizer lock detection system comprising: a reference clock that generates a reference clock signal; a frequency synthesizer including an input coupled to the reference clock and an output at which a synthesizer output signal is generated, the synthesizer output signal being locked in frequency to the reference clock signal; a distribution network, coupled to the synthesizer output, that distributes the synthesizer output signal as a downstream signal; a lock detector, coupled to the reference clock and the distribution network, that determines if the downstream signal is locked to the reference clock signal; and a receptor circuit coupled to the distribution network to receive the downstream signal therefrom, the receptor circuit comprising one of a microprocessor, a digital signal processor, a communication device and an information handling system; wherein the lock detector comprises: an observed pulse counter that determines an observed downstream count value by counting the number of pulses of the downstream signal that occur during a test window exhibiting a predetermined time duration; an expected pulse count unit that provides an expected downstream count value equal to the number of pulses of the downstream signal expected to occur during the test window; and a comparator, coupled to the observed pulse counter and the expected pulse count unit, that generates a lock signal to indicate that the downstream signal is locked to the reference clock signal when the observed downstream count value is approximately equal to the expected downstream count value.