Patent ID: 8060846

Claim:
A method of analyzing and correcting induced inductance effects in a circuit design, comprising: generating a test design containing a plurality of parallel wires conforming to a design technology utilized by the circuit design; determining a minimum number of wires of the plurality of parallel wires that are required to switch at substantially the same time to cause a glitch in a target wire of the plurality of parallel wires, the minimum number of wires denoting a switching density threshold; determining a timing window for each component of the circuit design; mapping the timing window to one or more portions of a clock period; incorporating the clock period portions for each timing window into a design database element for each component; analyzing the design database elements for each component to ensure satisfaction of density design rules for the circuit design; determining a switching density by comparing a number of switching elements to nonswitching elements; comparing the switching density to the switching density threshold; and inserting additional grounded metal wires into the circuit design until the switching density is less than the switching density threshold.