Patent ID: 7551156

Claim:
A liquid crystal display device comprising: a liquid crystal display panel including an upper substrate, a lower substrate on which N number gate lines and M number data lines cross each other, and a liquid crystal layer formed between the upper substrate and the lower substrate wherein the N number gate lines are divided into a plurality of groups: a gate driving circuit generating a first gate signal corresponding to the plurality of gate lines formed at each group, and sequentially outputting the first gate signal to all the group according to a first control signal from an exterior of the gate driving circuit; and a MUX circuit generating a second gate signal corresponding to the gate lines after receiving the first gate signal from the gate driving circuit, and sequentially supplying the second gate signal to the gate lines according to a plurality of second control signals from the exterior of the gate driving circuit, wherein the MUX circuit includes: a first group of switching transistors being divided into a first sub-group and a second sub-group, and which one side terminal is respectively connected to a plurality of gate lines formed each group in the liquid crystal display panel; a first inverter which one side and the other side terminal is commonly connected to switching transistors made of each of the first sub-group and the second sub-group for applying one signal of second control signals; a second group of switching transistors being divided into a third sub-group and a fourth sub-group, and which one side terminal is commonly connected to the other side terminal of switching transistors made of each of the first sub-group and the second sub-group; a second inverter which one side and the other side terminal is commonly connected to switching transistors made of each of the third sub-group and the fourth sub-group for applying another signal of second control signals; a third group of switching transistors being divided into a fifth sub-group and a sixth sub-group, and which one side terminal is commonly connected to the other side terminal of switching transistors made of each of the third sub-group and the fourth sub-group, which the other side terminal is commonly connected to each other for receiving the first gate signal; and a third inverter which one side and the other side terminal is commonly connected to switching transistors made of each of the fifth sub-group and the sixth sub-group for applying the other signal of second control signals.