Patent ID: 7884643

Claim:
A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH), the voltage level shifting circuit comprising: a first and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being connected to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being connected to a drain of the first PMOS transistor; a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS; a first switching device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor; and a first native NMOS transistor with a drain connected to the first switching device and a source connected to a drain of the first NMOS transistor, wherein both the first and second PMOS transistors are high voltage transistors and the first switching device is off when the VCCL is below a predetermined voltage level, and the first switching device is on when the VCCL is above the predetermined voltage level.