Patent ID: 8289760

Claim:
A memory device system, comprising: a plurality of stacked memory device dice connected to each other through a plurality of conductors, each of the memory device dice containing a plurality of memory cells; a logic die coupled to the memory device dice through a plurality of conductors, the logic die being operable to write data to and read date from the memory device dice responsive to a received memory command at a location corresponding to a received address; and a command processing circuit coupled to receive the commands and being coupled to the logic die and the memory device dice, the command processing circuit operating according to either an indirect operating mode or a direct operating mode, the command processing circuit being operable in the indirect operating mode to decode the received commands and to generate corresponding commands having a format that is different from the received commands and to couple the generated commands to the memory device dice, and being operable in the direct operating mode to apply the received commands to the memory device dice, wherein the command processing circuit includes a command register that is operable in the indirect operating mode to transmit commands and addresses to the memory device dice in a preset order and at preset times, and is operable in the direct operating mode to transmit commands and addresses to the memory device dice in the order and at the times the commands and addresses, respectively, are received by the command register.