Patent ID: 7681157

Claim:
The computerized method of decreasing processing time in multi-corner static timing analysis, the method comprising: determining an n number of parameters (P i ) defining a full process space {P 1 , P 2 , . . . P n } wherein the n number of parameters are organized in a parameter order from P 1 to P n , the full process space {P 1 , P 2 , . . . P n } including an n number of process sub-spaces each including parameters P i→n ; assigning a corresponding slack cutoff (c i ) {c 1 , c 2 , . . . c n } for each parameter of the n number of parameters, wherein each corresponding slack cutoff c i represents an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space {P i→n }; performing with a static timing analysis device a multi-corner timing analysis utilizing a plurality of the corresponding slack cutoffs (c i ) to output an indication of timing verification for one or more paths of an integrated circuit design, wherein said performing a multi-corner timing analysis includes: conducting a starting corner timing analysis to determine a starting corner slack for each of one or more predetermined paths of an integrated circuit design; comparing each starting corner slack to slack cutoff c 1 to determining any paths having a starting corner slack that fails the slack cutoff c 1 ; analyzing one or more remaining paths of the paths that fail the previous slack cutoff comparison by varying the next parameter P i in the parameter order, starting with P 1 , to each of its non-starting corner parameter values while holding any other unvaried parameter at its starting corner parameter value and holding any previously varied parameter at a corner parameter value that produced its corresponding worst slack value, said analyzing including: determining a worst slack value for each of the one or more remaining paths; comparing each worst slack value corresponding to varying P i with slack cutoff c i+1 ; and determining any paths that have a worst slack value corresponding to varying P i that fails the slack cutoff c i+1 ; and repeating said analyzing step for each parameter P i until no paths fail a slack cutoff comparison and/or said varying of P n−1 is performed; and generating a displayable image of the indication of timing verification.