Patent ID: 7082293

Claim:
A complimentary metal oxide semiconductor (CMOS) phase lock loop, comprising: an oscillator having a tuning input, and an output with a tunable frequency responsive to the tuning input; a mixer to mix the oscillator output with a second signal to produce a mixed signal; and a phase detector outputting an error signal which is a function of a phase difference between the mixed signal and an input signal, the error signal being applied to the tuning input, wherein the oscillator comprises a voltage controlled oscillator, the tuning input being responsive to a voltage of the error signal, the CMOS phase lock loop further comprising a bandpass filter to filter the mixed signal before being applied to the phase detector, the filtered mixed signal comprising a difference frequency between the tuned frequency of the oscillator output and a frequency of the second signal, a limiter to limit the filtered mixed signal from the filter before being applied to the phase detector, a charge pump disposed between the phase detector and the oscillator, and a loop filter disposed between the charge pump and the oscillator.