Patent ID: 7945872

Claim:
A computer-implemented method of analyzing a plurality of regions in a layout of an integrated circuit device for violation of a plurality of predetermined rules, the method comprising: subdividing the layout into a plurality of regions; performing rule checking locally, on each of multiple sets of polygons located within multiple corresponding regions of the layout, as to whether or not a rule in the plurality of predetermined rules is satisfied; generating data comprising a first subset of polygons selected within each set from each corresponding region, to be checked regardless of boundaries between regions; for each region of the layout, propagating a second subset of polygons from checking of said rule to checking of a next rule that follows said rule in a runset; at least one processor merging data generated from multiple regions, to yield merged data, at least by reconstituting a polygon in said layout from a plurality of portions of said polygon formed by said subdividing and located in a plurality of first subsets generated from corresponding regions; and performing rule checking globally on at least the merged data, including said polygon obtained by reconstituting and spanning across multiple regions, regardless of boundaries between the multiple regions, as to whether or not said rule is satisfied, thereby to identify, from within the merged data, a feature not previously identified by said performing rule checking locally.