Patent ID: 7696101

Claim:
A method used to form a semiconductor device, comprising: forming a patterned-first-support layer comprising a plurality of features over a layer to be etched, wherein each of the patterned-first-support layer features comprises first and second vertically oriented sidewalls; after forming the patterned-first-support layer, forming a patterned-first-top-masking layer comprising a plurality of spacers, with each of the patterned-first-top-masking spacers being formed on a respective one of the vertically oriented sidewalls of a respective one of the patterned-first-support layer features; prior to removing the patterned-first-support layer, forming a patterned-second-support layer comprising features, wherein each of the patterned-second-support layer features contacts a respective one of the patterned-first-top-masking layer spacers, and wherein each of a plurality of the patterned-second-support layer features is separated from an adjacent one of the patterned-second-support layer features by a gap; prior to removing the patterned-first-support layer and the patterned-second-support layer, forming a patterned-second-top-masking layer which fills the gaps and comprises a plurality of spacers, wherein each of the plurality of patterned-second-top-masking layer spacers is separated from an adjacent one of the patterned-first-top-masking layer spacers by a respective one of the plurality of patterned-second-support layer features; removing the patterned-first-support layer and the patterned-second-support layer; and subsequent to removing the patterned-first-support layer and the patterned-second-support layer, etching the layer to be etched using patterned-first-top-masking layer and the patterned-second-top-masking layer as a mask.