Patent ID: 7149953

Claim:
An apparatus comprising: an m-bit symbol metric computer that is operable to calculate a plurality of m-bit symbol metrics that correspond to a symbol of an LDPC (Low Density Parity Check) coded signal, wherein the symbol has m-bits and wherein the LDPC coded signal includes a plurality of symbols; a symbol node calculator that is operable to calculate a plurality of bit metrics using the plurality of m-bit symbol metrics; a bit node calculator that is operable to calculate soft messages corresponding to the m-bits of the symbol using the plurality of bit metrics; a check node operator that is operable to provide a plurality of edge messages to the bit node calculator, wherein: the plurality of edge messages corresponds to a plurality of edges that communicatively couple a plurality of bit nodes to a plurality of check nodes within an LDPC bipartite graph that corresponds to an LDPC code by which the LDPC coded signal is generated; the bit node calculator is operable to update the plurality of edge messages provided from the check node operator using the plurality of bit metrics calculated by the symbol node calculator; the bit node calculator is operable to perform min†− (min-dagger minus) processing when updating the plurality of edge messages; the bit node calculator is operable to provide the updated plurality of edge messages to the check node operator while the bit node calculator is operable to update the soft messages corresponding to the m-bits of the symbol using the updated plurality of edge messages; and the bit node calculator and the check node operator operate cooperatively to perform iterative decoding and to output best estimates of the m-bits of the symbol of the LDPC coded signal using latest updated soft messages corresponding to the m-bits of the symbol of the LDPC coded signal.