Patent ID: 7861067

Claim:
An adjustable cycle pipeline system comprising: a fetch stage for fetching information associated with an operation; a decode stage for decoding instructions including determining a number of execution sub-clock cycles utilized in executing each of said instructions and forwarding said number of execution sub-clock cycles to a pipeline stage clock if said fetch stage, said decode stage and a write stage can also be performed within said number of execution sub-clock cycles, wherein said decode stage includes a decode operation time table that maps each of said instructions to said number of execution sub-clock cycles utilized in executing each of said instructions; an execution stage for executing each of said instructions in accordance with said number of execution sub-clock cycles, wherein a sub-clock that generates said execution sub-clock cycles controls operations in said execution stage; said pipeline stage clock for generating said pipeline stage cycle, wherein said pipeline stage clock includes a counter for counting execution sub-clock cycles and when said counter reaches said number of pipeline sub-clock cycles received from said decode stage, a trigger edge of said pipeline stage clock is asserted to initiate a new pipeline stage cycle; and a sub-clock for generating said execution sub-clock cycles, wherein said execution sub-clock cycles are faster than said pipeline stage cycles; said write stage for writing results.