Patent ID: 7663403

Claim:
A high-speed asynchronous digital signal level conversion circuit comprising: a signal level converter for converting an input signal of a first voltage level into a signal of a second voltage level, the signal level converter including: first and second PMOS transistors cross-coupled with each other between the second power source voltage and the first and second nodes; and first and second NMOS transistors respectively connected between the first and second nodes and a ground voltage, and respectively receiving the input signal and an inverted input signal through gates; and a switching circuit for connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed, the switching circuit including: first and second switch controllers for outputting control signals by detecting variations from the input signal and the inverted input signal in response to drain voltages of the first and second NMOS transistors; wherein the first switch controller comprises second and fourth inverters connected in series to the gate of the second PMOS transistor and the drain of the first NMOS transistor, and wherein the second switch controller comprises first and third inverters connected in series to the gate of the first PMOS transistor and the drain of the second NMOS transistor; and first and second switches respectively connected to drains of the first and second NMOS transistors, and turned on/off in response to the control signals, wherein the first switch is a third PMOS transistor and the second switch is a fourth PMOS transistor, and wherein gate, drain, and source of the third PMOS transistor are connected to an output of the fourth inverter, an output of the first inverter, and the drain of the first NMOS transistor, respectively, and gate, drain, and source of the fourth PMOS transistor are connected to an output of the third inverter, an output of the second inverter, and the drain of the second NMOS transistor, respectively.