Patent ID: 8443118

Claim:
A direct memory access (DMA) controller comprising: a transmit circuit configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory, where there is a data structure for each DMA channel that is in use; and a data flow control circuit coupled to the transmit circuit and configured to control processing by the transmit circuit for each DMA channel, wherein each DMA descriptor in a given DMA channel comprises a serialize indication that indicates whether or not the DMA transfer described by the DMA descriptor is to be serialized with one or more subsequent DMA transfers described by one or more subsequent DMA descriptors in the given DMA channel, and wherein the data flow control unit is configured to delay processing of the subsequent DMA descriptors responsive to the serialize indication indicating serialization in a current DMA descriptor in the given DMA channel, and wherein the transmit circuit is configured to perform parallel processing for two or more DMA transfers in the given DMA channel, wherein the transmit circuit is configured to prevent parallel processing in the given DMA channel of the subsequent DMA transfer with the current DMA transfer in response to the serialize indication in the current DMA descriptor indicating serialization.