Patent ID: 7562285

Claim:
A mechanism, comprising: a link interface, wherein the link interface is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information; a first means for dynamically generating first error-detection information for at least a portion of write data; a second means for transmitting the write data, wherein the second means is coupled to the link interface; a first delay element coupled to an output from the first means; a third means for receiving second error-detection information corresponding to at least the portion of the write data, wherein the third means is coupled to the link interface; and error-detection logic coupled to an output from the first delay element and an output from the third means, wherein the error-detection logic is to detect errors in at least the portion of the write data based on the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.