Patent ID: 7939881

Claim:
A semiconductor device comprising: a semiconductor substrate; a source region and a drain region formed on said semiconductor substrate at a prescribed interval; a first impurity region, formed in contact with said source region, including a channel region; a drift layer formed between said first impurity region and said drain region; and a gate electrode formed through a gate insulating film provided on said first impurity region and said drift layer, wherein said gate electrode consists of two regions including a first conductivity type second impurity region opposed to said first impurity region and a third impurity region capable of forming a depletion layer, and wherein an end of said first impurity region closer to said drain region is formed substantially on an extension of a boundary, between said second impurity region and said third impurity region, extending in a direction substantially perpendicular to a direction along said channel region between said second impurity region and said third impurity region or formed on said source region's side of said extension of the boundary between said second impurity region and said third impurity region, and wherein said gate electrode includes a silicide film which formed selectively only on said second impurity region.