Patent ID: 7260711

Claim:
Apparatus for processing data, said apparatus comprising: (i) a shifting circuit; (ii) a bit portion selecting and combining circuit; and (iii) an instruction decoder, responsive to an instruction to control said shifting circuit and said bit portion selecting and combining circuit, for performing an operation upon a data word Rn and a data word Rm, wherein said operation yields a value given by: (a) selecting a first portion of bit length A of said data word Rn extending from one end of said data word Rn; (b) selecting a second portion of bit length B of said data word Rm subject to an arithmetic right shift by a right-shift amount specified as a shift operand within said instruction, said right-shift amount being independent of said bit length A of said first portion; and (c) combining said first portion and said second portion to form respective different bit position portions of an output data word Rd.