Patent ID: 7498637

Claim:
A semiconductor memory including a static type memory cell comprising: first and second driver transistors each having an FD-SOI structure in which a SOI layer is completely depleted, the first and second driver transistors being n-type transistors; first and second storage nodes for storing data therein; a first transfer transistor connected between one of a bit line pair for access to the memory cell and the first storage node; and a second transfer transistor connected between the other one of the bit line pair and the second storage node, wherein each of said first and second driver transistors comprises a semiconductor layer, including a well layer, formed in a semiconductor substrate, and a buried oxide film layer provided on said well layer; wherein source nodes of said first and second driver transistors are connected to a ground potential line, wherein said well layer of the first driver transistor is connected to a gate node of the first driver transistor via a first contact which penetrates said semiconductor layer, wherein said well layer of the second driver transistor is connected to a gate node of the second driver transistor via a second contact which penetrates said semiconductor layer, wherein said static type of memory cell has only four transistors constituted by said first and second transfer transistors and said first and second driver transistors, wherein a well layer of said first transfer transistor is connected to said second storage node, wherein a well layer of said second transfer transistor is connected to said first storage node, and wherein, in said static type of memory cell, well nodes of the first transfer transistor and first driver transistor are formed integral with each other, and well nodes of the second transfer transistor and second driver transistor are formed integral with each other.