Patent ID: 8466731

Claim:
A device comprising: a first positive power supply line carrying a first positive power supply voltage; a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage; a protection circuit comprising a MOS transistor, with the MOS transistor comprising a source-to-drain path; a diode, wherein the source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines, and wherein the diode is forward biased by the first and the second positive power supply voltages; and a control bias circuit comprising: an output coupled to a gate of the MOS transistor, wherein the control bias circuit is configured to output a bias voltage to the gate, with the bias voltage being proportional to, and smaller than, the first positive power supply voltage; and a first resistor and a second resistor coupled in series between the first power supply line and a VSS line, with a node between the first and the second resistors coupled to the gate of the MOS transistor.