Patent ID: 8359456

Claim:
A system for testing a computerized device, the computerized device comprising a plurality of processors, the computerized device comprising a memory device having a plurality of memory addresses, each of the plurality of processors being configured to perform the steps of: randomly determining an access permission associated with a memory address of the plurality of memory addresses, wherein the access permission is determined based upon a first random determination; randomly selecting an address of the plurality of addresses based on the access permission, wherein the address is based upon a second random determination; generating a test for the processor using the randomly determined access permission and the randomly selected address; running the test by executing an access operation in the address selected in said selecting the address; wherein each of the plurality of processors are configured to separately make the same random determinations of access permissions; and wherein the results of the tests for each processor are used to determine a bug in a functionality of one or more of the plurality of processors.