Patent ID: 8397152

Claim:
A method of detecting an attack by fault injection on a memory device comprising at least one group of memory cells configured to store at least one block of bits comprising data bits and m parity bits, each bit of the at least one block of bits being read into a corresponding one of the at least one group of memory cells, the method comprising: performing a parity check based upon a read value of each data bit and a read value of each of the m parity bits; inserting reference memory cells between at least some memory cells of the at least one group of memory cells to create separate packets of m memory cells; storing a reference bit in each reference memory cell, the reference bit having a reference value modifiable during an attack by fault injection; storing m bits of an associated one of the at least one block in each packet of m memory cells when m is greater than 1, the m bits being associated with different parities; and performing a check on a value of each reference bit when reading the at least one block of bits.