Patent ID: 7239581

Claim:
In a multiprocessor system comprising a plurality of processor modules, each one of the plurality of processor modules comprising an internal clock, a method for maintaining a substantially consistent running clock for the multiprocessor system, the method comprising: (a) designating one processor module to be a master processor module having a master internal clock; (b) designating each other processor module to be a slave processor module having a slave processor module internal clock; and (c) synchronizing each slave processor module internal clock by, for each slave processor module, (i) requesting, by the slave processor module at a first time according to the slave processor module internal clock, a current time according to the master internal clock; (ii) receiving, by the slave processor module at a second time according to the slave processor module internal clock, the current time according to the master internal clock; (iii) computing, by the slave processor module, an expected time by using at least the first time according to the slave processor module internal clock and the second time according to the slave processor module internal clock; (iv) determining, by the slave processor module, whether the expected time differs from the received current time according to the master internal clock; and (v) upon determining that the expected time differs from the received current time according to the master internal clock, correcting, by the slave processor module, the slave processor module internal clock.