Patent ID: 8900960

Claim:
A method comprising: forming a gate structure over a semiconductor substrate; performing a first implantation process with a first dopant on the substrate, thereby forming a lightly doped source and drain (LDD) region in the substrate, the LDD region being interposed by the gate structure; performing a second implantation process with a second dopant on the substrate by performing a tilt-angle ion implantation process, the second dopant being opposite the first dopant, thereby forming a doped region in the substrate, the doped region being interposed by the gate structure and spaced a distance from the gate structure; and after performing the first and second implantation processes, forming source and drain features on each side of the gate structure, wherein forming the source and drain features includes performing a first etching process and a second etching process to the semiconductor substrate to form a recess that defines a source and drain region in the semiconductor substrate, wherein the first etching process is different than the second etching process.