Patent ID: 7189662

Claim:
A method of forming a semiconductor construction, comprising of the following five steps in any order relative to one another: (1) forming at least a portion of a first gate oxide by exposure of a semiconductor material to deuterium-enriched steam, the first gate oxide having a first thickness; (2) forming at least a portion of a second gate oxide by exposure of a semiconductor material to deuterium-enriched steam, the second gate oxide having a second thickness which is at least about 15A less than the first gate oxide; (3) forming at least a portion of an oxide over a defined location of a conductively-doped region of a semiconductor material by exposure of the semiconductor material to deuterium-enriched steam; (4) forming at least a portion of an isolation region by exposure of a semiconductor material to deuterium-enriched steam; and (5) subjecting a semiconductor assembly to an anneal at a temperature of greater than or equal to about 350° C. while exposing the assembly to a deuterium-enriched ambient.