Patent ID: 7418612

Claim:
A semiconductor device with a power down mode, comprising: a power down detecting block for generating a power down mode signal by detecting that the power down mode is activated; a power source control block for producing a power control signal whose ratio of an enable period to a disable period is determined by the power down mode signal a current saving block whose driving current requirement is reduced in the power down mode; and a power switching block for controlling the power to the current saving block in response to the power control signal, wherein the power source control block generates the power control signal having a clock form during the power down mode, wherein the power source control block includes an oscillator for producing a reference pulse; a frequency divider for generating a divided pulse by frequency-dividing the reference pulse; and a signal synthesizer for producing the power control signal by logically operating the reference pulse and the divided pulse, wherein the oscillator has an odd number of inverters and an oscillation trigger for controlling an oscillating operation in response to the power down signal.