Patent ID: 7363467

Claim:
A logic circuit comprising: data flow logic; control flow logic to select and fetch a trace descriptor for processing, the fetched trace descriptor including at least one dependency descriptor, the control flow logic to dispatch to the data flow logic a dependency descriptor including dependency information having live-in information and live-out information for an instruction sequence and an address of the instruction sequence; the data flow logic coupled to the control flow logic to receive the dispatched dependency descriptor, to fetch the instruction sequence using the address from the received dependency descriptor, and to execute the instruction sequence according to the dependency information in the received dependency descriptor; and an issue window coupled between the control flow logic and the data flow logic, the issue window to store the dependency descriptor dispatched from the control flow logic wherein the issue window includes a first portion to store active dependency descriptors and a second portion to store inactive dependency descriptors, wherein an inactive dependency descriptor is to remain in the second portion until data to be used by the corresponding instruction sequence is available.