Patent ID: 7463466

Claim:
An integrated circuit with an electrostatic discharge (ESD) protection circuit therein, comprising: a plurality of bonding pads including at least an input/output pad and at least a power pad; a plurality of ESD units with each ESD unit having a one-to-one correspondence with one of the bonding pads, and each ESD unit having: a first diode, wherein the anode of the first diode is connected to a corresponding bonding pad; a second diode, wherein the cathode of the second diode is connected to a corresponding bonding pad; and an ESD clamping device having a first terminal and a second terminal, wherein the first terminal is connected to the cathode of the first diode and the second terminal is connected to the anode of the second diode, and when an ESD pulse is applied to a point between the first terminal and the second terminal, the ESD clamping device will transfer the electrostatic charges from the first terminal to the second terminal; a first ESD bus connected to the cathode of the first diode in the ESD units, wherein the first ESD bus is not connected to any one of the power pads inside the integrated circuit; and a second ESD bus connected to the anode of the second diode in the ESD units, wherein the bonding pads includes a first power pad such that the first power pad is connected to a power source having the highest voltage inside the integrated circuit when the integrated circuit operates, and the integrated circuit further includes a first metal-oxide-semiconductor (MOS) transistor for fixing the voltage in the first ESD bus such that a first source/drain of the first MOS transistor is connected to the first ESD bus and a second source/drain of the first MOS transistor is connected to the first power pad.