Patent ID: 7610454

Claim:
A memory address decoding method for determining an objective section of a given address in a memory, wherein the memory is formed by at least one section with at least one memory unit, the method comprising: assigning an address to each memory unit according to the memory size of the section; obtaining at least one bit-pattern of each section according to the common pattern of the bit of the addresses; and comparing the given address with each bit-pattern to determine the objective section of the given address, and sending a plurality of comparison signals after comparing the given address with those of each bit-pattern; the plurality of comparison signals being generated by performing a first logical AND of a mask bit generated from the bit patterns and an associated bit of the given address, performing a first logical NXOR of a result of the first logical AND and a standard address generated from the bit-patterns, and performing a second logical AND of an output of the first logical NXOR and an output of a second logical NXOR; wherein the addresses of the memory units located in the section with greatest size are firstly assigned, and the addresses of the memory units located in the section with smallest size are lastly assigned.