Patent ID: 7902594

Claim:
A semiconductor component comprising: a semiconductor substrate; an insulating region provided on the semiconductor substrate; a plurality of wire-form semiconductor layers of a first conductivity type aligned on the insulating region substantially parallel to each other and each having an upper surface and a side surface; a plurality of source/drain regions of a second conductivity type provided to the wire-form semiconductor layers, respectively, each of the source/drain regions of each wire-form semiconductor layer being apart from each other; a plurality of channel regions provided between the source/drain regions, respectively; a first insulating film provided on the upper surface and the side surface of each channel region; and a gate electrode provided on the first insulating film and continuously provided to cross the wire-form semiconductor layers, wherein a length of each channel region measured perpendicularly to a current flowing through the wire-form semiconductor layers in a wire direction and in parallel to a surface of the semiconductor substrate is equal to or below twofold a maximum depletion layer width determined based on an impurity concentration in the channel regions, each interval between the wire-form semiconductor layers is equal to or below twofold an interval between the upper surface of each wire-form semiconductor layer and the gate electrode, and a specific dielectric constant of at least a part of a surface of the insulating region is lower than 3.9.