Patent ID: 8716772

Claim:
A DRAM device, comprising: an array comprising a plurality of memory cells, the array including: a plurality of memory cell contacts; a plurality of digitline contacts; a plurality of wordline pairs oriented in a first direction, wherein a wordline pair of the plurality of wordline pairs has a space between wordlines that is oriented in the first direction; a plurality of dual bit active areas, wherein a dual bit active area of the plurality of dual bit active areas has a substantially longitudinal axis; and a plurality of digitlines, wherein a digitline of the plurality of digitlines is coupled to at least one of the plurality of digitline contacts, wherein the plurality of digitlines are oriented in a direction orthogonal to the first Direction, contacts disposed in the space between the wordline pair of the plurality of wordline pairs are all digitline contacts, and the longitudinal axis of the dual bit active area of the plurality of dual bit active areas is oriented at an angle with respect to the plurality of digitlines.