Patent ID: 7630226

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array including a plurality of memory cells arranged in a grid configuration, each of the plurality of memory cells comprising an irreversible storage element adapted to write data by breaking down an insulating film, with a write voltage being applied to its one end, a first transistor with its one end being connected to the other end of the irreversible storage element, and a second transistor with its one end being connected to the other end of the irreversible storage element; a plurality of write word lines connected to a gate of the first transistor to select the memory cell in a row direction in writing data; a plurality of read word lines connected to a gate of the second transistor to select the memory cell in a row direction in reading data; write bit lines connected to the other end of the first transistor to write data to the memory cells; read bit lines connected to the other end of the second transistor to read data from the memory cells; a row decoder selectively driving the write word lines and the read word lines according to an address signal; and a write-disturb prevention circuit for, in writing data, charging the read bit lines to a certain voltage.