Patent ID: 8629354

Claim:
A method for manufacturing a multi-layer PCB, comprising: forming a first conductive pattern layer and a second conductive pattern layer on upper and lower surfaces of a first insulating layer, respectively; forming a first hole for receiving a first integrated circuit in the first insulating layer by removing the first conductive pattern layer of a predetermined area; arranging the first integrated circuit in the first hole so that a lower surface of the first integrated circuit makes direct contact with the second conductive pattern layer without an insulating layer therebetween; stacking a second insulating layer and a third conductive pattern layer on the first conductive pattern layer and an upper surface of the first integrated circuit; attaching an adhesive tape on the second conductive pattern layer of a predetermined area for receiving a second integrated circuit; stacking a third insulating layer and a fourth conductive pattern layer on the second conductive pattern layer including the adhesive tape; cutting the fourth conductive pattern layer and the third insulating layer along a rim of the adhesive tape; forming a second hole for receiving the second integrated circuit in the third insulating layer by taking off the adhesive tape so that the third insulating layer and the fourth conductive pattern layer, which are disposed at the upper part of the adhesive tape, are simultaneously removed; arranging the second integrated circuit in the second hole in such a manner that a lower surface of the second integrated circuit makes direct contact with the second conductive pattern layer without an insulating layer therebetween; stacking a fourth insulating layer and a fifth conductive pattern layer on the fourth conductive pattern layer and an upper surface of the second integrated circuit; and forming a plurality of contact-holes in the second insulating layer and the fourth insulating layer so as to allow inter-layer electric connection.