Patent ID: 6865707

Claim:
A test data generator for generating test data patterns for testing a circuit, comprising: (a) a frequency multiplication circuit, configured to increase a low clock frequency of an input clock signal received by a test unit by a predetermined clock frequency multiplication factor, and further configured to generate an output clock signal with a high clock frequency for a circuit to be tested; (b) a plurality of data registers, each data register of said plurality of data registers configured to store a predetermined number of read test data words; (c) a multi-row set of register selection control data vectors, said set of register selection control data vectors configured to be received by the test unit with the low clock frequency of the input clock signal, each individual register selection control data vector of said multi-row set of register selection control data vectors configured to contain register selection control data at associated positions, wherein a number of register selection control data in a register selection control data vector of said multi-row set of register selection control data vectors is generally equal to the clock frequency multiplication factor; (d) at least one multiplexer configured to switch through a test data word read from said data registers with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of said multi-position register selection control data vector, such that during a clock period of the output clock signal, the test data word is switched through by the multiplexer when a signal edge of the output clock signal is specified by a register selection control datum of said register selection control data at an associated position of the register selection control data vector.