Patent ID: 7253526

Claim:
A semiconductor packaging substrate, comprising: a laminated circuit structure having a first surface and a second surface, the laminated circuit structure comprising: a plurality of patterned internal metal layers stacked up wherein the number of the internal metal layers is equal to or larger than four; a plurality of internal insulation layers, wherein one of the internal insulation layers is interposed between two adjacent internal metal layers, and the middle one of the internal insulation layers is an insulation core; and at least one contact via formed through each of the internal metal layers and each of the internal insulation layers, such that at least two of the internal metal layers are electrically connected to one another; and a build-up circuit structure on the first surface and the second surface of the laminated circuit structure, the build-up circuit structure comprising: a first external insulation layer having at least one first via and a second external insulation layer having at least one second via respectively arranged on the first surface and the second surface of the laminated circuit structure; and a patterned first external metal layer located on the first external insulation layer and a patterned second external metal layer located on the second external insulation layer, wherein the first external metal layer is electrically connected to one of the internal metal layers by the first via, and the second external metal layer is electrically connected to another of the internal metal layers of the laminated circuit by the second via, and wherein the first external metal layer has a plurality of first externally exposed areas and the second external metal layer has a plurality of second externally exposed areas.