Patent ID: 6873197

Claim:
A scan flip-flop circuit comprising: a usual mode data input-terminal; a scan-in data input terminal; an output terminal; a first master latch circuit, connected between said usual data input terminal, for receiving usual mode data at said usual data input terminal in synchronization with a first clock signal; a second master latch circuit, connected to said scan-in data input terminal and said output terminal, for receiving scan-in data at said scan-in data input terminal in synchronization with first and second scan clock signals; and a slave latch circuit, connected between said first master latch circuit and said output terminal, for receiving an output signal of said first master latch circuit in synchronization with said first clock signal and said second scan clock signal, said slave latch circuit comprising a control circuit, connected between an output of said first master latch circuit and said output terminal, for controlling transfer of said usual mode data to said output terminal in synchronization with a second clock signal independent of said first clock signal.