Patent ID: 8234479

Claim:
A processor-based system, comprising: a central processing unit (“CPU”); a system controller coupled to the CPU via a communications path, the system controller having an input port and an output port; an input device selected from the group consisting of a keyboard and a mouse coupled to the CPU through the system controller; an output device selected from the group consisting of a printer device and a display device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a memory hub controller storing a plurality of memory requests and outputting each stored memory request responsive to a flow control signal generated as a function of received memory request status signals, the memory hub controller further receiving and storing read data and the memory request status signals, the memory hub controller outputting the stored read data; and a plurality of memory modules coupled to the memory hub controller via a high-speed link, wherein the memory modules further comprise: a memory hub having a response generator, the response generator having a first input terminal operable to receive read data signals from the memory controller, a second input terminal operable to receive read status signals, the read status signals identifying read requests corresponding to each read data signal, and an output terminal, the response generator operable to generate read responses each comprising one of the read data signals and corresponding read status signals, the response generator further being operable to transmit the read responses from the output terminal to the memory hub controller.