Patent ID: 8650511

Claim:
A method comprising: receiving an integrated circuit (IC) design layout; applying an optical proximity correction (OPC) modification to the IC design layout; before performing a lithography process check (LPC), identifying a critical area of the OPC-modified IC design layout, wherein the identifying the critical area of the OPC-modified IC design layout comprises: separating the OPC-modified IC design layout into more than one pattern category; defining criteria for each pattern category; applying the criteria to each pattern category to filter out a first set of critical areas in the OPC-modified IC design layout; providing a simulated IC pattern of the first set of critical areas; and identifying a second set of critical areas from the simulated IC pattern of the first set of critical areas; and applying a lithography process check (LPC) modification to the OPC-modified IC design layout if the critical area of the OPC-modified IC design layout exhibits a hotspot.