Patent ID: 7221581

Claim:
A memory circuit comprising: a plurality of elementary storage cells, the elementary storage cells being arranged in rows and in columns thus forming a storage matrix, each elementary storage cell storing a logic level “0” or “1”, each logic level corresponding to a low voltage or a high voltage that is specific to it, wherein each elementary storage cell of the same column comprises at least one link transistor connecting the elementary storage cell to at least one same bit line, the at least one link transistor being a transistor of the n-MOS type whose substrate is biased at a substrate voltage, wherein the memory circuit comprises at least two biasing circuits, wherein the elementary storage cells of the same column are divided into at least two groups of cells, each group of cells being associated with a respective biasing circuit capable of receiving a group selection signal, the biasing circuit being connected to the cells of its associated group in order to ensure that the substrate voltage and low voltage are the same when the associated group is selected, and in order to ensure that the potential difference between the substrate voltage and the low voltage is negative when the associated group is not selected, and wherein the biasing circuit supplies the low voltage to the elementary storage cells of its associated group, the low voltage being equal to the substrate voltage when the group is selected, or being equal to a higher voltage than the substrate voltage when the group is not selected.