Patent ID: 8716844

Claim:
A chip package, comprising: a substrate; a signal conducting pad disposed on the substrate; a ground conducting pad disposed on the substrate; a first conducting layer disposed on the substrate and electrically connected to the signal conducting pad, wherein the first conducting layer extends from an upper surface of the substrate towards a lower surface of the substrate along a first side surface of the substrate, and the first conducting layer protrudes from the lower surface; a second conducting layer disposed on the substrate and electrically connected to the ground conducting pad, wherein the second conducting layer extends from the upper surface of the substrate towards the lower surface of the substrate along a second side surface of the substrate, and the second conducting layer protrudes from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer.