Patent ID: 7146451

Claim:
An apparatus for interfacing a microprocessor to a peripheral device via a peripheral component interconnect (PCI) protocol bus, the apparatus comprising: a first-in-first-out (FIFO) register for accumulating data units being exchanged between the microprocessor and the peripheral device; and a controller operable to: monitor a plurality of characteristics of data units in the FIFO register; determine whether the characteristics satisfy any of a plurality of preset criteria; and initiate transferring of the data units from the FIFO register to the peripheral device by way of the PCI protocol bus in response to any one of the plurality of preset criteria being satisfied by the characteristics of the data units in the FIFO register so that bandwidth on the PCI protocol bus is used efficiently for transferring the data units wherein the controller is configured to initiate transferring of the data units from the FIFO register to the peripheral device by way of the PCI protocol bus whenever the controller detects that the processor is attempting to communicate with another device.