Patent ID: 6900085

Claim:
A method of forming non-volatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region comprising memory cells and a peripheral region, wherein word lines in the core region connecting the memory cells are spaced apart by about 1 μm or less; forming one or more insulating layers for one or more electrostatic discharge protection transistors and one or more other transistors in the peripheral region; forming a poly layer over the insulating layers; patterning electrostatic discharge protection transistors and other transistors from the insulating layers and the poly layer; depositing spacer material over the electrostatic discharge protection transistors and the other transistors; etching the spacer material to form spacers; and with the spacers in place and without masking the other transistors, heavily doping source and drain regions for the electrostatic discharge protection transistors to provide channel lengths for the electrostatic protection transistors of about 1 μm or less.