Patent ID: 8027184

Claim:
A semiconductor storage device comprising: a plurality of reading blocks collaterally arranged in a second direction, wherein each of said plurality of reading blocks includes: a plurality of first wirings extended in a first direction different from said second direction, a plurality of second wirings extended in said second direction, and a plurality of resistive storage elements arranged at respective points where said plurality of first wirings and said plurality of second wirings intersect and storing data based on variations of resistance values, wherein each of said plurality of resistive storage elements is connected to a corresponding first wiring among said plurality of first wirings at one end, and connected to a corresponding second wiring among said plurality of second wirings at the other end; a plurality of third wirings extended in said second direction and provided correspondingly to said plurality of second wirings; a plurality of first reading switches arranged between each of said plurality of third wirings and said corresponding second wiring among said plurality of second wirings in each of said plurality of reading blocks; a first control circuit controlling to turn on and off said plurality of first reading switches and supplying a predetermined current or voltage to said plurality of first wirings; and a plurality of evaluating circuits connected to said plurality of third wirings and evaluating said currents or voltages, wherein when data is read from each of said plurality of resistive storage elements, said first control circuit selects a selection reading block from said plurality of reading blocks by said plurality of first reading switches, selects a selection first wiring from said plurality of first wirings in said selection reading block and supplies said predetermined current or voltage, and said plurality of evaluating circuits executes said evaluations of said currents or voltages in said plurality of third wirings.