Patent ID: 7397095

Claim:
A semiconductor device comprising: a substrate including first and second regions; a first gate electrode disposed on the substrate in the first region and formed of a first metal silicide; a second gate electrode disposed on the substrate in the second region and formed of a second metal silicide including the same metal as that of the first metal silicide; and a gate insulating layer interposed between the substrate and the first gate electrode, and between the substrate and the second gate electrode, wherein the gate insulating layer brings about a Fermi pinning effect increasing or decreasing an intrinsic work function of the first and second metal silicides, and wherein the first gate electrode formed of the first metal silicide has a height that is less than a height of the second gate electrode formed of the second metal silicide, such that the first metal silicide has a lower silicon concentration than the second metal silicide so that the Fermi pinning effect provided to the first gate electrode is less effective than that provided to the second gate electrode.