Patent ID: 8117587

Claim:
A programmed system-on-a-chip computer for embedded systems comprising: a) a microcontroller chip having: i) at least one on-chip CPU core, ii) on-chip memory including an on-chip programmable non-volatile memory and an on-chip RAM, iii) an on-chip communications interface adapted to be connected to a user terminal and configured to receive and transmit source code symbolic information, iv) I/O pins adapted to interface between the microcontroller chip and a system in which the microcontroller chip is to be embedded, and v) I/O registers connected to the I/O pins for reading current pin states and storing output pin data; and b) an operating system including a trusted layer which is wholly programmed into the on-chip programmable non-volatile memory and which is configured to run on the CPU core, the trusted layer including: A) a compiler configured to compile the source code symbolic information input by a user through the user terminal into a target program to be stored in the on-chip memory; B) a non-volatile memory controller configured to save the target program to the on-chip programmable non-volatile memory; and C) an interrupt service module including: I) an on-chip event detector which is configured to detect an asynchronous on-chip event specified in the target program during execution of the target program; and II) trampoline code which is configured to invoke, in response to the event detected by the on-chip event detector, an application-level interrupt handler which handles an interrupt specified for the event by executing a specific portion of the target program; wherein the trusted layer is configured to run the target program in an application layer, wherein the compiler is configured to initially compile the source code symbolic information input by the user to a delta portion of the target program which is stored in the on-chip RAM, and wherein the trusted layer further includes: D) a code access module which is configured to merge the delta portion of the target program stored in the on-chip RAM with a base portion of the target program stored in the on-chip programmable non-volatile memory; E) a pin controller for selectively configuring at least one of the I/O pins of the microcontroller chip, wherein each I/O pin configured by the pin controller is configured as one of an input pin and an output pin; and F) a variable access module configured to define at least one pin variable, wherein each pin variable defined by the variable access module is bound to one of the I/O pins configured by the pin controller through one of the I/O registers, wherein the variable access module is configured in such a manner that manipulation of each pin variable bound to one of the I/O pins configured as an output pin by the pin controller will cause a state of the output pin to change correspondingly, and examination of each pin variable bound to one of the I/O pins configured as an input pin by the pin controller will cause a state of the input pin to be detected.