Patent ID: 7425720

Claim:
A semiconductor device comprising: a first interconnection layer being provided as an upper layer on a semiconductor substrate and including wires arranged facing each other with a preset spacing in-between to form first and second terminals with a gap therebetween; a second interconnection layer being provided adjacent to said first interconnection layer and including a wire arranged vertically above said first and second terminals in a superposed relationship to form a third terminal; and a variable electrical conductivity member arranged in said gap and vertically between said first and second terminals of said first interconnection layer and said third terminal of said second interconnection layer so that said variable electrical conductivity member is in direct contact with said first, second and third terminals; said variable electrical conductivity member forming a switch element for varying the electrical conductivity across said first and second terminals by a signal applied to said third terminal; and wherein the state of connection between said first and second terminals of said switch element is variably set to a shorted state, an open-circuited state or to a state intermediate between said shorted and open-circuited states.