Patent ID: 6970995

Claim:
A computer system, comprising: a memory unit; a bus coupled to said memory unit for retrieving program instructions therefrom; and a processor coupled to said bus, wherein said processor comprises a register renaming system that includes: an instruction window that comprises a plurality of storage locations each of which stores a single program instruction, and wherein only a subset of the plurality of storage locations may be filled with new program instructions retrieved from said memory in a single processor cycle; control logic that assigns one of a plurality of tags to a new program instruction in said instruction window, each of said plurality of tags uniquely identifying a register for storing a result corresponding to a program instruction in said instruction window; a data dependency checker that determines if said new program instruction is dependent on another program instruction in said instruction window by comparing a source register address of said new program instruction with a destination register address of said other program instruction in said instruction window; and tag assignment logic that outputs a renamed source register address for said new program instruction, wherein said renamed source register address comprises a tag assigned to said other program instruction in said instruction window if said new program instruction is dependent on said other program instruction.