Patent ID: 8554514

Claim:
A test apparatus configured to receive, from a device under test, a clock signal and a data sequence, which is transmitted synchronously with the clock signal and which contains n (n represents an integer of 2 or more) phases of data for each cycle of the clock signal, and to test the device under test, the test apparatus comprising: a first time to digital converter configured to receive the clock signal, and to generate clock change point information which represents change timing of the clock signal; a second time to digital converter configured to receive the data sequence in increments of cycles of the clock signal, and to generate data change point information which represents change timing of the data sequence in increments of phases of the data; a calculation unit configured to calculate difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases; and a judgment unit configured to evaluate the device under test based upon the difference data received from the calculation unit.