Patent ID: 8314428

Claim:
A thin film transistor (TFT) comprising: a gate electrode; and a polysilicon substrate comprising: a channel region directly overlapping with the gate electrode in a top view; lightly doped drain (LDD) or offset regions disposed in contact with opposing sides of the channel region; source and drain regions disposed in contact with the LDD or offset regions, such that the LDD or offset regions and the channel region are disposed between the source and drain regions; and primary crystal grain boundaries, wherein, the primary crystal grain boundaries are disposed in the channel region and the source and drain regions, but are not disposed in the LDD or offset regions, the source and drain regions are formed through a single ion implantation process, a thickness of the channel region is substantially identical to a thickness of the source and drain regions, and the channel region and the source and drain regions are disposed directly in the same plane.