Patent ID: 8705860

Claim:
A device comprising: one or more processors; and memory to maintain a plurality of components executable by the one or more processors, the plurality of components comprising: a collection component that receives a plurality of nodes and a plurality of edges that are representative of a large problem, an individual node of the plurality of nodes being interconnected to another node of the plurality of nodes by one or more edges of the plurality of edges, the individual node being in two or more states, a state component that receives estimates of a plurality of states for the individual node and an energy function for the individual node, the energy function for the individual node being determined based in part on the two or more states of the individual node that is connected by one or more edges, a merging component that merges two or more nodes of the plurality of nodes to form at least one merged node based in part on an energy function of at least one edge interconnecting two nodes of the two or more nodes, the at least one merged node being interconnected to another merged node by at least one merged edge to form a smaller problem that is representative of the large problem, the smaller problem including an amount of merged nodes that is smaller than an amount of nodes of the large problem, and a solution component that determines, based in part on merged nodes and merged edges, a solution that minimizes an energy function of the smaller problem, the solution being used to determine a solution that minimizes an energy function of the large problem.