Patent ID: 7335932

Claim:
A semiconductor structure, comprising: a semiconductor substrate; a back gate region on the semiconductor substrate; a back gate dielectric region on the back gate region in a first direction, wherein the first direction is perpendicular to an interfacing surface between the back gate region and the semiconductor substrate; a semiconductor region on the back gate dielectric region in the first direction, wherein the semiconductor region comprises a channel region and first and second source/drain (S/D) regions, wherein the channel region is disposed between the first and second S/D regions, and wherein the semiconductor region is electrically insulated from the back gate region by the back gate dielectric region; a main gate dielectric region on the semiconductor region in the first direction; a main gate region on the main gate dielectric region in the first direction, wherein the semiconductor region is electrically insulated from the main gate region by the main gate dielectric region; a first contact pad adjacent to the first S/D region in a second direction and in direct physical contact with the first S/D region, wherein the second direction is perpendicular to the first direction and pointing from the second S/D region to the first S/D region; a first buried dielectric region directly beneath the first contact pad in the first direction and in direct physical contact with the first contact pad and the back gate region, wherein the first buried dielectric region physically and electrically isolates the first contact pad and the back gate region, wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region, and wherein the first buried dielectric region is in direct physical contact with the first S/D region, the back gate dielectric region, and the back gate region; a second contact pad adjacent to the second S/D region in a third direction and in direct physical contact with the second S/D region, wherein the third direction is perpendicular to the first direction and pointing from the first S/D region to the second S/D region; and a second buried dielectric region directly beneath the second contact pad in the first direction and in direct physical contact with the second contact pad and the back gate region, wherein the second buried dielectric region physically and electrically isolates the second contact pad and the back gate region, and wherein the second buried dielectric region has a third thickness in the first direction at least 1.5 times a fourth thickness of the back gate region.