Patent ID: 7549099

Claim:
A testing apparatus for testing a device under test comprising: a reference clock source for generating a reference clock for controlling operation of the device under test; a clock generating circuit for generating a reproduced clock of which frequency and phase are substantially the same as frequency of the reference clock and phase of output data of the device under test, respectively; a delay circuit for generating a strobe for delaying the reproduced clock; a timing comparator for obtaining an output value of the output data based on the strobe; a logic comparing unit for comparing the output value with a predetermined expectation value; and a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of said logic comparing unit, wherein said clock generating circuit comprises: a first phase comparing unit for comparing phase of the output data of the device under test with that of the reproduced clock and outputting a first comparison result signal; a second phase comparing unit for comparing phase of the reference clock with that of the reproduced clock and outputting a second comparison result signal; an adding unit for adding the first comparison result signal and the second comparison result signal and outputting an addition result signal; and a reproduced clock generating module for generating the reproduced clock based on the addition result signal.