Patent ID: 6871342

Claim:
A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor comprising the steps of: beginning execution of a first sequence of target instructions by committing state of the target processor and storing memory stores generated by previously-executed sequences of instructions at a point in the execution of instructions at which state of the target processor is known, beginning execution of a speculative sequence of host instructions following a branch from the first sequence of target instructions by immediately committing state and storing memory stores, attempting to execute the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding memory stores generated by the speculative sequence of host instructions if execution fails, beginning execution of a next sequence of target instructions if execution succeeds, and releasing a lock for any sequence of host instructions running in a locked condition immediately after committing state of the target processor and storing memory stores generated by previously-executed translation sequences.