Patent ID: 7920113

Claim:
An array panel comprising: a lower substrate; an upper substrate; a first gate line receiving a first gate pulse, the first gate line being arranged on the lower substrate; a second gate line receiving a second gate pulse, the second gate line being arranged on the lower substrate; a data line receiving a data voltage, the data line being arranged on the lower substrate; a liquid crystal capacitor comprising: a pixel electrode; a common electrode: and a liquid crystal layer interposed between the pixel electrode and the common electrode; a sharing capacitor comprising: a first sharing electrode; a second sharing electrode: and a first insulating layer interposed between the first sharing electrode and the second sharing electrode; a first switching element coupled to the first gate line, the data line, and the liquid crystal capacitor to provide the data voltage to the pixel electrode in response to the first gate pulse; and a second switching element coupled to the second gate line, the liquid crystal capacitor and the sharing capacitor to convert the data voltage of the pixel electrode into a compensated data voltage in response to the second gate pulse, wherein the data voltage and the capacitance of the sharing capacitor are determined by the dynamic capacitance of the liquid crystal capacitor.