Patent ID: 6922352

Claim:
A nonvolatile ferroelectric memory device comprising: a plurality of cell array blocks including a plurality of cell arrays having a multi-bitline structure which comprises a plurality of sub bitlines selectively connected to a main bitline and converts a sensing voltage of the sub bitlines to electric current to induce a sensing voltage in the main bitline; a plurality of common data buses for transmitting a sensing voltage of data stored in the cell array blocks, being shared by the plurality of cell array blocks; a sense amplifier array having a plurality of sense amplifiers for comparing the sensing voltage transmitted through the common data buses with a reference voltage; a reference voltage controller for adjusting the reference voltage in response to test mode control signals externally applied thereto; and a column selecting controller for selecting a predetermined number of the cell array blocks in response to the test mode control signals, and outputting sensing voltages of the selected cell array blocks to the common data buses at the same time.