Patent ID: 7190197

Claim:
An integrated circuit comprising: sampling circuitry for sampling input data at an input port of the integrated circuit in response to active edges of a first clock signal; driver circuitry for outputting output data from an output of the integrated circuit in response to active edges of a second clock signal, wherein the second clock signal is independent of the first clock signal in frequency and phase; and clock signal control circuitry comprising: a selector for selecting between a first clock signal and an inverse of the first clock signal; and a phase detector for determining a phase relationship between the first clock signal and the second clock signal, and in response causing the selector to select between the first clock signal and the inverse of the first clock signal to ensure that the active edges of the first clock signal are separated in time from the active edges of the second clock signal such that noise coupling between the driver circuitry and the sampling circuitry is minimized.