Patent ID: 7911228

Claim:
An integrated circuit having a plurality of logic cells, each of said plurality of the logic cells comprising: a first input terminal (wlutin), a second input terminal (tsel), a plurality of third input terminals (ta 0 , ta 1 , ta 2 , ta 3 ), and a first output terminal (wlutout); a lookup table (LUT) ( 202 , 302 ) having a plurality of LUT input terminals, which are respectively connected to said plurality of third input terminals of the logic cell and a LUT output terminal; and a first multiplexer (multiplexer) ( 204 , 304 ) having a first multiplexer input terminal, a second multiplexer input terminal, a select terminal and an multiplexer output terminal; wherein, the first multiplexer input terminal of the first multiplexer is connected to the first input terminal, the second multiplexer input terminal of the first multiplexer is connected to the LUT output terminal, the multiplexer output terminal of the first multiplexer is connected to the first output terminal (wlutout), and the select terminal is connected to the second input terminal and may be used to select which of the signals appearing at first multiplexer input terminal and the second multiplexer input terminal to pass through the first multiplexer; wherein, by coupling in chain the first input terminal (wlutin) of one of the plurality of the logic cells to the first output terminal (wlutout) of another one of the plurality of logic cells, a WLUT chain is formed; wherein each of said plurality of logic cells comprises a second multiplexer ( 206 ) having a first multiplexer input terminal, a second multiplexer input terminal, a multiplexer select terminal and a multiplexer output terminal; within each of the logic cells, the first multiplexer input terminal of the second multiplexer is connected to the multiplexer output terminal of the first multiplexer and the second multiplexer input terminal of the second multiplexer is connected to the output terminal of the LUT, the output terminal of the second multiplexer is coupled to a second output terminal (combout or regout) of the logic cell; wherein the multiplexer select terminal is driven by a configuration memory cell, which may be programmed to let the second multiplexer pass on the signal at its first or second multiplexer input.