Patent ID: 8450169

Claim:
A method of forming a semiconductor structure comprising a first field effect transistor and a second field effect transistor, said method comprising: forming a high dielectric constant material layer comprising a dielectric material having a dielectric constant greater than 8.0 on a semiconductor substrate; forming temporary gate structures and a planarization dielectric layer having a planar dielectric surface on said semiconductor substrate, wherein said temporary gate structures include disposable gate material portions; recessing said disposable gate material portions below said planar dielectric surface to form gate cavities over said semiconductor substrate; simultaneously exposing two different bottom surfaces within said gate cavities, wherein said two different bottom surfaces comprise: a first bottom surface of one of said gate cavities that is a surface of a portion of said high dielectric constant material layer; and a second bottom surface of another of said gate cavities that is a surface of a material different from said dielectric material of said high dielectric constant material layer; forming a contiguous gate dielectric layer on said two different bottom surfaces in said gate cavities and on said planar dielectric surface; and forming first and second gate dielectrics by removing portions of said contiguous gate dielectric layer above said planar dielectric surface, wherein a horizontal portion of said second gate dielectric has a different thickness than a horizontal portion of said first gate dielectric.