Patent ID: 7546500

Claim:
A method for generating test patterns for detecting transition faults in an integrated circuit (IC), comprising: receiving slack time values for nets in the IC, wherein a slack time value for a given net is the minimum amount of delay that the given net can tolerate before violating a timing constraint; for each transition fault to be monitored in the IC, using the slack time values for the nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault; and in response to determining that a test pattern cannot be generated which propagates the transition along the longest path to the transition fault: for each source flip-flop or input to the IC which does not produce a transition for a given test pattern, discarding the slack time values for the outputs of gates coupled to a source flip flop, for each gate coupled to the output of a source flip-flop or an input to the IC, propagating to the output of the gate the slack time values for the input of the gate which has the smallest slack time relative to the other inputs of the gate; and using the newly propagated slack time values to generate the test pattern which produces a transition that propagates along the longest path that can be generated to the transition fault.