Patent ID: 7180128

Claim:
A non-volatile memory, comprising: a substrate; a first row of memory cells comprising a plurality of memory cells, disposed on the substrate, wherein the first row of memory cells comprising: a plurality of stacked gate structures, wherein the stacked gate structures are separated from each other by a gap, and each stacked gate structure comprises, from the substrate surface upward, a select gate dielectric layer, a select gate and a cap layer; a plurality of spacers, disposed on the sidewalk of the stacked gate structures; a plurality of control gates, disposed in the gap between every pair or neighboring stacked gate structures, wherein the control gates are serially connected through a control gate line; a plurality of floating gates, disposed in the gap between every pair of neighboring stacked gate structures and positioned between the control gates and the substrate; an inter-gate dielectric layer, disposed between the control gates and the floating gates; a tunneling dielectric layer, disposed between the floating gates and the substrate; a first source/drain region, disposed in the substrate on one side of the first row of memory cells; a second source/drain region, disposed in the substrate on the other side of the first row of memory cells; and a second row of memory cells comprising a plurality of memory cells having structures identical to those of the first row of memory cells, wherein the first and the second row of memory cells are connected by the second source/drain region, and the selected gates of the first row of memory cells are connected to the selected gates of the second row of memory cells through a plurality of select gate lines and each select gate line is substantially perpendicular to the control gate line.