Patent ID: 8869013

Claim:
A circuit enabling generating a product in a decoder circuit, the circuit comprising: a first memory element coupled to receive a first error value and a first portion of a second error value; a second memory element coupled to receive the first error value and a second portion of the second error value; and an adder circuit coupled to add an output of the first memory element and an output of the second memory element, the adder circuit having a number of inputs equal to the number of memory elements, wherein: the output of the first memory element is generated in response to a first address comprising the bits of the first error value and the bits of the first portion of the second error value, which are combined to create the first address, wherein the output is a product of the first error value and the first portion of the second error value; and the output of the second memory element is generated in response to a second address comprising the bits of the first error value and the bits of the second portion of the second error value, which are combined to create the second address, wherein the output is a product of the first error value and the second portion of the second error value.