Patent ID: 8848480

Claim:
A method, comprising: providing a memory system comprising a first port a second port, a third port, a fourth port, an array of memory cells, a first set of word lines and bit lines coupled to the memory cells, a second set of word lines and bit lines coupled to the memory cells, and a system clock in which each cycle has a first phase and a second phase; applying a first clock, a first row address, and a first column address to the first port; applying a second clock, a second row address, and a second column address to the second port; applying a third clock, a third row address, and third column address, to the third port; applying a fourth clock, a fourth row address, and a fourth column address to the fourth port; and performing accesses to the array through: the first port responsive to the system clock entering the first phase of a first cycle of the system clock and the first clock being active using the first set of word lines and bit lines during the first phase of the first cycle; the second port responsive to the system clock entering the first phase of the first cycle and the second clock being active using the second set of word lines and bit lines if the first row address is different from the second row address during the first phase of the first cycle; the third port responsive to the system clock entering the first phase of the first cycle and the third clock being active using the first set of word lines and bit lines during the second phase of the first cycle; and the fourth port responsive to the system clock entering the first phase of the first cycle and the fourth clock being active using the second set of word lines and bit lines if the third row address is different from the fourth row address during the second phase of the second cycle.