Patent ID: 8362538

Claim:
A memory device comprising a plurality of memory elements, the memory elements each comprising: a first logic element comprising at least one of an inverter and a clocked inverter and a second logic element comprising at least one of an inverter and a clocked inverter, with the first and second logic elements holding data by being electrically connected to each other such that an input terminal of the first logic element is electrically connected to an output terminal of the second logic element and an input terminal of the second logic element is electrically connected to an output terminal of the first logic element; a capacitor; and a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor, wherein one of a source and a drain of the transistor is electrically connected to the input terminal of the first logic element and the output terminal of the second logic element, and the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor to write the data to the capacitor.