Patent ID: 8407653

Claim:
A method of estimating a derating factor for a plurality of potential soft errors in a circuit implementation of a circuit design, the method comprising: storing a representation of the circuit design, the representation specifying a plurality of circuit elements for implementing the circuit design; matching the plurality of circuit elements to a plurality of structural templates by a computing arrangement, each structural template being representative of one or more of the plurality of circuit elements and having associated information descriptive of one or more toggle rates; determining, by the computing arrangement, a plurality of respective estimated toggle rates for the plurality of circuit elements of the circuit design based on the information descriptive of one or more toggle rates associated with the matched structural templates; determining, by the computing arrangement, a derating factor of the circuit design as a function of the estimated toggle rates of the plurality of circuit elements, wherein the derating factor is an estimation of a fraction of the plurality of potential soft errors that would cause functional failure of the circuit design; and outputting data indicative of the derating factor.