Patent ID: 7447059

Claim:
A semiconductor integrated circuit having an internal SRAM that includes at least one row in which a plurality of memory cells are arrayed, the semiconductor integrated circuit comprising: a first bit line and a second bit line that are connected to first ports of the memory cells; a third bit line and a fourth bit line that are connected to second ports of the memory cells; a first transistor and a second transistor respectively composing first ports of adjacent first and second memory cells and having a shared impurity diffusion region connected to the first bit line via a first interconnection; a third transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the third bit line via a second interconnection; a fourth transistor and a fifth transistor respectively composing the first ports of the first and second memory cells and having a shared impurity diffusion region connected to the second bit line via a third interconnection; a sixth transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the fourth bit line via a fourth interconnection; a first write/read circuit that writes data to and reads data from the memory cells via the first port; and a second write/read circuit that writes data to and reads data from the memory cells via the second, wherein the lengths of the second and fourth interconnections are shorter than the lengths of the first and third interconnections, wherein the first, second, third, and fourth interconnections include a first conductive layer, a first wiring layer, a second conductive layer, and a second wiring layer, and wherein the second and fourth interconnections include a third conductive layer.