Patent ID: 8335967

Claim:
A memory system comprising: a Flash-EEPROM memory in which a plurality of memory cells capable of electrically erasing and writing data are arranged; a control circuit that controls a cache memory and the Flash-EEPROM memory; an interface circuit that communicates with outside; and a memory area of the Flash-EEPROM memory that is arranged in the Flash-EEPROM memory and stores a plurality of group data and a plurality of flag data for storing presence of inversion of all bits of respective group data, wherein in the group data, “1” logic data or “0” logic data in a direction in which a failure hardly occurs in data retention is written with respect to an ECC-corrected bit in original write data, and “1” logic data or “0” logic data in a direction in which a failure easily occurs in data retention is written with respect to other bits not ECC-corrected, with respect to a block, which is registered as an empty block, of the memory areas of the Flash-EEPROM memory.