Patent ID: 7118961

Claim:
A stitched MONOS memory array comprising: three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers; and stitches periodically contacting each of said resistive layers to a respective upper conductive layer wherein said stitches comprise: connections from said middle resistive layer to a bottom conductive layer overlying said top resistive layer; contact/via stacks from said bottom resistive layer to a top conductive layer; a middle conductive layer connecting cut ends of said middle resistive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer and wherein said middle conductive layer loops around said contact/via stacks; and connections from said top resistive layer to said middle conductive layer.