Patent ID: 7915083

Claim:
A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body has a main part and a plurality of terminals, the main part having a top surface and a bottom surface and including a plurality of layer portions stacked, the plurality of terminals being arranged on at least one of the top and bottom surfaces of the main part and electrically connected to the wiring; each of the plurality of layer portions includes a semiconductor chip; at least one of the plurality of layer portions further includes a plurality of electrodes that are electrically connected to the semiconductor chip and that each have an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is electrically connected to the end faces of the plurality of electrodes, the method comprising the steps of: fabricating a plurality of substructures each of which includes a plurality of preliminary layer portions arrayed, each of the preliminary layer portions being intended to be made into any one of the layer portions included in the main part, the substructures being intended to be cut later at a position of a boundary between every adjacent preliminary layer portions; fabricating a plurality of first layered substructures by using the plurality of substructures, each of the first layered substructures including a plurality of substructures stacked; and producing the plurality of layered chip packages by using the plurality of first layered substructures, wherein: each of the first layered substructures includes a plurality of pre-separation main bodies that are arrayed and intended to be separated from each other later into the individual main bodies; and the step of producing the plurality of layered chip packages includes the steps of: fabricating a second layered substructure by stacking the plurality of first layered substructures and bonding every two adjacent first layered substructures to each other; cutting the second layered substructure into at least one block in which a plurality of pre-separation main bodies are arrayed both in a direction of stacking of the first layered substructures and in a direction orthogonal thereto; forming the wiring simultaneously for the plurality of pre-separation main bodies included in the at least one block; and separating the plurality of pre-separation main bodies each provided with the wiring from each other so as to form the plurality of layered chip packages.