Patent ID: 7984405

Claim:
A method for determining post-physical-optimization timing of an integrated circuit (IC) design, comprising: receiving a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design; estimating capacitances for cells within the IC design based on analytic models of the cells; and for a net which is less than or equal to a specified length, in response to determining that an output load for a driving cell is greater than a specified capacitance, determining a buffered net by inserting a specified number of stages of buffers between the driving cell and the output load, wherein the drive strength of the buffers in a given stage is a specified factor more than the drive strength of the buffers in the previous stage, calculating, by using one or more computers, the post-physical optimization timing of the buffered net by multiplying the specified number of stages by the delay of the first stage of buffers, and in response to determining that the output load for the driving cell is less than the specified capacitance, determining the delay based on a load-delay model.