Patent ID: 8791728

Claim:
A dynamic latch comprising: a pair of parallel gates comprising a first parallel gate receiving a true clock signal and a seed signal, and a second parallel gate receiving said true clock signal and a data signal, said data signal comprising a received data signal output by a previous latch element; a logic circuit operatively connected to said parallel gates, said logic circuit performing logic operations using signals output by said parallel gates to produce an updated data signal; an additional gate operatively connected to said logic circuit, said additional gate controlling passage of said updated data signal, and said additional gate receiving a complement clock signal having an opposite polarity relative to said true clock signal, said true clock signal opening said first parallel gate and said second parallel gate when said complement clock signal closes said additional gate, and said true clock signal closing said first parallel gate and said second parallel gate when said complement clock signal opens said additional gate; an inverter operatively connected to said additional gate, said inverter receiving said updated data signal from said additional gate, and inverting and outputting said updated data signal as an output data signal; and two inputs, one of said inputs being connected to said first parallel gate and another of said inputs being connected to said second parallel gate.