Patent ID: 7038519

Claim:
A digital clock manager (DCM) comprising: a delay line including a plurality of series-connected symmetrical cascade voltage switch logic (CVSL) buffers coupled to receive an input differential clock signal, and in response, provide a plurality of delayed differential clock signals; and a CVSL multiplexer coupled to receive the delayed differential clock signals from output terminals of the series-connected CVSL buffers; wherein the CVSL multiplexer comprises: a first p-channel transistor having a source coupled to a first voltage supply terminal and a drain coupled to a first differential output terminal; a second p-channel transistor having a source coupled to the first voltage supply terminal and a drain coupled to a second differential output terminal; wherein a gate of the first p-channel transistor is coupled to the second output terminal; wherein a gate of the second p-channel transistor is coupled to the first output terminal; a first n-channel transistor having a drain coupled to the first differential output terminal and a gate coupled to receive a control signal; a second n-channel transistor having a drain coupled to the second differential output terminal and a gate coupled to receive the control signal; a third n-channel transistor having a source coupled to a second voltage supply terminal and a drain coupled to a source of the first n-channel transistor; and a fourth n-channel transistor having a source coupled to the second voltage supply terminal and a drain coupled to a source of the second n-channel transistor, wherein differential output terminals of one of the CVSL buffers are coupled to gates of the third and fourth n-channel transistors.