Patent ID: 7996618

Claim:
Apparatus comprising: a computer system central processor; and layered memory operatively coupled to said central processor and accessible thereby, said layered memory having a level one cache; said central processor and said layered memory cooperating to: store standard cache lines in the level one cache; following an initial delay, selectively store in interchangeable locations of the level one cache of the layered memory both standard cache lines and trace lines; partition an instruction(s) address presented to the level one cache; index the instruction(s) address into a tag array of the level one cache; compare the instruction(s) address with the tag array a first time to determine whether a match is found; if a match is found on the first comparison, then determine whether the match is a trace line; if the match is a trace line, check the trace length parameter, access the required partitions, and forward the instruction(s) for execution by the central processor; if the match is a conventional cache line, then check the target address, access the required partitions, force the leading instruction(s) to NOP, and forward the instruction(s) to execution by the central processor, then; build a new trace line, select a cache line to be replaced and replace the selected cache line with the new trace line; if no match is found on the first comparison, then mask the least significant bits of the instruction(s) address; and compare the masked instruction(s) address with the tag array a second time to determine whether a match is found; if a match is found on the second comparison; then if the match is trace line, declare a miss in the level one cache and fetch instruction(s) from a further level cache, forward the instruction(s) for execution by the central processor, build a new trace line, select a cache line to be replaced and replace the selected cache line; if the match is not a trace line, check the trace address, access the required partitions, force the leading instruction(s) to NOP, and forward the instruction(s) for execution by the central processor; then build a new trace line, select a cache line to be replaced and replace the selected cache line with the new trace line.