Patent ID: 7904640

Claim:
A memory system comprising: a first storing area as a cache memory included in a volatile semiconductor memory; second and third storing areas included in nonvolatile semiconductor memories in which data reading and writing is performed by a page unit and data erasing is performed by a block unit twice or larger natural number times as large as the page unit; a first input buffer included in the nonvolatile semiconductor memories and configured to perform buffering between the first storing area and the second storing area; a second input buffer included in the nonvolatile semiconductor memories and configured to perform buffering between the first storing area and the third storing area; and a controller that allocates storage areas of the nonvolatile semiconductor memories to the second and third storing areas and the first and second input buffers by a logical block unit associated with one or more blocks, wherein the controller executes: first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data written in the first storing area to the first input buffer as data in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data written in the first storing area to the second input buffer as data in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating, to the second storing area, a logical block that is allocated to the first input buffer and in which the data in the first management unit is stored; fifth processing for relocating, to the third storing area, a logical block that is allocated to the second input buffer and in which the data in the second management unit is stored; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer as data in the second management unit.