Patent ID: 8219965

Claim:
A layout design method of a semiconductor integrated circuit, said method comprising: providing a cell layout including a cell that comprises: a gate or a plurality of gates extending in a first direction; a plurality of diffusion layers; a first boundary of said cell in parallel with the gate or the plurality of gates; a second boundary of said cell being in an opposite side of the first boundary of the cell; a first distance between the first boundary and a closest diffusion layer of the plurality of diffusion layers from the first boundary; a second distance between the second boundary and a closest diffusion layer of the plurality of diffusion layers from the second boundary; a third distance between the first boundary and a closest gate of the gate or the plurality of gates from the first boundary; and a fourth distance between the second boundary and a closest gate of the gate or the plurality of gates from the second boundary; regenerating the cell layout to set the first distance and the second distance to a first value, or to set the third distance and the fourth distance to a second value, as executed by a processing unit of a computer; and generating a library data of said cell for a placement and routing tool, based on said cell layout.