Patent ID: 7861202

Claim:
A cell arrangement method, comprising the steps of: (a) inputting logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit of the semiconductor integrated circuit existing between flip-flops are defined; (b) analyzing, by using a design device including a CPU, the logic circuit information to detect a logic circuit sandwiched by two flip-flops; (c) counting the number of logic stages of the logic circuit detected at step (b); (d) determining, according to the number of logic stages counted at step (c), to which substrate potential a cell used for the logic circuit is to be connected; and, after steps (b) to (d) are performed on all of logic circuits sandwiched by two flip-flops in the logic circuit information, step (e) of performing an arrangement/wiring process based on the substrate potential determined at step (d) to generate layout data.