Patent ID: 8344756

Claim:
An integrated circuit for a field programmable gate array, comprising: a substrate including active circuitry fabricated in a logic plane and an inter-layer interconnect structure; and a plurality of vertically stacked memory planes in contact with one another and with the substrate and vertically positioned over the substrate, each memory plane including a plurality of re-writeable non-volatile two-terminal memory elements configured in at least one two-terminal cross-point array, each memory element configured to store more than one bit of non-volatile data, the inter-layer interconnect structure operative to electrically couple the active circuitry with the plurality of memory elements, and wherein the active circuitry includes sequencer logic operative to provide sequential memory addresses and write data for data operations on the plurality of memory elements, interface logic operative to receive the write data, memory logic operative to access the plurality of memory elements for the data operations, and configurable logic electrically coupled with at least a portion of the plurality of memory elements and operative to form a plurality of programmable cells configured to implement a programmed logic function.