Patent ID: 7745932

Claim:
A semiconductor package comprising: a conductive base having first and second major surfaces; a first group of semiconductor chips stacked and mounted on the first major surface of the conductive base, the width of the semiconductor chips of the first group taken along a first direction parallel to the first major surface being less than a width of the first major surface taken along the first direction, each of the first group of semiconductor chips having same functional pads, the first group of semiconductor chips comprising at least four semiconductor chips; a second group of semiconductor chips stacked and mounted on the second major surface of the conductive base, the width of the semiconductor chips of the second group taken along the first direction parallel to the second major surface being less than a width of the second major surface taken along the first direction, each of the second group of semiconductor chips having same functional pads, the second group of semiconductor chips comprising at least four semiconductor chips; a first group of pins adjacent to one side of the conductive base and having no direct electrical connection with the conductive base; a second group of pins adjacent to an opposite side of the one side of the conductive base and having no direct electrical connection with the conductive base, the first group of pins being line symmetric with the second group of pins with respect to a line having a second direction which is perpendicular to the first direction, and each pin of the first group of pins being line symmetric with a corresponding pin of the second group of pins having a same function with the corresponding pin of the second group of pins; a first group of wires connected between the first of chip pads and the first group of pins, chip pads of the first group having a same function and same relative location being connected to a same pin of the first group; a second group of wires connected between the second group of chip pads and the second group of pins, chip pads of the second group having a same function and same relative location being connected to a same pin of the second group; and an encapsulant encapsulating the conductive base and the semiconductor chips