Patent ID: 6999348

Claim:
A nonvolatile semiconductor storage unit comprising: a plurality of word lines; a plurality of memory cells connected to a bit line, each memory cell being connected to a corresponding one of said word lines and having a control gate and a floating gate; a sense latch circuit having a first node and a second node, wherein said first node is connected to one end of said bit line, said sense latch circuit detecting data on said bit line corresponding to a threshold voltage of a selected memory cell; a MOSFET connected between said bit line and said sense latch circuit said MOSFET having a gate coupled to receive said data on said bit line, and said MOSFET driving said second node of said sense latch circuit; a bit line precharge circuit which is connected to said bit line and which precharges said bit line; and a power supply circuit which is connected to said bit line precharge circuit and which generates precharge voltage for said bit line according to a threshold voltage of said MOSFET.