Patent ID: 8861273

Claim:
An integrated circuit device, comprising: a memory array comprising plural bit lines coupled with corresponding columns of memory cells in the array, plural reference lines, a plurality of access gate word lines coupled to access gates in corresponding rows in the array and a plurality of memory gate word lines coupled to memory gates in corresponding rows in the array, wherein the memory cells include respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines, the respective access transistors coupled either (i) in series between the memory transistors and the corresponding bit lines or (ii) in series between the memory transistors and one of the plural reference lines, and not (iii) in series between the memory transistors and the corresponding bit lines and between the memory transistors and one of the plural reference lines, wherein the respective access transistor does not store charge , and the respective access transistor is adjacent to a doped region of at least one of the corresponding bit lines and one of the plural reference lines; control circuitry including logic for reading, programming and erasing data stored in the memory cells in the array; wherein at least one of the memory transistors comprises a semiconductor body including a channel having a channel surface and a dielectric stack between the memory gate and the channel surface; the dielectric stack comprising a tunneling dielectric layer contacting one of the gate and the channel surface including a combination of materials arranged to establish a relatively low valence band energy level near said one of the gate and the channel surface, and an increase in valence band energy level at a first distance from said one of the gate and the channel surface and a decrease in valence band energy at a second distance more than 2 nm from said one of the gate and the channel surface; a charge trapping dielectric layer between the tunneling dielectric layer and another of the gate and the channel surface having a thickness greater than 5 nm; a multilayer blocking dielectric between the charge trapping dielectric layer and said another of the gate and the channel surface including an oxide layer with a first dielectric constant and a dielectric layer with a second dielectric constant exceeding the first dielectric constant.