Patent ID: 7434152

Claim:
A data compression circuit in a memory device, comprising: a plurality of first level data compression circuits for receiving data signals corresponding to bit locations of each word of a group of words of the memory device and for providing a first match signal and a second match signal, the first match signal having a first logic level and the second match signal having a second logic level if a corresponding bit location for each word of the group has a first data value, the first match signal having the second logic level and the second match signal having the first logic level if the corresponding bit location for each word of the group has a second data value, and the first and second match signals otherwise having the same logic level; and a second level data compression for receiving the first and second match signals from each of the first level data compression circuits and for providing a third match signal having a first logic level if all of the first match signals have the same logic level and all of the second match signals have the same logic level, and otherwise having a second logic level.