Patent ID: 7863974

Claim:
An apparatus for demodulating a signal, comprising: a front end module configured to receive an input signal and to provide a mixed signal by mixing the input signal with an oscillating signal; a filter configured to receive the mixed signal and to provide a filtered signal by filtering the mixed signal, wherein at least one characteristic of the filter is selectable based on a filter control signal; and a phase lock loop (PLL) configured to receive the filtered signal and to demodulate an output signal from the filtered signal, wherein the PLL includes a phase frequency detector configured to provide a phase error signal based on a difference between a PLL input signal and a clock feedback signal, wherein the PLL input signal is based on the filtered signal; a clock generator configured to generate a generated clock signal based on the phase error signal; a divider configured to provide a divided clock signal by dividing a frequency of the generated clock signal; a multiplexer configured to provide the clock feedback signal by selecting one of the divided clock signal or another clock signal based on a PLL control signal, wherein the another clock signal is either the generated clock signal or is based on the generated clock signal; another divider configured to provide another divided clock signal by dividing the frequency of the generated clock signal, wherein the multiplexer is configured to provide the clock feedback signal by selecting one of the divided clock signal or the another divided clock signal based on the PLL control signal; a compressor configured to provide a scaled signal based on scaling the PLL input signal by a scaling factor; and an output circuit coupled between a first node and a second node and configured to receive the scaled signal at the first node and to provide the output signal from a third node, wherein the output circuit includes: a first capacitor coupled between the first node and the second node; a first resistor coupled between the first node and a fourth node; a second capacitor coupled between the fourth node and the second node; a second resistor coupled between the first node and the third node; and a third capacitor coupled between the third node and the second node.