Patent ID: 8320156

Claim:
A semiconductor memory device comprising: a plurality of first wirings arranged in parallel; a plurality of second wirings arranged so as to cross the first wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable resistance element in series; a first selection portion selecting the first wiring; a second selection portion selecting the second wiring; and a power source portion applying predetermined selected-wiring-voltages to a selected first wiring being selected by the first selection portion and a selected second wiring being selected by the second selection portion, respectively, and applying predetermined unselected-wiring-voltages to unselected first wirings other than the selected first wiring and unselected second wirings other than the selected second wiring, respectively, a resistance element having a predetermined resistance value being provided between the power source portion and the unselected first and second wirings, wherein the resistance element includes a plurality of first resistance elements and a plurality of second resistance elements, the first resistance elements are provided on the unselected first wirings and the unselected second wirings, respectively, the variable resistance element is brought into either of a high-resistance state and a low-resistance state, and the resistance value of the first resistance element is substantially the same as that of the variable resistance element in the high-resistance state.