Patent ID: 8049543

Claim:
A delay locked loop comprising: a delay line comprising a plurality of delay blocks each configured to operate as a ring oscillator, which delays a reference clock signal by a predetermined phase, in response to a mode control signal and an initial delay value and to operate as a phase delay line, which controls a phase of the reference clock signal or a phase of a signal output from a previous delay block among the plurality of delay blocks, in response to the mode control signal; an edge combiner configured to generate an output clock signal having a constant duty cycle and a higher frequency than the reference clock signal in response to output signals of the delay blocks; a fine tuning block configured to control the delay blocks based on a phase difference between the reference clock signal and the output clock signal to control a locking operation on the output clock signal; and a mode control block configured to generate the mode control signal and the initial delay value based on the reference clock signal and whether each of the delay blocks has delayed the reference clock signal by the predetermined phase.