Patent ID: 8917131

Claim:
An apparatus comprising: a plurality of pull-up transistors coupled between a first node and a second node; a plurality of pull-up circuits to receive a data signal, each pull-up circuit including at least a transistor configured to provide the data signal to a latch responsive to a respective timing signal and wherein each pull-up circuit is further configured to provide a respective control signal from the latch to a gate of a respective one of the pull-up transistors responsive to the data signal and the respective timing signal, wherein the respective pull-up transistor is to switch responsive to the respective control signal; and a plurality of timing circuits coupled to the plurality of pull-up circuits, each timing circuit configured to provide a respective one of the timing signals to a respective one of the pull-up circuits, and wherein the timing circuits are to provide the timing signals such that the control signals switch the pull-up transistors at different times to modulate a slew rate of a signal on the second node, and each of the plurality of timing circuits comprise: a plurality of adjustable delays coupled to a pulse generator, wherein the combination of the plurality of adjustable delays and the pulse generator are configured to receive a clock signal and provide a respective one of the timing signals which are delayed based on a respective adjustable delay.