Patent ID: 8466508

Claim:
A non-volatile memory structure, comprising: a substrate; a plurality of stacked patterns disposed on the substrate, each of the stacked patterns comprising a charge storage structure and a gate from bottom to top, wherein the charge storage structure at least comprises a charge storage layer, the stacked patterns are physically separated from each other, and an opening being located between every two adjacent stacked patterns in the first direction; a plurality of stress patterns disposed on the substrate between two adjacent stacked patterns, respectively, in parallel and extending along the first direction, wherein the stress patterns are separated from each other in a second direction, the first direction intersecting the second direction and a height of the stress patterns is higher than a height of the charge storage layer and lower than a height of the plurality of stacked patterns; a plurality of doped regions respectively disposed in the substrate below the stress patterns; a plurality of word lines disposed above the stress patterns and the stacked patterns in parallel and extending along the second direction, wherein the stress patterns located above the doped regions are located below the word lines; and a dielectric layer disposed directly above the word lines and between adjacent word lines and completely filling the openings, a material of the dielectric layer being a stress material.