Patent ID: 6954098

Claim:
A power-rail ESD clamp circuit for mixed-voltage I/O buffer comprising: an ESD detection circuit, further comprising: a first resistor, having a first end and a second, the first end thereof being connected to a first node coupled to a first voltage; a capacitor, having a first end and a second end, the first end thereof being connected to a second node coupled to the second end of the first resistor; a second resistor having a first end and a second end, the first end thereof being connected to a second voltage; a first PMOS transistor, having a gate, a drain and a source, the gate thereof being connected to both a third node and the second resistor, the drain thereof being connected to a fourth node coupled to a grounded point, the source thereof being connected to the second end of the capacitor; a second PMOS transistor, having a gate, a drain and a source, the gate thereof being connected to the second node, the source thereof being connected to the first node; a third PMOS transistor, having a gate, a drain and a source, the gate thereof being connected to the third node, the source thereof being connected to the drain of the second PMOS transistor; and a first NMOS transistor, having a gate, a drain and a source, the gate thereof being connected to the third node, the drain being connected to a fifth node coupled to the drain of the third PMOS transistor; an ESD protection device, further comprising: a first end, being connected to the first node; a second end, being connected to the fourth node; and a trigger end, being connected to the fifth end.