Patent ID: 7818692

Claim:
A method of improving a design for a very large scale integrated circuit, the design representing a plurality of semiconductor devices interconnected in a circuit, the method comprising: using a computer to perform: a) determining whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range such that a performance goal and a matching goal for the circuit are served, and if so, b) moving the edge of the feature in the first direction by the distance, the distance being calculated to best serve the performance goal and the matching goal; c) repeating steps (a) and (b) for each of the plurality of semiconductor devices; and d) repeating steps (a), (b) and (c), if necessary, until the performance goal and matching goal for the circuit are deemed to be adequately served, wherein each of the semiconductor devices includes a transistor having a channel whose length extends in a longitudinal direction and whose width extends in a transverse direction, and the feature includes a stressed liner, the edge including a first edge of the stressed liner extending in the transverse direction and a second edge of the stressed liner extending in the longitudinal direction, wherein step (b) includes moving the first edge in the longitudinal direction and moving the second edge in the transverse direction.