Patent ID: 7904731

Claim:
An integrated circuit device comprising: a challengeable device-specific response generation circuit including circuitry for accepting a multiple-bit challenge value; circuitry for implementing a plurality of bistable logic modules, wherein each bistable logic module has an input for accepting an excitation signal and an output with two stable logic output states; each bistable logic module is configured to receive an excitation signal and after a time period from receiving the excitation signal reach a stable output in one of the two stable logic output states, and each bistable logic module is fabricated such that fabrication variation from device to devices fabricated according to the module design provides a device-specific likelihood of reaching each stable logic output state; circuitry for providing a response value based on the challenge value and outputs of multiple of the bistable logic modules; and circuitry coupled to the response generation circuitry for using stored redundant bits to correct the response value to a previously generated responses and using the corrected responses as a cryptographic key.