Patent ID: 8101469

Claim:
A method of forming a Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of: providing a semiconductor substrate; applying at least one first insulating layer that is temperature independent to the semiconductor substrate with at least a portion of the first insulating layer being a sacrificial layer; applying at least one structural layer that is temperature independent to the first insulating layer with at least a portion of the structural layer being made conductive; patterning the structural layer and the insulating layer; applying at least one protective layer overlying both the patterned first insulating and structural layer; etching the first insulating and structural layer; forming at least one opening in the semiconductor substrate and the protective layer; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a front face and a back face; applying at least one planarization layer overlying the substrate and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and a portion of a mechanical layer that is conductive on the substrate; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step with at least a portion of the first insulating layer that is the sacrificial layer.