Patent ID: 7956787

Claim:
A successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a capacitor array including a plurality of switched capacitors therein with varying weights each having a common plate connected to a common node and a switched plate; at least one comparator for comparing the voltage on the common node of the capacitor array with a reference voltage; a SAR controller for sampling an input voltage on said capacitor array in a sampling phase, and redistributing the charge stored thereon in a conversion phase by selectively changing the voltage on select ones of the capacitor array in accordance with a SAR conversion algorithm; an accumulator for accumulating a plurality of digital samples of the input voltage; at least one control register for configuring operation of the SAR ADC in at least one of a first mode and a second mode of operation, wherein the first mode of operation configures the SAR ADC to operate as an N-bit SAR ADC and the second mode of operation configures the SAR ADC to operate as a greater than N-bit SAR ADC; and wherein the SAR ADC uses dynamic offset adjustment to remove voltage offsets in increments between available LSB resolutions in the second mode of operation.