Patent ID: 7817653

Claim:
A circuit, comprising: a first selection module having a first data input, a second data input, a first validation input, a second validation input, a selected data output, a marker output, and a presence output, wherein a first validation signal received at the first validation input identifies whether or not a first data signal received at the first data input is valid, wherein a second validation signal received at the second validation input identifies whether or not a second data signal received at the second data input is valid, wherein a presence signal outputted at the presence output identifies whether or not at least one data signal is valid, wherein the first data input has an assigned selection priority higher than that assigned to the second data input, wherein if at least one data signal is identified as valid, the valid data signal having the higher assigned priority is transferred to the selected data output, and wherein a marker signal at the marker output identifies from which data input the transferred data signal is transferred.