Patent ID: 7746850

Claim:
An interface card built in a single unit of a computer telephony integration (CTI) system, the interface card being connected to a voice processing unit (VPU) of the single unit via a local CT-BUS; wherein 8 Mbps signals from the VPU in the CTI single unit are multiplexed into a single 128 Mbps signal, and converted into a low voltage differential signaling (LVDS) signal on a transmitting side of the interface card; wherein an external 128 Mbps LVDS signal is converted into transistor-transistor logic (TTL) signals and demultiplexed into 8 Mbps local CT-BUS compatible signals and sent to the VPU in the single unit on a receiving side of the interface card; wherein a latch and buffer unit of the interface card is defined as output from its hosting computer, the latch and buffer unit receiving serial code stream from the VPU of its hosting computer, and performing parallel/serial conversion and latch of the serial code stream; wherein a master RAM of the interface card comprises two ports, one port of the master RAM being connected behind the latch and buffer unit, frame tag bytes for alignment being written into a specific storage location of the master RAM, the code stream being read by a 128 Mbps clock synchronized to a local BUS clock at the other port of the master RAM, sent to an LVDS drive connected to the master RAM after parallel/serial conversion and output as an LVDS signal; wherein the interface card further comprises an LVDS receiver, a secondary RAM, and a frequency divider, the LVDS receiver receiving 128 Mbps LVDS level code stream and is connected with a parallel/serial conversion and locking unit to convert the 128 Mbps LVDS level code stream into 8 Mbps TTL level signals, the secondary RAM comprising two ports, one port of the secondary RAM being connected to the parallel/serial conversion and locking unit, the secondary RAM identifying start of frame based on identifying logic of built-in frame synchronization byte signals and writing the 8 Mbps TTL level signal sequence into the secondary RAM, the code stream being read with the 8 Mbps clock sequence from a local BUS at the other port of the secondary RAM and sent to the local BUS, the frequency divider dividing frequencies of received clock signals to generate 8 Mbps reference clock signals, and the 8 Mbps reference clock signals being also input to the local BUS.