Patent ID: 8446771

Claim:
A NAND nonvolatile semiconductor memory device comprising: a plurality of memory cell transistors arranged in a matrix in a column direction and a row direction and each comprising a charge accumulation layer and a control gate electrode configured to control a charge accumulation state of the charge accumulation layer; and a write circuit configured to carry out write on the plurality of memory cell transistors, wherein the memory cell transistors arranged in the same column include first memory cell transistors, and second memory cell transistors each of which is smaller in size than the first memory cell transistor in the column direction, the write circuit carries out write on a predetermined first memory cell transistor and then on another first memory cell transistor, and after the write on the another first memory cell transistor, carries out write on the second memory cell transistor, wherein the memory cell transistors arranged in the same row include the first memory cell transistors, and third memory cell transistors each of which is smaller in size than the first memory cell transistor in the row direction, and the memory cell transistors arranged in a column different from the one in which the first and second memory cell transistors are arranged include the third memory cell transistors and fourth memory cell transistors each of which is smaller in size than the third memory cell transistor in the column direction, and the write circuit carries out write on the third first memory cell transistor after the write on the predetermined memory cell transistor, and after the write on the third memory cell transistor and the second memory cell transistor, carries out write on the fourth memory cell transistor.