Patent ID: 8493776

Claim:
A self-referenced read circuit for determining an initially unknown value stored in an MRAM bit cell, the bit cell having a magnetic tunnel junction element with a pinned layer establishing a permanent magnetic field reference direction, and a free layer with a changeable magnetic field component that is selectively alignable parallel to the reference direction in a low resistance state of the magnetic tunnel junction element, and anti-parallel to the reference direction in a high resistance state of said element, the self-referenced reading circuit comprising: a current bias source and a switching circuit coupled to apply a read current bias to the magnetic tunnel junction element, thereby establishing current amplitude and potential difference conditions representing the unknown resistance state; a storage element responsive to the read circuit, operable for storing a value representing the unknown resistance state; a write circuit operable to impose one of the resistance states on the magnetic tunnel junction element after operation of the storage circuit to store said value; wherein the switching circuit sequentially couples the magnetic tunnel junction element to the current bias source to establish the conditions representing the unknown resistance state, and then to establish current amplitude and potential difference conditions representing the imposed one of the resistance states; a current summing node operable to produce a sum of a current level increased with resistance in one of the unknown state and the imposed state, with a current level decreased with resistance in the other of the unknown state and the imposed state; and, an output circuit responsive to the sum, identifying whether the unknown state and the imposed state were the same or different.