Patent ID: 7907450

Claim:
A method for operating an array of charge storage memory cells arranged in a NAND configuration including a plurality of NAND cells on semiconductor lines and a plurality of word lines coupled in parallel to the NAND cells, the plurality of semiconductor lines on an insulating layer and isolated from adjacent semiconductor lines of the NAND cells by isolation structures on the insulating layer, memory cells in the array including charge trapping structures overlying channel regions separated by source and drain regions in a corresponding semiconductor line, the method comprising: changing a data value stored in a target memory cell in a first NAND cell in the array, said changing comprising: applying a first bit line voltage to the semiconductor line of the first NAND cell; applying a first word line voltage to a corresponding word line of the target memory cell, the first word line voltage and the first bit line voltage differing by an amount sufficient to change the data value stored in the target memory cell; and applying a second word line voltage to corresponding word lines of the remaining memory cells in the first NAND cell, thereby coupling the first bit line voltage to the channel region of the target memory cell, the first bit line voltage and the second word line voltage differing by an amount sufficient to maintain respective data values stored in the remaining memory cells of the first NAND cell.