Patent ID: 8724271

Claim:
A circuit comprising: a first NMOS transistor having a first source, a first drain, and a first gate, the first source being coupled to a ground rail and the first drain being coupled to an I/O pad; and a gate driver control circuit coupled to the first drain and the first gate, wherein the gate driver control circuit provides a ground potential to turn off the first gate during an ESD event occurring from the I/O pad to the ground rail; and wherein the gate driver control circuit comprises: a second NMOS transistor having a second source, a second drain, and a second gate; and a first PMOS transistor having a third source, a third drain, and a third gate, wherein the third source is coupled to the first drain, the second drain is coupled to the first gate, the second source is coupled to the ground rail, and the second gate is coupled to the third drain.