Patent ID: 7940814

Claim:
A serial data receiver comprising: a plurality of first channels each having a 6 Gbps serial bit rate operating range, wherein each of the first channels is configured to receive a serial data signal having a serial bit rate up to the 6 Gbps serial bit rate operating range; a second channel having a 10 Gbps serial bit rate operating range, wherein the second channel is configured to receive a serial data signal having the 10 Gbps serial bit rate that exceeds the 6 Gbps serial bit rate operating range of each of the first channels; clock signal distribution circuitry comprising: a set of first conductors that distribute first, second and third clock signals to the plurality of first channels; and circuitry for allowing each of the plurality of first channels to select either the first, the second or the third clock signal for use by that channel; and a second conductor different from the set of first conductors that distributes the third clock signal to the second channel.