Patent ID: 7417477

Claim:
A PLL circuit which generates and outputs an output clock of a frequency N times (where N is a positive integer including 1) higher than that of a first clock, based on the first clock originating from an input clock, the PLL circuit comprising: an oscillator which generates a second clock of a frequency N×Y times (where Y is a positive integer not less than 2) higher than that of the first clock, upon receipt of a control input; an output-side frequency divider which generates the output clock by dividing the frequency of the second clock outputted from the oscillator by Y; a start/stop detection circuit which detects a stop and a resumption of the input clock; a frequency divider having a reset function, to which the second clock outputted from the oscillator and a detection result of the stop and the resumption of the input clock detected by the start/stop detection circuit are inputted, and which generates a third clock upon receipt of a detection result of the resumption after the input clock stops once, the third clock being a frequency obtained by dividing the frequency of the second clock by (N×Y), and being adjusted in phase; a phase comparator, to which the first clock and the third clock generated by the frequency divider are inputted, and which compares a phase of the first clock with a phase of the third clock; and a control input generator which generates and inputs a control input to the oscillator, upon receipt of a result of phase comparison by the phase comparator.