Patent ID: 7975076

Claim:
A data processing system comprising: a plurality of central processing units; a memory unit coupled to said plurality of central processing units; a plurality of I/O devices; a hypervisor that operates on said plurality of central processing units to control each of a plurality of logical partitions to which at least one of said plurality of central processing units and at least one of said plurality of I/O devices are allocated respectively such that a respective operating system can be executed individually on each of said logical partitions; and an I/O control unit that is coupled to said plurality of central processing units and said memory unit, and to which said plurality of I/O devices are coupled, and wherein said I/O control unit is connected with said plurality of I/O devices via a plurality of I/O slots, and said I/O control unit resets each of the I/O devices individually by asserting a reset signal prepared corresponding to the I/O slot that connects the I/O device with the I/O control unit.