Patent ID: 8618579

Claim:
A semiconductor integrated circuit device comprising: an element isolation region; and a first active region defined by the element isolation region in a semiconductor substrate, wherein the first active region is formed in the semiconductor substrate and includes a first well of a first conductivity type; wherein the first active region further includes a first region which extends in a first direction and in which a plurality of MISFETs is formed, and a second region which extends in the first direction and which feeds power to the plurality of MISFETs; wherein the first region and the second region are separated by an element isolation in planar view, and are connected with each other by the first well; wherein each gate electrode of each of the plurality of MISFETs is formed over at least the first region and extends in a second direction intersecting the first direction; wherein a plurality of first plugs are formed over each of the gate electrodes of the MISFETs, respectively; wherein a plurality of second plugs are formed over the second region and are placed along the first direction; wherein each the gate electrodes of the MISFETs includes a metal film; wherein each gate insulating film of each of the plurality of MISFETs has a dielectric constant higher than that of the silicon nitride film; and wherein when a distance between a center of the first plug and a center of the second plug is less than 2.5 times a diameter of the second plug, the second plug is not formed on the second region.