Patent ID: 7635880

Claim:
An image sensor integrated circuit, comprising: a plurality of photodetectors generating electrons excited by incident photons, each of the plurality of photodetectors including: an n-type region receiving the electrons excited by the energy of the photons including: a first n-type region receiving the electrons excited by the energy of the photons; and a second n-type region adjacent to and surrounding the first region, wherein a difference in n-type concentration between the first n-type region and the second n-type region causes electrons to move from the first region to the second region; a plurality of nodes, wherein each of the plurality of photodetectors has a corresponding node of the plurality of nodes; a plurality of transfer devices controlling a transfer of the electrons from said each of the plurality of photodetectors to the corresponding node, each of the plurality of transfer devices including: a first terminal coupled to the n-type region of one of the plurality of photodetectors; a second terminal coupled to one of the plurality of nodes; and a control terminal receiving the control signal, wherein the transfer of the electrons occurs between the first terminal and the second terminal in response to a control signal of sufficient value applied to the control terminal; a first plurality of p-type regions having a first p-type concentration stronger than a background concentration, wherein each of the first plurality of p-type regions has a lateral shape surrounding multiple photodetectors of the plurality of photodetectors; a second plurality of p-type regions having a second p-type concentration stronger than the first p-type concentration; a plurality of reset devices in the second plurality of p-type regions, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active; row and column circuitry; and a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.