Patent ID: 7403440

Claim:
An electronic memory apparatus comprising: a plurality of memory devices each having a plurality of nonvolatile memory cells that are refreshed during operation of the electronic memory apparatus; a control unit coupled to the plurality of memory devices to pass a same periodic clock signal to each of the memory devices, said clock signal causing the memory cells to be refreshed in the memory devices; and a plurality of temperature sensors, each temperature sensor associated with a respective memory device to measure a local temperature near the respective memory device during operation; wherein the plurality of memory devices comprises integrated memory chips that each have a plurality of memory banks, wherein the plurality of memory banks comprise memory cells coupled to word lines in each pulse of the periodic clock signal, wherein based on the measured local temperature, and without changing the frequency of the periodic clock signal, each memory device individually determines a refresh time by changing the number of memory cells simultaneously refreshed, and wherein the number of memory cells simultaneously refreshed is changed by changing the number of word lines simultaneously addressed in each pulse of the clock signal.