Patent ID: 7114058

Claim:
A method for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a computer system having at least one host processor and host memory, the method comprising: in response to a next instruction having a priority number which is pre-assigned prior to being associated with an instruction group, examining a current instruction group, with respect to the priority number of the next instruction, to determine if the current instruction group is completed; examining the next instruction to determine if a corresponding priority number of the next instruction is equal to or lower than a corresponding priority number of a current instruction of the current instruction group; adding the next instruction to the current instruction group if the current instruction group is not completed based on one or more predetermined conditions associated with the current instruction group; dispatching the current instruction group if the current instruction group is completed, wherein the current instruction group is completed when the one or more predetermined conditions are satisfied, wherein the next instruction is not added to the current instruction group if a corresponding functional unit associated with the priority number of the next instruction is not available for execution; adding the next instruction to the current instruction group if the corresponding priority number of the next instruction is higher than the corresponding priority number of the current instruction of the current instruction group; and dispatching without adding the next instruction the current instruction group if the corresponding priority number of the next instruction is equal to or lower than the corresponding priority number of the current instruction of the current instruction group.