Patent ID: 7414564

Claim:
A converter stage configured to process an analog input signal to a corresponding digital code and a residue signal in sample and gain operational modes, comprising: a switched-capacitor residue generator having at least one sample capacitor and an amplifier and arranged to switchably direct, in said sample mode, a sample of said input signal to said sample capacitor and to switchably couple, in said gain mode, said sample capacitor between a selected one of a plurality of reference signals and said amplifier to thereby provide said residue signal with a remnant charge thereby remaining in said sample capacitor; a flash converter arranged to receive said sample during said sample mode and to provide said corresponding digital code and identify said selected reference signal during said gain mode; and at least one replica capacitor arranged to switchably receive a replica charge in said gain mode and to be switchably coupled to said sample capacitor in a portion of said sample mode to thereby substantially cancel said remnant charge with said replica charge.