Patent ID: 7176561

Claim:
A semiconductor device comprising: a first package including a first interposer and a first semiconductor chip, the first interposer having a first wiring pattern, the first semiconductor chip being mounted on the first interposer and being electrically coupled to the first wiring pattern; a second package including a second interposer and a second semiconductor chip, the second interposer having a second wiring pattern, the second semiconductor chip being mounted on the second interposer and being electrically coupled to the second wiring pattern; a contact part electrically coupling the first wiring pattern to the second wiring pattern; and a reinforcer, wherein: a thermal expansion coefficient of the first package is larger than a thermal expansion coefficient of the second package; the second package is disposed so that the second interposer overlaps the first semiconductor chip and the first interposer; the contact part is provided between the first and second interposers so that a first end of the contact part is coupled to the first wiring pattern and a second end of the contact part is coupled to the second wiring pattern; and the reinforcer is provided to expose a part of the contact part and cover circumference of the first end of the contact part.