Patent ID: 7342826

Claim:
A data processing apparatus comprising: a central processing unit; and a nonvolatile memory unit having a plurality of memory cells, a plurality of first bit lines, a plurality of first amplifiers, a plurality of second bit lines, and a plurality of second amplifiers, wherein the central processing unit is capable of accessing to the nonvolatile memory unit via a bus, wherein the nonvolatile memory unit is arranged such that each of the memory cells is coupled to a corresponding one of the first bit lines, and two of the first bit lines each coupled to a different memory cell are coupled to a corresponding one of the first amplifiers via a select circuit, and the first amplifiers are coupled to corresponding ones of the second bit lines, the second bit lines are coupled to corresponding ones of the second amplifiers, and the second amplifiers are coupled to the bus, wherein in a read operation, the select circuit couples said two of the first bit lines and the corresponding one of the first amplifiers in accordance with a signal from the central processing unit, and wherein in a write operation, each of the two memory cells coupled to said two of the first bit lines coupled to said one first amplifier stores different data.