Patent ID: 8085066

Claim:
An apparatus comprising: a data processing circuit configured to generate a first multibit value in response to the data processing circuit executing first instructions stored in memory; a first clocked serial interface (CSI) circuit coupled to the data processing circuit, the first CSI circuit comprising (1) a data output port for serially outputting the first multibit value, and (2) a clock output port for outputting a first clock signal; an encoder circuit comprising (1) a data input port coupled to the data output port of the first CSI circuit, (2) a clock input port coupled to the clock output port of the first CSI circuit, and (3) a data output port for outputting a first encoded signal, the encoder circuit configured to generate the first encoded signal as a function of the first clock signal and the first multibit value received from the first CSI circuit; a first low voltage differential signal (LVDS) circuit comprising (1) an input port coupled to the data output port of the encoder circuit, and (2) a pair of output ports for outputting a first differential signal, the first LVDS circuit configured to generate the first differential signal as a function of encoded signal received from the encoder circuit.