Patent ID: 6912682

Claim:
A signal processor for subjecting data read from a recording medium to predetermined digital signal processing, and subjecting the data, which has been subjected to the predetermined digital signal processing, to error correction for each predetermined error correction block, said signal processor comprising: a first memory operable to sequentially store the data which has been subjected to the predetermined digital signal processing; a descrambling/error detection unit operable to perform descrambling processing to the data which is stored in said first memory and has been subjected to first error correction, and execute error detection to the data after the descrambling processing; a second memory operable to sequentially store the data which has been subjected to the descrambling processing; an error correction unit operable to perform the first error correction to the data stored in said first memory and perform second error correction to the data in said second memory if necessary; and a controller operable to transmit error-free data which has been stored in said second memory to a host computer, wherein, when said descrambling/error detection unit judges that there is an error in the data which has been subjected to the descrambling processing, the data stored in said second memory are read out for each predetermined error correction block, and subjected to error correction by said error correction unit, and when said descrambling/error detection unit judges that there is no error in the data which has been subjected to the descrambling processing, said error correction unit does not perform the second error correction, and said controller transmits the data stored in said second memory to the host computer.