Patent ID: 7479408

Claim:
A method of forming a stack package of two or more area array type chip scale packages, the method comprising: forming a lower chip scale package of an adjacent pair of chip scale packages including a substrate, a plurality of ball land pads formed on a lower surface of the substrate, circuit patterns terminating in a plurality of connection pads formed outside the area in which the plurality of ball land pads are formed, the circuit patterns and the plurality of connection pads formed on the lower surface of the substrate and electrically connected to the plurality of ball land pads, and one or more chips formed on an upper surface of the substrate and electrically connected to the circuit patterns; forming an upper chip scale package of the adjacent pair of chip scale packages in the same manner as the lower chip scale package; attaching the upper chip scale package to the lower chip scale package so that the ball land pads of the upper chip scale package face the opposite direction as the ball land pads of the lower chip scale package; and electrically connecting the circuit patterns of the upper chip scale package to the circuit patterns of the lower chip scale package.