Patent ID: 8730743

Claim:
An integrated circuit comprising: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store the fail address, wherein the semiconductor memory device comprises: a fail address register configured to store the fail address; an internal address generation unit configured to receive a external address and count and generate an internal address; an address comparison unit configured to compare the fail address with the internal address and generate a repair signal; an address decoder configured to enable a word line select signal and a bit line select signal of a memory cell corresponding to the test address or enable the word line select signal and the bit line select signal of a memory cell corresponding to the internal address, in response to the test mode enable signal and the repair signal; and a redundant address decoder configured to enable a redundant word line select signal and a redundant bit line select signal of a redundant cell in response to the repair signal.