Patent ID: 8000139

Claim:
A memory cell comprising: a floating gate NMOS transistor including a source that forms a first terminal of the memory cell, a drain, and a gate; a high voltage PMOS transistor including a source, an extended drain connected to the drain of the floating gate transistor, and a gate forming a second terminal of the memory cell; and a capacitor including a first terminal connected to the gate of the floating gate transistor, and a second terminal forming a third terminal of the memory cell; wherein the floating gate transistor can store a logic state; and wherein combinations of voltages can be applied to the first, second, and third terminals of the memory cell to program, inhibit program, read, and erase the logic state stored by the floating gate transistor; wherein to program the cell a program voltage is applied to the first terminal, and a select voltage is applied to the second and third terminals; to inhibit programming of the cell the second terminal is connected to ground; to read the cell a read voltage is applied to the first terminal, a select voltage is applied to the second terminal, and the third terminal is connected to ground; and to erase the cell an erase voltage is applied to the first terminal, and the second and third terminals are connected to ground.