Patent ID: 7380200

Claim:
A memory system comprising: a memory array including a plurality of memory bits disposed in a plurality of rows and a plurality of columns; a first parity memory having a stored first parity bit associated with each row of said memory array; an address decoder connected to said memory array and said first parity memory receiving an address to be accessed and selecting one row of said memory array and a stored first parity bit corresponding to said address to be accessed; a first parity generator connected to said memory array for generating a new first parity bit corresponding to data stored in said row of said memory array selected by said address to be accessed, comparing said new first parity bit with said selected stored first parity bit, and generating a soft error signal if said new first parity bit fails to match said selected stored first parity bit; a second parity memory having a stored second parity bit corresponding to each column of said memory array associated with a predetermined subset of less than all rows of said memory array; a second parity generator connected to said memory array for generating when triggered a new second parity bit corresponding to data stored in each column of said memory array of said predetermined subset of rows; a memory manager connected to said first parity generator, said second parity memory and said second parity generator, said memory manager for triggering said second parity generator upon receipt of a soft error signal from said first parity generator and said address to be accessed is within said predetermined subset of rows, comparing said new second parity bits with said stored second parity bits following triggering said second parity generator, generating an interrupt signal to a data processor connected to said memory system upon receipt of said soft error signal from said first parity generator if said address to be accessed is not within said predetermined subset of rows or if said address to be accessed is within said predetermined subset of rows and a plurality of said new second parity bits fail to match corresponding stored second parity bits.