Patent ID: 8897077

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; an n type well formed in the semiconductor substrate; a plurality of bit lines arranged along a first direction; a plurality of source lines arranged along the first direction and between the plurality of bit lines; a plurality of memory gate lines arranged along a second direction intersecting the first direction; and a memory cell array having a plurality of P type MIS memory cells formed in the n type well, the plurality of P type MIS memory cells being arranged in matrix, each of the plurality of P type MIS memory cells having a first P+ type drain diffusion region connected to a corresponding one of the plurality of bit lines, a first P+ type source diffusion region connected to a corresponding one of the plurality of source lines, a first channel region between the first P+ type drain diffusion region and the first P+ type source diffusion region, a stack of a gate insulation film, a charge storage layer, an inter-gate insulation film, and a first control gate integrally forming a corresponding one of the plurality of memory gate lines, wherein during a programming operation an n well voltage is applied to the n well, programming voltages lower than the n well voltage are applied to a selected one of the plurality of bit lines and a selected one of the plurality of source lines, a memory gate line voltage higher than the programming voltages is applied to a selected one of the plurality of memory gate lines, a program inhibit voltages higher than the programming voltages are applied to remaining ones of the plurality of bit lines and remaining ones of the plurality of source lines, and inhibit memory gate line voltages lower than the memory gate line voltage are applied to remaining ones of the plurality of memory gate lines.