Patent ID: 7308630

Claim:
A digital system, comprising: (a) N macro circuits, N being a positive integer; (b) an application-specific integrated circuit (ASIC); and (c) a shift/interface system being coupled to the N macro circuits and the ASIC, wherein, in response to the N macro circuits and the ASIC being in normal operation, the shift/interface system electrically couples each macro circuit of the N macro circuits to the ASIC, wherein, in response to the N macro circuits being tested, the shift/interface system is further configured to scan-in macro circuit test data in series, then to feed the macro circuit test data to the N macro circuits, then to receive macro circuit response data from the N macro circuits, and then to scan-out the macro circuit response data in series, wherein, in response to the ASIC being tested, the shift/interface system is further configured to scan-in ASIC test data in series, then to feed the ASIC test data to the ASIC, then to receive ASIC response data from the ASIC, and then to scan-out the ASIC response data in series, wherein the shift/interface system comprises ΣL i (i=1,2, . . . , N) shift/interface circuits, wherein, for i=1,2, . . . , N, L i is a positive integer, the L i shift/interface circuits being coupled one-to-one to L i input pins of the i th macro circuit of the N macro circuits, being coupled one-to-one to L i output pins of the ASIC, and being electrically coupled together in a chain, wherein, for i=1,2, . . . , N, and for j=1,2, . . . , L i , an ij th shift/interface circuit of the L i shift/interface circuits comprises an ij th shift/store unit and an ij th multiplexer, wherein, for i=1,2, . . . , N, in response to the i th macro circuit and the ASIC being in normal operation, for j=1,2, . . . , L i , the ij th multiplexer electrically couples an associated ij th output pin of the L i output pins of the ASIC to an associated ij th input pin of the L i input pins of the i th macro circuit, wherein, for i=1,2, . . . , N, in response to the i th macro circuit being tested, for j=1,2, . . . , L i , the ij th shift/store unit, is configured to scan-in a test bit, and the ij th multiplexer is further configured to transmit the test bit from the ij th shift/store unit to the ij th input pin of the L i input pins of the i th macro circuit, and wherein, for i=1,2, . . . , N, in response to the ASIC being tested, for j=1,2, . . . , L i , the ij th multiplexer is further configured to transmit a response bit from the ij th output pin of the ASIC to the ij th shift/store unit, and the ij th shift/store unit is further configured to receive and scan-out the response bit.