Patent ID: 7111186

Claim:
A method for generating a JBUS clock signal, the method comprising: inputting a central processor (CPU) clock signal to an alignment detection circuit, the CPU clock signal being generated from a phase lock loop (PLL) circuit utilizing a system clock signal having a frequency f SYS , the CPU clock signal having a leading edge at a selected clock cycle and a frequency f CPU , wherein the CPU clock signal has a static phase offset introduced by the PLL circuit; inputting a feedback signal from the PLL circuit to the alignment detection circuit, the feedback signal having a frequency f FDBK that is equal to the frequency F SYS , wherein the feedback signal has the same static phase offset introduced by the PLL circuit as the CPU clock signal; and generating a JBUS clock signal by the alignment detection circuit, a leading edge of the JBUS clock signal being synchronized with the leading edge of the CPU clock signal and having a frequency f JBUS that is equal to the frequency f FDBK .