Patent ID: 7397701

Claim:
A nonvolatile memory, comprising: a memory array including a plurality of columns, each column of the plurality of columns including a plurality of memory cells arranged in a series having a first end and a second end, each memory cell of the plurality of memory cells having at most a single charge storage state, each memory cell of the plurality of memory cells including: a substrate region including source and drain regions; a charge trapping structure storing the single charge storage state represented by a particular amount of charge at a particular part of the charge trapping structure; one or more storage dielectric structures at least partly between the charge trapping structure and the substrate region, and at least partly between the charge trapping structure and a source of gate voltage; a plurality of word lines coupled to said storage dielectric structures, the plurality of word lines acting as the source of gate voltage to the memory array; and logic coupled to the plurality of memory cells, said logic applying bias arrangements to the memory array to program, erase, and read the memory array.