Patent ID: 8117579

Claim:
A method for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer, comprising: generating a first input clock signal from a clock circuit in a computer; generating an intermediate clock signal from an input section of the GSD clock buffer in response to the first input clock signal and one or more first input control signals by: receiving a first clock signal that is derived from a first global LSSD clock signal, generating a gating signal based on the first clock signal and at least the one or more first input control signals, and producing the intermediate clock signal based on the one or more first input control signals and the gating signal; generating a mode control signal from a mode selection control section of the GSD clock buffer in response to a second input clock signal and at least one of the first input control signals; generating a plurality of LSSD clock signals from an output section of the GSD clock buffer in response to the intermediate clock signal and at least the mode control signal.