Patent ID: 8536919

Claim:
Circuitry, comprising: a first flip-flop having a data input, a data output, and a clock input; a second flip-flop having a data input, a data output, and a clock input, wherein the data input of the second flip-flop receives data from the data output of the first flip-flop; and a clock delay circuit that is a replica of the first flip-flop, wherein the clock delay circuit has a data input corresponding to the data input of the first flip-flop, a data output, and a clock input corresponding to the clock input of the first flip-flop, wherein the clock input of the clock delay circuit receives a clock signal, wherein the clock input of the first flip-flop receives the clock signal, wherein the data output of the clock delay circuit provides a delayed version of the clock signal to the clock input of the second flip-flop, wherein the clock signal received at the clock input of the first flip-flop passes through a first number of circuits in the first flip-flop to the data output of the first flip-flop, wherein the clock signal received at the clock input of the clock delay circuit passes through a second number of circuits in the clock delay circuit to the data output of the clock delay circuit, and wherein the second number of circuits is equal to the first number of circuits.