Patent ID: 7486560

Claim:
A virtual ground array device, comprising: a substrate; a first bit line having a first dielectric layer that is in direct contact with a top surface of the first bit line and spacers that are in direct contact with sidewall surfaces of the first bit line; a second bit line having a second dielectric layer that is in direct contact with a top surface of the second bit line and spacers that are in direct contact with sidewall surfaces of the second bit line; a word line; a first diffusion region, the first bit line configured to form a first inversion bit line in or near the first diffusion region when a sufficient voltage is applied to the first bit line, a second diffusion region, the second bit line configured to form a second inversion bit line in or near the second diffusion region when a sufficient voltage is applied to the second bit line, and a gate structure formed on the substrate, the gate structure connected with the word line and configured to form a channel region in the substrate between the first and second inversion bit lines when a sufficient voltage is applied to the gate via the word line.