Patent ID: 8069386

Claim:
A semiconductor device comprising: a memory; a memory BIST (Built-In Self-Test) circuit that performs a test of the memory; and a CPU (Central Processing Unit) that includes: a selector; and a flip-flop that receives and samples a signal output from the selector for accessing the memory to output the sampled signal for supply to the memory, wherein the selector is arranged at a stage preceding to the flip-flop, the selector receiving a first signal for accessing the memory output from the memory BIST circuit and a second signal for accessing the memory generated by the CPU and selecting one of the first and second signals received, the signal selected by the selector being supplied to the flip-flop, wherein the selector comprises: a first selector that selects and outputs an address and control signal generated by the memory BIST circuit, when a test using the memory BIST circuit is performed, and selects and outputs an address and control signal generated by the CPU, when the test using the memory BIST circuit is not performed; and a second selector that selects and outputs write data generated by the memory BIST circuit, when the test using the memory BIST circuit is performed, and selects and outputs write data generated by the CPU, when the test using the memory BIST circuit is not performed, and wherein the flip-flop includes: a first flip-flop that receives and samples an output of the first selector; and a second flip-flop that receives and samples an output of the second selector; the first flip-flop forming an access path of an address and control signal supplied to an address and control terminal of the memory and the second flip-flop forming an access path of write data supplied to a write data terminal of the memory.