Patent ID: 8074060

Claim:
A microprocessor embodied in hardware for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer by selectively initiating instruction retirement early, the microprocessor comprising: a plurality of execution units, each configured to calculate the result of an instruction, wherein the instruction is either an excepting type instruction or a non-excepting type instruction, wherein the excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit to calculate its result, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued to the execution unit to calculate its result; and a retire unit, coupled to the plurality of execution units, configured to make a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result, wherein the retire unit is configured to make the determination before the execution unit outputs the result of the non-excepting type instruction, wherein the retire unit is configured to make the determination after the execution unit outputs the result of the excepting type instruction.