Patent ID: 8362529

Claim:
A power semiconductor device having an adjustable output capacitance, comprising: a semiconductor substrate, having a top surface and a bottom surface, and the top surface of the semiconductor substrate having a first device region and a second device region defined thereon, wherein the semiconductor substrate comprises a substrate and an epitaxial layer, and the epitaxial layer has a first conductive type and is disposed on the substrate; at least one power transistor device, disposed in the semiconductor substrate of the first device region; a heavily doped region, having the first conductive type and disposed in the semiconductor substrate of the second device region, and an implantation concentration of the heavily doped region being higher than an implantation concentration of the epitaxial layer; a capacitor dielectric layer, disposed on the heavily doped region, and the capacitor dielectric layer being in contact with the heavily doped region; a source metal layer, disposed on the top surface of the semiconductor substrate, and the source metal layer being electrically connected to the power transistor device, wherein the source metal layer, the capacitor dielectric layer and the heavily doped region disposed in the second device region form a snubber capacitor, and the source metal layer covers the heavily doped region; and a drain metal layer, disposed on the bottom surface of the semiconductor substrate.