Patent ID: 7716622

Claim:
A method of re-implementing a memory module, or a part of a memory module, that has been implemented on an FPGA device, the method being executable on a computer, comprising: performing a physical timing analysis on an initial implementation of the memory module or the part of a memory module, the memory module being at least partially implemented in a dedicated memory logic block on the FPGA device; re-implementing the memory module or the part of a memory module, the re-implementation of the memory module or the part of a memory module comprising two or more logic blocks; identifying a critical pin in the dedicated memory logic block, the critical pin being one that is susceptible to faults due to a propagation delay identified in the physical timing analysis; separating the dedicated memory logic block by removing the critical pin and assigning the critical pin to at least one of the two or more logic blocks; placing the two or more logic blocks on the FPGA device; and re-connecting the two or more logic blocks, based at least in part on the physical timing analysis, so as to reduce circuit delay.