Patent ID: 6865125

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels; word lines, bit lines and source lines connected to said memory cells; a row decoder configured to select one of said word lines; a column decoder configured to select one of said bit lines; an input/output buffer with N bits to which program data is input to provide read data as an output; an input register with M bits configured to latch program data input in a plurality of cycles; a test data generator configured to produce test data with K bits from input data of said M bits; a column redundancy replacement circuit configured to replace defective columns of L bits in said memory cell array; a page buffer configured to latch output data of (M+K+L) bits from said column redundancy replacement circuit to which data of (M+K) bits is input; and a program circuit configured to generate first or second program voltages based on whether data of said page buffer is non-program data.