Patent ID: 7376872

Claim:
A method of testing memory function in an integrated circuit having embedded memory with multiple addresses to which data can be stored, comprising: storing multiple test vectors from an external tester to addresses in embedded memory; reading from the external tester a first address in the memory to retrieve a first test vector; comparing within the integrated circuit the bits of the retrieved first test vector to corresponding bits of an expected test vector, the comparing producing a first group of comparison bits that indicates on a bit-by-bit basis whether a fault exists in the memory; storing the first group of comparison bits; reading from a second address in embedded memory to retrieve a second test vector; comparing within the integrated circuit the bits of the retrieved second test vector to corresponding bits of an expected test vector, the comparing producing a second group of comparison bits that indicates on a bit-by-bit basis whether a fault exists in the memory; and logically combining the second group of comparison bits with the previously stored first group of comparison bits so as to preserve the state of a comparison bit that indicates a fault exists in the memory.