Patent ID: 8378999

Claim:
A driving circuit of a planar display device, the driving circuit comprising: a controller configured to output a latch signal; and a first and a second data driver configured to receive the latch signal, wherein each of the first and the second driver comprises: a data register configured to fetch a display data; a data latch circuit configured to latch the display data from the data register in response to a leading edge of an internal latch signal; a driver circuit configured to output the display data in response to a trailing edge of the internal latch signal; and an internal latch signal generation circuit configured to receive the latch signal to generate the internal latch signal, wherein the internal latch signal generation circuit comprises: a delay latch signal generator configured to receive the latch signal to generate at least first and second delay latch signals; and a selector configured to select, based on a select signal, one of the first and second delay latch signals as a signal corresponding to the internal latch signal, wherein a leading edge of the first delay latch signal is delayed for a first period from a leading edge of the latch signal, and wherein a leading edge of the second delay latch signal is delayed for a second period from the leading edge of the latch signal, the second period being different from the first period.