Patent ID: 8258572

Claim:
An integrated circuit structure comprising: a static random access memory (SRAM) cell comprising: a first straight fin; a bended fin physically disconnected from the first straight fin, wherein the bended fin comprises a first portion and a second portion parallel to the first straight fin, and wherein the first portion of the bended fin and the first straight fin have a first distance, and the second portion of the bended fin and the first straight fin have a second distance greater than the first distance; a third portion of the bended fin not parallel to the first straight fin and interconnecting the first portion and the second portion; a pull-down transistor comprising a portion of a first gate strip, wherein the first gate strip forms a first and a second sub pull-down transistor with the first straight fin and the first portion of the bended fin, respectively; and a pass-gate transistor comprising a portion of a second gate strip, wherein the second gate strip forms a first sub pass-gate transistor with the first straight fin, and wherein a first number of fins in the pull-down transistor is greater than a second number of fins in the pass-gate transistor.