Patent ID: 8368810

Claim:
A video processing apparatus for de-interlacing, comprising: a video decoder, for decoding a video data stream to generate an interlaced video signal and for transmitting a first interlaced control signal; and a de-interlacing circuit, coupled to the video decoder, the de-interlacing circuit comprising: a detecting unit, for generating a second interlaced control signal according to the interlaced video signal as well as the first interlaced control signal; and an interlacing to progressive converting unit, coupled to the detecting unit, for receiving the interlaced video signal as well as the second interlaced control signal and for converting the interlaced video signal into a first progressive video signal; and a selecting unit, coupled to the detecting unit and the video decoder, for selecting one signal from the first interlaced control signal and the second interlaced control signal as a third interlaced control signal; and a frame rate converting circuit, coupled to the de-interlacing circuit and the selecting unit, for adjusting a frame rate of the first progressive video signal to generate a second progressive video signal according to the third interlaced control signal.