Patent ID: 6882082

Claim:
A data transfer interface, comprising: a first receiver and driver pair coupled to a first segment of a first data bus, said first receiver and driver pair being configured to receive data on said first segment using said first receiver and selectively place data on said first segment using said first driver; a second receiver and driver pair coupled to a second segment of said first data bus, said second receiver and driver pair being configured to receive data on said second segment using said second receiver and selectively place data on said second segment using said second driver; and a selector circuit connected to said first and second receiver and driver pairs, said selector circuit selectively operating said first and second receiver and driver pairs according to a state of a command/address bus coupled to said selector circuit such that in a first state of said command/address bus said first receiver and driver pair passes data between said first bus segment and an I/O device and bypasses said second bus segment, and in a second state of said command/address bus said first and second receiver and driver pairs pass data between respective adjacent bus segments and bypass said I/O device wherein said first and second segments of said first data bus is of a first data width and said I/O device is of a second data width, said first and second data widths being unequal.