Patent ID: 7977803

Claim:
A chip comprising: a silicon substrate; a MOS device in or on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first circuit layer and a second circuit layer over said first circuit layer, wherein said metallization structure comprises a damascene electroplated copper; a second dielectric layer between said first and second circuit layers; a passivation layer over said metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer has a thickness greater than 0.35 micrometers, wherein said passivation layer comprises a nitride layer; a first metal layer over said passivation layer and on said first contact point, wherein said first metal layer has a thickness greater than 0.6 micrometers, wherein said first metal layer comprises a first adhesion layer and a first copper layer over said first adhesion layer; a polymer layer over said passivation layer and said first metal layer, wherein a second opening in said polymer layer is over a second contact point of said first metal layer, wherein said polymer layer covers a top surface and sidewall of said first metal layer, wherein said second contact point is connected to said first contact point through said first opening, wherein said second opening is not vertically over said first opening; and a second metal layer on said polymer layer and said second contact point, wherein said second metal layer is connected to said second contact point through said second opening, wherein said second metal layer has a thickness greater than 0.6 micrometers, wherein said second metal layer comprises a second adhesion layer, a second copper layer over said second adhesion layer and a gold-containing layer over said second copper layer, wherein there is no polymer layer covering a top surface and sidewall of said second metal layer.