Patent ID: 6881636

Claim:
A method of forming a transistor device, comprising: forming a gate stack over a semiconductor substrate; the gate stack comprising an electrically insulative pad, at least one electrically conductive material over the pad, and an electrically insulative cap over the at least one electrically conductive material; the gate stack comprising a pair of opposing sidewalls extending at least along the one or more conductive materials and the cap; forming an electrically insulative material along the sidewalls; anisotropically etching the electrically insulative material to form sidewall spacers along the sidewalls; implanting dopant into the substrate proximate the gate stack to form a pair of source/drain diffusion regions gatedly connected to one another through the gate stack; and depositing a deuterated silicon nitride-containing material over the gate stack and over the sidewall spacers; the deuterated silicon nitride-containing material being deposited from at least one deuterated nitrogen compound and one or more halogenated silicon compounds that do not contain hydrogen isotopes; the deuterated silicon nitride-containing material being a deuterated silicon oxynitride-containing material.