Patent ID: 6988154

Claim:
A user-configurable processing device having a user-configured processor interface device and digital signal processing (DSP) core associated therewith, comprising: a reduced instruction set computer (RISC) core in operative communication with said interface device; at least one memory port, said at least one memory port adapted to transfer data and signals to and from a storage device; at least one function port, said at least one function port adapted to transfer data and signals to and from a macro function; a data transfer fabric adapted to transfer data and signals between said at least one memory port and said at least one function port, and an arbitration unit adapted to arbitrate access to various portions of said storage device by said macro function; wherein said DSP core is specifically configured by said user to inter-operate with at least one of (i) an instruction and operand decode mechanism, (ii) an auxiliary register, and (iii) on-core memory resources associated with said RISC processor.