Patent ID: 7505335

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell which stores a plurality of data items in n-valued (n is a natural number equal to one or more) threshold voltages; a first data storage circuit which is connected to the memory cell and which stores externally inputted data of a first logic level or a second logic level; a second data storage circuit which is connected to the memory cell and the first data storage circuit and which stores the data of the first logic level or second logic level read from the memory cell; and a control circuit which controls the memory cell and the first and second data storage circuits and which manipulates the data stored in the first and second data storage circuits in the middle of writing data into the memory cell, reproduces the externally inputted data, and resumes writing data into the memory cell, and wherein the control circuit transfers data stored in the second data storage circuit to the first data storage circuit in a read operation.