Patent ID: 8031156

Claim:
A data driving circuit of a liquid crystal display, comprising: a decoder that receives n bits data and outputs 2 n selection signals where n is a natural number greater than 2; a switching part that switches a gamma reference voltage from a gamma reference voltage generator in accordance with the 2 n selection signals supplied by the decoder to output a first voltage and a second voltage; a voltage distributor that selects one of the first voltage and the second voltage from the switching part as a first output voltage in accordance with the most significant bit of input data including a plurality of n data bits, that multiplexes the first voltage and the second voltage to be output as one or more multiplexed output voltages wherein each of the one or more multiplexed output voltages is a voltage level of one of the first voltage and the second voltage selected in accordance with bits of the input data other than the most significant bit, and that outputs the first voltage as a final output voltage where n is a natural number greater than 2; and an output buffer that is driven by the first output voltage, the one or more multiplexed output voltage, and the final output voltage, wherein the voltage distributor includes a switch that switches one of the first voltage and the second voltage as a switched output voltage in accordance with the most significant bit of the 3 bit input data to be output to the output buffer, wherein the switch includes an inverter that inverts a level of the most significant bit of the input data having n bits to be output as an inverted most significant bit data and a transmission gate that selectively switches one of the first voltage and the second voltage to be output to the output buffer via a first output terminal in accordance with the most significant bit of the input data and the inverted most significant bit data output by the inverter, and wherein the voltage distributor further includes a multiplexing part that receives the first voltage and the second voltage and outputs the one or more multiplexed output voltages to the output buffer, each of the one or more multiplexed output voltages being one of the first voltage and the second voltage selected in accordance with bits of the 3 bit input data other than the most significant bit of the 3 bit input data.