Patent ID: 8863052

Claim:
A system for generating a structurally aware timing model for operation of a predetermined circuit design having at least one input terminal, at least one output terminal, and at least one component interconnected therebetween, the system comprising: a timing analysis unit executing to perform a timing analysis on the predetermined circuit design to generate a timing report including a set of operational timing characteristics respectively corresponding to a set of terminal pairs in the predetermined circuit design; a selection unit coupled to said timing analysis unit, said selection unit selecting from said set of terminal pairs at least one of each terminal pair having one of an input or output terminal; a model generation unit coupled to said timing analysis unit and said selection unit, said model generation unit executing to model operational timing of the predetermined circuit design, said model generation unit generating a timing arc indicative of delay in signal traversal between selected terminal pairs relative to a predetermined timing requirement thereof; and, a structural characterization unit coupled to said model generation unit, said structural characterization unit executing to selectively determine from the predetermined circuit design at least one preselected structural feature for each distinct signal path extending between each selected terminal pair, said structural characterization unit generating a structural weight indicative of said preselected structural feature for a representative one of the distinct signal paths selectively identified for each selected terminal pair; wherein a hybrid model is generated to include said timing arcs and said structural weights, each said structural weight being associated with one of said timing arcs; wherein said selection unit selects from said set of terminal pairs each terminal pair of a first, a second, or a third type, said first type pairing one said input terminal with one said output terminal, said second type pairing one said input terminal with one intermediate terminal defined by a component of memory type, and said third type pairing one of said intermediate terminals defined by a component of memory type with an output terminal.