Patent ID: 8097964

Claim:
An integrated circuit (IC), comprising: a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level having inter-level dielectric (ILD) layers between respective ones of said plurality of metal interconnect levels, and a bottom side, and at least one TSV array comprising a plurality of TSVs with each TSV extending from said top side to said bottom side and comprising an electrically conductive filler material surrounded by a dielectric liner; wherein said plurality of TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns; wherein at least a portion of said plurality of TSVs in said array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from said plurality of metal interconnect levels, and wherein at least one of said pair of exterior rows or at least one of said pair of exterior columns include a lower number of said electrically connected TSVs compared to a maximum number of said electrically connected TSVs in said plurality of interior rows and said plurality of interior columns, respectively.