Patent ID: 7508897

Claim:
A PLL circuit, comprising: a counter, being programmable, which divides a frequency of an input signal; a memory for storing plural patterns of set cycles of the counter; a serial bus for transmitting, to the memory, data for selecting one of the set cycles stored in the memory; and a parallel bus for transmitting, to the counter, the set cycle read out from the memory based on the data, wherein: the counter includes a frequency divider for dividing a frequency of an external signal at a frequency-dividing ratio chosen from a plurality of set frequency-dividing ratios in order to supply a signal for counting a number of pulses, and the memory stores plural patterns of the set frequency-dividing ratios in association with the set cycles and reads out one of the set frequency-dividing ratios and one of the set cycles simultaneously based on the data, and the PLL circuit includes a frequency-dividing parallel bus through which the set frequency-dividing ratio read out from the memory based on the data is transmitted to the frequency divider.