Patent ID: 7106655

Claim:
A delay-lock loop for generating a plurality of clock signals having predetermined phases relative to each other using an input clock signal, the system comprising: a first delay line receiving the input clock signal, the first delay line generating a first clock signal by delaying the input clock signal with a delay of D F , where D F is a fixed delay time; a second delay line receiving the input clock signal, the second delay line generating a second clock signal by delaying the input clock signal with a delay of D F +MD V , where D V is a variable delay time corresponding to a control signal applied to the second delay line and M is the ratio of the phase of the second clock signal relative to the phase of the first clock signal; a third delay line receiving the input clock signal, the third delay line generating a third clock signal by delaying the input clock signal with a delay of D F +D V ; and a phase detector receiving the first clock signal and the third clock signal, the phase detector being operable to generate the control signal corresponding to a difference between the phase of the first clock signal and the phase of the third clock signal.