Patent ID: 7035150

Claim:
A memory device, comprising: a plurality of storage cells arranged in an array or rows and columns; a plurality of bitlines, each bitline coupled to a plurality of storage cells along one of the columns; a plurality of wordlines, each wordline coupled to a plurality of storage cells along one of the rows; a column decoder having a plurality of control outputs, each of the control outputs coupled to a column of the array; and a variable delay circuit coupled to the column decoder and including a control input, the delay circuit causing the control outputs of the column decoder to be variably delayed based upon the control input, wherein the delay circuit comprises: a clock input; first transmission gate with an input coupled to the clock input, the first transmission gate comprising an n-channel transistor coupled in parallel with a p-channel transistor; a first delay element with an input coupled to an output of the first transmission gate, the first delay element including at least one inverter; a second transmission gate with an input coupled to an output of the first delay element; the second transmission gate comprising an n-channel transistor coupled in parallel with a p-channel transistor; a second delay element with an input coupled to an output of the first delay element, the second delay element including at least one inverter; a third transmission gate with an input coupled to an output of the second delay element, the third transmission gate having an output coupled to an output of the second transmission gate, the third transmission gate comprising an n-channel transistor coupled in parallel with a p-channel transistor; and logic circuitry adapted to generate a delay time, wherein the amount of delay is variable by activating particular combinations of the first, second and third transmission gates.