Patent ID: 7995413

Claim:
A memory device comprising: a memory plane including memory cells at the intersection of lines and columns of the memory plane; read amplifiers coupled to the columns of the memory plane; and a dummy path adapted to deliver an activation signal for activating the read amplifiers, wherein the dummy path includes: a first dummy column including dummy memory cells, two dummy bit lines to which the dummy memory cells are connected, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines by a discharge current that is adapted to control delivery of the activation signal; at least one second dummy column including dummy memory cells, the at least one second dummy column being adapted to generate a dummy leakage current that represents a leakage current of a column of the memory plane that is selected in read mode; and a circuit adapted to copy the dummy leakage current to the one dummy bit line of the first dummy column that is discharged by the discharge current, so that the discharge of the one dummy bit line of the first dummy column is also dependent on the dummy leakage current.