Patent ID: 7693930

Claim:
An asynchronous full adder, comprising: a set of combinational circuits that performs full addition with two addends and a carry-in that are dual-rail encoded, and to output a sum and a carry-out that are dual-rail encoded, each combinational circuit in the set including a plurality of columns of cascaded N-channel transistors between a node and ground, the combinational circuit performing full addition to generate an output, the output being one of the sum and the carry-out, the cascaded N-channel transistors being N-channel metal-oxide-semiconductor field-effect transistors (N-ch MOSFETs), each combinational circuit including: a detection device to detect input values; a precharge device to precharge the node if the detection device detects Null of an input value; a connecting device to connect input signals to gate terminals of the N-ch MOSFETs based on a truth table which specifies a combinational logic required to compute an output signal from input signals; a buffer to drive the node to a voltage of the output value; and the drain terminals of the N-ch MOSFETs at uppermost stages of all columns being connected to the node, and source terminals of the N-ch MOSFETs at lowermost stages of all columns being connected to the ground.