Patent ID: 7538705

Claim:
An over-sampling analog-to-digital converter (ADC) having improved voltage reference offset cancellation and reduced source induced 1/f noise, said ADC comprising: a sigma-delta modulator having plus and minus analog inputs, plus and minus reference voltage inputs and an output supplying serial digital information therefrom, wherein the sigma-delta modulator comprises: a plus input voltage capacitor having a capacitance of A*C/2, a minus input voltage capacitor having a capacitance of A*C/2, a first pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to the plus and minus analog inputs, respectively, a second pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to the minus and the plus inputs, respectively, a plus reference voltage capacitor having a capacitance of C/2, a minus reference voltage capacitor having a capacitance of C/2, a fifth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltage inputs, respectively, a sixth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltage inputs, respectively, a seventh switch adapted for switchably coupling the plus and minus reference voltage capacitors together, a third plurality of switches coupled to the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors, and adapted for switchably coupling a common mode voltage, VCM, to these capacitors, and a fourth pair of switches adapted for coupling the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors to a differential input of an amplifier, wherein the switches are sequenced in a charge phase and a transfer phase to produce five equally distributed voltage outputs from the amplifier of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN−VREF/2 and A*VIN−VREF, where A is gain, VIN is an input voltage, and VREF is a reference voltage; a chopper stabilized voltage reference supplying plus and minus reference voltages to the plus and minus reference voltage inputs of the sigma-delta modulator; and a chopper clock control coupled to the chopper stabilized voltage reference and the output of the sigma-delta modulator, wherein the chopper clock control uses the serial digital information from the output of the sigma-delta modulator to generate chopper clocks that cause the chopper stabilized voltage reference to supply reference voltages to the sigma-delta modulator that comprise an equal number of positive voltage offsets and negative voltage offsets for each level of digital-to-analog conversions, and whereby an average of the positive and negative voltage offsets cancel out voltage offset contribution to the reference voltages supplied to the sigma-delta modulator.