Patent ID: 7310258

Claim:
A semiconductor memory device comprising: a top bank area having a plurality of top banks, the top bank area arranged above a virtual bisector, wherein the virtual bisector divides a minor-axis of the semiconductor memory device; a bottom bank area having a plurality of bottom banks, the bottom bank area arranged below the virtual bisector; a first data I/O pad arranged in a top margin of the top bank area and coupled to the plurality of top banks; a second data I/O pad arranged in a bottom margin of the bottom bank area and coupled to the plurality of top banks; and a control line block, arranged between the top bank area and the bottom bank area in a direction of the virtual bisector, for transmitting inputted command and address, wherein one half of data corresponding to the inputted command and address are outputted from one of the plurality of top banks through the first data I/O pad and another half of the data are outputted from one of the plurality of bottom banks through the second I/O pad.