Patent ID: 7458053

Claim:
A multi-pass method for designing at least a portion of a circuit layout on a substrate, comprising: receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame, the fill pattern including a plurality of structures selected from the group consisting of fill structures, cheese structures and combinations thereof, wherein said first level forbidden area extends at least over the electrical component; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame, the first level framing having the fill pattern; adding a conductor to the next level frame, the conductor connected to the electrical component, a first portion of the conductor being in the first level frame and a second portion of the conductor being in the next level fill area; generating a next fill pattern on the next level fill area outside of a forbidden area of said next level fill area, the next fill pattern including a plurality of structures selected from the group consisting of fill structures, cheese structures and combinations thereof, wherein said next level forbidden area extends at least over the second portion of the conductor; and modifying the first level forbidden area to extend at least over the electrical component and the first portion of the conductor and removing any of the plurality of structures in the fill pattern that are within the modified first level forbidden area.