Patent ID: 7466647

Claim:
An 2:1 muxing mechanism for managing flow of data in a data processing system, said 2:1 muxing mechanism comprising: a 2:1 multiplexer, wherein the 2:1 multiplexer manages only two available control functions, wherein one of the only two available control functions is chosen from a bypass function and an array read function, and wherein the bypass function combines a regular bypass functionality and a page bit bypass functionality, and wherein the array read function reads data associated with a page bit into an array; a page bit bypass signal, wherein the page bit bypass signal is set to a default value, wherein the page bit bypass signal maintains the default value when the data in the array is not accessed, wherein the regular bypass functionality of the bypass function is activated if the page bit bypass signal maintains the default value, wherein the page bit bypass signal does not maintain the default value when the data in the array is accessed, and wherein the page bit bypass functionality of the bypass function is activated if the page bit bypass signal does not maintain the default value and the page bit has a value equal to a first value; an array read signal, wherein the array read signal activates the array read function if the page bit bypass signal does not maintain the default value and the page bit has a value not equal to the first value; an array read control signal mechanism, wherein the array read control signal mechanism is operably connected to the 2:1 multiplexer, and wherein the array read control signal mechanism provides the array read signal to the 2:1 multiplexer; and a page bit bypass control mechanism, wherein the page bit bypass control signal mechanism is operably connected to the 2:1 multiplexer, wherein the page bit bypass control signal mechanism is also operably connected to the array read control signal mechanism and wherein the page bit bypass control signal mechanism provides the page bit bypass signal to the 2:1 multiplexer.