Patent ID: 8466060

Claim:
A stackable vertical power MOSFET (SVP-MOSFET) device comprising: a semiconductor substrate with a bottom drain metal layer formed thereon; a plurality of gate regions and source-body regions formed atop the semiconductor substrate; a patterned gate metal layer and a patterned source-body metal layer respectively connecting the gate regions and the source-body regions; and: a conductive through substrate drain via (TSDV), formed through the semiconductor substrate but insulated there from whilst in contact with the drain metal layer, having a top drain contacting means and a bottom drain contacting means for respectively making a top surface and a bottom surface electrical contact to the TSDV; a conductive through substrate gate via (TSGV), formed through the semiconductor substrate but insulated there from whilst in contact with the gate metal layer, having a top gate contacting means and a bottom gate contacting means for respectively making a top surface and a bottom surface electrical contact to the TSGV; and a conductive through substrate source via (TSSV), formed through the semiconductor substrate but insulated there from whilst in contact with the source-body metal layer, having a top source contacting means and a bottom source contacting means for respectively making a top surface and a bottom surface electrical contact to the TSSV whereby, upon stacking of a plurality of the SVP-MOSFET devices, the thus formed SVP-MOSFET stack functions as a parallel electrical connection of the stacked SVP-MOSFET devices with a correspondingly reduced on-resistance Rds, increased current-carrying capacity and reduced package footprint.