Patent ID: 7450422

Claim:
A NAND memory array, comprising: at least two bit lines; and at least two strings of series-coupled non-volatile memory cells; wherein a first end of a first string of series-coupled non-volatile memory cells is selectively coupled to a first bit line with no intervening memory cells; wherein a second end of the first string of series-coupled non-volatile memory cells is selectively coupled to a second bit line with no intervening memory cells; wherein a first end of a second string of series-coupled non-volatile memory cells is selectively coupled to the second bit line with no intervening memory cells; and wherein the first end of the first string of series-coupled non-volatile memory cells and the first end of the second string of series-coupled non-volatile memory cells are selectively coupled to the first bit line and the second bit line, respectively, in response to a single control signal.