Patent ID: 8634174

Claim:
A circuit for protecting an integrated circuit from an electrostatic discharge (ESD) event, the circuit comprising: a power supply rail; an input/output pad; a buffer circuit comprising a first field-effect transistor with a gate coupled to the input/output pad, a source, a gate dielectric layer, and a body; a second field-effect transistor including a gate, a drain coupled to the body of the first field-effect transistor, and a source selectively coupled to the power supply rail; and a trigger circuit coupled with the input/output pad and with the gate of the second field-effect transistor, the trigger circuit configured to output a first voltage to the gate of the second field-effect transistor in response to the ESD event at the input/output pad and while the integrated circuit is unpowered, wherein the second field-effect transistor enters a cutoff condition in response to the first voltage at the gate of the second field-effect transistor so that the second field-effect transistor electrically isolates the body of the first field-effect transistor from the power supply rail.