Patent ID: 8275568

Claim:
A semiconductor test system with self-inspection of an electrical channel, comprising: a tester head, including a plurality of pin electronics cards (PE cards) inserted therein, the plurality of pin electronics cards containing a plurality of power channels, a plurality of I/O channels and a plurality of drive channels; a plurality of parameter detection units, being respectively electrically connected to the plurality of power channels, the plurality of I/O channels and the plurality of drive channels in the plurality of pin electronics cards; and a self-inspection controller, being electrically connected respectively to the plurality of power channels, the plurality of I/O channels and the plurality of drive channels in the plurality of pin electronics cards, and to the plurality of parameter detection units, in which the self-inspection controller controls inputting different inspection signals respectively to each of the plurality of power channels, each of the plurality of I/O channels and each of the plurality of drive channels, and the plurality of parameter detection units detect response signals respectively produced by each of the plurality of power channels, each of the plurality of I/O channels and each of the plurality of drive channels in response to the inspection signals respectively received thereby and output the same to the self-inspection controller.