Patent ID: 7310255

Claim:
A non-volatile memory, comprising: an array of memory cells to be programmed relative to a demarcation threshold voltage; a programming circuit for applying a programming pulse to the group of memory cells; a sensing circuit with a first configuration to verify the cells of the group relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage; a memory controller; said controller alternately controlling the operations of the programming circuit and the sensing circuit with the first configuration until one of the cells has been verified relative to the first reference threshold voltage; a program retardation circuit for slowing down subsequent programming of a memory cell that has been verified to the first reference threshold voltage; a program inhibit circuit for inhibiting a memory cell that has been verified relative to the demarcation threshold voltage from further programming; and said controller alternately controlling the operations of the programming circuit and the sensing circuit to verify the cells of the group relative to the first reference threshold voltage followed by verify relative to the demarcation threshold voltage until all cells in the group has been program verified relative to the demarcation threshold voltage.