Patent ID: 7804733

Claim:
A method for power management, comprising: activating all phases of a multi-phase memory voltage regulator; determining whether to decrease power supplied to at least one memory device, wherein determining whether to decrease the power supplied to the at least one memory device includes determining the extent to which a plurality of memory sockets are populated; if it is determined to decrease the power supplied to the at least one memory device, deactivating at least one phase of the multi-phase memory voltage regulator after the deactivating, setting a number of activated phases equal to a maximum number of phases; determining whether a central processing unit (CPU) associated with the multi-phase memory voltage regulator is in an active state or an idle state; if the CPU is in the idle state, deactivating at least one phase of the multi-phase memory voltage regulator; determining whether a power demand is less than a predetermined power threshold; and if the power demand is less than the predetermined threshold and the number of activated phases is greater than one, deactivating at least one phase of the multi-phase memory voltage regulator.