Patent ID: 8924627

Claim:
A flash memory device comprising: a plurality of flash memories, including a first flash memory and a second flash memory; a flash controller for accessing the first flash memory over a first channel and the second flash memory over a second channel; and a host interface operable to: receive a multi-command descriptor block from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request; select a first group of the access commands to execute concurrently and select a second group of the access commands to execute concurrently; after receiving the multi-command descriptor block, receive the first group of access commands from the host; execute the first group of access commands concurrently by accessing at least the first and second flash memories concurrently; after receiving the multi-command descriptor block, receive the second group of access commands from the host; and execute the second group of access commands concurrently by accessing at least the first and second flash memories concurrently.