Patent ID: 7906992

Claim:
A latch circuit, comprising: a bistable pair of transistors connected between a reset switch and a first supply voltage, and having a first port configured to receive a first current signal contemporaneously with a second current signal and to produce a first output voltage, and a second port configured to receive a third current signal and to produce a second output voltage; and a vertical latch connected between said first supply voltage and a second supply voltage, and connected to said first port; wherein said vertical latch comprises: a first current mirror transistor pair connected to said bistable pair of transistors and configured to produce said second current signal; and a second current mirror transistor pair connected to said first current mirror transistor pair; and wherein first and second drains of said first current mirror transistor pair are directly connected respectively to corresponding first and second drains of said second current mirror transistor pair to form respective first and second non-grounded drain nodes.