Patent ID: 7356435

Claim:
A semiconductor test apparatus, comprising: a first waveform generating means that generates a common pattern waveform corresponding to common information common to each of a plurality of semiconductor devices; a plurality of second waveform generating means that generates individual pattern waveforms indicative of an address of the defect memory area in each of the plurality of semiconductor memory devices, which is identified by each of the plurality of individual information in response to each of the plurality of semiconductor devices; and a waveform switching unit that selectively performs an operation of inputting the common pattern waveform generated from said first waveform generating means in common and an operation of inputting the individual pattern waveforms respectively generated from said plurality of second waveform generating means individually, as write addresses to write data into each of the plurality of semiconductor devices; and a test controlling unit configured to output information relating to the common pattern waveform and the individual pattern waveforms, wherein said first waveform generating means generates common writing data to identify a defect memory area of the semiconductor memory devices, and said waveform switching unit individually inputs the individual pattern waveform into each of the plurality of semiconductor memory devices, and in common inputs the writing data in order to write the writing data on the writing address.