Patent ID: 7904767

Claim:
A semiconductor test device, comprising: a test signal decoder decoding burn-in test mode signals to generate a first test signal which controls main wordlines driving signal and a second test signal which controls sub wordline driving signal; and a plurality of bank control units generating a multi wordline test mode signal corresponding to a bank control signal when the first and second test signals are disabled, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test wherein each bank control unit enables the main wordline driving signal regardless of some of a plurality of addresses in response to the bank control signal when the first test signal is disabled, enables the main wordline driving signal in response to the some of addresses when the first test signal is enable, enables the sub wordline driving signal in response to a remaining portion of the addresses when the second test signal is disabled, enables the sub wordline driving signal regardless of the remaining portion of the addresses in response to enabled the second test signal when the second test signal is enabled, and enables the wordlines in accordance to enabling of the main wordline driving signal and the sub wordline driving signal.