Patent ID: 7864909

Claim:
An apparatus, comprising: a plurality of data inputs that is operative to receive a first plurality of data signals, such that each of the first plurality of data signals has a first frequency; a clock input that is operative to receive a clock signal; a common clock delay element that is operative to modify the clock signal thereby generating a modified clock signal; a plurality of clock delay elements that is operative to process the modified clock signal thereby generating a modified plurality of clock signals such that each of the modified plurality of clock signals corresponds to one of the first plurality of data signals; a plurality of data delay elements that is operative to modify each of the plurality of data signals, respectively, thereby generating a second plurality of data signals; a plurality of demultiplexer groups that is operative to demultiplex the second plurality of data signals, based on the modified plurality of clock signals, thereby generating a third plurality of data signals, such that each of the third plurality of data signals has a second frequency; and a plurality of data outputs that is operative to output the third plurality of data signals.