Patent ID: 6895498

Claim:
An apparatus for writing a target address of a taken branch instruction into a branch target address cache (BTAC) upon execution of the taken branch instruction, the BTAC having a plurality of storage elements for caching target addresses of executed branch instructions, each of the plurality of storage elements comprising first and second entries for storing a target address, the apparatus comprising: a global indicator, for specifying a global one of the first and second entries of the BTAC plurality of storage elements; and branch control logic, coupled to said global indicator, for selecting one of the first and second entries to write the taken branch instruction target address into based on said global indicator, wherein said global one of the first and second entries specifies which of the first and second entries was last written to in any one of the plurality of storage elements when both of the first and second entries therein were invalid, wherein said branch control logic selects an opposite of said global one of the first and second entries specified in said global indicator to write the taken branch instruction target address into, wherein said branch control logic updates said global indicator to specify said selected entry, wherein the plurality of storage elements also includes a valid indicator associated with each of the first and second entries, for indicating whether the target address stored therein is valid or invalid, wherein if only one of the first and second entries is invalid in one of the plurality of storage elements that is selected for updating, said branch control logic selects said invalid entry to write without regard to said global indicator.