Patent ID: 7633791

Claim:
A memory device, comprising: a read-write circuit serving as a global sense amp, wherein the read-write circuit includes a common line for connecting to its component circuits having a read circuit, a latch circuit, a write circuit, and at least a select circuit, such that the read circuit includes a common pre-charge transistor for pre-charging the common line to a pre-charge voltage, a global pre-amp transistor for reading the common line, a global pre-set transistor for pre-setting a global pre-amp node connecting to the global pre-amp transistor, and a global main-amp transistor for reading to the global pre-amp node when a global amp enable transistor is enabled; and the latch circuit includes a cross coupled inverter latch connecting a pair of latch nodes, a latch reset transistor for resetting one of the latch nodes, and a pair of series transistors having a row select transistor pair for connecting to the pair of the latch nodes and a column select transistor pair for connecting to a pair of data lines; and the write circuit includes an inverter receiving one of the latch nodes, and a write enable transistor receiving an output of the inverter and driving the common line, where the inverter is composed of a pull-up transistor and a pull-down transistor which is supplied by a variable voltage source; and the select circuit is composed of a global pre-charge transistor for pre-charging a global bit line to the pre-charge voltage and a global select transistor for connecting the global bit line to the common line; and a local sense amp including a local pre-charge transistor for pre-charging a local bit line to the pre-charge voltage, a local pre-amp transistor for connecting to a local pre-amp node, a local pre-set transistor for pre-setting the local pre-amp node, a local main-amp transistor for reading to the local pre-amp node when a local amp enable transistor is enabled; and a write transistor is connected to the local bit line for connecting to the global bit line; and a memory cell connecting to the local bit line, wherein the memory cell is composed of a pass transistor and a capacitor for configuring a dynamic random access memory; and a variable voltage regulator for generating the pre-charge voltage as the variable voltage source; and a delay circuit for generating a delayed signal which disables the global enable transistor when reading.