Patent ID: 7413938

Claim:
A method of manufacturing a thin film transistor array substrate comprising: forming a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line; forming a gate insulating film on the substrate to cover the gate pattern thereon and an exposed portion of the substrate; forming a semiconductor pattern and a source/drain pattern over the semiconductor pattern, the source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a lower data pad electrode connected to the data line; forming a transparent electrode pattern, a passivation film pattern, and a gate insulation pattern, wherein the transparent electrode pattern covers a portion of the substrate, the transparent electrode pattern including a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode, and the passivation film pattern is stacked on the gate insulation pattern, the passivation film pattern and the gate insulation pattern covering a remaining portion of the substrate excluding the portion of the substrate covered by the transparent electrode pattern; shaping a lateral surface of the source/drain pattern exposed by the passivation film pattern to be further inclined, downward and outward, than the passivation film pattern; depositing a transparent material on the substrate having the photo-resist pattern formed thereon; and removing portions of the transparent electrode material on the photo-resist pattern, and the photo-resist pattern beneath, by a stripping process of the photo-resist pattern using a lift-off method, to form a transparent electrode pattern.