Patent ID: 7594102

Claim:
A method of operating a processor to fetch and execute a plurality of instructions, the processor comprising an execution unit, and the method comprising: a) operating the processor in a first mode to execute in the execution unit a first subset of instructions in the plurality of instructions, with each instruction in the first subset being executed no more than one time each time the instruction is fetched; and b) operating the processor in a second mode to execute in the execution unit a second subset of instructions in the plurality of instructions, with each instruction in the second subset executed a plurality of times each time the instruction is fetched, the second subset of instructions comprising a plurality of operands, each operand identified by an address, and wherein: operating the processor in the second mode comprises: comparing the address of each of the plurality of operands to a value defining a first range; and selectively processing each operand of the plurality of operands based on the comparing, the selectively processing comprising: for a first portion of the plurality of operands, renaming addresses identifying the operands successive times of the plurality of times that an instruction having an operand in the first portion is executed, the first portion of the plurality of operands each being identified based on the comparing as having an address in the first range; and for a second portion of the plurality of operands, using the same addresses identifying the operands for successive times of the plurality of times that an instruction having an operand in the second portion is executed, the second portion of the plurality of operands each being identified based on the comparing as having an address in a second range, the second range being different than the first range.