Patent ID: 8117392

Claim:
A physically distributed cache memory system comprising: an interconnection network; first level cache memory slices coupled with the interconnection network to generate tagged ordered store requests, each tagged ordered store request having a tag including a requestor identification and a store sequence token, wherein each of the first level cache memory slices has a unique requestor identification and a sequence token register to generate the tagged ordered store requests; and second level cache memory slices coupled with the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system to maintain a coherency of the physically distributed cache memory system without requiring interprocessor communications in response to each tag of the tagged ordered store requests, wherein the second level cache memory slices to request reordering of any tagged ordered store requests that are received out of order by at least one of the second level cache memory slices, wherein the second level cache memory slices are further to request reordering of any cache sequence array updates associated with the out of order tagged ordered store requests, wherein a cache sequence array is capable of identifying a next tagged ordered store request to be received at the second level cache memory slices.