Patent ID: 8918591

Claim:
In a data processing system having a system interconnect, a first processor coupled to the system interconnect, and a cache coherency manager (CCM) coupled to the system interconnect, wherein the first processor comprises a first cache, a method comprising: generating, by the CCM, one or more first snoop requests to the first cache of the first processor; storing the one or more first snoop requests to the first cache of the processor into a first snoop queue; setting a first cache enable indicator to indicate that the first cache of the first processor is to be disabled; in response to setting the first cache enable indicator to indicate that the first cache of the first processor is to be disabled, selectively invalidating the one or more first snoop requests to the first cache of the first processor, wherein the selectively invalidating includes invalidating the one or more first snoop requests when a first invalidate snoop queue indicator of the first processor has a first state, and selectively invalidating also includes not invalidating and completing the one or more first snoop requests when the first invalidate snoop queue indicator has a second state that is different from the first state; and disabling the first cache.