Patent ID: 7202533

Claim:
An integrated circuit structure comprising: (a) a first dielectric layer disposed on a semiconductor layer; (b) a first thin film resistor disposed on the first dielectric layer; (c) a second dielectric layer disposed on the first dielectric layer and the first thin film resistor; (d) a second thin film resistor disposed on the second dielectric layer; (e) a first layer of interconnect conductors disposed on the second dielectric layer including a first interconnect conductor contacting a first contact area of the first thin film resistor through a corresponding via opening, a second interconnect conductor contacting a second contact area of the first thin film resistor through a corresponding via opening, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor; (f) a third dielectric layer disposed on the second dielectric layer, the first layer of interconnect conductors and the second thin film resistor; and (g) a second layer of interconnect conductors disposed on the third dielectric layer including a fourth interconnect conductor extending through a corresponding opening in the third dielectric layer to contact the second interconnect conductor.