Patent ID: 7551020

Claim:
A compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the compensation circuit comprising: a first current source operative to generate a first current having a value which is substantially constant; a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source; a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current, whereby the at least one control signal generated by the processor is adapted to compensate the output impedance of the at least first MOS device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected; wherein the second current source comprises: a reference source generating a voltage which is proportional to a supply voltage of the compensation circuit; a voltage clamp operative to clamp the voltage generated by the reference source across at least a second MOS device, a gate of the at least second MOS device receiving the at least one control signal, the at least second MOS device being substantially matched to the at least first MOS device to be compensated; and a current mirror circuit operative to generate the second current, the second current being substantially matched to a current flowing through the at least second MOS device.