Patent ID: 7372742

Claim:
A memory system comprising: a controller that generates memory signals; and a non-volatile memory device, coupled to the controller, that operates in response to the memory signals, the device comprising: an array of memory cells arranged in a plurality of memory blocks, each memory block having a plurality of memory cells that are arranged in rows and columns such that the rows are coupled to word lines and the columns are coupled to bit lines; and a control circuit that is adapted to perform an erase operation on a first memory block of the plurality of memory blocks, perform an erase verify read operation on the first memory block to determine if one or more of the memory cells is unerased, perform a normal memory read operation on the first memory block in response to an erase verify read operation result indicating one or more memory cells are unerased, wherein the normal memory read operation determines which of the plurality of memory cells are unerased, and perform a selective erase operation only on wordlines coupled to unerased memory cells.