Patent ID: 7010673

Claim:
A method for pipelined processing, comprising a plurality of pipelined processing stages and wherein the method comprising the steps of: receiving a block ( 4 ) in a first logic unit ( 11 ) in a processing means ( 3 ); looking up a first instruction ( 13 a ) corresponding to a first program counter ( 7 a ), associated with the block ( 4 ) in a first instruction table ( 12 a ) comprising at least the first instruction ( 13 a ); executing at least one operation associated with the first instruction ( 13 a ) in the first logic unit ( 11 ); creating in the first logic unit ( 11 ) a second program counter ( 7 b ), associated with the block ( 4 ); receiving the block ( 4 ) in a second logic unit ( 14 ) in the processing means ( 3 ); looking up a further instruction ( 13 f ) corresponding to the second program counter ( 7 b ) in a second instruction table ( 12 b ) comprising at least the further instruction ( 13 f ); and executing at least one operation associated with the further instruction ( 13 f ) in the second logic unit ( 14 ).