Patent ID: 7928770

Claim:
A programmable device comprising: a programmable device core including programmable logic resources; and an I/O block coupled with the programmable device core, wherein the I/O block includes an I/O pin adapted to communicate a signal between the programmable device and an external device; wherein the I/O block comprises an input circuit coupled with the I/O pin and adapted to receive a double data rate input signal via the I/O pin from the external device, wherein the double data rate input signal includes an odd bit and an even bit in each cycle of a data strobe signal; wherein the input circuit comprises: a first set of registers coupled with the I/O pin and adapted to capture the double data rate input signal and to output a first single rate data signal corresponding with the odd bit of each cycle of the data strobe signal and a second single data rate signal corresponding with the even bit of each cycle of the data strobe signal, wherein the data strobe signal is synchronized with the external device; a second set of registers coupled with the first set of registers and adapted to receive the first and second single data rate signals from the first set of registers and to resynchronize the first and second single data rate signals with a full rate device clock signal to produce first and second resynchronized single data rate signals, wherein the full rate device clock signal is synchronized with the programmable device core; and first signal paths adapted to carry the first and second resynchronized single data rate signals, wherein the first signal paths are coupled to the second set of registers and first and second core connections that are coupled with the programmable device core.