Patent ID: RE44242

Claim:
A semiconductor memory comprising: a memory cell having first and second storage terminals storing information of logic levels complementary to each other; a power supply wiring supplying a predetermined power supply voltage to said memory cell; first and second pairs of bit lines each electrically connected to said first and second storage terminals of said memory cell, when selected; and first and second word lines connected to said memory cell, said first pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said first word line, and said second pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said second word line, wherein said first and second pairs of bit lines and said power supply wiring are provided in parallel to each other, with said power supply wiring interposed between said first and second pairs of bit lines.