Patent ID: 7870519

Claim:
A method, comprising: defining a set of signal path selection criteria; selecting a subset of signal paths that meet said selection criteria from a set of signal paths of an integrated circuit design; identifying pattern observation points for each signal path of said subset of signal paths; selecting a set of two or more features associated with signal paths of said integrated circuit design; for each signal path of said subset of signal paths, assigning a respective value to each feature of said set of features; applying a same set of test patterns that test said subset of signal paths to two or more integrated circuit chips, each integrated circuit chip of said two or more integrated circuit chips fabricated to said integrated circuit design, until at least two of said two or more integrated circuit chips fail; determining the failing signal paths of said subset of signal paths for each failing integrated circuit chip of said two or more integrated circuit chips; for each failing integrated circuit chip, mapping the failing signal paths and the observation point at which the failing signal paths were detected to corresponding features of said set of features to generate a fail table containing the failing paths of all said failing integrated circuit chips; and performing a statistical analysis of said fail table to determine suspect features that are characteristic of all said failing integrated circuit chips.