Patent ID: 8107279

Claim:
A semiconductor integrated circuit arranged inside a chip, the semiconductor integrated circuit comprising: an embedded SRAM including memory cells each having a pair of driver MOSs, a pair of load MOSs, and a pair of transfer MOSs; a control switch to supply PMOS and NMOS body bias voltages to wells of corresponding ones of said driver, load, and transfer MOSs; nonvolatile control memory storing therein, for each body bias voltage, control information indicative of whether the body bias voltage is supplied through the control switch in at least one active mode selected from the group consisting of an information holding operation, a write operation, and a read operation; sense circuitry which senses a leakage current characteristic of each of said MOSs; and a control unit, wherein the nonvolatile memory stores discrimination information regarding whether threshold voltage states of said MOSs are low or high, and wherein the control unit detects the leakage current characteristic by controlling a source voltage and a ground voltage of the embedded SRAM in order to measure individual threshold voltages of said MOSs.