Patent ID: 8476700

Claim:
A semiconductor device, comprising: a first region, a second region, and a third region separated from each other by an isolation region on a substrate; a recessed trench in the first region; a high voltage recess channel transistor comprising: a first gate insulating layer in the recessed trench, the first gate insulating layer having a first portion with a first thickness and a second portion with a second thickness greater than the first thickness, a high voltage recess gate electrode on the first gate insulating layer and filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the high voltage recess gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer; a low voltage planar channel transistor comprising: a second gate insulating layer on a surface of the second region of the substrate and having a third thickness smaller than the first thickness, a low voltage gate electrode on the second gate insulating layer, and a third impurity region at opposing sides of the low voltage gate electrode; and a high voltage planar channel transistor in the third region of the substrate.