Patent ID: 8230440

Claim:
A machine-implemented method comprising: identifying, by a utilization analyzer, a plurality of processor threads, wherein each processor thread corresponds to an accumulator and a processor utilization resource register, resulting in a plurality of accumulators and a plurality of processor utilization resource registers; identifying, by the utilization analyzer, from the plurality of accumulators, a quantity of accumulators included in a first combination of equal accumulators that each include a largest accumulator value, the first combination of equal accumulators corresponding to a first combination of processor utilization resource registers from the plurality of processor utilization resource registers; in response to determining that the quantity of accumulators included in the first combination of equal accumulators does not equal a power of two: selecting, by the utilization analyzer, a first subset of processor utilization resource registers from the first combination of processor utilization resource registers, the first subset of processor utilization resource registers omitting at least one processor utilization resource register from the first combination of processor utilization resource registers, wherein the omission of at least one of the processor utilization resource registers results in a quantity of processor utilization resource registers included in the first subset of processor utilization resource registers equaling a power of two; and distributing, by the utilization analyzer, processor utilization charges between the first subset of processor utilization resource registers; and in response to determining that the quantity of accumulators included in the first combination of equal accumulators equals a power of two, distributing, by the utilization analyzer, the processor utilization charges between the first combination of processor utilization resource registers.