Patent ID: 7622987

Claim:
A method for correcting one or more DC offsets in an amplifier, the method comprising: slicing an output signal of a gain stage of the amplifier to generate a 1-bit sliced signal, wherein symbols of the 1-bit sliced signal comprises a first state or a second state, wherein slicing is performed by electronic hardware; determining the presence of one or more patterns associated with DC offsets from the output signal of the gain stage of the amplifier by analyzing the 1-bit sliced signal for run length, wherein a run length comprises a count of consecutive runs of the first state or the second state, wherein a run length of at least a threshold value for the first state or the second state is associated with a positive DC offset or a negative DC offset, respectively; and generating a correction to reduce the DC offset based at least partly on a count of the run length of the first state or the second state.