Patent ID: 7996655

Claim:
A processor, comprising: at least one cascaded delayed execution pipeline unit having at least first second, and third pipelines that execute first, second, and third instructions, respectively, in a delayed manner relative to each other; at least first and second first-in first-out target delay queue (TDQs) in which results from the execution of instructions in the first and second pipelines are stored; priority logic configured to assign a priority to copies of source data for the third instruction based, at least in part, on the respective locations of the copies in the TDQs; and forwarding circuitry configured to: determine if the first and second TDQs each contain copies of source data for the third instruction; and if so: select one of the copies based on a respective priority assigned by the priority logic; and forward the selected copy of the source data from the target delay queue to an execution unit of the second or third pipeline, respectively.