Patent ID: 7673094

Claim:
A memory system comprising: a memory controller coupled to a first and a second bus switch, wherein: said memory controller provides a first chip select signal to said first bus switch and a second chip select signal to said second bus switch, said memory controller provides command address bus signals to said first and second bus switches, wherein said memory controller is synchronized, by sending said command address bus signals early relative to the first and second chip select signals, to compensate for propagation delay added to said command address bus signals by said first and second bus switches, and each of said first and second bus switches has an ON state and an OFF state, only one of said first and second switches being in the ON state at a time, wherein said first and second bus switches are selected to be in the ON state respectively by said first and second chip select signals; and a first dual in-line memory module coupled to said command address bus signals via said first switch and a second dual in-line memory module coupled to said command address bus signals via said second switch, wherein: when a respective one of said first and second switch is in the ON state, said respective one of said first and second switches provides the command address bus signals to a respective one of said first and second dual in-line memory modules, and when a respective one of said first and second switch is in the OFF state, said respective one of said first and second switches isolates the command address bus signals from a respective one of said first and second dual in-line memory modules.