Patent ID: 8774228

Claim:
A parallel input/output interface receiver, comprising: a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, the input data being non-calibration data for the n channels of the n+m channels and calibration data for the m channels of the n+m channels; a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time; and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time, wherein n is an integer greater than one, m is an integer greater than or equal to one, and a phase of the first clock signal provided by the first phase adjustor is prevented from being adjusted while a phase of the second clock signal provided by the second phase adjustor is permitted to be adjusted during a calibration process.