Patent ID: 7372155

Claim:
A semiconductor chip comprising: a silicon substrate; multiple semiconductor devices in or over said silicon substrate; a first dielectric layer over said silicon substrate; an interconnecting metallization structure over said first dielectric layer, wherein said interconnecting metallization structure is connected to said multiple semiconductor devices, and wherein said interconnecting metallization structure comprises multiple lower metal layers; a second dielectric layer between neighboring two of said multiple lower metal layers; a passivation layer over said first and second dielectric layers and over said interconnecting metallization structure, a first opening in said passivation layer exposing a first contact point of said interconnecting metallization structure, and a second opening in said passivation layer exposing a second contact point of said interconnecting metallization structure, wherein said first contact point is separate from said second contact point; an upper metallization structure over said passivation layer and over said first and second contact points, wherein a connecting portion of said upper metallization structure connects multiple portions of said interconnecting metallization structure through said first and second openings and through said first and second contact points, and wherein said upper metallization structure comprises multiple upper metal layers, wherein one of said multiple upper metal layers is thicker than each of said multiple lower metal layers; and a first polymer layer between neighboring two of said multiple upper metal layers, wherein said first polymer layer is thicker than each of said first and second dielectric layers.