Patent ID: 6985389

Claim:
A memory device, comprising: an array of memory cells arranged in row and columns, each memory cell comprising a select transistor and an electrically programmable resistive element coupled in series therewith, each column of memory cells being coupled to a bit line, each row of memory cells being coupled to a word line, the select transistor in each memory cell having a control terminal coupled to a corresponding word line; address circuitry for receiving an address value and driving a word line corresponding thereto to a voltage level to activate select transistors of memory cells coupled to the word line corresponding to the address value; a transistor coupled between a first bit line and a first reference voltage level; a reference cell coupled to the first bit line, comprising a select transistor and a resistive element coupled in series therewith, the reference cell, the transistor and an addressed memory cell in the column of memory cells coupled to the first bit line forming a differential amplifier circuit; and control circuitry having an output coupled to a control terminal of the transistor for activating the transistor during a memory read operation.