Patent ID: 7256112

Claim:
A method of fabrication of a bitline contact region for a memory device comprising the steps of: providing a substrate having a logic region and a memory region; providing in the logic region a logic transistor having silicide regions over logic S/D regions; providing in said memory region, a memory transistor comprised of a memory source region and a memory drain region and a memory source silicide region over said memory source region; forming an ILD dielectric layer over the substrate surface; forming a bitline contact opening in said ILD dielectric layer over the memory drain region in said memory region; forming a recess in the substrate in the memory region and into the memory drain region; performing a bitline contact region implant to form an unactivated bitline contact region under said recess; activating said unactivated bitline contact region to form an activated bitline contact region using a laser irradiation process.