Patent ID: 7060564

Claim:
A method of fabricating a memory device having a core region including an array of double-bit memory cells and a periphery region including associated logic circuitry, said method comprising: (a) providing a semiconductor substrate having a core area and a periphery area; (b) forming a multi-layer dielectric stack over the substrate in the core area and in the periphery area; (c) removing the multi-layer dielectric stack from the periphery area; (d) forming at least one gate dielectric layer over the substrate in the periphery area; (e) forming a first conductive layer over at least the periphery area; (f) implanting ion species into the core area of the semiconductor substrate; (g) performing a high temperature oxidation (HTO) step, said step being effective to (i) replace a top layer of the dielectric stack and (ii) activate implanted ion species to form buried bitlines in the core area; (h) removing HTO from the periphery area; and (i) forming a second conductive layer over the top layer of the dielectric stack in the core area and the first conductive layer in the periphery area.