Patent ID: 8541823

Claim:
A transistor, comprising: a doped well in a substrate, said doped well extending from a top surface of said substrate into said substrate a distance less than the thickness of said substrate; a gate dielectric layer on a top surface of said doped well region; a polysilicon gate electrode on a top surface of said gate dielectric layer; spacers formed on opposite sidewalls of said polysilicon gate electrode; source/drain extensions formed on opposite sides of said polysilicon gate electrode in said doped well region; source/drains formed on opposite sides of said polysilicon gate electrode in said doped well region; buried doped regions formed on opposite sides of said polysilicon gate electrode in said doped well region, said buried doped regions further from said polysilicon gate electrode than said source/drains and said source/drain extensions; a first doped region in said polysilicon gate electrode, said first doped region extending into said polysilicon gate electrode from a top surface of said polysilicon gate electrode; a second doped region in said polysilicon gate electrode, said second doped region abutting a bottom surface of said first doped region; a third doped region in said polysilicon gate electrode, said third doped region between said second doped region and said gate dielectric layer; a fourth region of said polysilicon gate electrode abutting said second doped region and abutting said third doped region; and a fifth region of said polysilicon gate electrode abutting third doped region and abutting said gate dielectric layer.