Patent ID: 8780600

Claim:
A stacked semiconductor package comprising: a package substrate; an integrated circuit die comprising a backside and an active side, wherein the backside of the memory controller is physically coupled to a first side of the package substrate, and wherein the active side of the integrated circuit die includes a plurality of bond pads and a plurality of flip-chip solder bumps; a die stack comprising a plurality of semiconductor dies, wherein: the plurality of semiconductor dies are physically coupled to one another; the plurality of semiconductor dies are electrically coupled to one another with a plurality of conductive epoxy traces; and the die stack is physically coupled to a second side of the package substrate, wherein the second side of the package substrate is opposite the first side of the package substrate; a plurality of electrically conductive vias extending from the first side of the package substrate, through the package substrate, to the second side of the package substrate, wherein: the plurality of electrically conductive vias are electrically coupled on the first side of the package substrate to the plurality of bond pads of the integrated circuit die; and the plurality of electrically conductive vias are electrically coupled on the second side of the package substrate to the die stack via the conductive epoxy traces.