Patent ID: 7151292

Claim:
A dual bit dielectric memory cell array comprising: a) a lightly doped substrate of P type conductivity; b) a plurality of parallel bit lines implanted to a bit line depth within the lightly doped substrate, each of the plurality of parallel bit lines of N type conductivity and defining a plurality of channel regions of P type conductivity spaced there between and each interface between a bit line and a channel region being a semiconductor junction; c) a charge trapping dielectric on the top surface of the substrate, the charge trapping dielectric including at least one charge trapping region disposed at least partially above each channel region and below a control gate corresponding to the channel region; and wherein d) each channel region comprising a central counter doped channel region of N type conductivity and extending from a top surface of the substrate into the channel region to a depth less than the bit line depth and being spaced from each semiconductor junction, wherein the counter doped channel region is spaced from each semiconductor junction by a pocket region of P type conductivity.