Patent ID: 8640076

Claim:
A method implemented on a computing device, comprising generating a model of effects of metal fill in an integrated circuit using a processor, wherein the metal fill model is generated prior to completion of any layout design for the integrated circuit, wherein: the generating the model of effects comprises: identifying at least one sub-cell having a plurality of metal fill shapes; modeling the at least one sub-cell in a capacitive and resistance network; determining effects of the at least one sub-cell; and extrapolating the model of the at least one sub-cell including the determined effects to encompass an open space between adjacent power transmission or signal lines within the integrated circuit that is to include the metal fill; the determined effects of the at least one sub-cell include an effective capacitance of the at least one sub-cell; and the extrapolated model provides a number of the at least one sub-cell placed within the open space between the adjacent power transmission or signal lines to provide an overall effective capacitance of the metal fill.