Patent ID: 7633570

Claim:
A liquid crystal display comprising: a plurality of data lines, each of the plurality of data lines being adapted to receive a corresponding data signal; a plurality of gate lines crossed with the plurality of data lines perpendicularly, each of the plurality of gate lines being adapted to receive a corresponding gate signal; a plurality of common lines for receiving a common voltage; a plurality of storage units, each of the plurality of storage units comprising: a first liquid crystal capacitor comprising a first end coupled to a corresponding common line of the plurality of common lines, and a second end; and a second liquid crystal capacitor comprising a first end coupled to the corresponding common line of the plurality of common lines, and a second end; a plurality of first switches, each of the plurality of first switches comprising: a first end coupled to the second end of a corresponding first liquid crystal capacitor of the plurality of first liquid crystal capacitors; a second end coupled to a corresponding data line of the plurality of data lines; a gate coupled to a corresponding gate line of the plurality of gate lines, wherein the first switch controls a signal connection between the first end and the second end of the first switch based on a gate signal furnished to the gate of the first switch via the corresponding gate line; and a first end capacitor coupled between the gate and the first end of the first switch; and a plurality of second switches, each of the plurality of second switches comprising: a first end coupled to the second end of a corresponding second liquid crystal capacitor of the plurality of second liquid crystal capacitors; a second end coupled to the first end of a corresponding first switch of the plurality of first switches; a gate coupled to a corresponding gate line of the plurality of gate lines, wherein the second switch controls a signal connection between the first end and the second end of the second switch based on a gate signal furnished to the gate of the second switch via the corresponding gate line; and a first end capacitor coupled between the gate and the first end of the second switch; wherein a capacitance of the first end capacitor of the first switch is greater than a capacitance of the first end capacitor of the second switch.