Patent ID: 7324317

Claim:
A microelectronic packaging structure, comprising: a dielectric layer; a plurality of terminals formed on the dielectric layer, the plurality of terminals including a first terminal and second terminals; a conductive portion coupled with the dielectric layer and arranged with respect to the first terminal to have an electrostatic discharge (ESD) breakdown path between the conductive portion and the first terminal when sufficient charges accumulate in the first terminal, a length of the breakdown path smaller than a distance between the first terminal and an closest adjacent terminal of the first terminal; a solder resist layer formed over the plurality of terminals, the solder resist layer having a first openings to expose the plurality of terminals for connection, the solder resist layer having a second opening to expose the conductive portion, the breakdown path to go through the second opening; and wherein the solder resist layer further has a third opening to expose a further portion of the first terminal, the breakdown path to go through both the second and third openings.