Patent ID: 7279668

Claim:
A sequential read-out circuit comprising: a first sample and hold circuit that includes a first sampling switch and a first sampling capacitor, the first sampling capacitor having a first and a second electrode; a first photocell in an array of photocells, the first photocell comprising a first read switch and a first photodiode, the first read switch being operable to couple the first photodiode to the first electrode of the first sampling capacitor; and an amplifier having a positive input terminal coupled to a reference voltage, the amplifier configured for operation in one of a unity gain mode and a charge transfer mode, wherein when operating in the unity gain mode, the first sampling switch is operable to couple the second electrode of the first sampling capacitor to a negative input terminal of the amplifier, thereby placing the second electrode of the first sampling capacitor at a voltage level equal to the reference voltage; a second sample and hold circuit that includes a second sampling switch and a second sampling capacitor, the second sampling capacitor having a first and a second electrode; a second photocell in an array of photocells, the second photocell comprising a second read switch and a second photodiode, the second read switch being operable to couple the second photodiode to the first electrode of the second sampling capacitor; and wherein the first sampling switch is operable to uncouple the second electrode of the first sampling capacitor from the negative input terminal of the amplifier and the second sampling switch is operable to couple the second electrode of the second sampling capacitor to the negative input terminal of the amplifier, thereby placing the second electrode of the second sampling capacitor at the reference voltage.