Patent ID: 8072258

Claim:
A booster circuit comprising: boosting cells arranged in M parallel lines (Mâ‰§4) and L stages (Lâ‰§2) and configured to perform boosting operation in synchronization with a plurality of clock signals having different phases, wherein each of the boosting cells includes a first boosting capacitor having two ends, one of the two ends being connected to an output terminal of the each boosting cell, and a clock signal corresponding to the each boosting cell being received at the other end, a first charge transfer transistor connected between an input terminal and the output terminal of the each boosting cell, and a first state controller configured to control the first charge transfer transistor, the first state controller includes a first transistor having a first conductivity type and a second transistor having a second conductivity type, the drains of the first and second transistors being connected to a gate of the first charge transfer transistor, and the input terminal of one of the boosting cells located in the same stage as that of the each boosting cell and in a first one of the lines other than the line of the each boosting cell, is connected to a control terminal of the first state controller for controlling a conductive state and a non-conductive state of the first charge transfer transistor, and the control terminal is connected to gates of the first and second transistors, whereby the M boosting cells in the same stage are connected in a ring shape.