Patent ID: 8604475

Claim:
An integrated circuit wafer comprising: A. a first die including: i. first core circuitry having inputs and outputs; ii. first bond pads; iii. first input buffers, each first input buffer having an input connected to one of the first bond pads and having an output connected to a separate input of the first core circuitry; and iv. first test circuits, each first test circuit having a data input connected to one output of the core circuitry, an expected data input connected to a separate one of the first bond pads, a mask data input connected to a separate one of the first bond pads, and the data input being selectively coupled to one of the expected data input and the mask data input as an output; and B. a second die including: i. second core circuitry having inputs and outputs; ii. second bond pads; iii. second input buffers, each second input buffer having an input connected to one of the second bond pads and having an output connected to a separate input of the second core circuitry; and iv. second test circuits, each second test circuit having a data input connected to one output of the core circuitry, an expected data input connected to a separate one of the second bond pads, a mask data input connected to a separate one of the second bond pads, and the data input being selectively coupled to one of the expected data input and the mask data input as an output.