Patent ID: 7750693

Claim:
A frequency divider comprising: a first latch circuit; and a second latch circuit coupled to said first latch circuit, wherein each of said first latch circuit and said second latch circuit comprises: a first level for generating a source current, said first level comprising a first transistor having a source terminal and a substrate both coupled to a source voltage: a second level for receiving a pair of input signals and for generating a pair of output signals, wherein said second level comprises a first sub-circuit and a second sub-circuit coupled in parallel, wherein said first sub-circuit comprises a pair of source-coupled transistors for receiving said pair of input signals, wherein said second sub-circuit comprises a pair of cross-coupled transistors for generating said pair of output signals, and wherein drain terminals of said pair of source-coupled transistors are coupled to a drain terminal of said first transistor from said first level; and a third level for receiving said source current and a pair of clock signals, said third level comprising a plurality of transistors controlled by said pair of clock signal, wherein each transistor of said plurality of transistors has a source terminal and a substrate both coupled to ground, and wherein said second level is coupled between said first level and said third level.