Patent ID: 7405112

Claim:
A method for fabricating a CMOS integrated circuit having an N-type drain region and a P-type drain region, the method comprising the steps of: depositing a high barrier height silicide forming metal in contact with the P-type drain region; heating the high barrier height silicide forming metal to form a high barrier height metal silicide in contact with the P-type drain region; depositing a low barrier height silicide forming metal in contact with the N-type drain region; heating the low barrier height silicide forming metal to form a low barrier height metal silicide in contact with the N-type drain region; depositing and patterning a dielectric layer to form a first opening exposing a portion of the high barrier height metal silicide and a second opening exposing a portion of the low barrier height metal silicide; depositing a low barrier height metal into the second opening and contacting the portion of the low barrier height metal silicide; depositing a high barrier height metal into the first opening and contacting the portion of the high barrier height metal silicide; depositing a conductive capping layer in contact with the high barrier height metal and in contact with the low barrier height metal; and filling the first opening and the second opening with a plug metal in contact with the conductive capping layer.