Patent ID: 8310853

Claim:
A layout structure of bit line sense amplifiers for use in a semiconductor memory device, the layout structure comprising: first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors; wherein: each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier, the respective active regions of the transistors of each of the first and second bit line sense amplifier are at least partially aligned along a first direction, the respective active regions of the first bit line sense amplifier defining a first row and the respective active regions of the second bit line sense amplifier defining a second row, and at least one transistor of the first and second bit line sense amplifiers, and at least one transistor of a third bit line sense amplifier, controlled by a second column selection line signal different from the first column selection line signal, share a portion of an active region.