Patent ID: 8909690

Claim:
An apparatus, comprising: hardware logic configured to receive a plurality of floating point operands of a floating point arithmetic operation; hardware logic configured to shift bits in a mantissa of at least one floating point operand of the plurality of floating point operands; hardware logic configured to store one or more bits of the mantissa that are shifted outside a range of bits of the mantissa of the at least one floating point operand; hardware logic configured to generate a vector value based on the stored one or more bits of the mantissa that are shifted outside the range of bits of the mantissa of the at least one floating point operand; and hardware logic configured to generate a resultant value for the floating point arithmetic operation based on the vector value and the plurality of floating point operands, wherein: the hardware logic configured to store one or more bits of the mantissa that are shifted outside a range of bits of the mantissa of the at least one floating point operand comprises hardware logic configured to set bits in bit positions of a separate register corresponding to the one or more bits of the mantissa shifted outside of the range of hits of the mantissa, each bit position in the separate register has a different associated probability weight, and the hardware logic configured to generate the vector value based on the stored one or more bits of the mantissa that are shifted outside the range of bits of the mantissa of the at least one floating point operand comprises hardware logic configured to generate the vector value based on probability weights associated with bit positions having corresponding hit values set in the separate register.