Patent ID: 6868001

Claim:
A semiconductor memory device, comprising: a first inverter consisting of a first PMOS transistor and a first NMOS transistor; a second inverter consisting of a second PMOS transistor and a second NMOS transistor, an input terminal thereof being connected with an output terminal of the first inverter and an output terminal thereof being connected with an input terminal of the first inverter; a third NMOS transistor connected with the output terminal of the first inverter; and a fourth NMOS transistor connected with the output terminal of the second inverter, wherein first and second P well regions are formed on opposite adjacent sides of an N well region, the first PMOS transistor and the second PMOS transistor are formed in the N well region in which a P+ diffused region is formed by injecting a P-type impurity, the first NMOS transistor and the third NMOS transistor are formed in the first P well region, and the second NMOS transistor and the fourth NMOS transistor are formed in the second P well region, and wherein a first word line is wired to the third NMOS transistor, and a second word line is wired to the fourth NMOS transistor and wherein a first wiring connecting the output terminal of the first inverter with the input terminal of the second inverter, and a second wiring connecting the input terminal of the first inverter with the output terminal of the second inverter are wired in the same wiring layer, and the first word line and the second word line are placed in the same direction.