Patent ID: 7200137

Claim:
A network that maximizes interconnect utilization between a plurality of processing elements, comprising: a plurality of ports; an interconnect that includes selectable data paths to transfer a packet between any two ports; a plurality of port interfaces, each coupled to a corresponding port and each communicating using packets and to provide a network transaction request via the corresponding port to request sending a packet to a destination port; each network transaction request including a destination address and a transaction size; and an arbiter, coupled to the interconnect and the plurality of ports, that controls packet transfer between the ports in such a manner as to maximize efficiency and minimize latency through the interconnect; wherein the arbiter arbitrates among network transaction requests and provides acknowledgements, controls the interconnect to enable a data path from a source port to a destination port for each acknowledged network transaction, and uses arbitration latency, data path latency and transaction size while tracking packet transfer progress to synchronize network transactions to minimize dead cycles in the interconnect.