Patent ID: 8661424

Claim:
A code generation system, the system comprising: a memory configured to store model analyzer instructions, model partitioner instructions, and code generator instructions; a processing unit configured to execute the model analyzer instructions to implement a model analyzer, to execute the model partitioner instructions to implement a model partitioner, and to execute the code generator instructions to implement a code generator; and at least one user input element configured to provide data received from a user to the processing unit; wherein the model analyzer is configured to identify data dependencies in a non-executable data flow diagram that describes functional behavior of an application, wherein the model analyzer is further configured to compute a data and computation map based on the data dependencies and to compute one or more implementation constraints; wherein the data flow diagram comprises a plurality of functional blocks and the data and computation map depicts data inputs/outputs of and computations performed by each of the functional blocks without explicit reference to the corresponding functional blocks; wherein the model partitioner is configured to compute one or more partition boundaries based on the data and computation map and the one or more implementation constraints; and wherein the code generator is configured to generate executable parallelized code based on the data flow diagram, the one or more implementation constraints, and the one or more partition boundaries, wherein the code generator is configured to map the code corresponding to each partition defined by the one or more partition boundaries to one of a plurality of cores of a multi-core processor, and to generate inter-core communication code for at least one line of the data and computation map crossed by the one or more partition boundaries.