Patent ID: 7135372

Claim:
A method of forming a p-channel transistor on a silicon substrate, comprising: forming a poly gate structure over the substrate; forming a lightly doped source/drain region in the substrate; forming an oxide liner adjacent to opposing side walls of the poly gate structure; forming a wide spacer on opposing side walls of the oxide liner; etching a recess in the lightly doped source/drain region of the semiconductor substrate on opposing sides of the wide spacer; forming raised SiGe source/drain regions in the recesses; partially etching the wide spacer subsequent to forming the raised SiGe source/drain regions to form a slim spacer on opposing side walls of the oxide liner; implanting a source/drain dopant into the substrate including the SiGe source/drain regions; and providing a silicide region in the implanted SiGe source/drain regions.