Patent ID: 8893103

Claim:
A method for automating asynchronous offload to many-core coprocessors, comprising: splitting, by a processor, a parallelizable loop in an input source code into a sampling sub-loop, a many integrated core (MIC) sub-loop, and a central processing unit (CPU) sub-loop; executing, by the processor, the sampling sub-loop to determine loop characteristics including memory-operations and processor-operations executed by the parallelizable loop; identifying, by the processor, optimal split boundaries based on the loop characteristics such that the MIC sub-loop will complete in a same amount of time when executed on a MIC processor as the CPU sub-loop will take when executed on a CPU; and modifying, by the processor, the input source code to split the parallelizable loop at the identified optimal split boundaries, such that the MIC sub-loop is executed on a MIC processor and the CPU sub-loop is concurrently executed on a CPU.