Patent ID: 8008136

Claim:
A method of manufacturing a semiconductor device, comprising: forming source and drain regions in a first silicon layer of the semiconductor device; forming a fin structure, the fin structure including first and second side surfaces; forming a first dielectric layer on the first and second side surfaces of the fin structure; forming a protective layer on a top surface of the fin structure; depositing a second silicon layer over the fin structure; etching the second silicon layer to form at least one gate electrode; performing a first silicide process to convert a portion of the first and second silicon layers into a metal-silicide compound that ranges in thickness from 50 Å to 700 Å; and depositing, after performing the first silicide process, a second dielectric layer over the device; planarizing the second dielectric layer to expose the metal-silicide compound of the gate electrode, without exposing the source and drain regions; performing a second silicide process to convert a remaining portion of the second silicon layer into the metal-silicide compound to form a fully-silicided gate electrode, where performing the second silicide process includes depositing a metal layer over the metal-silicide compound, of the gate electrode, that results from performing the first silicide process, where the protective layer protects the fin structure from the second silicide process, where the second silicide process is separate from the first silicide process, and where the fully-silicided gate electrode causes stress on the fin structure to enhance mobility in the fin structure.