Patent ID: 7698673

Claim:
A method for fabricating a circuit, comprising: fabricating a single stage network comprising a pull-down network that is configured to perform a desired logic function according to a plurality of inputs; and fabricating a multi-stage network that includes at least two stages, each of the at least two stages including a pull-down network that receives a respective portion of the plurality of inputs and each of the at least two stages cooperating to perform the desired logic function according to the plurality of inputs, wherein the single stage network includes a pull-up network to substantially compensate for leakage of current associated with the pull-down network of the single stage network; and fabricating a pull-up network to substantially compensate for leakage associated with the pull-down network of a first stage of the at least two stages, such that a ratio of size for the pull-up network of at least the first stage to size of the pull-down network of at least the first stage is reduced relative to a ratio of size for the pull-up network of the single stage network to size of the pull-down network of the single stage network.