Patent ID: 7679428

Claim:
A comparator comprising: first and second power source terminals; a first variable resistor which is connected to the first power source terminal at one end, and a resistance value of which changes according to voltages of a positive phase input signal and a negative phase reference signal; a second variable resistor which is connected to the first power source terminal at one end, and a resistance value of which changes according to voltages of a negative phase input signal and a positive phase reference signal; a first inverter which is inserted between the second power source terminal and other end of the first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal; a second inverter which is inserted between the second power source terminal and other end of the second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal; and a first switch and a second switch which reset the output voltages of the first inverter and the second inverter to a voltage of the first or the second power source terminal when the clock signal is at the first level.