Patent ID: 7030026

Claim:
A method for fabricating a semiconductor device comprising: the step of forming gate electrodes respectively in a first element region and in a second element region which are formed over a semiconductor substrate, with a gate insulation film formed therebetween; the step of forming a first resist film over the semiconductor substrate and the gate electrodes, the first resist film being opened in the first element region; the step of implanting a dopant in the first element region with the first resist film and the gate electrodes as a mask to form a first dopant diffused region; the first ashing processing step of ashing the first resist film; the step of forming a sidewall insulation film over the side wall of the gate electrode; the step of forming a second resist film over the semiconductor substrate, the gate electrode and the sidewall insulation film, the second resist film being opened in the second element region; the step of implanting a dopant in the first element region with the second resist film, the gate electrode and the sidewall insulation film as a mask to form a second dopant diffused region; and the second ashing processing step of ashing the second resist film, an ashing processing period of time in the first ashing processing step being shorter than an ashing processing period of time in the second ashing processing step.