Patent ID: 6904556

Claim:
A memory system, comprising: a plurality of memory boards, each of the memory boards having a respective plurality of memory segments that may store respective data values, the segments being grouped into parity sets such that each of the parity sets includes respective segments of number N, the number N being an integer, the N respective segments in each respective parity set including a respective parity segment and N- 1 respective data segments, the N respective segments in each respective parity set being distributed among the memory boards such that none of the memory boards has more than one respective segment from each respective parity set, and a respective data value stored in a respective parity segment in at least one parity set may be calculated by a logical exclusive-or of respective data values stored in respective data segments in the at least one parity set, wherein: each memory board includes a respective plurality of memory regions, each memory region includes a respective subset of the segments included in a respective memory board, and each of the segments included in a respective memory region may be assigned a respective base memory address different from other respective base memory addresses that may be assigned to other segments included in the respective memory region.