Patent ID: 8492831

Claim:
A vertical non-volatile memory device comprising: a substrate; a plurality of groups of memory cell strings on the substrate, each of the memory cell strings comprising a plurality of memory transistors distributed in a vertical direction, substantially perpendicular to the plane of the substrate, such that each of the memory cell strings extends vertically on the substrate, and a respective array of the memory transistors is disposed on each of several layers above the substrate; stacks of integrated word lines on the substrate, the integrated word lines being coupled to sets of the memory transistors, respectively, the memory transistors of each of said sets being those memory transistors which constitute a respective one only of the groups of the memory cell strings and which are disposed within the same layer above the substrate, wherein for each array of memory transistors on a respective layer above the substrate, there are a plurality of integrated word lines electrically isolated from each other in the layer and connected to sets of the memory transistors, respectively; and a stack of layers each of which has a plurality of coplanar word select lines on the substrate, wherein plural ones of the coplanar word select lines in each of the layers of the stack are connected to plural ones of the integrated word lines, respectively, constituting a respective one of the stacks of integrated word lines.