Patent ID: 8183926

Claim:
An output stage of an electronic circuit comprising: a first branch, coupled between first and second terminals across which is applied a D.C. voltage, comprising a series connection of a first N-channel MOS transistor and a first P-channel MOS transistor, the node between the first N-channel and P-channel MOS transistors being connected to an input terminal, the first N-channel MOS transistor being coupled to the first terminal by a first constant current source, the first P-channel MOS transistor being coupled to the second terminal by a second constant current source, the first N-channel and P-channel MOS transistors being diode-connected; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected to form a current mirror with the first N-channel MOS transistor and of a second P-channel MOS transistor connected to form a current mirror with the first P-channel transistor; and an output terminal connected between the second N-channel and P-channel transistors.