Patent ID: 7929654

Claim:
A circuit for recovering clock and data signals from an NRZ digital input signal carried in a digital communications system, the input signal having a data rate, and the circuit comprising: a clock means for generating a recovered clock signal having a recovered clock frequency synchronized to said data rate; initialization means for setting a delay select code signifying a delay interval of one of an intermediate, early, or late delay interval, said initialization means setting said delay select code to a preselected one of said delay intervals at the startup of said circuit; a data sampling bank receiving said NRZ digital input signal and triggered by said recovered clock, the bank comprising: i. early, intermediate, and late signal channels; ii. an intermediate delay means for delaying said NRZ digital input signal by said intermediate delay interval to form an intermediate delayed signal in said intermediate signal channel; iii. an early delay means for delaying said NRZ digital input signal by said early delay interval to form an early delayed signal in said early signal channel, said early delay interval being less than said intermediate delay interval; and iv. a late delay means for delaying said NRZ digital input signal by said late delay interval to form an late delayed signal in said late signal channel, said late delay interval being greater than said intermediate delay interval; a pattern detection means for detecting occurrences of a preselected bit pattern in said intermediate delayed signal, said preselected bit pattern consisting of a sequence of a preselected initial bit, a preselected multi-bit timing indication pattern having an indication number of bits, and a preselected final bit, and said pattern detection means generating a select pulse in response to each detection of said preselected bit pattern; a selection means connected to said pattern detection means and said data sampling bank, and operative in response to each receipt of said select pulse to update said delay select code; a multiplexer receiving said delay select code from said selection means and signals from said data sampling bank in said early, intermediate, and late signal channels, said multiplexer outputting an optimum delayed signal chosen from the signals in said early, intermediate, and late signal channels, according to said delay select code; and an output flip-flop receiving said optimum delayed signal from said multiplexer and being clocked by said recovered clock signal, said output flip-flop thereby forming said recovered data signal in synchrony with said recovered clock signal; and wherein said updating of said delay select code preserves said preselected bit pattern in said recovered data signal.