Patent ID: 8209519

Claim:
A pipeline processor having a first stage to read data from a general purpose register unit, a second stage to execute instruction, and a third stage to write back the data into the general purpose register unit, the pipeline processor comprising: a first pipeline register to retain data obtained by executing the second stage, and to allow the data to be written back into the general purpose register unit, the first pipeline register being provided between the second stage and the third stage, the first pipeline register including a first area to store a data validity flag indicating validity of the retained data; a first WRITE suspension unit to suspend execution of writing the data retained in the first pipeline register into a general purpose register of the general purpose register unit, until the data retained in the first pipeline register is rewritten by a subsequent instruction, even if the data validity flag indicates “valid;” and a data invalidation unit to cancel the execution of writing the data retained in the first pipeline register into the general purpose register into which the data is to be written by a preceding instruction and to invalidate the data retained in the first pipeline register, when data is written into the general purpose register by the subsequent instruction.