Patent ID: 8111573

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a first sub-bank having a plurality of nonvolatile memory cells arranged in a form of a matrix in which first terminals of the memory cells on a same row are connected to a common word line, and second terminals of the memory cells on a same column are connected to a common bit line, and a second sub-bank having a same configuration as that of the first sub-bank; a row decoder shared by the first sub-bank and the second sub-bank and arranged to apply a voltage to corresponding word lines in the first sub-bank and the second sub-bank at a same time; a first column decoder arranged to apply a voltage to the bit line of the first sub-bank; a second column decoder arranged to apply a voltage to the bit line of the second sub-bank; and a control circuit arranged to control a programming action, a programming verifying action, a re-programming action for the memory cell determined such that the programming action has not been normally performed in the programming verifying action, the programming verifying action for the re-programming action, an erasing action, an erasing verifying action, a re-erasing action for the memory cell determined such that the erasing action has not been normally performed in the erasing verifying action, and the erasing verifying action for the re-erasing action, in the memory cell array, wherein the control circuit performs the programming action to the first sub-bank and a reading action for the programming verifying action to the second sub-bank in a first action cycle and performs the reading action for the programming verifying action to the first sub-bank and the programming action to the second sub-bank in a second action cycle, and the control circuit executes the first action cycle and the second action cycle alternately.