Patent ID: 7383419

Claim:
A processor including: a memory port for accessing a physical memory under control of an address; at least one processing unit for executing instructions stored in the memory and/or operating on data stored in the memory; at least one address generation unit (hereinafter “AGU”) for generating an address for controlling access to the memory; the AGU being associated with at least a first set of a plurality of N registers that are used for address generation, where the set of registers enables the AGU to generate the address under control of an address generation mechanism; and a memory unit operative to save/load k of the N registers that are used for address generation, where 2<=k<=N, triggered by one operation, where the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.