Patent ID: 7716618

Claim:
A method for designing a complex integrated electronic circuit architecture including a plurality of circuit portions integrated into a single chip structure, the method comprising the following steps of: a) providing, using a computer system, at least one library of cells, the cells in each library having associated variable channel lengths; b) creating a layout of an integrated circuit using the cells from at least one library, each cell having an initial channel length L; c) performing a timing analysis of the integrated circuit to analyze more and less critical paths by evaluating respective path delays; d) selecting a set of less critical paths to be modified; e) evaluating the leakage currents of the less critical paths of said selected set; and f) modifying the initial channel lengths L of at least some of the cells, each of the cells having its channel length modified being involved in at least one of said less critical paths of said selected set on the basis of the corresponding evaluated leakage current and the respective path delays, whereby a modified integrated circuit with a reduced circuit leakage current is obtained.