Patent ID: 7954025

Claim:
A integrated circuit that supports scan chain based testing of combinational logic within the integrated circuit, the integrated circuit comprising: a plurality of combinational logic circuits, each combinational logic circuit comprising: a plurality of input data lines; a plurality of output data lines; and a plurality of interconnected logic elements configured to receive a binary input data value on each of the plurality of input data lines, to process the received binary input data values based on the interconnected logic elements, and to produce a binary output data value on each of the plurality of output data lines; at least one input latch array, wherein each input latch in the at least one input latch array controls passage of a binary input data value to one of the plurality of input data lines of one of the plurality of combinational logic circuits; a plurality of scan latches, each scan latch comprising: a passthrough switch that controls passage of a binary output data value received on one of the plurality of output lines and that opens and closes based on a value of a first slave phase clock signal; and a scanning control circuit that passes one of a scan test input data value and a scan test output data value based on a value of a scan clock signal; and an output storage circuit that receives one of a data value from the passthrough switch and a data value from the scan control circuit, wherein a first output port of an output storage circuit of a first scan latch is connected to an input port of the scanning control circuit of a second scan latch for passing an output data value stored by the output storage circuit to the input port of the scanning control circuit, and a second output port of the output storage circuit is connected to a next plurality of combinational logic circuits, and wherein the output storage circuit includes a first transistor that opens and closes based on a value of the scan clock signal and a second transistor that opens and closes based on an inverted value of the slave phase clock signal, and wherein a connection between the output storage circuit and a low signal source is open when one of the first transistor and the second transistor is open.