Patent ID: 7958410

Claim:
A memory chip, comprising: a receiver configured to receive a test signal having a plurality of random data bits; a clock phase shifter configured to shift a phase of a clock signal having a plurality of phases first through nth phases (n is a natural number); an error detector configured to determine whether a data bit of the plurality of random data bits sampled in synchronization with the clock signal has an error; a controller configured to control the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit has an error; a counter configured to count data bits when the error detector determines the data bit has no error, wherein the controller is configured to control the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when one of the plurality of random data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error.