Patent ID: 7444573

Claim:
An integrated circuit comprising: a plurality of operational circuits to be tested; a test read only memory storing at least one test set consisting of a test algorithm and test data; an external tester interface; and a programmable built-in self test unit connected to said plurality of operational circuits to be tested, said test read only memory and said external tester interface, said programmable built-is self test unit including a plurality of read and write read and write data registers, a pointer register storing a pointer indicating one of said plurality of read and write read and write data registers, an adder having a first input connected to said pointer register, a second input receiving data equal to +1 and an output connected to said pointer register; and wherein said programmable built-in self test unit is operable to load from said test read only memory operable for each test set stored in said test read only memory said test algorithm and said test data, test at least one of said plurality of operational circuits to be tested according to said test algorithm and said test data loaded, enable access to said data registers indicated by said pointer register and increment said pointer register by said adder when in a tester access mode.