Patent ID: 8243737

Claim:
A first-in, first-out (FIFO) buffer system for packet switching in a crossbar switch with a speedup factor of m, where m is an integer greater than one, the FIFO buffer system comprising: a plurality of staging registers configured to receive corresponding N-bit portions of data in packets; a plurality of one-port memory banks, each having width W and each being segmented into S portions each having a width W/S; a first logic module having its input coupled to each of the plurality of staging registers and its output coupled to each of the one-port memory banks, the first logic module configured to receive i) the N-bit portions of data in and ii) the outputs of the plurality of staging registers; a second logic module coupled to the plurality of one-port memory banks configured to construct data out read from the plurality of one-port memory banks; and an arbitration and control module adapted to provide one or more control signals; wherein i) the N-bit portions of the data in are stored into corresponding ones of the plurality of staging registers, ii) the first logic module receives a corresponding control signal from the arbitration and control module to select at least one of a) an N-bit portion of the data in and b) one or more of the outputs of the plurality of staging registers, and iii) the second logic module constructs the data out read from the plurality of one-port memory banks in accordance with a second control signal, and wherein in a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a corresponding one segment of the plurality of one-port memory banks in a round-robin fashion, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.