Patent ID: 7230846

Claim:
A memory array comprising: a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a transistor having a floating body capable of storing a charge and a second transistor connected to the floating body transistor; a plurality of first word lines to provide driving signals to the memory cells, wherein each first word line interconnects to a row of the memory cells; a plurality of second word lines to provide driving signals to the memory cells, wherein each second word line interconnects to a row of the second transistors within the memory cells wherein the purge line is activated to iniate a purge; a plurality of purge lines to provide driving signals to the memory cells, wherein each purge line interconnects to a row of the memory cells; and a plurality of bit lines to provide driving signals to the memory cells, wherein each bit line interconnects to a column of the memory cells, and wherein the driving signals provided on the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.