Patent ID: 8533424

Claim:
A computing system comprises: a computing core that includes: a processing module; main memory; and a memory controller coupled to the processing module and to the main memory; and a plurality of memory components operably coupled to the computing core, wherein the memory controller is operable to: receive a memory access request regarding a data segment; interpret the memory access request to determine whether an error encoding dispersal function of the data segment is applicable; when the error encoding dispersal function is applicable: identify at least a threshold number of memories based on the memory access request, wherein memories of the threshold number of memories includes at least one of: the main memory; and one or more of the plurality of memory components; and address the at least a threshold number of memories to facilitate the memory access request when the error encoding dispersal function is not applicable: identify one of the memories; and address the one of the memories to facilitate the memory access request.