Patent ID: 8352780

Claim:
A method for dealing with write errors when writing information data into two or more flash memory devices, wherein the two or more flash memory devices are assigned to a common data bus and in a bus write cycle the two or more flash memory devices are sequentially fed with said information data for storage therein, said method comprising the steps: in a current bus write cycle, at least one of said two or more flash memory devices is not fed for storage with a current section of said information data; at least in case an error is occurring while writing a current section of said information data into a page of a current one of said flash memory devices, writing said current section of said information data into a non-flash memory; during the following bus write cycle, while a current flash memory device containing that defective page is normally idle and said writing of said information data into other flash memory devices is ongoing, using that idle time period for copying a corresponding stored section of said information data from said non-flash memory to an assumed save or non-defect page of the current flash memory device.