Patent ID: 7805547

Claim:
A process for the transmission of data between a processor and a mass memory unit, the process comprising: providing a processor; providing a mass memory unit; providing a peripheral component microchannel interconnect architecture (PCMCIA) interface operatively connected between the processor and the mass memory unit; providing a memory interface operatively connected between the processor and the mass memory unit; transmitting initialization and control commands from the processor to the mass memory unit exclusively via the PCMCIA interface; providing a common data bus connected to said mass memory unit and a multiplexer connected to said PCMCIA interface, said memory interface and said mass memory unit; transmitting user data from the processor to the mass memory unit exclusively via the memory interface; providing a driver, wherein a first transmission path is defined from said processor to said mass memory unit via said PCMCIA interface and a second transmission path is defined from said processor to said mass memory unit via said memory interface, said initialization and control commands being transmitted via said first transmission path, said user data being transmitted via said second transmission path; and switching over from one of said first transmission path and said second transmission path to another one of said first transmission path and said second transmission path via said driver.