Patent ID: 7682992

Claim:
A method of forming a resistance variable memory device, comprising: providing a substrate; forming a conductive address line over said substrate; forming a first insulating layer over said address line and said substrate; forming an opening in said first insulating layer to expose a portion of said address line in said opening; forming a first electrode layer in said opening and over said address line; forming a Sb 2 Se 3 glass layer over said first electrode; forming a metal-chalcogenide layer comprising tin-selenide over said Sb 2 Se 3 glass layer; forming a first chalcogenide glass layer over said metal-chalcogenide layer; forming a metal layer over said first chalcogenide glass layer; forming a second chalcogenide glass layer over said metal layer; forming a second electrode layer over said second chalcogenide glass layer; and etching to form a stack of said Sb 2 Se 3 glass layer, said metal-chalcogenide layer, said first chalcogenide glass layer, said metal layer, said second chalcogenide glass layer, and said second electrode layer over said first electrode layer.