Patent ID: 8319780

Claim:
An apparatus, comprising: a first graphics processor for: encrypting video data, writing the encrypted video data in an encrypted region of a system memory, and in response to writing the encrypted video data in the encrypted region of the system memory, writing a first value to a first semaphore; a second graphics processor in communication with the first graphics processor via a bus, the second graphics processor for: identifying the first value of the first semaphore, retrieving the encrypted video data in response to the identification of the first value of the first semaphore, processing the encrypted video data to decrypt the video data, writing the decrypted video data in an unencrypted region of the system memory, and in response to writing the decrypted video data in the unencrypted region of the system memory, writing a second value to a second semaphore; and a data structure storing the first semaphore for use in synchronizing operation of the first graphics processor and the second graphics processor in order to secure communication therebetween; wherein the system memory includes at least a first buffer and a second buffer, wherein the first graphics processor writes the encrypted video data to the first buffer of the system memory, and the second graphics processor reads previously encrypted video data from the second buffer of the system memory while the first graphics processor writes the encrypted video data to the first buffer of the system memory.