Patent ID: 7618868

Claim:
A method of manufacturing a semiconductor integrated circuit device, the method comprising: providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked structure of a second gate insulating layer and a second gate; forming a blocking layer in the first transistor region; then conformally forming a second oxide layer on lateral surfaces of the second gate insulating layer and the second gate and on an exposed surface of the semiconductor substrate by performing oxidation on the second transistor region using the blocking layer as an oxidation mask to prevent oxidation of the first transistor region, then; removing the blocking layer of the first transistor region; then forming a pre-spacer layer on the entire surface of the semiconductor substrate; forming a first spacer by anisotropically etching the pre-spacer layer of the first transistor region and forming a second spacer by anisotropically etching the second oxide layer and the pre-spacer layer of the second transistor region; and forming source/drain regions in the semiconductor substrate to complete a first transistor and a second transistor.