Patent ID: 8873181

Claim:
A system comprising: a detection module configured to (i) sample a signal generated by a sensor to generate a digital signal, (ii) based on the digital signal, detect a pattern of a first plurality of bit islands on media, and (iii) based on the pattern of the first plurality of bit islands, determine a phase error of the digital signal; an adjustment module configured to (i) receive a first clock signal, and (ii) generate a second clock signal based on the phase error and the first clock signal, wherein the second clock signal is synchronized with start times or end times of the first plurality of bit islands; and a phase shifter module configured to, based on a predetermined value of a phase shift, adjust a phase of the second clock signal, wherein the detection module is configured to sample the signal generated by the sensor based on the second clock signal with the adjusted phase; and a write module configured to, based on the second clock signal prior to being phase adjusted, write data to the first plurality of bit islands or a second plurality of bit islands.