Patent ID: 7288786

Claim:
An integrated circuit configuration, comprising: a substrate formed with circuit elements; at least one wiring plane formed with first interconnects connecting said circuit elements and disposed to leave free spaces in said wiring plane; second interconnects for protection of the integrated circuit configuration against attacking analysis formed in said wiring plane and filling said free spaces in said wiring plane left free by said first interconnects, said second interconnects having a similar structure and appearance to said first interconnects in order to achieve a desired disguise, said second interconnects being formed as passive and voltaqeless interconnects, said second interconnects being lattice-shaped or meander-shaped; further elements connected to said second interconnects, said further elements not belonging to said circuit elements; and a driving circuit and an evaluation circuit connected to said second interconnects, for detecting one of an interruption of said second interconnects, a short circuit of one of said second interconnects with a further interconnect, or a bypass of said second interconnects.