Patent ID: 8045938

Claim:
A discrete filter comprising: a control signal generator that generates a plurality of control signals of a same frequency and varying phases; a history capacitor that integrates a received signal; a capacitor group comprised of m rotate capacitors (where m is a natural number of two or greater) that are sequentially connected in parallel with the history capacitor and integrate the received signal; and a buffer capacitor that integrates a signal released from the capacitor group, wherein: the m rotate capacitors forming the capacitor group integrate the received signal at respective timings based on the plurality of control signals; and the plurality of m rotate capacitors are divided into a plurality of groups based on timings at which the integrated received signal is released, and release the integrated received signal to the buffer capacitor such that at least part of a period in which the received signal is integrated in rotator capacitors forming one group selected from the plurality of groups and a period in which a received signal integrated in a period prior to the part of the period, is released from rotate capacitors forming other groups than the selected one group, overlap in the time domain, the discrete filter comprises a capacity adjusting section that is connected in parallel with the capacitor group and the buffer capacitor and that adjusts an amount of integration of the signal released from the capacitor group and integrated in the buffer capacitor.