Patent ID: 7913211

Claim:
A logic cell configuration processing method for a CMOS semiconductor in which leak current per unit width is equal for a P-channel MOS transistor and an N-channel MOS transistor, the method comprising: calculating a probable average leak current, which is an expected value of leak current of the P-channel MOS transistor and the N-channel MOS transistor in the logic cell based on an input signal to be input to the logic cell; comparing a contribution of the P-channel MOS transistor with a contribution of the N-channel MOS transistor to the calculated probable average leak current; deciding the P-channel MOS transistor or the N-channel MOS transistor, whichever has a greater contribution, to be a low leak type MOS transistor; and adjusting, by a computer, ON current of the low leak type MOS transistor to be equal to ON current of the other MOS transistor.