Patent ID: 8868885

Claim:
A method comprising: at a first stage: loading, from a data memory into a configuration vector memory within a processor configuration values, pointers to non-consecutive elements of data elements, stored at a source vector memory within the processor to be used for executing a program instruction; wherein the program instruction is a combination of two or more of predetermined elemental instructions, each elemental instruction executable at a different type of execution unit within the processor; and at a second stage: executing the elemental instructions of the program instruction in successive operations, wherein executing a first elemental instruction comprises: using a first portion of the configuration values stored at the configuration vector memory to permute on-the-fly data elements in the source vector memory such that non-consecutive data elements are input to a first-type execution unit; executing the first elemental instruction in the first-type execution unit according to the first portion of the configuration values; and outputting the result of the first-type execution unit to a first-result vector memory, which serves as a source vector register for a second-type execution unit which executes a second successive elemental instruction; executing the second elemental instruction in the second-type execution unit according to a second portion of the configuration values stored at a second configuration vector memory and values stored at the first-result vector memory; and outputting the result of the second-type execution unit to a second-result vector memory, wherein each type of execution unit comprises parallel execution units to execute the corresponding elemental instruction in parallel.