Patent ID: 8648392

Claim:
A semiconductor integrated circuit comprising standard cells, wherein: among the standard cells, a latch or a master slave flip-flop includes: a plurality of PMOS transistors formed on a substrate along a first direction such that a gate length direction of each of the PMOS transistors is parallel to the first direction; a plurality of NMOS transistors which are formed on the substrate along the first direction such that a gate length direction of each of the NMOS transistors is parallel to the first direction, and each of which is opposed to a corresponding one of the plurality of PMOS transistors in a second direction perpendicular to the first direction; and a plurality of gate lines which correspond to the plurality of PMOS transistors and the plurality of the NMOS transistors, respectively, and which are arranged parallel to each other and extend linearly along the second direction such that each of the gate lines passes through gate areas of a corresponding one of the PMOS transistors and a corresponding one of the NMOS transistors, and the latch or the master slave flip-flop further includes at least one dummy gate line arranged parallel to, and extending linearly along, the second direction together with the plurality of gate lines.