Patent ID: 7716267

Claim:
A decimal calculation apparatus which performs multidigit decimal calculation with a number of calculation digits set in a calculation instruction, and which comprises: a multidigit memory section which acts as a memory such that data are read and written on a per-word basis, each word comprising a plurality of digits, and which stores two BCD-coded operation data subjected to an operation, each operation data comprising a plurality of words; a start digit memory section which stores address data indicating an operation start digit; a calculation-instruction memory section which stores a calculation instruction having a type of calculation set therein; an address control circuit which, based on the calculation instruction stored in the calculation-instruction memory section, takes out the address data indicating the operation start digit from the start digit memory section and provides the multidigit memory section with an address signal for reading operation data on the per-word basis from a position where the start digit is a least significant digit of word data; and a decimal calculation section which (i) comprises a computing unit that processes BCD-coded data on the per-word basis, (ii) performs an operation for the operation data comprising the plurality of words read out from the multidigit memory section in response to designation by the address control circuit, and (iii) sequentially writes an operation result to the multidigit memory section.