Patent ID: 8111340

Claim:
A display apparatus comprising: scanning lines; signal lines crossing the scanning lines; thin-film transistors connected to the scanning lines and the signal lines; capacitors including a lower electrode, a dielectric film, and an upper electrode sequentially stacked over the scanning lines, the capacitors being connected to the thin-film transistors; a plurality of interlayer insulating films disposed over the scanning lines such that the signal lines, the thin-film transistors, and the capacitors are disposed between or on the plurality of interlayer insulating films; a plurality of upper interlayer insulating films included in the plurality of interlayer insulating films and disposed above the signal lines, the thin-film transistors, and the capacitors; common lines disposed between or on the plurality of upper interlayer insulating films; pixel electrodes disposed between or on the plurality of upper interlayer insulating films; and connection holes continuously penetrating the plurality of interlayer insulating films disposed between the common lines and the capacitors, the common lines and the capacitors being directly interconnected via the connection holes, and the connection holes having a ratio of depth to opening width of more than 1, wherein, one of the common lines is disposed on one of the plurality of upper interlayer insulation films and in one of the connection holes to directly connect the one common line to one of the capacitors, and the one of the plurality of upper interlayer insulating films is formed so that a ratio (β/α) of a first thickness (β) of the one of the plurality of upper interlayer insulation films from a bottom of the one connection hole to a height of the commons lines next to the connection hole to a thickness (α) of a portion of the one of the plurality of upper interlayer insulation films disposed on the one common line next to the one connection hole is 0.7 or more.