Patent ID: 6930628

Claim:
A circuit for generating a digital data signal from an analog input data signal comprising: a) master-slave flip-flop receiving said analog input data signal; b) an amplitude detecting circuit for detecting the amplitude of said analog input data signal, said analog input data signal including a clock signal, and generating an amplitude detection signal in response thereto said amplitude detecting circuit including a sample and hold circuit for receiving said analog input data signal, a frequency divider circuit for dividing said recovered clock signal by a predetermined amount and supplying a divided clock signal to said sample and hold circuit, and a squaring and integrating circuit coupled to said sample and hold circuit; c) a phase shifting circuit responsive to said amplitude detection signal for supplying a phase shifted clock signal as a clock input to said master-slave flip flop; a clock recovery circuit receiving said analog input data signal and generating a recovered clock signal from said clock signal in said analog input data signal; said amplitude detecting circuit including a sample and hold circuit for receiving said analog input data signal; a frequency divider circuit for dividing said recovered clock signal by a predetermined amount and supplying a divided clock signal to said sample and hold circuit, and a squaring and integrating circuit coupled to said sample and hold circuit.