Patent ID: 7295485

Claim:
A memory device comprising: a plurality of programmable memory cells; a plurality of local bit lines correspondingly coupled to said plurality of memory cells; a main bit line coupled to at least one local bit line; a plurality of switching transistors placed in series in said main bit line and dividing said main bit line into a plurality of main bit line partitions; wherein said switching transistors are coupled to control circuits capable of selectively isolating and selectively coupling at least one main bit line partition of the main bit line from or to at least one other main bit line partition of the main bit line; wherein at least one main bit line partition of the main bit line is configured to be coupled to at least one local bit line by a local bit line select transistor; wherein the at least one main bit line partition of the main bit line is configured to be coupled to a voltage bias line; and wherein at least one other main bit line partition of the main bit line is simultaneously coupled to a sense circuit.