Patent ID: 7294548

Claim:
A method of fabricating a semiconductor device, comprising the steps of: providing a substrate having a memory cell region and a high-voltage circuit region; forming a first source/drain region in the substrate within the memory cell region and forming a second source/drain region in the substrate within the high-voltage circuit region; sequentially forming an oxide layer, a first conductive layer and a top layer over the substrate; patterning the top layer and the first conductive layer to define a floating gate in the memory cell region, and removing the top layer and the first conductive layer in the high-voltage circuit region; performing an oxidation process to thicken the exposed oxide layer; removing the top layer; forming a barrier layer over the exposed floating gate; forming a second conductive layer over the substrate to cover the oxide layer and the barrier layer; and patterning the second conductive layer to define a gate in the high-voltage circuit region and a control gate in the memory cell region.