Patent ID: 8001319

Claim:
A semiconductor storage apparatus to be coupled with a system bus to receive a write request accompanied with first and second sectors of data, comprising: a plurality of nonvolatile semiconductor memories which store said first and second sectors of data therein; and a control module to be coupled with said system bus, and coupled with said plurality of nonvolatile semiconductor memories, wherein said control module sends a first erase command to one of said plurality of nonvolatile semiconductor memories to initiate a first internal erase operation of data within said one of said plurality of nonvolatile semiconductor memories, wherein, after said first erase command has been sent, said control module sends a second erase command to another of said plurality of nonvolatile semiconductor memories, different from said one of said plurality of nonvolatile semiconductor memories to which said first erase command was sent, to initiate a second internal erase operation of data within said other of said plurality of nonvolatile semiconductor memories while said one of said plurality of nonvolatile semiconductor memories is still performing said first internal erase operation responsive to said first erase command; and wherein the control module operates to send the first and second erase commands to predetermined ones of the nonvolatile semiconductor memories responsive to a management table internal to the control module, wherein the management table is capable of storing entries indicating predetermined portions of a plurality of the nonvolatile semiconductor memories to be subsequently erased, wherein the entries in the management table control the order in which the predetermined portions of the plurality of the nonvolatile semiconductor memories are erased, wherein the entries in the management table are updated in response to completion of each of the first and second internal erase operations.