Patent ID: 8507338

Claim:
A fabricating method of semiconductor structure, comprising the steps of: providing a substrate with a dielectric layer and a gate dielectric layer formed thereon, and a plurality of first doped regions and a plurality of second doped regions formed therein, wherein the dielectric layer has a first opening and a second opening exposing a portion of the substrate, the first doped regions are respectively formed in the substrate at two sides of the first opening and the second doped regions are respectively formed in the substrate at two sides of the second opening, the gate dielectric layer comprising a high-k dielectric layer and a barrier layer sequentially stacked on bottoms of the first opening and the second opening; forming a sacrificial layer on a portion of the gate dielectric layer within the second opening, a material of the sacrificial layer comprising polysilicon; forming a first work function metal layer on a portion of the gate dielectric layer within the first opening and the sacrificial layer; and removing the first work function metal layer and the sacrificial layer within the second opening.