Patent ID: 8426316

Claim:
A method of processing a semiconductor structure including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer, the method comprising the steps of: using a Chemical Mechanical Polishing (CMP) process to polish the semiconductor structure to expose areas of the TaN—Ta liner; providing a device having first and second chambers; establishing a first pressure in the first chamber and a second pressure in the second chamber, said first pressure being greater than said second pressure; conducting XeF2 into the first chamber; positioning the semiconductor structure in the second chamber; allowing XeF2 to pass from the first chamber to the second chamber; and exposing the semiconductor structure to the XeF2 in said second chamber after the CMP process to remove at least a portion of the TaN—Ta liner substantially completely to the dielectric layer while preserving all of the dielectric material; and wherein the CMP is finished before exposing the semiconductor structure to the XeF2 in order to remove the at least a portion of the TaN—Ta liner while reducing mechanical degradation, chemical modification and loss of the dielectric material by the CMP.