Patent ID: 8194691

Claim:
A multi-protocol processor comprising: a plurality of input/output (I/O) interfaces configured to facilitate selective optical-electrical trafficking of data transmitted in accordance with a selected one of a plurality of communication protocols; a plurality of data link and physical sub-layer processing units selectively coupled to each other and to one or more of the plurality of I/O interfaces, wherein said processing units are configured to be selectively employed in combination to perform selected data link and physical sub-layer processing on egress and ingress ones of said transmitted data, in accordance with said selected one of said plurality of communication protocols; a buffering structure coupled to at least one of said plurality of I/O interfaces and a media processing one of said data link and physical sub-layer processing units, wherein said buffering structure includes at least a first First-in-First-Out (FIFO) storage structure configured to stage a selected one of undiverted ones of a plurality of ingress packets and undiverted ones of a plurality of egress packets; and first associated packet drop logic coupled to the first FIFO storage structure, and configured to selectively effectuate head or tail flush of the first FIFO storage structure.