Patent ID: 7539878

Claim:
A data processing system on an integrated circuit, comprising: a central processing unit (CPU) for executing instructions, including a low power mode instruction used for entering a low power mode; wherein the CPU comprises an execution unit for executing instructions; a logic unit for asserting a low power mode signal in response to the CPU entering a low power mode instruction; a storage device for storing, prior to executing the low power mode instruction, a current state of a programmer's model; and a bus interface for coupling the CPU to a system bus; a clock generator for providing a clock signal to time various functions of the CPU; a power control unit, coupled to the logic unit, the power control unit receiving the low power mode signal, and in response, the power control unit for disabling the clock generator, maintaining a power supply voltage to the logic unit and the storage device, while removing the power supply voltage from the execution unit and the bus interface; wherein the central processing unit, the clock generator, and the power control unit are on the integrated circuit.