Patent ID: 6934182

Claim:
A static random access memory device, comprising: a memory comprising an array of memory cells, each memory cell comprising; a first and second passgate transistor; a first and second storage node, wherein the first passgate transistor is connected between a first bit line and a first storage node, wherein a gate terminal of the first passgate transistor connects to a word line, and the second passgate transistor is connected between a second bit line and the second storage node, wherein a gate terminal of the second passgate transistor connects to the word line; a first pull-up transistor, connected between a source voltage and the first storage node, wherein a gate terminal of the first pull-up transistor is connected to the second storage node; a second pull-up transistor, connected between the source voltage and the second storage node, wherein a gate terminal of the first pull-up transistor is connected to the first storage node; a first pull-down transistor, connected between the first storage node and a ground, wherein a gate terminal of the first pull-down transistor is connected to the second storage node; and a second pull-down transistor, connected between the second storage node and the ground, wherein a gate terminal of the second pull-down transistor is connected to the first storage node; wherein the first and second passgate transistors and the first and second pull-down transistors have first threshold voltages that are substantially the same, and wherein the first and second pull-up transistors have second threshold voltages that are substantially the same, and wherein the first threshold voltages are greater than the second threshold voltages.