Patent ID: 8110459

Claim:
A method of fabricating a semiconductor device, comprising: forming a n-channel MOSFET and a p-channel MOSFET on a semiconductor substrate; flexing the substrate with a first concavity; while the substrate is flexed with the first concavity, forming a first stress enhancing layer over the substrate to cover the n-channel MOSFET and the p-channel MOSFET; selectively removing a part of the first stress enhancing layer in an area corresponding to the p-channel MOSFET; flexing the substrate with a second concavity opposite to the first concavity; while the substrate is flexed with the second concavity, forming a second stress enhancing layer over the substrate to cover the n-channel MOSFET and the p-channel MOSFET; and selectively removing a part of the second stress enhancing layer in a an area corresponding to the n-channel MOSFET.