Patent ID: 8710862

Claim:
A memory subsystem comprising: a memory module comprising: a first rank of memory circuits comprising a first plurality of memory circuits; and a second rank of memory circuits comprising a second plurality of memory circuits; an interface circuit; a first transmission line electrically coupling the interface circuit to a first memory circuit of the first plurality of memory circuits of the first rank; and a second transmission line electrically coupling the interface circuit to a second memory circuit of the second plurality of memory circuits of the second rank; wherein the interface circuit is operable to: present the first and the second ranks of memory circuits to a memory controller as a single rank of emulated memory circuits; terminate one or more of the first transmission line with the first termination resistance or the second transmission line with the second termination resistance, wherein the first termination resistance and the second termination resistance are each selected based on at least a resistance-setting command for the single rank of emulated memory circuits received from the memory controller, and wherein the first termination resistance or the second termination resistance is different from a termination resistance indicated by the resistance-setting command received from the memory controller.