Patent ID: 7525143

Claim:
A semiconductor device comprising: a first interlayer insulating layer and a second interlayer insulating layer sequentially stacked on a semiconductor substrate having a cell array region and a peripheral circuit region; a first contact plug formed through a predetermined portion of the first interlayer insulating layer in the cell array region to contact the semiconductor substrate and having an upper surface that is lower than an upper surface of the first interlayer insulating layer; a cup-shaped lower electrode formed through the second interlayer insulating layer and a predetermined portion of the first interlayer insulating layer in the cell array region to contact the first contact plug, wherein the first interlayer insulating layer has a thickness that is greater than a thickness of the second interlayer insulating layer; a dielectric layer and an upper electrode conformally and sequentially covering at least a bottom and an inner sidewall of the lower electrode; and a second contact plug formed through the first interlayer insulating layer in the peripheral circuit region to contact the semiconductor substrate and having an upper surface at the same height as the upper surface of the first interlayer insulating layer.