Patent ID: 8451154

Claim:
A method of calibrating a DAC element in a stage of a pipelined analog to digital converter, the method comprising: providing a plurality of DAC elements each having a capacitor with a first plate connected to an operational amplifier and a second plate switchably connected to one of an input signal voltage Vin, a positive reference voltage +Vref, a negative reference voltage −Vref and a common voltage 0; providing an additional DAC element having a capacitor with a first plate connected to the operational amplifier and a second plate switchably connected to one of the positive reference voltage +Vref and the negative reference voltage −Vref; selecting one of the plurality of DAC elements to be a DAC element under calibration; applying a sequence of signals to the additional DAC element and the DAC element under calibration to obtain four calibration states while the input signal voltage to the DAC element under calibration is held at 0; and extracting a DAC element error of the DAC element under calibration by calculating an average of the difference between different pairs of the four calibration states.