Patent ID: 8705283

Claim:
A method comprising: applying a first voltage to a memory cell; applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition; applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage; applying a third voltage to the memory cell when the memory cell is not in the erased condition after applying the second voltage, the third voltage being higher than the second voltage; applying the second voltage at least one more time prior to applying the third voltage; wherein the first voltage is applied a first number of times and the second voltage is applied a second number of times, each of the first number and the second number is plural and the first number is equal to the second number; and wherein the first number is set according to the following equation: N train=( T max× V step)/{( V max− V min)× T pulse} wherein Ntrain is the first number, Vmax is a maximum voltage permitted to be used in an erase operation, Vmin is a minimum voltage to be used in the erase operation, Tmax is a maximum time allowed for the total erase operation, Vstep is an amount of voltage difference between the first voltage and the second voltage, and Tpulse is the time duration of the erase operation.