Patent ID: 7355243

Claim:
A flash memory device comprising: an isolation layer for defining a plurality of active regions in a semiconductor substrate, each of said active regions being a region in which a plurality of flash memory cells are to be formed; a gate stack formed to cross the active regions and the isolation layer; a sidewall spacer formed at sidewalls of the gate stack; a common source line for electrically interconnecting a plurality of sources of the flash memory cells, said common source line being formed in the isolation layer by partially removing an insulating material in the isolation layer, said common source line being formed in parallel to a word line formed over the gate stack, and said common source line including a recess region having a surface lower than a face of the active region; and a silicide layer formed on the common source line in parallel with the word line to interconnect the plurality of sources, wherein the common source line and a drain region are formed at both sides of the gate stack, and the first portion of the sidewall spacer adjacent to the common source line has a smaller thickness than a thickness of a second portion of the sidewall spacer adjacent to the drain region and wherein said silicide layer having a recess region having a surface lower than the face of the active region along the sidewall spacer adjacent to the common source line.