Patent ID: 8214624

Claim:
A method for processing a thread in a pipelined processor, the thread comprising a plurality of sequential instructions, the plurality of the sequential instructions comprising short-latency instructions, long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed, the method consisting essentially of the steps of: before processing each long-latency instruction, incrementing by one, a counter associated with the thread; after processing each long-latency instruction, decrementing by one, the counter associated with the thread; before processing each hazard instruction, checking a value of the counter associated with the thread; and if the counter value is zero, processing the hazard instruction, or if the counter value is not zero, pausing processing of the hazard instruction until a later time; and processing a subset of a plurality of the threads by executing one instruction from each thread in the subset; and after processing a final instruction of the thread, removing the thread from the subset of the plurality of the threads; and periodically checking the value of the counter associated with any threads having instructions that have been paused when the counter value is not zero, and, if the value of the counter of the thread is zero, transiting that thread to a waiting-to-be-processed state.