Patent ID: 8004903

Claim:
A semiconductor memory device, comprising: a memory cell array including bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than said first logic data; and a sense amp circuit having a clamp transistor operative to clamp a bit line voltage, said sense amp circuit being operative to detect data in a selected memory cell via said clamp transistor and said bit line, said sense amp circuit including a current source load provided to supply read current to said bit line through said clamp transistor, a transfer circuit arranged between said current source load and said clamp transistor and on/off-controlled based on read data, a sense transistor having a gate connected to a connection node between said current source load and said transfer circuit, and a data latch operative to hold data detected at said sense transistor, wherein said clamp transistor comprises a clamp NMOS transistor, wherein said sense transistor comprises a PMOS transistor having a source connected via a switching element to a power supply terminal and a drain connected to said data latch, wherein said current source load includes a current source PMOS transistor on-driven for a certain time period after the beginning in each read cycle to supply read current, and a current source NMOS transistor given a certain gate voltage during each read cycle to supply current corresponding to a voltage drop on said sense node while said current source PMOS transistor is turned off for data sense, wherein said sense amp circuit is operative to read data from said selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of said clamp NMOS transistor, and is controlled to supply no read current in said second read cycle to a selected memory cell from which said first logic data is detected in said first read cycle, wherein a certain voltage is applied to word lines in said memory cell array during said first and second read cycles, wherein a control voltage applied to said clamp NMOS transistor in said first read cycle is determined lower than that in said second read cycle, and wherein said transfer circuit is off-controlled based on data held in said data latch in said second read cycle after said first logic data is detected in said first read cycle.