Patent ID: 7238608

Claim:
A method of manufacturing a semiconductor device having a memory cell region and a peripheral region, comprising the steps of: forming an alignment mark for positioning made of a conductive material, in said peripheral region; forming a first insulating film so as to cover said alignment mark and extend to said memory cell region; forming a second insulating film on said first insulating film; forming a third insulating film on said second insulating film, said third insulating film having a low etching rate in relation to a first etchant for said first insulating film; forming an opening portion so as to extend through said third and second insulating films up to said first insulating film; forming a spacer on the side wall of said opening portion, said spacer having a low etching rate in relation to said first etchant for said first insulating film; forming a first contact hole so as to extend through said first insulating film, using said third insulating film and said spacer as masks; filling said opening portion and said first contact hole with a first conductive material to form a contact plug; and selectively removing said third insulating film using a second etchant whose etching rate to said second insulating film is low.