Patent ID: 7462524

Claim:
A method for fabricating a stressed MOS transistor comprising the steps of: providing a substrate of a monocrystalline semiconductor material having a first lattice constant; forming a conductive gate electrode overlying the substrate and a gate electrode extension angularly extending from the gate electrode, the gate electrode having opposing sides and having a thickness and defining a channel in the monocrystalline semiconductor material underlying the gate electrode; forming sidewall spacers on the opposing sides of the gate electrode and on the gate electrode extension; etching trenches in the semiconductor substrate in alignment with the sidewall spacers and simultaneously etching a portion of the thickness of the conductive gate electrode and the gate electrode extension leaving a remaining portion of the conductive gate electrode and a remaining portion of the gate electrode extension; and selectively growing a stress inducing layer of material on the remaining portion of the conductive gate electrode and on the remaining portion of the gate electrode extension, and filling the trenches, the stress inducing layer of material having a second lattice constant different than the first lattice constant, wherein a first lattice mismatch in lattice parameters between the stress inducing layer of material that is grown in trenches and the underlying monocrystalline semiconductor material causes compressive longitudinal stress to be applied to the channel, and wherein a second lattice mismatch in lattice parameters between (a) the gate electrode and the gate electrode extension and (b) the stress inducing layer of material that is grown on the gate electrode and the gate electrode extension causes a tensile transverse stress to be applied to the channel; and simultaneously doping the gate electrode the gate electrode extension, and the stress inducing layer of material that is grown in trenches with conductivity determining impurities.