Patent ID: 8416630

Claim:
A nonvolatile memory array comprising: one or more columns of memory cells, each memory cell comprising: a first transistor having a first source terminal coupled to a row enable signal line and a first floating gate; a second transistor having a second source terminal coupled to the row enable signal line and a second floating gate; a first control capacitor coupled between a first data line and the first floating gate; a first tunneling capacitor coupled between a tunneling signal line and the first floating gate; a second control capacitor coupled between a second data line and the second floating gate; a second tunneling capacitor coupled between the tunneling single line and the second floating gate; a first readout switch having a first readout terminal and a first terminal coupled to a drain terminal of the first transistor, wherein a first current at the first readout terminal is substantially equal to drain current of the first transistor when the first readout switch is turned on; and a second readout switch having a second readout terminal and a second terminal coupled to a drain terminal of the second transistor, wherein a second current at the second readout terminal is substantially equal to drain current of the second transistor when the second readout switch is turned on; and a hysteresis circuit having a first node and a second node, the first node coupled to the first readout terminal, the second node coupled to the second readout terminal, the hysteresis circuit configured to modify a duration over which one or more memory cells in a column are programmed by increasing or decreasing current at one of the first and the second readout terminals.