Patent ID: 6855599

Claim:
A fabrication method for a flash memory device, comprising: providing a first conductive type substrate, wherein the substrate comprises a second conductive type first well region, a first conductive type second well region which is formed in and shallower than the second conductive type first well and at least a pair of stacked gate structures which are sequentially formed thereon, wherein a gap is located between the pair of stacked gate structures; forming source/drain regions in the substrate beside two sides of the stacked gate structures, wherein a first source/drain region is below the gap and a pair of second source/drain regions is outside the stacked gate structures; forming a plurality of spacers on sidewalls of the stacked gate structures; forming a first patterned photoresist layer on the substrate, the first patterned photoresist layer exposes the gap; etching the substrate until penetrating through a junction between the first source/drain region and the first conductive type second well region to form a first trench by using the first patterned photoresist layer and the stacked gate structures with the spacer as masks; removing the first patterned photoresist layer; forming a second patterned photoresist layer on the substrate, the second patterned photoresist layer exposes a portion of the substrate outside the stacked gate structure; etching the portion of the substrate to the second conductive type first well region to form a pair of second trenches by using the second patterned photoresist layer and the stacked gate structures with the spacers as masks; performing an ion implantation process to implant dopants into bottoms and sidewalls of the second trenches to form a pair of doped regions; removing the second patterned photoresist layer; forming a first contact plug in the first trench and to form a pair of second contact plugs in the second trenches, wherein the first contact plug electrically short the first source/drain region below the gap, and the second contact plug electrically connects with the second source/drain regions disposed outside the stacked gate structures and the doped regions; forming an interlayer dielectric layer on the substrate; forming a third contact plug which connects with the first contact plug in the interlayer dielectric layer; and forming a conductive line on the interlayer dielectric layer, wherein the conductive line electrically connects with the third contact plug.