Patent ID: 7389387

Claim:
A system, comprising: a processor; a memory controller coupled to the processor, the memory controller including an array of tag address storage locations, and a command sequencer and serializer unit coupled to the array of tag address storage locations; and a system memory coupled to the memory controller, the system memory including at least two memory modules, each memory module including at least one bank of memory devices, and a memory module buffer having a data cache coupled to an eviction buffer, both coupled to the bank of memory devices, the memory module buffer including a command deserializer and decoder unit to control the data cache and the eviction buffer according to a plurality of commands delivered by the memory controller, the commands sequentially delivered over a plurality of transfer periods of a memory access transaction, the plurality of commands including an activate command and a writeback command, the memory controller to issue a write transaction, the command deserializer and decoder unit to store a current line of data within the data cache until the memory controller signals an eviction, the command deserializer and decoder unit to instruct the data cache to evict the current cache line of data from the data cache into the eviction buffer.