Patent ID: 8504960

Claim:
A method for performing static timing analysis on a circuit the method comprising: (a) partitioning, a circuit design represented as interconnected gates into a plurality of levels, each of a plurality of gates in at least a level having an input that is independent of outputs of other gates in the same level; (b) initializing a first set of gates belonging to a first level as a current set of gates belonging to a current level; (c) performing static timing analysis of the circuit design for each level of the circuit design, comprising: (c1) assigning a set of multiple execution threads to a plurality of processors to perform static timing analysis for the current set of gates; (c2) storing the results of the static timing analysis for the current set of gates in a storage medium; and (c3) responsive to determining that a next level exists, using the results of the static timing analysis of the current level as arrival times for gates of the next level, updating a set of gates in the next level as the current set of gates, updating the next level as the current level, and repeating (c1) through (c3).