Patent ID: 7526399

Claim:
A method of delay calculation of relative timing paths of an integrated circuit, said method comprising: calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component, wherein said on-chip variation depending on said systematic component is based on a distance between two stages on said relative timing paths and a delay time of each of said stages and said on-chip variation depending on said systematic component is calculated from the following equation set (1); RTS n = ∑ j = 1 m ⁢ TP ⁢ ⁢ 2 j * VS ⁡ ( L p ⁢ ⁢ 1 ⁢ n - p ⁢ ⁢ 2 ⁢ j ) / ∑ j = 1 m ⁢ TP ⁢ ⁢ 2 j ⁢ ⁢ RTS m = ∑ i = 1 n ⁢ TP ⁢ ⁢ 1 i * VS ⁡ ( L p ⁢ ⁢ 2 ⁢ m - p ⁢ ⁢ 1 ⁢ i ) ⁢ ∑ i = 1 n ⁢ TP ⁢ ⁢ 1 i ( 1 ) where said relative timing paths contains a first path and a second path, said first path contains n stages, said second path contains m stages, TP 1 n is a delay time of the n-th stage in said first path, TP 2 m is a delay time of the m-th stage in said second path, VS(L p1n-p2m ) is the systematic component at the n-th stage in said first path, L p1n-p2m is a distance between the n-th stage in said first path and the m-th stage in said second path, VS(L p2m-p1n ) is a systematic component of the m-th stage in said second path, L p2m-p1n is a distance between the m-th stage in said second path and the n-th stage in said first path, RTS n is an on-chip variation depending on the systematic component in said first path, and RTS m is an on-chip variation depending on the systematic component in said second path; and carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.