Patent ID: 6919736

Claim:
A field programmable gate array (FPGA) comprising: (a) a plurality of logic blocks organized as rows and columns; (b) a plurality of horizontal and vertical interconnect channels (HIC's and VIC's) extending respectively along the rows and columns of said logic blocks for providing interconnection between the logic blocks; (c) at least first and second columns of configurable memory blocks (CMB's) embedded among the columns of logic blocks, wherein: (c.1) each CMB spans a plurality of said HIC's; (c.2) each given CMB has plural data-I/O sub-busses, operatively coupled to a different one of the HIC's among the HIC's spanned by the given CMB; (c.3) each given CMB is programmably configurable into at least a respective shallow-and-wide mode in which data-I/O words of the CMB have a relatively large, first number of bits per word and a correspondingly relatively large first number of said data-I/O sub-busses are used for conducting in parallel, the bits of the data-I/O words in the respective shallow-and-wide mode; and (c.4) each given CMB is further programmably configurable at least into a respective deep-and-narrow mode in which data-I/O words of the CMB have a relatively small second number of bits per word and a correspondingly relatively small second number of said data I/O sub-buses are used for conducting in parallel, the bits of the data-I/O words in the respective deep-and-narrow mode, where the relatively small second number of the respective deep-and-narrow mode is less than the corresponding relatively large, first number of the respective shallow-and-wide mode.