Patent ID: 7944759

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells connected to a plurality of word lines, a plurality of source lines, and a plurality of bit lines, each memory cell having a transistor with a floating body; a source line driver configured to control at least one of the plurality of source lines to select at least one memory cell of the plurality of memory cells in response to an address signal; a source line voltage generation unit configured to receive a source line reference voltage to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, adaptively vary the source line output voltage according to a temperature, and supply the source line output voltage to the at least one source line; and a sense amplifier configured to sense a difference in current flowing through the plurality of bit lines in response to data read from the selected at least one memory cell, amplify the difference to a level having high output driving capability and output the amplified current.