Patent ID: 8412916

Claim:
An integrated computing system comprising: a central processing unit etched on a single substrate; north bridge operably coupled to the central processing unit, and etched on the single substrate, wherein the north bridge includes a memory access request buffer interoperably coupled with a memory controller, wherein the memory access request buffer receives the memory access request from the central processing unit at an operating clock rate of the central processing unit; a bus operably coupled to the central processing unit and the north bridge and contained on the single substrate, wherein the bus provides a transport medium for memory access requests and corresponding memory responses between the central processing unit and the north bridge at an operating clock rate of the central processing unit; south bridge that is etched on the single substrate, wherein the south bridge provides an interface between at least one external device and the north bridge; a device bus that is contained on the substrate, wherein the device bus couples the north bridge to the south bridge; and a graphics controller that is etched on the substrate, wherein the graphics controller includes a frame buffer controller for processing data transferences between the graphics controller and a frame buffer and wherein the graphics controller issues a graphics memory access request to the north bridge.