Patent ID: 7362650

Claim:
An memory arrangement, comprising: an even number k≧4 of physically spaced RAM chips, each RAM chip having a plurality z of memory cells which are organized in disjoint cell groups, wherein, in each cell group, m respective memory cells can respectively be selected simultaneously by a cell group address in order for m data items to be respectively written or read simultaneously via an m-bit data bus on the respective RAM chip and collectively as an n-bit data group; a register, connected between the respective m-bit data bus of each RAM chip and an n-bit parallel port, for buffering and transmitting n respective parallel data bits as an n-bit packet between the n-bit parallel port and the m-bit data buses, wherein n is equal to an integer multiple of m and wherein a number of m-bit data groups which corresponds to the integer multiple is written or read in parallel via the m-bit data buses; and a selection device which responds to selection bits in order to select a respective separate cell group within the number of chips which corresponds to the integer multiple for each of the disjoint m-bit groups of the n-bit packet in order to write or read the number of m-bit data groups which corresponds to the integer multiple in parallel via respectively associated m-bit data buses; wherein the k RAM chips are classified into q≧2 disjoint chip groups, each group comprising k/q chips which are disposed at substantially same distances from the register, wherein m=q*n/k, wherein the selection device is configured to select one chip group from the q≧2 disjoint chip groups for each n-bit packet, and wherein a respective m-bit data group is written to or read from the register in parallel from each chip of the selected chip group via the associated m-bit data bus.