Patent ID: 7222261

Claim:
A test module comprising: single source circuitry to generate a test signal to a test signal input of a design-for-test (DFT)/Built-in-system-test (BIST) analog/mixed-signal circuit-under-test included in a semiconductor device based on user-defined test patterns received from a vector memory, the vector memory configured to provide repeatable test patterns to the single source circuitry in a user-programmable control loop; capture circuitry configured to receive an output signal from a test signal output of the DFT/BIST analog/mixed-signal circuit-under-test based on the user-defined test patterns received from the vector memory; processing circuitry configured to respond to user-programmed algorithms and configured to analyze the output signal from the DFT/BIST analog/mixed-signal circuit-under-test independent of the host computer; and a programmable data bus coupled to the capture circuitry and the processing circuitry and configured to provide data from the capture circuitry to the processing circuitry; wherein the test module is configured for use in a semiconductor tester comprising a host computer.