Patent ID: 7960799

Claim:
A charge trap type non-volatile memory device, comprising: memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend, each of the memory cells having a tunnel insulating film formed on the silicon substrate, a charge film formed on the tunnel insulating film, and a common block film formed on the charge film; and element isolation insulating films each buried in the element isolation trench between the memory cells, wherein: each of the common block films is formed on the charge films and the element isolation insulating film, an upper surface of the element isolation insulating film is positioned between upper and lower surfaces of the charge film, to form a recess defined by the upper surface of the element isolation insulating film and two side walls of the charge films of two neighboring memory cells opposing to each other via the element isolation trench, each of the common block films has a protruding portion that protrudes downward and fits in the recess, and a central portion of an upper surface of the element isolation insulating film is higher than a peripheral portion of the upper surface thereof.