Patent ID: 8735235

Claim:
A method of fabricating a semiconductor device, comprising: providing a substrate including an insulating layer, a dummy gate structure, spacer elements adjacent the dummy gate structure, and a contact etch stop layer (CESL) surrounding the spacer elements and dummy gate structure; forming a trench in the insulating layer, wherein the trench has a first width and is formed by removing the dummy gate structure; modifying the profile of the trench after removing the dummy gate structure by removing a portion of the spacer elements without removing the CESL, wherein the modifying includes providing a first portion of the trench with a second width, and a second portion of the trench with the first width, the second width being greater than the first width and wherein the modified trench includes a sidewall having an upper portion that is oblique to and contiguous with a lower portion of the sidewall, the lower portion being substantially perpendicular the substrate; and forming a metal gate in the trench having the modified profile.