Patent ID: 7943926

Claim:
A nonvolatile memory device comprising: a plurality of lower electrodes; a first semiconductor oxide layer of a transition metal oxide on the plurality of lower electrodes; a second semiconductor oxide layer of a transition metal oxide on the first semiconductor oxide layer; a plurality of upper electrodes on the second semiconductor oxide layer; a plurality of lower common electrodes in a first direction on the plurality of lower electrodes; and a plurality of upper common electrodes on the plurality of upper electrodes, the plurality of upper common electrodes intersecting the plurality of lower common electrodes in a second direction, wherein the second semiconductor oxide layer has memory switching characteristics, the first semiconductor oxide layer and the second semiconductor oxide layer are between the plurality of lower electrodes and the plurality of upper electrodes at intersections of the plurality of lower common electrodes and the plurality of upper common electrodes, and a p-n junction is at an interface between the first and second semiconductor oxide layers, the p-n junction p-n diode coupling the first semiconductor oxide layer and the second semiconductor oxide layer.