Patent ID: 8179887

Claim:
A network system comprising: an ingress circuit configured to receive a packet from an input port, wherein the ingress circuit assigns a tag value associated with the packet; a delay line coupled to the ingress circuit and configured to store the packet together with the tag value in a sequence based on packet arrival time in the delay line, wherein the delay line provides a predefined delay for the packet; a demultiplexer coupled to the ingress circuit and operable to receive the packet with the tag value and identify a processing engine (“PE”) having a PE number in an array of PEs, the demultiplexer forwarding the packet to the PE for generating a processed packet; a tag memory coupled to the demultiplexer and configured to store the tag value addressed by the PE number; and a multiplexer coupled to the tag memory and the delay line, the multiplexer configured to replace the packet in the delay line with the processed packet in response to the tag value.