Patent ID: 8460971

Claim:
A semiconductor device packaging method comprising: providing a plurality of wafers; performing an electrical test applied to each of the wafers to acquire a plurality of available regions of each of the wafers; cutting the available regions down from the wafers, and thereby a plurality of wafer pieces are obtained, each of the wafer pieces having an active surface and a back surface, the active surface being opposite to the back surface and at least one bonding pad formed thereon; providing at least one carrier substrate having a first surface and a second surface opposite to each other; forming an adhesive layer on the first surface of the carrier substrate; bonding the wafer pieces to the carrier substrate by contacting the active surfaces of the wafer pieces with the adhesive layer, wherein each adjacent two of the wafer pieces are separated with a gap therebetween and whereby a part of the adhesive layer is exposed; filling a packaging layer into each of the gaps; forming at least one through silicon via in each of the wafer pieces to expose the bonding pad; forming a redistribution circuit layer on the back surface of each of the wafer pieces and filled into the through silicon via for electrical connection with the bonding pad; and performing a sawing process to saw starting from each of the packaging layers to the second surface of the carrier substrate, and thereby a plurality of semiconductor device packaging structures are obtained.