Patent ID: 8090062

Claim:
A process for a packet detection controller in an initial interpacket mode, said packet detection controller examining each of a plurality of RX_IQ streams of baseband data and asserting an associated GT_NFLR when an increase in signal level on a particular said stream exceeds a noise floor by an increment delta which is associated with said stream, each said stream generated by an antenna coupled to a variable gain amplifier coupled to a mixer forming said stream, said variable gain for each said stream controlled by an associated AGC controller, said streams equally weighted and applied to a packet detector with an SNR_MODE input initially set to LOW, the packet detector asserting a PACKET_DET output when a packet is detected, said packet detector also having a PD_RESET input for suspending the packet detection response of said packet detector; the process comprising: a first step of examining said plurality of said RX_IQ streams and if at least one said GT_NFLR is asserted before said PACKET_DET, asserting said SNR_MODE input to HIGH, asserting said PD_RESET input for a duration of time equal to an AGC process time during which time said AGC controller adjusts the gain of each said variable gain amplifier, thereafter unasserting said PD_RESET until said PACKET_DET is asserted within an interval of time following said GT_NFLR assertion, and if said PACKET_DET is not asserted within an interval after said GT_NFLR assertion, asserting said SNR_MODE signal to LOW and resetting said AGC controllers to an initial state; a second step of performing a single step AGC correction and suspending said AGC process if said PACKET_DET is asserted before the assertion of any said GT_NFLR signal.