Patent ID: 7893465

Claim:
A semiconductor device, comprising: a semiconductor substrate having a bonding pad area and a fuse area; a first conductive structure formed on the substrate, the first conductive structure having a thickness and a top surface and comprising a first metal layer; a metal fuse formed on the substrate in the fuse area, the metal fuse having a thickness smaller than the thickness of the first conductive structure and a top surface coplanar with the top surface of the first conductive structure; a first inter-metal dielectric (IMD) layer covering the first conductive structure and the metal fuse; a via hole formed through the first IMD layer such that the first conductive structure is partially exposed through the via hole; a second conductive structure formed on the first IMD layer over the substrate and electrically connected to the first conductive structure through the via hole, the second conductive structure comprising a second metal layer and an etching prevention layer formed over the second metal layer on areas of the substrate other than the bonding pad area but not in the bonding pad area; and a second IMD layer formed on the first IMD layer, the second IMD layer covering the second conductive structure and comprising an opening through which the fuse area and the bonding pad area are exposed through the first IMD layer.