Patent ID: 8363467

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory cell units, each of the memory cell units including data-rewritable non-volatile memory cells connected in series and a first selection transistor; a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array; a first gate line commonly connected to gates of the first selection transistors on the same row in the memory cell array; and a bit line, the first selection transistor being connected to the bit line; wherein a selected memory cell unit is connected to a selected word line, a first word line, a second word line and a third word line, all of the first word line, the second word line and the third word line being different from the selected word line, and the first word line, the second word line and the third word line being different from one another, and wherein a first voltage, a second voltage, a third voltage and a fourth voltage are respectively applied to the first word line, the second word line, the third word line and the first selection transistor when a high voltage for writing is applied to the selected word line in data writing, the first voltage, the second voltage and the third voltage are lower than the high voltage for writing, the first voltage, the second voltage and the third voltage are different from one another, the fourth voltage is lower than the first voltage and the third voltage, and the high voltage for writing is applied to the selected word line after the second voltage and the third voltage are applied to the second word line and the third word line, respectively.