Patent ID: 7446390

Claim:
A semiconductor device, comprising: a semiconductor substrate including a main surface; a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction, one end of each of said plurality of first interconnection connecting to a second interconnection; a plurality of third interconnections formed in said predetermined region and extending in said predetermined direction, one end of each of said plurality of third interconnection connecting to a fourth interconnection; and a plurality of fifth interconnections each adjacent to one of said plurality of first interconnections and said plurality of third interconnections located at an edge of said predetermined region, extending in said predetermined direction, and having a fixed potential, wherein said plurality of first interconnections and said plurality of third interconnections are located at substantially equal intervals in a first plane parallel to said main surface, said second interconnection, said fourth interconnection and said fifth interconnections are located in said first plane, one side of each of said plurality of first interconnections faces each of said plurality of third interconnections, and an another side of each of said plurality of first interconnections faces each of said plurality of third interconnections, an insulating layer is formed on said main surface and fills in between each of said plurality of first interconnections, between each of said plurality of third interconnections, and between one of said plurality of first interconnections and said plurality of third interconnections and said fifth interconnection adjacent to each other, said plurality of first interconnections, said plurality of third interconnections, and said plurality of fifth interconnections are located to align in a direction substantially perpendicular to said predetermined direction, and a capacitance is formed by said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection and said insulating layer formed between each of said plurality of first interconnections and each of said plurality of third interconnections.