Patent ID: 7310710

Claim:
A multi-context register file comprising: a first register file cell including: a plurality of bit cells to store data bits corresponding to a plurality of different processing threads, said plurality of bit cells including at least one first bit cell corresponding to a first processing thread and at least one second bit cell corresponding to a second processing thread; a router in communication with said plurality of bit cells to controllably couple a selected bit of data stored in said plurality of bit cells to a selected functional unit in response to control information; the multi-context register file further comprising at least a second register file cell including: a plurality of other bit cells to store data bits corresponding to said plurality of different processing threads, said plurality of other bit cells including at least one other bit cell corresponding to said first processing thread and at least one other bit cell corresponding to said second processing thread; and another router in communication with said plurality of other bit cells to controllably couple a selected bit of data stored in said plurality of other bit cells to a selected functional unit in response to control information.