Patent ID: 7480685

Claim:
A microprocessor for generating a packed sum of absolute differences, comprising: an instruction translator, for translating an MMX PSADBW macroinstruction into at least first and second microinstructions; and an MMX unit, coupled to said instruction translator, for generating a result of said PSADBW macroinstruction in response to said at least first and second microinstructions, wherein said macroinstruction includes packed operands, wherein said MMX unit generates packed differences of said operands in response to said first microinstruction, and generates a sum of absolute values of said packed differences in response to said second microinstruction; a plurality of subtractors, for generating said packed differences of said operands wherein said plurality of subtractors also generate a sign for each of said packed differences of said operands; and multiplexing logic, having a microinstruction type control input, wherein if said control input indicates said microinstruction type is of said second microinstruction, then said multiplexing logic selects selectively inverted said packed differences of said operands for providing to an adder as a plurality of addends, wherein if said control input indicates said microinstruction type is not of said second microinstruction, then said plurality of multiplexers select a plurality of partial products from a multiplier for providing to said adder as said plurality of addends.