Patent ID: 8046400

Claim:
A microprocessor, comprising: an x87 Floating Point Control Word (FPCW) including a Precision Control (PC) field programmable for specifying a precision of floating point (FP) calculations made by a FP unit (FPU) of the microprocessor; an instruction dispatcher, configured to dispatch an x87 FP addition instruction (FPADD) to the FPU, the FPADD having first and second FP addends, wherein mantissas of the first and second addends potentially include bits of lesser arithmetic significance than a precision specified by the PC field; and the FPU, configured to: add the first and second addends to generate a sum; determine whether at least one of a set of predetermined conditions exists in the first and second addends with respect to their contribution to a rounding determination of the sum and relative to the precision specified by the PC field; if none of the set of predetermined conditions exists: (1) make the rounding determination based on bits of the mantissa of the smaller of the first and second addends and the precision specified by the PC field; and (2) selectively round up the sum based on the rounding determination for generating a final result of the FPADD; and if at least one of the set of predetermined conditions exists: (1) derive rounding information from the first and second addends, save the sum, and save the rounding information; (2) signal the instruction dispatcher to re-dispatch the FPADD to the FPU; and (3) in response to the instruction dispatcher re-dispatching the FPADD to the FPU: (a) make the rounding determination based on the saved rounding information and the precision specified by the PC field; and (b) selectively round up the sum based on the rounding determination for generating the final result.