Patent ID: 7181716

Claim:
A method for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said method comprising: analyzing the electronic circuit to determine a first circuit parameter for each of the victim circuit and the aggressor circuits and a second circuit parameter for each of the aggressor circuits; ordering the aggressor circuits based on the first and second circuit parameters thereof; setting a current model parameter of the circuit model to an initial value; selecting a first aggressor circuit in accordance with said ordering; determining whether to reduce the selected aggressor circuit into a virtual attacker model before inserting into the circuit model based on the first circuit parameter thereof; updating the current model parameter in accordance with either the selected aggressor circuit or the virtual attacker model thereof to be inserted; inserting either the selected aggressor circuit or the virtual attacker model thereof to the circuit model in accordance with said determining; selecting a next aggressor circuit based on said ordering; and iteratively repeating said determining, said updating, said inserting, and said selecting a next aggressor circuit; wherein said ordering comprises: calculating an ordering factor for each aggressor circuit, the ordering factor being a function of the first circuit parameter and the second circuit parameter, further wherein the first circuit parameter represents a size of the circuit and the second circuit parameter represents a noise strength of the circuit, the ordering factor of each aggressor circuit being expressed as: F ( S,N )= S/S MAX +( N MAX −N )/ N MAX , where S is the size of the aggressor circuit, N is the noise strength of the aggressor circuit, S MAX is the size of the largest aggressor circuit, and N MAX is the noise strength of the strongest aggressor circuit.