Patent ID: 8269351

Claim:
A multi-chip stack package structure, comprising: a substrate, having an upper surface and a lower surface, a chip placement area being defined on and a plurality of contacts being disposed on said upper surface, said plurality of contacts being located outside said chip placement area; a first chip, having an active surface and a rear surface opposite to said active surface, said first chip being disposed on said chip placement area with said rear surface, a plurality of first pads being disposed on said active surface and a plurality of first bumps each being formed on one of said plurality of first pads; a plurality of metal wires, connecting said plurality of first bumps to said plurality of contacts; a second chip, having an active surface and a rear surface opposite to said active surface, a plurality of second pads being disposed on said active surface and a plurality of second bumps each being formed on one of said plurality of second pads, said second chip being mounted to said first chip with said active surface of said second chip facing said active surface of said first chip and said plurality of second bumps being correspondingly connected to said plurality of metal wires and said plurality of first bumps respectively; at least a third bump, disposing between each of said plurality of metal wires and each of said plurality of second bumps; and an encapsulant, encapsulating said substrate, said first chip, said second chip, and said plurality of metal wires.