Patent ID: 7396725

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an insulating layer, a first conductive layer, a dielectric layer and a capping conductive layer over a semiconductor substrate in which a cell region is defined; etching the capping conductive layer and the dielectric layer to form contact holes in a first region of a drain select line and a source select line region of the cell region; forming a second conductive layer, a tungsten silicide layer and a hard mask layer over the semiconductor substrate including the contact holes; etching the hard mask layer, the tungsten silicide layer, the second conductive layer, the capping conductive layer, the dielectric layer and the first conductive layer to form a cell gate; and etching the hard mask layer, the tungsten silicide layer, the second conductive layer and the first conductive layer of the first region to form a drain select line and a source select line.