Patent ID: 8176972

Claim:
A compliant sealed vapor chamber for the cooling of at least one semiconductor chip, comprising: a housing having a plurality of walls forming said vapor chamber including at least one flat wall and an opposite second spaced wall; heat pipes are being provided in contact with exterior peripheral surface of the walls of said vapor chamber; a corrugated resiliently flexible structure peripherally surrounding a center member of said opposite second wall so as to form a compliant wall structure; said center member being reciprocatably or tiltably displaceable relative to said one flat wall and in contact with said semiconductor chip, said center member being positioned in a recessed portion of an outer wall portion of said housing, said opposite second spaced wall having a central portion with a first thickness between two end portions having a second thickness greater than the first thickness, wherein said two end portions define said recessed portion therebetween; at least one spring member extending between said one flat wall and said center member to exert a biasing forces against said center member towards a semiconductor chip arranged therebeneath externally of said vapor chamber; a liquid-permeable wick arrangement lining the internal wall surfaces of said vapor chamber; a volatile fluid filling a portion of the volume of said vapor chamber, whereby heat generated by said semiconductor chip is transferred into said vapor chamber and for further conduction therefrom, and a layer of an interface material being located intermediate said center member and said semiconductor chip, said interface material directly contacting said center member and said chip without intervening elements between said interface material and said center member, and said interface material and said chip; said interface material being selected from the group of low melting point alloys consisting of indium-bismuth-tin and indium bismuth; and wherein an elastomeric barrier extends between said opposite wall of said vapor chamber and a substrate mounting said semiconductor chip so as to sealingly encompass said semiconductor chip.