Patent ID: 8064284

Claim:
A method of decoding a memory address in non-Flash re-writeable non-volatile comprising: receiving a memo address for one or more multi-type memories; decoding the memo address using redetermined memo select parameters operative to determine if the decoded memory address indicates that a specific multiple-type memory is among the one or more multi-type memories; outputting a memory select value for the specific multiple-type memory when the decoded memory address indicates that the specific multiple-type memory is among the one or more multiple-type memories; and outputting a non-select value when the decoded memory address indicates that the specific multiple-type memory is not among the one or more multiple-type memories, wherein each multiple-type memory includes at least one memory plane in contact with and fabricated directly above a silicon substrate that includes a logic plane having control logic block circuitry and decode logic circuitry fabricated in the logic plane, each memory plane including at least one memory block electrically coupled with the control logic block circuitry, and wherein the decode logic circuitry is configured to decode the memory address and to output the memory select value or the non-select value.