Patent ID: 7988744

Claim:
A method of producing capacitor structure comprising: arranging a first layer first polarity conducting strip and a first layer second polarity conducting strip on a first layer of an integrated circuit chip such that the first layer second polarity conducting strip is arranged adjacent to and spaced apart from the first layer first polarity conducting strip, and the first layer first polarity conducting strip and the first layer second polarity conducting strip are arranged as respective piecewise “S” shaped paths; arranging a second layer first polarity conducting strip and a second layer second polarity conducting strip on a second layer of the integrated circuit chip such that the second layer second polarity conducting strip is arranged adjacent to and spaced apart from the second layer first polarity conducting strip, the second layer first polarity conducting strip and the second layer second polarity conducting strip are arranged as respective piecewise “S” shaped paths, the second layer second polarity conducting strip is arranged overlying and electrically separated from the first layer first polarity conducting strip, and the second layer first polarity conducting strip is arranged overlying and electrically separated from the first layer second polarity conducting strip; electrically connecting the first layer first polarity conducting strip with the second layer first polarity conducting strip; and electrically connecting the first layer second polarity conducting strip with the second layer second polarity conducting strip.