Patent ID: 7772632

Claim:
A memory array comprising: a plurality of memory cells, individual ones of the memory cells comprising: first and second transistors, each of the first and second transistors respectively comprising a gate, a channel region, and a pair of source/drain regions; the gate of the first transistor and the gate of the second transistor each being within a respective opening formed in semiconductive material, one of the pair of source/drain regions of the first transistor and one of the pair of source/drain regions of the second transistor being laterally intermediate the gates of the first and second transistors and being shared by the first and second transistors, each of the other of the pair of source/drain regions of each of the first and second transistors being laterally outward of their respective gate; a conductive data line elevationally outward of the gate of the first transistor and the gate of the second transistor, the conductive data line being electrically connected with the other of the pair of source/drain regions of the first transistor and with the other of the pair of source/drain regions of the second transistor; and a charge storage device electrically connected with the shared source/drain region.