Patent ID: 8077522

Claim:
A memory comprising: a memory array, comprising a target cell, which provides a sense current, and a first adjacent cell, which provides a source current; a sense unit; and a biasing and shielding circuit, coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises: a first transistor having a gate coupled to a biasing voltage, a first terminal coupled to the sense unit; a second transistor having a gate coupled to the biasing voltage, a first terminal coupled to a first potential; and a capacitor coupled to the sense unit and the first transistor, wherein, the sense unit senses a sense voltage, which is hold by the capacitor, on a sense node and the biasing and shielding circuit prevents the sense current from the influence of the source current, wherein: the first transistor further comprises a second terminal coupled to a source of the target cell, the first transistor is turned on based on the bias voltage so as to bias the source of the target cell to a second bias voltage, and the first transistor further provides the sense current to charge the capacitor so as to establish the sense voltage on the sense node; and a second transistor further comprises a second terminal coupled to a source of the first adjacent cell and the second transistor is turned on based on the bias voltage so as to bias the source of the target cell to the second bias voltage.