Patent ID: 7447955

Claim:
A test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, comprising: a logical comparator for comparing each of data contained in said data strings read out of said memory-under-test with an expected value generated in advance; a data error counting section for counting a number of data inconsistent with said expected value; a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in said data strings of said memory-under-test to be classified into the class; comparing sections for comparing each of said plurality of upper limit values stored in said plurality of registers with a counted value of said data error counting section; and a classifying section for classifying said memory-under-test into the class corresponding to said register storing said upper limit value that is greater than said counted value, wherein said logical comparator compares data outputted out of said memory-under-test, which includes a plurality of bits per cycle, with logical values set in advance, for each of the plurality of bits, and said test apparatus further comprises a timing detecting section for detecting timing when values of the bits change based on a ratio of a number of times when each of the values of the bits coincides with each of the logical values set in advance to a number of times when the values of the bits have been compared with the logical values set in advance, and wherein said classifying section detects a failure of said memory-under-test when said counted value exceeds said upper limit value which is a maximum number of errors in said data string correctable by said error correcting code.