Patent ID: 8129841

Claim:
A semiconductor device, comprising: a substrate having a non-wettable surface at a first level; a lead formed over the substrate wherein a portion of the lead forms a lead interconnect site having a width equal to a width of the lead; a mask layer formed over the substrate with a surface at a second level different from the first level and an opening over the lead interconnect site and over a portion of the substrate; a semiconductor die; and a bump formed between the semiconductor die and lead interconnect site, the bump having: a first profile as seen in a sectional view taken transverse to the lead, the first profile having a tapered form within the opening of the mask layer such that the first profile has a first width at the first level substantially equal to the width of the lead interconnect site and a second width at the second level greater than the first width by nature of the tapered form to create a void with respect to the opening of the mask layer over the portion of the substrate due to the non-wettable surface, the first profile contacting the mask layer at the second level and the lead interconnect site at the first level, and a second profile as seen in a sectional view taken parallel to the lead, the second profile further having a length at the first level different from the first width of the first profile and equal to a length of the opening in the mask layer in a direction parallel to the lead.