Patent ID: 7355465

Claim:
A delay circuit, comprising: a signal generator having a control terminal for receiving a trigger signal and having an output terminal for outputting a signal when receiving the trigger signal with a pre-determined characteristic; a delay component having an input terminal for receiving the signal outputted by the signal generator and having an output terminal for generating an output signal delayed with a time delay corresponding to the time the delay component received the signal outputted by the signal generator; and a feedback circuit connecting the output terminal of the delay component to the control terminal of the signal generator, wherein the feedback circuit of the delay circuit comprises a multiplexer comprising: a first input terminal connected to the output terminal of the delay component, wherein the first input terminal of the multiplexer of the feedback circuit is directly connected to the output terminal of the delay component; a second input terminal fed by an input signal; and an output terminal connected to the control terminal of the signal generator.