Patent ID: 8095776

Claim:
A data processing system comprising: a first host device adapted to provide first data, an endian setting command for setting an interface to operate as a little endian interface, and an address assigned to the endian setting command, the first host device providing the first data in a little endian format; a second host device adapted to provide second data, an endian setting command for setting the interface to operate as a big endian interface, and the address, the second host device providing the second data in a big endian format; and a display control driver including: an interface coupled to the first host device and the second host device, the interface adapted to receive the first data and the second data, the endian setting command to set the interface to operate as one of the big endian interface or the little endian interface and the address from the first host device and the second host device, and a command register adapted to store the endian setting command when the address is supplied from the first host device or the second host device, wherein a high-order bit portion of the endian setting command is 0000000X, where X is 0 when setting the little endian interface, and where X is 1 when setting the big endian interface, wherein a low-order bit portion of the endian setting command is 0000000Y, where Y is 0 when setting the little endian interface, and where Y is 1 when setting the big endian interface, wherein a high-order bit portion of the address is 00000110, and wherein a low-order bit portion of the address is 00000110.