Patent ID: 8787352

Claim:
A serial data receiver comprising: a plurality of channels each having a serial bit rate operating range, wherein each of the plurality of channels is operable to receive a serial data signal and operate at the serial bit rate operating range, and wherein a first serial bit rate operating range of a first channel of the plurality of channels exceeds a second serial bit rate operating range of a second channel of the plurality of channels; a set of first conductors that distribute a first and a second clock signal, generated respectively by a first and a second phase-locked loop circuitry, to the second channel; a second conductor that distributes the second clock signal to the first channel, wherein the first clock signal is suitable for a third serial bit rate operating range and the second clock signal is suitable for a fourth serial bit rate operating range, and wherein the fourth serial bit rate operating range exceeds the third serial bit rate operating range; and circuitry for allowing the second channel to select the first or the second clock signal for use by the second channel.