Patent ID: 7043707

Claim:
A simulation result verification method used for LSI designing, wherein based on: a simulation result that is obtained by simulating a LSI design data and that represents a relationship between a time and an output state at each of a plurality of nodes of a semiconductor integrated circuit, and condition information specifying a condition for the output state in a period between times t 1 and t 2 of one of said plurality of nodes, determining whether the output state in the period between the times t 1 and t 2 of the one node in the simulation result agrees with the output state according to the condition information, wherein the given time t in the simulation result is any time within the period between the times t 1 and t 2 in the simulation result, the output state is a voltage, and the voltage at the given time t is determined by V=(Vb−Va)/(tb−ta)×t+Va−(Vb−Va)/(tb−ta) ×ta, and wherein the time ta is before the time t and the time tb is after the time t, and Va is the voltage of the output state at time ta, and Vb is the voltage of the output state at time tb.