Patent ID: 8450778

Claim:
A semiconductor device comprising: first and second interconnect structures in first and second columns, respectively, of an array having at least one row and at least two columns, the first and second interconnect structures being in a first row, each of the first and second interconnect structures comprising: a first reference voltage node, a first power supply node, first, second, third, and fourth conductors coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells, the first reference voltage node of each interconnect structure providing a respectively separate reference voltage to a bit cell corresponding to said interconnect structure, none of the first, second, third, and fourth conductors being connected to a corresponding conductor in the other interconnect structure, the first reference voltage node of each interconnect structure being switchable between at least two voltage values; and fifth and sixth conductors coupled to the first power supply node and to each other and formed at the first and second layers, respectively, the first power supply node of each respective interconnect structure providing a respectively separate power supply voltage to a bit cell corresponding to said respective interconnect structure, neither of the fifth and sixth conductors of each respective interconnect structure being connected to a corresponding conductor in the other interconnect structure, the first power supply node of each interconnect structure being switchable between at least two voltage values; wherein the second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer; wherein the interconnect structure in each column is coupled to a single reference voltage.