Patent ID: 8850225

Claim:
A cryptographic processor, comprising: an ingress section, comprising: an input buffer to receive an input data stream; and a first configurable controller to: (1) align the input data stream; (2) insert data into the input data stream; and (3) remove data from the input data stream; an cipher engine receiving the processed input data stream from the first configurable controller and encrypting the processed input data stream from the first configurable controller; an authentication section, comprising: a second configurable controller to: (1) align the input data stream; (2) insert data into the input data stream; and (3) remove data from the input data stream; an authentication engine receiving the processed input data stream from the second configurable controller and authenticating the processed input data stream; an egress section, comprising: a third configurable controller to: (1) align the received input data stream; (2) insert data into the input data stream; and (3) remove data from the input data stream; an output buffer to receive the processed input data stream from the third configurable controller; and a programmable microcontroller, separate from the first, second and third configurable controllers, that programs the first, second and third configurable controllers.