Patent ID: 8580663

Claim:
A process of forming an integrated circuit (IC) comprising the steps of: forming a source dielectric layer on a top surface of a well region; forming an implanted region in an upper portion of said source dielectric layer by a process of implanting an set of dopant atoms into said source dielectric layer such that less than 10 percent of said dopant atoms pass through said source dielectric layer into said well region using a gas cluster ion beam (GCIB) process, a molecular ion implantation process, or an atomic ion implantation process; and forming diffused regions of between 5 nm and 20 nm deep by a process of heating said IC such that a portion of said dopant atoms diffuse from said implanted region into top regions of said well using a spike anneal or a laser anneal, wherein said diffused region has an average doping dose above 10 14 cm −2 .