Patent ID: 7340699

Claim:
A semiconductor integrated circuit electrostatic discharge analysis apparatus comprising: a resistance network generation unit configured to generate a resistance network as a power supply interconnect equivalent circuit by using an interconnect pitch, an interconnect width and a sheet resistance of a power supply interconnect, in an entire logic cell region of a semiconductor LSI circuit; a protection network generation unit configured to generate an electrostatic discharge protection network including pads and protection elements, which are placed in an I/O cell region of a semiconductor LSI circuit, connected to the resistance network; and an analysis unit configured to calculate an inter-pad voltage between the pads when an electrostatic discharge equivalent current flows between the pads, in a design stage of I/O placement carried out before arranging logic cells; wherein the resistance network generation unit comprises: a logic cell region determination unit to arrange the logic cell region; a grid generation unit generating grids of the resistance network with a horizontal grid interval and a vertical grid interval in the logic cell region; and a combined resistance deployment unit deploying horizontally combined resistance along the horizontal line of the grids, and vertically combined resistance along the vertical line of the grids.