Patent ID: 7669028

Claim:
A memory controller, comprising: (i) an asynchronous buffer configured to receive data at a first clock frequency and send data at a second clock frequency; (ii) command control logic configured to select, for processing, a command from one or more lists of commands in response to receiving a request signal, and issue a valid signal indicating the command is available for processing; and (iii) a data flow controller configured to request the command from the command control logic by asserting the request signal at a first time, initiate transfer of data associated with the command into the asynchronous buffer in response to receiving the valid signal by asserting a move signal, receive an acknowledge signal indicating that the data associated with the command has been transferred into the asynchronous buffer, assert a launch signal to transfer the data associated with the command out of the asynchronous buffer, and to request data for a next command, assert the request signal at a second time wherein a time period between receiving the valid signal for the command and the second time is shorter than a first time period, wherein the first time period is a sum of a time period required to assert the move signal for the command and a time period to acknowledge that the data associated with the command has been moved.