Patent ID: 7707449

Claim:
A semiconductor device comprising: a multi-rate data path, wherein the multi-rate data path exhibits at least a first rate of operation and a second rate of operation, wherein the multi-rate data path includes: a first register circuit; a second register circuit, wherein an output of the first register circuit is electrically coupled to an input of the second register circuit via a combinational logic block, wherein the second register circuit includes a flip-flop and a multiplexer, and wherein the input to the flip-flop is electrically coupled to a first input of the multiplexer and the output of the flip-flop is electrically coupled to a second input of the multiplexer; and a control circuit, wherein the control circuit is operable to modify a rate at which the multi-rate data path operates by selecting the first input of the multiplexer during the second rate of operation, and selecting the second input of the multiplexer during the first rate of operation.