Patent ID: 7667273

Claim:
A semiconductor device comprising: a substrate; a p-channel MIS transistor that includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and having a first sub-layer provided in the first gate insulating film and a second sub-layer provided in the first gate electrode, each of the first and second sub-layers containing a 13-group element, the total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer; and an n-channel MIS transistor that includes: a p-type semiconductor layer formed on the substrate; second source/drain regions being formed in the p-type semiconductor layer and being separated from each other; a second gate insulating film being formed on the p-type semiconductor layer between the second source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a second gate electrode formed above the second gate insulating film; and a second interfacial layer being formed at an interface between the second gate insulating film and the second gate electrode, and containing a 15-group element.