Patent ID: 8365049

Claim:
An integrated circuit comprising: a first plurality of flip-flops, each flip-flop adapted to: receive a corresponding data-input signal and a corresponding clock-input signal; provide a corresponding data-output signal; and use less energy when the corresponding clock-input signal is constant than when the corresponding clock-input signal is not constant; and an error-detection module connected to receive the data-output signals of the first plurality of flip-flops, wherein the error-detection module is adapted to: generate a first error-detection code based on a first set of values of the received data-output signals of the first plurality of flip-flops; and process (i) the first error-detection code and (ii) a second set of values of the received data-output signals of the first plurality of flip-flops to generate an error-detection signal indicating whether or not the error-detection module detected a soft error of a flip-flop in the second set of values of the received data-output signals.