Patent ID: 7830716

Claim:
A device comprising: a sense amplifier comprising a first input and a second input; a global bit line to communicate information to the first input of the sense amplifier; and a plurality of NAND string modules, each one of the plurality of NAND string modules respectively comprising the following corresponding elements: a first node to communicate information to the global bit line, a buffer, a first switch comprising a control node, a first data electrode coupled to an output of the buffer, and a second data electrode, the first switch being operable to communicate information between the first data electrode and the second data electrode in response to an asserted read signal at the control node during a read access; a plurality of data paths, each data path of the plurality of data paths respectively comprising the first node, a corresponding NAND string of a plurality of NAND strings, and the buffer connected in series between the corresponding NAND string and the first node to communicate information between the corresponding NAND string and the first node, wherein a first data path of the plurality of data paths comprises the first node, the buffer, and a first NAND string of the plurality of NAND strings, and a second data path of the plurality of data paths comprises the first node, the buffer, and a second NAND string of the plurality of NAND strings.