Patent ID: 7964917

Claim:
A semiconductor device comprising: a first MIS (metal-insulator semiconductor) transistor including: a first gate insulating film formed on a first area of a semiconductor substrate; a first gate electrode formed on the first gate insulating film; a first L-shaped sidewall covering a side of the first gate electrode and part of the semiconductor substrate to have an L-shaped cross-sectional shape; and a first source/drain region formed laterally outward of a part of the first area covered with the first gate electrode and the first L-shaped sidewall; a second MIS transistor including: a second gate insulating film formed on a second area of the semiconductor substrate; a second gate electrode formed on the second gate insulating film; a second L-shaped sidewall covering a side of the second gate electrode and part of the semiconductor substrate to have an L-shaped cross-sectional shape; a first outer sidewall formed on the second L-shaped sidewall; and a second source/drain region formed laterally outward of a part of the second area covered with the second gate electrode, the second L-shaped sidewall, and the first outer sidewall; and a liner insulating film covering the first MIS transistor and the second MIS transistor and applying stress to a channel region of the first MIS transistor along the gate length direction of the first gate electrode, wherein no outer sidewall is formed on the first L-shaped sidewall, the minimum thickness of a first part of the liner insulating film located on the first source/drain region in a direction vertical to a surface of the semiconductor substrate is less than the minimum thickness of a second part of the liner insulating film located on the second source/drain region in the direction vertical to the surface of the semiconductor substrate, and the second part is made of a same insulating material as the first part and is a single layer.