Patent ID: 7181593

Claim:
An integrated circuit active memory device fabricated on a single semiconductor substrate, the active memory device comprising: a memory device having a data bus containing a plurality of data bus bits; an array of processing elements with each processing element coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements; an array control unit coupled to the processing elements in the array, the array control unit being operable to generate and to couple respective sets of the processing element instructions to the processing elements responsive to each of a plurality of array control unit commands applied to a command input of the array control unit; a memory device control unit coupled to the memory device, the memory device control unit being operable to generate and to couple respective sets of memory commands to the memory device responsive to each of a plurality of memory device control unit commands applied to a command input of the memory device control unit; and a command engine coupled to the array control unit and the memory device control unit, the command engine being operable to couple to the array control unit respective sets of the array control unit commands and to couple to the memory device control unit respective sets of the memory device control unit commands responsive to respective task commands applied to a task command input of the command engine.