Patent ID: 7366274

Claim:
A bidirectional shift register comprising: a former stage multiplexer comprising: a first transistor having a source for receiving a signal and a gate for receiving a forward clock; a second transistor having a source coupled with a drain of the first transistor, a gate for receiving a forward control signal, the second transistor being of a same type as the first transistor; a third transistor having a drain coupled with a drain of the second transistor, a gate for receiving a backward control signal, the third transistor being of the same type as the first transistor; and a fourth transistor having a drain coupled with a source of the third transistor, a gate for receiving the forward clock, the fourth transistor being of the same type as the first transistor; a former stage full-swing shift register comprising: a fifth transistor having a gate coupled with the drain of the second transistor, a source for receiving a backward clock, the fifth transistor being of the same type as the first transistor; a sixth transistor having a source coupled with a drain of the fifth transistor, a gate coupled with the gate of the first transistor, a drain for coupling with a first power source, the sixth transistor being of the same type as the first transistor; and a former stage capacitor having a first end coupled with the gate of the fifth transistor and a second end grounded; a latter stage multiplexer comprising: a seventh transistor having a source for receiving a signal and a gate for receiving the backward clock, the seventh transistor being of the same type as the first transistor; an eighth transistor having a source coupled with a drain of the seventh transistor, a gate for receiving the backward control signal, the eighth transistor being of the same type as the first transistor; a ninth transistor having a drain coupled with a drain of the eighth transistor, a gate for receiving the forward control signal, the ninth transistor being of the same type as the first transistor; and a tenth transistor having a drain coupled with a source of the ninth transistor, a gate for receiving the backward clock, a source coupled with the drain of the fifth transistor of the former stage full-swing shift register, the tenth transistor being of the same type as the first transistor; and a latter stage full-swing shift register comprising: an eleventh transistor having a gate coupled with the drain of the eighth transistor, a source for receiving the forward clock, a drain coupled with the source of the fourth transistor of the former stage multiplexer, the eleventh transistor being of the same type as the first transistor; a twelfth transistor having a source coupled with the drain of the eleventh transistor, a gate coupled with the gate of the seventh transistor, a drain for coupling with the first power source, the twelfth transistor being of the same type as the first transistor; and a latter stage capacitor having a first end coupled with the gate of the eleventh transistor and a second end grounded.