Patent ID: 7373490

Claim:
A machine readable medium having stored thereon a plurality of control signals and when accessed by a processor, causing said processor to: access a first set of bits as representing an instruction of a first plurality of instructions, said first plurality of instructions including a packed data instruction, a scalar floating point instruction, and a transition instruction to be executed between said packed data instruction and said scalar floating point instruction; if said first set of bits represents the packed data instruction then generate a first set of control signals to cause said processor to execute the packed data instruction on packed data contents of a storage representing a programmer visible register file, wherein said storage representing the programmer visible register file is operated as a flat register file while executing said packed data instruction; if said first set of bits represents the scalar floating point instruction then generate the first set of control signals to cause said processor to execute the scalar floating point instruction on floating point contents of the storage representing the programmer visible register file, wherein said programmer visible register file is operated as a stack while executing said scalar floating point instruction; and if said first set of bits represents the transition instruction then generate the first set of control signals to cause said processor to alter a tag data to indicate that the stack of the programmer visible register file is empty responsive to executing said transition instruction between execution of said packed data instruction and said scalar floating point instruction.