Patent ID: 8324663

Claim:
An apparatus comprising: a substrate; a MOS transistor having: a first portion of an active area formed in the substrate that includes a first source/drain region and a second source/drain, wherein the first portion is substantially rectangular; and a first gate formed over the substrate between the first and second source/drain regions; and a dual one-time programmable (OTP) cell having: a second portion of the active area formed in the substrate that includes a third source/drain region and a fourth source/drain, wherein the third source/drain region is electrically coupled to the second source/drain region, and wherein the second portion is substantially rectangular; a third portion of the active area formed in the substrate that includes a fifth source/drain region and a sixth source/drain, wherein the fifth source/drain region is electrically coupled to the second source/drain region, and wherein the second portion is substantially rectangular, and wherein the third portion is substantially parallel to the second portion to one another, and wherein each of the second and third portions are formed adjacent to opposite ends of the first portion; a second gate formed over the substrate between the third and fourth source/drain regions; and a third gate on the substrate between the fifth and sixth source/drain regions.