Patent ID: 8643426

Claim:
A voltage level shifter, comprising: an input node and an output node; an input circuit with an input inverter coupled to the input node, wherein the input circuit has a pull-down transistor with a gate electrode coupled to a first node of the input inverter and a first pull-up control transistor with a gate electrode coupled to an opposite second node of the input inverter, and wherein source electrodes of the pull-down transistor and the first pull-up control transistor are coupled to a low voltage reference; a transient path connectivity limiter with a pull-down transient connectivity limiter transistor and a pull-up transient connectivity limiter transistor, wherein the pull-down transient connectivity limiter transistor has a gate electrode coupled through a first capacitor to the first node of the input inverter and a source electrode of the pull-down transient connectivity limiter transistor is coupled to a drain electrode of the pull-down transistor, and wherein the pull-up transient connectivity limiter transistor has a gate electrode coupled through a second capacitor to the second node of the input inverter and a source electrode of the pull-up transient connectivity limiter transistor is coupled to a drain electrode of the first pull-up control transistor, wherein the transient path connectivity limiter further includes a rapid response pull-down gate control transistor having a source electrode coupled to the gate electrode of the pull-down transient connectivity limiter transistor, a drain electrode coupled to a primary voltage supply node and a gate electrode coupled to a secondary voltage supply node, wherein in operation the primary voltage supply node is at a higher voltage than the secondary voltage supply node; and an output circuit having a pull-up transistor with source and drain electrodes coupled between the primary voltage supply node and a drain electrode of the pull-down transient connectivity limiter transistor, wherein the drain electrode of the pull-up transistor is coupled to the output node and a gate electrode of the pull-up transistor is coupled to a drain electrode of the pull-up transient connectivity limiter transistor, and wherein the output circuit further includes a second pull-up control transistor having source and drain electrodes coupled between the primary voltage supply and the drain electrode of the pull-up transient connectivity limiter transistor and a gate electrode of the second pull-up control transistor is coupled to the drain electrode of the pull-down transient connectivity limiter transistor.