Patent ID: 7757040

Claim:
An apparatus for interfacing a processor employing a first command format and a memory employing a second command format, the apparatus comprising: a translation circuit adapted to couple a processor employing a first command format to a memory employing a second command format, the translation circuit: receiving a memory system command from the processor in the first command format, the memory system command in the first command format comprising a memory command, an associated address and data protocols for the memory command, and wherein the first command format comprises an extreme data rate (XDR) command format; automatically converting the memory system command in the first command format to a memory system command in a second command format, the second command format comprising a double data rate (DDR) format, and wherein the automatically converting comprises adjusting at least one of the memory command or the data protocols for the memory command of the memory system command in the first command format in converting to the memory system command in the second command format; and wherein the automatically converting comprises selecting address bits from the associated address in the XDR format for use in the associated address in the DDR format, wherein the selecting address bits includes referencing a DDR size configuration register to determine which row address bits and column address bits of the associated address in the XDR format to include in the associated address of the DDR format.