Patent ID: 7890721

Claim:
An electronic device comprising: a memory device having a memory array with memory cells grouped in erase blocks such that data in the memory cells can be erased on a block basis; a protection register array in the memory device, the protection register array including: a plurality of protection registers, each of the protection registers having a plurality of bit locations and an address in the memory device, a protection register being a storage area in the memory device that is separate from the erase blocks; and a set of bit locations in the protection register array arranged to store a lock status word, the lock status word being a multiple bit word including an individual lock status for each of the protection registers, the set of bit locations accessible in the memory device at an access address, the access address being a single address for the lock status word, the access address of the lock status word being different from the address of each protection register; and a circuit that stores and operatively accesses a lock status in the lock status word such that the circuit operatively determines a lock status of a specified protection register of the plurality of protection registers prior to applying a program pulse of a command sequence for operating on the protection register array, the command sequence including an address of the specified protection register of the plurality of programmable registers such that the circuit operatively matches the address of the specified protection register to a corresponding bit in the lock status word decoded from a verify function applied to read the lock status word at the single access address prior to applying the program pulse.