Patent ID: 6965257

Claim:
A level discrimination circuit comprising: (a) a first offset compensation circuit including: a first peak detection circuit detecting a first peak value of a first signal; a first summing circuit generating a first sum value according to the first peak value and a second signal; a second peak detection circuit detecting a second peak value of the second signal; and a second summing circuit generating a second sum value according to the second peak value and the first signal; and (b) a second offset compensation circuit including: a third peak detection circuit detecting a third peak value of the second sum value; a third summing circuit generating a third sum value according to the third peak value and the first sum value; a fourth peak detection circuit detecting a fourth peak value of the second sum value; and a fourth summing circuit generating a fourth sum value according to the fourth peak value and the first sum value; and (c) a comparator generating an output signal according to the third and the fourth sum values.