Patent ID: 8082383

Claim:
A semiconductor memory device comprising: a memory cell array which includes a nonvolatile memory cell; a power source circuit which includes a first register and generates a voltage to be used in at least any one of write, erase and read of data with respect to the memory cell; a sense amplifier which includes a second register, reads data from the memory cell and amplifies the read data; a control circuit which includes a third register and controls operation of the power source circuit and the sense amplifier; and a processor which controls operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction, and outputs the instruction to the first, second, and third registers, the instruction being stored in the first, second, and third registers, the control operations decoding the instruction stored in the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding, when the processor outputs an update enable signal to the third register, wherein when an operation of the power source circuit and the sense amplifier is based on control of the processor, the register stores the instruction in response to the update enable signal, when the operation of the power source circuit and the sense amplifier is not based on the control of the processor, the register is set in a reset state.