Patent ID: 7508902

Claim:
A shift register, comprising a plurality of stage circuits, wherein each of the stage circuits includes: a shift circuit, for receiving an input signal and providing an output signal obtained through logic calculation and delaying of the input signal, the shift circuit includes: a first three-state inverter, having an input end, a first control end, a second control end and an output end, for receiving the input signal through its input end, receiving a first clock signal through its first control end, and receiving a second clock signal through its second control end; a first inverter, having an input end and an output end, electrically connected to the output end of the first three-state inverter through its input end; a second three-state inverter, having an input end, a first control end, a second control end and an output end, electrically connected to the output end of the first inverter through its input end, for receiving a first control signal through its first control end, for receiving a second control signal through its second control end, and electrically connected to the input end of the first inverter through its output end; a third three-state inverter, having an input end, a first control end, a second control end and an output end, electrically connected to the output end of the second three-state inverter through its input end, for receiving the second clock signal through its first control end, for receiving the first clock signal through its second control end; a second inverter, having an input end and an output end, electrically connected to the output end of the third three-state inverter through its input end, wherein the output signal is produced according to the output of the second inverter; and a fourth three-state inverter, having an input end, a first control end, a second control end and an output end, electrically connected to the output end of the second inverter through its input end, for receiving the first control signal through its first control end, for receiving the second control signal through its second control end, and electrically connected to the input end of the second inverter through its output end; and each of the stage circuits, except the first one, further including: a logic circuit, for producing a control signal according to an internal signal of the containing stage circuit and replacing a clock signal required during the operation of the corresponding shift circuit with the control signal, the logic circuit includes: an XNOR gate, having a first input end, a second input end and an output end, electrically connected to the output end of the second inverter of the stage circuit through its first input end, and electrically connected to the output end of the first inverter through its second input end, outputting the first control signal; and a third inverter, for receiving the first control signal and outputting the second control signal.