Patent ID: 7467254

Claim:
A semiconductor memory device, comprising: at least two memory banks; wherein the semiconductor memory device is configured such that at least two processor units can carry out read accesses and write accesses to the memory banks and, by means of an inhibit command communicated by one of the processor units, the write access to the inhibited memory bank by at least one of the processor unit which has communicated the inhibit command and the other processor unit to the inhibited memory bank is prevented at least occasionally; a control circuit adapted to set, based on an inhibit command, which of the at least two processor units is prioritized, in case of an access collision, when the two processors attempt to access the same memory bank; and a register circuit, which can be configured with the aid of the inhibit command in such a way that the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally, wherein the register circuit is further configured with an item of information regarding which of the processor units is prioritized for an access in the case of an access collision.