Patent ID: 8275584

Claim:
A method of developing a statistical model for integrated circuits, the method comprising: creating a set of test patterns of test devices comprising metal-oxide-semiconductor (MOS) devices, resistors, capacitors, memory cells, wires, or a combination thereof, each one of the set of test patterns being on a semiconductor die; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from the set of intra-die data if the sigma_local is appointed as the first sigma and the set of inter-die data if the sigma_global is appointed as the first sigma, the first sigma being a single numerical value; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.