Patent ID: 8704696

Claim:
An analog-to-digital (AD) conversion circuit comprising: a reference signal generation unit configured to generate a reference signal that increases or decreases with the passage of time; a comparison unit configured to compare an analog signal serving as an AD conversion target with the reference signal and end a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal; a clock signal generation unit configured to have an oscillation circuit formed by n (n is an odd number greater than or equal to 3) delay units and including a first path in which a signal is transferred through each of the n delay units and a second path in which a signal is transferred by bypassing some of the n delay units, and output a lower-order phase signal including a plurality of signals output from the plurality of delay units; a latch unit configured to latch the lower-order phase signal at a timing related to the end of the comparison process; a higher-order count unit including a first counter circuit configured to acquire a higher-order count value by performing a count operation using a signal output from any one of the delay units arranged between two delay units positioned at both ends of the second path and arranged on the first path as a first count clock signal; a calculation unit configured to detect a change position of a logic state in a signal group including the plurality of signals constituting the lower-order phase signal latched in the latch unit in order to detect a state of the lower-order phase signal defined based on the count clock signal of the first counter circuit, and generate a lower-order count signal based on the detected change position; and a lower-order count unit including a second counter circuit configured to acquire a lower-order count value by performing a count operation using the lower-order count signal as a second count clock signal, wherein digital data corresponding to the analog signal is output.