Patent ID: 8178928

Claim:
An intermediate structure formed during the manufacture of a memory device, comprising: a first gate pattern having a first sidewall on a semiconductor substrate; a second gate pattern on the semiconductor substrate that is spaced apart from the first gate pattern, the second gate pattern having a second sidewall that faces the first sidewall, wherein the first and second sidewalls define a first gap region therebetween; a source/drain region in the semiconductor substrate between the first and second gate patterns; an etch stop layer on the first sidewall of the first gate pattern and on the second sidewall of the second gate pattern, the etch stop layer on the first sidewall and the etch stop layer on the second sidewall defining a second gap region therebetween; a unitary dielectric layer that consists of a single dielectric material and that has a planar upper surface on the first and second gate patterns and the etch stop layer and in the second gap region; a mask layer on the dielectric layer, the mask layer having an opening above the dielectric layer, the opening having a width that is less than the width of the second gap region; a preliminary contact hole in the dielectric layer beneath the opening, the preliminary contact hole having a width that is less than the width of the second gap region, wherein the dielectric layer forms the entirety of the sidewalls of the preliminary contact hole, and wherein the preliminary contact hole does not expose the source/drain region in the semiconductor substrate.