Patent ID: 7987437

Claim:
A method in a computer-aided design system for generating a functional design structure of an integrated circuit, said method comprising a processor of a computer system executing code that performs the functions of: sending a first request for a first bus grant to deliver a first data to a data bus connecting a source device and a destination device; receiving the first bus grant to deliver said first data to the data bus in response to said first request; determining whether a bandwidth of said data bus allocated to the first bus grant will be filled by said first data, wherein said bandwidth is a number of clock cycles allocated to the first bus grant; in response to determining that the bandwidth of said data bus allocated to the first bus grant will not be filled by said first data: appending a second data to said first data to provide combined data; determining whether said delivering of the combined data to said data bus during said first bus grant will violate a latency constraint of said data bus; responsive to determining that said delivering of the combined data to said data bus during said first bus grant will violate a latency constraint of said data, delivering only said first data to said data bus during said first bus grant; responsive to determining that said delivering of the combined data to said data bus during said first bus grant will not violate a latency constraint of said data, delivering the combined data to said data bus during said first bus grant; and delivering only said first data to said data bus during said first bus grant when the bandwidth of said data bus allocated to the first bus grant will be filled by said first data.