Patent ID: 7173866

Claim:
A circuit for controlling data output and data strobe signal generation in a DDR memory device, comprising: an internal clock generating unit for generating first and second internal clock signals; an enable signal generating unit for generating first to fourth enable signals according to a CAS latency and the first internal clock signal by receiving an external clock signal; a first pulse generating unit for outputting the second internal clock signal as a first pulse signal while the first enable signal is supplied and outputting the first internal clock signal as a second pulse signal while the second enable signal is supplied, the first and the second pulse signals are used to control the data output; and a second pulse generating unit for outputting the first internal clock signal as a fourth pulse signal while the fourth enable signal is supplied and outputting the second internal clock signal as a third pulse signal while the third enable signal is supplied, the third and the fourth pulse signals are used to control the data strobe signal generation.