Patent ID: 8503210

Claim:
A content addressable memory (CAM), comprising: a precharge component including a first input, a second input, and an output; and a first transistor coupled to the precharge component, a matchline of the CAM and a rail voltage; wherein when the first and second inputs of the precharge component are in a first state, the output of the precharge component is in a second state and the first transistor is activated to connect the matchline to the rail voltage, and when the first input of the precharge component is in the second state, the output of the precharge component is in the first state and the first transistor is not activated; an evaluate component including a first input, a second input, and an output; and a second transistor coupled to the evaluate component, the matchline of the CAM and a reference voltage; wherein when the first and second inputs of the evaluate component are both in the first state, the output of the evaluate component is in the second state and the second transistor is not activated, and when the first input of the evaluate component is in the second state, the output of the evaluate component is in the first state and the second transistor is activated to connect the matchline to the reference voltage; and an inverter having the matchline as an input; a third transistor coupled to the rail voltage, the matchline and the output of the inverter; a fourth transistor coupled to the output of the precharge component and the matchline; and a fifth transistor coupled to the output of the inverter, reference voltage and the fourth transistor; wherein when the precharge component output is in the first state, the third transistor is not activated and the fourth and fifth transistor are activated connecting the matchline to the reference voltage, and when the precharge component output is in the second state, the third transistor is activated connecting the matchline to the rail voltage and the third and fourth transistors are not activated.