Patent ID: 8094510

Claim:
An integrated circuit, comprising: a multi-level memory array of memory cells having at least one layer of word lines and more than one layer of bit lines, each layer of bit lines includes a bit line group; at least one noise detection line associated with each layer of bit lines; a selection circuit that selects a selected bit line associated with a particular bit line group, and a selected noise detection line associated with said particular bit line group; and a bit line sensing circuit, said bit line sensing circuit senses a signal on said selected bit line and a signal on said selected noise detection line, said bit line sensing circuit includes a voltage sensing circuit; said voltage sensing circuit includes a first precharge circuit for precharging said selected noise detection line to an unselected word line bias voltage; and a second precharge circuit for precharging said selected bit line to a voltage other than the unselected word line bias voltage.