Patent ID: 7283398

Claim:
In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for minimizing leakage current when detecting states of memory cells comprising: determining a selected bit line that is associated with a column of memory cells; and biasing a group of word lines at a negative voltage to limit leakage current contributions from associated memory cells in said column of memory cells when performing a verify operation, wherein said memory cells are coupled to said group of word lines, and wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts, wherein said verify operation comprises an erase verify operation comprising: determining a selected memory cell in said column of memory cells, said selected memory cell associated with said selected bit line, and a selected word line that is not part of said group of word lines; and biasing said selected word line at approximately 3 volts; biasing said selected bit line at approximately 0.65 volts; and floating remaining bit lines.