Patent ID: 7170553

Claim:
An apparatus for processing an image, wherein the image includes a plurality of unit blocks each containing M×N pixels where M pixels are arranged in a horizontal direction and N pixels are arranged in a vertical direction, the apparatus comprising: a memory for storing the image data of each pixel in the plurality of unit blocks; a direct memory access controller for reading the image data from the memory by accessing the memory on a block-by-block basis by generating the addresses of the pixels in each unit block; and a plurality of image processing modules for receiving the image data of each unit block read based on the addresses generated by the direct memory access controller and sequentially transferred via a data bus, processing the image data of the unit block, and outputting the processed image data of the unit block, wherein the direct memory access controller sequentially generates the addresses of the pixels in one horizontal line in each unit block and thereafter generates the addresses of the pixels on another horizontal line immediately below said one horizontal line in the unit block, and repeats this operation to read the image data of the unit block, and the direct memory access controller sequentially reads the image data of the unit blocks in one horizontal line in the image and thereafter sequentially reads the image data of the unit blocks on another horizontal line immediately below said one horizontal line in the image, and repeats this operation to read the data of the image.