Patent ID: 8639461

Claim:
A circuit for digitizing jitter in a high speed digital signal, said circuit comprising: a comparator establishing a trigger point within a digital signal for jitter analysis by comparing an input signal to a phase locked loop to an output signal of said phase locked loop and outputting said digital signal; a reference signal generator receiving said digital signal from said comparator and generating an offset reference signal based on said digital signal; a measure delay circuit receiving said digital signal from said comparator and outputting a delayed digital signal based on said digital signal; a programmable unit receiving said offset reference signal from said reference signal generator and said delayed digital signal from said measure delay circuit, said programmable unit comprising flip flops and said flip flops transitioning when said offset reference signal crosses said delayed digital signal; a counter counting transitions of said flip flops during established time intervals to determine a frequency of said digital signal; a clock generator; an interval counter operatively connected between said clock generator and said counter, said clock generator supplying a clock signal to said interval counter and said interval counter establishing said time intervals based on said clock signal; a logic element operatively connected to said counter, said logic element calculating a period of said digital signal based on said frequency; a delay shift circuit operatively connected between said logic element and said measure delay circuit, said delay shift circuit providing a linearized delay for said jitter analysis based on said period of said digital signal, said measure delay circuit outputting said delayed digital signal from said digital signal based on said linearized delay, and said logic element repeating said counting of said transitions of said flip flops for different time intervals to generate a jitter histogram of said digital signal.