Patent ID: 7116743

Claim:
A digital phase lock loop comprising: a synchronization unit producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the clock signals having (i) a modified frequency over the frequency of the seed clock signal and (ii) a phase shift from each other; a digital control oscillator receiving the clock signals and producing an output signal in reference to a received signal; a phase-frequency detection unit in which a phase and frequency of an input signal is detected and compared with the output signal from the digital control oscillator, wherein the received signal pertains to any errors between the input signal and the output signal; a filter (i) coupled to the digital control oscillator and (ii) configured to filter out possible noises in the output signal, wherein the output signal comprises a digitally controlled clock signal; and a first divider coupled between the digital oscillator and the filter, wherein the output signal is scaled down in the first divider and further filtered in the filter to produce a digitally controlled clock signal.