Patent ID: 8456227

Claim:
A current mirror circuit, comprising: first and second insulated gate field effect transistors having a drain electrode, a source electrode and a gate electrode, the gate electrodes of the first and second insulated gate field effect transistors being connected to each other; wherein the first and second insulated gate field effect transistors are an enhancement mode insulated gate field effect transistor respectively, a third insulated gate field effect transistor having a drain electrode, a source electrode and a gate electrode, the source electrode of the third insulated gate field effect transistor being connected to the drain electrode of the first insulated gate field effect transistor, and the drain electrode of the third insulated gate field effect transistor being connected to the gate electrodes of the first and second insulated gate field effect transistors and a current input terminal; a fourth insulated gate field effect transistor having a drain electrode, a source electrode and a gate electrode, the gate electrode of the fourth insulated gate field effect transistor being connected to the gate electrode of the third insulated gate field effect transistor, the source electrode of the fourth insulated gate field effect transistor being connected to the drain electrode of the second insulated gate field effect transistor, and the drain electrode of the fourth insulated gate field effect transistor becoming a current output terminal, wherein the third and fourth insulated gate field effect transistors are a depletion mode insulated gate field effect transistor respectively; and a bias circuit configured to provide a bias voltage to the gate electrodes of the third and fourth insulated gate field effect transistors.