Patent ID: 6986074

Claim:
A system-on-chip (SOC) comprising: a plurality of circuit blocks, each responsive to a respective local clock signal; a system clock connected to said circuit blocks for providing a system clock signal thereto for functioning as the respective local clock signals; a power control manager connected to said circuit blocks for selectively providing a shutdown signal thereto; each circuit block comprising a shutdown circuit for preventing the system clock signal from functioning as the respective local clock signal after the circuit block receiving the shutdown signal provides a shutdown acknowledgment signal to said power control manager; said power control manager being connected to each shutdown circuit through a respective power down request line for providing the shutdown signal thereto, and through a respective power down acknowledgment line for receiving the shutdown acknowledgment signal therefrom, said power control manager comprising a first register connected to the respective power down request lines for storing data indicating logic states of the shutdown signals, and a second register connected to the respective power down acknowledgment lines for storing data indicating logic states of the shutdown acknowledgment signals; and a central processing unit connected to said power control manager for determining whether each circuit block is in an active state or an idle state by querying said first and second registers.