Patent ID: 7971165

Claim:
A verifying apparatus comprising: a merging unit that deletes a first flip-flop which is logically equivalent to a second flip-flop and merges the first flip-flop to the second flip-flop on a reference circuit and an implemented circuit respectively based on design data of the reference circuit and the implemented circuit which is logically equivalent to the reference circuit; and a matching unit that matches the second flip-flop which remains after the merge process on the reference circuit and the second flip-flop on the implemented circuit according to name checking whether the name of the second flip-flop on the reference circuit and the name of the second flip-flop on the implemented circuit are identical, after the merging unit deletes and merges the first flip-flop, and wherein the merging unit deletes and merges a plurality of the first flip-flops, among which is an upstream flip-flop having an output logic identical to an input logic of a downstream flip-flop.