Patent ID: 8424015

Claim:
A data processing system, comprising: a processor; and a memory coupled to the processor, wherein the processor comprises logic that operates to: generate a transaction checkpoint data structure in internal registers of the processor, wherein the transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction; execute the transaction, wherein the transaction comprises a first portion of code that is to be executed by the processor; receive an interrupt of the transaction while executing the transaction; store the transaction checkpoint data to a data structure in the memory of the data processing system in response to receiving the interrupt; execute a second portion of code, different than the first portion of code; and restore a state of the program registers using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction, wherein the data structure in the memory is an interrupt context record data structure for a program corresponding to the transaction, and wherein the transaction checkpoint data is stored in a first portion of the interrupt context record data structure, and wherein restoring a state of the program registers using the data structure in the memory of the data processing system comprises: restoring the program registers to a state corresponding to a state prior to executing the transaction based on the checkpoint data stored in the first portion of the interrupt context record data structure in the memory; and executing a transaction re-checkpoint instruction to generate a new transaction checkpoint data structure in the internal registers of the processor.