Patent ID: 7591659

Claim:
A method for forming a CMOS semiconductor wafer comprising: providing a semiconductor substrate; forming a dielectric layer overlying the semiconductor substrate; forming a gate layer overlying the dielectric layer; patterning the gate layer to form a gate structure including edges; forming a dielectric layer overlying the gate structure to protect the gate structure including the edges, the dielectric layer having a thickness of less than 40 nanometers; etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer; depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region; causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region; forming a second protective layer overlying surfaces including the silicon germanium material and an entirety of the gate structure to seal any impurities in the patterned gate layer, wherein the second protective layer is formed after the silicon germanium material is formed in the source region and the drain region; and performing an anisotropic etching process on the second protective layer to form spacer structures to seal the gate structure, wherein the spacer structures are formed after the silicon germanium material is formed in the source region and the drain region; and exposing a top surface of the gate structure while sealing the edges of the gate structure using the spacer structures, wherein the exposing occurs after formation of the spacer structures.