Patent ID: 7603603

Claim:
A configurable memory architecture with built-in testing mechanism integrated in said memory comprising: a Memory Core for storing data; a Decoder Section connected to said Memory Core for decoding addresses; an I/O Section connected to said Memory Core for bi-directional shifting of data; and a Control Block connected to said I/O Section and said Decoder Section for generating control signals and an internal clock; wherein said I/O Section and said Control Block are enhanced to be configurable for built-in testing in test mode comprising: a configurable Serial Interface connected to said Control Block for shifting in and out test data and test status; a configurable Test Address Generator within said I/O Section connected to said Decoder Section; a configurable Test Pattern Generator within said I/O Section for generating test patterns on address and/or data lines during Test mode; a Data Compressor for compressing Memory data output, the Data Compressor comprising a series chain of AND gates each gate receiving a bit of Memory data and a series chain of OR gates each gate receiving a bit of Memory data; a configurable Test Result Comparator in said I/O Section comprising a multiplexer receiving outputs of the series chain of AND gates and series chain of OR gates, the multiplexer operating to multiplex the received outputs with expected test data during Test mode to output a verified result.