Patent ID: 7493541

Claim:
A method of testing integrated circuits having built-in self-test circuitry and built-in self-repair circuitry, said method comprising the steps of: establishing a selectively variable stress condition in an integrated circuit die; performing a built-in self-test operation to detect faults in selectively designated memory space, including redundant memory, of said integrated circuit die; generating fault information relating to any faults detected by the built-in self-test operation; cumulatively storing the fault information; iteratively repeating the stress condition establishing step, the built-in self-test operation performance step, the fault information generation step, and the fault information cumulative storage step; and performing a built-in self-repair operation to reconfigure any faulty portions of the integrated circuit die as indicated by the cumulatively stored fault information from all iterations of the stress condition establishing step, the built-in self-test operation performance step, the fault information generation step, and the fault information cumulative storage step following completion of the last iteration.