Patent ID: 7173328

Claim:
An integrated circuit package comprising: a semiconductor integrated circuit die mounted with a packaging substrate having a plurality of active circuit elements formed therein, the circuit elements including clocking circuitry that is spatially separated from selected other on-chip circuit elements, wherein a space on the die between the clocking circuitry and the selected other on-chip circuit elements is occupied by intervening circuitry; a plurality of bonding pads formed on a top surface the die with at least some of the bonding pads being formed above active circuit elements of the die and being electrically connected with the clocking circuitry and the selected other on-chip circuit elements; and an intra-chip electrical connection between the clocking circuitry and the selected other on-chip circuit elements, the connection formed by a wire bonded electrical connection between two of the bonding pads associated with the clocking circuitry and the selected other on-chip circuit elements, wherein the wire-bonded electrical connection passes above the intervening circuitry and wherein the bonding pads are formed over at least one active circuit component of the die and wherein the wire bonded electrical connections between the clocking circuitry and the selected other on-chip circuit elements are selected having electrical path lengths configured to maintain synchronization between the clocking circuitry and the other on-chip circuit elements.