Patent ID: 7368966

Claim:
An apparatus for correcting clock duty cycle, comprising: a phase comparator for comparing a phase of a rising clock with that of a falling clock to output a comparing signal; a clock duty cycle correction (DCC) controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate rising and falling pre-clock signals; and a clock selector for selectively outputting the rising and the falling pre-clock signals in response to the DCC enable signal and the weight selection signal, wherein the DCC enable signal is activated when the rising and the falling clocks are in a lock state and the weight selection signal is activated when a high pulse width of an external clock is larger than a low pulse width of the external clock, wherein the clock selector outputs the rising pre-clock signal as a rising feedback clock and the falling pre-clock signal as a falling feedback clock when the DCC enable signal is inactivated.