Patent ID: 8232828

Claim:
An analog circuit having improved response time, the analog circuit comprising: a low level limiter for converting a signal having a level lower than a predetermined reference level into a signal having a first predetermined level higher than the predetermined reference level; and an analog circuit section for amplifying the signal from the low level limiter into a signal having a second predetermined level, wherein the analog circuit section comprises a voltage follower including a first operational amplifier having a non-inverting input terminal connected to an output terminal of the low level limiter, an inverting input terminal, and an output terminal connected to the non-inverting input terminal, and the low level limiter comprises: a second operational amplifier having an inverting input terminal connected to an input terminal, a non-inverting terminal, and an output terminal; a p-channel metal-oxide semiconductor (PMOS) transistor having a source connected to an operating power terminal, a gate connected to the output terminal of the second operational amplifier, and a drain connected to the non-inverting input terminal of the second operational amplifier; a current source connected between the operating power terminal and the drain of the PMOS transistor to thereby generate a predetermined first current; and a first resistor connected between a ground and a connection node between the drain of the PMOS transistor and the non-inverting input terminal of the second operational amplifier.