Patent ID: 8258057

Claim:
A method of forming a semiconductor device comprising: forming a gate electrode on a gate dielectric layer formed on a planar semiconductor substrate; forming a source region and a drain region on opposite sides of said gate electrode wherein said semiconductor device has a gate length defined as the distance between said source region and said drain region and a gate width perpendicular to said gate length, said source region and said drain region each having a length parallel to said gate width; forming a dielectric layer over said source region and said drain region; forming a trench opening in said dielectric layer over one of said source region and said drain region, said trench opening having a trench length and a trench width wherein said trench length is greater than said trench width and wherein said trench length is parallel to said gate width, said trench length extending said entire length of said one of said source region and said drain region; and filling the trench opening with a conductive material to form a contact.