Patent ID: 8044687

Claim:
A wide input common mode voltage comparator comprising: a high common mode voltage comparator comprising: a bias NMOS transistor having a first source terminal coupled to ground; a pair of differential NMOS transistors coupled to a first drain terminal of the bias NMOS transistor; and a first load block coupled to the bias pair of differential NMOS transistor; a summing circuit; a low common mode voltage comparator comprising: a first native NMOS transistor serving as a bias transistor and being coupled to ground at its source terminal; second and third native NMOS transistors forming a differential pair, the second and third native NMOS transistors coupled to the drain terminal of the first native NMOS transistor and receiving an input differential voltage as gate voltages, the second and the third NMOS transistors having a threshold voltage between −100 to 100 mV; and a second load block comprising: a first PMOS transistor coupled at its drain terminal to the drain terminal of the second native NMOS transistor; the drain terminal of the first PMOS transistor additionally coupled to the gate terminal of the first PMOS transistor; a second PMOS transistor coupled at its drain terminal to the drain terminal of the third native NMOS transistor; the drain terminal of the second PMOS transistor additionally coupled to the gate terminal of the second PMOS transistor; a third PMOS transistor coupled at its gate terminal to the gate terminal of the first PMOS transistor, the drain terminal of the third PMOS transistor coupled to a first output; and a fourth PMOS transistor coupled at its gate terminal to the gate terminal of the second PMOS transistor, the drain terminal of the fourth PMOS transistor coupled to a first output; wherein: the first, second, third, and fourth PMOS transistors are coupled to a voltage source at their source terminals; the high common voltage comparator receives the input differential and generates a second output; the summing circuit receives the first output and the second output and generates a third output based on the first output and the second output.