Patent ID: 7702040

Claim:
A method of improving estimation of frequency error in a frequency locked loop (FLL) comprising: receiving k samples of in-phase (I ka ) and quadrature-phase Q ka and in-phase (I kb ) and quadrature-phase (Q kb ) by an integrate and dump block; generating k samples of integrated in-phase (I k ) and quadrature-phase (Q k ) samples from the I ka , Q ka , I kb and Q kb samples extending, in time interval, longer than the rate at which they were integrated; calculating phase angles, Φ ka , Φ kb , Φ k , of the received samples based on the received and generated k samples, wherein ‘k’ represents a sample number and ‘a’ and ‘b’ are each integers; calculating phase rotations, ΔΦ kab , ΔΦ kba , ΔΦ k using the calculated phase angles, Φ ka and Φ kb , by a carrier loop discriminator block; computing averaged phase rotation ΔΦ ab using ΔΦ kab phase rotations between each pair of neighboring received samples within the same data bit intervals; determining ‘valid’ sample averaged rotation ΔΦ kab based on the ability to detect a bit transition or no bit transition; computing improved averaged phase rotation using the sample averaged rotation ‘valid’ ΔΦ kab ; computing averaged phase rotation using the sample averaged rotation ‘valid’ ΔΦ k ; and determining a final phase error estimate ΔΦ to be used for estimation of a frequency error.