Patent ID: 7701282

Claim:
An offset canceling circuit comprising: a differential amplifier circuit configured to output a first output signal in response to a differential input signal; a latch circuit configured to hold a second output signal determined based on said first output signal; and an offset control circuit configured to supply a reference voltage to said differential amplifier circuit to adjust an offset of said differential amplifier circuit, wherein said second output signal is a binary signal, and said latch circuit changes a signal level of said second output signal based on said first output signal, and said offset control circuit acquires said second output signal from said latch circuit for each of a plurality of predetermined times and updates a voltage value of said reference voltage based on the signal level of said second output signal for at least two of the predetermined times which are acquired continuously in time series, wherein said latch circuit changes the signal level of said second output signal based on a comparison result of said first output signal and a threshold level, and wherein said offset control circuit holds the voltage level of said reference signal, when the signal level of said second output signal for the at least two of the predetermined times is different, and changes the voltage level of said reference voltage when the signal level of said second output signal for the at least two of the predetermined times is identical.