Patent ID: 7750452

Claim:
A semiconductor package, comprising: a substrate or leadframe structure; a plurality of stacked same-size interconnected dies disposed over the substrate or leadframe structure, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material; a plurality of bond pads formed on the top surface of each of the stacked same-size interconnected dies; a plurality of conductive traces formed on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs; and an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of stacked same-size interconnected dies.