Patent ID: 6958537

Claim:
A semiconductor device package comprising: a substrate; a first dielectric layer disposed over a surface of the substrate; a conductive trace layer disposed over the first dielectric layer; a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer; a metallization layer electrically coupled with the plurality of connection areas; a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein: the plurality of signal connection devices is electrically coupled with the metallization layer; an encapsulation layer disposed over the plurality of semiconductor dice; and a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.