Patent ID: 7167120

Claim:
An apparatus for digital-to-analog conversion, comprising: a timing controller, for receiving a grayscale value of a bits, and outputting a selection signal and a control signal of b bits, wherein a, b are both positive integers and a>b>=1, and the control signal is obtained by performing a grayscale dithering algorithm from a-bit to b-bit on the grayscale value, if the grayscale value is less than or equal to 2 a −2 c , in which c is equal to a−b, the selection signal is in a first state, and if the grayscale value is equal to 2 a −2 c +n, in which n is an integer and 0<n<2 c , the selection signal has a probability of n/2 c to be in a second state, and has a probability of 1−n/2 c to be in the first state; a scale-tuned circuit, for providing 2 b +1 scale-tuned voltages, of which V 0 is the lowest scale-tuned voltage, V(2 c ) is the second lowest scale-tuned voltage, and V(2 a ) is the highest scale-tuned voltage; and a digital-to-analog converter, for receiving the selection signal, the control signal and the scale-tuned voltages, outputting the scale-tuned voltage V(s×2 c ) corresponding to the first state if the selection signal is in the first state and the control signal value is s, and outputting the scale-tuned voltage V(2 a ) corresponding to the second state if the selection signal is in the second state, wherein s is the value of the control signal.