Patent ID: 7843907

Claim:
A method comprising: in one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor, initiating a mass storage session with a selected mass storage interface, the selected mass storage interface being coupled to the physical partitions via a switch fabric, the mass storage session at least in part via a mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces; accessing storage data via the selected mass storage interface in response to requests from the one of the physical partitions, the storage data being communicated in part via the switch fabric; and wherein the selected mass storage interface comprises a mass storage input/output controller, each physical partition comprises at least one respective partition input/output controller, each physical partition is formed at least in part by programmatically configuring links between processors of the physically partitionable symmetric multiprocessor to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis, and each of the input/output controllers is associated with one of a plurality of physical ports of the switch fabric and enabled to provide cellifying transport via the switch fabric at least in part by addressing cells to a particular one of the physical ports.