Patent ID: 7745287

Claim:
A method of fabricating a nonvolatile memory device, comprising: forming a pattern having sidewalls on a semiconductor substrate, to form an upper surface and a lower surface on the substrate; forming buried diffusion layers at the upper surface and the lower surface; forming bitline insulating layers at the semiconductor substrate on the upper surface and the lower surface excluding the sidewalls between a bottom surface of the bitline insulating layer on the upper surface and a top surface of the bitline insulating layer on the lower surface; forming a charge trap insulating layer at the sidewalls; and forming a gate electrode on the charge trap insulating layer wherein forming bitline insulating layers includes: conformally forming an oxidation barrier layer on a surface or an entire surface of the semiconductor substrate where the buried diffusion layers are formed; anisotropically etching the oxidation barrier layer to form insulating layer patterns covering the sidewalls of the pattern; annealing the semiconductor substrate including the insulating layer patterns to form a thermal oxide layer at the semiconductor substrate exposed between the insulating layer patterns; and removing the insulating layer patterns.