Patent ID: 7053687

Claim:
A phase shifter circuit, comprising: a circuit clock input terminal; a multi-bit circuit input terminal; a counter circuit having an input terminal coupled to the circuit clock input terminal and further having a multi-bit output terminal; a first subtractor having a multi-bit input terminal coupled to the output terminal of the counter circuit and further having a multi-bit output terminal; a first multiplexer circuit having a first multi-bit data input terminal coupled to the output terminal of the counter circuit, a second multi-bit data input terminal coupled to the output terminal of the first subtractor, a select terminal, and a multi-bit output terminal; a comparator circuit having a first multi-bit input terminal coupled to the output terminal of the first multiplexer circuit, a second multi-bit input terminal coupled to the circuit input terminal, and an output terminal coupled to the select terminal of the first multiplexer circuit; a second multiplexer circuit having a first multi-bit data input terminal coupled to the circuit input terminal, a second multi-bit data input terminal coupled to the output terminal of the counter circuit, a select terminal coupled to the output terminal of the comparator circuit, and an output terminal; and a phase shifter having a clock input terminal coupled to the circuit clock input terminal, a multi-bit control terminal coupled to the output terminal of the second multiplexer circuit, and an output terminal.