Patent ID: 8149025

Claim:
A gate driving circuit, adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating a plurality of internal shift data signal groups and thereby sequentially outputting a plurality of gate signals, wherein each of the internal shift data signal groups comprises a plurality of sequentially-generated internal shift data signals; the gate driving circuit comprising a plurality of gate signal generating modules and each of the gate signal generating modules comprising: a voltage modulation circuit, subjected to the control of the external control signal cooperative with a corresponding one of the internal shift data signal groups to determine whether directing the external gate power supply voltage inputted into the voltage modulation circuit to an output terminal of the voltage modulation circuit and thereby generating a modulated voltage signal at the output terminal of the voltage modulation circuit; and a gate output buffer circuit, electrically coupled to the output terminal of the voltage modulation circuit, comprising a plurality of output stages electrically connected with one another in parallel for sequentially outputting the modulated voltage signal as multiple ones of the gate signals to respectively drive multiple gate lines during the output stages being sequentially enabled; wherein the voltage modulation circuit comprises: a first transistor, wherein the first source/drain of the first transistor is electrically coupled to receive the external gate power supply voltage; a second transistor, wherein the first source/drain of the second transistor is electrically coupled to a predetermined potential, the second source/drain of the second transistor is electrically coupled to the second source/drain of the first transistor and further serves as the output terminal of the modulated voltage signal, and the gate of the second transistor is electrically coupled to the gate of the first transistor; and a control unit, for controlling voltages at the gates of the first and second transistors according to the external control signal and the corresponding one of the internal shift data signal groups, to determine on/off states of the first and second transistors; wherein the on/off states of the first transistor are opposite to the on/off states of the second transistor.