Patent ID: 7446587

Claim:
A semiconductor device comprising: a first variable delay circuit; a first circuit to which a first signal outputted from the first variable delay circuit is inputted; a second variable delay circuit; and a second circuit to which a second signal outputted from the second variable delay circuit is inputted, wherein the first variable delay circuit comprises at least one delay element, a first selector including a first switching element and a second switching element, a second selector including a third switching element and a fourth switching element, a first decoder for selecting one of the first switching element and the second switching element and a second decoder for selecting one of the third switching element and the fourth switching element, wherein an input terminal of the first variable delay circuit is connectable to an output terminal of the first variable delay circuit through the first switching element and the third switching element or through the second switching element, the delay element and the fourth switching element in accordance with a signal of the first decoder and a signal of the second decoder, wherein the first signal and the second signal which are divided from a single signal is inputted to each of the first variable delay circuit and the second variable delay circuit, and wherein a difference between a phase of the first signal outputted from the first variable delay circuit and a phase of the single signal is smaller than a difference between a phase of the first signal to be inputted to the first variable delay circuit and a phase of the single signal.