Patent ID: 7808033

Claim:
A method, comprising: demarcating both a first element active region and a second element active region in a semiconductor substrate using an element isolation structure that comprises a shield plate electrode formed on a first insulating film disposed on the semiconductor substrate; forming a transistor in the first element active region, wherein the transistor includes a first electrode; forming a conductive region in the second element active region; forming a second electrode over at least a portion of the conductive region, wherein the second electrode is separated from the conductive region by the first insulating film, and wherein the shield plate electrode and the second electrode are formed on the first insulating film such that the shield plate electrode is spaced apart from the second electrode; and electrically connecting the first electrode and the second electrode, wherein the connected first and second electrodes form a floating gate electrode of a non-volatile memory cell formed by the transistor and the conductive region.