Patent ID: 7982514

Claim:
A system comprising: a master flip flop that receives and stores state information during active mode and standby mode operation from a plurality of input signals; a slave flip flop that receives and stores state information during active mode operation from the master flip flop; a standby mode control circuit that controls the state of the master and slave flip flops during active and standby mode operation based on at least two control signals, wherein the control signals include, a clock input signal and a standby mode control input signal used in combination to generate a standby mode control output signal; a first transfer gate for controlling power to the master flip flop based on the standby mode control output signal; a second transfer gate for controlling power to the slave flip flop based on the standby mode control output signal; at least one power supply that supplies the slave flip flop during active mode operation and that supplies the master flip flop and the standby mode control circuit during active mode and standby mode operation.