Patent ID: 8431969

Claim:
A three-dimensional semiconductor device comprising: a substrate; stacked structures disposed adjacent one another in a horizontal direction on the substrate so as to occupy a two-dimensional space on the substrate; a first interconnection layer including first interconnections and disposed on the stacked structures; a second interconnection layer including second interconnections and disposed on the first interconnection layer; lower and upper conductive connection patterns extending between adjacent ones of respective pairs of the stacked structures, and wherein each of the stacked structures includes a plurality of stacked word lines so as to have at least one lower word line in a lower region of the stacked structure, and at least one upper word line in an upper region of the stacked structure located on the lower region, and each of the first interconnections is electrically connected to one of the lower word lines and each of the second interconnections is electrically connected to one of the upper word lines, each of the lower connection patterns electrically connects lower word lines which are disposed at the same height relative to an upper surface of the substrate, and the lower connection patterns and the lower word lines are of the same material, and have the same thickness, and each lower connection pattern is disposed at the same height relative the upper surface of the substrate as the lower word lines it connects, and each of the upper connection patterns electrically connects upper word lines which are disposed at the same height relative to an upper surface of the substrate, and the upper connection patterns and the upper word lines are of the same material, and have the same thickness, and each upper connection pattern is disposed at the same height relative the upper surface of the substrate as the upper word lines it connects.