Patent ID: 8185802

Claim:
A data memory system comprising: a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by said plurality of memory cells being collectively erased, at least binary pieces of digital data of “1” and “0” being stored as charges of a charge accumulation layer in the memory cell, a programming bit and an erasing bit being formed by a difference between the charges of the charge accumulation layer; an error correcting code generation circuit which generates a code for correcting error data of at least one bit from a first code, and produces an error correcting code recorded in the page; an error correcting code decoding circuit which corrects an error from the error correcting code to restore the first code by digital data recorded in the page; and a code conversion circuit which computes exclusive OR of a plurality of information bits and a plurality of bits in which a sequence of “programming bit-erasing bit” is repeated a plurality of times, and supplies the exclusive OR to the error correcting code generation circuit as the first code.