Patent ID: 8120937

Claim:
A content addressable memory device for storing data words, each bit of a data word being set to one of three ternary data values of low, high, and don't care, the content addressable memory device comprising: a plurality of match-lines; a plurality of memory cells electrically coupled in parallel circuit to one match-line of the plurality of match-lines, each memory cell storing one bit of the data word; a first memory element in each memory cell configured to store a low resistance state if the ternary data value of its corresponding bit is low and a high resistance state if the ternary data value of its corresponding bit is either high or don't care, the high resistance state being at least one order of magnitude higher in resistance than the low resistance state; a second memory element in each memory cell configured to store the low resistance state if the ternary data value of its corresponding bit is high and the high resistance state if the ternary data value of its corresponding bit is either low or don't care, the match-line electrically coupling the first memory element and the second memory element in a parallel circuit; and a match circuit electrically coupled to each match-line, the match circuit configured to measure a collective effective resistance of the plurality of memory cells electrically coupled to each individual match-line during a search operation; and wherein the match circuit is configured to determine a number of mismatched bits between the data word and a search word based on the collective effective resistance of an individual match-line, the number of mismatched bits being inversely proportional to the collective effective resistance.