Patent ID: 7602028

Claim:
A NAND flash memory device comprising: a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer; a first drain region and a first source region located in the lower semiconductor layer; a second drain region and a second source region located in the upper semiconductor layer; a first gate structure located on the lower semiconductor layer; a second gate structure located on the upper semiconductor layer; a bit line located over the upper semiconductor layer; and at least one bit line plug connected between the bit line and the first drain region, wherein the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer, and wherein each gate structure comprises a string selection line located adjacent the first or second drain region, a ground selection line located adjacent the first or second source region, and a plurality of word lines disposed between the string selection line and the ground selection line, and wherein the bit line extends in a direction that crosses over the word lines.