Patent ID: 8627032

Claim:
A memory management system comprising: a memory organized as a plurality of programmable memory segments, a plurality of requestors operable to originate memory access requests wherein the memory access request includes a memory address to be accessed, a descriptor of the requested access and a permission field containing a plurality of bits indicating the access permissions associated with the request, an extended memory controller operable to control access to said memory, said extended memory controller including a port operable to communicate with the plurality of requestors, a segment register associated with each memory segment operable to store parameter fields defining the memory segment including a memory starting address, memory size and a plurality of permission bits, a comparison circuit operable to compare the memory address range in the segment registers as defined by the starting address and memory size of each segment register, and the memory address provided as part of the memory access request provided by the requestor on said port, and further operable to select a segment register based on said comparison showing that the requested address is within said memory address range of the selected segment register, and a logic circuit operable to perform a logical AND operation between corresponding bits in the permissions field in the selected segment register and the permissions field provided as part of the memory access request provided on said port, resulting in merged permissions applicable to said memory access request.