Patent ID: 7999623

Claim:
An apparatus comprising: a time-to-digital converter (TDC) for converting a time difference between a reference clock and a feedback clock into a time difference signal; a cancellation circuit for receiving the time difference signal and generating a residual error signal according to the time difference signal and an instantaneous error signal, comprising: a series expansion for mapping the instantaneous error signal into a predicted error signal; and a summation circuit for subtracting from the time difference a predicted error signal to generate the residual error signal; a digital loop filter for filtering the residual error signal to generate a control code; a digitally controlled oscillator (DCO) for generating an output clock in accordance with a control by the control code; and a divider circuit for receiving a fractional number between 0 and 1 to generate the instantaneous error signal, and for dividing down from the output clock with a divisor value controlled by the fractional number to generate the feedback clock.