Patent ID: 7682929

Claim:
A method for fabricating an integrated circuit device structure having a design rule of less than 0.13 micron, the method comprising: providing a substrate; forming a pad oxide layer overlying the substrate; forming a nitride layer overlying the pad oxide layer; patterning the nitride layer and pad oxide layer; forming a trench structure within a thickness of the substrate using the patterned nitride layer and pad oxide layer as hard mask, the hard mask being free from an overlying photoresist material; selectively etching a portion of an exposed region of the pad oxide layer to form an undercut region in the pad oxide layer overlying the substrate; forming a first thickness of liner oxide within the trench structure using at least thermal oxidation of an exposed region of the trench structure to cover the trench structure, whereupon the thermal oxidation causes a rounding region near corners of the trench structure; selectively removing the thickness of liner oxide within the trench structure; forming a second thickness of liner oxide within the trench structure using at least thermal oxidation to cover the trench structure, whereupon the thermal oxidation causes a further rounding of the rounded region near corners of the trench structure; and selectively removing a portion of the patterned nitride layer while the second thickness of liner oxide protects the substrate in the trench region.