Patent ID: 7058065

Claim:
In a packet processor having a local packet memory (LPM) for storing packet data during processing, the LPM having a plurality of memory cells, the memory cells accessible by at least one memory access port, a system for managing port contention between at least two controllers that access the memory cells, comprising: a buffer for queuing write requests to the at least one memory port for a first one of the controllers; and a logic mechanism associated with the buffer for determining whether a write request from said first one of the controllers is within said buffer and is directed at a first one of the memory cells, and if so, whether a read request exists from a second one of the controllers and is directed at said first one of the memory cells; wherein, if a read request exists from said second one of the controllers and is directed at said first one of the memory cells while said write request is buffered, said read request is delayed until said write request has completed regardless of when said read request occurs.