Patent ID: 8395190

Claim:
A three-dimensional semiconductor memory device comprising: a substrate comprising a cell array region including a pair of sub-cell regions and a strapping region between the pair of sub-cell regions; a plurality of sub-gates sequentially stacked on the substrate in each of the sub-cell regions, each of the sub-gates including an extension extending laterally over the strapping region; a vertical-type channel pattern successively penetrating the stacked sub-gates within each of the pair of sub-cell regions; and interconnections electrically connected to the extensions of the stacked sub-gates, respectively, said interconnections including at least a first interconnection and a plurality of second interconnections located at the same level, said first interconnection electrically connected to an extension of an uppermost one of the plurality of sub-gates and each of the plurality of second interconnections electrically connected to extensions of corresponding ones of the plurality of sub-gates, which are below the extension of the uppermost one of the plurality of sub-gates.