Patent ID: 8154117

Claim:
An integrated circuit (IC), comprising: a substrate having a semiconducting surface; a first array of devices on and in said semiconducting surface, each of said devices in said first array comprising at least first and second coacting current conducting nodes; a plurality of layers disposed on said substrate, said plurality of layers comprising a plurality of electrically conductive layers and a plurality of dielectric layers; the substrate having a top dielectric surface; a first plurality of bump pads on or in said top dielectric surface, each of the first plurality of bump pads electrically connected to a first coacting current conducting node; each of the first plurality of bump pads electrically isolated from all other bump pads of the first plurality of bump pads below the top dielectric surface; the first plurality of bump pads forming a linear array enabling the first plurality of bump pads to form physical joints to a first common contact band external to the substrate; a second plurality of bump pads on or in said top dielectric surface, each of the second plurality of bump pads electrically connected to a second coacting current conducting node; each of the second plurality of bump pads electrically isolated from all bump pads of the first plurality of bump pads and all other bump pads of the second plurality of bump pads below the top dielectric surface; and the second plurality of bump pads forming a linear array enabling the second plurality of bump pads to form physical joints to a second common contact band external to the substrate, the second common contact band separated from and parallel to the first common contact band.