Patent ID: 8159275

Claim:
A phase-locked loop (PLL), comprising: a phase detector configured to compare the phase of an input clock signal with the phase of an output clock signal and output an up signal and a down signal; a charge pump configured to charge and discharge electric charges in response to the up signal and the down signal, respectively, and output a pumping voltage; a loop filter configured to filter the pumping voltage and output a filtering voltage; a bias generator configured to generate a bias voltage inversely proportional to a power supply voltage; a regulator configured to receive the bias voltage and the filtering voltage and output a control voltage having the same voltage level as the filtering voltage; and a voltage controlled oscillator configured to control and output the frequency of the output clock signal in response to the control voltage, wherein the bias generator comprises: a bias generation unit connected between the power supply voltage and a ground voltage and configured to generate a first bias set voltage and a second bias set voltage, which are proportional to the power supply voltage, through a first bias node and a second bias node, respectively, and to generate the bias voltage through a bias output node; and a first bias control unit connected between the bias output node and the ground voltage and configured to control the bias voltage to be inversely proportional to the power supply voltage in response to the second bias set voltage.