Patent ID: 7292175

Claim:
A method of testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units each of which delays an input pulse signal by a time depending on a value of an input voltage to be A/D converted, and an encoding circuit configured to count the number of said delay units through which said input pulse signal passes within a predetermined measuring time and to output a digital signal representing said counted number as an A/D converted digital signal of said input voltage, said method comprising the steps of: setting said A/D converter circuit in a test mode where said measuring time is set at a test-use sampling period shorter than a real-use sampling period used when said A/D converter circuit is in actual use; applying said input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of said delay units; and determining good and bad of said A/D converter circuit on the basis of digital signals outputted from said encoding circuit representing the numbers of said delay units through which said input pulse signal has passed within said test-use sampling period within each of said serial delay blocks.