Patent ID: 7698353

Claim:
A method performed by a data processing system implemented in circuitry, the method comprising: receiving a mantissa and an exponent of a floating point number, the mantissa represented by a first plurality of bits and the exponent represented by a second plurality of bits; partitioning the first plurality of bits into a plurality of regions; separately examining each of the plurality of regions for determining a position of a leading bit of the first plurality of bits, wherein the separately examining includes separately examining each of the plurality of regions for determining a position of a leading bit of the each region; selecting a region of the plurality of regions based on the separately examining each of the plurality of regions; and performing one of normalizing the selected region to produce a normalized floating point number or denormalizing the selected region to produce a denormalized floating point number, wherein the performing one of normalizing the selected region or denormalizing the selected region includes shifting a second plurality of bits including the selected region, wherein the second plurality of bits is less than the first plurality of bits.