Patent ID: 7404069

Claim:
A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of an expanded type, said device comprising: means for receiving a first signal representative of an actually executed instruction; means for receiving a second signal representative of an expanded instruction; means for receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by said microcontroller, microprocessor or data processing unit; means for storing consecutive addresses pointed to by a program counter; means including a state machine for processing said first, second and third signals in order to determine a pair that includes a source address and a destination address for an address branch, when appropriate; and storage means for storing said address pair, wherein said means for storing consecutive addresses pointed to by said program counter includes: a first register receiving a current value of the program counter presented by said microcontroller, microprocessor or processing unit; a second register having an input terminal and an output terminal; a first multiplexer having an output terminal, a first input terminal coupled to an output terminal of said first register and a second input terminal coupled to the output terminal of the first multiplexer, said first multiplexer being controlled by said first signal in order to allow either storing of contents of said first register, or recycling of a value previously stored in said second register; a third register having an input terminal and an output terminal; a second multiplexer having an output terminal, a first input terminal coupled to the output terminal of said second register, and a second input terminal coupled to the output terminal of the second multiplexer, said second multiplexer being controlled by a first control signal generated by said state machine; and a third multiplexer having a first input terminal coupled to the output terminal of said third register and a second input terminal coupled to the output terminal of said second register, and an output terminal coupled to said storage means for storing said address pair, said third multiplexer being controlled by a second control signal generated by said state machine.