Patent ID: 7889572

Claim:
A memory, comprising: a plurality of memory regions each comprising: a target memory cell; a source line coupled to a first terminal of the target memory cell; a bit line coupled to a second terminal of the target memory cell; a reading control circuit for selectively applying a working voltage to the source line; a clamp transistor having a first terminal coupled to the bit line; a latch coupled to a second terminal of the clamp transistor; a select transistor for selecting the bit line, wherein a second terminal of the select transistor is coupled to the first terminal of the clamp transistor; a pre-charge transistor having a first terminal for receiving the working voltage, and a second terminal coupled to the second terminal of the clamp transistor; a select switch having a first terminal coupled to the second terminal of the clamp transistor, and a second terminal coupled to the latch; and a reset switch having a first terminal coupled to the second terminal of the clamp transistor, and a second terminal for receiving a ground voltage.