Patent ID: 7511998

Claim:
A non-volatile memory device comprising: a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.