Patent ID: 7730263

Claim:
A method for prefetching data from a computer memory and placing it in a cache to be accessed by a processor during execution of a program thread comprising the steps of: executing a sequence of instructions in a program thread using a first processor, said instructions at least including a plurality of register-writing instructions, some of which specify an address where data to be loaded into a processor register during execution of said instruction resides; after each register-writing instruction is executed, supplying the instruction and a result thereof to a value predictor and updating the value predictor with said result; employing the value predictor to determine a likely result for a future execution of said instruction; if the predicted value is determined to have a confidence level exceeding a threshold, then substituting the instruction with a load immediate instruction, where said immediate is said predicted value; forming said instructions as they are processed by said value predictor into a prefetching thread; and executing said prefetching thread with a second processor that also accesses said cache, wherein said value predictor is attached to a unidirectional communication link connecting said first processor to said second processor which supplies each said register-writing instruction and the result thereof from said first processor to said value predictor and then supplies said prefetching thread from said value predictor to said second processor for execution thereby, whereby data to be employed during execution of said program thread is caused to be loaded into said cache by execution of said prefetching thread.