Patent ID: 7670885

Claim:
A method of manufacturing a thin-film semiconductor device, which comprises: forming an amorphous semiconductor layer on a transparent insulating substrate; forming a crystallized region in the amorphous semiconductor layer; forming a gate insulating film and a gate electrode on the crystallized region; implanting an impurity at low concentration into an expected source region and an expected drain region of the crystallized region respectively neighboring to opposite sides of the gate electrode, the implanting being performed using the gate electrode as a mask; forming an insulating film on a surface of the resultant structure; etching back the insulating film until the crystallized region is exposed to thereby form a sidewall spacer on a sidewall of the gate electrode; forming an amorphous semiconductor layer for forming a stacked source layer and a stacked drain layer on a surface of the resultant structure; implanting an impurity at high concentration into the crystallized region and the amorphous semiconductor layer with the gate electrode and the sidewall spacer being used as a mask to thereby form a source diffusion region and a drain diffusion region in the crystallized region; subjecting the amorphous semiconductor layer to heat treatment, thereby not only activating the impurity implanted in the crystallized region and the amorphous semiconductor layer but also restoring crystallinity of only a portion of the amorphous semiconductor layer which is formed on the crystallized region to thereby turn said portion into a polycrystalline semiconductor layer; and subjecting the resultant surface to selective etching to thereby leave only the polycrystalline semiconductor layer which is deposited on the crystallized region and to remove the amorphous semiconductor layer formed on other regions, thereby forming, in a self-aligned manner, a stacked source diffusion layer consisting of polycrystalline semiconductor on the source diffusion layer and a stacked drain diffusion layer consisting of polycrystalline semiconductor on the drain diffusion layer.