Patent ID: 8101515

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a first interlayer insulation layer on a substrate that includes a first active region and a second active region; patterning the first interlayer insulation layer to form a first opening that exposes the first active region; depositing a first conductive material in the first opening to form a first contact plug; forming a second interlayer insulation layer on the first interlayer insulation layer and the first contact plug; forming a second opening in the first and second interlayer insulation layers that exposes the second active region; depositing a second conductive material in the second opening to form a second contact plug, wherein a height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate; forming a third contact plug on the second contact plug, wherein the third contact plug is electrically connected to the second contact plug, wherein a silicide layer is formed at an interface between the second contact plug and third contact plug, wherein a height of a lower surface of the silicide layer from the substrate is greater than a height of an upper surface of the first contact plug from the substrate; forming a capping layer on the third contact plug; forming a first spacer on a side surface of the third contact plug, wherein the first spacer covers an entirety of a side portion of the silicide layer and extends from the silicide layer to the second contact plug; forming a third interlayer insulation layer on the second interlayer insulation layer, wherein the third interlayer insulation layer covers the third contact plug; patterning the third interlayer insulation layer to form a third opening that exposes the first contact plug; and depositing a fourth conductive material in the third opening to form a fourth contact plug that is electrically connected to the first contact plug.