Patent ID: 8278152

Claim:
A method of making an integrated circuit (IC), comprising: forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate through the opening without the deep trench extending through the top metal pad; filling a conductive material in the deep trench and the opening, resulting in a through-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; removing excessive conductive material, forming a substantially planar surface; forming a dielectric layer on the front side of the substrate after removing the excessive conductive material; grinding the substrate from a backside to expose the TWV feature; and etching the substrate in a scribe region from the backside to form a scribe-line trench.