Patent ID: 7315475

Claim:
A non-volatile semiconductor memory device comprising: a main memory cell which is included a non-volatile transistor and whose threshold voltage is adjustable; a reference memory cell which is included a non-volatile transistor and whose threshold voltage is adjustable; a sense amplifier which has a first input node, a second input nodes and an output node, the reference memory cell being coupled to the first input node; a current mirror type load circuit connected to the first input node and the second input node of the sense amplifier; a first transistor which has one end and the other end, the one end being coupled to the second input node of the sense amplifier; a reference current source circuit connected to the other end of the first transistor; a second transistor which has one end and the other end, the one end being coupled to the second input node of the sense amplifier, and the main memory cell being connected to the other end; and a controller which generates a control signal to control the first transistor being turned on and the second transistor being turned off when the threshold voltage of the reference memory cell is adjusted, and to control the first transistor being turned off and the second transistor being turned on when the threshold voltage of the main memory cell is adjusted at verification of writing to/erasing from the main memory cell.