Patent ID: 8363367

Claim:
A semiconductor circuit comprising: a network of a resistor and a capacitor located between a power supply node and electrical ground; an inverter comprising an output node at a serial connection of a drain of a p-type field effect transistor and a drain of an n-type transistor connection and an input node at a parallel connection of a gate of said p-type field effect transistor and a gate of said n-type transistor; a discharge transistor connected between said power supply node and electrical ground, wherein said output node of said inverter is electrically connected to a gate of said discharge transistor; and an electronic component having voltage snapback property or diodic property, wherein a first end of said electronic component is connected to said power supply node or electrical ground, and wherein a second end of said electronic component is connected to said input node of said inverter or said output node of said inverter, wherein said electronic component is selected from: an n-type field effect transistor (NFET) having a parasitic npn bipolar transistor across a source, a body, and a drain of said NFET, a parasitic source side resistance, and a drain side resistance, and wherein said source of said NFET is electrically shorted to a gate of said NFET, wherein said source of said NFET and said drain of said NFET consists of an n-doped semiconductor material and does not include a metal semiconductor alloy; and a p-type field effect transistor (PFET) having a parasitic pnp bipolar transistor across a source, a body, and a drain of said PFET, a parasitic source side resistance, and a drain side resistance, and wherein said source of said PFET is electrically shorted to a gate of said PFET, wherein said source of said PFET and said drain of said PFET consists of a p-doped semiconductor material and does not include a metal semiconductor alloy.