Patent ID: 8217434

Claim:
A semiconductor package comprising: a semiconductor chip comprising: a first surface and a second surface which faces away from the first surface, a circuit section placed in the semiconductor chip, first and second internal circuit patterns electrically coupled to the circuit section and at different depths with respect to the first surface, and first and second through-holes in which both pass through the first and second surfaces and respectively pass through the first and second internal circuit patterns; first and second insulation layers respectively on the first and second through-holes, the first and second insulation layers respectively having first and second openings that respectively expose the first and second internal circuit patterns along the first and second through-holes; first and second through-electrodes respectively within the first and second through-holes and respectively electrically coupled to the first and second internal circuit patterns which are respectively exposed by the first and second internal circuit patterns along the first and second through-holes; a first diffusion barrier on the first insulation layer and electrically coupled to the first internal circuit pattern; and a second diffusion barrier on the second insulation layer and having an opening that exposes the second internal circuit pattern.