Patent ID: 7528065

Claim:
A method of forming a field effect transistor (FET), said method comprising: providing a substrate; depositing a buried oxide (BOX) layer over said substrate; positioning a silicon on insulator (SOI) layer over said BOX layer; forming a shallow trench isolation (STI) region over said BOX layer; patterning a first gate structure on said SOI layer; patterning a second gate structure on said STI region; and attaching a landing pad to said second gate structure, wherein a width of said landing pad is at least twice a width of said second gate structure, wherein the structure of said second gate structure is discontinuous with the structure of said landing pad, and wherein said landing pad is formed to overhang a substantial portion of a height of said second gate structure; forming epitaxially-grown regions on opposite sides of said first gate structure; attaching a first sidewall spacer adjacent to and on opposite sides of said first gate structure; positioning a first gate dielectric layer in between said SOI layer and said first gate structure; forming a first salicide region on said first gate structure and said epitaxially-grown regions; connecting a first interconnect contact to said first salicide region; laying a dielectric liner over said first gate structure, said first sidewall spacer, said first salicide region, and said STI region; placing an interlevel dielectric layer over said dielectric liner; forming a second gate dielectric layer in between said STI region and said second gate structure; attaching a second sidewall spacer adjacent to and on opposite sides of said second gate structure, wherein said second sidewall spacer contacts a portion of said landing pad overhanging said second gate structure; forming a second salicide region on said landing pad; connecting a second interconnect contact to said second salicide region; laying said dielectric liner over said second sidewall spacer, said second salicide region, and said STI region; placing said interlevel dielectric layer over said dielectric liner, wherein in the attaching of said landing pad to said second gate structure, said landing pad comprises epitaxially-grown material; and configuring an upper surface of said landing pad to be higher than an upper surface of said first gate structure.