Patent ID: 7839688

Claim:
A NAND type flash memory device comprising: a flash memory cell array comprising a plurality of non-volatile memory cells arranged in rows and columns, each of the memory cells comprising a memory cell transistor including a charge storage portion adjacent a channel of the memory cell transistor affecting a threshold value of the memory cell transistor, each column including a string memory cell transistors connected in series; and a row selector circuit configured to select one of the rows and to cause a first voltage to exist on the selected row, a second voltage to exist on at least one row adjacent the selected row and a third voltage to exist on at least one of the remaining rows at a same instant in time during a program operation, wherein magnitudes of the first, second and third voltages are greater than zero, wherein the first voltage has a magnitude to allow programming of memory cells arranged along the selected row, wherein the magnitude of the second voltage is lower than the magnitude of the first voltage and the magnitude of the third voltage is lower than the magnitude of the second voltage, wherein the at least one row adjacent the selected row is a row that is most directly adjacent the selected row, wherein the first voltage is a program voltage and the second and third voltages are pass voltages, wherein the program voltage is sufficient to affect a charge level of memory cell transistors arranged along the selected row and which are memory cell transistors of a string of memory cell transistors which have a program data voltage applied thereto, wherein the second voltage has a magnitude sufficient to turn on but not program memory cell transistors arranged along the at least one row adjacent the selected row and which are memory cell transistors of a string of memory cell transistors which have a program data voltage applied thereto, wherein the third voltage has a magnitude sufficient to turn on but not program memory cell transistors arranged along the at least one of the remaining rows and which are memory cell transistors of a string of memory cell transistors which have a program data voltage applied thereto, wherein the row selector circuit causes the third voltage to exist on at least a majority of rows of those rows operably connected to memory cell transistors of strings of memory cell transistors which include a memory cell transistor operably connected to the selected row, and wherein the second voltage is caused to exist on first and second rows, each of the first and second rows being immediately adjacent to the selected row, wherein the row selector circuit causes, during a period after a start of a bit line setup period but preceding the same instant, voltages sufficient to turn on but not program memory cell transistors to exist on the selected row, the at least one row adjacent the selected row and the at least one remaining rows.