Patent ID: 7735032

Claim:
A design structure embodied in a computer-readable medium used in a design process, the design structure comprising a data communication circuit to facilitate communication between a deserializer, which is responsive to a serial data stream and which puts data onto a parallel bus, and a device that is in data communication with the parallel bus, in which the circuit includes: a. a deserialization clock that periodically asserts a clock read pulse each time data on the parallel bus is valid; b. a delay unit that receives the clock read pulse from the deserialization clock and that periodically asserts a corresponding delayed clock pulse, the delayed clock pulse being delayed from the clock read pulse by a predetermined period; and c. a clock tree that repeats the delayed clock pulse, thereby periodically asserting a plurality of end point repeated clock pulses, wherein each of the end point repeated clock signals has a substantially simultaneous leading edge, the predetermined amount of time selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.