Patent ID: 8346527

Claim:
A cycle simulation method for simulating an operation of a digital circuit, wherein a simulation model comprises a plurality of simulated latches representing a corresponding plurality of latch circuits to be modeled, the plurality of simulated latches having corresponding simulated inputs and corresponding simulated outputs, the plurality of simulated latches comprising a first simulated latch having a first simulated output and a second simulated latch having a second simulated input, wherein the first simulated output is connected by a simulated first logic path to the second simulated input, the method comprising: inserting simulated delay latches into corresponding paths of the plurality of simulated latches, the inserted simulated delay latches comprising a first simulated delay latch inserted in the simulated first logic path between the first simulated output and the second simulated input, the first simulated delay latch representing a logic delay of the digital circuit; simulating, by any one of a workstation or an accelerator machine, synchronous clocks of the digital circuit, the simulated synchronous clocks clocking the simulated latches, the simulated synchronous clocks corresponding to functional clocks of the digital circuit; simulating clocking of the inserted simulated delay latches using a delay latch clock to clock the inserted simulated delay latches, wherein each simulated delay latch delays the propagation of a simulated signal by a cycle of the delay latch clock, wherein a first signal of the first simulated output is propagated from the first simulated output to the first simulated delay latch by the delay latch clock and then clocked to the second simulated input by a simulated synchronous clock, such that a logic delay of the simulated first logic path is simulated; and running a simulation of the digital circuit using the simulation model to produce a simulation report based on simulated delays of said simulated delay latches.