Patent ID: 6976185

Claim:
A delay lock loop for an FPGA architecture comprising: a reference delay line having a first input and an output, said first input programmably coupled to a reference clock and selectably coupled through an inverter programmably disposed in series with said reference delay line; a feedback delay line having an input and an output; said input programmably coupled to a feedback clock and selectably coupled through an inverter programmably disposed in series with said feedback delay line; a phase detector having first input, a second input, and a plurality of outputs, said first input programmably coupled to said output of said reference delay line, and said second input coupled to said output of said feedback delay line, wherein said reference delay line and said feedback delay line are selectably coupled to said phase detector through a plurality of divide-by-two circuits; a control logic circuit having a plurality of inputs and a plurality of outputs, at least one of said plurality of inputs programmably coupled to at least one of said plurality of outputs of said phase detector; a programmable delay line having a reference clock input, a plurality of data inputs, and an output, said reference clock input coupled to said reference clock, said plurality of data inputs programmably coupled to said plurality of outputs of said control logic circuit to receive data to program a delay in said programmable delay line; a clock doubler having an input and an output, said input programmably coupled to said output of said programmable delay line; and a clock tree having an input and an output, said input programmably coupled to said output of said clock doubler, and said output forming said feedback clock programmably coupled to said input of said feedback delay line and a clock input of a flip-flop.