Patent ID: 8717274

Claim:
A driving circuit for driving a display having a plurality of pixels spatially arranged in a matrix form, comprising: (a) an input interface for processing input image signals into digital pixel signals associated with the pixel matrix and grayscales of the display; (b) a timing controller for generating a polarity control signal POL; (c) a series to parallel converter electrically coupled to the input interface for converting the digital pixel signals from a series format to a parallel format and the timing controller for controlling output paths of the parallel digital pixel signals, comprising: a plurality of latches, LATCH, for latching and outputting the parallel digital pixel signals, wherein the plurality of latches LATCH has N pairs of latches, wherein each pair of the latches comprises two of the plurality of latches LATCH; and a plurality of multiplexors, MUX, having N pairs of multiplexors, wherein each pair of multiplexors comprises two of the plurality of multiplexors MUX and corresponds to one pair of the latches, and wherein the two multiplexors MUX of each pair of multiplexors are electrically coupled to the two latches LATCH of the corresponding pair of latches for receiving the parallel digital pixel signals therefrom and controlled by the polarity control signal POL for selecting the output paths of the parallel digital pixel signals; and (d) a source driver electrically coupled to the series to parallel converter and the timing controller for converting the digital pixel signals into analog pixel signals and writing the analog pixel signals into the pixel matrix according to the polarity control signal POL, wherein the source driver comprises: a first latch array having a plurality of latches, Latch 1 , electrically coupled to the plurality of multiplexors MUX of the series to parallel converter through bus lines for latching the digital pixel signals receiving from the plurality of multiplexors MUX and simultaneously outputting latched digital pixel signals; and a second latch array having a plurality of latches, Latch 2 , electrically coupled to the first latch array for latching the digital pixel signals receiving from the first latch array and simultaneously outputting latched digital pixel signals.