Patent ID: 7411285

Claim:
A stacked semiconductor chip package, comprising: a mounting substrate having an upper surface and a lower surface opposed to said upper surface, a rectangular accommodating opening formed at a central portion of said mounting substrate, a plurality of plated through-holes each communicating said upper and lower surfaces, a plurality of first conductive metal lines formed on said upper surface of said mounting substrate, and a plurality of second conductive metal lines formed on said lower surface of said mounting substrate, each of said first conductive metal lines extending from a corresponding one of said plated through-holes to one of opening-confining walls that cooperatively confine said opening, each of said second conductive metal lines extending from a corresponding one of said plated through-hole to one of said opening-confining walls; a first semiconductor chip having an upper surface and a lower surface opposed to said upper surface, a plurality of conductive bumps provided on said lower surface of said first semiconductor chip, a plurality of third conductive metal lines formed on said upper surface of said first semiconductor chip, a plurality of fourth conductive metal lines formed on said lower surface of said first semiconductor chip, each of said third conductive metal lines extending from a corresponding edge of said first semiconductor chip to a predetermined position, each of said fourth conductive metal lines extending from a corresponding edge of said first semiconductor chip to a corresponding one of said conductive bumps so as to connect electrically with said corresponding one of said conductive bumps, said first semiconductor chip received in said accommodating opening of said mounting substrate so that each of said third conductive metal lines is linked electrically with a corresponding one of said first conductive metal lines, and that each of said fourth conductive metal lines is linked electrically with a corresponding one of said second conductive metal lines; and a second semiconductor chip having a lower surface and a plurality of conductive bumps provided on said lower surface, and mounted on said upper surface of the first semiconductor chip in such a manner that said conductive bumps of said second semiconductor chip are electrically connected to said corresponding third conductive metal lines.