Patent ID: 6903620

Claim:
A circuit configuration for setting an input resistance and an input capacitance of an integrated semiconductor circuit chip, the chip having an input and a ground node coupled to a substrate, the circuit configuration comprising: an RC network connected between the input and the ground node of the chip, said RC network containing: a plurality of resistance series disposed in parallel between the input and the ground node, each of said resistance series having a plurality of individual resistance elements to be selectively connected/disconnected in a series connection, said resistance elements can be selectively connected in parallel individually or in a plurality thereof to one or to a plurality of said resistance elements of an adjacent one of said resistance series; a plurality of capacitance elements which can be selectively connected from ends of said resistance elements of said resistance series to the substrate; and a plurality of connection/isolation elements each disposed for series connection between said ends of series connected resistance elements of each of said resistance series and for parallel connection between said ends of said parallelly adjacent resistance elements of said resistance series, individually or a plurality of said connection/isolation elements can be selectively placed in a connection state or an isolation state in one step for setting the input resistance and the input capacitance of the semiconductor circuit chip.