Patent ID: 7254727

Claim:
An information processor comprising: a main memory; an processor operatively coupled to said main memory and having (a) a normal-operation mode in which coherence control is performed for making data in a cache memory of said processor identical to data in a main memory and (b) a power-saving mode in which coherence control is suppressed to lower the power consumption from the power consumption of the processor when in said normal-operation mode, said processor entering said normal-operation mode when an input/output device accesses main memory while said processor is in said power-saving mode; an attribute setting module for setting a device area of said main memory to a non-cacheable attribute for exempting said device area from coherence control even in said normal-operation mode, said device area being an area of said main memory accessed by the input/output device; and an operation mode setting module for allowing said input/output device to access said device area while keeping the operation mode of said information processor in said power-saving mode when said input/output device requests access to said device area in said power-saving mode.