Patent ID: 8050080

Claim:
A memory device, comprising: a plurality of row lines and a plurality of column lines; and a memory cell coupled to one of the plurality of column lines and to one of the plurality of row lines, the memory cell including: a capacitor with a first plate coupled to a storage node of the memory cell; and a CMOS-compatible non-volatile storage element comprising a first node coupled to the storage node, wherein the CMOS-compatible non-volatile storage element is configured to hold a charge corresponding to a binary value, and wherein the CMOS-compatible non-volatile storage element is coupled to a control line; and access circuitry coupled to the plurality of row lines, the plurality of column lines, and the control line, wherein the access circuitry is configured to toggle the control line to a control voltage during a read operation, and wherein the CMOS-compatible non-volatile storage element is configured to set, in response to the control voltage, a voltage on the storage node that is dependent on a value of the charge.