Patent ID: 8373169

Claim:
A thin film transistor for an active matrix-type liquid crystal display comprising: a gate electrode that connects to a first gate line; a gate insulation layer on the gate electrode; a first semiconductor layer on the gate insulation layer; a second semiconductor layer divided into two parts facing each other on first and second portions of the first semiconductor layer; a source electrode overlapping the gate electrode and the first semiconductor layer and contacting one of the two parts of the second semiconductor layer; a drain electrode overlapping the gate electrode and the first semiconductor layer and contacting another one of the two parts of the second semiconductor layer, wherein the source and drain electrodes define a channel region in the first semiconductor layer having a length between the source and drain electrodes and a width the same as a width of at least one of the source and drain electrodes; a passivation layer on the source and drain electrodes and a pixel electrode electrically connected to the drain electrode, wherein an end of the pixel electrode overlaps a second gate line adjacent to the first gate line to form a storage capacitor having a storage capacitance, wherein the storage capacitance corresponds inversely proportional to the increment of the ratio of the width to the length (W/L) in the channel region for compensating a parasitic capacitance, wherein the width to the length (W/L) of the channel region is increased to have a range of 8 through 9 such that a parasitic capacitance is increased to have 774 pF, and a size of the overlapped portion between the pixel electrode and the second gate line is configured by expanding a portion where the end of the pixel electrode overlaps with part of the second gate line to reduce the storage capacitance of the storage capacitor in a range of 190 fF through 210 fF for compensating the increment of the parasitic capacitance and for preventing the occurrence of an indefinite spot of low temperature about 0° C., wherein a size range of the storage capacitance is selected to compensate for screen flicker due to an increase in the parasitic capacitance corresponding to an increment in the width to the length (W/L) ratio of the channel region, wherein a size of each pixel of the active matrix-type liquid crystal display is 99 μm×297 μm, wherein the storage capacitance is reduced to 200 Ff, wherein the second semiconductor layer has a higher dopant concentration than the first semiconductor layer, and wherein a length of the overlapped portion between the pixel electrode and the second gate line corresponds with a width of a pixel region corresponding with a distance between the data lines.