Patent ID: 6993693

Claim:
An interface circuit comprising: a scan flip-flop having a clock input for receiving a clock signal, a data input, a set input, and a first output terminal and a second output terminal, the first output terminal providing an output signal for use by a digital circuit that is also clocked by the clock signal; a first logic gate having a first input for receiving an analogue input signal, a second input for receiving a first test signal, and an output connected to the set input of the scan flip-flop; a second logic gate having a first input connected to the second output terminal of the scan flip-flop, a second input for receiving a clear signal, and an output; and a multiplexer having a first input connected to the output of the second logic gate, a second input connected to a second test signal, a control input connected to a test control signal and an output connected to the data input of the scan flip-flop, the scan flip-flop having a state at the first output terminal and second output terminal which is changed by arrival of the analogue input signal irrespective of when the analogue input signal arrives relative to the clock signal.