Patent ID: 8581919

Claim:
A display controller, comprising: an external memory; a timing controller configured to compress current frame data to generate front first in-first out (FIFO) input data, temporarily store the front FIFO input data and write the front FIFO input data to the external memory in a burst mode, and configured to read data from the external memory in the burst mode, temporarily store the read data as back FIFO output data, and decode the back FIFO output data to output previous frame data; and a memory controller configured to temporarily store the front FIFO input data and write the front FIFO input data to the external memory in the burst mode in response to an input valid signal, and configured to read the data from the external memory in the burst mode, temporarily store the read data as the back FIFO output data and output the back FIFO output data in response to an output valid signal, wherein the memory controller comprises: a controller configured to output a front control signal, a back control signal, a memory control signal, and a data buffer control signal, in response to the input valid signal and the output valid signal; a front FIFO confimed to temporarily store the front FIFO input data and output the stored front FIFO input data as the front FIFO output data, in response to the front control signal; a back FIFO configured to temporarily store the back FIFO input data and output the stored back FIFO input data as the back FIFO output data in response to the back control signal; and a data buffer configured to output the front FIFO output data to the external memory or output data output from the external memory as the back FIFO input data, in response to the data buffer control signal, wherein the external memory is configured to write data input from the data buffer in the burst mode or read stored data in the burst mode to output the data to the data buffer, in response to the memory control signal.