Patent ID: 7095124

Claim:
A semiconductor device comprising: a semiconductor chip in which a multilayer interconnection is formed on a silicon substrate and includes a dual damascene interconnection formed of copper embedded in an interlayer insulation film with a low relative dielectric constant through a barrier metal film; and a sealing resin layer which coats the semiconductor chip, wherein, the sealing resin layer meets, in coefficient of linear expansion (α) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1) E <0.891/{(α−α s ) 2 ×h} (1) where E represents the Young's modulus (GPa) of the sealing resin at room temperature; α represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature; αs represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate; and h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.