Patent ID: 7451293

Claim:
A computer system, comprising: an instruction sequencing unit configured to sequence instructions for manipulating data and to transmit the sequenced instructions; an array of processing engines configured to receive instructions corresponding to the sequenced instructions, each processing engine of the array of processing engines being configured to receive the data, and having: a first memory configured to store the data; a decision unit configured to store decision state; a Boolean unit configured to store a logic state and to modify the logic state as dictated by the received instructions; an integer unit configured to conditionally perform integer operations on the stored data as dictated by the stored decision state, the received instructions, and the logic state, so as to generate integer result data; and a second memory configured to store I/O data; wherein the Boolean unit is configured to modify the logic state in the same clock cycle as the integer unit performs the integer operations; and an I/O controller separate from the instruction sequencing unit configured to transmit the I/O data to, and receive the I/O data from, the array of processing engines in parallel with the sequencing of instructions and the transmitting of the sequenced instructions by the instruction sequencing unit.