Patent ID: 8350589

Claim:
An integrated circuit having a monitor circuit for monitoring timing in a critical path in the integrated circuit, the critical path having a target timing margin, the monitor circuit comprising: a first shift register having an input and an output, the first shift register including a delay circuit that applies a delay value to a received signal; a second shift register having an input and an output, wherein the inputs of the first and second shift registers are connected together to form a signal input node capable of receiving an input signal; and a logic circuit having an output and at least two inputs, each input connected to a corresponding one of the outputs of the first and second shift registers, wherein the output of the logic circuit indicates whether the target timing margin is satisfied or not satisfied, wherein: the first shift register comprises: a first flip-flop having an input connected to the signal input node and an output; the delay circuit connected to the output of the first flip-flop, and a second flip-flop having an input connected to the delay circuit; and the second shift register comprises: a third flip-flop having an input connected to the signal input node and an output; and a fourth flip-flop having an input connected to the output of the third flip-flop; and the delay circuit comprises: a gross-delay element adapted to provide a gross delay value; and a fine-delay detector circuit adapted to generate, based on the gross delay value, an output signal indicating the extent to which the target timing margin is satisfied.