Patent ID: 6858442

Claim:
A process for forming an integrated circuit comprising: providing a substrate prepared with: a transistor having first and second diffusion regions and a gate, a capacitor having top and bottom electrodes with a capacitor dielectric layer between the electrodes, a bottom electrode plug coupling the bottom electrode to the first diffusion region; depositing an interlevel dielectric layer on the substrate covering the capacitor; depositing a surface barrier layer over the interlevel dielectric layer; forming a hard mask over the surface barrier layer, the hard mask and the surface barrier layer comprising different materials; patterning the mask layer to form an opening corresponding to a deep contact via; forming the deep contact via in the interlevel dielectric layer, the contact via includes substantially vertical sidewalls; depositing a dielectric barrier layer on the substrate, the dielectric barrier layer lines the sidewalls and bottom of the contact via; etching the substrate to remove horizontal components of the dielectric barrier layer; and forming a contact plug in the deep contact via, the contact plug providing electrical coupling to the second diffusion region.