Patent ID: 7272677

Claim:
A serial interface for use in a programmable logic device, said serial interface including: a plurality of channels, each of said channels communicating between a parallel domain clocked by a parallel clock and a serial domain clocked by a serial clock that is a multiple of said parallel clock, each of said channels comprising at least one receiver for receiving serial data and converting said serial data to parallel data; and synchronization circuitry that aggregates signals from said plurality of channels and, when all selected ones of said channels are in an active state, initiates communication in each of said selected ones of said channels between said parallel domain and said serial domain; wherein: each said receiver comprises: circuitry for converting serial data to parallel data, a storage device for holding said converted parallel data, and a status signal generator that generates a status signal indicating that said circuitry for converting has locked on its respective converted parallel data; said synchronization circuitry comprises status signal cascade circuitry that aggregates said status signals from all selected ones of said receivers and activates reading of respective parallel data from each of said selected ones of said receivers when said aggregated status signals indicate that all of said selected ones of said receivers have locked on their respective converted parallel data; said status signal cascade circuitry comprises a gate in a respective receiver for combining said status signal of said respective receiver with said status signals of other said respective receivers; said gate comprises a two-input AND gate; a first input of said AND gate comprises said status signal of said respective receiver; a second input of said AND gate comprises an output of an AND gate in another of said receivers, said second input of said AND gate being selectable and further comprising an isolation signal; selection of said isolation signal removes any receiver above said respective receiver in said cascade from said cascade and thereby from said selected ones of said receivers; a respective AND gate of one of said receivers is at an end of said cascade circuitry; and output of said AND gate at said end of said cascade circuitry is an enable signal for enabling reading of the respective storage devices of all said selected ones of said receivers.