Patent ID: 8924697

Claim:
A method for processing interrupt requests in a hyperthreading processor that is suitable for executing at least two threads in parallel using at least two logic processors that are realized on a common chip, the at least two logic processors jointly use at least part of hardware provided by the common chip, the hyperthreading processor comprising at least a first register set provided in the hardware on the common chip and an additional register set provided in the hardware on the common chip, wherein an instruction pipeline is provided for each of the at least two threads, the method comprising: defining one of the at least two threads as a main thread for processing a program; assigning another thread of the at least two threads as an interrupt thread to the main thread, wherein independent registers provided in hardware are assigned to the at least two threads for supplying data without wait cycles to the respective threads; starting the main thread by the hyperthreading processor by processing instructions from an instruction pipeline corresponding to the main thread; receiving an interrupt request; storing interrupt data in a register of the additional register set assigned to the interrupt thread by the hyperthreading processor; after the interrupt request is received, placing the main thread in standby mode, wherein processing of the main thread is stopped and a current context of the main thread, including the corresponding instruction pipeline, is preserved; starting the processing of an interrupt routine in the interrupt thread; executing a part of the interrupt routine in the interrupt thread while the main thread is in the standby mode; transmitting a signal from the interrupt thread to the main thread after the part of the interrupt routine has been executed in the interrupt thread; resuming processing the program in the main thread after the signal from the interrupt thread has been transmitted to the main thread; and carrying out interrupt post-processing in the interrupt thread in parallel to the processing of the program in the main thread.