Patent ID: 7343444

Claim:
A memory system, comprising: a controller operable to receive a memory request and to transmit a corresponding memory request to an input/output port; a plurality of memory modules, each of the memory modules comprising: a plurality of memory devices arranged in a plurality of ranks; and a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module containing the memory hub in one of a plurality of modes; wherein the memory hub in a first of the memory modules is programmed such that the programming configures the first memory module so that all of the ranks of memory devices in the first memory module simultaneously respond to being addressed, the memory hub in a second of the memory modules is programmed such that the programming configures the second memory module so that half and only half of the ranks of memory devices in the second memory module simultaneously respond to being addressed, and the memory hub in a third of the memory modules is programmed such that the programming configures the third memory module so that each of the ranks of memory devices in the third memory module individually respond to being addressed; and a communications link coupling the input/output port of the controller to the input/output ports of the memory hubs in the respective memory modules.