Patent ID: 7842593

Claim:
A method for fabricating a semiconductor device, the method comprising the steps of: forming a recess gate having sidewalls over a semiconductor substrate defining a landing plug contact region; forming a gate spacer on a sidewall of the recess gate; soft-etching the semiconductor substrate in the landing plug contact region to form a recess having a rounded bottom and a sidewall; forming a sidewall spacer only over the gate spacer and the sidewall of the recess, wherein the sidewall spacer is thicker than the gate spacer; forming an insulating film over the semiconductor substrate including the recess gate, the recess gate spacer, and the recess; performing a planarization process on the insulating film to expose the recess gate; selectively etching the insulating film to form a landing plug contact hole; and filling the landing plug contact hole with a conductive layer to form a landing plug.