Patent ID: 7774739

Claim:
A method of designing a lithography mask on a semiconductor substrate, the method comprising: determining, by a computer, a maximum shifter width for a shifter space associated with a first set of critical dimension features on the substrate; setting a width of a shifter to be placed in a second set of features to the maximum shifter width, the second set of features being different from the first set of critical dimension features on the substrate; and if the shifter set to the maximum shifter width does not fit in a second shifter space associated with the second set of features, iteratively decreasing, by a preset increment, the width of the shifter to be placed into the second shifter space until the shifter fits in the second shifter space or until the shifter width is reduced to become equal to or less than a predetermined minimum shifter width; and flagging as a design rule violation the second shifter space for which the shifter can not fit after iteratively decreasing the width of the shifter.