Patent ID: 7272813

Claim:
A method for making an integrated circuit with an array of identical computational units on said integrated circuit, the method comprising: including a predetermined number of redundant computational units in said array of identical computational units; using a self-disabling logic in each of said identical computational units in said array, wherein said self-disabling logic is adapted to preventing loading of initialization data and operation of defective computational units, if any; and automatic re-mapping from said defective computational units to non-disabled computational units in said array for receiving said initialization data that was prevented from being loaded at said defective computational units wherein said automatic re-mapping includes using a data loading mechanism for loading said initialization data to each of said non-disabled computational units in a serial manner, said initialization data including control data, said data loading mechanism including a pointer for pointing to a current computational unit in said array for loading said initialization data, and wherein said pointer is sent through a serial connection connecting said identical computational units in said array.