Patent ID: 8264651

Claim:
A thin film transistor array comprising: a substrate; a gate line formed on the substrate, the gate line extending in a first direction; a data line insulated from the gate line, the data line extending in a second direction different from the first direction and crossing the gate line; and a pixel, wherein the pixel comprises a first pixel electrode portion comprising a plurality of spaced apart first electrode lines, the first pixel electrode portion having an associated TFT coupled to the first electrode lines, and a second pixel electrode portion comprising a plurality of spaced apart second electrode lines, the second pixel electrode portion capacitively coupled with the first pixel electrode portion; wherein a width of each of the first electrode lines of the first pixel electrode portion is narrower than a width of each of the second electrode lines of the second pixel electrode portion, and an interval between adjacent first electrode lines of the first pixel electrode portion is smaller than an interval between adjacent second electrode lines of the second pixel electrode portion.