Patent ID: 7680285

Claim:
A system, comprising: a processor coupled to computer-readable storage media containing instructions executable by the processor for implementing the following: an acoustic echo cancellation (AEC) component for controlling an acoustic echo; a capture buffer that includes capture data, the capture buffer having a capture write pointer and a capture read pointer; a render buffer that includes render data, the render buffer having a render write pointer and a render read pointer; and a clock drift compensator that adjusts the render read pointer, wherein the clock drift compensator adjusts the render read pointer by adding an error value to the render read pointer, wherein the error value is based, at least in part, on an actual difference between the render read pointer and the render write pointer, as compared with an ideal render offset between the render read pointer and the render write pointer, wherein the render read pointer is adjusted by adding the error value to the render read pointer so that the render data processed by the AEC component from the render buffer stays aligned in time with the capture data processed by the AEC component from the capture buffer to perform acoustic echo cancellation of the capture data using the render data.