Patent ID: 8742247

Claim:
A solar cell module, comprising: a substrate; a lower electrode layer having: first and second area-separating grooves thereon, the first and second area-separating grooves separating the substrate into an active area and a peripheral area surrounding the active area, the first area-separating groove being proximate to a first end of the active area and the second area-separating groove being proximate to a second end of the active area opposite the first end of the active area, and first cell-separating grooves in the active area; a semiconductor layer on the lower electrode layer, the semiconductor layer having second cell-separating grooves thereon, the second cell-separating grooves being spaced apart from the first cell-separating grooves; an upper electrode layer on the semiconductor layer, the upper electrode layer having third cell-separating grooves thereon, the third cell-separating grooves being spaced apart from the second cell-separating grooves first dummy cells in the peripheral area, the first dummy cells being spaced apart from the first and second area-separating grooves, wherein each of the first dummy cells has the lower electrode layer, the semiconductor layer, and the upper electrode layer; and second dummy cells in the peripheral area, the second dummy cells being spaced apart from the first dummy cells, wherein each of the second dummy cells has the lower electrode layer, the semiconductor layer, and the upper electrode layer, wherein: a portion of the semiconductor layer is in the first and second area-separating grooves, the portion of the semiconductor layer in the first area-separating groove directly contacts a first portion of the lower electrode layer in the peripheral area, and the semiconductor layer is completely between the first portion of the lower electrode layer and all of the upper electrode layer that overlaps the first portion of the lower electrode layer, the portion of the semiconductor layer in the second area-separating groove directly contacts a second portion of the lower electrode layer in the peripheral area, and the semiconductor layer is completely between the second portion of the lower electrode layer and all of the upper electrode layer that overlaps the second portion of the lower electrode layer the lower electrode layer of each of the second dummy cells directly contacts the portion of the semiconductor layer in the first or second area-separating grooves, and the semiconductor layer and the upper electrode layer of each of the second dummy cells are spaced apart from the semiconductor layer and the upper electrode layer in the active area.