Patent ID: 7643357

Claim:
A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture, comprising: a plurality of SRAM cells arranged into rows and columns within one or more sub arrays; power line selection circuitry associated with each column of the one or more sub arrays, the power line selection circuitry controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of each of the one or more sub arrays; wherein the power line selection circuitry is configured to locally convert a first voltage, corresponding to a cell supply voltage for a read operation of the SRAM cells, to a second voltage to be supplied to each SRAM cell selected for a write operation thereto, the second voltage being lower than the first voltage so as to facilitate a write function; and wherein the power line selection circuitry is further configured to locally convert the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.