Patent ID: 7366820

Claim:
A circuit for driving and controlling a second cache incorporated in a processor and comprising a plurality of RAMs, the circuit comprising: a decision unit that receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both; and a stop-instruction output unit that outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the decision unit wherein each of the RAMs comprises a memory-cell array, a first group of latches that input various external data items to the RAM, and a second group of latches that access the memory-cell array at prescribed timing in accordance with the data items input from the latches of the first group; and the stop-instruction output unit electrically disconnects the first group of latches and the second group of latches, or electrically disconnects the memory-cell array and the first and second group of latches.