Patent ID: 7336105

Claim:
A dynamic logic circuit having a clock input coupled to a clock signal, a plurality of logic inputs and a logic output comprising: a dynamic node pre-charged in response to a pre-charge phase of the clock signal; a logic tree for evaluating the dynamic node in response to a Boolean combination of the plurality of logic input signals and an evaluation phase of the clock signal; keeper logic having a first input coupled to the dynamic node, a second input coupled to a mode signal, a first output and a second output; and a single transistor keeper device having a first input coupled to the first output of the keeper logic, a second input coupled to the second output of the keeper logic, a power supply terminal coupled to a first voltage potential of a power supply, and a keeper terminal coupled to the dynamic node, wherein the keeper device couples the dynamic node to the first voltage potential of a power supply with a first conductivity in response to a first logic state of the dynamic node and couples the dynamic node to the first voltage potential of the power supply with a second conductivity in response to a logic combination of the first logic state of the dynamic node and a logic state of a mode signal; wherein the single transistor keeper device is a dual gate PFET having a back gate terminal coupled to the first output of the keeper logic circuit, a front gate terminal coupled to the second output of the keeper logic circuit, a drain terminal coupled to the dynamic node, and a source terminal coupled to the first voltage potential of the power supply; and wherein the dual gate PFET is an asymmetrical device and the back gate turns ON the dual gate PFET with the first conductivity, the front gate turns ON the dual gate PFET with the second conductivity and the second conductivity is greater than the first conductivity.