Patent ID: 8024631

Claim:
A scan test circuit, comprising: a plurality of tester inputs configured to receive scan test data for performance of a scan test of a circuit under test; a first set of scan chains including a first set of state variable devices; a second set of scan chains including a second set of state variable devices, the first set of state variable devices and the second set of state variable devices in communication with the plurality of tester inputs; a first compressor and a second compressor, wherein the first compressor is configured to (i) receive a first clock signal, (ii) compress first scan chain data output from the first set of state variable devices, and (iii) generate first compressor output data based on compression of the first scan chain data, and wherein the second compressor is configured to (i) receive an inversion of the first clock signal, (ii) compress second scan chain data output from the second set of state variable devices, and (iii) generate second compressor output data based on compression of the second scan chain data; and a plurality of tester outputs configured to provide output test data based on (i) the first compressor output data and (ii) the second compressor output data.