Patent ID: 8307196

Claim:
A data processing system, comprising: means for storing a first portion of an instruction, wherein the first portion of the instruction selects a vector operation; means for storing a second portion of the instruction, wherein the second portion of the instruction selects operand width used in the vector operation; means for storing a third portion of the instruction, wherein the third portion of the instruction selects one of an addition operation and a subtraction operation to be used in the vector operation; means for storing a fourth portion of the instruction, wherein the fourth portion of the instruction selects signed or unsigned for the vector operation; means for storing a fifth portion of the instruction, wherein the fifth portion of the instruction selects saturated or unsaturated for the vector operation; means for storing a sixth portion of the instruction, wherein the sixth portion of the instruction selects fractional or integer for the vector operation; means for storing a seventh portion of the instruction, wherein the seventh portion of the instruction selects one or more of an upper portion of a destination register and a lower portion of the destination register for storing a bit exact result of the vector operation; means for storing a eighth portion of the instruction, wherein the eighth portion of the instruction selects a width of the bit exact result of the vector operation; and means for storing a ninth portion of the instruction, wherein the ninth portion of the instruction selects a whether the bit exact result is stored in an accumulator as well as in the destination register.