Patent ID: 8345175

Claim:
A method of manufacturing an array substrate for an in-plane switching mode liquid crystal display device, comprising: forming a gate line, a gate electrode, and a first blocking pattern on a substrate through a first mask process; forming a gate insulating layer, an intrinsic silicon layer, an impurity-doped silicon layer, and a conductive material layer on the substrate including the gate line, the gate electrode and the first blocking pattern; forming a first semiconductor layer, a source electrode, a drain electrode, a data line, and a second semiconductor layer by patterning the conductive material layer, the impurity-doped silicon layer, and the intrinsic silicon layer through a second mask process, the data line crossing the gate line to define a pixel region and overlying the second semiconductor layer, wherein a portion of the second semiconductor layer has a width greater than a width of the data line and is disposed over the first blocking pattern; forming a passivation layer having a first contact hole exposing the drain electrode through a third mask process; and forming pixel electrodes and common electrodes through a fourth mask process, wherein the pixel electrodes contact the drain electrode through the first contact hole and alternate with the common electrodes.