Patent ID: 6845480

Claim:
A method of generating test patterns, comprising the steps of: providing a test pattern suitable for testing a test circuit; listing out and analyzing the test pattern; converting the test pattern into a digital circuit description language program and simulating the digital circuit description language program to produce a simulated test pattern, applying the simulated test pattern on the test circuit to obtain simulated test results; writing the digital circuit description language program into a memory unit; testing the test circuit using the program inside the memory unit to produce actual test results; and comparing the simulated test results with the actual test results: if the simulated results and the actual results match each other, the test circuit is repeatedly tested using the program inside the memory unit until no delay is found between loop backs; and if there is a mismatch between the simulated results and the actual results, the digital circuit description language program is adjusted and written back to the memory unit anew.