Patent ID: 8455923

Claim:
An integrated circuit formed on a substrate comprising nonvolatile memory array circuits, logic circuits and linear analog circuits, wherein the nonvolatile memory array circuits, the logic circuits and the linear analog circuits are each formed in active semiconductor areas separated by isolation regions formed of a shallow trench isolation; wherein the nonvolatile memory array circuits, the logic circuits and the linear analog circuits are in intercommunication to transfer signals and data between them and external circuitry; wherein the nonvolatile memory array circuits are formed in a triple well structure where a first deep well is formed with an impurity of a first conductivity type and a second well is formed with an impurity of a second conductivity type; and wherein the nonvolatile memory array circuits further comprises NAND-based NOR memory cells having at least two floating gate transistors serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading.