Patent ID: 7728350

Claim:
A memory cell, comprising: a semiconductor substrate with a linear arrangement of diffusion regions adapted to provide a negative differential resistance (NDR) response, the linear arrangement of diffusion regions including a first diffusion region, a second diffusion region, a third diffusion region, an intrinsic region, and a fourth diffusion region, the first and third diffusion regions being of a first type, the second and fourth diffusion regions being of a second type, the second diffusion region being positioned between the first diffusion region and the third diffusion region, the third diffusion region being positioned between the second diffusion region and the fourth diffusion region, and the intrinsic region being positioned between the third diffusion region and the fourth diffusion region; a gate separated from the second diffusion region by a gate insulator; a first conductor line connected to the first diffusion region; a second conductor line connected to the fourth diffusion region; a third conductor line connected to the gate; and wherein the memory cell is adapted to conduct charge between the first and second conductor lines through the first, second, third and fourth diffusion regions.