Patent ID: 8809964

Claim:
An electronic subsystem comprising: a semiconductor layer; at least one first transistor and at least one second transistor each with an adjustable threshold voltage and carried on one side of the semiconductor layer, a channel of the first transistor and the second transistor within the semiconductor layer; and on an opposite side of the semiconductor layer, an insulation layer including: at a predetermined first depth, a first trapping area extending at least under the channel of the at least one first transistor and including traps with a density greater than a density of traps in a third trapping area outside the first trapping area, at a predetermined second depth, a second trapping area extending at least under the channel of the at least one second transistor and including traps with a density greater than a density of traps in a fourth trapping area outside the second trapping area, the second trapping area differing from the first trapping area by at least one of the following features: the second depth is different from the first depth, or the second trapping area comprises a trap density distribution different from that of the first trapping area, or the second trapping area comprises implanted elements different from that of the first trapping area, wherein the semiconductor layer and the first and second trapping areas are capacitively coupled, such that the channel of the at least one first transistor and the at least one second transistor is fully depleted of charge carriers, the adjustable threshold voltage of the at least one first and the at least one first second transistors is determined by the density of traps in, respectively, the first and second trapping areas, and an electronic state of the at least one first and second transistors is determined by a transport of electrical charges through the respective channels of the at least one first transistor and the at least one second transistor.