Patent ID: 7659909

Claim:
An arithmetic logic unit (ALU) in a graphics processor, said ALU comprising: circuitry for performing a first operation using a first set of pixel data that is received in a pipeline register of said ALU via a graphics pipeline executed by said graphics processor, said first set of pixel data associated with a first pixel in a frame in a graphical display; and a first temporary register coupled to said circuitry that receives a result of said first operation, wherein said result of said first operation is programmably selectable for use in a second operation with a second set of pixel data that resides in said pipeline register after said first set of pixel data, said second set of pixel data also associated with said first pixel in said frame, said second set of pixel data separated from said first set of pixel data in said graphics pipeline by an intervening third set of pixel data, said third set of pixel data associated with a second pixel in said frame, wherein said first temporary register allows a result generated using said first set of pixel data to be used with said second set of pixel data in said ALU.