Patent ID: 8124961

Claim:
A single electron transistor, comprising: source/drain layers disposed apart on a substrate; at least one nanowire channel connecting the source/drain layers; a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel; a plurality of quantum dots in the portion of the nanowire channel insulated by the plurality of oxide channel areas; and a gate electrode surrounding the quantum dot, wherein the nanowire channel includes a first oxide channel area, a second oxide channel area, and a third oxide channel area, the first oxide channel area is surrounded by the gate electrode, the second oxide channel area is disposed adjacent to a first surface of the gate electrode, the third oxide channel area is disposed adjacent to a second surface of the gate electrode, and the plurality of quantum dots is between the first oxide channel area and the second oxide channel area or between the first oxide channel area and the third oxide channel area.