Patent ID: 7167031

Claim:
A synchronizing circuit comprising: a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock; a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal; and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit, wherein the phase comparator comprises a counter configured to perform a counting operation by using the third clock, a comparator configured to compare a count output of the counter with phase difference judgment region reference values, and a hysteresis circuit configured to output the frequency division ratio control signal based on a result of comparison by the comparator.