Patent ID: 8470656

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an element isolation region in a semiconductor substrate to represent an element region; forming a gate electrode over the element region; forming a first sidewall spacer having a first width over the semiconductor substrate of a first side of the gate electrode; forming a second sidewall spacer having a second width over the semiconductor substrate of a second side of the gate electrode, the second width is wider than the first width; implanting first impurities into the element region, using the gate electrode and the first sidewall spacer as a first mask, to form a first impurity region in the semiconductor substrate of the first side of the gate electrode, and using the gate electrode and the second sidewall spacer as a mask to form a second impurity region in the semiconductor substrate of the second side of the gate electrode; and activating the first impurities in the first impurity region and the second impurity region by heat treatment, wherein the first impurity region is smaller than the second impurity region, and an impurity concentration in the first impurity region is substantially equal to an impurity concentration in the second impurity region.