Patent ID: 8327057

Claim:
A device, comprising: a memory that includes a plurality of banks; and a control block to: receive requests intended for the memory, store the received requests in a same queue, generate, for each clock cycle of a plurality of clock cycles, a bank availability vector that includes a plurality of bits, each of the plurality of bits corresponding to a different one of the plurality of banks, each of the plurality of bits indicating an availability of each corresponding bank, of the plurality of banks, the availability of each bank being based on a counter associated with each bank of the plurality of banks, determine a number of the requests intended for each of the plurality of banks based on addresses associated with the requests stored in the queue, determine an order for the requests based on the determined number of the requests intended for each of the banks, determine, after determining the order for the requests, whether a particular bank, of the plurality of banks, associated with a particular request, of the requests, that is first in the determined order, is available during a particular clock cycle, the control block determining whether the particular bank is available during the particular clock cycle based on the bit, of the plurality of bits included in the bank availability vector, indicating the availability of the particular bank, and service, during the particular clock cycle, the particular request for the particular bank when the particular bank is available during the particular clock cycle.