Patent ID: 7538380

Claim:
A semiconductor device comprising: a first memory transistor; a first selective transistor; and a peripheral circuit transistor, wherein the first memory transistor comprises: a semiconductor layer; a first insulating film formed on a memory cell region of the semiconductor layer; a first electrode layer formed on the first insulating film; a first element isolating region formed of a first element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the first element isolating region isolating a first element region and being self-aligned with the first electrode layer; a second insulating film formed on the first electrode layer and the first element isolating region; and a second electrode layer formed above the second insulating film, the first selective transistor comprises: a third insulating film formed on a selective gate region of the semiconductor layer; a third electrode layer formed on the third insulating film; a second element isolating region formed of a second element isolating insulating film formed to extend through the third electrode layer and the third insulating film to reach the inner region of the semiconductor layer, the second element isolating region isolating a second element region and being self-aligned with the third electrode layer; a fourth insulating film formed on the third electrode layer and the second element isolating region, a first open portion exposing a surface of the third electrode layer being formed in the fourth insulating film; and a fourth electrode layer formed above the fourth insulating film and the exposed surface of the third electrode layer, the fourth electrode layer being electrically connected to the third electrode layer via the first open portion, the peripheral circuit transistor comprises: a fifth insulating film formed on a peripheral circuit region of the semiconductor layer; a fifth electrode layer formed on the fifth insulating film; a third element isolating region formed of a third element isolating insulating film formed to extend through the fifth electrode layer and the fifth insulating film to reach the inner region of the semiconductor layer, the third element isolating region isolating a third element region and being self-aligned with the fifth electrode layer; a sixth insulating film formed on the fifth electrode layer and the third element isolating region, a second open portion exposing a surface of the fifth electrode layer being formed in the sixth insulating film; and a sixth electrode layer formed above the sixth insulating film and the exposed surface of the fifth electrode layer, the sixth electrode layer being electrically connected to the fifth electrode layer via the second open portion, and a second gate length of the first selective transistor is longer than a first gate length of the first memory transistor and a third gate length of the peripheral circuit transistor is longer than the second gate length.