Patent ID: 8008751

Claim:
A semiconductor device comprising: an insulator layer; a first semiconductor region formed in a linear shape having an upper surface and two side surfaces along one direction on the insulator layer, the upper surface having a (001) surface, each of the two side surfaces having a (110) surface, the first semiconductor region having a <110> crystal direction as a longitudinal direction thereof and is made of Si having a uniaxial tensile strain in the <110>crystal direction; an n-channel MIS transistor formed on the first semiconductor region, the n-channel MIS transistor including a first gate electrode formed on at least the two side surfaces of the first semiconductor region through a first gate insulating film and having the <110>crystal direction as a channel length direction thereof and a first source/drain region formed on the first semiconductor region to interpose the first gate electrode therebetween; a second semiconductor region formed in a linear shape having an upper surface and two side surfaces on the insulator layer in parallel with the first semiconductor region, the upper surface having a (001) surface, each of the two side surfaces having a (110) surface, the second semiconductor region having the <110>crystal direction as a longitudinal direction thereof and is made of SiGe or Ge having a uniaxial compressive strain in the <110>crystal direction; and a p-channel MIS transistor formed on the second semiconductor region, the p-channel MIS transistor including a second gate electrode formed on at least the two side surfaces of the second semiconductor region through a second gate insulating film and having the <110>crystal direction as a channel length direction thereof and a second source/drain region formed on the second semiconductor region to interpose the second gate electrode therebetween.