Patent ID: 8619565

Claim:
An integrated circuit comprising: one or more ports to transmit and receive packets of first data on a network; and a forwarding engine to transfer the packets of the first data between the ports, wherein at least one of the ports comprises a packet generator to originate a first packet of the first data received by the at least one of the ports from the network, wherein the first packet comprises second data representing a time of generation of the first packet of the first data; a network transmit interface to transmit the first packet of the first data; a network receive interface to receive a second packet transmitted in reply to the first packet of the first data; a controller configured to calculate a network delay including a queue delay occurring when the first packet is queued for transmission based on the second data representing the time of generation of the first packet of the first data and a time of receipt or transmission of the second packet or a time of receipt of the first packet included in the second packet; an egress queue to store the packets of the first data received by the at least one of the ports from the forwarding engine; a test queue to store the packets of the first data originated by the packet generator; and a scheduler comprising (i) a first input in communication with the egress queue, (ii) a second input in communication with the test queue, and (iii) an output in communication with the controller, wherein the scheduler is configured to schedule packets in the egress queue and the test queue for transmission to the network, and wherein the controller is configured to perform network testing while also handling regular network traffic.