Patent ID: 8676871

Claim:
A semiconductor chip comprising: an instruction execution pipeline comprising: a) instruction fetch stage circuitry; b) instruction decode stage circuitry; c) execution stage circuitry comprising a functional unit to execute a first instruction and execute a second instruction, said first instruction being an instruction that multiplies two operands, said second instruction being distinct from said first instruction and being an instruction that approximates a function according to C0+C1X2+C2X2 2 , said functional unit having a multiplier circuit, said multiplier circuit having: i) a first input to receive bits of a first operand of said first instruction and receive bits of a C1 term of said second instruction, wherein a first datapath exists downstream from said first input for said first instruction and a second datapath exists downstream from said first input for said second instruction, wherein said first and second datapaths include different formatting logic; ii) a second input to receive bits of a second operand of said first instruction and receive bits of a X2 term of said second instruction.