Patent ID: 7339823

Claim:
A nonvolatile semiconductor storage apparatus comprising: a memory cell array including a plurality of memory cells capable of storing information of 2 bits or more in one memory cell; a writing control circuit for controlling a writing operation to the memory cell array; an erasing control circuit for controlling an erasing operation; a reading control circuit for controlling a reading operation; and a reading circuit capable of applying a plurality of reading methods, wherein the memory cell array is logically divided into a plurality of regions having different reading speeds, and the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions; and the reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region.