Patent ID: 8327221

Claim:
An apparatus, comprising: a plurality of bit engines to operate in parallel to process a plurality of bit edge messages corresponding to at least a first portion of a first sub-matrix of a low density parity check (LDPC) matrix and at least a second portion of the first sub-matrix of the LDPC matrix or at least a first portion of a second sub-matrix of the LDPC matrix; a plurality of check engines, communicatively coupled to the plurality of bit engines, to operate in parallel to process a plurality of check edge messages corresponding to the at least a first portion of the first sub-matrix of the LDPC matrix and the at least a second portion of the first sub-matrix of the LDPC matrix or the at least a first portion of the second sub-matrix of the LDPC matrix while the plurality of bit engines to update at least one additional plurality of bit edge messages corresponding to at least a first portion of the second sub-matrix of the LDPC matrix and at least a second portion of the second sub-matrix of the LDPC matrix or at least a first portion of a third sub-matrix of the LDPC matrix; and wherein: the apparatus to employ at least one most recently updated bit edge message corresponding to at least one of the first sub-matrix, the second sub-matrix, and the third sub-matrix to estimate an information bit encoded within a LDPC coded signal.