Patent ID: 8352532

Claim:
A circuit structure for multiplying a first number by a second number, each having a plurality of three-bit digits, the circuit structure comprising: a plurality of multipliers for pairs of the three-bit digits of the first number and the three-bit digits of the second number; wherein the multipliers produces a plurality of six-bit partial products, each multiplier producing the six-bit partial product from the pair of three-bit digits of the first and second numbers; wherein each multiplier includes a plurality of look-up tables, wherein a six-bit input of each of the look-up tables receives the pair of three-bit digits of the first and second numbers for the multiplier, and a one-bit output of each of the look-up tables of the multiplier produces a bit of the six-bit partial product for the multiplier; and a summing-tree circuit coupled to the multipliers, the summing-tree circuit including a plurality of adders arranged in a series of levels, the adders in an initial one of the levels producing a plurality of partial sums from the six-bit partial products from the multipliers, wherein for each first and successive second ones of the levels in the series, the adders in the second level produce another plurality of partial sums from the partial sums from the first level, a last one of the levels including one of the adders that produces a final product of the first and second numbers.