Patent ID: 7840622

Claim:
A method to convert a hexadecimal floating point number having an operand (H) and an exponent (E) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply-add with an A-register and a B-register accessed by a multiplier stage; a C-register accessed by a main adder stage, wherein a leading zero counting unit (LZC) is associated to the addend C-register; a control unit; a normalizer; and a rounder/reformatter; the method characterized in the following steps: loading the operand (H) into the B-register and the C-register in parallel; counting the leading zeros of the operand (H) by the leading zero counting unit while transferring the operand (H) unchanged through the multiplier stage of the FPU by multiplying the operand (H) with a neutral number; transferring the operand (H) unchanged through the main adder stage of the FPU by adding the operand (H) with a neutral number; calculating the difference of the leading zero result provided by the LZC and the input exponent (E) by the control unit and storing the difference as a Raw-Result-Exponent, wherein based on the Raw-Result-Exponent, determining a force signal (F) specifying special conditions consisting of ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’; normalizing the operand (H) in the normalizer stage of the FPU, and in parallel determining by the control unit, based on the special conditions, how to output the final result by the rounder/reformatter according to the formats consisting of: ‘use Normalized Result’, ‘force Infinity’, ‘force Maximum Number’, and ‘force Zero Result’; and outputting the final result as a binary floating point number by the rounder/reformatter according to the control unit's selection.