Patent ID: 7934075

Claim:
A group of computers integrated in a single substrate, said group of computers comprising: an input port; a first computer including memory for storing data and instructions, a processor for executing said instructions, a sequencer for providing pulses to said processor to cause the execution of said instructions, and at least two separate data communication ports; and a second computer including memory for storing data and instructions, a processor for executing said instructions, a sequencer triggered to produce pulses to cause the execution of instructions independently from said sequencer of said first computer, and at least two separate data communication ports; and wherein one of said data communication ports of said second computer is coupled to said input port; said second computer monitors said input port while said first computer accomplishes another task, said second computer being configured to handle input on said input port on behalf of said first computer and any other computers in said group of computers; a second one of said data communication ports of said second computer is coupled to one of said data communication ports of said first computer via a data bus, said data bus facilitating communication only between said second data communication port of said second computer and said data communication port of said first computer; any data transferred from said input port to said one of said data communication ports of said first computer coupled to said second one of said data communication ports of said second computer passes through said second computer; and said first computer is programmed to occasionally pause accomplishing said another task responsive to an instruction in said another task, and determine whether said second computer, responsive to said second computer receiving data on said input port, has initiated a communication with said first computer via said data bus.