Patent ID: 8726221

Claim:
A method comprising: displaying a user interface; causing, at least in part, a presentation in the user interface of a surface height topology and/or material density view of a system on chip (SOC) design that includes an IP block; modifying, by a processor and prior to a tape-out of the SOC design, a surface height topology and/or material density transition for the IP block in the SOC design based on the presentation; indicating in the presentation a low material density for the IP block, a high material density for a second IP block of the SOC design, adjacent the IP block, and an intermediate density for a third IP block of the SOC design adjacent the second IP block and remote from the IP block; and modifying by placing the third IP block between the IP block and the second IP block, to reduce the density transition between the IP block and the second IP block, wherein a high material density exceeds a density of 60%, and a low material density is less than a density of 25%.