Patent ID: 7884415

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on an upper surface of the semiconductor substrate; a plurality of gate electrodes each of which includes a floating gate electrode formed on the gate insulating film, an intergate insulating film formed on the floating gate electrode, and a control gate electrode formed on the intergate insulating film; and a plurality of inter-electrode insulating films formed on portions of the semiconductor substrate located between the plurality of gate electrodes, wherein each floating gate electrode has an upper end, a lower end and an intermediate portion between the upper and lower ends and is formed so that the intermediate portion of each floating gate electrode has a smaller length in a gate-length direction than each of the upper and lower ends of each floating gate electrode; each control gate electrode has an upper end, a lower end and an intermediate portion between the upper and lower ends and is formed so that the intermediate portion of each control gate electrode has a smaller length in a gate-length direction than each of the upper and lower ends of each control gate electrode; each inter-electrode insulating film includes a first air gap portion formed in a first portion thereof corresponding to the intermediate portion of each floating gate electrode and a second air gap portion formed in a second portion thereof corresponding to the intermediate portion of each control gate electrode; and each floating gate electrode includes a first side wall having a first recess and each control gate electrode includes a second side wall having a second recess.