Patent ID: 7185139

Claim:
An easy access dual ports structure, wherein said structure has a first port and a second port, and a CPU uses said dual ports structure to access said first port or said second port, said easy access dual ports structure comprising: a first register bank for storing values of said first port, wherein said values comprise a first status value; a second register bank for storing values of said second port, wherein said values comprise a status value; a global register for storing a control value and at least one status value of said two status values stored in said first register bank and said second register bank respectively; an address decoder coupling with said CPU to decode an address signal; and a selector for selecting one of said first register bank and said second register bank to couple with said address decoder and mapping the status value of another register bank to said global register according to said control value stored in said global register, wherein said CPU can access said first register bank or said second register bank through said address decoder.