Patent ID: 8346994

Claim:
A memory access control system, comprising: (a) an I/O access control apparatus comprising: a command receiver, which receives from an external DMA transfer requesting entity a control command that contains an address to be accessed and an ID for identifying the DMA transfer requesting entity, the address to be accessed being in a DMA address space that is a memory area used for a DMA transfer, where the DMA address space utilizes double-mapping of a DMA address both to a respective logical address that has been translated by the address translation unit and to a DMA requestor space for a respective DMA transfer requesting entity; and an access decision unit, which determines whether access of the DMA transfer requesting entity is permitted or not, by referring to an access permission/denial determination table that associates an address in the DMA address space with the ID of the DMA transfer requesting entity that is to be permitted to access the area specified by the address; and an access processing unit, which executes access of the DMA transfer requesting entity to the DMA address space, on the condition that the access has been permitted by said access decision unit; and (b) a process control apparatus comprises: a mapping unit, which sets a mapping table that associates a logical address space of a user process with the DMA address space; a processing unit for executing a main process and on which a device driver runs; a sub-processing unit for executing as a sub-process a user process assigned by the processing unit during the execution of the main process, and an address translation unit, which is configured as a part of the sub-processing unit and which translates a logical address into a physical address in the DMA address space when the user process contains instructions to access the DMA address space by specifying the logical address, so as to allow the user process to directly access the DMA address space without relying on the device driver that runs on the processing unit, where the address translation unit allows the user process to directly access a DMA requestor space when accessing the DMA address space, without relying on a device driver that is run on the processing unit, when the user process executed in the sub-processing unit issues instructions for access to the DMA address space.