Patent ID: 7475196

Claim:
A method of data processing in a data processing system including at least first and second coherency domains, wherein each of said first and second coherency domains includes at least one processor core and a memory, said method comprising: in response to an initialization operation by a processor core, said initialization operation indicating a target memory block to be initialized, a cache memory in said first coherency domain determining a coherency state of said target memory block with respect to said cache memory; in response to said determination, said cache memory selecting a scope of broadcast of an initialization request identifying the target memory block, wherein said selecting includes: selecting a narrower scope including said first coherency domain and excluding said second coherency domain in response to a determination of a first coherency state; and selecting a broader scope including said first coherency domain and said second coherency domain in response to a determination of a second coherency state; said cache memory broadcasting an initialization request with said selected scope; and in response to said initialization request, initializing said target memory block within a memory of the data processing system to an initialization value.