Patent ID: 8736236

Claim:
A master-slave interleaved boundary conduction mode (BCM) power factor correction (PFC) controller for controlling a PFC circuit with master and slave channels, said PFC controller comprising: a) a master channel controller configured to generate a master channel control signal and an inverted master channel control signal; b) a first phase shifter configured to provide a first phase shift for said master channel control signal, and to generate a delayed opening signal therefrom; c) a second phase shifter configured to provide a second phase shift for said inverted master channel control signal, and to generate a delayed shutdown signal therefrom; d) a slave channel controller configured to receive said delayed opening signal, said delayed shutdown signal, and a slave channel inductor current zero-crossing signal, and to generate a slave channel control signal therefrom, wherein said slave channel control signal and said slave channel are configured to be activated when said delayed opening signal and said slave channel inductor current zero-crossing signal are both active, and to be deactivated when said delayed shutdown signal is active; e) said slave channel controller comprising: a first RS flip-flop configured to receive said delayed shutdown signal at a reset terminal, and to generate a slave channel control signal for said slave channel; a first AND-gate configured to receive said delayed opening signal and said slave channel inductor current zero-crossing final, and to generate a slave channel opening signal therefrom, wherein said slave channel opening signal is coupled to a set terminal of said first RS flip-flop; and f) said slave channel controller further comprising: a first comparator configured to generate a first pulse signal: a first OR-gate configured to receive said first pulse signal and said delayed opening signal, and to generate a slave channel shutdown signal, wherein said slave channel shutdown signal is coupled to said reset terminal of said first RS flip-flop, wherein said slave channel is configured to be deactivated when at least one of said first pulse signal and said delayed opening signal is active.