Patent ID: 6976118

Claim:
A method for programming field programmable gate arrays (FPGA) operatively connected to a bus system of a computer device with configuration data, the method comprising by the steps of: (a) using a device driver to read the configuration data from a storage device operatively connected to the bus system of said computer device; (b) providing the configuration data to the FPGA by way of the bus system of said computer device; (c) programming the configuration data into an electrical erasable programmable read only memory (EEPROM) connected with said FPGA via a multiplexer, hereinafter referred to as a MUX element, adapted such that the configuration data is capable of being read from the FPGA to the EEPROM; (d) switching said MUX element such that the configuration data is capable of being read from said EEPROM into said FPGA; and (e) programming the configuration data from the EEPROM to said FPGA.