Patent ID: 7612596

Claim:
An internal clock generator comprising: a first internal clock signal generation circuit which receives a first internal clock signal having a first frequency and which uses the first internal clock signal to generate a second internal clock signal having a second frequency that is lower than the first frequency and which transmits the second internal clock signal; a second internal clock signal generation circuit, which receives the second internal clock signal transmitted from the first internal clock signal generating circuit and which uses the received second internal clock signal to generate a third internal clock signal having a frequency equal to the first frequency, the third internal clock signal being coupled to and controlling at least one of: a row control unit for a memory device and a column control unit for the memory device, wherein signal distortion is reduced by transmitting the second internal clock signal instead of transmitting the first internal clock signal, wherein the third internal clock signal is applied to the row control unit and the column control unit and controls an operating time point of the row control unit and the column control unit.