Patent ID: 7895026

Claim:
A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system, the method comprising: determining a component clocking rate for each of a plurality of synchronous components of the circuit design; classifying each of the plurality of synchronous components into a plurality of schedules according to the component clocking rate, wherein each schedule has a schedule clocking rate; for each clock cycle during the simulation: calculating, by a computer, a result of a modulus function of the clock cycle and the schedule clocking rate for each of the plurality of schedules; when at least one result is zero, selecting a schedule having a zero result and executing each synchronous component of the selected schedule; and when each result is non-zero, not selecting a schedule for the clock cycle; and when at least one result is zero, outputting a value determined through the executing of one of the synchronous components of the circuit design.