Patent ID: 6844621

Claim:
A semiconductor device comprising: an insulating substrate comprising a square or rectangular ceramic substrate, a top conductor pattern formed on and bonded to a top surface of the ceramic substrate, and a bottom conductor pattern formed on and bonded to a bottom surface of the ceramic substrate; a heat developing semiconductor component mounted on the top conductor pattern; and a metal base mounted in contact with the bottom conductor pattern, wherein the top conductor pattern and the heat developing semiconductor component are joined with a solder, wherein the bottom conductor pattern and the metal base are also joined with a solder, wherein the insulating substrate has means for relaxing thermal stress concentration created in the solder due to thermal cycling, and wherein the thermal stress concentration relaxing means comprises a chamfer at each of four corners of the ceramic substrate, with a chamfered dimension ranging from to 2 mm to 10 mm, the chamfered dimension being a distance along a side thereof from a corner thereof to a chamfered part an the side thereof.