Patent ID: 6868007

Claim:
A semiconductor memory system comprising: a nonvolatile memory which includes a memory cell array with memory cells of a NAND cell structure, a sense amplifier which amplifies data to be written into memory cells in the memory cell array and amplifies the data read from memory cells in the memory cell array, a page buffer which receives the page data outputted from the sense amplifier, a row decoder and control circuit which decodes a row address signal and controls the operation of the circuitry provided in the nonvolatile memory, a first decoder which decodes an address for a page copy destination and a data input command and controls the operations of the row decoder and control circuit, the sense amplifier, and the page buffer, and a second decoder which decodes an address for an ordinary program and a data input command and controls the operations of the row decoder and control circuit, the sense amplifier, and the page buffer; and a controller which includes a command issuing circuit which issues a command and supplies the command to the first decoder and the second decoder, an ECC circuit which corrects collapsed data in the buffer memory, when there is an error in the page data and the error is correctable, and a buffer memory with a data size necessary for at least one program.