Patent ID: 8901996

Claim:
A circuit, comprising: an input node configured to receive an input signal having a modulated component and a DC offset component; a modulation circuit configured to perform signal modulation and demodulation; a feedback loop comprising one or more circuit components configured to track a mean value of the input signal and to generate a DC offset correction signal from the mean value; and an adder coupled to the input node, an output of the feedback loop, and the input of the modulation circuit, wherein the adder is configured to subtract the DC offset correction signal from the input signal to generate a bipolar adjusted input signal, wherein the modulation circuit is selectively deactivated during a first operating phase so that the input signal is provided to the feedback loop and selectively activated during a second operating phase so that the bipolar adjusted input signal output from the adder is delivered to the modulation circuit before being provided to the feedback loop.