Patent ID: 7174013

Claim:
A method for producing a shortened representation of a collection of bits, comprising the steps of: inputting the collection of â€œnâ€ bits; summing a key having at least â€œnâ€ bits with the collection of bits to produce a sum; squaring the sum to produce a squared sum; performing a modular â€œpâ€ operation on the squared sum, where â€œpâ€ is at least as large as a first prime number greater than 2 n to produce a modular â€œpâ€ result; performing a modular 2 l operation on the modular â€œpâ€ result to produce a modular 2 l result where, â€œlâ€ is less than â€œnâ€; and outputting the modular 2 l result.