Patent ID: 8373261

Claim:
A chip stack package comprising: a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant directly on a first surface of the base substrate; at least one stack chip on a second surface of the base substrate, the at least one stack chip including a substrate, a chip through via electrode penetrating the substrate, and a chip pad connected to the chip through via electrode; an adhesive layer between the at least one stack chip and the second surface of the base substrate; an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant; and an external encapsulant on outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip.