Patent ID: 8452917

Claim:
A method for programming a load reduction dual inline memory module (LRDIMM), including at least one dynamic random access memory (DRAM), a serial presence detect (SPD) device for storing specified parameters for the LRDIMM, a load reduction buffer (LRB) deployed between the DRAM and a memory bus, a computing host capable of reading the specified parameters from the SPD and programming the DRAM with the specified parameters, the method comprising: (a) modifying at least one of the specified parameters to obtain modified parameters for the DRAM, comprising modifying a specified supported column address select latency (CL) bitmap; (b) programming the SPD device with the modified parameters; (c) booting the computing host, comprising: (i) determining programming values for the LRDIMM from the SPD modified parameters; (ii) modifying said programming values into corresponding modified programming values to account for a delay between the memory bus and DRAM caused by the LRB; and (iii) programming the LRDIMM, including sending the modified programming values to the DRAM.