Patent ID: 8625378

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell array including a plurality of memory cells; an input/output pad; an I/O circuit that outputs data read from the memory cells to the outside through the input/output pad and to which writing data and a command are input from the outside through the input/output pad; a first power supply voltage pad to which a first power supply voltage required for a writing, reading or erasing operation of the memory cells is applied; a second power supply voltage pad to which a second power supply voltage that is lower than the first power supply voltage and to be supplied to the I/O circuit is applied; a first voltage down-converting circuit that converts the first power supply voltage down to a first down-converted voltage that is higher than the second power supply voltage; a second voltage down-converting circuit that converts the second power supply voltage down to a second down-converted voltage that is lower than the first down-converted voltage; a first circuit group that requires a voltage equal to or lower than the first power supply voltage and equal to or higher than the second power supply voltage and to which the first down-converted voltage is supplied; and a second circuit group to which the second down-converted voltage is supplied.