Patent ID: 8759165

Claim:
A manufacturing method of an array substrate, comprising: providing a substrate; performing a first photolithography process, wherein the first photolithography process comprises: forming a first conductive layer, a gate insulating layer, a semiconductor layer and an etching stop layer on the substrate sequentially, and forming a first patterned photoresist on the etching stop layer; performing a first etching process to remove the etching stop layer and the semiconductor layer uncovered by the first patterned photoresist, and to partially expose the gate insulating layer; performing a second etching process to form a patterned gate insulating layer and a patterned etching stop layer by etching the first patterned photoresist, the etching stop layer and the gate insulating layer, and to partially expose the first conductive layer and the semiconductor layer; removing the first conductive layer uncovered by the patterned gate insulating layer to form a gate electrode; and removing the semiconductor layer uncovered by the patterned etching stop layer to form a patterned semiconductor layer, and to partially expose the patterned gate insulating layer; and performing a second photolithography process, wherein the second photolithography process comprises: forming a protective layer, wherein the protective layer at least partially covers the substrate and the patterned etching stop layer; and removing the patterned etching stop layer uncovered by the protective layer to at least partially expose the patterned semiconductor layer.