Patent ID: 7791137

Claim:
A high voltage metal oxide semiconductor (MOS) device, comprising: a substrate; an N-type epitaxial layer disposed on the substrate; an isolation structure disposed in the N-type epitaxial layer; a gate dielectric layer disposed on the N-type epitaxial layer and adjacent to the isolation structure; a gate disposed on the gate dielectric layer and a portion of the isolation structure; an N-type drain region disposed in the N-type epitaxial layer on that side of the gate close to the isolation structure; a P-type well disposed in the N-type epitaxial layer on another side of the gate; an N-type source region disposed in the P-type well; a first N-type well disposed under the isolation structure and in the N-type epitaxial layer on one side of the gate; a buried N-doped region disposed in the substrate under the N-type epitaxial layer and directly and physically contacted to the first N-type well; and a second N-type well disposed in the N-type epitaxial layer on that side of the gate close to the isolation structure and connected to the buried N-doped region, and the second N-type well and the N-type drain region have some overlapping area.