Patent ID: 8748993

Claim:
An integrated circuit structure comprising: a semiconductor substrate; a FinFET over the semiconductor substrate and comprising: a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and source/drain region at an end of the semiconductor fin; a first pair of shallow trench isolation (STI) regions comprising portions overlapped by portions of the source/drain regions, wherein two STI regions in the first pair of STI regions are separated from each other by a semiconductor strip, with edges of the two STI regions contacting edges of the semiconductor strip, and wherein the first pair of STI regions has first top surfaces; and a second pair of STI regions comprising portions overlapped by the gate electrode, wherein two additional STI regions in the second pair of STI regions are separated from each other by the semiconductor strip, wherein the two STI region and the two additional STI regions are in physical contact with the semiconductor substrate, and wherein the second pair of STI regions has second top surfaces higher than the first top surfaces.