Patent ID: 7684263

Claim:
A circuit for implementing an enhanced static random access memory (SRAM) write and read performance sort ring oscillator (PSRO) comprising: a plurality of SRAM base blocks connected together in a chain, each of said plurality of SRAM base blocks including a SRAM cell and a local evaluation block coupled to said SRAM cell; said SRAM cell including independent left wordline input and right wordline input; said SRAM cell includes an eight-transistor (8T) static random access memory (SRAM) cell and said 8T SRAM cell includes a static latch defined by a pair of parallel reverse polarity connected inverters; each of said plurality of SRAM base blocks receiving a wordline input and a reset input and providing a wordline output; said SRAM cell performing a write operation and a read operation responsive to said received wordline input; and said local evaluation block providing said wordline output responsive to said write operation and said read operation; said reset signal being applied in parallel to each of said plurality of SRAM base blocks; each of said plurality of SRAM base blocks includes a NAND gate receiving said wordline input and said reset signal, said wordline output of said SRAM base blocks being applied to said wordline input of a next one of said SRAM base blocks in said chain, and said wordline output of a last one of said plurality of SRAM base blocks in said chain providing a feedback signal coupled to said wordline input of a first one of said plurality of SRAM base blocks; and said feedback signal coupled to a ring oscillator output path.