Patent ID: 7590137

Claim:
A network processor disposed on an integrated circuit (IC), said network processor comprising: an ingress unit comprising a dual port block random access memory; an egress unit comprising a dual port block random access memory; a network interface configured to write packetized data to said ingress unit and read packetized data from said egress unit; and a coordination processor configured to coordinate movement of data between said ingress unit, said egress unit, and a system disposed on the IC, said coordination processor further comprising a network processor controller configured to extract non-packetized data from packetized data stored in said dual port block random access memory of said ingress unit by reading the packetized data starting at an address immediately following header information of the packetized data, wherein the header information is discarded, and the coordination processor outputs the non-packetized data without the header information, wherein said dual port block random access memory of said egress unit comprises read only header information which is inserted into non-packetized data written to said egress unit to packetize the non-packetized data, wherein said ingress unit, said egress unit, said network interface, and said coordination processor are disposed within the IC.