Patent ID: 7362587

Claim:
A multi-chip package comprising: a substrate; a first terminal to which a clock signal is input; a second terminal to which an inverted clock signal is input; a third terminal for outputting a data enable signal in synchronization with the clock signal or the inverted clock signal; a fourth terminal for outputting a data signal in synchronization with the clock signal or the inverted clock signal; a first semiconductor memory, provided on the substrate, which is controlled by the clock signal and the inverted clock signal, including: a first pad to which the clock signal is input, a second pad to which the inverted clock signal is input, a third pad for outputting the data enable signal, a fourth pad for outputting the data signal, a first peripheral circuit, a first circuit provided between the first pad and the first peripheral circuit, a second circuit provided between the second pad and the first peripheral circuit, a third circuit provided between the third pad and the first peripheral circuit, and a fourth circuit provided between the fourth pad and the first peripheral circuit; and a second semiconductor memory, provided on the substrate, which is controlled by the clock signal, including: a fifth pad to which the clock signal is input, a sixth pad to which the inverted clock signal is input, a seventh pad for outputting the data enable signal, an eighth pad for outputting the data signal, a second peripheral circuit, a fifth circuit provided between the fifth pad and the second peripheral circuit, a sixth circuit provided between the sixth pad and the second peripheral circuit, a seventh circuit provided between the seventh pad and the second peripheral circuit, and an eighth circuit provided between the eighth pad and the second peripheral circuit.