Patent ID: 6937527

Claim:
A triple redundant latch for reducing soft errors comprising: a) a first settable memory element; b) a second settable memory element; c) a third settable memory element; d) a first voting structure; e) a second voting structure; f) a third voting structure; g) wherein an identical logic value is set in each settable memory element; h) wherein inputs to the first, second, and third voting structures are provided by the first settable memory element, the second settable memory element, the third settable memory element and control signals used to set the settable memory elements; i) wherein an output of the first voting structure determines a logical value held on the first settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set; j) wherein an output of the second voting structure determines a logical value held on the second settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set; k) wherein an output of the third voting structure determines a logical value held on the third settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set; l) wherein a propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.