Patent ID: 7333364

Claim:
A downgradable cell-density flash-memory system comprising: a flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in the block; multi-level memory cells in the flash memory that each store B logical bits per cell, wherein the multi-level memory cells each store charge in one of 2 B levels to represent the B logical bits; a bit line coupled to a selected cell in the multi-level memory cells; a plurality of references generated from a first reference, the plurality of references being in a sequence of differing values; a plurality of comparators that generate a plurality of compare results by comparing the bit line to the plurality of references; translation logic that receives the compare results as inputs, and generates B read data bits for the selected cell; a bits-per-cell indicator stored for a selected block of the multi-level memory cells, the selected block containing the selected cell, the bits-per-cell indicator indicating when the selected cell stores B logical bits, and when the selected cell stores a downgraded number D of logical bits less than B logical bits; first downgrade logic, responsive to the bits-per-cell indicator, for blocking a least-significant of the B read data bits when the bits-per-cell indicator indicates that the selected cell stores D=B−1 logical bits; and second downgrade logic, responsive to the bits-per-cell indicator, for blocking a second least-significant of the B read data bits when the bits-per-cell indicator indicates that the selected cell stores D=B−2 logical bits; wherein B, D are whole numbers and B is at least 3; whereby least-significant bits in the B logical bits are blocked when the selected cell is downgraded by the bits-per-cell indicator.