Patent ID: 6898136

Claim:
A semiconductor memory device, comprising: a memory cell array comprising a plurality of cells; a plurality of sense amplifiers coupled to respective bit lines and respective bit-bar lines of respective cells in the plurality of cells, each of the plurality of sense amplifiers having a first terminal and a second terminal; a control signal generating circuit to generate first, second, and third control signals; a first switch to selectively couple the first terminals of the plurality of sense amplifiers to a power supply voltage terminal in response to the first control signal; a second switch to selectively couple the second terminals of the plurality of sense amplifiers to a ground voltage terminal in response to the second control signal; a third switch to selectively couple the first terminals of the plurality of sense amplifiers to a first charge recycling store in response to the third control signal; and a fourth switch to selectively couple the second terminals of the plurality of sense amplifiers to a second charge recycling store in response to the third control signal.