Patent ID: 7429880

Claim:
A precharge device comprising: a first node 301 and a second node 302 ; a series-parallel network of transistors 305 operable to electrically short-circuit the first and the second nodes together responsive to input signals; a NAND gate coupled to receive the first node and a clock signal and output signal to a third node 303 ; and a first clocking transistor M 30 comprising a first and a second current electrode and a control electrode, the first current electrode coupled to the first known voltage level, the second current electrode coupled to the first node and the control electrode coupled to the clock signal; and an evaluate transistor M 36 comprising a first and a second current electrode and a control electrode, the first current electrode coupled to the second node, the second current electrode coupled to a second known voltage level and the control electrode coupled to the clock signal; and a stabilizing element M 34 coupled to the third node to minimize erroneous functionality, loss of precharge, noise susceptibility and glitch; and clocking, circuitry for precharging the first and third nodes to the first known voltage level during a first phase of the clocking signal and for coupling the second node to the second known voltage level and evaluating the voltage on the first node as input to a first inverter to provide an output logic signal and evaluating the voltage on the third node as input to a second inverter to provide an inverted output logic signal during a second phase of the clock signal; and a first latching transistor M 31 comprising a first and a second current electrode and a control electrode, the first current electrode coupled to a first known voltage level, the second current electrode coupled to the first node and the inverted output logic signal as input to a third inverter is coupled to the control electrode.