Patent ID: 8291368

Claim:
A method for reducing a surface area of a pad limited semiconductor die, the method comprising: choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die; selecting, from the chosen outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to a single external connection pad; repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row, wherein the die pads of the common die pad group are positioned with respect to each other such that a bond wire connecting the die pads of the common die pad group to the external connection pad have a spacing less than a minimum defined bond wire spacing for the semiconductor device; adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row; repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on all of the outer die pad rows, has been selected by the selecting step; and fabricating the semiconductor die with the reduced overall length of the outer die pad row.