Patent ID: 7073140

Claim:
A method of performing crosstalk analysis for the design of an integrated circuit, comprising: generating a set of multi-variable patterns corresponding to one or more configurations of IC components; determining a delay impact of cross-talk for each of the multiple-variable patterns; analyzing an IC design to determine whether any of the multi-variable patterns are present in the IC design; and determining a performance effect on the IC design based upon the delay impacts respectively associated with the multi-variable patterns that are present in the IC design, wherein device-level simulation is performed to generate the set of multi-variable patterns and delay impact is fitted using the following fitting parameters: D=C*L+C 2 *L+C*L 2 +C 2 *L 2 +( C*L+C 2 *L+C*L 2 +C 2 *L 2 )* Ax +( C*L+C 2 *L+C*L 2 +C 2 *L 2 )* Ax 2 where C is coupling Cap ratio, L is coupling wire length (mm), and Ax is Aggressor driver size.