Patent ID: 7018935

Claim:
A method of forming a metal line of a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate comprising an underlying element and forming an interlayer insulating film thereon; (b) forming a metal line contact hole to expose a portion of the underlying element, and a metal fuse contact hole to expose a portion of the semiconductor substrate by etching a portion of the interlayer insulating film; (c) forming a metal line plug and a metal fuse plug by filling the metal line contact hole and the metal fuse contact hole with conductive materials, respectively; (d) forming a metal layer on the interlayer insulating film including the metal line plug and the metal fuse plug; (e) forming a photoresist pattern covered a metal line area including the metal line plug and a metal fuse area including the metal line plug, the photoresist pattern having at least one space between the metal line area and the metal fuse area; (f) etching the metal layer to form a metal line pattern and a metal fuse pattern, the metal line remains thinner than the metal line pattern at the space due to an etch loading effect, and the metal line pattern and the metal fuse plug being electrically connected to each other; and (g) performing an over-etching process of the metal fuse to remove the remaining metal layer at the space so that the metal line pattern and the metal fuse pattern are isolated each other.