Patent ID: 8294446

Claim:
A switching controller, comprising: a pulsewidth modulation (PWM) circuit that produces pulses at a first frequency and wherein each pulse has a period of at least a minimum pulsewidth duration; a clock circuit configured to output a clock signal to said PWM circuit; wherein said PWM circuit is configured to output pulses at the first frequency in accordance with a first clock signal; a minimum pulsewidth timer configured to initiate at an output of each pulse and to expire at the minimum pulsewidth duration; a comparator circuit that produces a current sense signal having a first state indicating a current greater than a threshold and a second state indicating the current is less than the threshold; a frequency reduction monitor circuit configured to assess the state of the current sense signal at the expiration of the minimum pulsewidth timer; wherein said frequency reduction monitor circuit is configured to output a frequency reduction signal to said clock circuit in response to determining that the current sense signal has the first state at expiration of the minimum pulsewidth timer; a restoration timer configured to initiate at the output of each pulse and to expire at after a predetermined time period that is longer than the minimum pulsewidth duration; a restoration monitor circuit configured to assess the state of the current sense signal prior to expiration of the restoration timer and at the expiration of the restoration timer; wherein said restoration monitor circuit is configured to output a frequency restoration signal to said clock circuit in response to determining that the current sense signal has the second state at expiration of the restoration timer; wherein said clock circuit is configured to decrease a frequency of the clock signal in response to receiving the frequency reduction signal; and wherein said clock circuit is configured to increase the frequency of the clock signal in response to receiving the frequency restoration signal.