Patent ID: 7535084

Claim:
A multi-chip package, comprising: a leadframe, comprising: a die pad having opposing upper and lower surfaces; and a plurality of leads surrounding the die pad, comprising a plurality of first leads and a plurality of second leads, each of the leads having an upper lead, a lower lead disposed below the upper lead and an intermediate lead connected to the upper lead and lower lead, wherein each of the lower leads having opposing upper and lower surfaces, each of the upper leads having opposing upper and lower surfaces; an upper chip attached to the upper surface of the die pad; a lower chip attached to the lower surface of the die pad; a plurality of first bonding wires electrically connecting the upper chip to the upper surfaces of the upper leads of the first leads; a plurality of second bonding wires electrically connecting the lower chip to the lower surfaces of the upper leads of the second leads; and a sealant encapsulating the upper chip, lower chip, first bonding wires and second bonding wires.