Patent ID: 8051251

Claim:
A snoop control method applied to an information processing apparatus including main memories and system controllers connected to CPUs having cache memories, the snoop control method of the system controller comprising: receiving a memory access request from any of the CPUs and notifying other system controllers of the memory access request; judging, when the memory access request from any of the CPUs for each of the cache memories in the CPU is received, for each of the cache memories, whether object data requested by the memory access request conflicts with object data requested by a prior access request received earlier than the memory access request, whether resources for transferring the object data requested by the memory access request are exhausted, and whether the object data requested by the memory access request is present in any of the cache memories; selecting a first status as a status of the cache memory, when it is judged at the judging that the object data requested by the memory access request conflicts with the object data requested by the prior access request, and selecting a second status as a status of the cache memory, when it is judged at the judging that the object data requested by the memory access request does not conflict with the object data requested by the prior access request, the resources for transferring the object data requested by the memory access request are not exhausted, and the object data requested by the memory access request is present in any of the cache memories; notifying the other system controller of a snoop processing result in which the status selected at the selecting and the cache memory are associated; and setting a final status as a first final status for retrying a snoop processing, when the first status is present in statuses of the cache memories, and setting the final status as a second final status for without retrying the snoop processing, when the first status is not present in statuses of the cache memories and the second status is present in statuses of the cache memories.