Patent ID: 6960952

Claim:
A circuit for generating an output signal with a predetermined duty cycle, comprising: a driver that generates an output signals; a detector coupled to the driver, to determine a common mode voltage of the output signal; a comparator coupled to the detector, to compare the common mode voltage of the output signal to a reference voltage for a predetermined duty cycle; a register coupled to the comparator, to store a value indicative of a difference between the common mode voltage of the output signal and the reference voltage; adjustment combining logic to combine a second value and the value stored in the register to produce an adjusted value; and a pre-driver to receive a signal corresponding to the adjusted value and to send a data signal corresponding to the output signal to the driver, wherein the value stored in the register causes the common mode voltage of the output signal to change so as to decrease the difference between the common mode voltage of the output signal and the reference voltage.