Patent ID: 8283569

Claim:
A method of fabricating an electrode array, said method comprising the steps of: depositing a first composition on a carrier wafer wherein the first composition defines a longitudinal slit and the first composition forms a first layer of a substrate; etching the carrier wafer through the longitudinal slit to define a channel underneath the first layer; depositing a second composition comprising a polymer through the longitudinal slit and onto the carrier wafer to form a tube around the channel and seal the longitudinal slit; disposing a plurality of feed lines comprised of conductive material on the substrate opposite the tube; disposing a plurality of electrodes on the substrate with each electrode electrically connected to at least one of the feed lines; etching the carrier wafer opposite the substrate to define voids with each void exposing an area of the tube; removing the areas of the tube exposed by the voids to define slots within the tube; and releasing the tube and substrate from the carrier wafer.