Patent ID: 8176292

Claim:
An apparatus, comprising: a processor; a memory; and an interface to connect the processor, memory, and a set of logics, the set of logics comprising: two or more boundary logics configured to determine a set of chunk boundaries for an object to be data reduced by a data reducer; and a control logic to control the data reducer to chunk the object based, at least in part, on the set of chunk boundaries the two or more boundary logics comprising two or more of: a run boundary logic configured to identify a set of run based chunk boundaries for the object and to add the set of run based chunk boundaries to the set of chunk boundaries; a delimiter boundary logic configured to identify a set of delimiter based chunk boundaries for the object and to add the set of delimiter based chunk boundaries to the set of chunk boundaries; a rules based boundary logic configured to identify a set of rules based chunk boundaries for the object and to add the set of rules based chunk boundaries to the set of chunk boundaries; and a data dependent boundary logic configured to identify a set of data dependent chunk boundaries for the object and to add the set of data dependent chunk boundaries to the set of chunk boundaries where the run boundary logic is configured to identify a run based chunk boundary in response to identifying a set of repeating characters, where the set of repeating characters includes at a least a threshold number of repeating characters; wherein the run boundary logic is configured to perform one or more of, run length encoding of members of the set of repeating characters, and controlling the data reducer to fun length encode members of the set of repeating characters.