Patent ID: 8198943

Claim:
An electronic circuit comprising a phase locked loop having a loop frequency selection input and including a controllable oscillator with an oscillator frequency control input, an offset control circuit coupled to the oscillator frequency control input to apply an offset to a control signal of the controllable oscillator, the offset control circuit including an offset control value determination circuit configured to determine at least a first and a second control offset value at least partly independently of one another; a control circuit with a control circuit input coupled to the loop frequency selection input and a control circuit output coupled to the offset control circuit, the control circuit being configured to cause the offset control circuit to apply the offset controlled by the first control offset value during a predetermined time interval before applying the offset according to the second control offset value, in response to a modification of the selected frequency, wherein the phase locked loop comprises a phase detector with a first input coupled to an input for receiving a reference signal, a second input coupled to an oscillator output of the controllable oscillator and an output coupled to the oscillator frequency control input, the control circuit having an input coupled to the input for the reference signal, the control circuit being configured to select the predetermined time interval based on transitions of the reference signal.