Patent ID: 6898738

Claim:
A method of comparing cache tag entries against a cache target utilizing a primary cache entry and a duplicate cache entry loaded with a same tag value, wherein: said method comprises: A) comparing a primary cache entry output from the primary cache entry against the cache target; B) comparing a duplicate cache entry output from the duplicate cache entry against the cache target; C) selecting the primary cache entry output as a cache entry output if the primary cache entry output matches the cache target; D) selecting the duplicate cache entry output as the cache entry output if the primary cache entry output does not match the cache target; E) testing a primary cache entry parity of the primary cache entry output for a primary cache entry parity result; F) testing a duplicate cache entry parity of the duplicate cache entry output for a duplicate entry parity result; G) identifying a primary cache entry hit when the primary cache entry output matches the cache target and the primary cache entry parity result is good; H) identifying a duplicate cache entry hit when the duplicate cache entry output matches the cache target and the duplicate cache entry parity result is good; I) identifying a cache entry hit when either the primary cache entry hit has been identified in step (G) or when the duplicate cache entry hit has been identified in step (H); J) comparing the primary cache entry output to the duplicate cache entry output; K) identifying a multiple bit parity error when the primary cache entry output does not match the duplicate cache entry output and the primary cache parity result is good and the duplicate cache entry parity result is good; L) identifying a both cache entries bad error when the primary cache parity result is bad and the duplicate cache entry parity result is bad; and M) identifying a fatal entry error when either a multiple bit parity error was identified in step (G) or a both cache entries bad error was identified in step (H).