Patent ID: 8332453

Claim:
A shifter comprising: a plurality of shift stages positioned within the shifter, and a detection circuit coupled to an input of a final shift stage of the plurality of shift stages, the detection circuit comprising a first decoder and a second decoder, a first gate bank coupled to an output of the first decoder, a second gate bank coupled to an output of the second decoder, and a reduction network coupled to the first and second gate banks, the shifter configured to perform a method comprising: receiving and shifting input data, by the plurality of shift stages, to generate a shifted result; receiving, by the detection circuit, a partially shifted vector from the input of the final shift stage along with a predetermined shift amount; and performing, by the detection circuit, an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel to a shifting operation performed by the final shift stage to generate the shifted result, the performing comprising: receiving, by the first and second decoders, the predetermined shift amount; receiving, by the first and second banks, upper and lower bits of the portion of the partially shifted vector; controlling the first and second gate banks, by the first and second decoders, to select specified bits of the upper and lower bits to be included in the all-one or all-zero detection operation based on the predetermined shift amount; receiving, by the reduction network, output bits from the first and second gate banks; receiving, by the reduction network, remaining bits between the upper and lower bits of the portion of the partially shifted vector; and detecting, by the reduction network, all-ones or all-zeros based on the received output bits and remaining bits.