Patent ID: 7505314

Claim:
A semiconductor memory device comprising: memory cell transistors each of which has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage, the threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors; a memory cell group in which current paths of the memory cell transistors are connected in series; a first selection transistor whose current path is connected in series to one of the memory cell transistors located closest to a source side in the memory cell group; word lines each of which is connected to the control gate of one of the memory cell transistors, upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line; and a first selection gate line which is connected to a gate of the first selection transistor.