Patent ID: 7698498

Claim:
A memory controller comprising: at least one coherent command/address input buffer to receive commands and addresses for coherent streams having sequential or nearly sequential memory access, wherein the addresses specify a memory bank and a location within the memory bank; at least one non-coherent command/address input buffer to receive commands and addresses for non-coherent streams having non-sequential or random memory access; at least one coherent arbiter, coupled to said at least one coherent command/address input buffer, to merge the commands and addresses from said at least one coherent command/address input buffer and sort the commands and addresses based on the addresses specified; at least one non-coherent arbiter, coupled to said at least one non-coherent command/address input buffer, to merge the commands and addresses from said at least one non-coherent command/address input buffer and sort the commands and addresses based on the addresses specified; at least one coherent plurality of bank buffers, coupled to the at least one coherent arbiter and associated with memory banks, to store the commands and addresses for the associated memory banks; at least one non-coherent plurality of bank buffers, coupled to the at least one non-coherent arbiter, to store the commands and addresses for the associated memory banks; and a scheduler, coupled to said at least one coherent plurality of bank buffers and at least one non-coherent plurality of bank buffers, to select the commands and addresses from said at least one coherent plurality of bank buffers and at least one non-coherent plurality of bank buffers to transact, wherein said scheduler is to operate in rounds and is to select a specific command type per round, wherein during each round said scheduler is to only select the commands and addresses having the specific command type from said at least one coherent plurality of bank buffers and at least one non-coherent plurality of bank buffers, and wherein said scheduler is to arbitrate between said at least one coherent plurality of bank buffers and said at least one non-coherent plurality of bank buffers.