Patent ID: 8754656

Claim:
A high speed test circuit receiving a tester clock from a tester for conducting a test on a circuit under test, the high speed test circuit comprising: an N-fold frequency multiplier circuit for receiving the tester clock and generating an N-fold frequency clock, wherein N is a positive real number; a test clock generator for generating a test clock according to the N-fold frequency clock and the tester clock, wherein the test clock is switchable between a high frequency (high frequency test clock) and a low frequency (low frequency test clock); a test signal generator operating under the test clock for generating a test signal to be sent to the circuit under test; and a comparator circuit comparing the test signal from the test signal generator with a response signal provided by the circuit under test in response to the test signal, to generate a comparison result, wherein the high speed test circuit tests the circuit under test according to the high frequency test clock, and performs a low speed operation according to the low frequency test clock.