Patent ID: 7049193

Claim:
In a process for fabricating a semiconductor structure, wherein the semiconductor structure comprises a core region, the core region including a passing wordline and a plurality of transistors, and a periphery region, the periphery region including one or more transistors, wherein the passing wordline is placed between two transistors of the plurality of transistors in the core region, a transistor having a transistor gate conductor and a transistor gate cap layer on the transistor gate conductor, a passing wordline having a wordline gate conductor and a wordline gate cap layer on the wordline gate conductor, wherein the passing wordline and an adjacent transistor are spaced a first distance apart; wherein adjacent transistors in the periphery region are spaced a second distance apart, or wherein the one transistor in the periphery region and an adjacent transistor in the core region are spaced a second distance apart, wherein the second distance is greater than the first distance, an improvement in the process comprising: depositing a middle-of-line liner overlying the core region and the periphery region of the semiconductor structure, such that a thickness of the middle-of-line liner in a first gap having the first distance in the core region is less than a thickness of the middle-of-line liner in a second gap having the second distance between the transistors in the periphery region.