Patent ID: 7968415

Claim:
A method of forming a CMOS device, comprising: providing a substrate having a semiconductor layer, nMOS and pMOS transistor gate electrodes formed over the semiconductor layer, and a selective n-type dopant implant performed into source and drain extension regions of the semiconductor layer adjacent to and extending partially under the nMOS gate structure; forming sidewalls to a first width on sides of the nMOS and pMOS transistor gate structures; performing a selective n-type dopant implant into shallow source and drain regions of the semiconductor layer adjacent to the nMOS transistor gate structure, using the first width sidewalls as a mask; forming sidewalls to a second width greater than the first width on the sides of the nMOS and pMOS transistor gate structures; and performing a blanket n-type dopant implant into deep source and drain regions of the semiconductor layer adjacent both the nMOS transistor gate structure and into deep source and drain regions of the semiconductor layer adjacent to the pMOS transistor gate structure, using the second width sidewalls as a mask; wherein the n-type doping by the blanket n-type dopant implant into the deep source and drain regions adjacent to the pMOS transistor gate structure is counterdoped by a selective p-type dopant implant into the deep source and drain regions of the semiconductor layer adjacent to the pMOS transistor gate structure.