Patent ID: 7877555

Claim:
A method of mapping a logical element of an integrated circuit design to a physical memory configuration, the method comprising: determining at least two potential mappings of the logical element of the integrated circuit design to the physical memory configuration; evaluating a power consumption of each potential mapping; ranking the potential mappings according to power consumption; selecting one of the potential mappings having a lowest power consumption; checking the selected potential mapping against at least one design constraint; assigning the selected potential mapping to at least one embedded memory block included in the physical memory configuration in response to a determination that the selected potential mapping satisfies the design constraint; and selecting a different one of the potential mappings in response to a determination that the selected potential mapping does not satisfy the design constraint, wherein evaluating the power consumption of each potential mapping includes determining for each potential mapping a number of embedded memory blocks; a number of active access ports associated with each embedded memory block; and an amount of associated logic circuits.