Patent ID: 8537327

Claim:
A manufacturing method for an array substrate, comprising: Step 1 , forming a gate metal film on a base substrate, applying a layer of photoresist on the gate metal film, and exposing and developing the photoresist with a double tone mask, so as to form a photoresist pattern including a first thickness region, a second thickness region and a photoresist-completely-removed region, the photoresist pattern in the first thickness region being at least located above a gate region, the photoresist pattern in the second thickness region being located above the gate line leading wire region, and the first thickness is less than the second thickness; Step 2 , etching so to remove the gate metal film corresponding to the photoresist-completely-removed region, and form a gate line, a gate electrode and a gate line leading wire; then ashing the photoresist so as to thin the photoresist by a thickness corresponding to the first thickness and remain a part of photoresist above the gate line leading wire region; Step 3 , sequentially depositing a gate insulating film, an active layer film and a source/drain metal film on the base substrate after Step 2 , applying a layer of photoresist on the source/drain metal film, and exposing and developing the photoresist with a double tone mask, so as to from a photoresist pattern including a third thickness region, a fourth thickness region and a photoresist-completely-removed region, the photoresist pattern in the third thickness region being at least located above a source/drain electrode region and a data line leading wire region, and the photoresist pattern in the fourth thickness region being located above a channel region, and the fourth thickness being less than the third thickness; Step 4 , etching so as to remove completely the active layer film and the source/drain metal film corresponding to the photoresist-completely-removed region; ashing the photoresist so as to thin it by a thickness corresponding to the fourth thickness; and then etching so as to etch the source/drain metal film and a part of the active layer film in the channel region, and form a TFT channel; and lifting off the remained photoresist pattern, and simultaneously lifting off the gate insulating film and the photoresist above the gate line leading wire region so as to expose the gate line leading wire; Step 5 , forming a protection layer and a pixel electrode on the base substrate after Step 4 by a patterning process.