Patent ID: 8531885

Claim:
A flash memory array, comprising: a matrix of a plurality of flash cell units arranged in a plurality of rows and columns, each of said flash cell units having a drain node and every two adjacent flash cell units in a column having a common source node; a plurality of word lines, each word line associated with a row of said flash cell units; a plurality of bit lines laid out perpendicular to said word lines, each bit line associated with a column of said flash cell units and connected to the drains of the flash cell units in the associated column; and a plurality of source lines laid out in parallel with said word lines, each source line associated with two adjacent rows of said flash cell units having common source nodes and connected to each common source node in the associated rows respectively through a diode; wherein each flash cell unit is a two-transistor two-bit NAND-based NOR flash cell formed on a triple P-type well, and each row of said flash cell units is associated with two word lines.