Patent ID: 7943966

Claim:
A layout of an integrated circuit device, comprising: a diffusion level layout portion including a number of diffusion region layout shapes to be formed within a portion of a substrate; a gate electrode level layout portion defined to pattern conductive features within a gate electrode level over the portion of the substrate corresponding to the diffusion level layout portion, the gate electrode level layout portion including a plurality of linear-shaped layout features placed to extend lengthwise in a first direction so as to extend parallel to each other, wherein the plurality of linear-shaped layout features are positioned in a side-by-side manner according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein the plurality of linear-shaped layout features include a first linear-shaped layout feature that forms both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, and wherein the plurality of linear-shaped layout features include a second linear-shaped layout feature that does not form a gate electrode of a transistor device, wherein the plurality of linear-shaped layout features include a third linear-shaped layout feature defined to form both a gate electrode of a second transistor of the first transistor type and a gate electrode of a second transistor of the second transistor type.