Patent ID: 8053885

Claim:
A wafer level diode package structure, comprising: a first semiconductor layer having a peripheral cutting area formed on a peripheral surface thereof; a second semiconductor layer connected with the first semiconductor layer, wherein the second semiconductor layer has an inner peripheral cutting area and an outer peripheral cutting area formed on a peripheral surface thereof, the inner peripheral cutting area of the second semiconductor layer is substantially flush with the peripheral cutting area of the first semiconductor layer, and the outer peripheral cutting area of the second semiconductor layer is exposed; an insulative layer disposed around and on the peripheral cutting area of the first semiconductor layer and the inner peripheral cutting area of the second semiconductor layer, wherein the insulative layer has a peripheral cutting area formed on a peripheral surface thereof and substantially flush with the outer peripheral cutting area of the second semiconductor layer; a first conductive structure formed on a bottom surface of the first semiconductor layer and a bottom surface of the insulative layer, wherein the first conductive structure has a peripheral cutting area formed on a peripheral surface thereof and substantially flush with the peripheral cutting area of the insulative layer; and a second conductive structure formed on a top surface of the second semiconductor layer, wherein the second conductive structure has a peripheral cutting area formed on a peripheral surface thereof and substantially flush with the outer peripheral cutting area of the second semiconductor.