Patent ID: 8680830

Claim:
A power supply device comprising: a control device including: an analog circuit unit, a digital circuit unit, and a memory circuit unit; first to Nth (where N≧2) inductors which have one ends coupled in common and supply first power to an external load; first to Nth drive units which respectively drive the first to Nth inductors; and a first bus, wherein the memory circuit unit stores a program therein, wherein the digital circuit unit includes: a processor core which executes the program; and a clock generating circuit which generates first to Nth clock signals and outputs the first to Nth clock signals to the first to Nth drive units respectively, wherein the analog circuit unit includes a first error amplifier circuit which outputs a first error amp signal to the first bus, the first error amp signal being generated by comparing a power supply voltage of the first power supplied to the external load with a first target power supply voltage set in advance and amplifying a difference between the power supply voltage and the first target power supply voltage, wherein the first drive unit generates a first pulse width modulation signal by a peak current control system using a phase of the first clock signal and the first error amp signal from the first bus and drives the first inductor, based on the first pulse width modulation signal, wherein the Nth drive unit generates an Nth pulse width modulation signal by a peak current control system using a phase of the Nth clock signal and the first error amp signal from the first bus and drives the Nth inductor, based on the Nth pulse width modulation signal, wherein the control device comprises a semiconductor chip and a semiconductor package, and wherein the processor core sets the frequencies and phases of the first to Nth clock signals at the clock generating circuit, based on the program, wherein the processor core sets any of the first to Nth clock signals at the clock generating circuit to a high impedance state, based on the program, wherein the first drive unit further includes a first detection circuit which detects whether the first clock signal is in a high impedance state, and stops the operation of driving the first inductor when the first detection circuit outputs a detection signal, and wherein the Nth drive unit further includes an Nth detection circuit which detects whether the Nth clock signal is in a high impedance state, and stops the operation of driving the Nth inductor when the Nth detection circuit outputs a detection signal.