Patent ID: 8615644

Claim:
A processor core supporting execution of multiple hardware threads, comprising: one or more instruction pipelines including execution units for executing instructions of the multiple hardware threads; an instruction fetch unit for fetching the instructions; an instruction dispatch unit for dispatching the instructions to the one or more instruction pipelines; a set of resources shared by the multiple hardware threads; and a control logic that receives an indication to disable a particular one of the multiple hardware threads, wherein the control logic signals the instruction dispatch unit to halt dispatch of instructions for the particular hardware thread, determines whether or not dispatched instructions in one or more instruction pipelines for the particular hardware thread that impact the set of shared resources have been completed, and responsive to determining that the dispatched instructions that impact the set of shared resources have completed, indicating to at least one other hardware thread that the particular hardware thread is disabled, wherein the control logic only indicates to the at least one other hardware thread that the particular hardware thread is disabled after determining that the dispatched instructions that impact the set of shared resources have completed.