Patent ID: 7265587

Claim:
Buffer circuitry comprising: a single-ended output buffer comprising at least one transistor that is activated when said buffer circuitry transmits a data signal through an output line; and pre-emphasis circuitry coupled to said single-ended output buffer and operative to activate at least one other transistor of said single-ended output buffer in response to at least one pre-emphasis input signal, wherein: said activation of said at least one other transistor increases a current that can be driven onto said output line during said transmission of said data signal; said at least one transistor and said at least one other transistor can be activated only when at least one respective enable signal has a first logical value; said at least one enable signal of said at least one other transistor is coupled to an output of said pre-emphasis circuitry; and said at least one pre-emphasis input signal is coupled to an input of said pre-emphasis circuitry.