Patent ID: 8830412

Claim:
A substrate for array process of panel display device, which comprises: at least an area corresponding to display panel, which further comprising a plurality of scan lines, a plurality of data lines, common electrode lines and a plurality of pixel units, the plurality of data lines and the plurality of scan lines being arranged in a checkerboard manner, each pixel unit electrically connected to a corresponding scan line and a corresponding data line; at least a shorting bar pad set, further comprising a plurality of scan liner pads electrically connected to the scan lines in a one-to-one correspondence manner, data liner pads electrically connected to data lines in a one-to-one correspondence manner, common electrode liner pad electrically connected to common electrode line, and color filter liner pad electrically connected to color filter substrate electrode; at least a wire serially connected to conductive hole, conductive hole being for connecting to color filter substrate electrode; at least a cell switch set, comprising a plurality of switch elements; and a PSVA mode pad set, further comprising at least a scan pad, at least a data scan pad and at least a common electrode pad; wherein a data scan pad selecting through the at least two switch elements to electrically connect to or disconnect from a same number of scan lines, data lines; common electrode pad being electrically connected to wire serially connected to conductive hole, and electrically connected to common electrode liner pad through at least another switch element; each switch element comprising: a first metal layer, electrically connected to a data scan pad or a wire serially connected to conductive hole; a second metal layer, disposed opposite to the first metal layer and electrically connected to a scan liner pad, a data liner pad or a common electrode liner pad; and an insulation layer, disposed between the first metal layer and the second metal layer; wherein before cell process, the insulation layer insulating the first metal layer and the second metal layer from each other to realize selection of electrical connection or disconnection between the switch element and a scan line, a data line or a common electrode line; during cell process, applying hard seal material to overlapping area of the first metal layer and the second metal layer so that the insulation layer being broken during pressing seal material to result in electrical connection between the first metal layer and the second metal layer to realize selection of electrical connection or disconnection between the switch element and a scan line, a data line or a common electrode line.