Patent ID: 8021748

Claim:
An interlayer dielectric layer for use in a printed wiring board, said layer formed on a lower interlayer insulating layer and said lower interlayer insulating layer having a through-hole formed therein, comprising: a curable resin disposed on the lower interlayer insulating layer and having a viahole opening with a diameter which is between 40 and 70 μm; and flaky particles dispersed in the curable resin, wherein at least one of the flaky particles has a ratio of the mean length to the mean width which is 1 to 20, the flaky particles have an aspect ratio of mean length to thickness falling with a range of 100 to 500, the interlayer dielectric layer is in contact with a conductive wiring pattern disposed on the lower interlayer insulating layer, and the conductive wiring pattern has an interline spacing of 12.5 μm or less.