Patent ID: 8466030

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a gate insulation layer and a gate electrode at predetermined areas of a semiconductor substrate; forming low density impurity areas at both sides of the gate electrode on the semiconductor substrate; forming a spacer at side walls of the gate insulation layer and the gate electrode, after forming the low density impurity areas; forming a thermal oxide layer on an exposed portion of the semiconductor substrate, adjacent to the spacer without overlapping with the spacer, and on the gate electrode, after forming the spacer; forming a source/drain area on the semiconductor substrate by implanting high density impurities at both sides of the gate electrode using the gate electrode and the spacer as an implantation mask, after forming the thermal oxide layer; forming an oxide/nitride layer on the semiconductor substrate by processing the thermal oxide layer with an nitrogen plasma process; and performing an annealing process for activating the impurities of the source/drain area.