Patent ID: 7523427

Claim:
A timing analyzer apparatus comprising: a storage device for storing path data indicating a plurality of cells constituting a timing verification target circuit in a semiconductor integrated circuit, delay data and standard deviation data of each cell, a weight for calculating a standard deviation of delay of the target circuit, and a threshold of timing verification; a standard deviation calculation device for calculating a sum of squares of standard deviations of the plurality of the cells using the path data and the standard deviation data of each cell, calculating a square root of the sum of squares, and obtaining the standard deviation of delay of the target circuit by multiplying the calculated square root by the weight; a delay calculation device for calculating delay of the target circuit by using the path data and the delay data of each cell; an evaluation value calculation device for calculating an evaluation value for timing verification by using the standard deviation of delay of the target circuit and the delay of the target circuit; a verification device for performing the timing verification by comparing the evaluation value with the threshold; and an output device for outputting a verification result.