Patent ID: 8558318

Claim:
An integrated circuit, comprising: a substrate, comprised of silicon having a first crystal lattice orientation; a layer of directly bonded silicon (DSB) having a second crystal lattice orientation formed on a top surface of said substrate; regions of STI field oxide formed in said layer of DSB such that the field oxide extends into said substrate; a layer of selective epitaxial growth (SEG) silicon having said first crystal lattice orientation on said top surface of said substrate in a first region for a first type of MOS transistor; a first type of well formed in said SEG layer and said substrate in said first region; an second type of well formed in a second region for a second type of MOS transistor in said DSB layer and said substrate that is different than said first region; a first type of MOS transistor formed on and in said first type of well; a second type of MOS transistor formed on and in said second type of well; a PMD liner formed on top surfaces of said first type of MOS transistor, said second type of MOS transistor and said field oxide region; a PMD layer formed on a top surface of said PMD liner; and contacts formed in said PMD layer and said PMD liner to make electrical connections to said first type of MOS transistor and said second type of MOS transistor.