Patent ID: 8232179

Claim:
A method for manufacturing a semiconductor device, the method comprising the steps of: providing a wafer comprising a semiconductor substrate, a first dielectric layer atop the semiconductor substrate, and a second dielectric layer atop the first dielectric layer; forming at least one recessed shallow trench isolation (STI) feature in said wafer, said recessed STI feature comprising a trench filled with a third dielectric fill material, said third dielectric fill material having a top surface substantially coplanar with or recessed below the uppermost top surface of the semiconductor substrate, wherein said second dielectric layer and said first dielectric layer are exposed along sidewalls of said trench above the top surface of said third dielectric fill material; forming a thin wet etch resistant dielectric layer over the wafer, said thin wet etch resistant dielectric layer in contact with and completely covering at least the top surface of said third dielectric fill material, said thin wet etch resistant dielectric layer comprising a fourth dielectric material that is more resistant to a wet etch process than at least said first dielectric layer, said thin wet etch resistant dielectric layer having a thickness in the range from about 10 Å-100 Å, wherein said step of forming said thin wet etch resistant dielectric layer further comprises depositing a thin amorphous dielectric layer that is in contact with and at least completely covers the top surface of said third dielectric fill and densifying said thin amorphous dielectric layer to form said thin wet etch resistant dielectric layer; depositing a fourth dielectric fill material over said thin amorphous dielectric layer; removing said fourth dielectric fill material and said thin amorphous dielectric layer from the top surface of said second dielectric layer prior to said step of densifying said thin amorphous dielectric layer; removing said second dielectric layer using a wet etch method that is selective at least to said thin wet etch resistant dielectric layer; and removing portions of said thin wet etch resistant dielectric layer above said first dielectric layer selectively to said first dielectric layer.