Patent ID: 7965273

Claim:
A buffer including: a first power source for supplying voltage; a second power source supplying lower voltage than the first power source; a first input terminal for supplying a voltage signal; a second input terminal for supplying a voltage signal, a polarity of the voltage signal of the first input terminal being opposite to a polarity of the voltage signal of the second input terminal; an input unit connected to each of the first power source, the second power source, the first input terminal, and the second input terminal; the input unit comprising: a first output terminal for outputting voltage; a seventh transistor, a first electrode of the seventh transistor connected to the first power source, a second electrode of the seventh transistor connected to the first output terminal, a gate electrode of the seventh transistor connected to the first input terminal; a fifth transistor, a first electrode of the fifth transistor connected to the first output terminal, a second electrode of the fifth transistor connected to the second power source; a sixth transistor, a first electrode of the sixth transistor connected to a gate electrode of the fifth transistor, a second electrode of the sixth transistor connected to the second power source, a gate electrode of the sixth transistor connected to the second input terminal; and an eighth transistor, a gate electrode of the eighth transistor connected to the first input terminal, the eighth transistor being coupled to the fifth transistor; and an output unit connected to each of the first power source, the second power source, and the first output terminal; the output unit including a second output terminal; the second output terminal outputting voltage of the first power source or voltage of the second power source.