Patent ID: 7060607

Claim:
A method for fabricating a semiconductor device including a semiconductor chip having first and second surfaces, comprising the steps of: providing a semiconductor chip having first and second opposing chip surfaces; forming an integrated circuit on the first chip surface, said circuit including active components, contact pads, at least one metal layer, and a mechanically strong, electrically insulating protective overcoat; forming a plurality of vias through said overcoat to access said at least one metal layer; depositing a stack of coplanar metal films on said overcoat contacting said at least one metal layer, said stack filling said vias and having at least one stress-absorbing film and an outermost being non-corrodible and metallurgically attachable film, said films having an electrically conductive seed metal layer attached to said electrically insulating overcoat and said metal-filled vias, at least one stress absorbing film over said seed metal layer of sufficient thickness to reliably absorb mechanical, thermal and impact stresses and an outercoat non-corrodable and metallurgically attachable electrically conductive layer; patterning said films into a network of lines such that said lines are located substantially vertically over said active components and are suitable for power current distribution; forming a plurality of windows in said overcoat to expose circuit contact pads; providing a pre-fabricated leadframe comprising a chip mount pad, a first plurality of segments suitable for electrical signals, and a second plurality of segments suitable for electrical power and ground; attaching said chip to said chip mount pad; attaching electrical conductors to said circuit contact pads and said first plurality of segments; and attaching electrical conductors to said network of lines and said second plurality of segments.