Patent ID: 7818626

Claim:
A memory error injector, comprising: a connector defined to connect the memory error injector to a standard memory module receptacle; a standard memory block defined to interface with the connector and operate in accordance with a standard memory specification; an error injection memory defined to store settings for a specified memory location within the standard memory block, a fixed logic state, a first number of access cycles, and a second number of access cycles; and error injection logic defined to allow normal transmission of data to or from the specified memory location for the first number of access cycles addressed to the specified memory location and force data transmitted to or from the specified memory location within the standard memory block to the fixed logic state for the second number of access cycles addressed to the specified memory location, wherein the first number of access cycles immediately precedes the second number of access cycles, wherein the error injection logic is defined to sequentially and continuously repeat a sequence of allowing normal transmission of data to or from the specified memory location for the first number of access cycles followed by forcing data transmitted to or from the specified memory location for the second number of access cycles, and wherein the error injection logic is defined to force the data to the fixed logic state during transmission of the data between the connector and the standard memory block.