Patent ID: 7463075

Claim:
A circuitry for establishing and automatically maintaining a predetermined duty cycle of a control signal, comprising: (a) a phase detector having a first input coupled to receive a data clock signal and a second input coupled to a synchronization conductor to receive a data synchronization signal, the phase detector producing a delay control signal having a value indicative of a phase difference between the data clock signal and the data synchronization signal; (b) a first delay circuit for producing a first delayed signal which is delayed relative to the data clock signal by an amount corresponding to a value of the delay control signal; and (c) a second delay circuit having an input receiving the first delayed signal and also having an output for producing the control signal by delaying the first delayed signal an amount which causes the control signal to have a predetermined duty cycle; wherein at least one delay circuit includes at least one of a current starved inverter circuitry that charges and discharges a capacitance to produce a saw-tooth signal having positive-going and negative-going half, or includes circuitry responsive to the duty cycle of the control signal for adjusting at least one of charging rate of capacitance or adjusting the duty cycle of the control signal.