Patent ID: 7788615

Claim:
A computer program product in a computer-readable storage device which is executed by a computer system for verifying that a design conforms to a desired property, said computer program product comprising: a computer-readable storage device; instructions on the computer-readable storage device for receiving a circuit design, a first initial state of said circuit design, and a property for verification with respect to said circuit design, wherein said first initial state is represented as a binary decision diagram that includes a plurality of nodes, and wherein said first initial state is further associated with an initial value that defines a value said first initial state takes at time 0; instructions on the computer-readable storage device for expanding said first initial state of said circuit design to create a superset of said first initial state containing one or more states reachable from said first initial state of said circuit design; instructions on the computer-readable storage device for synthesizing said superset to define a second initial state of said circuit design, wherein said second initial state is synthesized as a netlist by utilizing multiplexor representation over parametric variables to enable various paths through said plurality of nodes in said binary decision diagram and updating initial value mappings to appropriate synthesized gates represented in said netlist; instructions on the computer-readable storage device for overapproximating application of said superset and said second initial state to said circuit design through cutpoint insertion into said superset to obtain a modified superset, wherein said cut-point insertion replaces a gate in said netlist with a random gate; and instructions on the computer-readable storage device for verifying said property by comparing said property to said modified superset.