Patent ID: 6940106

Claim:
A semiconductor device comprising: a first conductive type of first MOS transistor which is formed in a first active area and in which a gate is configured from a first gate electrode, the first gate electrode having an end portion projecting from the first active area; a second active area arranged adjacent to the first active area; a second conductive type of second MOS transistor which is formed in the second active area and in which a gate is configured from the first gate electrode; a second conductive type of third MOS transistor which is formed in the second active area and in which a gate is configured from a second gate electrode; a third active area formed apart from the first active area; a first conductive type of fourth MOS transistor which is formed in the third active area and in which a gate is configured from a third gate electrode, the third gate electrode having an end portion projecting from the third active area; a fourth active area arranged adjacent to the third active area; a second conductive type of fifth MOS transistor which is formed in the fourth active area and in which a gate is configured from the third gate electrode; and a second conductive type of sixth MOS transistor which is formed in the fourth active area and in which a gate is configured from a fourth gate electrode, wherein the end portion of the first gate electrode projecting from the first active area is obliquely arranged relative to a gate width direction of the first MOS transistor, and the end portion of the third gate electrode projecting from the third active area is obliquely arranged relative to a gate width direction of the fourth MOS transistor.