Patent ID: 7800156

Claim:
A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) comprising: a substrate; an asymmetric non-volatile memory (NVM) cell including: a source region and a drain region diffused into the substrate and separated by a channel region; and a polycrystalline silicon (polysilicon) polycrystalline silicon floating gate at least partially disposed over the channel region; a low voltage (LV) MOSFET disposed on the substrate and including a first polysilicon gate having predefined first width that is foamed on a first gate oxide having a first oxide thickness, and first lightly doped drain (LDD) regions having a first doping concentration; and a high voltage (HV) MOSFET disposed on the substrate and including a second polysilicon gate having predefined second width that is formed on a second gate oxide, the second gate oxide having a second oxide thickness that is greater than the first oxide thickness, the HV MOSFET also including second LDD regions having a second doping concentration, wherein the polycrystalline silicon floating gate, source region and drain region are formed such that a gate-drain capacitance between said polycrystalline silicon floating gate and said drain region is substantially higher than a gate-source capacitance between said polycrystalline silicon floating gate and said source region, wherein the CMOS IC further includes means for programming the polycrystalline silicon floating gate by transferring a positive programming potential from the drain region to the polycrystalline silicon floating gate, and for erasing the polycrystalline silicon floating gate by transferring a potential lower than 0.5V from the drain region to the polycrystalline silicon floating gate, and wherein the polycrystalline silicon floating gate of said asymmetric NVM cell is formed on a third gate oxide that has the second oxide thickness, and the polycrystalline silicon floating gate comprises: an elongated first portion disposed over the channel region such that the first portion is disposed adjacent to a first section of the drain region, an elongated second portion extending into a second section of the drain region, the second section being spaced from the first section, and an implanted region disposed below the second portion of the polycrystalline silicon floating gate and abutting said first section of the drain region, said implanted region having a third doping concentration including a sum of said first doping concentration and said second doping concentration.