Patent ID: 7642826

Claim:
A DLL circuit comprising: a delay circuit to which a reference clock signal from outside is input and which outputs a first delayed clock signal obtained by delaying said reference clock signal by a delay time selected according to a first control signal and outputs a second delayed clock signal obtained by delaying said reference clock signal by a delay time selected according to a second control signal; an interpolation circuit which interpolates a phase difference between said first delayed clock signal as inputted and said second delayed clock signal as inputted so as to output an internal clock signal, comprising a first interpolation unit for interpolating a time difference between rising edges of said first delayed clock signal and said second delayed clock signal, a second interpolation unit for interpolating a time difference between falling edges of said first delayed clock signal and said second delayed clock signal, and a multiplexer for mixing and outputting output signals of said first interpolation unit and said second interpolation unit; an output circuit which generates a predetermined signal using said internal clock signal as a timing reference and outputs the same to outside; a dummy output circuit which has the same transmission characteristics as said output circuit, to which said internal clock signal is input, and which outputs a feedback clock signal having the same phase as said predetermined signal; a phase comparison circuit which compares a phase of said reference clock signal and a phase of said feedback clock signal; a first delay control circuit which controls said first control signal in a direction where both the phases are equal to each other in said phase comparison; and a second delay control circuit which controls said second control signal in a direction where both the phases are equal to each other in said phase comparison circuit, wherein said second delayed clock signal is controlled such that the delay time thereof is larger than that of said first delayed clock signal by an amount equivalent to one cycle of said reference clock signal.