Patent ID: 7280420

Claim:
A data compression circuit in a memory device, comprising: a plurality of first logic circuits, each first logic circuit for receiving data signals corresponding to a given bit location of each word of an output page of the memory device and for providing a first output signal indicative of whether each data signal has a first logic level, wherein there is a first logic circuit for each bit location of a word of the output page; a plurality of second logic circuits, each second logic circuit for receiving the data signals corresponding to the given bit location of each word of the output page of the memory device and for providing a second output signal indicative of whether each data signal has a second logic level different from the first logic level, wherein there is a second logic circuit for each bit location of a word of the output page; and a plurality of third logic circuits, each third logic circuit for receiving the first output signal and the second output signal of a corresponding pair of first and second logic circuits and for providing a third output signal indicative of whether each output signal from the corresponding pair of first and second logic circuits has the same logic level.