Patent ID: 8922471

Claim:
A driving device comprising: a plurality of shift registers couple in series, each of the shift registers having a first input signal terminal, a second input signal terminal, a first clock signal input terminal, a second clock signal input terminal, a first control signal input terminal, a second control signal input terminal, a first interim output signal terminal, a second interim output signal terminal and an output signal terminal, each of the shift registers including: a first driver driven by a first input signal input via the first input signal terminal and generating a first interim output signal controlled by a first clock signal; a second driver driven by a second input signal input via the second input signal terminal and generating a second interim output signal controlled by a second clock signal; and a buffer driven by the first interim output signal and the second interim output signal and generating an output signal output via the output signal terminal, wherein the buffer comprises a first transistor transmitting a voltage from a first voltage source having a first level as the output signal in turn-on time of the first transistor in response to the first interim output signal, a second transistor connected to a gate electrode of the first transistor to transmit a voltage having a second level for turning off the first transistor, and a third transistor having a first electrode connected to a second voltage source having a third level and a second electrode connected to the gate electrode of the first transistor and transmitting a voltage having the third level from the second voltage source in response to the second interim output signal, the third level being less than the first level; and a succeeding one of the shift registers receiving, from the first interim output signal terminal and the second interim output signal terminal of a previous one of the shift registers, the first interim output signal and the second interim output signal, respectively, at its first input signal terminal and its second input signal terminal, the first and second interim output signal terminals of the succeeding one of the shift registers being coupled to the first and second control signal input terminals, respectively, of the previous one of the shift registers.