Patent ID: 8675383

Claim:
A semiconductor device comprising: a first p-type well region, a first n-type well region, and a second p-type well region arranged in a first direction in a semiconductor substrate; a first active region formed in the first p-type well region, a second active region formed in the second p-type well region, and a third active region and a fourth active region formed in the first n-type well region and arranged in the first direction; memory cells formed by the use of the first p-type well region, the first n-type well region, and the second p-type well region and adjacent to each other in a second direction perpendicular to the first direction; and signal lines electrically connected to the memory cells, each of the memory cells including: a first n-type transistor including a first gate electrode formed over the first active region and a first n-type region and a second n-type region formed in the first active region on both sides of the first gate electrode; a second n-type transistor including a second gate electrode formed over the first active region on a second n-type region side from the first gate electrode and the second n-type region and a third n-type region formed in the first active region on both sides of the second gate electrode; a first p-type transistor including a third gate electrode formed over the third active region and electrically connected to the second gate electrode and a first p-type region and a second p-type region formed in the third active region on both sides of the third gate electrode; a third n-type transistor including a fourth gate electrode formed over the second active region and a fourth n-type region and a fifth n-type region formed in the second active region on both sides of the fourth gate electrode; a fourth n-type transistor including a fifth gate electrode formed over the second active region on a fifth n-type region side from the fourth gate electrode and the fifth n-type region and a sixth n-type region formed in the second active region on both sides of the fifth gate electrode; and a second p-type transistor including a sixth gate electrode formed over the fourth active region and electrically connected to the fifth gate electrode and a third p-type region and a fourth p-type region formed in the fourth active region on both sides of the sixth gate electrode, the second n-type region, the first p-type region, and the sixth gate electrode being electrically connected to one another and the fifth n-type region, the third p-type region, and the third gate electrode being electrically connected to one another, the signal lines including: a first word line electrically connected to the first gate electrodes of the memory cells adjacent to each other in the second direction and the first p-type well region; and a second word line electrically connected to the fourth gate electrodes of the memory cells adjacent to each other in the second direction and the second p-type well region.