Patent ID: 7957211

Claim:
A semiconductor memory device on a chip including an array of memory cells associated with a sense amplifier power supply circuit and a plurality of column access devices; and an interface coupled to the array of memory cells, the interface comprising: first delay circuitry for delaying a wordline timing pulse by a first predetermined delay amount to provide a first delayed wordline timing pulse; a first enable circuit for providing a sense amplifier enable signal in response to the wordline timing pulse and the first delayed wordline timing pulse; second delay circuitry for delaying the wordline timing pulse by a second predetermined delay amount to provide a second delayed wordline timing pulse, the second predetermined delay amount being greater than the first predetermined delay amount; a second enable circuit for providing a column select enable signal in response to the wordline timing pulse and the second delayed wordline timing pulse; and enabling circuitry configured to enable: the sense amplifier power supply circuit in response to the sense amplifier enable signal, and selected ones of the plurality of column access devices in response to the column select enable signal, after the sense amplifier power supply circuit is enabled.