Patent ID: 7734968

Claim:
A digital system, comprising: (a) N macro circuits, N being a positive integer; (b) an application-specific integrated circuit (ASIC); and (c) a shift/interface system being coupled to the N macro circuits and the ASIC, wherein, in response to the N macro circuits and the ASIC being in normal operation, the shift/interface system is configured to electrically couple each macro circuit of the N macro circuits to the ASIC, wherein, in response to the N macro circuits being tested, the shift/interface system is further configured to electrically disconnect each macro circuit of the N macro circuits from the ASIC, to receive macro circuit test data in series, then to feed the macro circuit test data to the N macro circuits, then to receive macro circuit response data from the N macro circuits, and then to scan-out the macro circuit response data in series, and wherein, in response to the ASIC being tested, the shift/interface system is further configured to electrically disconnect each macro circuit of the N macro circuits from the ASIC, to receive ASIC test data in series, then to feed the ASIC test data to the ASIC, then to receive ASIC response data from the ASIC, and then to scan-out the ASIC response data in series.