Patent ID: 8225265

Claim:
A processor-implemented method for modifying a logic circuit layout, the layout comprising a plurality of logic gates connected by conductive segments, the modification to optimize circuit propagation delays for improved circuit operation, the method comprising: inputting an initial layout of a physical electronic logic circuit having the plurality of logic gates; determining a respective size scaling factor for each of the logic gates in accordance with the initial layout and a minimum circuit delay criterion, wherein the minimum circuit delay criterion comprises a joint function of properties of at least some of the logic gates and at least some of the conductive segments; and outputting a modified logic circuit layout, wherein the modified logic circuit layout comprises a layout of the logic gates arranged in accordance with the initial layout, each of the logic gates being modified according to the respective determined size scaling factors, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay: and wherein said determining comprises selecting a respective scaling factor for logic gate i as a function of: x i opt = R 0 ( R i - 1 + R w i - 1 ) · ( C i + 1 + C w i ) C 0 · g i where: x opti equals the scaling factor; R 0 equals a specified constant resistance; C 0 equals a specified constant capacitance; R i−1 equals a respective output resistance of gate i−1; R wi equals a respective resistance of a conductive segment between logic gates i and i+1; C i+1 equals a respective input capacitance of gate i+1; C wi equals a respective capacitance of a conductive segment between logic gates i and i+1; and g i equals the logical effort of gate i, and wherein the logical effort of gate i equals (R i *C i )/(R 0 *C 0 ).