Patent ID: 7948259

Claim:
A semiconductor wafer comprising: a plurality of die regions arranged in an array; a plurality of kerf regions disposed between the die regions; a dielectric layer disposed in one of the kerf regions and in one of the die regions; a first conductive layer disposed adjacent the dielectric layer, and having a first conductive region disposed in the one of the kerf regions, and having a second conductive region disposed in the one of the die regions; a second conductive layer separated from the first conductive layer by the dielectric layer, and having a third conductive region disposed in the one of the kerf regions, and having a fourth conductive region disposed in the one of the die regions; a first test pad disposed in the one of the kerf regions; a first conducting line disposed in the one of the kerf regions and coupling the first test pad to the first conductive region; a second test pad disposed in the one of the kerf regions; a second conducting line disposed in the one of the kerf regions and coupling the second test pad to the first conductive region; and a third test pad disposed in the one of the kerf regions and coupled to the third conductive region.