Patent ID: 7700412

Claim:
A die package method, comprising: providing a wafer, and said wafer includes a top surface and a reverse surface and said wafer includes a plurality of chips and each said plurality of chips includes an active surface and there are a plurality of pads disposed on said active surface; forming a first protective layer on said top surface of said wafer and covering said plurality of pads; sawing said wafer to become said plurality of chips; providing a chip-placed frame, which includes a plurality of chip-placed areas, and a plurality of leads is used to connect each said plurality of chip-placed areas and there is a gap existed between each said plurality of chip-placed areas, and an adhesive layer is disposed on a top surface of each said plurality of chip-placed areas; pick and placing said plurality of chips on each said plurality of chip-placed areas and a reverse surface of each said plurality of chips is stuck on each said plurality of chip-placed areas by said adhesive layer; forming a polymer material on said chip-placed frame and said plurality of chips with said first protective layer thereon; placing a molding apparatus to planarize said polymer material to make said polymer material is filled between said plurality of chips and cover each said plurality of chips and said chip-placed frame; separating said molding apparatus to expose a top surface of said first protective layer on each said plurality of chips; removing said first protective layer to expose said plurality of pads of each said plurality of chips so as to the height of said polymer material is larger than each said plurality of chips; forming a patterned second protective layer to cover said exposed plurality of pads and portion of said polymer material; forming a plurality of fan-out and patterned metal traces, and each said plurality of patterned metal traces is electrically connected to said plurality of pads on said active surface of each said plurality of chips, and each said plurality of patterned metal traces includes a fan-out structure, which is extended out of said active surface of each said plurality of chips; forming a patterned third protective layer to cover said patterned metal trace and expose a portion of said fan-out structure, which is extended out of said active surface of each said plurality of chips; forming a plurality of patterned UBM (Under Bump Metallization) layers to cover a portion of said fan-out structure, which is extended out of said active surface of said chips, and said patterned UBM layer is electrically connected to said plurality of patterned metal traces; forming a plurality of conductive elements, and said conductive elements are electrically connected to patterned metal traces by said patterned UBM layer; and sawing said package structure and said leads of said chip-placed frame to form a plurality of stand alone and packaged chips.