Patent ID: 8473890

Claim:
A timing error sampling generator for determining timing violations of monitored paths, comprising: a hold delay element having an input configured to receive a clock signal and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to said clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored; a hold logic element having a first input coupled to said input of said hold delay element to receive said clock signal, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level; a setup delay element having an input configured to receive said clock signal and an output and configured to provide a setup violation delayed signal at said output by providing a second predetermined delay to said clock signal received at said input, said second predetermined delay corresponding to a setup violation time for said path to be monitored; and a setup logic element having a first input coupled to said input of said setup delay element to receive said clock signal, a second input coupled to said output of said setup delay element and an output at which said setup logic element is configured to respond to said first and second inputs to provide a clock setup signal when logic levels at said first and second inputs of said setup logic element are at an equivalent level.