Patent ID: 6950354

Claim:
A semiconductor memory, comprising: a plurality of real memory cells each of which has a real latch for storing write data and a transfer transistor connected to a storage node of the real latch; a real bit line connected to the real memory cells; a plurality of first dummy memory cells each of which has a first latch for storing a first logic and a transfer transistor connected to a storage node of the first latch; a plurality of second dummy memory cells each of which has a second latch for storing a second logic that is a reverse logic of the first logic and a transfer transistor connected to a storage node of the second latch; a dummy word line connected to gates of the transfer transistors of the first and second dummy memory cells; a dummy bit line connected to storage nodes of the first and second dummy memory cells through the transfer transistors; a dummy sense amplifier activating a sense amplifier start signal when a voltage of the dummy bit line has reached a predetermined, value due to activation of the dummy word line; and a real sense amplifier amplifying a voltage on the real bit line in response to activation of the sense amplifier start signal.