Patent ID: 7190032

Claim:
An insulated gate transistor comprising: a semiconductor thin film having a first main surface and a second main surface; a first gate insulating film formed on the first main surface of the semiconductor thin film; a first conductive gate formed on the first gate insulating film; first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film; a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film, a gate threshold voltage of the first conductive gate being controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions; a third gate insulating film formed on a portion of the second main surface of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region, an end of the third semiconductor region being disposed within a distance in which carriers of the second conductivity type diffuse from the portion of the second main surface of the semiconductor thin film; and a third conductive gate disposed in contact with the third gate insulating film.