Patent ID: 7924612

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell; a first gate control circuit that is coupled to the memory cell; and a second gate control circuit that is coupled to the memory cell, wherein the memory cell comprises: a first gate electrode that is formed above a channel region in a semiconductor substrate; a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer; and a charge trapping layer that is formed between the channel region and the second gate electrode, and that comprises a second insulating layer for trapping a charge, wherein data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer, wherein the first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor, and wherein the second gate control circuit brings the second gate electrode into a floating state, when the potential is applied to the first gate electrode.