Patent ID: 8735902

Claim:
A memory, comprising: a first array of first memory cells extending in a first direction from a first surface of a semiconductor material; a first select gate coupled to a plurality of the first memory cells of the first array of first memory cells; a second array of second memory cells extending in a second direction, opposite to the first direction, from a second surface of the semiconductor material; and a second select gate coupled to a plurality of the second memory cells of the second array of second memory cells; wherein the first array of first memory cells and the second array of second memory cells each comprise conductively doped regions in the semiconductor material; wherein the semiconductor material extends from the first array of first memory cells to the second array of second memory cells; and wherein a single source/drain region in the semiconductor material commonly couples both the first and the second select gates to a single data line and extends from the first array of first memory cells to the second array of second memory cells.