Patent ID: 7360076

Claim:
A cryptographic processing system comprising: (a) a cryptographic processor comprising: (a1) a cipher circuit configured to receive data packets and operable, upon receipt thereof, to selectively implement cipher processing of the data packets received thereby according to one of a plurality of data ciphering processes, to thereby selectively supply either cipher data packets or clear text data packets; (a2) a hash circuit coupled to selectively receive data packets from the cipher circuit and operable, upon receipt thereof, to hash process the data packets received therefrom according to one of a plurality of data hashing processes; the hash circuit including at least two hash sub-channels for selectively receiving either the cipher data packets or the clear text data packets; wherein the two hash sub-channels are configured for alternating between each successively received data packet, (a3) an input control circuit coupled to, and configured to control at least the cipher processing of the data packets by, the cipher circuit; and (a4) an output control circuit coupled to, and configured to at least control the hash processing of the data packets received by, the hash circuit; and (b) a security association data cache, coupled to the cryptographic processor, for storing security association data for at least two different security protocols to be implemented in the cipher circuit and hash circuit as necessary for each of the different security protocols.