Patent ID: 7697443

Claim:
A method of locating hardware faults in a parallel computer, the parallel computer comprising a plurality of compute nodes and a data communications network that includes data communications links connected to the compute nodes so as to organize the compute nodes as a tree, the tree characterized by a root compute node and a plurality of tiers of compute nodes, the method comprising: defining within the tree two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.