Patent ID: 8163630

Claim:
A method of manufacturing a semiconductor device, comprising: a step of using a semiconductor substrate of a first conduction type, having a structure wherein a first semiconductor layer of the first conduction type is stacked on a fourth semiconductor layer of the first conduction type, and having a concentration of an element of the first conduction type in the fourth semiconductor layer being in solid solubility less than a solid solubility limit of a semiconductor material constituting the fourth semiconductor layer, and forming a second semiconductor layer of a second conduction type on a surface layer of the first semiconductor layer, wherein an impurity concentration of the fourth semiconductor layer is in the range from 1×10 14 atoms/cc to 1×10 15 atoms/cc, and wherein at a position located in the fourth semiconductor layer, an integral value of the impurity concentration is equal to n c , the integral value obtained by integrating the impurity concentration from a boundary of the first semiconductor layer with the second semiconductor layer to the second main surface, where: n c =∈ s E c /g, ∈ s is a dielectric constant of a semiconductor of which the semiconductor device is made, q is an elementary charge, and E c is a dielectric breakdown field strength of the semiconductor, a step of forming a first electrode contacting the second semiconductor layer, a step of grinding a surface layer of the fourth semiconductor layer to make the semiconductor substrate have a desired thickness with the fourth semiconductor layer being exposed, a step of forming a third semiconductor layer of the first conduction type on a surface layer of a surface exposed by grinding the fourth semiconductor layer, and a step of forming a second electrode contacting the third semiconductor layer.