Patent ID: 8258028

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming at least two devices within a workpiece, wherein the workpiece comprises a first well comprising at least one first dopant and a second well comprising at least one second dopant disposed beneath the first well; forming at least one trench isolation structure within the workpiece between the at least two devices, the at least one trench isolation structure including a top portion and a bottom portion, a parasitic transistor being formed in the workpiece proximate the at least one trench isolation structure, the parasitic transistor having a threshold voltage, wherein forming the at least one trench isolation structure comprises forming the at least one trench isolation structure extending into the first well and at least partially into the second well; forming a thin insulating liner in the at least one trench isolation structure; filling at least the top portion of the at least one trench isolation structure with a semiconductive material; and forming a structure which causes the threshold voltage of the parasitic transistor to increase, wherein forming the structure which causes the threshold voltage of the parasitic transistor to increase comprises disposing an insulating material within the bottom portion of the at least one trench isolation structure beneath the semiconductive material, wherein disposing the insulating material comprises filling the at least one trench isolation structure within at least the second well.