Patent ID: 8416107

Claim:
A method for calibrating a digital-to-analog converter (DAC) comprising: during a pre-charge phase: grounding an X line and grounding a Y line that are inputs to a comparator; driving a thermometer code to an upper group of binary-weighted capacitors and to a surrogate capacitor that has a same capacitance value as a smallest capacitor in the upper group, for both an X-side array that has all capacitors connected to the X line and for a Y-side array that has all capacitors connected to the Y line; wherein the thermometer code drives a target capacitor low and drives lower capacitors high in the upper group when calibrating the target capacitor; wherein the thermometer code also drives low any larger capacitors that have a larger capacitance value than the target capacitor; driving low all capacitors in a lower group of binary-weighted capacitors and driving low a termination capacitor that has a same capacitance value as a smallest capacitor in the lower group, for both the X-side array and the Y-side array; during a bottom-plate sampling phase: floating the X line and the Y line to allow the comparator to compare X and Y-side voltages; during an error acquisition phase: inverting the thermometer code applied to the upper group so that the target capacitor and any larger capacitors are driven high and the lower capacitors are driven low in the X-side array; wherein charge sharing occurs between the target capacitor and the lower capacitors connected through the X line; continuing to drive the thermometer code to the upper group of the Y-side array; during a calibration search phase: driving a test sequence of high and low values onto the lower group of binary-weighted capacitors in the Y-side array; continuing to drive low all capacitors in the lower group of binary-weighted capacitors and the termination capacitor in the X-side array; comparing voltages on the X line and the Y line and adjusting the high and low values applied to the lower group until a minimum voltage difference is detected by the comparator; and storing as a calibration value for the target capacitor the high and low values applied to the lower group of the Y-side array that produced the minimum voltage difference.