Patent ID: 7776700

Claim:
A method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor having a lightly doped substrate region of a first conductivity type and a first impurity concentration extending to a surface of the semiconductor; impurity doping a first region of the first conductivity type through an opening in a first mask that exposes a first portion of said substrate region to form a first doped well having a first lateral edge extending to said surface, wherein the first doped well has a second impurity concentration that is greater than the first impurity concentration of the lightly doped substrate region; impurity doping a second region of a second, opposite, conductivity type through an opening in a second mask that exposes a second portion of said substrate region that is spaced apart from said first portion, thereby forming a second doped well and a first PN junction between the second doped well and said substrate region, wherein a portion of said PN junction extends to said surface; forming a gate electrode overlying said surface and having a gate dielectric formed therebetween, wherein a first lateral edge of said gate electrode is substantially aligned with said first edge and a second opposite edge of said gate electrode extends beyond said portion of said PN junction; implanting an impurity ion selectively into said first doped well at an angle greater than zero from an axis perpendicular to said surface, said impurity ion forming a HALO implant region in substantial self alignment with said gate electrode; impurity doping a source region of said second conductivity type at least partly in said first doped well; and impurity doping a drain region of said second conductivity type in a part of the second doped well spaced apart from said gate electrode.