Patent ID: 7759182

Claim:
A method of manufacturing an integrated circuit including a plurality of operable semiconductor devices formed on a semiconductor substrate, comprising: forming a layer of isolation material over the substrate; patterning and etching the layer of isolation material to provide areas of exposed substrate separated by isolation material; the provided areas establishing device active areas in locations on the substrate where operable semiconductor devices will be formed, and dummy active areas covering the remainder of the substrate which will be unused for operable semiconductor devices; the dummy active areas including equally sized whole dummy active areas substantially uniformly distributed over a majority of the remainder of the substrate, and lesser sized partial dummy active areas formed over parts of the remainder of the substrate too small to accommodate the size of the whole dummy areas; forming a layer of gate dielectric material over the patterned layer of isolation material, including over the provided areas of exposed substrate; forming a layer of gate electrode material over the layer of gate dielectric material; and patterning and etching the layers of gate electrode material and gate dielectric material to concurrently form patterned gate structures of substantially same height and size in the device active areas and in the dummy active areas throughout the substrate; wherein patterning and etching the layers of gate electrode material and gate dielectric material further comprises patterning and etching the layers of gate electrode material and gate dielectric material to form dividers over the isolation material between the dummy active areas concurrently with the formation of the gate structures, at locations substantially evenly spaced between neighboring dummy active areas.