Patent ID: 7682957

Claim:
A method of forming a pad and a fuse in a semiconductor device, the method comprising: forming first, second and third copper layers in a dielectric layer, the first copper layer being located in a pad region, the second and third copper layers being located in a fuse region, wherein the first, second and third copper layers are respectively connected to metal lines provided on a semiconductor substrate; forming a first insulating layer on the dielectric layer to cover the copper layers; selectively etching the first insulating layer to expose the second and third copper layers in the fuse region; forming a fuse pattern including first and second aluminum fuses on the first insulating layer in the fuse region, wherein the first aluminum fuse is connected to the exposed second copper layer, the second aluminum fuse is connected to the exposed third copper layer, and the first and second aluminum fuses are disconnected from each other mutually; forming a second insulating layer on the first and second aluminum fuses and the first insulating layer; selectively etching the first and second insulating layers to expose the underlying first copper layer in the pad region; forming an aluminum pad on the second insulating layer in the pad region, the aluminum pad being connected to the exposed first copper layer in the pad region; forming at least one third insulating layer on both the aluminum pad and the second insulating layer; forming a photoresist pattern on the third insulating layer, the photoresist pattern being formed to define a pad opening in the pad region and a fuse opening in the fuse region; and forming the pad and fuse openings by selectively etching the third insulating layer using the photoresist pattern, wherein the aluminum pad is exposed through the pad opening; and the first and second aluminum fuses are unexposed through the fuse opening.