Patent ID: 7797479

Claim:
A method comprising: performing a plurality of write operations to store data in different physical memory locations, each of the physical memory locations being associated with a logical address shared in common among the physical memory locations; storing sequence information in each of the physical memory locations, the sequence information stored in each of the physical memory locations and comprising first data indicative of a sequence number to indicate which one of the write operations occurred last, second data to indicate whether the physical memory location contains valid data and third data to indicate whether the physical memory location is associated with a blank state; and in response to a power failure, using the sequence information to reconstruct a logical-to-physical translation table indicative of a mapping between the logical address and one of the physical memory locations, comprising: constructing a temporary table comprising a first entry indicative of one of the physical memory locations and a second entry indicative of the sequence number stored in said one physical memory locations; and comparing the sequence number stored in the physical memory location to the sequence number indicated by the second entry and selectively updating the first and second entries based on the comparison.