Patent ID: 7519850

Claim:
A system comprising: an input storage unit, the input storage unit including at least one input configured to receive information from at least one processor, the input storage unit including at least one input configured to receive a clock signal, the input storage unit configured to provide a buffered input signal, the input storage unit comprising: an input setup unit, the input setup unit configured to receive information from the processor, the input setup unit configured to receive the clock signal, the input setup unit configured to provide the buffered input signal, the input setup unit comprising: a clock synchronization unit, the clock synchronization unit configured to receive the clock signal, the clock synchronization unit configured to provide a clock edge indicator signal; and an input receive unit, the input receive unit configured to receive information from the processor, the input receive unit configured to receive the clock signal, the input receive unit configured to receive the clock edge indicator signal, the input receive unit configured to provide the buffered input signal, the input receive unit comprising: an input buffer control unit, the input buffer control unit configured to receive the clock signal, the input buffer control unit configured to receive the clock edge indicator signal, the input buffer control unit configured to provide an input buffer enable signal; and an input buffer unit, the input buffer unit configured to receive information from the processor, the input buffer unit configured to receive the clock signal, the input buffer unit configured to receive the input buffer enable signal, the input buffer unit configured to provide the buffered input signal; and an input store unit, the input store unit configured to receive the buffered input signal.