Patent ID: 7179711

Claim:
A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate, with a first groove such that said first groove is formed in a region of said memory cell forming region uncovered by said first patterns, and with a second groove such that said second groove is formed in a region of said peripheral circuit region uncovered by said first patterns, wherein said first groove and said second groove extend in said semiconductor substrate, and wherein said second groove in said peripheral circuit region defines an active region of an MISFET in said peripheral circuit region; (b) filling an insulating material in said first groove and said second groove such that a upper surface of said insulating material is higher than a main surface of said substrate; (c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region; (d) after said step (c), forming first conductor patterns in said peripheral circuit region, in said memory cell forming region and over said insulating material, such that said first conductor patterns are filled between insulating material in said memory cell forming region; (e) forming an insulating film over said first conductor patterns; (f) forming a conductive film over said insulating film; and (g) patterning said conductive film and said first conductor patterns, wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell, wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and wherein, in said step (g), said conductive film of said peripheral circuit region and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.