Patent ID: 7646243

Claim:
A controlled transconductance differential input stage, comprising: a differential input stage, comprising: inverting and non-inverting input nodes; first and second complementary input stage field-effect transistors (FETs) (MN 2 ,MP 2 ) series-connected at a first node, the gate of said first input stage FET connected to said inverting node; first and second series-connected bias FETs (MN 1 ,MP 1 ) having the same polarities as said first and second input stage FETs, respectively, and arranged to conduct a first bias current, the gates of said first and second bias FETs connected to the gates of said first and second input stage FETs, respectively, such that the transconductances of said first and second input stage FETs vary with said first bias current; third and fourth complementary input stage FETs (MN 4 ,MP 4 ) series-connected at a second node, the gate of said third input stage FET connected to said non-inverting node; and third and fourth series-connected bias FETs (MN 3 ,MP 3 ) having the same polarities as said third and fourth input stage FETs, respectively, and arranged to conduct a second bias current, the gates of said third and fourth bias FETs connected to the gates of said third and fourth input stage FETs, respectively, such that the transconductances of said third and fourth input stage FETs vary with said second bias current; said first node connected to said second node; and a bias generator circuit, comprising: first and second bias generator FETs of like polarity and having their gates connected together; a first resistor having a resistance R 1 connected between a supply voltage and the source of said first bias generator FET; the drain of said first bias generator FET connected to a third node, said first bias generator FET being diode-connected; the source and drain of said second bias generator FET connected to said supply voltage and a fourth node, respectively; circuitry arranged to cause said first and second bias generator FETs to operate at unequal current densities such that said first resistor conducts a non-zero current, such that the transconductance of said second bias generator FET is inversely proportional to R 1 ; and a current mirror arranged to mirror the current in said second bias generator FET to provide said first and second bias currents, such that the transconductances of said input stage FETs are inversely proportional to R 1 .