Patent ID: 6917222

Claim:
A computer system comprising: an input device; an output device; a processor device operably coupled to said input device and said output device; and a memory device operably coupled to said processor device, said memory device including a skewed logic device, said skewed logic device selected from one of a skewed inverter rising logic device, a skewed inverter falling logic device, a skewed buffer rising logic device, a skewed buffer falling logic device, a skewed NOR falling logic device, a skewed NOR rising logic device, a skewed NAND falling logic device and a skewed NAND rising logic device, each of said logic devices including: a logic gate having a large channel width ratio for receiving an input signal and rapidly propagating an output edge onto an output signal in response to an input edge of the input signal; a reset network connected in parallel with said logic gate for resetting said output signal after said output edge has been propagated onto said output signal; and a feedback delay circuit connected in parallel with said reset network for delaying and returning said output signal back to said reset network.