Patent ID: 7248495

Claim:
A semiconductor memory device, comprising: a plurality of memory cells arranged in rows and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data, each memory cell being electrically isolated from adjacent memory cells thereto by means of a trench insulating film formed in a bottom of a cell isolating region of a trench structure, and each cell plate electrode comprising (i) a first electrode layer formed at least on a side wall of the trench and (ii) a second electrode layer formed above said trench insulating film and electrically connected to the first electrode layer formed on said side wall, said storage electrode being formed at a surface of a semiconductor region and facing to said cell plate electrode with a capacitor insulating film laid in between and being isolated from the storage electrode of an adjacent memory cell by means of the trench insulating film, and the trench being formed in said semiconductor region; a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes; a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs; and row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line.