Patent ID: 8191029

Claim:
A path monitor, comprising: a flip-flop having an input coupled to a path to monitor, a clock input coupled to a clock, and an output; comparison circuitry having an output, a first input coupled to said path and a second input coupled to said flip-flop output; first logic circuitry having a first input, a second input and an output, said first input coupled to said comparison circuitry output; and a timing error sampling generator having a clock input coupled to said clock and a first output coupled to said first logic circuitry second input; said first logic circuitry configured to respond to said first input and said second input thereof to provide a first error signal when both of said first and second inputs thereof are at a same logic level, wherein said timing error sampling generator includes a second output and said path monitor further comprises second logic circuitry having a first input, a second input and an output, said first input coupled to said comparison circuitry output, said second input coupled to said timing error sampling generator second output and said second logic circuitry configured to respond to said first and second input thereof to provide a second error signal when both of said first and second inputs thereof are at a same logic level.