Patent ID: 7749822

Claim:
A method of forming an integrated semiconductor device on a semiconductor substrate with a channel region and STI regions formed therein including a Field Effect Transistor (FET) device formed in and over said channel region adjacent to a resistor which is formed on a said STI region, said method comprising: forming a stack of layers on said substrate including a dielectric layer formed on said substrate, a conductive layer formed on said dielectric layer and an undoped polysilicon layer formed on said conductive layer; forming both an FET stack for said FET device over said channel region and a resistor stack for said resistor over a said STI region by patterning, and etching said dielectric layer, said conductive layer and said polysilicon layer with said resistor being formed from said conductive layer, with said resistor having distal ends, and with said gate electrode stack including portions of said dielectric layer, said conductive layer and said polysilicon layer; implanting dopant into said polysilicon layer of said FET stack to form a doped polysilicon gate electrode for said FET device; and forming electrical connections to said conductive layer of said resistor between said distal ends.