Patent ID: 8477542

Claim:
A semiconductor memory device, comprising: a silicon substrate; a plurality of memory layers arranged in multilayer, each memory layer including a cell array, said cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing said first lines, and a plurality of memory cells connected at intersections of said first lines and said second lines; a pulse generator operative to generate pulses required for data access to an access target memory cell in said plurality of memory cells; a control circuit operative to control said pulse generator such that the pulse output from said pulse generator has energy in accordance with the memory layer to which said access target memory cell belongs; and a current limiter operative to limit current flowing in said access target memory cell on access to said access target memory cell, wherein said control circuit controls said pulse generator based on the address of the access target memory cell and a parameter previously set at each of said plurality of memory layers.