Patent ID: 8785261

Claim:
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; forming a graphene layer on the formation substrate comprising annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane to reduce and desorb surface oxides at temperatures of about 700-900° C. and forming the graphene layer by silicon volatization at temperature of about 950° C.; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.