Patent ID: 7750389

Claim:
A vertical cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) pillar extending outwardly from a substrate, the MOSFET having a first source/drain region formed in a bottom of a trench adjacent to the pillar, a second source/drain region formed in a top of the pillar, a channel region between the first and the second source/drain regions in a sidewall of the pillar, and a gate formed in the trench and separated from the channel region by a gate insulator wherein the gate is shared by an adjacent vertical MOSFET formed in a pillar adjacent to the trench; a source line formed in the bottom of the trench adjacent to the vertical MOSFET, wherein the first source/drain region is coupled to the source line; a transmission line coupled to the second source/drain region; and wherein the gate insulator is configured to be programmed with one of a plurality of charge levels adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ) in response to operation of the vertical cell.