Patent ID: 7579243

Claim:
A method for forming split gate memory cells using a semiconductor substrate, comprising: forming a sacrificial layer; patterning the sacrificial layer to form a sacrificial structure with a first sidewall and a second sidewall; forming a layer of nanocrystals over the semiconductor substrate; depositing a first polysilicon layer over the semiconductor substrate; performing an anisotropic etch on the first polysilicon layer to form a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall; removing the sacrificial structure to leave the first polysilicon sidewall spacer and the second sidewall spacer; depositing a second polysilicon layer over the first and second polysilicon sidewall spacers and the semiconductor substrate; and performing an anisotropic etch on the second polysilicon layer to form a third polysilicon sidewall spacer adjacent to a first side of the first polysilicon sidewall spacer and a fourth polysilicon sidewall spacer adjacent to a first side of the second polysilicon sidewall spacer.