Patent ID: 8581397

Claim:
A semiconductor package comprising: a substrate comprising: a substrate body; a contact pad group having a plurality of contact pads arranged in parallel at a determined interval between two adjacent contact pads on a surface of the substrate body, dummy pads arranged at both sides of the contact pad group on the same surface of the substrate body and disposed to be electrically isolated from the contact pad group as islands; and a solder resist pattern having one or more openings formed on the same surface of the substrate body to expose the plurality of contact pads and the dummy pads; solder patterns formed on the contact pads; dummy solder patterns formed on the dummy pads; and a semiconductor chip comprising bumps electrically connected to the solder patterns and the contact pads of the contact pad group, the dummy solder patterns being electrically isolated from the semiconductor chip, wherein, the semiconductor chip, which comprised bumps electrically connected to the solder patterns and the contact pads of the contact pad group, overlaps the dummy pads arranged at both sides of the contact pad group.