Patent ID: 7341951

Claim:
A method of forming a semiconductor construction, comprising: providing a semiconductor substrate having a first region and a second region; forming a gate oxide layer across the first and second regions of the substrate; forming a silicon-containing layer over the gate oxide layer and across the first and second regions of the substrate; the silicon-containing layer having a thickness; the silicon-containing layer being n-type doped across the first region, and being p-type doped across second region; forming a titanium-containing layer over the silicon-containing layer and across the first and second regions of the substrate; forming a metal nitride over the titanium-containing layer and across the first and second regions of the substrate; forming an electrically insulative layer over the metal nitride and across the first and second regions of the substrate; providing a patterned mask over the electrically insulative layer to define a first transistor gate location over the first region of the substrate, and to define a second transistor gate location over the second region of the substrate; transferring a pattern from the patterned mask through the electrically insulative layer, the metal nitride and the titanium-containing layer, and only partially into the silicon-containing layer; the transferring of the pattern including a single etch which etches through the titanium-containing layer and into the silicon-containing layer; the partially-etched silicon-containing layer having an etched portion of its thickness and a remaining portion of its thickness; the transferring of the pattern forming a first partial gate structure over the first region and a second partial gate structure over the second region; the first and second partial gate structures having sidewalls comprising the titanium-containing layer, metal nitride, and etched portion of the silicon-containing layer thickness; forming a spacers along the sidewalls of the first and second partial gate structures; after forming the spacers, etching through the remaining portion of the silicon-containing layer thickness to form first and second transistor gates from the first and second partial gate structures; the first and second transistor gates having exposed surfaces of the silicon-containing layer; oxidizing the exposed surfaces of the silicon-containing layer of the first and second transistor gates; and forming source/drain regions within the substrate proximate the first and second transistor gates.