Patent ID: 7375397

Claim:
A semiconductor device, comprising: a support substrate; a buried oxide layer formed on the support substrate; a semiconductor layer deposited on the buried oxide layer, the semiconductor layer including device isolating regions and a plurality of device regions isolated from each other by the device isolating regions, each of the plurality of device regions including a channel region and a pair of electrode regions opposed to each other with the channel region sandwiched therebetween; a gate electrode opposed to the channel region via a gate insulating layer to form a transistor in the device regions; an interlayer insulating layer covering the gate electrode and the semiconductor layer; a first through conductor passing through the interlayer insulating layer into an electrical connection with the gate electrode; a second through conductor passing through the interlayer insulating layer, the device isolating regions, and the buried oxide layer and extending to the support substrate; and a first electrode pad and a second electrode pad formed on the interlayer insulating layer and electrically connected to the first through conductor and the second through conductor, respectively; wherein a first region of the semiconductor device is provided along an end of the interlayer insulating layer and a second region of the semiconductor device is surrounded by the first region on the interlayer insulating layer, and wherein the first electrode pad is formed on the first region, and the second electrode pad is formed on the second region.