Patent ID: 7236412

Claim:
An integrated semiconductor memory including redundant memory cells, comprising: a memory cell array including memory cells of a first memory cell type and a second memory cell type, wherein the memory cells of the first memory cell type are capable of storing data corresponding to data present at a data input terminal, and the memory cells of the second memory cell type are capable of storing data inverted with respect to the data present at the data input terminal, wherein a portion of the memory cells are the redundant memory cells, wherein the memory cells are selectable by address bits of an address and are connected to bit lines of a bit line twist, wherein the bit lines are offset with respect to one another in sections of the bit line twist; first word lines and second word lines arranged within the memory cell array in a first strip and a second strip, the first strip and the second strip being disposed on different sides of the bit line twist respectively, wherein the memory cells are drivable via the first and second word lines, and wherein a defective memory cell of either of the first and second memory cell types is replaceable by a redundant memory cell of either of the first and second memory cell types; a data inversion circuit configured to read and write data to the memory cells, wherein: the data inversion circuit writes to the redundant memory cell data corresponding to the data present at the data input terminal if the redundant memory cell and the defective memory cell are the same memory cell type; the data inversion circuit writes to the redundant memory cell data inverted with respect to the data present at the data input terminal if the defective memory cell is drivable via one of the first word lines and the redundant memory cell is drivable via one of the second word lines, and if the defective memory cell and the redundant memory cell are different memory cell types; and the data inversion circuit reads from the redundant memory cell data inverted with respect to the data present at the data input terminal if the defective memory cell is drivable via one of the first word lines and the redundant memory cell is drivable via one of the second word lines, and if the defective memory cell and the redundant memory cell are different memory cell types; and a first control unit configured to determine whether the defective and the redundant memory cells are drivable via one of the first and second word lines by comparing respective address bits of the address of the redundant and the defective memory cells.