Patent ID: 8311177

Claim:
A clock generating circuit, comprising: a phase detector, for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a filter, coupled to the phase detector, for filtering the control signal to generate a filtered control signal; a controllable oscillator, coupled to the filter, for generating a plurality of output clocks according to the filtered control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector, coupled to the controllable oscillator, for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; a feedback circuit, coupled to the phase detector and the phase selector, for generating the input clock according to the feedback clock; and a phase difference comparator, coupled to the controllable oscillator and the phase selector, for comparing the plurality of phases corresponding to the plurality output clocks respectively with a data phase of a data signal to generate a compared result, and generating the phase select signal according to the compared result.