Patent ID: 7003637

Claim:
A disk array device comprising: a plurality of hard disk drives; a plurality of channel control units for performing data transfer and reception between the channel control units and a plurality of information processing apparatuses being communicably connected thereto through a storage area network; a plurality of disk control units for performing data transfer and reception between the disk control units and said plurality of hard disk drives as communicably connected thereto; a CPU for performing control of said plurality of channel control units and said plurality of disk control units; a cache memory for storage of data being transferred and received between said channel control units and said disk control units; and a data transfer integrated circuit communicably connected via more than one bus to said channel control units, said disk control units and said CPU and also connected via a plurality of data buses to said cache memory, wherein said data transfer integrated circuit is responsive to an access request to said cache memory from one of said channel control units, said disk control units and said CPU, for providing access to said cache memory using one or more of said plurality of data buses, a number of which is determined in accordance with a transfer data length being set in the access request, said data buses are two data buses, said data transfer integrated circuit uses said two data buses to provide access to said cache memory when the transfer data length being set in the access request is longer than a predefined reference data length and, when the transfer data length set in the access request is shorter than or equal to said predefined reference data length, uses one of said data buses to get access to said cache memory, said data transfer integrated circuit includes a priority adding unit for adding, when receiving access requests to said cache memory from a plurality of ones of said channel control units or said disk control units or said CPU, an order of priority to the plurality of access requests, and said data transfer integrated circuit uses said two data buses to provide access to said cache memory when a transfer data length being set in one of said access requests with the highest order of priority is longer than said predefined reference data length and, when transfer data lengths being set in said access request with the highest order of priority and an access request with the second highest order of priority are shorter than said predefined reference data length, said data transfer integrated circuit uses one of said data buses for each of the access requests to thereby get access to said cache memory.