Patent ID: 7135902

Claim:
An apparatus including an integrated circuit with differential signal generator circuitry for providing at least one differential data signal with controlled rise and fall times and with built-in test circuitry therefor, comprising: a clock electrode via which is conveyed a data clock signal having a frequency; one or more data electrodes via which are conveyed one or more respective data signals; delay lock loop (DLL) circuitry coupled to said clock electrode and responsive to said data clock signal by generating a DLL signal substantially synchronous with said data clock signal, and by providing one or more delay control signals having respective magnitudes related to said data clock signal frequency; signal selection circuitry coupled to said clock electrode and responsive to a test control signal, a feedback signal having a frequency, and said data clock signal by conveying, as a selected signal, one of said feedback and data clock signals; signal delay circuitry coupled to said DLL circuitry and said signal selection circuitry, and responsive to at least one of said one or more delay control signals and said selected signal by providing, substantially synchronous with said selected signal, said feedback signal and a plurality of sequentially delayed clock signals having a frequency; latching circuitry coupled to said signal delay circuitry and one of said one or more data electrodes, and responsive to a portion of said plurality of sequentially delayed clock signals and one of said one or more respective data signals by providing a plurality of latched signals having respective magnitudes related to said plurality of sequentially delayed clock signals and said one of said one or more respective data signals; signal conversion circuitry coupled to said latching circuitry and responsive to said plurality of latched signals by providing a differential data signal corresponding to said one of said one or more respective data signals and having signal rise and fall times related to said plurality of sequentially delayed clock signals; and frequency comparison circuitry coupled to said clock electrode and said signal delay circuitry, and responsive to said data clock signal and one of said plurality of sequentially delayed clock signals by providing a test signal indicative of a difference between said data clock and delayed clock signal frequencies.