Patent ID: 7098712

Claim:
A register controlled delay locked loop (DLL) for generating a delay locked clock signal comprising: a clock generation unit which receives an external clock signal for generating a source clock signal by buffering the external clock signal and for generating a delay monitoring clock signal and a reference clock signal by diving the source clock signal by a natural number; a delay line unit which receives the source clock signal for generating the delay locked clock signal by delaying the source clock signal according to a delay amount of the delay line unit determined by a normal shift control signal and an acceleration shift control signal; a phase comparator for comparing phases of the reference clock signal and a feed-backed clock signal for outputting a comparison result; a shift register for generating a plurality of delay selection signals in response to the normal shift control signal and the acceleration shift control signal to thereby controls the delay amount of the delay line unit; a shift register controller for generating the normal shift control signal and the acceleration shift control signal based on the comparison result; and a delay model unit for estimating a delay amount generated while the external clock signal is passed to a data output pin to generate the feed-backed clock signal, wherein an absolute delay amount based on the acceleration shift control signal is larger than that based on the normal shift control signal.