Patent ID: 6864126

Claim:
A method for manufacturing a semiconductor device comprising: forming a gate electrode on a substrate; forming a first preliminary source/drain region with shallow junction in the substrate by performing ion implantation using the gate electrode as a mask; forming an interlayer dielectric (ILD) pattern with contact holes over the substrate including the gate electrode and the first preliminary source/drain region, the contact holes exposing the top of the gate electrode and some part of the first preliminary source/drain region; forming an expanded source/drain region by performing an ion implantation using the ILD pattern as a mask, the expanded source/drain region including the first preliminary source/drain region with shallow junction as the LDD region and a second preliminary source/drain region with deep junction; forming a silicide layer on the top of the gate electrode and the expanded source/drain region; and forming contact plugs by filling the contact holes with metal.