Patent ID: 6977200

Claim:
A method of manufacturing split gate flash memory on a substrate having a surface divided into a cell region and peripheral regions, the peripheral regions comprising a high voltage region and a low voltage region, the method comprising: forming a floating gate on the cell region; forming a first insulating film on the surface of the semiconductor substrate; selectively etching the first insulating film to remove the first insulating film from the cell region; forming a first oxide film on the surface of the semiconductor substrate to form a second insulating film on the cell region and a third insulating film on the peripheral circuit regions; selectively etching the third insulating film to remove the third insulating film formed on the low voltage region; and, forming a second oxide film on the surface of the semiconductor substrate to form a fourth insulating film on the low voltage region; wherein the second insulating film forms a control gate insulating film and a tunneling insulating film in the cell region, the third insulating film forms a high voltage gate insulating film in the high voltage region, and the fourth insulating film forms a low voltage gate insulating film in the low voltage region.