Patent ID: 7671684

Claim:
A FET bias circuit for applying a bias voltage across a gate and a source of an amplifying element FET for amplifying an input high frequency signal, the FET bias circuit comprising: a monitor element FET having a gate connected to the gate of the amplifying element FET and a source connected to the source of the amplifying element FET, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET; and a fixed bias circuit for applying the bias voltage so that the amplifying element FET enters a predetermined operating class by applying a bias voltage to the monitor element FET so that a drain current flowing to the monitor element FET enters a predetermined operating class; wherein said fixed bias circuit applies the bias voltage so that the amplifying element FET enters a predetermined operating class by applying a bias voltage to the monitor element FET in accordance with a detected voltage from the drain current of the monitor element FET and a reference voltage, which is a predetermined direct current voltage; and wherein said fixed bias circuit comprises: a first transistor having said detected voltage applied to a base; and a second transistor having said reference voltage applied to a base and an emitter voltage of said first transistor applied to an emitter and for outputting a collector current from a collector in accordance with a base-emitter voltage; wherein a bias voltage is applied to the monitor element FET in accordance with said collector current so that the bias voltage is applied for placing the amplifying element FET into a predetermined operating class.