Patent ID: 8729628

Claim:
A semiconductor device made by a method comprising: disposing an etch mask on an upper surface of a source/emitter layer of semiconductor material of a first conductivity type, wherein the source/emitter layer is on a channel layer of semiconductor material of the first conductivity type or a base layer of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel or base layer is on a drift layer of semiconductor material of the first conductivity type and wherein the drift layer is on a semiconductor substrate layer; selectively etching through the source/emitter layer and into the underlying channel or base layer through openings in the etch mask to form one or more etched features having bottom surfaces and sidewalls; removing the etch mask to expose the upper surface of the source/emitter layer; epitaxially growing a gate layer/base contact layer of semiconductor material of the second conductivity type on the upper surface of the source/emitter layer and on the bottom surfaces and sidewalls of the etched features; subsequently filling the etched features with a first planarizing material; etching through the gate layer/base contact layer on the upper surface of the source/emitter layer to expose underlying source/emitter layer; removing first planarizing material remaining after etching through the gate layer/base contact layer; anisotropically depositing a dry etch mask material on the upper surface of the source/emitter layer and on bottom surfaces of the etched features; etching the dry etch mask material to expose gate layer/base contact layer on the sidewalls of the etched features adjacent the upper surface of the source/emitter layer; filling the etched features with a second planarizing material such that the gate layer/base contact layer adjacent the source/emitter layer on the sidewalls of the etched features is exposed; etching through exposed gate layer/base contact layer on the sidewalls of the etched features adjacent the source/emitter layer to expose underlying source/emitter layer until the gate layer/base contact layer remaining in the etched features no longer contacts the source/emitter layer; and removing second planarizing material remaining after etching through exposed gate layer/base contact layer on the sidewalls of the etched features.