Patent ID: 7437634

Claim:
An apparatus, comprising: a control node of a functional circuit of an application circuit, the functional circuit having a system functional clock signal input, the application circuit disposed on an integrated circuit; a master scan flip-flop disposed on the integrated circuit, the master scan flip-flop having inputs to receive scan data and a first scan clock signal; and a slave scan flip-flop disposed on the integrated circuit and coupled to the master scan flip-flop, the slave scan flip-flop having a scan data output and an input to receive a second scan clock signal, the master scan flip-flop and the slave scan flip-flop operatively coupled to the functional circuit such that active circuitry of the master scan flip-flop and the slave scan flip-flop are independent of the functional circuit, wherein the first scan clock signal and the second scan clock signal are non-overlapping and are active when the system functional clock signal is in an off state, the scan data output coupled to the control node to set a value to operate the functional circuit at the control node when the system functional clock signal is in an on state.