Patent ID: 7941610

Claim:
A system for coherency directory updating in a multiprocessor computing system, comprising: a plurality of memory resources having a directory: a plurality of cells having respective caches and configured to be operably connected to an interconnect fabric, wherein the caches are physically separate from the memory resources and each of the caches includes address tags and state information associated with corresponding entries of the caches, wherein at least one of the caches includes entries for a corresponding plurality of coherency units that are part of the memory resources, wherein the plurality of coherency units are included in a memory block representing a contiguous portion of the plurality of memory resources, and wherein the directory is physically separate from the caches and stores ownership information that associates a particular one of the coherency units with at least one of the caches; and a controller configured to control at least a portion of the plurality of memory resources, and having a comparator configured to identify whether the memory block is local to a particular one of the cells in response to a write transaction; wherein the controller, if the memory block is local to the particular cell, is configured to set a state of the directory for the particular coherency unit to exclusive in response to the write transaction; and wherein the controller, if the memory block is not local to the particular cell, is configured to set the state of the directory for the particular coherency unit to invalid in response to the write transaction.