Patent ID: 8310269

Claim:
A test system for determining leakage of an integrated circuit (IC) under test, comprising: a test circuit formed on a same chip as the IC, the test circuit further comprising pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; the pulse generator comprising a variable frequency ring oscillator divided into a signal-enabled inverting gate and a plurality of sections, each section having an even number of inverting stages, a decoder configured to receive input bits corresponding to a selected duty cycle, and a multiplexer having logic coupled to the decoder and to the stages of the variable frequency ring oscillator, the multiplexer and decoder operative to generate from the variable frequency ring oscillator a pulse having a width according to the selected duty cycle and the frequency of a variable frequency ring oscillator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.