Patent ID: 8790978

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an element isolation region in a semiconductor substrate to represent a first device region and a second device region having a larger area than the first device region; forming a first gate electrode having a first width in the first device region; forming a second gate electrode having a third width in the second device region; forming a first sidewall spacer having a second width on a sidewall of the first gate electrode; forming a second sidewall spacer having a fourth width, which is wider than the second width, on a sidewall of the second gate electrode; implanting first impurities into the first device region, using the first gate electrode and the first sidewall spacer as masks, to form a first impurity region; implanting second impurities into the second device region, using the second gate electrode and the second sidewall spacer as masks, to form a second impurity region; and activating the first impurities and the second impurities by heat treatment, wherein a first length of the first impurity region in a direction perpendicular to the first gate electrode is shorter than a second length of the second impurity region in a direction perpendicular to the second gate electrode, and an impurity concentration in the first impurity region is substantially equal to an impurity concentration in the second impurity region.