Patent ID: 7003749

Claim:
A computer aided method for determining the existence of one or more conflicts in the placement or configuration of objects defining a circuit in the design of an integrated circuit, the method comprising the steps of: (a) defining a plurality of constraints each of which imposes at least one limitation on at least one of placement and configuration of at least one object that defines a circuit; (b) defining a plurality of constraint families each of which is comprised of a subset of the constraints defined in step (a), with each constraint family comprised of constraints of the same type; (c) determining for each constraint family of a subset of the plurality of constraint families defined in step (b) if a conflict exists between the constraints of said constraint family; (d) defining pairs of constraint families from the plurality of constraint families defined in step (b); (e) determining for each pair of constraint families of a subset of the pairs of constraint families defined in step (d) if a conflict exists between at least one constraint of one constraint family of said pair and at least one constraint of the other constraint family of said pair; (f) amending at least one of the constraints if a conflict is determined to exist in step (e); (g) repeating steps (c), (e) and (f) if at least one of the constraints was amended in the prior iteration of step (f); and (h) laying out the circuit objects subject to the constraints.