Patent ID: 7982245

Claim:
A semiconductor integrated circuit comprising: a main function transistor formed on a first active region of a substrate and comprising: a first gate stack formed by a first gate insulation layer and a first gate electrode disposed in a first overlapping portion over the first gate insulation layer, and a first gate electrode contact electrically connected to the first gate electrode outside the first overlapping portion; and a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”) formed on a second active region of the substrate and comprising: a second gate stack formed by a second gate insulation layer having the same thickness as the first gate insulation layer, and a second gate electrode disposed over a second overlapping portion of the second gate insulation layer; and a second gate electrode contact electrically connected to the second gate electrode within the second overlapping portion and configured to apply voltage stress to damage the second gate insulation layer.