Patent ID: 8330230

Claim:
A pad of a semiconductor device through which a bulk bias voltage is applied to a semiconductor substrate, the pad comprising: a junction area of the semiconductor substrate doped with a high concentration of impurity ions to reduce the ohmic contact resistance of the junction area relative to the semiconductor substrate; a polylayer portion disposed on the semiconductor substrate and electrically connected to the junction area through a direct contact; and a metal layer portion disposed on the polylayer portion, electrically connected to the polylayer portion and receiving a voltage having a fixed level, such that the voltage is directly applied to the semiconductor substrate through the direct contact and the junction area as the bulk bias voltage, wherein the junction area comprises first and second junction areas separately disposed in the semiconductor substrate, and the direct contact comprises a first direct contact disposed between the polylayer portion and the first junction area, and a second direct contact separate from the first direct contact and disposed between the polylayer portion and the second junction area.