Patent ID: 8039351

Claim:
A method of fabricating a hetero-junction bipolar transistor, the method comprising: providing a substrate including a bulk silicon having a <110> crystalline orientation; forming a buried oxide (BOX) within the bulk silicon having the <110> crystalline orientation; forming a silicon-on-insulator (SOI) region over the BOX, where the SOI region has a <100> crystalline orientation; forming a pnp hetero-junction bipolar structure on the bulk silicon having the <110> crystalline orientation, the pnp hetero-junction bipolar structure including; an emitter, a base and a collector, wherein the emitter is formed over the base, wherein the base is formed over the collector, and the collector is disposed on the bulk silicon having the <110> crystalline orientation; and forming a npn hetero-junction bipolar transistor (HBT) on the SOI region, the npn HBT including: an npn collector disposed on the SOI region; an npn base disposed on the collector to form a hetero-junction therebetween; and an npn emitter disposed on the base to form a hetero-junction therebetween.