Patent ID: 8552534

Claim:
A laminated semiconductor wafer comprising a plurality of semiconductor substrates having a plurality of scribe-groove parts formed along scribe lines, the plurality of semiconductor substrates including: a plurality of device regions each in contact with at least one of the plurality of scribe-groove parts, having a semiconductor device formed therein, formed in a rectangular shape, and insulated; and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts, wherein the plurality of wiring electrodes are arranged, for each of the plurality of device regions, in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides corresponding to boundaries between each of the device regions and the scribe-groove parts, and extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween among the plurality of device regions, a through hole formed therein which penetrates the scribe-groove parts of the plurality of semiconductor substrates laminated in a laminated direction in which the plurality of semiconductor substrates are laminated, and in which a plurality of the wiring electrodes, constituting a laminated electrode group laminated in the laminated direction among the plurality of wiring electrodes, appear; a through electrode which penetrates all of the plurality of semiconductor substrates through the through hole and is in contact with all of the wiring electrodes appearing in the through hole; and a plurality of laminated chip regions each of which is composed of the device regions laminated in the laminated direction in all of the plurality of semiconductor substrates.