Patent ID: 7058735

Claim:
A processor module having a direct memory access (DMA) control apparatus comprising: a processor unit for processing data and initiating a generation of one or more local DMA (LDMA) designators upon determining that a portion of the data is unavailable in local memory, and to thereafter continue processing which does not require the unavailable data while waiting for the unavailable data to become available in the local memory; a LDMA designator holder contained within the processor module and adapted to receive and hold LDMA designator; a LDMA controller contained within the processor module and communicatively coupled to the LDMA designator holder for receiving the LDMA designator and adapted to carry out a LDMA transaction in accordance with the content of the received LDMA designator to retrieve the unavailable data; and a plurality of staging registers coupled between the processor unit and the LDMA designator holder, each staging register for storing a different LDMA parameter and for writing a portion of a LDMA designator into a selected portion of the LDMA designator holder; wherein any one or more of the plurality of staging registers is capable of retaining its stored LDMA parameter between successive writings of LDMA designators to the LDMA designator holder when the LDMA parameter is unchanged so that the one or more staging registers need not be rewritten.