Patent ID: 7968407

Claim:
A method of manufacturing a semiconductor memory device, the method comprising: forming a trench in a substrate, the trench defining an active region on the substrate; forming an isolation layer in the trench; forming a tunnel insulation layer on the active region; forming a preliminary charge trapping layer on the tunnel insulation layer; forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer to form exposed top portions of the preliminary charge trapping layer; removing an upper portion of the isolation layer, after forming the etch stop layer, so that side portions of the preliminary charge trapping layer are exposed; removing the exposed top and side portions of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness; forming a dielectric layer on the charge trapping layer; and forming a gate electrode on the dielectric layer.