Patent ID: 8803580

Claim:
A Power-On Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage, comprising: a power switch ( 0 ), with the input terminal connected to the supply voltage; a band-gap comparator circuit ( 1 ), which is connected to the output terminal of the power switch ( 0 ), and configured to output two channels of current signals according to a variation signal of the supply voltage; a current comparator circuit ( 2 ), which is connected to the output terminal of the band-gap comparator circuit ( 1 ), and configured to compare the two channels of current signals and output a voltage detection signal; a state latch circuit ( 3 ), which is connected to the output terminal of the current comparator circuit ( 2 ), and configured to latch the voltage detection signal and output a latch signal; an output buffer circuit ( 5 ), which is connected to the output terminal of the state latch circuit ( 3 ), and configured to buffer the latch signal, wherein, the output buffer circuit ( 5 ) comprises a first buffer unit and a second buffer unit connected in sequence, the output terminal of the first buffer unit is connected to the power switch ( 0 ) and configured to control ON/OFF of the power switch ( 0 ), the second buffer unit outputs a final Power-On Reset signal; a brown out detector ( 4 ), with the input terminal connected to the supply voltage and the output terminal connected to the output terminal of the state latch circuit ( 3 ), configured to pull down the level at the output terminal of the state latch circuit ( 3 ) so as to reset the system when it detects the supply voltage is lower than the threshold required for normal operation of the system.