Patent ID: 8421141

Claim:
A non-volatile memory comprising: a substrate; a first gate stack located on the substrate; a selecting gate located on the substrate at a first side of the first gate stack; an erasing gate located on the substrate at a second side of the first gate stack; a source region located in the substrate under the erasing gate; a drain region located in the substrate at a side of the selecting gate; a first dielectric layer located between the first gate stack and the erasing gate and between the first gate stack and the source region; and a second dielectric layer located between the selecting gate and the substrate, the first gate stack comprising: a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially stacked from bottom to top; and a spacer located on a sidewall of the control gate and a sidewall of the inter-gate dielectric layer, wherein a side of the floating gate adjacent to the erasing gate has a warp-around profile and has a sharp corner, and the sharp corner protrudes beyond a vertical surface of the spacer.