Patent ID: 7177217

Claim:
A circuit for verifying and substituting a defective reference cell of a memory device comprising at least one reference current path including the reference cell and a decoding transistor connected in series, the reference cell and the decoding transistor each comprising a control terminal, the circuit comprising: at least one redundant reference current path identical to the at least one reference current path and in parallel therewith; a connection circuit for connecting in a mutually exclusive way the control terminals of the decoding transistor and reference cell of the at least one reference current path to a node having a pre-established voltage or the control terminals of the decoding transistor and reference cell of said at least one redundant reference current path to the node having the pre-established voltage, the connecting being based upon a logic signal; and a window comparator coupled to the at least one reference current path for comparing a current therein with a pair of upper and lower thresholds, and outputting the logic signal for said connection circuit based upon the comparison.