Patent ID: 6959397

Claim:
A programmable skew clock signal generator, comprising: a frequency generator circuit that produces an output signal F φ0 from a reference signal F ref ; a frequency accumulator, preloaded with a preload value P K1 for a first reference signal cycle and receiving a frequency division constant K 1 as an input thereto for subsequent cycles of F ref , the frequency accumulator having a maximum count K MAX and producing an overflow output; a phase accumulator, receiving the overflow output from the frequency accumulator as a clock signal, preloaded with a preload value P C1 for a first cycle of the overflow output from the frequency accumulator and receiving a phase offset constant C 1 as an input thereto during subsequent cycles of the overflow output from the frequency accumulator, the phase accumulator having a maximum count C MAX and producing a phase accumulator output; a delay line clocked by the reference signal F ref and producing a plurality of delayed reference clock signals at a plurality of tap outputs; tap selecting means receiving the phase accumulator output and selecting at least one of the tap outputs in response thereto to produce an output F φ1 whose phase shift φ 1 relative to F φ0 is a function of P K1 and P C1 ; and wherein the output F φ1 is given by: x ⁡ ( t ) = rect ⁡ ( t T p ) = { 1 for ⁢ ⁢  t  < T p 2 0 otherwise ⁢ ⁢ F ϕ ⁢ 1 = ∑ n = 0 ∞ ⁢ x ⁡ [ t - n ⁢ ⁢ T ϕ ⁢ ⁢ 1 - ϕ ] , where t is a time corresponding to a center of an output pulse, T p is the width of the output pulse, and T φ1 is the period of the pulse train, and wherein P K1 and P C1 are respectively given by: P K1 = ϕ 2 ⁢ π · K MAX ⁢ ⁢ and ⁢ ⁢ P C1 = [ K MAX - Frac ⁡ ( P K1 K ) ] · C MAX .