Patent ID: 6973606

Claim:
An apparatus comprising: an internal test bus (ITB); a plurality of deskew clusters coupled to the ITB, wherein the plurality of deskew clusters each include a deskew controller; an integrated test controller (ITC) coupled to the ITB, said ITC having an instruction register and a test access port finite state machine (TAP FSM); and a debug unit coupled to the ITC, said debug unit triggers a signal as an input to said ITC in response to an externally generated test signal; wherein the ITC only generates a single global control signal and each of the deskew controllers generates a first local control signal and a second local control signal in response to the single global control signal, where said ITC encodes and transmits states of said TAP FSM and test instructions to at least one logic unit controller over said ITB to test said apparatus, wherein a snapshot instruction and a shift instruction are transmitted in the single global control signal together and are partitioned into separate operations and it is not necessary to synchronize the snapshot instruction and the shift instruction.