Patent ID: 7034336

Claim:
A capacitorless 1-transistor DRAM cell comprising: doped source-drain regions disposed in semiconductor material; a channel region disposed in the semiconductor material between doped source-drain regions, wherein the source-drain regions are embedded in a dielectric material in such a way that the channel region is at least partially depleted of charge carriers in the absence of an applied electrical potential; and a gate electrode arranged alongside the channel region, the gate electrode being insulated from the channel region by a gate dielectric; wherein: a region made of the dielectric material is formed at a top side of a semiconductor body; the channel region is arranged at a sidewall of the region made of the dielectric material; the source-drain regions adjoin the channel region on both sides in the vertical direction with regard to the top side; the gate electrode is arranged alongside of the channel region that is remote from the region made of the dielectric material and in a manner isolated from said channel region by the gate dielectric; the gate electrode is electrically coupled to a word line; and an upper one of the source-drain regions is electrically coupled to a bit line.