Patent ID: 8082537

Claim:
A processor implemented method of designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC, a layout of the mother IC including at least one interface tile having an electrical configuration for communicating with interface logic of the daughter IC, the processor implemented method comprising: obtaining, using a processor, design rules for through die vias (TDVs) to be formed in the mother IC for implementing connections between the at least one interface tile and a physical interface of the daughter IC; defining, using the processor, a layout of the TDVs in the mother IC according to the design rules; defining, using the processor, at least one mask data for configuring an interconnect on the mother IC to physically connect the TDVs between the at least one interface tile of the mother IC and the physical interface of the daughter IC; and determining an interface logic data for the at least one interface tile based on a configuration of the TDVs, wherein the interface logic data is for configuring the at least one interface tile to couple signals from the mother IC to the TDVs without changing the electrical configuration of the at least one interface tile.