Patent ID: 8732375

Claim:
A configurable transceiver including a plurality of Physical Coding Sublayer (“PCS”) lane-based data paths, a lane-based data path comprising: a plurality of PCS lane-wide data processing circuitry blocks arranged in the data path, each circuitry block being adapted to perform a data processing step of at least one of a plurality of high speed communication protocols; a plurality of selection circuits coupled between at least some of the circuitry blocks, the selection circuits being configurable so that the data path either bypasses or utilizes particular ones of the plurality of circuitry blocks depending on which of the plurality of high speed data communication protocols the transceiver is to be configured to accommodate; and a plurality of local control circuitry blocks, each one coupled to a corresponding one of the plurality of lane-based data paths and to link-width control circuitry in the transceiver, each local control circuitry block being adapted to generate one or more of the following: (i) lane up-down information signals for the link-width control circuitry indicating up-down status of a corresponding lane-based receive data path and (ii) lane up-down control signals for controlling an up-down state of a corresponding lane-based transmit data path in response to signaling from the link-width control circuitry.