Patent ID: 8151132

Claim:
A memory device, comprising: a plurality of memory chips coupled in series, the first memory chip of the plurality of memory chips being coupled to a first terminal resistance and a last memory chip of the plurality of memory chips being coupled to a second terminal resistance; a register serially coupled to the memory chips, the register configured to receive an address signal, a control signal, and at least one clock signal; and an integrated delay-locked loop in the register, the integrated delay-locked loop comprising a phase detector, the phase detector configured to: receive the at least one clock signal and a delayed clock signal; compare a phase of the at least one clock signal to a phase of the delayed clock signal; generate an error signal based on the comparison; and integrate the error signal to generate a delay control signal and force the error signal to go to zero while maintaining a phase lock between the at least one clock signal and the delayed clock signal.