Patent ID: 8213219

Claim:
A memory cell system comprising: a memory cell comprising: a first access transistor having a first gate terminal corresponding to a word line of the memory cell, a first source/drain terminal corresponding to a first bit line of the memory cell, and a first drain/source terminal corresponding to a first storage node of the memory cell; a second access transistor having a second gate terminal corresponding to the word line of the memory cell, a second source/drain terminal corresponding to a second bit line of the memory cell, and a second drain/source terminal corresponding to a second storage node of the memory cell; a third drive transistor having a third gate terminal coupled to the second storage node, a third drain terminal coupled to the first storage node, a third source terminal corresponding to a reference voltage, and a third body terminal directly connected to the third gate terminal; and a fourth drive transistor having a fourth gate terminal coupled to the first storage node, a fourth drain terminal coupled to the second storage node, a fourth source terminal corresponding to the reference voltage, and a fourth body terminal directly connected to the fourth gate terminal; a word line selection and control module operatively coupled to the memory cell; and a sense amplifiers and decoders module operatively coupled to the memory cell; wherein the word line selection and control module and the sense amplifiers and decoders module are controlled to enter a standby state of the memory cell by asserting a leakage-inducing voltage at the word line, asserting a first standby voltage at the first bit line, and asserting a second standby voltage at the second bit line; wherein the first standby voltage is higher than the leakage-inducing voltage; and wherein the second standby voltage is higher than the leakage-inducing voltage.