Patent ID: 7480168

Claim:
A semiconductor memory device, comprising: a plurality of memory cells arranged in row and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data; a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes; a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs and bit lines in each pair being arranged with a bit line of other pair interposed in between; and row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line, said row selecting circuitry selecting one word line out of the word lines in accordance with the address signal.