Patent ID: 7403442

Claim:
A memory circuit, comprising: a plurality a memory cells organized in rows and columns; a plurality of word lines, each coupled to a respective row of memory cells; a plurality of driver circuits, each coupled to a respective word line, each driver circuit comprising: a driver unit for deactivating the respective word line after an access to a memory cell coupled to the respective word line; a discharging means for discharging the respective word line; and a first signal generator configured to generate a first control signal and a subsequent second control signal, wherein the first control signal triggers the driver unit to deactivate the respective word line and triggers the discharging means to start discharging the respective word line, and wherein the second control signal triggers the discharging means to stop discharging the respective word line; a plurality of bit lines, each coupled to a respective column of memory cells; a dummy bit line having a signal transmission behavior which is substantially similar to the signal transmission behavior of the bit lines; a dummy word line having a signal transmission behavior which is substantially similar to the signal transmission behavior of the word lines; and a second signal generator configured to provide the dummy bit line with a third control signal, wherein an output signal of the dummy bit line is provided to the dummy word line, wherein the output signal of the dummy bit line is utilized for triggering the first signal generator of at least one driver circuit to generate the first control signal, and wherein an output signal of the dummy word line is utilized for triggering the first signal generator of the at least one driver circuit to generate the second control signal.