Patent ID: 7529986

Claim:
A test method of a dynamic semiconductor memory device, said dynamic semiconductor memory device comprising a memory cell array having a storage area of parity data that is realized by product code that is composed of a first code and a second code; said test method comprising steps of: writing prescribed value data to said memory cell array; and as an encoding process realized by said first code, reading data from said memory cell array to generate a first parity, and writing said first parity that has been generated to said memory cell array; following a refresh operation of a prescribed interval, reading data encoded by said first code from said memory cell array, decoding the read data, and writing first corrected bits to said memory cell array; reading data from said memory cell array to which said first corrected bits have been written, determining pass/fail, and recording the determination results to a first fail memory; writing prescribed value data to said memory cell array, and, as an encoding process realized by said second code, reading data from said memory cell array to generate a second parity, and writing said second parity that has been generated to said memory cell array; following a refresh operation of a prescribed interval, reading data encoded by said second code from said memory cell array, decoding the read data, and writing second corrected bits to said memory cell array; reading data from said memory cell array to which said second corrected bits have been written, determining pass/fail, and recording the determination results to a second fail memory; and executing a prescribed logical operation relating to contents of said first fail memory and contents of said second fail memory, and based on results of said logical operation, deriving cells that are to be remedied by means of redundant cells.