Patent ID: 7298647

Claim:
A non-volatile memory comprising a plurality of storage units formed upon a substrate and arranged into a plurality of columns connected along respective bit lines each comprising a number of storage units connected in series between a first select transistor and a second select transistor, whereby the storage units form a corresponding number of rows such that the columns of elements along a given row are subdivided into a plurality of distinct subsets, with a number of word lines each connecting the storage elements of a corresponding row; biasing circuitry is connected to the select transistors, and wherein the voltage level on the gates of the first select transistors in one subset are settable independently of the voltage level on the gates of the first select transistors in the other subsets, and the voltage level on the gates of the second select transistors in said one subset are settable set independently of the voltage level on the gates of the second select transistors in the other subsets, and wherein the voltage levels applied to the select transistors in said one subset are not supplied to select transistors in the other subsets.