Patent ID: 7439755

Claim:
An electronic circuit, comprising: an output terminal; a plurality of field effect transistors (FETS) to be tested, said FETS having first drain-source terminals, gates, and second drain-source terminals; at least a first measuring FET having a first drain-source terminal, a gate, and a second drain-source terminal, said second drain-source terminals of said plurality of FETS to be tested being interconnected with said first drain-source terminal of said first measuring FET and said output terminal; a first biasing terminal, said second drain-source terminal of said first measuring FET being interconnected with said first biasing terminal; a second biasing terminal, said first drain-source terminals of said FETS to be tested being interconnected with said second biasing terminal; a state machine coupled to said gates of said FETS to be tested and said gate of said first measuring FET, said state machine being configured to energize said gate of said first measuring FET and to sequentially energize said gates of said FETS to be tested, whereby an output voltage appears on said output terminal; circuitry to compare said output voltage to a reference value; and a second measuring FET having a first drain-source terminal, a gate, and a second drain-source terminal, said first drain-source terminal of said second measuring FET being interconnected with said first drain-source terminal of said first measuring FET, said second drain-source terminal of said second measuring FET being interconnected with said first biasing terminal, said gate of said second measuring FET being interconnected with said state machine, said first and second measuring FETS each having a width, said widths being selected so as to operate a given one of said FETS to be tested at a measuring point wherein said given one of said FETS is operating, at a given time, in a desired one of a linear region and a saturation region.