Patent ID: 8381072

Claim:
A memory access apparatus comprising: a receiver that receives a reading instruction and a reading address from a processor; a comparator that compares an address stored in an address area of each of multiple cache line included in a cache memory with the reading address; a reading unit that reads error-correction coded data corresponding to the reading address which is stored in a main memory if the address stored in the address area does not correspond to the reading address; a decoder that performs error correction decoding of the error-correction-coded data; a detector that detects presence or absence of an error in the error-correction-coded data; a corrector that corrects the read error-correction-coded data if there is an error in the error-correction-coded data to yield corrected data, and outputting a correction execution signal indicating that correction has been performed; a storing unit that stores the corrected data into a data area of one of the multiple cache lines, stores the reading address in the address area of the one of the multiple cache line, and sets a dirty bit of the one of the multiple cache line to 1 based on the correction execution signal; and a transmitter that transmits the corrected data stored in the data area to the processor.