Patent ID: 8437215

Claim:
A memory comprising: a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells; a first word line on a first side of the row of bit cells, and a second word line on a second side of the row of bit cells, the first and second word lines being adjacent to each other; a first word line segment driver connected by the first word line, but not by the second word line, to the first plurality of bits cells and a second word line segment driver connected by the second word line, but not by the first word line, to the second plurality of bit cells, the first and second word line segment drivers being selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other of the first and second pluralities of bit cells; and a shared sense amplifier coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells, so that the shared sense amplifier is configured to receive signals from whichever of the one first bit cell or the one second bit cell is activated by the respective word line segment driver thereof at a given time.