Patent ID: 8867605

Claim:
A system comprising: a processor; and memory coupled to the processor; and a decoder coupled to the memory and comprising: a decoder first stage operable for decoding encoded frames to produce decoded frames, the encoded frames comprising an encoded first frame and an encoded second frame, and the decoded frames comprising a decoded first frame produced using the encoded first frame, the decoded frames also comprising a decoded second frame produced using the encoded second frame, wherein each of the decoded frames is classified as a type of frame selected from the group consisting of: an in-order frame comprising macroblocks in a specified order; a reference frame comprising information relied upon by another frame for decoding; and an out-of-order non-reference frame that is not an in-order frame and not a reference frame; and a decoder second stage coupled downstream of the first stage, the second stage comprising a first deblocker and a second deblocker, wherein the second deblocker is selected to deblock decoded frames classified as an out-of-order non-reference frame, wherein the first deblocker is selected to deblock decoded frames not classified as an out-of-order non-reference frame, wherein further the first decoded frame is not classified as an out-of-order non-reference frame and as such is deblocked with the first deblocker, wherein the second decoded frame is classified as an out-of-order non-reference frame and as such is deblocked with the second deblocker, the first deblocker and the second deblocker respectively deblocking the first and second decoded frames in parallel and concurrently.