Patent ID: 6874044

Claim:
A flash-memory peripheral comprising: a local central processing unit (CPU) for executing instructions for operating the flash-memory peripheral; a CPU bus primarily controlled by the local CPU; a flash-serial buffer bus not primarily controlled by the local CPU; a RAM buffer for storing flash data for storage by the flash-memory peripheral; a flash-memory controller for controlling a flash memory that stores the flash data, having a slave port for coupling to the CPU bus and receiving commands from the local CPU, and having a master port for coupling to the flash-serial buffer bus for transferring flash data to the RAM buffer; a serial link for connecting the flash-memory peripheral to a personal computer; and a serial engine for sending and receiving the flash data serially over the serial link, the serial engine having a slave port for coupling to the CPU bus and receiving commands from the local CPU, and having a master port for coupling to the flash-serial buffer bus for transferring flash data to the RAM buffer; wherein the flash data is read from the flash memory by the flash-memory controller and sent over the flash-serial buffer bus to the RAM buffer; wherein the flash data is read from the RAM buffer through the flash-serial buffer bus to the serial engine to be sent serially over the serial link, wherein incoming flash data is written to the RAM buffer through the flash-serial buffer bus from the serial engine, wherein the incoming flash data is read from the RAM buffer through the flash-serial buffer bus to the flash-memory controller and written to the flash memory, whereby the flash-serial buffer bus transfers the flash data and the CPU bus sends commands to the flash-memory controller and to the serial engine.