Patent ID: 7966543

Claim:
A cyclic comparison method for a processor in a low-density parity-check decoder, including a check node unit which receives a matrix having k elements, where k is an integer, compares the elements in each row of the matrix and outputs a result for generating a code bit and a decoding codeword, said method comprising the following steps: (a) sequentially removing one said element respectively at from first position to kth position to obtain k first level sequences with each said first level sequences having (k−1) elements, and outputting said first level sequences and a minimum value of each said first level sequences; (b) utilizing two said elements sequentially selected from said k elements input to said check node unit to form k second level sequences, and utilizing pairs of two said second level sequences sequentially selected from said k second level sequences to form k third level sequences; (c) utilizing pairs of two said third level sequences to form a plurality level sequences, and repeating step until obtaining k output results with each said output results containing (k−1) elements; and (d) comparing said output results obtained in Step (c) and said first level sequences obtained in Step (a) to determine whether they are identical; if they are identical, stopping process and outputting a minimum value of each said output results; if they are not identical, doing Step (c) again to obtain new output results until said new output results are identical to said first level sequences.