Patent ID: 8716109

Claim:
A method for fabricating a chip package, comprising: providing a semiconductor wafer, containing a plurality of chips, wherein an area between any two adjacent chips comprises a scribe line, each of the chips has at least one conductive pad not exposed on a surface of the semiconductor wafer and a seal ring formed outside of the conductive pad; providing a packaging layer; forming a plurality of spacers between the chips of the semiconductor wafer and the packaging layer, wherein each the spacer corresponding to each chip is separated from each other, the spacer is shrunk inward from an edge of the chip to form a recess section and the spacer is formed to overlap with the conductive pad and the seal ring; bonding the semiconductor wafer and the packaging layer together; and dicing the semiconductor wafer along the scribe line to form a plurality of chip packages, wherein a side surface is defined by the diced semiconductor wafer, the spacer and the packaging layer, and the side surface has the recess section located at the spacer.