Patent ID: 7998854

Claim:
A method of fabricating a wafer level integration module with interconnects comprising: providing a wafer having a first side and a second side; forming depressions in the first side of the wafer; depositing a first insulation layer on the first side of the wafer; depositing a first conductive layer on the insulation layer, the first conductive layer having a first side and a second side; depositing a second insulation layer on the first side of the first conductive layer; exposing the first conductive layer; fabricating a semiconductor functional device on the first side of the wafer; exposing from the second side of the wafer, the second side of the first conductive layer; depositing a third insulation layer on the exposed second side of the first conductive layer; patterning the third insulation layer and exposing portions of the first conductive layer; depositing a second conductive layer on the patterned third insulation layer; and exposing the second conductive layer for contact with external devices.