Patent ID: 7415558

Claim:
Circuitry comprising: a bus interface which communicates with a first master and a second master; endpoint storage circuitry, coupled to the bus interface, the endpoint storage circuitry comprising a plurality of data endpoints wherein each of the plurality of data endpoints is allocatable to one of the first master and the second master; a serial interface engine which communicates with a USB host; a USB function controller, coupled to the bus interface, endpoint storage circuitry, and serial interface engine, the USB function controller comprising: USB protocol logic, coupled to the serial interface engine; endpoint interrupt logic which generates interrupts based on information received from the USB protocol logic; interrupt steering registers, accessible by both the first master and the second master; and interrupt steering logic which routes each of the interrupts to a corresponding one of the first master and the second master based on steering information provided by the interrupt steering registers; and a resource ownership register, coupled to the first master and the second master, the resource ownership register allowing the first master to control a control endpoint under a first condition and allowing the second master to control the control endpoint under a second condition, wherein the first master and the second master are not USB hosts.