Patent ID: 7131085

Claim:
A method for verification of a system design represented by a model that includes a plurality of variables, the method comprising: arranging the variables in an Ordered Binary Decision Diagram (OBDD) according to an initial order of the variables, the OBDD comprising a number of nodes arranged in rows corresponding respectively to the plurality of the variables; assigning to each processor, among a group of two or more computer processors, a respective variable among the plurality of the variables; using each processor, reordering the rows of the OBDD by varying a position in the OBDD of one of the rows, which corresponds to the respective variable that is assigned to the processor, until at least one of the processors identifies a new order for the OBDD: and using the new order of the OBDD, verifying a characteristic of the model against a specification, wherein reordering the rows comprises, using each processor, finding the new order such that the number of the nodes in the OBDD is reduced relative to the initial order; and receiving first and second new orders, respectively, from first and second processors among the two or more computer processors, and selecting the new order from among the first and second new orders so as to minimize the number of the nodes in the OBDD.