Patent ID: 7649776

Claim:
A nonvolatile semiconductor memory system comprising: a nonvolatile semiconductor memory having: a plurality of NAND cell units having: a memory cell string that includes a plurality of memory cell transistors that are connected in series and capable of electrically rewriting data and storing data having two or more values represented by a threshold voltage thereof; a first select transistor that is connected between one end of the memory cell string and a source line; and a second select transistor that is connected between the other end of the memory cell string and a bit line, a plurality of word lines that are connected to a gate electrode of one of the memory cell transistors in each of the NAND cell units, the plurality of word lines including a first word line that is adjacent to the first select transistor; a first select gate line that is connected to a gate electrode of the first select transistor in each of the NAND cell units; a second select gate line that is connected to a gate electrode of the second select transistor in each of the NAND cell units; a row controller that selectively applies a read voltage to the word lines, the first select gate line, and the second select gate line; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to the first word line; wherein the row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating the data stored in the memory cell transistors.