Patent ID: 7208370

Claim:
A method for fabricating a vertical transistor in a trench, comprising: providing a trench, having a base and at least one side wall which consists, at least in certain regions, of a semiconductor material, and a transition region comprising an insulating material between the regions of the base and the side wall which consist of semiconductor material; selectively depositing semiconductor material on the regions of the side wall and the base of the trench which consist of semiconductor material, to form semiconductor layers, during which at least the semiconductor layer which is deposited on the side wall grows as an epitaxial semiconductor layer, and a space remains between the semiconductor layers which have been deposited on the base and the side wall; forming a thin dielectric, which partially limits an electric current, on at least one of the semiconductor layers which have been deposited; filling the space between the two semiconductor layers which have been deposited with a conductive material; and forming a gate dielectric and a gate electrode on the epitaxial semiconductor layer which has grown.