Patent ID: 8259762

Claim:
A high speed bit stream data conversion circuit comprising: a plurality of data conversion circuits to receive a first plurality of bit streams at a first bit rate and to produce at least one second bit stream at a second bit rate; a plurality of symmetrical data circuit pathways that include pairs of circuit pathways, and that transport the first plurality of bit streams to the plurality of data conversion circuits, wherein transmission time for each of the first plurality of bit streams are substantially equal; and a clock distribution circuit that receives a data clock signal, wherein the clock distribution circuit substantially symmetrically distributes the data clock signal to the plurality of data conversion circuits along a plurality of substantially symmetrical clock circuit pathways, wherein the plurality of substantially symmetrical clock circuit pathways include a trunk that is oriented along a bisection of the plurality of symmetrical data circuit pathways and includes substantially symmetrical branch pairs that extend outward from the trunk such that clock transmission time is substantially equal for each of the substantially symmetrical branch pairs, wherein each of the substantially symmetrical branch pairs correspondingly couple to each of the plurality of data conversion circuits.