Patent ID: 8345470

Claim:
A semiconductor memory device comprising: n pairs, n being an integer of two or more, of bit lines; m word lines, m being an integer of two or more; n×m memory cells provided at intersections of the n pairs of bit lines and the m word lines; and a control circuit, wherein each of the n×m memory cells includes a first access transistor coupled between one of the pair of bit lines corresponding to the memory cell and a first memory node of the memory cell, a second access transistor coupled between the other of the pair of bit lines corresponding to the memory cell and a second memory node of the memory cell, a first load transistor and a second load transistor coupled between a power supply node of the memory cell to which a memory cell power supply voltage is applied, and the first and second memory nodes of the memory cell, respectively, and a first drive transistor and a second drive transistor coupled between a ground node of the memory cell to which a memory cell ground voltage is applied, and the first and second memory nodes of the memory cell, respectively, in each of the n×m memory cells, the first and second access transistors each have a gate coupled to one of the m word lines which corresponds to the memory cell, the first load transistor and the first drive transistor each have a gate coupled to the second memory node of the memory cell, and the second load transistor and the second drive transistor each have a gate coupled to the first memory node of the memory cell, and the control circuit supplies a word line drive voltage to one of the m word lines which corresponds to one or more of the n×m memory cells to which data is to be written during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of the first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.