Patent ID: 7274069

Claim:
A memory cell having a memory transistor comprising: a gate electrode which is formed in a trench at a top side of a semiconductor body or a semiconductor layer and arranged between a source region and a drain region, which are located at the upper surface of the semiconductor material, and is isolated from the semiconductor material by dielectric material, wherein, between the source region and the gate electrode and between the drain region and the gate electrode, there is a layer sequence which comprises: a first oxide layer facing the semiconductor material; a nitride layer provided on the first oxide layer; and a second oxide layer, facing the gate electrode, and provided at least at lateral walls of the trench, wherein the nitride layer is absent in a curved region of the trench bottom, and in the curved region of the trench bottom in which the nitride layer is absent, the second oxide layer is present, and the first oxide layer and the second oxide layer together are thicker than the first oxide layer.