Patent ID: 8013395

Claim:
A semiconductor device having a dual-gate structure, the device comprising: a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween; a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region; a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region; an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto; a first p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto; a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto; a first n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto; a second p-type doped layer formed in a protruding part of the n-type gate electrode, where the n-type gate electrode protrudes from the first active region toward the first substrate contact portion and containing a p-type impurity introduced thereinto; and a second n-type doped layer formed in a protruding part of the p-type gate electrode, where the p-type gate electrode protrudes from the second active region toward the second substrate contact portion and containing a n-type impurity introduced thereinto, wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion, the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion, a distance between the second substrate contact portion and the second active region is greater than a distance between the first substrate contact portion and the first active region, and a width of the second n-type doped layer in the gate width direction is smaller than a width of the second p-type doped layer in the gate width direction.