Patent ID: 7111272

Claim:
In a FPGA having a plurality of individually programmable tiles of logic modules, each logic module including a plurality of programmable elements, a method of programming each of said tiles comprising: loading address data identifying one of the plurality of programmable elements designated for programming in each said tile; selecting an address of said programmable element designated for programming, wherein a mask bit for said programmable element is set from said loaded address data in each said tile; programming concurrently said programmable element identified by said address; determining whether said selected programmable elements designated for programming have been programmed; continuing to program said programmable element designated for programming if said programmable element designated for programming has not been programmed; soaking said programmable element in each said tile while concurrently resetting said mask register bit in each said tile; determining whether said programmable element designated for programming in each said tile has been programmed; and repeating said loading, said programming, said determining and said soaking if said programmable element designated for programming has not been programmed.