Patent ID: 8355499

Claim:
An encryption/decryption device, comprising an input logic circuit; an output logic circuit; and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit, each encryption/decryption circuit being capable of processing data at a respective encryption/decryption rate, wherein initialization vectors are combined with a first number of groups parsed from an input data stream to each parallel encryption/decryption circuit, the initialization vectors are incremented for a first parallel encryption/decryption circuit, and the incremented initialization vectors are used as initialization vectors for a second parallel encryption/decryption circuit, and wherein the number of encryption/decryption circuits is equal to or greater than an interface throughput rate divided by the encryption/decryption rate, and the input logic circuit operates to parse an input data stream into a number of groups, and distribute the number of groups to at least some of the number of encryption/decryption circuits according to a distribution order.