Patent ID: 8609505

Claim:
A method comprising: providing a semiconductor substrate; forming a first capacitor plate over the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; depositing a capacitor dielectric layer over the first capacitor plate and the semiconductor structure; patterning the capacitor dielectric layer to expose a first portion of an upper surface of the first capacitor plate and selected portions of the semiconductor substrate, wherein the patterning of the capacitor dielectric layer includes leaving a region of the capacitor dielectric layer extending beyond the surrounding spacer and contacting the semiconductor structure; forming a silicide layer in the first portion and the exposed selected portions; depositing an interlayer dielectric (ILD); forming a contact in the ILD, the contact contacting the silicide layer in the first region; forming a second capacitor plate over the capacitor dielectric layer over at least the first capacitor plate, the second capacitor extending laterally beyond the surrounding spacer and contacting the region of the capacitor dielectric layer, the second capacitor plate including one of: a metal plate formed in the ILD and including an upper surface in direct contact with a lower surface of a first metal layer, or a metal plate formed in the ILD that constitutes part of the first metal layer.