Patent ID: 7443249

Claim:
A Phase Locked Loop (PLL), comprising: a Phase Frequency Detector (PFD) for comparing a phase or frequency of a reference signal with a phase or frequency of an output signal and outputting an up signal or a down signal based on a comparison result; a charge pump circuit for generating a pumping current in response to the up signal or the down signal and increasing or decreasing the pumping current in response to a detection signal, wherein the charge pump circuit comprises: a first charge pump for generating a first current in response to the up signal or the down signal; a second charge pump for generating a second current in response to the up signal or the down signal; and a switching circuit connected in parallel to the first charge pump at an output node for connecting or disconnecting an output terminal of the second charge pump to or from the output node; a loop filter for outputting control voltage according to the pumping current; a Voltage Controlled Oscillator (VCO) for outputting the output signal having a frequency determined based on the control voltage; and a voltage detector for detecting the control voltage and outputting the detection signal based on a detection result.