Patent ID: 7863180

Claim:
A method for fabricating a microelectronic structure comprising: forming at least one dielectric layer on a semiconductor substrate; forming a first opening in the at least one dielectric layer to an underlying portion of the semiconductor substrate, wherein the first opening provides a first width portion of a via; forming an etch mask having a second opening exposing a portion of the underlying portion of the semiconductor substrate, wherein the first opening has a greater width than the second opening; extending the via with an isotropic etch into the semiconductor substrate to provide a second width portion and a third width portion, wherein a width of each of the second width portion and the third width portion are defined by etched semiconductor substrate sidewalls, the second width portion being narrower than the first width portion, the third width portion being wider than the second width portion and present at a greater depth of the semiconductor substrate than the second width portion; anisotropically etching the via to a final depth having a fourth width portion defined by sidewalls of a final depth etched portion of the semiconductor substrate, wherein the fourth width portion is at a depth in the semiconductor substrate that is present at a depth that is greater than the third width portion and has a smaller width than the first width portion; removing the etch mask; and filling the via with a conductive material.