Patent ID: 8587091

Claim:
A semiconductor packaging structure, comprising: a wafer having a first surface, a scribe-line region, an integrated circuit pattern and a plurality of pads are formed on the first surface, and a plurality of through holes penetrating said wafer, the through holes positioned in the scribe-line region; a second insulating material is filled in said through holes of said wafer, the second insulating material extended to a second surface of the wafer; a plurality of second conductive vias passing through said second insulating material that fills a through hole of said plurality of through holes, each of the plurality of second conductive vias being insulated from one another; a plurality of solder balls or needle pins are soldered to at least one of said second conductive vias; a plurality of first chips mounted on said first surface of said wafer, wherein each of said plurality of first chips has at least one pad mounted on the surface of said first chip opposite to said wafer; a first insulating layer disposed on said first surface of said wafer, said first insulating layer having a plurality of first conductive vias penetrating said first insulating layer, wherein said first insulating layer covers said first chips, said integrated circuit pattern and said first surface of said wafer; a conductive pattern layer formed on a surface of said first insulating layer opposite to said wafer, and said conductive pattern layer is electrically connected with said first conductive vias; wherein parts of said first conductive vias are connected with said pads of said wafer, parts of said first conductive vias are connected with said pads of said first chips and part of said first conductive vias are connected with said second conductive vias in said through holes; a third insulating layer having a pattern formed on a surface of said first conductive pattern layer which is opposite to said first insulating layer; and a metallic film formed on the inner surface of each of said through holes, wherein the metallic film extended to the surface of the second insulating material; wherein the second insulating material and the metallic film are both configured to extend from along the second surface of the wafer to a limited area.