Patent ID: 7295644

Claim:
A clock recovery adjustment circuit configured to adjust a clock signal recovered from a data stream, comprising: a) a clock phase adjustment circuit providing a clock phase adjustment signal, said clock phase adjustment circuit comprising parallel first and second clock phase adjustment paths configured to receive said clock phase information, said first clock phase adjustment path comprising a first multiplier and providing a first clock phase adjustment path signal, and said second clock phase adjustment path comprising a second multiplier and a first integrator and providing a second clock phase adjustment path signal; b) a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal; c) logic configured to (i) sample said data stream at predetermined times, (ii) receive a plurality of predetermined phases of said clock signal, and (iii) provide said clock frequency information and said clock phase information from sampled data and said predetermined phases of said clock signal; and d) an adder circuit, receiving said clock phase adjustment signal and said clock frequency adjustment signal, and providing a clock recovery adjustment signal.