Patent ID: 7787282

Claim:
A memory device comprising; an array of memory cells, wherein a number of the memory cells are commonly coupled to a select line, the number of memory cells including; a number of data cells, each of which being programmable to within a number of target threshold resistance (R t ) ranges which correspond to a number of data states; and a number of reference cells interleaved with the data cells, wherein each of the number of reference cells being programmable to within the number of target R t ranges; and control circuitry coupled to the array of memory cells and configured to; sense a level associated with at least one data cell; sense a level associated with at least one reference cell; and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell; wherein the number of memory cells commonly coupled to the select line include a number of groups of reference cells interleaved with the number of data cells, each reference cell in a group being programmable to within a particular target R t range; and wherein the control circuitry is configured to; sense a level associated with the group of reference cells; and compare the sensed level associated with the group of reference cells with the sensed level associated with the at least one data cell to determine a data state of the at least one data cell; wherein the sensed level associated with the group of reference cells is an average of a number of resistance levels associated with each reference cell in the group.