Patent ID: 8860223

Claim:
A memory comprising: a memory array including transverse row lines and bitlines, said row lines having an upper surface; a memory periphery associated with the memory array, said periphery including decoders electrically coupled to said transverse row lines and bitlines; a first dielectric over the memory array and the memory periphery; a second dielectric over the first dielectric, wherein the second dielectric is different from the first dielectric; a third dielectric over the second dielectric; a fourth dielectric over the third dielectric a first opening over the memory array through third and fourth dielectrics but not through the first and second dielectrics; a second opening over the memory periphery through the first, second, third, and fourth dielectrics; a metallization in the first and second openings and having an upper surface, wherein the upper surface of said metallization in the periphery being substantially co-planar with the upper surface of the metallization in the memory array, wherein said metallization having a first thickness in the first opening and further having a second thickness in the second opening, the second thickness greater than the first thickness; a first contact in the memory array, wherein the first contact extends from the first opening, through the first and second dielectrics and contacts two adjacent metal plugs below the first dielectric; and a second contact in the memory periphery, wherein the second contact extends from the second opening to a gate of a transistor.