Patent ID: 8200875

Claim:
An interrupt detection apparatus comprising: a detection address region storing unit configured to store an address region as a detection address region; an issuance interrupt information storing unit configured to store, as issuance interrupt information, second address information of a second interrupt message and a type of the second interrupt message; an interrupt message detection unit configured to determine, for a first interrupt message evaluated by the interrupt message detection unit, that first address information of the first interrupt message corresponds to the detection address region; and an interrupt issuing unit configured to issue the second interrupt message having the issuance interrupt information when it is determined that the first address information of the first interrupt message corresponds to the detection address region, wherein the interrupt issuing unit is configured to issue the second interrupt message via a first bus and a second bus, the interrupt issuing unit being coupled to a processor via the first bus and being coupled to at least one peripheral device via the second bus, and wherein the interrupt issuing unit is configured to issue the second interrupt message via the first bus when the type of the second interrupt message is a first type and is configured to issue the second interrupt message via the second bus when the type of the second interrupt message is a second type different from the first type.