Patent ID: 7558098

Claim:
A memory comprising: a memory cell array including a plurality of subarrays; a word line arranged on said memory cell array; a main bit line arranged to intersect with said word line; sub bit lines arranged on respective said subarrays and provided to be connectable to said main bit line; a storage portion connected between said word line and said sub bit lines; and a first transistor arranged between respective said sub bit lines for connecting said respective sub bit lines with each other; wherein nonselected said subarrays include a first subarray having a first sub bit line and a second subarray having a second sub bit line, said first and second subarrays being adjacent and separate from each other, said first sub bit line of said first subarray and said second sub bit line of said second subarray connected through said first transistor to fixed potentials arranged on both ends of said memory cell array.