Patent ID: 8635492

Claim:
A multiprocessing computer system comprising: a transactional memory system including a memory storage device; a plurality of processor cores in communication with said transactional memory system; a pairing sub-system adapted to dynamically pair two of said plurality of processor cores for fault tolerant operations of a current transaction in response to receipt of configuration information signals, said pairing sub-system providing a common signal path for forwarding identical input data signals to each said paired two processor cores for simultaneous pairwise processing thereat, said pairwise processing performing a lock-step execution of said transaction, said transactional memory storage device adapted to store error-free transaction state information used in configuring each paired core at said pairing sub-system for said simultaneous pairwise processing; decision logic device, in said pairing sub-system, for receiving transaction output results of each said paired two processor cores and comparing respective output results, said decision logic device generating an error-free indication signal upon determining matching transaction output results of said paired two processor cores when performing said lock-step execution, a control processor device, responsive to said error-free indication signal, for updating said transactional memory storage device with transaction state information associated with a most recent error-free transaction, said decision logic device further generating an error indication signal upon detection of non-matching transaction output results of said paired two processor cores when performing said lock-step execution, said control processor device, in response to said generated error indication signal, invalidating said output results obtained during performing the transaction, initiating a paired two processor core rollback to said most-recent error-free transaction state, reinitializing each said paired process core in a common microarchitectural state to ensure said lockstep execution on a cycle-by-cycle basis; and restarting said simultaneous pairwise transaction processing and initiating ensuring simultaneous lockstep execution.