Patent ID: 7508721

Claim:
A method of performing a programming operation in a non-volatile memory device having one or more memory cells each capable of storing N bits of data, where N is greater than or equal to one, and read/write circuitry connectable to the memory cells, the read/write circuitry including programming circuitry, bias circuitry to set bias conditions in the memory cells and one or more sets of latches each associated with a corresponding one of the memory cells to which the read/write circuitry is connected, the method comprising: applying a monotonically non-decreasing programming waveform from the programming circuitry to the memory cells; concurrently with applying said programming waveform, setting bias conditions in the memory cells by said bias circuitry, wherein a first set of bias conditions is used during a first programming phase and a second set of bias conditions is used during a second programming phase; and governing which of the programming phases is active by a first latch of each of said sets of latches.