Patent ID: 7321146

Claim:
A method of manufacturing a DRAM memory cell, the method comprising: forming word line structures on a semiconductor substrate where active regions are defined; forming drains and sources in the active regions on both sides of the word line structures; forming a first interlayer dielectric on the semiconductor substrate where the word line structures are formed; forming first contact pads and second contact pads in the first interlayer dielectric to contact the drains and sources, respectively; forming a second interlayer dielectric on the semiconductor substrate where the first contact pads and the second contact pads are formed; forming bit line structures on the second interlayer dielectric, the bit line structures being disposed perpendicularly to the word lines and being electrically connected to the first contact pads; depositing an insulating layer on the second interlayer dielectric on which the bit line structures are formed; forming storage node contact holes that expose the second contact pads by etching the insulating layer such that an entrance portion of the storage node contact holes extends in a direction parallel to a longitudinal axis of the bit line structures so as to be wider than a contact portion of the storage node contact holes; forming storage node contact plugs by filling the storage node contact holes with a conductive material; and forming storage node electrodes to contact the storage node plugs.