Patent ID: 8129752

Claim:
An integrated circuit, comprising: a substrate region; and a gate electrode level region formed above the substrate region, the gate electrode level region including at least three linear-shaped conductive structures formed to extend lengthwise in a first direction, each of the at least three linear-shaped conductive structures having a lengthwise centerline, the at least three linear-shaped conductive structures positioned in a spaced apart and side-by-side manner according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the at least three linear-shaped conductive structures is an integer multiple of the equal pitch, wherein the at least three linear-shaped conductive structures includes a first linear-shaped conductive structure having a gate portion that forms a gate electrode of a first transistor of a first transistor type, wherein the gate portion of the first linear-shaped conductive structure is the only gate portion of the first linear-shaped conductive structure, wherein the at least three linear-shaped conductive structures includes a second linear-shaped conductive structure having a first gate portion that forms a gate electrode of a second transistor of the first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, wherein a length of the first linear-shaped conductive structure as measured in the first direction is greater than or approximately equal to one-half of a length of the second linear-shaped conductive structure as measured in the first direction, and wherein the at least three linear-shaped conductive structures includes a third linear-shaped conductive structure having a length as measured in the first direction substantially equal to the length of the second linear-shaped conductive structure as measured in the first direction.