Patent ID: 7126225

Claim:
A multi-layer semiconductor wafer structure defining a multiplicity of dies formed thereon, said wafer structure comprising: a first scribe line having a selected width extending along a first direction; a second scribe line having a selected width extending along a second direction and intersecting said first scribe line; four dies located at and separated by the intersection of said first and second scribe lines wherein each of the four dies comprises a corner point adjacent the intersection of said first and second scribe lines; a first free area A 1 on the first scribe line adjacent the corner point of the first die, wherein A 1 is defined by the equation A 1 =D 1 ×S 1 , and wherein D 1 is the distance extending from the corner point of the first die, and S 1 is the width of the first scribe line; a second free area A 2 on the second scribe line adjacent the corner point of the second die, wherein A 2 is defined by the equation A 2 =D 2 ×S 2 , and wherein D 2 is the distance from the corner point of the second die, and S 2 is the width of the second scribe line; a third free area A 3 on the second scribe line adjacent the third corner point of the third die, wherein A 3 is defined by the equation A 3 =D 3 ×S 2 , and wherein D 3 is the distance from the corner point of the third die; a fourth free area A 4 on the first scribe line adjacent the corner point of the fourth die, wherein A 4 is defined by the equation A 4 =D 4 ×S 1 , and wherein D 4 is the distance from the corner point of the fourth die; and a fifth free area A S on the intersection of the first scribe line and the second scribe line and is defined by the equation A S =S 1 ×S 2 .