Patent ID: 7830336

Claim:
A driver device of a PDP (plasma display panel) comprising: an output buffer circuit comprising two cascade-connected MOS transistors of a same conductivity type wherein a connection point of said two MOS transistors is connected to a data electrode of a display cell; a level shift circuit that drives said output buffer circuit; an electric charge recovery circuit, connected to a power supply terminal of said output buffer circuit, that recovers for reusing electric charges remaining on the data electrode after a discharge of said display cell; and a power supply control circuit connected in parallel with said output buffer circuit between said power supply terminal of said output buffer circuit and a power supply terminal of said level shift circuit that controls so that a power supply voltage of said level shift circuit is higher than a sum of a power supply voltage of said output buffer circuit and a threshold voltage of said MOS transistors for at least a period of time during a recovery/reuse cycle period of said electric charge recovery circuit.