Patent ID: 7452751

Claim:
A method of manufacturing a semiconductor device, comprising: a circuit forming step of forming a first semiconductor circuit including a connecting terminal portion on a first semiconductor substrate; a hole forming step of forming a first hole of a predetermined depth reaching a semiconductor substrate matrix of said first semiconductor substrate at a position located outside of a region in which a second semiconductor element including a second semiconductor circuit and a second electrode formed previously in a second semiconductor substrate is to be disposed; an insulation film deposition step of depositing a insulation film on a lateral wall and a bottom of said first hole and a surface of said first semiconductor substrate in which said first semiconductor circuit is formed; an insulation film eliminating step of eliminating said insulation film formed on the bottom of said hole and said connecting terminal portion; a wiring conductor connecting step of forming a wiring conductor layer of an electrically conductive material such that one end portion of said wiring conductor layer is connected to the semiconductor substrate matrix forming the bottom of said hole with other end portion thereof serving as a first electrode; a resist pattern forming step of applying a resist on the side of said semiconductor substrate in which said first semiconductor circuit is formed to thereby form a resist pattern of a predetermined thickness, said resist pattern having an opening for forming said first hole; an electrode forming step of forming a through electrode on said electrically conductive material through said opening formed in said resist pattern by electroplating with said first semiconductor substrate matrix being used as a cathode; a resist removing step of removing said resist; an element interconnecting step of connecting a first semiconductor element including said first semiconductor circuit and said first electrode formed in said first semiconductor substrate with said second semiconductor element through the medium of said first electrode and said second electrode; a through electrode insulation coating step of coating said second semiconductor substrate and said through electrode with an insulation material on the surface of said first semiconductor substrate in which said first semiconductor circuit is formed; a surface grinding step of grinding the insulation material coated in said through electrode insulation coating step from a side of said first semiconductor substrate on which said second semiconductor substrate is mounted until said through electrode is exposed; and a back surface grinding step of grinding a back surface of said first semiconductor substrate by a predetermined thickness.