Patent ID: 7906433

Claim:
A method of manufacturing a semiconductor device comprising: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a via hole in the interlayer insulating film, the via hole reaching a bottom of the interlayer insulating film; (c1) forming a filling member over the interlayer insulating film, the via hole being filled with the filling member; (c2) forming a first hard mask over the filling member, the first hard mask having an opening corresponding to a wiring trench; (c3) etching the filling member using the first hard mask as an etching mask, the filling member remaining in a lower partial space in the via hole; after (c3) etching, (c4) removing the first hard mask to expose the filling member formed over the interlayer insulating film; after (c4) removing, (d) forming a wiring trench continuous with the via hole as viewed in plan, the wiring trench reaching partway in a thickness direction of the interlayer insulating film, the wiring trench being formed under a condition that an etching rate of the interlayer insulating film is faster than an etching rate of the filling member, in such a manner that a height difference after the (d) forming the wiring trench between an upper surface of the filling member left in the via hole and a bottom of the wiring trench is half or less than half a cross-sectional distance of the via hole; after (d) forming, (e) removing the filling member in the via hole; and after (e) removing, (f) filling an inside of the via hole and the wiring trench with a conductive member.