Patent ID: 7436008

Claim:
An integrated circuit device, comprising: a substrate; circuitry disposed on said substrate; a plurality of signal lines disposed on said substrate to interconnect portions of said circuitry on said substrate; a power grid disposed on said substrate, the power grid comprising: a plurality of first lines to supply a first voltage level to said circuitry on said substrate; and a plurality of second lines to supply a second voltage level to said circuitry on said substrate; a shield mesh disposed on said substrate, the shield mesh comprising: a plurality of third lines to supply the first voltage level on said substrate; and a plurality of fourth lines to supply the second voltage level on said substrate; wherein each of said signal lines is disposed between and adjacent to a respective one of said third lines of said shield mesh and a respective one of said fourth lines of said shield mesh within a layer on said substrate to reduce effects of electronic cross-talk between nearby ones of said signal lines; and wherein the first lines and the second lines are thicker, by a factor of at least two, than the third and the fourth lines.