Patent ID: 8810309

Claim:
A stack package having a plurality of chips which are stacked, comprising: first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively, wherein a first bias is applied to be transferred from the first voltage dropping unit of the lowest chip to the first voltage dropping unit of the highest chip through the first line, and a second bias is applied to be transferred from the second voltage dropping unit of the highest chip to the second voltage dropping unit of the lowest chip through the second line.