Patent ID: 7784000

Claim:
A method of sequential functional path identification for at-speed structural test performed on at least one computing device, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying, using the at least one computing device, which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing, the at least one computing device, path test generation for the identified sequential functional paths using launch-off-scan test sequences, the launch-off-scan test sequences including applying a single scan shift to all latches in the IC, wherein the single scan shift launches a test transition; and after the performing of the path test generation using the launch-off scan test sequences, performing, using the at least one computing device, path test generation for critical paths included in the plurality of critical paths not identified and not tested by the launch-off-scan test sequences using launch-off-capture test sequences having two functional captures, the launch-off-capture test sequences including applying a functional capture pulse to the all of the latches in the IC such that the launch-off-capture test captures input data from each functional port of each of the latches.