Patent ID: 7484198

Claim:
A method for laying out a first integrated circuit design, comprising the steps of: providing a first layout of the first integrated circuit design, for use with an integrated circuit fabrication process that specifies a minimum STI width, the first layout defining a plurality of masks, the masks defining a plurality of integrated features when applied in a fabrication process, the features defining a plurality of diffusion regions each including at least one respective particular channel region, the features further defining a first plurality of STI regions each transversely-adjacent to a respective one of the diffusion regions in the plurality of the diffusion regions, and the features further defining a second plurality of STI regions each longitudinally-adjacent to a respective one of the diffusion regions in the plurality of diffusion regions which are N-channel diffusions; and adding an additional diffusion region within each of the first and second STI regions and spaced from the adjacent diffusion region by no more than twice the minimum STI width, the additional diffusion regions containing no features which alter the first integrated circuit design.