Patent ID: 7633816

Claim:
A semiconductor memory device including a plurality of memory cells each having two or more storage statuses, a rewrite speed or a degree of deterioration of the memory cells varying depending on which one of the storage statuses is caused by rewriting, the device comprising: a memory body including a plurality of data storage units, each of which has a plurality of the memory cells and stores a value of one bit; a read/rewrite control unit for performing a process of reading stored values in the memory cells, and a process of rewriting the stored values in the memory cells; an operation unit for performing an operation with the stored values in the memory cells which constitute the determined data storage unit to obtain a stored value in the data storage unit; a comparing unit for comparing the stored value in the data storage unit obtained by the operation unit and an externally inputted value and outputting a signal indicating matching or mismatching therebetween; and a rewrite cell determination unit for determining the memory cell whose stored value needs to be changed such that the stored value in the data storage unit is equal to the externally inputted value when the comparing unit outputs the signal indicating the mismatching.