Patent ID: 8890229

Claim:
A nonvolatile semiconductor memory device comprising: a foundation layer; and a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a select gate electrode provided on the stacked body; a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body; a first insulating film provided between the semiconductor layer and each of the plurality of electrode layers; and a second insulating film provided between the select gate electrode and the semiconductor layer, the stacked body including a plurality of staircase regions, the each of the plurality of electrode layers including an exposed portion, and the exposed portion being not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers, and the exposed portion of each of the plurality of electrode layers being disposed in one of the plurality of staircase regions.