Patent ID: 7159100

Claim:
A computer-based method for providing extended precision in single instruction multiple data (SIMD) arithmetic operations, comprising the steps of: (a) loading a first vector into a first register, said first vector comprising a plurality of N-bit elements; (b) loading a second vector into a second register, said second vector comprising a plurality of N-bit elements; (c) executing an arithmetic instruction for at least one pair consisting of an N-bit element in said first register and an N-bit element in said second register, to produce a resulting element; (d) writing said resulting element into an M-bit element of an accumulator, wherein M is greater than N; (e) transforming said resulting element in said accumulator into a width of N-bits; and (f) writing said resulting element into a third register; wherein said accumulator comprises a plurality of M-bit elements and wherein steps (c)-(f) operate on a plurality of elements of said first and second vectors to produce a resultant vector formed from a plurality of resulting elements written to said third register; and wherein said resulting elements in said accumulator are wrapped around the representable range of said resulting elements.