Patent ID: 8120961

Claim:
A nonvolatile semiconductor memory device comprising: a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the electrode film being divided into a plurality of control gate electrodes extending in one direction; a plurality of select gate electrodes provided on the stacked body and extending in the one direction; a plurality of semiconductor pillars extending in a stacking direction of the stacked body and penetrating through the control gate electrodes and the select gate electrode; a plurality of source lines extending in the one direction and connected to an upper end portion of a subset of the semiconductor pillars; a plurality of bit lines extending in a direction crossing the one direction and connected to an upper end portion of the remaining semiconductor pillars; a connecting member interconnecting between a lower end portion of one of the semiconductor pillars with the upper end portion connected to the source line and a lower end portion of another of the semiconductor pillars with the upper end portion connected to the bit line; a charge storage layer provided between the control gate electrode and the semiconductor pillar; and a gate dielectric film provided between the select gate electrode and the semiconductor pillar, a different potential being applicable to uppermost one of the control gate electrodes than that applied to the other control gate electrodes.