Patent ID: 7772896

Claim:
A method for generating a clock frequency dependent on a reference clock signal, using an arrangement which has a digital phase detector, a digital loop filter connected to the latter, and a digital/analog converter connected to the latter, to all of which a common clock signal is applied, in which a control voltage is available at an output of the digital/analog converter and in which a quartz-stable, controllable oscillator is connected to the output of the digital/analog converter, which oscillator generates as an output signal a local clock signal corresponding to the clock frequency, in which the phase detector is fed the reference clock signal as first input signal via a first input and the local clock signal as second input signal via a second input, in which the relative phase angle of the two clock signals is ascertained in the phase detector by means of sampling pulses whose spacing from one another is determined by the common clock signal, in which a deviation of the phase angles is regulated by the oscillator in the sense of compensation and in which, upstream of one of the inputs of the phase detector, a multiplexer is connected into the transmission path of the respective incoming input signal, to which the corresponding input signal is fed directly, on the one hand, and via a delay circuit, on the other hand, and by which the reference clock signal or the local clock signal is fed to the phase, detector either directly or in delayed fashion, comprising: using the common clock signal as a system clock signal which is independent of the reference clock signal and of the local clock signal and whose frequency is higher by a factor of at least “5” than the frequency of the reference clock signal and of the local clock signal, respectively, and setting the temporal spacing between the edges of the undelayed clock signal, on the one hand, and of the delayed clock signal, on the other hand, such that the temporal spacing is greater than the temporal spacing of the sampling pulses of the phase detector (PD) that are predetermined by the system clock signal.