Patent ID: 7582526

Claim:
A method for manufacturing a memory device together with at least a high voltage device and a low voltage device, comprising: providing a substrate having a memory region and a peripheral region, wherein the peripheral region has a high voltage region and a low voltage region; forming a dielectric layer on the substrate, comprising: forming a dielectric material layer in the high voltage region and the low voltage region; and performing a thermal process to enlarge the dielectric material layer in the high voltage region, wherein a first thickness of a portion of the dielectric layer in the high voltage region is larger than a second thickness of a portion of the dielectric layer in the low voltage region; forming a buried diffusion region in the substrate in the memory region; forming a charge trapping layer and a blocking dielectric layer over the substrate in the memory region after the step of forming the buried diffusion region; forming a patterned conductive layer over the substrate so as to form a first gate, a second gate and a third gate in the high voltage region, the low voltage region, and the memory region respectively; and forming a source/drain region adjacent to the first gate in the high voltage region and adjacent to the second gate in the low voltage region in the substrate.