Patent ID: 8693490

Claim:
A method comprising: receiving, at an ingress module of a network processor, a data packet from a computer network, the data packet to be processed by one of a plurality of core processors of the network processor; storing, in a memory having a plurality of buffers, the data packet in the memory, the storing including storing distinct portions of the data packet in a set of buffers of the buffers if the data packet size exceeds a size of a buffer of the buffers; generating a packet buffer chain for the data packet, the generating including creating a plurality of packet buffer structures for the data packet, wherein one of the packet buffer structures is a header packet buffer structure corresponds to a first buffer of the set of buffers containing a first portion of the data packet, and wherein another one of the packet buffer structures is a tail packet buffer structure that corresponds to a last buffer of the set of buffers containing a last portion of the data packet, and linking each of the packet buffer structures from the header packet buffer structure to the tail packet buffer structure; adding the data packet to the input queue of the network processor, the adding including adding a pointer to the header packet buffer structure of the packet buffer chain of the data packet; determining whether the input queue contains queued data packets; responsive to a determination that the input queue contains queued data packets, obtaining a last data packet of the queued data packets; and updating a next packet pointer of a header packet buffer structure of a packet chain of the last data packet to point to the header packet buffer structure of the packet buffer chain of the data packet.