Patent ID: 7956406

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor region; a first insulating film on the semiconductor region; a charge storage layer on the first insulating film; a second insulating film which is provided on the charge storage layer, formed of a plurality of layers; and a control gate electrode on the second insulating film, wherein the second insulating film includes a bottom layer (A) provided above the charge storage layer, a top layer (C) provided below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C), the middle layer (B) has a higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C), an average coordination number of the middle layer (B) is smaller than that of the top layer (C), the average coordination number of the middle layer (B) is smaller than that of the bottom layer (A), the average coordination number of the middle layer (B) is 3 or less, the middle layer (B) comprises one of a silicon oxide film and a silicon oxynitride film, the middle layer (B) has a composition in which an average composition is represented by (SiO 2 ) x (Si 3 N 4 ) 1-x (0.75≦x≦1), the bottom layer (A) comprises one of Al-oxide, Al-oxynitride, Al-silicate, Al-nitride-silicate, Hf-oxide, and Al—Hf-oxide, and the top layer (C) comprises one of Al-oxide, Al-oxynitride, Al-silicate, and Al-nitride-silicate.