Patent ID: 7960234

Claim:
A method of fabricating a multi-gate transistor, the method comprising: forming a semiconductor structure over a semiconductor substrate, the semiconductor structure comprising: a channel region disposed within a fin of the multi-gate transistor, the channel region disposed between a source and a drain of the multi-gate transistor; a gate dielectric disposed about the channel region; and a gate electrode disposed about the gate dielectric, the gate electrode including first gate electrode material comprising a metal and second gate electrode material comprising polysilicon; selectively removing the second gate electrode material from the semiconductor structure using a dry plasma etch comprising oxygen; thereby exposing a vertically directed surface of the first gate electrode material to formation of metal oxide; performing a dry metal deglazing process to chemically remove metal oxide formed on the vertically directed surface of the first gate electrode material; and following the deglazing process, selectively removing portions of the first gate electrode material using an isotropic dry etch.