Patent ID: 8785112

Claim:
A method comprising: obtaining a first reticle with a first pattern corresponding to a design for a wafer pattern; detecting dark defects and/or design/OPC weak spots in the first pattern; obtaining a second reticle with a second pattern, the second pattern being dark except for openings corresponding to the dark defects and/or design/OPC weak spots in the first pattern, or forming a second pattern of openings on the first reticle, in a region outside the first pattern, the openings corresponding to the dark defects and/or design/OPC weak spots in the first pattern; exposing a resist covered wafer using the first and second patterns; including alignment marks and/or overlay marks and/or metrology structures on the second reticle or in the second pattern on the first reticle; providing matching overlay marks in the first pattern or on another reticle used for patterning a layer on the wafer prior to or subsequent to exposing the resist covered wafer using the first and second patterns; leaving dark areas in the first pattern at the positions corresponding to the metrology structures; and aligning the openings of the second pattern with the defects and/or design/OPC weak spots of the first pattern using the alignment marks; and/or measuring the structures corresponding to the overlay marks and/or metrology structures which are formed on the wafer after the exposures and development of the resist, thereby monitoring the process of the exposure with the second pattern.