Patent ID: 7227410

Claim:
A differential output circuit comprising first and second MOS transistors, first and second amplifiers, first and second loads, and first, second, third, fourth and fifth switches, wherein: said first MOS transistor has a gate connected to an output of said first amplifier, and a drain to said second and fourth switches; said first amplifier has a negative terminal connected to a first fixed potential, and a positive terminal to said first and second loads; said second MOS transistor has a gate connected to an output of said second amplifier, and a drain to said first and third switches; said second amplifier has a positive terminal connected to a second fixed potential, and a negative terminal to said fifth switch at a first terminal; said first and second switches are connected to a first node connected to said fifth switch at a second terminal and to said first load; said third and fourth switches are connected to a second node connected to said fifth switch at a third terminal and to said second load; said fifth switch has said second terminal connected to said first terminal when said second and third switches turn on; and said fifth switch has said third terminal connected to said first terminal when said first and fourth switches turn on.