Patent ID: 7287212

Claim:
An execution unit for performing a Viterbi decoding algorithm within a processor having general purpose registers, comprising an execution module including an AVIT instruction that determines updated state metrics and decision values for the Viterbi decoding algorithm, wherein said AVIT instruction comprises: receiving eight input metrics and eight state metrics, wherein an input metric is represented as input metrics[j], wherein a state metric is represented as states in[i]; calculating candidates(i,j)=(states_in[i]+input_metrics[j]), wherein candidates (i,j) is a nine bit value, wherein A0=candidate(0,0) B0=candidate(1,1) A1=candidate(0,2) B1=candidate(1,3) A2=candidate(0,1) B2=candidate(1,0) A3=candidate(0,3) B3=candidate(1,2) A4=candidate(4,4) B4=candidate(5,5) A5=candidate(4,6) B5=candidate(5,7) A6=candidate(4,5) B6=candidate(5,4) A7=candidate(4,7) B7=candidate(5,6) C0=candidate(2,2) D0=candidate(3,3) C1=candidate(2,0) D1=candidate(3,1) C2=candidate(2,3) D2=candidate(3,2) C3=candidate(2,1) D3=candidate(3,0) C4=candidate(6,6) D4=candidate(7,7) C5=candidate(6,4) D5=candidate(7,5) C6=candidate(6,7) D6=candidate(7,6) C7=candidate(6,5) D7=candidate(7,4) calculating, FOREACH i in 0..7 states_out[i] = (MIN(A<i>,B<i>,C<i>,D<i>))&0xff if(states_out[i]==A<i>) decisions[i] =0 | MSB(A<i>) if(states_out[i]==B<i>) decisions[i] =0x44 | MSB(B<i>) if(states_out[i]==C<i>) decisions[i] =0x28 | MSB(C<i>) if(states_out[i]==D<i>) decisions[i] =0x6C | MSB(D<i>), wherein MIN is defined as a value X out of a, b, c, and d for which WHICHMIN (X,Y) is 0 for all Y not equal to X in {a,b,c,d}, wherein WHICHMIN (a,b) is defined as if ((a−b)&0×80) then 0, otherwise 1, wherein & is bitwise AND, wherein MSB (a) is the most significant bit of (a); loading eight output state metrics into a set of state registers, wherein each output state metric is represented by states_out[i]; outputting eight 8-bit decision values, wherein each decision value includes: a bit 0 , wherein bit 0 is a value for reconstruction of the upper bits of final state metrics; bits 2 . . . 3 , wherein bits 2 . . . 3 is a value for encoding the path selected for state <i> in this decode step; and bits 4 . . . 5 , wherein bits 4 . . . 5 is a value for calculating bits u 1 and u 2 of the symbol which are most likely if the encoder was in state <i>.