Patent ID: 8354694

Claim:
A semiconductor structure comprising: a p-type field effect transistor (PFET) located above a silicon-germanium alloy layer in a substrate and including a germanium-containing source region, a germanium-containing drain region and an n-doped silicon-germanium alloy region having a same atomic ratio of germanium atoms to silicon atoms as said silicon-germanium alloy layer, wherein said silicon-germanium alloy layer includes silicon at a greater atomic concentration than said germanium-containing source region and said germanium-containing drain region, and said n-doped silicon-germanium alloy region contacts a surface of a gate dielectric of said PFET; and an n-type field effect transistor (NFET) located above said silicon-germanium alloy layer in said substrate and including a silicon-containing source region, a silicon-containing drain region and a p-doped silicon-germanium alloy region having a same atomic ratio of germanium atoms to silicon atoms as said silicon-germanium alloy layer, wherein said silicon-germanium alloy layer includes germanium at a greater atomic concentration than said silicon-containing source region and said silicon-containing drain region, and said p-doped silicon-germanium alloy region contacts a surface of a gate dielectric of said NFET.