Patent ID: 8332653

Claim:
A method for secure processing in a secure processing system having a processor and a plurality of secure operating modes, comprising: generating, using a cryptographic processor, a set of cryptographic keys, wherein the cryptographic processor is within a security boundary of the secure processing system; determining, responsive to a reset signal, whether a secure memory has been programmed with key material; selecting one of a plurality of boot sequences responsive to determining that the secure memory has been programmed with key material, wherein a first boot sequence in the plurality of boot sequences designates a first subset of memory locations accessible in a first secure operating mode, and wherein a second boot sequence in the plurality of boot sequences designates a second subset of memory locations accessible in a second secure operating mode; authenticating boot code for the selected boot sequence using a first key in the set of cryptographic keys; configuring a memory map designating open and secure memory locations based on the selected boot sequence; defining a policy for a selected secure operating mode based on the selected boot sequence; enforcing the selected secure operating mode using components within the security boundary, wherein enforcing the selected secure operating mode comprises: blocking access to secure peripherals based on the configuration of the memory map; decrypting secure code to be executed in the selected secure operating mode using a second key in the set of keys, and storing secure data for the selected secure operating mode in memory encrypted with the second key; and generating a signal enabling access of a master, configured to operate in the selected secure operating mode, to a memory location when the memory location is within a subset of secure memory locations corresponding to the selected secure operating mode.