Patent ID: 7340589

Claim:
A data processing device which performs pipeline control, the data processing device comprising: a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues, the instructions including a given target instruction and a prefix instruction which precedes the target instruction and modifies a function of the target instruction; a prefix instruction decoder circuit which performs decode processing only on a prefix instruction, the prefix instruction decoder circuit receiving the instruction codes of the instructions before decoding that are fetched in the instruction queues, judging whether or not each of the instruction codes is a given prefix instruction, and causing a target instruction modifying information register to store information necessary for decoding the target instruction modified by the prefix instruction when the judged instruction code is the given prefix instruction; and a general-purpose decoder circuit which receives each of the instruction codes of the instructions fetched in the instruction queues other than the prefix instruction as a decode instruction, and decodes the decode instruction, wherein, when the decode instruction is the target instruction, the decoder circuit decodes the target instruction modified by the prefix instruction based on target instruction modifying information stored in the target instruction modifying information register, wherein the given prefix instruction includes a shift prefix instruction for shifting an execution result of the target instruction, the function of which is expanded by the prefix instruction, wherein the prefix instruction decoder circuit causes the target instruction modifying information register to store shift information necessary for shifting the execution results of the target instruction modified by the shift prefix instruction when the input instruction code is the shift prefix instruction, and wherein the decoder circuit decodes the decode instruction so that the execution result of the target instruction modified by the shift prefix instruction is shifted based on the shift information stored in the target instruction modifying information register for execution of the target instruction when the decode instruction is the target instruction of the shift prefix instruction.