Patent ID: 7117398

Claim:
A program counter address comparator comprising: a first programmable reference address register storing a first reference address; a first comparator receiving said first reference address from said first programmable reference address register and a program counter address input for generating a greater than output, a less than output and an equal to output depending upon the relationship between said first reference address and the program counter address; a second programmable reference address register storing a second reference address; a second comparator receiving said second reference address from said second programmable reference address register and the program counter address for generating a greater than, less than or equal to output depending upon the relationship between said second reference address and the program counter address; first and second program counter compare control units connected to respective first and second comparators, each of said first and second program counter compare control units generating a corresponding first and second local event signal selectively dependent upon said greater than output, said less than output and said equal to output of said corresponding comparator and a corresponding first and second program counter compare event signal selectively dependent upon said local signal of the other program counter compare control unit.