Patent ID: 7327611

Claim:
A method of operating a memory cell comprising a gate, source and drain regions in a substrate region, and including a charge trapping structure, and one or more dielectric structures at least partly between the charge trapping structure and the gate and at least partly between the substrate region and the charge trapping structure, the method comprising: applying a read bias arrangement to determine a charge storage state of the charge trapping structure, wherein the read bias arrangement applies a voltage difference between the substrate region and one of the source region and the drain region, and floats the other of the source region and the drain region; measuring current flowing between the substrate region and said at least one of the source region and the drain region to determine the charge storage state of the charge trapping structure; applying an erase bias arrangement to adjust the charge storage state by increasing a net positive charge in the charge trapping structure; and applying a program bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure.