Patent ID: 8324684

Claim:
A planar, monolithic, high-voltage integrated circuit comprising: a semiconductor region of a first conductivity type over a semiconductor substrate of a second conductivity type, the semiconductor region forming a p-n junction with the semiconductor substrate; a first diffusion region of the first conductivity type in the semiconductor region, the semiconductor region extending vertically between the first diffusion region and the semiconductor substrate; a first field effect transistor (FET) includes: a first gate electrode, a first gate dielectric between the first gate electrode and the semiconductor region and over the semiconductor region, the first gate dielectric having a first and a second edge, a first body region of the second conductivity type in the semiconductor region wherein the first body region: overlaps a portion of the first gate dielectric at the first edge of the first gate dielectric, forms a p-n junction with the semiconductor region, and has an edge under the first gate dielectric, and a second diffusion region of the first conductivity type in the first body region and wherein the second diffusion region: overlaps a portion of the first gate dielectric at the first edge of the first gate dielectric, forms a p-n junction with the first body region, and has an edge under the first gate dielectric and, wherein: the first gate overlaps the second diffusion region less than the first gate overlaps the first body region, the first body region under the first gate dielectric and between the edge of the second diffusion region and the edge of the first body region is a first channel region, the first gate dielectric overlaps the semiconductor region at the second edge of the first gate dielectric, a portion of the semiconductor region between the first channel region and the first diffusion region is a drift region, and the first diffusion region is laterally spaced apart from the first channel region and is configured to receive a high voltage; a second FET includes: a second gate electrode, a second gate dielectric between the second gate electrode and the semiconductor region and over the semiconductor region, the second gate dielectric having a first and a second edge, and a third diffusion region of the first conductivity type in the semiconductor region wherein the third diffusion region is proximal to the first edge of the second gate dielectric, and wherein the second gate dielectric: is laterally disposed between the first and the third diffusion regions, is over a second channel region of the second FET, and overlaps the semiconductor region at the second edge of the second gate dielectric and, wherein; a portion of the semiconductor region between the second channel region and the first diffusion region is a drift region, and the first diffusion region is laterally spaced apart from the second channel region and is configured to receive the high voltage.