Patent ID: 7612397

Claim:
A memory cell comprising: a semiconductor substrate having a first conductivity type; two first impurity diffusion layers separately formed on the semiconductor substrate and having a second conductivity type different from the first conductivity type; a first gate electrode formed above a region containing at least a region sandwiched by the two first impurity diffusion layers through a first gate insulation film; a second impurity diffusion layer having the first conductivity type and formed above the semiconductor substrate so as to be separated from the semiconductor substrate by an impurity diffusion layer having the second conductivity type; a third impurity diffusion layer having the second conductivity type and formed on the semiconductor substrate; a second gate electrode formed above a region containing at least the second impurity diffusion layer through a second gate insulation film; a third gate electrode formed above a region containing at least the third impurity diffusion layer through a third gate insulation film; a MOS transistor comprising the semiconductor substrate, the first impurity diffusion layer, the first gate insulation film, and the first gate electrode; a first capacitor comprising the second impurity diffusion layer, the second gate insulation film, and the second gate electrode; a second capacitor comprising the third impurity diffusion layer, the third gate insulation film, and the third gate electrode; and a nonvolatile memory transistor in which one of the two first impurity diffusion layers is a source diffusion region, the other of the two first impurity diffusion layers is a drain diffusion region, the first gate electrode, the second gate electrode, and the third gate electrode are electrically connected to constitute a floating gate electrode, the second impurity diffusion layer constituting one electrode of the first capacitor is a first control gate electrode, and the third impurity diffusion layer constituting one electrode of the second capacitor is a second control gate electrode, wherein a different voltage can be applied to each of the first control gate electrode and the second gate electrode.