Patent ID: 7475313

Claim:
An integrated circuit comprising: a plurality of operational circuits to be tested; a test read only memory storing at least one test set consisting of a test algorithm and test data; and a programmable built-in self test unit connected to said plurality of operational circuits to be tested and said test read only memory including a first data register, said programmable built-in self test unit operable to load into said first data register from said test read only memory for each test set stored in said test read only memory said test data, a second data register, a pointer register storing data identifying one bit of said second data register, a multibit inverter connected to said first data register operable to invert each bit of a plurality of bits of said first data register, and a multibit multiplexer having a first input connected to said first data register, a second input connected to said multibit inverter, a control input receiving said bit of said second data register identified by said pointer register and an output, whereby said multibit multiplexer selects one of said first input and said second input for connection to said output; and wherein said programmable built-in self test unit is operable to test at least one of said plurality of operational circuits to be tested according to said test algorithm and said multibit multiplexer output.