Patent ID: 7936332

Claim:
A gate driving circuit comprising a shift register that has a plurality of stages cascade-connected to each other, the plurality of stages comprising one or more stages, each of which comprises: a pull-up section receiving a first clock signal, and passing the first clock signal as a gate signal when a first node signal is driven to a high voltage in response to a first input signal; a pull-down section discharging the gate signal to an off-voltage in response to a second input signal; a discharging section discharging the first node signal to the off-voltage in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage when the gate signal has been discharged to the off-voltage; and a second holding section responsive to a second clock signal, maintaining the first node signal at the off-voltage when the first input signal is at the off-voltage, wherein the second holding section has a greater transistor width-to-length ratio than the first holding section; said one or more stages each further comprising a carry section passing the first clock signal as a carry signal in response to the first node signal, wherein the second holding section has a smaller transistor width-to-length ratio than a sum of transistor width-to-length ratios of the first holding section and the carry section.