Patent ID: 7032121

Claim:
A method of generating a signal, comprising: providing a clock signal having a frequency (f osc ); determining a common divisor between the clock frequency (f osc ) and a reference frequency (f r ), the signal having an output frequency (f o ) given by k*f r where k is an integer; dividing the clock frequency (f osc ) by the common divisor to obtain a value N; dividing the value N by the integer k to obtain a ratio R and a remainder given by r/k; successively driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1−r/k and a fraction of times that the counter is driven to a count value of R+1 is given by r/k; and deriving the signal from an output of the counter.