Patent ID: 8645627

Claim:
A method of data processing in a data processing system including a processor core, a multi-level cache memory hierarchy including a lowest level cache, a memory controller, and a system memory coupled to the memory controller by a memory bus, said method comprising: the memory controller establishing a priority of read operations over write operations on the memory bus; the memory controller temporarily granting priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory, wherein: the lowest level cache is a set-associative cache including a plurality of congruence classes each having a plurality of ways including more recently used ways and less recently used ways, wherein the less recently used ways across all of the plurality of congruence classes are allocated as a virtual write queue into which the memory controller has visibility; temporarily granting priority to write operations comprises temporarily granting priority to write operations over read operations on the memory bus based upon a number of dirty cachelines within the virtual write queue but not based upon a number of dirty cachelines within the more recently used ways; and while write operations have priority of read operations on the memory bus, the memory controller issuing one or more write operations from a physical write queue of the memory controller to the system memory via the memory bus.