Patent ID: 8106874

Claim:
A shift register comprising: at least two clock transmission lines configured for transmitting a first clock pulse and a second clock pulse, wherein the first clock pulse and the second clock pulse have an amplitude, a duty ratio, and a frequency, and wherein the first clock pulse has an inverse phase relative to a phase of the second clock pulse; a plurality of stages receiving the clock pulses from the at least two clock transmission lines, and outputting a plurality of output-signals in sequence, wherein a first alternating stage of the plurality of stages receives the first clock pulse, and wherein a second alternating stage of the plurality of stages receives the second clock pulse; wherein each of the plurality of stages comprises: a voltage high input, a voltage low input, a first input, a second input, a first output, and a second output, wherein the voltage high input receives a high-level voltage signal, wherein the voltage low input receives a low-level voltage signal; an input circuit configured for receiving a first pulse signal from a previous stage for generating a reference signal, wherein a first stage of the plurality of stages receives a start signal applied by an external circuit; an output circuit configured for generating the first pulse signal to the first input of a next stage from the first output of the previous stage, and a second pulse signal to the second input of the previous stage from the second output of the next stage according to the reference signal, and one of the first clock pulse and the second clock pulse; wherein the input circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first inverter, wherein the voltage high input is first connected to the voltage low input via a source and a drain of the first transistor, a source and a drain of the third transistor, and a source and a drain of the fifth transistor connected sequentially and in series, and further first connected to the voltage low input via a source and a drain of the second transistor, a source and a drain of the fourth transistor, and a source and a drain of the sixth transistor connected sequentially and in series, gates of the first and fifth transistors are connected to the first input, gates of the second and sixth transistors are connected to the second input directly, gates of the third and fourth transistors are connected to an output terminal of the first inverter, the drains of the second and third transistors are connected together directly.