Patent ID: 7583118

Claim:
A delay locked loop (DLL) circuit, comprising: a first DLL section configured to receive a reference clock signal, to delay said reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay; a second DLL section, coupled in series to the first DLL section with respect to the reference clock signal, configured to delay said reference clock signal in response to a second control signal, and to generate said second control signal based on said reference clock signal delayed in said second DLL section and said phase delayed signal; and an input signal delay section configured to delay an input signal in response to said second control signal, wherein said first DLL section comprises: a first delay section configured to delay said reference clock signal over a plurality of delay stages in response to said first control signal; and a first control circuit configured to generate said first control signal from the reference clock signal and said reference clock signal delayed over said plurality of delay stages, wherein said first delay section outputs the delayed reference clock signals from some of said plurality of delay stages, and wherein said first DLL section further comprises: a first fixed delay circuit having a first fixed delay amount and configured to generate said phase delayed signal from some delayed reference clock signals.