Patent ID: 8760907

Claim:
A ferroelectric memory comprising: a plurality of ferroelectric memory cells, each ferroelectric memory cell comprising a ferroelectric capacitor; a write line; a read line; a plurality of ferroelectric memory cell select buses, one said select bus corresponding to each of said ferroelectric memory cells, wherein each of said ferroelectric memory cells comprises first and second gates for connecting said ferroelectric memory cell to said read line and said write line, respectively, in response to signals on said ferroelectric memory cell select bus corresponding to that ferroelectric memory cell; a write circuit that causes a charge to be stored in said ferroelectric capacitor of said ferroelectric memory cell currently connected to said write line, said charge having at least three different values determined by a data value having at least three states, each data value state corresponding to one of said charge values, none of said charges causing said ferroelectric capacitor to be fully polarized; and a read circuit that measures said charge stored in said ferroelectric capacitor of said ferroelectric memory cell currently connected to said read line to generate an output value, said output value corresponding to one of said states.