Patent ID: 7375562

Claim:
A method for indicating synchronizing edges of first clock and second clock signals, wherein the first and second clock signals have a gear ratio relationship, the second clock signal is synchronized with the first clock signal by a phase locked loop (PLL) comprising a pre-divider coupled to the first clock signal to divide a first input clock signal by a first integer into a third clock signal of a third frequency and a loop-divider coupled to the second clock signal to divide a second input clock signal by a second integer into a fourth clock signal of a fourth frequency, wherein the third and fourth frequencies are the same when the PLL is locked, the method comprising: obtaining a sample clock signal the frequency of which is a common divisor of the first and second clock signals by dividing the first or second clock signal; and generating an output clock signal indicative of the synchronizing edges of the first and second clock signals by detecting the edges of the sample clock signal, wherein generating the output clock signal at the synchronizing edges of the first clock signal and the second clock signal comprises: employing the first or second clock signal as a reference clock signal; generating a global signal asserted by the rising edges of the sample clock signal; generating a local signal asserted by a counting signal when the counting signal reaches a first value, wherein the counting signal is incremented on each edge of the reference signal and is reset by the global and local clock signals; and generating the output clock signal asserted when the counting signal reaches a second value.