Patent ID: 7747807

Claim:
A host controller that transfers data through a bus using a differential signal pair and transmits to device packets defined by a given standard at given intervals defined by the given standard, the differential signal pair being made up by a first differential signal and a second differential signal, the host controller comprising: a first comparator that is configured to receive the first differential signal, the first comparator being configured to compare a first voltage level of the first differential signal corresponding to a given packet in the device packets with a comparison voltage, and the first comparator being configured to detect that a host and a device have been disconnected when the first voltage level of the first differential signal corresponding to the given packet is higher than the comparison voltage; and a second comparator that is configured to receive the second differential signal, the second comparator being configured to compare a second voltage level of the second differential signal corresponding to the given packet in the device packets with the comparison voltage, and the second comparator being configured to detect that the host and the device have been disconnected when the second voltage level of the second differential signal corresponding to the given packet is higher than the comparison voltage, each of the first comparator and the second comparator including a first differential amplifier and a second differential amplifier; the first differential amplifier including a first input transistor and a second input transistor, the first input transistor and the second input transistor being connected in parallel between a first power supply and a second power supply of which power supply voltage being lower than that of the first power supply; the comparison voltage being input to a gate of the first input transistor; one of the first differential signal and the second differential signal being input to a gate of the second input transistor of the first differential amplifier of the first comparator; another of the first differential signal and second differential signal being input to a gate of the second input transistor of the first differential amplifier of the second comparator; the second differential amplifier including a third input transistor and a fourth input transistor the third input transistor and the forth input transistor being connected in parallel between the first power supply and the second power supply; a gate of the fourth input transistor being connected with a first output node connected between the first input transistor and the second power supply; and a gate of the third input transistor being connected with a second output node connected between the second input transistor and the second power supply.