Patent ID: 8780958

Claim:
A hybrid bit detection circuit for receiving global positioning bits from different types of satellite systems, the hybrid bit detection circuit comprising: a frequency lock loop (FLL) for receiving the global positioning bits from the different types of satellite systems and removing Doppler frequency error; an integrate and dump block coupled to an output of the FLL; a coherent detection circuit coupled to an output of the FLL and an output of the integrated and dump block; a coherent parity check block coupled to an output of the coherent detection circuit; a differential detection circuit coupled to the output of the integrate and dump block; a differential parity check block coupled to an output of the differential detection circuit, wherein the coherent detection circuit includes: a filter coupled to the output of the FLL; a subtractor for subtracting an output of the filter from the output of the FLL; an FLL noise removal block for receiving outputs of the subtractor and the integrate and dump block; a phase lock loop (PLL); a PLL control block for resetting the PLL based on output of the subtractor and PLL; a match filter for determining a maximum likelihood set of bits corresponding to the global positioning bits based on an output of the FLL noise removal block.