Patent ID: 7978451

Claim:
A circuit arrangement comprising: an electronic component having first and second terminals; and an ESD protection arrangement against disturbance pulses, which is coupled via connection terminals in parallel with the electronic component between the first and second terminals, the ESD protection arrangement comprising: a first ESD protection unit; and a second ESD protection unit, coupled in parallel with the first ESD protection unit, wherein the second ESD protection unit reacts more rapidly than the first ESD protection unit to a voltage rise at the connection terminals with a formation of a conductive current path between the connection terminals, wherein the second ESD protection unit comprises a MOS transistor having load path terminals coupled between the first and second terminals and having a control terminal, the control terminal of the MOS transistor being short-circuited with one of the load path terminals or being coupled to one of the load path terminals via a resistor, and the MOS transistor of the second ESD protection unit comprises a cellularly constructed MOS transistor having a first number of transistor cells.