Patent ID: 7368347

Claim:
A method for fabricating a dual bit memory device, the method comprising the steps of: forming a charge trapping layer overlying a substrate; fabricating two insulating members overlying the charge trapping layer; providing a first polycrystalline silicon layer overlying the charge trapping layer and about a first portion of sidewalls of the two insulating members; forming sidewall spacers overlying the first polycrystalline silicon layer and about a second portion of the sidewalls of the two insulating members; using the sidewall spacers as an etch mask, removing a portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer and exposing a first portion of the substrate; conformally depositing a first insulating layer overlying the insulating members and the exposed first portion of the substrate; forming a gate spacer between the two insulating members and overlying the first insulating layer; removing the two insulating members; etching a second portion of the charge trapping layer to form charge storage nodes and exposing a second portion of the substrate; and implanting impurity dopants into the second portion of the substrate to form impurity-doped bitline regions within the substrate, wherein the impurity-doped bitline regions are in electrical communication with the charge storage nodes.