Patent ID: 7984345

Claim:
A test apparatus which tests a memory under test storing, in each of its pages, a data sequence affixed with an error check and correction code, the test apparatus comprising: a test processing section which reads out, for each page, which is a unit of error correction, the data sequence stored in that page from the memory under test; a logical comparator which compares a value of each bit included in the data sequence read out from the memory under test with an expectation value of that bit; a first failure memory which stores, for each storage cell of the memory under test, bit pass/failure information indicating whether the storage cell is good or defective, based on a result of comparison by the logical comparator; a data error counting section which counts, for each page, a number of bits that do not match the expectation value; a page classifying section which judges, for each page and for each of a plurality of grades into which the memory under test is classified based on its quality, whether the number of bits that do not match the expectation value meets a condition of that grade; a second failure memory which stores, for each of the plurality of grades, page pass/failure information indicating whether each page is good or defective, based on a result of judgment by the page classifying section; and an output section which, in outputting the bit pass/failure information of each storage cell for each of the plurality of grades, if page pass/failure information indicating that a page including a bit corresponding to the storage cell meets the condition of that grade is stored in the second failure memory, changes the bit pass/failure information output from the first failure memory indicating that the storage cell is defective to bit pass/failure information indicating that the storage cell is not defective and outputs the changed bit pass/failure information, wherein the page classifying section comprises: a plurality of registers which are prepared correspondingly to the plurality of grades, and which respectively store upper limit values of a number of errors included in a page of the memory under test; a comparing section which compares each of the plurality of upper limit values stored in the plurality of registers with a count value of the data error counting section; and a judging section which, on a condition that the count value of the data sequence read out from the memory under test is equal to or smaller than the upper limit value, judges that the page which stores that data sequence meets the condition of the grade corresponding to that upper limit value.