Patent ID: 7183221

Claim:
A method of fabricating a semiconductor, comprising: depositing a metal layer outwardly from a dielectric layer; forming a mask layer outwardly from a first portion of the metal layer, the mask layer masking the first portion of the metal layer; incorporating a plurality of atoms into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer; removing the mask layer from the first portion of the metal layer; depositing a barrier layer outwardly from the first portion and the second portion of the metal layer; depositing a poly-Si layer outwardly from the barrier layer to form a semiconductor layer, the barrier layer operable to substantially prevent diffusion and reaction between the metal layer and the poly-Si layer; and etching the semiconductor layer to form a gate stack structure, the gate stack structure comprising a first gate electrode and a second gate electrode, the first gate electrode comprising at least part of the first portion of the metal layer and operating according to a first work function, the second gate electrode comprising at least part of the composition-altered portion of the metal layer and operating according to a second work function.