Patent ID: 7438557

Claim:
A stacked multiple electronic component interconnect structure comprising: a connector portion including a first connector surface provided with a first plurality of connector pads and a second connector surface provided with a second plurality of connector pads, wherein the connector portion is a flexible cable having a first plurality of conductors operatively connected to the first plurality of connector pads and a second plurality of conductors operatively connected to the second plurality of connector pads, the first plurality of conductors being distinct from the second plurality of conductors; a first double sided land grid array having a first surface provided with a first plurality of connector units and a second surface provided with a second plurality of connector units, the first surface being positioned on the first connector surface with the first plurality of connector units of the first double sided land grid array interfacing with the first plurality of connector pads; a second double sided land grid array having a first surface provided with a first plurality of connector units and a second surface provided with a second plurality of connector units, the first surface being positioned on the second connector surface with the first plurality of connector units of the second double sided land grid array interfacing with the second plurality of connector pads; a first electronic component mounted to the second surface of the first double sided land grid array, the first electronic component having a plurality of connector members that interface with the second plurality of connector units of the first double sided land grid array; a second electronic component mounted to the second surface of the second doubled sided land grid array, the second electronic component having a plurality of connector members that interface with the second plurality of connector units of the second double sided land grid array to form a stacked multiple electronic component interconnect structure that conserves space on an electronic board; and a circuit board having an electronic component interface cavity, the second electronic component being mounted in the electronic component interface cavity.