Patent ID: 7081381

Claim:
A method for forming a flash EEPROM on a substrate with other linear or logic devices comprising the steps of: isolating an EEPROM region from a linear or device region(s); forming a triple well in the EEPROM region; forming an EEPROM gate stack including a tunnel dielectric layer, a tunnel gate layer, a control dielectric layer, and a control gate layer; covering the substrate with a first deposited hard mask layer; opening the first deposited oxide layer to expose EEPROM source and drain regions; implanting the exposed EEPROM source and drain regions; covering the substrate with a second deposited hard mask layer; opening the second deposited oxide layer to expose linear or logic source and drain region(s); implanting the exposed linear or logic source and drain regions; forming gate stacks for logic or linear devices; and forming dielectric layers on the sidewalls of said EEPROM gate stack and on the sidewalls of said gate stack for said logic or linear devices wherein said dielectric layers on said sidewalls of said EEPROM gate stack is thicker than the dielectric layers on the sidewalls of said logic or linear devices.