Patent ID: 7205826

Claim:
A biasing circuit with power-down capability comprising: a current source connected to a drain of a first NMOS transistor through a first switch; a gate of the first NMOS transistor connected to the current source, and a source of the first NMOS transistor connected to ground; a first capacitor connected between the gate of the first NMOS transistor and ground; and a plurality of NMOS transistors forming a current multiplier and having gates connected to the current source; a plurality of current mirrors connected to drains of the plurality of NMOS transistors and to output switches, wherein each current mirror comprises: a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage, a second capacitor connected between the gate of the first PMOS transistor and the supply voltage, and a current multiplier connected to the output switches.