Patent ID: 7510918

Claim:
A method of manufacturing a transistor, the method comprising: providing an insulating layer having a first region and a second region enclosing the first region; forming an active pattern on the insulating layer in the first region; forming a dummy structure on the second region; forming a gate dielectric layer on the active pattern; forming a gate electrode pattern on the gate dielectric layer; forming a spacer on a sidewall of the gate electrode, the spacer covering a part of the gate dielectric layer; removing a part of the gate dielectric layer that is not covered by the spacer; forming an epitaxial growth structure on the first region to form a source/drain structure; and wherein the epitaxial growth structure is in contact with the active pattern, and wherein forming the dummy structure comprises: forming a first dummy layer on the insulating layer and on the active pattern; forming a second dummy layer on the first dummy layer; forming a second dummy layer pattern by partially removing the second dummy layer formed on the first region; forming a first dummy layer pattern using a first etching process for the first dummy layer formed on the first region and a part of it formed on the second region so that an undercut region is formed under the edge of the second dummy layer pattern; forming a third dummy layer on the second dummy layer pattern, the insulating layer, the active patterns, and in the undercut region; and forming a third dummy layer pattern in the undercut region using a second etching process and by removing the third dummy layer formed on the second dummy layer pattern, the insulating layer, and on the active pattern.