Patent ID: 7167023

Claim:
An integrated circuit comprising: a plurality of pads arranged along a peripheral region of the integrated circuit; a plurality of programmable logic elements arranged in a plurality of rows and columns in an interior portion of the integrated circuit, the programmable logic elements configurable to perform user-defined functions; a plurality of I/O banks arranged along at least part of the peripheral region of the integrated circuit, each I/O bank comprising at least one I/O section, each I/O section comprising: a plurality of I/O register blocks, each I/O register block having an input coupled to one of the plurality of pads; and a delay block having an input coupled to one of the plurality of pads and an output coupled to a clock input for each of the plurality of I/O register blocks; a plurality of programmable interconnect lines, configurable to couple the plurality of programmable logic elements to the plurality of I/O banks; and a delay-locked loop coupled to calibrate a delay through the delay block.