Patent ID: 6861284

Claim:
A method of producing a semiconductor device including an insulating core substrate, a plurality of layers of wiring patterns on said core substrate, and insulating layers each interposed between said wiring patterns, each adjacent pair of said wiring patterns being electrically connected to each other through conductor portions penetrating through said insulating layer interposed between said adjacent wiring patterns, said method comprising the steps of: press-bonding an electric insulating film to a surface of the core substrate, on which surface semiconductor chips connected electrically to said wiring patterns by flip-chip bonding are mounted, to form an electric insulating layer covering said semiconductor chips and said wiring patterns; forming via-holes in said electric insulating layers to expose said wiring pattern as a bottom thereof; forming a plating power feed layer for electrolytic plating on an inner surface of said via-holes and on a surface of said electric insulating layer, electrolytically plating said plating power feed layer to form a via-portion on the inner surface of each of said via-holes and a conductor layer on the surface of said electric insulating layer; etching said conductor layer to form a wiring pattern electrically connected to said wiring pattern of a lower layer through said via-portion; and mounting said semiconductor chips on said wiring pattern, and forming an electrical connection, by flip-chip bonding.