Patent ID: 7286416

Claim:
A non-volatile semiconductor memory device, comprising: a memory array having a plurality of non-volatile memory cells, arranged in rows and columns, each for storing data in a non-volatile manner; predecode circuitry arranged along one side of said memory array, for predecoding an address signal designating a memory cell of said memory array, and generating a predecoded address signal; address latch circuitry arranged along the one side of said memory array corresponding to said predecode circuitry, for latching the predecoded address signal from said predecode circuitry; cell selecting circuitry responsive to latching of the address of said address latch circuitry, for selecting an addressed memory cell of said memory array in accordance with the latched predecoded address signal latched by said address latch circuitry; and data reading circuitry for reading, in a data reading mode, data of the memory cell selected by said cell selecting circuitry, wherein said memory array is divided into a plurality of blocks; said address latch circuitry includes a plurality of address latch circuits arranged corresponding to respective blocks; and said cell selecting circuitry includes a plurality of decode circuits, arranged corresponding to the blocks, each for decoding the address signal from the address latch circuit arranged for the corresponding block and generating a cell selection signal, with interconnections between said plurality of address latch circuits and corresponding decode circuits being made equal in length to each other.