Patent ID: 7928492

Claim:
A non-volatile memory integrated circuit device comprising: a semiconductor substrate having a plurality of substantially rectangular field regions arranged in a matrix form, a short side and a long side of each of the substantially rectangular field regions being parallel to a row direction and a column direction of a matrix, respectively; word lines and select lines extending parallel to the row direction of the matrix on the semiconductor substrate, the word lines crossing the substantially rectangular field regions arranged in the row direction of the matrix, and the select lines partially overlapping the substantially rectangular field regions arranged in the row direction of the matrix, such that overlapping parts of long sides of the substantially rectangular field regions and overlapping short sides of the overlapping substantially rectangular field regions are located below the select lines without crossing the select lines such that end portions of the substantially rectangular field regions are located below the select lines; and a floating junction region formed within the semiconductor substrate between the word lines and the select lines, a bit line junction region formed opposite the floating junction region with respect to the word lines, and a common source region formed opposite the floating junction region with respect to the select lines.