Patent ID: 7834945

Claim:
A thin film transistor substrate, comprising: an insulation plate; a first signal line formed on the insulation plate and defining a first boundary of a pixel area; a storage electrode line formed on the insulation plate traversing a middle portion of the pixel area, the storage electrode line comprising a storage electrode having a larger width than the other portion of the storage electrode line; a gate insulation layer formed on the first signal line and the storage electrode line; a second signal line formed on the gate insulation layer and insulated from the first signal line and the storage electrode line, the second signal line crossing the first signal line and forming a second boundary of the pixel area; a coupling electrode formed on the gate insulation layer and fully overlapping the storage electrode; a thin film transistor comprising: a first terminal connected to the first signal line; a second terminal connected to the second signal line; and a third terminal; a passivation layer formed on the second signal line, the coupling electrode and the thin film transistor, the passivation layer comprising a first contact hole and a second contact hole; a first pixel electrode formed on the passivation layer, the first pixel electrode connected to the third terminal of the thin film transistor through the first contact hole and connected to the coupling electrode through the second contact hole; and a second pixel electrode formed on the passivation layer, the second pixel electrode separated from the first pixel electrode by an opening area and partially overlapped with the coupling electrode, the opening area comprising: a first portion having an upper part and a lower part, the upper part located in a pixel area above the storage electrode line and extending in a first diagonal direction from the storage electrode line, the lower part located in a pixel area below the storage electrode line and extending in a second diagonal direction from the storage electrode line; and a second portion substantially orthogonal with the storage electrode line and substantially fully overlapped with the storage electrode, wherein the first pixel electrode and the second pixel electrode are alternately arranged along a direction of the first signal line, and the coupling electrode overlaps the second portion of the opening area.