Patent ID: 7868357

Claim:
A gate driver-on-array structure for using in a display panel, comprising: a plurality of first conductive patterns, wherein the first conductive patterns are separated from each other; a plurality of semiconductor patterns disposed on the first conductive patterns; a plurality of second conductive patterns disposed on the semiconductor patterns, wherein each of the second conductive patterns substantially forms a U-shape; a plurality of third conductive patterns disposed on the semiconductor patterns, wherein each of the third conductive patterns is disposed correspondingly in one of the second conductive patterns, and wherein the first conductive patterns, the second conductive patterns, the semiconductor patterns and the third conductive patterns together form a plurality of thin film transistors; a first electrode line located at a side of the first conductive patterns and spaced from the first conductive patterns by a first distance; and a plurality of first connectors connected to the corresponding first conductive patterns and the first electrode line.