Patent ID: 8368213

Claim:
An integrated circuit device comprising: a silicon substrate; multiple layers of interconnecting lines; multiple insulating layers comprising an oxide; multiple metal vias in said multiple insulating layers and between said multiple layers of interconnecting lines, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines; a polymer layer over said silicon substrate, wherein an opening in said polymer layer is over a contact point of said multiple layers of interconnecting lines; and a metal bump on said contact point and on a top surface of said polymer layer, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises a metal layer on said contact point and on said top surface of said polymer layer, a copper pillar on said metal layer, wherein said copper pillar has a thickness between 10 micrometers and 100 micrometers, a nickel-containing layer on said copper pillar, wherein said nickel-containing layer has a width greater than said thickness of said copper pillar, and a spherical-contoured solder bump on said nickel-containing layer, wherein a left edge of said spherical-contoured solder bump extends further than a left edge of said nickel-containing layer and wherein a right edge of said semi-spherical contoured solder bump extends further than a right edge of said nickel-containing layer.