Patent ID: 8482293

Claim:
A method for calibrating an input/output (I/O) circuit in a chip, the I/O circuit having an output end, the chip comprising a plurality of basic impedances and a non-volatile memory, the method comprising: measuring an impedance value of one of the basic impedances, and recording the measured impedance value into the non-volatile memory; rendering a driving impedance at the output end of the I/O circuit; synthesizing a calibration impedance by utilizing the basic impedances; and estimating an impedance value of the driving impedance according to the calibration impedance to calibrate the I/O circuit, wherein the I/O circuit changes the impedance value of the driving impedance according to a strength control; the rendering the driving strength step sets the strength control to a first control value to render the driving impedance in a first impedance value at the output end of the I/O circuit; and the estimating step estimates the first impedance value according to the calibration impedance, and wherein: the I/O circuit is a reference I/O circuit; the driving impedance is rendered by the reference I/O circuit in the rendering the driving impedance step and the estimating step; the chip further comprises a plurality of I/O circuits, each of which matching with the reference I/O circuit; and the method further comprising determining strength controls corresponding to the plurality of I/O circuits according to calibration results of the reference I/O circuit.