Patent ID: 7644251

Claim:
A controller comprising: volatile random access memory including a table having at least one entry, the at least one entry including a significant address bit portion of a physical address of a memory location at a NAND flash non-volatile solid-state memory, the significant address bit portion comprising one of a block portion or a block and page portion; and translation hardware, the volatile random access memory accessible to the translation hardware, the translation hardware configured to sum binary data bits of a portion of a logical address and a pointer value to determine a random access memory address of the at least one entry and configured to determine the significant address bit portion of the physical address of the memory location at the NAND flash non-volatile solid-state memory based at least in part on the random access memory address of the at least one entry, wherein the physical address of the memory location is determined by directly appending a designated offset portion of the logical address to the significant address bit portion of the physical address, wherein the translation hardware is further configured to update the table by loading and executing software instructions stored at the NAND flash non-volatile solid-state memory.