Patent ID: 7964976

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes a plurality of layer portions stacked; the plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type; the at least one layer portion of the first type and the at least one layer portion of the second type each include a semiconductor chip; each of the semiconductor chips has a first surface and a second surface that are opposite to each other and a plurality of terminals disposed on the first surface; the at least one layer portion of the first type further includes a plurality of electrodes each having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, each of the plurality of electrodes having a portion that extends along the first surface of the semiconductor chip of the layer portion of the first type and that is connected to any one of the plurality of terminals of the semiconductor chip of the layer portion of the first type, whereas the at least one layer portion of the second type does not include any electrode having a portion that extends along the first surface of the semiconductor chip of the layer portion of the second type and that is connected to any one of the plurality of terminals of the semiconductor chip of the layer portion of the second type; and the wiring is connected to the end face of each of the plurality of electrodes.