Patent ID: 7538576

Claim:
A non-volatile-memory-transistor based lookup table for an FPGA including: a multiplexer having a plurality of address inputs, a plurality of data inputs, and an output; a plurality of multiplexer input circuits, each multiplexer input coupled to a different one of the data inputs of the multiplexer and including: a first n-channel transistor having a drain coupled to a voltage potential, a gate, and a source; a second n-channel transistor having a drain coupled to the source of the first n-channel transistor, a gate, and a source coupled to ground; a first non-volatile memory cell having an output coupled to the gate of the first n-channel transistor; a second non-volatile memory cell having an output coupled to the gate of the second n-channel transistor; n-channel transistors coupled to each of the data inputs of the multiplexer; a sense amplifier coupled to the output of the multiplexer.