Patent ID: 8667194

Claim:
In a system that includes a master component that is configured to communicate with one or more slave components over a clock wire and a data wire, a method for the master component to communicate over the data wire while enabling recovery of synchronization between the master component and the one or more slave components, the method comprising: determining that an operation is to be performed on a slave component of the one or more slave components; monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component; detecting at least a predetermined number “n” of consecutive bits of the same binary polarity that have occurred on the data wire while monitoring the data wire, the predetermined number of consecutive bits comprising a preamble of a frame, the preamble being automatically asserted on the data wire without the master component or the slave component needing to affirmatively assert the preamble on the data wire; transmitting a three bit operational code designating an operation state and a structure of the frame; dynamically adjusting the structure of the frame based at least partially on bandwidth available; and transmitting non-preamble portions of the frame over the data wire with guaranteed bits unconditionally inserted in predetermined bit positions that are positioned at least every “n” consecutive bit positions in the non-preamble portions of the frame, each predetermined bit position being offset a predetermined number of consecutive bit positions from the last bit position of the preamble, the guaranteed bits being opposite in polarity with respect to the preamble bits' polarity.