Patent ID: 7737508

Claim:
A non-volatile semiconductor memory device, comprising: a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; a plurality of selection gate transistors each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line; an element isolation region formed in a peripheral circuit portion outside a region in which the plurality of memory cell units are formed; a first diffusion region formed under the element isolation region; and a second diffusion region formed at a same depth as the first diffusion region from the boundary between the semiconductor substrate and the gate insulation film, the second diffusion region having a same conductivity as the first diffusion region, wherein the plurality of selection gate transistors have a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line, the pair of selection gate transistors have substantially the same structure, each of the pair of transistors has a portion in which an impurity concentration of a channel region thereof is constant in a gate length direction at a depth from the boundary between the semiconductor substrate and the gate insulation film, and the concentration distribution of impurity of the channel region of each transistor is same as that of a channel region of the memory cell, one end of the second diffusion region is between one of the pair of selection gate transistors and the memory cell adjacent to the one of the pair of selection gate transistors, and an other end of the second diffusion region is between other of the pair of selection gate transistors and the memory cell adjacent to the other of the pair of selection gate transistors.