Patent ID: 7033860

Claim:
A process for manufacturing a semiconductor device, said process comprising: covering an electrode terminal forming surface of a semiconductor wafer, on which a plurality of semiconductor elements are formed and arranged, with a cover layer comprising a flexible insulating film on which re-wiring patterns are formed, to adhere said cover layer to said electrode terminal forming surface in such a manner that electrode terminals of the semiconductor elements are electrically connected with connecting terminals of the re-wiring patterns; forming said semiconductor wafer with grooves from a surface opposite to said electrode terminal forming surface thereof, so that said grooves extend along boundary lines of said respective semiconductor elements; dividing said semiconductor wafer with said cover layer to obtain a plurality of units, each unit comprising a plurality of said divided semiconductor elements and a single sub-divided cover layer to define a single semiconductor device; and folding said divided cover layer of said respective divided unit along said grooves, so that at least some of said semiconductor elements in the respective unit are stacked.