Patent ID: 7386418

Claim:
A wafer fabricating method, comprising: inspecting a first wafer to obtain wafer defect data containing defect information for every die in the first wafer; generating a wafer map displaying defective dies and defect-free dies in the first wafer in accordance with the wafer defect data; determining an overall yield in accordance with the wafer defect data; determining a first systematic limited yield in accordance with the wafer defect data and the wafer map, wherein the first systematic limited yield is calculated excluding defective dies with localized distribution; determining a second systematic limited yield in accordance with the wafer defect data and the wafer map, wherein the second systematic limited yield is calculated excluding defective dies with repeated distribution; determining a random defect limited yield in accordance with the overall yield, the first systematic limited yield, and the second systematic limited yield; generating processing tool setting information in accordance with the overall yield, the first systematic limited yield, the second systematic limited yield, and the random defect limited yield; setting a plurality of processing tools in accordance with the processing tool setting information; and processing a second wafer with the processing tools.