Patent ID: 8659088

Claim:
An SRAM cell comprising a first, second, third and fourth semiconductor thin plates standing on a single substrate and sequentially arranged parallel to each other, on the first semiconductor thin plate a first four-terminal double gate FET with a first conduction type and a second four-terminal double gate FET with a second conduction type being formed and connected in series to each other, on the second semiconductor thin plate a third four-terminal double gate FET with the second conduction type being formed, on the third semiconductor thin plate a fourth four-terminal double gate FET with the second conduction type being formed, on the fourth semiconductor thin plate a fifth four-terminal double gate FET with the first conduction type and a sixth four-terminal double gate FET with the second conduction type being formed and being connected in series to each other, wherein the second and sixth four-terminal double gate FETs constitute select transistors with logic signal input gates thereof being connected to a word line, and wherein the first and third four-terminal double gate FETs and the fourth and the fifth four-terminal double gate FETs respectively constitute cross-coupled complementary inverters to realize a flip-flop, the SRAM cell having the first four-terminal double gate FET and the third four-terminal double gate FET neighboring each other and wherein logic signal input gates thereof are formed on the side surfaces facing the respective semiconductor thin plates; the fourth four-terminal double gate FET and the fifth four-terminal double gate FET are neighboring with each other and logic input gates thereof are formed on the side surfaces facing the respective semiconductor thin plates; the third four-terminal double gate FET and the fourth four-terminal double gate FET are neighboring with each other and threshold voltage control gates thereof are formed on the side surfaces facing the respective semiconductor thin plates; the second four-terminal double gate FET and the sixth four-terminal double gate FET are neighboring with each other sandwiching the second and third semiconductor thin plates and threshold voltage control gates thereof are formed on side surfaces facing the respective semiconductor thin plate; the threshold voltage control gates of the second, third, fourth, and sixth four-terminal double gate FETs are connected in common to a first bias wiring; threshold voltage control gates of the first and the fifth four-terminal double gate FETs are connected in common to a second bias wiring; the word line and the first and the second bias wirings are arranged in a direction perpendicular to the arrangement direction of the first, second, third and fourth semiconductor thin plates.