Patent ID: 6842039

Claim:
An integrated circuit comprising: a plurality of I/O blocks; a plurality of I/O configuration elements including outputs, the I/O configuration elements being coupled together as a shift register on a periphery of the integrated circuit, and the I/O configuration elements also being coupled to the plurality of I/O blocks for driving, each of the plurality of I/O blocks to one of multiple prescribed I/O configuration states based upon configuration bits provided at the outputs of the plurality of I/O configuration elements; a boundary scan chain comprising a plurality of boundary scan elements; a first pin; and a demultiplexer including at least an input, a first output, and a second output, the input being coupled to the first pin, the first output being coupled to a first one of the plurality of I/O configuration elements, the second output bin coupled to the boundary scan chain, the demultiplexer being for selecting either the configuration shift register the bound scan chain to receive data through first pin.