Patent ID: 8564469

Claim:
A pipelined analog-to-digital converter comprising: a conversion stage part including a plurality of serially connected conversion stages, each of the plurality of serially connected conversion stages converting an input voltage a B-bit digital code in response to at least one clock signal and outputting a residual voltage; and a digital correction circuit configured to perform a logic correction operation by binary shifting the B-bit digital codes output from the plurality of serially connected conversion stages, wherein each of the plurality of serially connected conversion stages comprises: a multiplying digital-to-analog converter configured to convert a (2 B −1)-bit digital code into an analog signal in response to the at least one clock signal and to output the residual voltage by subtracting the converted analog signal from the input voltage; and an analog-to-digital sub-converter configured to convert the input voltage into the (2 B −1)-bit digital code and the B-bit digital code, wherein the multiplying digital-to-analog converter comprises: a first sampler configured to sample the input voltage in response to a first clock signal; a digital-to-analog converter configured to convert the (2 B −1)-bit digital code into the analog signal in response to a second clock signal; a subtracter configured to subtract an output value of the digital-to-analog converter from an output of the first sampler; and a residual voltage amplifier configured to output the residual voltage by amplifying an output value of the subtracter in response to the second clock signal.