Patent ID: 7208986

Claim:
A method for synchronizing an output clock signal to an input clock signal, said method comprising: providing a first delay array comprising a plurality of serially-coupled delay units configured to receive and delay said input clock signal and to output said output clock signal, said plurality of delay units comprising a first one or more delay units and a second one or more delay units; synchronizing said output clock signal to said input clock signal by: receiving and delaying by a second delay array a signal that corresponds to said input clock signal; sampling outputs of said second delay array in response to a signal transition of said input clock signal; and selecting, based on said sampling, one of said plurality of delay units from said first delay array to either provide said output clock signal or to receive said input clock signal as input, wherein only said first one or more delay units of said plurality of delay units can be selected based on said sampling; and maintaining said output clock signal synchronized to said input clock signal by: measuring a phase difference between said input clock signal and said output clock signal; and selecting, based on said measuring, one of said plurality of delay units from said first delay array to either provide said output clock signal or to receive said input clock signal as input, wherein both said first one or more delay units and said second one or more delay units of said plurality of delay units can be selected based on said measuring.