Patent ID: 7738282

Claim:
A dual port static random access memory (SRAM) cell comprising: a first pull-up transistor having a first source and a first drain; a second pull-up transistor having a second source and a second drain; a first pull-down transistor comprising: a first drain end connected to the first drain of the first pull-up transistor; and a first gate end connected to a gate of the first pull-up transistor; a second pull-down transistor comprising: a second drain end connected to the second drain of the second pull-up transistor; and a second gate end connected to a gate of the second pull-up transistor; wherein the first pull-down transistor comprises: a first sub-transistor; and a second sub-transistor, wherein a drain of the first sub-transistor is connected to a drain of the second sub-transistor to form the first drain end, a source of the first sub-transistor is electrically connected to a source of the second sub-transistor by an additional active region to form a first source end, and a gate of the first sub-transistor is connected to a gate of the second sub-transistor to form the first gate end; and wherein the second pull-down transistor comprises: a third sub-transistor; and a fourth sub-transistor, wherein a drain of the third sub-transistor is connected to a drain of the fourth sub-transistor to form the second drain end, a source of the third sub-transistor is connected to a source of the fourth sub-transistor to form a second source end, and a gate of the third sub-transistor is connected to a gate of the fourth sub-transistor to form the second gate end.