Patent ID: 8102695

Claim:
A semiconductor device, comprising: first and second bit line select switch arrays each having a plurality of bit line select switches; and a sub-memory cell array adjacently disposed between the first and second bit line select line switch arrays and having a plurality of local bit lines, a plurality of word lines, and a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of local bit lines, wherein the local bit lines are connected to a global bit line through the first and second bit line select switch arrays, and current is caused to flow through the first and second bit line select switch arrays in the same direction at the time of writing, and wherein each said memory cell comprises a select element and a resistance change element, wherein one terminal of the select element is connected to a plate electrode shared by other memory cells and the other terminal thereof is connected to the resistance change element, and wherein a potential of the plate electrode is set to a potential between a ground voltage and a memory cell writing voltage.