Patent ID: 8028103

Claim:
A direct memory access (DMA) controller comprising: a transmit control circuit configured to read first DMA data from an address space in a host for a first DMA transfer, wherein the first DMA transfer includes at least a first operation to be performed on the first DMA data to produce a result; an offload engine coupled to receive the first DMA data and an associated DMA descriptor from the transmit control circuit, wherein the offload engine includes a security unit that includes a cipher circuit that is cross-coupled to a hash circuit, wherein the security unit is configured to selectably perform a cipher function on the first DMA data followed by a hash function to produce the result dependent upon control information included within the associated DMA descriptor; and a receive control circuit coupled to the offload engine to receive the result, wherein the receive control circuit is configured to write the result to a target location in the address space of the host, wherein the target location is specified for the first DMA transfer.