Patent ID: 8536917

Claim:
A duty cycle adjustment circuit, comprising: a differential control voltage generation circuit, comprising: first and second delta voltage generators; a variable current source configured to supply an input current, via a first p-type field effect transistor (pFET) and a first n-type FET (nFET), to the first and second delta voltage generators, wherein the first delta voltage generator outputs a positive delta voltage based on the input current, and the second delta voltage generator outputs a negative delta voltage based on the input current; and a control voltage inverter that is biased at a trip voltage of the control voltage inverter, and that is configured to output the trip voltage, and wherein the differential control voltage generator outputs a first control voltage equal to the trip voltage plus the delta voltage to a first inverter, and a second control voltage equal to the trip voltage minus the delta voltage to a second inverter; the first inverter, the first inverter having a trip voltage that is about the same as the trip voltage of the control voltage inverter, configured to receive a first inverter input signal comprising a sum of a first input clock signal received at a first clock signal input node and the first control voltage received from the differential control voltage generation circuit, and to output a first output clock signal, wherein variation of the input current by the variable current source is configured to vary a duty cycle of the first output clock signal; and the second inverter, the second inverter having a trip voltage that is about the same as the trip voltage of the control voltage inverter, configured to receive a second inverter input signal comprising a sum of a second input clock signal received at a second clock signal input node and the second control voltage received from the differential control voltage generation circuit, and to output a second output clock signal, wherein variation of the input current by the variable current source is configured to vary a duty cycle of the second output clock signal.