Patent ID: 7927989

Claim:
A method of forming a transistor comprising: providing a semiconductor substrate; forming a gate stack comprising a gate electrode, the gate electrode overlying a gate dielectric formed in direct contact with a predetermined portion of the semiconductor substrate, the gate electrode having a width; forming a relatively thin sidewall spacer dielectric layer along sidewalls of the gate dielectric and the gate electrode, wherein the relatively thin sidewall spacer dielectric layer has a thickness of about a tenth of the width of the gate electrode; forming recesses in the semiconductor substrate using an anisotropic etch using the relatively thin sidewall dielectric as a mask to leave a semiconductor pillar under the gate stack, whereby the semiconductor pillar has sidewalls vertically aligned to the relatively thin sidewall dielectric layer; implanting a species comprising one of a group consisting of carbon and nitrogen to form a boron barrier region on exposed portions of the semiconductor substrate and on sidewalls of the semiconductor pillar; after implanting the species, growing source and drain regions in the recesses that are in situ doped with boron; after growing the source and drain regions, forming relatively thick sidewall spacers adjacent to the thin sidewall spacer dielectric; implanting boron into portions of the source drain regions using the relatively thick sidewall spacers as a mask; and forming electrical contacts to the gate and the source and drain regions of the transistor.