Patent ID: 8728885

Claim:
A method of forming a FinFET device comprising a channel region and a plurality of source/drain regions, the method comprising: forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, said trenches defining a fin structure for said device comprised of first and second layers of semiconducting material, wherein said first layer of semiconducting material is selectively etchable relative to said semiconducting substrate and said second layer of semiconducting material, said fin structure extending in a gate-length direction across what will become said channel region and said source/drain regions for said device; forming a sacrificial gate structure above a portion of said fin structure corresponding to said channel region for said FinFET device, said sacrificial gate structure being comprised of a sacrificial gate insulation layer and a sacrificial gate electrode; forming at least one sidewall spacer adjacent said sacrificial gate structure; performing at least one etching process to remove said sacrificial gate structure and thereby define a gate cavity; while masking portions of said fin structure positioned outside of said at least one spacer, performing at least one selective etching process to selectively remove said first layer of semiconducting material relative to said second layer of semiconducting material within said gate cavity and thereby define a space between said second semiconducting material and said semiconducting substrate within said channel region of said device; and forming a final gate structure in said gate cavity.