Patent ID: 7502928

Claim:
An apparatus, comprising: a local memory; a bus operable to carry information to and from the local memory; one or more arithmetic processing units operable to process data and operatively coupled to the local memory; and a security circuit including a secret data area that is not accessible by devices outside the security circuit, the secret data area containing a first key and a second key, and the security circuit includes an accessible data area that is accessible by devices outside the security circuit, the security circuit being operable to: place the apparatus into any of a plurality of operational modes, wherein the plurality of operational modes includes at least: (i) a first mode whereby the apparatus and an external device are operable to initiate a transfer of information into or out of the local memory over the bus, (ii) a second mode whereby neither the apparatus nor the external device are operable to initiate a transfer of information into or out of the memory over the bus, and (iii) a third mode whereby the apparatus is operable to initiate a transfer of information into or out of the local memory over the bus, but the external device is not operable to initiate a transfer of information into or out of the local memory over the bus; and place a copy of the first key in the accessible data area when the apparatus is in the second mode.