Patent ID: 6931029

Claim:
Apparatus for synchronizing a clock with data received via an asynchronous transmission medium, comprising: a plurality of buffers connected to said asynchronous transmission medium; circuitry configured for reading out data from said buffers at a clock rate specified by said clock; a regulating circuit configured to regulate said clock rate according to transmission rate of said data; wherein said data received from said transmission medium is organized into packets; associated with each packet is a sequence field identifying transmission order of packets; said plurality of buffers comprises circularly arranged buffers, each allocated to a sequential one of said packets according to said sequence field, whereby packets are stored in order of transmission regardless of order of reception; associated with said buffers is a discrimination circuit configured to determine according to said sequence field whether a packet has been received by such time as its corresponding buffer is to be read out; and a packet received after readout of its corresponding buffer commences is discarded, whereby loss of a packet in transmission does not affect timing relationships among other packets.