Patent ID: 7095669

Claim:
A method for utilizing memory cells in a semiconductor memory device having a weak retention time, comprising: refreshing a first set of one or more rows of memory cells at a first frequency by generating a set of regular refresh request signals, wherein at least one of the rows of the first or second sets of rows is refreshed with each regular refresh request signal; and refreshing a second set of one or more rows of memory cells at a second frequency greater than the first frequency by generating a set of supplemental refresh request signals, wherein at least one of the rows of the second set of rows are refreshed with each supplemental refresh request signal; wherein a supplemental refresh request signal, of the set of supplemental refresh request signals, is generated to refresh a given row of the second set of rows in conjunction with a regular refresh signal, of the set of regular refresh request signals, generated to refresh a row having a harmonious address, harmonious addresses being row addresses occurring periodically after the address of the given row and having a defined periodic spacing therebetween.