Patent ID: 7071510

Claim:
A capacitor of an integrated circuit device comprising: a first insulation layer formed on a semiconductor substrate, the first insulation layer having a buried contact hole formed therein; a buried contact plug filling a portion of the buried contact hole to a predetermined height; a diffusion barrier spacer formed on the buried contact plug and on an inner side surface of an upper portion of the buried contact hole above the buried contact plug; a second insulation layer formed on the first insulation layer, the second insulation layer having a through hole with a diameter that is larger than that of the buried contact hole, wherein the diffusion barrier spacer and a top surface portion of the contact plug are exposed through the through hole; a barrier layer formed on a bottom portion and a side surface of the through hole; a lower electrode formed on the barrier layer; a dielectric layer formed on the lower electrode and an upper surface of the second insulation layer; and an upper electrode formed on the dielectric layer.