Patent ID: 6989590

Claim:
A power semiconductor device comprising: at least one insulating substrate; at least one power semiconductor element mounted on a metal pattern formed on a main surface of the insulating substrate; and a control circuit board configured to have a first surface facing toward said main surface of the insulating substrate with the power semiconductor element interposed between the main surface and the first surface, wherein at least one electronic component for control is mounted on a metal pattern formed on a second surface of the control circuit board facing away from the main surface of the insulating substrate and extending in parallel to said first surface, and at least one through hole with a hollow region is provided vertically to said first and second surfaces and said through hole with the hollow region is configured to electrically connect circuit patterns laminated between the first surface and the second surface, said at least one through hole with the hollow region being filled with a filler not required to electrically connect said circuit patterns.