Patent ID: 7294870

Claim:
A semiconductor chip comprising: a silicon substrate; multiple semiconductor devices in or on said silicon substrate; an interconnecting metallization structure over said silicon substrate, said interconnecting metallization structure comprising multiple lower metal layers; a dielectric layer between said multiple lower metal layers: a passivation layer over said interconnecting metallization structure and over said dielectric layer, wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip and a topmost nitride layer of said semiconductor chip, wherein said topmost nitride layer is over said topmost oxide layer; a polymer layer over said passivation layer, said polymer layer having a thickness greater than that of said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers and greater than that of said dielectric layer, and wherein said interconnecting metallization structure comprises multiple contact points exposed by multiple first openings in said passivation layer and by multiple second openings in said polymer layer, wherein said multiple first openings are aligned with said multiple second openings, wherein said multiple contact points are separate from one another; and an upper metallization structure over said polymer layer and over said multiple contact points, wherein a connecting portion of said upper metallization structure connects at least one portion of said interconnecting metallization structure with at least one other portion of said interconnecting metallization structure through said multiple first and second openings, and wherein said connecting portion comprises electroplated copper and has a thickness greater than those of said multiple lower metal layers.