Patent ID: 8736537

Claim:
A shift register comprising at least two shift register units, one of which comprising: a boosting signal TFT for receiving a first clock signal, and outputting a high voltage signal to an output terminal in a conductive state thereof; a first boosting drive TFT for receiving a frame start signal or an output signal of another shift register unit so as to turn on the boosting signal TFT; a second boosting drive TFT for receiving a reset signal or an output signal of an other shift register so as to turn on the boosting signal TFT; a plurality of lowering signal TFTs including a first lowering signal TFT, a second lowering signal TFT, a third lowering signal TFT, a fourth lowering signal TFT, and a fifth lowering signal TFT. the first lowering signal TFT for receiving the reset signal or the output signal of the other shift register, and outputting a low voltage signal to the output terminal in conductive state thereof; a first lowering drive TFT for receiving a second clock signal so as to turn on the second lowering signal TFT and the third lowering signal TFT; a second lowering drive TFT for receiving a third clock signal so as to turn on the fourth lowering signal TFT and the fifth lowering signal TFT; the second lowering signal TFT for receiving the output signal of the first lowering drive TFT, and lowering the output signal of the output terminal in conductive state thereof; the third lowering signal TFT for receiving the output signal of the first lowering drive TFT, and in conductive state thereof lowering the output signal of the output terminal; a first off-drive TFT for receiving the output signal of the first boosting drive TFT, and in conductive state thereof turning off the second lowering signal TFT and the third lowering signal TFT; the fourth lowering signal TFT for receiving the output signal of the second lowering drive TFT, and in conductive state thereof lowering the output signal of the output terminal; the fifth lowering signal TFT for receiving the output signal of the second lowering drive TFT, and in conductive state thereof lowering the output signal of the output terminal; and a second off-drive TFT for receiving the output signal of the first boosting drive TFT, and in conductive state thereof turning off the fourth lowering signal TFT and the fifth lowering signal TFT, and in the other shift register unit adjacent to said shift register unit, a boosting signal TFT, a first lowering drive TFT and a second lowering drive TFT receiving a fourth clock signal, a fifth clock signal and a sixth clock signal respectively.