Patent ID: 7111152

Claim:
A method of executing instructions in a computer system which method comprises supplying simultaneously a group of instructions each machine cycle for execution in parallel execution pipelines, decoding each instruction in the group, checking the instructions in the group to determine if any horizontal data dependencies exist between any pair of instructions in the group to be executed in a respective pair of parallel execution pipelines, and in response to determination of such a data dependency selecting a dependency control signal of either a first type if a temporary stall is required in one of the execution pipelines, and of a second type if the data dependency can be resolved by activating a bypass, said method further including generating a plurality of parallel microinstructions from the instructions, said microinstructions including an indication of the selected dependency control signal of the first or second type, supplying the microinstructions to the pair of parallel execution pipelines, and executing the microinstructions in the parallel execution pipelines including effecting a stall or a bypass depending on whether the selected dependency control signal is of the first or second type, wherein said execution pipelines include accesses to a data memory, said execution pipelines including a first set of execution pipelines which execute microinstructions needed for memory access operations and a second set of execution pipelines which carry out arithmetic operations, such that memory access operations and arithmetic operations are carried out in different execution pipelines; the method further comprising selecting an instruction grouping mode from either a superscalar mode with a first predetermined number of instructions in the same group or a very long instruction word (VLIW) mode having a second larger number of instructions in the same group, providing a grouping control signal to indicate which grouping mode is selected and using said grouping control signal to disable a dependency control signal of said first type.