Patent ID: 8171359

Claim:
An integrated circuit comprising: A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; B. a first test access port circuit including a state machine connected to the test clock lead and the test mode select lead, and a register connected to the state machine, to the test data in lead and that is coupled to the test data out lead, the first test access port circuit including a selection lead connected to the register; C. a boundary scan register connected to the state machine of the first test access port circuit, to the test data in lead and coupled to the test data out lead; D. functional circuitry; E. a second test access port circuit connected to the functional circuitry, the second test access port circuit including a state machine connected to the test clock lead and the test mode select lead, and a register connected to the state machine and the test data in lead and that is coupled to the test data out lead, the second test access port circuit including a selection lead connected to the register; and F. linking module circuitry including a state machine connected to the test clock lead and the test mode select lead, and a register connected to the test data in lead and coupled to the test data out lead, the linking module circuitry including selection leads coupled to the state machine and connected to the selection leads of the first test access port circuit and the second test access port circuit.