Patent ID: 7589991

Claim:
A semiconductor memory device which includes a latch circuit for storing complementary data at first and second storage nodes, wherein the latch circuit comprises: a first load transistor having a drain connected to the first storage node, a source to which a power supply voltage is supplied and a gate connected to the second storage node; a second load transistor having a drain connected to the second storage node, a source to which the power supply voltage is supplied and a gate connected to the first storage node; a first drive transistor having a drain connected to the first storage node and a gate connected to the second storage node; a second drive transistor having a drain connected to the second storage node and a gate connected to the first storage node; and a storage node voltage control circuit which has a function of connecting one of the first and the second storage nodes, which holds a low logic level, and a third node, which holds a high logic level.