Patent ID: 8468403

Claim:
Test circuitry, comprising: A. a test data input lead and a test data output lead; B. a first bus that includes a test clock lead and a test mode select lead; C. a second bus that includes a capture lead and a shift lead; D. a controller that has inputs coupled to the first bus and that has an instruction register control bus output and a data register control bus output; E. plural circuit blocks, each circuit block being a separate test domain, the circuit blocks being serially coupled together between the test data input lead and the test data output lead, each circuit block including: i. instruction register circuitry having a test data input coupled to the test data input lead, control inputs connected to the instruction register control bus, and control outputs; ii. first gating circuitry having a first input coupled to the data register control bus output, a second input connected to a control output of the instruction register circuitry, third inputs connected to the second bus, and having a first gated data register control output bus; iii. second gating circuitry having first inputs coupled to the data register control bus output, second inputs coupled to the first gated data register control output bus, a control input connected to a control output of the instruction register, and second gated data register control bus outputs; and iv. data register circuitry having first inputs coupled to the second gated data register control bus outputs, a test data input coupled to the test data input lead, and a test data output coupled to the test data output lead.