Patent ID: 8117485

Claim:
A memory system comprising: first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data; a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips; and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal.