Patent ID: 6967851

Claim:
An apparatus for reducing the power consumption of a PFC-PWM power converter comprising: a control terminal for detecting a line-input voltage, wherein a voltage at said control terminal is used to control a PFC signal, wherein said PFC signal is utilized to drive switching devices of a PFC boost converter of said PFC-PWM power converter; a first resistor having a first terminal supplied with said line-input voltage; a second resistor having a second terminal connected to a ground reference, wherein a first terminal of said second resistor and a second terminal of said first resistor are connected to said control terminal; a PFC power-manager of a PFC controller, having a PFC-control terminal connected to said control terminal; wherein said PFC power-manager determines a PFC-reference voltage for an error amplifier of said PFC controller in response to the voltage at said control terminal; wherein said PFC power-manager disables said PFC signal during an inhibit mode; wherein said inhibit mode is enabled when a low-voltage condition sustains longer than an inhibit-delay time; wherein said low-voltage condition means a voltage at said PFC-control terminal is lower than a low-voltage threshold voltage; and a PWM power-manager of a PWM controller, having a PWM-control terminal connected to said control terminal; wherein said PWM power-manager will pull the voltage at said control terminal low under a standby mode; wherein said standby mode is enabled when a low-load condition sustains longer than a standby-delay time; wherein said low-load condition means that a feedback voltage of said PWM controller is lower than a low-load threshold voltage; wherein said feedback voltage of said PWM controller decreases whenever a load of said PFC-PWM power converter decreases.