Patent ID: 7333527

Claim:
A circuit for reducing electromagnetic interference generated by a clock signal inside an electronic device, comprising: a signal generator for generating the clock signal; a delay generator for generating a delayed version of the clock signal using phase modulation, the delay generator comprising: a first delay line and a second delay line each receiving the clock signal, wherein the first delay line and the second delay line each produce a range of delays with a minimum value and maximum value, the total range of the first and second delay lines equal to at least one period of the clock signal; a delay multiplexer including a first input coupled with the first delay line and a second input coupled with the second delay line; and a delay controller coupled with the delay multiplexer and configured to select either one of the first and second delay lines to drive the output of the delay multiplexer in accordance with a control signal, the output comprising the delayed version of the clock signal; wherein the control signal controls the delay controller to produce an overall delay of the clock signal varying with time in such a manner as to cause spreading of the spectrum of the delayed version of the clock signal; and logic circuitry located within the electronic device and configured to receive the delayed clock signal.