Patent ID: 8842824

Claim:
An encryption processing circuit that encrypts plain text in a plurality of steps by using a cryptographic key, the circuit comprising: N (N is an integer equal to 2 or greater) sets, each of which including an encryption block and a register, wherein: the encryption block of an i-th (i=1 to N−1) set performs encryption in a certain step on plain text stored in the register of the i-th set or intermediate data stored in the register of the i-th set obtained from the plain text and intermediate data obtained by the encryption is stored in the register of an (i+1)-th set, and the encryption block of an N-th set performs the encryption in a certain step on plain text stored in the register of the N-th set or intermediate data stored in the register of the N-th set obtained from the plain text and intermediate data obtained by the encryption is stored in the register of a first set, wherein: the encryption on a plurality of pieces of plain text is performed simultaneously by the encryption processing circuit in at least a portion of time, and when the encryption in the certain step on certain plain text stored in the register of a certain set or intermediate data stored in the register of the certain set obtained from the certain plain text is performed in the encryption block of the certain set at a certain clock, the encryption in another step on other plain text stored in the register of the certain set or intermediate data stored in the register of the certain set obtained from the other plain text is performed in the encryption block of the certain set at the next clock of the certain clock, further comprising: a timing adjustment unit that adjusts a start time of the encryption of the other plain text so as to be shifted by a predetermined number of clocks at least with respect to the start time of the encryption of the certain plain text, wherein when the encryption in the certain step on the certain plain text stored in the register of the certain set or intermediate data stored in the register of the certain set obtained from the certain plain text is performed in the encryption block of the certain set at the certain clock by adjustments of the timing adjustment unit, the encryption in the other step on the other plain text stored in the register of the certain set or intermediate data stored in the register of the certain set obtained from the other plain text is performed in the encryption block of the certain set at the next clock of the certain clock.