Patent ID: 8762654

Claim:
A method, comprising: determining an arithmetic modulo result associated with an address of a page request and at least one other page request on a per page request basis, wherein the arithmetic modulo result is based, at least in part, on a modulus; determining, by a hardware controller, an access speed for the page request to a memory device with memory cells that are multiple level cells that have a same bit density, wherein the access speed is a number of clock cycles used to access a memory page associated with the page request in the memory device, wherein the page request is a request to access the memory page mapped to the memory device, wherein the page request and the at least one other page request are requesting to access a sequential string of memory pages and are requesting to access single pages on a per page request basis, wherein the modulus is based, at least in part, on access speeds of the sequential string of memory pages, and wherein the multiple level cells include a first set of memory pages that are accessed according to a first access speed and a second set of memory pages that are accessed according to a second access speed that is different from the first access speed; and scheduling the page request based, at least in part, on the access speed, wherein scheduling the page request includes assigning the page request to be serviced in parallel with the at least one other page request that is to access a different memory page in the memory device in a same number of clock cycles, wherein scheduling the page request includes aligning the page request and the at least one other page request, and controlling the page request and the at least one other page request to be executed in parallel, and wherein scheduling the page request and the at least one other page request is based, at least in part, on the arithmetic modulo result.