Patent ID: 8260981

Claim:
A direct memory access controller comprising: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, the controller includes means for synchronising execution of firmwares for at least two buffer memories as a function of a predetermined order of data originating from the at least two buffer memories required in an interlaced data sequence formed from the data originating from the at least two buffer memories to be transferred to the addressee, and wherein the means for synchronizing includes means for transmitting at least one read and update right from one firmware to another firmware, wherein holding a read and update right by one firmware currently being executed enables the one firmware to execute at least one data read in the buffer memory with which it is associated and at least one update of the corresponding read pointer.