Patent ID: 8786102

Claim:
A device comprising: a first semiconductor chip including a first surface, a second surface opposite to the first surface, and side surfaces joined to the first and second surfaces to define edges thereof; a plurality of first electrodes formed on the first surface of the first semiconductor chip; a plurality of second electrodes formed on the second surface of the first semiconductor chip, the second electrodes being electrically coupled to the first electrodes, respectively: a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions; a first insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first sealing resin so as to expose the second electrodes from the first insulating layer; a plurality of land electrodes formed over the first insulating layer apart from the first semiconductor chip, each of the land electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin; a plurality of rewiring layers each connected to an associated one of the second electrodes and elongated over the first insulating layer to reach a corresponding one of the land electrodes; and a second insulating layer formed on the first insulating layer and the rewiring layers so that the land electrodes expose from the second insulating layer, wherein the first semiconductor chi includes a plurality of through electrodes therein, and the first electrodes are electrically coupled to the second electrodes via the through electrodes, respectively.