Patent ID: 8559260

Claim:
A semiconductor memory device, comprising: a charge pump circuit configured to generate a pass pump voltage in response to a clock signal and a pump enable signal; and a regulator circuit configured to regulate the pass pump voltage to output a program pass voltage during a program operation and discharge the program pass voltage to output a verification pass voltage during a verification operation; wherein the regulator circuit detects the program pass voltage in a period during which the program operation switches to the verification operation and controls a period in which the program pass voltage is discharged, and wherein the regulator circuit comprises: a regulator configured to receive the pass pump voltage and a bandgap voltage and generate the program pass voltage; a discharge circuit configured to discharge the program pass voltage to a predetermined voltage level by comparing the bandgap voltage and a feedback voltage, generated by the regulator; and a control circuit configured to generate a control signal for enabling the discharge circuit in response to a regulator discharge control signal, generated by the discharge circuit and a regulator discharge signal activated for a predetermined time during the period in which the program operation switches to the verification operation.