Patent ID: 8607002

Claim:
A memory system comprising: a first memory vault comprising a first stacked plurality of memory arrays, each memory array in the first stacked plurality of memory arrays located on one of a plurality of stacked memory dies; a second memory vault comprising a second stacked plurality of memory arrays, each memory array in the second stacked plurality of memory arrays located on one of the plurality of stacked memory dies, the plurality of stacked memory dies including a first memory die and a second memory die, the first stacked plurality of memory arrays including a first memory array and a second memory array, the first memory array located on the first memory die, the second memory array located on the second memory die, the second stacked plurality of memory arrays including a third memory array and a fourth memory array, the third memory array located on the first memory die, and the fourth memory array located on the second memory die; a memory vault controller communicatively coupled to the first memory vault to provide at least one of control, switching, or communication logic associated with the first memory vault; and a prefetch controller to perform prefetch operations associated with the first memory vault.