Patent ID: 8917806

Claim:
A phase/frequency detector (PFD) module, applicable to a digital phase-locked loop (PLL), said PFD module comprising: a counting clock input terminal for receiving a counting clock signal; a reference clock input terminal for receiving a reference clock signal; a counting control terminal for receiving a count value; a phase error output terminal for outputting a phase error signal; a frequency error output terminal for outputting a frequency error signal; an edge detector provided with a detecting input terminal, a detecting clock terminal, and a detecting output terminal, said detecting input terminal being coupled to said reference clock input terminal and receiving said reference clock signal, said detecting clock terminal being coupled to said counting clock input terminal and receiving said counting clock signal, wherein when either a first edge or a second edge of said counting clock signal occurs, said edge detector detects whether or not a first edge of the signal at said reference clock input terminal has occurred, and if the first edge of said reference clock input terminal is detected, said detecting output terminal outputs an edge-detected signal, else said detecting output terminal outputs an edge-not-detected signal; a counter coupled to said detecting output terminal, said counting clock input terminal, and said counting control terminal, being provided with a counting output terminal coupled to said frequency error output terminal, wherein if said detecting output terminal outputs said edge-detected signal, then said counter outputs a counting result as said frequency error signal at said counting output terminal, resets, and loads said count value, and wherein if said detecting output terminal outputs said edge-not-detected signal, then the counter continues to count on the first edge or the second edge of said counting clock signal; and a frequency phase converter coupled to said counting output terminal for receiving said counting result, being provided with a converting output terminal coupled to said phase error output terminal, wherein said frequency phase converter performs integration over said counting result and outputs the integral formed as said phase error signal to said converting output terminal.