Patent ID: 7656182

Claim:
A testing method for chips, said method comprising: testing all chips from a lot after manufacture, wherein each chip comprises a parametric performance monitoring system on said chip, wherein said parametric performance monitoring system comprises at least one on-chip parametric measurement macro comprising a plurality of individually selectable test circuits to perform different types of tests, wherein each of said individually selectable test circuits comprises a device under test, wherein at least two devices under test comprise different types of devices under test, and wherein, for each chip, said testing comprises taking, by said parametric performance monitoring system on said chip, parametric measurements from said at least one on-chip parametric measurement macro, said parametric measurements comprising actual measured values for at least one parameter for each device under test and said at least one parameter comprising one of on current (Ion) and threshold voltage (Vt); determining yield loss based on results of said testing of said all of said chips; and correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements.