Patent ID: 8120981

Claim:
A semiconductor integrated circuit device comprising: a first functional block including a first fuse element, a first switching circuit configured to write data to the first fuse element when turned on, a first holding portion capable of holding a first write instruction transferred synchronously with a clock, and a first instruction portion configured to turn on the first switching circuit when a second write instruction is given thereto with the first write instruction held in the first holding portion; a second functional block including a second fuse element, a second switching circuit configured to write data to the second fuse element when turned on, a second holding portion capable of holding the first write instruction transferred from the first holding portion in synchronism with the clock, and a second instruction portion configured to turn on the second switching circuit when the second write instruction is given thereto with the first write instruction held in the second holding portion; and a control section which issues the second write instruction at a point in time when the first write instruction is held in the first and second holding portions as the data are written to the first and second fuse elements, wherein the first and second switching circuits each include a MOS transistor, one end of a current path of which is connected to the first or second fuse element and the other end of which is grounded, the first and second instruction portions individually include arithmetic circuits which compute the first and second write instructions and each apply a voltage higher than a threshold value of each said MOS transistor to a gate of the MOS transistor based on a result of the computation, and the first and second holding portions each include a flip-flop which holds the first write instruction.