Patent ID: 8481431

Claim:
A method for opening a one-side contact region of a vertical transistor, the method comprising: forming a first liner layer on both side walls of each pillar-shaped active region of a substrate which is spaced apart by a trench; forming a second liner layer over a portion of the surface of the first liner layer; forming a first sacrificial layer at a lower portion of the trench so that a portion of the first liner layer is exposed; forming a third liner layer over the exposed portion of the first liner layer and the second liner layer; filling the inside of the trench over the third liner layer and the first sacrificial layer with a second sacrificial layer; forming a polysilicon layer on a resulting structure in which the second sacrificial layer is formed; selectively doping impurities into the polysilicon layer by performing a plasma doping process and a tilt ion implantation process on the polysilicon layer; selectively exposing the third liner layer formed on one of the both sides of the active region, at which a one-side contact is to be formed, by selectively removing an undoped portion of the polysilicon layer; exposing the first liner layer formed on the side, at which the one-side contact is to be formed, by removing the exposed portion of the third liner layer; and exposing a surface of a contact region, in which the one-side contact is to be formed, by removing the exposed portion of the first liner layer.