Patent ID: 7679948

Claim:
A memory circuit, comprising: (a) a memory array defined by SRAM cells, the memory array having rows and columns, and wordlines for accessing selected rows through a passgate and bitlines for accessing selected columns; (b) a cell voltage level switch connected to a low power supply and a high power supply, the cell voltage level switch having, (i) a write operation state defined to selectively provide the low power supply to SRAM cells in columns in which a write operation is to occur, and provide the high power supply to SRAM cells in columns in which the write operation is not identified to occur; (ii) a read operation state defined to selectively provide the high power supply to SRAM cells in columns in which a read operation is to occur, and provide the high power supply to SRAM cells in columns in which the read operation is not identified to occur; (c) a recycle charge storage; (d) a precharge switch connected to the low power supply and to the bitlines of the memory array, the precharge switch being coupled to the cell voltage level switch through the recycle charge storage; (e) a column decoder for identifying columns selected for the read or write operation state; and (f) a write enable switch connected to the cell voltage level switch, the precharge switch, and the column decoder.