Patent ID: 7323727

Claim:
A semiconductor memory device comprising: a memory array portion including bit lines extending in a column direction, word lines extending in a row direction, and memory cells arranged in said row and column directions; a first peripheral circuit portion arranged adjacent to said memory array portion in said row direction; a second peripheral circuit portion, having a plurality of MOSFETs, arranged adjacent to said first peripheral circuit portion in said column direction; an external terminal supplied with a predetermined voltage from outside of said semiconductor memory device; a first voltage supply line formed over said bit lines and word lines and extending in said column direction; a second voltage supply line formed over said bit lines and word lines and extending in said row direction and into said first peripheral circuit portion, and a third voltage supply line formed in said first peripheral circuit portion and extending in said column direction and into said second peripheral circuit portion, wherein said first and second voltage supply lines are connected to each other at the intersection of said first and second voltage supply lines, each contact between said first and second voltage supply line being located immediately above said memory array portion, wherein said second and third voltage supply lines are connected to each other at the intersection of said second and third voltage supply lines wherein said first voltage supply line is connected to said external terminal, and wherein said predetermined voltage is supplied to said MOSFETs in said second peripheral circuit portion from said external terminal via said first, second and third voltage supply lines.