Patent ID: 7271058

Claim:
A memory cell array which is at least partially formed in a semiconductor substrate having a surface, the memory cell array comprising: a plurality of transistors, each comprising a first source/drain and a second source/drain region, a channel connecting the first and the second source/drain region, and a gate electrode which is adapted to control a conductivity of the channel, and a plurality of storage capacitors, each comprising: a storage electrode comprising a first and a second sections, the storage electrode being at least partially formed above the semiconductor substrate surface; a first counter electrode having a first portion adjacent to the first section of the storage electrode, the first portion extending in a first direction, and a second portion extending in at least one direction which is different from the first direction, wherein the second portion of the first counter electrode does not extend along the storage electrode; a first dielectric layer being disposed between the first portion of the first counter electrode and the storage electrode; a second counter electrode having a first portion adjacent to a second section of the storage electrode, the first portion extending in a second direction, and a second portion extending in at least one direction which is different from the second direction, wherein the second portion of the second counter electrode does not extend along the storage electrode; a second dielectric layer being disposed between the first portion of the second counter electrode and the storage electrode; and backside electrode contacts electrically connecting the first and the second counter electrodes, wherein the storage electrode is electrically connected with one of the first and second source/drain regions.