Patent ID: 8350841

Claim:
An ESD protection circuit, comprising: a first transistor having a first gate terminal, a first source/drain terminal and a second source/drain terminal, the first source/drain terminal being electrically coupled to a first power line, and the second source/drain terminal being electrically coupled to a second power line; a second transistor having a second gate terminal, a third source/drain terminal and a fourth source/drain terminal, the third source/drain terminal being electrically coupled to the first power line, and the fourth source/drain terminal being electrically coupled to the first gate terminal; a third transistor having a third gate terminal, a fifth source/drain terminal and a sixth source/drain terminal, the fifth source/drain terminal being electrically coupled to the fourth source/drain terminal and the first gate terminal, and the sixth source/drain terminal being electrically coupled to the second power line; a first voltage divider comprising a first impedance and a second impedance electrically coupled in series between the first power line and the second power line for supplying a first voltage to the second gate terminal according to a potential difference between the first power line and the second power line; and a second voltage divider comprising a third impedance and a fourth impedance electrically coupled in series between the first power line and the second power line for supplying a second voltage to the third gate terminal according to the potential difference between the first power line and the second power line; wherein one of a ratio of an impedance value of the first impedance to that of the second impedance and a ratio of an impedance value of the third impedance to that of the fourth impedance is more than 1, and the other of the ratio of the impedance value of the first impedance to that of the second impedance and the ratio of the impedance value of the third impedance to that of the fourth impedance is less than 1.