Patent ID: 7263642

Claim:
A parallel-testable multi-block chip comprising: a test clock that is pulsed during a test mode; an operating clock that is pulsed during the operating mode; a test-data input that receives a stream of test input data during the test mode, the test input data being synchronized to the test clock; an expected data line that carries expected test data synchronized to the test clock; a plurality of functional blocks that are capable of performing functions in parallel at a same time in response to the operating clock, the plurality of functional blocks being testably identical; each functional block in the plurality of functional blocks comprising: functional logic to perform functions in response to the operating clock; scan flip-flops that form a first scan chain that links an output of a prior scan flip-flop to a test input of a next scan flip-flop for all scan flip-flops except for a first scan flip-flop and a final scan flip-flop in the first scan chain, wherein each scan flip-flop also has a data input driven by the functional logic, wherein the data input is clocked to the output of a scan flip-flop when the operating clock is pulsed, while the test input is clocked to the output of the scan flip-flop when the test clock is pulsed; wherein outputs of the scan flip-flops are also inputs to the functional logic; wherein the first scan flip-flop in the first scan chain has a test input that receives the stream of test input data that is shifted through the first scan chain in response to pulsing of the test clock during the test mode; a comparator having an input that receives the output of the final scan flip-flop in the first scan chain and compares the output to expected test data from the expected data line and signals a fault when a mismatch occurs; and a test-capture register that is triggered to indicate a fault in the functional block in response to the comparator signaling the fault; wherein a plurality of test capture registers for the plurality of functional blocks is readable to determine which of the plurality of functional blocks is a failing functional block having the fault; wherein the expected test data matches outputs from the first scan chain in each of the plurality of functional blocks when no defects occur, wherein the plurality of functional blocks are tested with a same expected test data and are testably identical, whereby the plurality of functional blocks are tested in parallel using the expected test data that is compared in parallel to outputs of the first scan chains in each of the plurality of functional blocks.