Patent ID: 7787581

Claim:
A phase-locked loop circuit, comprising: a phase detector configured to receive an input reference signal, and a feedback signal, and detect a phase difference therebetween, and output a phase error signal based on the detected phase difference; a loop filter section configured to filter the phase error signal; a voltage controlled oscillator configured to generate an output signal as a function of the filtered phase error signal, and provide the feedback signal associated therewith via a divider circuit, wherein the loop filter section comprises a digital loop filter section comprising digital filtering means to filter the phase error signal, and a digital to analog converter configured to convert the filtered phase error signal to an analog filtered phase error signal, wherein the digital to analog converter is configured to generate a clock signal comprising a pseudo-random sequence of zeros and ones, and further configured to average the clock signal over a time period to form the clock signal, wherein a probability of the clock signal being a one is proportional to a desired control signal V TUNE , wherein the control signal V TUNE is fed into the voltage controlled oscillator in order to adjust a frequency of the output signal and the feedback signal associated therewith.