Patent ID: 8369138

Claim:
A semiconductor memory device comprising: a unit cell including a memory element; a word line coupled to a first end of the unit cell; a bit line coupled to a second end of the unit cell; a control signal generator configured to output an enable signal in response to a read command and an address signal received from an external node; a delay unit configured to delay the enable signal; a word line driving controller configured to determine whether the word line is activated or deactivated in response to the enable signal, an output signal of the delay unit, and a test signal; and a word line driving unit configured to drive the word line and output an access signal in response to an output signal of the word line driving controller, wherein, in a normal mode, data stored in the memory element is read out as a current signal flowing from the bit line to the word line through the unit cell, and wherein, in a test mode, data stored in the memory element is read out by performing a read operation while deactivating the word line.