Patent ID: 8188574

Claim:
A microelectronic element, comprising: a semiconductor chip including a monocrystalline silicon-on-insulator layer (“SOI layer”), a bulk monocrystalline silicon layer and a buried oxide (BOX) layer separating the SOI layer from the bulk silicon layer, the SOI layer having a plurality of microelectronic semiconductor devices therein, the chip having a plurality of peripheral edges extending in a direction away from the SOI layer downwardly through the BOX layer and the bulk silicon layer; a crack stop extending in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip outside the barrier, the crack stop including a first crack stop ring contacting a silicon portion of the chip above the BOX layer and extending continuously in the first lateral directions to surround the active portion of the chip; a guard ring (“GR”) including a GR contact ring extending downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending linearly at least generally parallel to the first crack stop ring to surround the active portion of the chip, the GR further including a continuous metal ring extending continuously in the first lateral directions to surround the active portion of the chip, the metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.