Patent ID: 7321168

Claim:
A semiconductor package, comprising: a semiconductor chip having an active surface, a backside and a plurality of bonding pads disposed on the active surface; a preformed lid covering the active surface of the semiconductor chip; a passivation layer covering the backside of the semiconductor chip; a plurality of solder pads disposed on a backside of the passivation layer, wherein adjacent ones of said solder pads are separated from each other by the passivation layer which isolates the adjacent ones of said solder pads from each other; a plurality of conductive pastes surrounding the semiconductor chip and being exposed on an outer peripheral surface of the semiconductor package; and a plurality of metal extension traces each extending from one of the bonding pads on the active surface of the semiconductor chip to an upper surface of one of the conductive pastes, wherein the bonding pads are respectively electrically connected to the solder pads on the backside of the passivation layer via the metal extension traces and the conductive pastes.