Patent ID: 7864578

Claim:
A semiconductor memory, comprising: a plurality of blocks, each of the blocks comprising a plurality of pages, each of the pages having a plurality of memory cells; and a mark storage area provided at each of the blocks, wherein the mark storage area of a block having defective bits fewer than N (N is an integer number more than 0) in all pages in the block stores a first data showing a normal block, the mark storage area of a block including at least one page having defective bits more than N and including no page having defective bits more than M (M is an integer number M >N) stores a second data showing a pseudo-pass block as a pseudo-normal block, the mark storage area of a block including at least one page having defective bits more than M stores a third data as a defective block, a block in which the first data is stored in the mark storage area is used, as a normal block, a block in which the third data is stored in the mark storage area is not used, but is classified as a defective block, and a block in which the second data is stored in the mark storage area is not used, but is classified as a defective block, when a number of defective bits detected for every error correction unit of each page is larger than a number of error correctable defective bits, while the block in which the second data is stored is used as an available block when the number of defective bits in all error correction units is less than the number of error correctable defective bits.