Patent ID: 6873537

Claim:
A ferroelectric memory cell array comprising: first and second bitlines formed in a first direction; first, second, third, and fourth split wordlines formed to cross the first and second bitlines; a first cell region including first and second memory cells; and a second cell region including third and fourth memory cells; wherein the first and third split wordlines are used as gate lines in the first cell region and as plate lines in the second cell region, and the second and fourth split wordlines are used as plate lines in the first cell region and as gate lines in the second cell region; wherein the third memory cell includes a third transistor with a gate connected to the second split wordline and one of a source and drain connected to the second bitline; and a third ferroelectric capacitor with one terminal connected to another one of the source and drain of the third transistor and another terminal of the third ferroelectric capacitor connected to the third split wordline.