Patent ID: 7799687

Claim:
A method of manufacturing a semiconductor memory device, the method comprising: forming a polysilicon layer pattern on a substrate; partially etching the substrate using the polysilicon layer pattern as an etching mask forming a trench at an upper portion of the substrate; forming a silicon oxide layer on the substrate covering the polysilicon layer pattern and filling up the trench; polishing the silicon oxide layer using a slurry composition until the polysilicon layer pattern is exposed forming an isolation layer in the trench, the slurry composition including about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto the polysilicon layer pattern forming a passivation layer on the polysilicon layer pattern, the nonionic surfactant having a triblock copolymer chemical structure including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block, and a remainder of water; and forming a structure on the substrate including the isolation layer, the structure including a gate insulation layer and a conductive pattern.