Patent ID: 8685776

Claim:
A method for forming a wafer level package device from only a base silicon-on-insulator (SOI) wafer and a cover plate wafer, the method comprising: etching at least one active component in an active layer of the base SOI wafer, the SOI wafer having a handle layer separated from the active layer by a dielectric layer; etching the dielectric layer in the vicinity of the formed at least one active component after etching of the at least one active component; etching a dielectric layer of the cover plate wafer to form cavities to coincide with the at least one active component, the cover plate wafer having a handle layer attached to the cover plate wafer dielectric layer; bonding the dielectric layer of a cover plate wafer to non-active components of the active layer; etching at least one of the handle layers and corresponding dielectric layer to expose a portion of a surface of the active layer; and forming a metallization on a portion of the exposed surface of the active layer, wherein the at least one active component is included within a cavity, thus the wafer level package device is formed from at most two SOI wafers.