Patent ID: 7375714

Claim:
A driving device comprising: a clocked NAND including a first reset signal input transistor, a second reset signal input transistor, and a first clocked inverter, a first electrode of the first reset signal input transistor being electrically connected to a voltage VDD, a second electrode of the first reset signal input transistor being electrically connected to an output terminal of the clocked NAND; a clock line CLKBX line configured to provide a clock signal CLKBX to the first clocked inverter; a clock line CLKX configured to provide a clock signal CLKX signal to the first clocked inverter; and a reset line RST configured to provide a reset signal RST to a gate electrode of the first reset signal input transistor and a gate electrode of the second reset signal input transistor, the first reset signal input transistor being active when the reset signal RST is at low level, the second reset signal input transistor being non-active when the reset signal RST is at low level, and an output voltage from the output terminal of the clocked NAND being at high level when the reset signal RST is at low level.