Patent ID: 8778808

Claim:
A method of fabricating a semiconductor device, comprising: sequentially stacking a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer over a semiconductor substrate, the gate electrode layer defining sidewalls; patterning the gate electrode layer, the second conductive layer, the dielectric layer, and the first conductive layer, wherein the first conductive layer partially remains to prevent the tunnel insulating layer from being exposed; etching the sidewalls of the gate electrode layer; forming a first passivation layer on the entire surface including the sidewalls of the gate electrode layer, wherein the first passivation layer formed on the sidewalls of the gate electrode layer is thicker than the first passivation layer formed in other areas; performing a cleaning process to remove byproducts resulting from the etch process of the gate electrode layer; and forming a gate pattern by etching the first passivation layer, the first conductive layer, and the tunnel insulating layer.