Patent ID: 8004482

Claim:
An apparatus for driving a liquid crystal display device, comprising: a liquid crystal panel including a plurality of gate lines and a plurality of data lines arranged perpendicularly to each other; a gate driver that supplies a gate pulse having a scan period to the gate lines, the scan period having a first period and a second period; and a data driver that samples an input N-bit (where N is a positive integer) digital data signal to generate positive (+) and negative (−) polarity analog data voltages, generates a modulated data voltage according to an M-bit (where M is a positive integer smaller than or equal to N) data value of the sampled digital data signal, outputs a positive data voltage higher than the positive (+) polarity analog data voltage and negative data voltage lower than the negative (−) polarity analog data voltage, and supplies the positive and negative data voltages to the data lines in the first period of the gate pulse and supplies the analog data voltage to the data lines in the second period of the gate pulse, wherein the data driver comprises: a shift register that generates a sampling signal; a latch that latches the N-bit digital data signal in response to the sampling signal and outputs the latched N-bit digital data signal in response to a data output enable signal; a modulator that generates the modulated data voltage in the first period of the gate pulse according to the M-bit digital data signal outputted from the latch, wherein the first period of the gate pulse is shorter than the second period of the gate pulse; and a digital/analog converter that converts the N-bit digital data signal from the latch into the analog data voltage, generates the positive and negative data voltages by mixing the analog data voltage and the modulated data voltage, and outputs the positive and negative data voltages to data lines according a polarity control signal; wherein the digital/analog converter comprises: a positive polarity decoder that generates the positive (+) polarity analog data voltage by decoding the N-bit digital data signal supplied from the latch; a negative polarity decoder that generates negative polarity analog data voltage by decoding the N-bit digital data signal supplied from the latch; a mixer having a positive data voltage generator connected to output terminals of the positive polarity decoder and the modulator and a negative data voltage generator connected to output terminals of the negative polarity decoder and the modulator, wherein the positive data voltage generator generates the positive data voltage by mixing the positive (+) polarity analog data voltages with the modulated data voltage and the negative data voltage generator generates the negative data voltage by subtracting the modulated data voltage from the negative (−) polarity analog data voltages; and a multiplexer that selects any one of the positive and negative data voltages according to a polarity control signal, and outputs the selected one to the data lines.