Patent ID: 7649992

Claim:
A processor that processes message data according to a cipher block chaining messaging authentication code (CCM) protocol, the processor comprising: a first input (TEXTIN) to receive headers and payloads of messages in block form; a second input (KEY) to receive a cipher key; a third input (CTRFINAL) to receive a counter block; a fourth input (TEXT_LD) to receive an indication that a data block is ready to be received at the processor's first input; a first output (CIPHERTEXTOUT) to provide a data block processes according to a cipher block chaining messaging authentication code (CCM) protocol; a second output (TRDY) to provide signal requesting the provision of a data block at the processor's first input; a first cipher circuit having a first input to receive a data block to be ciphered, a second input coupled to the processor's second input to receive a cipher key, a first output to provide a ciphered result, the first cipher circuit generating a ciphered result at its first output that is a function of a data block presented at its first input and a cipher key presented at its second input; a second cipher circuit having a first input to receive a data block to be ciphered, a second input coupled to the processor's second input to receive a cipher key, a first output to provide a ciphered result, the first cipher circuit generating a ciphered result at its first output that is a function of a data block presented at its first input and a cipher key presented at its second input; a controller coupled to receive at least the processor's first, third, and fourth inputs and to receive the first outputs of the first and second cipher circuits, and further coupled to provide data to the first inputs of the first and second cipher circuits, and to provide the outputs of the processor, the second controller having a first memory (Y) to store intermediate data blocks, wherein the controller circuit processes a first sequence of data blocks through the first cipher circuit to generate a message integrity code and a second sequence of data blocks through the second cipher circuit to generate a set of ciphered data blocks, wherein at least one of the data blocks in the first sequence is generated from data held in the first memory and a data block provided at the processor's first input, and wherein at least one of the data blocks in the second sequence is generated from a data block provided at the processor's first input.