Patent ID: 7890933

Claim:
An apparatus comprising: a processing unit of a processor; a memory coupled to the processor; and an instruction set operable on the processing unit of the processor and including instructions: to instantiate a data structure in the memory to collect a representation of a working set; and to define a hash unit operable on the processing unit to map a plurality of working set elements into the data structure using a hash function, wherein, in a program, the working set W(t i , τ) for i=1, 2 . . . , where i is an integer, is a set of distinct memory segments {s 1 , s 2 . . . s ω } accessed over the i th window of size τ within a time interval t i ; wherein the window is a sequence of τ consecutive memory accesses; wherein the working set size is ω, the cardinality of the set of unique segments that are accessed by members of the window.