Patent ID: 8782291

Claim:
A system comprising: a first processor; a second processor; a first memory; and a first multiplexer coupled to said first processor, said second processor and said first memory, wherein said first multiplexer comprises a plurality of outputs, wherein said first multiplexer is configured to communicate first content from said first memory to said first processor using a first output of said plurality of outputs, and wherein said first multiplexer is configured to directly receive said first content from said first memory and to communicate said first content from said first memory to said second processor using a second output of said plurality of outputs, wherein said second processor is configured to control a display device to display said first content while said first processor is in a low-power state, a second memory; and a second multiplexer coupled to said first processor, said second processor and said second memory, wherein said second multiplexer is configured to communicate second content from said second memory to said first processor in a first state, and wherein said second multiplexer is configured to communicate said second content from said second memory to said second processor in a second state.