Patent ID: 7732895

Claim:
A semiconductor device, comprising: at least one capacitor; at least one resistor; a plurality of triple-stacked structures all having the same structure, each of said triple-stacked structures comprising one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by said lower electrode layer and said upper electrode layer; a first via structure connected to an end of said at least one upper electrode layer; a second via structure connected to an end of said one lower electrode layer; a conductive pattern layer above the first via structure and the second via structure; and a third via structure, wherein a size of said lower electrode layer of each of said plurality of triple-stacked structures is the same with each other, wherein said at least one capacitor includes one of said plurality of triple-stacked structures, wherein said at least one resistor includes another one of said plurality of triple-stacked structures, wherein the conductive pattern layer is adapted to connect the first via structure to the second via structure, and wherein the conductive pattern layer is also adapted to connect the third via structure with the first via structure and the second via structure.