Patent ID: 7696572

Claim:
A semiconductor device, comprising: a plurality of split source regions of a first conductivity type interdigitated with a plurality of drain regions in a well region of a semiconductor substrate, wherein each of the split source regions includes a first source region and a second source region, and wherein at least one of the drain regions is located adjacent to at least one from a group consisting of: the first source region, and the second source region; a plurality of active area taps of a second conductivity type different from the first conductivity type, a first active area tap from among the plurality of active area taps being in electrical contact with the well region, wherein the first active area tap is located between the first source region and the second source region; an isolating layer enclosing the plurality of split source regions, the plurality of active area taps and the plurality of drain regions, a second active area tap from among the plurality of active area taps being in contact with the isolating layer; and a plurality of gate electrodes, wherein at least one of the gate electrodes defines a channel region between at least one pair from a group consisting of: the first source region and the first drain region, and the second source region and the first drain region.