Patent ID: 7886114

Claim:
A storage controller connected to a plurality of disk drives comprising: a shared memory; at least one channel control unit; a cache memory connected to the at least one channel control unit via a cache switch and having cache slots and temporarily storing data stored in said plurality of disk drives; at least one disk control unit connected to the cache memory via the cache switch and configured to control data transfer between the at least one channel control unit and the plurality of disk drives, wherein the at least one channel control unit includes: a plurality of channel processors each configured to process a read/write request from a host system, a plurality of local memories, each of which corresponds to one of the plurality of channel processors and stores a first management information and a group information, the first management information indicates whether data read and written by a corresponding channel processor exists in one of the cache slots of the cache memory, the group information indicates a relationship between each of a plurality of logical addresses provided to the host system and one of the plurality of channel processors; and a buffer memory, connected to the plurality of channel processors, for storing data transmitted between the plurality of channel processors, wherein the shared memory stores second management information indicating whether data read and written by the plurality of channel processor exists in one of the cache slots of the cache memory, wherein, when a first channel processor from among the plurality of channel processors receives a read request from the host system, the first channel processor selects a second channel processor from among the other channel processors based on the group information, and the first channel processor transmits a distribution processing request to the second channel processor, wherein upon receipt of the distribution processing request, the second channel processor checks whether a cache hit occurs based on the first management information corresponding to the second channel processor in one of the plurality of local memories corresponding to the second channel processor, wherein if the cache hit occurs with the first management information, then the second channel processor fetches the data from one of the cache slots of the cache memory and writes the fetched data in the buffer memory and the first channel processor controls transfer of data written in the buffer memory to the host system; and wherein if the cache hit does not occur with the first management information, then the second channel processor checks whether a cache hit occurs based on the second management in the shared memory.