Patent ID: 8384835

Claim:
A pixel circuit comprising: a display element unit including a unit display element; an internal node that configures as part of the display element unit and holds a voltage of pixel data applied to the display element unit; a first switch circuit that transfers the voltage of the pixel data supplied from a data signal line to the internal node through at least a predetermined switch element; a second switch circuit that transfers a voltage supplied to a predetermined voltage supply line to the internal node without passing through the predetermined switch element; and a control circuit that holds a predetermined voltage depending on the voltage of the pixel data held by the internal node at one terminal of a first capacitor element and controls connection/disconnection of the second switch circuit, wherein the second switch circuit includes a first transistor element and a third transistor element, the control circuit includes a second transistor element, and each of the first to third transistor elements has a first terminal, a second terminal, and a control terminal that controls an electrical connection between the first and second terminals, the second switch circuit is configured by a series circuit of the first transistor element and the third transistor element, the control circuit is configured by a series circuit of the second transistor element and the first capacitor element, one terminal of the first switch circuit is connected to the data signal line, one terminal of the second switch circuit is connected to the voltage supply line, the other terminals of the first and second switch circuits and the first terminal of the second transistor element are connected to the internal node, the control terminal of the first transistor element, the second terminal of the second transistor element, and the one terminal of the first capacitor element are connected to each other, the control terminal of the second transistor element is connected to a first control line, the control terminal of the third transistor element is connected to a second control line, and the other terminal of the first capacitor element is connected to the second control line or a third control line.