Patent ID: 8803339

Claim:
An integrated circuit (IC) chip, comprising: a matrix of solder bumps aligned in lines of a first axis and lines of a second axis, adjacent solder bumps aligned in the first axis having a minimum distance and adjacent solder bumps aligned in the second axis having the minimum distance, the matrix of solder bumps including: a first pair of solder bumps aligned in a first line of the first axis and configured to transmit a first pair of differential signals; a second pair of solder bumps aligned in a second line of the first axis and configured to transmit a second pair of differential signals; a third pair of solder bumps aligned in a third line of the first axis and configured to transmit a third pair of differential signals in a same direction as the second pair of solder bumps; and a fourth pair of solder bumps aligned in a fourth line of the first axis and configured to transmit a fourth pair of differential signals in a same direction as the first pair of solder bumps, wherein the first line and the second line are adjacent, and the second pair of solder bumps are staggered from the first pair of solder bumps to avoid alignment with the first pair of solder bumps in the second axis such that distances from at least one of the second pair of solder bumps to at least one solder bump of the first pair of solder bumps are larger than the minimum distance, the second line and the third line are adjacent, and the third pair of solder bumps are in alignment with the second pair of solder bumps in the second axis, and the third line and the fourth line are adjacent, and the fourth pair of solder bumps are staggered from the third pair of solder bumps to avoid alignment with the third pair of solder bumps in the second axis such that distances from at least one of the fourth pair of solder bumps to at least one solder bump of the third pair of solder bumps are larger than the minimum distance.