Patent ID: 7700399

Claim:
A method for manufacturing a CMOS image sensor, the method comprising: providing a semiconductor substrate; forming at least one isolation region between a periphery region of the substrate and a photo-sensing region of the substrate; forming a first well in the periphery region and a second well in the photo-sensing region of the substrate; forming a third well in the photo-sensing region of the substrate, the third well being associated with a photodiode; depositing a gate oxide layer on a surface of the substrate; depositing a polysilicon layer over the gate oxide layer; depositing a first metal layer over the polysilicon layer; etching the polysilicon layer and first metal layer to form an least one gate in the photo-sensing region and at least one gate in the periphery region; forming spacers for each of the at least one gate in the photo sensing region and the at least one gate in the periphery region; exposing the substrate to a first thermal environment to form silicide in the at least one gate in the periphery region; implanting a first plurality of ions to form at least two doped regions in the first well adjacent to the at least one gate in the periphery region; implanting a second plurality of ions to form a doped region in the second well adjacent to the at least one gate in the photo-sensing region; depositing a silicide block layer over the photo-sensing region including the photodiode and over the at least one gate and adjacent source and drain regions in the photo-sensing region while the periphery region remained exposed, wherein the silicide block layer does not extend over the periphery region of the substrate; depositing a second metal layer at least over the periphery region while the photo sensing region is being masked by the silicide block layer, wherein the second metal layer extends over the entire periphery region; exposing the substrate to a second thermal environment after deposition of the suicide block and after deposition of the second metal layer to form silicide in the at least two doped regions in the first well, wherein the silicide block layer prevents silicide formation in the doped region in the second well; and etching after the exposing to the thermal environment to remove the second metal layer.