Patent ID: 7779312

Claim:
A built-in redundancy analyzer (BIRA), built in a chip comprising a plurality of repairable memories, the BIRA comprising: a parameter switch unit, generating an identification code of a fault memory among the repairable memories according to a memory fault signal, and providing a parameter according to the identification code, wherein the parameter comprises a bit number of column address, a bit number of row address, a bit number of word, a number of redundancy columns, and a number of redundancy rows of the fault memory; an input conversion unit, coupled to the parameter switch unit for receiving the parameter, converting a fault location from a first format of the fault memory into a second format used in the BIRA according to the parameter, wherein the first and the second formats have different bit numbers; and an analysis conversion unit, coupled to the parameter switch unit for receiving the parameter and coupled to the input conversion unit for receiving the converted fault location, the analysis conversion unit performing a redundancy repair analysis according to the parameter and the fault location, converting an analysis result from the second format to the first format, and outputting the analysis result to the fault memory.