Patent ID: 6976199

Claim:
A logic circuit comprising: a combinatorial logic having at least first and second input signal lines and at least a first output signal line; and a shift register latch (SRL) chain and a last SRL within the SRL chain, connected to the output of the combinatorial logic, a first SRL of the SRL chain being connected to the first input signal line for outputting a first scan signal thereto, a second SRL of the SRL chain being connected to the second input signal line for outputting a second scan signal thereto, the last SRL being connected to the first output signal line for receiving a first output signal of the combinatorial logic; and a logic unit having at least first and second logic input lines and a logic output line, the first logic input line being connected to the first SRL for receiving the first scan signal therefrom, the second logic input line being connected to a pattern adjust line for receiving a control signal, the logic output line being connected to the second SRL for outputting a logic output signal thereto, wherein the logic output signal is at least one of the first scan signal and an inverted signal of the first scan signal, depending on the logic value of the control signal.