Patent ID: 8278718

Claim:
A semiconductor device comprising: a plurality of NMOS transistors each including a first gate stack and a first contact region, the first gate stacks defining first channel regions thereunder; a plurality of PMOS transistors each including a second gate stack and a second contact region, the second gate stacks defining second channel regions thereunder; a dielectric layer disposed over the NMOS and PMOS transistors; a first opening in the dielectric layer exposing the first contact regions of the NMOS transistors, the first opening extending below the first gate stacks; a second opening in the dielectric layer exposing the second contact regions of the PMOS transistors, wherein the second opening does not extend below the second gate stacks; a barrier plug material of same composition and intrinsic tensile stress disposed within a portion of both the first and second openings, wherein the barrier plug material induces a tensile stress on the first channel regions; and a contact metal disposed on the barrier plug material within the first and second openings, the contact metal having a lower resistivity than the barrier plug material.