Patent ID: 8558208

Claim:
A resistance random access memory comprising: a first electrode; a second electrode; a first variable-resistance layer and a second variable-resistance layer that are arranged between the first electrode and the second electrode; and at least one non variable-resistance layer that is arranged so that positions of the first variable-resistance layer and the second variable-resistance layer between the first electrode and the second electrode are symmetrical to each other, wherein the first variable-resistance layer is arranged to be in contact with the first electrode, the second variable-resistance layer is arranged to be in contact with the second electrode, and the at least one non variable-resistance layer is arranged between the first variable-resistance layer and the second variable-resistance layer to be in contact with the first variable-resistance layer and the second variable-resistance layer, and wherein the at least one non variable-resistance layer includes a first non variable-resistance layer arranged to be in contact with the first variable-resistance layer, and a second non variable-resistance layer arranged to be in contact with the second variable-resistance layer, and a third electrode is arranged between the first non variable-resistance layer and the second non variable-resistance layer.