Patent ID: 7401204

Claim:
A parallel processor performing parallel processing of one or more basic instructions contained in each of a plurality of instruction words, wherein each of the instruction words consists of the one or more basic instructions to be executed by one or more instruction execution units and delimiting information delimiting the one or more basic instructions, said parallel processor comprising: N instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel, wherein N is an integer greater than one; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information to supply at least one basic instruction contained in each instruction word; and an instruction issue unit issuing N instruction pairs in response to the at least one basic instruction supplied from said instruction fetch unit, the N instruction pairs being supplied to N respective instruction execution units for execution of the one or more basic instructions contained in the given instruction word, wherein each of the N instruction pairs supplied to a corresponding instruction execution unit includes a basic instruction and a single effective bit controlling whether the basic instruction is to be executed by the corresponding instruction execution unit.