Patent ID: 8176455

Claim:
A semiconductor device design support apparatus comprising: a first unit that divides a semiconductor device layout into a plurality of segments and generates a macro-model of said plurality of segments by using a current waveform of an instance included in said plurality of segments; a second unit that replaces a substrate interface pattern, with a substrate interface diagram so that a substrate resistance of the substrate interface diagram is substantially equal to a substrate resistance of said substrate interface pattern; and a third unit that generates a substrate netlist, based on said substrate interface diagram of said plurality of segments, wherein the first unit comprises: an input unit that receives as an input at least a layout information of a semiconductor device, the current waveform of the instance, a primitive library information, and a segment division information; a current waveform calculation unit that refers to the data input to said input unit and obtains the current waveform of each segment; a decoupling capacitance calculation unit that refers to the data input to said input unit and obtains a decoupling capacitance of each segment; a first substrate coupling resistance calculation unit that refers to the data input to said input unit and obtains a substrate coupling resistance of a first potential side of each segment; and a second substrate coupling resistance calculation unit that refers to the data input to said aid input unit and obtains a substrate coupling resistance of a second potential side different from said first potential side, of each segment, and wherein a macro-model that holds calculated values calculated by each of said calculation units is generated.