Patent ID: 8599618

Claim:
A method of operating a circuit to provide a word line output (WLS) comprising: supplying a first gate voltage (PG 1 ) at a first voltage bias (VP 1 ) to a source of a first transistor providing the output (WLS); providing the first voltage bias (VP 1 ) to a second transistor and supplying a second voltage bias (VN 1 ) and a second gate voltage (NG 1 ) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor; supplying a third voltage bias (VP 2 ) and a third gate voltage (PG 2 ) to a fourth transistor, and a fourth voltage bias (VN 2 ) and a fourth gate voltage (NG 2 ) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor; and providing a fifth voltage bias (VN 3 ) to a line connecting a first n-well of the third transistor to a second n-well of the fifth transistor.