Patent ID: 7545031

Claim:
A complementary package pair unit, comprising: a first semiconductor chip package, comprising a first substrate having a die mount side and a land side, the die mount side including a die attach region and an unoccupied region, a first package die attached in the die attach region of the die mount side of the first substrate, and first z-interconnection solder balls mounted on ball pads on the die mount side of the first substrate; and a second semiconductor chip package, comprising a second substrate having a die mount side and a land side, the die mount side including a die attach region and an unoccupied region, a second package die attached in the die attach region of the die mount side of the first substrate; wherein the first package is stacked on the second package, the die mount side of the first package facing the die mount side of the second package, wherein the die attach region of the first package is aligned with the unoccupied region of the second package, and wherein the first z-interconnection solder balls on the first package contact ball pads on the die mount side of the second substrate.