Patent ID: 7684534

Claim:
Receiver apparatus for a serial link, comprising: a first clock-data-recovery loop having a digitally controlled phase adjuster comprising recovery means to recover data and generation means to generate information about a phase difference between an input phase signal and a clock phase signal; a clock generator having a digitally controlled second phase adjuster to adjust a phase of said clock generator; a distributor to distribute phase difference information in digital form between said first clock-data-recovery loop and said digitally controlled second phase adjuster of said clock generator; and at least one second clock-data-recovery loop connected to at least one data lane; and at least one synchronizer, each synchronizer connected to one of said at least one second clock-data-recovery loop to transfer recovered data to a clock domain with a clock derived from said digitally controlled second phase adjuster of said clock generator, wherein said first clock-data-recovery loop is connected to a clock lane by one of a direct connection and an indirect connection and wherein at least one of said at least one second clock-data recovery loops can be selected to act as a first clock-data recovery loop.