Patent ID: 8555041

Claim:
A method comprising: receiving a single instruction that includes a return operation; dividing the single instruction into a first micro-operation and a second micro-operation in an instruction decode stage, wherein the first micro-operation is configured for performing the return operation and the second micro-operation is configured for performing a test operation; reading, using the first micro-operation, information associated with a return address from a register file in the instruction decode stage; providing, using the first micro-operation, the information associated with the return address to an arithmetic logic unit in an execution stage; reading, using the second micro-operation in the instruction decode stage in parallel with the first micro-operation in the execution stage, a content of a return value register; responsive to the reading using the second micro-operation in the instruction decode stage, testing the content of the return value register using the second micro-operation in the execution stage; setting, using the second micro-operation in the execution stage, status flags that includes writing a value into a flag register based on testing the content of the return value register; and providing, while the first micro-operation is in a memory stage in parallel with the second micro-operation in the execution stage, the information associated with the return address to a pipeline register connected to a multiplexer included in a writeback stage, the multiplexer configured for sending the information associated with the return address to a program counter via an output of the multiplexer.