Patent ID: 7253529

Claim:
A multi-chip package structure comprising: a first substrate having a top surface and a bottom surface; a first chip attached to the top surface of the first substrate; a plurality of first wires used for electrically connecting the first substrate and the first chip; a sub-package having a top surface and a bottom surface, wherein the bottom surface of the sub-package is attached to the first chip directly, the sub-package includes: a second substrate having a top surface and a bottom surface, the second substrate being electrically connected to at least one of the first substrate and the first chip; a second chip attached to the top surface of the second substrate and electrically connected to the second substrate; and a second molding compound used for encapsulating the second chip and part of the top surface of the second substrate; and a first molding compound used for encapsulating the first chip, the sub-package and the top surface of the first substrate.