Patent ID: 8867680

Claim:
A circuitry system comprising a first clock domain and a synchronous second clock domain of a streaming data bus system that employs a handshake-type transfer protocol, wherein the circuitry system further comprises a clock domain separation device connected into a streaming data link between said first clock domain and said second clock domain to connect the first and second clock domains and to enable a clock in the first and second clock domains to be switched on and off independently from each other while maintaining data integrity of the streaming data, said device comprising: a control logic having a sink interface for receiving control signals from and returning control signals to a data source arranged in said first clock domain, a source interface for transmitting control signals to and receiving control signals from a data sink arranged in said second clock domain, and a system clock input, a data output buffer, an auxiliary input buffer, and a multiplexer, wherein said control logic is connected to each of said data output buffer, auxiliary input buffer, and multiplexer, and wherein: the auxiliary input buffer and the multiplexer each have a data input connected to a same data line to receive a data stream from said data source of the first clock domain, the auxiliary input buffer is operable to buffer data elements of a data stream that has been accepted during a clock cycle in which a non-accept condition of the data sink has been transferred from the source interface to the sink interface of the device a data output of the auxiliary input buffer is connected to a second data input of the multiplexer, a data output of the multiplexer is connected to the data output buffer, and a data output of said data output buffer is connected to a data output line to transmit data to said data sink of the second clock domain, and wherein the clock domain separation device introduces a latency of one clock cycle in forward and backward transfer directions.