Patent ID: 7410870

Claim:
A method of forming a flash memory device, comprising the steps of: forming first and second trench isolation regions at side-by-side locations in a semiconductor substrate; forming a gate electrode of a string selection transistor on a portion of the semiconductor substrate extending between the first and second trench isolation regions; forming first and second trenches in the first and second trench isolation regions, respectively; depositing an inter-gate dielectric layer on the bottoms and sidewalls of the first and second trenches and on sidewalls and an upper surface of the gate electrode; depositing a first control conductive layer on the inter-gate dielectric layer; selectively etching the first control conductive layer and the inter-gate dielectric layer in sequence to expose the sidewalls and the upper surface of the gate electrode and define first and second control gate electrode segments that are separated from bottoms and sidewalls of the first and second trenches, respectively, by first and second inter-gate dielectric layer segments ; and forming a string selection line that extends on the first and second inter-gate dielectric layer segments and electrically contacts an upper surface and sidewalls of the gate electrode by depositing a second control conductive layer directly on the upper surface and sidewalls of the gate electrode and then selectively etching the second control conductive layer and the first control conductive layer in sequence to define the string selection line on the gate electrode and further define a control gate electrode of a memory cell transistor within the flash memory device.