Patent ID: 7847575

Claim:
A method of testing a semiconductor chip having plural circuit structures, comprising: testing a first of the plural circuit structures by (1) contacting with a first nano probe to a conductor structure on a first side of the semiconductor chip, (2) applying an external stimulus to a selected portion of the first side of the semiconductor chip to perturb the first of the plural circuit structures, (3) causing the semiconductor chip to perform a test pattern during the application of the external stimulus, and (4) sensing an electrical characteristic of the first of the plural circuit structures with the first nano probe during performance of the test pattern, the sensed electrical characteristic defining a reference electrical characteristic; testing a second of the plural circuit structures by (1) contacting with the first nano probe another conductor structure on a first side of the semiconductor chip, (2) applying an external stimulus to a selected portion of the first side of the semiconductor chip to perturb the second of the plural circuit structures, (3) causing the semiconductor chip to perform a test pattern during the application of the external stimulus, and (4) sensing an electrical characteristic of the second of the plural circuit structures with the first nano probe during performance of the test pattern; and comparing the sensed electrical characteristic of the second of the plural circuit structures with the reference electrical characteristic.