Patent ID: 8468009

Claim:
A hardware emulator having a plurality of emulation units, each emulation unit comprising: a processor; a memory having a plurality of read ports coupled to the processor; a shadow processor register coupled to a read port of the plurality of read ports, the shadow processor register storing a first amount of data received from the memory via the read port; a shadow processor, coupled to the shadow processor register and the memory, for addressing data within the memory; and an instruction memory configured to provide an instruction word and a control signal to the shadow processor, the instruction memory being further configured to provide a truth table in a field of another instruction word dynamically to the memory, where the control signal causes the shadow processor to select between the at least a portion of the first amount of data in the shadow processor register and the instruction word, wherein the at least a portion of the first amount of data and the instruction word function as a read address for the memory.