Patent ID: 7202125

Claim:
A method of forming a non-volatile memory array, high-voltage circuits and logic circuits on a substrate, the array overlying a first region of the substrate, the high-voltage circuits overlying a second region of the substrate and the logic circuits overlying a third region of the substrate, comprising: forming a first dielectric layer that extends across the first, second and third regions; forming a floating gate polysilicon layer that extends over the first dielectric layer across the first, second and third regions; forming an inter-layer dielectric layer that extends directly over the floating gate polysilicon layer across the first, second and third regions; forming a mask layer that extends over the inter-layer dielectric layer across the first, second and third regions; subsequently forming a plurality of shallow trench isolation structures that extend into the substrate and that separate portions of the floating gate polysilicon layer; and subsequently removing portions of the floating gate polysilicon layer and portions of the mask layer overlying the second and third regions of the substrate without removing portions of the floating gate polysilicon layer and portions of the mask layer that overlie the first region.