Patent ID: 8552958

Claim:
A gate drive circuit, comprising: a plurality of shift registers, in which plural stages are connected one after another to each other, configured to output a plurality of gate signals; and an output control part configured to block outputs of the shift registers during a vertical blanking interval, the output control part configured to apply a gate off voltage to all of the gate lines, wherein the plurality of shift registers are configured to generate the plurality of gate signals using at least one clock signal, and during the vertical blanking interval, the at least one clock signal is not supplied to the plurality of shift registers, wherein data signals are not applied to data lines during the vertical blanking interval, wherein the output control part comprises: a first switching element connected to an output terminal of each of the shift registers, respectively; a second switching element connected to an output terminal of the first switching element and the gate lines, respectively; and a switching control part configured to turn off the first switching elements and turn on the second switching elements during the vertical blanking interval, the second switching element being configured to apply the gate off voltage to the gate line, and wherein the switching control part comprises an SR latch part comprising a set terminal configured to receive a second vertical start signal applied to a last shift register of the shift registers and a reset terminal configured to receive a first vertical start signal applied to a first shift register of the shift registers to be applied after the second vertical start signal, and the SR latch part is configured to output an output signal turning off the first switching element and turn on the second switching element in response to a high level of the second vertical start signal.