Patent ID: 7218158

Claim:
A delay lock loop comprising: a fine delay block comprising: a fine delay line comprising a plurality of fine delay units, wherein an input of the delay line is configured to receive an input signal, and wherein each of the plurality of fine delay units is configured to shift the input signal by a first time delay; and a fine shift register comprising a plurality of individual shift registers each corresponding to a respective one of the plurality of fine delay units, wherein the shifted input signal produced by each of the plurality of fine delay units is fed back to control the respective shift register corresponding to the fine delay unit; and a coarse delay block configured to receive the shifted input signal from the fine delay line, and wherein the coarse delay block is controlled by the fine delay block, wherein the coarse delay block comprises a plurality of coarse delay units each configured to shift the shifted input signal by a second time delay, wherein the second time delay is greater than the first time delay, and wherein the fine delay line is configured to be reset if the input signal is shifted in the fine delay line by the second time delay.