Patent ID: 8120092

Claim:
A semiconductor memory device comprising: first gate electrodes of a plurality of memory cell transistors formed on a semiconductor substrate in series with each other; a second gate electrode of a first selection gate transistor which is adjacent to one end of the plurality of first gate electrodes formed in series with each other and formed on the semiconductor substrate; a third gate electrode of a second selection gate transistor which is adjacent to the second gate electrode of the first selection gate transistor and formed on the semiconductor substrate; a fourth gate electrode of a peripheral transistor formed on the semiconductor substrate; a first sidewall insulating film formed on a side surface of the second gate electrode; a second sidewall insulating film formed on a side surface of the third gate electrode; a third sidewall insulating film formed on a side surface of the fourth gate electrode; a first diffusion layer formed in the semiconductor substrate between the first gate electrodes; and a second diffusion layer formed in the semiconductor substrate between the first gate electrode and the second gate electrode, the second diffusion layer having impurity concentrations of an n-type impurity and a p-type impurity higher than those of the first diffusion layer, wherein a film thickness of the third sidewall insulating film is larger than film thicknesses of the first sidewall insulating film and the second sidewall insulating film, a space between the first gate electrode and the second gate electrode is larger than a space between the first gate electrodes, and a space between the second gate electrode and the third gate electrode is larger than the space between the first gate electrode and the second gate electrode.