Patent ID: 8507301

Claim:
A method for fabricating a TFT array substrate, comprising: forming a gate electrode, a gate line and a gate pad on a substrate; forming a gate insulating layer, a semiconductor layer and a metal layer on the gate electrode; patterning the gate insulating layer, the semiconductor layer and the metal layer so as to form patterns on the gate line, the data line, a TFT region, the gate pad and the data pad; coating and patterning a transparent conductive layer on the substrate to form source and drain electrodes, a semiconductor layer defining a channel therebetween, a channel passivation layer formed on the semiconductor layer, a pixel electrode connected to the drain electrode formed in the TFT region, and upper electrodes of the gate pad and the data pad, wherein the coating and patterning a transparent conductive layer includes: forming a transparent conductive layer on the substrate; forming a stepped photoresist pattern in the TFT region using a partial exposure mask; forming the source electrode, the drain electrode, the pixel electrode, the gate pad upper electrode and the data pad upper electrode by using the photoresist pattern; ashing the photoresist pattern; exposing the active layer defining the channel by patterning the metal layer and the ohmic layer corresponding to the channel, using the ashed photoresist pattern; forming the channel passivation layer on the exposed active layer by exposing the active layer to a plasma, using the ashed photoresist pattern as a mask; and removing the ashed photoresist pattern, and further comprising forming a transparent conductive pattern formed on the data line connected to the source electrode, the source electrode and the drain electrode, which is formed of the same material with the pixel electrode, wherein the gate pad upper electrode is formed on the data metal pattern, wherein the gate pad upper electrode is formed of the same material as transparent conductive pattern.