Patent ID: 7177997

Claim:
A communication bus system comprising: a bus medium ( 16 ); a bus controller ( 120 ) that is arranged to transmit and/or receive messages via the bus medium ( 16 ) in successive time frames, the bus controller ( 120 ) supporting isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively; a processor ( 10 ); a first and second memory section ( 122 a,b ) for exchange of data from the isochronous messages between the processor ( 10 ) and the bus controller ( 120 ), the bus system being arranged to give the bus controller ( 120 ) access priority over the processor ( 10 ) in first and second ones of the time frames respectively, the first and second ones of the time-frames alternating with one another, the bus controller ( 120 ) transferring data from isochronous messages between the bus medium ( 16 ) and the first and second memory section ( 122 a,b ) in the first and second ones of the time frames respectively, the processor ( 10 ) having access priority to the first and second memory section ( 122 a, b ) over the bus controller ( 120 ) in the second and first ones of the time frames respectively; a third memory section ( 14 ) for exchange of data from the non-isochronous messages, a relative access priority of the processor ( 10 ) and bus-controller ( 120 ) to the third memory section ( 14 ) being unchanged in all time frames.