Patent ID: 7869268

Claim:
An integrated circuit having a non-volatile memory, the integrated circuit comprising: a plurality of word lines; memory cells each including a memory point and a selection transistor having a control terminal connected to one of the word lines; a row decoder configured to supply word line selection signals; at least one voltage or current generator to supply the memory cells with an erase or programming voltage or current; and word line drivers interposed between the row decoder and the word lines, each word line driver being configured to cause the selection transistor of a selected memory cell of the memory cells to control an amplitude and a duration of an erase or programming voltage or current pulse applied to the memory point of the selected memory cell, the word line driver being configured to cause the selection transistor of the selected memory cell to control the amplitude and the duration of the erase or programming voltage or current pulse applied to the memory point of the selected memory cell by applying, on the word line coupled to the selected memory cell, a control pulse having a profile that corresponds to a profile of the erase or programming voltage or current pulse.