Patent ID: 8184665

Claim:
A network device comprising: a plurality of interface cards that receive clock signals and clock signal quality information via communication lines, the communication lines being of predetermined communication line types corresponding to the plurality of interface cards, respectively; a controller that acquires the clock signal quality information from the plurality of interface cards, determines one of the clock signals having a highest quality based on the clock signal quality information and instructs a clock processor to select the determined one of the clock signals; and the clock processor that generates a synchronization clock signal used for network synchronization with a DPLL (Digital Phase Locked Loop) circuit, which is included in the clock processor, based on the determined one of the clock signals, wherein the clock processor comprises: a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the plurality of interface cards receiving the determined one of the clock signals; and a clock controller that provides a coefficient to a digital filter included in the DPLL circuit based on the determined communication line type.