Patent ID: 7818641

Claim:
A substrate comprising: A. a full pin device having a first full pin interface that includes a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; B. a reduced pin device having a first reduced pin interface, the reduced pin interface having no more than two leads of which one is a data input/output lead; and C. an interface adapter having: i. a second full pin interface of a test data in lead, a test clock lead, a test mode select lead, and a test data out lead connected with the first full pin interface, ii. a second reduced pin interface having no more than two leads of which one is a data input/output lead connected with the first reduced pin interface, and iii. a third full pin interface that includes a test data in lead, a test clock lead, a test mode select lead, and a test data out lead that is coupled with the second full pin interface and the second reduced pin interface internally of the interface adapter.