Patent ID: 8214616

Claim:
A memory system comprising: a memory controller component; a plurality of memory components including a first memory component and a second memory component; conductors coupling the memory controller component to the plurality of memory components, wherein the conductors comprise: a common address/control bus connecting the memory controller component to each of the memory components in succession such that a first propagation time required for signals indicative of a write operation to propagate on the address/control bus from the memory controller component to the first memory component is different than a second propagation time required for the signals indicative of the write operation to propagate on the address/control bus from the memory controller component to the second memory component; separate first and second data buses connecting the memory controller component to the first and second memory components, the first data bus to convey first data, associated with the write operation, to the first memory component, and the second data bus to convey second data, associated with the write operation, to the second memory component; first and second timing signal conductors that extend from the memory controller component to the first and second memory components, respectively, the first timing signal conductor to convey a first timing signal that controls a time at which the first memory component samples the first data and the second timing signal conductor to convey a second timing signal that controls a time at which the second memory component samples the second data; and wherein the memory controller component includes circuitry to offset phases of the first and second timing signals based, at least in part, on the difference between the first and second propagation times.