Patent ID: 7434188

Claim:
In a circuit design comprised of cells and having a sensitivity to lithographic variation, a method for placing the cells to minimize the sensitivity of the design to lithographic variation, the method comprising: placing a first cell into a first location; placing a second cell into a second location; performing a lithographic simulation on said first cell representative of the likelihood of failure of said first cell in response to a plurality of fabrication conditions indicative of lithographic variation; generating environment data from said lithographic simulation; analyzing said environment data and said second location to determine if the sensitivity of the circuit design to lithographic variation is reducible by moving said first cell; moving said first cell in response to determining that the sensitivity of the circuit design to lithographic variation is reducible by moving said first cell; performing a lithographic simulation on said second cell representative of the likelihood of failure of said second cell in response to a plurality of fabrication conditions indicative of lithographic variation to produce additional environment data, wherein said analyzing said environment data comprises analyzing said additional environment data; and performing optical proximity correction on said first cell to produce optical data, and wherein said lithographic simulation on said first cell is performed on said optical data.