Patent ID: 8400850

Claim:
A semiconductor storage device comprising: a plurality of first SRAM cells that store data, the plurality of first SRAM cells being arranged in a lattice pattern; a plurality of first bit line pairs provided along first SRAM cells arranged in a column direction; a plurality of second SRAM cells each provided for one of the first bit line pairs, each of the plurality of second SRAM cells being configured to amplify and store a potential difference between read signals output to a corresponding one of the first bit line pairs; a control cell that controls an amplification function of the plurality of second SRAM cells; at least one second bit line pair provided in the plurality of second SRAM cells; a word line control circuit that outputs a first control signal used to activate first SRAM cells arranged on a row selected by a row address in the plurality of first SRAM cells, a second control signal used to activate a second SRAM cell selected by a column address in the plurality of second SRAM cells, and a third control signal used to activate the control cell; a plurality of word lines provided along first SRAM cells arranged in a row direction, the plurality of word lines being configured to transmit the first control signal; a sense amplification circuit that amplifies a potential difference between read signals output from a second SRAM cell activated based on the second control signal to the second bit line pair; and a write control circuit that outputs a write signal to the second SRAM cell activated based on the second control signal through the second bit line pair, wherein the word line control circuit: in a first activation period, raises a voltage level of the first control signal from a substrate potential to a predetermined potential at a first rate, and then raises the voltage level from the predetermined potential to a first power supply potential at a second rate lower than the first rate; in a second activation period subsequent to the first activation period, maintains the voltage level of the first control signal at the first power supply potential; and in a third activation period subsequent to the second activation period, raises the voltage level of the first control signal from the first power supply potential to a second power supply potential.