Patent ID: 7239652

Claim:
A digital logic circuit for determining an output value based on a plurality of inputs values, comprising: an n-level look-ahead network that converts the plurality of input values to a plurality of intermediate values, wherein n is an integer greater than zero; a plurality of multiplexers each having a first and a second input port, an output port, and a control port, the plurality of multiplexers arranged to form a pipelined multiplexer loop having at least a first and a second stage, the first stage consisting of a first multiplexer, and the second stage consisting of a second and a third multiplexer, the pipelined multiplexer loop being coupled to the n-level look-ahead network; a first communications link that couples the output port of the second multiplexer to the first input port of the first multiplexer; a second communications link that couples the output port of the third multiplexer to the second input port of the first multiplexer; a first feedback loop that couples the output port of the first multiplexer to the control port of the first multiplexer, the first feedback loop comprising a first delay device having a first delay time; and a second feedback loop that couples the output port of the first multiplexer to the control ports of the second and third multiplexers, the second feedback loop comprising the first delay device and a second delay device having a second delay time, wherein the first delay time is an integer multiple of the second delay time and is equal to (n +1) times a clock period of operation of the digital logic circuit.