Patent ID: 8060929

Claim:
An apparatus comprising: a microprocessor core; a bus interface that is in communication with the microprocessor core; random access memory (RAM) that is in communication with the bus interface; power-on reset (POR) circuit; an internal memory that is electronically erasable and nonvolatile and that in communication with the bus interface, wherein the internal memory includes at least one security bit that at least enables a security mode to prevent access to contents of the internal memory after the POR circuit has asserted a power-on/reset of the apparatus, and wherein the security bit, once set to enable the security mode, is reset when the contents of the internal memory are erased; an enable address (EAn) pin that is in communication with microprocessor core, wherein a first state of the EAn pin indicates that instructions are to be fetched from the contents of the internal memory; and a memory output port that is in communication with the bus interface, wherein the microprocessor core masks the memory output port when the EAn pin is in the first state.