Patent ID: 7859935

Claim:
A memory system comprising: a memory cell array; an access control circuit that receives either of an access start request or an access end request for the memory cell array and controls access to the memory cell array; a high-voltage-supply booster circuit for driving the access control circuit from a low voltage for memory access to a high voltage for memory access by supplying electric charge that is stored in advance to the access control circuit in response to the access start request; the high-voltage-supply booster circuit comprising: a high-voltage boost capacitor for discharging electric charge that is stored in advance from a first-reference-voltage supply source to the supply source of the high voltage in the access control circuit in response to the access start request; a first semiconductor switch, when charging, connecting a first electrode of the high-voltage boost capacitor to the first-reference-voltage supply source and, when discharging, connecting the first electrode to the high-voltage supply source in the access control circuit and, at other times, opening the first electrode; and a second semiconductor switch, when charging, connecting a second electrode of the high-voltage boost capacitor to the ground and, when discharging, connecting the second electrode to a second-reference-voltage supply source and, at other times, connecting the second electrode to the ground; and a low-voltage-supply booster circuit for absorbing excess electric charge when the access control circuit is switched from the high voltage to the low voltage in response to the access end request.