Patent ID: 8163190

Claim:
A method for fabricating a fine pattern, the method comprising: forming a target layer to be patterned on a semiconductor substrate; forming a sacrificial pattern on the target layer, the sacrificial pattern including first sacrificial patterns having a line shape and arranged at a first spacing, second sacrificial patterns connected to edges of the first sacrificial patterns, and third sacrificial patterns isolated at a second spacing narrower than the first spacing and arranged to face the second sacrificial patterns, wherein the third sacrificial patterns have a block shape extending in a direction perpendicular to the line shape of the first sacrificial patterns and the third sacrificial patterns are spaced from the sides of the second sacrificial patterns and are not connected to the second and first sacrificial patterns; forming a spacer on sidewalls of the sacrificial pattern to selectively fill a gap defined by the second spacing and expose the target layer corresponding to the first spacing; selectively removing the sacrificial pattern; and forming a fine pattern with partially different critical dimensions by selectively etching the exposed portion of the target layer using the spacer as an etch mask.