Patent ID: 7050036

Claim:
A liquid crystal display, comprising: a liquid crystal display panel having a liquid crystal cell matrix for displaying a picture; a scanning driver for applying a scanning pulse to scanning lines of the liquid crystal display panel; and a data driver for applying a video signal to data lines of the liquid crystal display panel, and wherein the scanning driver has a first shift register including a plurality of first stages connected in cascade for shifting a start pulse inputted through an input terminal and sequentially outputting the shifted pulse; and a plurality of first level shifters for level-shifting a voltage level of the shifted pulse applied from each of the first stages and outputting it as the scanning pulse, wherein the data driver has a sampling switch array for sampling and outputting the video signal in response to an input sampling signal, and a second shift register including: a plurality of second stages connected in cascade for shifting a start pulse inputted through an input terminal and sequentially outputting the shifted pulse; and a plurality of second level shifters for level-shifting a voltage level of the shifted pulse applied from each of the second stages and outputting it as the sampling signal, wherein each of the first stages and the second stages includes an output buffer for selecting and outputting either a clock signal at a first clock signal input line or a first supply voltage in accordance with voltages of a first node and a second node, wherein each of the first stages and the second stages includes a first controller for controlling the first node in accordance with the start pulse and a second controller for controlling the second node in accordance with the start pulse and a clock signal at a second clock signal input line; wherein each of the level shifters includes an output part for selecting and outputting either the first supply voltage or a third supply voltage in accordance with a voltage on a third node and a third controller for controlling the third node in accordance with a clock signal at a fourth clock signal input line and the first node.