Patent ID: 7523420

Claim:
A method of producing a design for a memory device from a banked memory architecture, the banked memory architecture specifying a maximum number of memory banks and a maximum number of rows per memory bank, the method comprising the steps of: (a) receiving input parameters indicating a number of properties of said memory device, said properties comprising at least a number of rows R for said memory device; (b) performing a degeneration process on the banked memory architecture in order to produce said design of a memory device having said properties, the degeneration process comprising the steps of: (i) selecting a number of memory banks B for said design, where said number is an integer less than or equal to the maximum number of memory banks specified by the banked memory architecture, and B is not constrained to be a factor of R; and (ii) partitioning the number of rows R amongst said memory banks selected at said step (b)(i) such that in each memory bank the number of rows in that memory bank is an integer less than or equal to the maximum number of rows per memory bank specified by the banked memory architecture.