Patent ID: 7620762

Claim:
A data transfer control device that controls data transfer, the data transfer control device comprising: a controller that analyzes a packet received from a host-side data transfer control device through a serial bus; an interface circuit that generates interface signals and outputs the interface signals to an interface bus, the interface signals including a vertical synchronization signal, a horizontal synchronization signal and a data signal; and an internal register in which timing information that specifies change timings of signal levels of the vertical synchronization signal, the horizontal synchronization signal and the data signal output from the interface circuit are set, the controller analyzing the packet received from the host-side data transfer control device through the serial bus to determine whether the racket includes a synchronization signal code in a synchronization signal code field, the synchronization signal code directing the interface circuit to generate the vertical synchronization signal and the horizontal synchronization signal, the interface circuit generating the vertical synchronization signal, the horizontal synchronization signal and the data signal based on the synchronization signal code set in the packet, and the interface circuit adjusting actual timings of the vertical synchronization signal, the horizontal synchronization signal and the data signal based on the timing information set in the internal register when the packet including the synchronization signal code is received.