Patent ID: 8754713

Claim:
A transmission and reception RFIC comprising: a receiving circuit for receiving a received signal, being applied to a direct conversion architecture; and a PLL circuit configured by a feedback loop, the PLL circuit comprising: a phase frequency detector making comparison of phases and frequencies of a reference signal and a feedback signal; a time to digital converter converting an output of the phase frequency detector into a digital value; a digital loop filter removing a high frequency noise component from an output of the time to digital converter; a digitally controlled oscillator controlled based on an output of the digital loop filter; and a divider frequency-dividing an output of the digitally controlled oscillator and outputting the feedback signal, wherein an offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the time to digital converter even when the PLL circuit is locked.