Patent ID: 8289783

Claim:
A semiconductor memory device comprising: a plurality of memory cells, in which a plurality of data are stored at i levels of level â€œ0â€, and level â€œ1â€ to level â€œ(iâˆ’1)â€ (i is a natural number equal to 1 or larger); and a control section configured to simultaneously write data to n (n is a natural number equal to 1 or larger) cells of the plural memory cells, wherein when the n memory cells are written, the control section performs a write operation and a write verify operation, when, in the write verify operation, m (mâ‰¦n) cells to be simultaneously written are not yet written, the control section repeats the write operation and the write verify operation again, and writes only write cells at lower levels at the beginning of the repeated operations.