Patent ID: 7840826

Claim:
A computer array comprising: a plurality of processors; and wherein each processor is connected to at least two adjoining processors by a plurality of links, each said link being connected to only two of said processors; said plurality of processors includes a plurality of edge processors located at the edge of said array, each said edge processor having three links connecting said edge processor to three adjacent processors, four corner processors, each said corner processor located at a corner of said array and having two of said links connecting said corner processor to two of said edge processors, and a plurality of hybrid processors, each of said hybrid processors connected by four links to four processors, the link of said edge processor not connected to another one of said edge processors or one of said corner processors being connected to a single said hybrid processor; said hybrid processors selectively switch between a rest mode, a routing mode, and a processing mode; and when one of said hybrid processors receives an instruction on one of said links connected to said one of said hybrid processors, said one of said hybrid processors switches between said rest mode and at least one of said routing mode and said processing mode.