Patent ID: 8476972

Claim:
A time amplifier circuit comprising: a first inverter comprising a first NMOS transistor and a first PMOS transistor, respective gates of the first NMOS and PMOS transistors coupled together to a first input node for receiving a first input signal, respective drains of the first NMOS and PMOS transistors coupled together to provide a first output signal at a first output node, a source of the first NMOS transistor coupled to a ground node through a first additional NMOS transistor having a gate coupled to the first input node; a second inverter comprising a second NMOS transistor and a second PMOS transistor, respective gates of the second NMOS transistor and the second PMOS transistor coupled together to a second input node for receiving a second input signal, respective drains of the second NMOS transistor and the second PMOS transistor coupled together to provide a second output signal at a second output node, a source of the second NMOS transistor coupled to the ground node through a second additional NMOS transistor having a gate coupled to the second input node; a first pull-down path, from the first output node to the ground node, enabled in response to the first input signal and the second output signal being high; and a second pull-down path, from the second output node to ground, enabled in response to the second input signal and the first output signal being high; wherein the voltage at the first input node is independent of the voltage at the second input node.