Patent ID: 7473648

Claim:
A method of forming a planar field effect transistor comprising the steps of: providing a semiconductor substrate; forming a gate dielectric layer on a top surface of said semiconductor substrate; forming a gate layer disposed on said gate dielectric layer; forming a first pattern layer for receiving a first portion of a gate layer pattern; providing said first portion of said gate layer pattern and patterning said first pattern layer with said first portion of said gate layer pattern, wherein said step of providing said first portion of said gate layer pattern comprises separating a representation of gate layer pattern into said first portion of said gate layer pattern containing at least one gate and a second portion of said gate layer pattern containing at least one gate pad; forming a planarizing layer over said first pattern layer; forming a second pattern layer over said planarizing layer for receiving said second portion of said gate layer pattern that combines with said first portion of said gate layer pattern to form said gate layer pattern; patterning said second pattern layer with said second portion of said gate layer pattern; etching said gate layer using said first pattern layer and second pattern layer as masks, thereby patterning said gate layer with said gate layer pattern; and completing said transistor.