Patent ID: 8234539

Claim:
A method for correcting errors in a memory array, the method comprising: (a) providing an error correction algorithm for correcting errors up to a first bit error rate in a correctable group of memory cells, said correctable group having a standard size; (b) generating a first set of ECC bits having information corresponding to a first group of memory cells, said first group having a first size larger than the standard size; (c) generating a second set of ECC bits having information corresponding to a second group of memory cells, said second group defined from said first group and having a second size smaller than said first size, so that the second group is a portion of said first group; (d) applying said error correction algorithm to correct errors in said first group based on said first set of ECC bits; (e) determining if said error correction algorithm based on said first set of ECC bits fails in step (d); and (f) if said error correction algorithm fails then applying said error correction algorithm to correct errors in said second group based on said second set of ECC bits.