Patent ID: 8296581

Claim:
A processor arrangement, comprising: a first processor, wherein the first processor is a trusted processor; a first processor secret key being assigned to the first processor; a second processor configured to be operable in a trusted mode and in a non-trusted mode; a second processor secret key being assigned to the second processor; wherein the first processor secret key and the second processor secret key are equal and form a shared secret key; at least one memory configured to be shared by the first processor and the second processor; wherein the second processor comprises: a memory interface configured to provide access to the at least one memory; and a processor communication interface configured to provide a memory access service to the first processor, wherein the first processor comprises a processor communication interface configured to use the memory access service from the second processor, wherein the first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service, wherein the first processor is configured to generate a random number and to provide the random number to the second processor, wherein the second processor is configured to generate a cryptographic hash value over a value previously stored in the memory and the random number using the shared secret key, and to store the generated cryptographic hash value in the memory; wherein the first processor is configured to directly read at least one of the value previously stored in the memory using the memory access service and the stored cryptographic hash value from the memory; wherein the second processor is configured to process data to be stored into the memory received from the first processor in a first data message using the at least one cryptographic mechanism and to generate a second data message including the data to be stored into the memory, in the context of the memory access service.