Patent ID: 7999817

Claim:
A graphics processing apparatus, comprising: a first graphics processing module; a second graphics processing module connected to the first graphics processing module; a memory connected to the first graphics processing module and the second graphics processing module; and a buffering unit connected to the memory and the first graphics processing module, the buffering unit configured to buffer vertex attributes en route to the memory, the vertex attributes including a first group of vertex attributes for a first vertex and a second group of vertex attributes for a second vertex, the first vertex being different from the second vertex, the buffering unit configured to reorder the first group of vertex attributes having an initial order to produce a reordered, first group of vertex attributes for the first vertex and having a modified order, the buffering unit configured to reorder the second group of vertex attributes having an initial order to produce a reordered, second group of vertex attributes for the second vertex and having a modified order, the buffering unit configured to coalesce a subset of the reordered, first group of vertex attributes and a subset of the reordered, second group of vertex attributes to form reordered coalesced vertex attributes to be stored within a common range of addresses in the memory, the buffering unit configured to issue a single write request to the memory on behalf of the reordered, coalesced vertex attributes, wherein the graphics processing apparatus is configured to route the vertex attributes from the first graphics processing module to the second graphics processing module and to the buffering unit, and the graphics processing apparatus is configured to feed back at least one of the reordered, coalesced vertex attributes from the memory to the first graphics processing module.