Patent ID: 8754580

Claim:
A semiconductor apparatus comprising: an input terminal to which an input voltage is applied; an output terminal at which an output voltage is obtained; a power supply circuit unit configured to generate the output voltage from the input voltage, the output voltage having a value corresponding to a duty cycle of a voltage setting signal that is externally applied to the semiconductor apparatus; and a determination circuit unit configured to determine whether the voltage setting signal has a predetermined signal level for the duration of a first predetermined time, wherein the determination circuit unit, when it determines that the voltage setting signal does not have the predetermined signal level for the duration of the first predetermined time, activates the power supply circuit unit, and deactivates the power supply circuit unit when it determines that the voltage setting signal has the predetermined signal level for the duration of the first predetermined time, wherein the determination circuit unit includes: a first capacitor; a first charge/discharge circuit configured to charge the first capacitor with the input voltage applied to the input terminal, and configured to discharge the first capacitor when the input voltage is not applied to the input terminal; a second capacitor; a second charge/discharge circuit configured to charge or discharge the second capacitor in accordance with a signal level of the voltage setting, and configured to change the rate of charging of the second capacitor depending on a terminal voltage of the first capacitor; a binarizing circuit configured to generate a signal for controlling the activation of the power supply circuit unit by binarizing a terminal voltage of the second capacitor; and a retaining circuit configured to retain a signal level of an output signal of the binarizing circuit upon inversion of the signal level of the output signal of the binarizing circuit as a result of the discharge of the second capacitor, the retaining circuit retaining the signal level of the output signal of the binarizing circuit by charging the second capacitor with the input voltage in accordance with the signal level of the voltage setting signal, wherein the second charge/discharge circuit is configured to decrease the rate of charging of the second capacitor when the terminal voltage of the first capacitor exceeds a predetermined value.