Patent ID: 8826061

Claim:
A timer comprising: a first buffer configured to set a first count reset value; a second buffer configured to set a second count reset value; a register block configured to receive the first and second count reset values from the first and second buffers, respectively, increase a count value, and reset the count value when the count value is the same as the first count reset value at a first particular time or when the count value is the same as the second count reset value at a second particular time; and a timer interrupt generator configured to receive reset information that the count value is reset from the register block and generate an interrupt request signal, wherein the first buffer is configured to change the first count reset value and generate a changed first count reset value, wherein the second buffer is configured to change the second count reset value and generate a changed second count reset value, and wherein each of the changed first and second count reset values is generated during increasing the count value.