Patent ID: 8476146

Claim:
A method, comprising: forming a first layer on a first side of a first wafer, the first wafer having a second side opposite the first side, the first layer having a first coefficient-of-thermal-expansion (CTE), wherein forming the first layer on the first side includes forming the first layer on a first silicon (111) surface on the first side of the first wafer; forming a third layer on the second side of the first wafer, the third layer having a third CTE), wherein forming the third layer on the second side includes forming the third layer on a second silicon (111) surface on the second side of the first wafer; after forming a third layer, bonding the first wafer to a silicon (100) surface of a second wafer in a manner so that the first layer is disposed in between the first and second wafers, wherein the silicon (100) surface interfaces with the first layer at a first interface; removing a portion of the first wafer from the second side; thereafter forming a second layer over the second side of the first wafer, the second layer having a second CTE higher than the first CTE; and after forming the second layer, cooling the second layer, the first layer, and the first and second wafers to about a room temperature, wherein the cooling causes the second layer to contract more than the first layer which creates a tensile stress at a second interface between the first layer and the second layer, wherein the cooling causes the second wafer having the silicon (100) surface to contract more than the first layer which creates a compressive stress at the first interface between the silicon (100) surface of the second wafer and the first layer, and wherein the tensile stress at the second interface and the compressive stress at the first interface substantially balance each other out during the cooling such that the first wafer, first layer, second layer, third layer, and second wafer are substantially flat after the cooling.