Patent ID: 8074196

Claim:
An integrated circuit design support apparatus for supporting a logical design of an integrated circuit, comprising: a memory including a control program for implementing the logical design of the integrated circuit; an input device for inputting a specification of the integrated circuit; and an arithmetic apparatus; wherein the arithmetic apparatus executes, based on the control program and the specification: a first stage for creating a functional design of the integrated circuit, a second stage for performing logic synthesis in response to the functional design result, a third stage for creating a floor plan of arranging a plurality of modules on a chip in response to the logic synthesis result, a fourth stage for determining whether there is any timing violation in wiring formed between a plurality of modules by using floor plan information obtained from the floor plan, a fifth stage for determining whether there is any wiring congestion in the plurality of modules by using the floor plan information, and a sixth stage for outputting the floor plan information as information for creating a packaging design of the integrated circuit when there is no timing violation and no wiring congestion, wherein the fifth stage includes: a tenth stage for calculating a first total length of wiring that can be formed in a module, an eleventh stage for calculating a second total length of wiring requested by the module, a twelfth stage for determining whether the second total length is within the first total length, and a thirteenth stage for determining that there is no wiring congestion in the module when the determination of the twelfth stage is affirmed, and determining that there is wiring congestion in the module when the determination of the twelfth stage is denied.