Patent ID: 7426600

Claim:
A bus switch circuit, comprising: plural master side interface circuits inputting/outputting signals for plural bus masters respectively; and one or plural slave side interface circuit(s) inputting/outputting signals for one or plural bus slave(s) and functionally coupled to the plural master side interface circuits via a switch matrix, wherein at least one external interrupt signal is inputted to at least one bus master, said plural master side interface circuits and said one or plural slave side interface circuits, the at least one interrupt signal comprising a priority that sets the at least one bus master that receives the at least one external interrupt signal to have a higher priority than the remaining plural bus masters that do not receive the external interrupt signal and establishing a signal path between said plural bus masters and said one or plural bus slave(s) in accordance with the priority through the switch matrix, wherein upon receiving the at least one external interrupt signal, an existing signal path between a bus master of the plural masters that does not receive the external interrupt signal and said one or plural bus slave is suspended.