Patent ID: 8736306

Claim:
An apparatus, comprising: a pre-emphasis circuit configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals; and an output stage circuit configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths, wherein the pre-emphasis circuit is configured to selectively inject charge onto the communication paths to assist with a signal transition on at least one of the communication paths; and a termination circuit coupled to the communication paths, wherein the termination circuit is configured to provide a differential termination to a common mode node, the termination circuit including: a transistor stack connected between a VDD node and a VSS node to determine a common mode potential on the common mode node between a VDD potential on the VDD node and a VSS potential on the VSS node; a first resistance between and directly connected to both a first one of the differential communication paths and the common mode node; and a second resistance between and directly connected to both a second one of the differential communication paths and the common mode node.