Patent ID: 7763991

Claim:
A voltage generating circuit comprising: a first step-down transistor including a gate controlled by a first voltage and a drain connected to a first high potential side power source side, and outputting, from a source of the first step-down transistor, a second high potential side supply voltage obtained by stepping down the first high potential side supply voltage, in an active state which allows a flow of a first consumption current; a second step-down transistor including a gate controlled by the first voltage and a drain connected to the first high potential side power source, and outputting the second high potential side supply voltage from a source of the second step-down transistor in the active state and in a standby state which allows a flow of a second consumption current whose amount is less than that of the first consumption current; and a gate voltage stabilizing circuit including a first transistor including a drain to which the first voltage is inputted and a gate to which a first control signal is inputted, a second transistor including a drain connected to a source of the first transistor, a source to which the first voltage is inputted, and a gate to which a second control signal is inputted, and a capacitor connected to the source of the first transistor and the drain of the second transistor, when the standby state changes to the active state, the first transistor changing from OFF to ON based on the first control signal, the second transistor changing from ON to OFF based on the second control signal, and therefore the capacitor drawing a charge on the gate side of the first step-down transistor to suppress a fluctuation in the first voltage to be applied to the gate side of the first step-down transistor, and when the active state changes to the standby state, the first transistor changing from OFF to ON based on the first control signal, the second transistor changing from ON to OFF based on the second control signal, and therefore the capacitor discharging an accumulated charge to the gate side of the first step-down transistor to suppress the fluctuation in the first voltage to be applied to the gate of the first step-down transistor.