Patent ID: 8069363

Claim:
A Double Data Rate (DDR) output latch comprising: a first edge triggered flip-flop for: receiving a first clock signal; receiving signals of a first part of a data bus; and providing the signals of the first part of the data bus synchronized to the first clock signal, a multiplexer for: receiving the synchronized signals of the first part of the data bus and signals of a second part of the data bus; and providing an output signal including either the synchronized signals of the first part of the data bus or the signals of the second part of the data bus depending on a multiplexor control signal, an edge detector for providing a second clock signal having a rate substantially double a rate of the first clock signal, a set-reset flip-flop for providing an output signal which changes state on both a rising and falling edge of the second clock signal, a delay element for: receiving the output signal from the set-reset flip-flop; and providing the multiplexor control signal, and a second edge triggered flip-flop for: receiving the output signal from the multiplexor; receiving the second clock signal; and providing a DDR output signal synchronized to the second clock signal.