Patent ID: 7793083

Claim:
A processor that, during operation, switches between a secure mode of performing processing with use of secure information and non-secure information and a normal mode of performing processing with use of the non-secure information, the processor comprising: an internal memory operable to have stored therein a plurality of secure information pieces and non-secure information pieces acquired from an external memory, a plurality of attribute information pieces each corresponding to a different stored information piece and indicating whether the corresponding information piece is one of the secure information pieces or the non-secure information pieces, and a plurality of processing specification information pieces each corresponding to a different one of the stored secure information pieces and being for specifying in which of a plurality of secure processes the corresponding secure information piece is to be used; and a disabling unit operable to, before a switch in a case of switching from the secure mode to the normal mode, specify, according to the attribute information pieces, a secure information piece from among the secure information pieces and non-secure information pieces stored in the internal memory, and disable only the specified secure information piece.