Patent ID: 7732330

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: selectively forming a first material including an amino group over a substrate by discharging a composition including the first material including an amino group; immersing the first material including an amino group in a solution including a first plating catalyst material so as to form the first plating catalyst material over the first material including an amino group; immersing the first plating catalyst material in a plating solution including a first metal material so as to form a source or drain electrode layer over a surface of the first material including an amino group; forming a semiconductor layer over the source or drain electrode layer; forming a gate insulating layer over the semiconductor layer; selectively forming a second material including an amino group over the gate insulating layer by discharging a composition including the second material including an amino group; immersing the second material including an amino group in a solution including a second plating catalyst material so as to form the second plating catalyst material over the second material including an amino group; and immersing the second plating catalyst material in a plating solution including a second metal material so as to form a gate electrode layer over a surface of the second material including an amino group.