Patent ID: 8309449

Claim:
A method for forming a semiconductor device comprising: forming neighboring buried gates on a semiconductor substrate including an active region; forming an insulating layer on the semiconductor substrate; selectively removing the insulating layer from at least a region over an upper part of the active region; forming a photoresist pattern to expose a cell area using an exposure mask for opening the cell area of the semiconductor substrate; etching the insulating layer using the photoresist pattern as an etch mask; forming a bit line on the upper part of the active region between the neighboring buried gates; and forming a storage electrode contact plug that is adjacent to the bit line and that has a laterally extending lower portion, wherein forming the bit line includes: forming a first interlayer insulating layer and a bit line contact plug on the active region between the neighboring buried gates; forming a bit line electrode, a first nitride layer, and a hard mask layer on the first interlayer insulating layer, the bit line electrode contacting the bit line contact plug; etching the hard mask layer, the first nitride layer, the bit line electrode, and the insulating layer to form a bit line structure; and forming a bit line spacer on a sidewall of the bit line structure.