Patent ID: 7242561

Claim:
An electrostatic discharge (ESD) protection unit for providing an ESD path from an input/output (I/O) pad to either a high voltage node VDD pin or a low voltage node VSS pin, the unit comprising: a first ESD detection circuit connecting to the I/O pad; an N-trigger low voltage triggered PNP (LVTPNP) device including an emitter connecting to the VDD pin, a collector connecting to the I/O pad, and an N-trigger node connecting to an output of the first ESD detection circuit wherein the N-trigger LVTPNP device shuts down in a normal operation and is speedily triggered on by way of a higher potential-level output applied by the first ESD detection circuit on the N-trigger node of the LVTPNP device upon an ESD stress occurs between the I/O pad and the VDD pin; a second ESD detection circuit connecting to the I/O pad; and a P-trigger LVTPNP device including an emitter connecting to the I/O pad, a collector connecting to the VSS pin, and an P-trigger node connecting to an output of the second ESD detection circuit wherein the P-trigger LVTPNP device shuts down in a normal operation and is speedily triggered on by a lower potential-level output applied from the first ESD detection circuit on the P-trigger node of the LVTPNP device upon an ESD stress occurs between the I/O pad and the VSS pin.