Patent ID: 7768061

Claim:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell, comprising: a semiconductor substrate; a doped drain region for a drain formed in a predetermined portion of the semiconductor substrate; an insulating layer pattern that forms a sidewall of a word line, the insulating pattern being on the doped drain region, the insulating pattern having second insulating layer spacers being apart from each other and a third insulating layer that fills a region between the second insulating layer spacers, and upper surfaces of the second insulating layer spacers being substantially coplanar with an upper surface of the third insulating layer; a doped source region on a predetermined portion of the semiconductor substrate, the doped source region being separated from the doped drain region by an interposing channel region; an ONO layer disposed on one sidewall of the insulating layer pattern and on a portion of the channel region; a gate insulating layer formed on the channel region where the ONO layer is not formed; and a spacer-shaped word line for a gate disposed on the ONO layer disposed on the sidewall of the insulating layer pattern, and on upper surfaces of the ONO layer and gate insulating layer.