Patent ID: 7510955

Claim:
A method of fabricating a multi-fin field effect transistor, comprising: providing a substrate having at least one trench therein, the top surface of the substrate being covered with a pad layer; filling a first oxide layer into the trench and removing a portion of the pad layer to form an opening, wherein the top surface of the first oxide layer is higher than that of the substrate; forming a first circular or rectangular insulating layer and a second circular or rectangular insulating layer interlaced with each other on the sidewall of the opening; forming a mask layer above the substrate to cover a portion of the first circular or rectangular insulating layer and second circular or rectangular insulating layer, and exposing a region predetermined to form a gate; removing a portion of the second circular or rectangular insulating layer by using the mask layer as a mask to expose a portion of the surface of the substrate; removing a portion of the substrate by using the mask layer and the first circular or rectangular insulating layer as masks to form two fin-type layers; removing the mask layer; forming a gate oxide layer on the sidewalls of the two fin-type layers and the surface of the substrate; forming a conductive layer in the region above the substrate; removing the first circular or rectangular insulating layer, a portion of the first oxide layer and the second circular or rectangular insulating layer which are not covered by the conductive layer, so as to expose the surface of the substrate; and forming a lightly doped region in the substrate by using the conductive layer as a mask.