Patent ID: 8148645

Claim:
A wiring substrate comprising: a base substrate; a first resin insulating layer provided on the base substrate; a laminated capacitor formed within the first resin insulating layer, the laminated capacitor comprising a plurality of capacitors laminated to each other by adhesive, each capacitor including a first electrode, a second electrode opposing the first electrode and a dielectric layer interposed between the first and second electrodes; a first via conductor electrically connecting the first electrodes of the plurality of capacitors to each other; a second via conductor electrically connecting the second electrodes of the plurality of capacitors to each other; a first external terminal electrically connected to the first via conductor; a second external terminal electrically connected to the second via conductor a plurality of conductor patterns provided on the base substrate; and a plurality of conductor patterns provided on the first resin insulating layer, wherein an end face of the laminated capacitor is substantially coplanar with an end face of the first resin insulating layer, the first via conductor electrically connects one of the conductor patterns on the base substrate with a respective one of the conductor patterns on the first resin insulating layer, the second via conductor electrically connects another one of the conductor patterns on the base substrate with another respective one of the conductor patterns on the first resin insulating layer, and a conductor pattern on the first resin insulating layer and the first electrode of the capacitor at an end face of the laminated capacitor are integrated so as to form an integral electrode.