Patent ID: 8270238

Claim:
An electrical system including embedded non-volatile memory configured to emulate NOR-Flash memory using non-Flash-based memory elements and including circuitry configured to reclaim defective memory in the embedded non-volatile memory, comprising: an integrated circuit including a first portion comprised of a semiconductor substrate including circuitry fabricated on a logic plane, and a second portion comprised of a plurality of vertically stacked memory planes in contact with the semiconductor substrate, the second portion is vertically disposed above and is fabricated directly on top of the logic plane and the plurality of memory planes are in contact with one another; at least one two-terminal cross-point memory array embedded in each of the plurality of memory planes and including a plurality of first and second conductive array lines that are electrically coupled with at least a portion of the circuitry and a including a plurality of re-writeable non-volatile two-terminal memory elements operative to store non-volatile data as a plurality of conductivity profiles, each memory element is positioned at a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and includes a first terminal directly electrically coupled with its respective first conductive array line and a second terminal directly electrically coupled with its respective second conductive array line such that each memory element is directly electrically in series with its respective first and second conductive array lines, each memory element including an electrolytic tunnel barrier in contact with the first terminal and having a thickness that is less than 50 Å, the electrolytic tunnel barrier in contact with and electrically in series with a mixed valence conductive oxide having mobile oxygen ions and the mixed valence conductive oxide in contact with the second terminal, the circuitry fabricated on the logic plane including a NOR-type Flash memory interface (NOR I/F) electrically coupled with a plurality of signals including control signals, address signals, and data signals for performing data operations on one or more of the plurality of two-terminal memory elements in the at least one two-terminal cross-point memory array, and a memory reclamation circuit configured to operate in a programming mode and a functional mode.