Patent ID: 7078889

Claim:
A semiconductor test apparatus comprising: a first time interpolator which receives a clock output from a device under test, obtains the clock by using a plurality of strobes having specified timing intervals, outputs the obtain clock as time-series level data, selectively receives level data indicative of an edge timing of a rise edge and/or a fall edge of the level data, and outputs positional data indicative of an edge timing of the selected level data; a second time interpolator which receives output data output from the device under test, obtains the output data by using a plurality of strobes having specified timing intervals, and outputs the obtained output data as time-series level data; a digital filter which receives and holds the positional data output from the first time interpolator, and outputs a recovery clock indicative of a predetermined edge timing from one or more sets of the positional data; and a data selection circuit which receives the time-series level data output from the second time interpolator, selects the level data with an edge timing of the recovery clock output from the digital filter, and outputs the selected level data as measurement data of the device under test.