Patent ID: 7492810

Claim:
A parallel correlator comprising: a data memory having a sample-sequential input and a sample-parallel output, said data memory organizing the sample-sequential input into blocks of n sequential samples and providing each of said blocks cyclically to said sample-parallel output; a segmented code register organized to receive a code sequence as an plurality of input samples, said segmented code register organizing the input samples into N segments of L length, wherein N is less than n and greater than one; the segmented code register configured to register the input samples in their order of input and to one of forward-shift or backward-shift the registered samples on each clock cycle prior to parallel output, said forward-shift shifting the registered samples by one sample position and the backward-shift shifting the registered samples by one segment of samples; said segmented code register having a sample parallel output; and an inner product calculator having at least two sample-parallel inputs, said inner product calculator having one output representing the inner product of the two sample-parallel inputs; wherein a first of said N segments is provided to the inner product calculator for processing with each of said blocks prior to providing a second of said N segments to the inner product calculator for processing with any of said blocks.