Patent ID: 8340112

Claim:
A method for implementing enhanced link bandwidth for a headless interconnect chip in an interconnect system, the headless interconnect chip not connected to a source device or a destination device, the interconnect system includes a multiple-path local rack interconnect system used to transfer packets from a source high bandwidth device to a destination high bandwidth device, the interconnect system includes a plurality of interconnect chips, each interconnect chip connected to a plurality of local (L) links and a plurality of distance (D) links and including the headless interconnect chip, said method comprising: providing the headless interconnect chip with a cut through switch and a store and forward switch, and a switch select logic operating in a threshold mode or a programmable counter mode for selecting the cut through switch or the store and forward switch; receiving a packet from an incoming link to be transmitted on an outgoing link on the headless interconnect chip; said switch select logic selectively using the cut through switch and the store and forward switch for moving packets received from the incoming link to the outgoing link on the headless interconnect chip based upon said switch select logic operating in said threshold mode or operating in said programmable counter mode.