Patent ID: 8115250

Claim:
A semiconductor device, comprising: a first conductivity type semiconductor base body; a first conductivity type pillar region including a first conductivity type semiconductor region integrally formed to cover the entire surface of the first conductivity type semiconductor base body; second conductivity type pillar regions including a second conductivity type semiconductor region periodically arranged in the direction approximately parallel to the main surface of the first conductivity type semiconductor base body and arranged in a striped pattern in approximately the same direction as the first conductivity type pillar region; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions of the transistors in the element region formed on the surface of the first conductivity type pillar region and in contact with the second conductivity type pillar regions, the body regions including a second conductivity type semiconductor region; a gate insulating film formed on the first conductivity type pillar region and body regions; gate electrodes formed on the gate insulating film in such a manner as to straddle part of the body regions and part of the surface of the first conductivity type pillar region; source regions formed on part of the surface of the body regions at the end portions of the gate electrodes, the source regions including a first conductivity type semiconductor region; and body potential extraction regions formed on the surface of the body regions, the body potential extraction regions including a second conductivity type impurity diffusion layer, wherein voids are formed in the second conductivity type pillar regions of the termination region.