Patent ID: 7163613

Claim:
A method of manufacturing a semiconductor device, comprising: immersing a substrate in a plating bath, wherein the substrate has a first interconnect pattern formed on one surface and a second interconnect pattern electrically connected to the first interconnect pattern and formed on the other surface; electrically connecting the first and second interconnect patterns to a cathode; disposing a first anode to face the first interconnect pattern; disposing a second anode to face the second interconnect pattern; and passing currents of different current densities between the first and second anodes and the cathode to form a first plating layer on the first interconnect pattern by the current from the first anode and to form a second plating layer on the second interconnect pattern by the current from the second anode so that the second plating layer is thicker than the first plating layer; providing a resin on the first plating layer; mounting a semiconductor chip on the substrate with the resin positioned therebetween so that the semiconductor chip is electrically connected to the first interconnect pattern; and providing a conductive material on the second plating layer.