Patent ID: 8448002

Claim:
A power management system comprising: a plurality of data processing modules coupled in series, wherein each of said data processing modules is operable for individually determining whether it is eligible to be placed into an idle state; a clock module coupled in parallel to each of said data processing modules, wherein said clock module is operable to turn off clock signals to any subset of said data processing modules eligible for said idle state while continuing to provide clock signals to any other of said data processing modules; and a controller module operable for detecting signals from said plurality of data processing modules, wherein said signals comprise a first signal asserted by a first data processing module, said first signal indicating that said first data processing module has determined it is eligible to be placed in said idle state, wherein further said controller module optionally asserts a second signal in response to said first signal, wherein said second signal is asserted if said controller module determines that said first data processing module is allowed to enter said idle state, and wherein said controller module does not assert said second signal if said controller module determines that said first data processing module will receive data from an upstream data processing module before said first data processing module can be placed in said idle state and then awakened.