Patent ID: 7299392

Claim:
A semiconductor integrated circuit device comprising: a PLL circuit; a frequency-dividing circuit; a first setting register circuit which holds first data; a timing detecting circuit; clock generation circuits comprising sequential circuits and gates; and logic circuits each of which comprises logic paths of a flip-flop—a logic stage—a flip-flop; wherein the PLL circuit is synchronized with an externally supplied clock pulse and generates an internal clock from the externally supplied clock pulse; wherein the frequency-dividing circuit generates test clock pulses with at least one of plural different phases and frequencies from the internal clock; wherein the test clock pulses pass through the gates to the flip-flops when the gates open; wherein the sequential circuits control opening and closing of the gates according to status transitions of the sequential circuits; wherein the sequential circuits concurrently transit to a predetermined state to open the gates, when the timing detecting circuit detects that the values of the test clock pulses correspond with the first data; and wherein the gates open in the predetermined state.