Patent ID: 7339407

Claim:
A delay locked loop (DLL) circuit for providing an adjustable time delay of a periodic input signal, comprising: a plurality of controllable delay elements, each delay element comprising a first input, a first output, and a control input, wherein the first inputs and the first outputs of the delay elements are connected in series to form a delay chain, the delay chain comprising a second input, the second input being the first input of a first delay element of the delay chain, and a second output, the second output being the first output of a last element of the delay chain; a phase detector connected to the second input and the second output, wherein the phase detector is configured to generate a control signal based on the periodic input signal and a delayed signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted via the respective control input coupled to the phase detector based on the control signal; a selection unit having inputs which are respectively connected to the respective outputs of the delay elements in the delay chain, wherein the selection unit is configured to select, based on a selection variable applied to the selection unit, an output signal from one of the delay elements as an output of the DLL circuit; and a compensation circuit configured to compensate for additional delay, which is additional to the delay provided by the delay elements, between the periodic input signal and the output signal from the DLL circuit and which is caused at least by the selection unit, wherein the compensation circuit modifies the selection variable provided to the selection unit to select the output signal.