Patent ID: 7476622

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a gate on a device formation region of a semiconductor substrate, and forming source and drain regions in the device formation region of the semiconductor substrate adjacent respective sides of the gate, wherein the gate comprises a gate dielectric layer, a gate conductive layer and sidewall spacers located at respective sidewalls of the gate conductive layer; sequentially forming a buffer layer and an etch stop layer over the source region, the drain region and the gate to obtain an intermediate structure; forming a planarized first interlayer insulating film over a surface of the intermediate structure, wherein the first interlayer insulating film is a silicon oxide film formed by high-density plasma chemical vapor deposition; dry etching the first interlayer insulating film until portions of the etch stop layer disposed over the source region, the drain region and the sidewall spacers are exposed to form self-aligned contact holes in the first interlayer insulating film over the source region and the drain region, respectively; wet etching the etch stop layer to remove the portions of the etch stop layer disposed over the source region, the drain region and the sidewall spacers; and forming respective contact pads by filling the self-aligned contact holes with conductive polysilicon.