Patent ID: 6864705

Claim:
An output buffer in operation under a power voltage and a ground voltage, comprising: an output end; a plurality of PMOS transistors interconnected between a voltage source for providing said power voltage and said output end in parallel; a plurality of NMOS transistors interconnected between a ground for providing said ground voltage and said output end in parallel; and a control circuit coupled to gates of said PMOS transistors and said NMOS transistors, wherein a first number of said PMOS transistors are turned on in response to the switching status of said output end from a low level to a high level, a second number of said PMOS transistors are turned on in response to the continuous status of said output end at said high level, a third number of said NMOS transistors are turned on in response to the switching status of said output end from said high level to said low level, and a fourth number of NMOS transistors are turned on in response to the continuous status of said output end at said low level, and wherein said first number and said third number are greater than said second number and said fourth number, respectively.