Patent ID: 8122199

Claim:
A multiport semiconductor memory device comprising: first and second port units respectively coupled to first and second processors; a first dedicated memory area accessed by only the first processor via the first port unit and implemented using Dynamic Random Access Memory (DRAM) cells; a second dedicated memory area accessed by only the second processor via the second port unit and implemented using DRAM cells; a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using Static Random Access Memory (SRAM) cells; a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area; and first and second interface units respectively coupled to the shared memory area, the first interface unit connecting the first port unit with the shared memory area and the second interface unit connecting the second port unit with the shared memory area, wherein each of the first and second interface units converts DRAM address/data compatible with data storage in the first and second dedicated memory areas into SRAM address/data compatible with data storage in the shared memory area.