Patent ID: 8686934

Claim:
A display device comprising: a first wire to which a first video signal is input; a source signal line driver circuit electrically connected to the first wire; and a first region and a second region which is adjacent to the first region, wherein the first region comprises: a first capacitor element; a second capacitor element; a first switch controlling conduction or non conduction between the first wire and a first electrode of the first capacitor element; and a second switch controlling conduction or non conduction between the first wire and a first electrode of the second capacitor element, wherein a second electrode of the first capacitor element is electrically connected to a second electrode of the second capacitor element, wherein the first switch is directly connected to the second switch, wherein the second region comprises a first pixel directly connected to the first wire, wherein each of the first switch and the second switch comprises an n-channel transistor and a p-channel transistor, wherein the n-channel transistor comprises: a first semiconductor layer including a first n-type region, a second n-type region, and a first channel formation region interposed between the first n-type region and the second n-type region; an insulating layer over the first semiconductor layer; and a first gate electrode over the insulating layer, the first gate electrode overlapping with the first channel formation region, wherein the p-channel transistor comprises: a second semiconductor layer including a first p-type region, a second p-type region, and a second channel formation region interposed between the first p-type region and the second p-type region; the insulating layer over the second semiconductor layer; and a second gate electrode over the insulating layer, the second gate electrode overlapping with the second channel formation region, wherein the insulating layer has a first opening overlapping with the second n-type region and a second opening overlapping with the second p-type region, wherein the first wire is electrically connected to the first n-type region and the first p-type region, wherein the second n-type region is directly connected to the second p-type region, wherein the second n-type region is electrically connected to the second p-type region through a metal layer formed in the first opening and the second opening, wherein a part of the second n-type region of the first switch is the first electrode of the first capacitor element, wherein a part of the second n-type region of the second switch is the first electrode of the second capacitor element, and wherein the first capacitor element and the second capacitor element are connected in turn to the first wire during a period from completing input of a first signal to a first gate signal line to starting input of a second signal to a second gate signal line.