Patent ID: 7932553

Claim:
A semiconductor device comprising: an insulated gate transistor including a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the plurality of first cells, the plurality of first cells and the second cell located in a semiconductor substrate, a gate terminal of the plurality of first cells coupled with a gate terminal of the second cell, a source terminal of the plurality of first cells coupled with a source terminal of the second cell on a lower potential side; and a resistor including a first terminal and a second terminal, the first terminal coupled with a drain terminal of the second cell, the second terminal coupled with a drain terminal of the plurality of first cells on a higher potential side, wherein a gate voltage of the insulated gate transistor is feedback-controlled based on an electric potential of the resistor, the insulated gate transistor is a vertical insulated gate transistor, and the semiconductor substrate comprises: a PN column layer having a first surface and a second surface and including a plurality of first columns having a first conductivity type and a plurality of second columns having a second conductivity type, the plurality of first columns and the plurality of second columns alternately arranged so as to be in contact with each other, each of the plurality of second columns providing a drift region; a first semiconductor layer having the first conductivity type and being in contact with the first surface of the PN column layer, the first semiconductor layer providing a channel-forming layer; a second semiconductor layer having the second conductivity type and being in contact with the second surface of the PN column layer, the second semiconductor layer providing a drain region; a plurality of second conductivity-type regions having the second conductivity type and disposed at a surface portion of the first semiconductor layer, each of the plurality of second conductivity-type regions providing a source region; and a separating region penetrating the second semiconductor layer to one of the plurality of first columns in such a manner that the separating region surrounds the second cell in a plane of the semiconductor substrate and the separating region divides the second semiconductor layer into a first section coupled with the drain terminal of the plurality of first cells and a second section coupled with the drain terminal of the second cell.