Patent ID: 6894520

Claim:
A semiconductor device, comprising a capacitance measurement circuit provided in a portion of a semiconductor substrate, the capacitance measurement circuit including a reference circuit and a test circuit, wherein: the reference circuit includes: a reference series circuit including two reference switching elements connected in series with each other via a first node therebetween, the two reference switching elements being turned ON/OFF at different timings from each other; a pair of first voltage supply sections for supplying two voltages, one being higher than the other, respectively to opposite ends of the reference series circuit; a first reference conductor section connected to the first node; and a second reference conductor section, with a dummy capacitor being formed between the first reference conductor section and the second reference conductor section, and the dummy capacitor having a dummy capacitance; the test circuit includes: a test series circuit including two test switching elements connected in series with each other via a second node therebetween, the two test switching elements being turned ON/OFF at different timings from each other; a pair of second voltage supply sections for supplying two voltages, one being higher than the other, respectively to opposite ends of the test series circuit; a first test conductor section connected to the second node; and a second test conductor section, with a test capacitor being formed between the first test conductor section and the second test conductor section, and the test capacitor having a test capacitance that can be represented by a sum of the dummy capacitance and a target capacitance; and the semiconductor device further comprises voltage suppression means for suppressing an amount of voltage change due to an overshoot or an undershoot in each of the switching elements of the capacitance measurement circuit.