Patent ID: 8042011

Claim:
A method for testing a multi-port memory device to detect multi-port memory fault, wherein the multi-port memory fault affects the memory device when the memory device is accessed simultaneously via a first port and a second port, the method comprising: receiving a sequence of instructions which implement a memory test; generating a first set of test operations for the first port of the memory device and a second set of test operations for the second port of the memory device based in part on the sequence of instructions, wherein the first set of test operations is configured to access a first memory cell of the multi-port memory device via the first port, wherein the second set of test operations is configured to access the first memory cell or a second memory cell of the multi-port memory device via the second port, wherein the second memory cell is adjacent to the first memory cell; applying the first set of test operations to the first port of the multi-port memory device, wherein said applying comprises applying one test operation from the first set of test operations in each iteration; applying the second set of test operations to the second port of the multi-port memory device, wherein said applying comprises applying one test operation from the second set of test operations in each iteration; and determining whether the multi-port memory fault occurs in the multi-port memory device by: inverting, by an irregular-data controller, an expected binary value for the first port in a current iteration in response to determining that a binary value that is being read from the first port in the current iteration was altered by a test operation from the second set of test operations that was performed on the second port during a previous iteration, and determining whether the accessed binary value that is read from the first port matches the inverted expected binary value.