Patent ID: 8432250

Claim:
An apparatus comprising: a multiplexer circuit configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal; a plurality of bit generation circuits each configured to generate one of said plurality of input bits, wherein (A) each of said bit generation circuits generates one of said input bits in response to (i) a first transistor signal connected to a first transistor configured to generate a first voltage threshold, (ii) a second transistor signal connected to a second transistor configured to generate a second voltage threshold, and (iii) a pinch signal, (B) each of said input bits is generated in response to a voltage mismatch between said first voltage threshold and said second voltage threshold, (C) said voltage mismatch occurs as a result of process variations during fabrication, and (D) said plurality of bit generation circuits provide a unique identification of said apparatus that does not change after fabrication; and a control circuit configured to generate said control signal.