Patent ID: 8647939

Claim:
A method of forming complementary metal oxide semiconductor (CMOS) devices, the method comprising: forming a patterned p-type field effect transistor (PFET) gate structure and a patterned n-type field effect transistor (NFET) gate structure over a substrate; forming a first solid source dopant material on the substrate, adjacent sidewall spacers of the PFET gate structure, and a second solid source dopant material on the substrate, adjacent sidewall spacers of the NFET gate structure; performing an anneal process at a temperature sufficient to cause dopants from the first and second solid source dopant materials to diffuse within the substrate beneath the PFET gate structure and NFET gate structure, respectively, so as to form source/drain extension regions; performing halo implants and annealing for the channel regions beneath the PFET and NFET gate structures prior to forming the first and second embedded semiconductor materials; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers of the PFET and NFET gate structures, corresponding to source/drain regions; forming a first embedded semiconductor material in the trenches adjacent the sidewall spacers of the PFET gate structure so as to provide a compressive stress on a channel region of the substrate defined beneath the PFET gate structure; and forming a second embedded semiconductor material in the trenches adjacent the sidewall spacers of the NFET gate structure so as to provide a tensile stress on a channel region of the substrate defined beneath the NFET gate structure; activating dopant materials within the first and second embedded semiconductor materials at a temperature selected to prevent relaxation of stress properties of the first and second embedded semiconductor materials.