Patent ID: 7961547

Claim:
A memory circuit, comprising: first and second memory cells which are connected in parallel between a common write word line and a common read bit line; a first write control circuit which is connected to the first memory cell to be conducted by a write control signal supplied to the common write word line, and to supply a first write signal to the first memory cell; a second write control circuit which is connected to the second memory cell to be conducted by the write control signal supplied to the common write word line and to supply a second write signal to the second memory cell; a first read control circuit which is connected to the first memory cell to be conducted by a first read control signal supplied to a first read word line, and to read out a first read signal to the common read bit line from said first memory cell; and a second read control circuit which is connected to the second memory cell to be conducted by a second read control signal supplied to a second read word line, and to read out a second read signal to the common read bit line from said second memory cell, wherein the first and second write signals are set respectively in the first and second memory cells at a same time via the common write word line, and when either one of the first and second read control signals is input, the first or second read control circuit, which is conducted by the either one of the first and second read control signals outputs a readout signal from the first or second memory cell, which is connected to the first or second read control circuit, to the common read bit line.