Patent ID: 7625797

Claim:
A method of manufacturing an embedded non-volatile (NV) memory, comprising: forming transistor and EEPROM (electrically erasable programmable read-only memory) regions in a semiconductor substrate; depositing a gate oxide on an entire surface of the semiconductor substrate, depositing a first polysilicon layer on the EEPROM region, and forming a first gate poly through patterning and etching processes; removing the gate oxide from regions not below the first gate poly; forming a logic gate oxide, a tunnel oxide and a coupling oxide; depositing a second polysilicon layer and forming a logic gate poly on the transistor region, and a second gate poly on sidewalls of the first gate poly through an etching process, wherein depositing the second polysilicon layer and forming the logic gate poly on the transistor region and the second gate poly on sidewalls of the first gate through the etching process comprises; depositing the second polysilicon layer on the semiconductor substrate including the logic gate oxide, the tunnel oxide, and the coupling oxide, forming a photoresist pattern on the second polysilicon layer, wherein the photoresist pattern does not cover the first gate poly, and etching the second polysilicon layer using the patterned photoresist as an etch mask, whereby the logic gate poly is formed on the transistor region and the second gate poly is formed on the sidewalls of the first gate poly; forming source/drain extension regions; forming sidewall spacer on sidewalls of the logic gate poly and the second gate poly; forming source and drain regions; and forming a silicide on exposed source and drain regions and the logic gate poly.