Patent ID: 7941772

Claim:
A method for correcting timing failures in an integrated circuit comprising: placing a first latch and a second latch near a critical path, wherein the first latch has an input comprising a data value on the critical path; generating a delayed data value from the data value; latching the delayed data value in the second latch; comparing an output of the first latch with an output of the second latch to determine whether the critical path comprises a timing failure condition; and using a controller to execute a predetermined corrective measure for the critical path, wherein: the determination of whether the critical path comprises the timing failure condition comprises determining whether the output of the first latch and the output of the second latch occur within a same clock pulse or different clock pulses; the output of the first latch and the output of the second latch occur within a same clock pulse when the output of the first latch and the output of the second latch occur between a leading edge and a trailing edge of the same clock pulse; and the output of the first latch and the output of the second latch occur within different clock pulses when the output of the first latch occurs before a leading edge of a first clock pulse and the output of the second latch occurs after a trailing edge of a second clock pulse.