Patent ID: 7982521

Claim:
A device for reducing noise induced errors, the device comprises: a latch that comprises a latch input node; and a voltage limiting transfer circuit coupled between a first input node and the latch, the voltage limiting transfer circuit adapted to selectively transfer an input signal from the first input node to the latch during transfer mode, and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range, wherein the voltage limiting transfer circuit comprises: a first transistor; a second transistor; and a third transistor, wherein: a source of the first and second transistors are coupled to a supply source; gates of the first and second transistors are coupled to each other and are adapted to receive an inverted scan enable signal; a drain of the first transistor is coupled to a first intermediate node; a drain of the third transistor is coupled to a second intermediate node; a drain of the second transistor is coupled to a source of the third transistor; and a gate of the third transistor receives an inverted clock signal.