Patent ID: 8743627

Claim:
A memory device, comprising: a memory cell array, comprising: a plurality of read word lines; a plurality of read bit lines; and a plurality of first memory cells, the first memory cells being arranged in a matrix, and each of the first memory cells being electrically connected to one of the read bit lines and one of the read word lines; a first pre-charging switch circuit electrically connected to each of the first memory cells, the first pre-charging switch circuit being used for receiving a first voltage and for determining whether or not to supply the first voltage to each of the first memory cells as an operating voltage according to a pre-charging control signal; a selecting circuit electrically connected to each of the read bit lines, the selecting circuit being used for selecting one of the read bit lines and referring the signal on the selected read bit line as an output signal; an auxiliary memory cell array, comprising: an auxiliary read bit line; and a plurality of second memory cells, the second memory cells being arranged in a column, and each of the second memory cells being electrically connected to the auxiliary read bit line and one of the read word lines; a second pre-charging switch circuit electrically connected to each of the second memory cells, the second pre-charging switch circuit being for receiving a reference voltage and for determining whether or not to supply the reference voltage to each of the second memory cells as an operating voltage according to the pre-charging control signal; a dynamic voltage controller electrically connected to the output of the selecting circuit and the auxiliary read bit line, the dynamic voltage controller being used for receiving a second voltage and for determining whether or not to supply the second voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit; and a sense amplifier electrically connected to the output of the selecting circuit and the auxiliary read bit line, the sense amplifier being used for comparing the voltage level of the output signal of the selecting circuit with the voltage level of the voltage on the auxiliary read bit line and outputting a sensing result accordingly.