Patent ID: 7294901

Claim:
A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type provided on said semiconductor substrate; a first impurity region of said first conductivity type provided in said semiconductor layer, extending from an upper surface of said semiconductor layer to reach an interface with said semiconductor substrate, said first impurity region defining a RESURF isolation region; a first trench isolation structure provided in said semiconductor layer defined in said RESURF isolation region to be connected to said first impurity region, extending from said upper surface of said semiconductor layer to reach at least the vicinity of said interface with said semiconductor substrate, said first trench isolation structure and said first impurity region together defining a first trench isolation region in said RESURF isolation region; a semiconductor element provided in said semiconductor layer defined in said RESURF isolation region excluding said first trench isolation region; and a first MOS transistor formed between said first trench isolation structure and said first impurity region, and without including a portion of said first trench isolation structure or said first impurity region, comprising a second impurity region of said second conductivity type provided in said upper surface of said semiconductor layer, said second impurity region being connected to a drain electrode of said first MOS transistor, a third impurity region of said first conductivity type provided in said upper surface of said semiconductor layer defined between said first and second impurity regions, and a first source region of said second conductivity type provided in an upper surface of said third impurity region, wherein said semiconductor device further comprises a buried impurity region of said second conductivity type provided directly below said second impurity region and at said interface between said semiconductor layer and said semiconductor substrate, said buried impurity region being higher in impurity concentration than said semiconductor layer.