Patent ID: 8373199

Claim:
A semiconductor device, comprising: a silicon substrate having a first active region and a second active region; a silicon germanium (SiGe) feature on the silicon substrate within the first active region, the SiGe feature within the first active region and the silicon substrate within the second active region are substantially coplanar; a p-type field effect transistor (PFET) formed in the first active region including: first source/drain (S/D) features distributed in the SiGe feature and the silicon substrate; a first channel in the SiGe layer, disposed between the first S/D features; and a first metal gate stack disposed on the SiGe layer and overlying the first channel; and an n-type field effect transistor (NFET) formed in the second active region including: second S/D features distributed in the silicon substrate; a second channel in the silicon substrate, disposed between the second S/D features; and a second metal gate stack disposed on the silicon substrate, overlying the second channel, and being different from the first metal gate stack in composition; a dielectric layer disposed on sidewalls of the first metal gate stack; and a spacer disposed on the dielectric layer.