Patent ID: 7414434

Claim:
An input circuit, comprising: first to fourth resistor elements serially provided between a first fixed potential and a second fixed potential being lower than said first fixed potential; an input terminal connected to a connection point of said second resistor element and said third resistor element for receiving an input signal; a first switching transistor controlled to turn on and off by a voltage at a connection point of said third resistor element and said fourth resistor element; a current supplying circuit outputting a supply current when said first switching transistor is on and not outputting said supply current when said first switching transistor is off; a constant voltage generating circuit receiving the supply current from said current supplying circuit to output a constant voltage; a constant voltage output buffering circuit that brings its output into a high-impedance state when said first switching transistor is off, and that receives the constant voltage of said constant voltage generating circuit to output a prescribed voltage to a connection point of said first resistor element and said second resistor element when said first switching transistor is on; a second switching transistor controlled to turn on and off by a voltage between opposing ends of said second resistor element; and a combinational circuit outputting a plurality of identify signals based on combinations of on and off states of said first switching transistor and said second switching transistor.