Patent ID: 8917565

Claim:
A solid state drive controller comprising: a first data transfer block connected to a first port; a second data transfer block connected to a second port; a plurality of FIFOs connected between the first data transfer block and the second data transfer block in parallel, and configured to transfer data between the first data transfer block and the second data transfer block; a plurality of error checking and correction (ECC) blocks coupled to the plurality of FIFOs, respectively; and a central processing unit (CPU) connected to the first and second data transfer blocks through a CPU bus, wherein data is transferred from the first port to the second port through the first data transfer block, the plurality of FIFOs and the second data transfer block, bypassing the CPU bus and the CPU, and data is transferred from the second port to the first port through the second data transfer block, the plurality of FIFOs and the first data transfer block, bypassing the CPU bus and the CPU, under control of the CPU, and wherein the plurality of ECC blocks are configured to generate ECC data based on first data stored in the plurality of FIFOs when the first data is transferred from the plurality of FIFOs to the second data transfer block and to detect errors of second data stored in the plurality of FIFOs when the second data is transferred from the second data transfer block to the plurality of FIFOs.