Patent ID: 8830411

Claim:
An array substrate comprising: a first pixel electrode forming a first capacitor with a first power line and a second capacitor with a second power line, the first power line and the second power lines extending along a gate line, the first and second power lines receiving voltages having different polarities, respectively, the first pixel electrode being electrically connected to a first data line; a second pixel electrode forming a fourth capacitor with the first power line and a fifth capacitor with the second power lines, the second pixel electrode being electrically connected to a second data line receiving a voltage having an opposite polarity to a voltage applied to the first data line; a first common electrode forming a third capacitor with the second power line, the first common electrode being electrically connected to the first power line; and a second common electrode forming a sixth capacitor with the first power line, the second common electrode being electrically connected to the second power line.