Patent ID: 7342318

Claim:
A semiconductor package, comprising: a first dielectric material layer formed with a plurality of openings penetrating the same; a conductive material applied in the openings of the first dielectric material layer; a first conductive layer formed on the first dielectric material layer and the conductive material, wherein the first conductive layer comprises a plurality of conductive traces; a second dielectric material layer applied over the first conductive layer, wherein a plurality of conductive vias are formed through the second dielectric material layer; a second conductive layer formed on the second dielectric material layer, and comprising a plurality of conductive traces, wherein each of the conductive traces of the second conductive layer has a terminal, and the conductive traces of the second conductive layer are electrically connected to the conductive traces of the first conductive layer by the conductive vias; at least one chip mounted on the second dielectric material layer and electrically connected to the terminals of the conductive traces of the second conductive layer; and an encapsulant for encapsulating the chip and the second conductive layer, with the first dielectric material layer and the conductive material being partly exposed from the encapsulant.