Patent ID: 7248514

Claim:
A semiconductor memory device comprising: a first memory array comprising a plurality of memory regions obtained by dividing the first memory array by one or more word lines; a second memory array comprising a plurality of memory sets, each of which corresponds to a memory region and has a predetermined number of memory groups corresponding to that memory region, wherein each memory group has a memory for storing a defective memory address that designates a defective memory included in the said corresponding memory region, and a redundant memory that becomes accessible when a memory address for accessing a memory in said corresponding memory region is input; a controlling unit for reading defective memory addresses from the memory set corresponding to a memory region on said first memory array and setting the redundant memories included in the same memory set to be accessible, when a memory address for accessing a memory in said memory region is input; and an access switching unit for judging whether or not an input memory address is an address of defective memory according to a comparison between the input memory address and defective memory addresses read out from said memory set in accordance with the input memory address, and switching an access operation so that the redundant memory included in the same memory group outputting an address of a defective memory is accessed instead of the defective memory when judging that the input memory address is the address of the defective; wherein said controlling unit executes processing for reading data from said first memory array, said second memory array, and said redundant memory in parallel when the memory address for accessing a memory on said first memory array is input.