Patent ID: 7912882

Claim:
An apparatus comprising: a Direct Digital Synthesizer (DDS) comprising: a Phase Locked Loop (PLL) multiplier configured to convert a system reference clock signal of a system reference clock frequency into DDS operation clock signal of a DDS operation clock frequency; a phase accumulator configured to operate using the DDS operation clock signal, accumulate a phase using a Frequency Tuning Word (FTW), and output an accumulated phase of a particular frequency; a phase-to-magnitude converter configured to operate using the DDS operation clock signal and generate a sinusoidal signal of the particular frequency having a magnitude corresponding to the accumulated phase of the particular frequency; and a Digital-to-Analog (DA) converter configured to operate using the DDS operation click signal from the PLL multipler and convert the sinusoidal signal of the particular frequency to an analog signal of a DDS output frequency, a band pass filter configured to pass the analog signal of the DDS output frequency from the DA converter over a particular frequency band of the DDS output frequency; and a comparator configured to transform the passed analog the signal into a square wave signal and output the square wave signal.