Patent ID: 7370161

Claim:
A multi-bank memory access arbiter in communication with a plurality of masters for receiving request information from the plurality of masters, storing write request information temporarily in a write buffer of the multi-bank memory access arbiter, and allowing the masters corresponding to the request information, which is received from the masters, to access a plurality of banks in communication with the multi-bank memory access arbiter, except a busy bank of the plurality of banks, and the temporarily stored write request information in the write buffer, in an access grant determination process, the multi-bank memory access arbiter comprising: a sub-arbiter that receives the request information from the masters, selects and outputs the write request information; the write buffer that stores the write request information temporarily; and a main arbiter that allows access grants to the masters corresponding to the request information for accessing the other banks except the busy bank in the request information output from the masters and to the write request information.