Patent ID: 8659450

Claim:
A system, comprising: an interface configured to: receive, for n=1, . . . , N where N is a length of a codeword, an array f(n); and receive, for n=1, . . . , N where N is a length of a codeword, an array g(n); and a processor configured to encode input data to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n), including by: in the event a previous codeword bit output is a one: in the event the input data is greater than or equal to an element in the array f(n) corresponding to a current bit index: outputting as a codeword bit a one; and updating the input data to be the input data minus the element in the array f(n) corresponding to the current bit index; and in the event the input data is less than the element in the array f(n) corresponding to the current bit index, outputting as the codeword bit a zero.