Patent ID: 6907585

Claim:
A semiconductor integrated circuit comprising: a logic circuit including having one or more flip-flops and one or more combinational circuits; and a test control circuit including, a control circuit configured to output a control signal for controlling connection states of the one or more flip-flops, and a pattern generation circuit configured to generate a test pattern for the logic circuit, wherein when the control signal is in a first state, each of the one or more flip-flops is connected to other flip-flops without passing through the one or more combinational circuits and transmits a test pattern generated from the pattern generation circuit to the other flip-flops, and wherein when the control signal is in a second state, each of the one or more flip-flops is connected to any of the one or more combinational circuits and outputs a stored test pattern to a connected combinational circuit, and wherein a phase of a clock signal to drive the control circuit advances further than a phase of a clock signal to drive the pattern generation circuit.