Patent ID: 8472199

Claim:
A solid state drive comprising: a circuit board having opposing first and second surfaces; a plurality of semiconductor chips attached to the first surface, the plurality of semiconductor chips including at least one memory chip and at least one stack of memory chips that are at least substantially glob top encapsulated, the at least one stack of memory chips including first, second and third stacks of memory chips, the first stack of memory chips including first and second memory chips and a third chip different from the first and second memory chips of the first stack of memory chips, the second stack of memory chips including first and second memory chips and a third chip different from the first and second memory chips of the second stack of memory chips, the third stack of memory chips including first and second memory chips and a third chip different from the first and second memory chips of the third stack of memory chips, the third chip of the first stack of memory chips being series-connected with the third chip of the second stack of memory chips, which is in turn further series-connected with the third chip of the third stack of memory chips; an interface connector within the solid state drive, the interface connector configured for connection to an end of a cable; and a controller in communication with at least a number of the plurality of semiconductor chips during operation, the number of semiconductor chips including the at least one memory chip, and the controller including an interface to receive, from a computer system via the interface connector, signals for processing within the solid state drive.