Patent ID: 7137564

Claim:
A communication protocol for multi-functional mini-memory cards; data being transferred through semi-duplex process and four bitstreams of data being transferred in parallel; a CLK signal being used as a base clock in data transfer; each clock has four bits of data being transferred in parallel, the four parallel data bits being indicated as D 0 , D 1 , D 2 , and D 3 ; in each bitstream, data being transferred as data packages; endpoints being as a data source and sink in a transmitting end and a receiving end, respectively; a data package includes start bits, package identification codes, communication endpoints; data length, payloads, package status codes, data formats; and end bits; wherein each package identification code has eight bits, four of which are identification codes and the other four of which are the same as the identification code, but arranged with an reverse order; the reverse identification code is added after the identification code, and each of the identification code and reverse identification code are transferred in one clock pulse, respective, and therefore, the package identification code is transferred in two clock pulses.