Patent ID: 8687424

Claim:
A flash memory comprising: a p-well region; and a plurality of strings formed on the p-well region, wherein each of the strings includes a plurality of memory cells connected in series, and the plurality of memory cells are formed on the p-well region and share the p-well region, wherein the memory cells are configured to be selectively programmed in response to a program voltage applied to a selected string and a body bias voltage independently connected to the p-well region, and all memory cells constituting a single page are configured to be erased in response to an erase voltage applied through a word line and the body bias voltage, wherein each of the strings comprises a string selection transistor electrically connected to a bit line, the memory cells are electrically connected to the string selection transistor, and a ground selection transistor is electrically connected to the memory cells, wherein the flash memory is configured such that, during a program operation, the string selection transistor is turned off, and electrons accumulated in response to the body bias voltage applied to the p-well are injected by performing hot carrier injection in response to the program voltage applied through the word line, and wherein the flash memory is further configured such that, during an erase operation, holes accumulated in response to the body bias voltage applied to the p-well are injected by performing hot carrier injection in response to the erase voltage applied through the word line.