Patent ID: 7196564

Claim:
A phase interpolation system, comprising: an input stage that provides first and second modulated input signals having selected first and second relative phase angles; and a weighting system configured to steer a first portion of the first modulated input signal to an output and a second portion of the first modulated input signal to an internal first node, the weighting system also being configured to steer a first portion of the second modulated input signal to the output and a second portion of the second modulated input signal to the first node, the first portion of the first and second modulated input signals being summed at the output to provide an interpolated output signal having a phase angle that is between the first and second phase angles; a first weighting network configured to selectively weight the first modulated input signal by steering the first portion of the first modulated input signal through a first weighting stage to the output based on a first control signal, and by steering the second portion of the first modulated input through a second weighting stage to the first node based on a second control signal; a second weighting network configured to selectively weight the second modulated input signal by steering the first portion of the second modulated input signal through a third weighting stage to the output based on the second control signal and by steering the second portion of the second modulated input through a fourth weighting stage to the first node based on the first control signal; wherein each of the first weighting stage and the second weighting stage further comprises a plurality of transistor devices that are selectively activated to conduct current corresponding to the first and second portions of the first modulated input signal therethrough based on the first control signal and the second control signal, respectively; wherein each of the third weighting stage and the fourth weighting stage further comprises a plurality of transistor devices that are selectively activated to conduct current corresponding to the first and second portions of the second modulated input signal therethrough based on the second control signal and the first control signal, respectively; wherein the first control signal comprises multi-bit control signal provided to activate M of the N transistor devices in each of the first weighting stage and the fourth weighting stage, where M is a positive integer less than or equal to N and N is a positive integer denoting the number of transistor devices; and wherein the second control signal comprises a multi-bit control signal provided to activate N minus M of the transistors devices in each of the second weighting stage and the third weighting stage in a complementary manner relative to the first weighting stage and the fourth weighting stage, such that a constant number of 2*N transistor devices remain activated over a range of interpolator settings defined by the first and second control signals.