Patent ID: 7388238

Claim:
A semiconductor integrated circuit device comprising: a logic circuit including at least one N channel type MOS transistor and at least one P channel type MOS transistor, drains of each of said at least one N channel type transistor and each of said at least one P channel type MOS transistor being coupled to each other; and a switch circuit for keeping a first source line to which a source electrode of each of the at least one P channel type MOS transistor is connected at a first potential in a first condition, and keeping said first source line at a second potential in a second condition, wherein a source electrode of said at least one N channel type MOS transistor is coupled to a second source line to which a source electrode of each of the at least one N channel type MOS transistor is connected, wherein said first source line is coupled to said switch circuit; and wherein an insulating layer for use in a gate of either of said at least one N channel type MOS transistor or said at least one P channel type MOS transistor has a thickness of 4 nm or less.