Patent ID: 6995459

Claim:
A semiconductor package comprising: a generally planar die paddle defining opposed top and bottom surfaces and multiple peripheral edge segments; a plurality of first leads defining opposed top and bottom surfaces, the first leads being segregated into at least two sets which extend along respective ones of the peripheral edge segments of the die paddle in spaced relation thereto; a plurality of second leads defining opposed top and bottom surfaces, the second leads being segregated into at least two sets which extend along respective ones of the sets of the first leads in spaced relation thereto; a plurality of third leads defining opposed top and bottom surfaces, the third leads being segregated into at least two sets which each extend between a respective pair of the sets of the first and second leads; a first semiconductor die attached to the top surface of the die paddle and electrically connected to at least one of each of the first, second and third leads; a package body at least partially encapsulating the first, second and third leads and the semiconductor die such that at least the bottom surface of the die paddle and the bottom surfaces of the first, second and third leads are exposed in the package body; at least two inner recesses disposed within the package body, each of the inner recesses being located between one set of the first leads and a respective one of the peripheral edge segments of the die paddle; and at least two outer recesses disposed within the package body, each of the outer recesses being located between one set of the second leads and a respective set of the third leads.