Patent ID: 7688324

Claim:
A graphics processor comprising: a memory controller, coupled to a memory, to control access to the memory; a host interface, coupled to the memory controller and coupled to a central processing unit (CPU), to receive requests from the CPU to access the memory; an audio processor coupled to the memory controller; a video capture and scaling unit coupled to the memory controller; a graphics acceleration unit coupled to the memory controller; and a video display controller coupled to the memory controller; wherein the memory controller coordinates access to the memory for at least each of video data, audio data and program data according to a multi-stage arbitration scheme, where at least one stage of the multi-stage arbitration scheme uses a priority scheme that is different from a previous stage of the multi-stage arbitration scheme to select between competing memory transaction requests, wherein the previous stage uses a client interface configured to control storage of one or more memory transaction requests in one or more entries to a buffer such that at most one memory transaction request for each type of a plurality of memory transaction request types is stored by the buffer, and wherein the at least one stage of the multi-stage arbitration scheme includes: a) multiple priority levels for each of the plurality of memory transaction request types; and b) wherein the at least one stage enables each of a subset of the plurality of the memory transaction request types to be elevated to a higher priority level within the at least one stage if a corresponding memory transaction request asserts a higher priority as a result of a memory requirement threshold being passed.