Patent ID: 8269277

Claim:
A semiconductor device, comprising: a source region near a working surface of a semiconductor region; a drain region near the working surface and laterally offset from the source region; a gate located above the working surface and located laterally between the source and drain regions; a well region extending from the drain region laterally towards the source region, and comprising at least a portion of the active region of the semiconductor device when the semiconductor device is biased into a conducting mode; and a top diffusion region near the working surface within the well region and comprising: a center portion located laterally between the source and drain regions; a drain-facing portion located adjacent to the center portion on a lateral edge of the center portion facing the drain region; and a source-facing portion located adjacent to the center portion on a lateral edge of the center portion facing the source region, the center portion laterally wider than the source- and drain-facing portions; and wherein the semiconductor region and top diffusion regions include a first conductivity type, and the source, drain and well regions include a second conductivity type.