Patent ID: 7923770

Claim:
A method of fabricating a memory device, comprising: forming a charge storage structure including a gate dielectric structure, a charge trapping layer and a second oxide layer from bottom to top; forming a gate conductive layer above the charge storage structure; and patterning the gate conductive layer and at least a part of the charge storage structure, such that the cross section of a patterned charge storage structure including a patterned gate dielectric structure, a patterned charge trapping layer and a patterned second oxide layer becomes approximately a trapezoid or a trapezoid analogue with the shorter side near the gate conductive layer and the longer side near the substrate; and during an oxidation process, an oxide encroachment is formed located at a region between the longer side of the charge storage structure and the substrate and not covered by the gate conductive layer but not extend under the gate conductive layer.