Patent ID: 8879303

Claim:
A memory circuit, comprising: a static random access memory including N banks of memory cells, each bank having M columns, where M and N are positive integers; rows of M sense amplifiers, each row of the M sense amplifiers placed between two banks of the memory cells, each row of the M sense amplifiers coupled to a sense amplifier control circuit and a local input/output circuit, each column of the M sense amplifiers corresponding to a bit of the memory cell, the bit having corresponding global read lines; a global read precharge tracking control circuit controlling a precharge of the global read lines using a track dummy global read line signal; a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits; and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle; wherein a dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the static random access memory forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.