Patent ID: 7915665

Claim:
A non-volatile memory cell including: a semiconductor body; a first memory-transistor well disposed within the semiconductor body; a first memory transistor formed within the first memory-transistor well and including spaced-apart source and drain regions; a first switch-transistor well disposed within the semiconductor body to a first side of the first memory-transistor well and electrically isolated from the first memory-transistor well; a first switch transistor formed within the first switch-transistor well and including spaced-apart source and drain regions; a second switch transistor formed within the first switch-transistor well and including spaced-apart source and drain regions; a first floating gate insulated from and self aligned with the source and drain regions of the first memory transistor and the first and second switch transistor; and a first control gate disposed above and self aligned with respect to the first floating gate and with the source and drain regions of the first memory transistor and the first and second switch transistors.