Patent ID: 8319292

Claim:
A semiconductor device comprising: (a) a memory cell array with a plurality of memory cells arranged in a matrix; (b) a word driver operable to select a specified row of the memory cell array; and (c) a column selecting unit operable to select a specified column of the memory cell array, wherein the word driver includes: an inverter circuit including: a first p-channel type MISFET having a first p-gate electrode; and a first n-channel type MISFET having a first n-gate electrode, wherein the first p-channel type MISFET and the first n-channel type MISFET are coupled in series with each other between a power supply line supplying power supply potential and a reference line supplying reference potential, and the first p-gate electrode and the first n-gate electrode are coupled electrically, wherein the inverter circuit further includes: a second p-channel type MISFET having a second p-gate electrode and coupled in parallel with the first p-channel type MISFET, the second p-gate electrode being coupled electrically with the first p-gate electrode, and wherein a threshold voltage of the first p-channel type MISFET and a threshold voltage of the second p-channel type MISFET are different from each other.