Patent ID: 7262108

Claim:
A method of forming an integrated circuit device, the method comprising: forming an insulating layer on an integrated circuit substrate; forming a first conductive layer on the insulating layer wherein the first conductive layer comprises a first material; forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer wherein the second conductive layer comprises a second material different than the first material; forming a hole in the second conductive layer so that portions of the first conductive layer are exposed through the hole; and after forming the hole in the second conductive layer patterning the first and second conductive layers so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed though the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole; wherein patterning the first and second conductive layers further comprises maintaining portions of the first and second conductive layers to define a conductive line spaced apart from the portion of the first conductive layer previously exposed through the hole; wherein patterning the first and second conductive layers includes forming a single photoresist pattern on portions of the first conductive layer previously exposed through the hole and on portions of the first and second conductive layers defining the conductive line, and removing portions of the first and second conductive layers exposed by the single photoresist pattern before forming the single photoresist pattern, forming a capping layer on the second conductive layer and on portions of the first conductive layer exposed through the hole, wherein patterning the first and second conductive layers comprises patterning the capping layer.