Patent ID: 7485564

Claim:
A method of forming a contact electrode for a semiconductor chip, said method comprising the steps of: forming a passivation layer upon a metal bonding pad surface; forming a tapered opening in said passivation layer that exposes said metallic bonding pad surface to define a location for a solder bump connection, wherein at least a portion of a tapered sidewall of said passivation layer around said tapered opening overlies said metal bonding pad surface; forming a barrier material liner directly upon said tapered sidewall of said patterned passivation layer and said metal bonding pad surface, said barrier material liner conforming to a surface of said patterned passivation layer including said tapered sidewall; filling said barrier material lined tapered opening with a conductive material layer and forming a layer of said conductive material atop said formed barrier material liner above said passivation layer surface; removing by polishing a portion of said conductive material layer and barrier material liner above said passivation surface to form a conductive material plug having a surface that is substantially coplanar with a surface of a final passivation layer and filling said tapered opening, wherein said polishing stops on a portion of said barrier material liner; forming a diffusion barrier layer patterned atop said substantially coplanar surface of said conductive material plug; providing solder material upon a surface of said diffusion barrier layer; and processing the solder material to form said solder bump connection atop said diffusion barrier layer while avoiding a masking step, said method enabling a chip having reduced pitch and increased mechanical stability of said solder bump connection.