Patent ID: 8621134

Claim:
A method of storage tiering with reduced use of Dynamic Random Access Memory (DRAM) for header overhead in mapping structure of said DRAM comprising: tiering a plurality of data storage devices into fast storage regions and slow storage regions such that data is not duplicated between said fast storage regions and said slow storage regions; mapping Logical Block Addresses (LBAs) of said fast storage regions and said slow storage regions into one tiered virtual drive such that said LBAs track the location of data within said one tiered virtual drive; assigning headers only for data in said fast storage regions and not for data in said slow storage regions; mapping in said DRAM only headers for data in said fast storage regions; moving cold data to said slow storage regions and hot data to said fast storage regions on a one-to-one basis such that infrequently accessed cold data in said fast storage region is moved to said slow storage regions and frequently accessed hot data in said slow storage regions is moved to said fast storage regions; and swapping LBAs of said hot data and said cold data of said one-to-one basis move in said header of said hot data in said fast storage region.