Patent ID: 8724363

Claim:
An anti-fuse memory ultilizing a coupling channel, comprising: a substrate, wherein an isolation structure is disposed in the substrate; a first doped region of a second conductive type disposed in the substrate, wherein a coupling channel region is defined between the first doped region and the isolation structure; a coupling gate disposed on the substrate between the first doped region and the isolation structure, and the coupling gate being adjacent to the doped region; a gate dielectric layer disposed between the coupling gate and the substrate; an anti-fuse gate disposed on the substrate between the coupling gate and the isolation structure, wherein the anti-fuse gate and the coupling gate have a space therebetween; and an anti-fuse layer disposed between the anti-fuse gate and the substrate, wherein the substrate is a substrate of a first conductive type, and the coupling channel between the coupling gate and the anti-fuse gate is formed by the substrate of the first conductive type.