Patent ID: 8386869

Claim:
A system for processing a signal, comprising: a defect detector configured to receive an input signal and to determine a location of a defect portion within the input signal and an amplitude of the defect portion, wherein: the defect detector is configured to determine the location of the defect portion within the input signal by performing maximum likelihood sequence detection (MLSD) using a trellis; the trellis includes a defect state that is associated with a sample in the input signal being defective and a normal state that is associated with a sample in the input signal being normal; and the defect detector is configured to determine the location of the defect portion within the input signal by permitting a transition from the defective state to the normal state only if the defective state has been consecutively occupied more than a specified number of times; a signal hardware processor configured to generate an adjusted signal by adjusting the amplitude of the defect portion using the determined location of the defect portion and the determined amplitude of the defect portion, wherein the signal processor is configured to perform the adjustment prior to error correction decoding; and an error correction decoder configured to perform error correction decoding on the adjusted signal.