Patent ID: 7807990

Claim:
A semiconductor device comprising: a substrate: a p-channel MIS transistor including: an n-type semiconductor region formed on the substrate; a p-type source region and a p-type drain region formed to face each other in the n-type semiconductor region; a first insulating layer formed on the n-type semiconductor region between the p-type source region and the p-type drain region, and containing silicon and oxygen, the first insulating layer having a first region; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, the second insulating layer having a second region, the second region being in a 0.3 nm range in a film thickness direction from a interface between the first insulating layer and the second insulating layer, the first region being in a 0.3 nm range in a film thickness direction from the interface between the first insulating layer and the second insulating layer, and each of the first and second regions including aluminum atoms with a concentration of 1×10 20 cm −3 or more to 1×10 22 cm −3 or less; and a first gate electrode formed on the second insulating layer, and an n-channel MIS transistor including: a p-type semiconductor region formed on the substrate and insulated from the n-type semiconductor region; an n-type source region and an n-type drain region formed to face each other in the p-type semiconductor region; a third insulating layer formed on the p-type semiconductor region between the n-type source region and n-type drain region, and containing silicon and oxygen; a fourth insulating layer formed on the third insulating layer, and containing hafnium, silicon, oxygen, and nitrogen; and a second gate electrode formed above the fourth insulating layer.