Patent ID: 7539043

Claim:
A semiconductor memory device comprising: a memory cell including a source layer, a drain layer, and a floating body provided between the source layer and the drain layer and being in an electrically floating state, the memory cell storing therein data according to number of majority carriers accumulated in the floating body; a word line connected to a gate of the memory cell, and extending in a first direction; a bit line connected to the drain layer of the memory cell, and extending in a second direction different from the first direction; a source line connected to the source layer of the memory cell, and extending in the first direction; a sense amplifier connected to the bit line, and sensing data from the memory cell selected by the bit line and the word line; a driver applying a voltage to the word line to form a channel in the memory cell and shifting a voltage of the source line in a voltage direction opposite to a transition direction of the voltage of the word line when first data indicating that the number of the majority carriers is small is written to the memory cell.