Patent ID: 7772091

Claim:
A manufacturing method of a semiconductor apparatus, said method comprising: a semiconductor chip formation step of forming a plurality of semiconductor chips in a plurality of semiconductor chip formation regions of a semiconductor substrate; an alignment pattern formation step of forming alignment patterns in scribe regions placed between the semiconductor chip formation regions of the semiconductor substrate; an internal connection terminal formation step of forming internal connection terminals on electrode pads of the semiconductor chips; an insulating layer formation step of forming an insulating layer having through grooves on the semiconductor substrate on which the semiconductor chips are formed in a state that the through grooves are opposed to the scribe regions of the semiconductor substrate; a metal layer formation step of forming a metal layer on the insulating layer, the metal layer having through grooves aligned with the through grooves formed on the insulating layer; a wiring pattern formation step of aligning formation positions of wiring patterns to be electrically connected to the internal connection terminals based on the alignment patterns and patterning the metal layer based on the formation positions and forming the wiring patterns; and a cutting step of cutting the semiconductor substrate of a portion corresponding to the scribe regions exposed by the through grooves of the insulating layer after the wiring pattern formation step.