Patent ID: 6882333

Claim:
A display apparatus comprises: pixel electrodes arranged like a matrix; display elements which operate according to the voltage of the pixel electrode; an X driver for supplying an X signal to X signal line arranged in the column direction; an Y driver for supplying an Y signal to Y signal line arranged in the row direction; a liquid crystal drive voltage supplying circuit for supplying a liquid crystal drive voltage to a liquid crystal drive voltage line arranged in a column direction; an XY calculating circuit provided at the intersection parts of the X signal line and the Y signal line and connected to the X signal line and the Y signal line for calculating and outputting the X and Y signals; a signal comparator for comparing an output of the XY calculating circuit with a reference voltage and outputting a first voltage when the output of the XY calculating circuit is higher than the reference voltage, and a second voltage when lower than that; a switch for controlling the connection of the pixel electrode and the liquid crystal drive voltage line, based on the output of the signal comparator; n-gradation approximation calculating circuit for dividing the pixels into pixel blocks of N rows×N′ columns, and converting the gradation level of each pixel of each block into n-gradation approximation picture signal approximated to n values less than N×N′, and a signal control circuit for controlling the X driver, the Y driver, and liquid crystal drive voltage supplying circuit, according to the n-gradation approximation picture signal, wherein n is two, the XY calculating circuit comprises two capacitors connected in series between the X signal line and the Y signal line, wherein the voltage of the connection node of two capacitors is input to the signal comparator as an output value, wherein the voltage VYMAX applied to Y signal line is a high voltage enough to allow the output of the XY arithmetic circuit to be higher than the reference voltage of the signal comparator regardless of the voltage applied to X signal line, wherein the voltage VYMIN applied to Y signal line is a high voltage enough to allow the output of the XY arithmetic circuit to be lower than the reference voltage of the signal comparator regardless of the voltage applied to X signal line, wherein VYMAX is applied to Y signal lines of the first to N-th rows, and VYMIN is applied to Y signal lines other than the first to Nth row, for the first selection period, wherein the voltages VY 1 <VY 2 < . . . <VYN are applied to Y signal lines of the 1 st to N-th rows, VYMAX is applied to Y signal lines of the (N+1)-th to 2N-th rows, and VYMIN is applied to Y signal lines other than the first to 2Nth rows, for the second selection period, and wherein, for the i-th selection period, the voltages VY 1 <VY 2 < . . . <VYN are applied to Y signal lines of the ((i−2)×N+1)-th to ((i−1)×N)-th rows, VYMAX is applied to Y signal lines of the ((i−1)×N+1)-th to (i×N)-th rows, and VYMIN is applied to Y signal lines other than the ((i−2)×N+1)-th to (i×N)-th rows.