Patent ID: 6946704

Claim:
A semiconductor memory device comprising: a plurality of first wirings, each of which is located along a first direction with a first wiring pitch; a plurality of chalcogenide material layers, each of which is located along said first direction; a plurality of second wirings, each of which is connected with a corresponding one of said chalcogenide material layers, and is located over said corresponding one of said chalcogenide material layers and along said first direction; and a plurality of vertical transistors, each of which is formed over said corresponding one of said first wirings and under a corresponding one of said second wirings and is comprised of a source region, a drain region, a channel region sandwiched between said source region and said drain region, a gate insulating film formed on all sides of said channel region and a gate electrode formed on said gate insulating film and surrounding said all sides of said channel region, wherein said drain region is electrically connected with said corresponding one of said second wirings through corresponding one of said chalcogenide material layers, wherein said source region is electrically connected with said corresponding one of said first wirings, wherein gate electrodes of two adjacent ones of said vertical transistors in a second direction, which intersects perpendicularly with said first direction, are connected with each other, and wherein gate electrodes of two adjacent ones of said vertical transistors in said first direction are separated from each other.