Patent ID: 6848035

Claim:
A semiconductor device, comprising: a plurality of memory banks, each including a plurality of memory cells; a cache memory that retains information read from said plurality of memory banks, the cache memory including a plurality of entries; and a plurality of data input/output nodes connected to an internal data bus connecting said plurality of memory banks to said cache as well as to an external data bus used to input/output information thereto/therefrom; wherein each of said plurality of entries comprises a data part that stores information read from some of said plurality of memory banks, and a tag part that stores address information corresponding to the information stored in said data part; said data part has a plurality of sub lines; said tag part has a plurality of first flags used to denote whether or not information stored in said plurality of sub lines is valid and a plurality of second flags used to denote whether or not information stored in said plurality of sub lines should be written newly in said memory banks; and wherein A=N·B is satisfied where the number of said sub lines is N, the data width of said internal data bus is A, and the data width of said external data bus is B.