Patent ID: 8824231

Claim:
A dynamic random access memory device, comprising: a first array of memory cells arranged in rows and columns, the first array comprising a first plurality of bitlines, each bitline being coupled to a column of memory cells in the first array; a second array of memory cells arranged in rows and columns, the second array comprising a second plurality of bitlines, each bitline being coupled to a column of memory cells in the second array; a plurality of sense amplifiers, each sense amplifier being selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines; a voltage supply having a voltage VBA corresponding to a bitline precharge voltage, the voltage supply being selectively connectable to each bitline of the first and second pluralities of bitlines; and logic for selectively connecting each bitline of the first plurality of bitlines and the complementary bitline of the second plurality of bitlines to one of a sense amplifier and the voltage supply during a read operation, such that each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply, wherein: the logic is responsive to at least one input signal to: connect every third bitline in the first and second arrays of memory cells to the voltage supply; and connect the remaining bitlines in the first and second arrays of memory cells to corresponding sense amplifiers.