Patent ID: 8872682

Claim:
An analog-to-digital conversion loop to generate a digital output signal corresponding to a low-pass filtered replica of an analog input signal, comprising: an analog adder to receive said input analog signal and an analog feedback signal and to generate an analog error signal corresponding to a difference between the analog input signal and the analog feedback signal; a circuit to receive as input the analog error signal and to output both an absolute value error signal and a sign value, the absolute value error signal being an analog signal having the absolute value of the analog error signal and the sign value indicating whether the analog error signal is positive or negative; an analog-to-digital converter to receive the absolute value error signal and to generate a corresponding digital error signal, the analog-to-digital converter having a nonlinear input-output conversion characteristic defining a larger quantization step the more the absolute value error signal differs from a null value, the digital error signal having N bits and the analog-to-digital converter comprising no more than N comparators; a digital integrator to receive the digital error signal and the sign value, and to generate said digital output signal corresponding to a time integration of said digital error signal; a digital-to-analog converter to receive said digital output signal and to generate said analog feedback signal as analog replica of the digital output signal.