Patent ID: 7545022

Claim:
An integrated circuit device comprising: a capacitor array comprising a first plurality of unit capacitors and a second plurality of unit capacitors, wherein a total number of unit capacitances in the capacitor array is no less than six, and wherein the first and the second pluralities of unit capacitors are placed in an alternating pattern in each row and each column; wherein each unit capacitor in the first plurality of unit capacitors comprises: a first common node comprising a first conductive bus and a plurality of first fingers connected to the first conductive bus; a plurality of second fingers, each being between and electrically insulated from two of the first fingers; and a second conductive bus interconnecting the plurality of second fingers; wherein each unit capacitor in the second plurality of unit capacitors comprises: a second common node comprising a third conductive bus and a plurality of third fingers connected to the third conductive bus; a plurality of fourth fingers, each being between and electrically insulated from two of the third fingers; and a fourth conductive bus interconnecting the plurality of fourth fingers; and wherein the first common nodes of the first plurality of unit capacitors are interconnected, the second common nodes of the second plurality of unit capacitors are interconnected, the second conductive buses of the first plurality of unit capacitors are interconnected, and the fourth conductive buses of the second plurality of unit capacitors are interconnected.