Patent ID: 7138340

Claim:
A method for fabricating a semiconductor device, comprising the steps of: forming a plurality of conductive structures on a substrate having an impurity diffusion region, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer and an etch stop layer on the plurality of conductive structures, wherein the first nitride layer is denser than the second nitride layer; forming an inter-layer insulation layer on the etch stop layer; partially removing the inter-layer insulation layer through a planarization process, wherein a portion of the inter-layer insulation layer having a predetermined thickness remains on the etch stop layer to protect the second nitride layer during the planarization process; forming a photoresist pattern on the inter-layer insulation layer; performing a self-aligned contact (SAC) etching process to selectively etch the inter-layer insulation layer, the second nitride layers, and the oxide layer by using the photoresist pattern as an etch mask until the first nitride layer is exposed to thereby form a contact hole; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the impurity diffusion region in the substrate.