Patent ID: 7425478

Claim:
A method of fabricating a semiconductor device, comprising: forming a gate insulating layer on a semiconductor substrate; forming a first gate electrode layer on the gate insulating layer; forming a dummy gate electrode layer on the first gate electrode layer; selectively removing the dummy gate electrode layer and the first gate electrode layer to form proto-gate electrodes each having the dummy gate electrode layer stacked on the first gate electrode layer; forming an embedded layer between the proto-gate electrodes; removing the dummy gate electrode layer of the proto-gate electrodes to form a space region on the first gate electrode layer; extending the space region to a prescribed width by removing the portion of the embedded layer surrounding the space region; forming a second gate electrode layer in the extended space region to form two-step gate electrodes having the second gate electrode layer stacked on the first gate electrode layer, wherein the gate length of the second gate electrode layer is longer than the gate length of the first gate electrode layer; removing the embedded layer; forming extension regions in the semiconductor substrate by introducing impurities employing the two-step gate electrodes as a mask; forming a side-wall insulating layer on the side wall of the two-step gate electrodes; and forming source-drain regions in the semiconductor substrate by introducing impurities employing the two-step gate electrodes and the side-wall insulating layer as a mask.