Patent ID: 7590719

Claim:
An information processing system for a host computer having a plurality of adapters, comprising: a storage device having a plurality of host side ports configured to be connected to the host computer; a plurality of processors for controlling said plurality of host side ports; a cache memory, connected to said plurality of host side ports, for temporarily holding data in response to commands from said host computer; a shared memory for accumulating information relating to an internal composition of said storage device for reference by said plurality of processors; and an internal management device for outputting said compositional information to an external device; and a management server connected to said internal management device and configured to be connected to the host computer, by a communications circuit; wherein communications paths are established between said plurality of host side ports the plurality of adapters of the host computer; wherein said storage device accumulates information relating to said communications paths, in said shared memory, and said internal management device refers to said information relating to communications paths and judges whether or not communications paths from the plurality of adapters to said cache memory can be secured in the event of at least one of said processors being blocked off; and wherein, when a judgment result of said internal management device is that said communications paths can be secured, then said internal management device sends a notification indicating that it is possible to block off the processors for which said judgment was made, to said management server, via said communications circuit.