Patent ID: 8315079

Claim:
A non-volatile memory device, comprising: a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line, each resistive memory units having a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit; a plurality of bit lines, each bit line being coupled to the first end of one of the resistive memory cells; a plurality of select transistors, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit; first and second global word lines, each global word line being coupled to a control terminal of at least one select transistor; and first and second source lines, each source line being coupled to a source terminal of at least one select transistor, wherein the memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.