Patent ID: 7923326

Claim:
A method for manufacturing a memory device comprising: depositing an insulating layer on a semiconductor substrate; forming a first trench in the semiconductor substrate by etching the insulating layer and the semiconductor substrate to a predetermined depth; forming a tunneling oxide layer in the first trench; forming a floating gate layer on the tunneling oxide layer inside the first trench; forming a dielectric layer on the floating gate layer; forming a control gate layer in the first trench on the dielectric layer; forming an oxide layer on the control gate layer; forming a second trench by removing central portions of the oxide layer, the control gate layer, the dielectric layer, the floating gate layer and the tunneling oxide layer in the first trench; forming a buffer dielectric layer on a sidewall of the second trench; forming a source junction by implanting impurity ions into the semiconductor substrate below the second trench; forming a source electrode in the second trench, electrically connected to the source junction; and forming a drain junction by implanting impurity ions into exposed areas of the semiconductor substrate.