Patent ID: 8035766

Claim:
A method of forming an array substrate having a color filter-on-thin film transistor (COT) structure for a liquid crystal display device, comprising: forming a gate line on a substrate along a transverse direction, a gate pad at one end of the gate line, and a gate electrode extending from the gate line; forming a first gate insulating layer on the substrate to cover the gate line, the gate pad, and the gate electrode; forming an active layer of intrinsic amorphous silicon and an ohmic contact layer of extrinsic amorphous silicon layer in series on the first gate insulating layer over the gate electrode; forming a data line, a data pad, a source electrode, and a drain electrode, the data line disposed perpendicularly crossing the gate line and defining a pixel region, the data pad disposed at one end of the data line, the source electrode extending from the data line on a first portion of the ohmic contact layer, and the drain electrode spaced apart from the source electrode on a second portion of the ohmic contact layer to form the thin film transistor; forming a second insulating layer over an entire surface of the substrate to cover the thin film transistor; forming a black matrix on the second insulating layers to cover the thin film transistor, the gate line, and the data line except a first portion of the drain electrode; forming a third insulating layer over an entire surface of the substrate to cover the black matrix; patterning the first, second, and third insulating layers to expose the first portion of drain electrode; forming a first transparent electrode layer over an entire surface of the substrate to cover the patterned third insulating layer and contacting the exposed portion of the drain electrode; forming a color filter on the first transparent electrode layer within the pixel region; forming a second transparent electrode layer over an entire surface of the substrate to cover the color filter and the first transparent electrode layer; patterning the first and second transparent electrode layers to form first and second pixel electrodes; and patterning portions of the first, second, and third insulating layer over the gate and data pads to form gate and data pad contact holes, respectively, after forming the first and second pixel electrodes.