Patent ID: 8131945

Claim:
A data caching method for reducing cross-interrogation latency in a computer system in a processor in communication with a high-speed buffer memory comprising an L1 cache memory and an L2 cache memory, said method comprising the steps of: copying data needed by said processor from a cache line in said L2 cache memory into a cache line in said L1 cache memory; copying said data needed by said processor from said L1 cache memory into a register in said processor, wherein said L2 cache memory includes an indication that said cache line stored in said L1 cache memory is owned; responding to said cache line in said L1 cache memory aging out by sending a signal updating said associated L2 cache memory to indicate that said cache line that aged out of said L1 cache memory is disowned; and updating said L2 cache memory upon receipt of said signal to indicate that said cache line in said L1 cache memory is disowned.