Patent ID: 8094494

Claim:
An operation method for a memory including a plurality of memory cells, comprising steps of: performing a first reading operation on the memory cells by applying a reference voltage; checking if a first total number of a first logic state in the first reading operation is correct or not; moving the reference voltage if the first total number of the first logic state in the first reading operation is not correct; performing a second reading operation on the memory cells by applying the moved reference voltage; checking if a second total number of the first logic state in the second reading operation is correct or not; comparing the first total number of the first logic state in the first reading operation with the second total number of the first logic state in the second reading operation if the second total number of the first logic state in the second reading operation is not correct; and stopping the moving the reference voltage step if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation, and storing the moved reference voltage as a target reference voltage.