Patent ID: 8315100

Claim:
A method of reading a single bit in a memory cell of a memory array, the method comprising: providing a memory array comprising: a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising: a high voltage access transistor; a floating gate memory transistor electrically connected to the access transistor; and a coupling capacitor electrically connected to the memory transistor; a first set of word lines each electrically connected to the coupling capacitor in each of the memory cells in a respective row; a second set of word lines each electrically connected to the access transistor in each of the memory cells in a respective row; a first set of bit lines each electrically connected to the access transistor in each of the memory cells in a respective column; a second set of bit lines each electrically connected to the memory transistor in each of the memory cells in a respective column, the second set of bit lines each electrically connected together; a plurality of column address transistors each electrically connected to a bit line in the first set of bit lines; a single voltage supply point electrically connected to the second set of bit lines; a program charge pump electrically connected to the voltage supply point; and an erase charge pump electrically connected to the voltage supply point; applying a first voltage to a bit line, in the second set of bit lines, connected to the memory transistor in the memory cell to be read; applying a second voltage to a word line, in the first set of word lines, connected to the capacitor in the memory cell to be read, the second voltage being greater than the first voltage; grounding a word line, in the second set of word lines, connected to the access transistor in the memory cell to be read; grounding word lines, in the first set of word lines, not connected to the memory cell to be read; grounding word lines, in the second set of word lines, not connected to the memory cell to be read; and activating a column address transistor in a column supporting the memory cell to be read.