Patent ID: 8594322

Claim:
An encoding/decoding apparatus, comprising: a central processing unit; and an encryption/decryption accelerator coupled to the central processing unit and directed by finite state machine logic, the encryption/decryption accelerator including: an input for input data to be encrypted/decrypted; an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data; an output for encrypted/decrypted data coupled to said arithmetic logic unit; a logic circuit coupling said input, said arithmetic logic unit, and said output, the logic circuit defining, through multiplexer circuitry, encryption/decryption paths for said input data, wherein the logic circuit includes a first terminal arranged to receive first command signals to select a first encryption/decryption path via the multiplexer circuitry and second command signals to select a second encryption/decryption path via the multiplexer circuitry; and a memory to store computer programs, each computer program representative of a corresponding encryption/decryption mode of operation, each computer program including instructions to select corresponding operations performed by the arithmetic logic unit, said memory configurable to periodically memorize a further computer program relating to a different mode of operation after the encryption/decryption accelerator is in operation, the further computer program receivable from outside the accelerator.