Patent ID: 7965481

Claim:
A high voltage tolerance circuit, comprising: a first transistor, a source and a body of the first transistor being coupled to a ground, a gate of the first transistor receiving a control signal, a drain of the first transistor being coupled to a first node; a second transistor, a source and a body of the second transistor being coupled to an I/O pad, a gate of the second transistor receiving the control signal, a drain of the second transistor being coupled to the first node; a third transistor, a source and a body of the third transistor being coupled to a second node, a gate of the third transistor being coupled to the first node, a drain of the third transistor being coupled to a power supply; and a latch-up device coupled between the second node and the I/O pad; wherein the first transistor is an N-type MOS transistor, and the second transistor and the third transistor are P-type MOS transistors.