Patent ID: 8466451

Claim:
A field-effect transistor (FET) inverter, comprising: a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant, and wherein the nanowire channels in any given one of the device layers have a pitch of from about 10 nm to about 200 nm, and wherein the device layers are separated from one another in the stack by in-situ doped sacrificial layers which are present in the stack between the source regions and the drain regions of the device layers but not between the nanowire channels in the stack; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers.