Patent ID: 8264891

Claim:
A non-volatile memory device including a semiconductor substrate and comprising: an array of memory cells divided into a plurality of erase units, wherein each one of the plurality of erase units includes a group of memory cells arranged according to a contiguous set of word lines and capable of being erased during a single erase operation, and an erase unit among the plurality of erase units comprises a first inner erase unit arranged according to a contiguous first subset word line in the set of word lines, and a second inner erase unit arranged according to a contiguous second subset of word line in the set of word lines; a first well region disposed in the semiconductor substrate and containing memory cells of the first inner erase unit connected to the first subset of word lines, and a second well region disposed in the semiconductor substrate and containing memory cells of the second inner erase unit connected to the second subset of word lines, wherein the first and second well regions are electrically isolated within the semiconductor substrate.