Patent ID: 7269029

Claim:
A test board for holding an integrated circuit comprising: a substrate comprising at least one layer having a first conductive voltage plane on a first surface thereof, a second conductive voltage plane on a second surface thereof opposite said first surface and at least one intermediate conductive layer isolated from said first voltage plane and from said second voltage plane; at least one contact array comprising a set of contacts adapted to make electrical contact with said integrated circuit, formed on said first voltage plane and making electrical contact with said first voltage plane; at least one terminal array having a set of electrical terminals disposed on at least one of said first surface and said second surface and making electrical contact with a transverse conductive element formed from said intermediate conductive layer; a first set of vertical conductive structures extending from a member of said contact array to a corresponding member of a corresponding contact array in said second conductive voltage plane and also making electrical contact with said transverse conductive element formed from said intermediate conductive layer that makes electrical contact with at least one member of said terminal array; and wherein a first subset of said set of contacts in said contact array are connected to said first voltage plane and isolated from said second voltage plane at the time of fabrication of the test board, a second subset of said set of contacts in said contact array are connected to said second voltage plane and isolated from said first voltage plane at the time of fabrication of the test board and a third subset of said set of contacts in said contact array that are connected to corresponding members of said terminal array and isolated from said first voltage plane and from said second voltage plane at the time of fabrication of the test board.