Patent ID: 6960517

Claim:
A method, comprising: forming a protective mask on a lightly doped monocrystalline semiconductor layer; etching a first portion of the lightly doped monocrystalline semiconductor layer to a first thickness, in alignment with the protective mask, by a first timed etch, to form a first stair-step level, the first stair-step level including a single upper stair step having two vertical sidewalls and a horizontal topwall; forming a first set of spacers along the entire length of the two vertical sidewalls of the upper stair step; etching a second portion of the lightly doped monocrystalline semiconductor layer in alignment with the spacers, to a second thickness, to form a second stair-step level, the second stair-step level having two lower stair steps subjacent to the upper stair step; and forming a gate dielectric and a gate electrode to border the vertical sidewalls and horizontal topwalls of a channel region of the lightly doped monocrystalline semiconductor layer.