Patent ID: 7031887

Claim:
A method for generating computer system level architectures that are capable of executing multiple functional specifications, given a set of physical resources, and subject to a set of design constraints, the method comprising: forming an initial master task graph from said multiple specifications, said initial master task graph including at least one hierarchical task having pointers to a plurality of sub-task graphs, wherein an XOR relationship exists between at least two of the plurality of sub-task graphs; processing said initial master task graph to provide a selected number of final master task graphs, each of said final master task graphs comprising a list of AND task graphs; generating a family of architectures for each of said final master task graphs, each of the architectures generated for a given final master task graph being capable of executing every AND task graph included in the list for the given final master task graph; and exploring each of said generated architectures for use in executing said multiple specifications.