Patent ID: 8421143

Claim:
A semiconductor device comprising: a semiconductor layer; a first memory transistor; and a peripheral circuit transistor; wherein the first memory transistor comprises: a first insulating film formed on the semiconductor layer in a memory cell region; a first electrode layer formed on the first insulating film; a first element isolating insulator formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, a top face of the first element isolating insulator being lower than a top face of the first electrode layer; a second insulating film formed on the first electrode layer and the first element isolating insulator; a second electrode layer formed on the second insulating film; and a third electrode layer formed on the second electrode layer; and the peripheral circuit transistor comprises: a third insulating film formed on the semiconductor layer in a peripheral circuit region; a fourth electrode layer formed on the third insulating film; a second element isolating insulator formed to extend through the fourth electrode layer and the third insulating film to reach an inner region of the semiconductor layer; a fourth insulating film formed on the fourth electrode layer, the fourth insulating film including a first open portion exposing a surface of the fourth electrode layer; a fifth electrode layer formed on the fourth insulating film; a sixth electrode layer formed on the fifth electrode layer and on the exposed surface of the fourth electrode layer, the sixth electrode layer being electrically connected to the fourth electrode layer via the first open portion; and a contact arranged above the second element isolating insulator and electrically connected to the sixth electrode layer.