Patent ID: 6993550

Claim:
A fixed point multiplying apparatus for performing a multiplication of a multiplier and an encoded multiplicand, the apparatus comprising: n number of n bit shift registers for storing binary data of the multiplier by shifting each of the binary data by one bit; multiplexers for selecting and receiving one data as an input from a group consisting of the data stored in the shift registers, inverted data of the stored data, and 0 in response to a control signal for selecting the input; control blocks for storing multiplicand data which are binary encoded according to equation 1, selecting the shift registers corresponding to bit values of the multiplicand data, and applying the control signal to the corresponding multiplexers; and n−1 number of adders for sequentially adding output values from the multiplexers according to each bit to output multiplication data of the multiplier and the multiplicand: w k = C k M - 1 · ( 1 - 2 ⁢ n k - ( M - 1 ) ) · 2 0 + ∑ i = 0 M - 2 ⁢ C k i · ⁢ ( 1 - 2 ⁢ n k i ) · 2 - ( M - 1 ) + i , where ∀i ∈ Z[0,M−1], C k i ∈ {0,1} and n k i ∈ {0,1}, Y = ∑ k ⁢ w k ⁢ x k , where w k is the multiplier and x k is the multiplicand, and x k = - C _ k i · 2 M - 1 + ∑ j = 0 M - 2 ⁢ C _ k j · 2 j , where ∀ j ∈ Z ⁡ [ 0 , M - 1 ] ⁢ ⁢ and ⁢ ⁢ C _ k j ∈ { 0 , 1 } . Equation ⁢ ⁢ 1