Patent ID: 7724018

Claim:
A method of determining operational characteristics of a wafer-level test system, comprising: providing an electronic assembly suitable for testing and calibrating a wafer-level test system, the electronic assembly including a first major surface with a plurality of electrical contact terminals disposed thereon and configured to make electrical contact with a wafer-level test system; coupling the electronic assembly to the wafer-level test system; operating the wafer-level test system such that a plurality of signals are communicated to the electronic assembly; processing, on the electronic assembly, the plurality of signals communicated from the wafer-level test system; and generating on the electronic assembly one or more electrical signals indicative of the operational characteristics of the wafer-level test system; wherein the electronic assembly comprises a substrate with a first plurality of electrical components disposed thereon; and a first stack-on layer with a second plurality of electrical components disposed thereon, the first stack-on layer disposed on the substrate; wherein the first stack-on layer has openings therein, by means of which, uppermost portions of the first plurality of electrical components may extend through the first stack-on layer.