Patent ID: 7205171

Claim:
A manufacturing method of a thin film transistor (TFT), comprising: forming a gate over a substrate; forming an inter-gate dielectric layer over the substrate covering the gate; forming a channel layer over a portion of the inter-gate dielectric layer at least over the gate, wherein the channel layer is a lightly doped amorphous silicon layer, and the step of forming the channel layer comprises: forming a first lightly doped sub-amorphous silicon layer over the portion of the inter-gate dielectric layer at a first deposition rate; and forming a second lightly doped sub-amorphous silicon layer over the first lightly doped sub-amorphous silicon layer at a second deposition rate; and forming source/drain regions over the channel layer so as to cover a portion of the channel layer, wherein the source/drain regions are separated by a distance wherein said channel is doped with a phosphorous ions in the range of about 1E17 ions/cm 3 to about 1E18 ions/cm 3 or boron ions in the range of about 1E16 ions/cm 3 to about 5E17 ions/cm 3 .