Patent ID: 8003489

Claim:
A method for forming an isolation structure in a semiconductor device, the method comprising: forming a trench in a semiconductor substrate; forming a liner layer on a sidewall of the trench, wherein the liner layer comprises a liner nitride layer and a liner oxide layer; forming a flowable insulation layer to at least substantially fill the trench; etching the flowable insulation layer to expose an upper portion of the liner nitride layer in the trench; performing a first preheating process by supplying a first preheating gas so as to release stress of the liner layer; performing a second preheating process by supplying a second preheating gas so as to oxidize the exposed upper portion of the liner nitride layer; forming a passivation layer over the exposed upper portion of the liner nitride layer and the flowable insulation layer, wherein the passivation layer is formed to have a predetermined thickness by using a first deposition source including oxygen (O 2 ), silane (SiH 4 ), and helium (He) gases; and forming a buried insulation layer over the passivation layer so as to fill the trench using a second deposition source including oxygen (O 2 ), silane (SiH 4 ), hydrogen (H 2 ), and helium (He) gases, the buried insulation layer being formed while keeping a deposition sputtering rate (DSR) at no more than approximately 22.