Patent ID: 6938172

Claim:
Circuitry for reducing power dissipation in a integrated circuit, comprising: a data latch for storing a first multibit digital signal; an input data latch for receiving a second multibit digital signal, said input data latch producing transformed and untransformed versions of said second multibit digital signal; a comparing circuit for comparing values of bits in respective bit positions of said first and second multibit digital signals and producing an output signal representative of a state transition at each bit position; summing circuitry coupled to said comparing circuitry for providing a sum of state transitions for each comparison of said multibit digital signals; a controller for determining if said sum exceeds a predetermined value, and producing a transformation vector signal in response thereto; a selection circuit coupled to said input data latch for selecting one of said transformed and said untransformed versions of said second multibit digital signal in response to said transformation vector signal.