Patent ID: 7589546

Claim:
A semiconductor inspection apparatus for performing wafer level burn-in for a plurality of semiconductor ICs, each semiconductor IC having a plurality of electrodes that input and output a signal or a power-supply voltage or a grounding voltage and are formed on a wafer, the semiconductor inspection apparatus comprising: a plurality of probes for performing inspection by connecting to each electrode of each semiconductor IC; a plurality of signal interconnects for inputting and outputting, via the plurality of probes, a signal to and from a signal electrode of each semiconductor IC; a power-supply interconnect for supplying, via the plurality of probes, a power-supply voltage to each power-supply electrode of each semiconductor IC; a grounding interconnect for supplying, via the plurality of probes, a grounding voltage to each grounding electrode of each semiconductor IC; a relay located between the power-supply interconnect and at least one of the power-supply electrodes; and a PTC element that located between the relay and the power-supply electrode, wherein a high voltage is applied to each of the semiconductor ICs, with the relay brought into a connected condition, and the burn-in is performed, with the PTC element tripped for all of the semiconductor ICs that have been proven to be defective, so that the relay is capable of being turned on while burn-in is performed.