Patent ID: 7721086

Claim:
A cryptographic system, comprising: a plurality of cryptographic sub-units, each of the sub-units being configured to perform a cryptographic operation on data blocks associated with a plurality of packets to form transformed blocks; a scheduler configured to: receive the packets, associate a sequence number with each of the packets, the sequence number being a timestamp indicative of a worst-case completion time for packet reassembly, and assign the packets to the sub-units; and a reassembler configured to: receive the transformed blocks from the sub-units, reassemble the packets from the transformed blocks, order the packets based on the associated sequence numbers, and output the ordered packets, the outputting including to: determine whether a particular packet of the ordered packets is marked as complete and the value of the timestamp associated with the particular packet is less than or equal to the current time; and output the particular packet once the determination is satisfied; wherein at least one of the plurality of cryptographic sub-units, the scheduler, and the reassembler is at least partially implemented using a hardware device.