Patent ID: 7400276

Claim:
A method for use with a circuit having a bus comprising m capacitively-coupled parallel bus lines where m is an integer greater than 1, the method comprising: restricting a number of possible transitions on the bus to a number smaller than the maximum number of possible transitions, 2 2m , by only including transitions each having a delay less than or equal to a predetermined delay threshold, T S , so that data transmissions on the bus occur at a transmission rate which is higher than the transmission rate allowable if the number of transitions had not been restricted, where T S is greater than zero, wherein vectors of m bits are transmitted along the bus during every clock period, T, and a transition is associated with a vector pair having a first vector of present data, u 0 , on the bus and a second vector of subsequent next data, u N , to be transmitted on the bus, the first vector, u 0 , includes u 0 1 , . . . , u 0 m vector components each associated with a respective one of the m bits on a corresponding one of the m lines and the second vector, u N , includes u N 1 , . . . , u N m vector components each associated with a respective one of the m bits to be transmitted on a corresponding one of the m lines, a transition comprises a transition from a logic state of each respective vector component of the first vector to a logic state of each respective corresponding vector component of the second vector where T S is less than T; and an amount of information transmitted during a clock period equal to T s , is equal to m s bits where m s is less than m so that information transmitted is transmitted at a rate which is T T s × m s m times faster than a rate which is possible when the number of possible transitions on the bus is not restricted.