Patent ID: 8773929

Claim:
A memory cell comprising: a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value, the plurality of transistors comprising: a first transistor of a first type in a first well of a second type having a first well tap connected to a source of the first transistor; a second transistor of the first type in a second well of the second type having a second well tap connected to a source of the second transistor; a third transistor of the second type in a third well of the first type having a third well tap connected to a source of the third transistor; and a fourth transistor of the second type in a fourth well of the first type having a fourth well tap connected to a source of the fourth transistor, the first well, second well, third well, and forth well being isolated from each other.