Patent ID: 8508255

Claim:
A digital circuit comprising: a buffer circuit comprising: a buffer data input; a buffer data output; a buffer clock input; and a buffer status signal output; a clocked device coupled to the buffer circuit, the clocked device comprising: a clocked device data input; a clocked device data output; and a clocked device clock input; a clock control device comprising: a clock control device clock input; a clock control device status signal input; and a clock control device clock output; wherein: the buffer is configured to transmit a status signal from the buffer status signal output; the clock control device is configured to: receive an input clock signal at the clock control device clock input and the status signal at the clock control device status signal input; generate an output clock signal based on the input clock signal and the status signal; and transmit the output clock signal from the clock control device clock output to the clocked device clock input.