Patent ID: 8499021

Claim:
A circuit for computing the circular convolution of an input signal with a finite impulse response, comprising: a first-in-first-out (FIFO) memory circuit configured to store M number of incoming input samples of the input signal in response to a first control signal and to provide stored input samples in response to a second control signal, M being the length of the finite impulse response; a multiplexer configured to receive the incoming input samples of the input signal as a first data input and the stored input samples from the FIFO memory circuit as a second data input, the multiplexer further configured to receive a third control signal as a select signal, the multiplexer operative to select either the first data input or the second data input as a data output in response to the select signal; a controller configured to generate the first, second and third control signals; and a convolve circuit configured to compute the convolution of the data output of the multiplexer and the finite impulse response, thereby generating circular convolution output samples, the convolution being performed on blocks of N number of input samples of the input signal, N being greater than M, wherein the controller is operative to generate the first control signal to cause the initial M input samples of each block of N input samples to be stored in the FIFO memory circuit as the stored input samples, to generate the third control signal to cause the (M+1)th to Nth input samples of each block to be provided to the convolve circuit for computing the convolution and after the Nth input sample of each block, to generate the second control signal to cause the M stored input samples to be provided to the convolve circuit for convolution with the finite impulse response, the convolve circuit further configured to be disabled for the (M+1)th to (N−M)th incoming input samples of each block of the input signal, and the convolve circuit is operative to compute the convolution of the data output of the multiplexer and the finite impulse response for the (N−M+1)th to Nth incoming input samples of each block and for the M stored input samples provided after the Nth input sample of each block, wherein the first control signal is asserted for the initial M input samples of the input signal and the second control signal is deasserted for the first block of input samples and is asserted for the initial M input samples of the input signal for subsequent blocks of input samples.