Patent ID: 8660170

Claim:
A circuit for correcting the quadrature phase error between the in-phase and quadrature sampling clocks in a quadrature bandpass-sampling receiver comprising: a quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) configured to receive an in-phase analog test tone and a quadrature analog test tone, combine the in-phase analog test tone and the quadrature analog test tone into a single-sided test tone, and demodulate the single-sided test tone to baseband to generate an in-phase digital signal based on the in-phase sampling clock, and generate a quadrature digital signal based on the quadrature sampling clock; a sampling clock generator configured to generate an in-phase sampling clock, having an in-phase sampling clock frequency; a ninety-degree phase shifter configured to receive the in-phase sampling clock, and generate a quadrature sampling clock based on the phase-shift control signal; a discrete Fourier transform (DFT) block configured to receive N samples of the in-phase digital signal to generate an in-phase complex Fourier coefficient, and receive N samples of the quadrature digital signal to generate a quadrature complex Fourier coefficient; an integrator configured to average M samples of the in-phase complex Fourier coefficient to generate a low-noise in-phase coefficient based on the symbol clock, and average M samples of the quadrature complex Fourier coefficient to generate a low-noise quadrature coefficient based on the symbol clock; a symbol clock generator configured to generate a symbol clock, having a symbol clock frequency; an in-phase/quadrature (I/Q) mismatch calculator configured to receive the low-noise in-phase coefficient and the low-noise quadrature coefficient, and generate a phase-shift control signal; a test tone generator configured to generate an in-phase test tone having an in-phase test tone frequency, and a quadrature test tone; a first multiplier configured to multiply the in-phase test tone with the in-phase sampling clock to generate an up-converted in-phase test tone; a second multiplier configured to multiply the quadrature test tone with the quadrature sampling clock to generate an up-converted quadrature test tone; a first digital-to-analog (D/A) converter configured to receive the up-converted in-phase test tone to generate a in-phase analog test tone; and a second D/A converter configured to receive the up-converted quadrature test tone to generate a quadrature analog test tone; wherein N is a positive integer, and M is between 1 and 100.