Patent ID: 7840863

Claim:
An integrated circuit, comprising: a test pin, a select enable pin, a functional clock pin, a scan-in pin and a scan-out pin; a test controller having a test input connected to said test pin, a functional clock input connected to said functional clock pin, a first control output and a second control output; and a scan chain comprised of serially connected latches and corresponding multiplexers, a first stage of each latch having an data input, a clock input connected to said functional clock pin and a first control input connected to said first control output of said test controller, a second stage of each latch having a data output and a second control input connected to said second control output of said tester controller, each multiplexer having a first selectable input, a second selectable input and an output and having a select enable input connected to said select enable pin, the data output of a previous latch of said scan chain connected to the first selectable input of a subsequent multiplexer corresponding to an immediately subsequent latch, the output of said subsequent multiplexer connected to the data input of said immediately subsequent latch, and the first selectable input of a first multiplexer corresponding to a first latch of said scan chain connected to said scan-in pin and a data output of a last latch of said scan chain connected to said scan-out pin.