Patent ID: 8271855

Claim:
A memory system, comprising: a plurality of reference memory elements, each reference memory element having a distinct reference resistance value; a back-end-of-the-line (BEOL) memory element configured to store multiple bits of data; and a front-end-of-the-line (FEOL) read and error detection circuit in electrical communication with the plurality of reference memory elements and the BEOL memory element, the FEOL read and error detection circuit configured to sequentially sense a difference between the distinct reference resistance of each of the plurality of reference memory elements and a first resistance of the BEOL memory element, wherein, based on the differences, the FEOL read and error detection circuit is further configured to output a decode state indicative of multiple bit data stored in the BEOL memory element or a programming error in multiple bit data stored in the BEOL memory element, and wherein the FEOL read and error detection circuit is further configured to correct the programming error using a pre-selected bias to re-program multiple bit data to the BEOL memory element wherein the FEOL read and error detection circuit is further configured to correct the programming error using a pre-selected bias to re-program multiple bit data to the BEOL memory element, the pre-selected bias comprises an upward or downward bias applied to the BEOL memory element and operative to re-write a corrected decode state indicative of multiple bit data to the BEOL memory element.