Patent ID: 7701785

Claim:
A memory comprising: an array of memory cells; a sense amplifier; a data line coupled to a sense amplifier for providing a signal indicative of a value stored in a memory cell of the array during at least a portion of read operation, wherein the data line is precharged at a first voltage during a precharge operation; a bit line segment, the bit line segment coupled to a memory cell of the memory array during at least a portion of a read operation of the memory cell; a regulation circuit, the regulation circuit including: a first transistor having a first current electrode connected to the data line, a second current electrode connected to the bit line segment, and a control electrode; a second transistor, the second transistor having a control electrode connected to the second current electrode of the first transistor; a third transistor, the third transistor having a first current electrode connected to the control electrode of the first transistor and a second current electrode connected to a first current electrode of the second transistor, wherein a first current electrode of the third transistor is coupled to a second voltage source during at least a portion of a memory read operation, wherein the second voltage source is configured to provide a higher voltage than the first voltage during a memory read operation; wherein the control electrode of the first transistor is biased at a higher voltage level than the first voltage during at least a portion of a read operation of a memory cell of the array.