Patent ID: 7768810

Claim:
In integrated circuit, a radiation tolerant static random access memory device comprising: a first pair of complementary transistors having an input and an output, said first pair of complementary transistors connected in series between a first voltage potential and a second voltage potential through a first node that provides the output for the first pair, and a gate of each of the first pair connected together as the input to the first pair of complementary transistors; a second pair of complementary transistors having an input and an output, said second pair of complementary transistors connected in series between the first voltage potential and the second voltage potential through a second node that provides the output for the second pair, and a gate of each of the second pair connected together as the input to the second pair, said output of said first pair of complementary transistors coupled to said input of said second pair of complementary transistors and said output of said second pair of complementary transistors coupled to said input of said first pair of complementary transistors; a first resistor coupled between said first and second pairs of complementary transistors; and wherein: an RC time constant of the radiation tolerant static random access memory device exceeds a selected recovery time of the s radiation tolerant static random access memory device.