Patent ID: 8003467

Claim:
A method for making a semiconductor device having metal gate stacks comprising: forming shallow trench isolation (STI) features in a silicon substrate, defining a first active region configured for a p-type field effect transistor (PFET) and a second active region configured for an n-type field effect transistor (NFET); forming, on the silicon substrate, a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening of the hard mask to form a recess in the silicon substrate within the first active region; growing a silicon germanium (SiGe) layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers on the silicon substrate and the SiGe layer; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; forming an eSiGe source/drain (S/D) stressor distributed in both the SiGe layer and the silicon substrate within the first active region; forming a first dielectric layer on the metal gate stack; forming light-doped drain (LDD) features in the SiGe layer; and forming a spacer on sidewall of the first dielectric layer prior to forming of the eSiGe S/D stressor.