Patent ID: 8238140

Claim:
A semiconductor memory comprising memory cells each in turn comprising: a pair of cross-coupled coupled inverters with respective outputs connected to paths respectively leading to each of a pair of bit lines disposed in correspondence to a column of the memory cells; a pair of switch units disposed between the bit lines and the outputs of the inverters; and a single word line controllable by conduction of the switch units; and wherein dynamic switching between a mode in which one bit is allocated to one memory cell (1-bit/1-cell mode) and a mode in which one bit is allocated to n (where n is two or more) coupled memory cells (1-bit/n-cell mode) is enabled, and by switching to the 1-bit/n-cell mode, operation stability of one bit is enhanced, a cell current during a read operation is increased (the read operation is made high in speed), and self-correction of bit error is enabled.