Patent ID: 8248848

Claim:
A memory circuit comprising: a memory array comprising multi-level cells, wherein each of the multi-level cells is configured to store M bits of data, where M is an integer greater than one; a first control module configured to (i) read a state of one of the multi-level cells, and (ii) perform one of a first erase operation and a first program operation on the one of the multi-level cells for the M bits of data during a first time period; and a comparing module configured to, subsequent to performing the one of the first erase operation and the first program operation, perform (i) a first XNOR on a first one of the M bits of data and a first control signal input, and (ii) a second XNOR on a second one of the M bits of data and a second control signal input, wherein the comparing module is configured to determine whether to perform one of a second erase operation and a second program operation based on results of the first XNOR and the second XNOR.