Patent ID: 8377783

Claim:
A method for reducing punch-through in a transistor device, comprising: forming a first well layer in a first implant region for a PMOS device using a directional Phosphorous implant in an energy range of 100 to 400 keV and a concentration range of 1e12/cm 2 to 2e13/cm 2 ; forming a first stop layer in the first well layer of lesser depth than the first well layer using an Arsenic dopant implant in an energy range of 20 to 100 keV and a concentration range of 1e12/cm 2 to 1e13/cm 2 ; forming a first doped layer in the first stop layer of lesser depth than the first stop layer using an Arsenic implant in an energy range of 1 to 10 keV and a concentration range of 5e12/cm 2 to 1e14/cm 2 , the first stop layer having a lower concentration of dopant impurities than the first doped layer; wherein the first stop layer and first doped layer implant conditions are selected so that the first doped layer is above and in contact with the first stop layer; forming an epitaxial layer on the first doped layer, wherein the epitaxial layer is undoped; forming a resulting transistor device, the resulting transistor device employing the undoped epitaxial layer; wherein the undoped epitaxial layer is above and in contact with the first doped layer, and wherein the first stop layer, the first doped layer, and the undoped epitaxial layer comprise a three-layer stack; and forming a source region and a drain region, the source and drain regions penetrating the three-layer stack through the first doped layer and partially into the first stop layer.