Patent ID: 7336755

Claim:
A phase-locked loop (PLL) for high data rate serial digital communications, comprising: a phase/frequency to voltage converter block for producing a voltage controlled oscillator (VCO) input voltage based upon a phase of a divided clock in relation to a reference signal; a VCO producing a plurality of clocks based upon the VCO input voltage; a multiplexer coupled to receive the plurality of clocks and further coupled to receive a clock select signal wherein the multiplexer produces a selected clock based upon the clock select signal; an integer divide by N block coupled to receive the selected clock wherein the integer divide by N block divides the selected clock by an integer amount to produce the divided clock; a state machine for generating the clock select signal wherein the state machine selects a clock according to a desired divider ratio; and wherein the state machine is adapted to obtain the desired divider ratio by adjusting a pulse period of one cycle of the clock select signal until a phase and frequency of the clock select signal is equal to a phase and frequency of the selected clock.