Patent ID: 8659461

Claim:
An analog-to-digital converter (ADC) circuit, comprising: multiple time-interleaved pipelined-successive approximation register (SAR) ADCs, each of the multiple time-interleaved SAR ADCs comprising: a first stage SAR sub-ADC for coarse conversion, the first stage SAR sub-ADC receiving and converting an analog input signal to generate a digital code and a residue signal; a residue amplifier for amplifying the residue signal generated by the first stage SAR sub-ADC to output a amplified residue signal, wherein the residue amplifier is shared between the multiple time-interleaved pipelined-SAR ADCs; a second stage SAR sub-ADC for fine conversion, the second stage SAR sub-ADC receiving and converting the amplified residue signal to generate a digital code; and a digital error correction logic for receiving and combining the digital code generated by the first stage SAR sub-ADC and the digital code generated by the second stage SAR sub-ADC to generate digital signal that represents the analog input signal, wherein the first stage SAR sub-ADC comprises a plurality of capacitive digital-to-analog converter (DAC) built as a flip-around Multiplying Digital to Analog Converter (MDAC) for improving feedback factor in the pipelined-successive approximation register (SAR) ADC.