Patent ID: 7659539

Claim:
A semiconductor device comprising: a semiconductor substrate; and at least one nonvolatile memory cell comprising a superlattice channel comprising a plurality of stacked groups of layers on said semiconductor substrate, spaced apart source and drain regions for causing transport of charge carriers through said superlattice channel in a parallel direction relative to the stacked groups of layers, each group of layers of said superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, said energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween, a floating gate adjacent said superlattice channel, and a control gate adjacent said floating gate.