Patent ID: 7795939

Claim:
A method for setup and hold characterization in an integrated circuit cell, the method comprising: generating a first and a second periodic signal, the first periodic signal having a frequency greater than the frequency of the second periodic signal; coupling the first periodic signal to a clock pin of a first sequential cell and coupling the second periodic signal to a data input pin of the first sequential cell, thereby causing the second periodic signal to be sampled at a transition of the first periodic signal; coupling the first periodic signal to a data input pin of a second sequential cell and coupling the second periodic signal to a clock pin of the second sequential cell, thereby causing the first periodic signal to be sampled at a transition of the second periodic signal, the second sequential cell being substantially identical with the first sequential cell; determining a first setup time from a first state transition in an output signal of the first sequential cell; and determining a first hold time from a first state transition in an output signal of the second sequential cell.