Patent ID: 7525333

Claim:
A current sense circuit comprising: a plurality of field-effect transistors including at least first, second, third and fourth transistors of the same polarity type, each having a source terminal, a drain terminal, and a gate terminal; the source terminals of each of the first, second, third and fourth transistors being coupled together; the drain terminals of each of the first, second, third and fourth transistors being coupled together; and the gate terminals of each of the first, second, third and fourth transistors being coupled together; an averaging drain voltage conveyance mechanism; a first drain sense resistor coupled between the drain terminal of the first transistor and the averaging drain voltage conveyance mechanism; a second drain sense resistor coupled between the drain terminal of the second transistor and the averaging drain voltage conveyance mechanism, wherein the averaging drain voltage conveyance mechanism is configured to provide an averaged drain voltage; and a mirror transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal of the mirror transistor is coupled to the gate terminals of each of the first, second, third and fourth transistors, and wherein the drain terminal of the mirror transistor is coupled to the averaging drain voltage conveyance mechanism so as to receive the averaged drain voltage provided by the averaging drain voltage conveyance mechanism, the averaged drain voltage being such that the drain-to-source voltage of the mirror transistor is consistently between the highest drain-to-source voltage of the at least two of the first, second, third and fourth transistors and the lowest drain-to-source voltage of the at least two of the first, second, third and fourth transistors.