Patent ID: 8416906

Claim:
A clock recovery circuit, comprising: a control circuit adapted to receive a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency, wherein the second frequency is higher than the first frequency, the control circuit comprising: a phase control block adapted to define non-overlapping portions of a pulse of the second clock including a center portion, left portion and right portion and determine whether an edge of the first clock is located within the center portion; and a frequency control block responsive to the determination that the edge of the first clock is located within the center portion and adapted to compare a number of periods of the second clock signal which occur within one or more periods of the first clock signal to a number derived from the divisor number and generate a frequency selection signal in response thereto; and a controlled oscillator circuit adapted to generate the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal.