Patent ID: 8110921

Claim:
A semiconductor package comprising: a support plate; a plurality of semiconductor devices having different thicknesses from each other and having respective electrode terminals, the semiconductor devices fixed on a surface of the support plate through a resin layer in such a manner that terminal surfaces of the electrode terminals are on the level with each other; an insulating layer formed on terminal forming surfaces, at which the electrode terminals are formed, of the semiconductor devices; at least one tapered bump formed on one of the terminal surfaces of the electrode terminals, the tapered bump having a tip surface formed in a smaller area than an area of the terminal surface of the electrode terminal, the tapered bump penetrating through the insulating layer in such a manner that the tip surface of the tapered bump is exposed through the insulating layer to a surface of the insulating layer; and a wiring pattern formed on the surface of the insulating layer and connected to the tip surface of the tapered bump, thereby allowing for increased wiring pattern density.