Patent ID: 7412470

Claim:
An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits, wherein each of said unit arithmetic circuits includes: at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two items of data; a second resister that holds data; a bit shifter operable to shift data to one of a left and a right direction; a subtractor operable to calculate a difference between two items of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among said input terminal, said output terminal, said first register, said adder, said second register, said bit shifter, said subtractor, and said absolute value calculating unit, wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing function that differs depending on the processing mode, and wherein the plurality of arithmetic processing blocks include first and second arithmetic processing blocks when the processing mode is a coding mode for a still picture, the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and the second arithmetic processing block has a digital filtering function.