Patent ID: 6936511

Claim:
A method of forming a DRAM cell in a semiconductor substrate comprising a trench capacitor connected by a buried strap to a vertical transistor comprising the steps of: etching a trench in said substrate, and forming a capacitor within the trench, the capacitor having a top exposed surface of a central electrode; depositing a layer of buried strap material as intrinsic polysilicon on the top exposed surface and diffusing dopant from said central electrode through said layer of buried strap material and into said semiconductor substrate; depositing a center separation layer of insulator within said layer of buried strap conductive material, thereby separating the buried strap from the center of the upper portion of the trench; recessing the buried strap material to form a recess having a recess depth around said center layer of insulator; filling said recess with an insulator plug, thereby establishing a separation layer of insulator filling said trench laterally and having a vertical extent equal to said recess depth and thereby separating said central electrode from the upper portion of the trench; and forming a vertical transistor adjacent to said separation layer of insulator.