Patent ID: 7355218

Claim:
An integrated circuit comprising: a semiconductor body of a first conductivity type; a first highly doped region of a second conductivity type disposed in the semiconductor body, the second conductivity type being different than the first conductivity type; a second highly doped region of the second conductivity type disposed in the semiconductor body and spaced from the first highly doped region; a first electrode overlying and insulated from the semiconductor body between the first highly doped region and the second highly doped region such that a transistor comprising the first highly doped region, the second highly doped region and the first electrode is formed; a fourth highly doped region of the first conductivity type disposed in the semiconductor body and spaced from the second highly doped region; and a second electrode overlying and insulated from the semiconductor body between the second highly doped region and the fourth highly doped region, the second electrode being coupled to a reference supply voltage node, wherein the second electrode is physically separate from the first electrode.