Patent ID: 7263142

Claim:
A timing loop controller for multilevel modulation scheme, comprising: a first buffer for orderly receiving I-channel digital signals and generating first buffered signals by buffering the received I-channel digital signals; a second buffer for receiving the received I-channel digital signals from the first buffer and generating second buffered digital signals; a first quantization means for receiving the buffered digital signals from the second buffer and generating first quantized signals by quantizing the second buffered digital signals; a second quantization means for receiving the I-channel digital signals and generating second quantized signals by quantizing the I-channel digital signals; a first sign detection means for receiving the first quantized signals and the second quantized signals and detecting sign change of the first quantized signals and the second quantized signals; a third buffer for orderly receiving Q-channel digital signals and generating a third buffered signals by buffering the received Q-channel digital signals; a fourth buffer for receiving the received Q-channel digital signals from the first buffer and generating fourth buffered digital signals; a third quantization means for receiving the fourth buffered digital signals from the fourth buffer and generating third quantized signals by quantizing the fourth buffered digital signals; a fourth quantization means for receiving the Q-channel digital signals and generating fourth quantized signals by quantizing the Q-channel digital signals; a second sign detection means for receiving the third quantized signals and the fourth quantized signals and detecting sign change of the third quantized signals and the fourth quantized signals; a timing error computation means for computing a timing error output value based on the I-channel digital signals, the first buffered signals, the first quantized signals, the Q-channel digital signals, the third buffered signals, the third quantized signals and the fourth quantized signals; a zero crossing detection means for detecting zero crossing at I axis and Q axis according based on results outputted from the first and second sign detection means; and a timing error control means for controlling the timing error value in case there is no sign change according to results outputted from the first and second sign detection means.