Patent ID: 8766685

Claim:
A phase locked loop (PLL) circuit, comprising: a phase frequency detector, configured to receive a first input signal and a second input signal, and to output a first adjustment parameter and a second adjustment parameter according to phase and frequency difference between the first input signal and the second input signal; a charge pump coupled to the phase frequency detector, configured to generate a current according to the first adjustment parameter and the second adjustment parameters; a low pass filter coupled to the charge pump, configured to generate a voltage according to the current; a voltage controlled oscillator (VCO) coupled to the low pass filter, configured to generate an oscillation frequency according to the voltage; a frequency divider configured to receive the oscillation frequency, to divide the oscillation frequency, and to generate the second input signal using the divided oscillation frequency; and a reset module configured to generate a reset signal to feed to the frequency divider, wherein the reset module is configured to receive the first signal; wherein the reset module comprises a first inverter, a first D-type flip flop, a second D-type flip flop, a third D-type flip flop, and an Exclusive-OR(XOR) gate, wherein the first inverter is configured to receive a third signal, a D port of the first D-type flip flop is connected to the first inverter, and a Q port of the first D-type flip flop is connected to a D port of the second D-type flip flop, a Q port of the second D-type flip flop is connected to both a first input port of the XOR gate and a D port of the third D-type flip flop, a Q port of the third D-type flip flop is connected to a second input port of the XOR gate, clock ports of the first, second and third D-type flip flops are all configured to receive the first input signal, such that the XOR gate outputs a reset pulse.