Patent ID: 8755245

Claim:
Memory control circuitry for sequencing memory operations for a memory comprising a plurality of sections in an iterative process, each iteration comprising a plurality of phases, and each phase comprising a plurality of cycles, the memory control circuitry comprising: a sequence generator configured to output a plurality of phase control signals, each phase control signal being associated with a different phase of an iteration, and configured to output a plurality of cycle control signals, each associated with a different cycle of a phase; and a plurality of control signal selectors, each control signal selector being associated with a different section of the plurality of sections of the memory, each control signal selector being configured to accept the phase control signals and the cycle control signals and to output a plurality of column control signals, the selector including for each output a selector circuit responsive to the phase control signals to select one of the cycle control signals accepted by the selector; wherein the memory control circuitry is configured to apply to each memory section the phase control signals and the column control signals output from the control signal selector associated with the memory section to select memory cells in the memory section, including selecting at least some of the memory cells in a read mode and at least some cells in a write mode responsive to the phase and column control signals.