Patent ID: 8705217

Claim:
A circuit comprising: a CMOS output buffer coupled between a first supply rail and a second supply rail; an ESD detection circuit configured to detect an ESD event and generate an event signal; a control circuit operable responsive to the event signal to activate the CMOS output buffer to connect the first supply rail to the second supply rail to discharge the ESD event; wherein the CMOS output buffer comprises a PMOS transistor and an NMOS transistor connected in series between the first supply rail and the second supply rail, and wherein the control circuit comprises circuitry configured to simultaneously activate the PMOS and NMOS transistors to connect the first supply rail to the second supply rail; an amplifier with differential outputs coupled to gates of the PMOS and NMOS transistors, the control circuit further comprising circuitry configured to disable the amplifier in response to the ESD event signal; a first standby transistor having a source-drain circuit coupled between the first supply rail and a gate of the PMOS transistor; and a second standby transistor having a source-drain circuit coupled between the second supply rail and a gate of the NMOS transistor; the control circuit further comprising circuitry configured to shut off the first and second standby transistors in response to the ESD event signal.