Patent ID: 6901016

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a first direction and in a second direction; a plurality of bit lines, each of the bit lines being connected in common to the plurality of memory cells arranged in the first direction; a first precharge switch, connected to a potential supply line via a fuse and connected to one end of each of the bit lines, the potential supply line supplying a predetermined potential, and the first precharge switch connecting the potential supply line to each of the bit lines when the bit lines are precharged to the predetermined potential; and a second precharge switch, connected to the potential supply line and connected to the other end of each of the bit lines, the second precharge switch connecting the potential supply line to each of the bit lines when the bit lines are precharged to the predetermined potential, wherein the second precharge switch is in a cut-off state during a standby period in which memory cells corresponding to the second precharge switch hold data without reading and writing data.