Patent ID: 6987408

Claim:
A digital delay locked loop (DLL) comprising: a clock generating means for generating a source clock and a reference clock; a delay line provided with a plurality of unit delays, for delaying the source clock by a predetermined time; a delay model for reflecting a delay time of an actual integral circuit to an output of the delay line; a phase comparing means for comparing a phase of the reference clock with a phase of a feedback clock outputted from the delay model; a jitter detecting means for detecting a maximum jitter timing in response to a phase comparison signal outputted from the phase comparing means and generating a multi-delay enable signal, wherein the jitter detecting means activates the multi-delay enable signal at a timing when the phase comparison signal maintains one of a lag or lead state during N bits and the state is changed; and a delay control means for controlling a delay amount of the delay line by unit-delay unit or multi-delay unit in response to the phase comparison signal and the multi-delay enable signal.