Patent ID: 7162560

Claim:
A system, comprising: a plurality of processors; a first plurality of boot-capable devices to supply a first plurality of interrupts; a second plurality of boot-capable devices to supply a second plurality of interrupts; and an interrupt controller subsystem, comprising a first programmable interrupt controller and a second programmable interrupt controller; wherein: if the system is partitioned into a first domain and a second domain: the first plurality of interrupts are received by the first programmable interrupt controller; a first processor-interrupting signal is generated by the first programmable interrupt controller, the first processor-interrupting signal to interrupt a first processor of the plurality of processors, wherein the first processor is in the first domain; the second plurality of interrupts are received by the second programmable interrupt controller; and a second processor-interrupting signal is generated the second programmable interrupt controller, the second Processor-interrupting signal to interrupt a second processor of the plurality of processors, wherein the second Processor is in the second domain; and if the system is not partitioned: the first plurality of interrupts and the second plurality of interrupts are received by the first programmable interrupt controller; the first processor-interrupting signal is generated by the first programmable interrupt controller, the first processor-interrupting signal to interrupt the first processor of the plurality of processors and the first processor-interrupting signal to cause a third processor-interrupting signal to be generated, the third processor-interrupting signal to interrupt the second processor of the plurality of processors.