Patent ID: 8507994

Claim:
A memory cell configured to operate as part of a semiconductor device, the memory comprising: a first CMOS inverter comprising a first transistor of a P channel and a second transistor of an N channel; a second CMOS inverter comprising a third transistor of a P channel and a fourth transistor of an N channel; a first gate wiring connecting a gate of the first transistor and a gate of the second transistor; a second gate wiring connecting a gate of the third transistor and a gate of the fourth transistor; a first metal layer disposed on the first and second gate wirings and comprising a first wiring portion and a second wiring portion, the first wiring portion being connected to a drain of the first transistor, a drain of the second transistor and the second gate wiring, the second wiring portion being connected to a drain of the third transistor, a drain of the fourth transistor and the first gate wiring, the first wiring portion overlapping the second gate wiring at least partially, and the second wiring portion overlapping the first gate wiring at least partially; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer, wherein the first transistor and the second transistor do not overlap in plan view of the memory cell, and the third transistor and the fourth transistor do not overlap in the plan view.