Patent ID: 8374040

Claim:
A memory system comprising: a plurality of memory arrays comprising a plurality of memory cells, the memory cells characterized by a variable write time; a memory bus configured to receive write commands, the write commands comprising write addresses and data lines; a plurality of data buffers configured to communicate with the memory arrays, each data buffer associated with one of the memory arrays; an address buffer configured to communicate with the memory arrays and to store the write addresses, the address buffer comprising a plurality of dedicated address buffers, each dedicated address buffer associated with one of the memory arrays; a mechanism configured to receive a write command comprising a write address and a data line from the memory bus, to split the data line into a number of parts, to store parts of the data line in different data buffers, to store the write address in the address buffer, and to initiate writing the parts of the data line to the memory arrays at the write address; and a write completion signal configured to communicate with the memory arrays for receiving write completion signals from the memory arrays, wherein a write completion signal is generated by a memory array in response to the memory array completing a write of a part of the data line to the write address, the write command completed when the write completion signals specifying the write address have been received from all of the memory arrays.