Patent ID: 7593500

Claim:
An apparatus for coordinating triggering of analog-to-digital conversions relative to a pulse width modulation (PWM) cycle timing, comprising: a timer counter ( 1002 ) having a clock input; an add/subtract circuit ( 1006 ) having a control input coupled to an add control signal, wherein when the add control signal is asserted the add/subtract circuit ( 1006 ) adds and when not asserted subtracts; a compare circuit ( 1004 ) having a first input coupled to an output from the timer counter ( 1002 ) and a second input coupled to an output from the add/subtract circuit ( 1006 ); a first multiplexer ( 1008 ) having a control input coupled to a falling edge mode signal, an output coupled to a first input of the add/subtract circuit ( 1006 ); a trigger offset register ( 1012 ) having an output coupled to a second input of the add/subtract circuit ( 1006 ); a second multiplexer ( 1010 ) having a control input coupled to the add/subtract control signal, an output coupled to a first input of the first multiplexer ( 1008 ) and a second input coupled to a start time value of a PWM signal; an active duty cycle register ( 1018 ) having an output coupled to a second input of the first multiplexer ( 1008 ); an active period register ( 1020 ) having an output coupled to a first input of the second multiplexer ( 1010 ); a third multiplexer ( 1014 ) having a control input coupled to a current limit mode signal, a first input coupled to an output from the compare circuit ( 1004 ) and a second input coupled to a rising edge of a fault signal; and a pulse driver ( 1016 ) having a control input coupled to a pulse selection signal, a pulse input coupled to an output of the third multiplexer ( 1014 ) and an output coupled to a trigger input of an analog-to-digital converter (ADC).