Patent ID: 7096407

Claim:
A system comprising: a plurality of memory cartridges, wherein each of the memory cartridges comprises a plurality of N-bit wide memory devices; a plurality of first error-handling modules each comprising a first and second mode of operation, wherein each of the plurality of first error-handling modules is configured to detect data errors in each of the N-bit wide memory devices when the first error-handling module is in the first mode of operation and configured to detect multi-bit data errors in two adjacent nibbles in a 2*N-bit wide memory device when the first error-handling module is operating in the second mode of operation, and wherein each of the plurality of first error-handling modules produces a first output signal, wherein N is an integer equal to 4, 8, 16 or 32; a second error-handling module electrically coupled to each of the plurality of first error-handling modules and configured to correct the data errors detected in any of the plurality of first error-handling modules, wherein the second error-handling module produces a second output signal; and a splitting device coupled between the plurality of memory cartridges and the plurality of first error-handling modules and configured to receive a plurality of data bits from any one of the plurality of memory cartridges and distribute the plurality of data bits evenly among each of the error detection modules.