Patent ID: 7631146

Claim:
A processor, comprising: a cache way prediction unit for predicting at least one cache way for selection from among a plurality of cache ways without accessing an instruction cache, the cache way prediction unit including, a determiner for ANDing a logic state of a determination signal (TNT) indicating whether a branch instruction is predicted to branch, a branch signal (TB) indicating whether a next fetch address to be fetched in a subsequent processor cycle is a branch target address (TADR) and a subtag signal, with the determiner generating at least one cache way enable signal (ENWAY); a branch prediction unit for providing the branch target address (TADR), where the branch target address (TADR) provided by the branch prediction unit is used for determining the next fetch address and predicting the at least one cache way in the cache way prediction unit; and a fetch unit for outputting a current fetch address (FADR) for each current clock cycle in response to a program counter signal, where the fetch unit receives the branch target address (TADR) from the branch prediction unit.