Patent ID: 6930325

Claim:
An integrated circuit architecture comprising an array of vertical FET selection transistors formed in a substrate in the form of parallel active webs made of semiconductor material arranged in a lateral direction of the circuit, wherein selection transistor drain terminals are formed by conductive strips buried below the active webs, and wherein selection transistor gates are formed by a spacer etched vertically at the side of the active webs; an array of memory cells each comprising a storage capacitor, wherein a buried strip makes contact with an electrode of the storage capacitor; a wordline for the memory cells of the memory array formed by the vertically etched spacer, wherein each storage capacitor is formed in a deep trench, which in each case delimits on an end side a section of the active web that contains the selection transistor, and which is filled with conductive electrode material; and a test structure integrated into the integrated circuit architecture, wherein the test structure includes a connection for common connection of the drain terminals of a plurality of vertical selection transistors, as first connecting means, wherein the first connecting means comprises diagonally extended deep trenches filled with the conductive electrode material, deposed between two adjacent laterally offset vertical FET transistors, wherein the buried strips present there form drain electrodes of the vertical selection transistors at the intersection of the buried strip form with the diagonally extended deep trench and active web.