Patent ID: 7496872

Claim:
An interconnect capacitance estimation system, which estimates interconnect capacitance in a circuit, comprising: a first storage device configured to store layout data; a library creating device configured to read said layout data, create a library including a table used for estimating a capacitance of a net in a semiconductor circuit based on said read layout data, and store said library into a second storage device; and an interconnect capacitance estimating device configured to estimate a capacitance of a target net in a target semiconductor circuit based on design data of said target semiconductor circuit and said table in said library, wherein said library creating device calculates a logic cone size of a logic cone which is a combined circuit composing a signal path through which a signal passes from an input stage of said net to an output stage of said net, creates said table which relates a capacitance of said net, said logic cone size and a fan-out of said net, and stores said table into said library, and said interconnect capacitance estimating device calculates a logic cone size of a logic cone of said target net based on said design data, and estimates a capacitance of said target net based on said logic cone size of said target net and said table.