Patent ID: 7555513

Claim:
A single instruction multiple data (SIMD) processor comprising: an arithmetic logic unit (ALU) comprising: a plurality of logic blocks, each of said logic blocks comprising a first set of inputs and a second set of inputs; a plurality of first interconnects comprising Nxm i data lines, interconnecting a plurality of N data portions of a first operand to said first inputs of each of said logic blocks, thereby providing the same data to said first set of inputs of each of said logic blocks, wherein said first operand represents data in the form a(0)a(1)a(2). . . a(P−1) , wherein each a(i) represents one of said data portions of said first operand, and wherein said plurality of first interconnects provides N data portions of said data in the form, a(j)a(j+1). . . a(j+N−1), to said first set of inputs of each of said logic blocks, where P>N; a plurality of groups of second interconnects, each of said groups comprising Nxm 2 data lines and interconnecting a different subset of N data portions of a second operand to each of said second set of inputs of said plurality of logic blocks, with each of said subsets of N data portions of said second operand having data units in at least one other of said subsets of N data portions of said second operand, wherein said second operand represents data in the form x(0)x(1)x(2). . . wherein each x(i) represents one of said data portions of said second operand, and wherein each of said second group of interconnects provides a subset of said data portions in said second operand in the form x(n)x(n+1). . . x(n+N−1), to second inputs of an interconnected one of said logic blocks; wherein each of said logic blocks calculates, from data at its first and second inputs, a(j)*x(n)+a(j+1)*x(n+1) . . . +a(j+N−1)*x(n+N−1).