Patent ID: 8410545

Claim:
A semiconductor memory comprising: a semiconductor substrate; unit arrays obtained by arranging memory cell transistors in a column direction, and arranged in a row direction; a buried insulating film formed on a part of an upper surface of the semiconductor substrate; and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate, wherein each of the memory cell transistors comprises: a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction; a gate portion formed on a side surface of the channel region in the row direction; a gate insulating film formed in the direction perpendicular to the upper surface of the semiconductor substrate along the side surface of the channel region in the row direction; a floating gate electrode formed on an upper surface of the buried insulating film, and formed on the gate insulating film on the side surface of the channel region in the row direction; an inter-electrode dielectric formed on an upper end face of the floating gate electrode; a control gate electrode formed on an upper surface of the inter-electrode dielectric, and extending in the row direction; and a first element isolation insulating film formed between the floating gate electrodes of the memory cell transistors.