Patent ID: 7644333

Claim:
A built-in self-test circuit to test logic within an integrated circuit, comprising: a scan driver coupled to a circuit under test to generate a sequence of test patterns in a test of the integrated circuit; one or more scan chains in the circuit under test, the one or more scan chains for receiving the test patterns during loading of the test patterns and for outputting test responses; a scan monitor coupled to the circuit under test to receive the test responses output from the one or more scan chains; wherein the scan monitor comprises hold logic coupled to a signature generation element, wherein the hold logic suspends signature generation for one or more but not all test responses to a complete test pattern by holding a signature value in the signature generation element such that the signature value in the signature generation element does not change while signature generation is suspended, wherein the hold logic is configured to receive a set of signals generated in testing circuitry, the set of signals including a signal indicating a first test pattern of the sequence of test patterns, a signal indicating that a test is finished, an external hold signal, and a capture operation signal, and wherein the hold logic suspends signature generation in response to one or more signals of the set of signals generated in testing circuitry.