Patent ID: 7927932

Claim:
A method of fabricating a semiconductor device, comprising: forming a lower insulating layer on a semiconductor substrate; forming an upper channel body pattern on the lower insulating layer; forming a transfer gate pattern traversing the upper channel body pattern, the transfer gate pattern having a non-metal transfer gate electrode; implanting impurity ions into the upper channel body pattern using the transfer gate pattern as an ion implantation mask to form a source region and a drain region; forming an intermediate insulating layer on the transfer gate pattern, the upper channel body pattern, and the lower insulating layer; forming a metal node plug contacting the source region of the upper channel body pattern in the intermediate insulating layer; and forming a metal word line contacting at least one sidewall and an upper surface of the non-metal transfer gate electrode and an insulating spacer covering a sidewall of the metal word line in the intermediate insulating layer.