Patent ID: 7531436

Claim:
A method of forming a P-N junction within a semiconductor substrate, comprising: providing a crystalline semiconductor substrate having a first doping type; forming a gate stack over the substrate and patterning the stack to form gates; forming spacers adjacent the gate stacks; implanting a dopant of a second type to form deep source/drain implants; etching the spacers; performing a non-amorphous implanting dopant of the second type to form source/drain extension region tail implants having a depth within the substrate; after performing the non-amorphous implanting of dopant, forming an amorphous semiconductor layer having the second doping type within and overlying the source/drain extension region tail implants; and then, performing a low temperature anneal to cause epitaxial growth within the amorphous layer, wherein the region of amorphization and epitaxial growth does not extend to the depth of the source/drain extension region tail implant.