Patent ID: 8872748

Claim:
A liquid crystal display device comprising: a liquid crystal display panel on which a plurality of data lines and a plurality of gate lines cross each other, and having a common electrode; a timing controller that generates a gate timing control signal and a data timing control signal, wherein the gate timing control signal includes a first and second gate start pulses generated in one frame period, a gate shift clock, a first gate output enable signal and a second gate output enable signal, and wherein the data timing control signal includes a first source output enable signal and a second source output enable signal; a data driving circuit that supplies positive polarity/negative polarity analog video data voltages to the data lines when the first and second source output enable signals are input thereto at a same logic level, and supplies positive polarity/negative polarity black voltages to the data lines in response to a pulse of the second source output enable signal; a first gate drive IC that shifts the first and second gate start pulses in accordance with the gate shift clock, and sequentially supplies first gate pulses which are synchronized with the positive polarity/negative polarity analog video data voltages to the gate lines included in a first block of the liquid crystal display panel during a low logic period of the first gate output enable signal; and a second gate drive IC that shifts a first carry signal supplied from the first gate drive IC in accordance with the gate shift clock and sequentially shifts second gate pulses which are synchronized with the positive polarity/negative polarity black voltages to the gate lines included in a second block of the liquid crystal display panel during a low logic period of the second gate output enable signal, wherein a pulse width of the second source output enable signal is longer than that of the first source output enable signal, and a phase of the first source output enable signal is different from that of the second source output enable signal.