Patent ID: 7964899

Claim:
A semiconductor device comprising: a single MIS transistor including an active region formed in a semiconductor substrate, a gate electrode formed on the active region, and source and drain regions formed in the active region; a stress control film being in direct contact with the semiconductor substrate, the source region, the drain region, and the gate electrode, and covering the semiconductor substrate, the source region, the drain region, and the gate electrode; and an interlayer insulating film stacked on the stress control film to be in direct contact with the stress control film, wherein: a direction of length of a channel connecting the source region and the drain region is parallel to the <100> crystallographic axis of the semiconductor substrate, the stress control film has a pair of openings formed to sandwich the gate electrode of only the single MIS transistor such that both ends of the gate electrode in a gate width direction are located between the pair of openings when viewed in plan, and the interlayer insulating film and the semiconductor substrate are in direct contact with each other in the pair of openings.