Patent ID: 7875514

Claim:
A method, comprising: forming a compressive stress-inducing layer above first and second device regions of a semiconductor device, said first device region comprising one or more first transistors and said second device region comprising one or more second transistors; determining a difference of a deposition rate of an interlayer dielectric material when deposited on said compressive and tensile stress-inducing layers, said determined difference having a value other than zero; selecting a thickness of a buffer material on the basis of said determined difference; forming said buffer material having said selected thickness above said compressive stress-inducing layer; selectively removing a portion of said buffer material and a portion of said compressive stress-inducing layer from above said first device region; forming a tensile stress-inducing layer above said first and second device regions; selectively removing a portion of said tensile stress-inducing layer from above said second device region by using said buffer material as an etch stop material; and forming said interlayer dielectric material above said first and second device regions using said buffer material as a height leveling material for reducing a height difference of said first and second device regions.