Patent ID: 8285892

Claim:
An apparatus comprising: an arbiter circuit comprising a first sub-arbiter circuit and a second sub-arbiter circuit, wherein (A) said first sub-arbiter circuit is configured to determine a first winning channel from a plurality of channel requests based on a first criteria, (B) said second sub-arbiter circuit is configured to determine a second winning channel received from said plurality of channel requests based on a second criteria, and (C) each of said plurality of channel requests represent a burst of data having a fixed length aligned to an address boundary of a memory; a protocol engine circuit configured to (i) receive a signal from said arbiter circuit indicating said second winning channel and (ii) write data to a memory using a protocol having a granularity equal to said burst of data, wherein said protocol engine limits access to said granularity during each of a plurality of arbitration cycles; and a channel router circuit configured to present said plurality of channel requests to said arbiter circuit and said protocol engine circuit, wherein (A) said second sub-arbiter circuit is configured to further prioritize the order of said first second winning channel when determining said second winning channel by overriding said first winning channel if said second criteria creates a more efficient data transfer and (B) said second criteria of said second sub-arbiter circuit is different than said first criteria of said first sub-arbiter circuit to statistically trade off (i) client bandwidth, (ii) client latency, and (iii) memory protocol efficiency.