Patent ID: 7154323

Claim:
A delay circuit for receiving an objective signal at any unit delay unit of a plurality of unit delay units connected in series so as to provide a predetermined delay time, wherein each unit delay unit comprises: a first logical portion for propagating a signal inputted to a first input terminal and outputting a first propagation signal corresponding to a first unit selection signal indicating selective status; a second logical portion for propagating a signal inputted to a second input terminal and outputting a second propagation signal corresponding to a second unit selection signal indicating non-selective status, having the same propagation delay time as the first logical portion; and a third logical portion for propagating the first propagation signal outputted from the first logical portion and the second propagation signal outputted from the second logical portion and outputting a third signal to an output terminal; and wherein the delay circuit comprises an independent unit delay unit in which the objective signal is inputted to the first input terminal and which is maintained in a state in which signal propagation of the objective signal is possible, wherein a unit delay time in the unit delay unit is capable of being measured, wherein the objective signal being inputted to the first input terminal and the output terminal of the unit delay unit of a preceding stage being connected to the second input terminal.