Patent ID: 8370603

Claim:
A non-volatile memory (NVM) package, comprising: an interface configured to receive a block address; a plurality of concurrently addressable memory units each containing a plurality of blocks; and a processor configured to map the block address to a block in one of the plurality of concurrently addressable memory units; and a host interface configured to receive a host chip enable signal from a host, where the processor is further configured to map the host chi enable signal to a chip enable signal of a concurrently addressable memory unit, the internal chip enable signal configured to activate the concurrently addressable memory unit; wherein the processor is configured to map the block address to a block in one of the plurality of concurrently addressable memory units in dependence upon a map that includes a run parameter and a stride parameter, where the run parameter comprises a number of concurrently addressable memory units that are accessible using the host chip enable signal, and the stride parameter is the number of blocks for an operation command within a concurrently addressable memory unit.