Patent ID: 7827454

Claim:
A semiconductor device comprising: a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein each of said judging circuits comprises: a first register for capturing the data from said logic circuits in a predetermined timing of a clock signal; a delay unit for delaying said clock signal; a second register logically equivalent to said first register, for capturing the data from said logic circuits in a predetermined timing of said clock signal, which has passed through said delay unit; a comparator for comparing an output from said first register and an output from said second register to output an error signal; and a scanning unit for making said second register a shift register to transmit said error signal held in said second register to a subsequent stage with a comparison result of said comparator; wherein said scanning unit comprises a first multiplexer to which said error signal transmitted from said judging circuit of a previous stage, the data from said logic circuit and a mode signal are input, and a second multiplexer to which an output from said first multiplexer, said error signal output from said comparator and a reset signal are input, and wherein when malfunction occurs, capturing of said data to said second register is stopped by said first multiplexer based on said mode signal and any of said error signal transmitted from said judging circuit of the previous stage through said second multiplexer and said error signal output from said comparator is captured by said second register and is transmitted to said judging circuit of the subsequent stage.