Patent ID: 8232157

Claim:
A method comprising: forming a semiconductor substrate including a CMOS region and a bipolar region; forming a first isolation layer in the CMOS region and second and third isolation layers in the bipolar region; forming a first P well at one side of the first isolation layer and a first N well at an opposite side of the first isolation layer; forming a deep P well in the bipolar region and a second N well in the deep P well corresponding to one side of the second isolation layer; forming a first gate in the first N well and a second gate in the first P well; forming a first source/drain by implanting second type impurities into the first N well, and an emitter and a collector by implanting second type impurities into the deep P well and the second N well at both sides of the second isolation layer; and then forming a second source/drain by implanting the second type impurities into the first P well, and a base by implanting the second type impurities into the second N well at one side of the third isolation layer.