Patent ID: 8093719

Claim:
An integrated circuit device comprising: an active area on a die comprising circuitry configured to perform core functionality of the device; a seal ring including a plurality of seal ring metal layers encompassing the active area, the plurality of seal ring metal layers including at least a first seal ring metal layer overlying a surface of the die and a second seal ring metal layer above the first seal ring metal layer, the seal ring further including a first plurality of redundant vias extending from the first seal ring metal layer to the second seal ring metal layer, the first plurality of redundant vias spaced apart from one another about the seal ring; and a second plurality of redundant vias extending from the first seal ring metal layer to the surface of the die; and wherein the first plurality of redundant vias comprise widths greater than widths of the second plurality of redundant vias, the second plurality of redundant vias comprise a number of vias greater than a number of the first plurality of redundant vias.