Patent ID: 7417469

Claim:
A method for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits, said method comprising: coupling an automatic self-adaptive keeper to a Local Bitline (LBL) of an N-way register; coupling a dummy cell to the LBL, wherein the dummy cell is similarly configured to one way of the N-way register file: connecting a stage one current mirror (CM 1 ) having CM 1 transistors communicatively connected in a first configuration between the dummy cell and the self adaptive keeper; detecting current leakage from the N-way register file on the LBL using the dummy cell, wherein the dummy cell matches the leakage current detected on the LBL; reducing the leakage current effects by providing optimally controlled compensation current from the automatic self adaptive keeper; wherein the automatic self adaptive keeper comprises: a stage two current mirror (CM 2 ) having CM 2 transistors communicatively connected in a second configuration, relative to each other, which second configuration is similar to the first configuration, and wherein a drain of a first CM 2 transistor within the stage two current mirror is coupled to a drain of a first CM 1 transistor within the stage one current mirror; wherein the stage two current mirror operates in combination with the stage one current mirror to provide a two-stage current mirror; a feedback transistor connected at its drain to the LBL and at its source to the stage two current mirror; and a feedback (clock-controlled) NAND gate having a first input terminal that is connected to the LBL and a second input that is coupled to a delayed clock input, which is a delayed version of an input clock signal, wherein the feedback NAND gate further provides a NAND output that is connected to a gate terminal of the feedback transistor.