Patent ID: 8283263

Claim:
An integrated circuit method for manufacturing an integrated circuit system comprising: loading a wafer having a bottom silicon oxide layer thereover into a processing chamber; pre-purging the processing chamber before depositing a nitride layer with only a first ammonia gas; depositing a first nitride layer over the bottom silicon oxide layer and the wafer utilizing first source gases; purging the processing chamber with a second ammonia gas; depositing a second nitride layer directly on the first nitride layer that is misaligned with the first nitride layer by utilizing second source gases that are the same as the first source gases; post-purging the processing chamber with a third ammonia gas; purging the processing chamber with a nitrogen gas; and etching the first nitride layer and the second nitride layer without substantial damage to the bottom silicon oxide layer due to the misalignment of the first nitride layer and the second nitride layer.