Patent ID: 8680667

Claim:
A package stack structure comprising: an upper package comprising an upper package substrate having a first edge and a second edge opposite to the first edge, the upper package substrate having a first region arranged near the first edge and a second region arranged near the second edge, the upper package comprising a first upper semiconductor device overlying the upper package substrate; a lower package having a lower package substrate and a lower semiconductor device, the lower package connected to the upper package through a plurality of inter-package connectors, the inter-package connectors comprising: first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for a address/control circuit; fourth inter-package connectors configured to provide a supply voltage for a data circuit, wherein a majority of the first and second inter-package connectors are disposed in the first region, and wherein a majority of the third inter-package connectors are disposed in the second region.