Patent ID: 8830758

Claim:
A semiconductor storage device comprising: a plurality of memory cells formed for each column and each row, each being connected to a bit line at one end of a current path; and a sense amplifier reading out data held by the memory cell by comparing a first current flowing in the bit line in accordance with the data with a second current flowing in a reference signal line which is set as a comparison current for the first current, wherein the sense amplifier includes: a first MOS transistor having one end of a current path to which a first voltage is applied, the other end connected to a first node, and a gate to which a first signal is supplied; a second MOS transistor having one end of a current path connected to the first node, and the other end connected to a second node to which the reference signal line is connected, the second MOS transistor having one of a first supply ability and a second supply ability higher than the first supply ability in accordance with the data held by the memory cell; a third MOS transistor having one end of a current path connected to the first node, and the other end connected to a third node connected to the bit line, the third MOS transistor having one of a third supply ability and a fourth supply ability higher than the third supply ability in accordance with a current flowing in the reference signal line; and a switch unit configured to ground each of the second MOS transistor and the third MOS transistor when a second signal is supplied, wherein the first signal and the second signal are sequentially generated based on a same set of signals, the second signal being associated with the first signal, and the sense amplifier turns off the first MOS transistor after transferring the data read out from the memory cell to an outside, and then supplies the second signal to the switch unit to set gates of the second MOS transistor and third MOS transistor to ground potential.