Patent ID: 8878715

Claim:
A time-to-digital converting circuit that converts a time when a logic of a reference data signal changes in a reference period into a digital value, comprising: a first signal input terminal to which a reference data signal is input; a second signal input terminal to which a reference clock signal is input at a first point in time in the reference period; a first signal output terminal from which a first digital value, which is the most significant bit, is output; a second signal output terminal from which a second digital value, which is of a lower order than the first digital value, is output; a first flip-flop having a data terminal to which a signal based on the reference data signal input to the first signal input terminal is input, a clock terminal to which the reference clock signal input to the second signal input terminal is input, and an output terminal that is connected to the first signal output terminal and from which a first output signal is output; a first delay controlling circuit that outputs a first data signal obtained by controlling a delay time of the reference data signal input thereto via the first signal input terminal based on the first output signal and a first clock signal obtained by controlling a delay time of the reference clock signal input thereto via the second signal input terminal based on the first output signal; and a second flip-flop having a data terminal to which a signal based on the first data signal is input, a clock terminal to which the first clock signal is input, and an output terminal that is connected to the second signal output terminal and from which a second output signal is output; wherein the first delay controlling circuit: controls the delay time of the reference clock signal to be shorter than the delay time of the reference data signal if the logic of the reference data signal changes before or at the first point in time; and controls the delay time of the reference clock signal to be longer than the delay time of the reference data signal if the logic of the reference data signal changes after the first point in time.