Patent ID: 7137081

Claim:
A method, in a data processing system, for selecting buffer insertion locations within an integrated circuit design, comprising: obtaining a tiled directed acyclic graph (DAG) of a portion of the integrated circuit design, wherein the tiled DAG includes a plurality of tiles; associating a first cost with each tile of the tiled DAG, wherein the first cost associated with a tile is based on a characteristic of the tile that is representative of suitability of the tile for buffer insertion; selecting a subset of tiles from the plurality of tiles based on the first cost associated with each tile, wherein the subset of tiles are candidate buffer insertion tiles; and associating a second cost with paths to each tile of the tiled DAG, wherein the second cost associated with the paths to each tile is representative of a cost due to a deviation from a symmetric distribution of buffer insertion points, and wherein the subset of tiles are selected based on both the first cost associated with each tile and the second cost associated with paths to each tile, wherein the first cost is a first function of the area density of the tile, and wherein the second cost is a second function of a difference between a spacing of the tile from a previously selected candidate buffer insertion tile, and a symmetrical spacing from the previously selected candidate buffer insertion tile.