Patent ID: 8780643

Claim:
A method comprising: storing first adjustment data at a first output timing adjustment circuit of a first memory chip; storing second adjustment data at a second output timing adjustment circuit of a second memory chip; accessing a memory cell array at the first memory chip to produce read data in response to receiving an access command at an access control circuit at the first memory chip; producing an output clock signal at the first output timing adjustment circuit on the first memory chip in response to the first adjustment data stored in the first output timing adjustment circuit; clocking a data output circuit coupled between the memory cell array and a plurality of data terminals at the first memory chip with the output clock signal to enable output data based on the read data to appear at the plurality of data terminals after a predetermined period of time from receiving the access command, the predetermined period of time being adjustable in accordance with the first adjustment data; and selecting the first memory chip from a plurality of memory chips to transfer the output data from the plurality of data terminals to a plurality of data paths shared by the plurality of memory chips; where the first and second adjustment data are different from each other so that a delay time from when the access command is received at the first memory chip until when the output data appears at the plurality of data terminals of the first memory chip matches a delay time from when the access command is received at the second memory chip until when the output data appears at the plurality of data terminals of the second memory chip.