Patent ID: 7716455

Claim:
A method of operating a processor to execute a plurality of instructions, each instruction operating on at least one operand associated with the instruction, the method comprising: loading a first page comprising a first portion of the plurality of instructions; evaluating a condition following execution of the first portion of the plurality of instructions and selectively loading one of a second page or a third page based on the evaluating, each of the second and third page being identified by a same common tag value, and wherein: instructions at corresponding offsets in the second and third pages operate on the same operands; and executing the first portion of the plurality of instructions comprises: a) executing a first instruction in the first portion of the plurality of instructions to generate a first result; b) prior to selectively loading the second page or the third page, buffering the first result with an indication that it is an operand for an instruction at an offset within a page having the common tag value; c) upon selectively loading the second page or the third page, making the first result available to a child instruction at the offset in the selectively loaded one of the second page or the third page by transferring the first result from the buffer to a location associated with the offset; d) selecting the child instruction on the page that is selectively loaded as a second instruction; and e) when the second instruction uses an operand, executing the second instruction using the first result as an operand, whereby the first result can be buffered for use in execution of an instruction in a second page or a third page that is conditionally loaded before an evaluation of a condition indicating whether to selectively load the second page or the third page.