Patent ID: 8635476

Claim:
A multi-core processor comprising: a plurality of enabled physical processing cores; a configurable resource shared by two or more of the cores, wherein configurations of the shared resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate; for each core, internal core power state management logic configuring the core to participate in a de-centralized inter-core power state discovery process carried out between the cores without the assistance of centralized non-core logic; wherein the internal core power management logic is duplicated in each core; wherein the internal core power management logic configures the core to instigate implementation of a composite target power state for configuring the shared resource, if the core is designated as a master core for the purpose of configuring the shared resource and the composite target power state is discovered through the de-centralized inter-core power state discovery process; wherein the composite target power state is a most power-conserving power state for the shared resource that will not interfere with any corresponding target power state of each core sharing the resource.