Patent ID: 7863990

Claim:
An oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, comprising: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage and starts new oscillation; a phase comparing section that phase compares a comparison signal having a phase in accordance with the oscillation signal outputted from the voltage control oscillation section with a signal having a phase in accordance with the reference clock; a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section; a pulser that outputs a pulse signal having a predetermined pulse width according to the edge of the reference clock, wherein the voltage control oscillation section stops generation of the oscillation signal in accordance with a leading edge of each pulse of the pulse signal, and starts generating a new oscillation signal in accordance with a trailing edge of each pulse of the pulse signal, the phase comparing section phase compares the comparison signal with the pulse signal; the voltage control oscillation section includes a plurality of NAND circuits, the NAND circuits connected into a loop including a first NAND circuit in the leading end and a second NAND circuit in the trailing end, each of the NAND circuits having a delay amount that changes according to the control voltage, the voltage control oscillation section outputs a signal outputted from any of the NAND circuits, as the oscillation signal, the pulser outputs a pulse signal indicating a logical value L during a period of the predetermined pulse width from the timing of the edge of the reference clock, the first NAND circuit outputs a NAND between the signal outputted from the second NAND circuit and the pulse signal, to the NAND circuit in the subsequent stage, the second NAND circuit outputs a NAND between the signal outputted from the NAND circuit in the preceding stage and the pulse signal, as the loop signal, to the first NAND circuit, and the second NAND circuit includes: a loop output circuit that outputs, to the first NAND circuit, the NAND between the signal outputted from the NAND circuit in the preceding stage and the pulse signal, as the loop signal; and a comparison output circuit that outputs, to the phase comparing section, a NAND between the signal outputted from the NAND circuit in the preceding stage and a logical value H, as the comparison signal.