Patent ID: 7954024

Claim:
A process of operating an internal scan test port and a test access port, comprising: A. initially enabling the test access port and disabling the scan test port; B. applying a clock signal to a combined test clock and clock input lead; C. applying a select signal to a combined test mode select and capture select lead; D. shifting instruction register data, that includes lock in data, along a combined test data input and scan input lead to an instruction register of the test access port; E. selecting the scan test port and disabling the test access port by applying a lock in signal from the lock in data in the instruction register to a flip flop, and then clocking the flip flop with an update instruction register signal from a test access port controller; and D. shifting test data into an internal scan register of the internal scan test port on the combined test data input and scan input lead, capturing test data in the internal scan register, and shifting test data out of the internal scan register on a combined test data output and scan output lead in response to a clock signal on the combined test clock and clock input lead and a select signal on the combined test mode select and capture select lead.