Patent ID: 7875551

Claim:
A method of forming an integrated circuit device, comprising: forming an interlayer insulating layer on a semiconductor substrate, said interlayer insulating layer comprising a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer; forming a contact hole that extends through the interlayer insulating layer and exposes the semiconductor substrate, by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material; partially filling the contact hole within the first electrically insulating layer with a sacrificial layer; forming a spacer layer on an upper surface of the sacrificial layer and on exposed portions of sidewalls of the first electrically insulating layer and on exposed portions of a lower surface of the second electrically insulating layers; selectively etching back the spacer layer for a sufficient duration to expose the sacrificial layer and define a spacer on an upper portion of the sidewall of the first electrically insulating layer that is recessed relative to the sidewall of the second electrically insulating layer within the contact hole; selectively removing the sacrificial layer to expose the semiconductor substrate and a lower portion of the sidewall of the first electrically insulating layer that is recessed relative to an inner sidewall of the spacer; and then filling the contact hole with an electrically conductive plug.