Patent ID: 8644439

Claim:
A circuit for transferring signals from a source clock domain to a destination clock domain, the circuit comprising: a first pulse generation circuit, actually and positively operating in the source clock domain, configured to generate a source data pulse from a source data signal; a hold flip-flop circuit, actually and positively operating in the source clock domain, configured to hold the source data pulse received from the first pulse generation circuit at an output of the hold flip-flop circuit; a clocked synchronizer circuit, actually and positively operating in the destination clock domain, configured to sample the source data pulse received from the output of the hold flip-flop circuit, wherein the source data pulse held at the output of the hold flip-flop circuit is configured to be clear when the source data pulse is sampled at an output of the clocked synchronizer circuit; and a second pulse generation circuit, actually and positively operating in the destination clock domain and coupled with the clocked synchronizer circuit, configured to generate a destination data pulse in response to the sampled source data pulse received from the output of the clocked synchronizer circuit.