Patent ID: 8018791

Claim:
A latency control system comprising: a clock synchronization circuit having at least one input to which an input clock signal is applied, and at least one output at which an output clock signal is provided, the clock synchronization circuit operable to adjust a timing of the output clock signal so that the output clock signal is synchronized with the input clock signal, the clock synchronization circuit being further operable to provide an upstream clock signal having a first timing relative to the timing of the input clock signal and a downstream clock signal having a second timing relative to a timing of the output clock signal; and a latency control circuit coupled to receive the upstream clock signal and the downstream clock signal from the clock synchronization circuit, and further configured to receive a latency value and to capture a command signal in response to the upstream clock signal and output the command signal in response to the downstream clock signal in a manner that causes the outputting of the command signal to be at a time determined by the latency value and to be synchronized with the output clock signal.