Patent ID: 7656731

Claim:
A memory circuit comprising: first global read line; a second global read line; a first sense amplifier having a first output lead and a second output lead; a second sense amplifier having a first output lead and a second output lead; a first discharge circuit that discharges the first global read line toward a first potential if a first digital logic value is present on either the first output lead of the first sense amplifier or the first output lead of the second sense amplifier; and a second discharge circuit that discharges the second global read line toward the first potential if the first digital logic value is present on either the second output lead of the first sense amplifier or the second output lead of the second sense amplifier; wherein the first discharge circuit includes only one transistor that is coupled to the first global read line, and wherein the second discharge circuit includes only one transistor that is coupled to the second global read line.