Patent ID: 7908461

Claim:
A cellular engine for a data processing system, said engine comprising: an associative memory device having n-cells, each of said n-cells being able to store m bits; a vector memory containing p-vectors, each of said p-vectors having a storage capacity of n×m-bits; a control interconnection network that for each of said n-cells generates a classification code that classifies a cell in dependence upon a local state and a global state of said cell; an instruction register for accepting an instruction issued from a controller; a clock device for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second, said clock device outputting said synchronizing clock signal to said associative memory device and said vector memory; and wherein said engine globally communicates said instruction to all of said n-cells simultaneously within one of said clock cycles, said instruction being executed in parallel by selected cells within said associative memory device, all within one of said clock cycles, in accordance with said classification of each of said n-cells by said control interconnection network.