Patent ID: 8477898

Claim:
A phase-locked loop (PLL), comprising: a 1/N frequency divider, wherein N is an integer; a voltage-controlled oscillator (VCO) configured to receive a control voltage and generate an output clock signal of frequency f syn based partly or solely on the control voltage; a programmable phase mixer coupled between an output of the VCO and an input of the 1/N frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f 1 by varying a phase difference between the output clock signal and the first clock signal; wherein the 1/N frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f 2 =f 1 /N; a phase detector configured to receive a reference clock signal of frequency f ref and the second clock signal from the 1/N frequency divider, and produce a phase error by comparing frequency f ref with frequency f 2 , wherein the phase error is used to update the control voltage so that frequency f 2 is synchronized to frequency f ref ; and a controller coupled to the programmable phase mixer, wherein the controller sends a control signal to the programmable phase mixer to control a phase offset produced by the programmable phase mixer; wherein the controller receives a control clock signal of frequency f dig , and wherein the phase offset is computed by evaluating an expression that comprises f syn , N, f ref , and f dig .