Patent ID: 6934921

Claim:
A method for resolving timing violations introduced by a logic built-in self test (LBIST) sub-circuit formed within an underlying integrated circuit, said method comprising: analyzing a circuit path-list corresponding to said integrated circuit for timing violations and generating a primary timing violations analysis output; generating a first netlist with LBIST based on said circuit path-list and an LBIST path-list corresponding to said LBIST sub-circuit; analyzing said first netlist with LBIST for timing violations and generating a secondary timing violations analysis output; comparing said secondary timing violations analysis output with said primary timing violations analysis output; generating an LBIST insertion constraint file based on said comparing; and generating a second netlist with LBIST based on said circuit path-list, said LBIST path-list, and said constraints file wherein said timing violations introduced by said LBIST sub-circuit are resolved in said second netlist with LBIST.