Patent ID: 8402402

Claim:
A method for determining simultaneous switching noise for multiple Input/Output (I/O) standards for an integrated circuit design, said method comprising: modeling a first I/O noise from a first I/O standard and modeling a second I/O noise from a second I/O standard, with the first I/O standard and the second I/O standard specifying at least one from a set consisting of: a voltage, a drive strength, a mode, and a termination for pins of the integrated circuit design; determining a greater contributor to an amount of noise at a first pin location between said first I/O noise and said second I/O noise; assigning to the first pin location, after the determining, one of the first I/O standard or the second I/O standard, wherein the assigning is based on the greater contributor to the amount of noise at the first pin location; repeating the determining and the assigning for remaining successive pin locations, wherein each pin location having one of the first I/O standard or the second I/O standard so assigned acts as a previously assigned pin during the determining for the remaining successive pin locations, and the determining for each successive pin location is based on accumulating an amount of noise contributed from each such previously assigned pin; and providing I/O standard assignments for each pin location for the integrated circuit design, wherein at least one of the modeling, determining, assigning, or repeating is executed through a processor.