Patent ID: 7876547

Claim:
A vertical parallel plate capacitor structure comprising: a first metallization layer including a first insulating layer, a first conductive-plate, and a second conductive plate, the first and second conductive plates in the first metallization layer laterally spaced apart within the first insulating layer by a first relative distance; a second metallization layer including a second insulating layer, a first conductive plate, and a second conductive plate, the first conductive plate in the second metallization level having a directly overlying relationship with the first conductive plate in the first metallization level and the second conductive plate in the second metallization level having a directly overlying relationship with the second conductive plate in the first metallization level, and the first and second conductive plates in the second metallization level laterally spaced apart within the second insulating layer by a second relative distance greater than the first relative distance; a third insulating layer between the first metallization level and the second metallization level; one or more first conductive plugs physically and electrically coupling the first conductive plate in the first metallization level with the first conductive plate in the second metallization level, the one or more first conductive plugs extending through the third insulating layer from the first conductive plate in the first metallization layer to the first conductive plate in the second metallization layer; one or more second conductive plugs physically and electrically coupling the second conductive plate in the first metallization level with the second conductive plate in the second metallization level, the one or more second conductive plugs extending through the third insulating layer from the second conductive plate in the first metallization layer to the second conductive plate in the second metallization layer; a first electrical connection with the first and second conductive plates in the first metallization layer, the first electrical connection configured to electrically bias the first and second conductive plates in the first metallization layer with a positive potential; and a second electrical connection with the first and second conductive plates in the second metallization layer, the second electrical connection configured to electrically bias the first and second conductive plates in the second metallization level with a negative potential.