Patent ID: 6933176

Claim:
A process for manufacturing an integrated circuit package comprising: mounting a semiconductor die, to a first surface of a substrate such that bumps on said semiconductor die are electrically connected to conductive traces of said substrate; mounting at least one collapsible spacer to at least one of a heat spreader, said semiconductor die and said substrate; fixing said heat spreader to at least one of said first surface of said substrate and said semiconductor die such that said at least one collapsible spacer is disposed therebetween; forming a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces; and singulating said Integrated circuit package, wherein fixing said heat spreader comprises: placing one of said heat spreader and said substrate in a mold cavity of a mold; releasably clamping the other of said heat spreader and said substrate to a die of said mold cavity, such that said at least one collapsible spacer is disposed between said heat spreader and said substrate; and molding a molding compound in the mold cavity, thereby molding the semiconductor die, the substrate, said at least one collapsible spacer and said heat spreader into the molding compound to provide a molded package.