Patent ID: 7571400

Claim:
A chip design verifying and chip testing apparatus, comprising: a computer comprising: a storing means for storing an input file, an output file, and an application program being for verifying and testing operation of a designed chip and a manufactured chip which have a plurality of functional blocks; an interface means controlling data transmission between the storing means and the chip; and a CPU for executing and controlling the application program, wherein, when the application program is executed, a graphic user interface is displayed on a monitor of the computer, and one of a verifying mode or a testing mode is set through the graphic user interface, and results are displayed through windows, wherein the interface means includes: a data applying means having first and second memories for storing the input file outputted from the storing means and applying the stored result to the chip, the data applying means in the verifying mode alternately storing data dividing data constituting the input file stored in the storing means into a predetermined unit in the first and second memories and alternately applying the data stored in the first and second memories to the chip, and the data applying means in the testing mode storing all data constituting the input file stored in the storing means in the first and second memories and applying the data stored in the first and second memories to the chip; and a data storing means having third and fourth memories for storing data outputted from the chip, the data storing means in the verifying mode alternately storing the data applied from the chip in the third and fourth memories and alternately outputting the data stored in the third and fourth memories to the graphic user interface, and the data storing means in the testing mode storing the data applied from the chip in the third and fourth memories and outputting the data stored in the third and fourth memories to the graphic user interface; and a controlling means for controlling data transmission between the storing means and the data applying means, between the data applying means and the chip, between the chip and the data storing means, and between the data storing means and the storing means, wherein the test mode is performed with the input file and the output file obtained after completing the verifying mode.