Patent ID: 8258053

Claim:
A method of forming a transistor, the method comprising: performing a first deposition process to form a first sub-layer of a spacer layer above an active region and a gate electrode structure formed on said active region, said gate electrode structure comprising a high-k dielectric material and a dielectric cap material formed on an electrode material, wherein forming said first sub-layer comprises providing a first precursor so as to form a preform of said first sub-layer and subsequently providing a second precursor to form at least a portion of said first sub-layer; performing a second deposition process to form a second sub-layer of said spacer layer on said first sub-layer; forming a spacer from said spacer layer; replacing a portion of said active region with a strain-inducing semiconductor material by using said spacer and said dielectric cap material as a mask; removing said spacer and said dielectric cap material; and forming drain and source regions in said active region.