Patent ID: 7728437

Claim:
A semiconductor package comprising: a semiconductor chip comprising a top surface and a bottom surface, the bottom surface having a plurality of bumps formed thereon; redistribution layer patterns formed under the semiconductor chip, comprising a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part; a patterned insulating layer formed below the redistribution layer patterns, exposing at least a part of the second part of the redistribution layer patterns; an encapsulation layer exposing a bottom surface of the patterned insulating layer and surrounding the semiconductor chip, the bumps, and the redistribution layer patterns; and an organic insulating layer interposed between the redistribution layer patterns and the semiconductor chip, having electrically conductive particles distributed in the organic insulating layer, wherein the electrically conductive particles are interposed between top surfaces of the first parts of the redistribution layer patterns and bottom surfaces of the bumps to directly contact the top surfaces of first parts of the redistribution layer patterns and the bottom surfaces of the bumps.