Patent ID: 8361841

Claim:
An MAP method comprising: providing a substrate strip including a plurality of substrate units arranged in an N by M matrix and a plurality of scribe lines defined between adjacent substrate units and at the peripheries of the matrix, wherein the substrate units have a same dimension corresponding to the dimension of a semiconductor package; pre-singulating the substrate units so that the substrate strip has a plurality of pre-cut grooves formed between adjacent substrate units and at the peripheries of the matrix, wherein the width of the pre-cut grooves is greater than the width of the corresponding scribe lines to expose a plurality of cut edges of the substrate units out of the scribe lines; disposing a plurality of chips on the substrate units; electrically connecting the chips to the substrate units; forming an encapsulant on the N by M matrix of the substrate strip by molding to continuously encapsulate the substrate units and to cover the scribe lines, wherein the encapsulant fills into the pre-cut grooves and further encapsulates the cut edges of the substrate units; and removing a portion of the encapsulant within the scribe lines to divide the N by M matrix into separate semiconductor packages corresponding to the substrate units with the cut edges of the substrate units still encapsulated by remains of the encapsulant.