Patent ID: 7161432

Claim:
A current mirror circuit, comprising: a current input node for receiving an input current to be mirrored; an upper current mirror, comprising: first and second transistors (MP 1 ,MP 2 ) having respective current circuits and control inputs, said first and second transistors connected in a cascode configuration between a supply voltage and a first node ( 30 ), their current circuits connected together at said current input node; and third and fourth transistors (MP 3 ,MP 4 ) having respective current circuits and control inputs, said third and fourth transistors connected in a cascode configuration between said supply voltage and a second node ( 32 ) with their current circuits connected together at a third node ( 34 ), said first and third transistors' control inputs connected together and to said first node, and said second and fourth transistors' control inputs connected together such that said first, second, third and fourth transistors form a cascoded current mirror which mirrors the current conducted by said first and second transistors to said second node; a lower current mirror connected to receive the current at said second node and to mirror said current to said first node to provide positive feedback to said upper current mirror, said upper and lower mirrors arranged such that the net loop gain is between zero and one, such that the current (i out ) conducted by said third and fourth transistors is proportional to said input current (i in ) applied to said current input node; and a means for biasing said first, second, third and fourth transistors such that the voltages at said current input node and said third node are substantially closer to said supply voltage than the voltages at the control inputs of said first and third transistors.