Patent ID: 7041534

Claim:
A method for manufacturing semiconductor chip packages, the method comprising the steps of: forming a first dielectric layer on an upper surface of a semiconductor wafer comprising a plurality of semiconductor chips each having a first bonding pad and a plurality of second bonding pads disposed on the upper surface of the semiconductor wafer; forming a plurality of first openings in the first dielectric layer to expose the first bonding pads of the semiconductor chips from the first dielectric layer; forming a first conductive metal layer on the first dielectric layer and the first bonding pads by plating or depositing; selectively etching the first conductive metal layer to form a plurality of second openings at locations corresponding to the second bonding pads; forming a second dielectric layer on the first conductive metal layer and the second openings; forming a plurality of third openings in the first dielectric layer and the second dielectric layer to expose the second bonding pads of the semiconductor chips from the first dielectric layer and the second dielectric layer wherein the third openings are smaller than the second openings such that the first conductive metal layer is not exposed in the third openings; forming a fourth opening in the second dielectric layer to expose a portion of the first conductive metal layer from the second dielectric layer; forming a second conductive metal layer on the second dielectric layer, the second bonding pads exposed in the third openings and the first conductive metal layer exposed in the fourth opening by plating or depositing; selectively etching the second conductive metal layer to form a plurality of conductive traces extending on the second dielectric layer and the second bonding pads exposed in the third openings or extending on the second dielectric layer and the first conductive metal layer exposed in the fourth opening; forming a third dielectric layer on the second dielectric layer and the conductive traces; forming a plurality of fifth openings in the third dielectric layer to expose a portion of each of the conductive traces from the third dielectric layer; forming a plurality of external contacts on the exposed portions of the conductive traces; and cutting the semiconductor wafer such that the semiconductor chips are separated from each other thereby obtaining the semiconductor chip packages.