Patent ID: 7747920

Claim:
A method for using a unified test controller to test and diagnose a plurality of clock domains in a scan-based integrated circuit in selected self-test or scan-test mode, the unified test controller having a global scan enable (GSE) signal and a test clock, each domain having a system clock, a scan clock, a scan enable (SE) signal, and a plurality of scan cells connected to form one or more scan chains; said method comprising the steps of: (a) concurrently shifting a test stimulus into all said scan chains of each said clock domain by using said unified test controller to clock said scan clock controlling each said clock domain at a shift clock speed, selectively derived from said test clock or said system clock of said clock domain, for a predetermined number of shift clock cycles, when said global scan enable (GSE) signal is set to logic value 1 during a shift-in operation; (b) capturing a test response into said scan chains of each said clock domain in an ordered sequence by using said unified test controller to clock said scan clock controlling each said clock domain at a selected capture clock speed, selectively derived from said test clock or said system clock of said clock domain, for a predetermined number of capture clock cycles, when said global scan enable (GSE) signal is set to logic value 0 during a capture operation; and (c) concurrently shifting said test response out of all said scan chains of each said clock domain for comparison or compaction by using said unified test controller to clock said scan clock controlling each said clock domain at a shift clock speed, selectively derived from said test clock or said system clock of said clock domain, for said predetermined number of shift clock cycles, when said global scan enable (GSE) signal is set to logic value ‘1’ during the shift-out operation.