Patent ID: 7035152

Claim:
An address decoder receiving address signals and selecting a memory element in response to the address signals, the address decoder comprising: a first plurality of decoder circuits configured to select a memory element for an access operation according to the address signals; a plurality of redundancy circuits, each redundancy circuit having a set of programmable elements for programming a redundancy address corresponding to a memory element selected by one of the first plurality of decoder circuits; a second plurality of decoder circuits coupled to the plurality of redundancy circuits and configured to select a redundancy element for the access operation in response to receiving address signals matching one of the redundancy addresses programmed in the redundancy circuits; and a decoder disable circuit coupled to the first plurality of decoder circuits and further coupled to the plurality of redundancy circuits, based on the redundancy addresses programmed in the redundancy circuits, the decoder disable circuit configured to selectively and concurrently disable the decoder circuits of the first plurality that select the memory elements corresponding to the redundancy addresses programmed in the redundancy circuits.