Patent ID: 7480195

Claim:
A method of testing a memory device, comprising: loading data values into an array of memory cells of the memory device, the array arranged in rows and columns; reading data values for a plurality of columns of the array; loading data values into a plurality of output latches from a source other than the array, the data values loaded into the plurality of output latches corresponding to expected data values for the plurality of columns; and comparing the data values read from the array with their expected data values, wherein the comparison is performed in the data path between the array and the output latches; wherein comparing a given data value read from the array with its expected data value comprises receiving the given data value read from the array at a first input coupled to a first location of the data path and receiving its expected data value at a second input coupled to a second location of the data path; and wherein the first location of the data path and the second location of the data path are selectively coupled to one another such that data signals may pass from the first location to the second location during a read operation of the memory device.