Patent ID: 7851856

Claim:
A semiconductor chip scale package (CSP) comprising: a semiconductor substrate; a semiconductor device including a discrete metal oxide semiconductor field effect transistor (MOSFET) having a plurality of cells formed in an active area of the semiconductor substrate; a source region disposed on a bottom of the substrate that is common to all the cells in the plurality, wherein each cell in the plurality comprises: a drain region disposed on a top of the semiconductor device; a gate configured to control a flow of electrical current between the source region and the drain region when a voltage is applied to the gate; a source contact located proximate the gate; and an electrical connection formed through the substrate between the source contact and the source region; at least one drain pad electrically coupled to the drain regions; at least one source pad electrically connected to the source region wherein the source pad is biased to the substrate; at least one gate pad electrically coupled to the gates; a drain metal substantially covering the entire active area; a buried body-source short structure connected to the source pad, wherein the buried body-source short structure runs beneath the drain metal; wherein the drain, source and gate pads are formed on one surface of the semiconductor device; wherein the plurality of cells are distributed across the substrate, whereby the electrical connections formed between the source contact of each semiconductor device and the source region are distributed across the substrate; wherein the drain pads are formed on the active area of the semiconductor package; wherein the source and gate pads are formed on a termination area of the semiconductor package that is outside the active area.