Patent ID: 8837221

Claim:
A random-read NOR flash memory array comprising one or more memory sectors, each sector comprising N+1 word lines; K local sub-bit lines, which are perpendicular to the word-lines; K local sub-source lines, which are perpendicular to the word-lines; (K+1)/2 global bit lines, wherein every two sub-bit lines are decoded to form one of said global bit lines; (K+1)/2 global source lines, wherein every two sub-source lines are decoded to form one of said global source lines; and (N+1)/2×K flash memory cells, wherein each flash memory cell is a NAND-based N-channel 2T-string NOR flash memory cell device storing two bits, and wherein said cells can be coupled with appropriate bias condition in circuit for respective operation, comprising: a first and a second storage NMOS transistor in series without common source line; a drain/source node, which is connected to a corresponding local sub-bit line, wherein the local sub-bit line and a local sub-source line are perpendicular to word lines; a source/drain node, which is connected to the corresponding local sub-source line; a first word line terminal, which is connected to a word line corresponding to the first transistor; a second word line terminal, which is connected to a word line corresponding to the second transistor; two gates of said two transistors, each transistor comprising a gate dielectric layer underneath of each of said gates, a floating gate underneath of each said dielectric layer, and a tunnelling oxide layer underneath of each of floating gates; a common triple P-well region underneath said tunnelling oxide layers comprising a N+ drain/source region connected to said drain/source node, and a N+ source/drain region connected to said source/drain node; a deep N-well region underneath the triple P-well region; and an active P-SUB region underneath the deep N-well region.