Patent ID: 7002864

Claim:
An SRAM-compatible memory device including DRAM cells arranged in a matrix form defined by rows and columns, and externally interfacing with an external system in which no timing period is provided for performing a refresh operation of the DRAM cells, the SRAM-compatible memory device comprising: first and second memory blocks each having the DRAM cells; first data lines for transferring data fetched from or to be written in a DRAM cell in the first memory block; second data lines for transferring data fetched from or to be written in a DRAM cell in the second memory block; a first sense amplifier for amplifying and latching data in the first data lines; a second sense amplifier for amplifying and latching data in the second data lines; a third sense amplifier for amplifying and latching data provided via the first data lines or the second data lines; a first switching unit for controlling an electrical connection between the first data lines and the third sense amplifier; and a second switching unit for controlling an electrical connection between the second data lines and the third sense amplifier.