Patent ID: 7280378

Claim:
A content addressable memory (CAM) cell comprising: a semiconductor substrate including a plurality of active zones; a first memory circuit comprising first and second sets of transistors for the storage of first and second compare data; a second memory circuit comprising first and second sets of transistors for the storage of data for enabling or disabling the CAM cell; and a comparison circuit for receiving first and second input data, and coupled to said first memory circuit for receiving the first and second compare data, and coupled to said second memory circuit for receiving an output signal therefrom, said comparison circuit comprising first and second sets of comparison transistors which respectively provide for comparison of the first and second compare data with the first and second input data under control of the output signal from said second memory circuit; said first and second sets of transistors of said first memory circuit and of said second memory circuit each comprising at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; the transistors of the second conductivity type on a same first active zone of said semiconductor substrate, and the transistors of the first conductivity type of said first set of transistors and of said second set of transistors of said first and second memory circuits on second and third active zones, respectively, being separated by said first active zone; said first and second sets of comparison transistors of said comparison circuit are on fourth and fifth active zones, respectively, being mutually separated from the first active zone.