Patent ID: 7284080

Claim:
A method of managing a memory bus, the method comprising: receiving a first memory access request from a first request agent that represents a first functional device and a second memory access request from a second request agent that represents a second functional device; loading a first access priority value into a first counter timer, wherein the first access priority value corresponds to a processing function that is provided by the first functional device; loading a second access priority value into a second counter timer, wherein the second access priority value corresponds to a different processing function that is provided by the second functional device; loading a timer resolution parameter into a control register, wherein the timer resolution parameter relates to an amount of time associated with a first counting cycle of the first counter timer and a second counting cycle of the second counter timer; dynamically adjusting a plurality of priority access values that includes the first priority access value and the second priority access value, wherein the plurality of priority access values are stored in the control register; and dynamically adjusting the timer resolution parameter based on the activity level of the memory bus; wherein the first functional device accesses the memory bus before the second functional device when the first access priority value represents a higher priority than the second access priority value; and wherein the second functional device accesses the memory bus before the first functional device when the second access priority value represents a higher priority than the first access priority value.