Patent ID: 7292177

Claim:
An asynchronous counter circuit that is allowed to selectively perform counting in an up-count mode or counting in a down-count mode, the counter circuit comprising an initial-value setting processor that sets a count value immediately before switching of count mode as an initial value at a time of the switching of the count mode before starting counting after the count mode is switched, wherein, a plurality of flip flops as basic elements of the counter are cascaded with each other, the initial-value setting processor includes a switching processor provided between the flip-flops cascaded with each other, the switching processor allows switching of the count mode by selecting a non-inverting output or an inverting output of a preceding flip-flop as a counter clock and supplying the counter clock to a clock terminal of a succeeding flip-flop, and the switching processor setting the count value immediately before the switching of the count mode to the succeeding flip-flop as an initial value.