Patent ID: 7397276

Claim:
A programmable logic device comprising: a plurality of programmable logic blocks; a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices comprising at least a first and a second slice each having at least a first lookup table, and wherein at least one of the programmable logic blocks comprises at least a first logic block slice, a second logic block slice, and a third logic block slice; wherein the first logic block slice is a logic block slice type different from the second logic block slice, and the third logic block slice is a logic block slice type different from the first and second logic block slices; and control logic adapted at a programmable logic block level to provide at least one of bundled and unbundled control signals at a logic block slice level for at least two of the logic block slices, wherein a number of the control signals available at the programmable block level is less than a number of control signals required by all of the logic block slices, and wherein at least some of the control signals are shared between different ones of the logic block slices.