Patent ID: 8132321

Claim:
A method for defining an embedded circuit structure, comprising: providing a substrate, wherein a first patterned conductive layer is disposed on said substrate; forming a first dielectric layer to cover said first patterned conductive layer and said substrate; forming a first organic film layer to cover said first dielectric layer; forming a via in said first dielectric layer and in said first organic film layer, said via exposing said first patterned conductive layer; performing a first cleaning step to roughen an inner wall of said via and desmear said first patterned conductive layer; and patterning said first dielectric layer and said first organic film layer to form a pad opening overlapping with said via in said first dielectric layer so that an outer surface of said first dielectric layer has a roughness A, an inner wall of said pad opening has a roughness B, and the inner wall of said via has a roughness C, wherein said via and said pad opening together define said embedded circuit structure and the roughness of A, B, C are mutually different.