Patent ID: RE43541

Claim:
Circuitry that applies voltages to a memory to perform applications wherein said memory includes plurality of memory cells, said plurality of memory cells organized in rows and columns, said circuitry A circuit, comprising: First first circuitry that applies configured to apply one of a first plurality of voltages to at least one of said a plurality of memory cells based upon a row in which said at least one of said plurality of memory cells is arranged and based upon an application to be performed by said at least one of said plurality of memory cells , said first circuitry including row latch circuitry having a first input that receives configured to receive one of a plurality of high voltages and a second input receives configured to receive one of a plurality of low voltages and an a first output for selectively applying one of configured to selectively apply said one of said plurality of high voltages and or said one of said plurality of low voltages to said at least one of said plurality of memory cells; and Second second circuitry that applies configured to apply one of a second said plurality of voltages to said at least one of said plurality of memory cells based upon a column in which said at least one of said plurality of memory cells is organized arranged and based upon said application to be performed by said at least one of said plurality of memory cells ; wherein said second circuitry includes column latch circuitry having a third input configured to receive a first group of said plurality of high voltages, a fourth input configured to receive a second group of said plurality of high voltages, a fifth input configured to receive one of said plurality of low voltages, and a second output configured to selectively apply said one of said plurality of high voltages or said one of said plurality of low voltages to said at least one of said plurality of memory cells .