Patent ID: 7755947

Claim:
A semiconductor memory device comprising: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories, wherein: the first nonvolatile memory is configured to receive an enable signal through the enable terminal from the outside of the package; the first nonvolatile memory is configured to output first data to the system bus in response to a first edge of the enable signal; the first nonvolatile memory is configured to output second data to the system bus in response to a second edge of the enable signal following the first edge; and the second nonvolatile memory is configured to latch the first data output from the first nonvolatile memory, through the system bus, once the first nonvolatile memory outputs the first data.