Patent ID: 8331158

Claim:
A semiconductor device comprising: a plurality of memory cells; a plurality of word lines connected to the memory cells; a plurality of charge pumps configured to apply to the word lines any of first to n-th (n is an integer equal to or larger than 2) voltages of which voltage levels are different from each other, when writing data into at least one of the memory cells; an application voltage selector configured to select a voltage to be applied to the word lines among the first to n-th voltages; a word-line-number register configured to store number of the word lines to which the first to the n-th voltages are applied, the word-line-number register storing the number of the word lines for each of the first to the n-th voltages; a storage configured to store a correspondence table showing a corresponding relationship between the number of the word lines for each of the first to the n-th voltages and the number of the charge pumps allocated to the first to the n-th voltages, respectively; and a generation voltage selector configured to allocate the charge pumps in order to respectively generate the first to the n-th voltages based on the correspondence table according to the number of the word lines for each of the first to the n-th voltages, wherein the charge pumps are configured to generate any of the first to the n-th voltages allocated respectively by the generation voltage selector.