Patent ID: 6904559

Claim:
A full response read-channel decoding system comprising: an equalizer for receiving and equalizing a reproduced signal obtained from a storage medium to thereby generate an equalized signal; a slicer being coupled to the equalizer for receiving and slicing the equalized signal outputted by the equalizer to thereby generate a sliced signal; a sampler being coupled to the slicer for receiving the sliced signal from the slicer and generating a binary signal by sampling the sliced signal; an error correction circuit being coupled to the sampler for receiving the binary signal and correcting random errors in the binary signal by checking a predetermined Run Length Limited (RLL) code and producing a corrected signal according to a trellis diagram for the predetermined RLL code; and a demodulator being coupled to the error correction circuit for receiving and demodulating the corrected signal outputted by the error correction circuit.