Patent ID: 6947272

Claim:
A circuit comprising: a switch; a first comparator coupled to the switch for comparing an input of the switch to an output of the switch; a current limit reference circuit coupled to the first comparator for providing a current reference that has a first reference level when a ratio of the output to the input is less than a fixed ratio, and a second reference level when the ratio of the output voltage to the input voltage is greater than the fixed ratio; a second comparator coupled to the current limit reference circuit for comparing the current reference to a current level in the switch; a driver circuit coupled between the second comparator and a control node of the switch; wherein the current limit reference circuit comprises a decode/multiplexer with two reference voltage inputs and an output coupled to an input of the second comparator; a logic gate having an output coupled to the decode/multiplexer; and a delay circuit coupled between an output of the first comparator and an input of the logic gate.