Patent ID: 7733156

Claim:
A transistor arrangement comprising: a first and a second field effect transistor, each of which has a first and a second source/drain terminal and a control terminal for application of a first or a second signal, the two field effect transistors being of the same conduction type; wherein the transistor arrangement is configured such that alternately: the first signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the second signal can be applied to the control terminal of the second field effect transistor; and the second signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the first signal can be applied to the control terminal of the second field effect transistor; wherein one of the first and second signals is a useful signal and the respective other signal is a reference potential, or in which the first signal and the second signal are in each case a reference potential, or in which the first signal and the second signal are in each case a useful signal.