Patent ID: 8283720

Claim:
A power semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type provided in an upper portion of the first semiconductor layer, the second and third semiconductor layers being alternately arranged on at least a portion of an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers of the second conductivity type provided on the third semiconductor layer and connected to the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode provided in a region including a directly overlying region of a portion of the fourth semiconductor layers located between the second semiconductor layer and the fifth semiconductor layer; a gate insulating film insulating the control electrode from the second semiconductor layer, the fourth semiconductor layers, and the fifth semiconductor layer; a first main electrode provided on a lower surface of the first semiconductor layer and electrically connected to the first semiconductor layer; and a second main electrode provided on the fourth semiconductor layers and the fifth semiconductor layer and connected to the fourth semiconductor layers and the fifth semiconductor layer, a sum of impurities in the second and third semiconductor layers is smaller near a second main electrode side than at a vertical center, in a direction from the second main electrode to the first main electrode, thereby an electric field in the second and third semiconductor layers is lower near the second main electrode side than at the vertical center, the amount of impurities in the second semiconductor layer near the second main electrode being smaller than the amount of impurities in the second semiconductor layer at the vertical center of the second semiconductor layer, and the amount of impurities in the third semiconductor layer near the second main electrode being smaller than the amount of impurities in the third semiconductor layer at the vertical center of the third semiconductor layer.