Patent ID: 7065696

Claim:
A system for providing forward error correction, comprising: an input buffer configured to receive and store a plurality of symbols from a plurality of channels, wherein upon storing a symbol block belonging to a channel, the input buffer outputs the symbol block, the symbol block being made up of a predetermined number of symbols, wherein upon outputting the symbol block, the input buffer begins to receive and store another symbol block associated with another channel; a first decoder configured to receive and process one symbol block belonging to one of the plurality of channels and generate an output, the output including a decoded symbol block and a corresponding channel identifier, wherein upon generating the output, the first decoder receives a next symbol block from the input buffer for processing, the next symbol block associated with one of the plurality of channels; a frame synchronizer configured to receive the output from the first decoder, perform frame synchronization on the decoded symbol block, and generate an output, the output including the decoded symbol block and the corresponding channel identifier and frame information used to identify locations of frame boundaries in the decoded symbol block; a derandomizer configured to receive the output from the frame synchronizer, derandomize the decoded symbol block and generate an output, the output including a derandomized symbol block and a corresponding channel identifier; a deinterleaver having a memory, the deinterleaver configured to receive the output from the derandomizer, combine derandomized symbols in the derandomized symbol block to form a plurality of derandomized words, form one or more write blocks each having a predetermined number of derandomized words, store the one or more write blocks into the memory based on the corresponding channel identifier of the derandomized symbol block during a write session, and read one or more read blocks from the memory based on a specified channel identifier during one or more read sessions; a second decoder configured to receive the one or more read blocks, correct any symbol errors therein, and generate an output, the output including one or more decoded blocks; and a packet synchronization circuit configured to receive the one or more decoded blocks and perform packet synchronization on the decoded blocks to identify packet boundaries within the one or more decoded blocks; wherein the input buffer, the first decoder, the frame synchronizer, the derandomizer, the deinterleaver, the second decoder and the packet synchronization circuit are able to respectively process data corresponding to the plurality of channels in a concurrent manner.