Patent ID: 8661392

Claim:
A semiconductor device, comprising: a plurality of cells, wherein each of the plurality of cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner, and wherein each of the plurality of cells includes circuitry for performing one or more logic functions, the circuitry including a plurality of conductive features defined in one or more levels of the cell, wherein one or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone, wherein the exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary, wherein the encroachment distance extends from a position corresponding to the inward extent of the exclusion distance from the first segment of the outer cell boundary, to an outermost edge of the encroaching feature relative to an interior of the given cell, wherein the level of the given cell having the encroaching feature is also defined to correspondingly include a spacing allowance region adjacent to a second segment of the outer cell boundary located opposite the given cell from the first segment of the outer cell boundary, wherein the spacing allowance region extends perpendicularly inward into the given cell from the second segment of the outer cell boundary by a spacing allowance distance equal to at least the encroachment distance plus the exclusion distance, wherein the spacing allowance region within the level of the given cell does not include any conductive features.