Patent ID: 7773718

Claim:
A shift register circuit comprising: a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, at least one of the plurality of bit register units comprising: a register comprising an input terminal, a clock input terminal and an output terminal; an input terminal switch unit, coupled to the input terminal of the register, for switching the input terminal of the register to couple to another bit register unit according to the control signal; and an output terminal switch unit, coupled to the output terminal of the register, for switching the output terminal of the register to couple to one of the plurality of data output terminals according to the control signal; and a control unit coupled to the plurality of bit register units for generating the control signal to control transference of the input signal.