Patent ID: 8760891

Claim:
An apparatus for power conversion comprising: a pulse width modulator (PWM) to generate ideal pulses without deadtime compensation; upper and lower logic circuits configured to detect pulses from the PWM, the upper logic circuit to hold the detected pulses until the upper logic circuit receives a safe to turn ON (STTO) signal directly from the lower logic circuit through an isolation boundary and the lower logic circuit to hold the detected pulses until the lower logic circuit receives a STTO signal from the upper logic circuit; upper and lower gate drivers configured to receive an output from the respective upper and lower logic circuits; upper and lower switches configured to receive a gating signal from the respective upper and lower gate drivers; and upper and lower comparators configured to determine a conduction state of the respective upper and lower switches and associated anti-paralleling diodes based at least partly on collector-emitter voltages of the upper and lower switches, wherein the upper and lower comparators are configured to provide the determined conduction state to the respective upper and lower logic circuits, wherein the upper and lower logic circuits to control the upper and lower gate drivers according to the determined conduction state, the determined conduction state being one of: the switch is conducting, the diode is conducting, or the switch is off, wherein the upper and lower logic circuits follow a sequence of determining whether the STTO signal should be sent to one another, the sequence including: (a) waiting for the STTO signal, wherein generation of the STTO is based on the formula: STTO =(NOT state 1 AND state 2) OR (NOT state 1 AND state 3); wherein state 1 corresponds to a positive differential voltage across the respective upper or lower switch resulting from the respective upper or lower switch conducting; wherein state 2 corresponds to a negative differential voltage across the respective switch resulting from an anti-paralleling diode, associated with the respective switch, conducting, the negative differential voltage at a level lower than an input voltage to the respective switch; and wherein state 3 corresponds to a high impedance across the respective switch resulting from the respective switch being OFF, and (b) providing the STTO signal if the STTO signal is not received within a preset time period during a deadtime of an ON state between the upper and lower switches.