Patent ID: 7180141

Claim:
A ferroelectric memory cell, comprising: a switching device comprising a bitline terminal, a storage node terminal, and a control terminal, the switching device being operable to selectively couple an array bitline at the bitline terminal with a cell storage node at the storage node terminal according to a wordline signal at the control terminal; and a ferroelectric capacitor structure comprising: a first electrode coupled with the switching device at a cell storage node, a second electrode forming a cell plateline node, a ferroelectric material located at least partially between the first and second electrodes, and a cell resistor integral to the ferroelectric capacitor structure, the cell resistor being in contact with the first and second electrodes and providing a resistance between the cell storage node and the cell plateline node that inhibits charge accumulation or charge loss at the cell storage node when the cell is not being accessed without significantly disrupting memory access operations when the cell is being accessed, and wherein the cell resistor further comprises an encapsulation layer extending over a top portion of the second electrode and between the first and second electrodes and providing the resistance between the cell storage node and the cell plateline node.