Patent ID: 8910109

Claim:
An apparatus for designing a reconfigurable programmable logic device (PLD), the apparatus comprising: a processor configured to run a system level design tool, the processor accepting, as inputs from a user, an identification of at least two personas to be used within a reconfigurable region of the PLD, wherein: the design tool defines one or more boundaries of a partial reconfig (PR) domain, the PR domain including a partitioned reconfigurable region of the PLD that is selectably configurable as any of the at least two personas; the PR domain includes at least one IP component configured to safely shut down, during reconfiguration of the PR domain, at least one signal, the at least one signal originating from or directed toward an element of the PLD outside of the PR domain; and the at least one IP component includes an interface controller and one or both of a machine-readable description of all the interfaces in the PR domain, and a list of the personas that can be used in the PR domain.