Patent ID: 7737794

Claim:
A method, in a circuit, for compensating for process variations, comprising: asserting a calibration signal to the circuit; selecting at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process based on one of an output from a memory device storing an identifier of a resistor previously selected from the plurality of resistors in the plurality of resistors or a control input to an n-bit bus of the circuit from testing equipment indicating the at least one resistor in the plurality of resistors to select; applying a second calibration voltage directly to a loop tilter of the circuit via a multiplexer coupled to the loop filter, wherein the second calibration voltage is selected by the multiplexer, from a plurality of possible second calibration voltages provided as input to the multiplexer, to thereby bias a voltage controlled oscillator of the circuit at a predetermined frequency of interest; comparing a first frequency of a reference signal to a second frequency of a feedback signal generated by the circuit based on the calibration voltage; determining if the second frequency of the feedback signal is within a tolerance of the first frequency of the reference signal; storing an identifier of the selected at least one resistor in the memory device coupled to the circuit if the second frequency of the feedback signal is within the tolerance of the first frequency of the reference signal; de-asserting the calibration signal after storing the identifier of the selected at least one resistor in the memory device, wherein the selecting, comparing, and determining operations are performed in response to asserting the calibration signal; providing a control input to an n-bit bus of the circuit in response to the second frequency of the feedback signal not being within the tolerance of the first frequency of the reference signal; selecting one of the control input to the n-bit bus or an output from the memory device in response to the calibration signal being asserted or de-asserted, wherein the control input is selected in response to the calibration signal being asserted, and wherein the output from the memory device is selected in response to the calibration signal being de-asserted; and operating the circuit using the selected at least one resistor based on the identifier stored in the memory device whereby a voltage output of the at least one resistor is input as a compensation voltage to the voltage controlled oscillator of the circuit.