Patent ID: 7313024

Claim:
A non-volatile memory device, comprising: a cell array having a plurality of strings consisting of memory cells coupled to bit lines and word lines; and a plurality of page buffers connected to the bit lines through a sensing line, each of the plurality of page buffers comprises: a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line and a pre-erase verify signal in order to verify whether data programmed into the memory cells have been erased; a main erase detection unit that detects main erase in response to the signal of the sensing line in order to verify whether data programmed into the memory cells have been erased; a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify; and a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify, wherein the main erase detection unit initializes a first node of the latch circuit at the time of the pre-erase.