Patent ID: 7629810

Claim:
An input and output circuit comprising: a first input and output terminal; an output-stage circuit that outputs an output signal to said first input and output terminal; and a control circuit that controls said output-stage circuit so that said output-stage circuit constitutes a differential pair in a normal operation mode, and constitutes a CMOS circuit in a test mode, wherein said output-stage circuit comprises: two cascade-connected circuits in each of which a first conductive type MOS transistor is series-connected with a resistance element; said differential pair being formed by a first and second conductive type MOS transistors each of which has a load of said cascade-connected circuit; and a third second conductive type MOS transistor that supplies operating current to said differential pair; and wherein said control circuit controls said output-stage circuit so that: in said normal operating mode, said two first conductive type MOS transistors are ON, an input signal is supplied to said differential pair, and a specified voltage is supplied to a control end of said third second conductive type MOS transistor; and in said test mode, the input signal is supplied to a control end of one of said first conductive type MOS transistors, said one being in connection with said first second conductive type MOS transistor, and the input signal is supplied to a control end of said third second conductive type MOS transistor, with said first second conductive type MOS transistor being ON regardless of the input signal to maintain an ON state.