Patent ID: 7646216

Claim:
A programmable logic device comprising: (a) a switch array comprising a plurality of switches each having a first terminal coupled to one of a plurality of columns and a second terminal couple to one of a plurality of rows, wherein the switch array is for interconnecting input and output lines of functional logic modules; (b) interface logic comprising input logic operable to provide one or more signals to the switch array, wherein the input logic comprises a first plurality of gates having a first terminal coupled to one or more of the plurality of switches; and an associated plurality of input buffers each one coupled to a second terminal of a respective one of the first plurality of gates; (c) sleep mode gates comprising a second plurality of gates each one having a first terminal coupled to a respective one of the plurality of columns and having a second terminal coupled to a common potential source; and a third plurality of gates each one having a first terminal coupled to a respective one of the plurality of rows and having a second terminal coupled to the common potential source; and (d) sleep mode control logic coupled to a control terminal of each gate of the first, second and third pluralities of gates.