Patent ID: 8735885

Claim:
A memory device comprising: an antifuse memory element comprising: a first electrode; an insulating layer over the first electrode; a silicon layer over the insulating layer; and a second electrode, a first driver circuit which writes a first data to the antifuse memory element being in a first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the antifuse memory element being in a second state is obtained, and a second driver circuit which writes a second data to the antifuse memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the antifuse memory element being in a third state is obtained, and wherein R 1 >R 2 >R 3 is satisfied when a resistance of the antifuse memory element being in the first state is R 1 , a resistance of the antifuse memory element being in the second state is R 2 , and a resistance of the antifuse memory element being in the third state is R 3 , wherein the antifuse memory element being in the first state is an initial state, wherein at least a part of the silicon layer of the antifuse memory element being in the second state is a silicide layer, and wherein the first electrode and the second electrode of the antifuse memory element being in the third state are shorted.