Patent ID: 7232736

Claim:
A method of fabricating a semiconductor device, comprising: forming a lower electrode including a first copper layer on a substrate; forming a first insulation layer covering the lower electrode; patterning the first insulation layer to form a window exposing a portion of the lower electrode; conformally forming a lower barrier electrode layer, a dielectric layer, and an upper barrier electrode layer on a surface of the substrate where the window is formed, and stacking a conductive layer including a second copper layer to fill a remaining space of the window; performing a planarizing etch process into the substrate where the conductive layer including the second copper layer is stacked to expose a top of the first insulation layer, forming a capacitor including a lower barrier electrode, a dielectric layer pattern, an upper barrier electrode, and forming an intermediate electrode; forming a second insulation layer on the substrate where the intermediate electrode is formed; forming an etch mask on the second insulation layer and etching the layers under the etch mask to form a connection contact hole exposing a portion of the intermediate electrode; and filling the connection contact hole with a conductive layer including a third copper layer.