Patent ID: 7863189

Claim:
A method for fabricating a conductive via structure in a semiconductor substrate comprising: forming a via hole in a semiconductor substrate, wherein the via hole comprises an open end on a first surface of the semiconductor substrate, an interior sidewall surface having an insulating layer formed thereon, and a closed end having a first conductive material providing a seed layer formed on a surface of the closed end of the via hole; performing an electroplating process to fill the via hole with a second conductive material to form a conductive via using an electroplating process wherein plating current is forced to flow only through the surface of the closed end of the via hole so that plating starts from the seed layer on the surface of the closed end of the via hole and progresses towards the open end of the via hole; and forming electrical contacts to each end of the conductive via, wherein forming the via hole comprises: forming a first insulating layer to cover the first surface of the substrate and sidewall and closed end surfaces of the via hole with first insulation material; forming a conformal conductive liner over the first surface of the substrate to line the insulation layer and a second closed end surface of the via hole; filling the via hole with a sacrificial material; planarizing the first surface of the substrate down to the conformal conductive liner on the first surface of the substrate, the planarization forming a planarized surface; forming a layer of second conductive material over the planarized surface; bonding a carrier substrate to the second conductive material; depositing a layer of third conductive material over the carrier substrate in electrical contact with the layer of second conductive material; recessing the second surface of the semiconductor substrate down to the closed end of the via hole to open the via hole on the recessed second surface; and removing the sacrificial material in the via bole.