Patent ID: 7210052

Claim:
A method for synchronizing all clock sources of semiconductor devices, comprising: (a) generating multiple clock sources in a plurality of semiconductor devices; (b) designating one semiconductor device having a clock source with the lowest rate clock signal as a master device and other devices as slave devices when the multiple clock sources are stable; (c) designating the lowest rate clock signal of the master device as a reference clock source; (d) performing, according to the reference clock source, a phase-aligned check on other clock sources in the master device, such that other clock sources of the master device are synchronized with the reference clock source to generate a zeroing signal; (e) respectively performing, according to the zeroing signal, a phase-aligned check on a local lowest rate clock source in each slave device, such that all local lowest rate clock sources of the slave devices are synchronized with the lowest rate clock signal of the master device to respectively generate an aligning signal; and (f) respectively performing, according to the aligning signal, a phase-aligned check on other clock sources in each slave device, such that other clock sources of each slave device are separately synchronized with the local lowest rate clock signal of the respective slave devices, thereby completing clock synchronization for the plurality of semiconductor devices.