Patent ID: 8159973

Claim:
An ultra-scalable supercomputer based on Master Process Unit architecture, said ultra-scalable supercomputer comprising: a plurality of processing and Axon nodes interconnected by multiple interconnection networks, each processing node including one or more central processing units to power computation functions and each Axon node connecting said, or a subset of, processing nodes to facilitate long-range or collective communications or connections to external subsystems or basic high-level processing or in combination of such functions; and wherein, said multiple interconnection networks comprise four independent networking subsystems including a point-to-point Master Process Unit based network, a global mesh-based network, an external management network, an external storage network; wherein a processing node includes a router device for the communication among neighboring processing nodes and its directly-connected Axon node; and wherein said router device for a processing node further comprises a FPGA-based Interconnect Network protocol adaptation functional block for performing the input/output operations between the switch fabric and the processing nodes' local CPUs, and the protocol adaptation layer is responsible for assembling and disassembling between the FPGA-based Interconnect Network packets and the original packets to destination CPUs without FPGA-based Interconnect Network headers or trailers while checking the packet integrity as an error detector.