Patent ID: 8395538

Claim:
A singled-ended, successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits, comprising: SAR logic; a resistive network; a plurality of switches individually controlled by said SAR logic; a plurality of most significant bit (MSB) capacitors, some of which are connected to a static voltage; and a pair of least significant bit (LSB) capacitors, a first LSB capacitor connected to one of the switches that selectively couples said first LSB capacitor to a reference voltage (Vref) or a selected first tap in said resistive network, and a second LSB capacitor connected to one of the switches that selectively couples said second LSB capacitor to the analog input voltage or a selected second tap in said resistive network; wherein said plurality of switches also comprises two sets of switches coupled to said resistive network, each set of switches is configured to couple a selected tap to each of said first and second LSB capacitors; and wherein, when determining the lower order bits, said SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of the first and second taps changes by Vref/[2 (n−m+1) ] where n is the nth bit being determined.