Patent ID: 7724812

Claim:
A de-jittering method for a clock signal employing a controllable divider, the method comprising: dividing a clock signal to be de-jittered and a feedback clock signal respectively; starting a count upon detection of a rising edge of the feedback divided clock signal; increasing a count value in response to detecting one period of an input high-frequency signal; decreasing the count value when detecting one period of the input high-frequency signal when detecting a falling edge of the divided clock signal to be de-jittered; terminating the counting procedure when detecting the rising edge of the next feedback divided clock signal; defining the count value as phase difference information; generating a control signal according to the phase difference information and outputting the control signal to the controllable divider; and the controllable divider dividing the input high-frequency signal to generate a stable clock signal according to the control signal, and outputting the stable clock signal as the feedback clock signal and the de-jittered clock signal.