Patent ID: 7027342

Claim:
A semiconductor memory device comprising: a memory cell array in which memory cells each comprising variable resistive elements which store three or more multi-level information depending on a change in electric resistance are arranged in row direction and column direction, a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction are provided, respective one ends of the variable resistive elements of the memory cells in the same row are connected to the same row selection line and respective the other ends of the variable resistive elements of the memory cells in the same column are connected to the same column selection line; a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected, and supplies a second voltage different from the first voltage when the readout is not selected, to each of the column selection lines; a row readout voltage supply circuit which supplies the second voltage to each of the row selection lines at the time of readout; and a sense circuit which senses a current flowing in a selected row selection line separately from a current flowing in unselected row selection lines and senses an electric resistance state of a selected memory cell at the time of readout; wherein each reference level between two adjacent memory levels when the memory levels of multi-level information stored in the memory cell are arranged in order of size of resistance values of the corresponding variable resistive element in a distribution range is defined by a reference current in a middle state between a first current state in which a current flowing in the row selection line selected when a high resistance memory cell in which the electric resistance of the selected memory cell is in a higher resistance state in the two adjacent memory levels is read out, becomes the largest state depending on a distribution pattern of an electric resistance state of the other unselected memory cell in the memory cell array, and a second current state in which a current flowing in the row selection line selected when a low resistance memory cell in which the electric resistance of the selected memory cell is in a lower resistance state in the adjacent two memory levels is read out, becomes the smallest state depending on the distribution pattern of the electric resistance state of the other unselected memory cell in the memory cell array, and the sense circuit is constituted so as to be able to compare the current flowing in the selected row selection line with the reference current corresponding to the reference level.