Patent ID: 7479418

Claim:
A method for balancing threshold voltages of a complementary metal-oxide-semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI substrate, wherein said CMOS circuit comprises an n-channel field effect transistor (n-FET) and a p-channel field effect transistor (p-FET), said method comprising: fabricating said CMOS circuit on said SOI substrate, wherein said SOI substrate includes: a semiconductor device layer containing source and drain regions of each of said n-FET and said p-FET; a second buried insulator layer vertically abutting said semiconductor device layer; a substrate region vertically abutting said second buried insulator layer and underlying said n-FET and said p-FET of said CMOS circuit; wherein said second buried insulator layer electrically isolates said semiconductor device layer from said substrate region; a first buried insulator layer vertically abutting said substrate region; a base semiconductor layer having a doping of a first conductivity type and located directly beneath said first buried insulator layer; wherein said first buried insulator layer electrically isolates said substrate region from said base semiconductor layer; and applying a substrate bias voltage to said substrate region, wherein a threshold voltage of said p-FET and a threshold voltage of said n-FET are impacted by said substrate voltage bias, and wherein a difference between said threshold voltage of said n-FET and said threshold voltage of said p-FET is reduced by at least 5%.