Patent ID: 7018893

Claim:
A method for fabricating bottom electrodes of stacked capacitor memory cells, comprising the steps of: providing a semiconductor wafer including a substrate; forming a plurality of contact plugs on the surface of the substrate; depositing a layer stack as a hard mask on the surface of the substrate and the plurality of contact plugs, the layer stack comprising at least a first mask layer, a second mask layer, and a third mask layer, wherein the first mask layer is deposited on the surface of the substrate and the plurality of contact plugs, the second mask layer is deposited on the first mask layer and the third mask layer is deposited on the second mask layer; etching a plurality of trenches into the hard mask, each of the trenches being located above and aligned with a respective contact plug and ranging from the surface of the third mask layer to the respective contact plug; partially etching the third mask layer to laterally recess the third mask layer with respect to sidewalls of the trenches formed within the hard mask; depositing a conductive layer on the surface of the hard mask, the conductive layer covering the side walls of the trenches and the contact plugs; removing the third mask layer by etching; removing the second mask layer by etching to separate portions of the conductive layer such that the separate portions form bottom electrodes; and wet cleaning the semiconductor wafer to provide a substantially residue free surface on each of the bottom electrodes.