Patent ID: 7350110

Claim:
A method for processing an instruction within a processor, wherein the processor processes a plurality of types of interruptions, and wherein the processor comprises a plurality of register fields for indicating one or more conditions, statuses, and/or modes that are active within the processor, the method comprising: executing an instruction within the processor; receiving an interruption signal by the processor; indicating whether the trap mode is active or inactive using a trap mode field within the processor, wherein a first trap mode field indicates that a single-step trap mode is active and wherein a second trap mode field indicates that a taken-branch trap mode is active; in response to receiving the interruption signal, determining whether a trap mode is to remain active during interruption processing; in response to a determination that the trap mode is to be deactivated during interruption processing, deactivating the trap mode; and invoking an interruption handler to perform in interruption processing for the received interruption signal.