Patent ID: 7473627

Claim:
Method for fabricating a semiconductor device, comprising the steps of: (a) forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; (b) forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; (c) depositing a second insulating layer over an entire surface of the substrate including the first insulating pattern and the first and second conductive patterns, and forming a second insulating pattern from the second insulating layer exposing an entire upper surface of the second conductive pattern; (d) forming a first salicide on an exposed substrate and a second salicide on an entire upper surface of the second conductive pattern; and (e) depositing a third insulating layer over an entire surface of the substrate including the first and second insulating patterns and the first and second conductive patterns, and forming a first contact hole and a second contact hole, respectively exposing the first salicide layer and the second salicide layer, wherein the second contact hole is a predetermined distance from the second insulating pattern and the predetermined distance is more than 60 nm.