Patent ID: 7607058

Claim:
TAP domain selection circuitry comprising: A. a test data input lead; B. a test data output lead; C. a test clock input lead; D. a test mode select input lead; E. an instruction register having a data input coupled to the test data input lead, a data output, control outputs, and a control input; F. first multiplexer circuitry having a first data input connected to the data output of the instruction register, a second data input, a data output coupled to the test data output lead, and a control input; G. TAP controller circuitry having a clock input connected to the test clock input lead, a mode input connected to the test mode select input lead, and control outputs; and H. blocking circuitry having control inputs connected to the control outputs of the TAP controller circuitry, control outputs connected to the control inputs of the instruction register and the first multiplexer circuitry, and a remove select input receiving a remove select signal, the blocking circuitry selectively connecting the control inputs to the control outputs in response to receiving a remove select signal of one state.