Patent ID: 7151315

Claim:
An integrated circuit comprising: one or more front end of line devices; a layer of doped oxide overlying the one or more front end of line devices; a plurality of refractory metal plugs in the doped oxide layer; a first barrier layer of silicon oxycarbide (SiOC) in contact with and directly overlying the layer of doped oxide and the plurality of refractory metal plugs; a low dielectric constant film in contact with and directly overlying the first barrier layer; wherein the low dielectric constant film and the first barrier layer include a plurality of metal-filled trenches etched there-through to provide a metal plug extending from the top of the low dielectric constant film to at least one of the plurality of refractory metal plugs; and a non-metal film positioned between the metal plug and the low dielectric constant film and between the metal plug and the first barrier layer, wherein an upper surface of the non-metal film is coplanar with an upper surface of the low dielectric constant film.