Patent ID: 7251184

Claim:
A semiconductor memory device with a hierarchical bit line structure, comprising: a plurality of subarrays arranged in a row direction and a column direction; a plurality of word lines connected to the subarrays provided in the row direction; a plurality of main bit lines connected to the subarrays provided in the column direction; and a voltage control section for controlling a voltage supplied to the subarray, wherein the subarray includes: a sub-bit line; a plurality of memory cells which are connected to the word lines and change a voltage of the sub-bit line to a voltage corresponding to data stored therein, in response to selection of the word lines; a first MOS transistor having a gate electrode connected to the sub-bit line and a drain electrode connected to the main bit line; a second MOS transistor having a gate electrode connected to the main bit line and a drain electrode connected to the sub-bit line; a third MOS transistor, whose conductivity type is different from a conductivity type of the second MOS transistor, having a gate electrode connected to the main bit line, a source electrode connected to a ground voltage, and a drain electrode connected to the sub-bit line, and the voltage control section is capable of applying a power source voltage to the source electrode of the first MOS transistor and the source electrode of the second MOS transistor.