Patent ID: 7782695

Claim:
A sensing circuit comprising: a memory circuit comprising a first offset circuit coupled to a memory cell and operable to offset a first current, the memory circuit including a first load element, and a first cascode transistor coupled to the first load element and the memory cell; a reference circuit including a second offset circuit operable to offset a second current; and a compare circuit coupled to the memory circuit and the reference circuit and configured to determine a state of the memory cell based on a calculated difference between the first current and the second current, the compare circuit being operable to perform a pre-charge phase that includes polarizing the memory cell, and an evaluation phase to calculate the difference, wherein the first offset circuit is operable to offset the first current in order to drive the memory cell to a polarization point, and wherein the memory circuit comprises a first bias circuit coupled to the first cascode transistor and operable to limit a voltage at a drain of the memory cell.