Patent ID: 8352807

Claim:
A semiconductor memory system comprising: a host device; and a semiconductor memory device, wherein said semiconductor memory device includes: a nonvolatile memory composed of a plurality of physical blocks; a data writer for writing data to said nonvolatile memory; a data reader for reading data from said nonvolatile memory; a memory manager having a logical-physical conversion table recording correspondence between a logical block according to a command issued from the host device and physical block of said nonvolatile memory, the memory manager converting a logical address given from said host device into a physical address of said nonvolatile memory; and a memory information informer for informing memory information on said nonvolatile memory, wherein said host device includes: a block boundary manager for managing a boundary of the physical block as a writing unit based on the memory information informed from said memory information informer of said semiconductor memory device, and for identifying a range of error propagation based on the size and boundary of the physical block; a command divider for dividing data to be written and a write command based on an access unit from said block boundary manager to the physical block; a data buffer for storing data to be written upon issuing a write command; a command issuer for issuing a write command to said semiconductor memory device, and in a case of a writing error occurs at writing to said semiconductor memory device, reading data to be written to a block in which a writing error occurs from said data buffer and reissuing the write command; and a data release determinator for determining whether or not data stored in said data buffer is released based on an error propagation range.