Patent ID: 6933207

Claim:
A method of forming integrated circuitry, comprising: forming LOCOS field oxide by providing nitride masking blocks over a silicon substrate; the nitride masking blocks being separated by spaces that are less than or equal to 0.25 micron; the spaces leaving portions of the silicon substrate exposed between the nitride masking blocks; subjecting the silicon substrate to dry oxidation to form LOCOS field oxide configured to provide isolation within the spaces and then removing the nitride masking blocks; and forming an array of memory cells in lines over the silicon substrate and occupying area thereover, the respective area consumed by at least some individual memory cells within the array being less than 8F 2 , where “F” is no greater than 0.25 micron and is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array; at least some of the minimum pitch adjacent lines of memory cells within the array being isolated from one another by the LOCOS field oxide.