Patent ID: 7870340

Claim:
An apparatus, comprising: a first level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the first level cache memory being operable to store an address tag and data; a next lower level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the next lower level cache memory being operable to store an address tag, status flags, and data; and an additional memory associated with the next lower level cache memory and including a plurality of memory lines, wherein the number of memory lines corresponds with the number of cache lines contained in a given way set of the first level cache memory, the additional memory being separate from the next lower level cache memory; wherein each cache line of the first level cache memory has an index associated therewith, each memory line of the additional memory includes respective L-flags for multiple cache lines of each way set of the next lower level cache memory, all L-flags associated with a given one of the indices plus any index offset from the first level cache memory are contained in a single memory line of the additional memory, and the next lower level cache memory does not include an L-flag contained within each cache line thereof.