Patent ID: 7701769

Claim:
A integrated circuit, comprising: a nonvolatile NAND memory array; a plurality of word lines as the source of gate voltage to the nonvolatile NAND memory array; and logic coupled to the nonvolatile NAND memory array, said logic performing operations by controlling bias arrangements of at least the plurality of word lines and the nonvolatile NAND memory array, the operations including: a programming operation controlling a series of programming bias arrangements to program at least a selected memory cell of the nonvolatile NAND memory array, wherein the series of programming bias arrangements include: the first set of changing gate voltage values being applied, at least partly via a first word line of the plurality of word lines, to a selected row of memory cells of the nonvolatile NAND memory array, the selected row including the selected memory cell, the second set of changing gate voltage values being applied, at least partly via one of other word lines of the plurality of word lines by the first word line, to one of unselected rows of memory cells of the nonvolatile NAND memory array, a first bit line voltage applied to a selected NAND column of the nonvolatile NAND memory array including the selected memory cell; and a second bit line voltage applied to one of unselected NAND columns of the nonvolatile NAND memory array not including the selected memory cell.