Patent ID: 8054707

Claim:
A method of operating a DRAM memory cell and a sense amplifier, both coupled to a bit line, comprising: in a first mode of operation: performing a first memory operation on the DRAM memory cell, including amplifying a voltage associated with information stored in the memory cell using a substantially invariant power supply voltage; in a second mode of operation: performing a second memory operation on the memory cell, comprising a self-refresh operation, including amplifying a voltage associated with information stored in the memory cell using a ramped power supply voltage; wherein the ramped power supply voltage has a ramp transition time greater than an RC time constant associated with the bit line and the sense amplifier; and wherein the second memory operation on the memory cell includes ramping the power supply voltage in a first direction over a first period of at least the ram transition time performing a first sub-operation, ramping the power supply voltage in a second direction opposite to the first direction over a second period of at least the ramp transition time, and then performing a second sub-operation.