Patent ID: 6873544

Claim:
A data storage device comprising: an array of resistive memory cells having rows and columns; a set of diodes electrically connected in series to a plurality of memory cells in the array; a plurality of word lines extending along the rows of the array; a plurality of bit lines extending along the columns of the array; a first selected memory cell in the array, wherein the first selected memory cell is positioned between a first word line in the plurality of word lines and a first bit line in the plurality of bit lines; and a circuit electrically connected to the array and capable of monitoring a signal current flowing through the first selected memory cell and comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the first selected memory cell is in; wherein the circuit is capable of obtaining the average reference current by placing an unselected memory cell in a first resistance state, sensing a first reference current while the unselected memory cell is in the first resistance state, placing the unselected memory cell in a second resistance state, sensing a second reference current while the unselected memory cell is in the second resistance state, and averaging the first reference current and the second reference current to obtain the average reference current.