Patent ID: 7709949

Claim:
A structure in a semiconductor die, said structure comprising: a first metal segment and a second metal segment situated on a dielectric layer, said first metal segment and said second metal segment being situated in an open region of said semiconductor die; a third metal segment and a fourth metal segment situated on said dielectric layer, said third metal segment and said fourth metal segment being situated in a dense region of said semiconductor die, respective sidewalls of said third and said fourth metal segments comprising substantially no residue or polymer; said first metal segment and said second metal segment being formed by etching a metal layer at a first etch rate, said third metal segment and said fourth metal segment being formed by etching said metal layer at a second etch rate, wherein said third and fourth metal segments are formed with substantially no sidewall undercutting by increasing an amount of an etch inhibitor such that said first etch rate is approximately equal to said second etch rate, wherein said etch inhibitor is selected from the group consisting of N2 and CHF3, wherein a spacing aspect ratio in said dense region is greater than 2.5, and wherein said dielectric layer between said third metal segment and said fourth metal segment is substantially co-planar with a bottom portion of said third metal segment and said fourth metal segment.