Patent ID: 7365382

Claim:
A memory having charge trapping memory cells comprising: a substrate; a plurality of conductive word lines; a plurality of memory cells including a plurality of shallow trench isolations, a plurality of source/drain regions bounded by the shallow trench isolations, a plurality of gate electrodes formed by respective parts of the word lines opposing the substrate between adjacent source/drain regions to form a plurality of channel regions, the gate electrodes being isolated from the source/drain regions by a trapping dielectric, wherein the gate electrodes are arranged in trenches at least partly formed in the substrate; the trapping dielectric comprises a storage layer sandwiched in between two boundary layers, and the storage layer being part of the trapping dielectric isolating one of the gate electrodes in a trench comprises at least two parts including a first part isolating the gate electrode from the source region and a second part isolating the gate electrode from the drain region, the first and second parts being formed by removing a bottom part of the storage layer located at the bottom of the trench.