Patent ID: 8645779

Claim:
A method for scan testing an integrated circuit including a plurality of on-chip logic modules, using an external automated test pattern generator (ATPG) tool, wherein each on-chip logic module includes a plurality of scan paths and each scan path includes a plurality of logic elements, the method comprising: configuring the integrated circuit for module level scan testing, wherein each on-chip logic module is tested independently; generating a first set of test patterns for module level scan testing by the external ATPG tool, wherein the first set of test patterns corresponds to a first set of design faults in the plurality of scan paths; testing the plurality of scan paths using the first set of test patterns; configuring the integrated circuit for chip level scan testing of one or more on-chip modules together, including synchronizing functional primary input and output ports of the integrated circuit and corresponding primary input and output ports of the plurality of on-chip logic modules; generating a second set of test patterns for chip level scan testing by the external ATPG tool, based on the first set of test patterns; and testing the plurality of scan paths-using the second set of test patterns.