Patent ID: 7548403

Claim:
An overcurrent detection circuit for detecting an overcurrent condition in an output transistor connected in series with an electrical load between a power supply and a first ground, the output transistor having a first output terminal connected to the load, a second output terminal connected to the first ground, and an input terminal, the overcurrent detection circuit comprising: a detection transistor having a first output terminal, a second output terminal connected to the second output terminal of the output transistor, and an input terminal connected to the input terminal of the output transistor so that the output transistor and the detection transistor can be turned on at a time; an operational amplifier having a non-inverting input terminal connected to the first output terminal of the output transistor, an inverting input terminal connected to the first output terminal of the detection transistor, and an output terminal; a current mirror circuit including a pair of first and second transistors having first output terminals connected together to the output terminal of operational amplifier, second terminals, and input terminals connected together, the second output terminal of the first transistor being connected to the input terminal of the first transistor and the first output terminal of the detection transistor; current detection means connected to the second output terminal of the second transistor to detect a current flowing through the second transistor; an early effect cancel circuit including a pair of third and fourth transistors, the third transistor having a first output terminal connected to the current mirror circuit, a second output terminal connected to the detection transistor, and an input terminal, the fourth transistor having a first output terminal connected to the current mirror circuit, a second output terminal connected to the current detection means, and an input terminal connected to the input terminal of the third transistor; and a fixed voltage source that generates a fixed voltage from the power supply and applies the fixed voltage to the input terminal of each of the third and fourth transistors, wherein an electric potential of the first output terminal of each of the third and fourth transistors is fixed by the application of the fixed voltage to the input terminal of each of the third and fourth transistors, so that the current mirror circuit is allowed to produce a mirror current even when a potential of the first ground is below a predetermined potential.