Patent ID: 7772706

Claim:
A method to make interconnects for a semiconductor die, comprising: forming a spacer adjacent a first conductive line, the spacer extending a distance from the first conductive line; forming a top dielectric layer on the spacer and first conductive line; forming an unlanded via hole that extends through the top dielectric layer to the first conductive line and the spacer, the spacer acting as an etch stop to prevent the via hole from extending below the spacer; and wherein the first conductive line has a first width within a selected distance of a desired area for the via hole to land and a second width less than the first width beyond the first distance; and wherein a second conductive line is spaced apart from the first conductive line, the spacer extends from the first conductive line to the second conductive line at locations where the first conductive line has the first width, and the spacer extends from the first conductive line but does not extend all the way to the second conductive line at locations where the first conductive line has the second width.