Patent ID: 7042374

Claim:
A current source cell comprising: a current source providing a first current to a first node, the current source being capable of being calibrated to provide the first current having a substantially constant value; a first switch coupled between the first node and a first output terminal and having a control terminal driven by a first control signal; a second switch coupled between the first node and a second output terminal and having a control terminal driven by a second control signal; and a latch circuit receiving a data signal, an output override control signal, and a clock signal, the latch circuit generating the first control signal and the second control signal as output signals, wherein when the output override control signal is asserted, the first control signal and the second control signal are driven by the latch circuit to a first logical state to cause the first and second switches to open; and when the output override control signal is deasserted, the first control signal and the second control signal are driven by the latch circuit to have logical states that correspond to the data signal as triggered by the clock signal where the first and second control signals have inverse logical states, thereby causing one of the first and second switches to close to steer the first current to a respective one of the first and second output terminals.