Patent ID: 8193579

Claim:
A trench type semiconductor device comprising: a first base layer of a first conductivity type having high resistivity; a gate insulating film placed on a bottom surface and a sidewall surface of a trench formed from a surface of the first base layer; a gate electrode placed on the gate insulating film and fills up into the trench; an interlayer insulating film placed by covering the gate electrode; a second base layer of a second conductivity type placed on the surface of the first base layer, and is formed more shallowly than a bottom surface of the trench; a first main electrode layer of the first conductivity type placed on a surface of the second base layer; a first main electrode is connected to the second base layer in a bottom surface of a self-aligned contact trench, and is connected to the first main electrode layer in a sidewall surface of the self-aligned contact trench, the self-aligned contact trench being configured to pass through the first main electrode layer and being formed in the second base layer by applying the interlayer insulating film as a mask, the first main electrode being disposed all over a device structure toward the self-aligned contact trench; a second main electrode layer placed at a back side of the first base layer; and a second main electrode placed at the second main electrode layer; wherein the interlayer insulating film includes arsenic implanted by ion implantation as an impurity, and an impurity concentration of arsenic in the interlayer insulating film is higher than impurity concentrations of the first base layer, the second base layer, and the first main electrode layer.