Patent ID: 7016997

Claim:
A method for testing an integrated drive electronics (IDE) device in a computer system, wherein the computer system includes a peripheral component interconnect (PCI) bus and an IDE bus coupled to the PCI bus, a plurality of IDE devices are connected to the IDE bus, and the PCI bus includes a plurality of input/output (I/O) ports, the method is operable under one of a real mode and a protected mode, and memory sharing can be done only in one of the real mode and the protected mode, the method comprising the steps of: when a selected one of the IDE devices is to be tested, setting up a testing flag at one of the I/O ports of the PCI bus and sending a command to the selected one of the IDE devices; in response to a specific interrupt signal issued by one of the IDE devices after the command is sent, determining whether to perform IDE device testing with respect to the specific interrupt signal by determining whether the testing flag is set up at the I/O port of the PCI bus; and if the testing flag is set up at the I/O port of the PCI bus, performing IDE device testing on the one of the IDE devices with respect to the specific interrupt signal, wherein the determination that the testing flag is set up at the I/O port of the PCI bus indicates that the one of the IDE devices with respect to the specific interrupt signal is the selected one of the IDE devices; wherein the testing flag is set up at the I/O port of the PCI bus so that the determination as to whether to perform IDE device testing with respect to the specific interrupt can be made regardless of whether the one of the IDE devices issues the specific interrupt signal under the real or protected mode.