Patent ID: 7436696

Claim:
A semiconductor structure comprising: a static random access memory (SRAM) cell comprising: a pull-up MOS device having a first drive current; a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current; and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device, wherein the first drive current and the third drive current have an α ratio of between about 0.5 and about 1, and wherein the second drive current and the third drive current have a β ratio of between about 1.45 and about 5; and a dynamic power circuit coupled to the SRAM cell, wherein the dynamic power circuit is configured to provide a dynamic bitline voltage for write operations of the SRAM cell, and to provide a static bitline voltage for read operations of the SRAM cell, and wherein the dynamic bitline voltage is higher than the static bitline voltage.