Patent ID: 8165297

Claim:
A transceiver comprising: an electrical interface configured to receive outgoing data signals from a host coupled to the transceiver and transmit incoming data signals to the host; a fiber optic transmitter configured to transmit the outgoing data signals received from the host via the electrical interface; a fiber optic receiver configured to receive the incoming data signals from an external device over a network communications channel; and a controller configured to encrypt a string and supply the encrypted string to the host via the electrical interface to authenticate the transceiver, authentication of the transceiver being contingent upon whether or not the transceiver has been certified as meeting a specified quality standard; wherein the controller comprises: a data bus; a central processing unit (CPU) coupled to the data bus; a voltage clock reset module and sleep mode logic sensors/filters and voltage regulator module coupled to the CPU; a read only memory (ROM), a random access memory (RAM), an electrically erasable and programmable read only memory (EEPROM) and a cryptography module coupled to the data bus; and an interrupt module, a timer module, a cyclic redundancy check (CRC) module, a random number generator, an inter-integrated circuit (I2C) receiver-transmitter, and a phase-locked loop (PLL) coupled to the data bus.