Patent ID: 6957401

Claim:
A computer implemented method for designing an integrated circuit (IC) floorplan silhouette-like power supply net for an IC having a transistor embedded silicon based substrate and an interconnect structure including at least three metal layers for power routing purposes and transistor interconnection purposes, the IC floorplan silhouette-like power supply net including at least one of a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net, the method comprising the steps of: (a) receiving (i) an IC floorplan including at least one power consuming entity for electrical connection to the IC floorplan silhouette-like power supply net, a power consuming entity constituting an exempt area, (ii) the designation of one or two metal layers of the interconnect structure assigned to be the supply layers exclusively reserved for the IC floorplan silhouette-like power supply net, and (iii) a SoS net boundary; (b) for each metal layer, determining a SoS net within the SoS net boundary, each SoS net being the logical complement of all the exempt areas of the IC floorplan within the SoS net boundary; and (c) outputting information with respect to the IC floorplan silhouette-like power supply net.