Patent ID: 8356166

Claim:
A computing apparatus comprising: one or more processors one or more memories coupled to the one or more processors; an instruction set architecture interface coupled to the one or more processors that includes mechanisms to implement instructions, wherein the instruction set architecture interface comprises: a mechanism including one or more processor level instructions that when executed by a processor with transactional memory hardware support performs a test to determine if the processor is in a transactional mode and tests a per-transaction per address hardware maintained indicator indicating if monitoring or buffering is set for the address and sets a flag when both the processor is in a transactional mode and when monitoring or buffering is set for the address, where the flag is later used to determine whether or not to bypass one or more mode specific transactional write barriers or one or more mode specific transaction read barriers when the one or more mode specific transactional write barriers or the one or more mode specific transactional read barriers are redundant or disabled, but when executed on a processor without transactional support, the one or more processor level instructions execute as one or more NOPs.