Patent ID: 7601610

Claim:
A process for the realization of a high integration density power MOS device, comprising the steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on said semiconductor layer, a dielectric layer of thickness comprised between 300 and 1300 nm; depositing, on said dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 15 and 150 nm; depositing a conductor material in said cavities and above the same to form a recess spacer wherein said recess spacer serves as gate electrode, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxides; providing a masking, by positioning a resist layer, of the regions which will lead signal transmission conductive layers, above said thick dielectric layer; and anisotropically etching the conductor layer and removing said resist layer, said anisotropically etching of said conductor layer defining, in a simultaneous way, said recess spacer and said signal transmission conductive layer.