Patent ID: 8909906

Claim:
A computer-implemented method in which a computer system performs operations comprising: executing an instruction including testing of a branch flag wherein a branch flag value is determined and compared to a predetermined value, said branch flag referencing a configuration bit vector wherein each bit in said configuration bit vector corresponds to a respective feature, said respective feature based on at least one of packet content and a configuration set, wherein said flag comprises an m+2*log 2 (n) bit field wherein m comprises an m-bit operator field representing a list of logical operations and wherein said 2*log 2 (n) bit field includes two log 2 (n) bit feature selector fields which identify a bit position of the feature in a configuration vector and wherein n comprises a number of vector bits; and continuing processing at an instruction located at a first location relative to a Program Counter (PC) when said branch flag returns a first result and continuing processing at a second location relative to said PC when the branch flag returns a second result.