Patent ID: 8884387

Claim:
A semiconductor device comprising: a semiconductor substrate comprising a conductive (“M2”) patterned area, wherein a top surface of the M2 patterned are and a top surface of the semiconductor substrate are co-planar; a via level (“VA”) pillar structure formed over and in contact with the M2 patterned area, wherein the VA pillar structure comprises a subtractively patterned metal layer, wherein the VA pillar structure is a sub-lithographic contact; an oxide layer formed over and in contact with at least the semiconductor substrate and adjacent to and in contact with the VA pillar structure, wherein a bottom surface of at least a first portion and a second portion of the oxide layer contacts a top surface of a first portion and a second portion of the M2 patterned area, respectively; and a magnetic tunnel junction (“MTJ”) stack comprising a first magnetic layer, a second magnetic layer, and an insulating layer, wherein at least a portion of the first magnetic layer, the second magnetic layer, and the insulating layer each is formed directly over the metal layer of the VA pillar and the first and second portions of the oxide layer, and wherein the first magnetic layer contacts the metal layer of the VA pillar, where first and second portions of the first magnetic layer contact the first and second portions of the oxide layer, respectively, wherein a size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact, and wherein a size of the MTJ stack corresponds to a size of the M2 patterned area.