Patent ID: 7362603

Claim:
A memory device comprising: a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area; and a third memory cell area disposed adjacent to a bottom side of the second memory cell area, and having a third latch area where one or more electronic components are constructed for storing a value, and a third peripheral area surrounding the third latch area, wherein the first memory cell area is shifted rightward by a first distance, the second memory cell area is shifted downward by a second distance, and the third memory cell area is shifted leftward by a third distance to form a stagger memory cell array, such that horizontal and vertical edges of the first, second, and third memory cell areas are not in alignment with each other.