Patent ID: 7158426

Claim:
A method for testing an integrated semiconductor memory, comprising: providing an integrated semiconductor memory which can be operated in a test operating state, the integrated semiconductor memory including a register for reading in a threshold value, a counter, and at least one memory bank with at least one word line with bit lines and memory cells, the memory cells each having a storage capacitor and a selection transistor, the selection transistor being controlled by driving one of the word lines in one of the memory banks with a control voltage, the respective memory bank and the respective word line selected for driving one of the word lines in one of the memory banks, the respective storage capacitors of the memory cells being connected to a respective one of the bit lines by turning on the respective selection transistors of the memory cells; and driving a control circuit in the test operating state synchronously with a clock edge of a control clock with a first control signal, so that a test includes selecting one of the memory banks, turning off the selection transistors in the selected memory bank by driving the word lines in the selected memory bank with the control voltage, connecting the bit lines in the selected memory bank and driving the bit lines with a precharge potential for a precharge time duration to be tested, the precharge time duration to be tested being set independently of a duration of a clock period of the control clock, altering a counter reading of the counter proceeding from a start value until the threshold value read into the register is reached, the time duration between the start value and reaching the threshold value representing a precharge time duration to be tested, selecting one of the word lines, and turning on the selection transistors by driving the selected word line in the selected memory bank with the control voltage, after the precharge time to be tested has elapsed.