Patent ID: 7879648

Claim:
A fabrication method for a high pin count chip package, comprising: providing a leadframe, wherein the leadframe comprises a chip carrier and a plurality of first lead pins configured around the chip carrier; forming a first channel on the first lead pins to define a first contact portion and a second contact portion thereon, wherein the first contact portion and the second contact portion are respectively located at two sides of the first channel; and the first contact portion and the second contact portion of the same first lead pin are connected to each other with a connecting portion; mounting at least one chip onto the chip carrier; performing a wire bonding process for electrically connecting the chip to the first contact portions and the chip to the second portions with a plurality of wires; encapsulating the chip, the wires, and the first channel with a molding compound; and performing a backside sawing process for electrically isolating the first contact portions and the second contact portions.