Patent ID: 8774325

Claim:
A circuit comprising: a phase difference selector configured to select one of a plurality of reference clock phase difference signals; a clock signal generator coupled to the phase difference selector, the clock signal generator configured to generate a plurality of clock signals based on the selected reference clock phase difference signal, each of the clock signals having a same frequency and a different phase; a reference clock phase detector coupled to the phase difference selector and the clock signal generator, the reference clock phase detector configured to generate the reference clock phase difference signals, each of the reference clock phase difference signals representing a phase difference between a reference clock and one of the clock signals; and a data signal phase detector coupled to the clock signal generator and the phase difference selector, the data signal phase detector configured to generate a data phase difference signal based on differences in phase between one or more of the clock signals and a data signal, the data phase difference signal being used by the phase difference selector to select one of the reference clock phase difference signals.