Patent ID: 8736346

Claim:
A level shift circuit comprising: a plurality of level shift units which are connected to each other and in which the delay time of a rising edge of an output voltage is different from the delay time of a falling edge of the output voltage, wherein the delay time of the rising edge of the output voltage from a previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit; and wherein the plurality of level shift units comprising: a first level shift unit that performs a level shift operation on the basis of a differential input voltage; and a second level shift unit that performs a level shift operation using an input voltage to the first level shift unit and an output voltage from the first level shift unit as differential input voltages.