Patent ID: 6963269

Claim:
An integrated circuit comprising: a first potential point; a second potential point; a third potential point; a fourth potential point; a fifth potential point; a first impedance element; a second impedance element; a third impedance element; a fourth impedance element; a first charge pump circuit; a second charge pump circuit; and a third charge pump circuit, wherein each of the first, second, and third charge pump circuits comprises a first FET, a second FET, a first capacitance, and a second capacitance; the source-drain path of each of the second FETs is coupled between first ends of the first and second capacitances for each of the first, second, and third charge pump circuits; the second end of each of the second capacitances is coupled to the fifth potential point; the first impedance element is coupled between the first potential point and the fifth potential point; the second impedance element is coupled between the first potential point and the second end of the first capacitance of the first charge pump circuit; the third impedance element is coupled between the second ends of the first capacitances of the first and second charge pump circuits; the fourth impedance element is coupled between the second ends of the first capacitances of the second and third charge pump circuits; the source-drain path of the first FET of each of the first and second charge pump circuits is coupled between the first end of the first capacitance of the respective first or second charge pump circuit and the fifth potential point; the source-drain path of the first FET of the third charge pump circuit is coupled to the second ends of the second capacitance of the second charge pump circuit and the first capacitance of the third charge pump circuit; and the second, third, and fourth potential points are coupled to the first end of the second capacitance of each of the first, second, and third charge pump circuits respectively.