Patent ID: 7851302

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming at least one active area in or over a workpiece, the workpiece comprising at least one first region and at least one second region; and forming a first metallization layer and a second metallization layer over the workpiece, thereby forming lower level and upper level interconnects of the semiconductor device and forming at least one capacitor, the at least one first region of the workpiece comprising a region wherein the first and the second metallization layers comprise the lower and the upper level interconnects of the semiconductor device respectively, the at least one second region comprising a region wherein the first and the second metallization layers comprise the at least one capacitor, wherein forming the at least one capacitor over the workpiece comprises: forming a first plate of the at least one capacitor over the workpiece in the first metallization layer, wherein the first plate and the lower level interconnects are formed simultaneously, forming a capacitor dielectric over the first plate, and forming a second plate in the second metallization layer over the capacitor dielectric, wherein the second plate and the upper level interconnects are formed.