Patent ID: 8385126

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including memory strings each including a plurality of memory cells connected in series, bit lines connected to one end of the memory strings, a source line connected to the other end of the memory strings, and word lines connected to control gate electrodes of the memory cells; and a control circuit configured to execute a reading operation of applying a reading voltage to the control gate electrode of a selected memory cell in a memory string to read data and applying a reading pass voltage to non-selected word lines connected to non-selected memory cells in the memory string to thereby determine whether or not the selected memory cell becomes conductive, the control circuit being configured to be capable of executing a first reading operation and a second reading operation, the first reading operation being an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a first value, and the second reading operation being an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value, and the control circuit being configured to, when executing the second reading operation, set the voltage between the control gate electrode and source to the second value while keeping a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.