Patent ID: 7361846

Claim:
A high electrical performance semiconductor package, comprising: a carrier having a first surface, a second surface opposite to the first surface, and a plurality of conductive vias for electrically connecting the first surface to the second surface; at least one chip attached to the first surface of the carrier; a plurality of via lands disposed in multiple rows on a peripheral area of the first surface of the carrier and electrically connected to the conductive vias; a plurality of fingers disposed around the chip and electrically connected to the corresponding via lands by conductive traces formed on the first surface of the carrier; a plurality of bonding wires for electrically connecting the chip to the fingers, wherein lengths of the bonding wires for transmitting differential pair signals are substantially equal, and lengths of the conductive traces for transmitting the differential pair signals are substantially equal; and a plurality of conductive regions disposed on the second surface of the carrier and electrically connected to the conductive vias.