Patent ID: 7449387

Claim:
A manufacturing method of a double LDD MOS transistor comprising the steps of: forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming a second LDD area by implanting and thermally annealing impurity ions using the gate electrode and the first spacer as a mask; forming a second spacer on both lateral walls of the gate electrode and the first spacer; forming a source-drain diffusion area by implanting and thermally annealing impurity ions using the gate electrode, the first spacer, and the second spacer as a mask; opening the second LDD area located at the bottom of the second spacer by removing the second spacer by selective etching after the source-drain diffusion area is formed; and forming salicide layers on the gate electrode, the opened second LDD area, and the source-drain diffusion area, respectively, by forming and annealing a salicide forming metal on the semiconductor substrate.