Patent ID: 7436722

Claim:
A semiconductor device, comprising: first and second bit lines; a plurality of memory cells coupled to the first and second bit lines; third and fourth bit lines; a first transistor coupled between the first bit line and the third bit line; a second transistor coupled between the second bit line and the fourth bit line; a sense amplifier including a first circuit coupled between the first bit line and the third bit line and between the second bit line and the fourth bit line, and a second circuit coupled between the third bit line and the fourth bit line; a first precharge circuit which precharges the first and second bit lines to a first precharge potential; and a second precharge circuit which precharges the third and fourth bit lines to a second precharge potential, wherein said second circuit amplifies a signal on one of the third and fourth bit lines to a first potential and a signal on the other of the third and fourth bit line to a second potential according to a storage signal from a selected one of the plurality of memory cells, the storage signal being transferred to the sense amplifier via the first circuit, wherein the first precharge potential is between the first and second potentials, wherein the second precharge potential is higher than the first precharge potential, and wherein a gate oxide film of the first transistor and a gate oxide film of the second transistor are thicker than a gate oxide film of a transistor included in the second circuit.