Patent ID: 8077065

Claim:
A data processing device comprising: a DA converter circuit; an amplifier circuit; an AD converter circuit; and a control circuit; wherein said control circuit is arranged to control calibration processing and bit-precision-variable AD conversion processing for said amplifier circuit with an expected gain of 2 n , where “n” represents a positive integer, wherein, in execution of said calibration processing, a gain of said amplifier circuit is calculated based on data obtained by amplifying an analog signal output from said DA converter circuit through use of said amplifier circuit and then converting the thus amplified analog signal through conversion by said AD converter circuit, and also based on data obtained by converting the analog signal through conversion by said AD converter circuit without amplification thereof by said amplifier circuit, wherein, in execution of said bit-precision-variable AD conversion processing, an analog signal amplified by said amplifier circuit with respect to an analog signal under measurement to be enhanced in bit precision is converted by said AD converter circuit, the result of the conversion is multiplied by a ratio of the expected gain to the gain calculated through said calibration processing so as to cancel a gain error, and based on data with the gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision, wherein, in execution of said bit-precision-variable AD conversion processing, an analog signal amplified by said amplifier circuit with respect to an analog signal under measurement to be enhanced in bit precision is converted by said AD converter circuit, the result of the conversion multiplied a ratio of the expected gain to the gain calculated through said calibration processing so as to cancel a gain error, and bit extension processing is performed on data with the gain error canceled to ensure continuity between data having different degrees of bit precision, wherein the number of extended bits in said bit extension processing is represented as “n”, and wherein, in execution of said bit extension processing, when a range to be enhanced in bit precision has a reference point, thereof at “0”, an increase of “n” bits is made on the highest-order bit position side of data with the gain error canceled.