Patent ID: 7599490

Claim:
A block cipher device for a cryptographically secured digital communication system comprising: a pair of first stages connected in parallel and receiving an input data block and a control data block, each first stage defining a respective first data path and comprising a sum modulo-two unit responsive to the control data block and the input data block, and a first nibble swap unit downstream from said sum modulo-two unit and being responsive to an output signal therefrom and the control data block for reordering the output signal front said sum module-two unit; a diffuser connected in both of the first data paths for mixing data therebetween; a key scheduler receiving a key data block and generating a random key data block based thereon; a pair of second stages connected in parallel downstream from said first stages and receiving the random key data block, the control data block and output signals from said first stages, each second stage defining a respective second data path and comprising a first linear modulo unit responsive to the random key data block, one of the output signals from said first stages, and the control data block for performing a modulo summing operation based on a first modulus q, an n th power modulo unit responsive to an output signal from said first linear modulo unit for performing an n th power modulo operation based on a second modulus p, and a second linear modulo unit responsive to the random key data block and an output signal from said n th power modulo unit for performing a modulo summing operation based on a third modulus r, each first, second and third modulus q, p and r being unique from each other, and said pairs of first and second stages each being selectively configurable so that only one first data path and only one second data path are operational while bypassing said diffuser; and an output stage connected to said second stages for generating an output data block for the block cipher.