Patent ID: 8076179

Claim:
A fabrication method for a multi-chip module comprising the steps of: preparing an integrated circuit chip component, the integrated circuit chip component being fabricated by; (i) mounting the integrated circuit chip having a first terminal unit with the first terminal unit upward on a first lower protective layer made of an insulating material on a first substrate, (ii) forming a first upper protective layer made of an insulating material on the first lower protective layer so as to cover the integrated circuit chip, (iii) forming a first interior vertical conducting unit in the first upper protective layer, the first interior vertical conducting unit being connected to the first terminal unit of the integrated circuit chip and exposed on the first upper protective layer, (iv) forming a first expanded wiring unit on the upper surface of the first upper protective layer so as to be connected to the first interior vertical conducting unitRa (v) forming a second upper protective layer on the first upper protective layer, the second upper protective layer covering the first expanded wiring unit, (vi) forming a first exterior vertical conducting unit in the second upper protective layer, the first exterior vertical conducting unit being connected to the first expanded wiring unit and reaching to an upper surface of the second upper protective layer, and (vii) forming a second terminal unit on the upper side of the first exterior vertical conducting unit so as to be positioned on the upper surface of the second upper protective layer; three-dimensionally aligning a plurality of the integrated circuit chip components in a further protective layer at upper and lower layer, the plurality of the integrated circuit chip components meeting the requirement of electric characteristics tests including 100 MHz or higher frequency test, functionary test, AC test and parametric test, and a burn-in test, or having identical quality and reliability thereof; electrically connecting the second terminal unit of the integrated circuit chip component at the lower layer and second terminal unit of the integrated circuit chip component at the upper layer by a further vertical conducting unit extending through the further protective layer; and forming a horizontal wiring and a vertical wiring in the further protective layer to connect the plurality of the integrated circuit chip components.