Patent ID: 8742496

Claim:
A memory cell, comprising: a source-drain structure in a semiconductor substrate wherein said source-drain structure includes a rounded top surface and sidewall surfaces; a first oxide layer formed on said top surface and said sidewall surfaces of said source-drain structure, wherein the thickness of a portion of said first oxide layer that is formed on said top surface of said source-drain structure is greater than the thickness of a portion of said first oxide layer that is formed on said sidewall surfaces of said source-drain structure and a conduction region of said source-drain structure is orthogonal to a direction from one sidewall surface of said source-drain structure to the other and comprises the area between said one sidewall surface of said source-drain structure and said other; a nitride charge storage layer formed on said first oxide layer; a second oxide layer formed on said charge storage layer; and a polysilicon layer formed on said second oxide layer.