Patent ID: 8281210

Claim:
An iterative decoder configured to implement a min-sum with correction algorithm, the iterative decoder having N parity check nodes coupled to M equality constraint nodes, the iterative decoder having a configurable decoder SNR gain versus decoder complexity, the decoder comprising: a first parity check node configured to send an output to a first equality constraint node, wherein responsive to a minimum magnitude of other M−1 inputs to the first parity check node being lower than a pre-determined threshold, the panty check node sends the output having the same minimum magnitude as that of the minimum magnitude of the other M−1 inputs to the first parity check node, whose sign is the product of the signs of all M−1 inputs, wherein responsive to the minimum magnitude of the other M−1 inputs to the first parity check node being greater than the pre-determined threshold, the parity check node subtracts a correction factor in the form of p·2 q from the minimum magnitude, whose sign is the product of the signs of all M−1 inputs, and wherein p and q represent selectable integers such that a higher value of q corresponds to a lower decoder complexity, and the decoder SNR gain is based on the value of P such that a lower magnitude of a difference between the correction factor and an optimal correction factor increases the decoder SNR gain.