Patent ID: 7904775

Claim:
A method, comprising: detecting error injection during execution of a sequence of instruction codes in an integrated circuit having a central processing unit provided for executing such instruction codes, the integrated circuit being configured to perform the detecting, the detecting comprising: during the execution of the sequence, taking off at a plurality of points of the integrated circuit through which signals pass, a plurality of logic signals, including at least one of deterministic address, control and data logic signals involved in the execution of the sequence; masking the plurality of logic signals to produce selected deterministic signals; producing current cumulative signatures based on the selected deterministic logic signals in the plurality of logic signals and in synchronization with a clock signal, each current cumulative signature varying according to a previous cumulative signature and to the deterministic logic signals, until, at an end of the execution of the sequence, a final cumulative signature is obtained; and comparing the final cumulative signature with an expected signature; and triggering at least one protective operation of the integrated circuit in response to detection of an injected error.