Patent ID: 7745278

Claim:
A method of forming a complementary metal oxide semiconductor (CMOS) structure having improved threshold voltage and flatband voltage stability comprising: providing a semiconductor substrate having a first device region and a second device region; forming a dielectric stack atop said semiconductor substrate including said first device region and said second device region, said dielectric stack comprising an insulating interlayer atop a high k dielectric, the high k dielectric present on the semiconductor substrate; removing said insulating interlayer from said first device region, without removing said insulating interlayer from said second device region; forming a gate conductor atop said insulating interlayer in said second device region and said high k dielectric in said first device region, wherein the first device region is an area for at least one nFET device and said second device region is an area for at least one pFET device, wherein said insulating interlayer stabilizes said second device regions threshold voltage and flatband voltage without shifting said first device region's threshold voltage and flatband voltage; and etching said gate conductor, said insulating interlayer and said high k dielectric to provide at least one gate stack in said second device region and at least one gate stack in said first device region, wherein the at least one gate stack in the first device region comprises, from bottom to top, the high k gate dielectric disposed directly on said semiconductor substrate and the gate conductor disposed on the high k gate dielectric, and the at least one gate stack in the second device region comprises, from bottom to top, the high k gate dielectric disposed directly on said semiconductor substrate, an insulating interlayer atop said high k gate dielectric, and the gate conductor atop said insulating interlayer.