Patent ID: 7501869

Claim:
A circuit comprising: a forwarded clock amplifier; a set of delay locked loops coupled to the forwarded clock amplifier; and a family of sets of phase interpolators in one-to-one correspondence with the set of delay locked loops, each delay locked loop to provide a set of clock signals to a corresponding set of phase interpolators; each delay locked loop comprising: a set of delay cells, where each delay cell comprises: a pull-up pMOSFET biased at a bias voltage V PBIAS ; a pull-down nMOSFET biased at a bias voltage V NBIAS ; a pMOSFET comprising a drain and a source connected to the pull-up pMOSFET; and an nMOSFET comprising a drain connected to the drain of the pMOSFET, and a source connected to the pull-down nMOSFET; a charge pump to provide the bias voltage V NBIAS ; and a bias circuit to provide the bias voltage V PBIAS , the bias circuit comprising a differential amplifier comprising a negative input port, a positive input port, and an output port; a pull-up pMOSFET comprising a gate connected to the output port of the differential amplifier, and a drain; a pMOSFET comprising a gate, and a source connected to the drain of the pull-up pMOSFET, and a drain connected to the positive input port of the differential amplifier; an nMOSFET comprising a gate, a drain connected to the positive input port of the differential amplifier, and a source; and a pull-down nMOSFET comprising a gate, a drain connected to the source of the nMOSFET, and a source; wherein the output port of the differential amplifier provides the bias voltage V PBIAS provided the gate of the pMOSFET of the bias circuit is held at a ground voltage, the gate of the nMOSFET of the bias circuit is held at a supply voltage V CC , the gate of the pull-down nMOSFET of the bias circuit is held at the bias voltage V NBIAS , and the negative input port of the differential amplifier is held at the voltage V CC /2.