Patent ID: 8149612

Claim:
A memory array having a plurality of memory cells, each memory cell comprising: a first inverter comprising a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a second inverter comprising a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the second node being coupled to a control terminal of the second transistor; a third inverter comprising a fifth transistor coupled between the reference voltage and a third node for storing the input data and a sixth transistor coupled between the third node and ground, the third node being coupled to a control terminal of the fourth transistor; and a fourth inverter comprising a seventh transistor coupled between the reference voltage and a fourth node for storing the inverted input data and an eight transistor coupled between the fourth node and ground, the fourth node being coupled to a control terminal of the sixth transistor; wherein the third and seventh transistors are implemented with physical dimensions which make the third and seventh transistors stronger than the first and fifth transistors, or the second and sixth transistors are implemented with physical dimensions which make the second and sixth transistors stronger than the fourth and eighth transistors.