Patent ID: 8924613

Claim:
A data processing device which controls transmission of data from bus masters to a memory device, the data processing device comprising: a master arbitrating unit configured generate a command with additional information assigned, the master arbitrating unit selecting one of the bus masters, and the additional information being assigned to a command sent from the one selected bus master; a data buffer which stores write data of a write command in a case where the command with the additional information is the write command; a write command buffer which stores the write command in a case where the command with the additional information is the write command; a read command buffer which stores a read command in a case where the command with the additional information is the read command; a signal issuing unit configured to issue a signal which indicates that storing of the write data is complete; and a command order determining unit configured to select one of a first command and a second command as a command to be issued to the memory device, the first command being the write command stored in the write command buffer and for which the issued signal indicates that the storing of the write data is complete, the second command being the read command stored in the read command buffer, and the command to be issued being whichever of the first command and the second command comes earlier in an order identified with the additional information assigned.