Patent ID: 8089127

Claim:
A dual triggered silicon controlled rectifier (DTSCR) comprising: a semiconductor substrate; an N-well, positioned in the semiconductor substrate; a P-well, positioned in the semiconductor substrate and adjacent to the N-well; a first N+ diffusion region and a first P+ diffusion region, positioned in the P-well, for use as a first electrode of the DTSCR; a second N+ diffusion region and a second P+ diffusion region, positioned in the N-well, for use as a second electrode of the DTSCR; a third P+ diffusion region, positioned in one side of the DTSCR and in direct contact with both the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and in direct contact with both the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage; wherein the third P+ diffusion region and the third N+ diffusion region are positioned across from each other and spaced apart in a direction of a gate width of the first gate.