Patent ID: 8479137

Claim:
A congestive placement preventing apparatus, for modifying a circuit layout, the apparatus comprising: at least one processor and a storage medium, the storage medium configured to store instructions which, when executed by the at least one processor, cause the at least one processor to: perform a congestion analysis on the circuit layout to generate an analysis result; define a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result wherein the congestion region includes electronic cells; and arrange the electronic cells in the congestion region to the congestion region and the share region, wherein the instructions further cause the at least one processor to extend and arrange the electronic cells in the congestion region to the congestion region and the share region, so as to reduce a density of electronic cells in the congestion region, wherein when the density of electronic cells in the congestion region is reduced to a predetermined value, the congestion region becomes a routable region in the congestion analysis performed by the analysis module, wherein the share region comprises a first share portion and a second share portion, and the congestion region, the first share portion and the second share portion are in sequence arranged from the inside out by regarding the congestion region as a center, and wherein the instructions further cause the at least one processor to extend an electronic cell at a first position of the congestion region to a second position in the congestion region or the first share portion according to a first extension ratio, and the second position is calculated according to a center point of the congestion region, the first position and the first extension ratio.