Patent ID: 7451421

Claim:
A method for implementing a design in different programmable logic devices (PLDs), comprising: providing a first programmable logic device including a first plurality of configurable tiles and a plurality of first interconnect lines coupled to the first plurality of configurable tiles, the first PLD being logically divisible into a first portion and a second portion, wherein each of the first interconnect lines comprises a first section included in the first portion and a second section included in the second portion; providing a second PLD comprising a second plurality of the configurable tiles substantially similar to the first portion of the first PLD, and further comprising a plurality of second interconnect lines coupled to the second plurality of configurable tiles and substantially similar to the first sections of the first interconnect lines, wherein each of the second interconnect lines is coupled to another of the second interconnect lines at a boundary of the second PLD to form pairs of the second interconnect lines; wherein the second PLD does not include a second portion substantially similar to the second portion of the first PLD from the first PLD; encoding the first PLD to render the second portion of the first PLD non-operational; providing a software model to design implementation software, wherein the software model describes behavior of the encoded first PLD and further describes the behavior of the second PLD, and wherein the software model is the same for both the encoded first PLD and the second PLD; generating and storing an implementation of a design by the design implementation software using the software model, wherein the implementation can be used in both the first and second PLDs.