Patent ID: 8368434

Claim:
A divide-by-three circuit, comprising: a chain of dynamic flip-flops comprising a first flip-flop, a second flip-flop, and a third flip-flop, wherein a signal path extends through the chain of dynamic flip-flops, and wherein the dynamic flip-flops are synchronously clocked by a clock signal; and a feedback circuit of combinatorial logic that has a first plurality of input leads coupled to a plurality of first locations along the signal path, a second plurality of input leads coupled to a plurality of second locations along the signal path, a propagation delay control input lead, and an output lead coupled to an input lead of the first flip-flop; wherein the plurality of first locations along the signal path comprises a first flip-flop slave stage location and a second flip-flop slave stage location, and the plurality of second locations comprises a first flip-flop master stage location and a second flip-flop slave stage location; wherein selection of master and slave mode operation enhances frequency range of the divide-by-three circuit.