Patent ID: 8429382

Claim:
A processor comprising: a substrate including a perimeter; a primary interconnect trunk situated along a first axis of the substrate, the primary interconnect trunk including first and second opposed ends, the primary interconnect trunk including a data trunk; a secondary interconnect trunk situated along a second axis of the substrate, the first axis intersecting the second axis such that the primary and secondary interconnect trunks divide the processor into first, second, third and fourth quadrants, the secondary interconnect trunk including first and second opposed ends; and a plurality of compute elements being situated in each of the first, second, third and fourth quadrants along the primary interconnect trunk, wherein each of the compute elements couples directly to the primary interconnect trunk; the compute elements of the first quadrant being switchably coupled to the data trunk via a first plurality of data on-ramps that extend across a portion of the data trunk but not fully across the data trunk; the compute elements of the second quadrant being switchably coupled to the data trunk via a second plurality of data on-ramps that extend across a portion of the data trunk but not fully across the data trunk; the compute elements of the third quadrant being switchably coupled to the data trunk via a third plurality of data on-ramps that extend across a portion of the data trunk but not fully across the data trunk; the compute elements of the fourth quadrant being switchably coupled to the data trunk via a fourth plurality of data on-ramps that extend across a portion of the data trunk but not fully across the data trunk; the compute elements of the first, second, third and fourth quadrants being switchably coupled to the data trunk via a plurality of data off-ramps that extend fully across the data trunk.