Patent ID: 7538577

Claim:
A system for configuring a programmable logic device comprising: a first programmable logic device comprising a first serial data input; a shift register coupled with the first programmable logic device, the shift register comprising: a plurality of bits of register storage, a shift register serial data input, a shift register serial data output, a shift register clock input, a parallel-load enable input, and a parallel data input port; and a memory coupled with the first programmable logic device and the shift register; wherein the first programmable logic device is adapted to: provide a first clock signal, receive a program-start signal, at least partially provide a configuration-start signal, and at least partially provide a configuration-status signal; wherein the first serial data input is adapted to receive a first serial configuration data signal; wherein the shift register is adapted to receive an instruction value via the parallel data input port, store the instruction value in the plurality of bits of register storage, and transmit the instruction value via the shift register serial data output; wherein: the shift register serial data input is adapted to receive a first logic signal, the shift register serial data output is adapted to provide a shift register serial data output signal, the shift register clock input is adapted to receive the first clock signal, the parallel-load enable input is adapted to receive the configuration-start signal, the parallel data input port is adapted to receive an instruction value, the instruction value corresponds to a memory instruction, and the shift register is substantially separate from the first programmable logic device; and wherein the memory is adapted to: receive the configuration-status signal, receive the first clock signal, receive the shift register serial data output signal, and provide the first serial configuration data signal.