Patent ID: 7321243

Claim:
A non-inverting register, comprising: a domino stage, coupled to a pulsed clock signal, and for evaluating a logic function according to the states of at least one data signal and a pulsed clock signal, said pulsed clock signal lagging a symmetric clock signal, wherein said domino stage pre-discharges a pre-discharged node low when said symmetric clock signal is high, and opens an evaluation window when said pulsed clock signal goes low, and pulls said pre-discharged node high if it evaluates, and keeps said pre-discharged node low if it fails to evaluate; a write stage, coupled to said domino stage and responsive to said pulsed and symmetric clock signals, which pulls a first preliminary output node low if said pre-discharged node goes high and which pulls said first preliminary output node high when said pre-discharged node and symmetric clock signal are low; an inverter having an input coupled to said first preliminary output node and an output coupled to a second preliminary output node; a low keeper path which keeps said first preliminary output node low when enabled, wherein said low keeper path is enabled when said symmetric clock signal and said second preliminary output node are both high and which is otherwise disabled; a high keeper path which keeps said first preliminary output node high when enabled, wherein said high keeper path is enabled when said second preliminary output node and said pre-discharged node are both low and which is otherwise disabled; and an output stage which provides an output signal based on states of said pre-charged node and said second preliminary output node.