Patent ID: 7902893

Claim:
A clock-signal generating unit for generating an output clock signal with a controlled duty cycle based on an input clock signal, comprising at least one delay line arranged to generate a plurality of mutually delayed output signals at different positions within the delay line based on the input clock signal; a control unit arranged to detect a position within one of the at least one delay line, the output signal of which has a delay, with respect to the input clock signal, that is essentially equal to one period of the input clock signal, and generate an output signal that indicates the detected position; a selection unit arranged to generate a delayed clock signal that has a delay, with respect to a signal associated with the input clock signal, that is essentially equal to a period of the clock signal multiplied with said duty cycle based on output signals from one of the at least one delay line and the output signal of the control unit; and circuitry for generating the output clock signal based on the signal associated with the input clock signal and the delayed clock signal.