Patent ID: 8883600

Claim:
A method for fabricating a transistor with reduced junction leakage current, comprising: forming a layered stack, the layered stack including at least a doped screening layer and an undoped channel layer over the screening layer; forming a gate stack over the undoped channel layer; forming a first spacer on each sidewall of the gate stack; implanting a shallow lightly doped drain region in the channel on either side of the gate stack and extending a defined distance inward from the outer edges of the gate stack; implanting deep lightly doped drain regions on either side of the gate stack to vertically extend the shallow lightly doped drain region a selected distance, the deep lightly doped drain region extending no more deeply than the bottom of the screening layer; forming a second spacer on the first spacer; implanting a source region on one side of the gate stack and a drain region on another side of the gate stack.