Patent ID: 7539931

Claim:
A method for reducing soft errors in logic comprising: obtaining a first delayed clock signal; obtaining a second delayed clock signal; applying a clock signal, the first delayed clock signal, the second delayed clock signal and a data output from a logic circuit to a triple redundant memory element; wherein the time delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit; wherein the time delay of the second delayed clock is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit; wherein an original logic value on the data output from the logic circuit before a soft error occurs is maintained on an output of the triple redundant memory element after the soft error occurs; wherein the triple redundant memory element comprises: three memory elements; a majority voting logic circuit; wherein an output from each memory element is connected to a separate input of the majority voting logic circuit; wherein the clock signal is connected to a first memory element; wherein the first delayed clock signal is connected to a second memory element; wherein the second delayed clock signal is connected to a third memory element.