Patent ID: 7644255

Claim:
An apparatus, comprising: a SIMD processing pipeline having a plurality of data path processing circuits organized into a matrix of M slices and N stages, where M and N are greater than 1 and each data path processing circuit of a given slice and a given stage operates to execute at least a portion of a SIMD instruction and pass a result thereof to a next data path processing circuit of the given slice and a subsequent stage until a destination register of the SIMD processing pipeline is reached; and a storage circuit operating to: (i) store respective sets of enable flags, each set having a respective enable flag for each processing circuit in a respective one of the stages and each set of enable flags being associated with a given SIMD instruction, and (ii) transfer the sets of enable flags from one stage for use with the processing circuits of a next stage each cycle, wherein at least some of the processing circuits at each stage are operable to at least partially disable operation in response to the enable flags transferred to the given stage during the given cycle.