Patent ID: 8593857

Claim:
A matrix-type semiconductor memory device comprising: a first line; a second line; a third line; a fourth line; and a plurality of memory cells, wherein the first line is parallel to the second line, wherein the third line is parallel to the fourth line, wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, wherein the first transistor comprises a oxide semiconductor film, wherein the oxide semiconductor film comprises indium and zinc, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor, wherein a gate of the first transistor is connected to the first line, wherein a source of the first transistor and a source of the second transistor are connected to the third line, wherein a drain of the second transistor is connected to the fourth line, wherein the other electrode of the capacitor is connected to the second line, and wherein the third line is provided between the first line and a substrate.