Patent ID: 7248630

Claim:
A receiver for delivering a data sequence (a k ) at a data rate 1/T from a received sequence (r n ) sampled at a clock rate 1/Ts, asynchronously to the data rate 1/T, the receiver comprising: an adaptive equalizer for delivering an equalized sequence (y n ) from said received sequence (r n ), said equalizer operating at the clock rate 1/Ts and having an equalizer coefficient vector (W n ) controlled by a control vector sequence (s n ) via a control loop; a first sampling rate converter for converting said equalized sequence (y n ) to an equivalent input sequence (x k ) to be fed to an error generator at the data rate 1/T; and an error generator for delivering the data sequence (a k ) from said input sequence (x k ) and an error sequence (e k ) to be used in the control loop, wherein said control loop comprises: a second sampling rate converter for converting a delayed version of said received sequence (r n ) into an intermediate control sequence (i k ) at the data rate 1/T; control information production means for deriving a synchronous control vector sequence (Z k ) at the data rate 1/T from the error sequence (e k ) and said intermediate control sequence (i k ); and temporal interpolation means for deriving the control vector sequence (s n ) from said synchronous control vector sequence (Z k ).