Patent ID: 7782287

Claim:
A data accessing interface coupled between a memory and a source, comprising: a multiplex output module, for outputting M bits of an N-bit digital data in each multiplexing operation to thereby output the N-bit digital data, wherein M and N are both positive integers, M is less than N, and N M is a positive integer; and a sequential input module, for sequentially latching data transmitted through M transmission lines to store the N-bit digital data; wherein the multiplex output module comprises: a buffer unit, for receiving the N-bit digital data from a complete row of the memory; and a multiplex unit, coupled to the buffer unit, for selecting an M bit digital data out of a plurality of M-bit digital data comprised of the N-bit digital data stored in the buffer unit in each multiplexing operation and then outputting the plurality of M-bit digital data one by one, thereby outputting the N-bit digital data.