Patent ID: 7084648

Claim:
A method of testing a semiconductor circuit, the circuit including a pair of contact pads and a biasing circuit for applying a voltage to the pair of contact pads, and further including a sensing circuit for providing a signal indicative of the voltage applied across the contact pads, the method comprising: connecting a load resistor across the pair of contact pads; disabling the biasing circuit; applying a first predetermined voltage to the contact pads; measuring a first output voltage produced by the sensing circuit in response to the first predetermined voltage; applying a second predetermined voltage to the contact pads; measuring a second output voltage produced by the sensing circuit in response to the second predetermined voltage; calculating the voltage gain and voltage offset of the sensing circuit based on the first and second output voltages corresponding to the first and second predetermined voltages, respectively; removing the applied voltage; enabling the biasing circuit to produce a desired voltage across the contact pads; measuring a third output voltage produced by the sensing circuit in response to the desired voltage; determining, from the third output voltage, an actual output voltage produced by the biasing circuit at the contact pads based on the previously calculated voltage gain and voltage offset of the sensing circuit; measuring a load resistor voltage across the load resistor induced by the actual output voltage; and calculating a parasitic resistance in series with the load resistor based upon any difference between the actual output voltage and the load resistor voltage.