Patent ID: 8427794

Claim:
A multi-pole circuit breaker operable to detect a series or parallel arc fault relative to one or more of at least two line conductors being monitored by the circuit breaker, comprising: a first sensor producing a first signal indicative of alternating current flowing through a first line conductor of the at least two line conductors; a second sensor producing a second signal indicative of alternating current flowing through a second line conductor of the at least two line conductors; a first controller operatively coupled to the first sensor, the first controller being programmed with instructions corresponding to a first arc-fault detection algorithm stored on a first memory accessible by the first controller, wherein the first arc-fault detection algorithm is operable to determine whether the arc fault is present on at least the first line conductor as a function of the first signal, and responsive thereto, produce a first output trip signal; a second controller operatively coupled to the second sensor, the second controller being programmed with instructions corresponding to a second arc-fault detection algorithm stored on a second memory accessible by the second controller, wherein the second arc-fault detection algorithm is operable to determine whether the arc fault is present on at least the second line conductor as a function of the second signal, and responsive thereto, produce a second output trip signal; a movable contact operable to interrupt the flow of alternating current from the first line conductor or from the second line conductor responsive to the first output trip signal or the second output trip signal, wherein the first controller is further programmed with instructions corresponding to a first push-to-test algorithm stored on the first memory, wherein the second controller is further programmed with instructions corresponding to a second push-to-test algorithm stored on the second memory, wherein the second push-to-test algorithm is initiated responsive to a push-to-test input signal received by the second controller, the second push-to-test algorithm being operable to produce an indication of a pass or a fail, and responsive thereto, cause an output signal to be sent to the first controller, wherein the first controller, responsive to receiving the output signal from the second controller, initiates the first push-to-test algorithm.