Patent ID: 8687398

Claim:
A sensing circuit in a Content Addressable Memory (CAM), the sensing circuit comprising: a match line electrically coupled to a plurality of CAM cells; and an inverter electrically coupled in a feedback loop to the match line, the inverter including an inverting threshold of the match line, the inverting threshold equal to a first voltage threshold during a pre-charge phase, the inverting threshold equal to a second voltage threshold during an evaluation phase; wherein the inverter receives a phase signal indicating whether the sensing circuit is in the pre-charge phase or the evaluation phase; wherein the output of the inverter is electrically coupled to a supply voltage through a first PMOS (P-type metal-oxide-semiconductor) transistor and a second PMOS transistor arranged in series circuit, wherein the first PMOS transistor is electrically coupled to the match line at its gate terminal, and the second PMOS transistor is electrically coupled to the phase signal at its gate terminal; and wherein the output of the inverter is electrically coupled to a ground voltage through a first NMOS (N-type metal-oxide-semiconductor) transistor and a second NMOS transistor arranged in series circuit, wherein the first transistor is electrically coupled to the match line at its gate terminal, and the second NMOS transistor is electrically coupled to the phase signal at its gate terminal.