Patent ID: 6847087

Claim:
A low-voltage nonvolatile memory array, comprising: a substrate; a cell well of a first conductivity type formed in the substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein the columns of the buried bit lines are isolated from each other and each of which is further divided into plurality of sub-bit line segments with deeply doped source wells of the first conductivity type connected to the cell well; a plurality of memory cell blocks serially arranged over one of the columns of buried bit lines, wherein a memory cell block corresponds to a sub-bit line segment, and each of the memory cell blocks comprises at least one memory transistor having a stacked gate, a source, and a drain; and a local bit line overlying the memory cell blocks and electrically connected to the drain of the memory transistor via a contact plug short-circuiting the drain and the subjacent buried bit line.