Patent ID: 7117284

Claim:
Apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain or a non-secure domain, said plurality of modes including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said exception condition occurs when said processor is operating in that one of said secure domain and said non-secure domain indicated by said domain value; and at least one domain switching exception handler address shared between said plurality of exception conditions for use if said exception condition occurs when said processor is not operating in that one of said secure domain and said non-secure domain indicated by said domain value.