Patent ID: 7005342

Claim:
A method of forming a semiconductor memory device, comprising: forming at least one memory array; forming a number of wordlines coupled to the memory array; forming a number of bitlines coupled to the memory array; forming at least one transistor coupled to the memory array, including: forming a gate dielectric layer on a semiconductor substrate; forming a first conductivity type semiconductor layer on top of the gate dielectric layer; selectively removing a portion of the first conductivity type semiconductor layer to expose the gate dielectric, the portion defining a first conductivity type well region; forming a first conductivity type semiconductor well in the first conductivity type well region, the first conductivity well region being located over a portion of a single second conductivity type semiconductor well, wherein the second conductivity type semiconductor well is sized to accommodate at least one transistor outside the first conductivity well portion; modifying the gate dielectric layer in the first conductivity type well region, the modified gate dielectric being adapted for operation with a second conductivity type gate material; depositing a second conductivity type semiconductor material on the gate dielectric layer and forming a first conductivity type gate from the first conductivity type semiconductor layer; and forming source/drain regions adjacent the gate.