Patent ID: 7991981

Claim:
A data processing system comprising: a processor; a memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; asynchronous memory mover logic; processing logic for completing an asynchronous memory move (AMM) operation, wherein the processor performs an effective address move of data from a first effective address to a second effective address and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address; and wherein, in response to the processor receiving one of a barrier instruction and a SYNC instruction during program execution, the processor stops executing all subsequent memory access instructions, excluding AMM store (ST) instructions, until receipt of a notification of completion of a barrier operation corresponding to the barrier/SYNC instruction, wherein a subsequently received AMM ST instruction is executed by the processor to generate an AMM operation that is performed by the asynchronous memory mover logic while the barrier operation proceeds to completion in parallel, such that the barrier operation does not affect the processing of AMM ST instructions received subsequent to the barrier/SYNC instruction and does not affect the corresponding AMM operations.