Patent ID: 8664633

Claim:
A non-volatile memory device comprising: a substrate; a first wordline on the substrate; an insulating layer on the first wordline; a second wordline on the insulating layer, wherein the insulating layer is between the first and second wordlines and wherein the first wordline is between the second wordline and the substrate; a bit pillar extending adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, wherein the bit pillar is electrically conductive; a first memory cell comprising a first resistance changeable element electrically coupled between the first wordline and the bit pillar, wherein the first memory cell further comprises a first diode element electrically coupled in series with the first resistance changeable element between the first wordline and the bit pillar, and wherein the first diode element comprises a first metal silicide layer and a first silicon layer; and a second memory cell comprising a second resistance changeable element electrically coupled between the second wordline and the bit pillar, wherein the second memory cell further comprises a second diode element electrically coupled in series with the second resistance changeable element between the second wordline and the bit pillar, and wherein the second diode element comprises a second metal silicide layer and a second silicon layer; wherein the bit pillar comprises a semiconductor material adjacent the first and second memory cells having a first dopant concentration, wherein the first silicon layer is electrically coupled between the first metal silicide layer and the semiconductor material of the bit pillar, wherein the second silicon layer electrically coupled between the second metal silicide layer and the semiconductor material of the bit pillar, and wherein the first and second silicon layers have a second dopant concentration that is less than the first dopant concentration.