Patent ID: 7593485

Claim:
A wireless receiver that processes a digital signal having an in-phase (I) signal component including a first, actual DC Offset Component (DCOC) and a quadrature-phase (Q) signal component including a second, actual DCOC, the wireless receiver comprising: a hardware (HW) block for receiving and processing the digital signal to produce a residual DCOC centered at DC, and generating parameters that estimate the residual DCOC, wherein the HW block includes, an I path for receiving the I signal component, and generating first parameters comprising a first residual DCOC estimate centered at DC and a first residual DCOC, wherein the first residual DCOC estimate comprises a first estimated DCOC value equal to a sum of first residual DCOCs accumulated during an accumulation period; and a Q path for receiving the Q signal component, and generating second parameters comprising a second residual DCOC estimate centered at DC and a second residual DCOC, wherein the second residual DCOC estimate comprises a second estimated DCOC value equal to a sum of second residual DCOCs accumulated during the accumulation period; a converter block coupled to the HW block that receives the residual DCOC centered at DC and converts the residual DCOC centered at DC to a residual DCOC centered at intermediate frequency (IF), wherein the converter block includes, a first IQ balance unit that receives a first complex IF signal including the first and second residual DCOC centered at DC; a first complex mixer coupled to the first IQ balance unit that up converts the complex IF signal to a first baseband signal (IQB*e j(wt+φ) ); an anti-alias filter (AAF) coupled to the first complex mixer that attenuates the first baseband signal by an attenuation factor K to generate an attenuated baseband signal (KIQB*e j(wt+φ) ); and a down sampler coupled to the AAF to down sample the attenuated baseband signal by a predetermined factor to generate a second, down converted baseband signal including the residual DCOC centered at IF; and a digital signal processor (DSP) coupled to the HW block and the converter block that receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the DCOC.