Patent ID: 6850429

Claim:
A cross point memory array comprising: a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other; a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer; a plurality of memory plugs located at the intersections of the first layer of conductive array lines and the second layer of conductive array lines, each memory plug being in electrical contact with one of the conductive array lines from the first layer and one of the conductive array lines from the second layer such that each memory plug is associated with a unique pair of conductive array lines; having a low resistive state and a high resistive state, the resistive state of the memory plug capable of being determined when a read voltage is applied across the unique pair of conductive array lines; and exhibiting a hysteresis that is characterized by a first write threshold when the memory plug is in the low resistive state and a second state threshold when the memory plug is in the high resistive state, wherein voltages applied across the unique pair of conductive array lines that are higher than the first write threshold have substantially no effect on the resistive state of the memory plug when the memory plug is in the low resistive state; and voltages applied across the unique pair of conductive array lines that are lower than the second write threshold voltage have substantially no effect on the resistive state of the memory plug when the memory plug is in the high resistive state.