Patent ID: 7933220

Claim:
An apparatus that divides roles in generating test packets for high packet volume tests between a general purpose processor and a configurable logic device, including: a microprocessor with a first memory; a programmable logic device with a second memory, wherein the second memory is not large enough to hold all data required to conduct a particular test, wherein the programmable logic device is coupled to the first memory by at least a local bus; a physical port coupled to the test packets being dispatched from the physical port; wherein the microprocessor comprises circuitry that generates a list of test packet recipes and test packet ingredients, and stores the list in the first memory for the particular test; and circuitry that generates the test packet ingredients and the test packet recipes, and stores the test packet ingredients and the test packet recipes in the first memory; wherein the programmable logic device further comprises circuitry that retrieves the list via at least the local bus into the second memory; circuitry that retrieves the test packet ingredients and the test packet recipes according to the list, via at least the local bus into the second memory, in segments such that the second memory is not overflowed; circuitry that generates test packets that combine the test packet ingredients according to the test packet recipes, and adding timestamps; and circuitry that dispatches the test packets via the physical port according to the timestamps.