Patent ID: 8209652

Claim:
A semiconductor device including a decoupling capacitor, the device comprising: a main power voltage supplying line arranged in a first direction and configured to supply a power voltage; a main ground voltage supplying line arranged in the first direction and configured to supply a ground voltage; a plurality of decoupling capacitor cells arranged between the main power voltage supplying line and the main ground voltage supplying line in the first direction and in a second direction perpendicular to the first direction, and configured to reduce power noise generated by the power voltage and the ground voltage; a plurality of sub power voltage supplying lines connected to the main power voltage supplying line and arranged in the second direction in borders of the plurality of decoupling capacitor cells and configured to supply the power voltage to the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines connected to the main ground voltage supplying line and arranged in a grid form defined by the first and second directions in the borders of the plurality of decoupling capacitor cells and configured to supply the ground voltage to the plurality of decoupling capacitor cells, wherein each of the plurality of decoupling capacitor cells has a first active region and a second active region, the first active region disposed to receive the ground voltage, the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor, wherein the plurality of decoupling capacitor cells further comprises: a semiconductor substrate having a first conductive type; and a gate poly layer formed on a portion of the semiconductor substrate excluding the first and second active regions, the gate poly layer being electrically insulated from the semiconductor substrate, wherein the first active region is configured to receive the ground voltage from an adjacent sub ground voltage supplying line among the plurality of sub ground voltage supplying lines, and the second active region is arranged to avoid the first active region and the gate poly layer region and is configured to receive the power voltage from an adjacent sub power voltage supplying line among the plurality of sub power voltage supplying lines.