Patent ID: 6912698

Claim:
A skew lot for an integrated circuit design including a plurality of field-effect transistors having an average gate-to-source capacitance, the skew lot comprising: a set of slow integrated circuits configured for test purposes, each slow integrated circuit including a plurality of slow field-effect transistors interconnected according to the integrated circuit design; and a set of fast integrated circuits configured for test purposes, each fast integrated circuit including a plurality of fast field-effect transistors interconnected according to the integrated circuit design; wherein each transistor in the plurality of field-effect transistors in the integrated circuit design has a nominal gate-insulator thickness (tn) and a nominal channel length (Ln), which define a ratio Ln/tn: wherein the slow field-effect transistors have an average channel-length-to-gate-insulator-thickness ratio greater than the ratio Ln/tn; and wherein the fast field-effect transistors have an average channel-length-to-gate insulator-thickness ratio less than the ratio Ln/tn.