Patent ID: 7969204

Claim:
A sample hold circuit for analog signals, comprising: a sample unit, sampling an analog signal when the sample hold circuit is in a first state; a plurality of capacitors, coupled to the sample unit, and eliminating a direct current (DC) offset voltage of the analog signal when the sample hold circuit is in a second state; a control module, coupled to the capacitors, and adjusting a number of the capacitors coupled to a common voltage according to a magnitude of the DC offset voltage, so as to determine a capacitance for eliminating the DC offset voltage; and a hold unit, coupled to the sample unit, and outputting an alternating current (AC) signal of the analog signal when the sample hold circuit is in the second state; wherein the control module comprises: a control unit; and a plurality of multiplexers, coupled to the control unit, and having output terminals coupled to the corresponding capacitors, wherein each of the multiplexers receives a first reference voltage, a second reference voltage and the common voltage, and is controlled by the control unit to output one of the first reference voltage, the second reference voltage and the common voltage through the output terminal.