Patent ID: 8422189

Claim:
A serially connected surge suppression optimization device, comprising: an input terminal; an output terminal; and a plurality of surge suppression units serially mounted between the input terminal and the output terminal, and having at least one pair of parallel inductors and a plurality of surge absorption units respectively connected with a rear end of each of the pair of inductors; wherein the pair of parallel inductors mounted in the surge suppression unit in a pre-stage and the pair of parallel inductors mounted in the surge suppression unit in a post-stage have different conductance values, the plurality of surge suppression units and the parallel inductors mounted in the surge suppression units in the pre-stage and the post-stage having different conductance values to reduce energy of a surge flowing in the input terminal, and to reduce a residual surge voltage; wherein the parallel inductors mounted in the surge suppression unit in the pre-stage have a medium conductance value range and the parallel inductors mounted in the surge suppression unit in the post-stage have a low conductance value range.