Patent ID: 8818304

Claim:
A transceiver comprising: a voltage controlled oscillator to generate a first sinusoidal signal and a second sinusoidal signal having a phase delay with respect to the first sinusoidal signal; a mixer to receive the first and second sinusoidal signals; a first buffer to receive the first sinusoidal signal, the first buffer to conver the first sinusoidal signal to a first rectangular wave signal; a second buffer to receive the second sinusoidal signal, the second buffer to convert the second sinusoidal signal to a second rectangular wave signal; a logic circuit to receive the first and second rectangular wave signals, the logic circuit to perform logical operation processing on the first and second rectangular wave signals to generate a logic signal with a predetermined duty cycle; and a class E power amplifier to receive the logic signal, the class E power amplifier to perform amplification operation based on the logic signal, wherein the first and second buffers are composed of the same circuit, the first and second buffers include a first capacitor, a first resistor, a first P-channel transistor, a second P-channel transistor, a first N-channel transistor, and a second N-channel transistor, the first capacitor has one end connected to input sides of the first and second buffers, the first resistor has one end connected to the other end of the first capacitor, the first P-channel transistor has a source connected to a higher voltage source, and has a gate connected to the other end of the first capacitor, the first N-channel transistor a drain connected to a drain of the first P-channel transistor and the other end of the first resistor, has a gate connected to the other end of the first capacitor, and has a source connected to a lower voltage source, the second P-channel transistor has a source connected to the higher voltage source, has a gate connected to the other end of the first resistor, and has a drain connected to output sides of the first and second buffers, the second N-channel transistor has a drain connected to a drain of the second P-channel transistor, has a gate connected to the other end of the first resistor, and has a source connected to the lower voltage source.