Patent ID: 7944750

Claim:
A non-volatile memory integrated circuit device comprising: a. a body of semiconductor material predominantly of one conductivity type, the body having a surface; b. a first well region having a conductivity type opposite that of the body, the first well region extending into the body from the surface; c. a second well region having a conductivity type opposite that of the body, the second well region extending into the body from the surface, wherein the first well region and second well region do not overlap; d. a source well region having a conductivity type the same as that of the body, the source well region extending into the body from the surface, wherein the source well region is contained within the first well region; e. a drain well region having a conductivity type the same as that of the body, the drain well region extending into the body from the surface, wherein the drain well is contained within the first well region, and wherein the source well region is separated from the drain well region by a distance; f. an insulation layer, wherein the insulation layer is formed on the surface; g. a floating gate, wherein the gate overlies the surface by an insulation distance, separated by an insulating material and wherein the floating gate substantially spans the distance and further substantially spans the second well region, wherein the floating gate comprises an uninterrupted electrical conducting path extending from the first well region to the second well region; h. means for applying a program voltage to the first well region and to the source well region; and i. means for applying a program bias voltage to the second well region.