Patent ID: 8406271

Claim:
A spread spectrum clock generating circuit, comprising: an external PLL (phase-locked loop); and an internal PLL, wherein the external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively, wherein the frequency divider is connected to the phase detector in order to form an external loop; the internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively, wherein an output terminal of the voltage-controlled oscillator is connected with a counter, and an output terminal of the counter is connected to an input terminal of the oscillator in order to form an internal loop, wherein a direct outputting clock of the voltage-controlled oscillator outputs a spread spectrum clock through an output buffer; the outputted spread spectrum clock is also sent to the counter; after counting M clock cycles, the counter outputs a pulse signal and sends the pulse signal into the input terminal of the voltage-controlled oscillator so as to form the internal loop, wherein M is a natural number selected randomly.