Patent ID: 7468615

Claim:
A level shifter circuit for shifting an input signal having a first voltage range that extends from a low voltage to a first voltage, to an output signal having a second voltage range that extends from the low voltage to a second voltage, wherein the first voltage is different from the second voltage, the level shifter circuit comprising: an inverter powered by the first voltage, wherein the inverter is coupled to provide a complement of the input signal; a differential input stage receiving the input signal and the complement of the input signal, wherein the complement of the input signal has the first voltage range; a current mirror stage powered by the second voltage and generating the output signal of the level shifter circuit; a protection stage coupled between the differential input stage and the current mirror stage, wherein the protection stage is disabled based on a disable signal, and wherein the protection stage includes at least one transistor fabricated having a thick oxide thickness; wherein the protection stage comprises: a first protection transistor having a source, a drain, and a gate, wherein the gate of the first protection transistor is coupled to the disable signal, and a second protection transistor having a source, a drain, and a gate, wherein the gate of the second protection transistor is coupled to the disable signal; wherein the differential input stage comprises: a third transistor having a source, a drain, and a gate, wherein the source of the third transistor is coupled to the low voltage, the gate of the third transistor is coupled to the input signal, and the drain of the third transistor is coupled to the source of the first protection transistor, and a fourth transistor having a source, a drain, and a gate, wherein the source of the fourth transistor is coupled to the low voltage, the gate of the fourth transistor is coupled to the complement of the input signal, and the drain of the fourth transistor is coupled to the source of the second protection transistor; and a capacitor coupled between the gate of the third transistor and the drain of the first protection transistor.