Patent ID: 7480611

Claim:
A method for increasing the usable memory capacity of a logic simulation hardware emulator during an emulation run, the method comprising the steps of: transforming an original logical array within a logic model into a transformed logical array during a logic synthesis operation, wherein a row within the transformed logical array comprises a plurality of merged rows from the original logical array; modifying read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time; loading the logic model and the modified read and write port logic into a physical memory of an emulation system residing within the logic simulation hardware emulator; executing an emulation run on the emulation system, wherein a host workstation reads from and writes to the transformed logical array within the emulation system via the modified read and write port logic, the emulation run producing a recalculated model state result; and providing the recalculated model state result from the emulation system to the host workstation.