Patent ID: 8531872

Claim:
A semiconductor integrated circuit comprising: a static random access memory (SRAM) provided on a large scale integrated circuit (LSI) chip, the SRAM including: a pair of bit lines, a word line, and a memory cell including a pair of load transistors coupled to first and second storage nodes, a pair of drive transistors coupled to the first and second storage nodes, and a pair of transfer transistors, a first transfer transistor of the transfer transistor pair being coupled between one of the bit lines of the pair of bit lines and the first storage node, and a second transfer transistor of the transfer transistor pair being coupled between the other bit line of the pair of bit lines and the second storage node, the first and second transfer transistors of the transfer transistor pair having respective gate electrodes coupled to the word line commonly, wherein the pair of load transistors are P type transistors provided on an N well of the LSI chip, and the pair of drive transistors and the pair of transfer transistors are N type transistors provided on a P well of the LSI chip; a control switch to supply selectively at least first and second voltages, which are different voltages from each other, for the N well and to supply selectively at least third and fourth voltages, which are different voltages from each other, for the P well; and a nonvolatile memory which stores first information indicative of which of at least the first and second voltages is supplied for the N well by the control switch, and which stores second information indicative of which of at least the third and fourth voltages is supplied for the P well by the control switch.