Patent ID: 8040156

Claim:
A lock detection circuit comprising: a front-end lock detector configured to receive an up signal or a down signal based on a phase difference between a reference signal and a feedback signal, and to output a preliminary lock detection signal indicating lock states of the reference signal and the feedback signal according to the up signal or the down signal; and a back-end lock detector configured to receive the preliminary lock detection signal from the front-end lock detector to output a final lock detection signal that maintains a high state for a preset time period, wherein the front-end lock detector includes: first and second delay devices configured to respectively delay the up and down signals for a predetermined time period and to output delayed up and down signals; a first D flip-flop receiving the delayed up signal and outputting the received signal in response to the down signal; a second D flip-flop receiving the delayed down signal and outputting the received signal in response to the up signal; and a NOR gate configured to perform a NOR operation on output signals of the first and second D flip-flops to output a high or low preliminary lock detection signal, wherein the back-end lock detector includes: a third D flip-flop receiving the preliminary lock detection signal and delaying the received signal as long as a time interval of the reference signal; a fourth D flip-flop receiving an output signal of the thrid D flip-flop and delaying the output signal of the third D flip-flop as long as the time interval of the reference signal; and an AND gate configured to perform an AND operation on the output signals of the third and fourth D flip-flop to output the final lock detection signal that maintains an active state for the preset time period, and wherein the back-end lock detector includes only two D flip-flops and outputs the final lock detection signal without using a divider.