Patent ID: 7724033

Claim:
A programmable integrated circuit, comprising: a logic core; a source input/output (I/O) bank comprising at least one source I/O pin, wherein the source I/O bank operates in normal operating mode and the source I/O pin is coupled to the logic core; a destination I/O bank comprising at least one destination I/O pin, wherein the destination I/O bank operates in normal operating mode and the destination I/O pin is coupled to the logic core; and a bypass routing bus that selectively couples to the source I/O bank and the destination I/O bank and bypasses the logic core; wherein the bypass routing bus comprises a plurality of bypass routes and a plurality of destination bypass signal generators, wherein each of the plurality of bypass routes is coupled to an input of at least one destination bypass signal generator, and wherein, responsive to the logic core entering low power mode and becoming inactive, the source I/O pin and the destination I/O pin are disconnected from the logic core and are coupled to the bypass routing bus, and wherein the bypass routing bus detects an I/O signal from the source I/O pin, responsively generates a bypass signal that is provided to the destination I/O bank and, responsive to the bypass signal, generates an output bypass signal on the destination I/O pin.