Patent ID: 7402490

Claim:
A method for manufacturing a memory device, the memory device comprising: a semiconductor body with at least one memory cell arranged in said semiconductor body; source and drain regions formed by doped regions in said semiconductor body and limited by junctions; a gate dielectric over a surface of said semiconductor body between said source and drain regions and having a layer thickness; a gate electrode over said gate dielectric; and a charge-trapping layer formed within said gate dielectric, the charge-trapping layer comprising two strips that are each located between an upper boundary of said junctions and said gate-electrode and which are enclosed by said gate dielectric, in which: in a first step, a layer of a material provided as gate dielectric and a layer of a material provided for said gate electrode are deposited and structured on said surface of said semiconductor body or substrate to form said gate electrode with sidewalls; in a second step, an etching process is performed to remove parts of said gate dielectric from beneath said gate electrode on opposite sides of said gate electrode; in a third step, oxide layers are produced on upper and lower surfaces, where said gate dielectric has been removed and after said gate dielectric has been removed, leaving spaces provided for said strips of said charge-trapping layer; in a fourth step, a material provided for said charge-trapping layer is deposited to fill said spaces; in a fifth step, excess deposits of said material are removed to form said strips; in a sixth step, sidewall spacers are formed at said gate electrode; and in a seventh step, an implantation is performed to produce said source and drain regions; wherein a thickness of the gate dielectric and a thickness of the strips are adapted to facilitate electron tunneling into the charge-trapping layer during an erasure process in which a positive voltage is applied to the gate electrode; and wherein the gate dielectric comprises silicon dioxide and the charge-trapping layer comprises silicon nitride, and wherein a ratio of said layer thickness of said charge-trapping layer and said layer thickness of said gate dielectric in said area between said strips is between 0.3 and 0.7.