Patent ID: 8279233

Claim:
A response speed compensating system, comprising: a circuit for compensating response speed configured to compare voltages of a current image and a previous image received form an external source, the circuit configured to change a gray voltage of the current image according to the difference between a gray voltage of the previous image and the gray voltage of current image; an internal frame memory configured to store the current image and output the previous image in response to a control signal, the internal frame memory comprising N sub frame memories formed in a single chip with the circuit for compensating response speed, wherein N is a natural number; a frame memory controller configured to generate the control signal in order to store the current image in the internal frame memory and to output the previous image from the internal frame memory, the frame memory controller comprising N sub frame memory controllers corresponding to each sub frame memory; and an encoder configured to generate a compressed current image by compressing the current image; a first decoder configured to generate a restored previous image by restoring a compressed previous image; and a data flow controller configured to transmit the compressed current image to the frame memory controller and to transmit the compressed previous image to the circuit for compensating response speed, the data flow controller comprising N write FIFO circuits and N read FIFO circuits corresponding each of the N sub frame memories, wherein the data flow controller comprises: a circuit for assigning an order of compression data, and which is configured to divide the compressed current image into a plurality of data groups based on a data bus width of the compressed current image inputted to the data flow controller.