Patent ID: 7278012

Claim:
A microprocessor comprising an instruction pipeline that includes or is associated with: an instruction cache configured to cache instructions for fetching into the instruction pipeline; a branch target cache configured to store branch target information for known branch instructions; a first branch history table configured to store first branch prediction information; a second branch history table configured to store second branch prediction information; and branch control logic configured to predict branch instructions as taken or not taken according to the first branch prediction information for branch instructions that are branch target cache hits, and according to the second branch prediction information for branch instructions that are branch target cache misses, wherein the microprocessor is configured to initiate accesses to the first and second branch history tables responsive to fetching an instruction address into the instruction pipeline, and further configured to abort the access to the second branch history table responsive to detecting that the instruction address is a hit in the branch target cache, such that a full access of the second branch history table is avoided for branch instructions that are branch target cache hits.