Patent ID: 7772656

Claim:
A device, comprising: a first single-crystal silicon layer separated from a base substrate by a buried oxide layer, a top surface of said buried oxide layer on a top surface of said substrate, a top surface of said first single crystal silicon layer on a top surface of said buried oxide layer; a first gate dielectric layer on a top surface of said a first single-crystal silicon layer; a second single-crystal silicon layer on a top surface of said first gate dielectric layer; a second gate dielectric layer on a top surface of said second single-crystal silicon layer; a single-crystal silicon fin formed on a top surface of said third gate dielectric layer; third and fourth gate dielectric layers formed on sidewalls of said single-crystal silicon fin; a dielectric cap formed on a top surface of said single-crystal silicon fin; a polysilicon gate on said second, third and fourth gate dielectric layers; a planar FET, said FET comprising a first channel region in said second single-crystal silicon layer under said polysilicon gate, first and second source/drains on opposite sides of said first channel region, said first and second gate dielectric layers, said first single-crystal silicon layer being a back gate of said planar FET, said polysilicon gate being a top gate of said planar FET; and a FinFET, said FinFET comprising a second channel region in said single-crystal-silicon fin, said third and fourth gate dielectric layers, third and fourth source/drains in said single-crystal silicon fin on opposite first and second ends of said second channel region, said polysilicon gate also being a gate of said FinFET.