Patent ID: 8564355

Claim:
A clock device comprising: a clock circuit to generate a plurality of clock signals including a first clock signal generated by a first phase locked loop (PLL) operating based on a reference clock from an external of the clock device and a second clock signal generated by a second PLL operating based on a reference clock from the first PLL, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part, wherein the reset part resets the first PLL and the second PLL when the determination part determines to reset the clock circuit, resets the second PLL when the second PLL is in an unlock state, and resets the second PLL after resetting of the first PLL when the first PLL is in the unlock state.