Patent ID: 8420491

Claim:
A method of fabricating a semiconductor structure, the method comprising: forming an NFET gate and a PFET gate on a surface of a substrate; forming a raised source and raised drain adjacent to the NFET gate and forming a raised source and raised drain adjacent to the PFET gate; forming silicide regions on the raised source and raised drain adjacent to the NFET gate and PFET gate; depositing at least one protective layer over the surface of the semiconductor structure, such that the at least one protective layer covers the gate, raised source, and raised drain of the NFET and the PFET; and planarizing the semiconductor structure to lower the protective layer to the level of the silicide regions, such that the raised source and raised drain of the PFET and NFET, and the PFET and NFET gates are of equal height above the surface of the substrate, thereby forming a planarized surface of the semiconductor structure; depositing a first film layer over the planarized surface of the semiconductor structure, a second film layer over the first film layer and a third film layer over the second film layer; wherein the first film layer and the third film layer comprise a nitride layer, and wherein the second film layer comprises an oxide layer; depositing a resist layer over the third film layer; removing a portion of the resist layer, thereby exposing a portion of the third film layer; removing the exposed portion of the third film layer and a portion of the second film layer underneath the exposed portion of third film layer, thereby creating an opening exposing a portion of the first film layer; removing the remainder of the resist layer; and depositing a conformal film layer over the semiconductor structure covering the remaining of the third film layer and sidewalls of the opening.