Patent ID: 7286385

Claim:
A memory circuit, comprising: a plurality of word lines; a plurality of pairs of complementary bank bit lines; a plurality of block select lines; and a plurality of block circuits, each of the block circuits comprising: a local bit line; a first transistor including a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source supplying a first voltage; a second transistor including a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit; wherein at least two block circuits are connected to a given pair of bank bit lines, the at least two block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.