Patent ID: 8218364

Claim:
An integrated circuit, comprising: a memory array on a substrate, including: a plurality of memory cells arranged in rows and columns, each memory cell having two doped regions and a channel region therebetween, each pair of adjacent memory cells being coupled by a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member; a first word line coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell; a plurality of bit lines, each bit line designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N−1) memory cell; a first global bit line coupled to the first bit line and the fifth bit line; a second global bit line coupled to the third bit line and the seventh bit line; a third global bit line coupled to the second bit line and the sixth bit line; a fourth global bit line coupled to the fourth bit line and the eighth bit line; a first select line coupling the first global bit line to the first bit line via a first switch; a second select line coupling the second global bit line to the third bit line via a second switch; a third select line coupling the first global bit line to the fifth bit line via a third switch; a fourth select line coupling the second global bit line to the seventh bit line via a fourth switch; a fifth select line coupling the third global bit line to the second bit line via a fifth switch, the fifth select line coupling the third global bit line to the sixth bit line via a sixth switch; and a sixth select line coupling the fourth global bit line to the fourth bit line via a seventh switch, the sixth select line coupling the fourth global bit line to the eighth bit line via an eighth switch.