Patent ID: 7723178

Claim:
A semiconductor structure fabrication method, comprising: providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer, wherein the first semiconductor layer consists of a semiconductor material; forming a second semiconductor layer on and in direct physical contact with the first semiconductor layer, wherein the second semiconductor layer consists of the semiconductor material; after said forming the second semiconductor layer is performed, forming a dielectric top portion and a first STI (Shallow Trench Isolation) region in the second semiconductor layer, wherein the dielectric top portion is in direct physical contact with the dielectric bottom portion, and wherein a portion of said second semiconductor layer is located between the first STI region and the dielectric top portion such that said portion of the second semiconductor layer separates the first STI region from the dielectric top portion; and forming a structure consisting of a first alignment mark region, a second alignment mark region, and a dielectric region surrounding a portion of said first alignment mark region and a portion of said second alignment mark region, wherein said first alignment mark region, said second alignment mark region, and said dielectric region each comprise a dielectric material, wherein said first alignment mark region and said second alignment mark region are formed within said first semiconductor layer such that a top surface of said first alignment mark region and a top surface of said second alignment mark region are each formed coplaner to a top surface of said first semiconductor layer, and wherein said dielectric region is formed within said first semiconductor layer and said second semiconductor layer.