Patent ID: 8580591

Claim:
Method of manufacturing a vertical Positive-Intrinsic-Negative (PIN) diode ( 30 ), comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer ( 32 ), an intrinsic layer ( 33 ) and a P-type layer ( 34 ); and forming an anode contact of the vertical Positive-Intrinsic-Negative (PIN) diode ( 30 ) by forming an anode metallization ( 35 ) on a first portion ( 34 a ) of the P-type layer ( 34 ) defining an anode region; characterized by further comprising: forming an electrically insulating layer ( 36 ) around the anode region ( 34 a ) such that a first portion of the intrinsic layer ( 33 ) extends vertically between the N-type layer ( 32 ) and the anode region ( 34 a ) and second portions of the intrinsic layer ( 33 ) extend vertically between the N-type layer ( 32 ) and the electrically insulating layer ( 36 ); forming a trench ( 38 ) in the electrically insulating layer ( 36 ) and in the second portions of the intrinsic layer ( 33 ) so as to expose a portion of the N-type layer ( 32 ) defining a cathode region and to define a sacrificial side-guard ring ( 36 a ) constituted by a portion of the electrically insulating layer ( 36 ) that extends laterally between the trench ( 38 ) and the anode region ( 34 a ) and laterally surrounds said anode region ( 34 a ); and forming a cathode contact of the vertical Positive-Intrinsic-Negative (PIN) diode ( 30 ) by forming a cathode metallization ( 39 ) on the exposed portion of the N-type layer ( 32 ) defining the cathode region; wherein forming the electrically insulating layer ( 36 ) comprises: carrying out the ion implantation in a second portion of the P-type layer ( 34 ), which is distinct from the first portion ( 34 a ) of the P-type layer ( 34 ) defining the anode region ( 34 a ) and which laterally surrounds said anode region ( 34 a ).