Patent ID: 7961013

Claim:
An inverter circuit, comprising: a first transistor of N channel and a second transistor of P channel which receive an input signal in parallel; a level shifter which detects the potential of an output signal derived from a connection point of said first transistor and said second transistor; and a third transistor which controls, upon receipt of an output of said level shifter, whether or not the input signal is inputted to either one of said first transistor and said second transistor, wherein said level shifter includes: a control inverter including a sixth transistor for receiving the output signal and a seventh transistor connected to a drain terminal of the sixth transistor; and a compensating inverter including an eighth transistor for receiving the input signal at the gate terminal and a ninth transistor connected to a drain terminal of the eighth transistor, and the control inverter and the compensating inverter are connected in a complementary manner.