Patent ID: 7525354

Claim:
A method of generating a clock output signal, comprising: generating a first delayed signal by delaying a clock reference signal with a time delay of a coarse delay line; generating a second delayed signal by delaying the clock reference signal with the time delay of the coarse delay line and a time delay of a first local coarse delay unit; generating a third delayed signal by delaying the clock reference signal with the time delay of the coarse delay line, the time delay of the first local coarse delay unit, and a time delay of a second local coarse delay unit; and generating a clock output signal using a phase mixer configured to adjust a particular time delay of the clock output signal by fine-shifting: based on the first delayed signal, when a phase of the clock output signal lags a phase of the clock reference signal by at least the time delay of the first local coarse delay unit; based on the second delayed signal, when the phase of the clock output signal lags the phase of the clock reference signal by less than the time delay of the first local coarse delay unit and leads the phase of the clock reference signal by less than the time delay of the second local coarse delay unit; and based on the third delayed signal, when the phase of the clock output signal leads the phase of the clock reference signal by at least the time delay of the second local coarse delay unit; wherein the phase mixer does not receive the clock reference signal.