Patent ID: 7495482

Claim:
A semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, comprising: a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of said power device in the high-potential side and a second state showing the non-conduction of said power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting said first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting said first level-shifted pulse signals from set input terminal and said second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of said SR-type flip-flop circuit by at least the pulse width of said first and second pulse signals.