Patent ID: 8860080

Claim:
An integrated circuit comprising: a power high pin configured to receive a first supply voltage; a power low pin configured to receive a second supply voltage; a signal pin configured to receive a signal; a first NPN bipolar transistor including an emitter electrically connected to the signal pin; a first PNP bipolar transistor including an emitter electrically connected to the power high pin, wherein the first PNP bipolar transistor and the first NPN bipolar transistor are cross-coupled and configured to operate as a first thyristor protection structure between the power high pin and the signal pin; a second NPN bipolar transistor including an emitter electrically connected to the power low pin; a third NPN bipolar transistor including an emitter electrically connected to the power low pin; a second PNP bipolar transistor including an emitter electrically connected to the signal pin, wherein the second PNP bipolar transistor and the third NPN bipolar transistor are cross-coupled and configured to operate as a second thyristor protection structure between the signal pin and the power low pin, wherein the first PNP bipolar transistor and the second NPN bipolar transistor are cross-coupled and configured operate as a third thyristor protection structure between the power high pin and the power low pin.