Patent ID: 7614564

Claim:
A method for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal, the method comprising the steps of: receiving the encoded data signal, each binary data item of the encoded data signal having the same duration, and each binary data item of the encoded data signal having one period of a periodic square wave when the binary data item is a first binary state or two periods of a periodic square wave when the binary data item is a second binary state; generating, from the encoded data signal, an edge detection signal consisting of four pulses per binary data item of the encoded data signal; sampling a level of the encoded data signal once every four pulses of the edge detection signal, and generating a binary signal of decoded data according to the level of the encoded data signal that is sampled; and generating, from the edge detection signal, a binary clock signal that is synchronous with the encoded data signal, the binary clock signal changing logic state every two pulses of the edge detection signal.