Patent ID: 8300475

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; and a control unit to control a signal applied to the plurality of memory cells, each of the plurality of memory cells being settable to: a first state having a first threshold voltage distribution: a second state having a second threshold voltage distribution of a voltage higher than the first threshold voltage distribution; and a third state having a third threshold voltage distribution of a voltage between the first threshold voltage distribution and the second threshold voltage distribution, the control unit, in an operation of setting a second memory cell to the second state and setting a third memory cell to the third state, the second memory cell being one of the plurality of memory cells, the third memory cell being another one of the plurality of memory cells, configured to perform: a first operation of setting the plurality of memory cells to the first state; a second operation of setting the second memory cell to a state having a threshold voltage distribution between the second threshold voltage distribution and the third threshold voltage distribution after the first operation; a third operation of performing a weak programming to increase a threshold voltage distribution of the plurality of memory cells after the second operation; and a fourth operation of setting the third memory cell to the third state after the third operation.