Patent ID: 8179173

Claim:
An electronic circuit for distributing a clock signal to a plurality of clock destinations comprising: a plurality of phase adjustment circuits, each corresponding to a respective one of the plurality of clock destinations for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal received from the respective one of the clock destinations; a plurality of phase detectors, each at the respective one of the clock destinations for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; a plurality of loop filters, each at the respective one of the clock destinations and each corresponding to a respective one of the plurality of phase detectors for generating and transmitting said respective DC voltage feedback signals, each corresponding to a phase shift in the clock signal at the respective one of the clock destinations, detected by the respective one of the phase detectors; and a plurality of current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals, wherein each phase adjustment circuit comprises a pair of push-pull digital-to-analog converters (DACs) programmable to adjust the phase shift of the clock signal for the respective one of the clock destinations.