Patent ID: 8775998

Claim:
A design support device that supports design of a three-dimensional integrated circuit that is composed of a plurality of semiconductor chips arranged in layers including a first semiconductor chip and a second semiconductor chip, the design support device comprising: a non-transitory memory device that stores a program; and a processing device that executes the program to cause the design support device to operate as: a through-via placement unit operable to determine respective placement positions of one or more through-vias on the first semiconductor chip, the through-vias each penetrating the first semiconductor chip to connect to the second semiconductor chip; a reserved cell placement unit operable to determine, based on the respective placement positions of the through-vias that have already been determined by the through-via placement unit, respective placement positions of one or more reserved cells on the first semiconductor chip where all other cells are prohibited from being placed, the reserved cells each penetrating the first semiconductor chip, and the respective placement positions of the reserved cells each being at a distance from a corresponding one of the respective placement positions of the through-vias; and a generation unit operable to generate layout data that includes the respective placement positions of the through-vias and the respective placement positions of the reserved cells, wherein when the design of the three-dimensional integrated circuit is changed such that the placement positions of the through-vias determined by the through-via placement unit are changed, the respective placement positions of the reserved cells are determined as respective new placement positions of the through-vias after the change.