Patent ID: 7309636

Claim:
A method of manufacturing a high-voltage metal-oxide-semiconductor (MOS) device, comprising: providing a semiconductor substrate having thereon a first ion well with a first conductivity type; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching away portions of the silicon nitride layer to form an active area mask pattern that covers a channel region, a drain region, a source region and a device isolation region of the high-voltage MOS device; performing an oxidation process to grow a first field oxide layer, a second field oxide layer and a third field oxide layer spaced-apart from one another on surface areas of the semiconductor substrate that are not covered by the active area mask pattern, wherein the first field oxide layer encloses the drain region, while the second field oxide layer encloses the source region; removing the active area mask pattern; removing the pad oxide layer; growing a gate oxide layer on the channel region; forming a gate on the gate oxide layer; performing a first ion implantation process to form a drain doping region in the drain region and a source doping region in the source region, wherein the drain doping region and the source doping region both have a second conductivity type; and performing a second ion implantation process to form a device isolation diffusion region with the first conductivity type in the device isolation region.