Patent ID: 7173327

Claim:
An apparatus comprising a first semiconductor integrated circuit comprising: a first surface and a second surface that are opposite to each other; and a clock distribution network having an input terminal which is a contact pad at the second surface and having a plurality of output terminals which are contact pads at the first surface; wherein the first semiconductor integrated circuit comprises a first semiconductor substrate which comprises a through hole, and the clock distribution network comprises a conductive feature going through the through hole; wherein the first semiconductor substrate further comprises one or more additional through holes; and the first semiconductor integrated circuit further comprises: one or more additional contact pads at the second surface at each of the additional through holes; an additional conductive feature in each of the additional through holes, the conductive feature providing at least a portion of a path for a signal and/or a power voltage and/or a ground voltage between the corresponding additional contact pad and a circuit element at the first surface.