Patent ID: 7759201

Claim:
A method of making a pillar shaped nonvolatile memory device array, comprising: forming a plurality of bottom electrodes over a substrate; forming at least one semiconductor device layer over the plurality of bottom electrodes; forming a plurality of spaced apart features over the at least one semiconductor device layer; providing alignment edge features adjacent to a device array boundary, wherein the alignment edge features have a larger size than the plurality of spaced apart features; forming sidewall spacers on the plurality of spaced apart features; forming a filler film over and between the plurality of spaced apart features; planarizing the filler film to expose upper portions of the plurality of spaced apart features and upper portions of the sidewall spacers to leave a plurality of filler features located between the sidewall spacers; forming a photoresist layer over the plurality of filler features and over the plurality of spaced apart features; exposing the photoresist layer using the alignment edge features during alignment; patterning the exposed photoresist layer to form a photoresist pattern covering a device array area; etching the filler film in areas outside of the device array boundary that are not covered by the photoresist pattern to remove the filler film from areas outside of the device array boundary; selectively removing the sidewall spacers to leave the plurality of spaced apart features and the plurality of filler features spaced apart from each other; etching the at least one semiconductor device layer using the plurality of spaced apart features and the plurality of filler features as a mask to form a plurality of pillar shaped diode containing nonvolatile memory cells; and forming a plurality of upper electrodes contacting the plurality of nonvolatile memory cells.