Patent ID: 8710592

Claim:
An SRAM cell comprising: a first PMOS active region and a second PMOS active region defined in a semiconductor substrate; a first NMOS active region and a second NMOS active region defined in the semiconductor substrate, the first and second NMOS active regions being disposed between the first PMOS active region and the second PMOS active region; a first PMOS pass gate crossing Over the first PMOS active region; a first NMOS pass gate crossing over the first NMOS active region; a first shared gate crossing over the first PMOS active region and the first NMOS active region; a second PMOS pass gate crossing over the second PMOS active region; a second NMOS pass gate crossing over the second NMOS active region; and a second shared gate crossing over the second PMOS active region and the second NMOS active region.