Patent ID: 8086979

Claim:
A method for designing a PMOS device to have a gate, a body, an extended drain region formed in the body, a drain junction breakdown point within at least one of the body and the extended drain region, and a maximum impact ionization point, wherein the extended drain region includes a drain, a deep drain implant, and a lightly doped drain implant between the deep drain implant and the gate, at least a portion of the lightly doped drain implant is located between the drain and the gate, at least a portion of the deep drain implant is located below the drain, and the maximum impact ionization point is located below the lightly doped drain implant within at least one of the body and the extended drain region, said method including the steps of: (a) determining a location of the gate, and a location of the maximum impact ionization point relative to the location of the gate, such that said location of the gate and said location of the maximum impact ionization point cause the device to exhibit no drain breakdown voltage walk-in in excess of a predetermined value; and (b) manufacturing an integrated circuit including the PMOS device.