Patent ID: 7936580

Claim:
A memory array, comprising: a plurality of bit lines; a plurality of source lines intersecting with the plurality of bit lines and forming a cross-point array; a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising: a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell; a first diode electrically between the magnetic tunnel junction data cell and the source line; and a second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directions; wherein the cross-point array is configured to be precharged to a specified precharge voltage level in a range from 40 to 60% of a write voltage, the precharge voltage being less than a threshold voltage of the first diode and second diode.