Patent ID: 8129755

Claim:
An integrated circuit, comprising: a substrate region; and a gate electrode level region formed above the substrate region, the gate electrode level region including at least four linear-shaped conductive structures formed to extend lengthwise in a first direction, each of the at least four linear-shaped conductive structures having a substantially equal length as measured in the first direction, each of the at least four linear-shaped conductive structures having a lengthwise centerline, the at least four linear-shaped conductive structures positioned in a spaced apart and side-by-side manner according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the at least four linear-shaped conductive structures is an integer multiple of the equal pitch, wherein one of the at least four linear-shaped conductive structures is a first linear-shaped conductive structure having a gate portion that forms a gate electrode of a first transistor of a first transistor type, wherein the gate portion of the first linear-shaped conductive structure that forms the gate electrode of the first transistor of the first transistor type is the only gate portion of the first linear-shaped conductive structure, wherein the first linear-shaped conductive structure includes a first non-gate portion that extends in the first direction away from a first end of the gate portion, wherein the first linear-shaped conductive structure includes a second non-gate portion that extends in the first direction away from a second end of the gate portion, and wherein a length of the first non-gate portion as measured in the first direction is at least twice a length of the second non-gate portion as measured in the first direction.