Patent ID: 8298928

Claim:
A method for manufacturing a semiconductor device comprising: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over said substrate, said first sacrificial layer being patterned to form in said first area a functioning wiring connected to an element arranged over said substrate; forming a second sacrificial layer in a second area over said substrate, said second sacrificial layer being patterned to form in said second area a dummy wiring; forming a third sacrificial layer at a side wall of said first sacrificial layer and forming a fourth sacrificial layer at a side wall of said second sacrificial layer after forming said first sacrificial layer and said second sacrificial layer, said third sacrificial layer and said fourth sacrificial layer being separated, the shape of said fourth sacrificial layer containing a closed-end loop; forming a concavity by etching said insulation layer to be processed using said third sacrificial layer and said fourth sacrificial layer as a mask; and filling a conductive material in said concavity; wherein a pattern density of said conductive material filled in said concavity in said first area is substantially equal to a pattern density of said conductive material filled in said concavity in said second area; wherein a spatial frequency calculated by a discrete Fourier transformation on groups of pixels of an image of the shape of said third sacrificial layer is substantially equal to a spatial frequency calculated by a discrete Fourier transformation on groups of pixels of an image of the shape of said fourth sacrificial layer.