Patent ID: 7647571

Claim:
A method of identifying state nodes in a circuit, the circuit having a plurality of circuit devices and a plurality of nodes that are separated by the plurality of circuit devices such that no two nodes are directly connected to each other, the plurality of nodes including a plurality of input nodes and a plurality of non-input nodes, the plurality of non-input nodes including internal nodes and output nodes, the plurality of input nodes to receive a plurality of valid logic state combinations, the method comprising: determining a plurality of logic values for the plurality of non-input nodes of the circuit that result from applying the plurality of valid logic state combinations to the plurality of input nodes of the circuit such that a logic value is determined for each valid logic state combination for each non-input node of the circuit; and forming a number of node sets, each node set including one or more non-input nodes, for each valid logic state combination, each non-input node in a multiple member node set having only high and low logic values that correspond with a valid logic state combination, or no high and low logic values that correspond with the valid logic state combination.