Patent ID: 7203810

Claim:
A synchronous semiconductor memory device compnsing: a first memory bank including a first memory cell, the first memory bank being configured to execute a first data operation on the first memory cell; a second memory bank including a second memory cell, the second memory bank being configured to execute a second data operation on the second memory cell while the first data operation is being executed; a synchronization device for generating synchronization signals in response to a clock signal and one or more control signals, the synchronization signals synchronizing the execution of the first data operation with respect to the execution of the second data operation; a first data path for transmitting data between the first memory cell and an input/output device during the first data operation; and a second data path for transmitting data between the second memory cell and the input/output device during the second data operation, wherein each of the first and second memory banks have access to a common input/output line, and wherein the input/output line connects each of the first and second data paths to both the first and second memory banks; and wherein the synchronization signals include, a first data path activation signal for activating the first data path during the first data operation and a second data path activation signal for activating the second data path during the second data operation, and wherein the synchronization device includes a data path activation device for generating the first and second data path activation signals based on the clock signal and the control signals, and wherein the synchronization signals include first selection signals, the first selection signals including, a first memory bank selection signal for selecting the first memory bank from a plurality of memory banks and first row and column identifiers for identifying a row and column address in the first memory bank corresponding to the first memory cell, and wherein the synchronization signals include second selection signals, the second selection signals including, a second memory bank selection signal for selecting the second memory bank from a plurality of memory banks; and second row and column identifiers for identifying a row and column address in the second memory bank corresponding to the second memory cell, and wherein the first selection signals activate the first memory bank to execute the first data operation on the first memory cell, and the second selection signals activate the second memory bank to execute the second data operation on the second memory cell, and wherein the synchronization device includes an address register for generating the first selection signals in synchronization with the second selection signals based on the clock signal and the control signals.