Patent ID: 7547964

Claim:
A semiconductor device package comprising: a first power semiconductor device having a first power electrode and a second power electrode on one surface thereof, and a second power semiconductor device having a gate electrode and a source electrode on one surface thereof and a drain electrode on another surface thereof, wherein electrodes of said first and second power semiconductor devices are interconnected to form a circuit, and wherein said first power semiconductor device is a III-nitride based semiconductor device; a lead frame including a die pad, a first lead, a second lead, and a third lead; an electrically insulating body disposed on said die pad and having said first power semiconductor device disposed thereon; and a protective housing enclosing at least said first and second power semiconductor devices, and at least a portion of said die pad, wherein said gate electrode is electrically connected to said first lead, said source electrode is electrically connected to said second lead, said drain electrode is electrically connected to said first power electrode, and said second power electrode is electrically connected to said third lead.