Patent ID: 7884638

Claim:
An on-chip termination (OCT) calibration circuit comprising: a first transistor coupled between a first terminal and a supply voltage; a second transistor coupled between the first terminal and a low voltage; and a feedback loop circuit that is configured to compare a signal from the first terminal to first, second, and third reference signals to generate a first calibration code that controls a conductive state of the first transistor and a second calibration code that controls a conductive state of the second transistor, wherein the feedback loop circuit selects the first calibration code and the second calibration code to cause a voltage at the first terminal to be within one of a first range defined by the first and the second reference signals and a second range defined by the second and the third reference signals, and wherein the OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.