Patent ID: 7276776

Claim:
A semiconductor device, comprising: a semiconductor substrate including a main surface; a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to one of said plurality of first interconnections located at an edge of said predetermined region, extending in said predetermined direction, and having a fixed potential; and an insulating layer formed on said main surface and filling in between each of said plurality of first interconnections and between said first interconnection and said second interconnection adjacent to each other, said plurality of first interconnections being located at substantially equal intervals in a first plane parallel to said main surface, and said plurality of first interconnections and said plurality of second interconnections being located to align in a direction substantially perpendicular to said predetermined direction, wherein a capacitance is formed by said plurality of first interconnections and said insulating layer formed between each of said plurality of first interconnections.