Patent ID: 8335098

Claim:
A memory device comprising a plurality of memory sets each including a mark bit storage area for storing a mark bit and a data bit storage area, the memory device comprising a one time programmable (OTP) memory including at least one OTP memory block and at least one pseudo-multi time programmable (MTP) memory block, the at least one OTP memory block including a number of memory sets of the plurality of memory sets that operate as an OTP memory, the at least one pseudo-MTP memory block including the plurality of memory sets that remain after the memory sets of the at least one OTP memory block are excluded and operates as a pseudo-MTP memory, the memory device further comprising: an address search unit that refers to the mark bit to obtain an identified address of one of the plurality of memory sets where data is to be read and written; a reading unit that accesses the data bit storage area of the memory set indicated by the identified address to read stored data in the data bit storage area of the indicated memory set; a writing unit that uses the identified address to identify a memory set in the at least one pseudo-MTP memory block where new data is to be written, and writes the new data in the data bit storage area of the identified memory set; and a mark bit writing unit that writes the mark bit in the mark bit storage area of the memory set indicated by the identified address, wherein the mark bit and new data are written in advance in the mark bit storage area of the at least one OTP memory block before the at least one pseudo-MTP memory block is accessed.