Patent ID: 7033892

Claim:
A method of forming trench MOSFET device, the method comprising the steps of: providing an n-type heavily doped silicon carbide substrate having an n-type drift layer formed thereon; forming a first photoresist pattern having openings to define p-base regions on said drift layer; performing a first ion implant to form said p-base regions in said drift layer using said first photoresist pattern as a mask; removing said first photoresist pattern; performing a second ion implant to form an n-type heavily doped layer in said drift layer and extended to a surface of said drift layer; forming a trench in said drift layer in between said p-base regions through a lithography and an etching process, wherein said trench separated from said p-base regions by an accumulation channel width; forming a gate oxide layer over all surfaces of said drift layer; forming a polycrystalline silicon layer on said gate oxide layer, and refilling said trench; patterning said polycrystalline silicon layer to form a trench polygate; forming a second photoresist pattern on said drift layer whose openings define p-type heavily doped regions; performing a third ion implant to form p-type heavily doped regions in said n-type heavily doped layer and extended to said surface of said drift layer using said second photoresist pattern as a mask, wherein each p-type heavily doped region is doped with around double p-type impurity concentration than n-type impurity concentration in said n-type heavily doped layer so that each p-type heavily doped region is thus abutting remnant n-type heavily doped layer and over one of said p-base regions; removing said second photoresist pattern; forming an insulating layer over all exposed surface of said drift layer; patterning said insulating layer to define a capping layer over said trench polygate and a portion of n-type heavily doped layer and to define a poly-gate contact; performing a thermal anneal to activate all ions doped; forming a first metal layer atop front surface of said silicon carbide substrate; patterning said first metal layer to form a source contact metal layer on said insulating layer, p-type heavily doped regions and said and n-type heavily doped layer and form a trench polygate contact metal layer on said poly-gate contact; removing all layers formed on a rear surface of said silicon carbide substrate until said silicon carbide substrate is exposed; and forming a second metal layer on said rear surface to be as a drain electrode.