Patent ID: 7598155

Claim:
A method of manufacturing an overlay mark, applicable in a non-volatile memory process, comprising: forming two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures in a substrate, wherein the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle; sequentially forming a first dielectric layer and a conductive layer on the substrate; performing a first planarization process to remove a portion of the conductive layer, till the first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are exposed; forming a second dielectric layer on the substrate; and forming a rectangle pattern on the second dielectric layer, wherein sides of the rectangle pattern are located above the second X-direction isolation structures and the second Y-direction isolation structures, respectively.