Patent ID: 7500138

Claim:
A processor suitable for use in a data processing system, comprising: first and second functional units for processing instructions executable by the processor, each functional unit being enabled to generate a direct event signal and an indirect event signal, wherein each event signal indicates the occurrence of a corresponding instruction processing event in the processor; a bus shared by the first and second functional units wherein a set of first indirect event signals is connected to the shared bus when the first functional unit is a master of the shared bus and a set of second indirect event signals is connected to the shared bus when the second functional unit is a master of the shared bus; and a performance monitor unit (PMU) including a plurality of performance monitor counters suitable for counting instruction processing events, wherein the PMU is connected to the shared bus and to the set of direct event signals such that, during any selected cycle, each direct event signal may be monitored by at least one of the counters and further wherein at least a portion of the indirect event signals associated with the functional unit that is master of the shared bus may be monitored by at least one of the counters; wherein the performance monitor unit includes a monitor mode control register (MMCR) associated with each of the counters, wherein the MMCR provides a signal from the direct event signals and shared bus signals for monitoring, the monitoring by comparison of at least one bit of a byte of the signal to at least one mask bit and at least one match bit and based on the comparison, the signal provides a set of event signals for counting by one of the associated counters.