Patent ID: 8314496

Claim:
A semiconductor device, comprising: a top level interconnect metal layer (Mtop) pattern; a below-to-top level interconnect metal layer (Mtop−1) pattern directly below the top level interconnect metal layer pattern; and a single first via plug pattern vertically disposed between the top level interconnect metal layer pattern and the below-to-top level interconnect metal layer pattern, electrically connected to the top level interconnect metal layer pattern and the below-to-top level interconnect metal layer pattern, wherein the top level interconnect metal layer pattern, the below-to-top level interconnect metal layer pattern and the single first via plug pattern have profiles parallel with each other from a top view, and wherein a first horizontal distance between an outer terminal of the single first via plug pattern and an outer terminal of the top level interconnect metal layer pattern or the below-to-top level interconnect metal layer pattern is the same to a second horizontal distance between an inner terminal of the single first via plug pattern and an inner terminal of the top level interconnect metal layer pattern or the below-to-top level interconnect metal layer pattern.