Patent ID: 7958463

Claim:
A method of manufacturing an integrated circuit comprising: designing layout information including patterns of cells, wires, and vias to be placed on a semiconductor substrate implemented in a graphic image space of a chip area; verifying the layout information in the graphic image space by placing a plurality of marks on each of contours of the patterns, allocating selectively a plurality of discrete areas in a same level with the patterns on the marks taking account of an influence of the optical proximity effect of the patterns, merging adjacent discrete areas overlapping each other into a single polygon so as to define a plurality of isolated groups by the polygon, sorting the marks into the isolated groups so that the adjacent marks are merged in a same group, determining a candidate hot spot by counting a total number of the marks included in each of the isolated groups, extracting a group with the total number of the marks more than a predetermined value, and modifying a corresponding pattern in the candidate hot spot; modifying the layout information by executing a lithography rule check; producing a plurality of masks based on modified layout information; forming an insulating film on the semiconductor substrate; selectively etching a part of the insulating film by using one of the masks; and forming corresponding actual vias and corresponding actual wires, using the modified layout information, connected to the actual vias in the insulating film.