Patent ID: 8374044

Claim:
A semiconductor device comprising: a first global bit line; a dummy global bit line; a plurality of first memory blocks that are arranged in a first direction, each of the plurality of first memory blocks including a first hierarchy switch that is connected to the first global bit line, and a first local bit line that is connected to the first global bit line via the first hierarchy switch; a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch; a first sense amplifier that is arranged between the first memory blocks and the dummy memory block, and amplifies a potential difference between the first global bit line and the dummy global bit line; a control circuit that controls the first hierarchy switches and the dummy hierarchy switch such that any one of a plurality of first hierarchy switches and the dummy hierarchy switch are brought into an on state, wherein a total number of memory cells connected to a plurality of the first local bit lines corresponding to the first sense amplifier is greater than a total number of dummy memory cells connected to the dummy local bit line corresponding to the first sense amplifier, wherein a length of the first local bit line is substantially equal to a length of the first dummy local bit line, wherein a length of the first global bit line is longer than a length of the dummy global bit line, a second global bit line and a third global bit line; a plurality of second memory blocks that are arranged in the first direction, each of the second memory blocks including a second hierarchy switch that is connected to the second global bit line, and a second local bit line that is connected to the second global bit line via the second hierarchy switch; and a second sense amplifier that is arranged between the first memory blocks and the second memory blocks and amplifies a potential difference between the second and third global bit lines, wherein the first memory blocks are arranged between the first and second sense amplifiers, wherein each of the first memory blocks further includes a third hierarchy switch that is connected to the third global bit line, and a third local bit line that is connected to the third global bit line via the third hierarchy switch, and wherein the control circuit activates any one of a plurality of the first hierarchy switches, any one of a plurality of the second hierarchy switches, any one of a plurality of the third hierarchy switches, and the dummy hierarchy switch.