Patent ID: 7598958

Claim:
A multi-chip graphics system for augmenting performance of a graphics processor using a partial defective graphics processor, comprising: a first graphics processing unit (GPU) chip configured as a master GPU chip, the master GPU chip having a first set of graphics stages including a first command module stage to receive a graphics command string from a central processing unit and in response generate a graphics output, said master GPU chip having a first version of a processing stage having a first group of parallel processing units, said master GPU chip including a first interlink interface; a second graphics processing unit GPU chip having a second set of graphics stages identical to said first set of graphics stages except that at least one stage has a defect that results in said second GPU chip not satisfying a performance criteria for performing a full sequence of steps for rendering an image, the second GPU chip configured as a slave GPU chip, the slave GPU chip having a second command module that is inoperative during normal use of the multi-chip graphics system, said slave GPU chip including an operative second version of said processing stage having a second group of parallel processing units and a second interlink interface, said slave GPU chip receiving graphics data from said master GPU chip for parallel processing in said second group of parallel processing units and processing said graphics data in parallel on behalf of said master GPU chip to improve performance of said master GPU chip; and said master GPU chip and said slave GPU chip packaged with a high bandwidth interlink for exchanging data and commands between said master GPU chip and said slave GPU chip, the high bandwidth interlink having a sufficient bandwidth such that said second version of said processing stage acts as an extension of said first version of said processing stage; the master GPU chip commanding the slave GPU chip via the high bandwidth link and utilizing said second version of said processing stage to increase an effective number of parallel processing units of said first version of said processing stage acting in parallel to process data; wherein the slave GPU chip extends the capability of only a subset of stages in said master GPU chip.