Patent ID: 8039363

Claim:
A method of processing chips connected in a two-dimensional array, comprising the steps of: slicing the array of chips along first slicing paths which extend in a first direction to thereby subdivide the array into a plurality of rows of connected chips, each said row including a plurality of connected chips; attaching a lead frame to contacts on the plural chips in the plural rows of connected chips; said lead frame comprising a plurality of leads mechanically connected to one another prior to the attaching step; each lead having a first terminal conductively attached to a contact on one of the chips and a second terminal extending beyond a boundary of the chip to which said first terminal end is attached; and slicing the rows of connected chips and the attached lead frame along second slicing paths which extend in a second direction perpendicular to the first direction, thereby separating the rows into individual chips and separating the individual leads connected to the contacts on the individual chips from the lead frame while leaving at least some of the leads connected to each chip extending across a boundary of that chip.