Patent ID: 8772869

Claim:
A power semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a plurality of third semiconductor layers of a second conductivity type formed in the second semiconductor layer with predetermined spaces therebetween; a plurality of fourth semiconductor layers of the second conductivity type provided on some of immediately upper regions of the third semiconductor layers and connected to the some of third semiconductor layers; a fifth semiconductor layer of the first conductivity type selectively formed on an upper surface of each of the fourth semiconductor layers; a control electrode provided between immediately upper regions of contiguous of the fourth semiconductor layers; a gate insulating film provided between an upper surface of the second semiconductor layer and the control electrode, the gate insulating film including first parts and a second part, the first parts being disposed in the immediately upper regions of contiguous of the fourth semiconductor layers, the second part being disposed in an immediate upper region of a central portion of the gate insulating film between the fourth semiconductor layers, the second part being located between the first parts, a second thickness of the second part being thicker than a first thickness of each of the first parts; a first main electrode provided on a lower surface of the first semiconductor layer and electrically connected to the first semiconductor layer; and a second main electrode provided on the fourth semiconductor layers and the fifth semiconductor layer and connected to the fourth semiconductor layers and the fifth semiconductor layer, and a first sheet impurity concentration of the second semiconductor layer located in an immediately lower region of the second part of the gate insulating film being higher than a second sheet impurity concentration of one of the third semiconductor layers disposed in an immediately lower region of one of the first parts of the gate insulating film, a third sheet impurity concentration of a second of the third semiconductor layers disposed in a second immediately lower region of the second part of the gate insulating film being higher than the second sheet impurity concentration.