Patent ID: 7183812

Claim:
A comparator system that provides a latch signal in response to an input signal, comprising: a differential network of transistors for receiving said input signal; cross-coupled transistors that respond to said differential network; a control transistor connected across said cross-coupled transistors and having a control terminal; and a bias network configured to apply to said control terminal: a) in a system latch phase, a latch bias voltage that biases off said control transistor; and b) in a system acquire phase, an acquire bias voltage that is substantially the voltage across two transistors which are each biased into conduction; wherein said bias network includes: a capacitor having first and second plates; first and second transistors that provide first and second voltages and are each biased into conduction; and a switch network that, in a system latch phase, couples said first plate to receive said first voltage and, in a system acquire phase, couples said second plate to receive said second voltage and couples said first plate to said control terminal; said cross-coupled transistors thereby providing said latch signal in said latch phase.