Patent ID: 7060557

Claim:
A method for fabricating a capacitor on a semiconductor substrate, the method comprising: simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region, whereby the at least one via exposes a via area of the cap dielectric layer and the at least one upper capacitor plate opening exposes an upper capacitor plate opening area of the can dielectric layer; simultaneously heating the cap dielectric layer with a heat source and impinging the exposed via area and exposed upper capacitor plate opening area of the cap dielectric layer with an energy beam, whereby the cap dielectric layer is modified in the via area and the upper capacitor plate opening area such that the dielectric values of the via area and the upper capacitor plate opening area are higher than the dielectric value of the remaining portions of the dielectric layer; forming a trench above the via; and filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure.