Patent ID: 7689954

Claim:
A method for predicting the signal delay in a circuit having circuit paths formed by elements connected by interconnects wherein: (1) at least some of the circuit paths intersect; (2) all elements and interconnects each: (a) have an associated signal delay D, and (b) have at least one of: (i) an adjacent upstream element or interconnect from which a signal delay is propagated, and (ii) an adjacent downstream element or interconnect to which the signal delay D is propagated; (3) at least one set of correlated signal delays is present, wherein at least one of the signal delays D X therein is correlated with at least one of the other signal delays D Y therein such that cov(D X , D Y ) is nonzero, and (4) one or more sets of correlated signal delays arise from global variations, the method comprising the following steps at any path intersection wherein at least two circuit paths intersect, with a first circuit path having a signal delay D 1 and a second circuit path having a signal delay D 2 : a. modeling each signal delay D by a function dependent on ∑ i = 1 M ⁢ ∑ k = 1 M ⁢ Γ i , k ⁢ G i ⁢ G k wherein: M is the number of global variations in the circuit; G i and G k are each a global variation reflecting the uncertainty in the value of D, each such uncertainty being shared by the element and one or more other elements in the circuit; and Γ i,k is a global sensitivity coefficient reflecting the dependence of D on both of global variations G i and G k in the circuit; b. evaluating using a computer the gaussianity of the function MAX(D 1 , D 2 ); c. if the gaussianity does not meet a threshold standard, storing signal delays D 1 and D 2 in a signal delay tuple Mt; and d. propagating the signal delay tuple Mt to any downstream element or interconnect using the computer.