Patent ID: 7353327

Claim:
A circuit comprising: a port for coupling the circuit to a synchronous dynamic random access memory (SDRAM) and to a chip-select-interface device, the port comprising: a plurality of terminals for coupling to the SDRAM and to the chip-select-interface device; a first terminal for coupling to the SDRAM, the first terminal being for supplying an address signal to the SDRAM during memory transactions with the SDRAM, the first terminal being for supplying a refresh control signal to the SDRAM during a refresh operation of the SDRAM; and a second terminal for coupling to the chip-select-interface device, the second terminal being for supplying an address signal to the chip-select-interface device during the refresh operation, wherein the plurality of terminals and the second terminal together supply at least part of an address to the chip-select-interface device during the refresh operation, wherein during the refresh operation an address signal A[ 10 ] is supplied from the second terminal to the chip-select-interface device concurrently with the refresh control signal being supplied from the first terminal to the SDRAM.