Patent ID: 6964000

Claim:
A semiconductor integrated circuit device, comprising: a random access memory having a plurality of memory cells to which a plurality of addresses are allocated respectively; and a serial shift register, having a plurality of flip-flops serially arranged, for receiving a serial signal in each of the flip-flops of a first group, outputting the serial signal from each flip-flop of the first group, receiving the serial signal in each of the flip-flops of a second group from the corresponding flip-flop of the first group, outputting a parallel signal from each flip-flop of the first group to obtain a first string of the parallel signals, outputting a parallel signal from each flip-flop of the second group to obtain a second string of the parallel signals, producing a first address from the first string of the parallel signals output from the flip-flops of the first group, producing a second address from the second string of the parallel signals output from the flip-flops of the second group, transmitting the first string of the parallel signals expressing the first address to the random access memory so as to specify the memory cell of the first address, and transmitting the second string of the parallel signals expressing the second address to the random access memory so as to specify the memory cell of the second address.