Patent ID: 7473573

Claim:
A method of fabricating a thin film transistor array panel, the method comprising: forming a gate wire on an insulating substrate, the gate wire including a gate line, and a gate pad connected to one end of the gate line; forming a gate insulating layer made of an organic insulating material on the insulating substrate such that the gate insulating layer exposes the gate pad and a portion of the gate line close to the gate pad; forming a semiconductor pattern on the gate insulating layer; forming a data wire on the gate insulating layer, the data wire having a data line intersecting the gate line, a source electrode connected to the data line and contacting the semiconductor pattern, a drain electrode facing the source electrode and contacting the semiconductor pattern, and a data pad connected to one end of the data line; and forming a passivation layer made of an organic insulating material on the gate insulating layer such that the passivation layer exposes the data pad and a portion of the data line close to the data pad, wherein the formation of at least one of the gate insulating layer and the passivation layer is made by way of slit coating or printing.