Patent ID: 7814279

Claim:
A method for maintaining memory coherence between nodes, the method comprising: providing at least one first node wherein the first node comprises: one or more central processing units (CPUs); cache memory associated with each of the one or more CPUs; shared memory; and a nodal directory identifying locations that reside in shared memory in the first node that are cached at other nodes; providing at least one second node wherein the second node comprises: one or more accelerators; cache memory associated with each of the one or more accelerators; and a local store associated with each of the one or more accelerators; coherently transferring a block of the shared memory from the first node to one of the local store or cache memory of an accelerator in the second node; non coherently performing one or more operations on the transferred block in the local store; and coherently writing back the block of memory to the shared memory device after performing the one or more operations.