Patent ID: 8335224

Claim:
A data-buffering apparatus configured to buffer a block of data having a variable block length, said data-buffering apparatus comprising: a queuing logic unit; a first buffer coupled to said queuing logic unit and configured to buffer a first portion of said block of data; and a second buffer coupled to said queuing logic unit and said first buffer, wherein: said second buffer is deactivated to render said second buffer inoperative when said first buffer is capable of buffering all of said block of data; said second buffer is activated to render said second buffer operative and buffers a second portion of said block of data when said first buffer is incapable of buffering all of said block of data; said apparatus consumes a predetermined amount of power when said second buffer is rendered operative; and said apparatus consumes less than one-half of said predetermined amount of power when said second buffer is rendered inoperative.