Patent ID: 8487430

Claim:
An integrated circuit chip package, comprising: an integrated circuit chip; a package board, wherein the integrated circuit chip is mounted onto a top surface of the package board, wherein the package board is configured to send or receive a signal at a frequency greater than 10 GHz, the package board comprising: a first impedance section configured to provide a first characteristic impedance, the first impedance section disposed in an upper portion of the package board, the first impedance section comprising: a signal line; one or more ground planes disposed vertically adjacent to the signal line; one or more transition layers that are dielectric, the one or more transition layers disposed among the signal line and the one or more ground planes; first one or more signal vias coupled to the signal line; and a first set of first ground vias disposed parallel to the first one or more signal vias at a first radius from the first one or more signal vias, the first set of first ground vias being disposed in one or more transition layers in the upper portion of the package board, the first set of first ground vias coupled to at least one of the one or more ground planes; and a second impedance section configured to provide a second characteristic impedance, the second impedance section disposed in a lower portion of the package board, the second impedance section comprising: a ground interface plane; second one or more signal vias vertically coupled to the first one or more signal vias; one or more transition layers that are dielectric; a first set of second ground vias disposed parallel to the second one or more signal vias at a second radius from the second one or more signal vias, the first set of second ground vias being disposed in one or more transition layers in the lower portion of the package board; and a plurality of contact pads disposed on a bottom surface of the package board, the plurality of contact pads being conductive, the plurality of contact pads comprising a signal contact pad and ground contact pads; wherein the ground interface plane is disposed between the first set of first ground vias and the first set of second ground vias and is coupled to the first set of first ground vias and to the first set of second ground vias, wherein the second one or more signal vias are connected to the signal contact pad, wherein the first set of second ground vias is connected to the ground contact pads; and a plurality of conductive balls, each of the plurality of conductive balls directly connected to a respective one of the plurality of contact pads; wherein a position of the first set of second ground vias relative to a position of the second one or more signal vias and a position of the signal contact pad relative to a position of the ground interface plane are configured to provide the second characteristic impedance that substantially matches the first characteristic impedance at a signal frequency greater than 10 GHz.