Patent ID: 8036061

Claim:
An integrated circuit comprising: a plurality of memory requestors; a memory supercell including a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the memory supercell is organized into a plurality of bank groups, wherein each of the plurality of bank groups includes a subset of the plurality of memory banks and a corresponding dedicated access port; a switch coupled between the plurality of memory requestors and the memory supercell, wherein the switch is configured, responsive to a memory request by a given one of the plurality of memory requestors, to connect a data path between the given memory requestor and the dedicated access port of a particular one of the bank groups addressed by the memory request; wherein, during a write request initiated by a particular requestor to write data to a storage location of the first bank group, data from the particular requestor is driven on a path to the first access port without driving data on segments connected to the second access port.