Patent ID: 7585734

Claim:
A method of fabricating a multi-gate transistor comprising: forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed; forming a gate insulating layer on the channel regions; forming a conductive layer for a gate electrode on the gate insulating layer conformally to the active pattern; forming a sacrificial layer for planarizing an upper surface of the substrate by filling a step of the conformally formed conductive layer for the gate electrode; forming the gate electrode by patterning the conductive layer and the sacrificial layer; forming a first spacer on the gate electrode and the lateral surfaces of the sacrificial layer remaining on the gate electrode; and removing the remaining sacrificial layer after forming the gate electrode, wherein in the removing of the sacrificial layer, the first spacer formed on the lateral surface of the sacrificial layer is removed together with the sacrificial layer so that the first spacer remains on the lateral surfaces of the gate electrode.