Patent ID: 7038504

Claim:
A three-state output buffer circuit, comprising: an input circuit configured to receive an output enable signal and an input signal, and to output a first control signal and a second control signal; a voltage generating circuit configured to receive the first control signal from the input circuit and a power voltage from a terminal of a positive source power voltage, to generate a predetermined reference voltage based upon the first control signal and the power voltage, and to output the predetermined reference voltage; and an output circuit configured to receive the predetermined reference voltage from the voltage generating circuit and the second control signal from the input circuit, and to generate one of an output signal and a specific state to an output terminal of the output buffer circuit, wherein the output circuit comprises: a first transistor configured to receive through a gate thereof the predetermined reference voltage from the voltage generating circuit and through a substrate gate thereof the power voltage from the terminal of the positive source power voltage, and to flow electric current to the output terminal of the output buffer circuit; a second transistor connected between the first transistor and the output terminal of the output buffer circuit, and configured to receive a constant voltage through a gate thereof from a constant voltage source; a third transistor configured to receive through a gate thereof the second control signal from the input circuit, and to flow electric current from the output terminal of the output buffer circuit to a terminal of a negative source power voltage; a fourth transistor connected between the output terminal of the output buffer circuit and the third transistor, and configured to receive a predetermined voltage through a gate of the fourth transistor; and a fifth transistor configured to supply a voltage smaller than an insulated voltage of the second transistor, to the substrate gate of the second transistor.