Patent ID: 8618584

Claim:
A semiconductor device comprising: a semiconductor substrate of a first general conductivity type; an epitaxial layer of a second general conductivity type formed on the semiconductor substrate; a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer; a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer; a third buried layer of the first general conductivity type connected to a center region of the first buried layer and extending from top and bottom surface portions of the first buried layer into the epitaxial layer and the semiconductor substrate respectively; a first drawing layer and a second drawing layer of the first general conductivity type each extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer and the third buried layer respectively; a first diffusion layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer and connected to the second drawing layer so as to be surrounded by the second buried layer and the first drawing layer in plan view of the semiconductor substrate, the first buried layer covering a bottom portion of the first diffusion layer; a second diffusion layer of the second general conductivity type connected to and surrounding the first diffusion layer in the plan view; a cathode electrode connected to the first diffusion layer and the second diffusion layer; and an anode electrode connected to the first drawing layer, wherein the first buried layer and the second buried layer are configured to form a PN junction diode, the third buried layer, the epitaxial layer and the second buried layer are configured to form a parasitic bipolar transistor, and the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.