Patent ID: 8101445

Claim:
A method for manufacturing a thin film transistor array panel, comprising: forming a gate line and a first signal line to connect the gate line to a driving circuit on a substrate; forming a semiconductor on the gate line; forming a data line and a drain electrode on the semiconductor; forming a second signal line to connect the data line to the driving circuit; forming a passivation layer and a sacrificial layer on the data line, the drain electrode, the first signal line, and the second signal line; forming a photosensitive film pattern comprising a first portion and a second portion of different thicknesses on the sacrificial layer; etching the sacrificial layer and the passivation layer using the photosensitive film pattern as a mask to form a contact hole exposing the drain electrode; removing the exposed sacrificial layer after removing the first portion of the photosensitive film pattern, and forming an undercut under the second portion of the photosensitive film pattern; forming a transparent conductive layer on the second portion of the photosensitive film pattern, the exposed drain electrode, and the passivation layer; and removing the second portion of the photosensitive film pattern disposed under the transparent conductive layer thereby removing the transparent conductive layer disposed on the second portion of the photosensitive film pattern among the transparent conductive layer to form a pixel electrode and a dummy pattern.