Patent ID: 8390501

Claim:
A successive approximation register (SAR) analog-to-digital converter (ADC) with a window predictive function, comprising: a first capacitor digital-to-analog converter (DAC) coupled to receive a first input signal; a second capacitor DAC coupled to receive a second input signal; a first coarse comparator configured to compare an output of the first capacitor DAC with a window reference voltage; a second coarse comparator configured to compare an output of the second capacitor DAC with the window reference voltage; a fine comparator configured to compare the output of the first capacitor DAC with the output of the second capacitor DAC; and a SAR controller coupled to receive outputs of the first coarse comparator and the second coarse comparator to determine whether the outputs of the first capacitor DAC and the second capacitor DAC are within a predictive window determined by the window reference voltage, wherein the SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window; wherein the SAR controller decodes the outputs of the first coarse comparator, the second coarse comparator and the fine comparator to obtain, a converted output of the SAR ADC.