Patent ID: 7034352

Claim:
A vertical dynamic random access memory (DRAM) cell device fabricated within a trench region in a substrate, the trench region having first and second opposing substantially vertical edges extending from the device surface, the vertical DRAM cell comprising: (a) a storage capacitor formed within the trench region for storing electrical charge; (b) a transistor formed within the trench region above the storage capacitor; (c) a buried strap having a top surface formed proximate to the first vertical edge between the storage capacitor and the transistor, the buried strap electrically coupling the storage capacitor and the transistor; and (d) an isolation collar region having a bottom edge, said collar region formed proximate to the second vertical edge of the trench, and said bottom edge extending past said transistor, but no further than about 100 nm below said top surface of said buried strap.