Patent ID: 7482240

Claim:
A method for manufacturing a semiconductor device comprising the steps of: (a) sequentially forming a first oxide film, a nitride film, and a stacked structure of a first polysilicon layer pattern and a hard mask layer pattern on a cell region and a peripheral circuit region of a semiconductor substrate having a lower structure, wherein the stacked structure defines a capacitor region; (b) forming an USG (undoped silicate glass) layer on the entire surface, wherein a thickness of the USG layer on the peripheral circuit region is thicker than that on the cell region; (c) selectively removing the USG layer on the cell region to expose the nitride film in the capacitor region; (d) removing the hard mask layer pattern on the cell region, and selectively removing the exposed nitride film to expose the first oxide film in the capacitor region; (e) removing the USG layer on the peripheral circuit region, and then selectively removing the exposed first oxide film to expose the lower structure in the capacitor region; (f) removing the first polysilicon layer pattern and the remaining nitride film on the cell region; (g) removing the hard mask layer pattern on the peripheral circuit region, and then forming a lower electrode layer on the surface of the capacitor region; (h) sequentially forming a dielectric layer, a plate electrode layer and a planarized second oxide film on the entire surface of the resultant, wherein the second oxide film fills up the capacitor region; (i) polishing the second oxide film, the plate electrode layer and the dielectric layer to expose the first polysilicon layer pattern on the peripheral circuit region; (j) removing the second oxide film, and then forming a planarized second polysilicon layer filling up the capacitor region on an entire surface of a resultant semiconductor substrate; and (k) patterning the second polysilicon layer, the first polysilicon layer pattern and the nitride film on the peripheral circuit region adjacent to the cell region using a fuse forming mask to form a fuse pattern.