Patent ID: 6969884

Claim:
A semiconductor device comprising: a semiconductor substrate including first and second element-formation regions which are partitioned by an isolation trench; first and second lower gate insulating films formed on the first and second element-formation regions, respectively; first and second floating gates formed on the first and second lower gate insulating films, respectively, the first floating gates including a first side surface and the second floating gate including a second side surface which is opposed to the first side surface, each of the first and second floating gates including an upper surface; an isolation insulating film which is formed at least in the isolation trench and which includes a depression formed in an upper surface thereof and an uppermost portion located higher than a surface of the semiconductor substrate and lower than the upper surface of each of the first and second floating gates; an upper gate insulating film formed on the first and second floating gates and the isolation insulating film; and a control gate line formed on the upper gate insulating film, and including an opposed portion which is opposed to the first and second floating gates, and a portion located inside the depression so that each of the first and second side surfaces of the first and second floating gates is entirely opposed to the control gate line, the first side surface of the first floating gate entirely aligning with a side surface included in the first element-formation region and defined by the isolation trench, and the second side surface of the second floating gate entirely aligning with a side surface included in the second element-formation region and defined by the isolation trench.