Patent ID: 7394703

Claim:
A method of erasing a single gate MONOS memory device comprising: providing polysilicon control gates on a substrate having an oxide-nitride-oxide (ONO) layer underlying each of said control gates wherein portions of said substrate underlying said control gates define channels and wherein said nitride portion of said ONO layer underlying said control gates provides two bits memory storage overlying at both sides of said each of channels; providing memory diffusions within said substrate between each two of said control gates wherein every other of said memory diffusions are connected to an overlying bit line through a local wiring overlying said substrate to form said single gate MONOS device; and erasing said single gate MONOS memory device by injecting hot holes into said nitride portion of said ONO layer from both sides of said channels or by Fowler-Nordheim ejection to remove hot electrons from said nitride portion of said ONO layer.