Patent ID: 7779338

Claim:
A deinterleaver and decoder system comprising: a deinterleaver for deinterleaving data, the deinterleaver including a plurality of memory banks for storing deinterleaved data; and a plurality of Viterbi decoders for decoding the deinterleaved data, the Viterbi decoders each configured to access separate ones of the plurality of memory banks than others of the Viterbi decoders, such that the plurality of Viterbi decoders can read data from memory banks in parallel, wherein a number of decoding steps undertaken by each of the Viterbi decoders for decoding the deinterleaved data is equal to a deinterleaver data length in bits, and wherein each Viterbi decoder receives some data that common to a plurality of the memory banks, the common data allowing the Viterbi decoders to pre-synchronize and post-synchronize.