Patent ID: 8656259

Claim:
A data transmission system comprising a transmission circuit and a reception circuit, wherein said transmission circuit comprises: a judgment section that generates a 1-bit width inversion instruction signal indicating whether or not a number of bits at which data has changed at a same time, among inputted 64-bit width data, has exceeded a predetermined threshold; a transmission data output section that outputs the data, with a polarity of each bit inverted, if the inversion instruction signal indicates that the number of the changed bits has exceeded the threshold and, otherwise, outputs the data without inverting the polarity; an instruction signal output section that outputs the inversion instruction signal at a timing of the output from said transmission data output section; an error code giving section that gives a 7-bit width error correcting code to the data outputted by said transmission data output section and to the inversion instruction signal outputted by said instruction signal output section; and a transmission section that transmits the data outputted by said transmission data output section, the inversion instruction signal being outputted by said instruction signal output section and the error correcting code to said reception circuit, wherein said reception circuit comprises: an error code correction section that performs an error code correction for the data and inversion instruction signal transmitted from said transmission circuit using the error correcting code transmitted from said transmission circuit; and a received data output section that outputs the data for which the error code correction has been performed, with the polarity of each bit inverted, if the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold and, otherwise, outputs the data for which the error code correction has been performed, wherein said judgment section uses a value corresponding to half a width of the inputted data as the threshold, wherein said judgment section judges whether the data has changed by comparing, for said each bit, the inputted data with what is obtained by delaying the inputted data by one clock at said transmission data output section, wherein said judgment section compares, between the inputted data and the data outputted from transmission data output section, each pair of corresponding bits of an n-bit width data, where n is an integer, and wherein, if a total number of pairs of bits different from each other exceeds n/2 as a result of a comparison, said judgment section generates and outputs “1” as the inversion instruction signal, and if the total number of pairs of bits different from each other is equal to or below n/2 as a result of the comparison, said judgment section generates and outputs “0” as the inversion instruction signal.