Patent ID: 7327153

Claim:
An apparatus for testing of a device-under-test (DUT), comprising: a test module, operably connected to a test head in the test system, including: a field programmable gate array (FPGA) that performs test setup of the device-under-test (DUT) and other components in the test module; a clock device that distributes a common clock signal to the components operably connected to the test module; a first direct digital synthesizer (DDS) to synthesize analog test signals controlled by the FPGA prior to transmitting the analog test signals to the DUT; a second direct digital synthesizer (DDS) to generate a high resolution clock signal controlled by the FPGA in order to clock the ADC for digitizing the tested analog signals from the DUT; and an analog-to-digital converter (ADC) to convert analog test data from the DUT to digital test data prior to transmission of the converted analog test data to the FPGA; and a load board, which operably connects the test module to the test head, for programming the test module to transmit and receive analog test signals to and from the DUT.