Patent ID: 8813054

Claim:
A parallel-code optimization system to identify siloed program references in parallel code that are free of cross-thread interference and to transparently expose the siloed program references to a compiler, comprising: a processor; a siloed program reference identifier, executed by the processor, to identify the siloed program references for procedures in parallel code, wherein identifying the siloed program references includes determining a Procedural Concurrency Graph (PCG) from the procedures, wherein each node in the PCG represents one of the procedures and an edge connecting two nodes in the PCG represents a possibility of the two procedures executing in parallel, and for each procedure, determining a union of immediate interference sets for the procedure based on edges connected to the node representing the procedure; determining a set V of Ivalues for the procedure that includes all Ivalues immediately read or written by the procedure; and subtracting the union of immediate interference sets from V to determine any siloed references for the procedure, wherein the siloed program references are references in the parallel code to accesses of objects and are free of cross-thread interference; and an intermediate representation (IR) updater to modify a data-flow abstraction based on the identified siloed program references.