Patent ID: 7553710

Claim:
A method for manufacturing a thin film transistor array panel, comprising: forming at least one of a first metal layer, forming a plurality of first photoresist patterns on the first metal layer, etching the first metal layer with the first photoresist patterns as masks to form a gate line comprising a gate electrode, stripping the first photoresist patterns, forming a semiconductor layer on the gate line, forming at least one of a second metal layer on the semiconductor layer, forming a plurality of second photoresist patterns on the second metal layer, and etching the semiconductor layer and the second metal layer with the second photoresist patterns as masks to form a semiconductor, a data line crossing the gate line and comprising a source electrode, and a drain electrode separated from the source electrode, stripping the second photoresist patterns, and forming a pixel electrode coupled with the drain electrode, wherein at least one of stripping the first photoresist patterns and stripping the second photoresist patterns is performed by using a photoresist stripper comprising about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.