Patent ID: 7838983

Claim:
A semiconductor package connecting a first wiring portion located on one side of a substrate and a second wiring portion located on the other side of the substrate, the semiconductor package comprising: a post electrode and a side electrode connected to the first wiring portion, said post electrode comprising a side wall, said side wall of said post electrode being covered by a first insulating layer, said first insulating layer having a first insulating end surface, said side electrode being exposed on said first insulating layer end surface; and a second insulating layer formed on a substrate, on which the second wiring portion is formed, wherein an exposed end of said second wiring portion formed when completely singulated into individual semiconductor packages and said side electrode are wired by an ink jet system using nano metal particles, wherein a side wire connects said exposed end of said second wiring portion and said side electrode, said side wire comprising said nano metal particles, wherein said side electrode is made the same height as said post electrode connected to the first wiring portion at one side of the substrate in which an LSI formation surface and said first wiring portion are located, and is formed simultaneously with the post electrode, and moreover, is arranged so as to ride over both of a chip end and a scribe line so as to be exposed when cut into individual chips from a wafer, and when the chip is completely cut so as to be singulated into individual semiconductor packages, the side electrode which runs off to the scribe line is also simultaneously cut, so that the side electrode can be exposed and formed on the package end surface.