Patent ID: 8078829

Claim:
A system for implementing waveform processing in a software defined radio (SDR) comprising a scaleable array processor including a plurality of micro-engines interconnected by a two dimensional topology, each micro-engine including multiple FIFOs for interconnecting to each other in the two dimensional topology, one micro-engine communicating with another adjacent micro-engine by way of the respective FIFOs, and the micro-engines dedicated to predetermined algorithms; wherein each micro-engine includes an independent local memory and an independent instruction memory, both coupled to an independent microprocessor, and the independent microprocessor is configured to execute an independent algorithm on data present in a dedicated FIFO of the respective micro-engine, each micro-engine is event driven, wherein unless data is present in an input FIFO of the respective micro-engine, the respective micro-engine is in a sleep mode, and the sleep mode disables a clock signal controlling the independent microprocessor and stops the execution of the independent algorithm, if all the multiple FIFOs of a respective micro-engine are empty, and the clock signal is generated by a phase locked loop; and wherein each processing engine includes a plurality of registers for executing multiple independent instructions, the plurality of registers from each processing engine are coupled to a multiplexer network, and a debug port is coupled between the multiplexer network and a host processor, and the host processor is configured to query each of the plurality of registers and receive data stored in the queried register by way of the multiplexer network for debug examination.