Patent ID: 7239681

Claim:
A system for maintaining a stable synchronization state in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to N second clock cycles, where N/M≧1, comprising: a first circuit portion operable to generate a load signal indicative of a known acceptable state from which a cycle may be loaded; a second circuit portion in communication with said first circuit portion, said second circuit portion operating to generate a lock signal indicative of a tolerable tracked skew between said first clock signal and said second clock signal; and a third circuit portion, operating responsive to said load signal, said lock signal, and a zero skew point indicator, for generating a synchronization stable state signal indicative of locking between said first clock signal and said second clock signal, wherein said third circuit portion is operable to transmit said synchronization stable state signal to said first circuitry disposed in said first clock domain.