Patent ID: 8503214

Claim:
A semiconductor memory device comprising: a plurality of memory blocks provided in a matrix configuration; and a plurality of main bit lines provided in correspondence with the memory blocks, wherein each of the memory blocks includes: a plurality of memory cells provided in a matrix configuration; a plurality of sub bit lines provided on a column-by-column basis; a plurality of word lines provided with respect to each of the columns and the rows and common to the memory blocks, wherein each of the memory cells in the memory block is provided with an independent word line; and a switch circuit that couples a corresponding main bit line of the main bit lines to any of the sub bit lines, and wherein in the operation of reading a target cell as the target of read among the memory cells, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit, and a word line corresponding to the column and the row of the target cell is selected from among the word lines.