Patent ID: 6954391

Claim:
A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled to the control bus; an MRAM array coupled to the address decoder and control circuit, the MRAM array having a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line; and a read/write circuit coupled to the data bus and the MRAM array, the read/write circuit including sensing circuits coupled to the bit lines, each sensing circuit comprising: an integrator circuit having a first integrator input electrically coupled to a reference level, a second integrator input coupled to a respective bit line, and first and second integrator outputs at which first and second output signals are provided, respectively, the integrator circuit further having an amplifier circuit having pairs of differential input and output nodes, the integrator circuit periodically switching the electrical coupling of each of the differential input nodes to a respective integrator input and the electrical coupling of each of the differential output nodes to a respective integrator output; a comparator having first and second input nodes electrically coupled to the respective integrator output and further having an output node, the clocked comparator periodically comparing voltage levels of the first and second input nodes and generating an output signal having a logic state based therefrom; and a current source having first and second current output nodes coupled to the respective integrator output, the current source switching the coupling of each current output node to the integrator output based on the logic state of the output signal of the comparator.