Patent ID: 7907661

Claim:
A circuit for testing a phase interpolator, comprising: a first phase interpolator comprising a first input, a second input and an output, the first and second inputs of the first phase interpolator being coupled to delay buffers in a delay locked loop (DLL) delay line; a second phase interpolator comprising a first input, a second input and an output, the first and second inputs of the second phase interpolator being coupled to the delay buffers in the DLL delay line; and a phase detector comprising a first input coupled to receive the output from the first phase interpolator and a second input coupled to receive the output from the second phase interpolator, the phase detector further comprising a fault-detection output that indicates when an output signal of the first phase interpolator crosses in time with an output signal of the second phase interpolator; wherein the first and second inputs of the first phase interpolator and the first and second inputs of the second phase interpolator are coupled to the DLL delay line; wherein the first phase interpolator comprises a predetermined delay offset with respect to a delay offset of the second phase interpolator, and the second phase interpolator comprises a predetermined state offset with respect to a state of the first phase interpolator.