Patent ID: 7117344

Claim:
A processor execution pipeline, comprising: a first instruction decoding unit that determines at least a kind of instruction in a current processing stage, decodes a first instruction into a first control signal, and decodes all other instructions with the exception of the first instruction into a second control signal as a through instruction upon determining at least the kind of instruction; a first processing unit provided in the current processing stage and connected to the first instruction decoding unit, the first processing unit being configured to perform a first operation on a first data when receiving the first control signal, and to pass through the first data when receiving the second control signal; a latch circuit provided between the current processing stage and a next processing stage, the latch circuit holding one of a result of the first operation and the first data passing through the first processing unit as a second data; a second instruction decoding unit that determines at least a kind of instruction in a next processing stage, decodes a second instruction into a third control signal, and decodes all other instructions with the exception of the second instruction into a fourth control signal upon determining at least the kind of instruction; a second processing unit provided in the next processing stage and connected to the second instruction decoding unit, the second processing unit being configured to perform a second operation on the second data when receiving the third control signal; and a multiplexer provided in the next processing stage for selecting an output of the second processing unit or the second data held in the latch circuit based on an output of the second instruction decoding unit.