Patent ID: 8404542

Claim:
A method of fabricating a semiconductor device, comprising: forming a plurality of device isolation patterns in a predetermined region of a semiconductor substrate to define an auxiliary active pattern, the auxiliary active pattern including a plurality of channel regions, a plurality of connection regions, each connection regions being disposed between a respective pair the channel regions, and a plurality of gate regions, wherein respective gates regions are disposed on at least two sides of each of the channel regions; forming an active pattern comprising the plurality of channel regions and the plurality of connection regions by recessing the plurality of gate regions of the auxiliary active pattern such that top surfaces of the plurality of gate regions are lower than the plurality of channel regions; forming a gate insulating layer covering sidewalls of the active pattern; forming a gate pattern on the at least two sides of each channel region, the gate pattern filling a plurality of recessed gate regions in which the gate insulating layer is formed; and forming a plurality of source/drain electrodes, each source/drain electrode formed in a respective connection region of the active pattern.