Patent ID: 8208593

Claim:
A system, comprising: clock-receiving circuitry to receive a global clock signal; phase-adjusting circuitry to adjust a phase of a first clock signal; and data-receiving circuitry to operate in one of at least a partial-rate mode and a full-rate mode; wherein in the partial-rate mode, a data bit is transmitted in at least two intervals, wherein a respective interval corresponds to a transmission time of one data bit in the full-rate mode; and the data-receiving circuitry receives the data bit based on the global clock signal; and wherein in the full-rate mode, a data bit occupies one interval; and the data-receiving circuitry receives the data bit based on a phase-adjusted local clock signal of which the frequency is substantially similar to that of the global clock signal and of which the phase is adjusted with respect to the data bits by the phase-adjusting circuitry.