Patent ID: 8166278

Claim:
An apparatus comprising: a first memory device configured to store an increment array, the increment array comprising one or more bits per array element; a second memory device configured to store at least 2 N data items, where N is a positive integer; an address shift register coupled to receive an increment from the first memory device and coupled to provide an address to the second memory device, wherein the increment is coupled to enable insertion of the increment into one or more lowest-order positions of the address shift register; and a comparison device coupled to the second memory device to compare at least a portion of an output data item from the second memory device corresponding to the address provided by the address shift register with at least a portion of a data item to be located in the second memory device to generate a comparison result, wherein if the comparison result indicates a difference between the output data item and the data item to be located, the address shift register is shifted with the increment inserted into the one or more lowest-order positions of the address shift register.