Patent ID: 8143129

Claim:
A method of fabricating a semiconductor structure, comprising: forming a nonvolatile charge trap memory device over a first portion of a substrate, the nonvolatile charge trap memory device further comprising a charge trapping dielectric stack consisting of dielectric material layers that include a blocking layer, a charge trapping layer, and a tunneling layer, wherein the tunneling layer is in contact with the first portion of the substrate; forming an NMOS gate stack adjacent to an NMOS sidewall spacer over a second portion of the substrate; implanting an NMOS source and drain region adjacent to the NMOS spacer prior to forming a liner; forming a PMOS gate stack adjacent to a PMOS sidewall spacer over a third portion of the substrate prior to forming the liner; forming the liner over the first portion of the substrate; implanting a PMOS source and drain subsequent to forming the liner; and forming a silicide adjacent to the NMOS sidewall spacer while the liner protects the nonvolatile charge trap memory device from silicide formation.