Patent ID: 8483345

Claim:
A receiving circuit which receives serial data, comprising: a voltage controlled oscillator which generates a sampling clock signal having a frequency based on an input control voltage; a first frequency divider which divides the frequency of the sampling clock signal at a division rate M, the division rate M being a real number; a second frequency divider which divides a frequency of a clock signal based on the received serial data at a division rate N, the serial data being generated such that level shift is produced at a rate of 2×q times within p bits, p and q being real numbers, and the division rate N being a real number represented by M×q/p; a frequency comparator which generates a phase/frequency difference signal based on a phase difference between an output signal of the first frequency divider and an output signal of the second frequency divider; and a control voltage generating circuit which generates the control voltage to control a frequency of the voltage controlled oscillator based on the phase/frequency difference signal.