Patent ID: 8767801

Claim:
An integrated circuit comprising: transmitter circuitry for producing a serial data output signal in which successive output data bits occur in synchronism with output clock signal pulses; clock and data recovery (“CDR”) circuitry for receiving a serial data input signal and recovering from the serial data input signal successive data bits based at least in part on clock information included in the serial data input signal as transitions between successive data bits in the serial data input signal; loop-back circuitry for controllably applying the serial data output signal to the CDR circuitry as the serial data input signal; and circuitry for controllably modulating time, based on an externally-supplied control signal, between occurrence of successive ones of the output clock signal pulses wherein: the CDR circuitry tracks modulation of the clock information in the serial data input signal up to a maximum trackable modulation frequency, and wherein the circuitry for controllably modulating time modulates the time between occurrence of successive ones of the output clock signal pulses at a frequency greater than the maximum trackable modulation frequency.