Patent ID: 7457172

Claim:
A parallel-to-serial converter, comprising: a first set of latches having a set of M parallel input terminals to receive and store M data bits, the first set of latches further including a serial output terminal coupled to a respective data output terminal, a serial clock terminal receiving a clock signal, a control terminal receiving a first shift control signal allowing the data bits to be shifted out of the first set of latches responsive to the clock signal, and a status output terminal generating a first status signal indicating that all of the data bits stored in the first set of latches have been shifted out of the first set of latches responsive to the clock signal; and a first flip-flop set responsive to an initiate signal and reset responsive to the first status signal, the first flip-flop having an output terminal coupled to the control terminal to apply the first shift control signal to the control terminal to allow the data bits to be shifted out of the first set of latches when the first flip-flop is set.