Patent ID: 7600061

Claim:
A data transfer control device that controls data transfer, the data transfer control device comprising: a controller that analyzes a packet received through a serial bus; an interface circuit that generates interface signals and outputs the interface signals to an interface bus, the interface signals including a vertical synchronization signal, a horizontal synchronization signal and a data signal; and a reset signal output circuit that outputs a reset signal of the interface circuit to the interface circuit; the interface circuit including: a horizontal counter that counts a horizontal synchronization cycle; a pixel counter that counts a pixel clock cycle; and a timing generator that outputs the vertical synchronization signal, the horizontal synchronization signal and the data signal based on a first count value from the horizontal counter and a second count value from the pixel counter, the controller analyzing a packet received through the serial bus to determine whether or not the received packet includes synchronization signal generation direction information that directs the interface circuit to generate the vertical synchronization signal and the horizontal synchronization signal, the reset signal output circuit outputting the reset signal to the interface circuit when the controller has determined that the received packet includes the synchronization signal generation direction information that directs the interface circuit to generate the vertical synchronization signal, and the horizontal counter and the pixel counter being reset by the reset signals in a vertical synchronization cycle to prevent occurrence of a malfunction due to noise imposed on the serial bus.