Patent ID: 7092289

Claim:
A flash memory, comprising: a flash memory array, including: (a) a plurality of array planes that constitute all storage corresponding to a logical address space of the Flash memory, each array plane further including: a plurality of blocks of memory cells, wherein the blocks store parameters, code, and data, and all the blocks in the array planes have a uniform size selected for parameter storage, wherein the blocks include: memory blocks having respective physical addresses that correspond to logical addresses of the Flash memory; and spare memory blocks having respective physical addresses that do not correspond to the logical addresses of the Flash memory; and (b) a redundancy information block of the array planes, storing therein defect addresses identifying memory blocks having defective memory elements within the array planes and substitute addresses for spare memory blocks replacing the memory blocks having the defective memory elements; a content addressable memory array coupled to the redundancy information block of the plurality of array planes to receive therefrom the defect addresses, and also being coupled to receive a logical signal from an external device for comparison with the defect addresses stored in the content addressable memory array; a memory array coupled to the redundancy information block of the plurality of array planes to receive therefrom the substitute addresses, and also having word lines coupled to respective match lines of the content addressable memory array, wherein in response to activation of one of the match lines, the memory array outputs a substitute address signal representing one of the substitute addresses stored in a row corresponding to the activated match line; and multiplexing circuitry connected to select between the logical address signal and the substitute address signal as a physical address signal, the multiplexing circuitry providing the physical address signal for selection of a memory cell being accessed.