Patent ID: 7902032

Claim:
A method of forming an integrated circuit (IC) including a plurality of compressively strained PMOS devices, comprising: providing a substrate wafer having a semiconductor surface including at least one PMOS region; forming a patterned gate stack comprising a gate electrode on a gate dielectric on a surface of said PMOS region; implanting said PMOS region on at least opposing sides of said gate stack using implant conditions comprising at least one compressive strain inducing specie selected from Ge, Sn and Pb, at a dose ≧1×10 15 cm −2 , and at an implantation temperature for said wafer during said implanting in a temperature range ≦273 K, wherein said implant conditions are sufficient to form an amorphous region; annealing said wafer using annealing conditions comprising a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at said peak temperature of ≦10 seconds, wherein said amorphous region recrystallizes by solid phase epitaxy (SPE), and completing fabrication of said PMOS device.