Patent ID: 7072219

Claim:
A method of operating an array of memory cells arranged in rows and columns, each or the memory cells comprising a body region, a contact region, a bottom dielectric, a charge trapping structure, and a top dielectric, wherein the contact region of memory cells in a particular column of the columns of memory cells is electrically coupled to a particular bit line of a plurality of bit lines arranged in columns, and the top dielectric of memory cells in a particular row of the rows is electrically coupled to a particular word line of a plurality of word lines arranged in rows, the method comprising: applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell, wherein the first bias arrangement applies a first voltage to the particular bit line coupled to the contact region of the selected memory cell and a second voltage to the particular word line electrically coupled to the top dielectric of the selected memory cell; and measuring current flowing between the particular bit line and the body region of the selected memory cell to determine the charge storage state of the charge trapping structure of the selected memory cell.