Patent ID: 8238148

Claim:
A semiconductor device comprising: a memory cell array comprising a plurality of memory cells configured to store a plurality of pre-fetch unit data; a plurality of registers configured to store the plurality of pre-fetch unit data; a write driver circuit configured to write the plurality of pre-fetch unit data to the memory cell array; and a sense amplifier circuit configured to sense and amplify the plurality of pre-fetch unit data and to store the amplified plurality of pre-fetch unit data in the plurality of registers, wherein during a write operation the write driver circuit writes the plurality of pre-fetch unit data, which is sequentially output from the plurality of registers, to the memory cell array, wherein during a read operation the sense amplifier circuit senses and amplifies the plurality of pre-fetch unit data, which is sequentially output from the memory cell array, and sequentially stores the amplified plurality of pre-fetch unit data in the plurality of registers, and wherein each of the plurality of registers are used in both the read and the write operations.