Patent ID: 7457787

Claim:
A neural network component, the component comprising: an addressable digital memory; a plurality of inputs configured to receive addresses for locations in said digital memory; at least one processing element for performing a plurality of different operations based on respectively corresponding values received from memory locations addressed via said inputs; at least one output providing the result of processing performed by said processing element; and said digital memory storing values representing processing element instructions at addresses respectively corresponding to the processing elements, said instructions corresponding to different operations; wherein the at least one processing element is configured to receive one of said stored values from the digital memory in response to a signal at an input, and is thereby instructed to execute a corresponding one of said plurality of operations by the value that is received from the digital memory; and wherein one of said plurality of different operations comprises generation of an output by the at least one processing element, and then resetting an activation level of the at least one processing element to a predetermined minimum level.