Patent ID: 8417911

Claim:
An address controller that receives a memory access request from a requesting function, the request including an address portion and a requester identification (RID) and provides a corrected memory request to a memory, wherein the correct memory request does not request access to a portion of the memory not assigned to a logical partition LPAR that owns the requesting function, the address controller comprising: a bit selector that receives a first portion of the RID and selects a bit from a vector that identifies whether the requesting function is an SR-IOV device or a standard PCIe device; a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector; and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.