Patent ID: 7867895

Claim:
A method of fabricating an interconnect structure comprising: providing an initial interconnect structure that includes a lower interconnect level comprising a first dielectric layer having at least one conductive material embedded therein, an upper interconnect level comprising a second dielectric having at least one via opening that exposes a portion of said at least one conductive material located atop said lower interconnect level, said lower and upper interconnect levels are separated in part by a dielectric capping layer, and a patterned hard mask on a surface of the said upper interconnect level; forming at least an infused surface region within an exposed portion of said conductive material; forming at least one line opening in said second dielectric material that extends above said at least one via opening; selectively removing said infused surface region to form a gouging feature within said conductive material; forming a diffusion barrier layer on exposed surfaces within at least one via opening, at least one line opening and at least said gouging feature; and filling said at least one line opening and at least one via opening with another conductive material.