Patent ID: 8093149

Claim:
A manufacturing method for a semiconductor device, comprising: (a) providing a semiconductor substrate; (b) forming a plurality of gate structures on the semiconductor substrate; (c) forming a first interlayer film to cover the semiconductor substrate and the gate structures; (d) forming a first wiring layer over the first interlayer film, the first wiring layer including sub-steps of: (d-1) forming a first layer including a second interlayer film with a dielectric constant of 3.0 or lower and a via; (d-2) after step (d-1), forming a second layer including a third interlayer film with a dielectric constant of 3.0 or lower and a wire; and (e) after step (d), forming at least one of upper wiring layers over the first wiring layer, each of the upper wiring layers being formed by performing the same step as step (d), wherein the first interlayer film and the second interlayer film are not removed from a wafer edge portion of the semiconductor substrate, and the third interlayer film is removed in a given width from the wafer edge portion of the semiconductor substrate.