Patent ID: 8719819

Claim:
A method comprising: managing, without direct intervention from an operating system (OS), a first user-level thread on a target instruction sequencer in response to executing a user-level monitoring instruction or a control transfer instruction on a source instruction sequencer of a processor, wherein the source instruction sequencer is under control of an application level program; and running a first user-level thread that contains one or more user-level instructions on the source instruction sequencer, wherein a user level control transfer instruction has: 1) a first field that makes reference to one or more instruction sequencers, 2) a second field for a scenario selected from a group of a first scenario to cause a sequencer whose identification is referenced in the first field to cause a set of sequencer-specific architectural states to be respectively initialized to a set of initial values, a second scenario to cause a thread executing on a sequencer whose identification is referenced in the first field to fork execution, and a third scenario to cause a sequencer whose identification is referenced in the first field to operate in a proxy execution mode, 3) a third field for a conditional parameter to condition execution of instructions that execute on a sequencer that executes a control transfer instruction, 4) a fourth field that defines a routing function to control whether a signal generated as a result of executing the user level control transfer instruction is sent as a broadcast, unicast, or multicast signal, 5) a fifth field for a scenario specific payload; and a user-level monitoring instruction includes: 1) a field that specifies an instruction sequencer, 2) a control message identifying a condition or anticipated event, and 3) a location of handler-code associated with the control message to perform a user-level thread operation.