Patent ID: 7217960

Claim:
A semiconductor device comprising: a substrate on which a first group III nitride semiconductor layer serving as an operation layer is formed; a second group III nitride semiconductor layer composed of a single layer or a plurality of layers, the second group III nitride semiconductor layer is formed on said first group III nitride semiconductor layer and functions as the barrier layer; a third group III nitride semiconductor layer which is not formed only at a gate forming region on said second group III nitride semiconductor layer; a first electrode which is formed on said third group III nitride semiconductor layer and functions as a source; a second electrode which is formed on said third group III nitride semiconductor layer and functions as a drain; an insulating film layer formed on said second and third group III nitride semiconductor layers between said first electrode and said second electrode; and a third electrode (gate) which is formed on said insulating film layer and controls a current flowing between said first electrode and said second electrode, wherein said second group III nitride semiconductor layer contains aluminum, and has a thickness and an aluminum composition ratio that are controlled so that, in the state where a voltage is not applied to said third electrode with respect to said first electrode, an energy at the bottom of a conduction band on a surface of said first group III nitride semiconductor layer directly under said third electrode may be higher than a Fermi energy in the location.