Patent ID: 8589839

Claim:
An electrostatic discharge (ESD) protection validator for an integrated circuit (IC), comprising: a circuit analyzer configured to compare component information of said IC with predefined ESD protection elements to identify ESD cells of said IC, wherein said component information is received from a netlist; wherein said circuit analyzer is configured to employ a pattern matching engine at a netlist level of abstraction to compare said IC component information with said predefined ESD protection elements, also at a netlist level of abstraction, to determine said identified predefined ESD cells existing in the netlist, said determining occurring at said netlist level of abstraction; an ESD cell verifier configured to compare physical attributes associated with said identified ESD cells, to ESD protection requirements and determine compliance therewith, said comparison performed with said netlist, and wherein said ESD cell verifier is configured to determine if each of said pins of said IC has an ESD cell coupled thereto.