Patent ID: 8884592

Claim:
A voltage regulator, comprising: a first switch; a hysteretic comparator coupled to an output of the first switch, wherein the hysteretic comparator is configured to generate a duty signal; and a Frequency Lock Loop (FLL), comprising: a delay module, a second switch coupled to the delay module, a first current source coupled to the second switch, and a second current source coupled to the second switch, wherein the first current source is configured to be larger than the second current source, wherein the FLL is coupled to a control input of the hysteretic comparator, and wherein the FLL is configured to: receive the duty signal, adjust a width of a pulse generated by the delay module based on a target switching frequency of the hysteretic comparator and a ratio of current between the first current source and the second current source, and generate, based on the pulse, a signal to alter a hysteresis of the hysteretic comparator such that a switching frequency of the first switch is maintained at the target switching frequency.