Patent ID: 8633520

Claim:
A semiconductor device comprising: a substrate having an impurity region therein; a gate electrode on the substrate; first and second interlayer insulating films on the substrate, said first interlayer insulating film extending between the second interlayer insulating film and the substrate; a metal interlayer insulating film on the second interlayer insulating film, said metal interlayer insulating film comprising a plurality of metal wiring layers therein; a liner insulating film extending between the second interlayer insulating film and the gate electrode; a first contact plug electrically connecting a first of the plurality of metal wiring layers to the impurity region; and a second contact plug electrically connecting a second of the plurality of metal wiring layers to the gate electrode, said second contact plug extending through said liner insulating film; wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film and the liner insulating film, and wherein said liner insulating film directly contacts a vertical sidewall of said second contact plug.