Patent ID: 8032350

Claim:
A method implementable in a computer system for generating a simulatable vector, comprising: creating in the computer system a transition vector from a sequence of bits having a rise time and a fall time, wherein the transition vector comprises voltage values only at timings corresponding to midpoints of transitions in the bit sequence; creating in the computer system a jittered transition vector from the transition vector, wherein the timing of the transitions in the jittered transition vector include timing jitter; creating in the computer system an upscaled jittered transition vector from the jittered transition vector, wherein the upscaled jittered transition vector comprises additional points when compared to the jittered transition vector, wherein at least some of the additional points comprise corners of the sequence of bits, wherein voltages of the additional points in the upscaled jittered transition vector are determined by the sequence of bits, and wherein timing of the corners is determined in accordance with the rise time and the fall time; and creating in the computer system a simulatable vector from the upscaled jittered transition vector, wherein voltages in the simulatable vector are separated by a time step.