Patent ID: 8866261

Claim:
A memory cell capacitor, comprising: a silicon wafer comprising a silicon-on-insulator (SOI) wafer having an SOI layer separated from a silicon substrate by a buried oxide (BOX); at least one trench in the silicon wafer that extends through the SOI layer, through the BOX and partway into the silicon substrate, wherein other than an n-band portion of the silicon substrate and a portion of the silicon substrate adjacent to the trench the silicon substrate is undoped, and wherein the portion of the silicon substrate adjacent to the trench is implanted with a dopant; sidewall spacers on vertical surfaces of the trench that cover and protect portions of the SOI layer through which the trench passes; a silicide within the trench that is formed in the silicon substrate and serves as a bottom electrode of the memory cell capacitor, wherein the portion of the silicon substrate implanted with the dopant extends out from the trench into the silicon substrate beyond the silicide, and wherein a contact resistance between the bottom electrode and the portion of the silicon substrate adjacent to the trench that is implanted with the dopant is from about 1 ×10 −6 ohm-cm 2 to about 1 ×10 −9 ohm-cm 2 ; a dielectric in the trench covering the bottom electrode; and a top electrode in the trench separated from the bottom electrode by the dielectric.