Patent ID: 8032804

Claim:
A memory system, comprising: a first memory vault comprising a first stacked plurality of memory arrays, each memory array in the first stacked plurality of memory arrays located on one of a plurality of stacked memory dies; a second memory vault comprising a second stacked plurality of memory arrays, each memory array in the second stacked plurality of memory arrays located on one of the plurality of stacked memory dies; a first memory vault controller (MVC) located on a logic die stacked with the plurality of stacked memory dies and communicatively coupled to the first memory vault to provide at least one of control, switching, or communication logic associated with the first memory vault; a second MVC located on the logic die and communicatively coupled to the second memory vault to provide at least one of control, switching, or communication logic associated with the second memory vault; and a system monitor processor of the logic die to monitor at least one operational parameter in a first set of operational parameters associated with at least one of the first and second memory vaults and to adjust at least one operational parameter in a second set of operational parameters associated with at least one of the first and second memory vaults.