Patent ID: 7276443

Claim:
A method for forming a metal wiring in a semiconductor device, the method comprising the steps of: i) depositing an interlayer dielectric film on a silicon substrate, the interlayer dielectric film having a contact hole for exposing a predetermined portion of the silicon substrate; ii) depositing a barrier layer on the interlayer dielectric film having the contact hole; iii) depositing, using an atomic layer deposition (ALD) technique, a first tungsten layer on the barrier layer by using SiH 4 or Si 2 H 6 as a reaction gas; iv) depositing, using the ALD technique, a second tungsten layer on the first tungsten layer by using B 2 H 6 as a reaction gas; v) depositing, using a chemical vapor deposition (CVD) technique, a third tungsten layer on the second tungsten layer resulting in the second and third tungsten layers having a combined specific resistance of less than about 12½ μΩ-cm and resulting in completely filing over the contact hole with the third tungsten layer; and vi) selectively etching the third tungsten layer, the second tungsten layer, the first tungsten layer, and the barrier layer, thereby forming the metal wiring.