Patent ID: 8457262

Claim:
An interference suppressor configured for computing interference-suppressed symbol estimates and performing processing during each of at least one iteration, the suppressor comprising a processor configured for calculating a stabilizing step size having a magnitude that is a function of at least a received signal; and weighting an error signal with the stabilizing step size; wherein the stabilizing step size is characterized by μ [ i ] = ( q _ - R ⁢ ⁢ F ⁢ ⁢ Γ [ i ] ⁢ b _ ^ [ i ] ) H ⁢ ( q _ - RF ⁢ ⁢ Γ [ i ] ⁢ b _ ^ [ i ] ) ( q _ - R ⁢ ⁢ Γ [ i ] ⁢ b _ ^ [ i ] ) H ⁢ R ⁡ ( q _ - R ⁢ ⁢ Γ [ i ] ⁢ b _ ^ [ i ] ) wherein μ [i] is a stabilizing step size after an i th iteration of the interference suppressor; q is a received signal vector produced from processing the received signal by a Rake receiver, combining, and despreading; {circumflex over (b)} [i] is a vector containing all symbol decisions after the i th iteration of the interference suppressor; R is a received-signal correlation matrix; F is an implementation matrix that is either an identity matrix or a transmit-signal correlation matrix; Γ (i) is a diagonal soft-weighting matrix that weights the elements of {circumflex over (b)} [i] ; and the superscript H denotes complex-conjugate matrix transposition.