Patent ID: 7675121

Claim:
A structure, comprising: a substrate comprising a buried oxide layer between a single-crystal upper silicon layer and a lower silicon layer; a contact region and a device region in said upper silicon layer; a dielectric isolation in said single-crystal upper silicon layer, a top surface of said dielectric isolation is coplanar with a top surface of said single-crystal upper silicon layer, said dielectric isolation extending to said buried oxide layer, said dielectric isolation completely surrounding and in direct contact with an inner perimeter and an outer perimeter of said contact region and completely surrounding and in direct contact with an outer perimeter of said device region; a doped polysilicon region extending through said single-crystal upper silicon layer in said contact region and extending through said buried oxide layer to said lower silicon layer, regions of said single-crystal upper silicon layer in said contact region remaining between said doped polysilicon region and said dielectric isolation; a gate dielectric layer between a gate electrode and a portion of said device region; a source region and a drain region in said device region, said source region and said drain region on opposite sides of said gate electrode; a first metal silicide layer on a top surface of said contact region, said first metal silicide layer contiguous on said doped polysilicon region and on said regions of said single-crystal upper silicon layer in said contact region remaining between said doped polysilicon region and said dielectric isolation; and a second metal silicide layer on a top surface of said source region and a third metal silicide layer on a top surface of said drain region.