Patent ID: 8037366

Claim:
A method, in a processing device, for issuing instructions in-order in an out-of-order Processor, the method comprising: receiving, by an instruction dispatch unit, an instruction for dispatch to one of a plurality of execution units in the processing device; analyzing, by the instruction dispatch unit, a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register; responsive to the previous tag associated with the previous instruction existing in the tag register injecting by the instruction dispatch unit, a consumer into the instruction that points to the previous tag corresponding to the previous instruction; determining by the instruction dispatch unit, whether the instruction produces data; responsive to the instruction failing to produce data injecting by the instruction dispatch unit, a false producer into the instruction wherein the false producer is added for scheduling of instructions in-order in the out-of-order processor; storing by the instruction dispatch unit, a tag corresponding to the instruction in the tag register; and dispatching, by the instruction dispatch unit, the instruction to an issue queue for issue to the one of the plurality of execution units.