Patent ID: 7224610

Claim:
A memory-cell-programming apparatus comprising: a bitline pair includes an even bitline and an odd bitline, the even bitline coupled to an even array of memory cells and the odd bitline coupled to an odd array of memory cells, the bitline pair capable of providing programming voltages to the even array and the odd array of memory cells; a first pair of bitline selection devices coupled to a programming-voltage node, the first pair of bitline selection devices capable of coupling the bitline pair to a programming-voltage level and configured to alternately couple a single bitline of the bitline pair at a time to the programming-voltage node; a storage cell capable of storing a single bit of coupling data; and a second pair of bitline selection devices coupled to the first pair of bitline selection devices, the bitline pair, and the storage cell, the second pair of bitline selection devices being configured to select the bitline pair based on the coupling data stored in the storage cell.