Patent ID: 7821848

Claim:
A flash memory comprising: a first input operable to receive an external input signal including at least one command, and to provide the at least one command on a first output; a first command decoder including a second input and a second output, the second input coupled to the first output, and operable receive the at least one command and to partially decode the at least one command to generate at least one partially decoded command; a first command latch coupled to the first command decoder, the first command latch including a third input, a fourth input, and a third output, and operable to receive the partially decoded command at the third input and to latch the partially decoded command when a first write enable signal is received at the fourth input; a second command decoder including a fifth input and a fourth output, the fifth input coupled to the third output of the first command latch, the second command decoder operable to further decode at least some portion of the partially decoded command that is latched into the first command latch to generate at least one further decoded command; and a second command latch coupled to the second command decoder, the second command latch including a sixth input, a seventh input, and a fifth output, and operable to receive the further decoded command at the sixth input and to latch the further decoded command when a second enable signal is received at the seventh input.