Patent ID: 7860181

Claim:
A decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing said coding constraint is greater than the length of a channel memory of said partial response, said decoding apparatus comprising: a first calculation unit configured to carry out a first calculation on first branch information, which is defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for said first branches; a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of said first calculation; and a third calculation unit configured to carry out said second calculation on second path information defined as information on second paths for second branches included in said three or more branches merging in said state determined in advance as branches having the same branch information, in which said third calculation unit is configured to carry out said second calculation prior to a predetermined time of processing carried out by said first and second calculation units.