Patent ID: 8144828

Claim:
A counter module comprising: a first set of registers configured to store respective sets of first control data; a second set of registers configured to store respective sets of second control data; a first counter coupled to the first set of registers and configured to: receive counter input signals and an internal control signal; and generate a first count output and a first terminal count output according to one of the respective sets of the first control data, the internal control signal, and the counter input signals; a second counter coupled to the first counter and to the second set of registers, and configured to: receive the counter input signals; generate a second count output and a second terminal count output according to one of the respective sets of the second control data and the counter input signals; and output control logic configured to generate a timer output based on one or more of: the first terminal count output; or the second terminal count output; wherein the internal control signal is based on the second terminal count output.