Patent ID: 7286404

Claim:
A method for operating a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells which are connected in series, a plurality of word lines which are connected to the plurality of non-volatile semiconductor memory cells, a first selection gate which is connected between a bit line and one end of an array of the plurality of serially connected non-volatile semiconductor memory cells, a first selection gate line which is connected to the first selection gate, a second selection gate which is connected between a source line and another end of the array of the plurality of non-volatile semiconductor memory cells, and a second selection gate line which is connected to the second selection gate, comprising: writing data in a memory cell selected from the plurality of non-volatile semiconductor memory cells; performing a write verify operation which charges the bit line with a first voltage, applies a second voltage to the first selection gate line and the second selection gate line, and brings the first selection gate and the second selection gate into conduction; sensing a voltage of the bit line after maintaining, for a predetermined time period, a state where a third voltage is applied to the word line which is connected to the memory cell in which the data is written; and keeping the second voltage applied to the first selection gate line and the second selection gate line, and sensing a voltage of the bit line after maintaining, for a predetermined time period, a state where a voltage of the word line which is connected to the memory cell in which the data is written is changed from the third voltage to a fourth voltage.