Patent ID: 8110483

Claim:
A method comprising providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); selectively amorphizing the plurality of SOI layer regions and the STI, wherein the selectively amorphizing includes implanting the plurality of SOI layer regions and the STI with an implant species, the implanting of the plurality of SOI layer regions performed at a higher energy level than the implanting of the STI, wherein the selectively amorphizing causes the plurality of SOI layer regions to have a defect concentration approximately greater than 10 percent, wherein a depth of the defect concentration is approximately 60 percent to approximately 70 percent of a thickness of the wafer; and removing a portion of each of the selectively amorphized SOI layer regions to form at least one recess in the amorphized SOI layer.