Patent ID: 7564135

Claim:
A semiconductor device comprising: a conductive pattern disposed on a substrate; a first interlayer dielectric layer disposed on the substrate and the conductive pattern; a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern; a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern; a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern; a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern; and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern, wherein a shortest distance between the first dummy pattern and the second dummy pattern is less than a resolution limit of a photolithography process.