Patent ID: 7759798

Claim:
A semiconductor device comprising: a chip region; a sealing ring region which surrounds the chip region in plan; and a dummy region which surrounds an outer periphery of the sealing ring region in plan, the dummy region comprising: a semiconductor substrate; a first laminate which is provided over the semiconductor substrate and includes a first interlayer dielectric film having a first mechanical strength; a second laminate which is provided over the first laminate and includes a second interlayer dielectric film having a mechanical strength higher than the first mechanical strength; at least one first region, the first region including a plurality of first metallic layers which are provided within the first laminate so as to mutually overlap in plan, and the first region also including vias for mutually coupling the first metallic layers; and at least one second region, the second region including a plurality of second metallic layers which are provided within the second laminate so as to mutually overlap in plan, and the second region also including vias for mutually coupling the second metallic layers, the second region overlapping at least a part of the first region in plan, being not coupled with the first region by vias, and sandwiching the second interlayer dielectric film between the second region and the first region.