Patent ID: 7474119

Claim:
A logic circuit apparatus comprising: a circuit arrangement information memory configured to store circuit arrangement information corresponding to each unit circuit of a plurality of unit circuits; a programmable logic circuit having a circuit arrangement which is dynamically reconfigurable using the circuit arrangement information; a plurality of process data memories, wherein a different pair of said process data memories is respectively provided for each of said unit circuits, one process data memory in each of said pairs being configured to store input data for a corresponding one of said unit circuits and a second process data memory in each of said pairs being configured to store output data for said corresponding one of said unit circuits; and a controller configured to monitor at least one of a storage amount of the input data, a storage amount of the output data and an amount of storage area availability in the process data memory for the output data corresponding to each unit circuit of the plurality of unit circuits, and to control reconfiguration of the circuit arrangement of the programmable logic circuit when at least one of the storage amounts satisfies a condition.