Patent ID: 7979616

Claim:
A memory interface device (MID) for use in a cascade interconnect system and in communication with one or more memory devices, the MID comprising: a first connection to a high speed bus for operating at a first data rate, the first connection including receiver circuitry operating at the first data rate; a second connection to the high speed bus; an alternate communication means for operating at a second data rate that is slower than the first data rate, the second data rate set by a programmable timing circuit; and logic for facilitating: receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence; receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred, wherein the second command sequence comprises one or more idle transfers; processing the commands received via the alternate communication means as if the commands are directed to the MID; and redriving the commands received via the alternate communication means onto the high speed bus if the commands are directed to a downstream MID, the redriving via the second connection to the high speed bus.