Patent ID: 7685590

Claim:
A system for generating a delta between a first program binary and a second program binary, the system comprising: one or more processors; one or more memories; means for obtaining a first control flow graph (CFG) representation of the first binary and means for obtaining a second CFG representation of the second binary; means for comparing the first and second CFG representations to identify blocks (nominally matched blocks) that match in the first and second CFG representations, thereby identifying blocks (nominally unmatched blocks) in the second CFG representation that do not match in the first CFG representation, the means for comparing being based upon content of blocks being compared and augmented local neighborhoods of blocks surrounding blocks being compared, wherein a local neighborhood of a particular block consists of blocks neighboring that block in a CFG representation, but less than all the blocks in that CFG representation, and an augmented local neighborhood of that particular block consists that block's local neighborhood plus a random sampling of blocks from a substantially larger neighborhood of blocks surrounding that block, an augmented local neighborhood in a CFG representation consisting of less than all the blocks in that CFG representation; means for determining edit-operations that merges the unmatched blocks into the first CFG representation so that first CFG representation is substantially identical to the second CFG representation; and means for producing a delta comprising the unmatched blocks and the edit-operations, wherein one or more of the means comprise processor-executable instructions, which are executable on the one or more processors and are stored on the one or more memories.