Patent ID: 7062165

Claim:
A data regenerator for regenerating a data signal, comprising: a convertor for converting a received data signal into a binary data signal in dependence on conversion parameters; a descrambler for descrambline the binary data signal output by the convertor to produce an uncorrected binary data signal; an error corrector for correcting errors in the uncorrected binary data signal based on error correction code contained in the uncorrected binary data signal to produce a corrected binary data signal; rescrambling means for rescrambling the uncorrected binary data signal and the corrected binary data signal; and a performance monitor including a comparitor for performing a bitwise comparison of the rescrambled corrected binary data signal with the rescrambled uncorrected binary data signal to determine information about the relative number of logic “1”s and logic “0”s that have been corrected by the error corrector and output a feedback signal representative of said informationt, and wherein said comparitor aenerates a first signal when the comparitor detects that a logic “1” has been changed to a logic “0” and a second signal when the comparitor detects that a logic “0” has been changed to a loaic “1” by the error corrector, and wherein the performance monitor includesa duty cycle generator responsive to the first and second signals for generating the feedback signal, the feedback signal being indicative of the ratio of corrected logic “1”s to corrected logic “0”s for predetermined durations of the data signal, wherein the convertor adjusts at least some of the conversion parameters in dependance on the feedback signal.