Patent ID: 7519891

Claim:
An apparatus comprising: a first data generator to generate a test data pattern; a transmitter in communication with the first data generator, the transmitter to transmit the test data pattern; a multiplexer coupled between the first data generator and the transmitter to pass the data pattern to be received by the transmitter; a receiver to receive the test data pattern after it has been transmitted by the transmitter; a second data generator to generate a second data pattern; a comparator coupled with the receiver, the comparator to compare the second data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel, wherein a start delimiter is used to delay the comparison to allow for delay in transmitting and receiving the test data pattern; a length counter to count a length of the test data pattern; and a round trip delay counter to time the delay between transmitting the test data pattern and receiving the test data pattern, wherein a number of clocks between a transmission and receipt of the start delimiter is counted by round trip delay counter; wherein the multiplexer selectively passes the received test data pattern to be re-transmitted by the transmitter.