Patent ID: 8588357

Claim:
A phase selector for tolerating jitter for a clock and data recovery circuit, the clock and data recovery circuit comprising an over-sampling circuit, a phase detecting module and a back-end processing module, the over-sampling circuit over-sampling an input data stream in each cycle, for generating M over-sampling signals, the phase detecting module detecting the M over-sampling signals for determining a transition region of the input data stream in each cycle and generating a phase detecting signal accordingly, the phase selector generating a phase selecting signal according to the phase detecting signal, the back-end processing module selecting one of the M over-sampling signals to be an output data signal according to the phase selecting signal, the phase selector comprising: a comparing module, for comparing the phase detecting signal generated by the phase detecting module with a phase selecting signal corresponding to a previous cycle, and comparing a phase detecting signal corresponding to previous N cycles with the phase selecting signal corresponding to the previous cycle, for generating (N+1) error signals; a weighting circuit, for calculating a weighting error signal according to the (N+1) error signals and (N+1) weighting parameters; and a predictor, for comparing the weighting error signal, a first predetermined threshold value and a second predetermined threshold value, for generating a phase adjusting signal, and generating the phase selecting signal according to the phase adjusting signal and the phase selecting signal corresponding to the previous cycle; wherein M and N represent positive integers greater than 1, respectively.