Patent ID: 8190829

Claim:
A data processing apparatus, comprising: a first and second data processing circuit, each with an output for outputting memory access requests, at least the first data processing circuit outputting respective access requests each during a respective validity duration interval; a multiplexing circuit with inputs coupled to the outputs of the first and second data processing circuits; a memory circuit with an input for accepting the access requests successively from an output of the multiplexing circuit, each at least after a minimum memory repetition period following acceptance of a preceding access request; a timing circuit coupled to the first and second data processing circuit and the memory circuit, and arranged to time operation of the first and second processing circuit each substantially periodically, so that the validity duration intervals are substantially periodical, the timing circuit being arranged to: select acceptance time points at which each particular access request from the first data processing circuit is accepted within the validity duration interval in which this particular access request is made, and delay a position of the acceptance time points within the validity duration intervals in response to an access request from the second processing circuit, the timing circuit comprising first and second clocking circuits coupled to clock inputs of the first and second data processing circuit at a first and second frequency of the first and second clocking circuit respectively, the sum of the first and second frequency being smaller than the inverse of the minimum memory repetition period.