Patent ID: 7599207

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells each constituted of a capacitor and a transistor connected to the capacitor are arranged in matrix form; a plurality of word lines respectively connected to the memory cells disposed in a column direction; a plurality of bit line pairs respectively connected to the memory cells disposed in a row direction; a word line driver that selectively activates the word lines; an address storage unit that stores a threshold memory address that sets a first block of the memory cell array wherein each respective data of one bit are stored in respective ones of the memory cells of the first block, and that sets a second block of the memory cell array wherein each respective data of one bit are stored in respective pairs of the memory cells of the second block, an address comparing unit that determines whether each of memory addresses for specifying the memory cells to be accessed belongs to either of the first and second blocks by comparison with the threshold memory address stored in the address storage unit; and an address switching unit that controls the word line driver in such a manner that when it is determined that the memory address for specifying each memory cell to be accessed belongs to the first block, a corresponding one of the word lines in the first block is activated and when it is determined that the memory address belongs to the second block, a corresponding pair of the word lines in the second block is activated.