Patent ID: 8020129

Claim:
A method, performed on a computer system, for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the method comprising: using the computer system to perform the following: obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data is obtained from a circuit-level model of the at least one logic gate and is in a form that approximates a current source, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance; obtaining a model of the interconnect circuit; deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit, wherein the deriving of a sequence of crossing times comprises estimating a charge supplied by the at least one logic gate to the interconnect circuit on a piecewise basis at each of the successive voltage thresholds provided in the driving point voltage waveform and determining a dynamic capacitance on a piecewise basis at each of the successive voltage thresholds from the estimated charges, wherein each crossing time is derived as a function of each determined dynamic capacitance and corresponding sequence of voltage thresholds; and generating a voltage waveform by piecing together the derived sequence of crossing times and the corresponding sequence of voltage thresholds, wherein the generated voltage waveform is a piecewise linear waveform indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.