Patent ID: 7415404

Claim:
A clock circuit for generating a sequence of clock signals, comprising: a first delay locked loop having a multi-tap adjustable delay circuit and a phase detector, the multi-tap adjustable delay circuit having an input clock node to receive a reference clock signal and a control node to receive a control signal and configured to generate the sequence of clock signals which are increasingly delayed from a first clock signal to a last clock signal by delaying the reference clock signal by respective delays that are a function of the control signal, the phase detector configured to compare the phase of the first and last clock signals and generate the control signal as a function of a phase relationship therebetween, the phase detector including a charge pump and configured to generate a first signal in response to a first-type of clock edge of the last clock signal lagging a second-type of clock edge of the first clock signal and generate a second signal in response to the first-type of clock edge of the last clock signal leading the second-type of clock edge of the first clock signal, the phase detector further configured to generate as the control signal a voltage that increases toward one polarity responsive to the first signal and toward the opposite polarity responsive to the second signal, the first delay locked loop configured to delay the last clock signal to have a first phase relative to the first clock signal; and a second delay locked loop configured to synchronize the first clock signal to a master clock signal whereby the clock signals in the sequence have different respective phases with respect to the master clock signal.