Patent ID: 7143246

Claim:
A method in a multiprocessor system, including at least two processors and a cache coherency controller, coupled to address concentration devices, the method operable in said cache coherency controller for improving coherent data transfers, the method comprising the steps of: initiating a first memory transaction request command to a first processor of said multiple processors; determining priority receipt status of a next memory transaction request; expanding snoop responses and accumulated snoop responses to provide a coherency action for all cacheline requests utilizing a burst command; forwarding said transaction requests from said master or said controller to a solitary global serialization device, said serialization device further comprising a multiple cacheline request indicator; grouping multiple and sequential coherent transfers into a burst operation on said processor bus; determining occurrence of the burst operation; timing said burst operation; snooping said burst operation to form a plurality of snoop replies; concentrating all addresses of said plurality of snoop replies to form a combined snoop response; and broadcasting the combined snoop response to a plurality of device entities.