Patent ID: 7968998

Claim:
A semiconductor package comprising: a generally planar die paddle defining opposed top and bottom paddle surfaces and multiple peripheral edge segments; a plurality of first leads which each define opposed top and bottom first lead surfaces, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle; a plurality of second leads which each define opposed top and bottom second lead surfaces and include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle in electrical isolation from the die paddle and each other; a semiconductor die attached to the top paddle surface of the die paddle and electrically connected to at least one of each of the first and second leads; and a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the downsets of the second leads are covered by the package body, and at least portions of the bottom paddle surface of the die paddle and the bottom first and second lead surfaces of the first and second leads are exposed in and substantially flush with the bottom surface of the package body, the bottom first lead surfaces of the first leads of each of the sets thereof being disposed between one of the peripheral edge segments of the die paddle and the bottom second lead surfaces of the second leads of a corresponding one of the sets thereof.