Patent ID: 8285922

Claim:
An address generator to perform operation of the address generation function f(X) which produces a unique address A corresponding to a binary input vector (hereinafter referred to simply as “input vector”) X if said input vector is a registered vector, otherwise produces “invalid value”, comprising: A. one or more master address generators to produce the unique address A corresponding to said input vector X if said input vector X belongs to a subset of a registered vector set, otherwise produce “invalid value”; B. a slave address generator that produces the unique address A corresponding to said input vector X if all the outputs of the master address generators are “invalid value” and said input vector X which belongs to said registered vector set, otherwise performs operation of a slave address generation function f 2 (X) to produce “invalid value” or an unique address A corresponding to said input vector X; and C. an output combiner that produces the output value of the master address generator or the output value of the slave address generator as the unique address A if the output value of the master address generator or the slave address generator are not “invalid value”, otherwise produces “invalid value”; wherein said master address generator comprising: a. a hash network to hash the bound variables X 1i to produce the hashed bound variables Y 1i for the partition (X 1i ,X 2i ) of the input vector X, where i denotes an index identifying master address generator; b. a tentative address generator that produces a unique address A as a tentative address A′ if the unique address A corresponds one-to-one to said bound variables Y 1i (i.e., when no hash collision occurs), otherwise (i.e., when hash collision occurs), produces an arbitrary value or one of the corresponding unique address A as a tentative address A′; c. a data re-generator that performs operation of data regeneration function f 1 (A), which is an inverse function of the address generation function f(X), wherein regenerated vector X″=f 1 (A′) is produced when said tentative address A′ produced by said tentative address generator is applied, and d. a unique address detector that compares said regenerated vector X″ with said input vector X, and produces said tentative address A′ if they are identical, otherwise produces “invalid value”; and wherein said slave address generator is configured by an LUT cascade logic network, consisting of plural subfunction memories connected in a cascade, and said each subfunction memory stores subfunction, which is obtained by a functional decomposition of the slave address generation function f 2 (X), as an LUT.