Patent ID: 8431457

Claim:
A method for fabricating a semiconductor device, comprising: a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches; a′) forming asymmetric sidewalls in the gate runner/termination trenches, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered due to application of the second mask; b) forming a first conductive region in the plurality of trenches; c) forming an intermediate dielectric region and a termination protection region by applying a second mask; d) forming a second conductive region in at least some of the trenches; e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask; f) disposing a metal layer; and g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask.