Patent ID: 8917554

Claim:
A method of operating non-volatile storage, comprising: applying an erase voltage to a first well in a substrate, wherein a NAND memory array resides on the first well, the NAND memory array including a plurality of blocks of non-volatile storage elements; applying a negative voltage to a second well in the substrate while applying the erase voltage, wherein a first word line (WL) switch transistor and a second WL switch transistor reside on the second well; applying a first voltage to a first terminal of the first word line (WL) switch transistor while applying the erase voltage, the first WL switch transistor having a second terminal coupled to a first word line in a selected block of the NAND memory array; applying a select voltage to the first WL switch transistor while applying the first voltage, the erase voltage, and the negative voltage, wherein the first voltage is passed to the first word line; applying the first voltage to a first terminal of the second WL switch transistor while applying the erase voltage, the second WL switch transistor having a second terminal coupled to a second word line in an unselected block in the memory array; and applying an unselect voltage to the second word line switch transistor while applying the first voltage, the erase voltage and the negative voltage, wherein the first voltage is not passed to the second word line.