Patent ID: 7257525

Claim:
A method for simulating a circuit, comprising: representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph; the hierarchically arranged set of branches including a first branch that includes one or more subcircuits and a second branch that includes one or more subcircuits; wherein the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches; wherein a subcircuit at a higher hierarchical level comprises one or more subcircuits in a lower hierarchical level; arranging the subcircuits from the hierarchically arranged set of branches into one or more groups; determining a data structure for each subcircuit in a group, wherein the data structure supports a combination of selectively flattened and selectively expanded group of subcircuits; selecting a subcircuit as a simulation leader in each group and identifying remaining subcircuits as followers in the group, wherein each simulation leader has states substantially equivalent to the followers; simulating the respective simulation leader of each group using a selectable simulation driver; storing simulation results of the respective simulation leader of each group; and replicating the simulation results of the respective simulation leader of each group to its followers.