Patent ID: 7483173

Claim:
A data processor with the function of synchronizing a plurality of chips, comprising: a first data processing section which includes input connection terminals which take in object data, an object data enable signal (INHDEN) from the outside, and an object read clock (IMCLK) from the outside, a data holding section in which the object data is stored on the basis of an internal clock, a synchronizing circuit which reads the object data stored in the data holding section on the basis of the object data enable signal (INHDEN) from the outside and the object read clock (IMCLK) from the outside, and output connection terminals which output to the outside the output object data from the data holding section, the object data enable signal (INHDEN) from the outside, and an internal clock equivalent to the object read clock (IMCLK); and a second data processing section which includes second input connection terminals corresponding to the input connection terminals, a second data holding section corresponding to the data holding section, a second synchronizing circuit corresponding to the synchronizing circuit, and second output terminals corresponding to the output connection terminals, wherein the object data enable signal (INHDEN) and object read clock (IMCLK) from the output connection terminals of the first object processing block are supplied to second input connection terminals.