Patent ID: 8145974

Claim:
An apparatus, comprising: a demodulator for processing a plurality of signals, successively received from a communication channel, thereby generating a plurality of digital signals, wherein the demodulator including a metric generator for calculating respective pluralities of log-likelihood ratios (LLRs) corresponding to a plurality of bits of the plurality of digital signals such that each of the plurality of LLRs corresponds to a respective one of the plurality of bits; a memory module, coupled to the demodulator, for selectively storing of LLRs from the respective pluralities of LLRs, correspondingly from the successively received plurality of signals, until LLRs corresponding to an entire encoded block being available for use in turbo decoding the entire encoded block; and a turbo decoder, coupled to the memory module, for employing the plurality of LLRs selectively stored within the memory module to make estimates of the plurality of bits of the entire encoded block; and wherein: the memory module including only a number of memory locations to store one LLR for each of the plurality of bits of the digital signal.