Patent ID: 7782064

Claim:
A test apparatus that tests a device under test, comprising: a control apparatus that controls the test apparatus; a pattern generator that generates a plurality of test patterns to be provided to a plurality of input terminals of the device under test; a plurality of variable delay circuits that designate a timing for supplying each of the plurality of test patterns to a corresponding input terminal of the plurality of input terminals; and a plurality of micro-controllers that operate in parallel, according to instructions from the control apparatus, to each measure a delay amount of a variable delay circuit when the variable delay circuit is set with a prescribed delay setting value and store the delay setting value in association with the measured delay amount; a reference clock generator that generates a reference clock; a plurality of test signal supplying sections that are provided to correspond respectively to a plurality of groups, each group including two or more input terminals from among the plurality of input terminals, and that each supply test signals based on the test patterns to the input terminals in the corresponding group, wherein each test signal supplying section includes: a plurality of the variable delay circuits; at least one micro-controller from among the plurality of micro-controllers; a plurality of memories that are provided to correspond respectively to the input terminals in the corresponding group, and that each output, to a corresponding variable delay circuit, a delay setting value stored in association with a delay designation value designated by the test pattern of the corresponding input terminal; and a plurality of test signal output sections that are provided to correspond respectively to the input terminals in the corresponding group, and that each output, to the corresponding input terminal, a test signal based on a corresponding timing signal, the plurality of variable delay circuits are provided to correspond respectively to the input terminals in each of the groups, and each generate a timing signal by delaying the reference clock by a delay amount according to a delay setting value input thereto, and the plurality of micro-controllers measure the delay amount based on the delay setting value for each variable delay circuit corresponding to each group according to instructions from the control apparatus, and each store the delay setting value associated with the delay designation value based on the measurement result for each variable delay circuit in the corresponding memory.