Patent ID: 7435642

Claim:
A method of evaluating the uniformity of the thickness of the polysilicon gate layer, comprising: providing a substrate having a dense trenches area and a sparse trenches area; forming a plurality of first trench isolation structures in the dense trenches area of the substrate and simultaneously forming a plurality of second trench isolation structures in the sparse trenches area of the substrate, wherein a mask layer is formed between the gaps of the first trench isolation structures and the second trench isolation structures; removing portions of the first trench isolation structures of the dense trenches area to make the top surface of the first trench isolation structures lower than that of the second trench isolation structures; removing the mask layer until the surface of the substrate is exposed; forming a polysilicon gate layer to cover the substrate, the first trench isolation structures and the second trench isolation structures; and performing a planarization process for removing portions of the polysilicon gate layer.