Patent ID: 7145382

Claim:
A charge pump circuit suitable for a low-voltage process, the charge pump circuit being connected by an input thereof to an integrated circuit voltage source to produce at a voltage-output terminal of the charge pump circuit a voltage V OUT higher than a voltage V DD of the integrated circuit voltage source, the charge pump circuit comprising a timing signal generator outputting a pair of complementary timing signals, and a plurality of voltage amplifying circuits formed in n stages, each stage having a first timing input coupled to one of said pair of complementary timing signals and a second timing input coupled to the other of said pair of complementary timing signals, each first timing input of said n stages being alternately coupled to a different one of said pair of complementary timing signals and each second timing input of said n stages being alternately coupled to a different one of said pair of complementary timing signals, each stage of said n stages of the voltage amplifying circuits comprising: a first CMOS device and a second CMOS device coupled to said first CMOS device, said first CMOS device including a first NMOS transistor with a drain coupled to a first node and a first PMOS transistor with a drain coupled to said first node, said second CMOS device including a second NMOS transistor with a drain coupled to a second node and a second PMOS transistor with a drain coupled to said second node, each of said first NMOS and first PMOS transistors respectively having a gate electrode coupled to said second node and each of said second NMOS and second PMOS transistors respectively having a gate electrode coupled to said first node, said first NMOS transistor having a source defining a first input and said second NMOS transistor having a source defining a second input, said first PMOS transistor having a source defining a first output and said second PMOS transistor having a source defining a second output; a first capacitor and a second capacitor, said first capacitor having a first terminal defining said first timing input and a second terminal coupled to said first node, said second capacitor having a first terminal defining said second timing input and a second terminal coupled to said second node; and two diode devices, each of said two diode devices having anodes connected to a respective one of said first and second nodes for guiding electrical charges accumulating on corresponding gate electrodes to a succeeding stage; wherein said first and second inputs of a first stage are mutually coupled to the V DD integrated circuit voltage source and said first and second outputs of each of said first through n–1 stages are connected to a corresponding one of said first and second inputs of a succeeding stage, said first and second outputs of said nth stage being mutually coupled to an output of said charge pump circuit.