Patent ID: 6875680

Claim:
A method of manufacturing a transistor using a dummy gate pattern, the method comprising: sequentially depositing on a substrate a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer; forming a trench region by etching said second nitride layer, said second oxide layer, said first nitride layer, said first oxide layer and said substrate; depositing a first insulation layer on said second nitride layer and said trench region; planarizing said first insulation layer up to said second nitride layer; forming a dummy gate pattern by etching said second nitride layer, said second oxide layer, said first nitride layer; forming a lightly doped drain (LDD) underneath both sides of said dummy gate pattern in said substrate and depositing a third nitride layer at both sides of said dummy gate pattern; removing said second nitride layer; forming a source and a drain underneath both sides of said dummy gate pattern in said substrate; depositing a fourth nitride layer and a second insulation layer thereon; planarizing said second insulation layer up to said fourth nitride layer on said dummy gate pattern; removing an exposed portion of said fourth nitride layer, said second oxide layer, and said first nitride layer in said dummy gate pattern; performing a local channel implantation to form a local channel region in said substrate; removing said first oxide layer in said dummy gate pattern and growing a third insulation thereto; forming a gate electrode in said dummy gate pattern.