Patent ID: 7383522

Claim:
A system for crosstalk-aware timing analysis, the system comprising: a crosstalk analysis module operable to: access a design of a circuit; identify one or more critical paths in the design, each critical path comprising one or more victim interconnects and one or more cells; identify one or more potential aggressor interconnects associated with each victim interconnect; for each victim interconnect, extract one or more parasitics of the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect; compute timing windows of the potential aggressor interconnects; compute a first timing of each cell and each victim interconnect on each critical path; and for each critical path: generate one or more timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on the critical path, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects; traverse the critical path from a start point on the critical path to an end point on the critical path; and using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the critical path, compute a second timing of each cell and each victim interconnect on the critical path according to the traversal of the critical path.