Patent ID: 8217683

Claim:
An electronic device comprising: electronic circuitry that has a phase-detector for detecting a phase difference between a first signal and a second signal, wherein: each of the first and second signals is a binary signal; the first and second signals are uniform; the phase-detector includes a basic phase-detector for detecting a phase difference of π/2; the basic phase-detector comprises: a first controllable current source, having a first main current path, and a second controllable current source, having a second main current path, the first and second main current paths being connected in parallel between a first output node and a further current source, wherein the first output node is coupled to a reference voltage via a first resistor; a third controllable current source, having a third main current path, and a fourth controllable current source, having a fourth main current path, the third and fourth main current paths being connected in parallel between a second output node and the further current source, wherein the second output node is coupled to the reference voltage via a second resistor; the first controllable current source has a first control input for receiving a first input signal representative of a linear combination of the first and second signals; the second controllable current source has a second control input for receiving a second input signal representative of a linear combination of a logic complement of the first signal and a logic complement of the second signal; the third controllable current source has a third control input for receiving a third input signal representative of a linear combination of the second signal and a logic complement of the first signal; the fourth controllable current source has a fourth control input for receiving a fourth input signal representative of a linear combination of the first signal and a logic complement of the second signal; the phase detector has a calibration circuit that comprises one or more first cells connected to the second output node; each respective one of the first cells comprises a respective fifth controllable current source, having a respective fifth main current path, and a respective sixth controllable current source having a respective sixth main current path, the respective fifth and respective sixth main current paths being connected in parallel between the second output node and a respective first current source; the respective fifth controllable current source has a respective fifth control input for receiving the third input signal; and the respective sixth controllable current source has a respective sixth control input for receiving the fourth input signal.