Patent ID: 7187000

Claim:
A semiconductor structure comprising: first and second isolation structures positioned to form first and second boundaries, the first and second isolation structures each have a first end, a second end, and an interior wall; a well region defined by the interior walls of the first and second boundaries, and doped with a first type dopant; a gate pedestal formed over the well region and having a first end and a second end distally positioned from the first end, wherein the second end at least partially overlies the well region and is doped with the first type dopant; a dielectric layer positioned between the gate pedestal and the well region; a source region and a drain region formed on opposite sides of the gate pedestal within the well region and doped with a second type dopant opposite in type to the first type dopant; and a junction isolation feature positioned between the well region and a substrate underlying the well region and configured to provide isolation between a lower region of the well region and the substrate, wherein the junction isolation feature is further positioned adjacent the interior walls of the first and second boundaries a distance that is not greater than that separating the first and second boundaries.