Patent ID: 7723802

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on one main surface of said semiconductor substrate; a first semiconductor region of the first conductivity type formed in a surface of said semiconductor layer and connected to said semiconductor substrate through a semiconductor region of the first conductivity type; a second semiconductor region of the first conductivity type formed in the surface of said semiconductor layer apart from said first semiconductor region; a third semiconductor region of the second conductivity type formed in a surface of said first semiconductor region so as to be surrounded by said first semiconductor region; a first gate electrode provided on a surface portion of said first semiconductor region which is sandwiched between said third semiconductor region and said semiconductor layer, with a first gate insulating film in between said first gate electrode and said surface portion of said first semiconductor region; a first collector electrode provided on said second semiconductor region; an emitter electrode connected to said first and third semiconductor regions; a fourth semiconductor region of the first conductivity type formed in the surface of said semiconductor layer apart from said first and second semiconductor regions; a fifth semiconductor region of the second conductivity type formed in a surface of said fourth semiconductor region so as to be surrounded by said fourth semiconductor region; a second collector electrode provided on said fifth semiconductor region and connected to said first collector electrode; and a sixth semiconductor region of the second conductivity tyre formed in the surface of said semiconductor layer apart from said third and fifth semiconductor regions; a conducting electrode separated from said first and second collector electrodes, separated from said fifth semiconductor region, and connected to said fourth semiconductor region and said sixth semiconductor region to bridge both of said fourth semiconductor region and said sixth semiconductor region and form a conducting path from said semiconductor layer to said fourth semiconductor region.