Patent ID: 7206902

Claim:
A prefetcher for predicting accesses to a memory comprising: a first memory address predictor configured to associate a subset of addresses to an address and to predict a group of addresses based on at least one address of said subset, wherein said at least one address of said subset is unpatternable to said address said first memory address predictor including: a nonsequential predictor to generate said group of addresses as nonsequential predictions when said address is detected, said nonsequential predictor including a repository for storing associations of said subset of addresses to said address in a manner that prioritizes each of said subset of addresses in relation to others, wherein said address is stored as a trigger address and said subset of addresses are stored as target addresses, and a nonsequential prediction engine configured to detect said address in a stream of addresses and is configured further to select said at least one address as a nonsequential prediction based on its priority being a highest priority, said highest priority being at least indicative that a processor has requested said at least one address most recently relative to others of said of addresses; a suppressor configured to suppress generating at least one predicted address; and an expediter to designate a first address of a sequential stream of addresses as a new trigger address for said at least one address if said trigger address is in said sequential stream and if said nonsequential predictions are generated sooner in time with said new trigger address than with said trigger address.