Patent ID: 8924612

Claim:
An apparatus for providing a bidirectional communications link between a master device and a slave device, comprising: first endpoint circuitry configured to be coupled to the master device; second endpoint circuitry configured to be coupled to the slave device; bidirectional communication circuitry coupled to said first endpoint circuitry and said second endpoint circuitry and configured to transfer forward data packets from the first endpoint circuitry to the second endpoint circuitry and to transfer reverse data packets from the second endpoint circuitry to the first endpoint circuitry; the first endpoint circuitry comprising a forward packet transmitter configured to generate said forward data packets and a reverse packet receiver configured to receive said reverse data packets into a reverse packet buffer circuit; the second endpoint circuitry comprising a reverse packet transmitter configured to generate said reverse data packets and a forward packet receiver configured to receive said forward data packets into a forward packet buffer circuit; the first endpoint circuitry further comprising forward credit use circuitry configured to gate transmission of forward data packets from the forward packet transmitter to the forward packet receiver in dependence on forward credit information issued from the forward packet receiver over said bidirectional communication circuitry in response to forward data packets being removed from said forward packet buffer circuit, the first endpoint circuitry further comprising forward credit checking circuitry configured to monitor a status of the forward credit use circuitry and to assert an outstanding forward credit signal if said status indicates that some forward credit information is outstanding from the forward packet receiver; and the second endpoint circuitry further comprising reverse credit use circuitry configured to gate transmission of reverse data packets from the reverse packet transmitter to the reverse packet receiver in dependence on reverse credit information issued from the reverse packet receiver over said bidirectional communication circuitry in response to reverse data packets being removed from said reverse packet buffer circuit, the second endpoint circuitry further comprising reverse credit checking circuitry configured to monitor a status of the reverse credit use circuitry and to assert an outstanding reverse credit signal if said status indicates that some reverse credit information is outstanding from the reverse packet receiver; wherein in response to a power down condition requiring a power down of at least one of the first endpoint circuitry and the second endpoint circuitry, performance of said power down is deferred until both said outstanding forward credit signal and said outstanding reverse credit signal have been de-asserted.