Patent ID: 7287213

Claim:
A circuit to calculate the cumulative parity of a binary number sequence, comprising: an array of functional modules, the modules aligned to form columns and rows within the array, the array configured to receive the binary number sequence at a first column of the modules and to produce the cumulative parity as output at a last column of the modules, each of the modules being one of: a parity module configured to receive certain input bits from one of the binary number sequence and a previous column and to calculate the parity of the certain input bits; and a delay module configured to receive other input bits from one of the binary number sequence and a previous column and to delay the other input bits, wherein the parity modules form the last column of the modules, the first column of modules to the second to last column of modules forms an inner array having an equivalent number of rows and columns of modules, and within the inner array of modules the parity modules form a diagonal of the inner array from a first row to a last row and the delay modules are the remaining modules within the inner array.