Patent ID: 7831006

Claim:
An apparatus for reducing transient current swings during mode transitions of high frequency/high power circuits, comprising: a high frequency signal source that generates a high frequency clock signal; a finite state machine coupled to the high frequency signal source; an n-bit ring shift register divider coupled to the high frequency signal source and to at least one output of the finite state machine; and a logic module defining a core clock output signal coupled to the high frequency signal source, to at least one output of the divider, and to the at least one output of the finite state machine, wherein the finite state machine generates an n-bit shift register input and a load signal; wherein the n-bit ring shift register divider receives the load signal and the n-bit shift register input and responsive to the load signal being asserted generates a register output; wherein the logic module receives the load signal, the high frequency clock signal, and the register output; wherein the logic module masks the high frequency clock signal according to the register output to generate a divided clock signal; and wherein the logic module selects between the high frequency clock signal and the divided clock signal based on the load signal.