Patent ID: 7412343

Claim:
A method for testing a field programmable gate array comprising: (a) applying a test pattern approximately simultaneously to a first path under test in the field-programmable gate array and a second path under test in the field-programmable gate array, wherein the first path under test and the second path under test have substantially the same propagation delays in a fault free circuit; (b) receiving a first output signal indicating that the test pattern has propagated through at least one of the first path under test and the second path under test; (c) receiving a second output signal that indicates the test pattern has propagated through each of the first path under test and the second path under test; (d) determining the interval between receiving the first output signal and the second output signal; and (e) identifying a fault in at least one of the first path under test and the second path under test when the interval exceeds a threshold; and (f) causing an indication of the fault to be output, wherein the determining the interval between the first output signal and the second output signal comprises: activating an oscillating signal after receiving the first output signal; deactivating the oscillating signal after receiving the second output signal; and counting the number of oscillation cycles occurring while the oscillating signal is active.