Patent ID: 8042020

Claim:
A data error correction circuit, comprising: a plurality of one-bit registers; a data error detection unit configured to detect whether all data values respectively stored in the plurality of the registers are equal to each other; and a data correction unit configured to determine correct data values based upon each of the stored data values, and configured to store the correct data values into the registers, respectively, if the data values are not equal, wherein the data error detection circuit comprises: a first AND-gate receiving all bits output by the one-bit registers; a plurality of inverters receiving the all bits, wherein each inverter receives a corresponding one of the all bits to generate inverted bits; a second AND-gate, all inputs of the second AND-gate receiving the inverted bits from the inverters; and an OR-gate receiving an output of the first AND-gate and an output of the second AND-gate, wherein an output of the OR-gate is a first logical value when all of the bits output by the one-bit registers are the same and a second and different logical value otherwise, wherein the data correction unit comprises: a logic gate receiving all bits output by the one-bit registers as inputs to output a value; a first selection unit receiving the value as a first input, an external data value as a second input, and a first selection signal based on the output of the OR-gate, wherein the first selection unit outputs one of its inputs to data terminals of the one-bit registers based on the first selection signal; and a second selection unit receiving an external clock signal as a first input, a clock signal based on the output of the OR-gate as a second input, and a second selection signal based on the output of the OR-gate, wherein the second selection unit outputs one of its inputs to clock terminals of the one-bit registers based on the second selection signal.