Patent ID: 6859395

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cell blocks arranged in a column direction and control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the control gate lines provided for the memory cell block, each of the plurality of memory cell units including a plurality of electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, a booster circuit which creates and generates program voltage, a plurality of different intermediate voltages and bit line voltage from power supply voltage, a row decoder which is supplied with the program voltage and the plurality of different intermediate voltages generated from the booster circuit, selects at least one of the control gate lines and selectively activates first and second selection gate lines respectively connected to gates of the first and second selection gate transistors, a bit line control circuit which is supplied with the bit line voltage generated from the booster circuit and performs operations of latching program data and sensing data at the readout time, and a column decoder which selects a column of the memory cell units, wherein the row decoder applies high voltage among the plurality of different intermediate voltages to non-selected control gate lines when the position of the selected control gate line lies near the bit line and applies low voltage among the plurality of different intermediate voltages to the non-selected control gate lines when the position of the selected control gate line is far away from the bit line.