Patent ID: 7663919

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells arranged in each of the columns being connected in series to form a NAND unit, the NAND unit having a first select gate connected to a first end of the NAND unit and a second select gate connected to a second end of the NAND unit, the first select gate being connected to one of bit lines, the memory cells arranged in each of the rows being connected to one of word lines, and first and second select lines arranged in a row being connected to respective gates of the first and second select gates; selection transistors which select the word lines, the first select line, and the second select line, gates of the selection transistors being connected in common; and a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read, and erase operations of data with respect to the memory cells, wherein the selection transistors are formed on a well, and a first negative voltage is supplied to the well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation, wherein the control circuit includes a negative voltage generator circuit which generates the first negative voltage.