Patent ID: 8539402

Claim:
A circuit design system comprising: a first computer to execute instructions, the first computer including a first storage device to store instructions for execution; a second computer to execute instructions independently of the first computer, the second computer including a second storage device to store instructions for execution; the first storage device having instructions stored therein to adapt the first computer to: receive a top level netlist of a top level of a partitioned integrated circuit design, receive a plurality of merged data and clock constraint timing graphs to respectively model a plurality of partition blocks in response to data and clock time budgeting, and optimize the top level netlist in response to the plurality of merged data and clock constraint timing graphs to design the top level without waiting for implementation of any partition block; and the second storage device having instructions stored therein to adapt the second computer to: receive a first partition block netlist of a first partition block in a lower level hierarchy of the partitioned integrated circuit design, receive a first clock timing constraint for the first partition block in response to the data and clock time budgeting, and optimize the first partition block; and wherein the top chip level and the first partition block are independently designed concurrently netlist to design the first partition block.