Patent ID: 7873830

Claim:
A method for controlling cryptography secured processing chips, said method comprising: obtaining a first cryptography secured processing chip and a second cryptography secured processing chip interfaced together via an interface circuit, and each coupled to an external memory, wherein the first cryptography secured processing chip is a first system on a chip having a tamper proof secure chip boundary and the second cryptography secured processing chip is a second system on a chip having a tamper proof secure chip boundary, the first and second cryptography secured processing chips being separate chips, and wherein the interface circuit is an unsecured communication link between the first and second cryptography secured processing chips which is used after power up of the first and second cryptography secured chips in establishing secure communications between the first and second cryptography secured processing chips through the external memory; independently powering up the first cryptography secured processing chip and the second cryptography secured processing chip; upon power up, authenticating the first cryptography secured processing chip to the second cryptography secured processing chip and authenticating the second cryptography secured processing chip to the first cryptography secured processing chip, wherein the authenticatings employ a first public/secret key pair stored in memory under battery power in the first cryptography secured processing chip and a second public/secret key pair stored in memory under battery power in the second cryptography secured processing chip; subsequent to the authenticatings, exchanging information between the first cryptography secured processing chip and the second cryptography secured processing chip, the exchanged information comprising for each cryptography secured processing chip: memory addresses of memory locations in external memory controlled by the cryptography secured processing chip; and using the exchanged information in coordinating access to the external memory by the first cryptography secured processing chip and the second cryptography secured processing chip, wherein the external memory is external to the first and second cryptography secured processing chips and the coordinating access comprises establishing secure communications between the first cryptography secured processing chip and the second cryptography secured processing chip through the external memory.