Patent ID: 8916939

Claim:
A device comprising: a substrate having first and second contact regions and a dielectric layer over the contact regions; first and second transistors over the substrate, wherein each of the transistors includes a gate conductor with first and second source/drain (S/D) regions; an etch stop layer disposed over the transistors; first and second vias in the dielectric layer, the first via is in communication with the first contact region and the second via is in communication with the second contact region, and a buried void which provides a communication path between the first and second vias, wherein the buried void is within the etch stop layer and extends to at least a portion of the dielectric layer, the buried void is at least partially filled with a dielectric filler, the partially filled buried void blocks the communication path between the first and second vias created by the buried void; and contact plugs, wherein the contact plugs are disposed in the vias.