Patent ID: 7180103

Claim:
A semiconductor device comprising: a III-VIII-V semiconductor substrate; a III-VIII-V channel layer formed over said substrate; a passivation layer comprising an insulating material formed over said channel layer; source and drain regions comprising source and drain contacts formed over said channel layer the source region in electrical contact with a source contact and the drain region in electrical contact with a drain contact; a gate electrode formed over the channel layer and in contact with the passivation layer wherein the device has a drift region which is the region between the gate electrode and the drain region; a second electrode formed over and in contact with the passivation layer, the second electrode extending into the drift region; wherein the passivation layer has an electrical thickness (E T ) that is calculated relative to a layer of Al 2 O 3 and is the thickness of the passivation layer (t) multiplied by the ratio of the dielectric constant of Al 2 O 3 to the average dielectric constant(K) of the passivation layer such that E T is less than about 0.3 μm and further that the passivation layer is an oxide formed by atomic layer deposition.