Patent ID: 8455313

Claim:
A method for fabricating a finFET device, the method comprising: forming a plurality of fin structures over a buried oxide (BOX) layer, the fin structures each comprising a semiconductor layer and extending in a first direction; forming a gate stack on the BOX layer, the gate stack being formed over the fin structures and extending in a second direction that is perpendicular to the first direction, the gate stack comprising a high-K dielectric layer and a metal gate; forming gate spacers on vertical sidewalls of the gate stack; depositing an epitaxial silicon (epi) layer over the fin structures, the epi layer merging the fin structures together; implanting ions to form source and drain regions in the semiconductor layers of the fin structures; forming dummy spacers on vertical sidewalls of the gate spacers; using the dummy spacers as a mask to recess or completely remove an exposed portion of the epi layer; and performing silicidation to form silicide regions that abut the source and drain regions, the silicide regions each including a vertical portion located on the vertical sidewall of the source or drain region.