Patent ID: 8837562

Claim:
An active capacitor multiplying circuit, comprising: a clock synthesis loop filter of at least second order, wherein the clock synthesis loop filter comprises a series combination of a first resistor and a first capacitor, and wherein the series combination of the first resistor and the first capacitor is coupled between a first charge pump interface and ground, and wherein the clock synthesis loop filter further comprises a second capacitor coupled between the first charge pump interface and the ground; a capacitor multiplying loop filter comprising a second capacitor coupled between a second charge pump interface and the ground, wherein the capacitor multiplying loop filter further comprises a second resistor coupled to the second charge pump interface and the second charge pump interface is coupled to the first charge pump interface; and an operational amplifier, driven by the first capacitor, for driving the second resistor, wherein a voltage presented at the first charge pump interface drives a voltage controlled oscillator (VCO).