Patent ID: 8171208

Claim:
A memory system comprising: a first storing area as a cache memory including a volatile semiconductor memory; second and third storing area including nonvolatile semiconductor memories in which readout and writing are performed in a page unit and erasing is performed in a block unit twice or a larger natural number times as large as the page unit; a management table group in which management information including storage locations of data stored in the first, second, and third storing areas is stored; and a controller that allocates a storage area of the nonvolatile semiconductor memory to the second and third storing areas in a logical block unit associated with one or more of the blocks, wherein when a readout request is received from outside, the controller determines, based on the management table group, whether an unwritten logical address area is present in the second or third storage area to which a logical address area requested to be read out is mapped and notifies, when the unwritten logical address area is present, predetermined fixed data to the outside in association with the unwritten logical address area.