Patent ID: 7869295

Claim:
A semiconductor memory apparatus comprising: a sense amplifier having two input lines and a power supply input terminal to receive a driving voltage, and configured to detect and amplify a difference between signals that are supplied to the two input lines; a sense amplifier voltage supply unit configured to supply a normal driving voltage as the driving voltage in a normal mode through the power supply input terminal of the sense amplifier and an overdriving voltage as the driving voltage in a overdriving mode through the power supply input terminal of the sense amplifier, an overdriving voltage level being higher than a normal driving voltage level; and a driving voltage unit configured to detect the overdriving voltage level of the power supply input terminal of the sense amplifier, and supply the normal driving voltage to the power supply input terminal of the sense amplifier using the detected overdriving voltage level, after overdriving mode, wherein the driving voltage unit includes a voltage detecting unit, a timing supply circuit unit, and a discharge control unit, and wherein the voltage detecting unit for detecting a level of a power supply voltage, includes: a power supply voltage divider unit configured to divide the level of the power supply voltage into predetermined levels and output a divided voltage; a power supply voltage state detecting unit configured to output a signal having information of the level of the power supply voltage in response to a voltage level difference between the divided voltage and a reference voltage; and a latch output unit configured to latch the signal having information of the level of the power supply voltage supplied from the power supply voltage state detecting unit for output to a discharge timing control unit.