Patent ID: 7391655

Claim:
A semiconductor integrated circuit comprising: nonvolatile memory cells each having a threshold voltage which can be changed reversibly by electrical erasing and writing; and a control circuit that controls the changing of the threshold voltage of each said nonvolatile memory cell, wherein said control circuit controls an erase process of performing simultaneous erasing to a plurality of the nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to at least one nonvolatile memory cell assigned to said one unit, based on a determination that the threshold voltage associated with said at least one nonvolatile memory cell has exceeded, in an erase direction, a first reference voltage level that is located between a lower limit voltage for a final erase distribution and a voltage level defining entry into a depletion state, and a second write process of performing, after a determination that all of the threshold voltages of the nonvolatile memory cells of the unit exceed, in the erase direction, a higher limit voltage of said erase distribution, writing to at least one nonvolatile memory cell of the unit based on a determination that the threshold voltage associated with that at least one nonvolatile memory cell has exceeded, in the erase direction, a second level located at said lower limit voltage for the final erase distribution.