Patent ID: 7790519

Claim:
A method of manufacturing a semiconductor device having a MOS gate side surface structure, the method comprising the steps of: providing a semiconductor substrate of one conductivity type having a main surface; forming a first insulator film covering the main surface of the substrate and exposing part of the main surface of the substrate by: forming a first oxide film having a first predetermined thickness on the entire main surface of the substrate; selectively etching the oxide film to form a patterned oxide film on the substrate having a major opening to expose the main surface of the substrate; forming a second oxide film having a second predetermined thickness that is substantially less than the first predetermined thickness over the major opening to cover the exposed main surface of the substrate; and forming a smaller opening than the major opening through the second oxide film to again expose the main surface of the substrate; forming a semiconductor layer of the one conductivity type on the exposed main surface of the semiconductor substrate and on the first insulator film, wherein the semiconductor layer is epitaxially grown from the exposed main surface of the substrate until the semiconductor layer is thicker than the first predetermined thickness; forming a second insulator film covering the semiconductor layer; forming a gate electrode of polycrystalline film on the second insulator film, the polycrystalline film covering only part of the second insulator film so that the polycrystalline film overlies the exposed part of the main surface not covered by the first insulator film and partly overlies the first insulator film; forming a base region of another conductivity type in a region of the semiconductor layer overlying the first insulator film; forming an emitter region of the one conductivity type in the base region, with part of the base region extending between the emitter region and a region overlying the exposed part of the main surface of the substrate not covered by the first insulator film; forming a third insulator film covering the gate electrode and the second insulator film; and forming an emitter electrode over the gate electrode and the third insulator film, the emitter electrode contacting the emitter region through the second and third insulator films.