Patent ID: 7812655

Claim:
A device, comprising: a delay-locked loop circuitry configured to trigger generation of first-type edges of a target signal for use with a digital pulse-width modulator in a digital feedback loop of a switched-mode power supply, and a main control circuitry configured to control operation of said delay-locked loop circuitry in a way that said delay-locked loop circuitry is turned on before generation of each first-type edge of said target signal and turned off after generation of each said first-type edge, wherein said delay-locked loop circuitry is configured to trigger generation of said first-type edges of said target signal at least partially based on a first clock signal, wherein said delay-locked loop circuitry comprises: a delay-locked loop configured to output a plurality of delayed representations of said first clock signal, and a combination circuitry configured to combine said plurality of delayed representations of said first clock signal into a signal via which said delay-locked loop circuitry triggers generation of said first-type edges of said target signal, wherein an operation of said combination circuitry is controlled by said main control circuitry, wherein said delay-locked loop comprises: a switch configured to receive a representation of said first clock signal; a line of delay elements connected to an output of said switch, wherein said delay elements in said line of delay elements generate said plurality of delayed representations of said first clock signal; a phase detector configured to control said delay elements based on a comparison of two different representations of said first clock signal, and a switch and phase detector control circuitry configured to control operation of said switch of said delay-locked loop and to turn on and off said phase detector of said delay-locked loop in response to at least one control signal generated by said main control circuitry.