Patent ID: 7947607

Claim:
A method for fabricating a virtual ground array device that uses inversion bit lines, the method comprising: forming a first diffusion region and a second diffusion region in a substrate; forming a polysilicon region over the substrate; patterning a dielectric layer and a polysilicon layer to form trenches that define a gate structure and that define regions for a first bit line and a second bit line, the regions defined for the first and second bit lines being near first and second implantation regions and separated from the substrate by a dielectric layer; forming the first and the second bit lines on the dielectric layer and in the regions defined by the trenches, such that each of the first and second bit lines form inversion bit lines in upper portions of the substrate adjacent the dielectric layer when an appropriate voltage is applied to the first bit line or the second bit line; and forming a word line in contact with the gate structure.