Patent ID: 7242559

Claim:
An input/output (I/O) circuit comprising: an NMOS transistor based electrostatic discharge (ESD) current bypass module with its source connected to a power supply node and its drain connected to a circuit pad; a high voltage tolerant charge module for disabling the ESD current bypass module when the circuit pad receives a voltage input higher than a reference voltage at the power supply node by charging a gate of the transistor to create a voltage difference between the gate and the drain, the high voltage tolerant charge module including a duality of MOS transistors connected in series with their gates coupled to the reference voltage, and a high voltage tolerant discharge module for disabling the NMOS transistor of the ESD current bypass module when the circuit pad receives a voltage input lower than the reference voltage, a gate of the NMOS transistor of the ESD current bypass module coupled to both the high voltage tolerant charge module and the high voltage tolerant discharge module, the duality of MOS transistors comprising a second NMOS transistor and a third PMOS transistor.