Patent ID: 7525512

Claim:
A method of testing and inspecting a plasma display panel in which a plurality of cells are formed at an intersection of each electrode disposed in a row direction and in a column direction, comprising: forming a field from a plurality of sub-fields, each subfield having an initializing period for producing an initial discharge, an address period for producing an address discharge with application of an address pulse voltage, and a discharge sustain period for producing a sustain discharge, and obtaining a gradation display using a combination of the plurality of sub-fields that are responsible for turning on the plurality of cells, wherein, the address pulse voltage is not applied to a target cell in a predetermined sub-field to be tested and inspected, but is applied to at least one specific cell of adjacent cells positioned adjacent to the target cell, and the address pulse voltage is applied to the target cell in a successive sub-field, and it is judged whether the target cell in the successive sub-field is on or not.