Patent ID: 7088197

Claim:
An adaptive power control interface for providing a variable voltage output to a digital system operating with a system clock frequency signal, comprising in combination: a first feedback loop including an analog reference voltage and means including a first voltage controlled oscillator for comparing said system clock frequency signal to said analog voltage reference to generate a first binary output signal from said first voltage controlled oscillator, a second feedback loop including a second voltage controlled oscillator for comparing said system clock frequency signal to said variable voltage output to generate a second binary output signal from said second voltage controlled oscillator; a first counter coupled to the first binary output signal of said first voltage controlled oscillator and a second counter coupled to the second binary output signal of said second voltage controlled oscillator; algebraic summing means to periodically sum a count in said first counter and a count in said second counter to generate a digital control word that represents the difference of the two sums; and control means responsive to said control word for controlling said variable output voltage.