Patent ID: 7196424

Claim:
A semiconductor device with a packaging circuit portion connected to a semiconductor chip, wherein the semiconductor chip includes a plurality of pad electrodes; the packaging circuit portion includes: wiring connected to the pad electrodes on the semiconductor chip; a plurality of mounting terminals; and a first signal path for receiving a signal output from a predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes; said semiconductor device includes a second signal path from a predetermined one of the mounting terminals to other one of the mounting terminal via the semiconductor chip, and the first signal path includes delay elements comparable to a delay in a first portion of the second signal path from the predetermined mounting terminal to one of the pad electrodes for input on the semiconductor chip and a delay in a second portion of the second signal path from one of the pad electrodes for output on the semiconductor chip to other one of the mounting terminals, and is disposed on a feedback path for phase comparison for synchronizing a phase of an output signal from the second signal path to a phase of an input signal to the second signal path, the second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip.