Patent ID: 7958413

Claim:
A method for reducing data reporting during memory testing, the method comprising: storing an address of a first failed memory location in a first failed memory location storage device when the first failed memory location is unique; comparing an address of a second failed memory location with the address stored in the first failed memory location storage device; continuing memory testing without reporting the second failed memory location when the address of the second failed memory location matches the address stored in the first failed memory location storage device, if the address stored in the first failed memory location storage device has been matched for more than a predetermined number of times; when the address of the second failed memory location matches the address stored in the first failed memory location storage device, storing the second failed memory location in a second failed memory location storage device; and when the second failed memory location is stored in the second failed memory location storage device, indicating that the address stored in the first failed memory location storage device is matched one more time.