Patent ID: 7960825

Claim:
A chip package comprising: ball-grid-array (BGA) substrate; a semiconductor chip over said ball-grid-array substrate, wherein said semiconductor chip comprises a semiconductor substrate, a MOS device in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a circuit structure over said first dielectric layer, wherein said circuit structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said MOS device, over said first and second dielectric layers and over said circuit structure, wherein said passivation layer comprises a nitride layer, wherein an opening in said passivation layer is over a contact point of said circuit structure, and said contact point is at a bottom of said opening, and a wirebonding pad over said semiconductor substrate, wherein said wirebonding pad is connected to said contact point through said opening, wherein said wirebonding pad comprises a copper layer; a glue material between said ball-grid-array substrate and said semiconductor chip, wherein said glue material contacts said ball-grid-array substrate and said semiconductor substrate; a wire bonded to said wirebonding pad and to said ball-grid-array substrate; a polymer material over said ball-grid-array substrate and over said passivation layer, wherein said polymer material encloses said wire; and a lead-free solder ball on said ball-grid-array substrate, wherein said lead-free solder ball comprises tin.