Patent ID: 8502236

Claim:
An insulated gate field effect transistor, comprising: a substrate of first conductive type, said substrate being made of silicon carbide and having a main surface with an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a reverse breakdown voltage holding layer of said first conductive type, said reverse breakdown voltage holding layer being made of silicon carbide and being formed on said main surface of said substrate; a well region of second conductive type different from said first conductive type, said well region being formed in said reverse breakdown voltage holding layer distant away from a first main surface thereof, said first main surface being a main surface adjacent to said substrate; an oxide film formed on said well region and made of oxide; a first conductive type contact region disposed between said well region and said oxide film and including an impurity of said first conductive type at a concentration higher than that of said reverse breakdown voltage holding layer; a channel region disposed between said well region and said oxide film in contact with said well region and said oxide film, connecting said first conductive type contact region and said reverse breakdown voltage holding layer to each other, and being of said first conductive type by including an impurity of said first conductive type at a concentration lower than that of said first conductive type contact region; and an electrode disposed on said oxide film, in a region including an interface between said channel region and said oxide film, a high-concentration nitrogen region being formed to have a nitrogen concentration higher than those of said channel region and said oxide film, wherein a nitrogen concentration in a region distant away by 10 nm or shorter from said interface between said channel region and said oxide film has a maximum value of not less than 1×10 21 cm −3 .