Patent ID: 8412906

Claim:
A memory apparatus comprising: an input to receive width selection information; an interface to exchange data with a remote device; a plurality of memory subsections, each subsection including columns of memory cells coupled to corresponding sense amplifiers; and routing coupling the memory subsections with the interface, the routing supporting first and second width configurations responsive to the width selection information; wherein in the first width configuration, the routing conveys data of a first data width between a first integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a first memory depth, and in the second width configuration, the routing conveys data of a second data width between a second integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a second memory depth; wherein the memory apparatus loads the sense amplifiers in the first number of the memory subsections for read operations in the first width configuration and loads the sense amplifiers in the second number of memory subsections for read operations in the second width configuration.