Patent ID: 7152131

Claim:
A data processor comprising: a master circuit which issues an access request; a slave circuit which performs processing in response to the access request, and supports a predetermined data size which is not supported by the master circuit; an intermediate circuit which converts an access size regarding the access request; a first data bus; a second data bus; a first address bus; and a second address bus, wherein the intermediate circuit comprises: access size control unit and a buffer unit comprising a first data buffer, a second data buffer, a first address buffer, and a second address buffer, a data selector, and an address selector; wherein the first data buffer comprises a lower data buffer and an upper data buffer; wherein the data selector selects either the first data buffer or the second data buffer from which data is output to the second data bus; wherein the address selector selects either the first address buffer or the second address buffer from which address is output to the second address bus; wherein a maximum access size of the master circuit is n bit; wherein a maximum access size of the slave circuit is 2n bit or more: wherein the lower data buffer and the upper data buffer stores n bit data, which are transferred from the master circuit throuah the first data bus, respectively; wherein the first address buffer stores a first address, which is transferred from the master circuit through the first data bus; wherein, when the access size control unit detects that a second address issued from the master circuit is the same as a predetermined address which is distinct from the first address after the lower data buffer and the upper data buffer store n bit data respectively and the first address buffer stores a first access address, the access size control unit outputs a signal; and wherein the data selector outputs the data from the first data buffer to the second data bus and the address selector outputs the first address buffer to the second address buffer when the data selector and the address selector receive the signal.