Patent ID: 8207610

Claim:
A semiconductor device having a multilayer interconnection structure, said multilayer interconnection structure comprising at least a first interconnection layer and a second interconnection layer formed over said first interconnection layer; said first interconnection layer comprising a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern in said first interconnection layer, and a second conductor pattern different from the first conductor pattern embedded in said first interlayer insulation film, said second interconnection layer comprising a third conductor pattern embedded in a second interlayer insulation film and constituting a part of an interconnection pattern in said second interconnection layer, said third conductor pattern being coupled to an extension part in a part thereof so as to extend in said second interlayer insulation film in a plane of said second interlayer insulation film, said extension part extending from an edge of said third conductor pattern and having a width smaller than a length of said edge when viewed from a direction perpendicular to said plane of said second interlayer insulation film, said third conductor pattern being electrically connected to said first conductor pattern at a first region of said extension part via a first via plug, said extension part making a contact with said second conductor pattern at a second region further away from said third conductor pattern with regard to said first region via a second via-plug of a diameter smaller than said first via-plug, said extension part of said third conductor pattern, said first via-plug and said second via-plug forming, together with said second interlayer insulation film, a dual damascene structure.