Patent ID: 8595683

Claim:
An apparatus for generating a user clock in a prototyping system, comprising: a clock generation circuit to generate a clock signal having a reference frequency; a plurality of programmable logic devices, wherein a first of the programmable logic devices is electrically connected to the clock generation circuit to receive the clock signal having the reference frequency from the clock generation circuit, comprising: a reset circuit to receive the clock signal having the reference frequency and to generate a reset signal to synchronize a frequency of the user clock across the plurality of programmable logic devices; a multiplier circuit to receive the clock signal having the reference frequency, wherein the multiplier circuit multiplies the clock signal having the reference frequency by a first value to generate a clock signal having a multiplied frequency; and a divider circuit to receive the reset signal from the reset circuit and to receive the clock signal having a multiplied frequency from the multiplier circuit, wherein the divider circuit is configured to divide the clock signal having the multiplied frequency by a second value to generate the user clock signal having the synchronized user clock frequency; and interconnect electrically connecting the first programmable logic device to the clock generation circuit.