Patent ID: 7358148

Claim:
A method for forming an air gap between a pair of interconnects on an interconnect level of a semiconductor device comprising: depositing a plurality of insulative layers of a semiconductor device; depositing a first hardmask insulative layer over the plurality of insulative layers; removing portions of the first hardmask insulative layer to expose regions of the uppermost of the plurality of insulative layers over which interconnects are to be formed, the regions of over which interconnects are to be formed being spaced apart; depositing a second hardmask insulative layer over the first hardmask layer and exposed regions of the uppermost of the plurality of insulative layers; removing portions of the second hardmask insulative layer over the first hardmask insulative layer to expose regions of the uppermost of the plurality of insulative layers over which interconnects are to be formed, leaving second hardmask spacers adjacent to the regions of the uppermost of the plurality of insulative layers over which interconnects are to be formed; using the first hardmask insulative layer and second hardmask spacers to etch the at least one of the underlying plurality of insulative layers to form interconnect openings; depositing a conformal insulative layer to form spacers on sidewalls of the interconnect openings; depositing conductive metal adjacent the conformal insulative layer spacers to form interconnects in the interconnect openings; etching portions of the first hardmask insulative layer and underlying plurality of insulative layers between the interconnects and conformal insulative layer spacers, and leaving second hardmask spacers adjacent to the interconnects and conformal insulative layer spacers, to form an air gap extending below at least one of the interconnects; depositing at least one insulative layer over the air gap and over the interconnects and conformal insulative layer spacers to seal the air gap.