Patent ID: 7202714

Claim:
A replica delay circuit configured for use in an internal clock generator, the replica delay circuit receiving an external clock signal and outputting an internal clock, and comprising: a circuit configured to synchronize a phase difference between the external clock signal and a reference clock signal, wherein the internal clock signal is derived in relation to the phases difference; a first replica delay unit, delaying the internal clock signal for a predetermined period of time and generating first delay clock signals; and a second replica delay unit, generating the reference clock signal in response to the first delay clock signals and changing a duty cycle of the reference clock signal in response to selected control signals, wherein the second replica delay unit comprises: a first amplifier generating second delay clock signals in response to the first delay clock signals and changing a common mode voltage level for the second delay clock signals in response to the selected control signals; and a second amplifier, comparing voltage levels for the second delay clock signals, outputting the reference clock signal in accordance with a comparison result, and changing the duty cycle of the reference clock signal in accordance with changes in the common mode voltage level of the second delay clock signals.