Patent ID: 8416856

Claim:
A circuit for computing sums of absolute difference, comprising: an absolute difference circuit, for receiving a first data PM i,j and a second data PS i,j , and outputting an absolute difference data AD i,j , wherein PM i,j PS i,j and AD i,j represent a (i,j) data of the first data, the second data and the absolute difference data, respectively, and wherein AD i,j =|PM i,j −PS i,j |, and i and j are integers not less than 0; a first selective circuit, for selecting the absolute difference data, a second sum of absolute difference data or a zero data, and outputting the selected one of the absolute difference data, the second sum of absolute difference data and the zero data as a first accumulative data according to a first preset timing sequence, wherein a value of the zero data is 0; a first adder, for receiving and adding the first accumulative data and a second accumulative data, and outputting a first sum; a first register, for receiving and locking the first sum according to a second preset timing sequence, and outputting a first sum of absolute difference data; a second selective circuit, for selecting the first sum of absolute difference data or the zero data, and outputting the selected one of the first sum of absolute difference data and the zero data as the second accumulative data; and a second register, for receiving and locking the first sum according to a third preset timing sequence, and outputting the second sum of absolute difference data.