Patent ID: 8762620

Claim:
A storage system comprising: a first and a second flash memory groups, each group comprising a plurality of flash memory devices; a storage controller including a plurality of groups of processors, each processor group comprising one or more processors for handling a different stage of a pipelined execution of host storage commands, the processor groups including: a host interface circuit coupled to receive a first host command from a first host through a host interface and a second host command from a second host through the host interface, the host interface circuit including: a first processor of the host interface circuit operably connected to one or more buffers that hold information received through the host interface, the first processor of the host interface circuit including software or hardware control disposed to format such information for use by downstream elements of the storage system; and a second processor of the host interface circuit operably connected to one or more buffers that hold information received from other storage system elements, the second processor of the host interface circuit including software or hardware control disposed to format such information for transmission through the host interface; a first processor group of the plurality of groups of processors including a first processor of the first processor group and a second processor of the first processor group, the first processor of the first processor group associated with the first flash memory group and the second processor of the first processor group associated with the second flash memory group, each such processor configured for controlling at least some operations of the flash memory group associated therewith; and a command processing circuit configured to provide the first host command to the first processor of the first processor group and the second host command to the second processor of the first processor group, the first flash memory group being configured to carry out, under control of the first processor of the first processor group, flash read or write operations relating to the first host command and the second flash memory group being configured to carry out, under control of the second processor of the first processor group, flash read or write operations relating to the second host command, the storage controller configured to cause the first and second host commands to be carried out substantially simultaneously.