Patent ID: 7133954

Claim:
A data bus system that has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry, the data bus system comprising: an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit, wherein the CPU is connected to an external access bus and an internal access bus: the internal memory unit is connected to the external access bus, the internal access bus and a test bus: the I/O unit is connected to the external access bus, the internal access bus and the test bus; the periphery circuitry is connected only to the internal access bus; the internal access bus is connected to the external access bus with a latch; and the data bus system can access all of an internal/external memory, an external porter and internal periphery circuits, and can also access an internal memory test mode using a read only internal memory test bus.