Patent ID: 8693268

Claim:
A semiconductor device comprising: a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation; a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell; a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation when the first voltage is less than the predetermined voltage at an end of the first period; a control circuit that generates a mode signal, the signal being activated during the first period and being deactivated during the second period; a first switch circuit that is coupled between a node of the charge pump circuit and the first memory cell, and that operates in response to the mode signal; and a second switch circuit that is coupled between the node of the charge pump circuit and the second memory cell, and that operates in response to the mode signal.