Patent ID: 7545163

Claim:
A motor system, comprising: a 3-phase DC motor having first, second and third phase windings; a drive circuit to selectively effect energization of the first, second and third phase windings during motor operation; a diagnostic and phase feedback circuit connected to indicate, during non-operation of the motor, at least a no fault state, a first fault state and a second fault state, the diagnostic circuit having one diagnostic output line at which (i) a no fault analog voltage condition is established during the no fault state, (ii) a first fault analog voltage condition is established during the first fault state and (iii) a second fault analog voltage condition is established during the second fault state, each of the voltage conditions distinct from each other; and a controller having an A/D converter operatively connected with the one diagnostic output line, wherein the controller monitors an output of the A/D converter to identify the presence of each of the no fault state, the first fault state and the second fault state; wherein the first fault voltage condition is indicative of either a motor disconnected fault or a first phase open fault, wherein the second fault voltage condition is indicative of either a second phase open fault or a third phase open fault; wherein the diagnostic and feedback circuit includes a first line associated with the first phase winding and operatively connected with the diagnostic output line, a second line associated with the second phase winding and operatively connected with the diagnostic output line and a third line associated with the third phase winding and operatively connected with the diagnostic output line, a first transistor connected between the first line and ground, a second transistor connected between the second line and ground and a third transistor connected between the third line and ground, the first, second and third transistors are normally maintained in respective OFF states during diagnostic monitoring when the motor is not operating; and wherein the controller is operatively connected to control the ON/OFF state of each of the first, second and third transistors, the controller upon identification of the first fault state selectively turns on each of the transistors for supplemental diagnostic evaluation.