Patent ID: 8773210

Claim:
A relaxation oscillator for generating an output clock signal, comprising: a resistor-capacitor (RC) circuit for generating first and second comparator input signals; a bias generation stage for generating first and second bias voltages, including: a reference voltage generator for generating the reference voltage using a supply voltage; a first transistor having a source terminal for receiving the supply voltage; a second transistor having a source terminal connected to a drain terminal of the first transistor, a gate terminal for receiving the reference voltage, and a drain terminal connected to a gate terminal of the first transistor for generating the first bias voltage; a third transistor having a drain terminal connected to the drain terminal of the second transistor, and a gate terminal for receiving the reference voltage; a first resistor having a first terminal connected to a source terminal of the third transistor and a second terminal connected to ground; a second resistor having a first terminal for receiving the supply voltage; a fourth transistor having a source terminal connected to a second terminal of the second resistor, a gate terminal for receiving the reference voltage, and a drain terminal for generating the second bias voltage; a fifth transistor having a drain terminal connected to the drain terminal of the fourth transistor, and a gate terminal for receiving the reference voltage; and a sixth transistor having a drain terminal connected to a source terminal of the fifth transistor, a gate terminal connected to the drain terminals of the fourth and fifth transistors, and a source terminal connected to ground; a first comparator stage, connected to the RC circuit and the bias generation stage, for receiving the first comparator input signal and the first and second bias voltages and generating a first comparator output signal; a second comparator stage, connected to the RC circuit and the bias generation stage, for receiving the second comparator input signal and the first and second bias voltages and generating a second comparator output signal; and a logic circuit that receives the first and second comparator output signals and generates a first intermediate signal and the output clock signal.