Patent ID: 7324367

Claim:
A memory device having an address bus and a data terminal, comprising: an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line; a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus; a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises: an active region formed in the substrate; a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions; a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts; a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.