Patent ID: 7679106

Claim:
A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell comprising: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines so as to be adjacent to the second diffused regions of the n-type MOS transistor, the fourth gate electrodes being connected to ground wiring so as to turn off the dummy n-type MOS transistors, wherein an absolute value of threshold voltage of the dummy p-type MOS transistor is higher than an absolute value of threshold voltage of the p-type MOS transistor, and an absolute value of threshold voltage of the dummy n-type MOS transistor is higher than an absolute value of threshold voltage of the n-type MOS transistor.