Patent ID: 8701063

Claim:
A computer-implemented method for reducing number of scenarios analyzed for an electronic circuit, the method comprising: receiving a plurality of scenarios for an electronic circuit, each scenario corresponding to a mode and a corner; grouping the scenarios into one or more groups of scenarios, each scenario from a group of scenarios corresponding to a particular mode; for each group of scenarios: selecting a winner scenario based on violations of scenarios of the group; identifying violations that are not covered by the winner scenario but are covered by at least one other scenario; and modifying, by a computer, the winner scenario by adjusting required times of timing nodes in the winner scenario so as to introduce violations in the winner scenario corresponding to the identified violations, wherein adjusting a required time of a timing node of the winner scenario comprises reducing the required time of the timing node by a margin, wherein the margin by which the required time of the timing node is reduced comprises a difference between a slack of the timing node in the winner scenario and a slack of the timing node from the other scenario scaled by a factor; and storing the modified winner scenarios for each group.