Patent ID: 6952115

Claim:
A programmable logic device (PLD), comprising a logic core connected to an input/output (I/O) interface, the I/O interface comprising one or more programmable I/O buffers (PIBs), wherein: at least one PIB can be programmed to perform three or more of: (a) a double data rate (DDR) input mode in which an incoming DDR data signal is converted into two single data rate (SDR) data signals that are made available to the logic core; (b) one or more demux input modes, different from the DDR input mode, in which an incoming data signal is demultiplexed into two or more lower-rate data signals that are made available to the logic core; (c) one or more DDR demux input modes in which an incoming DDR data signal is converted into four or more lower-rate SDR data signals that are made available to the logic core; and (d) one or more additional input modes in which an incoming data signal is made available to the logic core without any demultiplexing or DDR-to-SDR conversion; and the at least one PIB can be programmed to perform three or more of: (a) a DDR output mode in which two SDR data signals from the logic core are converted into a single outgoing DDR data signal; (b) one or more mux output modes, different from the DDR output mode in which two or more data signals from the logic core are multiplexed into a single, higher-rate, outgoing data signal; (c) one or more DDR mux output modes in which four or more SDR data signals from the logic core are converted into a single, higher-rate, outgoing DDR data signal; and (d) one or more additional output modes in which a data signal from the logic core is provided as an outgoing data signal without any multiplexing or SDR-to-DDR conversion.