Patent ID: 7395412

Claim:
An apparatus, for extending data modes within a microprocessor, the apparatus comprising: a translation unit translates an extended instruction stored in a computer readable storage into corresponding micro instructions executed by the microprocessor, wherein said extended instruction comprises: an extended prefix, for specifying an extended operand size for an operand corresponding to an operation that is prescribed by said extended instruction, wherein said extended operand size cannot be specified by an existing instruction set; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified opcode within said existing instruction set; wherein said translation unit comprises: an escape instruction detection unit, for detecting said extended prefix tag; an instruction decoding unit, for determining said operand along with said operation to be performed; and an extended decoding unit, coupled to said escape instruction detection unit and said instruction decoding unit, for determining said extended operand size, and for prescribing said extended operand size within said corresponding micro instructions, and an extended execution unit, coupled to said translation unit, receiving said corresponding micro instructions, and executing said operation using said operand according to said specified extended operand size for an operand.