Patent ID: 7796453

Claim:
A semiconductor device comprising: a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that controls connection and disconnection between the data I/O line pair and the data amplifier; an I/O line precharge circuit that precharges a first portion of the data I/O line pair, wherein the first portion of the data I/O line pair is separated by the data I/O line switch and located not on the side of the data amplifier; an amplifier precharge circuit that precharges a second portion of the data I/O line pair, the second portion of the data I/O line pair is separated by the data I/O line switch and located on the side of the data amplifier; a column decoder that generates a column selecting signal that selects a bit line pair from among a plurality of bit line pairs to which memory cells are connected according to a column address that is input; and a bit line selecting switch that connects, according to the column selecting signal, the bit line pair of a plurality of the bit line pairs and a data I/O line pair that outputs data from a memory cell to the outside.