Patent ID: 8125045

Claim:
A dielectric isolation type semiconductor device including a dielectric isolation type substrate, said dielectric isolation type substrate comprising: a support substrate; an embedded dielectric layer formed on an entire area of a first principal plane of said support substrate; and a semiconductor substrate of a first conductive type having a low impurity concentration being laminated on said support substrate through said embedded dielectric layer; wherein said semiconductor substrate comprises: a first semiconductor region of a first conductive type having a high impurity concentration that is selectively formed; a second semiconductor region of a second conductive type having a high impurity concentration that is arranged so as to surround said first semiconductor region in a manner spaced a predetermined distance from an outer peripheral edge thereof; a first main electrode that is joined to a surface of said first semiconductor region; and a second main electrode that is joined to a surface of said second semiconductor region; wherein said support substrate comprises: a through hole that is formed at a location containing therein a region that is superposed on said first semiconductor region in the direction of lamination thereof; a second dielectric portion that arranged in contact with a region of said embedded dielectric layer that appears in an opening of said through hole and is arranged; a rear surface electrode that is arranged in contact with the region of said embedded dielectric layer that appears in the opening of said through hole, a side wall of said through hole, said second dielectric portion, and a rear surface of said support substrate; and a first solder that fills a space enclosed by the region of said embedded dielectric layer that appears in the opening of said through hole, the side wall of said through hole and said second dielectric portion so as to make said space flat.