Patent ID: 8106441

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a first MISFET arranged at a first region of the main surface, the first region comprising an analog circuit forming region of the main surface, the first MISFET including a source region and a drain region each formed in the semiconductor substrate and a gate insulating film formed on the semiconductor substrate; a second MISFET arranged at a second region of the main surface, the second region being a different region from the first region, the second MISFET including a source region and a drain region each formed in the semiconductor substrate and a gate insulating film formed on the semiconductor substrate; a first capacitor element having a lower electrode, a first insulating film formed on the lower electrode, and a higher electrode formed on the first insulating film, the higher electrode being formed over the semiconductor substrate, the first capacitor element being arranged at the second region and electrically coupled to a power supply; a second insulating film formed over the first MISFET, the second MISFET and the first capacitor element; and a second capacitor element arranged at the first region and formed over the second insulating film, the second capacitor element having a lower electrode formed over the second insulating film, a third insulating film formed on the lower electrode, and a higher electrode formed on the third insulating film.