Patent ID: 7898307

Claim:
A phase-locked loop frequency synthesizer comprising: phase detector circuitry; and divider circuitry configured to produce a divided signal, the phase detector circuitry comprising: a reference input configured to receive a reference signal; a feedback input configured to receive the divided signal from the divider circuitry in a feedback path of the phase-locked loop; and pulse generation circuitry configured to generate control pulses for controlling a charge pump in the phase-locked loop in accordance with a frequency and phase relationship between the reference signal and the divided signal; wherein the divided signal comprises a pulse having a length shorter than a half period of the divided signal, and wherein the pulse generation circuitry is configured to generate the control pulses by masking the reference signal using the pulse of the divided signal as a mask, such that the edges of the control pulses correspond to the edges of the divided signal and an edge of the reference signal; the divider circuitry comprising: a main divider configured to divide an input signal received from the feedback path of the phase-locked loop by a division ratio selected from a pair of dual modulus division ratios in accordance with a dual modulus selection signal, and to output the divided input signal as an output signal, the main divider comprising a control input for receiving the dual modulus selection signal; and an auxiliary divider comprising a shift register clocked by the output signal on the main divider, the shift register comprising a parallel input configured to receive parallel input data in the form of a fraction selection signal at the start of a cycle, and a serial output connected to the control input of the main divider, the auxiliary divider being configured to produce serial output data, each bit of which serves as a said dual modulus selection signal to cause the main divider to operate using one or the other of the pair of dual modulus main division ratios, wherein the auxiliary divider is configured to produce the divided signal which comprises the pulse once per cycle and to output the pulse to the phase detector circuitry.