Patent ID: 8842034

Claim:
A resistor network implemented in an integrated circuit, the resistor network comprising: a plurality of metal layers; a first plurality of interconnect traces coupled in series at a first plurality of nodes, wherein each interconnect trace of the first plurality of interconnect traces is formed in a metal layer of the plurality of metal layers and has a selected resistance based on a size of the interconnect trace; a first plurality of switches coupled between the first plurality of nodes and an output node; a second plurality of interconnect traces coupled in series at a second plurality of nodes, wherein each interconnect trace of second first plurality of interconnect traces is formed in a metal layer of the plurality of metal layers and has a selected resistance based upon a size of the interconnect trace; and a second plurality of switches coupled between the second plurality of nodes and the output node; wherein a voltage at the output node is generated in response to a resistance of the resistor network based upon a configuration of the first plurality of switches and the second plurality of switches.