Patent ID: 8754416

Claim:
An active matrix thin film transistor array, comprising: an interconnection cross-over including two levels of metallic interconnections of the same metal and an inter-level insulator between the two levels of metallic interconnections; a plurality of thin film transistors, each thin film transistor of the plurality of thin film transistors comprising: a channel; a source region comprising a metal portion, the metal portion being of the same metal as the metallic interconnections, and a semiconductor portion doped with impurities, wherein the metal portion of the source region contacts a metallic source interconnection at a first interface, the metal portion of the source region contacts the semiconductor portion of the source region at a second interface, and the semiconductor portion of the source region contacts the channel at a third interface; and a drain region comprising a metal portion, the metal portion being of the same metal as the metallic interconnections, and a semiconductor portion doped with impurities, wherein the metal portion of the drain region contacts a metallic drain interconnection at a fourth interface, the metal portion of the drain region contacts the semiconductor portion of the drain region at a fifth interface, and the semiconductor portion of the drain region contacts the channel at a sixth interface; and polycrystalline silicon pixel electrodes.