Patent ID: 7681066

Claim:
A system comprising: a first processor core comprising a first circuit to generate a first data, wherein the first data is associated with a generated oscillation frequency of the first circuit; a second processor core comprising a second circuit to generate a second data, wherein the second data is associated with a generated oscillation frequency of the second circuit; a database comprising: a first reliability level assigned to the first processor core, the first reliability level associated with a case when a percentage difference between a stored initial oscillation frequency of the first circuit and the generated oscillation frequency of the first circuit is greater than a first reliability percentage, and a second reliability level assigned to the second processor core, the second reliability level associated with a case when a second percentage difference between a stored initial oscillation frequency of the second circuit and the generated oscillation frequency of the second circuit is greater than a second reliability percentage; and a processor core assignor to assign an application to the first processor core in a case that the first reliability level is equal to an application reliability requirement associated with the application.