Patent ID: 7825396

Claim:
A memory device, comprising: a substrate body having an array of contacts, the substrate body having a top surface; and a plurality of memory cells on the array of contacts, a memory cell in the plurality of memory cells including a first electrode member on the top surface of the substrate body and having a bottom surface contacting one of the contacts in the array of contacts, the first electrode having a substantially planar top surface; a second electrode member having an electrode surface spaced away from the top surface of the first electrode; an insulating spacer material over the first electrode member, the insulating spacer material defining a single pore between the top surface of the first electrode and the electrode surface of the second electrode, the pore having a width less than that of the top surface of the first electrode member; a memory element having sides and including programmable resistive memory material within the pore, and electrically coupled to the top surface of the first electrode and the electrode surface of the second electrode; and wherein the first and second electrode members have respective sides, and wherein the sides of the second electrode member are in alignment with the sides of the first electrode member, and wherein the memory element is isolated from memory elements of adjacent memory cells in the plurality of memory cells.