Patent ID: 7308660

Claim:
A calculation system of fault coverage comprising: a data acquiring module configured to acquire layout information and gate net data of an LSI; a layout analysis and fault link module configured to analyze a condition of connection of an input terminal and an output terminal of a basic cell regarding an entire layout based on the layout information and the gate net data, to extract the result of the analysis as layout element information, and to generate an undetected fault list; a fault detecting module configured to execute any of fault simulation and an automatic test pattern generation on the undetected fault list and to generate a detected and undetected fault list; and a weight calculating module configured to add the layout element information, which includes a path between the output terminal of the basic cell, of which the output terminal is connected, to a gate net included in the gate net data and the input terminal of the basic cell, of which the input terminal is connected, to the gate net, corresponding to a fault in the detected and undetected fault list as weight to a stuck-at fault assumed to the input terminal, based on a link file between faults and layout element information to be generated based on the layout information, the gate net data, and the detected and undetected fault list by the layout analysis and fault link module.