Patent ID: 8069024

Claim:
A computer-implemented method comprising: partitioning, using a processor, a circuit description into a plurality of simulateable partitions; sorting, using the processor, the plurality of simulateable partitions into one or more classes wherein each simulateable partition included in a given class is equivalent to each other partition in the given class within a specified tolerance; associating, using the processor, a dynamic state machine with each class, wherein one or more states of the dynamic state machine associated with a given class correspond to states reached by at least one simulateable partition in the given class during a simulation; during a simulation of the circuit description, result of which is stored for user review: responsive to a current state in the dynamic state machine for a first simulateable partition in the given class and further responsive to one or more input stimuli to the first simulateable partition, matching, using the processor, the one or more input stimuli to stimuli associated with a next state edge from the current state; changing, using the processor, the current state of the first simulateable partition to a second state of the dynamic state machine indicated by the next state edge; detecting, using the processor, that the first simulateable partition has reached a quiescent state; determining, using the processor, that one or more states visited by the first simulateable partition to reach the quiescent state differ from the quiescent state by less than a defined tolerance; and inserting, using the processor, one or more new next state edges in the dynamic state machine to bypass the one or more states, wherein each new next state edge has a change in time parameter of zero.