Patent ID: 7983891

Claim:
A computer-implemented method for determining a worst-case transition comprising: determining a first output timing event at an output of a gate for a first input timing event at an input of the gate based at least in part upon a timing model of the gate; determining a second output timing event at the output of the gate for a second input timing event at the input of the gate based at least in part upon the timing model of the gate; selecting, by using a processor, the first input timing event corresponding to the first output timing event as a worst case timing event if the first output timing event has a later arrival time of transitions at the output of the gate than the second output timing event and selecting the second input timing event corresponding to the second output timing event as the worst case timing event if the second output timing event has the later arrival time of the transitions at the output of the gate than the first output timing event such that one of a plurality of timing events propagated to the input of the gate with a worst output slew or output delay as a function of input slew at the output of the gate is selected as the worst case timing event; and storing information related to the worst-case timing event in a non-transitory computer readable medium.