Patent ID: 8218376

Claim:
A semiconductor static random-access memory operable in a normal operating mode and a retain-till-accessed (RTA) mode, comprising: a plurality of memory cells, arranged in rows and columns in at least one memory array block, each of the plurality of memory cells comprised of metal-oxide-semiconductor (MOS) array transistors, and disposed in a memory array region of an integrated circuit, each of the memory cells in a first memory array block biased in parallel between a first bias voltage node and a first power supply node; a first plurality of bias devices, disposed in the memory array region and associated with the first memory array block, each of the first plurality of bias devices having a conduction path connected in series with memory cells in its associated memory array block between a second power supply node and the first bias voltage node; and a first switch device, disposed outside of the memory array region of the integrated circuit, and having a conduction path connected between the second power supply node and the first bias voltage node, and having a control electrode receiving an RTA control signal so that the first switch device is turned on in the normal operating mode and turned off in the RTA mode.