Patent ID: 7136933

Claim:
An inter-processor communication system in which a plurality of processors are connected by a network, each processor of the plurality of processors including: a transmitting means for transmitting a packet to a destination processor of the plurality of processors for requesting address translation of a write address from a logical address to a physical address by the destination processor when transmitting transmission data to the destination processor, and for translating the logical address to a specific physical address to be used as a read address to read the transmission data from a memory; a means for translating a particular write address from a particular logical address to a particular physical address as requested in a particular packet that is received from a source processor of the plurality of processors; and a means for using the particular physical address that results from the address translation as a specific write address for writing particular transmission data received subsequent to said particular packet to a particular memory; wherein said transmitting means is configured to transmit said packet for requesting address translation to the destination processor before translating the logical address to the specific physical address to be used as the read address to read the transmission data from the memory.