Patent ID: 7033735

Claim:
A method for manufacturing a microelectronic structure comprising: forming a first patterned resist layer comprised of holes on a substrate; forming a water soluble negative resist layer on said first patterned resist layer that fills the holes in the first patterned layer; patternwise exposing said water soluble negative resist layer to selectively expose portions of said water soluble negative resist layer within and adjacent to selected holes in said first patterned resist layer; forming crosslinked plugs in exposed portions of said water soluble negative resist layer, said crosslinked plugs fill selected holes in said first patterned resist layer, and to form a thin crosslinked negative resist layer in unexposed regions of said water soluble negative resist layer adjacent to the first patterned resist layer; removing non-crosslinked regions of said water soluble negative resist layer to form a second patterned layer comprised of the crosslinked plugs and the thin crosslinked negative resist layer; and transferring the pattern in said second patterned layer into said substrate.