Patent ID: 7594061

Claim:
A mother-board, comprising: a chipset having a plurality of lanes, the lanes comprising lanes of a first group and lanes of a second group; a switch having a first switch circuit and a second switch circuit, wherein the switch receives a one-bit control signal having a digital first state or a digital second state and selectively turns on one of the first switch circuit and the second switch circuit in response to the control signal; a first graphics interface having M lanes, each of the M lanes comprising a transmitter and a receiver, wherein X lanes of the M lanes of the first graphics interface are permanently electrically connected to the lanes of the first group of the chip set, Y lanes of the first graphics interface are connected to the first switch circuit and selectively electrically connected to the lanes of the second group of the chipset through the first switch circuit when the control signal is in its first state to turn the first switch circuit on, and M, X, Y are positive integers, X and Y being smaller than M; and a second graphics interface having M lanes, each of the M lanes comprising a transmitter and a receiver, wherein X 1 lanes of the M lanes of the second graphics interface are connected to the second switch circuit and selectively electrically connected to the lanes of the second group of the chipset through the second switch circuit when the control signal is in its second state to turn the second switch circuit on, X 1 being a positive integer smaller than M.