Patent ID: 7087957

Claim:
A semiconductor device comprising: a compound semiconductor substrate; a channel layer provided on the compound semiconductor substrate; a buried layer provided on the channel layer; a first recess formed in the buried layer in an E-mode region; a second recess formed in the first recess in the E-mode region and another second recess formed in the buried layer in a D-mode region; and a gate electrode provided in the second recess in the E-mode region and another gate electrode provided in said another second recess in the D-mode region, wherein a distance between a surface of the buried layer and a bottom of the second recess in the E-mode region is shorter than another distance between another surface of the buried layer and a bottom of said another second recess in the D-mode region, and wherein a distance between the bottom of the second recess and the channel layer in the E-mode region is identical to another distance between the bottom of said another second recess and the channel layer in the D-mode region.