Patent ID: 8418110

Claim:
A method, executed on a processor, to design an integrated circuit, the method comprising: retrieving a netlist from a machine readable medium accessible by the processor, wherein the netlist includes at least a first net and a second net; obtaining a set of cell instances for the integrated circuit, including cell instances connected to the first net and cell instances connected to the second net; extracting, from the netlist, a first list of ports of the set of cell instances to be connected together in the first net; extracting from the netlist a second list of ports of the set of cell instances to be connected together in the second net; calculating port obscurity factors, including a first set of port obscurity factors for the first list of ports of the set of cell instances and a second set of port obscurity factors for the second list of ports of the set of cell instances, based, at least in part, on a number of routing tracks that are connectable to a particular port, by subtracting fractional shares of the routing tracks connectable to the particular port of a cell from a predetermined constant, wherein a calculation of a fractional share is inversely proportional to a number of ports of the cell that are connectable to a routing track; calculating, on the processor, a first routing priority based on the first set of port obscurity factors; calculating, on the processor, a second routing priority based on the second set of port obscurity factors; and storing information based on the first routing priority and the second routing priority on a computer usable medium.