Patent ID: 7793182

Claim:
An integrated circuit comprising: A. plural TAP domains, each domain having a TDI input terminal, a TDO output terminal, a TCK input terminal, a TMS input terminal, and a RCK output terminal; and B. a TAP domain selection circuit, the selection circuit having a separate set of outputs and at least one input for each TAP domain, each set including a TDI output connected to a TDI input terminal, a TDO input connected to a TDO output terminal, a TCK output connected to a TCK input terminal, a TMS output connected to a TMS input terminal, and a RCK input connected to a RCK output terminal, the selection circuit including an interface select circuit including: i. an instruction control bus input; ii. a TDO input lead coupled to the TDO output of each set; iii. an output enable 1 input lead; iv. a TDI/TDO or TDO lead; v. an I/O circuit having an input connected to the TDO input lead, a control input, and an output connected to the TDI/TDO or TDO lead; vi. a first buffer having an input connected to the TDO input lead, a control input, and an output connected to the TDI/TDO or TDO lead; vii. a first multiplexer having an input connected to the output enable 1 input lead, a control input connected to the instruction control bus input, and an output connected to the control input of the I/O circuit; and viii. a second multiplexer having an input connected to the output enable 1 input lead, a control input connected to the instruction control bus input, and an output connected to the control input of the first buffer.