Patent ID: 7002490

Claim:
A method of scrambling an unknown ternary signal with a known ternary signal, the known and unknown ternary signals being able to assume one of three states, comprising: inputting the unknown ternary signal to a first input of a scrambling ternary logic device; inputting the known ternary signal to a second input of the scrambling ternary logic device; the scrambling ternary logic device implementing a ternary logic function, sc, that satisfies the following equations: (1) A sc B=C, where A is the unknown signal, B is the known ternary signal and C is the output from the ternary logic device; (2) C sc B=A, if C and B were input to the ternary logic device; and (3) A sc C=B; if A and C were input to the ternary logic device; and outputting a scrambled ternary signal from an output of the scrambling ternary logic device.