Patent ID: 7312402

Claim:
A capacitor arrangement, comprising: a first and second mounting pad, each comprising a surface mount technology (SMT) pad; a first via disposed proximate, but separate from, the first mounting pad and coupled to the first mounting pad by a first conductor, the first via providing a pathway to a ground plane layer; a second via disposed proximate, but separate from, the second mounting pad and coupled to the second mounting pad by a second conductor, the second via providing a pathway to a power plane layer, the power plane layer being non-planar with the ground plane layer; and a first and second lead formed in the first and second via to connect the first conductor to the ground plane and to connect the second conductor to the power plane; wherein the first conductor is angled from the first mounting pad in a direction of the second via and the second conductor is angled from the second mounting pad in a direction of the first via, wherein a separation between the first via and the second via is reduced by the angling of the first and second conductor and the separation between the first via and the second via is configured to be substantially minimized irrespective of a separation between the first and second mounting pad.