Patent ID: 7419856

Claim:
A method of forming an integrated circuit device, comprising: forming a conductive layer on an integrated circuit substrate, the conductive layer extending from a cell region to a fuse region of the integrated circuit substrate; patterning the conductive layer to simultaneously form a plate electrode in the cell region and a buffer pattern in the fuse region; forming a first insulation layer on the plate electrode and the buffer pattern; forming a metal layer on the first insulation layer that extends from the cell region to the fuse region; patterning the metal layer to simultaneously form a metal wiring in the cell region of the integrated circuit substrate and a fuse pattern in the fuse region of the integrated circuit substrate; forming a second insulation layer on the metal wiring and the fuse pattern; forming a passivation layer on the second insulation layer; and etching the passivation layer and the second insulation layer in the fuse region of the integrated circuit substrate to form a window layer defining the fuse region.