Patent ID: 7986551

Claim:
A phase-change random access memory (PRAM) device, comprising: a register configured to sequentially generate a plurality of control pulses having respective active periods that do not coincide; a level control signal provider receiving a write loop signal indicating an n-th write loop, and providing a level control signal corresponding to the n-th write loop; a set controller sequentially receiving the control pulses and receiving the level control signal, generating a set control signal comprising a plurality of stages sequentially decreasing from a first voltage level to a second voltage level and varying the first voltage level or the second voltage level in response to the level control signal; and a write driver providing a set pulse where write data to be written in the PRAM device is set data, and providing a reset pulse where the write data is reset data, the set pulse comprising a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude, wherein the first or second current magnitude varies from one write loop to another.