Patent ID: 8306172

Claim:
An electronic device comprises: a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems, wherein one of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit; wherein the sampling logic comprises a plurality of data paths, each of the plurality of data paths to perform a resampling operation on a corresponding one of the multiple phase separated sampled outputs to produce a corresponding intermediate sampled outputs prior to performing a final sample of the corresponding intermediate sampled output at a single phase of the at least one clock signal to produce a corresponding sampled input data signal; and a cross-correlator to select a clock phase based on sampled input data signals provided by the plurality of data paths and to disable a subset of the plurality of data paths based on the selected clock phase.