Patent ID: 7472236

Claim:
A method for processing read requests in a data processing system having a memory control device with at least two mirrored memory ports, said method comprising: receiving a read request on a system interconnect by a memory access control module within a memory controller that generates and processes signals for reading and writing data from and to a system memory that employs memory mirroring in which a first set of memory modules is mirrored by a corresponding second set of memory modules, wherein said memory access control module controls reading and writing between said memory controller and said first and second sets of memory modules, wherein said memory controller includes a pair of port interface modules for respectively interfacing each of said pair of memory ports with said memory access control module, each of said pair of port interface modules includes a write request buffer for storing pending write requests received by said memory access control module; a read request buffer for storing pending read requests received by said memory access control module; a command generator module having arbitration logic for selecting a read or write request to be issued onto said memory bus from among a plurality of pending read and write requests stored within said read and write request buffers; and a conflict queue module for, in response to read and write requests being issued onto said memory bus, holding said issued read and write requests pending processing; coupling a memory bus having a pair of memory ports to said memory controller with said first and second set of memory modules; coupling a central data buffer to said memory bus, wherein said central data buffer stores data for pending read and write requests issued onto said memory bus; coupling an error detection module to said central data buffer, wherein said error detection module contains logic for detecting uncorrectable errors in data returned by execution of read requests; issuing said received read request by a read scheduler only to a specified one of said at least two mirrored of memory ports; and responsive to receiving an uncorrectable error signal from said error detection module indicating an unrecoverable error resulting from said read request issued to said one mirrored memory port, issuing said received read request to an alternate of said at least two mirrored memory ports prior to reporting a read request status to said read request buffer and holding the corresponding read request during said issuing of said read request to said alternate memory port prior to said reporting said read request status to said read request buffer.