Patent ID: 7647481

Claim:
A stacked register system for use in a processor, the system comprising: a stack of registers comprising a plurality of register banks, each register bank comprising at least one register, each register bank having a corresponding status value of ON or OFF; and a controller, the controller responsive to instructions operative to allocate a predetermined number of registers within the stack to one or more software functions, without assigning specific registers to corresponding instructions in the functions, the controller to selectively control the corresponding status value of one or more of the register banks, wherein the controller is responsive to register-allocating instructions by increasing a number of register banks that are assigned the corresponding status value of ON in response to at least one register-allocating instruction increasing a number of allocated registers, and by decreasing the number of register banks that have the corresponding status value of ON in response to at least one register-allocating instruction decreasing the number of allocated registers, wherein the controller assigns the corresponding status value of OFF to a particular register bank in response to a save/restore register stack pointer that moves outside the particular register bank.