Patent ID: 7057943

Claim:
A data output controller for a memory device, comprising: a first switching part turned on/off by an internal clock signal outputted from a DLL means and receiving a first pulse signal enabled during a predetermined time in synchronization with the internal clock signal; a latch part for latching the first pulse signal passing through the first switching part; a second switching part turned on/off by the internal clock signal and receiving a latch part output signal outputted from the latch part; a first decoding part for receiving the latch part output signal and a second switching part output signal outputted from the second switching part and performing an ‘AND’ operation of the received latch part output signal and the received second switching part output signal; a second decoding part for receiving a first decoding part output signal and the internal clock signal and performing an ‘AND’ operation of the received first decoding part output signal and the internal clock signal; a third decoding part for receiving the latch part output signal and the internal clock signal and performing an ‘AND’ operation of the received latch part output signal and the internal clock signal; a data output buffer unit controlled by the second decoding part output signal; and a data strobe signal buffer unit controlled by a third decoding part output signal.