Patent ID: 6875690

Claim:
A method of fabricating a semiconductor device comprising: forming conductive patterns by depositing a conductive layer and a capping layer on an insulating layer disposed on a semiconductor substrate; filling at least one space between at least two adjacent conductive patterns by depositing a first interlayer insulating layer in the at least one space; exposing a part of a sidewall of the capping layer by wet etching the first interlayer insulating layer without damaging the capping layer; forming a first spacer on an exposed part of the sidewall of the capping layer; forming a second interlayer insulating layer on the first interlayer insulating layer, the capping layer and the first spacer, and planarizing a top surface of the second interlayer insulating layer; forming a contact hole between the at least two adjacent conductive patterns, wherein the contact hole is self-aligned with the capping layer, by dry etching the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer; forming a second spacer in an innerwall of the contact hole; and forming a contact plug electrically connected to the semiconductor substrate by filling the contact hole with conductive material.