Patent ID: 6905964

Claim:
A method for fabricating self-aligned, copper metal barriers, in a dual damascene multi-layer copper wiring process, the method comprising the following steps: (a) providing a semiconductor substrate having a first insulator layer thereon; (b) forming a second insulator layer, an intermetal dielectric layer, over said first insulator layer; (c) forming a first set of trench and via openings in said second insulator layer; (d) forming a first set of copper metal interconnection lines, wiring, and contact vias filling said first set trench and via openings; (e) selectively deposited by atomic layer deposition a self-aligned, copper metal barrier on said first set of copper metal interconnection lines, wiring, and contact vias; (f) forming a third insulator layer, another intermetal dielectric layer, over said second insulator layer; (g) forming a second set of trench and via openings in said third insulator layer; (h) forming a second set of copper metal interconnection lines, wiring, and contact vias filling said second set trench and via openings, thus completing using dual damascene, the multi-layer copper wiring process.