Patent ID: 8675397

Claim:
A static random access memory (SRAM) cell comprising: first and second inverters cross-coupled for data storage, each inverter including a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices (PGs) configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of PGs for writing, wherein: each of the PU, PDs, and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the first and second inverters and a number of PGs in the at least two ports is greater than 1, a number of FinFETs in the SRAM cell is equal to or greater than 12; a first metal layer providing local interconnection to the first and second inverters, the first metal layer including: a first Vss line and a second Vss line; a Vdd line; a first constant voltage line and a second constant voltage line; and a first bit line and a second bit line, wherein the first and second Vss lines, the Vdd line, the first and second constant voltage lines, and the first and second bit lines are oriented in a first direction; a second metal layer formed over the first metal layer, the second metal layer including a first word line and a second word line oriented in a second direction that is different from the first direction, wherein the first word line is a write word line and the second word line is a read word line; and a read port for reading, wherein the read port is different than the at least two ports coupled with the plurality of PGs for writing, wherein the read port includes at least two PDs in parallel and at least two PGs in parallel.