Patent ID: 8847402

Claim:
A semiconductor device, comprising: a first wiring formed in a first wiring layer; a second wiring formed along the first wiring in the first wiring layer; a third wiring formed along the first and second wirings in a region between the first and second wirings of the first wiring layer; a projecting portion formed in a region between the first and second wirings of the first wiring layer and integrated into the first wiring; a fourth wiring formed in a second wiring layer, the fourth wiring intersecting with the first and second wirings and the projecting portion; a fifth wiring formed in the second wiring layer, the fifth wiring intersecting with the first, second, and third wirings; a first via group formed in an intersecting portion between the first wiring and the fourth wiring, the first via group coupling the first wiring and the fourth wiring; a second via group formed in an intersecting portion between the second wiring and the fifth wiring, the second via group coupling the second wiring and the fifth wiring; and a third via group formed in an intersecting portion between the projecting portion and the fourth wiring, the third via group coupling the projecting portion and the fourth wiring.