Patent ID: 7132337

Claim:
A method for producing charge-trapping memory devices, the method comprising: providing a semiconductor body having a main surface; arranging a gate electrode having opposite lateral edges above said main surface and forming an electrically insulating gate dielectric between said gate electrode and the semiconductor body; etching said gate dielectric to form recesses at opposite lateral edges of said gate electrode; applying a memory layer of dielectric material suitable for charge-trapping; removing said memory layer except for limited charge-trapping regions that are located in said recesses and that extend from said gate dielectric for a distance that is short of said lateral edges such that the outer limits of said charge-trapping regions are recessed with respect to said lateral edges; and forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in a self-aligned fashion with respect to said charge-trapping regions and wherein said introduction of said dopant comprises a process selected from the group consisting of gas phase doping, deposition of a doped layer followed by a thermal diffusion of the dopant, and plasma doping at low energy.