Patent ID: 8241999

Claim:
A semiconductor device comprising: a semiconductor substrate; a circuit element region formed on the semiconductor substrate; and a protective pattern formed so as to surround the circuit element region, the protective pattern comprising: a first element separation region formed on the semiconductor substrate; a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region; a first element region formed between the first element separation region and the second element separation region; a first gate layer formed on the first element separation region; a wiring layer formed on the first gate layer; a passivation layer formed above the wiring layer; a second element region; an insulation film formed on the second element region; and a second gate layer formed on the insulation film, wherein the first element separation region, the first element region, the second element separation region and the second element region are located in this order from the nearer side of the circuit element region.