Patent ID: 8339878

Claim:
An integrated circuit adapted to transmit a signal to an external destination via parallel signal lines, wherein the parallel signal lines include a first set of at least one of the parallel signal lines, and a second set of at least one of the parallel signal lines, the integrated circuit comprising: an output driver for each parallel signal line in the first set, each output driver for each parallel signal line in the first set operable to drive a respective bit of a first component of the signal onto the associated parallel signal line; an output driver for each parallel signal line in the second set, each output driver for each parallel signal line in the second set operable to drive a respective bit of a second component of the signal onto the associated parallel signal line; storage operable to store information representing at least two predefined phase control values; where the integrated circuit is operable to apply one of the at least two predefined phase control values to stagger the relative time of output of the first component of the signal relative to the second component of the signal.