Patent ID: 8644086

Claim:
A semiconductor device comprising: an external terminal; a plurality of first chips each of which includes a plurality of memory cells; a second chip that communicates with outside of the semiconductor device through the external terminal and controls the plurality of first chips; and a plurality of internal wirings coupled between the first chips and the second chip, wherein the plurality of first chips each communicates with the second chip through the plurality of internal wirings, the second chip includes a first fuse, and each of the first chips further includes: a second fuse; a first latch circuit that stores information in the second fuse; a second latch circuit that stores information in the first fuse supplied from the second chip through the internal wirings; a select circuit that selects one of the information stored in the first and second latch circuits; and a first control circuit that generates a redundancy determination signal based on the information selected by the select circuit.