Patent ID: 7285819

Claim:
A method of programming a storage cell in an array of storage cells, comprising: providing the array of storage cells, including a storage cell, the array comprising: a semiconductor layer; a first trench and a second trench spaced-apart from one another, wherein: each of the first trench and the second trench extends from a surface of the semiconductor layer; a portion of the semiconductor layer lies between the first and second trenches; and the portion of the semiconductor layer has a first wall immediately adjacent to the first trench and a second wall immediately adjacent to the second trench; a first control gate extending into the first trench; a first source/drain region underlying the first trench; a second source/drain region that: lies within the portion of the semiconductor layer and adjacent to the surface of the semiconductor layer, wherein the second source/drain region is spaced apart from the first wall, the second wall, or both the first and second walls; or underlies the second trench; a first set of discontinuous storage elements lying between the first control gate and the first wall of the portion of the semiconductor layer; and a second set of discontinuous storage elements lying between: the first control gate; and a part of the semiconductor layer at the surface of the portion of the semiconductor layer, wherein the part of the semiconductor layer lies outside the second source/drain region; and biasing the first source/drain region to a drain programming voltage (V PD ); biasing the second source/drain region to 0 V; and biasing the first control gate to a gate programming voltage (V PG ) to program a first bit of the storage cell by injecting charge into the first set of the discontinuous storage elements adjacent to the first wall of the portion of the semiconductor layer.