Patent ID: 7042874

Claim:
A digital switching system, comprising: multiplexing means for multiplexing time slots from a first plurality of circuits; switching memory means for storing and switching data of the time slots from the multiplexing means, for one frame period; switching control means including a switching correspondence means for directing interchange of the time slots stored in the switching memory means in response to a switching request from a network received through an upper layer controller; and demultiplexing means for demultiplexing into a second plurality of circuits, time slot data read out of the switching memory means using as addresses data from the switching correspondence means, the switching correspondence means comprising: information receiving means for receiving connection information from the upper layer controller; read-out controlling means for storing the connection information corresponding to before or after switching, received through the information receiving means, to addresses designated by the connection information in one of a first memory means and a second memory means, and for sequentially reading out the stored connection information in read-out order of the switching memory means; network switching control means for generating a switching signal in synchronization with an internal timing standard in response to the switching request provided by the upper layer controller; and read-out selection means for selecting read-out from one of the first memory means and the second memory means of the read-out controlling means in response to the switching signal provided by the network switching control means, wherein with respect to the read-out controlling means, the first memory means and the second memory means are each independently capable of simultaneously writing and reading.