Patent ID: 8604880

Claim:
An analog buffer circuit configured to substantially match an output impedance of an amplifier with an input impedance of a receiver, the circuit comprising: a primary transistor, the primary transistor having a first back gate terminal, a first source terminal, a first gate terminal, and a first drain terminal, the first source terminal being an output of the buffer circuit, the output being coupled to the receiver; a secondary transistor, the secondary transistor having a second back gate terminal, a second drain terminal, a second source terminal, and a second gate terminal, the secondary transistor configured to receive an input signal from the amplifier at the second gate terminal; wherein the first back gate terminal of the primary transistor is coupled to the second back gate terminal of the secondary transistor so that the second source terminal of the secondary transistor drives the first back gate terminal and responsively adjusts the transconductance of the primary transistor; wherein the second back gate terminal is coupled to the second source terminal and the first back gate terminal is not coupled to the first drain terminal; and further comprising a high pass filter coupled between the first back gate terminal and the second back gate terminal.