Patent ID: 6893900

Claim:
A method of making an integrated circuit chip package, comprising the steps of: a) forming a leadframe to include: a frame; a die pad integrally connected to the frame and defining opposed, generally planar first and second die pad surfaces, and at least one peripheral die pad side surface extending between the first and second die pad surfaces; and a plurality of tabs integrally connected to the frame and extending toward the die pad in spaced relation thereto, each of the tabs defining opposed, generally planar first and second tab surfaces and at least one peripheral tab side surface extending between the first and second tab surfaces; b) chemically etching the leadframe, a reentrant portion being disposed within at least portions of each of the peripheral die pad and tab side surfaces as a result of the etching of the leadframe; c) placing an integrated circuit die upon the first die pad surface of the die pad; d) electrically connecting the integrated circuit die to the first tab surface of each of the tabs; e) applying an encapsulant material to the frame, the integrated circuit die, the first die pad surface of the die pad, the first tab surface of each of the tabs, and into the reentrant portions of the peripheral die pad and tab side surfaces, without covering the second surface of each of the tabs; f) hardening the encapsulant material; and g) singulating the encapsulated frame so that the die pad and the tabs are severed from the frame, the second surface of each of the tabs being exposed within the package.