Patent ID: 7908507

Claim:
A data fetch circuit that masks an input of an invalid data strobe signal when it fetches a data signal synchronously with a data strobe signal with the data signal in accordance with a read instruction signal comprising: a response time measuring part measuring a response time from the input of the read instruction signal to a valid edge of the data strobe signal; and a standby part giving an instruction of a cancel of the mask of the data strobe signal after standing by for a standby time based on the response time in accordance with a standby start signal based on the read instruction signal, wherein the data strobe signal outputs the valid edge which makes a transition from a high impedance to a first logic level in accordance with the read instruction signal; and the response time measuring part comprises: a transition detecting part detecting the transition of the data strobe signal from the high impedance to the first logic level; and a measuring part measuring the response time from the input of the read instruction signal to an output of a detection result of the transition detecting part, and wherein the transition detecting part comprises: a first comparator in which the data strobe signal is inputted to an inversion input terminal and a first threshold voltage detecting the first logic level is inputted to a non-inversion input terminal; a second comparator in which an inversion data strobe signal complementary to the data strobe signal is inputted to a non-inversion input terminal and a second threshold voltage detecting the second logic level is inputted to an inversion input terminal; and a gate circuit that calculate an AND operation of outputs of the first and second comparators.