Patent ID: 8541277

Claim:
A method of fabricating a non-volatile memory device, comprising: sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate; patterning the first polysilicon layer and the tunnel insulation layer; forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer; forming a gate insulation layer on the substrate where the substrate is exposed; forming a second polysilicon layer to cover the dielectric layer; forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates comprising: sequentially etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer; and separating the etched layers into two parts; forming a first selection gate and a second selection gate contacted with sidewalls of the separated two dielectric layers and isolated from the substrate by the gate insulation layer; and forming a plurality of source/drain regions in portions of the substrate exposed after the etching of the middle portions.