Patent ID: 7170769

Claim:
A TCAM cell architecture comprising: a read/write bit line and a read/write bit complement line; a search bit line and a search bit complement line; an active NMOS layer, an active PMOS layer, a poly layer, and metal layers; a pair of memory elements connected to the associated read/write bit line and the read/write bit complement line for storing a data bit and a complement data bit; and a pair of compare circuits connected to the associated pair of memory elements and the associated search bit line and the search bit complement line that compares the stored data bit and the stored complement data bit with a received compare data bit via the search bit line and the search bit complement line, respectively, and drives a mismatch signal onto an associated match line when the stored data bit is not equal to the compare data bit, wherein each of the pair of memory elements are connected using substantially vertical interconnections that are disposed in the active NMOS layer and the active PMOS layer and further connected using substantially horizontal interconnections that are disposed in the metal layers, wherein the pair of memory elements and the associated read/write bit line and the read/write bit complement line are connected using substantially horizontal interconnections that are disposed in the poly layer and the metal layer, wherein each of the pair of compare circuits include a pair of NMOS transistors, and wherein the pair of NMOS transistors are connected using substantially vertical interconnections that are disposed in an active NMOS layer.