Patent ID: 7269067

Claim:
In a non-volatile memory device comprising a plurality of memory cells, each of the plurality of memory cells comprising a source, a drain, a dielectric layer formed on a substrate, a charge storage element comprising silicon nitride formed on the dielectric layer, an inter-gate dielectric formed on the charge storage element, and a control gate formed on the inter-gate dielectric, a method of programming at least one of the memory cells, comprising: applying a first voltage to the control gate; applying a second voltage to the drain the second voltage ranging from about 3 volts to about 5 volts; and applying at least one of a positive bias to the source or a negative bias to the substrate, wherein the charge storage element in each of the plurality of memory cells is configured to store charges representing two bits of information and applying the first and second voltages and at least one of the positive bias or the negative bias comprises: applying the first and second voltages and at least one of the positive bias or the negative bias for a duration ranging from about 0.1 microseconds (μs) to about 5 μs.