Patent ID: 7935545

Claim:
A method of performing a double-patterning (DP) processing sequence using a plurality of Site-Dependent (S-D) procedures, the method comprising: receiving a first set of wafers by one or more subsystems in a processing system; creating one or more first patterned layers on a first set of patterned wafers using a first S-D DP processing sequence, the first S-D DP processing sequence being performed using one or more of the subsystems in the processing system; establishing first confidence data for the first set of patterned wafers using a first S-D evaluation procedure; establishing a first set of high confidence wafers using the first confidence data; creating one or more second patterned layers on a second set of patterned wafers wherein the second set of patterned wafers are created by performing a second S-D processing sequence using the first set of high confidence wafers, the second S-D processing sequence being performed using one or more of the subsystems in the processing system, wherein the one or more second patterned layers are aligned relative to the one or more first patterned layers using a scanner subsystem; establishing second confidence data for the second set of patterned wafers using a second S-D evaluation procedure; and establishing a second set of high confidence wafers using the first confidence data or the second confidence data, or any combination thereof.