Patent ID: 7151037

Claim:
A method of forming a semiconductor construction comprising: providing a substrate; forming a transistor device supported by the substrate, the transistor device comprising a gate and a pair of conductively doped source/drain regions proximate the gate; the conductively doped source/drain regions being doped to a first conductivity type; the source/drain regions being a first source/drain region and a second source/drain region; forming an electrical connection from the first source/drain region to an electrical ground; epitaxially growing a semiconductive material pillar over the second source/drain region; doping the pillar with first conductivity type dopant; epitaxially growing a silicon-containing seed layer over the pillar; forming crystalline Si/Ge over the silicon-containing seed layer; the silicon-containing seed layer and crystalline Si/Ge being together incorporated into a resistor; doping the silicon-containing seed layer and the crystalline Si/Ge to a second conductivity type which is opposite to the first conductivity type; and forming an electrical connection from the resistor to V DD .