Patent ID: 8773903

Claim:
A NAND-based 2T-NOR flash memory array comprising: a plurality of NAND-based 2T-NOR flash cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each of said NAND-based 2T-NOR flash cells having a storage transistor with a cell gate, a source and a drain, and an access transistor with a select gate, a source and a drain, said source of said access transistor being connected in series with said drain of said storage transistor; a plurality of word lines with each word line connecting the cell gates of a row of said 2T-NOR flash cells, said word lines running in an X direction; a plurality of select-gate lines with each select-gate line connecting the select gates of a row of said 2T-NOR flash cells; a plurality of source lines with each source line connecting the sources of the storage transistors of one and only one column of said 2T-NOR flash cells, said source lines running in a Y direction perpendicular to said word lines; a plurality of bit lines with each bit line connecting the drains of the access transistors of one and only one column of said 2T-NOR flash cells, said bit lines running in parallel with said source lines; and wherein said storage transistor has an erased state with a negative threshold voltage and at least one programmed state with a positive threshold voltage, said NAND-based 2T-NOR flash memory array is partitioned into a plurality of memory sectors, each memory sector having a plurality of memory blocks, each memory block having a plurality of memory pages, and each memory page having one row of said NAND-based 2T-NOR flash cells with one word line and one select-gate line, and during a read operation in a selected memory page of a selected memory block in a selected memory sector, all word lines in said selected memory sector are applied with a power supply voltage Vdd or a boost voltage Vboost, the select-gate line in said selected memory page is applied with Vboost, all bit lines in said selected memory sector are applied with 1V, and all other word lines, all other select-gate lines, all other bit lines and all source lines in said flash memory array are applied with 0V.