Patent ID: 7529985

Claim:
A memory size allocation device used on an interleaver to process interleaving for an input data which contains a selected number (N+1) of data items, the interleaver buffering the N+1 data items in a plurality of memory addresses of a memory and outputting the N+1 data items in a delay sequence of m×Dm, where Dm is the delay of a m th data item and m is an integer ranging from 0, 1 to N, the memory size allocation device comprising: an address allocation unit for buffering each m th data item of the N+1 data in a m th buffer section which contains m×Dm+Pm memory addresses, where Pm is a number representing a predetermined number of the memory addresses for extra buffering of the m th data item; and an access control unit for assigning an empty memory address in the m th buffer section to allow the interleaver to buffer the m th data item therein and notifying the interleaver to retrieve the m th data item therefrom when the interleaver outputs the m th data item.