Patent ID: 7724578

Claim:
A memory device comprising: a memory array comprising a first floating body cell configured to store a first bit value and a second floating body cell configured to store a second bit value; and a sense amplifier device comprising: a first bit output configured to provide a first output voltage representative of the first bit value; a reference source configured to provide a reference voltage; a first current mirror configured to provide a first current to the first floating body cell based on the reference voltage; a first differential amplifier circuit configured to determine the first output voltage based on the reference voltage and a voltage across the first floating body cell resulting from application of the first current to the first floating body cell; a second bit output configured to provide a second output voltage representative of the second bit value; a second current mirror configured to provide a second current to the second floating body cell based on the reference voltage, wherein the second current is substantially equal to the first current; a second differential amplifier circuit configured to determine the second output voltage based on the reference voltage and a voltage across the second floating body cell resulting from application of the second current to the second floating body cell; and the reference source comprising a third floating body cell and a fourth floating body cell coupled in parallel, wherein the third floating body cell is configured to store a third bit value and the fourth floating body cell is configured to store a fourth bit value that is a complement of the third bit value.