Patent ID: 7847331

Claim:
A nonvolatile memory system, comprising: a nonvolatile semiconductor memory device utilizing a short channel effect between source region and drain region of a transistor; and control circuitry coupled to the nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device includes: (a) a first semiconductor region and a second semiconductor region, which are formed in a p-type semiconductor substrate; (b) a first conductor and a second conductor, which are formed over the semiconductor substrate between the first semiconductor region and the second semiconductor region, the first conductor being positioned on the first semiconductor region side, the second conductor being positioned on the second semiconductor region side; (c) a first insulator formed between the first conductor and the semiconductor substrate; and (d) a second insulator, which is formed between the second conductor and the semiconductor substrate and provided with an internal charge storage section, wherein the control circuitry controls an erase operation such that a voltage is applied between the second conductor and the second semiconductor region in order to inject first carriers of a first polarity into the charge storage section, and wherein the control circuitry is constructed and operates, in the erase operation, to apply a first potential of positive polarity to the second semiconductor region, to apply a second potential of a negative polarity to the second conductor, and to apply a third potential of positive polarity, which reverses a channel surface of the first semiconductor region to cause the short channel effect, to the first conductor.