Patent ID: 7200044

Claim:
A page buffer circuit of a flash memory device having a plurality of Multi-Level Cells (MLCs) connected to at least one pair of bit lines, comprising: an upper-bit register configured to at least one of sense a voltage of a sensing node, store upper sensing data and output inversed upper sensing data, and store input data and output inversed input data, in response to a first read control signal; a lower-bit register configured to at least one of sense a voltage of the sensing node, store first lower sensing data and output inversed first lower sensing data, in response to a second read control signal, and sense a voltage of the sensing node, store second lower sensing data and output inversed second lower sensing data, in response to a third read control signal; an upper bit verify circuit configured to receive one of the inversed upper sensing data and the inversed input data and output upper verify data according to the received data; and a lower bit verify circuit configured to receive the first lower sensing data or the inversed second lower sensing data, and output lower verify data according to the received data.