Patent ID: 7605472

Claim:
An interconnection region of a semiconductor device comprising: an interlayer insulating film which has an opening therein in the shape of the interconnection, the interlayer insulating film being formed of a low-dielectric-constant material; a barrier metal layer which is formed along an inner wall of the opening; a metal layer which fills the opening over the barrier metal layer and has a top surface substantially level with a top surface of the interlayer insulating film; and a capping layer covering the top surfaces of the interlayer insulating film and the metal layer, the capping layer having a first layer comprising a silicon compound having a nitrogen moiety overlying the top surfaces of the interlayer insulating film and the metal layer and a second layer comprising a silicon compound having a carbon moiety directly on the first layer, wherein the interconnection is a dual damascene interconnection comprising a via and a wiring above the via.