Patent ID: 8578140

Claim:
A branch prediction apparatus of a processor, comprising: a fetching unit that fetches a plurality of instructions including a first branch instruction and a second branch instruction from an instruction storage source based on a single instruction address; a branch instruction predicting unit that predicts whether an instruction to be executed by the processor is a branch instruction based on branch history information of a plurality of instructions executed in past; and an execution unit that executes at least one of the fetched plurality of instructions, the branch instruction predicting unit including: a history storage module that stores a branch destination address of the executed branch instruction as the branch history information in a storage location selected from any one of a plurality of storage locations of the history storage module determined from the single instruction address of the fetched plurality of instructions; an update module that updates a selection information for selecting a first storage location and a second storage location from the plurality of storage locations of the history storage module, to select different storage locations for a first branch destination address of the first branch instruction and a second branch destination address of the second branch instruction after the first branch destination address is stored in the history storage module; a selection module that selects a first storage location for the first branch destination address and a second storage location for the second branch destination address simultaneously, wherein the selection module selects the storage location for the second branch destination address based on the updated selection information; and a storage control module that controls the history storage module to store the first branch destination address and the second branch destination address in the selected storage locations.