Patent ID: 7960842

Claim:
A chip package comprising: a circuit substrate; an array of contact balls on a first side of said circuit substrate; a first chip over a second side of said circuit substrate, wherein said second side of said circuit substrate is opposite to said first side of said circuit substrate, wherein a horizontal distance between a left sidewall of said first chip and a right sidewall of said first chip is less than that between a left sidewall of said circuit substrate and a right sidewall of said circuit substrate, wherein said first chip comprises a silicon substrate; multiple first metal bumps between said circuit substrate and said first chip and vertically under said first chip, wherein each of said multiple first metal bumps has a bottom end on said second side of said circuit substrate; a first underfill between said first chip and said circuit substrate and between said multiple first metal bumps, wherein said first underfill contacts said circuit substrate; a second chip over said first chip, wherein said second chip comprises a silicon substrate; multiple second metal bumps between said first and second chips and vertically under said second chip, wherein each of said multiple second metal bumps has a top end on said second chip and a bottom end on said first chip; and a second underfill between said first and second chips and between said multiple second metal bumps, wherein said second underfill contacts said first and second chips.