Patent ID: 7783940

Claim:
An apparatus for reconfiguring a set of N base blocks with k redundant blocks in a memory, up to k of N base blocks being likely to be defective, said apparatus comprising: a) using k N-to-1 multiplexer (MUX Ri ) to reconfigure a write function, wherein each said N-to-1 multiplexer MUX Ri has N input signals (d 0 to d N−1 ) with the output of said N-to-1 multiplexer capable of being connected to the input signal of one of said k redundant blocks; and b) using N k+1-to-1 multiplexers (MUX i ) to reconfigure a read function, wherein each said k+1-to-1 multiplexer MUX i has k+1 input signals respectively connected from k redundant blocks and one base block input signal, N i , with the output of each said k+1-to-1 multiplexer capable of being connected to an output signal (q i ).