Patent ID: 8521977

Claim:
An information processing apparatus comprising: a first node that includes a first storing unit configured to store first identification information; and a second node that includes a second storing unit configured to store second identification information and includes a shared memory, the second node being coupled with the first node via an interconnect, wherein the first node includes a first processor including a transmitting unit that transmits a request for requesting an access to the shared memory, by attaching address information of the shared memory and the first identification information, and the second node includes a determining unit that determines whether or not an access to the shared memory is permitted based on the second identification information and the first identification information that is included in the request transmitted from the first node, the first processor further includes a cache memory that retains data obtained from the shared memory, and the first processor writes the data retained by the cache memory back to the shared memory in the second node when the determining unit in the second node rejects an access of the request for transferring data from the shared memory to the cache memory.