Patent ID: 7596737

Claim:
A system for testing a plurality of state retention circuits in an integrated circuit (IC) chip, the system comprising: a signal generator module having a clock generator configured to generate a clock signal, a power management unit configured to invoke a sleep mode in the IC chip, and a test mode controller configured to invoke a save and a restore signal; a data generator for supplying a series of predetermined data for the testing; a plurality of serially connected data latches receiving the clock, save and restore signals, wherein each data latch employs one of the plurality of state retention circuits; and a data comparator for comparing the data supplied by the data generator with data shifted out from the data latches during the testing, wherein the plurality of data latches save their existing data in their corresponding state retention circuits upon an assertion of the save signal, restore the data from the plurality of state retention circuits back to their corresponding data latches upon an assertion of the restore signal, and shifting the existing data along the series of the data latches one latch a cycle of the clock signal, wherein the data generator is configured to generate a first test pattern and a second test pattern, wherein the second test pattern is complementary to the first test pattern, and wherein an output of the data generator is coupled to an input of a first data latch at a first end of the plurality of data latches, and an output of a second data latch at a second end of the plurality of data latches is coupled to an input of the data comparator.