Patent ID: 6856552

Claim:
A semiconductor memory comprising: a cell array including a plurality of memory cells each comprising: an electron trapping layer formed above a semiconductor substrate, a control gate formed above said electron trapping layer; a pair of a source and a drain formed in a surface region of said semiconductor substrate to sandwich a region below said control gate; and a control circuit for performing control including: a data erase operation for setting said control gate of a memory cell of said cell array at a negative voltage with respect to said semiconductor substrate; and a detrap operation for making the absolute value of a negative voltage with respect to said semiconductor substrate, which is applied to said control gate, larger than that of the negative voltage during the data erase operation, and at the same time setting said source and drain at 0 V or at a positive voltage or floating said source and drain; wherein the control circuit makes control such that the potential difference between the semiconductor substrate and the control gate upon a detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.