Patent ID: 7429517

Claim:
A method for forming MOS transistors, comprising: providing a semiconductor substrate; forming a first dielectric layer on a surface of the semiconductor substrate; forming a gate electrode on said dielectric layer; forming source and drain regions in said semiconductor substrate adjacent said gate electrode; forming a plurality of dielectric layers over said semiconductor substrate, said gate electrode and said source and drain regions, the plurality of layers comprising a second dielectric layer and a third dielectric layer, wherein each of the second and third layers exert a compressive stress on the semiconductor substrate, or each of the second and third layers exert a tensile stress on the semiconductor substrate; removing the entire third layer formed over the semiconductor substrate, while leaving at least the second layer remaining over said gate electrode and said source and drain regions; forming a fourth dielectric layer over said at least second layer remaining over said gate electrode and said source and drain regions; and forming contact structures to said source and drain regions through said fourth dielectric layer.