Patent ID: 7301407

Claim:
A capacitor bank comprising: a first node; a second node; a plurality of first blocking capacitors, each of which has a first blocking capacitor first terminal connected to the first node, and a first blocking capacitor second terminal, wherein the same bias voltage of one-half of a known power supply voltage is applied to every first blocking capacitor second terminal; a plurality of N first accumulation-mode MOS (AMOS) varactors, each of which has a first AMOS varactor first terminal connected to the first blocking capacitor second terminal, respectively; a plurality of second blocking capacitors, each of which has a second blocking capacitor first terminal connected to the second node, and a second blocking capacitor second terminal, wherein the same bias voltage of one-half of a known power supply voltage is applied to every second blocking capacitor second terminal; and a plurality of N second accumulation-mode MOS (AMOS) varactors, each of which has a second AMOS varactor first terminal connected to the second blocking capacitor second terminal, and a second AMOS varactor second terminal connected to a first AMOS varactor second terminal, respectively, wherein N binary coded control signals having a value of either the power supply voltage or zero are applied to the respective first AMOS varactors second terminals connected to the second AMOS varactors second terminals, whereby respective capacitances of the plurality of N first AMOS varactors and respective capacitances of the plurality of of N second AMOS varactors are adjusted using the N binary coded control signals.