Patent ID: 7452804

Claim:
A method of fabricating a semiconductor device, the method comprising: providing a wafer that includes a conductive region, the wafer comprising a top surface; depositing a first conductive liner over the top surface of the wafer; forming a stencil pattern over the wafer, wherein the first conductive liner is removed from over the top surface of the wafer except under the stencil pattern; conformally depositing a second conductive liner over the stencil pattern; etching the second conductive liner to form sidewalls around the stencil pattern; after etching the second conductive liner, depositing a dielectric layer over the wafer; planarizing the dielectric layer down to the stencil pattern; removing the stencil pattern to form an aperture, wherein the aperture exposes the first conductive liner and the second conductive liner; and depositing a conductor in the aperture to form a conductive layer.