Patent ID: 8130019

Claim:
A circuit segment comprising: a) a first clocked device; b) a second clocked device; c) a data path between the first clocked device and the second clocked device for propagating data released by the first clocked device to the second clocked device, said data path having: i. a plurality of logical data paths between the first clocked device and the second clocked device, each of said logical data paths being associated with a respective logical path data propagation delay; ii. a logical data path selection module for selecting a logical data path amongst said plurality of logical data paths at least in part based on a logical data path selection control signal, data on the selected logical data path being propagated to the second clocked device; d) a clock propagation path for propagating clock signals to the first clocked device and the second clocked device, wherein the clock signal propagated to the second clocked device is delayed from the clock signal propagated to the first clocked device by a clock delay interval, the clock delay interval being derived at least in part based on the logical data path selection control signal so that the clock delay interval is related to the selected logical data path.