Patent ID: 7760637

Claim:
An interface between a data signal input and N data signal outputs, the interface comprising: a receiver core for separating the data signal input into M individual channels each channel having a different priority for each N data signal output having a different rate and different priority; an Interface Logic Unit (“ILU”) comprising M interface logic subunits each for processing one of the M individual channels and each comprising: means for separating at least one of the M individual channels into N intermediate signals; means for providing feedback to the receiver core regarding a condition of one or more of the N intermediate signals; means for generating control signals responsive to an error packet or an end of packet in one or more of the M individual channels; means for implementing load balancing among one or more of the N intermediate signals; means for implementing load balancing among the N data signal outputs; and a multiplexer unit comprising N multiplexers (“MUXes”) each receiving one of the N intermediate signals from each of M interface logic subunits and multiplexing the received intermediate signals to create one of the N lower speed data signals.