Patent ID: 6859400

Claim:
A semiconductor memory device comprising: a memory cell connected to a bit line; a sense amplifier connected to said bit line; a plurality of gates connected to said bit line; a plurality of latch circuits; a plurality of reading and writing gates, and a plurality of input-output ports, wherein during a read operation: said sense amplifier amplifies memory data output from said memory cell, a first transfer signal controls a first gate of said plurality of gates to transfer said amplified memory data to a first latch circuit of said plurality of latch circuits during a first read-transfer time period, said first gate being operable to electrically disconnect said first latch circuit from said bit line when other than said first read-transfer time period, a first read signal controls a first reading and writing gate of said plurality of reading and writing gates to present said amplified memory data from said first latch circuit to a first input-output port of said plurality of input-output ports during a first read-output time period, a second transfer signal controls a second gate of said plurality of gates to transfer said amplified memory data to a second latch circuit of said plurality of latch circuits during a second read-transfer time period different than said first read-transfer time period, said second gate being operable to electrically disconnect said second latch circuit from said bit line when other than said second read-transfer time period, and a second read signal controls a second reading and writing gate of said plurality of reading and writing gates to present said amplified memory data from said second latch circuit to a second input-output port of said plurality of input-output ports during a second read-output time period different than said first read-output time period.