Patent ID: 7660168

Claim:
A multi-port memory device, comprising: a plurality of ports; a plurality of bank control units; a plurality of banks, each of which is connected to a corresponding one of the bank control units; a read clock generation unit for generating a read clock in response to a read command; a data transmission unit for transmitting a read data from the banks to a corresponding one of the ports in response to the read clock; a column address generation unit for generating a column address; an input/output (I/O) sense amplification unit for amplify the read data; a pipe latch unit for latching an output of the I/O sense amplification unit; an I/O sense amplifier control unit for controlling the I/O sense amplification unit in response to the read command and a write command; and a pipe latch input control unit for controlling the output of the I/O sense amplification unit to the pipe latch unit, wherein every bank control unit is connected to all of the ports.