Patent ID: 7701764

Claim:
A method for executing a memory command by a plurality of non-volatile memories included in a multi-chip non-volatile memory device, the method comprising: concurrently receiving the memory command by first, second, and third memories of the plurality of non-volatile memories; executing the memory command by the first memory of the plurality of non-volatile memories in response to receiving the memory command; determining a first time delay for the second memory of the plurality of non-volatile memories in response to receiving the memory command; executing the memory command by the second memory of the plurality of non-volatile memories after the first time delay from receiving the memory command; and determining a second time delay for the third memory of the plurality of non-volatile memories in response to receiving the memory command; executing the memory command by the third memory of the plurality of non-volatile memories after the second time delay from receiving the memory command, the second time delay greater than the first time delay.