Patent ID: 8084986

Claim:
A dead-time compensation apparatus of a PWM inverter, the inverter having a plurality of switching elements, and turn-on and turn-off states of the switching elements controlled by a gate driver circuit to drive an induction motor using a constant V/f control, and a three-phase output current of the inverter detected to be as an analog detecting current by a current detecting circuit; the dead-time compensation apparatus of a PWM inverter comprising: an analog-to-digital conversion unit connected to the current detecting circuit to receive the analog detecting current and convert the analog detecting current into a digital detecting current; in a closed-loop speed control, an output frequency of the induction motor is received and converted into a digital detecting frequency by the analog-to-digital conversion unit; a voltage/frequency control unit connected to the analog-to-digital conversion unit to receive the digital detecting frequency; in the closed-loop speed control, the voltage/frequency control unit further receiving an external frequency command, and obtaining a frequency difference between the digital detecting frequency and the frequency command and outputting a corresponding reference voltage according to a relationship between voltage and frequency of the voltage/frequency control unit; a dead-time compensation logical unit connected to the analog-to-digital conversion unit and the voltage/frequency control unit to receive the digital detecting current and the reference voltage and outputting a voltage command; the dead-time compensation logical unit comprising: a root-mean-square calculation unit receiving the digital detecting current to calculate a root-mean-square value of the digital detecting current to be as a base current; a divider connected to the root-mean-square calculation unit to calculate a ratio between the digital detecting current and the base current to be as a per-unit current; a first current-to-voltage conversion unit connected to the root-mean-square calculation unit to receive the baser current and outputting a corresponding base compensation voltage according to a relationship between current and voltage of the first current-to-voltage conversion unit; a second current-to-voltage conversion unit connected to the divider to receive the per-unit current and outputting a corresponding per-unit compensation voltage according to a relationship between current and voltage of the second current-to-voltage conversion unit; a multiplier connected to the first current-to-voltage conversion unit and the second current-to-voltage conversion unit to calculate a compensation voltage by multiplying the base compensation voltage and the per-unit compensation voltage; and an adder connected to the multiplier to add the compensation voltage and the reference voltage to produce the voltage command; and a PWM generating unit connected to the dead-time compensation logical unit to receive and convert the voltage command and outputting a PWM voltage command to the gate driver circuit.