Patent ID: 8043914

Claim:
A method of fabricating a flash memory device, the method comprising: forming gate lines comprising a plurality of cell gate lines and a selection gate line, each comprising a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and a polysilicon layer operable to be a control gate, formed on a semiconductor substrate; forming a first insulating layer that selectively fills gaps between ones of the plurality of cell gate lines from the bottom up and gaps between a first side of the selection gate line and an adjacent one of the plurality of cell gate lines, and does not fill a space on a second side of the selection gate line that is opposite the first side of the selection gate line; forming a spacer on the second side of the selection gate line after forming the first insulating layer; and forming a second insulating layer adjacent the spacer on the second side of the selection gate line, removing some parts of the first insulating layer, the second insulating layer, and the spacer so that at least a part of upper and side surfaces of the polysilicon layer is exposed; and forming a metal silicide on the exposed portion of the polysilicon layer.