Patent ID: 7382016

Claim:
A nonvolatile semiconductor memory device, comprising: a semiconductor substrate including a memory cell region and a peripheral circuit region, the memory cell region including a plurality of first semiconductor active regions and a plurality of first isolation regions which isolate between the first active regions, each first isolation region extending toward a first direction, the peripheral circuit region including a second semiconductor active region and a second isolation region which isolates the second active region; a plurality of control gates, each control gate formed over the first active region and the first isolation region and extending toward a second direction intersecting to the first direction, respectively; a first insulating film formed on the first and a second active regions; a plurality of floating gates, each floating gate formed between the control gate and the first insulating film; a second insulating film formed between the floating gate and the control gate; and a peripheral gate formed on the first insulating film in the peripheral circuit region, including a first electrode portion formed on the first insulating film, a second electrode portion formed on the first electrode portion and a third insulating film located between the first and the second electrode portions; wherein a first upper surface of the first isolation regions facing to the control gate protrudes from a second upper surface of the first insulating film, a height of the first upper surface is lower than a height of a third upper surface of the floating gate, a fourth upper surface of the first isolation regions between the control gates is the same as a height of the second upper surface, and a fifth upper surface of the second isolation region protrude from the second upper surface, and a height of the fifth upper surface is lower than a height of a sixth upper surface of the first electrode.