Patent ID: 7319609

Claim:
A non-volatile memory device comprising: at least one current source coupled to a bit line, along which at least two memory cells sharing a common source line are connected, for generating a programming current on the bit line when one of the memory cells is selected for programming operation; and at least one voltage regulator coupled to the bit line between the current source and the memory cells for allowing the programming current to flow between the current source and the selected memory cell when a voltage level on the bit line is higher than a predetermined reference voltage, and blocking the programming current flowing between the current source and the selected memory cell when the voltage level on the bit line is lower than the predetermined reference voltage, thereby preventing a punch-through across the unselected memory cell from occurring, wherein the voltage regulator further comprises: at least one first MOS device coupled to the bit line between the current source and memory cells; at least one comparator having a first input terminal coupled to the predetermined reference voltage and a second input terminal coupled to the bit line between the first MOS device and the memory cells, for outputting a control signal indicating if the voltage on the bit line between the first MOS device and the memory cells is lower than the predetermined reference voltage; and at least one latch module coupled between the control signal of the comparator and a gate of the first MOS device for generating a latched control signal to turn off the first MOS device in response to the control signal.