Patent ID: 7945830

Claim:
A method for synthesizing a unified test controller for testing or diagnosing a plurality of clock domains in a scan-based integrated circuit in selected self-test or scan-test mode, said unified test controller having a global scan enable (GSE) signal and a test clock, each domain having a system clock, a scan clock, a scan enable (SE) signal, and a plurality of scan cells connected to form one or more scan chains; said method comprising the steps of: (a) compiling a hardware description language (HD:) code at a register-transfer level (RTL) or a netlist at a gate-level that represents said scan-based integrated circuit in physical form into a design database; (b) synthesizing said unified test controller; (c) integrating said unified test controller into said design database that represents said scan-based integrated circuit; (d) generating synthesized HDL code at said RTL or netlist at said gate-level; and (e) generating HDL test benches and automatic test equipment (ATE) test programs for verifying the correctness of said unified test controller in said scan-based integrated circuit in said selected self-test mode or said selected scan-test mode, wherein steps (a)-(e) are performed by a computer.