Patent ID: 7117409

Claim:
A method of testing a multi-port memory in accordance with a test pattern, the memory including a set of access ports and a plurality of memory cells accessible through the access ports, the access ports including at least first and second ports, the test pattern including at least a test element that is to be performed upon each of the memory cells and that includes at least consecutive first and second memory operations, said method comprising: a) generating a set of test clock signals that have the same test clock frequency, the test clock signals including at least a first test clock for controlling memory access through the first port, and a second test clock for controlling memory access through the second port, clock pulses of the second test clock lagging corresponding clock pulses of the first test clock by a first delay period; and b) conducting the first and second memory operations in a folded sequence upon one of the memory cells during the same test clock cycle of the test element, wherein the first memory operation is conducted through the first port during a first time period starting from a leading edge of one of the clock pulses of the first test clock and ending at a lagging edge of said one of the clock pulses of the first test clock, and wherein the second memory operation is conducted through the second port during, a second time period starting from a leading edge of one of the clock pulses of the second test clock and ending at a lagging edge of said one of the clock pulses of the second test clock; the first delay period having a duration sufficient to ensure that integrity of the first memory operation is not affected by the second memory operation and to ensure that the second time period overlaps the first time period such that the first and second memory operations are completed within the same test clock cycle of the test element.