Patent ID: 7320119

Claim:
A method for identifying a problem edge in an uncorrected or corrected mask layout which is to have manufacturing problems, the method comprising: creating an on-target process model that models a semiconductor manufacturing process under nominal process conditions; creating one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions; computing a process-sensitivity model using the on-target process model and the one or more off-target process models, wherein the process-sensitivity model-models sensitivity to variations in process conditions, and wherein computing of the process-sensitivity model comprises computing a linear combination of the on-target process model and the one or more off-target process models; computing an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which is used to detect edges in an image; and identifying a problem edge using the edge-detecting process-sensitivity model, comprising: computing a problem-indicator by convolving the edge-detecting process-sensitivity model with a multidimensional function that represents the mask layout; and comparing the value of the problem-indicator with a threshold to identify the problem edge in the mask layout.