Patent ID: 6957299

Claim:
A CAM interface that enables the integration of two or more CAM devices into a composite CAM array by connecting the CAM devices to the same Data bus lines and to the same Address bus lines, comprising: a) a plurality Wa of lines connecting the CAM interface to a number of Address bus lines and a plurality of Wb lines connecting the CAM interface to the CAM device wherein Wa is larger or equal to Wb; b) a first buffer for selectively connecting a first plurality Da of Data lines of the CAM to the same number of Data lines of the Data bus, the connection being done when a first enabling signal is set; c) a second buffer for selectively connecting a second plurality Db of data lines of the CAM to a second number of data lines of the data bus, the said second number of Data lines being equal to Db, the said connection being done when a second enabling signal is set; d) and a Priority Mask Circuit that receives as input a plurality W2 of Select Lines, the states of which define a Block Address for the CAM interface and also receives as input an enabling signal, the said Priority Mask circuit being further connected to a Data Bus via a number W3 of Data Lines, W3 being larger or equal to W2 wherein if a number or at least one of the memory cells within the CAM have stored data verifying a given relationship with the data set on the Address Bus lines, then the CAM selects one of the said number of cells, according to the internal priority order defined for the CAM, and applies the address of that cell on the said first buffer or the CAM applies the address of the single responding cell on the said first buffer, the CAM also outputs the said enabling signal to the Block Priority Mask; the Block Priority Mask logic circuit then applies the said Block Address on the said W3 number of Data Bus lines while masking any bit of that address that would interfere with any Address being Higher in a predefined direction that has been set on the said Data Bus lines; and in case that no Higher Address was output on the Data Bus, the Block Priority Mask logic circuit outputs the said first enabling signal to the said first buffer, whereupon the selected address is set to the said first number of Data Bus lines.