Patent ID: 8464125

Claim:
An apparatus comprising: an execution unit to perform a sequence of operations for a Cyclic Redundancy Check (CRC) instruction, the CRC instruction having a first operand and a second operand, the sequence of operations to perform a Cyclic Redundancy Check (CRC) operation on a 2n-bit data block stored in the second operand using one of a plurality of different n-bit polynomials stored in the first operand to cause the execution unit to: expand an n-bit polynomial to provide a pre-computed polynomial K; and perform a sequence of micro-operations on the 2n-bit data block using the n-bit polynomial and current n-bit residue stored in the first operand and the pre-computed polynomial K to provide an n-bit residue for the 2n-bit data block, wherein the sequence of micro-operations comprises a shuffle word micro-instruction to perform a shuffle by selection of an n-bit portion from the first operand and an n-bit portion from the second operand to store in a 2n-bit destination operand.