Patent ID: 7987340

Claim:
A processor system, comprising: a plurality of processors; and a network interconnecting said processors, wherein at least one transmitting processor is programmed to transmit data to a plurality of receiving processors during predefined time periods, and wherein the receiving processors are programmed to receive the transmitted data during said predefined time periods, wherein, during said predefined time periods at which the plurality of receiving processors are programmed to receive the transmitted data and at the same time as said at least one transmitting processor is programmed to transmit said data, said receiving processors are programmed to transmit an acknowledge signal to the respective transmitting processor, indicating whether they are able to accept the transmitted data, wherein the acknowledge signals from said plurality of receiving processors are combined into a combined acknowledge signals which indicates whether or not all of said plurality of receiving processors were able to accept the transmitted data; wherein each transmitting processor is programmed to detect the combined acknowledge signal and, in the event that the combined acknowledge signal indicates that not all of said receiving processors were able to receive said transmitted data, to retransmit said data to all of said plurality of processors during a next predefined time period; and wherein said transmitting processor is programmed such that when said combined acknowledge signal indicates that all receiving processors were able to accept the data then said is not retransmitted.