Patent ID: 7355467

Claim:
A physical layer segment including a delay line generator comprising: A first bias generator, And a second bias generator having: a positive reference, a negative reference, a first bandgap reference, and a second bandgap reference, A voltage control input, A delay line output, A first MOSFET having a first doping, Conductively coupling said first reference to said delay line output, And coupled at its gate to said voltage control input, A second MOSFET having a first doping, Conductively coupling said first reference to said delay line output, And coupled at its gate to said first bandgap reference, A third MOSFET having a complementary doping to said first doping, Conductively coupling said second reference to said delay line output, And coupled at its gate to said second bandgap reference, And a fourth MOSFET having a complementary doping to said first doping, Conductively coupling said second reference to said delay line output, And coupled at its gate to said delay line output.