Patent ID: 7322020

Claim:
A circuit layout for a photosensitive chip, comprising: a semiconductor substrate, having a matrix of photosensitive units, the photosensitive units aligned in a row in a first direction, the photosensitive units aligned in a column in a second direction, wherein the second direction is positioned at an angle relative to the first direction, wherein each said photosensitive unit comprises a first blocking region, a second blocking region and a photosensitive region, and each said first blocking region comprises a source and a drain; a plurality of first circuit lines, formed over the semiconductor substrate in parallel extending in the first direction, wherein the source and the drain of each said first blocking region are located on both sides of the corresponding first circuit lines extending in the first direction, a part of the source and a part of the drain are located between the corresponding neighboring photosensitive regions aligned in the second direction, and the first circuit line, the source and the drain together form a transistor, the transistor extending as a barrier between the neighboring photosensitive regions aligned in the second direction; a plurality of second circuit lines, formed over the semiconductor substrate in parallel extending in the second direction, the second circuit lines crossing over the first circuit lines, wherein the second blocking region of each said photosensitive unit is located under the corresponding second circuit line, the second circuit line being positioned between neighboring photosensitive regions aligned in the first direction; and a plurality of parallel third circuit lines formed over the semiconductor substrate extending in the first direction, wherein the third circuit lines are located above the corresponding first circuit lines, and each said third circuit line covers the source, and wherein the source is closer to a neighboring photosensitive unit compared to the drain.