Patent ID: 8219831

Claim:
A processor comprising: a device providing a power throttling output signal; a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the power throttling output signal, and to the decode pipe to control a rate of execution of instructions therein, whereupon determining that the power throttling output signal satisfies a predetermined criterion, the logical power throttling unit causes the decode pipe to one or both increase the number of idle processor cycles between processor cycles in which instructions are decoded, and decrease the number of instructions decoded in a processor cycle, to reduce, for a duration of a thermal time constant, an average number of instructions decoded per processor cycle without physically changing any of a processor cycle time and processor supply voltage levels, and wherein upon expiration of the thermal time constant, the power throttling output signal is determined again, and used to further control the rate of execution of instructions by retaining, increasing, or further reducing the rate.