Patent ID: 7929360

Claim:
A memory device, comprising: a memory cell which includes a floating gate MOS transistor having a charge trap region; a memory cell array, wherein a plurality of memory cells is serially connected to configure NAND flash memory, one side of the memory cell array is connected to a first select transistor, and the other side of the memory cell array is connected to a second select transistor, where the first select transistor is connected to a local bit line; and a local sense amp including a local dynamic read circuit and a local write circuit, wherein the local dynamic read circuit includes a local read transistor for connecting the local bit line to a local amp node, a local pre-charge transistor for pre-charging the local amp node, and a local amplify transistor which reads a discharge time of the local amp node whether charging a global bit line or not; the local write circuit includes a local write transistor for connecting the local bit line to the global bit line; and a global sense amp including a global dynamic read circuit, a global latch circuit, and a global write circuit, wherein the global dynamic read circuit includes a global reset transistor for resetting the global bit line, a global amplify transistor for reading the global bit line, and a global select transistor for configuring a global series connection with the global amplify transistor; a global latch circuit is connected to the global series connection for receiving a read data; the global write circuit includes a global write transistor for transferring a write data to the global bit line; and a read path which is set up for reading a stored data from the memory cell and transferring to the global latch circuit through the local bit line, the local dynamic read circuit, the global bit line and the global dynamic read circuit; and a write path which is set up for writing the write data from the global latch circuit to the memory cell through the local bit line, the local write circuit, the global bit line and the global write circuit; and a locking signal generator for realizing time-domain sensing scheme, wherein the locking signal generator generates a delayed signal as a locking signal for locking the global dynamic read circuit, and the locking signal generator receives a latched signal from the global latch circuit as a reference signal based on at least a reference memory cell.