Patent ID: 6963493

Claim:
A multi-layer electronic device comprising: a plurality of first device layers, each such layer having a first series of resistive/conductive patterns thereon and a plurality of via drilled therethrough; a plurality of second device layers, each such layer having a plurality of via drilled therethrough; wherein said first and second device layers comprise an epoxy-fiberglass composite material; a unitary device body formed by the bonded union of an interleaved stack of said plurality of first and said second device layers, wherein each of said via correspond to a respective portion of the resistive/conductive patterns on the underlying device layer and wherein one of said second device layers forms the uppermost device layer and the lowermost device layer is one of said first device layers; a second series of resistive/conductive patterns on an outer layer of said uppermost device layer; a plurality of terminations on said unitary body for electrical connection between other electronic devices and various of the resistive/conductive patterns throughout said unitary device body; individual passive components with respective first and second opposing terminations, wherein each individual passive component is vertically mounted into a selected of said plurality of via and wherein one of said first and second opposing terminations are electrically connected to a portion of said underlying first device layer's first series of resistive/conductive patterns; multiple portions of a non-conductive material respectively substantially filling the spaces defined by respective vias between each of said individual passive components and said second device layers, wherein said non-conductive material partially encases each said individual passive component to hold it in place while leaving one of said first and second opposing electrical terminations exposed and prevents shorting between respective first and second opposing electrical terminations; and an electrical connection between each of said passive components and at least a portion of said overlying first device layer's first series of resistive/conductive patterns through a corresponding one of said first device layer's plurality of via.