Patent ID: 7369614

Claim:
A device comprising: an MPEG decoder structured to decode several coded images from at least a first and a second MPEG stream for displaying simultaneously one image of the first MPEG stream and one image of the second MPEG stream, the coded images belonging to a first type or to a second type, the images of the first type being frame interlaced images comprising two fields, the decoding of which is completed in two periods, one of the periods being equal to the time duration of one field display, and the images of the second type being interlaced half-images or progressive images, the decoding of which is completed in one of the periods; and a decoder control circuit for controlling the MPEG decoder, the decoder control circuit being configured to receive an order to decode a plurality of images at each of the periods and including a priority assignment circuit structured to, at each period, grant among the images to be decoded a decoding priority such that the highest decoding priority is granted to images of the first type that have received their decoding order for more than one of the periods, a lower decoding priority is granted to images of the second type, and the lowest decoding priority is granted to images of the first type that have received their decoding order for less than one of the periods.