Patent ID: 7821832

Claim:
A flash memory device, comprising: at least two mats, each mat comprising a plurality of word lines, a plurality of bit lines, and a plurality of blocks that share the plurality of bit lines, where in each block, a plurality of memory cells serially connected to one of the bit lines constitute a string, a plurality of memory cells connected to one of the word lines constitute a page, and a plurality of the pages constitute the block; and a row decoder shared by the plurality of blocks of each of the at least two mats, wherein the row decoder comprises: a block decoder generating a block selection signal in response to a block address signal for selecting a block of the plurality of blocks; a block word line boosting circuit generating a high voltage block word line signal in response to the block selection signal; a word line driver driving a plurality of word line drive signals driving the word lines of the selected block using word line drive voltages according to an operation mode, and driving the word lines of an unselected block using a first bias voltage; and a string selection line driver driving a string selection signal of the selected block using a string selection drive voltage according to the operation mode, and for driving the string selection signal of the unselected block using a second bias voltage.