Patent ID: 7746145

Claim:
A level shill circuit having a first power voltage and a second power voltage greater than the first power voltage, the level shill circuit comprising: a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage; a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal; a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal; a first high-withstand-voltage N-channel MOS transistor having a drain connected to the second output terminal and a source connected directly to a ground, and having a gate through which the second input signal is input; a second high-withstand-voltage N-channel MOS depletion-type transistor connected to the first output terminal and having a gate through which the first input signal is input; and a second low-withstand-voltage N-channel MOS transistor connected between the second N-channel MOS depiction-type transistor and the ground and having a gate through which the first input signal is input, wherein the second high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts.