Patent ID: 7867852

Claim:
A method for manufacturing a vertical semiconductor device comprising: a) forming a body layer in an epitaxial layer wherein the epitaxial layer is of a first semiconductor type and the body layer is of a second semiconductor type; b) forming a trench in the epitaxial layer, wherein b) includes forming a thin oxide layer on the epitaxial layer; forming a nitride layer on top of the thin oxide layer; forming a thick oxide layer on top of the nitride layer; and etching the epitaxial layer through one or more openings in the thick oxide layer, nitride layer and thin oxide layer to form the trench; c) lining a bottom and one or more sidewalls of the trench with a gate insulating layer; d) forming a gate electrode in the trench in the body layer and epitaxial layer, wherein a gate oxide is disposed between the gate electrode and the body layer and between the gate electrode and the epitaxial layer, wherein d) includes depositing conductive material in the trench wherein the gate oxide is disposed between the conductive material and the epitaxial layer; and etching the thick oxide layer down to the nitride layer leaving a portion of the conductive material protruding above an exposed surface of the nitride layer such that at least a portion of the gate electrode protrudes above a surface of the epitaxial layer; e) forming a cap insulator over the gate electrode, wherein e) includes oxidizing the portion of the conductive material protruding above an exposed surface of the nitride layer; f) etching back around the cap insulator such that the top of the gate electrode is even with or protrudes above a surface of the epitaxial layer; g) forming a spacer on the epitaxial layer self-aligned to the cap insulator, wherein the spacer includes a heavy concentration of dopants of the first semiconductor type and wherein the spacer is self-aligned to the cap insulating layer, and wherein forming the spacer comprises depositing a layer of material and then anisotropically etching back the layer of material with an etch selective to the insulator cap such that only the spacer is left; h) diffusing at least a portion of the dopants of the spacer into the body layer to form a source region below the spacer wherein the source region is of the first semiconductor type; i) implanting a body contact region containing dopants of a second semiconductor type in the body layer and annealing the body contact region, wherein implanting a body contact region is self-aligned to the spacer; and j) forming a metal layer over the insulator cap, spacer, source region and body Contact region.