Patent ID: 7003066

Claim:
A phase selection unit for generating a recovered clock signal, the phase selection unit comprising: a phase select signal generator for generating a plurality of phase select signals in response to a FWD (forward) signal and a BWD (backward) signal from a digital filter; wherein said digital filter asserts said FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of said recovered clock signal; and wherein said digital filter asserts said BWD signal if the phase of said SDIN (serial digital input) signal lags the phase of said recovered clock signal; a first multiplexer for inputting a predetermined number of given clock signals arranged in a predetermined phase order and for outputting a first output clock signal and a second output clock signal with said first and second output clock signals each being one of said given clock signals; a first phase interpolator that receives said first and second output clock signals from said multiplexer to generate said recovered clock signal having a phase that is phase interpolated between the phases of said first and second output clock signals; a multiplexer control circuit that controls said multiplexer to select one of said given clock signals for each of said first and second output clock signals, depending on whether said phase select signals indicates that said FWD signal is asserted or that said BWD signal is asserted such that the phase of said recovered clock signal generated from said phase interpolator increases when said FWD signal is asserted and decreases when said BWD signal is asserted and remains substantially constant when said FWD signal and said BWD signal are not asserted; a second multiplexer for inputting said predetermined number of given clock signals and for outputting a third output clock signal that has a 180° phase shift from said first output clock signal and for outputting a fourth output clock signal that has a 180° phase shift from said second output clock signal; and a second phase interpolator that receives said third and fourth output clock signals to generate a complementary recovered clock signal that has a 180° phase shift from said recovered clock signal and that has a phase that is phase interpolated between the phases of said third and fourth output clock signals.