Patent ID: 7764081

Claim:
A programmable device comprising: logic blocks; configuration memory cells connected to the logic blocks for programmably configuring the logic blocks; configuration circuitry connected to the configuration memory cells to perform programming of the configuration memory cells; a memory coupled to the configuration circuitry for storing program state for the configuration memory cells; a refresh circuit connected to the configuration circuitry causing periodic programming of the configuration memory cells, wherein intervals for the periodic programming are set to maintain soft error immunity due to single event upsets (SEUs); wherein the refresh circuit comprises: a timer circuit for indicating a time period between refreshes of the configuration memory cells; and a refresh controller for providing a signal to the configuration circuitry to cause the configuration circuitry to perform programming when the timer circuit indicates a refresh should occur; wherein the periodic programming of the configuration memory cells includes reading program state from the memory and writing the program state as read from the memory to the configuration memory cells; and wherein the intervals include at least first and second intervals that are set during operation of the programmable device and the second interval is of shorter duration than the first interval.