Patent ID: 7872919

Claim:
A semiconductor memory device comprising: at least one memory cell which includes a charge accumulation layer and a control gate and is capable of storing data of two or more values in accordance threshold values; at least one bit line which is connected to the memory cell; at least one sense amplifier which senses identical data, which is stored in the memory cell, a plurality of number of times at a time of read; at least one n-channel metal oxide semiconductor (MOS) transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to the bit line; and at least one control unit which applies one of a first voltage and a second voltage, which is higher than the first voltage, to a gate electrode of the n-channel MOS transistor, wherein the control unit applies the first voltage to the gate electrode, thereby setting the n-channel MOS transistor in an ON state, and applies the second voltage to the gate electrode during a period after first sense and before second sense.