Patent ID: 8541863

Claim:
A single poly electrically programmable read only memory (EPROM) cell with improved data retention comprising: A P-type substrate, having top and bottom surfaces; an N-type buried layer formed in the top surface of the P-type substrate; an N-type epitaxial layer formed on the top surface of the P-type substrate and the N-type buried layer; an N-type well region formed in the N-type epitaxial layer; a LOCOS field oxide isolation formed at the periphery of the well region, extending outwardly from the N-type well region to the next device isolation, thereby defining the boundary of the N-type well region; a field oxide stress relief ring formed in the N-type well region, extending inwardly and spaced-apart from the LOCOS field oxide isolation to define an EPROM BIT cell region in the N-type well region, wherein no contacts, additional diodes or guard rings exist between the field oxide stress relief ring and the LOCOS field oxide; an EPROM BIT cell configured as a PMOS transistor, having a floating gate formed in the upper surface of the N-type well, contained within the field oxide stress relief ring; wherein the EPROM BIT cell comprises: a P+ source region formed within the field oxide stress relief ring; a P+ drain region formed within the field oxide stress relief ring and spaced-apart from the source region to define a N-type channel region therebetween; wherein the source region is spaced-apart from the field oxide stress relief ring, and further comprising an N-type contact region formed between the source region and the field oxide stress relief ring; and a conductive gate comprised of N-doped polysilicon formed over the channel region and separated therefrom by intervening dielectric material.