Patent ID: 7635626

Claim:
A method of manufacturing a dynamic random access memory (DRAM), comprising: providing a substrate; forming a plurality of transistors on the substrate; forming a first and a second landing pad contacts (LPCs) between the transistors; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer, wherein the first opening exposes the first LPC; conformally forming a barrier layer on the first dielectric layer; forming a bit line contact (BLC) in the first opening and forming a bit line (BL) on the first dielectric layer, wherein the BL and the BLC are electrically connected to each other; forming a liner layer on the sidewall of the BL; forming a second dielectric layer on the substrate, wherein the dry etching rate of the second dielectric layer is substantially equal to that of the liner layer, and the wet etching rate of the second dielectric layer exceeds that of the liner layer; and forming a storage node contact (SNC) in the second dielectric layer and in the first dielectric layer, wherein the SNC and the second LPC are electrically connected to each other.