Patent ID: 8204153

Claim:
A data receiving circuit comprising: a data discrimination circuit discriminating data in an input signal in accordance with a data discrimination clock; a boundary detection circuit detecting a boundary in said input signal in accordance with a boundary detection clock; a phase control code generating circuit generating a phase control code by receiving outputs from said data discrimination circuit and said boundary detection circuit; a boundary detection timing varying circuit dynamically varying boundary detection timing in said boundary detection circuit by applying a variation to said boundary detection phase control code; and a variation reducing circuit reducing a phase variation occurring in said data discrimination clock in accordance with the dynamic variation of said boundary detection timing performed by said boundary detection timing varying circuit, wherein said boundary detection timing varying circuit comprises: a variation generating circuit generating said variation; and an adder circuit adding said variation generated by said variation generating circuit to said boundary detection phase control code, wherein said variation generating circuit is capable of varying an output pattern, and wherein the phase difference between said input signal data and said data discrimination clock and the gain of a feedback loop maintain a predefined proportional relationship relative to each other, regardless of the amplitude of said variation generated by said variation generating circuit.