Patent ID: 8190862

Claim:
A hardware device for concurrently processing a plurality of tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, said device comprising: a plurality of task units for processing data, making decisions and/or processing data and making decisions, including at least one source task unit and at least one destination task unit; a task interconnection logic means interconnecting the plurality of task units for communicating actions from the at least one source task unit to the at least one destination task unit; and each of said task units including: a processor for executing steps of a task associated with a task unit of the task units in response to a received request action; a status manager for handling the actions from the at least one source task unit and building the actions to be sent to the at least one destination task unit; and a plurality of control/data registers each corresponding, for the task associated with the task unit, to an instance of the algorithm, each one of said control/data registers comprising a control field composed of a completion bit set to 1 when the task associated with the task unit is completed, a validation bit set to 1 when the task associated with the task unit is validated and a L/R bit indicating that the output in the algorithm flow is left or right when the task associated with the task unit includes a decision.