Patent ID: 8381142

Claim:
A method for designing a system on a target device, the method comprising: replacing a plurality of registers with at least one register and a timing exception, wherein the replacing is computer implemented; identifying a first plurality of registers that are in series or substantially in series, wherein the first plurality of registers includes the plurality of registers; traversing backward from the first plurality of registers through a first combinational logic path to a first register; performing a timing analysis on the first combinational logic path; traversing forward from the first plurality of registers through a second combinational logic path to a second register; performing a timing analysis on the second combinational logic path; and if the first combinational logic path is longer than the second combinational logic path, then the timing exception is imposed on the first combinational logic path; if the second combinational logic path is longer than the first combinational logic path, then the timing exception is imposed on the second combinational logic path.