Patent ID: 7443234

Claim:
A differential amplifier comprising: first to mth (where m is an integer equal to or greater than 2) input terminals; an output terminal; first to mth differential pairs; a current source circuit that supplies currents to respective ones of said first to mth differential pairs; a first node connected in common with first outputs of each of output pairs of said first to mth differential pairs; a second node connected in common with second outputs of each of output pairs of said first to mth differential pairs; a load circuit connected to said first and second nodes; an amplifier stage that receives a signal from at least one node of said first and second nodes as an input and has an output end connected to said output terminal; a capacitance element; and a changeover circuit that controls changeover between a first connection state and a second connection state, responsive to a control signal supplied thereto; wherein in said first connection state, a first input of each input pair of said first to mth differential pairs is made a non-inverting input and a second input of each input pair of said first to mth differential pairs is made an inverting input, the first inputs of the input pairs of said first to mth differential pairs are connected to respective ones of said first to mth input terminals, and the second inputs of the input pairs of said first to mth differential pairs are connected in common with one end of said capacitance element and in common with said output terminal; and in said second connection state, the first input of each input pair of said first to mth differential pairs is made an inverting input and a second input of each input pair of said first to mth differential pairs is made a non-inverting input, the first inputs of the input pairs of said first to mth differential pairs are connected in common with said output terminal, and the second inputs of the input pairs of said first to mth differential pairs are connected to the one end of said capacitance element; a first period in which the first connection state is selected and a second period which follows the first period and in which the second connection state is selected forming a data output period.