Patent ID: 6990562

Claim:
A memory controller ([ 0084 ]; FIG. 1 , 100 ), comprising: a memory ([ 0087 ] & [ 0095 ], discussing “memory map 1100 ” and “MAR 1102 ”; FIG. 11 ) to store indications of data/strobe ratios ([ 0087 ]) that are required to access memory devices ([ 0083 ]), discussing “memory modules” and “RAM devices”) that are coupled to the memory controller, said memory being addressed during memory device accesses of said memory controller; subsets of strobe drivers ([ 0085 ], [ 0086 ], [ 0094 ]), wherein each of said subsets receives addressed indications of data/strobe ratios during write cycles of the memory controller, and wherein at least one of said subsets generates strobes in response to only some of said indications of data/strobe ratios; pluralities of strobe receivers and data receivers ([ 0184 ], [ 0185 ], [ 0186 ]; FIGS. 10 & 18 ); and a switching network ([ 0184 ], discussing “multiplexer 1812 ”) to associate at least some of said strobe receivers with at least some of said data receivers, wherein said switching network receives addressed indications of data/strobe ratios during read cycles of the memory controller, and wherein said switching network associates different ones of said strobe receivers with said data receivers in response to different indications of data/strobe ratios.