Patent ID: 8012814

Claim:
A method of forming a semiconductor structure comprising: masking a top semiconductor portion of a top semiconductor layer in a first device region and a portion of said semiconductor layer in a second device region of a semiconductor-on-insulator (SOI) substrate with a masking layer; etching exposed portions of said top semiconductor layer in said second device region employing said masking layer as an etch mask, wherein a top surface of a buried insulator layer is exposed around said masked portion of said top semiconductor layer in said second device region; forming a first hole and a second hole within said buried insulator layer around said masked portion of said top semiconductor layer in said second device region, wherein a top surface of a bottom semiconductor layer is exposed in each of said first hole and said second hole; and forming a source region and a drain region directly underneath said top surfaces of said bottom semiconductor layer, wherein said masked portion of said top semiconductor layer constitutes a gate electrode of a field effect transistor, a portion of said buried insulator layer located directly underneath said gate electrode constitutes a gate dielectric of said field effect transistor, and said source region and said drain region constitute diffusion regions of said field effect transistor, whereby current between said source region and said drain region is controlled by said gate electrode.