Patent ID: 7265024

Claim:
A method of forming a trenched DMOS device, the method comprising: providing an N+ silicon substrate with an N epitaxial layer thereon, and a P substrate in the N epitaxial layer extending to a top surface thereof; forming in a device region a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof, and in a bus region a field oxide layer on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate; forming a gate oxide layer in the DMOS trenches and extending to cover the top surface of the P substrate adjacent the DMOS trenches, and a gate oxide layer in the bus trench and extending to cover the top surface of the P substrate adjacent the bus trench; forming a plurality of polysilicon gates in the DMOS trenches, and a polysilicon bus in the bus trench, the polysilicon bus having a top surface disposed at a lower level than the top surface of the field oxide layer; forming a plurality of N+ source regions in the P substrate adjacent the DMOS trenches; forming a plurality of P+ diffused regions in the P substrate, each of the P+ diffused regions being interposed between two of the N+ source regions; forming a first isolation layer over the P substrate to cover the polysilicon gates, and a second isolation layer to cover the field oxide layer, the second isolation layer having an opening to expose the polysilicon bus; and forming a source metal contact layer on the first isolation layer, and a metal line atop the polysilicon bus, the source metal contact layer connecting to the N+ source regions and the P+ diffused regions.