Patent ID: 7193436

Claim:
A field programmable gate array (FPGA) logic head, comprising: two 3-input look-up tables, six data input ports, four control signals, two data output ports, two latches, two dynamic (standard) multiplexers, and seven hard-wired (programmable) multiplexers; and a configuration, wherein: 3-input look-up tables, in a split mode, are capable of being used as separate look-up tables, with or without latched outputs; latches are capable of being used either as separate latches or as one flip-flop; 3-input look-up tables are capable of forming a 4-input look-up table, wherein the 4-input look-up table can be utilized separately, in connection with a latch, or in connection with a flip-flop; a combination of a 3-input look-up table and a latch is capable of being utilized as a unit in a cascade chain of such units, where every other latch in the chain latches the output of its corresponding look-up table for one half of a clock cycle and the other latches of the chain latch the outputs of their corresponding look-up tables for the other half of the clock cycle; a combination of the 4-input look-up table and a latch is capable of being utilized as a unit in a cascade chain of such units, where every other latch in the chain latches the output of its corresponding look-up table for one half of a clock cycle and the other latches of the chain latch the outputs of their corresponding look-up tables for the other half of the clock cycle; and a grouping of a combinational logic and a latch of the logic head is capable of being utilized as a unit in a cascade chain of such units, where every other latch in the chain latches the output of its corresponding combinational logic for one half of the clock cycle and the other latches of the chain latch the outputs of their corresponding combinational logic for the other half of the clock cycle.