Patent ID: 8627049

Claim:
A system comprising: a circuit configured to execute a series of instructions, said circuit including a cache memory, said cache memory generating a cache miss stall triggered upon a read miss into said cache memory and a corresponding victim eviction stall triggered if said cache miss stall causes a writeback of a dirty cache entry to be replaced with new data in said cache memory; and an encoder configured to receive event data corresponding to the executed series of instructions, said event data describes at least processor stalls including said cache miss stall and said victim eviction stall, said encoder grouping the received event data into a plurality of groups, outputting a highest priority event for each group as prioritized event data and providing said highest priority event of each group to a computer external to said system, said encoder grouping said cache miss stall and said corresponding victim eviction stall into one of said plurality of groups and assigning a lower priority to said cache miss stall than to said corresponding victim eviction stall.