Patent ID: 8819394

Claim:
A processor, comprising: a cache having a plurality of cache levels including a level 1 (L1) cache; a plurality of address generation units (AGUs); a plurality of arithmetic logic units (ALUs); a plurality of floating point (FP) units; instruction fetch logic to fetch one or more instructions; instruction decode logic to decode the instructions; out-of-order logic to perform out-of-order execution of the instructions; a register file including a set of 128-bit packed data registers to store packed single-precision floating point (SPFP) data elements and packed integer data elements; register renaming logic to rename logical registers to physical storage locations within the register file; and a plurality of execution units to execute a compare instruction to compare a first plurality of packed unsigned integer data elements stored in a first packed data register with a second plurality of packed unsigned integer data elements stored in a second packed data register, and to store a plurality of data elements in a third packed data register, wherein the plurality of data elements are to represent results of the comparison between the first packed unsigned integer data elements and the second packed unsigned integer data elements, the plurality of data elements to indicate whether the first packed unsigned integer data elements and the second packed unsigned integer data elements share an equal ordering of at least some data elements.