Patent ID: 8306128

Claim:
A video system, comprising: at least one video signal source; a video decoder, coupled to receive a video signal from the at least one video signal source, the video decoder comprising: functional circuitry; a common data port, coupled to the functional circuitry, for outputting a plurality of data streams from the common data port in an interleaved fashion; and a clock generator for outputting a plurality of clock signals, each clock signal corresponding to one of the plurality of data streams output from the common data port; a data bus, coupled to the common data port; encoder circuitry, having a plurality of inputs coupled to the data bus, and having a plurality of clock inputs, each coupled to receive one of the plurality of clock signals; wherein the encoder circuitry comprises: a first encoder, having an input coupled to the data bus and having a clock input coupled to receive a first one of the plurality of clock signals, the first encoder for receiving a first one of the plurality of data streams synchronously with the first one of the plurality of clock signals; and a second encoder, having an input coupled to the data bus and having a clock input coupled to receive a second one of the plurality of clock signals, the second encoder for receiving a second one of the plurality of data streams synchronously with the second one of the plurality of clock signals.