Patent ID: 7663186

Claim:
A semiconductor device comprising: a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a JFET layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layer and having an impurity concentration higher than that of the high-resistance epitaxial layer; an LDD layer of the first-conductivity type formed in a surface portion of the high-resistance epitaxial layer and in the region sandwiched by the second-conductivity type base layer so as to be connected to said first-conductivity type JFET layer; a gate insulating film covering the LDD layer and formed on at least a junction of the LDD layer and the second-conductivity type base layer, in the gate insulating film an opening being formed so as to expose a part of a surface of the LDD; a control electrode formed on the gate insulating film; and; a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode, wherein the second-conductivity type base layers sandwiching said first-conductivity type JFET layer are disposed close to each other so that depletion from the second-conductivity type base layer becomes dominant.