Patent ID: 7995025

Claim:
A liquid crystal display device comprising: a plurality of liquid crystal pixels arrayed substantially in a matrix; a vertical driving circuit that selects rows of the liquid crystal pixels for video signal writing and for non-video signal writing; a horizontal driving circuit that writes a video signal in the liquid crystal pixels of a row selected for the video signal writing and a non-video signal in the liquid crystal pixels of a row selected for the non-video signal writing; and a control circuit that generates a control signal to prevent any overlap between the video signal writing of one row and the non-video signal writing of any other row, and controls operation timings of the horizontal driving circuit and the vertical driving circuit to perform the video signal writing for each row of the liquid crystal pixels in units of one row in one vertical scanning period and to perform the non-video signal writing for the liquid crystal pixels in units of at least one row after the first video signal writing, with a delay of a time shorter than the vertical scanning period, wherein the vertical driving circuit is configured to set a selection pattern for disabling any overlap between a selection period of selecting the liquid crystal pixels of each row for the video signal writing and a selection period of selecting the liquid crystal pixels of any other row for the non-video signal writing, based on the control signal from the control circuit, the liquid crystal pixels constitute a display panel together with a plurality of gate lines which are arranged along the rows of liquid crystal pixels and a plurality of pixel switching elements which are arranged near the liquid crystal pixels, and are turned on to allow the horizontal driving circuit to perform writing to the liquid crystal pixels of a selected row when the gate line corresponding to the liquid crystal pixels of the selected row is driven, and the vertical driving circuit includes a gate driver that receives first and second vertical start pulses supplied from the control circuit every vertical scanning period, starts selection of the rows of liquid crystal pixels for the video signal writing and selection of the rows of liquid crystal pixels for a black insertion writing in response to the first and second vertical start pulses, and outputs drive voltages to the gate lines which correspond to a selected row for the video signal writing and a selected row for the black insertion writing and are changed in sync with a vertical clock signal supplied from the control circuit, and an output switching unit that receives the drive voltages output from the gate driver for the video signal writing and for the black insertion writing, and switches the drive voltages upon changes in a combination of at least two enable signals, to output them in a time-division manner.