Patent ID: 7633144

Claim:
A semiconductor package comprising: a substrate, which has a plurality of conductive patterns formed on upper and lower surfaces of the substrate and a solder mask layer formed on the lower surface of the substrate; a semiconductor die adhered by adhesive to the upper surface of the substrate; a plurality of conductive wires for electrically connecting die pads on an upper surface of the semiconductor die to bond fingers on the upper surface of the substrate; encapsulant pressed downward over an upper portion of the semiconductor die so as to cover the semiconductor die placed on the upper surface of the substrate and the conductive wires, wherein the encapsulant covers only a first part of the semiconductor die and only a first part of the conductive wires leaving a second part of the semiconductor die and a second part of the conductive wires exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the conductive wires comprises the entire upper portion of the conductive wires above a plane defined by the upper surface of the semiconductor die; and a plurality of solder balls fusion-welded to the conductive pattern formed on the lower surface of the substrate.