Patent ID: 8237282

Claim:
A semiconductor device, comprising: a semiconductor substrate including a main surface; a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction, one end of each of said plurality of first interconnections connecting to a second interconnection; a plurality of third interconnections formed in said predetermined region and extending in said predetermined direction, one end of each of said plurality of third interconnections connecting to a fourth interconnection; and a fifth interconnection located at an edge of said predetermined region, and extending in said predetermined direction, wherein said plurality of first interconnections and said plurality of third interconnections are located in a first plane parallel to said main surface, said second interconnection, said fourth interconnection and said fifth interconnection are located in said first plane, one side of each of said plurality of first interconnections faces each of said plurality of third interconnections, and another side of each of said plurality of first interconnections faces each of said plurality of third interconnections, an insulating layer is formed on said main surface and fills in between each of said plurality of first interconnections, between each of said plurality of third interconnections, and between one of said plurality of first interconnections and said plurality of third interconnections and said fifth interconnection adjacent to each other, said plurality of first interconnections, said plurality of third interconnections, and said fifth interconnection are located in a direction substantially perpendicular to said predetermined direction, a capacitance is formed by said plurality of first interconnections, said second interconnection, said plurality of third interconnections, said fourth interconnection and said insulating layer formed between each of said plurality of first interconnections and each of said plurality of third interconnections, said plurality of first interconnections and said second interconnection are one of electrodes of said capacitance, said plurality of third interconnections and said fourth interconnection are the other of said electrodes of said capacitance, a plurality of polysilicon films are formed in said predetermined region between said semiconductor substrate and said first plane, and each of the first, second, third, fourth, and fifth interconnections includes a copper metal, said semiconductor substrate includes a first well layer of a first conductivity type extending in said main surface, said fifth interconnection electrically connected to said first well layer, said first well layer being fixed at one of a ground potential and a power supply potential.