Patent ID: 8471379

Claim:
A semiconductor device comprising: a semiconductor chip including a main surface, a back surface opposite to the main surface, a plurality of pads arranged over the main surface, and a plurality of low noise amplifiers arranged over the main surface, the plurality of the pads including a first pad and a second pad, the plurality of the low noise amplifiers including a first low noise amplifier and a second low noise amplifier for amplifying an inputted signal, the first pad and the second pad being electrically connected to the first low noise amplifier and the second low noise amplifier, respectively; a wiring substrate including a main surface, a back surface opposite to the main surface, a plurality of electrodes arranged over the main surface of the wiring substrate, the plurality of electrodes including a first electrode, a second electrode, a first GND electrode, a second GND electrode, and a third GND electrode; and a plurality of external terminals arranged over the back surface of the wiring substrate and being electrically connected to the plurality of electrodes; wherein the semiconductor chip is mounted over the main surface of the wiring substrate, and the first and second pads of the semiconductor chip are electrically connected the first and second electrodes of the wiring substrate, respectively, wherein the first and second electrodes are disposed between the first and second GND electrodes, and the third GND electrode is disposed between the first and second electrodes, wherein the wiring substrate further includes a first conductor pattern and a second conductor pattern which are disposed over the main surface of the wiring substrate, wherein the first conductor pattern electrically connects the first GND electrode and the second GND electrode to each other and surrounds the first and second electrodes in a plan view, wherein the second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view, and wherein the first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view.