Patent ID: 8284530

Claim:
An electrostatic discharge (ESD) protection circuit comprising: a control circuit configured to generate a signal indicating whether an input voltage on an input/output pad is excessive; a voltage divider configured to receive the signal from the control circuit and to divide the input voltage to generate a divided voltage; an inverter chain comprising multiple inverters, a first inverter configured to receive the divided voltage, at least two inverters configured to generate transistor control signals; and a plurality of transistors configured to receive the transistor control signals and, when the input voltage is excessive, to protect a protected circuit from the excessive input voltage; wherein the control circuit comprises: first and second transistors coupled in series; and third and fourth transistors coupled in series; wherein a gate of the first transistor is coupled to receive a voltage generated between the third and fourth transistors; wherein gates of the third and fourth transistors are coupled to receive a voltage generated between the first and second transistors; and wherein a gate of the second transistor is configured to receive a supply voltage.