Patent ID: 8322596

Claim:
A wiring substrate manufacturing method, comprising: preparing a wiring substrate including a core layer having a principal surface, a resin insulating layer and a conductor layer alternately laminated to form at least one laminated layer on the principal surface of the core layer, a solder resist layer including opening portions and formed on an outermost surface of the at least one laminated layer such that respective portions of an outermost conductor layer are exposed from the opening portions; forming a Sn-containing underlying layer, wherein the step of forming a Sn-containing underlying layer consists of forming the Sn-containing underlying layer on the respective portions of the outermost conductor layer by a plating process; and fusing the Sn-containing underlying layer by a heating process, then mounting solder balls directly on respective portions of the fused Sn-containing underlying layer, and then connecting the solder balls to the respective portions of the Sn-containing underlying layer.