Patent ID: 7736953

Claim:
A semiconductor memory comprising: a semiconductor substrate having drain regions and first source regions, each of the drain regions and first source regions comprising a diffused region formed in the semiconductor substrate and having a width, the drain regions and first source regions running in a first direction orthogonal to the width thereof, the semiconductor substrate further having at least one second source region formed therein, wherein the at least one second source region has a length that runs in a second direction orthogonal to the first direction, wherein the length of the at least one second source region is substantially longer than the width of the first source regions; bit lines running in the second direction and coupled to the drain regions in the semiconductor substrate by a plurality of bit line contacts; and a source metal wiring line formed above each of the at least one second source region, wherein one or more source contacts are formed to connect the source metal wiring line and the at least one second source region therebelow, and wherein each of the one or more source contacts is aligned in the first direction with one or more corresponding ones of the bit line contacts such that each of the one or more source contacts is in line in the first direction with the one or more corresponding ones of the bit line contacts.