Patent ID: 7904438

Claim:
A system comprising: one or more processors; a memory communicatively coupled to the processors for storing a first data value, a second data value, and a flag; one or more threads executed by the processors without employing locking, when the first data value and the second data value are both to be updated: update the first data value upon which the second data value is dependent such that the first data value and the second data value are required to be updated in that order such that the first data value is updated before the second data value is updated, where updating the first data value comprises changing or modifying contents of the first data value; set the flag associated with the first data value, such that the flag effectively prevents further updating of the first data value until the flag has been cleared; wait for a length of time, such that any reading of the first data value and the second data value is guaranteed to not see the second data value as updated unless the first data value is also seen as updated, where the length of time is waited for without employing locking; clear the flag after the length of time has elapsed, to permit further updating of the first data value; and, update the second data value dependent upon the first data value, where updating the second data value comprises changing or modifying contents of the second data value, wherein any reading of the first and the second data values occurs without having to check the flag and without having to employ locking.