Patent ID: 7920244

Claim:
A liquid crystal display device, comprising: an array substrate including: a gate line and a common line on a first substrate, the common line spaced apart from the gate line; a gate insulating layer on the gate line and the common line, wherein the gate insulating layer has first and second thicknesses, and wherein the first thickness is greater than the second thickness; a data line on the gate insulating layer and crossing the gate line to define a pixel region; a thin film transistor connected to the gate and data lines, the thin film transistor includes a gate electrode connected to the gate line, a semiconductor layer on the gate insulating layer having the first thickness, and source and drain electrodes on the semiconductor layer, the source electrode connected to the data line; and first and second height adjusters, the first height adjuster on the gate insulating layer having the first thickness over at least one of the gate line and the common line, the second height adjuster on the gate insulating layer having the second thickness between the gate line and the common line, the first and second height adjusters has a semiconductor pattern and a conductive pattern that are made of the same material as the semiconductor layer and the source and drain electrodes, respectively; an opposing substrate facing the array substrate; a liquid crystal layer between the array substrate and the opposing substrate; a gap spacer corresponding to the first height adjuster and contacting the array substrate and the opposing substrate; a first press-buffer spacer corresponding to the second height adjuster, contacting the opposing substrate and spaced apart from the array substrate; and a second press-buffer spacer contacting the opposing substrate, corresponding to and spaced apart from a portion of the array substrate that has the gate insulating layer having the second thickness, wherein a distance between the first press-buffer spacer and the array substrate is substantially less than a distance between the second press-buffer spacer and the array substrate.