Patent ID: 7504861

Claim:
A mixed-voltage system, comprising: a first circuit operative at a first power supply voltage; a second circuit operative at a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage; and a buffer circuit coupled between the first circuit and the second circuit and configured to receive the second power supply voltage, the buffer circuit comprising: a first node coupled to the first circuit; a second node coupled to the second circuit; an input circuit coupled between the first node and the second node, wherein the input circuit is configured to receive at least one signal from the first circuit at the first node and to provide at least one signal to the second circuit at the second node, the input circuit comprising: a first part coupled to the first node; and an inverter coupled between the first part and the second node; wherein the first part is configured to provide a signal having a voltage level of approximately GY to the inverter in response to a first signal on the first node and to provide a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node; and an output circuit coupled between the first node and the second node, wherein the output circuit is configured to receive at least one signal from the second circuit at the second node and to provide at least one signal to the first circuit at the first node; wherein the first part of the input circuit comprises a deep N-well type MOS transistor.