Patent ID: 7049221

Claim:
A method for manufacturing a semiconductor device for forming a wiring by a dual damascene method, the method comprising the steps of: forming a mask for a wiring trench patterned to be a wiring trenches pattern on an interlayer dielectric film; forming a mask for a via hole patterned to be a via holes pattern on the mask for the wiring trench by using a multilayered resist; forming a hole shallower than a thickness of the interlayer dielectric film in the interlayer dielectric film by processing the interlayer dielectric film, using the mask for the via hole; forming a wiring trench in the interlayer dielectric film by processing the interlayer dielectric film, using the mask for the wiring trench, and simultaneously forming a via hole by passing the hole through a base layer; and embedding a wiring material in the wiring trench and said via hole, wherein said step of forming the mask for the via hole includes the steps of: forming an organic film, an inorganic film, and a photoresist layer in this order on the mask for the wiring trench; processing the photoresist layer so as to be a plane shape to the via hole; processing the inorganic film so as to be a plane shape to the via hole by using the photoresist layer as a mask; and processing the organic film so as to be a plane shape to the via hole by using the inorganic film as a mask, and simultaneously removing the photoresist layer, and said step of forming the hole includes a step of processing the mask for the wiring trench so as to be a plane shape to the via hole by using the organic film as a mask, and simultaneously removing the inorganic film, and the organic film is removed while forming the hole.