Patent ID: 8581203

Claim:
A radiation-detecting device comprising: a first multi-bit storage cell at a substrate comprising: a first charge storage structure comprising a first nitride-containing layer overlying a first channel region at the substrate, the first charge storage structure configured to store a first electrical charge; a first conductive gate layer overlying the first charge storage structure; a first source/drain region adjacent the first channel region, wherein a portion of the first source/drain region underlies a portion of the first charge storage structure and a first bit storage region for storing information, wherein the first bit storage region is between the first source/drain region and the first conductive gate layer; a second source/drain region adjacent the first channel region, wherein a portion of the second source/drain region underlies a portion of the first charge storage structure and a second bit storage region for storing information, wherein the second bit storage region is between the second source/drain region and the first conductive gate layer; and a second multi-bit storage cell at the substrate comprising: a second charge storage structure comprising a second nitride-containing layer overlying a second channel region at the substrate, the second charge storage structure configured to store a second electrical charge, wherein the second nitride-containing layer has an average thickness that is different than an average thickness of the first nitride-containing layer and a capacity to store electrical charge that is different than a capacity to store electrical charge of the first nitride-containing layer; a second conductive gate layer overlying the second charge storage structure; a third source/drain region adjacent the second channel region, wherein a portion of the third source/drain region underlies a portion of the second charge storage structure and a third bit storage region for storing information, wherein the third bit storage region is between the third source/drain region and the second conductive gate layer; and a fourth source/drain region adjacent the second channel region, wherein a portion of the fourth source/drain region underlies a portion of the second charge storage structure and a fourth bit storage region for storing information, wherein the fourth bit storage region is between the fourth source/drain region and the second conductive gate layer.