Patent ID: 6937688

Claim:
A counter comprising: a plurality of state units for generating a state, each state unit having a corresponding clock end for receiving a clock having a plurality of pulses; wherein each said state unit is capable of updating its corresponding state when receiving different pulses from the clock according to a predetermined law while each said state unit receives the clock from its corresponding clock end; and a clock gating circuit electrically connected to the plurality of state units for selecting at least one first state unit and at least one second state unit from the plurality of state units according only to an initial value and providing a triggering clock to the clock end of each said at least one first state unit and withholding the triggering clock from the clock end of each said at least one second state unit, such that second states corresponding to each said at least one second state unit are held constant while each said at least one first state unit updates its state corresponding to said at least one first state unit according to different pulses of the triggering clock; wherein the clock gating circuit does not provide the triggering clock to each said at least one second state unit according to each state changed of the said at least one first state unit, and does not withhold the triggering clock from each said at least one first state unit; and a latch circuit connected to the clock gating circuit for storing the initial value.