Patent ID: 7365587

Claim:
A contention-free keeper circuit, comprising: a keeper circuit, wherein the keeper circuit includes a first node and a second node; a delay element for providing a time delay, the delay element having an input and an output, wherein the delay element input is coupled to one selected from the group consisting of the first node and the second node; a high-to-low contention elimination element coupled between the first node and a first supply, and coupled to the delay element output; and a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit, further wherein the first supply is greater than the second supply.