Patent ID: 7856523

Claim:
A computer implemented system comprising: one or more processors; a memory; and a Content Addressable Memory (CAM) controller communicatively coupled to the one or more processors and the memory, the CAM controller configured to process data for parallel execution via a CAM data structure associated with the memory, the data structure having a tag comprising bits, the bits in the tag being sub-divided into a plurality of bit fields to index pointers in a hierarchy of look up tables stored in the memory, wherein the CAM controller is further configured to access the CAM data structure and successively search the hierarchy of look up tables associated with the plurality of bit fields, wherein: each entry in each of the look up tables of a high level in the hierarchy is associated with a pointer to another look up table of a low level in the hierarchy; each of the plurality of bit fields corresponds to a look up table in the hierarchy of the look up tables; each entry in a look up table of a lowest level in the hierarchy that corresponds to a last bit field in the tag is associated with a bin that stores multiple data entries in the memory and is configured to associate the multiple data entries to the tag; and each tag is associated with presence bits stored with each tag to indicate whether a data value associated with the respective tag is: not present, present but not cached, or present and cached.