Patent ID: 7836276

Claim:
A processing unit comprising: a first section for issuing, for each clock cycle at a first clock rate, one instruction and for collecting multiple sets of operands associated with the one instruction, wherein an active mask indicates a portion of processing threads in a group of threads that execute the one instruction in parallel, the portion of processing threads including a first processing thread that is included in the group of threads and does execute the one instruction but not including a second processing thread that is included in the group of threads and does not execute the one instruction; and a second section including first and second execution pipelines, each including two or more parallel data paths, wherein each one of the two or more parallel data paths corresponds to a different bit in the active mask, and wherein the operands and the active mask are supplied to one of the two execution pipelines, wherein the second section operates at a second clock rate that is different from the first clock rate, the first section includes an instruction buffer comprising a plurality of instructions of at least two types, the first execution pipeline is configured to execute instructions of a first type, and the second execution pipeline is configured to execute instructions of a second type, the first section is configured to select one of the instructions in the instruction buffer as the one instruction for each clock cycle at the first clock rate, and wherein an instruction of a different type is selected on alternating clock cycles.