Patent ID: 8205125

Claim:
An integrated circuit (IC) comprising: a plurality of memory elements operable as a plurality of scan chains, said plurality of scan chains grouped into a plurality of partitions whereby scan chains of each partition are enabled together via a corresponding partition enable signal, each scan chain connected to a Test Data Input to receive test data; and a test controller including a plurality of blocks, each block corresponding to one of said plurality of partitions, each block including a delay register storing digital data therein having a input receiving a digital data input and an output generating a digital data output, a count register storing a digital count therein having an input connected to said output of said corresponding delay register and an output generating a digital data output, a delay element having a first input receiving said digital data stored in a corresponding delay register, a second input and an output generating a digital data output having a predetermined state a predetermined time after receiving an input at said second input, said predetermined time corresponding to said digital data stored in a corresponding delay register, a counter having a trigger input connected to said output of said delay element and a count output generating a digital output corresponding to a count therein, said counter counting beginning upon receipt of a predetermined state at said trigger input, a comparator connected to said count register and said counter comparing said digital count stored in said count register with said count of said counter and generating a match signal when said digital count stored in said count register matches said count of said counter; an inverter having an input connected to receive said match signal of said comparator and an output, and an AND gate having a first input connected to receive said output of said delay element, a second input connected to receive said output of said inverter and an output generating said partition enable signal to a corresponding partition of scan chains, said plurality of blocks of said test controller disposed serially from a first block through a last block whereby said input of said delay register of said first block receives said Test Data Input, said input of said delay register of each subsequent block receives said output of said count register of a prior block, said input of said delay element of said first block receives a global start signal and said input of said delay element of each subsequent block receives said match signal of said comparator of a prior block; and said Test Data Input being received from a set of pins connected to an external tester, wherein the number of said set of pins is less than the number of said plurality of scan chains.