Patent ID: 7432746

Claim:
A buffer for interfacing complementary input signals having complementary metal oxide semiconductor (CMOS) voltage levels to a circuit operating with current mode logic (CML) voltage levels, the buffer comprising: a first branch receiving a first one of the complementary input signals and outputting a first complementary output signal having CML voltage levels, the first branch including, a first PMOS transistor having a first terminal connected to a first CMOS supply voltage, a second terminal providing the first complementary output signal, and a control terminal receiving the first complementary input signal, and a first NMOS transistor and a second PMOS transistor connected in series between the second terminal of the first PMOS transistor and a second CMOS supply voltage, the first NMOS transistor having a control terminal receiving the first complementary input signal, and the second PMOS transistor having a control terminal receiving a first branch bias voltage; a second branch receiving a second one of the complementary input signals and outputting a second complementary output signal having CML voltage levels, the second branch including, a third PMOS transistor having a first terminal connected to the first CMOS supply voltage, a second terminal providing the second complementary output signal, a control terminal receiving the second complementary input signal, and a second NMOS transistor and a fourth PMOS transistor connected in series between the second terminal of the third PMOS transistor and the second CMOS supply voltage, the second NMOS transistor having a control terminal receiving the second complementary input signal, and the fourth PMOS transistor having a control terminal receiving a second branch bias voltage.