Patent ID: 6993617

Claim:
A system-on-a-chip device consisting of: an on-chip processor; an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor; an on-chip peripheral component interconnect (PCI) input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM); an on-chip arbiter capable of communicating with the component interconnect (PCI) input/output (I/O) bus; an on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip expansion bus (E-bus) controller capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip Ethernet controller; an on-chip universal serial bus Host controller; an on-chip universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip I 2 C universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip GPIO capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip joint test access group (JTAG) device; an on-chip AC97 interface capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus; an on-chip private flash bus capable of latching configuration options at power-up; a first on-chip peripheral component interconnect (PCI) controller capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus, the on-chip memory controller, the on-chip processor, and the on-chip dynamic random access memory (DRAM); a second on-chip peripheral component interconnect (PCI) controller capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus, the on-chip E-bus controller, the on-chip Ethernet controller, and the on-chip USB Host controller; a first on-chip phase-lock loop (PLL) clock generator capable of sending a signal to the on-chip processor; an a second on-chip phase-lock loop(PLL) clock generator capable of sending a signal to the at least one on-chip peripheral component interconnect (PCI) controller.