Patent ID: 7715247

Claim:
A memory device, comprising: a memory cell including a pass transistor and a one-time programmable storage element, wherein the one-time programmable storage element is composed of a capacitor which is shorted or open for storing a data; and a first dynamic circuit serving as a local sense amp connecting to the memory cell through a local bit line, wherein the first dynamic circuit includes a reset transistor for resetting the local bit line, a local amplify transistor for reading the local bit line, where the local amplify transistor is serially connected to a local select transistor, a write transistor for connecting the local bit line to a write bit line; and a second dynamic circuit serving as a segment sense amp connecting to the local select transistor through a segment bit line, wherein the second dynamic circuit is composed of a pre-set transistor for pre-setting the segment bit line, a segment amplify transistor for reading the segment bit line where the segment amplify transistor is serially connected to a segment select transistor connecting to a global bit line; and a first tri-state inverter serving as a global amplify circuit of a global sense amp connecting to the global bit line, wherein the global sense amp includes a read circuit, a data transfer circuit, a returning buffer and a write circuit; and the read circuit includes the first tri-state inverter for reading the global bit line and a reset transistor for resetting the global bit line; and the data transfer circuit includes a second tri-state inverter for bypassing a write data and a read inverter for reading a common node which is connected to the first tri-state inverter and the second tri-state inverter; and the write circuit includes a data receive circuit for receiving the write data and a write transfer circuit for transferring an output of the data receive circuit to the write bit line; and the returning buffer includes an inverting buffer for buffering a returning read path connecting to the read inverter; and an output latch circuit receiving and storing an output from the returning buffer; and a latch control circuit generating a locking signal which is generated by a reference signal based on at least a reference memory cell, in order to lock the output latch circuit.