Patent ID: 7728386

Claim:
A semiconductor integrated circuit device having a CMOS integrated circuit capable of carrying out an operation at a comparatively high supply voltage, comprising: a first MOS type transistor having a drain profile to come in contact with a gate through a low concentration region having an impurity concentration which is equal to or lower than a predetermined concentration at a drain end; and a second MOS type transistor which has the same polarity as the first MOS type transistor and which is connected to a gate of the first MOS type transistor, wherein a gate voltage is applied to the gate of the first MOS type transistor through the second MOS type transistor to which a predetermined potential (a shielding voltage) is applied, the first and second MOS type transistors are N type and the source of the first MOS type transistor is connected to a first power supply; said semiconductor integrated circuit device further comprising: a composite type MOS semiconductor unit which has a drain profile to come in contact with the gate through a low concentration region having a predetermined length or more and predetermined concentration or less at a drain end of a third MOS type transistor and in which a common gate voltage to the first MOS type transistor is applied to a gate of the third MOS type transistor through a fourth MOS type transistor which has the same polarity as the third MOS type transistor to which a second predetermined potential (a second shielding voltage) is applied, the third and fourth MOS type transistors having a P type and a source of the third MOS type transistor being connected to a second power supply, said semiconductor integrated circuit device further comprising: a signal output end, the drain end of the first MOS type transistor and the drain end of the third MOS type transistor are directly connected to the signal output end.