Patent ID: 8779507

Claim:
An insulated gate semiconductor device comprising: a first semiconductor layer of a first general conductivity type; a channel layer of a second general conductivity type disposed on the first semiconductor layer; a plurality of first trenches extending in a first direction in the plan view of the semiconductor device, the first trenches penetrating through the channel layer and reaching the first semiconductor layer; a plurality of second trenches extending in a second direction in the plan view, each of the second trenches connecting a corresponding pair of first trenches in the plan view; a first insulating film provided on inner walls of the first trenches and the second trenches; a gate electrode disposed in the first trenches and the second trenches; a second insulating film covering the gate electrode; a source region of the first general conductivity type formed in a surface portion of the channel layer, the source region extending in the second direction in the plan view; and a body region of the second general conductivity type formed in a surface portion of the channel layer so as to be in contact with the source region and a corresponding first trench; wherein two of the first trenches and two of the second trenches define a cell which makes transistor operation possible, and the cell comprises two body regions of the second general conductivity type formed in a surface portion of the channel layer.