Patent ID: 8189413

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a first bit line through which a signal read out from a selected memory cell of the memory cell array is transmitted; a first sense amplifier circuit of single-ended configuration including an amplifying element amplifying a signal voltage of the first bit line so as to convert the signal voltage into an output current; and a control circuit controlling a test operation to measure a current flowing in the first sense amplifier circuit independently of currents flowing in other circuit portions, wherein a plurality of the first bit lines and a plurality of the first sense amplifier circuits are provided, and the control circuit controls the test operation to measure a total current flowing in the first sense amplifier circuits, and wherein the plurality of the first sense amplifier circuits are connected to a first ground potential which is independent from ground potentials connected to other circuit portions, and the first ground potential is capable of being externally connected via a terminal.