Patent ID: 7793068

Claim:
A mass storage memory system, comprising: a flash device for interfacing with a host, the flash device including re-programmable nonvolatile memory cells, the memory cells being arranged in a plurality of blocks that are erasable together; and the flash device further including a controller including a microprocessor that is adapted to receive files of data identified by the host to the flash device using file identifiers via a first interface and the controller causes a received data file to be stored in one or more memory blocks; and the controller receives data identified by the host to the flash device using logical addresses via a second interface and stores the received data in one or more memory blocks, wherein the data written via the first interface is indexed using the file identifiers so that the data is accessible via the second interface and the first interface; and data received via the second interface is indexed so that the data can be accessed via the first interface and the second interface; wherein the first interface is a direct data file storage (DFS) interface where data files received from the host are identified by the host to the flash device using the file identifiers and the second interface is a logical interface where data files received from the host are identified by the host to the flash device using the logical addresses.