Patent ID: 8510691

Claim:
A semiconductor verification apparatus for loading a logical value of a signal in a semiconductor device using the semiconductor device which comprises loading means capable of loading from outside logical values of memory elements in the semiconductor device, the apparatus comprising: memory element calculation means for calculating a logical formula for calculating the logical value of the signal described in the signal information treating the states of the memory elements being used as logical variable number therein, based on signal information in which the signal in the semiconductor device is described and circuit information in which a logical structure in the semiconductor device and a relation of connection thereof are described; loading control means for controlling the loading means to acquire only the logical values of the memory elements existing in the logical formula calculated by said memory element calculation means of the semiconductor device; logical value calculation means for calculating the logical value of the signal described in the signal information based on the logical formula calculated by the memory element calculation means and the logical values of the memory elements acquired by the loading control means; and central control means for controlling the memory element calculation means, the loading control means and the logical value calculation means to obtain the logical value of the signal described in the signal information.