Patent ID: 8455344

Claim:
A method of manufacturing a non-volatile memory device, the method comprising: forming field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate; forming a tunnel insulating layer on the active region; forming a charge trapping layer on the tunnel insulating layer; forming a blocking layer on the charge trapping layer; forming first insulating layers on upper surfaces of the field insulating layer patterns; forming a sacrificial layer on the charge trapping layer and field insulating layer patterns, the sacrificial layer filling spaces between adjacent field insulating layer patterns; performing a planarization process to remove the sacrificial layer, the first insulating layers, and the upper portions of the field insulating layer patterns; forming a conductive layer on the blocking layer, a lowermost surface of the conductive layer facing the blocking layer being substantially planar; and forming a word line structure on the blocking layer, on the first insulating layers, and on the conductive layer.