Patent ID: 7157312

Claim:
A method for manufacturing a surface mount package for a multi-chip device comprising the steps of: forming a planar leadframe having first and second die pads, corresponding contacts and leadouts and a trimable marginal edge temporarily securing the die pads, contacts and leadouts together in a planar structure; mounting an ASIC chip to the first die pad of the leadframe and wirebonding the chip to corresponding contacts on the leadframe; forming a body by over molding the ASIC and a portion of the leadframe to isolate the ASIC chip from environmental effects, and forming a chamber in the body adjacent to the second die pad having an opening for receiving a cover; mounting a sensor chip to the second die pad of the leadframe and wirebonding the sensor chip to the corresponding contacts on the leadframe; covering the opening with an apertured cover; sealing the cover therein; and generating a first plane and a second plane by deforming the leadframe, wherein the first die pad is positioned on and adjacent to the first plane, wherein the second die pad is positioned on and adjacent to the second plane, and wherein the second plane is offset from the first plane.