Patent ID: 7218544

Claim:
A mask ROM comprising: a plurality of bit lines; a plurality of word lines disposed so as to intersect with the plurality of bit lines; a plurality of bit cells provided along with the plurality of bit lines or the plurality of word lines, each of the bit cells being formed of a first conductivity type cell transistor having a gate electrode connected to one of the plurality of word lines wherein data is recorded by connection/disconnection between a drain of the cell transistor and one of the plurality of bit lines wherein if among the plurality of word lines, word lines located adjacent to each other are a first word line and a second word line, respectively, the mask ROM further includes a source node commonly connected to respective sources of cell transistors each having a gate electrode connected to the first word line or the second word line, and wherein if among the cell transistors in the bit cells, a transistor connected to a bit line is selected from the plurality of bit lines and the source node is selected in reading out data, a current flows from the selected bit line to the source node via the selected cell transistor; the mask ROM further comprising a first power supply line, wherein in reading out data, the selected bit line is connected to a bit line connected to a non-selected cell transistor via the selected cell transistor and the source node, or the first power supply line; and the mask ROM still further comprising a first conductivity type dummy cell transistor provided between the source node and the first power supply line and having a gate connected to the first word line or the second word line connected to the gate of the selected cell transistor and a drain connected to the source nodes wherein the first conductivity type dummy cell transistor conducts a voltage level of the first power supply line to the source node when a cell transistor connected to a word line which the first conductivity type dummy cell is connected to is selected.