Patent ID: 7786589

Claim:
A semiconductor device, comprising: a semiconductor substrate having a semiconductor element on an upper surface; a first wiring layer provided on or above the semiconductor substrate, the first wiring including a first dielectric film and a first wiring; a second wiring layer on or above the semiconductor substrate, the second wiring layer including a second dielectric film and a second wiring; a metal ring provided in the second dielectric film and configured to form a closed loop in a plan view; a first region surrounded by the metal ring in a plan view; a second region provided outside of the metal ring in a plan view; a through hole provided in the first wiring layer and the second wiring layer and penetrating the first wiring layer and the second wiring layer, and provided in the first region, the through hole provided in the closed loop of the metal ring in the second wiring layer; and an air gap provided in the first dielectric film in the second region.