Patent ID: 7511579

Claim:
A phase lock loop (PLL), comprising: a first divider configured to receive a reference signal and to divide the reference signal by a value R to obtain a divided signal; a phase/frequency detector (PFD) configured to compare the divided signal and a feedback signal to generate a compared signal; a loop filter, coupled to the phase/frequency detector configured to generate an operating voltage; a voltage controlled oscillator (VCO) configured to select one of a plurality of operating curves for oscillation based on a selection signal, and to generate an oscillation signal based on the operating voltage, wherein each operating curve corresponds to a frequency range; a second divider configured to divide the oscillation signal by a value N to obtain the feedback signal; a controller configured to operate in an initial mode to increase the values of R and N by a factor of A after the PLL is initially charged and to then recursively determine the selection signal by calculating differences between the feedback signal and the divided signal based on a reference clock; wherein when the selection signal converges to a stable value, the PLL is configured to switch to a normal mode to operate on one of a plurality of predetermined operating curves, the operating curve corresponding to the selection signal, the PLL further comprising: a third divider configured to divide the oscillation signal by M to generate the reference clock in the initial mode; wherein the third divider and the controller are disabled in the normal mode.