Patent ID: 7977766

Claim:
An anti-fuse structure formed using a substrate composed of a semiconductor material and having a top surface, the anti-fuse structure comprising: a trench including a bottom wall and a plurality of sidewalls that extend from the top surface of the substrate to the bottom wall, the sidewalls of the trench arranged with a cross-sectional geometrical shape that is independent of position between the bottom wall of the trench and the top surface of the substrate; a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench; a conductive plug in the trench; and a dielectric layer on the sidewalls of the trench, the dielectric layer disposed between the conductive plug and the doped region, wherein the dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes an irreversible breakdown of the dielectric layer within a region of the trench to electrically connect the doped region irreversibly with the conductive plug.