Patent ID: 8617941

Claim:
A method of fabricating a transistor, the method comprising the steps of: providing a substrate; forming a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; forming a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; selectively depositing a conformal high-k gate dielectric layer on the patterned organic buffer layer, wherein the patterned organic buffer layer is configured to serve as a nucleation and adhesion layer for the high-k gate dielectric layer such that the conformal high-k gate dielectric layer is formed selectively on exposed top and side surfaces of the patterned organic buffer layer; and forming metal source and drain contacts on the portions of the carbon-based material that serve as the source and drain regions of the transistor and a metal top-gate contact on the conformal high-k gate dielectric layer.