Patent ID: 7844828

Claim:
A computer-implemented method for verifying execution of a program comprising a plurality of code portions to be verified, the method comprising: entering a first code portion, wherein the first code portion comprises a first plurality of instructions beginning with a first entry point and ending with a first instruction that creates a first branch in the execution flow; executing, by a processor, the first code portion; calculating a first checksum during the execution of the first code portion, wherein the first checksum is calculated using first operating code, wherein at least one of the first plurality of instructions comprises the first operating code; comparing the first checksum to a first pre-calculated checksum during execution of the first instruction that creates the first branch in the execution flow and prior to exiting the first code portion, wherein the first pre-calculated checksum is passed as a parameter of the first instruction, wherein the first pre-calculated checksum is calculated, during compilation of the program, using the first operating code, wherein the first operating code is generated during compilation of the program; exiting the first code portion and entering the second code portion when the first checksum equals the first pre-calculated checksum, wherein the second code portion comprises a second plurality of instructions beginning with a second entry point and ending with a second instruction that creates a second branch in the execution flow; and detecting an anomaly when the first checksum is not equal to the first pre-calculated checksum, wherein detection of the anomaly results in the second code portion remaining unexecuted.