Patent ID: 7772867

Claim:
A semiconductor device, comprising: a semiconductor substrate; an application circuit and one or more test circuits formed on or in the substrate, the test circuits and the application circuit being electrically isolated from each other, wherein each test circuit comprises: a plurality of MOSFET transistors connected in parallel; the plurality of MOSFET transistors comprising alternating sources and drains arranged serially along a first direction in an elongated first common active region of the substrate; gate electrodes formed over the first common active region at positions respectively separating the sources and drains and elongated in second directions generally orthogonal to the first direction; an elongated second common active region of the substrate spaced from and generally parallel to and coextensive with the first common active region; and substrate active region extensions extending from respective each one of one of the sources or drains of the first common active region to the second common active region in third directions generally orthogonal to the first direction; a first contact pad commonly coupled to each gate electrode; a second contact pad commonly coupled to respective substrate terminals locally associated with each transistor; and a third contact pad commonly coupled to each one of the other of the sources and drains of the first common active region; wherein the test circuit comprises one or more stress increasing design features not present in the application circuit.