Patent ID: 8884270

Claim:
A field-effect transistor comprising: a substrate layer; an n-type drift layer on the substrate layer; an n-type channel layer on the drift layer; a plurality of raised regions on the channel layer, wherein the raised regions have an upper surface and are spaced from one another and define a trench between adjacent raised regions; an n-type source layer on the upper surface of the raised regions, wherein the n-type source layer has a higher dopant concentration than the raised regions; implanted p-type gate regions in the trenches between the raised regions; and a source contact layer extending over the plurality of raised regions; wherein the source contact layer is in electrical contact with the n-type source layer on one or more of the plurality of raised regions to form one or more electrically active source regions and wherein the source contact layer is not in electrical contact with the n-type source layer on one or more of the plurality of raised regions to form electrically inactive source regions.