Patent ID: 6851102

Claim:
A computer implemented method for supporting a register-transfer-level (RTL) design having descriptions of a first module and a second module of a semiconductor integrated circuit wherein outputs of the second module feed the first module, comprising: storing the descriptions of the first and second modules into a memory; determining a first number of module-to-module connections between the first module and the second module that are connected to a first sequential circuit via a combinational circuit within the first module; obtaining a decrement number by subtracting 1 from the first number; determining a second number of module-to-module connections connected to the first sequential circuit and to a second sequential circuit within the first module; using the second number as an increment number; comparing the decrement number with the increment number; and if the decrement number is greater than the increment number, then identifying the first sequential circuit and the combinational circuit as candidates for relocation to the second module.