Patent ID: 8008788

Claim:
A semiconductor device comprising a semiconductor chip: the semiconductor chip including: an alignment mark formation region in which an alignment mark is formed, the alignment mark being used for positioning when mounting the semiconductor chip over a mounting substrate; and an integrated circuit formation region in which an integrated circuit is formed; the alignment mark having a mark region in which a mark is formed, and a background region surrounding the mark region; the integrated circuit formation region having a plurality of element isolation regions formed over a semiconductor substrate, a MISFET formed in an active region partitioned by the element isolation regions, and wirings formed over the semiconductor substrate and the MISFET; the wirings being formed across a plurality of layers; and the alignment mark being formed in the same layer as an uppermost wiring layer, wherein a first pattern is formed in the alignment mark formation region, the first pattern including a portion formed in a layer lower than the alignment mark, wherein one wiring layer is formed in a layer lower than the uppermost wiring layer in the integrated circuit formation region, and wherein the portion of the first pattern and the one wiring layer are formed in the same layer.