Patent ID: 8178981

Claim:
A semiconductor device comprising: a plurality of first bonding pads, each of the plurality of first bonding pads has a first metal and a plurality of second metals, each of the plurality of second metals which has a first linear pattern having a plurality of stripes with a rectangular shape having a long side and a short side in a plan view, is arranged directly under the first metal, and is connected with the first metal; a plurality of second bonding pads, each of the plurality of second bonding pads has a third metal and a plurality of fourth metals, each of the plurality of third metals which has a second linear pattern having a plurality of stripes with a rectangular shape having a long side and a short side in a plan view, is arranged directly under the third metal, and is connected with the third metal concerned; and a passivation film which covers a first side wall and a first top surface of the first metal of each of the plurality of first bonding pads and a second side wall end a second top surface of the third metal of each of the plurality of second bonding pads and has a plurality of first openings and a plurality of second openings, each of the plurality of first openings exposing a part of the first top surface of the first metal of each of the plurality of first bonding pads, each of the plurality of second opening exposing a part of the second top surface of the third metal of each of the plurality of second bonding pads, wherein in the plan view, the first bonding pads are arranged uniformly and in order along a first long-side direction of the second metal, wherein in the plan view, the second bonding pads are arranged uniformly and in order along a second long-side direction of the fourth metal, the second long-side direction being perpendicular to the first long-side direction, wherein width W and interval D in a bottom of the second metals satisfy a relation: W≦D≦ 2 W, wherein in the plan view, a first input buffer and a first output buffer are formed below each of the plurality of first bonding pads, each of the first input bluffer and the first output buffer including a first transistor, the first input buffer receiving a first signal from the first bonding pad and outputting the first signal to an internal circuit, the first output buffer receiving a second signal from the internal circuit and outputting the second signal to the first bonding pad, and wherein in the plan view, a second input buffer and a second output buffer are formed below each of the plurality of second bonding pads, each of the second input buffer and the second output buffer including a second transistor, the second input buffer receiving a third signal from the second bonding pad and outputting the second signal to the internal circuit, the second output buffer receiving a fourth signal from the internal circuit and outputting the fourth signal to the second bonding pad.