Patent ID: 7585746

Claim:
A method of fabricating a device comprising: providing a substrate with a top substrate surface, the substrate including cell and non-cell regions; forming a charge storage stack on the substrate, wherein the charge storage stack comprises at least a tunneling layer on the substrate and a storage layer on the tunneling layer; forming trench isolation regions in the substrate in the cell and non-cell regions, the trench isolation regions having top isolation surfaces coplanar with a top surface of the charge storage stack; removing portions of the charge storage stack in the non-cell region, wherein removing forms top isolation surfaces in the non-cell region which are coplanar with top substrate surface; forming a gate dielectric layer in the non-cell region; forming a gate layer on the substrate over the storage layer and gate dielectric layer in the cell and non-cell regions; and patterning layers on the substrate to form gate stacks in the cell and non-cell regions.