Patent ID: 8089801

Claim:
A semiconductor memory device, comprising: a semiconductor substrate of a first conductivity type; first and second regions doped with a second conductivity type for a source and a drain formed on said semiconductor substrate; a channel region recessed into said semiconductor substrate and disposed between said first and second doped regions in said semiconductor substrate; a first gate dielectric layer disposed over said channel and extending over portion of said source and drain; an electrically conductive material floating gate as electrical storage node disposed over said first gate dielectric layer; a p-n junction diode disposed between said drain and said floating gate; electrically conductive materials as source-connection plug and drain-connection plug connecting source and drain to external electrical terminals a second gate dielectric layer disposed between said p-n junction diode and said drain-connection plug; a third gate dielectric layer disposed over said floating gate and extending over portion of said p-n junction diode; and a control gate disposed over said third dielectric layer; wherein a gated diode is formed by said p-n junction diode, said second gate dielectric, and said drain connection plug as the gate of said gated diode.