Patent ID: 6973421

Claim:
A BZFLASH subcircuit configured to simulate alongside an impedance controlled buffer and provide BZ codes dynamically to the impedance controlled buffer, said subcircuit comprising: a BZVREF subcircuit configured to provide a reference voltage equal to the I/O supply voltage divided by two; a P — FLASH subcircuit configured to receive the reference voltage from the BZVREF subcircuit and configured to supply a plurality of binary output codes; an N — FLASH subcircuit configured to receive the reference voltage from the BZVREF subcircuit, said N — FLASH subcircuit connected to said P — FLASH subcircuit and configured to supply a plurality of binary output codes to the P — FLASH subcircuit; a first dither block connected to the N — FLASH subcircuit, said first dither block configured to receive a dither count and the plurality of binary output codes from the N — FLASH subcircuit and configured to subtract the dither count from the plurality of binary output codes received from the N — FLASH subcircuit and provide output codes in both a binary and a decimal voltage format; and a second dither block connected to the P — FLASH subcircuit, said second dither block configured to receive a dither count and the plurality of binary output codes from the P — FLASH subcircuit and configured to add the dither count from the plurality of binary output codes received from the P — FLASH subcircuit and provide output codes in both a binary and a decimal voltage format.