Patent ID: 8605181

Claim:
A sensor formed in a substrate of a first conductivity type, the sensor comprising readout circuitry, a memory gate control circuit and an array of pixels arranged in rows and columns, each pixel comprising: a photodiode formed in the substrate; a sense node formed in the substrate; a transfer gate coupled between the photodiode and the sense node; and a memory gate insulatively disposed over the substrate, said memory gate coupled between the photodiode and the transfer gate, the memory gate including a memory gate electrode having a surface disposed on the substrate, wherein said substrate comprises no region of a conductivity type opposite the first conductivity type underneath said memory gate electrode; wherein the memory gate control signal circuit includes generator to generate a memory gate control signal that is coupled to the memory gate electrode of all pixels in the array and to switch alternately between a first voltage measured relative to a potential of the substrate and a second voltage measured relative to the potential of the substrate, the second voltage being intermediate between the first voltage and the potential of the substrate, the first voltage being sufficiently different from the potential of the substrate to vertically transfer substantially all photo charge in the photodiode into the memory gate towards the surface of the memory gate electrode in each pixel of the array of pixels, the second voltage being both (1) sufficiently different from the potential of the substrate to hold underneath the memory gate at the surface of the memory gate electrode all photo charge transferred into the memory gate in each pixel of the array of pixels and (2) sufficiently different from the first voltage to block transfer of photo charges in the photodiode into the memory gate in each pixel of the array of pixels; and wherein the readout circuitry includes mean for reading out substantially all photo charge transferred into the memory gate in each pixel of the array of pixels on a row-by-row basis while the memory gate control signal is at the second voltage.