Patent ID: 8447800

Claim:
A method of executing a nonfused floating-point multiply-add instruction in a processor to account for one or more of a plurality of denormal inputs and a denormal product comprising: performing, in a control logic of the processor: substituting a value zero for an original addend of the floating-point multiply-add instruction, inserting after the floating-point multiply-add instruction a floating-point add instruction having the original addend of the floating-point multiply-add instruction, inspecting a multiplier and a multiplicand of the floating-point multiply-add instruction, making a first determination, based on the inspecting, that the product of the multiply operation will not be a denormal number, making a second determination, based on the inspecting, that none of the inputs to the multiply operation are denormal numbers, and in response to the first and second determination, replacing the zero addend with the original addend of the multiply-add instruction, and converting the floating-point add instruction to a no operation (NOP); and performing the floating-point multiply-add instruction in a floating-point multiplier and a floating-point adder of the processor.