Patent ID: 7288445

Claim:
A method for forming a transistor, the method comprising the steps of: a) providing a semiconductor substrate; b) patterning the semiconductor substrate to provide a first body edge; c) providing a first gate structure of a first fermi level adjacent said first body edge; d) patterning the semiconductor substrate to provide a second body edge, the first and second body edges of the semiconductor substrate defining a transistor body; and e) providing a second gate structure of a second fermi level adjacent said second body edge, wherein the step of forming a substantially uniform dopant concentration density in the transistor body comprising forming a dopant concentration between 0.3 N A and 3 N A , where N A is defined as: N A = 2 ⁢ ɛ ⁢ ox ⁢ Eg Toxs · ( Toxs + λ ) [ ( Toxs ) + Toxw + Tsi · ɛ ox ɛ si ] 2 wherein ∈ ox =permittivity of the gate dielectric, wherein E Si =permittivity silicon, wherein T 0XS =insulator thickness with the gate electrode of the fermi level more attractive to the inversion channel carriers, wherein T 0XW =insulator thickness with the gate electrode of the fermi level less attractive to the inversion channel carriers, wherein T si =transistor body thickness, wherein λ=depth of the charge centroid of a inversion layer in a silicon body beneath the surface adjacent to a strong gate, and wherein E g =band-gap energy of silicon.