Patent ID: 7830484

Claim:
An inspection method using a TFT substrate comprising: preparing a substrate defined by a display area and a non-display area outside the display area; depositing a metal on an entire surface of the substrate and selectively removing the metal to form gate lines and common lines in the display area of the substrate, pad lines extended from the gate lines to the non-display area, a shorting inspection bar connected to the pad lines to cross the pad lines, and a plurality of signal inspection bars spaced apart from the shorting inspection bar at a predetermined interval and substantially parallel with the shorting inspection bar, wherein the common lines, the pad lines are substantially parallel with the gate lines and wherein the common lines are disposed between the gate lines; inspecting short between the gate lines and the common lines by applying voltage signals to the shorting inspection bar; depositing an insulating layer on the entire surface of the substrate including the gate lines, the common lines, the pad lines, the shorting inspection bar and the signal inspection bars; forming pad line contact holes, signal inspection bar contact holes, and shorting bar cutting holes by selectively removing the insulating layer; burying the pad line contact holes, the signal inspection bar contact holes, and the shorting bar cutting holes to deposit a transparent electrode on an entire surface of the insulating layer; and forming transparent electrode patterns by selectively removing the transparent electrode to connect the pad lines with the one of the signal inspection bars, and forming shorting bar patterns by removing the transparent electrode on the shorting bar cutting holes and the shorting inspection bar below the shorting bar cutting holes.