Patent ID: 8004435

Claim:
A discrete-time circuit that samples an inputted analog signal a plurality of number of times at different times respectively and averages results of a plurality of samplings, the discrete-time circuit comprising: a plurality of sampling circuits that samples the analog signal by a plurality of sampling clocks of which sampling periods overlap with each other and which has a relationship in which end times of the sampling periods are different from each other, in a first half cycle in a sampling cycle that is same cycle as an operation control clock of the discrete-time circuit; and an averaging processing circuit that performs average processing on each sampled value in the sampling circuits in response to a start of a period corresponding to a last half cycle of the sampling period in the operation control clock, wherein the averaging processing circuit includes an operational amplifier that includes a plurality of divided inverting input terminals that is connected to capacitors included in the sampling circuits, respectively, in one-to-one correspondence.