Patent ID: 7732892

Claim:
An integrated circuit (IC) device, comprising: a first and second metal pads formed at different positions in a first dielectric layer, wherein the first and second metal pads are metal layers of a planar bottom surface; a conductive line formed in a second dielectric layer underlying the first dielectric layer, wherein a top surface of the conductive line is entirely exposed by the second dielectric layer and the top surface of the conductive line is physically connecting the planar bottom surface of the first and second metal pads, and the conductive line is formed with a first portion at an end thereof and a second portion connected with the first portion, and the width of the first portion is greater than the width of the second portion, and the planar bottom surface of the first metal pad partially covers the first portion of the conductive line and is in physical contact with the top surface of the conductive line, and the planar bottom surface of the second metal pad partially covers the second portion of the conductive line and is in physical contact with the top surface of the conductive line; a third dielectric layer formed over the first dielectric layer, comprising a conductive contact formed therein, wherein the conductive contact physically contacts the first metal pad partially covering the first portion of the conductive line; and a conductive pad formed over the third dielectric layer, physically contacting the conductive contact formed in the third dielectric layer, wherein the conductive pad functions as an uppermost pad for applying a fuse blow-up process.