Patent ID: 7487374

Claim:
A method of managing power in power-gated circuits of a computer system comprising the steps of: receiving a first time interval M(P) and a second time interval N(P) for power-gated circuitry P; receiving a wake-up signal W(P) and an estimated time K(P) a next wake-up signal is expected following receipt of the wake-up signal W(P) for the power-gated circuitry P; determining whether K(P) is greater than a sum of M(P)+N(P); initiating a wake-up of the power-gated circuitry P on receipt of wake-up signal W(P); and generating a sleep mode signal P (SM(P))for the power-gated circuitry P after the time M(P) if K(P) is greater that the sum of M(P)+N(P) and generating the sleep mode signal for the power-gated circuitry P after the time M(P)+N(P) if K(P) is less than the sum of M(P)+N(P) and a next successive wake-up signal following W(P) has not been received.