Patent ID: 7472310

Claim:
A debugging mechanism in a system in which a plurality of bus masters share a common bus slave, the debugging mechanism comprising: a bus control unit for supporting the plurality of bus masters, registering details of write access requested from each bus master upon receiving the write access, and performing a release control of notifying each bus master of completion of access before completion of access to the bus slave and an access order control of not ensuring an execution order of bus access among the plurality of bus masters; a debugging register for designating conditions of bus access subjected to debugging; a dirty detector for constantly monitoring an operation of the bus control unit, detecting a period of status disparity between the bus master and the bus slave, the period ranging from registration of write access coincident with the conditions designated by the debugging register in the write buffer to completion of access to the bus slave, and sending a notification about the detected period; and a debugging unit, provided at the bus master, for treating the notification about detection of the status disparity period received from the dirty detector as an AND condition in detection of a debugging event, wherein the bus master provided with the debugging unit breaks an operation thereof by using a debugging event generated in establishment of operational conditions optionally designated by the debugging unit, during the status disparity period.