Patent ID: 7068525

Claim:
Method of operating multiple (n) parallel-connected pulse-controlled inverters ( 1 , 2 ), wherein the individual current(s) of the (n) pulse-controlled inverters ( 1 , 2 ), or of a number reduced by 1(n−1) of pulse-controlled inverters ( 1 , 2 ) is/are regulated, and each pulse-controlled inverter ( 1 , 2 ) includes first (IGBTT 11 , IGBTT 21 ) and second (IGBTT 14 , IGBTT 24 ) insulated gate bipolar transistors and first (D 11 , D 21 ) and second (D 14 , D 24 ) diodes each connected in parallel with a respective one of the first (IGBTT 11 , IGBTT 21 ) and second (IGBTT 14 , IGBTT 24 ) insulated gate bipolar transistors in the direction of reverse voltage (UD−) to forward voltage (UD+), the input variable of regulation is generated by the difference between the setpoint value and the actual value of the corresponding output current, and by the modulation pattern, and for each pulse-controlled inverter ( 1 , 2 ), when the actual value of current (I 11 , I 21 ) is greater than the setpoint value, a turn-on edge of the first transistor (T 11 , T 21 ) and turn-off edge of the second transistor (T 14 , T 24 ) are each delayed, a turn-off edge of the first transistor (T 11 , T 21 ) and turn-on edge the second transistor (T 14 , T 24 ) remaining undelayed, when the actual value of the current (I 11 , I 21 ) is smaller than the setpoint value, the turn-on edge of the first transistor (T 11 , T 21 ) and turn-off edge of the second transistor (T 14 , T 24 ) are undelayed, with the turn-off edge of the first transistor (T 11 , T 21 ) and turn-on edge of the second transistor (T 14 , T 24 ) each being delayed, and when the actual value of the current (I 11 , I 21 ) equals the setpoint value, the turn-on edges and turn-off edges of the first (T 11 , T 21 ) and second (T 14 , T 24 ) transistors all remain undelayed.