Patent ID: 7900110

Claim:
An integrated circuit, comprising: A. tap domain test access port circuitry having a test data in (TDI) input lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data out (TDO) output lead; and B. serial to parallel control circuitry having a TMS/TDI input lead, a clock input lead, and a TDO output lead, the controller circuitry being connected to the test access port circuitry by a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead of the test access port circuitry and to the TDO output lead of the serial to parallel control circuitry, the serial to parallel control circuitry including: i. serial input parallel output circuitry having a serial input connected to the TMS/TDI input lead, a clock input connected with the clock input lead, a TDI output, and a TMS output; ii. update register circuitry having a first input connected to the TDI output of the serial input parallel output circuitry and a first output connected to the TDI output lead, having a second input connected to the TMS output of the serial input parallel output circuitry and a second output connected to the TMS output lead, and having an update clock input; and iii. clock controller circuitry having an input connected to the clock input lead, an update clock output connected to the update clock input, and a test clock output lead connected to the TCK output lead.