Patent ID: 7293160

Claim:
A method for eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution, comprising: issuing instructions for execution in program order during execution of a program in a normal-execution mode, wherein issuing the instructions involves decoding the instructions; upon encountering an unresolved data dependency during execution of an instruction, performing a checkpointing operation and executing subsequent instructions in an execute-ahead mode; during execute-ahead mode instructions are decoded and issued in program order, wherein decoded instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred decoded instructions are executed in program order; and when the unresolved data dependency is resolved during execute-ahead mode, executing deferred decoded instructions in a deferred mode by initially issuing deferred decoded instructions from a deferred queue, feeding decoded instructions from a deferred SRAM through a decode unit and into the deferred queue, whereby, upon entering deferred mode, the decoded instructions in the deferred queue are issued to an execution unit without needing to be decoded, thereby providing time for deferred decoded instructions from the deferred SRAM to progress through a decode unit in order to read input values for the decoded instruction, but not to be re-decoded.