Patent ID: 8787074

Claim:
A static random access memory (SRAM) test structure, comprising: a p-type source/drain implant region comprising contacts (CAs) located in the p-type source/drain implant region, wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs in the SRAM test structure, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of V dd CAs and rectangular contacts (CArecs), wherein a CArec simultaneously contacts a gate line and a source/drain, and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.