Patent ID: 8886872

Claim:
A memory controller for controlling operation of a data storage device, the memory controller comprising: a command dispatcher configured to dispatch memory operation commands for execution by a plurality of memory devices of the data storage device, the command dispatcher including: a command buffer configured to separately and respectively queue the memory operation commands by maintaining, for each of the plurality of memory devices, a respective linked list of corresponding memory operation commands; and a selection circuit operationally coupled with the command buffer, the selection circuit including: a plurality of leaf nodes, each leaf node corresponding with one of the linked lists and being configured to provide an indication whether its corresponding linked list includes one or more memory operation commands awaiting dispatch; and an OR-reduction tree configured to reduce the indications of the plurality of leaf nodes to a root node indication, the root node indication indicating whether the command buffer has any memory operation commands stored therein that are awaiting dispatch, wherein the selection circuit is configured to iterate over the nodes of the OR-reduction tree to select memory operation commands for dispatch by the command dispatcher.