Patent ID: 7843751

Claim:
A semiconductor device, comprising: a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of data lines; and a plurality of sense amplifier circuits connected to the plurality of data lines, wherein each of the plurality of sense amplifier circuits is provided with a first MISFET pair of a first conductivity type in which a gate of one MISFET of the first pair is directly connected to the drain of the other MISFET of the first pair, a second MISFET pair of the first conductivity type in which a gate of one MISFET of the second pair is directly connected to a drain of the other MISFET of the second pair, and a third MISFET pair of a second conductivity type in which a gate of one MISFET of the third pair is directly connected to a drain of the other MISFET of the third pair, and wherein, for each said sense amplifier circuit, a threshold voltage of the first MISFET pair is smaller than a threshold voltage of the second MISFET pair.