Patent ID: 7811921

Claim:
A method of forming a semiconductor device comprising: forming a conducting line layer, a conducting line capping layer, and photoresist patterns, sequentially stacked on a semiconductor substrate; performing a first etch process on the conducting line capping layer, using the photoresist patterns as an etch mask, thereby forming conducting line capping layer patterns on the conducting line layer; removing the photoresist patterns from the semiconductor substrate; performing a second etch process on the conducting line layer, using the conducting line capping layer patterns as an etch mask, thereby forming a groove in the conducting line layer between the conducting line capping layer patterns, wherein the groove extends partially under the conducting line capping layer patterns to form a trench between the conducting line capping layer patterns and the conducting line layer; performing a third etch process on the conducting line layer, using the conducting line capping layer patterns as an etch mask, thereby forming conducting lines under the conducting line capping layer patterns respectively, each of the conducting lines and the conducting line capping layer patterns being sequentially stacked to form conducting line patterns, respectively; forming conducting line spacers on sidewalls of the conducting line patterns, respectively; forming a planarized interlayer insulating layer on the conducting line capping layer pattern to completely fill between the conducting line patterns; and forming a pad hole that penetrates a predetermined portion of the planarized interlayer insulating layer between the conducting line patterns, wherein the pad hole exposes the conducting line capping layer patterns and the conducting line spacers, and the conducting line spacers fill the trenches, respectively.