Patent ID: 7360178

Claim:
A method for producing a chip, comprising the steps of: (A) fabricating said chip only up to and including a first metal layer such that a core region of said chip has an array of cells, each of said cells having a plurality of transistors; (B) designing a plurality of upper metal layers above said first metal layer in response to a custom design created after said first fabricating has started, said upper metal layers interconnecting a first plurality of said cells to form (i) a mixed-signal module and (ii) a digital module, said mixed signal module generating at least one analog signal and at least one digital signal; and (C) fabricating said chip to add said upper metal layers, wherein (1) said designing comprises the sub-steps of (i) designing a first module at a first location using a second plurality of said cells, (ii) moving said first module away from said first location, (iii) designing a second module at said first location using at least one of said second plurality of said cells and (iv) moving said second module to a second location such that said second module uses a portion of said first plurality of said cells and a third plurality of said cells and (2) each of said cells comprises (i) five of said transistors, (ii) two well contacts and (iii) eleven pads in said first metal layer connected to each node of said transistors and each of said well contacts respectively.