Patent ID: 7373572

Claim:
An apparatus, comprising: a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a scan circuit including a shadow pulse latch, coupled to the system pulse latch, to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least one scan clock signal during a test mode operation; an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal; and the output joining circuit being adapted to disable the at least one shadow latch signal as an input to the output joining circuit during the test mode of operation.