Patent ID: 7458047

Claim:
A method of designing a layout of a functional block and an on-chip capacitor in a semiconductor integrated circuit, comprising: (a) designing a layout of a capacitor/block comprised of a functional block, and an on-chip capacitor having a predetermined capacity and disposed adjacent to the functional block; (b) judging whether the layout resulted from the step (a) satisfies predetermined requirements; (c) designing again a layout of a capacitor/block including an on-chip capacitor having a capacity smaller than a capacity of an on-chip capacitor of the previously designed capacitor/block, only when the layout resulted from the step (a) is judged not to satisfy the predetermined requirements; and (d) judging whether the layout resulted from the step (c) satisfies the predetermined requirements, the steps (c) and (d) being repeatedly carried out until the layout satisfies the predetermined requirements.