Patent ID: 8880807

Claim:
A data prefetcher, the data prefetcher comprising: a bitmask having a corresponding bit for every cache line within a memory block; a plurality of period match counters associated with a corresponding plurality of different pattern periods; a middle pointer that points in the bitmask to a middle cache line of the cache lines within the memory block that have been accessed, wherein each pattern period of the plurality of different pattern periods is a number of bits to the left/right of the middle pointer; and control logic that: updates the bitmask in response to the accesses to the memory block to indicate the cache lines within the memory block that have been accessed; computes the middle pointer in response to the accesses; updates the plurality of period match counters in response to accesses to the memory block by the microprocessor; determines a clearly winning pattern period of the plurality of different pattern periods based on the plurality of period match counters; and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clearly winning pattern period determined based on the plurality of period match counters wherein the bitmask, plurality of period mask counters, middle pointer and control logic are included in a microprocessor.