Patent ID: 8739083

Claim:
A layout decomposition method, executed by a logic processer of a computing system, comprising: receiving a design layout by the logic processer; identifying a design rule for layout decomposition by the logic processer, comprising: identifying a plurality of loose areas and dense areas on a substrate; and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate; and generating masks for forming the odd-numbered features in the first areas of the dense areas according to results of design rule identification by the computing system, wherein the masks comprising one set selected from the groups including: a first mask having a first pattern for fabricating, in the dense areas, patterns of spacers with pitches required in the dense areas, and a second mask having a second pattern for fabricating patterns in the loose areas and optional for cutting and/or shielding parts of the spacers in the dense areas; and a first mask having a first pattern for fabricating, on the entire substrate, patterns of spacers with pitches required in the dense areas, and a second mask having a second pattern for cutting the spacers in the loose areas and for cutting and/or shielding parts of the spacers in the dense areas.