Patent ID: 8792285

Claim:
An apparatus comprising: a page buffer circuit coupled to a bit line of a memory array, the page buffer circuit including a latch; and control circuitry coupled to the page buffer circuit, the control circuitry controlling a present multi-phase program operation for a memory cell accessed by the bit line coupled to the page buffer circuit, the present multi-phase program operation including: a program phase for which the latch stores program data; a program verify phase after the program phase, for which the latch stores program verify data; and a preparation phase after the program phase of the present multi-phase program operation and after the program verify phase of the present multi-phase program operation, for which the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation, wherein results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data, and in the present multi-phase program operation, the program verify data stored in the latch for the program verify phase and the preparation data stored in the latch for the preparation phase are not required to have a same value.