Patent ID: 8914571

Claim:
A scheduler operating to control execution within a memory of at least one operation request received in an input request set (IRS), wherein each operation request in the IRS includes a corresponding logical address, the memory including a plurality of zones and each zone including a plurality of blocks having neighboring logical addresses, each of the blocks is a logical space and a base unit to which a particular operation request is made, the scheduler comprising: a plurality of zone standby units having a one-to-one relationship with the plurality of zones, wherein each of the plurality of zone standby units is respectively configured to store an operation request received in the IRS and having a logical address indicating a corresponding zone; and to perform an operation indicated by the operation request with the zone as a unit, an output processing unit configured to determine a processing sequence of the plurality of zone standby units, receive at least one operation request stored in the plurality of zone standby units on the basis of the processing sequence, and provide an output request set (ORS) comprising the at least one operation request arranged on the basis of the processing sequence.