Patent ID: 6904447

Claim:
A 4-2 compressor for generating a sum bit and a carry bit as a result of four input data comprising: a first logic circuit for performing a NAND operation and a NOR operation of a first input data and a second input data, for generating a first XOR/XNOR operation result of the first input data and the second input data using the NAND operation result and the NOR operation result, and for generating a carry-out bit for a following stage by selecting either the NAND operation result or the NOR operation result in response to a third input data; a second logic circuit for generating a second XOR/XNOR operation result of the third input data and a fourth input data, and for generating a selection signal by selecting one of an XOR operation result and an XNOR operation result of the first XOR/XNOR operation result from the first logic circuit, in response to the second XOR/XNOR operation result; a third logic circuit for generating the sum bit by selecting one of a carry-input bit and an inverted carry-input bit in response to the selection signal from the second logic circuit; and a fourth logic circuit for generating the carry bit by selecting one of the inverted carry-input bit and an inverted fourth input data in response to the selection signal from the second logic circuit.