Patent ID: 7330808

Claim:
A method of reducing a size of a netlist for a hardware target architecture for simulation, comprising: create a netlist of objects specifying each object for the target hardware architecture, wherein the target hardware architecture is a field programmable gate array; identify objects specific to the target hardware architecture that are repeated to identify potential dummy objects; create a list of objects, from the netlist of objects, that are used by a circuit design to be implemented in the target hardware architecture; form a list of unused objects in the target hardware architecture from the netlist of objects and the list of objects used by the circuit design; replace at least one object in the netlist of objects for the target hardware architecture that is also specified in the list of unused objects and which is identified as a potential dummy object with an appropriate dummy object to form a modified netlist by removing functional hardware description language from the object; and simulate the modified netlist by simulating each object of the modified netlist inclusive of each dummy object, wherein for each dummy object, a signal provided to the dummy object is fed through the dummy object unchanged.