Patent ID: 7292086

Claim:
A delay circuit for delaying an input signal with an edge at a predetermined timing and outputting a delayed signal, comprising: N-stage circuits (where N is an integer greater than, or equal to, 2) having a first circuit to an N-th circuit connected in cascade, said input signal being input to said first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying said transmission signal of each stage of said N-stage circuits commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit of said N-stage circuits so that during a predetermined period from an edge timing of a signal input to said i-th circuit to an edge timing of said transmission signal delayed by said common delay circuit through said i-th circuit, said common delay circuit is connected to a signal path, and during the other period, said common delay circuit is disconnected from said signal path, wherein said delayed signal passing through said common delay circuit N times in the path of said N-stage circuits is generated.