Patent ID: 7136967

Claim:
A digital data processing device, comprising: at least one processor; a memory; a first cache for temporarily holding portions of said memory, said first cache containing a plurality of addressable associativity sets, each associativity set containing one or more respective cache lines and corresponding to a respective first cache subset of a plurality of discrete first cache subsets of addresses for accessing said first cache; and a second cache for temporarily holding portions of said memory, said second cache containing a plurality of addressable associativity sets, each associativity set containing one or more respective cache lines and corresponding to a respective second cache subset of a plurality of discrete second cache subsets of addresses for accessing said second cache; wherein each said associativity set of said first cache and each said associativity set of said second cache is contained in a respective congruence group of a plurality of congruence groups, each congruence group containing a respective plurality of associativity sets of said first cache and a respective plurality of associativity sets of said second cache; wherein addresses of the first cache subset corresponding to each respective associativity set of said first cache are allocated among each of the plurality of second cache subsets corresponding to respective associativity sets in said second cache within the same congruence group as the respective associativity set of said first cache.