Patent ID: 7477961

Claim:
A method of modeling yield for semiconductor products, the method comprising: determining expected faults for each of a plurality of library elements by running a critical area analysis on each of said library elements; assessing, from said critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products, and thereafter updating said expected number of faults for each library element in response to observed yield; establishing a database, said database including the die size and expected faults for each of said library elements; estimating integrated circuit product die size; selecting library elements to be used to create an integrated circuit die; obtaining fault and size data for each of the selected library elements; summing the adjusted estimated faults for each of said library elements; and calculating estimated yield; wherein the expected total number of faults for an integrated circuit die having N different library element types is determined by the expression: λ ⁡ ( t ) = ∑ i = 1 N ⁢ ⁢ n i ⁢ r i ⁢ λ i ⁢ τ i ⁢ F ⁡ ( t ) ; wherein t=time for which yield estimate is needed; λ(t)=total number of faults per chip at time t; n i =total number of library elements of type i present on the integrated circuit die; r i =redundancy factor for library element i; λ i =estimated number of faults for the i th library element; t i τadjustment factor for the i th library element, determined by comparing the yield data for that library element with the estimate value λ i ; and F(t)=learning factor at time t.