Patent ID: 8648401

Claim:
A semiconductor memory device, comprising: a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer proximate the first ferromagnetic layer, wherein the second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side; a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer; an electrode extending under and interfacing with each of the first, second, and third portions of the second ferromagnetic layer; and a transistor connected to the second ferromagnetic layer by a conductive feature interfacing with the electrode.