Patent ID: 8917552

Claim:
A nonvolatile semiconductor storage device comprising: multiple memory strings including multiple memory transistors connected in series; multiple first transistors that have first ends that are respectively connected to first ends of the multiple memory strings and are configured to be capable of having an adjustable threshold voltage; multiple bit lines each corresponding to one of the multiple memory strings, that are each connected to second ends of the multiple first transistors; a first line that connects gates of the multiple first transistors; and a control circuit configured to execute the write operation on the first transistors by applying a set voltage to the multiple bit lines and the first line, wherein the control circuit, during the write operation, configures the multiple bit lines so that the two bit lines that are adjacent to select bit lines are nonselect bit lines, applies a first voltage to a write bit line that is included in the select bit lines, then, after applying a second voltage that is higher than the first voltage to a write inhibit bit line that is included in the select bit lines, applies a third voltage that is higher than the second voltage to the nonselect bit lines, and while raising the voltage on the write inhibit bit line, maintains the write bit line at the first voltage, and then applies a fourth voltage for the write operation to the first line.