Patent ID: 8293598

Claim:
A process, comprising: manufacturing a memory device having a vertical bipolar transistor and a CMOS transistor in a semiconductor body having a surface, the manufacturing including: forming field insulation regions of dielectric material in said semiconductor body, the field insulating regions delimiting an array portion and a first circuitry portion, insulated from each other; forming the bipolar transistor in said array portion, including forming a buried first conduction region buried at a distance from said surface, forming a control region on said first conduction region, forming a second conduction region within said control region, and forming a control contact region within said control region and spaced apart from said second conduction region; and forming a first MOS transistor in said circuitry portion, including forming a first gate structure on said surface, forming first lightly doped regions in said body, laterally to said first gate structure, forming first lateral spacers on sides of said first gate structure, forming third conduction regions in said body, laterally to said first lateral spacers; wherein: forming the first lateral spacers comprises, after forming the first gate structure and before forming the second conduction region and the control contact region, the steps of: forming lower spacer portions on the sides of said first gate structure and forming a dielectric portion on said array portion; and forming upper spacer portions on top of and on the sides of said lower spacer portions, said lower spacer portions and upper spacer portions defining a multilayer structure; forming the bipolar transistor includes forming a protection mask by etching said dielectric portion on said array portion after forming the upper and lower spacer portions; forming the second conduction region includes selectively implanting first conductivity-type dopants through a first opening in the protection mask after forming the upper and lower spacer portions; and forming the control contact region includes selectively implanting second conductivity-type doping agents through a second opening in the protection mask after forming the upper and lower spacer portions.