Patent ID: 7701189

Claim:
A DC-DC buck converter comprising: an input terminal; an output terminal for supplying an output current to a load; a reference voltage terminal; an inductor coupled to the output terminal; a high-side power FET having a current path coupled in series between the input terminal and the inductor; a low-side power FET having a current path coupled between the reference voltage terminal and node between the high-side power FET and the inductor; a pulse width modulation controller coupled to receive a feedback signal from the output terminal, for providing pulse width modulated signals; and a gate driver circuit coupled to receive the pulse width modulated signals from the pulse width modulation (PWM) controller and, responsive thereto, to apply pulse width modulated drive signals to gates of the high-side and low-side power FETs, wherein the gate driver circuit supplies the drive signals to the gates of the power FETs at a variable voltage level adjusted in response to at least the output current, in order to substantially minimize the power dissipation of the gate driver circuit; a gate drive voltage controller that is coupled to receive signals that are representative of an input voltage at the input terminal, an output voltage at the output terminal, an input current at the input terminal, and the output current, wherein the gate drive voltage controller generates an adjustment signal at least in part in response to the signals that are representative of the input voltage, the output voltage, the input current, and the output current; and a voltage regulator that is coupled to the gate drive voltage controller so as to receive the adjustment signal and that is coupled to the gate driver circuit so as to provide an adjusted gate drive voltage to the gate driver circuit based at least in part on the adjustment signal.