Patent ID: 8497948

Claim:
A pixel structure, comprising: a first patterned metal layer disposed on a substrate and comprising a gate electrode, a gate extension electrode, and a data line including a first data line segment and a second data line segment; a gate insulating layer formed on the substrate and the first patterned metal layer; a semiconductor channel layer disposed on the gate insulating layer above the gate electrode; a second patterned metal layer disposed on the gate insulating layer and the semiconductor channel layer and comprising a source electrode, a drain electrode, a gate line and a common electrode, wherein the source electrode and the drain electrode are correspondingly disposed on the semiconductor channel layer above two sides of the gate electrode, and the common electrode is disposed above the first data line segment; a passivation layer formed on the gate insulating layer and the second patterned metal layer, wherein the passivation layer uncovers a portion of the gate line, a portion of the source electrode and a portion of the drain electrode of the second patterned metal layer, and the passivation layer and the gate insulating layer uncovers a portion of the gate extension electrode and a portion of the second data line segment of the first patterned metal layer; and a conducting layer covering the passivation layer, the gate line of the second patterned metal layer being electrically connected by the conducting layer to the gate extension electrode of the first patterned metal layer, the source electrode of the second patterned metal layer being electrically connected by the conducting layer to the second data line segment of the first patterned metal layer.