Patent ID: 7122877

Claim:
A semiconductor device comprising: a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and is in contact with the isolating region; an upper electrode provided on the capacitance insulating film so as to be spaced away from the isolating region; an electrode pad provided on the isolating region; a lead conductive film provided over a part of the capacitance insulating film and a part of the isolating region for connecting the upper electrode and the electrode pad; and an interlayer insulating film provided over the substrate, wherein contact holes penetrating the interlayer insulating film to reach the electrode pad are formed, and a ratio (S/L) of a total sum (S) of exposed areas of the electrode pad in the contact holes with respect to a total sum (L) of lengths of a boundary line in an overlapping portion of the boundary line and the lead conductive films is adjusted such that the breakdown of the capacitance insulating film is substantially suppressed, the boundary line being between the capacitance insulating film and the isolating region.