Patent ID: 8130894

Claim:
A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising: an interleaver memory configured to read-in a predetermined number of data symbols for mapping onto the OFDM carrier signals, and to read-out the data symbols for the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the carrier signals; and an address generator configured to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the carrier signals onto which the data symbol is to be mapped, the address generator including a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial; a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM carriers; and a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds the predetermined number of carriers, wherein the predetermined number of OFDM carrier signals is a maximum of four thousand and ninety six, the linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R′ i [10]=R′ i-1 [0]⊕R′ i-1 [2], and the permutation order forms, with an additional bit, a twelve bit address, which includes an eleven bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] in accordance with the table: R′ i [n] for n = 10 9 8 7 6 5 4 3 2 1 0 R i [n] for n = 7 10 5 8 1 2 4 9 0 3 6 and the additional bit is the most significant bit of the address, the value of the additional bit being toggled between 0 and 1 between successive OFDM symbols.