Patent ID: 7605420

Claim:
A semiconductor device, comprising: a memory cell formed in a memory cell region over a semiconductor substrate and including a laminated structure of a lower electrode, a TMR film and an upper electrode, and said TMR film and said upper electrode are formed over a portion of said lower electrode; an antioxidant film covering an upper surface of the lower electrode and a side surface of the TMR film at least; a first silicon oxide film formed over the antioxidant film; a read wire formed under the lower electrode and separated by a predetermined distance from the TMR film, in a plan view; an interlayer insulating film formed above said read wire and under said lower electrode and having a first opening exposing an upper surface of said read wire; a first metal plug formed in said first opening over said read wire and electrically connecting said read wire and said lower electrode; and wherein said interlayer insulating film includes a first interlayer insulation film and a second interlayer insulation film formed over said first interlayer insulation film, said first interlayer insulation film includes a material different from said second interlayer insulation film, and said antioxidant film and said first interlayer insulation film include the same material.