Patent ID: 8745453

Claim:
A system comprising: a memory controller configured to identify a first memory cell of a first plurality of memory cells as being defective; in response to identifying the first memory cell of the first plurality of memory cells as being defective, store information about the first memory cell of the first plurality of memory cells, which has been identified as being defective, in a second memory cell of a second plurality of memory cells, wherein the second plurality of memory cells is separate from the first plurality of memory cells, and wherein the second plurality of memory cells is configured to store the information at a lower density than data stored in the first plurality of memory cells; and in response to (i) reading the data from the first plurality of memory cells and (ii) the first memory cell of the first plurality of memory cells having been identified as being defective, read the information about the first memory cell stored in the second memory cell, and determine, based on reading the information about the first memory cell stored in the second memory cell, a location of the first memory cell, which has been identified as being defective, in the first plurality of memory cells.