Patent ID: 8332614

Claim:
A method for filtering quiesce interruption requests at a processor, the method comprising: storing translation lookaside buffer (TLB) entries in a TLB 1 at the processor, the TLB 1 comprising entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode; receiving a quiesce interruption request at the processor, the quiesce interruption request comprising a requesting zone indicator indicating a zone of the processor requesting the quiesce interruption, the processor executing in the host mode having no zone or the guest mode having the current zone; determining that the quiesce interruption request should be filtered by the processor, the determining responsive to the requesting zone indicator and to contents of a programmable filtering register for indicating exceptions to filtering performed by the processor; and responsive to the requesting zone indicator being the same as the current zone associated with the TLB entries, filtering the quiesce interruption request, wherein one or more quiesce interruption requests are filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.