Patent ID: 7411426

Claim:
A phase detector comprising; a first pulse generator responsive to a data signal; a first flip-flop having a clock terminal responsive to an output of the first pulse generator; said first flip-flop having a data terminal coupled to a first voltage; a second pulse generator responsive to a clock signal; and a second flip-flop having a clock terminal responsive to an output of the second pulse generator; said second flip-flop having a data terminal coupled to the first voltage; a third pulse generator responsive to said data signal, wherein a reset terminal of the first flip-flop is responsive to an output of the second pulse generator, wherein the reset terminal of each of the first and second flip-flops is further responsive to an output of the second pulse generator, wherein the reset terminal of each of the first and second flip-flops is further responsive to a reset signal, wherein each of said first, second and third pulse generators comprises a first logic block performing an inverse operation, a second logic block performing a delay operation, and a third logic block performing a NOR operation.