Patent ID: 8269284

Claim:
A method of manufacturing a semiconductor device having a static random access memory, comprising the steps of: forming an isolation insulating film in a main surface of a semiconductor substrate to define each of a first element formation region where a transistor of a first conductivity type is to be formed and a second element formation region where a transistor of a second conductivity type is to be formed; forming, in the first element formation region, gate structures including a first gate structure disposed over a region located between a first area and a second area spaced apart from each other, and a second gate structure disposed over a region located between the second area and a third area spaced apart from the second area; forming a first implantation mask having a first opening exposing a first side surface of the first gate structure facing toward the second area and exposing a region extending from the first side surface to a portion of the second area spaced apart at a predetermined distance from the first side surface, and covering a second side surface of the first gate structure facing toward the first area, the first area, and the second element formation region; implanting, via the first implantation mask, a first impurity through the first opening at an angle tilted from a direction perpendicular to the main surface of the semiconductor substrate; removing the first implantation mask; forming a second implantation mask having a second opening exposing the first gate structure, the second gate structure, the first area, the second area, and the third area, and covering the second element formation region; implanting, via the second implantation mask, a second impurity of the second conductivity type through the second opening at an angle tilted from a direction perpendicular to the main surface of the semiconductor substrate; removing the second implantation mask; and forming a bit line electrically coupled to the first area, and forming a wiring which electrically couples an area of the second element formation region serving as a source or drain electrode of the transistor of the second conductivity type to the second area and which serves as a storage node.