Patent ID: 8239797

Claim:
In a circuit design process, a method comprising acts of: performing a block placement of integrated circuit design blocks; performing a global routing among the integrated circuit design blocks; using a computer to perform a block placement movement process that includes: determining routing congestion within fragmented spaces between the multiple blocks: determining whether routing congestion within the fragmented spaces meets a target; in response to determining that routing congestion meets the target, performing detailed routing; in response to determining that congestion does not meet the target, determining a congestion weight within a first fragmented space adjacent to a first edge of at least one block relative to a congestion weight within a second fragmented space adjacent to a second opposed edge of the at least one block; and moving a placement of the at least one block in a first direction toward one of the first and second fragmented space determined to have a lower relative congestion weight and in a direction away from an other of the first and second fragmented space determined to have the higher relative congestion weight so as to produce a revised placement; performing another global routing among the integrated circuit design blocks having the revised placement; determining whether routing congestion within the fragmented spaces between the multiple blocks having the revised placement meets the target; in response to determining that routing congestion between the multiple blocks having the revised placement meets the target, performing detailed routing; in response to determining that routing congestion between the multiple blocks having the revised placement does not meet the target, repeating the revised block placement movement process.