Patent ID: 7282957

Claim:
A semiconductor integrated circuit, comprising: a NOR type first dynamic circuit of receiving a first clock and a plurality of pieces of data, wherein a first output node is charged during a first period which is one of a period from rising to falling of the first clock and a period of falling to rising of the first clock, and during a second period which is the other period, electric charge of the first output node is held when all of the plurality of pieces of data have the same value, while the electric charge of the first output node is discharged when at least one of the plurality of pieces of data has a different value from the other pieces of data; a NAND type second dynamic circuit of receiving a second clock and a signal of the first output node of the NOR type first dynamic circuit, wherein, during a first period or a second period of the second clock, electric charge of the second output node is held when the electric charge of the first output node of the NOR type first dynamic circuit is discharged, while the electric charge of the second output node is discharged when the electric charge of the first output node is held; a NOR type third dynamic circuit of receiving a third clock and a plurality of selection signals for selecting the respective pieces of data, wherein a third output node is charged during a first period of the third clock, and during a second period of the third clock, electric charge of the third output node is held when all of the plurality of selection signals selects none of the plurality of pieces of data; and a NAND type fourth dynamic circuit of receiving a fourth clock and a signal of the third output node of the NOR type third dynamic circuit, wherein, during a first period or a second period of the fourth clock, electric charge of the fourth output node is discharged when the electric charge of the third output node of the NOR type third dynamic circuit is held, wherein, when the NAND type second dynamic circuit receives a signal of the fourth output node of the NAND type fourth dynamic circuit and the electric charge of the fourth output node is discharged, the NAND type second dynamic circuit holds the electric charge of the second output node even when the electric charge of the first output node of the NOR type first dynamic circuit is held.