Patent ID: 7542857

Claim:
A method for determining worst case bit sequences, the method comprising the steps of: acquiring a first representation of a first response on a first signal line resulting from a first signal transmitted on the first signal line; acquiring a second representation of a second response on the first signal line resulting from at least one second signal transmitted on at least one second signal line, the at least one second signal line being substantially adjacent to the first signal line; and generating worst case bit sequences based upon the first representation of the first response and the second representation of the second response for transmission on the first signal line and the at least one second signal line for use in determining performance characteristics associated with at least the first signal line; wherein generating worst case bit sequences comprises generating worst case timing margin bit sequences and worst case voltage margin bit sequences for transmission on the first signal line and the at least one second signal line, wherein generating worst case timing margin bit sequences for transmission on the first signal line comprises determining a polarity of the first response at data-cell boundaries of the first response, wherein if the polarity at a data-cell boundary is positive, then an associated bit in a first worst case timing margin bit sequence for transmission on the first signal line is assigned a logic one value, and wherein if the polarity at a data-cell boundary is negative, then an associated bit in the first worst case timing margin bit sequence for transmission on the first signal line is assigned a logic zero value.