Patent ID: 7436919

Claim:
A method for bit synchronizing a plurality of serial bitstreams with a common clock signal having a common clock frequency, the method comprising the steps of: oversampling each of the plurality of serial bitstreams at a sampling frequency substantially equal to an integer multiple of the common clock frequency to create a plurality of phases associated with each of the serial bitstreams; detecting activity occurring within each of the plurality of phases for each of the serial bitstreams, wherein each of the plurality of phases corresponds to a cycle of the common clock signal; selecting one of the plurality of phases for each of the serial bitstreams based upon the activity detected within the selected phase; and extracting data from the selected phase for each of the serial bitstreams to thereby bit synchronize each of the plurality of serial bitstreams; wherein the selecting step comprises the step of adjusting a phase select counter by a counter adjustment logic to thereby select a tap associated with the selected phase.