Patent ID: 7187605

Claim:
A semiconductor storage device comprising: a memory cell array having a plurality of memory cell transistors arranged in a matrix form and having storage values written therein by connecting/disconnecting first main electrodes of the memory cell transistors to/from a first power line; a plurality of word lines respectively connected to control electrodes of the memory cell transistors along corresponding rows of the memory cell array; a plurality of bit lines respectively connected to other main electrodes of the memory cell transistors along corresponding columns of the memory cell array; a data line for selectively outputting a potential on the bit lines; a select transistor of a first conductivity type having a first main electrode connected to a corresponding one of the bit lines, an other main electrode connected to the data line, and a control electrode having a corresponding select signal input thereto; and a precharge transistor of a second conductivity type having a first main electrode connected to the corresponding one of the bit lines, an other main electrode connected to a second power line, and a control electrode having the corresponding select signal input thereto, wherein the select transistor and the precharge transistor are both controlled by the corresponding select signal.