Patent ID: 7825525

Claim:
An integrated circuit, comprising: first and second structures, each structure including: a set of sub-lithographic lines, for which a sum of a width of the sub-lithographic line and a width of adjacent sub-lithographic space is less than or equal to about a quarter of a minimum pitch achievable by lithography; and contact landing segments connected to at least one of the sub-lithographic lines at an end portion; the first and second structures being nested such that the sub-lithographic lines are disposed in a parallel manner within a width dimension and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure and the contact landing segments for the first and second structures being included within the width dimension, wherein the width dimension includes a dimension of four times a minimum feature size (F) achievable by lithography.