Patent ID: 7719529

Claim:
A circuit that generates a sequence of digital values for a corresponding sequence of analog voltages in each analog signal of an analog input, the analog voltages in each analog signal occurring at an identical fixed rate with a corresponding fixed time-period for each analog voltage level associated with an input pixel, the analog input comprising a minimum of one analog signal, the circuit comprising: a phase-locked-loop that generates a clock signal synchronized to the analog input with a frequency that is an integer multiple of a rate of input pixels in each analog signal so that an integer number of clock cycles occur over the time-period of each input pixel, said integer number of clock cycles comprising a sequence of clock phases that is repeated for the time-period of each input pixel; a sampling analog-to-digital converter, for each analog signal, that generates a digital sample for the analog signal at each cycle of the clock signal; a rendering circuit, for each analog signal, that determines each digital value in the sequence of digital values from at least one sample in a group of samples from the analog-to-digital converter that occur within a time-window that brackets a selected nominal phase of the clock signal; and a local phase adjustment means, for each analog signal, for selecting the at least one sample, wherein the local phase adjustment means locates possible transitions in the voltage level by determining difference values between samples from the analog-to-digital converter that are in close proximity and comparing the relative magnitudes of the difference values to one another and wherein the selection of the at least one sample excludes samples near transitions in the voltage level of the analog signal.