Patent ID: 8354311

Claim:
A method for forming a transistor, comprising: forming a fin from a crystalline substrate, wherein forming the fin includes: depositing a material on the crystalline substrate; using a mask pattern with a minimum feature length to etch the material to define at least two holes in the material, wherein the material provides sidewalls that surround and define each of the at least two holes, and wherein each of the at least two holes is one minimum feature length (F) wide; forming sidewall spacers on each of the sidewalls that surround and define the at least two holes; forming a fin pattern from the sidewall spacers, wherein the fin pattern provides an array of sidewall spacers, wherein a first row and an adjacent second row has a center-to-center spacing of the minimum feature length (F) less a thickness of the fin (ΔT), and the second row and an adjacent third row has a center-to center spacing of the minimum feature length (F) plus the thickness of the fin (ΔT); and using the fin pattern as a mask to etch the fin from the crystalline substrate, wherein the fin has a cross-sectional thickness in a first direction corresponding to the minimum feature length and a cross-sectional thickness in a second direction orthogonal to the first direction less than the minimum feature length, wherein the first direction is substantially parallel to a surface of the substrate and the second direction is substantially parallel to the surface of the substrate; forming a first source/drain region in the substrate beneath the fin; forming a surrounding gate insulator around the fin; forming a surrounding gate around the fin and separated from the fin by the surrounding gate insulator; and forming a second source/drain region in a top portion of the fin.