Patent ID: 8274822

Claim:
A nonvolatile memory device, comprising: a memory unit including: a first interconnect; a second interconnect extending in a direction non-parallel to an extension direction of the first interconnect; a memory cell including a resistance change layer provided at an intersection between the first interconnect and the second interconnect, a resistance of the resistance change layer to change due to at least one selected from a voltage applied via the first interconnect and the second interconnect and a current flowing via the first interconnect and the second interconnect; and a control unit connected to the first interconnect and the second interconnect to supply the at least one selected from the voltage and the current to the resistance change layer, the control unit being configured to increase an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.