Patent ID: 6873006

Claim:
An electrically programmable and erasable memory device comprising: a substrate of semiconductor material having a first conductivity type and a surface; a trench formed into the surface of the substrate, wherein the trench includes a sidewall that meets the substrate surface at an acute angle to form a sharp edge; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region formed in the substrate therebetween, wherein the first region is formed underneath the trench, and the channel region includes a first portion that extends substantially along the trench sidewall and a second portion that extends substantially along the substrate surface; an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion; and an electrically conductive control gate disposed over and insulated from the channel region second portion; wherein the channel region first and second portions are non-linear with respect to each other, with the channel region second portion extending from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.