Patent ID: 8378739

Claim:
A semiconductor chip having a first operation mode in which first current is consumed and a second operation mode in which second current larger than the first current is consumed, comprising: a reference voltage generating circuit for generating a first reference voltage; a first regulator having first current drive capability and generating a power supply voltage on the basis of the first reference voltage; a voltage buffer for generating a second reference voltage of a level according to the first reference voltage; a second regulator having second current drive capability higher than the first current drive capability and generating the power supply voltage on the basis of the second reference voltage; and an internal circuit which is driven by the power supply voltage generated by the first and second regulators and executes the first and second operation modes, wherein the first regulator and the voltage buffer are provided near the reference voltage generating circuit, wherein the second regulator is provided near the internal circuit, and wherein the voltage buffer and the second regulator are made inactive in the first operation mode.