Patent ID: 7643344

Claim:
A variable resistive memory device, comprising: a plurality of memory sectors; a plurality of memory cells in each of the plurality of memory sectors; a plurality of sub-wordlines, a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of the memory cells in a second sector; a plurality of local bitlines, each in signal communication with at least one of the plurality of memory cells; a local bitline selecting signal generator in signal communication with a plurality of local bitline selecting signal paths; a first local bitline selecting signal path in signal communication with at least a first pair of the plurality of local bitlines; and a second local bitline selecting signal path in signal communication with at least a second pair of the plurality of local bitlines; wherein a first of the first pair of local bitlines is in signal communication with a first of the first pair of the memory cells in the first sector and a second of the first pair of local bitlines is in signal communication with a second of the second pair of the memory cells in the second sector, and a first of the second pair of local bitlines is in signal communication with a second of the first pair of the memory cells in the first sector and a second of the second pair of local bitlines is in signal communication with a first of the second pair of the memory cells in the second sector.