Patent ID: 8161243

Claim:
An apparatus comprising: a cache to store one or more entries, wherein each entry corresponds to an input/output (I/O) memory access request and each entry is to comprise a guest physical address (GPA), corresponding to the I/O memory access request, and a corresponding host physical address (HPA); and a first logic to receive a first I/O memory access request from an endpoint device and to determine whether the first I/O memory access request comprises a future access hint associated with an address, wherein the future access hint is to indicate to a host whether the address may be accessed in the future and wherein entries in the cache that do not comprise a hint, corresponding to previous I/O memory access requests comprising future access hints, are to be replaced prior to entries that comprise the hint, wherein the first logic is to cause an update to one or more bits, corresponding to the address, of both a cache entry of the cache and an entry in an I/O translation look-aside buffer (IOTLB) in response to a determination that the first I/O memory access request comprises the future access hint.