Patent ID: 7944374

Claim:
A pseudo orthogonal code generator comprising: a serial-to-parallel converter which converts a serial transmission data into a 9-bit parallel data; a 4-bit counter which repeatedly counts from 0 to 15; and a combined circuit unit which sequentially generates 16-bit pseudo orthogonal codes using the 9-bit parallel data and the 4-bit counter values, wherein the combined circuit unit is comprised of cb ⁢ ⁢ 0 ⁢ ( I ) = b 0 ⊕ ( i 1 ⁢ Λ ⁢ ⁢ b 1 ) ⊕ ( i 0 ⁢ Λ ⁢ ⁢ b 2 ) cb ⁢ ⁢ 1 ⁢ ( I ) = b 3 ⊕ i 2 ⊕ ( i 1 ⁢ Λ ⁢ ⁢ b 4 ) ⊕ ( i 0 ⁢ Λ ⁢ ⁢ b 5 ) cb ⁢ ⁢ 2 ⁢ ( I ) = b 6 ⊕ i 3 ⊕ ( i 1 ⁢ Λ ⁢ ⁢ b 7 ) ⊕ ( i 0 ⁢ Λ ⁢ ⁢ b 8 ) cb ⁢ ⁢ 3 ⁢ ( I ) = b 0 ⊕ b 3 ⊕ b _ 6 ⊕ i 3 ⊕ i 2 ⊕ ( i 1 ⁢ Λ ⁡ ( b 1 ⊕ b 4 ⊕ b 7 ) ) ⊕ ( i 0 ⁢ Λ ⁡ ( b 2 ⊕ b 5 ⊕ b 8 ) ) C ⁡ ( I ) = ( - 1 ) ( cb ⁢ ⁢ 0 ⁢ ( I ) ⊕ cb ⁢ ⁢ 1 ⁢ ( I ) ⊕ cb ⁢ ⁢ 2 ⁢ ( I ) ⊕ cb ⁢ ⁢ 3 ⁢ ( I ) ) _ ⁢  ( cb ⁢ ⁢ 0 ⁢ ( I ) ⁢ Λ ⁢ ⁢ cb ⁢ ⁢ 1 ⁢ ( I ) )  ⁢ ( cb ⁢ ⁢ 2 ⁢ ( I ) ⁢ Λ ⁢ ⁢ cb ⁢ ⁢ 3 ⁢ ( I ) ) , 0 ≤ I ≤ 15 and, wherein C(I) is a pseudo-orthogonal code of the 9-bit parallel data for 0≦I≦15, b 0 ˜b 8 are the parallel data, and i 0 ˜i 3 are the 4-bit counter values binarized from the I which corresponds to an index for 16-bit pseudo-orthogonal code.