Patent ID: 8151012

Claim:
An apparatus comprising: a memory chip including an array block, and a first buffer coupled to the array block; a plurality of additional buffers coupled to the memory chip; I/O logic coupled to the memory chip to receive memory access requests for elements of the array block; and monitoring logic, coupled to the I/O logic, to monitor a workload of the apparatus by tracking additional buffer hits and misses; the I/O logic further coupled to a memory controller, the memory controller, in response the received memory access requests, to determine if the element is included in the additional buffers, in response to a determination that the element is included in the additional buffers, provide the element via the additional buffers in response to the memory access request, and in response to a determination that the element is not included in the additional buffers, load the element of the array block into the first buffer, load a portion of the contents of the first buffer into the additional buffers, a size of the portion is smaller than the first portion and is based, at least in part, on a spatial locality of the workload of the apparatus, and provide the element via the additional buffers in response to the memory access request.