Patent ID: 7623402

Claim:
A semiconductor memory device that executes a first refreshing executed in accordance with an external command and a second refreshing executed periodically in a timing generated in said semiconductor memory device, comprising: an oscillator that oscillates at an oscillating period which is p times (p: a positive integer or a reciprocal of a positive integer) as long as an activated period (referred to as tRAS period hereinafter) of a cell array for access in said second refreshing, and outputs a periodic signal including a plurality of cycles of said oscillating period, wherein: said second refreshing is executed by activating said cell array for a period equal to 1/p times a first period specified by a number of cycles in said periodic signal, and a period equal to said first period multiplied by q (q: a positive integer) is selected as a refresh period of said second refreshing; and a counter for counting a number of cycles in said periodic signal; and a reset generation unit that outputs a reset signal to said counter when a count of said counter is equal to a value corresponding to said q, wherein and said second refreshing is executed each time said reset generation unit generates a reset.