Patent ID: 7829458

Claim:
A method of forming a wiring structure in a semiconductor device, comprising: forming a first insulation layer on a substrate; forming a preliminary first plug and a preliminary second plug on the substrate through the first insulation layer; forming a second insulation layer on the first insulation layer covering the preliminary first plug and the preliminary second plug; forming a bit line structure on the second insulation layer, the bit line structure being electrically connected to the first plug; forming an opening by etching the second insulation layer to expose a sidewall of the bit line structure, the preliminary first plug and the preliminary second plug; forming a first plug and a second plug by partially etching the preliminary first plug and the preliminary second plug, the first plug having a recess on an upper peripheral portion; forming a protection spacer on the recess of the first plug and the sidewall of the bit line structure; and forming a pad on the second plug filling the opening.