Patent ID: 7777534

Claim:
A fraction-N frequency divider comprising: a multi-phase clock generator, for generating a plurality of clock signals with different phases corresponding to an input signal; a first phase selector, coupled to the multi-phase clock generator, for receiving the plurality of clock signals and for selecting one of the clock signals as a first clock signal according to a first phase selecting signal; a second phase selector, coupled to the multi-phase clock generator, for receiving the same plurality of clock signals as the first phase selector and for selecting one of the clock signals as a second clock signal according to a second phase selecting signal; a glitch-free multiplexer, coupled to the first phase selector and to the second phase selector, for selectively outputting one of the first clock signal and the second clock signal to provide a glitch-free clock signal; a control circuit, coupled to the first phase selector, to the second phase selector, and to the glitch-free multiplexer, for generating the first phase selecting signal and the second phase selecting signal according to a divisor setting, and controlling the clock switching timing of the glitch-free multiplexer; and a counter, coupled to the glitch-free multiplexer, for generating a frequency-divided signal according to the glitch-free clock signal.