Patent ID: 8553488

Claim:
A memory, comprising: a memory array; a plurality of control circuits configured to generate control signals for the memory array, wherein the plurality of control circuits comprise a plurality of word line driver circuits; a plurality of isolation circuits coupled to the plurality of control circuits, wherein the plurality of isolation circuits are configured to receive a plurality of isolation signals to isolate various ones of the control circuits, wherein a first isolation signal of the plurality of isolation signals corresponds to the plurality of word line driver circuits and at least one second isolation signal of the plurality of isolation signals corresponds to other ones of the plurality of control circuits, wherein the first isolation signal and the second isolation signal are independently controlled during a memory test to detect stuck-at faults associated with the plurality of isolation signals; wherein the memory is coupled to a testing circuit, wherein, to perform the memory test, the testing circuit is configured to: 1) write a first test pattern in one or more memory locations of the memory array; 2) assert the first isolation signal that controls isolation of the plurality of word line driver circuits; 3) while the first isolation signal is asserted, perform a read of the one or more memory locations of the memory array; 4) compare a result of the read to the first test pattern; and 5) determine a test result based on said comparing.