Patent ID: 7065168

Claim:
A digital circuitry, operative repetitively to perform a series of processing cycles, comprising: an input signal processing circuit performing, in each cycle, a predetermined processing operation on one or more input signal(s) received by the digital circuitry to derive therefrom one or more first signal(s), said predetermined processing operation being commenced in response to a first clock signal; a first clocked element receiving said one or more first signal(s) and a second clock signal, and producing one or more second signal(s), said first clocked element being switchable by said second clock signal between a first responsive state, in which the first clocked element changes said one or more second signal(s) in response to a change in said one or more first signal(s), and a first non-responsive state in which no change in said one or more second signal(s) occurs; a second clocked element receiving said one or more second signal(s) and a third clock signal, and producing one or more output signal(s) of said digital circuitry, said second clocked element being switchable by said third clock signal between a second responsive state, in which the second clocked element changes said one or more output signal(s) in response to a change in said one or more second signal(s), and a second non-responsive state in which no change in said one or more output signal(s) occurs; and a clock generating circuitry generating the second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a preselected delay time and said third clock signal being delayed relative to the first clock signal by less than said preselected delay time such that in each cycle the first clocked element enters said first non-responsive state before the end of said predetermined processing operation, and said second clocked element enters said second responsive state when the first clocked element is in said first non-responsive state.