Patent ID: 7761588

Claim:
An article of manufacture comprising at least one of hardware logic and a non-transitory computer readable storage medium having code that is implemented at an initiator node including an initiator adaptor to communicate with a target node, wherein the code is executed by the at least one of hardware logic and a processor to perform: communicating with the target node using a first communication protocol that uses an interface protocol to communicate using a second communication protocol to establish a connection for the second communication protocol; creating, with the interface protocol, data structures to enable communication with the target node to establish the connection with the target node for the second communication protocol; invoking an extension layer for the second communication protocol; passing the data structures to the extension layer to use to communicate with the target node using the second communication protocol; receiving a message including a direct reference to a memory location to invalidate from the target node through an initiator adaptor, wherein the direct reference is compatible with the second communication protocol, and wherein the initiator adaptor does not enable direct invalidating of the reference; invoking the initiator adaptor to invalidate the direct reference in response to determining that the direct reference does match one reference in a map; invalidating at least one direct reference indicated in the map associated with an indirect reference included in the invalidate message in response to determining that the direct reference does match one reference in the map or that the direct reference is not provided; and issuing, by the extension layer, an invocation to terminate the interface protocol, wherein the extension layer uses the data structures created by the interface protocol to communicate with the target node.