Patent ID: 8368829

Claim:
A liquid crystal display device comprising plurality of pixels that are arranged in columns and rows so as to form a matrix pattern, each said pixel including liquid crystal layer and a plurality of electrodes for applying a voltage to the liquid crystal layer, wherein each said pixel includes a first subpixel and a second subpixel, having liquid crystal layers to which mutually different voltages are applicable, and two switching elements that are provided for the first and second subpixels, respectively, and wherein each of the first and second subpixels includes a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them, and wherein the counter electrode is a single electrode provided in common for the first and second subpixels, while the storage capacitor counter electrodes of the first and second subpixels are electrically independent of each other, and wherein the device further includes a plurality of electrically independent storage capacitor trunks, and wherein each said storage capacitor trunk is electrically connected to the respective storage capacitor counter electrodes of either the first subpixels or the second subpixels of the pixels through storage capacitor lines, and wherein the storage capacitor trunks include an even number L of electrically independent storage capacitor trunks, and wherein a storage capacitor counter voltage to be supplied by way of each said storage capacitor trunk to its associated storage capacitor line has a first period (A) with a first waveform during one vertical scanning period, the first waveform oscillating between multiple voltage levels in a first cycle time (P A ), which is either K·L or 2·K·L times as long as one horizontal scanning period (H), where K is a positive integer and K·L or 2·K·L is at least equal to four, and wherein while the two switching elements are both ON, a display signal voltage is applied to the respective subpixel electrodes and respective storage capacitor electrodes of the first and second subpixels; after the two switching elements have been turned OFF, voltages at the respective storage capacitor counter electrodes of the first and second subpixels change; and if an interval between a point in time when the two switching elements in ON state have just been turned OFF and a point in time when the storage capacitor counter voltage changes for the first time is βH, the device satisfies the inequality P A /4H−1−Int (K/2)≦βP A /4H+Int(K/2) in each said pixel, where Int(x) is the integral part of an arbitrary real number x.