Patent ID: 8125828

Claim:
A reading method for a multi-level cell memory device, the method comprising: initializing a higher-bit register and a lower-bit register provided in a page buffer of the memory device having a plurality of wordlines and a plurality of multi-level cells, each cell being coupled to first and second bit lines and is configured to store at least two bits of data; selecting one of the first and second bitlines; coupling the selected bitline to a sensing node in response to a bitline selection signal and a discharge signal; selecting the lower-bit register as a read register according to read-control signals after one of the wordlines is selected; and reading a lower data bit from a selected multi-level cell corresponding to the selected bitline and the selected wordline by using the lower-bit register, wherein the step of reading the lower data bit includes detecting a voltage of the sensing node which is determined by a first read data bit output from the selected multi-level cell and storing a first lower sensing data bit into the lower-bit register in accordance with a result of the detection in response to a first lower read- control signal when a first read voltage is being supplied to the selected wordline, detecting a voltage of the sensing node which is determined by a second read data bit output from the selected multi-level cell and storing a second lower sensing data bit into the lower-bit register in accordance with a result of the detection in response to a second lower read-control signal when a second read voltage is being supplied to the selected wordline, transferring the second lower sensing data bit from the lower-bit register to the higher-bit register through the sensing node in response to a program control signal, detecting a voltage of the sensing node which is determined by the second lower sensing data bit and storing a higher sensing data bit into the higher-bit register in accordance with a result of the detection in response to a first higher read-control signal, inversing the higher sensing data bit and outputting the inverse of the higher sensing data bit, and outputting the inverse of the higher sensing data bit to a data input/output node as the lower data bit in response to an output control signal, wherein a logical value of the second lower sensing data bit is identical to or different from a logical value of the first lower sensing data bit.