Patent ID: 8169429

Claim:
A driving power supply circuit for controlling a driving voltage to have a voltage between a lower reference voltage and an upper reference voltage and for outputting said driving voltage from an output node comprising; a p-channel MOS transistor connected between a power supply conductor and said output node and being configured to be on when a first signal has a first logic level and to be off when said first signal has a second logic level; an n-channel MOS transistor connected between said output node and a ground conductor and being configured to be off when a second signal has the first logic level and to be on when said second signal has the second logic level; a logic circuit configured to output a first control signal when said first signal and said second signal have the first logic level, to output a second control signal when said first signal and said second signal have the second logic level, and to output a third control signal when said first signal has the second logic level and said second signal has the first logic level; a first comparing circuit configured to compare said driving voltage to said lower reference voltage in a high-speed-operation mode in response to said first control signal, to compare said driving voltage to said lower reference voltage in a low-power-consumption mode in response to said third control signal, to set said first signal to the second logic level and output said first signal to said p-channel MOS transistor when said driving voltage is higher than said lower reference voltage, and to set said first signal to the first logic level and output said first signal to said p-channel MOS transistor when said driving voltage is lower than said lower reference voltage; and a second comparing circuit configured to compare said driving voltage to said upper reference voltage in a high-speed-operation mode in response to said second control signal, to compare said driving voltage to said upper reference voltage in a low-power-consumption mode in response to said third control signal, to set said second signal to the second logic level and output said second signal to said n-channel transistor when said driving voltage is higher than said upper reference voltage, and to set said second signal to the first logic level and output said second signal to said n-channel transistor when said driving voltage is lower than said reference voltage.