Patent ID: 8313991

Claim:
A method for fabricating a high-K metal gate MOS device, the method comprising: providing a semiconductor substrate; forming a gate oxide layer over a surface region of the semiconductor substrate; forming a sacrificial gate electrode overlying the gate oxide layer; depositing a covering layer overlying the sacrificial gate electrode; depositing an inter-layer dielectric layer overlying the semiconductor substrate and the covering layer; planarizing the inter-layer dielectric layer until a portion of the covering layer atop the sacrificial gate electrode is exposed; implanting nitrogen ions in the inter-layer dielectric layer and the covering layer, wherein a depth of the nitrogen ions implantation is greater than a thickness of the portion of the covering layer atop the sacrificial gate electrode; polishing the inter-layer dielectric layer and the covering layer until a portion of the sacrificial gate electrode is exposed; removing the sacrificial gate electrode and the gate oxide layer to expose at least a portion of the surface region of the semiconductor substrate; depositing a high-K dielectric layer overlying the exposed portion of the surface region of the semiconductor substrate; and depositing a metallic layer overlying the high-K dielectric layer.