Patent ID: 7486725

Claim:
A bit error rate tester for counting a number of bit errors of an object to be tested, and the bit error rate tester comprising: a transmitter pseudo random bit sequences generator for generating a parallel N-bit original pseudo random bit sequences, wherein N is an integer greater than 1 and the object to be tested outputs a parallel N-bit code to be tested after receiving the original pseudo random bit sequences; a master pseudo random bit sequences generator for generating a parallel N-bit master pseudo random bit sequences; a slave pseudo random bit sequences generator for generating a parallel N-bit slave pseudo random bit sequences; a comparator for receiving, comparing, and determining whether the parallel N-bit code to be tested, the master pseudo random bit sequences, and the slave pseudo random bit sequences are the same or not, and outputting a comparison result; and a counting unit coupling to the comparator for counting the number of bit errors based on the comparison result; wherein, each of the transmitter pseudo random bit sequences generator, the master pseudo random bit sequences generator, and the slave pseudo random bit sequences generator comprises: a pseudo random bit sequences generating circuit for generating a parallel (N+P−1)-bit source pseudo random bit sequences having a maximum pattern length of 2 M −1, where M and P are the integers greater than 1, comprising: a plurality of pre-counting circuits, each of the pre-counting circuits is used to perform a logic operation based on one of a plurality algorithms and output one of a plurality of (N+P−1)-bit pre-counting results; at least one multiplexer module, comprising (N+P−1) multiplexers, each of the (N+P−1) multiplexers outputs one bit of one of the (N+P−1)-bit pre-counting results based on a pattern length selection signal; and at least a register module, comprising (N+P−1) registers, each of the (N+P−1) registers temporarily storing an output of one of the (N+P−1) multiplexers based on a timing and outputs one bit of the parallel (N+P−1)-bit source pseudo random bit sequences; wherein, each of the pre-counting circuits receives the parallel (N+P−1)-bit source pseudo random bit sequences and performs the logic operation on the parallel (N+P−1)-bit source pseudo random bit sequences based on the one of the algorithms, so as to output one of the pre-counting results, respectively; and a mark density control circuit for receiving the parallel (N+P−1)-bit source pseudo random bit sequences, and changing a mark density of the parallel (N+P−1)-bit source pseudo random bit sequences based on a mark density selection signal for outputting the parallel N-bit original pseudo random bit sequences, the parallel N-bit master pseudo random bit sequences, or the parallel N-bit slave pseudo random bit sequences respectively having a minimum mark density of ½ P .