Patent ID: 7936222

Claim:
A phase-locked loop circuit comprising: a first decimator receiving a reference signal to generating a decimated version of the reference signal by a decimation factor N; a second decimator receiving a clock signal to generate a decimated version of the clock signal by a decimation factor of N; a first phase detector generating first phase error information according to a phase difference between the decimated version of the reference signal and the decimated version of the clock signal input to the first phase detector; a second phase detector generating second phase error information according to a phase difference between the reference signal and the clock signal input to the second phase detector; a proportional charge pump generating a first voltage according to the second phase error information; an integral charge pump generating a second voltage according to the first phase error information; and a voltage-controlled oscillator (VCO) generating the clock signal according to a combination of the first and second voltages.