Patent ID: 8456884

Claim:
A semiconductor device comprising: a memory cell array in which a plurality of memory cells are arranged at least in one row, wherein the memory cell has an electric fuse device with a resistance value changeable according to a flowing current and a plurality of cell transistors having a source or a drain which is connected to one end of the electric fuse device, and the semiconductor device further including: a plurality of first lines each connected to a gate of each cell transistors in a form that all the cell transistors arranged on a current path at the time of reading out of all cell transistors and all the cell transistors not arranged on the current path at the time of reading out of all cell transistors are able to be turned ON/OFF independently from each other; a second line connected to the other end of the electric fuse device; and a third line connected to one of the source and the drain of each cell transistor which is not connected to the electric fuse device.