Patent ID: 8527257

Claim:
A method for generating an analog model of a logic cell, comprising: generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell; generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data; and generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell, the analog model including: one or more input nodes, each input node representing an input of the logic cell; one or more output nodes, each output node representing an output of the logic cell; a logic block for modeling Boolean logic of the logic cell, the logic block receiving each of the one or more input nodes as an input and configured to calculate an output based on the received input; a multiplexer receiving the output of the logic block as a select input, and receiving a low threshold signal and a high threshold signal at its data inputs and configured to output a transitioning analog signal; a transition-based parameter block receiving each of the one or more input nodes as an input and configured to, based on values of the one or more input nodes and parameters selected from the parameterized transition based analog model, output transition timing parameters; and a transition function block receiving the output of the multiplexer and the transition timing parameters, the transition function block configured to output an output logic signal, the output logic signal modeling behavior of the logic cell in response to inputs to the one or more input nodes.