Patent ID: 6838331

Claim:
A method of operating a dynamic random access memory (“DRAM”) device in a power-saving mode, comprising: reading a set of data bits from each of a plurality of groups of memory cells in the DRAM device; generating a respective set of check bits corresponding to each of the sets of data bits read from each group of memory cells; storing the sets of check bits in the DRAM device; after a delay, reading each set of data bits and corresponding sets of check bits from the memory cells; generating a set of syndrome bits derived from each of a respective set of data bits read from the DRAM device and from the corresponding set of check bits read from the DRAM device; determining from each of the sets of syndrome bits if any of the respective set of read data or read check bits is in error; if the syndrome indicates any bits of the read data is in error, correcting the error to generate corrected data; if the syndrome indicates any of the check bits is in error, correcting the error to generate corrected check bits; writing any corrected data to the DRAM device; writing any corrected check bits to the DRAM device; and setting the delay before a subsequent reading of data bits and corresponding sets of check bits as a function of the number of bits of data or check bits the syndrome indicates is in error.