Patent ID: 7531872

Claim:
A high voltage transistor, comprising: a single insulation layer on a substrate; an N + -type drain junction region on the single insulation layer; an N − -type drain junction region on the N + -type drain junction region; a P − -type body region provided in a first trench region of the N − -type drain junction region; a plurality of first gate patterns including a first gate insulation layer and a first gate conductive layer in other trench regions bordered by the P − -type body region and the N − -type drain junction region; a plurality of first source regions contacted to a first source electrode on the P − -type body region; a plurality of N + -type drain regions contacted to the N − -type drain junction region and individual drain electrodes; a P + -type drain junction region formed on the single insulation layer, wherein the P + -type drain junction region is formed to be apart from the N + -type drain junction region; a P − -type drain junction region formed on the P + -type drain junction region; an N − -type body region provided in a second trench region inside of the P − -type drain junction region; a plurality of second gate patterns including a second gate insulation layer and a second gate conductive layer in other trench regions bordered by the N − -type body region and the P − -type drain junction region; a plurality of second source regions contacted to a second source electrode on the N − -type body region; and a plurality of P + -type drain regions contacted to the P − -type drain junction region and individual drain electrodes.