Patent ID: 7868663

Claim:
A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having different phases sequentially enabled, the receiver circuit comprising: a sense amplifier configured to receive first signals as offset voltages, the first signals obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequent to the first clock signal, and configured to output second signals; a discharging controller configured to control a drive speed by controlling a discharging speed of the sense amplifier according to the offset voltages; a second sense amplifier configured to be synchronized with a third clock signal enabled subsequent to the second clock signal, and further configured to receive the second signals as second offset voltages, and sense and amplify the input data; and a second discharging controller coupled to the second sense amplifier, the second discharging controller configured to control potentials on nodes of the second sense amplifier according to the second offset voltages and to control a driven speed of the second sense amplifier.