Patent ID: 7418534

Claim:
An integrated circuit comprising: one or more processors coupled to an internal bus of the integrated circuit; a cache memory coupled to the bus to cache data for the integrated circuit; a plurality of interface circuits to transfer packet and non-packet data, wherein each interface circuit is to operate upon a particular mode of communication to transfer respective packet or non-packet data, in which one or more devices are coupled to respective one of the interface circuits based on respective mode of communication for transfer of respective data; and a bridge circuit coupled to the plurality of interface circuits and to the bus to transfer data between the interface circuits and the bus, the bridge circuit to maintain cache coherency for data cached in the cache memory for devices operable within the integrated circuit, but cache coherency is not maintained by the bridge circuit for data cached in the cache memory by one or more external devices coupled to the interface circuits, wherein the one or more processors, cache memory, plurality of interface circuits and bridge circuit are constructed on one integrated circuit chip as an integrated system on a chip.