Patent ID: 7610502

Claim:
A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device, comprising: an address bus; a control bus; an internal data bus; an address decoder coupled to the address bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit; and a read/write circuit coupled to the memory-cell array through the internal data bus to output data received from the memory-cell array, the read/write circuit including a synchronous data output circuit, comprising: an output driver having a data input terminal coupled to the internal data bus to receive input data, an output terminal at which output data is provided, and a clock terminal at which a clock signal is applied, the output driver configured to provide the input data as the output data in response to the clock signal; a synchronizing circuit having an input terminal at which an external clock signal is applied and having an output terminal at which an internal clock signal is provided; and a delay circuit having an input coupled to the output of the synchronizing circuit, an output coupled to the clock terminal of the output driver, and a selection terminal for receiving a selection signal, the delay circuit configured to provide the clock signal to synchronize output by the output driver, the clock signal having a delay with respect to the internal clock signal according to one of a plurality of programmable time delay circuits having different time delays and selected in accordance with the selection signal.