Patent ID: 7382054

Claim:
A method of manufacturing semiconductor devices on a semiconductor substrate, comprising the steps of: forming a plurality of multi-layer structures on the semiconductor substrate, wherein there are active source and drain device regions between and below the plurality of multi-layer structures; forming an etch stop layer over the semiconductor substrate with the plurality of multi-layer structures; forming a first dielectric layer over the etch stop layer, wherein the thickness of the first dielectric layer is greater than the combined thickness of the plurality of the multi-layer structures and the etch stop layer; planarizing the first dielectric layer to expose a portion of the etch stop layer; etching through the first dielectric layer and through the etch stop layer to create openings of the first portions of contacts and local interconnects simultaneously; depositing a first conductive layer in the first portions of contacts and local interconnects; planarizing the first conductive layer by chemical mechanical polishing to remove the first conductive layer that is not in the openings of the first portions of contacts and local interconnects; depositing a second dielectric layer over the first dielectric layer; patterning second portions of contacts above the first portions of contacts and etching through the second dielectric layer to create openings of the second portions of contacts above the first portions of contacts; and filling up a second conductive layer in the second portion of contacts, wherein the second conductive layer is in contact with the first conductive layer in the openings of the first portions of contacts.