Patent ID: 8279865

Claim:
A computer system comprising: a general purpose multi-core processor including a plurality of processing cores; and memory communicably coupled with the general purpose multi-core processor, wherein the memory includes a plurality of instructions executed by the general purpose multi-core processor, the plurality of instructions comprising: instructions executed by the general purpose multi-core processor to allocate a shared memory portion of the memory, wherein the shared memory is accessible from more than one context of execution; instructions executed by the general purpose multi-core processor to process a frame in a plurality of processing stages comprising at least a first processing stage executed in kernel space and a second processing stage executed in user space, wherein the first processing stage and the second processing stage are processed by separate contexts of execution; instructions executed by the general purpose multi-core processor to bind each of the plurality of processing stages to a processing core of the multi-core processor; and instructions executed by the general purpose multi-core processor to connect one or more processing stages with a point-to-point communication mechanism that allows the first processing stage and the second processing stage to exchange data related to the frame through mutual access to the shared memory portion of the memory.