Patent ID: 7990201

Claim:
A digital attenuator circuit comprising: an input node to receive an input signal to be attenuated; an output node to present an attenuated signal; a reference loss path between the input node and the output node comprising (i) a plurality of first series transistors and (ii) a plurality of cascaded shunt transistors each connected to a respective one of the plurality of first series transistors, wherein the input signal is varied in response to (a) a first voltage applied to a first biasing node connected to the plurality of first series transistors and (b) a second voltage applied to a second biasing node connected to the plurality of cascaded shunt transistors to improve Voltage Standing Wave Ratio (VSWR), wherein each of said plurality of cascaded shunt transistors receive said second voltage from said second biasing node; and an attenuation path between the input node and the output node comprising a plurality of second series transistors, wherein the input signal is varied in response to a third voltage applied to a third biasing node connected to the plurality of second series transistors to (i) attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state, (ii) equalize an effective phase length of the reference loss path and an effective phase length of the attenuation path and (iii) provide a constant phase when the digital attenuator circuit is switched between states.