Patent ID: 7818543

Claim:
A processing unit comprising: a length decode unit configured to obtain a plurality of instruction bytes based on a scan window of a predetermined size, wherein the instruction bytes are associated with a plurality of variable length instructions which are to be executed by the processing unit; wherein, for each instruction byte, the length decode unit is configured to estimate the start of a next variable length instruction following a current variable length instruction associated with a current instruction byte, and store, for each instruction byte, a first pointer to the estimated start of the next variable length instruction within the scan window; a pre-pick unit configured, for each instruction byte, to use the first pointer indicating the estimated start of the next variable length instruction to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store, for each instruction byte, a second pointer to the estimated start of the subsequent variable length instruction; and a pick unit configured to obtain a start pointer, which points to the instruction byte corresponding to the actual start of a first variable length instruction within the scan window, wherein the pick unit is configured to use the first and second pointers associated with the instruction byte corresponding to the actual start of the first variable length instruction to determine the actual start of additional variable length instructions within the scan window.