Patent ID: 7966435

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: an interface system comprising: a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, and wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; a read pointer that points to data read by the destination, wherein the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously, wherein a sampled copy of the write pointer is sent to the second clock domain to notify the second clock domain that data in the buffer is available for reading; and a hold unit to cause a delay in sending the sampled copy of the write pointer to the second clock domain by causing a delay in creating the sampled copy of the write pointer for a selected number of clock cycles.