Patent ID: 8027551

Claim:
A reconfigurable image processor for image processing, comprising: an arithmetic module, having a plurality of reconfigurable arithmetic units reconfigured to perform corresponding data processing actions; a first memory unit, coupled to said arithmetic module, storing at least one configuration; a bus control module, coupled to said first memory unit and a system bus for being coupled to an external device; and a connecting module, coupled to said arithmetic module, said first memory unit and said bus control module, wherein said connecting module reconfigures connections among said reconfigurable arithmetic units via said configuration, wherein said reconfigurable arithmetic units individually comprise: a context register, coupled to said first memory unit; an input source selector, coupled to said connecting module and said context register; a datapath unit, coupled to said context register and said input source selector for performing data operations; an output register, coupled to said connecting module and said datapath unit for storing output data; and a module controller, coupled to said context register, said datapath unit and said output register.