Patent ID: 7979679

Claim:
A processor for use in a computer system for conditionally carrying out an operation defined in a computer instruction, the processor comprising: input stores that hold a plurality of objects of a predetermined size, each object being associated with one of a plurality of lanes; a plurality of operators associated respectively with said lanes for carrying out the operation specified in the computer instruction on objects in corresponding lanes of said input stores; a condition code generator to generate one or more condition codes that are a side effect of executing a prior operation, and to store the generated one or more condition codes as stored condition values; and a condition code checker coupled to switches, wherein the condition code checker and switches determine for each lane whether the operation is to be executed on objects in that lane, the determination being based on the stored condition values, wherein two or more of the stored condition values are set to a same value when a degree of packing of the plurality of objects is less than a quantity of the plurality of lanes.