Patent ID: 7741152

Claim:
A method of making a three-dimensional package, comprising the following steps: (a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad; (b) forming at least one blind hole on the first surface of the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer covering the pad, the protection layer and the isolation layer; (e) forming a dry film on the conductive layer, the dry film having an opening at the position corresponding to the blind hole; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer, and the exposed conductive layer is cup-shaped, so as to accommodate the solder; (j) stacking a plurality of the wafers, and performing a reflow process, so that the conductive layer directly contacts and is embedded into the solder of the adjacent wafers; and (k) cuffing the stacked wafers, so as to form a plurality of three-dimensional packages.