Patent ID: 7839187

Claim:
A frequency divider, comprising: a transmission gate transmitting a clock signal according to an inverted enable signal; a first inverter inverting the clock signal outputted from the transmission gate; a first switch circuit generating a first control signal according to the inverted clock signal and an output signal of the frequency divider; a second switch circuit generating a second control signal according to the clock signal, the inverted clock signal, and the first control signal, wherein the second switch circuit comprises: a first transistor having a gate, a source, and a drain, wherein the source of the first transistor receives a supply voltage; a fourth transistor having a gate, a source, and a drain, wherein drain of the fourth transistor is connected to a ground terminal, and the gates of the first transistor and the fourth transistor receive the first control signal from the first switch circuit; a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor receives the clock signal, and the source of the second transistor is connected to the drain of the first transistor; and a third transistor having a gate, a source, and a drain, wherein the gate of the third transistor receives the inverted clock signal, the drain of third transistor, connected to the drain of the second transistor, outputs the second control signal, and the source of the third transistor is connected to the source of the fourth transistor; and a second inverter inverting the second control signal to generate the output signal, wherein the frequency of the clock signal is a multiple of the frequency of the output signal.