Patent ID: 7192825

Claim:
A method for fabricating a semiconductor memory device, comprising the steps of: forming a plurality of gate structures on a substrate; forming a storage node contact junction region extending below an upper surface of the substrate, the storage node contact junction region provided between two adjacent gate structures; forming an insulating spacer on sidewalls of the two adjacent gate structures; etching a first portion of the storage node contact junction region a given thickness to form a first trench including first trench sidewalls offset from sidewalls of the two adjacent gate structures such that a first distance between the first trench sidewalls is less than a second distance between the two adjacent gate structures, the first trench exposed by the insulating spacer, wherein the first trench sidewalls extend from the upper surface of the substrate to a lower surface of the trench contacting the storage node contact junction region; forming a dopant diffusion barrier layer on sidewalls of the insulating spacer and first trench sidewalls such that the dopant diffusion barrier layer covers the first trench sidewalls; etching a second portion of the storage node contact junction region exposed by the dopant diffusion barrier layer, thereby forming a second trench such that the width of the second trench is less than that of the first trench; and forming a contact plug within a space created between the gate structures and inside of the first trench and the second trench, the contact plug substantially filling in the second trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.