Patent ID: 8687446

Claim:
A semiconductor device testing system, the system comprising: an external testing device configured to produce control signals and refresh signals including preliminary refresh signals and location refresh signals, at least some of the preliminary refresh signals used in producing the location refresh signals, wherein the preliminary refresh signals and the location refresh signals include row address strobe (RAS) signals; one or more semiconductor devices; and an interface allowing connection between the one or more semiconductor devices and the external testing device; wherein at least one of the one or more semiconductor devices comprising: a memory array; self refresh circuitry configured to receive the control signals and the refresh signals from the external testing device through the interface; selection circuitry receiving the location refresh signals and selecting memory locations within the memory array to be refreshed in response to the location refresh signals; and a self refresh controller interacting with the self refresh circuitry and transmitting indicating signals to the external testing device through the interface, the self refresh controller comprising a self refresh test mode controller for placing the semiconductor device in a self refresh test mode when receiving the control signals and the refresh signals from the external testing device through the interface and responding to the control signals and the refresh signals by modifying performance of the self refresh of the memory array while in the self refresh test mode; wherein the indicating signals include at least one of internal RAS signals, RAS chain signals, or equilibrate signals.