Patent ID: 8659068

Claim:
A DRAM memory structure, comprising: a substrate; a first strip semiconductor material disposed on said substrate and extending along a first direction; a split gate disposed on said substrate, extending along a second direction and comprising independently a first block and a second block to divide said first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer at least partially sandwiched between said split gate and said substrate; a first gate dielectric layer at least partially sandwiched between said split gate and said strip semiconductor material; and a first capacitor unit electrically connected to said first source terminal, wherein said first capacitor unit is disposed on said substrate and comprises said first source terminal serving as a bottom electrode, a second dielectric layer at least partially covering said first source terminal to serve as a capacitor dielectric layer, and a capacitor metal layer at least partially covering said second dielectric layer to serve as a top electrode.