Patent ID: 7999377

Claim:
A 3-D integrated semiconductor structure prior to dicing said structure into discrete chip stacks comprising: a plurality of discrete structures, each said discrete structure comprising a handle wafer chip attached to a side of a first semiconductor chip which has been tested and determined to be functioning, said first semiconductor chip having a capture pad on a side opposite said handle wafer chip; and a wafer including a plurality of second semiconductor chips formed at chip sites thereon, each second semiconductor chip including at least one capture pad on a side thereof, wherein said first and second semiconductor chips are oriented such that said sides containing said at least one capture pad are internally positioned and face one another and wherein at least one capture pad of said first semiconductor chip on one of said discrete devices is bonded to said at least one capture pad of one of said plurality of second semiconductor chips at one of said chip sites on said wafer which has been tested and determined to be functioning and wherein a first semiconductor chip having been determined to be functional is not bonded to a second semiconductor chip site on said wafer which has been tested and determined not to be fully functional.