Patent ID: 8595597

Claim:
A system comprising: a NAND memory device; and a controller operatively coupled to the NAND memory device to determine a storage fidelity of the NAND memory device during operation of the NAND memory device, including a first a raw bit error rate (RBER) of the NAND memory device, determine whether the first RBER of the NAND memory device is less than a second RBER, the second RBER comprising an expected RBER for an end-of-life storage fidelity state for the NAND memory device, and adjust a programming speed characteristic of the NAND memory device, based on the storage fidelity of the NAND memory device, to increase the RBER of the NAND memory device in response to determining that the first RBER is less than the second RBER; the NAND memory device to execute an error correction code (ECC) to correct bit errors that occur during a read operation of the NAND memory device, the ECC provisioned for the expected RBER for the end-of-life storage fidelity state of the NAND memory device.