Patent ID: 8391048

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of first wirings, a plurality of second wirings crossing the plurality of first wirings, and a plurality of memory cells that respectively includes a variable resistor made of a hafnium oxide-based material and a diode serially connected to the variable resistor, and arranged at intersections of the plurality of first wirings and the plurality of second wirings; and a controller operative to select a given one of the memory cells, to generate an erase pulse which is used for erasing data, and to supply the erase pulse to the selected memory cell, wherein the erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell, the memory cell array is an equal or smaller than 22-nm generation memory cell array including equal or more than 1K×8K of the memory cells, the controller generates the erase pulse of a pulse width of a number of steps S (where S is an integer of not smaller than 2), and a relationship between a maximum value Tpmax of the pulse width of the erase pulse and a minimum value Tpmin thereof satisfies Log(Tpmax)≧0.8×(S-1)/S+Log(Tpmin).