Patent ID: 8144705

Claim:
A device comprising: a packet processor to: receive a packet, and process the packet to extract information from the packet to form a lookup key; and a multi-bank static random access memory (SRAM) processor to: receive the lookup key from the packet processor, where the lookup key includes a first address associated with a plurality of SRAMs, provide the first address to at least one of the plurality of SRAMs that store a recursive tree data structure, where access to the recursive tree data structure is iterative, and a memory address, corresponding to a first read transaction associated with the recursive tree data structure, depends on data acquired during a second read transaction, associated with the recursive tree data structure, that occurred prior to the first read transaction, read first data, from the at least one of the plurality of SRAMs, using the first address, determine that the first data is intermediate data that includes information associated with a plurality of next addresses in the recursive tree data structure, provide the plurality of next addresses to one or more of the plurality of SRAMs in response to determining that the first data is intermediate data, where the multi-bank SRAM processor, when providing the plurality of next addresses, is further to: determine, based on a particular field in the first data, points in the recursive tree data structure, and generate the plurality of next addresses using the first data, where the plurality of next addresses are associated, respectively, with the determined points in the recursive tree data structure, read second data from the one or more of the plurality of SRAMs using the plurality of next addresses, and transmit the second data to the packet processor in response to determining that the second data includes final data that does not include information associated with another address related to the recursive tree data structure.