Patent ID: 6867620

Claim:
A latchless dynamic asynchronous digital pipeline circuit comprising: a first processing stage configured to be driven through a cycle of phases consisting of a first precharge phase, followed by an first evaluate phase, and followed by a first isolate phase, solely in response to a first precharge control signal and a first evaluate control signal, wherein the output of the first processing stage is isolated from changes in the input thereof when in the first isolate phase and wherein the first precharge control signal is decoupled from the first evaluate control signal; a first stage controller responsive to a transition signal indicative of a phase of a second processing stage and configured to provide the first precharge control signal and first evaluate control signal to the first processing stage; a second processing stage configured to be driven through a cycle of phases consisting of a second precharge phase, followed by a second evaluate phase, and followed by a second isolate phase, solely in response to a second precharge control signal and a second evaluate control signal; a completion generator which is configured to provide the transition signal indicative of the phase of the second processing stage which is asserted upon completion of the second evaluate stage, wherein one interconnection is provided between the first processing stage and the second processing stage such that reception by the first stage controller of the transition signal indicative of the stage of the second processing stage enables the first processing stage to cycle through the precharge phase, the evaluate phase, and the isolate phase when the transition signal indicative of the phase of the second processing stage is asserted.