Patent ID: 8095707

Claim:
An apparatus for synchronizing peripherals in an embedded system comprising: a central processing unit (CPU); at least one input/output (I/O) peripheral; an address decoder and synchronizer(ADS) coupled to the CPU and the at least one input/output (I/O) peripheral wherein the ADS comprises: (a) an address decoder coupled to receive an address from the CPU and provide a translated address identifying one of the at least one I/O peripheral to be accessed; (b) an I/O peripheral clock sampler synchronizer (PCSS) coupled to receive the translated address, data, and control information from the CPU; (c) a CPU clock sampler synchronizer (CCSS) coupled to receive data and the acknowledgement from the at least one I/O peripheral; and (d) a timer and arbitrator (TA) circuit coupled to the CPU, the CCSS, and the address decoder, the TA circuit receiving: acknowledgement signals from the CCSS in response to receiving the acknowledgement from at least one I/O peripheral; the translated address from the address decoder; and data and control information from the CPU, wherein the TA circuit comprises: a timer coupled to the CPU and the address decoder, the timer generating a timeout signal after a predefined time duration; and an Enable Generation Circuit (EGC) coupled to the timer, the CPU, and the CCSS, the EGC enabling and/or disabling the operation of the CPU in response to the acknowledgement from the CCSS or the timeout signal from the timer; and a memory coupled to the ADS, wherein data read from or written to the at least one I/O peripheral is stored into a designated location of the memory in a clock domain of the at least one I/O peripheral.