Patent ID: 8813013

Claim:
A method comprising: generating, by one or more computer systems, a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD); partitioning, by the one or more computer systems, the circuit design into a first portion and a second portion, the first portion including an interface for coupling the first portion and the second portion; generating, by the one or more computer systems, a first programming file based on the HDL implementation that contains first configuration programming bits for only the first portion and that contains default programming bits for the second portion; generating, by the one or more computer systems, a second programming file based on the HDL implementation that contains second configuration programming bits for only the second portion and that contains default programming bits for the first portion; verifying, or providing to a third-party certification body for verification, at least the second configuration programming bits; revising the first portion; generating revised first configuration programming bits for the revised first portion; merging the revised first configuration programming bits for the revised first portion with the verified second configuration programming bits for the second portion; and providing the merged configuration programming bits for programming into a PLD.