Patent ID: 8233304

Claim:
A memory system, comprising: a system memory bus at least one memory module connected to the system memory bus, the memory module including at least one device, the device having at least one device D/Q (data input/output) terminal having a device output impedance when data is output from the memory module and a device input impedance when data is written into the memory module a memory controller connected to the system memory bus, the memory controller having at least one controller D/Q terminal coupled to the device D/Q terminal via the system memory bus, the controller D/Q terminal having a controller output impedance when data is written into the memory module and a controller input impedance when data is read from the memory module wherein a data signal propagates between the device D/Q terminal and the controller D/Q terminal as a primary signal via a direct path sequentially through a plurality of transmission line segments, each having a respective propagation delay and impedance, and as first and second reflected signals via first and second reflected paths wherein the first and second reflected signals have opposite polarity and similar amplitude and the first and second reflected paths have similar propagation delays such that the first and second reflected signals destructively interfere.