Patent ID: 8487804

Claim:
A successive approximation AD conversion circuit, comprising: a comparator circuit having a plurality of amplifier stages cascaded via coupling capacitances, which judges a magnitude of an input analog voltage and comparison voltages; a register which sequentially takes in and holds judgment results of the comparator circuit; and a local DA conversion circuit which converts values of the register to voltages and generates the comparison voltages, wherein the comparator circuit includes: a first comparator unit and a second comparator unit having a common first amplifier stage among the plurality of amplifier stages, the first comparator unit and the second comparator unit respectively having a first amplifier stage and a second amplifier state connected after the common first amplifier via coupling capacitances, a first comparison point shift circuit connected to an input terminal of the first amplifier stage and a second comparison point shift circuit connected to an input terminal of the second amplifier stage, and a logic circuit which generates a predetermined code according to an output of the first comparator unit and an output of the second comparator unit and generates a value to store in the register by performing a calculation process to the generated code, wherein the first comparison point shift circuit and the second comparison point shift circuit operate so as to shift the comparison voltages by a specified amount in directions opposite from each other when amplifying a potential difference between the input analog voltage and the comparison voltages in the first comparator unit and the second comparator unit.