Patent ID: 7657689

Claim:
A method for independently resetting a side of a bus bridge, the method comprising: receiving a reset signal on a first side of the bus bridge and not on a second side of said bus bridge; resetting a first component associated with the first side of said bus bridge and not resetting a second side of said bus bridge, wherein receiving the reset signal includes synchronously receiving the reset signal at both an interface and an alternating state handler, the interface coupling the first side component to the bus bridge and the alternating state handler being associated with the first side; sending a signal to a second component associated with said second side of the bus bridge after receiving said reset signal, said signal being compliant with a bus protocol of said second side; continuing to operate said second component associated with said second side of the bus bridge while resetting said first component without violating said bus protocol of said second side, wherein the first side corresponds to a first clock domain and the second side corresponds to a different second clock domain; and synchronizing the reset signal with the second side of the bus bridge such that a component associated with the second side transitions to an idle state.