Patent ID: 7320919

Claim:
A method for fabricating a semiconductor device, comprising the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenches; forming a gate conductive layer on the entire surface of the resulting structure so that the trenches are buried; sequentially forming a silicon-rich amorphous metal silicide layer and a gate hard mask on the gate conductive layer; patterning the gate hard mask and the silicon-rich amorphous metal silicide layer until upper portions of the gate conductive layer are removed by a predetermined thickness; forming a metal layer on the entire surface of the patterned structure; blanket etching the metal layer to remove portions of the metal layer and to sequentially remove exposed portions of the gate conductive layer and exposed portions of the gate insulating layer, leaving lateral metal capping layers on sides of the silicon-rich amorphous metal silicide layer and forming patterned gate stacks; and conducting the thermal treatment of the silicon-rich amorphous metal silicide layer constituting the gate stacks to form a crystallized metal silicide layer.