Patent ID: 8397000

Claim:
A system core for transferring instructions to an array processor, the system core comprising: a controller sequence processor (SP) executing an installed array processor program; an SP instruction memory coupled to the SP, the SP instruction memory storing SP instructions and processing element (PE) instructions and coupled to a direct memory access (DMA) bus; a plurality of PEs coupled to the SP and configured in an array processor; and a DMA controller operating under control of a DMA processor executing DMA instructions, the DMA controller coupled to the DMA bus and a system data bus, wherein the DMA processor manages SP and PE instruction transfers between a device coupled to the system data bus and the SP instruction memory coupled to the DMA bus, the SP and PE instruction transfers across the DMA bus to the SP instruction memory occurring in parallel with the plurality of PEs executing a PE instruction distributed from the SP in response to the SP executing the installed array processor program.