Patent ID: 7944242

Claim:
A semiconductor integrated circuit, comprising: a control circuit to output a control signal in a disable state when an input signal is supplied, and to output a control signal in an enable state when the input signal is not supplied; a signal generating circuit to generate a low-frequency signal based on the control signal, the low-frequency signal having a frequency lower than the input signal has; a multiplexer to receive the input signal and the low-frequency signal, to output the input signal upon receipt of the control signal in the disable state, and to output the low-frequency signal upon receipt of the control signal in the enable state; a first logic gate to receive the signal outputted from the multiplexer, the first logic gate having any one of a single stage configuration and a multi-stage configuration; and a second logic gate to receive the control signal and a signal outputted from the first logic gate, to output the signal outputted from the first logic gate upon receipt of the control signal in the disable state, and to stop outputting the signal outputted from the first logic gate upon receipt of the control signal in the enable state.