Patent ID: 7422941

Claim:
A method of forming an integrated circuit chip, comprising: providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip; forming a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, greater than that of said passivation layer, greater than that of said first dielectric layer and greater than that of said second dielectric layer, and wherein said forming said first polymer layer comprises a coating process and a curing process; forming a coil and a metal line on said first polymer layer, wherein said forming said coil comprises an electroplating process, wherein said coil has a thickness greater than that of said first metal layer and greater than that of said second metal layer, wherein said metal line has a thickness greater than that of said first metal layer and greater than that of said second metal layer, and wherein said metal line and said coil are separate from each other; and forming a second polymer layer over said metal line.