Patent ID: 8653877

Claim:
A current mirror modified level shifter, comprising: a pair of PMOS including a PMOS (M PL ) and a PMOS (M PR ), wherein a Vot node is connected to a drain of said PMOS (M PR ); a pair of NMOS including a NMOS (M NL ) and a NMOS (M NR ), wherein sources of said PMOS (M PL ) and said PMOS (M PR ) are coupled to a high voltage (HV), respectively; gates of said PMOS (M PL ) and said PMOS (M PR ) are coupled together through a Vm node which is located between said gates of said PMOS (M PL ) and said PMOS (M PR ); a suspended PMOS (M PM ) coupled to drain of said PMOS (M PL ), said Vm node being coupled to a Va node between drain of said suspended PMOS (M PM ) and drain of said NMOS (M NL ); and a voltage shifter PMOS (M PS ) coupled between gates of said PMOS (M PL ) and said PMOS (M PR ).