Patent ID: 7585730

Claim:
A method of fabricating a non-volatile memory device, the method comprising: forming a tunneling layer and a conductive layer on a semiconductor substrate; patterning each of the conductive layer, the tunneling layer, and the substrate to form a conductive pattern, a tunneling pattern, and a trench in the substrate; filling the trench with a insulating layer; exposing a partial sidewall of the conductive pattern; recessing the exposed partial sidewall of the conductive pattern in an inward direction to form a floating gate comprising a base portion and a protruding portion having a width smaller than that of the base portion; etching the insulating layer to form an isolation layer exposing the base portion of the floating gate; forming a dielectric layer, that extends along the base and protruding portions of the floating gate; and, forming a control gate that covers the base and protruding portions of the floating gate.