Patent ID: 7159200

Claim:
A semiconductor equipment comprising: an oscillating circuit section connected with an oscillator or an oscillating unit, and outputting a source clock signal; an internal circuit for operating synchronously with a system clock; and a duty changing circuit for changing a duty of the source clock outputted from the oscillating circuit section to a predetermined duty shifted away from a value of or around 50%, and for outputting the resultant source clock to the internal circuit as a system clock, wherein the duty changing circuit comprises: a delay generating section comprising a plurality of delay elements connected in series to each other and having an input from the source clock outputted from the oscillating circuit section; a first logic gate for calculating a logic product of a plurality of outputs from arbitrary stages of the plurality of delay elements comprising the delay generating section; a second logic gate for calculating a logic sum of a plurality of outputs from arbitrary stages of the plurality of delay elements comprising the delay generating section; and a latch circuit for switching between a high output and a low output according to output signals from the first logic gate and the second logic gate, and for outputting the signals as the system clock, wherein a signal with a largest delay amount is inputted only to the first logic gate, the signal being outputted from the delay generating section, wherein the internal circuit comprises: an operation circuit section for operating synchronously with one of a leading edge and a trailing edge of a signal outputted by the system clock, and a CTS circuit adjusting an arrival timing of a signal outputted by the system clock at the operation circuit section.