Patent ID: 7145226

Claim:
A microelectronic package, comprising: a carrier substrate, the carrier substrate having a die side and a non-die side, the die side having a first area for electrically interconnecting a die to the die side of the carrier substrate, and a second area having land pads on the die side of the carrier substrate, the land pads having a predetermined pitch; a die coupled to the first area; and an intermediate substrate directly laminated to the die side of the carrier substrate, the intermediate substrate located outside the periphery of the first area and that does not encapsulate the die, the intermediate substrate having conductive risers disposed therein corresponding to the land pads, the conductive risers configured to cooperate with the corresponding land pads to provide a standoff distance sufficient to accommodate the die, and each of the conductive risers having a first end and a second end, the first end being electrically interconnected to the land pad.