Patent ID: 7397283

Claim:
A circuit comprising: a configurable receiver circuit comprising: a first input node; a second input node; a switchable first resistor coupled to the first input node; a switchable second resistor coupled to the second input node; a switchable self-biasing circuit coupled to the first input node and the second input node; a supply voltage coupled to the switchable first resistor and the switchable second resistor; an amplifier for generating an internal format signal; a multiplexer or demultiplexer coupled to the configurable receiver circuit for receiving the internal format signal; and a configurable driver circuit coupled to the multiplexer or demultiplexer for receiving the internal format signal, comprising: a first transistor and a second transistor in a differential pair configuration; a switchable first source termination resistor coupled to a first transistor drain at a first output node; a switchable second source termination resistor coupled to a second transistor drain at a second output node; and a current source coupled to a first transistor source and a second transistor source.