Patent ID: 8344786

Claim:
A semiconductor integrated circuit, comprising: a first IO cell region and a second IO cell region each including at least one IO cell into and from which a signal having amplitude of a first voltage is input and output; a level shift circuit region located so that the second IO cell region is interposed between the level shift circuit region and the first IO cell region, the level shift circuit region including a plurality of level shift circuits arranged in a double or higher multiple line, one of the plurality of level shift circuits being configured to convert a signal output from the IO cell of the first IO cell region into a signal having amplitude of a second voltage and output the signal having the amplitude of the second voltage; and an internal circuit configured to be operated using the signal having the amplitude of the second voltage output from the one of the plurality of level shift circuits, wherein a signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the one of the plurality of level shift circuits is provided between the cell of the first IO cell region and the one of the plurality of level shift circuits, extending over or in the IO cell of the second IO cell region.