Patent ID: 7312146

Claim:
A method of forming an IC structure on a semiconductor substrate, the method comprising: a) depositing a first Cu diffusion barrier layer on the substrate, wherein the first Cu diffusion barrier layer comprises an electrically conductive Cu diffusion barrier layer; b) depositing an electrically conductive Cu seed layer on the first Cu diffusion barrier layer, such that the first Cu diffusion barrier layer and the Cu seed layer form a sandwich layer; c) depositing a first sacrificial layer on the sandwich layer; d) selectively developing the first sacrificial layer to form a first cavity extending through the first sacrificial layer to the sandwich layer; e) depositing a first Cu layer in the first cavity wherein the first Cu layer includes an exposed first Cu top surface, and wherein the first Cu layer includes a horizontal interconnect f) depositing a second sacrificial layer on the first sacrificial layer and on the first Cu top surface; g) developing the second sacrificial layer to form a second cavity extending through the second sacrificial layer and exposing at least a portion of the first Cu top surface; h) selectively depositing a second Cu layer in the second cavity including the exposed portion of the first Cu top surface, wherein the second Cu layer includes an exposed second Cu top surface and a via; i) removing the first and second sacrificial layers thereby forming a first Cu component comprising (1) the first and second Cu layers, (2) the exposed second Cu top surface and (3) an exposed extended Cu surface that extends between the second Cu top surface and the sandwich layer, and (4) an inverted damascene structure.