Patent ID: 7451068

Claim:
A method for dissecting a layout of an integrated circuit based on modeled intensity gradients to produce a segmentation for an optical proximity correction (OPC) process, comprising: calibrating the association between gradients and segment lengths by: modeling an intensity gradient including angle and magnitude across a test pattern; identifying target regions in the test pattern that have a large amount of correction shift variation; mapping intensity gradients including angles and magnitudes to the target regions; associating segment lengths with the target regions; and producing an association between intensity gradients including angles and magnitudes and segment lengths in the target regions, whereby the association is subsequently used in generating the segmentation for the layout; receiving the layout for the integrated circuit; performing a model-based simulation on the layout to generate 2-D intensity gradients along edges of features in the layout, wherein the 2-D intensity gradients include both magnitude and angle of the intensity change, and wherein an intensity gradient angle can be in any direction with respect to an edge; and generating a segmentation for edges in the layout based upon the 2-D intensity gradients, wherein the segmentation is used by a subsequent OPC process in generating corrections for the layout; wherein the OPC corrected layout is used to generate a mask for fabricating an integrated circuit.