Patent ID: 6870264

Claim:
A multi-level circuit substrate comprising: upper and lower parallel non-aligned interconnect layers respectively extending inwardly horizontally from opposite sides of the substrate and having an end termination at a central location in the substrate; insulation provided between the two interconnect layers; at least two vertically aligned conductors each respectively extending perpendicularly from one of the interconnect layers through the insulation and each having an inner end centrally of the substrate; an intermediate connection layer in a horizontal plane sandwiched between and in contact with the inner ends of the aligned conductors so as to provide an electrical connection between the upper and lower non-aligned interconnect layers; a shield layer provided in approximately the same horizontal plane as the intermediate connection layer and surroundingly spaced from and around the intermediate connection layer; and wherein a condition of (R·r)/(2·h)≦L≦(5·R·r)/h is satisfied, provided that a connection distance between the interconnect layers through the aligned conductors and the intermediate connection layer is h, the aligned conductors are circular cylinders having a diameter R, the intermediate connection layer has a circular periphery portion having a diameter r, and a spaced distance between the intermediate connection layer and the shield layer is L.