Patent ID: 8294256

Claim:
A chip package structure, comprising: a) a chip having a plurality of first and second contact pads thereon; b) a lead frame having a plurality of pins for external connection to said package structure, wherein said chip is disposed on said lead frame; c) a plurality of first bonding wires being ground bonding wires configured to connect said first contact pads to said lead frame, wherein said first contact pads comprise ground pads for operation at substantially a same potential; and d) a plurality of second bonding wires configured to connect said second contact pads to said plurality of pins on said lead frame, wherein said second contact pads comprise switch pads for operation at variable potentials, and power pads for operation at substantially a same potential, wherein said plurality of second bonding wires comprise switch signal bonding wires and wherein said switch final bonding wires and said ground bonding wires are arranged on a first side of said lead frame, e) wherein bonding wires connected to said power pads on said chip comprise power bonding wires arranged on a second side of said lead frame, said second side being opposite to said first side on said lead frame.