Patent ID: 7838878

Claim:
A semiconductor structure comprising: a semiconductor substrate comprising a two-dimensional array of sub-mounts, the array comprising respective columns and rows of sub-mounts, wherein each sub-mount comprises: a die attach pad and first and second contact pads inside a recess defined in a front-side of the substrate, and feed-through metallization in via structures extending from a surface within the recess to a back-side surface of the substrate, wherein the feed-through metallization in at least one of the via structures electrically couples the first contact pad on the front-side surface of the substrate to a first SMD pad on the back-side surface of the substrate, and wherein the feed-through metallization in at least one other via structure electrically couples the second contact pad on the front-side surface of the substrate to a second SMD pad on the back-side surface of the substrate; first conductive lines on the front-side of the substrate, wherein each first conductive line forms part of an electrical path that electrically connects together the first contact pads in a respective column of sub-mounts; second conductive lines on the back-side of the substrate, wherein each second conductive line forms part of an electrical path that electrically connects together the second contact pads in a respective row of sub-mounts; and a plurality of probe pads each of which is electrically connected to a respective one of the first or second conductive lines.