Patent ID: 7821297

Claim:
A low power output driver comprising: (a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a continuously regulated reduced voltage that is a lower voltage than the supply voltage; (b) a first driver input that receives a first logic signal; (c) a second driver input that receives a second logic signal; (d) a first driver output that outputs a first output signal; (e) a second driver output that outputs a second output signal; (f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage V L and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input; (g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and a constant voltage internal ground, the gate of the second NMOS being electrically coupled to the second driver input; (h) a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the reduced voltage V L and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and (i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the constant voltage internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input, when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage V L , the second driver output is pulled down to the constant voltage internal ground, and current through the first NMOS and the fourth NMOS is reduced to zero, when the second driver input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage V L , the first driver output is pulled down to the constant voltage internal ground, and current through the second NMOS and the third NMOS is reduced to zero, and the constant voltage internal ground differentiates the driver output raised to the reduced voltage from the driver output pulled down to the constant voltage internal ground.