Patent ID: 6898682

Claim:
An on-chip controller for issuing a READ command and for receiving data in response thereto, the on-chip controller operating in a first timing domain and comprising: a data valid circuit, having a locked state and an unlocked state, operative to receive a data valid signal indicating that the data is valid, the data valid circuit operative to be initialized into the unlocked state and to transition to the locked state in response to the data valid signal; a latency counter circuit implemented as a shift register operative to count clock cycles by shifting a predetermined shift register bit corresponding to a READ command in response to a clock cycle and to be reset in response to the issuing of the READ command, the shift register receiving a first logic bit if a READ command is generated during the clock cycle and receiving a second logic bit if a READ command is not generated during the clock cycle; a locked latency value storage element that is operative to identify a selected bit of the shift register in accordance with a number of clock cycles associated with an expected READ latency; and a data sample circuit being operatively coupled to the data valid circuit and to the latency counter circuit, the data sample circuit being operative when the data valid circuit is in the locked state to sample the data in response to a determination that the latency counter circuit contains a value that compares favorably with a stored counter value, and being operative when the data valid circuit is in the unlocked state to sample data in response to the data valid signal.