Patent ID: 8487303

Claim:
A semiconductor memory device comprising: a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a memory unit comprising a first memory cell and a second memory cell, wherein the first to fourth wirings are parallel to one another, wherein the first wiring and the fifth wiring intersect with each other, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor, wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor, wherein a gate of the first transistor is connected to the first wiring, wherein the other electrode of the first capacitor is connected to the second wiring, wherein a gate of the third transistor is connected to the third wiring, wherein the other electrode of the second capacitor is connected to the fourth wiring, wherein a drain of the second transistor is connected to a source of the fourth transistor, wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor, wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.