Patent ID: 7750417

Claim:
A non-volatile semiconductor memory comprising memory cell transistors comprising: a first source and a first drain regions having a first conductivity type disposed on an insulating layer; a first channel region having the first conductivity type touched on the insulating layer and interposed between the first source and first drain regions; a floating gate electrode disposed above the first channel region and insulated from the first channel region; a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode, and an enhancement mode select gate transistor connected to the source region of one of the memory cell transistors at one end of an array of the memory cell transistors arranged in a column direction of a matrix, the enhancement mode select gate transistor comprising: a second source and a second drain regions having the first conductivity type disposed on the insulating layer; a second channel region having a second conductivity type between the second drain region and the second source region, and a select gate electrode disposed above the second channel region and insulated from the second channel region, wherein a part of the semiconductor substrate comprises a cell array convex portion which is same material as the semiconductor substrate contacts with a bottom of the first drain region or the second drain region through an opening disposed in the insulating layer.