Patent ID: 8331555

Claim:
An MD5 processing apparatus comprising a programmable device programmed to include: a plurality of processing engines, wherein each processing engine is configured to perform one stage of an MD5 process, wherein each MD5 process stage comprises four MD5 operations in a corresponding MD5 round, each processing engine comprising: a 32-bit A register; a 32-bit B register; a 32-bit C register; a 32-bit D register and first, second, third and fourth sub-stage units, each sub-stage unit being configured to perform a corresponding one of the four MD5 operations in the corresponding MD5 round and each sub-stage unit comprising: a first adder comprising a plurality of logic cells configured to modulo add an A register value and an MD5 pre-adder value, wherein the MD5 pre-adder value comprises the modulo sum of an MD5 message segment and an MD5 constant value; a fixed MD5 nonlinear function processing unit comprising a plurality of logic cells configured to perform a fixed nonlinear function on inputs comprising a B register value, a C register value and a D register value; a second adder comprising a plurality of logic cells configured to modulo add an output of the fixed MD5 nonlinear function processing unit and the first adder; a fixed 32-bit-shift unit comprising routing circuitry configured to effect a fixed bit shift on an output of the second adder; and a third adder comprising a plurality of logic cells configured to modulo add the B register value and an output of the fixed 32-bit-shift unit; and a generator coupled to each of the processing engines, the generator being configured to pre-calculate a plurality of MD5 pre-adder values including the MD5 pre-adder value concurrently with the performing of the stages of the MD5 process by the processing engines; wherein each stage of the MD5 process performs the four MD5 operations of the corresponding MD5 round via the corresponding sub-stage units for advancing register values in the A register, B register, C register and D register respectively from A n , B n , C n , D n to A n+4 , B n+4 , C n+4 , D n+4 , respectively, and wherein each of the processing engines is configured to perform four iterations of the corresponding stage of the MD5 process to complete the corresponding MD5 round before supplying a corresponding output value, wherein a first processing engine of the processing engines is configured to supply the corresponding output value to a second processing engine of the processing engines; and wherein the second processing engine is configured to output an MD5 digest value as the corresponding output value.