Patent ID: 6842394

Claim:
A semiconductor integrated circuit comprising: an address buffer; a decoder; an activation circuit; and a plurality of pre-charge circuits, wherein an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, wherein a circuit formed by integrating the address buffer with the decoder comprises switching circuits in n stages, stacked and connected with each other, each having a first node formed by connecting the drain of an input transistor to the gate of a reference transistor, a second node served by the drain of the reference transistor, and a third node formed by connecting the source of the input transistor to the source of the reference transistor, and wherein said switching circuits in the respective stages being formed in the number of 2 raised to the (n− 1 )-th power such that the third node of each of a plurality of the switching circuits, in a n-th stage (the topmost stage), is connected to the first node or the second node of the respective switching circuits in a (n− 1 )-th stage, one terminal of the activation circuit the other terminal of which is connected to a first power source potential is connected to the third node of one of the switching circuits in a first stage (the bottom stage), the first node and the second node of the respective switching circuits in the first to n-th stages, respectively, are connected to each of the pre-charge circuits for pre-charging said nodes to a second power source potential, and the gate of the input transistor of the respective switching circuits in the first to n-th stages, respectively, receives a first to n-th input signal, respectively, a control signal being delivered to said activation circuit and pre-charge circuits, respectively.