Patent ID: 8335911

Claim:
A microprocessor comprising: a front end pipeline comprising a first shared resource that includes a first plurality of entries, wherein the front end pipeline is configured to concurrently fetch and decode a first plurality of instructions; an execution pipeline comprising a second shared resource that includes a second plurality of entries, wherein the execution pipeline is configured to concurrently issue a second plurality of instructions to a plurality of execution units, the second plurality of instructions corresponding to a plurality of threads; and a commit pipeline comprising a third shared resource that includes a third plurality of entries, wherein the commit pipeline is configured to commit results of a third plurality of instructions corresponding to the plurality of threads to architectural state; wherein one or more entries of each of the first, second, and third shared resources may be allocated for use by any of the plurality of threads each clock cycle; wherein the microprocessor further comprises control circuitry configured to allow each active thread of the plurality of threads to allocate at least a predetermined quota of entries of each of the first, second, and third shared resources.