Patent ID: 7566924

Claim:
A semiconductor device comprising: a gate on a substrate, the gate comprising a gate electrode material and a gate capping layer over the gate electrode material; a gate insulation layer, formed between the gate and the substrate; and a gate spacer on a sidewall of the gate, the gate spacer comprising: a second insulation layer, wherein an edge of the second insulation layer has a slope that continuously increases from a top surface of the gate to a level below the top surface of the gate; and a first insulation layer below the second insulation layer, wherein an edge of the first insulation layer extends from the level below the top surface of the gate to the gate insulation layer and has a slope that is positive with respect the slope of the edge of the second insulation layer such that the slope of the edge of the first insulation layer is less than the slope of the edge of a portion of the second insulation layer immediately above the level below the top surface of the gate, wherein a thickness of the first insulation layer at the level below the top surface of the gate is less than a thickness of the second insulation layer at the level below the top surface of the gate.