Patent ID: 6969685

Claim:
In a plasma processing reactor, a method of etching an integrated circuit (IC) from a substrate, said substrate including a patterned metal hard mask layer, at least one intermediate layer disposed below said patterned hard mask layer, and a dielectric layer disposed below said at least one intermediate layer, comprising: selectively etching said patterned metal hard mask layer using a first plasma, said first plasma being generated from a first feed gas mixture that contains oxygen (O 2 ); selectively etching said at least one intermediate layer using a second plasma, said second plasma being generated from a second feed gas mixture that does not contain said oxygen (O 2 ); and selectively etching said dielectric layer using a third plasma, said third plasma being generated from a third feed gas mixture that also does not contain said oxygen (O 2 ), wherein substantially all plasma generated from said oxygen of said first gas mixture is removed from said plasma processing reactor during said selectively etching said at least one intermediate layer and prior to said selectively etching said dielectric layer, and wherein said selectively etching said patterned metal hard mask layer is performed prior to said selectively etching said at least one intermediate layer, and said selectively etching said at least one intermediate layer is performed prior to said selectively etching said dielectric layer, and wherein said selectively etching said patterned metal hard mask layer, said selectively etching said at least one intermediate layer, and said selectively etching said dielectric layer are performed in said plasma processing reactor while said substrate is disposed in said plasma processing reactor.