Patent ID: 7586782

Claim:
A semiconductor device comprising: first and second word lines; first and second source lines; first and second bit lines each crossing the first word line, the second word line, the first source line, and the second source line; a first memory cell including a first MISFET having a gate connected with the first word line and having a source and a drain, one of the source and the drain of the first MISFET being connected with the first bit line, and a first variable resistor element, one side of the first variable resistor element being connected with the other of the source and the drain of the first MISFET and another side of the first variable resistor element being connected with the first source line; a second memory cell including a second MISFET having a gate connected with the first word line and having a source and a drain, one of the source and the drain of the second MISFET being connected with the second bit line, and a second variable resistor element, one side of the second variable resistor element being connected with the other of the source and the drain of the second MISFET and another side of the second variable resistor element being connected with the first source line; a third memory cell including a third MISFET having a gate connected with the second word line and having a source and a drain, one of the source and the drain of the third MISFET being connected with the first bit line, and a third variable resistor element, one side of the third variable resistor element being connected with the other of the source and the drain of the third MISFET and another side of the third variable resistor element being connected with the second source line; a fourth memory cell including a fourth MISFET having a gate connected with the second word line and having a source and a drain, one of the source and the drain of the fourth MISFET being connected with the second bit line, and a fourth variable resistor element, one side of the fourth variable resistor element being connected with the other of the source and the drain of the fourth MISFET and another side of the fourth variable resistor element being connected with the second source line; a first substrate node connected with the source and the drain of the first MISFET and the source and the drain of the third MISFET; and a second substrate node connected with the source and the drain of the second MISFET and the source and the drain of the fourth MISFET, wherein a current flows between the first substrate node and the first source line via the first variable resistor element when data is written into the first memory cell, and wherein a first voltage is supplied to the first substrate node, and then a second voltage lower than the first voltage or a third voltage lower than the second voltage is supplied to the first source line, and then the second voltage or the third voltage is supplied to the second source line when data is written into the first memory cell and then data is written into the third memory cell.