Patent ID: 7569927

Claim:
A power transistor package comprising: a rectangular ceramic base; one or more die affixed to an upper surface of the ceramic base; one or more source leads extending from at least one of a pair of opposite sides of the ceramic base; one or more gate and drain leads extending from at least one of a pair of opposite sides of the ceramic base; and a rectangular non-conductive unitary resilient cover overlying the ceramic base and including: a recess configured to receive the ceramic base and including a cavity to receive the one or more die, gate and drain leads and a portion of the source leads, the recess shaped to engage and press an outer periphery of the ceramic base against a heat sink; a rectangular marginal frame spaced outward from the recess to form a bottom surface along an outer edge of the non-conductive cover, the bottom surface of the marginal frame being parallel to and above an upper surface of the heat sink; four bolt holes for mounting bolts, each bolt hole arranged in one of four corners of the rectangular marginal frame to secure the ceramic base and source leads to the heat sink; and four separate bosses, each boss protruding from the bottom surface of one of the four corners of the rectangular marginal frame corresponding to each bolt hole and arranged outward of each of the bolt holes toward an outer edge of the cover to form a second bottom surface offsetting from the bottom surface of the marginal frame in a stair-stepped arrangement facing the heat sink and to serve as a pivot adjacent an outer periphery of the bottom surface of the rectangular marginal frame at each corner thereof, so that the rectangular non-conductive unitary resilient cover exerts a downward bending moment toward the heat sink inward of the mounting bolts for securing the non-conductive cover to the ceramic base.