Patent ID: 8035135

Claim:
A semiconductor memory device, comprising: a memory cell array region in which memory cells are formed in a repetitive pattern on a semiconductor substrate of the semiconductor memory device, wherein wirings in a predetermined layer formed on said memory cell array region are vertically and horizontally arranged in a form of a grid to correspond to the arrangement of said memory cells at least in said memory cell array region; wherein each wiring in a horizontal direction of said wirings has a wiring width equal to a length of M cells, each wiring in a vertical direction of said wirings has a wiring width equal to a length of N cells, a distance in a horizontal direction between two of said wirings adjacent to each other is equal to a length of M cells, and a distance in a vertical direction between two of said wirings adjacent to each other is equal to a length of N cells, provided that M and N are natural numbers, respectively.