Patent ID: 7509486

Claim:
A server, comprising: a system memory; and a processing unit coupled to said system memory via a system bus, said processing unit including: an execution unit, coupled to a decode unit, configured to execute arithmetic instructions to perform product and square operations, said execution unit including at least two multipliers connected directly with said system memory for multiplying data provided from said system memory, and at least one adder connected directly with said at least two multipliers for applying an addition operation to outputs of said at least two multipliers, said execution unit configurable to perform specified multiplication operations and specified multiplication and addition operations simultaneously relative to a clock cycle; and said decode unit being configured to determine if a square operation or a product operation needs to be performed on an operand, said decode unit being further configured to issue said arithmetic instructions to said execution unit so that said execution unit performs specified multiplication and addition operations and specified multiplication operations simultaneously relative to said clock cycle while performing either said square or product operation.