Patent ID: 6873181

Claim:
A method of incorporating non-arithmetic logic into arithmetic logic feeding the non-arithmetic logic including: identifying a programmable logic element performing an arithmetic logic function Fn the programmable logic element having a plurality of LE inputs and at least a first logical AND gate, the inputs of the first logical AND gate connected to at least two of the plurality of LE inputs, the programmable logic element further driven by at least one LE signal and driving an output signal Sn, the output signal Sn driving a fan-out free non-arithmetic logic block, the non-arithmetic logic block driven by a plurality of block signals including at least a block signal c and at least one further block signal such that; when c is asserted a function Gn of the non-arithmetic logic block generates output signal Sn; when c is not asserted, the Gn is not a function of Sn; and the number of LE signals driving the programmable logic operator plus the number of block signals driving the non-arithmetic logic block minus 1 is less than or equal to the number of LE inputs; rerouting the at least one further block signal and the block signal c to drive the programmable logic element, and reprogramming the function Fn of the programmable logic element to carry out the function Fn′ such that when c is asserted Fn′ is equal to Fn and when c is not asserted Fn′ is equal to Gn with Sn de-asserted.