Patent ID: 7421254

Claim:
A method for calibrating a power amplifier that services a communications transceiver, the method comprising: producing a test signal to test the power amplifier, wherein the power amplifier has a primary transconductance stage, a secondary transconductance stage, a cascode stage and an inductive load, in which a primary bias setting is coupled to the primary transconductance stage and a secondary bias setting is coupled to the secondary transconductance stage; applying the test signal to calibrate the bias settings by: (i) applying a first bias voltage to a gate of a metal oxide silicon transistor of the cascode stage and applying a second bias voltage to a base of a parasitic bipolar transistor formed in parallel with the metal oxide silicon transistor; (ii) applying a respective bias setting to the primary and secondary transconductance stages of the power amplifier; (iii) applying the test signal to the power amplifier to produce an amplified test signal; (iv) coupling back a portion of the amplified test signal to a receiver section of the communications transceiver; (v) producing a characterization of the amplified test signal, wherein the characterization indicates at least one of an error vector magnitude, intermodulation product magnitude, or 1 dB compression point of the amplified test signal; (vi) repeating (i) through (v) for respective set of bias settings, until a plurality of bias settings have been tested; and determining power amplifier bias control settings to operate the power amplifier, based upon the plurality of characterizations of the amplified test signal and the respective set of bias settings, so that the power amplifier has its response linearized to minimize error vector magnitude and intermodulation product magnitude; and applying the power amplifier bias control settings to the power amplifier.