Patent ID: 8451024

Claim:
A non-CMOS electronic circuit for driving a memory array, the non-CMOS electronic circuit comprising: a bipolar transistor; a MOS transistor functionally connected to a base of the bipolar transistor; a capacitor functionally connected to the MOS transistor and the base of the bipolar transistor; and a plurality of additional MOS transistors, at least one of which is electrically connected to at least one of the bipolar transistor or the MOS transistor, wherein (i) current flows through an emitter-base junction of the bipolar transistor only after a voltage on a gate of the MOS transistor is applied and until the capacitor is fully charged, and (ii) a type of the MOS transistor and each of the plurality of additional MOS transistors is the same, the type being selected from the group consisting of NMOS and PMOS.