Patent ID: 8913404

Claim:
A constant voltage/constant current (CVCC) control circuit for load regulation for a flyback switch mode power supply (SMPS), the CVCC comprising: a) a voltage feedback circuit configured to generate an output voltage feedback signal; b) a current feedback circuit configured to generate an output current feedback signal; c) a control signal generating circuit configured to receive said output voltage feedback signal and said output current feedback signal, and to generate a CVCC control signal; d) a first enable signal generating circuit configured to compare a first reference voltage and said CVCC control signal to generate a first enable signal; e) said control signal generating circuit comprising a current controller configured to calculate a difference between said output current feedback signal and a reference current to generate an error signal, a voltage controller configured to compare said output voltage feedback signal against a second reference voltage to generate a first control signal, and a select controller configured to control whether said flyback SMPS operates in a constant voltage mode or a constant current mode based on said first control signal and said error signal; f) said select controller comprising an OR-gate configured to receive said first control signal and said first enable signal, a first switch configured to receive said error signal and having a control terminal coupled to said OR-gate, a second switch coupled to said first switch and a discharge circuit and being configured to turn on when said first enable signal and said first control signal are inactive, and a capacitor coupled to ground and a common node of said first and second switches, wherein a voltage across said capacitor is configured as said CVCC control signal; and g) a pulse-width modulation (PWM) controller configured to generate a PWM control signal based on said CVCC control signal to control a main switch of said flyback SMPS, wherein said PWM control signal is configured to turn on said main switch when said first enable signal is inactive, and wherein said main switch remains off when said first enable signal is active.