Patent ID: 8391063

Claim:
A method of operating a memory cell, wherein the memory cell comprises a substrate having a protruding part, a top bit line located in a top portion of the protruding part, a first bottom bit line and a second bottom bit line located in the substrate respectively beside the protruding part, a word line located on the substrate and crossing over the first and second bottom bit lines, and a charge-storage layer located between the word line and the substrate, and wherein the memory cell has a first storage region, a second storage region, a third storage region and a fourth storage region located in the charge-storage layer, the first storage region and the second storage region are respectively adjacent to a lower portion and an upper portion of the protruding part at a side of the first bottom bit line, the third storage region and the fourth storage region are respectively adjacent to a lower portion and an upper portion of the protruding part at a side of the second bottom bit line, and the second storage region and the third storage region are regarded as a top storage region, the method comprising programming the top storage region of the memory cell, comprising: applying a first positive voltage to the word line; applying a second positive voltage to the top bit line; and respectively applied a bottom voltage to the first and second bottom bit lines; and the method comprising programming the first storage region of the memory cell, comprising: applying a third positive voltage to the word line; applying a top voltage to the top bit line; and applying a fourth positive voltage to the first bottom bit line.