Patent ID: 6954506

Claim:
A circuit for recovering a clock signal in a USB (universal serial bus) receiver, the circuit comprising: a phase detector for detecting a phase difference between data received from a USB transmitter and a recovery clock signal and generating a first control signal indicative of a detected phase difference; a bidirectional shift register for outputting a second control signal in response to the first control signal; a multiphase clock signal generator for processing a receiver clock signal of the USB receiver, wherein the receiver clock signal is the same as a transmitter clock signal of the USB transmitter, to generate a plurality of phase clock signals each having the same frequency as the receiver clock signal and a different phase offset from the phase of the receiver clock signal; and a phase selector responsive to the second control signal for selecting one of the plurality of phase clock signals and outputting the selected phase clock signal as a recovery clock signal, wherein the plurality of phase clock signals comprise first through N-th phase clock signals, wherein the different phase offsets of the first through N-th phase clock signals are about (360/N)I degrees, where N is an integer, and I is an integer equal to or greater than 0 and equal to or less than N−1.