Patent ID: 6985129

Claim:
A display device in which a display signal externally transferred in sequence is sampled based on an external clock signal and is supplied to each of pixels arranged in a matrix for causing each pixel to perform display, said display device comprising: a sampling signal generating circuit for generating a sampling signal used for sampling said display signal, based on said external clock signal; and at least one clock delaying circuit disposed between said sampling signal generating circuit and a terminal for supplying said external clock signal and having a function of delaying said external clock signal, wherein said at least one clock delaying circuit is connected to a signal transmission line for supplying said external clock signal to said sampling signal generating circuit, said signal transmission line and a connection line connecting to said signal transmission line being formed using a pattern mask in accordance with the required number of connections for the delaying circuit in the process for forming said signal transmission line and said connection line, wherein said clock delaying circuit is a inverter circuit formed by an n-type thin film transistor and a p-type thin film transistor which are connected in a complementary manner, and said n-type thin transistor and said p-type thin film transistor forming one inverter circuit are arranged such that active layers of said n-type and p-type transistor are spaced with an interval which is larger than the width of said signal transmission line.