Patent ID: 7671690

Claim:
A signal control system having a signal output, the signal control system comprising: a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector; at least one automatic level controller (ALC) coupled to the oscillating output of the PLL; a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC, wherein each of the switchable integrators is switchable between 1) a narrow bandwidth mode that provides for stable operation of the signal control system, and 2) a wide bandwidth mode that enables fast signal transitions at the signal output; and a controller configured to, in response to a signal transition request, i) open the PLL, ii) switch the switchable integrators from their narrow bandwidth modes to their wide bandwidth modes, iii) drive the VCO with a pre-tune voltage for a first predetermined time, and iv) program the frequency divider; and after driving the VCO with the pre-tune voltage for the first predetermined time, close the PLL and switch the first and second switchable integrators to their narrow bandwidth modes.