Patent ID: 7233032

Claim:
A static random access memory (SRAM) device, comprising: a substrate having an n-doped region interposing first and second p-doped regions; and an SRAM unit cell including: a first pass-gate transistor and a first pull-down transistor located at least partially over the first p-doped region; first and second pull-up transistors located at least partially over the n-doped region; a second pass-gate transistor, a second pull-down transistor, and first and second read port transistors, all located at least partially over the second p-doped region; a first transistor active region implanted in the first p-doped region and extending between source/drain contacts of the first pass-gate transistor and the first pull-down transistor; and a second transistor active region implanted in the second p-doped region and extending between source/drain contacts of the second pass-gate transistor and the second pull-down transistor.