Patent ID: 6957319

Claim:
An integrated circuit, comprising: a microcode unit configured to receive a microcoded instruction and, in response, to identify one of a plurality of microcode routines corresponding to the microcoded instruction; and a plurality of microcode ROMs fabricated within the same integrated circuit, coupled to the microcode unit and configured to collectively store the plurality of microcode routines, wherein at least one of the plurality of microcode ROMs is configured to output operations included in the microcode routine in response to the microcode unit identifying the microcode routine; wherein each of the plurality of microcode ROMs is independently accessible; wherein at least one of the plurality of microcode ROMs has a different access time than at least another one of the plurality of microcode ROMs; and wherein the plurality of microcode routines are stored in the plurality of microcode ROMs such that microcode routines having more performance criticality are stored in one of the plurality of microcode ROMs having a smaller access time than another one of the plurality of microcode ROMs in which microcode routines having less performance criticality are stored.