Patent ID: 7662689

Claim:
A method comprising: forming a selective first layer suitable as a first channel for a first circuit device on a first area of a substrate but not on a different second area of the substrate, the first layer comprising a selectively grown first material having a first lattice spacing different than a substrate lattice spacing of a substrate material defining a first interface surface of the substrate prior to doping the first layer or the substrate, wherein the first lattice spacing is in two dimensional coherent alignment with the substrate lattice spacing at the first interface surface; forming a dielectric layer on the selective first layer; then forming a selective second layer suitable as a second channel for a second circuit device on the different second area of the substrate but not on the dielectric layer, the second layer comprising a selectively grown different second material having a second lattice spacing different than first lattice spacing prior to doping the first layer or the second layer, and different that the substrate lattice spacing of the substrate material defining a second interface surface of the substrate prior to doping the second layer or the substrate, wherein the second lattice spacing is in two dimensional coherent alignment with the substrate lattice spacing at the second interface surface; forming a gate dielectric layer on a surface of the first layer and the second layer; and forming a gate electrode on the gate dielectric layer; wherein the substrate material comprises Si 1-X Ge X , the first material comprises Silicon, and X is between 0.1 and 0.3 to cause a bi-axial coherent tensile strain in the first layer sufficient to increase electron carrier mobility by at least 50 percent; and wherein the second material comprises Si 1-Y Ge Y , X<Y, and Y is between 0.2 and 0.6 to cause a bi-axial coherent compressive strain in the second layer sufficient to increase hole carrier mobility by at least 50 percent.