Patent ID: 7844650

Claim:
A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency f ref , the clock signal generator generating an output clock signal having a frequency f gen , wherein f gen is less than f ref , the clock signal generator comprising: (a) a modulo-N counter which accepts the reference clock signal as input, said modulo-N counter generating a phase-indication signal of the reference clock, wherein said phase indication signal has N clock phases repeating at a frequency of f ref /N; (b) an accumulator which by iteratively accumulating a frequency control word into a modulo-N adder, produces an accumulated value, wherein at least one bit of said accumulated value is fed-back into said modulo-N adder for adding modulo N to said accumulated value in the next iteration; wherein N of said modulo-N adder is the same integer as in said modulo-N counter; and (c) a clock edge selector which receives as inputs said phase indication signal and at least one bit of said accumulated value and by comparing said inputs selects an edge of the reference clock signal upon which to toggle the state of the output clock signal.