Patent ID: 8099539

Claim:
A method, comprising: controlling a set of multiplexers having a capability to multiplex data and an address from a System-on-a-Chip (SoC), a host device and a memory device through an arbiter circuit configured to perform arbitration per transaction, the host device being external to the SoC; selecting one of a memory clock and a host clock based on a status of the arbitration, the host clock being associated with the host device and the memory clock being associated with communication between the SoC and the host device; driving a final output on an interface associated with access of at least one of the SoC, the memory device and another SoC through the selected clock to provide glitchless switching of an interface signal coupled to a tri-state buffer; and setting a direction of a data and an address bus associated with the access through the tri-state buffer, wherein the arbitration is avoided at a command boundary of the memory device and done at an intermediate phase of an address, a command, a read data, and a write data associated therewith if a command time associated with the memory device exceeds a threshold.