Patent ID: 7247909

Claim:
A method for integrally forming at least one first device operating at a first voltage and at least one second device operating at a second voltage higher than the first voltage, the method comprising: forming a first gate structure and a second gate structure on a semiconductor substrate, the first and second gate structures being isolated from one another; forming one or more first spacers on sidewalls of the first gate structure and one or more second spacers on sidewalls of the second gate structure; forming one or more first double diffused regions adjacent to the first gate structure in the semiconductor substrate, and one or more second double diffused regions adjacent to the second gate structure in the semiconductor substrate; and forming one or more first source/drain regions within the first double diffused regions and one or more second source/drain regions within the second double diffused regions, wherein a junction depth of the first and second double diffused regions is deeper by 0.2 to 0.5 μm than a junction depth of the first and second source/drain regions, wherein the first double diffused regions function as one or more lightly doped source/drain regions for the first device, and the second double diffused regions function as one or more lightly doped source/drain regions for the second device, and wherein the first source/drain region has an inner boundary line substantially aligning with an outer surface of the first spacer and the second source/drain region has an inner boundary line distant from an outer surface of the second spacer such that the hot carrier effect caused by the second voltage higher than the first voltage is reduced.