Patent ID: 7705670

Claim:
A programmable gain amplifier, comprising, a first gain stage comprising, a first variable capacitor coupled to a first input signal; a second variable capacitor coupled to a second input signal; a first operational amplifier having a first input node linked to the first variable capacitor and a second input node linked to the second variable capacitor, for amplifying the first input signal and the second input signal as a first intermediate signal and a second intermediate signal, and outputting the first intermediate signal and the second intermediate signal to a first output node and a second output node, respectively; a first fixed capacitor linked to the first variable capacitor and the first output node; a first switch linked to the first variable capacitor and the first output node; a second fixed capacitor linked to the second variable capacitor and the second output node; and a second switch linked to the second variable capacitor and the second output node; and a second gain stage comprising, a third variable capacitor coupled to the first output node; a fourth variable capacitor coupled to the second output node; a second operational amplifier having a third input node linked to the third variable capacitor and a fourth input node linked to the fourth variable capacitor, for amplifying the first intermediate signal and the second intermediate signal as a first output signal and a second output signal, and outputting the first output signal and the second output signal to a third output node and a fourth output node, respectively; a third operational amplifier having a fifth input node linked to the third variable capacitor and a sixth input node linked to the fourth variable capacitor, amplifying the first intermediate signal and the second intermediate signal as a third output signal and a fourth output signal, and outputting the third output signal and the fourth output signal to a third output node and a fourth output node, respectively; a third fixed capacitor linked to the third variable capacitor and the third output node; and a fourth fixed capacitor linked to the fourth variable capacitor and the fourth output node.