Patent ID: 8050125

Claim:
A semiconductor memory device with an open bit line structure including bit line sense amplifiers, the semiconductor memory device comprising: a plurality of memory cell regions arranged in a matrix form along a row direction and a column direction; a plurality of bit line sense amplifier regions arranged in a matrix form, each of the plurality of bit line sense amplifier regions disposed between two adjacent memory cell regions in the row direction and including a plurality of sense amplifier blocks, each of the plurality of sense amplifier blocks including a first sense amplifying part and a second sense amplifying part and configured to sense and to amplify a signal difference between a bit line and a complementary bit line, each of the plurality of bit line sense amplifier regions including first voltage drivers to apply a power source voltage to the first sense amplifying parts; and a plurality of conjunction regions arranged in a matrix form, each of the plurality of conjunction regions disposed between two adjacent bit line sense amplifier regions in the column direction and including a control circuit to control the sense amplifier blocks, the plurality of conjunction regions including second voltage drivers to apply a ground voltage to the second sense amplifying parts, wherein the second voltage drivers are disposed for every two or more conjunction regions in the column direction.