Patent ID: 8644713

Claim:
A burst mode clock and data recovery (CDR) module for asynchronous, bursty, framed or continuous data transmission, the burst mode CDR module comprising: a data input port for receiving an incoming data transmission; a data splitter coupled to the data input port for splitting the incoming data transmission; a clock extraction module coupled to the data splitter, for receiving a clock signal from the incoming data transmission and producing a recovered clock when data is present at the data input port; a local clock of approximately a same frequency as the recovered clock; and a clock combining module coupled to the clock extraction module and the local clock; a synthesized clock coupled to the clock combining module, where the synthesized clock is produced from (i) the recovered clock; (ii) the local clock; or (iii) the product of combining the recovered clock and the local clock; a clock output port coupled to the clock combining module for output of the synthesized clock; a data retiming module coupled to the data splitter for receiving the incoming data transmission and the synthesized clock and retiming the incoming data transmission with the synthesized clock to produce an output data signal that is aligned with the synthesized clock; and a data output port coupled to the data retiming module for output of the output data signal.