Patent ID: 7293159

Claim:
A method comprising operating a general purpose processor (GPP) coupled via a port of the GPP to an application specific data path of an application specific instruction set processor (ASIP), the step of operating taking place in-between execution pipelines of the GPP and ASIP processors, and the step of operating comprising the steps of: an instruction unit of the GPP reading an instruction; employing a special interface of the GPP to determine if said instruction is a reserved instruction or a regular GPP instruction for execution on the GPP; if said instruction is a reserved instruction, conveying the reserved instruction read by the GPP to a pre-decoder of said ASIP via said GPP port, said reserved instruction being an instruction read from an instruction stream of the GPP; depending on said reserved instruction and corresponding to encoded source operands of said reserved instruction, reading the GPP General Purpose Register File and conveying read register values to the ASIP via said GPP port; in said pre-decoder, translating said received GPP reserved instruction to a form compatible with an instruction set architecture (ISA) of said ASIP; providing to the ASIP registers or memory any register values provided by the GPP; executing in said ASIP at least one ASIP compatible instruction resulting from said step of translating; conveying result control flags and result data values of said execution step to said GPP; said GPP storing the result data values into a GPP register file, and storing the result control flags into a condition register file; triggering the instruction unit upon the GPP receiving the result data values and result control flags from the ASIP on said port; and the instruction unit of said GPP continuing with the next instruction.