Patent ID: 7203118

Claim:
A semiconductor storage device having a memory cell array ( 21 ), which employs a memory element constructed of a gate electrode ( 1104 ) formed on a semiconductor layer ( 1102 ) via a gate insulation film ( 1103 ), a channel region ( 1121 ) arranged under the gate electrode ( 1104 ), diffusion regions ( 1107 a , 1107 b ) that are arranged on both sides of the channel region ( 1121 ) and have a conductive type opposite to that of the channel region ( 1121 ), and memory function bodies ( 1105 a , 1105 b ) that are formed on both sides of the gate electrode ( 1104 ) and have a function to retain electric charges, as a memory cell, the semiconductor storage device comprising: a first switch (SW 1 ) that has an input terminal to which an input voltage supplied from outside to the memory cell array is applied and has an output terminal connected to an input terminal of the memory cell array; a second switch (SW 2 ) that has an input terminal to which the input voltage is applied; a charge pump ( 23 ) that has a pump input terminal connected to an output terminal of the second switch (SW 2 ); a third switch (SW 3 ) that has an input terminal connected to a pump output terminal of the charge pump ( 23 ) and has an output terminal connected to the input terminal of the memory cell array ( 21 ); an input voltage determining circuit ( 24 ) that determines whether or not the input voltage is not higher than a prescribed voltage; and a control circuit ( 25 ) that turns on the first switch (SW 1 ) and turns off the second and third switches (SW 2 , SW 3 ) when the input voltage determining circuit ( 24 ) determines that the input voltage exceeds the prescribed voltage and turns off the first switch (SW 1 ) and turns on the second and third switches (SW 2 , SW 3 ) when the input voltage determining circuit determines that the input voltage is not higher than the prescribed voltage.