Patent ID: 6975544

Claim:
A method of controlling threshold voltage characteristics of a floating-gate field-effect transistor (“FET”) in which a pair of source/drain regions are separated from each other by a channel portion of a body region that forms a pn junction with each source/drain region, a floating-gate electrode overlies the channel portion, and a control-gate electrode overlies the floating-gate electrode above the channel portion, the FET being in a first condition when its programmable threshold voltage is (a) less than a first transition value V T1 if the FET is of n-channel type and (b) greater than −V T1 if the FET is of p-channel type, the FET being in a second condition when its programmable threshold voltage is (a) greater than a second transition value V T2 if the FET is of n-channel type and (b) less than −V T2 if the FET is of p-channel type where V T2 exceeds or equals V T1 , a first body voltage at a body node being converted into a second body voltage applied to the body region, a first control voltage at a control node being converted into a second control voltage applied to the control-gate electrode, the method comprising: placing the first body and first control voltages at respective body and control conditioning values different from each other such that the second body and second control voltages cause the FET to be in the first condition with its programmable threshold voltage (a) less V T1 than if the FET is of n-channel type or (b) greater than −V T1 if the FET is of p-channel type regardless of whether the FET was immediately previously in the first or second condition; and subsequently discharging the first body and first control voltages to respective body and control discharge values between the conditioning values, the body and control nodes being electrically connected to each other at least as the discharging act starts such that the first body and first control voltages begin to discharge largely simultaneously.