Patent ID: 7873813

Claim:
A computer system with a processing unit and a memory, the processing unit being arranged to fetch memory lines from the memory and execute instructions from the memory lines, each memory line being fetched as a whole and being capable of holding more than one instruction, at least one instruction from the memory lines comprising information, inserted at compile time, that signals explicitly how the processing unit, when processing the instruction from a current memory line, should control how a part of processing is affected by crossing of a boundary to a subsequent memory line, the processing unit being arranged to respond to the information by controlling said part of processing as signaled by the information, said information including at least a fetch bit and a realign bit, wherein the fetch bit signals explicitly whether or not the subsequent memory line has to be fetched during processing of the instruction, the processing unit being arranged to start fetching of the subsequent memory line in response to the explicit signaling by the fetch bit, and wherein the realign bit signals explicitly whether or not an instruction pointer should be updated from a position behind the instruction in the current memory line to a start of the subsequent memory line, so that information following the instruction on the current memory line is skipped over, the processing unit being arranged to update the instruction pointer to the start of the subsequent memory line in response to the explicit signaling by the realign bit.