Patent ID: 6962868

Claim:
A method of connecting wiring of a semiconductor integrated circuit device, said semiconductor integrated circuit device comprising first and second I/O slots arranged on a same wiring level in parallel along a peripheral portion of a chip within an inner region of the chip, a first pad arranged on a wiring level different from the first I/O slot and arranged above the first I/O slot, a second pad arranged on a wiring level different from the first I/O slot and arranged apart from the peripheral portion of the chip as compared with the first pad, a first wiring arranged in the inner region, which comprises a first end positioned at the first pad and a second end positioned at the peripheral portion above the first I/O slot, second wiring arranged in the inner region, which comprises a third end positioned at the second pad and a fourth end positioned at the peripheral portion above the second I/O slot, and a third wiring arranged in an outermost peripheral region of the chip, said method comprising: connecting the first pad to the first end in the inner region; connecting the second pad to the third end in the inner region; and connecting the second end to an I/O slot different from the first I/O slot via the third wiring in the outermost peripheral region.