Patent ID: 8569171

Claim:
A method comprising: forming a transistor on a substrate, the transistor having a gate electrode and source/drain regions; forming a masking layer over the substrate, the masking layer having openings exposing portions of the gate electrode and portions of the source/drain regions; depositing a metal in the openings on the exposed portions of the gate electrode and source/drain regions; forming metal silicide on the exposed portions of the gate electrode and source/drain regions; and removing unreacted metal and completely removing the masking layer, wherein the masking layer is formed by: forming an inter level dielectric (ILD) on the substrate, the ILD covering the transistor and having a substantially planar upper surface above an upper surface of the gate electrode; forming a lithographic mask on the ILD, the lithographic mask having openings corresponding to the exposed portions of the gate electrode and the source/drain regions; forming trenches in the ILD through the lithographic mask corresponding to the openings; and removing the lithographic mask.