Patent ID: 7279701

Claim:
A semiconductor device comprising: a semiconductor substrate; and at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising spaced apart source and drain regions on said semiconductor substrate, a superlattice comprising a plurality of stacked groups of layers on said semiconductor substrate between said source and drain regions, said superlattice having upper portions extending above adjacent upper portions of said source and drain regions and lower portions contacting said source and drain regions so that a channel is defined in lower portions of said superlattice, each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, said at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and a gate overlying said superlattice.