Patent ID: 7989847

Claim:
A layout of an integrated circuit device, comprising: a diffusion level layout portion including a number of diffusion region layout shapes to be formed within a portion of a substrate, wherein the number of diffusion region layout shapes include a diffusion region layout shape of a first diffusion type and a diffusion region layout shape of a second diffusion type separated by a central inactive region; a gate electrode level layout portion defined to pattern conductive features within a gate electrode level over the portion of the substrate corresponding to the diffusion level layout portion, the gate electrode level layout portion including a plurality of linear-shaped layout features placed to extend lengthwise in a first direction so as to extend parallel to each other, wherein the plurality of linear-shaped layout features includes a first linear-shaped layout feature having a first portion that extends over the diffusion region layout shape of the first diffusion type to form a gate electrode of a first transistor of a first transistor type, the first linear-shaped layout feature also having a second portion that extends over the central inactive region, and wherein the plurality of linear-shaped layout features includes a second linear-shaped layout feature having a first portion that extends over the diffusion region layout shape of the second diffusion type to form a gate electrode of a first transistor of a second transistor type, the second linear-shaped layout feature also having a second portion that extends over the central inactive region, and wherein a length of the second portion of the first linear-shaped layout feature is different than a length of the second portion of the second linear-shaped layout feature.