Patent ID: 8190802

Claim:
A circuit for performing arbitration when accessing a bus, comprising a logic gate arrangement ( 406 ) having a first input, a second input and an output, and configured to have a coupling from a first bus line to said first input, characterized in that: the circuit comprises a switching arrangement ( 404 , 405 , 407 , 901 ) configured to respond to a control signal by disconnecting a first half ( 402 ) of the first bus line from a second half ( 403 ) of the first bus line and coupling said second half ( 403 ) to a first fixed potential, said first half ( 402 ) being the one coupled to the first input of the logic gate arrangement ( 406 ), decoupling a second bus line ( 401 ) from the second input of said logic gate arrangement ( 406 ) and allowing the potential of said second input to become essentially equal with a second fixed potential, and coupling said second bus line to said first fixed potential; and two sources are available for providing the control signal to the switching arrangement ( 404 , 405 , 407 , 901 ), and one of said two sources is the output of the logic gate arrangement ( 406 ).