Patent ID: 8923141

Claim:
An apparatus for providing clock synchronization in a packet-based network having as components nodes and links therebetween and having a network topology, wherein the apparatus comprises: one or more processors; and a network interface communicatively coupled to the one or more processors and configured to communicate one or more packet flows among the one or more processors in a network; and logic coupled to the one or more processors and when executed operable to compute, from the network topology, a reciprocal clock synchronization packet path from a server to a synchronization destination according to a computation rule such that a return path of the reciprocal clock synchronization packet path from the synchronization destination is the same as a forward path of the reciprocal clock synchronization packet path; logic coupled to the one or more processors and when executed is operable to compute, from the network topology, a diverse reciprocal clock synchronization packet path, from the server to the synchronization destination, comprising a diverse forward path and a diverse return path, wherein no network component other than path end points is in both the reciprocal clock synchronization packet path and the diverse reciprocal clock synchronization packet path; logic coupled to the one or more processors and when executed is operable to inject a first time synchronization packet into the reciprocal clock synchronization packet path; inject a second time synchronization packet into the diverse reciprocal clock synchronization packet path; synchronize time at the synchronization destination with time at the server based on the first time synchronization packet and the second time synchronization packet.