Patent ID: 7715223

Claim:
A semiconductor integrated circuit device comprising: a plurality of memory cells, each of the memory cells including a first CMOS inverter which has a first P-channel MOS transistor and a third N-channel MOS transistor, a second CMOS inverter which has a second P-channel MOS transistor and a fourth N-channel MOS transistor, a first N-channel MOS transistor connected to an output node of the first CMOS inverter and a second N-channel MOS transistor connected to an output node of the second CMOS inverter, the memory cells being arranged in a matrix along a first direction and a second direction which is perpendicular to the first direction; a plurality of word lines, each of the word lines being connected to the first and second N-channel MOS transistors corresponding to the memory cells of the first direction; a plurality of first bit lines, each of the first bit lines being connected to the first N-channel MOS transistors corresponding to the memory cells of the second direction; a plurality of second bit lines, each of the second bit lines connected to the second N-channel MOS transistors corresponding to the memory cells of the second direction; a power supply line to supply a power voltage; a plurality of power transistors coupled to the power supply line and each of the power transistors arranged corresponding to the memory cells of the second direction; a plurality of memory cell power supply lines coupled to corresponding to the power transistors and each of the memory cell power supply lines arranged along the first and second bit lines; and a write driver which writes data to the memory cells, wherein each of the memory cells has a first part, a second part and a third part, and the parts are arranged in order of the first part, the second part and the third part along the first direction, wherein the first part includes the first N-channel MOS transistor and the third N-channel MOS transistor, wherein the second part includes the first P-channel MOS transistor and the second P-channel MOS transistor, and wherein the third part includes the second N-channel MOS transistor and the forth N-channel MOS.