Patent ID: 7529294

Claim:
A digital system, comprising: (a) a first pin and a second pin; (b) a first logic domain and a second logic domain; and (c) a first test pulse generator circuit and a second test pulse generator circuit, wherein the first test pulse generator circuit is electrically coupled to the first pin and the first logic domain, wherein the second test pulse generator circuit is electrically coupled to the second pin and the second logic domain, wherein in response to a first test signal being asserted and K common test enable signals being asserted, K being a positive integer, the first test pulse generator circuit is capable of generating two first test pulses to the first logic domain resulting in the first logic domain being tested, and wherein in response to a second test signal being asserted and the K common test enable signals being asserted, the second test pulse generator circuit is capable of generating two second test pulses to the second logic domain resulting in the second logic domain being tested.