Patent ID: 7804140

Claim:
A semiconductor structure comprising: a semiconductor portion located in a semiconductor substrate, said semiconductor portion having a first lengthwise sidewall, a second lengthwise sidewall, a first widthwise sidewall, and a second widthwise sidewall, and including a body region, a source region abutting said body region, and a drain region abutting said body region and disjoined from said source region, wherein said body region has a same composition throughout; a gate dielectric in direct contact with an upper surface of said body region; a shallow trench isolation structure located in said semiconductor substrate and laterally surrounding and abutting said semiconductor portion, wherein said source region laterally abuts said first widthwise sidewall, said drain region laterally abuts said second widthwise sidewall, and said source region and said drain region are separated from said first and second sidewalls by said body region, and wherein said body region is in direct contact with sidewalls of said shallow trench isolation structure; and a gate electrode overlying an edge of said source region and an edge of said drain region, wherein an underlying semiconductor layer is located directly beneath said body region and a bottom surface of said shallow trench isolation structure, said entirety of said body region and said underlying semiconductor layer have said same composition throughout and are epitaxially aligned to each other.