Patent ID: 8046615

Claim:
A microcomputer system comprising: a main CPU section including a main CPU that operates upon receiving a main clock signal; a sub-CPU section including a sub-CPU, the sub-CPU section having a smaller number of circuit gates than the main CPU section; a sub-oscillator circuit that oscillates and outputs a sub-clock signal, which has a frequency lower than that of the main clock signal and is supplied to the sub-CPU section, the sub-oscillator circuit being configured to change over between a continuous mode for continuous oscillation and an intermittent mode for intermittent oscillation; and a power supply control circuit that is mounted in the sub-CPU section, and controls a power supply to at least a part of the main CPU section, wherein the main CPU is configured to give an operation stop notification to the sub-CPU when the main CPU determines that an operation stop condition of the main CPU is satisfied, wherein the sub-CPU is configured to stop the power supply to at least a part of the main CPU section and set the sub-oscillator circuit to the intermittent mode when the sub-CPU recognizes the operation stop notification, wherein the sub-CPU is configured to check whether an operation start condition of the main CPU section is satisfied in a period where the sub-clock signal is supplied, and wherein the sub-CPU is configured to change over the sub-oscillator circuit to the continuous mode, and restart the power supply to at least a part of the main CPU section when the operation start condition is satisfied.