Patent ID: 7327356

Claim:
A data transmission device that transmits parallel data of a plurality of bits that is supplied from a transmission side in parallel to a reception side via a plurality of signal lines, each of the plurality of bits representing a first logic level or a second logic level, the data transmission device comprising: a parallel data control unit that outputs the parallel data when the number of bits representing the first logic level in the parallel data is equal to or less than the number of bits representing the second logic level and outputs parallel data for which a logic level of each bit of the parallel data is inverted when the number of bits representing the first logic level is greater than the number of bits representing the second logic level, and outputs inversion information indicating whether the parallel data that is supplied from the transmission side is inverted; a plurality of signal lines corresponding with each bit of the parallel data outputted by the parallel data control unit; a data transmitter portion that allows a first current to flow to the signal lines corresponding with a bit representing the first logic level in the parallel data outputted by the parallel data control unit and allows a second current that is larger than the first current to flow to the signal lines corresponding with a bit representing the second logic level in the parallel data; a data receiver portion that outputs parallel data of a plurality of bits by outputting a bit representing the first logic level as an output that corresponds with a signal line in which the first current flows and outputting a bit representing the second logic level as an output that corresponds with a signal line in which the second current flows; and a parallel data supply control unit that, when the inversion information indicates that parallel data supplied from the transmission side is inverted, supplies parallel data for which the logic level of each bit of the parallel data outputted by the data receiver portion is inverted to the reception side, and that, when the inversion information indicates that the parallel data supplied from the transmission side is not inverted, supplies parallel data that is outputted by the data receiver portion to the reception side.