Patent ID: 8779847

Claim:
A method for signal processing using a finite impulse response filter circuit, wherein the finite impulse response filter circuit includes a plurality of stages, the method comprising: receiving an input signal at the finite impulse response filter circuit including the plurality of stages, wherein each stage of the plurality of stages is associated with a sample value of the input signal and a stage weight; generating an output signal using the finite impulse response filter circuit, the output signal being equal to a weighted sum of the sample values of the input signal; generating an error signal indicating a difference between the output signal and a target; and applying a constraint to one or more of the stage weights, wherein applying the constraint to the one or more of the stage weights includes: changing the one or more stage weights within the constraint to reduce a magnitude of the error signal, wherein when a predetermined condition is satisfied, one or more first stage weights among the one or more stage weights is left unchanged, and wherein when the predetermined condition is not satisfied, one or more second stage weights among the one or more stage weights is left unchanged, at least one second stage weight being different from the first stage weights.