Patent ID: 7420861

Claim:
A semiconductor memory device, comprising: a bit line pair; a word line arranged perpendicular to the bit line pair; a local data line pair arranged parallel to the word line and connected to the bit line pair in response to a column selecting signal; first and second global data line pairs arranged parallel to the bit line pair and connected to the local data line pair; a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level; a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level; a first switching circuit connected between the local data line pair and the first global data line pair; a second switching circuit connected between the first global data line pair and the second global data line pair; and a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line.