Patent ID: 8559451

Claim:
A method comprising: decoding in parallel a first set of data blocks and a second set of data blocks using a first decoder processor of a decoder and a second decoder processor of the decoder, the first set of data blocks and the second set of data blocks having memory addresses associated with a plurality of non-overlapping memory banks; sorting the decoded first set of data blocks to a first plurality of buffers or a second plurality of buffers depending on the memory addresses of the first set of data blocks, the first plurality of buffers being associated with a first memory bank of the plurality of non-overlapping memory banks, and the second plurality of buffers being associated with a second memory bank of the plurality of non-overlapping memory banks; sorting the decoded second set of data blocks to the first plurality of buffers or the second plurality of buffers depending on the memory addresses of the second set of data blocks; selecting one of the decoded first set of data blocks or one of the decoded second set of data blocks from the first plurality of buffers and communicating the one of the decoded first set of data blocks or the one of the decoded second set of data blocks from the first plurality of buffers to the first memory bank; and selecting one of the decoded first set of data blocks or one of the decoded second set of data blocks from the second plurality of buffers and communicating the one of the decoded first set of data blocks or the one of the decoded second set of data blocks from the second plurality of buffers to the second memory bank; reading the one of the decoded first set of data blocks or the one of the decoded second set of data blocks from the first memory bank; and processing the one of the decoded first set of data blocks or the one of the decoded second set of data blocks through a systematic iteration.