Patent ID: 7814303

Claim:
A circuit, comprising: a register file including a plurality of vector registers configured to store operand vectors, wherein each operand vector includes a plurality of data elements; processing logic coupled to the register file and configured to process instructions from an instruction stream, wherein the instructions in the instruction stream are selected from an instruction set that defines a vector instruction and a swizzle sequence instruction, wherein the processing logic includes vector execution logic configured to retrieve operand vectors from the register file and process the retrieved operand vectors responsive to vector instructions received by the processing logic, and wherein the swizzle sequence instruction identifies a sequence of data element orders to be used during execution of a sequence of vector instructions to selectively shuffle data elements from operand vectors when the processing logic is processing the sequence of vector instructions; and swizzle logic coupled to the processing logic and configured to selectively shuffle data elements from operand vectors retrieved from the register file by the vector execution logic when the vector execution logic is processing the retrieved operand vectors, wherein the swizzle logic is configured to, in response to a sequence of vector instructions received by the processing logic subsequent to reception of a swizzle sequence instruction by the processing logic, sequence through a sequence of data element orders identified by the swizzle sequence instruction to selectively shuffle data elements from operand vectors retrieved from the register file by the vector execution logic such that each vector instruction in the sequence of vector instructions is executed by the vector execution logic with data elements from operand vectors retrieved from the register file by the vector execution logic shuffled using an associated data element order in the sequence of data element orders.