Patent ID: 7335553

Claim:
A method for forming memory cells comprising: providing a substrate on which has a grid shallow trench isolation (STI) and a plurality of active regions isolated by the STI, wherein the active regions are covered by a hard mask layer; forming a plurality of photoresist strips parallel to each other on part of the hard mask layer to define positions for deep trenches of a trench capacitor in any adjacent two active regions; performing an etching process with the STI and the hard mask layer used as an etching mask to etch the substrate and form the deep trenches respectively in the active region, wherein the STI are etched to the same height with the substrate; forming diffusion regions in the substrate of the sidewalls and the bottom in each deep trench; forming a capacitor dielectric layer on the surface of the sidewalls and the bottom in each deep trenches; forming capacitor bottom electrodes covering the STI between a pair of adjacent active regions in each deep trenches whereby a continuous structure is formed; and forming a plurality of transistors electrically connected to the capacitors on the substrate.