Patent ID: 8339882

Claim:
An integrated circuit device incorporating a random access memory array comprising: a first pair of cross-coupled transistors coupling a first pair of complementary bit lines to a first node; a second pair of cross-coupled transistors coupling a second pair of complementary bit lines to a second node; a first pair of common gate coupled transistors, each coupling one of said first pair of complementary bit lines to a reference voltage level and receiving a precharge signal at said common coupled gates thereof; a second pair of common gate coupled transistors, each coupling one of said second pair of complementary bit lines to a supply voltage level and receiving a complement of said precharge signal at said common coupled gates thereof; and first and second additional transistors for coupling said first and second nodes respectively to a charge sharing line in response to an additional precharge signal at their common coupled gates thereof, wherein said additional precharge signal is activatable prior to said precharge signal and said complement of said precharge signal.