Patent ID: 8216886

Claim:
A method for assembling a Flat No-lead semiconductor package, comprising: mounting a base surface of a semiconductor die to a support substrate; electrically connecting die electrical connection pads on an upper surface of the die to respective external connection pads that are mounted to the support substrate; encapsulating the semiconductor die and external connection pads with an encapsulation material to form the semiconductor package, wherein the encapsulation material and support substrate sandwich the external connection pads therebetween; curing the encapsulation material at a curing temperature; and rapidly cooling the encapsulation material from the curing temperature to a cooled temperature of no more than fifty degrees centigrade, the rapid cooling being at least partially assisted by a fluid flow directed over the encapsulation material to thereby reduce a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum cooling period of less than five minutes.