Patent ID: 7816216

Claim:
A method of forming a transistor, comprising: forming a vertically oriented opening within a semiconductor material, wherein the vertically oriented opening comprises a top, a bottom formed from the semiconductor material, and vertically oriented sidewalls between the top and bottom; isotropically etching the semiconductor material at the bottom of the vertically oriented opening to form a rounded opening of wider cross-section than the vertically oriented opening; anisotropically etching the semiconductor material of the rounded opening and in alignment with the vertically oriented opening to form a protruding opening below and continuous with the rounded opening, the protruding opening being of narrower cross-section than the rounded opening and having a rounded bottom; forming gate dielectric on exposed surfaces of the semiconductor material which define the vertically oriented opening, the rounded opening, and the protruding opening; and forming conductive gate material over the gate dielectric within the vertically oriented opening, the rounded opening, and the protruding opening.