Patent ID: 7352890

Claim:
A method for analyzing defects in electronic circuit patterns, comprising: inspecting a first object to detect structural defects during a production process and obtaining position information of said structural defects; detecting images of said structural defects using said position information of said defects; performing an electronic test on said first object after said production process is completed to detect electrical faults in said first object and obtain position information of said electrical faults; comparing said position information of said structural defects with said position information of said electrical faults and extracting corroborated defects having common position information between said structural defects and said electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of said defects, and results of performing the electronic test to each other; inspecting a second object during the production process to detect defects and obtain information of said defects including position information and image of said defects; classifying images of said defects detected on said second object into critical defects and non-critical defects by using information of said step for classifying images; and outputting information on said classified defects images of said second object.