Patent ID: 8058651

Claim:
A thin film transistor array substrate comprising: gate lines and data lines crossing each other to define pixel regions on a substrate; a plurality of thin film transistors disposed adjacent to each crossing point of one of the gate lines and one of the data lines, each thin film transistor including a gate electrode protruded from the gate line, a source electrode protruded from the data line, a drain electrode located adjacent the source electrode, and a semiconductor layer disposed between the gate electrode and the source and drain electrodes; a gate insulating layer disposed between the gate line and the semiconductor layer; a plurality of pixel electrodes on the pixel regions, being in contact with the drain electrode; a plurality of transparent electrode patterns directly on the data lines, wherein the source electrodes protrude from the data line; gate pad patterns disposed at an end of one of the gate lines; gate pad terminals disposed on one of the gate pad patterns, wherein the gate pad terminals are disposed on the same layer as the pixel electrode layer; data pad patterns disposed at an end of one of the data lines; data pad terminals disposed on one of the data pad patterns, wherein the data pad terminals are disposed on same layer as the pixel electrode layer; and a passivation layer formed over a surface of the substrate including the gate lines, the data lines, the thin film transistors, and the pixel electrode layer, wherein the semiconductor layer and the gate insulating layer are patterned to have same openings, and wherein the pixel electrodes, transparent electrode patterns, the gate pad terminals and the data pad terminals are located in the same layer.