Patent ID: 8132076

Claim:
A circuit for reordering data units of a data block in accordance with a first pre-determined function, the circuit comprising: a single-port memory module having a plurality of memory locations, wherein (i) each memory location has a corresponding address and (ii) each memory location corresponds to a different delay; a first address generator configured to, for each data unit of the data block, generate an address corresponding to a memory location into which the data unit is to be stored, wherein the first address generator generates each address in accordance with the first pre-determined function, wherein as the data units are read out of the plurality of memory locations of the single-port memory, the data units of the data block are reordered in accordance with (i) the first pre-determined function and (ii) the different delays associated with the plurality of memory locations; a dual-port memory module having a plurality of memory locations, wherein each memory location of the dual-port memory module has a corresponding address; and a second address generator configured to, for each data unit read out of a memory location of the single-port memory module, generate an address corresponding to a memory location of the dual-port memory module into which the data unit is to be stored, wherein the second address generator generates each address in accordance with a second pre-determined function.