Patent ID: 8502292

Claim:
A semiconductor device comprising m (m is an integer of 2 or more) write word lines, m read word lines, a bit line, a source line, a signal line and a first to an m-th memory cells connected in series between the bit line and the source line, the first to the m-th memory cells each comprising: a first transistor including a first gate electrode, a first source electrode, a first drain electrode and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode and a second channel formation region; and a capacitor, wherein the first channel foil cation region includes a semiconductor material different from a semiconductor material of the second channel formation region, wherein in each of the first to the m-th memory cells, the first gate electrode, either the second source electrode or the second drain electrode, and one electrode of the capacitor are electrically connected to form a node of which electric charges are held, and wherein a parasitic capacitance of the node included in the m-th memory cell is half of or more than half of a parasitic capacitance of the node included in an i (i is an integer of from 1 to (m−1))-th memory cell.