Patent ID: 6918018

Claim:
A data processing apparatus comprising: a central processor unit having three N-bit composite busses each of said busses carrying data, address, and control words; an internal memory partitioned into two memory banks; a memory interface unit connecting said central processor unit and said internal memory, said memory interface unit responsive to two addresses for supplying said central processor unit an N-bit data word from each memory bank corresponding to a first address on a first N-bit composite bus and one N-bit data word from a selected memory bank corresponding to a second address on a second N-bit composite bus; a pair of data paths each directly connected to one of said memory banks of said internal memory, a first data path carrying an N-bit data word corresponding to said first address and a second data path carrying an N-bit data word corresponding to said second address; and a numerical co-processor receiving three N-bit data words from said central processor unit and directly connected to said pair of data paths for receiving one N-bit data word from a memory bank opposite to said selected memory bank corresponding to said second address.