Patent ID: 7517750

Claim:
A method of manufacturing a memory device, comprising: forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once using a process using O 3 gas as a reactive gas, wherein the zirconium oxide layer is formed using TEMAZ (tetrakis methylethylamino zirconium; Zr[N(CH 3 )(C 2 H 5 )] 4 ) gas as a source gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern.