Patent ID: 8302064

Claim:
A method of obtaining performance improvement by selective feature sizing of devices contained within a semiconductor die, the method comprising: collecting performance metrics of devices contained within the semiconductor die, each performance metric being one of a leakage current measurement or a threshold voltage measurement; wherein each device has a respective individual performance metric value; categorizing each device into one bin of a plurality of bins in response to the collected performance metrics; wherein the categorizing includes categorizing all of the devices that have respective individual performance metric values that are within a range of performance metric values into a respective one of the plurality of bins, and the range of the respective individual performance metric values of the devices categorized into each of the plurality of bins does not overlap the range of the respective individual performance metric values of the devices categorized into any other of the plurality of bins; tagging each bin with a respective sizing adjustment; wherein the plurality of bins includes at least two bins that are tagged with different respective sizing adjustments that are not equal to zero; selectively altering feature sizes of each device categorized in each bin in accordance with the tagged sizing adjustment for each bin; and wherein the feature sizes are selectively altered by modifying one or more mask layers that define the feature sizes of devices categorized within the bins that are tagged with non-zero sizing adjustments.