Patent ID: 7764107

Claim:
A multiplexer comprising: a multiplexer circuit comprising: a differential input stage that receives at least two input data signals; a differential output stage that provides an output data signal and a compliment of the output data signal, the differential output stage comprising: a first transistor that receives an internal data signal from the differential input stage; a first current mirror coupled to the first transistor, wherein the first transistor controls the first current mirror in response to the internal data signal; a second transistor coupled to the first current mirror that receives a compliment of the internal data signal from the differential input stage; a first output node coupled to the first current mirror and the second transistor that provides the output data signal; a third transistor that receives the compliment of the internal data signal from the differential input stage; a second current mirror coupled to the third transistor, wherein the third transistor controls the second current mirror in response to the compliment of the internal data signal; a fourth transistor coupled to the second current mirror that receives the internal data signal from the differential input stage; and a second output node coupled to the second current mirror and the fourth transistor that provides the compliment of the output data signal; wherein the differential output stage maintains a rise time of the output data signal substantially the same as a fall time of the output data signal; and an adjustable biasing current that controls the rise and fall times of the output data signal; and a delay bias circuit that analyzes the rise time or the fall time of the output data signal and generates a bias control signal that is varied in response to the analysis; wherein the bias control signal is provided to the multiplexer circuit to adjust the biasing current.