Patent ID: 7521318

Claim:
A method of manufacturing a semiconductor device, including a memory cell transistor array having a gate structure a floating gate electrode and a control gate electrode on a semiconductor substrate, comprising: forming an isolation trench in self-alignment with floating gate electrodes of adjacent memory cell transistors on a surface layer of a semiconductor substrate; forming a first isolation insulating film of a first isolative material in the isolation trench in such a manner that a recess configured by the first isolation insulating film is formed in the isolation trench; implanting impurity ions into the semiconductor substrate under the isolation trench through the recess and the first isolation insulating film to form an impurity region in the semiconductor substrate in self-alignment with the recess; after the implanting of the impurity ions, filling a second isolative material in the recess to form a second isolation insulating film of the second isolative material in the recess; and activating the implanted impurity ions before or after the second isolation insulating film is formed, wherein the first isolation insulating film is formed of a silicon oxide film, and the second isolation insulating film is formed of a polysiloxane film.