Patent ID: 7391246

Claim:
A digital high speed programmable delayed locked loop (DLL) comprises: a zero degree phase shift digital delay line operably coupled to produce, from a clock signal, a zero phase shifted representation of the clock signal; a plurality of intermediate phase shift digital delay lines, comprising: a ninety degree phase-shift digital delay line operably coupled to produce, from the clock signal, a ninety degree phase-shifted representation of the clock signal based on an intermediate control signal; a one hundred and eighty degree phase-shift digital delay line operably coupled to produce, from the clock signal, a one hundred and eighty degree phase-shifted representation of the clock signal based on the intermediate control signal; and a two hundred and seventy degree phase-shift digital delay line operably coupled to produce, from the clock signal, a two hundred and seventy degree phase-shifted representation of the clock signal based on the intermediate control signal, wherein the two hundred and seventy degree phase-shifted representation of the clock signal corresponds to the intermediate phase-shifted representation of the clock signal; a three hundred and sixty degree phase shift digital delay line operably coupled to produce, from the clock signal, a three hundred and sixty degree phase shifted representation of the clock signal based on a three hundred and sixty degree control signal; and digital control module operably coupled to produce the intermediate control signal and the three hundred and sixty degree control signal based a phase difference between the zero phase shifted representation of the clock signal and the three hundred and sixty degree phase shifted representation of the clock signal.