Patent ID: 8370783

Claim:
A computer-implemented method comprising: storing data defining nets and corresponding pins for connection in an integrated circuit design; storing data defining a plurality of interconnect models; dividing the integrated circuit into a plurality of tiles; for each net, a computer selecting from among the plurality of interconnect models one or more interconnect models that satisfy timing constraints of the net for a set of tiles of the plurality of tiles, the computer assigning probability to each selected interconnect model of the net, the probability being a degree of possibility that the interconnect model will be used to connect the pins of the net and being evaluated based on at least one of area congestion, wire congestion, and power consumption when the interconnection model is used to connect the pins of the net; the computer assigning contribution from each selected interconnect model to area congestion, wire congestion, and power consumption of each tile of the plurality of tiles; the computer generating a map of the integrated circuit design indicative of probabilistic routing characteristics based on the contribution assigned to each of the tiles in the integrated circuit design and the probability of each selected interconnect model; and wherein each of the interconnect model is a combination of routing layers, repeater cell type, and wire width and spacing.