Patent ID: 8324705

Claim:
An integrated circuit structure comprising: a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region, wherein the metal-containing layer and the first well region form a Schottky barrier; an isolation region encircling the metal-containing layer; a third well region of the second conductivity type encircling at least a central portion of the first well region, wherein the third well region does not contact any portion of the first well region, and wherein the third well region comprises a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions; a fourth well region having substantially a same impurity concentration and substantially a same depth as the third well region; a first core MOS device with portions in the fourth well region; a fifth well region of the second conductivity type substantially on an inner side of the third well region, wherein the fifth well region forms a ring encircling a central portion of the first well region; and a second core MOS device of an opposite conductivity type than the first core MOS device, wherein the second core MOS device comprises a source/drain region, and wherein the fifth well region has substantially a same impurity concentration and substantially a same depth as the source/drain region.