Patent ID: 7391190

Claim:
A circuit for DC-DC conversion, comprising: an error circuit that is arranged to receive a feedback signal that is based, in part, on at least one of an output voltage or a load current; and to provide an error signal that is based, at least in part, on the feedback signal; a comparator that is arranged to compare the error signal with a pulse width modulating signal, and to provide a comparator output signal based on the comparison; a switch control logic circuit that is arranged to receive the comparator output signal, wherein the switch control logic circuit is arranged to receive a clock signal, and wherein the switch control logic circuit is configured to control a plurality of switches such that: at least when the input voltage is relatively close to a pre-determined voltage, the switches are controlled such that buck-boost mode PWM regulation is performed; the buck-boost PWM regulation has three distinct phases during each clock pulse of the clock signal, wherein the three phases include: a first phase that occurs between the beginning of the clock pulse and the time that the comparator trips, a second phase that occurs between the time that the comparator trips and the time that the comparator untrips, and a third phase that occurs between the time that the comparator untrips and a time that the next clock pulse begins; during one of the three phases, an inductor current is charged; during another of the three phases, the inductor current is discharged; and during yet another of the three phases, the inductor current is maintained at a roughly constant, non-zero value.