Patent ID: 7502658

Claim:
A method for performing fabrication sequence analysis, the method comprising: defining a process group, wherein a process group includes fabrication processes in a fabrication sequence; determining fabrication process paths in the process group to define independent variables, wherein a process path is a plurality of fabrication equipment used to fabricate a particular semiconductor device in the fabrication sequence; receiving a dependent variable for the fabrication sequence; performing analysis of variance to calculate a p-value for the process group; determining whether the p-value is lower than a threshold value; identifying a poor process path responsive to determining that the p-value is lower than a threshold value; outputting the identified poor process path; determining whether the dependent variable is a parametric value; calculating Cpk values, wherein Cpk = min ⁡ [ USL - mean 3 ⁢ σ , mean - LSL 3 ⁢ σ ] and USL is an upper specification limit, LSL is a lower specification limit, mean is an average value of the parametric variable for the process path, and σ is a standard deviation of the parametric variable for the process path; and identifying a process path having a lowest Cpk value as the poor process path.