Patent ID: 7898876

Claim:
A nonvolatile memory device, comprising: a memory cell array comprising a number of memory blocks each including memory cells for storing data, the memory cells being coupled by a bit line and a word line; a page buffer unit, comprising page buffers coupled to the bit line and configured to include a plurality of latch circuits for latching data to be programmed into the memory cells or storing data from the memory cells, wherein each of the page buffers comprises a bit line control unit configured to temporarily charge a voltage of a bit line varying according to a program degree of memory cells when a program verification operation is performed and to provide the bit line with the charged voltage when a program operation for the bit line is performed; and a control unit configured to control a program, read, or erase operation, charge a voltage of a bit line according to a verification result to the page buffer when a program verification operation is performed using a double verification method, and apply the bit line with the voltage charged at the page buffer when a program operation is performed.