Patent ID: 7948021

Claim:
A semiconductor memory device comprising: a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area; a word line contact area adjacent to the memory cell array area and having a second active area; first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area; first and second contact holes provided respectively corresponding to the first and second word lines in the word line contact area; and a word line driver connected to one end of each of the first and second word lines via the first and second contact holes, wherein, a dummy gate electrode is arranged just below the first and second word lines in the second active area, side surfaces of the first and second word lines are in contact with a first insulating film and a second insulating film on the first insulating film, and a highest portion of the first insulating film exists at a position lower than upper surfaces of the first and second word lines and higher than lower surfaces of the first and second word lines.