Patent ID: 7934032

Claim:
In an electronics system having a PCI Express-based processor (CPU) module in communication with a plurality of PCI Express-based input/output (I/O) modules, the CPU module having a fixed number of lanes with which to communicate with the I/O modules, a method for distributing the lanes among the I/O modules, the method comprising: receiving, by the CPU module, a coded signal from each I/O module through a sideband interface between the CPU module and that I/O module; identifying a link-width capability of each I/O module from the coded signal received from that I/O module through the sideband interface between the CPU module and that I/O module; configuring the CPU module to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability identified from the coded signal received from that I/O module; transmitting from the CPU module to each I/O module through the sideband interface between the CPU module and that I/O module a second coded signal that communicates to that I/O module the link width allocated to that I/O module; and training a link between the CPU module and each I/O module in accordance with the link width allocated to that I/O module.