Patent ID: 8493766

Claim:
A semiconductor device comprising: a first memory cell and a second memory cell, each of the first memory cell and the second memory cell including a first transistor and a second transistor; each of the first transistor and the second transistor in each of the first memory cell and the second memory cell comprising a gate, a source and a drain; a first wiring electrically connected to one of the source and the drain of the first transistor of the first memory cell and one of the source and the drain of the first transistor of the second memory cell; a second wiring electrically connected to the other of the source and the drain of the first transistor of the first memory cell and one of the source and the drain of the second transistor of the first memory cell; a third wiring electrically connected to the other of the source and the drain of the first transistor of the second memory cell and one of the source and the drain of the second transistor of the second memory cell; and a fourth wiring electrically connected to the gate of the second transistor of the first memory cell and the gate of the second transistor of the second memory cell, wherein in each of the first memory cell and the second memory cell, the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor.