Patent ID: 7571435

Claim:
A software method of improving at least one of efficiency and speed in executing a linear algebra subroutine on a computer having a floating point unit (FPU) with floating point registers (FRegs) and a load/store unit (LSU) capable of overlapping loading data and processing said data by the FPU, said FPU being interfaced with an L1 (Level 1) cache and having an L1 cache/FReg interface “loading penalty of n cycles”, n being an integer greater than or equal to 1, during which data is rearranged in up to n cycles in said FRegs because data arrives out of order for said processing, said method comprising: loading matrix data from a memory through a cache system at a fastest possible rate; and then either immediately or at a later time, for an execution code controlling operation of said linear algebra subroutine execution, overlapping by preloading data into said FRegs of said FPU and then rearranging the data in said FRegs for up to said n cycles, said overlapping causing said matrix data to arrive into said FRegs from said L1 cache to be timely executed by the FPU operations of said linear algebra subroutine on said FPU.