Patent ID: 8495550

Claim:
A sequential logic cell (also referred to as a latch), comprising: a. four inverter circuits, each inverter: i. comprising at least one p-type MOSFET and at least one n-type MOSFET; ii. connected as a Dual Interlocked Cell (DICE), the DICE cell having four nets (numbered 1,2,3,4), each net: 1. connected to: a. one inverter output and to two gates, such that the n'th net is connected to the output of the n′th inverter, b. to gate of the p-type MOSFET of the (n+1)'th inverter, and c. to the n-type MOSFET gate of the (n−1)'th inverter, in a cyclic manner (such that when n=0, then n−1 refers to the 4'th net, and when n=4 then n+1 refers to the first net), nets 1 and net 3 carrying the same voltage state and net 2 and net 4 carrying the inverse of the voltage state of net 1 and net 3 , 2. comprising: a. one p-type drain contact area (denoted p 1 , p 2 , p 3 , p 4 ); and b. one n-type drain contact area (denoted n 1 , n 2 , n 3 , n 4 ), these contact areas being the original drain contact areas, the MOSFETs of these contact areas being the original 8 MOSFETs, and the DICE circuit cell formed by these MOSFETs the original circuit cell, b. an arrangement where the contact areas of each of the four nets, are placed along a straight line in the layout; and c. the drain contact areas are placed along the straight line in the layout in any of the following orders: i. n 3 , n 4 , p 4 , p 1 , n 1 , n 2 , p 2 , p 3 ; ii. n 4 , n 3 , p 4 , p 3 , n 2 , n 1 , p 2 , p 1 ; iii. n 2 , n 3 , p 4 , p 3 , n 2 , n 1 , p 2 , p 1 ; iv. n 4 , n 1 , n 3 , n 2 , p 3 , p 2 , p 1 , p 4 ; v. n 1 , n 4 , n 3 , n 2 , p 2 , p 3 , p 4 , p 1 ; vi. n 1 , n 4 , n 3 , n 2 , p 4 , p 3 , p 2 , p 1 ; vii. n 4 , p 4 , n 3 , p 3 , n 2 , p 2 , n 1 , p 1 and viii. any order that can be derived naturally from these configuration, under consideration of the circuit symmetry, including cyclic permutations, or an interchange of the following drain contact area pairs: 1. [n 1 , n 3 ]; 2, [n 2 , n 4 ]; 3. [p 1 , p 3 ]; and 4. [p 2 , p 4 ].