Patent ID: 8583868

Claim:
A caching storage system, comprising: a plurality of flash memory units organized in an array configuration, each of the plurality of flash memory units comprising at least one flash memory device and a flash unit controller, and each flash unit controller providing the caching storage system with direct physical block access to its corresponding at least one flash memory device; and a storage cache controller that: selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, issues page write operations to a set of erase blocks, and maintains a block-line mapping for the array configuration, the block-line mapping is organized with flash unit erase blocks that include data information and/or parity information, and the flash unit erase blocks are grouped into erase stripes, and each of the erase stripes is a set of erase blocks that form a complete computation set for the storage cache's array configuration and includes at least one page-stripe that form complete independent parity sets such that a parity page in one page-stripe depends only on other pages within the same page-stripe.