Patent ID: 8731036

Claim:
A clock synchronization system for synchronizing a clock of a slave node with a clock of a master node, the system comprising: the master node including a packet transmitter configured to transmit a packet including a time stamp to the slave node, and the slave node including: a packet receiver configured to receive the packet transmitted from the master node; a packet filter configured to calculate as a value of delay of the packet a difference between a time stamp on the clock of the slave node when the packet is received and the time stamp of the packet received, to correct the value of the delay of the packet or a threshold for the delay of the packet based on a time stamp deviation between a time stamp obtained by the clock of the slave node when the slave node is in synchronism with the master node and a time stamp obtained by the clock of the slave node when the slave node is not in synchronism with the master node, and to perform filter processing on the packet received from the packet receiver based on the value of the delay of the packet and the threshold for the delay of the packet; and a phase synchronizer configured to output the clock of the slave node based on the time stamp included in the packet that is employed by the packet filter.