Patent ID: 8158538

Claim:
A method of manufacturing a single-electron transistor (SET) operating at room temperature using a silicon-on-insulator (SOI) substrate in which at least one buried oxide layer 10 and a top silicon layer 20 are stacked, the method comprising: a first step of forming a nano-wire structure 21 a by etching the top silicon layer 20 ; a second step of forming a second insulation film 30 over an entire surface of the SOI substrate; a third step of forming a trench 31 and a quantum dot 211 , 212 by etching the second insulation film 30 ; a fourth step of forming a third insulation film 40 over an entire surface of the SOI substrate; and a fifth step of forming a gate G in the trench 31 so that the gate wraps around the quantum dot 211 , 212 .