Patent ID: 8407489

Claim:
A processing system comprising: a processor; volatile memory responsive to the processor; non-volatile storage responsive to the processor; and instructions in the non-volatile storage, wherein the instructions, when executed by the processing system, enable the processing system to perform operations comprising: transitioning the processing system from an active state to a sleeping state; before transitioning the processing system from the active state to the sleeping state, using a firmware variable to save a resume descriptor to the nonvolatile storage, wherein the resume descriptor assigns an initialization operation to a component other than system firmware; after transitioning the processing system from the active state to the sleeping state, transitioning the processing system from the sleeping state to the active state, wherein the operation of transitioning the processing system from the sleeping state to the active state comprises initializing, by the system firmware, a first portion of the volatile memory; after transition from the sleeping state to the active state has begun, loading first stage resume content into the volatile memory, wherein the first stage resume content comprises data for a first program that was executing in the processing system before the processing system transitioned to the sleeping state; after transition from the sleeping state to the active state has begun, loading second stage resume content into the volatile memory, wherein the second stage resume content comprises data for a second program that was executing in the processing system before the processing system transitioned to the sleeping state; passing control to the first program before all of the second stage resume content has been loaded into the volatile memory; initializing, by an operating system (OS), a second portion of the volatile memory; and after transition from the sleeping state to the active state has begun but before the OS has finished initializing the second portion of the volatile memory, executing at least one user mode thread.