Patent ID: 7944725

Claim:
A semiconductor memory comprising: a plurality of read amplifiers; a plurality of pairs of complementary bit lines, each bit line of each pair of complementary bit lines having a first end connected to an associated one of the plurality of read amplifiers and a second end; a plurality of binary state memory cells coupled to each of the bit lines; and a plurality of first switching elements, each first switching element coupled to an associated bit line such that at least a first part of the associated bit line is selectively electrically decoupled from the associated read amplifier when reading and/or refreshing a selected binary state memory cell coupled to the associated bit line while a second part of the associated bit line remains electrically coupled to the associated read amplifier, wherein a first non-zero portion of the plurality of binary state memory cells is coupled the first part of the associated bit line and wherein a second non-zero portion of the plurality of binary state memory cells is coupled to the second part of the associated bit line.