Patent ID: 8339866

Claim:
A semiconductor memory device for erasing data comprising: a plurality of blocks including a plurality of memory cell transistors that are provided in every block and have floating gates formed through first gate insulating film above a well formed in a semiconductor substrate and control gates formed through second gate insulating film above the floating gates, data in the memory cell transistors being rewritable by controlling charge amounts accumulated in the floating gates; and a row decoder having a plurality of MOS transistors having drains that are respectively connected to corresponding word lines connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate and source voltages of the MOS transistors, wherein in an erasing operation, first MOS transistors that are contained in the MOS transistors and have drains connected to the word lines connected to the control gates of memory cell transistors of a selected block are turned on to fix the control gates of the memory cell transistors of the selected block to a first voltage, and second MOS transistors that are contained in the MOS transistors and have drains connected to the word lines connected to the control gates of memory cell transistors of non-selected blocks are turned off to set the control gates of the memory cell transistors of the non-selected blocks to a floating state, whereby an erasing voltage higher than the first voltage is applied to the well, and when a threshold value voltage of the memory cell transistors of the selected block is higher than a first threshold value voltage, the erasing voltage is applied to the well at only a specified frequency again, wherein the erasing voltage is applied at the specified frequency which is set to twice or more.