Patent ID: 7518602

Claim:
A test circuit of a display device comprising a plurality of pixels arranged in matrix, and a plurality of source signal lines for inputting a video signal to each of the plurality of pixels, comprising: a plurality of shift registers; a plurality of latch circuits; a plurality of first NOR circuits; a plurality of second NOR circuits; a plurality of first NAND circuits; a plurality of second NAND circuits; and a plurality of inverters, wherein the plurality of shift registers are connected in series to each other; wherein the plurality of shift registers are electrically connected to the respective plurality of latch circuits; wherein first input terminals of the plurality of first NOR circuits are electrically connected to the respective plurality of shift registers; wherein second input terminals of the plurality of first NOR circuits are electrically connected to the respective plurality of latch circuits; wherein the plurality of source signal lines are electrically connected to the respective plurality of latch circuits; wherein the plurality of second NOR circuits are connected in parallel to each other; wherein the plurality of second NOR circuits are electrically connected to the respective plurality of first NOR circuits; wherein the plurality of first NAND circuits are connected in parallel to each other; wherein the plurality of first NAND circuits are electrically connected to the respective plurality of second NOR circuits; wherein the plurality of first NAND circuits are electrically connected to the respective plurality of second NAND circuits; wherein among the plurality of second NAND circuits connected in series, a second input terminal of the NAND circuit of a first stage is electrically connected to a power supply; wherein input terminals of the plurality of inverters are electrically connected to output terminals of the plurality of second NAND circuits; wherein output terminals of the plurality of inverters are electrically connected to input terminals of the plurality of second NAND circuits that are different from the plurality of second NAND circuits connected to the input terminals of the plurality of inverters; and wherein the output terminal of the inverter of a last stage is electrically connected to a test output terminal.