Patent ID: 8630130

Claim:
A memory circuit comprising: a transistor; a capacitor; a feedback loop, the feedback loop comprising a first arithmetic circuit and a second arithmetic circuit; a third arithmetic circuit; and a switch, wherein an output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit, wherein the input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch, wherein an output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit, wherein the input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor, wherein the other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit, wherein a channel formation region of the transistor is formed in an oxide semiconductor layer, wherein the feedback loop is configured to be supplied with a clock signal and an inverted signal of the clock signal, wherein potentials of the clock signal and the inverted signal of the clock signal are fixed before a supply of a supply voltage and a supply of the clock signal and the inverted signal of the clock signal are stopped, wherein after the supply of the supply voltage and the supply of the clock signal and the inverted signal of the clock signal are stopped, the clock signal and the inverted signal of the clock signal returned and fixed to the potentials at which they had been fixed are supplied and the supply of the supply voltage is restarted, and wherein the switch is configured to be turned on after the clock signal and the inverted signal of the clock signal are supplied and the supply of the supply voltage is restarted.