Patent ID: 6963122

Claim:
A semiconductor chip, comprising: a capacitive structure, comprising: a) an inner node, comprising: a first pair of vertically aligned strips electrically connected with one or more vias, a second pair of vertically aligned strips electrically connected with one or more vias, the higher strips of both of said pairs at a same metal level, the lower strips of both of said pairs at a same lower metal level; b) an outer node, comprising: at said metal level: a first metal structure having a pair of windows, a first of said windows surrounding and isolated from a first of said higher strips, a second of said windows surrounding and isolated from a second of said higher strips; at said lower metal level: a second metal structure having a pair of windows, a first of said windows surrounding and isolated from a first of said lower strips, a second of said windows surrounding and isolated from a second of said lower strips; said first and second metal structures electrically connected with one or more vias; c) a third metal structure at another metal level other than said metal level and other than said lower metal level, said third metal structure at least partially vertically aligned with at least one of said pairs of vertically aligned strips, said third metal structure electrically connected to said inner node; and, d) a fourth metal structure at said another metal level, said fourth metal structure substantially surrounding said third metal structure on three sides of said third metal structure within the plane of said another metal level to shield said third metal structure, said fourth metal structure electrically connected to said outer node, said fourth metal structure not completely surrounding said third metal structure within the plane of said another metal level.