Patent ID: 7487300

Claim:
A data processing apparatus, comprising a first and second data processing circuit, each with an output for outputting memory access requests, at least the first data processing circuit outputting respective access requests each during a respective validity duration interval; a multiplexing circuit with inputs coupled to the outputs of the first and second data processing circuits; a memory circuit with an input for accepting the access requests successively from an output of the multiplexing circuit, each at least after a minimum memory repetition period following acceptance of a preceding access request; a timing circuit coupled to the first and second data processing circuit and the memory circuit, and arranged to time operation of the first and second processing circuit each substantially periodically, so that the validity duration intervals are substantially periodical with a longer period than the minimum memory repetition period, the timing circuit being arranged to select acceptance time points at which each particular access request from the first data processing circuit is accepted within the validity duration interval in which this particular access request is made, the timing circuit varying a position of the acceptance time points within the validity duration intervals, so that the position is delayed within the validity duration interval to make room for previously accepting an access request passed by the multiplexing circuit from the second data processing circuit and the position is moved toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit within subsequent periods of validity.