Patent ID: 8375171

Claim:
A system for providing a cache memory coherency mechanism within a multi-processor computing system utilizing a shared memory space across the multiple processors, the system comprising: a store address list for storing cache line addresses corresponding to a cache line write request issued by one of the multiple processors; a fetch address list for storing cache line dresses corresponding to a cache line fetch request issued by one of the multiple processors; a priority and pipeline module; a request tracker module; and a read/write address list; wherein the store address list and the fetch address list are queues containing result in cache lookup requests being done by the priority and pipeline module; each entry in the store address list and the fetch address list possess status bits which indicate the state of the request; and the request tracker module links the cache line write requests to fetch requests in order to delay a invalidation of the fetch request in order to maintain deferrals until the completion of the write request.