Patent ID: 7574633

Claim:
A test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal for outputting a clock signal showing the timing at which data signals output from the plurality of data terminals should be acquired, the test apparatus comprising: a reference clock source that generates a reference clock for this test apparatus; a plurality of first variable delay circuits that is provided corresponding to the plurality of data terminals and each of which delays the reference clock by a designated time; a plurality of timing clock generating sections that is provided corresponding to the plurality of data terminals and each of which outputs a timing clock having a phase obtained by shifting a phase of the reference clock delayed by the corresponding first variable delay circuit by a designated phase shift amount; a timing comparator that is provided corresponding to the plurality of data terminals and each of which acquires a data signal output from the corresponding data terminal in accordance with the corresponding timing clock; a plurality of second variable delay circuits that is provided corresponding to the plurality of data terminals and each of which delays the corresponding timing clock by a designated time; a plurality of phase comparators that is provided corresponding to the plurality of data terminals and each of which detects a phase difference between the clock signal output from the clock output terminal and the timing clock delayed by the corresponding second variable delay circuit in order to output the phase shift amount according to this phase difference; a first adjusting section that adjusts a delay amount of each of the plurality of first variable delay circuits so that the plurality of timing comparators acquires data signals simultaneously output from the plurality of data terminals based on the plurality of timing clocks output from the plurality of timing clock generating sections; and a second adjusting section that adjusts a delay amount of each of the plurality of second variable delay circuits, so that the plurality of timing comparators can acquire the data signals simultaneously output from the plurality of data terminals based on the clock signal output from the clock output terminal, in the state that the first adjusting section has adjusted the delay amount of each of the plurality of first variable delay circuits.