Patent ID: 7167022

Claim:
A logic circuit including: a plurality of look up tables (“LUTs”) driven by a plurality of select inputs, each of the plurality of LUTs included either in a first group of LUTs or a second group of LUTs; at least one of the plurality of select inputs driving each of the plurality of LUTs; at least a second of the plurality of select inputs driving each LUT in the first group of LUTs and connectable to drive at least one of the LUTs in the second group of LUTs; at least a third of the plurality of select inputs connectable to drive at least one of the LUTs in the first group of LUTs; at least two LUTs in the first group of LUTs each driving a first multiplexer (“MUX”) and a second MUX; at least a fourth of the plurality of select inputs driving a control input of the first MUX; and at least a fifth select input driving each LUT in the second group of LUTs and connectable to drive at least one of the LUTs in the first group of LUTs; at least a select sixth input of the plurality of select inputs connectable to drive at least one of the LUTs in the second group of LUTs; at least two LUTs in the second group of LUTs each driving a third MUX and a fourth MUX; a least a seventh select input of the plurality of select inputs driving a control input of the third MUX; and a first input MUX and second input MUX, the first input MUX driven by the at least third select input and the at least fifth select input wherein the first input MUX drives at least one of the LUTs in the first group of LUTs and the control input of the second MUX and the second input MUX drives at least one of the LUTs in the second group of LUTS and the control input of the fourth MUX.