Patent ID: 8200943

Claim:
In a microprocessor having a clock, a program control and a plurality of circuit components comprising at least one memory unit and at least one arithmetic logic unit having inputs and at least one output, the improvement wherein said plurality of circuit components are interconnected on a grid of buses; wherein said grid comprises an X-Y grid having respective X and Y buses and each circuit component connects to one or more of said buses; wherein a switch node is present on each intersecting point of an X and Y bus and provides direct bi-directional connection between said X and Y buses; wherein one or more of said plurality of X and Y switch node connections provides connection of a first one of said circuit components to one or more other ones of said circuit components; wherein each of the said plurality of circuit components is switchable under program control to be connected to a predetermined selection of one or more of said plurality of circuit components to route data through said grid for processing by said predetermined selection of one or more of the said plurality of circuit components; wherein said inputs and said at least one output of said arithmetic logic unit are each connected to a separate bus of said grid; and wherein said one or more of said plurality of arithmetic logic units is operative to receive, process and output data during one microprocessor clock cycle.