Patent ID: 7111265

Claim:
An I/O pin placement method for locating a plurality of I/O pins on an integrated circuit, the method comprising: (a) partitioning the pins into a plurality of pin groups, pins in a pin group being compatible with other pins in the same group under prescribed criteria relating to characteristics of an I/O bank group comprising one or more I/O banks such tat the pins in the pin group are operable to be placed in the I/O bank group without violating the prescribed criteria; (b) for a first pin group of the plurality of pin groups, generating at least one possible bank solution, a bank solution identifying one or more banks that can accommodate all the pins in the first group without violating the prescribed criteria; (c) for a first bank solution of the at least one possible bank solution, placing pins of the first pin group in the one or more banks identified by the first bank solution consistent wit a maximum window current restriction for pads in the one or more banks of the first bank solution; and (d) repeating (b) and (c) for respective other groups of the plurality of pin groups.