Patent ID: 7341891

Claim:
In an integrated circuit chip including first and second supply potentials, a method of making a programmable memory cell for storing a value, the method comprising: forming a plurality of metal layers separated by a plurality of via layers; forming a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias in the plurality of via layers; forming a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias in the plurality of via layers; forming a one cycle ladder structure, using the first and second metal interconnect structures, that traverses the plurality of metal layers from a bottom metal layer to a top metal layer and back to the bottom metal layer; coupling one of the first and second supply potentials to at least one of said first and second metal interconnect structures to form an output; and altering at least one of the plurality of metal layers to thereby program the output.