Patent ID: 7428677

Claim:
A boundary scan device comprising: a Level Sensitive Scan Design (LSSD) circuit; an LSSD clock structure operatively coupled to said LSSD circuit; and a switch driver circuit operatively coupled to an output of said LSSD circuit, wherein the switch driver circuit includes: a latch; a first gate for gating information into said latch operatively connected to an input of said latch; and a second gate for gating information from said latch operatively connected to said latch; wherein the LSSD circuit includes an L 1 latch connected in series to an L 2 latch and wherein the L 1 latch includes: a first inverter with input port and output port; a second inverter with an input connected to the output port and an output; a first N channel Field Effect Transistor (FET) operatively connected to the input port; a second N channel FET operatively connected to the input port; and a feedback conductor interconnecting the output to the input port.