Patent ID: 8890305

Claim:
A semiconductor device comprising: a wiring member having a first surface and a second surface opposite the first surface, a plurality of wirings being formed in the wiring member, a plurality of external terminals being arranged on the second surface; a first semiconductor chip including a memory element, and having a first main surface on which a plurality of first electrodes are formed; and a second semiconductor chip including a logic circuit adapted for controlling the first semiconductor chip, and having a second main surface on which a plurality of second electrodes and a plurality of third electrodes are formed, wherein the first semiconductor chip is mounted over the first surface of the wiring member such that the first main surface of the first semiconductor chip faces the first surface of the wiring member, and such that the first semiconductor chip is located over the second semiconductor chip, all of the first electrodes of the first semiconductor chip are electrically connected with the second electrodes of the second semiconductor chip, respectively, and not electrically connected with the external terminals of the wiring member, and the third electrodes of the second semiconductor chip are electrically connected with the external terminals via the wirings of the wiring member, respectively.