Patent ID: 7567469

Claim:
A semiconductor memory device, comprising: a bit line sense amplifier for amplifying a voltage potential difference of a bit line pair; a sense amplifying driver for supplying a high driving voltage to enable the bit line sense amplifier during an over driving period; and an over driving controller for controlling the over driving period according to fluctuation of a supply voltage, wherein the over driving controller includes a pulse generator for generating an over driving pulse having a width controlled according to the fluctuation of the supply voltage, wherein the pulse generator includes: a delay unit for delaying an input signal, wherein the delay unit includes a plurality of inverters in series; a supply voltage detector for detecting the level of the supply voltage, wherein the supply voltage detector generates an output that is directly proportional to the supply voltage; a delaying controller for controlling a delay time of the delay unit in response to an output of the supply voltage detector, wherein the delaying controller includes current sink transistors connected to the inverters, each current sink transistor is coupled to the said output of the supply voltage detector and receives a signal that is directly proportional to the supply voltage; and an output unit for outputting the over driving pulse by performing a logic operation to the input signal and an output of the delay unit.