Patent ID: 7743084

Claim:
A method comprising: receiving, in parallel, at least three decimal operands wit a decimal multioperand adder circuit of a processing circuit; performing binary carry-save addition with the decimal multioperand adder circuit to produce a set of sum bits and a set of carry bits by: performing a binary carry-save addition with at least two of the decimal operands, correcting one of the other decimal operands to produce a corrected version of the other one of the operands in parallel to performing the binary carry-save addition of the at least two operands, and selectively adding a result of the binary carry-save addition for the at least two operands with either the other one of the decimal operands or the corrected version of the other one of the operands based on a most significant bit of the carry bits to produce the set of sum bits and the set of carry bits; and outputting a decimal result based on the set of sum bits and the set of carry bits,