Patent ID: 6864173

Claim:
A method for forming bit lines, each bit line having a width, of a semiconductor device, comprising the steps of: forming a plurality of word lines and dopant areas on a semiconductor substrate; forming a first inter-insulation layer on the substrate including the word lines, the first inter-insulation layer including landing plug contacts exposing a part of each dopant area; forming landing plugs for embedding the landing plug contacts; forming second and third inter-insulation layers in that order on a front surface of the substrate including the landing plugs; forming a fourth mask pattern by a Damacene process on the third inter-insulation layer, wherein the mask pattern defines etching areas at least substantially along the width of each to-be-formed bit line; forming bit line contacts for exposing the landing plugs by etching the third and second inter-insulation layers according to the fourth mask pattern, wherein each bit line contact is formed within the width of the bit line; and forming bit lines for embedding the bit line contacts.