Patent ID: 7620751

Claim:
A host device comprising: a logic component including: a first set of registers having a plurality of bits; a second set of registers having a plurality of bits, each corresponding to a command issued from an initiator to a target, the command being in accordance with a first protocol, wherein each of the plurality of bits in the first set of registers indicate a valid flag of a corresponding bit in the second register; a task scheduler to monitor the plurality of bits of the second register and to schedule a command if a bit in the second register indicates that a command is to be issued; and a connection manager to determine which of a plurality of close connection commands to issue to the target, the plurality of close connection commands including a first close connection command and a second close connection command, the first close connection command being to end a connection to the target but continue to maintain an affiliation with the target, the second close connection command being to end both the connection and the affiliation, and while the affiliation is maintained, the target rejects a connection request from another initiator; if the first protocol is a certain serial protocol and all of a plurality of bits of a certain register are unset, the connection manager being to issue the second close connection command; if the first protocol is other than the certain serial protocol, the connection manager determining which of the plurality of close connection commands to issue based upon state of a single one of the plurality of bits of the certain register.