Patent ID: 7418579

Claim:
Component with a dynamically reconfigurable architecture for processing data comprising a data processing block TD and a general controller CG capable of controlling the data processing block TD characterized in that: the block TD comprises a plurality of reconfigurable elementary data processing blocks BE; each elementary block BE comprises two inputs, E 1 and E 2 for reception of data to be processed, and one output S for transmission of processed data; a common input data bus being capable of transmitting data to be processed to the input E 1 of each of the blocks BE and the controller CG; for each block BE, an output data bus connected to its output S, being capable of transmitting processed data outside the component and through a bypass data bus to the input E 2 of a single other block BE; the controller CG is capable of initializing configurations of blocks BE and controlling their dynamic reconfiguration, controlling data flows at the output from each block BE so as to transmit data either towards the outside or to the input E 2 of another block BE, and controlling data flows at the input of each block BE, wherein the controller CG is capable of controlling transmission of data received from the outside on the common input data bus as and when they arrive, in sequence to each of the blocks BE, the data being transmitted to the next block BE when the maximum processing capacity of the previous block BE is reached.