Patent ID: 8502287

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first cavity formed in the substrate, the first cavity having a sidewall and a bottom; a dielectric lining the sidewall and the bottom of the first cavity, wherein the dielectric is adapted to act as a gate insulator, wherein the gate insulator has a uniform thickness along all portions of the sidewall between an upper extent and a lower extent of a gate conductor; the gate conductor within the cavity extending to the gate insulator at the bottom of the first cavity; a body region of a first conductivity type located in the semiconductor substrate laterally outside the gate insulator; a source region of a second, opposite conductivity type, in the substrate proximate an upper portion of the first cavity and the body region, adapted to inject carriers into the body region in response to a bias applied to the gate conductor; a drain region of the second conductivity type in the substrate, coupled to the body region and adapted to collect carriers from the body region in response to a bias applied to the drain region; a void cavity in the substrate proximate the bottom of the first cavity, located between the drain region and the gate conductor; and a drift space of the second conductivity type underlying an entirety of the void cavity and located between the void cavity and the drain region.