Patent ID: 7550706

Claim:
An output circuit of a solid state imaging device comprising: a source follower circuit that amplifies a voltage value signal, the voltage value signal being formed by a charge detecting portion in accordance with an amount of a signal charge stored by each of pixels, and outputs the amplified voltage value signal as a pickup image signal; a reset transistor that discards the signal charge in the charge detecting portion, which had been subjected to formation of the voltage value signal, to a reset drain in an application of a reset pulse; a bias voltage generating circuit that applies a bias voltage through a resistor to a gate of the reset transistor to which the reset pulse is applied from a reset pulse generating circuit through a coupling capacitor, the bias voltage being generated from a power supply; and a protecting device that applies a voltage of the power supply to a node of the gate and the coupling capacitor so as to charge the coupling capacitor by the power supply when the power supply is turned ON, wherein the protecting device is constituted by an MOS transistor which is connected in parallel with the resistor and is brought into a conducting state to connect the power supply to the node when the power supply is turned ON, wherein the bias voltage generating circuit comprises an enhancement type transistor and an depression type transistor that are connected in series, and wherein a drain of the protecting device is connected to the power supply, a source of the protecting device is connected to the node of the gate of the reset transistor and the coupling capacitor, and a gate of the protecting device is connected to a node of the enhancement type transistor and the depression type transistor.