Patent ID: 7714669

Claim:
Electronic circuitry comprising a phase alignment circuit and a digital controlled oscillator (DCO) and a frequency divider, the electronic circuitry configured to: use the phase alignment circuit to determine a phase relationship between a first signal and a second signal, the second signal derived by dividing an output signal provided by the DCO; use the phase alignment circuit to disable operation of the frequency divider in accordance with the determination, the state of the frequency divider being preserved during the disabling; and use the phase alignment circuit to enable operation of the frequency divider in response to a next rising edge of the first signal, the frequency divider counting toward a predetermined state, the frequency divider providing an output pulse whenever the frequency divider reaches the predetermined state, wherein the phase alignment circuit comprises: a first circuit portion including at least one flip-flop, the first circuit portion configured to provide an internal enable/disable signal responsive to a first enable signal and a second enable signal and a first clock signal, the first clock signal corresponding to a divided-by-N digital controlled oscillator output signal; a second circuit portion including a selector, the second circuit portion configured to provide a second clock signal responsive to a reference clock input signal and an inverted reference input signal; and a third circuit portion including at least two other flip-flops, the third circuit portion configured to provide a frequency divider enable/disable signal responsive to the internal enable/disable signal and the second clock signal and a third clock signal, the third clock signal corresponding to a phase relationship between the first signal and the second signal.