Patent ID: 8062948

Claim:
A method of fabricating a transistor in a semiconductor device, the method comprising: forming a gate structure over a semiconductor substrate; forming a first trench by etching the semiconductor substrate on a side of the gate structure to a first depth; ion-implanting dopants of a first conductivity type to form a source/drain region in the semiconductor substrate on the side of the gate structure with the first trench; after forming the source/drain region, tilted-ion-implanting dopants of a second conductivity type different from the first conductivity type to form a counter doping region over the surface of the source/drain region: etching the semiconductor substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, wherein the source/drain region remains under the second trench after the etching of the semiconductor substrate to form the second trench; and growing an epitaxial layer within the second trench.