Patent ID: 7186592

Claim:
A process for manufacturing a metal oxide semiconductor (MOS) integrated device on a substrate of semiconductor material of a first conductivity type, said process comprising: forming active zones in said substrate; forming source regions of a second conductivity type inside said substrate, drain regions of the second conductivity type and gate structures including at least one layer of conductor material, said gate structures forming with the source regions and the drain regions a plurality of elementary MOS cells of said device; forming a plurality of separation zones alternating with said elementary MOS cells; and masking and depositing a metal layer on said semiconductor substrate in order to form first metal stripes for contacting the source regions, second metal stripes for contacting the drain regions and third metal stripes for contacting each conductor material layer of said gate structures at a point, wherein the formation of a mask and the deposition of said conductor material of the gate structures allows the formation of first prolongations of said conductor material and wherein the formation of a mask provided with windows on said separation zones for depositing metal in order to form fourth metal stripes connected with said third metal stripes and first prolongations of said fourth metal stripes being placed on said first prolongation of said conductor material in order to form another contact point.