Patent ID: 7812635

Claim:
A programmable logic device, comprising: a logic block, the logic block including: a first logic element having a first look up table, the first look up table comprising a first pair of sub-function generators including a first sub-function generator, the first logic element capable of implementing logic functions of a first order, the first sub-function generator including a first set of selection inputs, the first pair of sub-function generators configured to generate a first sub-function output and a second sub-function output, the first look up table of the first logic element including a first mux coupled to select either the first sub-function output or the second sub-function output; a second logic element having a second input look up table including a second pair of sub-function generators including a second sub-function generator, the second sub-function generator including a second set of selection inputs, wherein all selection inputs of the second set are configured to receive a plurality of selection signals other than a plurality of selection signals received by all selection inputs of the first set, wherein the selection inputs of the second set are equal in number to the selection inputs of the first set; and programmable sharing circuitry to selectively couple the first pair of sub-function generators and the second pair of sub-function generators so that the first logic element is capable of performing logic functions of either (i) the first order, or (ii) a second order, wherein the second order is higher than the first order, the programmable sharing circuitry coupled between the first mux and the first sub-function output.