Patent ID: 7769122

Claim:
A timing recovery circuit, for use in a receiver apparatus which receives as a received signal a carrier wave amplitude-modulated by a transmitter apparatus and which comprises an analog/digital converter for converting said received signal into a digital signal by sampling said received signal at n times the frequency of said carrier wave, where n is a positive integer, for recovering a clock signal of said transmitter apparatus by extracting phase difference information indicating a phase difference between transmit timing and receive timing, comprising: a decimation filter for directly inputting an output of said analog/digital converter and for decimating a frequency with which to sample the output of said analog/digital converter down to a frequency m times the frequency of said carrier wave, where m is an integer that satisfies the relation 1 <m <n; a phase difference information calculator for directly inputting an output of said decimation filter and for calculating said phase difference information from the output of said decimation filter, wherein there are three sample points for one symbol, of which a sample point at which an absolute value of a signal level is largest is used as a reference sample point, and the phase difference information is obtained from a difference between sample values at sample points on both sides of the reference sample point; a loop filter for averaging an output of said phase difference information calculator; and an oscillator for generating, based on an output of said loop filter, a clock signal with which said analog/digital converter performs said sampling.