Patent ID: 8040738

Claim:
A method for performing a memory operation in a semiconductor memory device including a plurality of predetermined memory arrays, the method comprising the steps of: receiving a memory operation signal; determining selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal; precharging bitlines of the plurality of predetermined memory arrays to a first voltage potential; after precharging to the first voltage potential, shutting off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential; and performing the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal.