Patent ID: 8595731

Claim:
A multi-core processor chip including at least one cluster of processor cores, wherein each of said at least one cluster includes a plurality of processor cores and a cluster controller unit that is configured to perform program instructions, wherein said cluster controller unit comprises a finite state machine (FSM) and a cluster table, said FSM embodied in a hardware component including memory modules and at least one processor and representing a state of said at least one cluster as one among a finite number of states that characterizes all possible states of said at least one cluster, and said cluster table identifying and keeping track of thread numbers that identify each thread being run within each processor core for all threads within said at least one cluster, and wherein said program instructions configure said controller unit to perform the steps of: determining threads running in a first processor core within a cluster; performing temporary reassignment of each of said threads in said first processor core to a second processor core within said cluster while said cluster controller unit keeps track of each temporary reassignment by making corresponding changes to said FSM; during each of said temporary reassignment of said threads, generating data relating to core performance in said first processor core; and estimating computational demand for each of said threads in said first processor core based on said data relating to core performance.