Patent ID: 7375394

Claim:
A fringing field induced charge trapping memory, comprising: an isolation or semiconductor substrate having a semiconductor layer formed thereon; a doped region formed in a portion of said semiconductor layer, wherein a pocket ion implantation region is optionally formed adjacent to said doped region, wherein the conductive type of said pocket ion implantation region is opposite to the one of said doped region; a gate dielectric layer formed on said semiconductor layer; a gate structure formed on said gate dielectric layer; a normal field induced channel formed in said semiconductor layer and under said gate structure and said gate dielectric layer, wherein at least one end of said normal field induced channel is electronically connected to said doped region; a multi-portion structure consisting of a perpendicular portion formed on the sidewall of said gate structure and a parallel portion formed on said semiconductor layer, wherein said parallel portion acts as tunneling part and said perpendicular portion acts as a charge barrier; a fringing field induced channel formed between said normal field induced channel and said doped region in said semiconductor layer and under said parallel portion of said multi-portion structure, wherein said fringing field induced channel is electronically connected to at least one end of said normal field induced channel; a charging layer or spacer for charge trapping or charge-storing formed on said multi-portion structure for storing carriers; and metal-semiconductor compounds or silicide formed on said gate structure and said doped region.