Patent ID: 7871920

Claim:
A chip fabrication method, comprising: providing a structure which includes: (a) a semiconductor substrate; (b) a transistor on the semiconductor substrate, and (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer greater than two, and wherein the transistor is electrically coupled to the N interconnect layers; forming a first dielectric layer on top of the N interconnect layers; forming a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers; forming a solder bump on the N interconnect layers, wherein the solder bump is electrically coupled to the transistor through the N interconnect layers; forming a laminate substrate on top of the solder bump; and forming an underfill layer being sandwiched between the second dielectric layer and the laminate substrate, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer, and wherein the underfill layer is not in direct physical contact with any interconnect layer of the N interconnect layers.