Patent ID: 8407457

Claim:
A system comprising: a pipelined processor for executing a plurality of instructions by sequentially fetching, decoding, executing and writing results associated with execution of each instruction; and debug circuitry coupled to the pipelined processor for monitoring execution of the instructions to determine when a debug event occurs and generating a debug exception to interrupt instruction processing flow, the debug circuitry further comprising control circuitry for indicating a count of a number of instructions that complete instruction execution by entering a writeback stage of the pipelined processor between an instruction that caused the debug event and a point in instruction execution when the debug exception in response to the debug event is taken, wherein the debug circuitry determines that a debug event has occurred in response to decoding one of the plurality of instructions, comparing an address formed by the pipelined processor with one or more predetermined debug addresses to determine if a data address match has occurred, and comparing a data value accessed by the pipelined processor with one or more predetermined data values to determine if a data value match has occurred, the debug event requiring a match of both comparing operations to occur.