Patent ID: 7564319

Claim:
A structure, comprising: a set of wiring levels on top of a semiconductor substrate, said wiring levels stacked on top of each other from a lowest wiring level nearest said substrate to a highest wiring level furthest from said substrate, each wiring level of said set of wiring levels comprising an interlevel dielectric layer and electrically conductive wires embedded in their respective interlevel dielectric layers; an inductor in said highest wiring level and a next to highest wiring level of said set of wiring levels, a first portion of said inductor confined within a first perimeter of a region of said highest wiring level, said first portion comprising a single electrically conductive non-magnetic loop between an inner magnetic core and a single closed outer magnetic loop, a second portion of said inductor confined within a second perimeter of a region of said next to highest wiring level and comprising a magnetic plate, bottom surfaces of said magnetic core and said outer magnetic loop in physical contact with a top surface of said magnetic plate; and a varactor formed in said substrate, said varactor aligned completely under said first perimeter.