Patent ID: 6941540

Claim:
A gate array design method for an integrated circuit utilizing multi-phase clock signals, said integrated circuit having a core region which is divided into a plurality of areas, each of said plurality of areas including sequential circuit sites and combination circuit sites, said method comprising: providing a netlist describing cells and interconnections thereof within said integrated circuit, said cells including sequential circuit cells to be placed in said sequential circuit sites and combination circuit cells to be placed in said combination circuit sites, different ones of said sequential circuit cells operating with different ones of said multi-phase clock signals; providing a site array data which describes site names of said sites and arrangement of said sequential circuit cells and combination circuit cells within said sites, said sites name respectively indicating cell types of cells which are allowed to be placed within said sites associated therewith, said cell types including said sequential circuit cells and said combination circuit cells; allocating each of multi-phase clock signals used in said integrated circuit to each of said plurality of areas to produce an allocation data representative of an association of said multi-phase clock signals to specific ones of said plurality of areas; modifying said site array data based on said allocation data such that each of said plurality of areas only includes sequential circuit cells which operate with the same ones of said multi-phase clock signals; modifying said netlist to allow said netlist to correspond to said modified site array data; and placing said integrated circuit based on said modified netlist and said modified site array data.