Patent ID: 7984271

Claim:
A processor device, comprising: a plurality of reservation stations, each having a plurality of entries; a plurality of arithmetic pipelines; and a controller for said plurality of reservation stations, and wherein, in a normal mode, a first reservation station of said plurality of reservation stations is associated with a first arithmetic pipeline of said plurality of arithmetic pipelines, in said normal mode, a second reservation station other than said first reservation station of said plurality of reservation stations is associated with a second arithmetic pipeline other than said first arithmetic pipeline of said plurality of arithmetic pipelines, when said controller detects a specific operation mode that an instruction dispatch from said first reservation station to said first arithmetic pipeline is not carried out, said controller makes said second reservation station dispatch a first instruction, having a first highest priority among entries, that satisfies a predetermined output condition to said second arithmetic pipeline and dispatch a second instruction, having a second highest priority, that satisfies said predetermined output condition to said first arithmetic pipeline, and wherein said controller detects either of said normal mode and said specific operation mode by receiving a signal representing whether or not a dispatch was carried out, from said first and second reservation stations, in said specific operation mode, after an instruction is dispatched from said second reservation station to said first arithmetic pipeline, when a dispatchable instruction exists in any entries of said first reservation station and first reservation station dispatches no instruction to said first arithmetic pipeline, said first reservation station outputs a signal representing said dispatch was carried out to said controller, and said controller detects mode change from said specific operation mode to said normal mode; wherein each of the plurality of entries hold bits to judge whether or not to dispatch instructions to the arithmetic pipeline, wherein the bits of each entry are ANDed to determine whether the dispatch is carried out; if the result of the ANDing is “1”, the dispatch is carried out, if the result of the ANDing is “0”, the dispatch is not carried out from the judged entry; and if the output result of all AND circuits is “0” the controller receives a signal representing a change of mode from normal mode to specific operation mode.