Patent ID: 7437538

Claim:
A processor, comprising: a first execution unit configured to execute a longer-latency floating-point instruction, wherein said longer-latency floating-point instruction defines a floating-point computation to be performed on one or more operands; and a second execution unit configured to execute a shorter-latency floating-point instruction; wherein said longer-latency floating-point instruction is configured to execute in a greater number of execution cycles than said shorter-latency floating-point instruction; wherein in response to said longer-latency floating-point instruction being issued to said first execution unit, said second execution unit is further configured to detect from one or more operands of said longer-latency floating-point instruction whether a result of said longer-latency floating-point instruction is determinable without actually performing said floating-point computation to completion; and wherein in response to detecting that said result is determinable, said second execution unit is further configured to flush said longer-latency floating-point instruction from said first execution unit and to determine said result.