Patent ID: 7710761

Claim:
A memory device, comprising: a bit sense line and a bitnot sense line; a random access memory (RAM) word line and a read only memory (ROM) word line; a static RAM (SRAM) bit cell coupled between said bit sense line and said bitnot sense line and responsive to a signal on said RAM word line, said SRAM bit cell including a first RAM pass transistor and a second RAM pass transistor; a ROM bit cell coupled between said bit sense line and said bitnot sense line and responsive to a signal on said ROM word line; and said ROM bit cell including a first ROM pass transistor, a second ROM pass transistor, a first node permanently coupling said first ROM pass transistor to one of a voltage line and a ground line, and a second node permanently coupling said second ROM pass transistor to the other of said voltage line and said ground line, according to programmed data of the ROM bit cell; and wherein said first RAM pass transistor, said second RAM pass transistor, said first ROM pass transistor, and said second ROM pass transistor share a common well region; said first RAM pass transistor and said first ROM pass transistor share a common first terminal connection to said bit sense line; and said second RAM pass transistor and said second ROM pass transistor share a common second terminal connection to said bitnot sense line.