Patent ID: 7984409

Claim:
A hardware description language (HDL) design structure encoded on a non-transitory machine-readable storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of an interconnect level in a back-end-of-line interconnect structure, the HDL design structure comprising: an insulating layer of a dielectric material having a top surface and a bottom surface; an opening having sidewalls extending from the top surface of the insulating layer toward the bottom surface of the insulating layer; a conductive feature disposed in the opening, the conductive feature having a top surface; a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening, the conductive liner layer having sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening; and a conformal dielectric material layer disposed on the sidewall portions of the liner layer, the top surface of the conductive feature, and the insulating layer.