Patent ID: 6897479

Claim:
A thin film transistor matrix device comprising: a plurality of thin film transistors formed on a substrate, each thin film transistor including a gate electrode, a channel layer, a source electrode, a drain electrode, and a gate insulating film between the gate electrode and the channel layer; a first terminal formed on the gate insulating film, said first terminal being connected to the drain electrode of at least one thin film transistor, and having an elongated shape having a first outer periphery and a second outer periphery extending in a length direction; a protective insulating film formed on the substrate, covering the plurality of thin film transistors and said first terminal; a plurality of first contact holes formed at a position corresponding to said first terminal, through said protective insulating film to an upper surface of said first terminal, the plurality of first contact holes being disposed inwardly of said first and second outer peripheries of said first terminal as viewed along the direction normal to the substrate, and arranged along the outer periphery so that said protective insulating film is left while no contact hole is formed in an area surrounded by said first contact holes; said first contact holes being arranged on a first virtual line and a second virtual line extending in a length direction of said first terminal, said first virtual line being disposed between a central line of said first terminal and said first outer periphery, and said second virtual line being disposed between said central line and said second outer periphery; and a first terminal protective conductive film formed on said protective insulating film, said first terminal protective conductive film being connected to said first terminal via said first contact holes.