Patent ID: 8189415

Claim:
A sensing amplifier applied to at least a memory cell coupled to a bit line or a complementary bit line, the sensing amplifier comprising: a sensing circuit, disposed between a sensing line and a complementary sensing line, for updating data or accessing data of the memory cell; a boosting circuit, coupled to the sensing line, the complementary sensing line, and the sensing circuit, for boosting the sensing line and the complementary sensing line during a boosting stage; at least one bit-line isolating circuit, coupled to the sensing circuit, for controlling whether to isolate the bit line from the sensing line and for controlling whether to isolate the complementary bit line from the complementary sensing line; and at least a P-sensing enhancement circuit, coupled to the sensing line, the complementary sensing line, and a reference voltage; wherein when the bit-line isolating circuit isolates the bit line from the sensing line and isolates the complementary bit line from the complementary sensing line, a voltage level of the bit line or the complementary bit line is pulled up to the reference voltage by the P-sensing enhancement circuit during an enhancement stage.