Patent ID: 8812889

Claim:
A method in a memory controller for power control according to a plurality of memory power modes of operation, comprising: generating power and resource control commands to correspond with one of the plurality of memory power modes of operation or to correspond with transitions between the plurality of memory power modes of operation; determining to transition from a first memory power mode of operation in which read and write memory access requests are received and serviced to a second memory power mode of operation, wherein the second memory power mode of operation is a reduced memory power mode of operation in which write memory access requests are received but not serviced; monitoring a plurality of buffers to determine if a read memory access request has been received from a memory client; determining to change from the second memory power mode of operation to the first memory power mode of operation upon detecting that the read memory access request has been received; if any write memory access requests are stored in the plurality of buffers, servicing the write memory access requests stored in the plurality of buffers; and after servicing at least one of the write memory access requests, servicing the read memory access request.