Patent ID: 8242990

Claim:
A liquid crystal display comprising: a liquid crystal display panel including a plurality of liquid crystal cells arranged at crossings of a plurality of data lines and a plurality of gate lines in a matrix format; a timing signal multiplying circuit that generates a first timing signal and a second timing signal whose frequency is higher than a frequency of the first timing signal; a frame counter that detects a multiplied frame period to be driven at the frequency of the second timing signal; a data processing circuit that outputs digital data and allows a frequency of the digital data output during the multiplied frame period to be higher than a frequency of the digital data output during a normal frame period except the multiplied frame period; a timing control signal generating circuit that generates a polarity control signal for controlling polarities of the digital data; a polarity control signal inverting circuit that increases a frequency of the polarity control signal to generate an inverse polarity control signal when a frame period is changed from the normal frame period to the multiplied frame period, wherein the frequency of the inverse polarity control signal is decreased when the frame period is changed from the multiplied frame period to the normal frame period; a data drive circuit that converts the digital data into a data voltage and controls a polarity of the data voltage in response to the inverse polarity control signal; and a gate drive circuit that supplies gate pulses to the gate lines.