Patent ID: 7925951

Claim:
An integrated circuit providing test pads in addition to scan circuitry comprising: A. core circuitry having a core output lead; B. a bond pad; C. an output buffer having an input lead coupled to the core output lead and having an output lead connected to the bond pad; D. a first test signal lead connected to a first test pad; E. a second test signal lead connected to a second test pad; F. peripheral scan circuitry having a peripheral scan path including scannable cells controlling switches: i. a first switch selectively connecting the first test signal lead to the output lead of the output buffer, the first switch having a switch input connected to the first test signal lead, a switch output connected to the output of the output buffer, and a control input connected with the peripheral scan circuitry; and ii. a second switch selectively connecting the second test signal lead to the output lead of the output buffer.