Patent ID: 6965596

Claim:
μ-law-to-A-law translating equipment, comprising: a timing pulse generator that generates a reference frame pulse; a μ-law signal receiving circuit that receives a μ-law PCM signal and outputs parallel μ-law PCM signals according to a reference frame pulse, said μ-law signal receiving circuit comprising: a line receiver that converts the μ-law PCM signal from bipolar to unipolar and outputs a unipolar μ-law signal, a frame buffer that temporarily stores the unipolar μ-law signal, a frame detector that detects the frame leading part of the unipolar μ-law signal and generates an address reset pulse synchronized with the frame leading position for writing to the frame buffer, a frame position comparator that measures the time lag in a position of a reference frame pulse and the address reset pulse for writing to the frame buffer and generates an address reset pulse for reading from the frame buffer, and a serial-parallel converter that converts and outputs a serial μ-law PCM signal read from the frame buffer to parallel μ-law PCM signals; a multiplexer that time-division multiplexes plural parallel μ-law PCM signals and outputs a time-division multiplexed μ-law PCM signal; a μ-law-to-A-law converter that converts the time-division multiplexed μ-law PCM signal to a time-division multiplexed A-law PCM signal; a demultiplexer that demultiplexes the time-division multiplexed A-law PCM signal and outputs plural parallel A-law PCM signals; and an A-law signal output circuit that receives the parallel A-law PCM signals and outputs a serial A-law PCM signal.