Patent ID: 8253136

Claim:
A nonvolatile semiconductor memory device comprising: a substrate; first wires of a stripe shape which are formed on the substrate; a first interlayer insulating layer formed over the first wires; first memory cell holes formed in the first interlayer insulating layer on the first wires; first variable resistance layers which are connected to the first wires via the first memory cell holes, respectively; first non-ohmic elements formed on the first variable resistance layers, respectively; second wires of a stripe shape which are formed on the first interlayer insulating layer such that the second wires respectively cross the first wires so as to be perpendicular to the first wires; a second interlayer insulating layer formed over the second wires; and upper wires formed on the second interlayer insulating layer; wherein each of the second wires has a plurality of layers including at least a portion of the first non-ohmic element and has an electrically-conductive layer in an uppermost layer of the second wire and a semiconductor layer or an insulator layer which is a portion of the first non-ohmic element in a lowermost layer of the second wire; wherein each of the first wires is connected to the upper wire via a first contact penetrating the first interlayer insulating layer and the second interlayer insulating layer; and wherein the uppermost layer of each of the second wires is connected to the upper wire via a second contact penetrating the second interlayer insulating layer.