Patent ID: 7623379

Claim:
A data writing method of a memory system including a memory controller and a non-volatile semiconductor memory being controlled by the memory controller and including a memory cell array, the data writing method comprising: (A) issuing a writing command by the memory controller; (B) receiving the writing command by the memory; (C) applying a writing pulse and writing data to a plurality of memory cells of the memory cell array by the memory; (D) verifying the data written into the plurality of memory cells; (E) returning a pass to the memory controller as a status by the memory if the verification passes; (F) determining whether or not the number of times of applying the writing pulse is equal to the number of pseudo pass issuing pulses if the verification fails; (G) repeating (C) to (F) if the number of times of applying the writing pulse is not equal to the number of pseudo pass issuing pulses; (H) determining whether or not the number of bit errors is equal to or less than a permissible bit number if the number of times of applying the writing pulse is equal to the number of pseudo pass issuing pulses; (I) returning a pass to the memory controller as a status by the memory if the number of bit errors is equal to or less than the permissible bit number; (J) determining whether or not the number of times of applying the writing pulse reaches a predetermined number if the number of bit errors exceeds the permissible bit number; (K) repeating (C) to (J) if the number of times of applying the writing pulse is equal to or less than the predetermined number; and (L) returning a fail to the memory controller as a status by the memory if the number of times of applying the writing pulse exceeds the predetermined number.