Patent ID: 7362835

Claim:
A clock generator circuit for generating an output clock signal, comprising: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal; wherein the random frequency code generator comprises: a random signal generator, being clocked by the first clock signal for generating a control signal randomly; and a second multiplexer electrically connected to the random signal generator and the accumulator, for selecting one preset frequency code from a plurality of preset frequency codes to be the frequency code according to the control signal.