Patent ID: 8481424

Claim:
A method for manufacturing a multilayer printed wiring board, comprising: forming a multilayer printed wiring board structure comprising a first buildup portion and a second buildup portion, the first buildup portion comprising a plurality of insulating layers, a plurality of conductor layers and a plurality of first viaholes formed in the insulation layers and electrically connecting the conductor layers through the insulation layers such that the first viaholes are formed in the insulating layers of the first buildup structure, respectively, the second buildup portion comprising a plurality of insulating layers, a plurality of conductor layers and a plurality of second viaholes formed in the insulation layers and electrically connecting the conductor layers through the insulation layers such that the first viaholes are tapered toward the second viaholes, the second via holes are tapered toward the first viaholes, and the second viaholes are formed in the insulating layers of the second buildup portion, respectively, wherein the first and second viaholes are formed by plating a plurality of openings formed after lamination of respective ones of the insulating layers of the first and second buildup portions, and each of the insulating layers in the first and second buildup portion is about 100 μm or less in thickness.