Patent ID: 7327607

Claim:
A method of operating a nonvolatile memory array storing data as charge storage states, the nonvolatile memory including nonvolatile memory cells arranged in columns, each of the nonvolatile memory cells including a first and a second current carrying node in a substrate region, and including a charge storage structure, and one or more dielectric structures at least partly between the charge storage structure and a source of gate voltage and at least partly between the substrate region and the charge storage structure, the method comprising: performing one or more memory operations applying a bit line bias to a bit line, comprising: electrically connecting the bit line bias to a first end of a column of nonvolatile memory cells, the column arranged in a series such that adjacent first and second current carrying nodes of adjacent memory cells in the column are electrically connected; and electrically connecting the bit line bias to a second end of the column of nonvolatile memory cells; and performing a second set of one or more memory operations applying the bit line bias to the bit line, comprising: electrically connecting the bit line bias to the first end of the column of nonvolatile memory cells, without electrically connecting the bit line bias to the second end of the column of nonvolatile memory cells, wherein the first and second ends of the column correspond to consecutive pass transistors in the column.