Patent ID: 7969699

Claim:
A trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being an NMOS transistor being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprising: a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during an ESD event, and to produce a second predetermined voltage complementary to the first predetermined voltage during a normal operation, wherein the voltage sensing circuit comprises a capacitor connected to the bonding pad and a resistor connected between the capacitor and a ground; and a voltage converting circuit coupled to a first node between the capacitor and the resistor for converting the first predetermined voltage to a third predetermined voltage for turning on the NMOS transistor during an ESD event, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the NMOS transistor during a normal operation, the voltage converting circuit including: an even number of inverters connected in series between the first node and a gate of the NMOS transistor; and a positive feedback circuit connected between the gate of the NMOS transistor and the first node for preventing a leakage current flowing through the NMOS transistor during a normal operation.