Patent ID: 8451887

Claim:
A phase interleaving control method for a multi-channel regulator system including a plurality of pulse width modulation integrated circuits connected in series, each said pulse width modulation integrated circuit determining a pulse width modulation signal for a respective channel, the method comprising operating each said pulse width modulation integrated circuit to perform the steps of: (A) during a first state detecting if any external clock appears at an input pin of said pulse width modulation integrated circuit; (B) if a first clock is detected in the step A, then performing the steps of: transiting to a second state for a slave mode; triggering the pulse width modulation signal with the first clock; and generating a second clock synchronous to and phase interleaved with the first clock, and outputting the second clock through an output pin of said pulse width modulation integrated circuit; and (C) if no external clock is detected in the step A, then performing the steps of: transiting to a third state for a master mode; triggering the pulse width modulation signal with an internal clock of said pulse width modulation integrated circuit; and generating a third clock synchronous to and phase interleaved with the internal clock, and outputting the third clock through said output pin.