Patent ID: 6947513

Claim:
CMOS transmitter carrier circuitry configured to receive a digital clock signal, the circuitry comprising: a phase locked loop including a voltage controlled oscillator configured to multiply the frequency of the digital clock signal by a predetermined multiple and control circuitry to maintain a desired frequency, the phase locked loop having an output providing a transmitter carrier, the control circuitry including a first charge pump coupled to a start-up circuit and configured to pump a frequency of the voltage controlled oscillator in response to a start-up command from the start-up circuit, and a second charge pump and configured to selectively pump up or down the frequency of the voltage controlled oscillator in steps smaller than the steps of the first charge pump; and divider circuitry having an input coupled to the voltage controlled oscillator and receiving the multiplied frequency, the divider circuitry being configured to divide by the predetermined multiple, and the divider circuitry having an output coupled to the control circuitry.