Patent ID: 8748869

Claim:
An apparatus comprising: a first layer of a silicon material suitable as a first channel for a first circuit device on a first interface surface of a Si 1-X Ge X material; wherein the layer of silicon material is under a tensile strain caused by a lattice spacing of the silicon material being smaller than a lattice spacing of the Si 1-X Ge X material at the first interface surface, wherein X is between 0.1 and 0.3; a second layer of a Si 1-Y Ge Y material suitable as a second channel for a second circuit device on a second interface surface of the Si 1-X Ge X material; wherein the layer of Si 1-Y Ge Y material is under a compressive strain caused by a lattice spacing of the Si 1-Y Ge Y material being larger than a lattice spacing of the Si 1-X Ge X material at the second interface surface, wherein X<Y, and Y is between 0.2 and 0.6; a gate dielectric layer in contact with the silicon material and the Si 1-Y Ge Y material; and a gate electrode on the gate dielectric layer.