Patent ID: 8487643

Claim:
A substrate comprising at least one exposure unit disposed at a transverse direction and a substrate test circuit, wherein the substrate test circuit comprises: a first data-line-test line, a first gate-line-test line and a first common-electrode-line-test line, which are connected with a first panel within a single exposure unit, wherein the first data-line-test line comprises a first data-line-test input terminal and a second data-line-test input terminal, which are disposed on both sides of the exposure unit, the first gate-line-test line comprises a first gate-line-test input terminal and a second gate-line-test input terminal, which are disposed on both sides of the exposure unit, the first common-electrode-line-test line comprises a first common-electrode-line-test input terminal and a second common-electrode-line-test input terminal, which are disposed on both sides of the exposure unit, the first data-line-test input terminal, the first gate-line-test input terminal and the first common-electrode-line-test input terminal are disposed on the same side of the exposure unit, a length of a wiring from the first data-line-test input terminal to the first panel is the same as a length of a wiring from the second data-line-test input terminal to the first panel; a length of a wiring from the first gate-line-test input terminal to the first panel is the same as a length of a wiring from the second gate-line-test input terminal to the first panel; and a length of a wiring from the first common-electrode-line-test input terminal to the first panel is the same as a length of a wiring from the second common-electrode-line-test input terminal to the first panel, wherein at least one of the wiring from the first data-line-test input terminal to the first panel and the wiring from the second data-line-test input terminal to the first panel, at least one of the wiring from the first gate-line-test input terminal to the first panel and the wiring from the second gate-line-test input terminal to the first panel and at least one of the wiring from the first common-electrode-line-test input terminal to the first panel and the wiring from the second common-electrode-line-test input terminal to the first panel comprise a zigzag route.