Patent ID: 7915676

Claim:
An integrated circuit including a semiconductor component, the integrated circuit comprising: a) a first p-type region forming a body region of a field effect transistor; b) a first n-type region adjoining the first p-type region and forming a drain region of the field effect transistor, the first p-type region and the first n-type region together forming a first pn junction; and c) a further p-type region spaced apart from the first p-type region, the further p-type region adjoining the first n-type region and forming a further pn junction, wherein the first p-type region of the first pn junction and the further p-type region of the further pn junction are operably connected to an identical potential, wherein the first p-type region has a first breakdown voltage with respect to the first n-type region and the further p-type region has a further breakdown voltage with respect to the first-n type region, wherein the further breakdown voltage is less than the first breakdown voltage such that, in the case of an overloading of the semiconductor component on account of reverse biasing of the first pn junction, the further pn junction is the first to break down relative to the first pn junction wherein the field effect transistor comprises a VDMOS; wherein the intergrated circuit further comprises a second p-type region spaced apart from both the first p-type region and the further p-type region, the second p-type region being operably coupled to the first p-type region and forming a second body region for the VDMOS, the second p-type region and the first n-type region adjoining to form a second pn junction wherein the second p-type region has a second breakdown voltage with respect to the first n-type region, the further breakdown voltage being less than the second breakdown voltage.