Patent ID: 7897451

Claim:
A method, comprising: forming drain and source extension regions of a P-channel transistor; annealing said P-channel transistor to provide said drain and source extension regions of said P-channel transistor in a substantially crystalline state; forming drain and source extension regions and at least a first portion of deep drain and source regions of an N-channel transistor after annealing said P-channel transistor and while maintaining said substantially crystalline state of said drain and source extension regions of said P-channel transistor; forming a material layer above said P-channel transistor and said N-channel transistor after forming said drain and source extension regions and said first portion of the deep drain and source regions of said N-channel transistor; re-crystallizing implantation-induced damage in said drain and source extension regions and said first portion of the deep drain and source regions of said N-channel transistor by annealing said P-channel transistor and said N-channel transistor in the presence of said material layer; and forming a second portion of said drain and source regions of said P-channel transistor after re-crystallizing said implantation-induced damage in said first portion of the drain and source regions of said N-channel transistor, said second portion being deeper than said drain and source extension regions of said P-channel transistor.