Patent ID: 7254052

Claim:
A memory circuit, comprising: a CBRAM resistance memory cell connected to a bit line and a word line; the CBRAM resistance memory cell comprising (i) a CBRAM resistance element, the resistance of which is set by a write current for storing an item of information and (ii) a selection switch, driven via the word line, to connect a first potential to the bit line via the CBRAM resistance element; a reference resistance cell connected to the bit line and to a reference line; the reference resistance cell comprising (i) a reference resistance element having a resistance set to a resistance threshold value and (ii) a reference selection switch, driven via the reference line, to connect a second potential to the bit line via the reference resistance element; a read-out unit configured to activate the reference selection switch and the selection switch such that a memory cell current is established between the CBRAM resistance memory cell and the bit line and a reference current is established between the reference resistance cell and the bit line, whereby a memory datum is read out of the CBRAM resistance memory cell; and an evaluation unit, connected to the bit line, configured to output the memory datum based on a resulting electrical quantity evaluated from the bit line.