Patent ID: 7054874

Claim:
A method for modeling the effects of overlapping of memory references in a queuing system model, comprising: processing a memory reference during execution of a queuing system model that simulates performance of a memory system; determining if the memory reference generates a cache miss; if the memory reference generates a cache miss, modeling the cache miss in a manner that accounts for possible overlapping of the cache miss with other memory references and other processor operations; and wherein modeling the cache miss involves, forwarding the memory reference to portions of the gueuing system model associated with lower levels of a memory hierarchy, probabilistically determining whether or not the cache miss can be overlapped with other memory references, wherein cache misses are modeled as either completely overlapping or non-overlapping, and wherein partial overlaps are accounted for by adjusting the probabilities of complete overlap and non-overlap, if the cache miss can be overlapped, resuming processing of subsequent memory references without waiting for the forwarded memory reference to return, and if the cache miss cannot be overlapped, waiting for the forwarded memory reference to return before processing subsequent memory references.