Patent ID: 7533402

Claim:
A satellite set-top box decoder apparatus formed on a single integrated circuit chip for simultaneously servicing a plurality of independent programs for display on independent display devices, comprising: a first processor for demultiplexing multiple input transport streams to generate a first video stream corresponding to a first program, and to further generate a second video stream corresponding to a second program; a Program Clock Recovery (PCR) circuit for extracting first PCR data from the transport streams corresponding to the first program, and for extracting second PCR data from the transport streams corresponding to the second program, a clock circuit responsive to the first and second PCR data for generating a first clock signal that is synchronized to a program clock for the first program and for generating a second clock signal that is synchronized to a program clock for the second program, the clock circuit including a dual phase locked loop (PLL) circuit in which a first multiplexer selects one of a plurality of first control words provided from extracted first PCR data and in which a second multiplexer selects one of a plurality of second control words provided from extracted second PCR data to separately control outputs of the PLL, wherein the first clock signal and the second clock signal are synchronized to corresponding first and second programs, but not to each other, in order to have independently timed first and second clock signals; a video decode circuit for simultaneously (1) decoding the first video stream under control of the first clock signal to render a signal, and (2) decoding second video stream under control of the second clock signal to render a second decoded video signal; and a video converter for simultaneously converting the first and second decoded video signals into analog video form respectively based on first and second clock signals in order to produce simultaneously two independent video signals for display on first and second display devices, in which the first and second video signals are independently and simultaneously generated from the same integrated circuit chip.