Patent ID: 7842566

Claim:
A method of manufacturing a semiconductor device, comprising: forming a semiconductor fin having a top surface and a sidewall, the top surface having a crystal plane {110} and the sidewall having a crystal plane {100}; forming a dielectric layer pattern extending along the semiconductor fin; forming a gate dielectric layer including a first portion on the sidewall of the semiconductor fin and a second portion on the top surface of the semiconductor fin simultaneously, such that the second portion is thicker than the first portion; and forming a gate electrode on the first and second portions, a lowermost surface of the gate electrode being lower than an uppermost surface of the dielectric layer pattern; wherein: forming the first and second portions includes: forming a mask pattern on the dielectric layer pattern and the top surface of the semiconductor fin to define a line region where a gate electrode will be formed, the line region being substantially perpendicular to the semiconductor fin; partially etching the exposed dielectric layer pattern using the mask pattern as an etch mask to expose the sidewall of the semiconductor fin; and thermally oxidizing the top surface and sidewall of the semiconductor fin having the different crystal planes.