Patent ID: 8214582

Claim:
A non-volatile memory system comprising: a non-volatile memory cell array having a plurality of multi-level cells forming a first area and a plurality of single-level cells forming a second area and configured to store write data at one of the first area and the second area; and a flash transition layer (FTL) configured to determine whether the write data should be stored in the first area or the second area based on a write data characteristic signal defined by an update characteristic of the write data, wherein the update characteristic of the write data is the number of access of an address associated with the write data, the FTL comprises a plurality of entries including at least one store entry and at least one empty entry, the FTL stores the number of access of the address to the empty entry, if there is no store entry corresponding to the address, and the FTL stores the number of access to the store entry selected in response to a least recently used (LRU) value, if there is no store entry corresponding to the address and no empty entry.