Patent ID: 8315303

Claim:
An apparatus for phase pre-emphasis, the apparatus comprising: a pattern detector configured to detect one or more patterns in data to be transmitted in a serial data signal; a modulator configured to stretch a pulse width of one or more bits of the one or more detected patterns in the serial data signal, wherein the modulator is configured to modify a clock signal to generate the modified clock signal, wherein the modified clock signal has a wider clock pulse than the clock signal for the one or more bits of the one or more detected patterns, wherein the clock signal and the modified clock signal are half rate, the modulator further comprising: a clock driver wherein an output of the clock driver is the clock signal; a pulse width modulator circuit having an output in parallel with the output of the clock driver such that when enabled, the output of the pulse width modulator circuit is in contention with the output of the clock driver; a control circuit configured to enable the output of the pulse width modulator circuit for an emphasis period that encompasses a half clock cycle to be stretched, at least a portion of a preceding half cycle, and at least a portion of a subsequent half cycle; and a buffer circuit with an input coupled to both the output of the clock drive and the output of the pulse width modulator circuit; and a serializer configured to convert the data from parallel form to serial form, wherein the serializer is configured to receive a modified clock signal as an input for timing of the serial data signal.