Patent ID: 8072798

Claim:
A semiconductor memory device, comprising: a bit line pair having a first bit line and a second bit line; a word line; and a memory cell formed between the bit line pair, wherein the memory cell comprises; an inverter pair including a first inverter and a second inverter which are cross-coupled to each other, a first transfer transistor provided between the first bit line and an output terminal of the first inverter and including a first front gate and a first back gate, the first front gate connected to the word line, the first back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are connected, a second transfer transistor provided between the second bit line and an output terminal of the second inverter and having a second front gate and a second back gate, the second front gate connected to the word line, the second back gate connected to a second node to which an output terminal of the second inverter and an input terminal of the first inverter are connected, a first driver transistor including a first gate connected to the second node, and one end of a first current path connected to a ground voltage, and a first read transistor including a third front gate and a third back gate, the third front gate connected to the word line, the read transistor including one end of a second current path connected to another end of the first current path, and another end of the second current path connected to the first bit line, wherein the third back gate of the first read transistor is connected to a first column selection line.