Patent ID: 8227295

Claim:
A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, comprising: providing at least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) comprising a tip extending from said top semiconductor surface to protrude beyond said bottom surface to a tip length, said tip having an outer dielectric tip liner, and an electrically conductive portion within said outer dielectric tip liner; applying a compliant layer, thicker than said tip length, to said bottom surface of said IC die; thinning said compliant layer to expose said dielectric tip liner from said distal portion of said tip; removing said dielectric tip liner from a distal portion of said tip to form an exposed electrically conductive tip portion; depositing a solder material on said exposed electrically conductive tip portion of said tip; patterning said solder material using a resist material into an isolated region centered over said tip; and reflowing and coalescing said solder material to form a solder bump on said exposed electrically conductive tip portion of said tip.