Patent ID: 7626855

Claim:
A semiconductor memory device comprising: first and second PMOS transistors formed on an n-type well; first and second NMOS transistors formed on a p-type well; a first transfer MOS transistor, a source of the first transfer MOS transistor being electrically connected to a first data line, and a drain of the first transfer MOS transistor being electrically connected to a drain of the first PMOS transistor, a source of the first NMOS transistor, a gate of the second PMOS transistor and a gate of the second NMOS transistor; a second transfer MOS transistor, a source of the second transfer MOS transistor being electrically connected to a second data line, and a drain of the second transfer MOS transistor being electrically connected to a drain of the second PMOS transistor, a source of the second NMOS transistor, a gate of the first PMOS transistor and a gate of the first NMOS transistor; a first word line electrically connected to a gate of the first transfer MOS transistor; a second word line electrically connected to a gate of the second transfer MOS transistor; and a drive circuit for controlling voltages applied to at least the n-type well, the sources of the first and second PMOS transistors, the drains of the first and second NMOS transistors, the first word line, the second word line, the first data line, and the second data line, wherein, during a write operation of the first PMOS transistor, the drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to the n-type well as well as the sources of the first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and the first data line, such that the drive circuit performs the write operation by accumulating electrons in a gate insulating film of the first PMOS transistor by a drain avalanche hot electron injection.