Patent ID: 8629506

Claim:
A complementary metal oxide semiconductor (CMOS) structure comprising: a first FET having a first polarity located upon a first active region of a semiconductor substrate, said first FET including a first gate that is located upon a first gate dielectric portion, said first gate dielectric portion is located only upon an upper horizontal surface of said semiconductor substrate in the first active region; a second FET having a second polarity different than the first polarity located upon a second active region of the semiconductor substrate separated from the first active region of the semiconductor substrate by an isolation region, said second FET including a second gate that is located upon a second gate dielectric portion, said second gate dielectric portion is located only upon another upper horizontal surface of said semiconductor substrate in the second active region, wherein: a third gate dielectric portion is located atop the isolation region and is positioned between and in direct contact with the first and the second gate dielectric portions; the first gate and the second gate are co-linear; an endwall of the first gate and an endwall of the second gate terminate facing each other over the isolation region and are entirely bare; and a spacer is present adjacent or adjoining a sidewall of the first gate and a sidewall of the second gate.