Patent ID: 8755211

Claim:
A semiconductor memory device comprising: a first cell array region; a second cell array region arranged in a row direction; a shunt region arranged between the first cell array region and the second cell array region; a first dummy bit line region arranged between the first cell array region and the shunt region; a second dummy bit line region arranged between the second cell array region and the shunt region; a first silicon pillar including a first pair of columnar portions and a first connection portion in the first dummy bit line region, each of the first columnar portions extending vertically with respect to a semiconductor substrate, the first connection portion connecting lower ends of the first pair of columnar portions; a second silicon pillar including a second pair of columnar portions and a second connection portion in the shunt region, each of the second columnar portions extending vertically with respect to the semiconductor substrate, the second connection portion connecting lower ends of the second pair of columnar portions, the second silicon pillar being adjacent to the first silicon pillar in the row direction; a source line connected to one of the pair of columnar portions of each of the first silicon pillar and the second silicon pillar; a first interconnection connected to the other of the first pair of columnar portions of the first silicon pillar, the first interconnection formed above the first silicon pillar on the same level as that of the source line; a second interconnection connected to the other of the second pair of columnar portions of the second silicon pillar, the second interconnection formed above the second silicon pillar on the same level as that of the source line; and a first dummy bit line connected to the first interconnection, the first dummy bit line formed above the first interconnection, wherein the first interconnection and the second interconnection are connected on the same level.