Patent ID: 8819507

Claim:
A method for chip circuit design with a built-in self test mechanism comprising: isolating primary outputs via a shadow register configured to capture a non-register primary output, wherein the non-register primary output is one of the primary outputs not resulting from a register; isolating primary inputs via an isolation logic device configured to capture a primary input, wherein the shadow register is configured to provide stimulus to the isolation logic device; selecting registers of the circuit for forming a test path, the selected registers including the shadow register and primary output registers; identifying n of the registers in the test path for outputting test response values, wherein n is an integer greater than 1; inserting an output tap from each one of the n identified registers in the test path into a signature register for forming n signature inputs from n output taps, wherein the n signature inputs together form a signature for comparing against one or more stored values in the signature register, wherein the output taps are substantially evenly spaced among the selected registers in the test path; and connecting the selected registers in a circular loop, wherein an input to a particular one of the selected registers is an output of a preceding one of the selected registers.