Patent ID: 7683679

Claim:
A frequency adjusting circuit comprising: an asynchronous finite state machine (AFSM) configured as a counter having an input that receives an input clock signal, wherein the AFSM provides a division factor from a plurality of phase signals and phase difference between each of the phase signals relative to one another, wherein each phase signal is a divided-down representation of the input clock signal, and wherein each phase signal is phase-shifted by a predetermined amount with respect to another of the phase signals; and programmable circuitry that generates divided down representation of the input clock signal as an output clock signal according to dynamic divide ratio information, the division factor, and the phase differences, wherein the programmable circuitry includes a down counter that receives a least a portion of the dynamic divide down ratio information and that counts down from the values of the divide ratio information in response to at least one of the phase signals produced by the AFSM.