Patent ID: 7898018

Claim:
A non-volatile memory cell including: a semiconductor body; a first memory-transistor well disposed within the semiconductor body; a first switch-transistor well disposed within the semiconductor body to a first side of the first memory-transistor well and electrically isolated from the first memory-transistor well by: a first isolation well region formed in the semiconductor body between the first memory-transistor well and the first switch transistor well and having a doping concentration different from the semiconductor body, and an underlying deeper isolation well region formed in the semiconductor body beneath the first isolation well region and having a different dopant concentration from the semiconductor body and the first isolation well region; a first memory-transistor formed within the first memory-transistor well and including spaced-apart source and drain regions; a first switch-transistor formed within the first switch-transistor well region and including spaced-apart source and drain regions; a first floating gate insulated from and self aligned with the source and drain regions of the first memory-transistor and the first switch transistor; and a first control gate disposed above and self aligned with respect to the first floating gate and with the source and drain regions of the first memory-transistor and the first switch-transistor.