Patent ID: 8914799

Claim:
A system, comprising: a processor; a memory; and a plurality of instructions stored in the memory that, when executed by the processor, perform the steps of: generating a plurality of threads within a parallel region of an application; setting a counter equal to a quantity of the plurality of threads; for each one of the plurality of threads: assigning an implicit task; executing the implicit task; upon encountering a task construct, during execution of the implicit task, for an explicit task: determining that a first task queue of a plurality of task queues is not full; setting an execution mode of the explicit task as an explicit asynchronous task within the task construct based on the determination that the first task queue is not full; converting at least one ancestor stack task to a heap task based on a determination that the explicit asynchronous task is descended from the at least one ancestor stack task; generating the explicit asynchronous task; adding the explicit asynchronous task to the first task queue, wherein the first task queue corresponds to the one of the plurality of threads, wherein each of the plurality of task queues corresponds to one of the plurality of threads, and wherein the explicit asynchronous task is executed by allocating a data environment data structure for the explicit asynchronous task on a heap of a host routine; and incrementing the counter by one.