Patent ID: 7256498

Claim:
A resistance-reduced semiconductor device, comprising: a resistance-reduced transistor, comprising: a gate stack on a silicon-containing substrate; a pair of source/drain regions in the silicon-containing substrate, oppositely adjacent to the gate stack; a metallized bilayer overlying each source/drain region to thereby reduce a resistance thereof, wherein the metallized bilayer comprises a metal top layer; a first dielectric layer having a conductive contact, overlying the resistance-reduced transistor; a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact electrically form a conductive pathway down to the top metal layer over one of the source/drain regions; a third dielectric layer having a second conductive feature, overlying the second dielectric layer; and a first conductive cap layer partially overlying the first conductive feature, wherein the first conductive cap layer exposes a portion of the top surface of the first conductive feature to thereby contact the second conductive feature directly and the first conductive feature.