Patent ID: 7032073

Claim:
Cache apparatus, comprising: first and second cache memories, coupled to receive and hold context information from an external memory with respect to a plurality of tasks, each task being activated by one or more activating events, so that the context information is available for access by a processor in performing the tasks; and a mapper, which is coupled to receive a classification of the tasks as fast and slow tasks, and which is adapted, upon receipt of one of the activating events for one of the fast tasks to be performed by the processor, to cause the context information with respect thereto to be received in the first cache memory, and upon receipt of one of the activating events for one of the slow tasks to be performed by the processor, to cause the context information with respect thereto to be received in the second cache memory; and a rate estimator module, which is adapted to compute respective rates of the tasks performed by the processor, so that the tasks are classified as the fast and the slow tasks, wherein the rate estimator module comprises: a rate estimator for each of the plurality of tasks, which is adapted to calculate a current-rate for a respective task, responsive to a previous-rate of the respective task, a first number of activating events received for the respective task, and a filter parameter; and an interface rate minimizer for the plurality of tasks, which is adapted to calculate the filter parameter, responsive to a second number of activating events received for the plurality of tasks and a number of accesses to the external memory.