Patent ID: 8441057

Claim:
An embedded memory device comprising: a first electrically conductive layer; a first electrically insulating layer over the first electrically conductive layer; an excavated feature in the first electrically insulating layer that extends through the first electrically insulating layer to the first electrically conductive layer, the first electrically conductive layer extending under all of the excavated feature and further extending beyond the excavated feature in at least a first dimension so as to also extend under a portion of the first electrically insulating layer at a first side of the excavated feature as well as under a portion of the first electrically insulating layer at an opposing, second side of the excavated feature; and a MIM capacitor in the excavated feature, the MIM capacitor comprising: a second electrically conductive layer located in the excavated feature adjacent to and electrically connected to the first electrically conductive layer; a second electrically insulating layer located in the excavated feature interior to the second electrically conductive layer; and a third electrically conductive layer located in the excavated feature interior to the second electrically insulating layer, wherein: the first electrically conductive layer acts as a floor of the excavated feature and the excavated feature further comprises sidewalls extending away from the floor; the second electrically conductive layer covers the floor and a first portion of the sidewalls; and the second electrically insulating layer covers the second electrically conductive layer and a second portion of the sidewalls.