Patent ID: 7157369

Claim:
A method of manufacturing a semiconductor device including a transistor formed on a semiconductor substrate and a capacitance element formed on said transistor and connected thereto, comprising: forming a transistor on a semiconductor substrate; forming a first interlayer dielectric film that covers said transistor; forming a first connection hole and a second connection hole in said first interlayer dielectric film so as to reach an upper face of said transistor; forming a continuous conductive layer in said first connection hole, in said second connection hole and on said first interlayer dielectric film, to thereby form a first conductive plug in said first connection hole, a second conductive plug in said second connection hole, and a surface conductive layer on said first interlayer dielectric film; forming a resist layer in a region on said surface conductive layer including right above said first conductive plug but excluding right above said second conductive plug; performing anisotropic etching on said surface conductive layer utilizing said resist layer as a mask to form a bit line connected to said first conductive plug and to expose an upper face of said second conductive plug; forming a second interlayer dielectric film on said first interlayer dielectric film; forming a third conductive plug connected to said second conductive plug in said second interlayer dielectric film; and forming a capacitance element connected to said third conductive plug on said second interlayer dielectric film.