Patent ID: 8088680

Claim:
A method for fabricating an integrated circuit, comprising: fabricating a gate electrode level region that forms part of a gate electrode level of the integrated circuit to include at least three linear conductive segments each fabricated to have a respective length and a respective width when viewed from above, wherein a size of the length of a given linear conductive segment is greater than or equal to a size of the width of the given linear conductive segment, and wherein the at least three linear conductive segments are fabricated to have their lengths extend in a first direction in a parallel manner, and wherein each of the at least three linear conductive segments is fabricated to have a substantially equal length as measured in the first direction, and wherein the at least three linear conductive segments are positioned in a side-by-side manner according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein at least one of the at least three linear conductive segments forms both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type.