Patent ID: 7120216

Claim:
A data/clock recovery circuit comprising: an edge detector for generating edge position information by using a receiver output as a clock signal, and by comparing phases of a plurality of clock signals constituting a clock signal group with a phase of an edge of the receiver output; a clock selection signal generating circuit for generating, using the receiver output as a clock signal, a clock selection signal in response to the edge position information generated by said edge detector, the clock selection signal causing an optimum clock signal for synchronizing the receiver output to be selected from the clock signal group, said clock selection signal generating circuit generates the clock selection signal in response to the positive edge position information and the negative edge position information; a clock selection circuit for selecting a clock signal from the clock signal group in response to the clock selection signal generated by said clock selection signal generating circuit, and for outputting a selected clock signal as a recovered clock signal; and a synchronizing circuit for synchronizing the receiver output using the recovered clock signal output from said clock selection circuit, and for outputting the synchronized receiver output as a synchronized data signal, wherein said clock selection signal generating circuit comprises means for generating the clock selection signal in response to the positive edge position information and the negative edge position information such that an update frequency of the clock signal is high when a phase difference between the positive edge and the negative edge is large, and is low when the phase difference is small.