Patent ID: 7470616

Claim:
A method of forming an interconnect structure, comprising: forming an oxide layer over a surface of a semiconductor substrate having a metallic contact formed in the substrate surface, wherein an upper surface of the metallic contact is coplanar with an upper surface of the oxide layer; forming a nitride capping layer over the oxide layer; forming an interlevel dielectric (ILD) layer over the nitride capping layer; forming a hard mask layer over the ILD layer; sequentially forming an organic planarizing layer (OPL), anti reflective coating (ARC) layer and photoresist (PR) layer over the hard mask layer; etching first and second openings through the PR, ARC, OPL, hard mask and ILD layers down to the nitride capping layer, wherein the first opening is aligned to the metallic contact in the underlying substrate surface; etching the nitride capping layer exposed at bottoms of the first and second openings using the PR, ARC or OPL layer as an etch mask to a portion of the upper surface of the metallic contact through the first opening and to expose at least a portion of the upper surface of the oxide layer through the second opening; stripping away any remaining portion of the PR, ARC and OPL layers to expose the hard mask layer; subsequent to the etching of the nitride capping layer; and performing a controlled oxide gouging of the exposed surface of the oxide layer in the second opening to avoid punch through of the oxide layer to an underlying layer or feature.