Patent ID: 7365404

Claim:
A semiconductor device comprising: a substrate; a first conductive type well region formed in the substrate; first and second source/drain regions constructed of a second conductive type diffusion layer formed on the well region; a gate insulator formed in a region located between the first source/drain region and the second source/drain region; a gate electrode formed on the gate insulator; first silicide reaction blocking regions formed in upper portions of the gate electrode and the first and second source/drain regions to block a silicide reaction in a thickness direction of the substrate; a sidewall spacer on each side of the gate electrode as viewed cross sectionally; wherein the first silicide reaction blocking regions are at least partially formed laterally outwardly of the sidewall spacer on each side of the gate electrode; and wherein a concentration of silicide reaction high-melting-point metal atoms is not higher than 1×10 16 cm −3 (i) at an interface between the gate insulator and the gate electrode, and/or (ii) at an interface between at least one of first and second source/drain regions and the well region.