Patent ID: 8717837

Claim:
A memory module comprising: a circuit board; a first plurality of memory components disposed on the circuit board, each of the memory components having an address/control input, a clock input, a data input and a strobe input; a termination structure disposed on the circuit board; an address/control signal path that extends from an edge of the circuit board to the termination structure, the address/control signal path being coupled along its length to the address/control input of each of the memory components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components; a clock signal path extending from the circuit board edge and coupled along its length to the clock input of each of the memory components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective memory components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the memory components, the clock signal indicating to the memory components respective times at which to sample the control signals arriving at their address/control inputs; a plurality of data signal paths, each extending from the circuit board edge to the data input of a respective one of the memory components and each including a first plurality of data signal conductors to convey a write data value and at least one mask signal conductor to convey a write mask signal that indicates whether the write data value is to be stored within the one of the memory components to which the data signal path extends; and a plurality of strobe signal paths that extend from the circuit board edge to respective strobe inputs of the memory components, each of the strobe signal paths to convey a strobe signal that indicates, to a respective one of the memory components, that the write data value is present on the data signal path coupled to the data input of the one of the memory components.