Patent ID: 8918688

Claim:
An integrated circuit comprising: A. functional data input leads and functional data output leads; B. a test data in lead, a test clock in lead, a test mode select lead, and a test data out lead; C. test access port controller circuitry having a test clock input connected to the test clock lead, a test mode select input connected to the test mode select lead, an instruction register control bus output, and a data register control bus output that includes a ShiftDR lead; D. instruction register circuitry having a test data input connected to the test data in lead, an instruction register control bus input connected to the instruction register control bus output, an IR gate control output, a data register mode output, and an AUX gate control output; E. IR gate circuitry having a data register control bus input connected to the data register control bus output, an AUX gate bus input, and a gated data register control bus output; F. data register circuitry having scan cells coupled to the functional input leads and the functional output leads, a test data input connected to the test data in lead, a test data output connected to the test data out lead, a data register mode input connected to the data register mode output, and a gated data register control bus input connected to the gated data register control bus output; G. auxiliary data register control leads that include a Capture lead; and H. AUX gate circuitry having AUX data register control inputs connected to the auxiliary data register control leads, a data register control bus input connected to the data register control bus output, and an AUX gate bus output connected to the AUX gate bus input, the AUX gate circuitry including a first gate having an AUX enable input coupled to the AUX gate control output, a Capture input coupled to the Capture lead, and a gated Capture output, and the AUX gate circuitry including a second gate having a ShiftDR input coupled to the ShiftDR lead, a gated Capture input connected to the gated Capture output, and a Shift-1 output included in the AUX gate bus output.