Patent ID: 7842587

Claim:
A semiconductor fabrication process, comprising: forming, using molecular beam epitaxy, a gate dielectric layer overlying a wafer substrate, wherein the substrate includes at least one layer of a III-V semiconductor compound and wherein the gate dielectric layer includes a compound comprising an oxygen element and a second element wherein the second element is present in the III-V semiconductor compound; patterning the gate dielectric layer to produce a gate dielectric structure having a substantially vertical sidewall; forming a contact structure overlying said wafer substrate and laterally displaced from the gate dielectric structure, wherein the contact structure comprises at least one metal and wherein a lateral separation between the contact structure and the gate dielectric structure defines a gap; heat treating the contact structure to produce an alloy region within the semiconductor substrate, wherein the alloy region underlies the contact structure and extends across a portion of the wafer substrate underlying the gap; and forming a capping layer overlying the wafer.