Patent ID: 7718520

Claim:
A method for fabricating a semiconductor integrated circuit device, the method comprising: forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate, wherein each preliminary gate electrode structure comprises a gate electrode and a gate capping film formed on the gate electrode; forming first spacers on sidewalls of the preliminary gate electrode structures; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region, wherein each selective epitaxial film is formed on a region of the semiconductor substrate exposed between gate electrodes; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region, thereby forming transistors in the cell array region and the peripheral circuit region; forming a first interlayer insulating film on the semiconductor substrate; patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions and self-aligned between gate electrodes; forming a first ohmic film on the elevated source/drain regions exposed through the first openings; forming a first barrier film on the first ohmic film; forming a metal film on the first barrier film; and removing a first portion of the metal film, a first portion of the first barrier film, and a first portion of the first ohmic film to form a plurality of self-aligned contact pads, wherein each self-aligned contact pad is node-isolated and the first portion of the metal film comprises at least one second portion of the metal film disposed on at least one of the gate capping films.