Patent ID: RE40673

Claim:
A shift register comprising a plurality of stages electrically connected to each other, each of said stages comprising: a first transistor having a first control terminal, which is turned on by a signal on a predetermined level supplied from one stage to said first control terminal, and outputs said signal on a predetermined level from one end of a first electric current path to the other end of said first electric current path; a second transistor having a second control terminal, which is turned on in accordance with a voltage applied to a wiring between said second control terminal and the other end of said first electric current path of said first transistor, and outputs a first or second signal supplied from outside to one end of a second electric current path as an output signal from the other end of said second electric current path; a load for outputting a power supply voltage supplied from outside; a third transistor having a third control terminal, which is turned on in accordance with a voltage applied to a wiring between said third control terminal and the other end of said first electric current path of said first transistor, and outputs said power supply voltage, which is fed from outside through said load, from one end of a third electric current path to the other end of said third electric current path so that said power supply voltage outputted from said load is displaced to a voltage on a predetermined level; and a fourth transistor having a fourth control terminal, which is turned on in accordance with a voltage applied to a wiring between said fourth control terminal and said load, has one end of a fourth electric current path, connected to the other end of said second electric current path of said second transistor, and outputs a reference voltage from the other end of said fourth electric current path to one end of said fourth electric current path, a first value indicative of a channel-width/a channel-length of said fourth transistor being equal to or larger than a second value indicative of a channel-width/a channel-length of said second transistor.