Patent ID: 8327368

Claim:
A method for managing a simultaneous multi-threaded (SMT) enabled processor system comprising a plurality of processors each activated to simultaneously execute a plurality of hardware threads, wherein said plurality of processors include an exclusive set of processors to execute work on, said method comprising: scheduling a plurality of tasks of a single-threaded (ST) workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of said ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to run in an idle process, by: setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors; draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors; passing each said hardware thread of said exclusive set of processors to said idle process, wherein said idle process search each local run queue associated with each said hardware thread for waiting jobs and cede each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty; applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors; sending an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and responsive to detecting said remaining hardware threads ceded to said hypervisor, placing each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle process.