Patent ID: 8120974

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the same address value of an address signal; a write bit line selector to select bit lines one by one from the memory banks, respectively, at the time of writing, the bit lines performing writing simultaneously; and a read bit line selector to select a bit line at the time of reading, the bit line outputting data.