Patent ID: 7786581

Claim:
A method of manufacturing a semiconductor device, comprising: forming a diffusion barrier layer on a substrate; and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features, wherein: a first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions, wherein the diffusion barrier layer provides an electrical path between the at least two features, and the method further comprises: electro-less plating an outer conductive layer on the at least two features while the at least two features are connected by the electrical path; and after the electro-less plating, processing the diffusion barrier layer so as to interrupt the electrical path wherein: the conductive layer is plated on a surface of the features that includes one or more of copper or nickel, the conductive layer includes one or more of nickel, gold, palladium, tin, or indium, and the diffusion barrier layer includes one or more of titanium, chromium, or aluminum, and wherein the conductive layer includes: a palladium layer on the surface of each feature; a nickel layer on each palladium layer; and at least one gold layer on each palladium layer.