Patent ID: 7508640

Claim:
A method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem provided for each phase (R,S,T) and comprises a DC voltage circuit formed by two series-connected capacitors, where the DC voltage circuit comprises a first principal connection and a second principal connection and a subconnection formed by the two adjacent and interconnected capacitors, and which said converter subsystem has a first, a second, a third and a fourth actuatable bidirectional power semiconductor switch and a fifth and a sixth power semiconductor switch, the first, second, third and fourth power semiconductor switches being connected in series and the first power semiconductor switch being connected to the first principal connection and the fourth power semiconductor switch being connected to the second principal connection, and where the fifth and sixth power semiconductor switches are connected in series, the junction between the fifth power semiconductor switch and the sixth power semiconductor switch is connected to the subconnection, the fifth power semiconductor switch is connected to the junction between the first power semiconductor switch and the second power semiconductor switch, and the sixth power semiconductor switch is connected to the junction between the third power semiconductor switch and the fourth power semiconductor switch, in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches or through the first and fifth power semiconductor switches, and the bottom fault current path running through the second, third, fourth and fifth power semiconductor switches or through the fourth and sixth power semiconductor switches, and in which the actuatable bidirectional power semiconductor switches are switched on the basis of a fault switching sequence, wherein the fault switching sequence in the event of detection of the top or the bottom fault current path (A, B) is followed by the detection's accompanying switching status of each actuatable bidirectional power semiconductor switch being recorded, wherein in the event of detection of the top fault current path (A) the first power semiconductor switch and then the third power semiconductor are turned off, and wherein in the event of detection of the bottom fault current path (B) the fourth power semiconductor switch and then the second power semiconductor are turned off.