Patent ID: 6882376

Claim:
A method of manufacturing an array panel for a liquid crystal display device, comprising: forming a gate line and a gate electrode on a substrate using a first mask; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a metal layer on the substrate in this order; forming an active layer, an ohmic contact layer, a data line, a source electrode, and a drain electrode using a second mask; forming a passivation layer using a third mask; and forming a pixel electrode on the passivation layer using a fourth mask, wherein a channel area between the source electrode and the drain electrode has a “U” shape defining two bending portions, and wherein the second mask includes a plurality of blocking patterns and a fine pattern, the blocking patterns corresponding to the data line, the source electrode, and the drain electrode, and the fine pattern corresponding to the channel area, and the blocking patterns and the fine pattern forming first and second slits such that the slit neighboring the drain electrode has widths at the two bending portions narrower than widths at portions between the two bending portions of the first and second slits.