Patent ID: 8151128

Claim:
An apparatus that supplies power in a computer system, comprising: a power adapter coupled to a source of electrical power; a set of power consumers coupled to a power bus in the computer system; a full-power mechanism coupled between the power adapter and the power bus, wherein the full-power mechanism supplies power for the power consumers while the computer system is operating in a full-power mode; and a low-power mechanism coupled between the power adapter and the power bus in parallel with the full-power mechanism, wherein the low-power mechanism supplies power for the power consumers while the computer system is operating in a low-power mode, and wherein the low-power mechanism comprises a switching element coupled in series with a voltage-reduction mechanism that reduces the voltage to a level suitable for the power consumers; wherein the full-power mechanism and the low-power mechanism are both enabled for a predetermined range of an output current while supplying power to the power consumers, and wherein, as the computer system transitions from the low-power mode to the full power mode, the low-power mechanism is disabled upon detecting that the output current is at a first predetermined threshold current within the range.