Patent ID: 8488657

Claim:
A system comprising: a first circuit comprising: a data transmitter circuit that transmits digital data based on a first clock signal; and a sync generator that outputs a sync signal based on the first clock signal; and a digital to analog converter circuit comprising: a data receiver circuit that latches the digital data based on a second clock signal; a digital to analog converter core that receives an output of the data receiver circuit; and a delay locked loop circuit that determines a delay based on the second clock signal and the sync signal and that outputs the first clock signal to the first circuit based on the second clock signal and the delay, wherein the delay locked loop circuit comprises: an in-phase/quadrature (I/Q) clock generator that receives the second clock signal and that generates I and Q signals; a phase detector that receives the sync signal and the second clock signal and that generates up and down signals, wherein the sync signal comprises a random bit; and a loop filter that receives the up and down signals; a phase interpolator that generates a fourth clock signal based on the I and Q signals and an output of the loop filter; and a clock divider that receives the fourth clock signal and that outputs the first clock signal.