Patent ID: 7058119

Claim:
A parallel architecture digital filter receiving p input signals (I 0 , . . . , I i , . . . . I p−1 ) and delivering p output signals (S 0 , . . . , S 1 , . . . , S p−1 ) which are the sums of the input signals weighted with M coefficients (C 0 , C 1 , . . . , C M−1 ), this filter comprising p parallel channels (V 0 , . . . , V i , . . . , V p−1 ) receiving the input signals (I 0 , . . . , I i , . . . , I p−1 ), characterized in that it comprises r+1 stages (E 0 , . . . , E j , . . . , E r ), where r is the integer portion of ratio (M+p−2)/2, the stage of rank j delivering p intermediate signals (R 0 j , . . . R 1 j , . . . R p−1 ) which are the weighted sums of the input signals defined by: R i j = ∑ q = 0 p - 1 ⁢ ⁢ ( C M - 1 - q + i - jp ) ⁢ I q + jp the filter further comprising a summing means receiving said intermediate signals (R i j ) and delivering p sums defined by: S i = ∑ j = 0 r ⁢ ⁢ R i j these p sums forming p output signals (S 0 , . . . , S i , . . . S p−1 ).