Patent ID: 8649473

Claim:
An apparatus to receive a burst data signal having data edges and corresponding to burst data including an initial portion, the apparatus comprising: an input circuit configured to receive an electrical signal and output an input signal; a reference data signal generator configured to generate a reference data signal having reference edges; a clock data recovery (CDR) circuit configured to generate a clock signal having clock edges, the CDR circuit having a first mode that attempts to synchronize the clock edges with the reference edges, and a second mode that attempts to synchronize the clock edges with the data edges and to recover data from the input signal based on the clock signal; a detection circuit configured to detect the initial portion in the data recovered from the input signal; and a controller configured to conduct a process including following steps in sequence: setting the CDR circuit in the first mode to synchronize the clock edges with the reference edges; setting the CDR circuit in the second mode while supplying the data recovered from the input signal to the detection circuit; keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the data; and initiating a next cycle of the process when the detection circuit does not detect the initial portion in the data within a predetermined time period, wherein the CDR circuit includes a clock phase moving circuit that temporarily moves a phase of the clock signal to a predetermined direction when the process proceeds from the step of setting the CDR circuit in the first mode to the step of setting the CDR circuit in the second mode.