Patent ID: 6888748

Claim:
A latching circuit comprising: a first p-channel transistor having a first drain, a first gate, and a first source, said first drain operatively connected to a source of a first supply voltage; second and third p-channel transistors having respective second and third drains, second and third gates, and second and third sources, said second and third drains mutually operatively connected to said first source; first and second n-channel transistors having respective fourth and fifth drains, fourth and fifth gates, and fourth and fifth sources, said fourth drain operatively connected to said second and third sources, said fourth source operatively connected to said fifth drain, said fifth source operatively connected to a source of a second ground voltage, said fourth gate operatively connected to said second gate; an inverter having an input operatively connected to said fourth drain and an input operatively connected to said third and fifth gates; and a third n-channel transistor having a sixth drain, a sixth gate, and a sixth source said sixth source operatively connected to said input of said inverter, said third n-channel transistor adapted to provide a conductive path between said sixth drain and said sixth source in response to a signal above a threshold magnitude applied at said sixth gate, wherein said third n-channel transistor is adapted to have said threshold magnitude adjusted in response to an electrical signal applied between said sixth drain and said sixth gate.