Patent ID: 7345511

Claim:
A complementary logic circuit, comprising: a first logic input; a second logic input; a first dedicated logic terminal; a second dedicated logic terminal; a first logic block comprising: a p-type transistor network for implementing a predetermined logic function, said p-type transistor network comprising a plurality of p-type transistors, and having an outer diffusion connection, a first network gate connection, and an inner diffusion connection, said outer diffusion connection of said p-type transistor network being connected to said first dedicated logic terminal, and said first network gate connection of said p-type transistor network being connected to said first logic input; and a second logic block comprising: an n-type transistor network implementing logic function complementary to said predetermined logic function, said n-type transistor network comprising a plurality of n-type transistors, and having an outer diffusion connection, a first network gate connection, and an inner diffusion connection, said outer diffusion connection of said n-type transistor network being connected to said second dedicated logic terminal, and said first network gate connection of said n-type transistor network being connected to said second logic input; said inner diffusion connections of said p-type transistor network and of said n-type transistor network being connected to form a common diffusion logic terminal, wherein said outer diffusion connection of said p-type transistor network and said outer diffusion connection of said n-type transistor network are separately configured, such that said p-type transistor network and said n-type transistor network share a single common diffusion logic terminal.