Patent ID: 8455944

Claim:
A semiconductor device, comprising: a semiconductor body of a first conductivity type; a channel region of the first conductivity type projecting from a part of the semiconductor body with an upwardly tapered shape, the channel region thereby including a first side surface which is inclined with respect to an upper surface of the semiconductor body, a second side surface which is opposite to the first side surface and inclined with respect to the upper surface of the semiconductor body, a third side interface which interfaces between respective one ends of the first and second side surfaces, and a fourth side interface which is opposite to the third side interface to interface between respective other ends of the first and second side surfaces; a first region formed on a side of the third side interface of the channel region; a second region formed on a side of the fourth side interface of the channel region, each of the first and second regions being of a second conductivity type, and the first and second regions being arranged in line in a first direction; a gate structure running in a second direction crossing the first direction and forming a current path between the first and second regions along the first side surface of the channel region; an additional channel region of the first conductivity type projecting from another part of the semiconductor body with an upwardly tapered shape, the additional channel region thereby including a fifth side surface which is inclined with respect to the upper surface of the semiconductor body, a sixth side surface which is opposite to the fifth side surface and inclined with respect to the upper surface of the semiconductor body, a seventh side interface which interfaces between respective one ends of the fifth and sixth side surfaces, and an eighth side interface which is opposite to the seventh side interface to interface between respective other ends of the fifth and sixth side surfaces, the seventh side interface being on a side of the first region; a third region formed on a side of the eighth side interface of the additional channel region, the third region being of a second conductivity type and the first to third regions being arranged in line in the first direction; and an additional gate structure running in the second direction and forming an additional current path between the first and third regions along the fifth side surface of the additional channel region.