Patent ID: 7937679

Claim:
A method for performing failure mode and effects analysis (FMEA) on integrated circuits comprising: preparing by a processor a FMEA database of a integrated digital circuit under design and computing FMEA results from said FMEA database, said FMEA database comprising records relative to zones (SZ) of said circuit; automatically extracting information from a integrated circuit description, at least at the gate level of abstraction, said extraction of information comprising: reading integrated circuit information; partitioning said circuit in elementary sensitive zones (SZ); said partitioning including selecting as zones registers from a netlist at gate level; and extracting logic cone information associated to said sensitive zones, said extracting comprising extracting input cone information and extracting output cone information; composing a sensitive zone database including said sensitive zone partition and the related logic cone information; using said information in the preparing the FMEA database, importing said sensitive zone database in said FMEA database; automatically computing by the processor on the basis of the information in said sensitive zone database fault model statistics for each record including failure rates for each sensitive zone; and using said fault model statistics for each record including failure rates for each sensitive zone for automatically computing in said FMEA database failure rates for each FMEA record and on the basis of said computer failure rates computing FMEA results.