Patent ID: 7386812

Claim:
A logic basic cell for forming at least one output signal from at least three input signals in accordance with a predeterminable logic function, comprising: a first unit for realizing a first decomposition of the logic function into a plurality of logic subfunctions; and a second unit for realizing a second decomposition of the logic function into a plurality of logic subfunctions; wherein each of the first unit and the second unit is set up for realizing a Shannon decomposition, or for realizing an iterative decomposition, or for realizing a disjoint decomposition, wherein the first unit is set up as a Shannon decomposition unit for realizing a Shannon decomposition of a logic function into a plurality of logic subfunctions, further comprising: at least eight data signal inputs, it being possible for a data signal to be provided at each of the data signal inputs; a first logic function block, which is coupled to a first data signal input and a second data signal input of the data signal inputs, and is located within the first unit; a second logic function block, which is coupled to a third data signal input and a fourth data signal input of the data signal inputs, and is located within the second unit; at least one logic function configuration input, by means of which it is possible to predetermine a logic subfunction which can be realized by the respective logic function block from a plurality of logic subfunctions which can be realized for combining the data signals present at the respective logic function block; the Shannon decomposition unit having a first multiplexer, the first data input of which is coupled to an output of the first logic function block and the second data input of which is coupled to an output of the second logic function block and the control input of which is coupled to a fifth data signal input of the data signal inputs; and a first data signal output coupled to the output of the first logic function block, a second data signal output coupled to the output of the second logic function block, and a third data signal output coupled to an output of the first multiplexer, at which data signal outputs it is possible to tap off separately in each case a signal at the output of the first logic function block, a signal at the output of the second logic function block and a signal at the output of the first multiplexer, respectively, wherein the second unit which realizes an additional decomposition of the logic function into a plurality of logic subfunctions comprises a second multiplexer, the control input of which is coupled to a sixth data signal input of the data signal inputs, the first data input of which is coupled to a seventh data signal input of the data signal inputs and the second data input of which is coupled to an eighth data signal input of the data signal inputs.