Patent ID: 8370779

Claim:
A computer implemented method for efficiently analyzing verification or validation results of one or more blocks or one or more full-chip power distribution systems, comprising: using at least one processor that is to execute a process, the process comprising: placing and routing one or more decoupling capacitors to stabilize one or more local supply voltages for one or more individual instances in an electronic design; determining a value of effectiveness for each of at least one of the one or more decoupling capacitors, wherein the value of effectiveness indicates how well the at least one of the one or more decoupling capacitors stabilizes the one or more local supply voltages; and analyzing a result for a multi-level hierarchical power distribution verification or validation, which provides transistor level resolution for the electronic design, based at least in part upon the value of effectiveness of the at least one of the one or more decoupling capacitors without requiring a criterion of a switching probability for a net to provide design guidance for the at least one of the one or more decoupling capacitors.