Patent ID: 8761327

Claim:
A method, comprising: at a system having a decoder and a processor: receiving a first clock signal having a first frequency, and outputting the first clock signal from the system in the form of a display out clock signal; using rational clock divider (RCD) logic at the system to generate a second clock signal in response to the first clock signal, the second clock signal having a second frequency, wherein the second frequency is lower than the first frequency; generating video media timers using the second clock signal; and generating at least one video capture timestamp in response to the second clock signal, wherein the video media timers and the at least one video capture timestamp are output from the system separately from the output of the first clock signal of the system so that the output of the at least one video capture timestamp and video media timers have a different frequency than the output first clock signal; receiving a third clock signal having a third frequency; generating a fourth clock signal having a fourth frequency and in response to the third clock signal, wherein the fourth frequency is lower than the third frequency, and outputting the fourth clock signal from the system in the form of an audio out clock signal; using RCD logic at the system to generate a fifth clock signal in response to the third clock signal, the fifth clock signal having a fifth frequency, wherein the fifth frequency is lower than the third frequency; generating audio media timers using the fifth clock signal; and generating at least one audio capture timestamp in response to the fifth clock signal, wherein the audio media timers and the at least one audio capture timestamp are output from the system separately from the output of the fourth clock signal of the system so that the output of the at least one audio capture timestamp and audio timers have a different frequency than the output fourth clock signal.