Patent ID: 7335542

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate having current input/output regions; (b) forming a resist laminate on the semiconductor substrate, the resist laminate having a lower region and an upper region; (c) forming an upper opening through the upper region of the resist laminate, the upper opening having a laterally broadening middle space; (d) forming a lower opening through the lower region of the resist laminate, the lower opening communicating the upper opening, having a limited size along a current direction, and having generally vertical side walls; (e) vapor-depositing a gate electrode insulating layer on a bottom of the lower opening from an upper side of the semiconductor substrate; (f) performing a heat treatment on the resist laminate to deform the side walls of the lower opening so that opposite ends of the lower opening along the current direction ride opposite ends of the gate electrode insulating layer and that the lower opening has a forward taper shape upwardly and monotonically increasing a size of the lower opening along the current direction; and (g) vapor-depositing a metal layer into the upper and lower openings from an upper side of the semiconductor substrate to fill a gate electrode stem in the lower opening, the gate electrode stem having a bottom area inside an upper surface area of the gate electrode insulating layer, and to form a head in the upper opening to thereby form a mushroom gate electrode, the head having an expanded size along the current direction.