Patent ID: 7795089

Claim:
A method of making a semiconductor device structure on a semiconductor substrate having a semiconductor layer having isolation regions, comprising: forming a first gate structure over a first region of the semiconductor layer and a second gate structure over a second region of the semiconductor layer; forming sidewall spacers along sidewalls of the first and second gates; forming a first insulating layer over the first and second regions in which the first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers; forming a second insulating layer over the first insulating layer; patterning the second insulating layer to leave a remaining portion of the second insulating layer over the second region; removing the first insulating layer from over the first region to leave a remaining portion of the first insulating layer over the second region; recessing the semiconductor layer in the first region adjacent to the first gate to form recesses; epitaxially growing a semiconductor material in the recesses; removing the remaining portion of the first insulating layer; and using the remaining portion of the second insulating layer as a hard mask in the step of removing the first insulating layer.