Patent ID: 8362528

Claim:
An inverter comprising: a first logic switch including a first region of a first conductivity type; a second region of a second conductivity type adjacent to the first region, a first junction being defined between the first and second regions; and a first gate overlying the first junction, the first gate including: a first thin oxide layer on a surface of the first and second regions; and a first gate electrode on the first thin oxide layer, the first thin oxide layer having a first lateral edge over an uppermost surface of the first region and a second lateral edge over an uppermost surface of the second region, the first gate electrode being highly-doped with a dopant of the first conductivity type, the first lateral edge and the second lateral edge being vertical to a plane formed by an interface between the first thin oxide layer and the first gate electrode; a second logic switch including a third region of the second conductivity type; a fourth region of the first conductivity type adjacent to the third region, a second junction being defined between the third and fourth regions; and a second gate overlying the second junction, the second gate including: a second thin oxide layer on a surface of the third and fourth regions; and a second gate electrode on the second thin oxide layer, the second thin oxide layer having a third lateral edge on the third region and a fourth lateral edge on the fourth region, the second gate electrode being highly-doped with a dopant of the second conductivity type, the third lateral edge and the fourth lateral edge being vertical to a plane formed by an interface between the second thin oxide layer and the second gate electrode; an electrical connection between the first and second gate electrodes for receiving an input voltage V i ; separate electrical connections to the first and third regions, respectively, for receiving biasing voltages; and an electrical connection between the first and third regions for producing an output voltage V o in response to application of an input.