Patent ID: 8880847

Claim:
A method for prefetching memory in caching systems, comprising: receiving a memory read request having an associated address; determining whether a most significant portion of the associated address are present within slots of an array for storing a most significant portion of a predicted address; and in response to a determination that the most significant portion of the associated address is not present within the slots of an array for storing the most significant portion of predicted addresses modifying a prefetch FIFO (First In-First Out) counter to point to a next slot of the array to cycle through the slots of the array before wrapping around to a first slot of the array, generating a new predicted address by incrementing the received most significant portion of the associated address if a direction bit has a first digital state and decrementing the received most significant portion of the associated address if the direction bit has a second digital state opposite to the first digital state, placing the new predicted address in the next slot of the array pointed to by the prefetch FIFO counter, and prefetching data from a lower-level hierarchical memory in accordance with the most significant portion of the predicted address in the next slot.