Patent ID: 7986736

Claim:
A receiver, comprising: a plurality of channels for receiving a signal, wherein each channel receives the signal independently, each channel having an analog-to-digital converter for an in phase (I) signal of the received signal and an analog-to-digital converter for a quadrature (Q) signal of the received signal; each channel further having a signal processing block coupled to the I and Q analog-to-digital converters; and a data combiner coupled to the signal processing blocks of each channel, that combines the I signals from each channel and combines the Q signals from each channel wherein the signal processing blocks are further coupled to a controller, the controller comprising a combiner that combines incoming correlation values from the plurality of channels wherein the controller further includes a master symbol sync, a master frame sync coupled to the master symbol sync, and a master sampling frequency offset feedback control coupled to the master frame sync; wherein the master symbol sync process incoming symbol synchronization correlations values from the plurality of channels to produce symbol boundary and packet detection control information; wherein the master frame sync determines a start of channel estimation symbols, header symbols and data symbols with a received packet; wherein the master sampling frequency offset feedback control provides control information to a symbol sync of the signal processing block and a phase locked loop that drives a clock using sampling frequency offset estimates from each channel.