Patent ID: 8006067

Claim:
An active memory, comprising: a memory device; and a processing element array including a plurality of processing elements arranged in rows and columns, each of the processing elements comprising: processing logic having an input port configured to receive data to be processed and an output port configured to transmit processed data; a results pipe, comprising: a results register coupled to the input port and the output port of the processing logic, the results register being configured to store processed data received from the processing logic and to store data that is to be provided to the processing logic to be processed; a neighborhood connection register coupled to the results register, the memory device and the neighborhood connection register of at least one of the other processing elements in the processing element array, the neighborhood connection register configured to both provide data to each processing element that is adjacent the processing element and to receive data from each processing element that is adjacent the processing element; and control logic coupled to the processing logic and the results pipe, the results pipe being configured to control the operation of the processing logic and the results pipe to allow data to be shifted through the processing element array in any direction.