Patent ID: 7907003

Claim:
An electronic circuit comprising: an output node; a first input transistor having: a first channel terminal configured to draw a first portion of a first current generated from a supply voltage; and a control terminal configured to receive a reference input; a second input transistor having: a first channel terminal configured to draw a second portion of the first current; and a control terminal configured in a feedback loop with the output node; a first output transistor having: a first channel terminal coupled to the output node and configured to draw a second current generated from the supply voltage; a second channel terminal coupled to a second channel terminal of the first input transistor; and a control terminal configured to receive a biasing signal; a second output transistor having: a first channel terminal configured to draw a third current generated from the supply voltage; a second channel terminal coupled to a second channel terminal of the second input transistor; and a control terminal configured to receive the biasing signal; a third output transistor having: a first channel terminal coupled to the second channel terminal of the first output transistor; a second channel terminal coupled to a reference voltage; and a control terminal coupled to a control node; a fourth output transistor having: a first channel terminal coupled to the second channel terminal of the second output transistor; a second channel terminal coupled to the reference voltage; and a control terminal coupled to the control node; and a capacitor coupled between the supply voltage and the control node to prevent the first and second transistors from turning off during a rising edge of the supply voltage, to prevent an output voltage generated at the output node from rising during the rising edge of the supply voltage.