Patent ID: 8274829

Claim:
A nonvolatile memory device comprising: an array of nonvolatile memory cells arranged in rows and columns, such that the nonvolatile memory cells located on each column are connected to communicate with a local bit line associated with each column, the nonvolatile memory cells on each row are connected to communicate with a word line, and the nonvolatile memory cells on two adjacent rows are commonly connected to communicate with a source line, wherein the array of nonvolatile memory cells is partitioned into sectors, where each sector is placed in a first isolation well and each sector of the array of the nonvolatile memory cells is divided into blocks and each block is divided into pages, and each page includes one row of the nonvolatile memory cells; and a plurality of peripheral circuits comprising a row decoder comprising a plurality of voltage isolators wherein each voltage isolator is connected to the word lines associated with one block of the nonvolatile memory cells, wherein each voltage isolator is formed in a second isolation well such that when biasing voltages are applied to the first and second isolation wells for reading, programming, erasing, and verifying selected nonvolatile memory cells, the biasing voltages applied to the array of nonvolatile memory cells do not exceed a drain to source breakdown voltage of the peripheral circuits.