Patent ID: 8359346

Claim:
A system comprising: a logic block that receives a plurality of bit values, the plurality of bit values including a first bit value, a second bit value, a third bit value, and a fourth bit value, the logic block further comprising: a first exclusive-OR function that receives the first bit value and the second bit value, and generates a linear output value based upon exclusive disjunction between the first bit value and the second bit value; an OR function that receives the third bit value and the fourth bit value, and generates a first nonlinear output value based upon logical disjunction between the third bit value and the fourth bit value; and a second exclusive-OR function that receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value, wherein the second nonlinear output value is utilized to represent the plurality of bit values.