Patent ID: 7825707

Claim:
A clock generation circuit for generating a clock signal according to a reference clock signal input to the clock generation circuit, the clock generation circuit comprising a frequency modulation circuit, wherein according to a selection signal showing which one of a frequency-unmodulated clock signal and a frequency-modulated clock signal is to be output, the frequency modulation circuit generates, based on the reference clock signal, one of the frequency-unmodulated clock signal and the frequency-modulated clock signal, and a PLL circuit for receiving the clock signal output from the frequency modulation circuit and for changing a bandwidth according to the selection signal, wherein the PLL circuit includes a low-pass filter having a resister and a capacitative element, and a charge pump, and the PLL circuit changes both a resistance value of the resister and a capacitance value of the capacitative element in the low-pass filter and a current amount of the charge pump to change the bandwidth.