Patent ID: 7299400

Claim:
An error correction circuit comprising: a selected-bit reverse circuit being configured to reverse error bits in output data based on a first signal, said output data including memory data and a check data from a memory device; an ECC circuit being configured to correct a one-bit error based on said output data; a checkbit generation circuit being configured to generate checkbits based on correction data outputted from said ECC circuit; an ECC data register being configured to store said correction data and said check data; a bit-comparing circuit being configured to compare each bit between a first data group of said output data from said selected-bit reverse circuit and a second data group of output data from said ECC data register; an address memory unit being configured to store an address corresponding to said memory data when said bit-comparing circuit detects a discrepancy between said first data group and said second data group; an error data memory unit being configured to include a plurality of memory circuits having a necessary number for a predetermined data-width, said error data memory unit being configured to write discrepancy information at a bit-location corresponding to said discrepancy when said bit-comparing circuit detects said discrepancy between said first data group and said second data group; a data OR circuit being configured to perform a logical operation between each data group stored in said plurality of memory circuits of said error-data memory unit and to generate said first signal.