Patent ID: 8379465

Claim:
A semiconductor static random-access memory operable in read and write cycles in a normal operating mode, and operable in a retain-till-accessed (RTA) mode, the memory comprising: a plurality of memory cells, arranged in rows and columns in at least one memory array block, each of the memory cells within a column biased from a corresponding one of a plurality of bias voltage nodes; a first plurality of bias devices, associated with a first memory array block, each of the first plurality of bias devices associated with at least one column of memory cells in the first memory array block, each of the first plurality of bias devices comprising: a first transistor having a conduction path connected in series between a power supply node and the bias voltage node of its associated at least one column; and a second transistor, having a conduction path connected between the power supply node and the bias voltage node of its associated at least one column, and having a control electrode for receiving a control signal; and control logic for generating control signals to the second transistor in each of the first plurality of bias devices so that the second transistor in each of the first plurality of bias devices is turned on in read cycles, so that the second transistor in each of the first plurality of bias devices is turned off in RTA mode for the first memory array block, and so that the second transistor in one of the first plurality of bias devices is turned off in a write cycle to a memory cell in its associated column.