Patent ID: 8530310

Claim:
A method for forming a semiconductor device comprising: providing a substrate prepared with a second gate feature having side and top surfaces; forming a first gate dielectric layer having first and second sub-layers over the second gate feature and substrate; processing the first gate dielectric layer to form nano-crystals in first and third portions of the first gate dielectric layer over the top surface of the second gate feature and substrate while a second portion on the side surfaces of the second gate feature are devoid of nano-crystals, wherein the first and third portions of the second sub-layer of the first gate dielectric layer are formed with a sufficient thickness to form nano-crystals when subsequently processed, and the second portion of the second sub-layer of the first gate dielectric layer is formed with a thickness insufficient to form nano-crystals when subsequently processed; forming a first gate electrode layer over the substrate; and patterning the first gate electrode layer, first gate dielectric layer and second gate feature to form a memory cell with a split gate.