Patent ID: 8060925

Claim:
A processor communicating with a first memory configured to store first information and first data, and communicating with a second memory configured to store second information and second data, comprising: a computing unit configured to perform computation using the first data and the second data; a generating unit configured to, when power supply suspension information is sent, generate first authentication information and second authentication information, send the first authentication information to the first memory, and send the second authentication information to the second memory; a first storing unit configured integrally with the computing unit to store the first authentication information and the second authentication information generated by the generating unit; a reading unit configured to read out the first information from the first memory and the second information from the second memory when the power supply resumes, the first information representing the first authentication information received by the first memory from the generating unit before the power supply stops, and the second information representing the second authentication information received by the second memory from the generating unit before the power supply stops; an authenticating unit configured to authenticate the first memory by comparing the first information and the first authentication information stored in the first storing unit, and to authenticate the second memory by comparing the second information and the second authentication information stored in the first storing unit, when the power supply resumes; and a controlling unit configured to control an access of the computing unit to the first memory and the second memory based on a result of the authentications.