Patent ID: 7262634

Claim:
A programmable logic device having programmable logic circuitry comprising: first operational circuitry; second operational circuitry; routing driver circuitry coupled to an output signal of the first operational circuitry; routing receiver circuitry coupled to an input of the second operational circuitry; and an interconnection conductor extending from the routing driver circuitry to the routing receiver circuitry, wherein the routing driver circuitry is configured to drive a routing signal onto the interconnection conductor, wherein the voltage swing of the routing signal is less than the voltage swing of the output signal of the first operational circuitry, wherein the routing receiver circuitry is configured to receive the routing signal from the interconnection conductor and to provide an input signal to the input of the second operational circuitry, and wherein at least one condition from the group consisting of the following is true: 1) the routing receiver circuitry comprises a full latch coupled to an inverter, and 2) the routing receiver circuitry comprises a low leakage input buffer coupled to an inverter.