Patent ID: 8405421

Claim:
A nonvolatile full adder circuit comprising: a full adder electrical circuitry comprising first input terminal for receiving first binary input signals, a second input terminal for receiving second binary input signals, a third input terminal for receiving binary carry-in signals, a first output terminal for providing a sum output signal, and a second output terminal for providing a carry-out signal; a high voltage source electrically coupled to a first source terminal of the full adder electrical circuitry; a low voltage source electrically coupled to a second source terminal of the full adder electrical circuitry; a first nonvolatile memory element comprising two stable logic states and electrically coupled to the first output terminal at its first end and to an intermediate voltage source at its second end, and a second nonvolatile memory element comprising two stable logic states and electrically coupled to the second output terminal at its first end and to the intermediate voltage source at its second end, wherein a logic state each of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends, and wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.