Patent ID: 6931469

Claim:
A 40/80-core cable discriminating method of discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said method comprising: setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used, wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state, wherein, when master and slave storage apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period, wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, wherein said first protocol period comprises a period that an SRST signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting, wherein said second protocol period comprises a period that the peripheral storage apparatus changes the PDIAG-signal into said first state within the PDIAG-signal has been settled into said first state, and wherein said third protocol period comprises a period that the PDIAG-signal is kept on said first state while the SRST signal is in said first state.