Patent ID: 8106690

Claim:
A semiconductor integrated circuit device comprising a clock generation circuit that includes: a PLL generating a first clock signal equal in frequency to a reference clock signal and a plurality of second clock signals each arbitrarily shifted in phase from the first clock signal; and a spread spectrum clock generator generating a frequency modulation clock signal which modulates the frequencies of the first and second clock signals generated by the PLL to spread an electromagnetic spectrum, wherein the spread spectrum clock generator includes: a frequency divider that frequency-divides the first clock signal output from the PLL; a frequency-divided clock generator that outputs a frequency-divided signal frequency-divided by the frequency divider based on the phase-shifted second clock signals output from the PLL to generate phase-shifted multiphase frequency-divided clocks; a frequency-divided clock selector that selects and outputs any two frequency-divided clocks whose phases are different from and closest to each other from among the multiphase frequency-divided clocks generated by the frequency-divided clock generator; a phase interpolation circuit that phase-shifts the frequency-divided clock by a phase shift obtained by dividing the phase difference between the two frequency-divided clocks from the two frequency-divided clocks selected by the frequency-divided clock selector and that outputs the resultant clock as the frequency modulation clock signal; and a control circuit that controls the frequency-divided clock selector and the phase interpolation circuit such that a period of the frequency modulation clock signal output from the phase interpolation circuit differs from a period of the first clock signal output form the PLL.