Patent ID: 8426859

Claim:
A semiconductor device comprising: a semiconductor layer including a drain region, a channel region, and a source region; a first insulating layer covering the semiconductor layer; a gate electrode which is formed on the first insulating layer and has a portion overlapping the channel region of the semiconductor layer with the first insulating layer sandwiched in between; a second insulating layer which is formed on the first insulating layer and covers the gate electrode; a drain electrode and a source electrode which are formed on the second insulating layer and respectively connected to the drain region and the source region of the semiconductor layer through a contact hole formed in the first insulating layer and the second insulating layer; and a capacitor electrode which is formed on the second insulating layer and has a portion facing the gate electrode with the second insulating layer sandwiched in between, wherein the second insulating layer has a thin portion, whose thickness is thinner than that of the second insulating layer in surrounding regions, on the portion of the gate electrode overlapping the channel region, and a part of the capacitor electrode faces the portion of the gate electrode overlapping the channel region with the thin portion of the second insulating layer sandwiched in between.