Patent ID: 7345363

Claim:
A semiconductor device comprising: a plastic package; a semiconductor chip comprising an active upper side with signal contact areas that are arranged in rows and in a central bonding channel; and a rewiring level arranged on the active upper side of the semiconductor chip and comprising an insulating layer, a rewiring layer arranged on the insulating layer and a closed metal layer that includes a bonding channel opening in the region of the central bonding channel; wherein: the semiconductor chip is fixed on the closed metal layer of the rewiring level by an adhesive bond and an insulating layer in such a way that the signal contact areas of the semiconductor chip are arranged in the bonding channel opening; the insulating layer of the rewiring level includes contact vias that extend from the closed metal layer to external contact areas for ground connections, and the rewiring layer comprises (i) signal conductor paths that extend from the central bonding channel to external contact areas for signal connections and (ii) ground or supply conductor paths that also extend from the central bonding channel, wherein the ground or supply conductor paths are arranged parallel to one another and in an alternating stacked relationship with the signal conductor paths, and the ground or supply conductor paths have a smaller width than the signal conductor paths.