Patent ID: 8149632

Claim:
A semiconductor device comprising: a terminal; first and second voltage lines supplied respectively with first and second potentials, the first potential being larger than the second potential; an output circuit comprising a first transistor of a first conductivity type coupled between the first voltage line and the terminal and a second transistor of a second conductivity type coupled between the second voltage line and the terminal; a gate level setting section coupled to the first and second transistors to control levels of control electrodes of the first and second transistors; and a core circuit producing information which is to be outputted at the terminal through the gate level setting section and the output circuit, the core circuit comprising a third transistor of the first conductivity type; the first transistor having a threshold value that is smaller in absolute value than a threshold value of the third transistor; the gate level setting section supplying the control electrode of the first transistor with a third potential that is larger than the first potential in a stand-by mode in which both of the first and second transistors are rendered non-conductive to prevent the information from the core circuit from being outputted at the terminal and with the first potential in an active mode in which one of the first and second transistors is rendered conductive to allow the information from the core circuit to be outputted at the terminal.