Patent ID: 8341576

Claim:
A design method of a semiconductor device which comprises a control target circuit section and a voltage control section which dynamically controls a supply voltage to said control target circuit section, wherein said control target circuit section comprises: a delay monitor circuit configured to measure a delay in said control target circuit section as a monitor delay; and a target delay register configured to store a target delay data which shows a target delay as a target value of said monitor delay, wherein said delay monitor circuit compares said monitor delay and said target delay shown by said target delay data and sends a comparison resultant signal to said voltage control section to show a result of the comparison, and wherein said voltage control section controls said supply voltage based on said comparison resultant signal such that said monitor delay approaches to said target delay, said design method comprising: producing delay libraries in which an inter-chip variation is substantively set to 0; performing a circuit design of a chip containing said control target circuit section; performing a timing analysis on said chip by using said delay libraries; and determining said target delay based on said delay library which satisfies a timing constraint.