Patent ID: 8159029

Claim:
A semiconductor device comprising: a semiconductor substrate comprising an active area; a source region and a drain region formed in the substrate; a gate structure formed on the substrate disposed between the source and drain regions; and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including a plurality of projections that each project toward the drain region and that are located proximate to an edge of the drain region, wherein the plurality of projections are connected together via a portion of the first isolation structure; wherein each of the plurality of projections includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction and wherein adjacent projections are spaced a distance from each other; and wherein a portion of the active area is disposed between each pair of the projections of the first isolation structure and is arranged such that it comprises a portion of a direct conduction path between the source region and the drain region.