Patent ID: 7187029

Claim:
A nonvolatile semiconductor memory device comprising a first cell which includes: a drain diffusion region and a source diffusion region formed on a surface layer of a semiconductor substrate; a first insulating film formed on the surface layer between the source diffusion region and the drain diffusion region; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; a first control gate formed on the second insulating film; a third insulating film formed on the first control gate and a sidewall thereof and on a sidewall of the floating gate; a second control gate formed on the first control gate with the third insulating film interposed therebetween; means for writing into the cell by causing electrons to be ejected from the floating gate into the substrate so as to lower a threshold voltage of the cell; a plurality of such cells are provided in a channel length direction, wherein a source diffusion region of the first cell and a drain diffusion region of a second cell adjacent to said first cell in the channel length direction are shared in common as one bit line; and wherein the second control gate is also formed on (a) the sidewall of the first control gate with the third insulating film interposed therebetween, on (b) the sidewall of the floating gate with the third insulating film interposed therebetween, and on (c) the source and drain diffusion regions with the third insulating film interposed therebetween, in the channel length direction.