Patent ID: 8422264

Claim:
A system comprising: a plurality of integrated circuits (“ICs”), wherein at least one IC of the plurality of ICs comprises: memory circuitry; and memory manager circuitry configured to: maintain a unique global identification (“ID”) for a data block stored by the plurality of ICs, wherein the global ID for the data block comprises: a node ID identifying an IC of the plurality of ICs which stores the data block, and a logical block number of the data block; maintain a translation mapping between a logical block number of a data block stored locally in the memory circuitry of the at least one IC and a physical portion ID of a portion of the memory circuitry of the at least one IC containing the locally stored data block; and access the portion of the memory circuitry of the at least one IC containing the locally stored data block in response to receiving a physical portion ID of the locally stored data block.