Patent ID: 8748302

Claim:
A method, comprising: forming a first dielectric material above a gate electrode structure of a transistor, wherein forming said first dielectric material comprises applying a deposition technique so as to substantially avoid creation of voids therein, said gate electrode structure comprising a placeholder material, said gate electrode structure extending to a first height level, wherein a height level of an entire exposed upper surface of said first dielectric material extends to at least a second height level that is higher than said first height level; performing a first planarization process so as to provide said first dielectric material with a substantially planar surface; after performing said first planarization process, removing an upper portion of said first dielectric material so as to reduce said height level of said entire exposed upper surface from said second height level to a third height level that is lower than said first height level; forming a second dielectric material above said first dielectric material, a height level of an entire exposed upper surface of said second dielectric material extending above said first height level; performing a second planarization process so as to remove an upper portion of said second dielectric material and form an exposed top surface of said placeholder material; and replacing said placeholder material at least with a metal-containing electrode material.