Patent ID: 8451621

Claim:
A semiconductor component, comprising: a substrate having a component receiving area and a plurality of bond pads; a first semiconductor chip having first and second surfaces, the first surface of the first semiconductor chip electrically coupled to the component receiving area; a first dielectric material over a portion of the second surface of the first semiconductor chip; a first electrical connector having first and second ends, the first end over the first dielectric material and adjacent to the second surface of the first semiconductor chip; a second semiconductor chip having first and second surfaces, the first surface of the second semiconductor chip electrically coupled to the first end of the first electrical connector, wherein the first end of the first electrical conductor is positioned between the first and second semiconductor chips; a second dielectric material over a portion of the second surface of the second semiconductor chip; a second electrical connector having first and second ends, the first end of the second electrical connector over the second dielectric material and adjacent to the second surface of the second semiconductor chip; and a third semiconductor chip having first and second surfaces, the first surface of the third semiconductor chip electrically coupled to the first end of the second electrical connector, wherein the first end of the second electrical connector is between the second and third semiconductor chips, wherein the first surface of the first semiconductor chip includes a portion of a drain, and further including a gate bond pad at a first portion of the second surface of the first semiconductor chip and a source bond pad at a second portion of the second surface of the first semiconductor chip.