Patent ID: 8629063

Claim:
A method comprising: forming at least one cavity in a substrate having a first region and a second region, the first region having a greater number of patterned cavities formed therein than the second region; depositing a layer of conductive material in the cavity included in the first region and over exposed portions of the substrate included in the second region; removing portions of the conductive material to expose portions of the substrate using a planarizing process; and removing residual portions of the conductive material disposed on the substrate in the second region using a reactive ion etch (RIE) process without removing remaining portions of the conductive material disposed in the patterned cavities of the first region, wherein the RIE process induces a lag based on a surface area difference of the conductive material disposed in the patterned cavities with respect to the residual portions of the conductive material such that the residual portions of the conductive material are removed at a faster rate than the conductive material disposed in the patterned cavities.