Patent ID: 8581822

Claim:
A method for driving a double-gate liquid crystal display device, comprising: precharging a first pixel unit by outputting a first data driving signal during a first period according to a first gate driving signal; main-charging the first pixel unit and precharging a second pixel unit by outputting a second data driving signal during a second period subsequent to the first period according the first gate driving signal and a second gate driving signal, wherein the first pixel unit is coupled to a data line and a first gate line and the second pixel unit is coupled to the data line and a second gate line; main-charging the second pixel unit by outputting a third data driving signal during a third period subsequent to the second period according the second gate driving signal and a third gate driving signal; reducing a precharge time of the first pixel unit during the first period and increasing a main-charge time of the first pixel unit during the second period when the first data driving signal and the second data driving signal have opposite polarities, or increasing the precharge time of the first pixel unit during the first period and reducing the main-charge time of the first pixel unit during the second period when the first data driving signal and the second data driving signal have a same polarity; and adjusting a first write period during which the second data driving signal is written into the first pixel unit during the second period and a second write period during which the third data driving signal is written into the second pixel unit during the third period, so that an amount of charges written into the first pixel unit during the second period is substantially equal to an amount of charges written into the second pixel unit during the third period; wherein: the first gate driving signal is at an enable level, the second gate driving signal is not at the enable level, and the third gate driving signal is not at the enable level during the first period; the first gate driving signal is at the enable level, the second gate driving signal is at the enable level, and the third gate driving signal is not at the enable level during the second period; the first gate driving signal is not at the enable level, the second gate driving signal is at the enable level, and the third gate driving signal is at the enable level during the third period; and pulse widths of the first gate driving signal, the second gate driving signal and the third gate driving signal are of a same length.