Patent ID: 8688877

Claim:
An integrated-circuit comprising: a memory array configured as a multiport memory having an interface to a write bus from which parallel data is received and an interface to a read bus to which parallel data is transmitted; a data port interface from which serial data is received from a data port and to which serial data is transmitted to the data port; a multiline port buffer configured to buffer data communicated between the memory array and the data port interface, each line of the multiline port buffer configured to buffer k words of data and operably coupled to the write bus, the multiline port buffer configured to: receive the serial data from the data port via the data port interface; convert, at a first frequency, the serial data received from the data port interface to n-bit-wide words of parallel data; buffer, at a second frequency, a k-word-long block of the n-bit-wide words of parallel data into one of the lines of the multiline port buffer as a block of k*n bits of data by sequentially writing k words of the n-bit-wide words of parallel data into k data storage elements of the line of the multiline port buffer; and transmit, at a third frequency, the block of k*n bits of data to the memory array via the write bus effective to write the block of k*n bits of data to the memory array, the third frequency different than the first frequency.