Patent ID: 6996822

Claim:
A method for assigning to and ordered executing of tasks by instruction processors in a multiple instruction processor computer system having at least three levels of memory, said at least three levels being at least two cache levels, a first of which is accessible directly by a single one of said instruction processors, a mid-level memory being a multiprocessor-accessible cache accessible by at least two of said instruction processors, and a third memory level being a main memory, accessible by all of said instruction processors, said method comprising: selecting a processor-associated switching queue to which to assign a now task, assigning said new task to said selected switching queue by placing information about said selected switching queue into said new task, running a one of said instruction processors based upon tasks having information in said one instruction processor's associated switching queue until there are no tasks in said one instruction processor's associated switching queue and then, determining through the use of a selection matrix which other switching queue may be used as a second level switching queue by said one instruction processor, and inquiring by said one instruction processor of said second level switching queue for a next task that may be available on said second level switching queue.