Patent ID: 6949441

Claim:
A method of making a ferroelectric memory device, comprising: forming a gate oxide layer and polysilicon layer on a semiconductor substrate having first and second active regions isolated from each other by an isolation layer, and patterning the gate oxide layer and polysilicon layer to form first and second split word lines across the first and second active regions; forming source and drain regions in exposed portions of the first and second active regions using the first and second split word lines as a mask, and forming a first interlevel insulating layer on the overall surface of the substrate; forming bit line contact holes to expose the source regions of the first and second active regions, and forming first and second bit lines perpendicular to the first and second split word lines, coming into contact with the source regions through the bit line contact holes; forming a second interlevel insulating layer, forming contact holes to expose the drain regions of the first and second active regions, forming first capacitor electrodes in a cylindrical shape, coming into contact with the drain regions through the contact boles; forming a ferroelectric layer on the overall surface of the substrate on which the first capacitor electrodes are formed, and forming second capacitor electrodes to be filled in the cylinders of the first capacitor electrodes; and forming a third interlevel insulating layer on the overall surface of the substrate including the second capacitor electrodes, forming contact holes to expose portions of the second capacitor electrodes, forming a metal layer on the overall surface of the substrate and selectively etching the metal layer to form first and second shunt split word lines.