Patent ID: 7120160

Claim:
A packet switching system, comprising: a plurality of input line processors; a plurality of output line processors; a plurality of input buffers including a plurality of queue buffers, being provided corresponding to the output line processors, and being connected to the input line processors; a crossbar switch being connected to the input buffers and the output line processors; an arbiter to arbitrate for assigning grant of transmitting a packet to said crossbar switch, to any of queue buffers to the queue buffers; and means to determine priority as a parameter between an interval of time for a packet to be transmitted to the crossbar switch from said queue buffer and a queue length of said queue buffer, both are calculated for each queue buffer of said queue buffers, to thereby select a queue buffer among all queue buffers in the input buffers and give the selected queue the grant for transmitting a packet to said crossbar switch, wherein said arbiter performs arbitration according to said priority determined on all queue buffers of the input buffers, and wherein the arbitration is performed based on a transmit priority level calculated by the equation of L=( 1/ In ( e x ( M - a*t )/( b*s ))) ×15, where L is the priority level, M is the time out, t is output data interval, s is the number of segments at present time, a is output data coefficient, and b is queue length coefficient.