Patent ID: 7625800

Claim:
A method of fabricating a MOS transistor, comprising steps of: coating a semiconductor substrate with a first oxide layer and removing a predetermined width of the first oxide layer by performing a photolithography process to the first oxide layer; forming a lightly doped drain (LDD) region by ion implantation and annealing using the first oxide layer as a barrier wherein the ion implantation uses impurities of a conductivity type opposite that of the semiconductor substrate; forming gate spacers by coating the semiconductor substrate with a second oxide layer and etching the second oxide layer; forming a channel in the LDD region by ion implantation and annealing using the first oxide layer and the gate spacers as a barrier, wherein the ion implantation to form the channel uses impurities having a conductivity type opposite that of the LDD region so as to cancel a part of the LDD region between the opposing edges of the gate spacers; forming a gate oxide layer on a surface of the semiconductor substrate between the opposing edges of the gate spacers; forming a polysilicon gate electrode by coating the first oxide layer, the gate spacer, and the gate oxide layer with a polysilicon layer and performing photolithography and etching processes to the polysilicon layer; and forming, by annealing, source/drain diffusion regions by ion implantation of impurities of a conductivity type opposite that of the semiconductor substrate using the gate electrode and the gate spacers as a barrier, wherein the photolithography process performed to the first oxide layer uses a first negative photoresist layer, the photolithography process performed to the polysilicon layer uses a second photoresist layer, and the etching process to the polysilicon layer removes a part of the polysilicon layer and the entire first oxide layer using the second photoresist as a mask.