Patent ID: 7511559

Claim:
A booster circuit comprising: n stage booster cells which are connected in series (n is an integer equal to or larger than 2), at least one booster cell among the n stage booster cells including: a charge transfer transistor that transfers charges from the preceding stage to the following stage; an output voltage boosting capacitor having one electrode connected to the output side of the charge transfer transistor and the other electrode to which a first clock signal having a predetermined phase is input; a gate voltage boosting capacitor having one electrode connected to a gate of the charge transfer transistor and the other electrode to which a second clock signal having a predetermined phase is input; and a switching transistor for connecting the gate of the charge transfer transistor to an input terminal of the charge transfer transistor; and a reset unit that pulls out a stored charge of the gate such that a pull-out lower limit voltage and a control signal are input through a pull-out lower limit voltage supply section and a control signal supply section and an absolute value of a gate voltage of the charge transfer transistor in at least one booster cell among the booster cells does not fall below the pull-out lower limit voltage on the basis of the control signal.