Patent ID: 8593867

Claim:
A flash memory device comprising: a memory cell array having a plurality of memory cells; a sensing node voltage controller configured to generate a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines and configured to receive the precharge voltage and the sensing node voltage control signal, the page buffer unit having a plurality of page buffers respectively corresponding to the plurality of bit lines, each of the plurality of page buffers including a bit line connection unit connected between a corresponding bit line and a sensing node, and configured to control a voltage of the sensing node responsive to the sensing node voltage control signal, a precharge unit connected to the sensing node, and configured to precharge the sensing node to the precharge voltage responsive to a precharge control signal, and a data input/output unit configured to determine data of a selected memory cell by sensing the voltage of the sensing node responsive to a latch control signal, and to output the data of the selected memory cell wherein after a precharge operation of the sensing node, the voltage of the sensing node is increased responsive to the sensing node voltage control signal before sensing the data of the selected memory cell.