Patent ID: 7642606

Claim:
A method of forming memory cell of a non-volatile memory device, comprising: providing a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; providing first and second memory cell transistor gates of first and second memory cell transistors on the substrate at opposite sides of the select transistor, each of the first and second memory cell transistor gates comprising: a tunnel insulating layer pattern; a charge storage layer pattern on the tunnel insulating layer pattern; a blocking insulating layer pattern on the charge storage layer pattern; and a control gate on the blocking insulating layer pattern; providing first and second floating junction regions in the substrate between the select transistor gate and the first and second memory cell transistor gates respectively, wherein the first and second floating junction regions are formed using the select transistor gate and the first and second memory cell transistor gates as masks during implantation of ions into the substrate to form the first and second floating junction regions; and providing first and second drain regions in the substrate at sides of the first and second memory cell transistor gates respectively opposite the first and second floating junction regions respectively.