Patent ID: 7064412

Claim:
An electronic package, comprising: a conductive trace layer having a first side and a second side, the conductive trace layer being patterned to define a piurality of interconnect pads; a dielectric substrate mounted on the first side of the conductive trace layer; an embedded capacitor having a capacitance of from about 1 nF/sq.cm. to about 100 nF/sq.cm., including a first conductive layer, a second conductive layer and a layer of dielectric material made of a non-conductive polymer blended with high dielectric constant particles disposed between the first and the second conductive layers, the first conductive layer attached to the second side of the conductive trace layer by a first adhesive layer; a plurality of interconnect regions extending through the first conductive layer and the dielectric material layer of the capacitor; and an interconnect member connected between each of the conductive layers of the capacitor and a corresponding set of the interconnect pads, the first conductive layer of the capacitor being electrically connected to a first set of the interconnect pads and the second conductive layer of the capacitor being electrically connected to a second set of the interconnect pads, the interconnect members corresponding to the second set of interconnect pads extending through one of the interconnect regions.