Patent ID: 8245169

Claim:
A computer-implemented method to simulate an electronic design layout, the method comprising: selecting one of a plurality of signal conductors included in the electronic design layout, the electronic design layout including the plurality of signal conductors and a plurality of metal fills that are void from carrying an electrical signal; assigning, by one or more processing devices, a first potential to the selected signal conductor and assigning a second potential to the non-selected signal conductors, the first potential different than the second potential; selecting, by one or more of the processing devices, one of the plurality of metal fills; assigning, by one or more of the processing devices, a surface potential variable to the selected metal fill, the surface potential variable corresponding to an unknown voltage potential residing on the selected metal fill; generating, by one or more of the processing devices, a zero charge equation for the selected metal fill, wherein the zero charge equation includes the surface potential variable and establishes that a total charge residing on the selected metal fill is equal to zero; including, by one or more of the processing devices, the zero charge equation in a system of equations, the system of equations including a plurality of grid point potential equations; solving, by one or more of the processing devices, the system of equations, the solving resulting in one or more solutions; computing, by one or more of the processing devices, capacitance values for the plurality of signal conductors based upon the one or more solutions; and simulating the electronic design layout using the computed capacitance values.