Patent ID: 7200027

Claim:
A reference generator system for providing bitline reference voltages for memory access operations in a ferroelectric memory device, the reference generator system comprising: a primary capacitance; a precharge system coupled with the primary capacitance, the precharge system being adapted to charge the primary capacitance before or during a memory access operation; and a reference system comprising a plurality of local reference circuits individually associated with a corresponding array column of a ferroelectric memory array, the local reference circuits individually comprising: a staging capacitance; a first switching device coupled between the staging capacitance and the primary capacitance, the first switching device being adapted to couple the staging capacitance to the primary capacitance for charge sharing therebetween to precharge the staging capacitance and to then isolate the precharged staging capacitance from the primary capacitance before or during the memory access operation; and a second switching device coupled between the staging capacitance and a bitline of the corresponding array column, the second switching device being adapted to isolate the staging capacitance from the bitline while the first switching device couples the staging capacitance to the primary capacitance to precharge the staging capacitance, and to couple the precharged staging capacitance to the bitline for charge sharing therebetween to provide a reference voltage to the bitline before or during the memory access operation.