Patent ID: 7936609

Claim:
A memory controller comprising: a counter configured to count the number of “0” data or “1” data in a data sequence that is to be recorded in memory cells of a semiconductor memory unit; an inverter configured to reverse all data in the data sequence; and a control unit configured to control to record the data in the semiconductor memory unit that is made of the memory cells and to reproduce the recorded data, wherein the memory cells assume record states with threshold voltages according to the data; set a flag added to the data sequence to indicate that a reverse processing has been performed, if the inverter has performed the reverse processing on the data in the data sequence so as to make the number of the memory cells in a predetermined record state great or small based on a count of the counter in a record operation; and perform re-reverse processing on the data in the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation, wherein the control unit controls the reverse processing of the inverter so as to make the number of the memory cells in a record state with a low threshold voltage great or to make the number of the memory cells in a record state with a high threshold voltage small.