Patent ID: 7446375

Claim:
A low voltage power device comprising a plurality of quasi-vertical LDMOS device cells, wherein each device cell comprises: a doped substrate and an epitaxial layer formed thereover having an upper surface; source and drain regions of a first conductivity type formed in the epitaxial layer proximate the upper surface of said epitaxial layer, said source and drain regions being spaced from one another and having a channel region of a second conductivity type formed therebetween; a conductive gate, said conductive gate formed over a gate dielectric layer formed over said channel region, said conductive gate partially overlapping said source and drain regions; a conductive trench sinker formed though said epitaxial layer and adjacent a selected one of said source and drain regions, said trench sinker electrically coupling said selected one of said source and drain regions to said substrate for coupling current from said channel to said substrate; and an insulator layer formed over said epitaxial layer and conductive gate; wherein said plurality of device cells is arranged in a closed cell configuration, said low voltage power device further comprising a pair of source and drain electrodes, one of the drain and source electrodes being disposed over said epitaxial layer and the other of the drain and source electrodes being disposed at a bottom side of said substrate, wherein said conductive gate is cross shaped, with said source and drain regions formed on opposite sides of individual arms of said conductive gate.