Patent ID: 7482693

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer; multiple power or ground pads arranged in an area array in a first region of said integrated circuit chip, wherein said area array has more than three rows and more than three columns, and wherein all pads in said area array are said multiple power or ground pads; multiple first peripheral pads arranged along multiple edges of said integrated circuit chip; multiple metal traces over said passivation layer; multiple second peripheral pads arranged in more than two rings surrounding said multiple power or ground pads and in a second region surrounding said first region, wherein said multiple second peripheral pads in each of said more than two rings comprise more than ten signal pads continuously arranged, wherein one of said more than ten signal pads in one of said more than two rings is connected to one of said multiple first peripheral pads through one of said multiple metal traces, and said one of said more than ten signal pads in said one of said more than two rings has a position from a top view different from that of said one of said multiple first peripheral pads; and multiple metal bumps on said multiple second peripheral pads.