Patent ID: 7194644

Claim:
An integrated circuit comprising: a main oscillator circuit supplying a first clock signal; a peripheral circuit supplying a periodic wake-up signal; a central processing unit having a first operating mode at full power, in which the first clock signal is applied to the central processing unit; an active halt mode, in which the main oscillator circuit and the central processing unit are deactivated, the central processing unit being awakened by the periodic wake-up signal; a secondary oscillator circuit adapted to supply a second clock signal of lower frequency than the first clock signal; and a circuit adapted to manage clock signals being arranged for, upon the wake-up of the central processing unit at the end of the active halt mode, waking up the secondary oscillator circuit and applying the second clock signal to the central processing unit so as to clock the central processing unit to the frequency of the second clock signal and thus obtain a second operating mode with reduced current consumption relative to the first operating mode, the circuit being operable to provide a transient state after waking up the secondary oscillator circuit in which the management circuit does not supply any clock signal at its clock output, the clock output being set to a selected voltage level so as to avoid interference during transitions between being clocked at a first clock signal rate and a second clock signal rate.