Patent ID: 8001377

Claim:
An apparatus, comprising: a main processing unit; a plurality of attached processing units, each including a local memory, a decryption unit, and a secure store containing a substantially unique key, each attached processing unit being operable to enter a normal mode of operation or a secure mode of operation; and a shared memory, wherein: the main processing unit is capable of initiating data transfers between the shared memory and a given one of the attached processing units that bypass the decryption unit when the given attached processing unit is in the normal mode, and the main processing unit is not capable of: (i) initiating data transfers from the given attached processing unit to the shared memory; or (ii) initiating data transfers from the shared memory to the given attached processing unit that bypass a respective decryption unit, when the given attached processing unit is in the secure mode; wherein the decryption unit of the given attached processing unit uses a respective substantially unique key from respective secure store to decrypt data transfers from the shared memory to a local memory of the given attached processing unit that are initiated by the main processing unit when the given attached processing unit is in the secure mode of operation.