Patent ID: 7709310

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate having current input/output regions; (b) forming an insulating layer on the semiconductor substrate; (c) forming a resist laminate on the insulating layer; (d) forming an upper opening through an upper region of the resist laminate, the upper opening having a laterally broadening middle space; (e) forming a lower opening through a lower region of the resist laminate, the lower opening communicating the upper opening, having a limited size along a current direction, and having generally vertical side walls; (f) etching the insulating layer exposed in the lower opening; (g) performing a heat treatment of the resist laminate to deform the side walls of the lower opening so that at least one of opposite ends of the lower region at the lower opening is retarded from a corresponding end of the insulating layer and that the lower opening has a forward taper shape upwardly and monotonically increasing a size of the lower opening along the current direction; (h) filling a gate electrode stem in the lower opening and forming a head in the upper opening, the head having an expanded size along the current direction; and (i) applying an energy beam to at least one of a pair of regions of the lower region of the resist laminate near the lower opening or a region where the lower opening is formed, wherein the heat treatment of said step (g) forms different taper shapes between a region where the energy beam is applied and a region where the energy beam is not applied, wherein said step (f) forms a contact opening in said insulating layer, and said step (g) is performed after said step (f) to deform the side walls of the lower opening to expose an upper surface of said insulating layer and said contact opening, and said step (h) forms the stem filling said contact opening, riding on said upper surface of the insulating layer in said lower opening.