Patent ID: 7191318

Claim:
A processor comprising: an instruction decoder for decoding instructions in a program being executed by the processor, the instructions including a copy instruction; a plurality of memory resources for storing data, including a register file containing registers that store operands operated upon by the instructions, the registers being identified by operand fields in the instructions decoded by the instruction decoder; a copy unit, activated by the instruction decoder when the copy instruction is decoded, for performing a copy operation indicated by the copy instruction, the copy operation reading a data block from a source resource in the plurality of memory resources, the source resource specified by the copy instruction, the copy operation writing the data block to a destination resource in the plurality of memory resources, the destination resource specified by the copy instruction, the copy operation parsing the data block to create a series of pointers that correspond to a series of data-items within the data block, wherein at least one of the data-items includes a file name or file handle.