Patent ID: 7600065

Claim:
A master that arbitrates for access to a shared memory device, the master comprising: a data processor; and a master memory device having sequences of instructions stored thereon, wherein execution of the sequences of instructions by the data processor causes the data processor to perform the steps of: controlling generation of a series of an indispensable command that is sent to an arbitrator, wherein any activation with a transition of a logical state of a request for access signal is synchronized to a respective generation of the indispensable command such that said activation of the request for access signal is latched within the arbitrator with a respective detection of said respective generated indispensable command; controlling generation of the request for access signal that is sent to the arbitrator together with one indispensable command in the series; and controlling generation of another request for access signal that is sent to the arbitrator together with a subsequent one of the indispensable command in the series when said request that was previously generated is rejected such that a respective approval or rejection for each request for access signal is synchronized to the series of indispensable commands.