Patent ID: 7688933

Claim:
A shift register circuit comprising: plural stages of signal holding circuits which are cascade-connected to hold a first signal based on a supplied input signal, to output an output signal based on the held first signal based on the supplied input signal, and to supply the output signal as the input signal to a subsequent stage; each of the plural stages of signal holding circuits comprising: an output circuit which: (i) is supplied with two types of clock signals comprising a first clock signal and a second clock signal, wherein a rise timing of the second clock signal is between a fall timing of the first clock signal and a rise timing thereof, (ii) is supplied with the input signal in synchronization with the fall timing of the first clock signal, (iii) is supplied with a second signal at a timing delayed by a delay time from a timing of applying the input signal to the rise timing of the second clock signal, and (iv) outputs the output signal at a timing in response to the first clock signal.