Patent ID: 7870454

Claim:
A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a memory; built-in self-test circuitry configured to execute a test algorithm that provides test information to said memory in response to a clock signal over a plurality of clock cycles, said test information comprising expected test data, and said test having a starting point; fail logic circuitry configured to, during execution of said test algorithm from said starting point, cyclically receive actual test values from said memory in response to said clock signal and compare said expected test data to said actual test values in a manner that generates a fail signal each time any one of said actual test values does not match said expected test data, said fail logic circuitry comprising a data register for holding each of said actual test values in seriatim; and test control circuitry configured to cause said built-in self-test circuitry to reload said data register with the one of said actual test values corresponding to a desired occurrence of said fail signal by re-executing said test algorithm from said starting point and stopping the re-execution of said test algorithm upon the re-occurrence of the desired occurrence of said fail signal such that the one of said actual test values corresponding to the desired occurrence of said fail signal is contained in said data register when the re-execution of said algorithm is stopped.