Patent ID: 7602009

Claim:
A non-volatile memory comprising: a non-volatile transistor including: source and drain regions located in a transistor body region, the source and drain regions are laterally spaced apart to form a channel region therebetween; a control gate isolated from and located vertically above the channel region; a multilayer charge trapping dielectric between the control gate and the channel region to trap positively charged holes, wherein the multilayer charge trapping dielectric comprising first, second and third layers of high-K dielectric selected from the group ZrSnTiO, ZrON, ZrTiO 4 , CrTiO 3 and YSiO; a discrete bi-polar junction having an n-type region substantially underlying the channel region, and a p-type region substantially underlying the n-type region; and program circuitry to program the multilayer charge trapping dielectric by uniformly injecting holes onto at least one layer of the first, second or third layers of high-K dielectric.