Patent ID: 7898270

Claim:
An internal voltage test circuit of a semiconductor memory apparatus, the internal voltage test circuit comprising: a comparing unit configured to compare a level of internal voltage with a level of external voltage to output a comparison result as an output signal when a test signal is enabled; and an output selecting unit configured to output the output signal of the comparing unit to a data output pad when the test signal is enabled, and output a data signal to the data output pad when the test signal is disabled, wherein the output selecting unit includes: a first pass gate having an input terminal, which is configured to receive the output signal, a first control terminal, which is configured to receive an inverted test signal, and a second control terminal that is configured to receive the test signal; and a second pass gate having an input terminal, which is configured to receive the data signal, a first control terminal, which is configured to receive the test signal, and a second control terminal that is configured to receive the inverted test signal.