Patent ID: 8309447

Claim:
A method of forming multiple threshold voltage devices on a same semiconductor chip comprising: providing an initial structure including a semiconductor substrate having at least an nMOS device region and a pMOS device region located therein, wherein a high k gate dielectric layer is located atop the semiconductor substrate in each of the device regions; forming a disposable mask atop the high k gate dielectric in each of the device regions; forming a first patterned mask protecting one of device regions, while leaving the other device region unprotected; removing an exposed portion of the disposable mask in the device region not protected by the first patterned mask to expose an underlying portion of the high k gate dielectric layer and removing the first patterned mask; forming a first material stack including a bottom layer comprising either an nFET threshold voltage adjusting material layer or a pFET threshold voltage adjusting material layer in each device region, wherein a portion of the nFET or pFET threshold voltage adjusting material layer is in contact with the exposed portion of the high k gate dielectric layer in the one device region; forming a second patterned mask atop the first material stack in the one device region, while leaving the other device region unprotected; removing exposed material layers within the other device region, stopping atop a portion of the high k gate dielectric layer in the other device region and removing the second patterned mask; forming a second material stack including a bottom layer comprising the other of the pFET or nFET threshold voltage adjusting material layer not present in the first material stack in each device region, wherein a portion of the pFET or nFET threshold voltage adjusting material layer of the second material stack is in contact with the exposed portion of the high k gate dielectric in the other device region; performing an anneal, wherein the portion of the high k gate dielectric layer that is in contact with the nFET threshold voltage adjusting material layer is converted to a dielectric-containing nFET threshold voltage adjusted region and wherein the portion of the high k gate dielectric layer that is in contact with the pFET threshold voltage adjusting material layer is converted to a dielectric-containing pFET threshold voltage adjusted region; and removing all material layers located above the dielectric-containing nFET threshold voltage adjusted region and the dielectric-containing pFET threshold voltage adjusted region.