Patent ID: 7254085

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of memory cells arrayed therein; a plurality of word lines configured to select the memory cells; a plurality of data lines configured to transmit data into and from the memory cells; a first potential line configured to supply a first drive potential to each of the memory cells; a second potential line configured to supply a second drive potential lower than the first drive potential to each of the memory cells; a first additional FET (FET: Field-Effect Transistor) disposed on one potential line of the first and second potential lines, to selectively bring the one potential line into conduction; a selection signal supply line configured to supply a selection signal to a gate terminal of the first additional FET, so as to set the first additional FET in an ON-state, when each of the memory cells is selected; a second additional FET disposed on the one potential line, in parallel with the first additional FET, to selectively bring the one potential line into conduction; and a bias supply line configured to supply a gate terminal of the second additional FET with a bias potential that has first and second levels respectively corresponding to non-selection and selection of each of the memory cells, wherein the second additional FET is turned on, with reference to the bias potential, by a voltage drop generated in the memory cell, and wherein the first level of the bias potential is a potential between the first and second drive potentials, and the second level of the bias potential is closer to one potential of the first and second drive potentials corresponding to the one potential line, than the first level is, wherein the first level of the bias potential is arranged such that the second additional FET is turned on before the voltage drop proceeds to a degree at which data stored in the memory cell is destroyed.