Patent ID: 8120389

Claim:
A clock generation circuit comprising: a reference clock signal input for receiving a reference clock signal; a phase locked loop circuit connected to said reference clock signal input including a phase detector having a first input connected to said reference clock signal input, a second input and an output, said phase detector generating a voltage level at said output corresponding to a phase difference between signals at said first and second inputs, a voltage controlled oscillator generating a plurality of local clock signals having the same frequency and respective differing phases evenly distributed over one cycle, one of said plurality of local clock signals supplied to said second input of said phase detector; a control word input receiving an input digital control word; a modulation function generating a time varying digital dither signal; an adder having a first input receiving said input digital control word, a second input receiving said digital dither signal and an output forming a dithered control word as sum of said input digital control word and said digital dither signal; a flying-adder frequency synthesizer including a multiplexer having a plurality of inputs, a control input and an output, each of said plurality of inputs receiving a corresponding one of said plurality of local clock signals, said multiplexer selecting for output at said output a signal on one of said plurality of inputs corresponding to said control input, a flip-flop having a clock input connected to said output of said multiplexer and an output forming an output clock signal, an adder having a first input receiving said dithered control word, a second input and an output forming a sum of said first and second inputs, and a register for storing a multibit digital control word having an input connected to said output of said adder, a load input connected to said output of said flip-flop and an output connected to said second input of said adder, said register having an integer part of a predetermined number of most significant bits connected to said control input of said multiplexer and a fractional part.