Patent ID: 7701258

Claim:
A latch comprising: an amplifying circuit, for receiving a first biasing current in a first state to amplify an input signal to generate an amplified signal; a latching unit, coupled to the amplifying circuit, for latching the amplified signal and for receiving a second biasing current in a second state to output the amplified signal; and a biasing circuit, coupled to the amplifying circuit and the latching unit, for providing the first biasing current to the amplified circuit in the first state and for providing the second biasing current to the latching unit in the second state, the biasing circuit comprising: a first biasing module, coupled to the amplifying circuit, for providing a third biasing current to the amplifying circuit in the first state; and a second biasing module, coupled to the amplifying circuit and the latching unit, for providing a fourth biasing current to the amplifying circuit in the first state and providing the fourth as the second biasing current to the latching unit in the second state; wherein the first biasing current is equal to a sum of the third biasing current and the fourth biasing current; wherein the first biasing module comprises: a first biasing current source, for providing the third biasing current: a first transistor, having a control end, a first end, and a second end, the control end coupled to a first clock, the first end coupled to the amplifying circuit, and the second end coupled to the first current source; and a second transistor, having a control end, a first end, and a second end, the control end coupled to a common voltage level, and the second end coupled to the first current source: and the second biasing module comprises: a second biasing current source, for providing the fourth biasing current; a third transistor, having a control end, a first end, and a second end, the control end coupled to the common mode voltage level, the first end coupled to the amplifying circuit, and the second end coupled to a second current source; and a fourth transistor, having a control end, a first end, and a second end, the control end coupled to a second clock, and the first end coupled to the latching unit, and the second end coupled to the second current source.