Patent ID: 8669597

Claim:
An integrated circuit memory device comprising: a substrate having a plurality of bit lines; a first inter-level dielectric layer disposed on the substrate and on the plurality of bit lines; a second inter-level dielectric layer disposed on the first inter-level dielectric layer; a plurality of source lines that extend through the first miter-level dielectric layer; a plurality of source line vias that extend through the second inter-level dielectric layer to each respective one of the plurality of source lines; a plurality of bit line contacts that extend through the first inter-level dielectric layer to each respective one of the plurality of bit lines, wherein the plurality of bit line contacts are staggered so that adjacent ones of the bit line contacts are not in a same row; a plurality of bit line vias that extend through the second inter-level dielectric layer to each one of the plurality of bit line contacts, wherein the plurality of bit line vias are staggered so that adjacent ones of the bit line vias are not in a same row; and a metallization layer coupled to one or more of the plurality of source line vias and one or more of the plurality of bit line vias.