Patent ID: 7199425

Claim:
A semiconductor device comprising: a semiconductor substrate provided with an isolation trench filled with an isolation film; and a plurality of non-volatile memory cells provided on the semiconductor substrate, each of the plurality of non-volatile memory cells comprising: a tunnel insulating film provided on the semiconductor substrate; a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in a channel width direction, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof; a control gate electrode above the floating gate electrode; and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode, wherein the plurality of non-volatile memory cells includes a first non-volatile memory cell including a first floating gate electrode and a second non-volatile memory cell, adjacent to the first non-volatile memory cell, including a second floating gate electrode, the isolation film covers lower side portions of the first and second floating gate electrodes in the channel width direction, and the widths of the first and second floating gate electrodes gradually increase, in the channel width direction, toward the lower surfaces of the first and second floating gate electrodes from the upper surface of the isolation film.