Patent ID: 8611122

Claim:
A device comprising: a first region including a plurality of first memory elements and a plurality of first vertical transistors arranged in a single line in a first direction, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding one of the first memory elements and a lower electrode, the first switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the first selective transistors through a first local bit line; a second region including a plurality of second memory elements and a plurality of second vertical transistors arranged in a single line in the first direction, the second vertical transistors comprising a plurality of second selective transistors and a second switching transistor, each of the second selective transistors including an upper electrode coupled to a corresponding one of the second memory elements and a lower electrode, the second switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the second selective transistors through a second local bit line; a third region formed between the first and the second regions and including a first wiring coupled between the upper electrode of the first switching transistor of the first region and the upper electrode of the second switching transistor of the second region; and a global bit line elongated in the first direction and running through the first, second and third regions, wherein the first vertical transistors of the first region further comprise a first connecting transistor including an upper electrode coupled to the global bit line and a lower electrode coupled to the first local bit line, and the second vertical transistors of the second region further comprise a second connecting transistor including an upper electrode coupled to the global bit line and a lower electrode coupled to the second local bit line.