Patent ID: RE41600

Claim:
A liquid crystal display device for receiving horizontal and vertical synchronization signals and at least one analog video signal synchronized with said horizontal synchronization signal from a host and displays an image on a screen thereof said LCD device comprising: a display mode discriminating means for discriminating a display mode supported by said host in response to said horizontal and vertical synchronization signals to generate first and second mode signals and first, second, third and fourth data signals related to said discriminated display mode; a clock generator for generating first and second pixel clock signals in synchronization with said horizontal synchronization signal, said first and second pixel clock signals having frequencies corresponding to said first and second data signals, respectively, a pulse number of said first pixel clock signal corresponding to one horizontal line being equal to a value of said first data signal and a pulse number of said second pixel clock signal corresponding to one horizontal line being equal to a value of said second data signal; an analog-to-digital converter for converting said at least one analog video signal into a digital video signal in synchronization with said first pixel clock signal; a memory for storing said digital video signal; a horizontal output generator for receiving said third and fourth data signals in response to said vertical synchronization signal and generating a horizontal output signal, said digital video signal being read from said memory in synchronization with said horizontal output signal, a pixel number per one cycle of said horizontal output signal being equal to a value of said third data signal, and a pixel number per a pulse width of said horizontal output signal being equal to a value of said fourth data signal; and a memory controller for enabling said digital video signal to be stored in said memory in accordance with said first and second mode signals, said horizonal synchronization signal and said first pixel clock signal, and enabling said digital video signal stored in said memory to be read from said memory in accordance with said second mode signal, said horizontal output signal and said second pixel clock signal.