Patent ID: 8482117

Claim:
A semiconductor device comprising: a first structure including a first substrate and an electronic component, wherein the first substrate includes a first surface and an opposite second surface, and the electronic component is arranged on the first surface of the first substrate and electrically connected to first wiring pattern formed on the first surface of the first substrate by solder; a first sealing resin layer that seals the first structure and is formed on the first surface of the first substrate; a second sealing resin layer that further seals and completely covers the first structure, wherein the second sealing resin layer includes a first surface and a second surface opposite the first surface; an insulation layer formed on the second surface of the first substrate and the first surface of the second sealing resin layer, wherein the insulation layer is larger than the first substrate when viewed from above; a via that extends through the insulation layer and is directly connected to a second wiring pattern formed on the second surface of the first substrate; additional wiring formed on the insulation layer and electrically connected to the electronic component through the first substrate and the via; another insulation layer formed on the second surface of the second sealing resin layer; and further wiring formed on another insulation later.