Patent ID: 7074673

Claim:
A method for forming a programmable logic array, comprising: forming a first logic plane that receives a number of input signals, wherein forming the first logic plane includes forming a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; forming a second logic plane, wherein forming the second logic plane includes forming a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and wherein forming each of the logic cells includes; forming a first source/drain region and a second source/drain region separated by a channel region in a substrate; forming a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide, the floating gate having a metal layer: forming a control gate opposing the floating gate; and forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate, the low tunnel barrier intergate insulator in contact with the metal layer of the floating gate.