Patent ID: 7920085

Claim:
An integrated circuit comprising: a different operational amplifier including a first output, a second output, a first input, and a second input, the operational amplifier being associated with an amplification factor; a first voltage input, the first voltage input being characterized by a first voltage; a second voltage input, the second voltage input being characterized by a second voltage; a first voltage source configured to provide a first reference voltage; a second voltage source configured to provide a second reference voltage; a first capacitor being electrically coupled to the first input and disengageably coupled to the first voltage input, the coupling to the first voltage input being associated with a first clock signal; a second capacitor being electrically coupled to the first input and disengageably coupled to the first voltage input, the coupling to the first voltage input being associated with the first clock signal; a third capacitor being electrically coupled to the second input and disengageably coupled to the second voltage input, the coupling to the second voltage input being associated with the first clock signal; a fourth capacitor being electrically coupled to the second input and disengageably coupled to the second voltage input, the coupling to the second voltage input being associated with the first clock signal; a first switch including a first switching position and a second switching position; a second switch including a third switching position and a third switching position; wherein: if the first switch is at the first switching position, the first capacitor is disengageably coupled to the first output and the second capacitor is disengageably coupled to the first voltage source; if the first switch is at the second switching position, the first capacitor is disengageably coupled to the first voltage source and the second capacitor is disengageably coupled to the first output; if the second switch is at the third switching position, the third capacitor is disengageably coupled to the second output and the second capacitor is disengageably coupled to the second voltage source; if the second switch is at the fourth switching position, the third capacitor is disengageably coupled to the second voltage source and the second capacitor is disengageably coupled to the second output.