Patent ID: 8188894

Claim:
A serial-to-parallel conversion circuit, comprising: a plurality of inputs, each of which being configured to receive a corresponding one of a plurality of serial data streams, each of the plurality of serial data streams including a corresponding one of a plurality of data units that each include a plurality of bits; a plurality of delay circuits, each of which being configured to receive a corresponding one of the plurality of serial data streams; a rotator circuit configured to receive the plurality of serial data streams, each of the plurality of serial data streams being delayed relative to one another by a corresponding one of a plurality of delay times associated with the plurality of delay circuits, the rotator circuit having a plurality of outputs, where each of the plurality of bits within each of the plurality of the data units is supplied to a corresponding one of the plurality of outputs of the rotator circuit; and a plurality of register circuits receiving the plurality of data units of the plurality of serial data streams, the plurality of register circuits being configured to output, in parallel, said each of the plurality of bits within said each of the plurality of data units.