Patent ID: 7812375

Claim:
A non-volatile memory device comprising: a first isolation layer formed with a plurality of depressions in a semiconductor substrate, where the depressions have a predetermined depth from an upper surface of the semiconductor substrate; a fin type first active region defined by the first isolation layer and having one or more inflected portions at its side walls exposed from the first isolation layer, where the first active region is divided into an upper portion and a lower portion by the inflected portions and a width of the upper portion is narrower than a width of the lower portion; a tunneling insulation layer formed on the first active region; a storage node layer formed on the tunneling insulation layer; a blocking insulation layer formed on the storage node layer; and a control gate electrode formed on the blocking insulation layer, wherein the inflected portion comprises a convex portion and a concave portion and wherein a top surface of the fin type active region is positioned above a top surface of the first isolation layer in the depressions.