Patent ID: 7566935

Claim:
An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND); a first Nwell formed in the P-type substrate; one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad; at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND; at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region; and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND; wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.