Patent ID: 8470660

Claim:
A method of manufacturing, comprising: providing a substrate having a source region and a drain region; forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region by etching a top surface of the substrate, the first recess having a first plurality of surfaces and the second recess having a second plurality of surfaces; epi-growing a semiconductor material in the recess of the source region and in the recess of the drain region; etching the top surface of the substrate adjacent to the source region thereby forming a first trench and exposing a surface of the epi-grown semiconductor material in the source region; etching the top surface of the substrate adjacent to the drain region thereby forming a second trench and exposing a surface of the epi-grown semiconductor material in the drain region; and depositing a dielectric material in the first and second trenches thereby forming shallow trench isolation (STI) features.