Patent ID: 7944930

Claim:
A packet-processing apparatus, comprising: a first memory; a second memory; a first functional unit to logically configure the first memory into blocks, wherein the blocks are logically configured into particles, and to logically configure the second memory into partitions so that there is a one-to-one correspondence between the blocks and the partitions, wherein for each particle in a block there corresponds a fixed number of storage bits in the partition in the second memory corresponding to the block; and a second functional unit configured to: store a packet in at least one particle in the first memory; store a packet information corresponding to the packet in at least some of the storage bits in the second memory corresponding to the at least one particle, each of the storage bits which correspond to the at least one particle in which the packet is stored being associated with the packet, so that the number of storage bits which are associated with the packet being indicative of a length of the packet; store a type bit in at least some of the storage bits in the second memory corresponding to the at least one particle, type bit designating whether the at least one particle in which the packet is stored number more than a threshold number of particles; and when the at least one particle in which the packet is stored number more than the threshold number of particles, store in the second memory a pointer to a last block in the first memory in which the packet is stored.