Patent ID: 8252691

Claim:
A method of forming semiconductor patterns, the method comprising: forming a photo resist template having a pattern of lines on a bottom layer, the pattern having a line width and a line spacing, the ratio of the line width to the line spacing being 1:A wherein 1≦A<3; depositing a spacer oxide conformal over the photo resist template by a Plasma Enhanced Atomic Layer deposition process, using sequential and alternating pulses of a silicon precursor and an oxygen plasma, such that trimming of the photo resist template occurs and the ratio of the line width to the line spacing becomes 1:3 and the thickness of the deposited spacer oxide is about equal to the trimmed line width, wherein the silicon precursor is SiH 2 [N(C 2 H 5 ) 2 ] 2 ; etching back the deposited spacer oxide such that spacer oxide films on upper and bottom surfaces of the pattern are removed, with spacer oxide films on side wall surfaces of the photo resist template remaining; removing the photo resist template remaining between the spacer oxide films by selective etching; and patterning the bottom layer by using the remaining spacer oxide films formed as mask.