Patent ID: 8607337

Claim:
A data scanning circuit comprising: a memory circuit configured to pre-store a plurality of codes that together form a rule, which, when satisfied, allows the data scanning circuit to prevent further processing of undesirable data, each code corresponding to a sub-rule and comprising plural bits, the memory circuit further configured to receive input data comprising at least a first data item and a second data item, and output a first of the plurality of codes and a second of the plurality of codes according to the first data item and the second data item, respectively, wherein the memory circuit is a static random access memory (SRAM); an operational circuit coupled to the memory circuit, the operational circuit configured to perform logic operations on a clock-shifted version of the first code and the second code to produce an operated result, the operated result based on the clock-shifted version of the first code and the second code, the logic operations including an AND logical operation; and a decision circuit coupled to the operational circuit, the decision circuit configured to analyze the operated result to determine whether the input data satisfies the rule.