Patent ID: 7850127

Claim:
A processor comprising: a first field programmable gate array comprising: a first central processing unit core programmed to perform a first function, and first programmable hardware logics programmed to perform a second function; and a second field programmable gate array comprising: a second central processing unit core programmed to perform a third function, and second programmable hardware logics programmed to perform a fourth function; and a communication interface between said first and second central processing unit cores, wherein said second field programmable gate array is diverse with respect to said first field programmable gate array, wherein a portion of the first function is structured to communicate first information from said first central processing unit core to said second central processing unit core through said communication interface, wherein a portion of the third function is structured to communicate second information from said second central processing unit core to said first central processing unit core through said communication interface, and, otherwise, said first function is substantially the same as said third function, and wherein said second function is substantially the same as said fourth function.