Patent ID: 8762973

Claim:
An information processing apparatus comprising: at least two CPUs; and a storage unit that stores a compilation result of an intermediate code instruction, wherein one CPU comprises: an intermediate code interpretation unit that sequentially reads, from a predetermined program described with intermediate code instructions, the intermediate code instructions along an execution route that is an order to execute each intermediate code instruction; determining whether or not there is a compilation result of the intermediate code instruction that has been read in the storage unit; when there is no compilation result of the intermediate code instruction, interpreting the intermediate code instruction; and, when there is a compilation result of the intermediate code instruction, designating the compilation result; and a program execution unit that, when an interpretation result of the intermediate code instruction is received from the intermediate code interpretation unit, executes the program by executing the intermediate code instruction based on the interpretation result and, when a designation of a compilation result is received from the intermediate code interpretation unit, executes the program by executing a native code that is the designated compilation result, and the other CPU comprises: a compilation execution unit that compiles the intermediate code instruction interpreted by the intermediate code interpretation unit to generate a native code and stores the generated native code in the storage unit.