Patent ID: 8756393

Claim:
A control circuit, comprising: a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, a write control circuit for executing write commands, wherein the write control circuit is adapted to start executing a write command when the write signal is applied to the write signal connection at a first edge of the system clock signal, wherein the write control circuit comprises a plurality of configuration signal connections for receiving configuration information, wherein the configuration information comprises information about a set write latency, and write operations are executed within a time that is shorter than the set write latency, and wherein the write control circuit is adapted to use a clock period, which precedes a second edge of the system clock signal that prompts the execution of the write command, as a first clock period of the set write latency, a read signal connection for receiving a read signal, and a read control circuit for executing read commands, wherein the read commands and the write commands are executed in different clock domains.