Patent ID: 8706789

Claim:
An apparatus comprising: a processor having an execution unit including a plurality of logic units to execute instructions, the execution unit including: a first selector to select a first portion or a second portion of an input operand based on whether an instruction is to perform a reciprocal operation or a square root reciprocal operation; a lookup table coupled to the first selector and including a plurality of entries, wherein the output of the first selector is to access a given one of the plurality of entries, each of the entries including a first term, a second term, and a legacy portion, wherein the first and second terms are set at a midpoint of an interval; a reciprocal logic unit including a plurality of levels of carry save adders (CSA) to receive the accessed entry and a portion of the input operand and to generate a reciprocal result for the input operand responsive to the instruction, wherein the first term is to be provided from the lookup table to a first level of the CSA adders; an encoder to receive a selection signal from a second selector, the second selector to output a portion of the input operand if the instruction is a reciprocal instruction or a square root reciprocal instruction and is to output a first value instead if the instruction is a legacy instruction; and wherein the legacy portion is used to generate a legacy result when the instruction is one of a legacy reciprocal instruction and a legacy square root reciprocal instruction.