Patent ID: 7539073

Claim:
A semiconductor memory device having a shared bit line sense amplifier structure, the semiconductor memory device comprising: a plurality of cell arrays each of which has a plurality of bit line pairs, the cell arrays including a first cell array disposed at an edge portion of a cell region and a second cell array disposed adjacent to the first cell array; a first precharging unit for precharging some bit line pairs of the first or second cell array; a second precharging unit for precharging the other bit line pairs of the first cell array; and an auxiliary precharging unit for assisting a precharge operation of the second precharging unit, wherein the auxiliary precharging unit includes: an auxiliary-precharging MOS transistor for connecting the bit line pairs with one another in response to an equalization signal; first and second MOS transistors for connecting one terminal and the other terminal of the auxiliary-precharging MOS transistor with the second precharging unit, respectively; and first and second connecting wires for connecting a drain and a source of the first and second transistors.