Patent ID: 7715266

Claim:
A memory detecting circuit, comprising: a first switch element comprising: a first end arranged to receive a standby power, and also connected to memory sockets of a first channel to receive a first memory detecting signal; a second end arranged to receive the standby power; and a third end grounded; a second switch element comprising: a first end connected to the first end of the first switch element; a second end connected to the standby power; and a third end; a third switch element comprising: a first end arranged to receive the standby power, and also connected to memory sockets of a second channel to receive a second memory detecting signal; a second end connected to the third end of the second switch element; and a third end grounded; a fourth switch element comprising: a first end connected to the first end of the third switch element; a second end connected to the second end of the first switch element; and a third end grounded; a fifth switch element comprising: a first end connected to the second end of the fourth switch element; a second end connected to the second end of the second switch element; and a third end grounded; a first indication device connected to the second end of the second switch element; and a second indication device connected to the second end of the fourth switch element; wherein upon the condition that memories are only installed into the memory sockets of the first channel, the first memory detecting signal is at a low voltage level, and the second memory detecting signal is at a high voltage level, thereby the first switch element and the second switch element are turned off, the third switch element and the fourth switch element are turned on, and the fifth switch element is turned off, so that the first indication device indicates the memories run in a single channel mode; wherein upon the condition that the memories are only installed into the memory sockets of the second channel, the first memory detecting signal is at a high voltage level, and the second memory detecting signal is at a low voltage level, thereby the first switch element and the second switch element are turned on, the third switch element and the fourth switch element are turned off, and the fifth switch element is turned off, so that the first indication device indicates the memories run in the single channel mode; and wherein upon the condition that the memories are installed into the memory sockets of the first and the second channels respectively, the first and second memory detecting signals are both at a low voltage level, thereby the first switch element, the second switch element, the third switch element and the fourth switch element are turned off, and the fifth switch element are turned on, so that the second indication device indicates the memories run in a dual channel mode.