Patent ID: 7689762

Claim:
A method, comprising: designating a reference memory location at a first physical memory address in a memory device; designating a target memory location at a second physical memory address in the memory device, the target memory location being designated for storing data in the memory device; in response to data being stored to the target memory location, incrementing the second physical memory address for the target memory location; determining that the second physical memory address for the target memory location has been incremented to the first physical memory address for the reference memory location; and in response to determining that the second physical memory address for the target memory location has been incremented to the first physical memory address for the reference memory location: incrementing the first physical memory address for the reference memory location when the first physical memory address is not mapped to a logical address; and leveling the reference memory location referenced by the first physical memory address when the first memory location is mapped to a logical address.