Patent ID: 7408394

Claim:
A measure controlled delay circuit, comprising: a measuring delay line circuit having a plurality of delay units connected in series and adapted to receive a first input signal, the measuring delay line circuit operable to hold a first logic state in each delay unit as the first input signal is propagated consecutively through the delay units, the measuring delay line circuit further adapted to receive a second input signal, each of the delay units being operable responsive to receiving the second input signal to assert the first logic state if the first input signal has propagated through and assert a second logic state if the first input signal has not propagated through the respective delay unit; and a signal generating delay line circuit having a plurality of delay units connected in series and adapted to receive at least a third input signal, each of the delay units of the signal generating delay line circuit adapted to receive the logic state of a corresponding delay unit of the measuring delay line circuit, the signal generating delay line circuit operable to generate an output signal by propagating at least the third input signal through a substantially equal number of delay units in the signal generating delay line circuit as the number of delay units through which the first input signal propagated through in the measuring delay line circuit.