Patent ID: 8868833

Claim:
A processor arrangement, comprising: a plurality of processors; a plurality of first-level instruction caches coupled to the plurality of processors; a plurality of first-level data caches coupled to the plurality of processors, respectively; at least one second-level cache coupled to the plurality of first-level instruction caches and to the plurality of first-level data caches; at least one shared memory coupled to the second-level cache for storing a plurality of data items, each data item having an associated cache control tag; and cache control circuitry coupled to the plurality of processors, to the plurality of first-level caches, and to the second-level cache, the cache control circuitry, responsive to a request from one of the plurality of processors for access to a data item, configured to: cache the data item in the respective one of the plurality of first-level caches in response to a first value of the cache control tag associated with the data item; and cache the data item in the second-level cache and not in any of the plurality of first-level caches in response to a second value of the cache control tag associated with the data item; wherein: data items with the cache control tag having the first value include constant values, read-only data items, and data items for which only one of the plurality of processors has write access; and data items with the cache control tag having the second value include data items for which at least one of the plurality of processors has write access and at least one other of the plurality of processors has read or write access.