Patent ID: 7034351

Claim:
A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, the memory device comprising: an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line; a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus; a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises: an active region formed in the substrate; an epitaxial post formed on a surface of the substrate over the active region, the epitaxial post defined by at least one surface facing away from the surface of the substrate and at least two peripheral surfaces; a transfer gate formed adjacent to the at least two peripheral surfaces of the epitaxial post; and a memory cell capacitor formed on an exposed surface of the epitaxial post.