Patent ID: 7003683

Claim:
For use with a clocked circuit, a clock selection circuit capable of receiving a first input clock signal and a second input clock signal and outputting to said clocked circuit a selected clock signal derived from one of said first and second input clock signals, said clock selection circuit comprising: a first clock control circuit that receives said first input clock signal and a first start signal, wherein said first start signal, when asserted, is capable of causing said first clock control circuit to output a first gated clock signal; a second clock control circuit that receives said second input clock signal and a second start signal, wherein said second start signal, when asserted, is capable of causing said second clock control circuit to output a second gated clock signal; a first interlock circuit that detects when said first clock control circuit begins outputting said first gated clock signal and, in response to said detection, that asserts a first disable signal capable of preventing said second clock control circuit from outputting said second gated clock signal; a second interlock circuit that detects when said second clock control circuit begins outputting said second gated clock signal and, in response to said detection, that asserts a second disable signal capable of preventing said first clock control circuit from outputting said first gated clock signal; and a first OR gate that receives said first and second gate clock signal and outputs said selected clock signal; wherein the first clock control circuit comprises a first flip-flop, a second flip-flop coupled in series with the first flip-flop, and a second OR gate having a first input coupled to an output of the first flip-flop and a second input coupled to an output of the second flip-flop.