Patent ID: 7050351

Claim:
A memory device comprising: a first subarray of memory cells organized into rows and columns; a first plurality of bit lines, each coupled to a column of memory cells; a first set of subarray isolators to selectively couple the first plurality of bit lines to a first row of sense amplifiers; a first set of common isolators to selectively couple the first row of sense amplifiers to a plurality of global I/O lines; and isolator control logic to coordinate the operation of the first set of subarray isolators to allow data in a row of memory cells within the first subarray to be copied to and latched by the first row of sense amplifiers, to coordinate the operation of the first set of common isolators to allow data latched by the first row of sense amplifiers to be transmitted to the plurality of global I/O lines, and to coordinate the operation of the first set of subarray isolators to prevent the loss of data latched by the first row of sense amplifiers by a precharge operation carried out to precharge the first plurality of bit lines.