Patent ID: 7571365

Claim:
An integrated circuit die, comprising: A. combinational logic core circuitry formed on the die; B. test access port (TAP) circuitry formed on the die and coupled to the combinational logic core circuitry, the test access port circuitry having a test data input (TDI) lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data output (TDO) lead; C. parallel scan path circuitry formed on the die and coupled to the combinational logic core circuitry and the test access port circuitry, the parallel scan path circuitry including serial input parallel output (SIPO) circuitry having an input coupled to the TDI lead and plural data output leads, plural scan paths coupled to the combinational logic core circuitry, each scan path having a serial data input connected to a data output of the SIPO and having a serial data output, and parallel input serial output (PISO) circuitry having plural data input leads, each connected to a serial data output of one scan path and an output coupled to the TDO lead; and D. die channel circuitry formed on the die, the die channel circuitry having a data I/O (DIO) bidirectional lead, a clock (CLK) input lead, a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead, the die channel circuitry including: i. a simultaneous bidirectional transceiver (SBT) connected to the DIO bidirectional lead and having an input connected to the TDO input lead, and a serial output lead; and ii. serial input parallel output (SIPO) circuitry having an input connected to the serial output lead of the simultaneous bidirectional transceiver, a clock input connected with the clock input lead, a TDI output connected to the TDI output lead, and a TMS output connected to the TMS output lead.