Patent ID: 8236613

Claim:
A wafer level chip scale package encapsulation method comprising the following steps: step 1: forming a plurality of semiconductor chips on a top portion of a wafer wherein each semiconductor chip is provided with a plurality of top electrode contact areas; step 2: forming a plurality of grooves on the top portion of the wafer alongside the semiconductor chips, each semiconductor chip corresponding to a groove; step 3: providing a clip array comprising a plurality of clip units connected by a clip array framework, each clip unit comprising a plurality of clip contact areas corresponding to the top electrode contact areas of each semiconductor chip, each clip contact area extending to a down set connecting bar; step 4: disposing the clip array on top of the wafer with the plurality of clip units aligned and superimposed on the plurality of the semiconductor chips, wherein each top electrode contact area connects to a corresponding clip contact area of a clip unit superimposed over the semiconductor chip, wherein the down set connecting bars are disposed inside the groove corresponding to the semiconductor chip; step 5: providing a molding material to encapsulate the top portion of the wafer and at least a portion of the clip, wherein the molding material substantially fills the groove; step 6: thinning the bottom portion of the wafer; and step 7: dicing the wafer into a plurality of wafer level chip scale packages.