Patent ID: 7210083

Claim:
A system for implementing postponed quasi-masking test output compression in an integrated circuit, comprising: a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs, said test response indicating faults in said integrated circuit, M and N being positive integers; and a correctable multiple input signature register with a size of M, communicatively coupled to said compressor, for receiving said M outputs from said compressor as data inputs (s[ 0 ], . . . , s[M−1]) and receiving M correction bits (c[ 0 ], . . . , c[M−1]) and L address bits (a[ 0 ], . . . , a[L−1]) as correction inputs, L being a positive integer, 2 L >=M, wherein said correctable multiple input signature register is suitable for detecting said faults when there is no or at least one unknown value in said test response.