Patent ID: 6871338

Claim:
A method for designing a semiconductor integrated circuit device, the method comprising: a first step of producing, for a plurality of placement regions on each of which a design pattern is to be placed, first layout data having a first expected value based on a first layout design rule; a second step of producing, if a difference between the first expected value and an expected finished size after fabrication of the first layout data falls within a first predetermined error tolerance, first OPC data by correcting the first layout data; a third step of producing, if the plurality of placement regions include an out-of-tolerance region for which the first OPC data falling outside the first predetermined error tolerance, second layout data having a second expected value for only the out-of-tolerance region based on a second layout design rule; a fourth step of producing second OPC data by correcting the second layout data such that an expected finished size after fabrication of the second layout data falls within a second predetermined error tolerance; and a fifth step of producing mask data by using the first OPC data and the second OPC data, wherein: the first layout design rule is different from the second layout design rule, and the first layout data is different from the second layout data.