Patent ID: 7215169

Claim:
An apparatus, comprising: a first circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process a first signal thereby generating a second signal there from, wherein the first signal is a differential signal; a second circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process a third signal thereby generating a fourth signal there from, wherein the second signal is a differential signal; and a third circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to: receive the second signal; receive the fourth signal; and process the second signal and the fourth signal thereby generating a fifth signal there from.