Patent ID: 7692231

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a mask pattern over a semiconductor substrate to define a channel region; etching a portion of the semiconductor substrate using the mask pattern as an etching mask to form a first pillar; forming a spacer over a sidewall of the mask pattern and the first pillar; etching a portion of the semiconductor substrate exposed between the first pillar and an adjacent first pillar using the spacer and the mask pattern as an etching mask to form a second pillar elongated from the first pillar; selectively etching a portion of the second pillar to form a third pillar; removing the spacer and the mask pattern; implanting an impurity into an upper part of the first pillar and the semiconductor substrate between the third pillar and an adjacent third pillar to form a source/drain region; forming a surrounding gate over an outside of the third pillar; forming a first insulating film over the semiconductor substrate the surrounding gate and the first pillar; selectively etching the first insulating film and a portion of the semiconductor substrate between the surrounding gate to form a recess for bit line isolation; subjecting the first insulating film to a reflow process to fill the recess; etching a portion of the first insulating film using a mask defining a word line; forming the word line to electrically connect with the surrounding gate; forming a second insulating film over the word line; polishing the second insulating film until a top surface of the first pillar is exposed; forming a storage node contact by selectively epitaxial-growing the exposed top surface of the first pillar as a seed layer; and forming a third insulating film over the second insulating film and the storage node contact.