Patent ID: 8154112

Claim:
A semiconductor memory apparatus comprising: a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of said wiring substrate; a first semiconductor device including electrode pads arranged along one external side of said wiring substrate, said first semiconductor device being mounted on said device mounting part of said wiring substrate so that pad arrangement sides all face in the same direction; a second semiconductor device including electrode pads arranged along at least one external side of said wiring substrate, and stacked on said first semiconductor device; an external connection terminal formed on another exterior side of said wiring substrate; a first metallic wire which electrically connects said electrode pads of said first semiconductor device with said connection pads of said wiring substrate; a second metallic wire which electrically connects said electrode pads of said second semiconductor device with said connection pads of said wiring substrate, and a third metallic wire which electrically connects said electrode pads of said first semiconductor device with said electrode pads of said second semiconductor device; wherein said electrode pads of said first semiconductor device and said electrode pads of said second semiconductor device are arranged parallel to an arrangement position of said connection pads of said wiring substrate, and said connection pads are electrically connected with said external connection terminal via an internal wiring.