Patent ID: 8124469

Claim:
A method of manufacturing an integrated circuit chip with a top voltage supply rail and a bottom voltage supply rail comprising: providing a plurality of metal layers defining at least one filler cell by manufacturing a first field effect transistor of a first type conductivity; arranging a first source electrode and a first drain electrode of a first field effect transistor to be directly connected together to form a short circuit together so as to act as a capacitor with respect to the bottom voltage supply rail to which at least one of the first source electrode or the first drain electrode is connected; providing a first gate electrode for the first field effect transistor that is electrically isolated from the first source electrode and the first drain electrode; providing a second field effect transistor of an opposite-type conductivity to the first field effect transistor; connecting a second source electrode or a second drain electrode of the second field effect transistor in series between the top voltage supply rail and the first gate electrode of the first field effect transistor; providing a second gate electrode for the second field effect transistor; and connecting the second gate electrode to a ground potential via a resistor.