Patent ID: 7325215

Claim:
A method of developing a circuit design, comprising the steps of: (A) generating a violation display based on violation information provided from a place-and-route tool, said violation display being viewable by a user and depicts (i) a plurality of performance violations in said circuit design and (ii) a plurality of user selectable buttons each associated with one of said performance violations; (B) generating a layout display based on layout information provided from said place-and-route tool, said layout display being viewable by said user and depicts a layout view of said circuit design, said layout view highlighting at least one element of (i) a plurality of cells and (ii) a plurality of networks, wherein each of said at least one element is along a path related to a particular one of said performance violations identified by said user through said user selectable buttons; and (C) generating a crosstalk display based on crosstalk information from said place-and-route tool in response to said user identifying a particular crosstalk violation of said performance violations, said crosstalk display being viewable by said user and depicting (i) a victim network in said circuit design associated with said particular crosstalk violation and (ii) up to a predetermined number of aggressor networks in said circuit design contributing to said particular crosstalk violation.