Patent ID: 6972211

Claim:
A method of forming a resistive memory array comprising: a) providing a substrate; b) implanting ions into the substrate to form a doped-well having a depth; c) depositing and patterning a polysilicon layer over the doped-well; d) etching the substrate to form trenches deeper than the depth of the doped-well and define doped lines; e) filing the trenches with oxide; f) polishing the oxide until reaching the polysilicon; g) removing the polysilicon; h) forming patterned lines perpendicular to the doped lines; i) depositing a second layer of oxide over the patterned lines; j) polishing the oxide and patterned lines down to the level of the first layer of oxide; k) removing the patterned lines; l) forming spacers by depositing a third layer of oxide and then plasma etching to expose select regions of the doped lines; m) implanting ions into the exposed regions, whereby a diode is formed; n) depositing bottom electrodes over the exposed regions and polishing the bottom electrodes level with the first oxide layer; o) depositing a resistive memory material overlying the bottom electrodes; and p) forming top electrodes overlying the resistive memory material and aligned with the bottom electrodes.