Patent ID: 7741149

Claim:
A method of fabricating a chip package structure, comprising: providing a metal thin plate comprising an upper surface and a lower surface, wherein the upper surface of the metal thin plate has a first protrusion part, a second protrusion part, and a plurality of third protrusion parts, the second protrusion part being sandwiched between the first protrusion part and the third protrusion parts, the first, the second, and the third protrusion parts being connected to one another; providing a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface; adhering the back surface of the chip to the first protrusion part; forming a plurality of first bonding wires and a plurality of second bonding wires, wherein the first bonding wires respectively connect the chip bonding pads and the second protrusion part, and the second bonding wires respectively connect the second protrusion part and the third protrusion parts; forming an upper encapsulant encapsulating the upper surface of the metal thin plate, the chip, the first bonding wires and the second bonding wires; forming an etching mask on the lower surface to expose the connections among the first, the second, and the third protrusion parts; and etching the metal thin plate to an extent that the first, the second, and the third protrusion parts are electrically insulated, such that the first protrusion part constructs a die pad, the second protrusion part forms a bus bar, and the third protrusion parts form a plurality of leads.