Patent ID: 7225446

Claim:
A processor switchable between a first execution mode and a second execution mode, the processor having a first processor context when in the first execution mode and a second processor context, larger than the first processor context, when in the second execution mode, wherein the processor is arranged to execute a plurality of threads on a time share basis, the threads being able to change execution mode, and wherein the processor is arranged to generate an exception when the processor attempts to change from one execution mode to the other to keep track of when the execution modes are used and control which processor contexts are preserved at which times; the number of threads in the second execution mode at any one time being limited, to limit the number of times that the second processor context is preserved and restored; the number of threads that may be in the second execution mode at any one time being less than the total number of threads that may be active on the processor at any one time; the processor being arranged such that, when said exception has been generated, a check is carried out to determine whether the thread that caused the exception is allowed to enter the second execution mode; the check determining whether a predetermined number of other threads are already in the second execution mode; wherein the processor is arranged such that, if a predetermined number of other threads are already in the second execution mode, execution of the thread that caused the exception is suspended until the number of other threads that are in the second execution mode is less than the predetermined number.