Patent ID: 8334174

Claim:
A fabrication method of a chip scale package, comprising the steps of: providing a carrier board having an adhesive layer; mounting at least a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, on the adhesive layer via the active surface thereof; bonding a composite board to the adhesive layer of the carrier board, the composite board comprising a hard layer and a soft layer, wherein the soft layer has opposite first and second surfaces, the hard layer is disposed on the second surface of the soft layer, and the composite board is bonded to the adhesive layer via the first surface of the soft layer in a manner that the chip is embedded in the soft layer; removing the carrier board having the adhesive layer so as to expose the active surface of the chip and a portion of the first surface of the soft layer; forming a first dielectric layer on the first surface of the soft layer and the active surface of the chip, followed by forming a plurality of openings in the first dielectric layer to expose the electrode pads of the chip, respectively, and forming at least a through hole penetrating the first dielectric layer, the soft layer, and the hard layer; and forming on the first dielectric layer a first wiring layer electrically connected to the electrode pads of the chip, forming a second wiring layer on the hard layer, and forming a conductive through hole in the through hole to electrically connect the first and second wiring layers.