Patent ID: 7486556

Claim:
A semiconductor memory comprising: a select gate formed in a meandering pattern; a plurality of floating gates coupled with said select gate, said plurality of floating gates including: a first floating gate arranged to have its gate width defined along a first direction; and a second floating gate arranged to be adjacent to said first floating gate and to have its gate width defined along a second direction perpendicular to said first direction, a plurality of memory cells sharing said select gate and each having one of said plurality of floating gates, said plurality of memory cells including first and second memory cells; a plurality of transistors connected respectively to outputs of said plurality of memory cells, said plurality of transistors including first and second transistors; and a control circuit for controlling said plurality of transistors, wherein, in writing data to said first memory cell, said control circuit turns on, out of said plurality of transistors, said first transistor connected to said first memory cell and said second transistor connected to said second memory cell to which current flows from said first memory cell.