Patent ID: 7795122

Claim:
A method of forming a transistor on a semiconductor substrate, the method comprising: forming a gate on the semiconductor substrate; after forming the gate, forming at least one first sidewall spacer on the semiconductor substrate adjacent to at least one side of the gate; after forming the at least one first sidewall spacer, implanting a source/drain dopant in the semiconductor substrate on each side of the gate and adjacent to the gate and first sidewall spacer to form a source region and a drain region; after implanting the source/drain dopant, performing a first anneal of the semiconductor substrate to activate the source/drain dopant; after implanting the source/drain dopant, removing the at least one first sidewall spacer; after performing the first anneal and after removing the at least one first sidewall spacer, implanting antimony in the semiconductor substrate between the source/drain region and the gate to form a source/drain extension region; and after implanting antimony, performing a second anneal of the semiconductor substrate to activate the antimony implant; the second anneal being conducted at a temperature within a range of approximately 1100° C. to 1400° C. for a time duration on the order of a tenth of a millisecond to approximately one millisecond.