Patent ID: 8189360

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a first element region disposed on the semiconductor substrate including; a first bent portion formed of a rectangular region, and a pair of first straight line portions connected to opposite both ends of the first bent portion respectively, extending in an opposite direction each other along a first direction, a width of the pair of first straight line portions being less than the width of the first bent portion; a second element region disposed on the semiconductor substrate including; a second bent portion formed of a rectangular region, and a pair of second straight line portions connected to opposite both ends of the second bent portion respectively, extending in an opposite direction each other along the first direction, and wherein a width of the pair of second straight line portions being less than the width of the second bent portion, and the first and second element regions are disposed so as to interpose an element isolation region having Feature Size Line Space therebetween, and the first and second bent portions are disposed along a second direction with an acute angle with respect to the first direction; contact plugs connected to respective first and second bent portions; first and second select transistors disposed in the first and second element regions respectively, adjacent to the contact plugs; select gate lines connected to the first and second select transistors extending in the second direction; and a plurality of word lines commonly connected to the memory cells in the first and second element regions, the word lines extending in the second direction in parallel with the select gate lines on an opposite side of the bent portion with respect to the select gate line.