Patent ID: 8732499

Claim:
A state retention component configured to form part of data processing circuitry, said state retention component configured to hold a state value at a node of said data processing circuitry when said data processing circuitry enters a low power mode, said state retention component comprising: a scan input, said state retention component configured, when a scan enable signal is asserted, to read in said state value from a scan input value applied at said scan input; a scan output, said state retention component configured, when said scan enable signal is asserted, to read out said state value to said scan output, wherein said state retention component is configured, when said scan enable signal is not asserted and said data processing circuitry is in said low power mode, to output at said scan output a parity value; and combinatorial function circuitry configured to generate said parity value on the basis of said state value and said scan input value, said combinatorial function circuitry configured such that said parity value inverts if either said state value or said scan input value changes, wherein said state retention component is provided with a retention voltage supply, said retention voltage supply configured to provide a sufficient voltage to hold said state value at said node of said data processing circuitry when said data processing circuitry enters said low power mode, wherein said combinatorial function circuitry is powered by said retention voltage supply.