Patent ID: 8604833

Claim:
An integrated circuit device comprising: at least one data processing circuit comprising an input stage, a combinatorial logic stage, and an output stage, wherein said input stage is responsive to a clock signal, and arranged to receive at least a first set of data signals and a second set of data signals, provide said first set of data signals to an input of said combinatorial logic stage during a first portion of a period of said clock signal, and provide said second set of data signals to said input during a second portion of said period, and said output stage is responsive to said clock signal, and arranged to receive from an output of said combinatorial logic stage at least a first result signal as a function of said first set of data signals during a first portion of a subsequent period of said clock signal, and receive from said output at least a second result signal as a function of said second set of data signals during a second portion of said subsequent period.