Patent ID: 7073048

Claim:
An array of microcomputers comprising at least a first microcomputer and a second microcomputer, said array comprising: a compound instruction register within the first microcomputer for receiving a first compound instruction that includes a cascade operation code (opcode) that, upon decoding, indicates whether the first instruction is to be sent to the second microcomputer in the array for execution; decode logic within the first microcomputer that fetches and decodes the first compound instruction from the register; a cascaded instruction pipeline for sending the first instruction to the second microcomputer for execution when the decoded cascade opcode indicates that the first instruction is to be sent to the second microcomputer; execution logic within the second microcomputer that executes the first instruction and determines a result; and a cascade response bus for sending the result from the second microcomputer to the first microcomputer; wherein the second microcomputer executes an application program until a compound instruction is received from the first microcomputer indicating that the second microcomputer is to execute the instruction, said compound instruction having priority over the application program.