Patent ID: 7492807

Claim:
A method for synchronizing interconnects in a link system, the method comprising: receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler, wherein the synchronizing comprises: transmitting from the transmit side to the receive side a synchronization notification via an out-of-band communication; transmitting from the transmit side all zero bits to the receive side; loading a scrambling pattern into the at least one pseudo-random bit sequence scrambler and transmitting the scrambled data from the transmit side to the receive side; detecting a state transition within the transmitted scrambled data employing an edge detection device positioned at the receive side of one of the plurality of lanes used as a synchronization lane; loading and initiating within the at least one pseudo-random bit sequence descrambler a predetermined descrambling pattern; de-scrambling the transmitted scrambled data at the receive side resulting in the input data; after completing the synchronizing, performing a skew correction on the synchronization lane by adjusting at least one FIFO pointer on the synchronization lane; and after skew correcting the synchronization lane, performing a skew correction on any remaining skewed lanes of the plurality of lanes by adjusting at least one FIFO pointer on each of the skewed lanes.