Patent ID: 8205135

Claim:
A memory, comprising: a memory core; a receiver block that receives a command indicating an operation and error detection/correction (EDC) data, and in response, generates an internal command, internal EDC data, and an internal address; a decoding/execution block that decodes the command in parallel with beginning execution of an EDC operation using the EDC data, immediately executes the operation without regard to completion of the EDC operation unless the command is a write command, but delays execution of the operation if the command is a write command until completion of the EDC operation, wherein the decoding/execution block comprises: an error decoder that receives the internal EDC data, the internal command and the internal address and in response generates an error signal; a command decoder that receives the internal command and in response generates a plurality of control signals including a write enable signal; and a write signal transfer block that receives the write enable signal and the error signal and in response generates a final write enable signal applied to the memory core to execute a write operation.