Patent ID: 8020134

Claim:
A method for processing a semiconductor chip design, comprising: flattening a netlist corresponding to the semiconductor chip design to produce a flattened netlist, wherein the flattened netlist comprises a plurality of logic elements and a plurality of interconnects; constructing an initial placement of the plurality of logic elements and the plurality of interconnects on a silicon substrate; performing logic clustering on the plurality of logic elements to generate one or more clusters, wherein the logic clustering is performed subsequently to the constructing; and partitioning the semiconductor chip design in accordance with the one or more clusters to form at least two partitions wherein the partitioning is performed in accordance with a slicing-based greedy algorithm that performs steps comprising: discretizing a placement image of the semiconductor chip design into a plurality of grids; iteratively bisecting the placement image in a biggest region at a time of the bisecting until a predefined number of partitions is obtained, wherein at least one of: the flattening, the constructing, the performing logic clustering, or the partitioning is performed using a processor.