Patent ID: 8107515

Claim:
A burst processing modem comprising: a receive side comprising; a channelizer comprising one or more stages coupled with a random access memory (RAM) array, the channelizer adapted to process a plurality of channels comprised in a plurality of intermediate frequency (IF) received beams and to write a plurality of frames included in each of the plurality of channels to the RAM array, each of the plurality of frames including one or more bursts; a receive frame state machine coupled with the RAM array and with the channelizer, the receive frame state machine adapted to generate a timing signal using a burst time plan for the plurality of frames included in each of the plurality of channels; and a demodulator coupled with the receive frame state machine and with the RAM array, the demodulator adapted to read from the RAM array only the one or more bursts from the plurality of frames indicated by the timing signal, demodulate the one or more bursts, and transmit the one or more bursts to a decoding module.