Patent ID: 7441139

Claim:
A skew adjusting circuit for parallel signals, which circuit adjusts skew among parallel signals when data signals are transmitted in parallel from a transmitting circuit to a receiving circuit, said skew adjusting circuit comprising: a selecting circuit which sequentially selects each of the parallel signals; a deskew signal generating circuit which generates a deskew signal, which is for adjusting skew, by performing a predetermined logical operation using a plurality of successive bits of a data signal selected by said selecting circuit and transmits the deskew signal to said receiving circuit; a skew detecting circuit provided for said receiving circuit, which circuit detects the skew by obtaining correlation between the deskew signal and the data signal selected by said selecting circuit and then obtaining an average value of the correlation; and a delay amount adjusting circuit provided for said receiving circuit, which circuit adjusts the skew by controlling the amount of delay of the data signal in accordance with the average value obtained by said skew detecting circuit.