Patent ID: 7023058

Claim:
A semiconductor integrated circuit device comprising plural flip-flops, plural logic circuits connected to output nodes of the plural flip-flops and first to third power lines, wherein the flip-flops have a first latch circuit an output node of which is connected with the output node of the flip-flops and a second latch circuit an input node of which is connected with the output node or an input node of the first latch circuit, an operation voltage for the first latch circuit and the logic circuit is supplied from the first and the second power lines, an operation voltage for the second latch circuit is supplied from the first and the third power lines, the first and the second power lines each have a first wiring width, the third power line has a second wiring width, a wiring for connecting the input node of the second latch circuit and the output node or input node of the first latch circuit has a third wiring width, and a difference between the first wiring width and the second wiring width is larger than a difference between the second wiring width and the third wiring width.