Patent ID: 8080775

Claim:
A readout circuit for reading from a matrix of addressable nodes comprising: a first half-circuit of a differential amplifier comprising: at least one source follower transistor adapted to receive an input signal from one of the addressable nodes; and at least one selector switch coupled to the source follower transistor and adapted to selectively activate the source follower transistor to receive the input signal; and a second half-circuit of a differential amplifier comprising: an output node adapted to provide an output signal of a readout of the one of the addressable nodes; a source leader transistor coupled to the output node and adapted to provide a feedback signal based on the readout of the one of the addressable nodes, the source leader transistor having a gate (G) connected to a feedback loop in electrical communication with the output node; and a tail current source selectively connected to the source follower transistor by the at least one selector switch and connected to the source leader transistor.