Patent ID: 7643598

Claim:
A frequency lock detector, comprising: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector; wherein the lock determiner receives a result value m from the counter and a result value d from the clock number difference detector; when the result value m from the counter is a predetermined counting number N generating and outputting a reset signal to the counter and the clock number difference detector, and when the result value m from the counter is less than the predetermined counting number N and the clock number difference d is larger than a predetermined value corresponding to a desired frequency accuracy generating and outputting a reset signal to the counter and the clock number difference detector; compares the clock number difference d between the reference clock signal and the recovered clock signal with the predetermined value corresponding to the desired frequency accuracy; determines whether the difference between the frequencies of the reference clock signal and the recovered clock signal is within the desired frequency accuracy; and outputs a lock signal based on the determination.