Patent ID: 8473535

Claim:
A pulse shaping filter comprising: a delay system comprising a digital delay chain; a multiplier system comprising at least one multiplier adapted to multiply a signal from an input signal or the delay system by a predetermined non-zero coefficient, the multiplier system comprising a current reference branch and at least one current branch system coupled to the current reference; and an adding system for summing each output of each multiplier of the multiplier system, wherein the current reference branch is adapted to receive a biasing current and the current reference branch comprises: a first PMOS transistor comprising a first PMOS source, a first PMOS gate, and a first PMOS drain; a first NMOS transistor comprising a first NMOS transistor source, a first NMOS transistor gate, and a first NMOS transistor drain; and a first NMOS switch comprising a first NMOS switch source, first NMOS switch gate, and a NMOS switch drain, and wherein the first PMOS drain is electrically coupled to the first NMOS switch drain and the first NMOS switch source is electrically coupled to the first NMOS transistor drain.