Patent ID: 8609507

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming gate patterns spaced apart from one another over a semiconductor substrate, wherein each of gate pattern includes a polysilicon layer; forming a first insulation layer over the semiconductor substrate having the gate patterns formed therein so that a first air gap is formed between the gate patterns; opening the first air gap by partially removing the first insulation layer over the first air gap; forming a sacrificial layer made of a material different than that of the first insulation layer, over the first insulation layer, wherein the sacrificial layer is formed alone an inner surface of the first air gap; partially etching the sacrificial layer and the first insulation layer to expose a part of each of the gate patterns; siliciding the exposed parts of the gate patterns; and forming a second insulation layer over the semiconductor substrate having the silicided gate patterns formed therein, wherein a second air gap is formed between the silicided gate patterns.