Patent ID: 8114749

Claim:
A method for fabricating a high voltage device, comprising: forming a high voltage first conductivity type well by injecting first conductivity type impurities into a semiconductor substrate; forming a first stack region having a first conductivity type drift region and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well by injecting first conductivity type impurities into the first stack region of the high voltage first conductivity type well; forming a second stack region having a second conductivity type drift region and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well by injecting second conductivity type impurities into the high voltage first conductivity type well; and forming a device isolation film between the first stack region and the second stack region for isolating the first stack region from the second stack region, wherein the device isolating film in the high voltage first conductivity type well is deeper than the first stack region and the second stack region.