Patent ID: 8486822

Claim:
A method for fabricating a semiconductor device having a dummy pattern comprising: forming an interlayer dielectric film on a semiconductor substrate including a first pattern region, a second pattern region, and a dummy region wherein the dummy region is located between the first pattern region and the second pattern region; forming a photoresist pattern having open regions on the interlayer dielectric film such that the first pattern region and the dummy region are partially exposed by the open regions; etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form contact holes in the first pattern region and a dummy contact hole in the dummy region; filling the contact holes and the dummy contact hole with a conductive material to form contact plugs and a dummy plug; depositing a semiconductor layer on the interlayer dielectric film comprising the contact plugs and the dummy plug; forming a first semiconductor layer pattern contacting top surfaces of the contact plugs in the first pattern region and forming a second semiconductor layer pattern in the second pattern region by patterning the semiconductor layer, wherein the first semiconductor layer pattern and the second semiconductor layer pattern have different pattern densities; and forming the dummy pattern on the interlayer dielectric film of the dummy region, wherein the dummy pattern contacts a top surface of the dummy plug by patterning the semiconductor layer, wherein the dummy pattern has the same height as the first and second semiconductor layer patterns, and wherein the dummy plug fixes the dummy pattern on the interlayer dielectric film.