Patent ID: 8437187

Claim:
A semiconductor integrated circuit comprising: a plurality of memory cells, each of the memory cells having first and second non-volatile memories and a plurality of switching elements, the first and second non-volatile memories and the switching elements being connected in series between a first power source and a second power source, wherein output wirings of at least two of the memory cells are connected to each other, and an input wiring is connected with control gates of the switching elements included in each of the at least two memory cells in order to send an input signal or an inverted signal of the input signal to the control gates, and wherein the memory cells are configured such that a plurality of the switching elements included in one of the at least two of the memory cells are turned off when the input signal or the inverted signal is inputted, and that another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the at least two memory cells are turned on when the input signal or the inverted signal is inputted.