Patent ID: 7642592

Claim:
A one-time programmable memory device, comprising: an isolation layer for defining an active area of a substrate; a tunnel oxide layer formed on the active area; a floating gate formed over the active area and the isolation layer; an inter-gate dielectric layer formed on the floating gate; and a control gate formed on the inter-gate dielectric layer, wherein a first portion of the floating gate, formed over the active area is narrower than a second portion of the floating gate formed over the isolation layer, and wherein the control gate is formed over the second portion of the floating gate and not over the first portion of the floating gate, and wherein a plurality of edges of the control gate are formed to be within corresponding edges of the floating gate such that an area of the isolation layer overlapped by the second portion is greater than an area of the isolation layer overlapped by the control gate, wherein the isolation layer has a trench-type structure having a substantially same height throughout the isolation layer, wherein the tunnel oxide layer is disposed on the uppermost surface of the isolation layer.