Patent ID: 8310041

Claim:
A stacked semiconductor package comprising: a first semiconductor chip configured to comprise a plurality of first pins on at least one side for connection with an external circuit; a second semiconductor chip configured to be stacked above the first semiconductor chip and comprise a plurality of second pins on at least one side corresponding to the first pins, the second pins having ends that extend toward and are spaced apart from upper portions of the corresponding first pins; a printed circuit board (PCB) configured to be disposed in a space between the second pins and chip bodies of the first and second semiconductor chips and along a length of the first and second semiconductor chips and comprise a plurality of conductive patterns, each extending from the end of the corresponding second pin toward the upper portion of the corresponding first pin; and a plurality of bonding portions, each configured to electrically connect a conductive pattern of the PCB, an end of a corresponding second pin and an upper portion of a corresponding first pin.