Patent ID: 8093596

Claim:
A pixel structure, formed on a substrate including a transistor region and a capacitor region, the pixel structure comprising: a patterned semiconductor layer disposed on the transistor region of the substrate, wherein the patterned semiconductor layer comprises a channel region and a source/drain region formed on two sides of the channel region; a first capacitor electrode disposed on the capacitor region of the substrate; a gate dielectric layer disposed on the patterned semiconductor layer and the first capacitor electrode; a gate disposed on the channel region of the patterned semiconductor layer; a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region; a first dielectric layer disposed on the gate and the aluminum capacitor electrode; at least one first wire disposed in the first dielectric layer for electrically connecting the source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode; a second dielectric layer disposed on the first wire; and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.