Patent ID: 8689079

Claim:
A memory device comprising: a memory configured to be accessed via a plurality of channels; a memory interface configured to access the memory via the plurality of channels in parallel based on a plurality of access commands; a command generator configured to sequentially issue channel-by-channel access commands to the memory interface in a predetermined access process for accessing the memory in units of blocks; a purger configured to return a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via the plurality of channels; a command progress manager configured to manage command progress in the access commands in the predetermined process based on command progress information and to update the command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel, wherein the command generator is further configured to issue the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information; and an overall-progress manager configured to detect an end of a block based on managing overall progress of the access commands on the plurality of channels.