Patent ID: 7120070

Claim:
A method for testing the serviceability of bit lines, sense amplifiers and pre-charge circuits in a DRAM memory device comprising the following steps: (a) setting a DRAM memory device in a test mode; (b) applying a write command to the DRAM memory device for writing a predetermined test data to a memory cell connected to a bit line and contemporaneously switching on an active-current generator for providing power to a sense amplifier and pre-charge circuit associated to the bit line; (c) switching off the active-current generator and switching a standby-current generator to the sense amplifier and the pre-charge circuit of the bit line at a controllable switching time, wherein the switching time is earlier with respect to a switching time in a normal operation mode; (d) performing a pre-charge operation on the bit line by closing a word line associated to the memory cell and applying a pre-charge voltage to the bit line by the associated pre-charge circuit; (e) reading the data stored in the memory cell; and (f) comparing the read data with the predetermined test data.