Patent ID: 8264872

Claim:
A column decoder for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in said memory cells, and a programming stage for programming said data; said column decoder comprising: a first reading terminal configured to be coupled to the reading stage; a programming terminal configured to be coupled to the programming stage; a bitline terminal configured to be coupled to a bitline of the array; a first decoder circuit configured to provide a first current path between said bitline terminal and said first reading terminal, a second decoder circuit, distinct and separate from said first decoder circuit, configured to provide a second current path, distinct from said first current path, between said bitline terminal and said programming terminal, wherein said first current path includes a first plurality of selection switches connected in series between said bitline terminal and said first reading terminal, and said second current path includes a second plurality of selection switches connected in series between said bitline terminal and said programming terminal; said selection switches of said first plurality and said selection switches of said second plurality being alternatively enabled according to address-selection signals; and a switch element configured to connect a reference potential to an intermediate node of said second current path, the intermediate node being between two consecutive selection switches of said second plurality; said switch element being operable when said second current path is not enabled.