Patent ID: 7541632

Claim:
A memory device, comprising: an access field transistor of a semiconductor substrate assembly, the access field transistor having a substantially linear active area defining a first axis, the substantially linear active area including a shared source, a first drain, and a second drain, the access field transistor also having a first gate disposed between the shared source and the first drain, and a second gate disposed between the shared source and the second drain; at least two substantially parallel word lines each having a first width, at least a portion of a first word line located between the first drain and the shared source, wherein the first word line is coupled to the first gate, and at least a portion of a second word line located between the second drain and the shared source, wherein the second word line is coupled to the second gate, which word lines define a second axis lengthwise along the word lines, wherein a third axis runs perpendicular to the second axis; and a digit line coupled to the shared source, wherein the digit line forms a substantially zig-zag pattern, and wherein the digit line has a second width that is about double the first width, wherein at least a portion of the digit line near the shared source does not run perpendicular to the word lines at the shared source, the portion defining a fourth axis, wherein an acute angle between the third axis and the fourth axis is within the range of 20° to 30°.