Patent ID: 7904704

Claim:
An instruction dispatching method, comprising: a scheduler, of a multithread processing unit, successively allocating, M number of execution cycles to N number of instruction execution threads such that each of the N number of instruction execution threads is allocated equal number of execution cycles of the M number of execution cycles, wherein N is an integer, and wherein M is an integer and a multiple of N; subsequent to successively allocating the M number of execution cycles, the scheduler determining that B number of execution cycles in a current instruction execution period is unallocated, where B is an integer; in response to said determining, the scheduler successively allocating the B number of execution cycles to one or more of the N number of instruction execution threads based at least in part on bandwidth requirements of the individual instruction execution threads of the N number of instruction execution threads, wherein individual instruction execution threads of the N number of instruction execution threads are allocated unequal number of execution cycles of the B number of execution cycles, wherein the current instruction execution period includes the M number of execution cycles and the B number of execution cycles; and a dispatcher, of the multithread processing unit, successively issuing an instruction for a respective instruction execution thread of the plurality of instruction execution threads based at least in part on (i) successively allocating the M number of execution cycles and (ii) the B number of execution cycles to the plurality of instruction execution threads.