Patent ID: 8201120

Claim:
A method for selecting timing points in an electrical interconnect network used in electrical simulations in a static timing analysis (STA) to improve the numerical accuracy of the STA, the method comprising: a) using a computer, inputting the electrical interconnect network and converting it into a graph; b) augmenting the graph by adding a first set of edges to connect all vertices of a selected logical port and a second set of edges to connect all the vertices of all other logical ports; c) partitioning the graph into biconnected components and articulation vertices, wherein one biconnected component comprises all the vertices of the selected logical port, and a second biconnected component comprises all the vertices of all the other logical ports; d) determining if the selected logical port's biconnected component is separate from the other ports' biconnected component, and if the components are separate, then selecting an articulation vertex on a path from the first biconnected component to the second biconnected component as a timing point for the selected logical port; and e) incorporating the selected articulation vertex into the selected logical port's timing point, thereby improving the numerical accuracy of the STA.