Patent ID: 7224202

Claim:
A high voltage level shifter, the high voltage level shifter coupled to receive a low-voltage input signal to generate a higher-voltage output signal, comprising: a resistor coupled between a first node and a first power supply rail; an inverter coupled to receive the input signal to generate an inverted input signal; a first circuit portion coupled between the first power supply rail and a second power supply rail for converting a low-voltage low-state signal into a higher-voltage low-state signal, the first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node, the first circuit portion coupled to receive the inverted input signal wherein the first circuit portion comprises: a first N-type transistor coupled between a second node and the first power supply rail, the first N-type transistor biased by the inverted input signal; a first P-type transistor coupled between the second node and a fourth node, the first P-type transistor biased by the first clamp circuit at the first node; and a second P-type transistor coupled between the second power supply rail and the fourth node, the second P-type transistor biased by a first internal bias wherein the fourth node supplies the output signal and wherein the first clamp circuit comprises a first diode and a second diode coupled in series between the first node and fourth node; and a second circuit portion coupled between the first power supply rail and the second power supply rail for converting a low-voltage high-state signal into a higher-voltage high-state signal, the second circuit portion includes a second clamp circuit, wherein the second circuit portion is biased through the second clamp circuit and the first node, the second circuit portion coupled to receive the input signal, wherein the second circuit portion provides the first internal bias for the first circuit portion and the first circuit portion provides a second internal bias for the second circuit portion.