Patent ID: 8377719

Claim:
A process of forming an integrated circuit, comprising the steps of: providing a substrate; forming a first matching component on said substrate; forming a second matching component on said substrate with a layout identical to that of said first matching component; forming a dielectric layer on said substrate and above said first matching component and said second matching component; forming a plurality of electrically active ferroelectric structures on said dielectric layer; forming a hydrogen barrier above said electrically active ferroelectric structures; forming an inter-level dielectric layer on said hydrogen barrier; forming a first plurality of via holes for electrically active vias through said inter-level dielectric layer and through said hydrogen barrier; forming a second plurality of via holes for dummy vias through said inter-level dielectric layer and through said hydrogen barrier in a dummy via configuration and positioned over said first matching component; forming a third plurality of via holes for dummy vias through said inter-level dielectric layer and through said hydrogen barrier in said dummy via configuration and positioned over said second matching component; forming a plurality of electrically active vias in said first plurality of said via holes; forming a first plurality of hydrogen permeable dummy vias in said second plurality of said via holes such that at least a portion of bottom surfaces of said first plurality of said hydrogen permeable dummy vias contact said dielectric layer; forming a second plurality of hydrogen permeable dummy vias in said third plurality of said via holes such that at least a portion of bottom surfaces of said second plurality of said hydrogen permeable dummy vias contact said dielectric layer; forming a first plurality of electrically inactive ferroelectric structures in a ferroelectric structure configuration over said first matching component, over said dielectric layer, and under said hydrogen barrier; and forming a second plurality of electrically inactive ferroelectric structures in said ferroelectric structure configuration over said second matching component, over said dielectric layer, and under said hydrogen barrier.