Patent ID: 8120986

Claim:
A semiconductor memory device comprising: a plurality of input/output (I/O) ports; and a memory array divided into a plurality of memory areas; wherein the plurality of memory areas comprises, a first memory area operatively connected to a first I/O port through a first access path; a second memory area operatively connected to a second I/O port through a second access path; and a third memory area operatively connected to both the first I/O port and the second I/O port, wherein semiconductor device is configurable such that the first memory is addressable through the first I/O port but not the second I/O port, the second memory area is only addressable through the second I/O port but not the first I/O port, and the third memory area is addressable through both the first and second I/O port, and wherein a size of at least one of the memory areas is variable.