Patent ID: 7371684

Claim:
A process for preparing an electronics structure, said process comprising the following steps: a) providing a substrate stack having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer; b) coating the substrate stack with a multi-layer hardmask stack; c) coating a topmost layer of the hardmask stack with a self-assembled layer; d) developing a pattern in the self-assembled layer; e) transferring the pattern into at least the topmost layer of the hardmask stack; f) blocking a portion of the pattern transferred into the topmost layer of the hardmask stack with a resist to protect a blocked portion of the pattern against being transferred deeper into the multi-layer hardmask stack; g) transferring an unblocked portion of the pattern through the multi-layer hardmask stack into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer; and h) stripping off the multi-layer hardmask stack.