Patent ID: 7278062

Claim:
A data processing system having a processor coupled to a bus, the data processing system comprising: access error detection circuitry, coupled to the bus, the access error detection circuitry detecting an access error which occurs on a data or instruction access on the bus; and access error response circuitry, coupled to the bus, the access error response circuitry initiating replacement of an existing value on the bus with a predetermined value rather than the existing value is provided to the processor, and the access error response circuitry continuing to replace the existing value on the bus with the predetermined value when the access error has been detected and a first indicator has been asserted, wherein the predetermined value has a selectable bit-ordering, wherein the selectable bit-ordering is one of big endian and little endian, wherein the predetermined value has a first value if the current mode of the data processing system is a first one of the plurality of modes, and wherein the predetermined value has a second one of the plurality of modes, and wherein the first value and the second value are not a same value.