Patent ID: 8004889

Claim:
A semiconductor memory device comprising: a memory cell array connected to a word line and a bit line, and composed of a plurality of memory cells arranged in a matrix, which store one value of an n value (wherein n is a natural number greater than 2); and a control circuit configured to control each voltage of the word line and the bit line in accordance with input data, the control circuit supplying a first voltage to a word line of a selected cell in a write operation, and supplying a second voltage to at least one of non-select word lines adjacent to the selected cell, and thereafter, changing a voltage of said at least one of non-select word lines adjacent to the selected cell from the second voltage to a third voltage, wherein the second voltage is less than the third voltage, wherein the word line of the selected cell is connected to a gate electrode of a first select transistor, and a word line of a non-selected cell is connected to a gate electrode of a second select transistor, and the gate electrodes of the first and second select transistors are connected in common and supplied with a common voltage, and wherein the common voltage supplied to the gate electrodes of the first select transistor and the second select transistor is set to a fourth voltage after a fifth voltage is supplied with the gate electrodes of the first select transistor and the second select transistor in order to supply the second voltage to at least one word line adjacent to the selected cell and the first voltage to the word line of the selected cell, wherein the fifth voltage is greater than or equal to the fourth voltage and the fourth voltage is greater than the third voltage.