Patent ID: 8890785

Claim:
A gate driving circuit located on a substrate, the gate driving circuit being suitable for driving a pixel array having a plurality of first pixels and a plurality of second pixels, each of the first pixels being electrically connected to one of a plurality of first scan lines, one of a plurality of first data lines, and one of a plurality of first driving lines, each of the second pixels being electrically connected to one of a plurality of second scan lines, one of a plurality of second data lines, and one of a plurality of second driving lines, the gate driving circuit comprising: a plurality of first shift registers, each of the first shift registers comprising: a first scan signal generator and a second scan signal generator electrically connected to a corresponding one of the first scan lines and a corresponding one of the second scan lines, respectively, so as to simultaneously output a first scan signal to the corresponding first scan line and output a second scan signal to the corresponding second scan line according to a plurality of clock signals; and a first control unit for generating a first control signal based on a first latch clock signal and a second control unit for generating a second control signal based on a second latch clock signal, the first control signal and the second control signal being transmitted to the first scan signal generator and the second scan signal generator, respectively, so as to control the first scan signal generator and the second scan signal generator to stop outputting the first scan signal and the second scan signal; and a plurality of second shift registers, each of the second shift registers comprising: a driving signal generator electrically connected to a corresponding one of the first driving lines and a corresponding one of the second driving lines for simultaneously outputting a first driving signal to the corresponding first driving line and outputting a second driving signal to the corresponding second driving line according to the clock signals; and a third control unit for generating a third control signal based on the first latch clock signal and a fourth control unit for generating a fourth control signal based on the second latch clock signal, the third control signal and the fourth control signal being transmitted to the driving signal generator, so as to control the driving signal generator to stop outputting the first driving signal and the second driving signal.