Patent ID: 7657683

Claim:
A cross-thread interrupt processor for a dual thread CPU having a first thread process and a second thread process, the interrupt processor having: a first interrupt controller (IC1) operative to receive interrupt requests from said second thread process and generate IC1 interrupts coupled to said first thread process and also to provide IC1 interrupt counts to said second thread process, said first interrupt controller also operative to receive interrupt acknowledgements from said first thread process; a second interrupt controller (IC2) operative to receive interrupt requests from said first thread process and generate IC2 interrupts coupled to said second thread and also to provide IC2 interrupt counts to said first thread process, said second interrupt controller also operative to receive interrupt acknowledgements from said second thread process; where said first interrupt controller interrupt request from said second thread process causes an associated IC2 interrupt count to increment, and said first interrupt controller acknowledgement from said first thread causes said IC1 interrupt count to decrement, said IC1interrupt count asserting said IC1 interrupt coupled to said first thread process said IC1 interrupt if said IC1 interrupt count is greater than 0; where said second interrupt controller interrupt request from said first thread process causes an associated IC2 interrupt count to increment, and said second interrupt controller acknowledgement from said second thread causes said IC2 interrupt count to decrement, said IC2 interrupt count asserting said IC2 interrupt coupled to said second thread processes interrupt if said IC2 interrupt count is greater than 0.