Patent ID: 7154804

Claim:
A semiconductor integrated circuit formed on a single chip, comprising: a central processing unit provided a clock signal from a clock generating unit; a memory accessible from said central processing unit, and including memory cells coupled with bit lines and source lines; and a bus coupled to said central processing unit and said memory, wherein said semiconductor integrated circuit has an active operation and a standby operation as an operation thereof, wherein said semiconductor integrated circuit is instructed as to a transition of the operation from said active operation to said standby operation, when said central processing unit executes a predetermined instruction, wherein, in said active operation, said central processing unit is capable of accessing said memory and said clock generating unit provides said clock signal to said central processing unit and to said memory, wherein, in said standby operation, said central processing unit stops an operation, and said clock generating unit stops providing said clock signal to said central processing unit and said memory, and wherein said memory makes the potential of said bit lines and the potential of said source lines equal to each other in said standby operation, and wherein said memory is capable of producing a potential difference between said bit lines and said source lines in said active operation.