Patent ID: 7071057

Claim:
A method of fabricating a MIM capacitor of a semiconductor device comprising: forming a lower interconnect on a semiconductor substrate; sequentially depositing second and third insulating layers over the lower interconnect; performing a first damascene process to form first and second via holes and a first trench within the second and the third insulating layers; filling the first and second via holes and the first trench with a conductive material to form a first contact plug connected to the lower interconnect and a second contact plug to be in contact with a lower electrode of a MIM capacitor; forming the MIM capacitor over the second contact plug; sequentially depositing fourth and fifth insulating layers; performing a second damascene process to form a third via hole and a second trench within the fourth and the fifth insulating layers; and filling the third via hole and the second trench to form a third contact plug in contact with the upper electrode of the capacitor and a fourth contact plug connected to the lower interconnect; wherein performing the first damascene process comprises: forming the first and second via holes within the third insulating layer; filling a photoresist material into the first and second via holes; hardening the photoresist; forming a mask pattern exposing the first via hole; forming a trench using the mask pattern as an etch mask; removing the etch mask; and removing the photoresist and the second insulating layer in the via holes.