Patent ID: 8643969

Claim:
An apparatus comprising: an input buffer; digital logic that is coupled to the input buffer, wherein the digital logic has at least one duration generator and at least one level shifter; a matching circuit that is configured to drive an inductive load; a first half H-bridge having: a first CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive a first voltage; a second CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive a second voltage; a third CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive a third voltage; and a fourth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive a fourth voltage; and a second half H-bridge having: a fifth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive the first voltage; a sixth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive the second voltage; a seventh CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit, and that is configured to receive the third voltage; and an eighth CMOS switch that is coupled to be controlled by the digital logic, that is coupled to the matching circuit and that is configured to receive the fourth voltage.