Patent ID: 8709897

Claim:
A method comprising: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a pocket implant region proximate to the gate structure including a portion that is directly below the gate structure and physically contacting a dielectric layer of the gate structure, wherein after forming the pocket implant region a portion of the semiconductor substrate forming a channel of the gate structure physically contacts the dielectric layer of the gate structure and is free of the pocket implant region; forming spacers adjacent to the gate structure; performing a dry etch to form a recess with a first contour; performing a wet etch to enlarge the recess to a second contour; performing a thermal etch to enlarge the recess to a third contour, wherein performing the thermal etch to enlarge the recess to the third contour includes completely removing the portion of the pocket implant region that is directly below the gate structure and physically contacting the dielectric layer of the gate structure, wherein after performing the thermal etch to enlarge the recess to the third contour the portion of the substrate forming the channel of the gate structure physicall contacts the dielectric layer of the gate structure; forming a source-drain structure in the recess having the third contour; and wherein the dry etch, the wet etch, and the thermal etch are performed without a light doped drain (LDD) implantation process having been previously performed to form a LDD feature in the substrate proximate the gate structure.