Patent ID: 8492833

Claim:
A semiconductor device, comprising: a semiconductor substrate including a cell region and a peripheral circuit region; a first trench for device isolation formed in the cell region of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit region, the second trench being deeper than the first trench; a device isolation layer filling the first and second trenches and being substantially flush with an upper surface of the semiconductor substrate in the cell region; a buried gate buried in the semiconductor substrate of the cell region; a peripheral circuit gate including a gate electrode, the peripheral circuit gate being provided in the peripheral circuit region and being in contact with the semiconductor substrate, and the peripheral circuit gate being formed within the device isolation layer and having an upper surface that is at substantially the same surface level as that of the buried gate; and a bit line which is in contact with the semiconductor substrate of the cell region and the gate electrode in the peripheral circuit region.