Patent ID: 7339221

Claim:
A semiconductor memory device, comprising: a semiconductor substrate having a main surface and an active region surrounded with an element isolation structure on said main surface; a transistor having first and second source/drain regions formed on a surface of said active region and a gate electrode layer serving as a word line, located on a region sandwiched between said first and second source/drain regions and extending across said active region; a hard mask layer formed on said gate electrode layer and having a plane pattern shape identical with that of said gate electrode layer; sidewall insulating films formed on sidewalls of said gate electrode layer and said hard mask layer; and first and second plug conductive layers each electrically connected to each of said first and second source/drain regions and covering a whole portion of both said first and second source/drain regions not covered with said gate electrode layer and said sidewall insulation films in plane view; a capacitor electrically connected to said first plug conductive layer; and a bit line electrically connected to said second plug conductive layer and extended perpendicular to said word line, wherein an extending direction of said active region is not perpendicular to both that of said word line and that of said bit line but is oblique, and an upper surface of said hard mask layer and an upper surface of each of said first and second plug conductive layers form substantially an identical plane, at least one of said first and second plug conductive layers has a pair of sides that are parallel to the longitudinal direction of said active region in plane view, and in plane view, one of said sides of said first plug conductive layer is collinear with one of said sides of said second plug conductive layer, and not perpendicular to both that of said word line and that of said bit line but is oblique.