Patent ID: 8530879

Claim:
A semiconductor memory device, comprising: a plurality of first lines disposed in parallel; a plurality of second lines disposed to intersect the first lines; and a memory cell array including memory cells, each of the memory cells being disposed at each of intersections of the first lines and the second lines, and each of the memory cells being configured by a rectifier element and a variable resistor connected in series, the rectifier element comprising: a first semiconductor region of a first conductivity type including an impurity of a first impurity concentration; and a second semiconductor region of a second conductivity type including an impurity of a second impurity concentration lower than the first impurity concentration, the first semiconductor region and the second semiconductor region being formed by silicon, and a junction interface of the first semiconductor region and the second semiconductor region being a pseudo-heterojunction formed by two layers that have different band gap widths and are formed of the same material.