Patent ID: 7020787

Claim:
A microprocessor that performs processing according to an instruction fetched from a memory, comprising: a calculation circuit that (i) includes partial calculation circuits which each perform partial data calculation, upon receiving a clock signal, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation circuits are to perform data calculation, wherein the partial calculation circuits, except for a partial calculation circuit that performs data calculation on a most significant bit of the N bits, are each operable to output a carry bit signal indicating an overflow occurring during data calculation, the calculation circuit includes a carry bit signal transmitting unit that inputs to each of all the partial calculation circuits except for a partial calculation circuit that performs data calculation on a least significant bit of the N bits, a carry bit signal outputted from a partial calculation circuit that performs data calculation on a number of less significant bits than the particular partial calculation circuit to which such a carry bit signal is to be inputted does; a bit width selecting unit operable to select a bit width mode that designates a certain number of bits on which data calculation is to be performed; an execution controlling unit operable to, if the fetched instruction is an instruction for data calculation, control the calculation circuit to perform data calculation; an operation controlling unit operable to, when the execution controlling unit controls the calculation circuit to perform data calculation, (i) have all the partial calculation circuits operate, in a case where the bit width selecting unit selects a first bit width mode designating N bits, and (ii) suspend operation of a predetermined number of the partial calculation circuits, and have the rest of the partial circulation circuits operate, in a case where the bit width selecting unit selects a second bit width mode designating less than N bits; and a carry bit signal inhibiting unit operable to, in a case where the bit width selecting unit selects the second bit width mode, inhibit the carry bit signal transmitting unit from inputting a carry bit signal to the predetermined number of the partial calculation circuits to which the supply of a clock signal is suspended by the operation controlling unit, wherein the operation controlling unit (i) in a case where the bit width selecting unit selects the first bit width mode, supplies a clock signal to each of all the partial calculation circuits, and (ii) in a case where the bit width selecting unit selects the second bit width mode, suspends the supply of a clock signal to a predetermined number of the partial calculation circuits, and supplies a clock signal to each of the rest of the partial calculation circuits.