Patent ID: 7000062

Claim:
A system comprising: a master device; a first integrated circuit buffer device; a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device; a first plurality of signal lines coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines communicate control information, address information and data from the master device to the first integrated circuit buffer device; a second plurality of signal lines coupled to the first integrated circuit buffer device; a second integrated circuit buffer device coupled to the second plurality of signal lines, the second integrated circuit buffer device to receive the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines; and a second plurality of integrated circuit memory devices coupled to the second integrated circuit buffer device; and a third plurality of signal lines coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the master device, the third plurality of signal lines to communicate information from the master device, the information to initialize the first integrated circuit buffer device and the second integrated circuit buffer device.