Patent ID: 7535052

Claim:
A method of fabricating a non-volatile memory integrated circuit device, the method comprising: forming a device isolation region in a substrate, thus defining a cell array region and a peripheral circuit region; forming a plurality of first and second pre-stacked gate structures in the cell array region, the first and second pre-stacked gate structures each having a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked, the first and second pre-stacked gate structures being formed so that a first pitch between neighboring first pre-stacked gate structures and a second pitch between neighboring first and second pre-stacked gate structures are narrower than a third pitch between neighboring second pre-stacked gate structures; forming a plurality of junction regions in the cell array region exposed by the first and second pre-stacked gate structures; forming a plurality of spacers on side walls of the first and second pre-stacked gate structures, the spacers being formed so that spacers between the first pre-stacked gate structures are connected to each other and spacers between the first and second pre-stacked gate structures are connected to each other, but spacers between the second pre-stacked gate structures are separated from each other; forming a second sacrificial layer pattern to fill each space between the second pre-stacked gate structures; removing the first sacrificial layer pattern from each of the first and second pre-stacked gate structures; forming a damascene metal layer pattern in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures; removing the second sacrificial layer pattern; and forming a stop layer on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.