Patent ID: 8679963

Claim:
A method of making a chip scale package, comprising: providing a semiconductor die having a first area supporting a plurality of first bond pads; arranging a dielectric layer over at least a portion of the first area; embedding the semiconductor die in a die support body formed of a molding material, in an orientation and position wherein the dielectric layer over at least the portion of the first area is exposed; exposing at least two of the plurality of first bond pads by opening a hole in the dielectric layer over each of said at least two of the plurality of first bond pads; forming a plurality of electrical leads on the dielectric layer, each of said electrical leads forming at least one second bond pad and extending from the at least one second bond to a corresponding one of the plurality of first bond pads, wherein said plurality of first bond pads are arranged in a first arrangement having a first density of bond pads per unit area and the second bond pads have a second arrangement having a second density of bond pads per unit area that is less than said first density; and forming a conducting bump on at least one of the second bond pads.