Patent ID: 8855962

Claim:
A system for testing standard interfaces of an electronic circuit, comprising: a first multiplexer for receiving a plurality of clock signals and selectively transmitting a first clock signal, based on a first test mode enable signal, a module clock select signal, and a test mode activate signal; a test port master, connected to the first multiplexer, for receiving at least one test pattern from an external testing apparatus, based on the first clock signal; a second multiplexer, connected to the test port master and a first bus network component, for receiving and selectively transmitting the at least one test pattern and a first bus network signal respectively, based on the first test mode enable signal, and the test mode activate signal; a first standard interface, connected to the second multiplexer, for connecting the electronic circuit to an external device, wherein the first standard interface is further connected to the test port master through the second multiplexer to bypass the first bus network component when the test mode activate signal and the first test mode enable signal are asserted, and wherein the test port master and the first standard interface are configured to operate in a master and a slave configuration, respectively, when the test mode activate signal and the first test mode enable signal are asserted; a third multiplexer, connected to the first standard interface, for receiving the plurality of clock signals and selectively transmitting a second clock signal, based on the test mode activate signal, the first test mode enable signal, and the module clock select signal; a fourth multiplexer, connected to the test port master and a second bus network component for receiving and selectively transmitting the at least one test pattern and a second bus network signal respectively, based on the test mode activate signal, and a second test mode enable signal; and a second standard interface, connected to the fourth multiplexer, for connecting the electronic circuit to an external memory device, wherein the second standard interface is further connected to the test port master through the fourth multiplexer to bypass the second bus network component when the test mode activate signal, and the second test mode enable signal are asserted.