Patent ID: 7016234

Claim:
A storage device comprising a plurality of storage cells arranged and each having a storage element and an active element comprising a MOS transistor which controls access to said storage element, and in which, by applying a voltage to said storage element, a resistance value of said storage element changes and information is recorded; wherein when recording operation to change the resistance value of said storage element from a high state to a low state is defined as information writing, and recording operation to change the resistance value of said storage element from a low state to a high state is defined as information erasure; if when erasing said written information the voltage applied to said storage cell is Ve and a voltage applied to a gate of said active element is Vg, a minimum voltage necessary when erasing said information is Vt, and a drain current flowing in said active element for a voltage V across a source and drain of said active element when said active element is in an ON state is represented by a function {I(Vg,V)}, then a resistance value R of said storage element after said information has been written satisfies a relation: R≧Vt/{I ( Vg,Ve−Vt )}.