Patent ID: 8793421

Claim:
An apparatus, comprising: an arbitration unit coupled to a plurality of request queues for a target circuit, wherein each request queue is configured to store requests generated by a respective one of a plurality of master circuits, wherein a request queue of one of the plurality of master circuits includes one or more queue stages, wherein each queue stage is configured to store a request from the master circuit and is associated with a respective latch, wherein the master circuit is configured to send, via the one or more respective latches, an indication specifying that a request has been submitted; wherein the one or more latches are driven separately from latches implementing the one or more queue stages such that the arbitration unit is configured to receive the sent indication while the request associated with the indication has stalled in one of the one or more queue stages; wherein the arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by the plurality of master circuits, wherein the information includes the received indication, and wherein the arbitration unit is configured to determine when the request was submitted based on the received indication.