Patent ID: 7297598

Claim:
A method of making embedded non-volatile memory (NVM) devices, comprising: forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate, wherein the first mask layer includes a plurality of openings in the cell region; oxidizing portions of the polycrystalline silicon layer exposed in the plurality of openings to form a plurality of poly-oxide features; removing the first mask layer; etching the polycrystalline silicon layer not covered by the plurality of poly-oxide features to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering process; forming a dielectric layer and then a second mask layer in both the cell region and the peripheral region; partially etching the second mask layer in the cell region after a layer of photoresist is formed over the second mask layer in the peripheral region; partially etching the dielectric layer formed in the cell region, while the second mask layer protects the peripheral region such that the dielectric layer formed in the peripheral region is not etched, whereby multiple thicknesses of the dielectric layer are formed; removing the second mask layer; and forming a plurality of control gates partially overlying and corresponding to the plurality of floating gates in the cell region.