Patent ID: 7615426

Claim:
A transistor comprising: a substrate having a surface; a gate dielectric on said surface of said substrate; a gate electrode on said gate dielectric; a spacer along a sidewall of said gate dielectric and gate electrode; a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween; a contact etch stop layer on said gate electrode and said spacers, and said source and drain, wherein said contact etch stop layer comprises a discontinuity extending in a channel width direction; an inter-level dielectric over said contact etch stop layer; a first contact opening over said gate electrode; a second contact opening over one of said source and said drain, wherein said discontinuity is between said first and second contact openings, and wherein the discontinuity does not adjoin the first and the second contact openings.