Patent ID: 7416940

Claim:
A method for fabricating a flash memory device, the method comprising the steps of: providing a silicon substrate; forming a plurality of gate stacks overlying said silicon substrate, wherein each of said plurality of gate stacks comprises a charge trapping layer and a control gate overlying said charge trapping layer, wherein said control gate is a first distance from said silicon substrate and wherein each gate stack of said plurality of gate stacks is a second distance from an adjacent gate stack; depositing a cell spacer material layer overlying said plurality of gate stacks; etching said cell spacer material layer to form a cell spacer about sidewalls of each of said plurality of gate stacks; and forming a first impurity doped region adjacent a first gate stack in said plurality of gate stacks and a second impurity doped region adjacent a last gate stack in said plurality of gate stacks, wherein, said first distance and said second distance are such that, when a voltage is applied to a selected gate stack of said plurality of gate stacks during a READ operation, a fringing field is created between said control gate of said selected gate stack and said silicon substrate and is sufficient to invert a portion of said silicon substrate between said selected gate stack and an adjacent gate stack.