Patent ID: 7428644

Claim:
A memory system, comprising: a memory controller; a memory bus operably coupled with the memory controller to communicate memory commands from the memory controller and communicate memory output signals to the memory controller; and a plurality of memory modules operably coupled with the memory bus, the memory modules generating the memory output signals and responsive to the memory commands, at least some of the memory modules comprising: an insulative substrate supporting a system interface; a plurality of memory devices disposed on the insulative substrate; a memory hub disposed on the insulative substrate and operably coupled with the memory devices and the system interface, the memory hub managing communications between the memory devices and the system interface in response to memory commands received via the system interface; an activity sensing device monitoring activity of the memory module containing the activity sensing device in processing memory commands, the activity sensing device being operable to generate an output corresponding thereto; and a module power controller coupled to the activity sensing device of the memory module containing the module power controller, the module power controller being operable to direct the memory devices in the memory module containing the module power controller to a reduced power state responsive to the output of the activity sensing device indicating activity of the memory module containing the module power controller is not of a desired level.