Patent ID: 7772060

Claim:
An integrated circuit comprising: at least one MOS transistor; and at least one bipolar transistor, wherein a channel of said MOS transistor and a base of said bipolar transistor are simultaneously formed in a common epitaxial layer disposed on a semiconducting surface of a substrate, said epitaxial layer comprising first and second silicon layers and first and second silicon-germanium layers, wherein said first silicon layer is interposed between said semiconducting surface and said second silicon-germanium layer, wherein said first silicon-germanium layer is interposed between said first and said second silicon layers, and wherein said second silicon layer is interposed between said first and said second silicon-germanium layers; and wherein said first layer of silicon-germanium includes an increasing concentration of dopant; said second layer of silicon includes a decreasing concentration of the same dopant; and the concentration of germanium in the second layer of silicon-germanium is higher than the concentration of germanium in the first layer of silicon-germanium.