Patent ID: 8411517

Claim:
A delay locked loop circuit for use in a semiconductor device, the delay locked loop circuit comprising: a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal; a control circuit unit for controlling a delay line in response to the detection signal; a delay line for delaying the input clock signal by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line; and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal, wherein the delay line further comprises: two or more inverter circuits in series; a first node at a first inverter circuit for receiving an the input clock signal; a second node at the first inverter circuit for outputting an inverted delayed clock signal; a first set of pull-up transistors, each having a gate connected to the first node and a drain connected to a third node; a first resistor connected at one end to the second node and connected at the other end to the third node; a set of pull-down transistors, each having a gate connected to the first node drain connected to a fourth node; and a second resistor connected at one end to the second node and connected at the other end to the fourth node.