Patent ID: 8245063

Claim:
A clock selector for a HOST_CLK and a NET_CLK clock source, said HOST_CLK associated with a HST_CLK_AVAIL which is asserted when said HOST_CLK is present, said NET_CLK associated with a NETCLK_OFF signal asserted when said NET_CLK is not available; a first doublet register having an input coupled to a first register, said first register having an output coupled to the input of a second register, said second register output coupled to said first doublet register output, said first and said second register clocked by said HOST_CLK; a second doublet register having an input coupled to a third register, said third register having an output coupled to the input of a fourth register, said fourth register output coupled to said second doublet register output forming a signal HCA, said third register and said fourth register clocked by said NET_CLK; a third doublet register having an input coupled to a fifth register, said fifth register having an output coupled to the input of a sixth register, said sixth register output coupled to said third doublet register output forming a signal NCO, said fifth register and said sixth register clocked by said NET_CLK; a clock select state machine having a first input coupled to said HCA and a second input coupled to said NCO, said clock select state machine containing state machine registers clocked by said NET_CLK, said state machine registers thereby generating a first output EN_HSTCLK and second output EN_NETCLK; a first AND gate having one input coupled to said HST_CLK_AVAIL and also to said second doublet register input, said first AND gate other input coupled to said EN_NETCLK, said first AND gate output coupled to said first doublet register input; a second AND gate having one input coupled to said HOST_CLK and the other input coupled to said first doublet register output; a third AND gate having one input coupled to said NET_CLK and the other input coupled to said EN_NETCLK; an OR gate generating said CLK_OUT output, said OR gate having one input coupled to said second AND gate output and the other input coupled to said third AND gate output.