Patent ID: 7657712

Claim:
A computer system comprising: a first processor comprising a first cache local to the first processor, the first processor being a general purpose processor; a second processor comprising a second cache local to the second processor, the second processor being a general purpose processor; and a memory resource shared by the first and second processors and coupled to the first and second processors at least partially over a common bus, the first cache selectively coupled to the shared memory resource via a switch network having an array of switches and a plurality of buses, the switch network assigning switch network resources to shared memory requests for the first processor according to a priority system determined at least in part from a type of the shared memory requests, the first processor performing a cache coherency protocol responsive to at least one shared memory request from the second processor, the first cache receiving an invalidation signal via the switch network in response to execution of an instruction by the second processor, wherein, the first processor is assigned a higher priority than the second processor, the higher priority being one factor of a plurality of factors the switch network considers in assigning switch network resources to the first processor.