Patent ID: 8536041

Claim:
A method for fabricating a transistor, the method comprising the steps of: providing a silicon layer; forming a first layer on the silicon layer, the first layer comprising a first high dielectric constant material; forming a second layer on the first layer, the second layer comprising a metal or metal alloy; forming a third layer on the second layer, the third layer consisting of one of silicon and polysilicon; etching at least the second and third layers so as to form at least second and third layers of a gate stack; depositing a sidewall spacer layer comprising a second high dielectric constant material; etching the sidewall spacer layer so as to form a sidewall spacer on sidewalls of the gate stack, the sidewall spacer covering the sidewalls of the second and third layers of the gate stack; implanting ions so as to form a source region and a drain region in the silicon layer on opposite sides of the gate stack; and implanting ions so as to form source/drain extensions in the silicon layer, each of the source/drain extensions underlying part but not all of the sidewall spacer, wherein a bottom surface of the second layer of the gate stack directly contacts a top surface of the first layer of the gate stack, a bottom surface of the third layer of the gate stack directly contacts a top surface of the second layer of the gate stack, the step of etching at least the second and third layers comprises performing an etch that stops on the silicon layer so as to etch the first, second, and third layers to form the first, second, and third layers of the gate stack on the silicon layer, and the step of etching the sidewall spacer layer comprises etching the sidewall spacer layer so that the sidewall spacer covers the sidewalls of the first, second, and third layers of the gate stack.