Patent ID: 7329563

Claim:
A method for forming a wafer level package by incorporating dual compliant layers comprising the steps of: providing a wafer having a multiplicity of IC dies formed on an active surface; forming a plurality of first I/O pads on said multiplicity of IC dies insulated by a first dielectric layer deposited therein-between; forming a plurality of metal cap layers with one on each of said plurality of I/O pads in electrical communication with said pads; depositing a first compliant layer of a first elastic material having tapered shoulder on top of said first dielectric layer; depositing a second compliant layer of a second elastic material on top of said first compliant layer; forming a plurality of metal traces on top of said first and second compliant layers each having a first end in electrical communication with one of said plurality of metal cap layers and a second end extending toward a center of said IC die; depositing a second dielectric layer on top of said plurality of metal traces insulating the latter from each other; exposing a plurality of second I/O pads with one on each of said plurality of metal traces; and forming a plurality of solder balls on said plurality of second I/O pads.