Patent ID: 8627304

Claim:
A processor in operational relationship with a general purpose computing machine for executing logic code, wherein the execution of the logic code causes the general purpose computing machine to: receive a first block of code as input, the first block of code including a program loop, wherein the program loop accesses one or more sets of memory addresses and at least one set of memory addresses is associated with a potential independent misalignment; convert the program loop into prologue, vector and epilogue loops, re-order the prologue, vector, or epilogue loops to facilitate merging of the prologue and epilogue loops; and merge the prologue and epilogue loops into a selective loop that performs conditional leaping address incrementation so that the vector loop accesses memory addresses that are aligned, wherein the conditional leaping address incrementation comprises: implementing a triplet structure having first, second and third values, wherein the first value is an index value, the second value refers to an address accessed by the first iteration of the epilogue loop, and the third value refers to a memory address accessed by the first iteration of the vector loop; incrementing a memory address in a first subset of memory addresses by incrementing the first value; determining whether the memory address is aligned by comparing the first value to the third value; and incrementing the memory address by a number of memory addresses in a second subset of memory addresses by resetting the first value to the second value, in response to determining that the memory address is aligned, wherein for the selective loop, the number of iterations during execution of the selective loop is known at compile-time, such that number of loops whose number of iterations will remain a compile-time-known-constant is maximized, and wherein the number of iterations during execution of the prologue loop and the epilogue loop is unknown.