Patent ID: 7617433

Claim:
An apparatus, comprising: a plurality of bit node processors that is operable to: during a first time, perform bit node processing that involves updating a first plurality of bit edges messages corresponding to a first plurality of non-zero elements that corresponds to each first column of each sub-matrix of a low density parity check matrix that includes a plurality of sub-matrices, each sub-matrix of the plurality of sub-matrices includes a plurality of rows and a plurality of columns; and during a second time, perform bit node processing that involves updating a second plurality of bit edges messages corresponding to a second plurality of non-zero elements that corresponds to each second column of each sub-matrix of the low density parity check matrix; and a plurality of check node processors that is operable to: during a third time, perform check node processing that involves updating a first plurality of check edges messages corresponding to a third plurality of non-zero elements that corresponds to each first row of each sub-matrix of the low density parity check matrix; and during a fourth time, perform check node processing that involves updating a second plurality of check edges messages corresponding to a fourth plurality of non-zero elements that corresponds to each second row of each sub-matrix of the low density parity check matrix; and wherein the first plurality of bit edges messages, the second plurality of bit edges messages, the first plurality of check edges messages, and the second plurality of check edges messages correspond to the selective connectivity via a plurality of edges between a plurality of bit nodes and a plurality of check nodes of an LDPC (Low Density Parity Check) bipartite graph that corresponds to an LDPC code.