Patent ID: 8818209

Claim:
A frequency decimation block for processing an analog input signal including a high-bandwidth data signal to generate a parallel set of parallel output signals, each output signal representing a respective portion of the high-bandwidth data signal, the frequency decimation block comprising: a preamplifier for amplifying the input signal to generate an amplified input signal; a frequency domain divider for frequency-dividing the amplified input signal to generate a set of frequency band signals including at least a low frequency band signal, a mid-frequency band signal, and a high frequency band signal, and for supplying each frequency band signal to at least one signal path; a respective non-linear processor connected in at least one signal path, each non-linear processor for processing a respective one of the frequency band signals using a respective branch signal to yield a corresponding composite signal; and a respective Low-Pass Filter (LPF) connected in each signal path, for low-pass filtering at least the composite signals to generate corresponding ones of the parallel output signals.