Patent ID: 7461365

Claim:
A method of designing a structured ASIC based integrated circuit, the method comprising: specifying a base array of function blocks; describing the base array as being organized into clusters of one or more of the function blocks, at least some of the clusters including a plurality of latch elements of the base array; describing one or more H-trees respectively over one or more of the clusters, each of the H-trees having a plurality of endpoints, at least some of the plurality of endpoints terminating near at least one corresponding latch element of the plurality of latch elements; describing an ad hoc circuit design that in conjunction with the base array defines at least in part a functionality of the structured ASIC based integrated circuit; imposing design constraints on the ad hoc circuit design including that one or more of the H-trees are predefined and correspond to the clusters having latch elements and that one or more of the predefined H-trees in conjunction with one or more conducting layers above the H-trees couple the latch elements of the corresponding clusters to one or more associated one-shot pulse generators such that the coupled latch elements emulate flip-flop functionality as observed by the ad hoc circuit design; wherein the H-trees corresponding to the clusters having latch elements provide matched path-lengths between each of the coupled latch elements of each corresponding cluster and the one or more associated one-shot pulse generators; and wherein an achievable effective flip-flop density of each corresponding cluster is greater than a density using actual flip-flops.