Patent ID: 7279384

Claim:
A method for manufacturing the semiconductor memory having plural cell transistors, the method comprising the steps of: (a) forming plural trenches extending in a first direction in the semiconductor substrate to form plural projections each of which has a pair of side surfaces; (b) implanting opposite type impurity ions to the trenches to form opposite conductive type regions in the semiconductor substrate, the opposite conductive type regions serving as the source and the gate of the cell transistor; (c) forming a first insulation layer in the surface of the opposite conductive type region and the side surface of the projection; (d) depositing first conductive material on both side surfaces and on the opposite conductive type region to form floating gates, the floating gate having a side surface that faces the projection via the first insulation layer; (e) dividing the first conductive material with respect to the first direction to form a pair of floating gates, the floating gate having a side surface that faces the projection via the first insulation layer; (f) depositing a second conductive material on the whole surface; and (g) forming a control gate by etching the portion of the second conductive material that is not covered with a stripe-shaped resist mask extending in a second direction perpendicular to the first direction, the control gate facing the top side of the projection via a second insulation layer, and the width of the resist mask in the first direction being smaller than the width floating gate.