Patent ID: 7135740

Claim:
A field-effect transistor (FET) switch, comprising: an N− drift layer; a first N+ layer on said N− drift layer which provides an ohmic contact to said N− drift layer; a first layer of metal on said first N+ layer which provides a drain connection for said FET switch; a pair of trenches recessed into said N− drift layer to a predetermined depth opposite said N+ layer, said trenches separated by a mesa region comprised of that portion of said N− drift layer found between said pair of trenches, said predetermined depth defining the bottom of said trenches; layers of oxide lining the sides of said trenches to form oxide side-walls in each trench that extend to the bottom of said trenches; a conductive material which fills each of said trenches; a second layer of metal connecting the conductive material in each of said trenches together which provides a gate connection for said FET switch; respective shallow P regions extending across the bottoms of respective trenches into said N− drift layer, each of said shallow P regions extending around the bottom corners of its respective trench's oxide side-walls; a second N+ layer on said N− drift layer within said mesa region which provides an ohmic contact to said mesa region; and a third layer of metal contacting said second N+ layer which provides a source connection for said FET switch; such that the application of a positive voltage to said gate connection greater than the built-in potential that exists between said shallow P regions and said N− drift layer causes holes to be injected from said shallow P regions into said N− drift layer thereby modulating said N− drift layer's conductivity and turning said switch on and enabling current to flow between said drain and said source connections via said mesa region; said ohmic contacts and said conductivity modulation combining to provide a low on-resistance for said switch.