Patent ID: 7419869

Claim:
A manufacturing method of a semiconductor device equipped with a plurality of nonvolatile memory cells each comprising a plurality of first electrodes placed over a semiconductor substrate, a plurality of second electrodes disposed over the semiconductor substrate to cross the plurality of first electrodes, and a plurality of third electrodes for charge accumulation disposed at positions which lie between any two adjacent ones of the plurality of first electrodes and overlap with the plurality of second electrodes two-dimensionally, the method comprising the steps of: (a) forming a first insulating film over the semiconductor substrate; (b) depositing, over the first insulating film, a third-electrode forming conductor film; (c) depositing a second insulating film over the third-electrode forming conductor film; (d) patterning the second insulating film and the third-electrode forming conductor film to form a plurality of layered patterns having the second insulating film and the third-electrode forming conductor film; (e) forming sidewalls over the side surfaces of each of the plurality of layered patterns; (f) forming a third insulating film over the semiconductor substrate between any two adjacent ones of the plurality of layered patterns; (g) depositing over the semiconductor substrate a first-electrode forming conductor film to fill the film between any two adjacent ones of the plurality of layered patterns; (h) removing the first-electrode forming conductor film to leave the film between any two adjacent ones of the plurality of layered patterns, thereby forming the plurality of first electrodes between any two adjacent ones of the plurality of layered patterns in self alignment with the plurality of layered patterns; (i) depositing a fourth insulating film over the semiconductor substrate to fill the film between any two adjacent ones of the plurality of layered patterns; (j) removing the fourth insulating film to leave a portion of the fourth insulating film between any two adjacent ones of the plurality of layered patterns, thereby forming the pattern of the fourth insulating film over the plurality of first electrodes between any two adjacent ones of the plurality of layered patterns in self alignment with the plurality of layered patterns; (k) removing the second insulating film; (l) removing the exposed sidewalls; (m) depositing a fifth insulating film over the semiconductor substrate; (n) depositing a second-electrode forming conductor film over the fifth insulating film; (o) patterning the second-electrode forming conductor film to form the plurality of second electrodes; and (p) patterning the third-electrode forming conductor film with the plurality of second electrodes as a mask, thereby forming the plurality of third electrodes having a projecting cross-section permitting the plurality of third electrodes to be higher than the plurality of first electrodes in self alignment with the plurality of second electrodes.