Patent ID: 8918590

Claim:
A multicore system in which a requester core makes a read request for data present in a memory, comprising: one memory; a main memory controller for connecting the memory to a ring bus; and a plurality of cores connected to the ring bus, wherein each of the cores further includes a cache interface and a cache controller for controlling the interface, the main memory controller further includes a cache history of all the cores, and in response to the request flowing in a predetermined path direction from the requester core to the main memory controller, the cache controller of each core connected to the ring bus executes: a step of snooping data on the request through the cache interface; and when the cache of the core connected in the predetermined path direction holds the data, a step of controlling the core to receive the request and return the data to the requester core; or when the cache of the core connected in the predetermined path direction does not hold the data, the main memory controller references the history of each core, and when any core connected to the ring bus in a reverse path direction to the predetermined path direction holds corresponding data, the main memory controller executes: a step of sending the request to the cache of the core and causing the cache controller of the core to send the data held in the cache to the requester core; or when no core connected to the ring bus in the reverse path direction to the predetermined path direction holds corresponding data, a step of reading the data from the memory and sending the data to the requester core.