Patent ID: 7134038

Claim:
A system for converting data rate, comprising: a first set of flip-flops configured in series; a second set of flip-flops configured in parallel and operatively coupled to the first set of flip-flops; and a third set of flip-flops configured in parallel and operatively coupled to the second set of flip-flops, wherein the first set of flip-flops is configured to store, in series, data in response to a first clock signal, wherein the second set of flip-flops is configured to store, in parallel, the stored data in the first set of flip-flops in response to the first clock signal, wherein the third set of flip-flops is configured to store, in parallel, the stored data in the second set of flip-flops in response to a second clock signal, and wherein the second clock signal has a faster clock rate than the first clock signal.