Patent ID: 7532483

Claim:
A method of interconnecting a first signal (“S 1 ”) line from an external circuit to a corresponding S 1 pad on an integrated circuit (“IC”) die, wherein the S 1 line is switchably connectable to a common signal (“Scom”) line of the IC that is in turn switchably connectable to a second signal (“S 2 ”) line of the IC, and wherein the S 1 line is terminated to a ground potential via a characteristic impedance while it is switchably decoupled from the Scom connection to the integrated circuit and is concurrently required to maintain at least 60 dB of isolation from a target signal (“S_target”) line, the method comprising: a) connecting the S 1 line from the S 1 pad on the IC to an S 1 connection terminal of the external circuit via an S 1 metallic path; b) switchably coupling the S 1 pad to a plurality of S 1 return pads via corresponding S 1 termination paths on the IC die that together approximately establish the characteristic impedance between the S 1 pad and the S 1 return pads, wherein the S 1 return pads are disposed on opposite sides of the S 1 pad and in operation will all be approximately at the ground potential; and c) connecting each of the plurality of S 1 return pads to the external circuit via a corresponding S 1 return metal path connected at one end to the S 1 return pad and at an opposite end to a corresponding S 1 return connection point, which in operation is coupled to the ground potential, such that a sum of currents of all S 1 return metal paths is substantially equal to an S 1 current that is conducted by the S 1 metallic path.