Patent ID: RE42145

Claim:
A memory bit cell comprising cross-coupled first and second inverters, each one of the inverters further comprising a pull-up transistor and a pull-down transistor having series-connected terminals defining a storage node, a first pass transistor coupled between a write bus and a first one of the storage nodes, a second pass transistor coupled between a read bus and a second one of the storage nodes, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, and a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, wherein one of the first and second pass transistors is an NMOS transistor and the other one of the first and second pass transistors is a PMOS transistor.