Patent ID: 7102183

Claim:
A MOS transistor, comprising: a semiconductor substrate region having N-type conductivity type; a first diffusion layer having P-type conductivity type, being provided in said semiconductor substrate region; a second diffusion layer having P-type conductivity type, being provided in said semiconductor substrate region; a channel region, being provided between said first diffusion layer and said second diffusion layer in an interior of said semiconductor substrate region; a gate insulating film, comprising a high dielectric constant film having higher dielectric constant than silicon oxide and being provided on said channel region; and a gate electrode, comprising polycrystalline silicon containing N-type impurity and being provided on said gate insulating film, the gate electrode sufficiently doped with the N-type impurity to inhibit gate depletion in the presence of Fermi level pinning occurring by diffusion within the high dielectric constant film.