Patent ID: 8258581

Claim:
An integrated circuit, comprising: a first transistor of a first transistor type formed in part by a first gate electrode formed to extend lengthwise in a first direction, wherein the first gate electrode corresponds to a first portion of a first gate level conductive structure formed within a first gate level channel within a gate level region of the integrated circuit; a first transistor of a second transistor type formed in part by a second gate electrode formed to extend lengthwise in the first direction, wherein the second gate electrode corresponds to a second portion of the first gate level conductive structure, wherein the second gate electrode is substantially co-aligned with the first gate electrode along a common line of extent in the first direction; a second transistor of the first transistor type formed in part by a third gate electrode formed to extend lengthwise in the first direction, wherein the third gate electrode corresponds to a portion of a second gate level conductive structure formed within a second gate level channel within the gate level region of the integrated circuit; a second transistor of the second transistor type formed in part by a fourth gate electrode formed to extend lengthwise in the first direction, wherein the fourth gate electrode corresponds to a portion of a third gate level conductive structure formed within a third gate level channel within the gate level region of the integrated circuit, wherein the first and second transistors of the first transistor type are formed in part by diffusion regions of a first diffusion type, and wherein the first and second transistors of the second transistor type are formed in part by diffusion regions of a second diffusion type, and wherein the diffusion regions of the first diffusion type are physically separate from the diffusion regions of the second diffusion type, wherein each of the first, second, and third gate level conductive structures is defined within its corresponding gate level channel without physically contacting another gate level conductive structure defined within an adjoining gate level channel, wherein each of the first transistor of the first transistor type and the second transistor of the first transistor type is formed in part by a shared diffusion region of the first diffusion type, wherein each of the first transistor of the second transistor type and the second transistor of the second transistor type is formed in part by a shared diffusion region of the second diffusion type, and wherein the first gate level channel is located between the second and third gate level channels.