Patent ID: 8074034

Claim:
A memory controller comprising: a first volatile memory interface adapted with logic to directly interface to a host volatile memory control, data, and address bus; the memory controller adapted to present to a host system an address space exclusively for storage locations in a volatile memory separate from the memory controller; a second volatile memory interface adapted with logic to directly interface to control, data, and address busses for the volatile memory; the controller adapted with logic to pass signals unchanged between the first volatile memory interface to the second volatile memory interface; a nonvolatile memory interface adapted with logic to couple with a nonvolatile memory; logic to copy the contents of both modified and unmodified areas of the volatile memory to the nonvolatile memory upon a loss of a primary power source for the volatile memory; the nonvolatile memory adapted with at least twice the memory storage capacity of the volatile memory; and logic to prevent direct access by the host system to an address space of the nonvolatile memory.