Patent ID: 6991982

Claim:
A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells comprising a memory transistor and a selection transistor, in which method parallel, strip-shaped active regions which are mutually isolated by field oxide are formed in a semiconductor body so as to border on a surface thereof, after which the surface is provided with a first system of conductor tracks which are covered with an insulating layer and directed transversely to the active regions, which conductor tracks serve as control gates of memory transistors at the location where the conductor tracks and the active regions cross each other, and below which conductor tracks, at the location where the conductor tracks and the active regions cross each other, charge storage zones of these transistors are formed, whereafter a layer of conductive material is deposited which is subsequently subjected to a planarization treatment, after which the flat conductive layer thus formed is provided with an etch mask with strips directed transversely to the active regions and extending above and directly next to the conductor tracks of the first system, after which the flat, conductive layer is anisotropically etched in accordance with a pattern, a second system of conductor tracks directed transversely to the active regions being formed which serve as a selection gate of selection transistors at the location where the conductor tracks and the active regions cross each other, characterized in that the conductive layer is deposited in a thickness such that the planarization treatment results in a flat layer which completely covers the insulating layer present on the conductor tracks of the first system of conductor tracks, so that by etching the flat, conductive layer a second system of conductor tracks is formed which extend to above the conductor tracks of the first system.