Patent ID: 7254505

Claim:
An apparatus for calibrating delay lines in an integrated circuit (IC), the apparatus comprising: a pulse generating circuit having an input and an output, the pulse generating circuit generating an electrical pulse signal upon receiving an edge of an electrical signal, the pulse signal having a substantially fixed time duration; a delay line having an input and an output, the delay line comprising a plurality of delay elements and delay element selection logic, the delay line receiving at the input of the delay line a pulse signal output from the pulse generating circuit and delaying the pulse signal from arriving at the output of the delay line by a time delay of a duration that depends on selection or deselection of delay elements by the delay element selection logic; and a feedback loop for feeding the delayed pulse signal output from the delay line back to the input of the pulse generating circuit, wherein receiving an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate a pulse signal.