Patent ID: 6850527

Claim:
A device for associating indexes to addresses chosen from among a greater number of values than the number of available indexes, including: a memory having a plurality of memory locations, each memory location containing at least one index and one respective check word, the check word of each index being equal to a first set of bits having first predetermined positions in the address that is to be associated with said indexes; a packing circuit for receiving a current address and for providing a packed address equal to a second set of bits having second predetermined positions in the current address, said first and second predetermined positions being distinct, said packed address used to select in a read mode a memory location; and a comparator for comparing the check word of said selected memory location to a third set of bits having said first predetermined positions in the current address, and for indicating that the current address corresponds to the selected memory location when the check word of the selected location is equal to the third set of bits.