Patent ID: 6900628

Claim:
A semiconductor integrated circuit, comprising: a first chip including a first input pad capable of communicating an electrical signal and a second chip including a second input pad capable of communicating an electrical signal; said first chip including a first power supply node for receiving a supply of a first voltage in a normal operation, a second power supply node for receiving a supply of a second voltage which is lower than said first voltage in said normal operation, a first protection circuit forming a current path between said first input pad and said first power supply node when the voltage of said first input pad is higher than that of said first power supply node by at least a prescribed amount while forming a current path between said first input pad and said second power supply node when the voltage of said first input pad is lower than that of said second power supply node by at least a prescribed amount, and a first test supply voltage control portion for setting the voltages of said first and second power supply nodes at the time of a test, said second chip including a third power supply node for receiving a supply of said first voltage in said normal operation, a fourth power supply node for receiving a supply of said second voltage in said normal operation, a second protection circuit forming a current path between said second input pad and said third power supply node when the voltage of said second input pad is higher than that of said third power supply node by at least a prescribed amount while forming a current path between said second input pad and said fourth power supply node when the voltage of said second input pad is lower than that of said fourth power supply node by at least a prescribed amount, and a second test supply voltage control portion for setting the voltages of said third and fourth power supply nodes at the time of said test; said semiconductor integrated circuit further comprising an external pin terminal for an electrical contact with said first and second input pads, said external pin terminal receiving an input of a prescribed current for testing said contact with said first and second input pads at the time of said test.