Patent ID: 8566770

Claim:
A sequential logic or memory cell and layout, comprising two or more latches, each latch having at least one net that stores a voltage state having a value, and at least one net that stores an opposite value, inverse, of the voltage state, comprising: a. an arrangement of contact areas of each net of each latch, which keep a certain voltage state or its inverse, in such a way that the contact areas of at least 4 of these nets are positioned along one line in the layout, and positioned relative to each other such that two contact areas which are placed next to each other: i. are part of nets which carry the same voltage state, and for which a single event has an opposite effect on the voltage state of the net to which the contact area belong; or ii. are part of different nets, which carry different voltage states, a certain state and its inverse, and for which said single event has the same effect on the voltage of the net.