Patent ID: 7884660

Claim:
A programmable delay element, comprising: a buffer configured to receive a source signal at a first input of the programmable delay element and to provide a first delayed replica of the source signal at a first output of the programmable delay element; and an interpolating multiplexer comprising a first input coupled to an output of the buffer, a second input coupled to a second input of the programmable delay element for receiving a second delayed replica of the source signal, and a third input for receiving a digital control signal comprising a plurality of bits, the interpolating multiplexer further comprising a plurality of switching elements, each switching element being operative in response to a corresponding bit of the digital control signal, wherein the interpolating multiplexer is configured to produce an output signal at a second output of the delay element comprising a first contribution of the first delayed replica and a second contribution of the second delayed replica in accordance with a state of the plurality of switching elements.