Patent ID: 7376808

Claim:
A method for modeling the performance of a memory address translation mechanism (MATM) while varying the memory page sizes of the application's data space, comprising: a) generating an execution profile that contains a memory address reference stream of an application, and events about the application's data allocations and de-allocations; b) generating a set of page size mappings; c) translating each memory reference in the input memory reference stream into a reference to a corresponding data object, by consulting the memory allocation and de-allocation events, to provide a data object reference stream; d) translating each data object reference into a corresponding page reference by consulting the page size mapping and by modeling the data allocation and de-allocation events in accordance with the mapping to provide a page reference stream and a number of pages of each page size that are needed by the respective mapping; e) using the page reference stream to provide a stream of reuse distance values; f) determining, for each reference in the reuse distance value stream, whether the reference results in a hit or a miss reference to the MATM to provide the number of hits and the number of misses for each MATM; and g) providing the hit and miss values to a cost model to estimate the number of miss cycles.