Patent ID: 8809965

Claim:
A semiconductor device including a first MIS transistor and a second MIS transistor, wherein the first MIS transistor includes: a first gate insulating film formed on a first active region of a semiconductor substrate and including a first high dielectric constant film, a first gate electrode formed on the first gate insulating film, first offset sidewalls formed on side surfaces in a gate length direction of the first gate electrode, second offset sidewalls formed on side surfaces in a gate length direction and the side surfaces of the gate width direction of the first gate electrode with the first offset sidewalls being interposed between the second offset sidewalls and the first gate electrode, and first extension regions formed in the first active region laterally outside the first gate electrode, the second MIS transistor includes: a second gate insulating film formed on a second active region of the semiconductor substrate and including a second high dielectric constant film, a second gate electrode formed on the second gate insulating film, third offset sidewalls formed on side surfaces in a gate length direction and a gate width direction of the second gate electrode, fourth offset sidewalls formed on the side surfaces in the gate length and width directions of the second gate electrode with the third offset sidewalls being interposed between the fourth offset sidewalls and the second gate electrode, and second extension regions formed in the second active region laterally outside the second gate electrode, and the first offset sidewalls are formed along the gate length direction but not formed along the gate width direction of the first gate electrode.