Patent ID: 7672112

Claim:
A component-embedded substrate comprising: a chip capacitor included in the component-embedded substrate, the chip capacitor including a ceramic laminate body and a plurality of terminal electrodes, the ceramic laminate body including a dielectric layer and a plurality of internal electrodes stacked along the dielectric layer, the plurality of terminal electrodes being arranged to connect the internal electrodes with one another; and first and second principal surfaces; wherein at least two of the plurality of terminal electrodes are connected to the first principal surface and define a first terminal electrode group; at least two of the plurality of terminal electrodes are connected to the second principal surface and define a second terminal electrode group; at least one terminal electrode in the first terminal electrode group is electrically connected to at least one terminal electrode in the second terminal electrode group via at least one of the internal electrodes; capacitance is provided by at least one pair of the terminal electrodes in the first terminal electrode group via the dielectric layer, and capacitance is provided by at least one pair of the terminal electrodes in the second terminal electrode group via the dielectric layer; and a direction in which the internal electrodes are stacked is parallel or substantially parallel to the first and second principal surfaces of the component-embedded substrate.