Patent ID: 6937530

Claim:
A memory device comprising: a plurality of inputs for receiving an external clock signal and a plurality of input signals; an array of memory cells; a command decode circuit connected to the inputs, the command decode circuit includes a decode output for providing a command signal to operate on the array of memory cells; and a delay locked loop (DLL) connected to the decode output, the DLL including: a plurality of delay stages for applying a first amount of delay to the external clock signal to generate a delayed signal; a selector connected to the delay stages for receiving the delayed signal to provide an internal clock signal, wherein the external and internal clock signals are synchronized; and a command react circuit connected to the selector, the command react circuit including a first input for receiving the command signal and a second input for receiving a phase detect signal and a command react circuit output for providing a select signal, wherein the command react circuit causes the selector to change the first amount of delay to a second amount of delay when the command signal is activated by certain combination of the inputs signals.