Patent ID: 7560201

Claim:
A method of transferring a circuit design layout to a layer of an integrated circuit (IC), the method comprising: using a resolution enhancement technique (RET) to define one or more fine-line patterns in a first masking layer, wherein the first masking layer is formed on the IC layer, wherein each feature of each fine-line pattern has a dimension less than a wavelength of light used to define the fine-line pattern, wherein a pitch of each fine-line pattern is less than or equal to the wavelength; one of removing and designating for removal portions of the fine-line pattern(s) not needed to implement the circuit design, and protecting desired portions of the fine-line features defined in the first masking layer; patterning the first masking layer, thereby forming a patterned first masking layer; forming a second masking layer over the patterned first masking layer; defining a plurality of coarse features of the circuit design layout in the second masking layer, wherein defining the plurality of coarse features includes accessing a desired layout of the layer of an integrated circuit, performing a shrink operation until any fine-line pattern on the desired layout disappears, and performing a grow operation on the shrunk layout so that any coarse feature has substantially a same size as that on the desired layout, wherein at least one coarse feature is formed to connect two fine-line features; patterning the second masking layer; and patterning the IC layer using a composite mask formed by the patterned first masking layer and the patterned second masking layer.