Patent ID: 7330386

Claim:
A semiconductor memory device in which memory cells are arranged in a matrix, each said memory cell being formed of a single transistor, the semiconductor memory device comprising: a plurality of word lines provided so as to correspond to rows in the matrix, respectively, each said word line being connected in common to respective gate terminals of transistors located in an associated one of the rows; a plurality of bit lines provided so as to correspond to columns in the matrix, respectively, each said bit line being connected to at least one of respective drain terminals of transistors located in an associated one of the columns; a plurality of source lines provided so that each said source line corresponds to every adjacent two rows in the matrix and is connected in common to respective source terminals of transistors located in the two rows; a precharge circuit for precharging the bit lines to a precharge potential according to a precharge signal indicating a period for precharging the bit lines; a precharge signal generator circuit for generating the precharge signal; and one or more source bias control circuits for controlling, during an active period in which an operation of reading out data from one of the memory cells, at least one of the source lines which is not connected to said one of the memory cells which is to be read out to be in a state where a source bias potential that is higher than a ground potential and lower than a power supply potential is supplied.