Patent ID: 7506126

Claim:
A mode detection circuit for initiating a memory access operation in a memory device receiving memory address signals and control signals, the detection circuit comprising: a first mode detection circuit operable to generate a first mode detection signal to be provided at a first output node in response to receipt of the memory address signals and receipt of control signals requesting an asynchronous memory access operation; a second mode detection circuit operable to generate a second mode detection signal to be provided at a second output node in response to receipt of an active clock signal and receipt of control signals requesting a synchronous memory access operation; a delay circuit coupled to the first and second mode detection circuits, the delay circuit including a timing circuit operable to provide a delayed mode detection signal a time delay after receiving a first occurrence of the first mode detection signal, the delay circuit further operable to interrupt provision of the delayed mode detection signal in response to the second mode detection signal, the delay circuit including a reset circuit operable to restart the timing circuit upon receiving a second occurrence of the first mode detection signal during the time delay; and an output circuit coupled to the second mode detection circuit and the delay circuit, the output circuit operable to provide an activation signal to initiate a memory access operation in response to the delayed mode detection signal or the second mode detection signal.