Patent ID: 8913459

Claim:
A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses, the method comprising: providing a clock signal to the plurality of DRAM devices; providing a read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal; providing a read clock signal to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address, wherein the one of the plurality of DRAM devices delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate a first delayed read clock signal to activate an input of a FIFO receiving read data; delaying the read clock signal by an amount corresponding to a speed of a slowest one of the plurality of DRAM devices to generate a second delayed clock signal; providing the second delayed read clock signal to the plurality of DRAM devices to initiate a data output operation in the one of the plurality of DRAM devices, wherein the one of the plurality of DRAM devices activates an output of the FIFO to supply the read data to the data bus; and receiving the read data on the data bus in synchronization with the second delayed read clock signal.