Patent ID: 8669618

Claim:
A semiconductor device and metal gates comprising: a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; a gate dielectric layer formed in the first gate trench and the second gate trench, respectively; a first U-shaped metal layer formed in the first gate trench and the second gate trench, and topmost portions of the first U-shaped metal layer being lower than openings of the first gate trench and the second gate trench; a second U-shaped metal layer formed in the first gate trench and the second gate trench, topmost portions of the second U-shaped metal layer being lower than openings of the first gate trench and the second gate trench, and the topmost portions of the first U-shaped metal layer and the topmost portions of the second U-shaped metal layer being un-coplanar; and a third U-shaped metal layer formed in the first gate trench and between the first U-shaped metal layer and the second U-shaped metal layer, topmost portions of the third U-shaped metal layer being lower than openings of the first gate trench and the second gate trench, and the topmost portions of the third U-shaped metal layer and the topmost portions of the second U-shaped metal layer being un-coplanar.