Patent ID: 8224264

Claim:
A circuit comprising: a digital signal processor (DSP) having one or more outputs ports, said DSP for generating at east three digital signals with a first one of the digital signals corresponding to a digital in-phase signal (I), a second one of the digital signals corresponding to a digital quadrature-phase signal (Q) and a third one of the digital signals corresponding to an envelope signal (E); a digital to analog converter (DAC) circuit coupled to receive the I, Q and E signals at digital input ports and to provide analog versions thereof at first, second and third output ports; a supply voltage selection circuit having a first plurality of inputs, each of said first plurality of inputs configured to couple to at least one rail voltage and having a second plurality of inputs configured to accept signals from said DSP and to provide an output voltage signal in response to values of the signals from said DSP; an envelope power supply circuit configured to receive an output voltage signal from said supply voltage selection circuit and an analog version of the envelope signal and to provide an amplifier bias voltage at an output there of wherein the voltage level of the amplifier bias voltage tracks the envelope signal; and an upconverter having a pair of input ports coupled to the first and second output ports of said DAC to receive analog versions of the I and Q signals, having a local oscillator port and having an RF output port; and an RF amplifier having an RF input port coupled the RF output port of said upconverter, an RF output port coupled to an output port of the circuit and a bias port coupled to an output of the envelope power supply circuit wherein the at least three digital signals generated by said DSP are each provided having N-bits and wherein the most significant M-bits of at least one of the at least three digital signals is provided to said supply voltage selection circuit such that the supply voltage rails are selected always to be above or equal to the envelope signal generated by the envelope power supply circuit.