Patent ID: 8305145

Claim:
A receiving circuit comprising: a first voltage-dividing circuit comprising first and second resistors connected in series between a first input terminal through which one of differential signals is input and a bias terminal through which a bias voltage is input, the first voltage-dividing circuit being configured to output a first input signal obtained by voltage division of the one of the differential signals based on a resistance ratio between the first and second resistors; a second voltage-dividing circuit comprising third and fourth resistors connected in series between a second input terminal through which another of the differential signals is input and the bias terminal, the second voltage-dividing circuit being configured to output a second input signal obtained by voltage division of the another of the differential signals based on a resistance ratio between the third and fourth resistors; a differential amplifier that amplifies the differential component between the first and second input signals; a common-mode voltage detection circuit that detects a common-mode voltage of the differential signals, the common-mode voltage detection circuit being connected between the first and second input terminals; and a bias voltage switching circuit that switches a voltage value of the bias voltage based on the common-mode voltage, wherein when the common-mode voltage is less than a threshold voltage at which the voltage value of the bias voltage is switched, the bias voltage switching circuit sets the bias voltage to a voltage value greater than the voltage value used when the common-mode voltage is greater than the threshold voltage.