Patent ID: 8252642

Claim:
A method comprising: providing a wafer having an impurity concentration and having a resistivity no greater than 20 ohm-centimeters, and having a top surface and a bottom surface; forming a first plurality of wells having a first conductivity type; forming a second plurality of wells having a second conductivity type opposite the first conductivity type; implanting ions into the wafer to form a substantially continuous buried layer in the wafer, the buried layer comprising the first conductivity type and a buried layer impurity concentration greater than the wafer impurity concentration, said buried layer extending substantially continuously beneath and vertically spaced apart from both the first and second plurality of wells; forming a first plurality of transistors proximate to the top surface of the wafer, said first plurality of transistors including a respective transistor disposed in each of the first plurality of wells; forming a second plurality of transistors proximate to the top surface of the wafer, said second plurality of transistors including a respective transistor disposed in each of the second plurality of wells; forming a conductive layer on the bottom surface of the wafer, to provide a vertical conductive path between the buried layer and the conductive layer.