Patent ID: 7944661

Claim:
A protection circuit for flat display device comprising: an input terminal inputting an input PWM (Pulse Width Modulation) control signal, having a high-logic voltage and a low-logic voltage; a signal attenuator attenuating the input PWM control signal, wherein the signal attenuator attenuates the high-logic voltage of the input PWM control signal; a reference voltage circuit dividing a first driving voltage from a first voltage source into a first reference voltage and a second reference voltage and outputting the first reference voltage and the second reference voltage, wherein the first reference voltage corresponds to a minimum allowable voltage of the attenuated high-logic voltage and the second reference voltage corresponds to a maximum allowable voltage of the attenuated high-logic voltage; and a comparison circuit comparing the attenuated PWM signal with the first reference voltage and second reference voltage and then outputting an output PWM control signal corresponding to the input PWM control signal to an output terminal, or a ground voltage to the output terminal, wherein the comparison circuit comprises; a second voltage source supplying a high-logic output voltage of the output PWM control signal to the output terminal through a pull-up resistor, the high-logic output voltage corresponding to the high-logic voltage of the input PWM control signal; a first comparator comparing the attenuated PWM signal with the first reference voltage, so that an output terminal of the first comparator is an infinite impedance state or outputs the ground voltage; and a second comparator comparing the attenuated PWM signal with the second reference voltage, so that an output terminal of the second comparator is the infinite impedance state or outputs the ground voltage, wherein the output terminal of the comparison circuit is commonly connected to the output terminals of the first and second comparators, and wherein the high-logic voltage of the input and output PWM control signals is higher than a voltage receivable by the first and second comparators.