Patent ID: 8375345

Claim:
A computer-implemented method of laying out an integrated circuit design comprising: receiving a machine-readable description of the integrated circuit design, by executing first instructions in a computer system; identifying at least one logic block in the description which is to be pre-optimized for placement wherein the at least one logic block has a first plurality of cells, input pins, output pins, and internal nets interconnecting the first plurality of cells, by executing second instructions in the computer system; deriving timing assertions for the at least one logic block, by executing third instructions in the computer system; generating a placement abstract for the at least one logic block, by executing fourth instructions in the computer system; synthesizing the at least one logic block using the timing assertions and the placement abstract, by executing fifth instructions in the computer system; removing placement information for the synthesized at least one logic block, by executing sixth instructions in the computer system; assigning lower-hierarchical weights to the internal nets, by executing seventh instructions in the computer system; assigning higher-hierarchical weights to external nets which interconnect a second plurality of cells outside of the at least one logic block, wherein the lower-hierarchical weights are greater than the higher-hierarchical weights, by executing eighth instructions in the computer system; and placing the first plurality of cells and the second plurality of cells with a wirelength optimization using the assigned lower-hierarchical weights and the assigned higher-hierarchical weights, by executing ninth instructions in the computer system.