Patent ID: 7816740

Claim:
An integrated circuit (IC) including a memory array having a plurality of memory cells, each memory cell in said memory array comprising: at least a first body region comprising a first plurality of source/drain regions, said first plurality of source/drain regions defining source/drains of a first pull-up or pull-down (PU/PD) transistor coupled to a first storage node, a second PU/PD transistor coupled to a second storage node, a first driver transistor, a first cell pass transistor, and a first buffer pass transistor, said first body region and said first plurality of source/drain regions being oppositely doped; a first gate electrode region defining a gate of at least said first PU/PD transistor and said first driver transistor; a second gate electrode region defining a gate of at least said first cell pass transistor and said first buffer pass transistor; and a third gate electrode region defining a gate of said second PU/PD transistor, wherein said third gate electrode region is coupled to said first storage node, said first gate electrode region is coupled to said second storage node, said first cell pass transistor is coupled to said first storage node, said first buffer pass transistor and said first driver transistor are coupled to a source/drain path of said first cell pass transistor, and said first buffer pass transistor is coupled between a first bitline (BL) node and said first driver transistor.