Patent ID: 8508398

Claim:
A system for a successive-approximation-register analog-to-digital-converter (SAR ADC), the system comprising: a first capacitive digital-to-analog converter (DAC), the first capacitive DAC having a size less than a second DAC of the SAR ADC, each of the first and second capacitive DACs receiving a value and a reference value, wherein the value received by the first DAC and the second DAC is the same value; a first conversion control module that generates first and second signals for a comparator of the SAR ADC based on outputs of the first and second capacitive DACs and an analog input signal; a second conversion control module that generates third and fourth signals for an SAR control module of the SAR ADC based on outputs of the comparator; and the SAR control module, the SAR control module configured to (i) control the first and second conversion control modules during a full conversion and a partial conversion, the full conversion preceding the partial conversion, (ii) determine an offset of the comparator based on the third and fourth signals received from the second conversion control module during each of the full and partial conversions, and (iii) control the SAR ADC based on the determined comparator offset.