Patent ID: 7301834

Claim:
A semiconductor memory device comprising: a plurality of memory cell arrays having a plurality of memory cells or memory cell units each of which include a plurality of memory cells, arranged in a matrix, the plurality of memory cell arrays being located independently of each other; a first memory cell array included in the plurality of memory cell arrays; a second memory cell array included in the plurality of memory cell arrays; a third memory cell array included in the plurality of memory cell arrays; a fourth memory cell array included in the plurality of memory cell arrays; a first memory cell array group including the first memory cell array and the second memory cell array; and a second memory cell array group including the third memory cell array and the fourth memory cell array, wherein the first memory cell array, the second memory cell array, the third memory cell array and the fourth memory cell array are different from one another, a first Pass/Fail signal indicative of success or failure of an operation is outputted in accordance with each of the first memory cell array group and the second memory cell array group.