Patent ID: 8421199

Claim:
A semiconductor package structure, comprising: a dielectric layer having a third surface and an opposite fourth surface; a metal layer disposed on the third surface and having a die pad and a plurality of traces, the traces each comprising a trace body, a bond pad extending to a periphery of the die pad, and a trace end opposite to the bond pad; a plurality of metal pillars penetrating the third surface and the fourth surface of the dielectric layer, wherein an end of each of the metal pillars is exposed from the third surface and connected to the die pad and the trace ends, and the other ends of the metal pillars protrude from the fourth surface; a plurality of metal pads disposed on the ends of the metal pillars protruding from the fourth surface without contacting the fourth surface, respectively; a semiconductor chip mounted on the die pad; a plurality of bonding wires electrically connecting the semiconductor chip to the bond pads, respectively; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the third surface of the dielectric layer.