Patent ID: 8686782

Claim:
A phase-lock loop device that generates a frequency adaptive clock signal across voltage domain boundaries comprising: a voltage controlled oscillator that receives an analog reference voltage; a level shifter that receives a clock signal from the voltage controlled oscillator and the analog reference voltage input to the voltage controlled oscillator and outputs the frequency adaptive clock signal, the level shifter further comprising: a first inverter connected to the output of the voltage controlled oscillator; a second inverter connected to the output of the first inverter; a capacitor connected to the output of the second inverter; a variable impedance circuit connected to the output of the capacitor; a fourth inverter coupled to the output of the variable impedance circuit; and wherein the variable impedance circuit enables the level shifter to be frequency adaptive by making the impedance very high at low voltage on the variable impedance circuit and making the impedance very low at high voltage on the variable impedance circuit.