Patent ID: 7136109

Claim:
A pixel clock generating circuit, comprising: a digital circuit generating a first signal, the first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency, and an analog circuit electrically coupled to the digital circuit, the analog circuit comprising: a reverse biased variable capacitance device having an anode and a cathode; an integrator having an input coupled to the digital circuit and an output coupled to the cathode of the reverse biased variable capacitor, the integrator arranged to integrate the first signal received from the digital circuit and produce an output voltage across the reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency; and a comparator circuit electrically coupled to the anode of the reverse biased variable capacitor, the comparator circuit producing the pixel clock having a frequency based on the capacitance of the reverse biased capacitor.