Patent ID: 6890812

Claim:
A method for forming a memory cell, comprising: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along side of the pillar, wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave the polysilicon layer only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; forming a gate opposing the single crystalline vertically oriented material of the second conductivity type; and forming a capacitor coupled to the second contact layer.