Patent ID: 7364973

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a gate insulating layer on a semiconductor substrate of a first conductivity type, the semiconductor substrate including a mask read only memory (ROM) device region and a high voltage device region; forming a plurality of gate electrodes in each of the mask ROM device region and the high voltage device region on the gate insulating layer; forming a mask islanded double diffused drain (MIDDD) type lightly doped region in the high voltage device region by implanting impurities of a second conductivity type, opposite the first conductivity type, only into the high voltage device region; coding a mask ROM by forming a plurality of source/drain regions by selectively implanting impurities of the second conductivity type only into the mask ROM device region to define an ON cell and an OFF cell in the mask ROM device region; forming an MIDDD-type heavily doped region in the high voltage device region by additionally implanting impurities of the second conductivity type into the MIDDD-type lightly doped region of the high voltage device region; and selectively additionally implanting impurities of the second conductivity type only into a source/drain region having a bit line contact in the mask ROM device region concurrently with the additional implanting of impurities of the second conductivity type for forming the MIDDD-type heavily doped region in the high voltage device region.