Patent ID: 8453095

Claim:
A method, comprising: a) creating a technology file adapted for use by an electronic design automation tool, the technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer; b) creating a netlist based on the technology file, the netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer; c) simulating a performance of the integrated circuit based on the netlist using an electronic design automation tool; d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings; e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings; and f) storing a data file representing a model of the integrated circuit in a non-transient computer readable storage medium.