Patent ID: 7674661

Claim:
A method of manufacturing a memory device, the method comprising: forming a pair of channel layers on both sidewalls of a sacrificial single crystalline layer pattern on a semiconductor substrate, the forming the pair of channel layers including, forming a preliminary channel layer on both sidewalls of the sacrificial single crystalline layer pattern and an exposed portion of the semiconductor substrate, the sacrificial single crystalline layer pattern not being formed on the exposed portion of the semiconductor substrate, the sacrificial single crystalline layer pattern extending in a first direction, and removing a portion of the preliminary channel layer formed on the exposed portion of the semiconductor substrate; etching the exposed portion of the semiconductor substrate to a depth to form a recess at an upper portion of the semiconductor substrate; forming an isolation layer in the recess; forming an ONO layer and a conductive layer on the isolation layer, the channel layers, and the sacrificial single crystalline layer pattern; patterning the ONO layer and the conductive layer to form an ONO layer pattern and a conductive layer pattern that extends in a second direction substantially perpendicular to the first direction; forming a spacer on sidewalls of the ONO layer pattern and the conductive layer pattern before the sacrificial single crystalline layer pattern is removed; and removing the sacrificial single crystalline layer pattern, wherein the sacrificial single crystalline layer pattern has an etching selectivity with respect to an upper portion of the semiconductor substrate so that the upper portion of the semiconductor substrate is substantially not removed when the sacrificial single crystalline layer pattern is removed.