Patent ID: 7403412

Claim:
A multi-supply CMOS static random access memory (SRAM) supplied by a base supply, portions of said multi-supply SRAM being supplied by an increased supply, said increased supply supplying a voltage above said base supply, said multi-supply SRAM comprising: an array of SRAM cells, each of said SRAM cells comprising: a pair of tailored NFET pass gates, each connected between a storage node and one of a pair of complementary bit lines, and a pair of cross-coupled inverters connected between an increased supply line (V dd+ ) line and a supply return line, each of said cross coupled inverters comprising: a first tailored n-type field effect transistor (NFET) exhibiting less leakage at the base supply voltage than base NFETs having a stated base design characteristic, said first tailored NFET connected drain to source between a storage node and a return voltage, and a PFET connected drain to source between said storage node and said V dd+ line, said storage node of the other of said pair of cross-coupled inverters connected to a control terminal of both said first tailored FET and said FET of said second conduction type; a word line decoder selecting a row of said cells in said array; a plurality of word line drivers connected to V dd+ and each driving a word line in a selected said row, said word line connected to a control terminal in both of said pair of tailored NFET pass gates, said word line driver selectively driving said word line substantially to V dd+ ; a bit decoder selecting a column of said cells in said array; at least one sense amplifier sensing data stored in a selected one of said cells; at least one input/output (I/O) driver powered by V dd , each said I/O driver passing written data to a selected said colunm and redriving sensed said data; local clock logic powered by Vdd and providing local timing for each cell access; and glue logic powered by V dd and controlling accesses to said SRAM.