Patent ID: 8208331

Claim:
A method, comprising: precharging a first output node and a second output node to a precharge voltage by coupling a channel of a first pre-charge FET between the first output node and a positive supply voltage; coupling a channel of a second pre-charge FET between second output node and a positive supply voltage, and coupling the channel of a third pre-charge FET between the gates of the first and second pull up FETs and applying a pre-charge control signal to a gate of each of the first, second and third pre-charge FETs; coupling at least one memory cell to a bit line (BL) and receiving a voltage value representing a stored data on the BL; receiving a voltage on a bit line bar (BLB); and sensing a relative voltage between the BL and the BLB in an imbalanced cross-coupled latch (ICL) and outputting a logic low value if a difference between a voltage on the BL and a voltage on the BLB exceeds a threshold, and outputting a logic high value if the difference does not exceed the threshold; wherein sensing the relative voltage comprises coupling the BL and BLB to the first and second output nodes and providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes, respectively, and an electrical ground coupled through the channel of an enable FET, each of the first and second pull down FET transistors having a gate coupled to the second and the first output nodes, respectively, in a cross coupled arrangement, and providing at least a first and a second pull up FET each having a channel coupled between a positive supply voltage and the first and second output nodes and each having a gate coupled to the second and first output nodes, respectively, and wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET.