Patent ID: 8830770

Claim:
A semiconductor memory device, comprising: a bit line equalizing signal generating unit including: a pulse signal generating unit configured to generate a pulse signal pulsing in a certain period by delaying an enable signal that is enabled corresponding to an active period, wherein a delay period of the enable signal and the certain period correspond to first and second activation periods, respectively; a drive controlling unit configured to generate a first pull-up drive signal that is enabled during the first activation period, a second pull-up drive signal that is enabled during the second activation period, and a pull-down drive signal that is enabled during an inactivation period of a bit line equalizing signal in response to the pulse signal and the enable signal; and a driving unit configured to drive an output terminal in response to the first and the second pull-up drive signals and the pull-down drive signal, wherein the bit line equalizing signal has a first supply voltage in the first activation period of a precharge operation period, has a second supply voltage in the second activation period of the precharge operation period directly following the first activation period, and has the first supply voltage in a third activation period of the precharge operation period directly following the second activation period, wherein the drive controlling unit includes: a first level shifting unit configured to shift the pulse signal to a second supply voltage level; an inverting unit configured to invert an output signal of the first level shifting unit to thereby output the second pull-up drive signal; and a drive signal generating unit configured to generate the first pull-up drive signal and the pull-down drive signal in response to the enable signal and the pulse signal.