Patent ID: 6931611

Claim:
A verification system comprising: a representation of a first design representing a specification having a predetermined functionality; a representation of a second design, the representation of the second design intended to satisfy the predetermined functionality of the first design, the verification system functioning to affirm that the representation of the second design satisfies the predetermined functionality of the representation of the first design; a plurality of design inputs; a tester for comparing the representation of the second design with the representation of the first design, and detecting when the representation of the second design does not satisfy the representation of the first design, the tester providing a failure indicator and a characterization of a failure in response to the detecting, the tester further comprising: a failure analyzer for applying one or more constraints to the characterization of the failure, the one or more constraints representing restrictions on permissible test parameters of the second design representation, and determining whether the one or more constraints will prevent the failure from occurring.