Patent ID: 7417457

Claim:
An integrated circuit, comprising: a first switching network (SN) comprising: a first plurality of M number of conductors; a second plurality of N sets of k number of conductors, where N is greater than two and where k is greater than two; a third plurality of I number of conductors comprising a fourth plurality of N sets of I0 number of conductors, wherein I0 approximately equals to M/N; and a first plurality of switches, wherein through the first plurality of switches, each of the M number of conductors of the first plurality of M conductors selectively couples to the third plurality of I number of conductors, wherein at least M−N+1 number of conductors of the first plurality of M conductors selectively couples to one of the I0 number of conductors of each of the fourth plurality of N sets of I0 number of conductors; and a second plurality of switches, wherein through the second plurality of switches, each of the I0 number of conductors of each set of the fourth plurality of N sets of the I0 number of conductors selectively couples to all conductors in one set of a respective set of the second plurality of N sets of k number of conductors without requiring any selectable connection of another conductor.