Patent ID: 7105933

Claim:
A semiconductor integrated circuit device comprising: a silicon substrate; a plurality of internal circuits each formed on an element region of the silicon substrate; a first input/output (I/O) cell formed on an I/O cell region of the silicon substrate, the first I/O cell including a first I/O circuit, a first electrode portion horizontally spaced apart from the first I/O circuit with respect to the silicon substrate and a second electrode portion formed on the first I/O circuit, the first electrode portion and the second electrode portion electrically connected to each other and electrically connected to a first internal circuit of the plurality of internal circuits; a second I/O cell formed on the I/O cell region of the silicon substrate, the second I/O cell including a second I/O circuit and a third electrode portion formed on the second I/O circuit, the third electrode portion electrically connected to a second internal circuit of the plurality of internal circuits; and an interlayer insulating film formed on the plurality of internal circuits, the first I/O cell and the second I/O cell and exposing the first electrode portion as a probing pad, the second electrode portion as a first terminal pad and the third electrode portion as a second terminal pad.