Patent ID: 8896126

Claim:
An integrated circuit package comprising: a first memory die having a first set of connections; a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections; a first substrate having (i) a first opening between a first portion and a second portion of the first substrate and (ii) a second opening between the second portion and a third portion of the first substrate, the first substrate having a third set of connections on the first portion to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections on the third portion to connect to the second set of connections of the second memory die via the second opening, wherein the second portion of the first substrate includes no connections to (i) the first set of connections of the first memory die and (ii) the second set of connections of the second memory die; and a second substrate having a first integrated circuit disposed thereon, wherein the first substrate is connected to the second substrate using solder balls with the first integrated circuit disposed between the first substrate and second substrate.