Patent ID: 8378487

Claim:
A packaged chip comprising: a semiconductor chip having a front surface, contact pads exposed at said front surface, and posts projecting upwardly from said front surface, said posts having sidewalls; a first dielectric material disposed on the front surface of the chip and on the sidewalls of the posts so that the first dielectric material and the posts form risers, each riser including a post and having a sloping surface defined by the first dielectric material, the sloping surfaces of each riser as a whole being disposed at a lesser angle to the front surface than the sidewall as a whole of the post included in the riser, said risers having tips; conductive lines propagating from the contact pads to the tips of the risers and extending over said sloping surfaces of the risers; and terminals terminating the conductive lines, said terminals being disposed on the tips of the risers.