Patent ID: 7211867

Claim:
A thin film memory cell comprising: a semiconductor thin film having a first principal surface and a second principal surface opposite the first principal surface; a first gate insulating film formed on the first principal surface of the semiconductor thin film; a first conductive gate formed on the first gate insulating film; a first semiconductor region and a second semiconductor region which are spaced apart from each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type; and a third semiconductor region having a conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film; wherein the semiconductor thin film has a combination of a thickness and an impurity concentration that depletion of carriers is caused between the first principal surface and the second principal surface between the first and second semiconductor regions below the first conductive gate under an electric potential of the first conductive gate; wherein a portion of the semiconductor thin film that is sandwiched between the first semiconductor region and the second semiconductor region forms a first channel formation semiconductor thin film portion; wherein the semiconductor thin film is extended between the first channel formation semiconductor thin film portion and the third semiconductor region to form a second channel formation semiconductor thin film portion which is in direct contact with the first channel formation semiconductor thin film portion; wherein a second gate insulating film is formed on the extended portion of the semiconductor thin film and a second conductive gate is formed on the second gate insulating film; and wherein the first conductive gate and the second conductive gate overlap each other and are insulated from each other by an intergate insulator.