Patent ID: 7848266

Claim:
A frequency synthesizer system to generate selectable analog output signals in response to an analog input signal, comprising: a first phase-locked loop (PLL) arranged to include a digitally-controlled oscillator (DCO) and to respond to said input signal to provide a reference signal with a plurality of selectable reference frequencies; and a second PLL arranged to include a voltage-controlled oscillator (VCO) to thereby provide said output signals in response to said reference signal; wherein said DCO is configured to respond to a tuning word and a DCO clock whose clock frequency f c establishes the width f c /2 of a plurality of Nyquist frequency zones and wherein said first PLL includes: a first feedback frequency divider to provide a divided reference signal; a low-pass analog reconstruction filter coupled between said DCO and said first feedback frequency divider and configured to substantially reject signals in all but a first one of said Nyquist zones to thereby generate said reference signal; a digital phase/frequency detector arranged to process said input signal and said divided reference signal; and a digital loop filter arranged to provide said tuning word to said DCO in response to said digital phase/frequency detector.