Patent ID: 8868960

Claim:
A method for synchronously stopping and starting units on chips in a node of a multi nodal computer system comprising a plurality of nodes, each of which includes chips of different types, wherein one of the chips is configured as a master chip, the master chip being connected to slave chips via at least two multi-drop nets, the at least two multi-drop nets comprising a checkstop net and a clockrun net, and wherein the master chip and the slave chips are connected to a reference clock, the method comprising: in response to a request received by the master chip from one of the chips to trigger events in the units, sending by the master chip a respective command to itself and to the connected slave chips at a next pulse of the reference clock following receiving of the request; and in response to the command being received at a receiving chip from the master chip, waiting by the receiving chip a defined number of clock cycles following the next pulse of the reference clock, and subsequently triggering a respective event in its units, depending on the received command.