Patent ID: 8227307

Claim:
A method of forming a semiconductor structure comprising: forming a threshold voltage adjusting layer atop a high k gate dielectric that is located above a semiconductor substrate; forming a patterned mask protecting a portion of the threshold voltage adjusting layer, while leaving another portion of the threshold voltage adjusting layer unprotected; forming an acid polymer atop the patterned mask and atop an exposed portion of the threshold voltage adjusting layer, said acid polymer comprises a polymerized compound or mixture of compounds comprising repeating structural units including at least one acid functional group attached thereto; baking the acid polymer to increase the acid concentration in the acid polymer and to diffuse acid moieties into the exposed portion of the threshold voltage adjusting layer which react with the exposed threshold voltage adjusting layer to provide an acid reacted threshold voltage adjusting layer; removing the baked acid polymer using an aqueous solution or an organic solvent; removing the patterned mask and the acid reacted threshold voltage adjusting layer, wherein at least said acid reacted threshold voltage layer is removed by a dry etching process selected from the group consisting of reactive ion etching, ion beam etching, plasma etching and laser ablation; and forming a conductive material atop remaining portions of the threshold voltage adjusting layer.