Patent ID: 6841448

Claim:
A method for fabricating embedded nonvolatile semiconductor memory cells, which comprises the steps of: providing a substrate divided into a high-voltage region, a memory region and a logic region; forming a first insulating layer on the substrate in the high-voltage region, the memory region and the logic region; removing the first insulating layer in the memory region; forming a second insulating layer in the high-voltage region, the memory region and the logic region; forming a charge storing layer in the high-voltage region, the memory region and the logic region; patterning the charge-storing layer in the memory region; forming a third insulating layer in the high-voltage region, the memory region and the logic region; removing the first to third insulating layers and also the charge-storing layer in the logic region; forming a fourth insulating layer in the high-voltage region, the memory region and the logic region; and forming and patterning a conductive control layer in the high-voltage region, the memory region and the logic region.