Patent ID: 8685633

Claim:
A method for optimizing wafer edge patterning, said method comprising providing a mask, said mask useable to print on a wafer, said mask having a first image, a second image, a third image, and a fourth image, wherein the mask is configured for exposure such that the first image is useable in a photolithography process to print a first, main image on the wafer, wherein the mask is configured for exposure such that each of the second and fourth images is useable in a photolithography process to print edge dummy shots around an edge of the first, main image, wherein the mask is configured for exposure such that the third image is useable in a photolithography process to print a second, alternative image on the wafer, wherein the mask is configured for exposure such that each of the first and third images is useable in a photolithography process to print edge dummy shots around an edge of the second, alternative image.