Patent ID: 8653606

Claim:
A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type adjacent to the first semiconductor layer; a plurality of first trenches; gate electrodes each of which is provided in each of the plurality of the first trenches; and a first and a second regions which are disposed between the first trenches and the second region has a wider distance between the first trenches than the first region, wherein the first region is provided with: a third semiconductor layer of the first conductivity type adjacent to the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type adjacent to the third semiconductor layer, the gate electrode is disposed in the first trench, contacting with the third semiconductor layer, the fourth semiconductor layer and the second semiconductor on each surface thereof via a first insulation film, and provided with: a first electrode that contacts in a low resistance with the first semiconductor layer; and a second electrode that contacts in a low resistance with the third semiconductor layer and the fourth semiconductor layer, the second region is provided with: a plurality of second trenches; and a third electrode disposed in each of the plurality of the second trenches, having a second insulation film between itself and a trench sidewall, and electrically connected to the second electrode, and the second semiconductor layer is interposed between the first trench and the second trench.