Patent ID: 8320379

Claim:
An arbiter circuit comprising: a plurality of input buffers to temporarily store packets arriving at input ports; and a packet switch to switch a packet between a particular input port of the plurality of input buffers and a particular output port, the packet switch being further to: concurrently process a first plurality of sequences, each sequence including portions that make up a packet, and assign packets, respectively associated with the first plurality of sequences, for output through the output ports at different times from one another, the packet switch including: a plurality of unit modules, each of the plurality of unit modules being associated with at least one of the input buffers and at least one of the output ports, the plurality of unit modules to process the first plurality of sequences; a first signal line connecting the plurality of unit modules in a ring, a first signal being transmitted through the first signal line in a first direction of the ring; and a second signal line connecting the plurality of unit modules in the ring, a second signal being transmitted through the second signal line in a second direction in the ring, opposite to the first direction.