Patent ID: 8175015

Claim:
A media access control (MAC) processor, comprising: a programmable controller; a memory coupled to the programmable controller, the memory to store machine readable instructions for implementing MAC functions corresponding to i) first data received by a communication device and ii) second data received by the communication device; and a hardware processor coupled to the programmable controller, wherein the hardware processor includes: a processing engine configured to implement MAC functions on the first data and the second data received by the communication device, wherein the first data corresponds to a first burst in a frame conforming to the Institute for Electrical and Electronics Engineers (IEEE) 802.16 Standard, and the second data corresponds to a second burst in the frame, a context memory coupled to the processing engine, the context memory to store state information of the processing engine corresponding to a plurality of contexts, wherein the plurality of contexts correspond to a plurality of respective bursts in the frame, and context switch logic coupled to the processing engine, the context switch logic i) to determine when the processing engine should switch contexts and ii) to signal the processing engine to pause processing the first data and to begin processing the second data, wherein the context switch logic is configured to cause a context switch based on an amount of data corresponding to a burst stored in a memory; wherein the processing engine is configured to i) pause processing the first data prior to completing processing of the first data, and ii) later resume processing the first data after processing at least some of the second data using state information stored in the context memory.