Patent ID: 8098344

Claim:
A liquid crystal display device, comprising: first through N-th gate bus lines formed parallel on a substrate; plural data bus lines formed over said substrate so as to cross said first through N-th gate bus lines via an insulation film; plural accumulation capacitor bus lines formed over said substrate parallel to said first through N-th gate bus lines; first and second transistors formed in each stage defined by a gate bus line and in each column defined by a data bus line, each of said first and second transistors having, in each of said stages and columns, a gate electrode connected electrically to said gate bus line and a drain electrode connected to said data bus line; a first picture element electrode connected, in each of said stages and columns, electrically to a source electrode of said first transistor; a second picture element electrode connected, in each of said stages and columns, to a source electrode of said second transistor and isolated from said first picture element electrode; and a third transistor provided in each of said stages and columns, said third transistor having, in each of said stages and columns, a gate electrode connected electrically to said gate bus line, said third transistor having, in each of said stages and columns, a source region connected to a second picture element electrode of a stage immediately preceding said stage, each of said third transistors in each stage further comprising a first buffer capacitance electrode connected electrically to a drain electrode thereof and a second buffer capacitance electrode disposed opposite to said first buffer capacitance electrode via an insulation film and connected to said accumulation capacitance bus line electrically, another third transistor being provided also in an (N+1)th stage following said N-th stage in each of said plural columns, said (N+1)th stage having a (N+1)th gate bus line, said another third transistor connecting, in said (N+1)th stage, N-th second picture element electrode of said column to a corresponding buffer capacitance.