Patent ID: 6856546

Claim:
A multi-state memory, comprising: a plurality of EEPROM memory cells, each of said memory cells coupled to a word line and to a bit line and able to store one of a plurality of multi-states, organized into a plurality of sectors; at least one tracking cell for each of said multi-states, associated with each of said plurality of sectors; read circuitry to read raw data associated with a programmed state of said tracking cell; converter circuitry to convert said raw data to digital form; circuitry to precharge said bit line coupled to a selected plurality of said memory cells and to then turn-on said word line coupled to selected said memory cells using a word line signal; wherein discharge rate of potential on said bit line provides a measure of program drive for said memory cell; and a memory controller to establish desired read points for each of a plurality of physical states, based upon digitally converted read said raw data from each said tracking cell.