Patent ID: 7569457

Claim:
A method of fabricating a semiconductor device, comprising steps of: (a) forming a gate electrode of an n-channel MISFET over an element isolation region of a first semiconductor region of p-type conductivity formed in a semiconductor body, and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body, wherein the element forming region is defined by a shallow groove isolation layer such that the shallow groove isolation layer is formed by a CMP method, and wherein a gate length of each of said gate electrodes is less than 200 nm; (b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity; (c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes; (d) after said step (c), implanting ions in a first region in said first semiconductor region to form a fourth semiconductor region of n-type conductivity; (e) after said step (c), implanting ions in a second region deeper than said first region in said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and (f) after said steps (d) and (e), forming a cobalt-silicide layer in said fourth semiconductor region, wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region, wherein said gate electrode of said n-channel MISFET is an N-type gate electrode, and wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.