Patent ID: 7225116

Claim:
A method for eliminating routing congestion in an integrated circuit (IC) layout for an IC to be fabricated, wherein a placement plan specifies a position within the layout for each of a plurality of cells that are be included in the IC, and wherein the cells are to be interconnected by nets routed in accordance with a routing plan, the method comprising the steps of: a. selecting one of the cells and a target position therefor; b. selecting a target area at a portion of the layout such that if the placement plan were to be revised to specify that the selected cell is to be positioned anywhere within the target area, the revision to the placement plan would reduce an amount of space within the layout that the routing plan must allocate to the nets to be connected to that cell, the target area being peripherally defined about the target position by a boundary selectively set for the selected cell; c. dividing the target area into an array of blocks delineated therein, wherein each block spans a separate portion of the target area, and wherein each block includes cell space for accommodating cells and routing space for accommodating nets; d. selecting one of the blocks having an estimated amount of unoccupied cell space sufficient to accommodate the selected cell; and e. revising the placement plan so that it specifies that the selected cell is to be positioned within the selected block.