Patent ID: 8581384

Claim:
A semiconductor package structure at least comprising: a lead frame having a plurality of leads, wherein each of the leads comprises: a first end portion, a second end portion and a half-etched portion in connection with the first end portion and the second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, the second end portion comprises a second upper surface and a second lower surface, and the half-etched portion comprises a third upper surface and a third lower surface; at least one chip disposed on top of the leads, wherein said chip comprises an active surface facing toward the first upper surfaces of the first end portions and a plurality of bumps disposed on the active surface, and wherein the bumps are electrically connected with the lead frame; a molding compound covering the chip and the leads, wherein the first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound; and an anti-conduction film covering the first lower surface of the first end portion of each of the leads directly so as to inhibit the first lower surfaces of the first end portions from electrically connecting another electronic component and such that the anti-conduction film is not electrically connected with the first end portions.