Patent ID: 7551114

Claim:
A method of reducing power consumption of a stage of a pipelined sub-analog to digital converter (pipelined sub-ADC) used in a time-interleaved ADC, said pipelined sub-ADC comprising a plurality of stages, said time-interleaved ADC containing a plurality of pipelined sub-ADCs including said pipelined sub-ADC, wherein each pipelined sub-ADC in said plurality of pipelined sub-ADCs is operable to process a corresponding one of a set of samples of an analog input captured by an input sample and hold unit of said time-interleaved ADC, said method comprising: operating said stage of said pipelined sub-ADC with a first set of clock signals, and a next stage of said pipelined sub-ADC with a second set of clock signals, wherein said next stage receives an output of said stage, wherein said first set of clock signals and said second set of clock signals are designed to cause a hold phase of said stage to commence at a first time instance earlier than a second time instance at which a sample phase of said next stage commences when processing the same sample received from said sample and hold unit.