Patent ID: 7861061

Claim:
A method for executing instruction packets on a computer comprising a pipelined processor where each instruction packet comprises a plurality of instructions, each of which is capable of being executed by an execution stage of the pipelined processor, and each of which is in one of a plurality of instruction formats, said method comprising the following steps: fetching a first of the instruction packets during an instruction fetch, wherein the first instruction packet includes each of a plurality of instructions fetched during the instruction fetch, wherein the plurality of instructions includes a first instruction that is in a first of the plurality of instruction formats, wherein the first instruction format comprises a plurality of option bits that indicate which, if any, of the remaining instructions in the first instruction packet are to be executed in the same execution cycle as the first instruction, and wherein the first instruction is the only instruction in the first instruction packet that is in the first instruction format; identifying from the option bits encoded in the first instruction of said plurality of instructions of said first instruction packet which, if any, of the remaining instructions within the first instruction packet are to be executed in the same execution cycle as the first instruction, wherein the option bits comprise at least one bit that corresponds to each of the instructions in the first instruction packet except for the first instruction, and wherein each option bit indicates whether its corresponding instruction is to be executed in the same execution cycle as the first instruction without reference to any of the other option bits; and executing said first instruction and any of said remaining instructions identified from the encoded option bits.