Patent ID: 7674637

Claim:
A structure stress monitoring method, comprising: providing a semiconductor chip which includes M regular solder bump structures and N monitor solder bump structures, wherein M and N are positive integers, wherein each regular solder bump structure of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip, and wherein each monitor solder bump structure of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip; performing a flip chip process for the semiconductor chip resulting in P monitor solder bump structures of the N monitor solder bump structures being cracked, wherein P is a positive integer not greater than N, wherein the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures, and wherein the cool-down stress results from a cool-down step of the flip chip process; determining a value of P; specifying a maximum acceptable number Q of cracked monitor solder bump structures of the N monitor solder bump structures, wherein Q is a positive integer smaller than N; if the value of P is equal to or smaller than Q, then determining that the cool-down stress resulting from the flip chip process is low and acceptable; and if the value of P is greater than Q, then determining that the cool-down stress resulting from the flip chip process is too high and unacceptable.