Patent ID: 7474136

Claim:
A three DLL circuit for assuring a 50% duty cycle of an output data signal of a DDR memory comprising: a first clock signal; a first delay locked loop including a first voltage controlled delay line, a first phase detector and a first feedback signal for generating a second clock signal from the first clock signal; a second delay locked loop including a second voltage controlled delay line and second phase detector for adjusting one transition of the DDR output data signal; a third delay locked loop including a third voltage controlled delay line and third phase detector for adjusting a second transition of the DDR output data signal; a third clock signal with rising and falling edges generated by the rising edges of the second and third delay line outputs, respectively, for enabling the DDR output data signal; and a fourth clock signal generated by delaying the third clock signal by a fixed delay and feeding it back as an input to the second and third phase detectors of the second and third delay locked loops.