Patent ID: 8842792

Claim:
An apparatus, comprising: at least one processor; at least one memory including executable instructions, the at least one memory and the executable instructions being configured to, in cooperation with the at least one processor, cause the apparatus to perform at least the following: broadcast a synchronization signal configured to provide a timing reference for slave devices; broadcast a discovery request packet with a given timing offset with relation to the timing reference, for reception by receptive slave devices having matching timing with the given timing offset; receive a response packet from each receptive slave device with the given timing offset; and detect a timing conflict in which the apparatus has simultaneously received two or more response packets, and to responsively cause the apparatus to transmit to the receptive slave devices a response change request packet, wherein the response change request packet is configured to request one or more of the receptive slave devices to cease sending response packets in response to a following discovery request packet sent with the given timing offset, and to change a timing offset for sending a response packet, wherein the synchronization signal is configured to energize the receptive slave devices, and wherein the at least one memory and the executable instructions are further configured to, in cooperation with the at least one processor, cause the apparatus to test validity of received response packets with check sums to determine a timing conflict from a check sum error.