Patent ID: 8058900

Claim:
A clock gate circuit for generating a clock signal, comprising: a multiplexer configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal, and configured to output the clock signal having the logic state selected from the first logic signal in response to rising transitions of the reference clock signal, and the second logic signal in response to falling transitions of the reference clock signal; and a logic module coupled to the multiplexer and configured to output the first logic signal and the second logic signal based on an enable signal and the output of the multiplexer, the logic module including: a first latch module configured to capture the first logic signal in response to the rising transitions of the reference clock signal and sustain the first logic signal; a second latch module configured to capture the second logic signal in response to the falling transitions of the reference clock signal and sustain the second logic signal; a first voltage pulling module configured to force the first logic signal into a logic state; and a second voltage-pulling module configured to force the second logic signal into the logic state.