Patent ID: 8627168

Claim:
A decoding device for pseudo-cyclic low-density parity-check codes having a structure with a variable cyclic permutation size, at least comprising: a plurality of cumulative LLR memories for storing cumulative reliability information being received values of the low-density parity-check codes or a sum of reliability information generated in a decoding process and the received values; a plurality of column processing/row processing components each including a plurality of processors corresponding to column processing and row processing of low-density parity-check code decoding for updating the reliability information; a multistage difference cyclic permutation means for performing cyclic permutation of data in a multistage fashion with a degree of parallelism corresponding to the number of data in one record of the cumulative LLR memories between the cumulative LLR memories and the column processing/row processing components, and, during writing to the cumulative LLR memories, executing processing integrating permutation for subsequent reading; a received value arrangement means for performing permutation of received data during writing of the received data to the cumulative LLR memories in accordance with operation of the multistage difference cyclic permutation means; an address administration means for storing a reading start address of the cumulative LLR memories and incrementing the address at reading in accordance with operation of the multistage difference cyclic permutation means; and a control means for calculating parameters to be used by the multistage difference cyclic permutation means and the received value arrangement means and the reading start address of the cumulative LLR memories to be stored in the address administration means.