Patent ID: 7447083

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of column groups, each having a predetermined number of column memory blocks, wherein each of the predetermined number of column memory blocks includes a plurality of memory cells sharing a plurality of word lines; a row decoder that decodes a row address signal and activates one of a plurality of word lines according to the decoding result; a column decoder that decodes a column address signal in response to a logic value(s) of one or some of bits of the column address signal and outputs column decoding signals to one of the plurality of column groups; sense amplifier groups respectively connected to the plurality of column groups through main local I/O line groups; and a data I/O circuit that outputs output data to I/O pads in response to amplified data, which are received through global I/O lines, wherein each of the sense amplifier groups amplifies internal data, which are received from a corresponding one of the plurality of column groups, and outputs the amplified data to the global I/O lines, and when any one of the plurality of column groups outputs the internal data in response to the column decoding signals, the remaining column groups do not output the internal data; wherein the column address signal is J bits (J is an integer); wherein the column decoding signals include first to eighth column decoding signals, and the column decoder includes: a select circuit that receives one of the J bits as a select signal and selectively outputs the remaining bits other than the one of the J bits to any one of a first output terminal and a second output terminal in response to the select signal; a first address driver that buffers the remaining bits received from the first output terminal; a second address driver that buffers the remaining bits received from the second output terminal; a first decoding unit that decodes the remaining bits received from the first address driver and outputs the first to fourth column decoding signals; and a second decoding unit that decodes the remaining bits received from the second address driver and outputs the fifth to eighth column decoding signals.