Patent ID: 7550830

Claim:
A stacked semiconductor package comprising: a first semiconductor package including: a first semiconductor chip having a first surface and a second surface; a plurality of redistribution patterns overlying the first surface of the semiconductor chip; a plurality of bond pads and a plurality of first solder ball pads formed on the first surface of the semiconductor chip, wherein a first group of the plurality of bond pads are respectively electrically connected to the plurality of first solder ball pads via a first group of the plurality of redistribution patterns; an insulating layer overlying the plurality of redistribution patterns, the insulating layer including openings to respectively expose portions of a second group of the redistribution patterns to define a plurality of first bond fingers; a multi-layered printed circuit board having a first surface and a second surface, the printed circuit board including a chip recess defined therein to receive the semiconductor chip; a plurality of second solder ball pads and a plurality of second bond fingers formed on the first surface of the printed circuit board; and a plurality of third solder ball pads formed on the second surface of the printed circuit board, wherein the first bond fingers and the second bond fingers are electrically connectable to each other a plurality of first solder balls formed on the third solder ball pads; and a second semiconductor package stacked on the first semiconductor package, the second semiconductor package electrically connected to the first semiconductor package through the first solder balls.