Patent ID: 7239574

Claim:
A synchronous storage device capable of switching between a first operation mode for accessing in synchronism with either edge of a pulse of an external clock signal and a second operation mode for accessing in synchronism with both edges of a pulse of the external clock signal, the synchronous storage device comprising: an L−n detector for counting pulses of the external clock signal while counting the initial latency (L) from start of accessing, and detecting the number of pulses of the external clock signal (L−n) by subtracting n, wherein n is a numerical value of 1 or greater in increments of 0.5, from the initial latency (L); and an internal clock signal generator coupled to the L−n detector for switching an internal clock signal from a first clock signal for synchronizing with either edge of a pulse of the external clock signal to a second clock signal for synchronizing with both edges of a pulse of the external clock signal, in response to the detected signal from the L−n detector when the second operation mode is being set.