Patent ID: 8299819

Claim:
A circuit configuration for reducing resettling time of a current detector means, said circuit configuration comprising: a differential pair of transistors including a first transistor which is coupled between a second node and a third node, wherein said first transistor receives a first input signal of a predetermined value at a first node, and a second transistor which is coupled between said third node and a fifth node, wherein said second transistor receives a second input signal of a variable value at a fourth node, said variable value being able to make a large shift relative to said predetermined value; a pair of transistors with a polarity different from said differential pair of transistors, including a third transistor which is coupled between said second node and said third node, and a fourth transistor which is coupled between said third node and said fifth node, wherein said third transistor and said fourth transistor share a common input terminal which is connected to said fourth node.