Patent ID: 6950488

Claim:
A delay locked-loop circuit comprising: a phase detector for detecting a phase difference between an external clock signal and an internal clock signal; a delay unit controller for generating a control signal in response to output of the phase detector; and a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising: a first group of delay cells used at or above a predetermined frequency; a second group of delay cells used with the first group of delay cells below the predetermined frequency; switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal; and a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group, wherein the delay use signal is a signal representing either the use of a last delay cell in the first group of delay cells or one of the remaining delay cells except the last delay cell.