Patent ID: 7757233

Claim:
A method of controlling a computer system having at least one processor including a plurality of cores, the method comprising: establishing a core max value, the core max value setting a maximum number of the plurality of cores operating at a predetermined time period based on an operating condition; determining a core run value, the core run value being associated with a number of the plurality of cores of the at least one processor operating at the predetermined time period; identifying at least one of the plurality of cores to stop in the event the core run value exceeds the core max value at the predetermined time period; transferring processes including a call stack, paging status, and memory access to memory from the at lease one of the plurality of cores prior to stopping the at least one of the plurality of cores; stopping the at least one of the plurality of cores, including stopping a process running at the at least one of the plurality of cores, in the event the core run value exceeds the core max value at the predetermined time period; re-determining the core run value including re-determining the number of the plurality of cores of the at least one processor currently operating; restarting the at least one of the plurality of stopped cores, including restarting the stopped process running at the at least one of the plurality of stopped cores, based on a priority level of the at least one of the plurality of stopped cores with respect to priority levels of other stopped cores if at least two cores have been stopped, in the event the core max value exceeds the re-determined core run value; and transferring processes including the call stack, the paging status, and the memory access from the memory to the restarted at least one of the plurality of cores.