Patent ID: 7948812

Claim:
A memory controller comprising: a. a phase reference node to convey a phase reference signal; b. a read strobe terminal to receive a read strobe; c. a write circuit having; i. a write strobe terminal from which a write strobe having a write-strobe phase is issued; ii. a write-data terminal from which write data having a write-data phase; is issued and iii. a write-phase adjustment node to receive a phase-adjustment signal; iv. wherein the write circuit adjusts at least one of the write-strobe phase and the write-data phase responsive to the phase-adjustment signal; and d. a phase comparator having a first comparator input node coupled to the read strobe terminal, a second comparator input node coupled to the phase reference node, and a comparator output node coupled to the write-phase adjustment node, the phase comparator to issue the phase adjustment signal on the comparator output node responsive to phase differences between the read strobe and the phase reference signal.