Patent ID: 7667517

Claim:
A system for generating a second clock from a first clock, wherein a ratio of a frequency of the first clock to a frequency of the second clock is a non-integer, the system comprising: a divider configured to use rising and falling edges of the first clock to generate cycles of the second clock, the cycles of the second clock having a duration of a first number of cycles of the first clock, wherein the divider is configured to generate other cycles of the second clock, the other cycles having the duration of a second number of cycles of the first clock, wherein the divider is configured to calculate a first timing error between a time associated with a first edge of the first clock and a time for an edge at the frequency for the second clock, wherein the divider is configured to calculate a second timing error between a time associated with a second edge of the first clock and the time for an edge at the frequency for the second clock, wherein the divider is configured to generate an edge at the time of the first edge if the first timing error is less than the second timing error, and wherein the divider is configured to generate an edge at the time of the second edge if the second timing error is less than the second timing error.