Patent ID: 6902959

Claim:
A method for fabricating a semiconductor device comprising: forming a gate wire over a gate insulating layer on a predetermined portion of an active region of a semiconductor substrate of a first conductivity-type; forming source/drain regions in the substrate at opposite edges of the gate wire by selectively ion-implanting a high density of an impurity of a second conductivity-type; forming a junction diode of the second conductivity-type in the substrate at a predetermined distance apart from the source/drain regions; forming an inter-level insulating layer having a plurality of contact holes to expose predetermined portions of the gate wire and junction diode; forming conductivity plugs in the contact holes; forming a metal layer on the inter-level insulating layer; and simultaneously forming a metal wire coupled to the gate wire, and a dummy metal pattern coupled to the junction diode by selectively etching the metal layer to expose predetermined portions of a surface of the inter-level insulating layer.