Patent ID: 7763514

Claim:
A method of fabricating an integrated circuit including a transistor, the method comprising: forming a gate groove extending in a surface of a semiconductor substrate; forming a first source/drain region and a second source/drain region in the semiconductor substrate, wherein the first and second source/drain regions are adjacent the substrate surface and extend to a first depth as measured from the substrate surface; forming a spacer on a sidewall of the gate groove, wherein the spacer extends from the substrate surface to a depth which is less than the first depth; forming a gate electrode in the gate groove, wherein a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate at a second depth which is less than the first depth, the second depth being measured from the substrate surface, wherein an upper groove portion is defined above the gate electrode; and filling the upper groove portion with an insulating material, wherein the spacer is removed subsequent to forming the gate electrode and prior to filling the upper groove portion with an insulating material.