Patent ID: 7075811

Claim:
A memory system comprising: a ferroelectric memory having a cell driving block and a data amplifying block, the cell driving block applying voltage to a data retention element and the data amplifying block amplifying readout data from the data retention element; a data latch circuit retaining output timings and pulse widths of control signals respectively controlling the cell driving block and the data amplifying block; and a timing generating circuit respectively outputting the control signals to the cell driving block and to the data amplifying block according to the output timings and the pulse widths of the control signals retained in the data latch circuit; wherein: the pulse widths of the control signals retained in the data latch circuit are set so that the pulse widths are shorter in a power-on state during which a power supply potential is supplied to the ferroelectric memory, to the data latch circuit, and to the timing generating circuit, whereas they are longer in a power-off instruction time that is from the time when the cut-off of the power supply potential has been instructed until the supply is cut off; and after the cell driving block and the data amplifying block of the ferroelectric memory have been started to operate with the output timings of the control signals, operating periods of the cell driving block and the data amplifying block are set to be longer in the power-off instruction time than in the power-on state.