Patent ID: 8853785

Claim:
An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; at least one electrically conductive material electrically connected to a gate of the first MOS transistor and arranged between the gate of the first MOS transistor and the channel region of the second MOS transistor; a first dielectric layer arranged at least between the electrically conductive material and the channel region of the second MOS transistor; a plurality of spacers that surround the gate of the first MOS transistor; and a second dielectric layer that at least partially covers a source and drain region of the first MOS transistor and which includes a portion that at least partially covers the plurality of spacers, such that the at least one electrically conductive material covers both the plurality of spacers and at least partially covers the second dielectric layer, wherein the channel region of the second MOS transistor in a plane parallel to the two primary faces of the semiconductor layer is completely included within a projection of the electrically conductive material in said plane, a length, in a cross-sectional view, of the electrically conductive material projected in said plane is greater than a length, in the cross-sectional view, of the channel region of the second MOS transistor projected in said plane, and the channel region of the second MOS transistor is arranged between the electrically conductive material and a gate of the second MOS transistor.