Patent ID: 8053900

Claim:
An integrated circuit structure comprising: a semiconductor chip comprising: a first dielectric layer over a first surface of a substrate; a second dielectric layer over a second surface of the substrate; a first patterned bond pad in the first dielectric layer, the first patterned bond pad protruding from the first dielectric layer, wherein the first patterned bond pad comprises a plurality of first portions, and a plurality of first openings between the plurality of first portions, with the first dielectric layer extending into the plurality of first openings; a second non-patterned bond pad in the second dielectric layer, the second non-patterned bond pad protruding from the second dielectric layer, wherein the second non-patterned bond pad is solid, having no openings formed therein; first connection structures connecting the plurality of first portions of the first patterned bond pad; a first through-silicon via (TSV) and a second TSV in the substrate, wherein the first and the second TSVs are electrically connected to the first patterned bond pad and the second non-patterned bond pad; and a solid bond pad exposed through the first dielectric layer, wherein the solid bond pad is smaller than the first patterned bond pad.