Patent ID: 8285942

Claim:
A method of processing memory requests for a line of data in a multi-level clustered shared-memory multiprocessor system, the method comprising: a processor generating a request for a line of data storable in a system memory; in response to a determination that a region protocol state of an entry within a region coherence array of the system indicates that the requested line of data may be cached by processors at multiple levels of interconnect within an interconnect hierarchy of the multi-level system, determining whether one or more region hint bits within the region protocol state of an entry in the region coherence array associated with the requesting processor provide an indication that the requested line of data is cached by at least one level of interconnect from the multiple levels of interconnect within the interconnect hierarchy of the system, wherein the region hint bits uniquely identify each level of interconnect within the interconnect hierarchy where cached copies of the requested line of data may be stored; in response to determining the one or more region hint bits provide an indication that the requested line of data is cached at a specific level of interconnect within the interconnect hierarchy, sending the request to the at least one level of interconnect within the interconnect hierarchy indicated by the region hint bits; wherein a level of interconnect is one of a chip level interconnect, a same processor node interconnect or another processor node interconnect; wherein the region coherence array is a meta-data array located in a cache hierarchy; determining whether the request for the line of data was satisfied by the specific level of interconnect indicated by the region hint bits; in response to determining the request for the line of data was not satisfied by the specific level of interconnect indicated by the region hint bits, updating, utilizing a most current combined snoop response, the region hint bits to indicate a level of the interconnect hierarchy at which the request for the line of data was actually satisfied; and sending the updated region hint bits to one or more levels of interconnect within the interconnect hierarchy indicated by the region hint bits that do not satisfy the request for the line of data.