Patent ID: 7073142

Claim:
A computer-aided wiring diagram verifying method of verifying diagram data for a wiring mask including oblique wirings which are formed from layout data of a semiconductor integrated circuit design and via cells which are arranged on the oblique wirings, comprising: a layer defining step wherein different layer numbers are defined by a layer defining unit to oblique wiring diagrams and via cell diagrams which are included in the layout data of the semiconductor integrated circuit design; a first diagram blending step wherein diagram data including the oblique wiring diagrams and the via cell diagrams is fetched from said layout data and the diagrams are blended every same layer number by a first diagram blending unit; an oblique wiring verifying step wherein the oblique wiring diagrams blended in said first diagram blending step are verified by an oblique wiring verifying unit; a second diagram blending step wherein said oblique wiring diagrams blended in said first diagram blending step and said via cell diagrams are blended and an oblique wiring mask diagram is formed by a second diagram blending unit; and a blended diagram verifying step wherein the oblique wiring mask diagram blended in said second diagram blending step is verified by a blended diagram verifying unit.