Patent ID: 8044981

Claim:
An image display system, comprising: a first pixel, comprising a first transistor and a first storage capacitor, wherein the first storage capacitor is coupled to the source of the first transistor via a first pixel electrode; a second pixel, comprising a second transistor and a second storage capacitor, wherein the second storage capacitor is coupled to the source of the second transistor via a second pixel electrode; a scan line, coupling the gates of the first and second transistors to transport a scan signal to control the conductance of the first and second transistors; a first data line, coupling the drain of the first transistor, and receiving a voltage data during a first time interval; and a second data line, coupling the drain of the second transistor, and receiving the voltage data during a second time interval later than the first time interval; wherein the first storage capacitor is designed according to the following formula: C st ⁢ ⁢ 1 = Δ ⁢ ⁢ V gate × C gd ⁢ ⁢ 1 Δ ⁢ ⁢ V 1 + V f ⁢ ⁢ 2 - C lc ⁢ ⁢ 1 - C gd ⁢ ⁢ 1 , where C st1 represents the capacitance of the first storage capacitor, C gd1 represents the capacitance of the parasitical capacitor coupled between the gate and drain of the first transistor, C lc1 represents the capacitance of the liquid crystal capacitor of the first pixel, ΔV gate represents the voltage variation at the scan signal, ΔV 1 represents a voltage coupling shift at the first pixel electrode, and V f2 represents a second feedthrough voltage which is the voltage variation at the second pixel electrode that varies with the scan signal.