Patent ID: 8040521

Claim:
A structure including a semiconductor material comprising: a target portion and a second portion, the target portion having a first feature when at least one of the following occurs: an external force or the effects thereof received by the second portion of the structure and an internal condition or the effects thereof occurs in the target portion; at least one or more test conditions, each test condition determined to test stress and circuit characteristics within the semiconductor or free-metal material occurring in the first feature of the target portion; and a plurality of test conditions shaped and arranged to be simultaneously incident to the target portion comprising the combination of at least one or more holograms, interferograms, holographic optical elements, free-carrier holograms, isochromatic holograms, phase-conjugate holograms, four-wave mixing phase holograms, or embossed holograms, or of any combination thereof; each test condition shaped and located to produce a first optical interference or primary interference pattern when the target portion and the corresponding interference pattern of the holograms, interferograms, holographic optical elements, free-carrier holograms, isochromatic holograms, phase-conjugate holograms, four-wave mixing phase holograms, or embossed holograms are exposed to non-invasive illumination and when the target portion has the corresponding at least first feature.