Patent ID: 7375559

Claim:
Differential comparator circuitry comprising: first replica circuitry comprising: input circuitry to receive a first input signal and a first reference signal and to provide a first bias signal; bias circuitry to provide a first control signal in response to the first bias signal, wherein the first bias signal and the first control signal form a first feedback loop; first main input circuitry to receive the first input signal and the first reference signal, wherein the first main input circuitry is biased in response to the first control signal; second replica circuitry comprising: input circuitry to receive a second input signal and a second reference signal and to provide a second bias signal; bias circuitry to provide a second control signal in response to the second bias signal, wherein the second bias signal and the second control signal form a second feedback loop; second main input circuitry to receive the second input signal and the second reference signal, wherein the second main input circuitry is biased in response to the second control signal; and wherein the first main input circuitry and the second main input circuitry are biased to provide an output signal that rejects common-mode differences in the first input signal and the second input signal.