Patent ID: 8586436

Claim:
A method of fabricating a semiconductor device, comprising: forming a plurality of gate structures including a first gate dielectric layer, a first metal layer, and a dummy layer overlying the first gate dielectric layer and the first metal layer; forming a masking element on a third gate structure; removing a first portion of the dummy layer from a first gate structure and a second gate structure of the plurality of gate structures, while the masking element is disposed on the third gate structure; after removing the first portion of the dummy layer, removing the masking element from the third gate structure; after removing the masking element, removing a second portion of the dummy layer, wherein the second portion includes a remaining portion of the dummy layer in the first and second gate structures, wherein the removing the second portion of the dummy layer provides a first trench in the first gate structure, a second trench in the second gate structure, and a third trench in the third gate structure, wherein the first trench has a greater depth than the third trench; and forming a second gate dielectric layer and a second work function metal layer in the first trench and the second trench.