Patent ID: 7488896

Claim:
An electronic device comprising: a wiring board which comprises: (a) a wiring laminated portion including: a plurality of dielectric layers comprised of a polymeric material and a plurality of conductor layers, wherein the plurality of dielectric layers and plurality of conductor layers are alternately laminated so that one of said plurality of dielectric layers may form a first main surface of said wiring laminated portion, (b) a pad array at a board side comprised of a plurality of metal terminal pads disposed on the first main surface, which is formed of said dielectric layer of said wiring laminated portion, and (c) a solder resist layer at the board side provided on the first main surface of said wiring laminated portion and having one or more individually formed openings at the board side so as to expose said metal terminal pads disposed on said pad array at the board side; and a semiconductor component comprising a terminal array at a semiconductor component side provided on a second main surface of the component and comprising a plurality of terminal pads disposed so as to individually correspond to said metal terminal pads constituting said pad array at the board side, wherein said pad array at the board side and said tenninal array at the component side are flip-chip bonded via one or more solder joint portions; wherein D/D 0 is in a range of 0.70 to 0.99, where D is a bottom surface inner diameter of at least one of said openings at the board side in said solder resist layer and D 0 is a cross-sectional diameter of at least one of said solder joint portions at the semiconductor component side.