Patent ID: 7710506

Claim:
A thin film transistor (TFT) array panel, comprising: a substrate divided into a display region and a peripheral region; a gate wiring pattern formed on the substrate; a first insulating film formed on the gate wiring pattern; a data wiring pattern formed on the gate wiring pattern and comprising a first data line and a second data line; a second insulating film formed on the data wiring pattern; a first electrostatic discharge protection circuit comprising: a first capacitor comprising a first electrode and a second electrode; and a resistor comprising a first semiconductor pattern formed in the peripheral region, electrically connected between the first data line and the first electrode, wherein the first electrostatic discharge protection circuit has no control electrode generating an electric field for controlling conductivity of the first semiconductor pattern, and wherein the data wiring pattern comprises the first electrode, and the gate wiring pattern comprises the second electrode; and a third electrode formed on the second insulating film, electrically connected to the first electrode and overlapping the second electrode.