Patent ID: 8355275

Claim:
A resistance change memory comprising: a memory cell including a resistance change element and a stacked layer structure which are connected in series; a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value; and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation, wherein the stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers, an amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor, and the first voltage pulse satisfies R on× C<T -lead< R off× C R on× C<T -trail where T-lead is a rise time [sec] of the first voltage pulse, T-trail is a fall time [sec] of the first voltage pulse, Roff is the first resistance value [Ω], Ron is the second resistance value [Ω], and C is a capacitance [F] of the capacitor.