Patent ID: 8241988

Claim:
A method for use in the fabricating of a semiconductor device, the method comprising: forming a plurality of gate patterns on a cell array region of a semiconductor substrate, and simultaneously forming dummy gate patterns in each of photo key regions spaced apart from one another on a photo key forming region of the substrate located outside and extending along the periphery of the cell array region; subsequently forming a first insulating layer over the substrate which buries the gate patterns and the photo key regions; performing a chemical-mechanical polishing (CMP) of the first insulating layer using the gate patterns and the dummy gate patterns as an etch stop layer; and performing a photolithography-based process to remove the first insulating layer from between the gate patterns and from the photo key regions, the photolithography-based process comprising directing light towards the photo key forming region of the substrate, analyzing that portion of the light which is transmitted as an optical signal from the photo key region, and aligning exposure apparatus of photolithographic equipment with the substrate on the basis of the analysis of the optical signal.