Patent ID: 7999559

Claim:
A digital fault detection circuit, comprising: an input circuit comprising an input and at least one output, wherein a first signal state at the input causes a predetermined signal state at the output and a second signal state at the input leaves the output floating; a signal line comprising a signal line input and a signal line output, wherein the signal line input is coupled to the output of the input circuit; a keeper circuit coupled to the signal line output and configured to keep the signal line at the predetermined signal state, after the signal state at the input has changed from the first signal state to the second signal state; and at least one fault detector cell coupled to the signal line between the signal line input and the signal line output, and configured to change the state of the signal line which is otherwise kept by the keeper circuit, in response to a fault, wherein the fault detector cell comprises a detector cell switch coupled between the signal line and a switchable first supply potential, wherein the detector cell switch is configured to separate the switchable first supply potential from the signal line in the absence of a fault and to connect the switchable first supply potential to the signal line in response to a fault.