Patent ID: 8681576

Claim:
A circuit comprising: a set of pre-charge and equalization devices configured to pre-charge and equalize a pair of data lines; a control signal line configured to control the pre-charge and equalization devices; and a word line configured to electrically couple a memory cell to a data line of the pair of data lines, wherein a first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line, and wherein the first voltage source is configured to generate the first voltage value to satisfy at least one of the following conditions: Vt+VBL<VPCEQ<Vr+VBL ; or (a) | Vt|+VBL<|VPCEQ−VDD|<Vr+VBL; (b) VBL represents a pre-charge and equalization voltage value of the pair of data lines: VDD represents an operational voltage value of the pre-charge and equalization devices; VPCEQ represents the first voltage value; Vt represents a threshold voltage of the pre-charge and equalization devices; and Vr represents a reliability voltage value of the pre-charge and equalization devices, Vr varying depending on a gate oxide thickness of the pre-charge and equalization devices.