Patent ID: 8743652

Claim:
A semiconductor device comprising: a clock terminal supplied with a clock signal having a predetermined frequency from outside; a chip select terminal supplied with a chip select signal from outside; a chip select receiver receiving the chip select signal to activate a first internal chip select signal; a command terminal supplied with a command signal from outside; a command receiver receiving the command signal to generate a first internal command signal, the command receiver being activated based on a first control signal; a latency control circuit activating a second internal chip select signal after elapse of first cycles of the clock signal since the first internal chip select signal is activated, the latency control circuit activating a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles; and a receiver control circuit activating the first control signal in response to the first internal chip select signal and deactivating the first control signal in response to the second control signal.