Patent ID: 7548456

Claim:
A combo memory cell having a random access mode and a read only mode and first and second logic states wherein voltage level of the first logic state exceeds the second logic state, comprising: a static random access memory cell, comprising: a first inverter comprising a first PMOS transistor and a first NMOS transistor, with gates thereof commonly connected to a first input node and drains thereof commonly connected to a first output node; and a second inverter comprising a second PMOS transistor and a second NMOS transistor, with gates thereof commonly connected to a second input node and drains thereof commonly connected to a second output node; wherein the first input node and the second output node are connected, as are the second input node and the first output node; and a mask read only memory (mask-ROM) code programmer coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.