Patent ID: 7657757

Claim:
A semiconductor device comprising: a cipher mode register to store a cipher mode indicator; a plurality of different cipher engine modules, each one of the cipher engine modules to implement a corresponding one of a plurality of different cipher operations; a plurality of different cipher mode logic modules, each one of the cipher mode logic modules to receive logic module input information and to implement a corresponding one of a plurality of different cipher modes on the logic module input information, the plurality of different cipher mode logic modules including a first cipher mode logic module configured to provide logic module output information based upon the received logic module input information to at least one of the plurality of different cipher engines to implement a first cipher mode; and a second cipher mode logic module configured to provide logic module output information based upon the received logic module input information to at least one of the plurality of different cipher engines to implement a second cipher mode; a data synchronization module coupled to receive input information and to selectively provide the logic module input information to one of the plurality of different cipher mode logic modules selected based upon the cipher mode indicator, the logic module input information based upon the input information; and an interface coupled to receive cipher engine input information and to selectively provide, based upon a cipher mode of the one of the plurality of different cipher mode logic modules, the cipher engine input information to one of the plurality of different cipher engine modules, the cipher engine input information based upon the logic module output information from the one of the plurality of different cipher mode logic modules.