Patent ID: 8745319

Claim:
A storage device comprising: flash memory comprising a plurality of physical data blocks; a flash memory controller that controls at least one of addressing, programming, erasing, and reading of the flash memory; a host interface for communicating with a host device; a magnetoresistive random access memory (MRAM) buffer electrically connected between the host interface and the flash controller; a processor that receives commands from the host device via the host interface and coordinates the at least one of addressing, programming, erasing and reading of the flash memory by the flash memory controller; and MRAM device memory electrically connected to the processor, the MRAM device memory storing control information comprising an erase count table and a flash translation layer table, wherein the erase count table comprises an erase count for each of the plurality of physical data blocks of the flash memory, the control information facilitating wear leveling of the flash memory according to a dynamic algorithm that comprises, upon receiving, from the host device, a write command for a logical address: scanning a portion of the erase count table corresponding to data blocks of the flash memory that are available to be written to; selecting an available data block of the flash memory based on its corresponding erase count; writing data corresponding to the write command to the selected data block; updating the flash translation layer table to reflect an association between the logical address and a physical address for the selected data block; and erasing a data block previously associated with the logical address and incrementing an erase count in the erase count table corresponding to the erased data block; wherein the MRAM buffer receives data via the host interface and stores the data until the data is written to the flash memory under control of the flash memory controller; and wherein upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.