Patent ID: 7496874

Claim:
A method of performing critical area analysis on an integrated circuit design having redundant and non-redundant elements, the method comprising the steps of: generating a graphical data symbol representation of the integrated circuit design; identifying any redundant elements of the integrated circuit in the graphical data symbol representation with unique identifiers; analyzing the graphical data symbol representation for undesired open-causing defects in wires and/or vias for the non-redundant elements; treating redundant and non-redundant elements differently during yield estimations in order to perform the critical area analysis; and wherein the generating comprises generating graphical design data (GDD) shapes for performing the critical area analysis for shorts and opens, wherein the critical area analysis for shorts uses the GDD and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design and wherein the critical area analysis for the opens uses the GDD and performs the critical area analysis for only the non-redundant elements of the integrated circuit design.