Patent ID: 7478354

Claim:
A method for producing a chip, comprising the steps of: (A) fabricating said chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of said chip has a plurality of slots, wherein each of said slots has a plurality of first transistors and a core region of said chip has an array of cells comprising a plurality of second transistors, each of said cells comprising (i) five of said second transistors, (ii) two well contacts and (iii) eleven pads in said first metal layer connected to each node of said second transistors and each of said well contacts, respectively; (B) designing a plurality of upper metal layers above said first metal layer in response to a custom design created after said first fabricating has started, said upper metal layers interconnecting a plurality of said first transistors to form a plurality of mixed-signal building block functions; and (C) fabricating said chip to add said upper metal layers during a second manufacturing phase.