Patent ID: 8201051

Claim:
A short burst error detector device, the device comprising: a first signal input, wherein the first signal input is configured to receive a first signal; a second signal input, wherein the second signal input is configured to receive a second signal, the second signal subject to a delay before being received by the second signal input; a logic gate, wherein the logic gate is configured to receive the first signal via the first signal input and the second signal via the second signal input, the logic gate configured to generate a logic output gate signal based on the received first signal and the second signal; a filter, wherein the filter is configured to receive the logic output gate signal from the logic gate and generate a filter output signal based upon the logic output gate signal, wherein the filter output signal is configured to flag errors; wherein the first signal is a soft output (Le), the soft output (Le) is provided to the logic gate via a low-density parity-checking (LDPC) code decoder; and an interleaver configured for receiving a sign disagreement of the soft output (Le) and a soft input (La) ((sign(La)¢sign(Le)), wherein the interleaver is present on the soft output (Le).