Patent ID: 7498856

Claim:
A circuit comprising: a voltage-controlled oscillator comprising an output port to provide an output clock signal, the circuit to provide a first feedback signal derived from the output clock signal; a divider circuit to provide a second feedback signal derived from the output clock signal divided by N+1 with a probability α and divided by N with a probability 1−α, where N is an integer; and a phase frequency detector to provide a first logic signal that is asserted at a rising edge of the reference signal, and to provide a second logic signal that is asserted at a rising edge of the second feedback signal, the phase frequency detector to sample the second logic signal at a rising edge of the first feedback signal to generate a third logic signal, where the third logic signal is sampled at a rising edge of the first feedback signal to generate a reset signal, where the first, second, and third signals are de-asserted after both the first and reset signals are asserted.