Patent ID: 7552272

Claim:
A memory system comprising: a plurality of units of erasable and re-programmable non-volatile memory cells having contiguous physical addresses organized into zones with address boundaries therebetween and wherein a distinct range of logical addresses are mapped into each of the zones; and a memory controller that reassigns the boundary addresses to delete at least one unit from each of the zones and to add said at least one unit to an adjacent zone without changing the number of units in the individual zones, the memory controller subsequently accessing the zones for programming data to or reading data from the reassigned memory cell units therein according to logical addresses of the data, and the memory controller repetitively reassigning the boundary addresses and accessing the zones at least until the plurality of memory cell units have all been moved from their zones to adjacent zones, thereby to spread out usage of the units accessed through the logical addresses; wherein reassigning the boundary addresses includes deleting a number of units from each of the zones less than ten percent of the units within the zone and adding said number of units to an adjacent zone.