Patent ID: 8230138

Claim:
A memory control device that, in response to a read request issued from a bus master, reads data from a memory having a burst transfer function, the memory control device comprising: a read unit operable to issue a read command to the memory according to a first read request issued from the bus master to burst read a predetermined amount of data in the memory starting from an address specified by the first read request; a storage unit operable to, after the read unit completes reading data pertaining to the first read request, continuously read and store data starting from an address following a last address of the data read by the read unit; a transfer unit operable to transfer the data read by the read unit to the bus master; and a determination unit operable to determine, upon newly receiving a second read request from the bus master, whether a difference between an address specified by the second read request and the address specified by the first read request falls within a predetermined range, wherein, if the determination unit determines that the difference between the address specified by the second read request and the address specified by the first read request falls within the predetermined range, then the transfer unit transfers, from the storage unit to the bus master, the predetermined amount of data starting from the address specified by the second read request.