Patent ID: 8202769

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming a stacked-layer structure including a first conductive layer, a first insulating layer provided over the first conductive layer, and a first semiconductor layer provided over the first insulating layer; forming a first mask over the stacked-layer structure, wherein the first mask includes a first region having a first thickness and a second region having a second thickness smaller than the first thickness; etching the first semiconductor layer, the first insulating layer, and the first conductive layer by using the first mask to form a second semiconductor layer, a second insulating layer, and a second conductive layer; side-etching the second conductive layer to form a first eaves portion in the second semiconductor layer and a gate electrode, the first eaves portion projecting beyond sides of the gate electrode; removing the second region of the first mask to form a second mask; etching at least the second semiconductor layer by using the second mask to form a third semiconductor layer including a second eaves portion, the second eaves portion projecting beyond the sides of the gate electrode; and adding an impurity to the third semiconductor layer to form, at least, an impurity region in the second eaves portion and a channel formation region in a position which overlaps the gate electrode.