Patent ID: 7550847

Claim:
A packaged semiconductor device, comprising: a substrate having a substrate surface and a recess extending from the substrate surface into the substrate; a semiconductor die in the recess, the semiconductor die having an integrated circuit and a bond site proximate to the substrate surface; an electric coupler having a first end on the bond site of the semiconductor die and a second end opposit the first end; a dielectric layer having a first portion over the semiconductor die and the electric coupler and a second portion in the recess of the substrate, the first portion of the dielectric layer having a first surface proximate to the substrate surface and a second surface opposit the first surface the first portion of the dielectric layer having a thickness between the first and second surfaces, the thickness being approximately equal to a height of the electric coupler between the first and second ends; and a conductive link on the dielectric layer and in direct contact with the electric coupler, wherein the conductive link and the electric coupler are separate components with a boundary therebetween.