Patent ID: 8174119

Claim:
A semiconductor package, comprising: a substrate; an adhesive layer formed over a first surface of the substrate; a semiconductor die having a back surface mounted to the adhesive layer over the first surface of the substrate; a plurality of conductive pads formed over the first surface of the substrate around a periphery of the semiconductor die; a plurality of first stud bumps formed over the conductive pads over the first surface of the substrate, the first stud bumps having a rounded base portion and a stem portion extending from the rounded base portion, the rounded base portion having a width greater than a width of the conductive pads, the stem portion being aligned with the conductive pads and having a width smaller than the width of the rounded base portion; a plurality of second stud bumps formed over a circuit surface of the semiconductor die, the second stud bumps having a rounded base portion and a stem portion extending from the rounded base portion, the stem portion having a width smaller than a width of the rounded base portion; an encapsulant deposited over the substrate, semiconductor die, first stud bumps, and second stud bumps; and a first patterned conductive layer formed over the encapsulant and electrically connected to the stem portion of the first stud bumps and the stem portion of the second stud bumps, the first patterned conductive layer including conductive traces, wherein a diameter of the stem portion of the first bumps is less than a width of a conductive trace, and wherein each one of the first stud bumps is connected to a corresponding second stud bump by one of the conductive traces.