Patent ID: 7056790

Claim:
A method for manufacturing a DRAM cell, the method comprising: forming a trench in an active region of a semiconductor substrate; implanting impurities into the active region; forming an insulator thin film and a gate insulating film simultaneously on the substrate and the trench; forming a storage node electrode of a MOS capacitor having a T-shaped structure and a gate electrode of a cell transistor simultaneously by depositing a conductive film on the insulator thin film and the trench to bury the trench and then patterning the conductive film; forming a source/drain of the cell transistor by implanting impurities into the resulting material; forming a contact electrode connected to the source/drain of the cell transistor or to the storage node electrode of the MOS capacitor by forming an interlayer insulating film on the whole surface of the resulting material, forming a contact hole on the interlayer insulating film and then burying the conductive film into the contact hole; and forming a wire connected with the drain and the storage node electrode and a bit line connected with the source through the contact electrode by depositing a conductive film on top of the interlayer insulating film and patterning the same.