Patent ID: 8466519

Claim:
A mask-defined read-only memory array formed on a substrate, the mask-defined read-only memory array comprising: a first ROM bit of a first polarity, the first ROM bit comprising: a first block layer formed over a first region of the substrate; a first metal-oxide-silicon (MOS) transistor comprising: a first source/drain diffusion region formed outside the first region of the substrate on a first side of the first block layer; a second source/drain diffusion region formed in the first region of the substrate; and a first gate layer electrically connected to a first word line for inducing a channel between the first source/drain diffusion region and the second source drain diffusion region; a first contact electrically connected to the first source/drain diffusion region for receiving a first select signal; a first diffusion region formed in the first region of the substrate on a second side of the first block layer different from the first side of the first block layer; and a second contact electrically connected to the first diffusion region for receiving a second select signal; and a second ROM bit of a second polarity opposite the first polarity, the second ROM bit comprising: a second metal-oxide-silicon (MOS) transistor comprising: a third source/drain diffusion region; a fourth source/drain diffusion region; and a second gate layer formed between the third source/drain diffusion region and the fourth source/drain diffusion region, the second gate layer electrically connected to a second word line for inducing a channel between the third source/drain diffusion region and the fourth source drain diffusion region; a third contact electrically connected to the third source/drain diffusion region for receiving a third select signal; and a fourth contact electrically connected to the fourth source/drain diffusion region for receiving a fourth select signal.