Patent ID: 8390109

Claim:
A chip package, comprising: a group of semiconductor dies arranged in a plank stack in an x direction, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein a surface for the plane comprises active electronics, wherein the z direction, the x direction and the y direction are substantially perpendicular to each other, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, and wherein the edges of the semiconductor dies define a face of the plank stack; a mechanical spacer between pairs of semiconductor dies in the group of semiconductor dies; and a substrate electrically coupled to the semiconductor dies along the x direction, wherein a plane of the substrate is defined by the x direction and the y direction; and wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads, proximate to a surface of the substrate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.