Patent ID: 7842949

Claim:
An integrated circuit comprising: A. an input die pad B. an output die pad; C. core circuitry having a core input lead and a core output lead; D. an input buffer having an output and having an input connected to the input die pad; E. a tristate output buffer having an input connected to the core output lead, a tristate input, and a data output connected to the output die pad; F. test circuitry having a core input connected to the core output lead, a test enable input lead, a compare strobe input lead, an expected data input lead coupled to one of the input die pad and the output die pad, a mask data input lead coupled to the other of the input die pad and the output die pad, a scan input lead, a scan output lead, and a scan control input lead; and G. a gate having a first input connected to the test enable input lead, a second input connected to the output of the input buffer, and an output connected to core input lead.