Patent ID: 8536918

Claim:
A flip-flop circuit comprising: a master latch that selectively receives a data signal or a scan data signal; and a slave latch that receives an output signal of the master latch, wherein one of the master latch and the slave latch is a high-level latch, and another one of the master latch and the slave latch is a low-level latch, the high-level latch being a circuit that captures a signal in a high level of a clock signal and holds data of the signal in a low level, the low-level latch being a circuit that captures a signal in a low level of a clock signal and holds data of the signal in a high level, wherein in a scan shift operation, the master latch captures the scan data signal in response to a first clock signal and the slave latch captures the output data signal in response to a second clock signal different from the first clock signal, wherein in another operation, the master latch captures the data signal in response to a normal clock signal and the slave latch captures the output data signal in response to the normal clock signal, and wherein the second clock signal is in a low level when the first clock signal is in a low level, and the first clock signal is in a high level when the second clock signal is in a high level.