Patent ID: 8286041

Claim:
A semiconductor integrated circuit, comprising: a scan chain which comprises: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein said first flip-flops and said second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register; a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of said first flip-flops and read from a memory circuit in a restoring operation in a normal mode to said series connection; and a second selecting circuit provided between one of said second flip-flops and one of said second flip-flops subsequent to said one second flip-flop in said series connection and configured to select an output of said one second flip-flop in the scan path test mode and an output of one of said first flip-flops which is previous to said one second flip-flop or a series connection of said second flip-flops including said one second flip-flop; and a backup control circuit configured to control said scan chain in a saving operation in the normal mode such that the internal state data is stored in the memory circuit without passing through said second flip-flops, in the restoring operation in the normal mode such that the internal state data from said first selecting circuit is set in said first flip-flops without passing through said second flip-flops, and in the scan path test mode such that the test data is shifted in the series connection.