Patent ID: 7185039

Claim:
A modular exponentiation processor comprising: a controller for receiving a reset signal and a clock signal and for generating write enable signals and a selection schedule signal; a “C′” register for receiving “C′” input data; a “B′” register for receiving “B′” input data; an “S” register for receiving “S” intermediate data; a multiplexer for receiving “D” constant data, for selecting three of the “C′” register, the “B′” register, the “S” register, and the “D” constant data, and for generating as output the selected three of the “C′” register, the “B′” register, the “S” register, and the “D” constant data as “P” data, “Q” data, and “R” data respectively in response to the selection schedule signal; and a sub-multiplier for receiving the “P” data, the “Q” data, and the “R” data and for generating a sum of the “P” data plus a product of the “Q” data times the “R” data.