Patent ID: 8760935

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a block including m (m being an integer equal to or greater than 2) cell units sharing l (l being an integer equal to or greater than 2) word lines; a block dividing unit configured to divide the block into p (p being an integer equal to or greater than 2) by grouping the l word lines into p groups; an erasing unit configured to have an erasing operation performed on each of divisional blocks formed by the dividing performed by the block dividing unit; and an erasing verifying unit configured to have an erasing verifying operation performed on each of the divisional blocks in the block subjected to the erasing operation by the erasing unit, wherein the block comprises: two select gate lines, a plurality of first select transistors connected in common to one of the two select gate lines, and a plurality of second select transistors connected in common to the other of the two select gate lines.