Patent ID: 8351557

Claim:
A clock detecting circuit, suitable for detecting whether a clock source supplies a predetermined clock signal normally, comprising: a plurality of first transmission elements, wherein each of the plurality of first transmission elements is coupled to a last first transmission element for receiving output data thereof, a received data is transmitted to an input terminal of a next first transmission element according to a sample clock signal, an input terminal of the first one of the plurality of first transmission elements is coupled to the clock source for receiving the predetermined clock signal, and a frequency of the predetermined clock signal is lower than a frequency of the sample clock signal; a plurality of first exclusive OR gates, wherein a first input terminal and a second input terminal of a kth first exclusive OR gate are respectively coupled to output terminals of a kth first transmission element and a (k+1)th first transmission element, k being an integer larger than 0 and smaller than a total number of the plurality of first transmission elements; and a first AND gate, receiving outputs from the plurality of first exclusive OR gates.