Patent ID: 8011090

Claim:
A method of forming and planarizing adjacent regions of an integrated circuit, the method comprising: providing a first region of an integrated circuit and a second region of an integrated circuit, the second region having an initial height; forming an array of features in the first region, the array having an edge, the edge comprising a boundary between the first region and the second region, forming the array comprising: forming a pattern of mandrel lines over a substrate; blanket depositing spacer material over and between the mandrel lines; removing the portion of the spacer material that overlies the mandrel lines to form spacers on either side of each mandrel line; and removing the mandrel lines while allowing the spacers to remain and form the array of features in the first region, the array of features having a feature height that is higher than the initial height of the second region; blanket depositing a filler material on and between the features in the first region and on the second region; blanket depositing a protective material on the filler material in both the first region and the second region; and performing a two-step etch comprising: in a first step, removing the protective material until the portion of the protective material that overlies the first region is completely removed and the portion of the protective material that overlies the second region is only partially removed; and in a second step, removing the filler material to reduce the height of the first region down to a height of the portion of the protective material in the second region.