Patent ID: 7037841

Claim:
A method for fabricating a semiconductor device having a dual damascene interconnecting line structure, comprising the steps of: providing a substrate having a dielectric layer thereon; forming a first photoresist layer having a via contact hole pattern on the dielectric layer; forming a sacrificial layer on the first photoresist layer and filling up the via contact hole pattern; forming a second photoresist layer having an interconnect trench pattern on the sacrificial layer, thereby exposing the sacrificial layer beneath the interconnect trench pattern; transferring the interconnect trench pattern to the sacrificial layer using the second photoresist layer as a mask; and etching the first photoresist layer and the dielectric layer using the second photoresist layer as a mask, thereby transferring the interconnect trench pattern to the dielectric layer and forming an interconnect trench, and continuously etching the dielectric layer along the via contact hole pattern to form a via contact hole in the dielectric layer.