Patent ID: 7856026

Claim:
A packet switch module, comprising: a plurality of input ports operable to receive a plurality of packets from a first component module; a plurality of output ports operable to transmit the plurality of packets to a second component module; and a switch matrix for directing the plurality of packets between the plurality of input ports and the plurality of output ports, said switch matrix comprises a Central Data Buffer with memory blocks operable to store temporarily the plurality of packets after their receipt by the plurality of input ports, wherein the memory blocks are managed in an addressing scheme, wherein free memory blocks are made available to any input port requiring packet buffering; and wherein said switch matrix further comprises a virtual output queue manager configured to maintain a plurality of virtual channels for at least one output port by maintaining a feature including a list of packets from the multiple packets designated for a virtual channel on the at least one output port, a count of packets stored within the Central Data Buffer, or a count of available packet space within the Central Data Buffer for the at least one output port.