Patent ID: 7199009

Claim:
A method for fabricating a power metal oxide semiconductor field effect transistor (MOSFET) comprises: forming an epitaxial layer, a gate dielectric layer and a gate layer over the substrate sequentially; patterning the gate dielectric layer and the gate layer to form a gate structure and a stacked mask structure, and a surface of a portion of the epitaxial layer is exposed between the gate structure and the stacked mask structure; forming a well region in the epitaxial layer and under the stacked mask structure and partially under the gate structure; forming a source region inside the well region and between the gate structure and the stacked mask structure using the gate structure and the stacked mask structure as masks; forming a patterned dielectric layer to cover the gate structure and the source region, while the patterned dielectric layer exposes an upper surface of the stacked mask structure; removing the stacked mask structure to form a contact opening exposing a surface of the well region; and forming a body region inside the well region and under the contact opening by using the patterned dielectric layer as a mask.