Patent ID: 8213155

Claim:
A multilayer chip capacitor comprising: a capacitor body having a plurality of dielectric layers laminated therein, the capacitor body comprising first and second capacitor units arranged therein; and first to fourth outer electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises first and second inner electrodes opposing each other while interposing a corresponding one of the dielectric layers, the first and second inner electrodes connected to the first and second outer electrodes and not connected to third and fourth outer electrodes, respectively to have polarity different from each other, and the first capacitor unit comprises a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit comprises the third and fourth inner electrodes opposing each other while interposing another corresponding one of the dielectric layers, the third and fourth inner electrodes connected to the third and fourth outer electrodes and not connected to the first and second outer electrodes, respectively to have polarity identical to the first and second inner electrodes, and the second capacitor unit comprises at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.