Patent ID: 8324932

Claim:
A static complementary transistor type logic gate circuit comprising: a first input terminal for receiving a first input signal; a second input terminal for receiving a second input signal; a third input terminal for receiving a third input signal; an output terminal; a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the first, second, and third input signals; a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the first, second, and third input signals; and a precharge device configured to selectively charge an intermediate node to a far-side supply voltage when the intermediate node is disconnected from a near-side supply voltage and disconnected from the output terminal.