Patent ID: 7257791

Claim:
A process of inserting buffers into an integrated circuit chip design having an initial circuit performance based on initial circuit parameters, comprising: a) providing a table having dimensions including height, input capacitance, output capacitance and ramptime and which identifies buffer types based on a plurality of circuit parameters associated with the dimensions; b) defining a routing tree comprising root, internal and leaf vertices arranged so that each internal and leaf vertex has one parent vertex and each root and internal vertex has at least one child vertex, the parent and child vertices defining respective tree segments, and each internal vertex has an associated set of initial circuit parameters of the chip; c) for each internal vertex, comparing the initial circuit parameters associated with the internal vertex to the circuit parameters associated with buffers identified in the table to identify whether to insert a buffer identified in the table to the respective internal vertex; and d) inserting an optimal buffer identified in the table to a segment associated with a selected internal vertex based at least in part on the comparison results.