Patent ID: 7009881

Claim:
A semiconductor memory device comprising a memory cell unit with a plurality of electrically rewritable memory cells connected in series, two ends thereof being coupled to a data transfer line and a reference potential line via select transistors, respectively, wherein said device has a data read mode defined as to detect a read current or a change thereof flowing between said data transfer line and said reference potential line, and judge data of a selected memory cell in said memory cell unit under the condition of: applying a read voltage to said selected memory cell, the read voltage being set to turn on or off said selected memory cell in accordance with data thereof; applying a pass voltage to remaining unselected memory cells, the pass voltage being set to turn on the remaining unselected memory cells without regard to data thereof; and making said select transistors on, and wherein in said data read mode, the more unselected memory cell or cells located on the source side of said selected memory cell, the higher the pass voltage applied to the unselected memory cell or cells located on the source side of said selected memory cell.