Patent ID: RE45227

Claim:
A two-channel, time-interleaved analog to digital converter (ADC) system comprising: a clock signal generator, for generating a clock signal at a frequency f and a period T; a first ADC coupled to the clock signal generator, the first ADC sampling and holding an input signal on odd cycles of the clock signal to provide a first digital signal; a second ADC coupled to the clock signal generator, the second ADC sampling and holding the input signal on even cycles of the clock signal to provide a second digital signal; an error measurement block coupled to receive the first and second digital signals, the error measurement block producing an error signal based on the first and second digital signals; an adaptive processor coupled to receive the error signal, the adaptive processor estimating at least one of offset, gain, and sample-time errors between the first and second ADCs based on the error signal, the adaptive processor feeding back a correction signal corresponding to the estimated error to correct one of offset, gain, and sample-time error of at least one of the first and second ADCs; and a multiplexer, for interleaving the first and second digital signals to form a digital representation of the input signal.