Patent ID: 8839063

Claim:
A method of testing devices under test (DUTs), at least one DUT comprising N number of scan channels associated with M number of Input/Output (I/O) ports, the method comprising: generating at least one control signal associated with a test pattern structure, the test pattern structure configured to be implemented to scan test the at least one DUT; selecting M1 number of ports from among the M number of I/O ports so as to receive a scan input corresponding to the test pattern structure based on the at least one control signal; selecting M2 number of ports from among the M number of I/O ports so as to provide a scan output corresponding to the test pattern structure based on the at least one control signal, each of M1 and M2 being a number selected from among a range of numbers between 0 and M, and a sum of M1 and M2 being less than or equal to M; and performing a scan testing of the at least one DUT based on a provision of the scan input to the M1 number of ports and a receipt of the scan output from the M2 number of ports.