Patent ID: 8350309

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first select gate transistor and a second select gate transistor, the plurality of memory cells being connected in series, the plurality of memory cells being connected between a source of the first select gate transistor and a drain of the second select gate transistor; a first source line located along a first direction in the memory cell array, the first source line being connected to a source of the second select gate transistor, the first source line being consisted of a first conductive layer; a word line located along the first direction, a gate electrode of one of the plurality of memory cells being connected to the word line, the word line being consisted of a second conductive layer; a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line; and a bit line located along a second direction perpendicular to the first direction, the bit line being connected to a drain of the first select gate transistor, the bit line being consisted of a third conductive layer, wherein at least a portion of the first conductive layer is located above the second conductive layer, the first conductive layer is located below the third conductive layer, the second conductive layer is located above at least a portion of the gate electrode of the first select gate transistor, and the second conductive layer is located above at least a portion of the gate electrode of the second select gate transistor.