Patent ID: 8713085

Claim:
A method for adding a first operand and a second operand, comprising: obtaining the first operand in a signed-magnitude representation using a number of bits; converting the first operand from the signed-magnitude representation to a first one's complement representation by inverting magnitude bits of the signed-magnitude representation of the first operand in response to a determination that the first operand is a negative operand; converting the second operand to a second one's complement representation; adding, in a first addition operation, the first one's complement representation to the second one's complement representation to generate a first partial sum, wherein the first addition operation is performed using a plurality of full adders followed by a half adder, the half adder adding least significant bits from each of the first operand and the second operand; removing an overflow bit of the first partial sum to generate a second partial sum; adding, in a second addition operation performed using a plurality of half adders, the overflow bit to the second partial sum at a least significant position of the second partial sum to generate a sum in a one's complement representation, wherein a total number of carry operations performed in the first addition operation and the second addition operation is less than or equal to one plus the number of bits in the first one's complement representation; and converting the sum from its one's complement representation to a signed-magnitude representation by inverting magnitude bits of the sum in response to a determination that the one's complement representation of the sum is negative valued.