Patent ID: 7321498

Claim:
A timing circuit for a synchronous rectifier having an input MOSFET switch coupled to primary windings of an isolation transformer, an output MOSFET switch coupled to secondary windings of the isolation transformer, and a complementary output MOSFET switch coupled to an output terminal, the timing circuit comprising: a first timing output signal circuit responsive to a pulse width modulated signal at a first input terminal and providing first and second timing output signals that switch low at time t 1 and high at time t 4 to control the input MOSFET switch and output MOSFET switch, respectively, wherein the first timing output signal circuit comprises: a first resistor coupled between the input terminal and a first node; a first diode having a cathode connected to the input terminal and an anode connected to the first node; a first capacitor coupled between the first node and a first voltage reference; and a first comparator having a positive input connected to the first node, a negative input connected to a second voltage reference, and an output providing the first and second timing output signals; and a second timing output signal circuit responsive to the pulse width modulated signal and providing a third timing output signal that switches high at time t 2 and low at time t 3 to control the complementary output MOSFET switch.