Patent ID: 8397197

Claim:
A computer readable non-transient storage medium storing instructions for causing a processor to estimate time delays during a floor planning process by performing the operations of: accepting an Integrated Circuit (IC) floor-plan that comprises floor space allocation for a first module and a second module; accepting a command defining a maximum delay value; estimating a first delay value between a first circuit element signal output interface that is disposed in the first module and a first module output port based on estimated timing factors derived from the IC floor-plan; estimating a second delay value between a second circuit element signal input interface that is disposed in the second module and a second module input port based on estimated timing factors derived from the IC floor-plan; estimating a third delay value between the first module output port and the second module input port based on estimated timing factors derived from the IC floor-plan; summing the first, second, and third delay values to create a time budget estimate; adjusting the IC floor plan or the maximum delay value to reduce time delays if the time budget estimate is greater than the maximum delay value.