Patent ID: 8138543

Claim:
A circuit structure, comprising: least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device, wherein said FinFET device comprises sidewalls; a trench isolation penetrating through said SOI and abutting said insulator, wherein said trench isolation surrounds said planar NFET device and said planar PFET device; wherein each of said three different kinds of devices comprise a high-k gate dielectric layer containing an identical high-k material for all of said three different kinds of devices, and wherein each of said three different kinds of devices comprise a mid-gap gate metal layer containing an identical mid-gap metal for all of said three different kinds of devices, wherein for said FinFET device said high-k gate dielectric layer overlays said sidewalls and said mid-gap gate metal layer is in direct contact with said high-k gate dielectric layer; individual workfunction modifying layers inbetween said high-k gate dielectric layer and said mid-gap gate metal layer, respectively for said planar NFET device and for said planar PFET device; and wherein said circuit structure is characterized as being a combination of a planar CMOS circuit and a FinFET circuit in SOI, wherein said planar CMOS circuit comprises said planar NFET device and said planar PFET device, and wherein each of said three different kinds of devices have an individually optimized threshold value.