Patent ID: 7475295

Claim:
A watchdog component affiliated with a host system that has a processor and a timer mechanism generating periodic clock outputs, the watchdog component comprising: an N-bit counter that is capable of counting up to a maximum value and counting down to a minimum value, said N-bit counter having a bit that is a most significant bit (MSB); a first output signal bus transmitting a first output signal for triggering a reset of a host system; a second output signal bus transmitting a second output signal for signaling a value of the MSB to the host system; a first input signal bus transmitting a first input signal that indicates whether the counter is to count up or down, said first input signal representing the received input and being generated based on the value of the MSB; a microprocessor with processing logic having code executing thereon for performing the function of directing a count of the watchdog component away from a closest end point of the counter values towards the opposite end point of counter values, wherein a first end point is a maximum counter value and a second, opposing end point is a minimum counter value, whereby generation of false keep-alive pulses while the system is in a hung state are substantially eliminated, said code executing on the processing logic to provide: logic for checking a state of the MSB of the counter; logic for automatically incrementing and decrementing the value of the counter based on a periodic signal received from a periodic source; logic for periodically determining a direction in which the counter values change (up or down) based on the value of the MSB, wherein: when the MSB is a first value indicating the counter is closest to a zero value, said processing logic for determining selects an upwards direction for changing/increasing the counter values; and when the MSB is a second value indicating the counter is closest to a maximum value, said processing logic for determining selects a downwards direction for changing/decreasing the counter values; logic for changing the direction of the counting by the counter from increasing to decreasing and from decreasing to increasing the value of the counter based on a received input triggered by a current value of the most significant bit (MSB) of the counter; and logic for triggering a watchdog event if the counter counts down through 0 or up through a maximum value (2^N); logic for initializing the counter with an initial midpoint value during one of a power-on state and a reset state, wherein the initial midpoint value is not the maximum value or the minimum value and use of the initial midpoint value enables the counter to initially count up or count down, depending on an initial setting of the component, until a first checking of the MSB bit is completed to determine a next direction of the counter.