Patent ID: 7279371

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line on a substrate; depositing a first insulating layer, a semiconductor layer, and a conductive layer in sequence on the gate line; photo-etching the conductive layer and the semiconductor layer simultaneously to form a semiconductor pattern and a conductive pattern; depositing a second insulating layer on the first insulating layer and the conductive pattern; photo-etching the second insulating layer to expose first and second portions of the conductive layer; forming a pixel electrode of light transmitting material on the first portion of the conductive layer and forming a redundant source pattern and a redundant drain portion covering a portion of the second portions of the conductive pattern; removing the second portion of the conductive layer not covered with the redundant source pattern and the redundant drain pattern to form a source electrode and a drain electrode and to expose a portion of the semiconductor layer; and forming a light blocking member on the exposed portion of the semiconductor layer, the light blocking member having an opening exposing the pixel electrode.