Patent ID: 8901659

Claim:
A non-planar semiconductor device comprising: at least one tapered semiconductor nanowire having a curved top surface and a curved bottom surface and located atop an insulator layer of a semiconductor-on-insulator substrate, wherein an end segment of said at least one tapered semiconductor nanowire is attached to a first semiconductor-on-insulator pad region and another end segment of said at least one tapered semiconductor nanowire is attached to a second semiconductor-on-insulator pad region, said first and second semiconductor-on-insulator pad regions are both located atop said insulator layer; a gate located on a portion of said at least one tapered semiconductor nanowire; a polysilicon line located on a surface of said gate and having a bottommost surface in contact with a surface of said insulator layer; a hard mask line located on an uppermost surface of said polysilicon line; a source region located on a first side of the gate; and a drain region located on a second side of the gate which is opposite said first side of the gate, wherein said at least one tapered semiconductor nanowire comprises a first semiconductor nanowire portion having a first width located on the first side of the gate and a second semiconductor nanowire portion having a second width that is located on the second side of the gate, wherein said second width is greater than the first width.