Patent ID: 7838352

Claim:
A method for fabricating a thin film transistor comprising: forming an amorphous silicon layer on a substrate; forming a semiconductor layer pattern having a channel layer in which no seed exists and no grain boundary exists by crystallizing and patterning the amorphous silicon layer, the forming a semiconductor layer pattern comprising; forming a first capping layer on the amorphous silicon layer; patterning the first capping layer so that a seed is formed in a source region or a drain region of the semiconductor layer pattern; forming a second capping layer on a top surface of the patterned first capping layer; forming a metal catalyst layer on the second capping layer; diffusing a metal catalyst of the metal catalyst layer through the second capping layer into the amorphous silicon layer; and forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer using the diffused metal catalyst; forming a gate insulating film on the semiconductor layer pattern; and forming a gate electrode on the gate insulating film.