Patent ID: 7345504

Claim:
An impedance adjustable circuit having an on-chip adjustable termination resistor for use in an integrated circuit chip, the integrated circuit chip including a bandgap voltage reference module, the adjustable termination resistor comprising: a reference resistor coupled to the bandgap voltage reference module, wherein a reference voltage is determined according to the reference resistor and an internal current outputted from the bandgap voltage reference module; a current mirror circuit for generating a mirror current according to an external current outputted from the bandgap voltage reference module as a reference current and a factor; a calibration transistor-resistor array electrically connected to the current mirror circuit, wherein the mirror current flows through the calibration transistor-resistor array to result in a comparing voltage across the calibration transistor-resistor array; a digital code generator electrically connected to the calibration transistor-resistor array for generating and outputting a digital code to the calibration transistor-resistor array, wherein the resistance of the calibration transistor-resistor array is determined according to the digital code; a comparator having two input terminals electrically connected to the reference resistance and the calibration transistor-resistor array, wherein the voltage level outputted from the comparator is changed from a first state to a second state when the digital code generator up counts to a target digital code such that the comparing voltage is just greater than the reference voltage; a decision and latch circuit electrically connected to the comparator and the digital code generator for recording the target digital code therein; and a termination resistor electrically connected to the decision and latch circuit and including a plurality of transistor-resistor arrays connected in parallel, wherein the resistance of the termination resistor is adjustable according to the target digital code outputted from the decision and latch circuit.