Patent ID: 7910432

Claim:
A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, each of the memory strings comprising: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge trap layer formed to sandwich an insulation layer with the first columnar semiconductor layer and accumulating charges; a plurality of first conductive layers formed to sandwich an insulation layer with the charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction; a protection insulation layer continuously covering over the plurality of first conductive layers and the second conductive layers; and an interlayer insulation layer formed on the protection insulation layer, respective ends of the plurality of first conductive layers in the first direction being formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers being formed in an area immediately above the top layer of the first conductive layers, and an etching rate of the protection insulation layer being different from an etching rate of the interlayer insulation layer.