Patent ID: 7317630

Claim:
A nonvolatile memory apparatus comprising: a controller circuit fabricated on a first integrated circuit chip and including a plurality of charge pump circuits, a system interface logic circuit, and a memory control logic circuit; a memory circuit fabricated on a second integrated circuit chip and including a memory array, a column decoder, and a row decoder; and a memory-controller interface including a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit, the memory-controller interface being configured to allow electrical coupling through a plurality of pins corresponding to the first and second pluralities of die bond pads of the controller circuit and the memory circuit, the first and second die bond pads including a command mode pin and multiplexed address/data-input/output (ADIO) pins, the controller circuit configured to determine data direction of at least the ADIO pins depending on a mode of the memory circuit set in response to a command sent on the ADIO pins while the command mode pin is asserted.