Patent ID: 8638599

Claim:
A semiconductor storage device comprising: a memory array including a plurality of memory cells arranged in a matrix; a plurality of read-word-lines and a plurality of write-word-lines, each of which is coupled to the memory cells belonging to a column in the memory array; a plurality of read-bit-lines, each of which is precharged to a predetermined voltage and coupled to the memory cells belonging to a row in the memory array; a plurality of first write-bit-lines and a plurality of second write-bit-lines, each of which is coupled to the memory cells belonging to a row in the memory array; a first driver configured to output a one-shot pulse having a predetermined width to the read-word-line when reading data; a plurality of read circuits, each configured to read data stored in the memory cell according to a voltage of the read-bit-line; a second driver configured to output a write signal having a predetermined voltage to the write-word-line when writing data; and a write circuit which supplies a signal according to values of data to be written in the first write-bit-line and the second write-bit-line, wherein the memory cell has a first mos transistor with one of current electrodes being coupled to the read-bit-line; a tunnel magnetoresistive element coupled between a control electrode of the first mos transistor and the read-word-line; and a capacitive element coupled to the tunnel magnetoresistive element and forming an RC circuit together with the tunnel magnetoresistive element.