Patent ID: 7339222

Claim:
A method for fabricating a memory array, said method comprising steps of: forming a plurality of trenches in a substrate, said plurality of trenches determining a plurality of wordline regions in said substrate, each of said plurality of wordline regions being situated between two adjacent trenches in said plurality of trenches, said each of said plurality of wordline regions having a wordline region width; forming a plurality of bitlines in said substrate, said plurality of bitlines being situated in a direction perpendicular to said plurality of trenches; forming a dielectric region in each of said plurality of trenches; forming a dielectric stack over said plurality of bitlines, said plurality of wordline regions, and said plurality of trenches; forming a plurality of wordlines, each of said plurality of wordlines being situated over one of said plurality of wordline regions; wherein said wordline region width determines an active wordline width of said each of said plurality of wordlines.