Patent ID: 8830156

Claim:
A gate driving circuit, comprising: a plurality of stages configured to output gate signals in response to first and second input signals and in response to first through third clock signals input to the plurality of stages, wherein each of the plurality of stages includes: an input unit configured to determine a level of voltage to be input to a first node based on the first input signal as a carry signal input from a previous stage and the second input signal as a carry signal input from a next stage; a first driving unit configured to output carry signals to the next stage, the carry signals being based on the first clock signal that is input according to the level of the voltage input to the first node and a first gate-off voltage that is input in response to the second clock signal; a second driving unit configured to output the gate signals based on the third clock signal that is input according to the level of the voltage input to the first node and a second gate-off voltage that is input in response to the second clock signal; and a leakage blocking unit configured to block leakage current of a transistor by maintaining a level of voltage input to a third node connected to the first node via at least one transistor.