Patent ID: 8766332

Claim:
A semiconductor die comprising: a substrate device level having a substrate pitch, wherein the substrate pitch comprises a substrate critical dimension and is a sum of a line feature and space feature formed at the substrate device level; and a first memory level above a substrate having a first memory pitch, wherein the first memory pitch comprises a first memory critical dimension and is a sum of a line feature and space feature formed at the first memory level and wherein the first memory pitch is smaller than the substrate pitch, wherein the first memory level does not include a device at least a portion of which is formed by part of the substrate or located in or below a surface of the substrate, and wherein the first memory level comprises: a first area comprising portions of a first plurality of memory cells, the first plurality of memory cells having the first memory pitch; and a second area having a fan-out pitch, wherein said fan-out pitch is larger than the first memory pitch.