Patent ID: 7110283

Claim:
A semiconductor memory device comprising: a first bit line for transferring data; a second bit line having a relationship of complementary potential levels with the first bit line; a storage section in which a drain electrode of a first transistor and a gate electrode of a second transistor are connected to each other to form a first node, and a drain electrode of the second transistor and a gate electrode of the first transistor are connected to each other to form a second node; a p channel type third transistor that is coupled between the first node and the first bit line and is controlled by a first signal on a word line for providing electrical connection of the first node and the first bit line; a p channel type fourth transistor that is coupled between the second node and the second bit line and is controlled by the first signal on the word line for providing electrical connection of the second node and the second bit line; and a first voltage, which is set on the condition that a difference between a source potential applied to each of the first and second transistors and a potential of a select level of the first signal on the word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors from a power supply circuit, wherein the third and fourth transistors are configured as a vertical structure, the third transistor is laminated over the first transistor, and the fourth transistor is laminated over the second transistor.