Patent ID: 8667373

Claim:
A frame boundary detection system for a data stream received by an Ethernet Forward Error Correction (FEC) layer, comprising: a shifter for intercepting data of one frame plus A bits from the data stream, wherein the A bits is less than a length of one frame, and A is a positive integer; two descramblers of which a first descrambler performs a descrambling operation on the data of one frame starting from the first bit of the data of one frame plus A bits, while a second descrambler performs a descrambling operation on the data of one frame starting from the (A+1) th bit of the data of one frame plus A bits; a syndrome generator for performing a first FEC check on the data descrambled by the first descrambler; and an error trapper including a big-little endian mode controller for controlling a big-little endian conversion of the error trapper, wherein the error trapper is used to perform a second FEC check on the data descrambled by the second descrambler if the error trapper operates in a big endian mode, wherein the first bit of the data of one frame plus A bits is a start position of the frame if the first FEC check is correct, and the (A+1) th bit of the data of one frame plus A bits is the start position of the frame if the second FEC check is correct.