Patent ID: 7634593

Claim:
A system for DMA transfer, comprising: a DMA controller; a bus connected to said DMA controller; a bus interface connected to said bus; and a plurality of registers coupled to said bus via said bus interface, wherein said bus interface is configured to allocate said plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow said DMA controller to access said plurality of registers through the consecutive addresses, and wherein said bus interface is configured to output to said bus a single data chunk into which respective data items of the registers read from the consecutive addresses are consolidated, said single data chunk having a first data width equal to that of said bus, and at least one of the respective data items having a second data width narrower than the first data width, and wherein the bus interface includes: a decoder configured to output a first decode signal in response to a first address supplied via the bus and a second decode signal in response to a second address supplied via the bus; and an OR gate configured to perform an OR operation between the first decode signal and the second decode signal to supply a signal indicative of a result of the OR operation to one of the registers, thereby allocating both the first address and the second address to said one of the registers.