Patent ID: 7184293

Claim:
A crosspoint type ferroelectric memory comprising: a plurality of memory cell arrays which are stacked with interlayer insulating layers therebetween; each memory cell array including: lower electrodes formed in stripes; upper electrodes formed in stripes in a direction that crosses the lower electrodes; ferroelectric capacitors respectively including a part of one of the lower electrodes, a part of one of the upper electrodes, and a ferroelectric part disposed at least at a crossing part of the one of the lower electrodes and the one of the upper electrodes; and an embedded insulating layer formed between the ferroelectric capacitors, wherein each interlayer insulating layer includes a conductive layer between a first insulating layer and a second insulating layer, and wherein the first insulating layer and the second insulating layer of each interlayer insulating layer are directly connected to one another in at least one part of a formation region of the interlayer insulating layer.