Patent ID: 7451424

Claim:
A processor-implemented method for determining a plurality of programmable connections through a switchbox module of a programmable logic device (PLD) design, the method comprising: inputting a netlist that describes the PLD design; inputting an identification of the switchbox module, the switchbox module including at least one instance of at least one multiplexer module; inputting characterization data for each multiplexer module of the switchbox module, the characterization data specifying a plurality of input pins and at least one output pin of the multiplexer module, wherein the multiplexer module programmably connects each output pin to one of the input pins; determining a plurality of pins of the switchbox module through which the programmable connections are provided via the at least one instance of the at least one multiplexer module of the switchbox module; determining each pair of the plurality of pins of the switchbox module that are functionally connected via at least one instance of the at least one multiplexer module, wherein the pair of the pins specifies a programmable connection, and the pair of pins are functionally connected if the pair of pins have equal respective logical values during operation of the PLD design; and outputting a respective specification of each of the programmable connections wherein the determining of the plurality of pins of the switchbox module through which the programmable connections are provided includes, searching the PLD netlist for reachable pins that are pins of the switchbox beginning at the input and output pins of each instance of the at least one multiplexer module according to the characterization data.