Patent ID: 7469352

Claim:
A method for reducing power consumption of a computer system, the computer system comprising a first memory module having a plurality of address pins, a second memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving corresponding address pins of the first and second memory modules, the method comprising: obtaining a first and a second number of required address pins respectively according to capacities of the first and the second memory modules, wherein the first required address-pin number comprises numbers of pins required for addressing first bank address and first RAS/CAS address, and the second required address-pin number comprises numbers of pins required for addressing second bank address and second RAS/CAS address; and setting the maximum of the first and second required address-pin numbers to a required address-pin maximum, if the required address-pin maximum is smaller than the number of driving units of the chipset, the chipset controls at least one driving unit to stop driving so that the number of driving units driven by the chipset is equal to the required address-pin maximum.