Patent ID: 8072252

Claim:
A flip-flop comprising: a plurality of input stages, wherein each of the input stages is coupled to receive a clock signal and two or more logically independent input signals, wherein each of the plurality of input stages is configured to perform a corresponding input logic function and to store a result of the corresponding input logic function, wherein each of the plurality of input stages includes first and second precharge circuits configured to precharge a first node and a second node, respectively, during a first phase of a clock signal, and wherein each of plurality of input stages is configured to discharge one of the first or second nodes during a second phase of the clock signal responsive to performing the corresponding input logic function; and an output stage, wherein the output stage is coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages and configured to, during the second phase of the clock cycle, logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function.