Patent ID: 7998827

Claim:
A method of manufacturing a semiconductor device, comprising: forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a first dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area; and aligning a third layer provided above the structure by using the second alignment mark, wherein the first dummy pattern provided above the first alignment-mark arrangement area is provided in the second layer and is formed in the same step as the second alignment mark, and wherein a second dummy pattern is provided in a first part of the third layer, and substantially no dummy pattern is provided in a second part of the third layer, the first part being located above the first alignment-mark arrangement area and the second part being located above the second alignment-mark arrangement area.