Patent ID: 7606960

Claim:
An apparatus comprising: a variable speed bus, the variable speed bus initialized with a first clock frequency; a first unit coupled to the variable speed bus, the first unit having a first rate of requests to access the variable speed bus; a second unit coupled to the variable speed bus, the second unit having a second rate of requests to access the variable speed bus; and an arbitration and bus clock control unit to monitor the first access request rate from the first unit and the second access request from the second unit, and to determine a second clock frequency for the variable speed bus based on the first access rate or the second access request rate, the arbitration and bus clock control unit being modified to track a rate of request of the first and second units to access the variable speed bus, the arbitration and bus clock control unit being further modified to recognize when there are no incoming requests and a percentage of arbitration slots that are being used, and to instruct a clock throttling logic to adjust a clock frequency associated with the variable speed bus according to bandwidth requirements of the first and second units based on the rate of request, wherein the adjusting of the clock frequency includes lowering the clock frequency to a lowest level necessary in accordance with the recognition of no incoming requests and the percentage of the arbitration slots being used and further in accordance with a historical average utilization including statistical data relating to sustained bandwidth needs such that the clock frequency of the variable speed bus is automatically adjusted depending on one or more of the rate of request, the percentage of arbitration slots being used, and the historical average utilization relating to the first and second units.