Patent ID: 7615437

Claim:
A method of manufacturing a non-volatile memory device, comprising: forming a multi-layer structure on a substrate by sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on the substrate; forming a first opening through the multi-layer structure to expose a first region of the substrate, the first opening being formed by partially etching the second insulation layer, the charge storage layer, and the first insulation layer; forming second and third openings through the second insulation layer to form a second insulation layer pattern, the second and the third openings being formed in first and second sections of the substrate, respectively, and exposing portions of the charge storage layer, the first section of the substrate including the first region of the substrate; forming a conductive layer on the second insulation layer pattern; forming a photoresist pattern structure on the conductive layer; and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching the conductive layer, the second insulation layer pattern, the charge storage layer, and the first insulation layer using the photoresist pattern structure as an etching mask, wherein the common source line is formed in the first region of the substrate, the ground selection line is formed in the first section and adjacent to the common source line, the string selection line is formed in the second section, and the gate structures are in a central region of the substrate between the first and the second sections.