Patent ID: 7655546

Claim:
A method of making an integrated circuit including a D-mode FET and an E-mode FET, the method comprising: providing a multi-layer structure comprising a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers, including a channel layer overlaid by a barrier layer overlaid by an etch stop layer, wherein the channel, etch stop and barrier layers are common to the D-mode and the E-mode FETs; forming respective source and drain contacts for the D-mode FET and E-mode FET on one of the epitaxial layers of the multi-layer structure; forming a gate recess in the multi-layer structure for the D-mode FET, and a gate recess in the multi-layer structure for the E-mode FET, wherein a surface of the barrier layer is exposed at a bottom of both the D-mode and E-mode gate recesses; and depositing a plurality of metal layers onto the exposed surface of the barrier layer within the D-mode and E-mode gate recesses, thereby forming a D-mode gate contact and an E-mode gate contact on the barrier layer, wherein the E-mode gate contact forms a Schottky contact with the barrier layer, wherein a first metal layer deposited in contact with the barrier layer in the D-mode gate recess is different than a first metal layer deposited in contact with the barrier layer in the E-mode gate recess.