Patent ID: 8487290

Claim:
An RRAM structure consisting of: a bottom electrode; a top electrode positioned above the bottom electrode, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO); and a resistive layer sandwiched between the bottom electrode and the top electrode, wherein the RRAM structure has a first V reset voltage of 3 to 4V corresponding to a first C reset current of 3 E-4 to 3 E-3A and a first V set voltage of 4 to 5V corresponding to a first C set current of 4 E-5 to 9 E-5A in the presence of ITO serving as the top electrode, and the RRAM structure has a second V reset voltage of 4 to 5V corresponding to a second C reset current of 3 E-4 to 5 E-4A and a second V set voltage of 5 to 6V corresponding to a second C set current of 3 E-5 to 5 E-5A in the presence of IZO serving as the top electrode.