Patent ID: 7064972

Claim:
A ferroelectric memory device comprising: a memory cell array including a matrix layout of memory cells each having a transistor with its gate connected to a word line and a ferroelectric capacitor having one end connected to a bit line and a remaining and connected to a plate line; a plate-line drive circuit for driving said plate line; a word-line drive circuit for driving said word line; and a sense amplifier connected to said bit line for detecting and amplifying data of said memory cell, wherein at least one of said plate-line drive circuit and said word-line drive circuit has a pullup circuit for potentially raising an output terminal of this at least one from a low level up to a high level and a pulldown circuit for letting said output terminal potentially drop from the high level down to the low level, and at least one of said pullup circuit and said pulldown circuit is arranged to be variable in drivability during driving.