Patent ID: 8484523

Claim:
A digital scan chain system having test scan comprising: a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output, wherein the test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry, a first of the plurality of flip-flop modules comprising: a first multiplexed master/slave flip-flop for multiplexing between the first data bit input and the test bit input, a clock input for receiving a first clock, and having an output for providing the first data bit output; a second multiplexed master/slave flip-flop for multiplexing between the second data bit input and the output of the first multiplexed master/slave flip-flop, a clock input for receiving the first clock, and having an output for providing the second data bit output; a latch having an input coupled to the output of the second multiplexed master/slave flip-flop, an output for providing the test bit output, and a clock input; and a logic gate having a first input for receiving the first clock signal, a second input for receiving a test enable signal, and an output coupled to the clock input of the latch for selectively clocking the latch only during a test mode, wherein the first clock is placed closer to the logic gate than to the clock input of each of the first and second multiplexed master/slave flip-flops so that the first clock transitions earlier at the logic gate than at the first multiplexed master/slave flip-flop.