Patent ID: 8386865

Claim:
An integrated circuit comprising: A. a test data in lead and a test data out lead; B. a first test access port including: i. a link update register having an input coupled to the test data in lead and an output coupled to the test data out lead, and ii. an augment instruction register having an input coupled to the test data in lead and an output coupled to the test data out lead; C. a second test access port including: i. a data register having an input coupled to the test data in lead and an output coupled to the test data out lead, ii. an instruction register having an input coupled to the test data in lead and having an output, iii. an augment instruction register having an input connected to the output of the instruction register and having an output coupled to the test data out lead, and iv. a boundary scan register having an input coupled to the test data in lead; and D. a third test access port including: i. a data register having an input coupled to the test data in lead and an output coupled to the test data out lead, ii. an instruction register having an input coupled to the test data in lead and having an output, and iii. an augment instruction register having an input connected to the output of the instruction register of the third test access port and having an output coupled to the test data out lead.