Patent ID: 8806129

Claim:
A mounted memory system, comprising: a first memory unit mounted on a bus; a first cache manager coupled to an input and an output of the first memory unit; a second memory unit mounted on the bus; a second cache manager coupled to an input and an output of the second memory unit, the first memory unit and the second memory unit being adapted to receive and send communications via the first cache manager and the second cache manager; a second set of sub-memory units and a second set of sub-processing elements coupled to the second cache manager, the second set of sub-memory units and the second set of sub-processing elements located on a lower hierarchical level than the second memory unit; and wherein the second cache manager is configured to receive a request for memory content from the first cache manager and direct the request for memory content to the input of the second memory unit to enable the second memory unit to function as a next-level higher cache to the first memory unit, including in the case that either of the following are non-operational: the second set of sub-memory units, and the second set of sub-processing elements.