Patent ID: 8576007

Claim:
An apparatus comprising: an amplifier that receives an input signal and that generates an output signal, wherein the amplifier includes: a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor receives a first portion of the input signal; and a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a second portion of the input signal; and a neutralization network having: a first neutralization capacitor that is coupled between the control electrode of the first transistor and the second passive electrode of the second transistor; and a second neutralization capacitor that is coupled between the control electrode of the second transistor and the second passive electrode of the first transistor, wherein the amplifier further comprises: a first output terminal that is adapted to provide a first portion of the output signal; a second output terminal that is adapted to provide a second portion of the output signal; a first bias network that is coupled to the first passive electrode of each of the first and second transistors; and a second bias network that is coupled to the second passive electrode of each of the first and second transistors, wherein the first and second transistors are MOS transistors, and wherein the first passive electrode, the second passive electrode, and the control electrode of each of the first and second transistors are the source, drain, and gate, respectively, wherein the first and second transistors further comprise first and second PMOS transistors, respectively, wherein the first bias network further comprises: a third PMOS transistor that is coupled to the source of the first PMOS transistor at its drain; and a fourth PMOS transistor that is coupled to the source of the second PMOS transistor at is drain and that is coupled to the gate of the third PMOS transistor at its gate.