Patent ID: 8472248

Claim:
A semiconductor memory comprising: a memory cell array which comprises memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds; a row control circuit which controls a row of the memory cell array; and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to a column of the memory cell array in accordance with a pointer corresponding to an external address signal, wherein the memory cell array and the column control circuit comprise column units including column groups and loop units including the column groups and set to extend across the column units, the column units are a control group set to the column control circuit, the column groups included in one loop unit are selected one by one from the column units belonging to the loop unit, the column control circuit sequentially activates column groups in a selected loop unit synchronously with a shift of the pointer across the column units, and the column control circuit switches a loop unit targeted for operation from the selected loop unit to a loop unit to be selected next after the column groups in the selected loop unit are sequentially activated, and the column control circuit sequentially activates column groups in the loop unit to be selected next synchronously with the shift of the pointer.