Patent ID: 8633738

Claim:
An output driver apparatus comprising: output driver circuitry coupled between a core-output node and an output pad; a D-flip-flop (DFF) array including a DFF array clock (CLK) input, a DFF array delay input and a DFF array output, the DFF array clock input being coupled to the output pad, and the DFF array output being coupled to the output driver circuitry, the DFF array being configured to output a code on the DFF array output in response to a difference between a signal on the DFF array clock input and each of a chain of delay reference signals on the DFF array delay input, the output driver circuitry being configured to adjust a driving strength in response to the code; and a delay line coupled between the core-output node and the DFF array delay input, the delay line configured to generate the chain of delay reference signals by applying a set of representative delays to a signal on the core-output node.