Patent ID: 7532527

Claim:
A semiconductor memory device comprising: a bank including a plurality of cell blocks; a first group of local input/output lines to transfer data stored on a first group of the cell blocks according to a first data output mode; a second group of local input/output lines to transfer data stored on a second group of the cell blocks according to the first data output mode and a second data output mode; a first precharge unit precharging the first group of the local input/output lines; a second precharge unit precharging the second group of the local input/output lines; a precharge signal generator to precharge the first and second groups of the cell blocks for the first data output mode and the second group of the cell blocks for the second data output mode, wherein the first data output mode is one of a 4-bit data operation mode and an 8-bit data operation mode and the second data output mode is a 16-bit data operation mode.