Patent ID: 8479131

Claim:
A computer-implemented method of calculating total resistance of a field effect transistor (FET) device, said method comprising: counting, by a computing device, a number (N) of contacts in each source region and drain region of said FET device; partitioning, by said computing device, each said source region and each said drain region into a plurality of contact regions, a number of contact regions in each said source region and each said drain region being equal to said number of contacts in each said source region and each said drain region, respectively; calculating, by said computing device, a set of resistances comprising a wire resistance (r), a contact resistance (R CA ), and a diffusion resistance (R) for each of said contacts in said FET device; determining, by said computing device, measured dimensions of widths, lengths, and distances of layout shapes forming said FET device and connections to said FET device; computing, by said computing device, a set of weights based on relative widths of said contact regions; determining, by said computing device, said total resistance of said FET device by summing products of said set of resistances and said set of weights for each of a plurality of contacts in series, said summing being performed for all of said plurality of contacts in one of said source region and said drain region of said FET device; and forming, by said computing device a netlist based on said total resistance of said FET device.