Patent ID: 8132136

Claim:
A method in a computer-aided design system for generating a functional design model of a dynamic critical path detector, the method comprising: generating, by a processor, a functional representation of a first latch arranged in a region of a critical path and structured to receive a data signal; generating a functional representation of a second latch arranged in a region of the critical path; generating a functional representation of a delay element to couple a delayed version of the data signal to the second latch; and generating a functional representation of a comparator device positioned between an output and input of two components of the second latch and structured and arranged to compare outputs of the first and second latches, wherein: a miscompare from the comparator device is indicative of an approaching timing failing condition and the miscompare occurs when the output of the first latch and the output of the second latch occur within different clock pulses; and the output of the first latch and the output of the second latch occur within different clock pulses when the output of the first latch occurs before a leading edge of a first clock pulse and the output of the second latch occurs after a trailing edge of a second clock pulse.