Patent ID: 7495589

Claim:
An analog to digital converter (ADC) comprising: (a) an integrator for sampling an input signal, having an input coupled to receive an input signal and also having an output; (b) a comparator having a signal input coupled to the output of the integrator, and an output representing a present state of the comparator depending on a relationship of an output voltage on the output of the integrator to a threshold voltage; (c) a digital filter having an input coupled to the output of the comparator and also having an output for conducting a gain-corrected digital output signal representative of the input signal; (d) a memory for storing an externally determined gain-adjusted LSB size number; and (e) circuitry coupled to the memory for applying an integral number of the gain-adjusted LSB size numbers to the input of the digital filter to cause the integral number of gain-adjusted LSB size numbers to be applied to content of the digital filter in accordance with the present state of the comparator to accumulate a value in the digital filter during successive cycles of the ADC so as to generate the gain-corrected digital output signal.