Patent ID: 7570072

Claim:
A display device comprising: a gate line; a source line; a power source line; a driver circuit for supplying a signal to the source line; a pixel portion driven by potentials of the gate line and the source line; a switching circuit connected to the gate line and the source line; a test circuit; and a first connection terminal and a second connection terminal connected to the test circuit; wherein the test circuit includes a first circuit connected to the gate line and the source line, a second circuit connected to the source line, and a third circuit connected to the gate line and the second circuit; wherein the switching circuit connects the gate line and the source line to the test circuit when a signal for controlling writing of the source line is not supplied to the driver circuit; wherein the first circuit compares an inputted potential of the gate line and an inputted potential of the source line and outputs a first potential to the first connection terminal when the inputted potential of the source line is lower than the inputted potential of the gate line; wherein the second circuit inputs a second potential to the third circuit, which is obtained by subtracting a reference potential from an inputted potential of the source line; wherein the third circuit compares an inputted potential of the gate line and the second potential and outputs a third potential to the second connection terminal when the second potential is lower than the potential of the gate line; wherein the pixel portion comprises a first transistor, a second transistor, and a light-emitting element; wherein a gate of the first transistor is connected with the gate line, one of a source and a drain of the first transistor is connected with the source line, and the other of the source and the drain of the first transistor is connected with a gate of the second transistor; and wherein one of a source and a drain of the second transistor is connected with the light-emitting element and the other of the source and the drain of the second transistor is connected with the power source line.