Patent ID: 7662522

Claim:
A method for manufacturing a semiconductor device comprising: calculating a correction amount for correcting a dimension error of a pattern on a patterned semiconductor substrate having the pattern generated in at least one of a plurality of manufacturing steps performed on the semiconductor substrate in which a circuit of one layer of a semiconductor device is formed, by using an area and a total side length of a perimeter of the pattern included in each grid region of a plurality of mesh-like grid regions made by virtually dividing a pattern creation region of an exposure mask; forming a pattern on the exposure mask, with correcting figure dimensions of the pattern on the exposure mask using the correction amount calculated above associated with said dimension error on the patterned semiconductor substrate; exposing the pattern on the exposure mask onto the semiconductor substrate on which a resist film is coated; developing the resist film after the exposing; and processing the substrate by using a resist pattern after the developing.