Patent ID: 8400833

Claim:
A method of evaluating a semiconductor storage device of a floating gate type, comprising: calculating an electron density distribution of a tunnel insulating film of a memory cell by multiplying a change rate of a threshold voltage Vt of the memory cell of the semiconductor storage device with respect to the change of the logarithm of a time with ε*Cr*2k/Tox/q (where ε is a permittivity of the tunnel insulating film of the memory cell, Cr indicates a coupling ratio of the memory cell, Tox indicates the thickness of the tunnel insulating film, k indicates an attenuation rate of the existence probability when the charges are detrapped and is represented as k=(2mE/(h/2n) 2 ) 0.5 , m indicates the mass of the electron, E indicates an energy level of the trap of the tunnel insulating film, h indicates a Planck's constant, and π indicates a circumference ratio).