Patent ID: 8208567

Claim:
An apparatus for reducing a Peak-to-Average Power Ratio (PAPR), the apparatus comprising: a gain processor for multiplying time signals in paths by gains set for respective paths; a delay processor for delaying gain-multiplied signals in second to last paths except for a first path by time delays set for respective second to last paths; a summer for summing the gain-multiplied signal for the first path received from the gain processor and the delayed signals received from the delay processor; a PAPR processor for measuring a PAPR of the summed signal received from the summer, for comparing the measured PAPR with a target PAPR, and for requesting one or more changes of at least one of the gain and the time delay of each path; and a gain delay controller for changing the at least one of the gain and the time delay of each path according to the request received from the PAPR processor and for controlling at least one of the gain processor and the delay processor according to the respective change, wherein, when the measured PAPR is larger than the target PAPR, the PAPR processor requests the one or more changes of the at least one of the gain and the time delay of each path, and the gain delay controller changes the at least one of the gain and the time delay of each path using a gain and delay combination that has not been previously used among all possible gain and delay combinations for each path.