Patent ID: 7092295

Claim:
A semiconductor memory device comprising a programming circuit for a nonvolatile memory cell, the programming circuit including a voltage switch connected to a gate of a nonvolatile memory cell, and a controller connected to the voltage switch for controlling the voltage switch to apply a voltage pulse to the gate of the nonvolatile memory cell until charges in an amount close to a target amount of charge are accumulated in the nonvolatile memory cell, wherein the controller controls the voltage switch to apply a first pulse having a first time width at a first voltage so that a first amount of charge which is smaller than the target amount of charge is accumulated in the nonvolatile memory cell, controls the voltage switch to apply, to the nonvolatile memory cell, a second pulse train of pulses each having a second time width shorter than the first time width so that a second amount of charge which is smaller than the target amount of charge and larger than the first amount of charge is accumulated in the nonvolatile memory cell, controls the voltage switch so that a voltage of each pulse of the second pulse train is higher than a voltage of the immediately preceding pulse and, further, controls the voltage switch to apply, to the nonvolatile memory cell, a pulse train of pulses each having a third time width shorter than the second time width so that a third amount of charge which falls within an allowable error range of the target amount of charge is accumulated in the nonvolatile memory cell, and wherein the nonvolatile memory cell includes a single gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and the writing or erasing operation to a selected one of the memory functional units formed on both sides of the gate electrode can be executed independently from the unselected one of the memory functional units by controlling each voltage applied to the diffusion regions and the gate electrode.