Patent ID: 8762121

Claim:
A simulated annealing method to determine placement of integrated circuit (IC) components within a core area of an IC during physical design of the IC, comprising: partitioning a netlist of the IC into a current number of bins representing areas of the IC to generate a current placement configuration at a current partition hierarchy level; calculating an iteration limit based on a level number of the current partition hierarchy level, wherein the iteration limit at the current partition hierarchy level has a linear relationship with the level number of the current partition hierarchy level; perturbing the current placement configuration to generate a new placement configuration; determining whether to accept the new placement configuration as the current placement configuration based on costs associated with the current placement configuration and the new placement configuration; and prior to partitioning further the netlist into a new number of bins at a next partition hierarchy level, determining whether a number of repeating the perturbing the current placement configuration and the determining whether to accept the new placement configuration has reached the iteration limit at the current partition hierarchy level, wherein the new number of bins is greater than the current number of bins.