Patent ID: 8042086

Claim:
A constrained random test bench for verifying an integrated circuit design, comprising: an instruction streamer configured to: hold an instruction sequence for verifying a particular mode of operation of an integrated circuit design, wherein the instruction sequence has a corresponding first priority; and detect an interrupt condition and queue an interrupt service routine instruction sequence a random time after detecting the interrupt condition, wherein the interrupt service routine instruction sequence has a corresponding second priority; a priority scheduler in communication with the instruction streamer, the priority scheduler operable to: issue the instruction sequence when the first priority is higher than the second priority; and issue the interrupt service routine instruction sequence when the second priority is higher than the first priority; wherein the instruction sequence and the interrupt service routine instruction sequence are each issued one instruction at a time; and an instruction translator in communication with the priority scheduler, the instruction translator configured to receive the issued instruction and apply it to the integrated circuit design to perform a requested operation, wherein an expected data value associated with the requested operation is stored in a particular register of a mirror memory; and wherein the instruction streamer is further configured to hold a second instruction sequence to: read a register of the integrated circuit design to retrieve a register data value, wherein the register of the integrated circuit design corresponds to the particular register of the mirror memory; compare expected data value to the register data value; provide an indication that the requested operation is a success when the expected data value matches the register data value; and provide an indication that the requested operation is a failure when the expected data value does not match the register data value.