Patent ID: 6862205

Claim:
A semiconductor memory device comprising: a plurality of memory cells each including a capacitor having a charge storage node, and a first MIS transistor and a second MIS transistor each having a first source/drain terminal connected to the charge storage node; a plurality of first word lines and a plurality of first bit lines respectively connected to gates and second source/drain terminals of the first MIS transistors; a plurality of second word lines and a plurality of second bit lines respectively connected to gates and second source/drain terminals of the second MIS transistors; a timer circuit for generating a periodic signal having a predetermined period; an access word line selection circuit for selectively activating the plurality of first word lines in response to an external access request; a refresh word line selection circuit for selectively activating the plurality of second word lines at the predetermined period with the periodic signal; a plurality of first sense amplifiers for data access connected to the respective first bit lines; and a plurality of second sense amplifiers for data refresh connected to the respective second bit lines, wherein the first sense amplifiers are activated in response to an external access request, and the second sense amplifiers are activated in response to the periodic signal, and wherein an activation time period of the first word lines and an activation time period of the second word lines are shifted in phase from each other.