Patent ID: 8889487

Claim:
A method for forming a three-dimensional gate driver integrated circuit, comprising: providing a low-side integrated circuit having formed thereon a low-side driver and a first LDMOS (lateral double-diffused metal-oxide-semiconductor) transistor, the low-side integrated circuit receiving a low-side input signal and a high-side input signal and providing a low-side output signal; providing a high-side integrated circuit having formed thereon a high-side driver, a first load circuit, and a latch circuit, the high-side integrated circuit providing a high-side output signal; attaching the low-side integrated circuit to a package die paddle; attaching the high-side integrated circuit to the low-side integrated circuit through a high voltage passivation layer; etching a through-silicon via opening in the high-side integrated circuit and the high voltage passivation layer, the through-silicon via opening contacting the first load circuit and extending to a drain terminal of the first LDMOS transistor formed on the low-side integrated circuit; and forming a conductive material in the through-silicon via opening, the through-silicon via thus formed electrically connecting the first load circuit to the drain terminal of the first LDMOS transistor, wherein the first LDMOS transistor and the first load circuit form a level shifter circuit, the first LDMOS transistor receiving a first signal relating to the high-side input signal and providing a first level-shifted signal to the latch circuit, the latch circuit generating a drive signal for driving the high-side driver.