Patent ID: 7418368

Claim:
A method for manufacturing yield testing and configuring a multi-core processor system chip comprising a plurality of processing cores, comprising: setting at least one adjustable power supply component to provide a supply voltage having an initial nominal supply voltage value to each of the plurality of processing cores, the initial nominal supply voltage value specified as operating a processing core at a minimum reference clock speed pursuant to a design rule; for N iterations selecting a core of the plurality of processing cores and iteratively lowering a core set supply voltage provided by the at least one adjustable power supply component to the selected core and observing a clock speed of the selected core at the lowered supply voltage until an Nth observed clock speed generated responsive to an Nth lowered supply voltage is less than the minimum reference clock speed and setting the at least one adjustable power supply component to provide an (N−1)th lowered supply voltage as an operative supply voltage to the selected core; repeating the N iteration core selecting, the iterative supply voltage lowering and clock speed observing and the (N−1)th lowered supply voltage operative supply voltage setting for each unselected core of the processing core plurality until each of the cores has been selected, wherein different cores may have different core operative supply voltages set relative to the minimum reference clock speed; determining an overall power consumption value for the multi-core processor system with each of the plurality of cores operating at its respective set operative supply voltage; and passing the multi-core processor system chip if the overall power consumption value does not exceed a specified maximum power consumption value; or failing the chip.