Patent ID: 7679597

Claim:
A scan driving circuit comprising a plurality of stages, the plurality of stages being for receiving four clocks, wherein each of the plurality of stages is configured to receive three of the four clocks, to receive and delay an input signal through an input terminal, and to output an output signal through an output terminal, wherein the input terminal of each of the plurality of stages is connected to the output terminal of a previous one of the stages, wherein each of the plurality of stages comprises: a transistor for turning on/off a connection of the input terminal according to a second clock among the clocks, the second clock for inputting through a second clock terminal; a switch section for transferring a first voltage to the output terminal according to a first clock among the clocks, and for preventing the first voltage from being transferred to the output terminal according to the input signal, the first clock for inputting through a first clock terminal; and a storage section for maintaining a voltage of the output terminal for a predetermined time, and for transferring a voltage of a third clock among the clocks to the output terminal according to the input signal, the third clock for inputting through a third clock terminal.