Patent ID: 7805621

Claim:
A bus interface comprising: a first power supply bus adapted to distribute a first power supply voltage, wherein the first power supply bus is adapted to be energized during a normal operating mode of the bus interface and the first power supply bus is adapted to be not energized during a low power operating mode of the interface; a second power supply bus adapted to distribute the first power supply voltage during the normal operating mode and distribute a second power supply voltage during the low power operating mode; first circuitry coupled with the first power supply bus; and second circuitry coupled with the second power supply bus, wherein: the first circuitry and the second circuitry are adapted to be powered using the first power supply voltage in the normal operating mode; the first circuitry is adapted to be powered down in the low power operating mode; the second circuitry is adapted to be powered by the second power supply voltage in the low power operating mode; the first circuitry comprises at least a portion of datapath circuitry of the bus interface; and the second circuitry comprises a power management control circuit adapted to, in the low power operating mode, receive a power management event indication signal and, responsive to the power management event indication signal, provide at least one of an in-band power management indication and an out-of-band power management indication to one or more devices in a computing system.