Patent ID: 7870322

Claim:
A memory module comprising: a substrate; a first signal line to carry a first signal, and a second signal line to carry a second signal, wherein the first signal line and the second signal line each have: (i) a respective first end coupled to a respective edge finger, (ii) a respective first line segment coupled to the respective first end and disposed along a width of the memory module, (iii) a respective second line segment disposed along a length of the memory module, (iv) the first line segment and the second line segment coupled at a respective turn, and (v) a respective second end coupled to a respective termination; a first synchronous memory device disposed on the substrate; and a second synchronous memory device disposed on the substrate, wherein the first synchronous memory device and the second synchronous memory device are connected to respective second line segments of the first signal line and the second signal line, wherein the first signal arrives at the first synchronous memory device before arriving at the second synchronous memory device and the first signal arrives at the second synchronous memory device before reaching the termination coupled to the second end of the first signal line, and wherein the second signal arrives at the first synchronous memory device before arriving at the second synchronous memory device and the second signal arrives at the second synchronous memory device before reaching the termination coupled to the second end of the second signal line.