Patent ID: 7509365

Claim:
A method of operating an arithmetic logic unit to eliminate latency associated with a dependent instruction which must select between a true and a complement of a previous instruction result, comprising: issuing a first operation to the arithmetic logic unit to be executed during a current cycle to yield a result; determining that a subtraction operation which immediately follows the first operation will require a complement of the result, prior to executing the first operation within the arithmetic logic unit, by decoding an instruction associated with the subtraction operation prior to the current cycle using instruction decode logic; sending an invert control signal to an adder, a rotator, and a data manipulation unit of the arithmetic logic unit from the instruction decode logic in response to said determining; inverting the result during the current cycle using the adder, the rotator, and the data manipulation unit in response to the invert control signal; and subtracting the result during a cycle subsequent to the current cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled.