Patent ID: 7565602

Claim:
A memory error detection device for a memory having memory cells arranged in memory rows and memory columns and having binary memory values, wherein at least respective memory rows or respective memory columns have associated therewith a parity bit, wherein a protection memory cell is arranged in a protection memory row of said memory rows or a protection memory column of said memory columns, wherein a first state of the protection memory cell indicates that the memory is write-protected and a different second state of the protection cell indicates that the memory is not write-protected, wherein at least a state of a parity bit of the protection memory row or the protection memory column is chosen such that the protection memory row or the protection memory column has a predetermined reference parity value in a state of integrity, wherein said predetermined reference parity value is chosen so that a row error or a column error in the protection memory row or the protection memory column representing a state of the protection memory cell signaling a write-protected state of the memory also results in the reference parity value; wherein said predetermined reference parity value is different from a parity value obtained for the protection memory row or the protection memory column when respective cells in the protection memory row or the protection memory column are in the second state; and wherein the memory error detection device comprises a comparator adapted to calculate the parity value for the protection memory row or the protection memory column and to compare the calculated parity value with said predetermined reference parity value.