Patent ID: 6941499

Claim:
A method to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device comprising: introducing a set of faults into an embedded memory behavior model wherein said embedded memory behavior model comprises a high-level language model and wherein each member of said set of faults comprises a finite state machine state, a memory address, and a memory data fault; thereafter simulating said built-in self-test circuit and said embedded memory behavior model wherein said built-in self-test circuit generates input data and address patterns for said embedded memory behavior model, wherein said embedded memory behavior model outputs memory address and data in response to said input data and address patterns, and wherein said input address and data and said memory address and data are compared in said built-in self-test circuit and a fault output is generated if not matching; de-scrambling said set of faults; and comparing said fault output and said de-scrambled set of faults to verify the performance of said built-in self-test circuit.