Patent ID: 7137053

Claim:
A method of configuring an integrated circuit for testing, wherein said integrated circuit comprises: a plurality of integrated circuit I/ 0 pins having a predetermined I/O frequency; a plurality of scan chains, in electrical communication with said I/O pins, wherein said scan chains have a predetermined latching frequency, said integrated circuit being adapted for connection to an integrated circuit testing device via an available number of said plurality of integrated circuit I/O pins, said method of configuring said integrated circuit for testing comprising at least one of the steps of: (a) minimizing an integrated circuit test time when said latching frequency is less than said predetermined I/O frequency and said available number of said plurality of integrated circuit I/O pins is less than a number of pins required for a proposed scan architecture; (b) minimizing said integrated circuit test time when said latching frequency is greater than said predetermined I/O frequency and said available number of said plurality of integrated circuit I/O pins is greater than said number of pins required for a proposed scan architecture; (c) minimizing said integrated circuit test time when said integrated circuit testing device frequency is less than said predetermined I/O frequency, the number of integrated circuit testing device pins is less than said available number of said plurality of integrated circuit I/O pins, and said integrated circuit testing device frequency is higher than or equal to a multiple of said predetermined latching frequency; (d) minimizing said integrated circuit test time when said integrated circuit testing device frequency is greater tan said predetermined I/O frequency, the number of integrated circuit testing device pins is less than said available number of said plurality of integrated circuit I/O pins and said predetermined I/O frequency is lower than said integrated circuit testing device frequency and said predetermined latching frequency; (e) minimizing said integrated circuit test time when said integrated circuit testing device's test frequency is higher than said predetermined I/O frequency and the number of integrated circuit testing device pins is less than said available number of said plurality of integrated circuit I/O pins, and said predetermined I/O frequency and said integrated circuit testing device's test frequency are both higher than a multiple of said predetermined latching frequency; and (f) minimizing said integrated circuit test time when said integrated circuit testing device's test frequency is lower than said predetermined I/O frequency and said predetermined latching frequency, and the number of integrated circuit testing device pins is greater than said number of pins required for said proposed scan architecture.