Patent ID: 7781776

Claim:
An active device array substrate, comprising: a substrate; a patterned first metal layer on the substrate, wherein the patterned first metal layer comprises a plurality of gate lines, a plurality of gates and a plurality of gate pads, and the gate lines are connected with the gates and the gate pads; a patterned first insulating layer on the substrate and the patterned first metal layer; a patterned semiconductor layer on the patterned first insulating layer; a patterned metal multilayer, which includes a plurality of data lines, a plurality of drains, a plurality of storage electrodes, a plurality of sources and a plurality of data pads, wherein the data lines are connected with the sources and the data pads, the sources and the drains are respectively configured above the gates, each of the drains and each of the storage electrodes respectively have a drain opening and a storage electrode opening, and the drain openings and the storage electrode openings expose parts of the patterned semiconductor layer; a patterned second insulating layer, parts of which are on the patterned metal multilayer, wherein the patterned second insulating layer and the patterned first insulating layer expose parts of the drain openings, parts of the storage electrode openings, parts of the data lines, parts of the data pads, parts of the gate lines, and parts of the gate pads, and wherein the exposed storage electrode openings and exposed drain openings have under-cut structures; and a patterned conducting layer, which includes a plurality of pixel electrodes electrically connected to the drains individually.