Patent ID: 8046644

Claim:
A method for testing a dynamic random access memory (DRAM) positioned externally from a system on chip (SoC), the SoC comprising a central processing unit (CPU) and a random access memory (RAM), the method comprising: copying a test program of the DRAM from the DRAM to the RAM; starting the test program in the RAM; storing a start physical address and an end physical address of the DRAM in a first register and a second register of the CPU, respectively; writing first test data to the start physical address of the DRAM in the first register of the CPU; reading second test data from the start physical address of the DRAM; determining whether the second test data is the same as the first test data; returning a test failure result and ending the test program if the second test data is not the same as the first test data; or adding a fixed value to the start physical address of the DRAM in the first register to obtain a next start physical address if the second test data is the same as the first test data; determining whether the next start physical address is less than the end physical address of the DRAM in the second register; writing the first test data to the next start physical address if the next start physical address is less than the end physical address of the DRAM in the second register, and repeating the reading and determining steps; or returning a test success result and ending the test program if the next start physical address is not less than the end physical address of the DRAM in the second register; wherein an available memory location of the RAM is between a first physical address and a second physical address of the RAM, and the test program is stored in the DRAM between a third physical address and a fourth physical address of the RAM; wherein the step of copying the test program of DRAM from the DRAM to the RAM comprises: storing the first physical address of the RAM in a third register of the CPU; storing the third physical address of the DRAM in a fourth register of the CPU; storing the fourth physical address of the DRAM in a fifth register of the CPU; copying the test program to the first physical address in the third register; adding the fixed value to the first physical address in the third register to obtain a new first physical address in the third register; adding the fixed value to the third physical address in the fourth register to obtain a new third physical address in the fourth register; determining whether the new third physical address in the fourth register is less than the fourth physical address in the fifth register; going on copying the test program to the new first physical address in the third register if the new third physical address in the fourth register is less than the fourth physical address in the fifth register; and stopping the copying block if the new third physical address in the fourth register is not less than the fourth physical address in the fifth register.