Patent ID: 8397190

Claim:
A method comprising: receiving a hardware description language (HDL) representation of a circuit block of an integrated circuit (IC), wherein the circuit block comprises a plurality of preexisting logic blocks; performing, by a processor: dissolving one or more hierarchical wrappers of the circuit block to access designated preexisting logic blocks of the plurality of preexisting logic blocks at a same level of hierarchy; creating new logic blocks, comprising: grouping together specified preexisting logic blocks of the designated preexisting logic blocks for each new logic block, wherein the specified preexisting logic blocks within each new logic block are logically equivalent to the specified preexisting logic blocks within each other new logic block; creating a respective hierarchical wrapper around each new logic block, comprising assigning a respective set of pins to each new logic block; and renaming logically equivalent pins within the respective sets of pins to have a same name for each new logic block, to provide identical respective interfaces for the new logic blocks: wherein each of the new logic blocks is logically equivalent to each other new logic block.