Patent ID: 7981786

Claim:
A method of fabricating a non-volatile memory device having a charge trapping layer comprising: forming a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode layer over a substrate, wherein the blocking layer is a first insulating layer; performing a first etching process using a mask layer pattern as an etching mask to remove the control gate electrode layer exposed by the mask layer pattern and to remove the blocking layer disposed between adjacent elements of the mask pattern layer by a specified thickness such that a portion of the blocking layer remains disposed between adjacent elements of the mask pattern layer; forming a second insulating layer on sidewalls of the control gate electrode layer and sidewalls of the blocking layer exposed by the first etching process; and performing a second etching process using the mask layer pattern and the second insulating layer as an etching mask to remove an exposed portion of the blocking layer disposed between each of the adjacent elements of the mask pattern layer, wherein the second etching process is processed as excessive etching to remove at least 50% of the total thickness of the charge trapping layer; and performing a process for curing etching damage on a sidewall of the blocking layer and a sidewall of an exposed portion of the charge trapping layer which are exposed by the excessive etching on the blocking layer.