Patent ID: 6952359

Claim:
A static content addressable memory array for a content addressable memory (CAM) device, comprising: a plurality of word lines; a plurality of data lines; a latch having complementary data nodes capacitively coupled to ground; first and second access transistors, each having a gate coupled to one of the plurality of word lines and coupled between a data node of the latch and a respective data line of the plurality; and a match circuit coupled to one of the complementary data nodes of the latch, the match circuit including first and second transistors coupled in series between the data lines to which the first and second access transistors are coupled, the first transistor having a gate coupled to a first one of the data nodes and the second transistor having a gate coupled to a second one of the complementary data nodes, and further including a discharge transistor coupled between a match line and ground, and having a gate coupled to a node between the first and second transistors, the match circuit configured to discharge the match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching.