Patent ID: 8201036

Claim:
An integrated circuit comprising: A. a TCK lead, a TMS lead, a TDI lead, and a TDO lead; B. a test access port circuit having a TCK input connected to the TCK lead, a TMS input connected to the TMS lead, a TDI input connected to the TDI lead, a TDO output, a TDO enable output, a data register and an instruction register that are connected to the TDI input and that are selectively coupled to the TDO output, and a state machine that is connected to the TCK input, the TMS input, the data register and the instruction register; C. a shadow access port circuit having a TCK input connected to the TCK lead, a TMS input connected to the TMS lead, a TDI input connected to the TDI lead, a SDO output, a SDO enable output, a data register and an instruction register that are connected to the TDI input and that are selectively coupled to the TDO output, and a state machine that is connected to the TCK input, the TMS input, the data register and the instruction register; and D. an output circuit having a TDO input connected to the TDO output, a TDO enable input connected to the TDO enable output, a SDO input connected to the SDO output, a SDO enable input connected to the SDO enable output, and a TDO output connected to the TDO output lead.