Patent ID: 7019575

Claim:
A mixing prevention circuit comprising: a first inverter circuit; a second inverter circuit having an input portion supplied with an output of the first inverter circuit; a third inverter circuit having an input portion supplied with an output of the second inverter circuit; a first p-channel MOS transistor and first n-channel MOS transistor whose gates are supplied with an output of the third inverter circuit and whose drains are connected together; a second n-channel MOS transistor having a gate supplied with the output of the first inverter circuit and a drain connected to a source of the first n-channel MOS transistor; a second p-channel MOS transistor and third n-channel MOS transistor whose drains are supplied with the output of the first inverter circuit and whose gates are supplied with the output of the third inverter circuit; a third p-channel MOS transistor having a gate connected to the drains of the first p-channel MOS transistor and first n-channel MOS transistor and a drain connected to a source of the second p-channel MOS transistor; and a fourth n-channel MOS transistor having a gate connected to the drains of the first p-channel MOS transistor and first n-channel MOS transistor and a drain connected to a source of the third n-channel MOS transistor.