Patent ID: 7605044

Claim:
A method comprising: forming a transistor over a semiconductor substrate, the transistor including a gate electrode, a source/drain region and a spacer having a laminated structure on sidewalls of the gate electrode including a first oxide film, a nitride film and a second oxide film; forming silicide over the gate electrode and the source/drain region; removing the second oxide film of the spacer; and forming a contact stop layer over the entire surface of the substrate including the gate electrode, wherein the contact stop layer is formed using a plasma enhanced chemical vapor deposition (PECVD) method, wherein the PECVD method is performed at a temperature range of between approximately 300 to 500° C. for 30 to 60 seconds with a bias power in a range between approximately 10 to 20 W and a ratio of SiH 4 to NH 3 in a range between 3:1 to 5:1, wherein the contact stop layer has at least one of tensile stress characteristics and compressive characteristics.