Patent ID: 8133608

Claim:
A battery pack short circuit management system, comprising: a plurality of cells, wherein each of said cells is electrically connected to a first collector plate and a second collector plate, and wherein said plurality of cells are electrically connected in parallel; a first plurality of fusible interconnects electrically connecting a first terminal of each of said plurality of cells, except for a first cell, to said first collector plate; a second plurality of fusible interconnects electrically connecting a second terminal of each of said plurality of cells, except for said first cell, to said second collector plate; a first fusible interconnect electrically connecting a first terminal of said first cell of said plurality of cells to said first collector plate, wherein said first fusible interconnect is not one of said first and second pluralities of fusible interconnects, and wherein said first fusible interconnect is configured to fuse after said first plurality of fusible interconnects fuse and after said second plurality of fusible interconnects fuse; a second fusible interconnect electrically connecting a second terminal of said first cell of said plurality of cells to said second collector plate, wherein said second fusible interconnect is not one of said first and second pluralities of fusible interconnects, and wherein said second fusible interconnect is configured to fuse after said first plurality of fusible interconnects fuse and after said second plurality of fusible interconnects fuse; and an arc suppression system corresponding to at least one of said first and second fusible interconnects, wherein said arc suppression system is not utilized with said plurality of cells except for said first cell.