Patent ID: 7191412

Claim:
A method of processing a circuit description for logic simulation, the circuit description having a hierarchy of components, each component in the hierarchy being described using one of a first hardware description language (HDL) or a second HDL, the method comprising: selecting a component in the hierarchy as a root component; elaborating the root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component up to a cross-language boundary, the root component being described using one of the first HDL or the second HDL and each component at the cross-language boundary being described using the other of the first HDL or the second HDL; storing each component at the cross-language boundary in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language; and establishing a connection between each component at the cross-language boundary and a respective parent component in the hierarchy.