Patent ID: 8224637

Claim:
A method of modeling a transistor in an integrated circuit design, comprising: obtaining layout data for the integrated circuit design; extracting a geometry relating the transistor to at least one well edge of at least one implant well from the layout data; calculating, using a computer, an effective well proximity value for the transistor based on the at least one well edge using a complementary error function, wherein the effective well proximity value for the transistor is calculated using a distance from a gate of the transistor to the at least one well edge and a distance representing a portion of the gate of the transistor which is parallel to the at least one well edge; measuring a threshold voltage associated with a second transistor of a test structure; and simulating the integrated circuit design based upon the calculated effective well proximity value and the threshold voltage associated with the second transistor of the test structure, wherein the response of the test structure is used to identify variations caused by integrated circuit device behavior.