Patent ID: 8103918

Claim:
A multiport memory comprising: an array of bit storage cells; a plurality of data access paths providing multiport access to said array, wherein said plurality of data access paths perform access operations during normal operations driven by respective clock signals, and at least one of said plurality of data access paths is responsive to an external memory adjust signal to adjust one or more access operation timings relative to a respective independent clock signal; and self-test support circuitry active during self-testing operations upon said multiport memory, said self-test support circuitry comprising: duplicate clock enabling circuitry, responsive to a duplicate clock enable signal, configured to enable a clock signal of one of said plurality of access paths used during said normal operations to be used as a shared clock signal to drive access operations for a group of access paths during said self-testing operations; and clock adjusting circuitry, responsive to said external memory adjust signal, configured to modify at least one characteristic of said shared clock signal to form a modified shared clock signal as used to drive at least one of said group of access paths during said self-testing operations while said shared clock signal is used to drive at least one other of said group of access paths during said self-testing operations.