Patent ID: 8269287

Claim:
A device comprising an MOS capacitor including a gate structure disposed upon an insulating layer on a substrate, the gate structure comprising a contiguous conductive layer patterned to form a plurality of gate fingers, each gate finger electrically connected to each other through the conductive layer and comprising a length L and a width W less than length L, and a plurality of source/drain diffusions formed in the substrate on each side of the plurality of gate fingers and extending substantially the entire length L of each gate finger, the plurality of source/drain diffusions are separated from each other by channel regions underlying each of the plurality of gate fingers, wherein the gate structure and the plurality of source/drain diffusions capacitively couple along the length of each of the plurality of gate fingers and a sum of a capacitance formed between the plurality of gate fingers and the source/drain diffusions formed on either side thereof is greater than a sum of a capacitance formed between a continuous conductive region under each gate finger and the overlying gate finger.