Patent ID: 7136443

Claim:
A sample selection and data alignment circuit for selecting a selected over sampled signal among a plurality of over sampled signals (S 0 , . . . , S n−1 ) obtained by over sampling an incoming serial data stream of bits at n clock phase signals (C 0 , . . . , C n−1 ) of a multiphase clock signal, according to a corresponding select signal, and synchronously aligning said selected over sampled signal relative to a predefined phase of said multiphase clock signal to produce a recovered data, the circuit comprising: n logic blocks, connected serially, each block comprising: a first logic block labeled 0; a plurality of n−2 intermediate logic blocks labeled 1 to (n−2); and a last logic block labeled (n−1); and an output latch coupled to said last logic block, said output latch having an output latch data input, an output latch clock input and an output latch data out, wherein said first logic block 0 includes a level sensitive latch 0 receiving over sampled signal S 0 on its data input 0 and the phase clock signal C 0 on its clock input 0, wherein said last logic block n−1 includes a multiplexer n−1 and a level sensitive latch n−1 that are serially connected, said multiplexer n−1 having a first and second multiplexer input n−1 and a multiplexer output n−1, said level sensitive latch n−1 having a latch data input n−1, a latch clock input n−1 and a latch output n−1, wherein the first multiplexer input n−1 is connected to the level sensitive output n−2 of the level sensitive latch of the preceding logic block and the second multiplexer input n−1 receives sampled signal S n−1 , and the multiplexer n−1 is controlled by select signal G n−1 ; the multiplexer output n−1 is connected to the latch data input n−1, that latch clock input n−1 receives clock phase G n−1 ; the latch output n−1 connected to the output latch data input, and wherein each of said intermediate logic blocks having label i, includes a multiplexer i and a level sensitive latch i that are serially connected, said multiplexer i having a first and second multiplexer input i, and said level sensitive latch i having a latch data input i, a latch clock input i and a latch output i, wherein the first multiplexer input i is connected to the level sensitive latch output i−1 of the level sensitive latch of the preceding logic block i−1 and wherein the second multiplexer input i receives over sampled signals S i ; said multiplexer i being controlled by a control signal i which is obtained by ORing select signal G i and the control signal i+1 of the next multiplexer i+1, the multiplexer output i being connected to the latch data input i and wherein the latch clock input i receives clock phase signal C i .