Patent ID: 6954209

Claim:
A computer system having a core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of Accelerated Graphics Port (AGP) buses wherein the plurality of AGP buses each have the same logical AGP bus number, the system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set connected to the host bus and the random access memory bus; the core logic chip set configured as a first interface bridge between the host bus and the random access memory bus; the core logic chip set configured as a plurality of second interface bridges between the host bus and a plurality of AGP buses the core logic chip set configured as a plurality of third interface bridges between the memory bus and the plurality of AGP buses, wherein the plurality of AGP buses are physically separate but have the same logical AGP bus number; a AGP address comparator; a AGP arbiter for receiving request signals from and issuing grant signals to AGP devices connected to the plurality of AGP buses; and a AGP target flow controller; the AGP address comparator receiving transaction addresses from the plurality of AGP bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of the plurality of AGP bus interfaces are the same or are within M bytes of each other, where M=16×2 n and n is zero or a positive integer number, then the AGP address comparator sends an address match signal to the AGP target flow controller which causes a retry signal to be issued from the one of the plurality of AGP bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of the plurality of AGP bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.