Patent ID: 8806253

Claim:
A microprocessor having power gate control logic comprising: an instruction scheduling unit coupled in handshaking relationship with an execution unit, said execution unit comprising a state machine implementing power gate control logic and logic for measuring a number of instructions being issued from the instruction scheduling unit per cycle and functional macros; said instruction scheduling unit comprising an instruction queue; wherein instructions are selectively sent between said instruction queue in said instruction scheduling unit and the functional macros according to said power gate control logic implemented by state machine in the execution unit, said state machine determining if the number of issued instructions per cycle is less than a threshold value, and determining further if at least two of the instructions being issued from the instruction scheduling unit are independent of each other only when the instructions issued per cycle is less than a threshold level, and issuing power gate mode control signals to remove power to the functional macros dynamically when said instructions are independent of each other without incurring significant loss of performance.