Patent ID: 7061296

Claim:
A circuit arrangement for generating a digital clock signal, the circuit arrangement comprising: a transistor circuit including a first, n-channel FET transistor and a second, p-channel FET transistor, which are connected in series, a comparator including a positive comparator input, a negative comparator input and a comparator output, a device for providing two switching thresholds, which, at its output, alternatively provides the two switching thresholds to the negative input of the comparator, a capacitance, which is alternately charged and discharged via the two FET transistors, the voltage present at the capacitance being fed to the positive comparator input, means for setting a frequency of the digital clock signal generated by the comparator by influencing the voltage at the positive comparator input, wherein an output signal generated at the output terminal of the comparator represents a digital clock signal, which is fed back to the input of the device for providing two switching thresholds and to the gate terminals of the first and second FET transistors, wherein the means for setting the frequency comprises a device for controlling currents respectively passing through the first FET transistor and the second FET transistor, and wherein the device for controlling currents includes means for controlling the first FET transistor and the second FET transistor such that the capacitance is continuously charged discharged via the first FET transistor and the second FET transistor.