Patent ID: 7660926

Claim:
An apparatus comprising a core for implementing a communications port, the core being operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing, whereby each sub-port is allocated a corresponding data transfer capacity, wherein the core comprises: a plurality of sequential logic elements operating at a plurality of data transfer rates corresponding to the data transfer capacities of the sub-ports, wherein the plurality of sequential logic elements are used to implement time division multiplexing by allowing data associated with each sub-port to be stored separately as the data is passed along a pipeline, wherein each sequential logic element is coupled to a corresponding control logic that is configured to distribute data to the sequential logic in a format which is suitable for the pipeline, and wherein only one of the plurality of sequential logic elements is active during any given phase of a phase cycle; and combinatorial logic operating at the full data transfer capacity of the port which is divided among the plurality of sub-ports, wherein the combinatorial logic is shared in the core by the plurality of sub-ports, wherein the combinatorial logic is configured to receive data from one of the plurality of sequential logic elements associated with a sub-port during any given phase of a phase cycle, wherein the combinatorial logic remains active during all phases of the phase cycle, and wherein the combinatorial logic comprises a finite state machine for controlling the combinatorial logic to operate upon the data associated with each sub-port.