Patent ID: 8918608

Claim:
An apparatus configured to allow execution of a single physical copy of at least a portion of code by at least two processing units, comprising: a plurality of processing units including at least a first processing unit and a second processing unit; an instruction memory connected to the first processing unit and the second processing unit via a virtual address mapping, the instruction memory storing a single copy of the at least a portion of code to be executed by the first processing unit and the second processing unit, wherein the at least a portion of code to be executed has a first virtual address starting point for the first processing unit and a second virtual address starting point for the second processing unit, such that a span difference that is equal to a predetermined offset value times a factor value is maintained; and a data memory accessible by the plurality of processing units via the virtual address mapping, wherein the data memory stores at least a first data block to be used by the first processing unit and having a third virtual address starting point, and a second data block to be used by the second processing unit and having a fourth virtual address starting point, such that the span difference between the third virtual address starting point and the fourth virtual address starting point is maintained; wherein at least a data access by the at least a portion of code to any of the first data block and the second data block is performed as a program counter relative memory access mode combined with a data offset, thereby allowing a single instantiation of the single physical copy of the at least a portion of code by at least the first processing unit and the second processing unit while maintaining separate data block accesses.