Patent ID: 7738623

Claim:
A shift register circuit comprising: first and second input terminals, first and second output terminals, a first clock terminal, and a reset terminal; a first transistor configured to supply a first clock signal inputted to said first clock terminal to said first output terminal; a second transistor configured to discharge said first output terminal; a third transistor configured to supply said first clock signal to said second output terminal; and a fourth transistor configured to discharge said second output terminal, said first transistor and said third transistor each having a control electrode connected to a first node, said second transistor and said fourth transistor each having a control electrode connected to a second node, and said shift register circuit further comprising: a fifth transistor connected between said first node and said first input terminal and having a control electrode connected to said second input terminal; and a sixth transistor having a control electrode connected to said reset terminal and configured to discharge said first node, wherein a pulse signal is input to the first input terminal.