Patent ID: 8174874

Claim:
A semiconductor memory device comprising: bit line pairs extending in a column direction, each of the bit line pairs comprising a first bit line and a second bit line; and memory cell groups connected to the bit line pairs, respectively, and each comprising memory cells, wherein each of the memory cells comprises a first transistor, a second transistor and a resistive memory element, a gate electrode of the first transistor is connected to a first word line extending in a row direction, a gate electrode of the second transistor is connected to a second word line extending in the row direction, one end of the resistive memory element is connected to the first bit line, a drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element, a source region of the first transistor and a source region of the second transistor are connected to the second bit line, a second transistor of a first memory cell shares a source region with a first transistor of a second memory cell which is adjacent to the first memory cell in the column direction, two bit line pairs which are adjacent in the row direction comprise a first column unit by connecting first bit lines thereof to each other, or connecting second bit lines thereof to each other, a second bit line or a first bit line located at a center of the first column unit is formed of a first interconnect layer, a first bit line or a second bit line located at least one end portion of the first column unit is formed of a second interconnect layer located above the first interconnect layer, the second interconnect layer is connected to a diffusion region of the first transistor or a diffusion region of the second transistor through a first contact or the resistive memory element, and a first bit line or a second bit line located at least one end portion is located closer to a center of the first column unit than a connecting part between the bit line and a lower layer.