Patent ID: 8125846

Claim:
An internal voltage generating circuit of a semiconductor memory device, comprising: a driving current generator configured to control the magnitude of a driving current and to supply a controlled driving current in response to a power-down enable signal, to a normal enable signal, and to an operating enable signal that are activated according to an operational mode; a comparison voltage generator configured to receive a reference voltage and an internal power supply voltage, to output a differentially amplified comparison voltage to a second node in response to a voltage of a first node that is determined according to a difference between the reference voltage and the internal power supply voltage, and to operate according to the driving current supplied to a third node; a bulk bias controller configured to receive at least two voltages and to selectively output a voltage among the received voltages as a bulk bias voltage in response to the power-down enable signal, the normal enable signal, and the operating enable signal; and an internal voltage driver configured to control a threshold voltage in response to the bulk bias voltage, to control a current amount in response to the comparison voltage, and to output the internal power supply voltage to an output node.