Patent ID: 7519747

Claim:
A buffer circuit comprising: a plurality of memory locations to hold data; a read pointer to point a read address of the plurality of memory locations from which to read output data; a write pointer to point a write address of the plurality of memory locations in which to write input data; the read pointer and the write pointer operable responsive to a read clock signal and a write clock signal, respectively, to sequence the read address and the write address, respectively, across an address space of the plurality of memory locations; a control register to store a nominal level for the buffer circuit; the control register being programmable for receiving the nominal level for setting latency of the read pointer; the latency of the read pointer being variable responsive to a fill level of the plurality of memory locations relative to the nominal level; and a controller to affect operation of the read pointer dependent on the write address of the write pointer, the read address of the read pointer, and the nominal level, wherein the controller is operable to: determine an amount of data in the buffer circuit based on a difference between the write address and the read address, cause the read pointer to increase the read address in advance of the read clock signal responsive to the amount of data being greater than the nominal level, and wherein the controller is configured to adjust the read pointer independently of the read clock signal.