Patent ID: 7676776

Claim:
A method for determining gate array distribution, the method comprising steps of: using a logic macro to perform analysis of spare gate array cells, using a computer, wherein a logic macro is a physical entity including control logic, wherein the analysis comprises: randomly placing a plurality of virtual test boxes in a logic circuit layout; counting the number of gate array cells in each of the plurality of virtual test boxes; recording the count and its location in a storage device; grouping the plurality of virtual test boxes into two groups: a first group with local clock buffers, and a second group without local clock buffers; determining a gate array cell percentage of each of the plurality of virtual test boxes, wherein said gate array cell percentage comprises a density of the gate array cells in the virtual test box; comparing the determined gate array cell percentage with pre-determined criteria for distribution of gate array cells; and flagging the test boxes with a poor distribution of gate array cells.