Patent ID: 8723844

Claim:
A display device comprising: a display area that includes a plurality of elongated gate lines; and a gate lines driver block that is connected to respective first ends of the elongated gate lines and includes a plurality of stages each configured to provide a gate voltage to a respective one of the gate lines, wherein a current stage among the stages includes a first inverter that is configured to operate in synchronism with a first clock signal supplied to the current stage, wherein the current stage further includes a second inverter that is configured to operate in synchronism with a second clock signal supplied to the current stage, wherein a phase of the second clock signal is opposite to a phase of the first clock signal, wherein the second inverter receives a gate voltage of a next stage that is also provided to a gate line of the plurality of elongated gate lines, wherein the first inverter receives a gate voltage of the current stage, wherein the current stage further includes an outputting circuit configured to output a gate voltage having at least one of a predetermined gate turn on voltage level (VGon) and a predetermined gate turn off voltage level (VGoff) in accordance with a controlled node that is controlled by both the first inverter and the second inverter, wherein the first inverter includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the second inverter includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein a control terminal of the first transistor and an input terminal of the first transistor receive the first clock signal, and an output terminal of the first transistor is connected to an input terminal of the second transistor, wherein a control terminal of the second transistor receives the gate voltage of the current stage, and an output terminal of the second transistor receives a low voltage, wherein a control terminal of the third transistor is connected to the output terminal of the first transistor, an input terminal of the third transistor receives the first clock signal or the second clock signal, and an output terminal of the third transistor is connected to an input terminal of the fourth transistor, wherein a control terminal of the fifth transistor and an input terminal of the fifth transistor receive the second clock signal, and an output terminal of the fifth transistor is connected to an input terminal of the sixth transistor, wherein a control terminal of the sixth transistor receives the gate voltage of the next stage, and an output terminal of the sixth transistor receives the low voltage, and wherein an input terminal of the seventh transistor is connected to the input terminal of the fifth transistor, and an output terminal of the seventh transistor is connected to an input terminal of the eighth transistor.