Patent ID: 8189375

Claim:
A method of programming a memory cell, comprising: providing a memory cell which contains a transistor; the transistor including a transistor gate spaced from a channel region by a gate dielectric, including a first source/drain region on one side of the channel region, and including a second source/drain region on an opposing side of the channel region from the first source/drain region; utilizing the first source/drain region as a source and the second source/drain region as a drain to induce one memory state of the memory cell; and utilizing the second source/drain region as a source and the first source/drain region as a drain to induce another memory state of the memory cell; wherein: the channel region comprises a first volume of programmable material adjacent the first source/drain region; the channel region comprises a second volume of programmable material adjacent the second source/drain region; and the channel region comprises non-phase change material between the first and second volumes.