Patent ID: 7091117

Claim:
A method of fabricating a semiconductor device, comprising the steps of: sequentially forming a polysilicon layer, a first insulating layer, and a photoresist layer over a gate insulating layer positioned on a semiconductor substrate; forming a photoresist pattern with a first groove by selectively patterning the photoresist layer to partially expose a surface of the first insulating layer; forming a second insulating layer over the photoresist pattern with the first groove and over the exposed surface of the first insulating layer; forming a sacrificial spacer on each inner wall of the first groove by etching back the second insulating layer and forming a second groove in the first insulating layer in communication with the first groove to expose a surface of the polysilicon layer at the bottom of the second groove; removing the photoresist pattern; forming an oxide layer pattern over the polysilicon layer at the bottom of the second groove; removing the sacrificial spacers and first insulating layer; and forming a gate electrode by etching the polysilicon layer using the oxide layer pattern as a mask.