Patent ID: 8779961

Claim:
A system comprising: a clock generator configured to generate a clock; a plurality of analog-to-digital converters, wherein each analog-to-digital converter of the plurality of analog-to-digital converters is respectively configured to convert a signal based on the clock, and output a first number of bits in response to converting the signal based on the clock; an averaging module configured to receive the first number of bits respectively output from each analog-to-digital converter of the plurality of analog-to-digital converters, and output a second number of bits, wherein the second number of bits is greater than the first number of bits; an additional analog-to-digital converter configured to convert the signal based on the clock; a detection module configured to detect when one of the plurality of analog-to-digital converters is defective; and a disconnection module configured to (i) disconnect the defective one of the plurality of analog-to-digital converters from the averaging module and (ii) connect the additional analog-to-digital converter to the averaging module in response to disconnecting the defective one of the plurality of analog-to-digital converters from the averaging module, wherein a first analog-to-digital converter of the plurality of analog-to-digital converters is configured to convert the signal based on a plurality of voltage ranges generated using a first set of capacitances in a first order, wherein a second analog-to-digital converter of the plurality of analog-to-digital converters is configured to convert the signal based on the plurality voltage ranges generated using a second set of capacitances in a second order, wherein the first set of capacitances and the second set of capacitances have a predetermined capacitance and are arranged in a predetermined order, and wherein the first order is different than the second order.