Patent ID: 7184358

Claim:
A semiconductor memory comprising: a memory array having a plurality of dynamic memory cells connected to a plurality of word lines, respectively; a boost voltage generator for generating a constant boost voltage as a high-level voltage of said word lines by using an external supply voltage, the boost voltage being higher than the external supply voltage; a plurality of first word decoders for decoding a first address signal in an active period during which said memory cells are accessed in response to an access request and a refresh request, outputting a low-level voltage when said first address signal indicates selection, outputting a high-level voltage when said first address signal indicates deselection, and outputting the high-level voltage in a standby period which is a period excluding said active period; a switch circuit, while in operation in a first specification, connecting a high-level voltage line with a boost voltage line in a first period including at least said active period, and connecting the high-level voltage line with an internal voltage line in a period excluding the first period, the high-level voltage line being for supplying the high-level voltage to said first word decorders, the boost voltage line being an output node of said boost voltage generator, the internal voltage line being supplied with a voltage lower than the boost voltage; and a plurality of word drivers formed in correspondence with said word lines, respectively, and each provided with a transistor, for outputting the boost voltage to said word lines when each transistor receives the low-level voltage at its gate from said first word decoders, and outputting the low-level voltage to said word lines when the each transistor receives the high-level voltage at its gate from said first word decoders.