Patent ID: 7844435

Claim:
An integrated circuit chip comprising: an integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and simulation modeling, wherein the RLC extraction and simulation modeling comprises the steps of: performing an RL extraction process which employs a two dimensional (2-D) scan line algorithm which is used to determine coordinates of return path conductors' power and signal shapes whose length is perpendicular to a scan line by scanning in both x and y directions for both voltage and ground in a radius on said chip determined by a user defined parameter for a power shape radius; within a user determined signal radius on said scan line locating adjacent signal conductors; and employing a scan line two dimensional (2-D) approximation of conductor shapes for parallel wiring for all planes where parallel wiring with respect to a target net exists for said return path conductors and said signal conductors; and wherein for pair adjacencies within said signal radius a two dimensional (2-D) RL field solver resistance inductive calculation is performed using resistance and induction information to determine a best fit at multiple frequency points and wherein said field solver resistance inductive calculation provides multiple RL extraction results for each frequency as frequency dependent RL parameters; caching and reusing synthesized circuits based on calculations using said frequency dependent RL parameters as a method to reduce calculation duplication of extracted shapes when identical physical data for 2-D cross-section shapes results from use of the scan line algorithm; wherein frequency dependent RLC circuits for non-monotonic resistance frequency variation are synthesized by approximating a complex impedance function by a ration of polynomials as representative stable circuits; and wherein circuit netlisting procedures include circuit synthesis results as pair-wise coupling interactions; and wherein circuit netlisting procedures include management of return path nodes of circuit synthesis results and referencing between input/output nodes of pair-wise coupling interactions and finding a set of poles and residues using resistance and inductance information using only real poles in a portion of a complex plane band in which circuit elements are realizable.