Patent ID: 8446193

Claim:
A clock conditioning circuit comprising: a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock; a controlled oscillator configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator; mode control circuitry switchable between at least two modes, including a tracking mode and a holdover mode, with the mode control circuitry operating in the tracking mode to couple the analog tuning signal to the control signal input of the controlled oscillator and with the mode control circuitry operating in the holdover mode to couple an analog holdover signal to the control signal input of the controlled oscillator; and converter circuitry configured to produce a digital representation of the analog tuning signal when the mode control circuitry is in the tracking mode and to provide the analog holdover signal to the control signal input when the mode control circuitry is in the holdover mode, with the analog holdover signal being based upon one of the digital representations produced when the mode control circuitry was in the tracking mode.