Patent ID: 7799628

Claim:
A method of fabricating a semiconductor device comprising: forming a high-k dielectric layer over a semiconductor substrate, the semiconductor substrate having a first region and a second region; forming a first metal layer over the high-k dielectric layer; forming a second metal layer over the first metal layer; forming a first silicon layer over the second metal layer; implanting a plurality of ions into the first silicon layer and the second metal layer overlying the first region of the substrate; forming a second silicon layer over the first silicon layer; patterning a first gate structure over the first region and a second gate structure over the second region, the first and second gate structures each including the high-k dielectric layer, the first metal layer, the second metal layer, the first silicon layer, and the second silicon layer; and performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively; wherein forming the silicide layer in the first gate structure drives the plurality of ions toward an interface of the first metal layer and the high-k dielectric layer in the first gate structure.