Patent ID: 8498855

Claim:
A circuit simulation apparatus comprising: a parameter calculating tool configured to extract a source-side gate spacing and a drain-side gate spacing of a target MOS transistor integrated in an integrated circuit from layout data of said integrated circuit, to calculate from said source-side gate spacing and said drain-side gate spacing, a parameter modification amount which is a modification amount of a transistor model parameter corresponding to a threshold voltage of said target MOS transistor, and to calculate said transistor model parameter corresponding to the threshold voltage of said target MOS transistor by modifying said transistor model parameter in accordance with said parameter modification amount, wherein said source-side gate spacing is a gate spacing between a gate of said target MOS transistor and a gate of a source-side MOS transistor integrated in said integrated circuit and said drain-side gate spacing is a gate spacing between the gate of said target MOS transistor and a gate of a drain-side adjacent MOS transistor integrated in said integrated circuit; and a circuit simulator configured to perform circuit simulation of said integrated circuit by using said calculated transistor model parameter, the parameter calculating tool and the circuit simulator are realized as a program stored in a non-transitory computer-readable recording medium of the circuit simulation apparatus.