Patent ID: 8508276

Claim:
A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node, wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter, wherein one of a source and a drain of the first transistor is electrically connected to the node, wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter, wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter, wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter, wherein the other of the source and the drain of the second transistor is electrically connected to the node, and wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor.