Patent ID: 8198720

Claim:
A stacked system of microelectronic die packages, comprising: a first die package having a first bottom side, the first die package comprising a first microelectronic die; a first dielectric casing at least partially covering the first die; and individual first metal leads coupled to the first die and having a first exterior surface; a second die package having a second bottom side and a top side adjacent to the first bottom side of the first package, the second die package comprising a second microelectronic die; a second dielectric casing at least partially covering the second die and having a lateral side; individual second metal leads coupled to the second die and having a second exterior surface and an interior surface region that generally faces the lateral side, wherein the individual second leads are at least generally aligned with the individual first leads and project, at least in part, towards the first package; and a package bond pad at the second bottom side and electrically coupled to the second die and to at least one of the second metal leads; external inter-package connectors coupling a first portion of individual first exterior surfaces with a second portion of individual second exterior surfaces; an interposer substrate adjacent to the second bottom surface, the interposer substrate having a substrate bond pad; and a bond pad connector attached to each of the package bond pad and the substrate bond pad.