Patent ID: 8471334

Claim:
A semiconductor device comprising: a channel formation region of first conductivity type; a first offset region of second conductivity type; a first insulating region buried in the surface of the first offset region; a first liner layer provided between the first offset region and the first insulating region, the first liner layer being formed of a conductive material and to be in contact with the first offset region; a first semiconductor region of second conductivity type provided on a side opposite to the channel formation region so as to sandwich the first insulating region therebetween and having impurity concentration higher than that of the first offset region; a second semiconductor region of second conductivity type provided on a side opposite to the first semiconductor region so as to sandwich the channel formation region therebetween and having impurity concentration higher than that of the first offset region; a gate insulating film provided on the channel formation region and the first offset region; and a gate electrode provided on the gate insulating film.