Patent ID: 7217586

Claim:
A method of fabricating a thin film transistor array substrate, comprising: forming a first conductive pattern group including a gate line, a gate pad, and a gate electrode of a thin film transistor, the thin film transistor connected to the gate line on a substrate; forming a gate insulating film on the substrate including the first conductive pattern group; forming a second conductive pattern group including a data line crossing the gate line, a source electrode of the thin film transistor connected to the data line, and a drain electrode of the thin film transistor, an ohmic contact layer, and a semiconductor layer for forming a channel region of the thin film transistor; forming a third conductive pattern group including a transparent electrode material connected to the drain electrode; etching the ohmic contact layer using the source and drain electrodes as a first etch mask; and etching the gate insulating film using the second and the third conductive pattern groups as a second etch mask, wherein the etching of the ohmic contact layer and the etching of the gate insulating film are performed simultaneously.