Patent ID: 7312113

Claim:
A method of forming a source/drain region of a semiconductor device, the method comprising: providing a semiconductor substrate in which a PMOS region including a first gate electrode pattern having a first gate oxide film and an NMOS region including a second gate electrode pattern having a second gate oxide film are defined; forming a first ion implant barrier insulation film over the semiconductor substrate in which the first and the second electrode patterns are formed, forming a photoresist pattern that exposes the NMOS region; performing a first ion implant process to form NMOS LDD regions in the NMOS region; performing a first strip process that strips the photoresist pattern and removes the first ion implant barrier insulation film of the NMOS region to a predetermined thickness to form a second ion implant barrier insulation film over the NMOS region; exposing the PMOS region, and then performing a second ion implant process to form PMOS pocket regions in the PMOS region; forming spacers on sidewalls of the first gate electrode pattern and sidewalls of the second gate electrode pattern; forming PMOS source/drain regions in the semiconductor substrate in which the PMOS pocket regions are formed by performing a third ion implant process to the PMOS region on which the first ion implant barrier insulation film is formed; and forming NMOS source/drain regions in the semiconductor substrate in which the NMOS LDD regions are formed by performing a fourth ion implant process to the NMOS region on which the second ion implant barrier insulation film is formed.