Patent ID: 8775841

Claim:
A circuit system for a node of a bus system, comprising: a transceiver circuit configured to selectively operate in at least an idle mode and in an operating mode, wherein the transceiver circuit has a lower power consumption in the idle mode in comparison to the operating mode, and wherein the transceiver circuit is supplied with power via a power supply unit integrated into the transceiver circuit; a control circuit connected to the transceiver circuit, wherein the control circuit is connected to the power supply unit for supplying power to the control circuit in the idle mode; a controllable voltage regulator coupled to the transceiver circuit, wherein the voltage regulator is (i) selectively deactivated in the idle mode to reduce power consumption and (ii) selectively activated in the operating mode to supply power to the transceiver circuit and the control circuit; and a controllable switch element situated between an output of the voltage regulator and an output of the power supply unit, wherein the controllable switch element is coupled to a trigger element for triggering the switch element, and wherein the output of the power supply and the output of the voltage regulator are electrically separated from one another by the switch element when the controllable voltage regulator is deactivated and the transceiver circuit is supplied with power via a power supply unit integrated into the transceiver circuit.