Patent ID: 8350331

Claim:
A semiconductor device, comprising: insulating gate type first and second transistors formed on an SOI substrate composed of a semiconductor support substrate, a buried insulating film and a semiconductor layer in the stated order, wherein said semiconductor layer includes first and second SOI regions having first and second film thicknesses, respectively, and said first film thickness is greater than said second film thickness, said first and second transistors are formed in the first and second SOI regions, and each comprises: a gate insulating film selectively formed on said semiconductor layer; a gate electrode formed on said gate insulating film; source/drain regions formed in said semiconductor layer to sandwich a body region, which is a region of said semiconductor layer beneath said gate electrode, and said source/drain regions reaching to said buried insulating film, wherein said source/drain regions in said first transistor have a recess structure where the level of the surface thereof is lower than the level of the surface of said body region, and said source/drain regions in said second transistor do not have said recess structure; a third transistor formed in said first SOI region, wherein said third transistor comprises, a gate insulating film selectively formed on said semiconductor layer, a gate electrode formed on said gate insulating film, and source/drain regions formed in said semiconductor layer to sandwich the body region which is a region of said semiconductor layer beneath said gate electrode and not to have said recess structure and to leave a portion of said semiconductor layer beneath without penetrating thorough said semiconductor layer; each of said first to third transistors comprises, a body contact region in which a body potential is provided, and a partial isolation region composed of an insulator formed in an upper layer part of said semiconductor layer and a partial semiconductor region in the semiconductor layer which is a layer beneath the insulator, wherein said body contact region is electrically connected to said body region via said partial semiconductor region in said partial isolation region.