Patent ID: 6838915

Claim:
An input and output circuit of a semiconductor device, comprising: a control signal generating means for generating a first control signal of a power supply voltage, a second control signal of a ground voltage and a third control signal of a high voltage greater than the power supply voltage, respectively, when the high voltage is applied to a pad of the semiconductor device under a power on condition of the semiconductor device, and generating the first and the second control signals having substantially the same voltages as the power supply voltage and the third control signal of the high voltage, respectively, when the high voltage is applied to the pad of the semiconductor device under a power off condition of the semiconductor device; an output buffer including first and second pull-up transistors connected in series between the power supply voltage and the pad, first and second pull-down transistors connected in series between the pad and the ground voltage, a pre-driver for pulling up or down a voltage of the pad in response to an input signal when an output enable signal is enabled and for switching off the first and second pull-up transistors and the first and second pull-down transistors when the output enable signal is disabled, and a first tolerance and current blocking means for adjusting voltage differences between respective gates and respective sources/drains of the first and second pull-up transistors and the first and second pull-down transistors to be below a predetermined voltage level in response to the first, second and third control signals, and preventing current flow from the pad to the power supply voltage if the high voltage is applied to the pad under power on or power off conditions; and an input buffer including a transmission gate for transmitting an input signal applied to the pad to a first node in response to the first control signal, a third, a fourth and a fifth pull-up transistors connected in series between the power supply voltage and a second node and having corresponding gates connected to a third node, the pad and the first node, respectively, a third pull-down transistor connected between the second node and the ground voltage and having a gate connected to the first node, a second tolerance and current blocking means for adjusting voltage differences between respective gates and respective sources/drains of the third, fourth and fifth pull-up transistors and the third pull-down transistor to be below a predetermined voltage in response to the first and third control signals, and preventing current flow from the pad to the power supply voltage if the high voltage is applied to the pad under either the power on or power off conditions.