Patent ID: 7826351

Claim:
A computer-implemented system, comprising: a processor; and a network interface in communication with the processor; wherein the processor is configured to minimize latency in data communication in network traffic based upon an inter-arrival time of individual data packets at the network interface by: a) applying a 2-state Markov modulated Poisson process (MMPP) algorithm useful for determining whether the packet arrival rates are ‘bursty’ (λ 1 ) representing heavy traffic conditions or ‘idle’ (λ 2 ) representing light traffic conditions to network traffic at the network interface; b) wherein a transition window [λ 1 max , λ 2 min ] is represented by boundary values λ 1 max for the inter-arrival time for bursty traffic, and λ 2 min for the inter-arrival time for idle traffic, c) wherein the processor is configured to determine a probability ρ 1 that a packet inter-arrival time is occurring in bursty traffic or a probability ρ 2 that the arrival time is occurring in idle traffic, and d) wherein the processor is configured to, based upon said probability ρ 1 or ρ 2 determination, either block or poll a transfer of data packets.