Patent ID: 7166513

Claim:
A method for fabricating a flash memory cell array, comprising: providing a substrate having a device insulating structure; forming a plurality of stack gate structures on said substrate, and said stack gate structure including a select gate dielectric layer, a select gate, and a gate cap layer, wherein said select gate dielectric layer being formed between said substrate and said select gate, said gate cap layer being formed on said select gate; forming a tunneling dielectric layer on said substrate; forming a spacer along a sidewall of said select gate; forming a floating gate between each of said stack gate structures, wherein said floating gate includes a recess and connected to said stack gate structure, and an upper sidewall of the floating gate is defined as between a top surface of said gate cap layer and a top surface of said select gate; forming an inter-gate dielectric layer on said floating gate; forming a control gate to fill at least one gap between each of said stack gate structures; removing a portion of said stack gate structures excluding a predetermined area of said flash memory cell array; and forming a drain region and a source region in said substrate, said drain region and said source region being on the one side and the other side out of said control gates and said stack gate structures respectively.