Patent ID: 8219379

Claim:
A test system for testing software to be run on a data processing apparatus having a plurality of processors configured to share access to a memory system, at least a part of the memory system having a memory ordering type specifying at least one ordering freedom which allows memory access requests to that part to be processed out of order from an original program order, the test system comprising: a processor simulator for each processor of the data processing apparatus, each processor simulator being configured to execute a sequence of instructions in program order; at least one access buffer unit, each access buffer unit being associated with one of the processor simulators and being configured to receive memory access requests issued by that processor simulator when executing memory access instructions within the sequence of instructions; each access buffer unit comprising: at least one buffer configured to store memory access requests issued by the associated processor simulator; and a controller configured to select an eviction policy, and to apply that selected eviction policy to determine an order in which the memory access requests are output from the access buffer unit to the memory system; the eviction policy being selected such that when the controller applies that selected eviction policy, the at least one ordering freedom specified by the memory ordering type of said part of the memory system is exercised in a manner compliant with the memory ordering type but to a degree exceeding that expected within the data processing apparatus.