Patent ID: 7460634

Claim:
A shift register circuit comprising a plurality of stages, each stage comprising: a first input (R n−1 ) connected to the output of the preceding stage; a drive transistor (T drive ) for coupling a first clocked power line voltage (P n ) to the output (R n ) of the stage; a compensation capacitor (C 1 ) for compensating for the effects of a parasitic capacitance of the drive transistor; a first bootstrap capacitor (C 2 ) connected between the gate of the drive transistor and the output (R n ) of the stage; and an input transistor (T in1 ) for charging the first bootstrap capacitor (C 2 ) and controlled by the first input (R n−1 ), wherein each stage further comprises an input section ( 10 ) coupled to the output (R n−2 ) of the stage two stages before the stage, and wherein the input section comprises a second bootstrap capacitor (C 3 ) connected between the gate of the input transistor (T in1 ) and the first input (R n−1 ).