Patent ID: 7193624

Claim:
A display apparatus comprising: a display module; and a power control unit coupled electrically to said display module, said power control unit including an alternating current-to-direct current converter adapted to be connected electrically to an external power source so as to receive an alternating current power therefrom, said converter providing a direct current output, a regulator connected electrically to said alternating current-to-direct current converter and having a power input end for receiving the direct current output from said alternating current-to-direct current converter, a control input end, and an output end, said regulator being operable in one of an enabled state, where said regulator outputs a target direct current power at said output end when said control input end receives a first level signal, and a disabled state, where said regulator does not output the target direct current power at said output end when said control input end receives a second level signal, a delay circuit connected electrically to said alternating current-to-direct current converter and said control input end of said regulator, said delay circuit being capable of outputting one of the first and second level signals to said regulator, a processor connected electrically to said output end of said regulator, said delay circuit and said display module, and an electronic switch connected electrically to said delay circuit and said processor, said electronic switch being operable for switching from an OFF-mode, where said processor permits said delay circuit to output the second level signal to said regulator such that said regulator is operated in the disabled state, to an ON-mode, where said electronic switch initially enables said delay circuit to output the first level signal to said control input end of said regulator such that said processor receives the target direct current power from said regulator and where said electronic switch outputs a trigger signal to said processor so as to enable said processor to latch the first level signal outputted by said delay circuit and to provide the target direct current power to said display module.