Patent ID: 7444564

Claim:
A method for implementing at speed bit fail mapping of an embedded memory system having a BIST (Built In Self Testing) engine, comprising: using a high speed multiplied clock which is an asynchronous multiple of a slower external clock of a tester to sequence BIST bit fail testing of the embedded memory system, said BIST generating a fail map data including all diagnostic fails for capture by a diagnostic register device under control of said high speed multiplied clock, the diagnostic fail data being stored in fail location latches of said diagnostic register device at a time of recognizing said BIST fail test; generating a signal for receipt by said tester to identify a BIST bit fail test for said tester, and; in response to said generated signal, implementing a BIST clock control logic for automatically pausing the BIST bit fail testing upon recognition of a fail of the embedded memory system, said BIST clock control logic gating off said high speed multiplied clock to BIST test latches and fail location latches of said diagnostic register; receiving, from said tester, a first signal asserted in response to receiving said generated signal; said BIST clock control logic automatically switching, in response to said received asserted first signal, said diagnostic register device to operate from a data capture mode controlled by the high speed multiplied clock to a serial transfer mode controlled by the slower external clock of the tester; using the slower external clock of the tester to read bit fail data out from said fail location latches of said diagnostic register device to the tester; and, receiving, from said tester, a de-asserted first signal when all fail data out from said fail location latches of said diagnostic register device are read; automatically switching, in response to said received de-asserted first signal, said BIST clock control logic to resume data capture at said fail location latches of said diagnostic register device at said high speed multiplied clock; and, resuming the BIST testing with the high speed multiplied clock from the point at which it was paused, wherein diagnostic bit fail data is extracted from said diagnostic register device without disturbing a state of said BIST or said embedded memory.