Patent ID: 7091710

Claim:
A low dropout voltage regulator comprising: an unregulated DC input terminal; a regulated DC output terminal, supplying an output current to an output load, wherein said output load is coupled from said regulated DC output terminal to a reference ground level; an output pass transistor, supplying power to said regulated DC output terminal, wherein said output pass transistor has a source coupled to said unregulated DC input terminal, and said output pass transistor has a drain connected to said regulated DC output terminal; an error amplifier, for controlling a gate of said output pass transistor; a bias transistor, coupled between an output of said error amplifier and said gate of said output pass transistor, wherein a drain of said bias transistor is coupled to said gate of said output pass transistor; a compensation network, coupled between said gate and said drain of said output pass transistor for frequency compensation; a mirror transistor, for generating a mirror current in proportion to said output current, wherein a source of said mirror transistor is coupled to said source of said output pass transistor, wherein a gate of said mirror transistor is coupled to said gate of said output pass transistor, wherein said mirror current is generated form a drain of said mirror transistor; a first programmable current source, generating a first-mirror current in proportion to said mirror current; a first-mirror transistor, for programming the impedance of said compensation network in response to said first-mirror current, wherein a gate and a drain of said first-mirror transistor are coupled to each other to form a current mirror, wherein said drain of said first-mirror transistor is coupled to said first programmable current source; a second programmable current source, generating a second-mirror current in proportion to said mirror current; and a second-mirror transistor, for programming the impedance of said bias transistor in response to said second-mirror current, wherein a source of said second-mirror transistor and a source of said bias transistor are coupled to said output of said error amplifier, wherein a gate of said bias transistor, a gate of said second-mirror transistor and a drain of said second-mirror transistor are coupled to said second programmable current source.