Patent ID: 7318127

Claim:
A method in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor, said SMT processor executing said multiple threads concurrently during each clock cycle, said method comprising: dynamically allocating said cache for use among said multiple threads; portions of said cache capable of being designated to store private data that is used exclusively by only a first one of said multiple threads; said portions of said cache capable of being designated to store shared data that is used by any one of said multiple threads; changing a size of said portions dynamically during execution of said multiple threads; storing a shared mode bit; said shared mode bit indicating whether data to be stored in said cache is to be shared among said multiple threads; said cache being an array that includes a plurality of different columns and a plurality of different rows; associating a different shared mode bit with each one of said plurality of different rows; and one of said shared mode bits indicating whether data that is stored in one of said plurality of rows that is associated with said one of said shared mode bits is to be shared among said multiple threads.