Patent ID: 8279681

Claim:
A method of using a nonvolatile memory array comprising: providing the nonvolatile memory array comprising: a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, wherein: the first memory cell is along a first row and a first column; the second memory cell is along the first row and a second column; the third memory cell is along a second row and the first column; and the fourth memory cell is along the second row and the second column; and each of the first, second, third and fourth memory cells includes: a capacitor having a first electrode and a second electrode; a tunnel structure having a first electrode and a second electrode; a state transistor including a source region, a drain region, and a gate electrode; and an access transistor including a source region, a drain region, and a gate electrode, wherein: a floating gate electrode includes the gate electrode of the state transistor, the second electrode of the capacitor, and the second electrode of the tunnel structure; and the source region of the access transistor is coupled to the drain region of the state transistor; and during a first erase pulse, erasing the first and second memory cells without significantly disturbing data within the third and fourth memory cells.