Patent ID: 8645877

Claim:
A method comprising: (a) receiving data representing a layout of a multi-patterned layer (DPT-layer) of an integrated circuit generated by a computer implemented place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving an identification of a first polygon within the plurality of polygons and a second polygon within the plurality of polygons, where the first and second polygons are both to be formed using a single first photomask; (c) identifying any intervening polygons of the plurality of polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path; (d) counting the separator regions; and (e) identifying a multi-patterning conflict if the count of separator regions along the first path is odd, prior to assigning all remaining ones of the plurality of polygons to the first photomask or to a second photomask to be used in the multi-patterning process.