Patent ID: 7553731

Claim:
A method of manufacturing a semiconductor device having a cell region having a vertical semiconductor switching cell group formed therein and a peripheral region located on a periphery of the cell region, comprising: preparing a semiconductor laminate of a first conductivity-type semiconductor layer and a first conductivity-type semiconductor substrate, a concentration of first conductivity-type impurities of the semiconductor layer being lower than the semiconductor substrate; forming a trench group extending from an upper surface of the semiconductor layer to a back surface of the semiconductor layer to form plural sections of the semiconductor layer such that a distance between opposite sides of each one of the sections formed at the peripheral region is so long that impurities cannot be doped deeply and a distance between opposite sides of each one of sections formed at a region other than the peripheral region is so short that impurities can be doped deeply; doping first conductivity-type impurities to an exposed surface of the semiconductor layer so that concentration of the first conductivity type impurities of the sections formed at a region other than an outermost portion of the peripheral region becomes higher than the semiconductor layer at the stage that they are prepared and lower than the substrate layer at the stage that they are prepared; removing a surface neighboring region of the semiconductor layer doped with the first conductivity-type impurities formed on the upper surface of the semiconductor layer; and filling a semiconductor material including second conductivity-type impurities into the trench group.