Patent ID: 7178071

Claim:
A device for detecting a delay time of a circuit, comprising: a feeder for feeding a test signal into the circuit, said test signal including a signal edge, the occurrence of which is related to a reference time; a sampler for sampling an output signal of the circuit at predetermined times to obtain a sequence of sample values, each sample value having an associated time duration equal to a time interval between adjacent predetermined times, a first state being associated with a sample value when said output signal has a first signal value and a second state being associated with a sample value when said output signal has a second signal value; a counter for counting said sample values of said sequence, to which an equal state is associated, starting from said reference time or from another reference time, the time interval of which to said reference time being known, to obtain counted sample values; and a calculator for calculating the delay time, said calculator calculating the delay time using at least one of: (a) a sum of the predetermined time durations associated with the counted sample values, (b) a sum of the predetermined time durations associated with the counted sample values and the another reference time, and (c) a sum of the predetermined time durations associated with the counted sample values and the time interval.