Patent ID: 6965923

Claim:
A memory system comprising: a plurality of memory devices associated with only one processor, with each memory device comprising: (a) an array of memory cells; (b) an addressing circuitry operatively coupled to the array of memory cells, wherein the addressing circuitry is capable of providing addresses to the array of memory cells; (c) a memory device bus interface; (d) a command decoder which decodes commands at the memory device bus interface, including an address assign command; and (e) a local address storage circuitry which stores a local address for identifying the storage circuitry's single associated memory device once the address assign command is decoded by the command decoder; and a memory controller having a controller bus interface coupled to the memory device bus interface, with the memory controller providing the local address to be stored in the local address storage circuitry of the memory device of the memory system together with the address assign command.