Patent ID: 7480874

Claim:
A method for designing an integrated circuit comprising the steps, performed by a data processing unit including a processor and a memory, of: obtaining a circuit data file in the form of a connectivity network with appended parasitic information; simulating circuit performance, based on said connectivity network with said appended parasitic information, to obtain results including simulated currents for discretized representations of metallic conductive paths; determining contextual representations of said metallic conductive paths based on said discretized representations; and performing reliability analysis on said contextual representations of said metallic conductive paths to determine whether a design for the integrated circuit meets reliability criteria; wherein: said contextual representations comprise representations of said metallic conductive paths as substantially integral entities with substantially accurate dimensions and geometries, upon which said reliability analysis can be conducted; said discretized representations comprise representations of said metallic conductive paths as discrete elements; and said appended parasitic information comprises at least one of parasitic resistances and parasitic capacitances of said metallic conductive paths.