Patent ID: 7783795

Claim:
A serial communication circuit that performs full duplex serial communication with a microcomputer based on a clock signal output from the microcomputer, the serial communication circuit comprising: a first register that loads first serial data in response to a first load signal, the first serial data being output from the microcomputer synchronously with the clock signal; first means that performs processing based on the loaded first serial data; second means that outputs a synchronous signal to the microcomputer at a first time interval greater than a transmission time of the first serial data, the synchronous signal causing the microcomputer to output next first serial data; a second register that loads second serial data in response to a second load signal, the second serial data being generated based on a result of the processing; third means that outputs the loaded second serial data to the microcomputer in response to the second load signal; a counter circuit that is incremented by each pulse of the clock signal and outputs the first load signal to the first register when reaches the number of bits of the first serial data, the counter circuit being reset in response to the second load signal; and a timer circuit that starts to count after the counter circuit outputs the first load signal for the first time and continues to count during the serial communication, the timer circuit expiring at a second time interval that is greater than the transmission time of the first serial data and shorter than a transmission interval of the first serial data, wherein the timer circuit outputs the second load signal each time the timer circuit expires.