Patent ID: 7344920

Claim:
A process for fabricating an integrated circuit package comprising: selectively etching a first side of a substrate thereby providing etched regions of said substrate to partially define at least a plurality of contact pads; adding a dielectric material to said etched regions of said substrate; selectively etching a second side of said substrate to further define the plurality of contact pads and thereby provide a package base of at least the contact pads and said dielectric; wherein selectively etching said second side of said substrate comprises: providing a plating resist on selected portions of said second side of said substrate; plating said etch-resist on said second side of said substrate, between said selected portions of said second side of said substrate; stripping said plating resist to expose said selected portions of said second side of said substrate; and etching said selected portions of said second side of said substrate, mounting a semiconductor die to said package base and connecting said semiconductor die to said contact pads; fixing a lid to said package base to cover said semiconductor die in a cavity between said lid and said package base; and singulating to provide said integrated circuit package.