Patent ID: 8296519

Claim:
A processing unit for a data processing system including multiple processing units, said processing unit comprising: a store-in lower level cache including reservation logic that determines presence or absence of a reservation with respect to the multiple processing units; and a processor core including: a store-through upper level cache; an instruction execution unit; a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation; and a flag; wherein the processor core, if a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.