Patent ID: 7425856

Claim:
A phase interpolator adapted to generate a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, wherein interpolation angle of the output clock signal Z is based on an applied weight value W, the phase interpolator comprising A-side circuitry and B-side circuitry connected to the A-side circuitry, wherein: the A-side circuitry is adapted to receive the input clock signal A; the B-side circuitry is adapted to receive the input clock signal B; the output clock signal Z is presented at an output node of the phase interpolator; and each of the A-side circuitry and the B-side circuitry comprises: a current source array comprising a plurality of parallel current sources; a switch block comprising a plurality of switches, each switch connected in series to a corresponding current source; and an encoder adapted to control the switches in the switch block based on the weight value W, such that total current through the phase interpolator varies with the interpolation angle of the output clock signal Z.