Patent ID: 7113426

Claim:
A non-volatile memory array, comprising: a plurality of memory cells, each cell receiving a bit line, word line, and release line; each memory cell including a cell selection transistor with first, second and third nodes, the first and second nodes being in respective electrical communication with the bit line and the word line, each cell further including an electromechanically deflectable switch, having a first, second and third node, the first node being in electrical communication with the release line, and a third node being in electrical communication with the third node of the cell selection transistor, the electromechanically deflectable switch including a nanotube switching element physically positioned between the first and third nodes of the switch and in electrical communication with the second node of the switch and wherein the second node of the switch is in communication with a reference signal; wherein each nanotube switching element is deflectable into contact with the third node of the switch in response to signals at the first and second nodes of the cell selection transistor and is releasable from such contact in response to a signal at the release line.