Patent ID: 8250322

Claim:
A control system for memory access, comprising: a system memory access command buffer, for temporarily storing a plurality of system memory access commands; a memory access command parallel processor, connected to the system memory access command buffer, for fetching and decoding the system memory access commands respectively to a plurality of DRAM access commands, temporarily storing the DRAM access commands in DRAM bank command FIFOs, and performing a process of priority setting for the DRAM access commands according to a DRAM bank priority table; a DRAM command controller, connected to the memory access command parallel processor and a DRAM, for receiving the DRAM access commands with the process of priority, and sending control commands accessed by the DRAM to the DRAM according to the order of the DRAM access commands received; and a read data buffer, connected to the DRAM command controller and the system bus, for temporarily storing read data from the DRAM and rearranging a sequence of the read data for the system memory commands.