Patent ID: 8171440

Claim:
A timing analyzing apparatus, comprising: a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and a timing analyzing unit which recognizes a clock path between a clock source located outside the partial area and one of two points on the circuits located in the partial area, another clock path located between the clock source and the other point of the two points on the circuits located in the partial area and a common part that exists outside the partial area and is common in the two clock paths; and performs a CRPR calculation between the two points wherein clock delay of the common part is purposefully neglected, to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.