Patent ID: 8627031

Claim:
A semiconductor memory device comprising: a command processor configured to process data in accordance with a data read request and a data write request, and to output processed data; a plurality of storage units; a plurality of controllers connected and corresponding to the plurality of storage units and configured to execute a read operation and a write operation with reference to the storage units; an adjustment module connected between the command processor and the controllers and configured to cause the controllers to execute the read operation and the write operation in accordance with the processed data from the command processor; and a setting register connected to the adjustment module and configured to hold identification data identifying whether each storage unit belongs to a first group for which the write operation is permitted, or to a second group for which the write operation is prohibited, wherein, when the processed data in accordance with the data write request is outputted from the command processor, the adjustment module is configured to exclude the controller connected to the storage unit of the second group from the write operation in accordance with the identification data, and to cause the controller connected to the storage unit of the second group to execute the read operation in a period while the write operation is executed by the controller connected to the storage unit of the first group.