Patent ID: 7190608

Claim:
A resistance variable memory device integrated circuit, comprising: an array of resistance variable memory cells, each resistance variable memory cell being connected to first and second digit lines, each resistance variable memory cell comprising at least four resistance variable memory elements and at least four access transistors, each access transistor being associated with and connected between a respective resistance variable memory element and a sub bit line; a first circuit connected between the first and second digit lines and the sub bit lines of at least one resistance variable memory cell, the first circuit adapted to write the at least one resistance variable memory cell to a first resistance state and erase the cell to a second resistance state; and sensing circuitry connected to the first and second digit lines, the sensing circuitry adapted to sense the state of an addressed memory cell by changing a cell plate potential of the memory elements within the cell and sensing the difference between the first and second digit lines connected to the addressed cell.