Patent ID: 8125068

Claim:
A semiconductor chip comprising: a substrate including an inner semiconductor circuit; a conductive inner circuit interconnection pad and a conductive chip pad disposed on a top surface of the substrate, the conductive chip pad and the conductive inner circuit interconnection pad being formed at the same level, wherein the conductive chip pad is disposed at a center line of the top surface; an upper passivation layer on the conductive inner circuit interconnection pad and the conductive chip pad; a conductive redistribution structure formed on the upper passivation layer, the conductive redistribution structure including a conductive redistribution interconnection and a first and second conductive redistribution via plugs, wherein the first conductive redistribution via plug is connected to the conductive inner circuit interconnection pad; and a conductive chip via plug configured to penetrate the substrate and electrically connect to the conductive redistribution interconnection through the second conductive redistribution via plug, wherein the conductive chip via plug comprises a chip via hole configured to penetrate the substrate, a sidewall barrier layer formed on a sidewall of the chip via hole, and a conductive plug on the sidewall barrier layer configured to fill the chip via hole.