Patent ID: 8446935

Claim:
A fractional rate converting filter in a transmitter comprising: a delay line for receiving from a baseband interface a digital input signal at a first sample rate, the delay line having delay blocks each providing an output, the delay line receiving samples gated at a plurality of clock cycles of an integer sub-multiple frequency of a clock provided by the interface that provides the digital input signal; a multiplier circuit configured to operate at each of the plurality of clock cycles for each input sample for receiving the output of each delay block and multiplying the outputs by corresponding filter tap coefficients, each filter tap coefficient being spaced by a first integer Y, the integer Y corresponding to an upconversion factor, the multiplier circuit providing tap outputs corresponding to each of the outputs and wherein the multiplier circuit is embodied as hardware, as a series of operating instructions configured to direct operation of a processor, or as a combination thereof; an adder circuit for receiving and summing the tap outputs to provide an output signal; and, a selector for iteratively shifting the filter tap coefficients corresponding to each output by a second integer Z in each clock cycle for the plurality of clock cycles at the integer sub-multiple frequency of the clock, wherein, the multiplier circuit is configured to multiply the output of each delay block by corresponding shifted filter tap coefficients in each clock cycle and the delay blocks are inhibited from receiving another input sample during the plurality of clock cycles, the integer Z corresponding to a downconversion factor, the output signal having a second sample rate at the integer sub-multiple frequency of the clock equivalent to the first sample rate multiplied by Y and divided by Z.