Patent ID: 7816176

Claim:
A method of manufacturing an electronic component package, the electronic component package comprising: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip that is bonded to the base and electrically connected to at least one of the external connecting terminals, the method comprising the steps of: fabricating a wafer, the wafer incorporating: a substrate that has a top surface and does not include the electronic component chip; and a plurality of sets of external connecting terminals that correspond to a plurality of electronic component packages and that are provided on the top surface of the substrate, the wafer including a plurality of pre-base portions that will be separated from one another later so that each of them will thereby become the base; bonding at least one electronic component chip to each of the pre-base portions of the wafer; and cutting the wafer so that the pre-base portions are separated from one another and a plurality of bases are thereby formed, the step of cutting the wafer being performed after the step of bonding the at least one electronic component chip to each of the pre-base portions, wherein the step of fabricating the wafer includes the step of forming the plurality of sets of external connecting terminals on the top surface of the substrate by plating, and the step of bonding the at least one electronic component chip to each of the pre-base portions of the wafer is performed after the step of forming the plurality of sets of external connecting terminals.