Patent ID: 8363635

Claim:
A system for reducing power consumption of signal synchronization circuit in an Orthogonal Frequency Division Multiplexing (OFDM) receiver comprising: a sync setting configured to change correlation data sample rate and synchronization parameters setting dynamically according to synchronization statuses and results; a sync pipeline configured to execute signal correlation with scalable synchronization window size, synchronization sequence length, synchronization delay and variable data sample rate, and to execute power on and off requests; and a sync controller configured to control frame and symbol synchronization operation flows, schedule synchronization timing, turns on and off the sync pipeline based on the operation flows, wherein the sync controller turns on power of the sync pipeline and starts symbol synchronization after frame synchronization is complete and a predetermined duration expires, turns off power of the sync pipeline when symbol synchronization is complete, and repeats the cycle until a predetermined number of symbols in a frame have been synchronized, and wherein the sync controller skips a plurality of frame or symbol synchronizations to reduce power consumption of the sync pipeline if averages of coarse timing and fine frequency offsets from a plurality of previous synchronizations are below predetermined thresholds.