Patent ID: 8766697

Claim:
A circuit, comprising: a level shifted signal node; a pull-up path coupled between the level shifted signal node and a first supply node of a higher voltage supply domain, said pull-up path configured to generate a pull-up current and including a first transistor having a first control terminal coupled to receive a feedback signal and a second transistor, coupled in series with the first transistor, having a second control terminal coupled to receive a bias signal; a pull-down path coupled between the level shifted signal node and a second supply node and configured to generate a pull-down current; and a biasing circuit configured to generate the bias signal coupled to the second control terminal; wherein the biasing circuit comprises a circuit path conducting a bias current, and wherein the pull-up current in the pull-up path is smaller than the bias current and the pull-down current in the pull-down path is greater than or equal to the bias current.