Patent ID: 7170135

Claim:
A voltage protection arrangement for use to protect a semiconductor structure from electro-static discharge voltage at an input node thereof, the arrangement comprising: discharge means, having an input for coupling to the input node, and an output for coupling to ground, the discharge means being arranged to provide a discharge path from the input node to ground if the voltage at the input node exceeds a threshold voltage, wherein the discharge means comprises self-triggered transistor means having one of: collector and emitter regions if said self-triggered transistor means comprises bipolar transistor means, and drain and source regions if said self-triggered transistor means comprises MOS transistor means, and at least one floating region therein ranged to modify a threshold voltage by separating an electric field between one of: the collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and the drain and source regions when the self-triggered transistor means comprises MOS transistor means.