Patent ID: 7810003

Claim:
A method of generating a test clock signal for scan testing of a main circuit in a semiconductor device, the method comprising: receiving an external clock signal and a control signal; generating a gate control signal, based on the control signal, synchronized with an internal clock signal; generating a gated clock signal by gating the internal clock signal based on the control signal, the internal clock signal having a frequency higher than a frequency of the external clock signal; and selectively outputting one of the external clock signal and the gated clock signal, the external clock signal being output during a shift period and the gated clock signal being output during a capture period, wherein generating the gate control signal comprises: generating a first control signal by synchronizing the control signal with the internal clock signal; generating a second control signal, which is initially active and which becomes inactive after a number of pulses of the internal clock signal equals a predetermined number after the first control signal becomes active; and generating the gate control signal, which is active when both the first control signal and the second control signal are active.