Patent ID: 7033870

Claim:
A semiconductor fabrication method, comprising the steps of: (a) providing (i) a gate layer, (ii) a gate dielectric layer on the gate layer, and (iii) a semiconductor layer on the gate dielectric layer, wherein the semiconductor layer is electrically insulated from the gate layer by the gate dielectric layer; (b) selectively implanting ions in the semiconductor layer so as to form first and second halo regions in the semiconductor layer, wherein the first and second halo regions comprise said ions; and (c) forming first, second, and third source/drain regions in the semiconductor layer, wherein the first halo region is in direct physical contact with the first source/drain region, and wherein the second halo region is in direct physical contact with the second source/drain region, and such that a first channel region in the semiconductor layer is disposed between and in direct physical contact with the first and second source/drain regions, such that a second channel region in the semiconductor layer is disposed between and in direct physical contact with the second and third source/drain regions, and such that the first and second channel regions are in direct physical contact with the gate dielectric layer.