Patent ID: 8369477

Claim:
A clock frequency divider circuit that generates an output clock signal obtained by dividing a frequency of an input clock signal into N/M (N is a positive integer and M is a positive integer greater than N) by masking (M-N) clock pulses among M clock pulses of the input clock signal based on a frequency division ratio defined as N/M, comprising: a mask control circuit comprising: a mask timing signal generation circuit that generates a mask timing signal used to preferentially masks a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among M clock pulses of the input clock signal based on a communication timing signal indicating the communication timing; and a mask restraint circuit that generates a mask signal obtained by processing the mask timing signal so that masking of the clock pulse is restrained at the communication timing; and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.