Patent ID: 7932846

Claim:
An A/D converter comprising: a sample/hold unit that samples an input analog signal at a predetermined timing to hold m (m≧2) equal analog values and successively outputs the m held equal analog values in time series; an A/D converting unit that converts the m equal analog values successively input in time series from the sample/hold unit to m digital signals in time series; a data-alignment adjusting circuit that adjusts timings of the m digital signals successively input in time series from the A/D converting unit to parallelize the m digital signals; and an averaging circuit that outputs an average value of the m digital signals input in parallel from the data-alignment adjusting circuit as a final A/D conversion result, wherein the A/D converting unit is configured of one A/D converting unit that converts the m equal analog values successively output in time series from the sample/hold unit to the m digital signals in a processing time that is 1/m of a time interval in which the sample/hold unit samples the m analog values.