Patent ID: 7774726

Claim:
A computer implemented method, comprising: using a computer system which comprises at least one processor and is configured for performing: analyzing a first set of pattern-dependent variations that is predicted to occur on a first level of an IC design; analyzing a second set of pattern-dependent variations that is predicted to occur on a second level of the IC design, in which the first level and the second level respectively represent a first layer and a second layer of films in a stack of films of the IC design, and the first set of pattern-dependent variations represents topological or thickness variations on the first and the second level; determining a dummy fill parameter to address both the first set and the second set of pattern-dependent variations, wherein dummy fill is implemented, based at least in part upon the dummy fill parameter, on the second level of the IC design to address both the first set and the second set of pattern-dependent variations, and the first level is determined not to add any or sufficient dummy fill to address the first set and the second set of pattern-dependent variations; and storing the dummy fill parameter of the IC design in a computer readable storage medium or a computer storage device of the computer system or displaying the dummy fill parameter on a display apparatus of the computer system.