Patent ID: 8575961

Claim:
A multi-valued driver circuit configured to selectively output, to a transmission line, one from among K voltages according to a selection signal, K representing an integer of 2 or more, and to be capable of independently adjusting the K voltages according to (M+Nl)-bit setting data, M and Nl each representing an integer, the multi-valued driver circuit comprising: an output port connected to the transmission line; first memory configured to store the upper M bits of the setting data for each of the K voltages; second memory configured to store the lower Nl bits of the setting data for each of the K voltages; M first selectors respectively provided for the upper M bits of the setting data, each configured to receive the corresponding bits of the K setting data, and to select one from among the corresponding bits of the K setting data according to the selection signal; Nl second selectors respectively provided for the lower Nl bits of the setting data, each configured to receive the corresponding bits of the K setting data, and to select one from among the corresponding bits of the K setting data according to the selection signal; M first buffer units respectively provided for the M first selectors, and each configured to output a voltage that corresponds to the output value of the corresponding first selector; M first resistors respectively provided for the M first buffer units, each configured to have a resistance value R, and each arranged such that the output voltage of the corresponding first buffer unit is applied to one terminal thereof, and the other terminal thereof is connected to the output port; Nl second buffer units respectively provided for the Nl second selectors, and each configured to output a voltage that corresponds to the output value of the corresponding second selector; a third buffer unit configured to generate a fixed voltage; Nl second resistors respectively provided for the Nl second buffer units, each configured to have a resistance value R, and each arranged such that the output voltage of the corresponding second buffer unit is applied to one terminal thereof; a third resistor configured to have a resistance value R, and arranged such that the output voltage of the third buffer unit is applied to one terminal thereof; and Nl fourth resistors connected so as to form a R-2R ladder network together with the Nl second resistors and the third resistor, with the aforementioned output port as an output terminal of the R-2R ladder network.