Patent ID: 8036300

Claim:
A circuit configured to generate a clock locked to a data signal, comprising: a first phase adjustment loop that adjusts phase of the clock through a finite phase range in manner responsive to detected phase difference between the clock and the data signal; and a second phase adjustment loop that stepwise adjusts phase of the clock responsive to detected phase difference between the clock and the data signal over an infinite range, the second phase adjustment loop to alter phase in a manner to vary effectively frequency of the clock to lock the clock to the data signal; and at least one phase interpolator that receives a plurality of phase signals that are of equal frequency but are offset in phase relative to one another, and that mixes the plurality of phase signals in response to a phase difference detected by at least one of the first phase adjustment loop and the second phase adjustment loop to produce the clock; wherein the first phase adjustment loop has a significantly shorter loop delay than the second phase adjustment loop, such that the first phase adjustment loop and second phase adjustment loop cooperate to vary both frequency and phase of the clock to minimize difference in phase between the clock and the data signal.