Patent ID: 8822334

Claim:
A method for manufacturing a semiconductor structure, comprising: a) providing a substrate on which a dummy gate stack is formed, forming a spacer at sidewalls of the dummy gate stack, and forming a source/drain region and a source/drain extension region at both sides of the dummy gate stack; b) removing at least part of the spacer to expose at least part of the source/drain extension region; c) forming a contact layer on the source/drain region and the exposed source/drain extension region, the contact layer being made of one of CoSi 2 , NiSi and Ni(Pt)Si 2-y or combinations thereof, and a thickness of the contact layer being less than 10 nm; and d) performing a replacement gate process, wherein a high K gate dielectric layer is subjected to annealing at a temperature ranging from 700° C. to 850° C. after the formation of the contact layer.