Patent ID: 8700688

Claim:
Apparatus for processing data comprising: an instruction decoder responsive to a program instruction to generate one or more control signals; a register bank having a plurality of registers; and processing circuitry coupled to said instruction decoder and said register bank and responsive to said one or more control signals to perform a data processing operation corresponding to said program instruction upon one or more data values stored within said register bank; wherein said instruction decoder is responsive to a polynomial divide instruction as a single instruction to generate one or more control signals that control said processing circuitry to generate as an output stored in said plurality of registers at least a quotient value representing a quotient polynomial for a polynomial division over a field of two elements of a numerator polynomial by a denominator polynomial, said denominator polynomial being an N degree polynomial given by the sum of c i x i for N≧i≧0, where c (N-1) to c 0 are respective bits stored in a register of said register bank and c N =1 and is not stored within said register, and the degree N of the denominator polynomial is greater than one.