Patent ID: 8112684

Claim:
An integrated circuit comprising: A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; B. an IC TAP domain including: i. a TAP controller having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input coupled to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input coupled to the test data in lead, a test data output, and control inputs connected to the control outputs; and iv. multiplexer circuitry coupling the test data outputs of the instruction register and the data register to the test data out lead; C. a core TAP domain including: i. a TAP controller having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input coupled to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input coupled to the test data in lead, a test data output, and control inputs connected to the control outputs; and iv. multiplexer circuitry coupling the test data outputs of the instruction register and the data register to the test data out lead; and D. input linking circuitry including: i. first gating circuitry having an input connected to the test mode select lead, an input connected to an IC TAP enable lead, and an output connected to the test mode select input of the IC TAP domain, and ii. second gating circuitry having an input connected to the test mode select lead, an input connected to a core TAP enable lead, and an output connected to the test mode select input of the core TAP domain.