Patent ID: 7106637

Claim:
A pseudo-static memory device receiving command and address signals at command and address terminals, respectively, the pseudo-static memory device comprising: an array of memory cells; an address decoding circuit coupled to the array of memory cells for decoding memory address signals representing memory addresses and accessing the memory cells of the array corresponding to the memory addresses; a data input/output circuit coupled to the array of memory cells to couple data to and from the memory cells of the array; a command decoder circuit coupled to the command terminals, the array of memory cells and the data input/output circuit, the command decoder circuit adapted to decode command signals and generate internal memory signals to perform memory operations; and an address interface circuit coupled to the command decoder circuit, the address decoding circuit and the address terminals to enable the command decoder circuit and initiate a memory operation a minimum time following receipt of a last received memory address, the minimum time sufficient to allow access to the array of memory cells for a previous memory operation to complete, the address interface circuit aborting the previous memory operation before being intitiated in the event the last received memory address is received before the minimum time elapses.