Patent ID: 6855611

Claim:
A method of fabricating a semiconductor device, which comprises a bipolar transistor, a CMOS and an electrostatic discharge protection circuit, the method comprising providing a substrate, which comprises an electrostatic discharge protection circuit region, a bipolar transistor region and a CMOS transistor region, wherein a first P well is formed in the electrostatic discharge protection circuit, a second P well is formed in the CMOS transistor region, and an N well is formed in the bipolar transistor region; simultaneously forming a first buried layer at a lateral junction between the first P well and the substrate, and a second buried layer at a lateral junction between the N well and the substrate; simultaneously forming a first sinker layer in the first P well and a second sinker layer in the N well, wherein the first sinker layer is electrically connected to the first buried layer, and the second sinker layer is electrically connected to the second buried layer; forming a first NMOS gate on the first P well, a second NMOS gate on the second P well, and a conductive layer on the N well; forming a first NMOS source and a first NMOS drain in the first P well at two sides of the first NMOS gate and a second NMOS source and a second NMOS drain in the second P well at two sides of the second NMOS gate simultaneously; forming a first P+ substrate-connecting region in the first P well and a second P+ substrate-connecting region in the second P well simultaneously; and forming a bipolar transistor on the conductive layer.