Patent ID: 8024598

Claim:
An apparatus for generating a clock using piecewise linear modulation, comprising: a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile including two or more linear signals; a delta-sigma modulator for receiving the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M; a phase-frequency comparator for outputting up and down pulses having the same phase difference as that between a reference clock and a feedback clock; a charge pump for outputting a predetermined current for a time corresponding to the phase difference between the up and down pulses; a loop filter for outputting a control voltage corresponding to the predetermined current; a voltage controlled oscillator (VCO) for outputting a multi-phase clock having a frequency corresponding to a level of the control voltage; and a fractional divider for receiving the multi-phase clock of the VCO, selecting a divider according to the K-bit profile, and outputting a divided clock as the feedback clock signal, by interpolating phases of the multi-phase clock, the fractional divider including a division controller for outputting a selection signal according to the K-bit profile of the delta-sigma modulator and the feedback clock, a phase selector for selecting a clock signal from the multi-phase clock according to the selection signal, and a phase interpolator for interpolating the selected clock signal according to the selection signal to generate a divided clock, wherein the phase selector includes an edge detector for detecting an edge of the output of the division controller, a sampling synchronizer for synchronizing the multi-phase clock with the detected edge, and a multiplexer for selecting the clock signal from the multi-phase clock and dividing the frequency of the multi-phase clock.