Patent ID: 7589385

Claim:
A complementary metal-oxide semiconductor (CMOS) transistor device, comprising: a semiconductor substrate; an NMOS transistor having a first gate, a first gate oxide layer between the first gate and the semiconductor substrate, silicon oxide offset spacer on sidewalls of the first gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the first gate, the N type lightly doped source/drain, and the N type heavily doped source/drain, wherein the tensile-stressed silicon nitride layer directly contacts the N type lightly doped source/drain; and a PMOS transistor having a second gate, a second gate oxide layer between the second gate and the semiconductor substrate, silicon nitride spacer on sidewalls of the second gate, P type lightly doped source/drain implanted into the semiconductor substrate under the silicon nitride spacer, P type heavily doped source/drain implanted into the semiconductor substrate next to the P type lightly doped source/drain, and compressive-stressed silicon nitride layer covering the second gate, the silicon nitride spacer, and the N type heavily doped source/drain.