Patent ID: 7358124

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a pair of first and second gate members on a substrate; forming a gate insulating layer on the first and the second gate members; forming a pair of first and second semiconductor members on the gate insulating layer; forming a pair of first and second source members and a pair of first and second drain members over the pair of first and second semiconductor members; forming a passivation layer on the substrate including the gate insulating layer, and the first and second semiconductor, source and drain members; and forming a pixel electrode connected to the first and the second drain members on the passivation layer, wherein at least one pair of the first and the second gate members, the first and the second semiconductor members, the first and the second source members, and the first and the second drain members are formed using a divisional light exposure, and a boundary line between shots in the divisional light exposure is located between the first gate member and the second gate member, between the first semiconductor member and the second semiconductor member, between the first source member and the second source member, or between the first drain member and the second drain member.