Patent ID: 7733588

Claim:
A phase error reduction system, comprising: a control module that generates source timestamps for a plurality of synchronization marks in a source signal using a clock and that generates a plurality of target timestamps; a phase-locked loop (PLL) module that determines phase errors between said source timestamps and said target timestamps and that minimizes said phase errors; and a harmonic removal module that communicates with said PLL module and that removes harmonics of said phase errors using a weighted moving average filter (MAF), wherein said harmonic removal module further comprises a repetitive feed forward (RFF) module that includes: an amplifier that scales said phase errors; a delay buffer that generates RFF commands to reduce said phase errors; said weighted moving average filter (MAF) that filters said RFF commands; and a summing module that provides sums of said phase errors scaled by said amplifier and said RFF commands filtered by said weighted MAF to said delay buffer.