Patent ID: 8683128

Claim:
A data processing system, comprising: a multi-level cache hierarchy including a lowest level cache, wherein the lowest level cache is a set-associative cache including a plurality of congruence classes each having a plurality of ways including more recently used ways and less recently used ways, wherein the less recently used ways across all of the plurality of congruence classes are allocated as a virtual write queue; a processor core coupled to the multi-level cache hierarchy; a memory controller coupled to the lowest level cache and to a memory bus of a system memory, the memory controller including: a physical read queue that buffers data read from the system memory via the memory bus; and a physical write queue that buffers data to be written to the system memory via the memory bus; wherein the memory controller has visibility into the virtual write queue and temporarily grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the virtual write queue of the lowest level cache memory but not based upon a number of dirty cachelines within the more recently used ways; and wherein the memory controller, while write operations are granted priority over read operations, issues one or more write operations from the physical write queue via the memory bus.