Patent ID: 7999901

Claim:
A thin film transistor array substrate comprising: thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that intersect each other; a plurality of gate pad units that group a plurality of gate pads extended from the gate lines; a plurality of data pad units that group a plurality of data pads extended from the data lines; test terminal units comprising at least one of gate test terminal units or data test terminal units, wherein the gate test terminal units include a plurality of gate test terminals and are provided adjacent to at least one side of the gate pad units to be connected thereto, and the data test terminal units include a plurality of data test terminals and are provided adjacent to at least one side of the data pad units to be connected thereto; gate terminal lines extended from the respective plurality of gate test terminals on the outside of the plurality of gate pads; and gate shorting bars provided on the outside of the gate terminal lines and connected to the plurality of gate pads, wherein the gate shorting bars each have a width of about 50 to about 60 μm, and the gate terminal lines each have a width of about 170 μm.