Patent ID: 7725682

Claim:
A method for executing instructions in a processor having a polymorphic execution unit, comprising: reloading a state associated with a first instruction class of an instruction set architecture and reconfiguring the polymorphic execution unit to operate in accordance with the first instruction class, directly responsive to an instruction of the first instruction class being encountered and the polymorphic execution unit being configured to operate in accordance with a second instruction class; reloading a state associated with a second instruction class of the instruction set architecture and reconfiguring the polymorphic execution unit to operate in accordance with the second instruction class, directly responsive to an instruction of the second instruction class being encountered and the polymorphic execution unit being configured to operate in accordance with the first instruction class; and executing, in another execution unit, other instructions from the instruction set architecture than any of the instructions from the first and the second instruction classes; wherein the state associated with either the first or the second instruction class is maintained unmodified in a de-configured state storage element, when the state associated with either the first or the second instruction class is unloaded from a register file operatively coupled to the polymorphic execution unit, and wherein a state associated with the other instructions is maintained in a register file operatively coupled to the other execution unit.