Patent ID: 8810701

Claim:
An amplifying/digitalizing circuit, comprising: an amplifier, having an input end and an output end; and a control circuit, coupled to the input end of the amplifier and directly connected to the output end of the amplifier, wherein when the amplifying/digitalizing circuit is operated under an amplifying mode, the control circuit has a first configuration to receive a first input signal and makes the amplifier generate an output voltage at the output end according to the first input signal and an amplification factor; and when the amplifying/digitizing circuit is operated under an ADC mode, the control circuit has a second configuration to receive a second input signal and makes the amplifier generate a comparison result according to the second input signal and the output voltage; wherein when the amplifying/digitalizing circuit is operated under a reset mode, the control circuit has a third configuration to reset the amplifier, and the control circuit comprises: a first capacitor, having: a first node, coupled to the first input signal; and a second node, coupled to the input end of the amplifier; a second capacitor, having: a first node, coupled to the input end of the amplifier; and a second node; a first switch, coupled between the second node of the first capacitor and the input end of the amplifier; a second switch, coupled between the input end of the amplifier and the output end of the amplifier; a third switch, coupled between the output end of the amplifier and the second node of the second capacitor; and a fourth switch, coupled between the second node of the second capacitor and the second input signal; wherein the first and third switches are switched on and the second and fourth switches are switched off under the amplifying mode; the fourth switch is switched on and the first, second and third switches are switched off under the ADC mode; and the first, second, and fourth switches are switched on and the third switch is switched off under the reset mode.