Patent ID: 8412991

Claim:
At a failure analysis computing device, a method for identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included, the method comprising: in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values being generated by combinational logic cells electrically connected with the scan chain; in a shift mode: sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell; identifying a particular scan cell providing output directly to the reference scan cell; and assigning a scan cell index to each scan cell according to a scan cell order, each scan cell being assigned a scan cell index that is different from the scan cell index of any other scan cell.