Patent ID: 7143375

Claim:
A logical equivalence verifying device for performing logical equivalence verification of two prescribed circuits to display the results thereof, said device comprising: a first identifier recording section that performs structural matching in which it is determined whether there are those portions in corresponding logic cones of said two circuits which correspond in circuit structure to each other, and records each result of said structural matching as an identifier for each element; a subcone extracting section that extracts a plurality of collections of elements as subcones from each of said logic cones, each element collection including elements which are connected with each other and have the same identifier; a verifying section that verifies logical equivalence between said two circuits for each subcone extracted by said subcone extracting section; and a display control section that displays a first group of subcones with mismatched results of said logical equivalence verification and a second group of subcones with matched results of said logical equivalence verification while distinguishing between these first and second groups of subcones based on the results of said logical equivalence verification, wherein, when verification information on the subcone becomes mismatched, said display control section graphically displays the mismatched subcone.