Patent ID: 8049308

Claim:
A semiconductor device comprising: a semiconductor substrate; a plurality of gate structures formed on a portion of the semiconductor substrate; an interlayer dielectric overlying the gate structures, the interlayer dielectric layer having a substantially flat surface region; a first copper interconnect layer overlying the substantially flat surface region of the first interlayer dielectric layer; a low K dielectric layer overlying the first copper interconnect layer; a second copper interconnect layer overlying the low K dielectric layer, the second copper interconnect layer having an upper surface; a plurality of metal ring structures enclosing an entirety of an inner region of the low K dielectric layer, the plurality of metal ring structures being provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the low K dielectric layer and to provide mechanical support between the first and second copper interconnect layers, each of the metal ring structures having a dielectric material disposed in between them; and a bonding pad structure overlying a region within the inner region, the bonding pad structure having a bottom portion being coupled to the second copper interconnect layer, wherein the entire bottom portion is completely within the upper surface of the second copper interconnect layer.