Patent ID: 6895424

Claim:
A processing element having support for alignment of significants, comprising: a first register block, said first register block including at least one first register for holding a first exponent and a first significant of a first floating point number; a second register block, said second register block including at least one second register for holding a second exponent and a second significant of a second floating point number and a second logic, said second logic capable of right shifting the significant of the second floating point number and said second logic also being capable of setting to zero each bit in a portion of said second significant to zeros; a shift control register; an arithmetic logic unit coupled to said first register block, said second register block, and said shift control register, said arithmetic logic unit storing in the shift control register a value equal to the difference between said first exponent and said second exponent, said arithmetic logic unit causing the second logic to right shift the significant or set to zero each bit in the portion of the significant, based upon the contents of said shift control register.