Patent ID: 8094705

Claim:
A tester for characterizing a device under test (DUT) comprising first and second serializer/deserializer (SERDES) modules, comprising: a first conductor adapted to, when the DUT is operatively coupled to the tester, couple a transmit (TX) output of the first SERDES module to a receive (RX) input of the second SERDES module; a first clock generator configured to, when the DUT is operatively coupled to the tester, clock the first SERDES module using a first clock signal; a second clock generator configured to, when the DUT is operatively coupled to the tester, clock the second SERDES module using a second clock signal, wherein the first clock signal is equivalent to the second clock signal with a first jitter; and a functional module configured to, when the DUT is operatively coupled to the tester, receive a first test result from the DUT by configuring the DUT to: convert, using the first SERDES module based on the first clock, first parallel test data generated by a first test pattern generator comprised in the DUT into first serial test data at the TX output of the first SERDES module, wherein the first serial test data is communicated to the RX input of the second SERDES module via the first conductor; convert, using the second SERDES module based on the second clock, the first serial test data at the RX input of the second SERDES module into first parallel verification data; and generate the first test result by analyzing the first parallel verification data based on a first pre-determined criterion using a first test pattern verifier comprised in the DUT.