Patent ID: 8526536

Claim:
A circuit for a transmitter configured to receive one or more input signals comprising: a load; a first Chireix compensation circuit comprising: a first power amplifier, a second power amplifier, a first Chireix inductor, and a first Chireix capacitor, wherein an output of the first Chireix compensation circuit is coupled to the load; a second Chireix compensation circuit comprising: a third power amplifier, a fourth power amplifier, a second Chireix inductor, and a second Chireix capacitor, wherein an output of the second Chireix compensation circuit is coupled to the load; and a switch configured to couple one or more Chireix input signals derived from the one or more input signals to either the first or second Chireix compensation circuits in accordance with a characteristic of the one or more input signals, wherein the outputs of the first and second Chireix compensation circuits are coupled to the load in reverse bias relative to each other.