Patent ID: 7811876

Claim:
A method, comprising: selectively performing a pre-amorphization process for drain and source regions of a plurality of first N-channel transistors in a first device region using non-dopant ions, while masking a plurality of first P-channel transistors in said first device region and masking a plurality of second P-channel transistors and a plurality of second N-channel transistors formed in a memory device region of a semiconductor device; performing a second pre-amorphization process selectively for said second N-channel transistors, wherein said second pre-amorphization process comprises an implantation step using a tilt angle; annealing said first and second P-channel transistors and said second N-channel transistors in the presence of a rigid material layer formed above said first device region to re-crystallize said first N-channel transistors in a strained state; and providing a strain-inducing mechanism in said first device region and said memory device region to induce strain in said first and second P-channel transistors and second N-channel transistors.