Patent ID: 8446173

Claim:
An apparatus comprising: an output driver configured to generate a differential output signal, wherein the output driver comprises a first subcircuit and a second subcircuit, wherein the first subcircuit is configured to generate a positive-logic output signal of the differential output signal, wherein the first subcircuit comprises one or more PMOS transistors configured to pull-up the positive-logic output signal for a first logic state of the differential output signal and one or more NMOS transistors configured to pull-down the positive-logic output signal for a second logic state opposite to the first logic state of the differential output signal; and wherein the second subcircuit is configured to generate a negative-logic output signal of the differential output signal, wherein the negative-logic output signal is inverted with respect to the positive-logic output signal, wherein the second subcircuit comprises one or more PMOS transistors configured to pull-up the negative-logic output signal for the second logic state of the differential output signal and one or more NMOS transistors configured to pull-down the negative-logic output signal for the first logic state of the differential output signal; and a control circuit configured to provide gate voltages of the PMOS transistors and/or the NMOS transistors of the output driver such that a relationship between an amount of on resistance of the PMOS transistors as compared to an amount of on resistance of the NMOS transistors is tunable.