Patent ID: 7858454

Claim:
A method, comprising: depositing a layer of nanotubes over a substrate; forming a source and a drain over the layer of nanotubes; forming a self-aligned gate over the layer of nanotubes between the source and the drain by: depositing a resist layer over the layer of nanotubes, source and drain; patterning the resist layer to expose an open window in a gate region over portions of the source and the drain and the layer of nanotubes extending between the source and the drain; forming a gate dielectric layer over at least the exposed portions of the source and the drain and the layer of nanotubes extending between the source and the drain; and forming a gate electrode layer over the gate dielectric layer, wherein the gate dielectric layer and the patterned resist layer serve to self-align the gate with respect to the source and the drain, wherein the self-aligned gate includes an overall width greater than a gate length distance between the source and the drain over the layer of nanotubes.