Patent ID: 8030701

Claim:
A memory cell of a nonvolatile semiconductor memory device comprising: a first insulating film which is arranged on a semiconductor substrate; a charge storage layer which is arranged on the first insulating film and which includes insulating material layers; a second insulating film which is arranged on the charge storage layer and whose permittivity is higher than that of the first insulating film; and a control gate electrode which is arranged on the second insulating film, wherein, when the insulating material layers included in the charge storage layer are represented as i=1, 2, . . . , n, starting from the first insulating film toward the second insulating film, the conduction band edge energy of each of the insulating material layers is expressed as φ c,i (i=1, 2, . . . , n), and the valence band edge energy of each of the insulating material layers is expressed as φ v,i (i=1, 2, . . . , n), the conduction band edge energy and valence band edge energy of adjacent layers of the insulating material layers satisfy one of (φ c,i+1 >φ c,i and φ v,i+1 >φ v,i ) and (φ c,i+1 <φ c,i and φ v,i+1 <φ v,i ) where i=1, 2, . . . , n−1 and, when the relative permittivity of the second insulating film is expressed as ∈ r , a potential barrier to electrons defined as the difference between the lowest conduction band edge energy level in the charge storage layer and conduction band edge energy level in the second insulating film is not lower than 4.5 ∈ r −2/3 (eV) nor higher than 3.8 (eV) and a potential barrier to holes defined as the difference between the highest valence band edge energy level in the charge storage layer and the valance band edge energy level in the second insulating film is equal to or larger than 4.5 ∈ r −2/3 (eV) and is equal to or smaller than 3.8 (eV).