Patent ID: 7940277

Claim:
A processor comprising: a first datapath having a first bit width; a second datapath having a second bit width greater than the first bit width; a plurality of third datapaths having a combined bit width less than the second bit width; a wide operand storage coupled to the first datapath and the second datapath for storing a wide operand received over the first datapath, the wide operand having a size with a number of bits greater than the first bit width; a register file including registers having the first bit width, the register file being connected to the first datapath and the third datapaths, and including storage for a wide operand specifier for specifying both an address and a size of the wide operand; a functional unit capable of performing operations in response to instructions, the functional unit coupled by the second data path to the wide operand storage and coupled by the third data paths to the register file, the functional unit referencing the register file to obtain information to allow storage of the wide operand in the wide operand storage; and wherein the functional unit executes a single instruction to perform an arithmetic operation which is later followed by an instruction for an extract controlled by at least one first register in the register file in which the at least one first register specifies a shift amount and a size of a field to be extracted from the wide operand.