Patent ID: 7582524

Claim:
A method for preparing a memory structure, comprising the steps of: forming a plurality of dielectric line-shaped patterns on a substrate having a dielectric structure with word lines, the dielectric line-shaped patterns being perpendicular to the word lines; forming a first silicon-containing layer covering the dielectric line-shaped patterns; forming a first implanting mask covering a portion of the first silicon-containing layer in a predetermined region; performing a first tilt implanting process to implant dopants into the first silicon-containing layer outside the predetermined region; forming a second implanting mask exposing a portion of the first silicon-containing layer in the predetermined region; performing a second tilt implanting process to implant dopants into the first silicon-containing layer inside the predetermined region, wherein the implanting direction of the first implanting process is different from the implanting direction of the second implanting process; removing a portion of the first silicon-containing layer other than a predetermined portion to form a first etching mask exposing a portion of the line-shaped pattern; incorporating the first etching mask to remove a portion of the dielectric line-shaped patterns so as to form a second etching mask having a plurality of dielectric blocks, the width of the dielectric block being a half of the width of the dielectric line-shaped pattern; removing a portion of the dielectric structure not covered by the second etching mask to form a plurality of openings in the dielectric structure; and forming conductive plugs in the openings.