Patent ID: 7694250

Claim:
A method of producing a system architecture with a design tool computer, the system architecture including a plurality of electrical components connected to each other, the components including electronic control units, sensors and actuators, the method comprising: a) identifying a set of undesirable events and ascribing to each of the undesirable events an indicator of severity; b) associating each of the undesirable events with any involved actuator of the actuators of the system architecture; c) developing a functional specification of an initial architecture proposed for implementation of the system architecture, the functional specification of the initial architecture including dataflow for and between electrical components thereof; d) refining on the functional specification fault tolerance requirements associated with the severity of each of the undesirable events and issuing refined fault tolerance requirements of the functional specification; e) producing replicates in the functional specification together with attached indicators of freeness of the replicates from other of the replicates, the indicators reflecting the refined fault tolerance requirements; f) defining a hardware structure for the system architecture; g) mapping, via the design tool computer, the functional specification onto the hardware structure; and h) verifying automatically that the indicators of freeness are preserved during the mapping.