Patent ID: 7430654

Claim:
A method of monitoring and controlling instruction dependency for microprocessors, the method comprising: fetching an instruction at thread control element from an instruction buffer; comparing, with a comparator, one or more source operand identifications of the instruction to one or more temporary register identifications, comparing, with the comparator, a thread control ID associated with the thread control element with pipeline thread control IDs in a pipeline, wherein each thread control element and comparator forms a bi-directional correspondence, and wherein each of the one or more temporary register identifications is stored in a temporary register identification pipeline storage location of a set of one or more temporary register identification pipeline storage locations; verifying whether any of the one or more source operand identifications at the thread control element matches any of the one or more temporary register identifications and verifying whether the thread control ID associated with the thread control element matches any pipeline thread control IDs; and in response to a match between the source operand identification and the temporary register identification and a match between the thread control ID associated with the thread control element and a pipeline thread control ID, prohibiting the instruction held in the corresponding thread control element from executing in that clock cycle, wherein the match corresponds to instruction dependency.