Patent ID: 7045900

Claim:
A semiconductor device, comprising: primary semiconductor chip; a secondary semiconductor chip face-down-bonded onto a surface of the primary semiconductor chip to form a chip-on-chip structure; a package that packages the chip-on-chip structure; a primary functional bump formed on the surface of the primary semiconductor chip, for electrical connection between internal circuits of the primary and secondary semiconductor chips; a primary dummy bump, formed on the surface of the primary semiconductor chip, not serving for electrical connection between the internal circuits, the primary dummy bump having a height that is substantially equal to a height of the primary functional bump; a secondary functional bump disposed in association with a peripheral portion of a mating surface of the primary semiconductor chip opposed to the primary semiconductor chip, for electrical connection between the internal circuits; and a secondary dummy bump, disposed in association with a central portion of the mating surface, not serving for electrical connection between the internal circuits but serving for absorption of a force exerted on the secondary semiconductor chip, the secondary dummy bump having a height that is substantially equal to a height of the secondary functional bump; the primary and secondary functional bumps being joined to each other, thereby electrically connecting the primary and secondary semiconductor chips, the primary and secondary dummy bumps being joined to each other over an area of contact extending over an entire active region of the mating surface of the secondary semiconductor chip.