Patent ID: 7718524

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating film containing Si on a semiconductor substrate; forming a metal mask on said interlayer insulating film, said metal mask being formed to a thickness of approximately 10 nm; forming a resist layer on said metal mask having a wiring pattern formed by a lithography technique; forming a pattern trench in said metal mask and said interlayer insulating film by etching away parts of said metal mask and said interlayer insulating film using the resist mask wiring removing said resist layer through an ashing using O 2 plasma; forming a seed layer containing an alloy of copper and another metal manganese on an internal wall of said pattern trench; forming a conductive layer containing copper on said interlayer insulating film so as to fill in said pattern trench; forming a barrier layer for preventing diffusion of copper by causing said seed layer and said interlayer insulating film to react with each other through an annealing treatment; and polishing the conductive layer and said metal mask on said interlayer insulating film to remove excessive Cu or Cu alloy using said metal mask as a polishing stopper so as to leave said conductive layer in said pattern trench, wherein said step of polishing the conductive layer and said metal mask on said interlayer insulating film to remove said excessive Cu or Cu alloy using said metal mask as said polishing stopper comprises: first polishing step of polishing said conductive layer by using a slurry having a polishing selectivity of said conductive layer to each of said metal mask and said interlayer insulating film; and second polishing step of polishing surfaces of said interlayer insulating film and said conductive layer until at least said metal mask is removed by using a slurry for substantially equalizing polishing rates of said metal mask, said interlayer insulating film, and said conductive layer to one another.