Patent ID: 7797361

Claim:
A method for generating random numbers, comprising: generating a plurality of oscillating digital output signals using at least two ring oscillators, and generating an external parity signal (PS) representing a logical state (“0,” “1”), where the external parity signal takes on the logical state “1” when and only when an odd number of the plurality of digital output signals (A 1 , A 2 , . . . , AL) exhibit the logical state “1” and takes on the logical state “0” otherwise, wherein the external parity signal (PS) is fed back to an external parity input of the ring oscillators wherein the sum of the periodicity of an output signal (A 1 , A 2 , . . . , A L ) generated by a first of oscillators, which is equal in value to an odd multiple (K 1 , K 2 , K 3 . . . , K L ) of a delay time of a gate, plus the delay time duration of the external parity signal (PS) at the external parity input of the first of the ring oscillators, equal in value to a multiple (M 1 , M 2 , M 3 , . . . , M L ) of the delay time of a gate, equals an odd multiple of the delay time of a gate and wherein the sum of the periodicity of an output signal (A 1 , A 2 , . . . , A L ) generated by a second of the ring oscillators, which is equal in value to an odd multiple (K 1 , K 2 , K 3 , . . . , K L ) of the delay time of gate, plus the delay time duration of the external parity signal (PS) at the external parity input of the second of the ring oscillators, equal in value to a multiple (M 1 , M 2 , M 3 , . . . , M L ) of the delay time of a gate, equals an even multiple of the delay time of a gate.