Patent ID: 7786597

Claim:
A multilayer wiring board, comprising: a substrate; a plurality of connection pads disposed on the substrate and arranged in a square grid fashion in a pad array area, wherein non-pad regions are arranged periodically along an outer periphery of the pad array area; a plurality of wiring patterns each connected to a corresponding one of the plurality of connection pads, wherein the connection pads and the wiring patterns are arranged so as to satisfy: {( Ndl+ 1) P−d−s }/( w+s )≧2 Ndr+Ndl ( a+ 1)+2 a, wherein P is a pad pitch of the connection pads, d is a diameter of the connection pads, s is a minimum interval between the wiring patterns and is a minimum interval between the wiring pattern and the connection pad that are adjacent to each other, w is a minimum width of the wiring patterns, Ndl is the number of non-pad rows in each of the non-pad regions, Ndr is the number of non-pad columns in each of the non-pad region, and a is an integer of (P−d−s)/(w+s).