Patent ID: 7081649

Claim:
A semiconductor integrated circuitry comprising: a first MISFET including gate electrodes formed on a main surface of a semiconductor substrate via a gate insulating film; a first semiconductor area in contact with a channel area formed under said gate electrodes on the main surface of said semiconductor substrate; a second MISFET including gate electrodes formed on the main surface of the semiconductor substrate via said gate insulating film; a low density semiconductor area in contact with a channel area formed under said gate electrodes on the main surface of said semiconductor substrate; and a high density semiconductor area formed outside said low density semiconductor area, wherein a cap insulating film is formed on top of said gate electrodes of said first and second MISFETS, first side walls formed with first insulating film are formed on side surfaces of said gate electrodes of said second MISFET, second side walls formed with second insulating film comprised of a different member from that of said first insulating film are formed outside said first side walls, a conductor portion connecting said first semiconductor area to a member formed in an upper layer of said first MISFET is formed in a self-aligning manner with respect to third side walls formed with said first insulating film and on side surfaces of the gate electrodes of said first MISFET, and wherein said high density semiconductor area is formed in a self-aligning manner with respect to said second side walls formed with said second insulating film, wherein a silicide layer is formed on the surface of said high density semiconductor area but a silicide layer is not formed on a surface of said first MISFET.