Patent ID: 8552953

Claim:
A display device comprising: a display panel with multiple pixels; and a display controller that receives an input video signal and a sync signal and gets an image presented on the display panel, wherein if one horizontal scanning period and one vertical scanning period of the input video signal are represented by 1H and V-Total, respectively, the display controller is configured to form one vertical scanning period V-Total of a first period in which one horizontal scanning period of the display panel is 1Ho, which is as long as 1H, and a second period in which one horizontal scanning period of the display panel is 1Hn, which is not as long as 1H, the second period is a number of continuous horizontal scanning periods each having a length of 1Hn, wherein the pixels are arranged in columns and rows so as to form a matrix pattern, each said pixel including, a first subpixel and a second subpixel, having liquid crystal layers to which mutually different voltages are applicable, a plurality of electrodes for applying the mutually different voltages to the liquid crystal layers, and two switching elements that are provided for the first and second subpixels, respectively, and each of the first and second subpixels includes, a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them, and wherein the counter electrode is a single electrode provided in common for the first and second subpixels, while the storage capacitor counter electrodes of the first and second subpixels are electrically independent of each other, and a storage capacitor counter voltage applied to each said storage capacitor counter electrode by way of an associated storage capacitor line oscillates in a cycle time that is an integer number of times as long as Ho during the first period included in V-Total but oscillates in a cycle time that is an integer number of times as long as Hn during the second period, when one vertical scanning period V-Total is represented as the sum of an effective display period V-Disp and a vertical blanking interval V-Blank and V-Total=m×H and V-Disp=m 0 ×H, then V-Disp=m 0 ×Ho, V-Blank=m 1 ×Ho+m 2 ×Hn, m, m 0 , m 1 and m 2 being positive integers, and m 2 ×Hn is an integer number of times as long as one cycle time of the storage capacitor counter voltage during the second period.