Patent ID: 7135393

Claim:
A semiconductor device manufacture method comprising the steps of: (a) preparing a semiconductor substrate comprising a well of a first conductivity type having a first depth and a threshold voltage adjusting region formed in said well and having a second depth shallower than the first depth; (b) forming a gate electrode above said semiconductor substrate, with a gate insulating film being interposed therebetween; (c) forming shallow low resistance regions in said semiconductor substrate by implanting impurity ions of a second conductivity type at a first dose and a first acceleration energy, to form extension regions in said semiconductor substrate on both sides of said gate electrode; (d) forming side wall spacers on side walls of said gate electrode; (e) forming source/drain regions by implanting impurity ions of the second conductivity type at a second acceleration energy higher than said first acceleration energy and a second dose, said source/drain regions forming junctions at a third depth deeper than the second depth; (f) implanting ions into said semiconductor substrate to amorphousize an upper layer of said gate electrode and upper layers of said source/drain regions; (g) implanting impurity ions of the second conductivity type at a third acceleration energy and a third dose larger than said second dose to form high concentration regions in said source/drain regions; and (h) activating implanted impurity ions.