Patent ID: 8144540

Claim:
An integrated circuit comprising: a two-port static random access memory (SRAM) cell comprising: a first half write-port comprising a first pull-up transistor, a first pull-down transistor, and a first pass-gate transistor interconnected to each other; a second half write-port comprising a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor interconnected to each other and to the first half write-port, wherein channel lengths of the first pass-gate transistor and the second pass-gate transistor are less than channel lengths of the first pull-down transistor and the second pull-down transistor; and a read-port comprising a read-port pull-down transistor connected to the first half write-port, and a read-port pass-gate transistor connected to the read-port pull-down transistor.