Patent ID: 7692993

Claim:
A semiconductor memory device, comprising: a plurality of memory blocks each including a plurality of memory cells arranged in a matrix pattern, a plurality of word lines respectively corresponding to rows of the plurality of memory cells, a plurality of bit lines respectively corresponding to columns of the plurality of memory cells, and a plurality of sense amplifiers respectively corresponding to the columns of the plurality of memory cells, wherein one of the plurality of word lines is activated simultaneously, the semiconductor memory device further comprising: a plurality of refresh block counters for generating block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks; a refresh word line counter for generating a common word line address that is common to the at least two memory blocks; and an arbitration circuit for generating at least one first word line address based on the at least two block addresses and the common word line address and arbitrating so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed.