Patent ID: 6967372

Claim:
An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween; a first insulation layer disposed over said substrate; an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of the channel region and over a portion of the first region; a second insulation layer having a first portion disposed over said first insulation layer and said substrate, a second portion disposed adjacent the floating gate and a third portion disposed over the floating gate, wherein the second insulation layer has a thickness permitting Fowler-Nordheim tunneling of charges therethrough; an electrically conductive control gate having a first portion disposed over the second insulation layer first portion and adjacent to the second insulation layer second portion, and a second portion extending over the second insulation layer third portion, the control gate having a substantially vertical sidewall portion; and an insulation spacer formed adjacent to the substantially vertical sidewall portion of the control gate; wherein the second region has an edge that is aligned with the substantially vertical sidewall portion.