Patent ID: 7639798

Claim:
A high speed data encryption architecture, comprising: fabric elements communicatively coupled to one another via a hardwired interconnect configured for implementing a plurality of cryptographic algorithms, each of said fabric elements including: a plurality of wide field programmable gate array (FPGA) blocks used for wide datapaths; and a plurality of narrow FPGA blocks used for narrow datapaths, wherein each of said plurality of wide FPGA blocks being communicatively coupled to each other and are interchangeable so that one of said plurality of cryptographic algorithms is mapped to one of said plurality of wide FPGA blocks, each of said plurality of narrow FPGA blocks being communicatively coupled to each other and are interchangeable so that one of said plurality of cryptographic algorithms is mapped to one of said plurality of narrow FPGA blocks; and a control block, communicatively coupled to each of said fabric elements via said hardwired interconnect, for providing control signals to said each of said fabric elements, wherein said fabric elements are configured for implementing at least two of said plurality of cryptographic algorithms concurrently, and no two concurrent cryptographic algorithms are allocated on a same wide FPGA block or a same narrow FPGA block.