Patent ID: 7479405

Claim:
A method of forming a PRAM having a circuit wire in a peripheral array region, comprising: forming a lower peripheral gate pattern on a first semiconductor substrate of at least one reference active region; forming a pad interlayer insulating layer on the first semiconductor substrate to cover the lower peripheral gate pattern; forming upper peripheral gate patterns on at least one other semiconductor substrate of at least one other active region, which are formed vertically in sequence from the upper surface of the pad interlayer insulating layer above the reference active region; forming pad interlayer insulating layers on the other semiconductor substrates to cover the upper peripheral gate patterns; and forming metal node plugs at both sides of the lower and upper peripheral gate patterns to be in contact with the first semiconductor substrate penetrating the pad interlayer insulating layers and the other semiconductor substrates, wherein the other active regions are formed in parallel with the reference active region, and the circuit wire is formed above the metal node plugs and is electrically connected to one of the metal node plugs.