Patent ID: 8753973

Claim:
A method of fabricating a semiconductor memory device comprising: forming a first interconnect layer and a first memory cell layer sequentially; patterning the first memory cell layer and the first interconnect layer to form a first structure of a linear pattern along a first direction in a first region and a second structure in a second region; forming a second interconnect layer and a second memory cell layer sequentially on the first structure and the second structure; patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern along a second direction different from the first direction and having a folded pattern of the third structure at a region immediately on the second structure in the second region; and removing the second memory cell layer and the second interconnect layer in the folded pattern of the third structure and the first memory cell layer of the second structure positioned immediately under the folded pattern of the third structure, wherein the first structure has a folded pattern of the first structure at a third region different from the first and second regions, and when removing the second memory cell layer and the second interconnect layer in the folded pattern of the third structure and the first memory cell layer positioned immediately under the folded pattern of the third structure, the first interconnect layer and the first memory cell layer in the folded pattern of the first structure are also removed.