Patent ID: 8004533

Claim:
A command parser in a graphics processing unit (GPU) for scheduling execution of received commands, comprising: a first input coupled to a scheduler, the scheduler being configured to set at least one register of a global command stream processor (CSP) register component based on a type of a bus interface command, the first input configured to communicate bus interface commands for execution by the command parser; a second input coupled to a controller that receives a ring buffer command from the scheduler upon receipt by the scheduler of a new or previously-partially executed context of commands and pointers, the command parser configured to execute commands associated with the new or previously-partially executed context of commands and pointers; a third input coupled to a command DMA component that receives DMA commands from the controller that are contained in the new or previously-partially executed context of commands and pointers and forwards the DMA commands and a pointer associated to the DMA commands to the command parser; and a plurality of outputs, wherein the command parser forwards data in correspondence to commands received on one or more of the first, second, and third inputs.