Patent ID: 8572148

Claim:
A data reorganizer, comprising: a first radix-k commutator for k a positive even integer greater than zero; wherein the first radix-k commutator is coupled to receive first parallel input streams to provide first parallel output streams; an address generator coupled to receive a clock signal and configured to generate select signals and address signals using the clock signal; memory buffers coupled to respectively receive the first parallel output streams from the first radix-k commutator and to respectively receive the address signals from the address generator; wherein the first parallel input streams have data in a first order; wherein the first radix-k commutator is coupled to receive a first select signal of the select signals and configured to reorder the first parallel input streams to rearrange the data via the first parallel output streams for segmented storage of the data in the memory buffers in a second order; and a second radix-k commutator coupled to receive second parallel input streams from the memory buffers to provide second parallel output streams; wherein the second radix-k commutator is coupled to receive a second select signal of the select signals and configured to reorder the second parallel input streams to rearrange the data via the second parallel output streams into a third order; and wherein the memory buffers form a single buffer stage between the first radix-k commutator and the second radix-k commutator.