Patent ID: 7132852

Claim:
A programmable logic device comprising: a plurality of logic elements (LEs) for performing logic functions that are arranged in one or more logic array blocks (LABs); at least one input/output (I/O) block for passing signals between said LEs and one or more I/O pads associated with said I/O block, said I/O pads providing input and output to said programmable logic device; and a signal routing architecture for routing signals among said LEs and said at least one I/O block comprising: a plurality of horizontal and vertical signal routing conductors and drive circuitry; at least one block input multiplexer for selectively providing signals from said plurality of horizontal and vertical signal routing conductors to said at least one I/O block; and at least one output bypass path for providing a direct connection between an output from one of said plurality of LEs and said at least one I/O block, wherein said at least one output bypass path does not travel through a multiplexer between said plurality of LEs and said at least one I/O block.