Patent ID: 6915458

Claim:
A method of single-step interruption debugging applied in a peripheral component interconnect (PCI) bus cycle, which comprises the steps of: sending out a request signal (REQ#) from a bus master to request for the control of the bus cycle; locking the signal states such as the address, data, command and byte enable (BE#) of the bus cycle and displaying them through a display; sending out the address, the command, a frame signal (FRAME#) and an IRDY# ready signal in the next bus cycle after a PCI arbiter responds a acknowledge signal (ACK#); decoding the address and command through a target device and sending out a device selection signal (DEVSEL#) from the target device; displaying the signal states such as the address, the data, the command, the byte enable locked in the previous bus cycle on the display; and sending out a TRDY# ready signal through a switch to end the PCI bus cycle.