Patent ID: 6917067

Claim:
A semiconductor memory device comprising: a semiconductor substrate having a plurality of active regions defined therein; a plurality of gate lines extending across the plurality of active regions, the plurality of gate lines including at least two adjacent gate lines; a capping layer covering top surfaces and sidewalls of the gate lines; a plurality of contact pads contacting the active regions between the at least two adjacent gate lines; a first interlayer insulating layer pattern disposed between the plurality of gate lines; a second interlayer insulating layer pattern disposed overlying the capping layer and the first interlayer insulating layer pattern, the second interlayer insulating layer pattern having a plurality of contact holes therethrough to expose top surfaces of the contact pads, the second interlayer insulating layer pattern having a top surface and a sidewall; a first etch stop layer pattern covering the top surface of the second interlayer insulating layer pattern; a second etch stop layer pattern disposed over a portion of the contact pad to cover the sidewall of the second interlayer insulating layer pattern; and a plurality of contact plugs extending through the contact holes to contact the top surfaces of the contact pads, wherein the first and second etch slop layer patterns each having an etch selectivity with respect to the second interlayer insulating layer pattern.