Patent ID: 7996812

Claim:
A method of correcting early-mode timing violations in a chip design formed by a plurality of interconnected nets and cells, the chip design having undergone placement, late-mode timing closure, routing, electrical and timing analysis, the method comprising: a) using a computer, selecting at least one of the plurality of interconnected nets and cells of the chip design having an early mode slack that is smaller than a predetermined threshold; and b) performing on said at least one of the plurality of interconnected nets and cells at least one local optimization without applying early mode padding, wherein changes requiring said local optimization are performed by incrementally adjusting the placement of the chip design, said incrementally adjusted placement comprising: i. an exact placement in an existing space within a specified distance; ii. an exact placement in an existing space within a specified distance with moves for creating sufficient area for a new or expanded cell; and iii. a placement allowing overlaps with existing cells.