Patent ID: 8116161

Claim:
A system for refreshing a DRAM array, comprising: refresh control circuitry that selectively generates requests to perform refresh operations; a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to a request to perform a refresh operation, the refresh address corresponding to a word line of the DRAM array to be refreshed; and address control and switching circuitry coupled to the refresh control circuitry, the address control and switching circuitry being adapted to selectively transmit read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations; wherein the refresh control circuitry comprises: a refresh timer oscillator; a latching circuit that is coupled to the refresh timer oscillator and that generates a refresh flag during which time a refresh operation may be completed; and a pulse width detector that is coupled to the latching circuit and that selectively causes the latching circuit to reset the refresh flag.