Patent ID: 8504950

Claim:
A method comprising: forming, on a wafer, at least one interconnect layer and a plurality of function blocks, wherein each function block includes a plurality of primitive cells, wherein each of the primitive cells comprises logic including a plurality of devices, wherein the at least one interconnect layer, circuitry of at least one of the function blocks, and circuitry of at least one of the primitive cells are fixedly defined by at least one component from a pre-existing library of standard cell logic, and wherein said forming is performed prior to receipt of a custom circuit design to be implemented using the plurality of function blocks, the plurality of primitive cells, and the at least one interconnect layer to thereby permit prefabrication of the plurality of function blocks; and interconnecting, prior to receipt of the custom circuit design, at least some of the plurality of primitive cells to each other by at least one interconnect in the at least one interconnect layer, and leaving disconnected, prior to receipt of the custom circuit design, the plurality of function blocks from each other.