Patent ID: 7565564

Claim:
A switching circuit for dynamically switching a first host clock signal to a second host clock signal, the switching circuit comprising: an adjustment unit, transmitting a first adjustment signal and a second adjustment signal; an oscillator, generating a fundamental clock signal; a first phase-locked loop, receiving the fundamental clock signal to generate the first host clock signal correspondingly according to the first adjustment signal; a second phase-locked loop, receiving the fundamental clock signal to generate the second host clock signal correspondingly according to the second adjustment signal; a switch-recording unit, transmitting a switch-recording signal according to the second adjustment signal; a control unit, transmitting a switch-triggering signal according to the switch-recording signal and a first control signal, the first control signal driving a central processing unit to enter a sleep state, in which a front side bus ceases to operate; and an output switch unit, switching the first host clock signal to the second host signal for adjusting the operating frequency of the front side bus according to the switch-triggering signal when the central processing unit enters the sleep state.