Patent ID: 8689037

Claim:
A method of controlling core clocks in a multicore central processing unit (CPU), the method comprising: executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core of the multicore CPU; and executing a first DCVS algorithm on a first core of the multicore CPU, wherein: executing the zeroth DCVS algorithm on the zeroth core causes the multicore CPU to monitor an idle time of the zeroth core and vary a zeroth clock frequency of a zeroth clock associated with the zeroth core based on the idle time and independent of a first clock frequency of a first clock associated with the first core, and executing the first DCVS algorithm on the first core causes the multicore CPU to monitor a memory-boundedness of a workload of the first core and vary the first clock frequency of the first clock associated with the first core based on the memory-boundedness of the workload and independent of the zeroth clock frequency of the zeroth clock.