Patent ID: 7567456

Claim:
A page buffer for an electrically programmable memory including a plurality of memory cells forming a plurality of memory pages, the page buffer comprising a plurality of storage units for at least temporarily storing data read from or to be written into the memory cells of selected memory pages of said plurality, each storage unit comprising a first latch and a second latch, operative with a selected bit line of memory cells and with a respective data line to an output interface of the memory, wherein each of said first and second latches includes: a first latch input/output terminal connected to a first terminal of a first switch device having a control terminal to receive an input control signal corresponding to a data bit to be written; and a second latch input/output terminal connected to a first terminal of a second switch device having a control terminal to receive a signal corresponding to a logic complement of the input control signal, wherein the first and second switch devices each have a second terminal connected to the respective data line for transferring a set voltage provided therethrough to the first or second latch input/output terminal depending on the data bit to be written into the latch in response to the input control signal and wherein one of the first and second switch devices is further configured to transfer onto the respective data line a read data bit from the latch in response to an output control signal received by the control terminal.