Patent ID: 8912812

Claim:
A diagnostic tool for testing a wafer-level integrated circuit (IC) device coupled to testing electronics, the diagnostic tool comprising: a first diagnostic tool adapted to be located at a first interface between a wafer probe and the wafer-level IC device, the first diagnostic tool comprising; a first compliant printed circuit comprising a flexible polymeric sheet with a plurality of contact pads contacting distal ends of probe members in the wafer probe at a first interface and raised probe members located on the compliant printed circuit in an array contacting a plurality of contact pads on the wafer-level IC device at the first interface; a plurality of conductive traces printed on the first compliant printed circuit and electrically coupling to the plurality of contact pads; and a plurality of electrical devices printed on the first compliant printed circuit at a position external to the first interface, the electrical devices coupled to the conductive traces and configured to provide one or more of continuity testing at the first interface or functionality testing of the wafer-level IC device.