Patent ID: 7102208

Claim:
A semiconductor package, comprising: a leadframe having: a chip paddle defining opposed top and bottom surfaces and a plurality of sides and corners; and at least two sets of leads extending along respective ones of the sides of the chip paddle in spaced relation thereto, each set of leads including at least two outer leads and at least one inner lead disposed between the outer leads, the inner and outer leads of each set each defining opposed top and bottom surfaces, with at least portions of the bottom surfaces of the outer leads of each set each being of a first length and at least a portion of the bottom surface of the inner lead of each set being of a second length which is unequal to the first length; a semiconductor chip mounted to the top surface of the chip paddle and electrically connected to at least one of the inner and outer leads; and an encapsulation material covering the leadframe and the semiconductor chip such that the portions of the bottom surfaces of the inner and outer leads of each set which are of the second length and the first length, respectively, are completely exposed in the encapsulation material and are arranged to intersect a single straight line extending between the outer leads.