Patent ID: 7181595

Claim:
A method for decoding a first composite packet in a processor, said method comprising the steps of: providing assembly code for each one of a plurality of instructions in a first combination of instructions in said first composite packet; matching a template in said first composite packet to a known template corresponding to one of a plurality of known syntaxes that includes multiple stop bits that indicate an end of an issue group and provide chaining information, wherein said plurality of known syntaxes are arranged as a plurality of first level nodes in a tree structure, wherein each of a plurality of second level nodes in said tree structure includes a combination of instruction types, and wherein each of a plurality of third level nodes in said tree structure includes an instruction type, wherein a plurality of paths extends between node levels and wherein each node of said plurality of first level nodes and said plurality of second level nodes has a path to a node of a different node level; matching each term in said one of said plurality of known syntaxes against a respective term in a resolved packet syntax using said tree structure, wherein said step of matching said one of said plurality of known syntaxes comprises a sub step of direct matching, followed by a sub step of indirect matching; using said resolved packet syntax to determine assembly code associated with execution of said first combination of instructions; providing assembly code associated with execution of said first combination of instructions.