Patent ID: 6934212

Claim:
A semiconductor apparatus formed on one semiconductor substrate, comprising: a plurality of memory cells, each including a capacitor having first and second electrodes for holding an information voltage, a MOSFET having a gate connected to the first electrode of the capacitor and having the information voltage of the capacitor supplied to the gate, and a writing transistor for supplying the information voltage to the capacitor; a plurality of word lines connected to the second electrode of the capacitor and a gate of the writing transistor; and a plurality of bit lines disposed in a direction orthogonal to the word lines for receiving a writing voltage and a source output of the MOSFET, wherein when the semiconductor apparatus is on a first mode, an OFF potential of the word lines is set to be a first potential, when the semiconductor apparatus is on a second mode, an OFF potential of the word lines is set to be a second potential, when the semiconductor apparatus is on the first and second modes, an ON voltage of the word lines is set to be a third voltage for turning OFF the writing transistor when a signal corresponding to the information voltage is read, and turning ON the MOSFET when the information voltage of the capacitor is at a high level, and to be a fourth voltage for turning ON the writing transistor when a writing voltage is supplied from the bit lines to the capacitor, and a current channel of the writing transistor is set in a direction vertical to the semiconductor substrate.