Patent ID: 8729941

Claim:
An input buffer, comprising: a differential amplifier having first and second input nodes and an output node, the differential amplifier being configured to generate an output signal at the output node that is substantially in phase with an input signal applied to the first input node and substantially out of phase with an input signal applied to the second input node, the differential amplifier further having third and fourth input nodes, the third input node being functionally in parallel with the first input node, and the fourth input node being functionally in parallel with the second input node, the differential amplifier further having fifth and sixth input nodes, the fifth input node being functionally in parallel with the first input node, and the sixth input node being functionally in parallel with the second input node; and a feedback circuit coupled to the output node and the first and second input nodes, the feedback circuit being configured to apply a first feedback signal to the third input node that is substantially in phase with the output signal and to apply a second feedback signal to the fourth input node that is substantially out of phase with the output signal, wherein the feedback circuit includes a first inverter and a second inverter, the first inverter having an input coupled to the output node of the differential amplifier and having an output coupled to the second input node, the second inverter having an input coupled to the output of the first inverter and having an output coupled to the fourth input node.