Patent ID: 7560324

Claim:
A method of fabricating a drain-extending MOS transistor, the method comprising: providing a semiconductor body having a channel region therein, the channel region being of a first conductivity type and having first and second opposite lateral sides; forming a well of a second conductivity type extending laterally outward only from the second lateral side of the channel region in the semiconductor body; forming a gate having first and second lateral sides, the gate including a thin gate dielectric positioned only at a location of the gate, the gate and thin gate dielectric overlying the channel region and a portion of the well; forming a source of the second conductivity type in the semiconductor body along the first lateral side of the channel region, the source being proximate the first lateral side of the gate; forming a drain of the second conductivity type spaced from the second lateral side of the gate in the well; and forming a voltage drop region in the well extending laterally between a first end proximate the second lateral side of the gate to a second end laterally spaced from the drain to shift high electric fields toward the drain and away from the gate thereby mitigating degradation of the gate dielectric in a high voltage operation, the voltage drop region comprising dopants of the second conductivity type, and wherein an operational voltage drop region has fewer dopants of the second conductivity type than that portion of the well at the same depth, wherein forming the voltage drop region comprises using an existing mask and processing step and exposing at least a portion of the voltage drop region while performing a source/drain implant for another transistor using dopants of the first conductivity type.