Patent ID: 8049654

Claim:
An apparatus comprising: a capacitive digital-to-analog converter (CDAC) that includes: a plurality of capacitors that are each coupled to a common node; and a plurality of switches, wherein each switch is coupled to at least one of the capacitors; a comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the comparator is coupled to the common node; and a controller that is coupled to the comparator and each of the switches, wherein the controller is configured to control the voltage level on the common node during a plurality of successive approximation steps by consecutively switching the capacitors to at least one of a first reference voltage and a second reference voltage in response to the bit decisions of the comparator, and wherein the controller performs at least one error correction step after an approximation step so as to limit an error voltage on the common node to an amount that is equal to or lower than a maximum voltage change on the common node that can be achieved during subsequent steps.