Patent ID: 8877589

Claim:
A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising: providing a pair of trench isolation regions extending into a background doped semiconductive material over a substrate; ion implanting conductivity enhancing impurity dopant into the background doped semiconductive material between the pair of trench isolation regions to form highest dopant concentration portions of the pair of source/drain regions, the highest dopant concentration portions comprising 1×10 13 to 1×10 16 ions/cm 3 ; conducting a dopant activation anneal, the semiconductive material having an exposed uppermost surface during the implanting and the anneal; prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion proximate each highest dopant concentration portion, the conductivity modifying impurity dopant being of an opposite conductivity type than dopant in the highest conductivity concentration portions; after the dopant activation anneal, etching an opening through the highest dopant concentration portion and lower dopant portion and into the background doped semiconductive material, the opening extending to a first depth that is less than a second depth to which the isolation regions extend; and depositing material from which a conductive portion of the transistor gate is made into the opening.