Patent ID: 7339236

Claim:
A semiconductor device comprising: a semiconductor substrate; an insulating layer which is formed on said semiconductor substrate; an n type semiconductor layer which is formed on said insulating layer; a p channel type MOS transistor which is formed in said semiconductor layer; and an n type impurity region which is formed in said semiconductor layer and has an impurity concentration higher than that of said semiconductor layer, wherein said MOS transistor has p type source and drain regions which are formed in an upper surface of said semiconductor layer at a distance from each other, said impurity region, at least, is formed over the entire bottom of said source region at a portion directly below said source region and is formed directly below said semiconductor layer between said source region and said drain region, and a peak position of the impurity concentration in said impurity region is set below a lowest end of said source region at a portion directly below the upper surface of said semiconductor layer between said source region and said drain region.