Patent ID: 7274046

Claim:
A tri-gate semiconductor device, comprising: a semiconductor substrate; a first gate located over said semiconductor substrate and over a high voltage gate dielectric within a high voltage core region; a second gate located over said semiconductor substrate and over a low voltage gate dielectric within a low voltage core region, wherein said semiconductor substrate further includes a low concentration of nitrogen near a surface thereof within said low voltage core region, and further wherein said low concentration of nitrogen ranges from about 1E18 ions/cm 2 to about 1E21 ions/cm 2 ; a third gate located over said semiconductor substrate and over an intermediate voltage gate dielectric within an intermediate voltage core region, wherein a thickness of said intermediate voltage gate dielectric is within about 0.1 nm to about 0.2 nm of a thickness of said low voltage gate dielectric; source/drains formed within said semiconductor substrate and associated with each of said first, second and third gates; and interconnects formed within dielectric layers located over said first, second and third gates that interconnect said first, second and third gates and said source/drains to form an operative tri-gate integrated circuit.