Patent ID: 7970019

Claim:
A process of synchronizing events on a packet switched network by: maintaining a master clock at a master node of a packet switched network of other interconnected nodes including one or more other nodes for converting analog audio input to digital audio packets and also including one or more other nodes for converting the digital audio packets to analog audio output; encoding a set N of between 50 and 250 high priority timing packets for transmission from the master node to one or more other nodes on the packet switched network and sending out the set of said N timing packets onto the network at pseudo-random intervals, within a time T of between 200 milliseconds to 1 second for the set of N timing packets, to increase a probability that at least some of the timing packets arrive at the one or more other nodes after traversing the packet switched network with a minimum network transit delay time; and at the one or more other nodes, filtering the timing packets received to determine packets with a least timing error by finding the minimum network transit time from the set of the N of timing packets sent between the master node and the one or more other nodes, by finding a minimum time offset from the set of the N timing packets; and then using only the timing packets received with the least timing error to synchronize a local clock maintained at each of the one or more other nodes, to the clock at said master node.