Patent ID: 8497507

Claim:
An array substrate for a liquid crystal display device, comprising: a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively, wherein the active layer is exposed through the first distance between the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively, the source electrode being connected to the data line; a passivation layer on the substrate and directly contacting a top surface of the first and second barrier patterns, wherein the passivation layer includes a drain contact hole; and a pixel electrode on the passivation layer and connected to the drain electrode via the drain contact hole, wherein the first and second barrier patterns include at least one of molybdenum (Mo) and molybdenum-titanium alloy (MoTi).