Patent ID: 8120152

Claim:
A semiconductor package comprising: a die pad; a first plurality of leads circumscribing the die pad, wherein each of the first plurality of leads includes: an upper sloped portion; a lower sloped portion; and a peak located between the upper sloped portion and the lower sloped portion of each of the first plurality of leads; a second plurality of leads disposed in corner regions of the package, wherein each of the second plurality of leads includes: an upper sloped portion; a lower sloped portion; and a peak located between the upper sloped portion and the lower sloped portion of each of the second plurality of leads; and a package body; wherein a marker lead included in the second plurality of leads has an exposed lower surface that is geometrically distinct from exposed lower surfaces of the first plurality of leads; and wherein the marker lead has a different shape from each of the remaining ones of the second plurality of leads.