Patent ID: 7045413

Claim:
A method of manufacturing a semiconductor integrated circuit, said method comprising: forming a device isolation layer in a semiconductor substrate to define first and second active regions; forming a plurality of first gate patterns that extend across the first active region and the device isolation layer, regions between the first gate patterns including a first space having a first width and a second space having a second width greater than the first width; selectively removing the device isolation layer exposed by the first space; forming a line-shaped first impurity region and an island-shaped second impurity region at the surface of the semiconductor substrate exposed by the first space and at the first active region exposed by the second space, respectively; forming a second gate pattern that extends across the second active region; forming low concentration source/drain regions at the second active region located on both sides of the second gate pattern; forming spacers on sidewalls of the second space and on sidewalls of the second gate pattern as well as a spacer layer pattern filling the first space; forming high concentration source/drain regions adjacent the low concentration source/drain regions at the second active region; removing said spacers to expose the sidewalls of the second space and the second gate pattern and leaving a recessed spacer layer pattern in the first space; and forming a conformal etching stop layer on the semiconductor substrate having the recessed spacer layer pattern.