Patent ID: 7803667

Claim:
A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure, comprising: providing a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer, wherein the patterned solder resist layer covers the recesses of the conductive layer; removing a part of the conductive layer to form a patterned conductive layer; bonding a plurality of chips onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer; electrically connecting the chips to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer; forming at least one molding compound to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires; and separating the molding compound and the patterned conductive layer.