Patent ID: 7135766

Claim:
A power device comprising: a silicon substrate having at least two transistors and an ohmic contact region circumscribing the at least two transistors; at least one dielectric layer formed over the silicon substrate; a common metal layer formed over the at least one dielectric layer and electrically coupled to a first region of each of the at least two transistors; an isolation metal layer formed over the at least one dielectric layer above the ohmic contact region and circumscribing the common metal layer and electrically coupled to the ohmic contact region; a first bump formed over the common metal layer; and a second bump formed over the isolation metal layer; wherein when the power device is mounted on a second substrate using the first and second bumps, the first bump and the common metal layer provide a low inductance ground and heat sink path from the silicon substrate to the second substrate, and the second bump, the isolation metal layer, and the ohmic contact region form an isolation structure isolating the at least two transistors from external devices.