Patent ID: 7037776

Claim:
A method of fabricating a DRAM cell, comprising the steps of: providing a substrate; forming an isolation structure within the substrate; patterning the substrate to form nodes adjacent the isolation structure; forming doped silicon glass node plugs within the nodes; forming respective N diffusion regions within substrate adjacent the doped silicon glass node plugs using a thermal drive-in process, wherein the N diffusion regions are exposed around top portions of the doped silicon glass node plugs; removing the doped silicon glass node plugs; forming a gate dielectric layer over the patterned substrate, lining the nodes; forming a conductive layer over the gate dielectric layer, filling the nodes; patterning the conductive layer to form: a top electrode capacitor within the nodes; and respective word lines over the substrate adjacent the top electrode capacitor; each word line having exposed side walls; and forming source/drain regions adjacent the word lines, wherein the source/drain regions are electrically connected to the N diffusion regions.