Patent ID: 8492900

Claim:
A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a third internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first local power distribution network over said silicon substrate and in said dielectric layer, wherein said first local power distribution network is connected to said first internal circuit and to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first local power distribution network; a second local power distribution network over said silicon substrate and in said dielectric layer, wherein said second local power distribution network is connected to said third internal circuit; a passivation layer over said dielectric layer; a first via in said passivation layer, wherein said first via is connected to said first local power distribution network; a second via in said passivation layer, wherein said second via is connected to said second local power distribution network; and a global power distribution network over said passivation layer, wherein said global power distribution network is connected to said first and second vias, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network, and wherein said second internal circuit is connected to said third internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network.