Patent ID: 7113431

Claim:
A method of erasing to maintain complimentary bit disturb control of a group of complementary bit-pairs of memory cells, each bit having multiple programming levels, the method comprising: comparing the program levels of a programmed bit and a complimentary unprogrammed bit within the bit-pairs of the group of memory cells to determine a disturb level for each bit-pair of the group; determining a combined disturb level representative of the individual disturb levels determined for the bit-pairs of the group; setting a drain voltage and a number of program passes for a target pattern to be stored in the memory cell based on the combined disturb level determined for the group; and erasing the unprogrammed bit of the bit-pairs to one of the program levels using the drain voltage and the number of program passes of the target pattern based on the combined disturb level to compensate for the disturbance level that exists between the complementary bit-pairs of the group of memory cells.