Patent ID: 8507995

Claim:
A semiconductor memory device comprising a static memory cell composed of four MOS transistors and two load resistance elements arranged on a substrate, wherein: the four MOS transistors function as first and second NMOS access transistors for accessing the memory cell and as first and second NMOS driver transistors for driving memory nodes to write and read memory cell data, wherein the first and second NMOS access transistors each comprise an N-type first diffusion layer, a first columnar semiconductor layer and an N-type second diffusion layer arranged vertically in tiers in an ascending order on the substrate, the first columnar semiconductor layer being formed with a first gate surrounding the first columnar semiconductor layer, and wherein the first and second NMOS driver transistors comprise an N-type third diffusion layer, a second columnar semiconductor layer and an N-type fourth diffusion layer arranged vertically in tiers in an ascending order on the substrate, the second columnar semiconductor layer being formed with a second gate surrounding the second columnar semiconductor layer; the first NMOS access transistor and first NMOS driver transistor adjoin each other; the second NMOS access transistor and second NMOS driver transistor adjoin each other; the first diffusion layer formed at a bottom of the first NMOS access transistor is connected directly to the third diffusion layer formed at a bottom of the first NMOS driver transistor, wherein the directly connected first and third diffusion layers, formed at the bottoms of the first NMOS access transistor and the first NMOS driver transistor, function as a first memory node for storing data; the first diffusion layer formed at a bottom of the second NMOS access transistor is connected directly to the third diffusion layer formed at a bottom of the second NMOS driver transistor, wherein the directly connected first and third diffusion layers, formed at the bottoms of the second NMOS access transistor and the second NMOS driver transistor, function as a second memory node for storing data; and the two load resistance elements are provided, respectively, on the directly connected first and third diffusion layers, formed at the bottoms of the first NMOS access transistor and the first NMOS driver transistor, functioning as the first memory node and on the directly connected first and third diffusion layers, formed at the bottoms of the second NMOS access transistor and the second NMOS driver transistor, functioning as the second memory node.