Patent ID: 8253477

Claim:
A voltage boost circuit, comprising: a first clock signal which toggles between a first voltage V 1 and a second voltage V 2 , where V 1 <V 2 ; an output node having an associated output node voltage; a first PMOS FET coupled between said first clock signal and said output node, said first PMOS FET including an nwell in which its drain, source and bulk regions reside; a semiconductor device coupled between said output node and a supply voltage; a capacitance, the first terminal of which is coupled to said output node, said voltage boost circuit arranged such that the voltage applied to the top (clock signal side) of said first PMOS FET toggles between ˜V 1 and ˜V 2 in response to said first clock signal; and a first delay circuit which is coupled to the second terminal of said capacitance and arranged to toggle the voltage on said second terminal to ˜V 2 a predetermined amount of time after the voltage applied to the top of said first PMOS FET toggles to ˜V 2 and to toggle the voltage on said second terminal to ˜V 1 a predetermined amount of time after the voltage applied to the top of said first PMOS FET toggles to ˜V 1 ; said voltage boost circuit arranged such that: said capacitance and thereby said output node is initially charged to ˜V 2 when the voltage applied to the top of said first PMOS FET toggles to ˜V 2 in response to said first clock signal, and said output node voltage is increased to a voltage greater than V 2 when the output of said first delay circuit toggles to ˜V 2 said predetermined amount of time after the voltage applied to the top of said first PMOS FET toggles to ˜V 2 ; said voltage boost circuit arranged such that the junction subjected to said voltage greater than V 2 is the nwell-substrate junction of said first PMOS FET.