Patent ID: 7937510

Claim:
A data compression architecture, comprising: a shift register structure comprising first and second parallel paths, each of said paths comprising a respective plurality of shift register elements for storing previously received data characters, each shift register element in the first parallel path being paired with a respective shift register element in the second parallel path; an input shift register for receiving and storing input data characters in pairs comprising first and second pairs during successive clock cycles, and for applying said stored pairs of input data characters to the register elements in said first and second parallel paths; logic circuitry associated with each of said shift register element pairs, for (i) comparing the first pair of said received input data characters with each of the previously received data characters stored in the pairs of shift register elements and with consecutive previously received data characters stored in adjacent pairs of shift register elements; (ii) detecting a match between said received input data characters and said previously received data characters stored in the pairs of shift register elements during one or more clock cycles, and (iii) determining a length of a sequence of received input data characters matching said stored previously received data characters by determining a number of clock cycles during which a match is detected in a particular pair of shift register elements, and applying a correction factor based on a type of match detected during a first clock cycle at a beginning of said sequence and during a later clock cycle at the an end of said sequence.