Patent ID: 7103803

Claim:
A method for verification of command processing in a computer system design having a multiple priority command queue, the method comprising: (a) inputting over time, multiple simulated requests into a simulation model of said computer system, each request having a priority and each request comprising a stage ( 1 ) request and tag transaction, a stage ( 2 ) command ID transaction, a stage ( 3 ) command system ID transaction, a stage ( 5 ) system combined response transaction and a stage ( 7 ) completion tag transaction; (b) sorting the priority of each request based on the stage ( 1 ) request and tag transaction of each request; (c) issuing an error if any particular stage ( 2 ) command ID transaction is not a transaction of a request previously sorted in step (b) or is not a retry stage ( 2 ) command ID; (d) issuing an error or ignoring a particular stage ( 3 ) command system ID transaction if said particular stage ( 3 ) command system ID transaction is not a transaction of a request having a previously issued stage ( 2 ) command ID transaction; (e) issuing an error or ignoring a particular stage ( 5 ) system combined response if said particular stage ( 5 ) system combined response transaction is not a transaction of a request having a previously issued stage ( 3 ) command system ID transaction; and (f) issuing an error if any particular stage ( 7 ) completion tag transaction is not a transaction of a request having a previously issued stage ( 5 ) system combined response transaction.