Patent ID: 7117238

Claim:
A pipelined circuit for pipelined processing of graphics data for generating an output word in response to an input word indicative of an input value and a control word, where the output word is indicative of a Taylor's series approximation of a reciprocal of the input value or a reciprocal of a square root of the input value depending on the control word, said circuit including: a first pipeline stage configured to respond to the input word and the control word by asserting a first set of values, the values in the first set including a Taylor's series coefficient for each term of a Taylor's series approximation of one of the output word and a mantissa of the output word, where the output word is indicative of a Taylor's series approximation of a reciprocal of the input value or a reciprocal of a square root of the input value depending on the control word; and at least one additional pipeline stage configured to generate the approximation of said one of the output word and the mantissa of the output word by performing at least one of addition, multiplication, and subtraction on a second set of values, wherein the values in the second set include at least one of the values in the first set and at least one intermediate value generated by the at least one additional pipeline stage in response to values including at least one other one of the values in the first set.