Patent ID: 7834661

Claim:
A level shifter, comprising: an input unit including a current-starved inverter configured to generate a control signal in response to an input signal and a bias voltage, the input unit being powered by a first power supply voltage; and a driving unit configured to generate an output signal in response to the control signal, the output signal having a voltage level higher than the input signal, the driving unit being powered by a second power supply voltage higher than the first power supply voltage, wherein the driving unit comprises: a current mirror configured to pull up a voltage level of the output signal in response to the control signal; and an NMOS driving transistor configured to pull down the voltage level of the output signal in response to the control signal, wherein the current-starved inverter comprises: a P-type MOS (PMOS) current-starving transistor coupled to the first power supply voltage; an N-type MOS (NMOS) current-starving transistor coupled to a ground voltage; and an inverter coupled between the PMOS current-starving transistor and the NMOS current-starving transistor.