Patent ID: 7060195

Claim:
A method for forming a liquid crystal display panel (LCD panel), the method comprising: providing a substrate, the substrate comprising a pixel array area, a gate pad area, and a source pad area positioned on a surface of the substrate and used for forming a plurality of pixels, a plurality of gate pads, and a plurality of source pads; depositing a first metal layer on the substrate; performing a first photo-etching-process (PEP) on the first metal layer to form a plurality of gate electrodes, a plurality of gate bottom pad electrodes, and a plurality of source bottom pad electrodes inside the pixel array area, the gate pad area, and the source pad area; sequentially forming an insulating layer and a doped semiconductor layer on the substrate; performing a second PEP on the doped semiconductor layer to form a plurality of active layers inside the pixel array area, and simultaneously remove portions of the doped semiconductor layer inside the gate pad area and the source pad area; depositing a second metal layer on the substrate; performing a third PEP on the second metal layer to form a plurality of source electrodes and a plurality of drain electrodes inside the pixel array area, and simultaneously form a plurality of gate top pad electrodes and a plurality of source top pad electrodes inside the gate pad area and the source pad area, wherein the gate top pad electrodes and the source top pad electrodes are electrically connected to the corresponding gate bottom pad electrodes and the corresponding source bottom pad electrodes respectively for performing an electrical testing process; forming a passivation layer on the substrate; performing a fourth PEP on the passivation layer to form a plurality of via holes inside the pixel array area, and simultaneously remove portions of the passivation layer inside the pixel array area; forming a plurality of contact holes inside the gate pad area and the source pad area; forming a transparent conductive layer on the substrate to fill the via holes inside the pixel array area and the contact holes inside the gate pad area and the source pad area; and performing a fifth PEP to define patterns of the transparent conductive layer.