Patent ID: 8243485

Claim:
A semiconductor apparatus having a plurality of chips, comprising: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate a chip identification signal of the corresponding one of the plurality of chips, wherein the frequency-divided signal is generated by frequency-dividing the clock signal, and the clock signal and the frequency-divided signal are transmitted via a plurality of through silicon vias (TSVs); and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal enables the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.