Patent ID: 8853023

Claim:
A method for stressing a pattern having a pattern surface with pattern dimensions, in a layer of semiconductive material on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy Si x Ge y with x and y being molar fractions, and a buried layer of silicon oxide, the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy Si x Ge y , the method comprising: determining a first function t SiGe =f(W), wherein t SiGe is an optimum thickness of the layer of alloy Si x Ge y as a function of a pattern dimension (W), thereby obtaining a maximum stress (S0 ZZ ) in said pattern, said optimum thickness being independent of the molar fraction y; determining a second function tc SiGe =g(y) wherein tc SiGe is a critical thickness of the layer of alloy Si x Ge y beyond which dislocations appear in said stress layer for a given molar fraction y; determining the molar fraction y by equality of the thicknesses t SiGe =tc SiGe , thereby defining, for a given pattern dimension (W), an optimum pair of values (t SiGe , y); fabricating the stack including the stress layer of alloy Si x Ge y using the optimum pair of values (t SiGe , y); and etching at the periphery of a surface of dimensions greater than or equal to those of said pattern surface dimensions, of the buried layer of silicon oxide and of the stress layer of alloy Si x Ge y over at least a part of the depth of said layer of alloy.