Patent ID: 7620789

Claim:
A memory controller comprising: a sequencing unit for receiving a plurality of memory access request signals from a plurality of requestors, the sequencing unit receiving the memory access request signals in a sequence corresponding to an order in which the requests were received from the requestors, wherein the memory access request signals comprise read requests and/or write requests; a rearranging unit for rearranging the sequence of the memory access request signals in response to detected memory access conflicts between temporally proximate non-executed requests in the sequence, the rearranging of memory access request signals including moving a conflicted memory access request ahead of its received position in the sequence, and whereby execution of the memory access requests is to be performed in the rearranged sequence; an execution unit for extracting a plurality of commands from the memory access requests and executing the plurality of commands, each memory access request comprising either a read or write command and data control commands, the plurality of commands being arranged in an execution order corresponding to the rearranged sequence, the execution order further arranged such that a data control command and the read or write command from a memory access request are separated and the data control command is placed ahead in the execution order to be executed before or while a read or write command from a different memory access request ahead in the execution order is executed and also such that after the read or write command of the different memory access request ahead in the execution order is executed, the separated read or write command of the memory access request is executed; and a reordering unit for reordering executed read requests into the order in which the requests were originally received, whereby the data obtained by the executed read requests are to be returned to the requestors in the reordered sequence.