Patent ID: 7102864

Claim:
A latch-up-free ESD protection circuit using an SCR, comprising: an SCR ( 10 ) being connected across an input pad (PAD) and a negative power supply V SS ; a turn-on switch ( 20 ) being connected across a positive power supply V DD and a gate of the SCR ( 10 ) to initiate the SCR ( 10 ); a turn-off switch ( 30 ) being connected across the positive power supply V DD and the gate of the SCR ( 10 ) to switch off the SCR ( 10 ); a transistor gating circuit ( 40 ) being connected across the positive power supply V DD and the negative power supply V SS , and also being connected to the turn-on switch ( 20 ) and the turn-off switch ( 30 ); whereby when overvoltage stress develops over the input pad (PAD) in a forward fast-transient mode, the transistor gating circuit ( 40 ) initiates the turn-on switch ( 20 ) to trigger the SCR ( 10 ) into conduction, so that high voltage over the input pad (PAD) is rapidly decreased to a holding voltage level of the SCR ( 10 ), thus the ESD protection circuit is immune to latch-up.