Patent ID: 8048698

Claim:
A method for manufacturing a thin film transistor array substrate, comprising: providing a substrate, defining a display area, a transition area and a pad area; forming a patterned first metal layer in the display area, the transition area and the pad area, wherein the patterned first metal layer includes a gate line and a gate electrode disposed in the display area, a data connecting line disposed in the transition area, and a data pad and a gate pad disposed in the pad area; forming a patterned first insulation layer to cover the substrate and the patterned first metal layer, and defining a first opening and a second opening in the pad area and a third opening in the transition area; wherein the first opening, the second opening and the third opening are adapted to expose a portion of the gate pad, a portion of the data pad and a portion of the data connecting line respectively; forming a patterned semiconductor layer on the patterned first insulation layer upon the gate electrode; forming a patterned second metal layer on the patterned first insulation layer and covering a portion of the patterned semiconductor layer, wherein the patterned second metal layer includes a data line, a source electrode electrically connected to the data line and a drain electrode, and the data line is adapted to cover the third opening for electrical connection to the data connecting line; and forming a patterned second insulation layer and a patterned planarization layer to cover the display area and the transition area, wherein the patterned second insulation layer and the patterned planarization layer have a drain contact opening for exposing a portion of the drain electrode.