Patent ID: 7638881

Claim:
A chip package, comprising: a chip having a plurality of chip pads disposed on a surface of the chip; a package substrate having a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer, wherein the first substrate pads and the second substrate pads are disposed on a surface of the package substrate, wherein the surface bonding layer is disposed on the first substrate pads and the second substrate pads, wherein the second substrate pad has a first region and a second region, and the surface bonding layer covers the first region of the second substrate pad and does not cover the second region of the second substrate pad; and a plurality of bumps disposed between the chip pads and the surface bonding layer, wherein the chip is electrically connected to the package substrate through the bumps, each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps, wherein the package substrate comprises: a first solder mask layer disposed on the second substrate pads, having a plurality of openings and covering the second region of the second substrate pads, and the surface bonding layer being disposed in the openings; and a second solder mask layer disposed on the surface of the package substrate and exposing the first substrate pads and the second substrate pads.