Patent ID: 8688917

Claim:
An apparatus comprising: logic to encounter a memory access operation referencing a memory address associated with a data item that is to be monitored; a data array of a cache memory including a plurality of lines, wherein a number of lines of the plurality of lines is to hold the data item responsive to the logic encountering the memory access operation; and a coherency state array of the cache memory including a state entry corresponding to each of the plurality of lines, wherein each of the state entries, which correspond to the number of lines to hold the data item, are to be updated to represent a monitored coherency state in response to the first number of lines to holding the data item, wherein the monitored coherency state includes a coherency state selected from a group consisting of a modified read (MR) state, a modified write (MW) state, a modified read write (MRW) state, an exclusive read (ER) state, and a shared read (SR) state, and wherein a state entry associated with a line that is not one of the number of lines to represent an unmonitored state, and wherein the unmonitored state includes a Modified Exclusive Shared and Invalid (MESI) state.