Patent ID: 8372743

Claim:
A process of forming an integrated circuit, comprising the steps of: forming a dielectric layer over a substrate; defining a plurality of parallel route tracks having a pitch distance in said dielectric layer; forming a first interconnect pattern in said plurality of parallel route tracks including a first lead pattern located in a first route track of said plurality of parallel route tracks; forming a second interconnect pattern in said plurality of parallel route tracks including a second lead pattern located in a second route track of said plurality of parallel route tracks immediately adjacent to said first route track; forming a third interconnect pattern in said plurality of parallel route tracks including a third lead pattern located in said first route track, wherein said third lead pattern is separated from said first lead pattern in the first route track by a distance less than one and one-half times a space between said first lead pattern and said second lead pattern; wherein said first interconnect pattern, said second interconnect pattern and said third interconnect pattern are formed using three distinct photolithography processes which have a dipole illumination source capable of resolving patterns in alternate instances of said plurality of parallel route tracks and not capable of resolving patterns in immediately adjacent instances of said plurality of parallel route tracks; and forming metal interconnect lines in said dielectric layer as defined by said first interconnect pattern, said second interconnect pattern and said third interconnect pattern.