Patent ID: 7684244

Claim:
A memory array circuit comprising: a plurality of word lines including a first word line and a second word line; a plurality of bit-lines; and a plurality of memory cell transistors including: a first memory cell transistor and a second memory cell transistor, wherein the first and second memory cell transistors include gates connected to the first word line, the first memory cell transistor includes a source connected to the first bit-line and a drain connected to the second bit-line, and the second memory cell transistor includes a source connected to the first bit-line and a drain connected to the first bit-line; and a third memory cell transistor and a fourth memory cell transistor, wherein the third and fourth memory cell transistors include gates connected to the second word line, the third memory cell transistor includes a drain connected to the first bit-line and a source connected to the second bit-line, and the fourth memory cell transistor includes a source connected to the first bit-line and a drain connected to the first bit-line.