Patent ID: 7480489

Claim:
A processor within a wireless terminal operable to perform data compression and decompression according to a data compression protocol, comprising: an interface that receives incoming information to be compressed or decompressed according to the data compression protocol; a processing module operably coupled to the interface; a data compression/decompression accelerator module operably coupled to the processing module, wherein the data compression/decompression accelerator module includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module; and shared memory operably coupled to the processing module and to the data compression/decompression accelerator module, wherein: the processing module is to store the information in the shared memory for retrieval by the data compression/decompression accelerator module and the processing module to generate an instruction to the data compression/decompression accelerator module that includes a pointer to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target for the performed process; the processing module and the data compression/decompression accelerator module are contained within a single Integrated Circuit (IC); and processing of the information to be compressed or decompressed according to the data compression protocol is performed by the data compression/decompression accelerator module as directed by the processing module and processed information is subsequently returned to the shared memory for retrieval by the processing module.