Patent ID: 7995693

Claim:
An apparatus for serial communication using embedded clock signals, comprising: a data divider for dividing a data stream into odd-numbered and even-numbered data streams; a clock-embedded signal generator for generating odd-numbered and even-numbered embedded clock signals by pulse amplitude modulating the odd-numbered and even-numbered data streams and, when an external clock is input, inverting polarities of the pulse amplitude modulated odd-numbered and even-numbered data streams; a clock-embedded signal recovery unit for recovering the odd-numbered and even-numbered data streams by comparing amplitudes of the odd-numbered and even-numbered embedded clock signals with reference voltages, respectively, and recovering synchronization information of the clock by detecting when amplitude polarities of the odd-numbered and even-numbered embedded clock signals are inverted; and a data integrator for integrating the odd-numbered and even-numbered data streams and supplying the result as the data stream.