Patent ID: 8232155

Claim:
A method of forming a device, comprising: forming an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface, wherein a top of the oxide layer is co-planar with a top of the pMOSFET region; patterning a hardmask nitride to cover the oxide layer above the pMOSFET region; removing poly-Si in the nMOSFET region; removing gate oxide in the nMOSFET region to expose a Si layer in a channel area of the nMOSFET region; removing Si to form a cavity in the channel area of the nMOSFET region; performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane; removing the hardmask nitride above the pMOSFET region; depositing an nMOSFET gate dielectric layer; depositing an nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer; depositing poly-Si on top of the nMOSFET metal gate layer, such that a top surface of the Poly-Si is below the top of the oxide layer; removing a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top surface of the oxide layer; and removing the oxide layer.