Patent ID: 7317222

Claim:
A memory cell comprising: a substrate having a channel region; a first dielectric layer over the substrate having a first portion thicker than a second portion, the first portion overlying at least a portion of the channel region; a charge storage layer over the first dielectric layer; a second dielectric layer over the charge storage layer, the second dielectric layer having a first portion thicker than a second portion, the first portion overlying at least a portion of the channel region; a gate electrode over the second dielectric layer and over the channel region, the gate electrode having a first sidewall and a second sidewall; a first sidewall dielectric and a second sidewall dielectric that is continuous with the second dielectric layer and respectively adjacent all of the first sidewall and the second sidewall of the gate electrode, wherein the first sidewall of the gate electrode is over the first portion of the second dielectric layer; and a sidewall spacer formed adjacent the first sidewall dielectric and the second sidewall dielectric.