Patent ID: 8860711

Claim:
A timing controller comprising: a reception unit which receives a video signal and a timing signal from a system; a control signal generation unit which generates a gate control signal and a data control signal with the timing signal, and outputs the gate control signal and the data control signal to a gate driver and a data driver, respectively; an image signal generation unit which realigns the video signal to output a realigned image signal; and a delay compensation unit which performs delay compensation for the realigned image signal with a circuit which is recombined according to a delay compensation value between each data drive Integrated Chip (IC) of the data driver and the image signal generation unit, and outputs the delay-compensated image signal to the each data drive IC, wherein the delay compensation unit includes: a plurality of delayers which are connected to the data drive ICs, respectively, and perform the delay compensation; a buffer which is connected to output terminals of the delayers, and transfers the delay-compensated image signal to the each data drive IC; and a combiner which stores the delay compensation value for recombining a delay compensation circuit of each of the delayers, the delay compensation value being stored for each delayer, and which is configured in plurality to be individually connected to the delayers which are respectively connected to the data drive ICs, or configured as one to store the delay compensation value for all the delayers, and wherein each of the delayers includes a plurality of delay cells and adjusts output timing of the realigned image signal to the data drive IC by processing the realigned image signal through one or more of the plurality of delay cells according to the delay compensation value transferred from the combiner.