Patent ID: 7031204

Claim:
A register apparatus having a two-way gating structure that receives a write enable signal, a chip select signal, at least one read signal, and an address signal for a register, comprising: a two-way gating portion for generating a coded write address by AND-operating a first signal with the address signal, the first signal being generated by AND-operating the chip select signal with the write enable signal, generating a coded read address by AND-operating a second signal with the address signal, the second signal being generated by AND-operating the chip select signal with an inverted signal of the write enable signal, and generating a reader activation signal by AND-operating the at least one read signal with the second signal; a writer for receiving the coded write address, decoding the coded write address, writing data using the decoded write address and the data received from a bus; and a reader for receiving the coded read address, decoding the coded read address, and outputting read signal to the bus using read signals and the decoded read address.