Patent ID: 8395869

Claim:
An ESD protection circuit comprising: a first connection circuit coupled between a pad and a first clamp node; a first EOS control circuit coupled between the first clamp node and an I/O clamp node; and an ESD clamp coupled between the I/O clamp node and a second power node; the ESD clamp working in a triggered conduction mode and a reverse conduction mode; wherein when the ESD clamp detects ESD, the ESD clamp works in the triggered conduction mode conducting the I/O clamp node to the second power node; when a voltage of the I/O clamp node is greater than a first characteristic voltage, the ESD clamp works in the reverse conduction mode conducting the I/O clamp node to the second power node; wherein when the pad receives EOS, the first EOS control circuit provides a first cross voltage between the first clamp node and the I/O clamp node such that the voltage of the I/O clamp node is less than the first characteristic voltage to prevent the ESD clamp from conducting between the I/O clamp node and the second power node, and wherein the ESD protection circuit is built within a single power domain between a first power node and the second power node, and the first clamp node is detached from the first power node.