Patent ID: 8427874

Claim:
A nonvolatile memory, comprising: an array of memory cells organized into a plurality of blocks having interleaving even and odd blocks, each block having a block of word lines for accessing the each block of memory cells; a first voltage bus for all even blocks to access a set of word line voltages; a second voltage bus for all odd blocks to access the set of word line voltages; a block decoder for each pair of adjacent even and odd blocks among the plurality of blocks; a voltage source for supplying the individual voltages; a first voltage switch for switching the voltage source to the first voltage bus when the selected block of word lines is even; a second voltage switch for switching the voltage source to the second voltage bus when the selected block of word lines is odd; and wherein: when a selected block of word lines is to receive the set of word line voltages, a pair of adjacent even and odd blocks containing the selected block of word lines is responsive to a respective block decoder being decoded to enable bus transfer of the first voltage bus to the even block of word lines in the selected pair of adjacent blocks and enabling bus transfer of the second voltage bus to the odd block of word lines in the selected pair of adjacent blocks.