Patent ID: 8327226

Claim:
An apparatus, comprising: a memory that is allocated to reported portions, and overprovisioned portions; an error correction circuit that generates error reports and that communicates with the memory in error correction coded data that has a controllable ECC length that is controlled by an ECC length input; an ECC length update circuit that receives the error reports and that provides an ECC length update to an ECC length table as a function of a history of error reports; an ECC length controller that accesses the ECC length table and that provides an ECC length to the ECC length input; and a memory allocation engine that accesses the ECC length table and that balances a size of the overprovisioned portions to maintain a size of the reported portions, the balancing being performed as a function of an average of ECC lengths in the ECC length table over a time interval in which a size of the memory decreases with accumulated erase cycles of the memory.