Patent ID: 7207018

Claim:
A method of determining a location of possible incorrectly connected polygons in a polygon representation of an integrated circuit having at least one conductive layer comprising steps of: (a) tessellating the polygon representation into predetermined shapes; (b) translating the predetermined shapes into nodes; (c) developing a node network where the nodes are connected directly to one another as a representation of shapes having adjacent edges; (d) identifying a current capacity between connected nodes for the nodes in the node network; (e) selecting at least two nodes in the node network that are electrically connected to possible in correctly connected polygons; (f) running a network flow analysis algorithm between the at least two selected nodes to determine areas of high current density based on the current capacities between adjacent nodes in the node network; and (g) flagging the areas of high current density as points of the possible incorrectly connected polygons for further investigation.