Patent ID: 8141068

Claim:
A computer method using a computer model for compiling a set of instructions for a processor which can process at least two instructions in a cycle, the method comprising: a. selecting, from a set of instructions, a first instruction and a second instruction to be issued to the processor in an issue group; b. generating dependency data reflecting dependencies between the first and second instructions; c. determining whether the dependency data, in any possible order of the instructions, satisfies the model; d. if the dependency data satisfies the model, proceeding to step (e) and, if not, rejecting the second instruction, selecting an alternate second instruction from the set of instructions, and returning to step (c); and wherein the method further comprises between steps (d) and (e): (d1) storing the dependency data for the first and second instructions in a memory; (d2) selecting a third instruction from the set of instructions; (d3) reading the dependency data from the memory and updating the dependency data to reflect dependencies between the first, second, and third instructions; (d4) determining whether the dependency data, in any possible order of the instructions, satisfies the model; (d5) if the dependency data satisfies the model, proceeding to step (e) and, if not, rejecting the third instruction, selecting an alternate third instruction from the set of instructions, and returning to step (d3) e. reordering the instructions in the issue group to an order that satisfies the model, wherein the relative order of instructions in the issue group to be executed within a cycle of the processor affects a function of the processor.