Patent ID: 7479428

Claim:
A method for fabricating an NROM memory cell, the method comprising: creating a plurality of source/drain regions by doping portions of a substrate; forming a nanolaminate gate dielectric layer on the substrate substantially between the plurality of source/drain regions, wherein forming the gate dielectric layer comprises forming one of the following structures: oxide-HfO 2 -oxide, oxide-ZrO 2 -oxide, oxide-ZrSnTiO-oxide, oxide-ZrON-oxide, oxide-ZrAlO-oxide, oxide-ZrTiO 4 -oxide, oxide-Al 2 O 3 -oxide, oxide-La 2 O 3 -oxide, oxide-LaAlO 3 -oxide, oxide-HfAlO 3 -oxide, oxide-HfSiON-oxide, oxide-Y 2 O 3 -oxide, oxide-Gd 2 O-oxide, oxide-Ta 2 O 5 -oxide, oxide-TiO 2 -oxide, oxide-Pr 2 O 3 -oxide, oxide-CrTiO 3 -oxide, or oxide-YSiO-oxide; and forming a gate on the gate dielectric layer; wherein forming the nanolaminate gate dielectric layer on the substrate comprises forming a first oxide layer on the substrate, forming a metal layer on the first oxide layer, converting the metal layer to a dielectric form and forming a second oxide layer on the metal layer after converting it to its dielectric form.