Patent ID: 8541824

Claim:
A field effect transistor (FET) formed in a doped well, the FET having a source, a drain, and a gate stack having a gate length, the FET comprising: a screening region positioned above the doped well, the screening region being doped with a first type of dopant to have a dopant concentration between 5×10 18 to 1×10 20 atoms/cm 3 , the screening region being electrically coupled to the doped well, the screening region being positioned below the gate to set a depletion depth; a substantially undoped semiconductive layer formed above the screening region, the substantially undoped semiconductive layer being adjacent to the screening region; a threshold voltage setting region in the substantially undoped semiconductive layer, the threshold voltage setting region being doped with the first type of dopant, the threshold voltage setting region dopant concentration modifying the threshold voltage of the FET; wherein the gate stack has a length Lg and is positioned above the doped well to control conduction between a drain and a source, the source and the drain being doped with a second type of dopant; wherein at least a portion of the substantially undoped semiconductive layer is maintained as a substantially undoped channel region having a first dopant concentration less than 1/10 of the screening region dopant concentration, with the substantially undoped channel region laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region, and the threshold voltage setting region is vertically positioned between the substantially undoped channel region and the screening region.