Patent ID: 7213127

Claim:
A system for generating addresses for a digital signal processor adapted to execute a program whose program instructions each include an address generation code for accessing at least one memory associated with said processor, said system comprising: a set of address registers; an address calculation circuit which calculates each access address to said at least one memory on the basis of at least one operation code designated by the address generation code of one of said program instructions and the content of one address register selected from said set of address registers, said address calculation circuit being configurable to perform a plurality of predetermined calculation operations in response to a plurality of predefined operation codes; said address generation code defining said operation code to be sent to said address calculation circuit and designating the address register whose content must be subjected to a calculation operation; and a control component which selectively transfers to said address calculation circuit the contents of said address register designated by said address generation code and of said at least one operation code defined by said address generation code; each address register of said set of address registers being further associated with a respective configuration register designated by said address generation code at the same time as said address register; each of said configuration registers containing at least one set of predefined operation codes each adapted to control one of said plurality of predetermined calculation operations in said address calculation circuit; and said system being adapted to select a mode of transmission of the contents of said designated address register and of said at least one defined operation code to said address calculation circuit from several transmission modes that include a predefined mode, said control component in said predefined mode transferring to said address calculation circuit said designated address register and at least one predefined operation code of said set of predefined operation codes contained in the respective configuration register associated with said designated address register, said at least one predefined operation code being selected from said set of predefined operation codes by said control component in dependence upon the value of at least a first bit of said address generation code.