Patent ID: 8522190

Claim:
A computer-implemented method for designing a clock gating mechanism, the method comprising: receiving a first netlist associated with at least a portion of an integrated circuit device, wherein a netlist comprises a description of components within the at least a portion of the integrated circuit device and the connections among the components; generating, with a processing unit, a first model of the clock gating mechanism that is configured to limit current draw within the at least a portion of the integrated circuit device associated with the first netlist; creating a second netlist by modifying the first netlist based on the first model; causing a first set of test vectors to be generated for the second netlist; causing a second set of test vectors to be generated for the first netlist; and applying the first set of test vectors to the second netlist to determine whether the first model of the clock gating mechanism meets one or more performance metrics; wherein the one or more performance metrics includes at least one of a ratio of the number of test vectors included in the first set of test vectors to the number of test vectors included in the second set of test vectors and a ratio of the test coverage associated with the first set of test vectors to the test coverage associated with the second set of test vectors.