Patent ID: 8247856

Claim:
A semiconductor device, comprising: a first transistor formed in a first region of a substrate, the first transistor having a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar; a second transistor formed in a second region of the substrate; an insulation interlayer pattern formed on the first region and the second region to cover the second transistor in the second region and expose an upper surface of the pillar in the first region through an opening in the insulation interlayer pattern, wherein an upper surface of the insulation interlayer pattern in the second region is substantially higher than an upper surface of the impurity region in the upper portion of the pillar in the first region; and a capacitor electrically connected to the impurity region of the first transistor in the first region of the substrate, wherein the capacitor includes a lower electrode which directly contacts the impurity region in the upper portion of the pillar exposed by the insulation interlayer pattern a dielectric layer formed on an entire outer surface of the lower electrode and an upper electrode formed on the dielectric layer, wherein the upper surface of the insulation interlayer pattern in the second region is substantially higher than a lower surface of the lower electrode of the capacitor.