Patent ID: 6992896

Claim:
A multi-chip electronic package comprising: an organic, laminate chip carrier including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material, said chip carrier including a plurality of electrical contacts on a first surface thereof and a plurality of electrical conductors on a second surface thereof, selected ones of said electrical contacts being electrically coupled to selected ones of said electrical conductors; a first, ASIC semiconductor chip positioned directly on said first surface of said organic, laminate chip carrier and electrically coupled to selected ones of said electrical contacts; a second, memory semiconductor chip positioned on said first semiconductor chip such that said first and second semiconductor chips are in a stacked orientation, said second semiconductor chip electrically coupled to selected ones of said electrical contacts by a plurality of wirebond connections; a stiffener member positioned on said first surface of said organic, laminate chip carrier and spacedly positioned about said first and second semiconductor chips; and a heat-sinking member positioned on said stiffener member and substantially over said first and second semiconductor chips.