Patent ID: 8707057

Claim:
A data processing apparatus, comprising: an address bus which outputs address data to be given to a memory apparatus; a scramble unit which scrambles write-in data as confidential data, the write-in data being to be stored into a storage position in the memory apparatus after scrambling, the storage position being identified by the address data output by the address bus, the scramble unit comprising: a first scrambler which scrambles the write-in data by XORing the write-in data and first mask data generated by using an address data which is the same as the address data output by the address bus for each bit to obtain first scrambled data, a first converter which performs one-to-one substitution conversion of the first scrambled data, and a second scrambler which scrambles the first scrambled data after conversion by the first converter by XORing the first scrambled data after conversion and second mask data generated by using an address data which is the same as the address data output by the address bus for each bit to obtain second scrambled data; and a data bus which outputs the second scrambled data obtained by the second scrambler of the scramble unit as the scrambled write-in data to the memory apparatus.