Patent ID: 8059451

Claim:
A multi-valued DRAM (dynamic random access memory) cell using a SET (single electron transistor) comprising: a switching transistor to which a data value is transmitted through a bit line BL; a storage capacitor which is connected to a charge storage node to which charges are supplied when the switching transistor is turned on and stores a data value; a load current transistor having a terminal connected to the charge storage node and controlling current supply from a current source to the SET; a voltage control transistor having a terminal connected to the charge storage node so as to be connected to the load current transistor, and the other terminal connected to the SET so as to control a terminal voltage of the SET; the SET having a terminal connected to the voltage control transistor, the other terminal connected to a voltage source terminal, and a gate connected to the charge storage node; and a refresh signal unit which i) is connected to gates of the load current transistor and the voltage control transistor, ii) is enabled by a predetermined period to turn on the transistors, and iii) applies refresh signals for re-charging the storage capacitor.