Patent ID: 7750688

Claim:
An output CMOS buffer for use in a digital device comprising: a final inverter stage including a first pair of complementary transistors each having a conductivity type, respective gate slew limiters and respective first and second inverters each supplied through the respective gate slew limiter controlling a slope of a gate signal of the gates of the first pair of complementary transistors; a second complementary pair of low-threshold transistors connected respectively in parallel to the complementary transistors of opposite conductivity type of the first pair; third and fourth inverters and respective gate slew limiters, each of the third and fourth inverters being supplied through the respective gate slew limiter controlling the slope of the gate signal of the gates of the second pair of complementary low-threshold transistors; a voltage supply node; a reference voltage node; a negative voltage node; and a positive voltage node; the third inverter being connected between the voltage supply node and the negative voltage node, and the fourth inverter being connected between the positive voltage node and the reference voltage node, the negative voltage and the positive voltage on the respective nodes being at least equal to an absolute value of the threshold voltage of the low-threshold transistors.