Patent ID: 7047162

Claim:
A computer-supported method for partitioning an electrical circuit comprising the steps of: imaging the electrical circuit is imaged onto a graph that exhibits the same topology as the electrical circuit; allocating weighting values to edges of the graph with which a required calculating outlay for determining electrical descriptive quantities for elements of the electrical circuit that are represented by the respective edge is described; a first sum value of the weighting values of the edges for edges coupled to one another and, in further iterations, the first sum value is respectively formed upon addition of at least one further edge until the respectively calculated, first sum value is greater than a prescribable, first threshold; forming a partition of the electrical circuit by the edges taken into consideration in the formation of the first sum value; for at least a part of the remaining edges that do not lie in the partition and that are coupled to at least one edge of the partition; determining a second sum value that derives from the sum of the first sum value and at least one weighting value of at least one remaining edge; when the second sum value is smaller than a prescribable second threshold, and when a plurality of edges that were taken into consideration in the formation of the second sum value that are coupled to edges that were not taken into consideration in the formation of the second sum value is smaller than a plurality of edges of the partition that are coupled to the remaining edges, then allocating the remaining edge to the partition and allocating the second sum value to the first sum value, and forming the partition by the edges taken into consideration in the formation of the second sum value.