Patent ID: 8150638

Claim:
A computer-implemented method of determining parasitic capacitance for a transistor within an integrated circuit, the method comprising: selecting a first expression to be C2D i =A2 i +B2 i /L+C2 i /(L 2 ), wherein C2D i represents a two-dimensional parasitic capacitance, wherein A2 i , B2 i , and C2 i are fitting coefficients determined by fitting a line to a first plurality of parasitic capacitances, and L represents transistor channel length of a plurality of two-dimensional transistor structures; determining, using a processor, a first set of coefficients for the first expression that calculates parasitic capacitance for a transistor structure according to the first plurality of parasitic capacitances derived from the plurality of two-dimensional transistor structures; inserting the first set of coefficients into the first expression; determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures, wherein the second expression comprises the first expression; inserting the second set of coefficients into the second expression; and solving the second expression to determine parasitic capacitance of the transistor.