Patent ID: 7456662

Claim:
A differential circuit operating at a high supply voltage, the circuit comprising: first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above first and second maximum gate-body voltages, respectively, each of the maximum gate-body voltage being a voltage at which the low-voltage gate dielectric layers is susceptible to deterioration, source electrodes of the first and second NMOS transistors being coupled to a common node, gate electrodes of the first and second NMOS transistors being coupled to first and second differential input signals, respectively, drain electrodes on the first and second NMOS transistors being coupled at least indirectly to a high power supply voltage, wherein the high power supply voltage is a voltage higher than the first and second maximum gate-body voltages of the first and second NMOS transistors, respectively, voltages on the drain electrodes representing results of a differential switching operation upon the first and second differential input signals, respectively, and bodies of the first and second NMOS transistors are coupled to a bias voltage such that first and second gate-body voltages of the first and second NMOS transistors are less than or equal to the first and second maximum gate-body voltages of the first and second NMOS transistors, respectively.