Patent ID: 7157322

Claim:
A method for manufacturing a semiconductor device comprising: implanting boron ions for forming a channel region to adjust threshold voltage within an NMOSFET forming region divided by an element dividing region; implanting two different ions after said implantation of boron, comprising: implanting arsenic ions in a semiconductor substrate at a first acceleration energy level which suppresses a reverse short channel effect to form arsenic ion implanted regions thereby forming source/drain regions within said NMOSFET forming region; after said implanting said arsenic ions, using a same photoresist mask as a phocoresist mask used in said implanting said arsenic ions, continuously implanting phosphorous ions in the arsenic ion implanted regions, at a second acceleration energy level lower than the first acceleration energy level, so as to form a concentration peak of the phosphorous ions located in the arsenic ion implanted region; and performing a heat treatment to activate the arsenic ions and the phosphorous ions in the ion-implanted regions to form source/drain regions and buffer regions, said buffer regions comprising phosphorous ions and extending beyond said source/drain regions, thereby suppressing transient enhancement diffusion (TED) of a boron implanted region; and forming an NMOSFET having the source/drain.