Patent ID: 8103998

Claim:
A method of verifying non-deterministic behavior of a design under test (DUT), comprising: predicting the non-deterministic behavior of the DUT comprising a plurality of behaviors of the DUT; forking respective verification tasks for each one of the plurality of behaviors, wherein the forking is performed as a result of the predicting the non-deterministic behavior; verifying an actual behavior of the DUT with each of the verification tasks; and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks, wherein the predicting, the forking, the verifying, and the terminating are performed using a computer device having a processor, and the predicting is performed in a software-based simulation of the DUT, and further comprising using the method to verify a core that contains several asynchronous crossings and that is responsible for locking onto a correct bit alignment to decode a received serial data stream, wherein the DUT comprises the core.