Patent ID: 7965110

Claim:
A sample-and-hold module comprising: a first differential pair of transistors constituting a unit-gain amplifier having an input for receiving an input voltage to be sampled and an output, the first differential pair of transistors being configured to be selectively supplied with current from a first current source; a follower transistor connected between the output of the first differential pair of transistors and a storage capacitor, the follower transistor having an emitter and a base and being configured to be selectively supplied with current from a second current source; a first current switch coupled between the follower transistor and the second current source and configured to cause the follower transistor to be turned on during a sampling phase by the application of the current from the second current source; a second current switch coupled between the first differential pair of transistors and the first current source and being configured to steer the current from the first current source either towards the base of the follower transistor during a hold phase for applying a disabling voltage to the base of the follower transistor, or towards the first differential pair of transistors during a period other than the hold phase; and a signal generation circuit configured to generate a hold signal and a complementary hold signal for defining the hold phase and controlling the second current switch, and to generate a sampling signal and a complementary sampling signal for defining the sampling phase and controlling the first current switch, and for at least one sample-and-hold cycle, a beginning of the sampling phase occurring at a delayed time after an end of the hold phase of a previous sample-and-hold cycle.