Patent ID: 6925590

Claim:
An integrated circuit comprising: a static logic scan circuit coupled to receive a scan mode signal to control whether or not scan is active and a scan clock signal to clock scan when scan is active, wherein the static logic scan circuit is coupled between an output of a first static storage device which receives a scan-in signal and a scan-in input of a second static storage device, in which the first and second static storage devices are clocked by the scan clock signal scan, the static logic scan circuit to prevent a race condition from the first static storage device and the second static storage device responsive to the scan mode signal indicating that scan is active, and the static logic scan circuit to use the scan mode signal to deactivate a first passgate to prevent toggling of the static logic scan circuit during non-scan; and a dynamic logic scan circuit coupled to receive the scan mode signal, the scan clock signal, and the scan-in signal, wherein the dynamic logic scan circuit is coupled to an internal node of a dynamic logic circuit, and wherein the dynamic logic scan circuit to provide the scan-in signal onto the internal node through a second passgate controlled by the scan clock and to retain the scan-in input on the internal node responsive to the scan clock signal, the dynamic logic scan circuit to also use the scan mode signal to deactivate a third passgate to prevent toggling of the dynamic logic scan circuit during non-scan.