Patent ID: 8411524

Claim:
A method for refreshing a semiconductor memory device comprising the steps of: applying a plurality of voltage potentials to a memory cell in an array of memory cells, wherein applying a plurality of voltage potentials to the memory cell comprises: applying a first voltage potential to a first region of the memory cell via a respective source line of the array; applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array; applying a third voltage potential to a respective word line of the array, wherein the word line is spaced apart from and capacitively to a body region of the memory cell that is electrically floating and disposed between the first region and the second region; applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array; and maintaining the first voltage potential applied to the first region at a constant level via the respective source line during the refresh of the semiconductor memory device.