Patent ID: 8446735

Claim:
A semiconductor package comprising: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing, wherein, in the first wiring pair and the second wiring pair provided adjacent to the first wiring pair, a ratio between a first capacitance and a second capacitance is equal to or more than 0.5 and equal to or less than 2, the first capacitance existing between a first portion of a wiring line constituting the first wiring pair, the first portion opposing the second wiring pair on a board wire side, and a second portion of a wiring line constituting the second wiring pair, the second portion being on the board wire side and opposing the first portion, the second capacitance existing between a third portion of a wiring line constituting the first wiring pair, the third portion opposing the second wiring pair on a wire side, and a fourth portion of the wiring line constituting the second wiring pair, the fourth portion being on the wire side and opposing the third portion.