Patent ID: 7995376

Claim:
A semiconductor storage device including a plurality of integrated memory cells each comprising: a first inverter having a first driver transistor and a first load transistor which are formed on a semiconductor substrate in order to form a first storage node; a second inverter having a second driver transistor and a second load transistor which are formed on said semiconductor substrate in order to form a second storage node; a first transfer transistor connected between said first storage node and a bit line to serve as a transistor connecting said memory cell to said bit line; and a second transfer transistor connected between said second storage node and a complementary-bit line to serve as a transistor connecting said memory cell to said complementary-bit line, wherein each of said memory cells has a layout in which said first transfer transistor, said first driver transistor, said second driver transistor and said second transfer transistor are connected in series and provided in a first semiconductor area formed as a segment having the shape of a straight line on said semiconductor substrate, said first load transistor is provided in a second semiconductor area formed as a segment on said semiconductor substrate, said second load transistor is provided in a third semiconductor area formed as a segment on said semiconductor substrate, and said first semiconductor area is sandwiched by said second semiconductor area and said third semiconductor area.