Patent ID: 7496881

Claim:
A computing device implemented method comprising: producing simulated resist contours from a mask usable to manufacture a semiconductor device, wherein producing the simulated resist comprises: sampling a photolithographic simulation of the mask to obtain a plurality of sampling points; connecting sampling points to form the simulated resist contours; modifying the simulated resist contour by shrinking the simulated resist contour by approximately one-half of a pinch tolerance; growing the shrunk simulated resist contour by approximately one-half of the pinch tolerance; and validating the mask by comparing the original simulated resist contour to the modified simulated resist contour to determine a symmetric difference, wherein if the symmetric difference indicate a violation of the desired wafer geometries, outputting a geometric representation of a portion of the mask that resulted in the violation to a user interface, validating further comprising determining whether the simulated contours include a pinch violation.