Patent ID: 7582921

Claim:
A semiconductor device comprising: a first wiring extending in a first direction and coupled to a plurality of first memory cells; a second wiring extending in the first direction and coupled to a plurality of second memory cells; a third wiring extending in the first direction and coupled to a plurality of third memory cells; a fourth wiring extending in the first direction and coupled to a plurality of fourth memory cells; a first contact provided at one end of the first wiring; a second contact provided at one end of the second wiring; a third contact provided at one end of the third wiring; and a fourth contact provided at one end of the fourth wiring, wherein the plurality of first to fourth memory cells are formed in a first rectangular region, wherein the first and fourth contacts are formed in a second region, wherein the second and third contacts are formed in a third region, wherein the first rectangular region is provided between the second region and the third region, wherein a first side of the first rectangular region extends in a second direction perpendicular to the first direction, and wherein a distance between the other end of the second wiring and the first side of the first rectangular region is shorter than a distance between the other end of the third wiring and the first side of the first rectangular region.