Patent ID: 7772833

Claim:
A flexible on-chip testing circuit for I/Os characterization of a plurality of I/O structures, said I/O structures comprising one of a multi-voltage IUT, and a single voltage IUT, said testing circuit utilizing a plurality of operational modes for measuring said I/Os characterization, said testing circuit comprising: a Test Interface providing a functional testing of the plurality of I/O structures and for interfacing with an external world; a register bank module coupled to said standard test interface for storing a plurality of instructions, and for measuring a plurality of results; a central processing controller (CPC) connected to said register bank module for fetching and executing the plurality of instructions, said controller comprising: a plurality of secondary state machines for measuring said I/Os characterization; and a primary state machine interacting with the plurality of secondary state machines for interpreting the plurality of instructions; and one or more characterization modules controlled by said central processing controller and said register bank for measuring one or more parameters.