Patent ID: 7642945

Claim:
An AD converter circuit that is a successive approximation type, comprising: a comparator for comparing an analog input signal with an output analog signal; a DA converter for outputting the output analog signal according to a digital signal output in accordance with a comparison result from the comparator; an AD converter for AD-converting the analog input signal to the digital signal output in accordance with a sampling period for sampling the analog input signal and comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter, and for outputting an AD-converted output signal if the output analog signal of the DA converter is equal to the analog input signal; and setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period, wherein the setting means comprises: a first divider circuit for dividing a clock signal to generate the first clock signal; a second divider circuit for dividing the clock signal to generate the second clock signal and supply the generated clock signal to the AD converter; and a counter circuit for counting the number of the first clock signals to supply a control signal for setting the sampling period to the AD converter.