Patent ID: 7895416

Claim:
A reconfigurable integrated circuit comprising: one or a plurality of controller elements, the plurality of controller elements including a first controller element and a second controller element, the first controller element having a first controller element architecture and a second controller element having a second controller element architecture, the first architecture being different from the second architecture; a plurality of processing elements, which can be concatenated to form at least one combinatorial logic datapath; the plurality of controller elements and the plurality of processing elements being logically grouped into at least one processing block; and reconfigurable interconnection means, which can be configured by one or a plurality of controller elements, the reconfigurable interconnection means being dynamically reconfigurable in real time and non real time, the reconfigurable interconnection means allowing data transfers between processing elements and data transfers between processing elements and controller elements; wherein one or a plurality of controller elements and processing elements are optimized for emulating high level language instruction contructs, and wherein one or a plurality of controller elements and processing elements are optimized for emulating different processor instruction sets.