Patent ID: 8405435

Claim:
A delay locked loop comprising: a test reference input; a normal reference input; a normal operating mode and a test operating mode; a test control input, which selects between the normal and test operating modes; a phase detector having a reference input, a feedback input and a charge control output; a charge pump coupled between the charge control output and a common node; a loop filter coupled to the common node; a first voltage-controlled delay line coupled between the reference input and the feedback input and having a first delay which is controlled by the common node; a second voltage-controlled delay line having a second delay which is controlled by the common node; a first multiplexer, which selectively couples the second delay line into and out of series with the first delay line between the reference input of the phase detector and the feedback input as a function of the test control input; and a second multiplexer, which alternately couples and decouples the normal reference input and the test input to and from the reference input of the phase detector as a function of the test control input.