Patent ID: 8541288

Claim:
A manufacturing method for a thin film transistor (TFT) array substrate, comprising: providing a substrate having a plurality of scan lines, a plurality of data lines, a plurality of storage electrode lines, and a plurality of switch devices formed thereon; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; wherein the normal alignment regions are defined at sides of the scan lines, the data lines, the storage electrode line, and the switch devices, and the abnormal alignment regions are defined at opposite sides of the scan lines, the data lines, the storage electrode lines, and the switch devices; forming an insulating layer and a transparent conductive layer on the substrate, sequentially; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits in the alignment material layer in each of the normal alignment regions along an alignment direction.