Patent ID: 8917534

Claim:
An apparatus comprising: a memory cell of a memory device; a bit-line coupled to the memory cell; a word-line coupled to the memory cell; a bit-line electrode coupled to the bit-line; a word-line electrode coupled to the word-line; current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module; sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the memory cell; and write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell, wherein the apparatus is configured to provide a potential of the word-line electrode that is lower than a potential of the bit-line electrode, and wherein the apparatus is configured to provide a capacitance of the word-line electrode that is lower than a capacitance of the bit-line electrode.