Patent ID: 7756659

Claim:
An integrated circuit comprising: at least first and second separate timing circuits that are created by the same fabrication process; wherein a first timing circuit is a clock and a second timing circuit is a delay circuit; a time specification for an at least first timing circuit is known, a first variable control circuit that controls the timing of at the least first clock timing circuit; a driver that outputs a control signal to the first variable control circuit; a trim value that is related to the fabrication process, wherein when the at least first timing circuit does not meet its time specification; the trim value is determined and applied to the driver so that the at least first timing circuit meets its timing specification; a second variable control circuit that controls the timing of a second timing circuit; and a second driver that outputs a second control signal to the second variable control circuit, wherein the trim value is applied to the second driver thereby trimming the timing of the second timing circuit to meet its timing specification, wherein the application of the trim value to the at least first and second timing circuits corrects for process, temperature and voltage variations.