Patent ID: 8625346

Claim:
A system comprising: a microcontroller coupled to and in communication with a memory device wherein the microcontroller generates control signals and communicates the control signals to the memory device through a control signal bus, generates address signals and communicates those address signals to the memory device through address input connections and reads and writes data from and to the memory device and wherein the data is communicated through input/output circuitry in the memory device; the memory device further comprising: a memory array comprising a plurality of memory cells arranged in rows and columns and organized into memory blocks including a first remappable memory block that operates only in a single bit storage configuration, the remaining memory blocks also remappable and adapted to operate in either the single bit storage configuration or a multiple bit storage configuration; and configuration registers, for storing configuration bits indicating a storage configuration status of each of the memory blocks; and control circuitry, coupled to an interface, the memory array and the configuration registers, for controlling which memory blocks store data in the multiple bit storage configuration and which memory blocks store data in the single bit storage configuration.