Patent ID: 7885367

Claim:
A data transmission system for adjusting the sampling timing of a DLL circuit among a plurality of DLL circuits in a receiver side, comprising: a transmitter side comprising, error detection/correction code generating means for adding an error detection/correction code to transmission data and outputting the transmission data with the error detection/correction code; means for transmitting, to the receiver side, a plurality of output bits of the error detection/correction code generating means in which one data bit associated with the DLL circuit to be adjusted is replaced with one bit for a sampling timing adjustment; and a spare channel for transmitting the one data bit associated with said DLL circuit to be adjusted, and the receiver side comprising, the plurality of DLL circuits provided for receiving each bit of the plurality of output bits and said spare channel; outputting means for outputting the outputs of each of the plurality of DLL circuits in which the output of said DLL circuit to be adjusted is replaced with the output of the DLL circuit associated with said spare channel; and error detecting/correcting means for receiving the outputs of said outputting means and performing error detection/correction thereon.