Patent ID: 7906835

Claim:
A printed circuit board (PCB) configured to mount a ball grid array package, the PCB comprising: a dielectric layer; and an electrically conductive layer on the dielectric layer; wherein the electrically conductive layer includes a plurality of land pads arranged in an array of rows and columns, wherein a perimeter edge of the array includes a pair of adjacent oblong shaped land pads; wherein the electrically conductive layer further includes an electrically conductive trace routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array; wherein the pair of adjacent oblong shaped land pads includes a first oblong shaped land pad and a second oblong shaped land pad, wherein the first oblong shaped land pad has a length along a first axis that is perpendicular to the perimeter edge and a width along a second axis that is perpendicular to the first axis, wherein the length is greater than the width; wherein the interior of the array includes a plurality of substantially round land pads; wherein a pair of adjacent substantially round land pads in the interior of the array are separated by a distance, D; wherein D<TW+ 2 ×TS, where TW=a width of the electrically conductive trace, and TS=a manufacturing tolerance for spacing of the trace from other electrically conductive features of the electrically conductive layer.