Patent ID: 6895016

Claim:
A time division multiplexing (TDM) arrangement for interfacing with a TDM bus having a plurality of transmit channels and a plurality of receive channels comprising: a data pump for generating a transmit data signal and receiving a receive data signal; a transmit storage register coupled to said data pump for buffering said transmit data signal; a transmit shift register coupled between said transmit storage register and said TDM bus for latching said transmit data signal from said transmit storage register and shifting said transmit data signal onto one of said plurality of transmit channels of said TDM bus; a receive shift register coupled to said TDM bus for receiving one of said plurality of receive channels from said TDM bus; and a receive buffer coupled between said receive shift register and said data pump for buffering said one of said plurality of receive channels; such that said data pump generates said transmit data signal, said transmit data signal passes through said transmit storage register and then through said transmit shift register onto said TDM bus; and said receive shift register receives said one of said plurality of said receive channels as said receive data signal, said receive data signal passes through said receive shift register and then through said receive buffer to said data pump; and, a channel coordinator coupled to said transmit shift register and said receive shift register for controlling said transmit shift register and said receive shift register, such that said channel coordinator controls which one of said plurality of transmit channels corresponds to said transmit data signal and controls which one of said plurality of receive channels corresponds to said receive data signal, and said channel coordinator controls said transmit shift register to shift said transmit data signal onto said TDM bus when said one of said plurality of transmit channels is available and controls said receive shift register to latch a portion of said receive data signal into said receive shift register when said one of said plurality of receive channels is available.