Patent ID: 8154072

Claim:
A nonvolatile semiconductor memory apparatus comprising a memory element including: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a first insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site that performs hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film, wherein physical film thicknesses of the first insulating layer and the second insulating layer satisfy the following three inequations: T 2 ≧−( T 2,low /T 1,low )× T 1 +T 2,low , T 1 ≧T 1,high , and T 1 ×∈ ox /∈ 1 +T 2 ×∈ ox /∈ 2 ≦8, where: T 1,low represents a physical film thickness of the first insulating layer when the first insulating film includes only the first insulating layer and the first insulating layer needs to reduce a leakage current to J low or lower, leakage current of the first insulating film in a first electric field applied in the first insulating film being required to be J low or lower as a required condition in a charge retaining state; T 2,low represents a physical film thickness of the second insulating layer when the first insulating film includes only the second insulating layer and the second insulating layer needs to reduce a leakage current to J low or lower, leakage current of the first insulating film in the first electric field applied in the first insulating film being required to be J low or lower as the required condition in the charge retaining state; T 1,high represents a physical film thickness of the first insulating layer that the first insulating layer needs to increase the leakage current in the first insulating film to J high higher in a second electric field E high applied in the first insulating film as a condition required when erasing is performed; ∈ 1 and ∈ 2 represent dielectric constants of the first and second insulating layers respectively, ∈ ox represents a dielectric constant of silicon oxide, and T 1 (nm) and T 2 (nm) represent the physical film thicknesses of the first insulating layer and the second insulating layer respectively when stacked.