Patent ID: 8873289

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array configured having NAND cell units arranged therein, each of the NAND cell units including a memory string and a bit-line-side select transistor and source-line-side select transistor that are connected respectively to the two ends of the memory string, the memory string being configured having a plurality of memory cells connected in series therein, each of the memory cells being configured capable of storing data in a nonvolatile manner; word lines extending in a first direction and commonly connected to the memory cells in a plurality of the NAND cell units; and bit lines extending in a second direction crossing to the first direction and connected to one ends of the NAND cell units, in one block, both a first and a second NAND cell units being connected to one of the bit lines, the bit-line-side select transistor in the first NAND cell unit and the source-line-side select transistor in the second NAND cell unit being disposed adjacently to each other, and the source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit being disposed adjacently to each other.