Patent ID: 7984218

Claim:
A processor provided with a plurality of cores, which comprises: an interrupt operation dedicated core which is used only for an interrupt operation; a normal core which outputs an interrupt request when an interrupt source is generated; and an interrupt control part which, upon receipt of the interrupt request, assigns an operation by an interrupt vector to the interrupt operation dedicated core, wherein the interrupt control part comprises: an interrupt receiving part which receives the interrupt request; a storing part which stores a table correlating an interrupt vector and the interrupt operation dedicated core; a retrieving part which refers to the table and retrieves an interrupt operation dedicated core corresponding to an interrupt vector contained in the interrupt request; a transmission part which sends an interrupt transaction to an interrupt operation dedicated core selected by the retrieving; and an interrupt destination field rewriting part which rewrites an interrupt destination field of the interrupt transaction to a core number indicating the interrupt operation dedicated core selected by the retrieving part, and the transmission part transmits the interrupt transaction to the interrupt operation dedicated core, and wherein, in the table, all of the cores correlated with the interrupt vector are the interrupt operation dedicated cores.