Patent ID: 7581054

Claim:
A data processing system comprising: a first processor; a second processor; a first local memory; a second local memory; a first local bus; a second local bus; a first bus bridge; a second bus bridge; a system bus including a first system bus and a second system bus; a first bus interface unit; and a second bus interface unit, wherein the first local memory is coupled to the first processor via the first local bus, and the second local memory is coupled to the second processor via the second local bus, wherein the first bus bridge has one port coupled to the first local bus and the other port coupled to the first system bus, and the second bus bridge has one port coupled to the second local bus and the other port coupled to the second system bus, wherein the first bus interface unit has a first port coupled to the first system bus, a second port coupled to the second system bus, and a third port coupled to the first local memory, and the second bus interface unit has a first port coupled to the first system bus, a second port coupled to the second system bus, and a third port coupled to the second local memory, wherein when the first processor supplies a first request signal for requesting an access to the second local memory to the first port of the second bus interface unit via the first local bus, the first bus bridge, and the first system bus, the second bus interface unit receives the first request signal and gives a first acknowledge signal for permitting the access by the first processor to the second local memory and, in response to the first acknowledge signal, the first processor accesses the second local memory via the first local bus, the first bus bridge, the first system bus, and the first port and third port of the second bus interface unit, and, wherein when the second processor supplies a second request signal for requesting an access to the first local memory to the second port of the first bus interface unit via the second local bus, the second bus bridge, and the second system bus, the first bus interface unit receives the second request signal and gives a second acknowledge signal for permitting the access by the second processor to the first local memory and, in response to the second acknowledge signal, the second processor accesses the first local memory via the second local bus, the second bus bridge, the second system bus, and the second port and third port of the first bus interface unit.