Patent ID: 7463521

Claim:
A method of operating a non-volatile memory having addressable pages of memory cells in a core array, comprising: providing for each memory cell of an addressed page a set of data latches having capacity for latching a predetermined number of bits; providing a first-in-first-out queue for receiving incoming memory operations and for outputting the queued memory operations to be executed in the core array; specifying a set of mergeable conditions when two or more memory operations are mergeable into a combined memory operation, the combined memory operation operating on all data associated with the operations being combined; accepting an incoming memory operation into the queue whenever there are sufficient data latches available for caching the data associated with the incoming memory operation; and whenever a memory operation being executed in the core array is mergeable with one or more queued memory operations, to be outputted from the queue, terminating the memory operation being executed and instead executing a combined memory operation of the mergeable memory operations; and whenever two or more queued memory operations to be outputted from the queue are mergeable among themselves but not with a memory operation being executed in the core array, executing a combined queued memory operation of the mergeable memory operations after the memory operation being executed in the core array has completed.