Patent ID: 8035407

Claim:
An integrated circuit comprising: A. double data rate bi-directional data leads; B. a bi-directional strobe lead; C. a double data rate clock input lead; D. a system clock input lead; E. a built-in self test output lead; F a processing unit; G. phase locked loop circuitry connected to the system clock input lead and having a test clock output; H. multiplexer circuitry having an input connected to the test clock output, an input connected to the double data rate clock input lead, and an output; and G. memory controller circuitry coupled to the processing unit and connected to the data leads and the strobe lead, when receiving data signals on the data leads the memory controller circuitry receiving a data strobe signal on the strobe lead that is aligned with the edges of the data signals, when sending data signals on the data leads the memory controller circuitry sending a data strobe signal on the strobe lead that is aligned with the center of the data signals, the memory controller including: i. a delay element having an input connected to the output of the multiplexer, an internal data strobe in output lead, and a phase shifted internal data strobe out output lead; and ii. built in self test circuitry having inputs connected to the internal data strobe in output lead, and the phase shifted internal data strobe out output lead, and an output connected to the built-in self test output lead.