Patent ID: 8265198

Claim:
A signal processing circuit, comprising: a demodulator having an input for receiving a received signal which includes falling and rising signal edges, and an output for outputting a demodulated received signal which, with signal edges of the received signal, includes transitions from a first level to a second level or vice versa, wherein times of the transitions depend on steepnesses of the signal edges; and a signal generator having an input for receiving the demodulated received signal and coupled to the output of the demodulator, and an output for outputting a corrected demodulated received signal which includes transitions, the times of which relative to times of the transitions of the demodulated received signal are set based on a reference signal to reduce influences of the steepnesses of the falling and rising signal edges in the corrected demodulated received signal relative to the demodulated received signal, wherein the received signal includes a received reference signal portion which is based on a known reference signal portion, wherein the signal generator is configured to derive from a comparison of a duration of the received demodulated reference signal portion and a duration of the known reference signal portion a time shift by which transitions in the corrected demodulated received signal are set relative to transitions in the demodulated received signal.