Patent ID: 7164592

Claim:
A semiconductor device comprising: a semiconductor chip mounted over a wiring board, wherein the wiring board has a plurality of wiring layers and has one surface formed with a plurality of chip connecting electrodes connected to the semiconductor chip and the other surface formed with a plurality of external connecting electrodes of the semiconductor device, said wiring board including wirings formed in the wiring layers and vias that connect the wirings among the wiring layers to connect the chip connecting electrodes and external connecting electrodes associated with one another, wherein the plurality of chip connecting electrodes include first chip connecting electrodes each used in an interface for a first signal whose logic value changes in a predetermined timing, and second chip connecting electrodes each used in an interface for a second signal having a timing at which a logic value thereof changes after the change timing of the first signal, and wherein a wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is principally performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is principally performed, are made different from each other.