Patent ID: 8247278

Claim:
A method for manufacturing a semiconductor device, comprising: a) forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer, wherein the second protection layer covers the semiconductor substrate and the first insulating layer with the gate stack formed between the second protection layer and both the semiconductor substrate and the first insulating layer, and the semiconductor substrate comprises a semiconductor layer, a stop layer, a sacrificial layer and a first protection layer which are stacked and patterned, a first sidewall spacer surrounding the patterned sacrificial layer and the patterned first protection layer, and a second insulating layer covering sidewalls of the patterned semiconductor layer; b) after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain region ion implantation in the semiconductor layer; c) after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack, and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; and d) performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer.