Patent ID: 8049847

Claim:
A pixel structure of a liquid crystal display array substrate, comprising: a substrate having a first area and a second area; a first patterned conductive layer formed on the substrate and comprising a first part, a second part and a third part, wherein the first part of the first patterned conductive layer is arranged on the first area, the second part of the first patterned conductive layer is used as a scan line and a gate electrode, and the third part of the first patterned conductive layer is used as an underlayer data line segment; a first interlayer dielectric layer formed to cover the first patterned conductive layer and the substrate; a patterned semiconductor layer formed on the first interlayer dielectric layer over the gate electrode; a second patterned conductive layer formed on the first interlayer dielectric layer and comprising a first part, a second part and a third part, wherein the first part of the second patterned conductive layer is arranged on the first interlayer dielectric layer of the first area and used as a common line coupled to a common electrode voltage, the first part of the second patterned conductive layer together with the first part of the first patterned conductive layer form a first storage capacitor, the second part of the second patterned conductive layer is used as a drain electrode and electrically connects with the first part of the first patterned conductive layer, and the third part of the second patterned conductive layer is used as an upperlayer data line segment and a source electrode to electrically connect with the third part of the first patterned conductive layer to form a data line; a second interlayer dielectric layer formed to cover the second patterned conductive layer and the substrate; a patterned transparent conductive layer formed on the second interlayer dielectric layer of the first area and the second area, wherein the patterned transparent conductive layer is coupled to the second part of the second patterned conductive layer, and the patterned transparent conductive layer together with the first part of the second patterned conductive layer form a second storage capacitor; a passivation layer formed to cover the patterned transparent conductive layer and the substrate and having an opening to expose the patterned transparent conductive layer of the second area, so as to form a transparent part of the pixel structure on the second area; and a patterned reflective metal layer formed on the passivation layer and electrically connected with the patterned transparent conductive layer to form a reflective part of the pixel structure on the first area.