Patent ID: 8865556

Claim:
A field-effect transistor (FET) device, comprising: a silicon-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX) and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device, raised above a surface of the SOI layer, adjacent to the gate stack, wherein the source and drain regions of the device comprise a semiconductor material comprising silicon germanium; and silicide contacts on and covering an entire top surface of each of the source and drain regions of the device, wherein the semiconductor material underlies each of the silicide contacts such that an interface is present between the silicide contacts and the semiconductor material, wherein the interface has an interface roughness of less than about 5 nanometers, wherein the semiconductor material that underlies each of the silicide contacts comprises a layer of the semiconductor material one side of which is in contact with the SOI layer and another side of which is in contact with the silicide contacts, and wherein a concentration of germanium is uniform throughout the semiconductor material that underlies each of the silicide contacts in that the concentration of germanium in the semiconductor material does not vary by more than 3 percent anywhere in the semiconductor material.