Patent ID: 8565361

Claim:
A system comprising: a clock configured to generate a clock signal; a root node configured to receive the clock signal, to generate a first frame including a first payload and a first overhead, and to generate a second frame including a second payload and a second overhead, the first overhead comprising a synchronization value based on the clock signal, and the second overhead also comprising the synchronization value; a radio channel network in communication with the root node for transmitting the first frame and the second frame; a first child node including a first phase lock loop, and configured to receive the first frame and to perform clock recovery including frequency synchronization using the synchronization value and the first phase lock loop; a second child node including a second phase lock loop, and configured to receive the second frame and to perform clock recovery including frequency synchronization using the synchronization value and the second phase lock loop; and an intermediate child node configured to receive the first frame from the root node before the first child node receives the first frame, and to attenuate jitter of the first frame.