Patent ID: 7821486

Claim:
A drive circuit of a display device comprising: at least one data transfer line to receive analog data signals including information for an image; a first latch to sequentially sample analog data signals transferred from the at least one data transfer line and to sequentially store the sampled analog data signals; a second latch to receive the sampled analog data signals from the first latch and to simultaneously supply the sampled analog data signals to a display; and wherein the first latch comprises a sampler to sequentially sample the analog data signals transferred from the at least one data transfer line, and a first buffer unit to store the analog data signals sampled by the sampler, to buffer the stored analog data signals, and to output the buffered analog data signals; wherein the sampler comprises a plurality of sampling switches connected between the at least one data transfer line and the first buffer unit, each sampling switch adapted to sample respective analog data signals transferred from the at least one data transfer line in a sequential manner; a shift register to supply sampling scan pulses to each of the sampling switches to sequentially turn on the sampling switches; wherein the second latch comprises an output controller to simultaneously output the sampled analog data signals stored in the first latch, and a second buffer unit to buffer the sampled analog data signals output from the output controller and to supply the buffered sampled analog data signals to the display; wherein the output controller comprises a plurality of output switches to simultaneously output the sampled analog data signals from the first latch, the output switches to simultaneously turn on in response to a control signal supplied from a source external to the output controller; wherein the control signal is only synchronized with a sampling scan pulse to be supplied to a last sampling switch that is turned on among the plurality of the sampling switches; wherein a plurality of buffers of the first buffer unit receive a voltage swing between a maximum grayscale voltage of a negative analog data signal and a maximum grayscale voltage of a positive analog data signal; wherein a plurality of buffers of the second buffer unit receive a voltage swing between a maximum grayscale voltage of a negative analog data signal and a maximum grayscale voltage of a positive analog data signal.