Patent ID: 8060765

Claim:
A method of controlling power usage of an electronic device that is governed by a clock, comprising the steps of: determining an activity level of at least one functional block of said electronic device based on a number of active flip-flops included in said at least one functional block; performing a digital on-chip calculation to derive an estimated power value based on said activity level by calculating a weighted sum of a plurality of flip-flop enable signals as a sum of a value of each said flip-flop enable signal multiplied by a weighting factor associated with the flip-flop enable signal, and wherein each said flip-flop enable signal is associated with a functional block of said at least one functional block, and for each said flip-flop enable signal, the weighting factor associated with the flip-flop enable signal represents the contribution of the functional block associated with the flip-flop enable signal relative to other functional blocks; comparing said estimated power value with a threshold power value; and decreasing a speed of the clock if said estimated power value is greater than said threshold power value.