Patent ID: 8207993

Claim:
A display driver comprising: a synchronization controller for sending a reference synchronization signal to a central processing unit (CPU) and for controlling the CPU to synchronize a write clock with the reference synchronization signal and to send the write clock; a write clock detector for detecting whether the write clock is received from the CPU and for outputting a selection signal indicative of whether the write clock is received from the CPU; a frame memory for receiving and storing display data sent from the CPU and synchronized with the write clock; a gray-level compensator for generating gray-level compensated display data based on display data of a current frame and display data of a previous frame previously stored in the frame memory; and a selector for outputting the gray-level compensated display data as scan data when the selection signal indicates that the write clock signal is received from the CPU, and for outputting the display data previously stored in the frame memory as scan data when the selection signal indicates that the write clock signal is not received from the CPU.