Patent ID: 7060541

Claim:
A method of fabricating a TFT array, comprising the steps of; forming a gate electrode and using a replacement method of an α-Si seed which is defined by a first mask to deposit a first wiring on the substrate, and defining the gate electrode of the TFT array; forming a dielectric layer, the α-Si layer, and an N+ layer, the layers being deposited in order, and the dielectric covering the top side of the gate electrode, and the α-Si layer being between the dielectric layer and the N+ Si layer; using a second mask to define multiple contact windows; depositing a transparent conducting layer, and the transparent conducting material placed on the multiple contact windows; defining a source and drain electrodes and using a third mask to define the source electrode and the drain electrode in the TFT array; etching channel; it using coverage of a fourth mask to etch the component contact window as a conducting channel; and placing a passivation layer, and depositing a passivation layer, and the fourth mask placed on the passivation layer, and processing etching on the passivation layer of non-fourth mask coverage for implementing TFT array.