Patent ID: 7200047

Claim:
A non-volatile memory device, comprising: an array of non-volatile memory cells; an erase circuit coupled to the non-volatile memory cells and configured to erase the same; and a coupling circuit coupled to the erase circuit and the array of non-volatile memory cells and operable to eciuilibrate a voltage of a source of a non-volatile memory cell and a well of the memory device, the coupling circuit further operable to discharge the voltage at the source and the well in accordance with a first discharge rate during a first phase and in accordance with a second discharge rate during a second phase, the coupling circuit including first and second diode circuits coupled to ground, first and second transistors operable to couple the source of the non-volatile memory cell to the first diode circuit and couple the well of the memory device to the second diode circuit during the first phase, a third transistor operable to couple the source to the well during the first phase, and fourth and fifth transistors operable to couple the source and the well to ground during the second phase.