Patent ID: 7379491

Claim:
A system comprising: a clocking circuit to provide a first repeater clock signal and a second repeater clock signal, the clocking circuit including a plurality of inverters, a first one of the plurality of inverters to receive the first repeater clock signal and a second one of the inverters to provide the second repeater clock signal; and a flop repeater circuit to receive the first and second repeater clock signals and an input data signal, the flop repeater circuit to provide an output data signal based on the first and second repeater clock signals, the flop repeater circuit including a plurality of transistors and inverters coupled together without any transmission gates to function as a flip-flop circuit that passes data, the flop repeater circuit further including: a master side to receive the input data signal and the first repeater clock signal and to provide a first signal, the master side to include a plurality of transistors to pass data based on the first repeater clock signal; and a slave side to receive the first signal output from the master side and the second repeater clock signal and to provide an output data signal, the slave side including a plurality of transistors to pass data based on the second repeater clock signal received at the slave side.