Patent ID: 7298221

Claim:
A phase-locked loop (PLL), comprising: a phase-frequency detector circuit configured to detect an error of an output clock signal in relation to a reference clock signal and to generate a charge pump control signal therefrom; a charge pump circuit configured to charge and discharge an output node thereof responsive to the charge pump control signal; a current-mode loop filter circuit coupled to the output node of the charge pump circuit and configured to generate a filtered current from the current at the output node of the charge pump circuit, wherein the current-mode loop filter circuit comprises: first and second transistors arranged as a current mirror circuit, the first transistor having a current path and a control electrode therefor coupled to the output node of the charge pump circuit; and a filter network configured to be coupled between the control electrode of the first transistor and a control electrode of the second transistor; and a current-controlled oscillator configured to generate the output clock signal responsive to the filtered current.