Patent ID: 8743020

Claim:
A high integrity, high availability avionics display architecture for an avionics display system, comprising: a) a plurality of display processing computers (DPC), each DPC comprising: at least two independent processing channels, each independent processing channel comprising at least two independent lanes, each independent lane comprising: 1. an I/O section; and, 2. a processor section; wherein each independent processing channel comprises an operative graphics section, wherein at least one of said independent lanes provides a critical display function that provides commands to said graphics section to drive a display signal to displays of said avionics system; and, at least one other of said independent lanes provides an integrity monitor function; and, b) a plurality of display integrity feedback interfaces from the displays of said avionics display system, said feedback interfaces providing integrity by allowing the integrity monitor functions to detect faults within the display signals and/or originating from the displays.