Patent ID: 7290158

Claim:
A semiconductor integrated circuit device, comprising: an internal bus; a plurality of internal modules connected to the internal bus and including a main module performing a predetermined function; and a clock generating unit generating a reference clock and a clock sync signal which indicates positions of valid clock edges in the reference clock, the clock generating unit supplying the reference clock and the clock sync signal to at least one of the plurality of internal modules, wherein said at least one of the plurality of internal modules is provided with a sync control module which generates an internal clock based on the reference clock and the clock sync signal, the sync control module comprises a control unit which generates an internal clock control signal that indicates whether said at least one of the plurality of internal modules is activated, and the sync control module starting or stopping the supply of the clock sync signal in response to the internal clock control signal, and the control unit of the sync control module generates the internal clock control signal based on any of an interrupt request signal, a DMA request signal, a clock control signal received from the main module, and a bus request or acknowledge signal defined by a bus protocol of the internal bus.