Patent ID: 7645659

Claim:
A method of manufacturing a power semiconductor device, the method comprising: preparing a semiconductor substrate having a constant concentration profile of a first conductivity type impurities in a depth direction; growing an epitaxial layer on one surface of the semiconductor substrate, the epitaxial layer being doped at a concentration lower than that of the semiconductor substrate and being intended to be used as a drift region; forming a base region of a second conductivity type in a predetermined region of the epitaxial layer; forming an emitter region of the first conductivity type in a predetermined region of the base region; forming a gate electrode with a gate insulating layer on the base region between the emitter region and the drift region of the epitaxial layer; forming an emitter electrode contacting with the base region and the emitter region; grinding a rear surface of the semiconductor substrate opposite the gate electrode to reduce the thickness of the semiconductor substrate, thereby setting an FS (field stop) region having a constant concentration profile of the first conductivity type impurities in a depth direction, wherein there is no need for ion-implantation and thermal treatment in order to form the field stop region; and forming a collector region of the second conductivity type on the ground surface of the semiconductor substrate of the FS region.