Patent ID: 7937523

Claim:
A memory system comprising: a nonvolatile semiconductor memory which has a plurality memory blocks each including memory cells capable of holding data, the data in each of the memory blocks being erased simultaneously, and the data being written simultaneously in pages in each of the memory blocks, each of the pages being a set of a plurality of memory cells; and a controller which outputs a first write instruction, a first row address, write data, and a second write instruction sequentially to the nonvolatile semiconductor memory, the first write instruction being an instruction to cause the nonvolatile semiconductor memory to recognize a start of a data write operation is started, the second write instruction being an instruction to cause the nonvolatile semiconductor memory to write the write data into the memory block, the controller being configured to issue a change instruction for the transferred first row address and a second row address differing from the first row address, the nonvolatile semiconductor memory writing the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writing the write data into the memory cells corresponding to the second row address without receiving the write data again when the change instruction has been issued.