Patent ID: 7706208

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines each intersecting the plurality of word lines; a plurality of memory cells each arranged at a desired crossing point between any one of the plurality of word lines and any one of the plurality of bit lines; first and second memory arrays inclusive of the plural memory cells, both the first and second memory arrays having a first memory capacity; third and fourth memory arrays inclusive of the plural memory cells, both the third and fourth memory arrays having a second memory capacity; fifth and sixth memory arrays inclusive of the plural memory cells, both the fifth and sixth memory arrays having a third memory capacity; a first memory block including the first, third, and fifth memory arrays; a second memory block including the second, fourth, and sixth memory arrays; and first and second bank addresses for selecting the first and second memory blocks, respectively; wherein: the third memory array is disposed between the first memory array and the sixth memory array; the fourth memory array is disposed between the fifth memory array and the second memory array; the first memory array and the fifth memory array are disposed adjacently to each other; the second memory array and the sixth memory array are disposed adjacently to each other; and the third memory array and the fourth memory array are disposed adjacently to each other.