Patent ID: 6903421

Claim:
An isolated high-voltage LDMOS transistor comprising: a P-substrate; a first diffusion region and a second diffusion region having N conductivity-type, wherein said first diffusion region and said second diffusion region form a N-well in said P-substrate, wherein said first diffusion region forms an extended drain region; a drain diffusion region, for forming a drain region, said drain diffusion region having N+ conductivity-type, wherein said drain region is disposed in said extended drain region; a third diffusion region, for forming a P-well separately located in said extended drain region of said N-well, said third diffusion region having P conductivity-type; a source diffusion region, for forming a source region, said source diffusion region having N+ conductivity-type, wherein a conduction channel is formed through said N-well, wherein said conduction channel connects said source region and said drain region; a contact diffusion region, for forming a contact region, said contact diffusion region having P+ conductivity-type; and a fourth diffusion region, for forming an isolated P-well to prevent breakdown, said fourth diffusion region having P conductivity-type, wherein said isolated P-well is located in said second diffusion region in order to enclose said source region and said contact region, wherein said N-well created by said second diffusion region produces a low-impedance path for said source region, wherein said N-well generated by said second diffusion region restricts a transistor current flow between said drain region and said source region.