Patent ID: 7603541

Claim:
A processor array, comprising an array of processor elements, wherein each of said processor elements comprises a modulo-n cycle counter, and wherein at least one of said processor elements is able to transmit control command signals to each of the other processor elements, each processor element being such that, on receipt of a control command signal, it acts on that signal only when its cycle counter reaches a predetermined value, and said one of said processor elements being such that it transmits control command signals only when its cycle counter takes a value which is within a predetermined range, said predetermined range being a subset smaller than a set of n possible values of the modulo-n cycle counter, the processor array further comprising a first connection between each of said processor elements, wherein said one of said processor elements is able to transmit synchronization control command signals on said first connection, and wherein each processor element acts on a synchronization control command signal received on said first connection by restarting its cycle counter.