Patent ID: 6919633

Claim:
An assembly structure for a memory device, comprising: a common substrate having multiple sections; a first layer of a memory array disposed on a first section of the multiple sections wherein the first layer of the memory array comprises a first plurality of conductor lines; a second layer of the memory array disposed on a second section of the multiple sections wherein the second layer of the memory array comprises a second plurality of conductor lines; at least one fold line disposed on the common substrate to define alignment of the first and the second layers of the memory array; and a layer of semiconductor materials disposed on at least one of the first and the second layers the memory array, wherein the first and second sections are configured to be folded along the at least one fold line so that the first and the second layers of the memory array are in contact with each other and wherein the first and the second plurality of conductor lines are arranged to interact with each other and the layer of semiconductor materials upon folding to form at least one memory cell spanning the first and the second layers of the memory array at intersections of the first and the second plurality of conductor lines.