Patent ID: 7642617

Claim:
An integrated circuit, comprising: a semiconductor layer of a first conductivity type having an upper surface; a depletion-mode transistor that comprises: a source region and a drain region, each extending from the upper surface into the semiconductor layer; and a channel region of the first conductivity type located at a first distance from the upper surface and laterally extending between the source region and the drain region; a first gate of a second conductivity type comprising: a first gate region located at a second distance from the upper surface greater than the first distance, said first gate region being adjacent to the channel region; and a first well that laterally surrounds the semiconductor channel and extends from the upper surface to the first gate region; and a second gate of the second conductivity type positioned adjacent to the upper surface between the source region and the drain region; and a MOS transistor that comprises: a second well for operatively forming therein a second-conductivity-type channel for conducting charges between a source and a drain of the MOS transistor, said second well being a well of the first conductivity type and extending from the upper surface into the semiconductor layer; and an isolation structure of the second conductivity type comprising: a third well that extends from the upper surface into the semiconductor layer and laterally surrounds the second well; and an isolation region located at the second distance from the upper surface and laterally extending between sides of the third well to enable the isolation structure to isolate the second well from at least a portion of the semiconductor layer.