Patent ID: 7200061

Claim:
A semiconductor memory device comprising: first and second regions each including a word line extending in a first direction, first and second bit lines extending in a second direction intersecting with said first direction, a memory cell connected to said word line and said first and second bit lines, an amplifier circuit for amplifying information read from said memory cell, first and second IO lines for receiving the read information from said amplifier circuit, and a source line for controlling said amplifier circuit; and a column select line connected to said first and second regions in common and extending in said second direction, wherein said amplifier circuit includes first to fourth MOS transistors, a gate of said first MOS transistor is connected to said first bit line, a gate of said second MOS transistor is connected to said second bit line, and sources of said first and second MOS transistors are connected to said source line, a drain of said third MOS transistor is connected to said first IO line and a drain of said fourth MOS transistor is connected to said second IO line, gates of said third and fourth MOS transistors included in the amplifier circuits provided in said first and second regions are connected to said column select line in common, a drain of said first MOS transistor is connected to a source of said third MOS transistor, a drain of said second MOS transistor is connected to a source of said fourth MOS transistor, in a first state, potentials of said first and second IO lines included in said first region are higher than a potential of the source line included in said first region, and the first and second IO lines included in said second region and the source line are equal in potential, and in said first state, information is read from the memory cell included in said first region.