Patent ID: 7459744

Claim:
An array of storage cells wherein at least one of the storage cells comprises: a semiconductor substrate including an uppermost surface and a first trench extending from the uppermost surface; a first diffusion region underlying a portion of a first trench defined in the semiconductor substrate wherein a conductivity type of the first diffusion region is opposite a conductivity type of the semiconductor substrate; a second diffusion region occupying an upper portion of the semiconductor substrate adjacent to the first trench wherein a conductivity type of the second diffusion region is opposite the conductivity type of the semiconductor substrate; a charge storage stack lining sidewalls and a portion of a floor of the first trench wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs); and electrically conductive spacers formed on sidewalls of the first trench adjacent to respective charge storage stacks, wherein substantially all of the electrically conductive spacers lie at elevations between an uppermost surface of the semiconductor substrate and a bottom of the trench.