Patent ID: 7687358

Claim:
A method of forming a gated device, comprising: depositing a first gate dielectric material over a channel region and over source/drain area of a semiconductor substrate; forming a conductive gate material over the first gate dielectric material; patterning the conductive gate material to form a gate over the first gate dielectric material, the gate comprising opposing sides defining a gate width therebetween; forming lightly doped drain regions laterally outward of the opposing sides of the gate after the patterning; after forming the lightly doped drain regions laterally outward of the opposing sides of the gate, isotropically etching the first gate dielectric material from both sides of the gate to recess the first gate dielectric material to under both sides of the gate; after the isotropically etching, depositing a second gate dielectric material different from the first gate dielectric material to within the recess beneath the gate, the second gate dielectric material having a different dielectric constant k than that of the first gate dielectric material; and forming a pair of source/drain regions proximate the channel region within the source/drain area, the forming the source/drain regions comprising forming highest dopant concentration of said regions after the isotropically etching, the highest dopant concentration of the source/drain regions being formed before the depositing of the second gate dielectric material.