Patent ID: 8587988

Claim:
A bipolar switching memory element comprising an antiserial circuit of at least two memory cells A and B which have, respectively, a stable state A0 and B0 having higher electrical resistance, and a stable state A1 and B1 having lower electrical resistance, comprising at least a first stable state 0 provided for storage, which is coded in the combination of states A1 and B0, and a second stable state 1 provided for storage, which is coded in the combination of states A0 and B1, wherein, by applying a first write voltage V 0 , the memory element is transferred into the state 0 and, by applying a second write voltage V 1 having the opposite sign, the memory element is transferred into the state 1, and a third, ON state which is coded in the combination of states A1 and B1 and is produced, starting at the state 1, by applying a read voltage V R , the magnitude of which is less than the write voltages V 0 and V 1 , and therefore, by applying this read voltage V R , the previously present state 0 or 1 is identified on the basis of the electrical resistance value of the memory element.