Patent ID: 7782995

Claim:
A hybrid counter array device for counting events with interrupt indication comprising: first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of said hybrid counter array; an overflow bit means associated with each respective N counter device, said overflow bit means being set in response to overflow condition; second counter portion comprising a memory array device having N addressable memory locations in correspondence with said N counter devices, each said addressable memory location being for storing a second count value representing higher order bits of said hybrid counter array, a combination of said first and corresponding second count values provide instantaneous measure of number of events received at a counter; a control means operatively coupled with each said N associated overflow bit means for monitoring each of said N associated overflow bit means of said first counter portion and initiating incrementing a value of a corresponding said second count value stored at said corresponding addressable memory location in said second counter portion in response to detecting a respective overflow bit being set, wherein after said initiating, said overflow bit means being reset; and, a means for comparing an incremented second count value against a pre-determined threshold value, and asserting an interrupt signal in response to said second count value being equal to a pre-determined threshold value.