Patent ID: 8456856

Claim:
A module comprising: a substrate; a processor unit on said substrate, wherein said processor unit comprises a first cache memory chip over said substrate and a processor chip over said first cache memory chip, wherein said first cache memory chip is connected to said processor chip through a plurality of microbumps between said first cache memory chip and said processor chip, wherein a pitch between a neighboring two of said plurality of microbumps is smaller than 60 micrometers; a mass storage on said substrate, wherein said mass storage comprises a first memory chip over said substrate and a second memory chip over said first memory chip, wherein said first memory chip is connected to said second memory chip through at least one first wirebonded wire; a main memory on said substrate, wherein said main memory comprises a first dynamic-random-access-memory chip over said substrate and a second dynamic-random-access-memory chip over said first dynamic-random-access-memory chip; and a connector connected to said substrate.