Patent ID: 7039895

Claim:
A method comprising using a pattern-dependent model of process-induced variation to predict a location on an integrated circuit for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the lithography tool during fabrication to accommodate a focus limitation of the lithography tool, the patent-dependent model predicting thickness variation of shapes or patterns of conductive and/or non-conductive features within an integrated circuit that is to be fabricated in accordance with a design by a method that includes (a) a fabrication process that will impart the thickness variation with respect to the integrated circuit and (b) a lithography process that uses-the lithography tool and a mask produced from the design to form shapes or patterns of conductive and/or non-conductive features of the design, and making the predicted thickness variation available to a pattern-dependent model for predicting width variation in the features of the design for use in altering the design or at least one mask derived from the design to enable the lithography tool to produce a feature dimension having a satisfactory dimension at the location.