Patent ID: 8117398

Claim:
A prefetch controller in a shared memory multiprocessor system comprising: a memory bank base address register for each of plural independently addressable memory bank of said shared memory system storing a corresponding memory bank base address; a plurality of comparators one for each independently addressable memory bank of said shared memory system connected to a corresponding memory bank base address register and receiving a prefetch address, having an output generating a match signal if a prefetch address is within an address range of said corresponding memory bank; a memory bank prefetch enable register having a memory bank prefetch enable bit corresponding to each independently addressable memory bank having a first digital state indicating prefetch is permitted to said corresponding memory bank and a second digital state indicating that prefetch is not permitted to said corresponding memory bank; a memory bank power up register having a power bit corresponding to each independently addressable memory bank having a first digital state indicating said corresponding memory bank is powered and a second digital state indicating said corresponding memory bank is not powered; and a logic network for each independently addressable memory bank of said shared memory system connected to said comparator, a corresponding prefetch enable bit and a corresponding power bit, said logic network generating a prefetch enable signal enabling prefetch to said corresponding memory bank if said comparator generates said match signal, said memory bank prefetch enable bit has said first digital state and said power bit has said first digital state.