Patent ID: 8402298

Claim:
An array-type processor comprising: a data path unit that includes a plurality of processor elements arranged in an array; a state-transition management unit that stores information for controlling changeover of a data path; and a delayed adjusting circuit that adjusts a delay of an input clock signal sue shied to said delay adjusting circuit, based upon information output from said state-transition management unit, and provides the delay-adjusted clock signal to the data path unit; length of the clock cycle of the delay-adjusted clock signal being adjustably changed in accordance with a critical path delay of the data path to be configured, the critical path including a plurality of the array processor elements of the data path to be configured, the critical path delay being the delay time of the critical path, wherein said delay adjusting circuit includes: a delay control information memory; and a programmable delay; wherein said delay control information memory stores a plurality of items of delay control information, delay control information is read out using a state number supplied from said state-transition management unit as an address, and the delay control information is supplied to said programmable array; and said programmable delay delays the clock signal by a delay time specified by the delay control information and provides the delayed clock signal to said data path unit, wherein said delay adjusting circuit receives a clock changeover signal for controlling changeover of an output from said programmable delay between an output at the time of program operation and an output at the time of data processing; and receives a write control signal that includes data prevailing at the time of program operation; at the time of program operation on the basis of the clock changeover signal, said programmable delay is adjusted and data transfer is performed synchronously between an output source of the write control signal and a write destination of the data of the write control signal among said delay control information memory of said delay adjusting circuit, a state control information memory of said state-transition management unit and a configuration information memory within the processor element; and at the time of data processing on the basis of the clock changeover signal, a clock signal obtained by delaying the input clock signal by said programmable delay in accordance with the delay control information is output.