Patent ID: 8144224

Claim:
A binning circuit for an image sensor, comprising: a column amplifier (CA), which generates a CA reset signal when the column amplifier is reset; a capacitor and a switch network coupled between an output of the image sensor and an input of the column amplifier; and a correlated double sampling (CDS) circuit controllably receiving the output of the column amplifier; wherein the switch network is controlled in a way such that an image signal of a first group of the image sensor is transmitted and stored in the CDS circuit, and an image signal of a second group is then added to the stored image signal of the first group; wherein the capacitor is coupled to the output of the image sensor at a first plate, and the switch network comprises: a first switch coupled between the input of the column amplifier and a second plate of the capacitor; and a second switch coupled between the second plate of the capacitor and ground.