Patent ID: 7000097

Claim:
A microprocessor system, comprising: (A) an instruction fetch unit adapted to fetch instructions from an instruction store and to provide a predetermined plurality of said instructions to an instruction buffer; and (B) an execution unit, coupled to said instruction fetch unit, adapted to execute said plurality of said instructions from said instruction buffer in an out-of-order fashion with respect to a predefined program order, said execution unit including a load store unit adapted to make load requests to a memory system out-of-order with respect to said predefined program order and store requests to said memory system in-order with respect to said predefined program order, said load store unit including (1) an address path adapted to manage a plurality of addresses associated with said plurality of said instructions and to provide addresses to said memory system, (2) a data path adapted to transfer load data from said memory system to said execution unit and to transfer store data from said execution unit to said memory system, and (3) a load aligner, coupled to said data path, for aligning unaligned load data transferred from said memory system to said execution unit, said load aligner including a plurality of multiplexers and a select line coupled to each of said plurality of multiplexers for selecting bytes of said load data returned from said memory system, and a data buffer for storing said selected bytes of data.