Patent ID: 8156472

Claim:
A microprocessor for executing instructions, comprising: a timing and control unit configured to: retrieve an instruction to compose a plurality of processes running in parallel from a memory, the instruction being expressed in a reflective process algebra, the reflective process algebra being arranged to represent a name as a literalization of a process and a process as a deliteralization of a name, decode the instruction, fetch data connected with the instruction, the data comprising at least a first name that is a literalization of a first process and a second name that is a literalization of a second process, the first name and the second name being obtained using the reflective process algebra, communicate at least the first name and the second name for composing the plurality of processes running in parallel; receive a result of the composing, the result comprising another name representing a composition of the plurality of processes; literalize the result of the composing; and save the result of the composing; and an arithmetic and logic unit configured to: receive at least the first name and the second name, perform the composing of the plurality of processes running in parallel, the composing including mathematically deliteralizing the first name to the first process and the second name to the second process, and initiate execution of the first and second processes concurrently; wherein a synchronization of the microprocessor includes a compiler-created explicit synchronization model based on the reflective process algebra.