Patent ID: 7296100

Claim:
A packet buffer write system comprising: a descriptor status array having n locations, a first end and a second end, each of said n locations having the value free or used; a packet buffer comprising a descriptor memory having said n storage locations and a data segment memory having said n storage locations; a plurality said n of unique packet memory slots, each said packet memory slot having a unique one of said descriptor status array locations, a unique one of said descriptor memory locations, and a unique one of said data segment memory locations, said packet memory slots thereby uniquely addressable by each said descriptor status array location; a next host controller which returns a slot-a pointer to said free value in said descriptor status array by searching from said first end of said descriptor status array; a next MAC controller which returns a slot-b pointer to said free value in said descriptor status array by searching from said second end of said descriptor status array; a host Tx controller coupled to said next host controller, said host Tx controller receiving host Tx Data including a Tx header and Tx payload and placing said Tx header into said descriptor storage slot-a, and placing said Tx payload into said data segment slot-a, said host Tx controller thereafter causing said next host controller to change said slot-a descriptor status array location value from said free to said used; a MAC Rx controller coupled to said next MAC controller, said MAC Rx controller receiving MAC Rx Data including an Rx header and Rx payload and placing said Rx header into said descriptor storage slot-b, and placing said Rx payload into said data segment slot-b, said MAC Rx controller thereafter causing said next MAC controller to change said slot-a descriptor status array location value from said free to said used.