Patent ID: 7116145

Claim:
A lock detection circuit in a phase-locked loop circuit including a phase-frequency detector and a voltage-controlled oscillator, comprising: a lock-detection-start-signal generator configured to receive an up signal and a down signal generated by the phase-frequency detector, to generate a delay time, and to further generate a lock detection start signal when a pulse width of the up signal or the down signal is less than the delay time; a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal, a duration of which is determined by rising edges of the up signal and the down signal; and a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator, and count the lock detection clock, to generate a lock detection signal indicative of a lock state in the phase-locked loop circuit.