Patent ID: 7179740

Claim:
A method of forming a chip scale package for a semiconductor device, comprising the steps of: (a) providing a semiconductor body; and (b) forming a via having a via top portion beginning at a top surface of said body and extending through said body to a via bottom portion on a bottom surface of said body; and (c) forming a filler material in said via after step (b), which filler material is used for structural support; (d) forming an input/output (I/O) interconnect physically and electrically coupled to said via bottom portion, said I/O interconnect structure being located within an area on the bottom surface of said body; and wherein said filler material is removed prior to forming said I/O interconnect; (d) forming an I/O signal line using conductive material via that is coupled to said I/O interconnect structure through said via; wherein said package is formed prior to the formation of any electronic circuits located in said semiconductor body.