Patent ID: 8258883

Claim:
A circuit comprising: a plurality of inverters arranged in a sequential loop, the sequential loop having a single feedback to only the plurality of inverters in the sequential loop; a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters, wherein a first one of the plurality of transmission gates comprises: a first field effect transistor (FET) having a first channel, and a second FET having a second channel, wherein the first channel and the second channel are coupled in parallel, and wherein a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively, wherein the first control signal and the second control signal are independent from each other; and wherein a second one of the plurality of transmission gates comprises a third FET coupled to a third control signal different from the first control signal and the second control signal.