Patent ID: 7429766

Claim:
A split gate type nonvolatile memory device comprising: source and drain regions spaced apart from each other on a semiconductor substrate; a supplementary layer pattern on the source region; a gate insulating layer on the semiconductor substrate and top and side surfaces of the supplementary layer pattern; a floating gate on the gate insulating layer at top and side surfaces of the supplementary layer pattern and isolated from the supplementary layer pattern by the gate insulating layer, the floating gate overlapping the supplementary layer pattern and the source region, such that a capacitance between the floating gate and the supplementary layer pattern is determined by an interface area between the floating gate and the top and side surfaces of the supplementary layer pattern; a floating gate poly-insulating layer and a tunneling insulating layer on the top surface of the floating gate and at the side surface of the floating gate, respectively; and a control gate on the floating gate poly-insulating layer and on the tunneling insulating layer.