Patent ID: 8464136

Claim:
A data transfer protection apparatus for a flash memory controller, comprising: an error-correcting-code encode circuit element for receiving a data sequence upon storing action and generating a first parity in accordance with the data sequence; a parity control element for connecting the error-correcting-code encode circuit element, receiving the first parity, selecting a sequence of constant values and outputting a second parity after calculating with the first parity, the second parity being stored in a NAND Flash Chip after combining with the data sequence; wherein the parity control element for receiving the data sequence and the second parity from the NAND Flash Chip upon reading the data sequence, and outputting the first parity after calculating with the sequence of constant values and the second parity; and an error-correcting-code decode circuit element for connecting the parity control element, receiving the data sequence and decoding the first parity, and checking whether the data sequence being correct or not.