Patent ID: 6983346

Claim:
A method modifying cache operation comprising the steps of: storing a last cache-miss address of a last received memory access request address which generated a cache miss; storing a last miss-address valid indicator; setting the last miss-address valid indicator to indicate valid upon a cache-miss with respect to the last miss-address; and resetting the last miss-address valid indicator to indicate invalid upon determining that data corresponding to the last miss-address is stored in the data-RAM; storing a last cache-hit address of a last received memory access request address which generated a cache hit; storing a last hit-address valid indicator; setting the last hit-address valid indicator to indicate valid upon a cache-hit with respect to the last hit-address; and resetting the last hit-address valid indicator to indicate invalid upon determining that a cache line replacement has occurred with respect to the last hit-address; on each memory access, comparing a fetch memory address with both the last cache-miss address and the last cache-hit address; if a match occurs between the fetch memory address and the last cache-miss address and the last miss-address valid indicator indicates valid, or if a match occurs between the fetch memory address and the last cache-hit address and the last hit-address valid indicator indicates valid, bypassing access to a tag-RAM and requesting data from a cache data-RAM; and if a match occurs between the fetch memory address and neither the last cache-miss address nor the last cache-hit address, if a match occurs between the fetch memory address and the last cache-miss address and the last miss-address valid indicator indicates invalid, or if a match occurs between the fetch memory address and the last cache-hit address and the last hit-address valid indicator indicates invalid, accessing the tag-RAM to determine if data is stored in the cache data-RAM.