Patent ID: 6956421

Claim:
A flip flop comprising: a state retention portion to store a bit of digital data, said state retention portion having a first storage node and a second storage node; and a clocking portion to transfer a new bit of digital data to said state retention portion in response to a clock signal, said clocking portion including: a first stack of transistors coupled to said first storage node to draw current from said first storage node when a first digital data value is being transferred to said state retention portion, said first stack of transistors including a first transistor having a gate terminal coupled to receive said clock signal and a second transistor having a gate terminal coupled to receive a delayed, inverted version of said clock signal; wherein said state retention portion includes a single latch and said single latch includes first and second inverters in a cross coupled configuration; wherein said state retention portion includes a first pull up circuit connected between said first inverter and a power supply node and a second pull up circuit connected between said second inverter and said power supply node, said first pull up circuit having a first pull up transistor and a second pull up transistor connected in parallel to provide two separate pull up paths for said first inverter.