Patent ID: 7640398

Claim:
A nonvolatile memory device comprising: a memory array configured to store data; a data register selectively coupled to the memory array and configured to copy at least one page of data between the memory array and the data register; a cache register disposed in the memory device; a first portion of the cache register selectively coupled to the data register and configured to copy the at least one page of data between the data register and the first portion of the cache register; a second portion of the cache register selectively coupled to the data register and the first portion of cache register, the second portion of cache register configured to copy the at least one page of data between either the first portion of the cache register or the data register and the second portion of the cache register; an input-output circuit selectively coupled to both the first portion of the cache register and the second portion of the cache register and configured to serially output a plurality of data bits of the at least one page of data; a control logic circuit selectively coupled to the memory array, the data register, the first portion of the cache register, the second portion of the cache register, and the input-output circuit and configured to selectively couple the second portion of the cache register to the input-output circuit to copy data between the second portion of the cache register and the input-output circuit, the control logic circuit being further configured to simultaneously selectively couple the memory array to the data register to copy data between the memory array and the data register or to simultaneously selectively couple the data register to the first portion of the cache register to copy data between the data register and the first portion of the cache register; and wherein the data register is configured to determine whether the first portion of the cache is full and copy an additional page when the first portion of the cache is not full, determine if the second portion of the cache is full when the first portion of the cache is full, and hold the data in the data register for a pre-defined waiting period, if the first and second portion of the cache is full.