Patent ID: 8549055

Claim:
Circuitry that is usable to perform a selectable one of (1) one M-bit by M-bit (“M×M”) multiplication and (2) two N-bit by N-bit (“N×N”) multiplications, where M is equal to 1.5N, comprising: N×N multiplier circuitry; 0.5N×M multiplier circuitry; 0.5N×N multiplier circuitry; first circuitry for additively combining outputs of the 0.5N×M multiplier circuitry and outputs of the 0.5N×N multiplier circuitry; shifter circuitry for shifting outputs of the N×N multiplier circuitry by a selectable one of (1) zero bits positions and (2) N bit positions toward greater arithmetic significance; and second circuitry for additively combining outputs of the shifter circuitry and outputs of the first circuitry.