Patent ID: 8724420

Claim:
An apparatus comprising: a timer unit configured to generate a pulse having a width inversely proportional to a voltage potential applied to a memory chip; and a voltage divider unit configured to divide the voltage potential down to a lower level, wherein an input of the voltage divider is coupled to an output of the timer unit, and wherein the voltage divider unit's ratio is adjustable through a level programmable device in response to a received level programmable signal, and wherein the voltage divider unit comprises a first p-type metal oxide semiconductor (PMOS) transistor having a source coupled to the voltage potential and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a drain coupled to ground, and wherein a gate of the first PMOS transistor and a gate of the second PMOS transistor are configured such that: both the first PMOS transistor and the second PMOS transistor are operating in their linear region during a write operation; and in response to a signal generated by the timer unit, the second PMOS transistor is turned off so that the voltage potential is applied to the memory chip.