Patent ID: 8769194

Claim:
An information processing system comprising: a first device including a memory cell array that holds storage data, an access control circuit that performs an access operation to the memory cell array and controls a power consumption of the first device; and a second device including a command issuing unit that issues a self-refresh command, a self-refresh exit command, an auto-refresh command, a power-down command, a power-down exit command, and a first command to the first device, wherein the command issuing unit issues the first command to the first device after elapse of a first period at earliest from issuing the power-down exit command, the command issuing unit issues the first command to the first device after elapse of a second period that is substantially the same time length as the first period at earliest from issuing the self-refresh exit command, the first device enters a self-refresh mode in response to the self-refresh command and exits the self-refresh mode in response to the self-refresh exit command, the access control circuit performs a refresh operation of the storage data on a first number of memory cells included in the memory cell array during the self-refresh mode, the access control circuit performs the refresh operation of the storage data on the first number of memory cells in response to the auto-refresh command, the first device enters a power-down mode in response to the power-down command and exits the power-down mode in response to the power-down exit command, the access control circuit reduces the power consumption without performing the refresh operation during the power-down mode, and the access control circuit performs the access operation to the memory cell array in response to the first command.