Patent ID: 7271842

Claim:
A video signal processing circuit for converting a first video signal of a first system having a first number of vertical scan lines to a second video signal of a second system having a second number of vertical scan lines greater than said first number, and wherein said first number of vertical scan lines having a portion of effective scan lines and a portion of scan lines of a pedestal level signal of unvaried value, comprising: a frame memory for storing successive frames of said first video signal; a writing controller for writing the portion of effective scan lines of said first video signal into said frame memory in synchronism with vertical and horizontal synchronous signals corresponding to the first video signal of the first system; a reading controller for reading the portion of the effective scan lines of the video signal written in said frame memory in synchronism with vertical and horizontal reference signals corresponding to the second video signal; a first signal selector for selectively outputting one of the video signal read out from said frame memory and the pedestal level signal, wherein said reading controller controls said signal selector so as to select the output from said frame memory while reading out the portion of the effective scan lines and to select the pedestal level signal, when finished reading the effective scan lines; and a vertical size controller for changing a vertical deflection width in accordance with a ratio of a repetitive frequency of the horizontal reference signal corresponding to the second video signal achieved by multiplying the horizontal synchronous signal corresponding to the first video signal.