Patent ID: 8350590

Claim:
An apparatus comprising circuitry that includes: a clock generation circuit that outputs a first signal, and that includes a first frequency selection section that is configurable to cause the first signal to have a first frequency that is one of a plurality of frequencies that are different; and a further circuit having a clock section that is responsive to the first signal and generates as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency, the further circuit including a second frequency selection section that is configurable to supply to the further circuit a clock signal that is one of the first and second signals; wherein the clock generation circuit outputs a third signal and the first frequency selection section causes: (a) the third signal to have the first frequency and to have a phase shift with respect to the first signal; or (b) the third signal to have the second frequency, the second frequency is less than the first frequency, and the clock section includes a D-type flip-flop having a clock input coupled to the first signal, a further input coupled to the third signal, and an output that carries the second signal.