Patent ID: 7733986

Claim:
A receiver comprising: an input terminal; a receiving unit coupled to the input terminal; a demodulating unit coupled to an output side of the receiving unit; and an output terminal coupled to an output side of the demodulating unit, the receiving unit including: a PLL; a mixer for mixing a local oscillation signal from the PLL and a signal from the input terminal; and a filter coupled to an output side of the mixer, the demodulating unit including: a frequency error detector for detecting a frequency error in a signal from the filter; a CPU for setting a frequency division ratio including an integer portion and a fractional portion; and a frequency controller for computing a correction value based on the detected frequency error and for computing a corrected frequency division ratio by adding or subtracting the correction value to the fractional portion of the frequency division ratio; the PLL including: a local oscillator for supplying the local oscillation signal to the mixer; a variable frequency divider for frequency-dividing the local oscillation signal from the local oscillator at the corrected frequency division ratio; an oscillator; and a phase comparator that is coupled to an input side of the local oscillator and compares a signal from the variable frequency divider with a signal from the oscillator.