Patent ID: 8120119

Claim:
A semiconductor structure comprising: an NMOS transistor including a gate stack and a silicided source or drain contact region, the gate stack defining a channel region thereunder; and a slot contact in contact with a portion of the silicided source or drain contact region below the gate stack, the slot contact being at least twice as long as it is wide, the slot contact comprising an intrinsically tensilely stressed tungsten barrier plug and a contact metal disposed over the intrinsically tensilely stressed tungsten barrier plug, the contact metal having a lower resistivity than the intrinsically tensilely stressed tungsten barrier plug; wherein a bottom thickness of the intrinsically tensilely stressed tungsten barrier plug comprising a bottom portion of the slot contact is greater than a sidewall thickness of the intrinsically tensilely stressed tungsten barrier plug comprising a sidewall portion of the slot contact, and the bottom thickness of the intrinsically tensilely stressed tungsten barrier plug is both above and below a gate dielectric layer of the gate stack such that the slot contact induces a tensile stress on the channel region.