Patent ID: 7171533

Claim:
A storage device, comprising: a memory; a microcomputer for taking in data read from the memory according to a externally-supplied clock signal or a clock signal generated based on the externally-supplied clock signal; a timing signal output circuit for outputting a timing signal indicative of a timing that is shifted by a first predetermined time period, which is determined according to a frequency of the clock signal which allows reading of data, from a predetermined edge in a read control signal which is used for controlling reading of data from the memory; a read data control circuit for performing control based on the timing signal for outputting the data read from the memory to the microcomputer; and a mask circuit for doing the following three steps during each one read cycle: (a) masking the data read from the memory to the microcomputer for the first predetermined time period; (b) allowing to pass the data read from the memory to the microcomputer for a second predetermined time period which is determined according to a frequency of the clock signal which allows reading of the data and; (c) masking the data read from the memory to the microcomputer until the next read cycle begins; wherein the read data control circuit performs control such that the microcomputer takes in the data output from the mask circuit only when the clock signal has a frequency between an upper limit and a lower limit determined according to the first and second predetermined time periods.