Patent ID: 7968443

Claim:
A method for fabricating a CMOS integrated circuit (IC), comprising: providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein said bevel surface and said backside surface comprises silicon or germanium; forming a metal comprising high-k gate dielectric layer on at least said topside semiconductor surface and on at least a portion of said bevel semiconductor surface and said backside semiconductor surface; selectively removing said high-k dielectric layer on said bevel semiconductor surface and said backside semiconductor surface while protecting said high-k dielectric layer on said topside semiconductor surface, said selective removing comprising: a first oxidizing treatment, and following said first oxidizing treatment, a fluoride comprising wet etch, and completing fabrication of said IC including forming at least one metal gate layer on said high-k gate dielectric layer after said selectively removing step.