Patent ID: 8411017

Claim:
A shift register comprising a plurality of shift register units coupled in series, each shift register unit comprising: an input end for receiving an input voltage; an output end for outputting an output voltage; a node; an input circuit for transmitting the input voltage to the node; a pull-up circuit for providing the output voltage according to a first clock signal and a voltage level of the node, wherein the first clock signal periodically switches between a high voltage level and a low voltage level; a first pull-down circuit for maintaining the voltage level of the node according to the first clock signal and a second clock signal, wherein the second clock signal periodically switches between the high voltage level and the low voltage level, and the first and second clock signals have opposite phases in a same period, the first pull-down circuit comprising: a first pull-down unit for controlling a signal transmission path between a first bias voltage and the node according to a first control signal, wherein a voltage level of the first bias voltage is higher than the low voltage level of the first and second clock signals; and a first control unit for providing the first control signal by outputting the first clock signal or the second clock signal according to the voltage levels of the first clock signal, the second clock signal, and the output voltage, the first control unit comprising: a first switch including: a first end for receiving the first clock signal; a second end for outputting the first control signal; and a control end coupled to the first end of the first switch; a second switch including: a first end coupled to the second end of the first switch; a second end for receiving the first clock signal; and a control end for receiving the second clock signal; and a third switch including: a first end coupled to the second end of the first switch; a second end for receiving the second clock signal; and a control end for receiving the output signal; and a second pull-down circuit for maintaining the voltage level of the node according to the second clock signal and a signal transmitted from a prior-stage shift register unit, the second pull-down circuit comprising: a second pull-down unit for controlling a signal transmission path between a second bias voltage and the node according to a second control signal, wherein a voltage level of the second bias voltage is higher than the low voltage level of the first and second clock signals; and a second control unit for providing the second control signal by outputting the first clock signal or the second clock signal according to the voltage levels of the first clock signal, the signal transmitted from the prior-stage shift register unit, and the output voltage.