Patent ID: 8519758

Claim:
A delay locked loop (DLL), comprising: a duty correction circuit configured to receive duty correction control data and including a skewed gate chain; a fine delay line and a coarse delay line configured to delay a selection input signal in response to delay control data; a phase detector configured to compare a phase of a clock for duty correction selected as the selection input signal with a phase of an output clock to generate a first detection value and compare a phase of an input clock with the phase of the output clock to generate a second detection value; a duty cycle detector configured to compare the phase of the output clock with the phase of the clock for duty correction to generate a duty detection value after the clock for duty correction and the output clock are aligned with each other; and a delay line controller configured to receive the first and second detection values and the duty detection value and to apply the duty correction control data and the delay control data to the duty correction circuit and the fine and coarse delay lines, respectively.