Patent ID: 7598802

Claim:
A semiconductor integrated circuit apparatus, comprising: a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors; a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit; a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit; and a first NchMIS transistor formed on a silicon substrate of a silicon-on-insulator structure, wherein: the second pseudo power supply line is connected to a drain of the first NchMIS transistor; a low potential side power supply line is connected to a source of the first NchMIS transistor; a gate of the first NchMIS transistor and the substrate are connected through a current limiter; an absolute value of a threshold voltage of the first NchMIS transistor does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit, or the first NchMIS transistor is a depletion type; and a low level of a signal applied to the gate of the first NchMIS transistor is lower than a potential of the low potential side power supply line.