Patent ID: 8484390

Claim:
A message handler of a communications module, comprising: a message memory, in which data is input or output in response to an access; a first buffer configuration arranged between the message memory and an interface to a communication link; a second buffer configuration arranged between the message memory and an interface to a user processor, the message memory being connected to the first buffer configuration and the second buffer configuration, and the data being accessed via the first or the second buffer configuration; at least one first finite state machine that controls the access to the message memory via the first buffer configuration; at least one second finite state machine that controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; a third finite state machine that assigns access to the message memory to the at least one first finite state machine and the second finite state machine as a function of their access requests; and an arrangement including: (a) processing circuitry adapted for controlling the second buffer configuration such that: in response to an access request in which a message object is to be transmitted between the message memory and the user processor, transmission of the message object to its target destination via the second buffer configuration is postponed until after the message object is fully loaded into the second buffer configuration; and while the transmission is postponed, further access requests between the message memory and the user processor along the same transmission direction are disabled; and (b) a first register storing a start identifier that indicates a start of transmission to the target destination, and a second register storing a message identifier that indicates whether a transmission is on-going.