Patent ID: 8713508

Claim:
A semiconductor device comprising: a semiconductor chip, the semiconductor chip including: a substrate; a multilayer interconnect layer formed over the substrate; an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell; an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell; a potential supply cell provided in one of the outer peripheral cell column and the inner peripheral cell column, the potential supply cell being one of a power potential supply cell and a ground potential supply cell; electrode pads formed in the uppermost interconnect layer of the multilayer interconnect layer, at least one of the electrode pads being provided in the first I/O cell, at least one of the electrode pads being provided in the potential supply cell, at least one of the electrode pads being provided in the second I/O cell; a first potential supply interconnect provided in an interconnect layer below the uppermost interconnect layer, the first potential supply interconnect being extending in the same direction as the outer peripheral cell column, the first potential supply interconnect being connected to the first I/O cell; a second potential supply interconnect provided in another or the interconnect layer below the uppermost interconnect layer, the second potential supply interconnect being extending in the same direction as the inner peripheral cell column, the second potential supply interconnect being located at an inner peripheral side of the first potential supply interconnect in a plan view, the second potential supply interconnect being connected to the second I/O cell; and a potential-supply connection interconnect connecting the first potential supply interconnect and the second potential supply interconnect, wherein the potential supply cell directly connects to one of the first potential supply interconnect and the second potential supply interconnect, and connects through the potential-supply connection interconnect to the other one of the first potential supply interconnect and the second potential supply interconnect.