Patent ID: 8178917

Claim:
A non-volatile semiconductor storage device comprising: a first layer provided on a substrate, and functioning as a plurality of electrically rewritable memory cells connected in series; and a second layer provided on the substrate around the first layer, and separately-placed from the first layer along a direction parallel to the substrate, the first layer comprising: a plurality of first conductive layers extending parallel to a substrate and laminated in a direction perpendicular to the substrate, the first conductive layers functioning as control gates of the memory cells; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer and configured to be able to accumulate charges, respective ends of the first conductive layers being formed in a stepwise manner in relation to each other in a first direction, the second layer comprising: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers, and respective ends of the second conductive layers being formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.