Patent ID: 7555083

Claim:
A synchronizing circuit comprising: an input signal synchronized with a transition of a first clock; an input device for generating a first signal in response to the input signal, for storing the first signal to be synchronized with a transition of a second clock by feeding back the first signal to the input device, and for initializing the first signal in response to a second signal; a first device for generating a third signal in synchronization with the transition of the second clock in response to the first signal; a second device for generating the second signal in synchronization with the transition of the second clock in response to the third signal; and a pulse generator for generating an output signal in response to the second and third signals, wherein the input device comprises: an input signal processor for generating a set signal in response to the input signal, for generating a reset signal in response to the second signal, and for generating a maintenance signal in response to the first signal fed-back to the input signal processor; and a third device for generating the first signal in synchronization with the transition of the first clock in response to the set signal, for storing the first signal so that the first signal is synchronized with the transition of the second clock in response to the maintenance signal, and for initializing the first signal in synchronization with the transition of the first clock in response to the reset signal.