Patent ID: 8499261

Claim:
A method of fabricating a semiconductor device, comprising: providing a layout design for the semiconductor device, the layout design containing a plurality of features; categorizing the plurality of features into a plurality of first features and a plurality of second features, each of the first features being spaced apart from adjacent first features at respective distances that are less than a predetermined distance, and each of the second features being spaced apart from adjacent second features at respective distances that are greater than the predetermined distance; sorting the first features into first and second subsets of features in a manner so that each of the features in the first and second subsets is spaced apart from adjacent features in the respective subset at respective distances that are greater than the predetermined distance; sorting the second features into third and fourth subsets of features in a manner so that a number of features in the third subset is free of substantial deviation from a number of features in the fourth subset; forming a first mask pattern with the first and third subsets of features; and forming a second mask pattern with the second and fourth subsets of features; wherein the predetermined distance is a function of one or more parameters selected from the group consisting of: a critical dimension of a semiconductor fabrication process; a wavelength of a radiation wave used in a photolithography process of the semiconductor fabrication process; a numerical aperture of a lens used in the photolithography process; and a process compensation factor.