Patent ID: 7911011

Claim:
A method of fabricating an electromechanical non-volatile memory device, the method comprising: forming first electrode patterns on a semiconductor substrate including an upper surface having insulation characteristics; forming a sacrificial layer pattern on sidewalls of the first electrode patterns; forming a bit line on the first electrode patterns and the sacrificial pattern using a conductive material having an elasticity generated by a voltage difference; forming an insulating layer on the bit line; forming a second electrode pattern in a gap between the first electrode patterns on the insulating layer; removing the sacrificial layer pattern and a portion of the insulating layer such that a residual of the insulating layer remains on an upper surface of the bit line formed on the substrate between the first electrode patterns; and forming a charge trap structure on the sidewalls and an upper surface of the first electrode pattern, wherein forming the charge trap structure comprises: forming a first dielectric layer, a charge trap layer and a second dielectric layer on a surface of the first electrode pattern and a surface of the semiconductor substrate; forming a mask pattern on the second dielectric layer formed on an upper surface and the sidewall of the first electrode pattern; and etching the second dielectric layer, the charge trap layer and the first dielectric layer on the semiconductor substrate using the mask pattern as an etching mask to form the charge trap structure.