Patent ID: 7251740

Claim:
An apparatus, comprising: a clock source to generate a clock signal; a first circuit, coupled to a first supply voltage source, to generate a first data signal and a second circuit coupled to a second supply voltage source; a flip-flop, having a pair of inputs coupled to the clock source and the first circuit, to generate a second data signal in response to the clock signal and the first data signal, with the flip-flop including a master latch and an upstream slave latch coupled to the master latch; a first level shifter, coupled to the flip-flop, to generate a level shifted data signal in response to the second data signal; a delay element coupled to the clock source and responsive to the clock signal to generate a delayed clock signal having a triggering clock edge and a non-triggering clock edge; a downstream slave latch, having an open state and a close state, a pair of inputs coupled to the first level shifter and the delay element and an output coupled to the second circuit, to generate an output data signal in response to the level shifted data signal and the delayed clock signal, with the triggering clock edge of the delayed clock signal switching the downstream slave latch from the close state to the open state; a second level shifter, coupled between the clock source and the downstream slave latch and in series with the delay element, and wherein the level shifted data signal has a plurality of rising and falling data edges and the delay element is operable to delay an arrival of the triggering clock edge at the downstream slave latch until after an arrival of the rising and falling data edges at the downstream latch.