Patent ID: 8432209

Claim:
A device, comprising a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop comprises: a retention latch that comprises a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that comprises a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during the power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginning of the power gating period.