Patent ID: 8872574

Claim:
An interpolation circuit comprising: an input terminal; a fourth switch configured to receive a first current corresponding to first input data from the input terminal, a second current corresponding to second input data from the input terminal and a third current corresponding to third input data from the input terminal; a first node, coupled to the fourth switch, configured to receive the first current from the fourth switch; a second node, coupled to the fourth switch, configured to receive the second current from the fourth switch; a third node, coupled to the fourth switch, configured to receive the third current from the fourth switch; a first capacitor circuit, the first capacitor circuit including: a plurality of first capacitors; a first switch configured to couple one end of each of the plurality of first capacitors to one of the first node and the second node; and a first output coupled to the other end of each of the plurality of first capacitors; a second capacitor circuit, the second capacitor including: a plurality of second capacitors; a second switch configured to couple one end of each of the plurality of second capacitors to one of the second node and the third node; and a second output node coupled to the other end of each of the plurality of second capacitors; and a third capacitor circuit, the third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch configured to couple the other end of the third capacitor to one of the first output node and the second output node.