Patent ID: 8195705

Claim:
An apparatus comprising: an embedded processor complex including a plurality of protocol processors; a control point processor coupled to the processor complex; a plurality of hardware accelerator co-processors accessible to each protocol processor and providing high speed pattern searching, data manipulation and frame parsing; at least one memory device, coupled to the processor complex, that stores data structures including a Direct Table, nodes, and leaves chained together; a Memory location coupled to the processor complex and storing a value representative of the maximum number of nodes to be accessed during a tree search routine wherein said maximum number of nodes is fewer than a total number of nodes available to be accessed during said tree search routine; a Contents Address Memory (CAM) coupled to the processor complex and storing pointers identifying a location whereat a leaf is stored; and a circuit that deletes pointers from the CAM based on one of leaf adjustments in the tree structure and none use of the information within predetermined time interval.