Patent ID: 7313752

Claim:
An apparatus for encoding a block low density parity check (LDPC) code, comprising: a first matrix multiplier for multiplying a received information word by a first partial matrix of a parity check matrix comprised of an information part corresponding to an information word, and a first parity part and a second parity part each corresponding to a parity; a second matrix multiplier for multiplying the information word by a second partial matrix of the parity check matrix; a third matrix multiplier for multiplying a signal output from the first matrix multiplier by a matrix product of a third partial matrix and an inverse matrix of a fourth partial matrix of the parity check matrix; a first adder for adding a signal output from the second matrix multiplier and a signal output from the third matrix multiplier; a fourth matrix multiplier for multiplying a signal output from the first adder by a fifth partial matrix of the parity check matrix; a second adder for adding a signal output from the first matrix multiplier and a signal output from the fourth matrix multiplier; a fifth matrix multiplier for multiplying a signal output from the second adder by the inverse matrix of the fourth partial matrix of the parity check matrix; and switches for multiplexing the information word, the output signal of the first adder as a first parity, and the output signal of fifth matrix multiplier as a second parity, according to a format of the block LDPC code.