Patent ID: 6998674

Claim:
A semiconductor integrated circuit device comprising: a plurality of static type memory cells respectively having a pair of load P-channel transistor and a driver N-channel transistor, an insulating layer for use in a gate of either of the load P-channel transistor or the driver N-channel transistor has a thickness of 4 nm or less; a power line being connected to source electrodes of each of the load P-channel transistors, through which power is supplied to each of the load P-channel transistors; and a source line being connected to source electrodes of each of the driver N-channel transistors; wherein a voltage difference between a voltage on the power line and another voltage on the source line is controlled to be set at a first value in an operating mode with a first current flowing from the load P-channel transistor to ground through the driver N-channel transistor, and wherein the voltage difference is further controlled to be set at a second value lower than the first value in a standby mode with another current at least one digit less than the first current.