Patent ID: 7595660

Claim:
A converter to convert a complementary metal-oxide semiconductor (CMOS) input signal to a differential emitter-coupled logic (ECL) output signal, the converter comprising: a reference level generator circuit comprising: first and second transistors connected in series between a first CMOS supply voltage and a second CMOS supply voltage, and using as their gate input signals a bias signal, the bias signal to have a first value substantially mid-way between the first and second CMOS supply voltages; and first and second components connected in series between the first and second transistors, the bias signal to be created at a first node where the first and second components are connected, the first component to create a first reference signal to have a second value a first voltage above the bias signal, the second component to create a second reference signal to have third value a second voltage below the bias signal; a source follower circuit comprising third and fourth transistors connected in series between the first and second reference signals in a source follower topology to create a single-ended ECL signal, the single-ended ECL signal to be created at a second node where the third and fourth transistors are connected, the third and fourth transistors using as their gate input signals the CMOS input signal; and an ECL buffer circuit to generate the differential ECL output signal based on the single-ended ECL signal and the bias signal.