Patent ID: 6967892

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix; a word line connected to two or more of the memory cells arranged in a row direction; a source line connected to two or more of the memory cells; a row decoder circuit configured to supply a write verify voltage to the word line; a plurality of bit lines each connected to two or more of the memory cells arranged in a column direction; and a plurality of bit line control circuits each being provided for at least one of the bit lines, and each storing data of a first logic level or a second logic level, wherein the bit line control circuit storing data of the first logic level performs a detection operation for detecting a written state of a first memory cell corresponding to the bit line control circuit storing data of the first logic level after a predetermined period from completion of a charging operation for charging a first bit line corresponding to the bit line control circuit storing data of the first logic level, and during the predetermined period, a first voltage is supplied to a second bit line corresponding to the bit line control circuit storing data of the second logic level.