Patent ID: 8225240

Claim:
A semiconductor device, comprising: a plurality of circuit patterns formed at regular intervals, and used as a part of a circuit; a first dummy pattern formed outside one of the circuit patterns that is positioned outermost, wherein a distance between an outermost circuit pattern and the first dummy pattern is equal to a distance between any adjacent two of the circuit patterns, and wherein a width of the first dummy pattern is less than a width of any of the circuit patterns, wherein each circuit pattern of the plurality of circuit patterns has a same shape, and is disposed so that end parts of the circuit patterns on either side are aligned with each other in an extending direction of the circuit patterns, and wherein the first dummy pattern has a same length as a length of the circuit pattern, and is disposed so that an end part of the first dummy pattern on either side is aligned with the end parts, on a same side, of the circuit patterns in an extending direction of the first dummy pattern; and second dummy patterns formed respectively outside both end parts of each of the plurality of circuit patterns, wherein a distance between each of the second dummy patterns and a corresponding one of the circuit patterns is equal to the distance between the outermost circuit pattern and the first dummy pattern, wherein a width of each of the second dummy patterns is equal to a width of the circuit patterns in a width direction of the circuit patterns, wherein a distance between any adjacent two of the second dummy patterns is equal to a distance between any adjacent two of the circuit patterns, and wherein a length of each of the second dummy patterns is less than the width of the circuit patterns in the extending direction of the circuit patterns.