Patent ID: 8358551

Claim:
A semiconductor memory storage device comprising: a plurality of data storage cells, said plurality of data storage cells being arranged in an array; said array comprising a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of said column; precharge circuitry for precharging said output lines to a predetermined voltage, said precharge circuitry comprising a plurality of switching devices corresponding to said plurality of columns each switching device controlled by a data output request signal and a power mode signal, said power mode signal being transmitted to at least some of said switching devices along a single transmission path such that said signal is sent to said at least some switching devices in series; said plurality of switching devices each comprising at least two switches, said at least two switches comprising a data output switch controlled by said data output request signal and a power mode switch controlled by said power mode signal, said plurality of switching devices connecting said output lines to said predetermined voltage in response to both said power mode signal indicating an operational mode and said data output request signal indicating data is to be output; wherein said power mode switch is configured to have a higher capacitance than said data output switch.