Patent ID: 8161246

Claim:
A microprocessor, comprising: a cache memory; a translation lookaside buffer; a tablewalk engine, configured to generate a load request of a page table entry in response to an indication that a first virtual address that implicates the page table entry is missing in the translation lookaside buffer; and a prefetch unit, configured to receive a physical address of a first cache line that includes a page table entry specified by a load request, the prefetch unit further configured to responsively generate a request to prefetch into the cache memory a second cache line, wherein the second cache line is the next physically sequential cache line to the first cache line, wherein the second cache line contains a plurality of page table entries, wherein the plurality of page table entries store a physical page address of a corresponding plurality of physical memory pages; and wherein the tablewalk engine is further configured to perform a tablewalk in response to an indication that a second virtual address is missing in the translation lookaside buffer, wherein the second virtual address implicates one of the plurality of page table entries contained in the prefetched second cache line, wherein to perform the tablewalk engine loads into the translation lookaside buffer from the cache memory, rather than from system memory, the physical page address stored in the one of the plurality of page table entries implicated by the missing second virtual address, wherein an access to the system memory to obtain the physical page address is avoided.