Patent ID: 8589469

Claim:
A multiplication engine for a digital processor comprising: a plurality of multipliers, each receiving a first operand and a second operand; a local operand register having a plurality of locations to hold the first operands for plurality of multipliers, wherein the plurality of locations correspond to respective ones of the multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of the second operands from the compute register file to respective ones of the multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the plurality of locations the local operand register to respective ones of the multipliers, to supply the second operands from the compute register file to respective ones of the multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein the control unit, upon detecting a first multiplication operation being executed by a first multiplier, causes the first operands to shift in the local operand register by a number of bits equal to a width of the first operands to respective next locations in the plurality of locations of the local operand register and supplies the shifted first operands to at least one subsequent multiplier corresponding to the respective next locations, thereby causing one or more of the first operands in the local operand register used by the first multiplier in the first multiplication operation to be reused by the at least one subsequent multiplier in at least one subsequent multiplication operation, and enabling two or more multiply instructions to be executed without reloading the local operand register with a complete set of new operands after each multiplication operation.