Patent ID: 8336010

Claim:
A method for analysis of a circuit design, the method comprising: receiving a design specific netlist of an integrated circuit design having a plurality of data paths; performing a first static timing analysis on a subset of data paths in the design specific netlist in response to a process corner library and a general on chip variation de-rating factor, wherein the static timing analysis generates first path timing data for the subset of data paths in the design specific netlist; performing a statistical static timing analysis on the subset of data paths in the design specific netlist in response to a process sensitive delay library, wherein the statistical static timing analysis generates second path timing data for the subset of data paths in the design specific netlist; with a processor, calculating one or more design-specific on-chip-variation (DS-OCV) de-rating factors in response to the first path timing data and the second path timing data, the one or more design-specific on chip variation de-rating factors to provide improved design specific timing results in a second static timing analysis of data paths in the design specific netlist.