Patent ID: 7483825

Claim:
A method for use with a digital design comprising standard logic elements of design source components for a cycle simulation verification model for use in validating said digital design, comprising the steps of: using a hybrid cycle simulation model and netlisting design source components utilizing a netlist tool which traverses a hierarchy of said digital design for purposes of identifying hierarchical design source components to use from a design library or data management system, and checking that all inputs and outputs of any hierarchical design source components properly bind, and creating netlist structural VHDL output from said hierarchical design source components for use in a next step for simulation, including constructing a hybrid cycle simulation model in which all design source components are compiled into 1-Cycle CDUs, all design source components are compiled into 2-Cycle CDUs, or the design source components are compiled into a combination of 1-Cycle and 2-Cycle CDUs, and wherein is included a merge and build step wherein said mixture of 1-cycle and 2-cycle CDUs are incorporated into a flattened cycle simulation model comprised of internal data structures representing said low level primitive blocks thereby producing a cycle simulation model containing a mixture of 1-cycle and 2-cycle CDU representations of design component source.