Patent ID: 7005714

Claim:
A semiconductor memory comprising a memory cell matrix including a plurality of cell columns arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors serially arranged along a column-direction, the memory cell matrix comprising: a plurality device isolation films running along the column direction, arranged alternatively between the cell columns; a plurality of first conductive layers arranged along the row and column-directions, a group of the first conductive layers arranged along one of column-direction is assigned to a corresponding cell column, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups; a plurality of lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, each of the lower inter-electrode dielectrics is made of insulating material containing at least silicon and nitrogen; an upper inter-electrode dielectric arranged both on the device isolation films and the lower inter-electrode dielectric so that the upper inter-electrode dielectric can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns, the upper inter-electrode dielectric is made of insulating material different from the lower inter-electrode dielectrics; and a plurality of second conductive layers running along the row-direction, each of the second conductive layers arranged on the upper inter-electrode dielectric so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.