Patent ID: 8547774

Claim:
A method comprising: simultaneously transmitting a plurality of bank access addresses from each of a first plurality of ports to each of a first plurality of memory banks implemented with single-port memory cells, wherein each of the first plurality of ports is designated as either a read port or a write port; and during each access cycle, within each memory bank of the first plurality of memory banks: comparing a unique bank address assigned to the memory bank with the bank access addresses provided from each of the first plurality of ports; initiating a read operation to the memory bank in response to detecting that the unique bank address assigned to the memory bank matches a bank access address provided by a port of the first plurality of ports designated as a read port; and initiating a write operation to the memory bank in response to detecting that the unique bank address assigned to the memory bank matches a bank access address provided by a port of the first plurality of ports designated as a write port.