Patent ID: 7616042

Claim:
A clock generator circuit comprising: a pre-stage and a post-stage toggle flip-flop circuit capable of outputting a pair of frequency-divided clock signals with different phases; and a delay flip-flop circuit capable of outputting a clock signal with a phase shifted with respect to the phases of the pair of frequency-divided clock signals being outputted from said post-stage toggle flip-flop circuit by delaying either one of the pair of frequency-divided clock signals being outputted from said post-stage toggle flip-flop circuit; wherein said post-stage toggle flip-flop circuit receives, as clock input, one of a pair of frequency-divided clock signals being outputted from the pre-stage toggle flip-flop circuit, said delay flip-flop circuit receives, as clock input, the other of the pair of frequency-divided clock signals being outputted from said pre-stage toggle flip-flop circuit, while the delay flip-flop circuit receives, as data input, either one of the pair of frequency-divided clock signals being outputted from said post-stage toggle flip-flop circuit; each of said pre-stage and post-stage toggle flip-flop circuits comprises a first latch circuit and a second latch circuit; the output signal of the first latch circuit is inputted to the second latch circuit and is outputted as the one of the pair of frequency-divided clock signals, while the output signal of the second latch circuit is inputted to the first latch circuit and is outputted as the other of the pair of frequency-divided clock; and the output signal outputted from the first latch circuit of the pre-stage toggle flip-flop circuit is inputted, as clock input, to the first latch circuit of the post-stage toggle flip-flop circuit and an inverted signal of the output signal outputted from the first latch circuit of the pre-stage toggle flip-flop circuit is inputted, as clock input, to the second latch circuit of the post-stage flip-flop circuit.