Patent ID: 7868953

Claim:
A thin film transistor array panel comprising: an insulating substrate; a gate line having a gate electrode and a storage capacitor electrode line formed on the insulating substrate; a gate insulating layer covering the gate line and the storage capacitor electrode line; a first contact hole formed at the gate insulating layer while exposing the storage capacitor electrode line; a semiconductor pattern formed on the gate insulating layer while being overlapped with the gate electrode; a data line assembly and a storage capacitor conductive pattern formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having a data line, a source electrode and a drain electrode, the storage capacitor conductive pattern being connected to the storage capacitor electrode line through the first contact hole; a passivation layer covering the data line assembly, the storage capacitor conductive pattern and the semiconductor pattern; a second contact hole formed at the passivation layer while exposing the drain electrode; and a pixel electrode formed at the passivation layer while being connected to the drain electrode through the second contact hole, the pixel electrode being overlapped with the storage capacitor conductive electrode to thereby form a first storage capacitor while being partially overlapped with the storage capacitor electrode line to thereby form a second storage capacitor, wherein the storage capacitor conductive pattern has an island shape.