Patent ID: 7764135

Claim:
A circuit arrangement for generating a clock signal for an electronic circuit, wherein the electronic circuit is of the type having a minimum duration clock signal pulse width to which the electronic circuit is responsive, the circuit arrangement comprising: a crystal oscillator circuit configured to generate an input signal; a variable threshold, multi-stage pulse shaping circuit coupled to the crystal oscillator circuit and configured to generate a pulse shaped signal from the input signal, wherein the pulse shaping circuit includes a plurality of stages, each stage including: a Schmitt trigger having a programmable trip point coupled to a voltage reference; a latch having first and second inputs coupled to an output of the Schmitt trigger; a delay coupled intermediate the second input of the latch and the output of the Schmitt trigger; and a first inverter coupled intermediate the second input of the latch and the output of the Schmitt trigger; a divider circuit configured to frequency divide the pulse shaped signal; first and second one shot circuits coupled to an output of the divider circuit; a second inverter coupled intermediate the output of the divider circuit 30 and the second one shot circuit; and a combiner circuit configured to combine the pulse shaped signal with outputs of the first and second one shot circuits.