Patent ID: 8258570

Claim:
A semiconductor device comprising: a substrate; a first insulator formed in a first area of the substrate, and a second insulator formed in a second area of the substrate; a first transistor formed over a first device region surrounded by the first area, the first transistor comprising a first gate insulating film having a first thickness, the first gate insulating film being formed over the first device region, a first gate electrode formed over the first gate insulating film, and first source and drain regions formed in the first device region at both sides of the first gate electrode; a second transistor formed over a second device region surrounded by the second area, the second transistor comprising a second gate insulating film formed over the second device region, the second gate insulating film having a second thickness less than the first thickness of the first gate insulating film, a second gate electrode formed over the second gate insulating film, and second source and drain regions formed in the second device region at both sides of the second gate electrode; a third insulator formed in a third area of the substrate; and a memory cell formed over a third device region surrounded by the third area, the memory cell further comprising a tunnel insulating film formed over the third device region, a floating gate formed over the tunnel insulating film, an insulating film formed over the floating gate, a control gate formed over the tunnel insulating film, and third source and drain regions formed in third device region at both sides of the floating gate and the control gate; wherein a first height of a top surface of the first insulator is less than a second height of a top surface of the second insulator, and wherein the first height of the top surface of the first insulator is less than a third height of a top surface of the third insulator.