Patent ID: 7911866

Claim:
A semiconductor memory comprising: a plurality of memory blocks each having memory cells; a command input unit receiving, from an exterior of the semiconductor memory, an access request for executing an access operation in which data is inputted or outputted to/from one of the memory blocks; and a memory control unit executing the access operation on one of the memory blocks and a refresh operation on at least one of the memory blocks on which the access operation is not executed, in response to the access request, wherein the memory control unit includes: a plurality of operation control units provided in correspondence with the plurality of memory blocks respectively and controlling operations to the memory blocks, wherein each of the plurality of operation control units includes a refresh hold circuit holding a refresh request, and a block control circuit, and wherein the block control circuit executes a refresh operation on a corresponding memory block when the access request does not address the corresponding memory block and the refresh hold circuit holds the refresh request, and starts executing the refresh operation on the corresponding memory block in a future access cycle in synchronization with an access operation corresponding to an access request in the future access cycle when the access request in the future access cycle does not address the corresponding memory block and the refresh hold circuit holds the refresh request, and wherein the memory control unit further includes: a refresh request generation unit, provided in correspondence with the memory blocks respectively, generating the refresh request at a predetermined cycle and sequentially outputting generated refresh requests to one of the operation control units, wherein the block control circuit provides and executes, in correspondence with each of the plurality of operation control units the access operation on the corresponding memory block when the access request addresses the corresponding memory block, and wherein the semiconductor memory further comprises: a timing control unit generating a common timing signal for determining a generation timing of access control signals outputted by the block control circuits, wherein said block control circuits simultaneously execute the access operation and the refresh operation on said memory blocks by using the access control signals which are synchronous with the timing signal.