Patent ID: 7326601

Claim:
A method for fabricating a stressed MOS device comprising the steps of: providing a silicon on insulator substrate comprising a thin layer of silicon on an insulator, the silicon on insulator substrate having a surface and a channel abutting the surface; forming a gate electrode overlying the thin layer of silicon, the gate electrode having a first edge and a second edge; anisotropically etching the thin layer of silicon to form a first recess aligned with the first edge and a second recess aligned with the second edge; isotropically etching the thin silicon layer to form a third recess extending from the channel to the insulator; filling the third recess with an expanding material to exert an upward force on the channel; filling the first recess and the second recess with a contact material; and ion implanting conductivity determining ions into the contact material to form a source region and a drain region aligned with the first edge and the second edge, respectively.