Patent ID: 7861105

Claim:
An apparatus for data clock and data recovery in a communication transmitter-receiver system comprising: a reference clock signal input, the reference clock signal to be received over a communication channel from a transmitter and having a fixed, divide by an integer “N”, frequency relationship to the data clock; a data input enabled to receive data transmitted at the data clock rate; a phase locked loop (PLL) having its input connected to the reference clock signal input to generate a signal having a frequency equal to the data clock, and with a phase relationship to the data clock; a delay locked loop (DLL) coupled to said PLL to generate multiple clock signals with the data clock frequency but with fixed successive phase delays between the multiple clock signals; an interpolator coupled to said DLL to select a clock signal from the clock signals generated, and further to adjust the phase of the selected clock signal in a delay circuit based on a feedback received to provide a recovered data clock signal; a latch, coupled to a recovered data clock output of the interpolator and to the data input, to provide a latched data output; a digital feedback loop, including a timing loop module, coupled to the latched data output and the interpolator, and generating the feedback to the interpolator, the feedback having at least a seven bit resolution; such that the recovered data clock signal has the same frequency and phase as the received data to automatically enable the latch to latch data at the center of a data eye, thereby recovering the data clock and data with high noise margin and low error rate.