Patent ID: 8739006

Claim:
An error correction code (ECC) syndrome generator circuit comprising: first syndrome generator circuitry for receiving data symbols and generating partial odd syndromes, SP j (k)'s, for odd values of j, for each bit location k of an output data symbol, wherein k=0, 1, 2, . . . K−1 bits; second syndrome generator circuitry for receiving said partial odd syndromes, SP j (k)'s, for odd values of j, and computing partial even syndromes, SP j (k)'s for even values of j, for each bit location k; and, first accumulator circuitry for receiving the partial odd syndromes and the computed partial even syndromes, SP j (k), and computing the syndromes S j =Σ k SPj(k), j is number of syndromes to be generated and k is number of bits of a data symbol.