Patent ID: 7421610

Claim:
A clock generation circuit that receives an input clock signal and generates an output clock signal, the clock generation circuit comprising: a first latch circuit that receives the input clock signal at a clock input thereof; a second latch circuit that receives the input clock signal at a clock input thereof; a first plurality of buffers connected in series, wherein a first buffer of the first plurality of buffers receives the input clock signal and a last buffer of the first plurality of buffers outputs a buffered input clock signal; a second plurality of buffers connected in series, wherein a first buffer of the second plurality of buffers receives an output of the second latch circuit and a last buffer of the second plurality of buffers outputs a divided clock signal; a selector circuit that receives at first and second data inputs respectively, the buffered input clock signal and the divided clock signal, and at a control input thereof a selector control signal, wherein an output of the selector circuit is the output clock signal; and a logic gate having a first input connected to an output of the first latch circuit and a second input that receives a scan mode signal, wherein an output of the logic gate is the selector control signal.