Patent ID: 8625015

Claim:
An analog-to-digital (AD) conversion circuit comprising: a reference signal generation section configured to generate a reference signal that increases or decreases with the passage of time; a comparison section configured to compare an analog signal to be subjected to AD conversion to the reference signal and configured to terminate a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal; a first count section configured to count a clock signal of a predetermined frequency as a count clock and outputting a count value; a latch section configured to latch the count value output from the first count section; and a latch control section configured to enable the latch section at a first timing related to an end of the comparison process and configured to cause the latch section to execute a latch operation at a second timing delayed by a predetermined time from the first timing, wherein digital data corresponding to the analog signal is output on the basis of the count value latched in the latch section.