Patent ID: 8369129

Claim:
A semiconductor memory device comprising: a variable resistance element configured to store a first data and a second data in accordance with a change in resistance value; a current generator configured to generate a reference current for determining data of the variable resistance element, and having a middle admittance between an admittance of the variable resistance element storing the first data and an admittance of the variable resistance element storing the second data; and a sense amplifier comprising a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal, wherein the middle admittance Ymid satisfies the following equation Y mid =( R max + R min)/(2 R max* R min) where Rmin is a resistance value of the variable resistance element storing the first data, and Rmax is a resistance value of the variable resistance element storing the second data.