Patent ID: 7167516

Claim:
A circuit for canceling precursor intersymbol interference from a received signal comprising: an analog to digital converter responsive to the received signal and having a sampling clock; an adaptive timing loop circuit to adjust a timing phase of said sampling clock so configured to remove a first precursor intersymbol interference from said signal, wherein said adaptive timing loop circuit comprises: a first delay element responsive to an error signal; a first multiplier circuit responsive to said first delay element and an estimate signal; a second multiplier circuit responsive to a loop gain control constant and said first multiplier circuit; a first summing circuit; and a second delay element responsive to said summing circuit, wherein said summing circuit is responsive to said second multiplier and said second delay element; and an open loop finite impulse response filter in communication with an output of said analog-to-digital converter having a coefficient determined by a gain mapping of a condition measurement of the received signal to remove all precursor intersymbol interference except for the first precursor intersymbol interference.