Patent ID: 7461284

Claim:
A method of minimizing elasticity FIFO queue size for synchronizing data between two clock domains comprising: writing a data block to a write location specified by a write pointer of said elasticity FIFO queue on each write clock cycle of a write clock; reading said data block from a read location specified by a read pointer of said elasticity FIFO queue on each read clock cycle of a read clock, said read location being behind said write location in said elasticity FIFO queue; and performing adjustment clock tasks on each adjustment clock cycle of an adjustment clock, said adjustment clock tasks further comprising: calculating a separation number of locations between said write pointer and said read pointer, said separation number of locations being a count of locations that said write location would need to catch up to said read location; calculating a correction number of locations, said correction number of locations being the greater of zero and a separation threshold number of locations subtracted from said separation number of locations; searching said elasticity FIFO queue for consecutive null locations, said consecutive null locations starting at said read location and ending at a last consecutive null location, each location of said consecutive null locations containing a null character; and adjusting said read pointer to specify an adjusted read location, said adjusted read location being one location after skipped locations, said skipped locations being a subgroup of said consecutive null locations starting at a first null location of said consecutive null locations and continuing for the lesser of said correction number of locations and a total count of said consecutive locations.