Patent ID: 8166286

Claim:
A data pipeline comprising: a first stage having: a data input for receiving a digital data input signal; a clock input and a data output; and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal; and a dynamic latch stage having: an input transfer element that is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time which is shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer during the first period of time; and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the second bi-stable element includes a pair of cross coupled inverters, and wherein the output of one inverter being coupled to the input of the other inverter through at least one transfer element, and the transfer element being adapted to transfer the output signal of one inverter to the input of the other inverter except during the first period of time.