Patent ID: 8786032

Claim:
A p-type semiconductor device, comprising: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack, which is positioned on the channel region, comprising a gate dielectric layer and a gate electrode layer; wherein the gate dielectric layer is positioned on the channel region, and the gate electrode layer is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the gate dielectric layer comprises a first dielectric layer and at least two second dielectric layers, the first dielectric layer being sandwiched between said two second dielectric layers, and the first dielectric layer is a high k gate dielectric layer, and the second dielectric layers are oxide or nitride layers containing Al and are positioned above and below the first dielectric layer as upper and lower second dielectric layers, respectively, the element Al being distributed at an upper surface of the upper second dielectric layer and a bottom surface of the lower second dielectric layer.