Patent ID: 8196111

Claim:
A verification testing system for a multiprocessor computer system comprising multiple parallel processor threads, comprising: a semaphore manager connected to the microprocessor and configured to rout ordered semaphore command instructions to the microprocessor threads; and a memory device comprising a plurality of buckets of executable ordered semaphore test commands, each bucket comprising a plurality of the commands arranged in different sequentially ordered command sequences legal under at least one rule for forming legal ordered sequences of semaphore commands; the semaphore manager configured to combine buckets by randomly selecting the buckets and an order of the buckets within a sequential bucket test combination wherein an order of any of the buckets relative to another of the buckets may be changed and the sequential test combination remain legal under the at least one rule and thereby generate a predictable result when executed by the threads; and wherein the semaphore manager is configured to sequentially distribute at least one each of the composite test command sequence commands to a first plurality of the processor threads and observe the performance of each of the first plurality of threads.