Patent ID: 8315094

Claim:
A semiconductor memory device comprising: first to sixth bit lines formed with metal wires of a second layer and arranged at a first pitch in parallel to one another, end portions of the first to sixth bit lines being aligned neatly along a line; first to third sense-amplifier bit lines formed with metal wires of the second layer and arranged at a second pitch that is twice larger than the first pitch at positions away respectively from the end portions of the second, the fourth, and the sixth bit lines in a bit-line direction; a fourth sense-amplifier bit line formed with a metal wire of a first layer arranged below the fourth bit line, an end portion of the fourth sense-amplifier bit line receding from the end portion of the fourth bit line; first and second selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines, a source region and a drain region located respectively on two sides of the pair of gate electrodes connected respectively to the first and second bit lines; third and fourth selection transistors with a pair of gate electrodes arranged in a direction normal to the first to third sense-amplifier bit lines, each of the third and the fourth selection transistors having a source region and a drain region located across the corresponding one of the pair of gate electrodes; a first wire formed with a metal wire of the first layer and arranged below the second bit line and the first sense-amplifier bit line, the first wire including a first end portion in which a first extension portion extends to a space below the third bit line and is connected to the third bit line, and a second end portion connected to one of the source and the drain regions of the third selection transistor; a second wire formed with a metal wire of the first layer and arranged below the third sense-amplifier bit line, the second wire including a first end portion in which a second extension portion is connected to the fourth bit line, and a second end portion connected to one of the source and drain regions of the fourth transistor; a third wire formed by use of a layer of the gate electrodes as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a metal wire of the first layer and arranged between the third wire and the second sense-amplifier bit line so as to connect the third wire to the second sense-amplifier bit line.