Patent ID: 7167407

Claim:
A dynamic semiconductor memory device comprising: a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs; a mode setting means to receive an externally-applied mode setting code and to generate a power saving mode control signal responsive to the mode setting code; and an address control means including: a refresh control signal generating means to generate a refresh control signal responsive to a refresh command and to extend a period of the refresh control signal and to reduce a pulse width of the refresh control signal responsive to the power saving mode control signal; a refresh address generating means to generate the refresh address responsive to the refresh control signal and to calculate the refresh address except the at least one predetermined bit responsive to the power saving mode control signal; a selection means to select and to output the externally-applied address or the refresh address responsive to the refresh command; and an address decoding means to decode an address output from the selection means to select one of the plurality of word lines during the normal mode operation, pre-charge the at least one predetermined bit of the address, decode all but the at least one predetermined bit of the address output from the selection means, and pre-charge at least one predetermined bit of the address to simultaneously select at least two word lines among the plurality of word lines in response to the power saving mode control signal.