Patent ID: 7005900

Claim:
A system comprising a clock doubler circuit, the clock doubler circuit comprising: an input clock terminal; an output clock terminal; a first counter circuit having a clock terminal coupled to the input clock terminal and a plurality of output terminals; a register having a plurality of data input terminals coupled to the output terminals of the first counter circuit, a clock terminal coupled to receive a clock update signal from the first counter circuit, and a plurality of output terminals; a set counter circuit having a clock terminal coupled to the input clock terminal, a plurality of data input terminals coupled to a first subset of the output terminals of the register, and an output terminal; a reset counter circuit having a clock terminal coupled to the output terminal of the set counter circuit, a plurality of data input terminals coupled to a second subset of the output terminals of the register, and an output terminal; and an output clock generator having a first input terminal coupled to the input clock terminal, a set input terminal coupled to the output terminal of the set counter circuit, a reset input terminal coupled to the output terminal of the reset counter circuit, and an output terminal coupled to the output clock terminal.