Patent ID: 8644073

Claim:
A non-volatile memory device comprising: a plurality of memory cells, each memory cell configured to store a bit having a first logic value or a second logic value; an input configured to receive a word defined by bits to be stored in said plurality of memory cells; programming circuitry configured to program a corresponding memory cell for each bit having the first logic value; and forming circuitry configured to receive the word from said input and to provide to said programming circuitry at least one additional word defined by bits to also be stored in said plurality of memory cells, said forming circuitry comprising a detector configured to periodically detect at least one operating parameter of the memory device, processing circuitry configured to calculate a current maximum number of simultaneously programmable bits based on a detected value of the at least one operating parameter and at least one characteristic parameter of the plurality of memory cells, and logic circuitry configured to generate the additional word, with the additional word having a number of bits having the first logic value equal to the current maximum number.