Patent ID: 7098104

Claim:
A method of fabricating a stacked-gate nonvolatile semiconductor memory device having a floating gate and a control gate, including the steps of: forming a tunnel insulating layer in a device forming region defined in a semiconductor substrate; forming an impurity-doped silicon layer on said tunnel insulating layer; forming a protective layer at a surface of said silicon layer; laminating a lower layer and an upper layer of a laminated mask layer on said protective layer in order; forming said upper layer into a desired pattern; forming a second upper layer on said pattern of said upper layer; etching said second upper layer and leaving said second upper layer only on a side surface of said first upper layer; etching said lower layer using said first and second upper layers as masks; forming a silicon pattern by etching said silicon layer using said lower layer as a mask; forming a second protective layer 121 covering a surface of said silicon pattern exposed; and etching out said lower layer.