Patent ID: 8751901

Claim:
A memory system comprising: a first memory; a second memory including a plurality of pages, each of the plurality of pages being a unit of data reading or data programming; error correcting circuitry configured to execute error correction processing for correcting data read out from the second memory; and controlling circuitry configured to: control data transfer between the first memory and the second memory, execute copy processing for writing the data in a second page of the second memory, after reading out data stored in a first page of the second memory to the first memory, determine whether the error correction processing for the data read out from the first page is successful, when executing the copy processing, store corrected data of the data read out from the first page in the first memory and write the corrected data in the second page, when the error correction processing is successful, and read out the data from the first page to the first memory and write the data not subjected to the error correction processing in the second page, when the error correction processing is unsuccessful.