Patent ID: 8136108

Claim:
An apparatus comprising: a memory; a second processor; a communications interface; a first processor configured to: receive an initiation request to update computer-readable instructions for the apparatus that are executable on a plurality of processors that include the first processor and the second processor; notify, through the communications interface, a host system about original computer program versions associated with the plurality of processors, wherein a first original computer program version is associated with the first processor and a second original computer program version is associated with the second processor; receive, through the communications interface, a first original set of computer-readable instructions and a first updated set of computer-readable instructions that are associated with the first processor and a second original set of computer-readable instructions and a second updated set of computer-readable instructions that are associated with the second processor; store the first original set, the first updated set, the second original set, and second updated set in the memory; initiate updating the first processor with the first updated set of computer-readable instructions from the memory; when the first processor does not successfully update, revert to the first original set of computer-readable instructions for the first processor; when the first processor has successfully updated with the first updated set of computer-readable instructions, initiate updating the second processor with the second updated set of computer-readable instructions from the memory; and when the second processor does not successfully update, revert to the second original set of computer-readable instructions for the second processor and to revert to the first original set of computer-readable instructions for the first processor.