Patent ID: 7652345

Claim:
A semiconductor device comprising: a substrate; a trench in a surface of the substrate, wherein the trench comprises first and second sub-trenches, wherein the first and second sub-trenches each comprise respective opposite side surfaces and a bottom surface, wherein the first sub-trench has a first width between respective side surfaces and wherein the second sub-trench has a second width between respective side surfaces that is greater than the first width; a trench oxide layer within the trench and having first and second sub-oxide layers, the first sub-oxide layer being positioned on side and bottom surfaces of the first sub-trench, and the second sub-oxide layer being positioned on side and bottom surfaces of the second sub-trench, and the first sub-oxide layer having a first thickness that is substantially uniform along the side and bottom surfaces of the first sub-trench, and the second sub-oxide layer having a second thickness that is substantially non-uniform along the bottom surface of the second sub-trench relative to the side surfaces of the second sub-trench and that is greater than the first thickness along the side surface of the second sub-trench; a liner layer on the trench oxide layer in the first and second sub-trenches; and an insulation pattern on the liner layer in the first and second sub-trenches.