Patent ID: 7428692

Claim:
A parallel precoder circuit that executes a differential encoding operation on n-row parallel input information series having 2-bit information series as one set, and outputs n-row parallel output information series, where n is an integer equal to or larger than 2, the parallel precoder circuit comprising: an nth-row delay circuit that delays an output set of a differential encoding operation circuit having a largest column number from among differential encoding operation circuits disposed in nth row; a zeroth-column differential encoding operation circuit that executes a differential encoding operation with an output set of the nth-row delay circuit as one input set and a first-row parallel input information series as other input set; a (2k)th-row first-column differential encoding operation circuit that executes a differential encoding operation with (2k)th-row parallel input information series as one input set, and an output set of the zeroth-column differential encoding operation circuit as other input set when k is 1, or (2k−1)th-row parallel input information series as the other input set when k is larger than 1, where k is an integer equal to or larger than 1 and equal to or smaller than n/2; (2k)th-row mth-column differential encoding operation circuit that executes a differential encoding operation with an output set of a (2k)th-row (m−1)th-column differential encoding operation circuit as one input set when 2k−2^(m−1) is equal to or larger than 1, and an output set of a (2k−2^(m−1))th-row (m−1)th-column differential encoding operation circuit as other input set when a differential encoding operation circuit is disposed in (2k−2^(m−1))th-row (m−1)th-column, or an output set of a differential encoding operation circuit having a largest column number from among differential encoding operation circuits disposed in (2k−2^(m−1))th row as the other input set when no differential encoding operation circuit is disposed in the (2k−2^(m−1))th-row (m−1)th-column, where m is an integer equal to or larger than 2 and equal to or smaller than h−1, and h is a smallest integer equal to or larger than (log 2 n)+1; and a (2k−1)th-row hth-column differential encoding operation circuit that executes a differential encoding operation with (2k−1)th-row parallel input information series as one input set, and an output set of a differential encoding operation circuit having a largest column number from among differential encoding operation circuits disposed in (2k−2)th row as other input set, wherein output sets of differential encoding operation circuits each of which having a largest column number from among differential encoding operation circuits disposed in first row to (n−1)th row become first-row to (n−1)th-row parallel outputs information series, respectively, and the output set of the nth-row delay circuit becomes nth-row parallel output information series.