Patent ID: 7119599

Claim:
A clock controlling circuit comprising: a first frequency dividing circuit for frequency dividing input clocks; a timing averaging circuit for receiving a first clock from a first position on a forward route of a clock propagation path at one end thereof fed with clocks frequency divided by said first frequency dividing circuit and a second clock from a second position on a return route thereof corresponding to said first position on said forward route, said timing averaging circuit outputting a signal of a delay time corresponding to a time obtained by dividing a timing difference of the first and second clocks in two equal portions, respectively; and a multiplication circuit for multiplying an output signal from said timing averaging circuit and outputting a multiplied output signal, wherein said timing averaging circuit comprises a plurality of switches, and wherein at least two of said plurality of switches have substantially equal on-currents, wherein said multiplication circuit comprises: a second frequency dividing circuit for frequency dividing said signal of a delay time from said timing averaging circuit to generate and output multi-phase clocks ; a period detection circuit for detecting a period of said signal of a delay time from said timing averaging circuit; and a multi-phase clock multiplication circuit fed with said multi-phase clocks output from said second frequency dividing circuit for generating multiplied multi-phase clocks.