Patent ID: 8234422

Claim:
An input/output interface for communicating between an application specific integrated circuit (ASIC) with a memory controller and a double data rate (DDR) memory device, the interface comprising: a strobe circuit comprising: a preamble logic element arranged to receive strobe signals from the DDR memory device and generate a preamble signal; a first counter arranged to receive the preamble signal and the strobe signals, the first counter generating a strobe count signal; a second counter arranged to receive a read enable signal and an ASIC-generated clock, the second counter generating a read count signal and a delayed version of the read enable signal; a strobe park circuit arranged to receive the preamble signal, the read count signal, the delayed version of the read enable signal and the strobe count signal, the strobe park circuit defining a strobe inactive state and strobe active states, each of the strobe inactive state and the strobe active states being valid for the duration of the preamble signal, the strobe park circuit transitioning from a second strobe active state to the strobe inactive state in response to a transition of the delayed version of the read enable signal and transitioning from a third strobe active state to the strobe inactive state in response to a transition of a function of the strobe count signal and the read count signal, the strobe park circuit tolerant of metastability issues in the read enable signal, the preamble signal and the function of the strobe count signal and the read count signal; and a first synchronizer arranged to receive the ASIC-generated clock and generate a synchronized count in response to a reset signal from the memory controller; and a data circuit comprising: a FIFO buffer arranged to receive a data input from the DDR memory device, the strobe signals, and the strobe count signal, the FIFO buffer generating a read data signal; and a second synchronizer arranged to receive the read data signal, the ASIC-generated clock, and the synchronized count, the second synchronizer generating a representation of the read data signal in synchronization with the ASIC-generated clock.