Patent ID: 7379855

Claim:
A method for selection of a simulation template, comprising: obtaining a wire length and an associated signal name; determining whether the wire length is for a signal originating from an embedded core in response to the associated signal name, the embedded core being a microprocessor, the embedded core having been designed separately from a host integrated circuit in which the embedded core is embedded; if the wire length is not for carrying the signal originating from the embedded core, selecting a wire line model for at least one conductive line associated with the wire length; selecting a driver in at least partial response to the associated signal name, the associated signal name having signal source information specifying driver type used; selecting the simulation template in response to the driver selected, the simulation template being one of a plurality of simulation templates, the simulation template being at the resistor-transistor level; iteratively repeating the selecting of the wire line model, the driver, and the simulation template for each of a plurality of drivers in a circuit; and simulating operation of the circuit using each said simulation template selected to generate timing information, wherein the circuit is gasket logic for coupling the embedded core to circuitry of the host integrated circuit.