Patent ID: 8836044

Claim:
An SRAM chip comprising: a plurality of SRAM cells, each SRAM cell comprising a plurality of low leakage NFETs and a plurality of PFETS; a plurality of logic NFETs; wherein each of the PFETs and each of the logic NFETs comprises a gate stack encapsulated by a nitride layer, wherein a plurality of nitride spacers are in direct physical contact with the gate stack of each of the logic NFETs, and wherein each of the low leakage NFETs comprise a gate stack encapsulated by an oxide layer, wherein no nitride spacers are in direct physical contact with the gate stack of each of the low leakage NFETs, each gate stack comprised of a high-K dielectric layer, and a metal layer, and wherein a Vt delta exists between the low leakage NFETs and the logic NFETs, wherein the low leakage NFETs have a threshold voltage that is larger than the threshold voltage of the logic NFETs.