Patent ID: 8759210

Claim:
A method comprising: providing a wafer; depositing a ball limiting metallurgy (BLM) layer over a surface of the wafer; depositing a first resist layer over the BLM layer; patterning the first resist layer to create a plurality of openings in the first resist layer; depositing a second resist layer over the first resist layer; patterning the second resist layer, wherein the patterning of the second resist layer includes removing the second resist layer from an upper surface of the first resist layer adjacent to a first opening having a first depth in the plurality of openings, and leaving the second resist layer on an upper surface of the first resist layer adjacent to a second opening having a second depth in the plurality of openings, wherein the first depth is shallower than the second depth; and electroplating a solder structure into each of the plurality of openings, wherein a first solder structure is plated into the first opening to a height above the upper surface of the first resist layer, and wherein a second solder structure is plated into the second opening such that it is confined by the second resist layer.