Patent ID: 8445883

Claim:
A method of manufacturing a nonvolatile semiconductor memory device comprising: a step (A) of forming a plurality of stripe-shaped lower copper wires on a substrate; a step (B1′) of forming an interlayer insulating layer over the substrate provided with the lower copper wires; a step (B2′) of forming a plurality of contact holes in the interlayer insulating layer such that the contact holes penetrate the interlayer insulating layer to surfaces of the lower copper wires, respectively; a step (B3′) of forming precious metal electrode layers comprising precious metal on the lower copper wires in bottom portions of the contact holes inside the contact holes, respectively, by electroless selective growth plating in which a metal layer is deposited only on a surface of each of the lower copper wires comprising electric conductors and is not deposited on a side wall of the interlayer insulating later comprising an insulator; a step (C) of filling resistance variable layers into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers inside the contact hole, respectively; and a step (D) of forming a plurality of stripe-shaped upper copper wires on the interlayer insulating layer and the resistance variable layers such that the upper copper wires are connected to the resistance variable layers, respectively, and cross the lower copper wires, respectively.