Patent ID: 8350594

Claim:
A method for designing a synchronous digital system comprising: accepting a specification of an asynchronous system, including accepting a specifications for each rule in a plurality of rules, the specification of each rule including a specification of a guard for determining when the rule may be applied, and a specification of an action that is performed as an atomic operation when the rule is applied; and processing the specification of the asynchronous system to form a corresponding specification of a synchronous digital system for operation according to a clock, including forming a specification of a scheduling circuit and specifications of circuits implementing a guard and action of each of the plurality of rules; wherein the plurality of rules includes at least some multi-cycle rules, and for each of the multi-cycle rules, the specification of the circuit implementing the multi-cycle rule includes a specification of a circuit implementing the action for the rule in a manner that may require multiple clock cycles to complete its action; and wherein the scheduling circuit includes logic for selecting rules to initiate according to guard values for the rules such that multiple multi-cycle rules may be active in one clock cycle.