Patent ID: 7313496

Claim:
A testing apparatus for performing a testing on a device under test (DUT) comprising: a performance board on which the DUT is mounted; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT on the basis of an output signal output by the DUT; a pin electronics which is provided between said main frame and said performance board and performs sending and receiving signals between said main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through said pin electronics and a comparator, and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through said pin electronics and a driver; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by said pin electronics or the loop signal output by said deterministic jitter injecting unit.