Patent ID: 7402482

Claim:
A method of making a transistor memory array with both read-only memory and rewriteable MOS or CMOS memory transistors, all having subsurface electrodes and channels comprising: providing a single mask set for forming a memory array of rows and columns of memory transistor sites, at least including masks for forming a subsurface active region, heavily doped first and second, spaced apart subsurface source and drain regions of a memory transistor and a select transistor respectively in the active region and defining channels therebetween; for a first set of memory transistor sites, providing a thin oxide layer over the channel of the memory transistor, a first polysilicon layer over the thin oxide layer and a second polysilicon layer spaced apart from and over the first polysilicon layer; for a second set of memory transistor sites, providing blocking mask portions extending the channel of the memory transistor to impede transistor conductivity, and blocking formation of the thin oxide layer and the first polysilicon layer, thereby forming read-only memory transistor cells that are open at the first set of sites; for a third set of memory transistor sites, increasing the source and drain regions of the memory transistor subsurface regions to an extent that the channel is shorted to establish permanent transistor conductivity at the second set of sites, the mask set further blocking formation of the thin oxide layer and the first polysilicon layer; and the subsurface active region having the same length for the first, second, and third sets of memory transistor sites.