Patent ID: 8099450

Claim:
Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit, said circuitry comprising a plurality of compression columns, each column receiving a plurality of unprocessed partial product term bits, at least one compression column comprising: a first circuit arranged to receive a first set of the plurality of unprocessed partial product term bits for the at least one compression column, the first circuit further arranged to combine the first set of the plurality of unprocessed partial product term bits to produce a first combined term bit set; and a second circuit arranged to receive a second set of the plurality of unprocessed partial product term bits for the at least one compression column and all of the first combined term bit set, wherein the second circuit is a clocked buffer arranged to output the second set of the plurality of unprocessed partial product term bits and all of the first combined term bit set to a pipeline retiming stage dependent on a clocked input.