Patent ID: 6930941

Claim:
A semiconductor memory device comprising: a sense amplifier group configured in a hierarchy to read out data from a memory cell; a complementary signal line group for connecting a sense amplifier of a lower hierarchy level of said sense amplifier group with a sense amplifier of a higher hierarchy level of said sense amplifier group and connecting the sense amplifier of the lower hierarchy level of said sense amplifier group with said memory cell; and a control circuit suppressing a drive of complementary signal lines of said complementary signal line group by the sense amplifier of lower hierarchy level, and rendering active the sense amplifier of higher hierarchy level before a potential difference between said complementary signal lines reaches a level of power supply voltage; wherein, when a sense amplifier of higher hierarchy level of said sense amplifier group is active, said active sense amplifier has no electrical interconnection with the complementary signal lines of said complementary signal line group for connecting said active sense amplifier with the sense amplifier of lower hierarchy level of said sense amplifier group or said memory cell.