Patent ID: 6937525

Claim:
A transistor comprising: a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other; a first insulation layer formed on a top of the projection; a pair of counter-conductivity type source/drain regions formed on a surface of said semiconductor substrate at opposite sides of the projection; second insulation layers each covering one of the pair of side walls of the projection and one of said pair of source/drain regions adjoining the side wall; a pair of floating gates respectively formed on the pair of side walls of the projection and facing said pair of side walls and said pair of source/drain regions via respective second insulation layers; third insulation layers each being formed on one of said pair of floating gates; and a control gate facing said pair of floating gates via said third insulation layers and facing the top of the projection via said first insulation layer; a potential difference for write-in being set up between said pair of source/drain regions while a write voltage is applied to said control gate, thereby causing a charge to be ballistically injected into at least one of said pair of floating gates.