Patent ID: 8103859

Claim:
An operation processing apparatus executing a store instruction for accessing a memory and a load instruction in random order when an execution in random order is available, the store instruction and the load instruction being included in a thread that is a sequence of instructions, the operation processing apparatus comprising: a first thread execution unit that executes a first thread including a store instruction; a second thread execution unit that executes a second thread including a first load instruction and a second load instruction that precedes the first load instruction; a cache memory that is shared by the first thread execution unit and the second thread execution unit; an instruction control unit controlling the first thread execution unit and the second thread execution unit; a determination unit that determines, when the first thread execution unit executes the store instruction to a target address of the cache memory, whether the second thread execution unit executes the first load instruction to the target address before the second load instruction and returns a target data of the first load instruction to the instruction control unit before the store instruction is executed; and an instruction re-execution request unit that requests the instruction control unit to re-execute instructions from a next instruction of the second load instruction by the second thread execution unit at a time when the second thread execution unit executes the second load instruction, when the determination unit determines that the second thread execution unit executes the first load instruction to the target address before the second load instruction and returns the target data of the first load instruction to the instruction control unit before the store instruction is executed.