Patent ID: 8466562

Claim:
A layered chip package comprising a plurality of layers that are stacked, wherein: at least one of the plurality of layers is a first-type layer and at least another one of the plurality of layers is a second-type layer; each of the first-type layer and the second-type layer includes a semiconductor chip; the semiconductor chip has a chip body including a circuit, a plurality of electrode pads electrically connected to the circuit, a plurality of through electrodes corresponding to the plurality of electrode pads, and an insulating film that insulates the plurality of through electrodes from the chip body; in every vertically adjacent two of the layers, the plurality of through electrodes of the semiconductor chip of one of the two layers are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layers; the first-type layer includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads; and the second-type layer includes no wires to electrically connect the plurality of through electrodes to the respective corresponding electrode pads, thereby the plurality of through electrodes are not connected to the circuit or to the corresponding electrode pads .