Patent ID: 8549255

Claim:
A processor configured to provide hardware initiated prefetching, the processor configured to perform: issuing a single prefetch instruction from millicode in the processor outside of a hardware prefetch engine, the issuing based on detection of a page crossing by the millicode; writing a prefetch address into a prefetch address register (PFAR); fetching to an end of page using the single prefetch instruction, by: a) attempting a prefetch according to the prefetch address; b) detecting one of a first level cache miss and a first level cache hit; c) sending a miss request to a next level cache and attempting cache access of the next level cache in a non-busy cycle, based on detecting a first level cache miss; d) incrementing the address in the PFAR and completing the prefetch, based on detecting a cache hit; and repeating a) thorough d) until the end of page is detected; wherein the sending of a miss request is based on determining that a miss resource is available, and prefetching is stopped using a stop instruction based on detecting one of an interrupt and an exception.