Patent ID: 8305788

Claim:
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines each connected to the plurality of memory cells arranged in rows; a plurality of bit line pairs each connected to the plurality of memory cells arranged in columns; a plurality of column selectors each provided for the corresponding bit line pair; a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs; a sense amplifier having an input terminal connected to the one common line, and the other input terminal connected to the other common line; and a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line, wherein the plurality of column selectors each comprise: a first switch element provided between the one of the corresponding bit line pair and the one common line; and a second switch element provided between the other of the corresponding bit line pair and the other common line, the plurality of capacitance adding circuits corresponding to the column selectors each comprise: a first capacitive element provided between the one of the corresponding bit line pair and the other common line; and a second capacitive element provided between the other of the corresponding bit line pair and the one common line.