Patent ID: 6998634

Claim:
A memory device using vertical nanotubes, comprising: an array of first electrodes arranged in strips in a first direction; a dielectric layer deposited on the array of first electrodes, the dielectric layer having a plurality of holes arranged therein; an array of nanotubes for emitting electrons, the array of nanotubes contacting the array of first electrodes and vertically growing through the plurality of holes in the dielectric layer; an array of second electrodes arranged in strips in a second direction on the dielectric layer, the array of second electrodes contacting the array of nanotubes, wherein the second direction is perpendicular to the first direction; a memory cell positioned on the array of second electrodes for trapping electrons emitted from the array of nanotubes; and a gate electrode deposited on an upper surface of the memory cell for forming an electric field around the array of nanotubes.