Patent ID: 7995412

Claim:
A memory device comprising: a memory array comprising a plurality of memory cells each storing an analog voltage; a plurality of reference memory cells that are part of the memory array and each storing a different reference voltage, wherein a first group of at least two reference memory cells of the plurality of reference memory cells are used to define an upper limit, wherein a second group of at least two reference memory cells of the plurality of reference memory cells are used to define a lower limit, wherein the second group uses different reference memory cells than the first group, and further wherein the plurality of reference memory cells are configured to track a temperature of the memory array such that a conversion window is different for different memory array temperatures; a buffer circuit to buffer the upper limit and the lower limit; and an analog-to-digital conversion circuit coupled to the memory array, wherein the analog-to-digital conversion circuit receives the buffered upper limit and buffered lower limit to define the conversion window.