Patent ID: 7410851

Claim:
A process for manufacturing a power semiconductor device, comprising: providing a semiconductor body of a first conductivity and first charge level; forming a plurality of spaced gate structures on said semiconductor body, each gate structure including at least a gate insulation body, and a gate electrode; implanting first dopants of a second conductivity into said semiconductor body through spaces between said gate structures; diffusing said first dopants of said second conductivity to form a plurality of channel regions; implanting dopants of said first conductivity into said channel regions through said spaces between said gate structures to form source implant regions; implanting second dopants of said second conductivity through said spaces between said gate structures to a depth below the depth of said channel regions; and diffusing said second dopants to form breakdown voltage enhancing regions having a second charge level; wherein said first charge level and said second charge level are such that said breakdown voltage enhancing regions and said semiconductor body deplete one another under application of a reverse voltage.