Patent ID: 7058832

Claim:
A state machine comprising: a memory storing a plurality of words representative of states of the state machine, each word having a plurality of bits, a word from the memory being supplied in response to a selection signal, the memory connected to receive a first clock signal; a first plurality of external input terminals for receiving information from an external circuit; a control circuit having a plurality of input terminals, at least some of which are coupled to the external input terminals to receive the information therefrom, the control/circuit supplying a first output signal; a selection circuit connected to receive the first output signal from the control circuit and in response provide the selection signal which when received selects one of the words in the memory and thereby causes selected interconnections in the memory to receive power; a clock circuit connected to receive the first output signal, the clock circuit disabling the first clock signal when the selection signal selecting one of the words in the memory selects the same word as in an immediately previous selection, the clock circuit thereby causing the selected interconnections in the memory to not receive power, and thereby reduce power consumption of the memory.