Patent ID: 7879645

Claim:
A method for manufacturing an array of memory cells, the method comprising: forming an array of bottom electrodes; forming a separation layer on the array of bottom electrodes, an isolation layer on the separation layer, and a sacrificial layer on the isolation layer; forming an array of openings overlying the array of bottom electrodes and extending into the separation layer, the forming an array of openings comprises forming lower opening segments within the isolation layer and forming upper opening segments within the sacrificial layer, the lower opening segments having widths greater than those of corresponding opening segments; forming etch masks within the array of openings, including depositing a fill material in the array of openings by a process causing formation of voids within the lower segments of the openings; and anisotropically etching the fill material to open the voids and expose the separation layer, thereby forming the etch masks comprising fill material within the openings; etching through the separation layer using the etch masks, thereby exposing upper surfaces of the corresponding bottom electrodes; removing the etch masks to define an array of vias within the separation layer, the vias having constricted parts extending to the upper surfaces of the corresponding bottom electrodes, and having enlarged parts on the constricted parts; forming memory elements within the vias, the memory elements having first memory element portions within the constricted parts and having second memory element portions within the enlarged parts, the memory elements comprising a memory material; and forming top electrodes on the memory elements.