Patent ID: 7880266

Claim:
An antifuse structure, comprising: a first conductor embedded within a semiconductor substrate comprising a semiconductor material, wherein said first conductor comprises a doped semiconductor material that includes said semiconductor material and at least one dopant, said first conductor having a planar upper surface throughout; a dielectric layer located directly on a top surface of said semiconductor substrate and having a planar top surface and a planar bottom surface throughout, wherein said planar upper surface of said first conductor contacts said planar bottom surface of said dielectric layer, wherein said first conductor is adapted to receive a first voltage potential (V 1 ) and a second voltage potential (V 2 ) and to heat said dielectric layer in response to V 1 and V 2 ; a second conductor located above said semiconductor substrate and separated from said first conductor by said dielectric layer and having a planar lower surface throughout, wherein said planar lower surface of said second conductor contacts said planar top surface of said dielectric layer, and the second conductor is adapted to receive a third voltage potential (V 3 ) and a fourth voltage potential (V 4 ) and to heat said dielectric layer in response to V 3 and V 4 ; a first contact structure that is in direct contact with a first portion of a surface of said second conductor and does not contact said dielectric layer and is configured to provide said third voltage potential (V 3 ); and a second contact structure that is in direct contact with a second portion of said surface of said second semiconductor and does not contact said dielectric layer and is configured to provide said fourth voltage potential (V 4 ), wherein said second conductor is a single contiguous structure that extends from said first portion of said surface of said second conductor to said second portion of said surface of said second conductor.