Patent ID: 6933547

Claim:
In an integrated circuit chip including a plurality of metal layers and first and second supply potentials, a memory cell circuit for modification of a default register value, the circuit comprising: a memory cell having a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein said first metal interconnect structure is coupled to one of said first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein said second metal interconnect structure is coupled to the other one of said first and second supply potentials, and an output, wherein a state of said output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers; a register having a data input, a data output and control inputs; and a control circuit coupled to said control inputs of said register, wherein said control circuit receives a chip reset signal and said memory cell output to thereby force said data output of said register to a default register value that equals said output of said memory cell, regardless of said data input of said register.