Patent ID: 7238619

Claim:
A via-first dual damascene process, comprising: providing a semiconductor substrate having a dielectric layer deposited over the semiconductor substrate, wherein the dielectric layer has a via opening; filling the via openings with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer; etching the GFP layer back to a predetermined depth to form a GFP plug in the via opening, wherein an exposed surface of the GFP plug is lower than a top surface of the dielectric layer, thereby forming a recess above the via opening; coating a photoresist layer over the dielectric layer, the photoresist layer filling the recess; performing a lithographic process to form a trench line pattern in the photoresist layer above the via opening, wherein the trench line pattern has a first section that has a substantially constant line width L and does not overlap with the via opening, and a second section that is directly above the via opening and has a tapered line width smaller than L, wherein the line width L is substantially equal to diameter of the via opening; and etching the dielectric layer and the GFP layer through the trench line pattern using the photoresist layer as an etching mask.