Patent ID: 7256443

Claim:
A semiconductor memory in which plural cell transistors are formed on a one conductive type semiconductor substrate and arranged in a column direction and a row direction perpendicular to the column direction to form a two-dimensional matrix, the cell transistor comprising: a first projection having a pair of side surfaces formed in the semiconductor substrate; a pair of opposite conductive type regions formed in both sides of the first projection in the semiconductor substrate, the opposite conductive type regions serving as the source and the drain of the cell transistor; a first insulation layer provided in the surfaces of the opposite conductive type regions and the side surfaces of the first projection; a pair of floating gates each of which is electrically isolated, the floating gate facing the opposite conductive type region via the first insulation layer and having a side surface facing the first projection via the first insulation layer; a second insulation layer formed on the floating gates; a control gate that faces the floating gate via the second insulation layer; a third insulation layer formed in the area in which the side surface of the floating gate is not covered with the first insulation layer, the side surface of the floating gate facing the control gate via the third insulation layer; and a fourth insulation layer provided between the first projection and the control gate.