Patent ID: 8847933

Claim:
A display device comprising: a plurality of pixels arranged in m rows and n columns (m and n are natural numbers greater than or equal to 4); respective first to m-th scan lines which are electrically connected to the n pixels arranged in respective first to m-th rows; respective first to m-th inverted scan lines which are electrically connected to the n pixels arranged in respective first to m-th rows; and a shift register electrically connected to the first to m-th scan lines and the first to m-th inverted scan lines, wherein the pixels arranged in the k-th row (k is a natural number less than or equal to m) each include: a first switch which is turned on by an input of a selection signal to the k-th scan line, and a second switch which is turned on by an input of a selection signal to the k-th inverted scan line, and wherein the shift register includes: first to m-th pulse output circuits, and first to m-th inverted pulse output circuits, wherein to the s-th (s is a natural number less than or equal to (m−2)) pulse output circuit, a start pulse is input (only in a case where s is 1) or a shift pulse output from the (s−1)-th pulse output circuit is input, and the s-th pulse output circuit outputs a selection signal to the s-th scan line and outputs a shift pulse to the (s+1)-th pulse output circuit, wherein the s-th pulse output circuit includes a first transistor and a second transistor which are turned on by an input of the start pulse or the shift pulse output from the (s−1)-th pulse output circuit and are in an on state until a first period ends, wherein in the first period, by using at least one of capacitive coupling between a gate and a source of the first transistor and capacitive coupling between a gate and a source of the second transistor, the s-th pulse output circuit supplies, as a selection signal, a potential which is the same or substantially the same as the potential supplied to a drain of the first transistor, from the source of the first transistor, and supplies, as a shift pulse, a potential which is the same or substantially the same as the potential supplied to a drain of the second transistor, from the source of the second transistor, wherein to the s-th inverted pulse output circuit, the start pulse (only in the case where s is 1) or the shift pulse output from the (s−1)-th pulse output circuit is input, and the s-th inverted pulse output circuit outputs a selection signal to the s-th inverted scan line, wherein the s-th inverted pulse output circuit includes a third transistor which is turned off by an input of the start pulse or the shift pulse output from the (s−1)-th pulse output circuit and is in an off state until a second period ends, wherein after the second period, the s-th inverted pulse output circuit supplies a selection signal to the s-th inverted scan line from a source of the third transistor, and wherein the first period corresponds to or is included in the second period.