Patent ID: 8570206

Claim:
A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a main digital-to-analog converter (DAC) coupled to receive at least one input, at least one output node of the main DAC generating an adjusted input; a comparing unit including a plurality of comparators coupled to receive the adjusted input; a SAR unit configured to generate a code for controlling the main DAC to generate the adjusted input based on a comparison output of the comparing unit; and a reference generator under control of the generated code for generating at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.