Patent ID: 8891289

Claim:
A 10-transistor dual-port SRAM with shared bit-line architecture, comprising: a first memory cell having a first storage unit, a first switch set, and a second switch set, the first switch set being connected to a first A-port bit line, a first B-port bit line, and the first storage unit, the second switch set being coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit; and a second memory cell having a second storage unit, a third switch set, and a fourth switch set, the third switch set being connected to the complement first A-port bit line, the complement first B-port bit line, and the second storage unit, the fourth switch set being coupled to a second A-port bit line and a second B-port bit line, and connected to the second storage unit, wherein the second memory cell makes use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.