Patent ID: 6933758

Claim:
A clock generation circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit for buffering the external clock signal to generate a reference clock signal; a delay monitor circuit for delaying the reference clock signal; a forward delay array for sequentially delaying an output clock signal of the delay monitor circuit in a forward direction to generate delayed clock signals; a mirror control circuit for detecting a clock signal synchronized with the reference clock signal among the delayed clock signals; a backward delay array for delaying the delayed clock signals detected by the mirror control circuit in a backward direction; a clock driver for receiving an output clock signal of the backward delay array to generate the internal clock signal; and a locking range control circuit for detecting whether one of the delayed clock signals of the forward delay array is synchronized with the reference clock signal, the locking range control circuit operating in response to at least one of the delayed clock signals, wherein the locking range control circuit selectively delays the reference clock signal to synchronize the internal clock signal with the reference clock signal.