Patent ID: 8493802

Claim:
A memory controller comprising: first circuitry to output: address information indicating a storage address for first write data; and a first timing signal to time reception of the address information within a first dynamic random access memory (DRAM), the first timing signal requiring a first propagation time to propagate from the memory controller to the first DRAM; second circuitry to output the first write data and a second timing signal to time reception of the first write data within the first DRAM, the second timing signal requiring a second propagation time to propagate from the memory controller to the first DRAM, the second circuitry including: a chain of delay elements to generate a plurality of delayed timing signals, and first select circuitry to select, as a transmission timing source of the second timing signal, a first one of the delayed timing signals, wherein the memory controller is operable in a calibration mode to enable the first select circuitry to select the first one of the delayed timing signals to time transmission of the second timing signal, wherein, during the calibration mode, the second circuitry outputs multiple delayed versions of the timing signals and selects, as the first one of the delayed timing signals, one of the delayed timing signals that compensates for mismatch between the first and second propagation times.