Patent ID: 7359264

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell array blocks including a plurality of column selecting signal lines and lower and upper blocks, each of the plurality of memory cell array blocks accessible in response to a block address, the plurality of column selecting signal lines selected in response to a column address, and each of the lower and upper blocks including a redundant column selecting signal line selected in response to a redundant column selecting signal and accessible in response to a lower and upper block address; a redundant enable signal generating circuit programming a defective block address, a defective lower and upper block address and a defective column address during a mode setting operation and generating a redundant enable signal when the defective block address, the defective lower and upper block address and the defective column address are applied during an operation; and a redundant decoder including a plurality of decoders for selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, the corresponding block address, and the lower and upper block address, wherein each of the plurality of decoders is electrically connected to one of the lower and upper blocks of the plurality of memory cell array blocks.