Patent ID: 7598563

Claim:
A memory device comprising: a semiconductor substrate having a first trench; a tunneling oxide layer at inner walls and a bottom surface of the first trench; a split gate including a floating gate, a dielectric layer and a control gate in sequence on lateral walls of the first trench, each of the floating gate, the dielectric layer and the control gate having an outermost sidewall contacting the tunneling oxide layer; buffer dielectric layers at sidewalls of the split gate, wherein each of the floating gate, the dielectric layer, and the control gate have an innermost sidewall in contact with the buffer dielectric layer; a source junction on the semiconductor substrate at a bottom surface of the first trench; a source electrode filling a second trench in a central portion of the first trench, electrically connected to the source junction; and a drain junction in the semiconductor substrate outside the first trench.