Patent ID: 7904857

Claim:
A method of receiving scan constraints from an external source that includes a list of scan clocks for generating an optimal number of scan clocks for testing an integrated circuit modeled at RTL, the integrated circuit having a plurality of clock domains and each domain having one of said scan clocks; said method comprising the steps of: (a) compiling, using a computer, the HDL (hardware description language) code that represents said integrated circuit at RTL into a design database; (b) the computer receiving said scan constraints from said external source that includes said list of scan clocks; and (c) based on said scan constraints, the computer analyzing said design database for generating said optimal number of scan clocks by identifying which selected clock domains do not interact with each other, and when said selected clock domains do not interact with each other, selectively replacing said scan clocks controlling said selected clock domains with one or more grouped scan clocks each for testing a plurality of said selected clock domains at the same frequency concurrently.