Patent ID: 7827336

Claim:
An information processing system, comprising: a first integrated circuit die comprising: a first system interconnect, the first system interconnect including a first plurality of master ports and a first plurality of slave ports, the first system interconnect operable as per a first system interconnect protocol; a first processor core communicatively coupled to a first master port of the first plurality of master ports; a memory communicatively coupled to a first slave port of the first plurality of slave ports; and a first slave circuit communicatively coupled to a second slave port of the first plurality of slave ports; and a second integrated circuit die, the second integrated circuit die comprising: a second system interconnect, the second system interconnect including a second plurality of master ports and a second plurality of slave ports, the second system interconnect operable as per the first system interconnect protocol; a second processor core communicatively coupled to a first master port of the second plurality of master ports; an addressable slave circuit communicatively coupled to a first slave port of the second plurality of slave ports, the addressable slave circuit having an addressable range of addresses, the addressable range of addresses corresponding to a first address range within an address map of the first integrated circuit die, the addressable range of addresses corresponding to a second address range within an address map of the second integrated circuit die; and a first master circuit communicatively coupled to a second master port of the second plurality of master ports; wherein the first slave circuit is communicatively coupled to the first master circuit for providing data during a data access to the addressable slave circuit by a system interconnect master of the first integrated circuit die via the first system interconnect and the second system interconnect.