Patent ID: 7235824

Claim:
A device comprising: a substrate of a first conductivity type; a channel of a second conductivity type formed in the substrate; a first gate region of the first conductivity type formed in a corresponding first portion of the channel, the first gate region covering a first area; a first contact connected to the first gate region, the first contact covering a fraction of the first area; a second gate region of the first conductivity type formed in a corresponding second portion of the channel, the second gate region covering a second area and being spaced by a first gap from the first gate region; a second contact connected to the second gate region, the second contact covering a fraction of the second area; a first gate electrode insulatively spaced from and disposed over the first gap, the first gate electrode being spaced from and overlaying an edge of the first gate region and an edge of the second gate region; a first clock line coupled to the first contact; a second clock line coupled to the first gate electrode; and a third clock line coupled to the second contact.