Patent ID: 8338314

Claim:
A method, comprising: forming a layer stack above first and second conductive lines formed in a device level of a semiconductor device, wherein forming said layer stack comprises forming a first stress-inducing dielectric layer above said first and second conductive lines, performing a surface treatment to introduce an etch indicator species into a surface portion of said first stress-inducing dielectric layer, and thereafter forming an etch stop layer above said first stress-inducing dielectric layer; forming a mask so as to expose said second conductive lines and cover said first conductive lines; performing an etch sequence adapted for removing an exposed portion of said layer stack from above said second conductive lines, wherein performing said etch sequence comprises: performing a first etch process to remove a first portion of said etch stop layer and a first thickness portion of said first stress-inducing dielectric layer; performing a second etch process to substantially completely remove a remaining portion of said etch stop layer and to remove a second thickness portion of said first stress-inducing dielectric layer; and performing a third etch process to substantially completely remove a remaining thickness portion of said first stress-inducing dielectric layer; forming a second stress-inducing dielectric layer above said second conductive lines and on a portion of said etch stop layer located above said first conductive lines; and selectively removing said second stress-inducing dielectric layer from above said first conductive lines.