Patent ID: 8493255

Claim:
An apparatus comprising: a negative voltage rail; a positive voltage rail; a plurality of multiplexer cells, wherein each multiplexer cell is controlled by at least one of a plurality of select signals, and wherein each multiplexer cell is deactivated when a control signal is deasserted, and wherein each multiplexer cell includes: an input terminal; an output terminal; a switch network that is coupled to the negative voltage rail; and a boosted switch that is coupled to the input terminal, the output terminal, and the switch network; and a boost circuit that is coupled to the output terminal of each of the multiplexer cells, the switch network of each multiplexer cell, and the positive voltage rail, wherein the boost circuit is controlled by the control signal, wherein the boost circuit further comprises: a first switch that is coupled to the positive voltage rail and to the switch network of each multiplexer cell, wherein the first switch is activated when the control signal is asserted; a second switch that is coupled to the ground and to the output terminal of each multiplexer cell, wherein the second switch is activated when the control signal is asserted; and a capacitor that is coupled between the first and second switches, and wherein each boosted switch further comprises an NMOS transistor that is coupled to the input terminal at the source, the output terminal at the drain, and the switch network at the gate, wherein each switch network further comprises: a third switch that is coupled to the source of the NMOS transistor; a fourth switch that is coupled to between the third switch and the output terminal; a fifth switch that is coupled to a node between the third and fourth switches and to ground; a sixth switch that is coupled between the negative voltage rail and the gate of the NMOS transistor; and a seventh switch that is coupled to between the first switch and the gate of the NMOS transistor.