Patent ID: 7160783

Claim:
A method of manufacturing a MOS transistor, comprising: subsequently forming a gate insulating layer and a gate conductive layer on a semiconductor substrate having a first conductivity type where an active region is defined by an isolation layer; implanting first impurities of the first conductivity type within the active region of the substrate by performing a first ion implanting process; forming a gate and a gate insulating layer pattern on the active region of the substrate by patterning the gate insulating layer and the gate conductive layer; implanting second impurities of a second conductivity type within the substrate at both sides of the gate by performing a second ion implanting process; implanting third impurities of the first conductivity type within the substrate under the edge of the gate by performing a third ion implanting process; forming a spacer on side walls at the gate; forming a first punch-through suppression region containing the first impurities, source/drain extension regions containing the second impurities, and a second punch-through suppression region containing the third impurities by performing a first thermal treatment process; implanting fourth impurities of the second conductivity type within the substrate at both sides at the spacer by performing a fourth ion implanting process; and forming source/drain regions containing the fourth impurities by performing a second thermal treatment process.