Patent ID: 7525850

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array including a plurality of nonvolatile memory cells, a bit line, and a word line; a page buffer electrically connected to the bit line and including a main data latch and a sub-data latch, the page buffer configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch; and a row decoder driven to control a word line of the memory array, wherein the page buffer comprises, a main latch block which drives the main data latch and which maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line, a sub-latch block which drives the sub-data latch, wherein the sub-data latch is flipped depending on the voltage level of the bit line, and a latch control block which selectively flips the main data latch depending on the voltage level of the bit line, wherein the latch control block is disabled depending on a logic state of the sub-data latch.