Patent ID: 8750056

Claim:
A semiconductor device for operating both in a high speed mode and in a low speed mode, the semiconductor device comprising: a memory cell array comprising a plurality of memory cells; a sense amplifier circuit connected to the memory cell array via a plurality of bit line pairs and including a plurality of sense amplifiers; a driving circuit connected to the memory cell array via word lines, the driving circuit comprising: a word line driver configured to generate a word line signal to drive the word lines; a sense amplifier driver configured to generate a sense amplifier enable signal to drive the plurality of sense amplifiers; and a clock signal delay circuit configured to generate a delayed clock signal by delaying a clock signal and to provide the delayed clock signal to the sense amplifier driver; and a data input/output circuit configured to receive data from the sense amplifier circuit and to output the data to an external device, wherein, in the high speed mode, the sense amplifier driver is configured to generate the sense amplifier enable signal in response to an edge of the delayed clock signal, wherein, in the low speed mode, the sense amplifier driver is configured to generate the sense amplifier enable signal in response to a first edge of the clock signal, wherein, in the high speed mode, the word line signal is generated in response to a second edge of the clock signal, and wherein, in the low speed mode, the word line signal shifts to a high level in response to the second edge of the clock signal and shifts to a low level in response to the first edge of the clock signal.