Patent ID: 8903092

Claim:
A system comprising: a first circuit comprising a demultiplexer that outputs N digital data streams in parallel, and a scrambling module that receives the N digital data streams in parallel and that scrambles the N digital data streams using a scrambling sequence; a data bus that receives the N scrambled digital data streams and the scrambling sequence; and a second circuit that communicates with the data bus and that comprises: a first processing module that includes a multiplexer to process the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one, and where M is different than N; one or more descrambling and processing modules that receive the M digital data streams, that further process the M digital data streams, and that descramble the M digital data streams based on the scrambling sequence received via the data bus; and a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.