Patent ID: 7477561

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells, each memory cell being of a static type and configured by metal insulator semiconductor (MIS) transistors; a plurality of word lines which select the memory cells; a plurality of bit lines which transfer data of the memory cells; a sense amplifier circuit which amplifies data transferred to the bit lines; a first dummy cell group including a plurality of first dummy cells, each first dummy cell being configured by MIS transistors and having data fixed therein; a dummy word line which selects the first dummy cell group; a dummy bit line to which data of the first dummy cell group is transferred; a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line; and a potential generating circuit which generates a first source potential applied to the first dummy cell group, wherein a power supply potential is applied to the memory cells; and the first source potential is lower than the power supply potential, and the first source potential is not a ground potential.