Patent ID: 8094511

Claim:
A non-volatile memory device comprising: an interface circuit for receiving a plurality of signals, including address signals and command signals; an input buffer for storing said plurality of signals received; a command circuit for receiving the output of said input buffer, and for controlling said device in response to the command signals received; a plurality of address registers for receiving the output of said input buffer for storing a plurality of address signals therefrom; a data buffer circuit for receiving the output of said input buffer for storing the data signals therefrom; an array of non-volatile memory cells, said array having a plurality of sub-arrays each of said sub-array being independently addressable; said array of non-volatile memory cells for storing data and for providing data in response to the plurality of address signals from the plurality of address registers; and wherein said command circuit for controlling the addressing of said array of non-volatile memory cells and for providing a plurality of continuous data in response to the plurality of address signals from the plurality of address registers.