Patent ID: 7817481

Claim:
A static random access memory decoder circuit comprising: a first cell supply line coupled to a first column of memory cells; a second cell supply line coupled to a second column column of memory cells; a write assist circuit including a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line, wherein the first threshold transistor has a first threshold voltage level and the second threshold transistor has a second threshold voltage level, wherein in response to a write assist signal, the write assist circuit connects a selected one of the first and second cell supply lines to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the associated one of the first and second threshold transistors; and control circuitry that selects the selected one of the first and second cell supply lines.