Patent ID: 8773942

Claim:
Apparatus having a memory array comprising a plurality of segments, a segment comprising: one or more rows of memory cells, each row comprising two or more memory cells and a wordline interconnecting the memory cells of the row; and control circuitry configured to selectively enable and disable access to all of the segment and selectively enable and disable access to any individual row of the segment, wherein: the control circuitry is configured to generate (i) a segment-enable control signal that controls access to all of the segment and (ii) a segment-level wordline-enable control signal that controls whether a wordline signal can be applied to the wordline of a row to be accessed, wherein (a) the wordline-enable control signal is distinct from the wordline signal and (b) the control circuitry is configured to gate the wordline-enable control signal with each wordline signal in a segment to control whether any wordline signal can be applied to a corresponding wordline of a row in the segment, such that: when access to a row in the segment is to be initiated, the control circuitry generates the segment-enable control signal and the wordline-enable control signal to enables access to all of the segment before enabling access to the row and before the wordline signal can be applied to the wordline; and when access to the row in the segment is to be terminated, the control circuitry generates the segment-enable control signal and the wordline-enable control signal to disables access to the row and to disable the wordline signal from being applied to the wordline before disabling access to all of the segment.