Patent ID: 6943089

Claim:
A semiconductor device manufacturing method, comprising: forming crystal nuclei to be nuclei of a Hemispherical Grained Silicon (HSG) layer only on an amorphous silicon layer, out of the amorphous silicon layer for a capacitor electrode and a silicon-based dielectric layer, which are formed on a surface of a substrate, by supplying a monosilane (SiH 4 ) in reaction chamber where the substrate is received; and forming the HSG layer only on the amorphous silicon layer by growing the crystal nuclei, and wherein when the crystal nuclei is formed, pressure in the reaction chamber is set to be in a range of 0.5 Pa or less, and also a temperature (° C.) of the substrate and a supplying flow rate (sccm) of the monosilane are set within a prescribed range, and wherein the prescribed range is bounded by an area surrounded by three straight lines listed below on rectangular coordinates defined by orthogonal X-axis and Y-axis where the temperature (° C.) of the substrate is represented along the X-axis and the supplying flow rate (sccm) of monosilane is represented along the Y-axis: X=600° C. Y=25 sccm Y=10X+6,300.