Patent ID: 7408812

Claim:
An electronic memory cell comprising: a PMOS select transistor configured to be coupled to a bit line and to control an operation of the memory cell, the PMOS select transistor having first drain and first source p-type dopant regions in an n-well within an uppermost side of a semiconductor substrate, and essentially zero voltage drop between the first drain region and the first source region when activated; a memory cell transistor having second drain and second source dopant regions in the uppermost side of the semiconductor substrate, and being configured for the second drain region to be coupled to the first drain region by a conductive interconnect structure above the uppermost side of the semiconductor substrate, the memory cell transistor further being configured to be coupled to a word line and to be programmable with a voltage about equal to a voltage on the bit line; and a shallow trench isolation region in the uppermost side of the semiconductor substrate separating the first and second drain regions.