Patent ID: 7263002

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of memory transistors each of which has nonvolatile storage capability by being turned on or off upon being selected; a main bit line; a plurality of sub-bit lines provided correspondingly to said main bit line, wherein for each column, one side electrodes of said plurality of memory transistors are connected to one of said plurality of sub-bit lines, and during a read period, one selected sub-bit line among said plurality of sub-bit lines and said main bit line are electrically connected and precharged to a predetermined potential, and then one memory transistor among said plurality of memory transistors having said one side electrode connected to said selected sub-bit line enters a selected state, whereby read data is obtained based on the amount of current flowing thorough said main bit line, said nonvolatile semiconductor memory device further comprising: resetting means resetting said main bit line and said selected sub-bit line to a standard potential after said read data is obtained during said read period, wherein said resetting means includes: main bit line resetting means resetting said main bit line to said standard potential; and sub-bit line resetting means resetting said plurality of sub-bit lines to said standard potential.