Patent ID: 7370138

Claim:
A mobile communication terminal with a NAND flash memory, comprising: a memory for storing address information indicative of a start address of a specific area including boot data to be read from the NAND flash memory; a sub-controller for determining whether a predetermined block including the boot data of the NAND flash memory is incapable of being booted, requesting transmission of the address information from a main controller when the predetermined block is incapable of being booted, and reading the boot data from the predetermined block of the NAND flash memory corresponding to the address information transmitted from the main controller, wherein the sub-controller includes a first internal buffer for temporarily storing the address information transmitted from the main controller, and a controller for determining whether the predetermined block including the boot data of the NAND flash memory is incapable of being booted, requesting transmission of the address information from a main controller when the predetermined block is incapable of being booted, receiving the requested address information from the first internal buffer, and reading the boot data from the predetermined block of the NAND flash memory corresponding to the address information, and wherein the controller includes a boot H/W (Hardware) logic including a first comparator, which compares predetermined data read from the predetermined block with prestored data of the sub-controller for determining whether the predetermined block storing the boot data of the NAND flash memory is the block incapable of being booted, and reading the boot data from the predetermined block of the NAND flash memory corresponding to the address information transmitted from the first internal buffer, a first register for temporarily storing the comparison result value of the first comparator, a second register for receiving the address information from the first internal buffer, and temporarily storing the received address information, and a second internal buffer for temporarily storing the boot data read by the boot H/W logic; and a second internal buffer for temporarily storing the boot data read by the boot H/W logic; and the main controller for detecting the address information stored in the memory upon receiving the transmission request of the address information from the sub-controller, and transmitting the detected address information to the sub-controller.