Patent ID: 7428687

Claim:
A processor-based system, comprising: a processor; a memory module comprising: at least one dynamic random access memory device having a plurality of memory cells arranged in rows and columns; a non-volatile memory storing fault addresses identifying the respective locations of memory cells in the at least one dynamic random access memory device that may have reduced data retention capabilities; and a memory controller coupled to the processor and to the memory module, the memory controller comprising: a storage device; an identifying circuit operable to generate a respective refresh address corresponding to each row of memory cells currently being refreshed in the at least one dynamic random access memory device; a control circuit operable to transfer to the storage device the fault addresses stored in the non-volatile memory; a comparator circuit operable to compare each refresh address to the fault addresses stored in the storage device, the comparator circuit being operable to generate a match indication if a predetermined characteristic of the refresh address matches a predetermined characteristic of any of the fault addresses stored in the storage device; and a controller operable responsive to the match indication to apply to the memory module an address corresponding to the fault address having the predetermined characteristic that matches the predetermined characteristic of the refresh address to cause the dynamic random access memory device to refresh a row of memory cells corresponding to the address applied to the memory module by the controller.