Patent ID: 8884283

Claim:
A semiconductor device comprising: a semiconductor layer comprising a channel formation region; a source electrode and a drain electrode over the semiconductor layer and electrically connected to the channel formation region; a gate electrode over the channel formation region; a gate insulating layer between the semiconductor layer and the gate electrode; and an electrode over the gate insulating layer, the electrode overlapping with the source electrode or the drain electrode with the gate insulating layer interposed therebetween, wherein an upper surface of the source electrode and an upper surface of the drain electrode are covered with the gate insulating layer, wherein the source electrode and the drain electrode comprise at least one of a metal, a metal oxide and a metal nitride, wherein a side surface of the semiconductor layer is in contact with the source electrode and the drain electrode, and wherein a portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other.