Patent ID: 8829963

Claim:
A flip-flop circuit comprising: a multiplexer configured to receive a first data bit (D 1 ), a scan data bit (SD), a scan enable control signal (SE) and a binary logical compliment signal (SEN) of the scan enable control signal (SE), wherein the scan enable control signals (SE) and (SEN) determine whether the data output (MXO) of the multiplexer is the binary compliment of data bit (D 1 ) or the binary compliment of scan data bit (SD); a master latch configured to receive the data output (MXO) of the multiplexer, a clock signal (CKT), a binary logical compliment signal (CLKZ) of the clock signal (CKT), a retain control signal (RET), the binary logical compliment signal (RETN) of the retain control signal (RET) and a preset signal (PREN), wherein signals (CKT), (CLKZ), (RET), (RETN), (RE) and (PREN) determine when the binary logical value of the data output (MXO) is presented on the output (MLO) of the master latch and when the output (MLO) of the master latch is latched in the mater latch; a transfer gate wherein the transfer gate transfers data from the output (MLO) of the master latch to the output of the transfer gate when the clock signal (CKT) transitions from a high logical value to a logical low value; wherein the transfer gate transfers data from the output (MLO) of the master latch to the output of the transfer gate when signal PREN transitions from an logical one to a logical zero; wherein the transfer gate transfers data from the output (MLO) of the master latch to the output of the transfer gate when signal RE transitions from an logical zero to a logical one; a slave latch configured to receive the output of the transfer gate, a second data bit (D 2 ), the clock signal (CKT), the binary logical compliment signal (CLKZ) of the clock signal (CKT), the retain control signal (RET), the binary logical compliment signal (RETN) of the retain control signal (RET), a slave control signal (SS) and the binary logical compliment signal (SSN) of the slave control signal (SS) wherein signals (CKT), (CLKZ), (RET), (RETN), (SS) and (SSN) determine whether the output of the transfer gate or the second data bit (D 2 ) is latched in the slave latch; wherein the output of the transfer gate is (QN).