Patent ID: 8495271

Claim:
A data processing system, comprising: a processor core; a system memory coupled to the processor core; an input/output (I/O) subsystem including: a plurality of partitionable endpoints (PEs), wherein each of the plurality of PEs includes one or more requesters each assigned a respective one of a plurality of requester identifiers (RIDs), and wherein at least one of the plurality of PEs includes an I/O adapter (IOA); and an input/output (I/O) host bridge, coupled to the processor core and to the I/O subsystem, wherein the I/O host bridge includes: a register that receives I/O messages from the processor core, wherein the I/O messages received from the processor core include interrupt messages; a buffer that receives I/O messages from the IOA, wherein the I/O messages from the processor core and the I/O messages from the IOA each specifies one of the plurality of RIDs assigned within the I/O subsystem and a message body specifying one of a plurality of different I/O message types; and logic coupled to the register and to the buffer that services a stream of I/O messages formed of I/O messages received from the register and from the buffer, wherein the stream of I/O messages serviced by the logic includes the interrupt messages received from the processor core, and wherein one of the interrupt messages received from the processor core was previously received by the I/O host bridge from the I/O subsystem and passed to the processor core.