Patent ID: 7953932

Claim:
A processor in a multi-processor shared data environment having a cache memory structure involving various ownership states as to a cache line, which state includes a read-only or shared state and an exclusive state for holding the line exclusively, with such processor comprising: a local cache adapted for communication with one or more shared higher level caches for sourcing cache lines; a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored; and a mechanism for performing a method comprising: setting the processor into a slow mode to fetch, decode and execute a single instruction at a time; receiving a current instruction that includes a data store of data to one or more target lines; executing the current instruction, the executing including storing the data into the temporary buffer; preventing the store queue from rejecting an exclusive XI corresponding to the target lines of the current instruction; and acquiring each of the target lines with a status of exclusive ownership and writing contents from the temporary buffer to each target line after instruction completion.