Patent ID: 8775717

Claim:
A flash memory controller for controlling a flash memory, comprising: a plurality of processors each with a register, an ALU and an internal memory, the plurality of processors including: a first set of processors; and a second set of processors; a plurality of random access memories, including: a first set of random access memories in the plurality of random access memories including one or more data structures related to memory commands; and a second set of random access memories in the plurality of random access memories each including a work queue for a corresponding processor of the plurality of processors; a crossbar switch connecting the plurality of processors with the plurality of random access memories, the crossbar switch including: a set of processor ports including one port for a respective processor and a set of memory ports including one port for a respective random access memory; and an internal switching mechanism configured to connect any processor port with any memory port, but not configured to connect a processor port with another processor port or a memory port with another memory port; wherein a processor in the first set of processors is configured to place a task for a processor in the second set of processors through the crossbar switch on a work queue associated with the processor in the second set of processors, the task placed on the work queue comprises a pointer to a data structure in the first set of random access memories.