Patent ID: 8000157

Claim:
A RAM macro having a storing circuit and a controlling circuit accessing the storing circuit, comprising: a timing generating circuit for outputting a first control clock generated from a rising edge of an externally input clock, and a second control clock generated from a falling edge of the externally input clock; and a testing circuit, which is a circuit for outputting to the controlling circuit various types of control signals for determining various types of timings of accesses made by the controlling circuit to/from the storing circuit, and to which the first and the second control clocks are input and an evaluation mode selection signal is externally input, for determining operation timings of the various types of control signals based on any one of the first and the second control clocks according to the evaluation mode selection signal, wherein an operation timing of a control signal synchronous with the first control clock does not depend on a frequency of the externally input clock, and an operation timing of a control signal synchronous with the second control clock depends on the frequency of the externally input clock.