Patent ID: 8669607

Claim:
An apparatus, comprising: a semiconductor substrate having a source region formed in the semiconductor substrate and having a drain region formed in the semiconductor substrate, spaced from the source region; a floating gate region formed over the semiconductor substrate and disposed between the source region and the drain region, the floating gate having a source side sidewall and an upper surface; a control gate formed over a portion of the floating gate, the control gate having a source side sidewall adjacent the source region in the semiconductor substrate and a drain side sidewall adjacent the drain region, a portion of the upper surface of the floating gate adjacent the source region and the drain region not covered by the control gate, the source side sidewall of the control gate having a source side sidewall spacer of a first thickness and the drain side sidewall of the control gate having a drain side sidewall spacer of a second thickness greater than the first thickness, the drain side sidewall spacer comprising an L-shaped liner over the floating gate, the source sidewall spacer having no L-shaped liners, the source side sidewall spacer and the drain side sidewall spacer of the control gate being asymmetric with respect to one another; an inter-poly dielectric over the source side sidewalls and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region.