Patent ID: 8049286

Claim:
A semiconductor device comprising: semiconductor substrate with an element formation region projecting from a base portion of said substrate and extending in a first direction along said base portion; element isolation regions buried in said semiconductor substrate such that said element formation region of said semiconductor substrate is flanked by said element isolation regions, said element isolation regions having upper surfaces; a gate electrode on said element formation region with a gate insulating film interposed between said gate electrode and said element formation region, said gate electrode crossing said element formation region in a second direction; and source-drain regions formed in said element formation region on both sides of said gate electrode, wherein, said element formation region includes a channel region under said gate electrode, said source-drain regions are positioned within said element formation region so as to extend below said upper surfaces of said element isolation regions, said element isolation regions include depressions in said upper surfaces which extend in said second direction and which flank said channel region, said gate electrode extends into said depressions in said upper surfaces of said element isolation regions and has an upper surface positioned above bottom surfaces of said depressions, and said channel region has an upper surface positioned above said bottom surfaces of said depressions.