Patent ID: 6987032

Claim:
A process for manufacturing an integrated circuit package comprising: mounting a semiconductor die to a first surface of a substrate; mounting a die adapter to said semiconductor die; wire bonding said semiconductor die to ones of conductive traces at said first surface of said substrate; mounting at least one collapsible spacer to at least one of a heat spreader, said die adapter and said substrate; placing one of said heat spreader and said substrate on a surface of a lower mold die; releasably clamping the other of said heat spreader and said substrate to an upper mold die of said mold cavity, such that said other of said heat spreader and said substrate is in contact with said upper mold die and said collapsible spacer is disposed and compressed between said heat spreader and said substrate to thereby press said one of said heat spreader and said substrate against said surface of said lower mold die; molding the semiconductor die, the substrate, the wire bonds, said die adapter, said at least one collapsible spacer and said heat spreader into a molding compound by molding in a mold cavity between said heat spreader and said substrate, resulting in a molded package having said at least a portion of said substrate exposed and at least a portion of said heat spreader exposed from said molded package prior to singulating; forming a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces; and singulating said integrated circuit package.