Patent ID: 8391282

Claim:
A switching network comprising: an array of switching elements, said array of switching elements comprising R rows and C columns, wherein each switching element belongs to a row and a column; a first plurality of interconnection networks wherein each interconnection network in the first plurality of interconnection networks connects switching elements in adjacent rows belonging to the array of switching elements and each interconnection network in the first plurality of interconnection networks has a topology matching a topology of an interstage interconnection network within a first multistage interconnection network architecture; and a second plurality of interconnection networks wherein each interconnection network in the second plurality of interconnection networks connects switching elements in adjacent columns belonging to the array of switching elements and each interconnection network in the second plurality of interconnection networks has a topology matching a topology of an interstage interconnection network within a second multistage interconnection network architecture, wherein R and C are positive integers and the first plurality of interconnection networks and the second plurality of interconnection networks route traffic through the switching network to reduce overall latency.