Patent ID: 7345506

Claim:
A method of implementing redundancy on a programmable logic device having a plurality of programmable resources arranged in rows and interconnected by first wire channels running perpendicular to the rows and second wire channels running perpendicular to the first wire channels, each first wire channel including a plurality of wire segments driven by a buffer, each of the wire segments spanning one or more of the rows and stitch-able to a next wire segment in the same first wire channel using a programmable stitching element, the method comprising: determining if a first wire segment of a first wire channel requires a programmed connection to a resource in the row furthest from the buffer driving the first wire segment and spanned by the first wire segment; reserving a next segment in the first channel if the first wire segment of the first wire channel requires a programmed connection to a resource in the row furthest from the buffer driving the first wire segment and spanned by the first wire segment; and assuming a maximum delay path including the programmable signal propagation delay of the reserved next segment and a stitching element coupled between the first segment and the reserved next segment of the first channel.