Patent ID: 7589571

Claim:
A capacitor coupled floating gate drive circuit comprising, a digital voltage source having two discrete operating voltage states separated by a substantially fixed dc voltage difference, a capacitor directly connected in series with said digital voltage source, a digital logic and drive circuit responsive to said digital voltage source, having at least an input terminal coupleable to said capacitor, a first output terminal, a second output terminal coupleable to a gate terminal of a mosfet, a first supply voltage terminal, and a reference terminal coupleable to a source terminal of said mosfet, wherein a voltage signal appearing at said first output terminal is substantially in synchronization with a voltage applied at said input terminal and a voltage signal appearing at said second output terminal is substantially in anti-synchronization to said voltage applied at said input terminal, a first resistor having two terminals with said first terminal of said first resistor coupled to said first output of said digital logic and drive circuit and said second terminal of said first resistor coupled to said capacitor, wherein said first resistor provides positive current feedback to said input terminal of said digital logic and drive circuit from said first output terminal of said digital logic and drive circuit, a first clamp diode having an anode terminal and a cathode terminal with said anode terminal of said first clamp diode directly connected to said input terminal of said digital logic and drive circuit and said cathode terminal of said first clamp diode directly connected to said first supply voltage terminal of said digital logic and drive circuit, a second clamp diode having an anode terminal and a cathode terminal with said cathode terminal of said second clamp diode directly connected to said input terminal of said digital logic and drive circuit and said anode terminal of said second clamp diode directly connected to said reference terminal of said digital logic and drive circuit, whereby said first resistor provides positive current feedback for reducing the responsiveness of said digital logic and drive circuit to charging or discharging currents of said capacitor, thereby preventing a change in logic state of said digital logic and drive circuit not commanded by said digital voltage source.