Patent ID: 7349246

Claim:
A phase change memory device comprising: a plurality of memory cell array blocks, each memory cell array block having phase change memory cells; a counter clock generation unit, which outputs first through third counter clock signal sets in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signal sets have different cycles; a decoding unit, which, in response to the first through third counter clock signal sets, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block; and a driving unit, which applies a firing current to the memory cell array blocks in response to the firing mode signal, wherein the firing current is larger than a reset current, which allows the phase change material to be in a reset state.