Patent ID: 8806141

Claim:
A method for increasing performance in a parallel computing system, the method comprising: while processing source code, prefetching data, from a memory storage device, whose addresses appear in a list, the list describing an arbitrary sequence of prior cache miss addresses; controlling the prefetching of the data by using at least one compiler directive issued by a compiler, the controlling includes: storing current cache miss addresses in a queue; creating the list based on the stored current cache miss addresses; using the list at a next processing of the source code; detecting a new cache miss; comparing an address corresponding to the detected new cache miss against a predetermined number of the current cache miss addresses stored in the queue; identifying a match between the compared address and one of the stored addresses in the queue; indicating that a portion of a lower-level cache line is missed upon identifying the match; and moving an address at a head of the queue from the queue to an array upon identifying no match.