Patent ID: 6856014

Claim:
A wafer structure defining a multiplicity of devices individually sealed by a cover wafer comprising: a substrate wafer having a selected size and including said multiplicity of devices formed thereon; an interposer wafer with a top side and a substrate side and having substantially said selected size, said substrate side bonded to said substrate wafer and said interposer wafer comprising a first plurality of parallel and spaced apart grid members and a second plurality of parallel and spaced apart grid members intersecting said first plurality of grid members to define a multiplicity of open areas in register with said multiplicity of devices formed on said substrate wafer; and a top wafer having a top surface and a bottom surface and substantially said selected size and said bottom surface bonding to said top side of said interposer wafer so as to provide a seal along the perimeter of selected ones of said multiplicity of devices between parallel pairs of intersecting grid members and under said top wafer, said top wafer further defining kerfs cut through said top surface of said top wafer and said intersecting grid members of said interposer wafer to provide separation between individual ones of said sealed devices.