Patent ID: 8809957

Claim:
A complementary metal-oxide semiconductor (CMOS) circuit, comprising: a wafer having a buried oxide (BOX) and an active layer on the BOX, wherein the active layer is configured to have at least one first region with a thickness t 1 and at least one second region with a thickness t 2 , and wherein t 2 is less than t 1 ; a nanowire field-effect transistor (FET) on the BOX formed in the second region of the active layer comprising: nanowires and pads patterned in the second region of the active layer, wherein the pads are attached at opposite ends of the nanowires in a ladder-like configuration, and wherein the nanowires are suspended over the BOX; a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the first gate stack serve as a channel region of the nanowire FET; an epitaxial material on portions of the nanowires and pads that serve as source and drain regions of the nanowire FET; a finFET on the BOX formed in the first region of the active layer comprising: a plurality of fins patterned in the first region of the active layer, wherein a height of the fins patterned in the first region of the active layer is greater than a thickness of the nanowires and pads patterned in the second region of the active layer based on the first region of the active layer being thicker than the second region of the active layer; a second gate stack covering at least a portion of each of the fins, wherein the portions of the fins covered by the second gate stack serve as a channel region of the finFET; and an epitaxial material on portions of the fins that serve as source and drain regions of the finFET.