Patent ID: 7692319

Claim:
A semiconductor wafer, comprising: multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction; a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other; and one or more alignment cells formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment cells being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer, wherein each of the one or more alignment cells is disposed between two opposing straight edges of two adjacent ones of the device chip areas, and includes a first alignment mark configured to have a longitudinal direction coinciding with the X axis and a second alignment mark configured to have a longitudinal direction coinciding with the Y axis, the two opposing straight edges of the two adjacent ones of the device chip areas are parallel to at least one of the scribe lines, and each of the one or more alignment cells is smaller than a width of the scribe lines measured in a width direction of the scribe lines.