Patent ID: 7161413

Claim:
A chopper-stabilized current mirror, comprising: a first pair of field-effect transistors (FETs) (MP 1 , MP 2 ) having their sources connected to a supply voltage and their gates connected to an input current I in ; a first switching network (S 1 ) comprising two inputs (in 1 , in 2 ), two outputs (out 1 , out 2 ), and a clock input, said inputs in 1 and in 2 connected to the drains of MP 1 and MP 2 , respectively, said network arranged to alternately connect in 1 and in 2 to out 1 and out 2 , respectively, and to out 2 and out 1 , respectively, in response to a first clock signal (CLK 1 ) applied to S 1 's clock input; a second switching network (S 2 ) comprising two inputs (in 1 , in 2 ), two outputs (out 1 , out 2 ), and a clock input, said inputs in 1 and in 2 coupled to the drains of MP 1 and MP 2 , respectively, said second switching network arranged to alternately connect in 1 and in 2 to out 1 and out 2 , respectively, and to out 2 and out 1 , respectively, in response to a second clock signal (CLK 2 ) applied to S 2 's clock input; an output impedance (r o ) boost amplifier (A 1 ) having differential inputs (in 1 , in 2 ) and outputs (out 1 , out 2 ) and a reference voltage input, said differential inputs in 1 and in 2 connected to out 1 and out 2 of S 2 , respectively, and said reference voltage input connected to a voltage V ref ; a third switching network (S 3 ) comprising two inputs (in 1 , in 2 ), two outputs (out 1 , out 2 ), and a clock input, said inputs in 1 and in 2 connected to out 1 and out 2 of A 1 , respectively, said third switching network arranged to alternately connect in 1 and in 2 to out 1 and out 2 , respectively, and to out 2 and out 1 , respectively, in response to a third clock signal (CLK 2 S) applied to S 3 's clock input; and a second pair of FETs (MP 3 , MP 4 ) having their sources connected to outputs out 1 and out 2 of S 1 , respectively, their gates connected to out 1 and out 2 of S 3 , respectively, the drain of MP 3 connected to I in and the drain of MP 4 providing said current mirror's output I out , such that said first pair of FETs are cascoded with said second pair of FETs and such that said amplifier boosts the output impedance at the drain of MP 4 ; said mirror arranged such that: switching network S 1 is clocked by CLK 1 to chop the signals at the drains of MP 1 and MP 2 and thereby reduce errors in I out due to mismatches between MP 1 and MP 2 ; and switching network S 2 is clocked by CLK 2 to chop the offset voltage of amplifier A 1 at the drains of MP 1 and MP 2 and switching network S 3 is clocked by CLK 2 S to chop the signals at the outputs of A 1 to reduce errors in I out due to the offset voltage of said r o boost amplifier and such that said r o boost amplifier always operates with negative feedback, CLK 2 and CLK 2 S shifted with respect to CLK 1 to reduce errors in I out due to parasitic capacitances at the sources of MP 3 and MP 4 .