Patent ID: 8707114

Claim:
A semiconductor device comprising: a decoder that activates one first test signal in a plurality of first test signals in response to an external test code signal, the one first test signal being indicated by the external test code signal; a first register unit electrically coupled to the decoder, the first register unit receiving in parallel the plurality of first test signals from the decoder, the first register unit outputting in series the plurality of first test signals as a plurality of second test signals; a second register unit electrically coupled to the first register unit, the second register unit receiving in series the plurality of second test signals from the first register unit, the second register unit outputting in parallel the plurality of second test signals as a plurality of third test signals; and a control unit electrically coupled to the second register unit, the control unit receiving in parallel the plurality of third test signals from the second register unit, the control unit controlling operation of a memory cell array in response to the plurality of third test signals.