Patent ID: 7047166

Claim:
A dynamically reconfigurable VLSI device for implementing in hardware any multiple outputs combinational target circuit having the output functions expressed in logical sum-of-product equations with a maximum of m inputs, a maximum of r outputs and a maximum of n product terms p(k), comprising: a register with m bits for storing the input variables; n cells, a cell C(k) for determining the logical value of a product term p(k) of said equations for given inputs; a block of r OR gates, each one with n inputs, associated with said cells C(k) for receiving the logical value of product terms p(k) and outputting the r bits of output functions; wherein said cell C(k) comprises: a storage area for storing the information that characterizes a product term, named mask word, product word and function word; first logic level means for receiving said m inputs and said mask word to produce a first intermediate result, which identify the input variables that form a product term; second logic level means for comparing the said product term with said first intermediate result to produce a second intermediate result concerning a product term; third logic level means for receiving said second intermediate result to produce the logical value of the product term; and forth logic level means for transferring said function word to r outputs, according to said logical value of said product term p(k), and subsequently to be OR-ed with function words of other product terms.