Patent ID: 8189399

Claim:
A method for erasing information stored in one memory cell including one access transistor and one control gate of the EEPROM comprising: an active area of a first conductivity type formed in a semiconductor substrate; a gate line formed on the active area; a first well of a second conductivity type formed in a first region of the active area; an access transistor having a floating gate formed of part of the gate line located on the first region, and a source region and a drain region formed at opposite sides of the floating gate in the first well; a first well tap of the second conductivity type spaced apart from the source and drain regions in the first well and having a higher impurity concentration than that of the first well; a control gate formed of part of the gate line located on a second region in the active area spaced apart from the first region; first impurity regions formed at both sides of the control gate in the second region of the active area; a second well tap of the first conductivity type formed in a third region of the active area spaced apart from the first region and the second region and having a higher impurity concentration than that of the active area; a second well of the second conductivity type in the second region of the active area spaced apart from the first well and surrounding the first impurity regions; and a third well tap in the second well spaced apart from the first impurity regions and having a higher impurity concentration than that of the second well, the method comprising: applying a predetermined erasing voltage to the source/drain regions of the access transistor and the first well tap; applying a ground voltage to the first impurity regions in the second region; and applying a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, to the second well tap.