Patent ID: 8863068

Claim:
A method for integrated circuit (IC) chip and IC package design comprising: dividing a layout region of said chip containing one or more current sources, one or more fixed electrical connectors and grid networks, into a number of bins, said electrical connectors delivering electrical current drawn by said current sources of said layout region via said grid networks; generating a data structure representing a current distribution relation between said bins and the one or more fixed electrical connectors, the data structure comprising a set of weighted vectors, each weighted vector representing a sensitivity of electrical connector currents with respect to each said bin, and indicating for each bin, a portion of bin current distributed to each electrical connector; obtaining, using said data structure, an amount of current flow via said fixed electrical connectors with respect to an amount of current drawn by said current sources in said bins; and determining, using said current flow and current drawn amounts, the optimal locations of blocks having said one or more current sources, with respect to one or more objectives and constraints, wherein a constraint includes a limit of electrical connector current to be drawn per bin, wherein a hardware processor is configured utilizing stored instructions to perform said layout region dividing, said generating, obtaining and determining steps.