Patent ID: 7725684

Claim:
A simultaneous multithreaded computer processor with speculative instruction issue that increases throughput, the computer processor comprising: multiple independent input buffers, wherein one set of buffers is provided for each of a plurality of independent threads of instructions; instruction issue logic that has an output buffer and is connected to the independent input buffers, wherein the instruction issue logic: receives a set of instructions comprising one instruction from each of the threads of instructions; identifies as dependent instructions those received instructions that require a result from a prerequisite instruction; determines a probability for each instruction that the each instruction will complete all stages of a multi-stage instruction pipeline of the processor without causing a stall, wherein the probability for each received instruction is expressed as a percentage value; selects the received instruction of the set that is least likely to cause a stall in the multi-stage pipeline; and issues the selected instruction into the pipeline for processing, from the instruction issue logic, when the probability for the selected instruction is above a predetermined threshold that is 50%; and wherein a first stage of the multi-stage pipeline is connected to an output buffer of the instruction issue logic.