Patent ID: 7533227

Claim:
A data processing system comprising: a memory hierarchy that provides coherent memory operation at a cache line level; and a processor chip coupled to the memory hierarchy via a system interconnect, said processor chip having a processor core, store queue (STQ) mechanism including a store queue, Read claim (RC) mechanism, and associated processor cache; logic within the STQ mechanism and RC mechanism for reducing latency of processing store conditional (STCX) operations, said logic including logic which: responsive to allocation of a STCX operation to an entry of the store queue, tags the entry as a higher priority entry relative to a prior entry allocated a regular store operation; and selects the higher priority entry for dispatch ahead of said prior entry during dispatch selection process, wherein the STCX operation is forwarded to said processor cache ahead of the regular store operation thus reducing store queue latency for forwarding STCX operations to said processor cache; wherein said RC mechanism further comprises logic for: first determining that both said higher priority entry and said prior entry are valid for dispatch; evaluating when a dispatch of the higher priority entry ahead of the prior entry does not violate a pre-defined architectural rule for dispatching entries from the store queue; and dispatching said higher priority entry ahead of said prior entry when a selection of said higher priority entry for dispatch ahead of said prior entry does not violate the predefined architectural rule for dispatching entries from the store queue.