Patent ID: 8847377

Claim:
A stacked wafer level package, comprising: an insulation member including a chip region having a receiving groove formed in a surface of the insulation member, a first peripheral region disposed at a first side adjacent to the chip region and a second peripheral region disposed at a second side adjacent to the chip region opposite the first side; a first semiconductor chip having a first bonding pad formed on an upper surface thereof and coupled to the receiving groove of the chip region of the insulation member; a second semiconductor chip disposed on a lower surface of the insulation member in the first peripheral region and a portion of a lower surface of the first semiconductor chip that is opposite to the upper surface adjacent to therein and having a second bonding pad formed on an upper surface thereof electrically connected to a first connection electrode that passes through a portion of the insulation member; a third semiconductor chip disposed on a lower surface of the insulation member in the second peripheral region and another portion of the lower surface of the first semiconductor chip adjacent to therein and having a third bonding pad formed on an upper surface thereof electrically connected to a second connection electrode that passes through a portion of the insulation member; and a redistribution structure including a first redistribution, a second redistribution, and a third redistribution each directy connected to the first bonding pad, the first connection electrode, and the second connection electrode, wherein the upper surfaces of the second and the third semiconductor chips are in direct contact with the lower surface of the first semiconductor chip, wherein the first redistribution, the second redistribution, and the third redistribution are placed on the same plane.