Patent ID: 8304172

Claim:
A method of creating device features on a semiconductor device structure, the method comprising: creating a first pattern of negative photoresist features overlying a target material of the semiconductor device structure, the first pattern of negative photoresist features defined by a first component photolithographic mask, wherein the first pattern of negative photoresist features is void of tip-to-tip and tip-to-line design rule violations; creating a second pattern of negative photoresist features overlying the target material, the second pattern of negative photoresist features defined by a second component photolithographic mask, the first pattern of negative photoresist features and the second pattern of negative photoresist features together forming a combined pattern of negative photoresist features, wherein the second pattern of negative photoresist features is void of tip-to-tip and tip-to-line design rule violations, the combined pattern of negative photoresist features is void of tip-to-tip and tip-to-line design rule violations; selectively etching the target material, using the combined pattern of negative photoresist features as an etch mask, resulting in a recess line pattern formed in the target material; and after selectively etching the target material, forming a third pattern of positive photoresist features that intersect and cover designated sections of the recess line pattern, wherein the third pattern of positive photoresist features is void of tip-to-tip and tip-to-line design rule violations.