Patent ID: 7479434

Claim:
A method of manufacturing one or more regions of a semiconductor device, the method comprising: forming a preliminary gate structure including an uppermost polysilicon layer pattern on a substrate; forming impurity regions in the substrate at both sides of the preliminary gate structure; forming spacers against sidewalls of the preliminary gate structure; forming a silicon oxide layer pattern having a thickness sufficiently thin so that a subsequent silicidation reaction occurs on a portion of the substrate next to the spacers; forming a metal layer on the preliminary gate structure, the silicon oxide layer pattern and the spacers; and reacting the metal layer with the preliminary gate structure and the substrate underneath the silicon oxide layer pattern to form a gate structure and a second silicide layer pattern on the impurity regions, respectively, the gate structure including an uppermost first metal silicide layer pattern having a first thickness, and the second silicide layer pattern having a second thickness thinner than the first thickness.