Patent ID: 8158469

Claim:
A method of fabricating an array substrate, comprising: forming a gate line and a gate electrode connected to the gate line; sequentially forming a gate insulating layer, an intrinsic amorphous silicon layer, an inorganic material insulating layer and a heat transfer layer on the gate line and the gate electrode; irradiating a laser beam onto the heat transfer layer to crystallize the intrinsic amorphous silicon layer into a polycrystalline silicon layer; removing the heat transfer layer; patterning the inorganic insulating material layer using a buffered oxide etchant to form an etch-stopper corresponding to the gate electrode, wherein a first process time for the step of patterning the inorganic insulating material layer is longer than a second process time minimally required for completely removing the inorganic insulating material layer; sequentially forming an impurity-doped amorphous silicon layer and a metal layer on the etch-stopper and the polycrystalline silicon layer; patterning the metal layer to form a data line, a source electrode and a drain electrode, the impurity-doped amorphous silicon layer to form an ohmic contact layer, and the polycrystalline silicon layer to form an active layer, the data line crossing the gate line and connected to the source electrode, the drain electrode spaced apart from the source electrode, an end of the source electrode and an end of the drain electrode overlapping the etch-stopper, the ohmic contact layer disposed under the source electrode and the drain electrode, and the active layer disposed under the ohmic contact layer and the etch-stopper; forming a passivation layer on the data line, the source electrode and the drain electrode and including a drain contact hole exposing a portion of the drain electrode; and forming a pixel electrode on the passivation layer and contacting the portion of the drain electrode through the drain contact hole.