Patent ID: 7420854

Claim:
A static random access memory (SRAM) cell, the SRAM cell comprising: a word-line for receiving an activation signal; a first and a second pass-gate transistors with their gate terminals commonly coupled to the word-line; a first and a second parasitic transistor with the first parasitic transistor and the first pass-gate transistor sharing the same source, bulk and drain terminals, and the second parasitic transistor and the second pass-gate transistor sharing the same source, bulk and drain terminals; a first and second bit-line with the first bit-line coupled to a first source or drain terminal of the first pass-gate transistor, and the second bit-line coupled to a first source or drain terminal of the second pass-gate transistor; and a first and a second pull-up transistor with their source terminals commonly coupled to a high voltage system (Vcc), wherein, a drain terminal of the first pull-up transistor, a second source or drain terminal of the first pass-gate, a gate terminal of the second pull-up transistor, and a gate terminal of the second parasitic transistor are all coupled together, and wherein, a drain terminal of the second pull-up transistor, a second source or drain terminal of the second pass-gate transistor, a gate terminal of the first pull-up transistor, and a gate terminal of the first parasitic transistor are all coupled together.