Patent ID: 7952508

Claim:
A circuit comprising: a common mode scrambler circuit comprising: a p input receiving a p input signal and an n input receiving an n input signal, wherein the p input signal and the n input signal is either in a low state or a high state; a p output transmitting a p output signal and an n output transmitting an n output signal, wherein the p output signal and the n output signal is either in a low state or a high state; and scrambler logic circuitry configured to receive a scrambler control signal which is either in a low state or a high state, wherein when the p input signal and the n input signal are in different states, the scrambler logic circuitry causes the p output signal to be in the same state as the p input signal and causing the n output signal to be in the same state as the n input signal, and wherein when the p input signal and the n input signal are in the same state, the scrambler logic circuitry generates the p output signal and the n output signal as a function of at least the scrambler control signal.