Patent ID: 8590010

Claim:
A method for identifying a chip having a memory array comprising; a) using a computer, determining parameters intrinsic to said memory array; b) generating a window address location of said memory array; c) selecting a first fail-count target; d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of first fail-counts until said first fail-count target is reached, wherein said first bit map includes passing and failing memory address locations; e) selecting a second fail-count target smaller than said first fail-count target; f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of second fail-counts until said second fail-count target is reached, wherein said second bit map includes passing and failing memory address locations; and g) comparing said first binary string to said second binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID).