Patent ID: 7912669

Claim:
A process comprising: identifying using a computer processor parameters of a circuit under test; determining using the computer processor an upper and a lower limit for one or more components of the circuit under test; generating using the computer processor a population of faulty and non-faulty circuits for the circuit under test; generating using the computer processor feature vectors for each faulty and non-faulty circuit; storing into a computer storage medium the feature vectors in a fault dictionary; generating using the computer processor a feature vector for an implementation of the circuit under test in a field operation; and comparing using the computer processor the feature vector for the implementation of the circuit under test in the field operation to the feature vectors in the fault dictionary; wherein the population of non-faulty circuits is generated using the computer processor by: assigning a value of a circuit component so that it remains within the upper and lower limits; supplying a test signal to each circuit in the population of non-faulty circuits, thereby generating responses of the non-faulty circuits; and forming a cluster in a multidimensional feature space of non-faulty circuits from the responses of the non-faulty circuits in the fault dictionary; and further wherein the population of faulty circuits is generated using the computer processor by: assigning a value of a circuit component so that it falls outside the range of lower and upper limits; supplying a test signal to each circuit in the population of faulty circuits, thereby generating responses of the faulty circuits; and forming a cluster in a multidimensional feature space of faulty circuits from the responses of the faulty circuits in the fault dictionary; estimating using the computer processor boundaries of the cluster of faulty circuits and the cluster of non-faulty circuits; and determining using the computer processor whether the circuit under test is faulty or non-faulty as a function of its relation to the cluster of faulty circuits and the cluster of non-faulty circuits.