Patent ID: 8560813

Claim:
A multithreaded processor for executing instructions from a plurality of instruction threads which may each include instructions of differing complexity, comprising: a plurality of pipelines for executing the instructions of differing complexity from the instruction threads in parallel, wherein the instructions of differing complexity comprise instructions from different instruction set architectures; and an instruction scheduler for issuing instructions and determining on each clock cycle which instructions are issued to the pipelines, wherein at least one pipeline comprises two pipeline paths, a fast path with a lower latency for executing instructions of a lower complexity and a slow path for executing instructions of a higher complexity and the instruction scheduler is configured to determine on which of the two pipeline paths issued instructions should execute and schedule the issued instructions on the two pipeline paths to avoid a data clash by maintaining a data record for the pipeline that records actions performed on that pipeline and using the data record for that pipeline to track when a higher complexity instruction has been issued and preventing issuing a lower complexity instruction to the corresponding lower complexity pipeline so that the higher and lower complexity instructions complete execution on different clock cycles.