Patent ID: 8649238

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of banks, the banks being divided into a first bank block and a second bank block; an address control unit for accessing the memory cell array; and a logic circuit configured to control the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually and simultaneously operate in a second operation mode, wherein each of the first and second bank blocks is individually divided into at least two groups in response to the command and the address signal, and each of the first and second bank blocks operates in one of a group mode and a non-group mode in the second operation mode, and wherein a first column access time is at least two times as long as a second column access time, and wherein the first column access time is associated with a column access time when at least one of the first and second bank blocks operates in the group mode, and the second column access time is associated with a column access time when at least one of the first and second bank blocks operates in the non-group mode.