Patent ID: 8063803

Claim:
An apparatus comprising: a plurality, M, of Analog to Digital Converters (ADCs) coupled to convert an input signal to a set of ADC outputs as M digital values, each of the ADCs having at least one of an offset correction input, a gain correction input, or a phase correction input; an adaptive processor, coupled to receive the M digital values, the adaptive processor estimating one or more correction signals for at least one of offset, gain, or phase error in at least one of the M ADCs, the adaptive processor determining the correction signals by: accumulating two or more of the M digital values over time, to provide M accumulated values, X k , for k=1 to M; determining a reference value, X mean , from a combination of the M accumulated values; providing an adjusted set of set of digital values from the M accumulated values, X k , and the reference value X mean ; from the adjusted set of digital values, determining at least one of an offset, gain or phase correction value corresponding to one or more estimated correction signals to be applied to correct at least one of offset, gain, or phase error of at least one of the ADCs; the estimated correction signals connected to a corresponding at least one of the offset, gain, or correction input of at least one of the ADCs; and a multiplexer, for interleaving the M digital values output by the ADCs to form a digital representation of the input signal.