Patent ID: 7893494

Claim:
A semiconductor device comprising: a substrate including a semiconducting layer positioned overlying an insulating layer, the semiconducting layer including a semiconducting body having a first portion and a second portion, wherein a planarization process is performed on the substrate and wherein a densification process is performed on the substrate; isolation regions present about a perimeter of the semiconducting body; a gate structure overlying an upper surface of the first portion of the semiconducting body; a dielectric spacer abutting the gate structure and atop the semiconducting body, wherein a portion of the semiconducting body is exposed; and a silicide body contact that is in direct physical contact with the second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region, wherein: a portion of the upper surface of the semiconducting body between the gate structure and the silicide is exposed in that it is not covered by the dielectric spacer, a portion of the upper surface of the semiconductor body has a non-silicide semiconducting region doped with a p-type dopant; and a bottom surface of the dielectric spacer, a top surface of the isolation regions and a top surface of the silicide are all coplanar to each other.