Patent ID: 7003763

Claim:
A data processor built in a semiconductor chip, comprising: a central processing unit; a debugging module; other circuit modules; and a plurality of buses coupled to said central processing unit and said other circuit modules, wherein said debugging module comprises: a selection circuit for selecting a bus in accordance with a trace condition from a plurality of buses used for an operation of said central processing unit or the other circuit module and obtaining trace information in accordance with the trace condition from the selected bus; a buffer circuit for holding trace information selected by said selection circuit and attribute information of the trace information which includes a bus identification information indicating a selected bus by said selection circuit; an output circuit capable of outputting the trace information and the attribute information of the trace information held in said buffer circuit in a predetermined format to the outside of said semiconductor chip; and a control circuit for controlling operations of said selection circuit, said buffer circuit, and said output circuit on the basis of the trace condition designated by said central processing unit and operating states of said central processing unit and the other circuit modules, wherein said selection circuit comprises: a first selector for selecting a bus for obtaining trace information from a plurality of buses and holding information of the selected bus on a bus cycle unit basis; a second selector for selecting a bus for obtaining trace information from a plurality of buses and holding information of the selected bus on the bus cycle unit basis; a command address buffer for holding a command address of a command immediately preceding to a command address being executed at present; and a third selector for selecting one of outputs of said first selector, said second selector, and said command address buffer and supplying the selected output to said buffer circuit, wherein said control circuit is capable of controlling the first and second selectors to select a bus designated by the trace condition, and is capable of controlling the third selector to output an output of said first selector, said second selector, or said command address buffer in accordance with appearance of an access mode designated by the trace condition.