Patent ID: 7370307

Claim:
A computer automated design system, adapted for designing a multi-level interconnect of a semiconductor integrated circuit, comprising: a subject routing module configured to set a first grid area defined by a first line group and a second line group orthogonal to the first line group and a first diagonal grid area defined by a third line group extending diagonally to the first line group and a fourth line group orthogonal to the third line group in a subject wiring layer assigned as one of wiring layers in the multi-level interconnect, the third and fourth line groups being connected to the first to second line groups, and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire in the first diagonal grid area based on the first to fourth line groups; and a next routing module configured to set a second grid area defined by the first and second line groups and a second diagonal grid area defined by the third and fourth line groups in an upper wiring layer assigned on the subject wiring layer in the multi-level interconnect so that the second grid area and second diagonal grid area overlap the first grid area and first diagonal grid area, and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire in the second diagonal grid area based on the first to fourth line groups.