Patent ID: 8685861

Claim:
A method of manufacture of an integrated circuit system comprising: providing an integrated circuit device; forming an undoped insulating layer over the integrated circuit device; forming a thin insulating layer over the undoped insulating layer having a dopant level within a range of dopant levels for preventing lateral etch by depositing the thin insulating layer with a flow of dopant between about thirty percent to about fifty percent of a bulk flow of the dopant; forming a doped insulating layer over the thin insulating layer by depositing the doped insulating layer with the bulk flow of the dopant; forming a recess by etching only the undoped insulating layer, the thin insulating layer and the doped insulating layer, the thin insulating layer including a thin insulating layer sidewall sloped less than a sidewall of the undoped insulating layer and a sidewall of the doped insulating layer; and forming a contact in the recess.