Patent ID: 7047399

Claim:
A computer system comprising: storage circuitry for holding a plurality of instructions at respective storage locations, the plurality of instructions including a first string of instructions including a set branch instruction indicating a target location within the storage circuitry at which a new instruction, not included in the first string, is stored, the new instruction to be executed only if a branch condition is satisfied, and the first string further including a subsequent instruction that is subsequent in the first string to the set branch instruction; instruction fetch circuitry to fetch instructions from said storage circuitry, the instruction fetch circuitry including a first instruction fetcher to fetch instructions, including the subsequent instruction, from the first string, and including a second instruction fetcher; and execution circuitry to execute fetched instructions, including executing the set branch instruction, wherein the second instruction fetcher is operative, responsive to execution of said set branch instruction by the execution circuitry and irrespective of whether the branch condition is satisfied, to fetch the new instruction from the location indicated by the set branch instruction, in parallel to the first instruction fetcher fetching the subsequent instruction.