Patent ID: 8809856

Claim:
A semiconductor device comprising: a substrate; a gate electrode layer on the substrate; a silicon nitride layer on the gate electrode layer; a first silicon oxide layer on the silicon nitride layer; a oxide semiconductor layer on and in contact with the first silicon oxide layer; a second silicon oxide layer on and in contact with a channel formation region of the oxide semiconductor layer and covering lateral end portions of the oxide semiconductor layer; a first conductive layer and a second conductive layer each on and in contact with the second silicon oxide layer a third silicon oxide layer on and in contact with the first conductive layer, the second conductive layer and the second silicon oxide layer; a planarizing insulating layer on the third silicon oxide layer, the planarizing insulating layer comprising an organic material; and a pixel electrode layer on the planarizing insulating layer, wherein each of the first conductive layer and the second conductive layer are on and in contact with the oxide semiconductor layer through an opening formed in the second silicon oxide layer and overlapping with the gate electrode layer, and wherein the pixel electrode layer is on and in contact with the first conductive layer through an opening formed in the planarizing insulating layer and the third silicon oxide layer.