Patent ID: 8042010

Claim:
A method for augmenting a circuit to detect and correct timing errors, the method comprising: partitioning the circuit into a set of blocks, wherein a respective block is clocked by a local clock signal; integrating an error signal propagation circuit between the set of blocks; and for a respective block: determining a set of internal registers that are to be implemented as double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error; replacing the determined set of internal registers with double data sampling registers; integrating a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block; and integrating into the respective block a timing circuit that generates the local clock signal from a global clock signal and the error signals.