Patent ID: 7036117

Claim:
An assembler for processing structured assembly language expressions utilized in structured assembly language programming, said assembler comprising: means for recognizing a structured assembly language expression's mnemonics containing elements arg1 cc arg2, wherein said cc is a condition code, wherein the form of said expression's mnemonics or the nature of one or more of said expression's elements selects a corresponding comparison opcode, wherein said arg1 and said arg2 are valid arguments for said selected comparison opcode; means for constructing a data structure referencing said arg1, said arg2, said cc, and a branch destination; means for generating a comparison opcode in response to elements of said data structure; means for generating a conditional branch based on said condition code in said data structure; means for generating a first branch location for execution to proceed as if said structured assembly language expression is true; means for generating a second branch location for execution to proceed as if said structured assembly language expression is false; means for generating a third branch location for execution to proceed to the end of said structured assembly language expression; and means for indicating said branch destination in said data structure is a branch to said first, said second, or said third branch locations.