Patent ID: 8450790

Claim:
A semiconductor device comprising: a first memory cell and a second memory cell formed over a main face of a semiconductor substrate, wherein the first memory cell includes: a first well of a first conductivity type formed in the semiconductor substrate; a first gate insulation film formed over the first well; a first control gate electrode formed over the semiconductor substrate through the first gate insulation film and having a first side face and a second side face positioned at opposite sides of the first control gate electrode; a second gate insulation film extendedly formed over the first side face of the first control gate electrode and the first well and containing a first charge retention film; a first memory gate electrode formed over the first side face of the first control gate electrode and insulated from the first control gate electrode and the semiconductor substrate through the second gate insulation film; a first drain region comprised of a semiconductor region of a second conductivity type opposite the first conductivity type, and formed over the semiconductor substrate in the vicinity of the first control gate electrode; and a first source region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the first memory gate electrode, wherein the second memory cell includes: a second well of the first conductivity type formed in the semiconductor substrate; a third gate insulation film formed over the second well; a second control gate electrode formed over the semiconductor substrate through the third gate insulation film and having a third side face and a fourth side face positioned at opposite sides of the second control gate electrode; a fourth gate insulation film extendedly formed over the third side face of the second control gate electrode and the second well and containing a second charge retention film; a second memory gate electrode formed over the third side face of the second control gate electrode and insulated from the second control gate electrode and the semiconductor substrate through the fourth gate insulating film; a second drain region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the second control gate electrode; and a second source region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the second memory gate electrode, wherein a first gate length of the first memory gate electrode of the first memory cell is longer than a second gate length of the second memory gate electrode of the second memory cell.