Patent ID: 8823113

Claim:
A four transistor circuit layout for an integrated circuit substrate, comprising: an isolation region in the integrated circuit substrate that defines an active region, the active region extending along first and second different directions; a common source region of the four transistors that extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region; four drain regions, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region; four gate electrodes, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions, a respective gate electrode including a vertex and first and second extending portions, the first extending portions having a straight line shape extending from the vertex along the first direction onto the isolation region and the second extending portions having a straight line shape extending from the vertex along the second direction onto the isolation region; a pair of source contact plugs that are connected to one another through the common source region; and four drain contact plugs, a respective one of which electrically contacts a respective one of the drain regions in a respective one of the four quadrants, wherein a first one of the pair of source contact plugs has a bar shape extending between the gate electrodes of a first pair of the four transistors, and a second one of the pair of source contact plugs has a bar shape extending between the gate electrodes of a second pair of the four transistors, and wherein the four drain contact plugs have a bar shape extending along the pair of source contact plugs.