Patent ID: 7725609

Claim:
A computing system comprising: an address bus; a data bus; a first processor configured with an address and data port coupled to said address bus, and a second processor configured with an address port coupled to said address bus and configured with a data port coupled to said data bus; a memory device comprising a first port coupled to said address bus, and a second port coupled to said data bus, wherein, for a communication between the memory device and the first processor, the first port of the memory device and the address and data port of the first processor interface via said address bus only, and the memory device is configured to handle both addresses and data from the first processor via said address bus only at its first port, wherein address and data pins of the first processor are multiplexed to said address bus and first port, and neither addresses or data from the first processor is handled at the second port of the memory device, wherein, for a communication between the memory device and the second processor, the first port of the memory device and the address port of the second processor interface via said address bus, and the second port of the memory device and the data port of the second processor interface via said data bus, and the memory device is configured to handle addresses from the second processor via said address bus only at its first port and to handle data from the second processor via said data bus only at its second port.