Patent ID: 7877580

Claim:
A method for speculatively executing program instructions in a microprocessor having execution units which commit results of non-speculative instructions to architected registers, comprising: detecting the occurrence of a stall condition during execution of the program instructions; speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, wherein said speculative executing occurs across multiple pipeline stages within the microprocessor; maintaining a vector of dirty bits to track the validity of the data for the speculatively executed instructions during their execution in the multiple pipeline stages of the microprocessor, wherein dirty bits in the vector are initially set to “0 ” and a given one of the dirty bits is set to “1 ” when an instruction passes a writeback stage where an invalid result calculated by one of the execution units is provided to a corresponding one of the architected registers; and monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages of the microprocessor.