Patent ID: 7305516

Claim:
A multi-port memory device, comprising: a global data bus having a plurality of bus lines; a plurality of data transmission/reception blocks, each of which includes a current sensing type transmitter/receiver for exchanging data with the global data bus, the data transmission/reception block including a plurality of banks and ports; a plurality of switching units for discharging each bus line of the global data bus in response to an initialization signal; and an initialization signal generator for generating the initialization signal in response to a bank active information signal defining an active section of all banks, which exchanges data with a corresponding one of the global data bus, wherein the initialization signal generator includes: a pulse generation unit for generating a bank active information pulse in response to the bank active information signal; a section signal generation unit for receiving the bank active information pulse and generating a bank active ignore signal for ignoring an activation of the bank active information pulse for a predetermined time after the bank active information pulse is activated; and a logic combination unit for generating the initialization signal in response to a power-up signal, the bank active information pulse and the bank active ignore signal.