Patent ID: 7683430

Claim:
An integrated circuit, disposed in or on a semiconductor region or layer which resides on or above a non-conducting portion of a substrate, the integrated circuit comprising: a semiconductor memory cell including: a transistor including: a first semiconductor region including impurities to provide a first conductivity type; a second semiconductor region including impurities to provide the first conductivity type; a body region disposed between the first semiconductor region, the second semiconductor region and the non-conducting portion of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; a gate spaced apart from the body region; and wherein the semiconductor memory cell stores (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and an active access element, electrically coupled to the transistor, including a first access line, a second access line and a control node, wherein the control node of the active access element and the second semiconductor region of the transistor are a common region.