Patent ID: 6937685

Claim:
An early-late pulse accumulator comprising: a first logic device configured to toggle a first output logic level upon receipt of an early pulse; a second logic device configured to toggle a second output logic level upon receipt of a late pulse, wherein the first and second logic devices are configured to allow only one of the first and second output logic levels to be toggled at a time; a first ripple divider configured to receive the first output logic level and to provide a scaled down count of the number of times the first logic device toggles; a second ripple divider configured to receive the second output logic level and to provide a scaled down count of the number of times the second logic device toggles; a first synchronizing logic device configured to receive the scaled down count of the number of times the first logic device toggles and to generate a first terminal count signal proportional to the number of early pulses received by the first logic device; a second synchronizing logic device configured to receive the scaled down count of the number of times the second logic device toggles and to generate a second terminal count signal proportional to the number of late pulses received by the second logic device; and an integrator configured to receive the first and second terminal count signals and generate a net early-late count.