Patent ID: 7383459

Claim:
An apparatus that performs phase-buffering on a bit-by-bit basis using control queues, comprising: a control queue configured to accept a first control signal and a second control signal, wherein the first control signal and the second control signal are mutually exclusive; wherein the first control signal being asserted indicates the value of a corresponding bit is zero, while the second control signal being asserted indicates the value of the corresponding bit is one; wherein the control queue includes a number of stages, wherein each control queue stage is comprised of asP* circuitry that provides four forward gate delays, six reverse gate delays, and three inversion loops; a forward-transfer mechanism within a stage configured to couple the first control signal and the second control signal from an input of the stage through storage elements to an output of the stage; and a reverse-transfer mechanism configured to accept an acknowledgement signal at the output of the stage and to transfer the acknowledgement signal through a storage element to the input of the stage.