Patent ID: 8809147

Claim:
A method for forming a dual conductive spacer memory cell, comprising: depositing and patterning a first dielectric layer on a semiconductor substrate; forming a layer of tunnel oxide on the exposed semiconductor substrate not covered by the patterned first dielectric layer; depositing a first conductive layer over the patterned first dielectric layer; etching the first conductive layer to form a first conductive spacer and a second conductive spacer above the tunnel oxide area; removing the patterned first dielectric layer; forming a channel oxide on the semiconductor substrate in selected area exposed by the removing of the first patterned dielectric layer; depositing a second dielectric layer on the semiconductor layer and enclosing the first and second conductive spacers; depositing and patterning a second conductive layer over the second dielectric layer to form a control gate over and between the first and second conductive spacers; and depositing a third dielectric layer over the control gate and etching the third dielectric layer to form dielectric spacers to enclose the control gate and the first and second conductive spacers.