Patent ID: 8604517

Claim:
A non-volatile semiconductor memory device, comprising: a memory cell array including a plurality of data control lines and a plurality of data transfer lines formed on a semiconductor substrate, and a plurality of memory cells selected by the data control line and the data transfer line; and a transistor formed on the semiconductor substrate, the transistor including: a gate insulating film formed on the semiconductor substrate and having a thickness greater than a thickness of a gate insulating film of the memory cell; a gate electrode on the gate insulating film; a sidewall insulating film formed on both side surfaces of the gate electrode; a source diffusion layer formed in a portion of the semiconductor substrate corresponding to one side of the gate electrode, and connected to a sense amplifier via a contact; a first hollow formed in a position at a height less than a bottom surface of the gate insulating film, directly below an outer side surface of the sidewall insulating film on another side of the gate electrode; a second hollow formed in the first hollow at a position at a height less than the first hollow; and a drain diffusion layer formed in a portion of the semiconductor substrate corresponding to another side of the gate electrode, the drain diffusion layer including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region surrounded by the low-concentration drain region and connected to the data transfer line via a contact.