Patent ID: 8291244

Claim:
A device for processing data comprising: one or more master units; one or more slave units; and an interconnect, coupled to said one or more master units and said one or more slave units, configured to route transactions, including data transfer transactions, along a wired path between said one or more master units and said one or more slave units; wherein a transaction received by at least one of said one or more slave units includes one or more usage signals specifying a usage prediction indicating when a next transaction will be sent to said at least one of said one or more slave units; and said at least one of said one or more slave units has a local slave power controller responsive to said one or more usage signals to switch said at least one of said one or more slave units to a first slave power state for an interval before said next transaction is expected to be received and to switch said at least one of said one or more slave units to a second slave power state in time to service said next transaction, said first slave power state having a lower power consumption than said second slave power state and said first slave power state having a response latency longer than said second slave power state.