Patent ID: 8040311

Claim:
A pulse width modulated display system comprising: a display controller to deliver voltages, control logic signals and image data to the display system; and an array of pixels, of which each pixel comprises the following elements: a SRAM memory cell having two complementary outputs; a DC balance control circuit controlled by a plurality of external control signals; a two-transistor inverter to apply one of two voltages to a pixel mirror; a single voltage source independent of voltage rails of the pixel array of the display system; and a counter electrode disposed opposite the array of pixels and operated at a voltage potential independent of the voltage potential of the pixels, wherein the complementary outputs of said SRAM memory cell are both presented to the DC balance control circuit; wherein the DC balance control circuit, responsive to the configuration of the external control signals asserts one of the two complementary outputs of the SRAM memory cell to gates of the two transistors of the inverter; and wherein the inverter, responsive to the voltage asserted on the gates of its transistors, applies one of two voltages to the pixel mirror for that pixel.