Patent ID: 8207568

Claim:
A MIM capacitor formed by the following process: providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over said dielectric layer; positioning a hard mask over said second conductive layer; positioning a resist over the hard mask as a mask pattern; removing exposed portions of said hard mask and said second conductive layer to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of said mask; undercutting said second conductive layer so that edges of said second conductive layer are located under said hard mask; and removing exposed portions of said dielectric layer and said first conductive layer using said hard mask to form a capacitor dielectric layer and a lower plate of said MIM capacitor having edges substantially aligned with respective edges of said hard mask, wherein the MIM capacitor comprises: the hard mask is disposed over and above an entire top surface of said second conductive layer of the formed MIM capacitor to form at least a part of an embedding oxide; said first conductive layer, said dielectric layer and said hard mask have a same width dimension; said second conductive layer has a width dimension that is smaller than the respective widths of said first conductive layer, said dielectric layer and said hard mask; said second conductive layer is sandwiched between and in direct contact with said dielectric layer and said hard mask such that a top surface of said second conductive layer is entirely covered by said hard mask; said hard mask entirely covers the top surface of said second conductive layer and extends past edges thereof; and the hard mask has an upper and a lower surface, and the entire upper and lower surfaces are planar.