Patent ID: 7171644

Claim:
A method of implementing an integrated circuit design, comprising the steps of: forming a base implementation set; wherein the base implementation set includes a plurality of base implementation set nodes, each base implementation set node corresponding to a partial netlist of the circuit design; forming a guide implementation set having a plurality of guide implementation set nodes based on the base implementation set; wherein each guide implementation set node annotates a respective base implementation set node; depositing at least one of a plurality of directives on at least one guide implementation set node among the plurality of guide implementation set nodes; wherein each of the plurality of directives controls selection of a task; generating a respective list of one or more tasks for each base implementation set node based on the directive of the guide implementation set node that annotates the base implementation set node, wherein each task in the list operates on the partial netlist corresponding to the base implementation set node; and invoking each respective list of tasks as each base implementation set node is visited.