Patent ID: 7514753

Claim:
A semiconductor device comprising: a silicon substrate; an n-type semiconductor device and a p-type semiconductor device, each being formed on the silicon substrate, the n-type semiconductor device including: an n-channel region formed on a surface of the silicon substrate; an n-type source region and an n-type drain region formed opposite to each other on a surface of the silicon substrate interposing the n-channel region therebetween; a first gate insulator formed on the surface of the n-channel region between the n-type source region and the n-type drain region; and a first gate electrode formed on the first gate insulator, and formed of a first mixed crystal compound of a metal element M and a first group-IV semiconductor element Si 1-a Ge a , where 0≦a≦1, Ge included in the first gate electrode being more than 5% with respect to Si, and the first mixed crystal compound being in contact with the first gate insulator; the p-type semiconductor device including: a p-channel region formed on a surface of the silicon substrate; a p-type source region and a p-type drain region formed opposite to each other on a surface of the silicon substrate interposing the p-channel region therebetween; a second gate insulator formed on the surface of the p-channel region between the p-type source region and the p-type drain region; and a second gate electrode formed on the second gate insulator, and formed of a second mixed crystal compound of the metal element M and a second group-IV semiconductor element Si 1-c Ge c , where 0≦c≦1, a≠c, and the second mixed crystal compound being in contact with the second gate insulator.