Patent ID: 8123137

Claim:
A semiconductor device comprising: an antenna; a memory circuit configured to receive electric power from the antenna; a detecting circuit configured to detect a voltage input to the memory circuit; and a control circuit configured to control operation of the memory circuit depending on an output signal from the detecting circuit, wherein the detecting circuit includes: an input terminal; an output terminal for outputting the output signal from the detecting circuit; a reference voltage terminal; a first resistor, wherein one terminal of the first resistor is electrically connected to the input terminal; a transistor, wherein one of a source and a drain of the transistor is electrically connected to the input terminal and a gate of the transistor is electrically connected to the other terminal of the first resistor; a diode portion having a plurality of diodes serially connected, wherein one terminal of the diode portion is electrically connected to the other terminal of the first resistor and the other terminal of the diode portion is electrically connected to the reference voltage terminal; a second resistor, wherein one terminal of the second resistor is electrically connected to the reference voltage terminal and the other terminal of the second resistor is electrically connected to the other of the source and the drain of the transistor; and a buffer circuit, wherein the other of the source and the drain of the transistor and the other terminal of the second resistor are electrically connected to the output terminal via the buffer circuit.