Patent ID: 7940562

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory cell units, each of the memory cell units including first and second selection transistors, and data-rewritable non-volatile memory cells connected in series between the first and the second selection transistors; a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array; a first gate line commonly connected to gates of the first selection transistors on the same row in the memory cell array; a second gate line commonly connected to gates of the second selection transistors on the same row in the memory cell array; and a bit line, wherein the first selection transistor is connected to a bit line, a selected memory cell unit is connected to a selected word line, a first word line, a second word line and a third word line, all of the first word line, the second word line and the third word line being different from the selected word line, the first word line, the second word line and the third word line being different from one another, the third word line is located between the selected word line and the first gate line in the selected memory cell unit, and the third word line is adjacent to the selected word line in the selected memory cell unit, and wherein in write pulse applying during data writing, a first intermediate voltage for writing is applied to the first word line in a first timing, a voltage level of the second word line changes from a first voltage to a second voltage in a second timing, a high voltage for writing is applied to the selected word line in a third timing which is later than both the first timing and the second timing, a third voltage is applied to the third word line in a fourth timing, which is earlier than the third timing, a fourth voltage is applied to the first gate line in a fifth timing which is earlier than all of the first timing, the second timing and the fourth timing, the first intermediate voltage for writing, the second voltage, the third voltage and the fourth voltage are respectively applied to the first word line, the second word line, the third word line and the first gate line when the high voltage for writing is applied to the selected word line, the high voltage for writing being higher than the first intermediate voltage for writing, the first voltage, the third voltage and the fourth voltage and each of the first intermediate voltage for writing, the first voltage and the third voltage being higher than the second voltage.