Patent ID: 7659572

Claim:
A semiconductor device comprising: a semiconductor substrate having an active region and an isolation layer defining the active region; and a metal gate formed on the active region of the substrate, wherein the metal gate comprises: a gate oxide layer formed on a predetermined area of the active region; a polysilicon layer formed on the gate oxide layer; a metal nitride layer formed on the polysilicon layer, wherein a cross sectional profile of the metal nitride layer substantially resemble the shape of U; a non-metal nitride layer formed on the polysilicon layer and only the outside sides of the metal nitride layer having the substantially U-shaped cross-sectional profile, wherein an upper surface of the non-metal nitride layer is coplanar with an upper surface of the metal nitride layer; a metal layer formed inside the metal nitride layer having the substantially U-shaped cross-sectional profile; a hard mask layer formed on the non-metal nitride layer, the metal layer, and the metal nitride layer having the substantially U-shaped cross-sectional profile; and a re-oxidation layer is formed on the sidewall of the polysilicon layer, the gate oxide and surface of the active region.