Patent ID: 7994823

Claim:
A flip-flop circuit having a scan function, the flip-flop circuit comprising: an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal; a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal, the dynamic input unit including at least two MOS transistors connected in parallel, the scan enable signal connected to a gate of one of the at least two MOS transistors and the second input signal connected to a gate of the other of the at least two MOS transistors; and a static output unit to receive the first timing signal and the first output signal and to output a static output signal, wherein the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.