Patent ID: 8792282

Claim:
A nonvolatile memory device, comprising: a memory cell array including a plurality of memory cell strings on a substrate; a read and write circuit connected to the memory cell strings through a plurality of bitlines, the read and write circuit configured to drive the bitlines; a substrate bias circuit configured to supply an erase voltage to the substrate during an erase operation; a program circuit configured to store time information; a counter configured to start counting when the erase voltage is supplied to the substrate during the erase operation; and an address decoder connected to the memory cell strings through a plurality of wordlines, at least one string selection line, and at least one ground selection line, the address decoder configured to supply a low voltage to the at least one ground selection line and the wordlines during the erase operation, the address decoder configured to float the at least one ground selection line when a count value of the counter matches the time information.