Patent ID: 7864619

Claim:
A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit comprising: a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal; a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit, and a discharge unit configured to discharge a word line of the memory, wherein: the discharge unit receives a third control signal and a busy signal, and the discharge unit discharges the word line in a write period in which the SET state current pulse and the RESET state current pulse are not generated, in response to the third control signal and the busy signal.