Patent ID: 8479179

Claim:
A method for compiling a program including a loop, the loop in the program including K instructions (K≧2) and repeating for M times (M≧2), comprising the steps of: a) performing resource conflict analysis to the K instructions in the loop; i) wherein in the case that K is an even number, determining successively and respectively whether functional units for executing an ith instruction (1≦i≦K/2) and those for executing a jth instruction ((K/2+1)≦j≦K), in the K instructions, are in conflict; and determining successively whether registers for executing the ith instruction (1≦i≦K/2) and registers for executing any one from the jth instruction ((K/2+1)≦j≦K) to the Kth instructions, in the K instructions, are in conflict; and ii) wherein in the case that K is an odd number, determining successively and respectively whether the functional units for executing the ith instruction (1≦i≦((K+1)/2−1)) and those for executing the jth instruction (((K+1)/2+1)≦j≦K), in the K instructions, are in conflict; and determining successively whether registers for executing the ith instruction (1≦i≦(K+1)/2−1) and registers for executing any one from the jth instruction (((K+1)/2+1)≦j≦K) to the Kth instruction, in the K instructions, are in conflict; b) dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and c) compiling the program, wherein the instructions in the first combined instruction section in a cycle N (N=2, 3, . . . M) and the instructions in the second combined instruction section in a cycle N−1 are compiled in parallel respectively.