Patent ID: 7488669

Claim:
A method of making at least one marker for double gate SOI processing on a SOI wafer, wherein the SOI wafer comprises a substrate, an oxidized layer on the substrate, and a semiconductor layer on top of the oxidized layer; wherein the double gate SOI processing is performed on at least one die; wherein the at least one die is located on the semiconductor layer and comprises at least an inner area arranged as a circuit area and an outer area arranged as scribe line area; wherein the double gate SOI processing comprises: separating the semiconductor layer from the oxidized layer, and attaching the separated semiconductor layer as a turned-over semiconductor layer on a surface of a new substrate, wherein the original top surface of the semiconductor layer is directed towards the surface of the new substrate, the method of making the at least one marker comprising: forming a first marker in a first direction in the scribe line area, said first marker having a diffraction structure wherein said diffraction structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in said first direction; and forming a second marker in the first direction in the scribe line area, the second marker being a mirror image of the first marker, around a second direction perpendicular to said first direction.