Patent ID: 7423905

Claim:
A read-only memory (ROM), comprising: a substrate; a plurality of row conductors insulated from each other and at least partially layered on a portion of said substrate; a plurality of column conductors insulated from each other and from said row conductors and at least partially layered on a portion of said plurality of row conductors; a plurality of amplifiers electrically connected to said column conductors; and at least one linear passive element attached between said row conductors and said column conductors, wherein at least one of said amplifiers connected to one of said column conductors has an input impedance much lower than the combined parallel impedance of said linear passive elements connected to said one of said column conductors, thus comprising a virtual ground, and at least one of said amplifiers connected to one of said column conductors is operable to output a first logical state when one of said linear passive elements is electrically connected between one of said row conductors and said one of said column conductors, and wherein said at least one of said amplifiers is operable to output a second logical state when said one of said linear passive elements is absent between said one of said row conductors and said one of said column conductors.