Patent ID: 6937078

Claim:
A circuit configuration for regenerating clock signals, comprising: an input differential amplifier generating first and second amplified signals in response to first and second differential input clock signals; first and second inverters generating respective first and second differential output clock signals; and an offset compensation circuit coupled to said first and said second inverters and adjusting a difference between the two output clock signals to a constant value, said offset compensation circuit further connected to said input differential amplifier and receiving the first and second amplified signals, said offset compensation circuit containing: a control amplifier having an input receiving the two output clock signals and outputting output signals derived from the output clock signals; and a further differential amplifier generating first and second amplified, offset-compensated signals from the first and second amplified signals of said input differential amplifier and the output signals of said control amplifier and feeding the first and second amplified, offset-compensated signals as drive signals to said inverters.