Patent ID: 7466576

Claim:
A system of content addressable memories (CAMs) for combining match results of two CAMs, comprising: a first CAM device; a second CAM device; a plurality of global match (ML) lines and dummy match lines and associated outputs of each CAM device coupled to their associated plurality of ML lines and dummy match lines; and an External Priority Encoder module comprising: an Interface Circuit for each of the first CAM device and the second CAM device; and a Priority Encoder block in communicating relationship with each Interface Circuit and wherein the Interface Circuit comprises: a synchronizer circuit; and a plurality of latches, wherein the synchronizer circuit combines and integrates the match results from the first CAM device and the second CAM device and triggers the operation of the External Priority Encoder module based on the latter arriving signal of the first CAM device and the second CAM device, wherein the plurality of latches coupled via the associated plurality of match lines and dummy match lines is used to clock match latches and the associated outputs to each of the first CAM device and the second CAM device to store associated match signals received from each of the first CAM device and the second CAM device, wherein the Priority Encoder block generates a signal HIT ADDRESS which gives a priority address location of a match line ML where both the first CAM device and the second CAM device have a match, and wherein the synchronizer circuit has the ability to handle mismatches between the first CAM device and the second CAM device as well as to differentiate valid and invalid combinations between the first CAM device and the second CAM device.