Patent ID: 6990007

Claim:
A semiconductor memory device comprising: a first cell group having at least two memory cells which are serially connected, the memory cell including a ferroelectric capacitor and a transistor which are connected in parallel; a first bit line selectively electrically connected to one end of the first cell group; a second bit line selectively electrically connected to another end of the first cell group; a first power supply connection circuit which selectively electrically connects a power supply line to the second bit line, the power supply line having a first potential; a sense amplifier which has a first terminal electrically connected to the first bit line, generates one of the first potential and a second potential onto the first terminal according to data stored in the memory cell and generates another one of the first potential and the second potential onto a second terminal thereof; and a first bit line connection circuit which selectively electrically connects the second terminal to the second bit line.