Patent ID: 7525393

Claim:
A digital frequency multiplier circuit comprising: a digitally controlled oscillator (DCO) for generating an internal feedback signal; a phase detector for detecting a phase difference pulse between said internal feedback signal and an external reference clock signal; and a control circuit, coupled between said phase detector and said DCO, for adjusting said DCO to align said internal feedback signal with said external reference clock signal in response to a detection of a phase difference between said internal feedback signal and said external reference clock signal, wherein said control circuit locks a modulation frequency of said DCO and monitors a state of said digital frequency multiplier circuit to maintain said lock, wherein said control circuit includes a counter for tracking state changes, and wherein said control circuit maintains the state of said digital frequency multiplier circuit by: determining whether a phase difference pulse representing the phase difference is detected, in response to detecting the phase difference pulse, the control circuit determining whether the detected phase difference pulse is a wide pulse including either a wide up pulse or a wide down pulse, wherein the wide pulse is generated when the phase detector detects a phase difference greater than a smallest increment of an output frequency of the DCO multiplied by a multiplier m, if the detected phase difference pulse is a wide pulse, updating the counter to indicate that the phase detector had last sent the wide up pulse or the wide down pulse to the counter, if the detected phase difference pulse in not a wide pulse, determining whether the phase detector had last sent either a first up pulse or a first down pulse to the counter, if the phase detector had last sent the first down pulse to the counter, determining whether the detected phase difference pulse is a second up pulse, in response to determining that the detected phase difference pulse is the second up pulse, updating the counter to show that the phase detector had last sent the first up pulse, if the phase detector had last sent the first up pulse to the counter, determining whether the detected phase difference pulse is a second down pulse, and in response to determining that the detected phase difference pulse is the second down pulse, updating the counter to show that the phase detector had last sent the first down pulse.