Patent ID: 7773356

Claim:
A protective circuit for a target circuit against an ESD event, the circuit comprising: the protective circuit having an anode and a cathode, the anode connected to a contact on the target circuit; the cathode connected to a reference contact on the circuit, wherein, when the protective circuit triggers due to the ESD event, the voltage between the contact and the reference contact on the target circuit is limited, thereby protecting the target circuit; a first PNP transistor with an emitter connected to the anode, a collector connected to the base of a first NPN transistor, and a base connected to the collector of the first NPN transistor; a first resistor connected from the anode to the base of the first PNP transistor; the emitter of the first NPN transistor connected to the emitter and the base of a second PNP transistor and to the collector of a second NPN transistor; the collector of the second PNP transistor connected to the base of the second NPN transistor, the emitter of the second NPN transistor connected to the cathode; a second resistor connecting the base of the second NPN transistor to the cathode; and a third resistor connecting the collector of the first NPN transistor to the collector of the second NPN transistor.