Patent ID: 7480190

Claim:
A circuit for indicating the program status of an EPROM comprising: a first transistor coupled to a first voltage potential; a second transistor coupled to the first voltage potential; a latching circuit coupled to the first transistor and the second transistor, wherein the latching circuit outputs a first output value when the current through the first transistor is greater than the current through the second transistor and outputs a second output value when the current through the first transistor is less than the current through the second transistor; a first capacitive element coupled between a gate of the first transistor and a third voltage potential, the capacitance of the first capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM, wherein the first digital state indicates that the EPROM has not been programmed and the second digital state indicates that the EPROM has been programmed; and a second capacitive element coupled between a gate of the second transistor and a fourth voltage potential, the capacitance of the second capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM.