Patent ID: 7501856

Claim:
A voltage level shifter, comprising: a pull-up circuit having a first PMOS transistor and a second PMOS transistor with source terminals thereof connected to a first voltage source; a path division circuit having a third PMOS transistor and fourth PMOS transistor with gates thereof connected to a second input voltage and a first input voltage, respectively, and with source terminals connected to drain terminals of the first PMOS transistor and second PMOS transistor, and with a drain terminal of the third PMOS transistor as a first output terminal and connected to a gate terminal of the second PMOS transistor and still a drain terminal of the fourth PMOS transistor as a second output terminal and connected to a gate terminal of the first PMOS transistor, and the second input voltage being an inverse signal of the first input voltage; a voltage drop circuit having a first NMOS transistor and a second NMOS transistor over a third NMOS transistor, and a fourth NMOS transistor, respectively, and the first NMOS transistor and the second NMOS transistor having source terminals connected to drain terminals of the third PMOS transistor and fourth PMOS transistor, respectively, the first second, third and fourth NMOS transistors being turned on; and a pull-down circuit having a fifth NMOS transistor and a sixth NMOS transistor with source terminals thereof grounded, the fifth NMOS transistor and sixth NMOS transistor having drain terminals connected to source terminals of the third NMOS transistor and fourth NMOS transistor, respectively, and having gates connected to the second input signal and first input signal, respectively.