Patent ID: 8250300

Claim:
A cache memory system, comprising a cache memory and a cache memory controller, wherein: the cache memory includes a plurality of storage locations, each storage location identified by a particular corresponding cache address and each storage location operable to store tag address portions during a first operation and data words during a second operation that is not simultaneous to the first operation, each data word corresponding to a respective tag address portion and wherein the tag address portion is different than the cache address; the cache memory controller is adapted to receive a first address and to access the cache memory based on the received first address, wherein the cache memory controller includes: a first address transformer adapted to receive the first address and to transform it into a first cache address corresponding thereto by applying a first transform function, the first cache address being used by the cache memory controller for accessing the cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations; a hit detector adapted to establish an at least partial hit condition based on a comparison of the retrieved at least a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer adapted to receive the first address and to transform it into at least one second cache address corresponding thereto by applying a second transform function, the cache memory controller being further adapted to use the at least one second cache address for accessing the cache memory to retrieve a data word corresponding to the retrieved tag address portion in case said at least partial hit condition is established.