Patent ID: 7831007

Claim:
A circuitry for improving the acquisition/locking time of phase-locked loops, comprising: a first switch for connecting with a node in a phase-locked loop where the node taps voltage from the phase-locked loop, the first switch configured to close when the phase-locked loop is in operation and to open when the phase-locked loop is powered down; an analog-to-digital converter (ADC) connected with the first switch for converting the voltage to a digital signal, the digital signal being a digital representation of the voltage; a memory module connected with the ADC to store the digital signal as a saved value; a digital-to-analog converter (DAC) connected with the memory module to convert the digital signal to an analog output; a second switch connected with and between the DAC and the node, the second switch configured to close for a period of time when the phase-locked loop is being powered-up and thereafter open, such that when the second switch is closed, the analog output is input through the node and into the phase-locked loop; and a comparator/threshold detector connected with and between the first switch, the second switch, and the memory module, the comparator/threshold detector being configured to compare the voltage from the first switch to the analog output from the DAC, and based on the comparison, to provide a signal to the memory module to cause the memory module to update its stored digital signal, such that the circuitry can update its digital representation of the voltage in the phase-locked loop such that when the phase-locked loop is powered-down, the digital representation of the voltage is stored in the memory module, and when the phase-locked loop is powering-up, the digital representation is converted into an analog signal that is output into the phase-locked loop to force the node in the phase-locked loop to the saved values as an initial condition during power-up procedures, thereby decreasing acquisition time in the phased locked loop.