Patent ID: 6975527

Claim:
A semiconductor die for connection to a metallization layer, comprising: a plurality of memory array groups, each memory array group having at least two memory array units, each said memory array unit comprising at least two memory arrays; two channels associated with each said memory array group, wherein each said channel is coupled to a different memory array unit and positioned between at least two said memory arrays of said memory array unit, and wherein each said channel defines a boundary line parallel to an outer edge of each said channel and extending to an edge of the die; and a plurality of conductive pads coupled to each said channel, wherein said conductive pads associated with each said memory array group are positioned such that greater than half of each conductive pad's surface area is located within a region of said semiconductor die that is external to an edge of said memory array and further circumscribed by said boundary lines, a first subset of the conductive pads being connected by bond wires to external leads in a first memory array configuration and not connected to any of the external leads in a second memory array configuration.