Patent ID: 8264443

Claim:
A gate driving circuit comprising stages, the stages being cascaded with each other and each comprising: a pull-up part which pulls up a gate voltage to a clock signal in response to a control voltage of a control terminal (Q-node) of the pull-up part during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal in response to the control voltage of the Q-node during the horizontal scanning period (1H), the Q-node being connected to a control electrode of the carry part; a pull-up driving part connected to the Q-node common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage and outputs the control voltage to the Q-node; and a ripple preventing part that includes a control electrode directly connected to the Q-node common to the carry part and the pull-up part, wherein the ripple preventing part prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.