Patent ID: 8195881

Claim:
A multi-level hierarchical memory system comprising: a processor configured to perform a method comprising: receiving a request for data in a multi-level hierarchical memory system that includes at least one level of cache as a primary cache, the request including a virtual address for accessing the data; querying a translation unit to obtain the absolute address corresponding to the virtual address, the translation unit configured to perform a multi-cycle translation process that generates a warning signal when the translation process is near completion, and that generates a done signal when the translation process is complete; performing a directory lookup, the directory lookup including a priority cycle set-up phase that is initiated in response to the warning signal being generated, and an execution phase that is initiated in response to the done signal being generated and upon obtaining the absolute address to determine whether a matching absolute address exists in a directory indicating that a line is available in the primary cache for accessing the requested data; sending a fetch request for the requested data to a next level in the multi-level hierarchical memory system above the primary cache, wherein at least a portion of processing of the fetch request by the next level in the multi-level hierarchical memory system occurs in parallel with the execution phase of the directory lookup; and receiving the requested data from the next level in the hierarchical memory system.