Patent ID: 7166901

Claim:
A semiconductor device comprising: a semiconductor substrate; a first well and a second well formed on the semiconductor substrate; a plurality of high voltage MOS transistors formed in the first well; a plurality of low voltage MOS transistors having gate lengths in a sub-micron order, the low voltage MOS transistors being formed in the second well; a first shallow trench isolation comprised of a first shallow trench disposed as an element isolator on a surface of a low voltage region of the semiconductor substrate on which the low voltage MOS transistors are formed, and a first dielectric embedded in the first shallow trench; a second shallow trench isolation comprised of two second shallow trenches disposed at an interval between a source region or a drain region of a first of the high voltage MOS transistors and a source or a drain region of a second of the high voltage MOS transistors as element isolators on a surface of a high voltage region of the semiconductor substrate on which the plurality of high voltage MOS transistors are formed, and a second dielectric embedded in each of the second shallow trenches; and a first channel cut region having a high impurity concentration disposed on the surface of the substrate between the two second shallow trenches of the second shallow trench isolation.