Patent ID: 7834796

Claim:
An analog-to-digital converter (ADC) comprising: an input switch; an array of binary-weighted capacitors configured to receive an input voltage signal via the input switch in an on-state of the input switch; a plurality of switches coupled in series with respective ones of the capacitors at an opposite side of the respective capacitor compared to the input switch, wherein the switches are configured to have respective first switching states in which the switches are coupled to a reference voltage (V DD ) and at least respective second switching states in which the switches are coupled to ground; a comparator having a first input configured to receive a voltage from the input switch side of the array of capacitors and a second input configured to receive a voltage signal about half of the reference voltage (V DD /2); and a successive approximation register (SAR) coupled to an output of the comparator and configured to control the input switch and the plurality of switches based at least in part on the output from the comparator; wherein the input switch is configured to be in the on-state longer than an amount of time the input switch is in an off-state to reduce an error rate of an analog-to-digital conversion of the input voltage signal.