Patent ID: 7286437

Claim:
A memory array in an integrated circuit comprising an array of dual-port memory cells arranged in rows and columns, each cell being connected to a read word line and at least one read bitline and a write word line and at least one write bitline; a read circuit connected to said at least one read bitline and a driver circuit connected to said at least one write bitline; in which said at least one read bitline comprises two read bitlines disposed along columns in at least two sections of said memory array, said read lines in said at least two sections having opposite senses of reception of electromagnetic radiation, whereby said read circuit receives common mode noise from said at least one write bitline; and said at least one write bitline comprises two write bitlines disposed in at least two sections of said memory array, said at least two sections having opposite senses of transmission of electric current, whereby said read circuit receives a reduced differential mode noise from said write bitline.