Patent ID: 7196932

Claim:
A nonvolatile semiconductor memory comprising: a first NAND string line including first memory cells connected in series and first select transistors connected to both ends of the first memory cells, respectively; a second NAND string line including second memory cells connected in series and second select transistors connected to both ends of the second memory cells, respectively; a first bit line which is connected to the first NAND string line; a second bit line which is connected to the second NAND string line, and which is different from the first bit line; and a common latch circuit having a common node connected to one end of each of the first and second bit lines, wherein the first program/read data of one of the first memory cells is latched in the common latch circuit, while second program/read data of one of the second memory cells is held by the second bit line, and wherein the first and second NAND string lines are provided in different banks.