Patent ID: 7205196

Claim:
A method for fabricating an integrated circuit comprising: forming a first oxide layer on a semiconductor material having at least one trench; forming a polysilicon layer on said first oxide layer, wherein said polysilicon layer includes a polysilicon layer portion of a trench area and a polysilicon layer portion of a planar area; and etching a part of said polysilicon layer so as to form a gate of a trench device in said trench area and a polysilicon layer of a planar device in said planar area simultaneously; and wherein before etching said part of said polysilicon layer said method further comprises: implanting a first dopant into said polysilicon layer portion of said trench area; and covering said polysilicon layer portion of said planar area with a mask layer; and wherein said first dopant is inplanted into said polysilicon layer portion of said trench area by an ion implantation; and wherein said ion implantation is performed by heating and diffusing.