Patent ID: 8004310

Claim:
A power supply regulation system comprising: a power transistor having a source connected to a first terminal of a power supply and a drain connected to a first power input terminal of a load, a connection between a second terminal of the power supply and a second power input terminal of the load; a transmission gate having a signal input that receives an on/off power control signal (DS), a first control input that receives a full/reduced power control signal (LS), a second control input that receives a complement (LS-bar) of the full/reduced power control signal, and an output connected to the gate of the power transistor; and a switching transistor having a source connected to a gate of the power transistor, a drain connected to the drain of the power transistor, and a gate connected to receive the complement of the full/reduced power control signal, whereby, when the full/reduced power control signal assumes a logic level corresponding with full power control, the transmission gate couples the on/off power control signal to the gate of the power transistor and the switching transistor is switched off, and when the full/reduced power control signal assumes a logic level corresponding with reduced power, the transmission gate output goes to a high-impedance state and the switching transistor causes the power transistor to enter a resistive state that conducts reduced power from the power supply to the load.