Patent ID: 8005179

Claim:
A preamble detector having: a plurality of preamble processors, each preamble processor having: a preamble processor input coupled to a first delay and producing an output; a second delay generating an output and having an input coupled to said first delay output; a first multiplier coupled to a conjugated output of said second delay and to said first delay output, thereby generating a first multiplier output; a second multiplier coupled to a conjugated output of said first delay and to said preamble processor input, thereby generating a second multiplier output; a subtractor forming the difference between said first multiplier output and said second multiplier output, said subtractor thereby forming an output substantially equal to the sum of m previous first multiplier output values; said subtractor coupled to a magnitude generator for producing a magnitude substantially equal to the magnitude of the real and imaginary parts of said accumulator output, thereby generating a preamble processor output; a summer for accepting said preamble processor outputs and forming a preamble detector sum; a comparator coupled to said summer and generating an output when said summer output exceeds a threshold value.