Patent ID: 7026678

Claim:
Dynamic random access memory circuitry comprising: a semiconductor substrate; word lines received over the semiconductor substrate; digit fines received over the word lines; an insulative layer received over the word lines, the digit lines and the substrate, the insulative layer having at least one well formed therein, the well comprising a substantially planar base received over the word lines and the digit lines, the well base comprising a thin layer of insulative material; the well peripherally defining an outline of a memory array area, area peripheral to the well comprising memory peripheral circuitry area; a plurality of memory cell storage capacitors received within the well, the memory cell storage capacitors of the plurality of memory cell storage capacitors comprising a storage node containers which are partially received within the insulative layer, and which extend through the thin layer of insulative material of the well base; and peripheral circuitry within the peripheral circuitry area operatively configured to write to and read from the memory array.