Patent ID: 6957375

Claim:
A device for performing an LDPC processing operation, the device comprising: a memory for storing a plurality of Z element vectors, each Z element vector including Z elements, each element including at least one bit to be processed; a parallel LDPC processing module including Z processing element arranged to operate in parallel; and a controllable factorable permuter for coupling said memory to said parallel LDPC processing module, said controllable factorable permuter including switching circuitry, said switching circuitry being responsive to a control signal to perform a factorable permutation operation on a Z element vector being passed through said factorable permuter, said factorable permutation operation including first and second permutation operations which cause first and second re-orderings of vector elements to occur, one of said first and second reordering operations being performed on n equally sized vector portions to cause a change in ordering of the elements in each of the n equally sized portions and the other one of the first and second permutation operations being performed on another size portion which is larger than any one of said n equally sized vector portions to cause a change in said another size portion, where n is an integer greater than 1.