Patent ID: 8060716

Claim:
An information processing device that performs operations by switching between a first processing relating to information that needs to be protected and a second processing that is different than the first processing, the information processing device comprising: a secure memory operable to store therein the information that needs to be protected; a plurality of processors, each of the plurality of processors being operable to operate in accordance with a program; a bus that connects the plurality of processors with each other; and a control unit operable to, (i) during a first period for performing the first processing, permit at least one of the plurality of processors to access the secure memory via the bus, and perform one of (a) stopping operations of the others of the plurality of processors and (b) prohibiting the others of the plurality of processors from accessing the secure memory via the bus, and (ii) during a second period for performing the second processing, prohibit all of the plurality of processors from accessing the secure memory via the bus, wherein the control unit includes: a connection/disconnection subunit operable to connect the secure memory with the bus during the first period, and disconnect the secure memory from the bus during the second period; and an access control subunit operable to, during the first period, permit the at least one processor to access the secure memory, and stop the operations of the others of the plurality of processors, wherein the access control subunit stops the operations of the others of the plurality of processors by continually outputting reset signals to the others of the plurality of processors, and wherein the information processing device further comprises a switch unit operable to switch a reference destination address to be referred to by the at least one processor from another memory that is different than the secure memory to the secure memory, by designating, as an available interrupt vector, a first interrupt vector including an address that indicates a position within the secure memory instead of a second interrupt vector including an address that indicates a position within the other memory.