Patent ID: 7924071

Claim:
A synchronization detection circuit comprising: a multiphase clock generation circuit which comprises a phase locked loop circuit that generates multiphase clock signals having a plurality of different phases, based on a reference clock signal, and which generates high-speed multiphase clock signals having a frequency obtained by multiplying a frequency of the reference clock signal, and low-speed multiphase clock signals having a frequency obtained by dividing a frequency of the high-speed multiphase clock signals; and a synchronous clock specifying circuit that specifies a clock signal synchronized with a synchronous signal from among the multiphase clock signals, and generates a synchronous position signal indicating a synchronous position of the synchronous signal, based on a comparison result between the synchronous signal and the high-speed multiphase clock signals and a comparison result between the synchronous signal and representative clock signals selected from the low-speed multiphase clock signals.