Patent ID: 8593859

Claim:
A semiconductor device receiving a first power supply voltage, comprising: a first voltage generation circuit driven by said first power supply voltage and generating a second power supply voltage; a second voltage generation circuit driven by said first power supply voltage and generating a third power supply voltage; a plurality of memory cells provided in rows and columns and driven by said second power supply voltage; a plurality of word lines provided to correspond to the rows of said plurality of memory cells, respectively; a plurality of word line drivers provided to correspond to said plurality of word lines, respectively, each word line driver being driven by said third power supply voltage and connected to the corresponding word line; a plurality of first switches provided to correspond to said plurality of word lines, respectively, each first switch being connected between a corresponding one of the word lines and a reference node providing a reference voltage and brought into a conductive state in response to a control signal; a second switch brought into a non-conductive state in response to the control signal and connected to said second voltage generation circuit for supplying said third power supply voltage to said plurality of word line drivers in a conductive state of said second switch; a row decoder driven by said third power supply voltage, receiving a row address and providing a row select signal to a word line driver, which brings a word line identified by the row address into an active state, among said plurality of word line drivers; and a control circuit driven by said first power supply voltage and generating said control signal based on a signal identifying a standby mode of said semiconductor device, said control circuit further controlling said second voltage generation circuit to halt supply of said third power supply voltage based on the signal identifying said standby mode.