Patent ID: 7535745

Claim:
A ferroelectric memory device comprising: an MIS transistor formed on a substrate; and a ferroelectric capacitor formed on an interlevel insulator above the MIS transistor, and including a first electrode and a second electrode separated by a ferroelectric film in-between, wherein the first and second electrodes are vertically disposed to face each other in a channel length direction of the MIS transistor and each consists of a single part; wherein the transistor and the ferroelectric capacitor are electrically connected in parallel to each other and constitute a single memory cell, the first electrode of the ferroelectric capacitor is connected with one source/drain of the MIS transistor by a first contact plug alone, the second electrode is connected with the other source/drain of the MIS transistor by a second contact plug alone, and the first and second contact plugs have the same dimension, wherein a distance between the first and second electrodes of the ferroelectric capacitor is smaller than a gate length of the MIS transistor.