Patent ID: 7038936

Claim:
A reading circuit for reading a memory cell having a single bit line and a corresponding reference cell, comprising: a first and second cascode circuit ( 24 ; 25 ) each having an input terminal ( 24 a ; 25 a ) and two output terminals ( 24 b , 24 c ; 25 b , 25 c ) respectively said input terminals ( 24 , 25 ) being adapted to be connected to a bit line of said memory cell and a corresponding reference bit line of said reference cell, respectively, a first and second current mirror circuit ( 26 , 27 ) having a first and second terminal ( 26 a , 26 b ; 27 a , 27 b ), respectively, wherein said first terminal ( 26 a ) of said first current mirror circuit ( 26 ) is coupled to said first output terminal ( 24 b ) of said first cascode circuit ( 24 ) and said second terminal ( 26 b ) of said first current mirror circuit ( 26 ) is coupled to said second output terminal ( 25 c ) of said second cascode circuit ( 25 ), wherein said first terminal ( 27 a ) of said second current mirror circuit ( 27 ) is coupled to said first output terminal ( 25 b ) of said second cascode circuit ( 25 ) and said second terminal ( 27 b ) of said second current mirror circuit ( 27 ) is coupled to said second output terminal ( 24 c ) of said first cascode circuit ( 24 ); and a tri-state buffer ( 28 ) coupled between the second terminals ( 26 b , 27 b ) of said first and second current mirror circuits ( 26 , 27 ), wherein said tri-state buffer ( 28 ) having bit invert capabilities.