Patent ID: 8230176

Claim:
A method, in a data processing system for reconfigurable cache size of a cache comprising a plurality of cache blocks, the method comprising: configuring a cache controller to use a first address decoder to access a first cache partition having a first size using a first routing structure, wherein the first cache partition comprises a first set of cache blocks, wherein the first set of cache blocks is a subset of the plurality of cache blocks, wherein the address decoder accesses each cache block in the first subset of cache blocks by traversing a first number of segments of the first routing structure; and responsive to an event, reconfiguring the cache controller to use a second address decoder to access a second cache partition having a second size using a second routing structure, wherein the second cache partition comprise a second subset of cache blocks, wherein the first set of cache blocks is a subset of the second set of cache blocks, wherein the second address decoder accesses each cache block in the second subset of cache blocks by traversing a second number of segments of the first routing structure, wherein the second number is greater than the first number.