Patent ID: 7203143

Claim:
A slew rate limiter comprises: a MOS transistor to the gate of which an input signal is inputted; a first current source connected to the source of said MOS transistor in series with said MOS transistor; a second current source connected to the drain of said MOS transistor in series with said MOS transistor; and a capacitor connected between the source of said MOS transistor and a reference potential, characterized in that, upon an increase in a wave form of said input signal, an output voltage of said MOS transistor increases with a slew rate which is determined by a difference between a current value of said first current source and a current value of said second current source, and a capacitance value of said capacitor, and upon a decrease in the wave form of said input signal, the output voltage of said MOS transistor decreases with a slew rate which is determined by the current value of said first current source and the capacitance value of said capacitor.