Patent ID: 7082063

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells coupled to the plurality of word lines and the plurality of bit lines so that one memory cell is coupled to one word line and one bit lines, wherein the plurality of memory cells stores information therein and each of which needs a first operation to hold the information stored therein; a row address decoder which receives row address signals and which selects one of plurality of word lines in accordance with the row address signals; a row address transition detector which receives the row address signals to detect a transition of the row address signals; a column address decoder which receives column address signals (and which selects one of the plurality of bit lines in accordance with the column address signals; a column address transition detector which receives the column address signals to detect a transition of the column address signals; and a timer which instructs the first operation to the plurality of memory cells in accordance with information holding capability of the plurality of memory cells, wherein the column address transition detector instructs a second operation which selects bit lines continuously to the column address decoder when the row address signals are constant and the column address signals are changed, and wherein the first operation is executed autonomously before or after a memory operation which is a reading operation for outputting the information from the memory cells or a writing operation for inputting the information to the memory cells each of which are different from the first operation.