Patent ID: 8759219

Claim:
A planarization method applied in a process of manufacturing a semiconductor component, comprising: providing a substrate; forming a dielectric layer above the substrate, the dielectric layer defining a trench therein; forming a barrier layer and a metal layer on the dielectric layer in sequence and filled in the trench; applying a first planarization process to the metal layer by using a first reactant so that a portion of the metal layer is removed to expose a portion of the barrier layer, an etching rate of the first reactant to the metal layer being greater than an etching rate of the first reactant to the barrier layer; and applying a second planarization process to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and a portion of the metal layer are removed to expose the dielectric layer, an etching rate of the second reactant to the barrier layer being greater than an etching rate of the second reactant to the metal layer; wherein the first planarization process is a first chemical mechanical polishing process, the second planarization process is a second chemical mechanical polishing process, the first reactant is a first chemical mechanical polishing slurry, the second reactant is a second chemical mechanical polishing slurry, each of the first chemical mechanical polishing slurry and the second chemical mechanical polishing slurry includes an oxidizer, and a concentration of the oxidizer of the first chemical mechanical polishing slurry is less than a concentration of the oxidizer of the second chemical mechanical polishing slurry.