Patent ID: 7111110

Claim:
A programmable logic device having a versatile Random Access Memory (RAM), the device comprising: a logic array block comprising: a plurality of multiplexers that drive output signals from the logic array block onto a plurality of global routing lines, wherein a selected portion of the global routing lines are adapted for transmitting output signals from the logic array block into the RAM, wherein the RAM comprises a plurality of memory blocks, wherein each of the memory blocks is associated with a decoder, and wherein each decoder that detects a unique pattern on at least one of the selected portion of the global routing lines enables a tri-state-driver that drives the output of the memory block associated with the decoder onto the at least one global routing line; a logic element comprising a plurality of inputs; a plurality of signal lines that: in a first configuration of the programmable logic device, provide address signals that, at least in part, specify a location in the RAM, the location that is adapted to be either written to or read from; and in a second configuration of the programmable logic device, provide a plurality of input signals to the inputs of the logic element.