Patent ID: 7685356

Claim:
A memory controller for controlling access to a flash memory in which stored data is erased in units of physical blocks, according to information supplied from a host system, the memory controller comprising: address administering means for administering a correspondence relation between logical addresses supplied from the host system and physical addresses in the flash memory; identification information generating means for generating a plurality of chronological identification information which is information to discriminate a chronological relation of a plurality of physical blocks storing data in an identical scope of logical addresses and which is information including a plurality of cyclic numbers each having priority; writing means for writing in a physical block in which data supplied from the host system is written, the chronological identification information corresponding to the data written in the physical block; reading means for reading the chronological identification information written by the writing means; and chronology determining means for determining, when there are the plurality of physical blocks storing data in an identical scope of logical addresses, the chronological relation of the plurality of physical blocks, based on the chronological identification information; wherein the chronology determining means determines the chronological relation of the plurality of the physical blocks by comparing the plurality of chronological identification information corresponding to the plurality of physical blocks; wherein in comparison of the plurality of chronological identification information, the cyclic numbers with an identical priority included in the plurality of chronological identification information are compared in order from the highest priority to the lowest priority; and wherein the chronological identification information is generated as follows: when cyclic numbers included in the plurality of chronological identification information are compared at each priority, cyclic numbers as comparison targets at each priority become cyclic numbers in an identical stage in a cycle order or cyclic numbers one stage different in the cycle order.