Patent ID: 7613969

Claim:
A method, comprising: operating a tester to assert a scan-enable signal; asserting the scan enable signal to an inactive value during a scan data capture cycle, wherein the inactive value is equivalent to a logic low; pulsing a clock signal during the capture cycle; asserting the scan enable signal to an active value during a shift scan cycle, wherein the active value is equivalent to a logic high; locking scan data into a first master latch of a negative-edge triggered scan register having the first master latch and a first slave latch when the clock signal has a falling edge; asserting the scan enable signal to the inactive value; transferring the scan data from the first master latch to the first slave latch to compensate for clock skew; asserting the scan enable signal to the active value; locking the scan data into a second master latch of a positive-edge triggered scan register having the second master latch and a second slave latch when the clock signal has a rising edge; and asserting the scan enable signal to the inactive value; and transferring the scan data from the second master latch to the second slave latch to compensate for clock skew.