Patent ID: 6995084

Claim:
A method for forming an interconnect structure for a semiconductor device, the method comprising: defining a via in passivation layer so as expose a top metal layer in the semiconductor device; forming a seed layer over said passivation layer, sidewalls of said via, and said top metal layer; forming a barrier layer over an exposed portion of said seed layer, said exposed portion defined by, a first patterned opening; annealing the semiconductor device so as to cause atoms from said barrier layer to diffuse into said seed layer thereunderneath; and following said annealing, forming a solder material over said barrier layer using a second patterned opening; wherein said annealing causes diffused regions of said seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of said seed layer, and wherein said second patterned opening is configured so as to have a lager diameter than said first patterned opening.