Patent ID: 6985395

Claim:
A semiconductor memory device comprising: a memory cell array including memory cells arranged in rows and columns; a word line connected in common to memory cells in each of rows of the memory cell array; a bit line connected in common to memory cells in each of columns of the memory cell array; a row decoder and a column decoder configured to select a row and a column of the memory cell array; a sense amplifier provided for each of the columns of the memory cell array; a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode; a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode; a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit; and a first comparison result register configured to store a comparison result of the first comparison circuit.