Patent ID: 8041856

Claim:
A first in and first out (FIFO) buffer system, comprising: a storage device for storing data; a write pointer for pointing to a write address of the storage device for a write operation; a read pointer for pointing to a read address of the storage device for a read operation; and a control logic for incrementing the read pointer based on a skip parameter of a skip register, wherein the skip parameter is used to characterize a validity of the data for the read operation, and wherein the skip register is a configurable register which enables skipping a number of locations for a read operation, wherein the control logic comprises a skip based control logic circuit for: setting a current location of the read pointer to a current location of the write pointer if a value of the skip parameter is greater than zero and a data count of the data; decreasing the value of the skip parameter by the data count; and, setting the data count to zero.