Patent ID: 7764540

Claim:
A semiconductor memory device including a memory array portion having a plurality of memory cells (MC) arranged in a matrix, charge line (CL), word line (WL) and bit lines (BL), in which each of said plurality of memory cells has an access transistor (ATr) and a storage transistor (STr) connected in series between said one of bit lines (BL) and a power source potential (VDD), the gate of said storage transistor (STr) is connected to said charge line (CL) and the gate of said access transistor (ATr) is connected to said word line (WL), said storage transistor (STr) and said access transistor (ATr) are isolated electrically from other adjoining memory cells (MC), by switching the potential of a connection node of said storage transistor (STr) and said access transistor (ATr) to a constant potential or a floating condition by turning ON/OFF said access transistor (ATr), the potential of a body region ( 23 b ) of said storage transistor (STr) is set to a high level or a low level so as to memorize binary data, wherein by activating said word line (WL) and said one of bit lines (BL) in parallel with said storage transistor (STr) set to OFF, the potential conditions of said charge line (CL), said word line (WL) and said one of bit lines (BL) are controlled so that the potential of said body region ( 23 b ) is raised by a leak current flowing from a drain side toward said body region ( 23 b ) in a period until said storage transistor (STr) is turned ON.