Patent ID: 8395940

Claim:
A page buffer circuit, comprising: a bit line selection unit coupled to first and second bit lines, and configured to select the first or second bit line in response to a first control signal and to couple the selected bit line to a sense node, or to selectively precharge the first and second bit lines to a first voltage level or discharge the first and second bit lines to a ground voltage level; a first latch unit configured to store program data and change a voltage level of the sense node according to the stored program data; a second latch unit configured to store data of a low logic level in response to a reset signal and discharge a selected bit line from a precharge state with the first voltage level to a second voltage level higher than the ground voltage level; and a voltage control element configured to raise a voltage level of the sense node or drop the voltage level of the sense node to a third voltage level lower than the second voltage level in response to a second control signal.