Patent ID: 7179732

Claim:
A method of fabricating an interconnection structure, the method comprising steps of: forming a first organic low-k material layer over a substrate; forming a stress redistribution layer on the first organic low-k material layer; forming a second organic low-k material layer on the stress redistribution layer; forming an a dual darnascene opening comprising a via opening and a trench in the first organic low-k materiallayer, the stress redistribution layer and the second organic low-k material layer, wherein the via opening passes through the first organic low-k material layer, the stress redistribution layer and a portion of the second organic low-k material layer, and the trench passes througji the other portion of the second organic low-k material layer; and filling the dual damascene opening with a conductive material for forming an interconnection; wherein the stress redistribution layer having a heat expansion coefficient close to that of the substrate, and the heat coefficient differs significantly from those of the first and second organic low-k material layers.