Patent ID: 7245554

Claim:
An integrated semiconductor memory device with clock-synchronous access control, comprising: an internal terminal that generates an internal clock signal, wherein read and write accesses are controlled clock-synchronously with the internal clock signal; a first input amplifier to amplify a level of a first input signal, the first input amplifier including an input terminal to apply the first input signal and an output terminal to generate a first output signal; a second input amplifier to amplify a level of a second input signal, the second input amplifier including an input terminal to apply the second input signal and an output terminal to generate a second output signal, wherein the first input amplifier is configured to generate a level of the first output signal in a manner dependent on the level of the first input signal, the second input amplifier is configured to generate a level of the second output signal in a manner dependent on the level of the second input signal, and the first input amplifier is configured to amplify the first input signal up to a first limiting frequency and the second input amplifier is configured to amplify the second input signal up to a second limiting frequency, the first limiting frequency being lower than the second limiting frequency; a controllable switch that selectively connects each of the output terminal of the first input amplifier and the output terminal of the second input amplifier to the internal terminal that generates the internal clock signal; wherein the output terminal of the second input amplifier is connected via the controllable switch to the internal terminal that generates the internal clock signal when the input terminal of the second input amplifier is driven by the second input signal, otherwise the output terminal of the first input amplifier is connected via the controllable switch to the internal terminal that generates the internal clock signal.