Patent ID: 8737132

Claim:
In a non-volatile memory circuit having non-volatile memory cells formed along a plurality of bit lines and a plurality of word lines according to a NAND type architecture, a method of programming the memory cells along a selected word line comprising: individually biasing the bit lines to one of a plurality of values, including a program inhibit level and a program enable level; biasing a common source line for the bit lines to a first non-zero voltage level; and applying a series of a plurality of programming pulses to the selected word line while the bit lines and common source line are so biased, wherein the series of programming pulses are applied without intervening verify operations, wherein the common source line is maintained at the first non-zero voltage level between the individual pulses of the series of programming pulses, and wherein bit lines biased at the program inhibit level are maintained at the program inhibit level between the individual pulses of the series of programming pulses.