Patent ID: 7633414

Claim:
A Manchester decoder circuit, the circuit comprising: a first circuit node for receiving a preamble found signal, a second circuit node for receiving a data input signal, and a third circuit node for receiving a recovered clock signal; a first flip-flop configured to store a phase of the data input signal responsive to the preamble found signal and the recovered clock signal and output the stored phase; a second flip-flop configured to alternate state responsive to the preamble found signal and the recovered clock signal and output a decision time signal; a third flip-flop configured to store a switch pulse signal responsive to the recovered clock signal and the switch pulse signal and output the stored switch pulse signal; first combinational logic configured to assert the switch pulse signal when the stored switch pulse signal is cleared, the decision time signal is active, and the stored phase of the data signal is the same logic value as a current phase of the data signal; a fourth flip-flop configured to decode a decision pair of phases of the data input signal responsive to the recovered clock signal, the preamble found signal and the decision time signal and output a data output signal; and second combinational logic configured to select the stored phase and current phase of the data input signal as the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and to select the stored phase and an inverted stored phase as the decision pair when either the switch pulse signal or stored switch pulse signal are asserted.