Patent ID: 7893478

Claim:
A semiconductor storage device having plural memory cells arranged in a two dimensional matrix and operationally related to word lines and bit lines which extend in first and second intersecting directions, comprising: a semiconductor substrate; an insulation layer provided on the semiconductor substrate; a semiconductor layer provided on the insulation layer; each memory cell including, a source layer provided in the semiconductor layer, a drain layer provided in the semiconductor layer, and a body provided in the semiconductor layer between the source layer and the drain layer, the body being in an electrically floating state, and accumulating or emitting a charge to store data; an emitter layer contacting the source layer, the emitter layer having an opposite conductive type to the source layer; a respective word line being provided to memory cells arrayed in the first direction; a source line connected to the source layers of the memory cells arrayed in the first direction; and a respective bit line connected to the drain layers of the memory cells arrayed in the second direction intersecting the first direction.