Patent ID: 7412554

Claim:
An apparatus to provide card-to-card communication in a computing system, comprising: a bus interface controller to manage a set of serial data lanes; said bus interface controller having a first mode of operation in which said set of serial data lanes is managed as a full bus and a second mode of operation in which a first subset of said serial data lanes is managed as one bus and a second subset of said serial data lanes is managed as a private bus the one bus coupling a first graphics processing unit (GPU) to a second GPU via a chipset with the private bus providing another data pathway between the first and second GPUs; and a reorder module to reorder data received via said private bus in said second mode of operation into a semantic order, said reorder module accounting for differences in data latency between a plurality of different data pathways in said second mode of operation associated with utilizing both said one bus and said private bus for communication between said first and second GPUs.