Patent ID: 8299469

Claim:
A thin film transistor (TFT) array panel, comprising: at least one gate line and at least one data line insulated from each other on an insulating substrate; at least two pixel electrodes; at least one thin film transistor (TFT) including a gate electrode, a source electrode and a drain electrode respectively, wherein the gate electrode is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to one of the pixel electrodes; and a capacitive electrode, at least a portion of the capacitive electrode overlapping the data line, wherein the capacitive electrode overlaps the pixel electrodes, and the capacitive electrode is without an opening or a slit facing the data line; and an ohmic contact layer disposed between the data line and the capacitive electrode, wherein a width of the ohmic contact layer is larger than a width of the data line; wherein one of the pixel electrodes is disposed in a first pixel region and another one of the pixel electrodes is disposed in a second pixel region.