Patent ID: 8370587

Claim:
A memory system comprising: an interface unit coupled to a host apparatus; a volatile first storing unit configured to store status information for notification to the host apparatus and address translation information; a nonvolatile second storing unit configured to store update information of the status information and the address translation information; and a controller including: a first management unit that controls data transfer between the host apparatus and the first storing unit via the interface unit and that manages the status information, and a second management unit that controls data transfer between the first storing unit and the second storing unit and that manages the address translation information; wherein the first management unit includes: an information writing unit that updates the status information according to a status of the memory system, an update information managing unit that manages update information indicating an updated section of the status information updated by the information writing unit, and an update information notifying unit that notifies the second management unit of the update information managed by the update information managing unit; the second management unit includes: an information controlling unit that updates the address translation table and that stores first difference information of the address translation information in the first storing unit; and a commit executing unit that collects, based on the update information, second difference information of the status information from the first storing unit when the update information is notified from the update information notifying unit, and accumulates the first and second difference information in the second storing unit.