Patent ID: 7962695

Claim:
A method of integrating a hybrid architecture in a set associative cache, the cache having a first type of memory structure used to implement one or more ways in each congruence class of the cache, and a second type of memory structure used to implement the remaining ways of the congruence class, the method comprising: upon a memory access request, determining whether the access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether the least recently used (LRU) way of the first type memory structure is also the LRU way of the entire congruence class, and in the event the LRU way of the first type memory structure is not the LRU way of the entire congruence class, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and further, in the event of a cache miss, filling the LRU way of the first type memory structure with a new cache line in accordance with the memory access request; and regardless of a cache hit or miss, updating LRU bits, depending upon the results of the memory access request.