Patent ID: 7304631

Claim:
A display driver circuit which drives signal electrodes of a display device based on gray-scale data, comprising: first to (M+N)th (M and N are positive integers) shift register blocks; a data input control circuit which controls input of the gray-scale data supplied to the first to (M+N)th shift register blocks; first to (M+N)th data mask circuits which generate first to (M+N)th gray-scale data by performing mask control for the gray-scale data supplied to the first to (M+N)th shift register blocks and output the first to (M+N)th gray-scale data; first to (M+N)th data mask control circuits which generate first to (M+N)th data mask control signals for performing mask control for the first to (M+N)th gray-scale data; and a signal electrode driver circuit which drives the signal electrodes by using drive voltages corresponding to the first to (M+N)th gray-scale data, the first to (M+N)th gray-scale data being held in the first to (M+N)th shift register blocks, wherein the first to Mth shift register blocks are disposed in a region on a first direction side of the data input control circuit, shift a given data enable signal input to the first shift register block and output the shifted data enable signal to a shift register block adjacent in a second direction opposite to the first direction, and hold the first to Mth gray-scale data based on the shifted data enable signal, wherein the (M+1)th to (M+N)th shift register blocks are disposed in a region on the second direction side of the data input control circuit, shift a data enable signal input to the (M+1)th shift register block from the Mth shift register block and output the shifted data enable signal to a shift register block adjacent in the second direction, and hold the (M+1)th to (M+N)th gray-scale data based on the shifted data enable signal, wherein the first to Mth data mask circuits are connected in the second direction in order from the first to Mth data mask circuit and mask the first to Mth gray-scale data in order from the first to Mth data mask circuit, wherein the (M+1)th to (M+N)th data mask circuits are connected in the second direction in order from the (M+1)th to (M+N)th data mask circuit and unmask the (M+1)th to (M+N)th gray-scale data in order from the (M+1)th to (M+N)th data mask circuit, wherein an ath (1≦a≦M; a is an integer) data mask control circuit generates an ath data mask control signal based on a data enable signal output from an ath shift register block and an ath data mask circuit masks an ath gray-scale data based on the ath data mask control signal, and wherein a bth (M+1≦b≦M+N; b is an integer) data mask control circuit generates a bth data mask control signal based on a data enable signal output from a (b-1)th shift register block and a bth data mask circuit masks a bth gray-scale data based on the bth data mask control signal.