Patent ID: 7741630

Claim:
An integrated circuit, comprising: a buried gate select transistor comprising a source region and a drain region; and a resistive memory element coupled to the buried gate select transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer; a common line; wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element; and wherein the source region of the buried gate select transistor is in direct physical contact to the common line wherein the buried gate select transistor comprises: a recess formed in an active area of a substrate, the active area comprising a source region and a drain region, the recess located between the source region and the drain region; a gate oxide layer lining the recess; and a gate comprising a conductive material at least partially filling the recess.