Patent ID: 7984212

Claim:
A system for utilizing peripheral first-in-first-out (FIFO) resources, comprising: a processor; a first peripheral FIFO controller coupled to the processor and a first peripheral device for controlling a buffering of first data associated with the processor; a second peripheral FIFO controller coupled to the processor and a second peripheral device for controlling a buffering of second data associated with the processor; a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller; a first FIFO coupled to the merge module via a first FIFO channel; and a second FIFO coupled to the merge module via a second FIFO channel, wherein the merge module merges the first FIFO channel associated with the first peripheral FIFO controller and the second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel, and wherein the merge module merges the first FIFO channel and the second FIFO channel if only one of the first FIFO channel and the second FIFO channel is an active FIFO channel.