Patent ID: 8832627

Claim:
An integrated circuit for routing an asynchronous signal, said integrated circuit comprising: a clock signal distributed within said integrated circuit via a clock distribution network; a plurality of destination storage elements clocked by said clock signal, said clock signal having a clock distribution network delay associated with said clock signal and said destination storage elements; an asynchronous signal to be routed to said destination storage elements; a distribution network that routes said asynchronous signal via an output from a distribution buffer to each of said destination storage elements; and a delay component that skews said clock signal relative to said clock distribution network delay, thus producing a skewed clock signal used to clock an asynchronous signal storage element, whereby said asynchronous signal arrives at each of said destination storage elements within a same clock cycle of said clock signal, wherein a delay associated with providing said clock signal to said destination storage elements is less than a combined delay of a delay associated with said delay component and a delay associated with providing said asynchronous signal from said distribution buffer to said destination storage elements.