Patent ID: 7853850

Claim:
A system for testing one or more hardware components, the system comprising: a test pattern injector coupled to a plurality of verification paths, each verification path passing through one or more hardware components, the verification paths including a trunk verification path and a matrix verification path, the trunk verification path passing through a switch and a network, the matrix verification path passing through the switch but not the network, the test pattern injector configured to: generate a plurality of unique test patterns, a test pattern generated to test one or more hardware features of the one or more hardware components of a corresponding verification path; and inject the test patterns into the corresponding verification paths; and a test pattern detector coupled to the verification paths, the test pattern detector configured to: establish a plurality of expected test patterns, an expected test pattern matching an injected test pattern of a corresponding verification path; receive the test patterns from the verification paths; and for each corresponding verification path, determine whether the received test pattern matches the expected test pattern.