Patent ID: 8555099

Claim:
An electronic device comprising: a host processor; a first graphics subsystem interconnected with said host processor; a frame buffer defined in memory accessible by said first graphics subsystem; a second graphics subsystem interconnected with said frame buffer and said host processor by way of a peripheral expansion bus, said second graphics subsystem lacking a dedicated frame buffer; said first graphics subsystem and said second graphics subsystem selectively operable to allow a selected one of said first and second graphics subsystems to render graphics into said frame buffer in response to at least one command from said processor; a display interface to present graphics in said frame buffer to a display interconnected with said display interface; a power controller interconnected with said second graphics subsystem to operate said second graphics subsystem in a lower power consumption mode; said host processor executing processor executable instructions causing said host processor to deselect said second graphics subsystem and select said first graphics subsystem for rendering graphics into said frame buffer, transitioning said electronic device from a first mode in which said second graphics subsystem renders said graphics into said frame buffer by way of said peripheral expansion bus to a second mode in which said first graphics subsystem renders said graphics into said frame buffer, and said second graphics subsystem is placed in said lower power consumption mode without restarting said electronic device, wherein said power controller disconnects power to at least a part of said second graphics subsystem in said second mode, without restarting said electronic device.