Patent ID: 7719339

Claim:
A voltage limiting circuit (VL) for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, where, in the case of the value of an input signal (Vin) of the voltage limiting circuit (VL) being less than that of a predetermined maximum voltage (Vmax), an output signal (Vin′) of the voltage limiting circuit (VL) is substantially proportional to the input signal (Vin), and where in an overvoltage case in which the value of the input signal (Vin) exceeds that of the predetermined maximum voltage (Vmax), the output signal (Vin′) is substantially constant, the voltage limiting circuit (VL) comprising: (a) a voltage divider (R 1 a , T 1 ; R 1 a , T 1 , R 1 c ) to which the input signal (Vin) is applied and which includes at least one variable-resistance voltage divider component (T 1 ) whose resistance can be varied by means of a control signal, (b) the voltage divider (R 1 a , T 1 ; R 1 a , T 1 , R 1 c ) being configured such that the output signal (Vin′) of the voltage limiting circuit is formed by the variable-resistance voltage divider component (T 1 ), and (c) a differential amplifier (OPAMP 2 ) coupled to the variable-resistance voltage divider component (T 1 ) for amplifying the difference between the output signal (Vin′) and a reference voltage (Vmax/2) that corresponds to the maximum voltage (Vmax), with the output signal of said differential amplifier (OPAMP 2 ) to provide the control signal to the variable-resistance voltage divider component (T 1 ), wherein for the overvoltage case the output signal (Vin′) of the voltage limiting circuit is substantially constant.