Patent ID: 7038255

Claim:
An integrated circuit arrangement ( 100 ), having at least one npn transistor ( 104 ) containing, in the following order in a manner adjoining one another, a first n-doped edge region ( 182 ), a p-doped base region ( 184 ) and a further n-doped edge region ( 186 ), and having at least one pnp transistor ( 102 ) containing, in the following order in a manner adjoining one another, a first p-doped edge region ( 114 ), an n-doped base region ( 116 ) and a further p-doped edge region 118 , the integrated circuit arrangement comprising a monocrystalline substrate ( 108 ) containing the base region ( 116 ) of the pnp transistor ( 102 ), the edge regions ( 114 , 118 ) of the pnp transistor and the first edge region ( 182 ) of the npn transistor ( 104 ), a base terminal region ( 139 ), adjoining the substrate ( 108 ), for the base region ( 116 ) of the pnp transistor ( 102 ), and at least one cutout ( 142 ) arranged in the base terminal region ( 139 ), the base region ( 116 ) of the pnp transistor ( 102 ) being arranged below said cutout ( 142 ), a first edge terminal region ( 120 ) for the further edge region ( 118 ) of the pnp transistor ( 102 ) being arranged in the cutout ( 142 ), and the first edge terminal region ( 120 ) containing a part near the substrate which is arranged in the cutout ( 142 ) and a part remote from the substrate which is arranged outside the cutout ( 142 ) and is arranged further away from the substrate ( 108 ) than the part near the substrate and overlaps the base terminal region ( 139 ).