Patent ID: 8854874

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells connected between first interconnections and second interconnections without transistors connected between the first interconnections and the second interconnections, each of the memory cells including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude, the reset operation being an operation of causing the memory cell to transit from a low resistance state to a high resistance state by applying a reset voltage between the first interconnection and the second interconnection, and the set operation being an operation of causing the memory cell to transit from the high resistance state to the low resistance state by applying a set voltage having a polarity different from the reset voltage between the first interconnection and the second interconnection; and a control circuit configured to perform the reset operation and the set operation for the memory cells, the control circuit performing the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.