Patent ID: 8103858

Claim:
A method for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions, the method comprising: identifying a numerical exception for a SIMD floating point operation; initiating a first SIMD micro-operation to generate a first packed partial result for the SIMD floating point operation; initiating a second SIMD micro-operation to generate a second packed partial result for the SIMD floating point operation, wherein a set of one or more packed source operands used to produce the first and second packed partial results for the SIMD floating point operation are stored in their original representation widths; initiating a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element; storing the third packed result for the SIMD floating point operation; and setting a flag identifying the denormal element of the third packed result in said first packed partial result.