Patent ID: 8842471

Claim:
A method of programming a non-volatile memory circuit having non-volatile memory cells formed along a plurality of bit lines and a plurality of word lines according to a NAND type architecture, comprising: performing an alternating plurality of pulse and verify operations on the memory cells along a selected word line, wherein a pulse operation includes: individually biasing the bit lines to one of a plurality of values, including a program inhibit level and a program enable level; biasing a common source line for the bit lines to a first non-zero voltage level; and applying a programming pulse to the selected word line while the bit lines and common source line are so biased; and wherein a verify operation includes: biasing the bit lines to a verify level; and concurrently biasing the common source line to a second non-zero voltage level; and subsequent to the pulse operations and prior to the subsequent verify operation, equalizing the bit lines and the common source line at a non-zero voltage level.