Patent ID: 7915116

Claim:
A method of manufacturing a memory device, the method comprising: defining at least one substantially linear active area within a substrate, said active area comprising a shared source, a first drain, and a second drain, the shared source, the first drain and the second drain defining a first axis; defining a first gate between the shared source and the first drain; defining a second gate between the shared source and the second drain; defining at least one pair of substantially parallel word lines within the substrate by a pitch-doubling technique such that each of the pair has a first width, said pair of word lines defining a second axis lengthwise wherein a first word line of the pair is coupled to the first gate, wherein a second word line of the pair is coupled to the second gate, wherein a third axis runs perpendicular to the second axis; and defining at least one digit line above the substrate in a substantially zig-zag pattern, wherein the digit line has a width about double that of the first width, wherein at least a portion of the digit line extends above and is coupled to the shared source, the portion defining a fourth axis, wherein an acute angle between the third axis and the fourth axis is within the range of 20° to 30°.