Patent ID: 7694199

Claim:
An integrated circuit comprising: A. core logic circuitry for performing normal operating functions of the integrated circuit and having a system data output lead; B. output buffer circuitry having an input selectively connected to the system data output lead and an output; C. boundary scan cell circuitry including first switch circuitry selectively connecting the system data output lead to a first node, multiplexer circuitry having an input connected to a serial input, another input connected to the first node, and an output, memory circuitry having an input connected to the output of the multiplexer circuitry and an output connected to a serial output, second switch circuitry selectively connecting the output of the memory circuitry to the first node, and third switch circuitry selectively connecting the first node and the input of the output buffer circuitry; and D. latch circuitry having an input connected to the output of the output buffer circuitry and an output connected to the input of the output buffer circuitry, the latch circuitry having less electrical output drive capacity than signals applied to the input of the output buffer circuitry through the first or second switch circuitries.