Patent ID: 7301833

Claim:
A method for controlling a shift redundancy circuit that selectively connects a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedies a deficiency relating to each of the plurality of selection lines for each memory block, the method comprising the steps of: generating a decode signal by decoding a deficiency address indicating a deficient location in response to a set signal; generating and holding, individually for each memory block having a deficiency to be remedied, a shift signal for determining the plurality of decode selection lines that are to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on the decode signal; selecting a held shift signal that corresponds to a selected memory block having a deficiency to be remedied, based on a memory block selection signal; and selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the selected shift signal.