Patent ID: 8159877

Claim:
A non-volatile memory (NVM) cell structure comprising: an NMOS control transistor having commonly-connected source, drain and bulk region electrodes to which a control voltage is applied and a gate electrode connected to a data storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes to which an erase voltage is applied and a gate electrode connected to the data storage node; a PMOS inverter transistor having a drain electrode connected to an output voltage node of the NVM cell; an NMOS inverter transistor having a drain electrode connected to the output voltage node; a first NMOS transistor that includes commonly-connected source and bulk region electrodes that are grounded, a drain electrode that is connected to the source of the PMOS inverter transistor, and a gate electrode connected to a first electrode; a first PMOS transistor having commonly-connected source and bulk region electrodes selectively connectable to receive the first supply voltage or the second supply voltage, a drain electrode that is connected to the source of the PMOS inverter transistor, and a gate electrode connected to the first electrode; a second NMOS transistor that includes commonly-connected source and bulk region electrodes that are grounded, a drain electrode that is connected to the source electrode of the NMOS inverter transistor; and a gate electrode connected to a second electrode; and a second PMOS transistor having commonly-connected source and bulk region electrodes selectively connectable to receive either the first supply voltage or the second supply voltage, a drain electrode connected to the source electrode of the NMOS inverter transistor, and a gate electrode connected to the second electrode.