Patent ID: 8171437

Claim:
A method for simplifying at least a portion of an integrated circuit embodied by a netlist, comprising: (a) setting a current state; (b) simulating, in a ternary fashion, the netlist at a time value by applying logical X values to all RANDOM gates of the netlist and to registers marked X_SATURATED of all registers of the netlist, wherein the logical X values represent one of a “do not care” value and an undetermined value representing either 0 or 1; (c) for each register of the netlist: determining, by using a computer, whether or not the register is not already marked as X_SATURATED and the register is found to depart from its expected prefix behavior; and if the register is not already marked as X_SATURATED and the register is found to depart from its expected prefix behavior: marking the register as X_SATURATED; and updating the current state with an X value upon the register; (d) searching for the current state in a hash table; (e) determining whether or not the current state was found in the hash table; (f) if the current state was found in the hash table, setting a converged value to one; (g) if the current state was not found in the hash table, inserting the current state into the hash table; (h) determining whether or not one or more computational and timing resources are exceeded; (i) if the one or more resources are not exceeded: incrementing the time value by one; and repeating from step (a); and (j) if the one or more resources are exceeded: determining whether or not the converged value is not zero; if the converged value is zero, indicating that the netlist could not be simplified; and if the converged value is not zero: simplifying the netlist using information from the hash table; and outputting the simplified netlist.