Patent ID: 6975528

Claim:
A read only memory device, comprising: a read only memory cell array including: a plurality of first read only memory cells coupled to a plurality of word lines, a plurality of first bit lines, and a plurality of first virtual ground lines; and a plurality of second read only memory cells coupled to a reference word line, a plurality of second bit lines and a plurality of second virtual ground lines; a reference memory cell array including: a plurality of first reference memory cells coupled to a plurality of dummy word lines, at least one reference bit line, and at least one reference virtual ground line; and at least one second reference memory cell coupled to the reference word line, the at least one reference bit line, and the at least one reference virtual ground line; and a dummy memory cell array including: a plurality of first dummy memory cells coupled to the plurality of dummy word lines, at least one dummy bit line, and at least one dummy virtual ground line; and at least one second dummy memory cells coupled to the reference word line, the at least one dummy bit line, and the at least one dummy virtual ground line; where the reference word line is selected when at least one of the plurality of word lines is selected.