Patent ID: 7994583

Claim:
A semiconductor device comprising: a semiconductor substrate; an n-type FinFET which is provided on the semiconductor substrate and which includes a first fin acting as an active region, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at one end and the other end of the first fin and sandwiching the channel region; a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin acting as an active region, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at one end and the other end of the second fin and sandwiching the channel region, wherein the n-type FinFET and the p-type FinFET constitute an inverter circuit, and a channel width of the p-type FinFET is equal to a channel width of the n-type FinFET, the fin width of the contact region of the p-type FinFET to act as an output node of the inverter circuit is greater than the fin width of the channel region of the n-type FinFET, a dimension in a direction parallel to a source-drain direction of the contact region, which acts as the output node of the inverter circuit, of the p-type FinFET is greater than a dimension in a direction parallel to a source-drain direction of the contact region, which acts as the output node of the inverter circuit, of the n-type FinFET, and the fin width of the channel region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.