Patent ID: 8599292

Claim:
A CMOS image sensor, comprising: a pixel array comprising a plurality of unit pixels arranged in a plurality of rows and columns, individual rows of unit pixels being coupled to respective row control signal lines; and a buffer comprising a plurality of row control signal drivers, each row control signal driver being coupled to a respective one of the row control signal lines, each row control signal driver configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias said row control signal line at a ground voltage when the respective row control signal line is in an inactive state, wherein each row control signal driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state, and wherein each row control signal driver comprises an inverter having an input for receiving the input pulse and an output coupled to its respective row control signal line, the inverter comprising a PMOS transistor coupled between a voltage supply node and the respective row control signal line and a first NMOS transistor, wherein gate and drain terminals of the PMOS transistor and first NMOS transistor are coupled together to form the inverter input and output, the row control signal driver further comprising a second NMOS transistor coupled between a source terminal of the first NMOS transistor and the ground node, wherein a gate bias of the second NMOS transistor is regulated to control a drive capability of the second NMOS transistor.