Patent ID: 6988160

Claim:
A computer system for transferring data between a receiving central processing unit (CPU) and a transmitting CPU by using only write operations therebetween for the purpose of avoiding a direct read operation by the transmitting CPU from the receiving CPU, said system comprising: a) at least one receiving central processing unit (CPU) comprising at least a read head register, a first queue length register, and a first total read register; b) at least one transmitting CPU comprising at least a write head register, a second total read register, a total write register, and a second queue length register; c) a local memory for said receiving CPU; d) a local memory for said transmitting CPU; e) means for connecting between said receiving CPU and said transmitting CPU where such means transfers write operations faster than read operations; and f) a circular queue defined between designated addresses in said local memory of said receiving CPU, wherein said read head register contains a pointer to the location of the next read from said circular queue and said write head register contains a pointer to the location of the next write into said circular queue, and wherein said receiving CPU is coupled to periodically update said second total read register in the transmitting CPU with a content of said first total read register using one or more write operations, and wherein said transmitting CPU is coupled to write data comprising one or more message separators and one or more messages into said circular queue, responsively to said write head register said second total read register, said total write register and said second queue length register.