Patent ID: 7656174

Claim:
A manufacturing method of a semiconductor device comprising: a step of creating circuits on a wafer to form a plurality of semiconductor devices; and a step of collectively inspecting electrical characteristics of the plurality of semiconductor devices in a state of the wafer by using a semiconductor inspection apparatus, wherein the semiconductor inspection apparatus comprises: a probe sheet including a plurality of contact terminals which contact electrodes provided on the wafer and are formed to have a pyramidal or truncated pyramidal shape, wires led out from the plurality of contact terminals, a plurality of peripheral electrodes electrically connected to the wires and having first peripheral electrodes connected to connection terminals for a tester and second peripheral electrodes having terminals of parts for an inspection circuit, and a metal film which is formed so as to surround the plurality of contact terminals and has almost the same linear expansion ratio as the wafer; a supporting member which interposes the wafer with the probe sheet; a tester which is connected to connection terminals for a tester of a probe cassette including the probe sheet and the supporting member and inspects electrical characteristics of a semiconductor device mounted in the probe cassette; and a vacuum degree control system which reduces pressure in a space between the probe sheet and the supporting member and controls a load applied between electrodes of the semiconductor device and the plurality of contact terminals.