Patent ID: 8102158

Claim:
A phase synchronization circuit comprising: a charging/discharging circuit configured to charge/discharge a capacitor in accordance with a drive signal giving an instruction to charge/discharge the capacitor, a current value of at least one of a charging current and a discharging current of the capacitor being settable; an oscillation circuit configured to output an oscillation signal having a frequency corresponding to a charging voltage of the capacitor; a drive circuit configured to output a first drive signal as the drive signal, the first drive signal being a signal for matching a charging period and a discharging period of the capacitor when a phase difference between an input signal as a reference of the oscillation signal and the oscillation signal is smaller than a predetermined phase difference and for reducing the phase difference when the phase difference is greater than the predetermined phase difference; and a setting circuit configured to receive setting data for setting the current value of at least one of the charging current and the discharging current of the charging/discharging circuit, hold the setting data, and set the current value of at least one of the charging current and the discharging current of the charging/discharging circuit based on the setting data, the drive circuit outputting as the drive signal a second drive signal for matching a charging period and a discharging period of the capacitor, when receiving an adjustment instruction signal giving an instruction to adjust a current value mismatch between the charging current and the discharging current of the charging/discharging circuit, the setting circuit holding the setting data for rendering at a constant level the charging voltage of the capacitor charged/discharged in accordance with the second drive signal.