Patent ID: 6916705

Claim:
A method for fabricating a semiconductor memory containing a memory capacitor including a lower electrode, an upper electrode and a capacitor insulating film disposed between said lower electrode and said upper electrode; a dummy conducting member electrically connected to said upper electrode; and an upper interconnect electrically connected to said dummy conducting member, comprising the steps of: (a) forming said lower electrode by forming a first conductor film over an insulating layer on a semiconductor substrate and patterning said first conductor film; (b) forming a dielectric film covering said lower electrode; (c) forming a second conductor film covering said dielectric film; (d) forming on said second conductor film, an etching mask covering a part of said lower electrode; (e) patterning said second conductor film and said dielectric film, whereby forming said capacitor insulating film and a capacitor insulating film extension from said dielectric film and said upper electrode and an upper electrode extension from said second conductor film; and (f) depositing a third conductor film on said substrate after the step (e) and patterning said third conductor film, whereby forming a conducting member in contact with side faces of said upper electrode extension and said capacitor insulating film extension and electrically connected to said dummy conducting member.