Patent ID: 7308381

Claim:
A method for performing timing verification for a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises: a clock circuit configured to output a plurality of clock signals, and an integrated circuit including a plurality of signal paths to which any of the plurality of clock signals output from the clock circuit is supplied, and wherein the timing verification is performed based on variations in the plurality of clock signals in the semiconductor integrated circuit, the method comprising the steps of: (a) obtaining a plurality of statistical clock skews by statistically calculating a clock skew occurring between each pair of any clock signals of the plurality of clock signals; (b) extracting from the integrated circuit a partial circuit driven by a clock signal pair in which one of the plurality of statistical clock skews occurs; (c) calculating a first statistical timing characteristic of signal paths included in the extracted partial circuit; (d) obtaining at least one of a maximum value and a minimum value of the calculated first statistical timing characteristic as a second statistical timing characteristic; and (e) performing timing verification for the signal paths included in the extracted partial circuit using the obtained second statistical timing characteristic.