Patent ID: 8587986

Claim:
A variable-resistance memory device comprising: a memory cell including a memory element being variable in resistance in accordance with a polarity of an application voltage applied to said memory element in a set or a reset operation and an access transistor connected to said memory element in series between a first common line and a second common line; and a driving circuit including a third control transistor connected between said first common line and a first path transistor, a fourth control transistor connected between a second supply line for supplying a second voltage and a second path transistor, said first path transistor connected between a first supply line for supplying a first voltage and said third control transistor, and said second path transistor connected between a second supply line for supplying a second voltage and said first common line, wherein said driving circuit controls a voltage applied to a gate electrode of said first path transistor, a voltage applied to a gate electrode of said second path transistor and a voltage appearing on said second common line so as to drive said first path transistor to carry out a drain output operation when said application voltage is applied to said memory element to execute said set operation and drive said second path transistor to carry out a source follower operation when said application voltage is applied to said memory element to execute said reset operation.