Patent ID: 8203475

Claim:
An Nth-order, parallel, multi-stage noise shaping (MASH) delta-sigma (ΔΣ) modulator, receiving a multi-bit input, and generating a multi-bit output and N carry out bits, comprising: N modulator stages, arranged in parallel from a first to an Nth stage, each stage comprising an input storage function; an output storage function; and an adder interposed between the input and output storage functions, the adder operative to add the output of the input storage function to the [MSB−1:0] bits of the output of the Nth stage output storage function; whereby the MASH input is the input to the first modulator stage; N−1 adder functions generating the input to the second through Nth modulator stages, each successive adder function operative to add another copy of the MASH input, such that the first adder function generates 2× the MASH input to the second modulator stage, and the N−1 st adder function generates N× the MASH input to the Nth modulator stage.