Patent ID: 7973350

Claim:
Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel extending in a first direction between the source region and the drain region, and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, the piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first conductive layer based on at least one electrically conductive material such that the piezoelectric layer is disposed between this first conductive layer and the other of the two biasing electrodes, the other of the two biasing electrodes overlying the gate of the transistor, such that the arrangement of the two biasing electrodes with the piezoelectric layer therebetween forms a stack in a direction that is orthogonal to the first direction.