Patent ID: 6901009

Claim:
A booster circuit applied for a non-volatile semiconductor memory device, which comprises a memory cell array of multiple non-volatile memory elements and has an operation mode including at least a standby mode to stand ready for an access to one of the multiple non-volatile memory elements, the booster circuit boosting a power source voltage and outputting a boosted voltage according to the operation mode, the booster circuit comprising: a rising time period detection circuit that detects a rising time period between a power supply ON time or a reset time of the non-volatile semiconductor memory device and a time when the boosted voltage reaches a desired voltage corresponding to the standby mode; an oscillation circuit that carries out an oscillating operation to generate and output a clock signal, the oscillation circuit generating a signal of a frequency, which is lower than a preset frequency in an ordinary state, as the clock signal during at least the rising time period, based on a result of the detection by the rising time period detection circuit; a charge pump circuit that boosts the power source voltage and outputs the boosted voltage, in response to the clock signal output from the oscillation circuit; and a level sense circuit that controls the oscillating operation carried out by the oscillation circuit, so as to make the boosted voltage output from the charge pump circuit equal to a predetermined setting voltage according to the operation mode, based on a reference voltage.