Patent ID: 6903572

Claim:
A switch matrix circuit comprising: a memory matrix section arranged plural memory cells in rows and columns for storing switching data using a memory element; a switch matrix section arranged plural switch cells that take either conductive or nonconductive state in rows and columns corresponding to said memory cells; one or more column choosing lines provided corresponding to the respective columns of said memory matrix section and switch matrix section so as to choose memory cells and switch cells that belong to the same column of said memory matrix section and switch matrix section; plural memory row choosing lines provided corresponding to the respective rows of said memory matrix section so as to choose the memory cells belonging to the same row of said memory matrix section; and plural switch row choosing lines provided corresponding to the respective rows of said switch matrix so as to choose the switch cells that belong to the same row of said switch matrix section; and arranged to choose intended one of said plural memory cells and a corresponding switch cell by means of said column choosing line, memory row choosing line, and switch row choosing line, and to determine either conductive or non conductive state of the corresponding switch cell according to the switching data of the memory cell chosen, wherein said switch cell comprises: a switch choosing element having a control terminal connected to said switch row choosing line, a first input-output terminal connected to said column choosing line, and a second input-output terminal to be conductive or non conductive to said first input-output terminal according to a control signal inputted to said control terminal, and a switch field effect transistor having a gate terminal connected the second input-output terminal of said switch choosing element, and first and second switch terminal to be mutually conductive or nonconductive according to a control signal inputted to said gate terminal; wherein said memory element; is a ferroelectric capacitor having first and second terminals; said memory cell further comprising a memory choosing element having a control terminal connected to said memory row choosing line, a first input-output terminal connected to said column choosing line, and a second input-output terminal that becomes either conductive or nonconductive to said first input-output terminal according to a control signal inputted to said control terminal and that is connected to the first terminal of said ferroelectric capacitor; further comprising: a plate line connected to the second terminal of said ferroelectric capacitor so as to apply a specified potential to the second terminal of said ferroelectric capacitor at the time of writing and reading said switching data to and from said ferroelectric capacitor; and a rated potential generating circuit connected to said column choosing line so as to generate the rated potential corresponding to said switching data at the time of reading said switching data from said ferroelectric capacitor.