Patent ID: 7215152

Claim:
An adaptive load output buffer comprising: a first set of series connected complementary cascode structures comprising respective p-channel and n-channel devices and having a first output node at a junction between the p-channel devices, a second output node at a junction between the complementary cascode structures, and a third output node at a junction between the n-channel devices; an output pad; first and second inverters; and at least one second set of series connected complementary cascode structures comprising a p-channel cascode structure and n-channel cascode structure and having a control terminal of the p-channel cascode structure connected to the first output node via said first inverter, a control terminal of the n-channel cascode structure connected to the third output node via the second inverter, and a common terminal between said p-channel and n-channel cascode structures connected to the second output node and said output pad.