Patent ID: 7702964

Claim:
An integrated circuit comprising: a trace module operable to: receive first trace data and a corresponding first current memory address from a first memory; form a first trace data packet that includes a compressed first current address based on the first current memory address, a first memory identifier associated with the first memory, and one of the first trace data and compressed first trace data; receive second trace data and a corresponding second current memory address from a second memory concurrently with receiving the first trace data and the corresponding first current memory address from the first memory; form a second trace data packet that includes a compressed second current address based on the second current memory address, a second memory identifier associated with the second memory, and one of the second trace data and compressed second trace data; filter the first trace data packet based on a first address criterion; filter the second trace data packet based on a second address criterion; generate a first trace data stream that does not include the first trace data packet or the second trace data packet prior to storing the trace data stream in a buffer of the trace module when the first trace data packet does not satisfy the first address criterion and when the second trace data packet does not satisfy the second address criterion; and generate a second trace data stream, wherein the second trace data stream includes the first trace data packet when the first trace data packet satisfies the first address criterion.