Patent ID: 7952955

Claim:
A semiconductor memory comprising: a memory cell; a word line coupled to a transfer transistor of the memory cell; a word driver configured to activate the word line; a first resistance portion configured to couple the word line to a low-level voltage line in accordance with an activation of the word line and to release connection after a first period in an activation period of the word line elapses; a second resistance portion configured to couple the word line to a high-level voltage line in a second period in the activation period wherein the second period is not included in the first period; and a third resistance portion configured to couple the word line to the low-level voltage line in the second period, the resistance of the third resistance portion being higher than a resistance of the first resistance portion, wherein a high-level voltage of the word line in the second period is lower than that of the high-level voltage line by a resistance voltage division of the second resistance portion and the third resistance portion.