Patent ID: 7449939

Claim:
A bias generator circuit comprising: an edge detector circuit having a clock input coupled to receive a clock signal and further having an output at which an activation signal is provided, the edge detector circuit configured to generate the activation signal having a first logic level until a specified edge of the clock signal is detected, at which time the edge detector circuit generates the activation signal having a second logic level during at least some of a plurality of subsequent edges of the clock signal; a voltage divider circuit coupled between a voltage supply and ground, the voltage divider circuit configured to establish an initial bias voltage at a bias node, the bias node selectively coupled to an output node while the activation signal is at the first logic level and being isolated from the output node responsive to the activation signal having the second logic level; and a discharge switch coupled between the bias node and a voltage node having a voltage different than the initial bias voltage, the discharge switch having a control node coupled to receive the activation signal, the discharge switch configured to couple the bias node to the voltage node in response to the activation signal having the first logic level.