Patent ID: 8078845

Claim:
A device comprising: a pipelined processor; an instruction memory unit; and a register file; wherein the pipelined processor comprises: a write-back unit; and an execution unit; a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction, to mask the first register identification information, and to determine an execution related operation of the first instruction in response to the first register group size information, the masked first register identification information, a second register group size information and a second register identification information, wherein a total number of least significant bits masked in the masked first register identification information is less than a total number of source registers associated with the first instruction; wherein the second register group size information and the second register identification information define a second group of target registers associated with a second instruction; and wherein the second instruction is provided to the pipelined processor before the first instruction.