Patent ID: 7804323

Claim:
An impedance matching circuit of a semiconductor memory device, comprising: an input unit for receiving a test calibration code; a test resistance unit for supplying a ground voltage to a first node and having resistance determined according to the test calibration code; a first pull-up resistance unit for supplying a supply voltage to the first node and for calibrating its resistance to that of the test resistance unit in response to a pull-up calibration code; a second pull-up resistance unit for supplying the supply voltage to a second node in response to the pull-up calibration code; and a pull-down resistance unit for supplying the ground voltage to the second node for calibrating its resistance to that of the second pull-up resistance unit in response to a pull-down calibration code, wherein the input unit includes: a logic gate for performing a NAND operation on a calibration test signal and the test calibration code; and an inverter for inverting an output of the logic gate.