Patent ID: 8595407

Claim:
An apparatus comprising: a first circuit disposed on a first side of a bus and configured to (i) store a plurality of thresholds in a first memory, wherein each of said thresholds represents a respective one of a plurality of regular bit patterns in a plurality of first data, (ii) generate a plurality of second data by representing each respective one of said first data as (a) an index to one of said thresholds and (b) a difference between said one threshold and said respective first data and (iii) transmit said second data on said bus, wherein each of said second data is narrower than said respective first data and a width of said bus is narrower than said respective first data; and a second circuit disposed on a second side of said bus and configured to (i) store said thresholds and a plurality of items in a second memory, (ii) receive said second data from said bus, (iii) select based on each of said indexes (a) one of said thresholds and (b) one of said items and (iv) reconstruct said first data by adding said thresholds to said differences in response to said items.