Patent ID: 8234603

Claim:
A method of designing an integrated circuit layout, comprising: providing a plurality of layouts of features to be printed; determining, employing a computer or computer system, the diffraction orders in spatial frequency space for each of said plurality of layouts; providing, employing said computer or computer system, a lithographic difficulty metric comprising a function of: an energy ratio factor comprising a ratio of hard-to-print energy to easy-to-print energy of said diffraction orders along an angular coordinate θ i of said spatial frequency space, wherein said hard-to-print energy comprises energy of said diffraction orders at values of the normalized radial coordinates r of said spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and said easy-to-print energy comprises energy of said diffraction orders located at intermediate values of said normalized radial coordinates r between said neighborhood of r=0 and said neighborhood of r=1; an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate θ i ; a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate θ i ; and a total energy entropy factor comprising total energy entropy of said diffraction orders; computing, for each of said plurality of layouts, employing said computer or computer system, values of said lithographic difficulty metric; and evaluating each of said plurality of layouts based on said values of said lithographic difficulty metric.