Patent ID: 8194372

Claim:
A system for protecting an integrated circuit (IC) from electrostatic discharge (ESD) events, the system comprising: a sensing circuit that detects an occurrence of an ESD event on at least one of a first power supply rail or a second power supply rail of the IC and, in response, outputs an alert signal identifying the occurrence of the ESD event; a driver circuit coupled to the sensing circuit that, responsive to receiving the alert signal from the sensing circuit, outputs an enable signal; and a cascaded switch comprising a first gate and a second gate adjacent to the first gate, wherein the first and second gates are disposed upon a channel located between a drain of the cascaded switch coupled to the first power supply rail and a source of the cascaded switch coupled to the second power supply rail, wherein each of the first and second gates is coupled to the driver circuit and receives the enable signal therefrom, and wherein, responsive to the enable signal, the cascaded switch closes and establishes a coupling between the first power supply rail and the second power supply rail of the IC; wherein: the first gate and the second gate of the cascaded switch comprise at least one dual-gated metal oxide semiconductor field effect transistor (MOSFET) device; the drain is a single drain of the dual-gated MOSFET device; the source is a single source of the dual-gated MOSFET device; and the channel is a single channel of the dual-gated MOSFET device.