Patent ID: 7502463

Claim:
A cryptography engine for performing cryptographic operations on a data block having a first portion and a second portion, the cryptography engine comprising: a key scheduler configured to provide a plurality of keys for cryptographic operation rounds, wherein the key scheduler includes a multi-stage pipeline and is further configured to generate a round key each clock cycle after a series of initialization clock cycles; and cryptographic round logic, wherein the cryptographic round logic is configured to receive a key from the key scheduler for a current cryptographic round and wherein the cryptographic round logic includes: means for combining via a first logical operation the key provided by the key scheduler with a first bit sequence to generate a second bit sequence, wherein the first bit sequence is an expansion of the first portion of the data block; substitution logic for receiving the second bit sequence and for generating a third bit sequence; a first inverse permutation logic for performing, during an initial cryptographic round, an inverse permutation of the first portion of the data block and for generating a first inverse permuted bit sequence, wherein the first inverse permuted bit sequence is a first input bit sequence for a subsequent cryptographic round; a second inverse permutation logic for performing, during an initial cryptographic round, an inverse permutation of the second portion of the data block and for generating a second inverse permuted bit sequence; means for combining via a second logic operation the third bit sequence with the second inverse permuted bit sequence to generate a fourth bit sequence; and a permutation logic for permuting the fourth bit sequence and generating a permuted bit sequence, wherein the permuted bit sequence is a second input bit sequence for the subsequent cryptographic round.