Patent ID: 8924834

Claim:
An error correction electronic circuit comprising: a buffer memory for holding a received string of bits from a transmitted string of bits subject to a probability of transmission error; a parity rule memory holding a set of parity rules for the transmitted string of bits, each parity rule describing a relationship between a subset of the transmitted string of bits; and a linear programming optimizer communicating with the buffer memory and parity rule memory to generate a corrected string of bits from the received string of bits using a linear programming process configured to maximize a probability that the corrected string of bits represents the transmitted string of bits, subject to the set of parity rules for the transmitted string of bits; wherein the linear programming optimizer iteratively repeats two steps, a first step adjusting values of the corrected string of bits based on iteratively changing replicas and a second step updating the iteratively changing replicas based upon their deviation from actual parity rules.