Patent ID: 8415211

Claim:
A method of fabricating a semiconductor device, comprising: providing a substrate comprising an active area isolated by an isolation structure, the active area comprising predetermined regions for subsequently formed drain and source separated by a predetermined region for a subsequently formed gate; forming a high voltage (HV) dielectric layer overlying the substrate; patterning the HV dielectric layer utilizing a patterning mask, forming an HV dielectric pattern, overlying the predetermined regions for the drain and parts of the predetermined regions for the gate, occupying a first predetermined intersection among the isolation structure and the predetermined regions for the drain and the gate, and a second predetermined intersection among the isolation structure and the predetermined regions for the source and the gate, exposing parts of the substrate; forming a low voltage (LV) dielectric layer, thinner than the HV dielectric layer, overlying the exposed substrate, completing formation of a gate dielectric layer overlying the substrate, wherein the gate dielectric layer comprises the HV dielectric layer acting as an HV dielectric portion and the LV dielectric layer acting as an LV dielectric portion, wherein the HV dielectric portion includes a first part in physical contact with the predetermined drain region but not in contact with the predetermined source region, and a second part in physical contact with the predetermined source region but not in contact with the predetermined drain region, and wherein the first part and the second part are entirely separated by the LV dielectric portion and are not in physical contact with each other; forming a gate electrode overlying the gate dielectric layer in the region predetermined there, and the isolation structure; patterning the gate dielectric layer, leaving parts thereof underlying the gate electrode, exposing the predetermined regions for subsequently formed drain and source of the substrate, wherein the remaining HV dielectric portion occupies a first predetermined intersection among the isolation structure, the predetermined region for the drain, and the gate electrode, and a second predetermined intersection among the isolation structure, the predetermined region for the source, and the gate electrode; and forming the source and the drain respectively in the regions predetermined there, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.