Patent ID: 8250578

Claim:
A method of pipelining a plurality of hardware accelerators of a computing system, comprising: pipelining individual partitions of each hardware accelerator of the plurality of hardware accelerators in a vertical pipeline associated with each hardware accelerator of the plurality of hardware accelerators; pipelining each hardware accelerator of the plurality of hardware accelerators in a horizontal pipeline associated with all hardware accelerators of the plurality of hardware accelerators; associating hardware accelerator addresses of a portion of the plurality of hardware accelerators to at least one processing unit (PU) or at least one logical partition (LPAR) of the computing system; receiving a work request for an associated hardware accelerator address; and queuing the work request for a hardware accelerator using the associated hardware accelerator address; wherein associating hardware accelerator addresses includes, identifying a shared pool of hardware accelerators of the plurality of hardware accelerators, providing a listing of the shared pool of hardware accelerators to a mapping server of the computing system, and associating addresses of the shared pool of hardware accelerators on the provided listing.