Patent ID: 7436902

Claim:
An encoder that is operable to generate a multi-dimensional space Gray code mapped LDPC (Low Density Parity Check) coded modulation signal, the encoder comprising: an LDPC encoder that is operable to encode a plurality of information bits thereby generating an LDPC codeword that includes a plurality of LDPC coded bits; wherein the plurality of LDPC coded bits is arranged into a plurality of symbols such that each symbol has a predetermined plurality (n) of bits, wherein n is an integer; a multi-dimensional space Gray code mapper that is operable to map each symbol of the plurality of symbols to a 2m-D (2m-dimensional) M PSK (Phase Shift Key) modulation using an m-D (m-dimensional) cycle Gray code map thereby generating a sequence of discrete-valued modulation symbols that comprise a digital format of the multi-dimensional space Gray code mapped LDPC coded modulation signal, wherein m and M are integers; and wherein: the m-D cycle Gray code map is a one to one and onto map that maps a first matrix, that includes each symbol of the plurality of symbols, to a second matrix that includes a plurality of 2m-D M PSK Gray code mapped symbols; the sequence of discrete-valued modulation symbols is composed of elements of the second matrix that are output from the multi-dimensional space Gray code mapper according to a predetermined order; and each symbol of the sequence of discrete-valued modulation symbols includes at least two pairs of I, Q (In-phase, Quadrature) values that are output from the multi-dimensional space Gray code mapper sequentially as a function of time.