Patent ID: 7611963

Claim:
A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of: etching a shallow trench in a silicon substrate of a semiconductor device; forming a dielectric liner layer on a floor and walls of the shallow trench; forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition; and forming a second doped oxide layer above and in direct contact with the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition; wherein the doping materials in the first doped oxide layer comprise boron and phosphorus; and the first processing condition comprises boron concentration in the range of approximately 4-8 wt %, phosphorus concentration in the range of approximately 3-6 wt %.