Patent ID: 6920582

Claim:
A method for testing circuit modules, comprising the steps of: driving at least one channel module by a test register; driving at least one control module by the test register; testing the at least one channel module by testing at least one scan chain of the channel module; testing the at least one control module by testing at least one scan chain of the control module; in each case testing multiply present channel modules which have a substantially identical scan chain structure tested with substantially identical channel sampling input signals in that channel sampling output signals obtained at a respective channel sampling output are combined in a manner dependent on channel sampling mode signals by gate units in such a way that the channel sampling output signals obtained can be fed temporally successively to a combination unit, the combination unit being designed such that only one of the gate output signals is switched through, an output signal of the combination unit is switched through to a single read-out terminal unit by a multiplexer unit in a manner dependent on a multiplexer sampling enable signal, and sampling enable signals are generated by an AND combination by a first gate unit and a second gate unit in that the sampling mode signals corresponding to the circuit modules to be tested are fed to a second input terminal of the 10 gate units; reading out test results via the read-out terminal unit; and comparing the obtained test results with at least one desired sampling output signal for the tested channel modules by a comparator unit.