Patent ID: 8575608

Claim:
A manufacturing method of a thin film transistor, comprising the steps of: forming a first wiring layer; forming a gate insulating layer so as to cover the first wiring layer; forming a first semiconductor layer over the gate insulating layer overlapping with the first wiring layer, forming a second semiconductor layer having a lower carrier mobility than the first semiconductor layer over the first semiconductor layer, forming an impurity semiconductor layer over the second semiconductor layer; forming an insulating film so as to cover the first semiconductor layer, the second semiconductor layer and the impurity semiconductor layer; anisotropically etching the insulating film to expose the impurity semiconductor layer, so that a sidewall insulating layer covering at least a side surface of the first semiconductor layer is formed; forming a second wiring layer over the impurity semiconductor layer and the sidewall insulating layer; and etching part of the second semiconductor layer and part of the impurity semiconductor layer, so that a source region and a drain region are formed, wherein the part of the second semiconductor layer is etched so that the first semiconductor layer is exposed.