Patent ID: 7439568

Claim:
A field effect transistor (“FET”), comprising: a transistor body region, a source region and a drain region, each of said transistor body region, said source region and said drain region being disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent to a sidewall of a trench, said substrate including a buried insulator layer underlying said SOI region and a bulk region underlying said buried insulator layer, said transistor body region being adjacent to said sidewall along a first side and a second side of said trench, said second side being opposite from said first side and across said trench from said first side, said FET further including a gate dielectric layer extending along said sidewall along said first and second opposite sides of said trench and a gate conductor disposed within said trench between said first and second opposite sides; a capacitor including a lower node operable as a first plate of said capacitor and a second plate separated from said lower node by a capacitor dielectric; a buried strap extending along said first side of said trench, said buried strap conductively connecting said drain region to said lower node; a trench top oxide separating said gate conductor from said lower node; a dielectric collar extending vertically along said sidewall between said trench top oxide and said lower node; and a body contact extending along said second side of said trench from said transistor body region to said bulk region of said substrate, said body contact having a vertically extending inner face contacting said dielectric collar and a vertically extending outer face remote from said inner face, wherein said outer face is in conductive communication with said SOI region and said bulk region.