Patent ID: 6846707

Claim:
A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT), the method comprising the steps of: providing a substrate comprising an N type LTPS TFT region and a P type LTPS TFT region; sequentially forming a patterned undoped polysilicon layer, a dielectric layer, a patterned conductive layer, and a first patterned photo resist layer, the patterned conductive layer and the first patterned photo resist layer comprising two first gaps in the N type LTPS TFT region; performing a first implantation process to implant N type dopants via the first gaps into the undoped patterned polysilicon layer to form a source and a drain of an N type LTPS TFT; performing a trimming process to remove a certain width of the first patterned photo resist layer; removing the patterned conductive layer not covered by the first patterned photo resist layer to form two second gaps and to define a gate of the N type LTPS TFT; performing a second implantation process to implant N type dopants via the second gaps into the undoped patterned polysilicon layer to form two lightly doped drains of the N type LTPS TFT; forming a gate of a P type LTPS TFT in the P type LTPS TFT region; and forming a source and a drain of the P type LTPS TFT in the P type LTPS TFT region.