Patent ID: 8822266

Claim:
A method for packaging integrated circuits, the method comprising: sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, wherein the epoxy layers are deposited by spin coating, the epoxy layers including a first epoxy layer and a second epoxy layer, there being a topmost epoxy layer in the multiplicity of epoxy layers; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited wherein the patterning of the at least one of the epoxy layers includes patterning the first epoxy layer; forming openings in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited wherein the forming of the openings includes forming an opening in the first epoxy layer; placing a first integrated circuit within the opening in the first epoxy layer wherein the first integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the first integrated circuit to thereby cover the first integrated circuit; inserting a first passive component on the second epoxy layer, the component being one selected from the group consisting of an I/O pad, an integrated circuit and an electrical device; forming at least one conductive interconnect layer, wherein each interconnect layer is formed over an associated epoxy layer, wherein each of the interconnect layers is formed from a conductor deposited and defined on the associated epoxy layer and does not include a lead frame; wherein the first integrated circuit is electrically connected with the component through at least one of the conductive interconnect layers, forming a multiplicity of external package contacts, wherein the integrated circuit is electrically connected to a plurality of the external package contacts at least in part through at least one of the conductive interconnect layers.