Patent ID: 7109895

Claim:
A data compression architecture, comprising: a shift register, comprising a plurality of shift register elements; a data input, for receiving input data characters, and for applying each received input data character to said shift register, such that said received input data character is stored in each shift register element of said shift register in turn; comparison circuitry, associated with each shift register element of said shift register, for comparing each received input data character with a respective input data character stored in said shift register element of said shift register; logic circuitry, associated with each shift register element of said shift register, for detecting a match when said comparison circuitry determines that the received input data character is equal to the respective input data character stored in said shift register element of said shift register; a flush input, for receiving a data flush input signal, and for applying a received data flush input signal to the logic circuitry associated with each shift register element of said shift register, such that no match is detected by said logic circuitry when said data flush input signal is received.