Patent ID: 7315915

Claim:
A non-volatile semiconductor memory device comprising: a cell array having electrically rewritable and non-volatile memory cells arranged therein, said cell array being divided into a plurality of blocks, each said block being divided into a plurality of sub-blocks each comprising one or plural and continuous pages; and a controller for controlling data erasure of said cell array in a way that each said sub-block serves as a unit of data erasure, each said sub-block in said cell array storing the number of data erasure which is renewed by each data erasure, and the number of data erasure is limited for each said sub-block to a permissible maximum value stored in a certain block in said cell array; a first register for storing said permissible maximum value read out of said certain block; a second register for storing the number of data erasure read out of a selected sub-block selected for data erasing before data erasure; and a judgment circuit for judging whether the number of data erasure read from said second register has reached said permissible maximum value or not, and wherein in a case the number of data erasure has not reached said permissible maximum value, the number of data erasure is renewed and written into said selected sub-block after having erased said selected sub-block.