Patent ID: 7386827

Claim:
A method of building a simulation environment that includes a design block for a programmable logic device (PLD), comprising: producing a first functional model that emulates interaction of a processor with a first interface of a bus for the processor, the first functional model controlled by a first script in a scripting language, the first script specifying a first plurality of transactions transferred between the first functional model and the first interface; producing a second functional model controllable to emulate a plurality of interfaces, the second functional model controlled to emulate a second interface of an input/output peripheral by a second script in the scripting language, the second script specifying a second plurality of transactions transferred between the second functional model and the second interface; producing a third functional model that emulates a memory subsystem, the third functional model responsive to a plurality of transactions of the bus for the processor; and automatically generating the simulation environment that simulates the design block for the PLD, wherein the simulation environment couples the bus for the processor to the design block and the first and third functional models, couples the second interface to the design block and the second functional model, and couples the first and second functional models via a synchronization bus used for synchronizing between the first plurality of transactions of the first script and the second plurality of transactions of the second script.