Patent ID: 7346871

Claim:
A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, comprising: a step of predicting a power-supply wiring space used in the semiconductor integrated circuit; a step of dividing the predicted power-supply wiring space onto respective wiring layers; and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers, wherein the step of estimating the complexity degree includes a step of generating virtual power-supply wirings as a signal wiring inhibiting area based on the wiring specification in respective wiring layers, and estimating the complexity degree at the time of laying the signal wirings based on a size of the signal wiring inhibiting area, and wherein the estimating step is the step of estimating the complexity degree at the time of laying the signal wirings, by calculating virtual power-supply wiring laying spaces along the wiring specification in respective wiring layers while using a predictive signal wiring space ratio in respective layers as input information, then adding the virtual power-supply wiring laying spaces to the predictive signal wiring space ratio, and then outputting a difference between a wiring space ratio obtained by considering the predictive power-supply area and an actual wiring space ratio at the time of laying the signal wirings.