Patent ID: 8421079

Claim:
A pixel structure comprising: a substrate; a scan line configured on the substrate; a data line configured on the substrate, an extension direction of the data line intersecting an extension direction of the scan line; a thin film transistor configured on the substrate and electrically connected to the scan line and the data line; a semiconductor layer configured on the substrate; a metal capacitor electrode configured on the semiconductor layer, a projection area of the metal capacitor electrode on the substrate being located within a projection area of the semiconductor layer on the substrate, and an edge of the projection area of the metal capacitor electrode being spaced from an edge of a projection area of the semiconductor layer; a passivation layer configured on the substrate and covering the scan line, the data line, the thin film transistor, the metal capacitor electrode, and the semiconductor layer; a pixel electrode configured on the passivation layer and electrically connected to the thin film transistor, a projection area of the pixel electrode on the substrate being located outside the projection area of the semiconductor layer on the substrate; and a transparent capacitor electrode configured on the passivation layer, a projection area of the transparent capacitor electrode on the substrate being located within the projection area of the metal capacitor electrode on the substrate.