Patent ID: 7741205

Claim:
A method of manufacturing an integrated circuit, comprising: forming a first dielectric layer over a wafer substrate; forming a semiconductor substrate over the first dielectric layer; forming a transistor device on or in the semiconductor substrate; forming one or more second dielectric layers over the transistor device; forming a metal feature positioned over the one or more second dielectric layers; forming a protective overcoat over the one or more second dielectric layers and over the metal feature; forming a hard mask layer over the protective overcoat; patterning the hard mask layer; forming a trench by etching the protective overcoat, and the one or more second dielectric layers, through the patterned hard mask layer; extending the trench through the semiconductor substrate and the first dielectric layer; patterning and etching the protective overcoat to form an opening to expose the metal feature; and forming conductive plugs within the trench and within the opening.