Patent ID: 8391015

Claim:
A printed wiring board, comprising: an insulating layer; a capacitor including a ceramic high dielectric layer, a first electrode and a second electrode, the high dielectric layer being interposed between the first and second electrodes such that a distance between the first and second electrodes is not more than 10 μm; a plurality of resin insulating layers formed on the insulating layer and including at least one upper resin insulating layer provided on a first electrode side of the capacitor, and at least one lower resin insulating layer provided on a second electrode side of the capacitor; a semiconductor device mounting pad including a first pad and a second pad, the semiconductor device mounting pad being formed on an outermost resin insulating layer of the at least one upper resin insulating layer; a first via conductor formed in one of the at least one upper resin insulating layer to electrically connect the first pad with the first electrode; a second via conductor formed in said one of the at least one of upper resin insulating layer to electrically connect the second pad with the second electrode; and an underfill covered area covered with an underfill resin provided between a semiconductor device to be mounted on the semiconductor device mounting pad, and the printed wiring board, the underfill covered area being provided on a surface of the printed wiring board facing the semiconductor device, wherein: when the underfill covered area is projected, along and parallel to a lamination direction of the resin insulating layers, to a face on which the high dielectric layer is formed, the underfill covered area is larger than an area in which the high dielectric layer is formed, when the high dielectric layer is projected, along and parallel to the lamination direction of the resin insulating layers, to a face on which the semiconductor device is mounted, the area in which the high dielectric layer is formed is larger than a semiconductor device mounting area, the underfill covered area contains an entirety of the area in which the high dielectric layer is formed, which contains an entirety of a pad formation area in which all mounting pads are formed, and the capacitor is located under the underfill covered area.