Patent ID: 7552158

Claim:
A digital filter, comprising: a first data input unit for sequentially delaying input data for a clock period, and sequentially and selectively outputting one of the input data and delay values for the calculation of a filter output value; a second data input unit for sequentially delaying a delayed input data for a clock period, and sequentially and selectively outputting one of the input data and delay values for coefficient update; a multiplier for multiplying the data value that is sequentially and selectively outputted from the second data input unit by an error value; a coefficient update unit for sequentially updating a coefficient by adding an output from the multiplier to an old feedback coefficient, storing updated coefficients in each delay that operates synchronously with a clock signal with a phase difference of 1/N period (N is the number of filter taps), and feedbacking a sequentially selected updated coefficient as the old coefficient; and an output unit for multiplying updated coefficients sequentially and selectively outputted from the coefficient update unit by data sequentially and selectively outputted from the first data input unit, storing in each delay which operates synchronously with a clock signal with a phase difference of 1/N period, adding all outputs from the delays for a predetermined summation period, and outputting the summed value.