Patent ID: 8121825

Claim:
A method for executing a hardware simulation and verification solution on multiple processors, wherein the hardware simulation and verification solution includes a simulation kernel to simulate changes in signal values, and a value change dump (VCD) module to store the changes in the signal values on a computer-readable storage medium, the method comprising: executing the simulation kernel on a first processor, thereby causing the first processor to: generate value change data, wherein the value change data comprise information about changes in signal values during simulation; and store the value change data in a shared memory segment; executing the VCD module on the second processor that is different from the first processor, thereby causing the second processor to: access the value change data from the shared memory segment over a bus; compress the value change data stored in the shared memory segment; and store the compressed value change data in the computer-readable storage medium for subsequent analysis; and wherein the simulation kernel and the VCD module are executed in parallel.