Patent ID: 7403046

Claim:
A sample-and-hold circuit, comprising: a first switch, having a first terminal receiving an input signal, for transmitting the input signal to a second terminal of the first switch in a sample period; a first capacitor, wherein a first terminal of the first capacitor couples to the second terminal of the first switch, a second terminal of the first capacitor couples to a first voltage, for storing a sampling result of the input signal; and an amplifier, coupling to the second terminal of the first switch, wherein the amplifier is disabled in the sample period, and the amplifier is enabled to output an output signal according to the sampling result in a hold period, the amplifier comprising: a positive input terminal coupling to the second terminal of the first switch; a negative input terminal; an output terminal for outputting the output signal; a first resistor, wherein a first terminal of the first resistor couples to the negative input terminal, and a second terminal of the first resistor couples to the output terminal; and an input stage coupling to the positive input terminal and the negative input terminal for outputting an internal signal in the hold period according to the signals of the positive input terminal and the negative input terminal and stopping to output the internal signal in the sample period, wherein the input stage comprises: a first controllable current source, for providing a current during a hold period and not providing the current during the sample period; a first transistor, having a gate terminal coupled to the positive input terminal, a first source/drain coupled to the first controllable current source, and a second source/drain coupled to an output stage; and a second transistor, having a gate terminal coupled to the negative input terminal, a first source/drain coupled to the first controllable current source, and a second source/drain coupled to the output stage; and the output stage, for providing the output signal to the output terminal according to the internal signal.