Patent ID: 8637906

Claim:
A semiconductor integrated circuit, comprising: a substrate; an oxide layer comprising a first oxide layer and a second oxide layer, wherein the first oxide layer is formed in direct contact with the substrate; a plurality of polysilicon members arranged at constant intervals in a matrix on the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members; and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect which supplies a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect which supplies a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix, wherein the second oxide layer is situated under the second polysilicon members and the first oxide layer is situated under the first polysilicon member, and a thickness of the first oxide layer is smaller than a thickness of the second oxide layer.