Patent ID: 7884676

Claim:
An FLL/PLL circuit that generates, based on an input signal, an output signal having a desired frequency, the FLL/PLL circuit comprising: a VCO which is supplied with a control voltage that is in accordance with the input signal, and which generates an output signal having a desired frequency that is in accordance with the control voltage; a feedback section that generates a feedback of the output signal of the VCO; an error detector that detects an error of the output signal of the VCO by comparing the generated feedback of the output signal of the VCO and the input signal; a loop filter which suppresses a high-frequency component of an output signal of the error detector, and which inputs the resulting signal into the VCO; a voltage retainer that retains an output of the control voltage of the VCO obtained when locked up at a first frequency; a reference signal generator that generates a predefined reference signal when the voltage retainer retains the output of the control voltage of the VCO; an adder that adds the reference signal to the control voltage outputted by the voltage retainer; a Kv calculator that calculates a gain Kv of the VCO, based on a degree of transition of an output frequency of the VCO, which is a difference between an output frequency of the VCO when locked up at the first frequency and an output frequency of the VCO when the reference signal is added; and a loop bandwidth controller which configures, based on the gain Kv of the VCO calculated by the Kv calculator, a gain of the loop filter to the optimum value, and which configures a desired loop bandwidth.