Patent ID: 7974099

Claim:
An apparatus comprising: a first printed circuit board (PCB) that includes a first PCB first surface; an electronics package configured to be disposed on the first PCB first surface; a second PCB; and a plurality of pins configured to secure the first PCB to the second PCB at an interval, the plurality of pins being further configured to form an array within the interval and configured to form an air gap between the plurality of pins within the interval, wherein at least a portion of the plurality of pins are connectable to the first PCB proximate the electronics package to receive at least a portion of heat generated by the electronics package and to conduct the portion of heat generated by the electronics package into the interval for dispersion; wherein the first PCB further includes a first PCB second surface, the first PCB comprises: a first core that includes a first core first surface and a first core second surface; a first metal layer configured to define a first trace disposed on the first core first surface; and a second metal layer configured to define a second trace disposed on the first core second surface, wherein the first core is interposed between the first metal layer and the second metal layer, wherein the first trace is in electrical communication with the second trace, and wherein the electronics package is in electrical communication with the first trace, wherein the second PCB includes a second PCB first surface and a second PCB second surface, the second PCB comprises: a second core that includes a second core first surface and a second core second surface; a third metal layer configured to define a third trace disposed on the second core first surface; and a fourth metal layer configured to define a fourth trace disposed on the second core second surface, wherein the core is interposed between the third metal layer and the fourth metal layer, and wherein the third trace is in electrical communication with the fourth trace, wherein the plurality of pins pass from the first core first surface to the first core second surface to conduct heat generated by the electronics package through the first core and to disperse the heat from the array, and wherein at least one of the plurality of pins engages the third trace, the fourth trace, the first trace and the second trace such that the first trace and the second trace are in electrical communication with the third trace and the fourth trace, respectively.