Patent ID: 7583104

Claim:
An integrated circuit device having a low power mode with a maintained configuration of an input receiver, and a maintained configuration and output data state of an output driver, comprising: a plurality of logic circuits having a low power mode; an input-output (I/O) node coupled to the plurality of logic circuits, the I/O node comprises an I/O keeper cell coupled to an output driver and an input receiver, wherein the output driver and the input receiver are configurable; wherein when the I/O keeper cell receives an enter low power mode signal the I/O keeper cell maintains the input receiver according to a receive configuration and the output driver according to an output configuration and at an output data state that were determined by the plurality of logic circuits before entering the low power mode; wherein when the I/O keeper cell receives a wake-up and restore from low power mode signal the I/O keeper cell returns control of the receive configuration of the input receiver and the output configuration and the output data state of the output driver to the plurality of logic circuits; and a low power mode register that stores logic levels for and controls the enter low power mode signal and the wake-up and restore from low power mode signal.