Patent ID: 7898310

Claim:
A phase doubler driver circuit, comprising: a first input for receiving an input PWM drive signal; first control logic for generating a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal; wherein in a first mode of operation alternating pulses of the input PWM drive signal are output as the first output PWM drive signal and the second PWM output drive signal respectively; wherein in a second mode of operation the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM drive signal exceeds the phase current associated with the second output PWM drive signal; second control logic for adding an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM drive signal responsive to a difference between a second current associated with the second phase current and the average current, wherein the average current comprises the average of the first current and the second current; and drive circuitry for generating drive signals responsive to each of the first output PWM drive signal and the second output PWM drive signal.