Patent ID: 7869558

Claim:
A counting circuit comprising: first storage circuitry which stores a count value; second storage circuitry which stores a calibration value; match circuitry coupled to the first storage circuitry which compares a first portion of the count value with a first predetermined threshold, wherein when the first portion of the count value matches the first predetermined threshold, the match circuitry asserts a calibration signal and when the first portion of the count value does not match the first predetermined threshold, the match circuitry negates the calibration signal; and count value update circuitry coupled to the first storage circuitry, the second storage circuitry, and the match circuitry, wherein the count value update circuitry: in response to the calibration signal being asserted and calibration being enabled, updates the count value in the first storage circuitry using the calibration value, in response to the calibration signal being asserted and calibration being disabled, updates the count value in the first storage circuitry using a predetermined step size, without using the calibration value, and in response to the calibration signal being negated, updates the count value in the first storage circuitry using the predetermined step size, without using the calibration value.