Patent ID: 6882184

Claim:
A clock switching circuit comprising: a clock output circuit providing a selected clock signal; and a plurality of clock signal transfer circuits receiving a plurality of input clock signals and a plurality of select signals, and outputting a plurality of transfer signals to the clock output circuit, each of the clock signal transfer circuits including a select signal transfer circuit connected to the clock output circuit, the select signal transfer circuit receiving one of the select signals and providing the received select signal responsive to the selected clock signal, an internal select signal generating circuit connected to the select signal transfer circuit, the internal select signal generating circuit providing an internal select signal responsive to the received select signal output from the select signal transfer circuit and one of the input clock signals, wherein the internal select signal generating circuit is a D flip-flop having an input signal terminal connected to receive the received select signal output from the select signal transfer circuit, an asynchronous reset signal terminal connected to receive the received select signal output from the select signal transfer circuit, a clock input terminal connected to receive one of the input clock signals, and an output signal terminal providing the internal select signal, and a clock signal passing circuit connected to the internal select signal generating circuit and the clock output circuit, the clock signal passing circuit providing the one of the input clock signals to the clock output circuit as a respective one of the transfer signals, responsive to the internal select signal.