Patent ID: 8907709

Claim:
A delay difference detection and adjustment device capable of detecting and adjusting a delay difference between two delay circuits, comprising: a first delay circuit including a plurality of serially connected first delay units operable to receive and then transmit a first clock; a second delay circuit including a plurality of serially connected second delay units operable to receive and then transmit a second clock in which the delay amount of the second delay circuit is adjustable; a storage circuit including a plurality of storage units coupled to the first and second delay circuits in which each of the storage units includes a data input end operable to receive the first clock from the first delay circuit and an operation clock reception end operable to receive the second clock from the second delay circuit, so that the storage circuit is operable to save a plurality of levels of the first clock in light of the second clock; a delay control circuit coupled to the second delay circuit and operable to adjust the delay amount of the second delay circuit; and an analyzing circuit coupled to at least one output end of the storage circuit and operable to generate an analysis result according to the cycle of the first clock and the plurality of levels of the first clock in which the analysis result indicates or is used to derive a unit delay difference between the first delay unit and the second delay unit.