Patent ID: 8193866

Claim:
An all-digital phase-locked loop (ADPLL) comprising: a digital macro module for receiving signals carrying phase information and frequency information related to a feedback signal, the digital macro module comprises: a digital loop filter, comprising a proportional path module and a digital low-pass filter, for generating an integer signal and a fractional signal; and a sigma-delta modulator (SDM) compensation module for predicting errors and for inputting the predicted errors into the digital loop filter; a modulator across the digital loop filter, comprising: a first accumulator having an input terminal for receiving a modulation signal; an accumulator (ACC) amplifier having an input terminal coupled to an output terminal of the first accumulator and an output terminal coupled to an input terminal of the digital loop filter; and a modulator (MOD) amplifier having an input terminal for receiving the modulation signal and an output terminal coupled to an output terminal of the digital loop filter; and a feedback path module, coupled between the output terminal of the digital loop filter and the input terminal of the digital loop filter, comprising: a second SDM; and a frequency divider for cooperating with the second SDM; wherein the ADPLL is used for direct-frequency modulation (DFM).