Patent ID: 8873295

Claim:
A memory, comprising: a decoder comprising an input terminal and a plurality of output terminals, the input terminal being configured to receive a power supply voltage; a memory array comprising a plurality of source lines and a plurality of memory units, the source lines each being electrically coupled to the respective output terminal of the decoder and N number of memory units; a plurality of loads each having a load value equal to that of each one of the memory units; a load detection circuit configured to obtain a N-bit input data of the memory, determine the number of the memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data, and generate a first determination result accordingly; and a load control circuit configured to receive the first determination result, wherein if the first determination result indicates that there are M number of the memory units required to update the content stored therein, the load control circuit provides (N−M) number of the loads to the decoder so as to couple in parallel the (N−M) number of the provided loads to a transmission path of the power supply voltage, wherein N and M are natural numbers.