Patent ID: 7752529

Claim:
An apparatus, comprising: a circuitry for performing both: calculation of a parity bit that is generated when encoding a first information bit using an LDPC (Low Density Parity Check) matrix such that the first information bit and the parity bit form at least part of a first LDPC coded signal; and syndrome checking calculation during decoding processing of a second LDPC coded signal using the LDPC matrix to determine a best estimate of a second information bit encoded within the second LDPC coded signal, wherein the syndrome checking calculation involving determining a syndrome associated with the best estimate of the second information bit encoded; and wherein: the circuitry includes a plurality of XOR (exclusive OR) logic gates, implemented in an array arrangement such that each XOR gate of the plurality of XOR gates corresponds to a non-zero element of the LDPC matrix, and a plurality of MUXs (multiplexors) that is operable to modify the connectivity of a subset of the plurality of XOR gates that corresponds to at least one column of the LDPC matrix that is employed to generate the parity bit; a select signal is operable to select a first connectivity of each MUX when the circuitry using the LDPC matrix performs encoding of the first information bit to form the first LDPC coded signal; and the select signal is operable to select a second connectivity of each MUX when the circuitry using the LDPC matrix performs decoding processing on the second LDPC coded signal.