Patent ID: 7840302

Claim:
A method of establishing equivalency in the fabrication of a split lot of wafers of integrated circuits fabricated with and without a change in fabrication process, comprising: fabricating wafers of integrated circuits with and without the change; splitting the fabricated wafers into a split lot of control wafers fabricated without the change and experimental wafers fabricated with the change; measuring one or more characteristics of the integrated circuits in the split lot of wafers; dividing a set of data regarding said split lot measured one or more characteristics into control and experimental subsets; summarizing statistics regarding said set and said subsets to an experimental unit above a site level; performing a two-way analysis of variance with respect to said statistics to determine said equivalency, using said set for one way of said analysis of variance and said subsets for another way of said analysis of variance; and upon determining said equivalency, adopting the change into the fabrication process and fabricating further wafers of integrated circuits using the changed fabrication process.