Patent ID: 8693234

Claim:
A memory unit comprising: a plurality of memory elements whose resistance state is reversibly changed according to a polarity of an applied voltage; and a drive section configured to selectively change a resistance state of a target memory element out of the plurality of memory elements from a low resistance state to a high resistance state and from the high resistance state to the low resistance state, wherein, the drive section is configured to execute (a) a setting operation for changing the resistance state of the target memory element from the high resistance state to the low resistance state, and (b) a resetting operation for changing the resistance state of the target memory element from the low resistance state to the high resistance state, and the drive section has an operation mode in which (a) in executing the setting operation, the drive section (i) performs a first stepwise operation in which the drive section repeatedly performs, at least one time, (1) a strong setting stress application step in which a relatively strong stress for performing the setting operation is applied to the target memory element, followed by (2) a weak resetting stress application step in which a relatively weak stress for performing the resetting operation is applied to the target memory element, and (ii) subsequently performs the strong setting stress application step, and (b) in executing the resetting operation, the drive section (i) performs a second stepwise operation in which the drive section repeatedly performs, at least one time, (1) a strong resetting stress application step in which a relatively strong stress for performing the resetting operation is applied to the target memory element, followed by (2) a weak setting stress application step in which a relatively weak stress for performing the setting operation is applied to the target memory element, and (ii) subsequently performs the strong resetting stress application step.