Patent ID: 7162003

Claim:
A system for selecting a first peripheral and a second peripheral, the first peripheral receiving a first clock frequency and the second peripheral receiving a second clock frequency, the first and second clock frequencies differing, in an integrated circuit including a processing circuit configured to receive the first clock frequency, transmit a select signal and an address signal, comprising: a bridge circuit coupled to the processing circuit, the first peripheral and the second peripheral, and configured to receive the select signal and the address signal and transmit a first peripheral select signal to the first peripheral and a second peripheral select signal to the second peripheral, the bridge circuit comprising a counter, wherein the counter is configured to process a count, the count being a predetermined number and based on whether the address signal indicates a first address and the select signal indicates that access is required to the first address, which is associated with the first peripheral, or to a second address, which is associated with the second peripheral, wherein the count differs for the first and second addresses, wherein the bridge circuit asserts the first peripheral and the second peripheral for a period of time based on the value of the count.