Patent ID: 7413939

Claim:
A method of fabricating a silicon-germanium CMOS comprising: preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer to form a silicon/germanium interface; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating layer; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium beginning at the silicon/germanium interface and extending laterally therefrom, thereby forming a single crystal germanium layer; and completing the CMOS device.