Patent ID: 7447095

Claim:
A multi-port memory device having a bank controller for controlling a parallel I/O communication between a plurality of ports and a plurality of banks, the multi-port memory device comprising: a write control unit for generating a write flag signal group and a write driver enable signal in response to a write command and a write clock selectively toggled only while write data are applied; a receiver for generating a write data frame including burst write data and a burst write command by selectively receiving parallel data from the ports; a data latch unit for outputting intermediate write data by storing the burst write data under control of the write flag signal group; a write data mask signal storage unit for receiving the burst write data and the burst write command to generate the data mask signal group in response to the write flag signal group; and a write driver for receiving the intermediate write data output from the data latch unit to write final write data to a memory cell of a corresponding bank in response to the write driver enable signal and the data mask signal group.