Patent ID: 7924246

Claim:
A pixel circuit that makes an electro-optical element emit light and that receives a pixel signal, a ramp level signal and a signal corresponding to a light-emitting period of the electro-optical element, the pixel circuit comprising: a drive current path having a current valve; a first transistor inserted in the driving current path of the electro-optical element; a current value setting circuit that sets the current value of the driving current path; a level holder that stores the level of the pixel signal; a comparison circuit that compares the level of the stored pixel image signal and the ramp level signal, outputs a comparison result and controls the operation time of the first transistor based on the comparison result; a second transistor that is arranged in the driving current path in series with the first transistor and is conductively controlled by the signal corresponding to the light-emitting period of the electro-optical element; and a drive transistor that supplies a drive current corresponding to the current valve of the driving current path of the electro-optical element; the comparison circuit including: an output terminal, first and second input terminals, first and second power sources, a third transistor having a first polarity and a fourth transistor having a second polarity connected in series between first power source and second power sources with the output terminal being a node disposed between the third and fourth transistors; a fifth transistor having a second polarity and a sixth transistor having a second polarity that are connected in series between the first input terminal to which the pixel signal is supplied and the second power source; a seventh transistor having a second polarity and an eighth transistor having a second polarity that are connected in series between the second input terminal to which the ramp level signal is supplied and the second power source; a first capacitance that is connected between a connection between the fifth and sixth transistors and a gate of the third transistor, and operates as the level holder; a second capacitance that is connected between a connection point between the seventh and eighth transistors and a gate of the fourth transistor, and stores the level of the ramp level signal; and a ninth transistor having a second polarity, a first end and a second end, the first end of the ninth transistor being connected to the output terminal and the second end of the ninth transistor being connected to the gates of the third and fourth transistors, a first selection signal that instructs the storing of the level of the pixel signal being supplied to the respective gates of the fifth, eighth, and in the transistors, and a second selection signal, corresponding to the possible light-emitting period being supplied to the respective gates of the sixth and seventh transistors.