Patent ID: 7989889

Claim:
A semiconductor wafer comprising: a first insulator layer; a first semiconductor device layer formed over the first insulator layer and comprising; a source, and a source extension adjacent to the source; a channel formed between the source and the drain; a drain, and a drain extension adjacent to the drain; and first intrinsic material between the source and the drain, such that the first intrinsic material has a resistivity greater than about one ohm·centimeter and the source, the drain, and the first intrinsic material form a lateral high-voltage metal oxide semiconductor field effect transistor (LHV-MOSFET); and a second insulator layer formed over the first semiconductor device layer; and wherein: the source comprises highly-doped semiconductor material having a carrier concentration greater than about 10 18 cm −3 ; the drain comprises highly-doped semiconductor material having a carrier concentration greater than about 10 18 cm −3 ; the channel comprises doped semiconductor material having a carrier concentration less than about 10 18 cm −3 ; the source extension comprises doped semiconductor material having a carrier concentration less than about 10 18 cm −3 ; and the drain extension comprises doped semiconductor material having a carrier concentration less than about 10 18 cm −3 .