Patent ID: 8527972

Claim:
A method for forming, in accordance with a definition file, a parallel processing system that includes a plurality of types of elements that operate in parallel, the method comprising: a first step of reading in the definition file, the definition file including a plurality of parallel descriptions that respectively define a plurality of parallel processes performed independently, the plurality of parallel descriptions including a first parallel description showing a first parallel process with a plurality of data inputs including at least one data input into which output data of another parallel process is inputted; a second step of generating, based on a hardware library in which information about the plurality of types of elements is stored, hardware configuration information including circuit configurations that execute the plurality of parallel processes defined by the plurality of parallel descriptions of the definition file and storing the hardware configuration information in a memory, the circuit configurations including at least one of the plurality of types of elements and each of the plurality of parallel processes being executed synchronously to each other and independently of orders defined by the plurality of parallel descriptions of the definition file; a third step of adding delay elements to the hardware configuration information stored in the memory so that data with a same latency from input into the parallel processing system are inputted into a plurality of data inputs of a circuit configuration that execute the first parallel process; and a fourth step of outputting the hardware configuration information stored in the memory.