Patent ID: 8667226

Claim:
A data processing system, comprising: a first master, the first master comprising: a cache; and snoop queue circuitry having a snoop request queue which stores snoop requests, the snoop queue circuitry receives snoop requests for storage into the snoop request queue and provides snoop requests from the snoop request queue to the cache, the snoop queue circuitry providing a ready indicator indicating whether the snoop request queue can store more snoop requests; and a second master, the second master comprising outgoing transaction control circuitry which controls initiation of outgoing transactions to a system interconnect, wherein in response to the ready indicator indicating that the snoop request queue cannot store more snoop requests, an initiation hold signal is provided to the outgoing transaction control circuitry to prevent the outgoing transaction control circuitry from initiating any outgoing transactions to the system interconnect within a subset of transaction types wherein the subset of transaction types comprises global write transactions, and the outgoing transaction control circuitry is configured to initiate all other memory accesses not within the subset of transaction types.