Patent ID: 7755169

Claim:
A semiconductor device comprising: an integrated circuit; a main wall including metal films surrounding said integrated circuit; and at least one sub-wall including metal films selectively positioned between said integrated circuit and said main wall, each of said sub-walls partially screening said integrated circuit from said main wall, and the totality of said sub-walls incompletely screening said integrated circuit from said main wall, wherein said integrated circuit, said main wall and said sub-wall share: a semiconductor substrate; and one or two or more interlayer insulation film(s) formed above said semiconductor substrate, in which openings are selectively formed, wherein a part of wires constituting said integrated circuit and a part of said metal films provided to each of said main wall and said sub-wall are substantially formed as a same layer, and wherein said sub-wall includes: a first wall piece which has a substantially fixed space from said main wall in plan view; a second wall piece which is formed between said first wall piece and said integrated circuit and has a substantially fixed space from said first wall piece; and a third wall piece which is connected to said main wall at two points and surrounds said first wall piece and said second wall piece with said main wall and itself.