Patent ID: 8748266

Claim:
A manufacturing method of a semiconductor device including a metal-insulator-semiconductor-field-effect transistor (MISFET), comprising steps of: (a) forming a trench in a semiconductor substrate; (b) after the step (a), forming a first insulating film over a bottom surface of the trench, over a side surface of the trench and over an edge portion of the trench by a thermal oxidation method, the edge portion being an intersection between the side surface of the trench and a surface of the semiconductor substrate; (c) after the step (b), forming a second insulating film over the first insulating film by a chemical vapor deposition (CVD) method, and (d) after the step (c), forming a first conductive film over the second insulating film, thereby the trench is filled with the first conductive film, the second insulating film and the first insulating film; wherein the first and second insulating films constitute a gate insulating film of the MISFET, wherein the first conductive film constitutes a gate electrode of the MISFET, wherein the edge portion of the trench has a sloping shape from the surface of the semiconductor substrate to the side surface of the trench, wherein, after said step (d), said first and second insulating films are kept on the bottom surface of the trench, on the side surface of the trench, and on the sloping shape of the edge portion of the trench, wherein, after the step (d), a thickness of the second insulating film formed over the side surface of the trench and over the edge portion of the trench having the sloping shape is greater than a thickness of the first insulating film formed over the side surface of the trench, and wherein the second insulating film consists essentially of silicon oxide and directly contacts the first insulating film.