Patent ID: 6953743

Claim:
A process for fabricating a contact structure for an integrated semiconductor circuit comprising: providing a silicon region on at least a portion of a surface of a semiconductor wafer for making electrical contact thereto; depositing a dielectric layer over the silicon region; etching a contact opening through the dielectric layer for exposing a portion of the silicon region, the contact opening having a sidewall; depositing a titanium metal layer within the contact opening to cover the portion of the silicon region exposed by the contact opening; depositing an amorphous titanium carbonitride film having substantially no crystalline titanium therein, the amorphous titanium carbonitride film lining the sidewall of the contact opening and overlaying the titanium metal layer covering the portion of the silicon region exposed by the contact opening using a vapor deposition process when the semiconductor wafer is located in a chamber; and filling at least a portion of the contact opening using a conductive material.