Patent ID: 8604583

Claim:
A semiconductor device comprising: (a) a semiconductor substrate of a first conductivity type; (b) a first well region formed in the semiconductor substrate, the first well region having a second conductivity type opposite to the first conductivity type; (c) a first semiconductor region of the second conductivity type, the first semiconductor region being formed within the first well region; (d) a first insulating film formed in the semiconductor substrate, the first insulating film being formed so as to surround the first semiconductor region in a plan view; (e) a second semiconductor region of the second conductivity type formed in the first well region, the second semiconductor region being formed outside the first insulating film such that the first insulating film is disposed between the first semiconductor region and the second semiconductor region; (f) a third semiconductor region of the first conductivity type, the third semiconductor region being formed so as to surround the first semiconductor region in the plan view; (g) a first conductor film formed so as to cover the first semiconductor region and the third semiconductor region and to be electrically coupled to the first semiconductor region and the third semiconductor region; (h) a second conductor film formed so as to cover the second semiconductor region and to be electrically coupled to the second semiconductor region; (i) a first plug electrically coupled to the first conductor film; and (j) a second plug electrically coupled to the second conductor film, wherein the electrical coupling of the first semiconductor region and the first conductor film is a Schottky coupling, wherein an impurity concentration of the first semiconductor region is higher than an impurity concentration of the first well region, wherein a depth of the second semiconductor region is greater than a depth of the first insulating film, wherein the third semiconductor region is formed at a peripheral portion of the first conductor film in the first well region, wherein the first semiconductor region and the third semiconductor region do not directly contact each other, and wherein a depth of the third semiconductor region is less than the depth of the first insulating film.