Patent ID: 7049680

Claim:
A semiconductor integrated circuit device comprising: a memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, and a second p-channel MISFET, each of said first n-channel MISFET and said second n-channel MISFET having a gate electrode formed over a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate, each of said first p-channel MISFET and said second p-channel MISFET having a gate electrode formed over said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate; a first insulating film formed over the MISFETs; a first conductive film and a second conductive film formed on said first insulating film and comprised of a different conductive layer from that of said gate electrodes of said MISFETs, said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, and said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET; a second insulating film formed over said first conductive film and said second conductive film; a power source line formed over said second insulating film and electrically connected to said source region of said first p-channel MISFET and said source region of said second p-channel MISFET; and a reference voltage line formed over said second insulating film, formed from a same level layer as that of said power source line and electrically connected to said source region of said first n-channel MISFET and said source region of said second n-channel MISFET.