Patent ID: 7863130

Claim:
A method for manufacturing an integrated circuit, comprising: forming a first trench and a second trench in a substrate; forming a first cavity and a second cavity within the substrate, wherein the first cavity is linked to the first trench at a first sidewall, wherein an opposite second sidewall of the first trench is not linked to any other cavity, wherein the second cavity is linked to the second trench at a first sidewall, and wherein an opposite second sidewall of the second trench is not linked to any other cavity; depositing a dielectric layer within the first cavity and the second cavity; depositing polycrystalline silicon over the dielectric layer within the first cavity and the second cavity, the polycrystalline silicon filling at least a part of the first trench and a part of the second trench, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer; and forming a gate over a portion of the substrate between the first cavity and the second cavity.