Patent ID: 7271413

Claim:
A semiconductor construction, comprising: a semiconductor substrate comprising a monocrystalline semiconductor material; a plurality of isolation regions within the semiconductor material and extending along a defined longitudinal direction, the isolation regions being spaced from one another by longitudinally-extending strips of the monocrystalline semiconductor material; a plurality of lines extending substantially orthogonally to the isolation regions; the lines having dielectric regions over the isolation regions and semiconductor sections between the dielectric regions; an array of pillars extending upwardly from the monocrystalline semiconductor material, the array comprising columns along the defined longitudinal direction and rows along a defined horizontal direction which is substantially orthogonal to the defined longitudinal direction; the columns of the array being between the isolation regions and along the longitudinally-extending strips of the monocrystalline semiconductor material, the pillars comprising mesas of the monocrystalline semiconductor material extending upwardly from the longitudinally-extending strips; a first set of source/drain regions at upper regions of the pillars; a second set of source/drain regions within the sections of the lines; a set of channel regions between the first and second sets of source/drain regions; and a plurality of gateline rows extending along the defined horizontal direction; the gateline rows extending along the rows of the array of pillars; the gateline rows, channel regions, and first and second sets of source/drain regions forming a plurality of transistor devices; individual transistor devices comprising a first source/drain region of the first set, a second source/drain region of the second set, a channel region extending from the first source/drain region to the second source/drain region, and a gate within the gateline row and proximate the channel region.