Patent ID: 6996766

Claim:
A memory controller comprising: a check/correct circuit coupled to receive an encoded data block from a memory comprising a plurality of memory devices, the encoded data block including a plurality of check bits, wherein the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block; and a data remap control circuit coupled to receive an indication that the check/correct circuit has detected the failure of a failing memory device of the plurality of memory devices, wherein the data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device, wherein each of the plurality of encoded data blocks has at least one bit stored in the failing memory device prior to remapping and has at least one other bit stored in a different memory device of the plurality of memory devices prior to the remapping.