Patent ID: 8030897

Claim:
An apparatus comprising: a charger circuit configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal; and a control circuit configured to generate said first charge signal and said second charge signal in response to a first battery signal and a second battery signal, wherein (A) (i) said apparatus enters a power down state in response to said host control signal initiating said power down state, (ii) said control circuit enters a sleep mode in said power down state and (iii) said control circuit disconnects operating power from said charger circuit in said power down state, (B) said charger circuit receives power from (i) said supply voltage when said apparatus is in a first mode, and (ii) at least one of said first charge signal and said second charge signal when said apparatus is in a second mode, (C) said control circuit monitors a remaining battery charge of said first battery signal and said second battery signal according to a first checking protocol when said apparatus is in said first mode, and (D) said control circuit monitors said remaining battery charge of said first battery signal and said second battery signal according to a second checking protocol when said apparatus is in said power down state, wherein said second checking protocol uses less power than said first checking protocol.