Patent ID: 7292062

Claim:
A system for distributing signals throughout an integrated circuit (IC), comprising: a. a transmitter unit that combines a plurality of signals into a serial signal stream and couples the serial signal stream to a conductor for distribution to a plurality of destinations in the IC, wherein the transmitter unit comprises: a multiplexer circuit that receives as input the plurality of signals and time multiplexes the plurality of signals to produce the serial signal stream; a counter circuit connected to the multiplexer circuit, wherein the counter circuit receives as input a clock signal and generates as output a counter signal having a count value that is incremented based on the clock signal, wherein the multiplexer circuit selects for output one of the plurality of signals based on the counter signal output by the counter circuit; and b. a plurality of receiver units, each at one of the plurality of destinations and connected to the conductor such that each receiver unit receives each of the plurality of signals in the serial signal stream and the counter signal, and based on the count value of the counter signal latches one of the plurality of signals from the serial signal stream, wherein each receiver unit comprises: a combinational logic circuit that receives as input bits of the counter signal representing the count value and generates an indication in an output signal when the count value of the counter signal matches an assigned count value, wherein the combination logic circuit comprises a plurality of inverter circuits each having an input and an output, wherein the input of each of the plurality of inverter circuits is connected to receive a corresponding bit of the counter signal, and an AND gate having a plurality of inputs and an output, wherein for each inverter circuit either the output or the input is coupled to a corresponding input of the AND gate depending on assigned count value, and wherein the AND gate generates the output signal that is coupled to the clock input of the flip-flop circuit, wherein the AND produces the indication in the output signal in response to signals at its inputs when the count value of the counter signal matches the assigned count value; and a flip-flop circuit having a clock input, a data input and a data output, wherein the data input is coupled to the conductor carrying the serial signal stream, wherein the flip-flop circuit is responsive to the output signal of the combinational logic circuit to latch one of the plurality of signals in the serial signal from the data input to the data output.