Patent ID: 7307877

Claim:
A circuit of a DRAM cell requiring a reduced output current comprising: a switch to activate a write operation to said DRAM cell, wherein a first terminal is connected to an input signal and a second terminal is connected to a gate of a pass transistor and a first terminal of a storage capacitor; said storage capacitor having a second terminal connected to ground voltage; said pass transistor operating as a switch to support a read operation out of said DRAM cell being a natural transistor, wherein its gate is connected to said storage capacitor, its current path is connected to supply voltage, and an other current path opposite to said current path is connected to a first terminal of a switch to activate a read operation; said switch to activate a read operation out of said DRAM cell having a second terminal connected to a current source and to output voltage; and said current source to support the read operation out of said DRAM cell, wherein said switch to activate said write operation is a standard transistor, and wherein said natural transistor is a MOS natural transistor.