Patent ID: 7002503

Claim:
A binary encoder comprising: a first latch transistor that is connected between a node of a first reference voltage and a first output node and responds to a signal output from a second output node; a second latch transistor that is connected between the node of the first reference voltage and the second output node and responds to a signal output from the first output node; an equalize transistor that equalizes a level of the first output node and a level of the second output node in response to a clock signal; a first control transistor that is connected between the first output node and a first control node and responds to the clock signal; a second control transistor that is connected between the second output node and a second control node and responds to the clock signal; a first discharge transistor that discharges the first control node to a level of a second reference voltage in response to a first input signal; and a second discharge transistor that discharges the second control node to the level of the second reference voltage in response to a second input signal.