Patent ID: 7935581

Claim:
A method of fabricating a thin film transistor (TFT) array substrate, comprising: forming a buffer layer on an entire surface of a substrate; forming a semiconductor layer of a first TFT, a semiconductor layer of a second TFT, and a lower electrode pattern of a storage capacitor on the substrate having the buffer layer formed thereon; performing channel doping on the semiconductor layers of the first and second TFTs and forming a lower electrode of the storage capacitor by injecting a plurality of first ions into the semiconductor layers of the first and second TFTs and the lower electrode pattern of the storage capacitor; forming a gate insulating layer on an entire surface of the substrate having the semiconductor layers of the first and second TFTs and the lower electrode of the storage capacitor; forming a gate electrode of the first TFT in a region on the gate insulating layer overlapping a region of a channel of the first TFT, a gate electrode of the second TFT in a region on the gate insulating layer overlapping a region of a channel of the second TFT, and an upper electrode of the storage capacitor in a region on the gate insulating layer overlapping the lower electrode of the storage capacitor; forming a source region and a drain region of the second TFT by injecting a plurality of second ions into corresponding regions of the semiconductor layer of the second TFT; forming a source region and a drain region of the first TFT by injecting a plurality of third ions into corresponding regions of the semiconductor layer of the first TFT; and forming lightly doped drain (LDD) regions of the second TFT by injecting a plurality of fourth ions into corresponding regions of the semiconductor layer of the second TFT while using the gate electrode of the second TFT as a mask, wherein only the second TFT comprises any lightly doped drain (LDD) regions.