Patent ID: 8762676

Claim:
A memory access control device for controlling access to a plurality of memory devices with differing latency, comprising: an access unit configured to access the plurality of memory devices; a control unit configured to control, in a case where a first access and then a second access are performed by the access unit, the timing of performing the second access by the access unit in accordance with a memory device accessed in the first access, a memory device accessed in the second access, and access types of the first and second accesses, wherein the access type indicates whether the access is a read access or a write access, and a storage unit configured to hold one or more command issuing intervals corresponding to combinations of information of a prior command and information of a next command, wherein the information of the prior command and the information of the next command indicate a memory device to be accessed and read access or write access, wherein the control unit controls the timing based on the interval for a combination corresponding to the first access and the second access.