Patent ID: 7089407

Claim:
A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising: a packet access unit comprising a plurality of first registers, moving received packet data into said first registers sequentially from the beginning and moving the moved packet data among said first registers and transmitting the moved packet data; a plurality of instruction procedure execution units, every instruction procedure execution unit having the same configuration as each other, for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit; a selection signal generation unit for generating a selection signal for selecting one of said instruction procedure execution units for performing the calculation corresponding to each of the packets in synchronization with a timing of receiving each packet; and an intermediate data transfer unit comprising a plurality of second registers, moving intermediate data obtained as a process result from one of said instruction procedure execution units corresponding to the packet data into said second registers to transfer the moved intermediate data in synchronization with the moving of the packet data and in parallel using said first registers in said packet access unit.