Patent ID: 8286039

Claim:
A first memory buffer device, comprising: an outbound receiving logic to receive a first data from a first uni-directional link, the first uni-directional link to electrically couple the first memory buffer device with at least a host controller; an outbound redriving logic to drive the first data across a second uni-directional link, the second uni-directional link to electrically couple the first memory buffer device with at least a second memory buffer device, the outbound redriving logic further to disable driving the first data across the second uni-directional link if the second memory buffer device is not coupled with the second uni-directional link; an inbound receiving logic to receive a second data from a third uni-directional link, the third uni-directional link to electrically couple the first memory buffer device with the at least second memory buffer device; and an inbound redriving logic to drive the second data across a fourth uni-directional link, the fourth uni-directional link to electrically couple the first memory buffer device with the at least host controller.