Patent ID: 8687761

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a system clock and a driving control voltage, wherein the Nth gate line is employed to transmit the Nth gate signal; a first input unit, electrically connected to the pull-up unit, for outputting the driving control voltage according to a first input signal; a first pull-down unit, electrically connected to the first input unit, for pulling down the driving control voltage according to a first control signal and a second input signal, the first pull-down unit comprising: a first transistor having a first end electrically connected to the first input unit, a gate end for receiving the first control signal, and a second end; a second transistor having a first end electrically connected to the second end of the first transistor, a gate end for receiving the second input signal, and a second end for receiving a power voltage, wherein the gate ends of the first and second transistors are both electrically connected to an (N+1)th shift register stage of the shift register stages for receiving an (N+1)th gate signal of the gate signals; and a third transistor having a first end electrically connected to the first end of the first transistor, a gate end electrically connected to the gate end of the second transistor, and a second end electrically connected to the second end of the first transistor; and a second pull-down unit, electrically connected to the first input unit and the Nth gate line, for pulling down the Nth gate signal according to the driving control voltage; wherein the first control signal and the second input signal are the (N+1)th gate signal.