Patent ID: 7969785

Claim:
A non-volatile memory (NVM) cell, comprising: a) a gate over a charge trapping layer, said charge trapping layer being insulated from said gate by a first insulating layer, said charge trapping layer being insulated from a channel by a second insulating layer; and b) source and drain on either side of said channel, said channel being under said second insulating layer, wherein said NVM cell is configured to be erased by channel-induced hot holes (CHH) that are produced by ramping down a voltage on said gate from a first positive voltage level to a second positive voltage level, c) wherein said NVM cell is configured to be programmed through said second insulating layer when in a high throughput mode by Fowler-Nordheim (F-N) tunneling, and when in a field programming mode by channel hot electron (CHE) injection.