Patent ID: 7382657

Claim:
A semiconductor memory device comprising: a memory cell array which has a plurality of memory cells arranged in matrix form, a plurality of word lines connected to the memory cells, and a plurality of bit lines connected to the memory cells; a charge circuit which includes a plurality of charging transistors which charge the bit lines, respectively; a bit line reset circuit which includes a plurality of resetting transistors respectively forcing potentials of the bit lines to a around potential, and a read circuit which includes a plurality of reading transistors whose gates are each connected to the bit lines and which outputs information according to the on and off states of the reading transistors, wherein: the charge circuit has a configuration in which at least two charging transistors are provided to the individual bit lines, at least one of at the least two charging transistors are each connected to the individual bit lines, and the remaining charging transistors are in a floating state in relation to the individual bit lines.