Patent ID: 7487297

Claim:
A data processing system comprising: a processor; a memory hierarchy coupled to the processor and comprising a data cache and prefetch buffer (DCPB) and at least one lower level storage device; wherein said DCPB comprises a load miss queue (LMQ), which includes a register for tracking a lateness interval; and a prefetch engine (PE) associated with the processor and comprising logic for: issuing prefetch requests for prefetching data from the at least one lower level storage device for utilization by the processor; saving an identifier (ID) of an ongoing prefetch within the LMQ, wherein said LMQ tracks when an ongoing prefetch is late via the lateness interval, which represents an interval between the issuance of the corresponding prefetch request until when the ongoing prefetch completes and the cache line is returned; and dynamically adjusting a prefetch distance between issuance of the prefetch request and issuance by the processor of a demand for a cache line being returned by the prefetch request so that a subsequent cache line within a prefetch stream is returned via a next issued prefetched request at effectively the same time a demand for data within that subsequent cache line is issued by the processor.