Patent ID: 8760928

Claim:
A memory comprising: a plurality of sensing nodes and reference nodes; a plurality of strings of memory cells, each string in the plurality being arranged for connection between a corresponding sensing node and a corresponding reference node in the plurality of sensing nodes and reference nodes, and including a string select switch to selectively connect the string to the corresponding sensing node and a ground select switch to selectively connect the string to the corresponding reference node; a plurality of word lines, at least one string select line and a ground select line, word lines in the plurality of word lines coupled to corresponding memory cells in the plurality of strings, the at least one string select line coupled to corresponding string select switches in the plurality of strings and the ground select line coupled to corresponding ground select switches in the plurality of strings; and logic and circuitry coupled to the plurality of word lines to apply a bias arrangement including: a first interval in which a first voltage is set up on a selected word line, a second voltage, higher than the first voltage, is set up on unselected word lines in the plurality of word lines, and the semiconductor body of memory cells on both sides of the selected memory cell in the selected string is coupled to a reference voltage; a second interval in which the string select switch for the selected string is open and bit line voltages are set up on the sensing node for a selected string; and a third interval in which the string select switch for the selected string is closed and current flows in the selected memory cell if its threshold is below the first voltage.