Patent ID: 8203082

Claim:
A printed circuit board, comprising: a first layout layer comprising a first signal line and second signal line, each comprising a curved first portion; a second layout layer comprising a third signal line and a fourth signal line, each comprising a curved first portion, the first layout layer being disposed above the second layout layer; at least a third layout layer disposed below the second layout layer; and a first via and a second via through the first layout layer, the second layout layer and the third layout layer, the curved first portions of the first signal line and the third signal line being coupled to the first via, the curved first portions of the second signal line and the fourth signal line being coupled to the second via; wherein the curved first portions of the first signal line and the third signal line are disposed around the first via to cooperatively generate a spiral inductance characteristic with respect to a portion of the third layout layer around the first via, the portion of the third layout layer around the first via includes a first via stub portion, the spiral inductance characteristic generated by the curved first portions of the first signal line and the third signal line substantially compensates the capacitance characteristic of the first via stub portion; and wherein the curved first portions of the second signal line and the fourth signal line are disposed around the second via to cooperatively generate a spiral inductance characteristic with respect to a portion of the third layout layer around the second via, the portion of the third layout layer around the second via includes a second via stub portion, the spiral inductance characteristic generated by the curved first portions of the second signal line and the fourth signal line substantially compensates the capacitance characteristic of the second via stub portion.