Patent ID: 7303967

Claim:
A method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor substrate including an isolation layer and a well; forming a gate electrode by interposing a gate oxide layer between the substrate and the gate electrode; performing a low-density ion implantation process with respect to the substrate using the gate electrode as a mask, forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; performing the ion implantation process with respect to the substrate using the gate electrode including the insulation spacer as a mask, forming a diffusion barrier, wherein the ion implantation process for forming the diffusion barrier is performed with ion energy of 10 to 35 keV and an ion dosage of 1.0E14 to 5.0E15 atoms/cm 2 , wherein, the ion implantation process is performed two to four times; performing a high-density ion implantation process with respect to the substrate including the diffusion barrier using the gate electrode including the insulation spacer as a mask, forming a source/drain; performing a first thermal treatment process with respect to a resultant structure including the source/drain, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and depositing a metal layer on the substrate, which passes through the first thermal treatment process, and performing a second thermal treatment process, forming a salicide layer.