Patent ID: 8617939

Claim:
A method for creating a self aligned FET in a back end of the line (BEOL) region of a semiconductor chip comprising the steps of: creating an etched hole in a dielectric layer between a first wiring plane and a second wiring plane in the BEOL, the etched hole extending part way but not entirely through the dielectric layer between the first wiring plane and the second wiring plane in the BEOL; depositing a conformal layer of silicon on the dielectric level and the etched hole; planarizing the semiconductor chip to remove the conformal layer of silicon except for a portion of the conformal layer in the etched hole, thereby creating a well of silicon; depositing a gate dielectric on the dielectric layer and the well of silicon; creating a gate electrode directly over a portion of the well of silicon; depositing a spacer oxide over the gate dielectric and the gate electrode; anisotropically etching the spacer oxide and the gate dielectric to expose the well of silicon except for areas of the well of silicon covered by the gate electrode and portions of the spacer oxide remaining after the anisotropic etch; and implanting the exposed portions of the well of silicon to create source/drain regions, thereby creating the self aligned FET.