Patent ID: 8514875

Claim:
A network device for processing packet data, the network device comprising: a first plurality of data communication ports; a second plurality of data communication ports; and a packet data processing pipeline coupled with the first and second pluralities of data communication ports, the packet data processing pipeline comprising: a first ingress module coupled with the first plurality of data communication ports; a second ingress module coupled with the second plurality of data communication ports, wherein the first ingress module and the second ingress module are independent of one another, arranged in a parallel fashion and each configured to perform switching functions on respective incoming packet data; a memory management unit (MMU) coupled with the two more ingress modules, the MMU being configured to store the incoming packet data in a memory; and two or more egress modules coupled with the MMU, the two or more egress modules being configured to transmit the incoming packet data, respectively, to two or more corresponding egress ports, the two or more egress modules being arranged in a parallel fashion, wherein the MMU is further configured to receive packet data using a network device clock signal operating at a clock speed for the network device and write the data to the memory using a multiplied clock signal operating at a multiplied clock speed that is greater than the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the two or more egress modules at the clock speed for the network device, where the multiplied clock signal is used to sample the network device clock signal to place timing domains of the multiplied clock signal and the network device clock signal in phase.