Patent ID: 7283388

Claim:
A memory device using a multiple layer nano tube cell, comprising: a multiple layer nano tube cell array including a plurality of unit nano tube cells arranged in row and column directions; a circuit device region for driving the plurality of multiple layer nano tube cell arrays formed on a silicon substrate located under the plurality of multiple layer nano tube cell arrays; and an insulating layer, formed between the plurality of multiple layer nano tube cell arrays and the circuit device region, for inter-insulating the plurality of multiple layer nano tube cell arrays and the circuit device region, wherein each of the plurality of nano tube cells comprises: a capacitor whose one terminal is connected to a word line; and a PNPN nano tube switch, which includes at least two or more PNPN diode devices successively connected in series and divided into two groups each connected in parallel between a bit line and the other terminal of the capacitor, for being selectively switched depending on a voltage applied to the word line and the bit line.