Patent ID: 7112479

Claim:
A method of forming a transistor device, comprising: providing a substrate; forming a first layer over the substrate; forming a patterned second layer over the first layer, the patterned second layer having an opening extending therethrough to the first layer, the second layer defining sidewalls of the opening, and the first layer defining a bottom of the opening; forming a third layer over the second layer and within the opening to narrow the opening; the third layer lining the sidewalls and bottom of the opening; forming a fourth layer over the third layer and within the narrowed opening; anisotropically etching the fourth layer to form sidewall spacers along the sidewalls of the opening, a portion of the third layer being exposed between the sidewall spacers; removing the exposed portion of the third layer; removing the sidewall spacers to leave steps of the third layer along the sidewalls; forming a gateline within the opening and over the steps of the third layer; removing the second layer; and forming source/drain regions gatedly interconnected by the gateline.