Patent ID: 7602638

Claim:
A non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising: a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data; and a flag circuit for outputting a flag signal to switch between the charge localized portions, wherein the memory cell stores static charge in either one of the first and second charge localized portions to hold the data, when the first charge localized portion does not have a production defect, the first charge localized portion stores the static charge to hold the data, and when the first charge localized portion has difficulty in storing the static charge due to the production defect, a charge localized portion to be read and written is changed from the first charge localized portion to the second charge localized portion in accordance with an output of the flag circuit, irrespective of an address signal inputted from outside of the semiconductor memory device, and the second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion, wherein the semiconductor memory device further comprises: a first bit line connected to a drain of the memory cell; a second bit line connected to a source of the memory cell; a first power supply line for supplying a first power supply voltage; a second power supply line for supplying a second power supply voltage; a first switch element for switching between a connection of the first bit line with the first power supply line and a connection of the first bit line with the second power supply line; and a second switch element for switching between a connection of the second bit line with the second power supply line and a connection of the second bit line with the first power supply line, wherein a potential of the first power supply voltage is different from a potential of the second power supply voltage, and the first switch element and the second switch element are controlled such that power supply voltages supplied between the source and the drain of the memory cell are reversed based on the flag signal output from the flag circuit.