Patent ID: 8402248

Claim:
A method in a network element for translating a logical memory address into a physical memory address, the network element including a plurality of memory types and memory sizes, the method comprising the steps of: receiving a memory access request for a data structure with a logical memory address that includes a region identifier and an offset into the region, wherein the region identifier identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on one or more processing requirements provided by a software programmer and a set of one or more available memories of the network element; accessing a region mapping table entry corresponding to the region identifier in a region mapping table that identifies the set of region attributes that are associated with the region; performing the following steps using at least a portion of the set of region attributes: determining an access target for the memory access request including a target class that identifies a class of memory, a target instance that identifies an instance within the class of memory, and a subtarget that identifies a particular physical address space of the instance within the class of memory; determining a physical memory address offset within the determined access target; and generating a physical memory address that includes: a network routing information portion that includes information to route the physical memory address to the target instance, and an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.