Patent ID: 7480181

Claim:
A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising: a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits; a state machine for controlling a read operation on a designated group of pages; said state machine sensing and latching a page of data in each of a series of reading cycles, wherein the sensing and latching in a current reading cycle are directed to a current page of data on a current wordline and are performed responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom; said state machine preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and said state machine performing in the current reading cycle, other than the first reading cycle, said sensing and latching of the current page while outputting a previous page sensed and latched in the just passed reading cycle.