Patent ID: 7876129

Claim:
An input/output (I/O) circuit having an output stage that includes a PMOS driver transistor connected between a positive supply voltage and an output node, the PMOS driver transistor having a gate electrode connected to a pull-up node, and an NMOS driver transistor connected between a negative supply voltage and the output node, the NMOS driver transistor having a gate electrode connected to a pull-down node, the I/O circuitry further comprising: first pre-driver circuitry connected directly to the pull-up node for providing a P-gate drive signal to the gate electrode of the PMOS driver transistor; second pre-driver circuitry connected directly to the pull-down node for providing an N-gate drive signal to the gate electrode of the NMOS driver transistor; a first feedback capacitor connected between the pull-up node and the output node; a second feedback capacitor connected between the pull-down node and the output node; capacitive feedback control circuitry connected between the output pad and the first and second feedback capacitors for controlling the time and voltage level at which the first and second feedback capacitors are applied to the pull-up and pull-down nodes, respectively the capacitive feedback control circuitry comprising first active feedback control circuitry connected between the output node and the pull-up node for controlling the P-gate drive signal; and second active feedback control circuitry connected between the output node and the pull-down node for controlling the N-gate drive signal; a first transmission gate connected between the first feedback capacitor and the output node; a first series of inverters connected to the first transmission gate for controlling the first transmission gate; a second transmission gate connected between the second feedback capacitor and the output node; and a second series of inverters connected to the second transmission gate for controlling the second transmission gate.