Patent ID: 7779254

Claim:
A system for extending multiple independent levels of security, comprising: a processing unit suitable for operation in a plurality of security levels; a bus controller operatively coupled to the processing unit, the bus controller including: security control logic for restricting access and flow of information between a physical memory and a plurality of input/output buses; and partition protection logic, the partition protection logic being configured for monitoring accesses to the physical memory, the partition protection logic including a set of registers for indicating which regions of the physical memory and an input/output memory are accessible and for indicating partition activity, the partition protection logic being configured for reporting invalid accesses to a system master and for prohibiting future access to physical memory until approval is provided by the system master, wherein the bus controller employs base address registers to allocate and map the physical memory to control which partitions of the physical memory are accessible to each of the plurality of buses, extending multiple independent levels of security to the plurality of input/output buses.