Patent ID: 7160778

Claim:
A method of manufacturing a semiconductor device, comprising: forming a pair of first source/drain regions apart from each other on a silicon substrate; forming a buffer oxide layer having a vertical transistor forming region exposing the pair of first source/drain regions; forming a first silicon epitaxial layer in the vertical transistor forming region; etching the buffer oxide layer so as to form a vertical gate forming region at a position laterally exterior to the pair of first source/drain regions; forming a vertical gate insulation layer in the vertical gate forming region; forming a second silicon epitaxial layer respectively in the vertical gate forming region and on the first silicon epitaxial layer; forming a pair of second source/drain regions, at positions above the pair of first source/drain regions, in the second silicon epitaxial layer formed on the first silicon epitaxial layer; and forming a plurality of vertical gates respectively connected to the second silicon epitaxial layer formed on the gate insulation layer and to the pair of second source/drain regions.