Patent ID: 8005884

Claim:
A processing device implemented method comprising: initiating a division operation in the processing device, wherein said operation comprises dividing a first operand by a second operand; calculating an intermediate floating-point (FP) quotient of the division operation with a first number of precision bits less than or equal to a second number of precision bits used by the processing device to represent a FP numeric value; determining a sign and a magnitude of a single remainder of the division operation; selecting the intermediate FP quotient to be a final FP quotient, in response to determining the magnitude of the single remainder is less than a given threshold; in response to determining the magnitude of the single remainder is not less than the given threshold: selecting a sum of the intermediate FP quotient and one unit in last place (ulp) to be the final FP quotient, in response to determining the sign of the single remainder is greater than zero; and selecting a difference of the intermediate FP quotient and one ulp to be the final FP quotient, in response to determining the sign of the single remainder is less than zero.