Patent ID: 8735243

Claim:
A method of forming a field effect transistor (FET) with a crystalline high-k dielectric, the method comprising: forming an interfacial oxide layer over a substrate; forming a crystalline high-k dielectric layer over the interfacial oxide layer, the crystalline high-k dielectric layer including a silicon stabilizing material therein configured to hinder one or more metals from penetrating across the crystalline high-k dielectric layer, the silicon stabilizing material introduced into the crystalline high-k dielectric layer by co-disposing silicon together with the crystalline high-k dielectric layer, wherein a concentration of silicon in the crystalline high-k dielectric layer is selected to be about 1%; forming a metal oxide cap layer on the crystalline high-k dielectric layer; forming a silicon oxide stabilizing agent layer on the metal oxide cap layer, the stabilizing agent layer having a thickness between about 0.1 nanometers (nm) and 0.5 nanometers thick, and the metal oxide cap layer having a thickness between about 0.2 nm and 0.7 nm; forming an electrically conductive metal gate electrode portion on the stabilizing agent layer; and forming a silicon gate electrode portion on the electrically conductive metal gate electrode portion, thereby forming the FET with the crystalline high-k dielectric.