Patent ID: 8710574

Claim:
An electronic memory cell comprising: an active area formed in a semi-conductor layer and including a channel provided between a source and a drain; a first gate provided at least over a first part of the channel; a portion of a first lateral spacer being provided against at least one lateral flank of the first gate, a part of which forms a second gate and is provided over at least a second part of the channel; one of the first gate and the second gate including a stack of layers, at least one of said layers being capable of storing electrical charges; and a portion of a second lateral spacer provided against at least one lateral flank of a block, the block being distinct from the first gate and provided over the semi-conductor layer, the second lateral spacer being in contact with the first lateral spacer and does not extend over the active area in a plan view, the first and second lateral spacers being composed of the same material or materials, and said portion of the second lateral spacer forming at least one part of an electrical contact pad electrically connected to the second gate.