Patent ID: 8637349

Claim:
A method for fabricating an integrated-circuit package comprising: providing a substrate; depositing an integrated-circuit chip in the integrated-circuit package; electrically connecting a plurality of electrical terminals on an external surface of the integrated-circuit package to the integrated-circuit chip; depositing a thin-film battery on the substrate, wherein the thin-film battery includes a first electrode that is not electrically connected to the integrated-circuit chip in the integrated-circuit package and a second electrode; electrically connecting the first electrode of the thin-film battery to an electrical terminal on an external surface of the integrated-circuit package; electrically connecting the second electrode of the thin-film battery to an electrical terminal on an external surface of the integrated-circuit package; encapsulating the integrated-circuit chip and the thin-film battery to form the integrated-circuit package, wherein the depositing of the integrated-circuit chip in the integrated-circuit package and the electrically connecting of the plurality of electrical terminals further includes: forming a first plurality of elongated metal-conductor leads, each of the first plurality of leads extending in a single plane, wherein the first plurality of leads are configured to form a die-support location, affixing the integrated-circuit chip to the die-support location, and electrically connecting the second electrode of the thin-film battery to the die-support location; and wherein the depositing of the thin-film battery includes: successively depositing a plurality of layers on one another as solid-state thin-film layers, wherein the plurality of layers includes a first electrode layer having the first electrode and a second electrode layer having the second electrode.