Patent ID: 7015851

Claim:
An improved analog to digital converter for converting an analog signal to a corrected digital output, comprising: an analog summing node having a first analog input, a second analog input, and an analog output, the analog signal connected to the first analog input of the analog summing node, the output of the analog summing node connected to the analog input of an analog to digital converter, a digital summing node having a first digital input, a second digital input, and a digital output, the digital output of the analog to digital converter connected to the first digital input of the digital summing node, a pseudorandom bitstream generator producing a serial digital bitstream, the serial digital bitstream feeding an analog filter, the output of the analog filter connected to the second analog input of the analog summing node, the serial bitstream feeding a digital filter, the output of the digital filter feeding the second digital input of the digital summing node, and the output of the digital summing node providing the corrected digital output.