Patent ID: 8587360

Claim:
A level-shifter circuit comprising: a first input configured to receive a first low-voltage phase signal, and having a first voltage dynamic with a first value; a second input configured to receive a second low-voltage phase signal, complementary with respect to the first low-voltage phase signal, and having the first voltage dynamic; a first output configured to supply a first high-voltage phase signal, level-shifted with respect to the first low-voltage phase signal and having a second voltage dynamic with a second value higher than the first value; a second output configured to supply a second high-voltage phase signal, level-shifted with respect to the second low-voltage phase signal and having the second voltage dynamic; a first transfer transistor coupled between a first reference terminal at a first reference voltage, and the second output, and having a control terminal configured to receive the first low-voltage phase signal; a second transfer transistor coupled between the first reference terminal and the first output, and having a control terminal configured to receive the second low-voltage phase signal; a third transfer transistor coupled between a second reference terminal at a second reference voltage having a value equal to the second value, and the second output; a fourth transfer transistor coupled between the second reference terminal and the first output; a plurality of protection transistors coupled in a cascode configuration and each coupled to a respective one of said first, second, third, and fourth transfer transistors, and configured to provide overvoltage protection between at least one of corresponding current-conduction terminals and control terminals, said plurality of protection transistors comprising a first protection transistor coupled between said first transfer transistor and the second output, and having a control terminal set at a voltage equal to the first value, a second protection transistor coupled between said second transfer transistor and the first output, and having a control terminal set at the voltage equal to the first value, a third protection transistor coupled between said third transfer transistor and the second output, and having a control terminal set at a biasing voltage, and a fourth protection transistor coupled between said fourth transfer transistor and the first output, and having a control terminal set at the biasing voltage; a control stage configured to supply a respective first control signal and second control signal to the control terminals of said third transfer transistor and said fourth transfer transistor; and a biasing stage configured to supply the biasing voltage to the control terminals of said third and said fourth protection transistors, the biasing voltage having a value based upon the values of the control signals on the control terminals of said third and said fourth transfer transistors.