Patent ID: 8248952

Claim:
A system for transferring data in a data processing system network, comprising: a determining mechanism for determining an adapter among a plurality of adapters that has a lowest transmit latency, wherein each one of the plurality of adapters is associated with a different one of a plurality of device drivers, and wherein each one of the plurality of adapters transmits data using a channel driver and an associated one of the plurality of device drivers; wherein for each one of the plurality of adapters: the different one of the plurality of device drivers that is associated with the one of the plurality of adapters calculates a transmit latency for the one of the plurality of adapters each time the different one of the plurality of device drivers receives the data from a channel system, which includes the channel driver, to be transmitted by the one of the plurality of adapters, wherein the different one of the plurality of device drivers updates one of a plurality of entries in a latency table to include the calculated transmit latency; wherein each time one of the plurality of device drivers receives the data: the channel system uses the plurality of entries to identify a particular one of the plurality of adapters that has a lowest transmit latency; and the channel system updates a latency register to store an identification of the particular one of the plurality of adapters that has the lowest transmit latency; wherein the transmit latency of each of the plurality of adapters is calculated by: dividing queued data to be transmitted by the one of the plurality of adapters by a bus bandwidth of the one of the plurality of adapters; and an assignment mechanism for assigning new data to be transferred to the particular one of the plurality of adapters that has the lowest transmit latency.