Patent ID: 7982260

Claim:
A non-volatile semiconductor memory device comprising: a memory string comprising a plurality of non-volatile memory cells connected in series, a drain-side selection transistor having one end connected to one end of the memory string, and a source-side selection transistor having one end connected to another end of the memory string, a bit line connected to another end of the drain-side selection transistor, a source line connected to another end of the source-side selection transistor; a substrate having a conductive layer as the source line formed on its surface; a plurality of columnar semiconductor layers formed on the substrate conductive layer and perpendicular to the substrate, each of the columnar semiconductor layers serving as a body of the memory string; an insulating layer formed around the columnar semiconductor layers, the insulating layer serving as a gate insulating film of the non-volatile memory cells, the drain-side selection transistor and the source-side selection transistor; and a plurality of electrode films formed around the insulating layer, the electrode films functioning as a gate electrode of the non-volatile memory cells, the drain-side selection transistor and the source-side selection transistor, a plurality of memory strings being connected to one bit line, the electrode films that serve as gate electrodes of the drain-side selection transistor and the source-side selection transistor comprising an laminate of two or more conductive films having different work functions, the work functions being set such that an inversion layer is formed under an edge of the gate electrode with a first voltage applied thereto, and an inversion layer is formed under the center of the gate electrode with a second voltage applied thereto, the absolute value of the first voltage being smaller than that of the second voltage.