Patent ID: 7655551

Claim:
A method of forming a complementary metal oxide semiconductor (CMOS) structure comprising: forming a first poly-Si containing material on a surface of a gate dielectric which is located on a semiconductor substrate, said first poly-Si containing material having a thickness of about 50 nm or less and having an interface with said gate dielectric; introducing dopant atoms into said first poly-Si containing material by gas phase doping, said gas phase doping comprises providing a gas including either a p-type dopant or an n-type dopant and annealing; depositing a second poly-Si containing material on a surface of said first poly-Si containing material, said second poly-Si containing material having a thickness that is greater than the first poly-Si containing material; selectively doping the second poly-Si-containing material to provide a doped second poly-Si containing material; and forming at least one field effect transistor (FET) on said semiconductor substrate, said at least one FET including a patterned stack comprising, from bottom to top, said gate dielectric, said first poly-Si containing material and said doped second poly-Si containing material.