Patent ID: 8202739

Claim:
A method of fabricating a semiconductor device, the method comprising: depositing a layer of insulating material on a substrate; during deposition of the layer of insulating material: after a first predetermined period of time, implanting a first dopant in the layer of insulating material and after a second predetermined period of time, implanting a second dopant in the layer of insulating material, after a third predetermined period of time, implanting a third dopant in the layer of insulating material, the first, second, and third predetermined periods of time together being less than a total deposition time, wherein the first, second, and third dopants are each detectable by physical, spectral, or chemical analysis; etching the layer of insulating material; during the etching, detecting depths of the first and second dopants; calculating, during the etching, a removal rate of the layer of insulating material from the depths of the first and second dopants; during the etching, detecting the depth of the third dopant; verifying, during the etching, the calculated removal rate of the layer of insulating material from the depth of the third dopant; and determining from the verified removal rate a position to stop the etching.