Patent ID: 7688122

Claim:
A charge pump comprising: a first input transistor operable to: receive an up (“UP”) signal; in response to receiving the UP signal, transmit a corresponding output current from a positive power supply to an output node; a second input transistor operable to: receive a down (“DN”) signal; in response to receiving the DN signal, transmit the corresponding output current from a negative power supply to the output node; a first cascode transistor and a second cascode transistor positioned in a first current path between the first input transistor and the output node; a third cascode transistor and a fourth cascode transistor positioned in a second current path between the second input transistor and the output node; a current mirror coupled to gates of the first, second, third, and fourth cascode transistors and operable to transmit a first bias voltage (V 1 ), a second bias voltage (V 2 ), a third bias voltage (V 3 ), and a fourth bias voltage (V 4 ) to the gates of the first, second, third, and fourth cascode transistors, wherein: the current mirror comprises a plurality of p-type metal-oxide-semiconductor (pMOS) field-effect transistors and a plurality of n-type metal-oxide-semiconductor (nMOS) field-effect transistors, each pMOS or nMOS transistor comprising a channel-width; the respective channel-widths of the pMOS and nMOS transistors determine values of the bias voltages V 1 -V 4 ; the bias voltages V 1 -V 4 respectively enable the first, second, third, and fourth cascode transistors to operate in a saturation region; and the plurality of pMOS transistors each have an equal channel-width (Wp); the plurality of nMOS transistors each have an equal channel-width (WN); and further comprising: one pMOS transistor having a channel-width of Wp/3; and one nMOS transistor having a channel-width of WN/3.