Patent ID: 7667268

Claim:
An isolated lateral DMOS transistor formed in a semiconductor substrate of a first conductivity type, the substrate not comprising an epitaxial layer, the isolated DMOS transistor comprising: a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate; a trench extending from a surface of the substrate at least to the floor isolation region, the trench comprising a central conductive portion and a dielectric material, the trench and the floor isolation region together forming an isolated pocket of the substrate, the dielectric material isolating the conductive portion from the isolated pocket and the substrate; a source region of the second conductivity type at the surface of the substrate in the isolated pocket; a drain region of the second conductivity type spaced apart from the source region at a surface of the substrate in the isolated pocket; a gate located atop a gate dielectric layer above an area of the surface of the substrate between the source region and the drain region; a drift region of the second conductivity type adjacent the surface of the substrate in the isolated pocket and the drain region, the drift region having a doping concentration less than the drain region; and a shallow trench isolation (STI) structure adjacent the surface of the substrate in the isolated pocket, the STI structure being enclosed on its sides and bottom by the drift region.