Patent ID: 8583944

Claim:
A circuit arrangement, comprising: a substitution block including a memory unit storing a plurality of substitution values and a plurality of ones-complement values that are corresponding ones-complements of the plurality of substitution values, wherein the substitution block, responsive to a request to read a specified one of the plurality of substitution values, concurrently reads and outputs the specified substitution value and the corresponding ones-complement value, and a power consumed in reading the specified one of the plurality of substitution values is uniform with a power consumed in reading another one of the plurality of substitution values; a cryptographic circuit coupled to the substitution block; a balancing circuit coupled to the substitution block; and wherein the cryptographic circuit and the balancing circuit are configured to concurrently operate on each of the plurality of substitution values and the corresponding one of the plurality of ones-complement values read from the memory unit, respectively; wherein power consumed together by the cryptographic circuit and the balancing circuit in the concurrent operation on the plurality of substitution values and the corresponding ones-complement values is uniform; wherein the balancing circuit is configured to obscure a current load imbalance between the cryptographic circuit and the balancing circuit by varying a current load that is driven by the balancing circuit; and wherein the balancing circuit is configured to vary the current load that is driven by ones-complement values according to a plurality of power consumption approximation models.