Patent ID: 7855455

Claim:
A structure comprising two device layers joined together to form an electronic system and further comprising: a first device layer disposed on a first substrate and comprising a first set of circuits and interconnect wiring; a second device layer disposed on a second substrate and comprising a second set of circuits and interconnect wiring; said first and said second device layers further connected using two sets of via connections comprising a first set of via connections that extend from below the top surface of said first device layer to the top surface of said second device layer and a second set of via connections that extend from said top surface of said first device layer through said second device layer, said second substrate and connecting to interconnect layers and input output terminals disposed on the back side of said second substrate; said structure further comprising an adhesive layer disposed between said top surface of said first device layer and said top surface of said second device layer and surrounding a portion of the height of said first and said second via connections; and further comprising an passivation coating to protect the sidewalls of said first and second sets of vias in said portions where they are surrounded by said adhesive layer.