Patent ID: 8492820

Claim:
An integrated circuit structure comprising: a substrate; a first trench of a deep trench isolation structure in said substrate; a shallow trench isolation structure in said substrate aligned above said first trench; a second trench of a deep trench capacitor in said substrate; a conformal insulator layer lining said first trench and only a lower portion of said second trench; a conductive material on said conformal insulator layer within both said first trench and said second trench, said shallow trench isolation structure above said first trench in combination with said conformal insulator layer lining said first trench encapsulate said conductive material within said first trench, and said conductive material within said second trench filling said second trench up to a top surface of said substrate such that, within an upper portion of said second trench, said conductive material is positioned laterally immediately adjacent to said substrate; a buried capacitor plate in said substrate adjacent to said lower portion of said second trench; and a device comprising a doped region at said top surface of said substrate and positioned laterally immediately adjacent to said conductive material in said upper portion of said second trench such that said device is electrically connected to said deep trench capacitor; and a second shallow trench isolation structure in said substrate and extending laterally from said substrate over only one edge of said second trench, said conductive material in said upper portion of said second trench being positioned laterally between said doped region and said second trench isolation structure, and said doped region, said conductive material in said upper portion of said second trench and said second shallow trench isolation structure having essentially coplanar top surfaces.