Patent ID: 7560358

Claim:
A method of preparing active silicon regions for CMOS or other devices, the method comprising: providing a structure having a first region and a second region, the structure comprising a silicon substrate having formed thereon a diffusion line that comprises: a first silicon layer; a silicon germanium layer over the first silicon layer; a second silicon layer over the silicon germanium layer; and a mask layer over the second silicon layer; forming an oxide layer in the first and second regions; forming a polysilicon layer over the oxide layer in the first and second regions; removing the polysilicon layer from the first region and depositing oxide therein in order to form an oxide anchor in the first region; removing the polysilicon layer from the second region; removing the silicon germanium layer from the diffusion line in order to create a gap therein; filling the gap with an electrically insulating material; and depositing oxide in the second region.