Patent ID: 8803145

Claim:
A bond pad condition sense structure in an integrated circuit device comprising: a bond pad; a patterned portion of a metal layer of the integrated circuit device wherein wirings of the integrated circuit are defined, coincident with a footprint area of said bond pad, having defined therein at least one interconnected first portion coupled to a node of the integrated circuit device, and to be externally accessible through a device pin coupled to said bond pad, and at least one interconnected second portion, interleaved with said at least one interconnected first portion and electrically isolated therefrom; a dielectric inter-metal isolation layer over said patterned portion; and a plurality of metal interconnects through said dielectric inter-metal isolation layer contacting said at least one interconnected first portion; said bond pad defined in an upper metal layer over said dielectric inter-metal isolation layer, coupled to said at least one interconnected second portion by said plurality of metal interconnects, and capacitively coupled to said at least one interconnected second portion.