Patent ID: 7747972

Claim:
A method for performing a timing analysis of an electronic circuit, the method comprising executing instructions stored on a computer-readable medium that cause a processor to: define a stage having an input and at least one output; determine a circuit portion connected to the at least one output influencing a timing behavior of said stage based on information characterizing a coupling of said circuit portion to said stage, wherein a portion of said electronic circuit coupled to said at least one output comprises a plurality of cells, and wherein said information comprises at least one shielding-grade value corresponding to each of the plurality of cells, wherein said shielding-grade value is a value representing magnitude of influence of a corresponding cell on the timing behavior of said stage, and wherein determining said circuit portion comprises adding shielding-grade values of successive cells connected in series relative to said at least one output of said stage until a sum of the added shielding-grade values is equal to or larger than a predetermined shielding-grade limit, wherein said circuit portion is determined to be the cells connected in series to said at least one output that correspond to the added shielding-grade values; and evaluate, for said timing analysis, the timing behavior of said stage based on a simulation of said stage and said circuit portion.