Patent ID: 6888483

Claim:
An input stage comprising: a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase Ï† 2 and substantially rejecting the signal corresponding to the output signal during the clock phase Ï† 1 ; and a track-and-hold amplifier tracking the input signal with its output signal during clock phase Ï† 1 and holding a sampled value during the clock phase Ï† 2 , the first autozero amplifier in each array receiving its input signal from the track-and-hold amplifier.