Patent ID: 7242244

Claim:
A method for testing a power output stage, the power output stage having at least one half bridge including an upper semiconductor switch and a lower semiconductor switch connected in series and to which an operating voltage is applied, and a control device operatively connected to the upper and lower semiconductor switches of the power output stage, wherein a junction point between the upper and lower semiconductor switches of the at least one half bridge form an output of the power output stage, said method comprising the steps of: performing, by the control device, a first test of the power output stage to determine whether the voltage at the output is within a predetermined central tolerance band when the first and second semiconductor switches of the at least one half bridge are not switched on; performing, by the control device, a second test to determine whether the voltage at the output is within a predetermined upper tolerance band when the upper semiconductor switch of the at least one half bridge is switched on; performing, by the control device, a third test to determine whether the voltage at the output is within a predetermined lower tolerance band when the lower semiconductor switch of the at least one half bridge is switched on; and identifying, by the control device, the power output stage as being free from defects which cause fault currents when the output voltage is within the respective tolerance bands in each of the first, second and third tests.