Patent ID: 7923645

Claim:
A method of fabricating a substrate comprising: patterning a photoresist layer on a first carrier to form a patterned photoresist layer, the patterned photoresist layer comprising circuit pattern artifacts; plating a first patterned etch stop layer on the first carrier and within the circuit pattern artifacts; plating a first patterned conductor layer on the first patterned etch stop layer and within the circuit pattern artifacts, wherein an etch stop metal of the first patterned etch stop layer is selectively etchable compared to a conductor metal of the first patterned conductor layer, wherein the first patterned etch stop layer and the first patterned conductor layer form a first etch stop metal protected circuit pattern; stripping the patterned photoresist layer; laminating the first etch stop metal protected circuit pattern to a second etch stop metal protected circuit pattern with a dielectric material, the second etch stop metal protected circuit pattern comprising a second patterned etch stop layer and a second patterned conductor layer; forming via apertures between the first etch stop metal protected circuit pattern and the second etch stop metal protected circuit pattern; forming electrically conductive vias in the via apertures comprising: forming a via conductor layer; and removing the via conductor layer except within the via apertures using a via conductor layer etch process, wherein the first patterned etch stop layer and the second patterned etch stop layer provide an etch stop for the via conductor layer etch process.