Patent ID: 7915923

Claim:
An apparatus for a communication system having a transmitter and a receiver, comprising: a driver block for coupling between the transmitter and the receiver to receive a transmission from the transmitter for processing by the driver block for providing the transmission after processing to the receiver; the driver block including a memory; the memory including programmable non-volatile memory cells for storing configuration settings associated with operation of the driver block; wherein the memory is coupled with control logic for providing a memory and control logic block; wherein the driver block further includes programmable input termination impedance, programmable output termination impedance, and a programmable signal detector, each of which are coupled to the memory and control logic block; wherein the programmable signal detector is coupled to receive the transmission from the transmitter and coupled to receive a threshold value from the memory and control logic block; wherein the threshold value is for determining whether the transmission to the driver block is present; wherein the programmable input termination impedance is coupled to the programmable signal detector to receive a switch signal for switching between a first input impedance for an active mode when the transmission is present and a second input impedance for a non-active mode when the transmission is not present; wherein the programmable input termination impedance is coupled to the memory and control logic block to set the first input impedance and the second input impedance; wherein the programmable output termination impedance is coupled to the programmable signal detector to receive the switch signal for switching between a first output impedance for the active mode when the transmission is present and a second output impedance for the non-active mode when the transmission is not present; and wherein the programmable output termination impedance is coupled to the memory and control logic block to set the first output impedance and the second output impedance.