Patent ID: 8135571

Claim:
A method for validating a specified manufacturing test rule pertaining to an electronic component, said method comprising the steps of: generating a file of test data sets, wherein each test data set in said file is valid for said rule, and each test data set includes a stimulus that comprises one or more single input vectors, and a set of results that are expected when the stimulus is applied to said electronic component; in response to recognizing that said electronic component has at least an analog element or a customized digital logic element, selectively creating a wrapper file to instantiate a base design corresponding to the electronic component and selectively adapting ports disclosed by the base design for simulation; constructing a testbench to prepare each of a plurality of testcases for simulation, wherein each testcase corresponds to the stimulus and the expected results of a different one of said test data sets, and each testcase is disposed to be simulated separately from every other testcase; selectively preparing each of said testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase; and comparing the simulated results and the corresponding expected results for each testcase, to determine whether there are any differences therebetween.