Patent ID: 6844576

Claim:
A design method for designing a master slice semiconductor integrated circuit having a placing and wiring method for a master slice type semiconductor integrated circuit conducted by an automatic placing and routing apparatus with respect to a master slice having a plurality of basic cells formed in a matrix, in which first and second power source wirings that are formed along a first direction and traverse the plurality of basic cells are connected to a plurality of signal wirings that are formed along the first direction or a second direction that traverses the first direction to provide connections within each of the plurality of basic cells and/or between the plurality of basic cells, the design method comprising: first step of registering in the automatic pacing and routing apparatus that defines the first direction or the second direction as a priority wiring direction definitions of effective pin positions that connect the plurality of signal wirings, the plurality of first and second power source wirings and the plurality of basic cells for each of layers in which the wirings are formed; second step of registering a net list that defines connections among the plurality of basic cells in the automatic placing and routing apparatus; and third step of determining placement of actual pin positions and wiring routes for the first and second power source wirings and the plurality of signal wirings based on data of the definitions of the effective pin positions and the net list, wherein the first step includes the step of defining the effective pin positions inside and outside a region between the first power source wiring and the second power source wiring, in a region corresponding to one of a plurality of component layers with which transistors of the plurality of basic cells are formed and on lattice grids along which the plurality of basic cells are formed, and the third step includes the step of connecting one of the plurality of component layers and two of the plurality of signal wirings at the determined pin positions, in which the two of the plurality of signal wirings are connected by the one component layer alone.