Patent ID: 7394157

Claim:
An integrated circuit comprising: a substrate including one or more devices; a first insulating layer overlying the substrate having one or more first level vias connecting to the one or more devices in the substrate; and a second insulating layer overlying the first insulating layer, the second insulating layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a first level metal line; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on a first level via of the number of first level vias, the barrier/adhesion layer including a layer substantially of zirconium or a layer substantially of hafnium; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.