Patent ID: 7512032

Claim:
An electronic device with non volatile memory cells, with optimized programming, of the type comprising at least one sector of matrix memory cells organized in rows and columns, the columns being organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and enabled respectively by a first select signal and by at least one second select signal generated by a decoder, the columns being associated with at least one Program Load PL controlled by a logic circuit and suitable for applying a programming pulse at a plurality of cells belonging to the enabled bit lines, further comprising a plurality of discharge transistors, each associated with a corresponding column and controlled by a control signal complementary to the control signal of the adjacent discharge transistor; and a column decoding which provides to enable the global bit lines with a number p of bits which address the first select signals and to enable the local bit lines with a number q of bits addressing the second select signals, one bit of the p bits and of the q bits is shared and suitable for activating the control signals.