Patent ID: 7790564

Claim:
A method of manufacturing a device structure in a semiconductor-on-insulator substrate having a semiconductor layer, a handle wafer, and a buried insulating layer between the semiconductor layer and the handle wafer, the method comprising: forming a first isolation region that includes a plurality of dielectric regions that extend from a top surface of the semiconductor layer to a first depth and surround a device region of the semiconductor layer; forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth shallower than the first depth and divides the device region into first and second doped regions each extending from the top surface to the buried insulating layer; and forming a third doped region of in the semiconductor layer that is oppositely doped relative to the first device region, that defines a first p-n junction along an interface of direct contact with the first device region, and that is located vertically in a stacked arrangement between the second isolation region and the buried insulating layer, wherein the first depth for the plurality of dielectric regions is less than the thickness of the semiconductor layer.