Patent ID: 7405606

Claim:
A D flip-flop, comprising: a master stage comprising a first data input line, a first clock line, a first data output line, and a storage circuit configured to store a signal applied at the first data input line; a slave stage comprising a second data input line operatively connected to the first data output line, a second clock line and a second data output line, and further comprising: a storage circuit; and a first switching element configured to electrically connect the input terminal of the storage circuit to the second data input line in response to a state of clock signal present on the second clock line, and a clock gating circuitry comprising an XNOR gate having two inputs connected to the first data input line and second data output line, respectively, and an output; a gating switching transistor having a gate connected to the output of the XNOR gate; and a gating inverter having an input adapted to connect to an external source of clock pulses, and output connected to the first clock line, and an enable input connected to the switching transistor as a load.