Patent ID: 7323372

Claim:
A method for providing electrostatic discharge protection during fabrication processing of photodiode array panels comprising the steps of: conducting a TFT deposition process to first generate a plurality of FET silicon dielectric layers, at least one of which is undoped; capping the dielectric layers by a thin metal layer having shorting bar traces for ESD protection; depositing a second metal layer for the traces in the array having contact with the shorting bar traces; metal etching to remove the metal shorting bars leaving metal traces with all metal traces still connected through undoped FET silicon bars to continuously provide a leakage current path for static charges, depositing a passivation layer; opening vias at each pixel in the array for photodiode bottom contact and a via above each FET silicon shorting bar; and, etching the FET silicon for diodes and simultaneously removing the undoped FET silicon bars to completely isolate all traces.