Patent ID: 7987014

Claim:
A method of sequencing wafer processing order to minimize sequence correlation in a cyclical two pattern model, the method comprising: generating a first sequence of wafer identifiers for specifying an order by which a first equipment processes wafers of a first wafer lot, wherein the first wafer lot has a predetermined number of slots and the first equipment includes a first subsystem for processing wafers in odd-numbered slots of the first wafer lot and a second subsystem for processing wafers in even-numbered slots of the first wafer lot; indexing the first sequence into a set of sequences, wherein the set contains sequences of wafer identifiers for select slots selected from one of the even-numbered slots and the odd-numbered slots; generating and indexing one or more downstream sequences of the wafer identifiers for specifying an order by which to process the wafers of the first wafer lot in one or more corresponding equipments downstream from the first equipment, wherein each of the generated sequences contains exactly a required number of wafer identifiers that match the wafer identifiers in every sequence previously indexed in the set; and processing the first wafer lot in one of the first and second subsystems of the first equipment in an order based on a first sequence indexed in the set of sequences.