Patent ID: 7610453

Claim:
A circuit for reordering each of a plurality of arrays in a sequence, the circuit comprising: a first port for receiving in a first serial order a number of values in each array in the sequence, wherein each array in the sequence has at least two dimensions; a generator of an address for each value in each array in the sequence, the address for each value in each array in the sequence being within a range of zero through one less than the number of values in the array; wherein the generator generates addresses for the arrays in the sequence in which the at least two dimensions are not equal and generates addresses for the arrays in the sequence in which the at least two dimensions are equal; a memory coupled to the first port and the generator, the memory adapted to perform an access to a location in the memory for each address from the generator, the access for each address including a read from the location that corresponds to the address before a write to the location in the memory, wherein the reads for the addresses serially read the values in a second serial order for each array in the sequence and the writes for the addresses serially write the values in the first serial order for each array in the sequence; and a second port coupled to the memory, the second port for transmitting in the second serial order the values in each array in the sequence, wherein the second serial order is different from the first serial order.