Patent ID: 7151406

Claim:
A class D amplifier output stage, comprising: an input configured to receive an input signal; an output configured to provide an output signal, the output being coupleable to a load; upper and lower output transistors operatively coupled to the output; a driver circuit configured to receive the input signal, and to generate non-overlapping first and second signals for driving the upper and lower output transistors, respectively, wherein the driver circuit is operative to apply the first and second drive signals to the upper and lower transistors, respectively, wherein a leading edge of the first drive signal follows a leading edge of the input signal by a dead time, and a trailing edge of the first drive signal is coincident with a trailing edge of the input signal, and wherein the input signal, the output signal, and the first and second drive signals have respective duty cycles; and a current sensing circuit configured to determine a direction of a current flowing through the load during at least two dead time intervals, wherein the driver circuit is further operative, in the event the direction of the load current corresponds to a first predetermined direction during the two dead time intervals, to vary the duty cycles of the respective first and second drive signals so that the leading edge of the first drive signal follows the leading edge of the input signal by a dead time, and the trailing edge of the first drive signal follows the trailing edge of the input signal by a dead time, thereby causing the duty cycle of the output signal to be substantially equal to the duty cycle of the input signal.