Patent ID: 8726110

Claim:
An integrated circuit, comprising: A. a first die that includes: i. a first interface having a TDI input signal lead, a TCK input signal lead, a TMS input signal lead, a TRST input signal lead, and a TDO output signal lead; ii. a second interface having a TDI output signal lead, a TCK output signal lead, a TMS output signal lead, a TRST output signal lead, and a TDO input signal lead; iii. first test access port circuitry having a TDI input, a TCK input, a TMS input, a TRST input, and a TDO output; and iv. first selection circuitry connected to the first interface, the second interface, and the first test access port circuitry, the first selection circuitry selectively connecting the signals on the first interface leads of the first die with the second interface leads of the first die and the inputs and output of the first test access port circuitry; C. a second die that is separate from the first die and that includes: i. a third interface having a TDI input signal lead, a TCK input signal lead, a TMS input signal lead, a TRST input signal lead, and a TDO output signal lead; ii. a fourth interface having a TDI output signal lead, a TCK output signal lead, a TMS output signal lead, a TRST output signal lead, and a TDO input signal lead; iii. second test access port circuitry having a TDI input, a TCK input, a TMS input, a TRST input, and a TDO output; and iv. second selection circuitry connected to the third interface, the fourth interface, and the second test access port circuitry, the second selection circuitry selectively connecting the signals on the third interface leads of the second die with the fourth interface leads, and the inputs and output of the second test access port circuitry; and D. leads connecting the signals on the second interface with the signals of the third interface.