Patent ID: 8691647

Claim:
A method of fabricating a semiconductor device formed on a semiconductor substrate having an active region, the method comprising the steps of: forming a gate dielectric layer on the semiconductor substrate, the gate dielectric layer comprising a first dielectric layer with a dielectric constant greater than SiO 2 and a second dielectric layer with a dielectric constant equal to SiO2, wherein the first dielectric layer directly contacts the semiconductor substrate, and wherein the second dielectric layer directly contacts the first dielectric layer; forming a source and a drain within the active region of the semiconductor substrate; forming a floating gate on the gate dielectric layer wherein the floating gate defines a channel interposed between the source and drain; forming a control gate above the floating gate; and forming an intergate dielectric layer interposed between the floating gate and the control gate, wherein the step of forming the intergate dielectric layer further includes the steps of: forming a first layer on the floating gate; forming a second layer on the first layer; and forming a third layer on the second layer, wherein each of the first, second and third layers have a dielectric constant greater than SiO 2 .