Patent ID: 7223658

Claim:
A method for fabricating a flash memory structure, comprising steps of: forming a first doped region in a semiconductor substrate; forming a V-groove in the semiconductor substrate and above the first doped region; forming two second doped regions in the semiconductor substrate and at two sides of the V-groove; forming a dielectric stack having a plurality of trapping sites on the surface of the V-groove including the steps of: forming a first oxide layer on the surface of the semiconductor substrate; forming a first nitride layer on the surface of the first oxide layer; forming a silicon-containing layer made of polysilicon or silicon germanium on the surface of the first nitride layer; forming a second nitride layer on the surface of the silicon-containing layer; and forming a second oxide layer on the surface of the second nitride layer; and forming a conductive layer on the surface of the dielectric stack and above the V-groove.