Patent ID: 7493470

Claim:
An apparatus comprising: a user-configured and extended digital processor core having a pipeline, comprising: a base instruction set, said set comprising a plurality of instructions adapted to run on said core; at least one extension instruction adapted to run on said core, said at least one extension instruction being user-designated, and optimized for real-time control applications; and extension hardware operatively coupled to said pipeline of said core, said extension hardware facilitating the running of said at least one extension instruction by said core; a storage device in data communication with said processor core; and at least one algorithm disposed at least partly in said storage device, said at least one algorithm being adapted to provide an output useful for real-time control applications based on at least one input and a plurality of state variables, said algorithm utilizing said at least one extension instruction to optimize the operation thereof; wherein said base instruction set comprises: a plurality of first instructions having a first length; a plurality of second instructions having a second length; and wherein said processor core further comprises logic adapted to decode and process both said first length and second length instructions from a single program having both first and second length instructions contained therein, wherein said first length is less than said second length; and said first instructions occur more frequently within said single program than said second instructions.