Patent ID: 7990788

Claim:
A semiconductor memory device having a refresh characteristic test circuit, the refresh characteristic test circuit comprising: a select signal generating unit for receiving first address signals and a test mode signal and generate select signals to select cell blocks; a main word line signal generating unit for receiving second address signals and the test mode signal and generate main word lines signals to select main word lines of the selected cell block; and a sub word line signal generating unit for receiving third address signals and the test mode signal and enable sub word lines of the selected main word line, wherein sub word line signal generating unit comprises: a first pre-decoder configured to pre-decode one part of first address signals in response to a test mode signal, and generate first pre-decoding signals to select a first group of adjacent sub word lines and a second group of adjacent sub word lines; a second pre-decoder configured to pre-decode the other part of the first address signals in response to the test mode signal, and generate second pre-decoding signals; and a decoder configured to decode the first pre-decoding signals and the second pre-decoding signals to enable a first sub word line of the first group and a fifth sub word line of the second group at a first time, enable a second sub word line of the first group and a sixth sub word line of the second group at a second time, enable a third sub word line of the first group and a seventh sub word line of the second group at a third time, and enable a fourth sub word line of the first group and an eight sub word line of the second group at a fourth time, wherein the first to eight sub word lines are associated with a selected main word line, and wherein said first, second, third and forth times are different from each other.