Patent ID: 7441105

Claim:
A processor, comprising: a plurality of registers, the plurality of registers arranged as a plurality of register groups including a first subset of registers and a second subset of registers, the second subset of registers including at least two registers not included in the first subset of registers; a first processing block having a first processing block first operand and a first processing block second operand coupled to the plurality of groups of registers through multiplexing circuitry, the multiplexing circuitry including more than one level of multiplexers, a second processing block having a first processing block first operand and a first processing block second operand coupled to the plurality of groups of registers through multiplexing circuitry, wherein the multiplexing circuitry allows the first processing block first operand, the first processing block second operand, the second processing block first operand, and the second processing block second operand only a total of two reads from the first subset of registers and only a total of two reads from the second subset of registers during a particular clock cycle.