Patent ID: 7327766

Claim:
A circuit configuration for receiving a data signal, comprising: a first connection for receiving the data signal; a second connection for receiving a first clock signal; an input buffer connected downstream of said first connection in a signal flow direction, said input buffer having a clock input; a clock-controllable memory element connected downstream of said input buffer; an output connection connected downstream of said memory element for carrying the data signal; a third connection supplying a second clock signal; a first multiplexer having a first input receiving the first clock signal, a second input receiving the second clock signal from said third connection, and an output connected to said clock input of said input buffer, said first multiplexer selectively supplying the first clock signal, in a first setting, and the second clock signal, in a second setting, to said input buffer for clock control; and a switchable signal path connected to bypass said memory element when said first multiplexer is in the second setting, wherein said output connection is coupled to an output of said switchable signal path.