Patent ID: 7336546

Claim:
A domino SRAM comprising in combination: a plurality of core memory cells in said domino SRAM organized in columns and rows with each of said columns comprised of a plurality of sub arrays of core memory cells, each of said sub arrays accessed by a local bit select logic; core memory cells in each sub array organized into a top group and a bottom group of core memory cells with half of the core memory cells in each sub array in the top group and half in the bottom group, with a local bit read line connected to said top group and a local bit read line connected to said bottom group; said local bit read line connected to said top group connected to one input of an OR gate and said local bit read line connected to said bottom group connected to another input of said OR gate; said OR gate located between said top group of core memory cells and said bottom group of core memory cells so that a core memory cell closest to said OR gate in said top group is the same distance from said OR gate as the core memory cell closest to said OR gate in said bottom group, the next closest in the top group is the same distance as the next closest in the bottom, and so on for all the core memory cells in the sub arrays.