Patent ID: 7533248

Claim:
A multithreaded processor, comprising: one or more processor cores each configured to concurrently execute instructions from a plurality of thread groups, wherein a given thread group comprises one or more instructions from one or more threads, wherein each processor core includes: a functional unit shared between the plurality of thread groups; one or more execution units; a multithreaded instruction source configured to request access to use the functional unit, and to provide an instruction from each of the plurality of thread groups in a given processor core execution cycle for execution by the one or more execution units and the functional unit; a processing unit coupled to the functional unit and configured to asynchronously request access to use the functional unit, wherein the processing unit is configured to independently execute instructions and to generate operations for execution by the functional unit, wherein the operations are unrelated to the instructions provided by the multithreaded instruction source; and arbitration functionality that includes a first indicator and a second indicator, wherein the first indicator indicates which of one of the processing unit and the multithreaded instruction source has priority for access to the functional unit, wherein the second indicator indicates which one of the plurality of thread groups has priority over remaining ones of the plurality of thread groups for access to the functional unit when the multithreaded instruction source has priority for access to the functional unit; wherein the functional unit is configured to execute one of an instruction provided by the multithreaded instruction source and an operation provided by the processing unit in a given cycle dependent upon which of the multithreaded instruction source and the processing unit has priority for access to the functional unit.