Patent ID: 8369161

Claim:
A method of controlling a semiconductor device having an insulation layer provided on a semiconductor substrate; a p-type semiconductor region provided on the insulation layer; an isolation region provided that surrounds the p-type semiconductor region to reach the insulation layer; an n-type source region and an n-type drain region provided on the p-type semiconductor region; a charge storage region provided above the p-type semiconductor region between the n-type source region and the n-type drain region, the method of controlling the semiconductor device comprising the steps of: applying a first voltage to the p-type semiconductor region to write a charge into the charge storage region while any of programming, erasing, and reading of a memory cell having the charge storage region is being performed; applying a second voltage, different from the first voltage, to the p-type semiconductor region to write a charge into the charge storage region while said any of programming, erasing, and reading of the memory cell is being performed; applying a third voltage to the p-type semiconductor region to erase the charge from the charge storage region; and applying a fourth voltage, lower than the third voltage, to the p-type semiconductor region to erase the charge from the charge storage region.