Patent ID: 8671245

Claim:
A master device for a computer system having a slave memory, the master device comprising: a plurality of cache lines for storing data; and a master interface for communicating with the slave memory, wherein, when processing a data request for data stored at a specified address in the slave memory: the master device transmits via the master interface to the slave memory (i) an address value corresponding to the specified address, (ii) a master identification value identifying the master device, and (iii) a line identification value in addition to the master identification value and identifying a subset of one or more of the cache lines in the master device, such that the slave memory transmits to the master device via the master interface (i) retrieved data corresponding to the address value, (ii) the master identification value, and (iii) the line identification value; and the master device (i) uses the master identification value to verify that the retrieved data corresponds to its own data request and (ii) uses the line identification value received from the slave memory to determine at least one of the cache lines into which to store the retrieved data, wherein, after the master device transmits the address value to the slave memory, but before the master device receives the retrieved data from the slave memory, (i) the master device does not retain the address value and (ii) the master device does not retain the line identification value.