Patent ID: 8236641

Claim:
A method for fabricating a semiconductor device comprising: forming a gate insulating film on a semiconductor region of a first conductivity type; forming a polycrystalline semiconductor layer on the gate insulating film; selectively etching the polycrystalline semiconductor layer to form a gate electrode pattern; forming a sidewall spacer on a side surface of the gate electrode pattern; injecting an ion of a first impurity element of a second conductivity type into the semiconductor region in self-alignment with the gate electrode pattern, before forming the sidewall spacer or after removing the sidewall spacer; activating the ion of the first impurity element by first annealing; injecting an ion of a second impurity element of the second conductivity type into the semiconductor region in self-alignment with the gate electrode pattern and the sidewall spacer, with the sidewall spacer formed on the side surface of the gate electrode pattern; and activating the ion of the second impurity element by second annealing, wherein a channel region is formed in a portion of the semiconductor region immediately below a gate electrode, wherein a source extension region and a drain extension region of the second conductivity are formed in a portion of the semiconductor region by the first impurity element, the source extension region and the drain extension region each having a junction depth which is less than or equal to 20 nm, the channel region being sandwiched between the source extension region and the drain extension region, wherein a source region of the second conductivity type is connected to one end of the source extension region, the one end of the source extension region being located farther from the channel region than another end thereof, the source region having a junction depth which is greater than the junction depth of the source extension region, wherein a drain region of the second conductivity type is connected to one end of the drain extension region, the one end of the drain extension region being located farther from the channel region than another end thereof, the drain region having a junction depth which is greater than the junction depth of the drain extension region, and wherein the first and second annealing are performed at a temperature ranging from 1273 K to 1600 K and for a time period on a double-logarithmic graph with an upper limit expressed by an equation (1) and a lower limit expressed by an equation (2): t= 3×10 −15 exp(49000/ T ) (1), and t= 3×10 −17 exp(49000/ T ) (2), where t represents a time period for the first and second annealing and T represents a temperature of the first and second annealing.