Patent ID: 8024680

Claim:
A method for forming a minimal leakage standard cell library, comprising: adding a plurality of cells associated with a first set of logic functions to the minimal leakage standard cell library using a processor, wherein each logic function in the first set of logic functions includes an unfolded base case cell and a folded cell; identifying a second set of logic functions, wherein the second set of logic functions is a subset of the first set of logic functions; adding a minimal leakage power cell for each of the identified set of logic functions to the minimal leakage standard cell library, wherein adding the leakage power cell includes: determining a base case for an unfolded implementation of the logic function, determining widths for transistors in a transistor topology used in the unfolded implementation of the logic function based on non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power for the transistor topology, assigning the determined widths to the transistors to generate a minimal leakage cell for the logic function.