Patent ID: 7626437

Claim:
An apparatus for converting a first differential clock signal and a second differential clock signal into a single-ended output clock signal, the apparatus comprising: a first voltage rail; a second voltage rail; an NMOS differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the NMOS differential amplifier receives the first differential clock signal, and wherein the second input terminal of the NMOS differential amplifier receives the second differential clock signal; a PMOS differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the PMOS differential amplifier receives a first differential clock signal, and wherein the second input terminal of the PMOS differential amplifier receives a second differential clock signal a bias circuit including: a first PMOS FET that is coupled to the PMOS differential amplifier at its drain and that is coupled to the first voltage rail at its source; a second PMOS FET that is diode-connected, that is coupled to the gate of the first PMOS FET at its gate, and that is coupled to the first voltage rail at its source; a first NMOS FET that is coupled to the NMOS differential amplifier at its drain and that is coupled to the second voltage rail at its source; a second NMOS FET that is coupled to the gate of the first NMOS FET at its gate, that is coupled to the second voltage rail at its source, and that is coupled to the drain of the second PMOS FET at its drain; and a third NMOS FET that is diode-connected, that is coupled to the gate of the second NMOS FET at its drain, and that is coupled to the second voltage rail at its source, wherein the third NMOS FET receives a bias current at its drain; a NAND gate that is coupled to the output terminals of the PMOS and NMOS differential amplifiers; a first inverter that is coupled to the NAND gate; and a second inverter that is coupled to the first inverter, wherein the second inverter outputs the single-ended output clock signal.