Patent ID: 7363556

Claim:
A testing apparatus for testing a memory-under-test, comprising: a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test; and a fail memory unit for storing the test result of said memory-under-test; wherein said fail memory unit further comprising: a write time measuring section for measuring a write time required for writing said test data per each of said pages; an integrating section for integrating said write time across a plurality of said pages set in advance; and a judging section for judging whether or not said memory-under-test is defect-free by comparing a value integrated by said integrating section with an expected value set in advance; wherein said integrating section integrates said write time per page group having said predetermined number of pages; and wherein said judging section judges whether or not said page group is defect-free based on an integral value of said write time per said page group.