Patent ID: 7952401

Claim:
A standby control circuit for an integrated circuit module having a primary clock circuit for providing a primary clock signal which is active in a normal operating mode of the integrated circuit module and inactive in a reduced power mode of the integrated circuit module, and a secondary clock circuit for providing a secondary clock signal independently of the mode of the integrated circuit module, the standby control circuit comprising: a first control circuit responsive, in the normal operating mode, to an asynchronous standby signal indicating a standby mode entry event to output, synchronous with the primary clock signal, a standby mode signal indicating a standby operating mode of the integrated circuit module; and a second control circuit responsive, in the reduced power mode, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with the secondary clock signal to indicate the standby operating mode, and wherein the first control circuit includes a first synchronizer circuit comprising at least two edge triggered registers that receive the primary clock signal as a clock input, the first synchronizer circuit has an input that receives the asynchronous standby signal, and an output for providing the standby mode signal synchronous with the primary clock signal, and wherein the first synchronizer circuit provides the standby mode signal within a first predetermined delay of the asynchronous standby signal.