Patent ID: 7809913

Claim:
A first memory module, comprising: a plurality of addressable storage locations for storing data; a first interface for receiving memory access commands for accessing said addressable storage locations; a second interface for re-transmitting memory access commands received in said first interface; control logic which supports a plurality of modes of operation, including a first mode and a second mode; wherein, in said first mode of operation, a first portion of said first interface receives a first portion of each memory access command at a first bus frequency, and a second portion of said first interface receives a second portion of each memory access command at a second bus frequency, said first bus frequency being different from said second bus frequency, and re-transmits at least a portion of said first portion of at least some said memory access commands at said first bus frequency using said second interface, and re-transmits at least a portion of said second portion of said at least some said memory access commands at said second bus frequency using said second interface to a second memory module; and wherein, in said second mode of operation, said first interface receives each memory access command at a single bus frequency, and in response thereto said control logic determines, with respect to each said memory access command received by said first interface, whether the respective memory access command addresses a data storage location in said first memory module, and (a) accesses a corresponding data storage location in said first memory module if the respective memory access command addresses a data storage location in said first memory module, and (b) re-transmits the respective memory access command at said single bus frequency to a second memory module if the respective memory access command does not address a data storage location in said first memory module.