Patent ID: 7816727

Claim:
A charge trapping memory comprising an array of memory cells, respective memory cells in the array including: a semiconductor body including a channel having a channel surface, and source and drain terminals adjacent the channel; a dielectric stack between the gate and the channel surface; the dielectric stack comprising: a tunneling dielectric layer contacting one of the gate and the channel surface; a charge trapping dielectric layer on the tunnel dielectric layer; a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising a first layer having a dielectric constant κ 1 contacting the charge trapping dielectric layer and a second layer contacting another one of the channel surface and the gate, the second layer having a dielectric constant κ 2 higher than κ 1 of the first layer, and the second layer having thickness less than κ 2 /κ 1 times that of the first layer.