Patent ID: 8001503

Claim:
A method of associating internal signals or ports in a design hierarchy of an integrated circuit design with a testcase to verify a defined aspect of the integrated circuit design, said design including a multitude of design files, the method comprising the steps of: inputting design files into a hierarchical path database generator; said hierarchical path database generator determining ports and signals in said design files, and storing said ports and signals in a hierarchical database in a logical hierarchical order, each of the ports and signals having a respective internal name local to a respective node of said integrated circuit design hierarchy and a path corresponding to the respective node; providing said testcase to verify a defined aspect of the integrated circuit design, said testcase specifying a plurality of internal signal or port names, each said internal signal or port name being local to a respective node of said integrated circuit design hierarchy and being specified without specifying a corresponding path name of the corresponding signal or port in the design hierarchy said integrated circuit design; responsive to providing said testcase to verify a defined aspect of the integrated circuit design, automatically parsing the testcase to identify at least some internal signal or port names therein; and for each of the internal signal and port names identified by said parsing the testcase, inputting the respective internal signal or port name into the hierarchical path database generator, and obtaining from the hierarchical path database generator a respective hierarchical path associated with the respective internal signal or port name for use by said testcase in accessing the corresponding signal or port, each said hierarchical path being in the design hierarchy of the integrated circuit design.