Patent ID: 7987339

Claim:
A system, comprising: a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; wherein said plurality of processors and said plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein the plurality of dynamically configurable communication elements are distinct from said plurality of processors; wherein, for each of said processors, said plurality of processor ports are configured for coupling to a first subset of said plurality of dynamically configurable communication elements; wherein, for each of said dynamically configurable communication elements, said plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of said plurality of said processors and a second subset of communication ports configured for coupling to a second subset of said plurality of dynamically configurable communication elements; wherein different pathways are operable to be created for data transfer among different subsets of said dynamically configurable communication elements, wherein each pathway is specified via one or more data elements, each comprising a plurality of portions, wherein each portion specifies configuration information of the data transfer for a dynamically configurable communication element along the pathway, wherein during data transfer each dynamically configurable communication element consumes its respective portion of the data element.