Patent ID: 8901645

Claim:
A semiconductor device comprising: a substrate; a word line in the substrate; a bit line contact plug on the semiconductor substrate; a bit line barrier layer on the bit line contact plug; a bit line electrode on the bit line barrier layer; a peripheral transistor insulating layer on the substrate; a peripheral transistor lower gate electrode on the peripheral transistor insulating layer; a peripheral transistor upper gate electrode on the peripheral transistor lower gate electrode; and a peripheral transistor capping layer on the peripheral transistor upper gate electrode, wherein the bit line electrode and the peripheral transistor upper gate electrode are at a same level, and the peripheral transistor upper gate electrode extends over the peripheral transistor lower gate electrode such that the peripheral transistor upper gate electrode and the peripheral transistor lower gate electrode are vertically apposed, and the peripheral transistor upper gate electrode and the peripheral transistor lower gate electrode are vertically aligned with each other.