Patent ID: 7153756

Claim:
A method of fabricating an SOI structure which comprises the steps of: (a) providing a substrate having at least one of active or passive elements on a surface thereof; (b) providing a device wafer having at least one of active or passive elements on a surface thereof; (c) forming an electrically insulating layer having a pair of opposed outer faces, one of said opposed outer faces disposed on a said surface of one of said substrate or said device wafer, said electrically insulating layer having an electrical interconnect structure disposed therewithin, a portion of said interconnect structure extending substantially to said one of said outer faces of said electrically insulating structure to make electrical contact with a device in at least one of the device wafer and the substrate; and (d) then bonding the other of said outer faces of said electrically insulating layer to the said surface of the other of said substrate or device wafer; further including the steps of forming an electrical insulation on at least one of said electrically insulating layer, said substrate or said device wafer insulating said interconnect structure from said device in said at least one of the device wafer and the substrate and applying a voltage across said electrical insulation to break down said electrical insulation and provide interconnection between said interconnect structure and said device.