Patent ID: 8243516

Claim:
An integrated circuit memory device comprising: a plurality of NAND-type flash memory cells; and a synchronous NAND interface comprising a single standard NAND flash interface pin arrangement and a clock (CLK) pin, the single standard NAND flash interface pin arrangement comprising pins being configured to allow the single standard NAND flash interface pin arrangement of the synchronous NAND interface to perform as a NAND interface, and wherein the pins are further configured to interface with a NOR-compatible memory interface to allow the NAND interface to perform as a NOR interface; wherein the single standard NAND flash interface pin arrangement comprises an address latch enable (ALE) pin and a command latch enable (CLE) pin, and wherein a first address line of the NOR-compatible memory interface is directly connected to the CLE pin and a second address line of the NOR-compatible memory interface is directly connected to the ALE pin to create a virtual address space such that writing through the NOR-compatible memory interface to a first address causes the memory device to receive a command via data pins of the NAND interface, writing through the NOR-compatible memory interface to a second address causes the memory device to receive an address via data pins of the NAND interface, and writing through the NOR-compatible memory interface to a third address causes the memory device to receive data via data pins of the NAND interface.