Patent ID: 8416612

Claim:
A memory comprising: memory devices that each store data of one bit; and a read unit that, by using one predetermined memory device of the memory devices that are included in a memory block having a predetermined unit number of the memory devices as an inversion flag device, is configured to: read out data of (the predetermined unit number −1) bits that is written in the other memory devices with the bits being inverted in a case where the data of one bit written in the inversion flag device is a first value representing any one of “0” and “1”, wherein the first value is written in the inversion flag device after at least one of the other memory devices is determined to be defective; and directly read out the data of (the predetermined unit number −1) bits that is written in the other memory devices in a case where the data of one bit written in the inversion flag device is a second value other than the first value.