Patent ID: 7262999

Claim:
A method for preventing read margin degradation for a memory array that is coupled to an ultra cycling memory device such that a first bit and a second bit of the ultra cycling memory device will be erased whenever all of memory devices of the memory array are erased, comprising: erasing the first bit and the second bit of the ultra cycling memory device when all of the memory devices of the memory array are erased; measuring a first current for the first bit of the ultra cycling memory device; programming the second bit of the ultra cycling memory device; measuring a second current for the first bit of the ultra cycling memory device; obtaining a first threshold voltage corresponding to the first current for the ultra cycling memory device; obtaining a second threshold voltage corresponding to the second current for the ultra cycling memory device; obtaining a threshold voltage difference between the first threshold voltage and the second threshold voltage; finding a cycling number based on the threshold voltage difference for the ultra cycling memory device; finding a threshold voltage shift based on the cycling number for the memory array; calculating an erase voltage based on the threshold voltage shift for the memory array; and erasing un-programmed memory devices of the memory array to reduce threshold voltages of the un-programmed memory devices of the memory array to a same extent as the threshold voltage shift after the memory array is programmed.