Patent ID: 8077508

Claim:
A circuit comprising: a plurality of magnetic random access memory cells each comprising a magnetic tunnel junction structure and an associated select transistor; one or more column decoders; one or more row decoders; a write driver circuit responsive to a data signal and read/write signals, the write driver circuit adapted to: cause a first signal line coupled to a first one of the magnetic random access memory cells to be tristated, and to cause a second signal line coupled to the first one of the magnetic random access memory cell to be at a first voltage during a read operation; cause the first signal line to be at a second voltage and the second signal line to be at the first voltage during a first write operation, wherein said second voltage is greater than said first voltage; and cause the first signal line to be at a third voltage and the second signal line to be at the second voltage during a second write operation, wherein said third voltage is smaller than said first voltage.