Patent ID: 7071725

Claim:
An apparatus for processing data, comprising: a plurality of input signal lines; a plurality of output signal lines; an electronic circuit configured to input first data from the plurality of input signal lines and to output second data to the plurality of output signal lines, the first data being one bit data represented by a combination of bits of the plurality of input signal lines, and the second data being one bit data represented by a combination of bits of the plurality of output signal lines, wherein the combination of bits of the plurality of signal lines of the one bit data “0” is a first bit status, the combination of bits of the plurality of signal lines of the one bit data “1” is a second bit status, and a hamming weight of the first bit status is equal to a hamming weight of the second bit status; and an input unit configured to input a control signal representing a distinction between a working phase and an idle phase, the working phase being a period to input and output the first bit status or the second bit status, and the idle phase being a period to input and output a third bit status as the combination of bit status of the plurality of signal lines of invalid data.