Patent ID: 6981101

Claim:
A multiprocessor system, comprising: a processing sub-system including a plurality of processors and a processor memory system; a scalable network operable to couple the processing sub-system to an input/output (I/O) sub-system; the I/O sub-system including a plurality of I/O interfaces; the I/O interfaces each operable to couple a peripheral device to the multiprocessor system and to store copies of data from the processor memory system in the local cache for use by the peripheral device; and a coherence domain comprising the processors and processor memory system of the processing sub-system and the local caches of the I/O sub-system, the local caches of the I/O subsystem operable to participate in the coherence domain through timed access to data in the processor memory system; wherein the I/O subsystem is operable to invalidate data upon expiration of a time interval and the processor memory system is operable to identify the data as free upon expiration of the time interval without sending any invalidation messages.