Patent ID: 8549204

Claim:
A host controller for controlling transactions in a multi-speed Universal Serial Bus (USB) environment comprising a first bus having a first data transfer rate, a second bus having a second data transfer rate different from the first data transfer rate, and multiple transaction translators configured to translate a first transaction transferred over the first bus at the first data transfer rate to a second transaction transferred over the second bus at the second data transfer rate, the host controller comprising: memory configured to store for each of different ones of the multiple transaction translators: an identifier; transaction translator capacity information indicating whether there is available capacity to translate a transaction; and a transaction list configured to store a plurality of requests to generate a split packet transaction and state information regarding execution status of the plurality of requests; and a scheduler configured to examine transaction lists and transaction translator capacity information for the different ones of the multiple transaction translators, execute in a predetermined period for one or more of the transaction lists a number of split packet transactions from the stored plurality of requests to generate a split packet transaction so that the split packet transactions included in the number have a capacity within the transaction translator capacity information, and to update the transaction translator capacity information based on state information and the capacity of the number of split packet transactions.