Patent ID: 8576625

Claim:
An apparatus, comprising: a memory array; and control circuitry coupled to the memory array, wherein the control circuitry is configured to based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges, wherein (i) N1 represents a number of memory cells of the memory array that have threshold voltages that fall into a first voltage range of the plurality of voltage ranges, (ii) N2 represents a number of memory cells of the memory array that have threshold voltages that fall into a second voltage range of the plurality of voltage ranges, and (iii) N represents a total number of memory cells of the memory array on which the plurality of read comparison results are based, determine (i) a first factor p1 that is based on a ratio of N1 and N, and (ii) a second factor p2 that is based on a ratio of N2 and N, based at least on (i) the number of memory cells that have threshold voltages in each of the plurality of voltage ranges and (ii) the first factor p1 and the second factor p2, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage, and read one or more of the plurality of memory cells based at least in part on the estimated offset amount.