Patent ID: 7714628

Claim:
A flip-flop comprising a transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit: the transfer unit comprising: a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal complementary to the sampled data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal; the storage unit comprising a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal, the storage unit comprising: drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error; the buffer unit for receiving input from at least one of the storage nodes and the redundant storage node and for providing an output sampled data signal.