Patent ID: 8223578

Claim:
A semiconductor device comprising: a plurality of terminals for receiving signals from outside of the semiconductor device and transmitting signals to outside of the semiconductor device; a first memory array including a plurality of dynamic type memory cells formed on a first semiconductor chip; and a memory controller being electrically connected to the plurality of terminals and the first memory array, and being formed on a second semiconductor chip other than the first semiconductor chip, wherein the plurality of dynamic type memory cells include a synchronous dynamic random access memory (SDRAM) cell, wherein the first memory array comprises at least two SDRAM banks of a first memory bank and a second memory bank, wherein the memory controller is configured to receive input signals from some of the plurality of terminals and access the first memory array by converting the input signals, and wherein the first memory array is accessible only via the memory controller in order to make signal communication between the outside of the semiconductor device and the first memory array, and wherein, in case that the memory controller receives a write access to the first memory array while the first memory bank performs a refresh operation, the memory controller accesses the second memory bank according to the write access.