Patent ID: 8125845

Claim:
A semiconductor integrated circuit device comprising: a plurality of word lines disposed approximately in parallel to a column direction; a plurality of bit-lines disposed approximately in parallel to a row direction; a plurality of ordinary memory cells connected to the plurality of word lines and the plurality of bit-lines; an access control circuit capable of selecting arbitrarily one word line from among the plurality of word lines in response to an address signal; and a plurality of sense-amplifiers connected to the plurality of bit-lines, wherein the semiconductor integrated circuit device further comprises a first replica bit-line, a second replica bit-line, a first replica memory cell, a second replica memory cell, a first logic circuit, and a second logic circuit, the first replica memory cell is connected to the first replica bit-line, and the second replica memory cell is connected to the second replica bit-line, an input terminal of the first logic circuit is connected to the first replica bit-line, and an output terminal of the first logic circuit is connected to the second replica bit-line, an input terminal of the second logic circuit is connected to the second replica bit-line, and a sense-amplifier enable signal is generated from an output terminal of the second logic circuit, and the sense-amplifier enable signal is supplied to the plurality of sense-amplifiers, whereby a plurality of read signals of the plurality of bit-lines are amplified by the plurality of sense-amplifiers, and a plurality of pieces of read data are generated from a plurality of output terminals of the plurality of sense-amplifiers.