Patent ID: 8432035

Claim:
A semiconductor device, comprising: a metallization system positioned above a substrate, said metallization system comprising: a metal line positioned in a dielectric layer and having a top surface, said metal line being comprised of a first metal material; a conductive cap layer positioned above said top surface, said conductive cap layer being comprised of a second metal material other than said first metal material; an etch stop layer is positioned above the conductive cap layer and substantially coplanar with and adjacent to a top surface of the dielectric layer; a via extending through said conductive cap layer and said etch stop layer and connecting to said top surface of said metal line, said via comprising a conductive barrier layer at least on sidewalls thereof; and an interface layer positioned between said conductive cap layer and said conductive barrier layer and between said top surface of the metal line and said conductive barrier layer, said interface layer comprised of a metal that is more noble than a metal of said conductive cap layer, wherein the interface layer is substantially restricted to a height that is equal to or less than a height level defined by a thickness of said etch stop layer.