Patent ID: 8305366

Claim:
A flat panel display, comprising: an image processing circuit comprising: a decoder for receiving an image signal and decoding the image signal into first complete frame image data and second complete frame image data; a scaler for generating first adjusted image data and second adjusted image data according to the first complete frame image data and the second complete frame image data; a memory module for storing the first adjusted image data and the second adjusted image data; a first transmitter for transferring the first adjusted image data; and a second transmitter for transferring the second adjusted image data, wherein the scaler transfers the first adjusted image data and the second adjusted image data to the first transmitter and the second transmitter, respectively; and a display module distinctly separate from the image processing circuit, the display module comprising: a panel; a first receiver for receiving the first adjusted image data; a second receiver for receiving the second adjusted image data; a compensated driving unit for outputting compensated driving data according to the first adjusted image data and the second adjusted image data; a timing controller for outputting the compensated driving data and a scan-starting signal according to timing; a data driver for receiving the compensated driving data and thus outputting a driving voltage to the panel; and a scan driver for receiving the scan-starting signal to sequentially control each row of pixels on the panel; wherein the display module does not include a memory module for storing image data.