Patent ID: 8223239

Claim:
A clock signal generation circuit of a delay locked loop type comprising: a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line based on a phase difference between the first and second clock signals in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal based on the phase difference between the first and second clock signals; a phase comparison section configured to compare an edge phase of the first clock signal with an edge phase of the second clock signal so as to output the phase difference by way of one of an up signal and a down signal to the delay amount controller and the pseudo-lock detection section, the up signal representing a phase difference between the first and second clock signals when the phase of the first clock signal is advanced with respect to the phase of the second clock signal, the down signal representing a phase difference between the first and second clock signals when the phase of the second clock signal is advanced with respect to the phase of the first clock signal, the phase comparison section comprising: (a) a first flip-flop having a clock terminal configured to receive the first clock signal; (b) a second flip-flop having a clock terminal configured to receive the second clock signal; and (c) a logical gate configured to perform a logical AND between outputs of the first and second flip-flops and generate reset signals for the first and second flip-flops at a same point in time; wherein the up and down signals are each generated for a respective period representing the corresponding phase difference between the first and second clock signals; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.