Patent ID: 7191113

Claim:
A method for modeling characteristics of a logical circuit, comprising: receiving input of a first plurality of values corresponding to points on an input voltage waveform of said logical circuit at discrete times, wherein said first plurality of values is a non-linear representation of said input voltage waveform; receiving input of a second plurality of values corresponding to points on an output voltage waveform of said logical circuit at said discrete times; selecting a particular one of said plurality of short-circuit current values; calculating a plurality of short-circuit current values forming a polygonal model of current through a given one of a complementary pair of transistors within said logical circuit for said discrete times in conformity with a model of said given transistor, a corresponding one of said first plurality of values, and a corresponding one of said second plurality of values, wherein a peak value of said polygonal model is equal to said selected particular one of said plurality of short-circuit current values, and wherein said polygonal model has a width equal to a time difference between a last one of said discrete times and a first one of said discrete times; and displaying a result of said calculating.