Patent ID: 7283530

Claim:
A system including: a network processor; a scheduler operatively connected within said network processor; a timing subsystem operatively coupled to the scheduler, said timing subsystem including: a search engine; an array of calendars with outputs operatively coupled to inputs of said search engine; a Winner Valid array operatively coupled to the calendar search engine; a Winning Location array operatively coupled to the calendar search engine; a Current Working Pointer array having outputs operatively coupled to the calendar search engine; a controller responsive to received signals to generate control signals which put the timing subsystem in an initial state and causes the calendar search engine to search identified calendars and load results of searches into the Winner Valid Array and Winning Location Array within a predefined time interval; and a final decision logic circuit arrangement operatively coupled to the Winning Location Array and the Winning Valid Array, wherein said final decision logic circuit arrangement parses information in said Winning Location Array and said Winning Valid Array to select one of the calendars as a Winner, selects a location in the Winner as Winning Location and generates a signal indicating the Winner and Winning Location are valid; and wherein the network processor includes: n flow queues, n>1; m port queues, m>1; and an embedded processor complex that routes packets into said flow queues wherein said scheduler is responsive to signals generated by the final decision logic circuit arrangement to cause the packets to be transported from the flow queues to the port queues.