Patent ID: 6903002

Claim:
A method of fabricating an integrated circuit comprising: forming a plurality of metal lines in a metal level, each metal line in the plurality of metal lines comprising a metal stack, at least two metal lines in the plurality of metal lines being spaced about 0.18 microns or less apart, wherein said metal stack comprises titanium layer, aluminum layer and titanium-tungsten layer; depositing a low-k dielectric over the plurality of metal lines such that an air gap is created at least between two metal lines in the plurality of metal lines, the low-k dielectric having a dielectric constant less than or equal to about 3.9; planarizing an entire surface of the low-k dielectric; and depositing a capping layer over the low-k dielectric such that the low-k dielectric forms a dielectric layer consisting substantially only of the low-k dielectric and air gaps.