Patent ID: 8392768

Claim:
A memory test system with advance features for completed memory system, comprising: a synchronous dynamic random access memory (SDRAM) for storing data; a system bus for sending a system bus command from a master; a SDRAM controller connected to the system bus for processing the system bus command and generating a SDRAM standard command; a high speed pad connected to the SDRAM controller and to the SDRAM through a PCB circuitry path for receiving and sending an electrical signal of the SDRAM; and a programmable loading test system for generating a test command to the SDRAM, wherein the programmable loading test system includes: a mode register controller for selecting and configuring a test mode for the programmable loading test system; a programmable loading command sequence generator connected to the mode register controller and the SDRAM controller for generating a programmable loading command sequence and a general purpose command sequence based on a configuration of the mode register controller; a programmable loading command address generator connected to the mode register controller and the SDRAM controller for generating a programmable loading command address and a general purpose command address based on the configuration of the mode register controller; a programmable loading data burst length generator connected to the mode register controller and the SDRAM controller for generating a programmable loading data burst length and a general purpose data burst length based on the configuration of the mode register controller; a programmable loading write data background generator connected to the mode register controller and the SDRAM controller for generating a programmable loading write data background and a general purpose write data background based on the configuration of the mode register controller; and a read data background checker connected to the mode register controller and the SDRAM controller for checking a read data output by the SDRAM controller based on the configuration of the mode register controller.