Patent ID: 7354820

Claim:
A method for fabricating a multi-layered semiconductor device, comprising: depositing a plurality of successive epitaxial layers on a substrate, said substrate extending laterally beyond said epitaxial layers; depositing a plurality of contact metals on said epitaxial layers, depositing a layer of self alignment material on said substrate, said self alignment material surrounding but not contacting said plurality of epitaxial layers or contact metals; depositing a planarization material over said, self alignment material, said plurality of epitaxial layers and said plurality of contact metals; etching said planarization material so it has a planar surface about the same level as the surface of the self-alignment material, and said plurality of contact metals protrude from said planar surface; and depositing a plurality of planar metals on said planar surface, each of said plurality of planar metals isolated from the others and each in electrical contact with a respective one of said plurality of contact metals.