Patent ID: 7199046

Claim:
A process for forming an integrated circuit structure comprising: forming a layer of dielectric material on a substrate, the layer of dielectric material comprising silicon dioxide or a dielectric material having a nominal dielectric constant value less than the dielectric constant of SiO 2 ; forming a hard mask layer on the dielectric layer, the hard mask layer comprising a nitride, a carbide, a refractory metal or a refractory metal nitride; forming a layer of tunable etch resistant anti-reflective (TERA) material on said hard mask layer; and forming a dual damascene structure for a metal interconnect, said dual damascene structure having a bottom opening extending to a surface of the substrate, and a top opening in communication with and wider than the bottom opening and extending to said layer of TERA material, wherein said layer of TERA material is etched to a width of the top opening and used as at least one of a top hard mask, a tunable anti-reflective coating, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer.