Patent ID: 8566487

Claim:
A monolithic packet engine system formed from a plurality of parallel packet engines, the system comprising: a plurality of packet engines configured to facilitate non-blocking communication, each packet engine including: a buffer system; a plurality of network ingress interfaces connected to the buffer system for accepting packets; a plurality of network egress interfaces; a plurality of egress queues having a first interface for enqueuing and dequeuing packets, and a second interface for transmitting packets via a network egress interface; and a chip-to-chip (C2C) interface coupled to another packet engine, wherein said C2C interface is configured to implement a common memory comprised of a plurality of buffer systems in said plurality of packet engines; and, wherein a first packet engine slices an accepted packet into bit slices, distributes bit slices to the buffer system of a second packet engine via the C2C interface and without using a switch fabric, reads the distributed bit slices from the buffer system of the second packet engine, and enqueues the packet for network transmission via a network egress interface from at least one of said first packet engine and said second packet engine.