Patent ID: 8081518

Claim:
A semiconductor storage device comprising: memory cells each of which includes a charge accumulation layer and a control gate, and which is capable of storing data of two or more values; a bit line connected to one of the memory cells; a sense amplifier carrying out sensing of the data stored in one of the memory cells a plurality of times at the time of reading; a clamp transistor forming a current path, one end of the current path being connected to the sense amplifier and the other end being connected to the bit line, the clamp transistor clamping the potential of the bit line; and a controller applying one of a first voltage and a second voltage higher than the first voltage to a gate electrode of the clamp transistor, wherein the controller applies the first voltage to the gate electrode to set the clamp transistor in an ON state, and applies the second voltage from the time after the first sensing to the time before the second sensing, and the controller switches from the second voltage to the first voltage before the second sensing.