Patent ID: 8520787

Claim:
An apparatus comprising: a plurality of receivers, each of the receivers being configured to receive a serial data stream, each of the receivers comprising: a shift register comprising a plurality of stages configured to propagate a stream of characters in sequence, each of the stages being configured to store a character, shift the character to a next stage of the shift register in response to a clock signal, a special character in the stream of characters, the special character comprising a character provided for timing alignment, and generate a signal indicative of detection of the special character; a count register configured to receive the signal generated by the shift mister, and to store a count upon receiving the signal generated by the shift register; and a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and configured to select one of the stages based on the count to generate an output for the multiplexer; and a multiplexer control circuit configured to control selection by the multiplexers such that the outputs of the multiplexers of the receivers are deskewed, wherein the count registers in the receivers are configured to store the counts with reference to a common timing reference count.