Patent ID: 7443702

Claim:
A start up circuit, comprising: a JFET transistor having a first terminal, a second terminal and a third terminal, in which the first terminal is coupled to receive a voltage source; a first transistor having a drain terminal, a source terminal and a gate terminal, in which the drain terminal of the first transistor is connected to the second terminal of the JFET transistor, the source terminal of the first transistor is coupled to provide a supply voltage to a control circuit of a power converter; a diode coupled from a transformer winding of the power converter to the control circuit for providing a further supply voltage to the control circuit; a second transistor having a drain terminal, a source terminal and a gate terminal, in which the drain terminal of the second transistor is coupled to the gate terminal of the first transistor and the third terminal of the JFET transistor, the gate terminal of the second transistor is coupled to receive a control signal, and the source terminal of the second transistor is coupled to a ground; and a resistive device connected from the third terminal of the JFET transistor to the second terminal of the JFET transistor; wherein the resistive device provides a bias voltage to turn on the first transistor and the JFET transistor when the second transistor is turned off, the control signal is coupled to turn on the second transistor for switching off the first transistor.