Patent ID: 7783866

Claim:
A computer implemented method for processing instructions, the computer implemented method comprising: selecting a first instruction of a set of instructions as a start instrumentation instruction, wherein an instrumentation instruction comprises an instruction that is executed to obtain information about an execution of an application; selecting a second instruction of the set of instructions as an end instrumentation instruction; selecting a target processor for executing instructions of the set of instructions in an instrumentation mode to form a selected target processor; executing the set of instructions using a normal set of processor resources in a current processor, wherein the normal set of processor resources comprises at least one of a pipeline, a cache, a translation look-aside buffer, and a performance counter; identifying the start instrumentation instruction for execution while executing the set of instructions using the normal set of processor resources in the current processor; identifying the selected target processor; responsive to identifying the start instrumentation instruction and the selected target processor: executing instructions of the set of instructions subsequent to the start instrumentation instruction in the instrumentation mode as instrumentation instructions using an alternate set of processor resources in the selected target processor; and locking the normal set of processor resources in a read only state; identifying the end instrumentation instruction for execution while executing the subsequent instructions in the instrumentation mode using the alternate set of processor resources in the selected target processor; and responsive to identifying the end instrumentation instruction: unlocking the normal set of processor resources from the read only state; and executing instructions of the set of instructions following the end instrumentation instruction using the normal set of processor resources in the current processor.