Patent ID: 8433961

Claim:
A data processing apparatus comprising: a circuit block to be tested; a plurality of scan chains, each scan chain in said plurality providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation; an input interface for receiving compressed input test data; decompression circuitry configured to support a plurality of decompression schemes associated with more than one test generation tool, the decompression circuitry being connected between the input interface and the plurality of scan chains; and configuration circuitry, responsive to a configuration stimulus, to configure the decompression circuitry to implement a selected decompression scheme from said plurality, wherein, on receipt of the compressed input test data from the input interface, the decompression circuitry applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to said plurality of scan chains.