Patent ID: 7046052

Claim:
A phase matched clock divider (PMCD) comprising: a first feed-through flip-flop having a clock input terminal coupled to receive a first input clock signal, an output terminal adapted to provide a first output clock signal, and a reset terminal; a plurality of series-connected flip-flops, each having a clock input terminal coupled to receive the first input clock signal, an output terminal adapted to provide a divided output clock signal, and a reset terminal; and reset logic adapted to provide a first reset signal to the reset terminal of the first feed-through flip-flop, and adapted to provide a second reset signal to the reset terminals of the plurality of series-connected flip-flops; wherein the first feed-through flip-flop includes an enable feed-through terminal, the enable feed-through terminal when receiving a feed-through mode signal enables the first input clock signal to be directly provided to the output terminal.