Patent ID: 7313038

Claim:
A semiconductor device comprising: a first write latch circuit group configured to latch data, and including a plurality of first write latch circuits corresponding to the size of the data being latched; a first nonvolatile memory element group including a plurality of first nonvolatile memory elements configured to be programmed with the latched data by electrically and irreversibly varying device characteristics of the first nonvolatile memory element group; a verify circuit configured to detect a defective first nonvolatile memory element in the first nonvolatile memory element group using the latched data and data read from the first nonvolatile memory element group; and a second nonvolatile memory element group including a plurality of second nonvolatile memory elements configured to be programmed with address data by electrically and irreversibly varying device characteristics of the second nonvolatile memory element group, wherein the address data indicates a position of the defective first nonvolatile memory element.