Patent ID: 8324741

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the four side surfaces of the main body, wherein: the main body includes pairs of layer portions, the pairs of layer portions being stacked in a stacking direction extending between the top surface and the bottom surface, each of the pairs of layer portions consisting of two layer portions that are stacked in the stacking direction; the pairs of layer portions include specific pairs of layer portions, each of the specific pairs of layer portions consisting of a first-type layer portion and a second-type layer portion; the specific pairs of layer portions are provided in an even number; each of the first-type layer portion and each of the second-type layer portion includes a semiconductor chip; a semiconductor chip of the first-type layer portion has a first surface and a second surface that face toward opposite directions, and a plurality of chip terminals provided on the first surface of the semiconductor chip of the first-type layer portion, the first surface and the second surface of the semiconductor chip of the first-type layer portion being substantially orthogonal to the stacking direction; a semiconductor chip of the second-type layer portion has a first surface and a second surface that face toward opposite directions, and a plurality of chip terminals provided on the first surface of the semiconductor chip of the second-type layer portion, the first surface and the second surface of the semiconductor chip of the second-type layer portion being substantially orthogonal to the stacking direction; the semiconductor chip of the first-type layer portion is non-malfunctioning; the first-type layer portion further includes a plurality of electrodes, each of the plurality of electrodes (1) being formed on the first surface of the semiconductor chip of the first-type layer portion, (2) having a bottom surface that is directly above the first surface of the semiconductor chip of the first-type layer portion, (3) extending along the first surface of the semiconductor chip of the first-type layer portion, and (4) connecting any one of the plurality of chip terminals of the semiconductor chip of the first-type layer portion to the wiring; the semiconductor chip of the second-type layer portion is malfunctioning; and the second-type layer portion does not include any electrode that extends along the first surface of the semiconductor chip of the second-type layer portion and that is connected to any one of the plurality of chip terminals of the semiconductor chip of the second-type layer portion, so that the semiconductor chip of the second-type layer portion is disabled.