Patent ID: 7999880

Claim:
A thin film transistor array panel comprising: a substrate; a gate line disposed on the substrate; a capacitive electrode disposed on the substrate wherein the capacitive electrode is separated from the gate line and is disposed at the same layer as the gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line and including a drain electrode; a coupling electrode connected to the drain electrode, disposed at the same layer as the drain electrode, overlapping the capacitive electrode, wherein a coupling capacitance is formed between the capacitive electrode and the coupling electrode; a passivation layer disposed on the gate line, the data line, and the thin film transistor and having a contact hole; and a pixel electrode including a first subpixel electrode connected to the drain electrode and a second subpixel electrode in contact with the capacitive electrode through the contact hole, wherein a planar area occupied by the contact hole is disposed within the coupling electrode.