Patent ID: 8335976

Claim:
A method for providing guaranteed component-failure correction and double-error correction in a memory system, the method comprising: accessing a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row-checkbit column containing row checkbits for each of the R rows, an inner-checkbit column containing R inner checkbits, and C-2 data-bit columns containing databits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components; calculating a row syndrome and an inner syndrome for the block of data, wherein the inner syndrome that results from any two-bit error in the same row is unique; if the row syndrome and the inner syndrome are both non-zero, determining from the row syndrome and the inner syndrome whether errors in the block of data are associated with a failed memory component; and if not, and if exactly two bits in the row syndrome are one, assuming that there exists a single-bit error in each of the two rows which have a row syndrome of one, and comparing the calculated inner syndrome against inner syndromes for all possible combinations of one-bit errors occurring in each of the two rows, and if the comparison matches a given inner syndrome, correcting the two bits associated with the given inner syndrome.