Patent ID: 7958396

Claim:
A system comprising: a first processor; at least one second processor, wherein each second processor comprises a respective internal component, each internal component performing a discrete function; a third processor; and a bus coupling said first processor, said at least one second processor, and the third processor, wherein the third processor is configured to monitor at least one interaction between the first processor and the at least one second processor via the bus, the third processor and each respective internal component of the at least one second processor being in direct connection via one or more wire connections, each of the one or more wire connections being independent of said bus, and said third processor being configured to monitor each internal component of the at least one second processor via a respective wire connection of the one or more wire connections, the third processor monitoring the at least one interaction between the first processor and the at least one second processor and each internal component, the third processor enforcing one of a plurality of selectable interaction policies between the first processor and the at least one second processor, and the enforced one interaction policy of the plurality of selectable interaction policies being selected, based at least in part, on either a particular process or an application running on the at least one second processor.