Patent ID: 7695897

Claim:
A method for forming an interconnect pattern of target critical dimensions in a dual damascene interlevel dielectric structure, comprising: forming a dual damascene interlevel dielectric structure comprising one or more interlevel dielectric layers that each has a dielectric constant ranging from about 1.5 to about 3.5 and one or more interlevel capping layers each located over one of the one or more interlevel dielectric layers and each having an etching selectivity of at least 10:1 over the interlevel dielectric layers, said one or more interlevel dielectric layers each comprises one or more materials selected from the group consisting of inorganic dielectric materials, C-doped oxides, F-doped oxides, fluorinated silica glass (FSG), dielectric polymers, organo-silicate materials, SiCOH-containing dielectric materials, spin-on dielectric materials, porous dielectric materials, non-porous dielectric materials, and mixtures or composites thereof, and said one or more interlevel capping layers each comprises one or more materials selected from the group consisting of organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, silsesquioxanes, silicon carbides, and mixtures or composites thereof; forming a hard mask stack over the dual damascene interlevel dielectric structure, wherein said hard mask stack comprises a lower nitride mask layer and an upper oxide mask layer, wherein the lower nitride mask layer and the upper oxide mask layer each has a thickness ranging from about 300 Å to about 700 Å; forming a resist layer having a thickness ranging from about 500 Å to about 2000 Å over the hard mask stack; patterning the resist layer to form one or more resist openings having critical dimensions that are smaller than the target critical dimensions by about 10 nm to about 20 nm and said target critical dimensions are from about 20 to about 60 nm; patterning the hard mask stack through the resist openings to form one or more hard mask openings, wherein the hard mask openings have the target critical dimensions; and patterning the dual damascene interlevel dielectric structure through the hard mask openings to form an interconnect pattern that is aligned with the hard mask openings and thereby also has the target critical dimensions, wherein the hard mask stack is patterned by a first reactive ion etching (RIE) step that uses a first gas mixture that consists of CHF 3 , CF 4 , O 2 and Ar and the dual damascene interlevel dielectric structure is patterned by a second RIE step that uses a second gas mixture that consists of C 4 F 8 , CHF 3 , N 2 , O 2 and Ar, and wherein the patterned resist layer is partially consumed during the first RIE step and is completely consumed during the second RIE step and further wherein only an upper portion of the upper oxide mask layer of the hard mask stack is removed during the second RIE step.