Patent ID: 7655968

Claim:
An in process semiconductor device, comprising: a plurality of container capacitor bottom plates, with each plate comprising, in at least one cross-sectional view, a bottom and first and second vertically oriented sides each having a height, with each side being unsupported along a majority of its height; a supporting layer having a bottom surface and a top surface, wherein the supporting layer contacts at least one of the vertically oriented sides of each container capacitor bottom plate of the plurality of bottom plates, and wherein majorities of the top and bottom surfaces of the supporting layer are free from contact with any other layer; wherein the plurality of container capacitor bottom plates comprises first, second, and third container capacitor bottom plates; the first and second capacitor bottom plates, in the at least one cross-sectional view, being spaced by a first distance with respect to a horizontal axis; the second and third capacitor bottom plates, in the at least one cross-sectional view, being spaced by a second distance with respect to the horizontal axis which is less than the first distance; the supporting layer, in the at least one cross-sectional view, bridging between the second and third capacitor bottom plates and not bridging between the first and second capacitor bottom plates; and the second capacitor bottom plate being located between the first capacitor bottom plate and the third capacitor bottom plate in the at least one cross-sectional view such that no other capacitor bottom plates are located between the first capacitor bottom plate and the second capacitor bottom plate or between the third capacitor bottom plate and the second capacitor bottom plate in the at least one cross-sectional view.