Patent ID: 7501879

Claim:
An eFuse circuit, comprising: a comparator having a first input and a second input, and further having an output providing a data output indication of the eFuse circuit; an eFuse cell comprising: an eFuse coupled to the first input of the comparator; a first transistor having a source-drain path coupling a first terminal of the eFuse to the first input of the comparator, and a gate coupled to receive a read signal; a second transistor having a source-drain path coupling the second terminal of the eFuse cell to a ground connection, and a gate coupled to receive the read signal; and a third transistor having a source drain path coupling a power supply connection to the first input of the comparator, and having a gate coupled to the second input of the comparator, and a reference generator circuit comprising: a resistor coupled to the second input of the comparator a first transistor having a source-drain path coupling a first terminal of the resistor to a second input of the comparator, and a gate coupled to receive the read signal; a second transistor having a source-drain path coupling the second terminal of the resistor to the ground connection, and a gate coupled to receive the read signal; and a third transistor having a source drain path coupling the power supply connection to the second input of the comparator, and having a gate coupled to the second input of the comparator.