Patent ID: 7852111

Claim:
A semiconductor device, comprising: an array circuit comprising a plurality of transistors connected in parallel, the respective impedance characteristics of which are known; an impedance comparing element that compares a reference impedance with an impedance of the array circuit and outputs a result of the comparison; a counter, which counts up or counts down the count value in accordance with the result of comparison output by the impedance comparing element; and a controller which assigns a transistor having a smallest deviation from a representative value of the impedances of the transistors constituting the array circuit, to the least significant bit of the counter, and assigns 2 (k−1) number of transistors of other transistors to the k-th bit, where k is a natural number equal to or greater than 2, and turns on or off each transistor assigned to each bit of the count value based on the value of each bit, wherein one or more of: the controller weights each of the transistors of the array circuit based on the deviation from the representative value of the impedances of the transistors, and assigns 2 (k−1) number of transistors to the k-th bit, where k is a natural number equal to or greater than 2; the counter cyclically counts up a count value or counts down the count value in accordance with the result of comparison output by the impedance comparing element, and the controller cyclically turns on or off each transistor assigned to each bit of the count value based on the count value of the counter.