Patent ID: 8164556

Claim:
A liquid crystal display, comprising: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the plurality of data lines, and a plurality of liquid crystal cells defined as first and second liquid crystal cell groups; a data driving circuit to supply a data voltage to the data lines in response to a polarity control signal; a gate driving circuit to supply a scanning pulse that swings between a gate high voltage and a gate low voltage to the gate lines; a first logic circuit to generate the polarity control signal differently for each frame period to maintain a polarity of the data voltage charged in the first liquid crystal cell group for two frame periods, and to invert one time a polarity of the data voltage charged in the second liquid crystal cell group for two frame periods; and a second logic circuit configured to: control the gate driving circuit to decrease the gate high voltage of the scanning pulse to a modulated voltage between the gate high voltage and the gate low voltage for a predetermined modulation time; and supply a control signal for modulating the scanning pulse to the gate driving circuit to control the modulation time, a falling edge of the control signal for modulating the scanning pulse being synchronized with the beginning of the predetermined modulation time, a rising edge of the control signal for modulating the scanning pulse being unsynchronized with the end of the predetermined modulation time, wherein the gate high voltage is about 20V, the gate low voltage is about −5V, and the modulated voltage is about 15V, and wherein the modulation time is more than 4.5 μs and equal or less than 5.5 μs.