Patent ID: 7786528

Claim:
A vertical semiconductor power MOS device with a buffer metal layer for copper bonding comprising a plurality of semiconductor power cells with each cell comprising a plurality of trench gates surrounded by a plurality of source regions above a plurality of body regions above a drain region disposed on a bottom surface of a substrate, wherein said trench MOSFET further comprising: a substrate of a first type conductivity; an epitaxial layer of said first type conductivity over said substrate, having a lower doping concentration than said substrate; a plurality of trenches extending into said epitaxial layer, surrounded by a plurality of source regions of said type conductivity above said body regions of the second type conductivity; a first insulating layer lining said trenches as gate dielectric; a doped polysilicon of the first type conductivity as gate regions overlying said first insulating layer; a second insulating layer disposed over said epitaxial layer as an oxide interlayer; a plurality of source-body contact trenches penetrating through said second insulating layer and said source regions, and into said body regions; a first front metal layer of Ti/TiN/W or Co/Ti/W comprising a Tungsten (W) layer deposited over a Ti/TiN or Co/TiN barrier layer, covering said second insulating layer and filling into said source-body trenches as trench metal plug connected to said source and body regions, and also as said buffer metal layer for minimizing copper wire bonding damage to semiconductor device; a second front metal disposed on front surface of device as source metal for Cu wire bonding; a backside metal disposed on backside of said substrate as drain metal.