Patent ID: 8437343

Claim:
A system on a chip (SoC) comprising: a protocol stack for a Peripheral Component Interconnect Express™ (PCIe™) load/store input/output communication protocol, the protocol stack being a transaction layer and a link layer; a physical (PHY) unit coupled to the protocol stack to provide communication between the SoC and a device coupled to the SoC via a physical link, the PHY unit of a low power communication protocol and including a physical unit circuit according to the low power communication protocol and a logical layer to interface the protocol stack to the physical unit circuit, the logical layer including a link training state machine to perform link training of the physical link and including a mapping logic to map first special symbols of the PCIe™ load/store input/output communication protocol to second special symbols of the low power communication protocol; and a second PHY unit separate from the PHY unit to provide communication between the SoC and the device via a sideband channel separate from the physical link, the sideband channel comprising a serial link, wherein the second PHY unit is to transmit a first presence signal to the device and to receive a second presence signal from the device, the link training state machine to configure the physical link responsive to receipt of the second presence signal in the second PHY unit.