Patent ID: 7605866

Claim:
A video processor, comprising: a video data input configured to receive a video file including a succession of video frames; a telecine and non-telecine progressive detector configured to receive the succession of video frames from the video data input and perform concurrent detection of a progressive scan pattern in frames not including a telecine pattern or a progressive scan pattern in frames including a telecine pattern; an interlaced detector configured to receive the succession of video frames and perform detection of an interlaced pattern if the telecine and non-telecine progressive detector does not detect a progressive scan pattern; a telecine inverter configured to receive the succession of video frames including a telecine pattern and drop frames to convert the succession of video frames including a telecine pattern to a succession of non-telecine frames; a deinterlacer configured to receive a succession of interlaced video frames and convert the succession of interlaced video frames to a succession of progressive scan video frames; a selector configured to select one of video data received by the video data input, video data output by the telecine inverter, or video data output by the deinterlacer for output; and a video data output configured to output a succession of non-telecine progressive video frames selected by the selector.