Patent ID: 7118957

Claim:
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a first insulation film over a substrate including a first region and a second region such that said first insulation film covers said first region and said second region; forming a first trench and a second trench in said first insulation film such that said first trench is located over said first region and said second trench is located over said second region of said substrate; filling said first trench and said second trench by a first conductive film to form a first electrode in said first trench and a second electrode in said second trench; forming a second insulation film over said interlayer insulation film so as to cover said first and second electrodes; forming a third trench in said second insulation film so as to expose said second electrode; forming a third electrode and a fourth electrode over said second insulation film simultaneously, wherein a capacitor element is formed by sandwiching said second insulation film between said third electrode and said first electrode and wherein said fourth electrode makes contact with said second electrode at said third trench; forming a third insulation film over said second insulation film so as to cover said third and fourth electrodes; and forming a fourth trench in said third insulation film, said step of forming said fourth trench being conducted while using said second insulation film as an etching stopper.