Patent ID: 6964887

Claim:
A semiconductor device manufacturing method comprising: a first step for mounting, in a wiring substrate which includes a first insulating layer with a first conductor layer having a wiring pattern on one surface side of the first insulating layer, a requisite number of semiconductor elements on the other surface side of the first insulating layer; a second step for forming a second insulating layer so as to completely cover said semiconductor elements, and forming a second conductor layer having a wiring pattern on said second insulating layer; a third step for forming via holes at certain positions in said second conductor layer and said second insulating layer so as to reach electrode terminals of said semiconductor elements and for also forming through holes between said first and second conductor layers at positions that avoid portions where said semiconductor elements are imbedded, so as to pass completely through in an up-and-down direction thereof; a fourth step for forming a third conductor layer over the entire top surface of said second conductive layer and bottom surface of said first conductive layer inclusive of inner wall surfaces of said via holes and said through holes; a fifth step for forming a wiring pattern on said third conductor layer, in such a way that the electrode terminals of said semiconductor elements are electrically connected to said second conductor layer via conductor layers on inner wall surfaces of said via holes and also in such a way that said second conductor layer is electrically connected to said first conductor layer via the conductor layers on inner wall surfaces of said through holes; a sixth step for obtaining a structure by forming a protective film covering said wiring patterns and said first and second insulating layers in such a way that terminal formation portions of said wiring pattern of said third conductor layer to which external connection terminals are to be connected are exposed on top and bottom surfaces of said structure; and a seventh step for dividing said structure obtained by the sixth step into semiconductor devices in such a way that at least one semiconductor element is contained in each semiconductor device.