Patent ID: 7005331

Claim:
A method for manufacturing a thin film transistor array substrate, comprising the steps of: providing a substrate; forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area; forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to define a source/drain contact hole, a data line contact hole and a terminal contact hole; and forming a transparent conductive layer, a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the data line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.