Patent ID: 7555629

Claim:
A memory card, comprising: a flash memory module, and a memory controller receiving an external command and an external address comprising a memory block address and start and end page addresses, and controlling a read operation and a write operation applied to the flash memory module, the memory controller comprising: a micro controller unit (MCU) converting the external address into a first internal address using a program stored in an internal memory associated with the MCU, and generating first command/address data in relation to the first internal address; a hardware accelerator (HWACC) generating a second internal address based on the first internal address and the external address in response to activation of a read signal and an acceleration enable signal and further generating second command/address data in relation to the second internal address; and a switch receiving the first command/address data from the MCU and the second command/address data from the HWACC, selecting between and outputting either the first command/address data or the second command/address data to the flash memory module; wherein the flash memory module reads data or writes data in response to the first command/address data or the second command/address data output by the switch, the MCU sets a hardware acceleration flag in the HWACC activating the acceleration enable signal after the flash memory module reads data using the first internal address, the HWACC activates the read signal whenever the external command received by the memory controller from the host system is associated with a read operation, the MCU transfers the external address to the HWACC after accessing the flash memory module in a read operation, and the HWACC comprises: a register storing a value of the hardware acceleration flag and a reference address derived from the external address; a selector circuit selecting between a current address and a next address in response to a mode signal and outputting the selected address as a new address; a judgment circuit detecting whether the reference address and the new address have a same memory block address, and whether the new address has a page address between the start page address and an end page address of the reference address; an address generator receiving the new address from the selector circuit and outputting the next address based on the new address; and, a state machine generating the second internal address based on the next address in response to the detection results received from the judgment circuit.