Patent ID: 8576525

Claim:
A serial surge suppression and overload protection optimization device comprising: an input terminal; an output terminal; and multiple surge suppression units serially connected between the input terminal and the output terminal, each surge suppression unit having: two parallel inductors; and multiple surge absorbing elements, each surge absorbing element connected to an output end of one of the parallel inductors and having a fuse serially connected therewith; whereby when surge energy of an intruding surge exceeds a threshold, each fuse serially connected with a corresponding surge absorbing element burns out to separate the surge absorbing element from a main power loop connected with the surge absorbing element for electrical safety protection, wherein: the serial surge suppression and overload protection optimization device has two surge suppression units and a ground wire; a pre-stage surge suppression unit has three surge absorbing elements, wherein each surge absorbing element has a fuse serially connected therewith for overload protection and is connected between two of the ground wire (G) and the output ends of the parallel inductors, and the three fuses are not serially connected to the line wire (L) and the neutral wire (N) of the main power loop; a post-stage surge suppression unit has three surge absorbing elements, wherein each surge absorbing element has a fuse serially connected therewith for overload protection and is connected between two of the ground wire (G) and the output ends of the parallel inductors, each fuse is serially connected with the line wire (L) or the neutral line (N) of the main power loop; two of the fuses are serially connected with the line wire (L) of the main power loop and the remaining one of the fuses is serially connected with the neutral wire (N) of the main power loop, or two of the fuses are serially connected with the neutral wire (N) of the main power loop and the remaining one of the fuses is serially connected with the line wire (L) of the main power loop; and a surge phase correction and compensation loop is connected to the output terminal and between the loop of the line wire (L) and the loop of the neutral wire (N) of the surge suppression device, and has a diode bridge, a zenor diode, a MOSFET, multiple capacitors, an inductor and a silicon controlled rectifier (SCR), the zenor diode, the MOSFET and the capacitors are parallelly and sequentially connected to an output terminal of the diode bridge, the inductor serves to adjust a phase of a bypass pulse, the SCR is serially connected to the cathode of the zenor diode through the inductor so that the diode bridge is operated to supply power to the capacitors, and one end of each capacitor is connected to the MOSFET, the MOSFET short-circuited when activated so that the capacitors discharge all power stored therein.