Patent ID: 8134395

Claim:
A digital switching circuit for receiving a clock signal and a data signal and for generating a first output signal and a second output signal based on the clock signal and the data signal, the digital switching circuit comprising: an input stage comprising: a clock input for receiving the clock signal, a data input for receiving the data signal, a first set-reset latch for generating a first node signal on a first node, and a second set-reset latch for generating a second node signal on a second node, and an output stage comprising: a first NAND gate having: a first A input connected to the first node of the input stage, a first B input connected to a second NAND gate output, a first leakage current control input connected to the second node of the input stage, and a first NAND gate output for providing the first output signal, a second NAND gate having: a second A input connected to the second node of the input stage, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first node of the input stage, and the second NAND gate output for providing the second output signal, wherein leakage current through the first NAND gate is substantially reduced based on application of the second node signal to the first leakage current control input, and leakage current through the second NAND gate is substantially reduced based on application of the first node signal to the second leakage current control input.