Patent ID: 7366953

Claim:
A method of identifying partially good cache memory of a computing system at time of power-on, comprising: performing built-in-self-test on said cache memory at said time of power-on to determine a number of defective subdivisions present in said cache memory of different types; determining a number of said defective subdivisions of said different types which are not repairable by an on-chip self-repair technique; reporting said number of said non-repairable defective subdivisions to a service element; logically deleting said non-repairable defective subdivision from a configuration of said computing system; and powering up and operating said computing system in a normal operational mode without said logically deleted subdivision, and wherein said computing system includes a plurality of processors, each processor having one said cache memory, said cache memory further comprising means for determining whether a number of said non-repairable defective subdivisions exceeds a threshold for one of said processors, and removing said one processor from said configuration of said computing system when said threshold is exceeded, and wherein said cache memory is an N-way set associative memory, and at least one of said types of subdivisions is a set of said cache memory, and said removing occurs when two or more of said sets of said cache memory of said one processor are determined by said BIST to be defective, and a replacement of said one defective processor with a spare processor included in said computing system does not require said spare processor to be physically moved.