Patent ID: 7075148

Claim:
A semiconductor memory having a multiplicity of memory cells, each of the memory cells comprising: a semiconductor layer arranged on a substrate, a semiconductor surface of the semiconductor layer having at least one step between a relatively deeper semiconductor region and a relatively higher semiconductor region that is higher in a direction normal to the substrate; N conductively doped deeper contact regions formed in the deeper semiconductor region, and at least one conductively doped higher contact region formed in the higher semiconductor region, each of the doped deeper contact regions being electrically connected to precisely one adjoining deeper contact and each of the doped higher contact regions being electrically connected to precisely one adjoining higher contact; N channel regions, wherein a separate channel region extends in the semiconductor layer between each doped deeper contact region and the doped higher contact region; at least one electrically insulating trapping layer designed for trapping and emitting charge carriers, the trapping layer being arranged on a gate oxide layer adjoining the channel regions; and at least one gate electrode for controlling electrical conductivity of the channel region, a control oxide layer being arranged between the gate electrode and the trapping layer, the deeper contacts and the higher contacts being arranged in a regular matrix-like cell array with rows and columns, the deeper contacts and the higher contacts being arranged alternately along each of the rows and columns.