Patent ID: 7326992

Claim:
An integrated circuit comprising a memory cell comprising: a first source/drain region in a semiconductor substrate, and a second source/drain region in the semiconductor substrate; a channel region located in the semiconductor substrate and extending between the first and second source/drain regions, the channel region comprising a first portion adjacent to the first source/drain region, a second portion adjacent to the second source/drain region, and a third portion between the first and second portions; a first floating gate adjacent to the first portion of the channel region and having a first width measured along a line extending from the first source/drain region to the second source/drain region along the channel region; a second floating gate adjacent to the second portion of the channel region and having a second width along said line; a first conductive gate for controlling a conductivity of the third portion of the channel region, the first conductive gate having a third width along said line; wherein the first floating gate is adjacent to a first side of the first conductive gate, the second floating gate is adjacent to a second side of the first conductive gate, and the first conductive gate has a top which meets the first and second sides; wherein the integrated circuit comprises a dielectric completely covering the first and second sides and the top of the first conductive gate, the dielectric being in physical contact with all of the first and second sides and all of the top of the first conductive gate; wherein the first conductive gate does not overlie the first and second floating gates; wherein the third width is smaller than at least one of the first and second widths.