Patent ID: 7536659

Claim:
A semiconductor memory device provided with a memory array region which is configured in such a way that the two-dimensional placement of a memory cell region where memory cells are arranged in the form of a matrix, plural circuits which selectively point to rows and columns in the memory cell region and which read and write data from and to the memory cells selectively pointed to, and a data input/output circuit which inputs the read data and which outputs the written data takes on the shape of a quadrilateral and a control region which is configured in such a way that the two-dimensional placement of an address input circuit which selectively outputs an address which specifies a row and a column according to an address control signal, a control circuit which sends out the address control signal according to an external control signal, a refresh circuit which produces the address control signal instead of the external control signal during standby to effect the refresh operation of the memory cell region, a timing generator circuit which adjusts the timings of the operations of the address input circuit, the control circuit, and the refresh circuit, and a clock generator circuit which synchronizes the data input/output circuit, the address input circuit, the control circuit, the refresh circuit, and the timing generator circuit takes on the shape of a quadrilateral, wherein the control region is connected to the memory array region with the mutually connected sides of both the regions differing in length.