Patent ID: 8112466

Claim:
A Field Programmable Gate Array (FPGA) comprising: a first computational block comprising: a multiplier configured to receive a first data input and a second data input; a first multiplexer comprising a dynamic select line and configured to receive a third data input; an accumulator configured to receive an output of the multiplier and an output of the first multiplexer; a second multiplexer configured to receive an output of the multiplier and an output of the accumulator; a register configured to receive an output of the second multiplexer and to provide an output and a feedback to the first multiplexer; and a third multiplexer configured to receive the output of the register and to provide a first computational block output; and a second computational block cascaded with the first computational block, wherein the second computational block is configured to receive the output of the second multiplexor without using the first computational block output of the third multiplexor.