Patent ID: 7269080

Claim:
A nonvolatile phase change memory device comprising: a memory array formed by memory cells arranged in rows and columns, word lines and bit lines connected to terminals of memory cells arranged in a same row and, respectively, in a same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage to a first terminal and a second biasing voltage to a second terminal of an addressed memory cell; and wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage, wherein the biasing circuit is coupled to the row decoder and to the column decoder to further supply a third biasing voltage to a first terminal and a fourth biasing voltage to a second terminal of non-addressed memory cells wherein the third biasing voltage and the fourth biasing voltage are in the range between the first biasing voltage and the second biasing voltage.