Patent ID: 8450198

Claim:
A method of forming a graphene-based switching device, the method comprising: forming a template layer on a substrate, the template layer selected to facilitate single crystal growth of subsequent material formed thereupon; patterning a resist layer on a portion of the template layer corresponding to a location of a subsequent field effect transistor (FET) channel region; forming an amorphous layer over the template layer and patterned resist layer, and thereafter removing the patterned resist layer so as to expose the portion of the template layer corresponding to the channel region; forming a bottom electrode layer over the amorphous layer and the exposed portion of the template layer, wherein portions of the bottom electrode layer on the template layer are crystalline in structure and electrically conductive, while portions of the bottom electrode layer on the amorphous layer are amorphous and insulating; forming a bottom gate dielectric layer over the bottom electrode layer, wherein portions of the bottom gate dielectric layer on the crystalline bottom electrode layer are crystalline in structure and exhibit ferroelectric and piezoelectric properties, while portions of the bottom gate dielectric layer on the amorphous bottom electrode layer are amorphous, non-ferroelectric and non-piezoelectric; forming a bi-layer graphene over the bottom gate dielectric layer; forming source and drain contact electrodes at opposing ends of the bi-layer graphene, the bi-layer graphene defining the FET channel region; forming a top gate dielectric layer over the bi-layer graphene; and forming a top gate electrode over the top gate dielectric layer.