Patent ID: 7190630

Claim:
A semiconductor storage device in which, with a storage cell connected to each of plural bit lines, continuous access is performed by that the bit lines are successively selected and connected to an amplifier circuit, wherein physically contiguous bit lines are partitioned into basic bit line groups in each of which two or more basic decode units identified by a lower identification address of a prescribed number of bits are contiguously disposed with bit lines within the basic decode unit being identified by a same order among the basic decode units, wherein the basic decode unit is constituted by bit lines identified by an upper identification address of a prescribed number of bits, and the semiconductor storage device comprises: an upper identification address decoder for selecting a prescribed bit line within the basic decode unit; a lower identification address decoder for selecting a prescribed basic decode unit; and an address conversion part that allocates at least one of a start address or an end address in identification address represented by the upper identification address and the lower identification address that identify bit lines partitioned into a basic bit line group to bit lines in physical positions other than those of bit lines in both ends of the basic bit line group.