Patent ID: 8566657

Claim:
A method, comprising: a) shifting a first logic sequence into a first scan chain having a first plurality of scan blocks coupled together; b) outputting a second logic sequence from each of the plurality of scan blocks in the first scan chain to a respective scan block in a second scan chain, the step including i) switching an input of a flip-flop in each of a third plurality of scan blocks in a third scan chain from being configured to receive a signal from function logic to being configured to receive a signal output from a respective scan block in the first scan chain, ii) switching an input of a flip-flop in each scan block of the second scan chain from being configured to receive a signal from function logic to being configured to receive a signal output from a respective scan block in the third scan chain, iii) receiving the signal output from the scan block in the third scan chain at the respective input of the flip-flop in the scan block of the second scan chain, and iv) receiving the signal output from the scan block in the second scan chain at the respective input of the flip-flop in each scan block of the first scan chain; c) shifting a third logic sequence out of the second scan chain; and d) identifying at least one improperly functioning scan block of the first scan chain based on the third logic sequence shifted out of the second scan chain.