Patent ID: 8513999

Claim:
A semiconductor device comprising: a first master-slave flip-flop circuit having a first master latch circuit which receives and latches a first data signal in synchronism with a first clock signal and a first slave latch circuit which receives and latches said first data signal from said first master latch circuit in synchronism with a second clock signal; and a second master-slave flip-flop circuit disposed side by side with said first master-slave flip-flop circuit and having a second master latch circuit which receives and latches a second data signal in synchronism with a third clock signal and a second slave latch circuit which receives and latches said second data signal from said second master latch circuit in synchronism with a fourth clock signal, and wherein said second slave latch circuit of said second master-slave flip-flop circuit is disposed adjacent to said first master latch circuit of said first master-slave flip-flop circuit, and said second master latch circuit of said second master-slave flip-flop circuit is disposed adjacent to said first slave latch circuit of said first master-slave flip-flop circuit.