Patent ID: 7157762

Claim:
A semiconductor device comprising: a substrate having a cell array region and a peripheral circuit region; a first device isolation layer defining a cell active region in the cell array region; a second device isolation layer having first and second sidewalls, the second device isolation layer defining a peripheral active region in the peripheral circuit region; a cell gate pattern that includes a plurality of conductive layers crossing over the cell active region; and a peripheral gate pattern that includes a plurality of conductive layers crossing over the peripheral active region, a lowermost layer of the peripheral gate pattern having first and second sidewalls that are aligned with respective of either the first and second sidewalls of the second device isolation layer or a vertical extension of the first and second sidewalls of the second device isolation layer, wherein the lowest of the plurality of conductive layers of the cell gate pattern and the lowest of the plurality of conductive layers of the peripheral gate pattern comprise different conductive layers.