Patent ID: 7965573

Claim:
A semiconductor device comprising: an internal power voltage generation means for producing an internal power voltage using an external power voltage under a control of a test mode internal power off signal to disable an internal power at a test mode; a plurality of individual power-up signal generation means for detecting a voltage levels of the external power voltage and a voltage level of the internal power voltage and for producing an individual power-up signals corresponding to the external power voltage detection and an individual power-up signal corresponding to the internal power voltage detection; a multiplexing means for, in response to the test mode internal power off signal, selecting one of the individual power-up signals corresponding to the internal power voltage detection and an alternate signal and outputting the selected one as an output signal of the multiplexing means; and a final power-up signal generating means for producing a final power-up signal in response to the individual power-up signal corresponding to the internal power voltage detection and the output signal of the multiplexing means.