Patent ID: 8053880

Claim:
A semiconductor package assembly, comprising: a first semiconductor package, including: a first substrate having first and second opposed surfaces, the first substrate having a first set of contact pads on the first surface and a second set of contact pads on the second surface, a first set of one or more semiconductor die mounted on the first surface of the first substrate, a first encapsulant for encapsulating at least the first semiconductor die, the encapsulant having a plurality of recesses in a surface of the encapsulant, the plurality of recesses not exposing electrical conductors encapsulated within the first encapsulant, and a plurality of electrical connectors, an electrical connector of the plurality of electrical connectors including: a base portion affixed to a contact pad of the second set of contact pads on the second surface of the first substrate, a neck portion extending from the base portion away from the contact pad, the neck portion being outside of the encapsulant, and a head portion extending from the neck portion and fitting within a recess of the plurality of recesses in the surface of the first encapsulant; and a second semiconductor package stacked on the first semiconductor package, including: a second substrate having third and fourth opposed surfaces, the second substrate having a third set of contact pads on the third surface, the head portion of the electrical connector affixed to a contact pad of the third set of contact pads, a second set of one or more semiconductor die mounted on the fourth surface of the second substrate, and a second encapsulant for encapsulating at least the second semiconductor die.