Patent ID: 7803654

Claim:
A method of fabricating an integrated circuit memory cell, comprising: forming a first electrode; forming an amorphous variable resistivity material on the first electrode; after forming the amorphous variable resistivity material, forming a crystalline variable resistivity material on the amorphous variable resistivity material; and forming a second electrode on the crystalline variable resistivity material, wherein: forming an amorphous variable resistivity material on the first electrode comprises: in a first process of a first deposition step, feeding hydrogen (H2) and an inert carrier gas carrying a germanium (Ge) precursor and a tellurium (Te) precursor onto the first electrode for a first time, wherein a ratio of H2 to inert carrier gas is a first value, and in a second process of the first deposition step, feeding hydrogen (H2) and an inert carrier gas carrying an antimony (Sb) precursor and a Te precursor onto the first electrode for a second time, wherein a ratio of H2 to inert carrier gas is a second value; and forming a crystalline variable resistivity material on the amorphous variable resistivity material comprises: in a first process of a second deposition step, feeding hydrogen (H2) and an inert carrier gas carrying a Ge precursor and a Te precursor onto the amorphous variable resistivity material for a third time that is greater than the first time, wherein a ratio of H2 to inert carrier gas is a third value that is less than the first value, and in a second process of the second deposition step, feeding hydrogen (H2) and an inert carrier gas carrying a Sb precursor and a Te precursor onto the amorphous variable resistivity material for a fourth time that is greater than the second time, wherein a ratio of H2 to inert carrier gas is a fourth value that is less than the second value.