Patent ID: 8799624

Claim:
An apparatus, comprising: a multicore computing system that includes multiple tiles each tile including a processor and a switch; a communication network among the processors that is configurable by the switch and processor of each tile; memory coupled to at least one of the multiple tiles, the memory having an address space; a hardware shim that is external to the multiple tiles the shim configured to couple an external device to the multicore computing system, the hardware shim comprising: circuitry to couple the hardware shim to one of the multiple tiles; circuitry configured to transmit or receive messages on the communication network to or from a coupled device; and circuitry including a translation lookaside buffer to store translated physical addresses to translate virtual addresses to physical addresses of the address space of the memory in response to receiving messages over the communication network that include a virtual address and that are received at the shim such that packet data is directly placed into the memory that is accessed with physical addresses of the memory.