Patent ID: 8804442

Claim:
A system comprising a controller chip and a semiconductor memory chip interconnected to the controller chip, the controller chip comprising: a set of first terminals that is connected to the semiconductor memory chip through a set of first signal lines; and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the semiconductor memory chip to cause the semiconductor memory chip to activate a strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state, the control circuit being further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the semiconductor memory chip to cause the semiconductor memory chip to return to the controller chip a data signal while activating the strobe signal at one of the first and second timings that is designated by the selected one of the sates of the edge specifying information.