Patent ID: 7305593

Claim:
A parallel turbo decoder comprising: an interleaver memory comprising n interleaver memory outputs; a routing multiplexer, comprising: n multiplexer inputs coupled to the n interleaver memory outputs; p multiplexer outputs based on a selected permutation of the n multiplexer inputs, where p and n are integer variables and n≧p; and a plurality of modules arranged in an array of interconnected rows, each module having first and second inputs, first and second outputs and a control input and arranged to supply signals at the first and second inputs to the first and second outputs in a direct or transposed order based on a value of a control bit at the control input, the array comprising a first row formed by a first group of p/2 of the modules of which the first and second inputs are each coupled to a respective one of the n multiplexer inputs and a last row formed by a second group of p/2 of the modules of which the first and second outputs are each coupled to a respective one of the p multiplexer outputs; and a memory containing a plurality of control bit tables each containing a plurality of control bits in an arrangement based on a respective permutation, the memory being responsive to the selected permutation to supply the plurality of control bits of the control bit table that corresponds to the selected permutation to respective control inputs of the modules.