Patent ID: 7977190

Claim:
A method of fabricating a floating gate memory array comprising: forming a gate oxide layer on each of a plurality of pillars in a substrate, wherein the pillars are defined by trenches on at least two sides of the pillar; forming a floating gate layer on the gate oxide layer; forming an inter-gate dielectric layer on the floating gate layer; isolating the inter-gate dielectric layer on the floating gate layer to create a plurality of isolated inter-gate dielectric regions on the floating gate layer and overlying each of the respective plurality of pillars, such that each of the inter-gate dielectric regions of the plurality of inter-gate dielectric regions is isolated from each of the other inter-gate dielectric regions of the plurality of inter-gate dielectric regions by the trenches; and forming a control gate layer on the plurality of inter-gate dielectric regions, after isolating the inter-gate dielectric layer to form the inter-gate dielectric regions.