Patent ID: 8609498

Claim:
A method, comprising: forming a plurality of cavities in a first silicon-containing crystalline semiconductor region adjacent to a first gate electrode structure of a first transistor of a semiconductor device by using a crystallographically anisotropic etch process, said first gate electrode structure comprising a first offset spacer formed on sidewalls thereof; forming a strain-inducing semiconductor alloy in said cavities by performing a selective epitaxial growth process having a self-limiting deposition behavior in at least one crystal axis; forming said strain-inducing semiconductor alloy on an upper surface of a second silicon-containing crystalline semiconductor region adjacent to a second gate electrode structure of a second transistor of said semiconductor device; and forming an excess portion of said strain-inducing semiconductor alloy above said strain-inducing material in each of said cavities by using said self-limiting deposition behavior so as to stop said selective epitaxial growth process, wherein outer surfaces of said excess portions of said strain-inducing semiconductor alloy that are positioned above an upper surface of said first silicon-containing crystalline semiconductor region are located in crystallographic planes that substantially prevent further formation of said strain-inducing semiconductor alloy.