Patent ID: 7577827

Claim:
A branch prediction unit for implementation in a processor architecture that supports instructions including multiple branch commands, the branch prediction unit comprising: a branch history memory storing information about previously-executed source instructions; a selection unit coupled to the branch history memory, the selection unit reading the information to select a predicted branch command from a plurality of branch commands included in a current instruction and outputting a position indication indicating a location of the predicted branch command in the current instruction; a branch target memory comprising: a first input coupled to the selection unit, the first input receiving the position indication from the selection unit, a second input coupled to a program counter in the processor architecture, the second input receiving a source instruction address from the program counter, a set memory that outputs a set of target instructions, and a comparison unit that receives the set of target instructions from the set memory and selects an instruction corresponding to the predicted branch command from the set of target instructions based on the source instruction address received from the program counter and the position indication received from the selection unit; and a multiplexer coupled to the branch target memory, the multiplexer outputting the selected instruction to a processor in the processor architecture.