Patent ID: 8106449

Claim:
A semiconductor device having a memory area formed of an array of a plurality of unit memory cells in a same chip, wherein: each of the unit memory cells has a write transistor and a read transistor, the write transistor is a field effect transistor including: a substrate having a main surface on which a first insulating layer is formed; a source and a drain formed on the first insulating layer; a channel formed on the first insulating layer and between the source and the drain and made of a semiconductor; a gate formed on an upper portion of the first insulating layer and between the source and the drain, the gate being electrically insulated from the channel by a gate insulating film, and controlling a potential of the channel; and a second insulating layer formed on an upper surface of the gate, wherein the entire boundary between the gate and the second insulating layer is lower than an upper surface of the source, the gate is formed without overlapping the upper surfaces of the source and drain, and the source and drain are formed without overlapping with an upper surface of the gate, the read transistor is a field effect transistor, one of the source and the drain of the write transistor that inputs and outputs a stored charge is electrically connected to a bit line, and one of the drain and the source not electrically connected to the bit line is electrically connected to a gate of the read transistor, an electrode, which is electrically separated from the gate of the read transistor, is formed near the gate of the read transistor, and only one insulating film is disposed between facing surfaces of the gate and the channel, between facing surfaces of the gate and the source, and between facing surfaces of the gate and the drain, the one insulating film being the gate insulating film.