Patent ID: 8621297

Claim:
An integrated circuit comprising: A. a substrate of semiconductor material; B. pads formed on the semiconductor material; C. functional circuits formed on the substrate and having a functional input lead; D. input buffer circuitry formed on the substrate, the input buffer circuitry having a buffer output lead connected to the functional input lead and having a buffer input lead coupled to an input pad; E. electrostatic discharge circuitry coupled to the buffer input lead; F. a serial scan path of scan cells formed on the substrate between a test data input lead and a test data output lead, both connected to a pad, some of the scan cells being switch cells; G. test leads formed on the substrate and coupled to the pads; H. a first switch cell coupling a first test lead to the buffer input lead between the electrostatic discharge circuitry and the input pad; I. a second switch cell coupling a second test lead to the buffer input lead between the electrostatic discharge circuitry and the input pad; and J. a third switch cell coupling a third test lead to the buffer output lead between the input buffer circuitry and the functional input lead.