Patent ID: 8255633

Claim:
A method for increasing performance in a parallel computing system, the method comprising: receiving a current cache miss address, a cache miss address representing an address that caused a cache miss; evaluating whether the current cache miss address is valid, a valid cache miss address referring to a cache miss address belonging to a class of cache miss addresses for which a prefetching is intended; comparing the cache miss address and a list address in response to determining that the current cache miss address is valid, the list address representing an address in a list, the list describing prior cache miss addresses; and prefetching data whose addresses appear in the list in response to determining that there is a match between the current cache miss address and a list address; said comparing including steps of: identifying a processing thread that initiates said data prefetching according to said list; said prefetching including steps of: executing a first directive in the processing thread, the executing of the first directive starting said data prefetching according to said list; executing a second directive in the processing thread, the executing of the second directive stopping said data prefetching.