Patent ID: 7010767

Claim:
A method of inserting buffers in a circuit design, comprising the steps of: preparing a physical hierarchy of the circuit design with placed macros; performing global routing on the physical hierarchy; determining a number of buffers to be inserted on each edge of nets of the global routing for boosting timing performance of the nets; calculating a position for each buffer; and inserting a buffer configured to boost timing performance at each calculated position; wherein: said step of determining a number of buffers comprises the steps of: identifying a set of at least one edge in said nets for inserting buffers; and determining an optimal number of buffers to be inserted on each edge said step of determining an optimal number of buffers comprises the step of, calculating, for each edge, the optimal number of buffers based on an optimal timing for the edge, a delay of the edge, and an impedance of the edge; and said step of calculating the optimal number of buffers comprises calculating C x i = T opt - D i - 1 - ( R eq i + 1 2 ⁢ R i ) ⁢ C i ( R eq i + R i ) ⁢ f i ; where C x i is a capacitance contribution of a branch of a merged segment on an edge as seen by a driving node of the segment; T opt is the delay of an optimal stage; D i is delay of the edge; R eq i is an equivalent resistance of the merged segment; f i is fanout of the branch; R i is a resistance of the edge; and C i is a capacitance of the edge.