Patent ID: 7068090

Claim:
An amplifier circuit, comprising: a first PMOS transistor; a first NMOS transistor having a drain connected to a drain of said first PMOS transistor; a signal input part connected to a gate of said first PMOS transistor and to a gate of said first NMOS transistor; a signal output part connected to said drain of said first PMOS transistor and to said drain of said first NMOS transistor; and at least one of first voltage shift means and second voltage shift means, said first voltage shift means for increasing a source voltage of said first NMOS transistor to reduce a DC offset, said second voltage shift means for decreasing a source voltage of said first PMOS transistor to reduce the DC offset; said first voltage shift means including: a second NMOS transistor interposed between a source of said first NMOS transistor and a ground part, and a DC offset detecting means for detecting the DC offset and for applying a voltage that is adjustable so as to reduce the DC offset to a gate of said second NMOS transistor; said DC offset detecting means including: a third PMOS transistor having characteristics that are substantially identical with those of said first PMOS transistor, a third NMOS transistor having a drain connected to a drain of said third PMOS transistor and having characteristics that are substantially identical with those of said first NMOS transistor, a biasing voltage source for supplying a direct-current bias voltage to a gate of said third PMOS transistor and to a gate of said third NMOS transistor, a fourth NMOS transistor having a drain connected to a source of said third NMOS transistor and having characteristics that are substantially identical with those of said second NMOS transistor, and an operational amplifier having a non-inverting input part connected to the drain of said third PMOS transistor and to the drain of said third NMOS transistor, an inverting input part connected to the gate of said third PMOS transistor and to the gate of said third NMOS transistor, and an output part connected to the gate of said second NMOS transistor and to a gate of said fourth NMOS transistor.