Patent ID: 8477833

Claim:
A 1/n-rate decision feedback equalizer (DFE), wherein n is a positive integer comprising: a plurality of branches, each branch including: a summer circuit configured to add a feedback signal to a received input; a latch circuit configured to receive an output of the summer circuit, the latch circuit of each branch being driven on different phases of a clock signal to provide different partial bit sequences; and a feedback circuit including: a multiplexer configured to receive as input, the different partial bit sequences from the latch circuit of each branch, the multiplexer having a clocked select input and configured to multiplex the different partial bit sequences from the latch circuit of each branch to assemble a full rate bit sequence; and a filter configured to provide cancellation of intersymbol interference (ISI) on the received input using an output of the multiplexer, an output of the filter being provided to the summer circuit of each branch.