Patent ID: 8456918

Claim:
A method of programming a flash cell unit having n memory cell transistors MC<0>through MC<n−1>, respectively controlled by n wordlines WL<0>through WL<n−1>, connected in series between a ground select transistor GST and a string selection transistor SST controlled by a string selection line SSL, memory cell MC<n−1>being closest to the SST, wherein n is a real number, the method comprising: applying a first predetermined voltage Vcc or Vcc−α to the string selection line SSL; and applying a low voltage Vcutoff (Vss) to the wordline of an unselected memory cell transistor situated between the ground select transistor GST and a second selected wordline while applying a predetermined second voltage (Vcc−α or Vcc+α) to the SSL while applying a programming voltage Vpgm to the second selected wordline, wherein the voltage increase +α or the voltage decrease −α of the predetermined second voltage Vcc is sufficient to reduce the difference between the channel potential of a first plurality of the memory cell transistors and the channel potential of a second plurality of the memory cell transistors, wherein the first plurality includes a memory cell transistor between the GST and the unselected memory cell transistor, and the second plurality includes the memory cell transistor connected to the second selected wordline.