Patent ID: 8036055

Claim:
A semiconductor storage device, comprising: a plurality of I/O terminals configured in a block, and including a representative I/O terminal and a non-representative I/O terminal; a plurality of memory cells each associated with said plurality of I/O terminals to store data; a data input portion to which data to be stored in said plurality of memory cells is input; and a data output portion which outputs data stored in said plurality of memory cells, said data input portion including a branch circuit which distributes the data input to said representative I/O terminal to all of said plurality of memory cells when the data to be stored in said plurality of memory cells is input while in test mode, and said data output portion including: a selection circuit which is connected to said representative I/O terminal, and which selects one of the data output from said plurality of memory cells and outputs the selected data from said representative I/O terminal when the data stored in said plurality of memory cells is output while in the test mode; and a dummy circuit which is provided between said non-representative I/O terminal and said memory cell associated with said non-representative I/O terminal, and reduces a delay difference of the data which said representative I/O terminal and said non-representative I/O terminal output, respectively, in a normal operation.