Patent ID: 8305836

Claim:
A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; first and second read word lines provided in each of sets each made of two adjacent ones of the rows; first, second, third, and fourth read bit lines provided in each of the columns; a first read row decoder controlling activation of said first read word line based on a set-specifying address in a first read address; a second read row decoder controlling activation of said second read word line based on a set-specifying address in a second read address; a first selector which is provided in each of the columns, and to which said first read bit line and said second read bit line are connected; a second selector which is provided in each of the columns, and to which said third read bit line and said fourth read bit line are connected; a first read column decoder providing control as to an output signal of which first selector out of the first selectors in all of the columns should be selected, based on a column-specifying address in said first read address; and a second read column decoder providing control as to an output signal of which second selector out of the second selectors in all of the columns should be selected, based on a column-specifying address in said second read address.