Patent ID: 7237070

Claim:
A method of data processing in a cache coherent data processing system, said data processing system including first, second and third processor cores each having a respective affiliated one of first, second and third cache memories, wherein said first, second and third cache memories are coupled by an interconnect fabric and said first and second cache memories are coupled by a private communication network to which said third cache memory is not coupled, said method comprising: at a first cache memory affiliated with a first processor core, receiving an exclusive memory access operation via the interconnect fabric coupling said first cache memory to second and third cache memories, wherein said exclusive memory access operation specifies a target address; in response to receipt of said exclusive memory access operation, said first cache memory detecting presence or absence of a source indication indicating that said exclusive memory access operation originated from said second cache memory to which said first cache memory is coupled by the private communication network; in response to detecting presence of said source indication, updating a coherency state field of said first cache memory that is associated with said target address to a first data-invalid state; and in response to detecting absence of said source indication, updating said coherency state field of said first cache memory to a second data-invalid state.