Patent ID: 8369148

Claim:
An integrated circuit, comprising: a memory cell structure, including: a first cell including a first storage structure and a first gate over a substrate, the first gate being over the first storage structure; a second cell including a second storage structure and a second gate over the substrate, the second gate being over the second storage structure, the first gate being separated from the second gate; a first doped region adjacent to the first cell, the first doped region being coupled to a first source; a second doped region adjacent to the second cell, the second doped region being coupled to a second source; and at least one third doped region between the first cell and the second cell, the third doped region being floating; and a circuit unit configured to apply a programming bias arrangement, including: applying a first voltage to the first doped region; applying a second voltage to the second doped region, the first voltage being higher than the second voltage; applying a third voltage to the first gate; applying a fourth voltage to the second gate; and applying a fifth voltage to the substrate, thereby programming the first cell; wherein the programming bias arrangement injects a first type of charges to the first storage structure of the first cell and is insufficient to turn on the first cell.