Patent ID: 8046647

Claim:
An integrated circuit comprising: at least one test input configured to receive test data from off chip and a test clock from off chip; a plurality of circuitry to be tested; and at least one test control circuitry between said at least one test input and said plurality of circuitry to be tested, arranged to receive test data on a data line from said at least one test input and to clock in said test data according to both a rising clock edge of said test clock and a falling clock edge of said test clock, wherein test data on said data line clocked in on said rising clock edge is directed from said at least one test control circuitry to a first one of said plurality of circuitry to be tested and is not directed to a second one of said plurality of circuitry to be tested, and wherein test data on said data line clocked in on said falling clock edge is directed from said at least one test control circuitry to the second one of said plurality of circuitry to be tested and is not directed to the first one of said plurality of circuitry to be tested.