Patent ID: 7724817

Claim:
A step-size estimator for controlling the step-size of an adaptive equalizer comprising: a delayed locked loop (DLL) for generating a punctual sample sequence based on received samples and first significant tap (FSP) location information, wherein the DLL comprises: a delay buffer for generating delayed samples based on the received samples; an interpolator for shifting the delayed samples, generating early and late time sequences, and generating the punctual sample sequence; a code tracking loop (CTL) for generating an interpolation index signal and a buffer address signal; an adder for generating an index signal by adding together a given FSP location signal and the buffer address signal, wherein the delay buffer aligns received samples for tracked FSPs within a certain resolution based on the index signal; and a common pilot channel (CPICH) signal-to-noise ratio (SNR) estimator for generating a CPICH SNR estimate based on the punctual sample sequence, wherein at least one filter tap coefficient used by the adaptive equalizer is updated based on an apparent speed of a channel.