Patent ID: 7659629

Claim:
A semiconductor integrated circuit having a multilayer wiring structure, comprising: circuit elements formed on a semiconductor substrate; a top metal wiring layer (M TOP ) including a plurality of top layer power supply wirings extending in a first direction, and a next-to-top metal wiring layer (M TOP-1 ) directly below the top metal wiring layer M TOP including a plurality of next-to-top layer power supply wirings extending in a second direction, each of the top layer and the next-to-top layer power supply wirings including a plurality of first potential wirings for supplying a first potential to the circuit elements and a plurality of second potential wirings for supplying a second potential to the circuit elements, wherein each of the plurality of top layer power supply wirings crosses each of the plurality of next-to-top layer power supply wirings with a top layer insulating film between them; and a plurality of first contacts provided in the insulating film for connecting the first potential wirings in the top and the next-to-top metal wiring layers with each other and a plurality of second contacts provided in the insulating film for connecting the second potential wirings in the top and the next-to-top metal wiring layers with each other.