Patent ID: 8631308

Claim:
An apparatus for determination of a position of a 1-bit error in a bit sequence that is coded by means of an inner code and an outer non-linear code, comprising: an error position determiner of the inner code configured to determine at least one possible error position of a bit error in the coded bit sequence based on the inner code; an error syndrome determiner of the outer code configured to determine a value of a non-linear syndrome bit of the outer code based on a non-linear function of bits in the coded bit sequence; a derivative determiner configured to determine a value of a derivative bit for at least one determined, possible error position of the bit error, based on derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence; and an overall error position determiner configured to determine an error position of the bit error based on the non-linear syndrome bit and at least one derivative bit when the error position determiner of the inner code determines more than one possible error position of the bit error, or the overall error position determiner configured to identify the bit error as a 1-bit error based on the non-linear syndrome bit and a derivative bit of a determined, possible error position, and distinguish the 1-bit error from a multi-bit error, and thus identify the determined, possible error position as the error position of the 1-bit error when the error position determiner of the inner code determines only one possible error position of the bit error in the coded bit sequence.