Patent ID: 8652896

Claim:
A method for fabricating a semiconductor memory device, said semiconductor memory device comprising: a first CMOS inverter comprising first and second MOS transistors having respective, mutually opposite channel conductivity types and connected in series at a first node on a semiconductor substrate; a second CMOS inverter comprising third and fourth MOS transistors having respective, mutually opposite channel conductivity types and connected in series at a second node on said semiconductor substrate, said second CMOS inverter forming, together with said first CMOS inverter, a flip-flop circuit; a first transfer transistor provided on said substrate between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line and driven by a selection signal on said word line; and a second transfer transistor provided on said substrate between a second bit line and said second node, said second transfer transistor having a second gate electrode connected to said word line and driven by a selection signal on said word line, said method comprising: forming a first polysilicon pattern on a device region of a first conductivity type defined on said semiconductor substrate by said device isolation region via a gate insulation film, a gate electrode of said first MOS transistor including said first polysilicon pattern; introducing a first impurity element of said second conductivity type into said device region at a first side of said first polysilicon pattern to form a source region of said second conductivity type at said first side of said first polysilicon pattern in said device; introducing a second impurity element of said second conductivity type into said device region at said first side and at a second side opposite to said first side of said first polysilicon pattern to form a drain extension region in a surface part of said device region at said second side of said first polysilicon pattern with an impurity concentration lower than an impurity concentration of said source region; forming sidewall insulation films on respective sidewall surfaces of said first polysilicon pattern; and introducing a third impurity element of said second conductivity type into said device region while using said first polysilicon pattern and said sidewall insulation films as a mask to form drain regions of said second conductivity type at respective outer parts of said sidewall insulation films of said first side and said second side of said first polysilicon pattern.