Patent ID: 8723321

Claim:
A semiconductor device having an integrated circuitry pattern, the semiconductor device comprising: a dielectric layer in the integrated circuitry pattern, the dielectric layer having an opening therein; a copper (Cu) or a Cu alloy interconnect line in the integrated circuitry pattern, in the opening, the Cu or Cu alloy line having an end surface and a width (“LW”) defined by first and second side surfaces; a capping layer on the Cu or Cu alloy line, in the integrated circuitry pattern; and a via in the integrated circuitry pattern, through the capping layer contacting the Cu or Cu alloy line, the via having the form of a solid rectangle in plan view having a width (“RW”) substantially parallel to LW and being spaced apart from the end surface, or having the form of a solid oval in plan view having a minor axis (“MA”) substantial parallel to LW, wherein the ratio RW:LW or MA:LW is less than or equal to about 0.7, wherein a first distance between a point on the perimeter of the via closest to the first side surface and a second distance between a point on the perimeter of the via closest to the second side surface are not equal, wherein a difference between the first distance and the second distance is not greater than about 10%, and wherein the via has a shape such that the ratio RW:LW or MA:LW is less than the ratio D:LW for a circular via having a diameter (“D”) and an area equal to or less than the area of the via with the RW or MA.