Patent ID: 8828815

Claim:
A method for fabricating a strained-silicon CMOS transistor, comprising: providing a semiconductor substrate having a first active region for fabricating a first transistor, a second active region for fabricating a second transistor, and an isolation structure disposed between the first active region and the second active region; forming a source / drain region for the first transistor and a source / drain region for the second transistor; forming a first etching stop layer, a first stress layer, and a second etching stop layer on the first transistor, the second transistor, and the isolation structure; forming a first patterned photoresist on the second etching stop layer of the first active region; performing a first etching process to completely remove the second etching stop layer and remove a portion of the first stress layer of the second active region; removing the first patterned photoresist after the first etching process is performed; performing a second etching process by utilizing the second etching stop layer of the first active region as a mask to remove the remaining first stress layer of the second active region after the first patterned photoresist is removed; forming a second stress layer on the second etching stop layer of the first active region and the first etching stop layer of the second transistor of the second active region after performing the second etching process; forming a third etching stop layer on the second stress layer; forming a second patterned photoresist on the third etching stop layer of the second active region; performing a third etching process to remove the third etching stop layer and a portion of the second stress layer of the first active region; removing the second patterned photoresist after performing the third etching process; and performing a fourth etching process after removing the second patterned photoresist by utilizing the third etching stop layer of the second active region as a mask to remove the remaining second stress layer of the first active region and the second stress layer between the first active region and the second active region.