Patent ID: 8338239

Claim:
A method for forming a complementary metal-oxide-semiconductor (CMOS) chip comprising a high performance device region and a high density device region, comprising: defining a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; forming a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; implanting source and drain regions of the NFETs in the high performance device region and the high density device region with n-type dopants, implanting source and drain regions of the PFETs in the high performance device region and the high density device region with p-type dopants, and diffusing the n-type dopants and the p-type dopants into the implanted source and drain regions; performing stress memorization technique (SMT) on the NFETs in the high performance device region; forming gate silicide and source/drain silicide in the NFETs and PFETs in the high performance device region, and forming gate silicide in the NFETs and PFETs in the high density device region; forming a neutral stressed liner over the NFETs and the PFETs in the high density device region; and forming a dual stressed liner over the NFETs and the PFETs in the high performance device region.