Patent ID: 8732226

Claim:
A microprocessor for a computer system including a floating point arithmetic logic, the floating point arithmetic logic responsive to a packed integer rounding instruction and comprising: a first unit to convert an input floating point number, of a plurality of packed floating point numbers of an argument of the packed integer rounding instruction, to a first integer number and to manipulate a conversion signal state; a second unit to add a value to the first integer number to produce a second integer number; a third unit to select a result integer from the first integer number and the second integer number based, at least in part, on an input rounding mode provided by an immediate field of the packed integer rounding instruction and the conversion signal state; a fourth unit to process the result integer into an output floating point number, the output floating point number being an integer rounded version of the input floating point number, the output floating point number being produced from the input floating point number in a single pass through the floating point arithmetic logic and in response to a single micro-operation decoded from the packed integer rounding instruction; and a fifth unit to provide the input floating point number as an output floating point number in response to an integer overflow condition generated by the first unit, wherein a second argument of number is to be provided to the floating point arithmetic logic in response to the instruction is to be to be used to detect the integer overflow condition.