Patent ID: 6995057

Claim:
A method for forming a folded bit line DRAM device, comprising: forming an array of memory cells formed in rows and columns, wherein forming each memory cell includes: forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer; forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars, and wherein forming the single crystalline vertical transistor includes: depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars; annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; forming a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array of memory cells, wherein forming the plurality of buried bit lines includes coupling the first contact layer of column adjacent pillars in the array of memory cells; and forming a plurality of word lines, wherein forming the plurality of word lines includes forming each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.