Patent ID: 8212346

Claim:
A semiconductor package comprising: a package substrate; and a semiconductor die coupled electrically and physically to the package substrate, wherein the semiconductor die includes a stress relieving layer incorporated therein, the stress relieving layer having a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package, wherein the semiconductor die includes a first side portion that has a first side that is physically attached to the package substrate, wherein the stress relieving layer has a first Coefficient of Thermal Expansion (CTE) determined in response to the predetermined structure, the first CTE of the stress relieving layer is different than a die portion CTE of the first side portion of the semiconductor die and is defined within a predetermined CTE range for reducing the tensile stress of the semiconductor package during heating and cooling of the semiconductor package, and wherein the predetermined location of the stress relieving layer is located proximate to a second side of the semiconductor die opposite to the first side, wherein the semiconductor die has a silicon substrate, and wherein the stress relieving layer is a layer formed within the silicon substrate.