Patent ID: 8598955

Claim:
A phase locked loop, comprising: a feedback circuit which provides a feedback signal based on an output signal, and a phase detector which generates at least one adjust signal based on a frequency of said feedback signal compared with a reference frequency; a charge pump receiving said at least one adjust signal and having an output coupled to a control node providing a control voltage; a capacitor and an adaptive resistance coupled in series between said control node and a reference node, wherein said adaptive resistance includes at least one current control input; a voltage controlled oscillator having an output providing said output signal based on a voltage level of said control voltage; a bias generator which converts said control voltage to a loop bias current, and which has at least one bias output which is based on said loop bias current and which is coupled to said at least one current control input of said adaptive resistance; and wherein said bias generator provides a bias voltage, and wherein said adaptive resistance comprises: a first transistor having a source coupled to a source voltage, having a gate receiving said bias voltage, and having a drain; a second transistor having a drain and gate coupled to said drain of said first transistor and having a source coupled to said reference node; and a third transistor having a drain coupled to said capacitor, having a gate coupled to said gate of said second transistor, and having a source coupled to said reference node.