Patent ID: 7827424

Claim:
A clock control system comprising: memory containing instructions executable by a processor that causes the processor to: receive at least vertical blank interval information associated with a vertical blank interval during display rasterization and, in response, to produce clock generator control information; produce memory clock control information in response to at least the received vertical blank interval information to dynamically change a frequency of a memory clock signal during the vertical blank interval; a graphics processor, operatively coupled to the processor, including: a clock signal generator operative to receive the clock generator control information and in response to produce a clock signal; a memory clock divider, operatively coupled to the clock signal generator and operative to receive the memory clock control information and the clock signal, and in response to produce the memory clock signal; a graphics engine clock divider, operatively coupled to the clock signal generator, and operative to receive graphics engine clock control information and in response to produce a graphics engine clock signal; a memory clock switch, operatively coupled to the graphics engine clock, the memory clock and to an additional memory, and operative to receive the memory clock signal, the graphics engine clock signal and memory switch control information and in response to switch the memory clock signal from the memory clock divider signal to the graphics engine' clock signal; and switch the memory clock signal to the received memory clock divider signal in response to a change of the frequency of the memory clock divider signal.