Patent ID: 7287143

Claim:
A semiconductor device comprising: a data strobe buffering means for generating N number of align control signals based on a data strobe signal and an external clock signal, including a strobe signal divider for receiving the data strobe signal to generate N number of the align control signals based on the data strobe signal sequence; a receiving block in response to N−1 number of the align control signals for receiving the plurality of input data and outputting intermediate N-bit data in a parallel fashion; and an outputting block in response to the remaining align control signal for receiving the intermediate N-bit data in the parallel fashion and outputting the intermediate N-bit data in synchronization with the remaining align control signal having an N/2 external clock period to generate the synchronized intermediate N-bit data as the N-bit output data, wherein the semiconductor device operates to receive a plurality of input data to output the N-bit output data at one clock, N being a positive integer, and N is at least 4, wherein the data strobe buffering means generates the N number of align control signals, each having an N/2 external clock period, the receiving block includes N−1 number of latch blocks in response to the N−1 number of the align control signals, and the data strobe buffering means includes: an instruction decoder for generating an initialization pulse for initializing the strobe signal divider in response to the data strobe signal.