Patent ID: 8921185

Claim:
A method for fabricating an integrated circuit, comprising the steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the second stacked structure, wherein the first stacked structure is still covered by the interlayer dielectric layer after planarizing, wherein the method for forming the first stacked structure and the second stacked structure includes the steps of: forming a second dielectric material layer on the substrate; forming a first poly-silicon layer on the second dielectric material layer; removing a portion of the second dielectric material layer and a portion of the first poly-silicon layer to expose the first active region; forming a first dielectric material layer on the first active region; forming a second poly-silicon layer conformally on the substrate, wherein the second poly-silicon layer has a first thickness and constructs a gate material layer with the first poly-silicon, a first portion of the gate material layer is the portion of the second poly-silicon layer located on the first active region and a second portion of the gate material layer is constructed from the portion of the first poly-silicon layer remained on the substrate and the portion of the second poly-silicon layer located on the second active region, the second portion of the gate material layer has a second thickness greater than the first thickness.