Patent ID: 7590024

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of unit bank cell arrays, the unit bank cell arrays having a plurality of unit block cell arrays, the unit block cell arrays including a plurality of cell array layers, the cell array layers having a plurality of unit cells arranged in row and column directions, wherein the unit block cell arrays are arranged in directions X, Y, and Z based on a deposition direction of their respective cell array layers, and the unit cells are configured to perform read/write operations individually, and wherein the unit cells comprise: a bottom word line; an insulating layer formed over the bottom word line; a floating channel layer formed over the insulating layer and kept at a floating state; a ferroelectric layer formed over the floating channel layer where data is stored; and a word line formed over the ferroelectric layer in parallel with the bottom word line, wherein a variable resistance is induced to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so that data is read/written.