Patent ID: 8044451

Claim:
A semiconductor device comprising: a semiconductor substrate including a cell array area and a peripheral circuit area; a cell transistor on the cell array area of the semiconductor substrate, the cell transistor including a first notch gate structure, a first channel region formed on the semiconductor substrate under the first notch gate structure, a first source region and a first drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the first notch gate structure, and two first memory layers locally formed on areas adjacent to the first source region and the first drain region between the first channel region and the first notch gate structure, wherein the first notch gate structure has a first conductive layer formed on the first gate insulation film and second conductive layers in the shape of spacers formed on portions of a first insulation film that contact both sidewalls of the first conductive layer; and a plurality of peripheral circuit transistors on the peripheral circuit area of the semiconductor substrate, at least one peripheral circuit transistor of the plurality of peripheral circuit transistors including a second notch gate structure, a second channel region formed on the semiconductor substrate under the second notch gate structure, a second source region and a second drain region formed on both sides of the second channel region, and a second gate insulation film formed between the second channel region and the second notch gate structure, wherein the second notch gate structure has a third conductive layer formed on the second gate insulation film and fourth conductive layers in the shape of spacers formed on sidewalls of the third conductive layer.