Patent ID: 8319313

Claim:
An integrated circuit, comprising: a first input/output (I/O) pad having a first single ended I/O signal line coupled thereto; a second input/output (I/O) pad having a second single ended I/O signal line coupled thereto; a first capacitor having (i) a first terminal coupled to said first I/O pad and/or said first single ended I/O signal line, (ii) a second terminal coupled to said second I/O pad and/or said second single ended I/O signal line, and (iii) a capacitance sufficient to reduce effects of cross talk between said first and second single ended I/O signal lines; and an I/O block including the first I/O pad, an input buffer configured to receive input signals transmitted to the first I/O pad, and an output buffer configured to place the output buffer in a high-impedance state when the I/O block receives one of the input signals.