Patent ID: 7937560

Claim:
A design structure as a set of instructions stored in a machine readable storage medium used in a design process, the design structure as a set of instructions representing a circuit to implement the circuit functions, the circuit being positioned between a first stage and a second stage of a multi-stage processor pipeline architecture for retaining a logic state of the multi-stage processor pipeline architecture, the circuit comprising: a comparing device including a storage node and a reference node, the storage node being coupled to an output of the first stage and the reference node being coupled to a reference logic value that is the same as the output of the first stage and wherein the storage node is further coupled to a second different logic value other than the output of the first stage; wherein during a first clock phase, the storage node is connected to the output of the first stage and during a second clock phase, the storage node is connected to the second different logic value; and wherein during both the first and the second clock phases, the reference node is coupled to the reference logic value to retain a logic state of the first clock phase of the multi-stage processor pipeline architecture; a storage capacitor being coupled between the storage node and a ground; and a logic state storing and dividing device including a reference capacitor, the logic state storing and dividing device coupled between the reference node and the reference logic in a manner to generate a logic at the reference node that is a fraction of the reference logic.