Patent ID: 8344505

Claim:
A wafer level chip package comprising: a die having an inactive side and an active side with an integrated circuit (IC) formed thereon, said die comprising a plurality of die pads in electrical communication with said integrated circuit; a stiffener attached to said inactive side; a compliant layer formed on said active side, said compliant layer comprising a two dimensional arrangement of UBM pads, said UBM pads in electrical communication with said die pads, and, comprising at least a first plurality of UBM pads of a first size placed near a center of said active side, spaced apart at a first pitch, and a second plurality of UBM pads of a second size smaller than said first size and spaced apart at a second pitch, placed near a periphery of said active side; a conductive rerouting layer in said compliant layer interconnecting each of a plurality of die pads on said active side, to a corresponding one of said UBM pads; and a plurality solder bumps, each formed on a corresponding one of said UBM pads, for attaching said wafer level semiconductor package.