Patent ID: 8324882

Claim:
A method, comprising: receiving a reference clock signal at a first phase lock loop; providing a first pulse via a first signal based on the reference clock signal and an output clock signal of the phase lock loop, a first pulse-width of the first pulse indicative of a first phase difference between the reference clock signal and the output clock signal; determining a first digital value based on the first pulse-width, wherein determining the first digital value comprises: delaying the first signal by a first delay to determine a first delayed signal; delaying the first signal by a second delay to determine a second delayed signal; storing a first asserted bit of a second digital value in response to determining the first signal and the first delayed signal are asserted at the same time; and determining the first digital value based on the second digital value, and based on a comparison of the second delayed signal with the first signal; and storing the first digital value.