Patent ID: 7235437

Claim:
A method for forming a multi-planar layout thin-film transistor (TFT) inverter circuit, the method comprising: forming a P-channel top drain vertical (TDV)-TFT with a gate having a length, and a width greater than the length, a first source/drain (S/D) region in a first horizontal plane, and a second S/D) region in a second horizontal plane, different than the first horizontal plane, as viewed in a vertical cross-section; forming an N-channel TDV-TFT, adjacent the P-channel TFT, with a gate having a length, and a width greater than the length, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third plane wherein forming P and N-channel TDV-TFTs includes: forming a P-channel rate connected to a gate contact, having sidewalls and a ton surface, overlying a substrate insulation layer; forming an N-channel gate connected to the gate contact, having sidewalls and a top surface, overlying the substrate insulation layer; forming a cap oxide layer overlying the P and N-channel gate top surfaces; forming a gate oxide layer overlying the P and N-channel gate sidewalls; forming the first S/D region overlying the P-channel cap oxide layer; forming the second S/D region overlying the substrate insulation layer, adjacent a P-channel gate first sidewall; forming a first channel region overlying the P-channel gate first sidewall, interposed between the first and second S/D regions; forming the third S/D region overlying the N-channel cap oxide layer; forming the fourth S/D region overlying the substrate insulation layer, adjacent an N-channel gate first sidewall, and connected to the second S/D region; forming a second channel region overlying the N-channel gate first sidewall, interposed between the third and fourth S/D regions; and, wherein the N-channel and P-channel and P-channel TDV-TFTs share the second and fourth S/D region.