Patent ID: 8492819

Claim:
A device comprising: a silicon-on-insulator (SOI) substrate comprising a silicon layer formed on a buried oxide (BOX) layer, which is formed on a substrate layer; a buried silicon strap including a first lateral surface and an opposite second lateral surface that extend through said silicon layer into said BOX layer, and a bottom surface disposed within said BOX layer; a recessed trench capacitor including a top surface disposed within said BOX layer and a lateral surface contacting said first lateral surface of said buried silicon strap; a conductive top plate formed on said top surface of said recessed trench capacitor, said conductive top plate including a top surface disposed within said BOX layer, and a lateral surface contacting said first lateral surface of said buried silicon strap; a dielectric cap formed on a top surface of said conductive top plate, said dielectric cap including a top surface that is co-planar with a top surface of said silicon layer; a first FET formed from said silicon layer, a first source/drain (S/D) region of said first FET contacting said opposite second lateral surface of said buried silicon strap; and a passing wordline disposed on a portion of said dielectric cap opposite to and separate from said buried silicon strap and being connected to a gate of a second FET in an adjacent row of an FET eDRAM cell array.