Patent ID: 8803228

Claim:
An array of memory cells, comprising: first and second successively adjacent rows of memory cells on a first row of pillars, each pillar of the first row of pillars having a memory cell of the first row of memory cells and a memory cell of the second row of memory cells on opposite sides thereof; third and fourth successively adjacent rows of memory cells on a second row of pillars, the second row of pillars being successively adjacent the first row of pillars, each pillar of the second row of pillars having a memory cell of the third row of memory cells and a memory cell of the fourth row of memory cells on opposite sides thereof, wherein the second and third rows of memory cells are successively adjacent to each other; a control gate, wherein all of the memory cells of the second row of memory cells are coupled to one side of the control gate and all of the memory cells of the third row of memory cells are coupled to an opposite side of the control gate; and alternating first and second bit lines, wherein each of the memory cells of the second row of memory cells is coupled to a respective one of the first bit lines and each of the memory cells of the third row of memory cells is coupled to a respective one of the second bit lines, and wherein at least one of the second bit lines is between a pair of the first bit lines and is successively adjacent to the first bit lines of the pair of first bit lines.