Patent ID: 7639736

Claim:
A receiver adapted to receive an input signal expressed as a sequence of data symbols, the receiver comprising: a. an input port that receives the input signal; b. an equalizer that is coupled to the input port and adjusts a magnitude of at least some of the data symbols of the input signal to produce an equalized signal; c. a sampler that is coupled to the equalizer and samples the equalized signal to produce a first sampled data signal; d. an amplitude detector that is coupled to the equalizer and samples the equalized signal with respect to a threshold voltage selected from a range of threshold voltages to produce a second sampled data signal, wherein the second sampled data signal and the selected threshold voltage are indicative of an amplitude of the equalized signal; e. control logic that is coupled to the amplitude detector, the control logic to generate an equalization signal in response to the second sampled data signal and to convey the equalization signal to the equalizer, and f. a clock node that receives a clock signal, wherein the amplitude detector samples the equalized signal under the timing control of the clock signal.