Patent ID: 8479071

Claim:
An information processing apparatus comprising: a system controller configured to divide data into a plurality of divided-data; a plurality of storage units configured to store the plurality of divided-data, respectively; and a plurality of storage controllers configured to write the divided-data into corresponding storage units or reading out the divided-data from the corresponding storage units, each storage controller including: a history storage unit configured to store histories of an operation of the corresponding storage controller, memory addresses being created in correspondence with the histories; an error detector configured to detect an error in the divided-data; and a history controller configured to control an update of the histories in the corresponding history storage units, and a scrub controller configured to control an operation of correcting and rewriting the divided-data after reading from a memory address among the memory addresses that is same as a memory address having an error, when one of the plurality of storage controllers detects a memory error, and wherein history controllers of the plurality of storage controllers are synchronously controlled based on a signal to stop the update of the histories in the plurality of storage units when the error detector of at least one of the storage controller detects the error, and the histories prior and subsequent to the detection of the error in the plurality of storage units are compared to analyze the error.