Patent ID: 8374305

Claim:
A clock recovery circuit for recovering clock signal based on inputted serial signal, comprising: a plurality of samplers configured to sample a serial input signal in synchronization with a plurality of first clock signals having different phases respectively and to output a plurality of sampling data pieces; a phase comparison circuit configured to output a serial phase information signal on the basis of the sampling data pieces, the serial phase information signal representing a phase relationship between a clock of the serial input signal and the different phases of the first clock signals; a serial-parallel conversion circuit configured to perform a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a frequency lower than that of the first clock signals, and to output a parallel phase information signal; a digital filtering circuit configured to calculate a phase deviation signal and a phase advance-delay signal on the basis of the parallel phase information signal, in synchronization with the second clock signal; a phase control amount processing circuit configured to generate a phase control signal on the basis of the phase deviation signal and the phase advance-delay signal and to output the phase control signal, the phase control signal being in synchronization with third clock signals having a frequency higher than that of the second clock signal; and a phase interpolation circuit configured to adjust the phases of the third clock signals on the basis of the phase control signal, and to output the first clock signals as recovery clock signals.