Patent ID: 7620769

Claim:
A flash-memory system comprising: a flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in the block; a volatile lookup table having storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the flash memory; a volatile usage table having valid bits for pages in the flash memory, wherein a valid bit for a page in the flash memory indicates a valid state when the page contains valid data, a stale state when the page contains data that has been replaced by newer data stored in a different page in the flash memory, and an erased state when the page has been erased and not yet written with data from the host; a sliding window indicating blocks in the flash memory, wherein the sliding window indicates a first block and a last block within the sliding window; a flash memory controller that relocates valid pages of data from the first block in the sliding window to the last block in the sliding window to allow the first block to be erased and recycled for later use; wherein the valid pages in the first block have valid bits in the valid state in the volatile usage table; whereby valid pages in the first block are relocated to allow erasing and recycling of the first block.