Patent ID: 8495314

Claim:
A system, comprising: a processor; a memory communicatively coupled to the processor, the memory having stored therein computer-executable components, comprising: a source component configured to generate an event to a listener component associated to the event by a weak reference; a first class component configured to set a first indication identifying whether the listener component is still associated with the event, wherein the first class component is associated with the source component; a second class component associated with the source component, wherein the second class component is configured to: in response to the first indication identifying that the listener component is still associated with the event, set a second indication to identify that the second class component is in a state for memory management; and in response to the first indication identifying that the listener component is not still associated with the event, set the second indication to identify that the second class component is not in a state for the memory management; and a finalizer component configured to: in response to the second indication identifying that the second class component is in a state for the memory management, perform the memory management of the first class component and the second class component; and in response to the second indication identifying that the second class component is not in a state for the memory management, not perform the memory management of the first class component and the second class component.