Patent ID: 7465995

Claim:
A semiconductor device comprising: a first well formed on a substrate; an electrostatic discharge (ESD) protection device formed on the first well; a resistor well adjacent to the first well, the resistor well having a different polarity type as opposed to that of the first well; a resistor having a gate structure formed on the resistor well separating a first doped region coupled to the ESD protection device and a second doped region coupled to a supply voltage for passing an ESD current from the second doped region to the first doped region to turn on the ESD protection device for dissipating the ESD current during an ESD event; and a buried well formed beneath the second doped region and adjacent to the resistor well, wherein the resistor well has an impurity density lower than that of the first and second doped regions for increasing resistance therebetween, wherein the ESD protection device is a MOS transistor having a gate and a source connected together to ground.