Patent ID: 8736319

Claim:
An electronic circuit for generating a reset signal, the electronic circuit comprising: a flip-flop circuit powered by a supply voltage, wherein the flip-flop circuit generates the reset signal in response to a voltage level of the supply voltage being equal to or greater than a first predetermined supply voltage level; a clock comparator circuit, wherein the clock comparator circuit outputs a clock signal; and an enable comparator circuit directly connected to the clock comparator circuit and the flip-flop circuit, wherein the enable comparator circuit outputs an enable signal; wherein: the flip-flop circuit is clocked by the clock signal; the clock comparator circuit is enabled by the enable signal; the flip-flop circuit is reset by the enable signal; and the enable signal is in a LO state when the supply voltage is at a voltage level that is less than a second predetermined supply voltage level, and wherein the enable signal is in a HI state when the supply voltage is at a voltage level that is greater than or equal to the second predetermined supply voltage level, and wherein the second predetermined supply voltage level is less than the first predetermined supply voltage level.