Patent ID: 7359262

Claim:
A semiconductor memory device comprising: an array of memory cells arranged in a row and column matrix; at least one relief memory area for redundancy relieving a fault memory area which contains a fault memory cell when the entire memory area determined by the array of the memory cells is divided into a plurality of memory areas and the fault memory cell exists in the certain memory area; a fault address storing means in which a fault address specifying the fault memory area is stored; and a comparator circuit for comparing an address of the memory area specified by an input address with the fault address and when the input address corresponds to the fault address, selecting the corresponding relief memory area, wherein the comparator circuit selects the corresponding relief memory area upon receiving from the outside a relief memory area select signal indicative of selection of the relief memory area even when the address of the memory area specified by the address input does not correspond to the fault address stored in the fault address storing means.