Patent ID: 7742489

Claim:
An apparatus comprising: a first protocol controller and a second protocol controller; protocol specific logic circuitry coupled to the first protocol controller and the second protocol controller, the protocol specific logic circuitry being adapted to communicate a first plurality of data packets formulated in a first data transfer format with the first protocol controller, and to communicate a second plurality of data packets formulated in a second data transfer format with the second protocol controller, wherein the protocol specific logic circuitry includes: a transmit memory adapted to temporarily store at least some of the first and second pluralities of data packets; and a bandwidth-allocation-module (BAM) processor configured to receive a first instruction message received by the protocol specific logic circuitry over an instruction data path, and to process the first instruction message by retrieving one or more data packets from the transmit memory; and bridge control circuitry coupled to the protocol specific logic circuitry, the bridge control circuitry being adapted to couple either the first protocol controller or the second protocol controller to a host processor depending on whether a received data packet is in the first data transfer format or the second data transfer format.