Patent ID: 8173497

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: preparing an SOI substrate having a cell region and a peripheral region, the SOI substrate being a stack structure comprising: a silicon substrate; a buried insulation layer; and a silicon layer; forming an epi-silicon layer in the buried insulation layer of the peripheral region to connect a peripheral portion of a channel area of the silicon layer with the silicon substrate, wherein forming the epi-silicon layer comprises: etching the silicon layer and the buried insulation layer in the peripheral region to define a groove therein exposing the silicon substrate, wherein defining the groove comprises: forming a first anti-growth film on the silicon layer exposing a portion of the silicon layer in the peripheral region; etching the exposed portion of the silicon layer to expose the buried insulation layer and define a first groove in the silicon layer; forming a second anti-growth film on sidewalls of the first groove; etching an exposed portion of the buried insulation layer to expose the silicon substrate and define a second groove in the buried insulation layer; and etching the buried insulation layer having the second groove defined therein such that the second groove has a width greater than that of the first groove; and forming a gate on the silicon layer; and forming junction areas in the silicon layer at positions corresponding to sides of the gate.