Patent ID: 8203208

Claim:
A semiconductor device comprising: at least two stacked semiconductor substrates; a plurality of bonded opposing bumps provided on and bonding opposing ones of the at least two stacked semiconductor substrates together with one another, with ones of the bonded opposing bumps to provide electrical conduction paths between the opposing ones of the at least two stacked semiconductor substrates, and where the plurality of bonded opposing bumps are oxide/contaminant cleaned, low-temperature bonded opposing bumps; and, at least one of: post-bonding deposited passivation layers on at least one of: exposed substrate surfaces of an inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; and, exposed bump surfaces of the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; a post-bonding deposited mechanical support layer on exposed substrate surfaces of an inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; and, at least one thinned substrate having at least one localized substrate deflection at irregularly-sized ones of the bonded opposing bumps.