Patent ID: 8420480

Claim:
A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising: forming a first dielectric layer on the substrate in the diode region and the NVM region; forming a first conductive layer on the first dielectric layer; forming a second dielectric layer on the first conductive layer; forming a second conductive layer over the second dielectric layer; forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell; performing an etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region; and performing an implant using the gate stack and the plurality of fingers as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.