Patent ID: 7443714

Claim:
A memory device, comprising: a memory cell including a pass transistor and a capacitor, which transistor is controlled by a word line; a memory cell array wherein a bit line is connected to a plurality of memory cell, a write transfer transistor, and a read transfer transistor, where drain of the read transfer transistor is connected to a segment read line; a segment read circuit for configuring an amplifier, wherein a read transistor is connected to a select transistor serially, and a pre-charge transistor is connected to the segment read line, where gate of the read transistor is connected to the segment read line, and drain of the select transistor is connected to a block read line; a memory segment wherein the segment read circuit is connected to multiple memory cell arrays; a memory block wherein multiple memory segments are connected to a block read circuit through the block read line; and the block read circuit wherein load devices are connected to the block read line through block select transistors, so that the load devices configure the amplifier with the segment read circuit as amplify device; and output of the amplifier is connected to output of a tri-state inverter and input of a read inverter; and the read inverter generates read output based on the output of the amplifier; a read path including multiple buffers to transfer the read output of the block read circuit of the memory block; a latch circuit storing read output of the memory block through the read path; a latch control circuit generating a locking signal to lock the latch circuit.