Patent ID: 8836136

Claim:
A microelectronic package comprising: a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element; wire bonds defining edge surfaces and having bases bonded to respective ones of the conductive elements, the bases including first portions of the edge surfaces that extend along the conductive elements with respective second portions of the edge surfaces being at an angle between 25° and 90° relative to the first portions, the wire bonds further having ends remote from the substrate and remote from the bases; and a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends wherein the conductive elements are disposed at positions in a pattern having a first minimum pitch between respective adjacent conductive elements of the plurality of conductive elements, and wherein the unencapsulated portions are disposed in positions in a pattern having a second minimum pitch between respective ends of adjacent wire bonds of the plurality of wire bonds, the second pitch being greater than the first pitch.