Patent ID: 8437196

Claim:
A sense-amplifier circuit for a memory device, comprising: a first input configured to be connected to a bitline associated with a memory cell; a second input configured to be connected to a reference stage configured to supply a reference current; a comparison stage configured to perform a comparison between a cell current of the memory cell and said reference current and supply an output signal indicating a state of said memory cell, said comparison stage including a current mirror that includes a first comparison transistor and a second comparison transistor coupled respectively to a first differential output and to a second differential output, the first comparison transistor being configured to supply a biasing current; a precharging stage configured to supply, prior to said comparison, a precharging current to said bitline so as to charge a corresponding capacitance of the bitline, said precharging stage being configured to divert said biasing current towards said bitline as said precharging current, and to allow, during said comparison, passage of part of said biasing current towards said first differential output and enable operation of said current mirror, wherein said first comparison transistor is coupled between a first reference voltage line and a precharge node configured to be coupled electrically to said bitline and said precharging stage comprises a first precharging transistor coupled between said precharge node and said first input, and having a control terminal; an operational amplifier having first and second inputs and an output, the first input being configured to receive said desired bitline voltage and the output being electrically coupled to the control terminal of the first precharging transistor; a second precharging transistor coupled between a first reference voltage line and an internal node coupled to the second input of the operational amplifier, the second precharging transistor having a control terminal coupled to the output of said operational amplifier; and a biasing-current generator coupled to said internal node and configured to generate a current substantially equal to said reference current.