Patent ID: 8111825

Claim:
A processor-implemented method of operating on a 64-bit plaintext input using a key to produce a 64-bit ciphertext output, the method comprising the steps of: at the processor, sequentially iterating a round function a number of times using the key to generate the 64-bit ciphertext output, the round function comprising: obtaining a first 32-bit round function input data block and a second 32-bit round function input data block; executing an FL sub-function using the first 32-bit round function input data block so as to generate a first interim output data block; executing an intermediate sub-function using the first interim output data block using the second 32-bit round function input data block so as to generate a second interim output data block, the intermediate sub-function being functionally equivalent to execution of two consecutive 16-bit FO sub-functions, the intermediate sub-function comprising a plurality of exclusive-OR operations using pairs of half-words of data; executing the FL sub-function using the second interim output data block so as to generate a third 32-bit interim output data block; performing an exclusive-OR operation on the first 32-bit round function input data block and the third 32-bit interim output data block so as to generate a first 32-bit round function output data block; using a first intermediate result and a second intermediate result generated by the intermediate sub-function so as to generate a second 32-bit round function output data block; and providing a 64-bit ciphertext output based on the second 32-bit round function output data block, wherein the number of times of execution of the round function is four, and wherein execution of the FL sub-function is a 32-bit operation.