Patent ID: 7338879

Claim:
A method of fabricating a semiconductor device, comprising: forming a lower insulating layer on a semiconductor substrate, forming a patterned lower plate and a lower interconnection line on the lower insulating layer, wherein forming the patterned lower plate comprises forming a first barrier metal layer on the lower insulating layer; forming a lower dielectric layer on the first barrier metal layer; forming a patterned intermediate plate on the lower dielectric layer, wherein the patterned intermediate plate comprises a first intermediate plate, a second intermediate plate, and a third intermediate plate; forming a first upper dielectric layer on the lower dielectric layer; forming an inter-insulating layer on the first upper dielectric layer; forming a second upper dielectric layer on the inter-insulating layer and the patterned intermediate plate; sequentially forming an etch stop layer and an upper insulating layer on the second upper dielectric layer; patterning the upper insulating layer to form a plurality of trenches; forming a first via hole to expose the patterned lower plate, a second via hole to expose the patterned intermediate plate, and a third via hole to expose the lower interconnection line; and filling the plurality of trenches and via holes with a conductive material, thereby forming a patterned upper plate electrically connected to the patterned lower plate, a patterned first upper interconnection line electrically connected to the patterned intermediate plate, and a patterned second interconnection line electrically connected to the lower interconnection line.