Patent ID: 7251155

Claim:
A semiconductor device having a dynamic memory array including a pair of complementary digit lines through which a plurality of memory cells activated by a plurality of word lines selected in accordance with row addresses for the plurality of memory cells may be accessed, the semiconductor device comprising: an enabling device for responding to a test mode enable signal to temporarily enable charging of the dynamic memory array; and energizing circuitry coupled to the enabling device for energizing more than one of the plurality of word lines in the dynamic memory array in accordance with each row address for a memory cell of the plurality of memory cells in response to the enabling device enabling use of the dynamic memory array so two memory cells of the plurality of memory cells are accessible through the pair of complementary digit lines may be accessed for each row address so that at least two memory cells in a group of memory cells in the memory array to each store a charge and to each share its stored charge with one of the two conductors for detecting a voltage using one of the two conductors.