Patent ID: 7842574

Claim:
A process for manufacturing a semiconductor power device, comprising the steps of: forming a semiconductor body of a first conductivity type and having a top surface; forming, in said semiconductor body, a trench having side walls and a bottom; coating said side walls and said bottom of said trench with a first dielectric material layer; filling said trench with a second dielectric material layer and an auxiliary dielectric material layer; etching said first, second, and auxiliary dielectric material layers via an etching process wherein, at the end of said etching step, said trench houses, at the bottom, portions of said first, second, and auxiliary dielectric material layers, said portions of the first and second dielectric material layers having a depth that is approximately equal and the auxiliary layer has a forked top profile; forming a gate-oxide layer on said walls of said trench; forming a gate region of conductive material within said trench and surrounded by said gate-oxide layer; and forming, within said semiconductor body, a body region having a second conductivity type and a source region having said first conductivity type, said first, second, and auxiliary dielectric material layers comprising materials having similar responses to said etching process, and said etching step comprising simultaneously etching said first dielectric material layer, said second dielectric material layer, and said auxiliary dielectric material layer so as to remove a portion of each of said first, second, and auxiliary dielectric material layers in a partial, simultaneous and controlled way within said trench.