Patent ID: 7872601

Claim:
An analog-to-digital converter providing a 4-stage digital signal output according to an analog signal input and comprising: an input terminal receiving the analog signal input; and a 2-level and 4-stage circuit having a clock and a counter clock, simultaneously using the clock and the counter clock to control an operation of the analog-to-digital converter and sequentially converting the analog signal input into the 4-stage digital signal output under the control of the clock and the counter clock, wherein the 4-stage digital signal output is a 12-bit digital signal output and the 2-level and 4-stage circuit further comprises: a first level circuit receiving a first stage analog signal input to provide a first and a second stage digital signal outputs and comprising: a first stage sample-and-hold circuit receiving the first stage analog signal input to provide a first stage sample-and-hold output signal; a first 3-bit flash analog-to-digital converter to provide the first stage and the second stage digital signal outputs according to the first stage and a second stage sample-and-hold output signals; a first 3-bit multiple digital-to-analog converter to provide a second stage analog signal input according to the first stage sample-and-hold output signal and the first stage digital signal output; a second stage sample-and-hold circuit to receiving the second stage analog signal input to provide the second stage sample-and-hold output signal; and a second 3-bit multiple digital-to-analog converter providing a third stage analog signal input according to the second stage sample-and-hold output signal and the second stage digital signal output; and a second level circuit providing a third stage and a fourth stage digital signal outputs according to the third stage analog signal input and comprising: a third stage sample-and-hold circuit receiving the third stage analog signal input to provide a third stage sample-and-hold output signal; a second 3-bit flash analog-to-digital converter providing the third and the fourth stage digital signal outputs according to the third stage and a fourth stage sample and hold output signals; a third 3-bit multiple digital-to-analog converter providing a fourth stage analog signal input according to the third stage sample-and-hold output signal and the third stage digital signal output; and a fourth stage sample-and-hold circuit receiving the fourth stage analog signal input to provide the fourth stage sample-and-hold output signal.