Patent ID: 8637926

Claim:
A method for making an insulator termination semiconductor device, comprising: a) applying a trench mask to a semiconductor substrate; b) etching the semiconductor substrate through the trench mask to form trenches TR1, TR2 and a plurality of trenches TR3 with three widths W1, W2 and W3, respectively, wherein the plurality of trenches TR3 are the narrowest trenches, wherein the trench TR1 surrounds the trenches TR3, wherein a portion of the width of one of the trenches TR3 overlaps the width of the trench TR1; c) forming a gate dielectric in the trenches TR1, TR2 and TR3; d) depositing a conductive material into the trenches TR1, TR2 and TR3, wherein a thickness of the conductive material is selected to fill up the trenches TR2 and TR3 but not the trench TR1; e) isotropically etching back the conductive material to form gate electrodes in the trenches TR3 and the gate runner in the trench TR2, wherein the conductive material is completely removed from the portion of the trench TR1 that is not overlapped by the portion of one of the trenches TR3; f) filling the trench TR1 with an insulator material to form an insulator isolation trench that surrounds the gate electrodes; g) forming a body layer in a top portion of the entire substrate; f) forming a source layer in a top portion of the entire body layer; h) applying an insulator layer on top of the semiconductor substrate; i) applying a contact mask on top of the insulator layer; j) forming contact openings to the source layer and to the gate runner through the insulator layer; and k) forming source and gate metal regions on the insulator layer in electrical contact with the source and gate runner contacts respectively.