Patent ID: 7804379

Claim:
An apparatus for providing dead time compensation to a pulse width modulation (PWM) signal and generating complementary PWM signals therefrom, said apparatus comprising: a first delay circuit for delaying a PWM signal and having an output of a delayed PWM signal; a first edge detector circuit for generating a start signal for each logic level transition of the PWM signal; a first timer coupled to the first edge detector circuit, wherein the first timer generate a compensation time period each time the PWM signal makes a logic level transition, the first timer has a first output of a compensation time period signal and a second output of a complementary compensation time period signal; an OR gate having a first input coupled to the delayed PWM signal, a second input coupled to the first output of the compensation time period signal and an output of a stretched PWM signal; an AND gate having a first input coupled to the delayed PWM signal, a second input coupled to the second output of the complementary compensation time period signal and an output of a shrunk PWM signal; a multiplexer having a first input coupled to the stretched PWM signal and a second input coupled to the shrunk PWM signal, wherein an output of the multiplexer is coupled to the first input when a current of an inductive load is flowing in a first direction and to the second input the current of the inductive load is flowing in a second direction, whereby the output of the multiplexer generates a compensated PWM signal; a second delay circuit for delaying the compensated PWM signal and having an output of a delayed compensated PWM signal; a second edge detector circuit for generating a start signal for each logic level transition of the delayed compensated PWM signal; a second timer coupled to the second edge detector circuit, wherein the second timer generate a dead-time time period each time the delayed compensated PWM signal makes a logic level transition, the second timer has an output of a dead time compensated PWM signal; an AND gate having a first input coupled to the compensated PWM signal, a second input coupled to the dead time compensated PWM signal and an output of a first complementary dead time compensated PWM signal (PWMH); and an AND gate having a first input coupled to the delayed compensated PWM signal, a second input coupled to the dead time compensated PWM signal and an output of a second complementary dead time compensated PWM signal (PWML).