Patent ID: 8127260

Claim:
A method for estimating timing delays in an integrated circuit design to optimize a circuit design during synthesis, the method comprising: with a computer, generating a physical wire-load model to model parasitic capacitance per unit length of a net and parasitic resistance per unit length of a net, the physical wire-load model responsive to a physical library; converting circuit information for each net into a plurality of equivalent net lengths; estimating a net length for each of the plurality of nets in the netlist of the integrated circuit design between each driver and one or more receivers; and summing respectively the plurality of equivalent net lengths and the estimated net length for each net together to generate a total net length estimate for each net; and calculating a timing delay for each of the plurality of nets in the netlist in response to the physical wire load model modeling parasitic capacitance per unit length and parasitic resistance per unit length, in response to the converting of circuit information into the plurality of equivalent net lengths, and in response to the total net length estimate.