Patent ID: 8649223

Claim:
A semiconductor storage device comprising: electrically rewritable memory cells; word lines each electrically connected to gates of the memory cells; bit lines each electrically connected to one end of a corresponding one of the memory cells; voltage controllers each comprising a switch circuit, the voltage controller being electrically connected to the bit line; sense amplifiers each electrically connected to the corresponding voltage controller; first transistors each electrically connected between the corresponding bit line and the corresponding sense amplifier; data latch sections each electrically connected to the corresponding sense amplifier to hold first data before reading operation on the corresponding memory cell and to hold second data if a current equal to or a larger than a first value flows via the corresponding bit line; pull down circuits each configured to reduce a potential of the corresponding bit line to a reset potential if the second data is held in the corresponding data latch section; and charging control circuits each configured to apply potentials to gates of the corresponding first transistor in reading operation on the corresponding memory cell, wherein the switch circuit is turned on or off depending on the data held in another data latch section electrically connected to another bit line located adjacently in a direction of the word lines, to control a connection between the bit line and the sense amplifier via the voltage controller.