Patent ID: 8183888

Claim:
A unit with three inputs for input signals a, b, c and with an output, comprising: four 3-input logic NAND gates, wherein the three inputs for input signals a, b, c are connected to the inputs of the first NAND gate, wherein the inputs of the second NAND gate are configured to receive inverted input signal a, inverted input signal b, and input signal c, wherein the inputs of the third NAND gate are configured to receive input signal a, inverted input signal b, and inverted input signal c, wherein the inputs of the fourth NAND gate are configured to receive inverted input signal a, input signal b, and inverted input signal c, and a 4-input logic NAND gate, wherein the outputs of the four NAND gates are connected to the inputs of the 4-input logic NAND gate to provide an output of the unit.