Patent ID: 7050350

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, the memory cell array including a field memory for storing data, a line memory for temporarily storing data, and a plurality of bit lines connected to the field memory and the line memory so that the field memory and the line memory share the bit lines; a first decoder coupled to the field memory for selecting one of the memory cells in the field memory; a second decoder coupled to the line memory for selecting one of the memory cells in the line memory; a sense amplifier circuit coupled to the memory cell array through the bit lines, wherein the sense amplifier amplifies data that appears on the bit lines from the field memory so that the line memory stores the amplified data; a transfer gate circuit coupled to the sense amplifier circuit; a write register coupled to the transfer gate circuit for temporarily storing data to be written in the memory cell array; and a first read register coupled to the transfer gate circuit for temporarily storing data read from the memory cell array.