Patent ID: 7161864

Claim:
A bit refresh circuit for refreshing register bit values comprising: a first latch circuit receiving an input signal, latching the input signal in response to a set signal, and outputting a first latch signal; a second latch circuit receiving the input signal, latching the inverted input signal in response to the set signal, and outputting a second latch signal; a determination circuit generating a refresh determination signal by using the first and second latch signals; a flip-flop receiving the refresh determination signal, latching the refresh determination signal in response to a refresh clock signal, and outputting the refresh determination signal as a determination result signal; an OR logic circuit performing an OR operation on a refresh verification signal and the determination result signal and outputting an OR operation result signal; and a NAND logic circuit performing a NAND operation on an initial signal and the OR operation result signal and outputting the NAND operation result signal as the set signal.