Patent ID: 7087999

Claim:
A semiconductor protection element comprising: a semiconductor substrate having a first region of a first impurity concentration and a pair of second regions having a second impurity concentration being higher than that of said first region; and silicide layers each being formed in a manner so as to be in contact with a surface of each of said second regions; wherein said first region has a first surface region not covered with said silicide layers and said second regions have second surface regions not covered with said silicide layers and said first surface region is sandwiched by two said second surface regions; wherein each of said silicide layers is formed in a manner that each of said second surface regions is in contact with said first surface region in a continued manner and that each of said second surface regions is exposed; and wherein each of said silicide layers makes up a low resistance region having a relatively low resistance value, each of said second surface regions makes up an intermediate resistance region having an intermediate resistance value, and said first surface region makes up a high resistance region having a relatively high resistance value.