Patent ID: 8375064

Claim:
An apparatus for reducing processing bandwidth for read back verification of stored data, the apparatus comprising: a file CRC module comprising executable code stored on a semiconductor device executed by a processor and configured to calculate a first file CRC for a data file; a segmentation module comprising executable code stored on the semiconductor device executed by the processor and configured to segment the data file into a plurality of data blocks, each data block beginning after a delimiter in the data file; a block CRC module comprising executable code stored on the semiconductor device executed by a processor and configured to calculate a data block CRC for each data block and append each data block CRC to the corresponding data block; an aggregated CRC module comprising executable code stored on the semiconductor device executed by a processor and configured to calculate a second file CRC as a sum of the data block CRCs and verify a copy of the data file in response to the second file CRC being equivalent to the first file CRC.