Patent ID: 8243273

Claim:
A semiconductor wafer having one or more dummy field regions configured to enable overlay measurements, comprising: a substrate including a plurality of die patterning regions; a set of semiconductor circuitry structures formed on the substrate, one or more of the semiconductor circuitry structures forming a plurality of actively patterned regions; and one or more dummy field regions patterned with periodic overlay features encoded with overlay alignment information, the one or more dummy field regions being formed on the substrate, a first portion of the one or more dummy fields formed on a first process layer, at least a second portion of the one or more dummy fields formed on at least a second process layer, the one or more dummy field regions formed in one or more non-active regions of each of the die patterning regions of the substrate, each of the die patterning regions further including one or more of the actively patterned regions, the one or more dummy field regions formed within one or more interstitial spaces between two or more of the actively patterned regions of each of the die patterning regions, the plurality of actively patterned regions formed over the one or more dummy field regions.