Patent ID: 7324547

Claim:
A network processing apparatus, said apparatus comprising: a host central processing unit (CPU); a system memory; a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets, and to provide an asynchronous boundary interface between a first clock domain of said MAC and a second clock domain of said media access controller interface (MI) subunit; a host media access controller (HM) for communicating with said media access controller interface (MI) subunit and said host CPU to address packet processing events, wherein said host media access controller (HM) accesses a plurality of push buffers that are stored in system memory to transfer commands or data between said HM and said host CPU; a sequence processor (SP) that is coupled to the MI and configured to provide automatic decapsulations, decryption, authentication, checksums, and decompression for input packets and compression, checksums, authentication, encryption and encapsulations for output packets; and an address translation module that is coupled to the SP and configured to perform routing and stateful firewall functions.