Patent ID: 8236690

Claim:
A method for fabricating a semiconductor package substrate, comprising: preparing a copper clad laminate, in which the insulating layer is sandwiched between two copper foils; depositing a second etching resist over a first side of the copper clad laminate and half etching the copper foil on a second side of the copper clad laminate; removing the second etching resist deposited on the first side of the copper clad laminate; depositing on the second side of the copper clad laminate a first plating resist which is open at a portion corresponding to the dummy region of the copper clad laminate; and plating the second side of the copper clad laminate and removing the first plating resist; depositing a first etching resist on both sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad in the copper foils of the copper clad laminate using the first etching resist, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.