Patent ID: RE40552

Claim:
A dynamic random access memory (DRAM) comprising: (a) a plurality of bit storage capacitors, (b) a folded bit line comprised of a complementary bit line pair for receiving charge stored on one of said capacitors, having bit line capacitance, (c) a sense amplifier having a pair of sense nodes for sensing a voltage differential across said sense nodes, (d) high resistance controllable current leakage imperfect isolating means connecting said bit line to said sense nodes for receiving an enabling voltage for causing current leakage therethrough between said sense nodes and the bit line while maintaining high resistance, (e) means for applying said enabling voltage for causing effective current to leak through the imperfect isolating means, (f) means for enabling said sense amplifier and establishing full predetermined logic levels across said sense nodes, (g) means for disabling said imperfect isolating means and thereby removing isolation between said sense nodes and the bit line, whereby current passing through the sense amplifier to said sense nodes is enabled to charge said bit line capacitance through said imperfect isolating means to a predetermined logic voltage level.