Patent ID: 7890704

Claim:
A method for implementing a cache coherency protocol for a data processing system having multiple processing units communicating over an address and data interconnect, said method comprising: the multiple processing units receiving a system-wide update complete signal over said interconnect indicating a completion of a storage-modifying operation targeting a particular address, where said storage-modifying operation results in a modified first cache line in a first cache memory in a first processing unit among said multiple processing units; determining if a second cache memory in a second processing unit among said multiple processing units held a second cache line associated with said particular address prior to receiving said system-wide update complete signal; wherein said determining further includes accessing a cache directory associated with said second cache memory to determine if said second cache line is in a hover coherency (H) state, wherein the H state indicates that the address tag for the second cache line is valid, and the cache line data in the second cache line is now invalid; wherein when a cache line is marked with an H state, the cache holding the cache line in the H state attempts to reacquire an updated copy of the cache line data from another cache line of another cache which holds the cache line in a modified (M) state; in response to determining said second cache memory held a second cache line associated with said particular address prior to receiving said system-wide update complete operation, issuing a prefetch request for a copy of said modified first cache line to replace said second cache line in said second cache memory before data associated with the particular address of said second cache line is requested by the processing unit associated with the second cache memory; and in response to the prefetch request returning the copy of the modified first cache line, updating said second cache line within said second cache memory with said copy of said modified first cache line.