Patent ID: 6987410

Claim:
A clock recovery circuit for adjusting timing of a clock signal to a data signal, comprising: plural stages of first variable delay elements coupled in series for sequentially delaying said data signal by a first delay amount; plural stages of second variable delay elements coupled in series for sequentially delaying said clock signal generated by a reference clock generating circuit as much as a second delay amount which is larger than said first delay amount; a plurality of timing comparators for sampling each of a plurality of said data signals delayed by each of said plural stages of first variable delay elements with said clock signal delayed by said second variable delay elements whose stages are respectively the same as said plural stages of first variable delay elements; a plurality of EOR circuits for performing exclusive OR operation respectively on sets of a plurality of said sampling results, a pair of sampling results by each of pairs of said sequential timing comparators being taken as one of said sets of a plurality of said sampling results; a timing judging unit for judging said timing of said clock signal generated by said reference clock generating circuit corresponding to said data signal based on an operation result of each of said plurality of EOR circuits; and a recovery variable delay circuit for delaying said clock signal generated by said reference clock generating circuit based on a judgment result of said timing judging unit.