Patent ID: 8278156

Claim:
A method of patterning layout elements during semiconductor device fabrication, comprising: determining an initial pattern, wherein determining the initial pattern includes: selecting first and second layout elements, resizing the first layout element, defining a data representation based on the resized first layout element, and combining the data representation based on the resized first layout element with a data representation of the second layout element; depositing a layer of a first material and patterning the layer to form the initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the initial pattern on a substrate and etching the spacer material such that the spacer material remains adjacent to the first pattern but is removed from other areas of the substrate; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.