Patent ID: 7496730

Claim:
In a computer system having at least one data processor, an operating system and a translation buffer (“TB”) associated with the at least one data processor, and a memory containing at least one Page Table Entry (“PTE”) that maps a virtual address to a physical address, wherein the at least one PTE includes an Access bit and a Valid bit, wherein the value of the Access bit is set when content in the at least one PTE has been accessed, wherein the value of the Valid bit is cleared when content of the at least one PTE becomes invalid, and wherein the TB caches content of the at least one PTE if the at least one data processor has accessed the at least one PTE, a method of reducing the number of translation buffer flushes issued by the operating system, the method comprising: flushing the TB only upon determining that the Access bit of the at least one PTE is set when the Valid bit of the at least one PTE is cleared.