Patent ID: 7991977

Claim:
An advanced processor, comprising: a plurality of processor cores configured to execute multiple threads; a data switch interconnect ring arrangement coupled to the plurality of processor cores and configured to pass information among the plurality of processor cores; a fast messaging network coupled to the plurality of processor cores and a plurality of communication ports; a plurality of fast messaging ring components, separate from the data switch interconnect ring arrangement, coupled to at least two of the processor cores, wherein at least one of the plurality of fast messaging ring components is configured to accommodate point-to-point transfer of messages between at least two of the processor cores and any of the plurality of communication ports; a memory management unit (MMU) coupled to at least one of the plurality of processor cores, the MMU having first, second, and third translation-lookaside buffer (TLB) portions operable in at least two modes, each TLB portion comprises a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification, wherein the at least two modes include a partitioned mode and a global mode; and wherein the first and second TLB portions are configured to allow a thread to freely allocate entries in the first and second TLB portions in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode, and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode.