Patent ID: 7523250

Claim:
A system, comprising: a memory controller; and at least one memory device connected to the memory controller via data, command, and address bus lines, wherein the at least one memory device comprises: a memory core; a transmitting and receiving interface that transmits and receives data, command, and address signals to/from the memory controller and/or to/from another memory device, wherein the system is operable to transmit the data, command, and address signals as serial signal streams in the form of signal frames in correspondence with a predetermined protocol; a frame decoder in a path between the transmitting and receiving interface and the memory core, that decodes signal frames received by the transmitting and receiving interface; and a temporary storage circuit that temporarily stores a number of write data and/or command units decoded by the frame decoder, the temporary storage circuit being in the receiving path between the frame decoder and the memory core and including: a cell array comprising a plurality of memory addresses; and an addressing and selector circuit to which address signals decoded by the frame decoder from signal frames supplied by the memory controller are applied, that addresses the cell array and that performs read/write selection out of/into the cell array, wherein the addressing and selector circuit includes an address pointer and a frame counter.