Patent ID: 8148225

Claim:
A method of forming a memory device comprising: providing a SOI substrate comprising first and second silicon layers and an insulating layer between the first and second silicon layers, wherein the SOI substrate comprises a periphery circuit region and a memory array region; reducing a thickness of the first silicon layer in the periphery circuit region and the memory array region; forming a fully depleted SOI NMOS transistor in the memory array region, which comprises the acts of: forming an oxide material over the SOI substrate; forming a doped polysilicon material of p-type conductivity over said oxide material; forming a gate stack comprising portions of said oxide material and of said doped polysilicon material; forming a p-type well in said first silicon layer below said gate stack; and forming source and drain regions of n-type conductivity on opposite sides of said gate stack within said p-type well in said first silicon layer; forming a partially depleted SOI NMOS transistor in the periphery circuit region, which comprises the acts of: forming the oxide material over the SOI substrate; forming a second doped polysilicon material of n-type conductivity over said oxide material; forming a second gate stack comprising portions of said oxide material and of said second doped polysilicon material; forming a second p-type well in said first silicon layer below said second gate stack; and forming source and drain regions of n-type conductivity on opposite sides of said second gate stack within said second p-type well in said first silicon layer.