Patent ID: 7082177

Claim:
A phase-locked loop (PLL) circuit comprising: (a) a frequency synthesis section comprising; (1) a voltage-controlled oscillator (VCO) adapted to generate a PLL output signal for the PLL circuit based on a control voltage signal applied at an input of the VCO; (2) a loop filter connected to the VCO input; (3) a phase frequency detector (PFD) adapted to compare a feedback signal derived from the PLL output signal to a reference signal; (4) a charge pump adapted to generate charge based on output signals from the PFD; and (5) a first switch adapted to selectively connect the charge pump to the loop filter; (b) a direct frequency control section comprising: (1) a look-up table (LUT) adapted to store digital data values representing a plurality of tuning voltages corresponding to different frequencies for the PLL output signal; (2) a first tuning section adapted to convert a digital data value received from the LUT into a corresponding tuning voltage for the VCO; (3) a second switch adapted to selectively connect the first tuning section to the VCO input to selectively apply the corresponding tuning voltage from the first tuning section as the control voltage signal for the VCO; (4) a second tuning section adapted to generate a digital data value for the LUT corresponding to the control voltage signal applied to the VCO input; and (5) a third switch adapted to selectively connect the VCO input to the second tuning section to selectively enable the second tuning section to update the LUT based on the generated digital data value; and (c) a controller adapted to control the first, second, and third switches.