Patent ID: 7417296

Claim:
A dielectric isolation type semiconductor device comprising: a semiconductor substrate; a dielectric layer disposed adjacent to an entire area of a principal plane of said semiconductor substrate; a first semiconductor layer of a first conductivity type and of a low impurity concentration bonded to said semiconductor substrate through said dielectric layer; a trench isolation annularly formed in said first semiconductor layer to separate said first semiconductor layer in a lateral direction so as to provide an element range; a high withstand-voltage device having a second semiconductor layer of the first conductivity type and of a high impurity concentration selectively formed on a surface of a central portion of said element range within said first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in said element range at a location apart from said second semiconductor layer so as to surround said second semiconductor layer; a first electrode disposed on and joined to a surface of said second semiconductor layer; a second electrode disposed on and joined to a surface of said third semiconductor layer; a first field plate disposed on said first semiconductor layer so as to cover said second semiconductor layer; a second field plate disposed on said first semiconductor layer so as to cover said third semiconductor layer and surround said first field plate; and a first high silicon concentration region formed in a porous oxide film region extending into said substrate and constituting a part of said dielectric layer at a location right under said first electrode; wherein said first electrode and said first high silicon concentration region are electrically connected to each other, and are configured to confine an electric potential within said porous oxide film between said substrate and said first high silicon concentration region.