Patent ID: 7996661

Claim:
A dynamic reconfigurable circuit comprising: a sequencer generating a first signal, a second signal and a PC value, the PC value for implementing a context corresponding to an instruction from a user or an upper program, the context being information which indicates setting of an operation of each of a plurality of processing elements and a connection between the processing elements; a condition branch signal generator generating a condition branch signal that indicates a start and stop of context switching when the first signal is received by the condition branch signal generator; a configuration memory storing the context, the configuration memory outputting the context based on the PC value; and a PE array that receives the second signal and the context, wherein the PE array includes: the processing elements for performing certain calculations according to a description of the context; a network circuit switching a connection of input/output value of data of each of the processing elements; and a counter performing a certain loop processing according to the description of the context and counting the number of loop implementations of the loop processing when the condition branch signal or the second signal is received.