Patent ID: 7916564

Claim:
A multi-chip semiconductor device receiving an externally provided current address and comprising: a plurality of semiconductor chips, wherein each one of the plurality of semiconductor chips comprises: a memory arranged in a plurality of memory blocks; a storing unit configured to store redundancy information portions; and a comparing unit configured to respectively compare the current address with each one of the redundancy information portions and generate an enable signal or a disable signal based on the comparison result, wherein the redundancy information portions comprise: a first redundancy information portion indicating a constituent redundancy block located in the memory of the semiconductor device and associated with a defective memory block in the plurality of memory blocks; a second redundancy information portion indicating an outgoing non-constituent redundancy block located in another one of the plurality of semiconductor chips and associated with a defective memory block in the plurality of memory blocks; and a third redundancy information portion indicating an incoming non-constituent redundancy block located in the semiconductor chip and associated with a defective memory block located in the memory of another one of the plurality of semiconductor chips.