Patent ID: 8098791

Claim:
A shift register comprising: a control circuit, for generating a control signal according to a start pulse signal during the control circuit is enabled; a pull-up circuit, for generating a gate pulse signal according to a clock signal during the pull-up circuit is enabled by the control signal, wherein the pull-up circuit comprises a dual-gate transistor, a first gate of the dual-gate transistor is electrically coupled to receive the control signal, a second gate of the dual-gate transistor is electrically coupled to receive a predetermined voltage, the first source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the second source/drain of the dual-gate transistor is electrically coupled to receive the clock signal; and a pull-down circuit, for pulling a potential at the first gate of the dual-gate transistor and another potential at the output terminal for the gate pulse signal down to a power supply potential; wherein the control circuit comprises a first transistor and a second transistor, the gate of the first transistor is electrically coupled to receive an enabling signal, the first source/drain of the first transistor is electrically coupled to the gate of the second transistor, and the second source/drain of the first transistor is electrically coupled to receive another clock signal phase-inverted with respect to the clock signal; the first source/drain of the second transistor serves as an output terminal for the control signal, and the second source/drain of the second transistor is electrically coupled to receive the start pulse signal.