Patent ID: 7254688

Claim:
A data processing apparatus that arbitrates sharing of a single semiconductor memory circuit among multiple data processing circuits, comprising: a semiconductor memory circuit that executes operations corresponding to a command signal, address signal and clock signal received external to the semiconductor memory circuit, the semiconductor memory circuit includes a clock enable signal input, and a chip select signal input; and a data processing circuit that supplies the semiconductor memory circuit with a first clock enable signal output to the clock enable signal input for enabling an input of the clock signal when active and disabling the input of the clock signal when inactive, and a first chip select signal output to the chip select signal input for enabling input of command signals when the chip select signal is active and disabling input of command signals when the chip select signal is inactive; wherein before the data processing circuit ends control of the semiconductor memory circuit and stops supplying the first clock enable signal output and first chip select signal output, a different data processing circuit starting control of the semiconductor memory circuit supplies the semiconductor memory circuit with a second clock enable signal output to the clock enable signal input and a second chip enable signal output to the chip enable signal input, the second clock enable signal output and the second chip enable signal output having clock enable signal and chip select signal logic values at the same state as the first clock enable signal output and the first chip enable signal output provided by the data processing circuit ending control of the semiconductor memory circuit.