Patent ID: 8897088

Claim:
A system on chip (SoC) comprising a memory array, wherein the memory array comprises: n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data; m bit lines each coupled to a corresponding one of the m columns of bit cells; m write drivers each coupled to a corresponding one of the m bit lines; an AND gate having n inputs each coupled to a corresponding one of the m bit lines, the AND gate having an output line; and an OR gate having n inputs each coupled to a corresponding one of the m bit lines, the OR gate having an output line, further comprising a test controller coupled to receive the output line from the AND gate and the output line form the OR gate, wherein the test controller on the SoC is operable to test the memory array by writing all ones to a row of bit cells and then reading the row of bit cells and testing the output of the AND gate to determine if all of the bit cells in the row contain a one; and by writing all zeros to the row of bit cells and then reading the row of bit cells and testing the output of the OR gate to determine if all of the bit cells in the row contain a zero.