Patent ID: 7408496

Claim:
A pipelined analog-to-digital converter, comprising: an amplifier comprising first and second input circuits; first and second pipeline stages, the pipeline stages sharing the amplifier, the first pipeline stage being switchably connectable to the first input circuit and the second pipeline stage being switchably connectable to the second input circuit; and a clock generator generating first and second clock signals and applying the first and second clock signals to the pipeline stages and amplifier, wherein the first clock signal causes the first stage to perform a first operation and the second stage to perform a second operation, the first clock signal disconnecting the first pipeline stage from the first input circuit during the first operation and connecting the second pipeline stage to the second input circuit during the second operation, and wherein parasitic capacitance is discharged from the first input circuit while the first clock signal is asserted by connecting an input node of the first input circuit to a voltage source.