Patent ID: 8576605

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged therein, each of the memory cells including a variable resistor and provided between a first line and a second line; a control circuit configured to apply to the memory cell through the first and second lines a writing voltage for writing data or a reading voltage for reading data; and a sense amplifier circuit configured to sense data retained in the memory cell based on a current flowing through the first line, in a data writing operation, the control circuit being configured to apply the writing voltage to each of n number of memory cells configuring one unit, wherein n≧3, such that the n number of memory cells may be supplied with different resistance values from one another, a number of combinations of the different resistance values that are given to the n number of memory cells configuring the one unit representing n! patterns of data, where n! denotes factorial of the n number, and in a data reading operation, the sense amplifier circuit being configured to compare a relationship of the resistance values of the n number of memory cells configuring the one unit, and read out n! patterns of data from the one unit, wherein in the data reading operation, the sense amplifier circuit compares a relationship of the resistance values of a every combination of groups of two of the n number of memory cells configuring the one unit, and reads out the n! patterns of data retained in the one unit in accordance with a data combination obtained as a result of comparison.