Patent ID: 7904677

Claim:
A memory control device for controlling access to a memory having a plurality of banks in a storage area, the device comprising: a packet disassembly section for disassembling received packet data into segments and detecting packet quality information; a memory management section having an address management table for managing an address of a storage destination of the plurality of banks, the memory management section being used for managing a state in which the packet data is stored according to the packet quality information; and a memory control section including: a segment/request information disassembler for disassembling the segments into data by an access unit by which the memory can be written/read and for generating write requests or read requests according to the access unit; and a memory access controller for exercising memory access control to write the data to the plurality of banks in response to the write requests or to read out the data from the plurality of banks in response to the read requests, wherein the memory access controller avoids banks access to which is prohibited because of bank constraints, extracts write requests or read requests corresponding to accessible banks from the write requests or the read requests generated, and gains write/read access to the memory.