Patent ID: 7999323

Claim:
A semiconductor structure comprising: a semiconductor substrate; at least one nMOS device located on one region of said semiconductor substrate, the at least one nMOS device including a first gate stack comprising a first interfacial layer on the semiconductor substrate, a first dielectric layer having a thickness of less than 5 nm on the interfacial layer, a low workfunction elemental metal having a workfunction of less than 4.2 eV and a thickness of less than 3 nm on the first dielectric layer, and a first metallic capping layer on the low work function elemental metal; and at least one pMOS device located on another region of said semiconductor substrate, the at least one pMOS device including a second gate stack comprising at least a high workfunction elemental metal having a workfunction of greater than 4.9 eV and a second metallic capping layer, wherein a surface oxide layer is present between the high work function element metal and the second metallic capping layer of the at least one pMOS, said surface oxide layer is not present between the low work function element metal and the first metallic capping layer of the at least one nMOS device.