Patent ID: 8421514

Claim:
A hazard-free minimal-latency flip-flop (HFML-FF) comprising: a master latch comprising: a first relay gate having an input to accept a D 1 signal with a binary value, an input to accept a clock signal, an input to accept an inverted shadow-D 2 signal, and an output to supply a D 2 signal with a binary value equal to a shadow-D 2 binary value, the first relay gate output supplied in response to the D 1 signal, the inverted shadow-D 2 signal, and the clock signal; a first shadow gate having an input to accept a shadow-D 1 signal, an input to accept the clock signal, and an output to supply a shadow-D 2 signal and the inverted shadow-D 2 signal, the first shadow gate outputs supplied in response to the shadow-D 1 signal and clock signal; a slave latch comprising: a second relay gate having an input to accept the D 2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal with a binary value equal to the D 1 and shadow-Q signal binary values, the second relay gate output supplied in response to the D 2 signal, the inverted shadow-Q signal, and the clock signal; and, a second shadow gate having an input to accept a signal selected from a group consisting of the D 2 signal and the shadow-D 2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal, the second shadow gate output supplied in response to the selected D 2 signal and clock signal.