Patent ID: 8405087

Claim:
A pixel structure, disposed on a substrate having an array of a plurality of pixel areas, the pixel structure being disposed in each of the pixel areas, the pixel structure comprising: a scan line, a gate electrode, and at least a common electrode wire disposed in each of the pixel areas, wherein the common electrode wire is positioned only in a portion of the pixel area; a first capacitance storage electrode disposed in each of the pixel areas, the first capacitance storage electrode being electrically connected between two adjacent common electrode wires; a gate insulation layer covering the scan line, the gate electrode, the common electrode wire, and the first capacitance storage electrode; a semiconductor layer disposed on the gate insulation layer above the gate electrode; a data line, a source, and a drain disposed in each of the pixel areas, the source and the drain being disposed on two sides of the semiconductor layer; a passivation layer disposed on the substrate to cover the data line, the source, and the drain, wherein the passivation layer above the drain has a contact window; and a pixel electrode electrically connected with the drain through the contact window.