Patent ID: 6871308

Claim:
A semiconductor inspection method for simultaneously detecting (1) stuck-at failures and (2) short-circuited adjacent lines in a logic circuit of a semiconductor apparatus, the method comprising: extracting data representing input lines of a logic circuit of a semiconductor apparatus represented by layout data and identifying combinations of adjacent input lines of said input lines; selecting one combination of adjacent input lines from said extracted combinations and setting each of said selected adjacent input lines to a first logical value of “0” or “1” and setting said input lines other than the selected adjacent input lines to a second logical value of “0” or “1”, so that an expected logical output value is output by such logic circuit when a stuck-at failure and a short circuit between the adjacent lines do not exist and an unexpected output logical value is output when at least one of a stuck-at failure and a short circuit between the adjacent lines does exist; and monitoring an output of such logic circuit that receives the input logical values, and comparing the monitored output with an output logical value that is expected when the input logical values are input to such logic circuit.