Patent ID: 7123679

Claim:
A counter comprising: a first output signal generator for outputting a first output signal in which a low level and a high level are output once per cycle of a clock signal, in response to the clock signal; an N-th output signal generator for outputting an N-th output signal in which a low level and a high level are output every 2 N−1 cycles of the clock signal, in response to the clock signal and an N−1th output signal, the N-th output signal generator including a clock input at which only the clock signal is applied, where N is a natural number greater than 1; an N+1th output signal generator for outputting an N+1th output signal in which a low level and a high level are output once per cycle of the N-th output signal, in response to the N-th output signal, the N-th output signal being directly connected to a clock input of the N+1th output signal generator; an N+M-th output signal generator for outputting an N+M-th output signal in which a low level and a high level are output every 2 M−1 cycles of the N-th output signal, in response to the N-th output signal and an N+M−1th output signal, wherein the first through N+M-th output signals represent logic values of an N+M-bit counter having the first output signal as the least significant bit (LSB) and the N+M-th output signal as the most significant bit (MSB); and a plurality of state generators including an N+M+1th output signal generator for outputting an N+M+1th output signal in which a low level and a high level are output once per cycle of the N+M-th output signal, in response to the N+M-th output signal and an N+M+K-th output signal generator for outputting an N+M+K-th output signal in which a low level and a high level are output every 2 K−1 cycles of the N+M-th output signal, in response to the N+M-th and N+M+K−1th output signals, where K is a natural number greater than 1, wherein each state generator receives a final output signal generated by a preceding state generator as a clock.