Patent ID: 7287119

Claim:
An integrated circuit memory device comprising: a memory core including a plurality of memory cells; a first set of pins coupled to the memory core, the first set of pins to receive a row address that identifies a row of the memory core, followed by a column address that identifies a column location of the row; a second set of pins coupled to the memory core, the second set of pins to receive a sense command followed by a write command, wherein the sense command specifies sensing of the row, wherein the write command specifies that the memory device receive write data to be stored at the column location, wherein the write command is presented internally to the memory device after a first delay time has transpired from when the write command is received at the second set of pins; a third set of pins to receive the write data after a second delay time has transpired from when the write command is received at the second set of pins; and a column access path coupled to the third set of pins and the memory core, the column access path to convey the write data to the column location.