Patent ID: 7640286

Claim:
A data processing apparatus for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result, the data processing apparatus comprising: multiplier logic circuitry for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors; sum logic circuitry for performing a sum operation to add a first set of bits of each of the pair of 2n-bit vectors; sticky determination logic circuitry for determining a sticky value from a second set of bits of each of the pair of 2n-bit vectors; and selector logic circuitry for deriving the n-bit result from the output of the sum logic with reference to the sticky value; the sticky determination logic circuitry comprising: a half-adder configured to generate carry and sum vectors from a negated version of the second set of bits of each of the pair of 2n-bit vectors; combination logic configured to perform a logical XOR operation on the carry and sum vectors with the least significant carry bit set to a logic 1 value; and sticky value derivation logic configured to derive the sticky value from the output of the combination logic, wherein n is an integer.