Patent ID: 8390352

Claim:
A circuit, comprising: one or more clock circuits; a first delay line configured to generate a first delay output, the first delay line comprising m delay elements, wherein m is an integer greater than 0; a second delay line configured to generate a second delay output, the second delay line comprising m+n delay elements, wherein n is an integer greater than 0, and wherein the first delay line and the second delay line receive a reference clock signal from at least one of the one or more clock circuits; a delay-measure circuit configured to: generate an offset pulse based on the first delay output and the second delay output; generate a delay measure based on the offset pulse; and output the delay measure; and an application circuit configured to: receive the delay measure and at least one input signal, wherein the at least one input signal is different from the reference clock signal; adjust the at least one input signal based on the delay measure to generate at least one output signal; and output the at least one output signal.