Patent ID: 7099171

Claim:
In a content addressable memory cell including a circuit operating from a predetermined supply voltage for storing a first bit of data at a first point and a second bit of data at a second point, a system for comparing the first bit and the second bit with a third bit of test data transmitted on a first line and a fourth bit of test data transmitted on a second line, the system comprising: a first transistor switchable to a first state in response to a first predetermined relationship between the first and second hits and the third and fourth bits and switchable to a second state in response to a second predetermined relationship between the first and second bits and the third and fourth bits; a second transistor operatively coupled to the first transistor and to the first line, the second transistor drawing approximately no current from the first line; and a third transistor operatively coupled to the first transistor and to the second line, wherein the first transistor and the second transistor share a common node that is precharged.