Patent ID: 8138042

Claim:
A method of increasing a capacitance area of a tri-gate memory cell, where the tri-gate memory cell comprises a substrate, a first electrically insulating layer over the substrate, and a tri-gate capacitor and a tri-gate transistor over the first electrically insulating layer, and where the tri-gate capacitor has a first semiconducting fin, the method comprising: depositing an inter-layer dielectric over the first electrically insulating layer and around the tri-gate capacitor and the tri-gate transistor, the inter-layer dielectric having an inter-layer dielectric surface; forming a trench in the inter-layer dielectric in which at least a portion of the first semiconducting fin is exposed; conformally depositing a first metal layer over the inter-layer dielectric surface, in the trench, and over the first semiconducting fin; conformally depositing a second electrically insulating layer over the first metal layer; conformally depositing a second metal layer over the second electrically insulating layer; and removing portions of one or more of the first metal layer, the second electrically insulating layer, and the second metal layer.