Patent ID: 6878582

Claim:
A method of fabricating a low gate induced leakage current (GIDL) MOSFET device comprising: forming an offset film on horizontal surfaces of a patterned central gate conductor and surrounding substrate areas; depositing a conductive diffusion barrier on sidewalls of the central gate conductor; forming metallic spacers over the conductive diffusion barrier on the sidewall of the central gate conductor stripping the offset film to form hanging metallic spacers over undercut regions; oxidizing the central gate conductor beneath the hanging metallic spacers to prevent a rectifying junction from being formed between the central gate conductor and subsequently formed left and right side wing gate conductors; depositing a polysilicon layer to fill the undercut regions below the hanging metallic spacers; removing the polysilicon layer by an isotropic etch while leaving the polysilicon layer remaining in the undercut regions below the hanging metallic spacers to form left and right side wing gate conductors.