Patent ID: 6949777

Claim:
A method of controlling an insulated gate transistor, comprising the steps of: providing an insulated crate transistor comprised of a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film, the semiconductor thin film having a thickness and an impurity concentration so that an electric potential of the first conductive gate causes depletion of carriers between the first main surface and the second main surface of the semiconductor thin film between the first and second semiconductor regions and below the first conductive gate; injecting carriers of the second conductivity type into the semiconductor thin film from the third semiconductor region; and thereafter applying a first electric potential to the first conductive gate to form a channel of the first conductivity type on a portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region.