Patent ID: 7880662

Claim:
An analog-to-digital converter for generating an output digital value equivalent to the difference between two analog signal values comprising: at least one input for receiving a first analog signal level and a second analog signal level; an input for receiving a ramp signal; a counter which is operable to count in a single direction; a control stage which is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal; and an output for outputting a value accumulated by the counter during a period when it is enabled, wherein the analog-to-digital converter is operable over a conversion cycle having two phases, with the ramp signal being reset between phases, and wherein the control stage is operable: during a first phase of the conversion cycle, to compare the ramp signal with the first analog signal level and to enable the counter during a portion of the time period between the time at which the ramp signal equals the first analog signal level and an end of the ramp signal, and during a second phase of the conversion cycle, to compare the ramp signal with the second analog signal level and to enable the counter during a portion of the time period between a start of the ramp signal and a time at which the ramp signal equals the second analog signal level; or, during a first phase of the conversion cycle, to compare the ramp signal with the first analog signal level and to enable the counter during a portion of the time period between a start of the ramp signal and a time at which the ramp signal equals the first analog signal level, and during a second phase of the conversion cycle, to compare the ramp signal with the second analog signal level and to enable the counter during a portion of the time period between the time at which the ramp signal equals the second analog signal level and an end of the ramp signal.