Patent ID: 7400164

Claim:
A method of using an array of selectable impedances for an integrated circuit output stage, said method comprising: matching an output impedance of the integrated circuit with an expected load so as to improve integrity of a high-frequency part of a broadband data signal, the matching being performed by: connecting first and second differential output terminals of the integrated circuit output stage to first and second array input terminals, respectively, of an array of capacitive elements and switch elements, the array including first and second array output terminals connected to the first and second array input terminals by first and second conductors, respectively, the array including a plurality of circuit branches, each circuit branch having a first end connected to one of the first and second conductors between the array input and output terminals, at least one circuit branch being connected on the first end thereof to the first conductor and at least one circuit branch being connected on the first end thereof to the second conductor, each circuit branch having a second end connected to a ground terminal, wherein each circuit branch has at least one of the capacitive elements connected in series with at least one of the switch elements, the array including one or more array control terminals for receiving one or more control signals that cause the switch elements to be activated or deactivated; and selectively applying one or more control signals to the one or more array control terminals to cause one or more of the switch elements to be activated or deactivated, wherein activation of one or more of the switch elements causes the capacitive elements connected in series with the activated switch elements to be placed in-circuit such that a selectable output impedance is provided at the first and second array output terminals.