Patent ID: 8068156

Claim:
A CMOS solid state imaging device comprising: an imaging region and a peripheral circuit region; a pixel portion in the imaging region that performs photoelectric conversion according to a quantity of received light; a transfer gate in the imaging region configured to read out charges obtained through the photoelectric conversion in the pixel portion; and peripheral transistors for processing signals from the pixel portion provided outside a periphery of the imaging region in the peripheral circuit region, the peripheral transistors including a logic transistor with a lightly doped drain (LDD) provided downstream of the charges transferred by the transfer gate, wherein, NLDD(Tx) is an impurity concentration of the LDD corresponding to the transfer gate, and NLDD(Logic) is an impurity concentration of the LDD of the logic transistor in the peripheral circuit region, NLDD(Tx)<NLDD(Logic), a voltage applied to the transfer gate is higher than a voltage applied to the logic transistor by a difference of between 0.5 V and 1.0 V, the difference in the voltage applied to the transfer gate and the voltage applied to the logic transistor affects a gate length of the transfer gate, and within the difference the pixel portion remains unaffected by the difference.