Patent ID: 7888216

Claim:
A method of fabricating a semiconductor device comprising: forming in the substrate a well region comprising a first type of dopant; forming a base region in the well region, the base region comprising a second type of dopant different from the first type of dopant; forming a source region and a drain region in a substrate, wherein the source and drain regions comprise the first type of dopant; forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein, wherein the well region surrounds the drain region and the base region, and wherein the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of length “L”, wherein L is substantially less than half the length of the gate electrode.