Patent ID: 7646091

Claim:
A semiconductor integrated circuit (IC) package which comprises: a substrate having a first surface and a second surface wherein; a first layer of the substrate includes, a first ground plane enabling electrical connection with low speed electronic circuitry, and a second ground plane that is spatially separated and electrically isolated from the first ground plane, the second ground plane enabling electrical connection with high speed electronic circuitry; a second layer of the substrate includes, a third ground plane configured for electrical connection with low speed electronic circuitry, and a fourth ground plane that is spatially separated and electrically isolated from the third ground plane, the third ground plane configured for electrical connection with high speed electronic circuitry; a plurality of electrical connections that electrically connect the first ground plane with solder balls mounted on the second surface of the substrate; a plurality of additional electrical connections that electrically connect the second ground plane with solder balls mounted on the second surface of the substrate; and peripheral electrical contacts arranged on the substrate and configured for connection with electronic circuitry external to the package; and at least one reference plane associated with each layer of the substrate and the ground planes included thereon.