Patent ID: 7614141

Claim:
A method of fabricating an integrated circuit device, comprising: receiving an integrated circuit device design; identifying at least one portion of the integrated circuit design where a modification of the integrated circuit device design is to be performed in order to reduce via-field inductance; modifying the integrated circuit device design, to generate a modified integrated circuit device design, by introducing at least one T-jog configuration in at least one via of the at least one portion of the integrated circuit device design; and fabricating the integrated circuit device based on the modified integrated circuit device design by providing a plurality of layers of a substrate and providing a plurality of vias extending through the plurality of layers from a surface of the substrate to designated layers in the plurality of layers, wherein: modifying the integrated circuit design further comprises selecting a wiring layer in a plurality of wiring layers that is closest to the surface of the substrate upon which one or more surface pads, associated with the plurality of vias, are provided for connecting a surface metallization circuit element to the designated layers in the plurality of layers, the at least one via, in the fabricated integrated circuit device, has the T-jog configuration in which the at least one via has two jogs, a first jog of the two jogs is formed, in the fabricated integrated circuit device, in a direction parallel to the plurality of layers towards a first adjacent via of the plurality of vias and a second jog of the two jogs is formed in a direction parallel to the plurality of layers towards a second adjacent via of the plurality of vias, and the first jog and second jog of the T-jog configuration are formed in the selected wiring layer that is closest to the surface of the substrate upon which one or more surface pads, associated with the plurality of vias, are provided.