Patent ID: 8565370

Claim:
A method of driving a gate line of a device including a shift register, the method comprising: maintaining, at a current stage (m), a first node signal at a high level based on one of a previous stage of a vertical start signal; outputting a clock signal as a gate signal provided to the gate line in response to the first node signal in a high state; maintaining the first node signal at a ground voltage by a first node holding part responsive to a clock signal of a stage two stages (m+2) beyond the current stage; maintaining the gate signal at the ground voltage by a gate holding part responsive to a clock signal of a stage three stages (m+3) beyond the current stage; and maintaining the gate signal at the ground voltage by a pull-down part responsive to a gate signal of the next stage or the vertical start signal, wherein the clock signal of the stage three stages (m+3) beyond the current stage is delayed by about ¾ period of the current stage (m) clock signal.