Patent ID: 6900098

Claim:
A method to fabricate a twin MONOS memory comprising: forming a deep N-well in a substrate; forming an oxide-nitride-oxide (ONO) layer overlying said substrate; depositing a first polysilicon layer overlying said ONO layer; depositing a cap nitride layer overlying said first polysilicon layer; patterning said cap nitride layer to said first polysilicon layer; forming an oxide mask on sidewalls of said patterned cap nitride layer; thereafter etching through said first polysilicon layer not covered by said cap nitride layer and said oxide mask to form first trenches and removing said ONO layer exposed within said first trenches by said etching; forming oxide spacers on sidewalls of said first trenches; thereafter depositing a second polysilicon layer within said first trenches and recessing said second polysilicon layer below said cap nitride layer; depositing an oxide layer overlying said recessed second polysilicon layer wherein said recessed second polysilicon layer forms raised diffusions; etching away remaining said first polysilicon layer not covered by said oxide mask leaving control gates underlying said oxide mask wherein said ONO layer lies only underneath said control gates and leaving second trenches; depositing a second oxide layer lining said second trenches; thereafter depositing a third polysilicon layer within said second trenches to form word gates between each two control gates and to form word lines overlying and crossing said word gates; forming source and drain regions; covering said gates with a dielectric layer; and making contacts through said dielectric layer to said source and drain regions to form word line contacts and diffusion contacts to complete said Twin MONOS memory device.