Patent ID: 7962728

Claim:
A data processor comprising: a data processing circuit executing instruction flows; and a data transfer unit, wherein the data processing circuit comprises a register to which the instruction flows reference or write, and a flag bit indicating a validity of the register, wherein the data processing circuit executes a first instruction for the data transfer unit to write data into the register, wherein the data processing circuit executes a second instruction to reference the register and invalidate the register after using the register, wherein if the register is valid when the data transfer unit loads the data of the first instruction for writing to the register, the data transfer unit waits until the register is invalidated to write the data into the register, wherein if the register is invalid when the data transfer unit loads the data of the first instruction for writing to the register, the data transfer unit writes the data into the register, wherein if the register is invalid when the data processing circuit executes the second instruction, the data processing circuit waits to reference the register, and wherein if the register is valid when the data processing circuit executes the second instruction, the data processing circuit references the register and invalidates the register.