Patent ID: 8404528

Claim:
A fabricating method of a pixel structure, comprising: providing a substrate having an array of a plurality of pixel areas; forming a scan line, a gate electrode, and at least a common electrode wire in each of the pixel areas, wherein the common electrode wire is positioned only in a portion of the pixel area; forming a first capacitance storage electrode in each of the pixel areas, the first capacitance storage electrode being electrically connected between two adjacent common electrode wires; forming a gate insulation layer covering the scan line, the gate electrode, the common electrode wire, and the first capacitance storage electrode; forming a semiconductor layer on the gate insulation layer above the gate electrode; forming a data line, a source, and a drain in each of the pixel areas, the source and the drain being formed on two sides of the semiconductor layer; forming a passivation layer on the substrate to cover the data line, the source, and the drain; forming a contact window in the passivation layer above the drain to expose the drain; and forming a pixel electrode in each of the pixel areas, the pixel electrode being electrically connected with the drain through the contact window.