Patent ID: 8279679

Claim:
A volatile semiconductor memory device comprising: a semiconductor layer; a memory cell array comprising a memory string, the memory string comprising a plurality of memory cells connected in series; a bit-line electrically connected to a first end of the memory string; a source-line electrically connected to a second end of the memory string; and a control circuit configured to control voltages applied to the semiconductor layer, control gates of the memory cells, the bit-line, and the source-line, the control circuit being configured to perform, in a write operation to the memory cell and a verify operation for verifying threshold voltage of the memory cell, a voltage control to provide the memory cell with a plurality of threshold voltage distributions, the control circuit being configured to apply, in a read operation from the memory cell, to a selected memory cell a read voltage between the lower and upper limits of the threshold voltage distributions, and apply to an unselected memory cell a first read-pass voltage higher than the upper limit of a first threshold voltage distribution, the first threshold voltage distribution being the maximum distribution of the threshold voltage distributions, and the control circuit being configured to apply, at least during a verify operation in a first write operation conducted before a second write operation that completes writing to the first threshold voltage distribution, a second read-pass voltage lower than the first read-pass voltage to the unselected memory cell, and apply to the semiconductor layer and the source-line a positive voltage.