Patent ID: 8040715

Claim:
A semiconductor storage device comprising: a semiconductor substrate; a plurality of memory cell arrays laminated on the semiconductor substrate, each of the memory cell arrays including a plurality of first wirings and a plurality of second wirings formed to intersect with each other, and memory cells each arranged at respective intersections between the first wirings and the second wirings, each of the memory cells including a rectifier element and a variable resistance element connected in series; and a control circuit operative to selectively drive the first and second wirings, the first and second wirings being shared by two of the memory cell arrays located adjacent to each other in a lamination direction; the control circuit being operative to provide, in a first memory cell array selected from among the plurality of the memory cell arrays, a first potential to a selected first wiring, a first standard potential that is lower than the first potential to a non-selected first wiring, a second potential that is lower than the first potential to a selected second wiring, and a second standard potential that is higher than the second potential to a non-selected second wiring, the control circuit being operative to provide, in a non-selected second memory cell array that shares the first wiring with the first memory cell array as well as in a non-selected third memory cell array located more distant from the first memory cell array than the second memory cell array, the first potential to all of the first wirings and all of the second wirings, and the control circuit being operative to provide, in a non-selected fourth memory cell array that shares the second wiring with the first memory cell array, as well as in a non-selected fifth memory cell array located more distant from the first memory cell array than the fourth memory cell array, the second potential to all of the first wirings and all of the second wirings.