Patent ID: 7882322

Claim:
A method to address a cache memory with a control data word that is transmitted from a processor unit to the cache memory over a double data rate bus in which a first group of bits that comprises one portion of the control data word is transmitted in response to an edge of a bus clock signal and a second group of bits that comprises another portion of the control data word is transmitted in response to a next following edge of the bus clock signal, the method comprising: transmitting the first group of bits comprising congruent class data for a cache address directory memory look up; latching the first group of bits in an interface register by an end of a first local clock cycle; latching the second group of bits in a compare address register during the first local clock cycle; arbitrating priority based on the first group of bits in the interface register starting in a beginning of a next second local clock cycle; latching the first group of bits latched in the interface register in a directory address register, addressing the directory, and latching the addressed content of the directory in a directory register in a next third local clock cycle; latching the second group of bits latched in the compare address register in a compare pipe register in the third local clock cycle; and comparing the content of the directory register with the second group of bits in the compare pipe register in a next fourth local clock cycle.