Patent ID: 7804169

Claim:
An integrated circuit package comprising: a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface; a plurality of conductive lines disposed on a portion of the second surface of the substrate; a semiconductor chip disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate; a plurality of bonding pads is disposed on a side of the semiconductor chip which is toward the second surface of the substrate; a plurality of bonding pads disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the conductive lines; and a first heat dissipation layer disposed in the first hole and extended into the chamber, wherein the first heat dissipation layer directly contacts one of the bonding pads.