Patent ID: 7061224

Claim:
An apparatus comprising: a delay lock loop circuit; a first input signal trace coupled to the delay lock loop circuit to provide a first input signal to the delay lock loop circuit; a first output signal trace coupled to the delay lock loop circuit to receive a first output signal from the delay lock loop circuit; first circuitry coupled to the first input signal trace, the first output signal trace and the delay lock loop circuit to generate a first test output signal on a first test output signal trace, the first test output signal indicative of a relationship between a first transition on the first input signal and a second transition on the first output signal; a second output signal trace coupled to the delay lock loop circuit to receive a second output signal from the delay lock loop circuit; second circuitry coupled to the first output signal trace, the second output signal trace and the delay lock loop circuit to generate a second test output signal on a second test output signal trace, the second test output signal indicative of a relationship between a third transition on the first output signal and a fourth transition on the second output signal; and wherein the first input signal trace and the first output signal trace are coupled to a first one or more delay cells of the delay lock loop circuit and the second output signal trace is coupled to a second one or more delay cells of the delay lock loop circuit.