Patent ID: 7895415

Claim:
An apparatus, comprising: a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system; and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system based, at least in part, on the sharing behavior between threads; a state logic to store data corresponding to a state in a finite state machine (FSM) and to control transitions between states in the FSM based on the cache sharing behavior between the threads, the state logic to control the first unit and the second unit; the first unit comprising: a detection logic to detect an inter-thread cache conflict condition between two or more threads in the multi-threaded computing system; and a classification logic to classify a thread as one of, a quiet thread, a non-quiet thread, a victim thread, a hybrid thread, and a bully thread, based on thread-to-thread affinity as determined by relative interdependent cache metrics, and the second unit comprising: a confinement logic to limit availability of cache space in the multi-threaded system to a bully thread; the FSM having four states, the four states being: an initial state where threads are run for a warm-up period, where miss rate counters are then reset, where threads are then run for a sample period, and where threads are classified as quiet or non-quiet based on miss metrics generated during the sample period; a classification state where accesses from non-quiet threads are isolated, where exclusive way partitioning among non-quiet threads is performed, where threads are then run for a test period, and where threads are then classified based on a change in miss metrics; a confinement state where cache space availability is limited for a bully thread, where a number of ways to allocate to a bully thread is determined, and where the number of ways is allocated to the bully thread to stabilize the bully thread; and a stable state that is to be held until one or more of a pre-determined number of cycles are executed in the multi-threaded computing system and a change in the composition of the set of threads.