Patent ID: 6949794

Claim:
A non-volatile semiconductor memory device comprising: a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer; and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit, wherein the shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor, and wherein the distance, where the diffusion layer region connected to the bit line or the source line overlaps the gate electrode, is made smaller than the distance, where the diffusion layer region connected to the memory cell transistor overlaps the gate electrode, at the positions thereof which have the same depth from the boundary between the semiconductor substrate and a gate insulation film.