Patent ID: 7411424

Claim:
A 2-input programmable logic generator (PLG) to perform as a 2-input look-up table with minimum number of PMOS transistors, the PLG comprising: pass gates for routing signals to an output of the PLG, wherein the pass gates are controlled by a first input to the PLG; programmable switches for routing a second input signal and a high-logic voltage to the pass gates, wherein the switches are NMOS transistors, gates of which are controlled by programmable memory units; and inverters for inverting signals; wherein the second input, the high-logic voltage, or their inverses are programmably routed to each of the pass gates; and wherein: the second input and the high-logic voltage are connected to a first node through a first and a second programmable switch, respectively, and wherein the first node is connected to a first pass gate through a third switch and also connected through a series combination of a first inverter and a forth switch; and the second input and the high-logic voltage are connected to a second node through a fifth and a sixth switch, respectively, and wherein the second node is connected to a second pass gate through a seventh switch and also connected through a series combination of a second inverter and an eight switch.