Patent ID: 8722536

Claim:
A method of making an integrated circuit substrate, comprising: laminating a plurality of metal circuit layers between insulating layers, wherein a top two of the metal circuit layers are power supply planes, and wherein a top one of the metal circuit layers includes power supply lands for connecting power supplies to a die, wherein a first plurality of the power supply lands have contiguous connection to the power supply plane formed by the top metal circuit layer; forming small-diameter blind vias between an inner one of the top two metal circuit layers and a second plurality of the power supply lands; forming large-diameter holes near edges of the substrate; plating a first plurality of the holes from the bottom of the substrate to the top metal circuit layer to form first large-diameter plated-through holes; plating a second plurality of the holes from the bottom of the substrate to the inner metal circuit layer to form second large-diameter plated-through holes; forming a plurality of small-diameter conductive vias proximate to and surrounding the holes; and providing terminals electrically connected to the bottoms of the first and second large-diameter plated-through holes to form power supply terminals of the substrate.