Patent ID: 7830176

Claim:
An integrated circuit comprising: a signal line carrying a line signal; a first signal driver circuit coupled to said signal line at a first location on said integrated circuit, said first signal driver circuit, responsive to a first control signal, configured to drive said line signal to a first signal level; a second signal driver circuit coupled to said signal line at a second location on said integrated circuit, said second location being separated from said first location with one or more further circuit elements disposed therebetween, said second signal driver circuit, responsive to a second control signal, configured to drive said line signal to a second signal level different from said first signal level; a first keeper circuit coupled to said signal line at said first location, said first keeper circuit, responsive to said first control signal and to said line signal, configured to maintain said signal line at said second signal level when said first signal driver circuit is not driving said signal line to said first signal level and said second signal driver circuit has driven said line signal to said second signal level; and a second keeper circuit coupled to said signal line at said second location, said second keeper circuit, responsive to said second control signal and said line signal, configured to maintain said signal line at said first signal level when said second signal driver circuit is not driving said signal line to said second signal level and said first signal driver circuit has driven said line signal to said first signal level.