Patent ID: 6838952

Claim:
An amplitude control device for an output signal from an oscillator, the amplitude control device comprising slaving means comprising: rectification means for rectifying the output signal; differential amplification means connected to said rectification means for providing a control signal for controlling an oscillator biasing current; a voltage divider bridge comprising first, second and third resistances connected together in series between a first voltage reference and a second voltage reference, said voltage divider bridge for dividing the first voltage reference into first and second voltage fractions, the first voltage fraction being taken between said first and second resistances, and the second voltage fraction being taken between said second and third resistances; an adder for adding the rectified output signal and the second voltage fraction, and providing a summed signal to a second input of said differential amplification means, said adder comprising a fourth resistance having a first terminal connected to said rectification means, and a second terminal connected to said voltage divider bridge for receiving the second voltage fraction; and a fifth resistance having a first terminal connected to said rectification means, and a second terminal connected to said voltage divider bridge for receiving the second voltage fraction; said rectification means comprising a first bipolar transistor comprising a base connected to the first terminal of said fourth resistance, a collector, and an emitter; and a second bipolar transistor comprising a base connected to the first terminal of said fifth resistance, a collector connected to the collector of said first bipolar transistor, and an emitter connected to the emitter of said first bipolar transistor; and said differential amplification means comprising a first P-type MOS transistor comprising a gate, a source connected to the collectors of said first and second bipolar transistors which forms an output of said differential amplification means, and a drain connected to a biasing voltage, a second P-type MOS transistor comprising a gate connected to the gate of said first P-type MOS transistor, a source connected to the gate of said first P-type MOS transistor, and a drain connected to the drain of said first P-type MOS transistor, a third bipolar transistor comprising a base connected to said voltage divider bridge for receiving the first voltage fraction, a collector connected to the source of said second P-type MOS transistor, and an emitter connected to the emitters of said first and second bipolar transistors, and a sixth resistance having a first terminal connected to the emitters of said first, second and third bipolar transistors, and a second terminal connected to the second voltage reference.