Patent ID: 6907510

Claim:
A method of accessing a configuration data space for a device, the device being connected to a processor through an interconnect, the method comprising: receiving a request from the processor to access the processor's addressable space, the request being generated in response to an instruction intended to access the device's configuration data space; accessing a map between the device's configuration data space and the processor's addressable space, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space, such that only the device's configuration data space is mapped to the one or more pages, the pages having a page size that is a unit for managing at least a portion of the addressable space in the processor; and translating, using the map, the request from the processor into a configuration cycle on the interconnect to access the device's configuration data space, wherein the one or more pages of processor addressable space are in a third address space of the processor, the processor having at least three address spaces, including a memory address space, an input-output address space, and the third address space, and the instruction comprises a third-address-space instruction.