Patent ID: 6970122

Claim:
Apparatus comprising LSB (least significant bit) subword interpolation circuitry that defines, for each input digital word, an offset voltage representative of an M bit LSB subword of the input digital word, the offset voltage modifying a coarse analog representation voltage of an N bit MSB (most significant bit) subword of the input digital word, the LSB subword interpolation circuitry comprising: a coarse analog representative voltage input to receive for each input digital word a corresponding coarse analog representative voltage representative of a level of a corresponding MSB subword; an LSB subword input to receive for each input digital word a corresponding LSB subword; an LSB modification circuit to modify a given LSB subword received via the LSB subword input, to create a given modified LSB subword; an offset voltage defining circuit to receive the given modified LSB subword, and to define, based on the given modified LSB subword, an offset voltage for modifying the corresponding coarse analog representative voltage; and a summation device to add an offset value representative of the offset voltage to a coarse analog value representative of the corresponding coarse analog representative voltage.