Patent ID: 7544623

Claim:
A method for fabricating a contact hole, comprising: providing a semiconductor substrate having thereon a conductive region; depositing a dielectric layer overlying said semiconductor substrate and said conductive region; coating an etching resistive layer on said dielectric layer; coating a silicon-containing layer on said etching resistive layer; coating a photoresist layer on said silicon-containing layer; performing a lithographic process to form a first opening in said photoresist layer, said first opening having an after-development-inspection critical dimension (ADICD); using said photoresist layer as a mask, dry etching said silicon-containing layer through said first opening, thereby forming a shrunk second opening in said silicon-containing layer; and using said silicon-containing layer and said etching resistive layer as etching hard masks, respectively, etching said etching resistive layer and said dielectric layer through said second opening to form a contact hole in said dielectric layer to expose a portion of said conductive region, wherein an after-etch-inspection critical dimension (AEICD) is defined at a bottom of the silicon-containing layer is 40% to 80% of said ADICD.