Patent ID: 7486113

Claim:
A decoder circuit comprising: first and second transistors connected in series between a first reference node and a second reference node; and third and fourth transistors connected in series between a connection node between the first and second transistors and the second reference node, wherein the first transistor is connected between the second reference node and the second transistor and receives a first signal at its gate, the second transistor is connected between the first transistor and the first reference node and receives a second signal corresponding to the first signal at its gate, the third transistor is connected between the second reference node and the fourth transistor and receives a third signal at its gate, the fourth transistor is connected between the third transistor and the connection node and receives a fourth signal corresponding to the third signal at its gate, and the first, second and fourth transistors are of the same conductivity type, and wherein the first transistor is composed of a plurality of transistors connected in series between the second reference node and the second transistor, and the plurality of transistors receive the first signal at their gates.