Patent ID: 7283396

Claim:
A non-volatile memory comprising: a memory matrix including, two voltage source lines; N bitlines, each of the N bitlines of the memory matrix being located between the two voltage source lines, where N is an integer greater than zero; N memory cells respectively attached to the N bitlines of the memory matrix; a reference matrix including, M voltage source lines, where M is an integer greater than two; N bitlines; and N reference cells respectively attached to the N bitlines of the reference matrix, wherein the M voltage source lines are interspersed among the N bitlines of the reference matrix such that there are less than N bitlines of the reference matrix located between corresponding pairs of the M voltage source lines; a decoder to select a first memory cell of the N memory cells in the memory matrix; and a logic generator to activate pre-determined ones of the M voltage source lines so that a reference cell in the reference matrix that corresponds to the first memory cell has a resistance that approximates a resistance associated with the first memory cell.