Patent ID: 7737744

Claim:
A register controlled delay locked loop (DLL) circuit, comprising: a phase comparator configured to compare phases of a source clock and a feedback clock with each other; a clock delay circuit configured to delay a phase of an internal clock synchronized with a clock edge of the source clock in response to an output signal of the phase comparator, wherein the clock delay circuit delays the phase of the internal clock using first delay units for a predetermined delay duration, and thereafter delays the phase of the internal clock using second delay units, each second delay unit providing a delay of longer duration than each first delay unit; and a delay replica model configured to reflect actual delay conditions of the source clock in an output clock of the clock delay circuit to output the feedback clock, wherein the clock delay circuit is configured to perform a normal mode operation of delaying the phase of the internal clock using the first delay units or the second delay units when a phase difference between the source clock and the feedback clock is greater than a predetermined range.