Patent ID: 7719118

Claim:
A semiconductor chip scale package including a plurality of through-vias, which are selectively electrically isolated from or electrically connected with a silicon substrate having said through-vias formed therein, a glass cover being superimposed on said silicon substrate; a dielectric layer being interposed between said glass cover and said silicon substrate; bond pads being arranged within said dielectric layer in electrical connection with contacts on an opposite surface of said silicon substrate, wherein said opposite surface of said silicon substrate includes backside wires extending between said bond pads in said dielectric layer and said contacts so as to provide the electrical connections therebetween; wherein said silicon substrate comprises superimposed doped silicon p−, n+ and n-layers; wherein said n+ layer is interposed between said p− and n− layers so as to ensure an ohmic contact is achieved with the silicon substrate; and wherein said silicon substrate incorporates deep trenches (DT) providing isolation between the p− layer and said contacts.