Patent ID: 7623482

Claim:
A system for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain, wherein said first clock domain is configured to operate with a first clock signal and said second clock domain is configured to operate with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, wherein N/M>1, comprising: a first circuit portion for providing said data blocks including said header block to a second circuit portion; control logic associated with said second circuit portion for processing said header block and generating, in response to said header block, a hint signal that gives advance notification of a possible data transfer operation, said hint signal being configured to be transferred via a synchronizer at least one data cycle prior to the transfer of said data blocks to a third circuit portion; and a control block associated with said third circuit portion, said control block operating responsive to said hint signal to generate data transfer control signals for controlling said third circuit portion in order to control output of said data blocks in a particular ordered grouping, wherein said first circuit portion, said second circuit portion and said control logic are disposed in said first clock domain and said third circuit portion and said control block are disposed in said second clock domain.