Patent ID: 7187727

Claim:
A clock and data recovery circuit comprising: a phase-shifting circuit for supplying phase-shifted clocks to a plural number of latch circuits, receiving an input data in common, for sampling the input data with transition edges of said phase-shifted clocks, said phase-shifted clocks being supplied respectively to said latch circuits from said phase-shifting circuit, for outputting sampled data; a phase detection circuit for producing a detected phase of a transition point of said input data associated with said phase-shifted clocks from outputs of said plural latch circuits and for outputting the detected phase; a filter for smoothing an output of said phase detection circuit; and a decoder for decoding an output of said filter; a circuit for controlling the phase of said phase-shifted clocks based on an output of said filter; said clock and data recovery circuit recovering clocks and data based on the input data; wherein said phase-shifting circuit includes: a switch, receiving a plural number of input clocks having respective different phases, for selecting at least two sets of clock pairs from said input clocks; and a plural number of interpolators, receiving said at least two sets of clock pairs, output from said switch, each interpolator outputting a signal having a delay time which is prescribed by a time corresponding to an interior division of a phase difference of said clock pair; wherein each of said interpolators includes: a charge circuit for turning a charging path and a discharging path of a capacitor on and off depending on logic values of said clock pairs; and a buffer circuit for varying an output logic value when a magnitudes relation between a terminal voltage of said capacitor and a threshold value are inverted; wherein a capacitance value of said capacitor is variably set by a control signal for determining the capacitance value; and output signals of said at least two interpolators are fed as said phase-shifted clocks to said latch circuits; and wherein switching selections of said clock pairs in said switch are controlled based on an output signal of said decoder, and an interior division ratio of said plural interpolators is variably set to control the phase of clocks supplied to said plural latch circuits.