Patent ID: 7813363

Claim:
A network interface of a packet data communication on-chip interconnect system, the network interface comprising: a state controller which monitors a transaction between a slave Intellectual Property (IP) block and at least two master IP blocks connected via a Network on a Chip (NoC) backbone; and a response generation logic unit stored in memory which generates an error response according to control by the state controller, wherein, when a transaction is input from a second master IP block of the at least two master IP blocks while the slave IP block is in a lock operation with a first master IP block of the at least two master IP blocks, the state controller controls discarding of the transaction input from the second master IP block, and the response generation logic unit to generate the error response, and transferring the error response to the second master IP block via the NoC backbone, wherein the second master IP block receives the error response generated by the response generation logic unit and retransfers the transaction input from the second master IP block to the slave IP block when an unlocked transfer is issued from the first master IP block.