Patent ID: 7580319

Claim:
A semiconductor memory device, comprising: a clock buffer configured to generate an internal clock signal based on an external clock signal; a command decoder configured to decode an external command signal to generate a write command signal; and an input latency control circuit configured to generate a column control signal and at least one write address control signal based on the internal clock signal, the write command signal and a write latency signal and configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the column control signal and the at least one write address control signal, wherein the input latency control circuit includes: a master circuit configured to generate the column control signal and the at least one write address control signal based on the internal clock signal, the write command signal and the write latency signal; at least one column slave circuit configured to gate a first address signal in the pipeline mode to generate the column address signal in response to the column control signal and the at least one write address control signal; and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and the at least one write address control signal.