Patent ID: 8735292

Claim:
A semiconductor processing method, comprising: forming a substrate which comprises a monocrystalline silicon-containing semiconductor substrate to comprise an electrically conductive bond pad supporting layer along a front side of the substrate, and to comprise a silicon nitride passivation layer over the bond pad supporting layer; the semiconductor substrate comprising a back side in opposing relation to the front side; the back side having an exposed surface, and the front side having an exposed surface comprising a surface of the silicon nitride passivation layer; utilizing plasma-enhanced atomic layer deposition to simultaneously deposit insulative material across the front side exposed surface and across the back side exposed surface; the plasma-enhanced atomic layer deposition being conducted at a temperature of from at least about 300° C. to less than or equal to about 500° C. to activate hydrogen in the silicon nitride passivation layer during the deposition; etching an opening that extends through the insulative material and through the silicon nitride passivation layer to expose a region of the bond pad supporting layer; and plating conductive material within the opening and directly on the bond pad supporting layer, the conductive material comprising one or more of nickel, palladium and gold.