Patent ID: 6958546

Claim:
A conductive bump overlying a layer of Under Bump Metallization (UBM), comprising: a semiconductor substrate, said semiconductor substrate having been provided with integrated circuitry, at least one layer of passivation over said semiconductor substrate, at least one contact pad in or over said substrate; access to said integrated circuitry for external contact by at least one first via having a first diameter through said at least one layer of passivation, said at least one first via being aligned with said at least one contact pad; at least one layer of negative photoresist over said at least one layer of passivation, further at least one layer of polyimide over said at least one layer of negative photoresist; access to said integrated circuitry for external contact by at least one second via having a second diameter through said at least one layer of polyimide, further through said at least one layer of negative photoresist, said second diameter being smaller than said first diameter, said second via being aligned with said first via; a layer of UBM metal over said at least one layer of polyimide, with a portion of said layer of UBM metal layer extending into said at least one second via and further extending into said at least one first via, contacting said integrated circuitry; and a layer of solder or a compound thereof over said layer of UBM metal, said layer of solder or a compound thereof being aligned with said at least one second via.