Patent ID: 8400443

Claim:
A plasma display device, comprising: a plasma display panel (PDP) including an upper substrate and a lower substrate, a plurality of scan electrodes, a plurality of sustain electrodes, and a plurality of address electrodes provided between the upper and lower substrates; and a driving unit applying a number of driving signals to the scan electrodes and the sustain electrodes, wherein, during a reset period of at least one of a plurality of subfields of a frame, a reset signal is applied to the scan electrodes and a positive bias voltage is applied to the sustain electrodes as a bias voltage signal, the reset period of the one of the plurality of subfields includes: a set-up period during which a level of the reset signal gradually increases to a first voltage, an intermediate period during which the level of the reset signal drops from the first voltage to a second voltage and is then maintained at the second voltage, and a first set-down period during which the level of the reset signal gradually decreases from the second voltage, wherein the bias voltage signal is applied to the sustain electrodes during the intermediate period that follows the set-up period, and wherein a length of an interval between a beginning of the intermediate period and a time when application of the bias voltage signal begins is at least 50% of a length of the intermediate period.