Patent ID: 8035150

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate on which active regions each including a drain region, a source region, and a channel region and having a top surface are formed; shallow trench isolations each formed of a first insulating film which fills a trench formed around a periphery of the active region in the semiconductor substrate, the first insulating film having a top surface, the shallow trench isolation having a portion adjacent to the drain region; gate electrodes each formed on a corresponding one of the channel regions via a gate insulating film; a second insulating film formed all over the surface of the semiconductor substrate; and drain contacts formed in the second insulating film at positions corresponding to the drain regions and electrically connected to the drain regions; wherein the height of the top surface of the first insulating film in a part of the shallow trench isolation which is adjacent to the drain region is equal to that of the top surface of the drain region to which the drain contact is connected, and the height of the top surface of the first insulating film in a part of the shallow trench isolation which is adjacent to the channel region is set greater than the height of the top surface of the first insulating film in the part of the shallow trench isolation which is adjacent to the drain region.