Patent ID: 8736475

Claim:
A finite impulse response digital-to-analog converter (FIRDAC) comprising: a digital data signal input; a series of two or more digital storage elements, the two or more digital storage elements operably connected; the digital data signal input connected to a first of the series of two or more of digital storage elements with each of the two or more of digital storage elements configured to provide delayed copies of the digital data signal input to a next operably connected digital storage element; a series of digital-to-analog (DAC) and AND elements each sequentially paired to a respective one of the two or more of digital storage elements and configured to receive the delayed copies of the digital data signal from a respective paired digital storage element and further configured to receive an alternating state clocking input signal with the state based on position within the series; a passive analog network connected to an output of each of the series of digital-to-analog (DAC) and AND elements; and wherein the output from each one in the series of digital-to-analog (DAC) and AND elements is summed using the passive analog network to produce an output analog signal.