Patent ID: 7283387

Claim:
A phase change memory device, comprising: a memory array comprising a plurality of phase change memory cells, a plurality of bit lines, and a plurality of word lines, wherein each phase change memory cell comprises a phase change element and a diode connected in series between a bit line and a word line; a control node; a plurality of column selection transistors which selectively connect respective bit lines to a data line; and a least one boosting circuit which receives a first voltage and outputs at least one control voltage which is greater than the first voltage; wherein, in a write operation mode, the phase change memory device is adapted to apply at least one control voltage from the at least one boosting circuit to the control node and respective gates of the column selection transistors; and wherein, in a standby mode, the phase change memory device is adapted to maintain the word lines and the bit lines at a same voltage, to apply a ground voltage to the gates of the column selection transistors, and to precharge the control node to the first voltage.