Patent ID: 7745894

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a first wiring layer, a second wiring layer, and a third wiring layer formed above the semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction; a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction; a first selection transistor and a second selection transistor formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer; a first magnetoresistive element which changes a resistance in accordance with a direction of a supplied current, and has one terminal electrically connected to a drain region of the first selection transistor, and an other terminal electrically connected to the first wiring layer; and a second magnetoresistive element which changes a resistance in accordance with a direction of a supplied current, and has one terminal electrically connected to a drain region of the second selection transistor, and an other terminal electrically connected to the third wiring layer.