Patent ID: 7256092

Claim:
A method of fabricating integrated circuits having both high voltage and low voltage devices, wherein a provided substrate contains at least one high-voltage device area and at least one low-voltage device area, and a first pad oxide layer over the substrate, the method comprising: performing a first ion implantation process to form a first ion well of a first conductivity type in the substrate within the high-voltage device area; performing a second ion implantation process to form a second ion well of a second conductivity type in the substrate within the high-voltage device area; stripping the first pad oxide layer; forming a second pad oxide layer; forming a masking layer over the second pad oxide layer; forming a plurality of openings in the masking layer to exposed a portion of the second pad oxide layer; performing a third ion implantation process to implant ions of the first conductivity type into the second ion well within the high-voltage device area, to form a first drift layer; thereafter performing a fourth ion implantation process to implant ions of the first conductivity type into the low-voltage device area, to form a third ion well of the first conductivity type; thereafter performing a fifth ion implantation process to implant ions of the second conductivity type into the low-voltage device area, to form a fourth ion well of the second conductivity type; thereafter performing a sixth ion implantation process to implant ions of the second conductivity type into the first ion well within the high-voltage device area, to form a second drift layer; performing an oxidation process to form a plurality of field oxide isolation structures through the openings in the masking layer; removing the masking layer and the second pad oxide layer; forming a first gate oxide layer over the substrate; performing a seventh ion implantation process to implant ions of the first conductivity type into the first ion well to form a first channel stop region within the high-voltage device area; performing an eighth ion implantation process to implant ions of the second conductivity type into the second ion well to form a second channel stop region within the high-voltage device area; performing a ninth ion implantation process in the fourth ion well within the low-voltage device area to form an anti-punch-through doping region in the fourth ion well; removing the first gate oxide layer within the low-voltage device area; growing a second gate oxide layer within the lowe-voltage device area; and forming a plurality of gate structures on the first and second gate oxide layers.