Patent ID: 7526631

Claim:
A method of enhancing a processor book, having at least two multi-chip modules (MCMs) each having a plurality of processor chips coupled to each other, wherein processor chips of both a first MCM and a second MCM are coupled to each other via intra-chip buses, and each processor chip of said first MCM is coupled to a respective processor chip of said second MCM via an MCM-to-MCM bus, and wherein each processor chip includes an external connector bus (ECB) designed to connect said processor book to components external to said processor book, said method comprising: directly connecting said ECB of each chip of said first MCM to an ECB of a chip of the second MCM to provide a direct transmission path between a source chip of said first MCM and a destination chip of said second MCM; directly connecting said ECB of each chip of said second MCM to an ECB of a chip of the first MCM to provide a direct transmission path between a source chip of said second MCM and a destination chip of said first MCM; wherein said connecting steps are completed according to a pre-set sequence designed to provide a direct path between a source chip of one MCM and a destination chip of another MCM that is a largest number of processor hops away from each other; and wherein further, said connecting steps enable an alternate routing path for data transmission and yields improved transmission latency among processor chips and provides a high percentage memory bandwidth usage.