Patent ID: 8391343

Claim:
A high data rate transceiver, comprising: a first programmable receive PMA module coupled to produce a first serial data; a first clock and data recovery (CDR) coupled to receive the first serial data, the first CDR producing a first recovered clock in a first CDR receive mode of operation and producing a first sample clock in a first CDR sample mode of operation; a second programmable receive PMA module coupled to produce a second serial data; a second CDR coupled to receive the second serial data, the second CDR producing a second recovered clock in the first CDR receive mode of operation and producing a second sample clock in a second CDR sample mode of operation; the first and second CDRs each further including selectable fine loop and coarse loop PLLs, each of the coarse loop PLLs including a coarse phase and frequency detector; and programmable circuit further comprising: mode determination circuit for determining, for each of the first and second CDRs, the CDR receive mode of operation; and mode switching circuit for generating and providing mode switching signals to the first and second CDRs to select which of the selectable fine loop PLL and coarse loop PLL are selectively coupled within each CDR to provide a corresponding receive or sample clock.