Patent ID: 7468909

Claim:
A semiconductor device comprising: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a first power supply; a second selecting circuit that connects or disconnects the source and drain to or from a second power supply; the first selecting circuit and the second selecting circuit being arranged on the opposite sides of the memory cell array; a first storage unit that stores first selecting information that indicates whether the source and drain are to be connected to the first power supply, the first storage unit being connected to the first selecting circuit; a second storage unit that stores second selecting information that indicates whether the source and drain are to be connected to the second power supply, the second storage unit being connected to the second selecting circuit, wherein the first storage unit and the second storage unit are provided on the same sides of the memory cell array as the first selecting circuit and the second selecting circuit, respectively; bit lines that connect the source and drain, the first selecting circuit, and the second selecting circuit; and a control circuit that transfers the first selecting information stored in the first storage unit to the second storage unit via the bit lines, the transferred first selecting information being the second selecting information.