Patent ID: 8803207

Claim:
An apparatus, comprising: a trench disposed in a semiconductor region; a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench; a gate dielectric lining a upper portion of the sidewall of the trench; a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer; an inter-electrode dielectric (IED) disposed in the trench over the shield electrode, the shield electrode having a curved top surface; and a gate electrode disposed in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED, the gate electrode having a first protrusion, a second protrusion, and a third protrusion, the second protrusion of the gate electrode being aligned along a centerline, the gate electrode having a bottom surface defining a first notch disposed on a first side of the centerline between the first protrusion and the second protrusion and a second notch disposed on a second side of the centerline between the second protrusion and the third protrusion.