Patent ID: 7053660

Claim:
An output buffer circuit comprising: first and second output transistors connected in series between a first power supply and a second power supply; first and second control circuits, connected to the first and second output transistors, for receiving an input signal and respectively generating first and second control signals for controlling the first and second output transistors, wherein the first and second output transistors generate an output signal at an output terminal of the output buffer circuit; and a third control circuit, connected between the output terminal and the first and second control circuits, for receiving the input signal and the output signal and controlling a slew rate of the output signal by controlling slew rates of the first and second control signals in accordance with the input signal and the output signal, wherein the third control circuit controls the first and second control circuits when the first and second output transistors are turned off to generate the first and second control signal in accordance with the input signal, and controls the first and second control circuits when the first and second output transistors are turned on such that the first and second control signals sharply rise or fall in response to a change in the input signal, gently rise or fall after a predetermined time elapses, and thereafter sharply rise or fall when the output signal reaches a predetermined level.