Patent ID: 8703001

Claim:
A method for etching at least a first set of wafers and a second set of wafers, the method comprising: providing an electrically negative grid member that is electrically negative relative to a reference; providing an electrically positive grid member that is electrically positive relative to the reference; disposing the electrically negative grid member with respect to the electrically positive grid member such that a first space exists between the electrically negative grid member and the electrically positive grid member; providing an electrically grounded grid member to be the reference; configuring the electrically grounded grid member such that the ground grid member is thicker than at least one of the electrically negative grid member and the electrically positive grid member; disposing the electrically negative grid member between the electrically grounded grid member and the electrically positive grid member; determining a first size for the first space; etching the first set of wafers with the first space configured to have the first size, wherein the electrically negative grid member is maintained apart from the electrically positive grid member by a first plurality of insulating connecting mechanisms defining the first size while etching the first set of wafers with the first space configured to have the first size, at least a subset of the first plurality of insulating connecting mechanisms being disposed throughout an interior region of the electrically negative grid member; determining a second size for the first space; and etching the second set of wafers with the first space configured to have the second size, the first size being larger than the second size, the first set of wafers requiring higher etch uniformity than the second set of wafers, wherein the electrically negative grid member is maintained apart from the electrically positive grid member by a second plurality of insulating connecting mechanisms defining the second size, the second plurality of insulating connecting mechanism substituting for the first plurality of insulating connecting mechanisms while etching the first set of wafers with the first space configured to have the second size, at least a subset of the second plurality of insulating connecting mechanisms being disposed throughout the interior region of the electrically negative grid member, wherein the first space between the electrically negative grid member and the electrically positive grid member is greater in dimension than a second space between the electrically negative grid member and the electrically grounded grid member.