Patent ID: 8244513

Claim:
A simulation execution apparatus comprising: a receiving unit configured to receive a cyclic signal; a plurality of registers; a simulation execution unit configured to execute simulation of a logic circuit model which operates with the use of the cyclic signal and the registers; a counter configured to count time based on the cyclic signal; a register value monitoring unit configured to monitor the values of the registers; a register data recording unit configured to begin recording, in a storage, during the simulation, an entry that includes register data, made up of the values of the registers, in association with the time of the counter when the value of at least one of the registers changes; a cyclicity detection unit configured to check, during the simulation, whether the register data of the entry recorded by the register data recording unit is identical to register data of a previous entry recorded in the storage, during the simulation, and to report a cyclicity of the register data in the storage when an identical entry is found; and a stop unit configured to give a stop instruction signal instructing stop of the simulation to the simulation execution unit when the cyclicity of the register data is reported.