Patent ID: 7169649

Claim:
A wafer scale fabrication process for fabricating three dimensional structures having at least one substantially enclosed cavity on a processed wafer including die elements containing pre-existing MEMS and IC structures thereon, comprising: applying and patterning a first photoresist mask on a first wafer containing at least one die having pre-existing MEMS and IC structures thereon to define boundaries of a first three dimensional structural element component; electrodepositing a structural layer of material into the patterned photoresist mask to define walls of the first three dimensional structural element component; electrodepositing a reflowable bonding layer on top of the structural layer; removing the first photoresist mask; applying and patterning a second photoresist mask on a second sacrificial wafer to define boundaries of a second three dimensional structural element component; electrodepositing a structural layer of material into the patterned second photoresist mask to define a second three dimensional structural element component; removing the second photoresist mask; mounting the first and second wafers on stages of a flip-chip alignment and bonding machine; rotating one of the stages to provide the first and second three dimensional structural element components in a spaced opposed orientation; precisely aligning the first and second three dimensional structural element components relative to each other; relatively moving the first and second wafers towards each other until the first and second three dimensional structural element components are substantially abutted; applying heat to reflow the bonding layer and bond the first three dimensional structural element component to the second three dimensional structural element component; and removing the second sacrificial wafer from the second three dimensional structural element component to form an integrated three dimensional structural element on a MEMS/IC containing die.