Patent ID: 6928598

Claim:
A circuit for protecting the values stored in a BISR repair block in an integrated circuit having a custom test flow, comprising: a plurality of soft latches within the BISR repair block, the soft latches being coupled together to form a BISR scan chain for holding BISR repair information; means for providing a chip level enable scan signal for enabling a scan test, and a scan hold control signal for controlling holding of the repair information in the soft latches of the BISR scan chain, wherein the chip level scan enable signal and the scan hold control signal cooperate to control connection of the BISR scan chain to other scan chains during a scan test, so that the BISR repair information is held within the soft latches and said scan test is any part of said custom test flow employing a BISR circuit; means for providing a BISR scan signal suitable for causing the scan test to be run; means for providing a diagnose enable signal, the diagnose enable signal cooperating with the chip level can enable signal and the scan hold control signal for enabling debugging of logic connecting the BISR scan chains; and means for receiving the chip level scan enable signal, the scan hold control signal, the BISR scan signal and the diagnose enable signal and providing a test enable signal and providing test enable signal determined by the expression TE=BS·DE·CLSE·SHC+DE·CLSE·SHC wherein TE is the test enable signal, BS is the BISR scan signal, DE is the diagnose enable signal, CLSE is the chip level scan enable signal, and SHC is the scan hold control signal.