Patent ID: 8373470

Claim:
A delay device comprising: a plurality of delay elements, each including a delay unit, an element input, an element output, a next element output, and an element return path; wherein the plurality of delay elements is coupled together in a chain between a device input and a device output such that the device input is coupled to the element input of a first delay element in the chain and the device output is coupled to the element output of the first delay element; wherein the next element output of the first delay element is coupled to the element input of a next delay element in the chain, and the element output of the next delay element is coupled to the element return path of a previous delay element in the chain; wherein one or more of the plurality of delay elements includes a NAND-gate configured to pass the input signal received at the element input to the next element output, and one or more remaining ones of the plurality of delay elements includes a NOR-gate configured to pass the input signal received at the element input to the next element output, and wherein the plurality of delay elements are alternatingly coupled together in the chain such that a delay element with a NAND-gate is coupled to a delay element with a NOR-gate; and a decoder unit configured to provide a respective selection control signal to each of the plurality of delay elements based upon a received delay control signal; wherein in response to the respective selection control signal each delay element is configured to selectively route a signal from the element input to one of the next element output or to the element output.