Patent ID: 8063445

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first conductivity type well region disposed on the semiconductor substrate; a second conductivity type high concentration source region and a second conductivity type high concentration drain region each disposed on a surface of the first conductivity type well region so as to be spaced from each other with a channel formation region interposing therebetween, the second conductivity type high concentration source region and the second conductivity type high concentration drain region each having a conductivity type opposite to a conductivity type of the first conductivity type well region, and having an impurity concentration higher than an impurity concentration of the first conductivity type well region; a second conductivity type low concentration drain region disposed to surround the second conductivity type high concentration drain region and to be brought into contact with the channel formation region; a second conductivity type high concentration source field region disposed between the second conductivity type high concentration source region and the channel formation region so as to be brought into contact with the second conductivity type high concentration source region and the channel formation region; a field oxide film and a source field oxide film disposed over a surface of the semiconductor substrate in regions excluding the second conductivity type high concentration source region, the second conductivity type high concentration drain region, and the channel formation region; a gate oxide film disposed over the surface of the semiconductor substrate, and located on the channel formation region so as to partially overlap with the field oxide film and the source field oxide film formed on both sides of the channel formation region; a polycrystalline silicon gate electrode disposed on both the gate oxide film and side-etched portions located at both ends of the gate oxide film; a protective oxide film disposed to cover structural components formed on the semiconductor substrate; a source electrode which is formed so as to be brought into contact with the second conductivity type high concentration source region; and a drain electrode which is formed so as to be brought into contact with the second conductivity type high concentration drain region, wherein the second conductivity type high concentration source field region has a length in parallel to a channel direction being equal to or larger than a sum of twice a mask alignment offset amount of the polycrystalline silicon gate electrode and the source field oxide film and twice a film thickness of the gate oxide film.