Patent ID: 7861192

Claim:
A system comprising: a register array, wherein the register array comprises a plurality of one bit storage element cells; clock enabling circuitry; and clock generation circuitry, wherein the clock generation circuitry is configured to provide a clock signal from a last ungated stage; wherein the clock enabling circuitry is configured to: receive the clock signal from the last ungated stage; receive a common clock enable signal corresponding to the plurality of one bit storage element cells; and provide a gated clock signal to the plurality of one bit storage element cells, in response to detecting the common clock enable signal is asserted; wherein each of the storage element cells is coupled to receive the gated clock signal, a unique enable signal, and a data input signal, and wherein each cell of said cells comprises: a storage element configured to store a current state of the cell; and a multiplexer configured to: receive as input the data input signal and a current value of the cell; and receive as a select signal the unique enable signal, wherein the unique enable signal selects either the data input signal or the current value of the cell for output; and convey as output a next state for said storage element.