Patent ID: 8134870

Claim:
A memory array comprising: a plurality of word lines; a plurality of bit-lines; and a plurality of memory cells configured to represent data values, each memory cell comprising a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal, wherein connections associated with the drain and source terminals of a particular memory cell determine a data value stored within the memory cell, and wherein memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values such that a first memory cell in the plurality of memory cells including a first drain terminal coupled to a first bit-line and a first source terminal coupled to the first bit-line represents a one value, and a second memory cell in the plurality of memory cells including a second drain terminal coupled to the first bit-line and a second source terminal coupled to a second bit-line represent a zero value.