Patent ID: 8446781

Claim:
A system, comprising: a memory controller configured to address a number of ranks of memory, the number of ranks being greater than one, each rank having a memory controller rank width; a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having a first number of data signals; and a plurality of memory modules, wherein each memory module is coupled to the memory controller through the memory bus, each memory module has the same number of ranks of memory as the memory controller is configured to address, each rank on each memory module having a module rank width that is less than the memory controller rank width, each memory module has a number of data pins coupled to the data bus that is equal to the module rank width, the data pins of the plurality of memory modules each being coupled to a different one of the data signals of the data bus, and a sum of the module rank widths of the plurality of memory modules is equal to the memory controller rank width.