Patent ID: 7415089

Claim:
A system comprising: a clock for generating a clock signal at half a rate of transmitted serial data from a signal source; a half-rate phase detector coupled to the clock and the signal source for oversampling the transmitted serial data and providing sampled data, and for detecting and grouping phase transitions between a phase lead and a phase lag in the sampled data and outputting phase transition data; a phase selector; an encoder, coupled to the half-rate phase detector, for encoding the phase transition data according to an optimum phase selected by the phase selector; and a confidence counter coupled to the encoder to receive the encoded phase transition data and provide an output representative of an accumulated effect of the phase transitions based on the encoded phase transition data, wherein the phase selector is coupled to receive the clock signal and the output from the confidence counter to select the optimum phase effective for recovering the clock relative to the transmitted serial data, and the phase detector provides to the encoder one set of oversampled data while oversampling at transition phases of the transmitted serial data and provides to the encoder two sets of oversampled data while oversampling at non-transition phases of the transmitted serial data.