Patent ID: 8229991

Claim:
A processor core to execute an instruction to perform a multiply and subtract operation, comprising: a decoder to decode the instruction and detect an operation code, a first operand, and a second operand, the first and second operands each having a first value and a second value; a plurality of general purpose registers (GPRs) including a first GPR to store the first operand and a second GPR to store the second operand; and an execution unit, coupled to the general purpose registers and an accumulation register, that includes: a partial product generator that generates a plurality of first partial products and a plurality of second partial products using the first and second operands, wherein each first partial product is a negated Booth recoded partial product based on the first value of the first operand and the first value of the second operand, and wherein each second partial product is a second Booth recoded partial product based on the second value of the first operand and the second value of the second operand, wherein the plurality of first partial products has higher bit significance than the plurality of second partial products; a plurality of first adders, coupled to the partial product generator, that generates a first result for the plurality of first partial products; a plurality of second adders, coupled to the partial product generator, that generates a second result for the plurality of second partial products; and a combiner, coupled to the first adders and the second adders, that generates a final result based on the first result, and the second result if the first operand and the second operand represent single values, the partial product generator assigns a value of zero to either a most significant partial product of the plurality of second partial products or to a least significant partial product of the plurality of first partial products, wherein the combiner further comprises: a saturation unit, coupled to a shift unit, wherein if the first value of the first operand and the first value of the second operand each equal negative one, the saturation unit replaces the first result with a saturation result; and if the second value of the first operand and the second value of the second operand each equal negative one, the saturation unit replaces the second result with the saturation result.