Patent ID: 8233620

Claim:
A cryptographic system, comprising: a register containing key data for a key; an input/output data block containing data for encryption; a processor coupled to the register and the input/output data block, operable for: receiving the data from the input/output data block, the data comprising a first sub-block of a block of data, wherein the number of bits in the first sub-block of data is less than or equal to the total number of bits in the block of data; performing a first encrypting operation on the first sub-block of data, the encrypting operation including computing a key schedule using the register as a workspace, wherein the computing overwrites the key data for the key resulting in the register containing data other than the key data for the key; at the end of the first encrypting operation on the first sub-block of data: computing an inverse key schedule for the key schedule used in the first encrypting operation to recover the key data for the key; and restoring the recovered key data for the key to the register, wherein the restoring overwrites the data other than the key data for the key in the register; receiving, from the input/output data block, data comprising a second sub-block of the block of data, wherein the number of bits in the second sub-block of data is equal to the number of bits in the first sub-block of data; and performing a second encrypting operation on the second sub-block of data using the recovered key data for the key.