Patent ID: 7831790

Claim:
A memory device comprising: an interface for receiving access requests, the interface having an address output to an address path and a data output to a data path, wherein address information is carried on the address path and data for writing to memory or data read from memory is carried on the data path; a memory cell array having a plurality of low-latency, rewritable, non-volatile memory cells forming at least one memory section; a word-select unit connected in the data path and to the address path and between the interface and the memory cell array to provide column selection; a section-select unit connected to the address path and between the interface and the memory cell array to provide row selection; wherein both the word-select unit and the section-select unit select a respective column and row of the memory cell array in response to the address information; a profile storage unit connected to said interface comprising a plurality of request profiles that each represent a profile of an access request, wherein each request profile includes: a set of request information elements, wherein at least one of the request information elements indicates whether an access request is a read request or a write request; and access flags, whose state indicates whether a corresponding access request is allowed to access the memory or not allowed to access the memory, the access flags comprising write protect flags and read protect flags; an access control unit connected to said profile storage unit and said memory and configured to allow or reject an access request; wherein said profile storage unit selects an access flag that corresponds to a request profile in response to an access request that fits the request profile; and wherein the access control unit allows or rejects an access request in response to the access flag that is selected by the profile storage unit and wherein a write request that violates a write access flag is ignored and a read request that violates a read access flag results in a fixed answer and wherein a violation triggers an interrupt pin on the interface.