Patent ID: 7504271

Claim:
A method of constructing at least a portion of an integrated circuit package, comprising: forming a base structure, of a green material, having a plurality of via openings therein; sintering the green material so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings; forming a low k-value dielectric material on the sintered ceramic base structure and having a plurality of openings therein; forming a conductive via in each via opening of the sintered ceramic base structure, the conductive vias including at least power, ground vias, and signal vias, each signal via extending through a respective opening in the low k-value dielectric material; and forming a capacitor structure on the sintered ceramic base structure next to the low k-value dielectric material, the capacitor structure including conductive power and ground planes and a high k-value dielectric layer between the power and ground planes, the power and ground planes being electrically connected to at least one of the power vias and one of the ground vias, respectively.