Patent ID: 7945827

Claim:
A multichip module, comprising: a silicon interposer having logic, said logic configured to (i) receive one or more external test signals and one or more output signals from each die of a plurality of dies, (ii) select a test input signal for said each die from said one or more external test signals and said one or more output signals of another die of said plurality of dies, and (iii) transmit one or more test result signals from any one of said plurality of dies for external communication; a first die of said plurality of dies, operatively connected to said silicon interposer and a second die of said plurality of dies, said first die having a first plurality of input/output (I/O) terminals configured to communicate with said logic, and having test circuitry for testing said first die with at least a first one of said test input signals; said second die operatively connected to said silicon interposer and said first die, said second die having a second plurality of input/output (I/O) terminals configured to communicate with said logic, and having test circuitry for testing said second die with at least a second one of said test input signals; and a package, said package (i) housing each of said first die and said second die and (ii) covering said silicon interposer; wherein said logic comprises a plurality of multiplexers, wherein at least a first subset of said multiplexers receive (i) at least one of said one or more output signals from a first subset of said first plurality of I/O terminals and (ii) at least one first external input signal; a second subset of said multiplexers receive (i) at least one of said one or more output signals from a first subset of said second plurality of I/O terminals and (ii) at least one second external input signal; and a third subset of said multiplexers receive at least a first one of said one or more test result signals from a second subset of said first plurality of I/O terminals and at least a second one of said one or more test result signals from a second subset of said second plurality of I/O terminals.