Patent ID: 7183831

Claim:
A clock switching circuit for receiving two clock signals and selectively outputting one of said two clock signals in accordance with a selection signal, the circuit comprising: a switching controller which receives said selection signal and said two clock signals, and transfers said selection signal at the beginning of a period in which both of said two clock signals are active; an internal selector which receives said two clock signals, and selectively outputs one of said two clock signals in response to said selection signal being transferred from said switching controller, and a latch circuit which transfers said selection signal in response to a tripper signal, wherein said internal selector has a positive logical control terminal and a negative logical control terminal, and wherein said latch circuit comprises: a first flip-flop circuit which transfers said selection signal and outputs a negative selection signal at a rising edge of said trigger signal; a second flip-flop circuit which transfers said selection signal from said first flip-flop circuit to said positive logical control terminal at a falling edge of said trigger signal; and a third flip-flop circuit which transfers said negative selection signal from said first flip-flop circuit to said negative logical control terminal at a falling edge of said trigger signal.