Patent ID: 7450659

Claim:
An upconverting circuit comprising: a clock for defining a sequence of input polyphase cycles; a polyphase component generator that provides 2N p polyphase components from an input signal having an in-phase and a quadrature signal at each input polyphase cycle, wherein N p >2, there being N p polyphase components corresponding said in-phase signal and N p polyphase components corresponding to said quadrature signal; a memory that stores said polyphase components from at least one polyphase cycle prior to the current polyphase cycle; a plurality of filters, each filter processing a plurality of said polyphase components stored in said memory to generate a filtered polyphase component corresponding to that filter, wherein in any given input polyphase cycle, at least one of said filters processes a plurality of different polyphase components stored in said memory from a corresponding polyphase cycle; and a multiplexer that outputs said filtered polyphase components in a predetermined order to generate a filtered output signal comprising an upconverted version of said input signal.