Patent ID: 7349992

Claim:
A system for enabling communication between a first network having a first network protocol and a second network having a second network protocol, the second network being a storage area network, said system comprising: a first data port for receiving first input data and first state information from said first network, said first input data being expressed in said first network protocol; a second data port for receiving second input data and second state information from said second network, said second input data being expressed in said second network protocol; a first microsequencer system configured to translate said second input data into corresponding data expressed in said first network protocol on the basis of said first state information, the first microsequencer system including one or more microsequencers configured to cooperate in translating said second input data into corresponding data expressed in said first network protocol; a second microsequencer system configured to translate said first input data into corresponding data expressed in said second network protocol on the basis of said second state information, the second microsequencer system including one or more microsequencers configured to cooperate in translating said first input data into corresponding data expressed in said second network protocol; and an instruction memory accessible to each of the microsequencers of the first and second microsequencer systems, said instruction memory having a plurality of instruction words, each of said instruction words forming a Very Long Instruction Word (VLTW) having a plurality of instruction fields executable in parallel by different functional units of each of the microsequencers to enable the microsequencers to execute a plurality of instructions in a single instruction cycle, the instruction memory being loadable via a processor interface to make the microsequencers programmable to accommodate different first and second network protocols.