Patent ID: 8856496

Claim:
A microprocessor configured to receive first and second program-adjacent macroinstructions of the instruction set architecture of the microprocessor, wherein the first macroinstruction instructs the microprocessor to load an operand from a location in memory into the microprocessor, to perform an arithmetic/logic operation using the loaded operand to generate a result, to store the result back to the memory location, and to update condition codes of the microprocessor based on the result, wherein the second macroinstruction instructs the microprocessor to jump to a target address if the updated condition codes satisfy a condition specified by the second macroinstruction and to otherwise execute the next sequential instruction, the microprocessor comprising: hardware execution units; and an instruction translator, configured to simultaneously translate the first and second program-adjacent macroinstructions into first, second, and third micro-operations for execution by the hardware execution units; wherein the first micro-operation instructs the hardware execution units to calculate the memory location address and to load the operand from the memory location address into the microprocessor; wherein the second micro-operation instructs the hardware execution units to perform the arithmetic/logic operation using the loaded operand to generate the result, to update the condition codes based on the result, and to jump to the target address if the updated condition codes satisfy the condition and to otherwise execute the next sequential instruction; wherein the third micro-operation instructs the hardware execution units to store the result to the memory location; wherein if one or more of the first, second, and third micro-operations causes an exception condition, the microprocessor is configured to cause the instruction translator to re-translate the first and second program-adjacent macroinstructions into more than three micro-operations and to cause the hardware execution units to execute the more than three micro-operations; wherein a first of the more than three micro-operations instructs the hardware execution units to perform the arithmetic/logic operation using the loaded operand to generate the result and updates the condition codes based on the result; and wherein a second of the more than three micro-operations instructs the hardware execution units to jump to the target address if the update condition codes satisfy the condition and to otherwise execute the next sequential instruction.