Patent ID: 8213257

Claim:
A Random Access Memory (RAM), comprising: a plurality of rows, each of the rows comprising a plurality of cells and a corresponding word-line; each cell comprising a latch for storing data, and at least a pass-gate transistor coupled between the latch, the corresponding word-line and a corresponding bit-line; a plurality of word-line drivers, each of the word-line driver comprising a power node receiving an operation voltage, a driving node coupled to one of the word-lines of the rows, an input node receiving a decoding signal, and a driving transistor comprising a control node and two channel terminal nodes respectively coupled to the input node, the driving node, and the power node; at least a first tracking transistor, corresponding to one of the word-line driver, comprising two channel terminal nodes with one of the two channel terminal nodes coupled to one of the driving node, and the other channel terminal node coupled to one of the two channel terminal nodes of a second tracking transistors; the first tracking transistor having electronic characteristics tracking those of the pull-up driving transistor of the corresponding word-line driver; and at least a second tracking transistor comprising two channel terminal nodes with one of the two channel terminal nodes coupled to one of the two channel terminal nodes of the first tracking transistor, the second tracking transistor having electronic characteristics tracking those of the pass-gate transistors of the cells.