Patent ID: 8860738

Claim:
An image processing circuit comprising: a data adjustment circuit configured for sequentially outputting (X×Y) (X and Y are natural numbers) pieces of pixel data corresponding to respective pixels in X rows and Y columns as output data from pixel data corresponding to pixels in a first row to pixel data corresponding to pixels in each row and outputting (K−Y) (K is a natural number greater than Y) pieces of dummy data every time the pixel data corresponding to the pixels in one row is output; a first line memory capable of storing K pieces of data and configured to store Y pieces of pixel data and (K−Y) pieces of dummy data input from the data adjustment circuit according to an input order for a certain period of time and to output the pieces of pixel data and the pieces of dummy data in the input order; a second line memory capable of storing K pieces of data and configured to store Y pieces of pixel data and (K−Y) pieces of dummy data input from the first line memory according to the input order for a certain period of time and to output the pieces of pixel data and the pieces of dummy data in the input order; an output timing control circuit; and an arithmetic circuit configured for storing the (X×Y) pieces of pixel data input from the first line memory and the second line memory through the output timing control circuit for a certain period of time and performing a filter process by using the stored (X×Y) pieces of pixel data, wherein the data adjustment circuit is configured to output the pieces of dummy data and the pieces of pixel data so that each of the first line memory and the second line memory store (K−Y) pieces of dummy data adjacent to each other and Y pieces of pixel data adjacent to each other.