Patent ID: 8455366

Claim:
A process for forming a semiconductor structure comprising: forming a plurality of gate lines on a surface of a semiconductor substrate, wherein each gate line of said plurality of gate lines includes at least a high k gate dielectric and an overlying metal gate; forming an organic planarizing layer (OPL) atop the semiconductor substrate and the plurality of gate lines; forming a patterned photoresist including at least one pattern atop the OPL, said at least one pattern is located atop a portion of each gate line of the plurality of gate lines; transferring the at least one pattern into the underlying OPL and gate line by etching; and removing the patterned photoresist and remaining OPL layer by a sequence of contacting steps comprising (a) first contacting with sulfuric acid, (b) second contacting with an aqueous solution comprising a cerium (IV) containing complex or salt and at least one ammonium salt or complex, and (c) third contacting with sulfuric acid.