Patent ID: 7827392

Claim:
A method of predicting branch instructions in a processor, comprising: storing in a Branch Target Address Cache (BTAC) a BTAC entry, the BTAC entry associated with a block of two or more instructions stored in one or more lines in an instruction cache (1-cache), only if the block includes at least one branch instruction having been evaluated taken, the BTAC entry having a tag field comprising a full instruction address of a first instruction in the block which begins at any full instruction address within an I-cache line; and upon fetching a group of instructions, accessing the BTAC to determine if an instruction in a corresponding block of instructions is a taken branch instruction; wherein each BTAC entry includes an indicator of which instruction within the corresponding block is a taken instruction; and wherein a first BTAC entry is associated with a first instruction block including first and second taken branch instructions, the first BTAC entry storing a branch target address (BTA) of the first taken branch instruction and a second BTAC entry associated with a second instruction block including the second taken branch instruction stores a BTA of the second taken branch instruction.