Patent ID: 7627698

Claim:
A method of transferring data from a producer task to a consumer task using a DMA controller having a system transfer unit coupled to a direct memory access (DMA) bus master device and having a core transfer unit coupled to instruction memory and data memory of a core processor complex, the method comprising: configuring the DMA controller to restart the system transfer unit when the system transfer unit is idle during a sequence of multiple data block transfers and a first semaphore register is non-zero; transferring data blocks of a first size from the producer task to a buffer in the DMA controller; updating the first semaphore register at the end of transfer of each of the data blocks of the first size has been flushed to the consumer task and an operational state of the system transfer unit to idle; and restarting the system transfer unit when the system transfer unit is idle during the sequence of multiple data block transfers and the first semaphore register is non-zero.