Patent ID: 8487706

Claim:
A power amplifier circuit comprising: a first field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to a gate electrode of the first field effect transistor and ii) a first DC control voltage input is adapted to be coupled to the gate electrode of the first field effect transistor; one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate electrodes of the one or more additional field effect transistors, an output of the power amplifier circuit being taken on a drain electrode of the last one of the one or more additional field effect transistors; and one or more capacitors, each coupled to a respective one of the one or more additional field effect transistors, wherein the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors are selected to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier circuit whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id.