Patent ID: 8035213

Claim:
A chip package structure, comprising: a first package portion, comprising: a first distribution layer having a first surface and a second surface; a chip disposed on the first surface of the first distribution layer; a plurality of internal conductors having a first terminal and a second terminal, wherein the first terminal is disposed on the first surface of the first distribution layer; and a sealant disposed on the first surface of the first distribution layer for covering the chip and partly encapsulating the plurality of internal conductors, so that the first terminal and the second terminal of each of the plurality of internal conductors are exposed from the sealant, wherein the first terminal of each of the plurality of internal conductors is projected from the sealant, and the first distribution layer contacts the first terminal of each of the plurality of internal conductors; and a plurality of first external conductors disposed on the second surface of the first distribution layer of the first package portion and electrically connected to the plurality of internal conductors, wherein the first distribution layer electrically connects the first terminal of each of the plurality of internal conductors to at least one of the plurality of first external conductors.