Patent ID: 8335750

Claim:
An apparatus comprising: a computer; a first hash entry held in the computer, wherein the first hash entry includes K bits; a memory in the computer that has an address space with a first plurality of addressable locations, wherein N of the first plurality of addressable locations in the memory hold input-data sample values of a first input pattern, wherein N is a count of the N addressable locations that have the input-data sample values from the first input pattern, and wherein each of M addressable locations of the first plurality of addressable locations holds an index value of a first state array, wherein each index value of the first state array represents an index in a range of 0 to N−1; an addressing unit that generates a first path having a first series of addresses through the first state array, wherein each successive one of the first series of addresses is based on a value from the first input pattern that is selected based on one of the index values obtained from the first state array; a first sensor unit operatively coupled to receive a path of addresses from the addressing unit, and operative to individually determine each bit of a plurality of bits based on the path of addresses, wherein the plurality of bits from the first sensor unit form at least a part of a first recognition address; and a first recognition unit operatively coupled to receive the first recognition address from the first sensor unit and configured to output an indication of a first recognized pattern in the first input pattern based on the received first recognition address.