Patent ID: 7539473

Claim:
In a phase lock loop (PLL) circuit device which includes a voltage controlled oscillator (VCO), a method to reduce overshoot during calibration of the PLL circuit device, comprising: determining when calibration of the PLL circuit device is initiated, including setting a present frequency band for the PLL circuit device to a base frequency band which is a lowest frequency band among a plurality of sequentially higher frequency bands to be used with the PLL circuit device; setting to a minimum size a smallest selection window used to determine a least amount of a differential control voltage offset from a pre-established center point reference voltage for each of the plurality of sequentially higher frequency bands to provide VCO calibration of the PLL device; centering present frequency of the VCO to the pre-established center point reference voltage prior to stepping the present frequency band to a next higher frequency band of the plurality of sequentially higher frequency bands by shorting a differential loop filter of the PLL circuit device having positive and negative branches, such that the differential loop filter is coupled to differential inputs of the VCO, by applying a high voltage input to a gate of a filter reset transistor having a source and a drain respectively coupled to either of the differential inputs of the VCO and to respective ones of the positive and negative branches of the differential loop filter; pausing, after the shorting of the differential loop filter for a preset time period, to allow the present VCO frequency to return to the pre-established center point reference voltage; sampling, after the pausing for the preset time period, the differential voltage control offset for the PLL circuit device for the present frequency band and determining whether the sampled differential voltage control offset is within the smallest selection window; stepping up the present frequency band to a next higher frequency band of the plurality of sequentially higher frequency bands in response to a determination that the sampled differential voltage control offset for the present frequency band is not within the smallest selection window, and in response to a determination that the present frequency band has not been stepped up to a maximum frequency band of the plurality of sequentially higher frequency bands; and incrementing the size of the smallest selection window by a predetermined amount if a present size of the smallest selection window is less than a preset maximum size for the smallest selection window; wherein calibration of the PLL circuit device is completed when it is determined that the sampled differential voltage control offset for the present frequency band is within the smallest selection window for the present frequency band.