Patent ID: 8301928

Claim:
A power controller in a shared memory multiprocessor system comprising: a memory bank base address register for each independently powerable memory bank storing a base address of a corresponding memory bank; a comparator for each independently powerable memory bank having a first input connected to said memory bank base address register for a corresponding memory bank, a second input receiving a processor access request memory address and an output generating a match signal if said processor access request memory address falls within an address range of said corresponding memory bank; and a memory bank power controller for each independently powerable memory bank powering a memory bank upon a match signal from a corresponding comparator, said memory bank power controller including a power bit having a first digital state when said memory bank power controller powers said corresponding memory bank and a second digital state when said memory bank power controller does not power said corresponding memory bank, an AND gate having a first inverting input connected to said power bit, a second non-inverting input receiving said match signal and an output, and said memory bank power controller signaling power up of said corresponding memory bank upon a predetermined digital output of said AND gate.