Patent ID: 8605477

Claim:
A semiconductor memory device comprising a first wiring, a second wiring, a third wiring, a fourth wiring, and a memory unit including a first memory cell and a second memory cell, which are arranged in a matrix, wherein the first wiring is parallel to the second wiring, wherein the third wiring is parallel to the fourth wiring, wherein the first wiring is orthogonal to the third wiring, wherein the first memory cell includes a first transistor, a second transistor, and a first capacitor, wherein the second memory cell includes a third transistor, a fourth transistor, and a second capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor, wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor, wherein a gate of the first transistor and the other electrode of the second capacitor are connected to the first wiring, wherein a gate of the third transistor and the other electrode of the first capacitor are connected to the second wiring, wherein a source of the first transistor, a source of the second transistor, and a drain of the fourth transistor are connected to the third wiring, and wherein a source of the third transistor, a source of the fourth transistor, and a drain of the second transistor are connected to the fourth wiring.