Patent ID: 7522440

Claim:
A memory devices, comprising: a memory cell array; a control signal generator circuit adapted to receive at least two internal clock signals and adapted to generate p control signals (where p is an integer≧3 and where p=2 n +k), where 2 n is a number of data bits (where n is an integer≧1) and k is a number of data bits (where k is an integer, k is≧1, and k is<2 n ), all of the p control signals being generated sequentially during one clock cycle of an external clock signal; at least one serial-to-parallel converter, adapted to receive a serial bit stream of m bits (where m is an integer≧3) sequentially, and adapted to convert the serial bit stream of m bits into a parallel m-bit stream in response to each of the p control signals, all bits of the parallel m-bit stream being output during one clock cycle of the external clock signal, wherein at least the 2 n data bits can be written to the memory cell array; and at least one parallel-to-serial converter, adapted to receive at least a parallel 2 n -bit stream read from the memory cell array and adapted to convert the parallel 2 n -bit stream into a serial bit stream in response to each of 2 n control signals, all bits of the serial bit stream being output during one clock cycle of the external clock signal, wherein at least the 2 n data bits can be read from the memory cell array.