Patent ID: 7757106

Claim:
A sequence circuit for making a sleep control signal output from a sleep control signal terminal of a chipset consistent with a first sleep signal and a second sleep signal output from a first sleep signal terminal and a second sleep signal terminal of a super I/O chip of a computer for controlling the sleep states of the computer, comprising: a switch circuit having an input terminal connected with a node and an output terminal connected to the first sleep signal terminal of the super I/O chip; and a control circuit comprising a first transistor and a second transistor, the first transistor having a gate connected to the node and a drain connected to the sleep control signal terminal of the chipset, the second transistor having a base connected to the drain of the first transistor and a collector connected to the second sleep signal terminal of the super I/O chip; wherein when the computer is off or in one of the sleep states, the node is at low level and the output terminal of the switch circuit outputs a low level signal; when the computer is on, the node is at high level and the output terminal of the switch circuit outputs a high level signal.