Patent ID: 7941567

Claim:
A modular computer system formed by connecting a processing module having a processor mounted thereon and a plurality of I/O modules in a stacked form via connectors, where differing ones of the plurality of I/O modules being differing types of I/O modules from one another, which operate with mutually differing types of bus-layout configurations, and where at least a portion of said connectors representing a reconfigurable generic bus, wherein each I/O module comprises: an I/O module connector representing one of the connectors; a module exclusive selection part for activating the module responsive to a module select signal input from a terminal in a predetermined position on a processing module side connector, the predetermined position being the same for said I/O modules; and an ID output part for outputting identification information of its own I/O module to at least one predetermined terminal on the I/O module connector on the basis of the module select signal output from said module exclusive selection part; wherein said processing module comprises: a module select signal output part for outputting the module select signal to a connector terminal to which the I/O module is connected; and an ID input part for taking in the identification information output to the at least one predetermined terminal on the I/O module connector, where said module select signal output part outputs the module select signal successively to the I/O modules connected to the processing module, and said ID input part recognizes the I/O modules and the identification information in association with an output order of the module select signal; and wherein in accordance with the association of the I/O modules with the identification information, for each differing type of I/O module stacked via the connectors, said processing modules reads out bus protocol, set up/hold duration timing of address-data-control signal, bus control parameter of bus width and device driver of the I/O module out of memory set in the predetermined position on a processing module side connector for accessing the differing type of I/O module.