Patent ID: 8604554

Claim:
A semiconductor device comprising: a first MIS transistor; and a second MIS transistor, wherein the first MIS transistor includes a first gate insulating film formed on a first active region in a semiconductor substrate, a first gate electrode formed on the first gate insulating film, a first silicide layer formed on the first gate electrode, first sidewalls each including a first inner sidewall formed on a side surface of the first gate electrode and having an L-shaped cross-section, and first source/drain regions of a first conductivity type formed in the first active region laterally outside the first sidewalls, the second MIS transistor includes a second gate insulating film formed on a second active region in the semiconductor substrate, a second gate electrode formed on the second gate insulating film, a second silicide layer formed on the second gate electrode, second sidewalls each including a second inner sidewall formed on a side surface of the second gate electrode and having an L-shaped cross-section, and second source/drain regions of a second conductivity type formed in the second active region laterally outside the second sidewalls, the first source/drain regions include a silicon compound layer which is formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region, and a width of the first inner sidewall is smaller than a width of the second inner sidewall.