Patent ID: 7339982

Claim:
A modular, jitter-tolerant, data acquisition and processing system, comprising: a receiving portion having: a first module configured to receive a serial bit stream and recover a serial data stream and a first clocking signal from the serial bit stream; a second module configured to receive the serial data stream and the first clocking signal and generate a parallel data stream and a second clocking signal; a third module configured to receive the parallel data stream and the second clocking signal, wherein the third module comprises a character synchronization sub-module, a decoding sub-module, a protocol handling sub-module, and a formatting sub-module; and a transmitting portion having: the third module further configured to receive a second parallel data stream from an analyzer, wherein the third module is further configured with an encoder sub-module to encode the received second parallel data stream; a divide by N module to derive a third clocking signal from the first clocking signal; and a fourth module configured to convert the encoded parallel data stream to a second serial data stream.