Patent ID: 8117468

Claim:
A computer comprising: a battery; and a superscalar microprocessor powered by the battery, the superscalar microprocessor comprising: an instruction decoding unit configured to decode machine code instructions; an instruction execution unit coupled to the instruction decoding unit and configured to execute, out-of-order, the machine code instructions, the instruction execution unit including a plurality of functional units configured to perform operations in conjunction with the execution of the machine code instructions; and a logic unit coupled to the functional units and configured to identify, in response to evaluating information based on one of the machine code instructions, one of the functional units as being required to operate in conjunction with execution of the one of the machine code instructions, wherein the logic unit is further configured to selectively control activation of the identified one of the functional units based at least in part on the evaluating information such that consumption of battery power by the identified one of the functional units is reduced.