Patent ID: 8354716

Claim:
A semiconductor device for use in a relatively high voltage application, the semiconductor device comprising: a substrate; a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device; a pair of second n-type well regions in the first n-type well region; a first p-type region in the first n-type well region between the second n-type well regions; a pair of conductive regions on the substrate between the second n-type well regions; and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region, dispersed in the substrate, and uniformly distributed in the substrate under the first n-type well region, and wherein the NBLs includes first NBLs located under the p-type region and second NBLs located under a region between the p-type region and each of the second n-type well regions, the first NBLs are distributed at a first density and the second NBLs are distributed at a second density, the first density being greater than the second density.