Patent ID: 7339408

Claim:
A circuit for receiving a reference clock signal and outputting clock signals having different phases corresponding to said reference clock signal, said circuit comprising: a plurality of serially-coupled delay units comprising a first delay unit operative to receive said reference clock signal, said plurality of serially-coupled delay units operative to output a plurality of clock signals phase-shifted differently relative to said reference clock signal, wherein each of said plurality of serially-coupled delay units comprise two parallel delay lines and at least one phase mixer, and wherein each of said plurality of serially-coupled delay units comprises at least three phase mixers; a phase detector operative to output a signal indicating a phase difference between said reference clock signal and one of said plurality of clock signals output by said plurality of serially-coupled delay units; and logic circuitry operative to control a phase shift of said plurality of serially-coupled delay units based on said output of said phase detector.