Patent ID: 7732310

Claim:
A method of forming a semiconductor structure, the method comprising: providing a semiconductor substrate; and forming a memory cell at a surface of the semiconductor substrate comprising: forming a gate dielectric on the semiconductor substrate; forming a control gate on the gate dielectric; forming a first and a second tunneling layer on a source side and a drain side of memory cell, respectively, wherein the first and the second tunneling layers each comprise a vertical portion on sidewalls of the gate dielectric and the control gate, and a horizontal portion on a top surface of the semiconductor substrate; tilt implanting a lightly doped source region underlying the first tunneling layer, wherein the tilt implanting tilts only from the source side to the drain side, and wherein a portion of the semiconductor substrate under the second tunneling layer is free from the tilt implanting; forming a storage on the horizontal portion of the second tunneling layer; forming a source region in the semiconductor substrate and adjacent to the first tunneling layer; and forming a drain region in the semiconductor substrate and adjacent to the second tunneling layer; wherein the completed formed drain region is spaced apart from a respective edge of the control gate and at least a portion of the second tunneling layer overlies a portion of the semiconductor substrate free from impurities from the tilt implanting and the forming of the drain region.