Patent ID: 8484543

Claim:
A fusebay controller structure comprising: a retrieval input configured to communicate with a storage data register; a retrieval output configured to communicate with a repair data register; a storage input configured to communicate with the repair data register; a storage output configured to communicate with the storage data register; a duplicate bit (DB) state machine having a retrieval mode in which the DB state machine is configured to reconstruct a bit of data from every pair of retrieved bits, and a storage mode in which the DB state machine is configured to generate a duplicate bit of data for each bit of received repair data; an error correction code (ECC) state machine having a retrieval mode in which the ECC state machine is configured to interpret ECC syndrome bits encountered in retrieved data, and a storage mode in which the ECC state machine is configured to generate ECC syndrome bits for received repair data; a first DB selector configured to bypass the DB state machine responsive to a first DB select state and to enable the DB state machine responsive to a second DB select state; and a first ECC selector configured to bypass the ECC state machine responsive to a first ECC select state and to enable the ECC state machine responsive to a second ECC select state.