Patent ID: 8630138

Claim:
A memory system comprising: a semiconductor memory and a controller having an access control unit controlling access to the semiconductor memory, wherein the semiconductor memory includes: a pair of memory blocks each having a plurality of memory cells, and word lines and bit lines connected to the memory cells; precharge switches configured to connect the bit lines to a precharge line; a sense amplifier shared by the memory blocks; connection switches configured to connect the sense amplifier to each of the bit lines of the memory blocks; a leak memory unit configured to store information about a bad memory block having a leak failure between the word lines and the bit lines; and a switch control circuit configured to set a cutoff function to turn off at least one of the connection switches corresponding to the bad memory block in a period in which no access operation of the memory cells is performed and to turn off at least one of the precharge switches corresponding to the bad memory block while the cutoff function is set.