Patent ID: 7299341

Claim:
An instruction prefetching device adapted for use in an embedded system that comprises a system bus, a processor coupled to the system bus, at least one peripheral controller coupled to the system bus, and a memory device, said instruction prefetching device comprising: a memory controller coupled to said memory device for serving as an input/output interface of said instruction prefetching device and said memory device and for fetching an instruction from said memory device; an instruction buffer coupled to said memory controller, for storing the instruction fetched by said memory controller; and a prefetching controller coupled to said system bus, for monitoring signal transaction on said system bus so as to determine whether said system bus is in a data access phase or not, wherein when said system bus is in the data access phase, the prefetching controller enables the memory controller to prefetch the instruction from said memory device and store the prefetched instruction into said instruction buffer without utilizing said system bus.