Patent ID: 7538996

Claim:
A CMOS level shifter circuit with protection against electrostatic discharge, comprising: a first inverter that receives a first input signal and provides an inverted first input signal; a first resistance; a second resistance; a first transistor that includes a first gate which receives the inverted first input signal, a first source that is connected to a first voltage potential and a first drain; a second transistor that includes a second gate which receives the first input signal, a second source that is connected to the first voltage potential and a second drain; a third transistor having a third source connected to a second voltage potential and a third drain connected to the first drain through the first resistance, and a third inverting gate; a fourth transistor having a fourth source connected to the second voltage potential and fourth drain that provides a fourth gate signal and is connected to the second drain through the second resistance, and a fourth inverting gate connected to the third drain, where the third inverting gate is connected to the fourth drain; a second inverter that receives the fourth gate signal and provides an output signal; and a fifth transistor having a fifth gate and fifth source connected to a third voltage potential and a fifth drain responsive to the fourth gate signal.