Patent ID: 7197733

Claim:
A single integrated circuit, comprising: a first circuit having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions; a circuit for indicating a potential speed capability of the data path, the circuit for indicating comprising: a second number of logic gates for providing voltage and delay characteristics comparable to the data path, wherein the second number is less than the first number; additional circuitry for representing parasitic characteristics in the data path, providing a first capacitive load to the second number of logic gates in response to a first voltage potential applied to the second number of logic gates and to the additional circuitry, and providing a second capacitive load to the second number of logic gates in response to a second voltage potential applied to the second number of logic gates and to the additional circuitry; wherein the first capacitive load is greater than the second capacitive load when the first voltage potential is greater than the second voltage potential; and trimming circuitry, adjustable after manufacture of the circuitry for indicating a potential capability, for adjusting the operational speed of the circuitry for indicating a potential speed capability.