Patent ID: 7331045

Claim:
A method of scheduling multiple groups of instructions in a computer program for execution on a processor, said processor being schedulable using a looped schedule, comprising: (i) identifying independent, and identical groups of instructions in said computer program; (ii) counting the number of said groups of instructions identified in (i); (iii) identifying a minimum number of cycles in which scheduling may be completed on said processor in said looped schedule; (iv) calculating, in dependence upon the number of said groups of instructions counted in (ii) and said minimum number of cycles identified in (iii), a starting cycle location in said looped schedule for each of said groups of instructions; wherein (i) comprises identifying independent, identical sub-graphs in a data dependency graph (DDG) corresponding to said computer program, said sub-graphs corresponding to said groups of instructions; wherein (ii) comprises counting the number of independent, identical sub-graphs of a given type; wherein in (iii) said minimum number of cycles in which scheduling may be completed on said processor is calculated based on the number of independent, identical sub-graphs of a given type counted in (ii), and based on maximum usage of operational performance characteristics of said processor, wherein the method further comprises: assigning sub-graphs of a given type a count number, beginning with 0, and calculating said starting cycle location for each said sub-graph dependent upon the following function: ceil((this sub-graph's count number)*(initiation interval)/(total number of sub-graphs of this type)); where “ceil(n)” rounds the value ‘n’ up to the nearest integer, and said initiation interval is the minimum number of cycles in which scheduling may be completed on said processor in said looped schedule, as calculated in (iv).