Patent ID: 7735029

Claim:
An integrated-circuit design method implementing a series of design stages to generate, in the final design stage of said series, design data defining an integrated circuit, each of the design stages processing design stage representing the design-in-progress, said integrated-circuit design method comprising a process for improving the manufacturability of the integrated circuit by: during at least one design stage of said series, identifying, in a portion of the design-in-progress, a set of one or more DFM improvements that could be made, at least one DFM improvement in said set potentially conflicting with a design requirement applicable during a later design stage in said series; deferring said at least one potentially-conflicting DFM improvement such that said potentially-conflicting DFM improvement is not implemented during the design stage where it is first identified; determining, during said later design stage, whether or not at least one potentially-conflicting DFM improvement identified and deferred at an earlier design stage actually conflicts with one or more design requirements applicable during said later design stage; and implementing, in the design, said deferred at least one potentially conflicting DFM improvement only after it has been determined, in said determining step during said later design stage, that there is no actual conflict with said specified one or more design requirements, and wherein: said manufacturability-improving process comprises the step of identifying, in said portion of the design-in-progress performed by an integrated-circuit design system, a region or regions that would be affected by a particular DFM improvement of said set; and the determining step of said manufacturability-improving process comprises verifying whether there are any of said identified regions that are unaffected by said one or more design requirements, and deciding that the DFM improvement(s) corresponding to said unaffected identified region(s) does (do) not conflict with said one or more design requirements, wherein: said one or more design requirements comprise the requirement for a region affected by a DFM improvement not to overlap with, or be within a predetermined distance of, a connection track; said region-identifying step comprises the step of tagging segments of candidate paths for connection tracks, the tagged segments of the candidate paths corresponding to segments of the candidate paths which overlap with or are within a predetermined distance of a region affected by a DFM improvement, and the verifying step comprises verifying, after routing to said portion of the design-in-progress has been performed, which tagged segments of candidate paths for connection tracks have not been used for routing.