Patent ID: 8735288

Claim:
A device manufacturing method comprising: providing a semiconductor substrate; forming first and second penetration electrodes each penetrating the semiconductor substrate; forming a multi-level wiring structure on the semiconductor substrate, the multi-level wiring structure comprising a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring; forming a first wiring pad as the lower-level wiring, the first wiring pad being electrically connected to the first penetration electrode; forming a second wiring pad formed as the upper-level wiring; forming a plurality of first through electrodes in the interlayer insulating film to make an electrical connection between the first and second wiring pads; forming a third wiring pad formed as the lower-level wiring, the third wiring being electrically connected to the second penetration electrode; forming a fourth wiring pad as the upper-level wiring; and forming a plurality of second through electrodes in the interlayer insulating film to make an electrical connection between the third and fourth wiring pads, wherein a number of the first through electrodes is greater than a number of the second through electrodes.