Patent ID: 8008702

Claim:
A system comprising: a substrate; a first active region and a second active region disposed in the substrate; a first and second multi-transistor element disposed on the substrate, the first and second multi-transistor elements each including: an isolation feature; a floating gate stack adjacent to the isolation feature, the floating gate stack including a first region, a second region, and a notch interposing the first and second regions; a control gate stack adjacent to the floating gate stack; a first bitline coupled to the first region of the floating gate stack; a second bitline coupled to the second region of the floating gate stack; and a wordline adjacent to the floating gate stack and the control gate stack; an erase gate disposed on the substrate and coupled to the first and second multi-transistor elements; and a common source coupled to the first and second multi-transistor elements, wherein the first multi-transistor element is coupled to the first active region and the second multi-transistor element is coupled to the second active region, and wherein the first and second multi-transistor elements are disposed such that the notch of their respective floating gate stacks open in opposite directions.