Patent ID: 7998811

Claim:
A method for manufacturing a semiconductor device comprising: forming a first gate insulating film and a plurality of second gate insulating films on memory cell and dummy cell regions of a semiconductor device respectively, the first gate insulating film and the plurality of second gate insulating films being different in thickness; forming a first conductive film on the first gate insulating film and the plurality of second gate insulating films; forming a resist pattern on the first conductive film; forming a first floating gate electrode and a plurality of second floating gate electrodes formed of the first conductive film on the first gate insulating film and the plurality of second gate insulating films respectively by etching the first conductive film using the resist pattern as a mask; forming an isolation trench on a surface of the semiconductor substrate by etching the first gate insulating film, the plurality of second gate insulating films, and the semiconductor substrate using the resist pattern as a mask; forming an isolation insulating film in the isolation trench; forming a gate interelectrode insulating film on top surfaces of the first floating gate electrode, the plurality of second floating gate electrodes, and the isolation insulating film; forming a second conductive film on the gate interelectrode insulating film; and forming a control gate electrode and a word line which are formed of the second conductive film by etching the second conductive film, the control gate electrode being provided above the first floating gate electrode and the plurality of second floating gate electrodes via the gate interelectrode insulating film, the word line being connected to the control gate, wherein the first gate insulating film and the plurality of second gate insulating films are provided beneath the word line, wherein the plurality of second gate insulating films and the plurality of second floating gate electrodes are provided along a direction of the word line, and wherein at least one of the plurality of second floating gate electrodes has a width in the direction of the word line different from ones of the plurality of second floating gate electrodes.