Patent ID: 7750474

Claim:
An integrated circuit device comprising: a first metal interconnect, an end of the first metal interconnect being coupled to a core of the integrated circuit device; a second metal interconnect, an end of the second metal interconnect being coupled to a first input/output (I/O) pin; a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect; a fourth metal interconnect, an end of the fourth metal interconnect being coupled to another core of the integrated circuit device; and a fifth metal interconnect, an end of the fifth metal interconnect being coupled to a second I/O pin; wherein the fourth metal interconnect and the fifth metal interconnect are substantially parallel to the first metal interconnect and the second metal interconnect; and wherein the third metal interconnect lies in a plane that is different from a plane that includes the fourth metal interconnect and a plane that includes the fifth metal interconnect such that the third metal interconnect is not electrically interconnected to either the fourth metal interconnect or the fifth metal interconnect.