Patent ID: 7298201

Claim:
A clock buffer circuit comprising: a differential amplifier circuit comprising: two load resistances; two differential stage transistors connected respectively to said load resistances; two inputs connected respectively to gates of said differential stage transistors; two outputs connected respectively to said differential stage transistors; and a constant current source transistor connected to said differential stage transistors, for supplying an operating current to said differential stage transistors; and a bias circuit for supplying to a gate of said constant current source transistor a bias voltage, wherein said bias circuit generates said bias voltage such that a voltage gain of said clock buffer circuit becomes a predetermined value irrespective of a variation of the resistance value of said load resistances, said bias circuit comprises a transistor connected to said constant current source transistor wherein the transistor is formed between a current mirror circuit and said constant current source transistor, and a current synthesized from a current generated by application of a reference voltage to an internal resistor and a current generated by application of the reference voltage to an external reference resistor is fed as an input current to said current mirror circuit.