Patent ID: 7664204

Claim:
A circuit, comprising: a phase locked loop to generate a local clock signal having a first phase and a first frequency; an offset adjustment circuit receiving timing information relating the local clock signal to an incoming data signal, to calculate a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal; a first phase interpolator, in communication with the phase locked loop and the offset adjustment circuit, to generate a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets; a clock recovery circuit, in communication with the first phase interpolator and the offset adjustment circuit, to generate the timing information responsive to whether the receive clock signal leads or lags the incoming data signal; a frequency detector, in communication with the offset adjustment circuit, to track the frequency offset and identify changes in a target frequency responsive to the frequency offset; a second phase interpolator, in communication with the phase locked loop and the frequency detector, to generate a transmit clock signal from the local clock signal having a third frequency responsive to the target frequency; and a transmitter, in communication with the second phase interpolator, to generate an outgoing data signal at the third frequency.