Patent ID: 7309649

Claim:
A method of building a closed air gap interconnect structure comprising the steps of: coating a first sacrificial dielectric on a substrate and patterning a set of discrete support regions formed by lithography therein; filling and planarizing said discrete support regions with a robust line support dielectric; patterning contact via holes in said first sacrificial dielectric by reactive ion etching; coating a second sacrificial dielectric on said first sacrificial dielectric and said discrete support regions; depositing a hard mask layer on said second sacrificial dielectric; patterning and etching line trenches in said second sacrificial dielectric and said hard mask layer; depositing a thin conformal dielectric passivation liner layer on said contact via holes and said line trenches; filling said line trenches and said contact via holes with a conductive liner and conductive fill material and planarizing said conductive fill material so that a top surface of said conductive fill material is substantially coplanar with a top surface of said hard mask layer; depositing a first dielectric cap layer on said hard mask layer and forming a stencil having a regular array of holes on a top surface of said first dielectric cap layer; transferring said regular array of holes into said first dielectric cap layer and said hard mask layer by reactive ion etching; extracting said first sacrificial dielectric and said second sacrificial dielectric through said contact via holes to form air gaps located substantially between said line trenches and a region beneath said line trenches not occupied by said contact via holes and said discrete support regions; and closing off said regular array of holes by depositing a second dielectric cap layer on said first dielectric cap layer to pinch off said regular array of holes in said first dielectric cap layer thereby forming said closed air gap interconnect structure.