Patent ID: 8405201

Claim:
An integrated circuit device, comprising: a semiconductor substrate having a front surface and a back surface with an integrated circuit (IC) component formed on the front surface; an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate; a contact plug formed in the ILD layer and electrically connected to the IC component; and a via structure formed in the ILD layer and extending through the semiconductor substrate, wherein the via structure comprises a metal layer, a metal seed layer surrounding the metal layer and having a sidewall, a barrier layer surrounding the metal seed layer, and a block layer sandwiched between the metal layer and the metal seed layer and extending along only a portion of the sidewall of the metal seed layer; and wherein the block layer comprises at least one of magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), or cadmium (Cd).