Patent ID: 8508969

Claim:
A device comprising: a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers; a plurality of second global bit lines each extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that each of the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers; a first memory block including a plurality of first local bit lines that are arranged in the first direction and a plurality of first hierarchy switches each coupled between an associated one of the first global bit lines and an associated one of the first local bit lines, the first memory block being disposed on the left side of the first sense amplifier array; a second memory block including a plurality of second local bit lines that are arranged in the first direction and a plurality of second hierarchy switches each coupled between an associated one of the first global bit lines and an associated one of the second local bit lines, the second memory block being disposed on the left side of the first sense amplifier array and sandwiched between the first sense amplifier array and the first memory block; a third memory block including a plurality of third local bit lines that are arranged in the first direction and a plurality of third hierarchy switches each coupled between an associated one of the second global bit lines and an associated one of the third local bit lines, the third memory block being disposed on the right side of the first sense amplifier array; and a fourth memory block including a plurality of fourth local bit lines that are arranged in the first direction and a plurality of fourth hierarchy switches each coupled between an associated one of the second global bit lines and an associated one of the fourth local bit lines, the fourth memory block being disposed on the right side of the first sense amplifier array and sandwiched between the first sense amplifier array and the third memory block; the first, second, third and fourth memory blocks being address-mapped such that the first and third hierarchy switches are rendered conductive while keeping the second and fourth hierarchy switches non-conductive and the second and fourth hierarchy switches are rendered conductive while keeping the first and third hierarchy switches non-conductive.