Patent ID: 7321398

Claim:
A processing circuit for a sync signal, comprising: a trial reference counter configured to receive a reference clock as a clock input and a first sync signal as a reset input and output a first count value; a trial sync spacing register configured to store a second count value; a trial window shaper circuit configured to receive the first count value and the second count value and generate a trial window signal when the first count value exceeds the second count value; a confirmation counter circuit configured to receive a window clock as a clock input, generate a confirmation count based on the window clock, and generate a confirmation signal when the confirmation count exceeds a minimum value; a reference counter configured to receive a reference clock as a clock input and an initialization signal as a reset input and output a third count value; and a window shaper circuit configured to receive the third count value and the second count value and generate the window signal when the third count value exceeds the second count value; wherein the window clock comprises a logic output operation based on the trial window signal and the first sync signal.