Patent ID: 7885110

Claim:
A memory device, comprising: a plurality of row lines and a plurality of column lines; a memory cell coupled to one of the plurality of column lines and to one of the plurality of row lines, wherein the memory cell includes a storage capacitor coupled to a storage node, a CMOS-compatible non-volatile storage element coupled to the storage node, and an access transistor coupled to the storage node; and access circuitry coupled to the CMOS-compatible non-volatile storage element, to the plurality of row lines, and to the plurality of column lines, wherein the access circuitry is configured to perform a read operation, and wherein the read operation comprises: an activation of the CMOS-compatible non-volatile storage element at a first time, wherein the CMOS-compatible non-volatile storage element is configured, in response to the activation, to apply a voltage to the storage node corresponding to a stored binary value; and a setting of the one of the plurality of row lines to a select voltage at a second time, later than the first time, wherein the storage capacitor is configured to substantially hold the voltage applied to the storage node for a period of time, and wherein an elapsed time between the first time and the second time is equal to or less than the period of time.