Patent ID: 7304904

Claim:
A memory system comprising: a sense amplifier, the sense amplifier including: a first inverter, the first inverter configured to sense a signal received by the sense amplifier and to produce a precharge voltage on a bitline, the bitline configured to be coupled to the sense amplifier; a feedback device, the feedback device coupled between an input of the first inverter and an output of the first inverter, the feedback device configured to communicate the precharge voltage to an input of the first inverter; a pull-up device, the pull-up device coupled between an input of the first inverter and an output of a supply-level voltage source; and a second inverter, the second inverter coupled to the output of the first inverter and configured to receive a first output signal from the first inverter and produce a second output signal, the second output signal being an output signal of the sense amplifier, the second output signal being an amplified version of the first output signal.