Patent ID: 8232822

Claim:
A charge pump, for providing an output signal according to a first control signal and a second control signal, the charge pump comprising: a first current source comprising a first transistor having a first terminal coupled to a first voltage; a second current source comprising a second transistor having a first terminal coupled to a second voltage; a first switch, having a control terminal for receiving the first control signal, a first terminal coupled to a second terminal of the first transistor, and a second terminal coupled to an output terminal of the charge pump; a second switch, having a control terminal for receiving the second control signal, a first terminal coupled to a second terminal of the second transistor, and a second terminal coupled to the output terminal of the charge pump; a third switch, having a control terminal for receiving an inverted signal of the first control signal and a first terminal coupled to the second terminal of the first transistor; a fourth switch, having a control terminal for receiving an inverted signal of the second control signal, a first terminal coupled to the second terminal of the second transistor, and a second terminal coupled to a second terminal of the third switch; a reset switch, having a first terminal coupled to the second terminal of the third switch and a second terminal coupled to the output terminal of the charge pump; a third transistor, having a first terminal coupled to the first voltage and a control terminal coupled to a control terminal of the first transistor; a fourth transistor, having a first terminal coupled to the second voltage, a second terminal coupled to a second terminal of the third transistor, and a control terminal coupled to a control terminal of the second transistor, wherein the control terminals of the second transistor and the fourth transistor are controlled by a bias circuit; and an operational amplifier, having a first input terminal coupled to the output terminal of the charge pump, a second input terminal coupled to the second terminal of the third transistor, and an output terminal coupled to the control terminals of the first transistor and the third transistor.