Patent ID: 8677293

Claim:
A computer-implemented method of evaluating proposed edits to a target layer of an integrated circuit, comprising executing code on a processor to perform processes including: determining at a layout layer of integrated circuit design, with aid of the computer, a number of editable regions for metal layers overlying the target layer, wherein an editable region for a metal layer is laterally arranged between segments of the metal layer; identifying a number of possible vertical milling paths extending from an exterior surface of the integrated circuit to the target layer at the layout layer of integrated circuit design, each possible vertical milling path passing through at least one editable region; generating a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, wherein each edit plan places possible edits that are based on the proposed edits in a different combination of possible vertical milling paths at the layout layer of integrated circuit design, calculating a figure of merit for each possible edit plan based on a set of predetermined factors, wherein the figures of merit for each possible edit plan are added together to form a sum for each possible edit plan, and selecting one of the number of possible edit plans to carry out an actual edit on a physical implementation of the integrated circuit, the selecting determined selecting an edit plan with the highest figure of merit.