Patent ID: 7373631

Claim:
A method of synthesizing a logic design for a structured ASIC implementation that is substantially functionally equivalent to an FPGA implementation of that logic design, the structured ASIC having an architecture that includes a plurality of hybrid logic elements, and the FPGA having an architecture that includes a plurality of look-up tables, each of the look-up tables having more logic capacity than each of the hybrid logic elements, the method comprising: producing a synthesis of the logic design that is usable to produce the FPGA implementation; dividing the synthesis into a plurality of parts, each of which is implementable in one of the look-up tables; and resynthesizing each of the parts for the structured ASIC implementation, wherein at least one of the parts requires more than a predetermined number of the hybrid logic elements, and wherein the resynthesizing of the at least one part comprises: subdividing the at least one part into a plurality of subparts; and resynthesizing each of the subparts for the structured ASIC implementation using no more than the predetermined number of the hybrid logic elements for each of the subparts.