Patent ID: 8553827

Claim:
A Phase-Locked Loop (PLL) circuit, comprising: a Phase-to-Digital Converter (PDC) configured to receive a reference signal and a feedback signal and to generate a stream of digital phase error words, wherein the PDC includes a charge pump and an Analog-to-Digital Converter (ADC), wherein the charge pump is configured to supply a pulse train to the ADC; a digital loop filter configured to receive the stream of digital phase error words, to filter the stream, and to output a stream of digital tuning words; a Digitally-Controlled Oscillator (DCO) configured to receive the stream of digital tuning words and to output an oscillating signal; and a loop divider configured to receive the oscillating signal and to output the feedback signal, wherein the charge pump is configured to supply the pulse train to an input node of the ADC, the pulse train includes a plurality of current pulses, each current pulse has a current magnitude, the charge pump is configured to receive a digital lock signal indicative of whether the PLL is in lock and to control the current magnitude as a function of the lock signal, the current magnitude of the current pulses is greater when the lock signal indicates that the PLL is in-lock, and the current magnitude of the current pulses is smaller when the lock signal indicates that the PLL is not in-lock.