Patent ID: 8295073

Claim:
A memory system, comprising: a back-end-of-the-line (BEOL) portion including a non-volatile third dimensional memory array, the non-volatile third dimensional memory array including a memory element, wherein the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage; a front-end-of-the-line (FEOL) portion including active circuitry, the active circuitry including a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, wherein the transceiver gate is further configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being electrically coupled with the memory element and configured to provide the another voltage; and a plurality of word lines electrically coupled with the memory element, wherein the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.