Patent ID: 8576603

Claim:
Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell on a second semiconductor device, the first and second semiconductor devices each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology using at least one non-volatile technology mask and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology using at least one baseline mask and comprising a single gate transistor which method includes manipulating a layout of the at least one baseline mask; the manipulation comprising: incorporating into a layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell in the at least one baseline mask to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating a layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell, wherein the Flash memory cell is paired with a second Flash memory cell that share a common contact, and the manipulation of the at least one baseline mask comprises: elimination of a layout of the common contact from the at least one baseline mask, and creating a layout for a ROM memory cell contact at the location of the former floating transistor.