Patent ID: 7721137

Claim:
A bus receiver, for receiving at least one first signal and a second signal both generated from an integrated circuit connected to a parallel bus, comprising: a receiving module electrically connected to the parallel bus to receive the first signal and the second signal transmitted through the parallel bus; and a deskewing module electrically connected to the receiving module to deskew the phases of the first signal and the phase of the second signal such that the first signal and the second signal are in the same phase, wherein the deskewing module comprises: at least one delay unit electrically connected to the receiving module; and at least one comparing unit for comparing the phases of the first signal and the second signal; wherein a first phase skew signal or a second phase skew signal is enabled and outputted to the delay unit in response to the compare, and the delay unit decreases or increases a delay time for transmitting the first signal in response to the first phase skew signal or the second phase skew signal such that the first signal and the second signal are synchronous in phase.