Patent ID: 8187943

Claim:
A process for manufacturing a MOS device resistant to ionizing-radiation, comprising: forming a surface semiconductor layer with a uniform thickness having a first type of conductivity; forming a gate structure above said surface semiconductor layer, said step of forming a gate structure comprising forming a dielectric gate region above said surface semiconductor layer and forming a gate-electrode region above said dielectric gate region; and forming body regions having a second type of conductivity within said surface semiconductor layer, laterally and partially underneath with respect to said gate structure such that an intercell region is formed in the semiconductor layer between body regions; wherein forming said dielectric gate region comprises forming a central region of said dielectric gate region, having a first thickness, above said surface semiconductor layer, and, subsequently, forming side regions of said dielectric gate region, having a second thickness, smaller than said first thickness such that the side regions are disposed over at least a portion of a body region and over at least a portion of the intercell region.