Patent ID: 8163601

Claim:
A method of making a chip-exposed semiconductor package comprising: plating a metal on a front side of a wafer comprising a plurality of chips thereon, wherein each chip on the wafer is provided with a gate electrode comprising a first gate metal layer and a source electrode comprising a first source metal layer on the front face of the wafer wherein the step of forming a plurality of plating areas on a front face of each chip comprising plating a second gate metal layer on top of the first gate metal layer and a second source metal layer on top of the first source metal layer, said plating a metal therefore forms a plurality of plating areas on a front face of each chip; grinding a backside of the wafer to reduce a thickness of the wafer; depositing a back metal layer on the backside of the wafer after grinding; applying a layer of conductive adhesive material on said plurality of plating areas; sawing the wafer with the back metal layer to form a plurality of separate chips each having the back metal layer located on a backside of the chip; providing a leadframe comprising a plurality of paddles, wherein each of the paddles is provided with a first metal contact finger and a plurality of second metal contact fingers substantially coplanar with the first metal contact finger and wherein a face of said first metal contact finger interfaces with the second gate metal layer via the conductive adhesive material and a face of said second metal contact fingers interfaces with the second source metal layer via the conductive adhesive material, and mounting a chip with the front face of the chip adhering onto a front face of each of the plurality of paddle through the conductive adhesive material disposed on the front face of the chip; adhering a tape on the back metal located on the backside of the chip; encapsulating the leadframe and the plurality of chips adhered onto the leadframe with a molding compound; removing the tape to expose the back metal on the backside of the chip through the molding material; sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.