Patent ID: 8675436

Claim:
A multi-channel semiconductor memory device, comprising: a plurality of sub-memory circuits, each sub-memory circuit having a memory cell array, a row decoder and a column decoder; and a common memory controller configured to control the sub-memory circuits so that two or more of the sub-memory circuits do not simultaneously perform a refresh operation, wherein each of the sub-memory circuits comprise a refresh controller configured to output a refresh mode signal to the common memory controller if a refresh command is received, to perform the refresh operation in response to a refresh enable signal received from the common memory controller, and to activate and output a refresh operation enable signal during the refresh operation, wherein the common memory controller comprises a common refresh controller configured to determine whether a sub-memory circuit has the activated refresh operation enable signal if the refresh mode signals are received from two or more of the sub-memory circuits, and to inactivate the refresh enable signals for the remaining sub-memory circuits while a sub-memory circuit has the activated refresh operation enable signal.