Patent ID: 8629691

Claim:
An integrated device comprising: a hard logic portion comprising a plurality of hard logic blocks, wherein a first of the hard logic blocks is configured to provide a first data signal; a field programmable gate array (“FPGA”) fabric comprising control logic and a plurality of soft logic modules, wherein a first of the soft logic modules is configured to provide a second data signal; and an interface configured to route signals between the hard logic portion and the FPGA fabric, the interface comprising: a combiner circuit; a first multiplexer configured to provide one of the first data signal and a zero value signal to the combiner circuit; and a second multiplexer configured to provide one of the second data signal and the zero value signal to the combiner circuit; wherein the combiner circuit is configured to combine the signals provided by the first and second multiplexers and to output a combined signal; wherein, responsive to a control signal from the control logic, the interface is further configured to selectively couple a first node in the hard logic portion to a node in the FPGA fabric.