Patent ID: 7440335

Claim:
A memory comprising: a plurality of lower level bit lines comprising: a first bit line and a second bit line; a higher level bit line; and bit line driving circuitry comprising: a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines; a first select input to receive a first select value; a second select input to receive a second select value, the second select value separate from the first select value; a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of the first select value; a second transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the first transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a representation of a first bit line value at the first bit line; a third transistor comprising a first current-carrying electrode coupled to the higher level bit line, a second current-carrying electrode coupled to a second voltage reference, and a control electrode to receive the representation of the first bit line value; a fourth transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of the second select value; a fifth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the fourth transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a representation of a second bit line value at the second bit line; a sixth transistor comprising a first current-carrying electrode coupled to the higher level bit line, a second current-carrying electrode coupled to the second voltage reference, and a control electrode to receive the representation of the second bit line value; and an output configured to drive a select one of a first bit value or a second bit value at the higher level bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.