Patent ID: 7038231

Claim:
A crosspoint memory array comprising: a substrate; a first conducting layer comprising conducting material on said substrate: a bit line comprising a first hard mask layer comprising conducting material adapted to be resistant to both a first and second etching process, wherein said bit line comprises both said conducting material of said first conducting layer and said conducting layer of said first hard mask layer; a multilayer stack over said bit line, wherein said multilayer stack comprises a phase-change material layer and a heater layer; a second conducting layer comprising conducting material on said multilayer stack; and a word line comprising a second hard mask layer comprising conducting material adapted to be resistant to said second etching process, wherein said word line comprises both said conducting material of said second conducting layer and said conducting layer of said second hard mask layer, wherein said word line being positioned over said multilayer stack and positioned at an angle to said bit line, and wherein said phase-change material layer is in contact with each of said bit line and said word line.