Patent ID: 8482045

Claim:
A semiconductor memory device, comprising: a plurality of active regions each of which has a first side surface and a second side surface opposite the first side surface, wherein the plurality of active regions are arranged in a first direction which is their lengthwise direction, and in a second direction different from the first direction such that a portion of the first side surface of each active region faces at least a portion of the second side surface of another active region, wherein the plurality of active regions are arranged such that a first group of active regions extending along the lengthwise direction faces a second group of active regions extending along the lengthwise direction, such that, in the lengthwise direction, a series of consecutive overlapping regions are formed where first side surfaces of an active region in the first group face second side surfaces of an active region in the second group; gate electrodes disposed at positions between the active regions where the first side surface and the second side surface face each other, such that along the lengthwise direction, gate electrodes are located at every other overlapping region, and insulating layers are located at positions between the gate electrodes; a word line connected to each gate electrode; and a bit line going across the active regions.