Patent ID: 7541848

Claim:
A PLL circuit comprising: a voltage controlled oscillator controlled by an analog control signal controlling an oscillation frequency over a first range and a digital control signal controlling the oscillation frequency over a range narrower than the first range; a frequency comparison circuit comparing one of a frequency of an output of the voltage controlled oscillator and a frequency of a signal obtained by frequency-dividing the output of the voltage controlled oscillator; and a frequency of a reference signal; and a phase comparison circuit comparing one of a phase of the output of the voltage controlled oscillator and a phase of the signal obtained by frequency-dividing the output of the voltage controlled oscillator; and a phase of the reference signal, wherein the PLL circuit is configured to control the oscillation frequency of the voltage controlled oscillator so that a frequency and a phase of one of the output of the voltage controlled oscillator and the signal obtained by frequency-dividing the output of the voltage controlled oscillator conform to the frequency and the phase of the reference signal, wherein a first circuit determining whether control of the oscillation frequency of the voltage controlled oscillator has reached a steady state is provided, and wherein at least one of a second circuit operating only when determination that the steady state has not been reached is made and a third circuit operating only when determination that the steady state has been reached is made is provided.