Patent ID: 7259459

Claim:
A semiconductor module comprising: a conductive plate having a first surface; a first semiconductor chip including a first MIS transistor, a source electrode of the first MIS transistor being formed on a bottom of the first semiconductor chip and connected to the first surface of the conductive plate; a second semiconductor chip including a second MIS transistor, a drain electrode of the second MIS transistor being formed on a bottom of the second semiconductor chip and connected to the first surface of the conductive plate, and the drain electrode of the second MIS transistor being electrically connected to the source electrode of the first MIS transistor through the conductive plate; an IC chip electrically connected to both a gate electrode of the first MIS transistor formed on a top of the first semiconductor chip and a gate electrode of the second MIS transistor formed on a top of the second semiconductor chip; an insulative envelope covering the conductive plate, the first semiconductor chip, the second semiconductor chip, and the IC chip; and connecting terminals electrically connected to the conductive plate, the first semiconductor chip, and the second semiconductor chip, the connecting terminals being partly exposed from the envelope.