Patent ID: 6842054

Claim:
Apparatus for generating an output signal whose frequency is lower than the frequency of an input signal, the apparatus comprising: a chain of frequency dividing cells, wherein each of the frequency dividing cells has a pre-defined division ratio and comprises a clock input for receiving an input clock; a divided clock output for providing an output clock to a subsequent frequency dividing cell; a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell; and a mode control output for providing a mode control output signal to a preceding frequency dividing cell; a latch for altering the division ratio of each the frequency dividing cells, a D-Flip-Flop circuitry with two latches, the first latch being clocked by a first signal output from the subsequent frequency dividing cell and the second latch being clocked by a second signal input to the preceding frequency dividing cell, whereby the frequency of the first signal is lower than the frequency of the second signal.