Patent ID: 8203327

Claim:
A device for counting oscillations of an oscillating time signal, which comprises: a first comparator which receives said time signal and which compares it to a first threshold value which is positive; a first AND logic gate, a first input of which is linked to the output of said first comparator; a first two-input bistable flip-flop, a signal input of which is linked to the output of said first AND logic gate; a first inverter which is mounted between the output of said first bistable flip-flop and the second input of said first AND logic gate; a second comparator which also receives said time signal and which compares it to a second threshold value which is negative, the output of said second comparator being linked to an initialization input of said first bistable flip-flop; a second AND logic gate, a first input of which is linked to the output of said second comparator; a second two-input bistable flip-flop, a signal input of which is linked to the output of said second AND logic gate, and an initialization input of which is linked to the output of said first comparator; a second inverter which is mounted between the output of said second bistable flip-flop and the second input of said second AND logic gate; an OR logic gate, the two inputs of which are linked respectively to the outputs of said first and second AND logic gates, and the output of which controls a switching means to generate a unit value intended to increment a counter, each time said time signal exceeds, alternatively, one of said first and second threshold values; and said counter which is thus incremented and which handles the counting of the oscillations of said oscillating time signal.