Patent ID: 8028286

Claim:
A method for scheduling applications on a chip multiprocessor comprising: identifying a thread operable to be scheduled by a scheduling policy for execution on the chip multiprocessor; estimating, for the thread, a performance value based on runtime statistics of the thread for a shared resource on the chip multiprocessor; applying the performance value to the scheduling policy in order to reallocate processor time of the thread commensurate with the performance value under fair distribution of the shared resource on the chip multiprocessor; and applying the performance value to the scheduling policy in order to reallocate processor time of at least one co-executing thread to compensate for the reallocation of processor time to the thread; wherein the estimating, for the thread, a performance value based on runtime statistics of the thread for a shared resource on the chip multiprocessor comprises at least one of: determining a fair level 2 (L2) cache miss rate based on the number of L2 cache misses per processing cycle that the thread would experience under equal L2 cache sharing on the chip multiprocessor; and determining a fair cycles per instruction (CPI) rate based on the number of processing cycles per instruction achieved by a thread under equal L2 cache sharing on the chip multiprocessor; and wherein the estimating, for the thread, a performance value based on runtime statistics of the thread for a shared resource on the chip multiprocessor comprises: estimating a fair number of instructions value based on the number of instructions the thread would have executed under the existing scheduling policy using the fair CPI rate; and determining the actual number of instructions completed by the thread for a predetermined time.