Patent ID: 6967611

Claim:
An analog-to-digital converter (ADC) comprising: an amplifier comprising an input and an output; and a switched capacitor network coupled to the input of the amplifier and being coupled to receive an analog input signal and a plurality of reference input signals input to the ADC comprising at least a first reference input signal and a second reference input signal, the switched capacitor network comprising a plurality of capacitors and switches, each of the plurality of capacitors being coupled to receive at least one of the analog input signal or one of the plurality of reference input signals, wherein the amplifier and switched capacitor network are configured to scale at least one of the plurality of reference input signals by a predetermined scale factor, the predetermined scale factor being determined at least in part by capacitance values of the switched capacitor network, the amplifier and switched capacitor network being further configured to provide an output signal comprising a predetermined gain of the analog input signal adjusted by the predetermined scale factor of the at least one of the plurality of reference input signals, the switched capacitor network comprising a first capacitor controllably coupled to receive the analog input signal, a second capacitor controllably coupled to alternately receive the analog input signal or the first reference input signal, and a third capacitor controllably coupled to alternately receive the analog input signal and the second reference input signal, the third capacitor being further controllably coupled to the first reference input signal and a third reference input signal, and wherein: the third capacitor is coupled to the analog input signal during a first clock phase; the third capacitor is coupled to the second reference input signal during a second clock phase when the analog input signal is within a first signal range; the third capacitor is coupled to the first reference input signal during a second clock phase when the analog input signal is within a second signal range; and the third capacitor is coupled to the third reference input signal during the second clock phase when the analog input signal is within a third signal range.