Patent ID: 7178072

Claim:
A method for storing memory test information, the method comprising the steps of: storing a portion of information related to locations and numbers of failed memory cells detected while testing memory, wherein the information is stored in a table having row and column portions, each row and column portion of the table including at least one address/error-count entry pair for storing an address of the respective row or column portion of memory where the failed memory cell is located and the number of failed memory cells detected in the respective row or column portion of memory; and updating the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable, based in part on whether a number of failed memory cells in a respective row or column portion of memory where the failed memory cell is located exceeds a number of available complementary type memory spares; wherein the first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.