Patent ID: 8336012

Claim:
A method for reducing a timing violation in a negative slack path from an integrated circuit design, the method comprising the steps of: identify the negative slack path in the integrated circuit design with a processor, identify positive slack paths by determining timing slack for paths disposed before and after the negative slack path, predict if whether performing additional timing optimization on the positive slack paths will produce additional margin on top of margin already available from the positive slack paths by applying more aggressive settings to a synthesis/physical optimization tool on the integrated circuit design, without actually performing additional timing optimization on the positive slack paths, determine if the additional margin is sufficient to reduce the timing violation to at least a desired level, perform additional timing optimization on the positive slack paths only when the margin is sufficient, use the margin to manipulate clock skew to reduce the timing violation on the negative slack path, and wherein the step of predicting whether margin can be obtained from a positive slack path is accomplished by analyzing at least two of: a number of cells in the path, types of cells in the path, fanout at each cell input/output pin in the path, drive strength of cells in the path, propagation delay across cells, interconnect delay on nets in the path, maximum delay threshold of cells in the path, and maximum net delay threshold.