Patent ID: 8183116

Claim:
A method of manufacturing a double gate transistor comprising a channel region and two gate electrodes disposed on opposing sides of the channel region, the method comprising the steps of: providing a semiconductor wafer with a laminate structure comprising an initial crystalline semiconductor layer which comprises a channel region, adjacent an amorphous semiconductor layer, introducing crystallisation inhibitors into a selected region of the semiconductor wafer, said selected region extending through the amorphous semiconductor layer in a position corresponding to a lateral position of the channel region; performing a crystallisation operation so as to crystallise regions of the amorphous semiconductor layer outside of the selected region thereby forming a developed crystalline semiconductor layer having a greater thickness than a thickness of said initial crystalline semiconductor layer away from said selected region and a substantially similar thickness to the thickness of said initial crystalline semiconductor layer within the selected region; selectively removing remaining amorphous semiconductor material; and forming gate electrodes on opposing sides of the channel region.