Patent ID: 8377772

Claim:
A method of fabricating a CMOS transistor comprising: providing a semiconductor substrate comprising isolated regions of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor; setting a threshold voltage (VT) of the I/O NMOS transistor by implanting a P-type dopant in the I/O NMOS transistor; setting a threshold voltage (VT) of the I/O PMOS transistor by masking the logic PMOS transistor and the I/O NMOS transistor and implanting an N-type dopant in the I/O PMOS transistor and the logic NMOS transistor to form a deep NWELL in both the logic NMOS transistor and the I/O PMOS transistor; masking both the I/O NMOS transistor with the set VT and the I/O PMOS transistor with the set VT to form an NWELL region in the logic PMOS transistor; and masking both the I/O NMOS transistor with the set VT and the I/O PMOS transistor with the set VT to form a PWELL region in the logic NMOS transistor.