Patent ID: 8230283

Claim:
A method for detecting hold path faults in an integrated circuit structure, comprising: identifying a set of data paths within the integrated circuit structure with at least one data path statistically having the highest timing slack within the integrated circuit structure, one data path traverses a setup storage device and a launch storage device and another data path traverses the launch storage device and a sink storage device; applying a test pattern to the integrated circuit structure to cause a data output pin of the launch storage device to initially assume a first logic value; generating a clock pulse along a clock path of the integrated circuit structure to cause the data output pin of the launch storage device to assume a second logic value opposite the first logic value, enabling a logic transition to travel from the launch storage device to the sink storage device; and examining the sink storage device to determine whether the sink storage device captured the effect of the transition, wherein a hold path fault is detected in the integrated circuit structure when the sink storage device captures the second logic value upon issuance of the clock pulse as a result of the transition of the data output pin of the launch storage device from the first logic value to the second logic value reaching a data input pin of the sink storage device prior to the sink storage device receiving the clock pulse.