Patent ID: 8110857

Claim:
An integrated circuit including a junction field effect transistor (JFET), comprising: a buried layer having a first electrical conductivity type formed in a semiconductor substrate; an epitaxial layer having a second electrical conductivity type formed over the semiconductor substrate and over the buried layer; first well regions having the first electrical conductivity type formed in the epitaxial layer down to the buried layer; a second well region having the second electrical conductivity type formed within the epitaxial layer between the first well regions; isolation regions formed in the surface of the epitaxial layer to electrically isolate different active areas from one another; a first threshold voltage region having the first electrical conductivity type formed in the second well region within a first active area between first and second adjacent ones of the isolation regions; a second threshold voltage region having the second electrical conductivity type formed in the first threshold voltage region, the first threshold voltage region formed deeper than the second threshold voltage region; and a source region and a drain region having the first electrical conductivity type formed in a spaced apart relationship in the first threshold voltage region.