Patent ID: 8817637

Claim:
An apparatus comprising: processing circuitry; and a storage device comprising algorithms, the processing circuitry configured to execute the algorithms, which causes the apparatus to: enable transmission of packet formatted data formatted at a first logical layer comprising a lower layer, utilizing a first-layer acknowledgement mechanism and enable transmission of the packet formatted data at a second logical layer comprising an upper layer that is higher than the lower layer, utilizing a second-layer acknowledgment mechanism; and generate an estimate of a selected second logical layer delay period, in response to received indicia, by which to delay generation of a second logical layer resend request requesting resending of the packet formatted data in an instance in which a determination reveals that the packet formatted data is unsuccessfully delivered to a second logical layer of a terminal, wherein the estimate of the selected second logical layer delay period is a fixed delay period based in part on the received indicia that is associated with communication characteristics corresponding to radio quality information of a communication system, the estimate of second logical layer delay period is generated prior to sending of the second logical layer resend request.