Patent ID: 7598775

Claim:
A phase and frequency detector comprising: a first phase and frequency detector configured to generate first and second pulsed signals in response to a comparison between a defined occurrence of first and second input signals, the first phase and frequency detector including first and second D-type flip-flops, wherein the clocking terminals of the first and second D-type flip-flops are configured to receive the first and second input signals respectively, the D terminals of the first and second D-type flip-flops are set to an asserted state, and the Q outputs of the first and second D-type flip-flops provide the first and second pulsed signals respectively; a reset signal generator configured to provide a reset signal to the reset terminals of the first and second D-type flip-flops based on the state of the first and second pulsed signals, wherein the reset signal generator includes an AND gate enabled by the first and second pulse signals and a delay buffer configured to delay the output the AND gate by a set delay to provide the reset signal; and a pulse blocker that receives the first and second pulsed signals and provides first and second output signals, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted.