Patent ID: 7718489

Claim:
A semiconductor structure fabrication method, comprising: forming a first structure that comprises (i) a semiconductor layer, (ii) first and second spacers on the semiconductor layer, and (iii) sacrificial back gate on the semiconductor layer, wherein the back gate is sandwiched between and is in direct physical contact with the first spacer and the second spacer, wherein said forming the first structure comprises forming the first spacer on the semiconductor layer, followed by forming the sacrificial back gate around the first spacer, followed by forming the second spacer around the sacrificial back gate; after said forming the first structure, etching away the sacrificial back gate and a portion of the semiconductor layer to form a first gate trench in the first structure, wherein said etching away leaves both the first spacer and the second spacer intact; filling the first gate trench so as to form a first conductive gate that is electrically insulated from the semiconductor layer by a first gate dielectric layer, wherein said filling results in the first conductive gate being in direct physical contact with both the first spacer and the second spacer, and wherein said filling further results in a top surface of the first conductive gate, a top surface of the first spacer, and a top surface of the second spacer being coplanar; after said filling, etching a portion of the first spacer which results in a remaining portion of the first spacer being a third spacer on a first side wall of the first conductive gate; after said etching the portion of the first spacer, using the third spacer as a blocking mask to etch the semiconductor layer so as to form a first fin on the first side wall of the first conductive gate; after said using the third spacer as the blocking mask, forming a first source/drain and a second source drain in the semiconductor layer; and after said forming the first source/drain and the second source drain in the semiconductor layer, forming a first conductive gate object on a second side wall of the first fin, wherein the first conductive gate object is electrically insulated from the first fin, the first source/drain, and the second source/drain.