Patent ID: 7760752

Claim:
A switch element having a plurality of ports, each port having a receive segment and a transmit segment for routing frames, comprising: a plurality of pseudo virtual lanes (PVLs) for transmitting frames, where each PVL is assigned a configurable initial priority for transmitting frames when credit is available at a receive segment of another port for receiving a frame; a first storage module for storing a configurable threshold value for each PVL that determines a number of credits that are allocated for each PVL before credit allocation for the PVL is modified; a second storage module for storing a configurable maximum credit value assigned to each of the PVL and at any given time, credit is assigned to a PVL if the maximum credit value has not been reached; a credit monitoring module for monitoring the threshold value and the maximum credit value for modifying a priority of the plurality of PVLs when credit is received for transmitting a frame; a timer module that monitors frame traffic for each PVL and if a PVL stops transmitting frames beyond a certain programmable duration, then an indicator is set indicating that the PVL is congested so that priority for the congested PVL can be lowered; and a minimum bandwidth module for providing a minimum bandwidth level for all the PVLs, which when enabled, bypasses credit assignment for the plurality of PVLs based on assigned priority, and instead assigns available credit to a PVL that was a last PVL to have been assigned credit.