Patent ID: 7935637

Claim:
A method for fabricating a microelectronic structure comprising: forming a backfilling material layer at least laterally adjacent a surface treated resist layer, wherein the backfilling material layer and the surface treated resist layer cover an entire upper surface of a substrate, wherein the surface treated resist layer includes an n-type or p-type doped first upper surface; surface treating the backfilling material layer to form a surface treated backfilling material layer at least laterally adjacent the surface treated resist layer, wherein the surface treated backfilling material layer includes an n-type or p-type doped second upper surface; and simultaneously etching the n-type or p-type doped first upper surface selective to an underlying portion of the surface treated resist layer and the n-type or p-type doped second upper surface selective to an underlying portion of the backfilling material layer with a first etch chemistry using a fluorine and carbon containing etchant gas; and simultaneously etching the underlying portion of the surface treated resist layer and the underlying portion of the backfilling material layer with a second etch chemistry that is selective to the substrate, wherein the second etch chemistry does not include fluorine and carbon containing etchant gas.