Patent ID: 7407871

Claim:
A method of forming a metal oxide semiconductor (MOS) device on a semiconductor substrate featuring passivation of defects at or near the top surface of said semiconductor substrate, comprising the steps of: forming an insulator isolation region in a top portion of a first region of said semiconductor substrate; forming a gate insulator layer on a second region of said semiconductor substrate, wherein said second region is not occupied by said insulator isolation region; depositing a group of layers; performing a plasma dry etch procedure to remove said group of layers from a first portion of said gate insulator layer while defining a gate electrode structure comprised of said group of layers on a second portion of said gate insulator layer; performing a first ion implantation procedure to form a source/drain region in portions of said second region of said semiconductor substrate not overlaid by said gate electrode structure; forming a first insulator spacer on a lower portion of said gate electrode structure; performing a second ion implantation procedure placing implanted ions into a top portion of said source/drain region for passivating said defects; forming a second insulator spacer on said gate electrode structure and on said first insulator spacer; and forming raised source/drain contacts on top of exposed regions of said source/drain region.