Patent ID: 8675799

Claim:
A circuit for generating a clock data recovery phase locked indicator, the circuit comprising: an oversampling logic unit for executing an oversampling operation on data from a channel to generate a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock; an alternating current estimator coupled to the oversampling logic unit for executing a discrete cosine transform on the plurality of alternating current terms outputted from the oversampling logic unit to generate a first value, and executing a discrete sine transform on the plurality of alternating current terms outputted from the oversampling logic unit to generate a second value within a first predetermined time; and a logic processor coupled to the alternating current estimator for comparing a number of the first values and a number of the second values within a second predetermined time, and generating the clock data recovery phase locked indicator according to a comparison result.