Patent ID: 6972209

Claim:
A method of forming a multilayer semiconductor integrated circuit structure comprising the steps of: a) forming a first via stud of a stacked via-stud in a first interconnection level connecting a metal feature formed in a semiconductor substrate to a first metal interconnection line segment, said first via-stud and first metal interconnection line formed in a first interconnect dielectric layer including a low-k dielectric material; b) forming a second interconnection level above said first interconnection level, said second interconnection level comprising a second interconnect dielectric layer including low-k dielectric material and forming therein a second level integrated via-stud in conductive alignment with said first metal interconnection line segment, and a second metal interconnection line segment of rectangular shape at a selected location such that one end of the second metal line segment is above the first metal line segment of the same length and the width; c) forming a third interconnection level above said second interconnection level, said third interconnection level comprising a dielectric layer including low-k dielectric material and forming therein a third level integrated via-stud connecting said second metal interconnection line segment of rectangular shape at an opposite end thereof with a third metal interconnection line segment, said first, second and third integrated via-studs and said second metal line segment forming a stacked via-stud arrangement in said low-k dielectric layers with said second metal line segment comprising a cantilever structure.