Patent ID: 6991942

Claim:
A method of forming an MFIS array comprising: providing an SOI substrate having a silicon film overlying an insulating material; forming a gate oxide layer overlying the SOI substrate; depositing a gate layer overlying the gate oxide layer; forming a first hard mask overlying the gate layer; forming a second hard mask overlying the first hard mask; patterning the second hard mask to protect gate areas; applying and patterning photoresist to protect active areas; using the photoresist and the second hard mask to protect underlying material and etching through the first hard mask; the gate layer; the gate oxide layer and the SOI silicon film; etching through the second hard mask, the first hard mask and the gate layer; performing a P+ ion implantation through the gate oxide layer to dope exposed portions of the SOI silicon film and then stripping the photoresist; depositing CVD oxide and performing a partial back etch to expose the second hard mask and portions of the gate layer not protected by the second hard mask; etching to remove exposed regions of the gate layer; forming N+ source/drain regions adjacent to the gate areas; forming a P+ substrate region within the SOI silicon film where the exposed regions of the gate layer have been removed; depositing oxide and CMP polishing to expose the gate layer; etching to remove the exposed gate layer and the underlying gate oxide layer; depositing a high-k dielectric gate material followed by a ferroelectric gate material; polishing the ferroelectric gate material to form ferroelectric gates; depositing and patterning top electrodes overlying the ferroelectric gates to form word lines; depositing an oxide cap overlying the top electrodes; and forming electrical contacts through the oxide cap.