Patent ID: 7215595

Claim:
A memory device comprising: a pair of complementary bitlines including a first bitline and a second bitline; a bitline precharge block coupled between the first bitline and the second bitline; a sense amplifier coupled to both the first bitline and the second bitline; a sense amplifier precharge block coupled to the sense amplifier, the sense amplifier precharge block being activated independently from the bitline precharge block; an isolation block coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side; and control circuitry providing a bitline precharge signal to the bitline precharge block, a sense amplifier precharge signal to the sense amplifier precharge block, a sense amplifier enable signal to the sense amplifier and a select signal to the isolation block, wherein the control circuitry causes the sense amplifier to operate as a cache by: causing the select signal and the sense amplifier enable signal to be active while the bitline precharge signal and the sense amplifier precharge signal are inactive so that a differential signal from the pair of complementary bitlines will be held in the sense amplifier; and subsequently, causing the select signal to be inactive and the bitline precharge signal to be active while the sense amplifier enable signal remains active and the sense amplifier precharge signal remains inactive such that the pair of complementary bitlines are precharged while the sense amplifier continues to hold the differential signal.