Patent ID: 7554119

Claim:
An active matrix substrate comprising: a substrate; gate lines and auxiliary capacitive electrodes formed on said substrate; a first interlayer insulating film covering said gate lines and said auxiliary capacitive electrodes; source lines formed on said first interlayer insulating film to intersect with said gate lines; semiconductor layers constituting switching elements at intersections of said gate lines and said source lines; drain electrodes each respectively corresponding to one of said switching elements; a second interlayer insulating film covering said source lines, said semiconductor layers, and said drain electrodes; and pixel electrodes connected to said drain electrodes through contact holes formed in said second interlayer insulating film, wherein: said drain electrodes are opposed in part to said auxiliary capacitive electrodes with said first interlayer insulating film sandwiched in between, so as to form holding capacitances for said pixel electrodes, and are provided so as to extend to upper areas of said auxiliary capacitive electrodes, respectively; said contact holes are formed to reach said drain electrodes at first areas of said drain electrodes surrounded by second areas of said drain electrodes under which said auxiliary capacitive electrodes are formed, but not at the second areas of said drain electrodes under which said auxiliary capacitive electrodes are formed; said auxiliary capacitive electrodes have holes; at least outer edges of said holes of said auxiliary capacitive electrodes are opposed to said drain electrodes with said first interlayer insulating film sandwiched in between; and said contact holes are formed to reach said drain electrodes in areas corresponding to areas of said holes of said auxiliary capacitive electrodes.