Patent ID: 7074681

Claim:
A method of manufacturing a semiconductor component comprising: providing a substrate having a surface; forming by a non LOCal Oxidation of Silicon (LOCOS) process, a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the substrate; forming a drift region in the substrate; forming a channel region in the substrate, at least a portion of the drift region located between the channel region and the non-electrically conductive region; and forming an electrically floating region in the substrate and contiguous with the non-eletrically conductive region; wherein at least a portion of the electrically floating region is located between the non-electrically conductive region and the channel region, at least a portion of the electrically floating region is located laterally with respect to the non-electrically conductive region, and at least a portion of the electrically floating region is located underneath the non-electrically conductive region.