Patent ID: 8400859

Claim:
A method for refreshing a Dynamic Random Access Memory (DRAM) having built-in test (BIST) circuitry, comprising: in response to a start-up of the DRAM, using the BIST circuitry to identify a first plurality of rows of the DRAM, wherein the first plurality comprises rows that meet a data retention criteria at a first refresh rate but do not meet the data retention criteria at a low power refresh rate and to identify a second plurality of rows of the DRAM, wherein the second plurality comprises rows which meet the data retention at the low power refresh rate; storing addresses in the DRAM of the rows of the first plurality of rows; soring a count of each refresh request after a last refresh of the second plurality of rows in a counter; and in response to the DRAM determining that a refresh is to be performed: performing a refresh on the first plurality of rows of the DRAM but not the second plurality of rows if the count in the counter is below a first threshold; and performing a refresh on the first plurality of rows and the second plurality of rows of the DRAM and reset the counter if the count in the counter equals the first threshold.