Patent ID: 8115247

Claim:
A non-volatile semiconductor memory device, comprising: a semiconductor substrate; a floating gate formed above a gate insulating film covering the semiconductor substrate; an erasing gate formed above the floating gate with a insulating film being formed therebetween; and a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position adjacent to the floating gate and the erasing gate along a first lateral direction parallel to the surface of the substrate, the floating gate and the erasing gate insulated from the control gate by a first sidewall insulating film, wherein, with respect to an upper surface of the semiconductor substrate, both ends of the floating gate have a same height, and wherein along a second lateral direction, perpendicular to the first lateral direction and parallel to the surface of the substrate, a distance between the floating gate and the erasing gate at an edge of the floating gate is less than a distance between the floating gate and the erasing gate at a center of the upper surface of the floating gate.