Patent ID: 8114746

Claim:
A method, comprising: forming a layer stack above a semiconductor layer of a semiconductor device, said layer stack comprising an etch stop layer formed above said semiconductor layer and a first mask layer formed above said etch stop layer; patterning said first mask layer so as to obtain a mask feature; forming a spacer element on sidewalls of said mask feature; removing said mask feature selectively to said sidewall spacer element; providing a second mask layer having a first opening exposing a portion of said sidewall spacer element so as to define a channel area and drain and source areas and having a second opening so as to define a position and lateral size of an isolation structure; forming trenches in said semiconductor layer by using said sidewall spacer element and said second mask layer as an etch mask so as to form a fin in said semiconductor layer, said fin corresponding to said channel area; forming a gate electrode structure at least on sidewalls of said fin; and forming drain and source regions in said drain and source areas, said drain and source regions connecting to said fin.