Patent ID: 8178433

Claim:
A method of forming a metal oxide semiconductor structure comprising the steps of: providing a structure comprising at least one patterned gate stack and source and drain regions on opposing sides of the at least one patterned gate stack, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, a dielectric liner on at least sidewalls of said polysilicon gate conductor, and spacers on said dielectric liner and adjoining sidewalls of at least the polysilicon gate conductor; depositing a material stack comprising a conformal dielectric layer and a planarizing dielectric layer on the structure including atop the at least one patterned gate stack; removing portions of the conformal dielectric layer and planarizing dielectric layer to expose said dielectric cap; removing the exposed dielectric cap to expose the polysilicon gate conductor; converting the polysilicon gate conductor into a fully silicided metal gate, wherein a remaining portion of the conformal dielectric layer and the planarizing dielectric obstructs metal used to form the fully silicided gate from being introduced to the source and drain regions; removing the remaining portion of the conformal dielectric layer and a remaining portion of the planarizing dielectric after converting the polysilicon layer into the fully silicided metal gate to expose said source and drain regions; and saliciding said source and drain regions after removing the remaining portion of the conformal dielectric layer and the remaining portion of the planarizing dielectric to form silicided source and drain regions that have a thickness that is less than the fully silicided metal gate.