Patent ID: 8042032

Claim:
A Viterbi decoder used for VDSL2, comprising: a branch metrics computation and update module for computing the cost metric for each branch, adding the branch cost with the previous node cost, and finding the survival path by finding the minimum cost among all potential branches; an information sequence update and decision module for storing all the survival paths; and a decision and information retrieval module for finding one survival path with minimum cost among all the survival paths; wherein the metrics computation and update process for the metrics computation and update module being divided into four pipeline stages that correspond to the sub-groups (0, 1, 2, 3), (4, 5, 6, 7), (8, 9, A, B), and (C, D, E, F) of the VDSL2 trellis diagram; and wherein the choice of the system clock being based on the decoding speed requirement of overall VDSL2 system.