Patent ID: 7542330

Claim:
A static random access memory (SRAM) cell, comprising: a first p-channel field effect transistor (PFET) and a second PFET, the sources of said first and second PFETs connected to a high voltage terminal of a power source of a power supply, a drain of said first PFET connected to a first node, a drain of said second of second PFET connected to a second node, a gate of said first PFET connected to said second node and a gate of said second PFET connected to said first node; a first n-channel field effect transistor (NFET) and a second NFET, the sources of said first and second NFETs connected to a low voltage terminal of said power source, a drain of said first NFET connected to said first node, a drain of said second NFET connected to said second node, a gate of said first NFET connected to said second node and a gate of said second NFET connected to said first node; and a first field effect transistor (FET) pass gate and a second FET pass gate, a drain of said first FET pass gate connected to said first node and a drain of said second FET pass gate connected to said second node; a source of said first FET pass gate connected to a first bitline and a gate of said second FET pass gate connected to second bitline, gates of said first and second FET pass gates connected to a wordline, current conduction from said source to said drain of said first FET pass gate being different from current conduction from said drain to said source of said first FET pass gate and current conduction from said source to said drain of said second FET pass gate being different from current conduction from said drain to said source of said second FET pass gate.