Patent ID: 8350603

Claim:
A circuit comprising: a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate; a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate; a first second PMOS transistor having a first second PMOS drain, a first second PMOS source, and a first second PMOS gate; a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate; a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; a second second PMOS transistor having a second second PMOS drain, a second second PMOS source, and a second second PMOS gate; and an inverter having an inverter input and an inverter output; wherein the first PMOS gate is coupled to the first NMOS gate and the second PMOS gate; the first PMOS drain is coupled to the first NMOS drain, to the second second PMOS gate, and to the second NMOS gate; the first PMOS source is coupled to the first second PMOS drain; the first second PMOS source is configured to receive a supply voltage value; the second PMOS source is coupled to the second second PMOS drain; the second PMOS drain is coupled to the second NMOS drain and to the inverter input; and the inverter output is coupled to the first second PMOS gate.