Patent ID: 8140937

Claim:
A computer system comprising: a processor; a memory further comprising a first memory unit, the first memory unit further comprising more than one memory rank; a memory controller coupled to the processor and to the memory, the memory controller coupled to the memory unit with a rank select having a rank select signal unique to the each memory rank in the memory unit, the memory controller further comprising: a functional encoded rank select; an initialization encoded rank select; a multiplexer configured to select the functional encoded rank select or the initialization encoded ranks select and output an encoded rank select; a parity generator configured to generate a parity of the value of the encoded rank select; an initialization control configured to, during a memory initialization period: drive the initialization encoded rank select; cause the multiplexer to select the initialization encoded rank select; and cause a first rank select signal for a first memory rank and a second rank select signal for a second memory rank to be active at a particular time; the initialization control further configured, during functional reads and writes, to cause the multiplexer to select the functional encoded rank select; and an error checking and correcting (ECC) unit that receives the parity from the parity generator and which generates ECC bits that are stored in a memory rank having an active rank select signal.