Patent ID: 8420497

Claim:
A method of forming a semiconductor structure comprising: forming a plurality of conductive landing pads that touch an isolation structure, the plurality of conductive landing pads being spaced apart and having a plurality of top surfaces, the first isolation structure having a top surface; forming a first metallic layer that touches the top surface of the first isolation structure and the plurality of top surfaces of the plurality of conductive landing pads, the first metallic layer having a top surface; forming a dielectric layer that touches the top surface of all of the first metallic layer, the dielectric layer having a top surface; forming a second metallic layer that touches the top surface of all of the dielectric layer and lies directly over all of the first metallic layer, the second metallic layer having a top surface; forming a protective layer that touches the top surface of the second metallic layer, the protective layer being non-conductive and having a top surface; forming a non-conductive layer that touches the top surface of the isolation structure, the plurality of top surfaces of the plurality of landing pads, and the top surface of the protective structure; and etching the non-conductive layer, the protective layer, the second metallic layer, the dielectric layer, and the first metallic layer to expose the plurality of top surfaces of the plurality of conductive landing pads and form a semiconductor structure, the semiconductor structure having a first metallic structure that touches each of the plurality of conductive landing pads, a dielectric structure that touches a top surface of the first metallic structure, a second metallic structure that touches a top surface of the dielectric structure, and a protective structure that touches a top surface of the second metallic structure.