Patent ID: 7242684

Claim:
A system for switching packets in a high-speed switching environment, the system comprising: one or more memory structures; a plurality of input structures that are each operable to write to each of the one or more memory structures a first switching structure coupling the input structures to the one or more memory structures such that each of the input structures is operable to write to each of the one or more memory structures; a plurality of output structures that are each operable to: read from each of the one or more memory structures; and communicate a first portion of a packet to a first component of a communications network before an input structure has received a second portion of the packet from a second component of the communications network; and a second switching structure coupling the plurality of output structures to the one or more memory structures such that each of the output structures is operable to read from each of the one or more memory structures, the second switching structure being coupled to the one or more memory structures by a first number of links and being coupled to the plurality of output structures by a second number of links, the first number of links being twice or more the second number of links.