Patent ID: 8145923

Claim:
A method of minimizing power consumption in a device, the method comprising: providing a plurality of circuit blocks having circuits for performing functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal generated by a power control circuit and a plurality of corresponding first enable signals stored in first memory elements of the device, wherein a particular one of the first set of circuit blocks is disabled if a corresponding one of the plurality of first enable signals indicates that the particular one of the first set of circuit blocks is to participate in a power reduction mode, and the first power reduction signal specifies that the first set of circuit blocks is to be in the power reduction mode; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal generated by the power control circuit and a plurality of corresponding second enable signals stored in second memory elements of the device, wherein a particular one of the second set of circuit blocks is disabled if a corresponding one of the plurality of second enable signals indicates that the particular one of the second set of circuit blocks is to participate in the power reduction mode, and the second power reduction signal specifies that the second set of circuit blocks is to be in the power reduction mode.