Patent ID: 7880238

Claim:
A memory device comprising: a substrate including at least one device region; a first field effect transistor having a first threshold voltage, the first field effect transistor including a first active region present in the at least one device region of the substrate, the first active region comprising a first drain and a first source; and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region comprising a second drain and a second source separated by a second channel region, the second source and the first source are provided by a shared dopant region in the at least one device region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.