Patent ID: 7956663

Claim:
A delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, said delay circuit comprising: an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein said delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, said first transistor and said second transistor being connected in series with each other between said output section and one power supply such that a drain of the first transistor is connected to a source of the second transistor, and said delay inverter has a third transistor of a different channel type from said first transistor and said second transistor for one of a second charge and a second discharge, said third transistor being connected in parallel with said second transistor such that the drain of the first transistor is connected to a drain of the third transistor and the source of the second transistor, and said delay inverter has a fourth transistor and a fifth transistor of the same channel type as said third transistor for one of the first charge and the first discharge, said fourth transistor and said fifth transistor being connected in series with each other between said output section and the other power supply, and said delay inverter has a sixth transistor of the same channel type as said first transistor and said second transistor for one of the second charge and the second discharge, said sixth transistor being connected in parallel with one of said fourth transistor and said fifth transistor.