Patent ID: 8711597

Claim:
A three-dimensional memory array, comprising: a first macro cell comprising: a first three-terminal device; a first electrical connector coupled to the first three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal device; a first memory cell coupled to a second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis; a second macro cell comprising: a second three-terminal device; a fourth electrical connector coupled to the second three-terminal device, the fourth electrical connector extending along a fourth axis that is parallel to the first axis, the fourth electrical connector also extending along the second axis, the fourth electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the second axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the second axis and a fifth axis that is parallel to the third axis, the sixth electrical connector is electrically coupled to the third electrical connector; and an electrically insulating spacer coupled between the third electrical connector and the fourth electrical connector.