Patent ID: 8577942

Claim:
A circuit that processes cryptographic algorithms, where the cryptographic algorithm is a combination of nonlinear and linear transforms to ensure security, the circuit comprising: at least one electronic device that forms the nonlinear transforms; at least one electronic device that forms a linear transformation; a random number generator, and a control that outputs timing control signals for the electronic devices, wherein the electronic device that forms the nonlinear transformation receives XOR data indicating data obtained by XORing data of n bits (n≧1) with a first random number of n bits, the first random number of n bits, and a second random number of 1 bit as input signals, performs an XOR operation of the XOR data with the first random number to obtain the data of n bits, performs a predetermined logic operation using each bit of the data of n bits obtained, performs an XOR operation of a result of the logic operation with the second random number, outputs as an output signal a result of the XOR operation of the result of the logic operation with the second random number, receives the timing control signal that instructs the electronic device to output the output signal, and outputs the output signal upon receipt of a leading edge of the timing control signal, where the leading edge of the timing control signal is generated after state transitions of the other input signals to the electronic device are fully completed.