Patent ID: 7911000

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines extending to a first direction; a plurality of word lines extending to a second direction crossing with the first direction; a plurality of source lines extending to the second direction; a semiconductor layer formed in a U-shape on the semiconductor substrate in a cross section along the first direction; a first diffusion layer provided at an upper part of the U-shaped semiconductor layer; a second diffusion layer provided at a lower part of the U-shaped semiconductor layer; a body formed at an intermediate portion of the semiconductor layer between the first diffusion layer and the second diffusion layer, the body being in an electrically floating state, and accumulating or discharging an electric charge to store data; a first gate dielectric film provided on a first side surface of the body, the first side surface facing the first direction; a first gate electrode provided via the first gate dielectric film on the first side surface; a second gate dielectric film provided on a second side surface of the body, the second side surface being provided on an opposite side of the first side surface of the body and facing the first direction; a second gate electrode provided on the second side surface via the second gate dielectric film, and insulated from the first gate electrode; a bit line contact electrically connecting the bit line to one of the first and the second diffusion layers; and a source line contact electrically connecting the source line to the other one of the first and the second diffusion layers, wherein the body, the first diffusion layer, and the second diffusion layer form memory cells, and a plurality of the memory cells adjacent in the first direction alternately share the bit line contact and the source line contact.