Patent ID: 7135367

Claim:
A manufacturing method of a semiconductor device in which a first and a second element isolation structures are formed on a semiconductor substrate, and transistors are included at active regions defined by the first element isolation structure, and a resistance element is included on the second element isolation structure, comprising the steps of: forming a semiconductor film on the semiconductor substrate including on the second element isolation structure, and processing the semiconductor film so that the semiconductor film is respectively left on the second element isolation structure and on the active regions to form a resistor and gate electrodes; forming a first mask exposing the active regions, doping a first impurity into both sides of the gate electrodes at the active regions, and thereafter, removing the first mask; forming a second mask exposing the resistor, doping a second impurity into the resistor, and thereafter, removing the second mask; forming an insulating film on a whole surface including the resistor and the gate electrodes, just after the second mask is removed; and processing the insulating film to leave the insulating film so as to cover a part of an upper surface of the resistor, and to cover side surfaces of the gate electrodes.