Patent ID: 8139790

Claim:
An integrated circuit, receiving a first signal and a first opposite signal from a microphone via a first node and a first opposite node, comprising: a biasing circuit, coupled between the first node, the first opposite node, a second node, and a second opposite node, biasing the microphone with a first voltage source and a second voltage source, filtering the first signal to generate a second signal at the second node, filtering the first opposite signal to generate a second opposite signal at the second opposite node, and comprising: a first resistor, coupled between the first voltage source and the first node; a first capacitor, coupled between the first node and the second node; a first load element, coupled between the second node and a third voltage source; a second resistor, coupled between the first opposite voltage source and the first opposite node; a second capacitor, coupled between the first opposite node and the second opposite node; and a second load element, coupled between the second opposite node and the third voltage source; and a buffering circuit, coupled between the second node, the second opposite node, a third node, and a third opposite node, buffering the second signal to generate a third signal at the third node, and buffering the second opposite signal to generate a third opposite signal at the third opposite node; wherein the buffering circuit comprises: a first amplifier, having an positive input terminal coupled to the second node, a negative input terminal coupled to the third node, and an output terminal coupled to the third node; and a second amplifier, having an positive input terminal coupled to the second opposite node, a negative input terminal coupled to the third opposite node, and an output terminal coupled to the third opposite node.