Patent ID: 8539403

Claim:
A computer-implemented method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element, wherein the first and second memory elements are functionally configured to have different values in at least one scenario; selecting the second memory element to be a dominant memory element over the first memory element; modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal, wherein said modifying is performed by a computer; wherein said modifying comprises: computing a combinatorial function indicative of when the values of the output signals of the first memory element and the dominant memory element are equal; and replacing usages of the output signal of the first memory element with usages of a combinatorial logic operative to provide the output signal of the dominant memory element in response to the indication by the combinatorial function and otherwise operative to provide the output signal of the first memory element; and whereby a reduction in observabiltiy of the first memory element in the design is achieved.