Patent ID: 8704293

Claim:
A three-dimensional semiconductor device, comprising: a stacked structure including a plurality of conductive layers stacked on a substrate, the plurality of conductive layers including at least a lowermost conductive layer and an uppermost conductive layer stacked on the substrate, and each of the lowermost conductive layer and the uppermost conductive layer including at least: top and bottom surfaces parallel to the substrate, a first sidewall extending along a first direction, and a second sidewall extending along a second direction perpendicular to the first direction, each of the first and second sidewalls connecting the bottom surface to the top surface along a third direction perpendicular to the first and second directions; and vertical channel structures penetrating the stacked structure, each vertical channel structure including a memory layer and a semiconductor pattern, and penetrating at least two of the plurality of conductive layers in the stacked structure, wherein a distance along the first direction between respective second sidewalls of the uppermost conductive layer and the lowermost conductive layer is smaller than a distance along the second direction between respective first sidewalls of the uppermost conductive layer and the lowermost conductive layer, the first and second directions defining a plane parallel to a surface supporting the substrate and the third direction being perpendicular to the surface supporting the substrate.