Patent ID: 8008216

Claim:
A method of fabricating an integrated circuit, comprising the steps of: providing a substrate; forming field oxide in said substrate; forming an n-well in said substrate; forming a p-well in said substrate; forming a gate dielectric layer on a top surface of said p-well; forming a sacrificial layer of material on a top surface of said gate dielectric layer; exposing said sacrificial layer to a nitridation source; removing said sacrificial layer; forming an n-channel MOS transistor in said p-well by a process comprising the steps of: forming a first gate structure on a top surface of said gate dielectric; forming n-type lightly doped source and drain regions in said p-well adjacent to said first gate structure; forming a first set of gate sidewall spacers abutting lateral surfaces of said first gate structure; forming n-type source and drain regions in said p-well adjacent to said first gate structure and contacting said n-type lightly doped source and drain regions; and forming a first set of silicide regions on, and in contact with, top surfaces of said n-type source and drain regions and said first gate structure; forming a p-channel MOS transistor in said n-well by a process comprising the steps of: forming a second gate structure on a top surface of said gate dielectric layer; forming p-type lightly doped source and drain regions in said n-well adjacent to said second gate structure; forming a second set of gate sidewall spacers abutting lateral surfaces of said second gate structure; forming p-type source and drain regions in said n-well adjacent to said second gate structure and contacting said p-type lightly doped source and drain regions; and forming a second set of silicide regions on, and in contact with, top surfaces of said p-type source and drain regions and said second gate structure; forming a pre-metal dielectric layer stack on said n-channel transistor and said p-channel transistor; forming contacts in said pre-metal dielectric layer stack on said n-type source and drain regions, said p-type source and drain regions, said first gate structure and said second gate structure; forming a first intra-level dielectric layer on said contact; and forming metal interconnect structures whereby the metal interconnect structures connect to and overlap said contacts.