Patent ID: 8260994

Claim:
An integrated circuit, comprising: an on-chip communication path connected to a plurality of on-chip functional modules, wherein at least one of the on-chip functional modules is capable of issuing packets; and an interface implemented on-chip and having at least one chip-side port connected to the communication path and configured to transmit the packets in parallel across a plurality of pins, the interface further having first and second circuit-side ports each with a reduced number of pins configured to communicate the packets off-chip via the reduced number of pins, the interface including a pair of dedicated power down signal chip-side pins each connected to one of a pair of dedicated power down signal circuit-side pins, the dedicated power down signal chip-side pins and the dedicated power down signal circuit-side pins configured to transparently transmit a power down request signal from an on-chip functional module across the interface to an off-chip circuit connected to the interface and to transmit a power down acknowledge signal from the off-chip circuit across the interface transparently to the on-chip functional modules, and a set of dedicated interrupt chip-side pins each connected to one of a set of dedicated interrupt circuit-side pins, the dedicated interrupt chip-side pins and the dedicated interrupt circuit side pins configured to transmit interrupt signals from an off-chip circuit connected to the interface transparently to at least one of the on-chip functional module, wherein the interface further comprises circuitry configured to chop a packet transmitted from the communication path on the plurality of pins on the at least one chip-side port so as to be transmitted in a plurality of cycles on the reduced number of pins on the first circuit-side port.