Patent ID: 8216893

Claim:
A method of fabricating a transistor device, comprising: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor substrate by a gate dielectric; reactive ion etching select regions of the semiconductor substrate on opposite sides of the gate conductor to form recessed regions in the substrate spaced apart by a channel region having undercut areas that extend under the gate conductor; forming a stressed material embedded in the undercut areas of the channel region under the gate conductor by depositing the stressed material across the recessed regions of the substrate and the gate conductor, anisotropically etching the stressed material using reactive ion etching to remove a portion of the stressed material from above the substrate, and isotropically etching the stressed material to remove the stressed material from all areas except within the undercut areas of the channel region; and epitaxially growing source and drain regions in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.