Patent ID: 7834683

Claim:
A controlled voltage circuit for reducing variations in CMOS delay, the controlled voltage circuit comprising: a voltage supply; a controlled supply comprising a controlled voltage for controlling voltage variations at the controlled supply; a constant current source, having a first terminal connected to the voltage supply; a unity gain operational amplifier, having a positive input node connected to a second terminal of the constant current source, a negative input node connected to an output of the unity gain operational amplifier, and the output of the unity gain operational amplifier connected to the controlled supply; a controlled voltage signal line, connected between the second terminal of the constant current source and the positive input node of the unity gain operational amplifier; and a plurality of transistors, comprising of a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series; wherein an input terminal of the controlled voltage circuit is at the constant current source, and an output terminal of the controlled voltage circuit is at the controlled supply; the voltage of the controlled voltage signal line is adjusted for compensating losses due to supply voltage, temperature and process variations; and the output of the unity gain operational amplifier is to control the controlled voltage circuit; wherein the first transistor is a P-channel MOSFET; a source terminal of the first transistor is connected to the second terminal of the constant current source and the positive input node of the unity gain operational amplifier; a gate terminal of the first transistor is connected to a source/drain joint terminal of the third transistor and the fourth transistor connected in series.