Patent ID: RE40168

Claim:
A semiconductor integrated circuit comprising: an adjusted circuit in which a first bias current flows, a slew rate of said adjusted circuit being dependent on said first bias current; a replica circuit of said adjusted circuit in which a second bias current flows, a value of said second bias current being substantially equal to that of said first bias current; an evaluation circuit configured to repeat a cycle of processing, said cycle of processing including: resetting an output thereof; obtaining a difference between first and second voltages at given times, said first voltage being one at an output of said replica circuit at a time when a first time interval has elapsed after a given voltage having been step-inputted to said replica circuit, said second value being one at said output of said replica circuit at a time when second time interval has elapsed after a voltage equal to said given voltage having been step-inputted to said replica circuit, said second time interval being different from said first time interval; and successively summing said differences; a comparator circuit for comparing a value obtained by said successively summing with a reference value; and a bias adjustment circuit for changing said second bias current according to a comparison result of said comparator circuit at every said given times.