Patent ID: 7288975

Claim:
A method of generating a clock signal for a digital circuit, comprising: determining that a first clock signal supplying said digital circuit has failed at a downstream node of a clock distribution path supplied by an output of a clock generator, wherein said first clock signal is derived from said output of said clock generator, wherein said determining further determines whether or not said output of said clock generator has failed; responsive to said determining that said first clock signal has failed, supplying a second clock signal in place of said first clock signal so that said digital circuit is operated, wherein said supplying said second clock signal is further performed responsive to determining that said output of said clock generator has failed; setting an initial condition of said clock generator so that said clock generator initially generates said first clock signal at or below a predetermined frequency at which said digital circuit is guaranteed to operate; restarting said clock generator at said predetermined frequency; and restoring said first clock signal to said digital circuit, whereby said supplying said second clock signal is terminated.