Patent ID: 7567450

Claim:
A read-only memory (ROM) comprising: a ROM core unit including a plurality of ROM core groups, each ROM core group including a plurality of transistors coupled to a plurality of word lines and a plurality of bit lines; a word line decoder to select a desired word line from the word lines; a column decoder to select a desired bit line from the bit lines; one or more charge units, each charge unit having a plurality of transistors that are coupled to one of a plurality of dummy bit lines, wherein the dummy bit lines are selected by one of the bit lines, the plurality of transistors of each charge unit being deactivated; a common reference voltage generator coupled to the dummy bit lines to generated a common reference voltage; and a plurality of sense amplifiers, each coupled to a corresponding ROM core group and the common reference voltage generator, wherein the common reference voltage generator generates the common reference voltage in response to a voltage charged through the dummy bit lines and transfers the generated common reference voltage to the sense amplifiers.