Patent ID: 7231569

Claim:
A scan flip-flop circuit comprising: an input stage receiving, selecting between, and outputting either a normal logic signal or a scan logic signal in accordance with an operation mode for the scan flip-flop circuit; a flip-flop receiving either the normal logic signal or the scan logic signal selected by the input stage, and outputting in accordance with a clock signal a first logic signal from a first flip-flop output terminal; an output stage receiving the first logic signal and comprising first and second output terminals; wherein a signal output from the first output terminal is identical to the normal logic signal received in the input stage, and a signal output from the second output terminal maintains a high logic value when the scan flip-flop circuit operates in a normal mode, and wherein a signal output from the first and second output terminals are identical to the scan logic signal received in the input stage when the scan flip-flop circuit operates in a scan mode.