Patent ID: 7324396

Claim:
A semiconductor memory device comprising: a. a plurality of wordlines and a plurality of bitlines arranged in an array; b. a plurality of storage cells at certain intersections of wordlines and bitlines; c. a plurality of sense amplifiers, wherein each sense amplifier is connected to either a first pair of bitlines or to a second pair of bitlines depending on which of the plurality of wordlines is activated, in order to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersections of a single one of the plurality of wordlines with said first pair of bitlines or with said second pair of bitlines, respectively; and d. a multiplexer connected to each sense amplifier, to said first pair of bitlines and to said second pair of bitlines, wherein the multiplexer selects either said first pair of bitlines or said second pair of bitlines for connection to the associated sense amplifier.