Patent ID: 7443734

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix; a storage section which stores an initial value of a write voltage corresponding to a write operation and a correction value for correcting the write voltage; and a voltage generating circuit which generates a word line write voltage in a first write operation on a first memory cell in the memory cell array or a second write operation on a second memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage stored in the storage section; wherein the voltage generating circuit, in the first write operation, generates a first high voltage supplied to the first memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage and further generates voltages higher than the first high voltage in increments of a first step voltage, and in the second write operation, generates a second high voltage supplied to the second memory cell in the memory cell array on the basis of the initial value and correction value of the write voltage and further generates voltages higher than the second high voltage in increments of a second step voltage, and the first step voltage is higher than the second step voltage.