Patent ID: 7554365

Claim:
A clock switching circuit for switching a first clock signal and a second clock signal, comprising: a clock switching control device generating a clock switching storing signal (mux_sel), a first enable signal (clk_a_gat_en) and a second enable signal (clk_b_gat_en) according to a clock switching signal (clk_sel); a multiplexer determining whether to output a third clock signal (clk_a_gated) or a fourth clock signal (clk_b_gated) according to the clock switching storing signal; a first clock gate control unit receiving the first clock signal and determining whether to output the third clock signal (clk_a_gated) corresponding to the first clock signal and a first gate enable signal (clk_a_gat_en_f) according to the first enable signal (clk_a_gat_en); a second clock gate control unit receiving the second clock signal and determining whether to output the fourth clock signal (clk_b_gated) corresponding to the second clock signal and a second gate enable signal (clk_b_gat_en_f) according to the second enable signal (clk_b_gat_en); a first synchronization device synchronizing the first gate enable signal to generate a first feedback enable signal (syncback_clk_a_gat_en) to the clock switching control device according to a reference clock (clk); and a second synchronization device synchronizing the second gate enable signal to generate a second feedback enable signal (syncback_clk_b_gat_en) to the clock switching control device according to the reference clock (clk).