Patent ID: 7785938

Claim:
A manufacturing method of a semiconductor integrated circuit, comprising: forming a first element formation layer including a first opening and a first semiconductor device over a first substrate, the first semiconductor device including a first semiconductor layer and first insulating layers sandwiching the first semiconductor layer; forming a release layer over a second substrate; forming a second element formation layer including a second opening and a second semiconductor device over the release layer, the second semiconductor device including a second semiconductor layer and second insulating layers sandwiching the second semiconductor layer; separating the second element formation layer from the second substrate; disposing the second element formation layer over the first element formation layer; and after disposing the second element formation layer over the first element formation layer forming a wiring in each of the first opening and the second opening, and electrically connecting the first element formation layer and the second element formation layer, wherein the first opening and the second opening overlap each other, and wherein the wiring is formed by dropping a conductive material in at least one of the first opening and the second opening.