Patent ID: 7682889

Claim:
A method of manufacturing an insulated gate field effect transistor, the method comprising: providing a substrate having a first major surface having a low-doped region at the first major surface, the low-doped region having a concentration of less than 5×10 14 cm −3 at the first major surface; forming gate trenches extending from the first major surface; forming trench insulator on a base and sidewalls of the gate trenches; implanting dopants of a first conductivity type at the base of the trenches; implanting a body implant of second conductivity type opposite to the first conductivity type in the low-doped regions between the gate trenches; carrying out a diffusion step to form an insulated gate field effect transistor structure in which the body implant diffuses towards the substrate in the low-doped region to form a p-n junction above a drain region and between a body region and the drain region, wherein the body region is doped to have the second conductivity type and the drain region is doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the gate trenches; and forming source regions at the first major surface adjacent to the gate trenches.