Patent ID: 6939752

Claim:
A method of fabricating a silicon-on-insulator (SOI) transistor in an integrated circuit (IC), the method comprising: fabricating a first source region of the silicon-on-insulator (SOI) transistor; fabricating a second source region of the silicon-on-insulator (SOI) transistor; fabricating a body contact region, the body contact region electrically coupled to a body region of the silicon-on-insulator (SOI) transistor; and fabricating a gate configured to control a current flow between the first and second source regions and a drain region of the silicon-on-insulator (SOI) transistor; fabricating a first isolation region, the first isolation region disposed between the first source region and the body contact region; and fabricating a second isolation region, the second isolation region disposed between the second source region and the body contact region.