Patent ID: 8495252

Claim:
A method for implementing PCI-Express (PCIE) memory domains for single root virtualized devices in a computer system comprising: using a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) to associate MMIO domains with PCI memory Virtual Function (VF) Base Address Register (BAR) spaces; providing one said MDD for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to a PCI host bridge (PHB); providing in said MDD a base address register defining the starting address in PCIE memory of a set of contiguous MMIO domains; providing in said MDD a size register defining the size of a region of contiguous PCI memory encompassing said MMIO domains; and providing in said MDD a programmable register containing an integer value, n, for dividing the totality of the PCIE memory address space determined by the Base Address Register into n MMIO domains of size 1/nth of said region size.