Patent ID: 7081673

Claim:
An interconnect structure comprising at least one conducting metal feature on a substrate, said substrate further comprising an interlayer dielectric layer surrounding said conducting metal feature, a multilayered dielectric diffusion barrier layer that is a barrier to metal diffusion and is comprised of at least two sublayers where at least one sublayer is an air barrier sublayer which prohibits air permeation and at least another sublayer is a low-k sublayer that is comprised of Si v N w C x O y H z where 0.1≦v≦0.8, 0≦w≦0.8, 0.05x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8, and v+w+x+y+z=1, and an interlayer dielectric that is comprised of a line level dielectric and a via level dielectric.