Patent ID: 7971114

Claim:
A method for testing a random-access memory (RAM) in an electronic device having a processor, the processor writing and/or reading values to/from the RAM via a data bus and an address bus of the electronic device, the method comprising: (a) performing a write and read test of the RAM by writing random values into storage locations corresponding to physical addresses of the RAM, reading the random values from the storage locations, and comparing the random values, to determine whether the RAM is able to be written and read normally; (b) performing a walking 1's test across the data bus by writing first particular values into the storage locations corresponding to the physical addresses of the RAM, reading the first particular values from the storage locations, and comparing the first particular values, wherein only one bit of each first particular value is set to “1”, and all other bits is set to “0,” to confirm whether each bit location of the data bus is able to hold a 1 value; (c) performing a walking 0's test across the data bus by writing second particular values into the storage locations corresponding to the physical addresses of the RAM, reading the second particular values from the storage locations, and comparing the second particular values, wherein only one bit of each second particular value is set to “0” and all other bits is set to “1,” to confirm whether each bit location of the data bus is able to hold a 0 value; (d) performing a walking 1's test across the address bus by writing random values into storage locations corresponding to first memory addresses of the RAM, reading the random values from the storage locations, and comparing the random values, wherein only one bit of each first memory address is set to“1” and all other bits is set to “0,” to confirm whether each bit location of the address bus is able to hold a 1 value; (e) performing a walking 0's test across the address bus by writing random values into storage locations corresponding to second memory addresses of the RAM, reading the random values from the storage locations, and comparing the random values, wherein only one bit of each second memory address is set to“0” and all other bits is set to “1,” to confirm whether each bit location of the address bus is able to hold a 0 value; (f) performing a write and read test to random blocks in the storage locations of the RAM by reading a value which is stored from the beginning of a storage location corresponding to a resource address, writing the value into a storage location corresponding to a destination address from the beginning of the storage location, reading the value from the beginning of the storage location corresponding to the destination address, and comparing the two read values, to determine whether the random blocks in the storage locations of the RAM are able to be write and read normally; and (g) outputting a final results of all test steps from (a) to (f) as to whether the RAM is in an operable status or not.