Patent ID: 7859898

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, the first memory cell being connected to a first word line and a first bit line, the second memory cell being disposed adjacent to the first memory cell and connected to the first word line, the third memory cell being disposed adjacent to the first memory cell and connected to a second word line and the first bit line, and the fourth memory cell being disposed adjacent to the third memory cell and connected to the second word line; a write circuit which writes lower bit data into the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell, and upper bit data into the first memory cell and the second memory cell in this order; a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the third memory cell; and a readout circuit which reads the first memory cell by use of the judgment potential corrected by the judgment potential correction circuit.