Patent ID: 8255703

Claim:
An apparatus, configured to perform a hash operation, the apparatus comprising: an atomic hash instruction, disposed within a microprocessor, configured to direct said microprocessor to perform the hash operation, wherein the hash operation is accomplished on one or more message blocks, and wherein said microprocessor translates said atomic hash instruction into first micro instructions and second micro instructions, said atomic hash instruction comprising: an opcode field, configured to prescribe that said microprocessor accomplish the hash operation and indicate whether the hash operation has been interrupted by an interrupting event; and a hash mode field, coupled to said opcode field, configured to prescribe that said microprocessor accomplish the hash operation according to a prescribed hash mode; wherein said microprocessor comprises: an integer unit, configured to operate in parallel with a hash unit, wherein said hash unit executes said first micro instructions to perform a hash of one or more message blocks, and wherein said integer unit executes said second micro instructions to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation.