Patent ID: 7572682

Claim:
A method of forming a semiconductor structure comprising: forming at least one line opening and at least one combined via and line opening in an interconnect dielectric material, said at least one combined via and line opening is formed by a via first and then line process; forming a first diffusion barrier layer having a first thickness within at least both of said openings; protecting the first diffusion barrier layer located within said at least one line opening, said protecting comprising forming a patterned material stack comprising, from top to bottom, an oxide layer and an organic planarizing material; forming a second diffusion barrier layer at least within said at least one combined via and line opening, said second diffusion barrier layer having a second thickness that is greater than the first; unprotecting the at least one line opening; and forming a third diffusion barrier having a third thickness that is greater than the first thickness on at least exposed horizontal surfaces within said at least one line opening, said third diffusion barrier is also formed on exposed horizontal surfaces within said at least one combined via and line opening which horizontal surfaces are provided by an angled gaseous bombardment process and said horizontal surfaces are not with said via, said third diffusion barrier and said second diffusion barrier forming a continuous diffusion barrier within the at least one combined via and line opening which is thicker than the underlying first diffusion barrier layer; forming a conductive material within said openings, wherein at least one fuse element is formed within said at least one line opening and at least one anti-fuse element is formed within said at least one combined via and line opening, wherein hillocks form in said at least one fuse element during operation and said first diffusion barrier located on said sidewalls of said at least one line opening is ruptured to expose said interconnect dielectric material.