Patent ID: 7835176

Claim:
A circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO) comprising: a plurality of SRAM base blocks connected together in a chain; each of said plurality of SRAM base blocks including an eight-transistor (8T) SRAM cell; said 8T SRAM cell being an unmodified 8T SRAM cell; a logic function coupled to said SRAM cell and to a local evaluation circuit coupled to said SRAM cell; said logic function of each of said plurality of SRAM base blocks receiving a read control signal input, a wordline input and a reset signal input; and said local evaluation circuit of each of said plurality of SRAM base blocks providing a wordline output; said reset signal and said read control signal input being applied in parallel to each of said plurality of SRAM base blocks; said wordline output of said SRAM base blocks being applied to said wordline input of a next one of said SRAM base blocks in said chain, and said wordline output of a last one of said plurality of SRAM base blocks in said chain providing a feedback signal coupled to said wordline input of a first one of said plurality of SRAM base blocks; and the dual-mode SRAM PSRO includes a write-through mode of operation responsive to said read control signal input, with an output frequency being determined by write-through performance of the 8T SRAM cell; and a read performance mode of operation responsive to said read control signal input, with the output frequency being determined by read performance of the 8T SRAM cell.