Patent ID: 8605719

Claim:
A circuit comprising: a plurality of processing circuits, each configured to process messages; a plurality of source circuits, each configured to generate the messages, each of said messages can be processed by any one of said plurality of processing circuits; and a network coupled between the plurality of processing circuits and the plurality of source circuit operative to select by which of the processing circuits the messages will be processed, the network comprising a plurality of distributor circuits, each distributor circuit having a plurality of source side interfaces and a plurality of consumer side interfaces, each distributor circuit being configured to select over which of the consumer side interfaces messages from the source side interfaces will be transmitted towards the processor circuits, based at least partly on signals from the consumer side interfaces that indicate a current ability to forward the messages via the consumer side interfaces and not based on the content of the message; wherein said source circuits are coupled to source side interfaces of a first plurality of the distributor circuits in the network and said processing circuits are coupled to consumer side interfaces of a second plurality of distributor circuits in the network, the consumer side interfaces of the distributor circuits in the first plurality being coupled directly or indirectly to the source side interfaces of the distributor circuits in the second plurality, with a connectivity such that at least two of the source circuits that are coupled to different ones of the distributor circuits in the first plurality are both coupled to all of said plurality of processing circuits via the distributor circuits of the second plurality; and wherein the circuit comprises first buffer memory circuits coupled to respective ones of the source side interfaces of the at least one of the distributor circuits, each first buffer memory circuit being configured to generate requests to supply messages to the source side of the distributor circuit dependent on whether the first buffer memory circuit has buffered one of the messages.