Patent ID: 7705655

Claim:
A circuit comprising: an input buffer circuit comprising: a first transistor having a base that is operable to receive a first input signal; a second transistor having a base that is operable to receive a second input signal, and wherein the second transistor has an emitter that is coupled directly to an emitter of the first transistor; and a third transistor having a base that is coupled to a first reference voltage, wherein the third transistor has an emitter that is directly coupled to the emitter of the first transistor and directly coupled to the emitter of the second transistor, wherein the third transistor has a collector that is directly coupled to a collector of the second transistor, wherein the third transistor is operable to control the first and second transistors, wherein the third transistor enables both the first transistor and the second transistor to receive single-ended input signals and differential input signals, wherein, when operating in a single-ended input mode, the first transistor is operable to receive a single-ended input signal and the second transistor is turned off, and wherein, when operating in a differential input mode, both of the first and second transistors are operable to receive differential input signals and the third transistor is turned off.