Patent ID: 8239441

Claim:
A method for performing leading zero estimation during an unfused multiply add operation, the method comprising: receiving, by an fused/unfused multiply adder, a plurality of terms x and y, wherein the terms x and y are usable in performing the unfused multiply add operation of (A*B)+C, and wherein each of the plurality of terms x and y is based on previously truncated terms s and t and a shifted C term, wherein the terms s and t are based on a product of A*B; calculating, by a leading zero anticipator (LZA), a first leading zero estimation based on the plurality of terms; determining if near total catastrophic cancellation has occurred, comprising determining if a most significant bit of a result of the computation (A*B)+C is proximate to least significant bits of C and a product of A and B; determining one or more of a plurality of values MSB, L, S, M, Xs, and Xt, wherein: MSB is the value of the most significant bit of A*B; L is a carry in from a right most number of bits of the terms s and t; S is a rounding bit of the terms s and t; M is a negate bit of the terms s, t, and the shifted C term; and Xs and Xt are most significant truncated bits of s and t, respectively; generating a second leading zero estimation based on the first leading zero estimation and one or more of the plurality of values MSB, L, S, M, Xs and Xt if the near total catastrophic cancellation has occurred, wherein the second leading zero estimation is a modified version of the first leading zero estimation; wherein the second leading zero estimation is usable in performing the unfused multiply add operation.