Patent ID: 8199597

Claim:
A semiconductor memory device comprising: first and second memory cell arrays next to each other in a first direction, comprising a plurality of memory cells and reference cells; a first area next to the first memory array in a second direction orthogonal to the first direction; a second area next to the first memory array on the side opposite to the first area in the second direction; a third area next to the second memory cell array in the second direction, and next to the first area in the first direction; a fourth area next to the second memory cell array on a side opposite to the third area in the second direction, and next to the second area in the first direction; a first sense amplifier in the first area, configured to supply a read current to a first memory cell in the first memory array while supplying a reference current to a first reference cell in the second memory cell array via the third area; and a first current sink in the fourth area, configured to sink the read current of the first memory cell via the second area while sinking a reference current of the first reference cell, wherein the first sense amplifier is configured to sense a memory data of the first memory cell based on the read current and the reference current.