Patent ID: 7508894

Claim:
A phase adjusting circuit for generating a phase adjusting value based on a phase difference of a target clock signal and an input signal, the phase adjusting circuit comprising: a phase-frequency detector configured to generate a first control signal and a second control signal by comparing a phase of the input signal with a phase of the target clock signal; a clock generator configured to generate a reference clock; a counter connected to the phase-frequency detector and the clock generator and configured to generate a first counting value by counting a number of cycles of the reference clock during a duration of the first control signal, and to generate a second counting value by counting the number of cycles of the reference clock during a duration of the second control signal; and a decision logic circuit connected to the counter and configured to: generate a third counting value based on the first counting value and the second counting value, calculate a sum of a plurality of the third counting values, if a number of the plurality of the third counting values is greater than a predetermined number of cycles, provide the phase adjusting value, wherein the phase adjusting value is set to zero if the sum is within a specified range, and is set based on the sum if the sum is outside the specified range.