Patent ID: 8659055

Claim:
A semiconductor device comprising: a substrate; a first n-type semiconductor layer; a p-type semiconductor layer; a second n-type semiconductor layer; a drain electrode; a source electrode; a gate electrode; and a gate insulation film, wherein the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer are laimiated at an upper side of the substrate in this order, the drain electrode is in ohmic-contact with the first n-type semiconductor layer, the source electrode is in ohmic-contact with the second n-type semiconductor layer, an opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer to an upper part of the first n-type semiconductor layer is formed at a part of the p-type semiconductor layer and a part of the second n-type semiconductor layer, the gate insulation film is formed so as to cover the opening portion to be filled or the notched portion, the gate electrode is arranged so as to fill the opening portion to be filled or the notched portion via the gate insulation film and is in contact with an upper surface of the first n-type semiconductor layer, side surfaces of the p-type semiconductor layer, and side surfaces of the second n-type semiconductor layer at inner surfaces of the opening portion to be filled or at a surface of the notched portion via the gate insulation film, the p-type semiconductor layer has a positive polarization charge at a first n-type semiconductor layer side in a state where a voltage is applied to none of the drain electrode, the source electrode, and the gate electrode, and the semiconductor device satisfies the following Equation (A) L ch > 2 ⁢ ɛ s ⁡ ( V bi + ⁢ V B ) qN a ⁡ ( 1 + N a N d ⁢ ⁢ 1 ) + 2 ⁢ ɛ s ⁢ V bi qN a ⁡ ( 1 + N a N d ⁢ ⁢ 2 ) ( A ) N d1 : impurity concentration of first n-type semiconductor layer (cm −3 ) N d2 : impurity concentration of second n-type semiconductor layer (cm −3 ) N a : impurity concentration of p-type semiconductor layer (cm −3 ) L ch : thickness of p-type semiconductor layer (cm) q: elementary charge (elementary electric charge) (C) ε s : permittivity of semiconductor layer (F/cm) V bi : built-in-potential (V) V B : withstand voltage of semiconductor device (V).