Patent ID: 7998809

Claim:
A method of forming a floating gate region comprising the acts of: providing a first insulating layer over a substrate; providing a conductive layer over the first insulating layer; forming a trench extending through the conductive layer and the first insulating layer and into the substrate; providing a second insulating layer over the conductive layer and within the trench; and planarizing the second insulating layer and any intermediate layers to remove all of the second insulating layer that is above the conductive layer, wherein the process used for planarization is a chemical mechanical planarization process that has characteristics which cause the planarization to stop when it reaches the conductive layer, wherein the floating gate region comprises a portion of the conductive layer which remains after the trench is formed and upon which the planarization stops, and wherein the second insulating layer within the trench forms an isolation region corresponding to the floating gate region.