Patent ID: 8159831

Claim:
A PCB (printed circuit board) for manufacturing a semiconductor package, the PCB comprising: a plurality of semiconductor package unit frames; a scribe lane dividing the plurality of semiconductor package unit frames; and a first printed circuit pattern for plating directly connected to a plurality of bond fingers on the semiconductor package unit frames and disposed to cross the scribe lane between adjacent semiconductor package unit frames, wherein each semiconductor package unit frame comprises: a plurality of via lands disposed closer to the center of the semiconductor package unit frame than a set of the plurality of bond fingers corresponding to the semiconductor package unit frame; a plurality of second printed circuit patterns directly connecting the set of the plurality of bond fingers to the plurality of via lands, and wherein the plurality of bond fingers directly contact the first printed circuit pattern for plating and are connected to the via lands of semiconductor package unit frames through the second printed circuit patterns, such that the bond fingers are disposed between the first printed circuit pattern for plating and the plurality of via lands in a corresponding semiconductor package unit frame.