Patent ID: 8198698

Claim:
A semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first MISFET formed in the first region; a first capacitance element formed over the second region; a plurality of grooves formed in the semiconductor substrate and embedded with an insulating material; a first active region formed in the first region of the semiconductor substrate and defined by the grooves; a first gate electrode of the first MISFET formed over the first active region; a first insulating film formed over the first and second regions so as to cover the first gate electrode; a first metal pattern and a second metal pattern formed over the first insulating film of the second region; and a third metal pattern substantially surrounding the first and second metal patterns and to be connected to a fixed potential, wherein the first capacitance element includes the first metal pattern as one electrode and the second metal pattern as another electrode, wherein a plurality of second active regions defined by the grooves are formed in the second region of the semiconductor substrate below the first capacitance element, wherein a plurality of first conductor patterns in the same layer as that of the first gate electrode are formed over the second region of the semiconductor substrate below the first capacitance element, wherein the second active regions are dummy active regions and do not function as part of a MISFET, wherein the first conductor patterns are dummy conductor patterns and do not function as part of a MISFET, wherein the first conductor patterns and the second active regions are electrically coupled to the third metal pattern, wherein each of the first conductor patterns is formed over one corresponding adjacent groove of the plurality of grooves in which the insulating material is embedded, and wherein each of the second active regions is disposed below the first capacitance element but is disposed so as not to overlap the first metal pattern or the second metal pattern in a planar manner.