Patent ID: 7706487

Claim:
An apparatus containing a serial/deserializer transceiver device (SERDES) for transmitting communications over an aggregate path to a receiving SERDES device; said aggregate path having an input and an output and comprising the transmitting SERDES, a channel and the receiving SERDES, said channel introducing distortions into said signal; said apparatus comprising a training frame for supplying a pre-defined input sequence to the input of the aggregate path, wherein said input sequence comprises multiple training frames wherein each frame comprises a string of like bits and a pseudo-random sequence; and, a processor for determining an output of the aggregate path that corresponds to the pre-defined input sequence, performing a cross-correlating analysis between the pre-defined input sequence and the corresponding output to determine an aggregate channel impulse response of the aggregate path using an average of a plurality of outputs; estimating an inverse of the aggregate channel impulse response; and utilizing said inverse in at least one of said SERDES devices to reduce said distortions.