Patent ID: 7592250

Claim:
A manufacturing method of a multilayer wiring board which includes a plurality of insulating layers, a plurality of conductive layers, a conductive non-through hole for electrically connecting the plurality of conductive layers to each other, and a capacitor produced by forming electrodes on upper and lower surfaces of at least one insulating layer containing a high-dielectric material, comprising at least: the step of forming conductive patterns including one of the electrodes of the capacitor, the conductive patterns having a recessed portion between the conductive patterns; the step of filling and hardening an insulating material different from the high-dielectric material in the recessed portion between the conductive patterns; the step of planarizing the surfaces of the conductive patterns and the surface of the insulating material filled and hardened in the recessed portion between the conductive patterns by polishing, so as to form planarized surfaces of both the conductive patterns and the insulating material filled and hardened in the recessed portion between the conductive patterns; the step of providing a high-dielectric material sheet in a semi-hardened state, said high-dielectric material sheet having the at least one insulating layer containing the high-dielectric material and a metal foil laminated thereto, and the step of heating and laminating the high-dielectric material sheet in the semi-hardened state on the planarized surfaces of both the conductive patterns and the insulating material filled and hardened in the recessed portion, so that the at least one insulating layer of the high-dielectric material sheet is between (a) the conductive patterns and the insulating material filled and hardened in the recessed portion, and (b) the metal foil.