Patent ID: 6947336

Claim:
A semiconductor device comprising: an output buffer circuit comprising a pull-up section having a plurality of pull-up transistors and a pull-down section having a plurality of pull-down transistors; a pad connected to an external resistor; and an output impedance control circuit, connected to the pad and the output buffer circuit, for controlling an impedance of the output buffer circuit according to an impedance of the external resistor, wherein the output impedance control circuit comprises: a first transistor connected to the pad; a first current source circuit for supplying DC current to the pad; a first level controller, connected to the pad, for controlling a gate voltage of the first transistor such that the pad is established at a predetermined voltage; a second transistor, connected to a first internal node, controlled by the first level controller; a first variable impedance circuit connected to the first internal node; a second current source circuit for supplying DC current to the first internal node; a first controller, responsive to a voltage variation of the first internal node, for generating a first control code for controlling the first variable impedance circuit so that a voltage of the first internal node is established at the predetermined voltage; and a first conversion circuit for receiving the first control code and for converting the first control code into a first string of data bits, wherein the first string of data bits are transferred in series to the output buffer circuit via a single transmission line.