Patent ID: 7265408

Claim:
A nonvolatile semiconductor memory device comprising: a substrate of a first conductive type; a plurality of stripe-shaped STI (shallow Trench Isolation) films formed in a surface of said substrate to extend in a column direction; a plurality of control gates as word lines formed on the surface of said substrate to extend in a row direction; a plurality of diffusion layers of a second conductive type formed in the surface of said substrate in a region between every two of said plurality of STI films and between every two of said plurality of control gates; a memory cell, comprising: two of said plurality of diffusion layers adiacent in the column direction; a portion of one of said plurality of control gates between adjacent two of said plurality of STI films corresponding to said adjacent two diffusion layers, and said memory cell stores data of two or more bits; a charge storage layer configured to store data of one or more bits in said memory cell; a plurality of wiring lines, each of which is provided for every two of said plurality of diffusion layers adjacent in the row direction to connect said adjacent two diffusion layers, wherein said plurality of wiring lines are formed such that other two diffusion layers of said two memory cells having said two diffusion layers are different two of said plurality of wiring lines; and a plurality of bit lines provided to extend in the column direction, wherein each of said plurality of bit lines is connected with one of every two of said plurality of wiring lines in the column direction.