Patent ID: 8429217

Claim:
A method, in a data processing system comprising a hardware implemented floating point execution unit, for executing a fixed point divide instruction using the floating point execution unit, comprising: receiving, in the floating point execution unit, operands of the fixed point divide instruction, wherein the operands include a numerator and a divisor; converting, in the floating point execution unit, the numerator and divisor to a floating point format; generating, in the floating point execution unit, an estimate of a reciprocal of the divisor; and determining a quotient for the fixed point divide instruction using the floating point formatted numerator, divisor and the estimate of the reciprocal of the divisor, wherein generating an estimate of the reciprocal of the divisor includes using an estimate table unit in the floating point execution unit to lookup an estimate of the reciprocal of the divisor, and wherein the lookup of the estimate of the reciprocal of the divisor in the estimate table unit is based on a shifted mantissa of the divisor, wherein determining a quotient for the fixed point divide instruction using the floating point formatted numerator, divisor and the estimate of the reciprocal of the divisor includes: making multiple passes through a pipeline of the floating point execution unit using results from a previous pass through the pipeline of the floating point execution unit, to generate estimates of the quotient for the fixed point divide instruction, wherein a final pass through the pipeline of the floating point execution unit involves truncating an estimate of the quotient to generate a final estimate of the quotient for the fixed point divide instruction.