Patent ID: 7386683

Claim:
A method for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated therewith and operatively connected via a first communications means, said method comprising: providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in said multiprocessor computing environment; directly connecting each said memory writing source to the dedicated input ports of all other snoop filter devices associated with all other processing units of said multiprocessor computing environment in a point-to-point interconnect fashion; providing, for each said snoop filter device, a plurality of parallel operating port snoop filters in correspondence with said plurality of dedicated input ports, each said plurality of plurality operating port snoop filters concurrently tracking snoop requests from a corresponding one of said plurality of memory writing sources and recording an address of each snoop request received in a corresponding snoop cache from its corresponding memory writing source, and, comparing each received snoop request address against all addresses recorded in said corresponding snoop cache, wherein each said snoop filter device concurrently filters snoop requests received from respective said dedicated memory writing sources and forwards a subset of those requests to its associated processing unit, whereby a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of said computing environment.