Patent ID: 7526695

Claim:
A scan BIST test configuration of circuitry within an integrated circuit comprising: A. functional circuitry including logic circuits to be tested; B. scan path circuitry formed of serially connected scan cells, each serially connected scan cell includes a multiplexer and a flip-flop with an output of the multiplexer being an input to the flip-flop, the multiplexer having response data and scan data inputs and the flip-flop having an output providing stimulus data and scan data, the scan path circuitry having stimulus output leads and response input leads connected to the logic circuits, the scan path circuitry having a serial data input lead, a serial data output lead, and control input leads, the scan path circuitry being organized in selectable, separate scan paths, each separate scan path having a serial data input lead connected to the serial data input lead, a serial data output lead selectively coupled to the serial data output lead, and a separate set of control input leads; C. test data generator circuitry having control inputs and having a serial test stimulus output connected to the serial data input lead; D. test data compactor circuitry having control inputs and having a serial test response input connected to the serial data output lead; E. controller circuitry having generator control outputs connected to the control inputs of the test data generator circuitry, compactor control outputs connected to the control inputs of the test data compactor circuitry, and scan path control outputs; and F. adaptor circuitry having control inputs connected to the scan path control outputs of the controller circuitry and a separate set of control output leads connected to the control input leads of each separate scan path.