Patent ID: 6936531

Claim:
The process for fabricating a chip structure, comprising: Step 1: providing a wafer with a plurality of electric devices, an interconnection scheme and a passivation layer, the electric devices and the interconnection scheme arranged inside the wafer, the interconnection scheme electrically connected with the electric devices, the passivation layer disposed on a surface layer of the wafer, the passivation layer having at least one opening exposing the interconnection scheme, wherein the largest width of the opening of the passivation ranges from 0.5 microns to 20 microns; Step 2: forming a conductive layer over the passivation layer of the wafer, and the conductive layer electrically connected with the interconnection scheme; Step 3: forming a photoresist onto the conductive layer, and the photoresist having at least one opening exposing the conductive layer; Step 4: filling at least one conductive metal into the opening of the photoresist, and the conductive metal disposed over the conductive layer; Step 5: removing the photoresist; and Step 6: removing the conductive layer not covered with the conductive metal.