Patent ID: 8063961

Claim:
A dual CDS/PxGA circuit comprising: a first sampler configured to sample a reset level and a data level of a first pixel; a second sampler configured to sample a reset level and a data level of a second pixel; and an operational amplifier configured to receive sampling values from the first and second samplers, calculate output signals of the first and second pixels using the sampling values, and amplify the calculated output signals, wherein a gain of the operational amplifier is determined based on capacitance of capacitors included in the first and second samplers, wherein the first sampler comprises: a first reset level sampler configured to sample the reset level of the first pixel; and a first data level sampler configured to sample the data level of the first pixel, wherein the second sampler comprises: a second reset level sampler configured to sample the reset level of the second pixel; and a second data level sampler for sampling the data level of the second pixel, and wherein the first reset level sampler, the first data level sampler, the second reset level sampler, and the second data level sampler comprise a plurality of capacitors and have substantially the same structure, wherein each of the first reset level sampler, the first data level sampler, the second reset level sampler, and the second data level sampler comprises: first and second sampling switches, each of which includes a first end that is coupled to an input terminal; a first amplification switch including a first end that is coupled to a common mode voltage terminal; a first sampling capacitor including a first end that is coupled to a second end of the first sampling switch; a second sampling capacitor including a first end that is coupled to a second end of the second sampling switch and a second end of the first amplification switch; a first variable capacitor including a first end that is coupled to the second end of the second sampling switch and the second end of the first amplification switch; a second variable capacitor including a first end that is coupled to a common node of second ends of the first sampling capacitor, the first variable capacitor and the second sampling capacitor; and a third sampling switch coupled between a second end of the second variable capacitor and the common mode voltage terminal.