Patent ID: 7504289

Claim:
A process for forming an electronic device comprising: providing a substrate; forming a first gate electrode of a first transistor structure over the substrate, wherein the first transistor structure includes a first channel region; forming a second gate electrode of a second transistor structure over the substrate, wherein the second transistor structure includes a second channel region that has a conductivity type opposite that of the first channel region; forming a first sidewall spacer that surrounds the first gate electrode and a second sidewall spacer that surrounds the second gate electrode, wherein the first and second sidewall spacers have a first stress; removing the second sidewall spacer; and forming a third sidewall spacer that surrounds the second gate electrode, wherein: forming the third sidewall spacer comprises: forming a tensile silicon nitride layer over the first gate electrode, the second gate electrode, the first sidewall spacer, and the substrate; and removing a portion of the tensile silicon nitride layer using an HF solution; the third sidewall spacer is formed after removing the second sidewall spacer and has a second stress different from the first stress; and after forming the third sidewall spacer: the first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode; and the third sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode.