Patent ID: 8193051

Claim:
A method of forming a semiconductor structure comprising the steps of: providing a p-type semiconductor structure comprising at least one first patterned gate stack on a first channel portion of a substrate, said first channel portion separating silicided p-type source and drain portions of said substrate, said at least one first patterned gate stack comprising a hafnium containing high-k gate dielectric atop said substrate, an insulating interlayer atop said high-k gate dielectric, and a first fully silicided gate conductor atop said insulating interlayer, wherein the insulating interlayer comprises aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), boron nitride (BN), boron oxynitride (BO x N y ), gallium nitride (GaN), gallium oxynitride (GaON) indium nitride (InN), indium oxynitride (InON) or combinations thereof; providing an n-type semiconductor structure comprising at least one second patterned gate stack on a second channel portion of a substrate, said second channel portion separating silicided n-type source and drain portions of said substrate, said at least one second patterned gate stack comprising the high-k gate dielectric atop said substrate, and a second fully silicided gate conductor atop said high-k gate dielectric, wherein the insulating interlayer is not present; and biasing said at least one first patterned gate stack and said at least one second patterned gate stack, wherein said insulating interlayer stabilizes the p-type semiconductor structure's threshold voltage and flatband voltage to a targeted value without degrading the n-type semiconductor structure's threshold voltage and flatband voltage.