Patent ID: 8006068

Claim:
A method for access to data storage, comprising: providing a general-purpose processor and an auxiliary processing unit interface coupled to the general-purpose processor; providing a coprocessor coupled to the auxiliary processing unit interface; providing data storage coupled to the general-purpose processor via the auxiliary processing unit interface for a read latency access and a fixed write latency access to the data storage; passing a first instruction to the general-purpose processor; passing the first instruction from the general-purpose processor to the auxiliary processing unit interface; identifying the first instruction as part of a set of instructions accessible by the auxiliary processing unit interface; wherein the first instruction is a store instruction that specifies a write address in the data storage and write data to write to that address; passing the first instruction from the auxiliary processing unit interface to the data storage and bypassing the coprocessor in the passing of the first instruction; storing the write data in the data storage at the write address in response to the first instruction; passing a second instruction to the general-purpose processor; passing the second instruction to the auxiliary processing unit interface; identifying the second instruction as part of the set of instructions accessible by the auxiliary processing unit interface; wherein the second instruction is a read instruction that specifies a read address in the data storage; passing the second instruction from the auxiliary processing unit interface to the data storage and bypassing the coprocessor in the passing of the second instruction; reading data from the data storage at the read address in response to the second instruction; and outputting the data read from the data storage to the general-purpose processor.