Patent ID: 7323902

Claim:
A logic element for use in a programmable logic device, the logic element comprising: a plurality of memory elements, each of the memory elements arranged to store a data value; a first plurality of multiplexers, each of the multiplexers being either directly or indirectly coupled to one or more of the memory elements and configured to output a selected one of data values stored in the memory elements; and a set of select signals configured to control the first plurality of multiplexers to output one or more of the data values stored in the memory elements respectively, the select signals being selectively coupled to the first plurality of multiplexers to implement the following logic functions: Z 1 being derived from the full set of the select signals; Z 2 being derived from a first sub-set of the full set of select signals, and Z 3 being derived from a second sub-set of the select signals, the second subset being different that the first subset but including at least one select signal in common with the first subset.