Patent ID: 7423330

Claim:
a semiconductor device comprising: a semiconductor substrate having a p-channel type transistor region; an element isolation region formed in a surface portion of said semiconductor substrate, said element isolation region defining a p-channel type active region in said p-channel type transistor region; a p-channel type gate electrode structure formed above said semiconductor substrate, traversing said p-channel type active region and defining a p-channel region under said p-channel type gate electrode structure; a compressive stress film selectively formed above said p-channel type active region and covering said p-channel type gate electrode structure; and a stress released region selectively formed above said element isolation region in said p-channel type transistor region, said stress released region releasing stress in said compressive stress film, wherein said stress released region is made of an ion implanted region, wherein said ion implanted region is a region where electrically inert impurity ions are implanted, wherein said compressive stress film above said p-channel type active region exerts a compressive stress on said p-channel region along a gate length direction, and said compressive stress film and said stress released region exert a tensile stress on said p-channel region along a gate width direction.