Patent ID: 7401164

Claim:
A process for controlling a multiple core expander comprising: using a test port of said multiple core expander to receive both data values as well as instructional and operational codes including a dummy bit from a host computer into a multi-bit shift register and a single bit shift register to said multiple core expander to put all but one core expander of said multiple core expander in bypass mode; decoding said instructional and operational input codes by a state machine of said one core expander not placed in bypass mode; serially reading data from, and serially writing data to, at least one internal register of said one core expander not placed in bypass mode by said state machine; transmitting a control signal from said state machine to a multiplexer to shift data to an output port of said one core expander not placed in bypass mode to either a series connected core expander or back to said host computer; and connecting internal registers to an expander bus wherein said internal registers store data that is used to operate said multiple core expander in order to perform various operations.