Patent ID: 7642865

Claim:
A circuit for generating multiple phase clock signals comprising: a voltage controlled oscillator (VCO) having a plurality of VCO cells cascaded in a ring structure to generate a plurality of VCO output clock signals; a clock divider circuit for dividing and phase shifting the VCO output clock signals, the clock divider circuit comprising a plurality of counters, one corresponding to each of the VCO output clock signals for dividing said VCO output clock signals by a specific number to generate a plurality of phase shifted output clock signals having a same frequency, such that each of said counters starts from a same state of a plurality of desired states and generates a plurality of phase shifted output clock signals in the same order in which said counters receive the VCO output clock signals; and a signal module for generating an external and internal signal after the VCO starts giving the output clock signals, said signal module comprising: a frequency detector for generating said signals when a frequency of the feedback clock is within a predefined range of an input clock; and a lock detector for indicating output of a lock, when frequency of the feedback clock is not within a predefined range of the input clock and for providing an enabling signal directly to said clock divider circuit.