Patent ID: 8048748

Claim:
A method, comprising: forming a first active region and a second active region in a semiconductor layer of a semiconductor device, said semiconductor layer being formed on a substrate having a back side; forming a mask layer above said first and second active regions and above said back side; removing said mask layer selectively from said first active region while preserving said mask layer above said second active region and said back side; forming a threshold adjusting semiconductor alloy selectively on said first active region while using said preserved mask layer as a mask; removing said mask layer at least from said second active region; and forming a first gate electrode structure of a first transistor on said threshold adjusting semiconductor alloy formed on said first active region and forming a second gate electrode structure of a second transistor on said second active region, said first and second gate electrode structures comprising a high-k dielectric gate insulation layer and a metal-containing gate electrode material.