Patent ID: 8569133

Claim:
A method of manufacturing a nonvolatile semiconductor memory device, said nonvolatile semiconductor memory device including a plurality of memory strings, each of which includes a plurality of electrically rewritable memory cells connected in series, and select transistors, one of which is connected to each of ends of each of said memory strings, said method comprising: forming a first conductive layer on an upper layer above a substrate; forming a trench extending in a first direction parallel to said substrate, so as to dig out said first conductive layer; forming a plurality of second conductive layers functioning as gates of said plurality of memory cells on an upper layer of said first conductive layer; forming a third conductive layer functioning as a gate of a select transistor above an uppermost layer of said second conductive layers; forming a first through hole in said second conductive layers and a second through hole in said third conductive layer to pass through the plurality of said second conductive layers and said third conductive layer, and to align with vicinities of both ends in said first direction of said trench; forming a memory gate insulating layer including a charge storage layer on a side surface facing said trench, said first through hole, and said second through hole; forming a first semiconductor layer functioning as bodies of said plurality of memory cells on a side surface of said memory gate insulating layer to fill said trench and said first through hole; forming a second semiconductor layer functioning as a body of said select transistor on a side surface of said memory gate insulating layer to fill said second through hole; and forming a gap between said second semiconductor layer and said third conductive layer by removing said memory gate insulating layer adjacent to said second semiconductor layer from an upper layer of said third conductive layer to a position between said third conductive layer and the uppermost layer of said second conductive layers, while leaving said second semiconductor layer.