Patent ID: 7515076

Claim:
An integrated circuit, comprising: an analog-to-digital converter for receiving an analog input signal and providing a digital output, wherein a discrete-time sampling circuit of the analog-to-digital converter is responsive to a first clock signal to sample the analog input signal; a digital logic circuit for performing processing operations within the integrated circuit, wherein the digital logic circuit is responsive to a second clock signal to cause transitions of logic within the digital logic circuit; and a clock generator circuit for receiving a master clock signal and providing the first clock signal and the second clock signal as frequency divisions of the master clock signal, wherein the clock generator circuit includes a first clock divider for generating the first clock signal from the master clock signal and a second clock divider for generating the second clock signal from the master clock signal, and wherein the clock generator circuit adjusts an edge relationship between the first clock signal and the second clock signal such that transitions of the second clock signal do not occur near critical sampling edges of the first clock signal by presetting the first clock divider or the second clock divider with an offset value, whereby sampling error in the analog-to-digital converter due to transition noise coupled from the digital logic circuit is substantially eliminated.