Patent ID: 6971020

Claim:
An electronic circuit for the securing of a cryptography coprocessor comprising: a memory module for storing a message to be processed by an encryption or decryption operation and an unencrypted digital key; a battery of input/output registers connected to the memory module by a first two-way link for receiving digital key data from said memory module comprising the unencrypted digital key and a plurality of scrambling bits intermixed with the unencrypted digital key; said battery of input/output registers comprising a scrambling register for storing the scrambling bits separate from the unencrypted digital key data; an input register for receiving the message to be processed; a key register for receiving the unencrypted digital key data for use in the encryption or decryption operation; a multiplexer to carry out a transfer of data between the battery of input/output registers and the input register and the key register; a second, dedicated two-way link connecting said multiplexer and said scrambling register for transferring the scrambling bits therebetween substantially simultaneously with the transfer of data between the battery of input/output registers and said multiplexer; and a processing module connected to said scrambling register, said input register, and said key register for determining the unencrypted digital key based upon the digital key data in said key register and the scrambling bits in said scrambling register, and for performing the encryption or decryption operation on the message stored in the input register based thereon; a control module for controlling the memory module, the battery of input/output registers, the multiplexer and the processing module; and an output register to transmit the result of the encryption or decryption operation to the battery of input/output registers through the multiplexer.