Patent ID: 8008143

Claim:
A method for fabricating an integrated circuit device having gate dielectric layers of varying thicknesses, the method comprising: providing a substrate with a first region, a second region, and a third region; forming a first gate structure in the first region, wherein the first gate structure includes a first gate dielectric layer having a first thickness, a barrier layer, and a dummy gate layer; forming a second gate structure in the second region, wherein the second gate structure includes a dummy gate dielectric layer and the dummy gate layer; forming a third gate structure in the third region, wherein the third gate structure includes the dummy gate dielectric layer and the dummy gate layer; removing the dummy gate layer from the first, second, and third gate structure, thereby forming openings in the first, second, and third gate structures; performing an implantation process in the second region; removing the dummy gate dielectric layer from the openings of the second and third gate structures; forming an interfacial dielectric layer to partially fill in the openings of the second and third gate structures, wherein the interfacial dielectric layer of the second gate structure has a second thickness and the interfacial dielectric layer of the third gate structure has a third thickness; and forming a gate in the openings of the first, second, and third gate structures.