Patent ID: 8473683

Claim:
A computer-implemented method for processing at least one store instruction in a parallel computing system including a plurality of computing node, a computing node including a plurality of processor cores and at least one shared cache memory device, a processor core having at least one local cache memory device, the method comprising: receiving the at least one store instruction from a first processor core; storing the at least one store instruction in a first queue associated with the first processor core; storing the at least one store instruction in a second queue associated with a first local cache memory device of the first processor core; updating first data in the first local cache memory device according to the at least one store instruction; storing the at least one store instruction in a third queue associated with the at least one shared cache memory device; invalidating second data in the at least one shared cache memory, the second data associated with the at least one store instruction; invalidating third data in other local cache memory devices associated with other processor cores, the third data associated with the at least one store instruction; and flushing only the first queue.