Patent ID: 8190803

Claim:
A system comprising: a root bus controller configured to pre-assign root bus access timeslots to individual of a plurality of root processors, and further configured to access a root memory in response to a root memory access request received from a root processor during the root processor's pre-assigned root bus access timeslot; a leaf bus controller configured to pre-assign leaf bus access timeslots to individual of a first set of one or more leaf processors, and further configured to access a leaf memory in response to a leaf memory access request received either from a root processor during the root processor's pre-assigned root bus access timeslot or from a leaf processor during the leaf processor's pre-assigned leaf bus access timeslot; a root bus configured to provide a communications path between the root bus controller, the leaf bus controller, and the plurality of root processors; and a leaf bus configured to provide a communications path between the leaf bus controller and the first set of leaf processors.