Patent ID: 6902869

Claim:
A method of manufacturing a multilayer circuit board; (a) applying a first continuous homogenous metal layer on a first dielectric layer, (b) applying a first photoresist on said first metal layer; (c) exposing and developing said first photoresist to define a conductive bump; (d) etching the first metal layer not covered by said first photoresist to reduce the height of said exposed metal layer and to provide said conductive bump; (e) removing said first photoresist; (f) applying a second photoresist onto said first metal layer; (g) exposing and developing said second photoresist to define a pattern comprising said conductive bump and a plurality of circuit lines; (h) etching the first metal layer exposed by the development of said second photoresist to form said conductive bump having an upper surface and a plurality of circuit lines in said first metal layer; (i) removing said second photoresist; (j) forming a second dielectric layer on the plurality of circuit lines and the substrate exposed by etching, said dielectric layer defining a hole which exposes the top surface of the conductive bump; (k) applying a second metal layer onto said second dielectric layer and onto the exposed upper surface of said conductive bump to provide a multilayer substrate comprising a first metal layer and a second metal layer on opposing surfaces of said second dielectric layer, wherein said first metal layer and said second metal layer are interconnected by a solid conductive bump.