Patent ID: 7292477

Claim:
A semiconductor memory device comprising: a memory cell; a voltage supplying section which supplies control gate voltage to a control gate of the memory cell and supplies drain voltage to a drain of the memory cell when data is written into the memory cell; and a control section which verifies a threshold value of the memory cell after data is written into the memory cell, wherein the voltage supplying section supplies first control gate voltage to the control gate for a first control time period and supplies preset write voltage to the drain for a first write time period which is shorter than the first control time period, starts after start of supply of the first control gate voltage and ends before elapse of the first control time period when a data write operation into the memory cell is started, the voltage supplying section supplies second control gate voltage obtained by raising the first control gate voltage by constant voltage to the control gate for a second control time period which is shorter than the first control time period and supplies the preset write voltage to the drain for a second write time period which is shorter than the first write time period, starts after start of supply of the second control gate voltage and ends before elapse of the second control time period in a case where it is detected that a data amount written in the memory cell is insufficient as the result of a first verify operation by the control section, and the voltage supplying section supplies third control gate voltage obtained by raising the second control gate voltage by the constant voltage to the control gate for the second control time period and supplies the preset write voltage to the drain for the second write time period in a case where it is detected that a data amount written in the memory cell is insufficient as the result of a second verify operation by the control section.