Patent ID: 8481404

Claim:
A method, comprising: forming an isolation trench in a semiconductor material of a semiconductor device, said isolation trench having a sidewall connecting to an active region of a first transistor of a memory cell of said semiconductor device, said sidewall delineating said active region in a length direction; introducing an implantation species into a portion of said active region through at least a portion of said sidewall, said implantation species extending along said length direction with a specified distance from said sidewall into said active region; filling said isolation trench with an insulating material after introducing said implantation species so as to form an isolation structure; forming said first transistor in and above said active region; forming a portion of a gate electrode of a second transistor of said memory cell above said isolation structure; forming a dielectric material so as to enclose said first transistor and said second transistor; and forming a contact element in said dielectric material, said contact element connecting said active region and said portion of the gate electrode of said second transistor.