Patent ID: 8223058

Claim:
A switched-capacitor circuit, comprising: a capacitor array circuit configured to receive a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal; a comparator configured to receive the output signal of said capacitor array circuit; and a current source, disposed between a first fixed voltage source and an output terminal of said switched-capacitor circuit, configured to supply a current to the output terminal thereof until an output signal of the comparator changes; said capacitor array circuit including: a plurality of input capacitors for receiving a plurality of input signals in parallel with each other; and a regulating capacitor for storing a charge to compensate for an offset component caused by a delay in said comparator, wherein the respective output terminals of the plurality of input capacitors and the regulating capacitor are combined into one, and a current is supplied from a constant current source to the regulating capacitor for a length of time corresponding to the delay in said comparator.