Patent ID: 7754571

Claim:
A method for forming a strained channel in a semiconductor device, comprising: providing a transistor, comprising: a gate stack exposed with a gate electrode on a semiconductor substrate; a pair of source/drain regions in the substrate on opposite sides of the gate stack; a pair of spacers on opposing sidewalls of the gate stack; forming a passivation layer covering the gate electrode and the spacers; forming a resist pattern on a portion of the passivation layer; performing an etching by using the resist pattern as an etching mask to the passivation layer and the semiconductor substrate, forming a recess region in each of the source/drain regions and leaving a patterned passivation layer covering portions of the gate electrode and the spacers, wherein an edge of the recess region aligns to an outer edge of the spacers and the patterned passivation layer does not cover entire sidewalls of the spacers and a top surface of the semiconductor substrate; and after performing the etching, then directly filling the recess regions with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.