Patent ID: 8570056

Claim:
A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirect secure said corresponding semiconductor wafers and that possess a mechanism for positioning said corresponding semiconductor wafers; and a probe card, arranged outside or in between said plurality of laminated semiconductor wafers so as to face said semiconductor wafers, that transmits a signal or power to said plurality of semiconductor wafers, wherein a plurality of subject chips are formed in said semiconductor wafers; and said probe card comprises one or more inspecting chips capable of performing non-contact transmission to said subject chips in said semiconductor wafers, wherein said subject chip includes at least one non-contact transmission electrode that performs non-contact transmission of a signal or power, and said inspecting chip includes at least one non-contact transmission electrode that performs non-contact transmission of a signal or power to said non-contact transmission electrode of said subject chip.