Patent ID: 8553457

Claim:
A method carried out in a memory device having a plurality of non-volatile memory cells, and each non-volatile memory cell of the non-volatile memory cells having multiple possible states being defined by respective threshold voltage ranges including a first voltage range, a second voltage range, a third voltage range and a fourth voltage range, the second voltage range being adjacent to a lowest voltage range which is the first voltage range, the third voltage range being in-between the second and fourth voltage ranges, and the method comprising: when operating the non-volatile memory cell in a Multiple Bit per Cell (MBC) storage mode, storing more than one bit of data by: carrying out lower page programming, the lower page programming being a first stage of programming; and carrying out upper page programming, the upper page programming being a second stage of programming; and when operating the non-volatile memory cell in a Single Bit per Cell (SBC) storage mode, storing a single bit of data by: carrying out single stage programming; and using only the first voltage range and the fourth voltage range to store the single bit of data.