Patent ID: 7697262

Claim:
A multilayer electronic component, comprising: a plurality of first electrode layers, each first electrode layer comprising a first dielectric layer having first and second surfaces thereof bounded by four edges and a first conductive layer covering a portion of said first surface of said first dielectric layer and extending to at least a portion of one edge of said first dielectric layer; a plurality of second electrode layers alternately stacked with said plurality of first electrode layers, each second electrode layer comprising a second dielectric layer having first and second surfaces thereof bounded by four edges and a second conductive layer covering a portion of said first surface of said second dielectric layer and extending to at least a portion of one edge of said second dielectric layer, the second conductive layer formed as a mirror image of the first conductive layer; a first conductive termination layer covering a portion of said at least one edge of said first electrode layer and electrically connecting said first conductive layer of each of said plurality of first electrode layers; and a second conductive termination layer covering a portion of said at least one edge of said second electrode layer and electrically connecting said second conductive layer of each of said plurality of second electrode layers; wherein portions of said plurality of first electrode layers overlap portions of said plurality of second electrode layers in a non-contacting relationship; wherein said first conductive termination layer and said second conductive termination layer are configured so as to form a gap there between along a portion of said at least one edge of both said first and second electrode layers; whereby a minimum current loop area is formed from said first conductive termination layer through said overlapped plurality of first electrode layers and plurality of second electrode layers to said second conductive termination layer.