Patent ID: 8275976

Claim:
A hierarchical microprocessor having a plurality of execution clusters and a hierarchical instruction scheduler, the hierarchical microprocessor configured to virtualize one or more execution threads to create a plurality of virtual threads, the hierarchical microprocessor comprising: a second-level instruction scheduler configured to: receive instructions for execution; store second-level operand status information for respective operands of the instructions; dispatch the instructions at a granularity corresponding to an instruction group to respective execution clusters based at least partly on respective second-level operand status information of one or more but fewer than all instructions of the instruction group; assign respective virtual threads of the plurality of virtual threads to respective execution clusters of the plurality of execution clusters; and dispatch instructions associated with a given respective virtual thread to a single execution cluster of the plurality of execution clusters, wherein the second-level instruction scheduler includes: a timing wheel circuit configured to schedule the instructions based at least partly on respective predictions as to when one or more of the respective operands of the instructions will be available, the timing wheel circuit including a circular instruction buffer; and a picker circuit configured to notify the second-level instruction scheduler when one or more operands of a respective instruction become available, the picker circuit including a comparison circuit configured to determine when the one or more operands become available; a plurality of first-level instruction schedulers each operatively coupled with the second-level instruction scheduler, each first-level instruction scheduler being included in a respective execution cluster, the first-level instruction schedulers each configured to: receive instructions for execution from the second-level instruction scheduler; store first-level operand status information for respective operands of the instructions received from the second-level instruction scheduler; and dispatch instructions for execution at a granularity corresponding to an individual instruction to respective execution units of the execution clusters based at least partly on the instructions' respective first-level operand status information; and at least one replay loop coupled between the plurality of first-level instruction schedulers and the second-level instruction scheduler, the at least one replay loop configured to: receive from at least one first-level instruction scheduler of the plurality of first-level instruction schedulers at least one instruction of a particular instruction group for re-scheduling via the second-level instruction scheduler.