Patent ID: 7166893

Claim:
A semiconductor integrated circuit device, comprising: a first semiconductor principal surface and a second semiconductor principal surface separated from each other over a semiconductor body, and a first and second MISFETs formed in said first and second semiconductor principal surfaces, respectively; said first MISFET comprising: a first gate electrode provided over said first semiconductor principal surface with a gate insulation film interposed therebetween, a first region having a relatively low concentration which is aligned with said first gate electrode and which exhibits the conductivity type opposite to the conductivity type of said first semiconductor principal surface, a first insulation film provided over a side wall of said first gate electrode, and a second region which is aligned with said first insulation film, which exhibits the same conductivity type as said first region and which is in contact with said first region, said second MISFET comprising: a second gate electrode provided over said second semiconductor principal surface with a gate insulation film interposed therebetween, a third region having a relatively low concentration which is aligned with said second gate electrode and which exhibits the conductivity type opposite to the conductivity type of said second semiconductor principal surface, a second insulation film provided over a side wall of said second gate electrode, and a fourth region which is aligned with said second insulation film, which exhibits the same conductivity type as said third region and which is in contact with said third region, wherein the thickness of said second gate insulation film is greater than that of said first gate insulation film, wherein, at the direction of the gate length, the length of said second insulation film is greater than that of said first insulation film, wherein said second insulation film is formed over the upper surface of said second gate electrode.