Patent ID: 7330952

Claim:
An integrated circuit memory device comprising: a memory core including a plurality of memory cells; a pin to receive a clock signal; a first set of pins to receive, using the clock signal: a write command to specify that the memory device receive write data and store the write data in the memory core; and a read command to specify that the memory device output read data accessed from the memory core, wherein the first set of pins receive the read command after the first set of pins receive the write command; and a second set of pins to receive the write data after a first delay time has transpired from when the write command is received at the first set of pins; the second set of pins to provide, for each pin of the second set of pins, output of at least two bits of the read data after a second delay time transpires from when the read command is received, wherein the at least two bits of the read data are provided during a clock cycle of the clock signal, wherein the second delay time is based on the first delay time.