Patent ID: 7010765

Claim:
A method for processing an integrated circuit (IC) design including a description of a net for conveying a signal downstream from a root node to a plurality of leaf nodes wherein the net comprises a plurality of inverters and a plurality of a segments including a single root segment connected to the root node, a plurality of inverter segments, each terminating at an input of a separate one of the inverters, at least one branch segment branching into a plurality of other net segments, and at least one leaf segment, each terminating at a separate one of the leaf nodes, the method comprising the steps of: a. generating one data set corresponding to each leaf segment; b. generating two data sets corresponding to each branch segment; c. generating two data sets corresponding to each inverter segment; and d. generating one data set corresponding to the root segment, wherein each data set corresponding to any one of the segments indicates a total number of inverters to be removed downstream of the segment, indicates whether removal of the indicated number of inverters downstream of the corresponding segment will affect a logic state of the signal as it arrives at any leaf node downstream of the corresponding segment, wherein each data set corresponding to any one of the segments indicates whether it terminates on a downstream inverter that is to be removed, and wherein each data set corresponding to any one of the segments references a data set corresponding to each segment immediately downstream of its corresponding segment.