Patent ID: 8589629

Claim:
A computing system comprising: a first source configured to generate memory requests; a second source different from the first source configured to generate memory requests; a shared cache comprising a first portion of one or more entries and a second portion of one or more entries different from the first portion; and a shared cache controller coupled to the shared cache, wherein the shared cache controller is configured to: determine the first portion is permitted to have data allocated by the first source but not by the second source; and determine the second portion is permitted to have data allocated by the second source but not by the first source; perform said determining based upon identification of either the first source or the second source as a source of a command comprising a corresponding memory request and at least one of the following: a command type of the corresponding memory request, and hint bits, wherein said hint bits are part of the command sent by the source and are distinct from the identification of the source; and wherein data stored in either the first portion or the second portion may be hit for a read or a write access by either of the first source or the second source.