Patent ID: 7136313

Claim:
A semiconductor storage device having: a memory cell array section, into which nonvolatile memory is arranged; and a peripheral circuit section for performing input/output of data into/from the memory cell array section and memory control; wherein the memory cell array section comprises: a main storage area; a redundant storage area, for storing information in lieu of a faulty area of the main storage area; a first setting function storage area and a second setting function storage area for storing faulty address information indicating the faulty area and operation mode setting information about the semiconductor storage device; the first setting function storage area being formed from electrically-rewritable nonvolatile memory; the second setting function storage area being formed from once-rewritable nonvolatile memory; wherein the peripheral circuit section comprises: an operation mode register for temporarily storing the operation mode setting information; a faulty address register for temporarily storing the faulty address information; and wherein the semiconductor storage device comprises: selective transfer means for selectively transferring, from the first setting function storage area and the second setting function storage area, the operation mode setting information to the operation mode register or the faulty address information to the faulty address register.