Patent ID: 7164287

Claim:
A semiconductor device including: interface buffers whose internal impedances are controlled by impedance control data; and an impedance control circuit that generates the impedance control data, wherein the impedance control circuit includes a first impedance control mode that generates the impedance control data by a sequential comparison operation resulting from predetermined impedance control steps and sets the impedance control data in the interface buffer, and a second impedance control mode that updates the impedance control data set in the interface buffer by a sequential comparison operation resulting from the predetermined impedance control steps, wherein the impedance control steps of the first impedance control mode and the impedance control steps of the second impedance control mode are different, wherein the impedance control steps of the first impedance control mode are different steps of plural stages, and wherein relatively larger steps of the different steps of plural stages are used in the former sequential comparison operation and relatively smaller steps are used in the latter sequential comparison operation.