Patent ID: 7254698

Claim:
A method for executing a hexadecimal floating point instruction in a computer system, the computer system comprising a plurality of general registers, and a general purpose processor in communications with a computer memory, the processor comprising one or more execution units, the execution units executing instructions fetched from the computer memory, the method comprising the steps of: (a) fetching a hexadecimal floating point instruction; (b) responsive to fetching the hexadecimal floating point instruction, determining that the hexadecimal floating point instruction is either a multiply and add instruction or a multiply and subtract operation; and (c) responsive to the determining step, (1) fetching a first operand comprising a first exponent value and a first fraction (significand) value and a second operand comprising a second exponent value and a second fraction (significand) value; (2) multiplying the first fraction value and second fraction value to produce a full precision result; (3) fetching a third operand comprising a third exponent and a third fraction value; (4a) when the hexadecimal floating point instruction is a multiply and add instruction, adding the third operand to the full precision result to produce a second result; (4b) when the hexadecimal floating point instruction is a multiply and subtract instruction, subtracting the third operand from the full precision first, result to produce a second result; (5) deriving a fourth fraction value from the second result; and (6) storing a result operand, the result operand comprising the fourth fraction.