Patent ID: 7867815

Claim:
A method for manufacturing a memory device, comprising: forming an electrode layer having a top surface, the electrode layer including a first pan-shaped electrode and a second pan-shaped electrode, and an insulating wall between the first and second pan-shaped electrodes, and wherein the first and second pan-shaped electrodes have respective first and second side wall structures, and the insulating wall and the respective first and second side wall structures extend to the top surface of the electrode layer, and the insulating wall has a width between the first and second side wall structures at the top surface; forming a bridge of memory material on the top surface of the electrode layer across the insulating wall, the bridge comprising a patch of memory material having a first side and a second side and contacting the first and second side wall structures on the first side, the bridge defining an inter-electrode path between the first and second side wall structures across the insulating wall having a path length defined by the width of the insulating wall, wherein the memory material comprises a programmable resistive material.