Patent ID: 8856433

Claim:
A memory card, comprising: a memory unit having a first read clock generator for generating a first read clock signal and at least one nonvolatile memory; a card controller for controlling the memory unit and having a second read clock generator for generating a second read clock signal, wherein the memory unit transfers read data for a read command and the first read clock signal generated within the memory unit to the card controller, and wherein the card controller transfers the read data from the memory unit to an external device that is external to the memory card along with the second read clock signal; and a card I/O circuit for output-latching the read data to the external device in synchronism with the second read clock signal, wherein the card controller upon receiving the read command controls the second read clock generator to generate the second read clock signal; and wherein the second read clock signal is transferred to the external device substantially only during a read operation when read data is being transferred to the external device; and wherein a time duration for sending the second read clock signal is determined from a size of the read data.