Patent ID: 8098786

Claim:
A reception apparatus, which receives a serial data signal and a clock signal, and samples and outputs data of each bit of said serial data signal based on said clock signal, comprising: a sampler block circuit, which takes as input said received serial data signal, also takes as input a multiphase sampling clock signal, and samples and outputs the data of each bit of said serial data signal with timing indicated by said sampling clock signal; a phase adjustment circuit, which takes as input said received clock signal, adjusts the phase of the input clock signal, and outputs a clock signal after this phase adjustment; and a sampling clock signal generation circuit, which takes as input said clock signal phase-adjusted and output by said phase adjustment circuit, and generates said multiphase sampling clock signal based on the input clock signal, and characterized in that said phase adjustment circuit adjusts the phase of said clock signal such that the delay time from generation of said multiphase sampling clock signal in said sampling clock signal generation circuit until indication of sampling timing by said sampling clock signal in said sampler block circuit is canceled.