Patent ID: 7113440

Claim:
A semiconductor memory device comprising: a self refresh request signal generation means which receives a self refresh signal for generating a base periodic signal, a plurality of divided signals and a self refresh request signal, wherein the self refresh request signal generation means includes a frequency division unit includes a plurality of frequency dividers, wherein a first frequency divider of the plurality of frequency dividers receives the base periodic signal in order to generate a first divided signal by doubling a period of the base periodic signal, and a next frequency divider of the plurality of frequency dividers receives an output signal of a previous frequency divider in order to generate a next divided signal by doubling a period of the output signal of the previous frequency divider; an internal voltage generation control signal generation means for generating an internal voltage generation control signal in response to the plurality of divided signals; and an internal voltage generation means for generating an internal voltage in response to the internal voltage generation control signal, wherein the internal voltage generation control signal generation means includes: a first logic gate for performing a NAND operation of the base periodic signal and the plurality of divided signals; a first inverter for inverting an output signal of the first logic gate; a second logic gate for performing a NAND operation of inverted signals of the base periodic signal and the plurality of divided signals; a second inverter for inverting an output signal of the second logic gate; a third logic gate for performing a NOR operation of output signals of the first inverter and the second inverter; and a third inverter which receives an output signal of the third logic gate in order to output the internal voltage generation control signal.