Patent ID: 8030099

Claim:
A method for determining time to failure characteristics of an on-chip interconnect subject to electromigration, comprising the steps of: providing a test structure comprising a parallel connection of a plurality of such on-chip interconnects; and performing at least two electromigration tests on the test structure, wherein each test comprises: applying a particular current density and a particular sample temperature to the test structure and measuring a first electrical resistance, applying a first alternating current with a first root mean square (RMS) value to anneal the test structure, applying a second alternating current with a second RMS value greater than the first RMS value and measuring a second electrical resistance greater than the first resistance, adjusting an oven temperature to a particular oven temperature and measuring a third electrical resistance that is substantially equal to the first electrical resistance, based on the particular oven temperature, determining a thermal resistance of the test structure for the particular current density and the particular sample temperature, and applying a direct current with a third RMS value substantially equal to the second RMS value and determining a plurality of electrical resistance measurements of the on-chip interconnects while approximately maintaining the particular stress temperature using the thermal resistance; and based on the resistance measurements of each test, determining at least one time to failure characteristic of the test structure.