Patent ID: 7756231

Claim:
A digital clock generation circuit, comprising: a digital clock configurable to produce an output at either one of a first frequency and a second frequency, the second frequency being different from the first frequency; a clock control circuit controlling the digital clock and selectively setting the digital clock to produce the output at one of the first frequency and the second frequency; an excess pulse counter, communicatively coupled to the clock control circuit and the digital clock, the excess pulse counter determining a number of pulses produced by the digital clock at the second frequency that differs from the number of pulses that would have been produced by the digital clock at the first frequency; an output phase correction circuit, communicatively coupled to the digital clock, the excess pulse counter, and the clock control circuit, the output phase correction circuit removing, in response to the clock control circuit commanding the digital clock to change from producing an output at the second frequency to producing an output at the first frequency, the number of pulses from the output that were counted by the excess pulse counter; and a fixed frequency clock producing a fixed frequency output at a third frequency, wherein the digital clock accepts a reference base clock input at a reference frequency, wherein the digital clock produces the output at the first frequency by dividing the reference frequency by a first integer and produces the output at the second frequency by dividing the reference frequency by a second integer, and wherein the fixed frequency clock produces the fixed frequency output by dividing, when the output is produced at the first frequency, a frequency of the output by a first factor and by dividing, when the output is produced at the second frequency, the frequency of the output by a second factor, the value of the first integer multiplied by the first factor being equivalent to the second integer multiplied by the second factor.