Patent ID: 7420485

Claim:
A sigma-delta modulator, comprising: a data input configured to receive a data word; a first modulation stage comprising at least two adders; at least one further modulation stage comprising at least two adders; and a modulator output configured to output a bit stream; wherein a first adder in the first modulation stage comprises a first input configured to receive a low-significance component of the data word, a second input configured to a delayed first result from the first adder and an output configured to output the first result with a carry; wherein an at least one second adder in the first modulation stage comprises a first input configured to receive a delayed more significant component of the data word, a second input configured to receive a delayed second result from the at least one second adder, a third input configured to receive a delayed carry from a preceding adder and an output configured to output the second result with a carry; wherein the results from the adders in the first modulation stage form a result word which is provided to the adders of the further modulation stage with an unvarying delay therebetween; wherein a first adder in the further modulation stage comprises a first input configured to receive a low-significance component of the result word, a second input configured to receive a delayed first interim result from the first adder, and an output configured to output the first interim result with a carry; wherein an at least one second adder in the further modulation stage comprises a first input configured to receive a more significant component of the result word, a second input configured to receive a delayed second interim result from the at least one second adder, a third input configured to receive a delayed carry from a preceding adder and an output configured to output the second interim result with a carry; and wherein the bit stream is derived from a carry from a final one of the at least two adders in the first modulation stage and from a carry from a final one of the at least two adders in the further modulation stage.