Patent ID: 7998823

Claim:
A method, comprising: forming an active semiconductor region bordered by an isolation trench, said active semiconductor region defining a first PN junction and a second PN junction with a well region of said semiconductor region, said first PN junction defining a first junction depth, said second PN junction defining a second junction depth within a central area of said active semiconductor region; forming a third PN junction in said well region at a location proximate a contact region prior to forming the first and second PN junctions and prior to forming any contact opening adjacent to said active semiconductor region, said third PN junction having a third junction depth at said isolation trench, said third junction depth being greater than either of said first and second junction depths, wherein said third PN junction is formed by a doped region abutting said isolation trench, and wherein forming said active semiconductor region comprises performing a first implantation process for defining said first junction depth, a second implantation process for defining said second junction depth and a third implantation process for defining said third junction depth; providing a resist implantation mask covering at least said central region of said active semiconductor region and performing said third implantation process on the basis of said resist implantation mask, wherein said resist mask at least exposes a landing area for forming a contact plug on said contact region, and said landing area is selected to include at least a maximum allowed misalignment that may occur during the formation of said contact opening; forming a dielectric layer over said contact region; forming a contact opening in said dielectric layer to communicate with said contact region; and filling said contact opening with a conductive material.