Patent ID: 7966544

Claim:
A process comprising: loading an input memory of an LDPC decoder with data corresponding to an LDPC frame to be decoded and comprising a number N of log-likelihood ratios, or LLRs, of which a number K are information LLRs and a number N−K are parity LLRs, where N and K are integers, wherein: at least one stream is formed of binary words of a first type, each corresponding to multiple information LLRs, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out (FIFO) ring buffer, and first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and second memory accesses are made in page mode in order to write the binary words of the second type to a second zone of the input memory.