Patent ID: 7756148

Claim:
A computer-implemented method for generating synthesizable code representing a multi-threaded first-in first-out (FIFO) storage memory, comprising: generating a first portion of the synthesizable code, wherein the first portion represents a sender interface with a first thread identifier input port and a write data input port that is configured to receive data for multiple execution threads; generating a second portion of the synthesizable code, wherein the second portion represents a storage resource configured to store the data for the multiple execution threads in a shared memory; generating a third portion of the synthesizable code, wherein the third portion represents a receiver interface with a second thread identifier input port, a speculative read port that is configured to provide a rollback capability for entries in the storage resource, and a read data output port that is configured to output the data for the multiple execution threads that corresponds to a thread identifier received by the second thread identifier input port; and configuring the multi-threaded FIFO storage memory based on at least one of the first portion, the second portion, or the third portion.