Patent ID: 7154979

Claim:
A method of enhancing jitter tolerance in a communications network, comprising: providing at least two non-linear paths, a first of said non-linear paths to adjust a phase of an input data in response to a data pattern of said input data, and a second of said non-linear paths to adjust said phase of said input data in response to an amplitude of data samples from said input data, and a phase locked loop to lock a phase of a clock to said phase of said input data; inputting said input data to said communications network; estimating a phase error based on said data samples from both a center of a data eye of said input data and from a phase sample from said input data half-a-baud later in time, said data samples and said phase sample being derived from said input data; correlating said phase error with a sign of recovered data to provide a correlated phase error, the sign being a positive or negative value; filtering said correlated phase error by a loop filter to generate an output; summing said output with output from said at least two non-linear paths to generate a summed output; and converting said summed output into clock phase information.