Patent ID: 7017009

Claim:
A cache memory device, provided between a CPU and a main memory, for operating as a fast buffer memory, said cache memory device comprising: a cache section for storing a tag and data as a pair; and a control circuit having a data attribute determining function, wherein input data is stored in said cache section when said control circuit determines that attribute information affixed to said input data by a Direct Memory Access (DMA) indicates a predetermined attribute, said input data is transferred to said main memory when said control circuit determines that said attribute information of said input data does not indicate said predetermined attribute, and when there is a reading access or an external writing access, said cache section is accessed first, and, in a case where a mishit occurs and said control circuit determines that attribute information of data to be accessed indicates said predetermined attribute, a block to be replaced is selected from said cache section by a predetermined method and a tag and data of said block to be replaced are replaced with a tag of an access address where said reading or writing access has been made and data is stored at an access address of said main memory, then a process for said reading or writing access is executed, and, in a case where a mishit occurs and said control circuit determines that said attribute information of said data to be accessed does not indicate said predetermined attribute, permitting transmission and reception of those address and data which are associated with said reading or writing access to and from said main memory without intervention of said cache section.