Patent ID: 8804757

Claim:
A chip, comprising: block compare logic to simultaneously compare a source block against multiple reference blocks from one or more reference windows for a reference frame, the reference blocks organized into a plurality of search units, each search unit defining at least two macro blocks, wherein a macro block comprises a block of 8 by 8 pixels or 16 by 16 pixels, and wherein the one or more reference window has a plurality of different search units; and control logic coupled to the block compare logic to control it to execute block comparisons and generate error information for blocks in search units, wherein search units are selected in accordance with both fixed path navigation and adaptive path navigation, wherein fixed path navigation comprises a predefined sequence of search units based on the source block's position within a current frame where the search units are predefined before searching the source block begins, wherein adaptive path navigation comprises search units that are dynamically determined based on prior comparison results and wherein adaptive path navigation is synchronized with fixed path navigation by taking into account conditions associated with the fixed path navigation.