Patent ID: 7395408

Claim:
A parallel execution processor comprising: a plurality of processing elements; an obtaining unit operable to obtain an instruction sequence including one or more instructions; a decoding unit operable to decode the obtained instruction sequence into the one or more instructions; a group forming unit operable to form the processing elements into as many groups as the number of instructions included in the instruction sequence; a plurality of register files, each of which corresponds to a different one of the processing elements; and an execution controlling unit operable to assign the one or more instructions decoded by the decoding unit to the groups of the processing elements, so that each group of the processing elements receives a different one of the one or more instructions, and control the processing elements so that (i) the instructions received by the groups of the processing elements are executed in parallel, (ii) in each group, all processing elements in the group each execute the same instruction received by the group, and (iii) each processing element receives data from a different register file.