Patent ID: 6852471

Claim:
A method of manufacturing an integrated circuit (IC) product comprising: exposing a pattern in at least one layer of material in the IC using at least two mask patterns, the first mask pattern comprising a phase shifting pattern and the second mask pattern comprising a trim pattern, the phase shifting pattern defining substantially all of the pattern of the layer of material and the trim pattern for protecting the pattern defined using the phase shifting pattern and clearing phase shifting artifacts; said exposing using an optical lithography exposure system having a setting of values of a set of one or more optical parameters that control characteristics of exposures, to the first mask pattern and the second mask pattern, where said setting of values is substantially the same while exposing the first and second mask patterns, and using a first dosing for the first mask pattern and a second dosing for the second mask pattern, the first dosing and the second dosing being in a ratio of 1.0 to r, wherein 2.0<=r<=4.0.