Patent ID: 8610193

Claim:
A NAND unit cell, comprising: a first vertical column comprising alternating plurality of control gate structures and insulative material structures; second and third vertical columns on opposing sides of the first vertical column relative to one another, the second and third vertical columns comprising semiconductor material containing alternating n-type doped regions and p-type doped regions; the n-type doped regions of the second vertical column being horizontally aligned with the n-type doped regions of the third vertical column, and the p-type doped regions of the second vertical column being horizontally aligned with the p-type doped regions of the third vertical column; the control gate structures being horizontally aligned with either the n-type doped regions or the p-type doped regions; vertically-extending as an upwardly opening container layers of a tunnel dielectric, a charge-storage material, and a charge- blocking material between the first column and each of the second and third columns, the control gate structure and the insulative material structure being within said container; wherein at least one of the control gate structures, together with n-type and p-type doped regions of the second and third vertical columns, is incorporated into a string device of the NAND unit cell; wherein a first control gate structure of the plurality of control gate structures within the container is spaced from a second control gate structure of the plurality of control gate structures within the container that is immediately adjacent the first control gate structure only by the electrically insulative material and wherein the forming of the alternating layers of electrically insulative material and electrically conductive material comprises forming the first control gate structure above the layer of charge-blocking material and forming the second control gate structure above the first control gate structure.