Patent ID: 6882188

Claim:
A feedback control I/O buffer driven by a system voltage, comprising: an input/output circuit comprising a first PMOS transistor and a first NMOS transistor and having a transmission terminal coupled to an I/O pad, wherein the first PMOS transistor has an N-well region, a gate of the first NMOS transistor receives a first gate control signal, and a drain of the first PMOS transistor serves as the transmission terminal; a P-gate control circuit conveying a second gate control signal to the gate of the first PMOS transistor; a feedback detection device having an input coupled to the transmission terminal to output a feedback signal according to an input voltage at the I/O pad; and an N-well control circuit coupled to the P-gate control circuit to control the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device, wherein the N-well control circuit comprises: a second PMOS transistor having a source coupled to the I/O pad, a gate coupled to the system voltage, and a drain coupled to the N-well region of the first PMOS transistor; a third PMOS transistor having a Rate coupled to the system voltage, a source coupled to the I/O pad, and a drain; a fourth PMOS transistor having a gate coupled to the drain of the third PMOS transistor, a drain coupled to the system voltage, and a source coupled to the N-well region of the first PMOS transistor; a third NMOS transistor having a gate coupled to the feedback signal from the feedback detection device, and a source coupled to the ground, and a fourth NMOS transistor having a gate coupled to the system voltage, a source coupled to a drain of the third NMOS transistor, and a drain coupled to the gate of the fourth transistor.