Patent ID: 8203900

Claim:
A data serializer, comprising: a logic system configured to receive a plurality of parallel data digits and a corresponding plurality of clock signals having different phases, the logic system being configured to generate a plurality of data sample signals each of which has a respective value corresponding to the value of respective one of the parallel data digits, the logic system being configured to generate each of the data sample signals at a respective time corresponding to a transition of a respective one of the clock signals; a switching circuit comprising a plurality of switches coupled to each other in parallel between an output node and a first voltage, each of the switches being coupled to the logic system to receive a respective one of the data sample signals, each of the switches being configured to be controlled by the received data sample signal; and a bias element coupled to the output node and being configured to bias the output node to a second voltage that is different from the first voltage, the output node being maintained at the second voltage by the bias element if none of the switches are closed, the output node being maintained at the second voltage when none of the switches are closed without switching any voltage to the output node.