Patent ID: 8278712

Claim:
A cellular transistor, comprising: an N-type heavily doped (N+) buried layer (NBL); an N-well connected to said NBL and formed after formation of said NBL; a first N+ layer connected to said N-well and formed after formation of said N-well; a P-well partially surrounded by said NBL and said N-well; a plurality of drains formed on and adjacent to said P-well, wherein each drain of said drains comprises a second N+ layer and is connected to said NBL via said N-well and said first N+ layer; and a source formed on said P-well, wherein said source comprises a third N+ layer configured to form a conducting channel between said second N+ layer of said each drain and said third N+ layer of said source, wherein a breakdown voltage of said cellular transistor increases if a drain voltage at said drains increases.