Patent ID: 7325206

Claim:
A method comprising enabling a generation of an electronic design using a pattern-dependent model to predict thickness or topographical variation within an integrated circuit that is to be fabricated in accordance with the electronic design by a method that includes (a) a fabrication process that will impart thickness or topographical variation with respect to the integrated circuit, and (b) a lithography or etch process that will form shapes or patterns of conductive and/or non-conductive features corresponding to the electronic design on a surface and making the predicted thickness or topographical variation available to the pattern-dependent model for predicting width variation in features that correspond to the electronic design for use in evaluating or adjusting the electronic design, in which the width variation comprises at least one of the shapes or patterns having an intended width dimension which corresponds to a predicted different width dimension based upon interaction between the lithography or etch process and the thickness or topographical variation at different locations on a die.