Patent ID: 8462553

Claim:
A two-transistor FLOTOX EEPROM cell that prevents punch-through and high voltage disturbances during cell programming comprising: a select transistor having a drain connected to a bit line and a gate connected to a word line; and a floating gate thin oxide transistor having a drain merged with a source of the select transistor, a source connected to a source line, and a gate connected to a gated word line; wherein the bit line and the source line are parallel and the bit line and the source line are perpendicular to the word line and the gated word line; wherein, during a programming operation of an associated selected two-transistor FLOTOX EEPROM cell, in which the two-transistor FLOTOX EEPROM cell is not selected, a very large programming voltage is applied to the bit line and a punch through inhibit programming voltage is applied to the source line such that a drain-to-source voltage of the select transistor and the floating gate thin oxide transistor is less than a drain-to-source breakdown voltage of the select transistor and the floating gate thin oxide transistor.