Patent ID: 7795073

Claim:
A method for manufacturing a wafer level stack package, comprising: back-grinding a lower surface of a wafer comprising a plurality of first semiconductor chips, the first semiconductor chips being at a wafer level; attaching a support member to a lower surface of the back-grinded wafer; stacking one or more individual second semiconductor chips over corresponding ones of the first semiconductor chips by interposing an adhesive or an adhesive tape between adjacent stacked semiconductor chips of the first and second semiconductor chips; forming first through-electrodes to electrically connect the first semiconductor chips to the corresponding one or more second semiconductor chips; attaching third semiconductor chips to respective uppermost ones of the stacked second semiconductor chips, the third semiconductor chips having second through-electrodes electrically connected to the first through-electrodes and re-distribution lines electrically connected to the second through-electrodes; attaching outside connection terminals to the re-distribution lines of the third semiconductor chips; and sawing the first semiconductor chips of the wafer level having the corresponding second and third semiconductor chips stacked thereon, such that the first semiconductor chips are at a chip level.