Patent ID: 8039349

Claim:
A method for fabricating a semiconductor device including a substrate, an N-type non-planar transistor having a first plurality of fin structures, and a P-type non-planar transistor having a second plurality of fin structures, the method comprising the steps of: selectively amorphorizing a portion of each fin structure included within the first plurality of fin structures utilizing at least a first angled ion implantation process; depositing a first sacrificial strain layer over the first plurality of fin structures to apply stress to the amorphized portions thereof; annealing the non-planar semiconductor device to recrystallize the amorphized portion of each fin structure included within the first plurality of fin structures in a stress-memorized state; removing the first sacrificial strain layer; selectively amorphorizing a portion of each fin structure included within the second plurality of fin structures utilizing at least a second angled ion implantation process; depositing a second sacrificial strain layer over the second plurality of fin structures to apply stress to the amorphized portions thereof; annealing the non-planar semiconductor device to recrystallize the amorphized portion of each fin structure included within the second plurality of fin structures in a stress-memorized state; removing the second sacrificial strain layer; and forming a plurality of gate stacks overlying the first and second pluralities of raised crystalline structures, the step of forming a plurality of gate stacks performed after the steps of annealing.