Patent ID: 7366012

Claim:
A synchronous non-volatile memory device, including: a non-volatile memory; circuit means for performing operations on the memory, the circuit means comprising a power circuit that comprises voltage boosting circuit blocks or current generators that operate in a stand-by condition at a first level of power consumption and in an active condition at a second level of power consumption that is higher than the first level of power consumption; means for receiving and processing a request of operation and operative information required for performing the operation in temporal succession, the request of operation received when the power circuit is in the stand-by condition; wherein the means for receiving includes a communication interface for interfacing the memory device with an external bus, the external bus having a data transfer parallelism lower than an internal data transfer parallelism of the memory device activation means for activating the circuit means, including the power circuit, in response to the request of operation, the activation means activating the circuit means from the stand-by condition to the active condition while the receiving means is processing the request of operation and operative information; means for enabling the execution of the operation in response to the operative information, and deactivation means for automatically deactivating the circuit means, including the power circuit, to the stand-by condition in response to the completion of the operation.