Patent ID: 7372335

Claim:
A circuit comprising: a first stage having an output terminal, the output terminal having a corresponding first parasitic capacitance; a second stage having an input terminal, the input terminal having a corresponding second parasitic capacitance; and a passive network having an input terminal coupled to the output terminal of the first stage and an intermediate node coupled to the input terminal of the second stage, wherein the first parasitic capacitance is included as the input capacitance of the passive network, and the second parasitic capacitance is included as the capacitance of the intermediate node of the passive network, and wherein the second parasitic capacitance is the largest capacitance in the passive network, and wherein the passive network comprises one or more first inductors, at least one capacitor, one or more second inductors, and a resistor, and wherein the one or more first inductors, the one or more second inductors, the at least one capacitor, the resistor, and the first and second parasitic capacitances are configured as a fourth order or greater ladder network having the resistor coupled to a last node of the network.