Patent ID: 7093152

Claim:
A semiconductor device, comprising: a clock generation unit which generates a clock signal; a first module which asserts a clock-control request signal; one or a plurality of second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof, upon completion of a currently performed operation, in response to the assertion of the clock-control request signal; an on-chip bus; a plurality of modules connected to said on-chip bus; and a bus arbiter which arbitrates a bus right between bus masters that are some of said plurality of modules, wherein said bus arbiter is one of said one or said plurality of second modules, and asserts the clock-control acknowledge signal as a response to the assertion of the clock-control request signal from said first module after refusing to grant the bus right to any one of the bus masters upon completion of a currently performed transfer operation on said on-chip bus, wherein said clock generation unit selectively changes the clock signal supplied to said one or said plurality of second modules in response to assertion of all the clock-control acknowledge signals output from said one or said plurality of second modules including said bus arbiter.