Patent ID: 7565510

Claim:
A microprocessor executing an unaligned load instructions and another load instruction, said another load instruction being subsequent instruction to the unaligned load instruction, the microproccessor comprising: a memory including a plurality of data lines; an input register storing data included in data lines; a saved register capable of storing the data from the input register; an evaluation unit determinig whether an instruction to be executed is the unaligned load instruction or not, the saved register being coupled to the input register to receive the data when the evaluation unit determines the instruction to be executed is the unaligned load instruction; and a merge unit coupled to the memory and to the saved register to merge the data with other data stored in the memoery when the instruction to be executed is the unaligned load instruction, wherein the merge unit merges the data with the other data after an access to the memory for said another load instruction,and wherein when the evaluation unit determines that the instruction to be executed is the unaligned load instruction, the evaluation unit saves the data stored in the input register to the saved register so as to make the input register available to subsequent instructions.