Patent ID: 8880965

Claim:
A low power scan flip-flop cell operable in a functional mode and a scan mode, comprising: a multiplexer for receiving a data input (D) signal and a scan input (SI) signal, and generating a first data signal depending on a scan enable (SE) signal; a master latch, connected to the multiplexer, for receiving the first data signal and generating a first latch signal; a scan slave latch, connected to the master latch, for receiving the first latch signal and generating a scan output (SO) signal; and a data slave latch, connected to the master latch and receiving the first latch signal, for generating a Q output depending on the SE signal and the first latch signal, wherein the Q output is maintained at a predetermined level during the scan mode, and wherein the data slave latch comprises: a first tri-state inverter, a first normal inverter, a second tri-state inverter and a first transistor, wherein the first normal inverter and the second tri-state inverter are connected in a loop, and the first tri-state inverter and the first transistor are connected in series and disposed between a power supply node (VDD) and ground (VSS), wherein the first tri-state inverter receives the first latch signal and generates a second data signal (/Q) at a first connection node connected to an input of the first normal inverter and an output of the second tri-state inverter, and wherein the Q output is generated at a second connection node connected to an output of the first normal inverter and an input of the second tri-state inverter, and wherein the first and second tri-state inverters are controlled by a clock signal.