Patent ID: 8300464

Claim:
A method comprising: writing data comprising a first plurality of bits to a first memory, a first portion of the first plurality of bits being predetermined to match in a comparison with a second plurality of bits stored in a second memory, and a second portion of the first plurality of bits being predetermined to not match in a comparison with the second plurality of bits; setting a time delay of a gating signal to a first value, the gating signal for aligning data read from the first memory to a clock signal; serially reading the first plurality of bits from the first memory; comparing the first plurality of bits to the second plurality of bits; detecting if a transition from the first portion of the first plurality of bits to the second portion of the first plurality of bits occurs within a time period; if the transition occurs within the time period, resetting the first value of the time delay of the gating signal by a second value; and if the transition occurs outside of the time period, adjusting the delay of the gating signal to a third value and repeating the steps of serially reading, comparing, detecting, and adjusting until the transition occurs within the time period.