Patent ID: 6900537

Claim:
A hybrid field effect transistor package for use in a power circuit, comprising: a gate contact; a source contact; a drain contact; a silicon carbide semiconductor die consists of one of a junction field effect transistor and a metal semiconductor field effect transistor, the silicon carbide semiconductor die having three electrodes including a source electrode, a gate electrode and a drain electrode, each of the three electrodes being on one of a top surface and a bottom surface of the silicon carbide die and the drain electrode being electrically connected to the drain contact; and a silicon metal oxide semiconductor field effect transistor comprising a doped silicon substrate and three electrodes including a source electrodes a gate electrode and a drain electrode, each of the three electrodes being on one of an upper surface and a lower surface of the silicon transistor, the gate electrode of the silicon transistor being electrically connected to the gate contact, the drain electrode of the silicon transistor being electrically connected with the source electrode of the silicon carbide die and the source electrode of the silicon transistor being electrically connected to both the source contact and the gate electrode of the silicon carbide die; wherein one of the three electrodes of the silicon carbide die is mounted over at least a portion of one of the three electrodes of the silicon transistor or one of the three electrodes of the silicon transistor is mounted over at least a portion of one of the three electrodes of the silicon carbide die.