Patent ID: 8335810

Claim:
A processor comprising: a decoder for decoding instructions and activating an execution unit to perform mathematical operations, wherein the execution unit comprises: an Arithmetic Logic Unit (ALU) for performing mathematical operations of the processor; a unidirectional rotator configured to shift or rotate data in one direction; and a first multiplexer responsive to the decoder activation, wherein the first multiplexer switches the output of the ALU and the unidirectional rotator to a pipeline including a plurality of stages; a general register file for storing data from memory; a second multiplexer configured to select a shift value to shift or rotate the data in the one direction from one of a first input responsive to the general register file, a second input responsive to the pipeline, a third input responsive to the decoder, and a fourth input responsive to a shift correction logic; a control unit configured to determine whether an instruction is a first register-based instruction to shift or rotate the data in the one direction, a second register-based instruction to shift or rotate the data in an opposite direction, or an instruction-based shift or rotate instruction that includes a number of bit positions to shift the data; the shift correction logic configured to modify the shift value when the instruction is the second register-based instruction, the modified shift value being usable by the unidirectional rotator to shift or rotate the data in the one direction by the modified shift value to generate the same result as if the data in the unidirectional rotator had otherwise been shifted or rotated in the opposite direction by the shift value; and a latch including an input responsive to the second multiplexer and an output coupled to the shift correction logic, wherein the latch is configured to receive the shift value and is further configured to selectively provide the shift value to one of the shift correction logic and the unidirectional rotator to selectively bypass the shift correction logic, and wherein the shift correction logic is bypassed in response to a determination of the control unit that the instruction is the first register-based instruction to shift or rotate the data in the one direction or the instruction-based shift or rotate instruction.