Patent ID: 7358787

Claim:
A dual purpose current mode logic (“CML”) latch circuit, comprising: a CML latch having a first section operable to receive at least a pair of differential input data signals and a second section including a pair of cross-coupled devices, the CML latch being operable to generate at least one output signal in accordance with the states of the pair of differential input data signals; a first tail device for controlling a flow of current to operate the first section of the CML latch, the first tail device being operable to receive a first differential clock signal; a second tail device for controlling a flow of current to operate the second section of the CML latch, the second tail device being operable to receive a second differential clock signal, the first and second differential clock signals representing a single clock signal; and a mode control device operable to receive a mode control signal to operate the CML latch as a buffer or as a latch, such that when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the first and second differential clock signals, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.