Patent ID: 7877675

Claim:
A semiconductor memory apparatus capable of detecting an error in data input/output, comprising: a memory cell block including a plurality of memory cells; a data input unit configured to receive data from outside the semiconductor memory apparatus and perform predetermined signal processing to record the received data in the memory cell block; a first global data line coupled between the data input unit and the memory cell block; a data output unit configured to receive data from the memory cell block and perform predetermined signal processing to output the received data to the outside of the semiconductor memory apparatus; a second global data line coupled between the memory cell block and the data output unit; a multiplexer configured to selectively output data from the first or second global data line in response to a control signal; and an error detection code generator configured to generate an error detection code having a plurality of bits to indicate whether the data output from the multiplexer includes an error, and output the error detection code to the outside of the semiconductor memory apparatus.