Patent ID: 7318207

Claim:
A method for verifying layout interconnections comprising: (a) extracting a loop circuit as a loop portion in a first circuit model, wherein said first circuit model of a semiconductor design, includes: branch interconnections which includes first branch interconnections included in said loop portion and other branch interconnections as second branch interconnections, first nodes, each of which is connected with an edge of corresponding one of said branch interconnections, and terminals of circuit elements, each of which is connected with said edge of corresponding one of said branch interconnections; (b) replacing said loop portion with a second node to generate a second circuit model which does not have said loop portion, based on said first circuit model; (c) calculating a second current value of each of said second branch interconnections, based on said second circuit model; (d) generating a third circuit model of said loop portion, based on said first interconnections; (e) calculating a first current value of each of said first branch interconnections, based on said third circuit model; and (f) comparing said first and second current value with a predetermined current value to carry out verification.