Patent ID: 8445918

Claim:
A circuit arrangement, comprising: a plurality of semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer, and wherein each semiconductor die includes a semiconductor substrate; and an array of conductive through vias disposed in each of the plurality of semiconductor dies, the array of conductive through vias in each semiconductor die extending through such semiconductor die, wherein a first subset of the conductive through vias are configured as data-carrying through vias that are coupled to the circuit layer on such semiconductor die to communicate data between the circuit layer on such semiconductor die and another circuit layer disposed on another semiconductor die in the stack, wherein a second subset of the conductive through vias are configured as power-carrying through vias that are coupled to a power distribution network for the circuit layer on such semiconductor die, wherein a third subset of the conductive through vias are configured as thermal-only through vias that are non-data-carrying and non-power-carrying and that conduct thermal energy generated by the circuit layers within the stack, and wherein the thermal-only through vias in each semiconductor die are electrically isolated from the power distribution network and any generated data signals for the circuit layer on such semiconductor die, extend between the opposing faces of such semiconductor die, and have higher thermal conductivity than the semiconductor substrate of such semiconductor die.