Patent ID: 8681526

Claim:
A multi-synchronous first in first out memory, comprising: a memory having a selectable number of addressable memory locations for storing information, the selectable number of addressable memory locations being a programmable size of the first in first out memory specifiable in increments of one addressable memory location up to a maximum number of addressable memory locations; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the memory locations using a read address that is cyclical to the programmable size; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions configured to write to one or more of the memory locations using a write address that is cyclical to the programmable size; selectable transaction retry control means configured to cause the read control means to repeat selected pop transactions and/or cause the write control means to repeat selected push transactions; and a transaction register storing the next addressable memory location and a start register storing the starting address for a transaction, wherein retrying the transaction in the same clock cycle in which the retry signal is asserted causes the transaction register to latch the next addressable memory location after the starting address instead of the starting address, the selectable transaction retry control means being enabled, or initiated and stopped, without impacting original read or write status of the first in first out memory.