Patent ID: 8102007

Claim:
A pFET synapse transistor, comprising: a readout transistor for injecting electrons into a floating gate, the readout transistor comprising: a p− doped substrate including: a first n− well; a first p+ doped region disposed in said first n− well forming a first source; a second p+ doped region disposed in said first n− well forming a first drain, a number of electrons injected into the floating gate increased when a voltage difference between the first source and the first drain is increased; and a channel disposed in said first n− well between said source and said drain; a first layer of gate oxide above said channel and said first n− well; and a first polysilicon floating gate disposed above said layer of gate oxide; and a shorted transistor for removing electrons from the floating gate, the shorted transistor comprising: a p− doped substrate including a second n− well, a second drain within the second n− well, and a second source within the second n− well, wherein the second drain comprises a third p+ doped region within the second n− well, and the second source comprises a fourth p+ doped region; a second layer of gate oxide above said first n− well; a second polysilicon floating gate above said second layer of gate oxide, the second polysilicon floating gate connected to the first polysilicon floating gate; and a conductor connecting the second drain and the second source, wherein a number of electrons removed from the second polysilicon floating gate is increased when voltage at the second drain or the second source is increased, wherein the conductor comprises a conductive layer which forms a bridge over said second polysilicon floating gate.