Patent ID: 7961516

Claim:
A NAND flash memory comprising blocks which are units of writing and deletion of data, the block comprising: memory cells from which data corresponding to values of held threshold voltages can be read by applying a reading voltage to control gates of the memory cells; source-side selection gate transistors connected between a common source line and the memory cells; drain-side selection gate transistors connected between a bit line and the memory cells; and monitor cells which are configured as the memory cells and have a threshold voltage set according to monitor data, and from which data corresponding to values of held threshold voltages can be read by applying a decision voltage to control gates of the monitor cells, wherein first data corresponding to the values of the threshold voltages held by the monitor cells is read by applying the decision voltage to the control gates of the monitor cells, the first data being read from the monitor cells and the monitor data are compared with each other, second data stored in all the memory cells in the block is read according to a result of comparison between the first data read from the monitor cells and the monitor data, and the second data is stored again in the memory cells of the block or another block.