Patent ID: 7482226

Claim:
A manufacturing method of a semiconductor memory device comprising the steps of: forming a gate electrode by patterning on a semiconductor substrate via a gate insulating film; forming one diffusion layer by doping impurities into such a surface layer of the semiconductor substrate that is at one side of the gate electrode; forming a lightly-doped impurity region by doping impurities into such a surface layer of the semiconductor substrate that is at other side of the gate electrode at a concentration lower than the concentration of the other side of the gate electrode; forming a pair of sidewall films on side surfaces of the gate electrode; and forming a heavily-doped impurity region partially overlapping the lightly-doped impurity region by doping a high concentration of impurities into such a surface layer of the semiconductor substrate that is at the other side of the sidewall film as well as the gate electrode to thereby form other diffusion layer composed of the lightly-doped impurity region and the heavily-doped impurity region.