Patent ID: 7982155

Claim:
A method of manufacturing semiconductor devices, comprising: conducting a manufacturing procedure on a plurality of working substrates with a plurality of shot areas arrayed on each of the working substrates, a predetermined number of the working substrates implementing one of a plurality of lots, wherein the lots, the working substrates and the shot areas implement a testing-hierarchy of testing-position levels; classifying the lots into a plurality of groups, each of the groups having a different set of testing positions along the testing-position levels in the testing-hierarchy, each of the groups including a plurality of wafers; creating a test recipe of a subject group to be tested next to a previous group based on analysis information of a variation of defects in a specified testing-position level in the previous group, the test recipe including a set of testing-position levels in the subject group defined by a rule with different set of numbers of the testing positions in each of the testing-position levels from the previous group; assigning a plurality of testing apparatuses to each of the groups, according to test recipes created for each of the groups; and testing defects in the subject group based on the test recipe.