Patent ID: 8576656

Claim:
A latency counter that counts a latency of an internal command, the latency counter comprising: a counter circuit that counts a clock signal; and a point-shift FIFO circuit, wherein the point-shift FIFO circuit includes: a plurality of latch circuits that latch the internal command; an input selecting circuit that supplies the internal command to one of a plurality of signal paths based on a count value of the counter circuit; a shift circuit that supplies the internal command on one of the signal paths to a predetermined one of the latch circuits based on a preset correspondence relation between the signal paths and the latch circuits; and an output selecting circuit that outputs the internal command stored in one of the latch circuits based on the count value of the counter circuit, wherein each of the latch circuits is an SR latch circuit that is set in response to activation of the internal command and is reset in response to activation of a different count value of the counter circuit from the corresponding count value.