Patent ID: 7482230

Claim:
A method of forming a recess channel transistor in a semiconductor substrate having an activation region defined by adjoining device insulation regions, the method comprising the steps of: etching gate forming portions in the activation region, so as to form first recesses; etching the device insulation regions, so as to form trenches; filling each trench and each first recess with an insulation layer; etching a center portion of the insulation layer filled inside each first recess and continue etching the semiconductor substrate under the etched center portion of the insulation layer, so as to make second recesses that are deeper than the first recesses, wherein the unetched portions outside the etched center portion of the insulation layer remaining at near the opening of each second recess forms insulation buffer patterns; forming a gate insulation layer on an inner wall of each second recess, excluding the surface of the insulation buffer patterns; forming a gate conductive layer on the whole surface of the substrate having the second recesses and the insulation buffer patterns; etching the gate conductive layer, so as to form the gates such that each gate comprises a recess gate formed inside one second recess and a top gate formed on the recess gate; forming spacers at both sidewalls of each gate; and performing source/drain ion implant on the resultant of the substrate, so as to form a source region and a drain region at both sides of each gate in the substrate, wherein the source and drain regions have an even doping profile due to an existence of insulation buffer patterns.