Patent ID: 7142025

Claim:
A phase difference detector adapted to generate a phase difference signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having an output terminal to provide a first output signal; a second bistable element clocked by the second signal and having an output terminal to provide a second output signal; means for determining a change of said phase difference signal, responsive to said first and second output signals; a reset circuit having first and second input terminals respectively connected to receive said first and second output signals and adapted to determine a resetting of the first and the second bistable elements responsive to an attainment of a respective prescribed state of the first and the second output signals, said first and second input terminals of the reset circuit substantially symmetrical to each other from a point of view of a respective input impedance associated with each of them; and a symmetrization element coupled to the output terminals of the first and second bistable elements, the symmetrization element including first and second transistors, the first transistor having a control terminal coupled to the output terminal of the first bistable element and having a first terminal, the second the transistor having a control terminal coupled to the output terminal of the second bistable element and having a first terminal coupled to the first terminal of the first transistor.