Patent ID: 7336754

Claim:
A clock and data recovery circuit having a frequency tracking loop and a phase tracking loop, said clock and data recovery circuit comprising: a phase detector comparing a phase of an input data signal with a phase of a synchronous clock signal; a phase interpolator receiving an input clock signal and a control signal, adjusting a phase of an output clock signal based on the control signal, and supplying the output clock signal to said phase detector as the synchronous clock signal, said phase detector and said phase interpolator owned in common by said frequency tracking loop and said phase tracking loop; a pattern generator generating a signal for variably setting the phase of the output clock signal from said phase interpolator based on a result of phase comparison by said phase detector and outputting the so generated signal, said pattern generator provided in said frequency tracking loop; and a circuit generating the control signal to said phase interpolator based on a result of phase detection by said phase tracking loop and said outputted signal of said pattern generator in said frequency tracking loop.