Patent ID: 7668035

Claim:
A memory circuit comprising: a global read bit line; a global read bit line latch; a plurality of sub-arrays, each of said sub-arrays comprising: a first local read bit line; a first local write bit line; a first plurality of memory cells interconnected with said first local read bit line and said first local write bit line, said first local read bit line being decoupled from said first local write bit line; a second local read bit line; a second local write bit line; a second plurality of memory cells interconnected with said second local read bit line and said second local write bit line, said second local read bit line being decoupled from said second local write bit line; and a local multiplexing block interconnected with said first and second local read bit lines and configured to ground said first and second local read bit lines upon assertion of a SLEEP signal and to selectively interconnect said local read bit lines to said global read bit line; and a global multiplexing block interconnected with said global read bit line and configured to maintain said global read bit line in a substantially discharged state upon assertion of said SLEEP signal and to interconnect said global read bit line to said global read bit line latch.