Patent ID: 8441041

Claim:
An integrated circuit memory device comprising: a substrate having a peripheral area and a core area; a first inter-level dielectric layer disposed on the substrate; a second inter-level dielectric layer disposed on the first inter-level dielectric layer; a peripheral contact that extend through the first inter-level dielectric layer in the peripheral area; a peripheral via that extends through the second inter-level dielectric layer to the peripheral contact in the peripheral area; a plurality of peripheral dummy vias that extend through the second inter-level dielectric layer and adjacent the peripheral via in the peripheral area; a metallization layer wherein at least a portion is coupled to the peripheral via; a plurality of source lines that extend through the first inter-level dielectric layer in the core area, wherein the peripheral contact is enlarged relative to the plurality of source lines; a plurality of source line vias that extend through the second inter-level dielectric layer to each respective one of the plurality of source lines in the core area; a plurality of bit line contacts that extend through the first inter-level dielectric layer to each respective one of a plurality of bit lines in the core area; a plurality of bit line vias that extend through the second inter-level dielectric layer to each one of the plurality of bit line contacts in the core area; and the metallization layer wherein at least a second portion is coupled to one or more of the plurality of source line vias and a third portion is coupled to one or more of the plurality of bit line vias.