Patent ID: 8159074

Claim:
A semiconductor chip comprising: a semiconductor substrate; a transistor in or on said semiconductor substrate; a first metal interconnect over said semiconductor substrate, wherein said first metal interconnect comprises electroplated copper; a second metal interconnect over said semiconductor substrate, wherein said second metal interconnect has a portion spaced apart from said first metal interconnect; a third metal interconnect over said semiconductor substrate, wherein said third metal interconnect has a portion spaced apart from said first metal interconnect and from said second metal interconnect; an insulating layer over said semiconductor substrate, wherein a first opening in said insulating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, wherein a second opening in said insulating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, and wherein a third opening in said insulating layer is over a third contact point of said third metal interconnect, and said third contact point is at a bottom of said third opening; a fourth metal interconnect on said first and second contact points and over said insulating layer, wherein said first contact point is connected to said second contact point through said fourth metal interconnect, wherein said fourth metal interconnect comprises a first metal layer and a second metal layer on said first metal layer, wherein said first metal layer is under said second metal layer, but not at a sidewall of said second metal layer; a metal bump connected to said third contact point through said third opening, wherein said metal bump comprises a tin-containing solder having a thickness between 10 and 300 micrometers; and a dielectric layer on a top surface of said fourth metal interconnect and over a top surface of said insulating layer, wherein no opening is in said dielectric layer on said top surface of said fourth metal interconnect, wherein said metal bump has a top higher than a top surface of said dielectric layer.