Patent ID: 7550352

Claim:
A method of fabricating a MOS transistor comprising: forming an isolation layer at a predetermined region of a semiconductor substrate to define an active region; etching a predetermined region of the active region to form an upper trench region that crosses the active region, the upper trench region dividing the active region into two sub-active regions; forming a low concentration impurity layer under a bottom surface of the upper trench region, the low concentration impurity layer having a different conductivity type from the semiconductor substrate; forming a spacer on sidewalls of the upper trench region that are adjacent to the sub-active regions; selectively etching the semiconductor substrate in the upper trench region using the spacer as an etching mask to form a lower trench region under the upper trench region; forming a gate insulating layer on sidewalls and a bottom surface of the lower trench region; forming a gate electrode that fills the lower trench region, surrounded by the gate insulating layer, and that fills the upper trench region, surrounded by the spacer; and forming a pair of high concentration source/drain regions at top surfaces of the sub-active regions that are located at both sides of the upper trench region respectively, wherein the low concentration impurity layer under the bottom surface of the upper trench region is formed prior to formation of the spacer.