Patent ID: 8743649

Claim:
A semiconductor memory comprising: memory cells disposed in a matrix; a first selection unit which selects any of first signal lines respectively connected to memory cell lines arranged in a first direction, in response to an access request to access the memory cells; a second selection unit which selects any of second signal lines respectively connected to the memory cell lines arranged in a second direction intersecting with the first direction, after the first selection unit starts operating; a first voltage generation unit which generates a first power supply voltage to be supplied to the first selection unit; a second voltage generation unit which generates a second power supply voltage to be supplied to the second selection unit, when a start-up signal is in an activating state; a switch which short-circuits a first power supply line supplied with the first power supply voltage and a second power supply line supplied with the second power supply voltage to each other, when a short-circuit signal is in the activating state; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal after completion of access operations based on the access request, and deactivates the start-up signal in response to deactivation of the short-circuit signal.