Patent ID: 8284887

Claim:
A clock data recovery circuit comprising: a first phase detector configured to detect a difference in phase between input data and a clock signal extracted from said input data and generate signals each representing an analog quantity corresponding to said difference in phase; a loop filter configured to indirectly integrate and smooth said signals output by said first phase detector; a charge pump configured to supply an electrical charging current to said loop filter in accordance with a specific one of said signals output by said first phase detector or draw an electrical discharging current from said loop filter in accordance with another one of said signals output by said first phase detector; a voltage-controlled oscillator configured to generate said extracted clock signal vibrating at a frequency determined by a voltage output by said loop filter; a second phase detector configured to detect the polarity of said difference in phase between said input data and said extracted clock signal; a phase correction information generation section configured to generate phase correction information to be used for eliminating a phase offset of said first phase detector in accordance with detection results produced by said second phase detector; and a phase correction information addition section configured to add said phase correction information generated by said phase correction information generation section to a feedback loop including said first phase detector, said loop filter, said charge pump and said voltage-controlled oscillator, wherein said phase correction information addition section increases or decreases said electrical charging current supplied from said charge pump to said loop filter and decreases or increases said electrical discharging current drawn from said loop filter to said charge pump.