Patent ID: 8817515

Claim:
A nonvolatile semiconductor memory device comprising: m×n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2; m word lines each connected to n memory cells in a corresponding one of the rows of the m×n memory cells; n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×n memory cells; a word line drive circuit configured to selectively activate the m word lines; a write driver configured to supply a rewrite voltage; a first selection circuit including n first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, and n second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and a second selection circuit including n third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines.