Patent ID: 7765504

Claim:
A computer-performed method of designing an electrical circuit interconnect structure, comprising: in a computer model of an interconnect structure design implemented by a computer system, determining that a blind via transitioning vertically from a signal layer located between a first metal reference plane and a second metal reference plane through the second metal reference plane is a via conducting a critical signal, and wherein the signal layer and the first and second metal reference planes are parallel to each other; checking other vias in a horizontal vicinity of the blind via for at least one other via that provides a return current path from the first metal reference plane to another metal reference plane, wherein the another metal reference plane is a metal reference plane other than the first and second metal reference planes, for transporting a return current conducted in the first metal reference plane to the another metal reference plane, wherein the return current is a return current for the critical signal; determining whether or not a distance between horizontal positions of the blind via and the at least one other via is greater than a specified threshold; responsive to determining that the distance between the horizontal positions of the blind via and the at least one other via is greater than the specified threshold, altering the computer model of the interconnect structure design to change the horizontal position of the blind via or the at least one other via to reduce the distance between the horizontal positions of the blind via and the at least one other via, whereby an area of an inductive loop formed between the blind via and a path of the return current is reduced; and storing an altered computer model resulting from the altering in a memory of the computer system.