Patent ID: 7024326

Claim:
Method of optimizing the timing between signals to be latched and a respective latching clock signal with respect to a given circuitry arrangement, (a) receiving and providing target timing data (TTD), which are descriptive for a target timing between said signals to be latched and said latching clock signal, (b) receiving and providing test timings (TT), which are descriptive for test timings of said latching clock signal, (c) receiving and providing a test input signal (I), as a test signal to be latched, (d) for each of said test timings (TT): setting and receiving a delay test value of a clock delay line (CDL), describing the delay which is received by a clock signal traveling along said clock delay line (CDL), inputting and thereby receiving a clock signal (C) through said clock delay line (CDL) and said test input signal (I) as a sample signal (S) through a sample signal line (SSL) simultaneously and in particular at respective input sections thereof (CDLi, SSLi), measuring a phase difference between said clock signal (C) and said sample signal (S) at respective end sections or output sections (CDLo, SSLo) of said clock delay line (CDL) and of said sample signal line (SSL), respectively, (e) comparing the obtained phase differences to said target timing data (TTD), and (f) choosing and setting a distinct delay test value as a delay value for said clock delay line (CDL) for operating for which the respective phase difference fits best to the target timing data (TTD); wherein a non-feedback phase detection/phase alignment circuit (PD) is employed.