Patent ID: 7050463

Claim:
A bit-rate detection circuit for detecting a bit rate of a stream of input bits of SONET data having a pair of sequential framing bytes of value F6h and 28h, provided at a first, maximum rate, a second rate of half the maximum rate, or a third rate at a rate of a quarter of the maximum rate, comprising: a plurality of shift registers adapted to serially shift in the input bits of SONET data having a data rate from a first transceiver, said shift registers being clocked at the first rate; and logic circuitry responsively coupled to said shift registers and configured to provide an output signal indicative of the data rate by detecting a first pattern of 1010 or 0101 in first selected bits in the framing bytes in the shift registers, detecting a second pattern of 101 or 010 in second selected bits in the framing bytes in the shift registers, detecting a third pattern of 1001 or 0110 in third selected bits in the framing bytes in the shift registers, and setting the value of the output signal to indicate the first, second or third rate in dependence upon which of the first, second and third patterns are detected.