Patent ID: 7176123

Claim:
A method for manufacturing metal lines of a semiconductor device, the method comprising the steps of: forming a first interlayer insulating film exposing a top portion of a lower metal line on a semiconductor substrate; forming a stacked structure of a first etch barrier film, a second interlayer insulating film, a second etch barrier film, a third interlayer insulating film, and an anti-reflection film; etching the stacked structure to form a via contact hole exposing a portion of the first etch barrier film on the lower metal line; removing the exposed portion of the first etch barrier film to expose the lower metal line; forming a photoresist film on the entire surface of the exposed lower metal line, the via contact hole, and the remaining anti-reflection film; subjecting the photoresist film to an exposure and development process using an upper metal line mask to form a photoresist film pattern for defining an upper metal line region, wherein the photoresist film pattern further fills a portion of the via contact hole to cover the exposed lower metal line; etching the anti-reflection film and the third interlayer insulating film using the photoresist film pattern as a mask to form the upper metal line region; removing the photoresist film pattern to expose the lower metal line; after the photoresist film pattern is removed, forming an upper metal line contacting the lower metal line by filling the upper metal line region.