Patent ID: 8547139

Claim:
A CMOS logic integrated circuit comprising: a level shifter configured to convert a signal of a first logic level to a signal of a second logic level, the signal of the first logic level changing between a first low potential and a first high potential higher than the first low potential, and the signal of the second logic level changing between the first low potential and a second high potential higher than the first high potential; and a CMOS logic circuit including: a first N-channel type MOSFET and a second N-channel type MOSFET connected in series with the first N-channel type MOSFET, a first signal of the first logic level being input into a gate of the first N-channel type MOSFET, a second signal of the second logic level having an inversion relationship with the first signal and being input into a gate of the second N-channel type MOSFET; and a pull-up transistor, a gate of the pull-up transistor being connected to the first N-channel type MOSFET and the second N-channel type MOSFET, and the signal of the second logic level being input into a source of the pull-up transistor.