Patent ID: 8305126

Claim:
A method comprising: operating a plurality of flop circuits of an integrated circuit (IC) in a first mode, each of the plurality of flop circuits having a master latch and a slave latch, wherein operating in the first mode includes, for each of the plurality of flop circuits, the master latch being transparent in accordance with a first clock signal and the slave latch being transparent in accordance with a second clock signal, and wherein the master latch and slave latch are not concurrently transparent; operating each of the plurality of flop circuits in a second mode, wherein in operating in the second mode includes, for each of the plurality of flop circuits, holding the master latch transparent and wherein the slave latch is transparent in accordance with the second clock signal; and determining, based on said operating in the first mode and the second mode, which of the plurality of flops is to operate as a master-slave flip-flop and which flops are to operate as pulse flops for a subsequent revision of the IC.