Patent ID: 6953729

Claim:
A method of manufacturing a heterojunction field effect transistor, the method comprising: epitaxially forming a composite substrate, having a plurality of semiconductor layers on a semi-insulative substrate, the semiconductor layers including a semiconductor layer that serves as an active layer and at least one other semiconductor layer, formed over the upper side or both over the upper side and under the lower side of said active layer, that serves as an N-type carrier supply layer for supplying an electron to said active layer; diffusing F atoms on the surface of the epitaxial substrate; forming a gate electrode on said composite substrate; and forming N-type source and drain areas, by carrying out: ion injection for forming N-type semiconductors in predetermined areas of said composite substrate, each of said source and drain areas formed to one side of said gate electrode, and an annealing process for activating the ion injected areas, wherein: said upper-side N-type carrier supply layer, between said source area and said drain area, is doped with Selenium (Se) or Tellurium (Te), or at least one of said upper- and lower-side N-type carrier supply layers, between said source area and said drain area, is doped with Selenium (Se) or Tellurium (Te).