Patent ID: 8415789

Claim:
A three-dimensionally integrated semiconductor device in which various circuit elements, including a semiconductor chip, are attached to opposite faces of a wiring substrate, the device being characterized in that the wiring substrate has, on each of first and second main faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions, and also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the first main face and the connection pad portions and the wiring traces on the second main face; the semiconductor chip is attached to the first main face of the wiring substrate and is connected to the connection pad portions on the first main face, a post electrode component including a plurality of post electrodes supported by a support portion is fixed to and electrically connected to the wiring traces on the first main face at predetermined positions, resin sealing is performed, and the support portion is separated so as to expose end surfaces of the post electrodes; and another circuit element is disposed on the second main face of the wiring substrate and is connected to the connection pad portions on the second main face.