Patent ID: 7031177

Claim:
A non-volatile content addressable memory, comprising: a multiplicity of memory cells ordered into a matrix of rows and columns; a word line associated with every row of cells; a first and a second bit line associated with every column of cells; an input terminal and an output terminal; a ground control line, a ground line and a match control line associated with every row of cells; a search activation terminal and a match indication terminal associated with every row of cells; each cell comprising: a first non-volatile memory element having a control terminal connected to the word line associated with the row containing the cell, a first terminal connected to the first bit line associated with the column containing the cell and a second terminal connected to a match node of the cell; a second non-volatile memory element having a control terminal connected to the word line associated with the row containing the cell, a first terminal connected to the second bit line associated with the column containing the cell and a second terminal connected to the match node of the cell; a first controlled electronic switch connected between the input terminal and the output terminal of the cell and having a control terminal connected to the match node of the cell, the controlled electronic switches of the cells of the same row being connected in series with each other between the search activation terminal and the match indication terminal associated with the row; a second controlled electronic switch connected between the ground line associated with the row containing the cell and the cell output terminal and having a control terminal connected to the match control line associated with the row containing the cell; and a third controlled electronic switch connected between the match node of the cell and the ground line associated with the row containing the cell and having a control terminal connected to the ground control line associated with the row containing the cell.