Patent ID: 7642594

Claim:
An electronic device comprising: a trench within a substrate, wherein the trench has a first wall; a first set of memory cells oriented substantially along a first direction; a second set of memory cells oriented substantially along the first direction; a first gate line electrically connected to the first set of memory cells, wherein the first gate line is a select gate line; a second gate line electrically connected to the second set of memory cells, wherein: when compared to the first gate line, the second gate line is electrically connected to more sets of memory cells that lie along the first direction; the second gate line is a control gate line; and within a memory array including the first and second sets of memory cells, a length of the first gate line is substantially parallel to a length of the second gate line; and discontinuous storage elements, wherein for each memory cell within the first set of memory cells, a first set of the discontinuous storage elements lies between the second gate line and the first wall of the trench, wherein the first set of storage elements include a first storage element and a second storage element, both of which lie along the first wall, and wherein all of the first storage element lies at an elevation higher than all of the second storage element.