Patent ID: 6985025

Claim:
Control circuitry for adjusting a power supply level of a digital processing component having varying operating frequencies, said control circuitry comprising: a plurality of delay cells coupled in series, each of said plurality of delay cells having a delay based on a value of the power supply level, such that a clock edge applied to an input of one of the delay cells ripples sequentially through said plurality of delay cells; and power supply adjustment circuitry capable of adjusting the power supply level, said power supply adjustment circuitry operable to (i) monitor outputs of at least a first delay cell and a second delay cell immediately following the first delay cell, (ii) determine that said clock edge has reached an output of said first delay cell and has not reached an output of said second delay cell in response to a next sequential clock edge being applied to the delay cell input, and (iii) generate a control signal capable of adjusting the power supply level based on the determination.