Patent ID: 8859390

Claim:
A method of forming a 3D IC comprising the steps of: providing a bonded structure comprising a first component bonded to a second component using a bonding layer, said first component having a first semiconductor substrate and a first layer with first metallization formed therein, said second component having a second semiconductor substrate that is substantially thinner than the first semiconductor substrate and a second layer with second metallization formed therein, and said bonding layer comprised of a first adhesion layer formed on the first layer and a second adhesion layer formed on the second layer, and said bonded structure having a periphery; forming a crack stop in the first layer; forming a passivation layer on said second semiconductor substrate; forming one or more holes through said passivation layer, said second semiconductor substrate, said second layer, and said bonding layer; and filling said one or more holes to form a circumferential wall, the circumferential wall contacting said crack stop and extending through said second semiconductor substrate, said second layer, and said bonding layer and adjacent to said periphery.