Patent ID: 8053326

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a first interlayer insulation layer and a second interlayer insulation layer; forming a first storage node contact plug that penetrates said first interlayer insulation layer and a second storage node contact plug that penetrates said second interlayer insulation layer; forming a separation insulation layer over the second interlayer insulation layer; performing a main etch process to form an open region by selectively etching the separation insulation layer, the open region exposing a top surface of the second storage node contact plug; performing an over-etch process to expand the open region by etching the second storage node contact plug and the second interlayer insulation layer, thereby a bottom portion of the expanded open region extending laterally beyond side surfaces of the second storage node contact plug after the performance of the over-etch process; forming a storage node in the expanded open region; and removing the separation insulation layer, wherein the first interlayer insulation layer and the separation insulation layer comprise an oxide layer and the second interlayer insulation layer comprises a nitride layer.