Patent ID: 7012851

Claim:
A nonvolatile ferroelectric memory device comprising: first and second cell array blocks which independently operate in a split word line structure, wherein each of the first to fourth cell array blocks has a hierarchical bit line structure having a plurality of local bit lines correspondent to each of columns and a global bit line which is selectively connected to one of the plurality of the local bit lines by a plurality of switching transistors; driving means for driving a split word line in the split word line structure, wherein the driving means includes: an output terminal connected to the split word line; decoding means for receiving a plurality of row address signals and activating the split word line; pull-down means for carrying out a pull-down operation at the output terminal when the split word line is nonactivated; pull-down control means for controlling the pull-down means in response to an output signal from the decoding means and an external control signal; pull-up means for supplying a pumping voltage to the output terminal; and pull-up control means for controlling the pull-up means by applying the output signal from the decoding means to the pull-up means in response to a word line control signal.