Patent ID: 8384199

Claim:
An electronic module comprising: a chip layer including; at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; and a structural encapsulant material surrounding and physically contacting the at least one side surface of each chip of the chip layer, the structural encapsulant material having an upper surface substantially co-planar with or parallel to the upper surface of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of the at least one chip and defining at least a portion of a back surface of the chip layer, and wherein the structural encapsulant material provides structural integrity to the electronic module and extends between the front surface and the back surface of the chip layer at an edge of the electronic module; a Faraday shield structure configured and positioned to suppress RF noise for a chip of the at least one chip of the chip layer when coupled to a ground, the Faraday shield structure being at least partially embedded within the chip layer, wherein the Faraday shield structure comprises at least one RF suppression structure fabricated of a conductive material, structurally configured to suppress RF noise and extend through the structural material between the front surface and the back surface of the chip layer, and wherein the at least one RF suppression structure of the Faraday shield structure comprises a picket fence type structure configured to suppress RF noise and wherein the picket fence type structure comprises a plurality of closely spaced conductive structures extending through the structural material between the front surface and the back surface of the chip layer in spaced opposing relation to the side surface of the chip to suppress RF noise.