Patent ID: 7898088

Claim:
A semiconductor wafer, comprising: a multiplicity of integrated circuit dice arranged therein, each die having an active surface and a back surface, each back surface being substantially opposite the active surface, the back surfaces of the dice cooperating to form the back surface of the wafer; a plurality of singulation streets that define the two-dimensional array of dice, the singulation streets separating associated peripheral side edges of adjacent dice from one another; a multiplicity of bond pads, the bond pads being arranged such that each die includes a plurality of bond pads on its active surface, the plurality of bond pads of each die including at least a set of signal bond pads configured for carrying electrical signals and a set of power bond pads configured for coupling to power or ground lines; and one or more metallic layers deposited substantially uniformly over portions of the active surface of each die and arranged to overlie at least two of the power bond pads from each die to form at least one extended I/O pad on the active surface of the die that is electrically connected with each of the associated at least two power bond pads, each extended I/O pad extending at least to and coming in direct contact with at least one peripheral side edge of the associated die, the extended I/O pad including a contact surface that overlies one of the power bond pads and extends to the at least one peripheral side edge of the associated die, wherein each of the extended I/O pads on the active surface of the die forms an external contact pad arranged to electrically connect with an external device positioned over the active surface of the die.