Patent ID: 6900909

Claim:
An image processors, comprising: image memory configured to store image data; an image memory control unit, which is connected to at least one connected unit, including at least one of an image reading unit for reading image data, an image processing unit for processing and editing image data, and an image writing unit for writing image data to transfer paper, and is configured (1) to receive at least one of first image data read-in by said image reading unit and second image data subjected to image processing by said image processing unit, (2) to transmit at least one of the first image data and the second image data to said image memory, and (3) to transmit the image data stored in said image memory to at least one of said image processing unit and said image writing unit; a system control unit configured to control transmission or reception of control signals used in each of said at least one connected unit or between said at least one connected unit; and a source detection unit configured to detect a source of image data received by said image memory control unit, wherein said system control unit is configured to control said image memory control unit according to the source of the image data detected by said source detection unit, and to determine a transmission order of the image data to said image memory; and said image memory control unit is configured to control access to the image memory so as to prevent a collision between jobs relating to accesses of the image memory, based on priorities of the jobs.