Patent ID: 7521285

Claim:
A method for fabricating chip-stacked semiconductor packages, comprising the steps of: preparing a chip carrier module plate including a plurality of chip carriers, and mounting a first chip on a predetermined position of each of the chip carriers, wherein the first chips are electrically connected to the chip carriers; providing a heat sink module plate including a plurality of heat sinks, the heat sinks corresponding in size to the chip carriers, wherein a plurality of through holes are formed around each of the heat sinks, and each of the heat sinks is correspondingly attached to each of the first chips; mounting a second chip on each of the heat sinks, wherein the second chips are electrically connected to the chip carriers via conductive wires penetrating the through holes of the heat sink module plate; performing a molding process to form an encapsulant for completely encapsulating the first chips, the second chips and the heat sink module plate on the chip carrier module plate; and performing a singulation process to cut along edges of the chip carriers and the heat sinks to form chip-stacked semiconductor packages integrated with the heat sinks.