Patent ID: 7082513

Claim:
An integrated memory, comprising: a memory cell array of memory cells for storing data; an access controller for controlling a memory access to said memory cell array for at least one of reading and writing data; an addressing unit for addressing selected ones of said memory cells corresponding to the memory access based on received addressing signals; and an addressing calculation logic unit connected to said addressing unit, to be activated by a test mode signal for a test operation of said memory cell array, receiving command signals and address signals for the test operation, calculating the addressing signals from the command signals and the address signals for the memory access, and feeding the addressing signals into said addressing unit, said addressing calculation logic unit including: a register unit for storing address parameters for calculating the addressing signals; a computation cascade connected downstream of said register unit and calculating the addressing signals; a writing-back logic unit connected downstream of said computation cascade and writing back present addressing signals to said register unit; and a control unit connected to said register unit and said computation cascade for controlling a calculation process and for feeding initialization values.