Patent ID: 7274234

Claim:
A digital storage element, comprising: a master transparent latch that receives functional data signals from data input ports and a scan data signal from a scan input port, the master transparent latch having a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of said functional data signals; and a slave transparent latch coupled to said master transparent latch, said slave transparent latch comprising dedicated functional data and scan data output ports; wherein, while operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping; wherein a first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch and, when activated, the first transistor resets the digital storage element when the first clock signal is in a first state and, when activated, the second transistor resets the digital storage element when the first clock signal is in a second state.