Patent ID: 7868320

Claim:
A semiconductor device comprising: a substrate; a transistor in a peripheral circuit, formed over the substrate; a first insulating layer formed over the transistor; a second insulating layer having a first opening and a second opening, the second insulating layer being over the first insulating layer; a capacitor in the first opening, the capacitor in the peripheral circuit comprising: a first conductive layer formed over the first insulating layer, electrically connected to the transistor, wherein an edge portion of the first conductive layer is covered with the second insulating layer; a second conductive layer formed over the first conductive layer and the second insulating layer; and a first organic compound layer formed between the first conductive layer and the second conductive layer and over the second insulating layer; a memory element in the second opening, the memory element in a memory cell array comprising: a third conductive layer formed over the first insulating layer, wherein an edge portion of the third conductive layer is covered with the second insulating layer; a fourth conductive layer formed over the third conductive layer and the second insulating layer; and a second organic compound layer formed between the third conductive layer and the fourth conductive layer and over the second insulating layer, wherein the memory element is electrically connected to the peripheral circuit, and wherein the first organic compound layer comprises a same material as the second organic compound layer.