Patent ID: 8524551

Claim:
A method of forming a heterojunction bipolar transistor, comprising: depositing a first stack including an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning the first stack to form a trench extending to the substrate, the trench having a sidewall; depositing a silicon layer over a resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewall of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a further boron-doped silicon layer over the resultant structure; forming a dielectric spacer on the sidewall of the trench; filling the trench with an emitter material; exposing polysilicon regions outside the side wall of the trench by selectively removing the sacrificial layer of the first stack; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities.