Patent ID: 6927790

Claim:
A digital camera system, comprising: a host controller; a digital image sensor for sensing a digital image defined by pixels of data; a memory coupled to said digital image sensor via a data bus; a microcontroller having an RS-232 serial input/output (I/O) port coupled to said host controller, said microcontroller further having control signal output ports and a data I/O port; a bi-directional tri-state buffer coupled to said data I/O port and said data bus for passing data therebetween; at least one of said control signal output ports coupled to each of said digital image sensor, said memory and said tri-state buffer; said microcontroller receiving control signals from said host controller and issuing said control signals over said control signal output ports to control access to said data bus wherein only one of a plurality of data transfer paths is established, said plurality of data transfer paths including a first data transfer path from said microcontroller through said tri-state buffer to said digital image sensor, a second data transfer path from said digital image sensor to said memory, and a third data transfer path from said memory through said buffer to said host controller via said RS-232 serial I/O port of said microcontroller, wherein said memory is disabled by said microcontroller when said one of said plurality of data transfer paths is said first data transfer path.