Patent ID: 8351237

Claim:
A ferroelectric random access memory comprising: a first buffer configured to receive a power-down notification and configured to output a first signal, wherein the first buffer is configured to change the first signal from a first value to a second value based on the notification; a second buffer configured to generate and supply an inner clock signal and configured to stop supplying the inner clock signal when the first signal changes from the first value to the second value; a third buffer configured to receive, hold, and output an address signal; a first controlling unit configured to receive and output a command signal; a second controlling unit configured to generate and output a basic signal, wherein the basic signal comprises a third value when the command signal output from the first controlling unit comprises a bank active command, and wherein the basic signal comprises a fourth value when the command signal comprises a precharge command and the first signal comprises the second value; a memory cell array comprising at least one memory cell, the memory cell comprising a ferroelectric capacitor and a cell transistor; a sense amplifier configured to read data, via a pair of bit lines, from the memory cell corresponding to the address signal; and a third controlling unit configured to write the data back to the memory cell corresponding to the address signal at a predetermined time after a time the basic signal changes to the third value and when the basic signal comprises the fourth value.