Patent ID: 7363465

Claim:
A semiconductor device, comprising: a bus master comprising a bus control circuit that receives an access address from a given module through a first bus and requests access based on the received access address to a semiconductor storage medium through a second bus; and a bus slave comprising a memory controller that controls access to the semiconductor storage medium based on an access request received through the second bus; wherein: the bus control circuit of the bus master comprises a first relative address control circuit that performs a process for requesting the access using a relative address to the semiconductor storage medium through the second bus, the process including generation of the relative address corresponding to an absolute address received through the first bus and generation of an identification signal indicating the relative address, the relative address being generated based on a difference between an absolute address corresponding to a previously accessed address and an absolute address of the received access address; and the memory controller of the bus slave comprises a second relative address control circuit that decides whether the received access address is a relative address or not and, if the received access address is a relative address, calculates an absolute address based on the relative address and the absolute address corresponding to the previously accessed address.