Patent ID: 7885297

Claim:
A synchronization device with a system time clock (STC) and generating an output data with a first sampling rate, comprising a memory; a demultiplexer receiving a bit stream and extracting a packetized elementary stream (PES) from the bit stream, wherein the demultiplexer writes the PES into the memory; a comparator obtaining a presentation time stamp (PTS) from the PES and comparing the PTS and the STC; and a sampling rate converter having a converting factor, sampling the PES in the memory according to the converting factor, and generating the output data according to the PES; wherein the sampling rate converter changes the converting factor according to the compared result of the comparator; and when a difference between the PTS and the STC exceeds a predetermined range, the comparator outputs an indication signal, and the sampling rate converter changes the converting factor according to the indication signal.