Patent ID: 7719874

Claim:
A non-volatile memory device, comprising: a plurality of first array lines; a plurality of second array lines substantially perpendicular to said plurality of first array lines; a plurality of non-volatile memory cells including a steering element in series with a state change element, each arranged between one of said first array lines and one of said second array lines, said plurality of memory cells including a subset of memory cells, each arranged between selected first array lines and selected second array lines and subjected to a bias during an operation to switch said subset of memory cells from a first resistance state to a second resistance state, said operation including at least one voltage pulse having an amplitude that changes to increase said bias for said subset of memory cells; and control circuitry in communication with said plurality of first array lines and said plurality of second array lines, said control circuitry switches a first non-volatile memory cell of said subset of memory cells from said first resistance state to said second resistance state by: applying a first voltage pulse to said first non-volatile memory cell at a first starting value and changing an amplitude of said first voltage pulse at a substantially constant slope to a first ending value, determining whether said first non-volatile memory cell has reached said second resistance state after applying said first voltage pulse, and applying a second voltage pulse to said first non-volatile memory cell at a second starting value and changing an amplitude of said second voltage pulse at a substantially constant slope to a second ending value if said first non-volatile memory cell has not reached said second resistance state after applying said first voltage pulse.