Patent ID: 8862825

Claim:
A processor supporting a coarse-grained array mode and a very long instruction word (VLIW) mode, comprising: a core of the processor; a scratch pad memory including a shared section in which a variable used in the coarse-grained array mode is stored; a cache memory to cache a variable used in the VLIW mode from a dynamic random access memory (DRAM) including a local/stack section in which the variable used in the VLIW mode is stored; and an address decoding unit to determine which section a memory access request received from the core is associated with, of the shared section and the local/stack section, based on a memory address corresponding to the memory access request received from the core, wherein the scratch pad memory and the cache memory are distinct hardware components within the processor, and wherein the scratch pad memory is not accessed in the VLIW mode.