Patent ID: 8537838

Claim:
A system for receiving one or more input signals and for producing one or more output signals, the system comprising: (a) a master controller for generating input processor control signals and output processor control signals, and for assigning a unique global identification code to each of a plurality of packet source signals; (b) an input processor having: (i) one or more input ports for receiving the input signals; (ii) one or more input signal processors for processing the input signals to provide one or more processed signals (iii) an input processor memory system for buffering the input signals and the processed signals, wherein at least some of the buffered signals are designated as packet source signals; (iv) one or more packetized signal output ports; (v) one or more packetized signal output stages for retrieving one or more of the packet source signals from the input processor memory system and for producing one or more packetized signals at the packetized signal output ports, wherein each of the packetized signals includes a series of packetized signal packets, wherein each of the packetized signal packets contains the unique global identification code corresponding to one of the packet source signals and data corresponding to the same packet source signal; and (vi) an input processor local controller for controlling the operation of at least the signal processors and the packetized signal output stages in response to the input processor control signals; (c) an output processor having: (i) one or more packetized signal input ports for receiving the packetized signals; (ii) one or more packetized signal input stages for extracting data corresponding to each of the packet source signals from each of the packetized signals and for storing data corresponding to each of the packet source signals in a separate buffer in the output processor memory system as an output source signal based on the unique global identification code in the packetized signal packets of each packetized signal; (iii) one or more output signal generators for providing one or more output signals, each of the output signals corresponding to one or more of the output source signals; (iv) an output processor local controller for controlling the operation of the packetized signal input stages and the output signal generators in response to the output processor control signals; and (d) a communications link coupled between the one or more packetized signal output ports and the one or more packetized signal input ports.