Patent ID: 7968976

Claim:
A semiconductor apparatus, comprising: an active die region; a guard ring having a plurality of stacked metal layers, the plurality of stacked metal layers including a top metal layer, the guard ring having an inner boundary closer to the active die region and an outer boundary further from the active die region; a first dielectric layer having a top boundary and a bottom boundary, at least some of the top metal layer being between the top and bottom boundaries of the first dielectric layer; a passivation layer over at least a portion of the top metal layer and at least a portion of the first dielectric layer; and a metal capping layer over the top metal layer, the metal capping layer comprising: a first portion proximate to the outer boundary of the guard ring and in direct contact with the first dielectric layer, a second portion proximate to the outer boundary and in direct contact with the top metal layer, and a third portion proximate to the inner boundary of the guard ring and separated from the top metal layer by the passivation layer.