Patent ID: 8347042

Claim:
A flash memory device comprising: a control logic circuit to generate cache input control signals and cache output control signals, the control logic circuit receiving a chip enable signal having a plurality of bit signals, wherein: the cache input control signals correspond to the bit signals, each cache input control signal is generated when corresponding bit signals are at a low level, the control logic circuit receives addresses when an address latch enable signal is enabled, the latch enable signal being enabled when the bit signals are at a low level, the cache input control signals are generated in sequence during a program operation and are simultaneously generated during a read operation, and the cache output control signals are simultaneously generated in the program operation and are generated in sequence in the read operation; a plurality of planes each including a plurality of memory cell blocks, wherein: the number of planes corresponds to the number of bit signals of the chip enable signal, and in the program operation, data is simultaneously programmed in each of the plurality of planes; a plurality of page buffers, each page buffer connected to a corresponding one of the planes, each page buffer simultaneously latching an input data bit to be output to its corresponding plane and simultaneously latching an output data bit received from the corresponding plane; and a plurality of cache buffers, each cache buffer connected to a corresponding one of the page buffers and the corresponding plane, wherein: in the read operation, the data programmed in the plurality of planes is simultaneously output to the plurality of cache buffers based on the cache output control signals, the cache buffers store in sequence the input data bits in response to the cache input control signals in the program operation and simultaneously store the latched output data bits in response to the cache input control signals in the read operation, and the cache buffers simultaneously transfer the stored data bits to the corresponding page buffers in response to the cache output control signals in the program operation and transfer the stored data bits in sequence to an external device in response to the cache output control signals in the read operation.