Patent ID: 7539789

Claim:
A memory circuit, comprising: a write interface; wherein the write interface is N-bits wide, and N is greater than 1; a read interface; a deserializer circuit having an input port and a plurality of output ports, wherein the input port of the deserializer circuit is coupled to the write interface; wherein the deserializer circuit further includes a plurality of write enable output terminals; a plurality of first-in first-out memories (FIFOs), each FIFO having a write enable input terminal coupled to an associated one of the write enable output terminals of the deserializer circuit, each FIFO further having an N-bit wide data output port coupled to the read interface; wherein each FIFO has a data-in port at least N-bits wide, and the data-in ports of the FIFOs are coupled to the N-bit wide write interface such that N bits of data at the N-bit wide write interface are presented at once in parallel to the data-in ports of all of the FIFOs; wherein the deserializer is configured to provide respective write enable signals on the output ports to the write enable input ports of the plurality of FIFOs, and for each successive set of N bits on the write interface, the deserializer enables writing of the set of N bits to a different one of the plurality of FIFOs; and wherein each FIFO provides a respective full status signal in response to the FIFO being full and a respective empty status signal in response to the FIFO being empty.