Patent ID: 7821483

Claim:
An interface circuit whereby data is transmitted through first data signals during a first data period, a second data period, and a third data period respectively corresponding to a first rising, a first falling edge, and a second rising edge of a clock signal, wherein the first data period, the second data period, and the third data period are continuous, the second data period follows the first period, and the third data period follows the second data period, the interface circuit comprising: a transition detection unit for selectively asserting a first detection signal, of which a constant level of the first detection signal lasts longer than a ½ cycle of the clock signal, in response to the number of the first data signals having transitions between the first data period and the second data period, and selectively asserting a second detection signal, of which a constant level of the first detection signal lasts longer than a ½ cycle of the clock signal, in response to the number of the first data signals having transitions between the second data period and the third data period; and a transition reduction unit for generating second data signals by outputting the inverted and non-inverted first data signals respectively when the first detection signal or the second detection signal is asserted and de-asserted.