Patent ID: 8559232

Claim:
A DRAM-like non-volatile memory (NVM) array, comprising: a matrix of a plurality of NVM cell units arranged in a plurality of rows and columns, each of said NVM cell unit including a first NVM cell device and a second NVM cell device as a pair with each NVM cell device having a drain node and a source node; a plurality of word lines, each word line associated with a row of said NVM cell units; a plurality of bit line pairs, each bit line pair associated with a column of said NVM cell units, and each bit line pair having a first bit line connected to the drain nodes of the first NVM cell devices in the associated column, and a second bit line connected to the drain nodes of the second NVM cell devices in the associated column, said bit line pairs being laid out perpendicular to said word lines; a plurality of source line pairs, each source line pair associated with a column of said NVM cell units, and each source line pair having a first source line connected to the source nodes of the first NVM cell devices in the associated column, and a second source line connected to the source nodes of the second NVM cell devices in the associated column, said source line pairs being laid out perpendicular to said word lines; a plurality of column decoders, each column decoder associated with a column of said NVM cell units; and a plurality of cross-coupled latch-type sense amplifiers, each latch-type sense amplifier associated with a column of said NVM cell units, each latch-type sense amplifier having symmetric first and second inputs coupled to the first and second bit lines in the associated column through the associated column decoder; wherein in each NMV cell unit, the first NVM cell device and the second NVM cell device each have a floating-gate storage cell, and the two floating-gate storage cells are programmed with respective erased and programmed threshold voltages as a pair to store only one bit of binary data.