Patent ID: 8379434

Claim:
An integrated circuit, comprising: an array of SRAM cells configured in rows and columns, each said SRAM cell including: a bit driver, said bit driver including a drain node, a source node, and a gate node; a bit-side node connected to said drain node of said bit driver; a bit load, said bit load including a drain node connected to said bit-side node, a source node, and a gate node; a bit-bar driver, said bit-bar driver including a drain node, a source node, and a gate node connected to said bit-side node; a bit-bar side node connected to said drain node of said bit-bar driver, to said gate node of said bit driver and to said gate node of said bit load, said bit-bar side node being free of a connection to a passgate transistor; a bit-bar load, said bit-bar load including a drain node connected to said bit-bar side node, a source node, and a gate node connected to said bit-side node; a bit-side passgate, said bit-side passgate including a first source/drain node connected to said bit-side node, a second source/drain node connected to a bit line, and a gate node connected to a word line; and a bit-bar-side auxiliary driver transistor, said bit-bar-side auxiliary driver transistor including a drain node directly connected to said bit-bar side node, a source node, and a gate node connected to said bit-side node; and node, a source node, and a gate node connected to said bit-side node; and an auxiliary driver transistor bias circuit coupled to said source node of said bit-bar-side auxiliary driver transistor in said each said SRAM cell, such that said auxiliary driver transistor bias circuit is capable of biasing said source nodes of said bit-bar-side auxiliary driver transistors in said array of SRAM cells.