Patent ID: 8069560

Claim:
A manufacture method of a multilayer wiring board comprising a core board, a wiring layer, and an electrically insulating layer that are stacked on said core board, said manufacture method comprising: forming a plurality of through holes in a core member, wherein a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, and said core member is selected from silicon, ceramics, glass, a glass-epoxy composite, and metal; causing said through holes to be conductive by a conductive material thereby to electrically connect between the front and the back of the core board; stacking a wiring layer and an electrically insulating layer on one surface of said core board to form a multilayer wiring layer; and forming a capacitor on the other surface of said core board, wherein the forming the capacitor comprises: forming a dielectric layer of the capacitor on the surface of the core board; forming an opening in the dielectric layer on the predetermined through hole to provide a wiring layer; using, as an upper electrode of the capacitor, the conductive material in the through hole where the dielectric layer has no opening; and providing a lower electrode of the capacitor via said dielectric layer on said through hole, thereby to form the capacitor.