Patent ID: 8325535

Claim:
A nonvolatile semiconductor storage device comprising: a memory cell array including a first line, a second line intersecting the first line, and a memory cell provided at the intersection of the first line and the second line; and a write/erase unit configured to write and erase data in and from the memory cell selected by the first line and the second line, the memory cell including a memory element and a rectifying element connected in series, a physical state of the memory element being changed by electric energy, during data write or erase, the write/erase unit supplying a first electric pulse to the selected memory cell, the first electric pulse having an electric energy to an extent that the physical state of the memory element of the selected memory cell does not transition, and accumulating charges in the rectifying element of the selected memory cell, and after supplying the first electric pulse, and a certain pulse interval thereafter, the write/erase unit supplying a second electric pulse to the selected memory cell, the second electric pulse having larger electric energy than the first electric pulse, the second electric pulse causing the physical state of the memory element of the selected memory cell to transition.