Patent ID: 7795936

Claim:
A data center tracking circuit comprising: a clock tree having a plurality of clock buffers connected in series, the clock tree configured to buffer a clock signal, and output an output signal; a sensing block configured to sense the phase change of the output signal on the basis of the clock signal, and output a sensing signal; and a delay compensation block configured to adjust a current supplied to the clock tree in response to the sensing signal, and to thereby adjust the phase of the output signal, wherein the delay compensation block includes: a filter unit configured to determine a corresponding logic value based on the voltage level of the sensing signal input over a certain period of time, and output a sum signal based thereon; a fine state machine configured to output a digital code in response to the sum signal, wherein the digital code is obtained by adding or subtracting the sum signal to or from a default value of the digital code; a digital-to-analogue converter configured to convert the digital code into an analogue signal; and a regulator unit configured to adjust the amount of current input to the clock tree in response to the analogue signal; wherein the delay compensation block further comprises a register unit configured to store the digital code, and transmit the stored digital code to the digital-to-analogue converter when relocking is required.