Patent ID: 7915655

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; and at least one metal-oxide semiconductor transistor constructed on the semiconductor substrate, each of the at least one metal-oxide semiconductor transistor including: source and drain electrodes of a second conductivity type disposed beneath a surface of the semiconductor substrate and spaced apart from each other; a channel region defined between the source and drain electrodes beneath the surface of the semiconductor substrate; a first dielectric layer disposed on the semiconductor substrate and overlapping the source and drain electrodes and the channel region therebetween; and a gate electrode disposed on the first dielectric layer and connected to a gate wire to receive a gate voltage, the drain electrode including: a first drain region located away from the channel region and from the first dielectric layer; and a second drain region located between the first drain region and the channel region, having a planar surface extending between an edge of the first drain region and an edge of the first dielectric layer, the source electrode including: a first source region located away from the channel region and away from the first dielectric layer and; a second source region located between the first source region and the channel region, having a planar surface extending between an edge of the first source region and an edge of the first dielectric layer, the second source region surrounding the first source region below a surface of the semiconductor substrate, the gate electrode including: a first gate layer located on the first dielectric layer and being laterally spaced from the first drain region and the first source region and having edges resting over the second drain region and the second source region, the first gate layer being electrically isolated from the gate wire; a second gate layer located over the first gate layer, the second gate layer being electrically connected to the gate wire; and a second dielectric layer located between, and electrically isolating, the first gate layer and the second gate layer, wherein both (a) a surface area of a surface of the second gate layer and (b) a surface area of a surface of the second dielectric layer are less than a surface area of a surface of the first gate layer.