Patent ID: 8269280

Claim:
An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) pin against positive and negative ESD events, the ESD protection circuit comprising: a first P-type well formed on a P-conductivity type substrate; at least one MOS transistor comprising at least one NMOS finger formed on a surface of the substrate within the first P-type well, the at least one NMOS finger including a source connected with VSS, a drain connected with the IC pin, and a gate coupled with VSS; a second P-type well formed on the substrate, the second P-type well surrounding the first P-type well and being concentric therewith, the second P-type well being connected directly with VSS, the first P-type well being connected to the second P-type well through the substrate; an N-type well formed on the substrate, the N-type well disposed between the first and second P-type wells and being concentric with the first and second P-type wells, the N-type well being connected with the drain of the at least one NMOS finger; wherein the second P-type well and the N-type well, together, form a P/N junction diode operative to provide an ESD current path during the negative ESD event.