Patent ID: 7428616

Claim:
An information processing apparatus comprising: a memory circuit configured to allow a CPU to access the same memory areas of a memory using a plurality of different address sets; cache means for performing cache control with one address set of the plurality of different address sets serving as a cacheable address set and another address set of the plurality of different address sets serving as an uncacheable memory address set; allocating means for, in a case where an acquisition of a first area of a prescribed size in the memory is requested by a client, respectively appending second areas to both ends of the first area, wherein each second area is a size of at least a line size saving as a cache unit, wherein the second areas are unused and specifically are not provided to the client and are not used by another client, and wherein the presence of the second areas at both respective ends of the first area prevents data in the first area from being destroyed by an access of the other client and DMA transfer of the data in the first area, and said allocating means further for allocating the first area and the second areas in the memory that is accessible byte uncacheable memory address set; and a DMA controller configured to perform the DMA transfer of the data in the first area of the memory.