Patent ID: 7883938

Claim:
A method of manufacturing a plurality of stacked die semiconductor packages, comprising: attaching a bottom surface of a second silicon wafer to a top surface of a first silicon wafer, said second silicon wafer having a plurality of unfilled vias and a layer of bonding material at the bottom surface; attaching a bottom surface of a third silicon wafer to a top surface of the second silicon wafer, said third silicon wafer having a plurality of unfilled vias and a layer of bonding material at the bottom surface, and said unfilled vias of the second and third silicon wafers are aligned with one another; removing said bonding material from said aligned unfilled vias; filling said aligned unfilled vias with a conductor; forming conductive bumps at ends of said aligned vias; back grinding a bottom surface of said first silicon wafer; separating said stacked semiconductor dies from each other; attaching the bump end of said separated stacked semiconductor dies onto a substrate; encapsulating said separated stacked semiconductor dies and substrate; and singulating said encapsulated assembly into individual stacked die semiconductor packages.