Patent ID: 7183155

Claim:
A method of fabricating a non-volatile memory device, comprising the steps of: forming at least two trench isolation layers having a first depth each in a device isolation area of a semiconductor substrate, wherein the trench isolation layers comprise sidewalls having vertical profiles; forming a first conductive type well having a second depth smaller than the first depth in an active area of the semiconductor substrate defined by the at least two trench isolation layers, wherein a width of a lower part of the first conductive the well is equal to that of an upper part of the first conductive type well; forming an ONO layer on a prescribed upper area of the first conductive type well wherein the ONO layer comprises a lower oxide layer, a nitride layer, and an upper oxide layer; forming a wordline conductor layer on the ONO layer; and forming source and drain regions in the prescribed upper area of the first conductive type well.