Patent ID: 7253518

Claim:
A wirebond electronic package comprising: an organic laminate substrate having an external surface; an electrically conductive circuit layer positioned on said external surface of said organic laminate substrate and including a plurality of wirebond pads; a semiconductor chip positioned on said external surface of said organic laminate substrate and electrically coupled to said wirebond pads of said electrically conductive circuit layer; and a pattern of thermally conductive material positioned on said external surface of said organic laminate relative to said wirebond pads of said electrical circuit, said pattern of thermally conductive material including a plurality of substantially concentric spaced-apart lines, said semiconductor chip positioned on said external surface of said organic laminate substrate being bonded to said external surface of said organic laminate substrate and said plurality of substantially concentric spaced-apart lines of said pattern of thermally conductive material so as to be thermally coupled to said plurality of substantially concentric spaced-apart lines of said pattern of thermally conductive material.