Patent ID: 8854903

Claim:
A data alignment circuit comprising: a first buffer section configured to invert and buffer a first pulse in response to a control signal; a second buffer section configured to invert and buffer ground voltage in response to the control signal; a first inverter configured to invert and buffer output signals of the first and second buffer sections and transmit the inverted and buffered signals as a first control pulse; a third buffer section configured to invert and buffer a second pulse in response to the control signal; a fourth buffer section configured to invert and buffer the ground voltage in response to the control signal; a second inverter configured to invert and buffer output signals of the third and fourth buffer sections and transmit the inverted and buffered signals as a second control pulse; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.