Patent ID: 7917797

Claim:
A circuit for generating an output clock signal from an input signal, the input signal having a plurality of transitions derived from a plurality of transitions of an original clock signal, the original clock signal having a first frequency that differs from a second frequency of the output clock signal, wherein the second frequency is a product of the first frequency and a ratio of a first integer value over a second integer value, the circuit comprising: an accumulator for periodically adding an offset value to a phase value of the output clock signal, the phase value having an integer part and a fractional part, wherein the periodically adding includes adding the offset value to the fractional part with a carryout, and adding the carryout to the integer part modulo the first integer value; a fractional phase detector coupled to the accumulator for generating, for each of the plurality of transitions of the input signal, a respective phase error that is a product of the phase value at the transition and a ratio of the second integer value over the first integer value; a loop filter coupled to the accumulator and the fractional phase detector, the loop filter for generating the offset value from a filtering of the respective phase errors; and a generator coupled to the accumulator for generating the output clock signal from the phase value.