Patent ID: 8384423

Claim:
A memory controller, comprising: a transmit circuit coupled to an output node, wherein the transmit circuit is to transmit first data to a memory device through the output node; a receive circuit coupled to a first input node, wherein the receive circuit is to receive second data from the memory device through the first input node; a calibration circuit; control logic coupled to the calibration circuit, wherein the calibration circuit and the control logic are to select a first reference voltage and a driver impedance for the transmit circuit and are to select a second reference voltage and a termination impedance for the receive circuit, wherein the first reference voltage, the second reference voltage, the driver impedance and the termination impedance are selected from a set of pre-determined values, and wherein the set of pre-determined values are associated with different signaling modes for communication of the first data and the second data; and a comparator and a switching mechanism in the calibration circuit, wherein the comparator is coupled to a third reference voltage and selectively coupled to pre-determined voltages by the switching mechanism, and wherein, based on an output from the comparator, the control logic configures the switching mechanism to select the first reference voltage and the second reference voltage from the pre-determined voltages.