Patent ID: 7927968

Claim:
A method of forming a dual stress shallow trench isolation (STI) region, comprising: depositing an oxide layer and a nitride layer on a substrate, wherein said substrate comprises a semiconductor layer on an insulator layer, said semiconductor layer being patterned to form a first transistor region and a second transistor region, separated from said first transistor region on said insulator layer; etching said oxide layer and said nitride layer to said insulator layer, to form a shallow trench isolation (STI) region between said first transistor region and said second transistor region, such that a bottom surface of said shallow trench region comprises said insulator layer; depositing and patterning a first compressive layer, such that said first compressive layer is formed only above said first transistor region and on a first portion of said insulator layer located between said first transistor region and said second transistor region and adjacent to said first transistor region; depositing and patterning a first tensile layer, such that said first tensile layer is formed only above said second transistor region and on a second portion of said insulator layer located between said first transistor region and said second transistor region and adjacent to said second transistor region, wherein a sidewall of said first tensile layer abuts a sidewall of said first compressive layer; depositing a second tensile layer on said first compressive layer and said first tensile layer; and polishing said second tensile layer, said first compressive layer, and said first tensile layer, such that said shallow trench isolation (STI) region between said first transistor region and said second transistor region comprises dual stress regions of a compressive region adjacent to said first transistor region and a tensile region adjacent to said second transistor region, wherein a portion of said tensile region overlies a portion of said compressive region.