Patent ID: 7701425

Claim:
A display driver that drives a plurality of data lines of a display panel including a plurality of scan lines, the plurality of data lines and a plurality of pixels, based on display data, the display driver comprising: a display data bus to which display data is supplied in accordance with the sequence in which the data lines are arranged; a shift register that has a plurality of flip-flops connected in series, shifts a shift start signal based on a shift clock, and outputs shift outputs from the flip-flops; a shift register control circuit that supplies the shift clock and the shift start signal to the shift register; a data latch that has a plurality of flip-flops and fetches display data on the display data bus, based on the shift outputs from the flip-flops of the shift register; and a drive circuit that drives the data lines, based on the display data that has been fetched into the data latch, the shift register control circuit supplying the shift clock to the shift register in a vertical scan period in which the scan lines are scanned, to cause the shift register to fetch display data for one horizontal scan, then halting the supply of the shift clock to the register; and the shift register control circuit supplying the shift clock to the shift register in a vertical blanking period between the vertical scan period and next vertical scan period, to clear contents held in the shift register; the display driver further comprising a mode setting register that sets a first mode or a second mode; when the first mode has been set in the mode setting register, the shift register control circuit supplying the shift clock to the shift register to cause the shift register to fetch display data for one horizontal scan in each of a plurality of horizontal scan periods included in the vertical scan period, then halting the supply of the shift clock to the shift register in the each of the plurality of horizontal scan periods included in the vertical scan period, and the shift register control circuit supplying the shift clock to the shift register or initializing the flip-flops of the shift register to clear the contents held in the shift register in the vertical blanking period; and when the second mode has been set in the mode setting register, the shift register control circuit supplying the shift clock to the shift register to cause the shift register to fetch display data for one horizontal scan, then supplying the shift clock to the shift register to clear contents held in the shift register.