Patent ID: 7750912

Claim:
A system comprising: a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, wherein the processor unit comprises at least one processor core, a display controller configured to couple to a display, and a bridge coupled to the processor core, the display controller, and the memory interface, wherein memory requests from the display controller are routed to the memory through the bridge, and wherein memory requests from the processor core are routed to the memory through the bridge; a second interface coupled to the bridge in the processor unit; and a graphics processing unit configured to render data into a frame buffer stored in the memory, the frame buffer representing an image to be displayed on the display, wherein a first path from the graphics processing unit to the memory includes the second interface, and wherein memory requests from the graphics processing unit are routed on the second interface to the bridge and from the bridge to memory; wherein the processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and wherein the display controller is configured to read the frame buffer data for display even if the second interface is deactivated, and wherein a second path from the display controller to the memory excludes the second interface, and wherein a third path from the processor core to the memory excludes the second interface.