Patent ID: 8713506

Claim:
A dynamic power recovery system, comprising: a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, said initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of said at least one path based on said first conditional downsizings, wherein said lower dynamic power cells have an internal capacitance that is less than an internal capacitance of said cells first conditionally downsized; and a speed recovery module associated with said power recovery module and configured to carry out a speed recovery process in each of said multiple scenarios concurrently, said speed recovery process including determining whether said first conditional downsizings cause a timing violation with respect to said at least one path and making second conditional upsizings with higher dynamic power cells until said timing violation is removed.