Patent ID: 7541248

Claim:
A method of manufacturing an integrated semiconductor device having a plurality of semiconductor elements formed in a well region of a semiconductor layer and each having a source of a first-conductivity-type semiconductor, a drain of the first-conductivity-type semiconductor and a body region of a second-conductivity-type semiconductor between said source and said drain, and a lower impurity concentration layer of the first-conductivity-type in an upper region of said well region, comprising the steps of: implanting impurities concurrently into a first lower impurity concentration layer of one semiconductor element and into a second lower impurity concentration layer of another semiconductor element, an implantation mask being used that includes a portion corresponding to said first lower impurity concentration layer of said one semiconductor element and having a first opening ratio as well as a portion corresponding to said second lower impurity concentration layer of said another semiconductor element and having a second opening ratio different from said first opening ratio, wherein said drain is higher impurity concentration than said lower impurity concentration, said one semiconductor element has a breakdown voltage higher than that of said another semiconductor element, said implantation mask being used has said first opening ratio smaller than said second opening ratio, and said one semiconductor element is adjacent to said another semiconductor element; and providing, in said semiconductor layer, a wall-shaped element-isolation insulating film for isolating said one semiconductor element from said another semiconductor element, prior to said step of implanting impurities; and annealing said integrated semiconductor device after said step of implanting impurities to diffuse said impurities.