Patent ID: 7888605

Claim:
An IC chip device comprising: a semiconductor device; an electrode pad provided on the semiconductor device; a passivation layer formed on the semiconductor device and on a first portion of a surface of said electrode pad; and an intermediate layer formed directly on the electrode pad and on the passivation layer, the surface of the intermediate layer being larger than the surface of the electrode pad, and the intermediate layer comprising: a first metal layer formed directly on a second portion of the surface of said electrode pad where said passivation layer is not formed, a second metal layer formed directly on the first metal layer, and a third metal layer formed directly on the second metal layer, wherein, when the semiconductor device is accommodated in a printed circuit board, the intermediate layer establishes electrical connection between the electrode pad and a conductive circuit formed on a first interlayer insulating layer of the printed circuit board through a first via hole structure formed in the first interlayer insulating layer, the first via hole structure being electrically connected to a second via hole structure formed by a second interlayer insulating layer formed over the first interlayer insulating layer and the first via hole structure and having a second via hole opening therein and a second via hole structure formed in the second via hole opening.