Patent ID: 7544582

Claim:
A method for fabricating a semiconductor device comprising: defining active regions and field regions in a semiconductor substrate; forming an insulating pattern on the active regions of the semiconductor substrate; forming spacers at both sides of the insulating pattern; forming a first field channel stop ion implantation layer at a first predetermined depth in the semiconductor substrate using the insulating pattern and the spacers as a mask; forming a second field channel stop ion implantation layer at a second predetermined depth in the semiconductor substrate using the insulating pattern and the spacers as a mask; removing the spacers; etching the semiconductor substrate to form a trench and expose the first and second field channel stop ion implantation layers using the insulating pattern as a mask; forming an STI layer by gap-filling the trench with an STI insulator and planarizing the STI insulator; and forming p-type and n-type wells by respectively implanting impurity ions into different active regions of the substrate.