Patent ID: 8370712

Claim:
A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage, said method comprising: monitoring an occurrence of an error during a read operation in a memory unit of said device, wherein (i) said memory unit is subdivided into dice, and each said die comprises at least one block, (ii) said error is correctable by error-correcting code, and (iii) said monitoring is carried out for said at least one block; programming said memory unit according to said monitored occurrence of said error, wherein said programming comprises wear-leveling said monitored block according to said error monitored for said monitored block; and if said at least one block is writable, setting apart said writable block of said memory unit, and wherein wear-leveling is implemented for a block that is distinct from said writable block that has been set apart.