Patent ID: 7089444

Claim:
A clock and data recovery circuit that recovers digital data and an embedded clock from an incoming serial data stream, the clock and data recovery circuit comprising: a reference clock input; a recovered clock output; a first phase-locked loop that receives a reference clock from the reference clock input, that locks onto the reference clock when the clock and data recovery circuit is operated in a reference mode, and that provides a corresponding reference clock signal directly to the recovered clock output when the clock and data recovery circuit is operated in the reference mode; a serial data stream input that receives the serial data stream; a second phase-locked loop that receives the serial data stream from the serial data stream input, that locks onto the incoming serial data stream when the clock and data recovery circuit is operated in a data mode, and that provides a corresponding recovered clock signal directly to the recovered clock output when the clock and data recovery circuit is operated in the data mode; and a control circuit that automatically switches the clock and data recovery circuit between the reference mode and the data mode.