Patent ID: 7411452

Claim:
A buffer amplifier, comprising: a DC bias stage; two complementary differential amplifiers; a second stage amplifier coupled to the pair of complementary differential amplifiers and the DC bias stage; and an output stage coupled to the second stage amplifier; wherein the second stage amplifier comprises a first set of bias transistors, M 11 and M 12 ; a second set of bias transistors, M 13 and M 14 ; the two sets of bias transistors forming a bi-circuit: wherein the M 11 and M 12 bias transistors are coupled to a transistor M 15 , which is coupled to a transistor M 17 ; wherein the M 13 and M 14 bias transistors are coupled to transistor M 16 , which is coupled to a transistor M 18 ; wherein in a stable state, the bias transistors are biased from the bias circuit and the current from the differential amplifiers do not flow into the bias transistors, the M 16 M 17 transistors are in the triode region and output transistors of the output stage consume no power.