Patent ID: 7681628

Claim:
A method for controlling back gate bias in a static random access memory (SRAM) cell, comprising: providing a back gate bias voltage to a back gate of at least one transistor in the SRAM cell; and dynamically controlling the back gate bias voltage based on an operational mode of the SRAM cell by: applying a first back gate bias voltage during a Read operational mode and a Half-Select operational mode of the SRAM cell, wherein in the Read mode, bit lines are precharged to a high level and a write line is at a high level, and wherein in the Half-Select mode the bit lines are charged to a high level and the write line is at a high level; and applying a second back gate bias voltage, different from the first back gate bias voltage, during a Write operational mode and a Standby mode of the SRAM cell, wherein in the Write mode, the bit lines are at a low level and the write line is at a high level, and wherein in the Standby mode, the write line is at a low level.