Patent ID: 7746101

Claim:
A logic block, comprising: a logic circuit having first and second self-timed inputs and a self-timed output; and an input circuit, wherein the input circuit comprises: a first multiplexing circuit having a plurality of self-timed inputs coupled to a plurality of self-timed inputs of the logic block, and further having a self-timed output coupled to the first input of the logic circuit; and a second multiplexing circuit having a self-timed first input coupled to a self-timed cascade input of the logic block, a self-timed second input coupled to a self-timed data input of the logic block, and a self-timed output coupled to the second input of the logic circuit, wherein the output of the second multiplexing circuit is further coupled to a cascade output of the logic block, and wherein the cascade output of the logic block is coupled to a cascade input of an adjacent logic block.