Patent ID: 8557650

Claim:
A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising: forming an isolation region in the non-NVM region; forming a dummy dielectric in an area of the non-NVM region surrounded by the isolation region and forming a gate dielectric in the NVM region; after forming the dummy dielectric and the gate dielectric, forming a first conductive layer over the substrate in the NVM region and the non-NVM region; patterning the first conductive layer in the non-NVM region; after patterning the first conductive layer, forming an NVM dielectric layer over the NVM region and the non-NVM region; forming a second conductive layer over the NVM dielectric layer; forming a patterned masking layer over the second conductive layer in the NVM region and in the non-NVM region, wherein: the patterned masking layer defines at least one NVM gate stack in the NVM region and at least one dummy feature in the non-NVM region, wherein the dummy feature is over the isolation, and performing an etch comprising: simultaneously etching the second conductive layer in the NVM region and in the non-NVM region using the patterned masking layer; simultaneously etching the NVM dielectric layer in the NVM region and in the non-NVM region using the patterned masking layer; and simultaneously etching the first conductive layer in the NVM region and in the non-NVM region using the patterned masking layer, using the dummy dielectric in endpoint detection of the etch.