Patent ID: 6888886

Claim:
An interface apparatus for receiving digital data serially transmitted in a predetermined format where predetermined identification data are incorporated in serial digital data in predetermined cycles, said interface apparatus comprising: a pulse train generation circuit that generates a bit-data extracting pulse train, having predetermined pulse generation patterns, in response to detection of a variation in received serial digital data; a bit-location information generation circuit that, on the basis of the bit-data extracting pulse train generated by said pulse train generation circuit, generates bit location information specifying each bit location in the received serial digital data; a bit-data extraction circuit that extracts data of each bit from the received serial digital data by use of the generated bit-data extracting pulse train; an identification data detection circuit that detects the identification data from the data extracted by said bit-data extraction circuit; a control device that is adapted to set a locked state at least on condition that the bit location information generated by said bit-location information generation circuit when the identification data is detected by said identification data detection circuit corresponds to a predetermined bit location, and generate a lock status signal in correspondence with setting of the locked state; and a data reproduction circuit that, on the basis of the data of each bit extracted by said bit-data extraction circuit and with reference to the bit location information, reproduces the received serial digital data on condition that the lock status signal is indicative of the locked state; wherein said control device sets the locked state on further condition that two of the identification data have been detected in succession and a parity calculation for a subframe immediately preceding detection of a second one of the two identification data has yielded a predetermined result.