Patent ID: 7595748

Claim:
A method of gain error calibration in a pipelined analog-to-digital converter (ADC), wherein the pipelined ADC comprises a plurality of stages connected in series, each of the stages generates a stage output signal as a stage input signal of a subsequent stage of the series, a first stage and a second stage selected from the stages generate the stage output signals thereof with a common operational amplifier, the method comprising: making the first stage generate the stage output signal thereof according to both a first correction number and the stage input signal thereof; making the second stage generate the stage output signal thereof according to both a second correction number and the stage input signal thereof; collecting a plurality of stage output values respectively generated by the stages; correlating the stage output values with the first correction number to estimate a first gain error estimate of the first stage; correlating the stage output values with the second correction number to estimate a second gain error estimate of the second stage; and weighting the first gain error estimate and the second gain error estimate to obtain a predicted gain error for gain error calibration in the first stage and the second stage.