Patent ID: 8539321

Claim:
Apparatus for correcting at least one bit error within a coded bit sequence, the apparatus comprising: an error syndrome generator configured to determine an error syndrome of a coded bit sequence, wherein the error syndrome is derived by a multiplication of a check matrix (H) with the coded bit sequence, wherein the check matrix (H) comprises a first sub-matrix (H u ), a second sub-matrix (H a ) and a third sub-matrix (H c ), wherein each sub-matrix comprises a plurality of lines, wherein each line comprises a plurality of binary components, wherein at least a first predefined component or a second predefined component of each line of the first sub-matrix (H u ) comprises a first bit value, wherein the second sub-matrix (H a ) comprises lines being linearly independent of each other, wherein the first predefined component and the second predefined component of each line of the second sub-matrix (H a ) comprises a same second bit value, wherein the third sub-matrix (H c ) comprises lines being linearly independent of each other, wherein the first predefined component or the second predefined component of each line of the third sub-matrix (H c ) comprises the first bit value, wherein either an XOR-sum of the first predefined components of all lines of the first sub-matrix (H u ) and the third sub-matrix (H c ) is equal to the second bit value and an XOR-sum of the second predefined components of all lines of the first sub-matrix (H u ) and the third sub-matrix (H c ) is equal to the second bit value, if the first bit value is equal to 1, or an XNOR-sum of the first predefined components of all lines of the first sub-matrix (H u ) and the third sub-matrix (H c ) is equal to the second bit value and an XNOR-sum of the second predefined components of all lines of the first sub-matrix (H u ) and the third sub-matrix (H c ) is equal to the second bit value, if the first bit value is equal to 0, wherein a result of a multiplication of the check matrix (H) and a test vector is equal to a result of a multiplication of the second sub-matrix and a resulting vector, wherein at least one component of the resulting vector comprises the second bit value; and a bit error corrector configured to correct a bit error within the coded bit sequence based on the determined error syndrome of the coded bit sequence.