Patent ID: 8035139

Claim:
A dynamic random access memory (DRAM) device, comprising: a plurality of memory cells, each memory cell including an access junction field effect transistor (JFET) having at least a gate electrode and a drain electrode formed from a semiconductor layer and in physical contact with a semiconductor substrate; and at least one sense amplifier coupled to selected of the memory cells, the sense amplifier including a sense bipolar junction transistor (BJT) having an emitter electrode formed from the semiconductor layer and in physical contact with the semiconductor substrate; wherein, the sense BJT includes a first base region comprising a first portion of the semiconductor substrate doped to one conductivity type, a second base region comprising a second portion of the semiconductor substrate doped to the one conductivity type, a lightly doped base region formed below the emitter electrode comprising a third portion of the semiconductor substrate doped to the one conductivity type, a first base intermediate region disposed between the first base region and the lightly doped base region comprising a fourth portion of the substrate doped to the one conductivity type, and a second base intermediate region disposed between the second base region and the lightly doped base region comprising a fifth portion of the substrate doped to the one conductivity type.