Patent ID: 7335957

Claim:
A semiconductor memory integrated circuit, comprising: a plurality of pads arranged along an axis; a peripheral circuit having a plurality of control circuits which are arranged at varying distances from the pads and are configured to receive a plurality of input signals to generate a plurality of output signals in response to a plurality of control signals; and a plurality of fuse circuits arranged between the plurality of the pads and the peripheral circuit and arranged in a line at substantially the same distance from the axis of the pads, each fuse circuit coupled to a corresponding control circuit and arranged along the same axis as the other fuse circuits; wherein the plurality of fuse circuits are disposed such that the plurality of fuse circuits are accessible through an opening in a BGA package, and wherein a first region on which the plurality of pads and the plurality of fuse circuits are arranged does not overlap with a second region on which a plurality of balls of the BGA package are disposed.