Patent ID: 7594096

Claim:
A data processing system for speculative execution of instructions by a microprocessor non speculative execution of instructions and commits results of said non speculative instructions to at least one architected facility, comprising: means for determining the occurrence of a stall condition during the execution of said non speculative instructions; means for speculatively executing speculative instructions during said stall condition across multiple pipeline stages within said microprocessor; means for determining the validity of speculative data utilized during said speculative execution; means for retrieving valid data for use by said non speculative instructions upon removal of said stall condition, wherein the means for determining the validity of speculative data utilized during said speculative execution comprises means for forwarding validity bits along with the instructions through a pipeline of the microprocessor via a first forwarding path associated with the pipeline of the microprocessor; and means for forwarding dependency on load values along a second forwarding path associated with the pipeline for the speculative instructions, wherein the dependency on load values have at least one dependency on load bit that determines at which one of the multiple pipeline stages the data retrieved by a load instruction is determined to be valid or invalid, and wherein a pipeline stage at which data retrieved by the load instruction is determined to be valid or invalid is any one of the multiple pipeline stages.