Patent ID: 7506233

Claim:
An interface circuit transferring a clock signal and first and second interface signals inputted from the outside of a semiconductor device to an internal circuit of the semiconductor device, comprising: a selection circuit receiving the first and second interface signals, generating a time division serial output signal by selecting one of the first and second interface signals in response to the voltage level of the clock signal, and outputting the time division serial output signal to a single input terminal of the semiconductor device via a single signal line; a first holding circuit connected to the single input terminal for receiving the time division serial output signal, the first holding circuit capturing the first interface signal of the time division serial output signal in response to the transition of the voltage level of the clock signal from a L level to a H level and outputting the first interface signal to the internal circuit; and a second holding circuit connected to the single input terminal for receiving the time division serial output signal, the second holding circuit capturing the second interface signal of the time division serial output signal in response to the transition of the voltage level of the clock signal from the H level to the L level and outputting the second interface signal to the internal circuit.