Patent ID: 7402890

Claim:
A method for forming a structure, comprising: providing, a substrate; forming, a first doped region within said silicon substrate, wherein said first doped region comprises a first dopant having a first polarity; forming, a second doped region within said substrate and over first doped region, wherein said second doped region forms a first electrode of a capacitor; forming, a third doped region within said substrate and over first doped region, wherein said third doped region forms a second electrode of said capacitor, wherein each of said second doped region and said third doped region comprises a same second dopant having a second polarity, wherein said forming said second doped region and said forming said third doped region is performed simultaneously, and wherein said first doped region, said second doped region, and said third doped region in combination form a PN junction; and forming, a first shallow trench isolation structure between said second doped region and said third doped region, wherein said first shallow trench isolation structure isolates said second doped region from said third doped region, wherein said capacitor comprises a main capacitance, wherein said structure comprises a first parasitic capacitance and a second parasitic capacitance, wherein said main capacitance comprises a capacitance between said second doped region and said third doped region, wherein said first parasitic capacitance represents a parasitic connection between said second doped region and said first doped region, wherein said second parasitic capacitance represents a parasitic connection between said third doped region and said first doped region, wherein a first distance between said second doped region and said first doped region is about equal to a second distance between said third doped region and said first doped region, and wherein said first parasitic capacitance is about equal to said second parasitic capacitance.