Patent ID: 8116334

Claim:
A First In First Out (FIFO) communication buffer for receiving data from a source and distributing the data to a first sink and a second sink, the FIFO communication buffer comprising: a FIFO memory having: a first data port for receiving the data from the source, and a first address port for addressing storage of the data written into the first address port; a second data port for providing the data to the first sink, and a second address port for addressing the data for reading from the second data port received at the first address port; and a third data port for providing the data to the second sink, and a third address port for addressing the data for reading from the third data port received at the first address port; and a FIFO control circuit for providing the first address, the second address and the third address, wherein the FIFO control circuit increments the first address toward the second address and the third address when valid data is received, and increments the second address and the third address when the data is read out.