Patent ID: 8817943

Claim:
A shift register comprising a plurality of stages for sequentially outputting A-scan pulses and B-scan pulses, wherein at least one of the stages comprises: an A-sub-stage that controls a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generates an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse; a B-sub-stage that controls a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generates a B-carry pulse based on the voltage at the B-set node, the voltage at the at least one B-reset node and any one B 1 -clock pulse; and a scan output controller that generates a corresponding one of the A-scan pulses based on the voltage at the A-set node and the A-clock pulse and generates a corresponding one of the B-scan pulses based on the B-carry pulse and any one B 2 -clock pulse.