Patent ID: 7768099

Claim:
A semiconductor device, comprising: a first damascene interconnect structure comprising: a conductive via formed through a first interlevel dielectric layer and a first dielectric etch stop layer located under the first interlevel dielectric layer, wherein the conductive via contacts a first interconnect structure located under the first dielectric etch stop layer; and a conductive trench formed through a second interlevel dielectric layer and a second dielectric etch stop layer located between the first and second interlevel dielectric layers, wherein the conductive trench contacts the conductive via; and a metal-insulator-metal capacitor comprising: a first plate electrode formed on a second interconnect structure located under the first dielectric etch stop layer; a second plate electrode formed on the first dielectric etch stop layer and substantially overlapping the first plate electrode; and a second damascene interconnect structure formed through the first and second interlevel dielectric layers and the second dielectric etch stop layer and contacting the second plate electrode.