Patent ID: 6920067

Claim:
An integrated circuit with embedded single-poly non-volatile memory (NVM), comprising a core circuit; and an input/output (I/O) circuit embedded with an array of single-poly non-volatile memory cells, each of the single poly non-volatile memory cells formed in a semiconductor substrate comprising: a well formed in the semiconductor substrate, the well being electrically connected to a well voltage; a first metal-oxide semiconductor (MOS) transistor formed in the well; a drain region of the first MOS transistor electrically connected to a bit line voltage; a second metal-oxide semiconductor (MOS) transistor formed in the well; a source region of the first MOS transistor electrically connected to a drain region of the second MOS transistor; a source region of the second MOS transistor electrically connected to a source line voltage; wherein the first MOS transistor includes a floating gate which is isolated from any other control terminals, a gate of the second MOS transistor is electrically connected to a select gate voltage, wherein the first and second MOS transistors perform the same electrical behavior as those MOS transistors employed in the I/O circuit.