Patent ID: 8440552

Claim:
A method to fabricate a transistor, comprising: providing a wafer comprising a substrate, an insulating layer disposed over the substrate and semiconductor layer disposed over the insulating layer; the wafer being provided with at least one gate structure comprising on sidewalls thereof a layer of dielectric material, a portion of the layer of dielectric material extending away from the gate structure and being disposed on a surface of the semiconductor layer; forming a raised source and a raised drain on the semiconductor layer adjacent to the portion of the layer of dielectric material; removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer between the gate structure and the raised source and the raised drain; applying a layer of material comprised of a glass containing a dopant, the layer of material being applied so as to cover at least the exposed portion of the surface of the semiconductor layer; diffusing the dopant from the layer of material through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region; and removing the layer of material.