Patent ID: 7439126

Claim:
A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, the method comprising: forming a silicon oxide-based first insulating film around a bit line formed on a semiconductor substrate; forming a silicon nitride-based second insulating film on said first insulating film; forming a silicon oxide-based third insulating film on said second insulating film; forming a first resist mask on said third insulating film; forming a first hole that reaches said first insulating film through said second and third insulating films; forming a resist mask having an opening, whose diameter is larger than that of said first hole, on said third insulating film; forming a second hole that reaches a first plug for establishing electrical connection with a diffusion layer of said memory cell selection transistor; forming a second plug by depositing plug material inside said second hole; forming a silicon oxide-based fourth insulating film on said second plug; forming a third hole by etching said fourth insulating film using an end face of said second plug as an etching stopper layer; and forming a conductive film inside said third hole so as to serve as an electrode for said capacitor, wherein said second hole is formed by etching, using said resist mask as an etching mask, under conditions in which an etching rate for said first and third insulating films is higher than an etching rate for said second insulating film.