Patent ID: 7466600

Claim:
A non-volatile memory, comprising: an array of non-volatile memory having a plurality of addressable regions; a memory operable to store data; an address decoder coupled to the array and operable to provide access to the addressable regions; a latch operable to be set to a first state or a second state; and control logic coupled to the memory, address decoder and latch, and operable to query the state of the latch in response to receiving a memory command, in response to the latch having a first state, the control logic operable to read data stored in the memory, set the latch from the first state to the second state, and disable access to defective addressable regions of the array of non-volatile memory identified by the stored data prior to executing the received memory command, in response to the latch having a second state, the control logic operable to execute the received memory command without disabling access to defective addressable regions of the array.