Patent ID: 7952943

Claim:
A semiconductor memory device, comprising: a plurality of column groups each of which includes a plurality of column memory blocks; a column decoder for selecting a column group from the column groups in response to one bit or some bits of a column address signal and addressing column memory blocks of the selected column group in response to remaining bits of the column address signal; and a plurality of main local I/O line groups that are selectively connected to the column memory blocks in response to operation of the column decoder, wherein the column decoder includes a select circuit that transfers the remaining bits of the column address signal to a column group in response to some of bits of the column address signal; a plurality of address drivers that transfer the remaining bits of the column address signal to the column groups, wherein each address driver is connected to output of the select circuit and the number of the address drivers is same as the number of the column groups; and a plurality of decoding units that decode the remaining bits, wherein each decoding unit is connected to the address driver and the number of the decoding units is same as the number of the column groups.