Patent ID: 7289387

Claim:
A wordline decoder for a non-volatile memory device comprising: a first inverter to receive a block selection signal, invert the block selection signal into a first inverted result, and output the first inverted result to a first node; a second inverter to receive a signal on the first node, invert the signal on the first node into a second inverted result, and output the second inverted result to a second node; a first and a second transistor, each transistor having a gate coupled to a power supply, the first and second transistors coupled in series between the second node and a third node, and to transmit a signal on the second node to the third node; a third transistor coupled between the third node and a fourth node and having a gate coupled to the third node; a fourth transistor coupled between a high voltage supply and a fifth node, and having a source coupled to the high voltage supply and a gate coupled to the third node; and a fifth transistor coupled between the fifth node and the third node, and having a gate coupled to the first node.