Patent ID: 7158443

Claim:
A system for providing at least one periodic output clock signal, comprising: a programmable frequency divider having an input terminal receiving an input clock signal, a control terminal receiving a divider select signal, and an output terminal, the programmable frequency being operable to divide the frequency of the input clock signal by an integer number determined by the select signal to generate a clock signal at the output terminal; a delay-lock loop having phase detector and a delay line, the delay line of the delay-lock loop having an input terminal coupled to the output terminal of the programmable frequency divider so that the clock signal generated by the programmable frequency divider propagates through the delay line to generate the at least one periodic output clock signal; and an initialization circuit coupled to the programmable frequency divider and the delay-lock loop, the initialization circuit being operative during an initialization period to set the delay of the delay line to a minimum delay value and to compare the timing of the at least one periodic output clock signal to the timing of the input clock signal, the initialization circuit generating the select signal with a value determined by the timing comparison.