Patent ID: 8675390

Claim:
A Non-Volatile Resistive memory comprising: a first array of bitcells (I/O) having a first voltage reference cell having a first voltage reference cell voltage output, a first voltage reference cell selectable link from the first voltage reference cell voltage output to a first I/O voltage reference line, and a first sense amplifier coupled to the first I/O voltage reference line, wherein the first voltage reference cell is configured to generate at the first reference cell voltage output a first reference voltage approximately midpoint between a given high read voltage and a given low read voltage; a second I/O having a second voltage reference cell having a second voltage reference cell voltage output, a second voltage reference cell selectable link from the second voltage reference cell voltage output to a second I/O voltage reference line, and a second sense amplifier coupled to the second I/O voltage reference line, wherein the second voltage reference cell is configured to generate at the second voltage reference cell output a second reference voltage approximately midpoint between the given high read voltage and the given low read voltage; and a voltage reference line coupling link between the first I/O voltage reference line and the second I/O voltage reference line.