Patent ID: 8299498

Claim:
A semiconductor device comprising: a drain region of one type of nitride semiconductor, the drain region including impurities and being electrically connected to a drain electrode; a drift portion placed above the drain region; a gate portion placed above a part of the drift portion; and a source region of one type of nitride semiconductor, the source region including impurities, being placed above another part of the drift portion and being electrically connected to a source electrode, wherein the drift portion comprises a first hetero junction, the first hetero junction including: a first semiconductor region of one type of nitride semiconductor and a second semiconductor region of another type of nitride semiconductor which are in contact with each other, wherein: the first semiconductor region is placed within a range where the gate portion exists in a plan view and extends along a direction along which the drain region and the gate portion align, the second semiconductor region is placed within the range where the gate portion exists in the plan view and extends along the direction along which the drain region and the gate portion align, and a bandgap energy of the second semiconductor region is different from a bandgap energy of the first semiconductor region, the gate portion comprises a second hetero junction and a gate electrode facing the second hetero junction, the second hetero junction including: a third semiconductor region of one type of nitride semiconductor and a fourth semiconductor region of another type of nitride semiconductor which are in contact with each other, wherein: the third semiconductor region extends along a direction perpendicular to the direction along which the drain region and the gate portion align, the fourth semiconductor region extends along a direction perpendicular to the direction along which the drain region and the gate portion align, and a bandgap energy of the fourth semiconductor region is different from a bandgap energy of the third semiconductor region, the first hetero junction and the second hetero junction are configured to be electrically connected to each other, the second hetero junction is configured to be electrically connected to the source region, the first hetero junction is formed at a c-plane, and the second hetero junction is formed at an a-plane or an m-plane.