Patent ID: 6936887

Claim:
In an array of non-volatile memory cells formed in rows and columns on a semiconductor substrate with elongated source and drain diffusions extending between columns of cells and word lines extending across rows of cells, wherein individual cells have a first channel segment between adjacent source and drain diffusions in the substrate that is controlled by at least one storage element and a second channel segment that is controlled by a select gate portion of one of the word lines, an improved structure comprising: trenches formed in the semiconductor substrate as part of the cells, said second channel portion of the individual cells being provided along at least a sidewall of one of the trenches and the select gate being positioned in the trench, elements of the source and drain diffusions and the first and second channel segments of adjacent cells being formed in a regular non-mirrored pattern in a direction across the array through these elements, and elongated third gates extending across the array along and capacitively coupled with the storage elements.