Patent ID: 8749908

Claim:
A data processing circuit, the circuit comprising: a first comparison circuit operable to compare a first set of digital samples derived from an analog input with a first sync pattern to yield a first comparison value corresponding to a first phase; a second comparison circuit operable to compare a second set of digital samples derived from the analog input with a second sync pattern to yield a second comparison value corresponding to a second phase; a comparator circuit operable to identify the first comparison value as less than the second comparison value, and to provide the first phase as a phase correction output; and an ideal sync pattern circuit operable to provide the first sync pattern corresponding to the first phase and the second sync pattern corresponding to the second phase, wherein the ideal sync pattern circuit includes an ideal sync pattern look up table operable to provide the expected sync pattern at the first phase and the expected sync pattern at the second phase based at least in part on a channel bit density.