Patent ID: 7956404

Claim:
An array of non-volatile memory cells including: a semiconductor body; a plurality of switch-transistor wells disposed within the semiconductor body; a plurality of memory-transistor wells disposed within the semiconductor body and electrically isolated from the memory-transistor wells, each memory-transistor well disposed between two switch-transistor wells; a plurality of memory transistors formed within the plurality of memory transistor wells, each memory transistor including spaced-apart source and drain regions; a first plurality of switch-transistors formed within each switch-transistor well, each switch transistor in the first plurality of switch transistors associated with one of the plurality of memory transistors in a memory-transistor well disposed to a first side of the switch-transistor well in which it is disposed and including spaced-apart source and drain regions; a second plurality of switch-transistors formed within each switch-transistor well, each switch transistor in the second plurality of switch transistors associated with one of the plurality of memory transistors in a memory-transistor well disposed to a second side of the switch-transistor well in which it is disposed opposite to the first side and including spaced-apart source and drain regions; a floating gate associated with each memory transistor, each floating gate insulated from and self-aligned with the source and drain regions of the memory transistor and each switch transistor with which it is associated; and a control gate associated with each memory transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the memory transistor and each switch transistor with which it is associated.