Patent ID: 8412911

Claim:
A method, comprising: receiving, by a demap manager of a processor, a global demap request for invalidation of an address translation from an initiating one of a plurality of cores, wherein the address translation maps a virtual memory address or a real memory address to a physical memory address, wherein the demap manager is a hardware unit of the processor separate from the plurality of cores; in response to the global demap request, performing, by the demap manager of the processor both an internal demap operation and an external demap operation; wherein performing the internal demap operation comprises sending, by the demap manager of the processor, a request to one or more of the plurality of cores other than the initiating core to invalidate the address translation within each of the one or more cores; wherein performing the external demap operation comprises sending, by the demap manager of the processor, a request to one or more other demap managers of one or more other processors to invalidate the address translation in one or more cores of the one or more other processors; receiving, by the demap manager of the processor, an internal acknowledgement that the address translation has been invalidated within at least one of the one or more cores; receiving, by the demap manager of the processor, an external acknowledgement from at least one of the one or more other processors that the address translation has been invalidated within the at least one of the one or more other processors; determining, by the demap manager of the processor, whether the address translation has been invalidated within all of the one or more cores of the processor and all of the one or more cores of the one or more other processors; and in response to determining, by the demap manager of the processor, that the address translation has been invalidated within all of the one or more cores of the processor and all of the one or more cores of the one or more other processors, sending an acknowledgement to the initiating one of the plurality of cores that the request for invalidation has been satisfied.