Patent ID: 8004907

Claim:
A memory comprising: a static random access memory (SRAM) bitcell comprising a pair of cross-coupled inverters, wherein a first inverter of the pair of cross-coupled inverters includes a first device having a body and a second inverter of the pair of cross-coupled inverters includes a second device having a body; a first selection circuit having a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device; a second selection circuit having a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of the first device and to the body of the second device; a word line coupled to the SRAM bitcell; and a word line driver coupled to the first supply voltage terminal and which drives the word line.