Patent ID: 7829957

Claim:
A semiconductor device which includes an enhancement-mode field-effect transistor and a depletion-mode field-effect transistor on a same semiconductor substrate that includes GaAs, said semiconductor device comprising: a first threshold adjustment layer including AlGaAs adjusting a threshold voltage of a gate of the enhancement-mode field-effect transistor; a first etching stopper layer formed on said first threshold adjustment layer, said first etching stopper layer including disordered InGaP; a second threshold adjustment layer formed on said first etching stopper layer, said second threshold adjustment layer adjusting the threshold voltage of a gate of the depletion-mode field-effect transistor and including AlGaAs; a second etching stopper layer formed on said second threshold adjustment layer, said second etching stopper layer including disordered InGaP; a contact layer formed on said second etching stopper layer; a first source electrode and a first drain electrode, which are a source electrode and a drain electrode, respectively, in the enhancement-mode field-effect transistor, said first source electrode and said first drain electrode forming ohmic contact with said contact layer; a second source electrode and a second drain electrode, which are a source electrode and a drain electrode, respectively, in the depletion-mode field-effect transistor, said second source electrode and said second drain electrode forming ohmic contact with said contact layer; a first gate electrode of the enhancement-mode field-effect transistor, which is formed in an opening defined by removing said contact layer, said second etching stopper layer, and said second threshold adjustment layer, and which is in contact with said first threshold adjustment layer, said first gate electrode penetrating through said first etching stopper layer in a double recess structure; and a second gate electrode of the depletion-mode field-effect transistor, which is formed in an opening defined by removing said contact layer and which is in contact with said second threshold adjustment layer, said second gate electrode penetrating through said second etching stopper layer in the double recess structure.