Patent ID: 7317251

Claim:
A multichip module comprising at least one first semiconductor chip and at least one second semiconductor chip, the semiconductor chips being arranged in a coplanar manner with respect to each other on or in a support medium and including contact areas arranged on active top sides of the first and second semiconductor chips; wherein at least one second semiconductor chip is arranged adjacent with at least one first semiconductor chip, and the at least one second semiconductor chip includes an arrangement of contact areas that is at least partly mirror image symmetrical in relation to an arrangement of contact areas of the at least one first semiconductor chip that is adjacent the second semiconductor chip such that contact areas disposed at or near a first edge of a first semiconductor chip are aligned and correspond with contact areas disposed at or near a first edge of an adjacent second semiconductor chip that faces the first edge of the first semiconductor chip, and contact areas disposed at or near a second edge of the first semiconductor chip that opposes the first edge of the first semiconductor chip are aligned and correspond with contact areas disposed at or near a second edge of the adjacent second semiconductor chip that opposes the first edge of the second semiconductor chip; and wherein first wiring arrangements extend between contact areas of adjacent first and second semiconductor chips, and second wiring arrangements extend from contact areas on at least some of the semiconductor chips to external contacts on the multichip module.