Patent ID: 8285524

Claim:
A simulation method comprising: determining a relationship between stress time and a degradation rate of drain current on a basis of a first table in which data of a lifetime of an evaluation target transistor, at a reference degradation rate, said lifetime being dependent on voltage, is written for three kinds of voltages, that is, gate voltage, drain voltage and back bias voltage, or on a basis of a second table in which data of said degradation rate of said drain current of said evaluation target transistor, during a reference time, said degradation rate of said drain current being dependent on voltage, is written for said three kinds of voltages; and calculating an amount of change in drain current in accordance with said degradation rate of said drain current, using a third table in which information indicating a change in said drain current, said information being dependent on voltage, is written for said three kinds of voltages, said third table being based on actually measured data, at said reference degradation, of drain current of said evaluation target transistor after degradation according to said stress time, drain current in an initial state of a particular transistor model and said relationship between said stress time and said degradation rate of said drain current.