Patent ID: 8890626

Claim:
A method for phase detection within a divider-less phase locked loop (PLL), comprising: receiving a pulse phase detector (pulse PD ) signal associated with a reference frequency; receiving a voltage controlled oscillator positive differential (VCOP) signal and a voltage controlled oscillator negative differential (VCON) signal, the VCOP signal and the VCON signal corresponding to a differential pair associated with an output frequency of a voltage controlled oscillator (VCO); generating a first up signal and a first down signal for a first charge pump (CP), at least one of the first up signal or the first down signal based on the pulse PD signal and at least one the first up signal or the first down signal based on the VCOP signal; and generating a second up signal and a second down signal for a second CP, at least one of the second up signal or the second down signal based on the pulse PD signal and at least one of the second up signal or the second down signal based on the VCON signal.