Patent ID: 8022455

Claim:
A semiconductor device comprising: a semiconductor substrate having buried contact landing pads and direct contact landing pads; a lower interlayer insulating layer disposed on the semiconductor substrate; a plurality of parallel bit line patterns disposed on the lower interlayer insulating layer to fill the direct contact holes; a passivation layer conformally covering the lower interlayer insulating layer and the bit line patterns; an upper interlayer insulating layer covering the semiconductor substrate having the passivation layer; buried contact plugs disposed in the upper interlayer insulating layer between the bit line patterns and extended to contact the respective buried contact landing pads through the passivation layer and the lower interlayer insulating layer; storage node electrode holes formed in the upper interlayer insulating layer, the storage node electrode holes exposing upper surfaces of the buried contact plugs; and voids formed in the upper interlayer insulating layer between the bit line patterns and between the buried contact plugs.