Patent ID: 7294937

Claim:
A multi-layer semiconductor wafer structure defining a multiplicity of dies formed thereon, said wafer structure comprising: at least two first scribe lines having a selected width S 1 , each of said at least two first scribe lines extending along a first orientation and defining a first edge of at least two first dies of said multiplicity of dies; at least two second scribe lines having a selected width S 2 , each of said at least two second scribe lines extending along a second orientation and defining a second edge of at least two second dies and intersecting said at least two first scribe lines, and said first edges of said at least two first dies and said second edges of said at least two second dies intersecting at corner points; first restricted areas A 1 defined on said first scribe line where placement of a test key is restricted, and said first restricted areas A 1 being defined by the equation A 1 =D 1 ×S 1 , where D 1 is the distance along the first edge extending from a corner point of said at least two first dies; second restricted areas A S at intersections of said at least two first scribe lines and said at least two second scribe lines, said second restricted areas A S being defined by the equation A S =S 1 ×S 2 ; at least one first test key formed on each one of said at least two first and said at least two second scribe lines, but not on said restricted areas A and A S ; and at least one second test key formed in at least one of said A 1 restricted areas and said A S restricted areas.