Patent ID: 7013563

Claim:
A method of testing spacings in at least one pattern of openings in at least one conductive layer of a multilayered printed circuit board (PCB) to determine if said spacings meet acceptable criteria, said method comprising: providing a multilayered PCB including an active area having at least one internal conductive layer having at least one pattern of openings therein; providing a plurality of first patterns of apertured test pads spacedly positioned substantially along the outer periphery of said multilayered PCB externally of said active area; providing a plurality of second patterns of apertured test pads spacedly positioned substantially adjacent said active area of said multilayered PCB and closer to said active area than said plurality of first patterns of apertured pads; drilling a plurality of holes through said plurality of first patterns of apertured test pads to determine if each of said plurality of first patterns meet a first acceptable tolerance value; drilling a plurality of holes through said plurality of second patterns of apertured test pads to determine if each of said plurality of second patterns meet a second acceptable tolerance value; comparing said second acceptable tolerance value to an acceptable tolerance value assigned to said at least one pattern of openings in said active area of said multilayered PCB only if one or more of said first patterns of said apertured test pads fail to meet said first acceptable tolerance value; and determining whether said patterns of openings in said active area meet said acceptable criteria based solely on whether the second pattern of apertured test pads nearest said pattern of openings meets said second acceptable tolerance value and not on whether others of said second patterns of apertured test pads meet said second acceptable tolerance value.