Patent ID: 8435849

Claim:
A method of forming a CMOS IC, comprising the steps of: forming a first polysilicon layer on a top surface of a first gate dielectric layer in an NMOS area and a top surface of a second gate dielectric layer in a PMOS area; forming a compressively stressed metal layer on a top surface of said first polysilicon layer; forming an NMOS stress layer photoresist pattern on a top surface of said compressively stressed metal layer in said NMOS area; removing said compressively stressed metal layer from areas exposed by said NMOS stress layer photoresist pattern; removing a portion of said first polysilicon layer from areas exposed by said NMOS stress layer photoresist pattern; forming a second polysilicon layer on a top surface of said compressively stressed metal layer and a top surface of said first polysilicon layer; forming a gate photoresist pattern on a top surface of said second polysilicon layer in said NMOS area over said compressively stressed metal layer and in said PMOS area; removing said second polysilicon layer, said compressively stressed metal layer, and said first polysilicon layer from areas exposed by said gate photoresist pattern.