Patent ID: 8799729

Claim:
An integrated circuit comprising: A. an output pad; B. first core circuitry having: i. a first data output lead coupled to the output pad; ii. a first data input lead; iii. first functional circuitry having a functional output formed of an output buffer circuit having an output coupled to the first data output lead, a functional input formed of an input buffer circuit having an input coupled to the first data input lead, and first parallel scan paths, each scan path having a serial output; iv. first scan collector circuitry having a serial input coupled to the first data input lead, a serial output, and parallel inputs connected to the serial outputs of the first parallel scan paths; and v. a first collector output buffer having an input connected to the serial output of the first scan collector circuitry, an output coupled to the first data output lead, and a control input that selectively disconnects the buffer input from the buffer output; C. second core circuitry having: i. a second data output lead; ii. second functional circuitry having a functional output formed of an output buffer circuit having an output coupled to the second data output lead, and second parallel scan paths, each scan path having a serial output; iii. second scan collector circuitry having a serial output coupled to the second data output lead, a serial input, and parallel inputs connected to the serial outputs of the second parallel scan paths; and D. multiplexer circuitry having a first input coupled to the second data output lead, a second input, and an output coupled to the first data input lead.