Patent ID: 7873923

Claim:
A method performed on a computer system, comprising: using the computer system to perform the following: synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch from one state to another state less often than an amount specified by a user-defined low switching node threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching, wherein the power gating logic expression determining includes: functionally simulating the potential PGC; determining a least common output value of the potential PGC based on the functional simulating; and selecting the minimum set of inputs to the potential PGC that are least switching and encompasses the least common output value based on the functional simulating as the power gating logic expression, wherein the selecting includes: selecting a value N less than a total number of inputs to the potential PGC; for each input subset with size equal to the value N, formulating logic expressions using the input subset that encompasses the least common output value and all possible input expressions that generate the least common output value; determining whether energy savings using the power gating logic expression meets a user-defined energy savings criteria that is representative of an acceptable level of energy savings to substantiate accepting the potential PGC; and accepting the potential PGC in response to meeting the user-defined energy savings criteria.