Patent ID: 7151470

Claim:
A data converter for accepting padded input data at one of a plurality of first data widths each having a corresponding first data rate, and outputting padded data at one of a plurality of second data widths each having a corresponding second data rate, said data converter comprising: a first number of data register units each of a register width receiving said input; a second number of data selector units each of a selection width and each connected to a transmission conductor, for routing each bit received at said register units to one of said transmission conductors, said transmission conductors transmitting said padded output data; a plurality of clock sources for providing respective pairs of clocks corresponding to respective ones of said selected pairs of first and second data widths; and: a programmable clock selector for programmably selecting a respective pair of clocks corresponding to respective one of said selected pairs of first and second data widths; wherein: said first number, said second number, said register width and said selector width are determined by a widest one of said plurality of first data widths and a widest one of said plurality of second data widths.