Patent ID: 6870831

Claim:
A time:space:time switch fabric, comprising: (a) a plurality of spatially distributed data switches, each one of said data switches further comprising: (i) a first plurality of ingress ports; (ii) a plurality of egress ports equal to said first plurality; (iii) a space switch for selectably spatially rearranging data transmission between any one of said ingress ports and any one of said egress ports; (iv) an ingress time switch coupled to an input of said space switch, said ingress time switch for selectably temporally rearranging data received on said ingress ports; (v) an egress time switch coupled to an output of said space switch, said egress time switch for selectably temporally rearranging data output by said space switch; (b) a plurality of spatially distributed data serializers, each one of said data serializers further comprising: (i) an input bus for receiving signals to be routed through said switch fabric; (ii) an output bus for outputting signals routed through said switch fabric; (iii) a second plurality of egress ports, each one of said data serializer egress ports further comprising a high speed serial link selectably connectible to any one of said data switch ingress ports; (iv) a plurality of ingress ports equal to said second plurality, each one of said data serializer ingress ports further comprising a high speed serial link selectably connectible to any one of said data switch egress ports; wherein: (i) said data switch ingress and egress ports and said data serializer ingress and egress ports further comprise a composite fabric of said data switches characterized by at least: (1) p planes, where p is a power-of-two integer less than or equal to said second plurality of said data serializer ingress and egress ports; (2) s stages, where s is an odd integer number; (3) a depth d, where d is a power-of-two integer less than or equal to said first plurality of said data switch ingress and egress ports; said composite fabric comprising p*s*d inter-connected ones of said data switches; (ii) said data switch ingress ports of a first one of said stages are coupled to said data serializer egress ports; (iii) said data switch egress ports of an s th one of said stages are coupled to said data serializer ingress ports; and, (iv) said data switch egress ports of each n th one of said stages are coupled to data switch ingress ports of each n+1 th one of said stages, where 1<n<s.