Patent ID: 8115251

Claim:
A recessed gate FET comprising: a substrate having an upper doped portion having a first conductivity and a lower doped portion having the first conductivity beneath a substrate surface; a gate structure formed within a trench beneath the substrate surface, said gate structure having a gate dielectric surrounding the sidewalls and bottom of said trench, and having a gate conductor present on the gate dielectric and filling the trench, a top surface of said gate conductor being recessed from an upper substrate surface; a channel region surrounding the gate structure, and in direct contact with the gate dielectric, wherein the channel region is in contact with the upper doped portion and is in contact with the lower doped portion of the substrate; source and drain diffusion regions of a second conductivity formed at either side of said gate structure at said substrate surface, wherein the source and drain diffusion regions are in direct contact with a portion of the channel region that is present in the upper doped portion of the substrate, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, such that said bottom portion of said trench exhibits lower threshold voltage than an upper portion of said trench, said recessed gate FET thereby exhibiting improved suppression of short channel effects.