Patent ID: 7865790

Claim:
An on-chip stuck-at fault detector in an integrated circuit using a test circuit for critical path testing, comprising: a sequence circuit having a first sequential circuit and a second sequential circuit, the sequence circuit being enabled to sensitize the critical path between a source sequential circuit and a destination sequential circuit; wherein the sequence circuit includes an output coupled to an input of the source sequential circuit; an analyzer circuit including an analyzer sequential circuit having an input coupled to the output of the destination sequential circuit and enabled to capture an output from the destination sequential circuit in the analyzer sequential circuit, the analyzer circuit configured to compare a signal output from the destination sequential circuit and a signal output from the analyzer sequential circuit at predetermined clock cycles; a controller configured to enable storage of value in a sticky-bit flip flop in the analyzer circuit at the predetermined clock cycles; wherein the first sequential circuit is initialized to a zero mode and the second sequential circuit is initialized to a zero mode; and wherein no stuck-at faults are determined to be present in the sequence circuit in response to the analyzer circuit determining that the signals output from the destination sequential circuit and the analyzer sequential circuit have different values during the predetermined clock cycles, and the analyzer circuit further configured to store a zero result in the sticky-bit flip flop in response to the signals output from the destination sequential circuit and the analyzer circuit having different values during the predetermined clock cycles; and wherein a stuck-at fault is determined to be present in the sequence circuit in response to the analyzer circuit determining that the signals output from the destination sequential circuit and the analyzer sequential circuit have equal values, and the analyzer circuit further configured to store a one result in the sticky-bit flip flop in response to the signals output from the destination sequential circuit and the analyzer circuit having equal values during the predetermined clock cycles.