Patent ID: 7557742

Claim:
A pipelined analog-to-digital converter comprising: a first sigma-delta converter having a first input terminal, a first output terminal, and a first error terminal, receiving an input signal at the first input terminal, providing a first partial digital output signal at the first output terminal, and providing a first error signal at the first error terminal; a first sample-and-hold stage having a second input terminal in communication with the first error terminal and a second output terminal, receiving the first error signal at the second input terminal and providing a first hold signal at the second output terminal; a second sigma-delta converter having a third input terminal in communication with the second output terminal and a third output terminal, receiving the first hold signal at the third input terminal and providing a second partial digital output signal at the third output terminal, wherein each of the first sigma-delta converter and the second sigma-delta converter is second-order or higher.