Patent ID: 7363598

Claim:
A method for minimizing an impact of process variation in an electronic circuit design of an integrated circuit, comprising: based on an electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit; calibrating the pattern dependent model based upon an information from a patterned test wafer or a test semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising other than an oxide chemical mechanical polishing process; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.