Patent ID: 8055871

Claim:
A method for switching synchronous data transaction speeds across a memory interface between a processing device and a synchronous memory, comprising: receiving a clock at a first speed across the memory interface; locking a clock unit within the synchronous memory to produce an output clock at a full speed using a first set of clock divider values and the clock at the first speed as an input; receiving a speed change command that specifies a second speed for synchronous data transactions across the memory interface that is different than the full speed; configuring the clock unit to continue to produce the output clock at the full speed using a second set of clock divider values and the clock at the second speed as the input; allowing the output clock to drift by disabling updates to the clock unit while the clock divider values are changed from the first set of values to the second set of values; and performing the synchronous data transactions across the memory interface between the processing device and the synchronous memory at the second speed while receiving the clock at the second speed and maintaining the output clock at the full speed while the clock changes from the first speed to the second speed and after the clock is received at the second speed.