Patent ID: 8239638

Claim:
A processor comprising: a load/store unit comprising a queue, wherein the load/store unit is configured to issue a store memory operation from the queue, and wherein the queue is further configured to store data to be written to memory in response to the store memory operation; a data cache coupled to the load/store unit and accessed by the store memory operation in parallel with writing the store memory operation into the queue in the load/store unit, wherein the queue is configured to store a cache hit/miss indication for the store memory operation, wherein the cache hit/miss indication indicates hit/miss in the data cache; a memory request buffer coupled to the load/store unit; and a control unit configured to cause the issued store memory operation to write the data cache with the data from the queue responsive to the issued store memory operation only updating one or more complete error correction code (ECC) granules and the cache hit/miss indication indicating cache hit, and wherein the control unit is configured to cause the issued store memory operation and the data from the queue to be written to the memory request buffer responsive to the issued store memory operation partially updating at least one ECC granule and the cache hit/miss indication indicating cache hit, wherein the data cache is written at a first pipeline stage of a load/store pipeline in the processor in response to the issued store memory operation and the memory request buffer is written at a second pipeline stage of the load/store pipeline that is subsequent to the first pipeline stage in the load/store pipeline in response to the issued store memory operation.