Patent ID: 8264871

Claim:
A device comprising: a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the word lines, and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines; a switch circuit including a first terminal and a plurality of second terminals each coupled to an associated one of the bit lines, the switch circuit being configured to form an electrical path between the first terminal and a selected one of the second terminals; a write circuit configured to write data into a selected one of the memory cells through the switch circuit, the write circuit comprising, a first potential line supplied with a first potential voltage, a second potential line supplied with a second potential voltage, a first transistor coupled between the first potential line and the first terminal of the switch circuit, a first latch circuit including first and second input/output nodes, a second transistor coupled between the first input/output nodes of the first latch circuit and the second potential line, a third transistor coupled between the second input/output node of the first latch circuit and the second potential line, a second latch circuit including third and fourth input/output nodes, a fourth transistor coupled between the third input/output node of the second latch circuit and the second potential line, fifth and sixth transistors coupled in series between the fourth input/output node of the second latch circuit and the second potential line, a control electrode of the fifth transistor being coupled to the first input/output node of the first latch circuit, and a first gate circuit including a first input node coupled to the third input/output node of the second latch circuit, a first output node coupled to a control electrode of the first transistor, a first control node coupled to the second input/output node of the first latch circuit, and a second control node coupled to the second input/output node of the first latch circuit; and a control circuit supplying a first signal to a control electrode of the second transistor, a second signal to control electrodes of the third and fourth transistors, and a third signal to a control electrode of the sixth transistor.