Patent ID: 7952390

Claim:
A logic circuit, comprising: a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state; a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain; and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops, wherein the input signal is controlled by a first signal in a first test operation and controlled by a second signal in a second test operation, the first signal assuming an enable value during a test using the scan chain, the second signal assuming an enable value during a scan shift in which the scan chain performs a shift operation, and the second signal assuming both an enable value and a disable value during a capture time in which the at least one of the plurality of scan flip-flops loads data from the combinational logic circuit.