Patent ID: 7804994

Claim:
An overlay method for determining the overlay error of a device structure formed during semiconductor processing, comprising: for a first set of process conditions, producing calibration data that specifies a relative difference between an overlay error of a first target at a first location of a test wafer and a second target at a second location of the test wafer, wherein the first location corresponds to a location on a production wafer that is outside a die area of a production wafer and the second location corresponds to a location that is inside the die area of the production wafer; measuring an overlay error of a production target that is located approximately at the first location that is outside the die area on a production wafer formed with the given set of process conditions, wherein the production wafer also includes a device structure that is located approximately at the second location within the die area of the production wafer; and determining an overlay error of the device structure by adjusting the overlay error, which was measured for the production target, by the relative difference between the overlay errors of the first and second targets of the test wafer as specified in the calibration data, wherein the overlay error of the device structure is determined without measuring an overlay error on the device structure.