Patent ID: 8324939

Claim:
A differential logic circuit comprising: a differential logic unit which receives a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of differential signal output terminals thereof; a current source circuit which supplies controllable current to the differential logic unit; a load circuit connected to the pair of differential signal output terminals; and a load control circuit comprising a constant voltage control loop comprising: an input terminal for receiving a direct-current output voltage of the differential logic circuit; and an output terminal connected to a voltage control node of the load circuit, wherein the load control circuit is connected to the load circuit and controls a load of the load circuit such that the direct-current output voltage of the pair of differential signal output terminals is constant; wherein the differential logic unit comprises: a switch circuit which receives a pair of differential logic signals as differential clock signals and selectively connects a differential pair or a holding unit to the current source circuit, based on the differential clock signals and the differential logic circuit functions as a data latch.