Patent ID: 8397213

Claim:
A method for programming hardware for processing user data on a machine including the hardware, comprising the following steps: a) a plurality of modules are made available, wherein each module can execute at least one function for processing the user data; b) the modules are classified into a plurality of module types according to predetermined properties; c) interfaces for interconnecting the modules are provided; d) interconnection rules are defined depending on the module types to accomplish self-regulating control of a data flow between the interconnected modules by means of control and inhibit signals; d1) wherein the inhibit signals are generated by a module type; d2) wherein the data flow is stopped by an active inhibit signal running in opposite direction to the direction of the data flow; d3) wherein the control signals running in the direction of the data flow control the data flow via the indication of the validity of data; e) an interconnection of the modules (topology) which corresponds to a sequence of functions which is valid for processing the user data is provided; and f) the hardware programming is generated from the topology thereby enabling the machine to process user data, characterized in that a module has an output latency which determines the number of valid data words the module can output after the data flow to this module has been stopped.