Patent ID: 8583841

Claim:
A video relay circuit, comprising: an input channel adapted to receive input video data packets from an input video data stream, wherein the input video data stream is in High Definition Multimedia Interface (HDMI) format and is associated with a stream clock signal having a first period; a first circuit configured to: generate a local clock signal having a second period; convert the input video data packets into DisplayPort (DP) video data packets for a display device; and transmit, in a link signal, the DP video data packets and a factor relating the first period to the second period; a second circuit coupled to the first circuit and configured to: receive the link signal from the first circuit; obtain the factor from the link signal; recover, based on the factor and the second period, the stream clock signal; and retime and recondition the DP video data packets using the stream clock signal; and an output channel adapted to receive the DP video data packets from the second circuit, and to provide the DP video data packets into an output video data stream associated with the stream clock signal, wherein the output video data stream is in HDMI format.