Patent ID: 8049650

Claim:
A method for testing a high-speed digital to analog converter based on an undersampling technique, comprising: providing a tested digital to analog converter integrated with a triangular pattern generator, a PWM device, a synchronous control circuit, a digital processing circuit, and a modulation circuit to form an equivalent analog to digital converter; deducing a piecewise relationship of an input of a signal generator comprising a digital to analog converter and an output of the equivalent analog to digital converter; the signal generator generating a uniform-distribution random analog output signal to the equivalent analog to digital converter; collecting signals from an output terminal of the equivalent analog to digital converter, and substituting the signals into the piecewise relationship to obtain a transition voltage of the equivalent analog to digital converter; calculating nonlinearity of the equivalent analog to digital converter to obtain a nonlinear error of the tested digital to analog converter; deducing a test result of the tested digital-analog converter from the transition voltage and a nonlinear error of the equivalent analog to digital converter and the nonlinear error of the tested digital to analog converter.