Patent ID: 7958327

Claim:
A data processing system comprising: a processor; a memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; an asynchronous memory mover (AMMR) coupled to the processor; an instruction fetch unit (IFU) that provides instructions for executing on the processor, wherein said instructions include an asynchronous memory move (AMM) store (ST) instruction that the processor executes to perform the following functions: initiating the AMMR to perform an asynchronous memory move operation in a virtual address space, wherein the asynchronous memory move operation moves data from a first memory location having a first real address to a second memory location having a second real address utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location; reading the data from the source effective address; tagging the data with the destination effective address within an effective address space to complete a processor level effective address move of a corresponding AMM operation in virtual address space; and triggering the AMMR to complete a physical move of the data to the second memory location, wherein the physical move occurs independent of the processor.