Patent ID: 7408981

Claim:
A receiver comprising: a. a first sampler having: i. a first plurality of sampler input terminals, including a first sampler data terminal to receive an input data stream and a first sampler reference terminal; and ii. a first sampler output terminal to produce a first sampled data stream from the input data stream; b. a second sampler having i. a second plurality of sampler input terminals, including a second sampler data terminal to receive the input data stream and a second sampler reference terminal; and ii. a second sampler output terminal to produce a second sampled data stream from the input data stream; c. a feedback circuit having: i. a plurality of delay elements selectively coupled to the first and second sampler output terminals to alternatively receive one of the first and second sampled data streams, each delay element to provide at least one historical bit from the selected one of the first and second sampled data streams; and ii. a plurality of data-weighting circuits, each data-weighting circuit coupled between one of the plurality of delay elements and at least one of the first and second sampler input terminals to provide a weighted feedback to the at least one of the first and second sampler input terminals based on the at least one historical bit from the corresponding delay element; and d. a comparison circuit to compare the first sampled data stream with the second sampled data stream; wherein the comparison circuit produces an error signal responsive to a mismatch between the first and second sampled data streams.