Patent ID: 7064738

Claim:
A liquid crystal display device comprising: a liquid crystal display panel which has a plurality of pixels constituted of active elements and formed in a matrix; a plurality of drain drivers which apply driving voltages based on control signals including image data and pixel clock signals inputted from an external signal source to a plurality of pixels in a lateral direction of the matrix; a plurality of gate drivers which apply scanning voltages to a plurality of pixels in a longitudinal direction of the matrix; and a display control device having parallel-serial conversion means which performs a parallel-serial conversion of the image data based on the pixel clock signals and supplies the image data to the drain drivers, wherein the display control device comprises: a clock signal synthesizer which generates reference clock signals formed by multiplying a frequency of the pixel clock signals inputted from the external signal source “a” times, and a clock signal comparator circuit which compares the inputted pixel clock signals and an output of the reference clock signals of the clock signal synthesizer, determines whether it is effective or ineffective based on the presence or the absence of the irregularity of timing of the pixel clock signals, and outputs a clock ineffective signal which stops the supply of the pixel clock signals to the parallel-serial converting means, when the result of the determination is ineffective, provided that the number of the image data is set to N pieces, the number of display data inputted to the drain drivers of the liquid crystal display panel is set to M pieces, and N/M is set to satisfy the relationship of 1/a (a: integer), the N pieces of display data is converted into M pieces of display data (M≦N) based on clocks a×CL which is obtained by multiplying the frequency “a” times using a clock multiplying circuit and, thereafter, the M pieces of display data are inputted to the drain drivers at double edges consisting of rising of signal and falling of signal of the clocks CL.