Patent ID: 7960284

Claim:
A III-V compound semiconductor substrate manufacturing method, comprising: a polishing step of polishing the surface of a platelike III-V compound semiconductor crystal until the arithmetic-mean roughness of the surface decreases to a first roughness Ra 1 of 50 Å or less; a cleaning step, subsequent to said polishing step, of cleaning the III-V compound semiconductor crystal surface; a first dry-etching step, subsequent to said cleaning step, of applying first bias power to an electrode for carrying the III-V compound semiconductor crystal, and meanwhile subjecting the crystal surface to first dry-etching employing a first halogen-containing gas; and a second dry-etching step, subsequent to said first dry-etching step, of applying second bias power smaller than the first bias power to the electrode, and meanwhile subjecting the III-V compound semiconductor crystal surface to second dry-etching employing a second halogen-containing gas to thereby decrease the arithmetic-mean roughness of the surface to a second roughness Ra 2 that is less than said first roughness Ra 1 , such that Ra 2 /Ra 1 is less than 1.0 and such that the photoluminescent intensity through the semiconductor crystal is at least 30% enhanced over the crystal's photoluminescent intensity prior to said dry-etching steps.