Patent ID: 8432742

Claim:
A non-volatile memory cell array, comprising: sector selection transistors controlled by a voltage applied to sector selection lines; first through fourth memory cells connected in series to the sector selection transistors; a first common source line connected between the first memory cell and the second memory cell; and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line, wherein a first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line, wherein each of the memory cells comprises a memory transistor controlled by a voltage applied to the selection lines and a control gate controlled by a voltage applied to the word lines and connected in series to the memory transistor, wherein the memory cells comprise first through fourth memory cells connected in series to each other while sharing a bit line, the word lines comprise first through fourth word lines connected to control gates of the first through fourth memory cells, respectively, the selection lines comprise first through fourth selection lines connected to memory transistors of the first through fourth memory cells, respectively, the common source lines comprise first and second common source lines, the first common source line is connected between the control gate of the first memory cell and the control gate of the second memory cell, and the second common source line is connected between the control gate of the third memory cell and the control gate of the fourth memory cell, wherein the first memory cell is programmed by applying the first voltage to the first common source line and the second voltage to the second common source line, applying a third voltage different from the first and second voltages to the first through fourth word lines and the bit line, applying a fourth voltage different from the first through third voltages to the first selection line, and applying a ground voltage to the second through fourth selection lines.