Patent ID: 8169049

Claim:
A semiconductor device comprising: a plurality of memory dies each comprising: a first wiring layer comprising a first connecting portion; a second wiring layer; a first insulation layer formed between the first wiring layer and the second wiring layer to insulate the first wiring layer and the second wiring layer; and a first interlayer connector having a fuse function disposed in a first contact hole formed through the first insulation layer to electrically connect the first wiring layer and the second wiring layer; a controller configured to control the memory dies; a package housing the memory dies and the controller; a connecting portion electrically connecting an inner side of the package and an outer side of the package; a first connecting wire connecting the connecting portion and the first connecting portion; and a second connecting wire connecting the connecting portion and the controller, wherein a resistance value per unit length of the first interlayer connector is larger than a resistance value per unit length of the first wiring layer, and wherein the first interlayer connector is cut off in the contact hole if a first current exceeding a threshold current flows through the first interlayer connector.