Patent ID: 7339240

Claim:
A dual gate integrated circuit, comprising: high voltage gate transistors located on a semiconductor substrate and each having a nitridated, high voltage gate dielectric located thereunder; low voltage gate transistors located on said semiconductor substrate and each having a nitridated, low voltage gate dielectric located thereunder, each of said low voltage gate dielectrics having substantially a uniform thickness within about 1 nm of a target thickness of said low voltage gate dielectric, wherein a goodness of fit between said semiconductor substrate and said nitridated low voltage gate dielectrics ranges from about 0.997 to about 0.999; source/drain regions associated with each of said high voltage and low voltage transistors; dielectric layers located over said high voltage and low voltage transistors; and interconnects extending through said dielectric layers to interconnect said high voltage and low voltage transistors to form an operative integrated circuit.