Patent ID: 8886997

Claim:
A hardware security module, comprising: a microprocessor and a program encoded on a non-transitory medium readable by said microprocessor that, upon execution by said microprocessor, causes said microprocessor to carry out an operation, wherein the hardware security module is configured, according to a master-slave mode of communication with an external master entity over a first communication channel, to receive a command to execute the program thereby to carry out the operation and to transmit a corresponding response, wherein the program is a compiled program comprising code that is executable by the microprocessor, said code including at least one debugging instruction, wherein, whether or not said at least one debugging instruction is executed, said at least one debugging instruction does not modify the carrying out of said operation when the program is executed, the debugging instruction provided for debugging the code that forms the program, and wherein the hardware security module is configured to: in response to receipt of the received command to execute the program, execute the program and thereby generate debugging data resulting from execution of the at least one debugging instruction incorporated within the program, and transmit, during the execution of the compiled program, said generated debugging data to an external entity over a second communication channel, said second communication channel being initiated by the hardware security module.