Patent ID: 7005754

Claim:
A semiconductor device assembly, comprising: at least one semiconductor device package having a plurality of conductors extending from a first exposed surface of the at least one semiconductor device package and at least two apertures extending from the first surface to a second, opposing exposed surface of the at least one semiconductor device package; a carrier substrate having at least two alignment features thereon spaced and positioned in correspondence to spacing and positioning of the at least two apertures, the at least one semiconductor device package superimposed over the carrier substrate with the at least two apertures aligned with the at least two alignment features, wherein the carrier substrate includes a plurality of terminal pads located and configured to correspond with the plurality of conductors when the at least two apertures are aligned with the at least two alignment features; and structure securing the at least one semiconductor device package to the carrier substrate comprising pins inserted through the at least two apertures and secured to the carrier substrate, wherein each of the pins includes at least one mechanical locking feature located adjacent an end thereof.