Patent ID: 8897076

Claim:
A non-volatile memory system comprising: a data cell array including a plurality of main memory cells in which data are stored; and a reference cell array including, a plurality of first reference word lines connected to first reference memory cells and extending in a first direction, a plurality of second reference word lines connected to second reference memory cells and extending in the first direction alternately with the first reference word lines, a plurality of reference bit lines to each of which the first and the second reference memory cells are alternately connected in a line extending in a second direction perpendicular to the first direction, and a combined cell having at least one pair of the first reference memory cell and the second reference memory cell that share a common gate, the common gate being enabled in both the first reference memory cell and the second reference memory cell in the at least one pair such that a current flows in both the first reference memory cell and the second reference memory cell in the at least one pair at a same time to generate a reference signal for processing the data in the main memory cell, the first and the second reference memory cells having different cell characteristics.