Patent ID: 7626422

Claim:
An output driver operating at a given data rate, comprising: a plurality of transistors including a first and a second transistor, receiving at least one input signal; a plurality of resistors including a first resistor connected between a drain of the first transistor and a first voltage and a second resistor connected between a drain of the second transistor and the first voltage, the first resistor being a portion of a first plurality of resistors and the second resistor being a portion of a second plurality of resistors, wherein at least one of the first or second plurality of resistors is selectively connected in response to at least one code signal generated through an analog-to-digital conversion of a voltage in a voltage controlled oscillator; and a tail current source connected between the plurality of transistors and a second voltage, the tail current source controlling a given current level of at least one signal based at least in part on the given data rate, wherein the given current level is further based at least in part on a control signal and the control signal is received from a variable delay line within a delay locked loop circuit.