Patent ID: 7180498

Claim:
A display device that receives image data and displays the image data on a display block which is a display panel, the display device comprising: an input circuit for receiving image data input thereto; first to N-th (N≧2) storage circuits which are line memories for storing image data input via said input circuit, based on a first clock signal, such that the image data is divided into respective N regions; first to M-th (M≧N) driving circuits which are display drivers for driving respective M regions of at least part of the display block formed by dividing the at least part of the display block; an image data supply circuit for reading out image data stored in each of said first to N-th storage circuits and supplying the image data to a corresponding one of said driving circuits; a clock signal generation circuit for generating a second clock signal; a synchronization reference signal generated by said image data supply circuit based on said second clock signal; and a read enable signal, which is generated by said image data supply circuit based on said synchronization reference signal, for enabling image data to be read out from said first to N-th storage circuits and be supplied to said first to M-th driving circuits, in synchronism therewith, wherein the second clock signal generated by said clock signal generation circuit has a frequency F satisfying: F≧Pn/Tt and Tt<Th, provided that: Cn is the number of the m-th driving circuit which receives image data transferred by a n-th storage circuit (1≦m≦M, 1≦n≦N), nx is a n where Cn is maximum; Pn is the number of pulses required for transfer of image data from the nx-th storage circuit to the corresponding driving circuit; Tt is a time period required for transfer of image data from the nx-th storage circuit to the corresponding driving circuit; and Th is one horizontal time period.