Patent ID: 8648422

Claim:
A semiconductor device comprising: a semiconductor substrate made of first semiconductor having a first lattice constant; an isolation region formed in said semiconductor substrate and defining an active region; a gate electrode structure including an elongating gate electrode formed above and crossing said active region; the active region being defined between first and second borders between the active region and the isolation region, which borders are along elongating direction of the gate electrode structure; the gate electrode structure, defining a first source/drain region adjacent to said first border, and a second source/drain region adjacent to said second border, in said active region; a first subsidiary gate electrode structure including a first subsidiary gate electrode, disposed above a surface of said semiconductor substrate and covering the first border adjacent to the first source/drain region; a recess formed by etching the first source/drain region between said gate electrode structure and said first subsidiary gate electrode structure; and a semiconductor layer epitaxially grown embedding said recess and made of second semiconductor having a second lattice constant different from said first lattice constant.