Patent ID: 8450827

Claim:
An apparatus, comprising: a semiconductor substrate; a rectangular active area defined in a portion of the semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures comprising rectangular shapes disposed in parallel and spaced apart over the doped well region, the gate structures comprising gate conductors lying over gate dielectric material; source and drain regions corresponding to each of the at least two gate structures, forming rectangular shapes parallel to the gate structures and disposed in the well region formed on opposing sides of the gate structures; at least two gate strap conductors disposed over the active area comprising the gate conductor material and arranged in parallel to one another and perpendicular to the at least two gate structures, the at least two gate strap conductors electrically coupling the at least two gate structure conductors to one another; a first interlevel dielectric layer overlying the gate conductors and the gate strap conductors; a gate connector formed in a first metal layer overlying the first interlevel dielectric layer and overlying the at least two gate structures and electrically coupling the at least two gate structures via contact structures formed in the interlevel dielectric layer and extending to the at least two gate structures; source and drain connectors formed in a second metal layer and overlying the source and drain regions in the well region and electrically coupled to the source and drain regions; and a second level of interlevel dielectric material electrically separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer.