Patent ID: 8810297

Claim:
A circuit device comprising: a clock generator configured to output a clock signal having a first frequency; plural phase controllers configured to input the clock signal having the first frequency output by the clock generator, and output respective clock signals having the first frequency and having phases that are advanced or delayed with respect to a phase of the clock signal having the first frequency output by the clock generator; a selector configured to input plural clock signals having the first frequency output from the plural phase controllers, sequentially select pulses of the plural clock signals having the first frequency, and output a clock signal having a second frequency; a pattern generator configured to generate a test pattern based on the clock signal having the second frequency output from the selector; and a circuit configured to input the clock signal having the second frequency output from the selector and the test pattern generated by the pattern generator, operate based on the clock signal having the second frequency, and output operation results of the operations when inputting the test pattern based on the clock signal having the second frequency.