Patent ID: 8196072

Claim:
A method of fabricating a semiconductor device, comprising: providing an integrated circuit layout plan, the integrated circuit layout plan having a plurality of features; sorting the plurality of features into a plurality of first features and a plurality of second features, each of the first features being separated from adjacent first features at respective distances that are less than approximately X, and each of the second features being separated from adjacent second features at respective distances that are greater than approximately X; assigning each of the first features into one of a first subset and a second subset of the first features; assigning each of the second features into one of a first subset and a second subset of the second features; forming a first mask pattern with the first subset of the first features and the first subset of the second features, the first mask pattern having a first global pattern density; and forming a second mask pattern with the second subset of the first features and the second subset of the second features, the second mask pattern having a second global pattern density; wherein the assigning each of the first features is carried out in a manner so that a group of the first features in the first subset interleave with a group of the first features in the second subset, and the assigning each of the first features and the assigning each of the second features are carried out in a manner so that a difference between the first and second global pattern densities is less than a predetermined value.