Patent ID: 7030012

Claim:
A method of forming an integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region including the steps as follows: forming a thick polysilicon layer having a first thickness over both said array region where word lines are located and over said support region where said logic circuits are located; then removing said thick polysilicon layer only from said array region; then depositing a thin polysilicon layer over both said array region and said support region, with said thin polysilicon layer having a second thickness substantially less than said first thickness, and with said thin polysilicon layer being formed on said thick polysilicon layer in said support region; then depositing a metallic conductor coating including at least an elemental metal layer portion over said thin polysilicon layer; and then forming word lines in said array region from said thin polysilicon layer and forming gate electrodes in said support region from said thick polysilicon layer and said thin polysilicon layer above said thick polysilicon layer.