Patent ID: 8288219

Claim:
A method of forming semiconductor transistors, comprising: forming a gate electrode over but insulated from a semiconductor body region for each of first and second transistors; performing a double doped drain (DDD) implant to form DDD source and drain regions in the body region for the first transistor; after forming the DDD source and drain regions, forming off-set spacers along side-walls of the gate electrode of each of the first and second transistors; after forming the off-set spacers, performing a lightly doped drain (LDD) implant to form LDD source and drain regions for the second transistor; after forming the LDD source and drain regions, performing a 1 st source/drain (S/D) implant to form a 1 st source and drain regions within each of the DDD and LDD source and drain regions; and forming main spacers adjacent the off-set spacers of the first and second transistors, wherein the 1 st source and drain regions are of the same conductivity type as the DDD and LDD source and drain regions, and a doping concentration of the 1 st source and drain regions is greater than that of the DDD and LDD source and drain regions.