Patent ID: 7791397

Claim:
A high speed digital level shifter comprising: a first power supply node at a first supply voltage; a second power supply node at a second supply voltage wherein the second supply voltage is higher than the first supply voltage; an input node configured to receive an input signal; an output node; a signal driver coupled to the first power supply node and to the input node wherein the signal driver has a first signal driver output node configured to output a boosted signal corresponding to the input signal and a second signal driver output node configured to output a boosted signal corresponding to an inverted input signal, wherein the signal driver comprises a first charge pump coupled to the first signal driver output node, and a second charge pump coupled to the second signal driver output node; an output circuit coupled to the second power supply node and having a first input coupled to the first signal driver output node and a second input coupled to the second signal driver output node, and having an output coupled to the output node, wherein the output circuit comprises a first nMOS transistor and a second nMOS transistor; and a signal stepper comprising: a first CMOS inverter comprising two transistors with a common gate connection having a first input coupled to the input node and to the common gate connection, and a first output directly connected to a source of the first nMOS transistor; and a second CMOS inverter comprising two transistors with a common gate connection and having a second input coupled to the first output of the first inverter and coupled to the common gate connection, and a second output directly connected to a source of the second nMOS transistor.