Patent ID: 7852673

Claim:
A method for programming a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising: during programming of the enhanced mode memory cell, applying a first voltage on the gate structure to turn on a channel region having the second conductive type in the substrate under the gate structure between the first doped region and the second doped region and applying a first bias between the first doped region and the second doped region to inject a plurality of electrons into the gate structures in a way of channel hot carrier; and during programming of the depletion mode memory cell, applying a second voltage on the gate structure to invert a conductive type of a portion of the first doped region under the gate structure from the second conductive type into the first conductive type and applying a second bias on the first doped region to inject a plurality of holes into the gate structures in a way of band-to-band tunneling hot carrier.