Patent ID: 7446011

Claim:
A process for manufacturing a cell array that includes a plurality of cells, each cell including a selection bipolar transistor and a corresponding storage component, each said bipolar transistor having a first, a second and a control region, and each said storage component having a first and a second terminal, said first region of each bipolar transistor being connected to said first terminal of the corresponding storage component, the process comprising: forming a common region of a first conductivity type in a body of semiconductor material; forming said second regions; forming a plurality of active area regions of a second conductivity type and a first doping level, overlying said common region and forming said control regions; forming a plurality of conduction regions of said first conductivity type in said active area regions and forming said first regions; and forming, in said active area regions, a plurality of control contact regions of said second conductivity type and a second doping level, higher than said first doping level, wherein each active area region is shared by at least two bipolar transistors.