Patent ID: 6906573

Claim:
A semiconductor circuit, comprising: a first output MOS transistor which includes a first terminal connected to a first power source and a second terminal connected to an output terminal to be connected to a load circuit; a second output MOS transistor which includes a third terminal connected to a second power source having a lower voltage than the first power source and a fourth terminal connected to the output terminal; a first functional block circuit which is connected between a control terminal of one of the first output MOS transistor and the second output MOS transistor and the output terminal, wherein the first functional block circuit includes at least one first diode, the first diode being a CB shorted NPN transistor which is formed by shorting a collector and a base of an NPN transistor and using the shorted collector and base as an anode and using an emitter as a cathode, or the first diode being a CB shorted LPNP transistor which is formed by shorting a collector and a base of a lateral PNP transistor and using the shorted collector and base as a cathode and using an emitter as an anode; and a second functional block circuit which is provided in parallel with the first functional block circuit and includes at least one second diode connected in an opposite direction to the first diode of the first functional block circuit, the second diode being a CB shorted NPN transistor or a CB shorted LPNP transistor.