Patent ID: 8164364

Claim:
A differential input circuit comprising: (a) first and second input transistors each having a first electrode, a second electrode, and a control electrode, the control electrode of the first input transistor being coupled to a first input signal, and the control electrode of the second input transistor being coupled to a second input signal, and circuitry for biasing the first and second input transistors; (b) a pass transistor coupled between the first electrode of the first input transistor and the first electrode of the second input transistor, for limiting a voltage difference between the first electrode and the control electrode of the first input transistor when it is turned off in response to a large difference between the first and second input signals, the pass transistor being a FET (field effect transistor); and (c) clamping circuitry coupled to the first and second input signals and also coupled to a control electrode of the pass transistor for controlling the pass transistor, the clamping circuitry including 1) a first level shift transistor having a first electrode, a second electrode, and a control electrode, and a second level shift transistor having a first electrode, a second electrode, and control electrode, the first electrodes of the first and second level shift transistors being coupled to a first supply voltage, the control electrodes of the first and second level shift transistors being coupled to the first and second input signals, respectively, and 2) a voltage selector circuit coupled between the second electrodes of the first and second level shift transistors for selecting a voltage on the second electrode of one of the first and second level shift transistors according to which of the second electrodes of the first and second level shift transistors is at a higher voltage, and producing a corresponding control voltage on the control electrode of the pass transistor.