Patent ID: 7739425

Claim:
A method of communicating between a sending component and a receiving component over a bus, the bus comprising a first channel, which is a single channel, and a second channel, the method comprising: broadcasting from the sending component on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data; storing the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers; retrieving read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers; and broadcasting from the receiving component the retrieved read data on the second channel; wherein the transfer qualifiers comprise a plurality of transfer qualifier groups, each of the transfer qualifier groups comprising one or more of the transfer qualifiers; wherein each of the transfer qualifier groups is broadcast on the first channel concurrently with a different one of the address locations; wherein the receiving component stores a portion of the write data based on the transfer qualifier group and the address location contained in one of the concurrent broadcasts; wherein one of the transfer qualifiers in the transfer qualifier group contained in said one of the concurrent broadcasts comprises a payload size signal indicating the number of bytes contained in the portion of the write data; wherein a second one of the transfer qualifiers in the transfer qualifier group contained in said one of the concurrent broadcasts comprise a burst transmission signal to indicate the number of clock cycles that the sending component will use to broadcast the portion of the write data; and wherein a third one of the transfer qualifiers in the transfer qualifier group contained in said one of the concurrent broadcasts comprise a byte enable signal to indicate the number of bytes of the write data that will be broadcast by the sending component during each of the clock cycles.