Patent ID: 7466592

Claim:
A semiconductor memory device, comprising: a plurality of memory cells aligned in rows and columns; a plurality of word lines arranged corresponding to the memory cell rows, and connected to the memory cells in corresponding rows; a circuit for generating a first voltage at a predetermined voltage level to be transmitted onto a selected word line in said plurality of word lines; a division circuit for generating a plurality of divided voltages by dividing said first voltage; a plurality of reference cells provided corresponding to the divided voltages and selectively rendered conductive in accordance with the respective divided voltages; a reference voltage generation circuit for generating reference voltages in accordance with currents flowing through the respective reference cells; and a sense amplifier circuit for generating a comparison reference current in accordance with a selected reference voltage among the reference voltages generated by said reference voltage generation circuit and comparing the comparison current with a current flowing through a selected memory cell to detect memory cell data in accordance with a result of comparison.