Patent ID: 7910958

Claim:
A semiconductor device, comprising: a substrate having a portion of the substrate formed to include a plurality of diffusion regions, wherein the plurality of diffusion regions include at least one p-type diffusion region and at least one n-type diffusion region; a gate electrode level region formed vertically over the portion of the substrate, the gate electrode level region including a plurality of linear-shaped conductive segments defined to extend lengthwise in a first parallel direction, wherein some of the plurality of linear-shaped conductive segments within the gate electrode level region are defined to include one or more gate electrode portions which extend over one or more of the p-type diffusion regions to form respective PMOS transistor devices, and wherein some of the plurality of linear-shaped conductive segments within the gate electrode level region are defined to include one or more gate electrode portions which extend over one or more of the n-type diffusion regions to form respective NMOS transistor devices, wherein a number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region formed above the portion of the substrate, wherein the plurality of linear-shaped conductive segments include, a first linear conductive segment defined to form both a gate electrode of a first PMOS transistor device and a gate electrode of a first NMOS transistor device, and a second linear conductive segment defined next to, spaced apart from, and parallel to the first linear conductive segment, wherein the second linear conductive segment does not faun a gate electrode of a transistor device.