Patent ID: 8124475

Claim:
A method for fabricating an integrated circuit arrangement with a capacitor, in which the following method steps are performed without any restriction by the order specified: providing a substrate containing an insulating layer made of electrically insulating material and a semiconductor layer, the insulating layer containing an insulating region, patterning the semiconductor layer in order to form at least one electrode region near the insulating region for a capacitor and in order to form at least one active region for a transistor, after the patterning of the semiconductor layer, producing at least one dielectric layer, after the production of the dielectric layer, producing an electrode layer, forming an electrode of the capacitor which is remote from the insulating region in the electrode layer, forming a control electrode of the transistor taking place at the same time as the formation of the electrode region remote from the insulating region, and the at least one electrode region near the insulating region containing a multiplicity of webs.