Patent ID: 7064978

Claim:
A nonvolatile memory cell formed on a substrate comprising: a floating gate placed over a channel region of said memory cell and between a source region and a drain region of said memory cell, said floating gate aligned with an edge of said source region and an edge of said drain region and having a width constrained by a width of said edge of said source and said edge of said drain to prevent said floating gate from having wings overlapping a shallow trench isolation region bounding said nonvolatile memory cell; and a gating transistor having a source connected to the drain region, a drain and a gate connected to a select gate signal to selectively apply a bit line voltage signal to the drain region; wherein said memory cell has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate; wherein said nonvolatile memory cell is in communication with a programming apparatus that places a charge upon said floating gate, said programming apparatus comprising: means for applying a moderately high positive voltage to said control gate, means for applying an intermediate positive voltage to said drain region, means for applying a very large positive voltage to said gate of said gating transistor, and means for applying a ground reference voltage to said source region; wherein the very large positive voltage is from approximately +15V to approximately +22V.