Patent ID: 7494867

Claim:
A manufacturing method for a semiconductor device comprising: forming a lower interconnection on a semiconductor substrate; forming a first interlayer insulation film in which the lower interconnection is buried; forming an MIM capacitive element on the first interlayer insulation film, said MIM capacitive element being formed by layering a lower electrode, a dielectric film, and an upper electrode; forming a second interlayer insulation film in which the MIM capacitive element is buried; forming via holes in the second interlayer insulation film so as to reach the lower electrode; forming a connection plug by filling the via hole with conductive film; and forming an upper interconnection to be connected to the connection plug above the second interlayer insulation film; wherein the forming of the MIM capacitive element includes: forming a first conductor film on the first interlayer insulation film; and forming a lower electrode of the MIM capacitive element by selectively removing the first conductor film and forming first resistive elements and at least one dummy metal film, both the first resistive elements and the at least one dummy metal film being provided at the same level as the lower electrode.