Patent ID: 8765550

Claim:
A method of fabricating a floating-gate n-type MOSFET comprising: forming a first and a second thick oxide region on a p-type substrate; implanting a DNwell (Deep Nwell) region; implanting a Pwell region above the DNwell region and between the first and second thick oxide regions; wherein a first portion of the Pwell region abuts a first portion of DNwell region; implanting a first Nwell region below the first oxide region; wherein a first portion of the first Nwell region abuts a second portion of the DNwell region; wherein a second portion of the first Nwell region abuts a second portion of the Pwell region; implanting a second Nwell region below the second oxide region; wherein a first portion of the second Nwell region abuts a third portion of the DNwell region; wherein a second portion of the second Nwell region abuts a third portion of the Pwell region; growing a gate insulation on the Nwell region; depositing poly-silicon on the gate insulation; etching the poly-silicon to form a poly-silicon gate; forming oxide side-walls on sides of the poly-silicon gate; implanting a first n-type dopant into the Pwell on both sides of the oxide side-walls forming a source and a drain; forming nitride side-walls on the oxide side-walls; implanting a second n-type dopant into the source and the drain; forming a silicide-blocking layer over the poly-silicon gate, the oxide side-walls, the nitride walls, a first portion of the source and a first portion of the drain; forming a silicide on a second portion of the source and on a second portion of the drain; forming a nitride layer over the silicide-blocking layer, the poly-silicon gate, the oxide side-walls, the nitride walls, the first portion of the source and the first portion of the drain; forming a conductive layer over the nitride layer; forming metal contacts on the second portion of the source and on the second portion of the drain.