Patent ID: 8350612

Claim:
A reset circuit, comprising: a power detector module, detecting whether a voltage of a power source being lower than a threshold voltage, and correspondingly outputting a first reset signal; and a pulse-width determination module, coupled to the power detector module, determining whether a pulse-width of the first reset signal being long enough, and correspondingly outputting a second reset signal to reset a system, the pulse-width determination module comprising: a delay circuit delaying the first reset signal for the threshold time to output a delayed reset signal, the delay circuit comprising: a first resistor module, providing a first resistance, wherein a first terminal of the first resistor module is coupled to a first voltage, the first resistor module comprising: a first bias circuit, providing a first bias voltage; and a first transistor module, having a control terminal receiving the first bias voltage, a first terminal coupled to the first voltage, and a second terminal coupled to the second terminal of the switch module; a second resistor module, providing a second resistance, wherein a first terminal of the second resistor module is coupled to a second voltage, the second resistor module comprising: a second bias circuit, providing a second bias voltage; a switch module, having a control terminal coupled to the power detector module, a first terminal coupled to the logic circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module, wherein the first terminal selectively connected to the second terminal or the third terminal thereof in accordance with the control terminal thereof; and a capacitor module, coupled between the first terminal of the switch module and the second voltage, wherein the first bias circuit comprises a NOT gate having an input terminal coupled to the first terminal of the switch module, and an output terminal providing the first bias voltage to the control terminal of the first transistor module; and a logic circuit, coupled to the delay circuit and the power detector module, and processing a logical AND operation with the first reset signal and the delayed reset signal for outputting the second reset signal.