Patent ID: 7870429

Claim:
A control apparatus comprising: an operator including a pair of processor cores connected to a boundary scan bus, and adapted to mutually diagnose opponent processor cores in between; a memory configured to store therein data and programs to be executed by the operator; an I/O interface configured for input and output signals to be processed for associated processes in the operator; and a normal bus configured for normal connections among the operator, the memory, and the I/O interface, wherein the operator comprises a first generalized processor core and a second generalized processor core each respectively connected to the boundary scan bus, the memory has a set of a first boundary scan control program and a second boundary scan control program for the operator to perform boundary scan tests, a first expected value data and a second expected value data each respectively to determine a conformity of a result of an associated boundary scan test, and a control program for the operator to perform a control, the first generalized processor core comprises a first boundary scan tester, a first intra-processor circuit to be tested by the first boundary scan tester, and a control pattern setter configured for selection of the control program or the set of the first and second boundary scan control programs, whichever is to be executed by the operator, to have a control pattern of the control apparatus preset to the first intra-processor circuit, the second generalized processor core comprises a second boundary scan tester, and a second intra-processor circuit to be tested by the second boundary scan tester, and the control pattern is followed for a time-dividing implementation of and between a boundary scan test to be performed to the second generalized processor core, through the boundary scan bus, by and from the first intra-processor circuit having the first boundary scan control program sampled therefor, and a boundary scan test to be performed to the first generalized processor core, through the boundary scan bus, by and from the second intra-processor circuit having the second boundary scan control program sampled therefor, depending on a diagnosis request command received from the first intra-processor circuit, through the normal bus, in accordance with a setting of the control pattern.