Patent ID: 7500167

Claim:
A decoder comprising: an input buffer configured to receive a first input signal; a decoding device for decoding the first input signal using an iterative process, the iterative process includes a plurality of iterations, the decoding device includes a fetch component obtaining the first input signal from the input buffer, the fetch component configured to provide the first input signal to the decoding core and the data error calculator at the same time, a decoder core receiving the first input signal from the fetch component and decoding the first input signal, the decoding core configured to determine that the iterative process is complete based on an nth iteration and wherein a last two consecutive iterations of the plurality of iterations have the same result, and an output buffer for receiving the decoded first input signal; and a re-encoder configured to re-code the decoded first input signal received from the output buffer; a data error calculator configured to receive the first input signal and the re-encoded first input signal and calculate a transport channel bit error rate (BER) of the first input signal during the decoding of the first input signal by the core decoder, wherein the data error calculator calculates the BER based on an nth−1 iteration, such that the calculation of the BER is simultaneous with the decoding of the first input signal.