Patent ID: 7448031

Claim:
A method of compiling a software program comprising: identifying a first set of load instructions in the software program to be compiled having an expected latency greater than or equal to a predetermined threshold associated with a first cache; requesting that the first set of load instructions be scheduled to have a first predetermined latency; scheduling the software program; comparing actual latencies of the first set of load instructions in the scheduled software program to the first predetermined latency; if the actual latency associated with a load instruction in the first set of load instructions is less than the first predetermined latency, marking the load instruction to access the first cache; creating a second set of load instructions, the second set of load instructions excluding the load instructions that are marked to access the first cache; identifying from the second set of load instructions, a third set of load instructions having an expected latency greater than or equal to a second predetermined threshold associated with a second cache; requesting that the third set of load instructions be scheduled to have a second predetermined latency; scheduling the software program; comparing actual latencies of the third set of load instructions in the scheduled software program to the second predetermined latency; if the actual latency associated with a load instruction in the third set of load instructions is less than the second predetermined latency, marking the load instruction to access the second cache; and completing compilation of the software program and outputting executable code for the software program with the marked load instruction.