Patent ID: 7518937

Claim:
A parallel bit test circuit for a semiconductor memory device having a memory cell array in which a plurality of memory cells connected to a plurality of data lines are arrayed in a matrix, the circuit comprising: a plurality of data compressors configured to receive data output from the data lines, compress the data, and output the compressed data, each of the plurality of data compressors being coupled with a given number of data lines; a delay unit configured to receive a clock signal and, when a burst length is a natural number equal to or more than 2, generate (N−1) number of delayed clock signals from the clock signal; and a bus width converter configured to receive the compressed data through M number of input terminals, divide the compressed data into N number of data sets, and sequentially and serially output the N number of data sets through M/N number of output terminals in response to the clock signal and the (N−1) number of delayed clock signals, M being the number of bits of the data output from the data lines.