Patent ID: 6847239

Claim:
A frequency divider for reducing the frequency of a clock signal by an odd numbered factor n, where n is an integer value, comprising: a clock generator circuit for receiving the clock signal and for providing an n-divided clock signal having a first and second logic level, the clock generator circuit driving the n-divided clock signal from the first logic level to the second logic level in response to a reset signal; and, a clock delay circuit for activating the reset signal at n clock transitions after receiving the first logic level of the n-divided clock signal, and for deactivating the reset signal within n clock transitions after receiving the second logic level of the divided clock signal, the clock generator circuit driving the n-divided clock signal from the second logic level to the first logic level at n clock transitions after activation of the reset signal wherein the clock generator circuit includes a first resettable flip-flop having a data input connected to a supply voltage and the clock delay circuit includes a reset input for receiving the reset signal and a second resettable flip-flop having a data input for receiving the divided clock signal and a reset input for receiving the reset signal, the second resettable flip-flop providing a delayed n-divided clock signal, and at least one pair of serially connected non-resettable flip-flops receiving the delayed n-divided clock signal from the second resettable flip-flop for activating and deactivating the reset signal.