Patent ID: 8901957

Claim:
A processor comprising: a programmable logic circuit that includes a plurality of processing units and is configured to selectively use the processing units to reconfigure a logic circuit, wherein the programmable logic circuit is capable of performing a first process, followed by a second process which relates to the first process, and wherein the programmable logic circuit is capable of reconfiguring a first logic circuit, which corresponds to first circuit configuration information according to the first process, and a second logic circuit, which corresponds to second circuit configuration information according to the second process, each of the first and second logic circuits including an information holding unit; a first control circuit that is configured to generate an execution control signal for executing the first process, the first control circuit is configured to store the second circuit configuration information in the information holding unit of the first logic circuit; and a second control circuit that is configured to obtain the second circuit configuration information from the information holding unit of the first logic circuit in response to completion of the first process and control the programmable logic circuit so as to reconfigure the second logic circuit corresponding to the second circuit configuration information.