Patent ID: 8760593

Claim:
A thin film transistor disposed on a substrate, comprising: a gate electrode disposed on the substrate; a gate dielectric layer covering the gate electrode and the substrate; a patterned semiconductor layer disposed on the gate dielectric layer over the gate electrode, having a channel region disposed over the gate electrode and source/drain regions disposed at both sides of the channel region; source/drain electrodes disposed on the source/drain regions of the patterned semiconductor layer, the source/drain electrodes comprising a stack of a patterned barrier layer and a patterned metal conductive layer, the patterned barrier layer being disposed on the source/drain regions of the patterned semiconductor layer, the patterned metal conductive layer being disposed on the patterned barrier layer and in contact with the patterned barrier layer; a passivation layer made of a material consisting essentially of a metal nitride, the passivation layer covering a top surface of the patterned metal conductive layer, wherein the passivation layer has a thickness of 5-200 angstrom; and a protection layer covering the passivation layer, the channel region of the semiconductor layer, and the substrate.