Patent ID: 7879668

Claim:
A method of manufacturing a semiconductor device, comprising: forming a first gate electrode in a first area of a substrate; forming a second gate electrode in a second area of the substrate; forming non-crystalline regions in the first area of the substrate adjacent to the first gate electrode; forming first source/drain regions including N-typed impurities in the first area of the substrate adjacent to the first gate electrode; forming a layer composed of one of a nitride or an oxynitride and having a first stress which is a tensile stress on the substrate to cover the first gate electrode, the first source/drain regions, and the non-crystalline regions located in the first area of the substrate and to cover the second gate electrode located in the second area of the substrate; forming a mask on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area of the substrate; etching the second portion of the layer to form a sacrificial spacer on a sidewall of the second gate electrode; partially etching the second area of the substrate using the mask, the second gate electrode and the sacrificial spacer to form recesses in the second area of the substrate adjacent to the second gate electrode and wherein the recesses formed in the second area of the substrate are exposed by the first portion of the layer located in the first area of the substrate; forming patterns having a second stress which is a compressive stress in the recesses, wherein the patterns formed in the recesses are exposed by the first portion of the layer located in the first area of the substrate; and forming second source/drain regions including P-typed impurities in the patterns adjacent to the second gate electrode after forming the patterns in the recesses, wherein the second source/drain regions formed in the patterns are exposed by the first portion of the layer located in the first area of the substrate.