Patent ID: 7788554

Claim:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a static random access memory (SRAM) cell write performance evaluation circuit including a SRAM core, said SRAM core including a plurality of wordlines, each wordline being connected to connected to one SRAM cell from only one bit column; a ring oscillator circuit coupled to said SRAM core selectively generating wordline pulses; an input logic coupled to said SRAM core applying data to the SRAM core, an output logic coupled to said SRAM core and ring oscillator circuit selectively providing an output oscillator signal to identify a minimum wordline pulse width to write said SRAM cell; and a state machine coupled to said ring oscillator circuit and said input logic, said state machine controlling said ring oscillator circuit to enable incrementally varying a wordline pulse width and said state machine controlling write and read operations to said SRAM core for implementing SRAM cell write performance evaluation.