Patent ID: 8400382

Claim:
A digital-to-analog converter circuit configured to convert an m-bit digital signal into an analog signal, the circuit comprising: a circuit configured to segment the m-bit digital signal into n-bit (n≦m/2) units from a least significant bit to a most significant bit; an n number of bit voltage generators, each bit voltage generator configured to convert a bit of the segmented n-bit units of the m-bit digital signal into a first voltage or a second voltage, wherein n>1, each bit voltage generator including a pair of switches which selectively apply the first and second voltages; an n number of first capacitors respectively associated with the n-bit units, each capacitor configured to store a respective first voltage for a respective bit output from the respective bit voltage generator when one of the switches of the pair of switches is selectively applied, and configured to store a respective second voltage for a respective bit output from the respective bit voltage generator when the other switch of the pair of switches is selectively applied, each of the first capacitors having a first end electrically connected to the pair of switches of the respective bit voltage generator; an n number of first switches whose first ends are respectively electrically connected to the n number of first capacitors; an n number of second switches, each second switch having one end that is electrically connected to the first end of a respective first capacitor and the first end of a respective first switch, and having another end that is grounded; a second capacitor electrically connected to second ends of the n number of first switches; an output unit configured to output a voltage stored in the second capacitor as an analog signal; and a control unit configured to (a) control the n number of first switches, (b) control the n number of second switches, (c) connect in parallel the n number of first capacitors with the second capacitor, and (d) adjust the voltage stored in the second capacitor, wherein, a capacitance value of the first capacitor corresponding to a qth bit of each unit (where q is an integer equal to 1 or greater but not greater than n) is set to a value obtained by multiplying the capacitance of the first capacitor corresponding to the least significant bit with 2 q-1 .