Patent ID: 7091544

Claim:
A dynamic random access memory (DRAM) structure, comprising: a plurality of active areas in a substrate and disposed into a horizontal array, wherein each of the active areas is structurally independent; a plurality of deep trenches (DT), wherein each of the DT is located in the substrate of the corresponding active area and the DT form a checkerboard-like arrangement with adjacent DT in the same row being kept at a fixed distance; a plurality of long bit line contact plugs above the active areas and in contact with the active areas; wherein each of the long bit line contact plugs is connected to two of the diagonally neighbor active areas; a plurality of word lines above the active areas, wherein the word lines form a vertical array and each of the active areas crosses each two of the word lines; a plurality of bit lines passing above and in contact with the long bit line contact plugs; wherein the bit lines and the word lines form a crossing array; an insulating layer on the long bit line contact plugs; and a plurality of contact holes in the insulating layer and on each of the long bit line contact plugs to expose the long bit line contact plugs for electrical communications with part of the bit lines; wherein the size of the contact holes is smaller than that of the long bit line contact plugs and the contact holes do not overlap with the active areas.