Patent ID: 7023061

Claim:
A semiconductor device comprising: a plurality of memory transistors arranged in an array; a plurality of word lines serving also as gate electrodes of memory transistors in a same row, arranged extending in a row direction, and repeating at distances in a column direction; an insulating film being formed between the word lines so that the word lines are insulated and isolated from each other, a dimension of the distance between word lines being defined by a thickness of said insulating film; a first charge storage film comprising a plurality of films and having a charge storage capability formed on a semiconductor; a plurality of first word lines formed on said first charge storage film and formed in parallel with each other at predetermined distances; a second charge storage film covering surfaces of said first word lines and surfaces of said semiconductor exposed between the first word lines, comprising a plurality of films, and having a charge storage capability; and a plurality of second word lines facing the surfaces of said semiconductor exposed between said first word lines across said second charge storage film and insulated and isolated from said first word lines by an insulating film interposed so that distances from said first word lines, including the thickness of said second charge storage film, becomes the film thickness, wherein said first word lines and said second word lines extend outward from a memory cell array region and then are bent in a direction different from a direction of arrangement of said word lines and wherein a pitch of arrangement between said first word lines and said second word lines at front end sides from said bent portions is set larger than a pitch of arrangement between said first word lines and said second word lines in said memory cell array, and wherein at least one of two ends of each second word line in a width direction overlaps an end of a first word line in the width direction where said insulating film interposed.