Patent ID: 8243531

Claim:
A reference potential generating circuit of a semiconductor memory, comprising: a first MOS transistor group that includes a plurality of first MOS transistors, which are used for supply of current to an internal circuit of the semiconductor memory and are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group and is used for temperature compensation; a third MOS transistor that is connected to a circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential output from a predetermined connection point of the plurality of first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to permit the supply of current to the internal circuit of the semiconductor memory is input.