Patent ID: 8767442

Claim:
A semiconductor device comprising: a memory cell array comprising a memory cell; a first driver circuit; and a second driver circuit, wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, wherein the first channel formation region comprises a first semiconductor material, wherein the second channel formation region comprises a second semiconductor material, wherein the first gate electrode, the second drain electrode, and one electrode of the first capacitor are electrically connected to each other, wherein the first driver circuit is electrically connected to the first drain electrode and the second source electrode, wherein the second driver circuit is electrically connected to the other electrode of the first capacitor and the second gate electrode, wherein a second capacitor is provided between the second driver circuit and the memory cell and one electrode of the second capacitor is electrically connected to the second gate electrode, wherein the second capacitor comprises a first conductive layer, an insulating layer over the first conductive layer, a second conductive layer over the insulating layer, a third conductive layer in contact with the second conductive layer, and a fourth conductive layer in contact with the third conductive layer, wherein the first conductive layer comprises the first semiconductor material, wherein the insulating layer is provided in the same layer as a gate insulating layer of the first transistor, wherein the second conductive layer is provided in the same layer as the first gate electrode, wherein the third conductive layer is provided in the same layer as the second source electrode and the second drain electrode, and wherein the fourth conductive layer is provided in the same layer as the second gate electrode.