Patent ID: 7422949

Claim:
A method of manufacturing a high voltage transistor, the method comprising: forming a mask pattern covering a first region on a first conductive semiconductor substrate; forming a gate insulating film on a surface of the semiconductor substrate exposed through the mask pattern; forming a gate electrode asymmetrically extending from an upper surface of the gate insulating film to an upper surface of the mask pattern; removing the mask pattern to expose the first region; implanting a low concentration impurity having a second conductivity opposite to the first conductivity on the resultant semiconductor substrate such that a low concentration source region and a low concentration drain region are formed at both sides of the gate electrode; forming each of asymmetric-structured first insulating spacer and second insulating spacer on both sidewalls of the gate electrode; implanting with a high concentration impurity using the gate electrode, the first insulating spacer and the second insulating spacer as an implant mask to form a high concentration source region and a high concentration drain region; and forming a metal silicide layer on the high concentration source region and the high concentration drain region.