Patent ID: 6981100

Claim:
A memory device supporting a plurality of possible prefetch modes, including at least a maximum prefetch mode and a minimum prefetch mode, comprising: a memory array; a read circuit comprising a read latch and coupled to the memory array for transferring a first plurality of words corresponding to said maximum prefetch mode from said memory array to said read latch, and for transferring a second plurality of words from said read latch to an external device, wherein said second plurality is a controllable parameter of said read circuit and is equal to or less than said first plurality; a programmable element for storing a current prefetch mode chosen from a plurality of possible prefetch modes; and a control circuit coupled to said read circuit; wherein said control circuit, in response to a read command, detects the current prefetch mode stored in said programmable element, and operates said read circuit by setting said second plurality to correspond to the current prefetch mode.