Patent ID: 7761066

Claim:
A circuit comprising: an analog output module that receives a bias signal and a control signal; a delay module that receives a first signal and that generates a delayed first signal; a control module that receives said delayed first signal and that generates said control signal based thereon; and an envelope generating module that receives a second signal including amplitude information related to said first signal, wherein said envelope generating module generates an envelope signal to selectively increase said bias signal to said analog output module when said first signal exceeds a voltage supply reference and before a corresponding portion of said first signal is received by said analog output module, wherein said envelope generating module selectively increases voltage of said bias signal to a voltage level that is greater than or equal to a voltage level of said envelope signal when said envelope signal exceeds said voltage supply reference, and wherein said control module comprises: a switch that is connected to said analog output module and that receives said voltage supply reference; and a capacitance that is connected between a first digital to analog converter and said switch.