Patent ID: 7890820

Claim:
A semiconductor test system with self-inspection of memory repair analysis, comprising: a memory repair analysis device, for executing a particular repair analysis operation to produce repair line address information; an analysis fail memory, including a fail address memory for storing fail bit address information, and a repair address memory; and a self-inspection controller, respectively electrically connected to the memory repair analysis device and the analysis fail memory, wherein the self-inspection controller controls storing a set of simulated fail bit addresses into the fail address memory, controls storing a set of simulated repair line addresses into the repair address memory, in which a simulated repair line address refers to a particular correct one correspondingly generated after the memory repair analysis device executes the above-said particular repair analysis operation with respect to the set of simulated fail bit addresses, further controls the memory repair analysis device to execute the above-said particular repair analysis operation with respect to the set of simulated fail bit addresses in the fail address memory and to produce the repair line address information, and compares the repair line address information with the set of simulated repair line addresses in the repair address memory.