Patent ID: 6900101

Claim:
A method of fabricating an extended drain MOS transistor, comprising: forming a first well of a first conductivity type in a substrate; forming a second well of a second conductivity type in the substrate, the first and second conductivity types being opposite; forming a drain of the first conductivity type in a portion of the first well; forming a source of the first conductivity type in a portion of the second well; forming a thick dielectric extending laterally from a first end adjacent the drain to a second opposite end in the first well, the thick dielectric extending into the first well of the substrate, wherein the first well has a concentration of dopants of the first conductivity type less than or equal to a first concentration value proximate the second end of the thick dielectric; forming a thin dielectric over the substrate, the thin dielectric extending from the second end of the thick dielectric in the first well to the source in the second well; forming a conductive gate contact structure extending over the thin dielectric and over a portion of the thick dielectric; and implanting additional dopants of the first conductivity type at a second concentration value in an adjust region of the substrate proximate the second end of the thick dielectric, the second concentration value being greater than the first concentration value; wherein the transistor is fabricated in a wafer, wherein forming the thick dielectric comprises: forming a trench extending into the substrate in the first well; depositing dielectric material into the trench and over the wafer; planarizing the wafer; and wherein the additional dopants of the first conductivity type are provided in the adjust region after forming the trench and prior to depositing dielectric material into the trench.