Patent ID: 7519649

Claim:
A system for performing decimal division, the system comprising: input registers for storing a scaled divisor and a scaled dividend; a plurality of multiples registers for storing a subset of multiples of the scaled divisor; and a pipeline mechanism including a two cycle adder, a latching multiplexer connected to the multiples registers and the two cycle adder, a remainder register connected to the two cycle adder, remainder selection circuitry connected to the remainder register, quotient selection circuitry connected to the multiplexer, the remainder selection circuitry and the remainder register, and a quotient accumulator connected to the two cycle adder, the pipeline mechanism calculating quotient digits in response to the scaled divisor and the scaled dividend, wherein each quotient digit is calculated in three clock cycles and the calculating includes: selecting a new quotient digit; and calculating a new remainder using the two cycle adder, wherein input to the two cycle adder includes data from one or more of the multiples registers.