Patent ID: 7237099

Claim:
A multiprocessor system comprising: a plurality of CPUs (central processing units); respective local buses, each connected to a corresponding one of said CPUs; a memory having stored therein a plurality of control programs which are respectively executed by said CPUs; a common bus which is connected to said memory and can be accessed via said local buses; and a plurality of data registers constituting identification registers, each connected to only a corresponding one of said CPUs via a respective one of the local buses of the corresponding one of said CPUs; wherein each of said identification registers has an identification value permanently stored therein, the identification value being unique to said each identification register, and wherein each of said identification registers is adapted to respond to a readout address supplied from the corresponding one of said CPUs by reading out and supplying to said corresponding CPU said stored identification value, wherein each of said CPUs is adapted to respond to input thereto of an interrupt signal relating to a specific interrupt condition by generating information indicative of an interrupt vector predetermined as corresponding to said interrupt condition, said interrupt condition being a condition for which a plurality of said CPUs must execute respectively different interrupt handling processing; said memory has stored therein an interrupt handler program whose position within said memory is specified by said interrupt vector; said interrupt handler program includes a plurality of respectively different CPU-linked interrupt handler routines which respectively correspond to said CPUs; and said interrupt handler program includes instructions for causing a CPU which executes said interrupt handler program to successively generate said readout address and thereby obtain the identification value corresponding to said CPU, judge said value, and perform execution branching, in accordance with a result off said judgement, to the one of said CPU-linked interrupt handler routines which corresponds to said CPU.