Patent ID: 8637384

Claim:
A method to fabricate a transistor, comprising: forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of said at least one electrically conductive channel, said gate structure having a width and a length and a height defining two opposing sidewalls of said gate structure and being formed such that said at least one electrically conductive channel said passes through said sidewalls of said gate structure; forming spacers on said sidewalls of said gate structure; forming a layer of epitaxial silicon over said at least one electrically conductive channel where said at least one electrically conductive channel is not covered by said spacers; siliciding the layer of epitaxial silicon to form a layer of silicide: removing said spacers; and forming a dielectric layer to be disposed over said gate structure and portions of said electrically conductive channel that are external to said gate structure such that an air gap underlies said dielectric layer, said air gap being disposed adjacent to said sidewalls of said gate structure in a region formerly occupied by said spacers, said air gap being disposed between said sidewalls of said gate structure and opposing sidewall surfaces of said layer of silicide that is disposed upon said at least one electrically conductive channel external to said gate structure.