Patent ID: 7368961

Claim:
A clock distribution network comprising: a. a synchronization circuit having: i. a reference clock node to receive a reference clock signal; ii. a local-clock node to provide a local clock signal; iii. a first phase detector having a first phase-detector node, coupled to the reference clock node, and a second phase-detector node; and iv. a first feedback path extending between the local-clock node and the second phase-detector node; v. wherein the synchronization circuit maintains a first fixed phase relationship between the reference clock signal and the local clock signal; b. a clock switch having a switch input node coupled to the local-clock node, a switch output node, and a select node, the clock switch to selectively couple the switch input node to the switch output node; c. a clock network having a root node coupled to the switch output node and a plurality of clock branches extending from the root node to a plurality of clock-destination nodes, wherein the clock network conveys the switched, local clock signal from the clock switch to the plurality of destination nodes as a plurality of distributed clock signals; d. a second phase detector having third and fourth phase-detector input nodes; and e. a second feedback path extending from at least one of the destination nodes to the third phase-detector input node.