Patent ID: 7791428

Claim:
A loop gain calibration method for an all-digital phase-locked loop (ADPLL), comprising: modulating a gain of a sigma delta modulator compensation module (SDMCM) amplifier of a SDM compensation module according to a code variance corresponding to a half of a reference period of a reference signal received by a TDC module of the ADPLL, a reference frequency of the reference signal received by the TDC module, a frequency response of a DCO of a DCO/SDM module of the ADPLL or a combination thereof; and modulating a gain of a modulator (MOD) amplifier of a modulator according to a frequency variance in an input terminal of a Sigma Delta Modulator (SDM) of a feedback path module of the ADPLL, a code variance corresponding to the frequency variance, a fractional code variance, the reference frequency of the reference signal received by the TDC module or a combination thereof.