Patent ID: 7774530

Claim:
A digital signal processing system, comprising: a plurality of digital signal processors (DSP's) in a power line carrier system transceiver, the DSP's configured to receive a three phase waveform in a power distribution system, the DSP's further configured to extract digital data embedded in the three phase wave form with a frequency-shift keying modulation scheme, the digital data received from a usage metering device in a customer endpoint, the usage metering device configured to transmit electricity usage data in a customer endpoint, wherein at least one of the DSP's having an external memory, the DSP's further configurable to substantially simultaneously act as a master processor and as a slave processor relative to another DSP of the plurality, each of the DSP's further having a slave port and a master port, the slave port configured to transmit data from the external memory of a slave processor and the master port configured to access data on behalf of a master processor; an arbiter, the arbiter including a field programmable gate array; a bus coupled to at least one of the DSP's and the arbiter; wherein a first DSP configured as a master processor has exclusive access to the external memory of another DSP of the plurality; and a single board computer configured to receive the extracted electricity metering data from the plurality of DSP's, the single board computer and communicate the electricity metering data to a central billing system; wherein the arbiter is configured to maintain DSP status data, the DSP status data reflecting which of the DSP's is configured as a slave processor and the identity of the master processor configured to access the external memory of slave processor DSP's, the DSP status data further includes a slave busy flag corresponding to each of the plurality of DSP's, the slave busy flag set by a DSP claimed as a slave processor by another DSP of the plurality, the DSP status data further including a master processor identifier corresponding to each of the plurality of DSP's, the master processor identifier of a first DSP set by the arbiter to reflect the identity of a DSP of the plurality claiming the first DSP as a slave processor; requests to access the external memory of the slave processor DSP's and data from the external memory of slave processor DSP's are communicated along the bus; responsive to a first request from the first DSP to claim the second DSP as a slave processor, the arbiter is configured to deny the first request if the second DSP is claimed as a slave processor by a third DSP; and the master processor has exclusive access to the external memory of the slave processor relative to other DSP's of the plurality.