Patent ID: 8349630

Claim:
A method for manufacturing a thin film transistor array substrate, comprising the following steps: forming a plurality of gate electrodes on a transparent substrate; forming a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a photo-resist layer on the transparent substrate and the gate electrodes in sequence; using a multi tone mask to pattern the photo-resist layer, so as to allow the photo-resist layer to have different thicknesses and channels, wherein the channels are formed above the gate electrodes; using the patterned photo-resist layer to act as a mask and performing a wet etching and a dry etching to etch the semiconductor layer, the ohmic contact layer and the electrode layer, so as to remove a portion of the semiconductor layer, a portion of the ohmic contact layer and a portion of the electrode layer, and to form a plurality of source electrodes and a plurality of drain electrodes at both sides of the channels, respectively; heating the photo-resist layer, so as to allow a portion of the photo-resist layer to reflow into the channels and to shelter the channels; using the photo-resist layer to act as another mask after reflowing, and performing another dry etching for the semiconductor layer, so as to remove a portion of the semiconductor layer; removing the photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer, wherein the pixel electrode layer is electrically connected to the drain electrodes.