Patent ID: 7760726

Claim:
A two-chip/single-die packet switch operating in an internal memory mode in storing packet data of a received packet in an internal memory store, and operating in an external memory mode in storing the packet data in an external memory storage connected to the packet switch, the packet switch comprising: a. a packet reception block including only internal memory mode logic for storing received the packet data in the internal memory store and for issuing a packet processing job request in respect of the packet stored in the internal memory store; b. a packet processing block including only internal memory mode logic for performing operations on packet header information and for issuing a packet transmission job request in respect of the processed packet; c. an external memory storage interface including only external memory mode logic, the external memory storage interface being in communication with the external memory storage; d. an external memory storage manager block including only external memory mode logic for tracking external memory storage occupancy; and e. a packet data transfer engine including both internal and external memory mode logic for conveying the packet data between the internal memory store and the external memory storage interface responsive to the transmission job request.