Patent ID: 6915504

Claim:
An arithmetic device allocation design method for allocating arithmetic operations in a data flow graph, which includes a branch and a node respectively representing a flow of data and an arithmetic operation, to an arithmetic device based on a scheduling result when performing high-level synthesis for synthesizing a circuit from behavioral descriptions which do not include information about hardware structures and only include a processing algorithm, the method comprising the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased circuit area due to a selector to be provided so as to allocate the arithmetic operation A to an arithmetic device C to which another arithmetic operation B has already been allocated and an increased area due to an arithmetic device D to be created anew to which only the arithmetic operation A is allocated; based on said comparing step, when the increased circuit area due to the selector is smaller than the increased area due to the arithmetic device D, allocating the arithmetic operation A to the arithmetic device C to which the another arithmetic operation B has already been allocated while providing the selector; and based on said comparing step, when the increased circuit area due to the arithmetic device D is smaller than the increased area due to said selector, creating the arithmetic device D anew so as to allocate the arithmetic operation A to the arithmetic device D created anew.