Patent ID: 8572546

Claim:
A method of modeling a transistor, the method comprising performing, by an apparatus including a memory unit, the steps of: extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage; fitting a mobility function including model parameters on the reference mobility values to extract the model parameters; and putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region; wherein the mobility function is expressed by the following equation, μ = ( 1 K b ⁡ ( V gate - V on ) β + 1 K a ⁡ ( V gate - V on ) α ) - 1 wherein, “Ka”, “Kb”, “α” and “β” denote the model parameters, “Vgate” denotes the reference gate voltage applied to the gate electrode, “Von” denotes a turn on voltage of the transistor, and “μ” denotes a mobility of the channel layer calculated using the model parameters, the reference gate voltage and the turn on voltage.