Patent ID: 7470955

Claim:
An integrated circuit having negative potential protection, comprising: a first double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, wherein the first-type epitaxial pocket is formed in a second-type substrate; a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket; one of a first-type+ ring or an isolation trench formed through the first-type epitaxial pocket between the second-type+ isolation ring and the first DMOS cell; a second DMOS cell formed in the first-type epitaxial pocket, wherein the first and second DMOS cells have a common drain and a source of the second DMOS cell is coupled to one of the isolation ring and the substrate; and a comparator including an output, a first input and a second input, wherein an output of the comparator is coupled to a gate of the second DMOS cell, and wherein the first input of the comparator receives a reference signal and the second input of the comparator is coupled to the common drain, where the comparator provides a turn-on signal to the gate of the second DMOS cell when a signal at the second input is below the reference signal, and where the turn-on signal causes the second DMOS cell to conduct shorting a base-emitter junction of a parasitic NPN transistor.