Patent ID: 8305116

Claim:
An injection-locked frequency dividing apparatus, comprising: a frequency multiplier, for receiving a frequency signal and generating a multiple-frequency signal according to the frequency signal; a first linear mixer and a second linear mixer, both coupled to the frequency multiplier for receiving the multiple-frequency signal, the first and the second linear mixer respectively receives a first input signal and a second input signal and mixes the multiple-frequency signal with the first input signal and the second input signal to generate a first mixed signal and a second mixed signal respectively, wherein a phase of the first input signal is complementary to a phase of the second input signal, wherein the first linear mixer comprises: a first mixing transistor, having a gate for receiving the first input signal, a first source/drain coupled to a supply voltage, and a second source/drain coupled to the frequency multiplier for receiving the multiple-frequency signal and mixing the multiple-frequency signal with the first input signal to generate the first mixed signal at the second source/drain of the first mixing transistor; the second linear mixer comprises: a second mixing transistor, having a gate for receiving the second input signal, a first source/drain coupled to the supply voltage, and a second source/drain coupled to the frequency multiplier for receiving the multiple-frequency signal and mixing the multiple-frequency signal with the second input signal to generate the second mixed signal at the second source/drain of the second mixing transistor; an oscillator, coupled to the first linear mixer, the second linear mixer, and the frequency multiplier, for generating the frequency signal, and the oscillator further receives the first mixed signal and the second mixed signal for generating a first output signal and a second output signal according to the first mixed signal and the second mixed signal, wherein a phase of the first output signal is complementary to a phase of the second output signal; a first output buffer, coupled to the oscillator for receiving the first output signal; and a second output buffer, coupled to the oscillator for receiving the second output signal, wherein the first output buffer and the second output buffer respectively generate a first buffered output signal and a second buffered output signal according to the first output signal and the second output signal.