Patent ID: 8198662

Claim:
A semiconductor memory device including a memory element including a MOSFET and a MOS capacitor comprising: a semiconductor substrate including a support substrate, an insulating layer formed over the support substrate, and a semiconductor layer formed over the insulating layer; an element isolation layer between the transistor forming region and the capacitor forming region; a projection provided within a periphery of the capacitor forming region of the semiconductor layer; a capacitor groove provided in the insulating layer; a gate insulating film over the semiconductor layer, over the element isolation layer, and within the capacitor groove; a floating gate electrode over the gate insulating film, the floating gate electrode dividing the semiconductor layer at an end portion of the transistor forming region, overlapping a doped region of the MOSFET, and overlapping the projection of the semiconductor layer of the capacitor forming region; a source and a drain of the MOSFET; and a capacitor electrode of the MOS capacitor; wherein the capacitor groove includes an undercut portion below the projection.