Patent ID: 7595222

Claim:
A method for manufacturing a semiconductor device including a first semiconductor chip having first electrodes on a fringe region of a main surface thereof, and a second semiconductor chip smaller in area than the first semiconductor chip and having second electrodes on a main surface thereof, comprising: a first step of preparing a first semiconductor wafer having a plurality of first semiconductor chips; a second step of preparing a second semiconductor wafer having a plurality of second semiconductor chips; a third step of cutting the second semiconductor wafer into the second semiconductor chips with a dicing blade while tapering ends of each second semiconductor chip in a forward direction; a fourth step of connecting the first semiconductor wafer and the second semiconductor chips together by bonding a surface of each second semiconductor chip that is opposite to the main surface thereof to a region of the main surface of a corresponding first semiconductor chip of the first semiconductor wafer other than the fringe region; a fifth step of forming a conductive film on the resultant first semiconductor wafer and patterning the conductive film to form wirings for connecting the first electrodes of each first scmiconductor chip to the second electrodes of a corresponding second semiconductor chip; and a sixth step of cutting the resultant first semiconductor wafer into the first semiconductor chips as stacked-chip elements each having the first and second semiconductor chips stacked on each other.