Patent ID: 8022306

Claim:
A printed circuit board on which an electronic component is to be mounted, comprising: a base insulating layer; a conductor trace that is formed on one surface of said base insulating layer and has a terminal to be electrically connected to said electronic component; a cover insulating layer that has an opening causing said terminal of said conductor trace to be exposed and is formed on the one surface of said base insulating layer to cover said conductor trace excluding a portion below said opening; and a metal layer formed on the other surface of said base insulating layer, wherein said metal layer includes an opposite region that coincides with said opening of said cover insulating layer, and a stress relief region that contains said opposite region and is larger than said opposite region, one or plurality of slits are formed in said metal layer to divide said opposite region into a plurality of small regions and divide said stress relief region into a plurality of large regions including said small regions, respectively, and when a ratio of an area of one of said small regions with respect to a whole area of said opposite region is A %, a ratio of an area of said large region including said one small region with respect to a whole area of said stress relief region is set to not less than (A−α) % and not more than (A+α) %, said α being not more than (A×0.3).