Patent ID: 8200951

Claim:
A method for performing, in a processor, an operation to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream via a single instruction, comprising: (a) reading a plurality of bit field sizes referenced by a field sizes operand of the single instruction, one bit field size per source lane; (b) reading a plurality of bit fields from a plurality of source lanes referenced by a source operand of the single instruction, one bit field per source lane, wherein the number of bits in each bit field is determined by a respective one of the plurality of bit field sizes; (c) writing the plurality of bit fields into a combination reservoir in a continuous sequence; and (d) responsive to a determination that a number of bits in the combination reservoir is greater than or equal to a predetermined value: (i) writing the predetermined number of bits from the combination reservoir to a destination register; and (ii) reducing a count of the number of bits in the combination reservoir by the predetermined value, wherein each of the plurality of bit fields corresponds to data from a different tone or sub-carrier of a received signal.