Patent ID: 8797197

Claim:
An analog-to-digital conversion (ADC) stage ( 300 ) for digitizing two or more analog signals, the ADC stage ( 300 ) comprising: four or more ADCs ( 303 , 305 , 307 , 309 ) configured to receive the two or more analog signals, generate a first digitized signal from a first analog signal of the two or more analog signals, generate at least a second digitized signal from at least a second analog signal of the two or more analog signals to create two or more digitized signals, generate a first redundant digitized signal from the first analog signal, and generate a second redundant digitized signal from the second analog signal, with the first and second redundant digitized signals being generated substantially in parallel with the two or more digitized signals; a processing device ( 330 ) coupled to the four or more ADCs ( 303 , 305 , 307 , 309 ), with the processing device ( 330 ) configured to generate first and second phase drift values from phase differences between the first and second redundant digitized signals and the two or more digitized signals and compensate the two or more digitized signals using the first and second phase drift values.