Patent ID: 7285996

Claim:
A delay locked loop (DLL) circuit comprising: a delay line comprising serially connected first and second delay elements with said second delay element serially connected to a duty cycle monitor, wherein each delay element is adapted to receive at least a clock input signal and output at least a clock output signal with a phase offset from said clock input signal, the delay line configured so that at least one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal; and a feedback circuit configured to generate delay adjust signals based upon said phase offsets between at least one pair of signals selected from a set containing said reference input clock signal and said clock output signals, said delay adjust signals being fed back to at least one of said plurality of delay elements to cause said reference input clock signal to said plurality of clock output signals to be progressively phase-shifted apart equally about 360 degrees.