Patent ID: 8240016

Claim:
A method for manufacturing a multilayer electronic component comprising: a step of preparing a laminate having first and second principal surfaces opposed to each other, first and second end surfaces, and first and second side surfaces, the first and second end surfaces and the first and second side surfaces connecting the first and second principal surfaces, which includes a plurality of stacked insulator layers and a plurality of internal electrodes extending along the interfaces between the insulator layers, and in which an end of each of the plurality of internal electrodes is exposed at a predetermined surface corresponding to one of the first and second end surfaces, the ends of the plurality of internal electrodes being isolated from each other; a step of forming external electrodes on the predetermined surfaces of the laminate such that the ends of the plurality of internal electrodes exposed at the predetermined surfaces are electrically connected to each other by the corresponding external electrodes; and a step of forming thick-film edge electrodes at edge portions of the first and second principal surfaces and the first and second side surfaces adjacent to the first and second end surfaces by applying a conductive paste containing a metal powder and a glass frit, followed by baking, the thick-film edge electrodes being connected to either of the external electrodes; wherein the step of forming the external electrodes includes a step of attaching a plurality of conductive particles having a particle size of at least about 1 μm to the predetermined surfaces of the laminate prepared in the step of preparing the laminate; and a step of performing plating directly on the predetermined surfaces to which the conductive particles are attached.