Patent ID: 8793299

Claim:
A processor comprising: a memory to store one or more instructions including a multiply-add instruction; a register file including a plurality of registers to store packed data including a first complex number and a second complex number; and one or more execution units, wherein the one or more execution units to multiply the first and second complex number in response to performing the multiply-add instruction, wherein the one or more execution units to, generate a result data using elements of the first and second complex number, the result data includes a first result data element (R) and a second result data element (I), the first result data element is equal to [(r1×r2)−(i1×i2)] and the second result data element is equal to [(r1×i2)+(r2×i1)], the first complex number includes a first real value (r1) and a first imaginary value (i1) and the second complex number includes a second real value (r2) and a second imaginary value (i2), and store the result data in a destination indicated by the multiply-add instruction without adding the first result data element with the second result data element.