Patent ID: 7672803

Claim:
A system for providing programmable test conditions for a built-in self test circuit of a memory device, the system comprising: a flash memory; a BIST interface circuit adapted to receive one or more global variables associated with the test conditions of a plurality of memory tests used on the flash memory and to output results of the memory tests based on the value of the variables, wherein the global variables are shared between the plurality of memory tests; and wherein the global variables comprise one or more of: a drain voltage, a gate voltage, a reference voltage, a reference current, a number of pulses used in a checker board pattern test, a number of pulses used in a diagonal pattern test, a number of pulses used in an erase test, a number of pulses used in a zeroes program test, a repair/no repair selection, a program stress and read/read only selection, and a pattern to be used during a read test; and wherein test conditions associated with the global variables comprise: a drain voltage value, a gate voltage value, a reference voltage value, a reference current value, a maximum number of pulses used in a checker board pattern test, a maximum number of pulses used in a diagonal pattern test, a maximum number of pulses used in an erase test, a maximum number of pulses used in a zeroes program test, selection of one of a repair/no repair, selection of one of a program stress and read/read only, and selection of one of a read test pattern, respectively; and wherein the BIST interface circuit is adapted to adjust one or more test conditions of the shared global variables based on one or more earlier test results and use the adjusted one or more test conditions in an additional test; and a BIST circuit adapted to test operations of the flash memory based on the value of the variables programmed into the test conditions and to report results of the memory tests.