Patent ID: 8228222

Claim:
An amplifier device for receiving a digital input signal, and comprising: a digital delta-sigma modulator comprising M delta-sigma stages each comprising a state loop, where M is at least equal to 3, a quantifier receiving a signal supplied by a delta-sigma stage and supplying a quantified signal, and state loops to send state signals to adders of the delta-sigma stages, a power circuit to supply to an electric load an output signal which is function of the quantified signal, and N state loops of a first type configured to send the output signal to the adders of N delta-sigma stages of lower rank, where N is at least equal to 1, each state loop of the first type including: an analog low-pass filter for filtering the output signal and supplying a filtered output signal, and an analog to digital converter for converting the filtered output signal into digital filtered output signal, and supplying to the adders of the N delta-sigma stages of lower rank a digital filtered output signal including non-idealities of the output signal.