Patent ID: RE45307

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells; each of the plurality of transfer transistors comprising: a gate electrode formed on a semiconductor substrate via a gate insulation film; diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and upper layer wirings provided above the diffusion layers, wherein the transfer transistors comprise enhancement-type transistors and depression-type transistors, the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with a predetermined voltage at least when the transfer transistors become conductive to prevent depletion of the diffusion layer, and the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates.