Patent ID: 8225147

Claim:
An apparatus to determine a synchronization point in a first sequence of n-state symbols with n an integer equal to or greater than 2, comprising: a receiver to receive the first sequence of n-state symbols, wherein an n-state symbol is represented by a signal and the first sequence of n-state symbols contains a second sequence of n-state synchronization symbols that determines the synchronization point, wherein the second sequence of n-state synchronization symbols is determined by an n-state Linear Feedback Shift Register (LFSR); and a shift register based detector corresponding to the n-state LFSR to detect in the first sequence of n-state symbols the second sequence of n-state synchronization symbols, wherein: the detector includes an n-state logic function with a first and a second input and an output, the n-state logic function is defined by an n-state truth table wherein a state of the output is a first of n states only when the first and the second input have identical states, and wherein the first input of the n-state logic function and an input of the shift register are enabled to receive the first sequence, the second input of the n-state logic function receives an n-state symbol from an element of the detector and the output is enabled to provide a third sequence in response to the second sequence.