Patent ID: 7596666

Claim:
A semiconductor memory device, comprising: at least one shared memory area allocated in a memory cell array; a plurality of ports corresponding to a plurality of processors, each port used by the corresponding processor to selectively access the shared memory area; and an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port corresponding to the processor requesting access to the shared memory area to indicate whether access to the shared memory area is allowed; wherein the occupancy state signaling unit comprises: a plurality of decoding and generating units to decode external signals applied through the ports to generate active enable signals from the decoded external signals; a port output selecting unit to receive the active enable signals and output select control signals, wherein only one of the select control signals is at a logic high level at any time; and a plurality of occupancy state information outputting units to output respective port occupancy state information through data output pads of each port in response to the select control signals.