Patent ID: 7603639

Claim:
A method for designing integrated circuitry (“IC”), the method comprising: simulating noise of modeled IC operation, wherein the simulating includes simulating by a computer system and excludes certain clock circuitry of the IC; applying the simulated noise by the computer system to buffers of a clock tree of the modeled IC and responsively generating a first simulated clock tree output signal; scaling, by the computer system, components of the first simulated clock tree output signal in a frequency domain responsive to time domain variations of the components at respective frequencies; generating, by the computer system, a simulated, substantially noise-only, clock tree output signal in a frequency domain, including removing ones of the components responsive to i) at least one clock signal frequency of the certain clock circuitry and ii) magnitudes of the time variation scaled components; generating, by the computer system, a second simulated clock circuitry output signal responsive to applying a closed loop transfer function of the certain clock circuitry to a simulated reference clock signal and the substantially noise-only clock tree output signal; and selecting a circuit structure or a fabricating process for the IC responsive to jitter of the transformed second simulated clock circuitry output signal.