Patent ID: 8872566

Claim:
A semiconductor chip comprising: a plurality of latch circuits for fetching data bits in synchronization with a clock signal; a plurality of data pads associated with the plurality of latch circuits respectively, and arranged along an outer periphery of the semiconductor chip; a clock pad arranged along the outer periphery of the semiconductor chip; a clock line having a plurality of sub-lines to respectively connect the latch circuits with the clock pad; a plurality of data lines to connect the latch circuits with the data pads respectively; a plurality of first waveform shaping devices associated with the plurality of latch circuits respectively, each said first waveform shaping device being connected between the associated latch circuit and the clock pad; a plurality of second waveform shaping devices associated with the plurality of latch circuits respectively, each said second waveform shaping device being connected between the associated latch circuit and the associated data pad; a plurality of delay circuits associated with the plurality of latch circuits respectively, each said delay circuit being connected between the associated latch circuit and the associated data pad, each said delay circuit having an amount of delay corresponding to an amount of charge/discharge current supplied to an associated capacitor; and a ground line connected to one end of each said capacitor, wherein the ground line extends along the outer periphery of the semiconductor chip between the data pads and the delay circuits.