Patent ID: 7429512

Claim:
A method of fabricating a flash memory device, the method comprising the steps of: forming transistors in a cell region defining a cell gate, and forming high voltage PMOS and NMOS transistor formation regions defining a PMOS transfer gate and an NMOS transistor gate, respectively, on a semiconductor substrate; forming a source region by a source ion implant process; implanting a Double Doped Drain (DDD) ion into the cell region and the high voltage PMOS transistor formation region to form a first source junction and a first drain junction in the cell region and to form first and second P− junctions in the high voltage PMOS transistor formation region; performing a cell source/drain ion implant process on the cell region to form a second source junction and a second drain junction in the first source junction and the first drain junction, respectively; and forming spacers on the sides of the cell gate and the PMOS transistor gate and the NMOS transistor gate, and performing an ion implant process on the high voltage PMOS transistor formation region to form first and second P+ junctions in the first and second P− junctions.