Patent ID: 7765498

Claim:
A computer-implemented method, comprising: inputting a lookup table comprising, for a predetermined set of features supported by an integrated circuit (IC) fabrication process, dimensions and process induced dimension variations for each feature; inputting an IC layout; extracting a netlist from the IC layout, the extracted netlist specifying circuit elements implemented by the IC layout and further specifying interconnections between the circuit elements; running a search pattern on the IC layout to identify features in the IC layout corresponding to the features included in the lookup table; modifying, by a computer, dimensions of one or more of the circuit elements in the extracted netlist corresponding to the identified features using values of dimensions and process induced dimension variations from the lookup table, wherein a modified netlist is generated; performing a post-layout simulation of the modified netlist, wherein the post-layout simulation simulates behavior of an IC fabricated with the modified netlist; and outputting results of the post-layout simulation.