Patent ID: 7634751

Claim:
A design support system for aiding design of a semiconductor integrated circuit, the design support system comprising: a rough wiring unit configured to: receive cell arrangement information indicating an arrangement of a plurality of cells; define a plurality of rough grid areas on a wiring region having a plurality of layers; roughly allocate wiring paths into each rough grid area, wherein the wiring paths are configured to connect the plurality of cells, and wherein the wiring paths are allocated based on occupying areas of the wiring paths when a multi-cut via is used; and output rough wiring path information indicating the roughly allocated wiring paths; a detailed wiring unit configured to: receive the rough wiring path information; arrange the wiring paths in each rough grid area by use of a single-cut via; and output detailed wiring path information indicating the arranged wiring paths; and multi-cut via replacing unit configured to: receive the detailed wiring path information; and replace the single-cut via with the multi-cut via; and output layout information indicating the wiring paths that have been arranged with the multi-cut via replacing the single-cut via.