Patent ID: 8766230

Claim:
A multi-bit memory unit, comprising: a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region, the gate stack structure comprising: an insulating layer over the substrate; a first solid electrolyte cell over the insulating layer, the first solid electrolyte cell having a capacitance that is controllable between at least two states and proximate the source region; a second solid electrolyte cell over the insulating layer, the second solid electrolyte cell having a capacitance that is controllable between at least two states and proximate the drain region; an insulating element separates the first solid electrolyte cell from the second solid electrolyte cell; a first anode electrically coupled to the first solid electrolyte cell; a second anode electrically coupled to the second solid electrolyte cell; and a gate contact layer electrically coupled to a voltage source, wherein the first solid electrolyte cell is disposed between the gate contact layer and the insulating layer and the second solid electrolyte cell is disposed between the gate contact layer and the insulating layer.