Patent ID: 7073112

Claim:
A plurality of memory arrays, each memory array comprising: a compilable address magnitude comparator, the compilable address magnitude comparator of each memory array receiving a self-test address from a self-test controller and comparing the self-test address to a compiled maximum address of each memory array, the compilable address magnitude comparator of each memory array preventing testing of memory of each memory array corresponding to the self-test address if the self-test address exceeds the compiled maximum address of each memory array; wherein the compilable address magnitude comparator of each memory array prevents testing of memory of each memory array by forcing a memory pass signal; wherein the compilable address magnitude comparator of each memory array includes a row comparator and a column comparator, the row comparator comparing a self-test row address of each memory array and the column comparator comparing a self-test column address of each memory array; and wherein the compiled maximum address of each memory array comprises a maximum row address of each memory array and a maximum column address of each memory array; wherein the compilable address magnitude comparator of each memory array prevents testing of memory of each memory array by forcing a read operation instead of a write operation.