Patent ID: 8273652

Claim:
A method of manufacturing a semiconductor memory device, the method comprising: providing a semiconductor substrate having junction regions and contact plugs formed thereon, the junction regions being formed between gate patterns and the contact plugs being connected to the corresponding junction regions in a first insulation layer with which the gate patterns are covered; forming a second insulating layer including first and second pad holes, wherein the first and second pad holes extend in different directions, the first and second pad holes exposing the contact plugs; forming first and second conductive pads in the first and second pad holes, respectively; forming a third insulating layer including dual damascene patterns and pad contact holes, wherein the dual damascene pattern exposes an extended portion of the first conductive pad, the pad contact hole exposing an extended portion of the second conductive pad; forming a first pad contact plug and a first bit line in the dual damascene pattern; forming a second pad contact plug in the pad contact hole; forming a fourth insulating layer including trenches that exposes the second pad contact plugs; and forming a second bit line in the trench.