Patent ID: 7730268

Claim:
A memory interface, comprising: a first controller adapted for coupling to a volatile memory; a second controller adapted for coupling to a nonvolatile memory, wherein access to the volatile memory and the nonvolatile memory is shared by a first processor and a second processor coupled to the memory interface; a first interface component adapted to: receive, from the first processor, a first volatile memory read request and a first nonvolatile memory read request; satisfy the first volatile memory read request by accessing the volatile memory; and satisfy the first nonvolatile memory read request by accessing the nonvolatile memory and the volatile memory; a second interface component adapted to receive, from the second processor, a second volatile memory read request and to satisfy the second volatile memory read request by accessing the volatile memory; a third interface component adapted to receive, from the second processor, a second nonvolatile memory read request and to satisfy the second nonvolatile memory read request by accessing the nonvolatile memory; a transaction interleaver configured to receive the first volatile memory read request, the first nonvolatile memory read request, the second volatile memory read request, and the second nonvolatile memory read request ; and a dual port random access memory (RAM) comprising one or more addressable memory locations accessible to the first processor and the second processor and usable to carry out interprocessor communication between the first processor and the second processor,