Patent ID: 8914756

Claim:
A process for fabricating an integrated circuit comprising an analog block and a digital block, the process comprising: designing the analog block and the digital block to be on a same substrate; the designing of the analog block and the designing of the digital block comprising taking each design from a library of components, the library of components defined in a native technology and having an associated shrunken technological version for the library of components; the designing of the analog block comprising generating a first initial file representative of the analog block in the native technology, and constructing, based on the first initial file, a first intermediate file representative in said native technology of at least part of the analog block and a dimensional reduction in contacting areas on electrically active regions and electrically conductive interconnects between metallization levels; the designing of the digital block comprising generating a second initial file representative of the digital block in the native technology, and constructing, based on the second initial file, a second intermediate file representative in said shrunken technological version of all of said digital block; and generating at least one mask file based upon the analog and digital blocks and a combination of the first intermediate file and the second intermediate file.