Patent ID: 8853823

Claim:
A capacitor of a nonvolatile memory device, comprising: first and second lower electrodes formed in a capacitor region of a semiconductor substrate to each have a rake structure, wherein fingers of each rake structure alternate with the fingers of the other rake structure; a first dielectric layer formed between the first and second lower electrodes and over the first and second lower electrodes; first and second upper electrodes formed over the first dielectric layer to each have a rake structure, wherein fingers of each rake structure alternate with the fingers of the other rake structure have a crossing finger structure; a second dielectric layer formed between the first and the second upper electrodes; a first electrode line coupling the first upper electrode to the first lower electrode; and a second electrode line coupling the second upper electrode to the second lower electrode, wherein the first upper electrode is formed over the second lower electrode, and the second upper electrode is formed over the first lower electrode.