Patent ID: 6977837

Claim:
A semiconductor memory comprising: a first and a second field effect transistors having a first line as gates, one ends of current paths of the first and second field effect transistors being connected to a reference electrode supplied with a reference potential; a third and a fourth field effect transistors having a second line as gates, one ends of current paths of the third and fourth field effect transistors being connected to the reference electrode; a fifth field effect transistor having a first word line as a gate, one end of a current path of the fifth field effect transistor being connected to the other ends of the current paths of the first and second field effect transistors; and a sixth field effect transistor having a second word line as a gate, one end of a current path of the sixth field effect transistor being connected to the other ends of the current paths of the third and fourth field effect transistors, wherein the current paths of the first and second field effect transistors are connected in parallel between the one end of the current path of the fifth field effect transistor and the reference electrode, and the current paths of the third and fourth field effect transistors are connected in parallel between the one end of the current path of the sixth field effect transistor and the reference electrode.