Patent ID: 8395933

Claim:
A resistance-change semiconductor memory comprising first to fourth memory cells aligned in a first direction, wherein each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor, a second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction, the other end of the resistive memory element is connected to one of the first and second bit lines which is not connected to the second source/drain region; the second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared, and the first and second memory cells are arranged in a first element region, and the third and fourth memory cells are arranged in a second element region different from the first element region.