Patent ID: 6894549

Claim:
A ferroelectric, non-volatile SR flip-flop comprising: a set input; a reset input; a Q output; a complementary Q output; a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output; a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output; and a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground; and a third ferroelectric capacitor coupled between the Q and complementary Q outputs.