Patent ID: 7233380

Claim:
A method of fabricating an array substrate for use in an IPS-LCD device, comprising: forming a gate line, a gate electrode, a common line and first and second common electrodes on a substrate using a first metal layer, wherein the gate and common lines are disposed in a first direction; forming a gate insulation layer on an entire surface of the substrate to cover the first metal layer; forming an active layer on the gate insulation layer and an ohmic contact layer on the active layer using an amorphous silicon and impurity-doped amorphous silicon; forming a data line, a source electrode, a drain electrode and a pixel electrode using a second metal layer, wherein the data line is disposed on the gate insulation layer in a second direction substantially perpendicularly crossing both the gate line and the common line to define a pixel area, wherein the source and drain electrodes are disposed on the ohmic contact layer and spaced apart from each other, and wherein the pixel electrode is disposed on the gate insulation layer and includes a first portion that is disposed between the first and second common electrodes, a second portion that is disposed to have a width along the first direction substantially completely overlapped by the second common electrode, and a third portion that is disposed above the common line, wherein the first and second portions of the pixel electrode are substantially perpendicular to the third portion of the pixel electrode; and forming a thin film transistor at a crossing of the gate and data lines, the thin film transistor having of the gate electrode, the active layer, the ohmic contact layer, the source electrode and the drain electrode, wherein the second common electrode is formed to have a width larger than the first common electrode.