Patent ID: 6839816

Claim:
A method for cache updating, comprising: providing at least a first processor and a second processor having a first cache and a second cache, respectively; obtaining, with the first processor, a first lock to a first shared memory region; accessing, with the first processor, at least a first location in the first shared memory region; placing a cache line for the first location in the first cache; releasing the first lock with the first processor; obtaining, with the second processor, the first lock after the first processor releases the first lock; in response to the second processor obtaining the first lock, pushing from the first cache to the second cache the cache line for the first location without an access by the second processor to the first shared memory region for the first location; and obtaining, with the first processor, a second lock to a second shared memory region after obtaining the first lock and before releasing the first lock by the first processor; accessing, with the first processor, at least a third location in the second shared memory region; releasing, with the first processor, the second lock before the first processor releases the first lock; if the second processor obtains the second lock after the first processor releases the second lock, pushing from the first cache to the second cache a cache line for the third location in response to the second processor obtaining the second lock; and if a third processor obtains the second lock after the first processor releases the second lock, pushing from the first cache to a third cache of the third processor a cache line for the third location in response to the third processor obtaining the second lock.