Patent ID: 8120181

Claim:
An integrated circuit comprising: a silicon substrate; a transistor in or on said silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a separating layer over said first metallization structure and said dielectric layer, wherein said separating layer comprises a nitride, wherein a first opening in said separating layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening; a first polymer layer over said separating layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers; a second metallization structure on said first polymer layer, wherein said second metallization structure is connected to said first contact point through said first opening and a second opening in said first polymer layer, wherein said second metallization structure comprises a glue layer and an electroplated copper layer over said glue layer, wherein an undercut has an edge of said glue layer recessed from an edge of said electroplated copper layer; and a second polymer layer on said second metallization structure.