Patent ID: 8493115

Claim:
A phase locked loop (PLL) circuit, comprising: a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal; a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, the loop filter including: a first MOS capacitor and a resistor connected in series between a power supply voltage terminal and an output terminal of the voltage adjusting unit, and a capacitor connected in parallel to the first MOS capacitor and the resistor and configured to accumulate or emit charges depending on the charge pumping of the voltage adjusting unit and control the level of the frequency control voltage; a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage; and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to counterbalance each other, the current control circuit including: a current generator including a current mirror circuit including first and second current paths and configured to control an inflow amount of the compensation current of the second current path according to a control current supplied from a second MOS capacitor to the first current path, wherein one side of the first current path is connected to the second MOS capacitor, and one side of the second current path is connected to a node between the first MOS capacitor and the resistor, and a voltage controller configured to compare a path voltage, which varies with the control current, with a reference voltage and output a current control voltage used for controlling the control current based on the comparison result.