Patent ID: 8051403

Claim:
A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit, comprising: a defect distribution extraction unit which extracts a distribution of resistance or current caused by physical defects related to layout elements or a combination of the layout elements composing the semiconductor integrated circuit; a delay fault-layout element information extraction unit which extracts the layout elements or the combination of the layout elements with interconnect wiring information including location information and interconnect capacitance, and a delay fault to be associated with inside the semiconductor integrated circuit as delay fault-layout element information by associating the layout elements or the combination thereof with delay faults to be assumed inside the semiconductor integrated circuit, the delay fault resulting from a value obtained from the resistance and interconnect capacitance of the layout element, or the combination thereof; a delay defect distribution calculation and weighting unit which calculates a distribution of delay defect on the basis of the distribution of the resistance or current and adds weight to each of the delay faults on the basis of the delay fault-layout element information; and a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, the delay defect distribution of resistance or current caused by physical defects, and the weights.