Patent ID: 7542352

Claim:
A bit line precharge circuit, comprising: a reference precharge sub-circuit, comprising: a first current mirror, receiving a reference current and providing a first current to a first drain bias controller according to the reference current; the first drain bias controller, coupled to the first current mirror, comprising a first inverter and a first clamping NMOS transistor, wherein a source end of the first clamping NMOS transistor is coupled to an input of the first inverter and used to receive the first current, and an output of the first inverter is coupled to a gate end of the first clamping NMOS transistor; and a first current-voltage converter, coupled to a drain end of the first clamping NMOS transistor of the first drain bias controller, acting as a precharge PMOS transistor whose gate end is coupled to ground or acting as a diode load according to a precharge signal; and at least one precharge sub-circuit, comprising: a second current-voltage converter, acting as a precharge PMOS transistor whose gate end is coupled to ground or acting as a diode load according to the precharge signal; a second clamping NMOS transistor, a gate end thereof is coupled to the output of the first inverter, a drain end thereof is coupled to the second current-voltage converter and a sensed amplifier, and a source end thereof is coupled to one end of an equalization switch; the equalization switch, the other one end thereof is coupled to the source end of the first clamping NMOS transistor, controlled by the precharge signal to equalize the both ends thereof; and a memory cell, controlled by a word line signal, having a bit line coupled to the source end of the second clamping NMOS transistor.