Patent ID: 7595665

Claim:
A clock gated circuit comprising: a clock signal receiving unit configured to apply a first voltage to a fighting node when a clock signal is at a first logic; a discharging unit configured to discharge an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when an enable signal is activated; a voltage maintaining unit configured to maintain the fighting node at one of a power voltage or a ground voltage; an output unit configured to invert a logic level of the fighting node to generate a gated clock signal; a blocking unit configured to block a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging occurs; and a blocking prevention unit configured to prevent blocking of a power voltage provided to the fighting node by the voltage maintaining unit, when the clock signal is at the second logic and the enable signal is deactivated before the fighting node is fully discharged, wherein the gated clock signal is fixed at a specific logic level when the enable signal is deactivated, regardless of a logic level of the clock signal.