Patent ID: 7969201

Claim:
A decoder circuit comprising: a gradation-voltage output section, configured by a plurality of MOS transistors arrayed in a tournament manner with a plurality of hierarchies, that outputs from an output terminal a gradation voltage selected by a MOS transistor of the plurality of MOS transistors that is selected in accordance with a decode signal input to a first hierarchy among the plurality of hierarchies; and a discharge section that discharges electric charges accumulated in a second wiring by a coupling capacity caused between a first wiring connecting MOS transistors of the plurality of MOS transistors that are of a top hierarchy and the output terminal, and the second wiring connecting between MOS transistors of the plurality of MOS transistors that are in adjacent hierarchies among the plurality of hierarchies, wherein the discharge section discharges the electric charges accumulated in the second wiring for a predetermined period from when a start signal which starts operation of the decoder circuit is changed from an OFF state to an ON state.