Patent ID: 7313769

Claim:
A method of producing an integrated circuit (IC) device layout representation corresponding to an IC device design, said method comprising: (a) generating an initial layout representation in accordance with a plurality of design rules; (b) simulating how structures within at least a portion of the initial layout representation will pattern on a wafer; (c) based on the simulating step, identifying portions of the layout representation which include structures demonstrating poor manufacturability; (d) based on the simulating step, identifying portions of the layout representation in which extra manufacturability margin is present; and (e) modifying at least one of (i) portions of the layout representation which include structures demonstrating poor manufacturability and (ii) portions of the layout representation in which extra manufacturability margin is present; wherein for portions of the layout representation including structures demonstrating poor manufacturability, step (e) includes: at least one of (i) providing more space between adjacent structures, (ii) decreasing linewidth of one or more structures, and (iii) making edges of one or more structures wider.