Patent ID: 6848032

Claim:
A method for pipelining cache coherence operations in a shared memory multiprocessor system, comprising: receiving a command to perform a memory operation from a processor in the shared memory multiprocessor system; wherein the command is received at a coherence circuit that is coupled to local caches of processors in the shared memory multiprocessor system; if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, delaying the command until the in-progress pipelined cache coherency operation completes; and if the command is not directed to a cache line that is subject to an in-progress pipelined cache coherency operation: reflecting the command to local caches of other processors in the shared memory multiprocessor system, accumulating snoop responses from the local caches of other processors, and sending an accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system.