Patent ID: 8253173

Claim:
A semiconductor device, comprising: a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged opposite the number of P-diffusion such that a non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively; at least seven linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device, the at least seven linear shapes being spaced apart from each other in a second direction in accordance with a first equal pitch, the second direction being perpendicular to the first direction, and a spacing of the at least seven linear shapes in the second direction forming a regular pattern, wherein all linear shapes within the gate layer region of the region of the semiconductor device are within 1930 nanometers of each other, wherein some of the at least seven linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including, (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor, (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that, (i) the first N and P transistors aligned along the first direction and electrically connected to each other through their gate defining shapes, (ii) the second N and P transistors aligned along the first direction and their gate defining shapes having extensions not electrically connected to each other, (iii) the third N and P transistors aligned along the first direction and their gate defining shapes having extensions not electrically connected to each other, (iv) the fourth N and P transistors aligned along the first direction and electrically connected to each other through their gate defining shapes, (v) the first, second, third and fourth N and P transistors maintain the spacing in the second direction to form the regular pattern, and (vi) the second and third N and P transistors are respectively positioned between the first and fourth N and P transistors; a first contact contacting the gate defining shape of the second N transistor; a second contact contacting the gate defining shape of the second P transistor; a third contact contacting the gate defining shape of the third N transistor; and a fourth contact contacting the gate defining shape of the third P transistor, wherein at least two of the first, second, third, and fourth contacts are positioned outside the non-diffusion region that exists between the number of N-diffusion collectively and the number of P-diffusion collectively.