Patent ID: 8543960

Claim:
A method of optimizing power and timing for an integrated circuit (IC) chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges, said method comprising: selecting a high voltage to be supplied to all cells of said IC chip using an IC technology that exhibits temperature inversion, said high voltage meeting said timing delay performance from a closed timing analysis for said IC chip across a full temperature range for all operation, said full temperature range being divided into a lower temperature range and a higher temperature range, said high voltage meeting said power consumption performance across said lower temperature range and a portion of said higher temperature range extending from a lower bound of said higher temperature range to a temperature cut point within a range of temperature cut points in said higher temperature range; selecting a low voltage to be supplied to said all cells of said IC chip, said low voltage meeting said timing delay performance and said power consumption performance from said temperature cut point to an upper bound of said higher temperature range; powering-on said all cells of said IC chip at said high voltage; after said powering-on, monitoring a temperature of said IC chip; and lowering said high voltage supplied to said all cells of said IC chip to said low voltage, when said temperature cut point is exceeded, to meet said power consumption performance while meeting said timing delay performance.