Patent ID: 7162559

Claim:
An interrupt controller for interrupts generated by one or more I/O devices to one or more CPUs coupled to the one or more I/O devices through a system controller device, the interrupt controller comprising: a number N of first level interrupt registers, each having a number M of bits, each bit corresponding to a particular interrupt; a number N of first level mask registers, each having a number M of bits, each bit corresponding to a particular interrupt, each of the N first level mask registers corresponding to one of the N first level interrupt registers and each of the M bits in each of the N first level mask registers corresponding to one of the M bits in the corresponding first level interrupt register; a number N of first level mask logic devices, each receiving the M bits from a corresponding one of the N first level interrupt registers and the M bits from the corresponding one of the N first level mask registers and outputting a first level signal; a second level interrupt register having N bits, each for storing the first level signal output by a different one of the first level mask logic devices; a number X of second level mask registers, the number X corresponding to the number of CPUs coupled to the one or more I/O devices through the system controller device, each of the second level mask registers having a number N of bits; and a number X of second level mask logic devices, each of the X second level mask logic devices receiving the N bits from the second level interrupt register and the N bits from a corresponding one of the X second level mask logic devices and outputting an interrupt indication signal to a corresponding one of the CPUs; wherein the state of each of the N bits in the second level interrupt register, as set by the first level signal output by each first level mask logic devices, is based on the states of the M bits in each corresponding first level interrupt register and the corresponding M bits in the corresponding first level mask register; and wherein the state of the interrupt indication signal output by each of the second level mask logic devices is based on the states of the N bits in the corresponding second level mask register and the N bits in the second level interrupt register.