Patent ID: 7130367

Claim:
A delay lock loop (DLL) circuit for an N-bit datapath, comprising: a clock loop, including a clock variable delay unit (VDU) for receiving and delaying a clock signal, a data VDU for receiving and delaying the clock signal, a phase detector configured to measure a phase difference between the delayed clock signals, a filter/control circuit for adjusting the delay of the clock VDU to align the clock signal to within an eye opening of each one of a plurality of at least partially parallel data signals, and a lock circuit for generating a lock signal when the clock signal is aligned; and N data loops, each data loop being enabled by the lock signal and including a clock VDU for receiving and delaying the clock signal, a data VDU for receiving and delaying one of N at least partially-coincident parallel data signals being time-shifted from each other, a phase detector configured to measure a phase difference between the delayed clock signal and the delayed data signal, the filter/control circuit for adjusting the delay of the data VDU to align the data signal with the adjusted delayed clock signal, and a demultiplexer for outputting the aligned data signal and adjusted delayed clock signal.