Patent ID: 6925411

Claim:
An apparatus that measures an alignment between a first semiconductor die and a second semiconductor die, comprising: a plurality of conductive elements on the first semiconductor die; a plurality of conductive elements on the second semiconductor die, wherein the plurality of conductive elements on the second semiconductor die have a different spacing than the plurality of conductive elements on the first semiconductor die, whereby a vernier alignment structure is created when the plurality of conductive elements on the first semiconductor die overlap the plurality of conductive elements on the second semiconductor die; a charging mechanism configured to selectively charge each of the plurality of conductive elements on the first semiconductor die, wherein charging a conductive element on the first semiconductor die induces a charge in one or more conductive elements on the second semiconductor die when the conductive element on the first semiconductor die overlaps one or more conductive elements on the second semiconductor die; an amplification mechanism configured to amplify signals induced in the conductive elements on the second semiconductor die; and an analysis mechanism configured to analyze the amplified signals to determine the alignment between the first semiconductor die and the second semiconductor die.