Patent ID: 7499339

Claim:
A flash memory device, comprising: at least one memory array comprised of non-volatile memory cells arranged in rows and columns; a data register, for storing data corresponding to stored states of the memory cells in the at least one memory array; and control circuitry, coupled to the data register, coupled to input/output terminals, and coupled to a plurality of control terminals, for receiving data from the input/output terminals and for presenting data to the input/output terminals, and for controlling the operation of the device in a normal operating mode and in an advanced mode, responsive to control signals received at the control terminals; wherein, in the normal operating mode, the control circuitry presents data words at the input/output terminals responsive to a read data strobe signal received at a first one of the plurality of control terminals; wherein, in the normal operating mode, the control circuitry latches data words received at the input/output terminals into the data register, responsive to a write data strobe signal received at the second one of the plurality of control terminals; wherein, in the advanced operating mode for a read transfer, the control circuitry presents read data strobe signals and write data strobe signals at corresponding ones of the plurality of control terminals, the write data strobe signals out-of-phase relative to the read data strobe signals, and presents data words at the input/output terminals responsive to a selected transition of each of the read data strobe signal and the write data strobe signal.