Patent ID: 7969193

Claim:
A differential sensing and TSV timing control scheme for a stacked device having pluralities chip layers, comprising: a first chip layer of said stacked device including a timing-detecting circuit and a relative high ability driver at the same chip layer horizontally coupled to said timing-detecting circuit; a sensing circuit coupled to said timing-detecting circuit in said first chip layer by a horizontal conductive line; a first differential signal driver coupled to said sensing circuit horizontally in said first chip layer; a Nth chip layer of said stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on said Nth chip layer; wherein said N is a nature number and is more than one; wherein said Nth relative high ability driver is vertically coupled to said first relative high ability driver through one relative low loading TSV and (N−2) relative high loading TSVs to act dummy loadings, said relative low loading TSV and said (N−2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer, wherein said relative low loading TSV and said (N−2) relative high loading TSVs are formed in a shared configuration; wherein said Nth differential signal driver is vertically coupled to said first differential signal driver through a pair of relative low loading TSVs and (N−2) pairs of relative high loading TSVs, vertically, said pair of relative low loading TSVs and said (N−2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer; and each said relative low loading TSV being formed between said first and a second chip layers, each said relative high loading TSV being formed between any adjacent two chip layers of said stacked device; whereby said detecting circuit activates said sensing circuit when an active signal reaches to a trigger point.