Patent ID: 7764088

Claim:
A frequency detection circuit, for a clock data recovery (CDR) circuit, comprising: a phase detector, sampling a data signal according to a first clock signal provided by the CDR circuit and obtaining a first plurality of sampling values, and providing a phase instruction signal according to the first plurality of sampling values; a first delayer, delaying the first clock signal so as to obtain a second clock signal; a frequency detector, coupled to the first delayer, sampling the data signal according to the second clock signal and obtaining a second plurality of sampling values, and providing a frequency instruction signal according to the second plurality of sampling values; and a logic circuit, coupled to the phase detector and the frequency detector, executing a logic computation with the phase instruction signal and the frequency instruction signal to generate a clock instruction signal; wherein when the phase instruction signal and the frequency instruction signal both present a frequency boosting status, the logic circuit makes the clock instruction signal to present the frequency boosting status; when the phase instruction signal presents a frequency reduction status while the frequency instruction signal presents the frequency boosting status, the logic circuit makes the clock instruction signal to present the frequency reduction status; and when the frequency instruction signal presents the frequency reduction status, the logic circuit makes the clock instruction signal to present a frequency maintaining status; wherein when the clock instruction signal presents the frequency boosting status, the CDR circuit boosts a frequency of the first clock signal; when the clock instruction signal presents the frequency reduction status, the CDR circuit reduces the frequency of the first clock signal; and when the clock instruction signal presents the frequency maintaining status, the CDR circuit maintains the frequency of the first clock signal unchanged.