Patent ID: 7185226

Claim:
A method of providing fault tolerance in a parallel computer system which includes a plurality of parallel processors to render the computer system tolerant to hardware failures comprising: providing the computer system with extra groups of redundant standby processors, said computer system comprising an array of a×b×c compute nodes connected as a three dimensional torus wherein each compute node connects by 6 links, including wrap links, in the + and −x, y, z directions to 6 adjacent compute nodes, and further including communication links over a global combining tree of links, and a similar combining tree for a set of global interrupt signals; and, designing the computer system so that the extra groups of redundant standby processors can be switched to operate in place of a group of processors of the computer system which experiences a hardware failure, wherein the computer system's torus, global combining tree, and global interrupt signals pass through a link chip which redirects signals between different ports of the link chip to enable the computer system to be partitioned into multiple, logically separate systems.