Patent ID: 7010677

Claim:
A data processor with a hardware repeat function which executes a repeat block composed of plural instructions N times (N is an integer equal to or more than 0) repeatedly, and stops the repeat processing after processing a designated instruction in a N+1 th repeat processing, independently of an operation specified by an instruction being executed, said data processor comprising: a detecting unit for detecting that a processing instruction is said designated instruction and the repeat processing breaks after said designated instruction has been completed; a first instruction processing sequence switching unit to switch the instruction processing sequence to a first instruction within the repeat block after a last instruction in the repeat block has been completed when the repeat processing is made to continue by a detection result of said detecting unit; and a second instruction processing sequence switching unit to inhibit fetching of remaining instructions within the repeat block after completion of said designated instruction and to make fetching of a next instruction outside of said repeat block when the repeat processing is made to break by the detection result of said detecting unit.