Patent ID: 6856176

Claim:
An apparatus for providing an input output from an integrated circuit, the apparatus comprising: an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices coupled between a power supply (V DDO ) and an I/O pad; a lower pair of N-channel MOS devices (NMOS), coupled between the I/O pad and a ground potential; a first bias circuit providing a first bias voltage to the first upper PMOS device when the I/O pad is in an output mode and V DDO voltage otherwise; a second bias circuit providing a second bias voltage to the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit providing a first fixed voltage to the second upper PMOS device when V PAD is less than the V DDO voltage and a voltage equal to V PAD otherwise; and a fourth bias circuit providing a second fixed voltage when V PAD is less than a pre-determined value and a voltage higher than the second fixed voltage otherwise.