Patent ID: 8004361

Claim:
A circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, wherein: the first transistor, the second transistor, the third transistor, and the fourth transistor are all of a same conductivity type, sources of the first transistor, the second transistor, the third transistor, and the fourth transistor are electrically coupled together, drains of the first transistor and the third transistor are electrically coupled together, drains of the second transistor and the fourth transistor are electrically coupled together, a feature of the third transistor is three times a feature of the first transistor such that 3 ⁡ [ μC ox ⁡ ( W L ) ] T ⁢ ⁢ 1 = [ μC ox ⁡ ( W L ) ] T ⁢ ⁢ 3 is satisfied where “T 1 ” denotes the first transistor and “T 3 ” denotes the third transistor, a feature of the fourth transistor is three times a feature of the second transistor such that 3 ⁡ [ μC ox ⁡ ( W L ) ] T ⁢ ⁢ 2 = [ μC ox ⁡ ( W L ) ] T ⁢ ⁢ 4 is satisfied where “T 2 ” denotes the second transistor and “T 4 ” denotes the fourth transistor, wherein C ox comprises a gate dielectric capacitance of a respective transistor, W is a width of a channel of the respective transistor, and L is a length of the channel of the respective transistor; a first switch operable to selectively electrically couple a first input terminal to a gate of the third transistor; and a second switch operable to selectively electrically couple a second input terminal to a gate of the fourth transistor.