Patent ID: 7275137

Claim:
An apparatus for handling a transmit enable signal in a memory controller, comprising: transmit enable logic that is configured to assert the transmit enable signal at least for a first predetermined number of cycles greater than one and for the duration of a write; and control logic that provides a feedback signal to the transmit enable logic, wherein the control logic provides the feedback signal to the transmit enable logic by: generating at least one queue of bits to track the sequence of memory commands; asserting the feedback signal if the at least one queue is empty; if an entry at a top of the at least one queue indicates a valid write command, asserting the feedback signal and removing the entry from the at least one queue; and if the entry at the top of the at least one queue does not indicate a valid write command, deasserting the feedback signal and removing the entry from the at least one queue; wherein the transmit enable logic has at least one feedback loop, and wherein the transmit enable logic is configured to receive the feedback signal in the at least one feedback loop and to keep the transmit enable signal asserted after the first predetermined number of cycles if the feedback signal is asserted and to deassert the transmit enable signal for a second predetermined number of cycles greater than one if the feedback signal is deasserted.