Patent ID: 7436232

Claim:
A clock repeater for regenerating a clock signal on a clock distribution line, comprising: an edge detector means for sensing a rising edge and a falling edge of said clock signal and generating respective pull-up and pull-down control signals in response thereto; and an output driver means, connected to said edge detector means to receive said control signals therefrom, for recovering high and low logical levels of said clock signal; wherein said edge detector means further comprises: a level detector means for generating a first signal and a second signal by detecting a rise edge from a low logical level and a fall edge from a high logical level of said clock signal; a first logic NOR gate adapted to receive an inverse of the first signal and an inverse of the second signal; a second logic NOR gate adapted to receive the first signal and the second signal; a set/reset latch coupled to an output of the first logic NOR gate at a set input terminal, and an output of the second logic NOR gate at the reset input terminal to produce a third signal; a first logic NAND gate adapted to receive the first signal, the inverse of the second signal and the third signal to generate the pull-up control signal; and a third logic NOR gate adapted to receive the inverse of the first signal, the second signal, and the third signal to generate the pull-down control signal.