Patent ID: 8145804

Claim:
A device comprising: a memory flow controller having a direct memory access (DMA) engine; wherein the DMA engine is configured to transfer data between a local memory dedicated to a processing element and a data source external to the processing element; wherein the DMA engine is configured to transfer multiple-word lines of data; and wherein the DMA engine is configured to operate alternately in either a first mode or a second mode, wherein in the first mode, the DMA engine transfers each line of data without transposing the words in each line of data, and wherein in the second mode, the DMA engine transposes the words in each line of data when the DMA engine transfers the line of data; wherein the device further comprises a processing element configured to receive lines of data transferred by the DMA engine to the local memory, wherein the processing element includes logic circuitry configured to add doublewords in the lines of data, wherein the logic circuitry is configured to carry bits from the first words of the doublewords to the second words of the doublewords in response to determining that the data source implements a little-endian data representation, and wherein the logic circuitry is configured to carry bits from the second words of the doublewords to the first words of the doublewords in response to determining that the data source implements a big-endian data representation.