Patent ID: 6916734

Claim:
A method for manufacturing a semiconductor device, comprising: forming a lower dielectric layer on top of a lower metal layer; forming an upper metal layer on top of the lower dielectric layer; forming an upper dielectric layer on top of the upper metal layer; forming a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer, and that serves as a contact region for access to a solder pad portion of the lower metal layer; forming a dielectric lining layer on the upper dielectric layer such that the dielectric lining layer fills the cavity; removing a central portion of the dielectric lining layer from the cavity such that the dielectric lining lines a peripheral cavity-confining surface of the cavity that is transverse to a plane of the lower metal layer to isolate the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer; and filling the cavity with a liquid metal to form an electrical contact that enables external electrical connection with the lower metal layer.