Patent ID: 8054853

Claim:
A meshed switching architecture supporting time division multiplexed and packet connections over common links, comprising: a plurality of connections in a mesh configuration between a first slot and one or more slots; and first circuitry on the first slot and each of the one or more slots connected to the plurality of connections, wherein the first circuitry is configured to provide an interface between each of the plurality of connections and between second circuitry on the first slot and each of the one or more slots; wherein the second circuitry comprises packet processing circuitry and time slot mapping circuitry; wherein the first slot and the one or more slots are each configured to accept both packet and time division multiplexed cards simultaneously; and wherein the plurality of connections support packet and time division multiplexed connections with separate switching of both the packet and the time division multiplexed connections and with transporting the packet and the time division multiplexed connections together within separate connections of the plurality of connections.