Patent ID: 7517758

Claim:
A method of forming a vertical transistor, comprising: providing a first material received over a monocrystalline material and an opening through the first material extending to the monocrystalline material; lining opposing sidewalls of the opening with a second material by deposition of the second material over the first material and to within the opening over the monocrystalline material, followed by anisotropic etching of the second material effective to expose the monocrystalline material centrally within the opening; epitaxially growing a first silicon-comprising layer from the exposed monocrystalline material within the second material-lined opening; etching the second material lining effective to expose monocrystalline material therebeneath adjacent the first silicon-comprising layer; after the etching, epitaxially growing a second silicon-comprising layer from the first silicon-comprising layer within the opening and from the monocrystalline material exposed within the opening beneath the second material that was removed, the second silicon-comprising layer being contiguous within the opening; forming a gate dielectric layer of the vertical transistor over the second silicon-comprising layer, and a gate of the vertical transistor over the gate dielectric layer; and providing the second silicon-comprising layer to comprise at least a part of both a channel region of the vertical transistor and a source/drain region of the vertical transistor.