Patent ID: 7135934

Claim:
A programmable phase locked loop (PLL) circuit, comprising: a receiver circuit that level shifts voltage of a first clock relative to a second clock to provide a level-shifted third clock and that provides a fourth clock based on said second clock, said receiver circuit providing said third and fourth clocks; a phase frequency detector circuit having first and second inputs to receive said third and fourth clocks, and a plurality of outputs providing a plurality of clock control signals based on a comparison between said third and fourth clocks; a pulse delay modulator that has a plurality of inputs that receive said plurality of clock control signals and a plurality of outputs that provide a plurality of delayed clock control signals; a charge pump having a plurality of inputs receiving said plurality of clock control signals and an output providing a frequency control voltage; and a voltage controlled oscillator (VCO) having a first input receiving said frequency control voltage, a plurality of second inputs receiving said plurality of clock control signals and said plurality of delayed clock control signals and an output providing a fifth clock having a frequency controlled by said frequency control voltage, said VCO including a programmable phase control circuit that dynamically adjusts phase of said fifth clock using said plurality of clock control signals and said plurality of delayed clock control signals; wherein said second clock is based on said fifth clock.