Patent ID: 7567073

Claim:
An interface circuit comprising: an output-side circuit that outputs a data signal and a data strobe signal which stipulates sampling timing of the data signal; and an input-side circuit that inputs a data signal and a data strobe signal; the interface circuit complying with predetermined specifications in which phase relationships between the data signal and the data strobe signal in the data output and input take on respective ones of prescribed relationships; wherein said output-side circuit includes: a first selector that receives as inputs a first phase shift amount signal which stipulates a phase shift amount when a normal mode is in effect and a second phase shift amount signal which stipulates a phase shift amount when a test mode is in effect, and selects the first phase shift amount signal when the normal mode is in effect and the second phase shift amount signal when the test mode is in effect; a first variable delay circuit that receives a clock signal and adds to the clock signal a delay conforming to the phase shift amount signal selected by said first selector to supply the resultant signal as a sampling clock signal; and an output-data sampling circuit that samples the data signal output responsive to the sampling clock signal from the first variable delay circuit; a signal obtained by phase-shifting the clock signal a fixed amount being output as the data strobe signal; and wherein said input-side circuit includes: a second selector that receives as inputs a third phase shift amount signal which stipulates a phase shift amount when a normal mode is in effect and a fourth phase shift amount signal which stipulates a phase shift amount when a test mode is in effect, and selects the third phase shift amount signal when the normal mode is in effect and the fourth phase shift amount signal when the test mode is in effect; a second variable delay circuit that receives the data strobe signal input thereto and adds to the data strobe signal a delay conforming to the phase shift amount signal selected by said second selector to supply the resultant signal as a sampling clock signal; and an input-data sampling circuit that samples the data signal input thereto responsive to the sampling clock signal from the second variable delay circuit.