Patent ID: 8217694

Claim:
A synchronous mirror delay (SMD) circuit, comprising: an input buffer; a data path model coupled to the input buffer; a forward delay line coupled to the data path model; a control circuit coupled to the forward delay line and coupled to the input buffer; and a backward delay line coupled to the control circuit and coupled to the input buffer; wherein the forward delay line and the backward delay lines each contain a plurality of serially-connected delay elements of differing unit time delay; wherein the control circuit is configured to reproduce a clock signal received at the input buffer by selectively adjusting a number of serially-connected delay elements utilized by the forward delay line and the backward delay line to accommodate a time period of the clock signal within each of the forward delay line and the backward delay line; wherein the forward delay line and the backward delay line each comprise a portion having a set of three serially-connected delay elements in which a first delay element of the set of three serially-connected delay elements has a first unit time delay, a second delay element of the set of three serially-connected delay elements has a second unit time delay and a third delay element of the set of three serially-connected delay elements has a third unit time delay; wherein the second delay element of the set of three-serially connected delay elements is interposed between the first and the third delay elements of the serially-connected delay elements in the forward delay line and in the backward delay line; and wherein a value of the second unit time delay is between a value of the first unit time delay and a value of the third unit time delay.