Patent ID: 7952406

Claim:
A delay locked loop circuit, comprising: a voltage level detection unit configured to detect a level of an external power source voltage; a phase comparison unit configured to compare a phase of a reference clock with a phase of a feedback clock; a clock delay unit configured to designate one of a first delay cell unit and a second delay cell unit as an initial delay cell unit and the other as a connected delay cell unit based on an output signal of the voltage level detection unit, delay the reference clock by the initial delay cell unit until a delay amount of the reference clock reaches a predetermined delay amount, delay the reference clock by the connected delay cell unit after the delay amount of the reference clock reaches the predetermined delay amount in response to an output signal of the phase comparison unit, and output a delay locked clock; and a delay duplication modeling unit configured to change the delay locked clock to reflect an actual delay condition of the reference clock and output the feedback clock.