Patent ID: 8458507

Claim:
A dual in line memory module comprising at least one dynamic random access memory (DRAM) module, said DRAM module comprising: clock divider circuitry configured to receive a clock input signal having a first frequency from a clock input receiver, said clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and said clock input signal, said output signal including a second frequency being a fraction of the first frequency and said inverted output signal based on said clock input signal; a multiplexer configured to receive said clock input signal and said output signal and to generate a multiplexed output; a receive clock tree configured to receive said multiplexed output; and a address/command/control bus configured to receive said multiplexed output and to reduce an operational frequency of said address/command/control bus in response to an increase in an operational frequency of a data bus associated with said dual in line memory module.