Patent ID: 8892969

Claim:
An apparatus comprising: a memory device having a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each erase block of the plurality of erase blocks identified by an erase block number unique within the respective erase block group and matching an erase block number of a corresponding erase block in at least one other erase block group of the plurality of erase block groups; and a mapping for storing at least one group address number corresponding to an erase block number identifying a non-defective erase block in the base erase block group and matching an erase block number identifying a defective erase block in at least one of the plurality of erase block groups other than the base erase block group, wherein the plurality of erase blocks are grouped into groups of erase blocks, the groups of erase blocks including a first remapped group, the first remapped group includes a non-defective erase block of the base erase block group and a non-defective erase block of a second erase block group among the plurality of erase block groups, the non-defective erase block of the base erase block group and the non-defective erase block of the second erase block group having different erase block numbers.