Patent ID: 6970521

Claim:
A data extracting circuit comprising: a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices; an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located; a clock selecting section for selecting one of outputs of the delay devices responsive to the edge detection signal; and a latch for receiving the output, selected by the selecting section, and the data signal as clock and data inputs, respectively, and for outputting read data; wherein the selecting section comprises: multiple switches provided for the respective delay devices, each said switch selectively delivering the output of associated one of the delay devices responsive to the edge detection signal; and an OR gate tree, in which a plurality of OR gates are connected together like a tree and which receives outputs of the switches.