Patent ID: 7240320

Claim:
A method of implementing a design on a programmable logic device comprising: compiling a first design of the programmable logic device, wherein the first design is implemented using a first set of programming frames; compiling a second design of the programmable logic device; and generating a second set of programming frames of a bit stream for the second design, wherein the second design is compiled to maximize the number of common programming frames in the first and second sets of programming frames, and wherein the number of common programming frames in the first and second sets of programming frames is maximized by: generating a database that identifies the correspondence between resources of the programmable logic device and programming frames of the programmable logic device that control the resources; identifying a first set of resources used in a first manner in the first design; reducing costs associated with using the first set of resources of the first design in the first manner; and applying the reduced costs associated with using the first set of resources of the first design in the first manner when compiling the second design.