Patent ID: 7519856

Claim:
A fault tolerant system including a plurality of systems constituted by the same computer hardware components, each of the systems comprising: a processor section that can operate in a lock-step synchronous state between own system and other system; an input/output section to be connected to the processor section; a controller to be connected between the processor section and input/output section; and a signal transmission path that connects the own system and other system through the controller, the controller comprising: state management means for managing a plurality of system operations for performing error processing, synchronization processing, and resynchronization processing for fault tolerant by associating a plurality of states corresponding to the system operations with predetermined event signals; and control means for selecting the plurality of system operations while changing the plurality of states for every system based on the event signals and allowing the processor section to perform selected system operation, wherein the plurality of states include: an online-system state corresponding to a state integrated into a system providing a service; an offline-system state corresponding to a state separated from a system providing a service; and a fault-system state corresponding to a state separated from a system providing a service due to error detection, wherein the online-system state includes: an online divide state corresponding to a state where the processor sections of the own and other systems operate in asynchronous state at power-on time; and an online ready state corresponding to a state where the processor sections of the own and other systems operate in asynchronous state, the offline-system state group includes: an offline divide state corresponding to a state where the processor sections of the own and other systems operate in asynchronous state at power-on time and constituting a pair with the online divide state; and an offline state corresponding to a state where the processor sections of the own and other systems operate in asynchronous state and constituting a pair with the online ready state.