Patent ID: 8832538

Claim:
A method of detecting data transmission errors in an Inter-Integrated Circuit (‘I 2 C’) system, the I 2 C system comprising an I 2 C source device, an I 2 C destination device, and a data transmission signal line coupling the I 2 C source device and the I 2 C destination device, the data transmission signal line configured to carry data transmission signals between the I 2 C source device and the I 2 C destination device, the method comprising: receiving, by the I 2 C destination device from the I 2 C source device, a data transmission signal, the data transmission signal encoded with a set of bits and comprising voltage alternating between a logic low voltage and a logic high voltage; detecting, by the I 2 C destination device, rise time of a preselected bit in the set of bits of the data transmission signal; if the detected rise time of the preselected bit is less than a predefined threshold, determining that the I 2 C source device injected a parity bit in the data transmission signal, and if the detected rise time of the preselected bit is not less than a predefined threshold, determining that the I 2 C source device did not inject a parity bit in the data transmission signal; and determining, by the I 2 C destination device, whether the data transmission signal includes an error in dependence upon the parity of the set of bits of the data transmission signal.