Patent ID: 8825464

Claim:
A method for conducting a power consumption simulation of an integrated circuit, the method comprising: dividing a serial power consumption simulation of the integrated circuit into a plurality of time segments based on a specified number of clock cycles by: performing a forward-progressing logic simulation of the integrated circuit; extracting first state information of a plurality of logic devices of the integrated circuit after the logic simulation is performed for a first time segment equal to the specified number of clock cycles; extracting second state information of the plurality of logic devices of the integrated circuit after the logic simulation is performed for a second time segment equal to the specified number of clock cycles; initializing a first representation of the plurality of logic devices of the integrated circuit according to the first extracted state information; initializing a second representation of the plurality of logic devices of the integrated circuit according to the second extracted state information; simulating power consumption of the first representation of the plurality of logic devices and the second representation of the logic devices simultaneously on a plurality of separate simulation benches; and aggregating results of simulations of the integrated circuit for the plurality of time segments.