Patent ID: 8482070

Claim:
An apparatus comprising an integrated circuit, said integrated circuit comprising a plurality of cells placed in a first row, said first row including a plurality of first cells, each including a first pMOS field effect transistor of UTBOX FDSOI technology including a first semiconductor ground plane lying beneath said first pMOS transistor, and a first semiconductor well having n-type doping lying beneath said first semiconductor ground plane and configured to apply an electrical potential to said first semiconductor ground plane, and a first nMOS field effect transistor of UTBOX FDSOI technology including a second semiconductor ground plane lying beneath said first nMOS transistor, and a second semiconductor well having p-type doping lying beneath said second semiconductor ground plane and configured to apply an electrical potential to said second semiconductor ground plane, and a plurality of second cells, each including a second pMOS field effect transistor of UTBOX FDSOI technology including a third semiconductor ground plane lying beneath said second pMOS transistor, and a third semiconductor well having p-type doping lying beneath said third semiconductor ground plane and configured to apply an electrical potential to said third semiconductor ground plane, and a second nMOS field effect transistor of UTBOX FDSOI technology including a fourth semiconductor ground plane lying beneath the second nMOS transistor, and a fourth semiconductor well having n-type doping lying beneath said fourth semiconductor ground plane and configured to apply an electrical potential to said fourth semiconductor ground plane, said first and second cells being placed so that pMOS transistors of first and second standard cells belonging to said first row are aligned along said first row, and a first transition cell including a fifth semiconductor well, wherein said first transition cell is contiguous with first and second standard cells of said first row so as to ensure electrical continuity with either one or the other of the n-doped first and fourth semiconductor wells or the p-doped second and third semiconductor wells of first and second standard cells.