Patent ID: 7073113

Claim:
An apparatus for adaptive sigma-delta modulation, comprising: (a) a summing junction for comparing an analog input signal x(n) to an encoding signal v(n) to generate an error signal e(n) representing a difference between the analog input signal x(n) and the encoding signal v(n); (b) a noise shaping filter for filtering the error signal e(n) to generate a signal p(n); (c) an absolute value block for generating an absolute value of the signal p(n); (d) a first one-bit quantizer for converting the signal p(n) into a binary output signal y(n); (e) an adapter for generating a scaling signal d(n) for scaling a step-size of the first one-bit quantizer using an estimation of the absolute value of the signal p(n), wherein the adapter comprises: (1) a summing junction for subtracting the scaling signal d(n) from the absolute value of the signal p(n) to generate an output signal; (2) a second one-bit quantizer for converting the output signal from the summing junction into a binary sequence signal q(n); (3) an integrator for integrating the binary sequence signal q(n); and (4) an exponential term block for converting the integrated binary sequence signal q(n) to the scaling signal d(n); and (f) a multiplier for multiplying the binary output signal y(n) by the scaling signal d(n) to generate the encoding signal v(n).