Patent ID: 7034724

Claim:
A training circuit of a digital-analog converter, comprising: a digital-analog converter, comprising a plurality of capacitance-correcting circuits; a sampling/holding switching circuit coupled to the digital-analog converter to sample and hold an voltage outputted from the digital-analog converter; a comparator, having two input terminals coupled to output terminals of the sampling/holding switching circuit respectively to compare the voltage outputted from the digital-analog converter with a next voltage so as to output a comparison signal; a counter coupled to the comparator and the digital-analog converter to receive the comparison signal outputted from the comparator, according to the comparison signal, generating a counting value to the digital-analog converter, wherein when the comparison signal is at a first level, 1 is added to the counting value so that the digital-analog converter outputs the voltage accordingly, and when the comparison signal is at a second level, the countcr stops; a selector coupled to the comparator to receive the comparison signal, and coupled to the counter to receive a selecting signal, wherein when the comparison signal is at the second level, the selector is enabled; and a plurality of capacitance-correcting counters coupled to the selector, the counter and the digital-analog converter respectively, corresponding to the capacitance-correcting circuits, wherein when the comparison signal is at the second level, the selector selects one of the capacitance-correcting counters to correct a capacitance-correcting circuit corresponding thereto according to the selecting signal, and when the comparison signal is at the first level, the selected capacitance-correcting counter stops and 1 is added to the counting value of the counter.