Patent ID: 8367503

Claim:
A method of manufacturing a semiconductor device including a first group of transistors, and a second group of transistors each of which is lower in operating voltage than each of said transistors in said first group, said first group of transistors and said second group of transistors being formed on a semiconductor substrate, each of said transistors in said first group having a first gate electrode formed on said semiconductor substrate through corresponding one of first gate insulating films, and a silicide layer formed on corresponding one of said first gate electrodes, each of said transistors in said second group having a second gate electrode formed in a trench for gate formation, formed in an insulating film above said semiconductor substrate, through corresponding one of second gate insulating films, said manufacturing method comprising the steps of: forming a protective film for covering said silicide layer after said silicide layer is formed on each of said first gate electrodes of said first group of transistors; and forming said second gate electrodes in said trenches for gate formation through said second gate insulating films, respectively; forming a gate having said first gate insulating film, said first gate electrode, and a hard mask laminated in order in each of said first region in which said first group of transistors is formed, and said second region in which said second group of transistors is formed on said semiconductor substrate; forming a first source/drain region of each of said transistors in said first group in said first region of said semiconductor substrate, and forming a second source/drain region of each of said transistors in said second group in said second region of said semiconductor substrate; planarizing a surface of said insulating film at the same time that said hard mask of each of said gates is exposed after said insulating film is formed so as to cover each of said gates in said first region and said second region; removing said hard mask of each of said gates in said first region; forming said silicide layer on each of upper surfaces of said first gate electrodes in said first region; forming said protective film for covering said silicide layer on said insulating film in said first region; forming trenches for gate formation in said insulating film by removing said gates in said second region; and filling a conductive material in each of said trenches for gate formation to form each of said second gate electrodes after said second gate insulating film is formed in each of said trenches for gate formation.