Patent ID: 6901489

Claim:
An apparatus comprising: a cache memory; a sequencer; and a set of application engines in communication with said sequencer, wherein said set of application engines includes a streaming input engine including: a fetch engine including a memory opcode output in communication with said cache memory and a memory address output in communication with said cache memory; an alignment circuit including: a data buffer in communication with said cache memory and adapted to store data accessed in said cache memory by said fetch engine, a register coupled to receive data from said data buffer, a byte selector coupled to receive data from said data buffer and data from said register, wherein said byte selector is adapted to provide selected data, wherein said byte selector selects said selected data from said data from said data buffer and said data from said register, and a shifter coupled to receive said selected data from said byte selector and adapted to provide shifted data, wherein said shifter provides said shifted data by shifting a number of bytes from said selected data onto an output, and an output register coupled to said alignment circuit to receive said shifted data.