Patent ID: 6874053

Claim:
A shared memory multiprocessor comprising: a plurality of nodes each configured with at least one of a processor having a cache memory, a memory device and an I/O device; and an inter-node connection network for interconnecting a plurality of said nodes; wherein at least one of a plurality of said nodes includes at least two of said processor, said memory device and said I/O device, and the plurality of said nodes include at least one said processor, at least one said memory device and at least one said I/O device, wherein each of said nodes includes an information adding unit for adding, to a memory access request or an I/O access request issued by said processor or said I/O device in a respective local node, node information indicating a node constituting a destination of transfer of the access request, and a transfer unit for selectively transferring the access request to said inter-node connection network in accordance with the node information added to the access request, and wherein said inter-node connection network transfers said access request to the node indicated by the node information added to said access request.