Patent ID: 6933762

Claim:
A DC offset cancellation circuit for being inserted between a pair of differential output terminals and a pair of differential input terminals of a differential amplification circuit that amplifies a pair of differential input signals inputted to the differential input terminals thereof and outputs a pair of differential output signals from the differential output terminals thereof, and which cancels a DC offset voltage between the differential output signals, comprising: a low-pass filter that performs low-pass filtration on the differential output signals inputted thereto so as to output a filtered signal; a mixing circuit that outputs a pair of mixed differential input signals, which are generated by mixing the filtered signal into the differential input signals such that a negative feedback is performed, to the differential input terminals of the differential amplification circuit; and a characteristics changing circuit that changes a cutoff frequency and a slew rate of the low-pass filter; wherein the characteristics changing circuit is a characteristics changeover circuit that performs changeover either to a first state in which the cutoff frequency of the low-pass filter is a first cutoff frequency fc 1 and the stew rate thereof is a first slew rate SR 1 , or to a second state in which the cutoff frequency of the low-pass filter is a second cutoff frequency fc 2 and the slew rate thereof is a second slew rate SR 2 ; the DC offset cancellation circuit comprises a characteristics changeover instruction circuit that, when the differential input signals are a pair of pulse differentiated differential input signals obtained by subjecting a base pulse signal of a generally square wave shape to differentiation or high-pass filtration, outputs a characteristics changeover pulse signal giving an instruction for changeover to the first state at a first timing at which the base pulse signal falls and a characteristics changeover pulse signal giving an instruction for changeover to the second state at a second timing at which the base pulse signal rises; and the characteristics changeover circuit is configured so as to change the state of the low-pass filter from the second state to the first state at the first timing and to change the state of the low-pass filter from the first state to the second state at the second timing according to the inputted characteristics changeover pulse signal.