Patent ID: 8569160

Claim:
A method for device fabrication, comprising: providing a base wafer as part of a front-end-of-the-line (FEOL) circuitry fabrication process; forming active circuitry on a plurality of FEOL circuitry die on the base wafer, the FEOL circuitry fabrication process operative to configure each FEOL circuitry die for subsequent electrical coupling with one or more layers of memory to be fabricated directly above each FEOL circuitry die; forming the one or more layers of memory directly on top of each FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process, the forming including electrically coupling a portion of the active circuitry in each FEOL circuitry die with the one or more layers of memory that are formed directly above each FEOL circuitry die.