Patent ID: 6970020

Claim:
A phase detector for providing an UP control signal and a DOWN control signal in a high-speed loop circuit based on relative alignment between a full-rate data signal and a clock signal derived by said loop circuit, said phase detector comprising: circuitry for deriving a half-rate quadrature clock from said derived clock signal; circuitry for comparing a first quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first portion of said UP control signal; circuitry for comparing a second quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second portion of said UP control signal; circuitry for comparing a third quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first portion of said DOWN control signal; circuitry for comparing a fourth quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second portion of said DOWN control signal; circuitry for combining said first and second portions of said UP control signal into a single UP control signal; and circuitry for combining said first and second portions of said DOWN control signal into a single DOWN control signal.