Patent ID: 6861724

Claim:
A semiconductor integrated circuit including an interface circuit which receives a relatively high first voltage and a relatively low second voltage as power supply voltages, and suspends operation of the interface circuit in a non-access mode so that an external access is not executed by shutting off supply of the first voltage to be applied to the interface circuit that receives an externally supplied signal, the interface circuit comprising: an input buffer that operates by applying at least the first voltage as the power supply voltage; a transfer gate that is coupled to and between an external input terminal and an input end of the input buffer, and that transmits an external signal input from the external input terminal to the input end of the input buffer; and a gate voltage control circuit that outputs a gate voltage to be applied to a gate electrode of the transfer gate, the gate voltage control circuit outputting a voltage produced based on the first voltage as the gate voltage in an access mode so that an external access is executed while outputting a voltage produced based on the second voltage as the gate voltage in the non-access mode.