Patent ID: 8203549

Claim:
A plasma display panel driving method for driving a plasma display panel which includes a plurality of scan electrodes extending in a first direction and a plurality of address electrodes extending in a second direction orthogonal to the first direction in which a negative polarity scan pulse is applied to one of the scan electrodes and a positive polarity address pulse is applied to one of the address electrodes from an address electrode driving circuit to generate an address, wherein: the positive polarity address pulse is generated by using a charge sharing system, in which before clamping the one of the address electrodes at a predetermined high voltage or a predetermined low voltage, an averaged voltage generated by short-circuiting the plural address electrodes and thereby averaging electric charges remaining in the plural address electrodes is applied to the one of the address electrodes; a falling time of the address pulse falling from the averaged voltage to the predetermined low voltage as a result of the clamping is longer than a rising time of the address pulse rising from the averaged voltage to the predetermined high voltage as a result of the clamping; the rising time is shorter than a charge sharing rise time of the address pulse from the predetermined low voltage to the averaged voltage; the falling time is longer than a charge sharing fall time of the address pulse from the predetermined high voltage to the averaged voltage; and clamping of the one of the address electrodes at the predetermined low voltage starts after the scan pulse applied to the one of the scan electrodes falls to a lower voltage and after the scan pulse applied to another one of the scan electrodes rises to a higher voltage.