Patent ID: 7973383

Claim:
A semiconductor integrated circuit device comprising: a first conductivity type semiconductor substrate; a first conductivity type semiconductor layer provided on said first conductivity semiconductor substrate, said first conductivity type semiconductor layer being coupled to a first power supply; a device forming portion provided on an upper surface of said first conductivity type semiconductor layer and including a second conductivity type well connected to a second power supply, and a first conductivity type well, wherein the entirety of said device forming portion is provided on the upper surface of said first conductivity type semiconductor layer, said device forming portion having a bottom surface contacting with said upper surface of said first conductivity type semiconductor layer, said upper surface of said first conductivity type semiconductor layer being substantially flat, and wherein a first device is formed within a region of the device forming ortion including the first conductivity type well and a second device is formed within a region of the device forming portion including the second conductivity type well; and a decoupling capacitor formed at an interface between said first conductivity type semiconductor layer and said second conductivity type well.