Patent ID: 8492218

Claim:
A method of fabricating a semiconductor structure, comprising: forming a first liner over a first portion of a semiconductor substrate; forming a second liner over a second portion of said semiconductor substrate, wherein said second liner overlies said first liner; depositing a masking layer over said first liner and said second liner; forming a sidewall of said masking layer above a top surface of a peripheral portion of said first liner by patterning said masking layer; removing portions of said second liner that are not covered by said patterned masking layer; and laterally recessing said second liner from underneath said patterned masking layer, causing a peripheral portion of said second liner to be removed from above said peripheral portion of said first liner, wherein the peripheral portion of said first liner is present on a gate structure that is located on an isolation region separating the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.