Patent ID: 8677306

Claim:
A microcontroller controlled network-fabric in a Structured ASIC comprising: a core comprising memory cells and logic cells in a Structured ASC having via-configurable interconnections; a Tester, wherein the Tester is a microprocessor; a network-aware IO comprising a routing fabric connected to the Tester and operatively connecting the Tester to the core, the network-aware IO set up into a static routing bus under the control of the Tester wherein the network-aware IO comprises a plurality of network agents; the network agents arranged by the microprocessor to form at least one signal circuit path forming a network operatively connecting the microprocessor to the core; the microprocessor controlling the state of the network agents to determine whether the agents can pass data and establish the signal circuit path from the microprocessor to the core, for purposes of testing the core; wherein the plurality of network agents under the control of the microprocessor; and, the Structured ASIC is configured through the via-configurable interconnections in the Structured ASIC.