Patent ID: 6882011

Claim:
An electrostatic discharge (ESD) protection device having reduced trigger voltage, comprising: a substrate of first conductivity type; a first MOS transistor of second conductivity type disposed on said substrate, said first MOS transistor comprising a first gate, a first gate dielectric disposed under said first gate, a first heavily doped region of said second conductivity type implanted into said substrate at one side of said first gate, and a second heavily doped region of said second conductivity type implanted into said substrate at the other side of said first gate; a second MOS transistor of said second conductivity type laterally disposed on said substrate in proximity to said first MOS transistor, said second MOS transistor comprising a second gate, a second gate dielectric disposed under said second gate, a third heavily doped region of said second conductivity type implanted into said substrate at one side of said second gate, and a fourth heavily doped region of said second conductivity type implanted into said substrate at the other side of said second gate; and at least one floating gate MOS transistor comprising a floating gate dielectric formed on said substrate and a floating gate overlying said floating gate dielectric, said floating gate MOS transistor being located between said first MOS transistor and said second MOS transistor, wherein said floating gate MOS transistor is serially connected to said first MOS transistor via said second heavily doped region and is connected to said second MOS transistor via said third heavily doped region.