Patent ID: 8239732

Claim:
A system that facilitates error correction of data in a non-volatile memory, comprising: an error correction code (ECC) component that generates at least one parity bit comprising a value based on a first set of data being written to a portion of the non-volatile memory, wherein the portion of the non-volatile memory comprises a second set of data stored thereon that is in addition to the first set of data; an evaluation component that analyzes at least one of the second set of data, a stored parity code associated with the second set of data, and a stored indicator data associated with the second set of data, wherein the stored parity code and the stored indicator data are located in the portion of the non-volatile memory; an indicator component that sets an indicator data associated with the first set of data as a function of the at least one parity bit and the analysis performed by the evaluation component; and a controller component that, when the first set of data is being read from the non-volatile memory, facilitates enabling or disabling error correction of the first set of data based on the indicator data and communicates, to other system components, information related to an error detection and correction status of the first set of data; wherein the non-volatile memory includes a plurality of memory locations, wherein at least one of data, a parity code, or indicator data, or a combination thereof, is written to, read from, or stored in, at least one memory location of the plurality of the memory locations.