Patent ID: 6985394

Claim:
A semiconductor memory device having a memory cell array region and a peripheral circuit region separate from the memory cell array region, the semiconductor memory device comprises: a plurality of memory cells; a pair of bit lines which is coupled respectively to a pair of memory cells of the plurality of memory cells; a pair of local input/output lines which is coupled to the pair of bit lines via a first switching circuit; a pair of global input/output lines which is coupled to the pair of local input/output lines via a second switching circuit; an input/output line sense amplifier, coupled to the pair of global input/output lines, for sensing and amplifying data of the pair of global input/output lines and outputting the amplified data; and a plurality of first precharge circuits, disposed between the second switching circuit and the input/output line sense amplifier and coupled to the pair of global input/output lines, for precharging the pair of global input/output lines in response to a first precharge control signal, wherein the plurality of memory cells, the pair of bit lines, the pair of local input/output lines, the pair of global input/output lines, and the plurality of first precharge circuits are located in the memory cell array region, and wherein the input/output line sense amplifier is located in the peripheral circuit region.