Patent ID: 7307905

Claim:
A sense amplifier for coupling with an asymmetric SRAM cell that provides faster access times when the asymmetric SRAM cell stores a first predetermined binary value, said sense amplifier comprised of: a first pair of cross coupled inverters across a bitline (BL) and a bitline bar (BLB); a second pair of cross coupled inverters operably coupled with the first pair of cross coupled inverters; a plurality of additional transistors forming a dummy column of cells that store a second predetermined binary value at all times wherein during a read operation of the SRAM cell one of the dummy cells will have its wordline asserted, said dummy column of cells operably coupled with the first pair of cross coupled inverters; and four inputs operably coupled with a subset of transistors of the sense amplifier wherein the inputs include the BL, the BLB that derive from the SRAM cell, a dummy bit line (D), and a dummy bitline bar (DB) that are input to the dummy cells such that D is input to the sense amplifier on the same side as BLB while DB is input to the sense amplifier on the same side as BL.