Patent ID: 8455349

Claim:
A method of manufacturing at least one layered chip package, the at least one layered chip package comprising: a main body that includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions; and a plurality of through electrodes that are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions, wherein: each of the plurality of layer portions includes a semiconductor chip as its principal part; and at least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes, the method comprising the steps of: fabricating a substructure that includes the main body of the at least one layered chip package, the step of fabricating the substructure including the steps of: fabricating an initial substructure which will become the substructure after the formation of the plurality of through holes, the initial substructure including a plurality of initial layer portions which will become the plurality of layer portions after the formation of the plurality of through holes, each of the plurality of initial layer portions including the semiconductor chip, a plurality of insulator fill holes and insulating layers, the plurality of insulator fill holes being formed in the semiconductor chip to penetrate the semiconductor chip, the insulating layers being made of an insulator and filling the respective insulator fill holes, and forming the plurality of through holes in the initial substructure so that the initial substructure becomes the substructure, the plurality of through holes being formed to penetrate the insulating layers of the plurality of initial layer portions, and forming the plurality of through electrodes in the plurality of through holes in the main body of the substructure.