Patent ID: 8539167

Claim:
A shared memory device comprising: a plurality of processor elements; a plurality of memory modules configured to be accessible by said plurality of processor elements wherein the plurality of memory modules includes intervening even and odd memory modules; a partially overlapped multi-port connection device configured to enable a specific processor element out of said plurality of processor elements to access a specific memory module out of said plurality of memory modules and configured to enable a processor element other than said specific processor element, from said plurality of processor elements, to access other memory modules out of said plurality of memory modules, such that the partially overlapped multi-port connection device partially shares and accesses said specific memory module and other memory modules out of said plurality of memory modules; wherein said plurality of processor elements are allowed to access via said connection device a plurality of memory systems such that each memory system is constituted by at least one shared memory module from the plurality of memory modules, wherein each of the shared memory modules from the plurality of memory modules is configured to be utilized separately by multiple memory systems of the plurality of memory systems, and wherein each memory system is configured such that the shared memory module contains at least one even memory module and at least one odd memory module; an arbitration circuit configured to prioritize and grant simultaneous requests from the plurality of processor elements and a controller to access any one of the plurality of memory modules based on a round-robin prioritized order; and a controller configured to communicate with an external entity and to control access to said plurality of memory modules, wherein said controller can access all memory modules from the plurality of memory modules via said connection device, and wherein said controller controls access to said plurality of memory devices by sending a request to transfer data to the arbitration circuit, waiting to receive a permission to transfer data from the arbitration circuit, and communicating with the external entity to perform data transfer after receiving the permission to transfer data from the arbitration circuit.