Patent ID: 7093084

Claim:
Shift register circuitry comprising: random access memory circuitry including a two-dimensional array of intersecting rows and columns of memory cells; input circuitry associated with each of the columns for conveying data in parallel to all of the cells in the associated column; output circuitry associated with each of the columns for conveying data from the associated column; write counter circuitry for selecting a each of the rows, one after another, in a repeating series for writing data into the memory cells in the selected row, the data that is written into each memory cell in the selected row being the data that is then being conveyed in parallel to all of the cells in the column that includes that cell by the input circuitry associated with that column; read counter circuitry for selecting each of the rows, one after another, in the repeating series for reading data from the memory cells in the selected row, the data that is read from each memory cell in the selected row being applied to the output circuitry associated with the column that includes that cell, the read counter circuitry being maintained in the series ahead of where the write counter circuitry is in the series; and a feedback connection from the output circuitry associated with at least one of the columns to the input circuitry associated with a different one of the columns.