Patent ID: 7825738

Claim:
A method for signal processing, the method comprising: in a reference generator, increasing a frequency of an input reference signal utilized by a phase-frequency detector (PFD) in a fractional-N phase-locked-loop (PLL) synthesizer comprising said reference generator, said PFD, a charge pump, a divider, a voltage controlled oscillator (VCO), and a loop filter; generating an enable signal for said PFD utilizing said increased frequency input reference signal; generating a single signal for controlling said charge pump utilizing said increased frequency input reference signal and a divider signal generated by said divider whose input frequency is substantially the same as that of a VCO signal generated by said fractional-N PLL synthesizer, wherein said single signal enables a switched charge up portion of said charge pump to charge said loop filter and wherein said loop filter is discharged by an unswitched leakage current in said charge pump that is independent of said single signal; and generating said VCO signal based on a filtered output of said controlled charge pump, wherein said filtered output is generated by said loop filter.