Patent ID: 8738978

Claim:
An integrated circuit comprising: scan test circuitry; and additional circuitry subject to testing utilizing the scan test circuitry; the additional circuitry comprising at least first and second circuitry cores; the scan test circuitry comprising a plurality of scan chains, including at least one wrapper cell scan chain arranged between the first and second circuitry cores, the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation; wherein at least one of the wrapper cells of the wrapper cell scan chain comprises: a flip-flop having a data input and a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores; and a multiplexer having a functional path input, a scan shift input and an output; and wherein the output of the multiplexer is coupled to the data input of the flip-flop and to a functional path input of the second circuitry core.