Patent ID: 7843214

Claim:
A semiconductor integrated circuit device, comprising: a first power supply wiring which receives a first voltage supply; a second power supply wiring, which receives a second voltage supply and is laid in parallel to the first power supply wiring; a plurality of standard cells provided in a substantially rectangular area having two sides that are a part of the first power supply wiring and a part of the second power supply wiring; and at least one transistor resistance area provided in the rectangular area, wherein each of the standard cells includes: a first well of a first conductivity provided along the first power supply wiring; a second well of a second conductivity provided along the second power supply wiring and between the first well and the second power supply wiring; a first-conductivity MOS transistor provided in the second well; and a second-conductivity MOS transistor provided in the first well, wherein the transistor resistance area includes: a third well of the first or second conductivity, having a substantially rectangular shape including two sides that are a portion of the first power supply wiring and a portion of the second power supply wiring; and a plurality of MOS transistor resistances each having a conductivity opposite to that of the third well, and wherein the plurality of MOS transistor resistances are arranged so that a number of MOS transistor resistances among the plurality of MOS transistor resistances are connected to each other serially, in parallel, or in a combination of serial and parallel connections between the first-conductivity MOS transistor and the second-conductivity MOS transistor.