Patent ID: 7788625

Claim:
A computer-implemented method comprising: automatically generating a design for each of a plurality of prototype systems-on-chip, wherein each prototype system-on-chip has a different architecture comprising a unique combination of at least one master coupled to at least one slave through a bus, wherein each architecture is configured for implementation within a single chip and is determined by automatically generating permutations of at least one of a number of masters, a number of buses, or a number of slaves subject to permutation constraints limiting a total number of masters, slaves, and buses in each automatically generated architecture, wherein each design is a programmatic representation of a circuit; analyzing the design for each of the plurality of prototype systems-on-chip using at least one electronic design automation (EDA) tool; extracting data from results of the analyzing the design for each of the plurality of prototype systems-on-chip, wherein the data describes at least one characteristic of each design for the plurality of prototype systems-on-chip comprising bus transaction timing information; storing the data for each of the plurality of designs for prototype systems-on-chip, the designs, and a description of the architecture for each of the plurality of prototype systems-on-chip within a memory as a selectable, prototype system-on-chip option; selecting a prototype system-on-chip option from the plurality of prototype systems-on-chip options according to the stored data comprising bus transaction timing information; and generating a user-design using the architecture of the selected prototype system-on-chip option, wherein the user-design comprises the unique combination of at least one master coupled to at least one slave through a bus as specified by the selected prototype system-on-chip option.