Patent ID: 8643579

Claim:
An array substrate comprising: a gate line including a plurality of sub lines receiving a same gate signal; a plurality of data lines crossing the gate line; a plurality of pixel electrodes, each of the pixel electrodes being disposed between two adjacent sub lines; a first thin film transistor electrically connected to a first sub line, a first pixel electrode, and a first data line; a second thin film transistor electrically connected to a second sub line, the first pixel electrode, and the first data line; a third thin film transistor electrically connected to the second sub line, a second pixel electrode, and a second data line; a fourth thin film transistor electrically connected to a third sub line, the second pixel electrode, and the second data line; a fifth thin film transistor electrically connected to the third sub line, a third pixel electrode, and a third data line; and a sixth thin film transistor electrically connected to a fourth sub line, the third pixel electrode, and the third data line, wherein the first and second thin film transistors each connected to the first pixel electrode and the first data line are simultaneously driven to increase a charging rate of the first pixel electrode, the third and forth thin film transistors each connected to the second pixel electrode and the second data line are simultaneously driven to increase a charging rate of the second pixel electrode, and the fifth and sixth thin film transistors each connected to the third pixel electrode and the third data line are simultaneously driven to increase a charging rate of the third pixel electrode.