Patent ID: 8583850

Claim:
An integrated circuit comprising: a first bus configured to convey signals in a first direction along a first axis; a second bus configured to convey signals in a second direction along the first axis, wherein the second direction is opposite the first direction, wherein signal lines of equal bit significance of the first bus and the second bus are arranged adjacent to each other; a third bus configured to convey signals in a third direction along a second axis, wherein the second axis is perpendicular to the first axis; a fourth bus configured convey signals in a fourth direction along the second axis, wherein the fourth direction is opposite of the third direction, wherein signal lines of equal bit significance of the third bus and the fourth bus are arranged adjacent to each other, wherein each of the first, second, third and fourth buses are N bits wide, and wherein each of the first, second, third, and fourth buses are unidirectional buses; and a crossbar unit having N crossbar switching circuits, wherein each of the N crossbar switching circuits is configured to couple a selected signal line of one of the buses to a corresponding selected signal line of another one of the buses.