Patent ID: 8392871

Claim:
A method of creating multiple mask designs used in a multiple exposure lithographic patterning process, each of said mask design including a plurality number shapes, the mask design being used for printing a design layout on a semiconductor wafer, the method comprising: a) using a computer, creating a first set of tolerance bands (TBs) for each edge of each shape in the design layout, said first set of TBs defining inner and outer tolerance of edge locations of the printed edges; b) dividing said edges of each shape in the design layout and said first set of TBs to create a plurality of sets of design edges and a plurality of sets of TBs, with one set of each plurality of sets of design edges and plurality of sets of TBs created for each mask in a multiple exposure lithographic patterning process; and c) applying the plurality of sets of TBs to create a plurality of mask designs which when printed in said multiple exposure lithographic patterning process result in wafer shapes having edges printed within the inner and outer tolerance of the design layout defined by said first set of TBs.