Patent ID: 8704565

Claim:
A lock detection circuit mounted in a DLL circuit, the DLL circuit including: a reference clock signal generation circuit configured to generate a reference clock signal from a pulse width modulation signal generated by pulse width modulation of digital data, a period of the reference clock signal being twice a period of the pulse width modulation signal, a phase of the reference clock signal being equal to a phase of the pulse width modulation signal; a delay circuit including a delay line configured to output an input signal after delaying the input signal by a prescribed delay amount, a plurality of stages of the delay lines being connected in series, the reference clock signal being input to the delay line of a first stage; a phase comparison circuit configured to output a first control signal, the reference clock signal and an output signal of the delay line of a final stage being input to the phase comparison circuit; and a charge pump configured to output a second control signal to the delay lines to control the delay amount based on the first control signal, the phase comparison circuit being configured to output the first control signal to reduce the delay amount when an OVER signal is input, output the first control signal to increase the delay amount when an UNDER signal is input, and output the first control signal to match a phase of the output signal of the delay line of the final stage to the phase of the reference clock signal when the OVER signal and the UNDER signal are not input, the DLL circuit being configured to output at least a portion of the output signals of the delay lines, the lock detection circuit comprising: an OVER signal generation circuit configured to determine whether or not a delay amount of the entire delay circuit is not less than an OVER threshold based on the output signals of the delay lines and send the OVER signal when the delay amount of the entire delay circuit is not less than the OVER threshold; an UNDER signal generation circuit configured determine whether or not the delay amount of the entire delay circuit is not more than an UNDER threshold based on the output signals of the delay lines and send the UNDER signal when the delay amount of the entire delay circuit is not more than the UNDER threshold; and an initial state response circuit configured to output a third control signal to the delay lines and cause the charge pump to stop the output of the second control signal when the pulse width modulation signal is not input, the third control signal controlling the delay amount to cause the delay amount of the entire delay circuit to be within one of a range in which the OVER signal generation circuit is operable, a range in which the UNDER signal generation circuit is operable, and a range that is greater than the UNDER threshold and less than the OVER threshold.