Patent ID: 8782589

Claim:
A method of stabilizing placement of a logic path in an integrated circuit design comprising: receiving a circuit description of the integrated circuit design having a plurality of cells interconnected to form a plurality of original nets wherein the original nets include an input net of the logic path and an output net of the logic path in a preliminary layout, by executing first instructions in a computer system; designating the logic path as a region for which placement stability is desired, by executing second instructions in the computer system; inserting in the circuit description at least first and second virtual pins wherein the first virtual pin has a first fixed location proximate the input net and is interconnected with the input net and the second virtual pin has a second fixed location proximate the output net and is interconnected with the output net, by executing third instructions in the computer system; optimizing placement of the cells while maintaining the first virtual pin at the first fixed location and maintaining the second virtual pin at the second fixed location to constrain the logic path, by executing fourth instructions in the computer system; and after said optimizing, removing all of the virtual pins from the circuit description, by executing fifth instructions in the computer system.