Patent ID: 8477768

Claim:
Data transfer system for transferring data signals between a system input and a system output, said system comprising: a first data consuming set, designed to receive said data signals from said system input, to write said data signals in said first data consuming set, and to read said data signals from said first data consuming set for sending said data signals towards a second data consuming set, said second data consuming set, designed to receive said data signals from said first data consuming set, to write said data signals in said second data consuming set, and to read said data signals from said second data consuming set for sending said data signals to said system output, and transfer means for transferring said data signals from said first data consuming set to said second data consuming set, wherein said first data consuming set comprises a first FIFO memory storing said data signals for delaying the writing in said second data consuming set of said data signals read from said first data consuming set and said first data consuming set comprises a first Low Voltage Differential Signaling cell placed at the output of the first FIFO memory; said second data consuming set comprises a second FIFO memory storing said data signals for further delaying the writing in said second data consuming set of said data signals read from said first data consuming set, and a second Low Voltage Differential Signaling cell placed at the input of the second FIFO memory; and said first data consuming set is designed to insert with said data signals to be transmitted to said second data consuming set a read request signal, said read request signal is a single bit signal which when set to ‘1’ triggers the reading of said data signals in said first FIFO memory, said transfer means are designed to carry said read request signal with said data signals through the first and second Low Voltage Differential Signaling cells, and said second data consuming set is designed to receive said read request signal which when set to ‘1’ triggers the writing of said data signals in said second FIFO memory; wherein said first data consuming set is designed to exploit a same first clock for writing said data signals in said first FIFO memory and for reading said data signals from said first FIFO memory, while said second data consuming set is designed to exploit a second writing clock for writing said data signals in said second FIFO memory and a second reading clock for reading said data signals from said second FIFO memory.