Patent ID: 7086029

Claim:
A processor-implemented method for implementing a circuit design, comprising: assigning portions of a first version of a circuit design to a plurality of areas of an integrated circuit, wherein each portion is assigned to one of the areas; generating respective netlists for the portions of the first version of the circuit design; implementing the first version of the circuit from the netlists; inputting netlists representing a second version of the circuit design, wherein portions of the second version of the circuit design correspond to the portions of the first version and are assigned to areas of the integrated circuit to which the portions of the first version are assigned; for each of the plurality of areas, comparing a first netlist of a portion of the first version of the circuit design assigned to the area to a corresponding second netlist of the portion of the second version of the circuit design; implementing, in place of an implementation of the first netlist, the second netlist of the second version of the design in response to the second netlist being not equal to the first netlist; and bypassing implementing the second netlist in response to the second netlist being equal to the first netlist.