Patent ID: 7895550

Claim:
A processor-based method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process, the method comprising the steps of: using the processor, characterizing the given process to form a mathematical model that, associates changes in polysilicon density and active density in a design for the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property, laying out the integrated circuit design with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors, dividing the integrated circuit design into virtual portions, for at least a given one of the portions of the integrated circuit design, measuring the polysilicon density and the active density of the portion, determining whether an adjustment to at least one of the gate length and the gate width will reduce variation in the desired property between the transistors in the portion of the integrated circuit design, using the processor, for at least one of the transistors in the given portion of the integrated circuit design, selectively adjusting at least one of the gate length and the gate width of the transistor according to the mathematical model based on at least one of the polysilicon density and the active density of the portion, to reduce variation in the desired property between the transistors in the integrated circuit design, and fixing the integrated circuit design into a non-transitory medium.