Patent ID: 7493476

Claim:
A processor, comprising: decode logic coupled to an instruction cache; a micro-sequence vector table coupled to the decode logic, wherein the micro-sequence vector table comprises an entry for each bytecode in an instruction set of the processor; and a register coupled to said decode logic, wherein the register is dedicated for storage of an immediate operand of a bytecode, wherein the decode logic is configured to: obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache, use the single bytecode to locate an entry corresponding to the single bytecode in the micro-sequence vector table, wherein a size of the immediate operand is indicated by bits in the entry, and when indicated by information in the entry, obtain the immediate operand from the instruction cache and store the immediate operand in the register for use by a micro-sequence that is executed in lieu of the single bytecode, wherein the information in the entry comprises an indicator set to indicate that the micro-sequence is to be executed in lieu of the single bytecode and an indicator set to indicate that the immediate operand is to be obtained.