Patent ID: 7955952

Claim:
A method, comprising: (a) for each integrated circuit chip of an array of integrated circuit chips on a semiconductor substrate, forming proximate to respective perimeters of each integrated circuit chip respective continuous first stress rings, respective edges of said respective first stress rings parallel to respective edges of said integrated circuit chips; after (a), (b) for each integrated circuit chip of said array of integrated circuit chips, forming respective continuous second stress rings between respective first stress rings and respective perimeters of said integrated circuit chips, respective edges of respective second stress rings parallel to respective edges of said integrated circuit chips, said first and second stress rings having opposite internal stresses; after (b), (c) for each integrated circuit chip of said array of integrated circuit chips, forming respective continuous gaps between respective first stress rings and respective second stress rings; after (c), (d) for each integrated circuit chip of said array of integrated circuit chips, forming a respective set of wiring levels from a first wiring level to a last wiring level on said substrate; and after (d), (e) dicing said array of integrated circuit chips into individual integrated circuit chips.