Patent ID: 7363408

Claim:
An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said interrupt control system comprising: an interruption message generator for decoding and identifying a message signaled interrupt (MSI) issued by said first peripheral device or said second peripheral device when interruption is to be conducted, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); a stop clock control module coupled to said interruption message generator and said CPU and de-asserting a stop clock signal that is previously asserted to have said CPU enter a power-saving state to have said CPU deactivate said power-saving state in response to said interruption status indicating message; and an interruption status indicating path for transmitting said interruption status indicating message.