Patent ID: 7426710

Claim:
A method for automatic design of a large scale circuit, the method comprising: providing a cell library comprising a plurality of cells providing a plurality of cell function; wherein said plurality of cell functions includes at least one clock-related function; wherein each of said plurality of cell functions has a corresponding nominal cell function load; wherein each of said plurality of cell functions is provided by three or more of said cells, each having a drive strength and a delay at said nominal cell function load depending on said drive strength; wherein said delays are substantially equal to a set of predetermined design delays for each of said plurality of cell functions; wherein a design delay spacing is defined for each pair of said cells performing the same one of said cell functions and having adjacent delays by taking a difference of the delays of the two cells of said pair; wherein the design delay spacings corresponding to at least one of said plurality of cell functions do not decrease as drive strength increases; and performing a circuit design by selecting cells from said cell library according to said plurality of cell functions and said cell drive strengths.