Patent ID: 7793176

Claim:
A method of fault-testing a logic circuit of an integrated circuit, wherein the logic circuit includes: 1) a plurality of logic gates, 2) a plurality of circuit nodes connecting together ones of the plurality of logic gates, 3) a plurality of primary inputs, and 4) a plurality of primary outputs, the method comprising: Setting a termination criterion for terminating fault testing, Selecting a node from among the plurality of nodes; back-tracing a faulty behavior being tested from the node to a selected one of the primary inputs along a first path that traverses through the plurality of circuit nodes to the selected one of the plurality of primary inputs; forward-propagating the faulty behavior being tested from the node to a selected one of the primary outputs along a second path that traverses through the plurality of circuit nodes to the selected one of the plurality of primary outputs; marking as exercised ones of the plurality of circuit nodes through which the faulty behavior is propagated along the first and second paths; and repeating each of said selecting, said back-tracing, said forward-propagating and said marking steps until the termination criterion is met.