Patent ID: 7752585

Claim:
A method for design of in an integrated circuit (“IC”) device design process, wherein the IC device has entities related to one another in a logical hierarchy, wherein design production processes executed by a computer system produce representations of the respective entities and delay-definition data structures for the respective entities, the method comprising: selecting ones of the data structures, wherein the data structures are for inputting to a timing analysis process, and wherein the selecting comprises: finding, by a first process executing on a computer system, the delay-definition data structures for the entities; receiving data structures found by the first process and checking the received data structures for missing or corrupted components by a second process executing on the computer system, wherein the checking rejects data structures having missing or corrupted components; and receiving non-rejected data structures from the second process and selecting, by a third process executing on the computer system, from among the received, non-rejected data structures, a data structure with a most recent compile date for each respective entity; and providing the selected ones of the non-eliminated data structures to the timing analysis process for timing performance of the entity representations at hierarchical boundaries to determine whether the entities will function together at a desired frequency.