Patent ID: 7752581

Claim:
A method implemented by at least one computer comprising: at least one computer obtaining defect characteristic data; the at least one computer obtaining chip circuit design data across a whole semiconductor chip layer, the circuit design data comprising design shapes; a memory accessible by the at least one computer specifying a probability relationship across the whole semiconductor chip layer between the defect characteristic data and the chip circuit design data, wherein said probability relationship includes at least one risk factor of the defect characteristic data relative to the design shapes, wherein the risk factor is weighted for a specific physical location along the semiconductor layer and the risk factor relates to inoperability of an individual semiconductor chip; the at least one computer estimating probability of inoperability of the semiconductor chip for said probability relationship based on the defect characteristic data and the chip circuit design data; the at least one computer generating a probability model comprising an accumulated probability of inoperability of the semiconductor chip for all defects of the defect characteristic data; the at least one computer applying the generated probability model to a batch of semiconductor chips made with the chip circuit design data using actual defects measured in the batch; and the at least one computer outputting a predicted yield based on the applied probability model.