Patent ID: 8384149

Claim:
A semiconductor memory device including a first memory cell having a first floating gate and a second memory cell having a second floating gate, comprising: a semiconductor substrate having a contiguously formed recessed portion, the recessed portion having first and second sidewalls and a bottom surface joining the first and second sidewall surfaces, the semiconductor substrate having a first conductivity type; first, second, and third regions provided in the semiconductor substrate, the first, second and third regions having a second conductivity type opposite the first conductivity type, the recessed portion being provided between the first and second regions, the third region extending along the bottom surface of the recessed portion; the first floating gate provided in the recessed portion proximate the first sidewall and being spaced closer to the first region than the second region; the second floating gate provided in the recessed portion proximate the second sidewall and being spaced closer to the second region than the first region; an electrode having at least a portion provided in the recessed portion between the first and second floating gates, the electrode being insulated from the bottom surface of the recessed portion and the first and second floating gates; a conductive layer, a first portion of the conductive layer being insulated from and overlying a first portion of the substrate between the first region and the first floating gate, a second portion of the conductive layer being insulated from and overlying a second portion of the substrate between the second region and the second floating gate, the first and second portions of the conductive layer, upon application of a bias to the conductive layer, inducing first and second channels in the first and second portions of the substrate, respectively; a first driver circuit configured to selectively apply a second potential to the first region; a second driver circuit configured to selectively apply a second potential to the second region; a third driver configured to selectively apply a third potential to the third region; a fourth driver circuit configured to selectively apply a fourth potential to the electrode; a fifth driver circuit configured to selectively apply the bias to the conductive layer; and a sixth driver circuit configured to selectively apply a sixth potential to the substrate, wherein the third region and the electrode are common to the first memory cell and the second memory cell, and wherein at least one of a top surface of the first floating gate and a top surface of the second floating gate is flush with a top surface of the substrate.