Patent ID: 8141008

Claim:
A computer-aided design (CAD) system configured for correcting a circuit design layout containing a process critical feature, comprising: a processor; a memory connected to the processor; and a non-transitory computer usable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of: evaluating a detected error in the circuit design layout; said evaluating comprising: simulating the process critical feature of the circuit design layout within the limits of a process domain, wherein the process domain is defined by: determining a range of process variations of a plurality of nominal process conditions for a lithographic process; determining a probability distribution of the range of process variations of the plurality of nominal process conditions during a predefined circuit manufacturing process using the determined range, wherein the probability distribution is determined through test pattern measurements from the predefined manufacturing process; and defining the process domain, wherein the process domain defines limits of the range of process variations of the plurality of nominal process conditions and the limits are respectively based on determined probability distributions of the nominal process conditions; said evaluating further comprising detecting an error in the circuit design layout based on results from the simulation of the process critical feature; the instructions further configured to cause the processor to perform the operations of: creating a metric for process criticality based on a predicted edge movement and a resulting deviation in an electrical performance characteristic derived from the detected error; selecting a layout geometry based on the metric to determine whether the layout geometry requires modification to improve an electrical performance characteristic; and automatically performing a modification to the geometry layout to improve the electrical performance characteristic.