Patent ID: 8362802

Claim:
An asynchronous arbitration circuit, comprising: a multiplexer including first and second data inputs, a selection input and an output; a data register (REG) including an input connected to the output of the multiplexer, the data register including an enable input; a first latch (L 1 ) including an input, an output, and an enable input, the input of the first latch (L 1 ) providing a first request signal (Req 0 ) input; a second latch (L 2 ) including in input, an output, and an enable input, the input of the second latch (L 2 ) providing a second request signal (Req 1 ) input; a mutual exclusion element to select a first arriving request from the first request signal and the second request signal, the mutual exclusion element including a first and a second input and a first and a second output, the first output of the mutual exclusion element being connected to the enable input of the first latch (L 1 ) and the second output of the mutual exclusion element being connected to the enable input of the second latch (L 2 ), wherein the outputs of the mutual exclusion element are further connected to inputs of an SR flip flop with an output of the SR flip flop connected to the selection input of the multiplexer such that one of the first and second outputs of the mutual exclusion element corresponding to the selected first arriving request is outputted at the output of the SR flip flop to cause selection of one of the first and second data inputs to the multiplexer and to maintain the output of the SR flip flop after reset of the mutual exclusion element; a third latch (L 5 ) including an input, an output, and an enable input, the input of the third latch (L 5 ) being connected to receive the first request signal (Req 0 ) output by the first latch (L 1 ) and the second request signal (Req 1 ) output by the second latch (L 2 ) combined through an XOR element; and an XNOR element including two inputs and an output, the inputs of the XNOR element being connected to receive the output of the third latch (L 5 ) and an acknowledgement signal (Ack) input from a succeeding stage, respectively, and the output of the XNOR element being connected to the enable input of the third latch (L 5 ) and the enable input of the data register (REG).