Patent ID: 8321726

Claim:
A memory circuit comprising a memory array comprising a plurality of rows and a plurality of columns, each row comprising at least one addressable word, said memory array comprising at least one redundant row and at least one redundant column; error detection circuitry configured to analyze said memory array, by accessing words within said memory array and detecting errors within said accessed words; and error repair circuitry configured to select for a detected error either a redundant row or a redundant column to replace one of said rows or columns containing said detected error; wherein said error repair circuitry is configured to determine for said detected error whether said detected error is a single error bit in said accessed word or whether it is one of a plurality of error bits within said accessed word, and if said detected error is said one of said plurality of error bits, said error repair circuitry is configured to preferentially select a redundant row rather than a redundant column to repair said detected error; and in response to detecting that said detected error is a single error bit in said accessed word said error repair circuitry is configured to preferentially select a redundant column rather than a redundant row to repair said detected error without detecting whether there are other errors in the same column as said detected error.