Patent ID: 7288978

Claim:
A delay circuit for outputting an output signal produced by delaying an input signal according to a control signal for controlling a delay time, the delay circuit comprising: an inverter that is formed in between a source power line and a sink power line by a first conductivity-type transistor (M 6 ) on the source side and a second conductivity-type transistor (M 7 ) on the sink side which complementarily become conductive according to a level of the input signal; a source side current mirror that is formed by two source side transistors (M 4 , M 5 ) provided between the source power line and the inverter, wherein their control electrodes are connected in common and one of the source side transistors (M 4 ) is connected to form a diode and in series to the first conductivity-type transistor (M 6 ); a sink side current mirror that is formed by two sink side transistors (M 10 , M 11 ) provided between the inverter and the sink power line, wherein their control electrodes are connected in common and one of the sink side transistors (M 10 ) is connected to form a diode and in series to the second conductivity-type transistor (M 7 ); a bias circuit that generates two bias signals to drive the first conductivity-type transistor (M 6 ) and the second conductivity-type transistor (M 7 ) respectively according to the control signal; a first drive transistor (M 3 ) provided between the source power line and the second conductivity-type transistor (M 7 ) that drives according to one of the bias signals; and a second drive transistor (M 9 ) provided between the first conductivity-type transistor (M 6 ) and the sink power line that drives according to the other of the bias signals, wherein the other of the source side transistors (M 5 ) and the other of the sink side transistors (M 11 ) are connected in series, wherein, when the first conductivity-type transistor (M 6 ) becomes conductive on the basis of one level of the input signal, a first current path is formed through the one of the source side transistors (M 4 ), the first conductivity-type transistor (M 6 ), and the second drive transistor (M 9 ) between the source power line and the sink power line, and the output signal being the delayed inverse of the one level of the input signal is output from a connection point of the other of the source side transistors (M 5 ) and the other of the sink side transistors (M 11 ), and wherein, when the second conductivity-type transistor (M 7 ) becomes conductive on the basis of the other level of the input signal, a second current path is formed through the first drive transistor (M 3 ), the second conductivity-type transistor (M 7 ), and the one of the sink side transistors (M 10 ) between the source power line and the sink power line, and the output signal being the delayed inverse of the other level of the input signal is output from the connection point of the other of the source side transistors (M 5 ) and the other of the sink side transistors (M 11 ).