Patent ID: 7430239

Claim:
A bit-detection arrangement able to convert an analog signal having an amplitude into a digital signal representing a bit sequence from which the analog signal is derived, the bit-detection arrangement comprising: a preprocessing unit able to convert the analog signal into a processed signal suitable for further processing and able to produce a first output signal, the preprocessing unit comprising an analog to digital converter which is able to output the processed signal at a sample rate controlled by a first clock signal; a digital phase locked loop able to lock on the processed signal and able to output a phase signal using the first clock signal; a clock divider able to use a second clock signal to produce the first clock signal by dividing a frequency of the second clock signal by a factor n, where n is an integer greater than one, a bit decision unit able to output the digital signal and a third clock signal using the phase signal, the first clock signal, the second clock signal and the first output signal; and the preprocessing unit further comprising: a quantizer able to produce the first output signal by quantizing the amplitude of the analog signal, and a phase detector able to determine a phase difference between the first output signal and the second clock signal, and able to feed a second output signal having an amplitude to the analog to digital converter, where the amplitude of the second output signal indicates the phase difference, and the bit decision unit comprising a sample and hold unit able to sample the first output signal, using the second clock signal, and to hold n samples, sample y=1 to sample y=n , of the first output signal for a clock period of the first clock signal, n being a division factor of the second clock signal.