Patent ID: 8710880

Claim:
A power-on reset circuit, comprising: a first resistor, comprising a first terminal and a second terminal, wherein the first terminal is coupled to a ground terminal; a first transistor, comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the second terminal of the first resistor, and the control terminal of the first transistor is utilized for receiving a reference voltage; a second resistor, comprising a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second terminal of the first transistor; a second transistor, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the second resistor, and the control terminal of the second transistor is coupled to the second terminal of the second transistor and is utilized for receiving an input voltage; and a comparator, comprising a first input terminal and a second input terminal, wherein the first input terminal is coupled between the first terminal of the second resistor and the second terminal of the first resistor for receiving a comparison voltage, the second input terminal is utilized for receiving the reference voltage, and the comparator is utilized for generating a power-on reset signal according to the comparison voltage and the reference voltage.