Patent ID: 8102791

Claim:
A system for generating an address for interleaving in a wireless communication system, said system comprising: at least one input translation module that receives an input signal and translates the received input signal to generate a nominal input signal based on a value of the received input signal; and an address generation module operatively coupled to said at least one input translation module, wherein said address generation module receives said nominal input signal and generates an address for interleaving based on said nominal input signal, wherein said address for interleaving is equal to or less than a predetermined value, said predetermined value dependent on a number of bits in said input signal, wherein translating said received input signal into said nominal input signal comprises: estimating a value of said nominal input signal as 159 when said value of said received input signal is 155; estimating said value of said nominal input signal as 1023 when said value of said received input signal is 993; and estimating said value of said nominal input signal for all remaining values of said received input signal by utilizing: I n =I r +floor(I r /32), wherein I n is said value of said nominal input signal, I r is said value of said received input signal and floor(x) is a standard mathematical function, which returns a highest integer less than or equal to x.