Patent ID: 8716076

Claim:
A method for fabricating a semiconductor device, the method comprising: providing a substrate having an active substrate region defined by isolation regions; forming a gate structure on the substrate, the gate structure having a gate body with sidewall spacers thereon; removing the gate body and exposing a channel region in the active substrate region that is defined by the sidewall spacers; selectively forming an epitaxial region on the channel region, the epitaxial region spanning the active substrate region and projecting above the substrate, the epitaxial region having a relatively long lateral dimension in the channel width direction and self-aligned to the channel region, wherein a lattice constant of the epitaxial region differs from a lattice constant of the substrate, such that strain is induced in regions of the substrate proximal to the epitaxial region; forming a gate dielectric layer overlying the epitaxial region and the surface of the sidewall spacers; conformally depositing a gate metal layer on the gate dielectric layer; depositing a fill material over the gate metal layer and substantially filling an area between the sidewall spacers and the gate metal layer; and planarizing the fill material, the gate metal layer, and the gate dielectric layer to form a gate electrode overlying the gate dielectric, the gate electrode having a relatively long lateral dimension substantially parallel to the relatively long lateral dimension of the epitaxial region.