Patent ID: 8364859

Claim:
A storage device comprising: a storage section; a storage controller that controls access to the storage section; a controller that performs a communication process with a host device; a data terminal; a reset terminal; and a clock terminal, wherein the host device is electrically connected to first to n-th (n is an integer of two or more) storage devices including the storage device through a bus, wherein a reset signal that is output from the host device is input to the reset terminal through the bus, wherein the controller determines that an operational mode is a normal communication mode when a voltage level of the reset terminal is changed from a voltage level indicating a reset state to a voltage level indicating a reset-disabled state during a time period for which a voltage level of the clock terminal is a first voltage level, wherein the controller determines that the operational mode is a connection detection mode when the voltage level of the reset terminal is changed from the voltage level indicating the reset state to the voltage level indicating the reset-disabled state during a time period for which the voltage level of the clock terminal is a second voltage level, and wherein a clock that includes first to n-th (n is an integer of two or more) clock cycles is input to the clock terminal, and wherein when the controller determines that the operational mode is the connection detection mode, the controller outputs a response signal to the host device through the data terminal for an m-th (m is at least one of integers satisfying 1 ≦m≦n) clock cycle among the first to n-th clock cycles after the voltage level of the clock terminal is changed from the second voltage level to the first voltage level, the response signal indicating that the storage device is connected, the m-th clock cycle corresponding to information on the ID of the storage device.