Patent ID: 7473963

Claim:
A unit cell of a metal oxide semiconductor (MOS) transistor comprising: an integrated circuit substrate; a MOS transistor on the integrated circuit substrate, the MOS transistor having a source region, a drain region and a gate region, the gate region being between the source region and the drain region; first and second channel regions between the source and drain regions, the channel region being defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region, the first and second protrusions extending away from the integrated circuit substrate; a gate electrode in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions; and an isolation layer on the integrated circuit substrate such that the source region, drain region, gate region and first and second channel regions are free of the isolation layer, the isolation layer having an upper surface that is lower than upper surfaces of the first and second channel regions.