Patent ID: 8024521

Claim:
In a processor system comprising a main memory and a first processor element including a first processor unit coupled to an external cache, a method for atomic operation, the method for executing an atomic operation instruction, the method comprising: a) when executing the atomic operation instruction with the first processor unit, atomically loading data from a lock-line in the main memory into a first location X in the external cache, wherein a size of the data is larger than a data size for standard atomic operations with the first processor unit, wherein the lock-line is accessible by the first processor unit and a second processor unit in a lock-free manner, wherein the first and second processor units have different reservation sizes for atomic operations, wherein a data size for the lock-line is larger than a reservation size for standard atomic operations with the first processor unit; and b) when executing the atomic operation instruction reserving the data in a second location Y in the external cache, wherein reserving the data in the second location includes copying the contents of the first location X into the second location Y; and making an indication that the contents of the second location Y have been changed subsequent to a prior reservation.