Patent ID: 7071040

Claim:
A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on said substrate, and source and drain electrodes formed above source and drain regions formed in said semiconductor layer, said source and drain electrodes being composed of aluminum or aluminum alloy, said method comprising the steps of: (a) forming a gate electrode electrically insulated from said semiconductor layer through a gate insulating film; (b) implanting ions of impurity having a predetermined electrical conductivity, into at least a part of said semiconductor layer for forming said source and drain regions; (c) forming an interlayer insulating film entirely over said substrate; (d) forming contact holes throughout said interlayer insulating film such that at least a part of said source and drain regions is exposed through said contact holes; (e) forming an electrically conductive film composed of aluminum or aluminum alloy, in said contact holes for forming said source and drain electrodes electrically connecting said source and drain regions through said contact holes; and (f) immediately after said step (e), thermally annealing said substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere.