Patent ID: 8728893

Claim:
A method of fabricating a semiconductor memory device, comprising: alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate; forming an active pattern on the substrate, such that the active pattern penetrates the sacrificial layers and the insulating layers; continuously patterning the insulating layers and the sacrificial layers to form a trench; removing the sacrificial layers exposed in the trench to form recess regions, such that the recess regions expose a sidewall of the active pattern; forming a blocking insulating layer on the substrate; depositing a gate conductive layer on the blocking insulating layer, such that the deposited gate conductive layer completely fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer; and performing an isotropic etch process with respect to the deposited gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.