Patent ID: 6962841

Claim:
A method of forming a memory cell comprising: providing a semiconductor substrate; forming a P well in said semiconductor substrate; forming an N well in said semiconductor substrate adjacent to said P well; forming an N type active region in said P well; forming a P type active region in said N well; forming an isolation region in said semiconductor substrate to isolate said N type active region from said P type active region; providing a polysilicide gate electrode structure composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film, wherein said polycrystalline silicon film comprises an N+ polysilicon layer over said N type active region and a P+ polysilicon layer over said P type active region; and forming an ultrathin oxidea diffusion barrier layer in said polysilicide gate electrode structure over a portion of said polycrystalline silicon film between said polycrystalline silicon film and said metal, metal silicide, or metal nitride film.