Patent ID: 8062539

Claim:
A method for manufacturing a multilayer printed wiring board with an embedded capacitor circuit, which is characterized by comprising the following steps A1 to E: step A1: a first-conductive-metal-layer laminating step where a dielectric layer and a first conductive metal layer are provided on the surface having a base electrode of a core material with base electrode(s) on one side or both sides of its insulating layer; step B: an top-electrode fowling step where the first conductive metal layer(s) locating as an outer layer(s) is(are) processed into top electrodes and the dielectric layer(s) in the area other than those of the circuit portions is(are) exposed; step C: a dielectric-layer removing step where the exposed dielectric layer, which is in the area other than those of circuit portions, is removed; step D: a second-conductive-metal laminating step where the gaps among the top electrodes are filled in and an insulating layer and a second conductive metal layer are provided on the top electrodes; and step E: an outer layer circuit forming step where the second conductive metal layer is processed into outer layer circuits, wherein in the dielectric-layer removing step, a chemical treatment is used to remove the exposed dielectric layer(s), which are in the area other than those of circuit portions for the top electrodes, wherein the chemical treatment comprises a de-smear treatment.