Patent ID: 7183150

Claim:
A method comprising: providing a semiconductor substrate, providing a layer of resist protective oxide (RPO) on a surface of the substrate, the layer of RPQ comprising a first layer of silicon dioxide, a layer of silicon nitride, and a second layer of silicon dioxide; patterning the layer of RPO wherein a region over the substrate containing at least one CMOS device is not covered by the layer of RPO, said step of patterning the layer of RFO comprises: (i) patterning the first layer of silicon dioxide including using a photoresist layer; (ii) removing the photoresist layer and subsequently patterning the layer of silicon nitride using the first layer of silicon dioxideas a mask; (iii) pattering the second layer of silicon dioxide using the first layer of silicon dioxide and the layer of silicon nitride as a mask by applying a wet-etch to the second layer of silicon dioxide; and saliciding contact surfaces of the at least one CMOS device.