Patent ID: 8625329

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and each including a variable resistive element; and a control circuit which controls resistance values of the variable resistive elements in such a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected one of the plurality of first lines and a selected one of the plurality of second lines by applying a first voltage to the selected first line and by applying a second voltage to the selected second line, wherein the control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and applies a pulsing voltage as the second voltage to the selected second line, and the second voltage includes a voltage pulse which is raised from a second initial voltage which the memory cell is a non-selected state to a raised voltage which the memory cell is a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with a change in the first voltage reaches a compliance current.