Patent ID: 8619931

Claim:
An integrated circuit device comprising: one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater; and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers and to data utilization circuitry disposed on the integrated circuit device, wherein each of the transceivers comprises: a phase detector configured to receive the serial signals and a current clock signal, wherein the current clock signal is based at least in part on the multi-phase clock signal, and to output one or more recovered data signals that indicate data recovered from the serial signals and one or more alignment error signals that indicate whether the current clock signal is aligned with the serial signals; and a phase interpolator configured to receive a phase interpolator control signal and the multi-phase clock signal and to output the current clock signal, wherein the phase interpolator control signal is based at least in part on the one or more alignment error signals and wherein the current clock signal is approximately aligned with the serial input signals.