Patent ID: 8161349

Claim:
A data parallelizing receiver comprising: an input signal receiver that receives packetized serial data, samples the serial data, aligns the sampled data in an input order, and converts the aligned data into parallel data to output the parallel data; a cyclic redundancy check (CRC) partial calculator that receives the parallel data, classifies the parallel data into groups according to the input order, and performs a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results; a CRC partial calculation merger that receives the plurality of partial CRC calculation results and merges the partial CRC calculation results to output CRC calculation data; a clock generator that receives a system clock signal, generates a first clock signal to synchronously sample the serial data, generates a second clock signal to frame the sampled data, and generates a third clock signal having a phase that lags a phase of the second clock signal; a command decoder that receives a first bitstream of a parallel data merge signal obtained by merging a previously input first bitstream for each of the groups to generate a third bitstream of the parallel data merge signal synchronously with the third clock signal, and receives a second bitstream of a parallel data merge signal obtained by merging a subsequently input second bitstream for each of the groups to generate a merged second bitstream, and decoding the merged second bitstream to output decoded commands; an output command selector that receives the decoded commands, temporarily stores the decoded commands, and holds the decoded commands in standby to selectively output the decoded commands in response to a selection signal received with the decoded commands, wherein the output command selector comprises: a command queue that receives the decoded commands, temporarily stores the decoded commands, and holds the decoded commands for a predetermined time according to a data transmission protocol to output the decoded commands; and a multiplexer that receives the decoded commands from the command decoder and the command queue to selectively output the commands in response to the selection signal; a data error determiner that receives the CRC calculation data, performs a logic NOR on the CRC calculation data, and determines whether there is a data error to output an error determination signal; and an error command selector that receives the decoded command and the error determination signal and performs a logic AND on the decoded command and the error determination signal to selectively output the decoded command only when the data error is not detected.