Patent ID: 7745323

Claim:
A metal interconnection structure of a semiconductor device, comprising: lower metal interconnection layers disposed on a semiconductor substrate; an intermetallic dielectric layer made of a low-k material disposed on the semiconductor substrate, wherein the intermetallic dielectric layer has a thickness of 7,000 to 12,000 Å; a first buffer layer for decreasing a stress applied to the lower metal interconnection layers from the intermetallic dielectric layer disposed between the lower metal interconnection layers and the intermetallic dielectric layer said first buffer layer made of a metal oxide, wherein the first buffer layer has a thickness of 500 to 1,000 Å, and wherein the first buffer layer is deposited by chemical vapor deposition at a temperature of less than 500° C.; a first intermetallic dielectric layer made of a low-k material disposed on the first buffer layer of the metal oxide; a second buffer layer deposited on the first intermetallic dielectric layer for decreasing a stress applied to the lower metal interconnection layers from the first intermetallic dielectric layer and from a second intermetallic dielectric layer, said second buffer layer made of a metal oxide, wherein the second buffer layer has a thickness of 500 to 1,000 Å, and wherein the second buffer layer is deposited at a temperature of less than 500° C.; a second intermetallic dielectric layer made of a low-k material disposed on the second buffer layer of a metal oxide, wherein the total thickness of the first and second intermetallic dielectric layers is outside the range of 7,000 to 12,000 Å; and an upper metal interconnection layer disposed on the second intermetallic dielectric layer and electrically connected through the second intermetallic dielectric layer, second buffer layer, first intermetallic dielectric layer and first buffer layer to the lower metal interconnection layers.