Patent ID: 8286059

Claim:
An encoder configured to encode cyclic codes, the encoder comprising: a first word register and a second word register each having an input and an output; an input adder that is coupled to the output of the first word register, the input adder being configured to receive input words and to output corresponding feedback words; a first adder array that is coupled between the input of the first word register and the output of the second word register; a feedback loop that is configured to selectively transmit feedback words to the input of the second word register and an input of the first adder array; a controller that is configured to cause the encoder to operate in an input mode and an output mode, during the input mode, feedback words are sequentially transmitted on the feedback loop, a number of bits per a feedback word being different from a word width of at least one of the first and second registers, and states of the first word register and the second word register are updated, while during the output mode, states of the first word register and the second word register are sequentially shifted out of the first word register as parity words; and a multiplexer to output the input words and parity words from the encoder such that each parity word is appended to a corresponding input word.