Patent ID: 7764085

Claim:
A buffer circuit having at least an input terminal for receiving an input signal and an output terminal for outputting an output signal; said buffer circuit further comprising: a pulling up transistor and a pulling down transistor connected to said output terminal, respectively pulling up and pulling down said output terminal; a control circuit connected between said input terminal and said output terminal; said pulling up transistor directly receiving said input signal through said control circuit receiving an output of said control circuit; wherein said control circuit causes said pulling up transistor and the pulling down transistor to go from an ON state to an OFF state during a first interval in which the input changes from low to high, while said pulling down transistor is OFF, and during a second interval following the first interval said pulling down transistor is transferred from an OFF state to an ON state and during a third interval following the second interval said pulling down transistor is transferred from said ON state to said OFF state while said pulling up transistor is maintained in said OFF state.