Patent ID: 8001172

Claim:
A circuit for correlating an input signal comprising: a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produce a scaled signal, wherein the scaling factors in successive processing elements correspond to the coefficients in a Fourier series approximation of a desired frequency response; a timing circuit for causing the scaled signal to be presented in time-delayed succession to be successive sampled by the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample, wherein the timing circuit is configured to cause the timing signal to be presented in time-delayed succession to successive ones of said analog sampling unit processing elements, said timing circuit comprising a timing element in parallel with an associated analog sampling unit processing element, and said timing element comprising a phase lock loop or a delay lock loop; and a multiplier configured to multiply the scaled signal and produce an output wherein the multiplier includes each analog sample unit processing element to scale the output and sum the scaled outputs of said processing elements.