Patent ID: 8284619

Claim:
A semiconductor integrated circuit comprising: a memory cell array including a plurality of memory cells, and a plurality of word lines and a plurality of bit lines coupled to the memory cells; an internal circuit including a plurality of circuit blocks to operate by receiving an internal power supply voltage and the circuit blocks including a row decoder to select one of the word lines to supply a high level voltage to a selected word line, a sense amplifier coupled to the bit lines to amplify a data signal on the bit lines, and a column switch to couple one of the bit lines to a data bus; an operation control circuit to generate a plurality of kinds of operation control signals to control operations of the row decoder, the sense amplifier and the column switch, respectively, according to an access request to access the memory cell, an internal voltage control circuit to generate a plurality of regulator control signals according to the operation control signals; and an internal voltage generation circuit including a plurality of regulators which operate in response to activation of the respective regulator control signals to generate the internal power supply voltage by using an external power supply voltage.