Patent ID: 7508059

Claim:
A chip package comprising: a first semiconductor chip having a first side and a second side, wherein said first side of said first semiconductor chip is opposite to said second side of said first semiconductor chip, and wherein said first semiconductor chip comprises a first metal pad, a metal layer and a first passivation layer at said first side of said first semiconductor chip, wherein said first passivation layer comprises a nitride layer, wherein an opening in said first passivation layer is over said first metal pad, wherein said first metal pad has a top surface at a bottom of said opening in said first passivation layer, wherein said metal layer is over said first metal pad and over said first passivation layer and is connected to said first metal pad through said opening in said first passivation layer, and wherein said metal layer comprises a second metal pad over said first passivation layer, wherein said second metal pad is connected to said first metal pad through said opening in said first passivation layer and has a position, from a top perspective view, different from that of said first metal pad; a second semiconductor chip having a first side and a second side, wherein said first side of said second semiconductor chip is opposite to said second side of said second semiconductor chip, wherein said second semiconductor chip comprises a third metal pad at said first side of said second semiconductor chip, and wherein said second side of said second semiconductor chip is joined with said second of said first semiconductor chip; a substrate having a first side and a second side, wherein said first side of said substrate is opposite to said second side of said substrate, wherein said substrate comprises a fourth metal pad at said first side of said substrate and a fifth metal pad at said second side of said substrate, and wherein said first side of said substrate is joined with said first side of said second semiconductor chip; a first wirebonded wire connecting said second metal pad of said first semiconductor chip to said fourth metal pad of said substrate, wherein said first wirebonded wire is bonded to said second metal pad of said first semiconductor chip and to said fourth pad of said substrate; and a second wirebonded wire connecting said third metal pad of said second semiconductor chip to said fifth metal pad of said substrate through an opening in said substrate, wherein said second wirebonded wire is bonded to said third metal pad of said second semiconductor chip and to said fifth metal pad of said substrate.