Patent ID: 7306552

Claim:
A method of fabricating a semiconductor device on a semiconductor substrate having a resistor region, the method comprising: defining active regions in the resistor region of the semiconductor substrate with a trench isolation layer; forming an insulating layer on the active regions, the insulating layer self-aligned with the trench isolation layer; forming first conductive layer patterns on the insulating layer, the first conductive layer patterns self-aligned with the trench isolation layer; forming a second conductive layer on the semiconductor substrate having the first conductive layer patterns; patterning the second conductive layer to form a second conductive layer pattern that covers the first conductive layer patterns and the isolation layer between the first conductive layer patterns, the first conductive layer patterns and the second conductive layer pattern forming a load resistor pattern; forming a planarized interlayer insulating layer on the load resistor pattern; exposing the load resistor pattern over the active regions with resistor contact holes, the resistor contact holes formed through the planarized interlayer insulating layer; and filling the resistor contact holes with resistor contact plugs that contact the load resistor pattern.