Patent ID: 7062657

Claim:
A normalization/denormalization circuit included in a cryptography accelerator unit coupled to an external processor, comprising: a normalization sub-circuit arranged to generate normalized data based upon corresponding unnormalized data containing unnormalized data blocks; a context sub-circuit coupled to the normalization sub-circuit for characterizing the normalized data in relation to the unnormalized data; and a denormalization sub-circuit coupled to the context sub-circuit arranged to provide the unnormalized data based upon the normalized data and the characterization, wherein the normalization/denormalization circuit provides a normalization/denormalization service to the cryptography accelerator unit, wherein, for each unnormalized data block, the normalization sub-circuit reads he unnormalized data block, shifts the data block according to a shift amount, and writes the data block shifted according to the shift amount into a memory address calculated according to (R−S−1+I)% B, where R is a length of the unnormalized data divided by a number of bits per data block, S is a length of data beginning from a leading one bit to a least significant bit of he unnormalized data divided by the number of bits per data block, I is a current unnormalized data block number processed by the normalization sub-circuit, and B is the number of bits per data block.