Patent ID: 8341434

Claim:
A computer chip comprising: a Voltage Regulation Module (VRM) array, wherein said VRM array is distributed in a three dimensional (3D) arrangement on said computer chip, wherein said VRM array comprises a first VRM and a second VRM; a power plane comprising a first power bus and a second power bus operatively connected by a voltage gate, wherein the first power bus is coupled to the first VRM, and the second power bus is coupled to the second VRM, wherein the first VRM provides a first fixed voltage to the first power bus, and the second VRM provides a second fixed voltage to the second power bus; a power island comprising a first circuit and a second circuit, wherein the first power bus is coupled to the first circuit and the second power bus is coupled to the second circuit; and a communication logic configured to: receive, via the first VRM, a first determined power need for the first circuit, receive, via the second VRM, a second determined power need for the second circuit, determine whether the first VRM has excess voltage based on the first determined power need and the first fixed voltage, and in response to a determination that the first VRM has excess voltage, automatically cause the first power bus to push excess voltage onto said power plane via the voltage gate.