Patent ID: 7754554

Claim:
A method for fabricating a CMOS integrated circuit including an NMOS transistor disposed in and on a silicon-comprising substrate and a PMOS transistor disposed in and on the substrate, the method comprising the steps of: depositing a first silicide-forming metal on the NMOS and PMOS transistors, wherein the first silicide-forming metal forms a silicide at a first temperature; forming a buffer layer of the first silicide-forming metal on one of the NMOS and PMOS transistors; forming an insulating layer overlying first silicide-forming metal of the other of the NMOS and PMOS transistors; depositing a second silicide-forming metal overlying the NMOS and PMOS transistors, wherein the second silicide-forming metal forms a silicide at a second temperature that is different from the first temperature; and heating the first silicide-forming metal and the second silicide-forming metal at a temperature that is no less than the higher of the first temperature and the second temperature.