Patent ID: 8218370

Claim:
A method of erasing a single bit in a memory cell of a memory array, the method comprising: grounding a word line, in a first set of word lines, connected to the memory cell to be erased, wherein the memory cell is one of a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising: an access transistor; a floating gate memory transistor electrically connected to the access transistor; and a coupling capacitor electrically connected to the memory transistor; grounding a word line, in a second set of word lines, connected to the memory cell to be erased; applying a first voltage to a bit line connected to the memory cell to be erased; and applying a second voltage to word lines, in the first set of word lines, not connected to the memory cell to be erased, the second voltage being about one-half of the first voltage.