Patent ID: 7939443

Claim:
A method for defining a rectangular interlevel connector array (RICA) in a semiconductor chip layout, comprising: defining a virtual grid for interlevel connector placement, wherein the virtual grid is defined by a first set of parallel virtual lines that extend across the layout in a first direction and by a second set of parallel virtual lines that extend across the layout in a second direction that is perpendicular to the first direction, wherein each intersection point between the first and second sets of parallel virtual lines is a gridpoint in the virtual grid; and placing a first plurality of interlevel connector structures at respective gridpoints in the virtual grid to form a first RICA, whereby neighboring interlevel connector structures of the first RICA are spaced apart from each other by a first number of gridpoints in the first direction and by a second number of gridpoints in the second direction, and whereby the first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level.