Patent ID: 7230489

Claim:
A system comprising: a transmitter; a receiver; and a transmission line coupled to the transmitter and the receiver; the receiver including: an amplifier; and a delay and gain circuit comprises a first converter and a second inverta coupled to an output of the amplifier, wherein an output of the delay and gain circuit is fed back to the amplifier; wherein the amplifier includes a first, a second and a third pMOS transistor and a first, a second and a third nMOS transistor; wherein a gate of the first pMOS transistor and a gate of the first nMOS transistor are coupled to an input of the amplifier; wherein a gate of the second pMOS transistor and a gate of the second nMOS transistor are coupled to a drain of the first pMOS transistor and a drain of the first nMOS transistor; and wherein a gate of the third pMOS transistor and a gate of the third nMOS transistor are coupled to an inverse input of the amplifier.