Patent ID: 7746129

Claim:
A ramp generator circuit for generating a ramped voltage at an output node, comprising: a pulse generator circuit for generating a pulse comparison clock signal and a reset pulse clock signal from a single input clock signal so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal; a switched comparator circuit comprising a first input coupled to receive a reference signal, a second input coupled to the output node to receive the ramped voltage, and a comparator output node, wherein the switched comparator circuit is configured to produce, in response to the pulse comparison clock signal, a comparison signal at the comparator output node which indicates a difference between the ramped voltage and the reference signal; a charge pump circuit comprising a charge pump capacitor which is charged or discharged to develop a control voltage in response to the comparison signal; a voltage-to-current converter circuit for generating a ramp current in response to the control voltage; a charging capacitor which is coupled to receive the ramp current so as to develop the ramped voltage at the output node; and a clamping circuit coupled across the charging capacitor for discharging the charging capacitor in response to the reset pulse clock signal.