Patent ID: 7422971

Claim:
A process of forming a semiconductor device comprising: providing a gate stack upon a silicon-on-insulator (SOI) substrate; forming a first spacer and a second spacer on the gate stack; growing an elevated epitaxial first layer upon the substrate; at the gate stack, forming a gate stack undercut; and at the undercut, growing an embedded epitaxial source/drain junction, wherein growing the embedded epitaxial source/drain junction at the undercut further includes: substantially removing the elevated epitaxial first layer under conditions to form the undercut, to expose a self-aligned region of the insulator of the SOI substrate, and a lateral residue of the silicon on the SOI substrate; and at the undercut, growing an embedded epitaxial source/drain junction under conditions that cause epitaxial silicon to form a closure seam between the undercut and the lateral residue.