Patent ID: 7515470

Claim:
A semiconductor integrated circuit device comprising: a memory cell array into which a nonvolatile semiconductor memory connected to a word line is integrated, and which includes a plurality of blocks; a row decoder which selects the word line; a column control circuit which carries out writing of data into the nonvolatile semiconductor memory and reading data from the nonvolatile semiconductor memory; a storage unit which includes information registration areas with which it is possible to register a plurality of information including base values; a first register group which includes a plurality of first registers into which the base values of said plurality of information are set; a first selection signal generating circuit which generates a first selection signal for selecting said plurality of first registers; a second register group which includes a plurality of second registers into which a plurality of raising values are set; and a second selection signal generating circuit which generates a second selection signal for selecting said plurality of second registers, wherein, after the base values of said plurality of information are set into the first register group, operation of a base value set into a first register selected by the first selection signal and a raising value set into a second register selected by the second selection signal is carried out, and a result of the operation is returned to the first register selected by the first selection signal.