Patent ID: 7912670

Claim:
A multi-core processor chip, comprising: a plurality of processing cores; a plurality of adjustable power supplies, each of the adjustable power supplies connected to a one of the plurality of processing cores and configured to provide a supply voltage to the one of the plurality of processing cores; a programmable controller in communication with the plurality of adjustable power supplies; and an inter-core voltage-level translation communication block component configured to enable the plurality of processing cores to function with divergent on-signal supply voltages supplied by the adjustable power supplies; wherein the programmable controller is configured to manufacturing yield test and configure the multi-core processor chip by: setting the adjustable power supplies to an initial nominal supply voltage value, the initial nominal supply voltage value specified as operating a processing core at a minimum reference clock speed pursuant to a design rule; select each of the plurality of processing cores and iteratively lowering a core set supply voltage provided by the selected core's adjustable power supply until an Nth observed clock speed generated by the core responsive to an Nth lowered supply voltage is less than the minimum reference clock speed and set the selected core adjustable power supply to provide an (N-1)th lowered supply voltage as an operative supply voltage to the selected core, wherein different cores may be configured to have different core operative supply voltages set relative to the minimum reference clock speed; and pass the multi-core processor system chip if an overall power consumption value for the multi-core processor system with each of the plurality of cores operating at its respective set operative supply voltage does not exceed a specified maximum power consumption value; or fail the chip.