Patent ID: 7529333

Claim:
A shift register, comprising: first and second stages for sequentially outputting scan pulses to drive first and second gate lines, one of the first and second stages comprising: a pull-up switching device connected to an enabling node of the one of the first and second stages; a first pull-down switching device connected to a first disabling node of the one of the first and second stages; a second pull-down switching device connected to a second disabling node of the one of the first and second stages, wherein one terminal of source and drain terminals at the pull-up switching device, one terminal of source and drain terminals at the first pull-down switching device and one terminal of source and drain terminals at the second pull-down switching device are commonly connected to one of the gate lines; and a node controller, wherein the node controller of the first stage controls the logic state of the enabling node of the first stage, the first disabling node of the first stage and the first disabling node of the second stage, wherein the node controller of the second stage controls the logic state of the enabling node of the second stage, the second disabling node of the second stage and the second disabling node of the first stage.