Patent ID: 8089978

Claim:
A device, comprising: a memory unit; a shift register coupled to the memory unit; a memory unit controller coupled to the memory unit, and a communication line interface, whereas the memory unit is adapted to store channel information from multiple channels, and whereas the memory unit controller is adapted to control a provision of the channel information from the memory unit to the shift register; and shift register logic adapted to replace the channel information outputted by the shift register by a predefined content when the shift register stores a communication channel disable code an under-run is detected; whereas a communication channel that experienced the under-run is defined as a disabled communication channel, and whereas the channel information is characterized by a stop bit and whereas the communication channel disable code lacks the stop bit; whereas the shift register logic is further adapted to transmit, via the communication line interface, idle signals during the at least one later time slot allocated to the disabled communication channel; and whereas the device is adapted to transmit the channel information from enabled communication channels.