Patent ID: 8451050

Claim:
Information technology equipment comprising: a circuit block; a local power source line for supplying a power source to the circuit block; a power source line; and a first transistor provided with a source-drain path thereof between the power source line and the local power source line, wherein the first transistor is controlled to an OFF state in a first state of the circuit block, and controlled to an ON state in a second state of the circuit block; a second transistor; and an adjustable current source which provides a current that can be adjusted to a plurality of values; wherein a gate of the first transistor is connected to a gate of the second transistor; wherein a source of the second transistor is connected to the power source line; wherein a drain of the second transistor is connected to the gate of the first transistor, the gate of the second transistor, and the adjustable current source; wherein when circuit block is shifted from the first state to the second state, the first transistor is controlled by adjusting the current of the adjustable current source such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a value predetermined to restrain power source noise due to leakage current of the circuit block.