Patent ID: 8683168

Claim:
A memory card, comprising: a plurality of first blocks configured to store user information therein, to which first physical addresses which are not duplicate are assigned, respectively; a plurality of second blocks configured to individually store therein said first physical addresses of initial defective blocks out of said plurality of first blocks; a plurality of third blocks configured to individually store therein said first physical addresses of late defective blocks out of said plurality of first blocks; and a computing device configured to obtain a first physical address corresponding to a logical address on the basis of said logical address, information stored in said second blocks, and information stored in said third blocks, wherein said third blocks are assigned third physical addresses which are not duplicate, respectively, said first physical addresses of said late defective blocks are stored in said third blocks such that when said third blocks are viewed in ascending order of said third physical addresses, said first physical addresses of said late defective blocks stored in said third blocks are arranged in the order that late defects occur, said computing device (A) obtains said first physical address corresponding to said logical address on the basis of said logical address and said information stored in said second blocks, and (B) determines if said first physical address obtained in said step (A) agrees with any one piece of said information stored in said third blocks, and when said computing device determines in said step (B) that said first physical address agrees with one piece of said information stored in said third blocks, said computing device (C) obtains an alternate logical address on the basis of said third physical address of said third block which stores therein said first physical address obtained in said step (A) and a leading alternate logical address which is prepared in advance, and (D) obtains said first physical address corresponding to said logical address on the basis of said alternate logical address and said information stored in said second blocks.