Patent ID: 8055967

Claim:
An integrated circuit, comprising: A. a substrate; B. a first die carried on the substrate, the first die including: i. a first test access port interface having a TDI input signal lead, a TCK input signal lead, a TMS input signal lead, a TRST input signal lead, and a TDO output signal lead; ii. a second test access port interface having a TDI output signal lead, a TCK output signal lead, a TMS output signal lead, a TRST output signal lead, and a TDO input signal lead; and iii. first linking module circuitry including a controller, an instruction register, and multiplexer circuitry for selectively coupling the signals on the first test access port interface leads of the first die with the second test access port interface leads of the first die; and C. a second die carried on the substrate, the second die including: i. a first test access port interface having a TDI input signal lead, a TCK input signal lead, a TMS input signal lead, a TRST input signal lead, and a TDO output signal lead, the signals on the first third test access port interface of the second die being connected with the signals on the second test access port interface of the first die; ii. a second test access port interface having a TDI output signal lead, a TCK output signal lead, a TMS output signal lead, a TRST output signal lead, and a TDO input signal lead; and iii. second linking module circuitry including a controller, an instruction register, and multiplexer circuitry for selectively coupling the signals on the first test access port interface leads of the second die with the second test access port interface leads of the second die.