Patent ID: 7411302

Claim:
A semiconductor device comprising: semiconductor elements formed in a semiconductor substrate; a first interlayer insulation film formed over said semiconductor elements; first wirings, second wirings and third wirings formed over said first interlayer insulation film, respectively; and a second interlayer insulation film formed over said first, said second and said third wirings, wherein said third wirings are electrically connected with said semiconductor elements, wherein said first and second wirings are not electrically connected with said semiconductor elements, wherein said first, second and third wirings are formed at a same layer, wherein said first wirings are formed regularly, wherein said second wirings are formed regularly, wherein a planar size of each of said first wirings is larger than a planar size of each of said second wirings, wherein each and every one of said first wirings has a same planar size, wherein each and every one of said second wirings has a same planar size, wherein grooves are formed in said semiconductor substrate such that said grooves define active regions and dummy regions, wherein said semiconductor elements are formed in said active regions, wherein said first and second wirings are arranged over said dummy wirings, and wherein elements isolation insulating films are filled in said grooves.