Patent ID: 8825965

Claim:
A method comprising: receiving a memory request from a memory controller via a first channel, wherein the memory request includes a logical rank identification (ID) for a logical rank and a logical memory address within the logical rank; using a memory expansion map to map the logical rank ID and a portion of the logical memory address to a first sub-channel selected from a plurality of sub-channels and a first physical rank selected from a plurality of physical ranks connected to the first sub-channel; based on the memory request, selecting a location in a memory that is to be communicatively coupled with the first sub-channel, the location in the memory being selected from the first physical rank, and the selecting of the location in memory including identifying a look-up table based on the logical rank ID included within the memory request, using the look-up table with the logical rank ID and the portion of the logical memory address to identify the first sub-channel selected form the plurality of sub-channels and the first physical rank selected from the plurality of physical ranks connected to the first sub-channel, using a bank ID included within the logical memory address as an index to one or more bits of a row address, and determining that the first physical rank includes an activated row based on the logical rank ID and the one or more bits of the row address, the activated row including the location in the memory where the data is stored; configuring a set of field effect transistors to communicatively couple the first channel with the first sub-channel to enable data to flow from the first channel to the first sub-channel; and allowing the data to flow between the memory controller and the location in the memory via the first channel and the first sub-channel, the data being allowed to flow without retiming the data to align with a clock signal, and the data being stored at the location in the memory.