Patent ID: 7782671

Claim:
A semiconductor device including a plurality of memory cell transistors, comprising: a semiconductor substrate including a first and a second end regions and a cell region located between the first and the second end regions, the memory cell transistors located in the cell region; a first word line located from the first end region to the second end region through the cell region along a predetermined direction, the first word line including a first main word line portion located from the cell region to the first end region and a first dummy word line portion located in the second end region along an extension direction of the first main word line portion, a first end of the first dummy word line portion located near a second end of the first main word line portion via a first dividing portion located in the second end region; a second word line located adjacent to the first word line from the first end region to the second end region through the cell region in parallel with the first word line, the second word line including a second main word line portion located from the cell region to the second end region and a second dummy word line portion located in the first end region along an extension direction of the second main word line portion, a third end of the second dummy word line located adjacent to a fourth end of the second main word line portion via a second dividing portion located in the first end region; a first contact located in the first end region and electrically connected to the first main word line portion; and a second contact located in the second end region and electrically connected to the second main word line portion.