Patent ID: 8129253

Claim:
A method for providing parasitic current control over devices borne by a semiconductor wafer having a substrate, at least one active component layer and a surface layer during burn-in, the method comprising the steps of: forming at least one trench around and defining boarders with active regions, wherein said at least one trench extends from said surface layer through said at least one active component layer towards said substrate and wherein said at least one trench further defines inactive regions that hinder current flow therethrough; and performing a burn-in process for a plurality of the devices borne in the semiconductor wafer at the same time using a first contact plate connected to a first side of the semiconductor wafer and a second contact plate connected to a second side of the semiconductor wafer, the surfaces of the first and second contact plates clamping the semiconductor wafer, wherein during the burn-in process, the first and second contact plates are each a single common electrical contact to all devices that are borne in the semiconductor wafer and undergo the burn-in process.