Patent ID: 7964465

Claim:
A structure fabrication method, comprising: providing a structure which includes: (a) a fin region comprising a first semiconductor material, wherein the fin region includes: (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface, wherein the second and fourth surfaces are parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer in direct physical contact with the channel region, and (c) a gate electrode region in direct physical contact with the gate dielectric layer, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region; after said providing is performed, covering the first and second surfaces but not the third and fourth surfaces with a patterned covering layer; and after said covering is performed, etching the first and second source/drain portions at the third and fourth surfaces, respectively.