Patent ID: 7917723

Claim:
A computer system, comprising: an address translation table that maps a plurality of physical memory locations to corresponding virtual address and has an entry, wherein the entry indicates a first physical memory location that corresponds to a virtual address; a processor that when operational generates a message, wherein the message indicates a second physical memory location and the virtual address to which it corresponds; an memory management unit (MMU) that communicates with the processor when the system is operational, said MMU comprising a cache containing at least one of the physical memory locations to corresponding virtual address translations stored in the address translation table and that, when operational, receives the message from the processor and directly updates the entry in the address translation table to indicate the second physical memory location thereby relieving the processor from the task of updating the address translation table; and a tree structure located within the address translation table, wherein the tree structure comprises a first intermediate entry that indicates the first physical memory location, and a second intermediate entry that has a pointer to the first intermediate entry wherein the tree structure is a first tree structure, and wherein the processor creates a second tree structure comprising a first intermediate entry that has a pointer to the second physical memory location, and a second intermediate entry that has a pointer to the first intermediate entry of the second tree structure.