Patent ID: 8863054

Claim:
A circuit verification method for a deeply embedded portion of a logic pipeline circuit, the method comprising: for the deeply embedded portion of the logic pipeline circuit, the deeply embedded portion comprising one or more inputs that are directly inaccessible to an external processing device executing a first computer code to simulate operation of the logic pipeline circuit, the external processing device being external to the logic pipeline circuit, executing, with the external processing device, a second computer code to simulate operation of the deeply embedded portion, the external processing device having direct access to the one or more inputs of the deeply embedded portion when executing the second computer code; directly forcing, with the external processing device executing the second computer code, the one or more inputs of the deeply embedded portion to one or more known values; receiving, by the external processing device, an output signal from the deeply embedded portion of the logic pipeline circuit, the output signal being based on the one or more inputs forced to the one or more known values; and verifying, with the external processing device, operation of the deeply embedded portion based on a comparison of the received output signal and an expected value, the expected value being a value that the deeply embedded portion is expected to output in response to directly forcing the one more inputs to the one or more known values.