Patent ID: 8732631

Claim:
A method for handling violations during verification of a design configuration, the method comprising: receiving, at one or more computer systems, information indicative of a first set of geometric shapes for each layer of the design configuration; receiving, at the one or more computer systems, information indicative of a set of design rules, each design rule in the set of design rules indicative of a series of one or more primitive operations; generating, with one or more processors associated with the one or more computer systems, a second set of geometry shapes for a first layer of the design configuration as a result of one or more primitive operations; and generating, with one or more processors associated with the one or more computer systems, a list of fix information for the first layer of the design configuration in response to a verification of the second set of geometry shapes for the first layer of the design configuration based on a first primitive operation and a list of fix information for a second layer of the design configuration generated in response to a verification of a third set of geometry shapes for the second layer of the design configuration based on a second primitive operation that precedes the first primitive operation, wherein each element in the lists of fix information comprises at least a pair of edges indicative of a verification violation and a displacement needed to resolve that violation.