Patent ID: 6944055

Claim:
A semiconductor memory device comprising: a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which stores n bits data (3<n, n being an integer); a plurality of bit lines connected to said plurality of memory cells arranged in the column direction; a plurality of word lines connected to said plurality of memory cells arranged in the row direction; a plurality of data storage circuits which are connected to said plurality of bit lines in a one-to-one correspondence; a first latch circuit included in each of the data storage circuits, which store one of the input data and the output data; a second latch circuit included in each of the data storage circuits; a write circuit, which writes the input data stored in one of the first latch circuit to the memory cells; and a write verify circuit which verifies the data of the memory cells, the data verified by the write verify circuit is stored in another latch circuit of the second latch circuit.