Patent ID: 7251164

Claim:
An integrated circuit device comprising: a memory cell array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region and separated therefrom by a gate dielectric; and wherein the memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region; and wherein each memory cell includes one or more operating or response characteristics and wherein the plurality of memory cells includes variations in operating or response characteristics; and operating characteristics adjustment circuitry, coupled to the memory cell array, to generate one or more signals to responsively adjust one or more operating or response characteristics of at least one predetermined memory cell of the plurality of memory cells, wherein the adjusted one or more operating or response characteristics of the at least one predetermined memory cell reduces a statistical variation of the operating or response characteristics of the plurality of memory cells of the memory cell array.