Patent ID: 6985842

Claim:
A model for representing a bidirectional wire input/output (I/O) during computer simulation of an electronic device, the model being tangibly embodied in a computer readable memory unit that comprises a Hardware Description Language (HDL) application program therein, the model being adapted to be used in a computer simulation of the electronic device by executing the HDL application program on a processor of a computer system, the model comprising: a) a first path between a first port and a second port, the first path including a second NMOS device; b) a second path between the second port and the first port, the second path including a first NMOS device; and c) a control mechanism, the control mechanism checking signal values (S 1 ) on the first port and signal values (S 2 ) on the second port when a change is detected on the first port or the second port, the control mechanism enabling the second NMOS device when a change is detected on the first port and the first port does not equal the second port, the control mechanism enabling the first NMOS device when a change is detected on the second port and the first port does not equal the second port, wherein the second path further includes a third NMOS device and wherein the first path further includes a fourth NMOS device, wherein the third and fourth NMOS devices are tied on to function as pass data-devices, wherein the first path and second path are electrically in parallel, wherein the second NMOS device and the fourth NMOS device are electrically in series within the first path, wherein the first NMOS device and the third NMOS device are electrically in series within the second path, wherein the gates of the third and the forth NMOS devices are held high throughout the computer simulation of the electronic device, wherein the control mechanism comprises a first control output C 1 directly coupled to the gate of the first NMOS device and a second control output C 2 directly coupled to the gate of the second NMOS device, wherein the signal values (S 1 ) at the first port are directly coupled to a source/drain of the first NMOS device, and wherein the signal values (S 2 ) at the second port are directly coupled to a source/drain of the second NMOS device.