Patent ID: 7548484

Claim:
A semiconductor memory device, comprising: a cell matrix including a plurality of cells; a column decoding unit having a plurality of column decoders to selectively activate the cells in response to code signals containing column address information for the cells, wherein each of the column decoders includes: a pre-driving unit to provide a state output signal transitioning between a power supply voltage and a source voltage in response to the code signals; and a driving unit to output a column selection signal to activate a corresponding one of the cells in response to the state output signal, wherein each of the pre-driving unit and the driving unit includes at least one PMOS transistor and at least one NMOS transistor to receive a pumping voltage and a back-bias voltage, respectively, through their bulk, and the pre-driving unit receives the back-bias voltage as a source voltage in an active mode, the pumping voltage having a voltage level higher than that of the power supply voltage and the back-bias voltage having a voltage level lower than that of a ground voltage.