Patent ID: 7892918

Claim:
A method of fabricating a wiring structure in a semiconductor device, the method comprising: forming a first insulation layer on a substrate having a first contact region and a second contact region; forming a first pad and a second pad on the first contact region and the second contact region, respectively, the first and the second pads being higher than the first insulation layer; forming a blocking layer pattern on the first insulation layer between the first pad and the second pad, the blocking layer pattern being higher than the first pad and the second pad; forming a second insulation layer on the blocking layer pattern, the first pad and the second pad; forming an opening by partially etching the second insulation layer to expose the first pad and the blocking layer pattern; forming a spacer on a sidewall of the opening; and forming a plug on the first pad to fill the opening, wherein forming the first insulation layer and forming the first and the second pads comprise: forming a preliminary first insulation layer on the substrate; partially etching the preliminary first insulation layer to form contact holes exposing the first and the second contact regions; forming the first and the second pads in the contact holes, respectively; and partially removing the preliminary first insulation layer to form the first insulation layer.