Patent ID: 8222707

Claim:
A semiconductor package structure, comprising: a substrate having an accommodating portion, a through hole, a first surface and a second surface opposite to the first surface, wherein the accommodating portion and the through hole are extended to the second surface from the first surface; a sensing chip disposed in the accommodating portion, wherein the sensing chip has an active surface and a chip surface opposite to the active surface and comprises a pad located on the active surface; a first patterned conductive layer formed on the first surface; a hole conductive layer formed on the through hole and connected to the first patterned conductive layer; a second patterned conductive layer formed on the second surface and connected to the hole conductive layer; an electrical connection portion used for electrically connecting the pad and the first patterned conductive layer; a die attach film (DAF) adhered to the chip surface; and a dielectric layer covering the first patterned conductive layer, the sensing chip, the electrical connection portion, the second patterned conductive layer and the die attach film, wherein the dielectric layer has a first aperture and a second aperture, the first aperture exposes a part of the active surface, and the second aperture exposes a part of the second patterned conductive layer.