Patent ID: 8541848

Claim:
A semiconductor device, which is disposed on a semiconductor substrate having an upper surface, the semiconductor device comprising: a source region disposed near the upper surface of the semiconductor substrate and having a first conductivity type; a drain disposed near the upper surface of the semiconductor substrate and having the first conductivity type, the drain spaced apart from the source region; a field oxide region disposed over the upper surface of the semiconductor substrate between the source and the drain; a gate electrode disposed over the upper surface of the semiconductor substrate and disposed between the field oxide region and the source, wherein a gate dielectric is sandwiched between the gate electrode and the upper surface of the semiconductor substrate to provide electrical isolation there between; a current diversion region disposed in the semiconductor substrate under a portion of the drain nearest the source region, the current diversion region having a second conductivity type opposite the first conductivity type and arranged to divert current flow between source and drain thereunder to limit current crowding at the portion of the drain nearest the source region; and a conductive field plate disposed over a portion of the field oxide near the drain, wherein the current diversion region is self-aligned with respect to the conductive field plate.