Patent ID: 7745291

Claim:
A method comprising: forming, in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; partially filling each of the trenches with a dielectric material that covers the first and second sidewalls; filling a remaining portion of the trenches with a conductive material to form first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from near a bottom of the mesa to a top surface of the semiconductor substrate; forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the lower portion of the mesa; forming a gate embedded within the dielectric material adjacent the body region, the gate being insulated from the body region and the fist and second field plates; forming a drain region of the first conductivity type at the bottom of the mesa, the drain region being connected to the drift region; forming a source electrode connected to the source region; and forming a drain electrode connected to the substrate.