Patent ID: 8148789

Claim:
A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a selection gate transistor controlling whether to conduct current to the memory strings, wherein each of the memory strings comprises: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; a plurality of first conductive layers contacting the block insulation layer; and a first sealing/insulating layer formed to seal the top of the space made by the first air gap, the charge accumulation layer being continuously formed over the plurality of memory cells, the selection gate transistor comprises: a second columnar semiconductor layer formed in contact with the top or bottom surface of the first columnar semiconductor layer and extending in a direction perpendicular to the substrate; and a second conductive layer formed along the second columnar semiconductor layer, the first sealing/insulating layer is formed in a position different from a position between the second columnar semiconductor layer and the second conductive layer.