Patent ID: 8120205

Claim:
A system comprising: a communication bus; and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current, wherein each POL regulator has a respective phase in the current sharing arrangement, wherein each POL regulator is configured to transmit and receive information over the bus according to a bus communication protocol corresponding to the bus; wherein each POL regulator is configured to autonomously add and drop its phase as required by the system, by sequentially manipulating, over a programmable number of switch cycles, a respective pulse width of each of a couple of respective gate signals respectively controlling a high-side field effect transistor (FET) and a low-side FET in the POL regulator's output stage.