Patent ID: 8315097

Claim:
A nonvolatile semiconductor memory device, comprising: a memory string configured by a plurality of memory transistors and a spare memory transistor connected in series, the memory transistors and the spare memory transistor being electrically rewritable; word lines connected to gates of the memory transistors; a spare word line connected to a gate of the spare memory transistor; and a control circuit configured to control a voltage supplied to the memory string, the memory string comprising: a first semiconductor layer extending in a perpendicular direction with respect to a substrate and configured to function as a body of the memory transistors and as a body of the spare memory transistor; a charge storage layer formed to surround a side surface of the first semiconductor layer; a plurality of first conductive layers formed to surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, the first conductive layers being configured to function as the gates of the memory transistors and as the word lines; and a second conductive layer formed to surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, the second conductive layer being configured to function as the gate of the spare memory transistor and as the spare word line, the control circuit being configured capable of driving the spare word line in place of the word lines.