Patent ID: 7485518

Claim:
A method of forming a semiconductor structure comprising: forming a first multilayered structure comprising a relaxed SiGe alloy layer, a biaxial tensile strained Si layer located on a surface of said relaxed SiGe alloy layer, and a tensile-strained epitxial SiGe alloy layer located on a surface of said biaxial tensile strained Si layer, wherein said tensile-strained epitxial SiGe alloy contains a lower Ge content than said relaxed SiGe alloy layer; bonding said first multilayered structure to an insulating layer of a second multilayered structure on a surface opposite said relaxed SiGe alloy layer, said bonding includes contacting said first multilayered structure and said second multilayered structure and annealing, wherein said contacting is performed in the presence of an external force and at a temperature from about 15° to about 40° C; removing said relaxed SiGe alloy layer to expose a surface of said biaxial tensile strained Si layer; and forming at least one field effect transistor on said biaxial tensile strained Si layer.