Patent ID: 7616859

Claim:
A semiconductor device comprising: a first conductive-type semiconductor substrate having a first side and a second side opposite to the first side; a transistor region including a second conductive-type base layer formed to a surface portion of the first side of the substrate, a plurality of insulated gate trenches formed to the base layer, a second conductive-type first diffusion layer formed to a surface portion of the second side of the substrate, and an emitter electrode formed on the first side of the substrate; and a diode region coupled in antiparallel with the transistor region and including a first conductive-type second diffusion layer formed to the surface portion of the second side of the substrate, the second diffusion layer having a higher impurity concentration than the substrate; wherein the diode region includes a plurality of diode cells that are repeatedly arranged and grouped together to form a diode, wherein the transistor region includes a cell region and a boundary region located between the cell region and the diode region, wherein in the cell region, the base layer is divided by the plurality of insulated gate trenches into a plurality of body regions and a plurality of floating regions, the body and floating regions being alternately arranged, each body region being connected to the emitter electrode, each floating region being disconnected from the emitter electrode, wherein the cell region includes a plurality of spaced-channel insulated-gate bipolar transistor cells that are repeatedly arranged and grouped together to form a spaced-channel insulated-gate bipolar transistor, each transistor cell having a corresponding one of the plurality of body regions and a corresponding one of the plurality of floating regions, wherein in the boundary region, the base layer is divided by the plurality of insulated gate trenches into a plurality of divided regions, and wherein a first spacing between adjacent insulated gate trenches in the boundary region is less than a second spacing between adjacent insulated gate trenches between which each floating region is located in the cell region.