Patent ID: 8071969

Claim:
A semiconductor memory device comprising: a substrate; a first interconnect layer having a plurality of first potential supply lines extending in a first direction; a second interconnect layer having a plurality of second potential supply lines extending in a second direction crossing the first direction; a variable resistance film located between the first potential supply line and the second potential supply line; a diode located between the variable resistance film and one of the first potential supply line and the second potential supply line sandwiching the variable resistance film, the one potential supply line being located nearer to the substrate, the diode extending along the potential supply line located nearer to the substrate and passing a current in a direction from the first potential supply line to the second potential supply line; and an upper electrode film located between the variable resistance film and one of the first potential supply line and the second potential supply line sandwiching the variable resistance film, the one potential supply line being located farther from the substrate, wherein: the first interconnect layer and the second interconnect layer are alternately stacked on the substrate, a region of an upper surface of the diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region, and the diode is laterally thicker than the upper electrode film.