Patent ID: 7485520

Claim:
A method of manufacturing a semiconductor structure, comprising: forming a semiconductor fin containing a silicon layer and a silicon germanium layer on a semiconductor substrate, wherein said silicon germanium layer is located directly beneath said silicon layer and said silicon germanium layer has an atomic concentration of germanium from about 2 to about 15 percent; forming a silicon oxide layer directly on said semiconductor substrate and sidewalls of said silicon germanium layer, wherein said silicon oxide layer is disjoined from said silicon layer; forming a silicon germanium oxide ring on said semiconductor fin out of said silicon germanium layer; forming a gate dielectric directly on said semiconductor fin; forming a gate conductor directly on said gate dielectric; removing portions of said silicon germanium ring from outside an area of said gate conductor to from two disjoined silicon germanium oxide blocks abutting said gate conductor; removing said silicon germanium alloy layer from end portions of said semiconductor fin by a substantially isotropic etch, wherein a remaining portion of said silicon germanium alloy layer in a center portion of said semiconductor fin constitutes a semiconductor pedestal providing an electrically conductive path between said semiconductor fin and said semiconductor substrate; and forming source and drain regions within said end portions of said semiconductor fin, wherein the remainder of said semiconductor fin not including said source and drain regions constitutes a body, said body and said semiconductor pedestal and said semiconductor substrate are doped with dopants of a first conductivity type, said source and drain regions are doped with dopants of a second conductivity type, and said second conductivity type is the opposite of said first conductivity type.