Patent ID: 8423342

Claim:
A simulation parameter extracting method of a MOS transistor that extracts a true gate-overlap capacitance serving as a capacitance of a part in which the gate overlaps the source or the drain, the gate-overlap capacitance being one of parameters used for a simulation of the MOS transistor, the method comprising: evaluating a measured value that includes the gate-overlap capacitance by measuring a capacitance between the gate and the drain in each of a plurality of layout patterns at a predetermined bias voltage, the layout patterns including contact plugs that are arranged on and electrically connected to the source and the drain, the number of the contact plugs being different for each layout pattern, other configurations of the layout patterns than the number of the contact plugs being the same for each layout pattern; evaluating, by using a computer processor, a gate-overlap capacitance calculation value of each of the plurality of the layout patterns by subtracting a contact parasitic capacitance between the contact plug and the gate from the measured value, the contact parasitic capacitance being obtained by a simulation with varying a model parameter for evaluating a parasitic capacitance between the contact plug and the gate; and extracting the gate-overlap capacitance calculation value as the gate-overlap capacitance at the model parameter when the gate-overlap capacitance calculation value is about constant regardless of the number of the contact plugs.