Patent ID: 7115930

Claim:
A semiconductor memory device comprising: a first select transistor formed on an upper surface of a substrate and having a first multi-layer gate; a second select transistor formed on the upper surface of the substrate and having a second multi-layer gate; a first stepped portion formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of said substrate; a second stepped portion formed by etching the substrate adjacent to the second multi-layer gate of the second select transistor such that the second stepped portion forms a cavity in the upper surface of said substrate; a first contact plug formed in a region of the first stepped portion, the first contact plug being partially in contact with the first stepped portion; a second contact plug formed in a region of the second stepped portion, the second contact plug being partially in contact with the second stepped portion; a first insulating film formed between the first contact plug and the first multi-layer gate, the first insulating film being partially in contact with the first stepped portion; a second insulating film formed between the second contact plug and the first multi-layer gate, the second insulating film being partially in contact with the second stepped portion; a memory cell unit including at least one memory cell transistor formed between the first select transistor and the second select transistor, each memory cell including an impurity diffusion layer; and a third stepped portion formed by etching the substrate adjacent to each memory cell such that at least part of the third stepped portion forms a cavity in the upper surface of said substrate.