Patent ID: 8501580

Claim:
A process for fabricating a semiconductor device having reduced capacitance for high frequency circuit protection comprising: depositing n-type dopant material by solid or gas phase deposition, or implant n-type material using ion implantation to a polished side, top surface of a device wafer that serves as an n-type substrate; forming an n+ buried layer by driving the n-type dopant material into the device wafer; forming an intermediate layer by growing a thermal oxide layer and/or then depositing plasma-enhanced oxide, TEOS oxide, or polysilicon; performing a direct wafer bonding procedure using a handling substrate of either p-type or n-type wafer by bonding the device wafer with the handling substrate and then annealing; then grinding and polishing from the back side of the device wafer up to a remaining device layer forming trenches that surround the device region with depth extending from the top surface, going through the n+ buried layer and reaching down to the intermediate layer and then forming an n+ layer on the sidewalls of the trenches by solid or gas phase deposition or ion implantation; filling the trenches by growing a layer of thermal oxide on the sidewalls of the trenches and followed by deposition of plasma enhanced oxide, nitride, TEOS oxide, CVD oxide, or polysilicon into the trenches and then planarizing the top surface by plasma etch back or polishing; forming n+ region of the device by forming an oxide layer on the top surface of the device layer and then etching the oxide by photolithography, then depositing n-type dopant material by solid or gas phase deposition or ion implantation and then driving in by high temperature diffusion; forming p+ region of the device by etching the oxide using photolithography, then depositing p-type dopant material by solid or gas phase deposition or ion implantation and then driving in by high temperature diffusion so that the breakdown voltage between cathode and anode of the device is set to a targeted voltage for high frequency circuit protection.