Patent ID: 7410838

Claim:
A method for fabricating a memory cell, comprising: forming a first conductive line and a first diode component on a substrate sequentially; forming a dielectric layer on the substrate covering the first conductive line and the first diode component; etching the dielectric layer to create an opening exposing the first diode component; forming a stack filling the opening, comprising a second diode component, a buffer layer and an anti-fuse layer; and forming a second conductive line on the dielectric layer, connecting the stack and generally perpendicularly to the first conductive line, wherein the dielectric layer is formed before the stack of the second diode component, the buffer layer and the anti-fuse layer is filled, and wherein the stack is formed by the steps of: oxidizing a surface of the first diode component to create an oxide layer to act as the anti-fuse layer; filling the opening with silicon to form a silicon column contacting the anti-fuse layer; and performing an ion implantation to the silicon column to form a heavily doped upper portion of the silicon column as the buffer layer and a lightly doped lower portion of the silicon column as the second diode component.