Patent ID: 7683405

Claim:
A MOS transistor, comprising: a semiconductor substrate having a first recess and a second recess therein; a gate electrode on the semiconductor substrate between the first recess and the second recess; a first impurity doped region in the semiconductor substrate below the first recess; a second impurity doped region in the semiconductor substrate below the second recess; an impurity doped epitaxial layer on the first impurity doped region and on the second impurity doped region that at least partially fills the first recess and the second recess; and a metal silicide layer on the impurity doped epitaxial layer, wherein an impurity concentration of the impurity doped epitaxial layer has a gradient in a vertical direction, and wherein a peak impurity concentration of the impurity doped epitaxial layer is near a top surface of the impurity doped epitaxial layer.