Patent ID: 7759995

Claim:
A semiconductor integrated circuit comprising: a first p-channel MOS transistor which has a first current path and a first gate, first input data being input to one end of the first current path, the other end of the first current path outputting a first control signal, and a reference voltage being supplied to the first gate; a second p-channel MOS transistor which has a second current path and a second gate, the first control signal being input to the second gate, and a power supply voltage being supplied to one end of the second current path; a first n-channel MOS transistor which has a third current path and a third gate, the first input data being input to one end of the third current path, the other end of the third current path outputting a second control signal, and the power supply voltage being supplied to the third gate; a second n-channel MOS transistor which has a fourth current path and a fourth gate, the second control signal being input to the fourth gate; a third p-channel MOS transistor which has a fifth current path and a fifth gate, second input data being input to one end of the fifth current path, the other end of the fifth current path outputting a third control signal, and the reference voltage being supplied to the fifth gate; a fourth p-channel MOS transistor which has a sixth current path and a sixth gate, the third control signal being input to the sixth gate, one end of the sixth current path being connected to one end of the fourth current path of the second n-channel MOS transistor and to the other end of the second current path of the second p-channel MOS transistor, the power supply voltage being supplied to the other end of the sixth current path; a third n-channel MOS transistor which has a seventh current path and a seventh gate, the second input data being input to one end of the seventh current path, the other end of the seventh current path outputting a fourth control signal, and the power supply voltage being supplied to the seventh gate; and a fourth n-channel MOS transistor which has an eighth current path and an eighth gate, the fourth control signal being input to the eighth gate, one end of the eighth current path being connected to the other end of the fourth current path of the second n-channel MOS transistor, and the reference voltage being supplied to the other end of the eighth current path.