Patent ID: 6979522

Claim:
A method for exposing at least two semiconductor wafers in an exposure tool, the method which comprises: providing a first semiconductor wafer to the exposure tool for exposing the first semiconductor wafer; aligning the first semiconductor wafer using determined values of a first set of alignment parameters that depend on characteristics of the two semiconductor wafers; exposing the first semiconductor wafer with a first pattern using a combination of the first set of alignment parameters and a second set of alignment parameters that account for an exposure tool-offset; calculating values of a set of parameters representing an overlay accuracy of the first pattern on the first semiconductor wafer using a formula for each of the parameters of the set representing the overlay accuracy, the formula being a function of each of the alignment parameters of the first set; adjusting values of the second set of alignment parameters to correct for an overlay inaccuracy of the first pattern; and aligning the second semiconductor wafer in response to the values of the second set of alignment parameters that have been adjusted and exposing the second semiconductor wafer.