Patent ID: 7945874

Claim:
A method comprising designing a driver with matching stages having matched transistors, wherein said designing by using a computer comprises: interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage; determining a size of the transistors using the results of interpreting of the offset and re-determining the size until a simulated yield of the driver obtained by a simulation using measured matching information and the determined size of the transistors approximates a targeted yield; using a resulting determined size to fabricate the driver and obtaining a test yield of the manufactured driver; and if the test yield is not the targeted yield, adjusting the measured matching information until the adjusted yield of the driver obtained by the simulation approximates the test yield, wherein the driver corresponds to a source driver having a plurality of buffers and the matching stage is included in the respective buffer, wherein the matching stage comprises input stages having transistors matched to each other and active load stages having transistor matched to each other, wherein in the step of determining the size of the transistors, an area of the input stage is increased according to the difference in threshold voltage in the input stage, and an area of the active load stage is increased according to the difference in threshold voltage in the active load stage, and wherein the step of determining the size of the transistors further comprising reducing a transconductance of the active load stage, increasing a transconductance of the input stage, and increasing a length of the active load stage for reducing the offset.