Patent ID: 7160816

Claim:
A method for fabricating a semiconductor device, comprising the steps of: forming a plurality of gate line patterns on a substrate with a defined cell region and a peripheral circuit region; forming sequentially a first insulation layer and a second insulation layer; forming a first mask layer covering the cell region on the second insulation layer in the cell region and forming a second mask layer in the peripheral circuit region, wherein the second mask layer is separated from the first mask layer; etching the second insulation layer with use of the first and the second mask layers as an etch mask to form a spacer at both sidewalls of each gate line pattern in the peripheral region and simultaneously form a guard beneath the second mask layer; removing the first and the second mask layers; forming a third mask layer covering the whole regions of the peripheral circuit region including a guard region, thereby opening the cell region; and performing a wet etching process to the second insulation layer remaining in the cell region by using the third mask layer as an etch mask.