Patent ID: 6915406

Claim:
An address translation apparatus comprising: an address translation buffer including an operand address translation buffer, which stores operand address translation data for translation of an operand virtual address into a physical address, and an instruction address translation buffer, which stores instruction address translation data for translation of an instruction virtual address into a physical address, the operand address translation buffer and the instruction address translation buffer having a fixed area and sharing the same memory; an operand access control unit that carries out control to execute an operand access with priority, and to hold an instruction virtual address corresponding to an instruction access, when an access collision has occurred that the operand access to the operand address translation buffer and the instruction access to the instruction address translation buffer are generated at the same time; and an instruction access control unit that carries out control to execute an instruction access after finishing the operand access, and to translate the instruction virtual address held into a physical address based on data stored in the instruction address translation buffer.