Patent ID: 7839193

Claim:
A method of operating a duty cycle correction circuit, comprising: maintaining a state of a duty cycle corrected signal; generating a first transition in the state of the duty cycle corrected signal responsive to an input signal; generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal; generating a delay control signal responsive to a plurality of phase-shifted versions of the input signal using a plurality of delay flip-flops; and generating a delayed version of the input signal using a delay locked loop circuit responsive to the delay control signal; wherein a first one of the plurality of delay flip-flops is responsive to a first one of the plurality of phase shifted versions of the input signal at a data input thereof and is responsive to a second one of the plurality of phase shifted versions of the input signal at a clock input thereof; and wherein a second one of the plurality of flip-flops is responsive to the second one of the plurality of phase shifted versions of the input signal at a data input thereof and is responsive to the first one of the plurality of phase shifted versions of the input signal at a clock input thereof.