Patent ID: 8898434

Claim:
A processor apparatus, comprising: at least one central processing unit core (CPU); first logic in said CPU operable to implement a simultaneous multithreaded (SMT) operational mode in said CPU wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing a cache memory resource within said CPU; second logic in said CPU operable to implement an autothread (AT) operational mode in said CPU; third logic in said CPU operable to determine as part of said AT operational mode (1) whether there is a resource conflict between said hardware threads and (2) whether said resource conflict undermines instruction execution throughput; and fourth logic in said CPU responsive to said third logic detecting a resource conflict that undermines instruction execution throughput and operable to adjust relative instruction execution rates of said hardware threads in said CPU based on relative priorities of said software threads specified to said processor apparatus by a software scheduling entity.