Patent ID: 8046650

Claim:
An integrated circuit comprising: A. a test data input lead, a test clock lead, a test mode select lead, and a test data output lead; B. test access port circuitry including: i. a TAP state machine having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input connected to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input connected to the test data in lead, a test data output, and control inputs connected to the control outputs; iv. multiplexer circuitry coupling the test data outputs of the instruction register and the data register to the test data out lead; and v. control circuitry having an input connected to the test mode select lead, a TAP control input, and an output connected to the test mode select input of the state machine; and C. device address port circuitry having a test clock input coupled to the test clock lead, a test mode select input connected to the test mode select lead, a test data input connected to the test data input lead, and a control output connected to the TAP control input.