Patent ID: 7500044

Claim:
A control unit for a first-in, first-out (FIFO) buffer for transferring data between a first clock domain corresponding to a first clock signal and a second clock domain corresponding to a second signal, the control unit comprising: a first clocked storage device clocked by the first clock signal, wherein the first clocked storage device is configured to store a first pointer to address the FIFO buffer; a second clocked storage device clocked by the second clock signal, wherein the second clocked storage device is configured to store a second pointer to address the FIFO buffer; a third clocked storage device clocked by the second clock signal, wherein the third clocked storage device is coupled to receive a third pointer that corresponds to the first pointer, the third pointer transmitted from the first clock domain to the second clock domain to be received by the third clocked storage device; a fourth clocked storage device having an input coupled to an output of the third clocked storage device and clocked by the second clock signal; a detect circuit that comprises a sample storage device configured to store a sample history of a third clock signal derived from a selected clock signal of the first clock signal and the second clock signal, wherein the samples are taken in a selected clock domain of the first clock domain and the second clock domain that is different from the clock domain of the selected clock signal, wherein the detect circuit is configured to detect rising edges of the selected clock signal responsive to the sample history, and wherein the detect circuit is further configured to detect a first run length of a plurality of possible run length in the sample history, wherein each of the plurality of possible run length has a corresponding likelihood of occurrence based on a ratio of a first frequency of the first clock signal and a second frequency of the second clock signal, and wherein the first run length has a corresponding likelihoods of the plurality of possible run lengths, and wherein the detect circuit is configured to initialize one or more values to track a phase relationship between the second clock signal and the first clock signal responsive to detecting the first run length; and a mode control unit configured to select the output of the third clocked storage device to be compared to the second pointer if a transition in a value of the third pointer, if any, meets setup and hold requirements of the third clocked storage device according to the phase relationship between the second clock signal and the first clock signal as indicated by the sample history.