Patent ID: 7510960

Claim:
A method for fabricating a connection between two transistor elements on a semiconductor substrate, comprising the steps of: providing the semiconductor substrate with a silicon layer ( 304 ) forming a first transistor element ( 304 ), a polysilicon layer ( 306 ) forming a second transistor element ( 306 ), a first side spacer ( 312 A) on one side of second transistor element ( 306 ) and a second side spacer ( 312 A) on an opposite side of the second transistor element ( 306 ), and a dielectric layer ( 316 ) overlying the first transistor element ( 304 ), the second transistor element ( 306 ), and the third dielectric layer ( 312 ); applying a layer of photo resist ( 318 ) over an upper surface of the dielectric layer ( 316 ); photo patterning said photo resist layer to form at least first and second contact areas ( 308 A, 309 A) with an area of photo resist ( 318 A) therebetween; forming at least first and second cavities ( 320 A, 320 B) corresponding to the at least first and second contact areas ( 308 A, 309 A) extending through the photo resist layer ( 318 ) to the dielectric layer ( 316 ) with a region ( 318 B) of the photo resist remaining therebetween; etching the dielectric layer ( 316 ) through the at least first and second cavities ( 320 A, 320 B) to form at least first and second contact cavities ( 321 A, 321 B) in the fourth dielectric layer ( 316 ) and concurrently reducing the thickness of the photo resist layer ( 318 ) and resist region 318 B to form a first intermediate cavity ( 321 C) between first and second contact cavities ( 321 A, 321 B) and a first separation region ( 316 A) of the dielectric layer ( 316 ) between the first and second contact cavities ( 320 A, 320 B); further etching the dielectric layer ( 316 ) until the first contact cavity ( 321 B) contacts the first transistor element ( 304 ), the second contact cavity ( 321 A) contacts the second transistor element ( 306 ), the first intermediate cavity ( 321 C) extends between contact cavities ( 321 A, 321 B) and down to the first separation region ( 316 A) of the dielectric layer ( 316 ) between contact cavities ( 320 A, 320 B); and depositing conductive metal in the first and second contact cavities ( 324 A, 324 B) and in the intermediate cavity ( 320 C) to form a first, a second and an intermediate conductive metal pillar 324 A, 324 B and 324 C.