Patent ID: 8155257

Claim:
A synchronizing circuit comprising: numerically controlled oscillating means for generating a signal of a predetermined phase; phase rotating means for rotating a phase of a symbol of a demodulated signal obtained by demodulating a modulated signal resulting from digital modulation of a carrier according to the signal of said predetermined phase, said demodulated signal including an I-component in phase with said carrier and a Q-component orthogonal to said carrier; phase error estimating means for estimating a phase error from the rotated phase of the symbol of said demodulated signal; a loop filter for filtering said phase error and controlling said numerically controlled oscillating means according to a result of the filtering; and gain controlling means for controlling first and second gains of said loop filter in symbol units of said demodulated signal, the symbol units forming one of (a) a known section as a section of known symbols and (b) a main signal section as a section of main signal symbols; wherein said gain controlling means controls said first and second gains so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of said known section to a predetermined symbol; phase error average calculating means for calculating an average value of the phase error in said known start section; and adding means for adding the calculated said average value to a phase correction quantity as output of said loop filter; wherein said gain controlling means controls said first and second gains such that phase error correction in said known start section is stopped in said loop filter, said adding means adds said average value to said phase correction quantity when the symbol of said demodulated signal becomes the predetermined symbol, and said numerically controlled oscillating means generates the signal of said predetermined phase according to the phase correction quantity to which said average value is added.