Patent ID: 7912989

Claim:
A network interface through which a resident device connects with a network to communicate with an opposite node on said network, said network interface comprising: one or more driving clock generation circuits; a PLL circuit configured to provide a clock signal to said one or more driving clock generation circuits; and a driving control circuit configured to control said PLL circuit and said one or more driving clock generation circuits to stop generation of clock signals by said one or more driving clock generation circuits in said network interface and to stop generation of the clock signal by the PLL circuit, when a disconnect mode is established when said opposite node is not connected to said network, wherein said driving control circuit controls said PLL circuit to resume generation of said clock signal when a release condition of said disconnect mode of said network interface is satisfied, and controls said one or more driving clock generation circuits to resume said generation of clock signals, when a predetermined time elapses after said release condition of said disconnect mode of said network interface is satisfied; wherein said driving control circuit of said network interface includes a timer which determines whether said predetermined time has elapsed after said release condition has been satisfied.