Patent ID: 8685809

Claim:
A method of forming a semiconductor structure having reduced contact resistance comprising: forming at least one field effect transistor on a surface of a semiconductor substrate; forming a source diffusion region and a drain diffusion region within said semiconductor substrate at a footprint of said at least one field effect transistor; patterning said source diffusion region and said drain diffusion region utilizing a self-assembled block copolymer as an etch mask; etching to form an ordered, nanosized pattern within each of said source diffusion region and drain diffusion region, wherein said ordered nanosized pattern comprises a plurality of openings extending into a semiconductor material of said source diffusion region and said drain diffusion region, each opening has a pair of vertical sidewalls and a planar bottommost surface portion; and forming a conductive material comprising a metal semiconductor alloy directly contacting an uppermost semiconductor surface of said source diffusion region and said drain diffusion region located adjacent to each opening, and directly contacting said semiconductor material of said source diffusion region and said drain diffusion region located at said sidewalls and said planar bottommost surface portion of each of said openings, wherein said conductive material within said opening does not completely fill each of said openings.