Patent ID: 8661204

Claim:
A method in a shared-memory multiprocessor of decoupling a detection of conflicting concurrent accesses to memory from an action taken in response to the detected conflicts, the method comprising: providing a plurality of processor cores, each processor core of said plurality of processor cores having one or more local caches; permitting software on each processor core of said plurality of processor cores to specify that certain reads and writes are speculative and should commit together as a transaction, or be rolled back; permitting said local caches of said plurality of processor cores to retain copies of speculatively read or written lines despite an occurrence of conflicting concurrent speculative reads or writes; monitoring activities of said plurality of processor cores for an occurrence of one or more of said conflicting concurrent speculative reads or writes and summarizing said occurrences in one or more conflict summary tables (CST) for each processor core of said plurality of processor cores as a software-visible indication of zero or more other processor cores of said plurality of processor cores on which concurrent speculative reads or writes that conflict with speculative reads or writes of said processor core have occurred; and ensuring that transactions commit atomically and memory remains consistent provided that requests by software to commit a transaction are made only in an absence of concurrent nonspeculative or committed reads or writes that conflict with the reads or writes of the transaction.