Patent ID: 8103854

Claim:
An apparatus for parallel processing comprising: a plurality of processing elements (PEs); a local PE instruction memory (PE Imem) associated with each PE and containing local PE instructions for execution locally on the associated PE; a local PE very long instruction word (VLIW) memory associated with each PE and containing at addressable locations local PE VLIWs each having a plurality of slot instructions for execution in parallel locally on the associated PE; and a VLIW memory (VIM) controller in each PE that is used to select between SIMD instructions fetched and distributed by a control function in parallel to multiple PEs, the local PE instructions fetched from the local PE Imem, and the local PE VLIWs fetched from the local PE VLIW memory, wherein each PE is initialized to receive the distributed SIMD instructions and wherein each PE receiving a distributed thread start (Tstart) instruction causes instruction path selection logic to switch from receiving the distributed SIMD instructions to fetching the local PE VLIWs, each PE local VLIW fetched in response to a fetched local PE instruction, wherein the instruction path selection logic switches back to receiving the distributed SIMD instructions in response to determining a thread stop instruction has been received and the thread stop instruction encoded to execute a PE instruction in the shadow of the thread stop instruction and wherein each PE further comprises local hold generation logic that is responsive to the thread stop instruction fetched from the local PE Imem to generate a PE hold signal which is returned to the control function.