Patent ID: 7929655

Claim:
A system adapted to control transfer of a signal sequence in a first clock domain to a plurality of other clock domains, the first clock domain comprising first circuitry having an input adapted to receive a signal from the signal sequence and an output adapted to output the signal in dependence on a first clock signal to the plurality of other clock domains, the signal at the output of the first circuitry having a first state, and wherein each of the plurality of other clock domains comprises circuitry adapted to transmit a signal representing the first state in dependence on the respective clock signal, the system comprising: detecting circuitry adapted to detect receipt of the signals from the plurality of other clock domains and to provide an update signal when all of the signals received from the plurality of other clock domains have a common state; and gating circuitry adapted to receive the update signal and, in response to the update signal, to allow a next signal in the signal sequence to be received at the input of the first circuitry, wherein the detecting circuitry comprises comparator circuitry adapted to compare the signal at the output of the first circuitry with the common state and to provide the update signal based on the comparison.