Patent ID: 8148260

Claim:
A method of forming a memory device, comprising: forming a buried contact pad and a bit line on a semiconductor substrate; forming a buried contact plug on one side of the bit line and connected to the buried contact pad; forming a bit line contact pad and a bit line contact plug connected to the bit line contact pad on the semiconductor substrate; forming an interlayer insulating layer between the bit line contact pad, the bit line contact plug, the bit line, the buried contact pad and the buried contact plug; and forming a buried contact spacer between the buried contact plug and the bit line, wherein the buried contact plug has a width that is greater at a part near a top surface of the buried contact pad than on one side of the bit line, and wherein forming the buried contact plug includes, forming a buried contact hole exposing a portion of the buried contact pad and laterally expanding under the bit line to form an expanded lower region of the buried contact hole, forming a first buried contact plug in the expanded lower region of the buried contact hole and connected to the buried contact pad; and forming a second buried contact plug on the first buried contact plug, the second buried contact plug filling an upper region of the buried contact hole, wherein forming the buried contact hole further includes, patterning the interlayer insulating layer to form a preliminary buried contact hole having a bottom surface lower than a bottom surface of the bit line, and forming a bit line spacer on a sidewall of the preliminary buried contact hole, wherein the bit line spacer is formed to have a bottom surface lower than the bottom surface of the bit line, and wherein the bottom surface of the buried contact spacer and a top surface of the first buried contact plug are on a same surface.