Patent ID: 8759178

Claim:
A method for manufacturing a semiconductor device comprising: a first step of forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer, in such a manner that a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer; a second step of, after the first step, forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; a third step of, after the second step, forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring, in a manner that the gate insulating film covers a periphery and a top of the pillar-shaped silicon layer, the polysilicon gate electrode covers the gate insulating film, and after the polysilicon gate electrode and the polysilicon gate wiring are formed, an upper surface of polysilicon gate electrode is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer; a fourth step of, after the third step, forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; a fifth step of, after the fourth step, depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring, in such a manner that the metal gate wiring is connected to the metal gate electrode and extends on the silicon substrate in a direction perpendicular to a direction of the fin-shaped silicon layer; and a sixth step of, after the fifth step, forming a contact so as to make direct contact between the contact and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer.