Patent ID: 7549139

Claim:
A method of operating a programmable logic device comprising: performing a timing analysis of a design of the programmable logic device having a plurality of active blocks, each active block of the plurality of active blocks having a plurality of paths; determining a plurality of timing slacks associated with a plurality of paths of an active block for each of the plurality of active blocks of the design; determining a minimum timing slack for each of the plurality of active blocks of the design; enabling, for each active block of the plurality of active blocks, the assignment of either of a first supply voltage or a second supply voltage to operate an active block; assigning the first supply voltage to operate a first set of one or more active blocks of the programmable logic device, the first supply voltage corresponding to the minimum timing slack determined for each active block in the first set; and assigning the second supply voltage, less than the first supply voltage, to operate a second set of one or more active blocks of the programmable logic device, the second supply voltage corresponding to the minimum timing slack determined for each active block in the second set, wherein minimum timing slacks determined for each active block in the first set are less than minimum timing slacks determined for each active block in the second set.