Patent ID: 8356218

Claim:
A fault location estimation device, comprising: a faulty scan chain identification unit that identifies a faulty scan chain and a fault type thereof based on a result of a scan chain operation verification test; a faulty scan flip-flop (scan FF) narrowing unit that compares a test result, as an observed value, of a faulty scan chain of a defective circuit with a simulation result for determining a faulty scan FF range beginning at a location of a scan FF where both results differ; and a path trace narrowing unit that references logic circuit configuration information, a signal line expected value, a failure-observed scan FF, and a test result of a defective circuit to extract a scan FF on the faulty scan chain, which is reached from a failure-observed scan FF observed on a normal scan chain by tracing back a failure-propagation path while performing an implication procedure for an input side and, based on a position of the extracted scan FF on the scan chain, determines a faulty scan FF range for further narrowing the faulty scan FF range determined by said faulty scan FF narrowing unit.