Patent ID: 7265583

Claim:
A voltage level conversion circuit for converting an input signal having a logical voltage corresponding to a first power supply voltage into an output signal having a logical voltage corresponding to a second power supply voltage that is higher than the first power supply voltage, and outputting the output signal, said voltage level conversion circuit comprising: a latch circuit comprising plural MOS transistors each having the second power supply voltage as a breakdown voltage, and operable to latch a non-inversion logic corresponding to the input signal at a first latch node while latching an inversion logic reverse to the input signal at a second latch node; a first N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and a ground voltage supply; a second N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second latch node and the ground voltage supply; and a transistor driving circuit having the first power supply voltage as a power supply voltage, and operable to apply, when the input signal transits, a pulse signal having a pulse height that is boosted to a level higher than the first power supply voltage, to a gate of the first N channel MOS transistor or to a gate of the second N channel MOS transistor; a third N channel MOS transistor having the first power supply voltage as a breakdown voltage, which is connected in series to the first N channel MOS transistor, between the first latch node and the ground voltage supply; and a fourth N channel MOS transistor having the first power supply voltage as a breakdown voltage, which is connected in series to the second N channel MOS transistor, between the second latch node and the ground voltage supply.