Patent ID: 7987382

Claim:
A digital sub-circuit adapted for embedding in an at least partially digital circuit to minimize the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit, the at least partially digital circuit further comprising an internal or external system clock for providing a clock signal having a phase and a frequency to the at least partially digital circuit, the digital sub-circuit comprising: a clock modulating circuit, the clock modulating circuit comprising a phase/frequency modulating circuit configured to modulate the phase and/or frequency of the clock signal before the clock signal is applied to at least part of the at least partially digital circuit, the modulated clock signal being optimized in phase and/or frequency by an optimization process to minimize switching noise of the other digital sub-circuit on the at least partially digital circuit, wherein the optimization process is based on minimizing a cost function, the cost function being a function of a supply current of the other digital sub-circuit.