Patent ID: 8185856

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: acquiring, by means of a computer system, information on a graphic composing a physical layout of a semiconductor integrated circuit; extracting from said information on the graphic a first portion having a wiring length equal to or greater than a preset length; extracting from said information on the graphic a second portion that does not meet a predetermined photolithography condition; calculating, by means of the computer system, a signal delay based on the physical layout, and obtaining a wiring associated with at least one of the first portion and the second portion not meeting a threshold for a signal delay set forth in a specification; and inserting, by means of the computer system, a repeater into a region of said graphic (a) having said wiring length equal to or greater than the preset length, and (b) not meeting the predetermined photolithography condition, in response to said calculation.