Patent ID: 8051401

Claim:
A method of generating a layout for an integrated circuit having at least a substrate upon which a plurality of gates are formed, a first metal layer overlying said substrate and a second metal layer overlying said first metal layer, said method comprising the steps of: selecting a placement upon said integrated circuit of a plurality of power connection conductors to be formed as part of said first metal layer, a plurality of routing connection conductors to be formed as part of said first metal layer and a plurality of power rail conductors to be formed as part of said second metal layer, such that: (i) said plurality of power rail conductors are disposed substantially parallel to one another across said integrated circuit; (ii) said plurality of power connection conductors are disposed at positions at least partially overlaid by said power rail conductors and providing power connections between said power rail conductors and said gates, said power connection conductors overlaid by at least one power rail conductor having a plurality of gaps therebetween in said first metal layer; and (iii) at least one of said plurality of routing connection conductors runs through one of said plurality of gaps; and extending said power connection conductors disposed at least partially overlaid by said at least one power rail conductor so as to close at least one of said plurality gaps not having a routing connection conductor running therethrough, said steps implemented on a general purpose computer.