Patent ID: 7480155

Claim:
A phase shift modulation generator for controlling a full-bridge converter, said generator comprising: inputs for receiving an N 1 +1 bit frequency value, an N 2 +1 bit phase value, and a clock signal; a first register with an N 3 +1 bit input and an N 3 +1 bit output, wherein said first register is clocked by said clock signal; a second register with an input and an output, wherein said second register is clocked by said clock signal; a first adder with an N 3 +1 bit first input, an N 3 +1 bit second input, and an N 3 +1 bit output, wherein said first input of said first adder receives said frequency value extended to a length of N 3 +1 by zero-padding, said second input of said first adder is connected to said output of said first register, and said output of said first adder is connected to said input of said first register; a second adder with a first input, a second input, and an output, wherein said second adder is configured to subtract a value on said second input from a value on said first input, and wherein N 2 +1 most significant bits of said output of said first adder are connected to said first input of said second adder, said second input of said second adder receives said phase value; and a most significant bit of said output of said second adder is connected to said input of said second register; a first delay element with an input and an output, wherein said input of said first delay element is connected to a most significant bit of said output of said first register; a first logic gate with a first input connected to said output of said first delay element and a second input connected to said most significant bit of said output of said first register; a second logic gate with a first input connected to said output of said first delay element and a second input connected to said most significant bit of said output of said first register; a second delay element with an input and an output, wherein said input of said first delay element is connected to a most significant bit of said output of said second register; a third logic gate with a first input connected to said output of said second delay element and a second input connected to said most significant bit of said output of said second register; and a fourth logic gate with a first input connected to said output of said second delay element and a second input connected to said most significant bit of said output of said second register, wherein an output of said first logic gate controls an upper transistor of a left half bridge of said converter, an output of said second logic gate controls a lower transistor of a left half bridge of said converter, an output of said third logic gate controls an upper transistor of a right half bridge of said converter, and an output of said fourth logic gate controls a lower transistor of a right half bridge of said converter.