Patent ID: 7983091

Claim:
A flash memory array comprising: a plurality of memory segments, each memory segment of the plurality of memory segments comprising a plurality of memory cell blocks, the plurality of memory cell blocks comprising a plurality of bitlines; a data cache configured to store read data of selected bitlines of a selected memory segment, wherein the selected memory segment is a memory segment from the plurality of memory segments selected for a read operation; and a plurality of segment data handlers, one segment data handler of the plurality of segment data handlers coupled between the data cache and a memory segment and each of segment data handlers other than the segment data handler coupled between the data cache and the memory segment is coupled between a pair of adjacent memory segments of the plurality of memory segments, each segment data handler configured to condition the plurality of bitlines of a memory segment coupled to the each segment data handler, wherein conditioning the plurality of bitlines of the memory segment comprises at least one of pre-charging at least one bitline to a pre-charge voltage and shielding at least one bitline to a reference potential, sense read data from at least one bitline of the plurality of bitlines of the memory segment coupled to the each segment data handler, and transmit the sensed read data to the data cache; wherein the each segment data handler transmits the sensed read data to the data cache through at least one segment data handler laid between the memory segment of the pair of adjacent memory segments and the data cache, when the each segment data handler is coupled between the pair of adjacent memory segments; and wherein the each segment data handler transmits the sensed read data to the data cache directly when the each segment data handler is coupled between the data cache and a memory segment.