Patent ID: 8848422

Claim:
A variable resistance nonvolatile memory device comprising: a memory cell array having a plurality of memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of a plurality of word lines and one of a plurality of bit lines, the variable resistance element changing a resistance value reversibly in response to an applied voltage pulse, and the current steering element carrying a current from which the current steering element is assumed to be conducting as a result of an application of a voltage exceeding a predetermined threshold voltage; a memory cell selection circuit that selects at least one of the memory cells from the memory cell array by selecting at least one of the word lines and at least one of the bit lines; a write circuit that rewrites the resistance value of the variable resistance element of the selected memory cell by applying a voltage pulse to the selected memory cell; and a read circuit that reads a state of the selected memory cell by performing voltage application on the selected memory cell so that one of a first voltage higher than the threshold voltage and a second voltage lower than or equal to the threshold voltage is applied to the current steering element of the selected memory cell, wherein the write circuit sets the variable resistance element of the memory cell selected from among the plurality of memory cells to one of a first low resistance state and a first high resistance state by applying, as the voltage pulse, a corresponding one of a first low-resistance write pulse and a first high-resistance write pulse to the selected memory cell, the read circuit (i) reads a resistance state of the variable resistance element of the selected memory cell by applying the first voltage to the selected memory cell, and (ii) determines that the selected memory cell is a faulty memory cell having a short-circuit fault in the case where a value of a current passing through the selected memory cell is higher than or equal to a predetermined value when the resistance state of the variable resistance element of the selected memory cell is read, and the write circuit sets a variable resistance element of an other memory cell different from the faulty memory cell and located on at least one of the bit line and the word line that includes the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.