Patent ID: 7713832

Claim:
A method of fabricating a semiconductor device, the method comprising: forming an interlayer insulating pattern over a semiconductor substrate, the interlayer insulating pattern defining a plurality of storage node regions; forming a lining conductive film over the interlayer insulating pattern including the storage node region; forming a capping insulating film over the lining conductive film; etching the interlayer insulating pattern, the lining conductive film and the capping insulating film between the storage node regions to form a recess exposing the interlayer insulating pattern on the bottom of the recess and the lining conductive film on sidewalls of the recess; shaping the capping insulating film and the lining conductive film to be planar so that the lining conductive layer is electrically separated from each other to form a respective lower storage electrode; forming a supporting pattern filling the recess; and removing the capping insulating film and the interlayer insulating pattern to expose the lower storage node.