Patent ID: 7020228

Claim:
A DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal, said DLL circuit comprising: a functional block having a constant current source; and a bias generation means for generating a constant current source bias signal for controlling the constant current source of the functional block, said bias generation means comprising bias control means which changes the bias signal according to the frequency of the input signal, wherein the bias control means comprises: a control circuit for outputting a first counting control signal which controls the start of counting of the input signal based on a predetermined external signal; a counting control means for outputting a second counting control signal after the elapse of a predetermined time from the input of the first counting control signal; counting means for controlling the start and end of counting of the input signal respectively according to the first counting control signal and the second counting control signal; and correction signal generation means for outputting a bias correction signal based on the results of counting by the counting means.