Patent ID: 8729933

Claim:
A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal, comprising: an input terminal, a frequency multiplier control unit connected to said input terminal, an output terminal connected to said frequency multiplier control unit, a first detecting unit connected to said frequency multiplier control unit and said output terminal, a second detection unit connected to said frequency multiplier control unit and said output terminal, a duty cycle adjusting unit connected to said first detecting unit, said second detecting unit and said frequency multiplier control unit, and a ground terminal connected to said first detecting unit and said second detecting unit; wherein said frequency multiplier control unit comprises: a first buffer connected to said input terminal, an AND gate connected to said input terminal and said first buffer, a first NOR gate connected to said input terminal and said first buffer, and a second NOR gate connected to said AND gate and said first NOR gate; wherein said first detecting unit comprises: an inverter connected to said second NOR gate and said output terminal, a first resistance connected to said inverter, and a first capacitance connected to said first resistance; wherein said second detecting unit comprises a second buffer connected to said second NOR gate and said output terminal, a second resistance connected to said second buffer, and a second capacitance connected to said second resistance; wherein said duty cycle adjusting unit comprises a comparator connected to said first resistance, said first capacitance, said second resistance, said second capacitance and said first buffer.