Patent ID: 8294197

Claim:
A semiconductor device comprising: a substrate having a planar top surface; a blocking layer comprising a dielectric with a k value of >8 disposed on and co-planar with the planar top surface of the substrate and having a top surface, the blocking layer and the substrate each having a conduction band such that the barrier height between the conduction band of the blocking layer and the conduction band of the substrate is greater than about 3.1 eV; a floating gate having a bottom surface disposed on the top surface of the blocking layer and over the planar top surface of the substrate; a retention layer over the floating gate; a control gate over the retention layer; a tunneling layer over the control gate; a top gate over the tunneling layer; and a voltage source electrically coupled between the top gate and the control gate, wherein electrons generated by the voltage source have an energy level of lower than a conduction band of the retention layer.