Patent ID: 8860137

Claim:
A method of fabricating a field-effect transistor, the method comprising: forming a source electrode probing pad and a drain electrode probing pad on a substrate, wherein the substrate comprises a silicon dioxide layer disposed over a silicon wafer, and the probing pads comprise titanium and are patterned on a surface of the silicon dioxide layer; forming aluminum back gates on the surface of the silicon dioxide layer, each aluminum back gate positioned between a portion of the source electrode probing pad and the drain electrode probing pad; heating the substrate in oxygen to oxidize a surface of the aluminum, thereby forming a layer of aluminum oxide on the aluminum back gate; contacting the substrate with a solution comprising aminopropyltriethoxysilane to couple the aminopropyltriethoxysilane to the aluminum oxide and the silicon dioxide; contacting the substrate with a solution comprising semiconducting carbon nanotubes to form a semiconducting nanotube thin film over the aluminum oxide and at least a portion of the silicon dioxide to which the aminopropyltriethoxysilane is coupled, wherein the semiconducting nanotube thin film forms a conduction channel; forming source electrode and drain electrode extensions comprising palladium, the source electrode and drain electrode extensions coupled to the source electrode and drain electrode probing pads, respectively, to yield a conduction channel length of less than 1 μm; and removing carbon nanotubes outside the conduction channel, wherein at least 95% of the carbon nanotubes are semiconducting, and the transistor has an on/off ratio equivalent to or greater than 4.0, at a drain voltage of less than or equal to −1.0 V, and gate voltages of 2.0 V and −2.0 V, respectively.