Patent ID: 7183817

Claim:
A high speed output buffer, comprising: an input circuit having an input receiving a digital input signal and first and second outputs providing first and second signals collectively representing said input signal, said first and second signals each operating within a first voltage range having a first common mode voltage; an AC interface having first and second inputs receiving said first and second signals, respectively, and having corresponding first and second outputs providing corresponding first and second preliminary drive signals in which said first preliminary drive signal is AC coupled to said first signal; a DC detection and correction circuit that is operative to detect a state of said first signal and to correct a state of said first preliminary drive signal; first and second drive circuits having first and second inputs receiving said first and second preliminary drive signals, respectively, and having first and second outputs providing first and second drive signals, respectively; wherein said first drive circuit operates within a second voltage range having a second common mode voltage that is greater than said first common mode voltage and wherein said second drive circuit operates within a third voltage range; wherein said first, second and third voltage ranges are each within a maximum voltage range suitable for a single thin-gate device; and an output circuit having first and second inputs receiving said first and second drive signals, respectively, and having an output that switches an output node within a fourth voltage range that is greater than said maximum voltage range.