Patent ID: 7269529

Claim:
A data processing apparatus incorporating a processor and a tamper-resistant secured circuit, wherein: said processor outputs a test start instruction to said tamper-resistant secured circuit; said tamper-resistant secured circuit is provided with a test means for conducting a self-diagnostic test on the tamper-resistant secured circuit and, when said test start instruction is received from said processor, said test means conducts a self-diagnostic test of the tamper-resistant secured circuit and outputs a test result indicating whether the tamper-resistant secured circuit is normal or not to said processor; wherein when said tamper-resistant secured circuit performs a normal operation other than said self-diagnostic test, on condition that data input to said tamper-resistant secured circuit matches with any one of a predetermined plurality of formats regulated in advance, said test means brings said secured circuit to perform processing using the input data; while when performing said self-diagnostic test, on condition that the data input to said tamper-resistant secured circuit matches with a predetermined part of formats among said predetermined plurality of formats, said test means performs said self-diagnostic test by using the input data.