Patent ID: 7142669

Claim:
An apparatus for selectively processing first and second cryptographic hash algorithms, comprising: a register file ( 12 ) having at least five registers for storing chaining variables; a function circuit ( 22 ) receiving first (B), second (C) and third (D) chaining variables and an output that provides a logical data value; a first multiplexer ( 24 ) having an input coupled to the register file for receiving a fourth (E) chaining variable and an output that provides the fourth chaining variable when the first cryptographic hash algorithm is being processed by the apparatus and a zero value when the second cryptographic hash algorithm is being processed by the apparatus; and a summing circuit ( 30 ) having a first input coupled to the output of the function circuit for receiving the logical data value, a second input coupled to the output of the first multiplexer, and an output coupled to the register file.