Patent ID: 7089439

Claim:
A memory device in which output data is supplied on an output in an output clock cycle within a read latency of more than one output clock cycle, comprising: a memory including memory cells, and having address/data paths and timing paths which emulate the address/data paths, the address/data paths outputting data in response to addresses and the timing paths outputting dummy data in response to an address emulation signal; a clock channel having inputs and outputs; a clock generator, responsive to an input clock, producing an output clock signal having said output clock cycles with an adjustable phase and a dummy data reference clock signal on the input of the clock channel, and producing an address emulation signal on the timing path in the memory, the address emulation signal and the dummy data reference clock signal having substantially equal periods that are a multiple of the output clock cycle long; an output clock phase detector coupled to the output of the clock channel and to timing path of the memory, which generates signals indicating a phase relationship between transitions of the dummy data and the output clock signal from the output of the clock channel; and clock control logic coupled to the clock generator and to the output clock phase detector, for adjusting the adjustable phase of the output clock signal on the input of the clock channel.