Patent ID: 7475187

Claim:
An interface circuit implemented in a semiconductor memory chip having a memory core, the interface circuit being connectable to a shared read and write data/command-and-address bus and comprising: a serial output terminal connectable to a serial input terminal of an interface circuit of another memory chip or to a serial input terminal of a memory controller; a serial input terminal for receiving a serial stream of data/command-and-address signals from a serial output terminal of an interface circuit of another memory chip or from a serial output terminal of a memory controller; a reference clock receiving terminal for receiving a reference clock signal; a read and write data/command-and-address signal re-driver/transmitter path for re-driving read data signals and write data/command-and-address signals not destined for the semiconductor memory chip and received at the serial input terminal; and a main signal path leading from a parallel read data input terminal to the serial output terminal for transmitting read data from the memory core and from the serial input terminal to a parallel write data/command-and-address signal output terminal to transfer parallel write data/command-and-address signals to the memory core and including: a synchronization unit for synchronizing data/command-and-address signals received at the serial input terminal with the reference clock signal; a serial-to-parallel converter for serial-to-parallel converting write data/command-and-address signals destined for said semiconductor memory chip; a first-in-first-out write data buffer register configured to buffer the synchronized and serial-to-parallel convened write data/command-and-address signals destined for the semiconductor memory chip and convert a clock domain of the write data/command-and-address signals to a clock domain of the memory core; a first-in-first-out read data buffer register configured to buffer the parallel read data signals received from the memory core and convert a clock domain of the parallel read data signals from the clock domain of the memory core to the clock domain of the reference clock signal; a parallel-to-serial converter for parallel-to-serial converting the buffered and clock domain converted parallel read data signals into a serial read data signal stream; and a first switching device configured to insert the parallel-to-serial converted read data signal stream into the serial data stream of the read and write data/command-and-address signal re-driver/transmitter path.