Patent ID: 7392366

Claim:
A multithreaded processor comprising: an instruction cache with a plurality of cache locations; a thread selection and priority circuit configured to monitor processor flags and selectively retrieve contents of each of said plurality of cache locations, said instruction thread selection and priority circuit comprising: means for generating a fetch gate signal from thread monitor and control flags, means for combining said fetch gate with a dispatch stall signal and providing a flow rate indicator responsive to said combination, said flow rate indicator indicating flow rate mismatch in said pipeline, means for determining Data/Instruction (D/I) cache misses, responsive to said flow rate mismatch, means for determining a branch mis-prediction responsive to said processor flags, means for determining a next thread responsive to said means for flow rate mismatch determination and said means for D/I cache miss determination, and means for indicating a next thread; an instruction fetch unit pipeline configured to receive the selectively retrieved contents from said thread selection and priority circuit; and a plurality of instruction buffer threads, wherein each of the selectively retrieved contents are passed to one of the instruction buffer threads through said instruction fetch unit pipeline, the thread selection and priority circuit being further configured to retrieve contents only for threads indicated by the processor flags as being capable of receiving the selectively retrieved contents.