Patent ID: 7635985

Claim:
A method of analyzing a delay characteristic of an interconnection line in a semiconductor device using a test pattern fabricated in the semiconductor device having a first metal line shape similar to that of the interconnection line, wherein the test pattern includes the first metal line formed as a snake shaped structure having a plurality of concave-convex sections each having the same width; a second metal line formed in a comb shape on the same layer as the first metal line such that a plurality of teeth portions of the second metal line are respectively formed between the concave-convex sections at one side of the first metal line; a third metal line formed in a comb shape on the same layer as the first metal line such that a plurality of teeth portions of the third metal line are respectively formed between the concave-convex sections at the other side of the first metal line; a plurality of probe pads connected at both ends of the first metal line; and ground plates respectively formed on upper and lower layers above and below the layer having the first, second and third metal lines, the method comprising the steps of: measuring the capacitance and resistance of the first metal line over a range of widths for the first metal line; calculating the capacitance and resistance per unit length of the first metal line using the measured capacitance and resistance of the first metal line; calculating the thickness of an insulating layer from the capacitance per unit length of the first metal line; calculating sheet resistance and width reduction from the resistance per unit length of the first metal line; and analyzing a delay characteristic of an interconnection line using the calculated capacitance, calculated sheet resistance, calculated thickness of the insulating layer and calculated width reduction.