Patent ID: 7550822

Claim:
A dual-damascene wiring pattern of an integrated circuit, comprising: a first metal wiring pattern on an integrated circuit substrate; an inter-metal dielectric layer extending on the integrated circuit substrate, said inter-metal dielectric layer having a via hole therein that extends opposite an upper surface of said first metal wiring pattern; a first barrier metal layer lining a sidewall of the via hole; an etch-stop layer extending between the upper surface of said first metal wiring pattern and said inter-metal dielectric layer, said etch-stop layer having an opening therein that is self-aligned to said first barrier metal layer so that an inner sidewall of the opening in the etch-stop layer is vertically aligned with an inner sidewall of said first barrier metal layer; and a second metal wiring pattern that extends into the via hole and opening, and is electrically connected to said first metal wiring pattern.