Patent ID: 6850100

Claim:
A output buffer circuit comprising: a power supply potential node to which a power supply potential is supplied; a ground potential node to which a ground potential is supplied; an output node for outputting data; a first output transistor provided with a control electrode and connected between the power supply potential node and the output node; a second output transistor provided with a control electrode and connected between the ground potential node and the output node; a first node; a first current source connected between the first node and the ground potential node; a first capacitor element connected between the first node and the output node; a first control circuit connected between the first node and the control electrode of the first output transistor for controlling a conductive state of the first output transistor in response to a potential of the first node; a first clamp circuit for supplying a given potential to the first node when the first control circuit is inactivated and stopping the supply of the given potential when the first control circuit is activated; a second node; a second current source connected between the second node and the power supply potential node; a second capacitor element connected between the second node and the output node; a second control circuit connected between the second node and the control electrode of the second output transistor for controlling a conductive state of the second output transistor in response to a potential of the second node; and a second clamp circuit for supplying a given potential to the second node when the second control circuit is inactivated and stopping the supply of the given potential when the second control circuit is activated.