Patent ID: 8630135

Claim:
A semiconductor memory device comprising: a memory cell array having memory cells arranged therein at intersections of word lines and bit lines, the word lines extending in a column direction and the bit lines extending in a row direction, the row direction being a direction perpendicular to the column direction; a row decoder disposed on a side of the memory cell array in the column direction and configured to supply one of the word lines with a first drive signal for selecting one of the memory cells; a sense amplifier circuit disposed on a side of the memory cell array in the row direction and configured to detect a change in potential of one of the bit lines and thereby determine data stored in one of the memory cells; a dummy word line formed extending in the column direction; a dummy bit line formed extending in the row direction; and a buffer circuit connected directly to the dummy word line, at least one of the dummy word line and the dummy bit line being disposed outside of the memory cell array, a signal being outputted toward the sense amplifier circuit via the dummy bit line and the dummy word line as a second drive signal, the sense amplifier circuit being configured to be activated based on the second drive signal, and the buffer circuit being configured by a logic gate circuit including two NMOS transistors connected in series, one of the two NMOS transistors having a source connected to a drain of the other one of the two NMOS transistors.