Patent ID: 6956770

Claim:
In a non-volatile memory having an array of memory storage units, each unit having a charge storage unit between a control gate and a channel region defined by a source and a drain, and a bit line switchably coupled to the drain, a method of programming in parallel a page of memory storage units having a common word line interconnecting their control gates, comprising: (a) providing a bit line for each memory storage unit of the page, switchably coupled to the drain thereof; (b) determining for each of those memory storage units of the page slated to be programmed whether or not its neighboring memory storage units are in a program inhibit mode; (c) for those memory storage units of the page slated to be program inhibited, applying a first predetermined voltage to each of the bit lines thereof to inhibit programming; (d) applying a second predetermined voltage to each bit line of those memory storage unit of the page slated to be programmed to enable programming, said second predetermined voltage for said each bit line being a function of the operation mode of its neighboring memory storage units so as to offset any perturbation therefrom; and (e) applying a programming voltage pulse to said word line in order to program in parallel the memory storage units of the page, wherein those memory storage units having a bit line with said first predetermined voltage are program-inhibited by virtue of their floated channel boosted to a program inhibited voltage condition, and a perturbation resulted from the boosting on any neighboring programming memory storage unit is compensated by said offsetting from said second predetermined voltage.