Patent ID: 8279689

Claim:
An apparatus comprising: a memory controller having circuitry to access a first memory interface coupled to a memory channel and to access a second memory interface coupled to the memory channel, the memory controller having circuitry to access a third memory interface coupled to the memory channel, the memory controller having circuitry to provide, when a READ operation or a WRITE operation is to be performed to a memory, a first on-die termination (ODT) signal to disable a first ODT circuit to be coupled to the first memory interface, the circuitry to provide, when the READ operation or the WRITE operation is to be performed to the memory, a second ODT signal to enable a second ODT circuit to be coupled to the second memory interface, and the circuitry to provide, when the READ operation or the WRITE operation is to be performed to the memory, a third ODT signal to enable a third ODT circuit to be coupled to the third memory interface.