Patent ID: 8095761

Claim:
A method for switching synchronous data transaction speeds across a memory interface between a processing device and a synchronous memory, comprising: locking a clock unit within the synchronous memory to an input clock at a first speed; performing synchronous data transactions across the memory interface at the first speed, wherein the input clock remains at the first speed while synchronous data transactions are performed across the memory interface at the first speed; receiving a speed change command that specifies a second speed for synchronous data transactions across the memory interface, wherein the second speed is related to the first speed by a divide ratio specified by the speed change command; configuring the synchronous memory to perform the synchronous data transactions across the memory interface at the second speed; performing the synchronous data transactions across the memory interface at the second speed, wherein the data transactions are synchronized based on an internal clock generated by multiplying the input clock by the divide ratio, and the input clock remains at the first speed while synchronous data transactions are performed across the memory interface at the second speed; and sampling data received from the processing device at the second speed for output to the synchronous memory at the second speed.