Patent ID: 8363456

Claim:
A semiconductor device having a plurality of memory cells arranged in a row direction and a column direction of a semiconductor substrate, wherein for the semiconductor substrate, a first n well and a second n well of n-conductive type extending in the column direction, and a first p well, a second p well and a third p well of p-conductive type extending in the column direction, respectively, are formed, and the first p well, the first n well, the second p well, the second n well and the third p well are arranged in this order when viewed in the row direction; wherein the memory cell has a first inverter including a first driver transistor of n-channel type and a first load transistor of p-channel type, a second inverter including a second driver transistor of n-channel type and a second load transistor of p-channel type, and a positive-phase access transistor and a negative-phase access transistor of n-channel type; wherein cells of the memory cells, which are arranged side by side in the row direction, are connected by a word line extending along the row direction and cells of the memory cells, which are arranged side by side in the column direction, are connected by a positive-phase bit line and a negative-phase bit line extending along the column direction; wherein an output terminal of the first inverter is coupled to an input terminal of the second inverter as a first storage node and an input terminal of the first inverter is coupled to an output terminal of the second inverter as a second storage node; wherein in the positive-phase access transistor, a gate and the word line, a drain and the positive-phase bit line, and a source and the first storage node are coupled, respectively; wherein in the negative-phase access transistor, a gate and the word line, a drain and the negative-phase bit line, and a source and the second storage node are coupled, respectively; wherein the positive-phase access transistor is disposed in the first p well, the first load transistor is disposed in the first n well, the first driver transistor and the second driver transistor are disposed in the second p well, the second load transistor is disposed in the second n well, and the negative-phase access transistor is disposed in the third p well; and wherein cells of the memory cells, which neighbor each other when viewed in the row direction, share the first p well and the third p well, respectively.