Patent ID: 8468307

Claim:
An information processing apparatus comprising: shared memory including a plurality of banks; a plurality of processors; and a network that connects the plurality of processors and the shared memory, wherein each processor includes a cache that stores a copy of a part of data stored in the shared memory, and a Fence control unit that transmits an identifier to each bank through the network at timing when guarantee of completion of consistency processing of data stored in the shared memory and the cache is requested, and confirms that the identifier is returned from each bank, and each bank includes a memory main body, a directory unit that stores area information of the memory main body for data stored in the cache and issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and a queuing unit that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing, the plurality of processors include a first processor and a second processor, and when the first processor requests the second processor to guarantee the completion of consistency processing of data, the Fence control unit of the second processor transmits the identifier to each bank, and the queuing unit of each bank queues the identifier at a position subsequent to the queued invalidation request and transmits the identifier after transmission of the invalidation request queued before queuing of the identifier.