Patent ID: 8745335

Claim:
A memory controller comprising: a plurality of ports in communication with an electronic memory; a memory arbiter in communication with the electronic memory and operative to determine priorities among a plurality of access requests from the plurality of ports; a plurality of latency determiners in communication with the plurality of ports, a latency determiner of the plurality of latency determiners in communication with a port of the plurality of ports and operative to determine a latency value indicative of a time difference between origination of an access request from the port and a response from the electronic memory, the latency value corresponding to the access request; a plurality of target registers associated with the plurality of ports, a target register of the plurality of target registers associated with the port to store a target value for the port, the target value indicative of a desired average latency for the plurality of access requests from the port; and a plurality of accounting units associated with the plurality of ports, an accounting unit of the plurality of accounting units associated with the port that maintains a running sum of differences between a plurality of latency values of the access requests and the target latency value for one or more of the plurality of access requests from the port to provide the memory arbiter a delta of a priority value.