Patent ID: 8829960

Claim:
A delay locked loop comprising: a coarse delay line configured to have a plurality of unit delays and delay an reference clock to output a delayed clock; a phase mixing unit configured to delay the delayed clock to output a delayed output clock; a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock; a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate a first phase detection signal based on a result of the comparison, compare the phase of the reference clock with a phase of the feedback clock delayed by a unit delay amount of each unit delay of the coarse delay line to generate a second phase detection signal based on a result of the comparison, and compare the phase of the reference clock with a phase of the feedback clock advanced by the unit delay amount to generate a third phase detection signal based on a result of the comparison; a locking detection unit configured to output a locking signal by selecting a first locking detection signal generated by comparing a previous state and a current state of the second phase detection signal with each other or a second locking detection signal generated in response to logic levels of the first to third phase detection signals at the same timing; and a control unit configured to control the coarse delay line and the phase mixing unit in response to the locking signal and the first phase detection signal.