Patent ID: 7116746

Claim:
A synchronous clock phase control circuit comprising: a phase clock generation unit which generates “n” clock signals delayed by T/n×0, T/n×1, . . . and T/n×(n−1), where n>1, n is an integer and T is a cycle, from a reference clock signal and thereby having different phase delays, respectively, using an input clock signal having a cycle T input from externally as the reference clock signal; a phase selection unit which selects “m” clock signals having different phases from the “n” clock signals having the different phases and generated by the phase clock generation unit, based on “m” control signals input from externally, respectively, where m>1 and m is an integer; “m” clock selection units each of which selects one of the externally input clock signal and the clock signal selected by the corresponding phase selection unit, based on a corresponding detection signal; “m” synchronous clock generation units which synchronize the clock signals selected by the clock selection units with a trigger signal asynchronous with the externally input clock signal, and output the synchronous clock signals, respectively; and “m” synchronous detection units which detect synchronization of the clock signals output from the synchronous clock generation units with the trigger signal, and output the corresponding detection signal to the “m” clock selection units when synchronization is detected.