Patent ID: 8561006

Claim:
A CAD device that implements a method for designing a semiconductor circuit device, the CAD device comprising: a first determining unit determining signal transmission time necessary for each signal transmission circuit in an LSI circuit to transmit a signal; a second determining unit determining a frequency distribution of the signal transmission time; a detecting unit detecting the longest signal transmission time on the basis of the signal transmission time; a third determining unit determining an output inversion rate at which the logic of an output signal from each flip-flop circuit is inverted on the basis of the amount of charge held in a critical node in each flip-flop circuit and a logic of input signal in each flip-flop; a calculating unit calculating a soft error rate of the LSI circuit on the basis of the frequency distribution of the signal transmission time, an operating clock period, and the output inversion rate of each flip-flop circuit; and a modifying unit, when a predetermined soft error rate is less than the soft error rate of the LSI circuit as a result of comparison, modifying the LSI circuit to the extent possible without changing the longest signal transmission time by changing the frequency distribution of the signal transmission time.