Patent ID: 6996644

Claim:
An electronic device, comprising: a controller programmed to produce first address data on an output thereof; a plurality of integrated circuits (ICs) addressable by the controller; and a shared bus, said shared bus joining the controller and the plurality of ICs such that the controller is able to send data to the plurality of ICs over the shared bus; wherein each IC of the plurality of ICs comprises: an input for receiving address data, said address data representing an address of the IC on the shared bus; an address register for storing the received address data as the address of the IC on the shared bus; output generator logic for modifying the received address data to produce modified address data that is different from the received address data, said modified address data representing an address of another IC on the shared bus; and an output for providing the modified address data; wherein the input of a first IC of the plurality of ICs communicates with the output of the controller, and the inputs of succeeding ICs communicate with the outputs of preceding ICs in a daisy chain configuration; wherein the first address data produced on the output of the controller represents an address of the first IC on the shared bus; and wherein the modified address data provided on the output of each IC of the plurality of ICs represents an address of a corresponding succeeding IC in the daisy chain configuration on the shared bus.