Patent ID: 8067801

Claim:
A semiconductor device, comprising a first transistor and a second transistor formed in a semiconductor layer, said first transistor including: a first gate electrode formed on said semiconductor layer via a first insulator; a first source region formed in said semiconductor layer in relation to said first gate electrode; and a first drain region formed in said semiconductor layer to sandwich the first gate electrode with said first source region, said second transistor including: a second gate electrode formed on said semiconductor layer via a second insulator; a second source region formed in said semiconductor layer in relation to said second gate electrode; an LDD region formed in said semiconductor layer and adjacent to said second source region; a drift region formed in said semiconductor layer to sandwich said second gate electrode with said LDD region, the drift region having a lower impurity concentration than that of the LDD region; and a second drain region formed in said semiconductor layer and adjacent to said drift region to sandwich the second gate electrode with said second source region, wherein said first gate electrode has a first sidewall formed on sides thereof and said second gate electrode has a second sidewall formed on sides thereof, wherein the width of said first sidewall along said first insulator differs from the width of said second sidewall along said second insulator, and most part of said drift region is formed in a region under said second sidewall.