Patent ID: 7417480

Claim:
A method of providing a duty cycle correction apparatus, comprising: providing a first pair of field effect transistors (FETs) having a first P-type FET and a first N-type FET; providing at least two linear resistors coupled to the first pair of FETs, wherein a first linear resistor is coupled to the first P-type FET and a second linear resistor is coupled to the first N-type FET; providing a first switch coupled to the first linear resistor; and providing a second switch coupled to the second linear resistor, wherein an input signal is provided to the first pair of FETs and a corrected input signal is output by the at least two linear resistors, and wherein the first and second switches are selectively controlled so as to cause at least one of the first or second linear resistors to increase or decrease a duty cycle of the input signal, wherein a resistance value associated with the first linear resistor is less than approximately ten percent of a resistance value associated with the first P-type FET, and wherein a resistance value associated with the second linear resistor is less than approximately ten percent of a resistance value associated with the first N-type FET.