Patent ID: 6962863

Claim:
A method for fabricating a semiconductor device comprising the steps of: forming above a substrate an interconnection layer having an upper surface covered by a cap insulation film; forming a first insulation film on the substrate with the cap insulation film and the interconnection layer formed on; forming a second insulation film whose etching rate is higher than that of the first insulation film on the first insulation film; anisotropically etching the second insulation film and the first insulation film to leave the first insulation film selectively on side walls of the interconnection layer and the cap insulation film and leave the second insulation film selectively on a lower region of a side wall of the first insulation film; forming a third insulation film on an upper region of the side wall of the first insulation film and a side wall of the second insulation film; forming a fourth insulation film on the substrate with the interconnection layer and the first, second and third sidewall insulation films, the fourth insulation film contacting to the third sidewall insulation film; and anisotropically etching the fourth insulation film and the third insulation film with the cap insulation film and the first to the third insulation films as a stopper to form a contact hole down to the substrate in the fourth insulation film and the third insulation film.