Patent ID: 7827430

Claim:
A circuit comprises: a clock circuit coupled to produce a digital clock signal; a processing module coupled to: determine whether a harmonic component of the digital clock signal having a nominal digital clock rate interferes with operation of at least a portion of the circuit; when the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit, provide an indication to the clock circuit to adjust rate of the digital clock signal from the nominal digital clock rate to an adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate do not interfere with the operation of the at least a portion of the circuit; and processing circuitry coupled to: receive data at the nominal digital clock rate; process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate; and interpolate, at an interpolation rate corresponding to the adjusted digital clock rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.