Patent ID: 7364966

Claim:
A method for use during fabrication of a semiconductor device, comprising: providing a semiconductor wafer substrate assembly comprising a first region having a contact location and a second region free from the contact location; forming a first dielectric layer comprising a first material over the first region and over the second region; forming a second dielectric layer comprising a second material different from the first material over the first dielectric layer and over the first and second regions; performing a first etch of the second dielectric layer and the first dielectric layer to form a first opening in the first and second dielectric layers and to expose the second region; etching the second dielectric layer selective to the first dielectric layer to expose a surface of the second dielectric layer and to form a lip from the first dielectric layer; forming a first conductive layer within the opening in the first and second dielectric layers in contact with the second region and the lip formed from the first dielectric layer; performing a second etch of the second and the first dielectric layers to form a second opening in the first dielectric layer and to expose the contact location in the first region using the first conductive layer which contacts the lip as an etch mask for the first dielectric layer; forming a second conductive layer in the second opening in the first dielectric layer in contact with the contact location of the first region; and etching the first conductive layer to recess the first conductive layer within the first opening in the first dielectric layer and to remove the first conductive layer from contact with the lip of the first dielectric layer.