Patent ID: 8310098

Claim:
A circuit for compensating for power interruptions, the circuit comprising: a first array of capacitors, the capacitors being arranged in parallel within the array; a second array of capacitors, the capacitors being arranged in parallel within the array; a first switching element configured to selectively couple the first array of capacitors to a power rail disposed between a power source and a load; a second switching element configured to selectively couple the second array of capacitors to the power rail; a monitor configured to receive a measurement of a first parameter from the first array of capacitors, a second parameter from the second array of capacitors, and a third parameter from the power rail in real time; and a controller operatively coupled to the first and second switching element, the controller configured to receive the first, second, and third parameters from the monitor and to switch at least one of the first and second switching elements in real time based on the received parameters.