Patent ID: 7146469

Claim:
An apparatus comprising: a high speed memory unit to store data received from an external memory device, the high speed memory unit having faster memory access speed compared to the external memory device; a memory controller coupled to the high speed memory unit to control access to the high speed memory unit; and an external bus interface (EBIF) unit coupled to the memory controller and adapted to receive data from the external memory device and to transfer the data received from the external memory device to the high speed memory unit, the EBIF unit, based on a memory request issued by a host device to read a block of data from the external memory device, (i) initiates a burst or page mode read cycle even when memory requests by the host device immediately subsequent to the memory request are not directed to the external memory device, (ii) stores at least a portion of the block of data read in the high speed memory unit in response to the burst or page mode read cycle, and (iii) retrieves requested data from the high speed memory unit in response to subsequent memory requests issued by the host device for data already stored within die high speed memory unit.