Patent ID: 8901572

Claim:
A semiconductor device comprising: an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate opposite the first surface, wherein a first p type pillar region of the plurality of p type pillar regions is disposed within the n− type epitaxial layer, and the n type pillar regions and the p type pillar regions are spaced apart from the trench, and are not disposed in an area corresponding to the bottom of the trench.