Patent ID: 7375372

Claim:
A thin film transistor (TFT), comprising: a substrate; a gate, disposed over the substrate; an inter-gate dielectric layer, disposed over the substrate covering the gate; a channel layer, disposed over a portion of the inter-gate dielectric layer, at least over the gate, wherein the channel layer comprises a lightly doped amorphous silicon layer, and the lightly doped amorphous silicon layer comprises: a first lightly doped sub-amorphous silicon layer, disposed over a portion of the inter-gate dielectric layer; and a second lightly doped sub-amorphous silicon layer, disposed over the first lightly doped sub-amorphous silicon layer, wherein the effective content ratio of the dopants in the first lightly doped sub-amorphous silicon layer and the effective content ratio of the dopants in the second lightly doped sub-amorphous silicon layer are substantially different; and source/drain regions, disposed over the channel layer, wherein the source/drain regions are separated by a distance.