Patent ID: 8638615

Claim:
A semiconductor storage device comprising: a memory cell array comprising a plurality of memory cells capable of holding data; and a data latch group capable of holding a first address of the memory cell serving as a read target or a second address of the memory cell serving as a write target, and the data held by the memory cells, wherein the data latch group comprises a plurality of data latch units including at least a first data latch unit and a second data latch unit, the first data latch unit holds first write data to be written to any of the memory cells and a first write address corresponding to the first write data, or first read data read from the memory cell array and a first read address corresponding to the first read data, while the second data latch unit holds second write data to be written to any of the memory cells and a second write address corresponding to the second write data, or second read data read from the memory cell array and a second read address corresponding to the second read data.