Patent ID: 7408389

Claim:
An output circuit, comprising: a first current mirror circuit having first and second current paths each connected to a potential point at high potential side; a first PMOS transistor having a drain, a gate, a source and a back gate, said source being connected to said potential point at high potential side through said second current path of said first current mirror circuit, and said back gate being connected to said potential point at high potential side; a first gate resistor connected to said gate of said first PMOS transistor; and an output resistor connected between said drain of said first PMOS transistor and a potential point at low potential side, wherein current flows through said first current path of said first current mirror circuit corresponding to the current flowing through said first gate resistor, and an output voltage is determined based on a voltage drop at said output resistor, the output circuit further comprising a first NMOS transistor having a source, a drain and a gate, wherein said source is connected to a middle potential point for supplying a potential between said potential point at high potential side and said potential point at low potential side, said drain is connected to said gate of said first PMOS transistor through said first gate resistor, and an input signal is supplied to said gate, the output circuit further comprising: a second gate resistor; and a second NMOS transistor having a source, a drain and a gate, wherein said source is connected to said middle potential point, said drain is connected to said gate of said first PMOS transistor through said second gate resistor, and another input signal is supplied to said gate.