Patent ID: 7777529

Claim:
A dynamic flip-flop comprising: a data input for receiving a data signal; a clock input for receiving a clock signal; a first circuit node adapted to store a voltage representing a state of the dynamic flip-flop; a pull-up circuit connected with the first circuit node and adapted to change the voltage of the first circuit node to a high logic level voltage in response to the data signal having a first value during a state transition period specified by the clock signal; a pull-down circuit connected with the first circuit node and adapted to change the voltage of the first circuit node to a low logic level voltage in response to the data signal having a second value during the state transition period specified by the clock signal, said pull-down circuit comprising first and second transistors; and a leakage compensation circuit comprising a third transistor connected with a second circuit node and adapted to draw a current from the first circuit node, wherein the current compensates for a leakage current supplied by the pull-up circuit to the first circuit node, and wherein the third transistor is weaker than the first and second transistors.