Patent ID: 7920405

Claim:
A non-volatile memory device comprising: a memory cell array comprising a plurality of word lines, a plurality of bit lines, and a plurality of non-volatile memory cells, a respective non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line, the variable resistive material having a resistance level that varies according to data to be stored; a selection circuit configured to select at least one non-volatile memory cell of the plurality of non-volatile memory cells in which data will be written; a sensing circuit configured to obtain feedback on the resistance level of the selected non-volatile memory cell while supplying the write bias to the selected non-volatile memory cell, and further configured to compare the resistance level of the selected non-volatile memory cell and a reference resistance level, and to output a result of the comparison; and an adaptive write circuit configured to supply a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data on the selected non-volatile memory cell and further configured to gradually increase the write bias during writing until the resistance level of the selected non-volatile memory cell varies below or above a predetermined resistance level, wherein the sensing circuit is operative to feedback the resistance level to the adaptive write circuit seamlessly during writing, and wherein the adaptive write circuit modifies the write bias according to the feedback resistance level during writing.