Patent ID: 7234120

Claim:
A method for identifying a faulty net in a design implemented on a programmable logic device (PLD), comprising: generating configuration data that implements a duplicate circuit of a failing sub-circuit in the design; configuring the PLD with the configuration data that implements the failing sub-circuit and the duplicate circuit; applying at least one set of input signals to the sub-circuit and the duplicate circuit; comparing a signal from each net in the sub-circuit to a corresponding net in the duplicate circuit; identifying a net in the sub-circuit as faulty in response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit; comparing a signal from each segment of a plurality of wire segments in the faulty net to a signal from a segment of wire in the corresponding net in the duplicate circuit; and identifying a wire segment of the plurality of wire segments in the faulty net as faulty in response to the signal from the wire segment in the faulty net being unequal to the signal from the segment of wire in the corresponding net of the duplicate circuit.