Patent ID: 7199613

Claim:
An output buffer generating an output signal having a swing equaling a first voltage level, said output buffer comprising: a first transistor and a second transistor together operating as a first inverter, each of said first transistor and said second transistor being of a voltage specification of a second voltage level, wherein said second voltage level is lower than said first voltage level; a third transistor ( 320 -A) and a fourth transistor protecting said first transistor and said second transistor from exposure to said first voltage level, wherein each of said first transistor, said second transistor, said third transistor, and said fourth transistor contains a source terminal, a drain terminal, and a gate terminal, the source terminal of said third transistor is coupled to the drain terminal of said first transistor at a fourth node, the gate terminal of said third transistor is coupled to a reference voltage at a first node, the drain terminal of said third transistor is coupled to the drain terminal of said fourth transistor, the source terminal of said fourth transistor is coupled to the drain terminal of said second transistor at a fifth node, the gate terminal of said fourth transistor is coupled to said reference voltage at a second node, the gate terminal of said first transistor is coupled to receive a first input swing signal, the gate terminal of said second transistor is coupled to receive a second input swing signal, each of said first input swing signal and said second input swing signal having a lower swing than said first voltage level, the source terminal of said second transistor is coupled to receive a ground voltage, the source terminal of said first transistor is coupled to receive a supply voltage of said first voltage level, a parasitic capacitance of said third transistor and said fourth transistor coupling said output signal to said first node and said second node respectively; and a second inverter, a first capacitor, and a second capacitor together countering the effect of coupling of said output signal to said first node and to said second node, said second inverter generating an inverted signal of said output signal at a sixth node, said first capacitor connecting said inverted signal to said first node, and said second capacitor connecting said inverted signal to said second node.