Patent ID: 8390605

Claim:
An interface circuit, comprising: a plurality of receivers each for receiving one of a plurality of sub-pixel values in one time period; a multiplexer for multiplexing the sub-pixel values received by the receivers; a plurality of shift registers corresponding to the receivers, each of the shift registers temporarily storing at least one of the multiplexed sub-pixel values; and a latch circuit receiving the sub-pixel values temporarily stored in the shift registers according to a shift register signal; wherein under a selection mode a number of the receivers are turned on to receive the sub-pixel values and the rest of the receivers are turned off, the receivers correspondingly receive a same number of the sub-pixel values as that of the turn-on receivers in a first time period and correspondingly receive another same number of the sub-pixel values as that of the turn-on receivers in a second time period next to the first time period, and the sub-pixel values received in the second time period are multiplexed and separately stored in the corresponding shift registers after the sub-pixel values received in the first time period are multiplexed and separately stored in the other corresponding shift registers.