Patent ID: 8310061

Claim:
A stacked integrated circuit, comprising: a first die with a first surface and a second die with a second surface facing the first surface; a plurality of microbumps coupling the first surface of the first die to the second surface of the second die, the microbumps fully structurally supporting the second die and electrically coupling the first die and the second die; and a capacitor formed to comprise a first conducting plate on a region of the first surface where no microbump is coupled to the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode, the dielectric contacting a portion of the first and second surfaces of the dies, the capacitor being disposed between a side wall of the first die or a sidewall of the second die at an outer edge of the stacked integrated circuit and a microbump of the plurality of microbumps to the outer edge of the stacked integrated circuit.