Patent ID: 6901492

Claim:
An electronic device comprising: a plurality of N source memories having respective source addresses for storing a plurality of N input data sets; a processor connected to said source memories and clocked by a clock signal and having a plurality of N outputs for producing, per cycle of the clock signal, a plurality of N output data sets each corresponding to a respective one of the N input data sets and having a respective source address and target address associated therewith; a plurality of N target memories each having a respective target address associated therewith; a plurality of N interleaving tables for storing a respective target address for each source address; and a plurality of N cells each being connected between the N outputs of said processor and also being connected to said N interleaving tables and a respective target memory; each cell for receiving the output data sets, and for selecting up to N of the received output data sets and causing the selected output data sets to be stored in said respective target memory based upon the target and source addresses thereof and said interleaving tables.