Patent ID: 7400185

Claim:
A circuit for applying current to an antifuse coupled between a first node and a second node with a potential V PP , the circuit disposed on an integrated circuit and comprising: a first n-channel MOS transistor having a source coupled to a third node switchably coupleable between a potential of about V PP /2 and ground potential, a drain, and a gate, the first n-channel MOS transistor having a BVDss rating of less than V PP ; a second n-channel MOS transistor having a source coupled to the drain of said first n-channel MOS transistor, a drain coupled to the second node, and a gate, the second n-channel MOS transistor having a BVDss rating of less than V PP ; a bootstrap circuit formed form a third n-channel MOS transistor having a source coupled to the first node, a drain coupled to a node selectively carrying the potential V PP or the potential V PP /2, and a gate, and a fourth n-channel MOS transistor having a source coupled to the gate of the third n-channel MOS transistor, a drain coupled to a precharge select node, and a gate coupled to a programming control node; and circuitry coupled to the gate of said first n-channel MOS transistor and the gate of the second n-channel MOS transistor and configured to, in a current-applying mode, apply a potential of either zero volts or about V PP /2 to the gate of the first n-channel MOS transistor and to apply a potential of about V PP /2 to the gate of the second n-channel MOS transistor.