Patent ID: 7844922

Claim:
A semiconductor integrated circuit device, comprising: a two-dimensional array of dynamic type logic circuit cells in which transistors constituting a logic section are in an unconnected condition; and wiring for distributing a respective clock signal to each respective row of these dynamic type logic circuit cells, wherein each of the dynamic type logic circuit cells has a precharge section, a clock gating section and a driving section in addition to the logic section and also transistors constituting respectively the precharge section, the clock gating section and the driving section are in an unconnected condition, wherein the transistors constituting respectively the precharge section, the clock gating section and the driving section are brought into a connected condition in accordance with rule restrictions of a circuit, and wherein the transistors constituting the driving section of a first dynamic logic circuit cell are connected based on a wiring length between the first dynamic logic circuit cell and a second dynamic logic circuit cell.