Patent ID: 7348250

Claim:
A method of forming an integrated circuit containing selected bipolar transistors from a first set of bipolar transistors and a second set of bipolar transistors formed in a SiGe layer comprising the steps of: forming said SiGe layer on a semiconductor substrate; simultaneously forming in said SiGe layer a first set of collectors for said first set of bipolar transistors and a second set of collectors for said second set of bipolar transistors; simultaneously forming a first base layer, having a base dopant and first base thickness, for said first set of bipolar transistors and for said second set of bipolar transistors, said first base layer being formed in a layer of material having a concentration ramp of Ge concentration in the vicinity of a base-collector junction; forming a second layer of base material over and abutting said first base layer in said second set of transistors; and simultaneously forming a layer of emitter material disposed above and abutting said bases in said first set and second sets of bipolar transistors, said emitter material having a concentration curve of emitter dopant extending through at least part of said base so that said concentration curve of emitter dopant in said first set intersects said concentration ramp of said first set in a vertical location where a concentration ramp rate of said first set is greater than a threshold value; and said second layer of base material having a thickness such that said second set of transistors have a greater distance between a base-emitter junction and a base-collector junction, so that said concentration curve of emitter dopant in said second set intersects said concentration ramp of said second set in a vertical location where a concentration ramp rate of said second set is less than said threshold value.