Patent ID: 7248522

Claim:
An integrated circuit device including a memory array comprising: at least one sense amplifier having Active, Standby and Sleep modes thereof coupled to complementary bit lines, said sense amplifier having first and second voltage nodes thereof; a first transistor coupling said first voltage node to a first voltage source, a control terminal of said first transistor being coupled to receive a first control signal; and a second transistor coupling said second voltage node to a second voltage source, a control terminal of said second transistor being coupled to receive a second control signal, wherein, in a Standby Mode of operation, said first control signal is substantially at a level of said first voltage source and said second control signal is substantially at a level of said second voltage source and wherein, in a Sleep Mode of operation, said first control signal is substantially at a level greater than said first voltage source and said second control signal is substantially at a level lower than said second voltage source.