Patent ID: 7129152

Claim:
A method for fabricating a short channel field-effect transistor, comprising the steps of: a) preparing a semiconductor substrate; b) forming a first mask layer at a surface of the semiconductor substrate; c) lithographically patterning the first mask layer to form a first mask with substantially perpendicular side walls; d) carrying out a chemical conversion of at least one side wall of the first mask to form a sublithographic mask layer; e) lithographically patterning the sublithographic mask layer to form a sublithographic gate sacrificial layer; f) removing the first mask; g) forming spacers at side walls of the sublithographic gate sacrificial layer; h) forming at least one of connection regions and source/drain regions in the semiconductor substrate; i) forming a sacrificial filling layer to embed the sublithographic gate sacrificial layer and the spacers; j) removing the sublithographic gate sacrificial layer to form a gate recess; k) forming a gate dielectric in the gate recess; l) forming a control layer in the gate recess; m) removing the sacrificial filling layer in order to uncover the source/drain regions; n) forming connection layers for the source/drain regions; and o) forming an insulation layer in order to level a semiconductor surface.