Patent ID: 8084300

Claim:
A method for manufacturing a semiconductor package, comprising: preparing a substrate having an interior, a top surface and an opposing bottom surface, including forming conducting paths in the interior of the substrate, and forming conducting pads on the top surface and on the bottom surface, aligned with respective ends of said conducting paths and in electrical contact therewith; mounting semiconductor devices on the top surface; applying a molding compound to the substrate and to the semiconductor devices, thereby covering the top surface and encapsulating the semiconductor devices; contacting the bottom surface to a holding surface; cutting through the molding compound, the substrate, and the holding surface, thereby forming a plurality of package units each having an upper surface, side surfaces, a semiconductor device, and a conducting pad portion exposed at a side surface, neighboring package units having a first gap therebetween with a first width; causing the package units to be disposed on a final surface so that neighboring package units have a second gap therebetween with a second width greater than the first width, thereby permitting coverage of said side surfaces by a conductive shield layer, and wherein the second width is approximately equal to a height of a package unit; subsequently applying the conductive shield layer to the package units, to form a conductive shield covering each package unit at the upper surface and the side surfaces thereof and covering portions of the final surface adjacent to the side surfaces, thereby making electrical contact with said exposed conducting pad portion, neighboring shielded package units being separated by a gap having a width approximately equal to a height of a package unit; and removing the package units from the final surface to form singulated packages.