Patent ID: 7154327

Claim:
A noise filtering circuit comprising: a first signal source configured to provide a first signal that is synchronized with a first clock signal and exhibits a first noise; a second signal source configured to provide a second signal that is synchronized with a second clock signal and exhibits a second noise, wherein the first and second clock signals are asynchronous; a first delay circuit configured to generate a first blanking signal in response to the first clock signal, wherein the first blanking signal has a duration corresponding with a duration of the first noise; a second delay circuit configured to generate a second blanking signal in response to the second clock signal, wherein the second blanking signal has a duration corresponding with a duration of the second noise; a first storage device configured to store the first signal in response to the first blanking signal, such that the first noise is not present when the first signal is stored; a second storage device configured to store the second signal in response to the second blanking signal, such that the second noise is not present when the second signal is stored; and a logic circuit coupled to receive the first and second signals stored in the first and second storage devices, and in response, provide an output signal.