Patent ID: 7492016

Claim:
A chip including a hybrid complementary metal oxide semiconductor (“CMOS”) structure, comprising: a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of said substrate, said first region and said bulk region having a first crystal orientation, said bulk device further including a first gate conductor overlying said first region; a SOI device disposed in a semiconductor-on-insulator (“SOI”) layer separated from said bulk region of said substrate by a buried dielectric layer, said SOI layer having a second crystal orientation different from said first crystal orientation, said SOI device including a second gate conductor overlying said SOI layer of said substrate; a first diode disposed in a second region of said substrate in conductive communication with said bulk region, said first diode having a cathode in conductive communication with at least said first gate conductor and having an anode in conductive communication with said bulk region, said first diode having a breakdown voltage in excess of which said first diode is highly conductive, such that said first diode is operable to conduct a discharge current to said bulk region when a voltage on said first gate conductor exceeds said breakdown voltage; a second diode disposed in a third region of said substrate in conductive communication with said bulk region, said second diode having a cathode in conductive communication with at least one of a source region or a drain region of at least said SOI device and an anode in conductive communication with said bulk region, said second diode having a breakdown voltage in excess of which said second diode is highly conductive, such that said second diode is operable to conduct a discharge current to said bulk region when a voltage on said at least one of said source region or said drain region exceeds said breakdown voltage, wherein said cathode of said first diode vertically overlies said anode of said first diode and said cathode of said second diode vertically overlies said anode of said second diode; and a first conductive line conductively connecting one of a source region of said bulk device or a drain region of said bulk device to one of a source region of said SOI device or a drain region of said SOI device, wherein a conduction path between said first gate conductor and said cathode of said first diode includes a second conductive line, said second conductive line being disposed at a greater height from a major surface of said semiconductor substrate than said first gate conductor.