Patent ID: 8603888

Claim:
A process comprising: forming n spaced-apart select line control gates, n being an integer greater than one; forming a dielectric over the n select line control gates; forming n+1 spaced-apart electrode contacts in the dielectric such that one of the spaced-apart electrode contacts is disposed between each of two select line control gates of the n spaced-apart select line control gates; forming n+1 electrodes, wherein each of the n+1 electrodes contacts a respective one of the n+1 electrode contacts; forming n variable-resistance material memory (VRMM) cells coupled between pairs of ones of the n+1 electrodes; forming 2n conductive spacers, wherein each of the conductive spacers are in contact with one of the VRMM cells and one of the n+1 electrodes; forming a lower film and an upper film such that each spacer electrode contacts the lower film and the upper film with the variable-resistance material of the respective VRMM cell between the lower film and the upper film; and forming a select gate and a sense line contact that are spaced apart and, when the n select line control gates are all in one of an on state or an off state, are coupled in series with the n select line control gates.