Patent ID: 7045848

Claim:
A semiconductor integrated circuit device comprising: a memory cell including a first region formed in a semiconductor region, a second region formed in said semiconductor region, a channel region interposed between said first region and said second region, a first gate electrode, a second gate electrode, a first silicide layer formed on said first gate electrode, a second silicide layer formed on said second gate electrode and electrically isolated from said first silicide layer, a third silicide layer formed on said second region, a fourth silicide layer formed on said first region, and a first insulating film for electrically isolating said first gate electrode from said second gate electrode, wherein said channel region comprises a first channel region and a second channel region such that said first channel region is arranged between said first region and said second channel region and such that said second channel region is arranged between said second region and said first channel region, wherein a first gate insulating film is provided between said first channel region and said first gate electrode, wherein a second gate insulating film is provided between said second channel region and said second gate electrode, wherein said second gate insulting film includes a nonconductive charge trap film corresponding to a charge storage region, wherein said first gate electrode has a first side surface and a second side surface, opposed to said first side surface, such that said first insulating film is formed between said first side surface and said second nate electrode, wherein a first sidewall spacer comprised of an insulating film is formed in self-alignment with a side wall on said second gate electrode and with a side surface of said nonconductive charge trap film, wherein said second silicide layer and said third silicide layer are electrically isolated by said first sidewall spacer, and wherein said first silicide layer and said fourth silicide layer are electrically isolated by a second sidewall spacer comprised of an insulating film and formed in self-alignment with said second side surface of said first gate electrode.