Patent ID: 7675794

Claim:
A design structure embodied in a machine readable medium, the design structure comprising: a write circuit for an SRAM cell or an SRAM array, wherein said SRAM cell or said SRAM array is supplied by a higher cell specific voltage (Vcs), said write circuit further comprising a gate in order to switch said write circuit on and off, wherein said write circuit is driven at a core logic voltage (Vdd), characterized in that during write operations, said write circuit is driven by said higher cell specific voltage (Vcs), characterized in that in order to drive said write circuit by said higher cell specific voltage (Vcs), said gate of said write circuit is driven by said first higher voltage (Vcs) and characterized in that in order to drive said gate of said write circuit with said first higher voltage (Vcs), an arrangement of at least three successive stages is used, said at least three successive stages comprising an even number of stages supplied by said first higher voltage (Vcs).