Patent ID: 8766958

Claim:
A gate driving circuit unit comprising: a signal input interface for receiving an input pulse signal; a signal output interface for outputting a driving signal; a first clock signal control module comprising: a driving unit comprising a control end that transfers a first clock signal to the signal output interface after applied with a driving voltage; and a clock feed-through suppressing unit that couples the control end to the signal output interface under control of the first clock signal; wherein the first clock signal lags one phase behind the input pulse signal; an input signal control module that receives the input pulse signal from the signal input interface and provides the driving voltage for the control end; a third clock signal control module that provides a shutdown voltage for the control end under control of a third clock signal, the third clock signal lagging two phases behind the first clock signal; and a fourth clock signal control module that pulls down the voltage of the signal output interface under control of a fourth clock signal, the fourth clock signal being one phase ahead of the first clock signal.