Patent ID: 8843805

Claim:
A method comprising: receiving, with a memory controller of a computing device that controls a dynamic random access memory (DRAM) comprising a plurality of banks, a write command that specifies data and an address, wherein each of the banks comprises DRAM storage elements arranged in a two-dimensional array of rows and columns, wherein each of the DRAM storage elements is a bit in a physical address space for the DRAM; in response to receiving the write command, writing, with the memory controller via a first command to the DRAM, the data to a physical address in the DRAM for the data that is based at least on the address specified in the write command; and writing, with the memory controller via a second command to the DRAM, error protection bits for the data to a physical address in the DRAM for the error protection bits that is based at least on the address specified in the write command, wherein the physical address in the DRAM for the data and the physical address in the DRAM for the error protection bits identify non-contiguous data storage locations in the physical address space of the DRAM.