Patent ID: 8384061

Claim:
A nonvolatile memory device comprising: a substrate; a plurality of first wires which are formed on the substrate and extend in parallel with each other in a first direction; a first interlayer insulating layer formed over the substrate and the plurality of first wires; a plurality of second wires which are formed on the first interlayer insulating layer and extend in parallel with each other in a second direction crossing the first direction when viewed in a thickness direction of the first interlayer insulating layer; a second interlayer insulating layer which is formed over the first interlayer insulating layer and the plurality of second wires; and a plurality of third wires which are formed on the second interlayer insulating layer and extend in parallel with each other in a third direction crossing the second direction when viewed in a thickness direction of the second interlayer insulating layer; a plurality of first through-holes formed to penetrate the first interlayer insulating layer at three-dimensional cross points of the plurality of first wires and the plurality of second wires, respectively; a plurality of second through-holes formed to penetrate the second interlayer insulating layer at three-dimensional cross points of the plurality of second wires and the plurality of third wires, respectively; first nonvolatile memory elements; and second nonvolatile memory elements, wherein: each of the plurality of second wires has a stacked structure including a first semiconductor layer, a conductive layer and a second semiconductor layer which are stacked together in this order, each of the first nonvolatile memory elements includes a first resistance variable layer and a first electrode layer which are stacked together in this order on an associated one of the plurality of first wires and inside an associated one of the plurality of first through-holes, each of the second nonvolatile memory elements includes a second electrode layer and a second resistance variable layer which are stacked together in this order on an associated one of the plurality of second wires and inside an associated one of the plurality of second through-holes and are connected to an associated one of the plurality of third wires, the first electrode layer, the first semiconductor layer and the conductive layer constitute each of first diode elements, the conductive layer, the second semiconductor layer and the second electrode layer constitute each of second diode elements, each of the first semiconductor layer of the plurality of second wires entirely covers an upper opening of each of the plurality of first through-holes and protrudes outward over the upper opening, and each of the second semiconductor layer of the plurality of second wires entirely covers a lower opening of each of the plurality of second through-holes and protrudes outward over the lower opening.