Patent ID: 8516320

Claim:
An integrated circuit comprising: A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; B. an IC TAP domain including: i. a TAP controller having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input coupled to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input coupled to the test data in lead, a test data output, and control inputs connected to the control outputs; and iv. multiplexer circuitry coupling the test data outputs of the instruction register and the data register to the test data out lead; C. a core TAP domain including: i. a TAP controller having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input coupled to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input coupled to the test data in lead, a test data output, and control inputs connected to the control outputs; and iv. multiplexer circuitry coupling the test data outputs of the instruction register and the data register to the test data out lead; and D. output linking circuitry including multiplexer circuitry having a first input connected to the test data output of the data register of the IC TAP domain, a second input connected to the test data output of the data register of the core TAP domain, and an output coupled to the test data out lead.