Patent ID: 8693254

Claim:
A non-volatile semiconductor memory device comprising: a memory array comprising a plurality of blocks each comprising a set of NAND cell units, each NAND cell unit comprising a memory string comprising a plurality of memory cells connected in series; a plurality of word-lines each commonly connecting gates of memory cells arranged in a first direction; a word-line transfer transistor having a first end connected to one of the word-lines; a control gate line having a first end connected to a second end of the word-line transfer transistor; and a leak sense circuit configured to perform a leak sense operation of sensing a leak current between the word-lines, the leak sense circuit comprising: a limiter circuit configured to compare a voltage of the control gate line and a set voltage, thereby switching a logic of a flag signal; a booster circuit having a function of boosting a voltage supplied to the control gate line, and being configured to start or stop its operation according to the logic of the flag signal; a leak reference circuit having a function of leaking a leak reference current from the control gate line; a counter configured to generate a first count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered non-conductive and the leak reference circuit is driven, the counter being configured to generate a second count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered conductive and the leak reference circuit is undriven; and a comparator configured to compare the first count value and the second count value.