Patent ID: 7024594

Claim:
A computer system adapted to process different types of faults, with a given error coverage rate, the computer system comprising: at least two processing unit cores, each processing unit core comprising: a microprocessor; a memory having one or more segments and protected by a device generating and controlling an error detection and correction code; and a memory access watch device comprising an intrinsic means for protecting itself against transient errors, comprising: an electronic server set adapted to control said memory; a means for the segmentation of said memory and verification of a right for access to each of said one or more segments of said memory; a means for protecting said one or more segments of said memory allocated to saving recovery context information; and a means for generating a correction demand signal to said at least two processing unit cores and to a control device, each of said at least one processing unit adapted to execute the same software asynchronously; a control device, comprising: a centralized electronic server set including at least one clock generator, at least one timer, and at least one watch; a means for receiving said correction demand signal; a macro-synchronization means for the at least two processing unit cores, said macro-synchronization means adapted to upon receipt of a first one or more messages from a first of said at least two processing unit cores, wait for a predetermined time for receipt of a second one or more messages from a second of said at least two processing unit cores, said first one or more messages equivalent to said second one or more messages, each processing unit core having stopped at the same point in the software to transmit said first one or more messages and said second one or more messages; a means for initiating a correction phase for different cases of error, said means adapted to, if said messages are different, simultaneously transmit a correction phase demand to each of said at least two processing unit cores; a means for executing said messages and releasing said at least two processing unit cores if said messages are identical; a means for direct memory access in said at least two processing unit cores; and a means for processing inputs and outputs; and one or more links linking each processing unit core to said at least two processing unit cores and said control device.