Patent ID: 7904772

Claim:
A circuit protected against timing errors or parasitic disturbances, the circuit comprising: a combinatory logic circuit having at least one output, said at least one output having a value at an occurrence of an edge of a clock signal and maintaining this value at least for a determined time period in the absence of errors or disturbances, said clock signal having a determined frequency and phase; a first flip-flop connected to said at least one output and rated by a clock; a second flip-flop connected to said at least one output and rated by the clock, said clock signal of determined frequency and phase, and delayed by a predetermined delay shorter than said time period; and a circuit for analyzing outputs of the flip-flops, the analysis circuit indicating an occurrence of a timing error or parasitic disturbance if the flip-flop outputs are different, by setting the output of the analysis circuit (comparator) at a pre-determined value that indicates the presence of an error or disturbance in the circuit, whereby such an error may be corrected.