Patent ID: 8829953

Claim:
A programmable clock divider for generating a divided clock signal based on an input clock signal, comprising: a first comparator that compares a ratio value and a count value, and generates a first signal; a second comparator that compares the ratio value and the count value, and generates a second signal; a first flip-flop, having an input terminal connected to the first comparator for receiving the first signal, a clock terminal for receiving the input clock signal, and an output terminal that provides a delayed first signal; a second flip-flop, having an input terminal connected to the second comparator for receiving the second signal, a clock terminal for receiving the input clock signal, and an output terminal that provides a pre-delayed second signal; an active-low latch, connected to the second flip-flop, that receives the pre-delayed second signal and provides a delayed second signal; and a multiplexer having a first input terminal connected to the first flip-flop for receiving the delayed first signal, a second input terminal connected to the active-low latch for receiving the delayed second signal, a select terminal for receiving the input clock signal, and an output terminal for generating the divided clock signal, wherein the second delayed signal is output by the multiplexer when the input clock signal is at a logic high state and the first delayed signal is output by the multiplexer when the input clock signal is at a logic low state.