Patent ID: 7793178

Claim:
A memory cell supporting a functional mode and a scan mode, said memory cell being designed to receive and store a functional input in said functional mode, said memory cell being designed to receive and store a scan input in said scan mode, said memory cell comprising: a master latch comprising: a first switch receiving said functional input and a first clock signal as inputs, said first switch providing said functional input when said first clock signal is operative, wherein said first clock signal is operative in said functional mode and non-operative otherwise; and a second switch receiving said scan input and a second clock signal as inputs, said second switch providing said scan input when said second clock signal is operative, said second clock signal being operative in said scan mode and non-operative otherwise; a slave latch comprising: a third switch coupled to the master latch; a first inverter and a second inverter, a fourth switch and a fifth switch, wherein said first inverter and said second inverter are connected back-to-back between the third switch and a first node if either said fourth switch or said fifth switch is in an ON state; a third inverter, wherein the third switch is coupled between said first node and said third inverter; a NOR gate receiving the output of said third inverter on one input, and a inverse of a scan enable signal on another input, and wherein the output terminal of said NOR gate provides a stored value of said functional input when said scan enable signal is at a logic zero; and a NAND gate coupled to said first node on one input and said scan enable signal on another input, wherein the output terminal of said NAND gate provides a stored value of said scan input when said scan enable signal is at a logic one.