Patent ID: 7786786

Claim:
A multiphase clock circuit comprising: a master clock signal of frequency fc; a divide by N frequency divider circuit having an input and an output; where N is any integer greater than one (1); means applying the master clock signal to the input of the divide by N circuit for producing a base clock signal of frequency fc/N at its output; a series chain of N clocked data flip-flops (DFFs), each one of said DFFs having a data input port, a data output port and a clock input port; and said DFFs being interconnected in an ordered sequence with the output of the divide by N circuit being coupled to the data input port of the first DFF of the chain and the data output port of each succeeding flip flop, except for the last, being connected to the data input port of a succeeding flip-flop; wherein the flip-flops and the divide by N circuit are formed using superconducting Josephson Junctions (JJs) interconnected to form rapid single flux quantum (RSFQ) circuits whose operations are based on the distribution of quantized data pulses, where each single-flux-quantum (SFQ) pulse has a peak height on the order of 1 millivolt (mV) and a pulse width on the order of 2 picoseconds (ps) such that the time-integrated pulse is precisely equal to 2.07 mV−ps=h/2e=Φ 0 , the fundamental magnetic flux quantum; and means responsive to the master clock signal for concurrently applying a clock signal of frequency fc to the clock input port of all the DFFs for producing N sequentially and equally spaced clocked signals, each of frequency fc/N.