Patent ID: 7898895

Claim:
A semiconductor device, comprising: a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines, the plurality of word lines extending in a first direction in parallel to one another, the plurality of bit lines extending in a second direction in parallel to one another, the first direction intersecting the second direction, the memory cell array being defined by a plurality of sides, said plurality of sides including a first side parallel to the word lines, a second side parallel to the bit lines, a third side being opposed to the first side, and a fourth side being opposed to the second side; a first input/output port defined for inputting/outputting data to/from the memory cell array, the first input/output port being arranged on the first side and the third side of the memory cell array; a second input/output port defined for inputting/outputting data to/from the memory cell array, the second input/output port being arranged on the second side of the memory cell array; a plurality of sense amplifiers to amplify data of the memory cells through the plurality of bit lines; a first select circuit which is controlled to be on/off by one or more first select control lines each extending in the first direction, the first select circuit being connected between the plurality of sense amplifiers and the first input/output port and provided along the first side of the memory cell array; a second select circuit which is controlled to be on/off by one or more second select control lines each extending in the second direction, the second select circuit being connected between the plurality of sense amplifiers and the second input/output port and provided along the first side of the memory cell array; a first column decoder to selectively activate the one or more first select control lines in response to an input column address, the first column decoder being arranged along the second side of the memory cell array; and a second column decoder to selectively activate the one or more second select control lines in response to the input column address, the second column decoder being arranged along the first side of the memory cell array, and wherein each of a plurality of bit lines is directly connected to a corresponding sense amplifier, a corresponding first select circuit, and a corresponding second select circuit.