Patent ID: 6988237

Claim:
An integrated circuit comprising: a memory comprising a plurality of memory lines, each memory line comprising a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line, wherein one or more vector pairs of test data are stored in the memory, wherein bit values of at least an nth vector pair alternate every n bits, and wherein vectors in at least a vector pair are shifted n bits relative to each other; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit comprising an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch comprising first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.