Patent ID: 7898854

Claim:
A semiconductor memory device comprising: first to third memory cell units each including a first select transistor, a second select transistor and a plurality of memory cell transistors which are connected in series in a first direction between the first select transistor and the second select transistor, the first select transistors of the respective memory cell units being adjacent to each other in a second direction and the second select transistors of the respective memory cell units being adjacent to each other in the second direction; a first bit line which is commonly connected to an end portion of the first select transistor of the first memory cell unit and to an end portion of the first select transistor of the second memory cell unit; a second bit line which is connected to an end portion of the first select transistor of the third memory cell unit; a first source line which is connected to an end portion of the second select transistor of the first memory cell unit; and a second source line which is commonly connected to an end portion of the second select transistor of the second memory cell unit and to an end portion of the second select transistor of the third memory cell unit, wherein those of the memory cell transistors, which neighbor the first and second select transistors, are used as select memory cell transistors, and the select memory cell transistors include a first and second select memory cell transistor where each of the first and second select memory cell transistors includes a charge accumulation layer which is configured to store multi-bit data.