Patent ID: 8917588

Claim:
A fast Fourier transform and inverse fast Fourier transform (FFT/IFFT) operating core, the FFT/IFFT core comprising: a first multiplexer, for multiplexing a first FFT input sequence and a third FFT input sequence; an inputting buffer, for storing and outputting the first FFT input sequence; and an operating module having a zero operating stage, a first operating stage, and a K-th operating stage, wherein the zeroth operating stage, based on a corresponding process indicating signal and a corresponding bypass indicating signal, either for performing one of bypassing an output signal of the first multiplexer and transforming the output signal of the first multiplexer by an FFT operation so as to generate a first output signal 1 0 , or for performing one of bypassing a second output signal 2 1 of the first operating stage and transforming the second output signal 2 1 of the first operating stage by an IFFT operation so as to generate a second output signal 2 0 ; the first operating stage, based on the corresponding process indicating signal and the corresponding bypass indicating signal, either for performing one of bypassing the first output signal 1 0 of the zeroth operating stage and transforming the first output signal 1 0 of the zeroth operating stage by an FFT operation so as to generate a first output signal 1 1 , or for performing one of bypassing a second output signal 2 2 of a second operating stage and transforming the second output signal 2 2 of the second operating stage by an IFFT operation so as to generate a second output signal 2 1 ; and the K-th operating stage, based on the corresponding process indicating signal and the corresponding bypass indicating signal, either for performing one of bypassing a first output signal 1 K−1 of a (K−1)-th operating stage and transforming the first output signal 1 K−1 of the (K−1)-th operating stage by an FFT operation so as to generate a first output signal 1 K , or for performing one of bypassing a second IFFT input sequence and transforming the second IFFT input sequence by an IFFT operation so as to generate a second output signal 2 K , K is an integer greater than or equal to 2; wherein the corresponding process indicating signal and the corresponding bypass indicating signal are generated, the corresponding process indicating signal indicates that one of the first FFT input sequence, the second IFFT input sequence, and the third FFT input sequence inputted to the operating module is processed by either a decimation-in-time algorithm or a decimation-in-frequency algorithm, and the corresponding bypass indicating signal indicates whether the one of the first FFT input sequence, the second IFFT input sequence, and the third FFT input sequence inputted to the operating module directly passes the operating module.