Patent ID: 6936878

Claim:
A semiconductor memory device having a plurality of memory cells arranged in an array, comprising: a flip-flop of said memory cells having a pair of inverters formed of driver MOS (Metal Oxide Semiconductor) transistors and load elements; a pair of access MOS transistors of said memory cells electrically connected to input nodes of said inverters respectively; an interlayer insulation film covering said access MOS transistors and said driver MOS transistors; a pair of capacitive elements of said memory cells formed on said interlayer insulation film and electrically connected to said input nodes of said inverters; a word line electrically connected to gate electrodes of said pair of access MOS transistors and extending in the same direction as an extending direction of gate electrodes of said driver MOS transistors and disposed between said gate electrodes of said driver MOS transistors; a pair of active region patterns formed by integrating a pair of active regions of said access MOS transistors with a pair of active regions of said driver MOS transistors and extending in a direction orthogonal to an extending direction of said word line; and a pair of bit lines extending in a direction orthogonal to the extending direction of said word line and electrically connected to active regions of said access MOS transistors respectively; wherein a length of said memory cells in the extending direction of said word line is longer than that in an extending direction of said bit lines, said bit lines are disposed above said access MOS transistors and said driver MOS transistors, said load elements are disposed above said bit lines, and said capacitive elements are disposed above said load elements.