Patent ID: 7053691

Claim:
A circuit comprising: a first transistor, a second transistor, a third transistor; and a first power source, a second power source, and an output source; wherein if both the first power source and the second power source are available or if the first power source is available but the second power source is not available, then the circuit selects the first power source as the output source; the first transistor and the third transistor are on; and the second transistor is off; else if the first power source is not available and the second power source is available, then the circuit selects the second power source as the output source; the first transistor and the third transistor are off; and the second transistor is on; a gate of the second transistor is directly coupled to the first power source; and a delay circuit for eliminating the race condition between the first power source and the second power source, when both the first power source and the second power source are available; the delay circuit being coupled between the first power source and a gate of the first transistor.