Patent ID: 8680691

Claim:
A semiconductor device comprising: a package substrate including an upper surface, a plurality of substrate pads formed on the upper surface, a plurality of wiring lines formed on the upper surface, and a lower surface opposite to the upper surface, the upper surface having a first substrate side and a second substrate side crossing to the first substrate side, the wiring lines being connected with the substrate pads, respectively; a semiconductor chip including a main surface, a plurality of chip pads formed on the main surface, and a back surface opposite to the main surface; a plurality of first electrodes arranged between the semiconductor chip and the package substrate; and a plurality of second electrodes formed over the lower surface; wherein the semiconductor chip is mounted over the package substrate via the first electrodes such that the main surface faces to the upper surface; wherein the chip pads are electrically connected with the substrate pads via the first electrodes, respectively; wherein the wiring lines are extended from the substrate pads toward the first substrate side, respectively; wherein the substrate pads are arranged along a first substrate side of the upper surface in a plan view, and arranged in rows; wherein the substrate pads has a first substrate pad group including a plurality of first substrate pads, and a second substrate pad group including a plurality of second substrate pads; wherein the first substrate pads are arranged in a matrix comprised of a plurality of first rows each parallel to a direction in which the first substrate side is extended and a plurality of first columns each parallel to a direction in which the second substrate side is extended, and arranged with a first pitch; wherein the second substrate pads are arranged in a matrix comprised of a plurality of second rows each parallel to the direction in which the first substrate side is extended and a plurality of second columns each parallel to the direction in which the second substrate side is extended, and arranged with the first pitch; wherein the second substrate pads are arranged further from the first substrate side of the upper surface than the first substrate pads in the plan view, and arranged further from the second substrate side of the upper surface than the first substrate pads in the plan view; wherein a distance between a first extended line of a first grid line connecting a plurality of first outer substrate pads of the first substrate pads with each other and a second extended line of a second grid line connecting a plurality of second outer substrate pads of the second substrate pads with each other is greater than zero and less than the first pitch; wherein each of the first outer substrate pads is arranged in a column of the plurality of first columns closest to the second substrate pad group in the plan view; and wherein each of the second outer substrate pads is arranged in a column of the plurality of second columns closest to the first substrate pad group in the plan view.