Patent ID: 7250651

Claim:
A semiconductor memory device comprising: a semiconductor body with a main semiconductor surface; shallow trench isolations arranged parallel to one another at said surface and running along a first direction; transistor bodies of semiconductor material provided for memory cell transistors and located at said main semiconductor surface between said shallow trench isolations; floating gate electrodes formed of electrically conductive material and electrically insulated by dielectric material, each of said floating gate electrodes being provided as a storage node of one of said memory cell transistors; each of said floating gate electrodes being arranged on top of one of said transistor bodies, said dielectric material forming a tunnel dielectric between the floating gate electrode and an upper surface of said transistor body; control gate electrodes formed of electrically conductive material, each control gate electrode capacitively coupled to a corresponding one of said floating gate electrodes via a coupling dielectric between the control gate electrode and an upper surface of the coupled floating gate electrode; wordlines electrically connecting said control gate electrodes; said upper surface of said transistor body forming a set of points, where a tangential plane to said surface exists, which has a normal directed perpendicularly to said plane; said coupling dielectric having a thickness at said points of said upper surface of said transistor body, a value of said thickness being measured along the direction of said normal at that point; a primary tunnel area being formed by an area of said upper surface of said transistor body in which said thickness deviates at most by twenty percent from a minimum value of said thickness; said primary tunnel area having a dimension across one transistor channel which is measured byte length of a curve formed byte intersection of said primary tunnel area of one of said memory cell transistors and a plane which is orthogonal to the first direction; and said dimension being larger than a minimal distance between adjacent shallow trench isolations by at least ten percent.