Patent ID: 8700813

Claim:
An information handling system comprising: a first processor coupled to a first device via a first chipset; a second processor coupled to a second device via a second chipset; a basic input/output system (BIOS) including a system management interrupt (SMI) handler; and a management controller; wherein the management controller is configured to: receive a first data packet bound for the first device; send the first data packet to the first device via the first chipset; and wherein the BIOS is configured to: receive a notification from the management controller, the notification indicating that the management controller has received a second data packet bound for the second device; determine that the second device is communicating with the second processor; assign a peripheral component interconnect express (PCIe) capability identifier to the second device; retrieve the second data packet from the management controller; send a payload of the second data packet to the second device, wherein the payload is sent via the PCIe capability identifier; and send a status message to the management controller, the status message indicating that the payload has been delivered to the second device.