Patent ID: 7788528

Claim:
A repair module adapted to a memory for repairing one of n bit lines through m bit bus, m≧n, and comprising: a decoding unit, generating a switching control signal and a selecting control signal according to an index value of the one of the n bit lines; a plurality of switching units, each of the switching units having a first input terminal, a second input terminal, a first output terminal and a second output terminal, the first and the second input terminals of the 1 st switching unit respectively coupled to the 1 st bit line and a dummy line, the first and the second input terminals of the i th switching unit respectively coupled to the 1 st bit line and the first output terminal of the (i−1) th switching unit, 2≦i≦m, wherein each of the switching units conducts the first and the second input terminals to the first and the second output terminals respectively, or conducts the first and the second input terminals to the second and the first output terminals respectively according to the switching control signal; and a plurality of multiplexers, each of the multiplexers having a first input terminal and a second input terminal, the first and the second input terminals of the j th multiplexer respectively coupled to the second output terminal of the (j+1) th switching unit and the second output terminal of the j th switching unit, 1≦j≦m−1, the first and the second input terminals of the m th multiplexer respectively coupled to the first and the second output terminals of the m th switching unit, wherein each of the multiplexers selects a bit line of the first input terminal thereof or a bit line of the second input terminal thereof for signal transmission according to the selecting control signal.