Patent ID: 8799712

Claim:
An integrated circuit comprising: A. core circuitry having scan paths, the scan paths including scan data input leads, scan data output leads, and scan control input leads; and B. a test access mechanism having: i. a serial data input lead, ii. a serial data output lead, iii. parallel data output leads coupled to the to the scan data input leads, iv. parallel data input leads coupled to the scan data output leads, v. control output leads coupled to the scan control input leads, vi. a clock signal input lead; vii. a functional clock signal input lead; viii. a test/read input lead, ix. a test access mechanism enable input lead, x. a scan frame input register having a scan frame input lead connected with the serial data input lead, the scan frame input register including a stimulus section, a command section, and a frame marker section connected in series with the serial data input lead, and xi. a scan frame copy register having an output coupled with the serial data output lead, the scan frame copy register being coupled to the stimulus section, the command section, and the frame marker section of the scan frame input register, the scan frame copy register being coupled to the serial data input lead through the scan frame input register.