Patent ID: 7636904

Claim:
A computer-implemented method to evaluate a layout of an integrated circuit design, the method comprising: for each position as a current position, in a plurality of positions along a longitudinal direction of a feature in the integrated circuit design: automatically performing lithography simulation at a plurality of locations in a transverse direction relative to the longitudinal direction, to obtain a corresponding plurality of simulated intensities at said current position, automatically determining at least one constant at said current position, said constant being comprised in a formula that models the plurality of simulated intensities as a function of distance in the transverse direction at said current position, and automatically computing a value at said current position, based on at least the formula, the constant, and a known threshold for intensity; and automatically locating a position of a critical dimension in the feature, based on at least a plurality of values at the plurality of positions, obtained from said computing; and automatically applying at least one test, based at least on the position of the critical dimension in the feature obtained from said automatically locating; wherein a result of said automatically applying at least one test is comprised in a memory.