Patent ID: 8601329

Claim:
A test apparatus for testing a device under test, comprising: a test executing section configured to execute a test on the device under test; a fail memory, coupled to the test execution section, configured to store a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory, coupled to the fail memory, configured to store the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory, coupled to the buffer memory, configured to store the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section, coupled to the cache memory, configured to analyze the test result stored in the cache memory.