Patent ID: 7205803

Claim:
A delay circuit producing an output clock signal, said delay circuit comprising: a plurality of delay cells arranged in series with each other, said plurality of delay cells including an input/output delay cell which receives an external clock signal and outputs an adjusted clock signal, the plurality of delay cells having at least two delay cells with different delays, the plurality of delay cells being configured so that a first delay cell of the at least two delay cells with different delays is alternated with a second delay cell of the at least two delay cells with different delays for ensuring linearity; a delay control circuit coupled to said plurality of delay cells, said delay control circuit being operable to select a clock signal path in said delay circuit when receiving at least one delay command signal, wherein each of said plurality of delay cells comprises at least one inverting logic circuit and at least one tri-state inverting logic circuit, wherein said delay command signal includes decoding code, said decoding code further including a plurality of bits, a bit included in the plurality of bits being configured for powering the at least one tri-state inverting logic circuit on and off, wherein the delay circuit is configured for having an intrinsic delay for the delay circuit equivalent to a minimum intrinsic delay of a single delay cell included in the plurality of delay cells of the delay circuit.