Patent ID: 7038674

Claim:
A method for driving a display device having a gamma correction circuit for correcting a video signal at a gamma value of 2.0 or below and a plurality of pixels disposed with a light emitting element, a driving TFT for controlling drive of the light emitting element, a switching TFT for controlling drive of the driving TFT, and an erasing TF 1 , the method comprising: inputting a digital video signal to the plurality of pixels in n write periods Ta 1 , Ta 2 , . . . and Tan while the switching TFT is held in ON-state; selecting to light or not to light the pixel by the digital video signal in display periods Tr 1 , Tr 2 , . . . and Trn; and erasing the digital video signal inputted to the plurality of pixels in erase times Te 1 , Te 2 , . . . and Te(m−1) while the erasing TFT is held in an ON-state, wherein one frame period has the n write periods Ta 1 , Ta 2 , . . . and Tan, and the (m−1) erase times Te 1 , Te 2 , . . . and Te(m−1) (m is an arbitrary number from 2 to n), among the n write periods Ta 1 , Ta 2 , . . . and Tan, the write periods Ta 1 , Ta 2 , . . . and Tam are overlapped with the erase times Te 1 , Te 2 , . . . and Te(m−1) each other, respectively, a period of time to start each of the (m−1) erase times Te 1 , Te 2 , . . . and Te(m−1) after having started each of the write periods Ta 1 , Ta 2 , . . . and Tan is the display periods Tr 1 , Tr 2 , . . . and Tr(m−1), a ratio of lengths of the display periods Tr 1 , Tr 2 , . . . and Trn is expressed by 2 0 :2 1 : . . . 2 (n−1) , and a period of time to start each of the n write periods Ta 1 , Ta 2 , . . . and Tan after having started each of the (m−1) erase times Te 1 , Te 2 , . . . and Te(m−1) is non-display periods Td 1 , Td 2 , and Tdn.