Patent ID: 8703620

Claim:
A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer over an active surface of the first portion and having formed thereon over a second portion of the semiconductor substrate an oxide layer over an active surface of the second portion, the first portion and the second portion being electrically isolated by a shallow trench isolation feature, wherein the active surface of the second portion is substantially parallel to the active surface of the first portion, and wherein the hard mask layer extends to a height above the active surface of the first portion that is higher than a height above the active surface of the second portion to which the oxide layer extends, the method comprising: removing the oxide layer from over the second portion to expose a surface region of the second portion and simultaneously reducing a height of the hard mask layer by applying a dilute hydrogen fluoride etching solution; recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution over both portions to form a recessed surface region, the APM solution being provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20; wherein recessing the surface region of the second portion comprises recessing the surface region to a depth between about 2 nm and about 20 nm, wherein recessing the surface region of the second portion comprises recessing the surface region at a temperature between about 40° C. and about 80° C.; and epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region of the second portion, wherein growing the SiGe comprises growing to a height that is approximately parallel with the active surface of the first portion.