Patent ID: 7202150

Claim:
A method of manufacturing a semiconductor memory device, comprising: (a) a step of depositing a first gate insulating film including a charge trapping layer on a substrate, then depositing a first electrically conductive film on said first gate insulating film, and then depositing an insulating film on said first electrically conductive film to form a stripe-shaped first gate electrode structure; (b) a step of depositing a second gate insulating film including a charge trapping layer on the entire substrate, with said first gate insulating film which covers said first gate electrode left, and depositing a second electrically conductive film on said second gate insulating film to form a second gate electrode structure extending in a striped pattern in a direction perpendicular to the direction of extension of said first gate electrode; (c) a step of implanting impurity ions to form a diffusion region of impurities on a portion of the substrate surface where there lack said first and second electrically conductive films; and (d) a step of forming an interlayer insulating film and forming a contact for electrical connection to said impurity diffusion region; and (e) a step of forming an electrically conductive interconnection, connecting to said diffusion region via said contact, on said inter-layer insulating film.