Patent ID: 8090967

Claim:
A method for managing power states for an interconnect to couple a processor to a memory comprising: generating an early warning signal upon receiving a request, in a memory controller, from the processor and transmitting the early warning signal to a control logic that controls the interconnect, wherein the early warning signal initiates a power state transition for the interconnect from a first power state to a second power state; decoding in the memory controller whether the request is a read or write operation and sending the request to the memory; transitioning the interconnect from the first power state to the second power state when the request is a write operation using the early warning signal to enable transmission of a completion response to the processor, otherwise, transitioning the interconnect from the first power state to the second power state based on comparison of a delay of a difference between the early warning signal and a response to the read operation from a memory with respect to a wakeup delay associated with the transition from the first power state to the second power state, the first power state a lower power state than the second power state.