Patent ID: 7825777

Claim:
An integrated circuit comparator, comprising: at least one n-bit comparator cell configured to determine a non-strict inequality between a first n-bit operand A[n−1, . . . , 0] and a second n-bit operand B[n−1, . . . , 0], according to the following expression and boolean equivalents of the following expression: C o = ( … ⁡ ( ( C i ⁡ ( A 0 + B 0 _ ) + A 0 ⁢ B 0 _ ) ⁢ ( A 1 + B 1 _ ) + A 1 ⁢ B 1 _ ) ⁢ … ⁡ ( A n - 2 + B n - 2 _ ) + A n - 2 ⁢ B n - 2 _ ) ⁢ ( A n - 1 + B n - 1 _ ) + A n - 1 ⁢ B n - 1 _ , where n is a positive integer greater than one, C i is a control input signal and C o or its complement is a control output signal, said at least one n-bit comparator cell comprising: a first pair of MOS transistors electrically connected in parallel between first and second nodes and having gate terminals that receive operand bit A 0 and a complement of operand bit B 0 , respectively; a second pair of MOS transistors electrically connected in parallel between the second node and a third node and having gate terminals that receive operand bit A 1 and a complement of operand bit B 1 , respectively; a third pair of MOS transistors electrically connected in series between the second node and a fourth node and having gate terminals that receive the operand bit A 0 and the complement of operand bit B 0 , respectively; a fourth pair of MOS transistors electrically connected in series between the third node and the fourth node and having gate terminals that receive the operand bit A 1 and the complement of operand bit B 1 , respectively; and a MOS input transistor having a first current carrying terminal electrically connected to the first node, a second current carrying terminal electrically connected to the fourth node and a gate terminal that receives the control input signal C i .