Patent ID: 7486530

Claim:
A memory device, comprising: a memory array having a plurality of memory cells arranged in rows and columns; a plurality of sense amplifiers coupled to the memory array; a data cache coupled to the plurality of sense amplifiers; and a data comparison circuit coupled between the data cache and the plurality of sense amplifiers, wherein the data comparison circuit contains a plurality of bit comparators, each of the plurality of bit comparators having an output directly coupled to a common error signal line, and where each bit comparator of the plurality of bit comparators is adapted to compare a first data value held in a sense amplifier of the plurality of sense amplifiers with a second data value held in the data cache and express a data match or data mismatch signal from an output of a bit comparator directly on the common error signal line, wherein the data comparison circuit further comprises: a pull-up circuit coupled to the common error signal line; and wherein each bit comparator of the data comparison circuit has a first and second data input, wherein the first data input is coupled to an output of the sense amplifiers and the second data input is coupled to an output of the data cache, and where each of the plurality of bit comparators is directly coupled to the common error signal line with an open collector output; wherein each bit comparator further comprises: an open collector XNOR gate having a first and second inputs and an open collector output, wherein the first XNOR input is coupled to the first data input, the second XNOR input is coupled to the second data input, and the open collector output is coupled directly to the common error signal line.