Patent ID: 7761835

Claim:
A design method of a semiconductor device comprising: using a computer to implement steps of: a mask region setting step of setting a mask region to a layout of the semiconductor device; a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero; and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout, wherein the parasitic parameter changing step includes: a virtual wiring layer generation step of generating the virtual wiring layer corresponding to the actual wiring layer of the semiconductor device; a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero; a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer; a wiring length correction step of extending the wiring part of the virtual wiring layer by a predetermined length; a wiring regeneration step of connecting the end of the wiring part of the virtual wiring layer with the end of a disconnected wiring of the actual wiring layer with a virtual contact plug, thereby providing a continuous wiring; and a defining step of defining the parasitic parameters of the virtual contact plug as zero.