Patent ID: 7781277

Claim:
An integrated circuit, comprising: a first transistor of a first conductivity type, including a first strained transistor channel, wherein the first transistor is characterized by a first value of stress along a first axis and a second value of stress along a second axis that is perpendicular to the first axis; a first stressor overlying the first transistor; a second transistor of a second conductivity type, including a second strained transistor channel, wherein the second strained transistor channel is characterized by a third value of stress along the first axis and a fourth value of stress along the second axis; wherein the first, second, and fourth values are tensile stress values and the third value is a compressive stress value; and a second stressor overlying the second transistor, wherein a source/drain region displaced on either side of the first strained transistor channel is comprised of a semiconductor having a lattice constant that differs from the lattice constant of silicon and the second stressor is different than the first stressor.