Patent ID: 8659463

Claim:
A method for operating a successive approximation register analog-to-digital converter for converting input signals corresponding to a series of successive bits into digital data, the method comprising: latching first input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the first input signals to a latch; latching second input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the second input signals to the latch after amplifying the second input signals during a first period of amplification by using a preamplifier; and latching third input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the third input signals to the latch after amplifying the third input signals during a second period of amplification by using the preamplifier, wherein the second period of amplification is longer than the first period of amplification.