Patent ID: 8024678

Claim:
An interface to a dynamically configurable arithmetic unit, comprising: a plurality of data alignment modules, each data alignment module of the plurality of data alignment modules receiving a plurality of input variables, wherein the plurality of input variables are associated with one or more arithmetic expressions; a plurality of multiplexers coupled to the plurality of data alignment modules, wherein a data alignment module has a plurality of outputs coupled to a first multiplexer, the first multiplexer having a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit; a second multiplexer comprising a plurality of input instructions and the selection line, each instruction of the plurality of input instructions being associated with one of the arithmetic expressions and having an operation to be performed by the dynamically configurable arithmetic unit, wherein the second multiplexer is configured to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line; and wherein each of the plurality of multiplexers is independently and selectively coupled to a selectable number of registers configured to time align each of the plurality of input variables and the input instructions provided to the dynamically configurable arithmetic unit.