Patent ID: 8923047

Claim:
A semiconductor memory device, comprising: memory strings each of which comprises a drain select transistor, memory cells, and a source select transistor, which are substantially perpendicularly disposed over a substrate; a first bit line coupled to drain select transistors of first group memory strings among the memory strings; a second bit line coupled to drain select transistors of second group memory strings among the memory strings; source lines coupled to source select transistors of the memory strings, respectively; and peripheral circuits configured to turn on source select transistors of non-selected memory strings coupled to source lines to which a precharge voltage is supplied, or turn on drain select transistors of non-selected memory strings coupled to bit lines to which a program inhibition voltage is supplied in order to precharge channel regions of non-selected memory strings before a program voltage is supplied to a memory cell included in a selected memory string among the memory strings, wherein the source select transistors of the memory strings coupled to different bit lines are coupled to a same source line, and wherein the source select transistors of the memory strings coupled to the same bit line are coupled to different source lines.