Patent ID: 7235455

Claim:
A method of manufacturing a semiconductor device comprising the steps of: forming an element isolation insulating film in a first region of a semiconductor substrate; forming a gate insulating film in a second region of the semiconductor substrate; forming a conductive film on the gate insulating film and on the element isolation insulating film; forming a first opening in the conductive film of the first region; patterning the conductive film of the second region to make the conductive film into a gate electrode; forming a source/drain region in the semiconductor substrate beside the gate electrode; forming an interlayer insulating film on each of the gate electrode and the conductive film as well as in the first opening; forming a second opening with a size to encompass the first opening in the interlayer insulating film of the second region; forming a hole in the element isolation insulating film under the first opening; applying resist onto the interlayer insulating film, and in the first and the second openings as well as in the hole: aligning the electron beam exposure apparatus with the semiconductor substrate under the state where the resist is applied, while using the first opening and the hole as an alignment mark, by scanning the mark with a electron beam of the electron beam exposure apparatus through the second opening and measuring an intensity of a reflected electron beam from the mark; exposing the resist existing in a hole formation region of the first region with an electron beam using the electron beam exposure apparatus after carrying out the alignment; developing the resist to make a resist pattern after the exposure; and forming in the interlayer insulating film a hole with a depth reaching the source/drain region by etching the interlayer insulating film by use of the resist pattern as a mask.