Patent ID: 8879185

Claim:
Synchronization circuitry comprising: frequency offset circuitry configured to produce a frequency offset estimate based, at least in part, on a location of a servo synchronization marker; data timing circuitry coupled to the frequency offset circuitry, the data timing circuitry configured to: receive the frequency offset estimate from the frequency offset circuitry; obtain a phase correction value and a frequency correction value; produce a data clock timing control signal based on the frequency offset estimate, the phase correction value, and the frequency correction value; and apply the data clock timing control signal to a phase interpolator to modify a phase of a write clock; and protocol circuitry configured to change a mode of the synchronization circuitry between a bit-patterned media write mode and a continuous media write mode, wherein in the bit-patterned media write mode, data is written to discontinuous bit islands separated by non-magnetic areas.