Patent ID: 7196554

Claim:
An integrated circuit comprising: a clock signal input node for providing a first clock signal; a phase locked loop with an input coupled to the clock signal input node for receiving said first clock signals and for providing a second clock signal; a multiplexer having a first input, a second input, a select input and an output, the first input being coupled to an output of the phase locked loop for receiving said second clock signal, and the second input being coupled to the clock signal input node for receiving said first clock signal, said select input for receiving a control signal for switching the output of said multiplexer between said first clock signal and said second clock signal; and a frequency monitor having an input coupled to the clock signal input node for comparing the frequency of said first clock signal to a selected limiting frequency and a monitor output coupled to said select input of the multiplexer, said monitor output providing said control signal to switch said multiplexer output to said first clock signal if the frequency of said first clock signal is less than said selected limiting frequency and to switch said multiplexer output to said second clock signal if the frequency of said first clock signal is greater than said selected limiting frequency.