Patent ID: 7284113

Claim:
A data converter for converting a group of vectors from a time serial to a time parallel format, wherein in the time serial format, sets of corresponding components of the vectors each have a time slot, and in time parallel format, each vector has a time slot, the converter comprising: an input rotator configured to rotate each set of corresponding components of all time serial vectors by an amount that depends on the time slot of the set of corresponding components, wherein the input rotator is comprised of a plurality of multiplexer stages for rotating each set of corresponding components; a bank of register files coupled to the input rotator to receive a rotated set of corresponding components, and having a register file in the bank configured to store each rotated set of corresponding components; an output rotator coupled to the bank of registers files, for receiving and rotating the components of a vector by an amount that depends on the time slot of the vector in time parallel format to generate the vector in time parallel format, wherein the output rotator is comprised of a plurality of multiplexer stages for rotating the components of each vector; and a controller configured to control addressing of the bank of register files when the corresponding components of each vector are stored in a register of the bank in horizontal and vertical write operations, and to control addressing of the bank to collect the components of each vector for subsequent output rotation in horizontal and vertical read operations, said controller further configured to control alternating horizontal reading and writing and vertical reading and writing operations upon the bank of register files, wherein the controller is comprised of: address lines configured to identify a proper component register of each respective register bank, wherein the address lines are provided by outputs of multiplexers configured to receive inputs from an up counter and a down counter located within the controller; and control bits configured to control operation of the multiplexer stages within the input rotator and the output rotator, wherein the control bits are provided by outputs from the up counter.