Patent ID: 7822884

Claim:
An adaptor circuit comprising: a peripheral port configured to connect to at least one peripheral device; a system port configured to connect to a plurality of further devices; a direct memory access manager configured to autonomously manage data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port; and a bypass circuit, coupled to said system port, said peripheral port and said direct memory access manager, configured to operate in: (i) a bypass mode to connect said system port to said peripheral port such that data transfers managed from outside said adaptor circuit pass between said system port and said peripheral port; and (ii) in a direct memory access mode to connect said system port to said direct memory access manager and to connect said peripheral port to said direct memory access manager such that said direct memory access manager autonomously manages data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port.