Patent ID: 8437388

Claim:
A data latch circuit of a decision feedback equalization (DFE) system, comprising: a parallel p-channel metal-oxide-semiconductor field-effect transistor (PMOS) pair, each of a source of the parallel PMOS pair being coupled to a chipset voltage, and each of a gate of the parallel PMOS pair being coupled to a second clock to pre-charge each of a drain of the parallel PMOS pair to the chipset voltage during a first stage of clocking of the data latch circuit; a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair of a two parallel NMOS pair, each of a source of the first parallel NMOS pair being coupled to a first clock, each of a drain of the first parallel NMOS pair being coupled to the PMOS pair, and each of a gate of the first parallel NMOS pair being coupled to a differential input voltage; a second parallel n-channel metal-oxide semiconductor field-effect transistor (NMOS) pair of the two parallel NMOS pair, each of a source of the second parallel NMOS pair being coupled to the first clock, each of a drain of the second parallel NMOS pair being coupled to at least one of the PMOS pair and the first parallel NMOS pair, and each of a gate of the second parallel NMOS pair being coupled to a differential decision feedback equalization (DFE) voltage through a through a decision feedback digital to analog converter (DAC) of the DFE system external to the data latch circuit; a cross-coupled PMOS pair to generate a positive feedback to at least one of the first parallel NMOS pair, the second parallel NMOS pair and another NMOS pair during a second stage of clocking the data latch circuit; a cross-coupled NMOS pair to escalate the positive feedback during a third stage of the clocking of the data latch circuit, each of a source of the cross-coupled NMOS pair being coupled to a third clock; and a latching circuit to generate a signal data based on the positive feedback, the latching circuit being an S-R latch, and an input of the latching circuit being coupled to at least one of the PMOS pair, the first parallel NMOS pair, the second parallel NMOS pair, the cross-coupled PMOS pair and the cross-coupled NMOS pair, wherein the first clock, the second clock, and the third clock are low during the first stage of clocking the data latch circuit, wherein the first clock and the second clock are high but the third clock is low during the second stage of clocking the data latch circuit, and wherein the first clock is low but the second clock and the third clock are high during the third stage of clocking the data latch circuit.