Patent ID: 8679965

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming a first interlayer dielectric (ID 1 ) in a cell region on a substrate; forming first landing plug contacts (LPC 1 ) through the ID 1 and connected to the substrate; forming first bit lines (BL 1 ) on the ID 1 that extend substantially along a first direction on the ID 1 ; forming a second interlayer dielectric (ID 2 ) to cover the BL 1 ; forming first storage node contacts (SNC 1 ) through the ID 2 and electrically coupled to the LPC 1 wherein the SNC 1 are offset at a first predetermined width (W 1 ) from the LPC 1 in a direction away from the BL 1 ; forming a third interlayer dielectric (ID 3 ) on the ID 2 ; forming second landing plug contacts (LPC 2 ) through the ID 3 and electrically coupled to the SNC 1 ; forming second bit lines (BL 2 ) on the ID 3 that extend substantially along the first direction so that the BL 2 on the ID 3 are substantially in parallel to the BL 1 on the ID 1 and are aligned between the BL 1 ; forming a fourth interlayer dielectric (ID 4 ) to cover the second bit lines; and forming second storage node contacts (SNC 2 ) through the ID 4 and electrically coupled to the LPC 2 wherein the SNC 2 are offset at a second predetermined width (W 2 ) from the LPC 2 in a direction away from the BL 2 .