Patent ID: 7457182

Claim:
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; memory cell array including a plurality of memory cells allocated at the intersecting positions of a plurality of said word lines and a plurality of said bit lines; and a self-timing circuit allocated at the area near said memory cell array to generate the self-timing signal to determine operation timing of an internal circuit when data is read from said memory cell, wherein said self-timing circuit further comprising, dummy word lines selected responding to selection of said word lines, a first dummy memory cell for self-timing connected to said dummy word lines to set the stored data to a first state and a first dummy bit line including dummy memory cell for load set to the non-selected state to set the stored data to a second state opposing to the first state, a second dummy memory cell for self-timing connected to said dummy word lines to set the stored data to a third state and a second dummy bit line including a second dummy memory cell for load set to the non-selected state to set the stored data to a fourth state identical to said third state, and a timing control circuit for inputting said first dummy bit lines and said second dummy bit lines and outputting said self-timing signal with delay only for the period corresponding to a changing rate of potentials of said first and second dummy bit lines.