Patent ID: 8154945

Claim:
A decoding circuit withstanding a high voltage via a low-voltage MOS transistor, the decoding circuit comprising two CMOS inverters connected serially; wherein the decoding circuit further includes four switches, all being provided with one common terminal, two connection terminals and one control terminal; the substrate of a PMOS transistor (MP 1 ) of the first CMOS inverter is connected with the substrate of a PMOS transistor (MP 2 ) of the second CMOS inverter and the common terminal of the second switch (KA 2 ), whose two connection terminals are power source VCC and ground VSS, respectively; the source of the PMOS transistor (MP 1 ) of the first CMOS inverter is connected with the source of the PMOS transistor (MP 2 ) of the second CMOS inverter and the common terminal of the first switch (KA 1 ), whose two connection terminals are floating and power source VCC, respectively; the source and the substrate of an NMOS transistor (MN 1 ) of the first CMOS inverter are connected with the common terminal of the third switch (KA 3 ), whose two connection terminals are connected with a half negative high voltage and the ground, respectively; and the source and the substrate of an NMOS transistor (MN 2 ) of the second CMOS inverter are connected with the common terminal of the fourth switch (KA 4 ), whose two connection terminals are connected with the negative high voltage and the ground, respectively.