Patent ID: 7836195

Claim:
An apparatus comprising: a network adapter to provide packets to a memory coupled to a processor including a first hardware thread and a second hardware thread, the memory including a first descriptor queue associated with the first hardware thread to store packets, a second descriptor queue associated with the second hardware thread to store packets, a first input queue to receive the packets from the first descriptor queue, and a second input queue to receive the packets from the second descriptor queue, the network adapter to insert a marker into the first descriptor queue to cause migration of a first network flow from the first hardware thread to the second hardware thread where the marker flows along with the packets from the first descriptor queue into the first input queue, while preserving packet order of the first network flow, the memory further including a temporary buffer associated with the second hardware thread to store packets of the first network flow from the second input queue after dequeuing of the packets from the second input queue and prior to dequeuing of the marker from the first input queue, and a socket buffer associated with a process running on the first hardware thread to store packets of the first network flow from the first input queue after dequeuing of the packets from the first input queue prior to the marker being dequeued from the first input queue, and wherein the network adapter is to include a hardware thread identifier and a queue identifier in the marker and to store the marker in the first descriptor queue using a direct memory access (DMA) channel.