Patent ID: 8212759

Claim:
A timing controller for an LCD panel, the timing controller receiving transmitted signals including control signals and pixel data and converting the control signals and the pixel data into serial signals that are transmitted to N source drivers, the timing controller comprising: a signal receiver for receiving the transmitted signals; a data reader, coupled to the signal receiver for acquiring data from the signal receiver; a logic control unit, coupled to the data reader for receiving the data acquired by the data reader to generate the pixel data; a data conversion unit, coupled to the logic control unit for receiving the pixel data, converting the pixel data into serial signals, and outputting the serial signals, wherein the data conversion unit comprises: a memory having a first memory segment and a second memory segment; a first multiplexer for receiving the pixel data and transmitting the pixel data to the first memory segment or the second memory segment according to a first selection signal; a buffer having a first buffer section and a second buffer section; a second multiplexer for receiving the pixel data from the memory and selectively transmitting the pixel data to the first buffer section or the second buffer section according to the first selection signal and a second selection signal; a demultiplexer for receiving the pixel data from the buffer and selectively outputting the pixel data in the first buffer section or the second buffer section according to the second selection signal; and a parallel-to-serial converter for receiving the pixel data from the demultiplexer, converting the pixel data into serial signals, and outputting the serial signals; a control line, coupled between the data conversion unit and the N source drivers for transmitting a mode control signal; and N channels, wherein the i th channel is independently coupled between the data conversion unit and the i th source driver, and the i th channel receives the i th serial signal and transmits to the i th source driver when the mode control signal is in a first state, wherein i is an integer between 1 and N, N is an integer greater than 1.