Patent ID: 6943106

Claim:
A method of fabricating an interconnect for a semiconductor component, comprising: providing a semiconductor component, the component having a first side at a first elevational level and an opposing second side at a second elevational level above the first elevational level; forming an opening which extends entirely through the component, the opening accordingly extending from the first side of the component to the opposing second side of the component, the opening having sidewalls; depositing a first material along the sidewalls of the opening, the depositing being conducted at a temperature of less than or equal to about 200° C.; plating a solder-wetting material within the opening and over the first material, the solder-wetting material only partially filling the opening; and forming solder within the opening and along the solder-wetting material, the solder filling the opening and extending from the first elevational level of the first side of the component to the second elevational level of the opposing second side of the component.