Patent ID: 7214561

Claim:
A method of assembling a packaging assembly comprising: preparing a substrate having a plurality of chip-site lands disposed on a first surface of a substrate; disposing a plurality of first solder balls on the chip-site lands; applying an underfill resin around the chip-site lands and the first solder balls; preparing a semiconductor chip having: a plurality of semiconductor elements provided on a surface, a plurality of low dielectric constant films stacked on the surface, each of the low dielectric constant films having an effective dielectric constant of equal to or less than 3.5, and a plurality of metallic interconnections stacked with the low dielectric constant films, with coherence strength of the low dielectric constant films to the semiconductor elements and the metallic interconnections being equal to or less than 15 J/m 2 ; disposing a plurality of second solder balls on corresponding bonding pads disposed on the semiconductor chip; aligning the first solder balls with corresponding second solder balls; connecting the first and second solder balls by melting the first solder balls; and hardening the underfill resin.