Patent ID: 8743107

Claim:
A liquid crystal display device capable of improving charging rate to pixels comprising: a display panel that displays a picture thereon, wherein the display panel includes a plurality of gate lines and a plurality of data lines; a plurality of gate drive ICs that forward scan pulses for driving the gate lines; a plurality of upper data drive ICs that supply pixel voltages to each one side of the data lines and drive the data lines; a plurality of lower data drive ICs that supply the pixel voltages to each the other side of the same data lines being driven by the plurality of the upper data drive ICs and drive the same data lines; a first timing controller that generates and supplies an upper data control signal to the plurality of upper data drive ICs for controlling operation of the plurality of upper data drive ICs; and a second timing controller that generates and supplies a lower data control signal to the plurality of lower data drive ICs for controlling operation of the plurality of lower data drive ICs; wherein there is at least one communication line connected between the first timing controller and the second timing controller, and outputs of the first timing controller and the second timing controller can be synchronized by making communication between the first timing controller and the second timing controller; wherein the first timing controller receives and re-arranges picture data from a system and supplies the same to the upper data drive ICs, matching to timings; wherein the plurality of upper data drive ICs generate the pixel voltages base on the picture data from the first timing controller; wherein the second timing controller receives and re-arranges picture data from a system and supplies the same to the plurality of lower data drive ICs, matching to timings; wherein the plurality of lower data drive ICs generate the pixel voltages base on the picture data from the second timing controller; wherein the first timing controller supplies the picture data starting from the upper data drive IC positioned at one side edge of the display panel to the upper data drive IC positioned at the other side edge of the display panel in succession, and the second timing controller supplies the picture data starting from the lower data drive IC positioned at the other side edge of the display panel to the lower data drive IC positioned at the one side edge of the display panel in succession.