Patent ID: 7667489

Claim:
A voltage regulator, comprising: a driver circuit including a first inverter, a second inverter, a first output transistor, and a second output transistor; the first inverter and the second inverter each being tri-stated during a power-on reset mode; the first inverter and the second inverter each function as buffers during a suspend mode and an awake mode; the first output transistor coupled to a first output node of the driver circuit; the first output node being of the first inverter; the second output transistor coupled to a second output node of the driver circuit, the second output node being of the second inverter; the first inverter and the second inverter powered in association with a first voltage; the first output transistor and the second output transistor powered in association with a second voltage; the first voltage provided using either a first supply or a second supply; neither the first supply nor the second supply being ground; the second voltage provided using the second supply; and the first output transistor and the second output transistor each configured for being substantially conductive during the power-on reset mode.