Patent ID: 7737441

Claim:
A semiconductor device comprising: an n-channel TFT provided over a substrate and in a driver circuit; a p-channel TFT provided over said substrate and in said driver circuit; and a pixel TFT provided over said substrate; said n-channel TFT comprising: a first source region and a first drain region; a first channel region provided between said first source region and said first drain region; a first gate electrode having a first taper portion and provided adjacent to said first channel region with a first gate insulating film therebetween; and a first LDD region provided between said first channel region and at least one of said first source region and said first drain region and overlapping said first gate electrode, said pixel TFT comprising: a semiconductor island comprising a second source region and a second drain region and a plurality of second channel regions each provided between the second source region and the second drain region; a gate insulating film provided on each of said plurality of second channel regions; a plurality of second gate electrodes, each second gate electrode provided on said gate insulating film and over one of said second channel regions; and a gate wiring provided over the second gate electrodes outside the semiconductor island and provided in contact with said gate insulating film of said pixel TFT, wherein each of said second channel regions is interposed between two second LDD regions, wherein each of said plurality of second gate electrodes comprises a first conductive layer and a second conductive layer provided over said first conductive layer, wherein said second conductive layer includes a second taper portion, and said first conductive layer includes a third taper portion, wherein said third taper portion overlaps the corresponding second LDD region, wherein said semiconductor island further comprises an impurity region provided between adjacent two of said second channel regions, and wherein said impurity region has an impurity concentration higher than that of a part of said two second LDD regions, said p-channel TFT comprising: a third source region and a third drain region; a third channel region provided between said third source region and said third drain region; and a third gate electrode having a fourth taper portion and provided adjacent to said third channel region with a third gate insulating film therebetween, said semiconductor device further comprising: a fourth insulating film comprising an organic material provided over said second gate electrodes of said pixel TFT to provide a leveled upper surface over said second gate electrodes of said pixel TFT; and a pixel electrode provided over said fourth insulating film and having a light reflective surface, wherein a taper angle formed in an edge of at least one of said first taper portion and said third taper portion and said fourth taper portion is 5° to 35°.