Patent ID: 8717829

Claim:
A system for detecting a soft error in a memory device during a memory read/write operation, comprising: a latch having a clock input terminal for receiving a first clock signal and a data input terminal for receiving input data corresponding to the memory read/write operation, wherein the latch latches the input data at the beginning of the memory read/write operation in response to a rising edge of the first clock signal and generates a latch output; a master flip-flop having a clock input terminal for receiving a second clock signal and a data input terminal connected to the latch for receiving the latch output, wherein the master flip-flop continuously receives and stores the latch output during the memory read/write operation based on the second clock signal; a slave flip-flop having a clock input terminal for receiving the second clock signal and an input terminal connected to an output of the master flip-flop for receiving the latch output, wherein the slave flip-flop receives and stores the latch output at the end of memory read/write operation based on the second clock signal; and a comparator, having a first input that receives the input data and a second input connected to an output of the slave flip-flop for receiving the latch output therefrom, for comparing the input data and the latch output and thereby detecting a soft error during the memory read/write operation.