Patent ID: 7867849

Claim:
A method of manufacturing a non-volatile memory device, comprising: forming at least one gate structure on an upper face of a substrate, the at least one gate structure including a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate; forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure; forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate; exposing a lower face of the substrate; and curing defects in the tunnel insulation layer pattern by providing an annealing gas to the upper face of the substrate and the lower face of the substrate, wherein the curing of the defects in the tunnel insulation layer pattern is performed by providing the annealing gas directly to the upper face of the substrate and directly to the lower face of the substrate, and wherein exposing the lower face of the substrate includes removing remaining layers on the lower face of the substrate, the remaining layers including a silicon nitride layer formed on the lower face of the substrate while forming the silicon nitride layer on the at least one gate structure on the upper face of the substrate.