Patent ID: 6928020

Claim:
A semiconductor memory device, comprising: a memory cell array comprising memory cells which require refresh; an access circuit which performs refresh of the memory cell array after performing reading of the memory cell array for an access address or writing of the memory cell array for the access address based on a write request and write data presented asynchronously for the access address; an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and a control circuit which starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included in at least one of a chip select signal which controls the selected or non selected state, and the access address, and in which a completion timing has been set after it is determined whether the write request has been presented, taking the time of detection as a reference.