Patent ID: 8054682

Claim:
A non-volatile memory device comprising: a cell array including a plurality of memory cells; a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state; and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop, wherein the page buffer block includes a plurality of page buffers, each of the page buffers comprising: a sensing node connected to a bitline of a selected memory cell; a first latch configured to store data sensed from the selected memory cell through the sensing node; a second latch configured to store data to be programmed to the selected memory cell; an output node for outputting the data of the first latch; and a ground circuit configured to ground the sensing node or the output node with reference to the second latch.