Patent ID: 8432732

Claim:
A memory device, including: a memory array having memory cells formed along a plurality of word-lines; a voltage generation circuit to provide a first voltage level to an output node; decoding circuitry, whereby the first voltage level from the output node can be selectively applied to the word-lines; and a word-line defect detection circuit, including: a capacitive voltage divider, connected between the output node and a low voltage level; a first switch, through which an intermediate node of the capacitive voltage divider is connected to receive a voltage derived from the first voltage level; and a comparator having a first input connected to the intermediate node of the capacitive voltage divider and a second input connected to receive a reference voltage, wherein the memory device performs a process for the detection of defective word-lines, the including: a pre-charge phase, where the decoding circuitry connects the output node to apply the voltage level to a pattern of a first set of the word-lines and the first switch is closed; a subsequent isolation phase, where the output node is left to float and the first switch is open; and a subsequent detection phase, where the first switch is open and the output of the comparator indicates the value of the voltage level on the intermediate node relative to the reference voltage.