Patent ID: 7894171

Claim:
A protection circuit for protecting an NMOS device from an excessive voltage stress, comprising: a cascoding NMOS transistor cascoded between the NMOS device and a first voltage source; and an adjusting circuit, coupled to the first voltage source, a second voltage source, and a gate of the cascoding NMOS transistor, for adjusting the voltage at the gate of the cascoding NMOS transistor according to the voltages of the first voltage source and the second voltage source, so as to protect the NMOS device from the excessive voltage stress caused by the first voltage source, wherein the adjusting circuit includes a voltage divider, coupled between the first voltage source and a third voltage source, and configured so as to provide a divided voltage to the gate of the cascading NMOS transistor when the voltage of the first voltage source is higher than the voltage of the second voltage source, and a first PMOS transistor having a gate coupled to the second voltage source, a source coupled to the first voltage source, and a drain coupled to the voltage divider.