Patent ID: 7233522

Claim:
A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of: biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and then capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell; wherein the biasing step comprises: (a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string; (b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and (c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and then (d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage; wherein the method further comprises: (e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage; (f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line; (g) turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string; and (h) turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.