Patent ID: 8765607

Claim:
A method for making a semiconductor device, comprising: providing a semiconductor substrate of a first conductivity type comprising a plurality of tiles that are spaced apart between active circuit areas; forming one or more isolation regions on the semiconductor substrate between the active circuit areas by performing chemical mechanical polishing on an insulating material using the plurality of tiles to promote planar chemical mechanical polishing of the insulating material between the active circuit areas; forming at a top surface of each of the plurality of tiles a corresponding plurality of well tie structures of the first conductivity type: forming a first metal interconnect structure in contact with a first plurality of well tie structures for electrically connecting a first plurality of tiles to a first predetermined supply voltage to provide latch-up protection; and forming a second metal interconnect structure in contact with a second plurality of well tie structures for electrically connecting a second plurality of tiles to a second predetermined supply voltage to provide latch-up protection, where the first plurality of tiles comprise N+ substrate regions located in close proximity to n-type emitter circuits.