Patent ID: 8510512

Claim:
A data processing system, comprising: at least a first processing node, a second processing node and a third processing node coupled by an interconnect fabric; wherein the first processing node includes: a master and a plurality of snoopers capable of participating in interconnect operations; and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node, such that the plurality of snoopers in the first processing node and the third processing node do not receive the request of the master; and wherein the second processing node includes: a plurality of snoopers capable of participating in interconnect operations; and a node interface having a directory indicating if memory blocks assigned to the second processing node are cached other than in the second processing node, wherein said node interface, responsive to the request, permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.