Patent ID: 8648467

Claim:
A method of manufacturing a semiconductor memory device, comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and a cell array having memory cells, each of the memory cells being connected with the first line and the second line at respective intersections of the first lines and the second lines, the method comprising: forming a first stacked-structure by sequentially stacking a first line layer forming the first line and a memory cell layer forming the memory cell; forming a first stripe part and a first hook part at the first stacked-structure by etching the first stacked-structure into a stripe pattern extending in a first direction, the first stripe part extending in the first direction and being aligned at a certain pitch in a second direction perpendicular to the first direction, and the first hook part protruding from a side of the first stripe part in the second direction; forming a second stacked-structure on the first stacked-structure by sequentially stacking a second line layer forming the second line and the memory cell layer; forming a second stripe part and a second hook part at the second stacked-structure by etching the second stacked-structure into a stripe pattern extending in the second direction, the second stripe part extending in the second direction and being aligned at a certain pitch in the first direction, and the second hook part protruding from a side of the second stripe part in the first direction; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting a side of the first hook part or a side of the second hook part and extending in a stacking direction perpendicular to the first direction and the second direction, when there is the second stacked-structure under the first stacked-structure in etching the first stacked-structure, the second stacked-structure being etched into a stripe pattern extending in the first direction to form the memory cell into a matrix pattern in the second stacked-structure, when there is the first stacked-structure under the second stacked-structure in etching the second stacked-structure, the first stacked-structure being etched into a stripe pattern extending in the second direction to form the memory cell into a matrix pattern in the first stacked-structure, in etching the first stacked-structure, the etching being conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer, and in etching the second stacked-structure, the etching being conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.