Patent ID: 7968405

Claim:
A method of manufacturing a semiconductor device, comprising: forming an isolation layer in a semiconductor substrate defining an active region; forming a molding pattern on the isolation layer; forming a first conductive layer on a sidewall and a top surface of the molding pattern and the semiconductor substrate; selectively removing the first conductive layer on the top surface of the molding pattern forming a conductive pattern, the conductive pattern including a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern; removing the molding pattern; and forming an inter-gate dielectric layer on the isolation layer and the conductive pattern, wherein forming the conductive pattern comprises: forming a sacrificial layer on the first conductive layer; planarizing the sacrificial layer and the first conductive layer exposing the top surface of the molding pattern; and removing the planarized sacrificial layer.