Patent ID: 8265917

Claim:
A high-level integrated circuit (“IC”) modeling system comprising: a first co-simulator modeling a first portion of an IC system at a first free running clock speed; wherein the first co-simulator executes on a host computer; a second co-simulator modeling a second portion of the IC system according to a second free running clock speed; wherein the second co-simulator emulates the second portion of the IC system on a programmable integrated circuit (IC); a shared first-in-first-out (“FIFO”) buffer, a first portion of the shared FIFO buffer being configured in the programmable IC and a second portion of the shared FIFO buffer being configured in the host computer; a co-simulation synchronization interface configured to automatically change at least one of the first free running clock speed and the second free running clock speed to a single-step mode in response to a user-selected trigger condition; wherein the co-simulation synchronization interface includes an interface for user specification of names of one or more signals of the IC system, of the trigger condition based on the names of the one or more signals and one or more logical operators, and of a duration that is a selected number of clock cycles and associated with the trigger condition; and wherein the co-simulation synchronization interface is further configured to return at least one of the first co-simulator or the second co-simulator from the single-step mode to the first free running clock speed or to the second free running clock speed, respectively, in response to operating in the single-step mode for the selected number of clock cycles.