Patent ID: 8423682

Claim:
A processor, comprising: a micro-code sequencer; a macro-code instruction interceptor to detect an input/output access operation associated with an input/output address space and a first configuration memory address of a first bit size, wherein such a detection indicates that an input/output access to a memory-mapped register in a core hardware element is to be executed, then responsively combine the first configuration memory address and configuration data associated with the input/output access operation to generate a data packet, wherein the first configuration memory address and the configuration data are included in a peripheral component interconnect (PCI) configuration space and the configuration memory address is at 0xCF8; and an integrated device to be accessed at a second memory address indicated contents of the data packet wherein the second memory address is of a second bit size that is larger than the first bit size and indicates the memory-mapped register, wherein the macro-code instruction interceptor forms a portion of the micro-code sequencer, and wherein the micro-code sequencer is to access a scratch pad memory that records the first configuration memory address.