Patent ID: 8397130

Claim:
A memory device comprising: a memory circuit, comprising: one or more wordlines, a decoder operable to receive a wordline encoded address that corresponds to a target wordline of the one or more wordlines absent a soft error in the wordline encoded address, the decoder being configured to decode the wordline encoded address so as to actuate an actuated wordline that corresponds to the wordline encoded address, wherein the actuated wordline matches the target wordline absent the soft error in the wordline encoded address and is mismatched with the target wordline when there is the soft error in the wordline decoded address; an encoder coupled to the one or wordlines and configured to: detect the actuated wordline; and encode a first re-encoded address corresponding to the actuated wordline; soft error detection circuitry coupled to the memory circuit and configured to detect the soft error in the wordline encoded address whenever the first re-encoded address corresponds to the actuated wordline that is mismatched with the target wordline; and soft error handling circuitry coupled to the memory circuit and configured to handle the soft error when detected.