Patent ID: 8026044

Claim:
A method of forming fine patterns of a semiconductor device, the method comprising: forming a first pattern on a semiconductor substrate, the first pattern comprising a plurality of first line patterns having a feature size F and an arbitrary pitch P, the plurality of first line patterns being repeated in a first direction; forming a second pattern comprising a plurality of second line patterns formed between adjacent first line patterns of the plurality of first line patterns to form a fine pattern having a half pitch P/2, the plurality of second line patterns being repeated in the first direction; forming a gap in at least one first line pattern of the plurality of first line patterns in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the at least one first line pattern through the gap; and forming at least one jog pattern, extending in the first direction from at least one first line pattern adjacent to the connected second line patterns, the at least one jog pattern causing a gap in at least one of the connected second line patterns in the second direction.