Patent ID: 6887798

Claim:
A method for modifying stress formation in a semiconductor structure comprising the steps of: providing a structure having a patterned material stack located on top of a surface of a semiconductor substrate, said patterned material stack having at least one opening that exposes a portion of the semiconductor substrate; forming at least one trench into the exposed portion of the semiconductor substrate, each trench having sidewalls that extend to a common bottom wall; filling said at least one trench with a trench dielectric; forming a blockmask over a first region of said substrate leaving a second region of said substrate exposed; removing said patterned material stack from said second region of said substrate; and subjecting at least one of the sidewalls and a portion of the common bottom wall of each trench in said second region of said substrate to a plasma nitridation process, wherein said first region of said substrate is subsequently processed to provide pFET devices.