Patent ID: 7691672

Claim:
A method of manufacturing a semiconductor apparatus, comprising the steps of: fabricating a plurality of first semiconductor chips, with each provided over a surface thereof a bump for external connection; joining said plurality of first semiconductor chips to a dummy support substrate through said bumps, said bumps defining an interface between the first semiconductor chips and the dummy support substrate; filling the spaces between said plurality of first semiconductor chips with an insulating material so as to form a pseudo-wafer over said dummy support substrate; polishing a surface of said pseudo-wafer opposite the dummy support substrate so as to reduce the thickness of the pseudo-wafer and each said first semiconductor chip; forming an external connection terminal on the back side of each said first semiconductor chip electrically connected to each said respective bump formed on the opposite side of each said first semiconductor chip; mounting second semiconductor chips over said external connection terminals; removing said dummy support substrate by polishing so as to at least partially expose said bumps; and dicing said pseudo-wafer on a chip by chip basis.