Patent ID: 8773895

Claim:
A memory cell comprising: a latch having a supply node, a ground node, a storage node Q, and a storage node QB; a gating device having a control node and further connected to a voltage supply and to the supply node of the latch; and a feedback loop directly connecting the storage node QB with the control node of the gating device, wherein the ground node of the latch is connected to ground and wherein the storage node Q and the storage node QB are each connected to a separate write circuitry, wherein responsive to a writing of a logic “0” or a logic “1” into the memory cell, the feedback loop and the gating device are configured to cut off the voltage supply to the latch when the storage nodes reach steady state in which only one of the storage nodes stores a valid value while maintaining readability, and wherein leakage currents through the latch are reduced in the steady state.