Patent ID: 8352895

Claim:
A computer-implemented method comprising: determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included; setting each of the pull-down, pass-gate, and pull-up devices at process corner G; performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters; generating a normal probability distribution for I read based on the local Monte Carlo simulations around process corner G; extrapolating the worst case I read value from the normal probability distribution of I read to define a process corner SRM representing a slowest SRAM bit on a chip; repeating the steps of determining a process corner G, setting individual devices at process corner G, performing Monte Carlo simulations, generating a normal probability distribution, and extrapolating the worst case I read value for multiple SRAM cells; creating a library of SRM corner values for multiple SRAM cells; and validating an SRAM cell based on a selected SRM corner from the library.