Patent ID: 8504780

Claim:
A computer, comprising: a first processor for executing a first OS; a first I/O device capable of inputting and outputting data to and from a first apparatus based on control of the first processor which executes the first OS; a second processor for executing a second OS; a second I/O device capable of inputting and outputting data to and from a second apparatus based on control of the second processor which executes the second OS; a shared memory which is accessible by the first and second processors; and an interrupt controller for controlling the sending of an I/O complete interrupt to the first processor or the second processor, wherein the first processor issues a control command for causing the first I/O device to read, from the first apparatus, target data to be sent to the second apparatus and store the target data in the shared memory, based on the control command, the first I/O device reads the target data from the first apparatus and thereafter transfers the target data to the shared memory, and then generates an I/O complete interrupt, the interrupt controller delivers the I/O complete interrupt generated by the first I/O device to the second processor, when the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus, based on the control command the second I/O device reads the target data from the shared memory and sends the target data to the second apparatus, the interrupt controller can be set with a delivery destination of the I/O complete interrupt, the first processor implements the setting in the interrupt controller so that the I/O complete interrupt generated by the first I/O device is delivered to the second processor, the second I/O device generates an I/O complete interrupt after sending the target data to the second apparatus, the interrupt controller delivers the I/O complete interrupt generated by the second I/O device to the first processor, when the first processor receives the I/O complete interrupt generated by the second I/O device from the interrupt controller, the first processor releases a storage area of the shared memory storing the target data, the second I/O device sends the target data to the second apparatus in units of packets of a predetermined size, and generates the I/O complete interrupt after completing the sending of the final packet of the target data, the first I/O device is an HBA (Host Bus Adapter), and transfers the target data to the shared memory based on DMA (Direct Memory Access), the second I/O device is an NIC (Network Interface Card), and reads the target data from the shared memory based on DMA, the first apparatus is a storage apparatus for storing data, and the second apparatus is a computer coupled to a network.