Patent ID: 8595449

Claim:
An integrated circuit, comprising: a resistive memory comprising an array of resistive memory cells; a memory controller configured to control operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and the memory controller and configured to schedule internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command, the internal maintenance operations comprising accessing at least a subset of the resistive memory cells in the array, wherein operation of the memory scheduler and the internal maintenance operations are transparent to the external device, and wherein, for each resistive memory cell accessed, the internal maintenance operations comprise: performing a first read operation by comparing a storage level of the resistive memory cell with a first sense amplifier level; in response to the first read operation indicating a first logical state, selecting a second sense amplifier level from a plurality of amplifier levels according to the first logical state, wherein the second sense amplifier level is different than the first sense amplifier level; performing a second read operation by comparing the storage level of the resistive memory cell with the second sense amplifier level; and performing a write operation to restore a storage level representing the first logical state in the resistive memory cell in response to the second read operation failing to indicate the first logical state.