Patent ID: 7831801

Claim:
An integrated circuit, comprising: a plurality of processing units; a first direct memory access block, the first direct memory access block including a first dual-ported random access memory and a first decoder; a first processing unit and a second processing unit of the plurality of processing units being topologically coupled via the first direct memory access block for providing a multiple processor array; a first memory controller of the first processing unit being directly bused to one port of the first dual-ported random access memory and to a first processor of the first processing unit; a first memory cache of the first processing unit coupled to the first memory controller; a second memory controller of the second processing unit separate from the first memory controller, the second memory controller being directly bused to another port of the first dual-ported random access memory and to a second processor of the second processing unit; a second memory cache of the second processing unit coupled to the second memory controller; and the multiple processor array configured to use the first dual-ported random access memory for first direct buffer level access to a first shared addressable memory space of the first dual-ported random access memory as shareable between the first processing unit and the second processing unit in response to signals from the first memory controller and the second memory controller, each of the first memory controller and the second memory controller accessing the first shared addressable memory space to enable implementing a predetermined activity.