Patent ID: 7675138

Claim:
A semiconductor device comprising: a first parallel plate capacitor formed on a substrate and connected to a first differential node, the first parallel plate capacitor including a first layer and a second layer, the first layer of the first parallel plate capacitor being electrically connected to the first differential node; a second parallel plate capacitor formed on the substrate and connected to a second differential node, the second parallel plate capacitor including a first layer and a second layer, the first layer of the second parallel plate capacitor being electrically connected to the second differential node; and a first interdigitated capacitor connected between and electrically connected to the first differential node and the second differential node and formed at least partially above the first parallel plate capacitor, the first interdigitated capacitor including a first layer and a second layer, the first layer of the first interdigitated capacitor being electrically connected to the first differential node and to the first layer of the first parallel plate capacitor, and the second layer of the first interdigitated capacitor being electrically connected to the second differential node and to the first layer of the second parallel plate capacitor; wherein the first layer of the first parallel plate capacitor, the second layer of the first parallel plate capacitor, the first layer of the first interdigitated capacitor, and the second layer of the first interdigitated capacitor each comprise a separate layer.