Patent ID: 7883937

Claim:
A method of forming an electronic package having a substrate with contacts thereon, said method comprising: placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with said substrate so that one of said plurality of solder bumps is in superimposition with respect to one of said contacts and one of said plurality of bonding pads, with a volume being defined between a region of said substrate in superimposition with said integrated circuit; filling a portion of said volume outside of said solder bumps with a quantity of underfill; and forming, on said substrate, a fluid flow barrier consisting of a plurality of baffles each extending above said substrate from solder mask material deposited upon said substrate around said volume, defining a flow restricted region, with said fluid flow barrier having dimensions sufficient to prevent said quantity of underfill from flowing outside of said flow restricted region, wherein forming further includes forming said fluid flow barrier with a hiatus separating adjacent baffles of sufficient dimensions to prevent said quantity from flowing outside of said flow restricted region through capillary action of said fluid flow barrier with underfill.