Patent ID: 7649232

Claim:
A p-channel MOS transistor, comprising: a silicon substrate including a channel region therein; a gate electrode formed on said silicon substrate in correspondence to said channel region via a gate insulation film; a source extension region of p-type and a drain extension region of p-type formed in said silicon substrate at respective sides of said channel region; a source region of p-type and a drain region of p-type formed in said silicon substrate at respective lateral sides of said gate electrode at respective outer sides of sidewall insulation films formed on respective sidewall surfaces of said gate electrode in a partially overlapping relationship with said source extension region of p-type and said drain extension region of p-type respectively; a pair of trenches formed respectively in said source region of p-type and said drain region of p-type; silicide films covering a bottom surface and a side surface of said pair of trenches, respectively; a metal film or a conductive metal nitride film formed in each of said pair of trenches over a corresponding one of said silicide films, said metal film functioning as a compressive stress source, wherein a bottom surface of said metal film or said conductive metal nitride film is located at a level lower than an interface between said channel region and said gate insulation film.