Patent ID: 7376152

Claim:
An apparatus comprising: a first circuit configured to generate a data output signal in response to (i) a data input signal comprising a series of words, (ii) a valid word signal, and (iii) a select signal; and a second circuit configured to generate said select signal in response to (i) said valid word signal, (ii) a start of frame signal, (iii) an end of frame signal and (iv) said data output signal, wherein (a) said select signal adjusts a starting point of each of said words to match a starting point of said first word and (b) said second circuit comprises (i) a decoder configured to present a length signal in response to said data output signal, (ii) a subtractor configured to present a sum signal in response to said length signal and a first enable signal and (iii) an adder circuit configured to generate said select signal in response to said sum signal.