Patent ID: 8391305

Claim:
An apparatus comprising: one or more processors; a plurality of qualifier matrixes, wherein each of the plurality of qualifier matrixes is configured to determine qualified sources in a subset of supported sources that are associated by assignment constraints to a set of sinks by determining that a source is a qualified source when at least one sink in the set of sinks is available and is qualified to receive work from the source, and wherein the plurality of qualifier matrixes are configured to operate in parallel, and wherein each of the plurality of qualifier matrixes provides a source qualified signal for each determined qualified source; and a hierarchical source scheduler coupled to the plurality of qualifier matrixes and configured to receive the source qualified signal from each of the plurality of qualifier matrixes and to select a single selected source from among all determined qualified sources, wherein the hierarchical source scheduler comprises: a plurality of first level source scheduler modules, each configured to select simultaneously an intermediate selected source from a subset of a plurality of sources; and a second level source scheduler module coupled to the plurality of first level source scheduler modules and configured to receive intermediate selected sources from the first level source scheduler modules and to select the single selected source from the intermediate selected sources.