Patent ID: 8901648

Claim:
A metal oxide semiconductor (MOS) device having a plurality of MOS transistor cells formed in an array, wherein the plurality of MOS transistor cells comprises (i) a first MOS transistor cell and (ii) a second MOS transistor cell, and wherein the first MOS transistor cell comprises: a drain region; a gate region surrounding the drain region and formed in a loop around the drain region; a first plurality of source regions arranged around the gate region, wherein each source region of the first plurality of source regions is situated across from a corresponding side of the drain region, wherein a first source region of the first plurality of source regions is not adjacent to any other source regions of the first plurality of source regions such that the first source region of the first plurality of source regions is separated from the other source regions of the first plurality of source regions by one or more interposing regions, and wherein a second source region of the first plurality of source regions is adjacent to a third source region of the first plurality of source regions such that no interposing region lies between (i) at least a part of the second source region and (ii) at least a part of the third source region, wherein the second source region forms a common source region for each of (i) the first MOS transistor cell and (ii) the second MOS transistor cell, wherein the second MOS transistor cell comprises a second plurality of source regions, and wherein the first source region is adjacent to a fourth source region of the second plurality of source regions of the second MOS transistor cell such that no interposing region lies between (i) at least a part of the first source region and (ii) at least a part of the fourth source region.