Patent ID: 7292119

Claim:
A phase locked loop frequency synthesizer, comprising: an LC-tank circuit which includes an inductor and a variable capacitor in which a capacitance changes depending on an input voltage; a group of fixed-value capacitors which are selectively connected to said LC-tank circuit in parallel; a voltage controlled oscillating unit which outputs a signal with a frequency determined by said LC-tank circuit and said group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of said frequency output from said voltage controlled oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines a combination of said fixed-value capacitors to be connected to said LC-tank circuit based on a frequency dividing ratio setting signal including information about a dividing ratio of said second signal, and controls the connection of said fixed-value capacitors selected from said group of fixed-value capacitors based on said selection signal; and a variable capacitor controlling unit which selects either one of a fixed bias voltage and a voltage obtained by converting said output current output from said phase control unit and inputs the selected voltage to said variable capacitor of said LC-tank circuit, wherein said fixed-value capacitor controlling unit includes: a first counter which counts said first signal; a second counter which counts a count number of said second signal while said first counter counts predetermined numbers of said first signal; a calculation unit that calculates an ideal value for said count number of said second signal while said predetermined numbers of said first signal is counted; and a comparator which compares said count number counted by said second counter and said ideal value and outputs a differential operator thereof, said fixed-value capacitor controlling unit correcting said selection signal based on said differential operator.