Patent ID: 7130958

Claim:
A serial flash-memory chip comprising: a flash-memory array of electrically-erasable programmable read-only memory (EEPROM) cells; row and column decoders for selecting EEPROM cells in the flash-memory array for reading, writing, or erasing in response to a flash address; a serial-bus interface to a serial bus connected to pins of the serial flash-memory chip, for transmitting and receiving serial data over the serial bus; a serial engine, coupled to the serial-bus interface, for converting serial data from the serial bus to parallel data; an internal controller, coupled to the serial engine, for responding to flash commands sent over the serial bus in request packets, and for generating completion packets that are sent over the serial bus in response to the flash commands; and data buffers, coupled between the flash-memory array and the internal controller, for buffering data read from the EEPROM cells in response to the internal controller decoding a read flash command in a read-request packet, the data being loaded into a data payload of a completion packet; wherein the internal controller programs data into the EEPROM cells through the data buffers in response to a program flash command in a write-request packet received over the serial bus, whereby the serial flash-memory chip has a serial-packet interface for commands, address, and data.