Patent ID: 7761608

Claim:
A host bus adapter (HBA) operationally coupled to a host computing system for sending and receiving information to and from a network device, the HBA comprising: a TCP/IP offload engine (TOE) device having a detection/location logic for concurrently processing markers, data integrity fields (“DIFs”) and digests using a marker locator bit, a DIF locator bit and a digest locator bit in a control path that is used to control data flow in a data path; wherein the detection/location logic includes (i) a DIF counter whose value is used for setting the DIF locator bit in a data stream for processing DIFs in an append mode where a DIF is inserted in the data stream, for processing DIFs in a validate and remove mode where the DIF is validated and removed from the data stream, and for processing DIFs in a validate and keep mode where the DIF is validated and kept in the data stream; (ii) a digest counter whose value is used for setting the digest locator bit such that digests are processed by a digest verification and generation logic when the data stream reaches the digest verification and generation logic and (iii) a marker counter whose value is used for setting the marker locator bit such that a marker can be identified and removed from the data stream by a marker removal logic when the data stream reaches the marker removal logic.