Patent ID: 7238993

Claim:
A pixel circuit, comprising: a P − silicon substrate; an N − well formed in said P − silicon substrate, wherein said N − well in said P − substrate forms a PN junction which can accumulate signal-generated charge; a first P + region and a second P + region formed in said N − well; a PMOS transistor having a source, a drain, a channel, and a gate formed in said N − well, wherein said first P + region forms said source, said second P + region forms said drain, and that part of said N − well between said first P + region and said second P + region forms said channel of said PMOS transistor; and a gate oxide formed over said channel of said PMOS transistor; an electrode formed on said gate oxide over said channel of said PMOS transistor, wherein said electrode forms said gate of said PMOS transistor; a first NMOS transistor having a drain connected to an output node, a gate, and a source connected to said source of said PMOS transistor; an N + region formed in said N − well; and a second NMOS transistor having a source connected to said N + region formed in said N − well, a drain connected to said gate of said first NMOS transistor, and a gate connected to said source of said first NMOS transistor.