Patent ID: 8067290

Claim:
A method for forming a bipolar transistor within a semiconductor body having a reduced base-collector capacitance, comprising: forming a collector region comprising an active collector region and having a first conductivity type; forming a base-collector dielectric film above the collector region; forming one or more base connection regions overlying the base-collector dielectric film, the one or more base connection regions having an opposite conductivity type as the collector region; selectively etching the base-collector dielectric film to form an undercut area below an edge of respective base connection regions; forming one or more selective base connection regions in the undercut area, the one or more selective base connection regions having a thickness less than the undercut area; selectively isotropically etching the base-collector dielectric film to form a large cavity configured between the one or more base connection regions and the collector region; selectively forming an active base region in the large cavity electrically coupling the one or more base connection regions and the collector region, wherein selectively forming the active base region separates the large cavity into one or more gas filled isolation cavities configured between the one or more base connection regions and the collector region; and forming an appropriately patterned emitter region, having the same conductivity type as the collector region, overlying the active base region.