Patent ID: 7960986

Claim:
An assembly for providing concurrent electrical access to one or more integrated circuits on a wafer, comprising: an edge-extended wafer translator having a central portion, and an edge-extended portion vertically offset from the central portion; a mounting fixture upon which the vertically offset edge-extended portion is disposed; a first probe structure operable to contact a first plurality of inquiry-side contact terminals; and a second probe structure operable to contact a second plurality of inquiry-side contact terminals: wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer; wherein the first plurality of wafer-side contact terminals are electrically connected to the first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to the second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator; and wherein, during operation, the first probe structure is laterally movable relative to the mounting fixture and the second probe structure is fixed relative to the mounting fixture.