Patent ID: 8680615

Claim:
A transistor, comprising: a semiconductor substrate including a surface layer extending from an upper surface of the semiconductor substrate to a surface depth; a gate dielectric overlying a channel region of the surface layer; a gate electrode overlying the gate dielectric, the gate electrode including a first sidewall and a second sidewall; a source region comprising a portion of the surface region extending between the channel region and a source contact region; a drift region comprising a portion of the surface region extending between the channel region and a drain region; a shield interlevel dielectric (ILD) overlying at least a portion of an upper surface of the gate electrode, the second sidewall, and a portion of the drift region; a shield plate comprising an electrically conductive layer overlying at least a portion of the shield ILD, the shield plate defining a shield plate edge overlying the drift region, wherein the shield plate edge comprises a customized shield plate edge wherein a displacement between the customized shield plate edge and the second sidewall varies along a length of the second sidewall.