Patent ID: 8839021

Claim:
A memory device comprising: a non-volatile semiconductor memory; a non-volatile memory side signal pattern storage configured to prestore a pattern of a first tuning signal and a pattern of a second tuning signal, the pattern of the first tuning signal and the pattern of the second tuning signal being sent to a host device to which the memory device is connected through signal lines; and a memory controller configured to perform control for sending and receiving signals to and from the host device to which the memory device is connected through signal lines, the memory controller performing control to receive command signals through a command line, send response signals through the command line, and send and receive data signals through data lines in synchronization with a clock signal received through a clock line, and to perform control to send the first tuning signal through one signal line and send the second tuning signal through another signal line so that a time period during which the first tuning signal is sent and a time period during which the second tuning signal is sent overlap each other.