Patent ID: 7454674

Claim:
A jitter detector comprising: a delay chain configured to receive an input and to generate a plurality of outputs responsive to the input, each output delayed from the input by a different delay time; a first plurality of clocked storage devices, wherein each of the first plurality of clocked storage devices is coupled to receive a respective output of the plurality of outputs as an input and further coupled to receive a first clock input; a logic circuit coupled to receive outputs of the first plurality of clocked storage devices and configured to identify a first clocked storage device of the plurality of clocked storage devices that captures the respective output in error, wherein the first clocked storage device captures the least delayed output of the plurality of outputs that are captured in error; circuitry configured to generate the input to the delay chain, and wherein the circuitry is further configured to generate a check signal to the logic circuit to check outputs of the first plurality of clocked storage devices to detect error, and wherein the logic circuit is configured to detect that the respective output is in error with respect to an expected value indicated by the check signal; and a second plurality of clocked storage devices coupled to the logic circuit and to receive a second clock input, wherein each of the second plurality of clocked storage devices corresponds to a respective one of the first plurality of clocked storage devices, and wherein the second plurality of clock storage devices are configured to accumulate an indication of which of the first plurality of clocked storage devices has captured the respective output in error, wherein the indication is accumulated over a plurality of clock cycles of the first clock input and the second clock input.