Patent ID: 7263477

Claim:
A computer-implemented method for modeling devices having different geometries in an integrated circuit using a device model, comprising: dividing a geometrical space including the different geometries into a first set of subregions and a second set of subregions, the first or the second set of subregions including one or more subregions, wherein each of the second set of subregions includes at least some portion that is not included in the first set of subregions; extracting a set of model parameters for each of the first set of subregions using model equations associated with the device model and measurement data obtained from a plurality of test devices; determining binning parameters for each of the second set of subregions using one or more model parameters associated with one or more subregions in the first set of subregions; and saving at least some of the model parameters or the binning parameters in one or more files.