Patent ID: 8826057

Claim:
A multiple time domain synchronizer, comprising: first and second registers electrically connected in series, said first register configured to latch a first signal in-sync with a first clock associated with a first time domain and said second register configured to latch a second signal generated by an output of said first register in-sync with a second clock that is phase-delayed relative to the first clock; a latency selection circuit having a first input configured to receive a register output signal derived from said first register and a second input configured to receive a register output signal from said second register, said latency selection circuit configured to selectively pass one of the register output signals at the first and second inputs to an output thereof in response to a latency control signal; and a synchronization circuit electrically coupled to an output of said latency selection circuit and comprising first and second unequal timing paths therein, said synchronization circuit responsive to a third clock that synchronizes capture of a register output signal selected by said latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured register output signal as active.