Patent ID: 7600082

Claim:
A virtualization logic embodied on a computer-readable medium and configured to be operably connected to a processor configured without internal virtualization logic, comprising: a first data store configured to store a trappable memory address associated with a virtual device; an address comparison logic configured to receive a memory transaction from the processor and to selectively produce a trap when the memory transaction references the trappable memory address; where the address comparison logic being configured to provide a posted response to the processor in response to receiving a memory write transaction from the processor; and the address comparison logic being configured to provide a read defer response to the processor in response to receiving a memory read transaction from the processor; a second data store configured to store data associated with a memory read transaction for which the address comparison logic produced a trap; a third data store configured to store data associated with a memory write transaction for which the address comparison logic produced a trap; and a transaction logic configured to selectively provide a signal to the processor in response to the address comparison logic producing the trap where the signal causes the processor to invoke executable code for interacting with the virtual device.