Patent ID: 7102690

Claim:
A clock signal synthesizer with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data, said converter providing a first reference clock signal with a frequency F 1 , said clock signal synthesizer comprising: a phase-locked loop (PLL) oscillator generating a clock signal with a frequency F 1 ×N in response to said first reference clock signal received by an input end thereof, and outputting said clock signal with said frequency F 1 ×N from an output end thereof; a divider feedback circuit electrically connected to said input end of said PLL oscillator for receiving and proceeding a divided-by-N operation on said clock signal with said frequency F 1 ×N, and feeding a feedback clock signal with a frequency F 1 back to said PLL oscillator; a first divider output circuit electrically connected to said PLL oscillator for receiving and proceeding a divided-by-P 1 operation on said clock signal with said frequency F 1 ×N, and outputting a first output clock signal with a frequency F 1 ×N/P 1 ; and a second divider output circuit electrically connected to said PLL oscillator for receiving and proceeding a divided-by-P 2 operation on said clock signal with said frequency F 1 ×N, and outputting a second output clock signal with a frequency F 1 ×N/P 2 , wherein a value P 2 /P 1 correlates to a ratio of the pixel number of a horizontal scan line in said non-interlacing scan data to the pixel number of a horizontal scan line in said interlacing scan data.