Patent ID: 7443708

Claim:
An array of FeRAM memory cells, comprising: a plurality of columns arranged along a bit line direction and a plurality of rows arranged along a word line direction; a plurality of plate lines arranged along a word line direction; a common plate line driver connected to, and configured to drive the plurality of plate lines, thereby globally interconnecting the plate lines in the array; first and second FeRAM memory cells arranged in the bit line direction in a first column, the first and second FeRAM memory cells operably associated with different plate lines; and third and fourth FeRAM memory cells arranged in the bit line direction in a second column, the third and fourth FeRAM memory cells operably associated with different plate lines, wherein a plate line of the first FeRAM memory cell is locally interconnected to a plate line of the second FeRAM memory cell by a first local plate line interconnection, and a plate line of the third FeRAM memory cell is locally interconnected to a plate line of the fourth FeRAM memory cell by a second local plate line interconnection, thereby providing an FeRAM memory array having a reduced plate line resistance.