Patent ID: 7707472

Claim:
A method for testing a plurality of on-chip memory blocks on an integrated circuit, the method comprising: configuring a plurality of data selection circuits with a control signal, wherein a first state of the control signal configures the plurality of data selection circuits for transferring built-in self test (BIST) data and address values from a single BIST controller serially to input scan chain segments associated with a plurality of on-chip memory blocks; wherein a second state of the control signal configures the plurality of data selection circuits for transferring the BIST data and the address values from the single BIST controller in parallel to the input scan chain segments associated with the plurality of on-chip memory blocks; loading the BIST data from the input scan chain segments into memory cells in the plurality of on-chip memory blocks; reading output BIST data from the memory cells; loading the output BIST data read from the memory cells into output scan chain segments associated with the plurality of on-chip memory blocks; transferring the output BIST data from the output scan chain segments to comparators; performing OR logic functions on the output signals of the comparators and output signals of registers using logic gates; and transferring output signals of the logic gates to inputs of the registers.