Patent ID: 8659059

Claim:
A semiconductor device comprising: a transistor structure including: a channel region formed in a monocrystalline semiconductor substrate; a source region formed at least partially in the monocrystalline semiconductor substrate adjacent the channel region; a drain region formed at least partially in the monocrystalline semiconductor substrate adjacent the channel region; a gate dielectric layer formed on the channel region; and a gate electrode formed on the gate dielectric layer, the gate electrode having a conductive portion over the channel region having inwardly sloping sidewalls such that the conductive portion of the gate electrode has a bottom cross-section length that is greater than an upper portion cross-section length; a contact plug contacting the gate electrode at a gate contact region of the gate electrode having inwardly sloping sidewalls, wherein at least part of the contact plug is on the inwardly sloping sidewalls at the gate contact region of the gate electrode; and a strain inducing layer formed over the transistor structure.