Patent ID: 6979613

Claim:
A method for fabricating a trench capacitor of DRAM devices, comprising: providing a semiconductor substrate having a pad oxide layer and a pad nitride layer formed thereon; etching a deep trench into the pad nitride layer, the pad oxide layer and the semiconductor substrate; doping the deep trench to form a buried doped plate in the semiconductor substrate adjacent to a lower portion of the deep trench, the buried doped plate serving as a first electrode of the trench capacitor; forming a node dielectric layer on interior surface of the deep trench; depositing a first conductive layer on the node dielectric layer inside the deep trench; recessing the first conductive layer to a first depth in the deep trench, the first conductive layer serving as a second electrode of the trench capacitor; depositing a spacer silicon layer on the node dielectric layer on sidewall of the deep trench; locally ion doping an upper portion of the spacer silicon layer; selectively removing the non-doped spacer silicon layer to expose the node dielectric layer; removing the exposed node dielectric layer to expose a silicon surface inside the deep trench, and simultaneously forming a dielectric spacer protecting the pad oxide layer; and simultaneously oxidizing the exposed silicon surface inside the deep trench and the doped spacer silicon layer, thereby forming a thermal silicon oxide layer and an oxide spacer, respectively.