Patent ID: 7617408

Claim:
A system for providing accurate time generation in a computing device, the system comprising: the computing device including a computing device clock and a first microprocessor operatively coupled to the computing device clock; and a master clock device operatively coupled to the computing device via a communications link, the master clock device including a master clock and a second microprocessor operatively coupled to the master clock, the master clock configured to provide a master clock output, wherein the first microprocessor is configured to synchronize a time of the computing device clock to the master clock output to provide the accurate time generation in the computing device using a latency adjusted time derived from a total system latency of the system; wherein the first microprocessor is further configured to: determine the total system latency based on a delay incurred between issuance of a first command by the first microprocessor and receipt of a first time-data signal by the first microprocessor, the first time-data signal representative of the master clock output at a first time and caused to be transmitted by the second microprocessor in response to receipt of the first command; and derive an accurate time from a second time-data signal, the second time-data signal representative of the master clock output at a second time and caused to be transmitted by the second microprocessor at a time instant known by the first microprocessor in response to receipt of a second command caused to be transmitted by the first microprocessor.