Patent ID: 8351563

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: an input unit, electrically connected to an (N−1)th shift register stage of the shift register stages for receiving an (N−1)th start pulse signal, and electrically connected to an (N−2)th shift register stage of the shift register stages for receiving an (N−2)th driving control voltage, for outputting an Nth driving control voltage according to the (N−1)th start pulse signal and the (N−2)th driving control voltage; a pull-up unit, electrically connected to the input unit and an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to the Nth driving control voltage and a system clock, wherein the Nth gate line is employed to transmit the Nth gate signal; an energy-store unit, electrically connected to the pull-up unit and the input unit, for performing a charging/discharging process based on the Nth driving control voltage; and a pull-down unit, electrically connected to the input unit and the Nth gate line, and electrically connected to an (N+2)th shift register stage of the shift register stages for receiving an (N+2)th gate signal of the gate signals, for pulling down the Nth gate signal and the Nth driving control voltage according to the (N+2)th gate signal.