Patent ID: 7166509

Claim:
A method for operating a memory, comprising: programming one or more floating gate transistors in a DRAM array, wherein each floating gate transistor in the DRAM array includes a write once read only memory cell including; a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a gate insulator; wherein the floating gate is formed of a large work function material; a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; and a transmission line coupled to the second source/drain region; wherein programming the one or more floating gate transistors in the reverse direction includes: applying a first voltage potential to a first source/drain region of the floating gate transistor; applying a second voltage potential to a second source/drain region of the floating gate transistor; applying a gate potential to a control gate of the floating gate transistor; and wherein applying the first, second and control gate potentials to the one or more floating gate transistors includes creating a hot electron injection into the high work function floating gate of the one or more floating gate transistors adjacent to the source region such that the one or more floating gate transistors become programmed floating gate transistors and operate at reduced drain source current in a forward direction.