Patent ID: 7936626

Claim:
A sense amplifier for a memory comprising: a first transistor having a first end coupled to a bit line of the memory, a second end coupled to a first voltage terminal, and a control end; an operational amplifier having a first input end, a second input end coupled to the first end of the first transistor, and an output end coupled to the control end of the first transistor; and a compensating circuit coupled between the first input end and the output end of the operational amplifier, for generating a compensating voltage to the first input end of the operational amplifier according to a voltage of the control end of the first transistor, wherein the compensating circuit comprising: a first NMOS transistor having a drain, a source coupled to the ground, and a gate coupled to the output end of the operational amplifier; a first current mirror coupled to the drain of the first NMOS transistor for generating a first replicating current of bit line of the memory; a second current mirror coupled to the first current mirror for generating a second replicating current of bit line of the memory; and a resistor having a first end coupled to the second current mirror, and a second end coupled to a reference voltage source.