Patent ID: 7858987

Claim:
A semiconductor device comprising: a driver circuit including a first n-channel TFT and a p-channel TFT, and a pixel portion including a second n-channel TFT; the first n-channel TFT including a first semiconductor layer, a gate insulating film over the first semiconductor layer, and a first gate electrode over the gate insulating film, wherein the first semiconductor layer contains a first channel forming region, a pair of first impurity regions, a pair of second impurity regions, and a pair of third impurity regions; the p-channel TFT including a second semiconductor layer, the gate insulating film over the second semiconductor layer, and a second gate electrode over the gate insulating film, wherein the second semiconductor layer contains a second channel forming region, and a pair of fourth impurity regions; the second n-channel TFT including a third semiconductor layer, the gate insulating film over the third semiconductor layer, and a third gate electrode over the gate insulating film, wherein the third semiconductor layer contains a third channel forming region, a pair of fifth impurity regions, and a pair of sixth impurity regions, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode has a tapered side surface, wherein the pair of first impurity regions are overlapped with the tapered side surface of the first gate electrode, wherein the pair of second impurity regions are not overlapped with the first gate electrode, wherein the pair of fifth impurity regions are not overlapped with the third gate electrode, wherein the pair of third impurity regions contain an impurity imparting n-type at a higher concentration than that of the pair of first impurity regions and the pair of second impurity regions, and wherein the pair of sixth impurity regions contain an impurity imparting n-type at a higher concentration than that of the pair of fifth impurity regions.