Patent ID: 7861014

Claim:
A memory system, comprising: a memory hub device integrated in a memory module; and a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises: burst logic integrated in the memory hub device, wherein the burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data; and a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of read data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of read data on a memory channel, wherein the amount of read data is equal to or less than a conventional data burst amount of data for the set of memory devices, wherein, in response to receiving a read access request, the memory hub controller forwards the read access request to the set of memory devices and, in response, receives a first portion of read data having an amount of data equal to the conventional data burst amount of data from the set of memory devices, and wherein the memory hub controller selects, based on the burst length field, a second portion of the read data having a smaller amount of data than the first portion of read data.