Patent ID: 8842722

Claim:
A DFE (decision feedback equalizer) circuit, comprising: a summer circuit to add a first feedback signal, a second feedback signal, and a received signal and generate an input signal; a decision-making slicer circuit to sample the input signal from the summer circuit and generate an output signal; a feedback circuit comprising: a first feedback filter in a first feedback path of the DFE, wherein the first feedback filter comprises a continuous time filter with an order of at least 1, which generates the first feedback signal; a second feedback filter in a second feedback path of the DFE, wherein the second feedback filter comprises a continuous time filter with an order greater than 1, which generates the second feedback signal; a first delay circuit and a second delay circuit; a first analog amplifier and a second analog amplifier; and a second summer circuit; wherein the first delay circuit and first analog amplifier are serially connected between an output of the decision-making slicer circuit and a first input of the second summer circuit, wherein the second delay circuit and second analog amplifier are serially connected between an output of the decision-making slicer circuit and a second input of the second summer circuit, and wherein an output of the second summer circuit is connected to an input of the second feedback filter.