Patent ID: 7986541

Claim:
An integrated circuit device having a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, wherein the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, wherein each of the RAM blocks is disposed along a first direction in which the bitlines extend, wherein each of the memory cells has a short side and a long side, wherein the bitlines are formed along a direction in which the long side of the memory cell extends, wherein the wordlines are formed along a direction in which the short side of the memory cell extends, wherein each of the RAM blocks includes a sense amplifier circuit which outputs M-bit (M is an integer larger than one) data upon one wordline selection, wherein at least M×L (L is an integer larger than one) memory cells are arranged in each of the RAM blocks along a second direction in which the wordlines extend, and wherein (M×L)-bit data is supplied to the sense amplifier circuit upon one wordline selection.