Patent ID: 8604813

Claim:
A built-off test device, comprising: a signal processing block configured to duplicate a test signal, to apply a plurality of duplicated test signals to each of a plurality of devices under test through each of corresponding channels, and to provide a plurality of decision signals based upon a plurality of test result signals being received from each of the devices under test; an output selection block configured to merge the decision signals as a final decision signal or to sequentially output the decision signals as the final decision signal, in response to an output mode selection signal; and a signal control block configured to provide the test signal to the signal processing block or to provide the final decision signal externally, in response to a first switching control signal, wherein the signal processing block includes a plurality of signal processing units, each of the signal processing units comprising: a buffer that duplicates the test signal to provide the duplicated test signal; a relay that provides the duplicated test signal to the corresponding device under test when a second switching control signal is at a first logic level; a comparison circuit that compares the corresponding test result signal with a reference level to provide the corresponding decision signal when the second switching control signal is at a first logic level; and a register that stores and outputs the decision signal, wherein the buffer is provided with first and second power supply voltages, and a voltage level of the duplicated test signal is adjustable according to the first and second power supply voltages.