Patent ID: 8904265

Claim:
An apparatus, comprising: a turbo encoder to encode at least one information bit in accordance with a mother code to generate systematic bits, first redundancy bits, and second redundancy bits, wherein: a first of a plurality of puncturing patterns is provided as a first function of the mother code, wherein the first of the plurality of puncturing patterns is applied to puncture at least one of the systematic bits, the first redundancy bits, and the second redundancy bits to generate a first of a plurality of turbo coded blocks having a first of a plurality of code rates; and a second of the plurality of puncturing patterns is provided as a second function of the mother code, wherein the second of the plurality of puncturing patterns is applied to puncture the at least one of the systematic bits, the first redundancy bits, and the second redundancy bits to generate a second of the plurality of turbo coded blocks having a second of the plurality of code rates; and wherein the turbo encoder shifts by at least one bit, at least one of: the first of the plurality of turbo coded blocks, and the second of the plurality of turbo coded blocks; and a transmitter to: modulate a first of the plurality of turbo coded blocks to generate a first of a plurality of turbo coded signals during a first time; and modulate a second of the plurality of turbo coded blocks to generate a second of the plurality of turbo coded signals during a second time.