Patent ID: 7137022

Claim:
A timing adjustment circuit, comprising: an input circuit effective to receive an external clock signal and output an input clock signal; a delay adjustment circuit effective to delay the input clock signal from the input circuit to output a delayed input clock signal; and a clock driver effective to output an internal clock signal to a data output circuit in response to the delayed input clock signal from the delay adjustment circuit, so that a phase of an output signal outputted from the data output circuit has a predetermined relation with respect to that of the external clock signal, a phase advance/delay signal generation unit, the phase advance/delay signal generating unit effective to selectively compare the internal clock signal and either one of the external clock signal and the output signal of the data output circuit to produce a phase advance/delay signal indicating whether the phase of the output signal of the data output circuit advances or delays with respect to the phase of the external clock signal; a phase comparison circuit for comparing the phase of the output signal of the replica circuit with that of the external clock signal and outputting a comparison result to the delay adjustment circuit to adjust the delay of the delay adjustment circuit; and an external output unit for outputting an output of the phase comparison circuit to the outside, wherein the comparison result of the phase comparison circuit is supplied as the phase advance/delay signal to the external output unit.