Patent ID: 7076615

Claim:
A scalable, interval matching circuit, comprising: a. an input terminal, configured to receive data representing an ordered k-bit input group, the input bit group having n contiguous segments, b. a configurable queuing means for receiving said contiguous segments and independently delaying each of the segments by different preconfigured amounts, producing an ordered k-bit group of delayed segments, c. an ordered set of interval calculators, each of the interval calculators accessing a configurable memory element, decode and arithmetic logic, such that each of said interval calculators will receive, according to order number, one of the said delayed segments, and each said interval calculator will: i. receive an o-bit entry_ptr field signal, ii. produce an o-bit next_entry_ptr signal, d. a means for ordered interconnection of said interval calculators, so as to connect each said next_entry_ptr output to the neighboring entry_ptr input, e. a means to configure said configurable queuing means and the configurable memory elements of said interval calculators, f. an output terminal producing data representing a value uniquely identifying the interval or intervals matched by said k-bit input group.