Patent ID: 7983370

Claim:
A clock and data recovery circuit comprising: a phase synchronization loop including: an oscillator outputting a clock signal, a frequency of which is variably controlled based on a control signal supplied thereto; a first phase detector detecting a phase difference between said clock signal output from said oscillator and a received data signal; and a first integrator integrating an output from said first phase detector to supply an integrated signal to said oscillator as said control signal; a discriminator circuit, responsive to a discrimination clock signal, discriminating said received data signal and outputting a discriminated data signal; a second phase detector circuit detecting a phase difference between said discriminated data signal, discriminated and output by said discriminator circuit, and said received data signal; a second integrator integrating a comparison result output from said second phase detector circuit; and a phase shift circuit shifting a phase of said clock signal, output from said oscillator, based on an integrated signal from second integrator, to produce said discrimination clock signal supplied to said discriminator circuit, wherein said discriminator circuit, said second phase detector circuit, said second integrator and said phase shift circuit comprise a feedback loop separate from said phase synchronization loop.