Patent ID: 7626518

Claim:
A decoding system in a graphics processing unit, comprising: a software programmable core processing unit having a variable length decoding unit (VLD) unit, the VLD unit capable of performing shader functionality, the shader functionality including selectively implementing decoding of a video stream coded based on at least one of a plurality of different coding methods to provide a decoded data output, wherein the VLD unit further comprises a direct memory access (DMA) engine module comprising a bitstream buffer and DMA engine, the DMA engine module configured to, responsive to execution of a shader instruction per slice, repeatedly and automatically buffer in the bitstream buffer a predefined quantity of bits as the predefined bits are consumed, the bits corresponding to the video stream, and wherein the VLD unit is further configured to stall the DMA engine module responsive to anticipated underflow in the bitstream buffer, wherein the decoding is implemented using a combination of software and hardware.