Patent ID: 7018925

Claim:
A method for manufacturing a dual gate integrated circuit, comprising: forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate; patterning a photoresist over said nitridated, high voltage gate dielectric layer to expose said nitridated, high voltage dielectric within a low voltage region, said patterning leaving an accelerant residue on said exposed nitridated, high voltage gate dielectric layer; and subjecting said exposed nitridated, high voltage dielectric to a high vacuum to remove said accelerant residue; forming a nitridated, low voltage gate dielectric layer over said semiconductor substrate within said low voltage regions; forming high voltage gate transistors over said nitridated, high voltage gate dielectric layer; forming low voltage gate transistors over said nitridated, low voltage gate dielectric layer; forming source/drain regions associated with each of said high voltage and low voltage transistors; forming dielectric layers located over said high voltage and low voltage transistors; and forming interconnects extending through said dielectric layers to interconnect said high voltage and low voltage transistors to form an operative integrated circuit.