Patent ID: 7006391

Claim:
A semiconductor memory device for reading and writing storage data in accordance with an address signal, comprising: a regular memory cell array having a plurality of regular memory cells arranged in rows and columns, said regular memory cell array being divided into a plurality of regular memory cell groups each having memory cell rows of M in number (M: natural number) and memory cell columns of N in number (N: natural number) being in correspondence with each other; and a redundant repair circuit for repairing a regular memory cell possibly having a defect, said redundant repair circuit including a plurality of spare memory cell groups to replace the regular memory cell groups when said address signal matches with a replacement address, each of said spare memory cell groups including M spare memory cell rows and N spare memory cell columns, a plurality of replacement address storage circuits provided for the spare memory cell groups for storing, as said replacement addresses, the addresses corresponding to the regular memory cell groups containing the defective memory cells, respectively, and an address comparing circuit for instructing repairing of the regular memory cell in accordance with the comparison between said address signal and said replacement address.