Patent ID: 8453090

Claim:
A method of optimizing a logic circuit, the method comprising: providing a logic circuit, the logic circuit comprising cells; performing a static timing analysis of the logic circuit using a computer; identifying an input of a logic circuit cell that violates a timing condition, the input coupled to a logic path comprising at least one level of logic, identifying the input of the logic circuit comprising determining an early arrival time and a late arrival time at the input of the logic circuit cell that violates the timing condition, comparing a difference between the early arrival time and the late arrival time to a threshold, and determining that the timing condition is violated if the difference between the early arrival time and the late arrival time is greater than the threshold; identifying a last node along the logic path that violates the timing condition; and inserting a buffer to fix the timing condition, inserting comprising placing the buffer at least one node before the last node along the logic path that violates the timing condition.