Patent ID: 7154766

Claim:
A ferroelectric memory comprising: a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor; a sense amplifier connected to the bit line; a block selector decoder which controls ON/OFF of the block selecting transistor; and an enable signal generating circuit which controls timing for operating the sense amplifier and the block selector decoder, wherein each of said plurality of unit cells has a structure in which a ferroelectric capacitor and a cell transistor are connected in parallel, the enable signal generating circuit changes the timing for operating the sense amplifier and the block selector decoder depending on a position of a selected unit cell objective for data read of said plurality of unit cells, and wherein the period until the sense amplifier is operated since the level of the plate line is changed depending on the position of the selected unit cell and the period until the block selecting transistor is turned off since the level of the plate line is changed change complementarily.