Patent ID: 7348236

Claim:
A method of concurrently forming a select gate and a floating-gate memory cell in a NAND memory array, the method comprising: anisotropically removing portions of a second conductive layer disposed on and adjoining an upper surface and sidewalls of a first conductive layer such that remaining portions of the second conductive layer self align with and form conductive spacers on the sidewalls of the first conductive layer, the first conductive layer is disposed on a first dielectric layer that is disposed on a substrate of the memory array, wherein the first conductive layer and the conductive spacers form a floating gate of the floating-gate memory cell in a memory cell portion of the memory array; forming a second dielectric layer overlying the first conductive layer and the conductive spacers; forming a third conductive layer on the second dielectric layer; forming a fourth conductive layer on the third conductive layer so that, in a select gate portion of the memory array, the fourth conductive layer passes through the third conductive layer and the second dielectric layer and contacts the first conductive layer to electrically connect the first and third conductive layers in the select gate portion of the memory array, wherein the third and fourth conductive layers form a control gate of the floating-gate memory cell, wherein the fourth conductive layer and the electrically connected first and third conductive layers form a control gate of the select gate; forming a cap layer on the fourth conductive layer, wherein a portion of the cap layer in the select gate portion of the memory array extends below an upper surface of the third conductive layer; and separating the select gate in the select gate portion of the memory array from the floating-gate memory cell in the memory cell portion of the memory array.