Patent ID: 7464284

Claim:
A system for driving data over a data bus, the system comprising: a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus; a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal; an output latch device that drives data over the data bus in response to an edge of the data clock signal; and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock; wherein the output latch device includes a plurality of master-slave latches, each having a master portion and a slave portion, the skew corrector generating a master clock that allows data to pass from an input of the master portion to an input of the slave portion in response to both the bus clock signal and the data clock signal being provided in a same predetermined state, the master clock blocking the data from passing from the master portion to the slave portion in response to the bus clock signal and the data clock signal being provided in different states, and the slave portion driving data over the data bus in response to an edge of the data clock signal.