Patent ID: 8743580

Claim:
A system comprising: a first memory cell comprising: a first pass transistor comprising: a first drain coupled to either a first bit line or a second bit line through a first conductive path formed by a first first-level contact and a first first-level via, wherein the first bit line and the second bit line are formed in a first interconnect layer; a first gate coupled to a first word line through a first word line strap structure formed in the first memory cell, wherein the first word line is in a second interconnect layer formed over the first interconnect layer; and a first source coupled to a first VSS line formed in a first first-level contact; a second memory cell horizontally adjacent to the first memory cell, wherein the second memory cell comprises: a second pass transistor comprising: a second source coupled to a third VSS line formed in the first first-level contact, wherein the third VSS line is electrically coupled to the first VSS line; and a second gate coupled the first word line through the first word line strap structure; and a second VSS line formed in the first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line and the third VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line.