Patent ID: 8000158

Claim:
A semiconductor memory device, comprising: a plurality of memory cell matrixes, each of which contains a multiplicity of memory cell arrays whose number is larger than 2 n and smaller than 2 n+1 , n being a natural number, the multiplicity of memory cell arrays comprising 2 m normal memory cell arrays, m being a number of bits of an address, wherein a data access operation is performed on a normal memory cell in the normal memory cell arrays as a normal word line corresponding to the normal memory cell is activated in response to the address, and 2 n+1 −2 m dummy cell arrays; and redundancy memory cell arrays for use in a repair operation, wherein a first repair-expected memory cell in the normal memory cell arrays is replaced with a dummy cell included in the dummy cell arrays as a redundancy word line corresponding to the dummy cell is activated in response to an address corresponding to the first repair-expected memory cell, wherein a second repair-expected memory cell in the normal memory cell arrays is replaced with a redundancy memory cell included in the redundancy memory cell arrays in response to an address corresponding to the second repair-expected memory cell, and wherein the first repair-expected memory cell and the second repair-expected memory cell are disposed on the basis of a bit line sense amplifier.