Patent ID: 7002202

Claim:
A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the memory device comprises: an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising: a bottom electrode; a top electrode; a dielectric layer interposed between the bottom electrode and the top electrode; and at least one metal oxynitride barrier layer, wherein each metal oxynitride barrier layer is interposed between the dielectric layer and an electrode selected from the group consisting of the bottom electrode and the top electrode; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.