Patent ID: 7851867

Claim:
An integrated circuit, comprising: a semiconductor substrate that has a first well region and a second well region containing p-type impurity at a first concentration; an enhancement type MOS transistor formed in the first well region and having a first channel region under a first gate electrode; and a depletion type MOS transistor formed in the second well region and having a second channel region under a second gate electrode, wherein in a surface region of the first channel region, a first layer is formed that contains a p-type impurity at a second concentration, in a surface region of the second channel region, a second layer is formed that contains an n-type impurity at a third and a p-type impurity at a fourth concentration, the fourth concentration is the same as the first concentration and the second concentration is higher than the first concentration, and wherein in the second channel region, second p-type pocket implantation regions are provided under and directly contact the second layer; and in the first channel region, first p-type pocket implantation regions are provided under and directly contact the first layer.