Patent ID: 7787320

Claim:
A semiconductor memory comprising: a memory cell and a reference cell comprised a resistance change element; a first bit line connected to one end of the memory cell; a second bit line connected to one end of the reference cell; and a sense amplifier connected to the first bit line and the second bit line, wherein the sense amplifier includes, a first FET of a first conductive type in which a drain is connected to a first output node, a gate is connected to a second output node, and a source is connected to a first power source node; a second FET of a first conductive type in which a drain is connected to the second output node, a gate is connected to the first output node, and a source is connected to the first power source node; a third FET of a second conductive type in which a drain is connected to the first output node, a gate is connected to the second output node, and a source is connected to a first input node; a fourth FET of a second conductive type in which a drain is connected to the second output node, a gate is connected to the first output node, and a source is connected to a second input node; a fifth FET of a second conductive type in which a drain is connected to the first input node, and a source is connected to a second power source node; and a sixth FET of a second conductive type in which a drain is connected to the second input node, and a source is connected to the second power source node, the sense operation being started by charging or discharging the first output node from the first input node with a first current and by charging or discharging the second output node from the second input node with a second current, and the fifth and sixth FETs are turned off at starting the sense operation and turned on after starting the sense operation, the first bit line is connected to the first input node, and the second bit line is connected to the second input node.