Patent ID: 7094689

Claim:
A method for forming an interconnect structure, comprising the steps of: providing a semiconductor substrate with a first barrier layer formed thereon; forming a first dielectric layer above the first baffler layer; patterning and etching the first dielectric layer to form a plurality of stakes having first openings therebetween, the plurality of stakes for providing mechanical supporting strength for the interconnect structure, the first openings exposing a portion of the first baffler layer; forming a sacrificial layer in the first openings and above the plurality of stakes; forming a hard mask layer above the sacrificial layer; forming a light sensitive layer over the hard mask layer; patterning the light sensitive layer to define a pattern therein; etching the hard mask layer, the sacrificial layer, and the first baffler layer according to the pattern in the light sensitive layer to form second openings; filling the second openings with a conductive material to form metal lines; and removing the sacrificial layer to form air gaps.