Patent ID: 7272058

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory blocks which are arranged in an array form and can collectively erase data stored therein and a redundant block having memory cells not less than memory cells in one of the memory blocks; associating means for associating a faulty block containing a faulty memory cell with the redundant block; a block switching circuit for selecting the associated redundant block when the memory block identified by an input address is associated with the redundant block by the associating means; an error detection circuit for detecting an error in an accessing operation to the memory block; and a faulty block identification circuit for identifying the memory block having the detected error as a faulty block when the error is detected by the error detection circuit, wherein when the error is detected by the error detection circuit, in the case where the redundant block which is not associated with the faulty block exists, the faulty block identification circuit associates the faulty block having the detected error with the redundant block.