Patent ID: 8891304

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of blocks, each of the plurality of blocks including a plurality of memory strings and a plurality of word lines, each of the plurality of memory strings including serially connected memory cells, one end of the serially connected memory cells is coupled to a bit line through a first select transistor and another end is coupled to a source line through a second select transistor; and a controller configured to: read data by applying a first read pass voltage to unselected word lines and applying a read voltage to a selected word line; before a read operation is performed, apply the first read pass voltage to all of the plurality of word lines to detect an overly programmed memory cell that is not turned on even though the first read pass voltage is applied to its gate; and when at least one overly programmed memory cell is detected, read data by applying a second read pass voltage to the unselected word lines and applying the read voltage to the selected word line, wherein the second read pass voltage is higher than the first read pass voltage.