Patent ID: 7437544

Claim:
A data processing apparatus comprising: an instruction store operable to store a sequence of instructions including at least one multiple iteration instruction; and a processing unit operable to execute the sequence of instructions, the processing unit comprising at least a first processing path and a second processing path to enable at least two instructions of the sequence to be executed in parallel, wherein: for each instruction in said sequence, the instruction store is operable to issue that instruction to one of the first processing path or the second processing path, when executing instructions in parallel, the first processing path is operable to execute an instruction which is earlier in the sequence than the instruction executed in the second processing path, the multiple iteration instruction is an instruction which when issued once to a processing path by the instruction store is iteratively executed multiple times within the processing unit, and when executing the multiple iteration instruction, the processing unit is operable to cause a first iteration of the multiple iteration instruction to be executed in that one of the first processing path or the second processing path to which the multiple iteration instruction has been issued by the instruction store, but to cause all remaining iterations of the multiple iteration instruction to be executed in the first processing path.