Patent ID: 7009878

Claim:
A non-volatile semiconductor device comprising: a memory cell array having electrically erasable programmable non-volatile memory cells; a plurality of reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array, each reprogramming and retrieval circuit having a first latch and a second latch, the first latch being connected to a selected bit line of the memory cell array via a first transfer switch and a second transfer switch series-connected to each other, the second latch being connected to a connection node of the first and the second transfer switches via a third transfer switch, a data node of the second latch being connected to data input and output lines via column selection switches; and a controller that controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array, wherein, after the data has been programmed in a selected memory cell, the programmed data is retrieved for programming verification, the retrieved data being sensed and stored in the first latch.