Patent ID: 6893930

Claim:
A method for fabricating a field effect transistor on an active device area of a semiconductor substrate, the method including the steps of: A. forming a gate dielectric and a gate electrode on said active device area of said semiconductor substrate; B. implanting antimony (Sb) dopant into exposed regions of said active device area of said semiconductor substrate to form a drain extension junction and a source extension junction; C. performing a low temperature thermal anneal process at a temperature less than about 950° Celsius for activating said antimony (Sb) dopant within said drain and source extension junctions; D. forming spacers at sidewalls of said gate dielectric and said gate electrode; E. implanting antimony (Sb) dopant into exposed regions of said active device area of said semiconductor substrate to form a drain contact junction and a source contact junction having a deeper depth than said drain and source extension junctions; F. performing a low temperature thermal anneal process at a temperature less than about 950° Celsius for activating said antimony (Sb) dopant within said drain and source contact junctions; and wherein said steps D, E, and F are performed after said step A and before said steps B and C such that said drain and source contact junctions are formed before said drain and source extension junctions in a disposable spacer process with an additional step of: G. removing said spacers from said sidewalls of said gate dielectric and gate electrode after said steps E and F and before said steps B and C.