Patent ID: 7692103

Claim:
A wiring substrate comprising: a lower insulating resin layer; wiring pattern layers provided on surfaces of the lower insulating resin layer; upper insulating resin layers provided on surfaces of the lower insulating resin layer and the wiring pattern layers; via holes extending through at least one of the upper insulating resin layers; and via conductors provided in the via holes and connected electrically with at least one of the wiring pattern layers, wherein at least one of the upper insulating resin layers contains an epoxy resin containing 30 to 50% by weight of an inorganic filler of SiO 2 having an average grain diameter of 1.0 to 10.0 μm and a thermal coefficient of greater than 40 ppm/° C. to 50 ppm/° C., and at least one of the via holes has a lower end opening diameter of 40 μm or more and less than 60 μm on a side of the wiring pattern layers.