Patent ID: 7054181

Claim:
A non-volatile ferroelectric cell array block having a hierarchy transfer sensing architecture, comprising: a plurality of sub cell arrays, each with a hierarchy bit line architecture, wherein each of a plurality of main bit lines is connected to a plurality of sub bit lines which are formed at both sides of one main bit line and selectively connected to the one main bit line to transfer cell data; a plurality of sub bit line sense amplifiers corresponding one by one to the sub cell arrays, sensing a cell data transferred to a sub bit line of a corresponding sub cell array in response to a sensing control signal and thereby amplifying the cell data of the corresponding sub bit line; a main bit line sense amplifier, sensing the cell data transferred to the corresponding main bit line from the sub bit line amplified by the sub bit line sense amplifier and thereby amplifying the cell data of the main bit line; and a word line/plate line driver, selectively activating a word line/a plate line of the sub cell array for a read and write operation of the cell data.