Patent ID: 8458503

Claim:
A system comprising: a processor coupled to a platform control hub, an external voltage regulator and an embedded controller, the processor having a sustain power plane including: a cache memory in which a processor context is stored, a wake logic to handle processor wakeup and context restore, an input/output (I/O) interface between the processor and the platform control hub, the external voltage regulator and the embedded controller, and an electrostatic discharge clamp; wherein the processor is to enter a connected standby sleep state upon: receipt of a timer signal from the wake logic; gating of a clock operating in the processor; powering of the cache memory with a dedicated power plane separate from the sustain power plane; powering down of remaining components powered by the sustain power plane and powering down of the sustain power plane; redirection of wakeup sources for handling processor wakeup and context restore to the platform control hub; and transference of at least one architectural function of the processor to the platform control hub.