Patent ID: 6924675

Claim:
A buffer device, comprising: an input line device for receiving input data; a plurality of latch stages connected to said input line device, each of said latch stages including at least a data input terminal, a latch device, a multiplexer, and a data output terminal; said multiplexer having at least a first selection state and a second selection state, and said multiplexer being provided and configured in a respective one of said latch stages and being controllable such that either said data output terminal is selectively supplied directly with the input data present at said input line device, when said multiplexer is in the first selection state, or said data output terminal is supplied with data buffered in said latch device, when said multiplexer is in the second selection state, for providing data with one of a selectable latency and a selectable delay; an output line device for outputting output data corresponding to the input data; said latch device of a first one of said latch stages, as seen from said output line device, having a feedback loop for data buffering; and said multiplexer of said first one of said latch stages being associated with said feedback loop and being configured such that the output data on said output line device are kept stable.