Patent ID: 7358143

Claim:
A method of manufacturing a semiconductor device having a trench gate type MISFET, comprising the steps of: (a) providing a semiconductor substrate; (b) forming a single crystal silicon layer over a main surface of the semiconductor substrate; (c) forming a plurality of gate trenches of the MISFET on a main surface of the single crystal silicon layer; (d) forming a plurality of gate dielectric films in the gate trenches respectively; (e) forming a plurality of gate portions on the gate dielectric films respectively; (f) forming a plurality of channel regions of the MISFET, in the single crystal silicon layer, between adjacent gate portions respectively; (g) forming a plurality of source regions of the MISFET, in the single crystal silicon layer, over the channel regions respectively; (h) forming a silicon oxide film over the source regions and gate portions; (i) forming a plurality of contact trenches, in the silicon oxide film and single crystal silicon layer, to expose the source regions and channel regions; (j) forming a barrier film in the contact trenches to contact with the source regions and channel regions; and (k) forming a source electrode on the barrier film, wherein conduction types of the semiconductor substrate, single crystal silicon layer and source regions are n-type; wherein a conduction type of the channel regions is p-type; wherein the source electrode is comprised of an aluminum film; and wherein the barrier film is comprised of a molybdenum silicide film.