Patent ID: 7904667

Claim:
A memory device, comprising: one or more controlling bits, wherein each controlling bit is capable of being set; and one or more controlled register bits coupled to the one or more controlling bits, wherein each controlled register bit is capable of being coupled to an external binary state device, each binary state device being located external to the memory device; wherein the setting of the one or more controlling bits defines which controlled register bits of the one or more controlled register bits are input read register bits and which are output drive register bits; and wherein, each input read register bit is capable of reflecting a state signal associated with an external binary state device coupled to the input read register bit, and each output drive register bit is capable of reflecting a state signal associated with an external binary state device coupled to the output drive register bit and is further capable of altering the state signal associated with the external binary state device coupled to the output drive register; and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.