Patent ID: 7754531

Claim:
A method for packaging microelectronic devices, comprising: coupling a plurality of individual microelectronic dies to a support member after the microelectronic dies have been singulated, wherein the individual dies include at least a first microelectronic die and a second microelectronic die; depositing an encapsulant onto the dies and the support member and thereby forming a first dielectric layer that covers the dies and at least a portion of the support member; forming a plurality of vias in the first dielectric layer, wherein the vias in the first dielectric layer include (a) first vias that are aligned with individual microelectronic dies and extend a first depth through the first dielectric layer to the individual microelectronic dies and (b) second vias that are between individual microelectronic dies and extend a second depth completely through the first dielectric layer to the support member; fabricating a plurality of conductive lines in the first vias, wherein individual conductive lines extend between first ends electrically coupled to the dies and second ends on and/or in the first dielectric layer; fabricating first portions of a plurality of conductive links in the second vias; depositing a second dielectric layer onto the conductive lines, the conductive links and exposed areas of the first dielectric layer between the conductive lines and the conductive links; forming a plurality of vias through the second dielectric layer, wherein the vias in the second dielectric layer include (a) third vias that extend through the second dielectric layer to the second ends of the conductive lines and (b) fourth vias that extend through the second dielectric layer to the conductive links; fabricating a plurality of conductive ball-pads in the third vias; fabricating second portions of the plurality of conductive links in the fourth vias; and cutting the support member, the first dielectric layer and the second dielectric layer to separate the first and second dies.