Patent ID: 7742343

Claim:
A metal oxide semiconductor device array structure comprising: a plurality of metal oxide semiconductor devices coupled to each other and each of said metal oxide semiconductor devices comprises: a device layer having a first surface and a second surface; a first ion-implanted layer formed on said first surface of said device layer and providing at least one source, at least one drain and at least one channel; and at least one first gate structure formed on said first ion-implanted layer; a plurality of bit-line selection switches coupled to said metal oxide semiconductor devices; a plurality of bit lines, wherein each said bit line is coupled to said metal oxide semiconductor devices via a plurality of bit-line contact windows on different said device layers and said bit-line selection switches on different said device layers; and a plurality of word lines interconnecting said gate structures of said metal oxide semiconductor devices and implementing turning on/off of said metal oxide semiconductor devices, wherein data are transferred to specified said metal oxide semiconductor devices via said bit lines; said metal oxide semiconductor devices are further coupled to a source line, and said source line perpendicularly crosses said bit lines; each of said source line is coupled to said metal oxide semiconductor devices via a plurality of source-line contact windows on different said device layers and said source-line selection switches on different said device layers; and said bit lines are further coupled to a plurality of bit-line contact windows to integrate corresponding said metal oxide semiconductor devices into a 3-dimensional array structure.