Patent ID: 7662665

Claim:
A method for fabricating a semiconductor package, comprising: providing a semiconductor chip comprising a dielectric layer therein having a plurality of exposed conductive layers thereon; providing a first dielectric substrate having a first surface and a second surface, the first surface having a plurality of exposed via plugs thereunder, wherein no solder bump formed between the semiconductor chip and the first dielectric substrate, wherein the dielectric layer in the semiconductor chip and the first dielectric substrate have different dielectric constants from each other; bonding the semiconductor chip to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs; removing a portion of the second surface of the first substrate to expose the opposite ends of the plurality of via plugs; forming a plurality of UBM layers on the surfaces of the opposite ends of the plurality of via plugs; forming a plurality of solder bumps mounted on the UBM layers; and providing a second substrate having a first surface and a second surface, the solder bumps mounted to the first surface of the second substrate.