Patent ID: 7737000

Claim:
A process for the collective fabrication of structures having two superposed elements bonded together, starting from two plates, a first lower plate including an array of first elements and a second upper plate including second elements, the first plate including electronic circuitry elements and contact pads and having upper face protected by a planar insulating protective layer covering all of said electronic circuitry elements, said planar insulating protective layer having indentation zones formed by etching a thickness of said protective layer along dicing paths, said contact pads being located within the indentation zones, the process comprising the following steps: bonding a lower face of the second upper plate to the insulating layer formed on the upper face of the first lower plate, over the major portion of their respective surfaces, but not bonding the indentation zones in the insulating protective layer on the first lower plate; and dicing the first lower and second upper plates into individual structures including said two superposed elements, comprising said first element belonging to said first lower plate and the second element belonging to said second upper plate, the dicing comprising at least dicing of an element of the second upper plate via its topside along a first dicing line passing along a dicing path, and dicing of an element of the first lower plate, located beneath the element of the second upper plate, via its underside along a second dicing line passing along the same dicing path but not superposed with the first dicing line, so that a portion of the first element, including said contact pads, lying between the two dicing lines, is not covered by the second element.