Patent ID: 8232589

Claim:
A semiconductor integrated circuit device comprising: a plurality of static type memory cells each having a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor, a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, a gate of the second P-channel MOS transistor and a gate of the second N-channel MOS transistor being connected to each other, and a drain of the second P-channel MOS transistor, a drain of the second N-channel MOS transistor, a gate of the first P-channel MOS transistor and a gate of the first N-channel MOS transistor being connected to each other; a power line connected to sources of the first and second P-channel MOS transistors of the plurality of static type memory cells; a source line connected to sources of the first and second N-channel MOS transistors of the plurality of static type memory cells; and a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line, wherein insulating layers used in the gates of the first P-channel MOS transistor, the second P-channel MOS transistor, the first N-channel MOS transistor, and the second N-channel MOS transistor have a thickness of 4 nm or less, wherein the power voltage control circuit controls the power voltage so that the power voltage becomes a first voltage in an operating mode and a second voltage smaller than the first voltage in a standby mode to make a gate tunnel leak current flowing between the source and the gate of the first P-channel MOS transistor and a gate tunnel leak current flowing between the source and the gate of the second N-channel MOS transistor smaller in the standby mode rather than in the operating mode in case that the first P-channel MOS transistor and the second N-channel MOS transistor are in on-state, and wherein a potential of a substrate of the first P-channel MOS transistor in the standby mode is equivalent to a potential of the source of the first P-channel MOS transistor in the standby mode, and a potential of a substrate of the second P-channel MOS transistor in the standby mode is equivalent to a potential of the source of the second P-channel MOS transistor in the standby mode.