Patent ID: 8409955

Claim:
A method of forming a semiconductor device, the method comprising: forming active regions and isolation regions in a semiconductor substrate, the active regions and isolation regions extending in line patterns in a first direction, the active regions and isolation regions being alternately aligned in a second direction across the first direction; forming gate electrode grooves in the semiconductor substrate, the gate electrode grooves extending in the second direction and across the active regions and isolation regions; forming gate insulating films on inside walls of the gate electrode grooves; forming buried gate electrodes on the gate insulating films and in lower portions of the gate electrode grooves; forming cap insulating films in upper portions of the gate electrode grooves, the cap insulating films covering the buried gate electrodes; forming a first interlayer insulating film on an upper surface of the cap insulating film and on an upper surface of the semiconductor substrate; planarizing an upper surface of the first interlayer insulating film; forming openings in line shape in the first interlayer insulating film, the openings exposing first active regions and the isolation regions, the first active regions being adjacent to the isolation regions in the second direction, the first active regions being for formation of bit line contacts; forming a conductive layer which bury the openings and extends over the first interlayer insulating film, the conductive layer in the openings being in contact with upper surfaces of the first active regions; forming a first silicon nitride film on an upper surface of the conductive layer; and patterning a stack of the conductive layer and the first silicon nitride film to form bit-lines including bit contacts which are in contact with the upper surfaces of the first active regions.