Patent ID: 8830510

Claim:
A serial communication apparatus comprising a reception apparatus and a transmission apparatus, wherein: the reception apparatus includes: a reception unit configured to receive one bit of data in a predetermined cycle; a memory unit; a reception counter which is updated when the data received by said reception unit has the same value as that of 1-bit data received one cycle before; a memory control unit configured to control storage into said memory such that when a value of said reception counter reaches a first value, the data received by said reception unit is stored into said memory, and when the data received by said reception unit is different from the data received one cycle before, the 1-bit data received one cycle before is stored into said memory; and a storage counter which is updated when data having the same value is stored into said memory, wherein when a value of said storage counter reaches a third value, said memory control unit further controls storage into said memory not to store the data into said memory, and the transmission apparatus includes: a generation unit configured to generate data; an addition unit configured to increment, when 1-bit data of the data generated by said generation unit is the same as preceding 1-bit data, a bit count, and add, when an incremented bit count meets a predetermined condition, inverted data as dummy bit data; and a transmission unit configured to transmit the data generated by said generation unit or the dummy bit data added by said addition unit in a second predetermined cycle, wherein a maximum cycle (T) of the second predetermined cycle and the predetermined cycle (SCLK) satisfy SCLK=T/n (n is a natural number not less than 3), and the predetermined condition is that bit count (m) as a condition for adding the dummy bit data meets m≦n−1.