Patent ID: 7681154

Claim:
A method for designing a device, the device comprising a first semiconductor chip, a second semiconductor chip and an adjustment target, the first semiconductor chip comprising an input pad, a first power supply pad and a first ground pad and serving as an input circuit, the second semiconductor chip comprising an output pad, a second power supply pad and a second ground pad and serving as an output circuit, the output pad being electrically coupled to the input pad, the adjustment target being connected to the first and the second semiconductor chips, the method comprising: calculating using a computer a main target variable from an input circuit chip model, an output circuit chip model and a target impedance model, the input circuit chip model being created by representing the first semiconductor chip in frequency domain in consideration of first and second capacitor models and a chip internal capacitor model, the first capacitor model being between the input pad and the first power supply pad, the second capacitor model being between the input pad and the first ground pad, the chip internal capacitor model being between the first power supply pad and the first ground pad, the output circuit chip model being created by representing the second semiconductor chip in frequency domain, the target impedance model being assumed by representing the adjustment target in frequency domain; and comparing using the computer the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.