Patent ID: 8883577

Claim:
A semiconductor device manufacturing method comprising: forming a fin region over a substrate, the fin region having an apex portion and a sidewall portion and extending in a first direction; forming a dummy gate electrode over the fin region, the dummy gate electrode extending in a second direction different from the first direction; forming a first insulating film over the dummy gate electrode and the fin region; polishing the first insulating film until the dummy gate electrode is exposed; removing at least part of the exposed dummy gate electrode to form a trench, a surface of the fin region being exposed in the trench while leaving at least part of the dummy gate electrode positioned under the first insulating film and a second part of the dummy gate electrode at a bottom portion of the trench without removing; after removing the exposed dummy gate electrode, forming a gate insulator over the surface of the fin region exposed in the trench; depositing a gate electrode material over the gate insulator and over the first insulating film; and polishing the gate electrode material over the first insulating film until the first insulating film is exposed to form a gate electrode.