Patent ID: 7539056

Claim:
A nonvolatile semiconductor memory comprising: a data line; a first memory cell unit including not only a first memory string in which a plurality of memory cells with charge accumulating regions are electrically connected in series but also first and second select transistors connected to said data line from one end of said first memory string; a second memory cell unit including not only a second memory string structured similarly to said first memory string but also third and fourth select transistors connected to said data line from one end of said second memory string, said second memory cell unit being adjacent to said first memory cell unit; a third memory cell unit including not only a third memory string structured similarly to said first memory string but also fifth and sixth select transistors connected to said data line from one end of said third memory string, said third memory cell unit being adjacent to said second memory cell unit; a first select signal line electrically connected to a control electrode of said first select transistor of said first memory cell unit and to a control electrode of said third select transistor of said second memory cell unit; and a second select signal line electrically connected to a control electrode of said fourth select transistor of said second memory cell unit and to a control electrode of said sixth select transistor of said third memory cell unit.