Patent ID: 7250333

Claim:
A method comprising: forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel; forming a source doped region and a drain doped region on laterally opposed sides of the gate electrode in the substrate; forming a spacer having a first insulating layer and a second insulating layer on laterally opposed sides of the gate electrode, wherein the first insulating layer and the second insulating layer are different materials; forming an unlinearized drain contact region abutting the drain doped region in the substrate; forming a resistor doped region abutting the unlinearized drain contact region in the substrate, the resistor doped region having an area to provide a resistivity to linearize a voltage transfer characteristic across the sourced doped region and to perform as a resistor for an output stage of a buffer used to drive a transmission line; and forming a linearized drain contact region abutting the resistor doped region.