Patent ID: 7808570

Claim:
A display device active matrix substrate comprising: an insulating substrate having a display area where pixels are disposed in a matrix shape and a peripheral circuit area disposed in a peripheral area of said display area where peripheral circuits are formed; a plurality of scanning lines formed in said display area along a row direction; a plurality of image data lines formed in said display area along a column direction, said image data lines defining a plurality of pixel areas together with said scanning lines; a pixel transistor island semiconductor layer formed in said display area near at each cross point between said scanning line and said image data line, and a plurality of peripheral circuit transistor island semiconductor layers formed in said peripheral circuit area; a gate insulating film for a pixel, having a first thickness and covering a middle position of each of said pixel transistor island semiconductor layers; a first gate electrode made of a first wiring line disposed on said first gate insulating film for a pixel above and overlapping said pixel transistor island semiconductor layers; a gate insulating film for a peripheral circuit, having a second thickness thinner than said first thickness and covering a middle position of each of part of said peripheral circuit transistor island semiconductor layers; and a second gate electrode made of a second wiring line and disposed on said gate insulating film for a peripheral circuit, wherein said pixel transistor island semiconductor layer, said gate insulating film for a pixel and said first gate electrode constitute a pixel transistor, and said scanning line includes a lower scanning wiring line made of said second wiring line and an upper scanning wiring line made of said first wiring line, formed above said lower scanning wiring line and extending across at least one of said plurality of image data lines, said upper scanning wiring line being connected to said lower scanning wiring line, wherein said gate insulating film for a pixel includes a lower first gate insulating film made of a same layer as said gate insulating film for a peripheral circuit and an upper gate insulating film formed on said lower first gate insulating film, and wherein an intermediate insulating layer made of a same layer as said upper second gate insulating film is disposed covering said lower scanning wiring line, an intermediate contact hole is formed through said intermediate insulating layer, and said upper scanning wiring line is formed on said intermediate insulating layer, and connected to said lower scanning wiring line via said intermediate contact hole.