Patent ID: 8345052

Claim:
A method for using a graphics processing unit (“GPU”) frame buffer in a multi-GPU computing device as cache memory, comprising: designating a first GPU subsystem in the multi-GPU computing device as a rendering engine, wherein the first GPU subsystem includes a first GPU and a first frame buffer; designating a second GPU subsystem in the multi-GPU computing device as a cache accelerator, wherein the second GPU subsystem includes a second GPU and a second frame buffer; and directing an upstream memory access request associated with an address from the first GPU subsystem to a port associated with a first address range; configuring the first address range to cover a first portion of a second address range assigned to the second GPU subsystem; determining that the memory access request is directed to a second portion of the second address range, wherein the second portion of the second address range is not accessible to the first GPU; and redirecting the memory access request to a register communicatively coupled to the second frame buffer to cause the second portion of the second address range to be accessible by the first GPU.