Patent ID: 7714596

Claim:
A method of measuring sheet resistance and junction leakage associated with a semiconductor layer formed at a surface of a wafer, said method comprising the steps of: a) contacting a surface of a semiconductor layer with a plurality of probes in a predetermined mechanically distributed pattern, said plurality of probes being electrically coupleable to a computer system; b) first determining, by said computer system with respect to said plurality of probes, a sheet resistivity value for said semiconductor layer; c) second determining, by said computer system with respect to said plurality of probes, a junction leakage value associated with said semiconductor layer, said second determining step including the steps of: i) establishing a reverse bias voltage potential across a junction between said semiconductor layer and said wafer, wherein said reverse bias voltage potential is set at a predetermined voltage value; ii) measuring, through a first probe of said plurality of probes, a current conduction value for said junction; iii) measuring, through second, third and fourth probes of said plurality of probes, a plurality of voltage differential values, wherein said junction leakage value is computed based on said sheet resistivity value, said current conduction value, and said plurality of voltage differential values.