Patent ID: 7272056

Claim:
A method for controlling an output of data in a semiconductor memory device, the method comprising the steps of: i) detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay of the external clock signal; ii) analyzing data in an information storage unit, in which an internal timing is defined, based on values detected in step i), wherein step ii) includes the substeps of: storing a timing of an internal signal by using a ROM, in which a period of time required for generating a signal created by analyzing a read command from an input of an external clock is stored as a multiple of a unit delay timing: storing a read replica as a multiple of coarse unit delay (CUD) by using the ROM; and calculating cycles of lost DLL-clocks by using data stored in the ROM; and iii) adjusting a data output timing in accordance with predetermined CAS latency based on values analyzed in step ii).