Patent ID: 8531852

Claim:
A control system for at least one voltage converter having a plurality of cells in series wherein a module and phase components of an input voltage Vei relative to a frame of reference (d, q) are delivered to each cell, comprising an AC part and a DC part, characterized in that it includes a high speed current control loop relating to the AC part that delivers a control voltage Ve, and a lower speed voltage control loop relating to the cells that delivers an active power ψi, such that: Ψ i = C i 2 ⁢ ( 2 R pi ⁢ C i ⁢ Z i + ⅆ ⅆ t ⁢ Z i ⁢ ⁢ _ ⁢ ⁢ ref - K 1 ⁢ Zi ⁢ E Zi - K 2 ⁢ Zi ⁢ sign ⁡ ( E Zi ) ) where: K 1zi and K 2zi are positive adjustment gains; C i is a continuous capacitance of a capacitor Ci of each cell; R pi is losses associated with each cell; Z i — ref is a referenced value of Zi=(U DCi ) 2 , U DCi being a direct voltage across the capacitor C i ; and E Zi is such that E Zi =Z i −Z i — ref , in that a link between these two control loops is obtained via a consumption of active power in the cells representing an output of the lower speed control loop, in that it comprises means for obtaining a current reference i e — ref d for the high speed control loop, by effecting a summation Σψ i of the active power consumptions in N cells with i e ⁢ ⁢ _ ⁢ ⁢ ref d = ∑ i = 1 N ⁢ Ψ i - V e q ⁢ i e ⁢ ⁢ _ ⁢ ⁢ ref q V e d , and by making use of a phase locked loop on the control voltage V e , and including a module for error correction in the phase locked loop, such that the control voltage Ve, which is a total output voltage component (Ve) of the AC part, is given by the following equation: V e = V ePLL + K PLL ⁢ ∑ i = 1 N ⁢ ( ∫ 0 1 ⁢ E Zi ⁢ ⅆ t ) where: V ePLL is an output of the phase locked loop; K PLL ⁢ ∑ i = 1 N ⁢ ( ∫ 0 1 ⁢ E Zi ⁢ ⅆ t ) is a correction term; K PLL is an adjustment gain; and E Zi is an error in tracking a square of the DC voltage.