Patent ID: 8898494

Claim:
A processor comprising: an integrated circuit including: a first core; a cache memory; a communication bus coupled to the first core, the communication bus to connect the first core and the cache memory; a core workload monitor configured to determine a core workload for the first core; a bus workload monitor configured to determine a bus workload for the communication bus; and balancing control adapted to receive the bus workload from the bus workload monitor and to dynamically tune power allocation between the first core and the communication bus based on a power limit for the integrated circuit and a comparison between the bus workload and a bus workload threshold, the power limit corresponding to a maximum thermal dissipation capacity for the integrated circuit, wherein a power consumption of one of the first core and the communication bus is to be reduced, the power consumption reduction to be limited to maintain operation of the one of the first core and the communication bus above a low limit.