Patent ID: 8145880

Claim:
An integrated circuit comprising a microprocessor matrix of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch comprising: at least one data switch link register including a first matrix link-enable register field specifying a first link enable status for a corresponding link—of a plurality of inter-processor matrix links of said each matrix processor, and a second matrix link-enable register field specifying a second link-enable status for the corresponding link, wherein the first link enable status is an enabled or disabled status for the corresponding link for an entire inter-processor message category selected from a group consisting of broadcast messages and processor-to-processor messages, and wherein the first matrix link-enable register field includes at least one bit specifying an enabled or disabled status for the entire inter-processor message category for each for the plurality of inter-processor matrix links; and matrix routing logic connected to the at least one data switch link register and configured to route an inter-processor message through the matrix according to the first matrix link-enable register field.