Patent ID: 8319525

Claim:
A leakage current suppression circuit for detecting an output error caused by a leakage current flowing through at least a floating node of a D Flip-flop (DFF) and compensating for the leakage current so as to correct the output error, comprising: a detection circuit for receiving an output signal and a clock signal of the DFF, and detecting whether the output error has occurred, to generate a detection result; wherein the detection circuit comprises: a first pulse generator for generating a plurality of first pulses according to the clock signal; a second pulse generator for generating a plurality of second pulses according to the output signal; a first switch coupled between a first supply voltage and a detection node and turned on or off according to a voltage of the output signal; and a second switch coupled between a second supply voltage and the detection node and turned on or off according to voltages of the plurality of first pulses and the plurality of second pulses, wherein the detection circuit generates the detection result at the detection node according to on/off statuses of the first and second switches; and a compensation circuit for compensating for the leakage current according to the detection result to correct the output error.