Patent ID: 7446990

Claim:
An integrated circuit comprising: a plurality of I/O cells, each I/O cell of the plurality of I/O cells is one of a first type or of a second type, wherein: each I/O cell of the first type includes an ESD trigger circuit for detecting an ESD event; each I/O cell of the second type includes an ESD clamp device for providing a discharge path for discharging current from an ESD event in response to a detection of an ESD event by an ESD trigger circuit of an I/O cell of the first type, each I/O cell of the second type does not include an ESD trigger circuit to which the ESD clamp device of the I/O cell is responsive; wherein: each I/O cell of the first type has an active circuitry physical layout as per a first active circuitry floor plan, wherein for each I/O cell of the first type, circuitry of the ESD trigger circuit is located at a first designated area of the first active circuitry floor plan; each I/O cell of the second type has an active circuitry physical layout as per a second active circuitry floor plan, the first active circuit floor plan being of a same size and shape as the second active circuitry floor plan, wherein for each I/O cell of the second type, the ESD clamp device occupies a second designated area of the second active circuitry floor plan; wherein a location of the first designated area in the first active circuitry floor plan is a location that corresponds to a location of the second designated area in the second active circuitry floor plan.