Patent ID: 7994033

Claim:
A manufacturing method of a semiconductor apparatus, the method comprising steps of: forming a first conductive type first semiconductor region with an impurity concentration lower than that of a first conductive type semiconductor substrate on a first principal surface of the semiconductor substrate; forming a first mask layer on the first semiconductor region, the first mask layer having an opening part with a shape including a first region in which a plurality of islands are aligned with an interval and a second region in which each end of the plurality of islands of the first region are connected, in a plan view; injecting an impurity into the first semiconductor region from the opening part of the first mask layer and forming a second conductive type second semiconductor region which forms a PN junction with the first semiconductor region and thereafter removing the first masking, the second semiconductor region including a plurality of island portions and a connecting portion which connects ends of the plurality of island portions, in a plan view; forming a first electrode in contact with the second semiconductor region and the first semiconductor region; and forming a second electrode on a second principal surface of the semiconductor substrate.