Patent ID: 7333565

Claim:
A semiconductor integrated circuit for communication with a built-in reception circuitry of a direct down conversion formula provided with mixer circuits for demodulating I signals and Q signals by synthesizing signals of two oscillation frequencies differing in phase from each other into reception signals, and performing demodulation of reception signals of a plurality of frequency bands by changing over the frequency of said oscillation frequency signals, wherein first stage amplifier circuits for amplifying reception signals respectively matching said plurality of frequency bands are provided, said mixer circuits are provided at a stage subsequent to said first stage amplifier circuits as common circuits for reception signals of said plurality of frequency bands, and buffer circuits whose outputs take on high impedances in their unselected state while matching to said first stage amplifier circuits are provided between said first stage amplifier circuits and said mixer circuits, wherein a variable gain amplifier circuit having an offset canceling circuit is provided on the output side of said mixer circuits, and a dummy amplifier circuit and a dummy buffer circuit having respectively the same configurations as said first stage amplifier circuits and buffer circuits but not involved in the amplification of reception signals are provided on the output side of said mixer circuits, and wherein said offset canceling circuit is so configured as to perform offset calibration in a state in which the genuine first stage amplifier circuits for amplifying reception signals and buffer circuits are placed in an inactive state and said dummy amplifier circuit and dummy buffer circuit are in an activated state.