Patent ID: 8209522

Claim:
A hardware processor configured to execute an instruction, the hardware processor comprising: a first hardware register configured to store extraction information associated with a field, wherein the field is stored in a portion of a received packet; a parser configured parse the received packet to determine packet format information about the received packet; a combiner configured to combine the determined packet format information with field format information associated with the field to generate the extraction information stored in the first hardware register; a pair of hardware registers that combine to hold the received packet, wherein each register of the pair holds a portion of the received field; a second hardware register configured to store an extracted portion of data from the received packet, wherein the extracted portion corresponds to the field; an opcode identifier configured to identify the instruction; and an argument receiver configured to receive: a first argument designating the first hardware register; a second argument designating the pair of hardware registers; and a third argument designating the second hardware register, wherein the hardware processor is configured to cause an extraction of any portion of the field from the pair of hardware registers based on the extraction information stored in the first register and place the extracted portion of the field into the second register.