Patent ID: 7673203

Claim:
An interconnect delay fault test (IDFT) controller generating a control signal for testing an interconnect delay fault of a boundary scan cell using an IEEE 1149.1 specification, wherein the controller comprises: a logic unit that generates the control signal comprising an update signal and a capture signal to carry out an update and a capture based on a system clock signal within one interval of the system clock signal in the boundary scan cell by receiving a data register shift signal, a data register update signal and a data register clock signal of the IEEE 1149.1 specification, and wherein the logic unit comprises: a first AND logic for carrying out an AND operation of an IDFT control mode signal indicating a normal mode or an IDFT mode, and an inverted data register shift signal; a second AND logic for carrying out an AND operation of the IDFT control mode signal and the data register update signal; a third AND logic for carrying out an AND operation of the IDFT control mode signal and the system clock signal; a first flip-flop for carrying out a flip-flop operation of an output signal of the second AND logic using an output signal of the third AND logic as a clock signal to output an IDFT_UpDR signal: a second flip-flop for carrying out a flip-flop operation of an output signal of the first flip-flop using an output signal of the third AND logic as the clock signal to output an IDFT_CapDR signal; a first multiplexer for multiplexing the data register update signal and the IDFT_UpDR signal based on the IDFT control mode signal to output the update signal; and a second multiplexer for multiplexing the data register clock signal and the IDFT_CapDR signal based on an output signal of first AND logic to output the capture signal.