Patent ID: 7432597

Claim:
A semiconductor device, comprising: a semiconductor substrate; a memory region provided on said semiconductor substrate; and a logic region provided on said semiconductor substrate; wherein said memory region includes: a first transistor provided on said semiconductor substrate, a first insulating layer covering said first transistor, a plurality of first conductive plugs connected to a diffusion layer of said first transistor and terminated on an upper surface of said first insulating layer, a capacitor element provided on said first insulating layer, and a bit line provided on said first insulating layer; wherein said logic region includes: a second transistor provided on said semiconductor substrate and covered with said first insulating layer, a plurality of second conductive plugs connected to a diffusion layer of said second transistor and terminated on an upper surface of said first insulating layer, and an upper interconnect provided on said second conductive plug; wherein said plurality of second conductive plugs includes a plug connected to said upper interconnect via at least one conductive plug; and wherein said plurality of first conductive plugs includes a plug connected to said capacitor element, a plug connected to said bit line, and an isolated plug connected neither to said capacitor element nor to said bit line.