Patent ID: 8873553

Claim:
A switch system, comprising a layer 2 switching processor and a plurality of line cards connected to said layer 2 switching processor, said plurality of line cards including at least one representative line card: wherein each line card excluding said representative line card comprises: an FDB table having FDB information entried therein; a packet processing unit that, when the FDB information of a received packet has not been entried into said FDB table of the line card, transmits a learning notification including said FDB information to said representative line card via said layer 2 switching processor; and an updating unit that receives the learning notification including the FDB information coming from said representative line card via said layer 2 switching processor, and updates said FDB table of the line card; and wherein said representative line card comprises: an FDB table having the FDB information entried therein; and a learning unit that receives the learning notification coming from said line card via said layer 2 switching processor, determines whether the FDB information of said learning notification has been entried into said FDB table of the representative line card, updates the FDB table of the representative line card when said FDB information has not been entried, and transmits the learning notification including said FDB information to the other line cards via said layer 2 switching processor with a multicast; wherein said learning unit of the representative line card controls a flow rate of said learning notification; and wherein said learning unit of the representative line card comprises an FDB buffer for accumulating the learning notifications coming from the other line cards, and controls a flow rate of the learning notification by said FDB buffer so that the learning notification can be processed.