Patent ID: 7312117

Claim:
A method of manufacturing a semiconductor device, comprising: forming word line structures in a first direction on a substrate of which an active region is defined; forming source/drain regions in the active region at both sides, respectively, of the word line structures; forming a first insulating interlayer on the substrate having the word line structures; forming first and second contact pads through the first insulating interlayer to allow the first and second contact pads to contact the source/drain regions, respectively; forming a second insulating interlayer on the substrate having the first and second contact pads; forming bit line structures in a second direction substantially perpendicular to the first direction on the second insulating interlayer to allow the bit line structures to contact the first contact pad, the bit line structures being substantially perpendicular to the word line structures; forming an insulation layer structure on the second insulating interlayer; patterning the insulation layer structure to form storage node contact holes between the bit line structures, the storage node contact holes having a lower portion and an upper portion wider than the lower portion, and the upper portion of the storage node contact holes extending in the second direction and having a side face substantially perpendicular to the first direction; filling the storage node contact holes with a conductive material to form storage node contact plugs; and forming storage node electrodes on the storage node contact plugs.