Patent ID: 7038491

Claim:
A programmable level shifter, comprising: a first P-type FET coupled between a first power line and an output node; a first N-type FET coupled between the first P-type FET and a second power line; a second P-type FET coupled between the first power line and a gate electrode of the first P-type FET, having a gate electrode coupled to the output node; a second N-type FET coupled between a gate electrode of the first P-type FET and an inverted input node, having a gate electrode coupled to a third power line; a third P-type FET having a first electrode, a second electrode coupled to the first electrode thereof, and a gate electrode coupled to the inverted input node; a fourth P-type FET coupled between the gate electrode of the second N-type FET and the third P-type FET, having a gate electrode coupled to the inverted input node; a fifth P-type FET coupled between a gate electrode of the first N-type FET and the third P-type FET, having a gate electrode coupled to a non-inverted input node; a third N-type FET coupled between the fifth P-type FET and the second power line, having a gate electrode coupled to the non-inverted input node; a sixth P-type FET coupled between the third N-type FET and the inverted input node, having a gate electrode thereof coupled to the non-inverted input node; and a programmable device coupled between the first power line and the output node, comprising at least a seventh P-type FET; wherein the programmable device can be programmed to determine whether the seventh P-type FET is connected in parallel with the first P-type FET to change an effective resistance between the first power line and the output node when the first P-type FET is turned on.