Patent ID: 8151089

Claim:
An array-type processor, comprising: a multiplicity of processor elements which individually execute data processing and supply event data as output in accordance with instruction codes for which data are individually set, said multiplicity of processor elements being arranged in rows and columns; a plurality of state control units that intercommunicate to realize linked operation as necessary; and an event distributing means for distributing said event data to said plurality of state control units, said event distributing means comprising dedicated event communication lines that connect said plurality of state control units, wherein said instruction codes of said multiplicity of processor elements are successively switched by said plurality of state control units in accordance with a computer program that has been installed in advance and in accordance with said event data, and wherein said plurality of state control units comprises at least four state control units that are directly interconnected to each other by respective dedicated event communication lines so that each of said at least four state control units is directly connected to all other ones of said state control units.