Patent ID: 6903957

Claim:
A read only memory (ROM) embedded dynamic random access memory (DRAM) device, comprising: a DRAM array comprising first volatile memory cells; and a half density ROM array comprising: a plurality of memory cell pairs arranged in rows and columns, each memory cell pair comprising a hard programmed non-volatile cell and an unprogrammed volatile cell; a plurality of word line pairs, each word line pair connected to a row of the plurality of memory cell pairs, a first word line connected to access the hard programmed non-volatile cell and a second word line connected to access the unprogrammed volatile cell; a plurality of complementary digit line pairs; sense amplifier circuitry coupled to the plurality of digit line pairs, each digit line pair connected to couple a column of the plurality of memory cell pairs to the sense circuitry, a first digit line of the digit line pair connected to the hard programmed memory cell and a second digit line of the digit line of the pair connected to the unprogrammed dynamic memory cell; and access circuitry to couple one of the non-volatile memory cells and one of the second dynamic memory cells to the differential digit lines in response to a pair of word line signals.