Patent ID: 7161841

Claim:
A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprising: providing an FPGA having a core containing a plurality of n-channel non-volatile memory cell interconnect switches, each switch formed in a switch p-well region and coupled to a source/drain of an n-channel MOS transistor formed in a grounded p-well region disposed within a n-well and electrically isolated from the switch p-well region; selecting at least one non-volatile memory cell interconnect switch for erasing; disconnecting from ground the switch p-well region and the source of the n-channel MOS transistor associated with the at least one non-volatile memory cell; and applying a V CC potential to the source/drain of the n-channel transistor to which the non-volatile memory cell is coupled, applying a potential of at least VCC to the n-well containing the non-volatile memory transistor, and applying an erase potential to the gate of the selected non-volatile memory cell interconnect switch.