Patent ID: 8483350

Claim:
A shift register comprising a plurality of serially-coupled shift register units, an Nth stage shift register unit among the plurality of shift register units comprising: an input end for receiving an input voltage; an output end for outputting an output voltage; a node; a pull-up driving circuit for transmitting the input voltage to the node; a pull-up circuit for providing the output voltage according to a first clock signal and the input voltage so that the output voltage is at a first voltage level during a driving period of the Nth stage shift register unit, wherein the first clock signal switches between the first voltage level and a second voltage level with a predetermined frequency and the first voltage level is higher than the second voltage level; a pull-down circuit for maintaining the output voltage at a third voltage level during a period excluding the driving period of the Nth stage shift register unit, wherein the third voltage level is higher than the second voltage level; and a fast pull-down circuit for maintaining a voltage level of the node or the output end according to a feedback voltage so that the output voltage is at the second voltage level during a driving period of an (N+1)th stage shift register unit among the plurality of the shift register units; wherein the fast pull-down circuit comprises: a first switch including: a first end coupled to the node; a second end for receiving a voltage having the third voltage level; and a control end for receiving the feedback voltage; and a second switch including: a first end coupled to the output end; a second end for receiving the first clock signal; and a control end coupled to the control end of the first switch.