Patent ID: 7035156

Claim:
A semiconductor memory device having a data-input/output mode and a refresh mode as an access operation to a memory cell, comprising: a mode discriminating circuit for discriminating between the data-input/output mode and the refresh mode at every operation cycle constituted by, as one unit, an operation period for carrying out the access operation and a stand-by period from an end of the operation period to a start of a next operation period; a switching control circuit for outputting a switching control signal in the operation period after a start of the operation cycle only in a case where an operation mode discriminated by the mode discriminating circuit is different from an operation mode in the former operation cycle; and an address switching circuit for switching a connection to a decoding circuit at every output of the switching control signal, while one of external address used in the data-input/output mode and a refresh address from a refresh address counter used in the refresh mode is always connected to the decoding circuit.