Patent ID: 7464018

Claim:
A data processor integrated circuit comprising: a data processor ( 210 ) generating trace data; a trace data collection unit ( 230 ) connected to said data processor and receiving said trace data; a trace data export unit ( 240 ) connected to said trace data collection unit including at least one trace data first-in-first-out buffer, said trace data export unit operable to determine when a trace data first-in-first-out buffer is in danger of overflowing; upon determination that the trace data first-in-first-out buffer is in danger of overflowing stalling a predetermined number of pipeline stages in the pipeline following a first pipeline stage, inhibiting a central processing unit of the data processor from beginning a new instruction, transmitting data from the trace data first-in-first-out buffer while the pipeline is stalled; during any interval between stalling the predetermined number of pipeline stages and when the central processing unit is inhibited from beginning a new instruction, buffer in a first-in-first-out buffer any received asynchronous trig ger events, and before restarting the predetermined number of pipeline stages, transmit data from the trace data first-in-first-out buffer corresponding to the received asynchronous events.