Patent ID: 7514321

Claim:
A method of making a monolithic, three dimensional array of semiconductor devices, comprising: forming a plurality of second semiconductor pillar active regions in a second device level, wherein the second semiconductor pillar active regions are separated from each other by insulating material regions; epitaxially growing a first semiconductor layer on the second semiconductor pillar active regions and on the insulating material regions, such that grain boundary regions in the first semiconductor layer are located over the insulating material regions; planarizing the first semiconductor layer; patterning the first semiconductor layer into a plurality of first strips extending in a first direction; forming a first insulating layer between the plurality of first strips; patterning the first semiconductor layer to remove the grain boundary regions and to leave a plurality of substantially single crystal first semiconductor pillar active regions in a first device level by patterning the plurality of first strips and the first insulating layer to form the plurality of the first semiconductor pillar active regions; forming a first charge storage dielectric film in spaces between the first semiconductor pillar active regions, wherein the first charge storage dielectric film comprises one or more trenches; and filling the trenches in the first charge storage dielectric film with first word lines; wherein the array of semiconductor devices comprises an array of vertical NAND strings.