Patent ID: 8117473

Claim:
A noise reduction apparatus of a dynamic power management processor, the apparatus comprising: a mode setting unit configured to detect a use state of a processor and to set an operation mode of the processor; and a power supply unit configured to supply a voltage corresponding to the operation mode set by the mode setting unit, wherein the mode setting unit is configured to change the operation mode of the processor periodically between a sleep mode and a low frequency mode in response to receiving a periodically generated signal during the sleep mode of the processor, wherein the low frequency mode includes a low frequency mode voltage and a low frequency mode clock frequency respectively lower than a general mode voltage and a general mode clock frequency and respectively higher than a sleep mode voltage and a sleep mode clock frequency, and wherein, if usage of the processor is higher than a certain value while the operation mode is periodically changed between the sleep mode and the low frequency mode, the operation mode returns to a general operation mode.