Patent ID: 7170522

Claim:
A combined image processing circuit comprising: a first image processing circuit and a second image processing circuit serially connected to one another, each image processing circuit comprising: a plurality of line buffers, each line buffer storing pixel data of a plurality of pixels as line data, said plurality of pixels configuring a single image line of an image; a first image processing part performing a first image processing task on original image data provided from the exterior by using the line data stored in at least one of said plurality of line buffers, and providing processed image data; a second image processing part performing a second image processing task on the processed image data provided from said first image processing part by using the line data stored in at least one of said plurality of line buffers, and providing processed image data; a line buffer selector that selectively connects said first image processing part and said second image processing part to any number of line buffers among said plurality of line buffers; a first output path selector that selects one of an output path that skips the first image processing task and an output path that performs the first image processing task; and a second output path selector that selects one of an output path that skips the second image processing task and an output path that performs the second image processing task, wherein the first image processing circuit and the second image processing circuit are identical in structure.