Patent ID: 7754551

Claim:
A method for making very low V t metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions, characterized in that the method uses a low-temperature shallow junction process to lower the interface reaction of CMOSFETs under fabrication processes, which temperature is lower than 900° C., including the steps as follows: A. Apply high-κ gate dielectric deposition, post-deposition anneal, and dual metal-gates deposition; B. Apply gate patterning, wherein self-aligned Ga or Ni/Ga with top capping layer was deposited for p-MOS, followed by 550˜900° C. RTA solid-phase diffusion (SPD); C. For n-MOS, self-aligned H 3 PO 4 was spun deposited, transformed to P 2 O 5 at 200° C. and SPD at 850˜900° C. RTA; alternatively similar to p-MOS case, Ni/Sb with top in capping layer was deposited, followed by 600˜700° C. RTA SPD.