Patent ID: 7808046

Claim:
An electrostatic protection device for a semiconductor circuit comprising: a semiconductor substrate having a well formed therein; at least two sets of transistor fingers formed in at least two predetermined areas spaced apart from each other of the semiconductor substrate, each transistor finger among a set of transistor fingers extending in a first direction along the substrate and having a first end and a second end opposite the first end, each set of the transistor fingers comprising: a plurality of gates arranged in parallel with respect to each other in one direction; and a plurality of sources and drains, wherein one source and one drain are alternately arranged at each side of each gate in the semiconductor substrate; a well pickup surrounding each set of the transistor fingers such that any two sets of the transistor fingers are separated by a portion of the well pickup; and metal wires disposed in a second direction separated from each other by a distance along the first direction, the metal wires connected to at least two portions of each of the drains and connected to an input/output pad to which electrostatic discharge (ESD) excessive current is introduced, wherein the ESD excessive current is introduced to each of the drains through the metal wires.