Patent ID: 7890823

Claim:
An electrical package comprising: an external input portion; an external output portion; a plurality of integrated circuits that is compatible with a compressed deterministic pattern test, each of the integrated circuits including: an input portion; a decompressor that is connected to a part of the input portion; scan chains that are connected to the decompressor; a compactor that is connected to the scan chains; a selector that is connected to the compactor and the part of the input portion to selectively output an output of the compactor or an output of the part of the input portion; and an output portion that is connected to the selector, wherein the integrated circuits are serially connected so that the output portion of the integrated circuit is connected to the input portion of the subsequent integrated circuit to form a sequential path, wherein the input portion of the integrated circuit configuring an initial stage of the sequential path is connected to the external input portion; and wherein the output portion of the integrated circuit configuring a final stage of the sequential path is connected to the external output portion.