Patent ID: 7613982

Claim:
A data processing apparatus for a flash memory comprising: a user request unit which issues a request for performing a data operation on a flash memory using a logical address; a conversion unit which converts the logical address into a physical address; and a control unit which performs the data operation on the physical address and writes inverted data to an inverted data region of the flash memory, the inverted data used to indicate whether an extracted ECC is erroneous, wherein, before performing the data operation, the control unit obtains the inverted data and loads the inverted data into a buffer by inverting generated error correction code (ECC) loaded in the buffer, the generated ECC corresponding to data loaded in the buffer which is to be used in the data operation, and wherein, while performing the data operation, the control unit writes the inverted data from the buffer to the inverted data region of the flash memory, and writes the generated ECC from the buffer to an ECC region of the flash memory to be extracted from the ECC region as the extracted ECC, the inverted data and the extracted ECC being mutually exclusive of each other.