Patent ID: 8274112

Claim:
A semiconductor memory device, comprising: rows and columns of active pillar structures comprising semiconductor material, each of the active pillar structures protruding from a surface of the device, wherein odd and even rows of the active pillar structures are alternately disposed in a first direction, odd and even columns of the active pillar structures are alternately disposed in a second direction, the odd rows and the even columns of the active pillar structures each consist of a plurality of first ones of the active pillar structures, the even rows and the odd columns of the active pillar structures each consist of a plurality of second ones of the active pillar structures, and the columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures; buried bit lines each extending longitudinally in the first direction, and each of the buried bit lines electrically connected to the first pillar structures which make up one of the even columns of the active pillar structures and to the second active pillar structures which make up an adjacent one of the odd columns of the active pillar structures, and electrically connected to the first and second active pillar structures at lower portions thereof; first gate patterns each extending longitudinally in the second direction and respectively enclosing central portions of the first active pillar structures which make up one of the odd rows of the active pillar structures; and second gate patterns each extending longitudinally in the second direction and respectively enclosing central portions of the second active pillar structures which make up one of the even rows of the active pillar structures, wherein the first and the second gate patterns are spaced apart from each other in the first direction by intervals each smaller than respective widths of the first gate patterns and respective widths of the second gate patterns.