Patent ID: 8823415

Claim:
A logic gate, comprising: a first input terminal, receiving a first input logic value of the logic gate; a second input terminal, receiving a second input logic value of the logic gate; an output terminal, outputting a logic operation result of the logic gate; a first resistive non-volatile memory device; and a second resistive non-volatile memory device, wherein a bottom electrode of the first resistive non-volatile memory device and a bottom electrode of the second resistive non-volatile memory device are respectively coupled to the first input terminal and the second input terminal of the logic gate when a top electrode of the first resistive non-volatile memory device and a top electrode of the second resistive non-volatile memory device are coupled to the output terminal of the logic gate, and the top electrode of the first resistive non-volatile memory device and the top electrode of the second resistive non-volatile memory device are respectively coupled to the first input terminal and the second input terminal of the logic gate when the bottom electrode of the first resistive non-volatile memory device and the bottom electrode of the second resistive non-volatile memory device are coupled to the output terminal of the logic gate.