Patent ID: 7557801

Claim:
A display device comprising: a plurality of pixels; a decoder for selecting one or more of memory circuits in each of the plurality of pixels, wherein the decoder is electrically connected to the plurality of the pixels; an address latch circuit for holding a potential of an address data or updating the potential of an address data, wherein the address latch circuit is electrically connected to the decoder; an address controller for being input a synchronous signal, and outputting an address data, wherein the address controller is electrically connected to the address latch circuit; an image data latch circuit for holding a potential of an image data or updating a potential of an image data, wherein the image data latch circuit is electrically connected to the plurality of the pixels; a write control circuit for outputting write control signals of an address data and an image data, wherein the write control circuit is electrically connected to the image data latch circuit, the address latch circuit and the address controller; and a display control circuit for inputting a display control signal to the respective pixels, wherein the display control circuit is electrically connected to the plurality of the pixels and the write control circuit.