Patent ID: 7268402

Claim:
A memory cell, comprising: a capacitor; a trench-isolated transistor having a gate, a drain and a source, the source being coupled to one terminal of the capacitor, the trench-isolated transistor including first and second isolation trenches each disposed on a respective side of a portion of semiconductive material, the first and second isolation trenches each comprising: a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductive material at a first angle other than ninety degrees, the first sidewall comprising a segment which is substantially straight linear, the first sidewall not being substantially straight linear along an entirety of its length; a second isolation trench portion within and extending below the first isolation trench portion, the second isolation trench portion having a second depth and including a second sidewall intersecting the first sidewall at a second angle with respect to the surface that is greater than the first angle and is other than ninety degrees, the second isolation trench portion having a bottom portion at the second depth of the semiconductive material, the semiconductive material at the bottom portion being doped relative adjacent portions of the semiconductive material; and a dielectric material filling the first and second isolation trench portions.