Patent ID: 7279987

Claim:
An arrangement for simulating a phase locked loop, comprising: a behavioral model for simulating a phase locked loop as a set of behavioral blocks based upon a high level description language; a loop filter model, used by the behavioral model, the loop filter model being implemented as a series of integrators based on a transfer function for creating a loop voltage for generating phase adjustments; and a digital simulator for outputting a prediction of a response of the phase locked loop, wherein the digital simulator simulates the behavioral model that produces a number value and simulates the loop filter model that processes the number value with the series of integrators, wherein the behavioral model comprises: a voltage controlled oscillator model for generating a signal allowing a phase indication signal to be created; a phase/frequency detector model for comparing a phase of a reference signal and the phase indication signal and producing phase adjustment control signals; and a charge pump model for producing the number value of a signal representing a magnitude and direction of an output current, and wherein the voltage controlled oscillator model includes an integrator that begins at an initial VCO value and changes until the VCO value equals the loop voltage, the voltage controlled oscillator model generating an output clock having a different state.