Patent ID: 8772827

Claim:
A semiconductor device, comprising: a first-conductivity-type semiconductor layer including an active region in which a transistor having a plurality of impurity regions is formed, and a marginal region surrounding an outer periphery of the active region; a second-conductivity-type channel layer formed between the active region and the marginal region so as to form a front surface of the semiconductor layer; at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer; a gate insulation film formed on an inner surface of the at least one gate trench; a gate electrode formed inside the gate insulation film in the at least one gate trench; at least one isolation trench arranged between the active region and the marginal region to surround the outer periphery of the active region, and formed to extend from the front surface of the semiconductor layer through the channel layer, the at least one isolation trench having a depth equal to a depth of the at least one gate trench; an inter-layer insulation film formed on the semiconductor layer; a first terminal formed on the inter-layer insulation film and connected to the gate electrode through the inter-layer insulation film; a bonding wire; and a second terminal formed on the inter-layer insulation film and connected to one of the impurity regions of the transistor through the inter-layer insulation film, wherein the at least one isolation trench is positioned directly below the second terminal, and the second terminal is formed to cover the active region, and the first terminal includes a gate pad to which the bonding wire is connected, and when seen in a plan view, the gate pad surrounds an outer periphery of the second terminal, and the at least one isolation trench bypasses the gate pad.