Patent ID: 7215569

Claim:
A semiconductor integrated circuit device comprising: a first transistor formed on a bulk substrate region in a semiconductor substrate and having a source or drain layer connected to a first reference voltage; and a second transistor including an impurity layer region formed on the bulk substrate region and being of a conductivity type different from that of the bulk substrate region, a semiconductor region formed on the impurity layer region and being of a conductivity type the same as that of the bulk substrate region, a source layer and a drain layer formed in the semiconductor region and being of a conductivity type different from that of the bulk substrate region, a gate insulating film provided between the source layer and the drain layer and formed on the semiconductor region, a gate electrode formed on the gate insulating film, and a body region surrounded by the source layer, the drain layer, the impurity layer region, and the gate insulating film on a section along a source-drain direction and being of a conductivity type the same as that of the bulk substrate region, the impurity layer region being depleted, wherein the source layer or the drain layer of the second transistor is connected to the first reference voltage through the first transistor.