Patent ID: 7269807

Claim:
A program stored in a computer-readable medium which generates a pattern of a semiconductor integrated circuit device, the program causing a computer to execute: a first step of calculating a pattern area ratio of a semiconductor integrated circuit device or a pattern occupancy ratio in a cheek window set for the semiconductor integrated circuit device on an assumption that a dummy pattern defined by a process condition is virtually placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region of each instance provided in the semiconductor integrated circuit device without actually placing the dummy pattern; a second step of verifying whether or not the pattern area ratio or the pattern occupancy ratio has attained a predetermined target value, wherein if the pattern area ratio or the pattern occupancy ratio has not attained the predetermined target value, a generation specification for the dummy pattern is changed within a range that complies with a process rule; a third step of calculating the pattern area ratio or the pattern occupancy ratio on an assumption that a dummy pattern generated with changed generation specification in the second step is virtually placed in the unoccupied region of the semiconductor integrated circuit device or in the unoccupied region of the each instance without actually placing the dummy pattern; and a fourth step of verifying whether or not the pattern area ratio or the pattern occupancy ratio has attained the predetermined target value; and a fifth step of actually placing a dummy pattern which attains the predetermined target value in the unoccupied region of the semiconductor integrated circuit device or in the unoccupied region of the each instance based on the result of the second step or the fourth step.