Patent ID: 7680282

Claim:
A signal processing circuit comprising: a plurality of basic circuits connected in series, each of said basic circuits including: an arithmetic circuit to receive a first input signal and a second input signal, calculate a third signal based on said first input signal and said second input signal, and make the third signal available; a first selection circuit to output one of said first input signal and said third signal as a first output signal; and a second selection circuit to output one of said second input signal and said third signal as a second output signal, wherein said first output signal of said first selection circuit is supplied as an input signal to a second basic circuit of a succeeding stage of said signal processing circuit, as viewed from an input side of said signal processing circuit, and said second output signal of said second selection circuit is supplied as an input signal to a third basic circuit of a preceding stage of said signal processing circuit, as viewed from the input side of said signal processing circuit.