Patent ID: 8664766

Claim:
A semiconductor structure comprising: a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on said first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein said conductively filled via is in contact with an exposed surface of the at least one conductive feature of said first interconnect level by an anchoring area, said conductively filled via is separated from said second dielectric material by a first diffusion barrier layer, and said conductively filled line is separated from said second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to said conductively filled line, and wherein said first diffusion barrier layer is present only on sidewalls of said second dielectric material and said dielectric capping layer within said at least one conductively filled via and only on some portions of an exposed upper surface of the at least one conductive feature, and wherein said second diffusion barrier layer is in direct contact with a sidewall of said second dielectric material in said at least one conductively filled line and is present in said at least one conductively filled line that is located above said conductively filled via, but absent from said at least one conductively filled via, and wherein an upper surface of said conductively filled line is coplanar with an upper surface of the second dielectric material.