Patent ID: 6909196

Claim:
An integrated circuit semiconductor device having a bonding pad region of a multilayered wiring structure, comprising: at least n, where n ≧3 wiring layers in electrical contact with one another, including an uppermost wiring layer at metal level M(n) and a lowermost wiring layer at metal level M 1 , and n−1 interlevel dielectric (ILD) layers, one ILD layer between every two wiring layers; the uppermost wiring layer at metal level M(n), containing a metal bond pad capable of making electrical connections outside the device, and formed on a top surface of an uppermost ILD layer; a second wiring layer at metal level M(n−1 ) including a solid metal pad underlying an entirety of the metal bond pad; and the lowermost wiring layer at metal level M 1 , containing a metal pad having an area less than 30% of an area of the metal bond pad, and formed at a bottom surface of a lowermost RD layer.