Patent ID: 8245060

Claim:
A system comprising: a plurality of memory regions, each of said memory regions having at least a low power state and a high power state; a controller to manage the power states of said memory regions separately and independently; a performance monitor to measure a performance characteristic of memory objects in each of said memory regions; a processor to manage memory contents by a method comprising: monitoring each of a plurality of memory objects to determine an access frequency for each of said memory objects; monitoring each of said plurality of memory objects to determine said performance characteristic for each of said memory objects; identifying a first memory region as a candidate for low power operation; determining an optimized location for at least a subset of said plurality of memory objects, said optimized location being determined based on said performance characteristic; from said optimized location, identifying a first memory object as a low frequency access object; moving said first memory object to said first memory region; and operating said first memory region in said low power state.