Patent ID: 7437529

Claim:
In a data processing system, a method comprising: determining when a large virtual page of memory is required; identifying a target memory location comprising a plurality of small virtual pages for coalescing as the large virtual page, wherein said identifying does not reject selection of a target memory location that includes one or more of DMA-mapped pages and pinned pages and pages that are pre-translated for DMA; performing a first phase page promotion to move one or more smaller pages that are of a first type from within a target memory location to another memory location, wherein the first type is a small virtual page that is being utilized and is not a pinned page or a DMA-mapped page, and wherein the target memory location has a range of contiguous address space that is sufficient for the large virtual page; when the first phase page promotion fails to provide sufficient contiguous, small, free virtual pages to combine into the large virtual page and there exist at least one page of a second type, regardless of the number of first type pages that were promoted from within the target memory location, dynamically and automatically implementing a second phase page promotion to move one or more small pages that are of the second type from within the target memory location to another memory location, such that sufficient contiguous small, unused virtual pages are available for combining into the large virtual page, wherein the second type is a small virtual page that is one of a pinned page or a DMA-mapped page or a page that is pre-translated for DMA; re-ordering an associated page address directory to account for the new memory location of each small virtual page moved to another memory location; and providing an address within the page address directory for the large virtual page created.