Patent ID: 7643981

Claim:
A computer system for determining whether a pulse is wide enough to serve as a clock to a latch, the computer system comprising: a memory; a circuit simulated in the memory; and a processor coupled to the memory, wherein the circuit simulated in the memory comprises a clock chopper block and a latch, wherein the clock chopper block provides a clock input to the latch; wherein the clock chopper block comprises an inverter and a NOR gate, wherein the inverter receives a first signal as an input and provides a second signal as an output, wherein the NOR gate receives the first signal and second signal as inputs and provides a third signal as an output, and wherein the third signal is provided as the clock input to the latch; wherein a falling transition of the first signal causes a rising transition of the third signal after a first delay and wherein the falling transition of the first signal causes a rising transition of the second signal that causes a falling transition of the third signal after a second delay; wherein the processor is programmed to capture, responsive to the falling transition of the first signal, the rising transition of the third signal and the falling transition of the third signal; wherein the processor is programmed to determine the first delay and the second delay; wherein the processor is programmed to determine a pulse width of the third signal based on the first delay and the second delay; and wherein the processor is programmed to determine whether the pulse width of the third signal is wide enough to serve as the clock input to the latch.