Patent ID: 8761325

Claim:
An apparatus for sampling a received digital data signal comprising: a clock generator to generate a clock signal having a phase; a first phase shifter coupled to the clock generator to continuously adjust the phase of the clock signal; a first sampler coupled to the first phase shifter to sample the received signal responsive to the clock signal as phase-adjusted by the first phase shifter; a controller coupled to the first sampler and configured to dither the phase of the clock signal to dynamically maximize the vertical eye opening of the received signal at a sampling time, wherein the controller is configured to determine the vertical eye opening by determining a first signal value that a first predetermined proportion of samples are below and a second signal value that a second predetermined proportion of signal values are below and determine the difference between the first and second signal values; a second phase shifter coupled to the clock generator to adjust the phase of the clock signal; and a second sampler coupled to the second phase shifter to sample the received signal responsive to the clock signal as phase-adjusted by the second phase shifter at the sampling time when the vertical eye opening is maximized to produce an output signal.