Patent ID: 7777269

Claim:
A memory circuit comprising a NAND-type memory string, the NAND-type memory string comprising: a bit line contact; a source contact; a plurality of dual-gate memory cells serially connected by source/drain regions, wherein (a) a first source/drain region at one end of the serially connected dual-gate memory cells is selectably, electrically coupled to the bit line contact and a second source/drain region at another end of the serially connected dual-gate memory cells is selectably, electrically coupled to the source contact, and wherein (b) the dual-gate memory cells each comprise: a memory device having a channel region provided on a first surface of a polycrystalline semiconductor layer; and an access device having a channel region provided on a second surface of the polycrystalline semiconductor layer, wherein a thickness of the polycrystalline semiconductor layer is provided such that a sensitivity parameter between the access device and the memory device is less than a predetermined value and wherein the sensitivity parameter being the magnitude of the ratio of the change in the access gate threshold voltage and an applied voltage on the memory device.