Patent ID: 8665632

Claim:
A semiconductor memory device, comprising: a memory cell array including a memory cell layer, said memory cell layer containing plural first lines, plural second lines intersecting said first lines, and plural memory cells provided at the intersections of said plural first lines and second lines, wherein said memory cell has asymmetrical voltage-current characteristics on application of a voltage of a first polarity and on application of a voltage of a second polarity different from said first polarity, wherein said memory cell has a first state, and a second state and a third state of higher resistances than that in said first state, wherein said memory cell, (1) in said second state, makes a transition to said first state on application of a first voltage of said first polarity, (2) in said first state, makes a transition to said second state on application of a second voltage of said second polarity, (3) in said first state, makes a transition to said third state on application of a third voltage of said second polarity (the third voltage<the second voltage), and (4) in said third state, makes a transition to said first state on application of a fourth voltage of said first polarity (the fourth voltage<the first voltage).