Patent ID: 8407572

Claim:
A Viterbi decoder capable of effectively reducing the amount of memory used in operations, comprising: a survival memory unit, comprising a plurality of banks, for storing a plurality of survivor metrics corresponding to a plurality of states into a writing column of a writing bank of the plurality of banks according to a writing bank sequence and a writing column sequence in alternating intervals of a clock; and a trace back unit, coupled to the survival memory unit, for reading a reading column of each bank of the plurality of banks not performing storing operations according to a reading bank sequence and a reading column sequence in reverse to the writing bank sequence and the writing column sequence in every interval of the clock, comprising: a plurality of trace back elements, each for reading a survivor metric corresponding to the first trace back state in a first reading column according to a first trace back state, to output a second trace back state to another trace back element; and an interval selector, for skipping operations of one trace back element in alternating intervals of the clock.