Patent ID: 8063896

Claim:
A display device, comprising: a display panel having a data line; and a source driver coupled to said panel, said source driver including a control circuit and an amplifier, said amplifier being coupled to said data line to supply a data signal with an offset voltage, said amplifier being responsive to a control signal from said control circuit to invert a polarity of said offset voltage, wherein said control circuit generates said control signal in response to a pattern select signal, a gate start pulse signal, and a strobe signal indicative of a cycle of inversion of the polarity of said offset voltage, wherein the source driver is configured to drive said display panel in a 2H inverted drive, wherein said polarity of said offset voltage of said amplifier during said 2H inverted drive is inverted for every one horizontal line in response to said pattern select signal, wherein the display device further comprises a gate driver for scanning gate lines in the display panel, wherein the gate start pulse signal is supplied to the gate driver for initiating the scan by the gate driver, wherein the source driver comprises: a plurality of registers sequentially receiving display data from an external source; a plurality of latches responsive to the strobe signal to latch the display data from the registers simultaneously; and a driver circuit for driving the data lines in response to the display data latched in the latch circuits, and wherein the control circuit comprises: a first divider circuit dividing the gate start pulse signal to generate ¼ divided gate start pulse signal; a second divider circuit dividing the strobe signal to generate ¼ divided strobe signal and ½ divided strobe signal; a first selector circuit in response to the pattern select signal to select either the ¼ divided strobe signal or the ½ divided strobe signal; and a second selector circuit in response to an output of the first selector circuit for outputting the ¼ divided gate start pulse signal or the inverted signal of the ¼ divided gate start pulse signal.