Patent ID: 8009783

Claim:
An interface for transmission of a synchronous digital input signal composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency, said interface comprising at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel, the output samples being transmitted at a second clock frequency, integer multiple N of a third frequency, said third frequency being substantially equal to the first frequency, each sampled bit being substantially composed of N samples, a serial input signal giving M parallel signals, wherein said interface comprises an electronic device for frequency-locking the third frequency onto the first clock frequency, said device comprising: means for counting the number of samples composing each sampled bit; incrementation-decrementation means for the third clock frequency, configured in such a manner that the third clock frequency is increased when said number of samples is less than the integer multiple N and decreases when said number of samples is greater than N.