Patent ID: 7631172

Claim:
A hardware microprocessor, comprising: wherein the microprocessor is configured to more accurately predict a target address of a return instruction in the presence of a software program that intentionally and explicitly uses the return instruction in a non-standard call/return sequence; a branch target address cache (BTAC), configured to store a plurality of target address predictions and a corresponding plurality of override indicators for a corresponding plurality of return instructions, and configured to provide a prediction of a target address of the return instruction from among said plurality of target address predictions and to provide a corresponding override indicator from among said plurality of override indicators; wherein each of said plurality of override indicators is updated to a true value in response to detecting that the microprocessor was caused to branch to an incorrect target address of said corresponding return instruction that was predicted by a return stack for a most recent execution of said return instruction regardless of whether the prediction of the target address of the return instruction provided by the BTAC also was incorrect; said return stack, configured to provide a prediction of said target address of said return instruction; and branch control logic, coupled to said return stack and said BTAC, configured to cause the microprocessor to branch to said prediction of said target address of said return instruction provided by said BTAC, and not to said prediction of said target address of said return instruction provided by said return stack, when said override indicator is a true value.