Patent ID: 7022565

Claim:
A method of fabricating a trench capacitor of a mixed mode integrated circuit, comprising: forming a first shallow trench isolation region and a second shallow trench isolation region in a semiconductor substrate, wherein the first shallow trench isolation region is used for isolating an active device and a passive device; forming a first patterned photoresist layer on the semiconductor substrate to expose the second shallow isolation region only, removing oxide in the second shallow trench isolation region by using the first patterned photoresist layer as a mask to leave a plurality of shallow trenches, removing the first patterned photoresist layer; forming a gate structure and a source/drain region of semiconductor basic devices in sequence on the first shallow trench isolation region, and forming a polysilicon layer on the second shallow trench isolation region used as a lower electrode layer while forming the gate structure; forming a dielectric layer and an upper electrode layer in sequence on the semiconductor substrate; forming a second patterned photoresist layer on the semiconductor substrate to cover the second shallow trench isolation region and to expose devices on the first shallow trench isolation region; and removing the exposed upper electrode layer by using the second patterned photoresist layer as a mask to form the trench capacitor on the upper electrode layer, the dielectric layer and the polysilicon layer in the trench.