Patent ID: 7495991

Claim:
A semiconductor memory device comprising: at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; at least one bank area, arranged between the global line block and the data transmission block, each bank area containing a plurality of banks, a plurality of data I/O blocks located closer to the data transmission block than the global line blocks—and a plurality of control blocks located closer to the global line block than the data transmission block; and decoding control blocks corresponding to the plurality of banks, respectively, wherein the inputted command and address are transmitted to the decoding control blocks via the center of the semiconductor memory device.