Patent ID: 7292067

Claim:
A buffering apparatus, comprising: a first interface for receiving/transmitting a first input/output from/to a first component having a first predetermined set of logic voltage levels; a second interface for receiving/transmitting a second input/output from/to a second component having a first predetermined set of logic voltage levels; a buffering system disposed between the first and second interfaces, the buffering system being clocked by a clock signal and comprising first and second synchronization paths connected to the first and second interfaces, respectively, and first and second sets of cross-coupled NOR gates connected to the first and second interfaces, respectively, wherein each of the first and second synchronization paths comprises a plurality of flip-flops connected in series and clocked by the clock signal, and wherein a number of flip-flops in the first and second synchronization paths is determined by a ratio of a frequency of the clock signal to a frequency of transitions between logic voltage levels at the first interface or second interface.