Patent ID: 7373486

Claim:
A renamer comprising: a plurality of storage locations, each of the plurality of storage locations assigned to a respective renameable resource and configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource; and compare circuitry coupled to the plurality of storage locations and coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are committing their results to architected state, wherein the compare circuitry is configured to detect a match between the identifiers in the plurality of storage locations and the one or more retiring instruction identifiers; wherein an encoded form of the identifiers is logically divided into a plurality of fields, and wherein the input comprises a first plurality of bit vectors, wherein each of the first plurality of bit vectors corresponds to a respective field of the plurality of fields and includes a bit position for each possible value of the respective field, and wherein the compare circuitry detecting a match between a first identifier in a first storage location of the plurality of storage locations and one of the retiring instruction identifiers comprises detecting a set bit in the same bit position of one of the first plurality of bit vectors and a corresponding one of a second plurality of bit vectors, wherein the second plurality of bit vectors correspond to the first identifier, and wherein a first bit vector of the first plurality of bit vectors comprises a mask having set bits for each of the retiring instruction identifiers, and wherein each retiring instruction identifier corresponds to a different instruction operation that is committing its result to architected state.