Patent ID: 8239788

Claim:
A method for semiconductor wafer processing, comprising: receiving an integrated circuit chip size as an input; determining a frame structure segment size based on the chip size on a reticle, the frame structure segment size being less than the chip size; establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer, each of the shots including at least one frame structure segment having the frame structure segment size and at least one chip, the initial shot layout having an initial chip count; shifting at least one of a row of shots or a column of shots relative to an adjacent row or column of shots by an offset distance to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout, the offset distance baked on the frame structure segment size; comparing the initial shot layout and the at least one additional shot layout; and selecting one of the initial shot layout and the at least one additional shot layout as a final shot layout based in part on a total number of shots and having a final chip count that is greater than or equal to the initial chip count; and exposing the wafer to a light using the final shot layout.