Patent ID: 7791959

Claim:
A memory integrated circuit device comprising: a MOS back bias voltage generator configured to generate a MOS back bias voltage, the MOS back bias voltage generator including, a first temperature sensing unit configured to sense a temperature of the memory integrated circuit device; a first voltage adjusting unit configured to receive an output signal of the first temperature sensing unit and configured to output a voltage based on the output signal of the first temperature sensing unit such that the voltage output changes based on changes in the sensed temperature; and a MOS back bias voltage outputting unit configured to receive the voltage output by the first voltage adjusting unit and configured to output the MOS back bias voltage based on the voltage output by the first voltage adjusting unit, wherein the first voltage adjusting unit includes a first resistor configured to receive the MOS back bias voltage, an n-th resistor configured to receive a ground voltage of the memory integrated circuit device, second through (n−1)th resistors connected between the first resistor and the n-th resistor, and a plurality of MOS transistors connected to the second through (n−1)th resistors, respectively, in parallel, the plurality of MOS transistors are configured to receive respective portions of the output signal of the first temperature sensing unit through their gates, and the output voltage of the first voltage adjusting unit is output through a connection node between the first and second resistors.