Patent ID: 8631312

Claim:
An apparatus, comprising: an input to receive a first LDPC (Low Density Parity Check) coded signal having a first code rate and a first block size and a second LDPC coded signal having a second code rate and a second block size; and an LDPC decoder to decode the first LDPC coded signal using a first LDPC matrix, including a first plurality of sub-matrices, to make a first estimate of a first information bit and to decode the second LDPC coded signal using a second LDPC matrix, including a second plurality of sub-matrices, to make a second estimate of a second information bit; and wherein, within each of the first right hand side matrix and the second right hand side matrix: each sub-matrix located on a respective diagonal is a respective CSI (Cyclic Shifted Identity) sub-matrix; in every row between a top row and a next to bottom row, which is above and adjacent to a bottom row, inclusive, each sub-matrix located on a right hand side of the respective diagonal is a respective zero-valued sub-matrix; the first code rate is one of 1/2, 2/3, 3/4, and 5/6; and the second code rate is another one of 1/2, 2/3, 3/4, and 5/6 that is different from the first code rate.