Patent ID: 8055852

Claim:
A computer system, comprising: a plurality of processors operating in parallel to perform parallel processing functions; a system controller coupled to the processors, the system controller including a memory controller; and a system memory device coupled to the memory controller, the system memory device comprising: at least one bank of memory cells; an addressing circuit coupled to the memory controller, the addressing circuit being operable to address the at least one bank of memory cells responsive to address signals received from the memory controller; a data path coupled to the memory controller, the data path being operable to couple write data from the memory controller and to couple read data from the at least one bank of to the memory controller; a command decoder coupled to the memory controller, the command decoder being operable to generate control signals to control the operation of the memory device responsive to memory command signals received from the memory controller; and a processing system within the system memory device coupled to the at least one bank of memory cells, the processing system being configured to be responsive to a command from one of the plurality of processors to perform an indivisible update operation in the system memory device in which the processing system reads data from a location in the at least one bank of memory cells, the processing system performs a processing function on the data read from the location in the at least one bank of memory cells to provide results data, and the processing system writes the results data to the same location in the at least one bank of memory cells from which the read data was read, the processing system preventing access to the data read from the location in the at least one bank of memory cells by any of the plurality of processors while the indivisible update operation is being performed.