Patent ID: 7257096

Claim:
A power ramping controller of a transmitter comprising frames for transmitting, each frame comprising a plurality of slots, each slot comprising a data period and a guard period for classifying continuous slots of the plurality of slots, the power ramping controller comprising: a ramp memory for dividing power levels of the plurality of slots within a power level range and storing the divided power level range from a lowermost address to an uppermost address; a counter for allocating a start address of the ramp memory for designating a power level of a first slot of the plurality of slots to a lower index and a final address of the ramp memory for designating a power level of a second slot of the plurality of slots to an upper index; and a controller for, dividing the guard period into a number of indices of the counter, increasing the lower index of the counter by 1 and subtracting 1 from the start address, decreasing the upper index of the counter by 1 and subtracting 1 from the final address, designating an address, at a time when a difference obtained by subtracting the start address from the final address is 0 or 1, as an inflection address, and determining ramp steps as power levels stored in addresses corresponding to the number of indices of the counter at the guard period.