Patent ID: 8751975

Claim:
A method comprising: determining model parameters for forming an integrated circuit; and generating a techfile using the model parameters, wherein the generating the techfile is performed using a computer, and wherein the techfile comprises at least two of a C_worst table, a C_best table, and a C_nominal table, and wherein: the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other; the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other; and the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other, wherein the techfile is embodied on a tangible non-transitory storage medium, wherein the step of generating the techfile comprises: determining a maximum shift of a first lithography mask relative to a second lithography mask, wherein the first and the second lithography masks are comprised in a double patterning mask set; selecting a shift magnitude smaller than the maximum shift, wherein the shift magnitude represents a shift of a first net in the first lithography mask relative to second nets in the second lithography mask; calculating coupling capacitance values between the first net and each of the second nets; calculating a total capacitance of the capacitance values; repeating the steps of selecting, calculating the coupling capacitance values, and calculating the total capacitance, wherein in each cycle of the repeating, an additional shift magnitude different from the shift magnitude is selected, and an additional total parasitic capacitance is calculated; selecting a greatest capacitance from the total parasitic capacitance and the additional total parasitic capacitance; and selecting a smallest capacitance from the total parasitic capacitance and the additional total parasitic capacitance; and converting the greatest capacitance and the smallest capacitance into an equivalent k_worst value and a k_best value, respectively, wherein the k_worst value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to increase to the greatest capacitance when the first lithography mask shift relative to the second lithography mask, and wherein the k_best value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to reduce to the smallest capacitance when the first lithography mask shift relative to the second lithography mask.