Patent ID: 8429386

Claim:
An apparatus, comprising: a computer processor configured to execute instructions for a plurality of threads, wherein the computer processor includes a rename unit, and a reorder buffer that comprises: a next tag array having first and second write ports, an output port, and a first read port; a reorder buffer array having a third write port and a second read port; a first buffer circuit that is configured to receive a first tag value from the rename unit and delay delivery of the first tag value to the first write port of the next tag array, wherein the second write port of the next tag array and the third write port of the reorder buffer array are configured to receive the first tag value from the rename unit at an earlier clock cycle of the computer processor than the first write port of the next tag array receives the first tag value from the first buffer circuit; and a second buffer circuit that is configured to receive a second tag value from the output port of the next tag array and provide the second tag value to the first read port of the next tag array and the second read port of the reorder buffer array; wherein the computer processor is configured to assign tag values from a fixed set of tag values to instructions being executed by the computer processor, wherein the tag value assigned to a given instruction in a given thread being executed by the computer processor is usable to determine a program order for the given instruction relative to other instructions within the given thread; and wherein the computer processor is configured to dynamically allocate tag values in the fixed set of tag values between the plurality of threads.