Patent ID: 8806232

Claim:
A system comprising: one or more processors; a cache coupled to the one or more processors; a memory controller coupled to the cache; a bridge coupled to the cache via a separate connection than a connection of the memory controller to the cache, wherein the bridge is configured to couple to one or more peripherals via a second separate connection than the separate connection of the bridge to the cache, and wherein the bridge is configured to bridge memory operations issued by each of the one or more peripherals through the cache to the memory controller, and wherein the bridge is configured to bridge operations from the processors to the peripherals, wherein the peripherals comprise one or more hardware input/output (I/O) devices, and wherein the bridge comprises a plurality of registers that are programmable with data representing a first plurality of operations to be performed prior to powering down the cache and a second plurality of operations to be performed during a power up of the cache, and wherein the first plurality of operations to be performed prior to powering down the cache comprises at least one write operation to a register within the cache, wherein the at least one write operation causes the cache to perform a command, and wherein the bridge is configured to perform the first plurality of operations in response to a power down event for the cache and to perform the second plurality of operations in response to a power up event for the cache; and a power manager configured to generate the power down event responsive to detecting that the one or more processors are powered down and further responsive to detecting that there are no pending operations from the one or more peripherals to the memory controller.