Patent ID: 7981725

Claim:
A fabricating process of a chip package structure, comprising: providing a first substrate having a plurality of first bonding pads; providing a second substrate having a plurality of second bonding pads; forming a plurality of bumps on the first bonding pads of the first substrate; forming a first two-stage adhesive layer on the first substrate; B-stagizing the first two-stage adhesive layer to form a first B-staged adhesive layer, wherein a method for forming the first B-staged adhesive layer comprises: forming a plurality of first two-stage adhesive pillars to surround the bumps; B-stagizing the first two-stage adhesive pillars to form a plurality of first B-staged adhesive pillars; forming a second two-stage adhesive layer on the second substrate; B-stagizing the second two-stage adhesive layer to form a second B-staged adhesive layer, wherein a method for forming the second B-staged adhesive layer comprises: forming a plurality of second two-stage adhesive pillars on the second bonding pads, wherein each of the second bonding pads is entirely covered by one of the second two-stage adhesive pillars, respectively; B-stagizing the second two-stage adhesive pillars to form a plurality of second B-staged adhesive pillars; and bonding the first substrate and the second substrate via the first B-staged adhesive layer and the second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.