Patent ID: 8836143

Claim:
A package-on-package chip package, comprising: a substrate having a plurality of top bond pads and a plurality of bottom bond pads; an integrated circuit proximate a top surface of the substrate, the integrated circuit having terminals electrically coupled to a first subset of the plurality of top bond pads; a cap encapsulating the integrated circuit on at least a portion of the top surface of the substrate, the substrate having a second subset of the plurality of top bond pads positioned outside of a perimeter of the cap, and the cap comprising an encapsulant; a plurality of extension features comprising the encapsulant positioned on at least a portion of the top surface of the substrate, the plurality of extension features extending from the cap to a perimeter of the substrate, the plurality of extension features having a height measured from the top surface of the substrate to a top surface of the plurality of extension features above the substrate that is less than a height of the cap, and the substrate having at least two top bond pads of the second subset not covered by the plurality of extension features; and a top chip package electrically coupled to the at least two top bond pads of the second subset.