Patent ID: 7162588

Claim:
A method of cache line fetching comprising the steps of: providing a first memory having a memory location therein for storing a first set of N data elements and a second adjacent set of N data elements, both sets of data elements line aligned within the first memory, wherein N data elements form an integral number of lines; providing a cache memory; providing a processor for accessing the cache memory and for operating in each of two modes, a first mode and a second mode; determining a mode of operation of the processor; when the processor is in the first mode of operation, transferring data from the first memory to the cache memory N data elements at a time; and, at least some times when the processor is in the second mode of operation, transferring data from the first memory to the cache memory M×N data elements at a time wherein M is an integer greater than 1; wherein the first mode includes a cache hit mode wherein data requested by the processor is stored within the cache at a time of a request therefor and wherein the second mode includes a cache miss mode wherein data requested by the processor is other than stored within the cache at a time of a request therefor.