Patent ID: 7656698

Claim:
A non-volatile memory (NVM) cell structure comprising: a first NVM cell; a second NVM cell; a static random access memory (SRAM) cell; a first pass gate structure connected between the first NVM cell and the SRAM cell, the first pass gate structure being responsive to a first and second states of a pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell; a second pass gate structure connected between the second NVM cell and the SRAM cell, the second pass gate device being responsive to the first and second states of the pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell; a first equalize structure connected between the first pass gate structure and the first NVM cell and responsive to an equalize signal to connect the first NVM cell to a ground; a second equalize structure connected between the second pass gate structure and the second NVM cell and responsive to the equalize signal to connect the second NVM cell to ground, and wherein each of the first and second NVM cells comprises: a P-IGFET programming transistor having a gate electrode connected to a common floating gate node; a P-IGFET read transistor having a gate electrode connected to the common floating gate node; a P-IGFET erase transistor having a gate electrode connected to the common floating gate node; and a fourth P-IGFET control transistor having a gate electrode connected to the common floating gate node, wherein the first pass gate structure is connected between the P-IGFET programming transistor of the first NVM cell and a first data node of the SRAM cell.