Patent ID: 8050110

Claim:
A semiconductor memory device having an active state for performing a read or write operation and an inactive state, comprising: a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit, wherein the pull-up latch unit includes: a latch unit for preventing the data I/O line from floating; and a charging unit for controlling the latch unit to charge the data I/O line when the semiconductor memory device is in the inactive state by determining a logic level of an output signal of the latch unit based on a charging signal generated by combining a clock enable signal denoting an enable state of a clock signal of the semiconductor memory device and a row address strobe (RAS) idle signal transitioning a standby mode.