Patent ID: 7983859

Claim:
A defect analyzer system, comprising: a program storage device storing instructions; and an arithmetic unit executing the instructions to: divide a defect analyzing region of a wafer into a plurality of grid squares, the wafer having a circuit pattern formed thereon; store a pattern feature quantity based on design data of the circuit pattern; extract a pattern feature quantity for each of the grid squares from the stored pattern feature quantity; classify the plurality of grid squares into a plurality of groups based on the pattern feature quantities; store defect information including a defect position and size having been detected in the defect analyzing region; extract the defect information from the stored defect information and match the defect information with the defect analyzing region; determine the number of defects for each defect size in each of the plurality of groups and calculate a defect size distribution; compare the defect size distribution and a predetermined estimation distribution in each of the plurality of groups and calculate a difference; and compare the difference of each of the plurality of groups and a predetermined threshold value, extract the group having the difference equal to or smaller than the predetermined threshold value, and output the defect information corresponding to the extracted group.