Patent ID: 7649214

Claim:
An integrated circuit system comprising: a first core circuit in a first power domain; a first header module coupled between a first power supply voltage and the first core circuit, wherein the first header module includes at least one first PMOS transistor having a source coupled to the first power supply voltage in the first power domain and a drain coupled to the first core circuit; a first footer module coupled between a first complementary power supply voltage and the first core circuit, wherein the first footer module includes at least one first NMOS transistor having a drain coupled to the first core circuit and a gate of the first PMOS transistor, a source coupled to the first complementary power supply voltage in the first power domain, and a gate coupled the drain of the first PMOS transistor; a first inverter with its input coupled to the first core circuit and its output coupled to a second inverter in a second power domain; a second core circuit coupled to the second inverter; a second header module coupled between a second power supply voltage separate from the first power supply voltage and the second core circuit for increasing an impedance against an ESD current flowing between the first inverter and the second inverter during an ESD event; and a second footer module coupled between a second complementary power supply voltage separate from the first complementary power supply voltage and the second core circuit.