Patent ID: 7685488

Claim:
A boundary scan circuit arrangement for detecting logic level crossing in an integrated circuit, the boundary scan circuit arrangement comprising: a logic level crossing detection circuit including a flip-flop having a reset input coupled to a reset signal having a value that varies as a function of an actual logic level of the integrated circuit, the flip-flop being reset from a “1” to a “0” value as a function of the reset signal; and the logic level crossing detection circuit being adapted to indicate a logic level crossing condition of the integrated circuit as a function of a reset condition of the flip-flop; wherein: the logic level crossing detection circuit further includes: another flip-flop having a reset input coupled to another reset signal that varies as a function of an actual logic level of the integrated circuit; and wherein the reset signals provided to each flip-flop reset input are respectively provided, for a particular logic level to reset one of the flip-flops and not the other; and the logic level crossing detection circuit is adapted to indicate the logic-level crossing condition of the integrated circuit as a function of the reset condition of both flip-flops.