Patent ID: 8289254

Claim:
A liquid crystal display apparatus comprising: a plurality of pixels arranged in a matrix, wherein each of the pixels includes a switching element connected to a pixel electrode for applying a voltage to a liquid crystal placed between the pixel electrode and a counter electrode; a plurality of scan lines arranged in a column direction, wherein each of the scan lines is connected commonly to the plurality of switching elements arranged in the row direction; and a vertical scan circuit configured to supply the scan line with a scan signal, generated based on a vertical scan clock signal, to control the switch element between a conducting state and a non-conducting state, and for scanning the pixels scan line by scan line sequentially, wherein the scan signal includes a first conducting signal setting the switch element at the conducting state, a second conducting signal setting the switch element at the conducting state following to the first conducting signal, and a non-conducting signal setting the switch element at the non-conducting state between the first and second conducting signals, and wherein the vertical scan circuit supplies a predetermined scan line with the second conducting signal, wherein the vertical scan circuit supplies to the other scan line which is scanned next to the predetermined scan line with the non-conducting signal after the supply of the first conducting signal to the other scan line and before the end of the supply of a voltage based on a video signal to the pixel on a predetermined row on which a plurality of switching elements commonly connected to the predetermined scan line are arranged during a period in which the second conducting signal is supplied to a predetermined scan line, and wherein the vertical scan circuit comprises a shift register circuit, a first signal generating circuit configured to output a logical product signal based on a control clock signal and an output signal from the shift register, a second signal generating circuit configured to output a logical sum signal as the scan signal generated based on the logical product signal and the output signal from the shift register, and a third signal generating circuit configured to generate the control clock signal based on a signal generated by delaying the vertical clock signal through a delay circuit and to supply the control clock signal to the first signal generating circuit.