Patent ID: 8473661

Claim:
A computer-implemented method of providing multi-process protection for a host system communicating with a plurality of hardware-based functional verification systems, comprising: providing a set of control registers for each execution unit of a plurality of execution units in a controller switch, wherein the controller switch has a plurality of device ports, resides in the host system, and facilitates communication between the host system and the plurality of hardware-based functional verification systems connected to the plurality of device ports of the controller switch; receiving a first access request to access an execution unit of the plurality of execution units from a first process of a plurality of processes, wherein the plurality of processes run on the host workstation, and wherein the plurality of execution units are configured to process instructions received from the host workstation relating to the plurality of hardware-based functional verification systems; allocating a set of direct accessible addresses to the set of control registers of the execution unit; granting the first process of the plurality of processes exclusive access to the execution unit until the first process releases the exclusive access; and denying a second access request from a second process of the plurality of processes to access the execution unit, while the first process retains exclusive access to the execution unit, by checking the assignment of the set of direct accessible addresses to the set of control registers of the execution unit for assignment to a process other than the second process.