Patent ID: 7297590

Claim:
A method for fabricating an integrated pin diode: producing a doped region of one conduction type which is near a carrier substrate; producing a doped region remote from the substrate, which is further away from the carrier substrate than the region near the substrate and is of a different conduction type than the conduction type of the region near the substrate; producing an intermediate region, which is arranged between the region near the substrate and the region remote from the substrate and is undoped or provided with a weak doping in comparison with the doping of the region near the substrate and the doping of the region remote from the substrate; producing at least one electrically conductive terminal region, which leads to the region near the substrate, in a layer containing the intermediate region; producing a doped decoupling region at the same time as the region near the substrate, the decoupling region having the same conduction type as the region near the substrate; producing a circuit arrangement carried by the carrier substrate and containing at least two electronic components; and producing a circuit substrate, which is arranged between the decoupling region and at least one of the components, and the circuit substrate forming a pn diode or an np diode with the decoupling region, the decoupling region being arranged between one portion of the components and the carrier substrate and not between the other portion of the components and the carrier substrate, and in a layer in which the region near the carrier substrate and the decoupling region are arranged, regions outside the region near the substrate and the decoupling region are provided with a doping of a different conduction type from the region near the substrate and the decoupling region or are undoped.