Patent ID: 7392171

Claim:
A computer based test bench generator for an integrated circuit memory model, comprising: a repository storing an identification of memory models catalogued according to memory type, number of ports and synchronous/asynchronous functional operation along with a test type associated with each such memory model; means for entering behavior data of a memory model under test, the behavior data comprising an identification of ports in the memory model under test and a description for each such port of port cycles and port behavior; means for entering configuration data of the memory model under test; means for automatically generating test benches, said means being configured to select the test type from the repository based on a match between the entered configuration data of the memory model under test and the catalogued memory models from said repository and further execute a software-based test case file generation algorithm which generates, according to the entered configuration and behavior data, specific test vectors for the selected test type for uniquely testing the memory model under test.