Patent ID: 8160860

Claim:
A computer implemented method of simulating a logic design having power domains, comprising: identifying, using one or more processors, a switchable power domain of the power domains, the switchable power domain having primary inputs and having a power state switchable between a power-on state and a power-off state; traversing, using one or more processors, the logic design to analyze driver and load logic of each of the primary inputs to the switchable power domain to identify any pure pass-through nets each of which has no driver and no load logic in the switchable power domain; inserting, using one or more processors, an implicit logic device at each of the primary inputs not coupled to a pure pass-through net that does not have the driver and load logic in the switchable power domain, each implicit logic device being in a corrupting state when the switchable power domain is in the power-off state and in a bypassing state when the switchable power domain is in the power-on state, the corrupting state corrupting the respective primary input with an undefined logic state, the bypassing state driving the respective primary input with a logic state of respective driver logic; and performing, using one or more processors, an event-driven simulation of the logic design.