Patent ID: 7247916

Claim:
A semiconductor memory comprising a memory cell matrix including a plurality of cell columns arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors serially arranged along a column-direction, each of cell columns is isolated by a plurality device isolation films running along the column direction, arranged alternatively between the cell columns, each of memory cell transistors comprising: a first conductive layer; a lower inter-electrode dielectric made of insulating material containing at least silicon and nitrogen, extending to side surfaces of the first conductive layer from a top surface of the first conductive layer, each of farthest ends of the extending lower inter-electrode dielectric is sandwiched between the corresponding side surface of the first conductive layer and a side surface of corresponding device isolation film; an upper inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, arranged on the lower inter-electrode dielectric; and a second conductive layer on the upper inter-electrode dielectric, wherein a group of the first conductive layers arranged along one of column-direction is assigned to a corresponding cell column, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups; the upper inter-electrode dielectric is arranged both on the device isolation films and the lower inter-electrode dielectric so that the upper inter-electrode dielectric can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns; and a plurality of second conductive layers running along the row-direction so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.