Patent ID: 7680972

Claim:
A system for handling a predetermined interrupt, comprising: a system memory; a processing unit in communication with the system memory, the processing unit having an interrupt channel; a micro interrupt handler stored in the system memory, the micro interrupt handler defining at least one task associated with the predetermined interrupt; and an interrupt handler stored in the system memory, the interrupt handler defining all tasks associated with the predetermined interrupt except the at least one task; wherein when the predetermined interrupt occurs, the micro interrupt handler and the interrupt handler are called sequentially by the processing unit, and wherein when the processing unit receives the predetermined interrupt while executing an existing task, the processing unit: writes a portion of the existing task to the system memory; reads the micro interrupt handler associated with the predetermined interrupt from system memory; writes a remaining portion of the existing task to the system memory; executes the tasks defined in the micro interrupt handler in parallel with writing the remaining portion of the existing task to the system memory; reads the interrupt handler associated with the predetermined interrupt from memory; and executes the tasks defined in the interrupt handler.