Patent ID: 7989337

Claim:
A method for implementing vertical airgap structures between chip metal layers comprising the steps of: forming a first metal layer; depositing a first layer of silicon dioxide dielectric onto said first metal layer; etching a vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer; said etched vertical air gap having a set width substantially equal to a width of a metal signal trace of said first metal layer; depositing a second layer of silicon dioxide dielectric and sealing said vertical air gap; etching a next trace layer from said second layer of silicon dioxide dielectric and etching a via opening through said second and first layers of silicon dioxide dielectric; and depositing a second metal layer in said etched next trace layer and depositing metal into said via opening; said etched vertical air gap having a set height substantially less than to a distance between said first metal layer and said second metal layer.