Patent ID: 6850107

Claim:
A variable delay circuit for delaying an input clock signal applied to a clock input terminal to produce a delayed clock signal at a clock output terminal, the variable delay circuit comprising: a plurality of inverting logic circuits arranged in series with each other; a delay select circuit receiving at least one delay command signal indicative of a delay of the variable delay circuit, the delay select circuit being operable to generate at least one control signal responsive to the delay command signal, the delay circuit comprising a shift register having a plurality of stages each of which provides a respective control signal, one of the shift register stages storing a unique data bit that is different from the data bits stored in the other shift register stages; and a clock transfer control circuit coupled to the inverting logic circuits, the delay select circuit, and the clock input terminal, the clock transfer control circuit being operable responsive to the at least one control signal to vary the number of inverting logic circuits through which the input clock signal is coupled between the clock input terminal and the clock output terminal, the clock transfer control circuit further being operable to adjust the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal, the clock transfer control circuit comprising: a plurality of pass gates each of which is coupled between the output of a respective inverting logic circuit and the output terminal, each of the pass gates having a control terminal coupled to a respective stage of the shift register; and a polarity control circuit coupled to the inverting logic circuits so that the input clock signal is coupled through the polarity control circuit between the input terminal and the output terminal, the polarity control circuit being operable to alternately invert and not invert the clock signal coupled therethrough as the unique data bit shifts from one shift register stage to the next.