Patent ID: 7038436

Claim:
A switching type dc-dc converter, comprising: a switching transistor circuit; a smoothing circuit connected to the output end of said switching transistor circuit and adapted to provide a smoothed output voltage; a constant-voltage control circuit for maintaining said output voltage at a constant level, said constant-voltage control circuit having an error amplification circuit for comparing a detection voltage associated with said output voltage with a reference voltage to output an error signal in accord with the difference between said detection voltage and reference voltage, an oscillation circuit for providing a comparison signal and a periodic signal each having a respective predetermined period of cycle, and a pulse width modulation circuit for comparing said error signal and comparison signal to generate a switching control signal to be supplied to said switching transistor circuit; and a current restriction circuit for restricting the current that flows through Bald switching transistor circuit, said current restriction circuit having a current detection circuit for detecting and providing the level of current flowing through said switching transistor circuit, a reference current level setting circuit for setting the level (referred to as reference current level) of a reference current such that said reference current level decreases in accord with the decrease in said output voltage; a comparison circuit for providing an over-current detection signal when said detected current level exceeds said reference current level, and a switching control signal stopping circuit for stopping said switching control signal to said switching transistor circuit in response to said over-current detection signal and for reviving said switching control signal in response to said periodic signal, wherein said oscillation circuit is adapted to receive a detection voltage associated with said output voltage and output said comparison signal and periodic signal having said predetermined period of cycle when said detection voltage inputted is put lower than a predetermined voltage but otherwise output a comparison signal and a periodic signal each having a longer period of cycle than said predetermined period of cycle.