Patent ID: 8723050

Claim:
A method for manufacturing multilayer printed circuit board, comprising: providing a first circuit substrate, the first circuit substrate comprising a first electrically conductive trace layer, a first dielectric layer, and a second dielectric layer, the first electrically conductive trace layer being sandwiched between the first dielectric layer and the second dielectric layer, the first electrically conductive trace layer comprising a first conductive terminal, the second dielectric layer being a solder mask and filling gaps defined between the first electrically conductive trace layer, a first through hole defined in the second dielectric layer with the first conductive terminal exposed therethrough; providing a second circuit substrate, the second circuit substrate comprising a second electrically conductive trace layer, a third dielectric layer, and a fourth dielectric layer, the second electrically conductive trace layer being sandwiched between the third dielectric layer and the fourth dielectric layer, the second electrically conductive trace layer comprising a second conductive terminal, a second through hole defined in the third dielectric layer, a third through hole defined in the fourth dielectric layer, the second conductive terminal being exposed through the second through hole and the third through hole; providing a third circuit substrate, the third circuit substrate comprising a third electrically conductive trace layer, a fifth dielectric layer, and a sixth dielectric layer, the third electrically conductive trace layer being sandwiched between the fifth dielectric layer and the sixth dielectric layer, the third electrically conductive trace layer comprising a third conductive terminal, a fourth through hole defined in the sixth dielectric layer with the third conductive terminal exposed therethrough; forming a first anisotropically conductive adhesive layer on one of the second dielectric layer and the fourth dielectric layer; forming a second anisotropically conductive adhesive layer on one of the third dielectric layer and the sixth dielectric layer, and positioning the second circuit substrate between the first circuit substrate and the third circuit substrate; and laminating the first circuit substrate, the second circuit substrate, and the third circuit substrate together, such that the first anisotropically conductive adhesive layer is adhesively sandwiched between the second dielectric layer and the fourth dielectric layer, and extends into the first through hole and the third through hole to electrically connect the first conductive terminal to the second conductive terminal, the second anisotropically conductive adhesive layer is adhesively sandwiched between the third dielectric layer and the sixth dielectric layer, and extends into the second through hole and the fourth through hole to electrically connect the second conductive terminal to the third conductive terminal.