Patent ID: 7183205

Claim:
A method of manufacturing an integrated circuit, comprising the steps of: providing a patterned first material layer with features having top surfaces and sidewalls, the patterned first material layer being composed of a silicon material and being formed over a second material layer which is formed over a substrate; in a conversion process, consuming first material at the feature sidewalls to form third material at the feature sidewalls, the width of third material at each of the sidewalls being greater than the width of first material consumed at the respective sidewall in the conversion process; patterning the second material layer using the third material as mask; forming a fourth material layer over the substrate; exposing the top surfaces of the features in the first material layer through the fourth material layer; removing the exposed first material layer to expose portions of the second material layer through the fourth material layer; and further patterning the second material layer using the fourth material layer as a mask.