Patent ID: 8543791

Claim:
An apparatus for reducing a page fault rate in a virtual memory system, the apparatus comprising: a main storage unit which stores a page table, the page table comprising a page table entry, the page table entry comprising a reference address used for reading page information of first data from the main storage unit and a flag that indicates whether the page information has been recently read; a buffer unit which stores a portion of the page table entry, the portion of the page table entry comprising the reference address for reading the page information of the first data; and a processor which reads data from the main storage unit or which stores data in the main storage unit; wherein if a page fault for second data requested to be read by the processor from the main storage unit occurs, the processor sets the flag in the page table entry to indicate that the page information has not been recently use searches the buffer unit for the portion of the page table entry corresponding to the page table entry having the set flag, determines that the portion of the page table entry exists in the buffer unit based on a result of the search, and invalidates the portion of the page table entry in the buffer unit for reading the page information of the first data, in response to determining that the portion of the page table entry exists in the buffer unit.