Patent ID: 8098954

Claim:
A distorted aberration correction processing apparatus, comprising: a first memory for storing an input image, said first memory being burst-accessible; a second memory, said second memory being random-accessible; an output coordinate calculation circuit which selects a plurality of coordinates of a rectangular area of an output image; a distorted aberration calculation circuit which obtains a distortion ratio at each of the coordinates selected by the output coordinate calculation circuit; a coordinate conversion circuit which obtains the coordinates of the input image stored in the first memory corresponding to the plurality of coordinates selected by the output coordinate calculation circuit, on the basis of the distortion ratio obtained by the distorted aberration calculation circuit; a first address control circuit which burst accesses the first memory to read out therefrom an image of a first rectangular area of the input image stored in the first memory and writes, into the second memory, an image included in only a second rectangular area which is a partial area of the first rectangular area and has a smaller size than the first rectangular area; a second address control circuit which random-accesses the coordinates of the area written in the second memory by the first address control circuit, corresponding to the plurality of coordinates selected by the output coordinate calculation circuit, to read out an image corresponding to the plurality of coordinates selected by the output coordinate calculation circuit; and an output control circuit which generates the output image by controlling the output coordinate calculation circuit, the distortion aberration calculation circuit, the coordinate conversion circuit, the first address control circuit and the second address control circuit so as to repeatedly operate together until all the coordinates of the output image are selected, wherein, the first address control circuit controls read-out address of the first memory and write addresses of the second memory such that the first rectangular area includes all the coordinates obtained by the coordinate conversion circuit and has a lateral size which is an integer times as long as a burst length of the first memory, and the second rectangular area includes all the coordinates obtained by the coordinate conversion circuit.