Patent ID: 8026139

Claim:
A method of fabricating a non-volatile memory device, the method comprising: forming an isolation layer in an isolation region of a semiconductor substrate; forming a tunnel insulating layer and a first conductive layer for a floating gate in an active region of the semiconductor substrate; forming a dielectric layer, a second conductive layer for a control gate, and a gate hard mask over the first conductive layer and the isolation layer; patterning the second conductive layer using the gate hard mask as an etch mask; patterning the dielectric layer so that the first conductive layer is etched, thereby reducing a height and a thickness of the dielectric layer remaining on sidewalls of the first conductive layer with the height of the dielectric layer remaining on the sidewalls of the first conductive layer being lower than a height of the sidewalls of the first conductive layer, wherein an etch rate of the dielectric layer is higher than an etch rate of the first conductive layer when the patterning the dielectric layer is performed; and patterning the first conductive layer using the gate hard mask as an etch mask.