Patent ID: 8039960

Claim:
An electrical interconnect within a semiconductor package, consisting of: a substrate having a plurality of active devices formed thereon; a contact pad formed on the substrate in electrical contact with the plurality of active devices; a first insulation layer formed over the substrate; a second insulation layer formed over the first insulation layer; a first barrier layer formed over the contact pad and the first and second insulation layers; an adhesion layer formed over the first barrier layer; a seed layer formed over the adhesion layer; a single cylindrical inner core pillar including a hollow interior centered over and formed within a footprint of the contact pad; a second barrier layer and a wetting layer formed over the single cylindrical inner core pillar and the hollow interior; and a spherical bump formed around the second barrier layer, the wetting layer, and the single cylindrical inner core pillar, wherein a footprint of the spherical bump encompasses the footprint of the contact pad, and the spherical bump is electrically connected to the contact pad.