Patent ID: 8431454

Claim:
A fabricating process of circuit substrate, comprising: providing a substrate and a dielectric stack layer, wherein the substrate has a pad, the dielectric stack layer is disposed on the substrate and overlays the pad, the dielectric stack layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and the etching rate of the third dielectric layer is greater than the etching rate of the first dielectric layer and the second dielectric layer; forming an opening at the dielectric stack layer, wherein the opening is corresponding to the pad; performing a wet etching process on the dielectric stack layer to remove the portion of the third dielectric layer surrounding the opening so as to form a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening; and performing a plating process on the dielectric stack layer and the pad to respectively form a first plating layer and a second plating layer at the dielectric stack layer and the pad, wherein the gap isolates the first plating layer from the second plating layer.