Patent ID: 8514627

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of memory blocks including a plurality of cell units; first lines each provided commonly for the plurality of memory blocks and each connected to first terminals of plural ones of the cell units; second lines each connected to second terminals of plural ones of the cell units; and a control circuit configured to control signals to be supplied to the cell units, each of the plurality of cell units including: a memory string including a plurality of electrically-rewritable stacked first memory transistors connected in series; a second memory transistor connected at its one terminal to one terminal of the memory string; a first transistor connected between the other terminal of the second memory transistor and the first line; and a second transistor connected between the other terminal of the memory string and the second line, the control circuit being configured to execute an erasing operation on a selected cell unit in a selected memory block, the control circuit being configured to, in an erasing operation, in order to raise a voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, be capable of executing: an operation of generating a GIDL current by setting a voltage of the second line connected to the selected cell unit higher than a voltage of a gate of the second transistor included in the selected cell unit; an operation of setting a voltage of the gate of the second memory transistor included in the selected cell unit equal to or higher than the voltage of the second line connected to the selected cell unit; and an operation of setting a voltage of a gate of the first transistor included in the selected cell unit equal to or lower than a voltage of the first line connected to the selected cell unit, the control circuit being configured to, in an erase operation, in order to set a voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, to be capable of executing: an operation of suppressing generation of a GIDL current by setting a voltage of a gate of the second transistor included in the non-selected cell unit equal to or higher than a voltage of the second line connected to the non-selected cell unit; and an operation of suppressing generation of a GIDL current by setting a voltage of a gate of the first transistor included in the non-selected cell unit equal to or higher than the voltage of the first line connected to the non-selected cell unit, and the control circuit being configured to be capable of executing an operation of applying a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.