Patent ID: 7114019

Claim:
An interface system for interfacing to one or more peripheral devices, the interface system comprising: a data bus; a first plurality (N) of interfaces, wherein at least two of the interfaces are of different types, wherein each of the N interfaces comprises a respective clock input; a first plurality (N) of latches, wherein each of the N latches is configured to couple a corresponding one of the N interfaces to the data bus, wherein each of the N latches comprises a respective clock input; a data buffer coupled to each of the N latches via the data bus; and clock generation circuitry which is operable to generate N clock signals, wherein each one of the N clock signals is provided to a respective one of the N interfaces and to a corresponding respective one of the N latches; wherein the clock generation circuitry is operable to generate each of the N clock signals in a time division multiplexed manner to enable each respective one of the N interfaces, through its corresponding one of the N latches, to access the data buffer through the data bus, wherein each respective one of the N interfaces thereby accesses the data buffer in a time division multiplexed manner.