Patent ID: 8495327

Claim:
A memory controller comprising: first and second output modules for driving first and second data, respectively, to be written to a memory device; a clock module for providing an internal clock signal, wherein the clock module receives an external clock signal that is also provided to the memory device; and a timing control module for producing first and second timing control signals that are supplied to the first and second output modules, respectively; wherein the first and second output modules drive the first and second data at different times responsive to the internal clock signal and the first and second timing control signals, respectively; wherein the timing control module includes: a first module for adjusting the first and second timing control signals, which control the first and second output modules for a write operation, based on a first value for accommodating variations in process parameters, voltage, and/or temperature of the memory device, wherein the first value is provided to the first module by internal BIOS of the memory controller.