Patent ID: 7574688

Claim:
A method of compiling a Hardware Description Language (HDL) representation of a circuit design using a High-level Language (HLL) function comprising: during compilation, by using a computer, of the HDL representation of the circuit design, identifying an attribute of the HDL representation of the circuit design for which a value has not been calculated and which is used to parameterize the HDL representation of the circuit design, wherein the value specifies a hardware implementation characteristic of the circuit design; determining that the HDL representation of the circuit design comprises an HDL function that is executed to calculate a value for the attribute that parameterizes the HDL representation of the circuit design, wherein the HDL function is not translated into hardware during synthesis of the circuit design, and an HLL function that is executed to calculate a value for the attribute that parameterizes the HDL representation of the circuit design, wherein the HLL function and the HDL function are functionally equivalent alternatives of one another; identifying a compilation directive, within the HDL representation of the circuit design, instructing a synthesis tool to select, at compile time, the HLL function to compute the value for the attribute; selecting the HLL function to be executed in lieu of the HDL function according to the compilation directive; and determining a value for the attribute of the HDL representation of the circuit design by natively executing the HLL function.