Patent ID: 8645448

Claim:
An apparatus for performing carryless multiplication, comprising: a carryless preformat unit, configured to receive a multiplier operand, and configured to partition said multiplier operand into a plurality of parts; a Booth encoder, configured to receive said plurality of parts, configured to evaluate said plurality of parts, and configured to direct selection of first partial products of a multiplicand operand, wherein said plurality of parts are configured such that said Booth encoder is precluded from selection of second partial products, and wherein said second partial products reflect implicit carry operations; a compressor, operatively coupled to said Booth encoder, configured to sum said first partial products via a configuration of carry save adders that generate sum bits and carry bits, wherein said carry save adders are arranged in a Wallace tree configuration, and wherein generation of said carry bits is disabled during execution of the carryless multiplication; a left shifter, coupled to said compressor, configured to shift bits of one or more outputs of said compressor; and exclusive-OR logic, coupled to said compressor and said left shifter, configured to execute an exclusive-OR function on said outputs to yield a carryless multiplication result.