Patent ID: 7969797

Claim:
A semiconductor memory device, comprising: a voltage detector configured to detect a level of an external power supply voltage based on a first target level, and to output a detection signal according to the detection result; a first internal voltage detecting unit configured to detect a level of the internal voltage terminal, based on a second target level, the first internal voltage detecting unit being turned on/off in responses to the active signal; a second internal voltage detecting unit configured to detect the level of the internal voltage terminal, based on the second target level, the second internal voltage detecting unit being turned on/off in response to the active signal and the detection signal; a first internal voltage driving unit configured to drive the internal voltage terminal with a first driving ability in response to an output signal of the first internal voltage detecting unit; and a second internal voltage driving unit configured to drive the internal voltage terminal with a second driving ability in response to an output signal of the second internal voltage detecting unit, wherein both the first and second internal voltage detecting units are turned on when the active signal and the detection signal are activated.