Patent ID: 7544555

Claim:
A method of manufacturing a semiconductor device comprising: forming first and second active regions on a semiconductor substrate surface; forming a first gate insulation film having a first thickness on the first active region; forming a second gate insulation film having a second thickness on the second active region; forming gate electrode material on the first and second gate insulation films; forming hard mask material having the first thickness on the gate electrode material; patterning the hard mask material to cause a first hard mask pattern to remain on the gate electrode material positioned on the first active region and to cause a second hard mask pattern to remain on the gate electrode material position on the second active region; patterning the gate electrode material using the first and second hard mask patterns as a mask to form a first gate electrode on the first active region and to form a second gate electrode on the second active region; forming a first insulation film on the first and second active regions; forming a second insulation film on the first insulation film; etching the second insulation film to form a first side wall spacer on side walls of the first and second gate electrodes; removing the first side wall spacer formed on the side wall of the second gate electrode; etching the first insulation film to expose the first and second hard mask patterns, form a second side wall spacer comprising the first and second insulation films on the side wall of the first gate electrode, and form a third side wall spacer comprising the first insulation film on the side wall of the second gate electrode; etching and removing the first and second hard mask patterns and the first and second gate insulation films simultaneously; and forming a metal film on the surfaces of the first and second gate electrode and on the surfaces of the first and second active regions.