Patent ID: 7065632

Claim:
An apparatus for speculatively forwarding storehit data in a microprocessor pipeline, the apparatus comprising: first and second virtual address comparators, for comparing a virtual load address with first and second virtual store addresses to generate a virtual match signal for indicating whether first and second storehit data is likely present in a store buffer and a result forwarding cache, respectively, of the microprocessor, wherein if said first and second storehit data are both present said second storehit data is newer than said first storehit data; first and second physical address comparators, for comparing a physical load address translated from said virtual load address with first and second physical store addresses translated from said plurality of virtual store addresses to generate a physical match signal for indicating whether said first and second storehit data is certainly present in said store buffer and said result forwarding cache, respectively; forwarding logic, coupled to receive said virtual match signal, for forwarding said second storehit data present in said store buffer in response to said virtual match signal indicating no match between said virtual load address and said second virtual store addresses but not a match between said virtual load address and said first virtual store address, prior to generation of said physical match signal; and control logic, for receiving said virtual and physical match signals and generating a stall signal for stalling the pipeline subsequent to said forwarding logic forwarding said storehit data from said store buffer if said physical match signal indicates a match between said physical load address and said second physical store addresses although said virtual match signal previously indicated no match between said virtual load address and said second virtual store addresses, until correct data specified by said physical load address is provided to replace said previously forwarded second storehit data.