Patent ID: 7210012

Claim:
A memory device comprising: a non-volatile memory array having a plurality of memory blocks; and a write-protection control circuit configured to store a start block address and an end block address associated with write protected regions of the non-volatile memory array and wherein the write-protection control circuit is further configured to control a write operation of the non-volatile memory array based on a relationship of a write block address of the write operation to the start block address and the end block address, wherein the write-protection control circuit is further configured to prevent the start and end block addresses from being updated after the start and end block addresses are initially stored in the write-protection control circuit, wherein the write-protection control circuit is further configured to store a plurality of start and stop block addresses that define a plurality of unlocked regions and to control a write operation of the non-volatile memory array based on a relationship of a write block address of the write operation to the plurality of unlocked regions.