Patent ID: 7564925

Claim:
A device ( 6 ) for converting into a digital signal a received signal (Sr) modulated at the timing rate of a clock (CK) and comprising successive bits in the form of modulation between low and high amplitude levels, said device including: a decision circuit ( 6 a ) for supplying, as a function of a comparison of an amplitude (V) of said received signal (Sr) to a decision threshold level, a binary signal (Sb) having a first state or a second state according to whether said amplitude is less than or greater than said decision threshold level, said first and second states being respectively associated with first and second bit values; and a control circuit ( 6 b ) for adjusting a threshold value (Vth, Th) of said decision threshold level; said device being characterized in that said control circuit ( 6 b ) comprises: a first counting module ( 12 ) able to calculate a differential numerical value representing an algebraic difference (ADN) between two numbers (N 1 , N 0 ) of bits of a the binary signal and that respectively have said second bit value and said first bit value, this counting module supplying an indication of the sign (SDN) of said difference; a control module ( 13 , 14 ) for the first counting module ( 12 ) for defining durations (TR, tr 1 -tr 3 ) of successive time periods during which said differential numerical value is calculated; and an adjustment module ( 15 ) adapted to increase or to decrease said threshold value (Vth, Th) by an increment value (DTh) at the end of each time period according to whether said sign indication (SDN) respectively indicates a positive sign or a negative sign.