Patent ID: 8129265

Claim:
A method of forming an integrated circuit chip, comprising: providing a silicon substrate, a transistor in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, and a passivation layer over said silicon substrate, over said first metallization structure and over said dielectric layer, wherein an opening in said passivation layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said opening in said passivation layer, wherein said passivation layer comprises a nitride; forming a second metallization structure on said contact point and over said passivation layer, wherein said forming said second metallization structure comprises forming a glue layer, next forming a seed layer on said glue layer, next forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a region of said seed layer, next electroplating a first copper layer on said region, next forming a nickel layer over said first copper layer in said opening in said photoresist layer, next removing said photoresist layer, and then removing said seed layer and said glue layer not under said first copper layer; and mounting a discrete passive component over said second metallization structure, wherein said discrete passive component is connected to said contact point through said second metallization structure.