Patent ID: 7871868

Claim:
A method for fabricating a thin film transistor array plate for use in a liquid crystal display, comprising: sequentially forming a transparent conductive layer and a sacrificial layer on a substrate; patterning the sacrificial layer, the transparent conductive layer and the substrate to form at least one scanning trench and at least one capacitive trench arranged alternately in parallel, wherein the at least one scanning trench has at least one TFT area, the at least one scanning area, and at least one first terminal area, and the at least one capacitive trench has at least one capacitive area and at least one second terminal area, and wherein the depths of the first and the second terminal areas are gradually decreased to zero toward the end of the scanning trench and the capacitive trench; sequentially forming a first metal layer, a dielectric layer, a silicon layer and a doped silicon layer respectively in the scanning trench and the capacitive trench as well as on the substrate surrounding the first and the second terminals, wherein the material of the dielectric layer is the same as that of the sacrificial layer; laterally etching the exposed sidewalls of the sacrificial layer and the dielectric layer to withdrawn the sidewall profile of the sacrificial layer and the dielectric layer; forming a second metal layer on the sacrificial layer, the transparent layer, and the doped silicon layer; simultaneously defining a TFT in the TFT area, upper electrodes of storage capacitors and a data line in the capacitive area, and two terminal structures respectively in the first and the second terminal areas by a photolithography and etching process with a single exposure step; forming a protective layer on the exposed layers; removing a residual photoresist of the single exposure step and layers thereon; and removing the sacrificial layer, the dielectric layer which have exposed sidewalls and layers thereon.