Patent ID: 8824223

Claim:
A semiconductor memory apparatus comprising: an internal tuning unit configured to tune a generation timing of a data input strobe signal according to a phase difference between an external clock signal and a data strobe clock signal; and a data input sense amplifier configured to transmit data bits to a global line in response to the data input strobe signal, wherein the internal tuning unit is configured to control a delay amount of the external clock signal depending upon a detection result for the phase difference and output the data input strobe signal, wherein the internal tuning unit comprises: a data input control unit configured to receive the data strobe clock signal and the external clock signal, and generate a first control signal and a second control signal; and a data input strobe signal generating unit configured to generate the data input strobe signal in response to the external clock signal, a write command signal, the first control signal, and the second control signal, which includes a signal combining section configured to combine the write command signal and the external clock signal, a first delay section configured to selectively delay an output signal of the signal combining section in response to the first control signal, and a second delay section configured to selectively delay an output signal of the first delay section in response to the second control signal, and outputs the data input strobe signal.