Patent ID: 8775996

Claim:
A method comprising: determining, within a sector in a clock network design for a microprocessor, combinations of candidate sink locations for sector buffers, wherein the candidate sink locations comprise candidate connection points for connecting output terminals of the sector buffers to wire structures of the sector; for each of the combinations of candidate sink locations, transforming resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit; transforming capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit; performing a direct current circuit analysis based, at least partly, on the resistances and the current sources, wherein results of the direct current circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector; storing, by a computer, the results of the direct current circuit analysis for the combinations of candidate sink locations; determining, with the results of the direct current circuit analysis, which of the combination of candidate sink locations has at least one of the minimum variance of voltage and the minimum of the maximum values of currents; and selecting, as connection points for the output terminals of the sector buffers, the combination of candidate sink locations that has at least one of the minimum variance of voltage and the minimum of the maximum values of currents.