Patent ID: 8473718

Claim:
A central processing unit (CPU), comprising: logic to decode virtual machine instructions; logic to decode non-virtual machine instructions; a common instruction cache to store the virtual machine and non-virtual machine instructions; execute logic to receive and process output from the logic to decode non-virtual machine instructions; a hardware accelerator to process virtual machine instructions to produce an output that can be processed by the execute logic; an operand stack for the virtual machine instructions, the operand stack being maintained in a register file as a ring buffer, an overflow/underflow mechanism for moving operands in the operand stack between a register file and a memory, said register file also storing data associated with the non-virtual machine instructions; an instruction buffer that receives virtual machine instructions from the common instruction cache, the instruction buffer being coupled to the logic to decode virtual machine instructions; an instruction buffer control element that receives an indication of the number of virtual machine instructions used by the logic to decode virtual machine instructions to control loading of the virtual machine instructions into the instruction buffer from the common instruction cache.