Patent ID: 7472322

Claim:
A test circuit comprising: a waveform generator formed within scribe lines that extend between a die or within a test die of a semiconductor wafer, the waveform generator formed during a semiconductor process that forms the die on the semiconductor wafer; a transistor to be tested formed within scribe lines that extend between a die or within a test die of the semiconductor wafer, the transistor to be tested formed during a semiconductor process that forms the die on the semiconductor wafer, the transistor to be tested including a gate that is electrically coupled to the waveform generator, and including a source and a drain that are electrically coupled together; a first contact pad electrically coupled to the source and the drain of the transistor to be tested for providing a bias voltage to the transistor to be tested, the first contact pad formed within scribe lines that extend between a die or within a test die of said semiconductor wafer, the first contact pad formed during a semiconductor process that forms the die on the semiconductor wafer; and a second contact pad electrically coupled to the body of the transistor to be tested, the second contact pad formed within scribe lines that extend between a die or within a test die of the semiconductor wafer, the second contact pad formed during a semiconductor process that forms the die on the semiconductor wafer.