Patent ID: 7570091

Claim:
A power-on reset circuit of a semiconductor integrated circuit, the semiconductor integrated circuit having a first internal circuit operated at a first source voltage supplied from outside the semiconductor integrated circuit and having the power-on reset circuit which supplies a power-on reset signal at startup thereof to a second internal circuit operated at a second source voltage generated from the first source voltage, the power-on reset circuit comprising: a first monitoring unit configured to output a first monitoring signal when the first source voltage reaches a first predetermined level; a second monitoring unit configured to output a second monitoring signal when the second source voltage reaches a second predetermined level; a determination unit, which is operated at the first source voltage and is operatively coupled to outputs of the first and second monitoring units, configured to output a reset signal when the first and second monitoring signals are outputted respectively by the first and second monitoring units; and an output unit which is operated at the second source voltage and operatively coupled to an output of the determination unit, and configured to convert the reset signal to the level of the second internal source voltage and further configured to output the converted reset signal as the power-on reset signal, wherein the determination unit comprises: a first P channel MOS transistor which is connected between the first source voltage and an internal node and whose gate terminal is operatively coupled to and controlled by the first monitoring signal output of the first monitoring unit; second and third P channel MOS transistors which are connected in series between the first source voltage and the internal node and whose gate terminals are respectively operatively coupled to and controlled by the reset signal output of the determination unit and the second monitoring signal output of the second monitoring unit; first and second N channel MOS transistors which are connected in series between the internal node and a ground potential and whose gate terminals are respectively operatively coupled to and controlled by the first and second monitoring signal outputs of the first and second monitoring units; and an inverter having an input operatively coupled to the internal node and configured to output the reset signal by inverting a signal at the internal node.