Patent ID: 7535390

Claim:
A time-interleaved analog-to-digital converter (ADC), comprising: a first sub-ADC, comprising: a first resistor series, for providing a first set of reference voltage levels; a first set of pre-amplifying units, coupled to the first resistor series and an input signal line, for amplifying a difference among each reference voltage level of the first set of reference voltage levels and an input voltage level of the input signal line to generate a first set of amplified signals; and a first digital value determining module, coupled to the first set of pre-amplifying units, for generating a first digital value according to the first set of amplified signals; a second sub-ADC, comprising: a second resistor series, for providing a second set of reference voltage levels; a second set of pre-amplifying units, coupled to the second resistor series and the input signal line, for amplifying a difference among each reference voltage level of the second set of reference voltage levels and the input voltage level of the input signal line to generate a second set of amplified signals; and a second digital value determining module, coupled to the second set of pre-amplifying units, for generating a second digital value according to the second set of amplified signals; and a calibration module, comprising: a switch module, coupled to the first resistor series and the input signal line, for selectively providing one reference voltage level of the first set of reference voltage levels onto the input signal line; and a calibration engine, coupled to the first and the second sets of pre-amplifying units and the first and the second digital value determining modules, for calibrating the first set of pre-amplifying units according to the first digital value and calibrating the second set of pre-amplifying units according to the second digital value.