Patent ID: 8477896

Claim:
A hardware clock-data recovery doubler circuit for digitally encoded communications signals, comprising: a first level shifter with an output coupled to a first inverter and an input coupled to a second inverter; a second level shifter with an input coupled to a third inverter and an output coupled to a fourth inverter; a first multiplexer circuit with inputs coupled to outputs of the first and second inverters; a second multiplexer circuit with inputs coupled to outputs of the third and fourth inverters; a NAND logic gate with a first input coupled to an output of the first multiplexer circuit and a second input coupled to an output of the second multiplexer circuit; and a fifth inverter with an input coupled to an output of the NAND logic gate and an output coupled to a plurality of transmission gates comprising the first and second multiplexer circuits; wherein the output of the NAND logic gate is also coupled to an opposing side of the plurality of transmission gates comprising the first and second multiplexers.