Patent ID: 8060771

Claim:
A method to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses of either polarity comprising the following steps: (1) providing a state machine circuit having a clock input signal from an oscillator and an asynchronous suspend input signal suspending a clock output signal while the suspend signal is ON; (2) checking if said suspend is OFF and, if positive go to step 3, else go to step 4; (3) following with the clock output signal the clock input signal and go to step 2; (4) retaining clock output signal in present state; (5) checking if the suspend signal goes to zero and if positive go to step 6, else go to step 2; and (6) resuming clock output signal following clock input signal when clock input signal state corresponds to retained clock output state and go then to step (2).