Patent ID: 7254675

Claim:
A memory system comprising: at least one single in-line memory module (SIMM) including at least one memory device and a signal transmission line connected between the memory device and a connection terminal; at least one dual in-line memory module (DIMM) including at least two memory devices and a signal transmission line connected between the two memory devices and a connection terminal, a first socket which receives the connection terminal of the at least one SIMM; a second socket which receives the connection terminal of the at least one DIMM; and a signal transmission line connected between the first and second sockets, wherein a length of the signal transmission line of the at least one SIMM is longer than a length of the signal transmission line of the at least one DIMM, and wherein the longer length of the signal transmission line of the at least one SIMM increases the signal delay time of the at least one SIMM to further compensate for the signal delay time difference caused by the signal transmission line connected between the first and second sockets.