Patent ID: 7962909

Claim:
A processor comprising: an execution core configured to execute instructions including instructions comprising a guest; and a circuit coupled to the execution core and configured to monitor the execution core, wherein the circuit: is configured to detect that the guest is executing responsive to monitoring the execution core, is programmable to limit an execution of the guest in the execution core to an execution interval, is configured to limit the execution of the guest to the execution interval responsive to detecting that the guest has been executing for a length of the execution interval, is programmable to select at least one event to monitor from a predetermined set of monitorable events that are detectable from the guest execution, comprises a counter configured to measure the length of the execution interval by counting responsive to detecting the at least one event, is configured to enable the counter responsive to detecting that the guest is executing, and is configured to signal the execution core to exit the guest to limit the execution of the guest to the execution interval responsive to detecting, via the counter, that the guest has executed for the length of the execution interval in response to reaching a limit corresponding to the at least one event.