Patent ID: 8289795

Claim:
A semiconductor memory device comprising: a plurality of memory units, each of the memory units comprising: a memory array comprising a plurality of pairs of bit lines, a plurality of word lines, a plurality of memory cells placed at crossing positions of the bit lines and the word lines, and a plurality of sensing amplifiers, each of the sensing amplifiers being coupled to one of the pairs of bit lines, so as to latch data of the one of the pairs of bit lines according to a sensing enabling signal; and a sensing signal generating circuit for generating the sensing enabling signal to activate the sensing amplifiers and for stopping generating the sensing enabling signal to deactivate the sensing amplifiers; and a command decoder for generating a first row enabling signal after receiving a first activate command, so as to activate a first word line of the word lines in a first memory unit of the memory units, after receiving a set of write commands, the command decoder generating a set of column enabling signals and sequentially writing test data into the memory cells coupled to the first word line according to the set of column enabling signals, after receiving a first pre-charge command, the command decoder stopping generating the first row enabling signal, so as to deactivate the first word line, after receiving a second activate command, the command decoder generating a second row enabling signal, so as to activate a second word line of the word lines in the first memory unit of the memory units, and the command decoder stopping generating the second row enabling signal after receiving a second pre-charge command, so as to deactivate the second word line, wherein the semiconductor memory device is selectively operated in a normal mode or a test mode, when the semiconductor memory device is in the test mode, the sensing signal generating circuit generates the sensing enabling signal after the command decoder receives the first activate command, and the sensing signal generating circuit maintains a voltage value of the sensing enabling signal after the command decoder receives the first pre-charge command, such that data latched by the sensing amplifiers are directly written into the memory cells coupled to the second word line after the second word line is activated.