Patent ID: 7557396

Claim:
A semiconductor device comprising, as viewed in cross section: a substrate; a gate insulating film formed on an upper surface of the substrate; a gate electrode formed on the gate insulation film; side wall spacers formed on oppositely facing side walls of said gate electrode; recesses formed in said substrate below said upper surface of the substrate with said gate electrode therebetween; first epitaxial layers formed in said recesses below said upper surface of the substrate; extension layers formed on said first epitaxial layers above said upper surface of said substrate and having slant regions between at least said first epitaxial layers and said side wall spacers; source/drain layers formed on said extension layers; and sidewall films between the sidewall spacers and the source/drain layers, wherein, said extension layers comprise second epitaxial layers which have a conductivity type opposite that of the conductivity type of said first epitaxial layers, said slant regions of said extension layers diminish in thickness in proximity of said gate electrode so as to reduce an electrical coupling capacity with said gate electrode, and first epitaxial layers and said extensions are positioned laterally outside of said gate electrode, said gate insulation film and said sidewall spacers.