Patent ID: 7928489

Claim:
A semiconductor device comprising: a semiconductor substrate; a plurality of transistors formed on a surface of said semiconductor substrate; an interlayer insulating film for covering said transistors; a plurality of ferroelectric capacitors formed over said interlayer insulating film, an electrode of each of said plurality of ferroelectric capacitors being connected to one of a source or a drain of said transistor via a first contact plug; and a plurality of bit lines formed over said interlayer insulating film, each of said plurality of bit lines being connected to the other one of the source or the drain of said transistor via a second contact plug, wherein said plurality of ferroelectric capacitors are arranged in an array, wherein each of said plurality of ferroelectric capacitor has substantially a square planar shape, wherein distances between adjacent ferroelectric capacitors are substantially constant in any of longitudinal directions and in any of latitudinal directions of the array constituted by said ferroelectric capacitors, wherein the distances in the longitudinal direction are the same as the distances in the latitudinal direction, and wherein said plurality of bit lines extends to a direction parallel to a surface of the semiconductor substrate, and extends to a direction parallel or perpendicular to two sides of said square planar shape in plan view.