Patent ID: 8309423

Claim:
A method of forming an integrated circuit, comprising the steps of: providing a p-type substrate; forming a p-type epitaxial layer on a top surface of said p-type substrate; and forming a high voltage diode by a process further comprising the steps of: forming a deep n-well cathode in said p-type epitaxial layer by ion implanting a first set of n-type dopants into said p-type epitaxial layer; forming an uncontacted n-type diffused ring region in said p-type epitaxial layer surrounding said deep n-well cathode by ion implanting a second set of n-type dopants into said p-type epitaxial layer, such that an average dopant density of said uncontacted n-type diffused ring region is higher than an average dopant density of said deep n-well cathode; and forming cathode contacts on said deep n-well cathode.