Patent ID: 7242076

Claim:
A package for a semiconductor die comprising: a semiconductor die comprising one or more transistors; a die pad with one or more integral leads and with an upper surface and a lower surface opposite said upper surface, wherein said die is mounted on said upper surface; a plurality of leads comprising a first set of one or more leads and a second set of one or more leads, wherein each lead of the plurality of leads has a first surface and a second surface, wherein the one or more leads of the first set are physically isolated from said die pad, and wherein the one or more leads of the second set are said integral leads of said die pad and are electrically connected to a terminal on said semiconductor die; a plurality of bond wires, wherein each bond wire of said plurality of bond wires is electrically connected between the die and the first surface of a lead of the first set; and a package body formed of a hardened encapsulant material, wherein the encapsulant material covers said die and said plurality of leads, and the second surface of said plurality of leads is exposed at an exterior surface of the package body; and wherein the leads in the first set comprise means for locking the leads in the encapsulant material.