Patent ID: 7376182

Claim:
An apparatus for generating a phase offset pulse width modulation (PWM) output, comprising: a timer; an offset register; an adder having a first input coupled to the timer and a second input coupled to the offset register; a period register; a subtractor having a first input coupled to an output of the adder and a second input coupled to the period register; a multiplexer having a first input coupled to an output of the subtractor, a second input coupled to the output of the adder, and a third input having logic for selecting either the first or second input for coupling to an output of the multiplexer, wherein if a subtraction result of the subtractor is negative or zero then coupling the first input to the output of the multiplexer, and if a subtraction result of the subtractor is positive then coupling the second input to the output of the multiplexer; a duty cycle register; a comparator having a first input coupled to the duty cycle register and a second input coupled to the output of the multiplexer, wherein the comparator output comprises the phase offset PWM output.