Patent ID: 7495988

Claim:
An integrated circuit device having a display memory which stores at least part of data displayed in a display panel which has a plurality of scan lines and a plurality of data lines, wherein the display memory includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells; wherein a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells are formed in a metal interconnect layer in which the wordlines are formed; wherein a plurality of second power supply interconnects for supplying a second power supply voltage to the memory cells are formed in another metal interconnect layer in which the bitlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory are formed in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.