Patent ID: 8542549

Claim:
An electrical fuse (eFuse) bit cell comprising: a program transistor having a first program terminal, a second program terminal, and a third program terminal; a read transistor having a first read terminal, a second read terminal, and a third read terminal; and an eFuse having a first end and a second end, wherein the first end, the first program terminal, and the second read terminal are coupled together; the read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode, the program transistor is configured to handle a program current in the program mode, the program current flowing between the eFuse and the program transistor; and the program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode, the read transistor is configured to handle a read current in the read mode, the read current flowing between the eFuse and the read transistor.