Patent ID: 7719085

Claim:
A semiconductor device comprising: an interconnect provided in a first insulating interlayer; a first conductive layer located with a spacing from said interconnect; a first insulating layer provided on said first conductive layer; a second conductive layer provided so as to face said first conductive layer across said first insulating layer, said second conductive layer constituting a capacitor element in combination with said first conductive layer and said first insulating layer; a second insulating layer covering both said second conductive layer and said interconnect, said second insulating layer also covering a part of said first insulating layer which does not cover said second conductive layer; a first via plug provided in a second insulating interlayer, said second insulating interlayer having an etching selectivity different than that of said second insulating layer, said first via plug penetrating said second insulating layer thus to be connected to said interconnect; and a second via plug provided in said second insulating interlayer, said second via plug penetrating said second insulating layer thus to be connected to said second conductive layer.