Patent ID: 7271348

Claim:
A circuit board comprising: first and second reference plane layers where the inner surface of each layer is separated by and in contact with a dielectric layer; an embedded discrete surface mount first decoupling capacitor mounted to the outer surface of the first reference plane layer, the first decoupling capacitor comprising a first electrode connected to the first reference plane and a second electrode; a first buried via electrically contacted to the second electrode of the first decoupling capacitors, the first buried via extending through the first reference plane layer and the dielectric layer to electrically contact the second reference plane layer; an embedded discrete surface mount second decoupling capacitor mounted to the outer surface of the second reference plane layer, the second decoupling capacitor comprising a first electrode connected to the second reference plane and a second electrode; a second buried via electrically contacted to the second electrode of the second decoupling capacitors, the second buried via extending through the second reference plane layer and the dielectric layer to electrically contact the first reference plane layer; and vias extending generally along a direction perpendicular to the first and second reference plane layers, wherein the first and second decoupling capacitors are aligned generally along the direction and overlapping one another to increase an amount of space in the circuit board through which the vias are extendable.