Patent ID: 8688959

Claim:
A processor unit for shuffling data, comprising: a register file including a plurality of registers to store data; an instruction fetch unit to fetch an instruction; an instruction decode unit to decode the instruction; an execution unit operative to execute the instruction, receive from the register file a set of source data elements and a set of L control elements, wherein each of said L control elements is associated with a data element position in a resultant and indicates a position of one of said source data elements within a particular vector within said register file; said execution unit also operative to shuffle a data element of the set of source data elements designated by an individual control element to said associated resultant data element position and where the execution unit supports the following values of L: a first value; second value that is half the first value; a third value that is half the second value; a fourth value that is half the third value; wherein said execution unit includes more than one multiplexing level through which said data elements will flow, a first multiplexing layer to select data elements from only a portion of a particular vector having said data element, a second multiplexing layer to select data elements from another portion of said particular vector.