Patent ID: 8289051

Claim:
An integrated circuit chip, comprising: core logic circuitry positioned over a substrate and within a core logic layout boundary delineated on the substrate; and an array of input/output cells substantially surrounding and abutting the core logic layout boundary, each of the input/output cells including input/output transistors oriented in a same direction as the other input/output transistors in the array, each input/output cell further comprising: an input/output layout boundary delineated on the substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides; first and second power conductors located over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides; first and second ground conductors located over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides; and a bond pad located within the input/output layout boundary over the substrate.