Patent ID: 6914273

Claim:
A GaN based enhancement mode MOSFET, comprising: a GaN comprising layer; a (Group III) x Ga 1−x N layer, where x is from 0 to 1, disposed on said GaN layer, a thickness of said (Group III) x Ga 1−x N layer being less than 20 nm; a doped semiconductor source and a doped semiconductor drain extending through said (Group III) x Ga 1−x N layer into said GaN layer, said source and drain separated by a channel region comprising said (Group III) x Ga 1−x N layer and said GaN layer, wherein a first p-n junction is formed where said source contacts said channel region and a second p-n junction is formed where said drain contacts said channel region; a gate dielectric layer disposed over said channel region, and a gate electrode overlapping said source and said drain disposed on said gate dielectric, wherein said MOSFET is in an off-state when said gate is not biased.