Patent ID: 8227839

Claim:
A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs), comprising: forming a plurality of active circuit elements on or in a top side of a semiconductor wafer; forming a plurality of embedded vias through said top side of said semiconductor wafer after said forming said plurality of active circuit elements, said plurality of embedded TSVs having a depth of at least 10 μm; depositing a metal filler layer comprising a filler metal to fill said plurality of embedded vias; chemical mechanical polishing (CMP) said metal filler layer to form a plurality of embedded TSVs, said plurality of embedded TSVs comprising a polished top TSV surface that provides exposed filler metal; forming an electrically conductive hillock suppression structure by forming a Si or Ge doped region or a silicide or germanicide at said polished top TSV surface or forming a metal layer on said polished top TSV surface having a composition different from said filler metal; depositing a dielectric layer on said semiconductor wafer including over said hillock suppression structure, and removing said dielectric layer over said polished top TSV surface to allow metal contact thereto.