Patent ID: 8378404

Claim:
A semiconductor structure of display device, comprising: a substrate with a thin film transistor region and a pixel capacitor region; a semiconductor layer including a first semiconductor portion on the thin film transistor region of the substrate and a second semiconductor portion on the pixel capacitor region of the substrate; a gate dielectric layer covering the semiconductor layer and the substrate; a gate electrode formed on the gate dielectric layer above the first semiconductor portion within the thin film transistor region, wherein the first semiconductor portion including a channel region under the gate, and a source electrode and a drain electrode located at two opposite sides of the channel region; a bottom electrode formed on the gate dielectric layer above the second semiconductor portion within the pixel capacitor region; an interlayer dielectric layer covering the gate electrode, the bottom electrode and the gate dielectric layer, the interlayer dielectric layer including a first contact hole, a second contact hole and a third contact hole, the first contact hole and the second contact hole being respectively exposing the source electrode and the drain electrode, and the third contact hole being exposing the bottom electrode; a source electrode plug and a drain electrode plug being electrically contacted to the source electrode and the drain electrode via the first contact hole and the second contact hole respectively; a top electrode being electrically contacted to the bottom electrode via the third contact hole, wherein there is no intermediate electrode between the top electrode and the bottom electrode; a capacitor dielectric layer and a planarization layer covering the source electrode plug, drain electrode plug, the top electrode and the interlayer dielectric layer, wherein the capacitor dielectric layer and the planarization layer include a fourth contact hole passing through the capacitor dielectric layer and the planarization layer exposing the drain electrode plug and an opening passing through the planarization layer exposing the capacitor dielectric layer over the top electrode; and a pixel electrode formed on the capacitor dielectric layer within the opening and electrically connected to the drain electrode by filled in the fourth contact hole.