Patent ID: 7652504

Claim:
An apparatus comprising: a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the circuit, wherein the level shifter is coupled to receive a second input signal sourced from circuitry supplied by a second supply voltage during use, and wherein the level shifter is configured to generate the first input signal by level shifting the second input signal; wherein the level shifter is further coupled to receive a power control signal indicating, when asserted to a first logic state, that the second supply voltage is to be powered down to a ground reference, and wherein the level shifter is configured to assert a predetermined voltage level on the first input signal independent of the second input signal and responsive to an assertion of the power control signal to the first logic state; and wherein the level shifter comprises: a node and an internal node; a first pullup circuit coupled between the node and a first power supply conductor powered by the first supply voltage during use; a first pulldown circuit coupled between the node and ground; a second pullup circuit coupled between the internal node and the first power supply conductor; a second pulldown circuit coupled between the internal node and ground; a transistor coupled to the node, wherein the transistor is controlled responsive to the power control signal and the transistor is configured to establish a first voltage on the node that causes the predetermined voltage level on the first input signal responsive to the assertion of the power control signal to the first logic state; and at least one additional transistor coupled to the internal node and controlled responsive to the power control signal, and wherein the additional transistor is configured to establish a second voltage on the internal node responsive to the assertion of the power control signal to the first logic state.