Patent ID: 8324679

Claim:
A nonvolatile semiconductor memory comprising: a semiconductor substrate; first and second memory cells formed on the semiconductor substrate, being adjacent to each other across a first element isolation insulating region, and each including a stacked gate structure including a floating gate, a control gate, and a first insulator sandwiched between the floating gate and the control gate; and first and second select gate transistors formed on the semiconductor substrate, being adjacent to each other across a second element isolation insulating region, each including a stacked gate structure including a first gate, a second gate, and a second insulator sandwiched between the first gate and the second gate, and including an open portion exposing a surface of the first gate, the second gate being electrically connected to the first gate via the open potion, the first memory cell and the first select gate transistor constituting a part of a first NAND string, and the second memory cell and the second select gate transistor constituting a part of a second NAND string, wherein each of the floating gates of the first and second memory cells includes a stacked structure including a first film and a second film arranged on the first film, a width of the second film is narrower than a width of the first film in an orthogonal direction of a direction of the first and second NAND strings, a lowest point of the first insulator contacting with the first element isolation insulating region exists on a position lower than an upper surface of the first film and higher than an upper surface of the semiconductor substrate, each of the first gates of the first and second select gate transistors includes a stacked structure including a third film and a fourth film arranged on the third film, and a lowest point of the fourth film contacting with the second element isolation insulating region exists on a position lower than an upper surface of the third film.