Patent ID: 7917731

Claim:
A method of fetching instructions, comprising: accessing an instruction cache with a first instruction address that causes a cache miss; obtaining a second instruction address comprising a branch target address of a predicted-taken branch instruction, wherein the second instruction address is not associated with a prefetch attribute, but is identified as a predicted branch target address; initiating a higher-level memory transaction to retrieve a first instruction associated with the first instruction address; and during a latency period of the higher-level memory transaction: flushing the first instruction address and the second instruction address from an instruction fetch pipeline, wherein the second instruction address re-enters the instruction fetch pipeline in response to the flushing, wherein the re-entered second instruction address is associated with the prefetch attribute to identify the re-entered second instruction address as a prefetch instruction, and wherein the re-entered second instruction address is not identified as a predicted branch target address; and ascertaining whether a second instruction that is associated with the second instruction address is stored in the instruction cache without retrieving any instructions associated with the second instruction address from the instruction cache.