Patent ID: 8344989

Claim:
A shift register, comprising: a plurality of scan stages to output scan pulses to a plurality of gate lines; a first dummy stage to output a first dummy scan pulse to a first of the plurality of scan stages; and a second dummy stage to output a second dummy scan pulse to a last of the plurality of scan stages, wherein each of the plurality of scan stages includes a scan direction controller to selectively output a forward voltage and a reverse voltage having opposite voltage levels in response to the scan pulse from a prior stage and a later stage, wherein each of the plurality of scan stages further includes an output unit to sequentially output a first scan pulse and a second scan pulse based on voltages of a plurality of set nodes and reset nodes and to supply the first and second scan pulses to the latter stage and to the prior stage, respectively, wherein the first scan pulse is output earlier than the second scan pulse, and wherein the first scan pulse is supplied to the latter stage, and the second scan pulse is supplied to the prior stage.