Patent ID: 6871254

Claim:
A processor comprising: a plurality of storage units operable to store data; a first data-retaining unit operable to retain data fed from one of said storage units in order to send out the retained data as first candidate operation data; a second data-retaining unit operable to retain data fed from one of said storage units in order to send out the retained data as second candidate operation data; an operating unit operable to operate the first and second candidate operation data that are parallel-entered into said operating unit from said first and second data-retaining units, respectively; and an address-generating unit operable to generate a first address signal indicating a storage position at which first candidate operation data-yielding data is stored in one of said storage units, a second address signal indicating a storage position at which second candidate operation data-yielding data is stored in one of said storage units, a first read enable signal generated with each of said storage units for controlling the output of the first candidate operation data-yielding data from the corresponding storage unit, and a second read enable signal generated with each of said storage units for controlling the output of the second candidate operation data-yielding data from the corresponding storage unit; wherein each of said storage units allows data stored at the storage position indicated by the first address signal to be fed into said first data-retaining unit in response to the first read enable signal; and wherein each of said storage units allows data stored at the storage position indicated by the second address signal to be fed into said second data-retaining unit in response to the second read enable signal.