Patent ID: 8373446

Claim:
A power supply detection circuit comprising: an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node; a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH; a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage; and an output circuit that inverts the first output voltage to generate a second output voltage at a second node; wherein the input circuit comprises: a first inverter to invert the core power supply voltage to generate the first output voltage; and a first p-type metal oxide semiconductor (PMOS) transistor in series connection with the first inverter to enable increase of the first output voltage to the core power supply voltage; wherein the sense logic circuit comprises: a second PMOS transistor responsive to the first output voltage to sense the voltage drop associated with the first output voltage; and a plurality of transistors, coupled to the second PMOS transistor, to enable sensing of the voltage drop; wherein the current mirror circuit comprises: a first n-type metal oxide semiconductor (NMOS) transistor, having a source coupled to the sense logic circuit, to control the current mirror circuit in response to the second output voltage; a second NMOS transistor, having a gate coupled to the first node, to provide an input to the current mirror circuit in response to the first output voltage; and a plurality of transistors, coupled to the first NMOS transistor and the second PMOS transistor, to increase the first output voltage to an input and output power supply voltage in response to the voltage drop.