Patent ID: 7029953

Claim:
A method of fabricating a semiconductor package for three-dimensional mounting, comprising: (a) providing a substrate, an upper surface of the substrate including a first region and a second region, the first region including an upper metal pattern formed thereon and the second region including at least one registration mark, a lower surface of the substrate including lower metal pattern formed thereon, said upper metal pattern and said lower metal pattern being electrically connected to each other through said substrate; (b) providing a semiconductor chip; (c) placing said semiconductor chip on the upper surface of said substrate within the first region; (d) electrically connecting the semiconductor chip and the upper metal pattern to each other; (e) sealing the semiconductor chip and the upper metal pattern with sealing resin, the sealing resin covering the first region but not the second region, whereby the registration mark is not covered by the resin; and (f) forming, in the first region and through the sealing resin, a through hole which reaches the upper metal pattern by using the registration mark to align the through hole to the upper metal pattern; and (g) forming a wire inside the through hole to electrically connect to the upper metal pattern.