Patent ID: 7725680

Claim:
An application specific integrated circuit (ASIC) comprising: a first bus that communicates with inputs and outputs of N processing modules, where N is an integer greater than 1; a control module that communicates with said first bus and a second bus that is different than said first bus, and generates first control signals; a routing module that communicates with said first bus, receives data via said second bus from a first memory, selectively routes said data to a first of said inputs, and selectively routes one of said outputs to a second of said inputs, wherein said routing module selects said first and second of said inputs based on said first control signals; and a second memory that is different than said first memory, wherein said second memory communicates with said first bus, wherein said control module generates second control signals that are different than said first control signals, and wherein said routing module selectively routes said data and said one of said outputs to portions of said second memory based on said first control signals, wherein a memory size of said portions is determined based on said second control signals.