Patent ID: 7136447

Claim:
A clock recovery circuit for establishing bit synchronization with a received signal, comprising: a first sample circuit having an early clock for detecting the received signal and generating a plurality of first sample signals for output; a first accumulation circuit for receiving the first sample signals and performing a summation operation to generate a first accumulated signal for output; a second sample circuit having a late clock for detecting the received signal and generating a plurality of second sample signals for output; a second accumulation circuit for receiving the second sample signals and performing a summation operation to generate a second accumulated signal for output; a third sample circuit having an on-time clock for detecting the received signal and generating a plurality of third sample signals for output; an adding device for computing the first sample signals and the second sample signals according to the third sample signals to generate an output signal; a loop filter for receiving the output signal to generate a first control signal output; a match filter for deriving an n-th symbol from the received signal by seeking the first sample signals and the second sample signals to generate a second control signal, wherein n is an integer; and a clock-producing device for generating a clock at an ideal impulse-producing time controlled by the first control signal and the second control signal.