Patent ID: 8294195

Claim:
A nonvolatile semiconductor memory element comprising: a source region; a drain region; a channel region that is sandwiched between the source region and the drain region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulating film; a second insulating film that is laminated with the first insulating film; and a third insulating film, wherein the first insulating film is provided between the third insulating film and the second insulating film; wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film; wherein the third insulating film has a trap level density smaller than that of the first insulating film; wherein the charge storage film includes a conductive charge storage film, wherein the second insulating film is provided between the first insulating film and the control gate, and wherein the third insulating film is provided between the first insulating film and the conductive charge storage film.