Patent ID: 7596173

Claim:
A clock generator for generating a single-phase clock into which jitter has been injected, comprising: a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other; and a jitter injecting section for injecting jitter into said respective clock signals based on jitter data representing jitter to be injected into an output of said clock generator, said jitter injecting section comprising: a plurality of jitter injecting circuits corresponding to respective clock signals, each of the jitter injecting circuits injecting jitter into its corresponding clock signal and outputting the corresponding clock signal into which jitter has been injected; and a jitter control section that controls jitter in each of the jitter injecting circuits based on individual jitter data representing jitter to be injected into the corresponding clock signal, wherein said plurality of jitter injecting circuits comprises a plurality of variable delay circuits provided corresponding to the plurality of clock signals to delay and output the corresponding clock signals, and wherein said jitter control section is constructed and arranged to control the delay time of said respective variable delay circuits based on said jitter data of jitter to be injected into said output clock.