Patent ID: 7605629

Claim:
An adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units, the delay circuit generates a plurality of delay clock signals, the adjusting circuit comprising: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals, wherein the difference signal generating circuit comprises a plurality of difference signal generating modules, each of the difference signal generating modules receiving the reference clock signal and a corresponding delay clock signal to generate a difference signal and including an AND gate and a D flip-flop, where the AND gate receives the reference clock signal and the corresponding delay clock signal, an output terminal of the AND gate is coupled to the clock terminal of the D flip-flop, and the data terminal of the D flip-flop receives a constant logic level; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; and a multiphase clock signal generating circuit, for generating a plurality of clock signals corresponding to different phases according to a first specific clock signal, and outputting one of the clock signals to the delay circuit to generate the delay clock signals; wherein the target delay clock signal is one of the delay clock signals.