Patent ID: 8009483

Claim:
A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor respectively; a first PMOS transistor having the floating gate as a gate; and a second PMOS transistor having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, a write data signal is inputted to either a drain or a source of the first NMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and electrons in the floating gate are erased by a tunnel current flowing through a gate insulating film of the second PMOS transistor while applying positive voltage pulses as the erase signal, with the control gate signal being set at a reference voltage.