Patent ID: 7468559

Claim:
A board-on-chip semiconductor integrated circuit package, comprising: a plurality of solder balls; a printed circuit board having a slot and a plurality of substrate pads; a die having a circuit wire connected through the slot from a circuit of the die to conductive traces disposed on the printed circuit board and a plurality of solder balls pads arranged about the die on a circuit side thereof such that when the die and the printed circuit board are brought into proximity with one another the plurality of solder ball pads are not disposed adjacent to the slot, each of the plurality of solder balls being connected between one of the plurality of substrate pads and one of the plurality of solder ball pads, each of the plurality of solder balls being electrically disconnected from the circuit; and an underfill material between and connecting the die and the printed circuit board, the underfill material having a coefficient of thermal expansion that is substantially equal to the coefficient of thermal expansion of the solder ball.