Patent ID: 8589892

Claim:
A computer-implemented method for generating a test for a Design-Under-Test (DUT) based on a template, wherein the method is performed by a processor, the method comprising: partitioning the template into at least a first portion and a second portion, wherein the first portion is determined to be executed in speculative execution by the DUT; injecting a branch instruction operative to cause the DUT to perform speculative execution, the branch instruction defines at least a speculative branch leg and a non-speculative branch leg, wherein the DUT is operative to perform speculative execution of the speculative branch leg; generating a first set of instructions based on the first portion of the template, wherein the first set of instructions is placed in the speculative branch leg; generating an invalid instruction as part of the first set of instructions; simulating, by a reference model of the DUT, speculative execution of the first set of instructions, as well as, simulating execution of the invalid instruction in speculative execution; rolling back the reference model to revoke the speculative execution prior to generating a second set of instructions, and to further revoke simulated execution of the invalid instruction; and generating the second set of instructions, wherein the second set of instructions is placed in the non-speculative branch leg.