Patent ID: 7838368

Claim:
A method of manufacture of a transistor device, comprising: commencing growth of a nanostructure by growing a doped region in the form of a nanowire to form the source or drain; continuing the growth of the nanostructure under changed growth conditions to grow a channel region in the form of a nanotube; continuing the growth of the nanostructure by growing a doped region in the form of a nanowire to form the other of the source or drain; forming an insulated gate adjacent to the channel region; providing a substrate; providing a plurality of catalytic starting points for growing nanostructures; commencing growth of a nanostructure by growing doped regions in the form of a nanowire starting from the catalytic starting points, continuing the growth of the nanostructure under changed growth conditions to grow an undoped channel region in the form of a nanotube; and continuing the growth of the nanostructure by growing a doped region in the form of a nanowire to form the other of the source or drain; forming a dielectric layer as a gate insulator over the channel region of the nanostructures; and forming a conductive gate material over the dielectric layer.