Patent ID: 8295105

Claim:
A semiconductor memory device comprising: a plurality of word lines arranged in rows; a plurality of bit lines arranged in columns; an address decoder that selects one of the word lines in response to an address signal; a sense amplifier that amplifies potentials generated on the bit lines; and a sense amplifier control circuit in which the more distant the word line selected by the address decoder is from the sense amplifier, the later the sense amplifier is activated, wherein the sense amplifier is activated in response to a sense amplifier enable signal, and the sense amplifier control circuit includes a delay time adjustment circuit in which the more distant the word line selected by the address decoder is from the sense amplifier, the longer a delay time of the sense amplifier enable signal is set and a pulse width adjustment circuit in which the more distant the word line selected by the address decoder is from the sense amplifier, the narrower a pulse width of the sense amplifier enable signal is set.