Patent ID: 8458380

Claim:
An integrated circuit comprising: a memory that stores a first task list and a second task list, wherein the first task list includes task instructions, and wherein the second task list includes task instructions; a first bus coupled to the memory; a processor adapted to write task instructions into the memory across the first bus; a first buffer; a second buffer; a third buffer; a second bus coupled to the memory; a first sub-circuit comprising: a first processing circuit adapted to read first data from the first buffer, to process the first data thereby generating second data, and to write the second data into the second buffer; and a first task manager adapted to read a first task instruction of the first task list from the memory across the second bus, to interpret the first task instruction, and to configure the first processing circuit based on a result of the interpreting; and a second sub-circuit comprising: a second processing circuit adapted to read the second data from the second buffer, to process the second data thereby generating third data, and to write the third data into the third buffer; and a second task manager adapted to read a second task instruction of the second task list from the memory across the second bus, to interpret the second task instruction, and to configure the second processing circuit based on a result of the interpreting, and wherein the second task list includes a third task instruction, wherein the second task manager reads the third task instruction from the memory across the second bus, interprets the third task instruction, and executes the third task instruction by starting the second processing circuit upon assertion of a signal received from the first processing circuit.