Patent ID: 8355478

Claim:
A system for aligning clock and data signals comprising: a clock shifting circuit, receiving an incoming clock signal and outputting a shifted clock signal, comprising: a phase locked loop (PLL) with a reference input, a feedback input, and a PLL output, wherein the incoming clock signal connected to the reference input; a plurality of n D flip flops connected in series, each D flip flop having a D input, a clock input, a Q output, and a Q-bar output, wherein the PLL output is connected to the clock input of every D flip flop, wherein the Q output of a D flip flop is connected to the D input of a subsequent D flip flop in the series, wherein the Q-bar output of a last D flip flop in the series is connected to the D input of a first D flip flop in the series, wherein the Q-bar output of the last D flip flop in the series is buffered and connected to the feedback input, where n is an integer; and wherein the shifted clock signal is at least one Q output from the series of D flip flops; and a data clocking circuit, receiving the shifted clock signal and a plurality of incoming data bits and outputting a plurality of reclocked data bits.