Patent ID: 7865855

Claim:
A method for generating a layout for an integrated circuit having a plurality of sinks and at least one source, the source supplies a plurality of signals to the respective plurality of sinks, wherein a first logic is defined by a synthesis step, and wherein during a first layout generation procedure, a placement algorithm for placing a plurality of clones associated with the source on said first layout is performed, the method comprising: identifying the source which supplies at least one of said respective sinks and having a negative slack; finding all sinks having a negative slack driven by the source; clustering said sinks according to timing and placement information read from a database, yielding a plurality of clusters of sinks, in which each cluster includes only a predetermined portion of said plurality of sinks; generating a plurality of clones associated with a respective one of said clusters of sinks; and coupling said clones to respective ones of said clusters of sinks yielding a second layout, wherein the identifying, the finding, the clustering, the generating, and the coupling are performed by one of a chip layout tool and a timing optimization tool in a computer system.