Patent ID: 8589848

Claim:
A computer-implemented method of placing cells in a layout for an integrated circuit design, comprising: receiving a circuit description for the integrated circuit design which includes a plurality of cells interconnected to form a plurality of nets, the cells having locations from a previous placement, by executing first instructions in a computer system; identifying at least one cluster of the cells forming datapath logic, by executing second instructions in the computer system; determining a datapath width for the cluster, by executing third instructions in the computer system; identifying at least one placement set of cells in the cluster, by executing fourth instructions in the computer system; defining a plurality of tiers in the placement set based on connectivity of the cells in the placement set, by executing fifth instructions in the computer system; selectively assigning the cells in the placement set to the tiers constrained by the datapath width, by executing sixth instructions in the computer system; and ordering cells within each tier, by executing seventh instructions in the computer system.