Patent ID: 8730095

Claim:
An electromagnetic transmitter arrangement, comprising: one of an antenna line array and subarray, said one of said line array and subarray defining at least first and second ends, said one of said line array and subarray including at least first, second, third, fourth, and fifth antenna elements, with said first antenna element at said first end of said one of said line array and subarray, said fifth antenna element at said second end of said one of said line array and subarray, said third antenna element at the center of said one of said line array and subarray, said second antenna element lying between said first and third antenna elements, and said fourth antenna element lying between said third and fifth antenna elements; first, second, third, fourth, and fifth radio-frequency signal sources each signal source including a dither block to generate signals with a frequency offset that progressively increases at each of said first, second, third, fourth and fifth antenna elements, such that said first signal source generates signals at frequency of f0, said second signal source generates frequencies of f0±Δf, where the symbol ± means “plus and minus,” said third signal source generates frequencies of f0±2Δf, said fourth signal source generates frequencies of f0±3Δf, and said fifth signal source generates frequencies of f0±4Δf; and a first radio-frequency signal path extending from said first signal source to said first antenna element, a second radio-frequency signal path extending from said second signal source to said second antenna element, a third radio-frequency signal path extending from said third signal source to said third antenna element, a fourth radio-frequency signal path extending from said fourth signal source to said fourth antenna element, and a fifth radio-frequency signal path extending from said fifth signal source to said fifth antenna element, wherein each of said first, second, third, fourth and fifth radio-frequency signal paths includes a controllable switch, each said controllable switch connected in parallel with a corresponding one of said first, second, third, fourth and fifth dither blocks, each said controllable switch configured to bypass the corresponding dither block when the controllable switch is closed.