Patent ID: 7188291

Claim:
A circuit configuration for testing a circuit, the circuit having at least one memory cell array and at least one addressing and control unit, the circuit configuration comprising: a test data line connected to the circuit under test; a test device for providing a test mode and connected to said test data line, said test device having a test mode unit for producing test data supplied to the circuit under test through said test data line, said test device performing test procedures sequentially, the test procedures involving actual data output by the circuit under test on a basis of the test data and the actual data being compared with prescribed nominal data in said test mode unit; a result data line for sequentially outputting test results obtained using the test procedures on a basis of the comparison; and a combinational logic device for logically combining the test results output sequentially to produce an overall result data such that the overall result data indicates fault free operation of the circuit under test only if the actual data being output match the prescribed nominal data in all of the sequentially performed test procedures, the overall result data being output through an addressing and control line by the addressing and control unit of the circuit under test.