Patent ID: 7113004

Claim:
A sense amplifier adapted to sense an input signal on a pair of global bitlines comprising a first bitline and a second bitline, comprising: a. an amplifier offset cancellation network mitigating one of an inherent offset signal value and a dynamic offset signal value, and producing a residual offset signal value; b. an offset equalization network, coupled with the amplifier offset cancellation network and substantially eliminating the residual offset signal value; c. an isolation circuit, isolating the sense amplifier from the global bitlines when the sense amplifier is unused; and d. a charge-sharing circuit operably coupled with the amplifier offset cancellation network, the offset equalization network, and the corresponding global bitlines and adapted to discharge the first bitline with a limited swing when one of the bitlines is logic low and adapted to discharge the second bitline with a limited swing when both of the bitlines are logic high.