Patent ID: 8605476

Claim:
A semiconductor device comprising: first and second global bit lines; a plurality of first local bit lines respectively connected to the first global bit line via first hierarchical switches; a plurality of second local bit lines respectively connected to the second global bit line via second hierarchical switches; a plurality of first memory cells allocated to each of the first local bit lines; a plurality of second memory cells allocated to each of the second local bit lines; a plurality of word lines that connect the first and second memory cells to corresponding first and second local bit lines, respectively; a first sense amplifier connected to the first and second global bit lines via first and second sense switches, respectively; a second sense amplifier connected to the first and second global bit lines via third and fourth sense switches, respectively; and a control circuit, wherein the control circuit activates one of the word lines to simultaneously connect selected ones of the first and second memory cells to corresponding first and second local bit lines, the control circuit brings one of the first hierarchical switches and the first and second sense switches into an electrically conductive state, said one of the first hierarchical switches being provided between the corresponding first local bit line connected to the selected first memory cell and the first global bit line, thereby transferring data stored in the selected first memory cell to the first sense amplifier, the control circuit brings the first hierarchical switch into an electrically nonconductive state, and thereafter activates the first sense amplifier, thereby amplifying data stored in the selected first memory cell, the control circuit brings one of the second hierarchical switches and the third and fourth sense switches into an electrically conductive state, said one of the second hierarchical switches being provided between the corresponding second local bit line connected to the selected second memory cell and the second global bit line, thereby transferring data stored in the selected second memory cell to the second sense amplifier, the control circuit brings the second hierarchical switch into an electrically nonconductive state, and thereafter activates the second sense amplifier, thereby amplifying data stored in the selected second memory cell, and the control circuit brings the first and fourth sense switches and the first and second hierarchical switches into an electrically conductive state, and also brings the second and third sense switches into an electrically nonconductive state, thereby simultaneously restoring data amplified by the first and second sense amplifiers into the selected first and second memory cells, respectively.