Patent ID: 7669096

Claim:
An integrated circuit comprising: first and second circuit means each comprising a first internal node; first and second multiplexer circuit means each comprising first and second input nodes, a control node, and an output node, the first input node of the first multiplexer circuit means coupled to the first internal node of the first circuit means, the first input node of the second multiplexer circuit means coupled to the first internal node of the second circuit means, the second input nodes of the first and second multiplexer circuit means coupled to logical 0, the control signal nodes of the first and second multiplexer circuit means coupled to a control signal; and a third circuit means comprising a first input node coupled to the output node of the first multiplexer circuit means, a second input node coupled to the output node of the second multiplexer circuit means and an output node; wherein the control signal may be used to select the first internal node of the first circuit means or the first internal node of the second circuit means for monitoring at the output node of the third circuit means.