Patent ID: 7329600

Claim:
A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning said first metal layer to form a patterned first metal wiring; forming a support structure on said patterned first metal wiring using a stamp contact printing technique, wherein said support structure is a first insulating material having a dielectric constant K 1 ; depositing a second insulating material onto said support structure, wherein said second insulating material has a dielectric constant K 2 ; planarizing said second insulating material to a surface of said support structure; depositing a polish-stop film layer over said planarized second insulating material and said support structure; forming a plurality of metal studs in said planarized second insulating material and said support structure under said polish-stop film layer; depositing a second metal layer onto said polish-stop film layer; and patterning said second metal layer to form second mental wiring interconnected to said first metal wiring via said metal studs.