Patent ID: 6930931

Claim:
A program counter circuit comprising: an up counter for holding, in an initial state, a prescribed initial value of a first PC value, outputting the first PC value for each reference clock pulse, and counting up a feedback value of the output first PC value and holding a resulting count-up value; at least one pre-jump PC register for holding, as a second PC value, a pre-jump PC value of a jump that is prescribed by a program, and for outputting the second PC value for each reference clock pulse; at least one post-jump register for holding, as a third PC value, a post-jump PC value of the jump, and for outputting the third PC value for each reference clock pulse; at least one down counter for holding a value indicating the number of repetitions of a repeat sequence that is prescribed by the program, outputting the value for each reference clock pulse, and counting down a feedback value of the output value when receiving a prescribed subtraction instruction signal and holding a resulting count-down value; a selector for selecting one of the first PC value that is output from the up counter and the third PC value that is output from the post-jump PC register, and for outputting the selected PC value as an output PC value of the program counter circuit; and a logic circuit coupled to the selector, the up counter, the pre-jump PC register, the post-jump PC register, and the down counter, for providing a logic that causes the selector to select the third PC value if the output PC value of the selector coincides with the first PC value that is output from the pre-jump PC register and the output value of the down counter is not a value indicating that the number of repetitions is 0, and to select the first PC value in the other cases.