Patent ID: 7361557

Claim:
A method of manufacturing a semiconductor device including a trench-gate type MISFET, comprising the steps of: (a) preparing a semiconductor substrate having a first semiconductor layer thereon, said first semiconductor layer having a main surface, said semiconductor substrate having a back surface, and said semiconductor substrate and semiconductor layer having a first conduction type; (b) forming a first insulation film over the main surface of the first semiconductor layer; (c) forming trenches in the first insulating film and first semiconductor layer; (d) forming gate insulating films of the MISFET on inner walls of the trenches; (e) forming a conductive film over the first insulating film and on the gate insulating films; (f) etching the conductive film on the first insulating film so as to form gate conductive layers of the MISFET on the gate insulating films, said gate conductive layers being electrically connected to each other; (g) after the step (f), removing the first insulting film over the main surface of the first semiconductor layer, top surfaces of the gate conductive layers being positioned above the main surface of the first semiconductor layer; (h) forming a base region of the MISFET having a second conduction type in the first semiconductor layer, said second conduction type being opposite to the first conduction type; (i) forming a source region of the MISFET having the first conductive type on the semiconductor layer; (j) forming a second insulating film over the gate conductive layers and the main surface of the first semiconductor layer; (k) etching the second insulating film so as to form side wall spacers on side surfaces of the gate conductive layers; (l) after the step (k), etching the main surface of the first semiconductor layer between adjacent gate conductive layers so as to form a contact hole, said contact hole contacting the source region and the base region; and (m) forming a source conductive layer in the contact hole, said source conductive layer being electrically connected with the source region and the base region.