Patent ID: 7949835

Claim:
A data processing apparatus comprising: main processing logic operable to execute a sequence of instructions in order to perform a process; subsidiary processing logic operable to perform at least part of said process on behalf of the main processing logic; a memory accessible by the main processing logic when performing said process, the main processing logic defining a portion of said memory to be allocated memory accessible to the subsidiary processing logic when performing said at least part of said process; a memory management unit, programmable by the main processing logic, for controlling access to the allocated memory by the subsidiary processing logic, the main processing logic being operable to program the memory management unit such that for an access request issued by the subsidiary processing logic relating to the allocated memory, the memory management unit produces a memory address and one or more associated memory attributes identifying one or more properties of the allocated memory at that memory address, wherein the main processing logic is operable to produce a set of tables, each table in the set containing a number of descriptors, each descriptor defining for an associated address range access control information from which said memory address and one or more associated memory attributes can be derived, the main processing logic being further operable to program the memory management unit to identify the location of the set of tables and circumstances in which each table should be used.