Patent ID: 8049479

Claim:
A semiconductor device comprising: a first semiconductor chip having a high-side semiconductor switch; a second semiconductor chip having a low-side semiconductor switch; a third semiconductor chip including a high-side pre-driver configured to drive the high-side semiconductor switch, and a low-side pre-driver configured to drive the low-side semiconductor switch; a first tab, which is electrically connected to an input terminal and on which the first semiconductor chip is mounted; a second tab, which is electrically connected to an output terminal and on which the second semiconductor chip is mounted; a third tab, which is electrically connected to a logic ground terminal and on which the third semiconductor chip is mounted; and a power ground terminal different from the logic ground terminal, and which is electrically independent of the logic ground terminal, wherein the first tab and a drain terminal of the first semiconductor chip are electrically connected, the second tab and a source terminal of the first semiconductor chip are electrically connected, and the second tab and a drain terminal of the second semiconductor chip are electrically connected, wherein the power ground terminal and a source terminal of the second semiconductor chip are electrically connected, wherein a gate driving terminal of the high-side pre-driver and a gate of the high-side semiconductor switch are electrically connected via a first bonding wire, and a reference potential terminal of the high-side pre-driver and a source of the high-side semiconductor switch are electrically connected via a second bonding wire, wherein a gate driving terminal of the low-side pre-driver and a gate of the low-side semiconductor switch are electrically connected via a third bonding wire, and a reference potential terminal of the low-side pre-driver and the third tab for the logic ground terminal are electrically connected via a fourth bonding wire, and wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the second bonding wire, the third bonding wire, and the fourth bonding wire are packaged in one package.