Patent ID: 7180136

Claim:
A device, comprising: a transistor comprised of a plurality of source/drain regions formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, said bulk substrate being doped with a first type of dopant material; a first well formed in said bulk substrate, said first well being doped with a second type of dopant material that is of a type opposite said first type of dopant material; a second well formed in said bulk substrate within said first well, said second well being doped with a dopant material that is the same type as said first type of dopant material, said transistor being formed in said active layer above said second well; a source/drain well formed in said bulk substrate within said second well under each of said source/drain regions, said source/drain wells being comprised of a dopant material that is of the same type as said first type of dopant material, said source/drain wells having a dopant concentration level of said first type of dopant material that is less than a dopant concentration level of said first type of dopant material in said second well; an electrical contact for said first well; and an electrical contact for said second well.