Patent ID: 7969182

Claim:
A semiconductor device comprising: a calibration circuit configured to perform a pull-down calibration operation based on a pull-down calibration enable signal, the calibration circuit including, a first pull-up resistance structure connected to a first node, the first pull-up resistance structure configured to adjust an impedance of the first pull-up resistance structure based on pull-up calibration data having a first value, a first comparing unit configured to compare a voltage of the first node and a reference voltage, and output pull-down calibration data based on the pull-down calibration enable signal and the comparison of the voltage of the first node and the reference voltage, and a pull-down resistance structure connected to the first node, the pull-down resistance structure configured to adjust an impedance of the pull-down resistance structure based on the pull-down calibration data; and a command control unit configured to output the pull-down calibration enable signal based on a delay-locked loop (DLL) reset signal.