Patent ID: 6839784

Claim:
A control unit of an input/output node for a computer system comprising: a plurality of scheduler units each including: a first buffer circuit coupled to receive control commands corresponding to commands received from a first source, wherein said first buffer circuit includes a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to said respective virtual channel; wherein said plurality of virtual channels includes a posted channel, a non-posted channel and a response channel; a second buffer circuit coupled to receive control commands corresponding to commands received from a second source, wherein said second buffer circuit includes a second plurality of buffers each corresponding to a respective virtual channel of said plurality of virtual channels for storing selected control commands that belong to said respective virtual channel; and an arbitration unit coupled to said first buffer circuit and to said second buffer circuit, said arbitration unit is configured to arbitrate between said control commands stored in said first buffer circuit and said control commands stored in said second buffer circuit; wherein each of said control commands contains a subset of information included within the corresponding commands received by said first source and said second source.