Patent ID: 8082425

Claim:
A system comprising: a cache configured to store instructions of a computer program; and a processor; wherein the processor is configured to: replicate an original instruction of said instructions to create a copy of the original instruction, in response to determining the original instruction corresponds to a first instruction type; not replicate the original instruction of said instructions, in response to determining the original instruction corresponds to a second instruction type which is to be executed by a first functional unit, wherein there are M copies of the first functional unit, each copy corresponding to two or more threads of a plurality of threads, where M is a positive integer; and convert the original instruction of the second instruction type from a unary type having only one source operand to a binary type having two source operands; and execute the original instruction of the second instruction type as converted, in response to determining a source operand of the two source operands is ready from a first thread and a source operand of the two source operands is ready from at least one other thread of the plurality of threads.