Patent ID: 7238577

Claim:
A method of fabricating a semiconductor power device structure, the method comprising: forming a layer of etch stop material on a semiconductor substrate; forming a first layer of dielectric material on the layer of etch stop material; forming a second layer of dielectric material on the first layer of dielectric material; patterning the first and second layers of dielectric material to form trenches therein to expose a plurality of spaced-apart surface region stripes of the etch stop material; introducing dopant having a first conductivity type into the semiconductor substrate beneath the exposed surface region stripes of the etch stop material to define a plurality of space-apart stripes having the first conductivity type in the semiconductor substrate; forming a layer of conformal material over the structure resulting from the foregoing steps such that the conformal material fills the trenches formed in the first and second layers of dielectric material; planarizing the layer of conformal material to a top surface of remaining second dielectric material; removing the remaining second dielectric material to expose a plurality of spaced-apart surface region stripes of the first dielectric material; introducing dopant having a second conductivity type that is opposite the first conductivity type into the semiconductor substrate beneath the exposed surface region stripes of the first dielectric material to define a plurality of space-apart stripes having the second conductivity type in the semiconductor substrate, thereby defining a substrate structure that comprises a plurality of adjacent substrate stripes that alternate between substrate stripes having the first conductivity type and substrate stripes having the second conductivity type; removing remaining conformal material; and removing remaining first dielectric material.