Patent ID: 7598180

Claim:
A semiconductor device produced by a process comprising: forming a molding layer over a semiconductor wafer; etching the molding layer, using a first photoresist pattern on the molding layer as an etching mask, to form a plurality of storage node holes, wherein the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area; forming first and second storage nodes in the first and second storage node holes, respectively; forming a second photoresist pattern on the molding layer that covers the edge chip area; selectively etching the molding layer, using the second photoresist pattern as an etching mask, to expose portions of the first storage nodes; sequentially forming a lower interlayer dielectric layer and an etch stop layer on the semiconductor wafer prior to formation of the molding layer; and forming a plurality of contact plugs electrically connected to the semiconductor wafer, wherein the contact plugs include at least one first buried contact plug formed in the effective chip area, and at least one second buried contact plug formed in the edge chip area.