Patent ID: 7581055

Claim:
A memory system, comprising: a plurality of memory requestors; a first rank containing a plurality of memory modules each of which comprises: a plurality of memory devices; and a memory hub coupled to a plurality of the memory requestors and to the memory devices in the memory module, the memory hub in each of the memory modules in the first rank including a plurality of first ports and being configured to allow any of the memory requesters to access the memory devices to which it is coupled or to access any of the first ports in the memory hub; and a second rank containing a plurality of memory modules each of which comprises: a plurality of memory devices; and a memory hub coupled to the memory devices in the memory module, each of the memory modules in the second rank including a plurality of second ports corresponding in number to the number of memory modules in the first rank, the memory hub in each of the memory modules in the second rank being coupled to each of the memory modules in the first rank through respective ones of the first ports and the second ports, the memory hub in each of the memory modules in the second rank being operable to allow any of the memory requestors to access the memory devices to which it is coupled through at least one memory module in the first rank.