Patent ID: 7315546

Claim:
A method of aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock, comprising: a) estimating a predicted delay for transmitting packets between a source and destination over the network; b) sending time-stamped synchronization packets to said destination, each time-stamped synchronization packet carrying timing information based on a master clock at said source; c) receiving a set of synchronization packets at said destination to create a set of data points; d) weighting said set of data points so that synchronization packets exhibiting a delay further from said predicted delay are accorded less weight than synchronization packets exhibiting a delay closer to said predicted delay; e) updating said predicted delay to create a current delay estimate based on said set of data points taking into account the different weighting of said data points; f) continually repeating steps d and e on new sets of data points created from newly received synchronization packets using the current delay estimate for said predicted delay; and g) continually aligning a clock domain at said destination with a clock domain at said source based on the current delay estimate for packets traversing the network between the source and destination.