Patent ID: 7403428

Claim:
A non-volatile memory system, comprising: a set of non-volatile storage elements having a well region, said set includes a first and a second subset of non-volatile storage elements, said first subset is interior to said second subset; said set of non-volatile storage elements includes a first non-volatile storage element adjacent to a first select gate for said set and a second non-volatile storage element adjacent to a second select gate for said set; said second subset of non-volatile storage elements is interior with respect to said first non-volatile storage element and said second non-volatile storage element; and managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry receives a request to erase said set, said managing circuitry, in response to said request, applies a first voltage signal to each non-volatile storage element in said set, applies an erase voltage to said well region, and changes said first voltage signal for each non-volatile storage element in said first subset after beginning application of said erase voltage, said managing circuitry changes said first voltage signal while applying said erase voltage to said well region, said managing circuitry changes said first voltage signal for each non-volatile storage element in said second subset after changing said first voltage signal for each non-volatile storage element in said first subset.