Patent ID: 7519941

Claim:
A manufacturing method comprising: designing multiple masks, wherein said masks contain patterns for corresponding blocks of circuitry with corresponding performance and timing requirements, and wherein said designing comprises establishing, for each of said masks, at least predetermined mask specifications and sets of rules for mask formation; pre-qualifying each of said masks individually with respect to said corresponding performance and timing requirements, wherein said pre-qualifying comprises: for each specific mask, forming said specific mask on a test chip; using said specific mask to form a specific block of circuitry on said test chip; and, electrically testing said test chip to determine whether said specific block of circuitry meets specific performance and timing requirements and, if not, repeating said designing of said specific mask; maintaining said masks, once pre-qualified, in a library; designing an integrated circuit structure with at least one block of circuitry having predetermined performance and timing requirements; selecting, from said library, a pre-qualified mask that corresponds to said at least one block of circuitry; and using said pre-qualified mask to pattern said at least one block of circuitry onto a substrate, wherein said pre-qualifying ensures that, once formed on said substrate, said at least one block of circuitry will meet said predetermined performance and timing requirements.