Patent ID: 6888412

Claim:
A phase locked loop (PLL) circuit for reducing electromagnetic interference (EMI) including a phase comparator for comparing the phase of an externally input reference clock signal with the phase of a feedback signal to output an up or a down signal according to the compared result, a charge pump for generating a charge signal for supplying or sinking charges in response to the up or down signal, and a loop filter for low-pass filtering the charge signal to generate direct current (DC) control voltage, the PLL circuit comprising: a voltage-controlled oscillator (VCO) for generating an output clock signal oscillated into an oscillating frequency corresponding to the control voltage; a multiphase interpolater for generating first through n-th shifted signals, which have a predetermined offset so as not to overlap one another, by using the output clock signal; and a feedback signal portion for receiving the up/down signal to determine whether the feedback signal is locked to the reference clock signal, for outputting the output clock signal as the feedback clock signal before the feedback signal is locked to the reference clock signal, and for sequentially selecting one of the first through n-th shifted clock signals to be the feedback clock signal once the feedback clock signal is locked to the reference clock signal.