Patent ID: 7310275

Claim:
A non-volatile memory device comprising: a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line; and a page buffer coupled to the memory cell array via a sensing line, wherein the page buffer comprises: a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured not to be activated during program, read, and verification operations and to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell; and a second latch unit including a second latch circuit and coupled to the sensing line, the second latch unit being configured not to be activated during the copy-back operation and be activated during program, read, and verification operations, the second latch unit configured to receive data to be programmed in the memory cells and store the data during the program operation, the second latch unit configured to read the data programmed in the memory cells and store the read data during the read and verification operations.