Patent ID: 8081715

Claim:
A wireline receiver circuit comprising: an input configure to receive a digital signal via a wireline; a plurality of filters arranged in parallel and configured to each be enabled during different time periods, respectively, in response to a plurality of enable signals, respectively, in order to select and discretely filter different portions of the digital signal in parallel and output a plurality of filtered signals, wherein each filter of said plurality of filters comprises at least one of: a differential switch pair responsive to the digital signal, and an integrator that integrates the digital signal; and wherein each filter of said plurality of filters comprises: a current source that provides current to said integrator; and a bias circuit configured to provide a current definition to said current source; and a plurality of samplers configured to sample different ones of the plurality of filtered signals in parallel to generate another digital signal having at least one of an improved signal-to-noise ratio and bit error rate.