Patent ID: 8169081

Claim:
An integrated circuit structure comprising: a first conductive layer below an uppermost passivation layer, the first conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region; an under bump metallization layer over the first conductive layer, the under bump metallization layer extending over the uppermost passivation layer, the under bump metallization layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region; at least one of the first conductive area or the first conductive region including a first protrusion extending toward the second conductive area or second conductive region, respectively; and conductive vias through the uppermost passivation layer connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, the conductive vias including at least one via connected to the first protrusion.