Patent ID: 6888799

Claim:
A synchronized digital hierarchy (SDH) test apparatus comprising: an Rx section overhead (SOH) processor for performing frame detection of received SDH data; an Rx administrative unit (AU) processor for extracting AU data composed of an AU pointer and a payload from data proccessed by said Rx SOH processor, and for detecting an information leading head position designated by said AU pointer; a Tx AU processor for generating AU data in which a part of the payload of AU data extracted by said Rx AU processor is substituted with a desired data; a Tx SOH processor for generating a new SDH data with the AU data generated by said Tx AU processor and the data from said Rx SOH processor and transmitting the new SDH data; a FIFO memory installed between said Rx AU processor and said Tx AU processor, for sequentially storing payload data of AU data extracted by said Rx AU processor and outputting to said Tx AU processor in an order of memorization; and an AU pointer processor for outputting an AU pointer adjusting a number of data in said FIFO memory, allowing said Tx AU processor to read in the payload of AU data, after a time lag (Î”T 2 +Î”T 4 ) of an information leading head position of the payload generated by processing of AU data by said Rx AU processor and said Tx AU processor, by extracting the number of data in said FIFO memory, wherein said Tx AU proccessor is adapted to read out the payload of AU data from said FIFO memory, generate AU data, and output to said Tx SOH processor so that said information leading head position is at a position designated by an AU pointer value output from said AU pointer processor.