Patent ID: 7633731

Claim:
A high-voltage dual-polarity p-well pump ESD protection circuit for an I/O pad of an integrated circuit comprising: an n-channel MOS discharge transistor formed in a p-well and having a drain coupled to the I/O pad, a source coupled to ground, and a gate; a MOS capacitor having a gate coupled to the I/O pad, a source and a drain; a first resistor coupled between the source and drain of the MOS capacitor and a ground node; an n-channel MOS pulldown transistor having a drain coupled to the source and drain of the MOS capacitor, a source coupled to the ground node, and a gate coupled to a power-supply voltage node; an n-channel MOS p-well control transistor having a source coupled to the ground node, a drain coupled to the p-well, and a gate; a second resistor coupled between the I/O pad and the drain of the n-channel MOS p-well control transistor; an n-channel MOS pump transistor having a gate coupled to the gate of the first n-channel MOS transistor, a drain coupled to the I/O pad, and a source coupled to the p-well.