Patent ID: 6847248

Claim:
A method of protecting an integrated circuit from over voltage, the method comprising: accepting a voltage from a power supply input to the integrated circuit; accepting a pad voltage from an external voltage source; comparing the power supply voltage to a predetermined value; coupling a bias voltage for the integrated circuit to a gate of a PMOS (P-channel Metal Oxide Semiconductor) device when the power supply is below the predetermined value; and coupling the pad voltage to a bias_mid node through the PMOS device to provide the bias voltage for the integrated circuit when the power supply is below the predetermined value, wherein coupling the bias voltage for the integrated circuit to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device when the power supply is below the predetermined value comprises coupling the bias voltage to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device through a first plurality of diode connected MOS devices when the power supply is below the predetermined value.