Patent ID: 7547947

Claim:
A memory cell comprising: a first non-planar transistor comprising: a first semiconductor fin comprising a first channel; and first gates adjacent said first channel; a second non-planar transistor comprising: a second semiconductor fin comprising a second channel; and second gates adjacent said second channel; and a third non-planar transistor comprising: a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls; and third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates, wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights, wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and wherein said third semiconductor fin is wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.