Patent ID: 7405957

Claim:
A memory component configured in a wafer having at least a first and second edge, the memory component comprising: at least one memory bank array; a data path coupled to the memory bank array; and a plurality of data pads coupled to the data path and configured with the data path to bus data to and from the memory bank array and configured such that each of the data pads are located adjacent the first and second edges of the wafer; wherein the memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer, the data pad on the first edge being coupled to the memory bank by the data path, and at least one of the data pads used to bus data is located on the second edge of the wafer, the data pad on the second edge being coupled to the memory bank by the data path.