Patent ID: 8765558

Claim:
A method for fabricating a complementary metal oxide semiconductor (CMOS) structure comprising: forming a dummy CMOS structure over a semiconductor substrate that includes a first active region of a first polarity separated from a second active region of a second polarity different polarity than the first polarity by an isolation region, said dummy CMOS structure comprising a dummy gate that traverses the first active region, the isolation region and the second active region; removing a first portion of the dummy gate over the first active region and an adjoining portion of the isolation region to provide a first aperture; backfilling the first aperture with a first gate; removing a second portion of the dummy gate over the second active region and an adjoining portion of the isolation region to provide a second aperture; backfilling the second aperture with a second gate that is separated from the first gate by a third remainder portion of the dummy gate; removing the third remainder portion of the dummy gate to provide a third aperture bounded by facing endwalls of the first gate and the second gate; and filling the third aperture with a passivation layer.