Patent ID: 8201112

Claim:
A system comprising: a hardware module; and one or more computer-readable tangible storage devices and a design structure stored on at least one of the one or more computer-readable tangible storage devices; wherein a physical representation is generated when the design structure is processed by the hardware module; wherein the physical representation includes: a circuit for managing voltage swings across field effect transistors in the circuit, comprising: a reference precision resistor; a first field effect transistor and a second field effect transistor, wherein a gate of the first field effect transistor is tied to a gate of the second field effect transistor, wherein a drain to source resistance of the second field effect transistor is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second field effect transistor is applied to a gate of the first field effect transistor to set a bias point of the first field effect transistor; and a third field effect transistor cascoded to the first field effect transistor, wherein a source of the first field effect transistor is coupled to the drain of the third field effect transistor to extend a voltage range in which respective gate voltages of the first field effect transistor and the third field effect transistor maintain a linear relationship with respective drain to source voltages of the first field effect transistor and the third field effect transistor.