Patent ID: 8901982

Claim:
A method of calibrating a delay line, comprising: inputting a first clock signal to the delay line wherein the delay line has a plurality of taps; inputting a second clock signal to a reference circuit, wherein the second clock signal is different from the first clock signal and the reference circuit has a plurality of taps; selecting a first tap of the delay line as a current delay tap; selecting a first tap of the reference circuit as a current reference tap; determining whether or not output signals of the current delay tap and the current reference tap align; in response to determining that the output signals do not align: repeating a selection of a next tap of the reference circuit as the current reference tap and a determination of whether or not the output signals align until the output signals align: storing reference tap data indicative of the current reference tap in association with a delay tap number of the current delay tap; selecting a next tap of the delay line as the current delay tap; and repeating the determining whether or not the output signals align.