Patent ID: 8039354

Claim:
A method comprising: forming at least two wiring levels containing interconnect members upon a substrate; forming a passive circuit element in said at least two wiring levels having a first portion formed on a first wiring level simultaneously with interconnect members formed on said first wiring level and a second portion formed on a second wiring level simultaneously with interconnect members formed on said second wiring level, further comprising: forming a capacitor comprising at least two sets of interdigitated electrodes in each of said first and second wiring levels, forming each of said interdigitated electrodes connected vertically to corresponding electrodes in the other of said first and second wiring levels by a set of vertical connection members, thereby forming an effective vertical plate, in which said vertical connection members are arrayed in rows disposed along finger electrodes of each of said interdigitated electrodes, with vertical connection members connecting said finger electrodes located in each of said first and second wiring levels, in which said vertical connection members are disposed in staggered rows disposed along said finger electrodes, with a row of vertical connection members connecting finger electrodes of one of said interdigitated electrodes alternating with a row of vertical connection members connecting finger electrodes of the other of said interdigitated electrodes; forming said finger electrodes having a finger width greater than the width of said vertical connection members; and forming in at least one of said first and second wiring levels vertical connection members arrayed in a set of unit cells having a first pitch, and forming in at least one other of said first and second wiring levels vertical connection members arrayed in a set of unit cells having a second pitch greater than said first pitch.