Patent ID: 7375399

Claim:
A semiconductor memory device having on a semiconductor substrate: a logic block; a memory block constituted by a plurality of unit memory cells; and a high-voltage block supplied with a first voltage larger than a voltage which is supplied to said logic block and said memory block; wherein said unit memory cells each include at least two transistors: a write transistor connected at either a source or drain thereof to a bit line and at the other to an electric charge storage node, said write transistor storing an electric charge into, and releasing the electric charge from, said electric charge storage node; and a read transistor whose conductance in a channel region provided between a source and drain of said read transistor is changed dependently on an amount of electric charge stored into or released from said electric charge storage node by said write transistor; wherein said read transistor has a gate-insulating film thicker than that of a transistor provided in said logic block; and wherein a diffusion layer that determines gate length of said read transistor is provided adjacently to a high-density impurity diffusion region which forms part of the source or drain of said read transistor, said diffusion layer having a junction depth smaller than, and an impurity density higher than, those of a diffusion layer which determines gate length of a transistor constituting said high-voltage block.