Patent ID: 7486147

Claim:
A phase locked loop, comprising: a phase frequency detector operable to produce an error signal indicative of a difference in phase or frequency between a reference signal and a feedback signal; a charge pump operable to generate a current pulse proportional to said error signal; a loop filter operable to filter said current pulse to produce a control voltage; a voltage controlled oscillator operable to produce an oscillation based upon said control voltage; a frequency divider coupled to receive said oscillation and operable to divide said oscillation by a divide ratio to produce said feedback signal; a controller coupled to receive said reference signal and operable to generate a frequency divider control signal based upon said reference signal to control operation of said frequency divider, to generate a phase frequency detector control signal substantially simultaneous to said frequency divider control signal to control operation of said phase frequency detector and to generate a calibration signal to control calibration of said voltage controlled oscillator; a calibration module operable to calibrate said voltage controlled oscillator upon receipt of said calibration signal; a loop filter controller coupled to receive said calibration signal and operable to produce and maintain said control voltage at a calibration control voltage for calibration of said voltage controlled oscillator; a divider reset switch coupled to receive said frequency divider control signal and operable to reset said frequency divider when said frequency divider control signal is in a reset state; and a phase frequency reset switch operable to reset said phase frequency detector when said phase frequency detector control signal is in a reset state; wherein said controller is further operable to generate said frequency divider control signal in said reset state at a time that substantially brings an output of said phase locked loop into phase lock.