Patent ID: 7480763

Claim:
A programmable logic device having a versatile Random Access Memory (RAM), the device comprising: a plurality of logic array blocks, each of the logic array blocks comprising a plurality of logic elements and an embedded RAM memory block that is addressable by the plurality of logic elements; a plurality of multiplexers adapted to drive output signals from the plurality of logic array blocks onto a selected portion of a plurality of global signal lines; an embedded array block logic array block (EAB LAB), wherein the EAB LAB is adapted to provide a plurality of signals via the global signal lines to the plurality of logic array blocks and their respective RAM memory blocks, the global signal lines adapted to: in a first configuration of the programmable logic device, provide address signals that, at least in part, specify a location in at least one RAM memory block, the location that is adapted to be either written to or read from; and in a second configuration of the programmable logic device, provide a plurality of input signals to a plurality of inputs of at least one logic element.