Patent ID: 6859377

Claim:
A dynamic associative memory device, comprising: a word line; a pair of first bit line (BL) and second bit line (/BL) which has signal potentials opposite to the first bit line; a plurality of memory cells, wherein each of the memory cells includes; a data-storing capacitor connected to the first bit line or the second bit line through first transmission gate capable of being switched to ON-state in accordance with an activation of the word line, and having a cell plate supplied with a source voltage; and at least one second transmission gate provided in series between the first bit lines and the second bit line, capable of being switched to ON-state in response to a memory node potential at an opposite side of a source voltage supply-side of the data-storing capacitor; and a memory cell initializing circuit for controlling the memory node potential upon receiving a reset signal so that at least one of the second transmission gates is switched to OFF-state.