Patent ID: 7372719

Claim:
A DRAM semiconductor memory device comprising: a plurality of memory cells, each memory cell including a selection transistor and a storage capacitor, the plurality of memory cells being arranged in a memory cell array with bit lines and word lines, wherein a drain region of each selection transistor is connected to a respective bit line and a gate of each selection transistor is connected to a respective word line; a plurality of bit lines including at least a pair of first and second bit lines, wherein each of the first and second bit lines includes a memory cell connected to the bit line and a further memory cell connected to the bit line; a plurality of sense amplifiers including a sense amplifier being connected to the pair of first and second bit lines; and a driving circuit device connected to the gate of each further memory cell connected to the first and second bit lines, wherein the driving circuit is configured to simultaneously switch on the gates of the further memory cells in response to initiating a precharge operation for charging the pair of first and second bit lines to an equalization voltage.