Patent ID: 8604849

Claim:
A phase locked loop comprising: a phase frequency detector (PFD) configured to detect a phase difference and a frequency difference between inputs of a reference clock signal and a feedback clock signal, wherein the PDF is configured to output an up signal based on at least the reference clock signal and output a down signal based on at least the feedback clock signal; a logic gate including an AND gate with an inverted input and a non-inverted input, wherein one of the up signal or the down signal from the PFD is coupled to the inverted input and the other signal is coupled to the non-inverted input, wherein the AND gate is configured to logically combine the inverted input and the non-inverted input to produce a pulse signal; and a time to digital converter (TDC) coupled to the logic gate wherein the pulse signal output from the AND gate is input to the TDC as an enable signal for the TDC, and wherein the TDC is configured to generate a digital timing signal representing a difference between two edges of the pulse signal; wherein the digital timing signal is configured to control an oscillator.