Patent ID: 7265396

Claim:
A semiconductor device including arrays of basic cells, each basic cell comprising: a source region; a drain region; a pair of gate electrodes; a source/drain region formed between the gate electrodes; a first contact area placed in the source region; a second contact area placed in the drain region; a third contact area placed in the each gate electrode; a fourth contact area placed in the source/drain region; a first wiring portion on a first wiring layer connected to the first contact area as a source terminal of a transistor, including a plurality of prospective grid points arranged in the direction of height of the cell, the plurality of prospective grid points corresponding to wiring grids for layout design and a via contact area can be placed on the each prospective grid point; a second wiring portion on the first wiring layer connected to the second contact area as a drain terminal of the transistor, including the plurality of prospective grid points arranged in the direction of height of the cell; a third wiring portion on the first wiring layer connected to the third contact area as a gate, terminal of the transistor, including the plurality of prospective grid points arranged in the height and width directions of the cell; and a fourth wiring portion on the first wiring layer connected to the fourth contact area as a source/drain terminal of the transistor, including the plurality of prospective grid points arranged in the height and width directions of the cell.