Patent ID: 7924185

Claim:
A semiconductor integrated circuit device comprising: a shift register configured to successively take in and hold input serial data on the basis of a first clock signal; at least one pattern detection section configured to detect at least one predetermined pattern contained in the serial data taken in the shift register; and a timing determination section configured to, when the serial data held in the shift register is output by being converted into parallel data by using a second clock signal having a speed lower than that of the first clock signal, determine timing of conversion from the serial data to the parallel data on the basis of a result of detection performed by the at least one pattern detection section, wherein the pattern detection section includes: a logic circuit configured to divide the predetermined pattern in the serial data into one or more first-group bits and second-group bits, and to determine whether or not the serial data input to the shift register coincides with the one or more first-group bits; and a determination section configured to determine whether or not the serial data input to the shift register coincides with the second-group bits, by checking the bits of the serial data one by one.