Patent ID: 8143078

Claim:
A method for monitoring an amount of metal contamination imparted into wafers during a semiconductor process, the method comprising: exposing at least one silicon-on-insulator structure to the semiconductor process, the silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the semiconductor process imparting metal contaminants in the silicon layer; evaluating metal contamination indicators of the silicon-on-insulator structures, the evaluation including: thermally annealing the silicon-on-insulator structure to cause the metal contaminants in the silicon layer to dissolve; cooling the silicon-on-insulator structure to form metal precipitates in the silicon layer; and detecting the metal precipitates, the detecting step creating pits, holes and/or cavities on the front surface of the silicon-on-insulator structure and involving directing light to the front surface of the silicon-on-insulator structure and detecting scattered reflected light; producing a first defect map by use of the scattered reflected light; verifying whether the amount of metal contaminants imparted into semiconductor wafers is acceptable by comparing the first defect map to a second defect map produced when the level of contamination was determined to be acceptable, the first and second defect maps being produced using substantially the same process conditions including the thermal anneal temperatures, the thermal anneal times, cooling rates and process for detecting the metal precipitates.