Patent ID: 8508017

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate on which a first region, a second region, and a third region are defined; isolation regions in the first region, the second region, and the third region of the semiconductor substrate; a plurality of active regions in the first region and the third region separated from one another by the isolation regions; a plurality of gate lines in the first region and the third region of the semiconductor substrate overlapping a part of the active regions and a part of the isolation regions; an interlayer insulating layer in the first region, the second region, and the third region of the semiconductor substrate covering the whole surface of the semiconductor substrate; a plurality of shared contacts in the first region and the second region penetrating the interlayer insulating layer, the shared contacts contacting the active regions and the gate lines in the first region and contacting the isolation regions in the second region; and a plurality of nodes in the first region, the second region, and the third region, the nodes being electrically connected to the shared contacts on the interlayer insulating layer in the first region and the second region and being apart from the gate lines and the active regions on the interlayer insulating layer in the third region.