Patent ID: 8631194

Claim:
An electronic device comprising a memory control circuit that controls a DRAM, wherein the memory control circuit performs: a first distributed refresh process for issuing refresh commands to the DRAM at a predetermined interval so that storage elements of which the DRAM is configured are refreshed at least once in a predetermined period Ts; a concentrated refresh process for issuing, triggered by a predetermined request which is different from refresh commands to the DRAM, a predetermined number of times Nc of burst refresh commands in a burst having been issued in the concentrated refresh process at an interval in the predetermined period Ts that is shorter than the predetermined interval; and a second distributed refresh process for, when the predetermined number of times Nc of refresh commands have been issued and a concentrated refresh process has been performed in the predetermined period Ts, calculating a refresh interval Tr for refreshing remaining storage elements to the DRAM that have not yet been refreshed in the predetermined period Ts and issues refresh commands at the calculated refresh interval Tr.