Patent ID: 7369133

Claim:
A graphics subsystem, comprising: a memory controller to service memory requests issued by a plurality of graphics clients to a graphics memory with each memory request having an associated data transfer size, the memory controller providing a non-partitioned view of said graphics memory to a the plurality of graphics clients while dividing a graphics memory access bus into individual memory bus partitions, each of which is a fraction of the graphics memory access bus size, said memory controller partitioning information within said graphics memory into a plurality of independently accessible memory partitions operable to service a memory request independently of the other memory partitions, said memory controller routing data between said plurality of independently accessible memory partitions and said plurality of graphics clients via said individual memory bus partitions, said memory controller determining which memory requests are to be serviced in particular clock cycles via one or more of said independently accessible memory partitions and said individual memory bus partitions; wherein said plurality of graphics clients submit variable data transfer size memory requests to the memory controller and said memory controller identifies individual memory requests requiring a subset of said independently accessible memory partitions and determines if another memory request can be serviced in parallel via another subset of said independently accessible memory partitions to improve throughput.