Patent ID: 8373272

Claim:
An integrated circuit device comprising: a semiconductor substrate; a plurality of active MOS devices formed on the semiconductor substrate; an interlayer dielectric layer overlying the plurality of active MOS devices; at least six patterned metal layers formed within the interlayer dielectric layer; at least one single metal bonding pad formed in a top patterned metal layer and located directly over at least one of the active MOS devices, the metal bonding pad being coupled to one or more patterned metal layers thereunder; and a passivation layer having an opening formed over the at least one single metal bonding pad; and a buffer-metal-layer free region disposed between the plurality of active MOS devices and the at least one single metal bonding pad, the buffer-metal-layer free region being free of a buffer-metal-layer within the interlayer dielectric layer cracks directly below a bonding area; and wherein the interlayer dielectric layer is substantially free of.