Patent ID: 8310268

Claim:
A method, comprising: parsing a hierarchy of an electrical reference model that comprises one or more reference modules; processing a description file that specifies relationships between ports of instances within an electrical design model and corresponding ports of the one or more reference modules of the electrical reference model, wherein the description file includes one or more names, wherein the one or more names respectively correspond to one or more implicit defines, wherein each of the one or more implicit defines includes a path through the hierarchy of the electrical reference model to a respective one of the one or more reference modules; and dependent on said processing, generating a test bench for verifying the electrical design module; wherein the test bench is computer-executable to: drive one or more input ports of the electrical design module with values presented to one or more corresponding ports of the electrical reference model; check, on a clock-cycle basis, one or more output ports of the electrical design model against one or more corresponding ports of the electrical reference model; and record, for each given one of the one or more output ports, an indication of whether the given output port matches a corresponding port of the electrical reference model.