Patent ID: 8040746

Claim:
A zero leakage read only memory (ROM) including a memory array, the memory array comprising a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of memory cells, wherein each of the plurality of memory cells are connected to a plurality of word lines, comprising: one or more address decoders for selecting at least one of the plurality of bit lines and word lines; a plurality of sense amplifiers for sensing the plurality of bit lines, wherein each of the plurality of sense amplifiers is associated with a corresponding bit line of the plurality of bit lines; a reference word line column for vertical tracking of the at least one of the plurality of word lines using a first predefined loopback; a reference bit line column comprising a reference bit line for vertical tracking of at least one of the plurality of bit lines using a second predefined loopback; and a control circuit comprising: a precharge generator for generating a precharge signal that pre-charges the reference bit line and at least one of the plurality of bit lines to a first predefined threshold voltage; a word line clock generator for generating a word line enable signal based on voltage of the bit line and the reference bit line reaching the first predefined threshold voltage; and a sense amplifier enable generator for activating the sense amplifier of the plurality of sense amplifiers for performing a read operation.