Patent ID: 7212598

Claim:
A method of regenerating an output clock signal for controlling the coupling of received data to an output port therefor comprising the steps of: (a) clocking said received data into a first in, first-out (FIFO) storage buffer in accordance with an input clock signal associated with said received data signal and a data valid signal representative of valid received data; (b) coupling said input clock signal to a multitap delay line, having outputs that provide respectively different phase delayed versions of said input clock signal; (c) coupling one of said outputs of said multitap delay line to said output port from which said output clock signal is derived, said output clock signal being coupled to said FIFO storage buffer to clock out data therefrom; (d) controllably coupling to said output port an output of said multitap delay line that provides a later-in-time delay relative to said one of said outputs of said multitap delay line, in response to said output clock signal exhibiting a clock frequency that is higher than the effective frequency of said valid data signal, thereby reducing the frequency of said output clock signal, or controllably coupling to said output port an output of said multitap delay line that provides an earlier-in-time delay relative to said one of said outputs of said multitap delay line, in response to said output clock signal exhibiting a clock frequency that is lower than the frequency of said valid data signal, thereby increasing the frequency of said output clock signal.