Patent ID: 7697330

Claim:
A non-volatile memory array for a field-programmable-gate-array device having drain-side segmentation and comprising: a plurality of memory cells arranged as an array of rows and columns, the array divided into a plurality of segments, each segment including a plurality of rows, each memory cell including a non-volatile memory transistor having a source, a drain, a floating gate, and a control gate, the source of each non-volatile memory transistor in each segment coupled together to a common source line, the non-volatile memory transistors in each segment being formed in a well associated only with that segment; at least one switch transistor associated with each non-volatile memory transistor, the at least one switch transistor having a source, a drain, a floating gate and a control gate and wherein each non-volatile memory transistor shares a floating gate with its associated at least one switch transistor; a column line associated with each column in the array; a column segment line associated with each segment of the array, each column segment line coupled to the drains of each non-volatile memory transistor in the segment; a segment select transistor coupled between each column segment line and its associated column line; and a high-voltage driver transistor coupled to each column line.