Patent ID: 8484590

Claim:
A computerized software implemented method to identify both specific floating transistor gates and causes of said specific floating transistor gates in an electronic circuit design comprising a plurality of electrically interconnected transistors, said method comprising: obtaining said electronic circuit design; using at least one computer processor to perform the steps of: for at each transistor gate of a plurality of transistor gates for which an analysis is desired, performing a logic expansion to create a logic tree representation of a previous level of predecessor circuit portions that drive a state of said each transistor gate, and determining if any states of predecessor nodes in the previous level of the predecessor circuit portions show up more than once with different values such a logical conflict indicates said each transistor gate does not float; repeating said logic expansion for next previous levels of the predecessor circuit portions, seeking logical conflicts within the expanding logic tree representation, until it can be determined that either no predecessor circuit portion can cause said each transistor gate to float, or until a predecessor circuit portion that does cause said each transistor gate to float is identified; and if such predecessor circuit portion that does cause said each transistor gate to float is identified, reporting an identity of said each transistor gate as a probable floating gate.