Patent ID: 7109552

Claim:
A self-aligned trench DMOS transistor structure, comprising: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a lightly-doped epitaxial semiconductor layer being formed on a heavily-doped semiconductor substrate; a source region being formed in the lightly-doped epitaxial semiconductor layer surrounded by a trench gate region, wherein the source region comprises a base diffusion region of a second conductive type, a self-aligned heavily-doped contact diffusion region of the second conductivity type being formed in a middle surface portion of the base diffusion region through a first self-aligned implantation window, a self-aligned heavily-doped source diffusion ring of the first conductivity type being formed in an outer surface portion of the base diffusion region and on an outer surface portion of the self-aligned heavily-doped contact diffusion region through a second self-aligned implantation window, and a self-aligned source contact window being formed by a semiconductor surface of the self-aligned heavily-doped contact diffusion region surrounded by the self-aligned heavily-doped source diffusion ring and an inner semiconductor surface of the self-aligned heavily-doped source diffusion ring; the trench gate region being formed in the semiconductor substrate with a shallow trench depth being formed slightly larger than a junction depth of the moderately-doped base diffusion region and within the lightly-doped epitaxial semiconductor layer, wherein the trench gate region further comprises a gate oxide layer being formed over a trenched semiconductor surface, a highly conductive composite gate layer being formed over the gate oxide layer and an etched-back capping oxide layer being formed on the highly conductive composite gate layer; and a source metal layer being at least formed on the self-aligned source contact window in the source region and on the etched-back capping oxide layer in the trench gate region.