Patent ID: 8327205

Claim:
A method of testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies, the method comprising: during a first scan mode, providing a test signal to the circuit using a clocked scan chain clocked at a test frequency; ending the first scan mode; subsequently providing a transition in a clock circuit reset signal; using the transition in the clock circuit reset signal to trigger the operation of a clock divider circuit which derives the first and second clock signals from an internal clock of the integrated circuit, such that the first and second clock signals start at substantially the same time; during a test mode, performing a test of the integrated circuit with the at least two cores being clocked with timing derived from the first and second clock signals; and ending the test mode, and starting a second scan mode during which a result to the test signal is output using the clocked scan chain clocked at the test frequency.