Patent ID: 7380109

Claim:
An apparatus, for extending address modes within a microprocessor, the apparatus comprising: hardware translation logic, configured to translate an extended instruction into an associated micro instruction sequence for execution by the microprocessor, wherein said extended instruction has been fetched from external memory, and wherein said extended instruction comprises: an extended prefix, configured to allow for specification of one of a plurality of extended address modes for address calculation corresponding to an operation, wherein said each of said plurality of extended address modes correspond to one of a plurality of address sizes, and wherein said each of said plurality of extended address modes is not otherwise provided for by instructions in an existing instruction set; an extended prefix tag, configured to indicating said extended prefix, wherein said extended prefix tag comprises a first opcode within said existing instruction set, and wherein in said first opcode otherwise specifies a first operation according to said exhisting instruction set; and instruction entities according to said existing instructionset, wherein said extended prefix and said extented prefix tag precede said instruction entities in said extended instruction, and wherein said instruction entities comprise a second opcode that prescribes said operation to be executed by the microprocesser; and extended execution logic, coupled to said translation logic, for receiving said associated micro instruction sequence, and for performing said address calculation to generate an extended address according to said one of a plurality of extended address modes.