Patent ID: 8587341

Claim:
A portion of an integrated circuit having geometric features defined at a resolution of 28 nm or less, said features corresponding to at least active, poly, first metal, and second metal layers, said integrated circuit portion comprising at least: a continuous region of at least 100×100 um 2 tiled with abutting baseTemplate frames, each baseTemplate frame defined on either side by adjacent, minimum-spaced poly tracks and on top and bottom by opposing positive and negative supply rails in the first or second metal layer; each of said baseTemplate frames containing at least some geometric features in each of the active, poly, first metal, and second metal layers; said continuous region characterized in that: (i) the poly layer features within said continuous region exhibit a template regularity metric of greater than 90%; (ii) the first metal layer features within said continuous region exhibit a template regularity metric of greater than 50%; and, (iii) the second metal layer features within said continuous region exhibit a template regularity metric of greater than 50%; said continuous region also including: (a) at least two distinct types of special connectors, each instantiated within fewer than 5% of said baseTemplate frames, each of said special connector types comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame; and, (v) cells implementing at least six distinct logic functions.