Patent ID: 7616075

Claim:
A circuit, comprising: a voltage regulator configured to provide an output voltage; a phase frequency detector configured to compare phases and frequencies between a reference clock and a feedback clock, and outputs a clock resulting from the comparison on an output; a charge pump configured to output an electric charge in accordance with the output from the phase frequency detector; a first path setting section configured to couple the output of the phase frequency detector to the voltage regulator in a first mode of operation such that the output voltage of the voltage regulator is based on the output of the phase frequency detector in the first mode of operation, couple the output of the phase frequency detector to the charge pump in a second mode of operation and switch between the first mode of operation and the second mode of operation; a low pass filter configured to store the electric charge injected from the charge pump to output a first control voltage on an output; a control-voltage generating circuit configured to output a second control voltage on an output, wherein the second control voltage is obtained by dividing the output voltage of the voltage regulator; a voltage controlled oscillator configured to output an output clock; a second path setting section configured to couple the output of the control-voltage generating circuit to the voltage controlled oscillator in a first mode of operation, couple the output of the low pass filter to the voltage controlled oscillator in a second mode of operation and switch between the first mode of operation and the second mode of operation such that the voltage controlled oscillator produces the output clock in accordance with the second control voltage and the output voltage of the voltage regulator in the first mode of operation and the voltage controlled oscillator produces the output clock in accordance with the first control voltage and the output voltage of the voltage regulator in the second mode of operation; and a divider configured to output the feedback clock, wherein the feedback clock is obtained by dividing the output clock of the voltage controlled oscillator to the phase frequency detector.