Patent ID: 7516032

Claim:
A method for providing improved resolution in measuring the pulse width of digital signals, comprising the steps of: counting the integral number of measuring clock pulses covered by said digital pulse, triggering a chain of serially coupled inverters coupled to the measuring clock, operable to receive the pulse, and operable to measure a portion of the duration of the pulse, a first one of the inverters operable to transition an output signal in response to an edge of the clock signal, and one or more subsequent inverters each operable to transition a respective output signal in response to a transition of an output signal from a previous one of the inverters, each of the first and subsequent inverters having a respective delay, the sum of the delays being greater than one half of the time period of the clock signal and less than the time period of the clock signal; determining a delay count based on the number inverters that have been triggered; measuring the delay count obtained from said chain of inverters from the leading or trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adding said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.