Patent ID: 7370265

Claim:
A MLC LDPC (Multi-Level Code Low Density Parity Check) encoder that is operable to generate an LDPC coded signal, the encoder comprising: an MLC LDPC encoder that is operable to encode a plurality of bits thereby generating an MLC block that include a plurality of levels; a symbol mapper that is operable to: generate a first symbol that includes a first bit from a first level of the plurality of levels of the MLC block and a second bit from a second level of the plurality of levels of the MLC block; generate a second symbol that includes a third bit from the first level of the plurality of levels of the MLC block and a fourth bit from the second level of the plurality of levels of the MLC block; symbol map the first symbol to a first constellation having a corresponding first mapping; and symbol map the second symbol to a second constellation having a corresponding second mapping; and wherein: the LDPC coded signal includes the symbol mapped first symbol and the symbol mapped second symbol.