Patent ID: 7240256

Claim:
A semiconductor memory test apparatus which tests a memory device comprising: a test pattern generator which generates a test pattern signal and an expected value pattern signal; the test pattern signal being applied to the memory device whose memory area is constituted by a plurality of banks where addresses to the banks are generated automatically in a burst mode operation upon receiving a start column or start row address from the semiconductor memory test apparatus; a logic comparator which compares a response output signal of the memory device with the expected value pattern signal, and detects a result of a mismatch as a failure of a cell; a failure analysis memory which stores failure information at the same address as an address of the failure cell in the memory device; a failure analysis address generator which generates a failure analysis address which sets in the failure analysis memory the same address space as that in the memory device which is in the burst mode operation; and a register file block provided in the failure analysis address generator, the register file block having a plurality of registers corresponding to the respective banks of the memory device; wherein each register in the register file block corresponding to the bank outputs the row or column address to the failure analysis memory which is the same column or row address as that automatically generated in the memory device after the start column or start row address at each clock cycle in the burst mode operation of the bank.