Patent ID: 7047508

Claim:
A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a sequential logic circuit including a first sequential logic gate, a combinational logic circuit, and a second sequential logic gate, wherein an output signal outputted from the first sequential logic gate is transmitted to the second sequential logic gate via a plurality of signal transmission paths of the combinational logic circuit; one of a plurality of source clock signals is selected and then inputted to a clock input terminal of the first sequential logic gate; and one of a plurality of destination clock signals is selected and then inputted to a clock input terminal of the second sequential logic gate, the method comprising the steps of: determining a plurality of source-to-destination edge time margins which are the time difference between a rising/falling edge of each destination clock signal and the rising/falling edge of each source clock signal, the selection of the rising edge or the falling edge of the clock signals are determined according to the characteristics of the corresponding sequential logic gate; selecting a smallest edge time margin from the source-to-destination edge time margins, wherein the smallest edge time margin is associated with one of the source clock signals and one of the destination clock signals; and determining whether a timing violation occurs on the signal transmission paths by performing static timing analysis on the sequential logic circuit using the source clock signal and the destination clock signal which both are associated with the smallest edge time margin, wherein if no timing violation occurs, the sequential logic circuit is verified, that when the sequential logic circuit receiving any other one of the source clock signals and any other one of the destination clock signals, the timing violation will not occur, whereby the static timing analysis is accomplished efficiently.