Patent ID: 7618891

Claim:
A method for forming a semiconductor structure comprising: providing a semiconductor substrate including a first device region comprising a silicon-containing semiconductor material, a second device region comprising said silicon-containing semiconductor material, and a dielectric isolation region laterally abutting said first device region and said second device region and located in said semiconductor substrate; forming a metal alloy layer over said first device region and said second device region and said dielectric isolation region, wherein said metal alloy layer comprises nickel and at least one additional metal; annealing at a first annealing temperature ranging from about 150° C. to about 500° C., wherein nickel contained in said metal alloy layer reacts with silicon contained in said first device region and said second device region to form nickel silicide of a first phase over said first device region and said second device region, wherein said first annealing temperature is selected so that said at least one additional metal in said metal alloy layer does not react with silicon contained in said first device region and said second device region to form a silicide of said at least one additional metal and remains as an unreacted at least one additional metal within said nickel silicide of said first phase; selectively etching said metal alloy layer using a first etching solution to remove substantially all un-reacted nickel from said dielectric isolation region between said first device region and said second device region, wherein said unreacted at least one metal remains over said dielectric isolation region; annealing at a second annealing temperature ranging from about 300° C. to about 600° C., wherein said nickel silicide of said first phase further reacts with silicon contained in said first device region and said second device region to form nickel silicide of a second phase over said first device region and said second device region, wherein the second phase has a lower resistivity than the first phase, and wherein said second annealing temperature is selected so that said unreacted at least one additional metal in said nickel silicide of said first phase reacts with silicon contained in said first device region and said second device region to form a silicide of said at least one additional metal within said nickel silicide of said second phase during formation of said nickel silicide of said second phase; and selectively etching stringers of said at least one additional metal using a second etching solution to remove substantially all of said at least one additional metal from an upper surface of said dielectric isolation region, thereby forming self-aligned metal silicide contacts that are electrically isolated from each other.