Patent ID: 7489158

Claim:
A plurality of feedback sub-circuits for providing line load compensation and reflection reduction in a signal transmitting circuit, each said plurality of feedback sub-circuits comprising: a first transistor, a second transistor and a third transistor, an emitter of said first transistor and a collector of said second transistor being connected to a base of said third transistor at a first node, a base of said second transistor being connected to an emitter of said third transistor at a second node; a feedback capacitor having a first lead connected to a base of said first transistor at a third node, and said feedback capacitor having a second lead connected to a collector of said third transistor at a fourth node; and wherein said feedback capacitor has a capacitance selected to produce a constant rise/fall time regardless of a load of an input received from said signal transmitting circuit and reduces reflection, said constant rise/fall time of said feedback capacitor being equal to a predetermined fractional value of a transmission bit time of said signal transmitting circuit, said bit transmission time being based on a baud rate and a maximum transmission line length.