Patent ID: 7840932

Claim:
A method for fabricating an integrated circuit using photolithography equipment for imaging dense and isolated features having a critical dimension, comprising: in a first imaging process, imaging integrated circuit dense and isolate features having the critical dimension by passing radiation through a reticle onto one or more radiation sensitive layers of one or more wafers, to provide a plurality of shots made at respective focus offsets of different magnitudes and directions from a given focus; establishing a dense and isolate feature critical dimension bias correlation for the shots made in the first imaging process; determining an offset direction for subresolution assist features imaged in the shots made in the first imaging process; in a second imaging process, imaging the integrated circuit dense and isolate features having the critical dimension by passing radiation through the reticle onto a radiation sensitive layer of a production wafer; determining a defocus condition in the second imaging process; determining an amount and direction of focus correction needed for the second imaging process based on the dense and isolate feature critical dimension bias correlation and the imaged subresolution assist feature offset direction; adjusting the focus for the second imaging process based on the determined amount and direction of focus correction needed; and repeating the second imaging process for another wafer using the adjusted focus.