Patent ID: 8044464

Claim:
A semiconductor device comprising: a substrate having an insulating surface; a first transistor having a first semiconductor layer, a first gate insulating layer and a first gate electrode layer, over the substrate having the insulating surface; a first insulating film which covers the first transistor; an interlayer insulating layer over the first insulating film; a second transistor having a second semiconductor layer, a second gate insulating layer and a second gate electrode layer, over the interlayer insulating layer; and a second insulating film which covers the second transistor, wherein the first semiconductor layer is bonded to the substrate having the insulating surface with a first insulating layer, wherein the second semiconductor layer is bonded to the interlayer insulating layer with a second insulating layer, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, and wherein the second insulating film has a compressive stress, and a channel formation region of the second semiconductor layer is distorted due to the compressive stress of the second insulating film.