Patent ID: 7583485

Claim:
An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) having integrated first and second electrostatic discharge protection components, comprising: a first electrostatic discharge (ESD) protection component that has a multi-fingered structure; and a second electrostatic discharge (ESD) protection component coupled in series to said first electrostatic discharge (ESD) protection component that is approximately one half the size of said first electrostatic discharge (ESD) protection component, wherein said first electrostatic discharge (ESD) protection component and said second electrostatic discharge (ESD) protection component are integrated and coupled via a buried layer to buried layer region wherein a first buried layer is formed underneath a p-well region of said first electrostatic discharge (ESD) protection component and a second buried layer region is formed underneath an n-sinker region of said second electrostatic discharge (ESD) protection component, and wherein a snapback holding voltage of said electrostatic discharge protection circuit is greater than an operating voltage of said electrostatic discharge protection circuit and a snapback condition is not sustained by said operating voltage and wherein a snapback trigger voltage of said electrostatic discharge protection circuit is lower than an oxide breakdown voltage of said IC and is different from said snapback holding voltage.