Patent ID: 7084072

Claim:
A method of manufacturing a semiconductor device, the method comprising the steps of: i) forming a gate in a cell region and a peripheral region formed on a silicon substrate, respectively; ii) depositing a buffer oxide layer on the gate and the silicon substrate; iii) annealing a resultant structure of the silicon substrate by using NH 3 in such a manner that the buffer oxide layer is nitrified while forming a nitride layer thereon, and diffusing nitrogen into the buffer oxide layer such that a oxynitride layer is formed in the buffer oxide layer, thereby enhancing an interfacial surface characteristic between the buffer oxide layer and the silicon substrate; iv) depositing a nitride spacer layer on the buffer oxide layer; v) depositing an oxide spacer layer on the nitride spacer layer; vi) forming an oxide spacer at the peripheral region of the silicon substrate by etching an entire surface of the oxide spacer layer while masking the cell region of the silicon substrate; and vii) removing the oxide spacer layer remaining in the cell region through a wet dip process by using the nitride spacer layer as an etch barrier while masking the peripheral region of the silicon substrate.