Patent ID: 7600206

Claim:
A method of estimating signal delay in a VLSI circuit, comprising: inputting a file interconnect circuit parasitic parameter, a signal transition time, a logic cell library, and a circuit structure of an original system to a file data read system; for each network interconnect system, analyzing structure of a specific target interconnect circuit and calculating a system moment of the specific target interconnect circuit which is applied to calculation of an equivalent capacitance and construction of a projection matrix; in recursion moment operation, a circuit moment of each node in the specific target interconnect circuit being obtained in linear time, and the projection matrix being further constructed; in construction of a reduced model, determining whether an amount of nodes in the specific target interconnect circuit is higher than a default order; when higher than the default order, applying a sparse matrix to store the file interconnect parasitic circuit parameter of the original system; and applying sparse matrix multiplication to obtain a final reduced model for analysis of a signal time domain that is simulated by a simulation system; with the final reduced model staying passive and stable and having an operation condition of input and output nodes identical to that of the original system; contrarily, when less than the default order, constructing a Modified Nodal Analysis matrix system directly corresponding to a Modified Nodal Analysis matrix system representing a current and voltage behavior pattern for analysis of the time domain simulation; with the analysis of the signal time domain simulation, calculating an equivalent capacitance loaded by a drive element and applying a table look-up to obtain an output signal of an input interconnect circuit structure; with the analysis of the signal time domain simulation, making a time domain simulation for the Modified Nodal Analysis matrix system and then off analyzing for a drive logic gate delay time, an interconnection circuit delay time, and a output signal conversion time; and determining whether a interconnect network system has not been processed; if yes, returning the structure of the specific target interconnect circuit to analyze a next signal from an interconnect circuit; and if not, making final the system delay estimation.