Patent ID: 7831877

Claim:
A chip comprising: first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during capture periods; and circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal; wherein the circuitry to provide the first and second test clock signals includes: a first test clock circuit including a first delay circuit and a first multiplexer to pass a first delay clock signal as the first test clock signal during the scan input periods, the first delayed clock signal being a scan shift clock signal delayed by at least the first delay circuit, and pass a first capture clock signal as the first test clock signal during the capture periods; and a second test clock circuit coupled with the first test circuit including a second delay circuit and a second multiplexer to pass a second delayed signal as the second test clock signal during the scan input periods, the second delayed clock signal being the first delayed clock signal from the first test clock circuit delayed additionally by at least the second delay circuit, and pass a second capture clock signal as the second test clock during the capture periods.