Patent ID: 7560962

Claim:
A device comprising: a clock circuit generating a reference signal; a component generating a plurality of digital values; a processor processing said plurality of digital values; and a phase lock loop (PLL) receiving said reference signal and generating an external signal which drives operation of one of said component and said processor, said PLL containing a divider which receives said external signal as an input signal and generates a divided signal as an output signal, said output signal having a first frequency and said input signal having a second frequency, wherein said first frequency equals a non-integer fraction represented by (M+F) of said second frequency, wherein M represents an integer and F represents a fraction, said divider comprising: a multi-phase generator circuit generating a plurality of intermediate signals from said input signal, said plurality of intermediate signals which are relatively phase shifted with respect to each other; a selection circuit selecting as a selection output a first intermediate signal in a first cycle of said input signal, a second intermediate signal in a Mth cycle of said input signal, and any of said plurality of intermediate signals in the remaining ones of the M cycles of said input signal, said selection circuit comprising: a multiplexer which receives said plurality of intermediate signals and selects one of said plurality of intermediate signals in a corresponding one of said plurality of M cycles according to a corresponding control value; a controller receiving said input signal and providing said control values in said M cycles of said input signal, wherein said selection circuit spreads said phase shift of F times of said time period in a plurality of said M cycles and selects first Q of said plurality of intermediate signals which are successively phase shifted by 1/Rth of said time period and selects the same signal as that selected in Qth cycle, thereafter in the remaining (M-Q) cycles, wherein said first intermediate signal and said second intermediate signal are contained in said plurality of intermediate signals, wherein said second intermediate signal is phase shifted by a magnitude of F times the time period of said input signal in comparison to said first intermediate signal and F equals Q/R. wherein Q and R represent integers, wherein each of said plurality of intermediate signals are equally phase shifted by 1/Rth of said time period; and a counter counting a number of state changes on said selection output, wherein an edge of said output signal is generated every instance said counter counts M cycles in said selection output.