Patent ID: 7177985

Claim:
A microprocessor coupled to a system memory, the microprocessor comprising: a memory subsystem, having a plurality of cache memories for caching data received from the system memory; an instruction decode unit, coupled to said memory subsystem, for decoding an instruction, said instruction specifying a data stream in the system memory and a parameter, said parameter specifying one of said plurality of cache memories; a stream prefetch unit, coupled to said memory subsystem, for generating one or more prefetch requests to said memory subsystem to prefetch a cache line of said data stream from the system memory into said one of said plurality of cache memories specified by said parameter; and a load unit, coupled to said memory subsystem, for generating a load request, including an address, to said memory subsystem to load data specified by said address from the system memory into the microprocessor; wherein said instruction specifies a fetch-ahead distance, wherein said stream prefetch unit monitors said load request to determine when said address hits in said data stream, wherein said stream prefetch unit generates said one or more prefetch requests such that said data stream is prefetched into said one of said plurality of cache memories at least said fetch-ahead distance ahead of said load request address hitting in said data stream; wherein if a difference between an address of said one or more prefetch requests and said load request address hitting in said data stream is more than said fetch-ahead distance, said stream prefetch unit suspends generating said one or more prefetch requests.