Patent ID: 8665628

Claim:
A ferroelectric memory device, comprising: a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of plate lines; a plurality of memory cells which are disposed at the positions of intersection of the word lines and bit lines, and which respectively have an access gate which connects to the word line and the bit line, and a ferroelectric capacitor provided between the access gate and the plate line; a latch amplifier, which latches stored data according to an amount of charge output to the bit lines from the ferroelectric capacitors; and a write amplifier, which drives the bit lines according to write data or according to the latched stored data, wherein the bit lines are precharged to a reference potential by beginning of an active period; in the active period, at a first time a selected word line of the plurality of word lines is driven according to an input address, and the plate line is driven from the reference potential to a high-level potential being higher than the reference potential so that the ferroelectric capacitor is caused to output electric charge to a selected bit line of the plurality of bit lines, and thereafter at a second time, the selected bit line is brought to the reference potential regardless of the write data or the latched stored data so that first data is written to a selected memory cell of the plurality of memory cells, and thereafter at a third time, the plate line is driven to the reference potential and is maintained at the reference potential together with the selected bit line; and in a precharge period after the active period, the write amplifier drives the selected bit line from the reference potential to the high-level potential when the write data or the latched stored data is high-level so that second data is written to the selected memory cell.