Patent ID: 7103792

Claim:
An information processing system, comprising: first and second modules each comprising a semiconductor integrated circuit; a clock generator for generating a first clock signal to be applied to the modules; a chipset comprising a zero-delay clock buffer configured to generate second and third clock signals from the first clock signal to control the modules; a first clock line configured to transfer the first clock signal to the zero-delay clock buffer, said first clock line comprising a first segment and a second segment, wherein a first end of the first segment is connected to the clock generator, wherein a second end of the first segment and a first end of the second segment are commonly connected to the zero-delay clock buffer, and wherein a second end of the second segment is connected to a first termination circuit; a second clock line, electrically isolated from the first clock line, configured to transfer the second clock signal to the modules, wherein a first end and a second end of the second clock are connected respectively to the zero-delay clock buffer and a second termination circuit; and a third clock line, electrically isolated from the first clock line, configured to transfer the third clock signal, wherein a first end and a second end of the third clock line are respectively connected to the zero-delay clock buffer and a third termination circuit.