Patent ID: 8139400

Claim:
A memory circuit comprising: a plurality of bit line structures, each of said bit line structures comprising a true bit line and a complementary bit line; a plurality of word lines structures intersecting said plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at said plurality of cell locations, each of said cells comprising: a logical storage element; a first access transistor selectively coupling a given one of said true bit lines to said logical storage element, wherein a current from said logical storage element to said given one of said true bit lines is higher than a current from said given one of said true bit lines to said logical storage element; and a second access transistor selectively coupling a corresponding given one of said complementary bit lines to said logical storage element, wherein a current from said logical storage element to said corresponding given one of said complementary bit lines is higher than a current from said corresponding given one of said complementary bit lines to said logical storage element; wherein at least one of said first and second access transistors comprises an asymmetric access transistor configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins.