Patent ID: 8487383

Claim:
A flash memory device, comprising: a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well; a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, the first peripheral region including: an LV NMOS region where an NMOS transistor for the LV switch is disposed, an LV PMOS region where a PMOS transistor for the LV switch is disposed, an HV NMOS region where an NMOS transistor for the HV switch is disposed, and an HV PMOS region where a PMOS transistor for the HV switch is disposed; and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches, the second peripheral region including an HV PMOS region where an NMOS transistor for an HV bulk voltage switch is disposed, the HV PMOS region including a pocket p-well configured to accommodate the NMOS transistor for the HV bulk voltage switch and an n-well configured to surround the pocket p-well.