Patent ID: 7804326

Claim:
A voltage level shifter, comprising: a voltage adjustment circuit configured for receiving a first voltage and a second voltage and for generating an adjustment voltage; an inverter configured for receiving an input signal and for operating at the first voltage; a first NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to an output signal, and a source connected to a reference voltage; a second NMOS transistor having a gate connected to the first voltage and a source connected to the output terminal of the inverter; a first PMOS transistor having a gate connected to the output signal, a drain connected to a drain of the second NMOS transistor, and a source connected to the adjustment voltage; and a second PMOS transistor having a gate connected to the drain of the second NMOS transistor, a drain connected to the output signal, and a source connected to the adjustment voltage; wherein when the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.