Patent ID: 7612449

Claim:
A semiconductor device, comprising: a substrate comprising an upper substrate surface with an upper substrate ground trace and an upper substrate power trace; a lower substrate surface with a lower substrate ground trace, a lower substrate power trace, and a periphery; a substrate ground via electrically connecting the lower substrate ground trace to the upper substrate ground trace; and a substrate power via electrically connecting the lower substrate power trace to the upper substrate power trace; a die mounted on the upper substrate surface, the die having a first wire bond electrically connecting the die to the upper substrate ground trace, the die having a second wire bond electrically connecting the die to the upper substrate power trace; an array of solder balls attached to the lower substrate surface, the array comprising: a first set of ground solder balls that are positioned immediately next to the periphery; a second set of power solder balls; a power/ground solder ball pair composed of a first ball selected from the first set and a second ball selected from the second set, the first ball and the second ball being immediately next to each other, the first ball electrically connected to the lower substrate ground trace, and the second ball electrically connected to the lower substrate power trace; and wherein each ground solder ball on the lower substrate surface is positioned immediately next to the periphery, and wherein each power solder ball on the lower substrate surface is positioned immediately next to one of the ground solder balls.