Patent ID: 7085798

Claim:
An N-bit two level lookahead adder for adding two N-bit numbers, comprising summing means for calculating alternative partial M-bit sums; a first set of carry modules for generating g i , p i and k i signals for each of the N bits; a second set of carry modules, responsive to said g i , p i and k i signals, for generating a set of M-bit G, P and K signals therefrom, each of said second set of carry modules having a sense amplifier connected to a logic evaluation module containing two connecting nodes connected to said sense amplifier, two chains of source follower transistors having a first node, a final node and a set of intermediate nodes controllably connected to ground and to a reference voltage by first and second sets of connecting transistors, said final node of each of said chains being connected to one of said connecting nodes; first precharge means for precharging each of said set of two connecting nodes to ground; means for charging one of said connecting nodes to a reference voltage other than ground in an evaluation mode; and a set of output modules, responsive to said set of carry signals, for selecting alternative partial sums and connecting a selected set of said alternative partial sums to a set of output terminals.