Patent ID: 7515483

Claim:
A page buffer of a flash memory device including a memory cell array, the page buffer comprising: a first bit line selection unit configured to select one of at least one pair of first bit lines coupled to the memory cell array and to connect the selected bit line to a first sensing line; a second bit line selection unit configured to select one of at least one pair of second bit lines coupled to the memory cell array and to connect the selected bit line to a second sensing line; a separation unit configured to disconnect the first sensing line and the second sensing line during a programming operation such that memory cells of the memory cell array corresponding to the selected first bit line and the selected second bit line are simultaneously programmed, the separation unit further configured to connect the first sensing line and the second sensing line during a cache program operation; a precharge unit configured to precharge the first and second sensing lines; a first register coupled to the first bit line selection unit through the first sensing line, the first register configured to latch a first input data; and a second register coupled to the second bit line selection unit through the second sensing line, the second register configured to latch a second input data, wherein the first input data and the second input data are simultaneously programmed in the memory cells corresponding to the selected first bit line and the selected second bit line, respectively, such that the first input data and the second input data are programmed in the corresponding memory cells on a two-page basis.