Patent ID: 8703508

Claim:
A method for wafer-level testing a plurality of diced multi-chip stacked packages, comprising the steps of: providing the plurality of multi-chip stacked packages where each multi-chip stacked package includes a plurality of chips vertically stacked together and has a top surface, a bottom surface, and a plurality of testing electrodes disposed on the top surface; fixing the multi-chip stacked packages on a transparent reconstructed wafer according to a die-on-wafer array arrangement wherein the transparent reconstructed wafer includes a plurality of component placement regions defined by a plurality of alignment marks and has a photosensitive adhesive adhered to the bottom surfaces of the multi-chip stacked packages to locate the multi-chip stacked packages within the component placement regions, wherein the transparent reconstructed wafer further has a barcode of wafer ID disposed at an edge of the transparent reconstructed wafer outside the component placement regions; loading the transparent reconstructed wafer with the multi-chip stacked packages into a wafer tester; using a plurality of probes of a probe card installed in the wafer tester to probe the testing electrodes to electrically test the multi-chip stacked packages; and radiating light on the photosensitive adhesive through the transparent reconstructed wafer to pick up and sort out the multi-chip stacked packages.