Patent ID: 7138930

Claim:
A system for encoding/decoding multi-bit data values, comprising: a datapath for receiving a plurality of multi-bit input data values including a first input data value and at least one other input data value, the input data values have a predetermined order of significance, with the first input data value being the least significant input data value and a last input data value being a most significant input data value; a plurality of compute engines that compute different output values in response to an input value, each other input data value being input to least two corresponding compute engines; and a multiplexer (MUX) corresponding to each other input data value, each MUX having inputs that receive output values of the compute engines corresponding to the other input data value, each MUX having a select input coupled to an output of another MUX, the multiplexer corresponding to the most significant input data value provides a running disparity value that is coupled to a first compute engine that receives the least significant input data value.