Patent ID: 7992114

Claim:
A method comprising: receiving, at one or more processors associated with one or more computer systems, a timing requirement for a timing path in a chip design; estimating a first timing effect on the timing path that accounts for a random variation occurring independent of location within the chip design; estimating a second timing effect on the timing path that accounts for a systematic variation within the chip design; and selecting a margin for the chip design that satisfies the timing requirement after adjusting the timing path for the first timing effect and the second timing effect, wherein estimating the second timing effect includes: applying a correlation to a spatial partitioning of the chip design, the spatial partitioning including a plurality of bins, the correlation correlating a variation of a first of the plurality of bins with a variation of a second of the plurality of bins, the correlation including a function of distance between the first and second bins along a power mesh of the design.