Patent ID: 8456924

Claim:
A semiconductor memory device comprising: a data alignment unit configured to align data, which are sequentially inputted, in response to a data strobe signal; a latching operation control unit configured to receive the data strobe signal, and generate a latching control signal in response to information indicating an interval between a write operation and a next write operation; a data latching unit configured to latch an output signal of the data alignment unit in response to the latching control signal; and a data synchronization output unit configured to synchronize output signals of the data latching unit in response to a plurality of data input strobe signals, and output the synchronized signals to a plurality of data lines, wherein the data synchronization output unit comprises: a first synchronization group configured to synchronize the output signals of the data latching unit in response to a first data input strobe signal among the data input strobe signals; and a second synchronization group configured to synchronize the output signals of the data latching unit with the output signals of the first synchronization group in response to a second data input strobe signal among the data input strobe signals, and output the synchronized signals to the plurality of data lines.