Patent ID: 8190867

Claim:
A processor comprising: a register file having a plurality of registers; a decoder coupled with the register file, the decoder to decode a first instruction, the first instruction having a 32-bit instruction format, the first instruction having a first field to specify a first source register of the register file having a first plurality of packed signed 16-bit integers and a second field to specify a second source register of the register file having a second plurality of packed signed 16-bit integers; and a functional unit including circuitry coupled with the decoder, the functional unit to generate a result according to the first instruction that is to be stored in a destination register specified by a third field of the first instruction, the result including a third plurality of packed 8-bit integers, the third plurality of the packed 8-bit integers including an 8-bit integer for each 16-bit integer in the first plurality of the packed signed 16-bit integers, and an 8-bit integer for each 16-bit integer in the second plurality of the packed signed 16-bit integers, the 8-bit integers corresponding to the first plurality of the packed signed 16-bit integers next to one another in the result, and the 8-bit integers corresponding to the second plurality of the packed signed 16-bit integers next to one another in the result, a highest order 8-bit integer of the result corresponding to a highest order 16-bit integer of the first plurality of the packed signed 16-bit integers, and a lowest order 8-bit integer of the result corresponding to a lowest order 16-bit integer of the second plurality of the packed signed 16-bit integers, and each 8-bit integer of the third plurality of the packed 8-bit integers including one of (a) a low order 8-bits of a corresponding 16-bit integer and (b) a saturation value.