Patent ID: 6954827

Claim:
A data processing system comprising: a processor; and a multi-way set-associative cache memory for storing data to be used by the processor, wherein the cache memory comprises: a data memory being divided into a plurality of data ways, the data memory for storing data to be used by the processor; a tag memory being divided into a plurality of tag ways, the tag memory for storing a tag address; and a cache size selector for selecting for operation those data ways among the plurality of data ways of the data memory and those tag ways among the plurality of tag ways of the tag memory that are determined to function normally, and excluding from operation those data ways among the plurality of data ways of the data memory and those tag ways among the plurality of tag ways of the tag memory having defective memory cells, the number of selected data ways of data memory being equal to the number of selected tag ways of tag memory, wherein the cache size selector receives a plurality of hit signals, each hit signal from a corresponding tag way, and outputs a plurality of selection signals, each selection signal corresponding to a data way, and wherein the cache size selector further comprises a selection signal designator that designates one hit signal among the plurality of hit signals from the corresponding selected tag ways for output as a selection signal for each of the plurality of selection signals corresponding to a selected data way.