Patent ID: RE41589

Claim:
A data processing system, comprising: a data processing unit; a memory which is divided into a plurality of banks such that an access is made to one of said banks at a time; a plurality of address registers coupled to said data processing unit, and corresponding to said plurality of banks; a comparator coupled to at least one of outputs from said address registers; and a controller coupled to said comparator , ; a first line for sending a row address strobe signal, which is shared with the plurality of banks, from the controller to the memory; a second line for sending a column address strobe signal, which is shared with the plurality of banks, from the controller to the memory; a third line for sending a bank signal, which is shared with the plurality of banks, from the controller to the memory; wherein said data processing unit accesses one of said banks , which is specified by the bank signal of the third line, for reading out data, and accesses another bank of said banks for writing data, wherein each of said plurality of address registers holds recently accessed addresses corresponding to said plurality of banks, wherein said comparator compares an access address for a bus access with contents of at least one of said address registers, when said data processing unit issues said bus access, and wherein said controller omits transfer of said access address to said memory in response to an indication of a coincidence by said comparator, when said bus access is a next bus access after a bus access to a different bank, said indication indicating a coincidence between said access address and said contents of said at least one of said address system registers .