Patent ID: 8300461

Claim:
An area saving electrically-erasable-programmable read-only memory (EEPROM) array, comprising: a plurality of parallel bit lines, that are classified into a plurality groups of bit lines, containing a first group bit line and a second group bit line; a plurality of parallel word lines, arranged perpendicular to said bit lines, and containing a first word line; a plurality of parallel common source lines, arranged parallel with said word line, containing a first common source line; and a plurality of sub-memory arrays, each is connected to two group of said bit lines, said word lines, and said common source line, each said sub-memory array includes: a first memory cell, connected to said first group bit line, said first common source line, and said first word line; a second memory cell, connected to said second group bit line, said first common source line, and said first word line, said first memory cell and said second memory cell are arranged to be symmetric to each other, and are located on a same side of said first common source line; a third memory cell, connected to said first group bit line, said first common source line, and said first word line, and is arranged to be symmetric to said first memory cell with said first common source line as an axis; and a fourth memory cell, connected to said second group bit line, said first common source line, and said first word line, and is arranged to be symmetric to said second memory cell with said first common source line as said axis, said third memory cell and said fourth memory cell are arranged to be symmetric to each other, and are located on two different sides of said first common source line, just as said first and said second memory cells are located on said two different sides of said first common source line.