Patent ID: 7907374

Claim:
An electrostatic discharge (ESD) prevention circuit for preventing an output circuit from being affected by an electrostatic voltage, and the ESD prevention circuit comprising: an output circuit comprising a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, and an output unit, wherein a drain of the second NMOS transistor is coupled to the output unit and a gate of the second NMOS transistor is coupled to the PMOS transistor; a NOR logic gate coupled to the output circuit; an even-stage circuit coupled to the NOR logic gate and comprising a plurality of inverters, wherein a number of the inverters is even; and a level-rising circuit, coupled to the NOR logic gate for a voltage source, and for blocking a correlation with the even-stage circuits coupled to the output circuit, so that an output of the NOR logic gate is at a low logic level.