Patent ID: 8621411

Claim:
A method of identifying bit stacks in an integrated circuit design comprising: receiving a circuit description for the integrated circuit design which includes a plurality of cells interconnected to form a plurality of nets, the cells having locations from a previous placement, by executing first instructions in a computer system; identifying at least one cluster of the cells from the design, by executing second instructions in the computer system; generating candidate bit stacks from groups of interconnected cells in the cluster, by executing third instructions in the computer system; calculating wirelength costs for the candidate bit stacks based on the cell locations, by executing fourth instructions in the computer system; and selecting a partition from a plurality of different partitions of the candidate bit stacks as final bit stacks wherein said selecting is based on a minimum total wirelength cost for the partition equal to the sum of the wirelength costs of all candidate bit stacks in the partition, by executing fifth instructions in the computer system.