Patent ID: 7855135

Claim:
A method to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor, comprising: forming a MHK gate stack upon a substrate, the MHK gate stack comprising a bottom layer comprised of high dielectric constant material, a middle layer comprised of metal, and a top layer comprised of one of amorphous silicon or polycrystalline silicon; forming a single depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, said single depleted sidewall layer comprised of one of amorphous silicon or polycrystalline silicon; and forming an offset spacer layer over the single depleted sidewall layer and over exposed surfaces of the bottom layer, wherein the offset spacer layer is formed to be physically in contact with the single depleted sidewall layer and with the exposed surfaces of the bottom layer, wherein the offset spacer layer has a thickness in a range of about three to six nanometers.