Patent ID: 7907086

Claim:
An electronic system architecture having a plurality of processing nodes, each processing node providing a function or part of a function implemented by the system, comprising: one single synchronization link which supplies all the processing nodes with one and the same general synchronization message having a simplified header, a base clock, a synchronization signal and a reference date, a plurality of asynchronous data interchange links, each link allowing the interchange of specific data between two specific processing nodes, the interchanged data being accompanied by a generic header including all the information which is used by the various processing nodes and which relates to the system's operating step to which the interchanged data refer, each processing node having means suitable for interfacing with the synchronization link and for implementing its internal sequencing on the basis of the base clock and the synchronization message; and each processing node having means suitable for processing the headers associated with the input data received by a data interchange link and for associating the appropriate header with the output data produced.