Patent ID: 8861513

Claim:
A method for calibrating receivers of a parallel I/O bus receiver interface, said method comprising: receiving N+1 parallel data signals along respective paths, one of said N+1 parallel data signals comprising a spare data signal; coupling received N parallel data signals along respective paths to corresponding N receiver devices of N+1 parallel-configured bit receiver devices, and coupling a remaining one received parallel data signal to two adjacent bit receivers or two adjacent bit receivers of two or three adjacent parallel bit receivers; calibrating, using a calibration logic device, one of said two adjacent bit receiver devices during a calibration cycle; qualifying, using a qualification logic device, data decisions made during calibration processes performed by the calibration logic device, wherein a same data signal being used for calibrating a receiver during said calibration cycle is provided to the adjacent receiver of either said two adjacent or said three adjacent bit receivers; and configuring an output switching network to route an output of the bit receiver being calibrated to said calibration logic block, and simultaneously route outputs of the remaining N bit receivers of the N+1 parallel-configured receivers as N-bit wide parallel data signal outputs, wherein one output of an adjacent receiver receiving said same data signals during said calibration cycle is simultaneously routed to said qualification logic block.