Patent ID: 7398485

Claim:
A method of optimizing router settings to increase integrated circuit yield, comprising: reviewing yield data in an integrated circuit manufacturing line to identify structure-specific mechanisms that impact said integrated circuit yield; establishing one of a plurality of structural identifiers and one of a plurality of weighting factors for each of said structure-specific mechanisms, comprising establishing weighting factors comprising lower values relative to other weighting factors to structure-specific mechanisms comprising single wires spaced a minimum distance from at least one of double wires and triple wires; modifying said router settings based on said structural identifiers and said weighting factors to minimize layout placement of structures that are known to create systematic defects; and tuning said router settings to minimize random defects, comprising: selecting multiple representative chips, performing router test cases by routing each of said chips with a different weighting factor, generating graphical data for each of said router test cases, performing a critical area analysis for each of said router test cases, and selecting a router test case for said tuning of said router settings based on results of said critical area analysis.