Patent ID: 7818642

Claim:
An apparatus comprising: a plurality of first level matrices, each first level matrix including m input terminals and n output terminals, each first level matrix having a row for each of a plurality of circuit elements of a corresponding logic block of the apparatus that provides an input into one of the m input terminals and a column for each of the n output terminals, all of the first level matrix rows being non-zero and each of the rows being different from each other, wherein all of the first level matrix rows have an odd number of one values; a plurality of second level matrices each coupled to the n output terminals of one of the first level matrices, wherein each of the second level matrices has n input terminals and p output terminals, wherein the output terminals correspond to an output from the apparatus and the number of p output terminals is substantially less than the combined number of the n output terminals; and a pipeline stage coupled between each of the plurality of second level matrices to shift inputs to a corresponding second level matrix from one of the corresponding logic blocks.