Patent ID: 8873316

Claim:
An integrated non-volatile memory (NVM) system, comprising: an array of non-volatile memory (NVM) cells; bias voltage generator circuitry configured to generate bias voltages for the NVM cells; and controller circuitry configured to obtain operating temperature measurements relating to the NVM system, to determine performance degradation for the NVM system based upon the temperature measurements, and to adjust voltage levels for the bias voltages generated by the bias voltage generator circuitry based upon the performance degradation determination; wherein the controller circuitry is further configured to conduct program and erase operations for the NVM system using the adjusted voltage levels; wherein for a program operation a voltage level for a gate bias voltage is adjusted higher than a default gate bias voltage level if an operating temperature measurement is higher than a threshold operating temperature; and wherein for an erase operation a voltage level for a body bias voltage that is adjusted higher than a default body bias voltage level if an operating temperature measurement is lower than a threshold operating temperature.