Patent ID: 8724406

Claim:
A bidirectional shift register, comprising: a first register circuit comprising: a first register stage having a first end, a second end and an output end, wherein the first end of the first register stage is electrically coupled to an output end of a second register stage of a previous-stage bidirectional register shift register, the first register stage is configured to receive a first control signal, a second control signal and an end stage clock signal, the first register stage is electrically coupled to a third voltage source; and a first output buffer stage electrically coupled to the first register stage and having a first end, a second end and n numbers of scanning signal output ends, wherein the first end of the first output buffer stage is electrically coupled to the first end of the first register stage, the second end of the first output buffer stage is electrically coupled to the second end of the first register stage, the first output buffer stage is further electrically coupled to a first voltage source and a second voltage source; and a second register circuit comprising: a second register stage having a first end, a second end and an output end, wherein the first end of the second register stage is electrically coupled to the output end of the first register stage, the second end of the second register stage is electrically coupled to an output end of a first register stage of a next-stage bidirectional shift register, the output end of the second register stage is electrically coupled to the second end of the first register stage and a first end of the first register stage of the next-stage bidirectional shift register, the second register stage is configured to receive the first control signal, the second control signal and a complementary end stage clock signal, the second register stage is further electrically coupled to the third voltage source; and a second output buffer stage electrically coupled to the second register stage and having a first end, a second end and n numbers of scanning signal output ends, wherein the first end of the second output buffer stage is electrically coupled to the first end of the second register stage, the second end of the second output buffer stage is electrically coupled to the second end of the second register stage, the second output buffer stage is further electrically coupled to the first voltage source and the second voltage source; wherein the first register circuit and the second register circuit each use n+1 numbers of clock signal lines, and n is a positive integer.