Patent ID: 7916050

Claim:
An apparatus comprising: a first analog-to-digital converter (ADC) that receives a first input signal; a switch that receives the first input signal and that is adapted to receive a second input signal; a second ADC that is coupled to the switch so as to receive at least one of the first and second input signals; clocking circuitry that is coupled to each of the first and second ADCs so as to provide a first clock signal to the first ADC and a second clock signal to the second ADC; and mismatch circuitry that is coupled to the first ADC, the second ADC, and the clocking circuitry so as to operate in at least one of in-phase/quadrature (IQ) mismatch correction mode if the second ADC receives the second input signal and timing skew correction mode if the second ADC receives the first input signal.