Patent ID: 7555668

Claim:
An integrated circuit device, comprising: a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals of equivalent frequency received at an interface of the integrated circuit device; and a data capture circuit configured to capture a plurality of data streams associated with the plurality of data strobe signals, said data capture circuit comprising: a skew control circuit responsive to the skew data, said skew control circuit configured to determine a fast skew limit in response to identifying a second internal clock signal having a relatively slow skew when compared to a first internal clock signal having a relatively fast skew and further configured to reduce a skew difference between a first data stream associated with the first internal clock signal and a second data stream associated with the second internal clock signal by capturing the first data stream in-sync with a phase-delayed version of the first internal clock signal having a skew that lags the fast skew limit.