Patent ID: 7713816

Claim:
A method for fabricating a semiconductor device, comprising: forming an isolation layer on a semiconductor substrate on which a capacitor region and a transistor region are defined; forming a trench in the isolation layer; sequentially forming a first polysilicon layer, a dielectric layer, and a second polysilicon layer on an entire surface of the substrate including the trench; forming a capacitor in the trench by performing a chemical mechanical polishing (CMP) process, the CMP process being performed until an upper surface of the isolation layer is exposed; forming a first photoresist pattern to expose the transistor region; removing the second polysilicon layer and the dielectric layer using the first photoresist pattern as a mask; forming a second photoresist pattern in the transistor region; and forming a gate electrode by selectively removing the first polysilicon layer in the transistor region using the second photoresist pattern as a mask.