Patent ID: 6940781

Claim:
A nonvolatile memory apparatus comprising: a nonvolatile memory array having a plurality of nonvolatile memory cells; control circuitry having a first circuit and a second circuit; an address generation circuit; and a plurality of word lines, each of which is coupled to corresponding ones of said nonvolatile memory cells, wherein said control circuit controls a first operation in response to receiving a command from outside thereof, wherein in said first operation, said control circuit performs control such that: said address generation circuit generates a first address for selecting one word line, said first circuit operates to cause first data to be stored into nonvolatile memory cells coupled to said one word line, and then to cause data to be read from said nonvolatile memory cells coupled to said one word line, said second circuit compares said data read from said nonvolatile memory cells coupled to said one word line and expectancy data in accordance with said first data, and stores said first address when said data and said expectancy data do not match, and said address generation circuit generates a second address, different from said first address, for selecting another one of said word lines after storing said first address.