Patent ID: 8040166

Claim:
A frequency multiplier, comprising: a first transistor (Q 1 ) having a first terminal, a second terminal and a third terminal; a second transistor (Q 2 ) having a first terminal, a second terminal and a third terminal; a voltage controlled oscillator (VCO) and a balun comprising a first balanced terminal, a second balanced terminal and a third terminal, wherein the first terminal of the first transistor is connected to the third terminal of the second transistor through one or more circuit elements, said one or more circuit elements including a first capacitor, the first terminal of the second transistor is connected to the third terminal of the first transistor through one or more circuit elements, said one or more circuit elements including a second capacitor, the third terminal of the first transistor is connected to the first balanced terminal of the balun, the third terminal of the second transistor is connected to the second balanced terminal of the balun, the second terminal of the first transistor is connected to an output node, the second terminal of the second transistor is connected to the same output node, and the vco is connected to the third terminal of the balun.