Patent ID: 8492209

Claim:
A method for forming a transistor, comprising: forming a semiconductor material on an insulator; forming an insulating layer and a gate over a first portion of the semiconductor material; forming spacers over a second portion and a third portion of the semiconductor material, wherein the spacers adjoin the insulating layer, and wherein the first portion, second portion, and third portion form a floating body region; forming a source region by implanting an impurity into a fourth portion of the semiconductor material after forming the spacers, wherein the fourth portion is adjacent the second portion; and forming a drain region by implanting the impurity into a fifth portion of the semiconductor material after forming the spacers, wherein the fifth portion is adjacent the third portion; wherein the electrically floating body region extends outside of at least one lateral boundary of the gate at its closest proximity to the gate such that no portion of at least one of the source region and the drain region is disposed directly under the gate.