Patent ID: 7132363

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a single first dielectric layer overlying a substrate; forming a first barrier layer, comprising a first dielectric barrier material, on the single first dielectric layer with an interface therebetween, etching to form a single opening entirely within and defined by side surfaces of the single first dielectric layer and a bottom over an underlying conductive feature; forming a second barrier layer, comprising a second dielectric barrier material different from the first dielectric barrier material, on and in contact with an entire upper surface of the first barrier layer overlying the single first dielectric layer, on the side surfaces of the single first dielectric layer defining the single opening and on the bottom of the single opening; etching, with selectivity to the first barrier layer, to remove the second barrier layer from, and stopping on, the upper surface of the first barrier layer, and to remove the second barrier layer from the bottom of the single opening exposing the underlying conductive feature, leaving a portion of the second barrier layer as a liner on the side surfaces of the single first dielectric layer defining the single opening; filling the single opening with metal forming an overburden on the first barrier layer; and planarizing to form a lower metal feature.