Patent ID: 6927991

Claim:
A memory device accessible with different communication protocols, the memory device comprising: a plurality of pins being connected to an external bus; a memory having inputs for receiving a chip enable command and a write enable command; an address bus and a data bus coupled to said memory; a multi-protocol interface coupled to said plurality of pins for receiving a timing signal and a start signal of a received communication protocol cycle, and coupled to said address and data busses and generating the chip enable command and the write enable command for said memory, said multi-protocol interface comprising at least two interfaces, each interface for decoding a respective communication protocol when enabled by a respective interface enable signal; and an automatic selection circuit for selecting one of said at least two interfaces to be used and receiving as inputs the timing signal and the start signal of the received communication protocol cycle, said automatic selection circuit comparing bits transmitted during a preamble of the received communication protocol cycle with pre-established bit patterns corresponding to preambles of the communication protocols associated with said at least two interfaces, and generating the respective interface enable signal for one of said at least two interfaces based upon the comparison, the comparison corresponding to an edge of the start signal.