Patent ID: 7769922

Claim:
A processing system for accessing data, the processing system comprising: a processor comprising an execution unit for executing instructions; a stream register unit being part of the processor and configured to supply a first type of data from a peripheral to the execution unit of the processor, the stream register unit including at least one stream register unit FIFO configured to store the first type of data received from the peripheral; a FIFO coupled to the peripheral to receive said first type of data from the peripheral and connected to the stream register unit by a communication path, along which said first type of data can be supplied from the FIFO coupled to the peripheral to the at least one stream register unit FIFO; and a memory bus, separate from the communication path, connected between a data memory and the processor, across which the processor can access a second type of data, the second type of data being randomly accessible data held in the data memory; wherein the first type of data is supplied via the communication path directly from the FIFO coupled to the peripheral to the at least one stream register unit FIFO of the stream register unit of the processor and the second type of data is supplied via the memory bus, separate from the communication path, between the data memory and the processor; and wherein the stream register unit is configured to: in response to a request for a data item from the execution unit, when the data item in located in a next location of the at least one stream register unit FIFO, provide the data item to the execution unit, when the at least one stream register unit FIFO does not contain the data item in the next location, request the data item from the FIFO coupled to the peripheral by setting a “taken” signal across the communication path to a logic high, and when the FIFO coupled to the peripheral indicates that the data item is not available at the FIFO coupled to the peripheral by sending a “valid” signal set to a logic low, send a stall signal to the execution unit causing the execution unit to stop executing instructions.