Patent ID: 7856581

Claim:
A method for testing input output circuits, comprising: initializing Input-Output (I-O) circuits in a plurality of I-O circuits for performing an external test on the I-O circuits, wherein the plurality of I-O circuits are segmented together into at least a first I-O segment of two or more I-O circuits; and providing an on-chip analog bus to provide external access for the external test to two or more input-output pins that provide Parametric Test Measurement (PMU) functionality to the first I-O segment through two or more I-O circuits but less than all of the I-O circuits within the first I-O segment, wherein the on-chip analog bus couples via a switchable device to the two or more input-output pins that an external tester can connect to, and the external tester is configured to provide the PMU functionality to the first I-O segment, wherein the remaining I-O circuits within the first I-O segment couple to the external tester through the two or more I-O circuits.