Patent ID: 7996702

Claim:
A system for testing overclocking capability of a central processing unit (CPU) of a computer, comprising: an frequency generator configured for generating and adjusting a real-time frequency of the CPU; a watchdog timer configured for receiving a counter signal in a preset time interval from the CPU; and a basic input and output system (BIOS) comprising: an input module configured for inputting an initial frequency to the frequency generator; a watchdog control module configured for sending a counter signal to the watchdog timer via the CPU in a preset time interval, wherein upon a condition that the watchdog timer does not receive a next counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer; and a frequency increasing module configured for adding a preset increment to the real-time frequency of the CPU to obtain a newly adjusted frequency, and providing the newly adjusted frequency to the frequency generator to adjust the real-time frequency of the CPU after the watchdog control module sends the next counter signal to the watchdog timer.