Patent ID: 8745604

Claim:
A computer implemented method of compiling a program, for execution on a tiled processor comprising plural tiles each tile comprising a processor, memory, and a switch, the method comprising: partitioning by a compiler on a computer system the program into subprograms, the subprograms for execution on plural ones of the tiles; and subpartitioning by the compiler on by the computer system, the subprograms into separate compute instruction stream partitions and separate switch instruction stream partitions, the compute instruction stream partitions being independent partitions from the switch instruction stream partitions, with switch instructions in the switch instruction stream partitions indicating which input and output ports of switches of the different tiles to connect for corresponding message transfers among switches and switch instruction streams enabling execution of computations and switch data on a tile in the same clock cycle; and determining by the compiler on the computer system dependencies among switch instruction subpartitions for processing of the computer program on the tiled processor.