Patent ID: 7279946

Claim:
A clock controller for use with an off-chip driver, the clock controller comprising: a node receiving a reference clock represented by at least one clock signal; a first delay element configured to delay one of the at least one clock signals by a first delay time to provide a first delayed clock; a second delay element configured to delay one of the at least one clock signals by a second delay time to provide a second delayed clock; a restore circuit configured to provide to the off-chip driver at least a first output clock based on the first and second delayed clock, wherein the off-chip driver provides output data based at least on the first output clock; and an adjustment circuit configured to adjust the first and second delay times so as to adjust edges of the first output clock such that output data from the off-chip driver aligns with edges of the reference clock, and to adjust the second delay time to maintain the first output clock at a desired duty cycle.