Patent ID: 7981731

Claim:
A method of forming an integrated antifuse circuit having one programmable element and one FET semiconductor device, comprising the steps of: forming the programmable element horizontally directed on a substrate having a first electrode and an insulator disposed between the substrate and said first electrode, said insulator having a first value of a given parameter to provide a low breakdown voltage: forming horizontally directed the FET semiconductor device next to the programmable element on the substrate having a second electrode and the insulator disposed between the substrate and said second electrode, said insulator having a second value of said given parameter that is different from said first value to provide a high breakdown voltage; said programmable element and FET device are formed by forming a first dielectric for both the FET device and the programmable element on the substrate; masking areas on the substrate where either programmable element or FET device is to be formed, so as to expose a portion of said insulator where either the selected programmable element or FET device is to be formed such that the both the programmable element and the FET device are self-aligned with the first dielectric and the insulator; coupling said electrodes of said programmable element and FET device to one another; and coupling a source of programming energy to the programmable element.