Patent ID: 8198184

Claim:
A method for fabricating an integrated circuit, comprising the step of: forming a SiON gate dielectric layer having a graded nitrogen concentration over a substrate; and forming a polysilicon gate electrode layer over the SiON gate dielectric layer, wherein the SiON gate dielectric layer has a higher nitrogen concentration adjacent to the polysilicon gate electrode layer than adjacent to the substrate, wherein the step of forming the SiON gate dielectric layer comprises the steps of: forming a base oxide layer over the substrate; performing a nitridation process on said base oxide layer to form a SiON layer; and annealing the SiON layer, wherein said annealing step denudes nitrogen from an upper surface of the SiON layer; and after annealing the SiON layer, depositing a layer of SiN over the SiON layer.