Patent ID: 8533397

Claim:
A method implemented for execution on one or more processors for improving data access performance in a storage system, the method comprising: receiving a request to destage a first partial stride of data from a storage cache to one or more storage devices, wherein data is stored in the one or more storage devices as a full stride with parity data calculated for the full stride; reserving space on said one or more storage devices to store a full stride of data; destaging the first partial stride of data to a first portion of the reserved space on the one or more storage devices by: allocating the reserved space such that (1) the first portion of the reserved space includes data blocks that are allocated to the requested first partial stride of data and (2) a second portion of the reserved space includes data blocks that remain unallocated; and padding the second portion of the reserved space that includes the unallocated data blocks with binary bits, so that the second portion of the reserved space remains available for destaging of one or more additional partial strides of data from the storage cache during a later data destaging from the cache, wherein the first and second portions of the reserved space correspond to a full stride of data with parity data calculated based on value of the first partial stride of data stored in the first portion of the reserved space and value of the binary bits stored in the second portion of the reserved space, such that the binary bits do not affect value of the parity data calculated for the full stride of data; and delaying calculating the priority value for the data stored in the reserved space, unit the second portion of the reserved space is allocated in a thin provisioned address space when additional data is destaged from the cache into the second portion of the reserved space.