Patent ID: 8643187

Claim:
A high speed electronics interconnection system for interconnecting two or more on-chip electronic elements, said interconnection system comprising: at least one electrical signal plane comprising at least one electrical conductor for carrying an electrical signal horizontally along the xy-plane from one electronic element to another; at least one first dielectric system, wherein one side of the at least one electrical signal plane is laid on the at least one dielectric system or embedded in the at least one dielectric system, the at least one first dielectric system comprising: at least one first dielectric layer, and at least one first open trench embedded in the at least one first dielectric layer, wherein each said at least one first open trench is matched with one of said at least one electrical conductor, wherein each said at least one first open trench runs parallel with and directly above and/or below the at least one electrical conductor to which said at least one first open trench is matched, such that the xy-coordinates of said at least one first open trench substantially match or overlap with the xy-coordinates of said at least one electrical conductor, and wherein each said at least one first open trench is located in close proximity to the at least one electrical conductor to which said at least one first open trench is matched, such that dielectric loss across said at least one electrical conductor is reduced; at least one signal via connected to the at least one electrical conductor, and at least two ground vias located in close proximity to said signal via, such that a desired impedance is maintained along the height of said at least one signal via, connected to a ground plane, and oriented to be parallel with the at least one signal via along the entire height of said at least two ground vias.