Patent ID: 8610446

Claim:
A combination comprising: a device to be tested, comprising a semiconductor wafer, a semiconductor chip, a semiconductor package, a semiconductor module or a semi-finished semiconductor module; and a testing device comprising, a pressure vessel including an internal space therein; a mounting stand disposed in the internal space of the pressure vessel, on which the device to be tested is mounted; test electrodes disposed in the internal space of the pressure vessel, and supplying a predetermined test voltage to the device to be tested mounted on the mounting stand; and a pressurization unit that raises a pressure of the internal space of the pressure vessel such that a voltage at a dielectric breakdown of the device to be tested becomes higher than a maximum value of the predetermined test voltage applied to the device to be tested, wherein the predetermined test voltage is supplied from the test electrodes to the device to be tested mounted on the mounting stand, and testing of the device to be tested is carried out in a condition in which the pressure of the internal space of the pressure vessel is raised by the pressurization unit.