Patent ID: 8426273

Claim:
A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of laterally spaced conductively doped source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising: ion implanting conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions, the highest dopant concentration portions comprising 1×10 13 to 1×10 16 ions/cm 3 ; conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions, the semiconductive material having an exposed uppermost surface during the implanting and the anneal; after the dopant activation anneal, etching an opening through the conductivity enhancing dopant into the semiconductive material of the substrate; forming a gate dielectric that lines the entire sidewalls of the opening and directly overlies the uppermost surface of the semiconductive material; and depositing material from which a conductive portion of the transistor gate is made into the opening.