Patent ID: 6965253

Claim:
A reduced-input-capacitance bus switch comprising: a bus-switch transistor, having a gate driven by an enable signal, a drain connected to a first input, and a source connected to a second input; an isolated well under the bus-switch transistor, the isolated well isolated from a supply, the supply being a power source or a ground; a second well of an opposite polarity type as the isolated well, the second well being formed under and surrounding the isolated well; wherein a substrate is a same polarity type as the isolated well; a well tap for electrically connecting to the isolated well; a first well-shorting transistor, having a gate driven by the enable signal, a drain connected to the first input, and a source connected to the well tap; a second well-shorting transistor, having a gate driven by the enable signal, a drain connected to the second input, and a source connected to the well tap; and a biasing transistor, formed outside the isolated well, responsive to the enable signal or to an inverse of the enable signal, having a channel between the well tap and the supply that conducts current when the enable signal turns off the bus-switch transistor, whereby the isolated well is shorted to the first and second input when the bus-switch transistor is turned on.