Patent ID: 6844218

Claim:
A method of forming a plurality of integrated circuit die on a semiconductor wafer, comprising: forming a first integrated circuit die in a first area in a fixed position relative to the semiconductor wafer, comprising the steps of: forming at least two devices in the first area, the at least two devices selected from a group of active and passive devices; forming a first metal layer comprising portions connecting to the at least two devices in the first area; forming a second integrated circuit die in a second area in a fixed position relative to the semiconductor wafer, the second area separated from the first area by a scribe area, comprising the steps of: forming at least two devices in the second area, the at least two devices selected from a group of active and passive devices; forming the first metal layer to further comprise portions connecting to the at least two devices in the second area; forming the first metal layer to further comprise a portion electrically connecting a portion of the first metal layer in the first area to a portion of the first metal layer in the second area and thereby extending in the scribe area, wherein the semiconductor wafer comprises a semiconductor substrate; wherein a distance D max is defined between a plane along the semiconductor substrate and a plane of an intra-die metal connecting layer formed as part of the first integrated circuit die and the second integrated circuit die; and wherein the first metal layer is a distance from the semiconductor substrate equal to or less than D max .