Patent ID: 7243277

Claim:
The method of combining multilevel memory cells for an error correction scheme comprising following steps: providing at least one memory cell, wherein said memory cell has q voltage levels and q is not limited to by value of 2 m , m>0, then the storing bit of said memory cell can be indicated to └log 2 q┘; combining n said memory cells to form a memory, n>1, then the storing bits of said memory can be indicated to └log 2 (q) n ┘, and said memory further comprises residual voltage levels, wherein said residual voltage levels are the voltage levels which can not present any bit and the number of residual values can be indicated to q n −2 └log 2 (q) n ┘ ; storing a data to said storing bits └log 2 (q) n ┘ and treating said residual voltage levels of said memory for marking the error to identify an error location of said data.