Patent ID: 7573098

Claim:
An NMOS transistor comprising: a semiconductor substrate of a P-type conductivity; first and second well regions of an N-type conductivity formed spaced apart in the semiconductor substrate; a conductive gate formed on the semiconductor substrate and electrically isolated from the semiconductor substrate by a dielectric layer, the conductive gate being formed over the region between the spaced apart first and second well regions, the region of the substrate between the spaced apart first and second well regions under the conductive gate forming the channel region of the transistor; first and second dielectric spacers formed on the sidewalls of the conductive gate; first and second heavily doped regions of the N-type conductivity formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers, the first and second heavily doped regions forming source and drain regions, wherein the first well region extends from partway in the first heavily doped region through an area under the first spacer to the channel region, and the second well region extends from partway in the second heavily doped region through an area under the second spacer to the channel region, the first and second well regions bridging the source and drain regions to the channel region of the transistor without any lightly doped regions.