Patent ID: 6998879

Claim:
A level determination circuit determining a logic level of an input signal for each of a plurality of periods, each period defined by a clock signal, comprising: a comparison circuit for comparing a potential of said input signal with a reference potential used for comparison of said input signal to output a signal of a logic level corresponding to a result of the comparison; and a setting circuit operative in response to said input signal of a first potential level being received in an Nth period (N being a natural number) for setting said reference potential's level in an (N+1)th period to a second potential level, operative in response to said input signal of a potential level higher than said first potential level being received in said Nth period for setting said reference potential's level in said (N+1)th period to a potential level equal to or higher than said second potential level, and operative in response to said input signal of a potential level lower than said first potential level being received in said Nth period for setting said reference potential's level in said (N+1)th period to a potential level equal to or lower than said second potential level.