Patent ID: 8865583

Claim:
A method for manufacturing a semiconductor device comprising: forming an insulation layer to be processed over a semiconductor substrate, said semiconductor substrate including a plurality of functioning elements which is to be connected to at least one of a plurality of functioning wirings on said semiconductor substrate; forming a first sacrificial layer in a first area over said insulation layer, said first sacrificial layer being patterned to form in said first area said plurality of functioning wirings connecting said plurality of functioning elements being arranged over said semiconductor substrate; forming a second sacrificial layer in a second area over said insulation layer, said second sacrificial layer being patterned to form in said second area a dummy wiring; forming a third sacrificial layer at a side wall of said first sacrificial layer and forming a fourth sacrificial layer at a side wall of said second sacrificial layer, said third sacrificial layer and said fourth sacrificial layer being separated; forming a concavity by etching said insulation layer to be processed using said third sacrificial layer and said fourth sacrificial layer as a mask; and filling a conductive material in said concavity to form said plurality of functioning wirings and said dummy wiring, each functioning wiring side wall arranged in a longitudinal direction of said plurality of functioning wirings being separated by a substantially equal distance from one of an adjacent dummy wiring side wall arranged in a longitudinal direction of an adjacent said dummy wiring and another adjacent functioning wiring side wall arranged in a longitudinal direction of an adjacent said functioning wiring.