Patent ID: 8407635

Claim:
A method of producing a hierarchical power information structure for a circuit design, the method comprising: using a computing device to traverse a circuit design hierarchy, that includes multiple instances encoded and arranged hierarchically in computer readable storage device, from a top design level to a bottom design level to identify at least one intermediate design level in the circuit design hierarchy; identifying one or more power nets and one or more ground nets in an intermediate design level; associating, by the computing device, identified power nets with ground nets to produce one or more power domains; identifying an instance of one or more special cells in the intermediate design level that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure; generating, by the computing device, power rules for the intermediate level design using the special cell constructs; traversing the circuit design hierarchy from the bottom design level to the top design level to map higher design level power domains to lower design level power domains; and storing the power domains and power rules as power intent as at least a portion of a data structure associated with a schematic for the intermediate level design.