Patent ID: 8296505

Claim:
A system for controlling a flash memory, the system comprising: a descriptor array receipt unit for receiving, from a processor, a descriptor array including at least one descriptor corresponding to at least one operation; and a flash memory control unit for verifying the descriptor included in the descriptor array and executing a flash memory control command included in the verified descriptor, wherein the descriptor is stored in a memory different from the flash memory, in an array fashion, wherein the flash memory control unit returns to be in a ready state by finishing all operation by the descriptor, wherein the flash memory control unit executes the flash memory control command independent from the operation of the processor; wherein the flash memory control command includes a foreground flash memory control command and a background flash memory control command, wherein the flash memory control unit divides the descriptor into a plurality of unit requests with respect to block or page, and inserts a Synchronization (SYNC) packet acting as a marker indicating a boundary between the unit requests, wherein a point of time when the SYNC packet arrives at all interface devices is a scheduling point of time when the requests of the foreground flash memory control command are capable of preempting the requests of the background flash memory control command.