Patent ID: 8099530

Claim:
A data processing apparatus that controls data transfer between a plurality of modules and a memory, comprising: a first interface that controls first data read from the memory; a first buffer that stores the first data read by the first interface; a second interface provided to each of at least two first modules belonging to said plurality of modules and controlling output of the first data to a corresponding one of the at least two first modules; a first register that holds information indicating which region of the memory will be allocated to each of the at least two first modules; and a second register that holds information indicating which region of the first buffer will be allocated to each of the at least two first modules, wherein the first interface determines, with reference to the first register, from which region of the memory the first data will be read, and determines, with reference to the second register, in which region of the first buffer the first data read from the memory is stored, and wherein the second interface determines, with reference to the second register, in which region of the first buffer the first data is stored, reads the first data, and outputs the first data to a corresponding one of the at least two first modules.