Patent ID: 8092961

Claim:
A method of manufacturing a semiconductor device, said method comprising: position aligning a pattern of a semiconductor wafer in a current process of a pattern exposure process using information on a pattern that is formed before the current process; and exposing the semiconductor wafer, wherein said position aligning comprises: calculating a correction value set of a current lot for each of misalignments in a scale and a rotation of the pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets for preceding processes to the current process in the immediately-preceding lot, and a summation of completeness value sets for preceding processes to the current process in the current lot; and controlling a correction of a shift, the scale, and the rotation of the pattern in the chip by using the correction value sets.