Patent ID: 7115500

Claim:
A method for forming a via in a semiconductor device of a type that comprises a silicon substrate with an embedded first metal layer, said silicon substrate and said embedded first metal layer covered with a dielectric layer, and said dielectric layer covered with a resist mask having portions that form an aperture through said resist mask, said method comprising the steps of: applying a first vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer; etching a via cavity through a top portion of said dielectric layer with said first vertical anisotropic dry etch process; applying an isotropic wet etch process through said aperture in said resist mask to sidewalls of said via; and etching a sloping surface in said sidewalls of said cavity with said isotropic wet etch process cavity wherein said isotropic wet etch process is applied to said sidewalls of said via cavity for a period of time selected so that an amount of said dielectric layer that is removed by a lateral portion of said isotropic wet etch process allows an application of a subsequent second vertical anisotropic dry etch process to create smooth sidewalls for said via cavity.