Patent ID: 7257790

Claim:
A layout structure of a semiconductor integrated circuit formed on a semiconductor substrate by a photolithographic process using an exposing light having a wavelength of λ, the layout structure comprising: an internal circuit region including a cell array formed by arranging a plurality of unit cells in rows and columns, an outer perimeter of the internal circuit region having an internal side; a peripheral circuit region formed by arranging a plurality of peripheral circuit cells along the internal side, each of the plurality of peripheral circuit cells being different from any of the plurality of unit cells and including a peripheral circuit pattern in at least one layer, an outer perimeter of the peripheral circuit region having a peripheral side that does not face the internal side; and a proximity dummy region formed by arranging a plurality of proximity dummy cells along the peripheral side, each of the plurality of proximity dummy cells having a proximity dummy pattern, which does not contribute to a logical function of the semiconductor integrated circuit, in the at least one layer, wherein the proximity dummy patterns in the plurality of proximity dummy cells arranged along the peripheral side form, in the at least one layer, a line-and-space repetition structure extending along the peripheral side and including two or more pairs of lines and spaces between the lines in every 8×λ at any position within the proximity dummy region.