Patent ID: 8301932

Claim:
Apparatus for processing data comprising: first circuitry within a first clock domain and operating in synchronism with a first clock signal; second circuitry within a second clock domain and operating in synchronism with a second clock signal, said second clock signal, in at least one mode of operation of said apparatus, being at least one of (1) asynchronous with said first clock signal and (2) having a different frequency from said first clock signal; a first-in-first-out memory circuitry having an input coupled to said first circuitry and an output coupled to said second circuitry and configured to pass a data value from said first circuitry to said second circuitry; wherein said first-in-first-out memory circuitry includes write pointer circuitry within said first clock domain and configured to store a write pointer value indicative of a write position within said first-in-first-out memory circuitry to which a next input data value received from said first circuitry will be written; said first-in-first-out memory circuitry includes read pointer circuitry within said second clock domain and configured to store a read pointer value indicative of a read position within said first-in-first-out memory circuitry from which a next output data value to be output to said second circuitry will be read; said first-in-first-out memory circuitry includes at least one pointer synchronising circuit configured to pass a pointer being one of said write pointer and said read pointer between a portion of said first-in-first-out memory circuitry within said first domain and a portion of said first-in-first-out memory circuitry within said second domain, said at least one pointer synchronising circuit having: (i) a plurality of synchronising paths with respective different synchronising delays, a synchronising path being selected for use from said plurality of synchronising paths in dependence upon a relationship between said first clock signal and said second clock; and (ii) a transition register configured to hold for output, upon at least one change in synchronising path from a first synchronising path to a second synchronising path that increases synchronising delay, a pre-switch value of said pointer output from said first synchronising path until a post-switch value of said pointer synchronized by passage through said second synchronising path is available for output.