Patent ID: 7370260

Claim:
A memory circuit, comprising: a magnetoresistive random access memory (MRAM) core for storing data received by the memory circuit and outputting stored data, the magnetoresistive random access memory (MRAM) core having a reserved portion; an error correction code (ECC) coder for adding a redundancy code to the data for storing in the magnetoresistive random access memory (MRAM) core; an ECC corrector, coupled to the magnetoresistive random access memory (MRAM) core, for performing an analysis of the stored data and the redundancy code to detect and correct errors in the stored data that is output by the magnetoresistive random access memory (MRAM) core and providing an error signal when an error is detected from the analysis; an error counter, coupled to the ECC corrector, the ECC coder and the magnetoresistive random access memory (MRAM) core, for providing a count of occurrences of the error signal for storage in the reserved portion of the magnetoresistive random access memory (MRAM) core by using an unused portion of a write memory cycle during a read operation to implement said storage; a write cycle counter coupled to the ECC corrector, the ECC coder and the magnetoresistive random access memory (MRAM) core for providing a count of write cycles for storage in the reserved portion of the magnetoresistive random access memory (MRAM) core in response to the error; and a read cycle counter coupled to the ECC corrector, the ECC coder and the magnetoresistive random access memory (MRAM) core for providing a count of read cycles for storage in the reserved portion of the magnetoresistive random access memory (MRAM) core in response to the error.