Patent ID: 7260799

Claim:
A verification method suitable for use with an original model of an integrated circuit, the original model being described by a netlist including a set of gates and a set of edges representing interconnections between the gates, comprising: proposing, as an equivalence class, a set of candidate gates suspected of exhibiting equivalent behavior; selecting one of the candidate gates as a representative gate; creating a set of equivalence gates, wherein such an equivalence gate comprises an XOR or XNOR sourced by the representative gate and a respective one of the candidate gates; substituting the output of the representative gate for the outputs of the candidate gates; applying a plurality of transformation engines to the netlist having the substituted representative gate output, in order to eliminate gates and, thereby, create a speculatively reduced netlist; and producing predetemined logic states of gates in the speculatively reduced netlist other than the equivalence gates responsive to applying a selected series of logic signals to the speculatively reduced netlist, wherein the produced logic states indicate verification coverage and the verification coverage is deemed valid if none of the equivalence gates change logic state responsive to the application of the selected series of logic signals.