Patent ID: 6937514

Claim:
A semiconductor memory device comprising: a plurality of memory cells each of which includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor having one end of its current path connected to one end of a current path of the first MOS transistor; a memory cell array which has the memory cells arranged in a matrix in such a manner that the memory cells adjoining in the column direction share the other ends of the current paths of the first MOS transistors or the other ends of the current paths of the second MOS transistors; bit lines each of which connects commonly the other ends of the current paths of the first MOS transistors of the memory cells in the same column; word lines each of which is formed by connecting commonly the control gates of the first MOS transistors of the memory cells in the same row; select gate lines each of which is formed by connecting commonly the gates of the second MOS transistors of the memory cells in the same row; a column decoder which selects any one of the bit lines; a first row decoder which selects any one of the word lines; a second row decoder which selects any one of the select gate lines; and first metal wiring layers which are provided for every select gate lines, each of which is formed in the row direction so as to pass through almost the central part of the memory cells, is connected electrically to the corresponding one of the select gate lines, and transmits a row select signal for the second row decoder to select the select gate line.