Patent ID: 7355881

Claim:
A memory circuit comprising: a plurality of cells, wherein each of the cells is configured to store a bit of data; a plurality of local bitlines, wherein each of the plurality of cells is coupled to one of the plurality of local bitlines, wherein each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path, wherein the signal path and the complementary signal path of each of the plurality of local bitlines are cross-coupled by a pair of transistors, and wherein each of the plurality of cells is coupled to one of the plurality of local bitlines; and a pull circuit, wherein the pull circuit is configured to, in a first state, pull up the signal path and pull down the complementary signal path, and wherein in a second state, the pull circuit is configured to pull down the signal path and pull up the complementary signal path, wherein the pull circuit includes: a first pulldown line operatively coupled to the signal path and the complementary signal path, wherein the first pulldown line, when activated, is configured to cause the complementary signal path to be pulled down to a reference voltage and the signal path to be pulled up to a logic voltage; and a second pulldown line operatively coupled signal path an the complementary signal path, wherein the second pulldown line, when activated, is configured to cause the signal path to be pulled down to a reference voltage and the complementary signal path to be pulled up to a logic voltage.