Patent ID: 8898368

Claim:
A memory module, comprising: a plurality of dynamic random access memory (DRAM) chips, each DRAM chip having one or more data input/output (D/Q) terminals, each of said D/Q terminals having an associated load such that said DRAM chips present a plurality of loads, each of said D/Q terminals conveying data; and data redriving/retiming circuits connected between a system memory bus and the D/Q terminals of the plurality of DRAM chips such that data is written from said system memory bus to said DRAM chips in parallel and is read from said DRAM chips and conveyed to said system memory bus in parallel via said data redriving/retiming circuits; wherein the data redriving/retiming circuits provide isolation between said system memory bus and the D/Q terminals of the DRAM chips, thereby isolating said system memory bus from said plurality of loads associated with said plurality of DRAM chips; and wherein the data redriving/retiming circuits comprise: a first register to store data received via the system memory bus for writing into the plurality of DRAM chips; a second register to store data read from the plurality of DRAM chips for output to the system memory bus, wherein each of said first and second registers has an input and an output; a first buffer arranged to receive and buffer said data stored in said first register; and a second buffer arranged to receive and buffer said data stored in said second register, wherein each of said first and second buffers has an input and an output, the output of said first register connected to the input of said first buffer, the output of said first buffer connected to the input of said second register, the output of said second register connected to the input of said second buffer, and the output of said second buffer connected to the input of said first register.