Patent ID: 7773713

Claim:
A method for clock data recovery for a direct digital synthesizer, the method comprising: receiving a digital signal having a clock frequency; calculating a coarse measurement value of the clock frequency using a counter, wherein calculating the coarse measurement value comprises: obtaining a counter value from the counter upon receiving a first signal edge of the digital signal; incrementing the counter value upon receiving each signal edge of a reference clock signal; stopping the counter upon receiving a second signal edge of the digital signal; placing the counter value into a count memory, if the counter value is less than a stored counter value currently in the count memory; and indicating the coarse measurement value, wherein the coarse measurement value corresponds to the counter value; calculating a fine measurement value of the clock frequency using a tap delay line; calculating a data set for the direct digital synthesizer from the coarse measurement value and the fine measurement value; and programming the direct digital synthesizer using the data set to produce an output clock signal with a frequency that is an approximate replica of the clock frequency.