Patent ID: 7681170

Claim:
A method performed in a computer system to output a circuit design layout, comprising: automatically inserting a plurality of predetermined filling forms within a circuit design layout stored in memory of the computer system, each filling form of said plurality of predetermined filling forms being configured to eliminate a corresponding jog area of a plurality of jog areas within said circuit design layout; automatically identifying a filling form of said plurality of predetermined filling forms that violates at least one predetermined design rule applicable to said circuit design layout; automatically determining whether the identified filling form that violates at least one predetermined design rule can be customized; automatically adapting said filling form that violates at least one predetermined design rule to comply with said at least one predetermined design rule if it is determined that the filling form can be customized; and automatically combining remaining predetermined filling forms in compliance with said at least one predetermined design rule within said circuit design layout to form a circuit design output layout that is output by the computer system.