Patent ID: 7032105

Claim:
A computer system comprising: a processor for controlling operations of the computer system; a dynamic random access memory (DRAM) for storing programs and data; a basic input/output system for dividing the dynamic random access memory (DRAM) into a first memory block and a second memory block during a power on self test (POST) process, wherein the first memory block is used for storing an operating system (OS), and the second memory block is used for storing user data; and a bridge circuit electrically connected to the processor and the dynamic random access memory (DRAM) for controlling data transmissions between the processor and the dynamic random access memory (DRAM), the bridge circuit comprising: a conversion circuit for changing formats of instructions and data, the conversion circuit comprising: an instruction format conversion module for converting a hard disk access instruction into a memory access instruction; a data format conversion module for converting data complying with a hard disk storage format into data complying with a memory storage format so that the data complying with the hard disk storage format are stored in the second memory block; and a control port for receiving an input signal to determine whether the conversion circuit is activated; a memory control circuit for accessing data stored in the dynamic random access memory (DRAM) according to the memory access instruction; and a data self-refresh circuit for constantly refreshing the dynamic random access memory (DRAM) to maintain data stored in the dynamic random access memory (DRAM); wherein when the processor issues a hard disk access instruction, the bridge circuit will access data stored in the dynamic random access memory (DRAM) according to the hard disk access instruction, and when the computer system is in a sleeping state or a power-off state, the data self-refresh circuit will constantly refresh the dynamic random access memory (DRAM) to maintain the data stored in the dynamic random access memory (DRAM), wherein the basic input/output system will read the input signal during the power on self test (POST) process, and will determine whether the first and second memory blocks are generated.