Patent ID: 7606061

Claim:
A static random access memory (SRAM) device comprising: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line, wherein the latch unit further comprises: a first PMOS transistor having a source coupled to a supply voltage; a first NMOS transistor having a drain and a gate coupled to a drain and a gate of the first PMOS transistor, respectively; a second PMOS transistor having a source coupled to the supply voltage; and a second NMOS transistor having a drain and a gate coupled to a drain and a gate of the second PMOS transistor, respectively; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit, wherein the power saving module comprises a first source line coupled to a source of the first NMOS transistor, and a second source line coupled to a source of the second NMOS transistor.