Patent ID: 8250286

Claim:
A block management method, for managing a multi level cell (MLC) NAND flash memory, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages, the block management method comprising: configuring a plurality of logical blocks for being accessed by a host; recording a logical block belonging to a frequently accessed block; and performing a special mode to respectively use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of the logical block belonging to the frequently accessed block, wherein when a mother-child block transient relation corresponding to the logical block is closed, the logical block maps to the lower pages of the at least two physical blocks of the MLC NAND flash memory.