Patent ID: 7820502

Claim:
A method for fabricating a circuit on a substrate, the method comprising: forming a plurality of first catalyst pads in an array on a plurality of rows of a conducting material; forming a first insulating layer on the first catalyst pads and the plurality of rows of the conducting material; forming a gate electrode layer on the first insulating layer that is separated from the first catalyst pads and the plurality of rows of the conducting material by the first insulating layer; patterning the gate electrode layer and the first insulating layer to define a plurality of gate electrodes arranged in a plurality of parallel columns to define an array with the parallel rows of the conducting layer and to at least partially expose each of the first catalyst pads at a location proximate to a vertical sidewall of a respective one of the gate electrodes; directing a reactant to the plurality of first catalyst pads; synthesizing at least one semiconducting carbon nanotube on each of the plurality of first catalyst pads from the reactant by a chemical vapor deposition process; depositing a second insulating layer on the gate electrodes and the at least one semiconducting carbon nanotube on each of the plurality of first catalyst pads; planarizing the second insulating layer; and after the second insulating layer is planarized, forming a plurality of contacts each extending through the second insulating layer to be electrically coupled with a leading tip of the at least one semiconducting carbon nanotube on one of the first catalyst pads.