Patent ID: 7787285

Claim:
A computer-readable medium encoding an apparatus, the encoded apparatus being a memory circuit, the encoded apparatus comprising: a plurality of bit line structures; a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, said plurality of word line structures comprising paired read and write word lines; a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding one of said bit line structures under control of a corresponding one of said word line structures, each of said cells in turn comprising: a first inverter having first and second field effect transistors (FETS); and a second inverter having third and fourth FETS, said second inverter being cross-coupled to said first inverter to form a storage flip-flop; wherein said second FET is a metal oxide semiconductor FET (MOSFET) configured with separately biased front and back gates, said front gate of said second FET being ground-biased, and wherein at least some of said cells are asymmetrically controlled by said paired read and write word lines.