Patent ID: 8609499

Claim:
A method comprising: forming a gate dielectric on sidewalls of a middle portion of a first semiconductor fin; forming a gate electrode over the gate dielectric, wherein the gate electrode comprises a portion over and aligned to the middle portion of the first semiconductor fin, wherein a second semiconductor fin is on a first side of the gate electrode, and does not extend to under the gate electrode, and wherein the first and the second semiconductor fins are spaced apart from each other and parallel to each other; etching a first end portion of the first semiconductor fin and the second semiconductor fin; performing an epitaxy to form a first epitaxy region, wherein the epitaxy region comprises: a first portion extending into a first space left by the etched first end portion of the first semiconductor fin; and a second portion extending into a second space left by the etched second semiconductor fin, wherein the first and the second portions merge with each other to form the first epitaxy region; and forming a first source/drain region in the first epitaxy region.