Patent ID: 7301381

Claim:
A high-speed flip-flop comprising: a master terminal receiving input data in response to an inverted clock signal and an internal clock signal, the inverted clock signal being generated by inverting a clock signal; a slave terminal receiving an output of the master terminal and outputting the received output as an output signal in response to the inverted clock signal and the internal clock signal; and an output pre-driving unit driving the output signal in response to the inverted clock signal and an output of the master terminal, wherein the master terminal comprises: a first inverter receiving a clock signal and outputting the inverted clock signal; a second inverter receiving the inverted clock signal and outputting the internal clock signal; a first tri-state buffer receiving the input data in response to the internal clock signal and the inverted clock signal; and a first latch latching an output of the first tri-state buffer wherein the output pre-driving unit comprises: a first PMOS transistor having a source to which a supply voltage is applied, and a gate to which the inverted clock signal is input; and a second PMOS transistor having a source connected to a drain of the first PMOS transistor, a drain to which the output signal is input, and a gate to which the output of the master terminal is input.