Patent ID: 7518395

Claim:
A circuit arrangement, comprising: a driver circuit comprising an input and an output and configured to output an output signal on the output responsive to an input signal received at the input, the driver circuit comprising an output stage coupled between the input and the output of the driver circuit, the output stage including a first pull-up device and a first pull-down device coupled to the output; and a slew rate boost circuit coupled to the output of the driver circuit and configured to increase a slew rate of the driver circuit by reducing an output impedance of the driver circuit during transitions in the output signal, the slew rate boost circuit comprising: a first pulse generator configured to generate a first pulse responsive to a transition in the input signal from a first logic state to a second logic state; a second pulse generator configured to generate a second pulse responsive to a transition in the input signal from the second logic state to the first logic state; a second pull-up device coupled to the output of the driver circuit in parallel with the first pull-up device and configured to activate and reduce the output impedance of the driver circuit responsive to the first pulse from the first pulse generator; and a second pull-down device coupled to the output of the driver circuit in parallel with the first pull-down device and configured to activate and reduce the output impedance of the driver circuit responsive to the second pulse from the second pulse generator; wherein the first pulse generator is an up pulse generator and the second pulse generator is a down pulse generator, wherein the first and second pull-up devices are PFET devices coupled between the output of the driver circuit and VDD, wherein the first and second pull-down devices are NFET devices coupled between the output of the driver circuit and ground, and wherein the circuit arrangement further comprises first and second NAND gates, the first NAND gate having a first input coupled to receive a driver enable signal, a second input coupled to receive the input signal, and an output coupled to a gate input of the first pull-up device, and the second NAND gate having a first input coupled to receive the driver enable signal, a second input coupled to receive the first pulse, and an output coupled to a gate input of the second pull-up device.