Patent ID: 7915656

Claim:
A nonvolatile semiconductor memory apparatus comprising: a semiconductor substrate; an active element forming region provided on said semiconductor substrate and including a plurality of active elements; a wire forming region which is provided on said active element forming region to electrically connect the active elements and includes two or more semiconductor electrode wires and a wire region insulating layer covering the semiconductor electrode wires; a memory portion forming region which is provided above said wire forming region and provided with memory portions arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, said memory portion forming region including an upper electrode wire, a resistance variable layer, a lower electrode wire, and a memory region insulating layer covering the upper electrode wire, the resistance variable layer, and the lower electrode wire; wherein the lower electrode wires are formed in a stripe shape above said wire forming region via a first insulating layer serving as the memory region insulating layer; the resistance variable layers are embedded to fill contact holes formed in an interlayer insulating layer serving as the memory region insulating layer such that the resistance variable layers are respectively connected to the lower electrode wires; the upper electrode wires are formed in a stripe shape on the interlayer insulating layer such that the upper electrode wires are respectively connected to the resistance variable layers and respectively cross the lower electrode wires; the memory portions are each constituted by the lower electrode wire, the resistance variable layer, and the upper electrode wire corresponding to a region where the lower electrode wire and the upper electrode wire cross each other; a first oxygen barrier layer which is interposed between said memory portion forming region and said wire forming region and extends continuously over an entire of said memory portion forming region to block oxygen for at least the entire of said memory portion forming region; and a second oxygen barrier layer provided between the interlayer insulating layer and the upper electrode wires wherein an insulating material used for the wire region insulating layer has a dielectric constant smaller than a dielectric constant of an insulating material used for the memory region insulating layer; when the resistance variable layers are arranged like islands to respectively correspond to the memory portions in a planar view, a region surrounding by a shortest line and in an annular form an outer periphery of the resistance variable layers arranged at an outermost side corresponds to said memory portion forming region.