Patent ID: 7443730

Claim:
A flash memory device comprising: a memory cell array including pluralities of bitlines and wordlines, and pluralities of memory cells arranged at regions intersecting the wordline and bitlines; a control circuit generating pluralities of control signals to regulate a programming operation; a voltage generator providing a program voltage, a pass voltage lower than the program voltage, a decoupling voltage lower than the minimum threshold voltage of a programmed memory cell but higher than the maximum threshold voltage of an erased memory cell, and a blocking voltage higher than the decoupling voltage but equal to or less than the pass voltage, in response to the control signals; and a row selection circuit decoding a row address of a memory cell to be programmed, applying the blocking voltage to at least one more wordlines adjacent to a selected wordline, applying the decoupling voltage to at least one more wordlines adjacent to the wordline supplied with the blocking voltage, applying the pass voltage to the rest of the wordlines, and applying the program voltage to the selected wordline, in response to the decoding result and the control signals.