Patent ID: 8654568

Claim:
A process of performing a write operation, comprising: biasing a source node of a first read buffer driver transistor of a first read buffer in a half-addressed SRAM cell to Vss; biasing a source node of a second read buffer driver transistor of a second read buffer in said half-addressed SRAM cell to Vss; turning on a first access transistor in said first read buffer in said half-addressed SRAM cell, wherein said first access transistor is coupled to a bit-side data line; turning on a second access transistor in said second read buffer in said half-addressed SRAM cell, wherein said second access transistor is coupled to a bit-bar-side data line; floating a source node of said first read buffer driver transistor in an addressed SRAM cell; floating a source node of said second read buffer driver transistor in said addressed SRAM cell; turning on a bit-side passgate transistor and a bit-bar-side passgate transistor in said addressed SRAM cell; and turning on a bit-side passgate transistor and a bit-bar-side passgate transistor in said half-addressed SRAM cell, wherein said bit-side passgate transistor is directly connected to said bit-side data line and a bit-side data node, and further wherein said bit-bar-side passgate transistor is directly connected to said bit-bar-side data line and a bit-bar-side data node.