Patent ID: 8860650

Claim:
A display device including a plurality of gate lines crossing a plurality of data lines, comprising: a first shift register and a second shift register, each of the first and second shift registers including a plurality of first to m-th stages for supplying gate pulses to the gate lines, m being a positive integer, each stage comprising: a node controller configured to: drive a first node to a high level using a high level output signal from the (k−2)-numbered stage, and concurrently discharge a voltage of a second node to a low level using a low level output signal from the (k+2)-numbered stage; and charge the second node at a high level using a high level output signal from the (k+2)-numbered stage, and concurrently discharge the voltage on the first node to a low level using a low level output signal from the (k−2)-numbered stage, wherein k is a positive integer from 1 to m; and an output unit configured to output one of a plurality of clock signals in accordance with the respective voltages of the first and second nodes, wherein the first shift register is formed at a first side of the display panel and electrically connected to odd numbered gate lines, wherein the second shift register is directly formed at the other side of the display panel and electrically connected to even numbered gate lines, and wherein the plurality of clock signals include eight sequentially phase-delayed clock signals, four of the sequentially phase-delayed clock signals being electrically connected to sequential stages of the first shift register, and the other four of the sequentially phase-delayed clock signals being electrically connected to sequential stages of the second shift register.