Patent ID: 7394287

Claim:
An apparatus, comprising: a programmable logic device, the programmable logic device including: a plurality of CLBs arranged in rows and columns of an array; a plurality of inter-CLB lines interconnecting the CLBs of the array; each of the plurality of CLBs having a first slice of logic cells and a second slice of logic cells, wherein the first slice of logic cells and the second slice of logic cells of the CLBs in a given column of the array are interconnected by a first carry chain and a second carry chain respectively; and one of the logic cells including: one or more Look Up Tables for implanting logic functions on a set of inputs provided to the one logic cell; an arithmetic logic circuit configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain; a first output register; and a second output register, wherein the set of outputs generated by the logic cell are partitioned among the first output register and the second output register.