Patent ID: 8223042

Claim:
A circuit, comprising: encoder logic configured to receive 2 m m-bit data patterns and encode the 2 m m-bit data patterns to n-bit encoded data patterns, n being greater than m and m being a positive integer greater than one, wherein: the encoder logic is configured to map the 2 m m-bit data patterns to a subset of less than 2 n of the n-bit encoded data patterns; and the n-bit data patterns in said subset having a smallest possible range of Hamming Weight variation while a number of the n-bit data patterns in said subset being not less than 2 m ; and a driver configured to transmit the n-bit encoded data patterns via a single-ended parallel communication link, wherein the n-bit encoded data patterns transmitted by the driver via the single-ended parallel communication link have the smallest possible range of Hamming Weight variation.