Patent ID: 6842180

Claim:
An apparatus comprising: an integrated central processing unit (CPU) having a pre-fetch stride analyzer and an out-of-order engine, a victim cache memory coupled to said CPU, a pre-fetch buffer coupled to said CPU, a graphics engine having a first graphics memory and a second graphics memory coupled to the integrated CPU, a main memory coupled to a memory controller, wherein the memory controller is coupled to the CPU and the graphics engine, a host address decoder coupled to the integrated CPU, a front side bus (FSB) coupled to the integrated CPU and the host address decoder, and a plurality of memory components, wherein one of the first graphics memory, the second graphics memory, and both the first graphics memory and the second graphics memory can be used by said CPU to perform as said victim cache memory and said pre-fetch buffer in addition to said victim cache memory and said pre-fetch buffer, where said first graphics memory and said second graphics memory increase memory size available for said victim cache and said pre-fetch buffer.