Patent ID: 6946746

Claim:
A wire-bond package comprising: a substrate having a surface with a first portion and a second portion positioned relative to said first portion; a semi-conductor chip positioned on said first portion of said surface of said substrate, said semi-conductor chip having a layer of circuitry thereon; a first power layer and ground layer arranged in an interstitial pattem positioned on said second portion of said surface of said substrate; said interstitial pattem on said second portion of said substrate surface comprising a simulated single ring configuration: a first signal ring adjacent said first power layer or said ground layer positioned on said second portion of said surface of said substrate; an electrical interconnection between said interstitial pattern on said second portion of said surface of said substrate and said circuitry on said semi-conductor chip with two first wires each having a substantially similar first vertical height; and an electrical interconnection between said first signal ring and said circuitry on said semi-conductor chip with a second wire having a second vertical height greater than said substantially similar first vertical height of said two first wires.