Patent ID: 7932765

Claim:
A delay line comprising: a plurality of delay cells interconnected in a lattice configuration, the delay cells each supporting at least three propagation paths each of which traverse at least one delay element, wherein a first path propagates an input signal from a prior cell stage back to the prior cell stage, a second path propagates the input signal from the prior cell stage to a next cell stage, and a third path propagates a returned signal from the next cell stage to the prior cell stage, and a switch control to select a number of delay cells for inclusion in a configurable signal path extending from an input of the delay line to an output of the delay line, the configurable signal path including a signal path having a plurality of delay elements coupled in parallel to interpolate a delay, wherein at least one delay cell located outside but adjacent to the configurable signal path receives an active data signal based on an input signal to the delay line.