Patent ID: 8489843

Claim:
A configurable memory device comprising: a substrate; an array of non-volatile memory cells including at least one non-volatile memory cell on the substrate; an array of volatile memory cells including at least one volatile memory cell on the substrate; an interface configured to enable coupling of the memory device to a memory controller associated therewith, the interface comprising an address translation logic configured to be programmed through a set of registers associated therewith to enable configurable mapping of different sectors of the memory device to different memory address space locations in a computing system associated with the memory device; a tag register associated with the array of volatile memory cells to track a data update associated therewith; and a hybrid memory on the substrate formed through programming a portion of the array of non-volatile memory cells to have a same address as a portion of the array of volatile memory cells, wherein the hybrid memory is configured to be non-volatile and to enable random access of data therein.