Patent ID: 8878304

Claim:
A fuse circuit for final test trimming of an integrated circuit (IC) chip, comprising: (1) at least one electrical fuse; (2) at least one control switch each connected in series with a corresponding one of the at least one electrical fuse between a grounding pin and a predetermined pin, wherein each control switch includes: (2a) a control terminal for receiving a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse such that the fuse circuit is open, wherein the predetermined current flows from the predetermined pin to the grounding pin; (2b) a source terminal and a drain terminal, defining a channel controlled by the control signal between the source terminal and a drain terminal as a channel for the predetermined current to flow through, the controlled channel and the corresponding electrical fuse being coupled in series; and (2c) a bulk terminal, wherein the bulk terminal and the drain terminal inherently form a parasitic diode to block the predetermined current from flowing through the bulk terminal; and (3) a resistant device, coupled between the bulk terminal and the source terminal, wherein the bulk terminal is between the parasitic diode and the resistant device.