Patent ID: 7017069

Claim:
A PWM (pulse width modulation) control circuit for generating a PWM signal, comprising: a counter for incrementing or decrementing a count value in accordance with a given operation clock; an edge-point value setting register for storing an edge-point value which specifies a first edge-point at which the level of the PWM signal varies; a PWM output circuit for varying the level of the PWM signal at said first edge-point specified by said edge-point value, based on said count value from said counter and said edge-point value from said edge-point value setting register; a delay value setting register provided on low order side of said edge-point value setting register, for storing a delay value of at least one bit which specifies a delay time of said first edge-point; and a period value setting register for storing a period value which specifies a period of the PWM signal, wherein said PWM output circuit delays said first edge-point by a period which is smaller than one-clock period of said operation clock, in accordance with said delay value stored in said delay value setting register; and wherein said delay value setting register stores an M-bit delay value; and wherein said PWM output circuit delays said first edge-point by any one of substantially ½ M clock period, substantially 2/2 M clock period, and substantially (2 M −1)/2 M clock period of said operation clock, in accordance with said M-bit delay value stored in said delay value setting register.