Patent ID: 8030705

Claim:
A semiconductor device comprising: a first conductive type well in a semiconductor substrate; a second conductive type well on the first conductive type well; a first trench passing through the second conductive type well and a portion of the first conductive type well; a gate in the first trench with a gate dielectric between the gate and the walls of the trench; a first conductive type source region on the second conductive type well and surrounding a lateral surface of the gate; a second conductive type body region on the second conductive type well and surrounding a lateral surface of the first conductive type source region; a common drain provided between the gate and an at least one adjacent gate, wherein the common drain is connected to the first conductive type well and the common drain surrounds a lateral surface of the second conductive type body region; a high-concentration first conductive type buried layer below the first conductive type well; and a high-concentration first conductive type plug between the common drain and the first conductive type buried layer.