Patent ID: 8045401

Claim:
A memory comprising: a storage array for storing data; and access circuitry for transmitting said data to and from said storage array, said access circuitry forming a data path for inputting and outputting data to said storage array, said access circuitry comprising a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, said further latch comprising an output latch for outputting said data from said storage array, and said first and second clock signals are synchronised with each other; said memory further comprising: a multiplexer, a scan input and a scan enable input, said multiplexer being responsive to an asserted scan enable signal at said scan enable input to form a scan path comprising said latch and said further latch connected together to form a master slave flip flop, such that scan data input at said scan input passes through said master slave flip flop and not through said storage array while said scan enable signal is asserted and is output by said output latch.