Patent ID: 8089310

Claim:
A charge domain circuit, comprising: an input; a first signal output portion coupled to the input, the first signal output portion comprising: a first plurality of delay registers for sampling an input signal from the input at a specified time interval, the first plurality of delay registers performing no multiplication of the input signal; a first adder coupled after the first plurality of delay registers; a first multiplier coupled after the first adder; and a first switch coupled after the first multiplier for outputting a first signal; a second signal output portion coupled to the input, the second signal output portion comprising: a second plurality of delay registers for sampling the input signal, the second plurality of delay registers performing no multiplication of the input signal; a second adder coupled after the second plurality of delay registers; a second multiplier coupled after the second adder; and a second switch coupled after the second multiplier for outputting a second signal; and an output coupled to the first switch and the second switch.