Patent ID: 7461310

Claim:
A method for performing a test on at least one integrated circuit (IC), wherein each IC produces output signals in response to input signals and comprises a plurality of logic blocks and a plurality of clocked devices, wherein the clocked devices of each IC are interconnected to form at least one scan chain, wherein during a normal mode of scan chain operation, the clocked devices forming each scan chain convey data signals between logic blocks of the IC, wherein during a scan mode of scan chain operation, each scan chain provides output state data representing states of the data signals conveyed by the clocked devices forming the scan chain and then sets the data signals to states indicated by input state data, and wherein the test spans a plurality of test cycles of a uniform test cycle period, the method comprising the steps of: a. selecting at least one of the logic blocks as a delay test block, b. performing a functional test spanning a plurality of test cycles on each IC by placing each scan chain in its normal mode of operation, by providing the input signals to the IC, by clocking each clocked device of the IC, and by monitoring the IC's output signals to determine whether they are of expected states, wherein, the functional test includes at least one capture procedure wherein clocking of each clocked device receiving an output data signal of at least one of the delay test blocks follows clocking of each clocked device providing an input data signal to that delay test block with a target delay that is shorter than the test cycle period, and wherein during other portions of the functional test, clocking of each clocked device receiving an output data signal of any one of the delay test blocks follows clocking of each clocked device providing an input data signal to that delay test block with a target delay that is longer than the target period, and c. temporarily interrupting the functional test following each capture procedure to carry out a scan procedure by placing each scan chain in the scan mode of operation and acquiring the output state data from the scan chain representing states of the data signals conveyed by the clocked devices at a point when the functional test was interrupted.