Patent ID: 8401512

Claim:
A semiconductor device comprising; a plurality of three terminal semiconductor portions housed on a single substrate, wherein each three terminal semiconductor portions further comprises a source terminal, a drain terminal, and a gate terminal; a LO+ signal is coupled to a first subset of the plurality of gate terminals; a LO− signal is coupled to a second subset of the plurality of gate terminals; a RF+ signal is coupled to a first subset of the plurality of drain terminals; a RF− signal is coupled to a second subset of the plurality of drain terminals; an IF+ signal is coupled to a first subset of the plurality of source terminals; and an IF− signal is coupled to a second subset of the plurality of source terminals; wherein the first subset of the plurality of source terminals are coupled together; wherein the first subset of the plurality of gate terminals are coupled together; wherein the second subset of the plurality of gate terminals are coupled together; and wherein at least one of the source terminal, drain terminal and gate terminal are shared among a plurality of adjacent three terminal semiconductor portions.