Patent ID: 8842029

Claim:
A delta modulator for receiving an analog signal, comprising: a delta operator means for producing a differential signal; a course analog-to-digital converter means for finding a range of said differential signal, said course analog-to-digital converter being used to estimate said range of said differential signal and set several ranges, under fixed or non-fixed quantization step size, a range of a sampling signal difference being estimated in order to prevent an overload of said differential signal; a fine analog-to-digital converter means for dynamically adjusting a size of quantized step, said fine analog-to-digital converter using a binary search method to solve a differential voltage until a minimum bit or a minimum unit defined by a user; a time-shared comparator; a memory unit; a timing controller, comprising a successive approximation register, an asynchronous clock generator means for detecting a comparator output to generate a half-stable duration wherein said asynchronous clock generator generates several sets of phase clock to control said successive approximate register, and a flip-flop; a channel register; a channel signal; an overflow and underflow detection circuit; and a digital adder means for adding an output binary code of the memory unit and a digital output code; wherein, an output addition result of said digital adder is stored into said memory unit, and said second analog-to-digital converter being used to dynamically adjust said quantization step size for quantizing said differential signal based on a result of said first analog-to-digital converter.