Patent ID: 8495539

Claim:
A method for compiling a hardware description language (HDL) specification for simulation of a circuit design, the method comprising using one or more processors to perform operations including: elaborating the circuit design from the HDL specification; determining singly-driven and multiply-driven nets of the elaborated circuit design; for each singly-driven net, assigning a respective memory location to store a value of a corresponding driver of the net at runtime; for each multiply-driven net, assigning a contiguous block of memory to store values of corresponding drivers of the net at runtime; generating simulation code that models the circuit design, the simulation code configured and arranged to, during runtime, for each singly-driven net, store a value of the corresponding driver of the singly-driven net in the respective memory location, and for each multiply-driven net, store the values of the corresponding drivers in the assigned block of memory; and storing the generated simulation code.