Patent ID: 7715241

Claim:
A method of erasing a P-channel non-volatile memory, the P-channel non-volatile memory comprising: a select transistor and a memory cell connected in series and disposed on a substrate, wherein the select transistor comprises a select gate disposed on the substrate and a first source/drain region and a second source/drain region disposed in the substrate at both sides of the select gate; and the memory cell comprises a control gate disposed on the substrate, a charge storage structure disposed between the substrate and the control gate, and the second source/drain region and a third source/drain region disposed in the substrate at both sides of the control gate, the erasing method comprising: applying a first voltage to the substrate, applying a second voltage to the third source/drain region, and applying a third voltage to the control gate to inject holes into the charge storage structure by substrate hole injection effect, wherein a voltage difference between the first voltage and the second voltage is sufficient to form a depletion region under the third source/drain region and the control gate, and the third voltage is sufficient to pull holes in the depletion region into the charge storage structure; and applying a fourth voltage to the first source/drain region, and applying a fifth voltage to the select gate, wherein a voltage difference between the first voltage and the fifth voltage is sufficient to turn on a channel region under the select gate, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage, the fourth voltage is same as the second voltage and the fifth voltage is less than the first voltage.