Patent ID: 7800434

Claim:
A digital signal receiver comprising: an input terminal for receiving an original digital signal; a high pass filter, connected to the input terminal, for at least filtering out a DC component and a fundamental frequency of the original digital signal and passing higher frequencies contained in an edge transition of the original digital signal, the high pass filter being configured to output a positive spike upon the original digital signal transitioning to a first logic state and output a negative spike upon the original digital signal transitioning to a second logic state, a level of the original digital signal between its edge transitions not being used by the receiver to detect a state of the original digital signal; and a memory element coupled to an output of the high pass filter, the memory element comprising a latch having a first data input connected to receive a pulse corresponding to the positive spike and a second data input connected to receive a pulse corresponding to the negative spike, such that the latch outputs the first logic state upon the high pass filter outputting the positive spike and outputs a second logic state upon the high pass filter outputting the negative spike, to substantially recreate the original digital signal from only the edge transitions of the original digital signal.