Patent ID: 7390711

Claim:
A manufacturing method of a MOS transistor, comprising: forming a gate stack with a gate insulation layer and a gate electrode layer on a semiconductor substrate; forming an oxide layer at the sidewall of the gate electrode layer; forming a capping oxide layer on the oxide layer, wherein the capping oxide layer is formed as a middle temperature oxide (MTO) that is formed at a temperature of 700-780° C.; forming an extended source/drain region having a predetermined depth by a first ion implantation process using the gate stack as an ion implantation mask; forming a gate spacer layer on a sidewall of the gate stack; forming a first source/drain region that is deeper than the extended source/drain region by a second ion implantation process using the gate spacer layer as an ion implantation mask; and forming a second source/drain region that is shallower than the extended source/drain region by a third ion implantation process using the gate spacer layer as an ion implantation mask.