Patent ID: 7451376

Claim:
An irregular low-density parity-check code decoder comprising: (p 1 ×m 1 ) bit processing units configured to perform bit update computation for sequentially updating bit information corresponding to column positions included in respective rows of a first parity-check matrix and a second parity-check matrix, the first and second parity-check matrices being arranged adjacent to each other, the first parity-check matrix being formed of (m 1 ×n 1 ) first permuted matrices and divided into n 1 column blocks, each of the first permuted matrices having an array of (p 1 ×p 1 ), the second parity-check matrix being formed of (m 2 ×n 2 ) second permuted matrices and divided into n 2 column blocks, each of the second permuted matrices having an array of (p 2 ×p 2 )(p 1 >p 2 ), a bit at each of the column positions being set to “1”; p 1 parity processing units configured to perform parity update computation for updating parity information corresponding to row positions in p 1 columns of each of the n 1 column blocks of the first parity-check matrix, a bit at each of the row positions being set to “1”, p 2 parity processing units included in the p 1 parity processing units being configured to perform parity update computation for updating parity information corresponding to row positions in p 2 columns of each of the n 2 column blocks of the second parity-check matrix, a bit at each of the row positions being set to “1”; and a controller configured to cause, whenever the (p 1 ×m 1 ) bit processing units have finished bit update computation for p 1 column positions in the respective rows of the first parity-check matrix, the p 1 parity processing units to perform parity update computation corresponding to p 1 columns of one of the n 1 column blocks to which the p 1 column positions belong, the controller being configured to cause, after the p 1 parity processing units finish parity update computation for p 1 columns of a first one of the n 1 column blocks, the (p 1 ×m 1 ) bit processing units to start next bit update computation, the controller being configured to cause, whenever (p 2 ×m 2 ) bit processing units have finished bit update computation for p 2 column positions in the respective rows of the second parity-check matrix, the p 2 parity processing units to perform parity update computation corresponding to p 2 columns of one of the n 2 column blocks to which the p 2 column positions belong, the controller being configured to cause, after the p 2 parity processing units finish parity update computation for p 2 columns of a first one of the n 2 column blocks, the (p 2 ×m 2 ) bit processing units to start next bit update computation.