Patent ID: 7102892

Claim:
A carrier for arranging integrated circuit chips in a three-dimensional array on a circuit board, said carrier comprising: a) a platform with a top surface and a bottom surface; b) a first strut at a first side of said platform and a second strut at a second side of said platform, said struts providing support for said platform and thereby creating a space below the bottom surface of said platform; c) said platform having a pattern of connection pads on its top surface for receiving at least one integrated circuit chip on the top surface on the pattern of connection pads, a bottom side of each pad of said pattern of pads being connected to a via that passes down through said platform to a lower layer in said platform wherein said via connects to a conductive path that extends towards said first or second strut; d) said first and second struts having strut vias that extend up through each strut from the bottom of said strut to the top of said strut wherein each of said strut vias connect to a specific conductive path in said platform which specific conductive path connects to a specific via descending from a pad of the pads of the pattern of connection pads; e) wherein said carrier forms a modular unit that can accept at least one integrated circuit chip on said pattern of connection pads on the top surface of said platform on said pattern of connection pads and connect that chip to a printed circuit board to which said carrier is attached and provide in the space below the bottom surface of said carrier room for attaching at least a second integrated circuit chip to a circuit board on which said carrier is attached; f) wherein said vias are formed by plating an aperture with a conductive material.