Patent ID: 7092297

Claim:
In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to said plurality of rows, a plurality of bit lines coupled to said plurality of columns, the memory cells comprising a source, a control gate coupled to a word line, and a drain coupled to a bit line, and capable of storing at least one bit, a method for erasing said array of memory cells, comprising: applying a positive voltage to odd word lines in said plurality of word lines in a first phase of an erase cycle, said plurality of word lines comprising alternating odd and even word lines; applying a negative voltage to said even word lines in said plurality of word lines in said first phase of said erase cycle; applying said negative voltage to said odd word lines in said plurality of word lines in a second phase of said erase cycle; and applying said positive voltage to said even word lines in said second phase of said erase cycle.