Patent ID: 8880854

Claim:
A microprocessor having a plurality of architectural segment registers, wherein the plurality of architectural segment registers comprise first and second mutually exclusive subsets, the microprocessor comprising: a temporary register; a memory, configured to store first and second microcode routines; and an instruction decoder, coupled to said memory, configured to encounter an instruction that specifies one of the plurality of architectural segment registers for loading a new value into, wherein said instruction decoder is configured to invoke the first microcode routine if the one of the plurality of architectural segment registers is in the first subset and to invoke the second microcode routine if the one of the plurality of architectural segment registers is in the second subset; wherein the first microcode routine is configured to unconditionally load the new value into the one of the plurality of architectural segment registers; wherein the second microcode routine is configured to load the new value from memory into a temporary register of the microprocessor and to compare the new value loaded into the temporary resister with a current value stored in the one of the plurality of architectural segment registers; wherein the second microcode routine is configured to load the new value into the one of the plurality of architectural segment registers if the new value loaded into the temporary register does not equal the current value stored in the one of the plurality of architectural segment registers; and wherein the second microcode routine is configured not to load the new value into the one of the plurality of architectural segment register if the new value loaded into the temporary register equals the current value stored in the one of the plurality of architectural segment registers.