Patent ID: 7286383

Claim:
A memory structure, comprising a plurality of 6T memory cells each comprising two NMOS and two PMOS transistors with the drains of the NMOS transistors connected to the drains of the PMOS transistors, and further comprising two pass gates, a plurality of row select lines for selecting rows of memory cells in the structure, wherein the row select lines present a load, a plurality of column select lines, which together with the row select lines allow individual memory cells to be selected for precharging, and a pair of bit lines for each memory cell, wherein adjacent memory cells share a bit line to define a shared bit line, the selecting of memory cells comprising using logic that includes a first set of pass gates controlled by the row select lines and a second set of pass gates controlled by the column select lines, the load on the row select lines being reduced by sharing pass gates between adjacent memory cells in a row.