Patent ID: 8730625

Claim:
An electrostatic discharge (ESD) protection circuit comprising: a clamping transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode coupled to a second power supply voltage terminal, and a control electrode; and a trigger circuit comprising: a detection circuit having an input terminal coupled to monitor a power supply voltage, and having an output terminal; a first transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the output terminal of the detection circuit, and a second current electrode coupled to the second power supply voltage terminal; a first inverter having an input terminal coupled to the second current electrode of the first transistor, and an output terminal coupled to the control electrode of the clamping transistor for providing a trigger signal to the control electrode of the clamping transistor; a second inverter having an input terminal coupled to the output terminal of the first inverter, and an output terminal, wherein the second inverter having a switching voltage that is lower than a midpoint voltage of a power supply voltage provided to the first and second power supply voltage terminals; and a third inverter having an input terminal coupled to the output terminal of the second inverter, and an output terminal coupled to the control electrode of the first transistor and not coupled to the control electrode of the clamping transistor, wherein the third inverter is configured to provide a feedback signal to the first transistor that is distinct from the trigger signal provided by the first inverter to the clamping transistor.