Patent ID: 7315205

Claim:
An integrated circuit comprising: a first transistor coupled between an input node and a first node; a matching circuit block coupled between the first node and a second node; the second transistor coupled between the second node and a third node; a first circuit block coupled between the third node and a fourth node; a second circuit block coupled between the fourth node and a fifth node; a third transistor coupled between the fifth node and a sixth node; a third circuit block coupled between the sixth node and a seventh node; and a fourth circuit block coupled between the fourth node and the seventh node, wherein in a first mode of operation, a signal provided at the input node passes through the first transistor, matching circuit block, second transistor, first circuit block, and fourth circuit block, and in a second mode of operation, a signal provided at the input node passes through the first transistor, matching circuit block, second transistor, first circuit block, second circuit block, third transistor, third circuit block.