Patent ID: 7316975

Claim:
A method of forming a semiconductor structure, comprising: providing a substrate comprising a first transistor element and a second transistor element each having inner sidewall spacers having approximately the same width; depositing a layer of a material over said first transistor element and said second transistor element and said inner sidewall spacers; modifying a first portion of said layer of material located over said first transistor element; performing an etching process, said etching process being adapted to remove said modified first portion of said layer of material at a greater etch rate than an unmodified second portion of said layer located over said second transistor element; implanting ions of at least one dopant material into at least one of said first transistor element and said second transistor element after said etching process; performing a second etching process adapted to remove residues of said layer of material; and forming a silicide region proximate said first and second transistor elements, the silicide region being spaced from said first and second transistor elements based on a width of said inner sidewall spacers.