Patent ID: 8245232

Claim:
A system comprising: a memory system; a thread analysis component configured to analyze one or more threads requesting access to the memory system based on an effect of at least one of memory bandwidth, latency, or bank parallelism on performance of the memory system, the analysis being configured to determine or estimate at least a first value representing a stall time for one of the one or more threads due to sharing the memory system with one or more other threads, and a second value representing a stall time for the one thread in an absence of other threads sharing the memory system; a thread prioritization component configured to apply a stall-time fairness policy to prioritize requests from the one or more threads based at least in part on an analysis of the one or more threads by the thread analysis component; and a scheduling component configured to compute a memory slow-down value for the one thread based on a ratio of the first value to the second value.