Patent ID: 7307869

Claim:
A method for reading data from a dynamic memory circuit having at least one memory cell which is addressable via a word line and a bit line, comprising: a) turning on a switching element to connect a first reading amplifier to the bit line, wherein the switching element in the off state isolates the first reading amplifier from the bit line, activating the word line to read the memory cell, and activating the first reading amplifier to initiate assessment of an information on the bit line; b) turning off the switching element to decouple the bit line from the first reading amplifier, and activating a second reading amplifier, wherein the second reading amplifier is connected to the memory cell via the bit line and connected between the switching element and the memory cell, the second reading amplifier being isolated from the first reading amplifier when the switching element is turned off; c) when the switching element is turned off, writing the information back to the memory cell by utilizing the second reading amplifier connected to the memory cell via the bitline and transferring the information which has been read by the first reading amplifier to a data bus.