Patent ID: 7289096

Claim:
A shift register in which multiple stages are connected one after another to each other, the shift register sequentially outputting output signals of respective stages, the multiple stages including odd numbered stages for receiving a first clock signal and even numbered stages for receiving a second clock signal having a phase different from the first clock signal, each of the multiple stages comprising: a pull-up section for providing a corresponding one of the first and second clock signals to an output terminal; a pull-up driving section coupled to an input node of the pull-up section, for turning on the pull-up section in response to a front edge of an input signal and tuning off the pull-up section in response to a front edge of an output signal of one of next stages; a pull-down section for providing a first power voltage to the output terminal; and a pull-down driving section coupled to an input node of the pull-down section, for turning off the pull-down section in response to the front edge of the input signal and turning on the pull-down section in response to the front edge of the output signal of one of the next stages.