Patent ID: 7285477

Claim:
A method of fabricating a semiconductor structure, comprising: forming one or more devices in a silicon-on-insulator substrate, said substrate comprising a buried oxide layer between an upper silicon layer and a lower silicon layer and a pre-metal dielectric layer on a top surface of said upper silicon layer; forming a set of one or more first wiring levels on a top surface of said pre-metal dielectric layer, each wiring level of said first set of wiring levels comprising electrically conductive wires in a corresponding dielectric layer; removing said lower silicon layer from said substrate to expose a bottom surface of said buried oxide layer; forming electrically conductive first contacts to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said set of first wiring levels in physical and electrical contact with said first contacts; forming electrically conductive second contacts to said devices, one or more of said second contacts extending from said bottom surface of said buried oxide layer to said devices; forming a set of one or more second wiring levels over said buried oxide layer, each wiring level of said second set of wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts; forming a dielectric trench isolation in regions of said upper silicon layer, said trench isolation extending from said top surface of said upper silicon layer to said buried oxide layer; wherein said devices include field effect transistors comprising source/drains formed in said upper silicon layer and gate electrodes formed over said upper silicon layer and separated from said upper silicon layer by a gate dielectric layer; wherein said forming said one or more devices includes forming an electrically conductive metal silicide layer on top surfaces of said source/drains and said gate electrodes; and wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said trench isolation to physically and electrically contact a corresponding contact of said second contacts, said corresponding contact extending from said bottom surface of said buried oxide layer through said trench isolation.