Patent ID: 7158414

Claim:
A reference voltage generator circuit for nonvolatile memory devices, comprising: at least one bias reference voltage generator (BRVG) for generating a reference voltage at a predetermined reference node thereof; a start-up bias reference voltage generator (SBRVG) coupled to the reference node, the SBRVG further comprising: a first and a second pull-up pMOS transistors coupled in parallel with a gate of the first pull-up pMOS being controlled by a control signal and a gate of the second pull-up pMOS being coupled to the reference node; a first nMOS transistor for functioning as a reference memory cell with its gate controlled by a wordline control signal; a second nMOS transistor connected in series with the first nMOS transistor with its gate controlled by a bitline control signal; a third nMOS transistor coupled in series with the first pull-up pMOS transistor with a drain of the third nMOS transistor coupled to a drain of the first pull-up pMOS transistor, with a source of the third nMOS transistor coupled to the reference node, and with its gate controlled by a start-up control signal; a separation module coupled in series with the third nMOS transistor for isolating the reference node; and a negative feedback module coupled in series with and between the second nMOS transistor and the separation module; a monitor reference voltage generator (MRVG) for generating a monitor reference voltage; and a comparison module for comparing the monitor reference voltage with the reference voltage to produce the start-up control signal, wherein the SBRVG enhances a discharging speed of the reference voltage and when the monitor reference voltage and the reference voltage are matched, the start-up control signal stops the SBRVG from operating, thereby having the BRVG maintain the reference voltage.