Patent ID: 7176056

Claim:
A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) preparing a lead frame having a die pad, a plurality of leads arranged around the die pad, and a palladium plated layer formed in a part of each of the plurality of leads; (b) mounting a semiconductor chip over the die pad; (c) electrically connecting a plurality of electrodes of the semiconductor chip with the plurality of leads through a plurality of wires, respectively, by using a capillary; and (d) sealing the semiconductor chip, the plurality of wires, and a part of the plurality of leads with a resin, wherein one end portion of each of the plurality of wires is connected with the palladium layer at an adhered portion of each of the wire which is formed at the one end portion of each of the plurality of wires by applying an adhering force with the capillary; and wherein the adhering force of the capillary is set so as to secure at least 10 μm or more of a thickness of the adhered portion of each of the wires.