Patent ID: 8638157

Claim:
Level shifting circuitry for generating an output signal in response to an input signal, said input signal having one of an input high voltage level and an input low voltage level, said output signal having one of an output high voltage level and an output low voltage level, said level shifting circuitry comprising: a first level shifter configured to generate a first intermediate signal having a primary transition in response to a falling edge transition of said input signal and a secondary transition in response to a rising edge transition of said input signal, said falling edge transition comprising a transition from said input high voltage level to said input low voltage level and said rising edge transition comprising a transition from said input low voltage level to said input high voltage level; and a second level shifter configured to generate a second intermediate signal having a primary transition in response to said rising edge transition of said input signal and a secondary transition in response to said falling edge transition of said input signal; wherein: said first level shifter is configured to generate said primary transition of said first intermediate signal in response to said falling edge transition faster than said second level shifter generates said secondary transition of said second intermediate signal in response to said falling edge transition; said second level shifter is configured to generate said primary transition of said second intermediate signal in response to said rising edge transition faster than said first level shifter generates said secondary transition of said first intermediate signal in response to said rising edge transition; and said level shifting circuitry comprises output switching circuitry configured to switch said output signal between said output high voltage level and said output low voltage level in response to said primary transition of said first intermediate signal and said primary transition of said second intermediate signal, wherein said first level shifter comprises a first feedback loop configured to retain signal vales in one of a first state and a second state in dependence on said input signal, said first intermediate signal being obtained from the signal value at a first intermediate output point of said first feedback loop, and said second level shifter comprises a second feedback loop configured to retain signal values in one of said first state and said second state in dependence on said input signal, said second intermediate signal being obtained from the signal value at a second intermediate output point of said second feedback loop.