Patent ID: 7804123

Claim:
A nonvolatile semiconductor memory comprising: a semiconductor substrate including first and second diffusion layers; a channel formed between the first and second diffusion layers; a gate insulating film formed on the channel; a floating gate electrode formed on the gate insulating film, the floating gate electrode including an upper surface having a first upper end portion, a second upper end portion and a middle upper portion located between the first and second upper end portions; a control gate electrode formed above the floating gate electrode, the control gate electrode including a bottom surface having a first bottom end portion facing to the first upper end portion, a second bottom end portion facing to the second upper end portion and a middle bottom portion facing to the middle upper portion and located between the first and second bottom end portions; an inter-gate insulating film formed between the middle upper and middle bottom portions and absent in the first and second upper end potions and the first and second bottom end portions, the inter-gate insulating film having a first dielectric constant; and additional insulating films formed between the first upper and the first bottom end portions and between the second upper and second bottom end portions, the additional insulating films including a second dielectric constant which is lower than the first dielectric constant.