Patent ID: 7576960

Claim:
A circuit protection device comprising a ground fault circuit interrupter protection device ( 1 ), a ground fault test circuit module ( 3 ), a drive module ( 4 ) having a solenoid K 1 B, an SCR Q 1 , and a triode Q 3 , and a circuit module ( 2 ) having a master control system ( 2 - 1 ) that periodically sends out an impulse that simulates an electric shock signal, a monitoring system ( 2 - 2 ) that has an interlocking amplifier and comparator, and a signaling system ( 2 - 3 ) that indicates normal or faulty operation of the device, wherein an input of the circuit module ( 2 ) is connected to an output of the ground fault circuit interrupter protecting device ( 1 ); an output of the circuit module ( 2 ) is connected to an input of the ground fault circuit interrupter protecting device ( 1 ); an input of the circuit module ( 2 ) is connected to an output of the drive module ( 4 ), wherein the master control system ( 2 - 1 ) is connected to a power input line N; the monitoring system ( 2 - 2 ) is connected to an anode of the SCR Q 1 and a base of the triode Q 3 ; the signaling system ( 2 - 3 ) is connected to two input pins of the solenoid K 1 B, and wherein the master control system ( 2 - 1 ) comprises a resistor R 20 , a resistor R 23 , and a capacitor C 13 , each having one end connected together; another end of the resistor R 20 , and a first end of a triode Q 5 , a resistor R 15 , and a resistor R 12 , all being connected to a VCC; a resistor R 23 having one end connected to a second end of the triode Q 5 ; a resistor R 18 having one end connected to a third end of the triode Q 5 ; another end of the capacitor C 13 and one end of a capacitor C 11 , both being connected to a power input; another end of the resistor R 18 , capacitor C 11 , and one end of a resistor R 16 , all being connected to pin 1 and pin 2 of an integrated block U 2 A; another end of the resistor R 16 and one end of a capacitor C 12 , both being connected to pin 3 of the integrated block U 2 A; another end of the resistor R 15 and another end of the capacitor C 12 , both being connected to pin 5 and pin 6 of an integrated block U 2 B; a resistor R 19 , a resistor R 5 , a diode D 9 , and a resistor R 14 , all having one end connected to pin 4 of the integrated block U 2 B; another end of resistor R 19 and a first end of a triode Q 4 being connected; a second end of the triode Q 4 and another end of the resistor R 12 being connected; a third end of the triode Q 4 being connected to the power input line N which has passed through a signal transformer L 1 and a neutral transformer L 2 .