Patent ID: 7906779

Claim:
A thin film transistor comprising: a polysilicon layer formed over a substrate having a channel region, a source region and a drain region; a conductive layer formed in an upper layer of the polysilicon layer for covering at least a part of the source region and the drain region; a gate insulating film formed in a region to cover at least a region including the polysilicon layer and the conductive layer; a contact hole formed to penetrate the gate insulating film with a depth to expose the conductive layer; and a wiring layer formed along a sidewall of the contact hole, wherein a first edge portion of the conductive layer is tapered at an angle of 10 to 20 degrees with respect to a bottom surface of the conductive layer, the first edge portion being formed inside a second tapered edge portion of the polysilicon layer, the second tapered edge portion being tapered at an angle of 30 to 40 degrees with respect to a bottom surface of the polysilicon layer.