Patent ID: 7539845

Claim:
An apparatus, comprising: a plurality of tiled integrated circuits, each tiled integrated circuit comprising a plurality of tiles arranged in an array of tiles, each tile comprising a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and an interface coupled to a plurality of the tiles of a first tiled integrated circuit and a second tiled integrated circuit, the interface being configured to transfer data between one or more switches of tiles in a first tiled integrated circuit and one or more switches of tiles in a second tiled integrated circuit that is coupled to the first integrated circuit over the interface, wherein the interface comprises a communication link; a first multiplexer configured to multiplex data from switches of at least two and fewer than all edge tiles of the first tiled integrated circuit to transfer across a communication link to the second tiled integrated circuit; a second multiplexer configured to multiplex data from switches of at least two and fewer than all edge tiles of the second tiled integrated circuit to transfer across a communication link to the first tiled integrated circuit; wherein each tiled integrated circuit is configured send a message out of an origin tile, receive the message at a first edge tile that does not have a switch physically connected to a multiplexer of the interface, trigger an interrupt in response to the message being routed out of the first edge tile, determine whether the first edge tile has a switch physically connected to a multiplexer of the interface in response to the interrupt, and forward the message to a second edge tile that does have a switch physically connected to a multiplexer of the interface in response to determining that the first edge tile does not have a switch physically connected to a multiplexer of the interface, with the first and second edge tiles being on an edge of the array of tiles of the tiled integrated circuit from which the message is sent.