Patent ID: 7386821

Claim:
A method for forming an integrated circuit, comprising: accessing a library of primitive cells and edge codes in the formation of an integrated circuit layout, wherein each primitive cell includes four side edges, each side edge being characterized by a predetermined edge code, each primitive cell further including (i) parital-layout features and (ii) a portion thereof that includes a region or feature other than partial-layout features, wherein the partial layout features comprise features selected from the group consisting of a portion of a gate electrode, a portion of an active region of a transistor device, and a portion of an active area contact, and wherein each partial-layout feature by itself would not suffice as a functional portion of a semiconductor device of the integrated circuit; using at least one edge code of at least one previously placed primitive cell of the integrated circuit layout, selecting a primitive cell from the library based upon an edge code of the primitive cell with compatibility information of the at least one edge code of the at least one previously placed primitive cell and placing the selected primitive cell into the integrated circuit layout adjacent the at least one previously placed primitive cell based upon the corresponding edge code compatibility, wherein the compatibility information comprises information for identification of edges of other primitive cells that the selected primitive cell can be adjacent to in the integrated circuit layout; and manufacturing the integrated circuit using the integrated circuit layout.