Patent ID: 7386691

Claim:
An electronic device comprising: a plurality of N elementary source memories having respective source addresses for storing a plurality of N input data sets; a processor connected to said source memories and clocked by a clock signal and having a plurality of N outputs for providing, per cycle of the clock signal, a plurality of N output data sets each corresponding to a respective one of the N input data sets and having a respective source address and target address associated therewith; a plurality of N target memories each having a respective target address associated therewith; a plurality of N interleaving tables for storing a respective target address for each source address; and a plurality of N cells connected in a ring, each cell also being connected between a respective output of said processor, a respective interleaving table, and a respective target memory; each cell for receiving output data sets from the respective output of said processor and from a plurality of adjacent cells in the ring, and providing at least one of the received output data sets to at least one of said adjacent cells and said respective target memory based upon the respective source and target addresses thereof and said respective interleaving table.