Patent ID: 7304335

Claim:
A vertical-conduction and planar-structure MOS device having a double thickness gate oxide comprising: a semiconductor substrate comprising spaced apart active areas and defining a JFET area there between, said JFET area also forming a channel between said spaced apart active areas; a gate oxide on said semiconductor substrate and comprising a first portion having a first thickness on said active areas and at a periphery of said JEET area, and a second portion having a second thickness on a central area of said JFET area, the second thickness being greater than the first thickness; said JFET area comprising an enrichment region under the second portion of said gate a first polysilicon layer on said first portion of said gate oxide; a first polysilicon layer on said first portion of said gate oxide; and a second polysilicon layer on said second portion of said gate oxide and directly on said first polysilicon layer, with an entire upper surface of said second polysilicon layer being planar.