Patent ID: 7155647

Claim:
A system configured for scan chain testing, said system comprising: a scan clock signal; a first block coupled to the scan clock signal, wherein the first block includes a first plurality of scan cells, each of the first plurality of scan cells being configured to maintain a scan cell state; and a second block coupled to the scan clock signal, wherein the second block includes a second plurality of scan cells, each of the second plurality of scan cells being configured to maintain a scan cell state; wherein each of the first block and the second block are configured to operate in a first mode, wherein in the first mode the first block is configured to convey the first plurality of scan cell states out of the first block responsive to detecting the scan clock signal; and wherein the first block is configured to operate in a second mode, wherein in the second mode the first block is configured to recirculate its scan cell states responsive to detecting the scan clock signal; wherein whenever the first block conveys scan cell states between the first plurality of scan cells, the second block conveys scan cell states between the second plurality of scan cells; a control circuit configured to return said first plurality of scan cells to an original state by: determining a number N of said first plurality of scan cells; determining a number M of cycles the first plurality of scan cells has recirculated subsequent to being in said original state; determining a number P of cycles required to return said scan cells to said original state, wherein P is calculated to be M % N cycles, where % is the modulus operator; and recirculating the first plurality of scan cells an additional P cycles.