Patent ID: 8291207

Claim:
An integrated circuit package configured to operate in a network device, the package comprising; a data interface enabling interconnection with a data link and receipt of an 8B/10B encoded audio-video signal from a first network device connected with the interface through the data link, wherein the link is configured to receive the 8B/10B encoded audio-video signal at a data rate comprising one of a finite number of known bit rates; local reference clock circuitry having a stable local reference clock frequency; clock generation circuitry operable during a device start-up period prior to the engagement of an operating system, said clock generation circuitry enabling the use of signal edges that form part of the received 8B/10B encoded audio-video signal together with an analysis of the finite number of known bit rates to extract a signal based clock frequency from the 8B/10B encoded audio-video signal wherein the signal based clock is associated with one of said finite number of known bit rates; frequency locking circuitry that enables frequency locking the signal based clock frequency with said local reference clock frequency in the absence of link training information; and decoding circuitry configured to decode the 8B/10B encoded audio-video signal.