Patent ID: 7359474

Claim:
A clock-recovering filter circuit for use in a clock recovery circuit that generates a recovery clock signal from input data from an external device and a reference clock signal, the filter circuit comprising: a first input terminal which receives a first phase-advancing signal for advancing the phase of the recovery clock signal when the recovery clock signal is delayed with respect to the input data; a second input terminal which receives a first phase-delaying signal for delaying the phase of the recovery clock signal when the recovery clock signal is advancing with respect to the input data; a pulse-inserting circuit which inserts pulses in the first phase-advancing signal or the first phase-delaying signal, thereby generating a second phase-advancing signal or a second phase-delaying signal; and a frequency-offset detecting circuit which detects frequency-offset data from the second phase-advancing signal and the second phase-delaying signal, the frequency-offset data representing a frequency difference between the recovery clock signal and the reference clock signal, wherein the pulse-inserting circuit inserts the pulses in accordance with the frequency-offset data when the first phase-advancing signal or the first phase-delaying signal is not input.