Patent ID: 8705286

Claim:
A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising: a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits after a read operation; means for reading and latching a page of data in each of a series of reading cycles, wherein said reading and latching in a current reading cycle is directed to a current page of data on a current wordline and is responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom, said reading and latching arranged to, in the current reading cycle, other than a first reading cycle, read and latch the current page while outputting a previous page read and in a reading cycle just prior to the current reading cycle; and means for preemptively reading and latching the prerequisite data for the current page prior to the current reading cycle; and wherein said means for preemptively reading and latching is arranged to, while the previous page is output, preemptively reads and latches the prerequisite data for the current page prior to the current reading cycle and to preemptively read and latch the prerequisite data for a next page that is to be read while the previous page is output.