Patent ID: 7109736

Claim:
A channel for an integrated circuit tester, the channel comprising: an input/output (I/O) port; a first transistor for turning on and off in response to a first control signal supplied thereto, said first transistor having a first terminal linked to said I/O port, and having a second terminal, said first transistor conductively linking said first and second terminals through low impedance when turned on and isolating said first and second terminals through high impedance when turned off; a second transistor for turning on and off in response to a second control signal supplied thereto, having a third terminal linked to said I/O port, and having a fourth terminal, said second transistor conductively linking said third and fourth terminals through low impedance when turned on and isolating said third and fourth terminals through high impedance when turned off; reference signal generation means for selectively supplying one of a first reference voltage and a constant current to said fourth terminal selected in response to a third control signal supplied thereto; a source of second reference voltage; comparator means linked to said I/O port for producing an indicating signal indicating whether a voltage at said I/O port exceeds an adjustable reference voltage supplied thereto; and control means for supplying said first, second and third control signals and said adjustable reference voltage to said first and second transistors, said reference signal generation means and said comparator respectively.