Patent ID: 7790494

Claim:
A method of fabricating a memory device, the method comprising: forming a bit line on a substrate in a first direction; forming a stack including a first interlayer insulating layer, a lower word line, a trap site and a first sacrificial layer in a second direction crossing the bit line; forming a second interlayer insulating layer to fill sidewalls of the stack and including a contact hole to expose the bit line at the sidewalls of the stack; forming a pad electrode inside the contact hole; forming a cantilever electrode on the pad electrode and the second interlayer insulating layer in the first direction, to be connected to the top of the first sacrificial layer; forming a second sacrificial layer and an upper word line on the cantilever electrode and the second interlayer insulating layer formed on the stack in the second direction; forming a third interlayer insulating layer around sidewalls of the second sacrificial layer and the upper word line; forming a trench to expose the first interlayer insulating layer at the bottom, by removing the upper word line, the second sacrificial layer, the cantilever electrode, the first sacrificial layer, the trap site and the lower word line in the second direction; and forming a space above and under the cantilever electrode, by removing the first sacrificial layer and the second sacrificial layer exposed by the trench.