Patent ID: 7912888

Claim:
A computing device comprising: rounding processing means for inputting therein multiplier factors and multiplicands respectively constituted of z bits (where z≧2), determining whether specific areas of respective upper n bits (where z>n≧2) of the multiplier factors and the multiplicands are respectively being used, discarding the upper n bits and lower (z/2-n) bits in the multiplier factors and the multiplicands, if the specific areas are not used and rounding the corresponding multiplier factors and multiplicands to z/2 bits respectively, and discarding lower z/2 bits in the multiplier factors and the multiplicands, if the specific areas are used and rounding the corresponding multiplier factors and multiplicands to z/2 bits respectively; memory means for storing information about the discarded respective numbers of bits respectively; a z/2-bit multiplier for performing multiplication on the multiplier factors and multiplicands rounded by the rounding processing means and outputting multiplication results therefrom; and digit adjusting means for shifting the multiplication results on the basis of the number-of-bits information stored in the memory means to adjust digits.