Patent ID: 7809081

Claim:
A method for operating a linearizer for a circuit, the method comprising: generating a set of coefficients via a characterizer means coupled to an input to and an output from the circuit; predistorting a signal input to the circuit via predistortion means responsive to the coefficients and generating via the circuit a linearized output in response thereto; providing in the predistortion means circuitry configured for performing the steps of: filtering the signal through a linear digital filter having one or more linear digital filter taps, each linear digital filter tap other than a first linear digital filter tap being successively delayed by one delay unit; generating one or more powers of the signal; inputting one or more of the generated powers of the signal through one or more tapped delay lines, each tapped delay line having one or more nonlinear digital filter taps, each nonlinear digital filter tap other than a first nonlinear digital filter tap being successively delayed by one delay unit; applying the coefficients to the linear and nonlinear digital filter taps; summing each of the nonlinear digital filter taps corresponding to a certain number of delay units; and adding the sum of each of the delay units from the summing step to a particular linear digital filter tap.