Patent ID: 7995017

Claim:
A thin film transistor array panel comprising: a substrate; a first signal line formed on the substrate and extending in a first wiring layer; a second signal line formed on the substrate and extending in a second wiring layer to cross with the first signal line; a first thin film transistor and a second thin film transistor that are respectively connected to the first and the second signal lines; a pixel electrode that is partitioned to have first and second partitions, wherein the first and second partitions have respective first and second partition boundary edges, with the first partition boundary edge being spaced apart from and facing the second partition boundary edge, wherein the first signal line extends underneath the first and second partitions and along a not straight path also disposed under the first and second partitions, and wherein the first and second spaced apart partition boundary edges of the respective first and second partitions respectively extend along and above opposed sides of the not straight path, and a connection electrically connecting the first partition and the second partition; wherein the connection is disposed in the same wiring layer as that of the second signal line.