Patent ID: 8552901

Claim:
An analog-to-digital converter (ADC) comprising: a plurality of single slope ADCs, each comprising: an analog input operable to receive an analog input signal; a ramp input operable to receive an analog ramp signal of a plurality of analog ramp signals; and a comparator operable to compare the analog input signal to the analog ramp signal; and an output operable to produce a digital representation of the analog input signal based upon the comparison, wherein the plurality of single slope ADCs are operable to receive analog ramp signals that are out of phase with one other; a ramp generator that is operable to generate analog ramp signals for the plurality of single slope ADCs, the ramp generator comprising circuitry to simultaneously generate the plurality of analog ramp signals such that successive ramps signals of the plurality of analog ramp signals are out of phase with one another based upon a clock signal; and digital output circuitry operable to receive outputs from the plurality of single slope ADCs and to produce a digital representation of the analog input signal based thereupon.