Patent ID: 7659160

Claim:
A method comprising: forming a semiconductor device that comprises a source region, a drain region, a channel region present in a semiconductor substrate, a gate dielectric layer located over the channel region of the semiconductor substrate, a gate electrode located over the gate dielectric layer, a first dielectric layer located over and covering the source region, the drain region, and the gate electrode, and a second dielectric layer located over the first dielectric layer; selectively removing a portion of the first and second dielectric layers to form at least one contact hole that exposes either the source region or the drain region; selectively removing a portion of the first dielectric layer along a sidewall of said at least one contact hole; and filling said at least one contact hole with a metallic material to form at least one metallic contact that is electrically connected to either the source or the drain region, wherein said at least one metallic contact comprises a lower portion that is located in the first dielectric layer and an upper portion that is located in the second dielectric layer, and wherein the lower portion has a larger cross-sectional area than the upper portion, and said upper portion is centrally aligned to the lower portion to provide an inverted T cross sectional geometry, wherein the upper portion has a first cross sectional diameter and the lower portion has a second cross sectional diameter, wherein the first cross sectional diameter is equal to or less than ½ the second cross sectional diameter.