Patent ID: 8159033

Claim:
An ESD protection device including a MOS structure formed inside of a semiconductor functional device layer, the ESD protection device comprising: a semiconductor substrate; a drain region of the MOS structure being a surge absorbing end and formed in the semiconductor substrate; a device isolation region surrounding the MOS structure; and a junction forming region formed in the semiconductor substrate between the drain region of the MOS structure and the device isolation region, the junction forming region being in contact with the drain region and exposed at a surface of the semiconductor substrate to form a PN junction together with the drain region, the drain region including at a portion in contact with the junction forming region a lower impurity concentration drain region having an impurity concentration lower than that of another higher impurity concentration portion in the drain region, the lower impurity concentration portion being exposed at said surface, the higher impurity concentration portion, the lower impurity concentration portion and the junction forming region are disposed in this given order along a line that is parallel to said surface.