Patent ID: 8060717

Claim:
A system for regulating data operations access to a plurality of non-Flash embedded re-writable non-volatile memory devices, comprising: a plurality of memory devices in electrical communication with a bus, each memory device including a silicon semiconductor substrate including active circuitry fabricated on a logic plane of the silicon semiconductor substrate, one or more memory layers in direct contact with and fabricated directly above the silicon semiconductor substrate, at least one of the memory layers in the plurality of memory devices configurable to operate as an obfuscation layer in electrical communication with the bus and operative to obstruct physical access to one or more memory layers, at least one two-terminal cross-point memory array embedded in each memory layer, each array including a plurality of first conductive array lines that are oriented orthogonally to a plurality of second conductive array lines, the plurality of first and second conductive array lines are electrically coupled with at least a portion of the active circuitry, and a plurality of re-writeable non-volatile two-terminal memory elements operative to retain stored data in the absence of electrical power, each memory element positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines, each two-terminal memory element is electrically in series with its respective first and second conductive array lines; and a memory access circuit including a device access determinator in electrical communication with a host device interface and configured to determine a geographical location of the memory devices, the device access determinator including determination logic configured to enable or disable data operations access to one or more of the plurality of memory devices in response to signals communicated over the host device interface, and a memory storage controller in electrical communication with the bus and configured to control data operations access to the at least one of two-terminal cross-point memory arrays, the memory storage controller including an obfuscation layer manager circuit in electrical communication with the bus and configured to perform data operations on one or more obfuscation layers.