Patent ID: 8187969

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer over surfaces of the conductive patterns such that the first conductive layer is formed within the contact holes; etching the surface of the first conductive layer to expose upper end surfaces of the conductive patterns so as to form contact plugs isolated in the respective contact holes; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming a hard mask layer on the resultant structure including the partially etched conductive patterns, wherein the hard mask layer is formed after the step of forming the conductive layer, the interlayer dielectric and the contact plug.