Patent ID: 8848464

Claim:
A semiconductor device comprising: a bit line; a word line; a memory cell comprising: a first transistor including a channel region comprising an oxide semiconductor, a second transistor including a channel region comprising any of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide, and a capacitor, wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the bit line, wherein the other of the source and the drain of the first transistor and a gate of the second transistor are electrically connected to one of electrodes of the capacitor, and wherein the other of the electrodes of the capacitor is electrically connected to the word line; and a writing circuit electrically connected to the memory cell through the bit line, the writing circuit configured to input one of a plurality of write data potentials or a reference potential as a write data potential to the memory cell, and wherein the writing circuit is configured to write the one of the plurality of write data potentials to the memory cell when a potential applied to the gate of the second transistor is higher than a threshold voltage of the second transistor.