Patent ID: 6924184

Claim:
A method for making a semiconductor device, comprising: providing a substrate; providing a gate stack over the substrate; implanting into the substrate using the gate stack as a mask to form a source and a drain adjacent to the gate stack; forming a first dielectric layer over the substrate and gate stack; forming a second dielectric layer over the first dielectric layer; polishing the second dielectric layer to the first dielectric layer over the gate stack to form a substantially planar surface comprising an exposed portion of the first dielectric layer over the gate stack and an exposed surface of the second dielectric layer; forming a third dielectric layer over the substantially planar surface, wherein the third dielectric comprises a spacer dielectric layer on the substantially planar surface and an anti-reflective layer over the spacer dielectric layer; etching vias in the third dielectric layer, the second dielectric layer, and the first dielectric layer over the source and the drain; and filling the vias with conductive material.