Patent ID: 7732862

Claim:
A semiconductor device, comprising: a substrate having a major surface, wherein the substrate comprises a first conductivity type; a pedestal structure overlying a portion of the major surface, wherein the pedestal structure includes a dielectric material; a conductive material disposed along a side surface of the pedestal structure to define an edge of a first conduction electrode of the semiconductor device, wherein the first conduction electrode comprises a control electrode; an offset doped region of a second conductivity type formed in the major surface adjacent the first conduction electrode, wherein the offset doped region comprises a wider portion adjacent the major surface, and a narrower portion underlying the wider portion, and wherein the wider portion of the offset doped region forms a drain edge of a channel region when the semiconductor device is in operation, and wherein the control electrode overlaps portions of both the wider and the narrower portions of the offset doped region; a current carrying region of the first conductivity type formed in the offset doped region; a second doped region of the second conductivity type formed in the substrate external to the offset doped region and in proximity to and spaced apart from the drain edge of the channel region; and a first conductive layer formed as part of the pedestal structure and coupled to the second doped region.