Patent ID: 7202706

Claim:
A circuit fabricated in an integrated circuit with a differential input and a differential output, the circuit comprising: a differential circuit with a first NMOS transistor and a second NMOS transistor, where the first NMOS transistor has a source, a gate, and a drain, and the second NMOS transistor has a source, a gate, and a drain, where the source of the first NMOS transistor and the source of the second NMOS transistor are coupled, where the gate of the first NMOS transistor and the gate of the second NMOS transistor are configured to receive the differential input, and where the drain of the first NMOS transistor and the drain of the second NMOS transistor are configured to provide the differential output; a first current source with at least a first terminal, where the first terminal of the first current source is coupled to the source of the first NMOS transistor and to the source of the second NMOS transistor; a first active load with at least a first terminal coupled to the drain of the first NMOS transistor of the differential circuit, where the first terminal of the first active load has an inductive impedance characteristic as seen from the drain of the first NMOS transistor; and a second active load coupled to the drain of the second NMOS transistor of the differential circuit, where the second active load has an inductive impedance characteristic as seen from the drain of the second NMOS transistor; wherein the differential circuit, the first current source, the first active load, and the second active load form at least part of a state machine.