Patent ID: 7209798

Claim:
A method of operating a semiconductor processing system comprising: receiving, by the semiconductor processing system, input data comprising reference metrology data for a wafer including reference metrology data for at least one isolated structure on the wafer and reference metrology data for at least one nested structure on the wafer; creating an Iso/Nested control strategy including a first control plan for controlling a first etching process using the reference metrology data for the wafer; creating a second control plan for controlling a second etching process using the reference metrology data for the at least one nested structure on the wafer; calculating a measured bias trim using the difference between measured data for an isolated structure and measured data for a nested structure; determining a bias trim target; calculating a bias trim adjustment; determining the recipe settings to achieve the desired bias trim adjustment; computing the remaining BARC trim; and determining the recipe settings to achieve the desired BARC trim.