Patent ID: 7511316

Claim:
A semiconductor device including a semiconductor substrate which comprises: a first semiconducting region; a second semiconducting region formed on an upper surface of said first semiconducting region with higher impurity concentration than that of said first semiconducting region; a third semiconducting region of the conductivity type different from the conductivity types of said first and second semiconducting regions, said third semiconducting region being formed adjacent to said second semiconducting region and on the opposite side of said second semiconducting region from said first semiconducting region; a fourth semiconducting region formed on a bottom surface of said first semiconducting region with the higher impurity concentration than that of said first semiconducting region; and a PN junction region formed between said second and third semiconducting regions; wherein said third semiconducting region is formed in a whole upper surface of said semiconductor substrate; a periphery region is formed integrally with said third semiconducting region and annularly along whole side surfaces of said semiconductor substrate; said periphery region of the third semiconducting region is formed adjacent to the outer surfaces of said first, second and fourth semiconducting regions so as to encircle and cover said first, second and fourth semiconducting regions with said periphery region to prevent outward exposure of the outer surfaces of said first, second and fourth semiconducting regions from the side surfaces of said semiconductor substrate; the periphery region of said third semiconducting region is in contact to the outer surface of said fourth semiconducting region at a bottom surface of said semiconductor substrate; the bottom surface of said semiconductor substrate is covered with an insulating layer formed with an opening; and an electrode is in electrical contact to said fourth semiconducting region through said opening.