Patent ID: 8451085

Claim:
A co-fired multi-layer stack chip resistor, comprising: a ceramic substrate having a predetermined thickness, and formed by stacking a plurality of ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant, wherein the porcelain slurry is attached to the surface of the bearing membrane; a multi-layer stack resistance structure monomer stacked on the ceramic substrate, and comprising a plurality of bearing membranes and a plurality of resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction; wherein the multi-layer stack resistance structure monomer and the ceramic substrate are sintered and shaped with the predetermined sintering temperature and the predetermined sintering time in a kiln stove after stacking the multi-layer stack resistance structure monomer on the ceramic substrate; wherein the first and the second terminal portions of each resistive layer extend respectively alone the horizontal direction to form the terminal connectors, and the terminal connectors are respectively exposed to the first and the second terminal planes of the multi-layer stack resistance structure monomer; a first terminal pole formed on the first terminal plane of the multi-layer stack resistance structure monomer with conducting materials, and connected to the first terminal portion of every resistive layer; and a second terminal pole formed on the second terminal plane of the multi-layer stack resistance structure monomer with conducting materials, and connected to the second terminal portion of every resistive layer.