Patent ID: 8379846

Claim:
An encryption apparatus having a reset port at which a reset signal is applied, said apparatus comprising: a memory for storing a first ciphertext key; a first key register, configured as a volatile register, for storing a first plaintext key; a second key register for storing a second plaintext key; a third key register, configured as a non-volatile register, for storing a third plaintext key; an encryption processor coupled to said first, second, and third key registers; a random number generator coupled to said first key register; and a controller coupled to said random number generator, said memory, and said encryption processor, said encryption processor and said controller being configured to cause said first plaintext key to be formed using said random number generator and stored in said first key register in response to activation of said reset signal, configured to cause said second plaintext key to be generated by said encryption processor from said first ciphertext key using said first plaintext key and to be stored in said second key register, configured to apply first and second cryptographic algorithms, wherein said first cryptographic algorithm requires more processing time than said second cryptographic algorithm, said first cryptographic algorithm being applied using said third plaintext key, and said second cryptographic algorithm being applied using said first plaintext key, and configured to convert said first ciphertext key into a second ciphertext key using said second then said first cryptographic algorithms to allow said second plaintext key to be recoverable after said activation of said reset signal.