Patent ID: 7851295

Claim:
A method of manufacturing a flash memory device, comprising: forming a gate oxide layer on the semiconductor substrate; forming a first polysilicon layer on the gate oxide layer; forming an ONO layer on the first polysilicon layer; forming a second polysilicon layer on the ONO layer; patterning the gate oxide layer, the first polysilicon layer, the ONO layer, and the second polysilicon layer to form a gate region; forming a first tetraethyl orthosilicate (TEOS) layer sidewall spacer on both sides of the gate region; forming an oxide layer on the semiconductor substrate; forming a silicon nitride (SiN) layer on the semiconductor substrate; and patterning the oxide layer and the SiN layer to form a passivation layer and a SiN layer spacer, wherein the passivation layer is formed on the semiconductor substrate and under the SiN layer and on the side of the first TEOS layer; wherein the first TEOS layer is surrounded by the gate region, the SiN layer, the passivation layer, and teh semiconductor substrate.