Patent ID: 7687338

Claim:
A method comprising: forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process, said disposable spacer process leaving an oxide spacer on top of source and drain extension regions of said pFET forming a height gap between said oxide spacer and said eSiGe; depositing a gap-filling layer directly on said eSiGe in said source and drain regions and on said oxide spacer on top of said source and drain extension regions in a first process, said gap-filling layer covering said height gap and forming a coplanar surface of said source and drain regions and said source and drain extension regions; depositing a layer of offset spacer material on top of said gap-filling layer in a second process different from said first process; etching said offset spacer material and said gap-filling layer, thus forming a set of offset spacers and exposing said eSiGe in said source and drain regions of said pFET; and finishing formation of said pFET.