Patent ID: 8020168

Claim:
A method of dynamic virtual software pipelining on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising: segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, including assigning each stage to a thread of execution on an IP block; and executing each stage on a thread of execution on an IP block, including: executing a first stage, producing output data, the output data including control information for the next stage and payload data; sending by the first stage the produced output data to a second stage; and consuming the produced output data by the second stage in dependence upon the control information.