Patent ID: 8372711

Claim:
A method of fabricating a non-volatile memory device, the method comprising: defining an active region on a semiconductor substrate; forming a first conductive layer on the active region of the substrate; forming an insulating layer on the first conductive layer; forming a second conductive layer on the insulating layer opposite the first conductive layer; forming a hard mask layer on the insulating layer; patterning the hard mask layer, the second conductive layer, and the insulating layer to respectively form a hard mask pattern, an upper conductive pattern and an insulating pattern; forming a third conductive layer on exposed surfaces of the hard mask pattern, the upper conductive pattern, the insulating pattern, and the first conductive layer; anisotropically etching a portion of the third conductive layer to form a sidewall conductive pattern on, and electrically connecting, at least a portion of sidewalls of the upper conductive pattern and the first conductive layer; etching a portion of the first conductive layer to form a lower conductive pattern using the hard mask pattern and the sidewall conductive pattern as an etch mask; and patterning the hard mask pattern, the upper conductive pattern, the insulating pattern, and the lower conductive pattern to form a plurality of gate lines and a plurality of word lines, wherein the gate lines cross over the active region, and wherein a plurality of the word lines are between adjacent pairs of the gate lines and cross over the active region.