Patent ID: 8841942

Claim:
A voltage switch circuit having an output terminal connected to an array bus signal line, an input voltage being selectively provided to the array bus signal line by a decoding unit, the voltage switch circuit comprising: a first NMOS transistor, wherein a drain terminal of the first NMOS transistor is connected to the output terminal of the voltage switch circuit, and a source terminal and a body terminal of the first NMOS transistor are connected to a node b; a first bias voltage controlling circuit, wherein a control terminal of the first bias voltage controlling circuit is connected to the output terminal of the voltage switch circuit, an input terminal of the first bias voltage controlling circuit is connected to an input terminal of the voltage switch circuit, and an output terminal of the first bias voltage controlling circuit is connected to a gate terminal of the first NMOS transistor, wherein in a first operating state, the node b is biased by the first bias voltage controlling circuit to have a reference voltage; a second NMOS transistor, wherein a drain terminal of the second NMOS transistor is connected to the node b, a gate terminal of the second NMOS transistor connected to a logic voltage source, and a source terminal and a body terminal of the second NMOS transistor are connected to a node a; a second bias voltage controlling circuit, wherein a control terminal of the second bias voltage controlling circuit is connected to the input terminal of the voltage switch circuit, an input terminal of the second bias voltage controlling circuit is selectively connected to the logic voltage source and a read voltage source, and an output terminal of the second bias voltage controlling circuit is connected to the node a; and a third NMOS transistor, wherein a drain terminal of the third NMOS transistor is connected to the node a, a gate terminal of the third NMOS transistor is connected to the input terminal of the voltage switch circuit, and a source terminal and a body terminal of the third NMOS transistor are connected to a ground terminal.