Patent ID: 8237043

Claim:
An integrated parallel Peltier Seebeck element chip comprising: a plurality of adjacent pairs, each adjacent pair including a first silicon semiconductive portion and a second silicon semiconductive portion which have different Seebeck coefficients and are formed in an insulating substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface, each of the first and second silicon semiconductive portions extending through the insulating substrate from the first substrate surface to the second substrate surface; a plurality of thermal conduction terminal portions, wherein each of the thermal conduction terminal portions connects, by ohmic contact, the first and second silicon semiconductive portions of one of the adjacent pairs on the first substrate surface; a plurality of terminal side portions, wherein each terminal side portion covers, by ohmic contact, only one of the adjacent first and second silicon semiconductive portions of the adjacent pairs on the second substrate surface; and a plurality of conducting wires, wherein each of the conducting wires is electrically connected with only one of the terminal side portions.