Patent ID: 8179492

Claim:
A liquid crystal display device comprising: a pair of substrates opposed to each other; a liquid crystal layer sealed between the substrates; a plurality of gate bus lines formed on one of the substrates so as to be parallel with each other; a plurality of drain bus lines formed so as to cross the gate bus lines with an insulating film interposed in between; a plurality of storage capacitance bus lines formed parallel with the gate bus lines; first and second transistors each having a gate electrode electrically connected to an nth gate bus line and a drain electrode electrically connected to one of the drain bus lines; a first pixel electrode electrically connected to a source electrode of the first transistor; a second pixel electrode which is electrically connected to a source electrode of the second transistor and is separated from the first pixel electrode; a pixel region having at least a first sub-pixel in which the first pixel electrode is formed and a second sub-pixel in which the second pixel electrode is formed; a third transistor having a gate electrode electrically connected to an (n+1)th gate bus line, a source electrode connected or coupled to the second pixel electrode, and a drain electrode connected or coupled to one of the storage capacitance bus lines; a buffer capacitance portion which establishes capacitive coupling between the drain electrode of the third transistor and the storage capacitance bus line or between the source electrode of the third transistor and the second pixel electrode; an extending portion electrically connected to the (n+1)th gate bus line and extending in parallel with the (n+1)th gate bus line; and wherein the gate electrode of the third transistor is provided in the extending portion.