Patent ID: 8837202

Claim:
A semiconductor memory device comprising: a bit line; four word lines; a first selection line parallel to the four word lines; a second selection line parallel to the four word lines; and two cells each including two memory cells, a sub bit line, a first selection transistor, a second selection transistor, and an amplifier circuit, wherein a drain of the first selection transistor is connected to the bit line, wherein a gate of the first selection transistor and a gate of the second selection transistor are connected to the first selection line and the second selection line, respectively, wherein a source of the first selection transistor and a first terminal of the amplifier circuit are connected to the sub bit line, wherein a second terminal of the amplifier circuit is connected to a source of the second selection transistor, wherein a drain of the second selection transistor is connected to the bit line, wherein each of the two memory cells includes a transistor and a capacitor, wherein capacitance of the capacitor is 1 fF or less, and wherein the transistor of each of the two memory cells comprises a gate connected to one of the four word lines.