Patent ID: 7991926

Claim:
A packet switch comprising: a plurality of input ports; a plurality of output ports; a plurality of input buffers, each having a same storage size, each associated with a different one of the plurality of input ports, and each comprising a number of banks as a function of N, wherein N is defined by a ratio of a preselected size to a smallest packet size and wherein N is an integer greater than or equal to one, each bank having a same storage size, and each bank being configured to store a different one of N segments of a packet received by its associated input port; a plurality of output buffers, each having a same storage size, each associated with a different one of the plurality of output ports, and each comprising a number of banks as a function of N, each bank having a same storage size, and each bank configured to receive from the memory during each packet transmission time a different segment of a packet destined for an associated output port; and a memory configured to store in each of its addressable storage locations a subsegment of each packet stored in each of the input buffers, wherein during each packet transmission period all packets stored in all of the plurality of input buffers are stored in the memory.