Patent ID: 8572456

Claim:
An interleaving system comprising: a plurality of interleavers, each interleaver arranged to address data items from a respective section of a block of data items with destinations in segments of an interleaved version of the block; a plurality of sets of first-in, first out buffers (FIFOs), a respective set of FIFOs for each interleaver such that each set of FIFOs is associated with a respective interleaver, each set of FIFOs containing a plurality of FIFOs, each FIFO in the respective set of FIFOs is associated with a respective one of the segments to which the respective interleaver can address data items, and the respective interleaver is associated with each FIFO in the respective set of FIFOs; a plurality of memories, each memory for a respective one of the segments; and a router arranged to direct into each FIFO data items addressed to a memory associated with the FIFO by the respective interleaver associated with the FIFO and arranged to direct into each memory only data items from FIFOs associated with the memory.