Patent ID: 8675386

Claim:
A memory device, comprising: a memory unit comprising a plurality of first conductive lines and a plurality of second conductive lines that cross the first conductive lines; and a driving unit module coupled with the plurality of the first conductive lines through respective ones of a plurality of contacts and coupled with the plurality of the second conductive lines through respective ones of the plurality of contacts, wherein the driving unit module comprises a plurality of transistors corresponding to the plurality of the first conductive lines and the plurality of the second conductive lines, respectively, and the plurality of the contacts are coupled with junction regions of the transistors, wherein the plurality of the contacts comprise plugs, and contact areas between the junction regions of the plurality of the transistors and the plugs are the same, wherein as cross points between the plurality of first conductive lines and the plurality of the second conductive lines become farther from the driving unit, a distance between the plurality of the contacts and gates of the plurality of the transistors is decreased.