Patent ID: 7800107

Claim:
An apparatus comprising: a semiconductor substrate; a plurality of first shallow trench isolation layers formed in a semiconductor substrate and defining a first active area, wherein the first active area includes a plurality of first active area portions formed between adjacent first shallow trench isolation layers; a plurality of second shallow trench isolation layers formed in the semiconductor substrate and defining a second active area which encloses the first active area; a gate electrode formed on the first active area; an interlayer insulating layer formed over and contacting the gate electrode; a plurality of first contact plugs formed on the second active area and extending through the interlayer insulating layer; a plurality of second contact plugs formed on the second active area and distal from the plurality of first contact plugs; a metal wiring layer electrically connected to the second active area via one of the plurality of first contact plugs; a first pad electrically connected to the gate electrode via one of the plurality of second contact plugs; and a second pad electrically connected to the metal wiring layer via another one of the plurality of second contact plugs.