Patent ID: 8122188

Claim:
A multi-port memory system comprising: a plurality of input buffers, each input buffer configured to receive command signals from a corresponding processor; a plurality of command decoders, each command decoder coupled to a corresponding input buffer and configured to decode a refresh command from the command signals received by the corresponding input buffer and output the refresh command; a shared memory bank; a refresh controller coupled to the command decoders and configured to receive the refresh commands output from the command decoders and selectively apply the refresh commands to the shared memory bank; and a comparator coupled to the refresh controller and the input buffers, and configured to compare the plurality of command signals with a setting to generate a comparison result, wherein the refresh controller is configured to selectively apply a refresh command to the shared memory bank in response to the comparison result, and wherein the comparator is further configured to, for each command signal, compare a chip select signal of the command signal with a mode register code to generate the comparison result.