Patent ID: 7020865

Claim:
A process of implementing a logic circuit for logical operations based on a function f N =x 1 OR( x 2 AND( x 3 OR( x 4 AND . . . x N . . . ))) or f′ N =x 1 AND( x 2 OR( x 3 AND( x 4 OR . . . x N . . . ))), comprising steps of: a) selecting N as the number of variables of the logic circuit; b) defining a top portion of the logic circuit based on a pre-selected pattern of first and second gate types, the top portion defining at least a top level of the logic circuit and having N inputs and ]N/3[ outputs; c) defining a lower portion of the logic circuit having the same number of inputs as the number of outputs of the top portion; d) defining the inputs of the lower portion as coupled to the outputs of the top portion; and e) implementing the logic circuit as the defined top and lower portions with two-input gates to a depth between 2n and 2n+2 where n is an integer and N is between 3 n and 3 n+1 .