Patent ID: 7906809

Claim:
A semiconductor device comprising: an isolation region selectively formed in a semiconductor substrate, a gate wiring structure selectively formed on the semiconductor substrate, the semiconductor substrate thereby having first and second surface portions defined by the isolation region and the gate wiring structure, each of the first and second surface portions including a plurality of side edges, at least one of the side edges being defined by the gate wiring structure and the remaining ones of the side edges being defined by the isolation region; and elevated source and drain regions formed respectively on the first and second surface portions, each of the elevated source and drain regions including a lower surface which is in contact with an associated one of the first and second surface portions with the same shape as the associated one of the first and second surface portions and an upper surface which is substantially the same as the lower surface and aligned with the lower surface, each of the elevated source and drain regions further including a side surface which protrudes from an associated one of the remaining ones of the side edges of a corresponding one of the first and second surface portions on a slant in a direction of the isolation region without substantially contacting with the isolation region, followed by slanting in an opposite direction to the isolation region to terminate the upper surface, wherein a cross-sectional area of each elevated source and drain region in any plane parallel to the substrate is greater than the area of the upper or lower surfaces thereof.