Patent ID: 7796460

Claim:
A nonvolatile semiconductor memory device comprising an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse, the antifuse including a semiconductor substrate of a first conduction type, a first semiconductor layer of a second conduction type formed in the surface of the semiconductor substrate, a first electrode provided on the first semiconductor layer to be given a first voltage, a second semiconductor layer of the second conduction type provided on the semiconductor substrate with the insulator interposed therebetween, a second electrode provided on the second semiconductor conduction layer to be given a second voltage different from the first voltage, a first device isolation region provided adjacent to the first semiconductor layer on the semiconductor substrate; and a third semiconductor layer of the first conduction type having a higher impurity concentration than the semiconductor substrate and formed in the surface of the semiconductor substrate as surrounded by the first device isolation region, and given a potential equal to that on the first electrode, the first electrode or the second electrode being formed of a metal silicide.