Patent ID: 8841759

Claim:
A semiconductor package comprising: a first semiconductor package comprising a first chip part on a first board, a first mold member covering the first chip part on the first board, a first wiring pattern at a lower surface of the first mold member, a first wire connecting the first wiring pattern to the first chip part, a first via hole through the first board, and a first plated layer comprising a first electrode pattern connected to the first wiring pattern of the first board on the first mold member; and a second semiconductor package comprising a second chip part on a second board, a second mold member covering the second chip part on the second board, a second wiring pattern at a lower surface of the second mold member, a second wire connecting the second wiring pattern to the second chip part, a second via hole through the second board, and a second plated layer comprising a second electrode pattern connected to the second wiring pattern of the second board on the second mold member; wherein the second semiconductor package is disposed on the first semiconductor package, wherein the first electrode pattern is disposed at an upper surface of the first mold member, wherein the first plated layer is disposed at the upper surface and a side surface of the first mold member, wherein the first mold member is formed by a molding method, wherein the first mold member covers the first wire, wherein the first wire is disposed in the first mold member, wherein the first plated layer is disposed at an outer surface of the first mold member, wherein the first plated layer is connected with the first wiring pattern which is connected with the first via hole, wherein a portion of an upper surface of the first plated layer is exposed to be connected with a second via hole of the second semiconductor package, wherein one end of the second via hole is directly connected with the first electrode pattern, and wherein another end of the second via hole is directly connected with one end of the second wiring pattern.