Patent ID: 7212483

Claim:
A modulation device for converting input data words of p bits into code words of q bits, concatenating adjacent ones of the code words with a merge bit sequence of r bits to form a code word sequence, and outputting the code word sequence, the modulation device comprising: a modulation means for converting the input data words of p bits into the code words of q bits while prefetching at least a current code word and a next code word; a merge bit inserting means for generating a plurality of code word sequences by temporarily concatenating the current code word and the next code word with each of a plurality of merge bit sequences of the r bits respectively to prepare a plurality of code word sequences without conforming to at least one of a minimum run-length (d+1)T and a maximum run-length (k+1)T which are set on the basis of a run-length limiting rule RLL(d, k); a DSV value calculation means for calculating the DSV value of each of the large number of code word sequences as generated by the merge bit inserting means; a comparing and selecting means for selecting one code word sequence having an absolute DSV value as calculated by the DSV value calculation means closest to zero among the large number of code word sequences; and a final code word sequence output means for outputting a final code word sequence finally determined by concatenating the current code word and the next code word with the merge bit sequence which is inserted between the current code word and the next code word of the one code word sequence as selected by the comparing and selecting means, wherein d is a minimum number of successive 0's occurring between adjacent logic 1's in the code words of q bits, k is a maximum number of successive 0's occurring between adjacent logic 1's in the code words of q bits, and T is a length of a channel bit.