Patent ID: 7384837

Claim:
In a dual gate CMOSFET device, a method for forming thin silicon germanium (SiGe) dislocation regions, the method comprising: forming a silicon substrate; forming a first layer of relaxed SiGe overlying the substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of relaxed SiGe, having a thickness of less than 5000 Å; forming a first layer of strained-Si overlying the first layer of relaxed SiGe; forming a second layer of strained-Si overlying the second layer of relaxed SiGe; forming an n-doped well (n-well) in the substrate and the overlying first layer of relaxed SiGe; and, forming a p-doped well (p-well) in the substrate and the overlying second layer of relaxed SiGe.