Patent ID: 7924617

Claim:
A method of operating a NAND architecture non-volatile memory device, comprising: applying a first voltage to two or more first word lines coupled to one or more first strings of memory cells, wherein the two or more first word lines comprise two or more adjacent word lines; applying a second voltage to remaining word lines coupled to the one or more first strings of memory cells, wherein the second voltage is less than the first voltage; applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells; and applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage; wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.