Patent ID: 7276405

Claim:
A method of forming a power semiconductor device, comprising: forming a first drift region of a first conductivity type over a semiconductor substrate, the first drift region having a lower impurity concentration than the semiconductor substrate; forming a second drift region of a the first conductivity type over the first drift region, the second drift region having a higher impurity concentration than the first drift region; forming a plurality of stripe-shaped body regions of a second conductivity type in an upper portion of the second drift region; forming a third region of the first conductivity type in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region; and forming a gate electrode which laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each third region, wherein adjacent stripes of body regions are spaced apart from one another by a predetermined distance such that when a reverse bias is applied across the junction formed between each body region and the second drift region a resulting depletion region has a substantially flat boundary in the second drift region.