Patent ID: 8008935

Claim:
A tester for testing an integrated circuit, the tester comprises: a signal generator, adapted to: (a) provide a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad; (b) provide a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad; and a processor, adapted to compare between a first test result and a second test result, wherein the first test result represents a first state of the first memory element sampled a predefined period after a first provision of the first signal and the second test result represents a second state of the second memory element sampled the predefined period after a second provision of the second signal; wherein the tester is adapted to alter the predefined period, and to repeat the first provision of the first signal and the second provision second signal and the comparison of the first test result to the second test result such as to detect a time difference between a first path propagation period and a second path propagation period.