Patent ID: 8212908

Claim:
A timing signal generator that generates a timing signal in synchronization with a predetermined cycle based on a reference clock, the timing signal generator comprising: a signal dividing unit that divides the predetermined cycle into a plurality of partial periods, thereby generating a divided signal, wherein an output level can be set with respect to each partial period, the timing signal generator further comprising: a phase shifting unit that generates a phase-shifted signal having a phase shifted from the divided signal when the partial period is shifted accompanying a change between a first state in which a timing clock is output and a second state in which the timing clock is not output; and a selecting unit that selects one of the divided signal and the phase-shifted signal according to the phase of the timing clock, wherein the partial period is shifted based on the signal selected by the selecting unit, wherein: the signal dividing unit counts one of multi-layer clocks generated by a delay locked loop dividing a clock with the predetermined cycle up to a predetermined number to generate the divided signal, and the phase shifting unit generates the phase-shifted signal based on another multi-layer clock that is not counted by the signal dividing unit.