Patent ID: 8902145

Claim:
A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the second transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor, wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor, wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor, wherein a gate of the eighth transistor is directly connected to the gate of the first transistor, wherein the other of the source and the drain of the second transistor is directly connected to one of a plurality of wirings, wherein the other of the source and the drain of the fourth transistor is directly connected to the one of the plurality of wirings, wherein the other of the source and the drain of the sixth transistor is directly connected to the one of the plurality of wirings, wherein the other of the source and the drain of the seventh transistor is directly connected to the one of the plurality of wirings, wherein the other of the source and the drain of the eighth transistor is directly connected to the one of the plurality of wirings, wherein the other of the source and the drain of the first transistor is electrically connected to another one of the plurality of wirings, wherein the other of the source and the drain of the fifth transistor is directly connected to an additional one of the plurality of wirings, wherein a gate of the third transistor is electrically connected to the another one of the plurality of wirings, wherein a clock signal is input to the gate of the second transistor, and wherein the clock signal is input to the gate of the fourth transistor.