Patent ID: 7889550

Claim:
A control driver for non-volatile memory, the control driver comprising: a first driving circuit comprising: a first pull-up transistor for pulling up a first control line signal according to a first pull-up signal, the first pull-up transistor comprising: a first terminal for pulling the first control line signal up to approximately a first control line voltage; a second terminal for receiving the first control line voltage; and a control terminal for receiving the first pull-up signal, and turning on the first pull-up transistor when voltage of the first pull-up signal is less than voltage of the first control line voltage; a first pull-down transistor for pulling down the first control line signal according to the first pull-up signal, the first pull-down transistor comprising: a first terminal coupled to the first terminal of the first pull-up transistor for pulling the first control line signal to approximately a low power supply voltage; a second terminal for receiving the low power supply voltage; and a control terminal for receiving the first pull-up signal, and turning on the first pull-down transistor when voltage of the first pull-up signal is greater than the low power supply voltage; a first level shift up circuit having an output terminal directly coupled to the control terminal of the first pull-up transistor and the control terminal of the first pull-down transistor for outputting the first pull-up signal, the first level shift up circuit receiving a first select signal, outputting the first pull-up signal at a first voltage when the first select signal is asserted, and outputting the first pull-up signal at a second voltage when the first select signal is not asserted; and a first select circuit coupled to the first level shift up circuit for outputting the first select signal, the first select circuit receiving a plurality of first decoding signals, asserting the first select signal when all of the first decoding signals are asserted, and not asserting the first select signal when any of the first decoding signals is not asserted.