Patent ID: 7595625

Claim:
A current mirror, comprising: a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively; and a base current compensation block inserted between the input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference, comprising: a bias current generator of a bias current and a first compensation transistor inserted, in series with each other, between the voltage reference and the input terminal; and a second compensation transistor inserted between the voltage reference and the common control terminals of the first and second mirror transistors and having a control terminal connected to a control terminal of the first compensation transistor; wherein the base current compensation block further comprises: a third compensation transistor inserted between the voltage reference and common control terminals of the first and second compensation transistors, and having a control terminal connected between the bias current generator and the first compensation transistor.