Patent ID: 7117381

Claim:
A data transmission circuit comprising: a control signal generation circuit, which receives a strobe signal and a clock signal, which generates a write control signal that is activated in response to the strobe signal, and which generates a read control signal that is activated in response to a first rising or falling edge of the clock signal after the write control signal is activated; a write state machine which is activated in response to the write control signal, which internally synchronizes with the strobe signal, and which sequentially outputs a plurality of input control signals; a conversion circuit which latches serial input data at a timing of the input control signals to converts the input serial data into parallel latched data; a read state machine which is activated in response to the read control signal, which internally synchronizes with the clock signal, and which sequentially outputs a plurality of output control signals; and a selection circuit which selects the parallel latched data in response to the output control signals, and which outputs the selected data as serial output data which has the same data order as the serial input data.