Patent ID: 6954398

Claim:
A semiconductor memory device comprising: subword drivers (SWDs), each of which has a plurality of subword driver circuits commonly connected to a main word line and also connected to different subword selection lines to drive respective subword lines, each of the SWDs being connected to driver input terminals and the subword lines; and a common inverter circuit having an inverter input terminal and an inverter output terminal, the inverter input terminal being connected to the main word line and the inverter output terminal being connected to the plurality of driver input terminals, wherein each of the subword driver circuits includes an internal inverter circuit that is connected to an inverter output terminal connected to the main word line and the subword selection lines and has its output terminal connected to the subword lines, and a drive transistor connected to the subword selection lines, the inverter output terminal and the output terminal of the internal inverter circuit, and each of the subword drive circuits is driven by a subword selection signal received through one of the subword selection lines.