Patent ID: 8018003

Claim:
A field effect transistor (FET) formed in a substrate, the FET comprising: a channel region; a first insulating layer; a second insulating layer; a source region having a first sidewall in direct contact with the channel region, the source region being electrically isolated from the substrate by the first insulating layer, the first insulating layer surrounding the source region except along the first sidewall, wherein the first sidewall extends to a depth defined by a bottom of the source region, wherein the first insulating layer is a single layer; a drain region having a second sidewall in direct contact with the channel region, the drain region being electrically isolated from the substrate by the second insulating layer, the second insulating layer surrounding the drain region except along the second sidewall, wherein the second sidewall extends to a depth defined by a bottom of the drain region, wherein the second insulating layer is a single layer; a dielectric layer overlying the channel region; and a gate overlying the dielectric layer, wherein edges of the gate and the dielectric layer are aligned in a straight line with channel-side edges of the first and second insulating layers as well as the first and second sidewalls.