Patent ID: 7971029

Claim:
A barrier synchronization method for causing a plurality of processors to execute a parallel processing, comprising: when a processor of the plurality of processors completes a process to be executed in the parallel processing, inverting a value of a barrier state register corresponding to the processor, wherein each of the plurality of processors corresponds to one of a plurality of the barrier status registers, each of the plurality of the barrier status registers storing one-bit data indicating an execution status of a process executed by a corresponding processor, and barrier synchronization of the plurality of processors is executed by a plurality of barrier blades, and each one of the plurality of barrier blades includes a barrier mask register having a plurality of bits, each bit of barrier mask register corresponding to one of the plurality of processors and indicating whether or not a corresponding processor is included in a synchronization group in which a set of processors execute the parallel processing together, and a Last Barrier Synchronization register (LBSY); and inverting a value of the LBSY when values of barrier status registers, in a same synchronization group indicated by the barrier mask register, become same.