Patent ID: 7807526

Claim:
A method of forming a non-volatile random access memory cell comprising: forming a plurality of trench structures into an array region of a semiconductor substrate, wherein each of the trench structure has a depth from about 1 to about 2 μm; forming a source diffusion beneath each trench structure and forming a vertical select channel along sidewalls of each trench structure; forming a select transistor within each trench structure; providing a trench isolation region between selected trench structures, wherein the trench isolation region isolates a first select transistor in a first trench structure of the plurality of trench structures from a second select transistor in an adjacent trench structure of the plurality of trench structures, wherein the trench isolation region is present overlying a portion of a gate conductor of at least one of the first and second select transistor, and extends from a sidewall of the first trench structure through the semiconductor substrate to a sidewall of the adjacent trench structure; and forming a memory transistor including an oxide/nitride/oxide gate dielectric on a surface of said semiconductor substrate, said memory transistor is located adjoining said selected trench structures, in which a memory state is represented by a charge stored in the oxide/nitride/oxide gate dielectric, wherein a drain diffusion of the memory transistor is formed extending from an upper surface of the substrate between a gate structure of the memory transistor and a sidewall of the plurality of the trench structures, in which the drain diffusion of the memory transistor provides the drain diffusion of the select transistor.