Patent ID: 8537299

Claim:
An array substrate, comprising a plurality of pixel units defined by interacting of a plurality of gate lines along a row direction and a plurality of data lines along a column direction, and a pixel electrode formed within each of the pixel units, wherein each row of the pixel units are provided with a first gate line and a second gate line in the gate lines, and each of the pixel units is provided with a first thin film transistor and a second thin film transistor; the first thin film transistor is connected with the first gate line, and the second thin film transistor is connected with the second gate line; the first thin film transistor is connected with the data line at one side of the pixel unit, and the second thin film transistor is connected with the data line at the other side of the pixel unit, and the second thin film transistors of the pixel units in one row and the first thin film transistors of the pixel units in an adjacent row within the same columns are connected to the same column of the data lines, wherein a gate driver is connected to the first gate line and the second gate line through a control device and controls the first gate line and the second gate line for each pixel unit to alternately turn on with a period of one frame by a control signal, wherein the control device comprises: a first control thin film transistor; and a second control thin film transistor, wherein source electrodes of the first control thin film transistor and the second control thin film transistor are connected to the gate driver through a periphery gate line; a gate electrode of the first control thin film transistor is connected with a first control signal line, and a gate electrode of the second control thin film transistor is connected with a second control signal line; a drain electrode of the first control thin film transistor is connected with the first gate line and a drain electrode of the second control thin film transistor is connected with the second gate line, wherein the first control signal line and the second control signal line are connected with a timing controller, and the timing controller provides control signals with the first control signal line and the second control signal line with the period of one frame.