Patent ID: 7734944

Claim:
A method for launching two bits of data from a chip on to one bus terminal at double the rate of the rate of and on-chip clock, including the steps of: storing an even bit in an even bit master/slave register in response to a master m 1 /slave s 1 clock signal operating at the on-chip clock rate; storing and odd bit in an odd bit master/slave register in response to the master m 1 /slave s 1 clock signal; coupling an output of the even bit master/slave register as one input to a multiplexer whose output is coupled to said one bus terminal; coupling an output of the odd bit master/slave register as an input to a master register that stores the input in response to a master m 2 clock signal, and whose output is coupled as another input to said multiplexer, said master register delaying the output of the odd bit master/slave register for an interval determined by the master m 2 clock signal; coupling a select signal operating at said on-chip clock rate to said multiplexer to launch onto said bus terminal an even bit on one have cycle of said select signal and an odd bit on the other half cycle; delaying said select signal with respect to the master m 1 /slave s 1 clock signal and the master m 2 clock signal with a delay element whose delay interval is programmable to match the signal set-up interval required by the inputs to said multiplexer; and determining the delay interval by comparing an edge of the select input to the multiplexer with an edge of a data bit on said bus terminal.