Patent ID: 8482329

Claim:
An integrated circuit having a core and an input receiver for downconverting an external voltage (e.g., 104 ) having a voltage level of an input/output (I/O) supply VDDIO in a high-voltage VDDIO voltage domain into a downconverted voltage (e.g., 116 ) having a voltage level of a core supply VDD in a low-voltage VDD voltage domain, wherein the VDDIO voltage level of the external voltage is greater than the VDD voltage level of the downconverted voltage, wherein the input receiver comprises: a hysteresis comparator (e.g., 102 ) configured to receive and compare the external voltage to a reference voltage (e.g., 106 ) and generate, with hysteresis, an intermediate voltage based on the comparison of the external voltage to the reference voltage; voltage-conversion circuitry (e.g., 108 / 114 ) configured to convert the intermediate voltage from the high-voltage VDDIO voltage domain into the low-voltage VDD voltage domain of the downconverted voltage; and a stress protection module (e.g., 110 ) configured between the I/O supply VDDIO and a supply node of the hysteresis comparator, wherein: the hysteresis comparator comprises a plurality of low voltage transistors that cannot operate reliably at the VDDIO voltage level; and the stress protection module enables the hysteresis comparator to operate properly in the high-voltage VDDIO voltage domain.