Patent ID: 6985399

Claim:
A main word line driver circuit of a semiconductor memory device, the circuit generating main word line signals enabling a plurality of main word lines, respectively, comprising: a voltage supply unit which supplies a first voltage to a first node during a first time interval and then supplies a second voltage higher than the first voltage to the first node for a second time interval later than the first time interval; and a plurality of output units connected to the first node which receive the first voltage and the second voltage supplied to the first node, each of the output units receiving a precharge signal and a respective decoded row address signal and comprising a second node inverted by an inverter to generate a respective main word line signal output by the output unit, the second node being connected to the first node through a transistor in response to the respective decoded row address signal such that the second node receives through the transistor the first and second voltages generated by the voltage supply unit in response to the respective decoded row address signal, each output unit, in response to the precharge signal and the respective decoded row address signal and the first and second voltages, generating the respective main word line signal.