Patent ID: 6864729

Claim:
A method of switching the mode of a PLL circuit, wherein the PLL circuit includes a phase comparator for comparing the phase of a reference frequency-divided signal and the phase of a comparison frequency-divided signal with each other and generating a comparison output signal, a charge pump for generating a current depending on the comparison output signal from the phase comparator, a voltage-controlled oscillator for generating an output signal having a predetermined frequency in accordance with the current generated by the charge pump, a lock detecting circuit for detecting a locked state of the PLL circuit in accordance with the comparison output signal from the phase comparator and generating a lock detecting signal when the locked state is detected, and a shift register for generating a frequency-dividing ratio setting signal for changing a frequency-dividing ratio used to generate at least one of the reference frequency-divided signal and the comparison frequency-divided signal, and wherein the PLL circuit has a first mode for locking an output signal thereof up to a desired frequency at a high speed and a second mode in normal use, the method comprising the steps of: detecting a high impedance state of the charge pump; controlling the lock detecting signal using the frequency-dividing ratio setting signal to generate a mode switching signal in accordance with the controlled lock detecting signal; and switching the mode of the PLL circuit from the first mode to the second mode or from the second mode to the first mode in response to the mode switching signal when the high impedance state is detected.