Patent ID: 8355269

Claim:
A composite memory bit cell suitable for use in integrated circuits that utilize pushed layout rules comprising: two foundry-supplied bit-cell layouts for two six-transistor SRAM bit cells, said foundry-supplied bit-cell layouts utilizing pushed layout rules, and two foundry-supplied edge-cell layouts compatible with the layouts for said SRAM bit-cell layouts, and minor bit-cell layout modifications and minor edge-cell layout modifications to enable functionality as data storage bits, mask bits and as compare transistors, and interconnections between said two foundry-supplied bit-cell layouts and said two modified foundry-supplied edge-cell layouts to constitute the functionality of a Ternary Content Addressable Memory bit cell such that the first of said six-transistor SRAM bit cells stores the data bit, while the second of said six transistor SRAM bit cells stores the mask bit and the transistors in said modified edge-cell layouts comprise the compare function of the Ternary Content Addressable Memory, and whereby said composite layout of said composite bit cell provides enhanced functionality with a layout that is optimized for area and performance by virtue of maintaining the salient layout features of the original foundry-supplied bit-cell and edge-cell layouts.