Patent ID: 7502725

Claim:
A method for simulating and verifying an address generation interlock (AGI) resolution function and an early AGI resolution function, the method comprising: receiving an AGI instruction from an instruction unit decode pipeline; determining if the instruction is an address generation interlock (AGI) type of instruction or an early AGI type of instruction; if the instruction is an AGI type of instruction, then: executing an AGI resolution function in a simulation environment to generate an address for the instruction based on the instruction and a pool of registers, the pool of registers controlled by a register manager using random and sequential register management techniques; if the instruction is an early AGI type instruction, then: executing an early AGI resolution function in a simulation environment to generate an address for the instruction based on the pool of registers and the instruction; and outputting the address to the instruction unit decode pipeline for use in further processing of the instruction; thereby utilizing the simulation environment to simulate and verify operation of the AGI resolution function and the early AGI resolution function.