Patent ID: 8014482

Claim:
A signal receiving circuit, comprising: a sampler, for receiving an analog signal and for sampling the analog signal to generate a sampling signal according to a sampling clock; an ADC, coupled to the sampler, for transferring the sampling signal to a digital signal; an equalizer, coupled to the ADC, for equalizing the digital signal to generate an equalized digital signal; a quantizer, coupled to the equalizer, for quantizing the equalized digital signal to generate a processed digital signal; and a timing recovery circuit, directly coupled to an output terminal of the sampler and coupled to the equalizer, for adjusting timing of the sampling clock according to the processed digital signal and the digital signal, wherein the timing recovery circuit includes a timing recovery parameter generating circuit and a loop filter, and the timing recovery parameter generating circuit comprises: a computing circuit, coupled to the equalizer and the quantizer, for receiving the processed digital signal and the digital signal, and for computing an initial timing recovery parameter according to the processed digital signal and the digital signal; a candidate value generating circuit, for providing a plurality of candidate values; and a multiplexer, coupled between the computing circuit and the candidate value generating circuit, for selecting one of the candidate values as an adjusting value according to a selecting signal; wherein the computing circuit further adjusts timing of the sampling clock according to the adjusting value, wherein the candidate values respectively correspond to different transmitting lengths of the analog signal.