Patent ID: 8359479

Claim:
A cryptoengine configured for providing countermeasures against attacks, said cryptoengine comprising: an input/output (I/O) control unit; a memory, the memory configured for being communicatively coupled with the I/O control unit and further configured for receiving an input from the I/O control unit and for providing an output to the I/O control unit in response to said input; a controller, the controller configured for being communicatively coupled with the I/O control unit for transmitting and receiving control signals; and an Arithmetic Logic Unit (ALU) including a plurality of storage components and a plurality of computational components, the plurality of storage components including status bit registers which are flip-flop circuits configured for holding bits of a state of the ALU, at least one of the flip-flop circuits being driven only by a set-to-zero signal and a save-output-from-comparator signal for providing protection against attacks, the ALU configured for being communicatively coupled with the controller, the ALU further configured for receiving commands from the controller and for providing at least one of status bits and flags to the controller, the ALU further configured for being communicatively coupled with the memory, the ALU further configured for providing output signals to the memory and for receiving input signals from the memory, wherein the cryptoengine is configured for being communicatively coupled with a host computing device, and wherein the cryptoengine is configured for embedding hardware support for promoting protection against said attacks, said attacks including at least one of: timing analysis attacks, power analysis attacks, side channel attacks, and internal signal observation attacks.