Patent ID: 6893899

Claim:
A method of creating a stack of integrated circuits selectively connected to provide increased memory density in an application, the method comprising the steps of: providing a carrier frame configured to have a plurality of members emergent into a window within the carrier frame; applying a first portion of a solder-containing compound to the first side of the plurality of members; placing a first packaged integrated circuit having external leads extending away from the packaged integrated circuit in contact with the plurality of members; processing the first integrated circuit and the carrier frame with a heat source to create a first set of solder connections between the plurality of members and a plurality of the external, extending away, leads of the first packaged integrated circuit; applying a second portion of a solder-containing compound to the second side of the plurality of members of the carrier frame; placing a second packaged integrated circuit having external leads extending away from the second packaged integrated circuit in contact with the plurality of members; and processing the second integrated circuit and the carrier frame with a heat source to create a second set of solder connections between the plurality of members and a plurality of the external, extending away, leads of the second integrated circuit.