Patent ID: 7323362

Claim:
A method for stress-reduced assembly of a semiconductor device, including a chip having at least one contact pad and a substrate having at least one terminal pad, comprising the steps of: positioning said substrate on a pallet; attaching a reflow element to said chip contqact pad; flipping said chip onto said substrate so that said reflow element is placed in contact with said substrate terminal pad; moving said pallet into a first workstation, including means for performing reflow operations; supplying thermal energy to said chip and said substrate sufficient to reflow said element, thereby creating an assembly of chip and substrate spaced apart by a gap; transferring said pallet including said assembly from said first workstation into a first chamber maintained at a constant first temperature, and positioning said pallet in a waiting line for a first period of time; withdrawing said pallet from said waiting line and moving said pallet into a second workstation including means for performing underfill operations; filling said gap with a polymer precursor; transferring said pallet including said filled assembly from said second workstation into a second chamber maintained at a constant second temperature sufficient to polymerize said precursor, and positioning said pallet in waiting line for a second period of time; completely polymerizing said precursor; and withdrawing said pallet from said waiting line and cooling the completed assembly to ambient temperature.