Patent ID: 7023728

Claim:
Semiconductor memory system comprising: a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively, a plurality of conduction lines which can be selectively connected to the plurality of column lines and including a first and a second conduction line which can be connected to said first and second column lines, generating means provided with a plurality of output lines including at least a first and a second output line to make available a first and a second reading/writing voltage respectively to be supplied to said first and second terminal, groups of selection transistors which can be activated/deactivated to/from conduction by means of command lines to selectively connect the plurality of output lines to the plurality of conduction lines, wherein each group of transistors comprises at least a first and a second transistor connected to the same command line, said first and second transistors having corresponding operative terminals connected directly to the first and to the second output lines respectively, and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.