Patent ID: 7518173

Claim:
A semiconductor device comprising: a semiconductor substrate; a MOS transistor formed in said semiconductor substrate and having an insulated gate and source/drain regions on both sides of said insulated gate; a ferroelectric capacitor formed over said semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed over said upper electrode and having a thickness of half of or thinner than a half of a thickness of said upper electrode; an alumina film covering said ferroelectric capacitor; an interlayer insulating film formed directly on said alumina film; a contact hole formed through said interlayer insulating film, exposing said metal film; a conductive glue film covering an inner surface of said contact hole, consisting of TiAlN; and a conductive plug burying said contact hole; wherein said metal film is a Pt film and said upper electrode has a thickness of 200 nm to 300 nm.