Patent ID: 8830741

Claim:
A phase-change memory, comprising: multiple phase-change memory cells, each having a higher or lower resistance; multiple data bitlines, each connected to be shunted by a selected one of said cells, and at least one reference bitline, connected to be shunted by a reference current; wherein said reference current discharges said reference bitline with a time constant which is slower than the time constant of said lower resistance in discharging said data bitlines; multiple sense amplifiers, each connected to at least a respective one of said bitlines, and each configured to output a logic transition when the voltage of the bitline passes a fixed threshold voltage; and latching circuits operatively connected to receive respective outputs of said sense amplifiers; wherein a respective one of said sense amplifiers is connected to said reference bitline, and provides a clock output which is connected to activate said latching circuits; whereby sensing occurs without requiring said sense amplifiers to reach a stable state.