Patent ID: 8489966

Claim:
A method for predicting failure of a solid-state mass storage device having a controller and at least one nonvolatile memory device comprising pages that are organized into memory blocks, the method comprising: assigning at least a first of the memory blocks as wear indicator means and excluding the wear indicator means from use as data storage for the nonvolatile memory device; using at least a set of the memory blocks of the nonvolatile memory device for data storage whereby data are written to and erased from each memory block of the set of memory blocks in program/erase (P/E) cycles; collecting information regarding the number of P/E cycles encountered by the memory blocks of the set of memory blocks and accessing the information to perform wear leveling on the set of memory blocks; subjecting the wear indicator means to P/E cycles so that the wear indicator means is subjected to a number of P/E cycles that is greater than the number of P/E cycles encountered by the memory blocks of the set of memory blocks; performing integrity checks of the wear indicator means and monitoring a bit error rate thereof; and taking corrective action if the bit error rate of the wear indicator means increases.