Patent ID: 7675134

Claim:
A temperature compensated voltage reference fabricated on an integrated circuit die, comprising: a first P-channel metal oxide semiconductor (P-MOS) transistor having an N-type polysilicon gate, wherein the N-type polysilicon gate causes the first P-MOS transistor to have a first threshold voltage; the first P-MOS transistor having a first width; a second P-MOS transistor having a P-type polysilicon gate, wherein the P-type polysilicon gate causes the second P-MOS transistor to have a second threshold voltage; the second P-MOS transistor having a second width, wherein the first and second widths are selected for optimal temperature compensation; the first and second P-MOS transistors are configured as a differential pair of an operational amplifier; and the operational amplifier has an output voltage substantially equal to a difference between the first and the second threshold voltages, wherein the first and second widths of the first and second P-MOS transistors are selected to compensate for a variation in the output voltage over a temperature range.