Patent ID: 7075830

Claim:
A method for programming a single-bit storage SONOS memory cell, wherein said single-bit storage SONOS memory cell comprises a channel region between a left bit line and a right bit line, a composite dielectric layer for storing digital data, and a word line overlying said composite dielectric layer, the method comprising: performing a left side electron injection on said single-bit storage SONOS memory cell by applying a relatively high word line voltage (V WL, HIGH ) to said word line, applying a relatively high left bit line voltage (V LBL, HIGH ) to said left bit line, and applying a relatively low right bit line voltage (V RBL, LOW ) to said right bit line; and performing a right side electron injection on said single-bit storage SONOS memory cell by applying said relatively high word line voltage (V WL, HIGH ) to said word line, applying a relatively low left bit line voltage (V LBL, LOW ) to said left bit line, and applying a relatively high right bit line voltage (V RBL, HIGH ) to said right bit line.