Patent ID: 7870328

Claim:
A memory controller that accesses a flash memory having multi planes each of which has physical blocks, a multi-plane write function for writing data into associated physical blocks of the multi planes simultaneously, and a plane-by-plane write function for writing data into a physical block, comprising: first search means for detecting the associated physical blocks all of which are free physical blocks and non of which is in a defect state; second search means for detecting physical blocks each of which is a free physical block and belongs to the associated physical blocks including at least one physical block being in the defect state; write means for performing both plane-by-plane write in which the write means writes data into a physical block and multi-plane write in which the write means writes data into the associated physical blocks of multi planes simultaneously; and discrimination means for discriminating which one of a set of associated physical blocks is subjectable to the plane-by-plane write when the set of the associated physical blocks to which the multi-plane write is disabled occurs, wherein when the associated physical blocks are detected by the first search means, the write means performs the multi-plane write to the detected associated physical blocks, when the associated physical blocks are not detected by the first search means, the write means performs the plane-by-plane write to the physical blocks detected by the second search means, the second search means has a non-set good block table having a list of physical block addresses of free physical blocks to which the multi-plane write is disabled but the plane-by-plane write is enabled, and when a set of physical blocks to which the multi-plane write is disabled occurs, the discrimination means writes a physical block address of any physical block which is discriminated as being subjectable to the plane-by-plane write into the non-set good block table.