Patent ID: 8723268

Claim:
A method for manufacturing a functional cell library, comprising: specifying a base structure comprising: a first set of semiconductor fins aligned on a first axis, one or more of the semiconductor fins in the first set including room for at least one channel region and at least two source/drain regions of finFETs; a second set of semiconductor fins aligned on the first axis, one or more of the semiconductor fins in the second set including room for at least one channel region and at least two source/drain regions of finFETs; specifying a functional cell using the base structure, the cell comprising elements of: a patterned gate conductor layer including a plurality of gate elements on corresponding fins in the first and second sets of semiconductor fins, the gate elements being disposed over channel regions of the corresponding semiconductor fins; at least one patterned conductor layer overlying the patterned gate conductor layer; and a plurality of interlayer connectors, including interlayer connectors aligned over semiconductor fins in the first and second sets and connected to the gate elements of particular finFETs on the corresponding fins; and storing machine readable specifications of the cell in a cell library that is stored in a non-transitory computer readable medium.