Patent ID: 8158508

Claim:
A chip package comprising: a substrate comprising a solder mask, a first contact point in a channel in said solder mask, a second contact point in said channel, wherein said first contact point is separate from said second contact point in said channel, wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, and an interconnect covered by said solder mask; a semiconductor device comprising a polymer layer at a top of said semiconductor device and a metal pad having a third contact point at a bottom of an opening in said polymer layer; a copper pillar between said third contact point and said substrate, wherein said copper pillar is connected to said third contact point through said opening, wherein said copper pillar has a thickness between 10 and 100 micrometers; a solder between said copper pillar and said substrate, wherein said solder is connected to said copper pillar, wherein said solder electrically contacts said first contact point; and an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill.