Patent ID: 7420534

Claim:
A display apparatus comprising: a pixel array unit including a plurality of gate lines, a plurality of signal lines, and pixels arranged in a form of a matrix at intersections of the gate lines and the signal lines; a vertical driving circuit for sequentially selecting the pixels via the gate lines; and a horizontal driving circuit for writing a video signal to the selected pixels via the signal lines, said pixel array unit, said vertical driving circuit, and said horizontal driving circuit being disposed on an identical substrate; wherein said vertical driving circuit includes: a shift register having a multistage-connected structure with one stage corresponding to at least two gate lines, for sequentially outputting a shift pulse from each stage; an intermediate gate circuit unit corresponding to each stage of the shift register, for processing a shift pulse of one stage and a shift pulse of a preceding stage and thereby generating a temporally separate intermediate pulse in each stage; and an output gate circuit unit corresponding to each stage of the intermediate gate circuit unit, and operating in response to an externally supplied clock pulse for processing the intermediate pulse outputted from each stage of the intermediate gate circuit unit and thereby sequentially outputting a drive pulse to two corresponding gate lines to sequentially select pixels; wherein said shift register includes a dummy additional stage disposed in front of the first stage thereof, and a shift pulse outputted from the additional stage is supplied to a first stage of the intermediate gate circuit unit which stage corresponds to the first stage of the shift register; wherein the shift register is driven by an externally supplied clock pulse having substantially the same frequency as the externally supplied clock pulse supplied to the output gate circuit unit; and wherein the externally supplied clock pulse supplied to the shift register is shifted 90° from the externally supplied clock pulse supplied to the output gate circuit unit.