Patent ID: 8076715

Claim:
A semiconductor memory device, comprising: a first dual-bit memory cell comprising a first shared bit line in a substrate and a second shared bit line in the substrate; a second dual-bit memory cell adjacent to the first dual-bit memory cell, the second dual-bit memory cell comprising the second shared bit line, wherein the second shared bit line is disposed between the first and second dual-bit memory cells, wherein the second shared bit line comprises: an epitaxial polysilicon region disposed in the substrate, a first implanted portion underlying a first memory cell ONO stack, and a second implanted portion underlying a second memory cell ONO stack and being spaced apart from the first implanted portion by the epitaxial polysilicon region, wherein the epitaxial polysilicon region has a depth into the substrate greater than the depth of the first and second implanted portions; and an insulator region disposed only within the substrate directly beneath and in contact with the epitaxial polysilicon region, and extending into the substrate to a depth sufficient to prevent electrons from flowing between the first dual-bit memory cell and the second dual-bit memory cell, wherein the whole insulator region is entirely beneath a greatest depth into the substrate of the epitaxial polysilicon region.