Patent ID: 6974987

Claim:
A semiconductor device comprising a DRAM memory cell including a memory cell transistor and a capacitor in a semiconductor layer, wherein: the memory cell transistor comprises: a gate dielectric provided on the semiconductor layer; a gate electrode provided on the gate dielectric; a source diffusion layer and a drain diffusion layer provided to either side of the gate electrode in the semiconductor layer; and a first sidewall covering the sides of the gate electrode, the capacitor comprises: a plate electrode including a lower part with which a capacitor trench formed by entrenching the semiconductor layer is filled and an upper part opposed to the gate electrode; a capacitance dielectric formed along the wall surfaces of the capacitor trench below the plate electrode and interposed between the lower part of the plate electrode and the semiconductor layer; and a second sidewall covering the sides of the upper part of the plate electrode, the first sidewall is formed of a dielectric in common with the second sidewall, and the whole source diffusion layer is covered with the first and second sidewalls.