Patent ID: 7236416

Claim:
A memory system, comprising: a memory configured to operate in a self-refresh mode and an auto-refresh mode, the memory having a plurality of memory locations; and a memory controller configured to access a first one of the memory locations while a second one of the memory locations is being refreshed in the auto-refresh mode, wherein the memory comprises a plurality of memory banks, the first one of the memory locations being located in a first one of the memory banks and the second one of the memory locations being located in a second one of the memory banks, wherein the memory further comprises a refresh address register configured to sequence through a plurality of memory addresses in the self-refresh mode, each of the memory addresses corresponding to one of the memory locations to be refreshed in the self-refreshed mode, and wherein the memory controller has access to the refresh address register, wherein the memory further comprises a readable register coupled to the refresh address register, the memory controller having access to the refresh address register through the readable register.