Patent ID: 7565591

Claim:
A circuit testing system, for testing a circuit under test with logic circuits and a scan chain comprising flip-flop cells with inputs and outputs operationally connected to the logic circuits, the circuit under test including a plurality of clock domains, each containing a respective part of the flip-flop cells that are clocked by a respective domain clock signal, the circuit testing system comprising: a test controller arranged to switch the circuit under test to a test mode wherein the test controller supplies successive test input patterns through the scan chain, each test input pattern being associated with a respective combination of domain clock signals that are selectively enabled to capture a response of the logic circuits to the test input pattern into flip-flop cells of the scan chain, the test controller using the captured response from at least part of the flip-flop cells to detect faults in the circuit under test; a test pattern selector arranged to select a set of test input patterns and the associated combinations of domain clock signals for use by the test controller, wherein a particular test pattern in the selected set has the properties that, when the particular test pattern is applied by the test controller: the response to the particular test pattern captured by a timing sensitive flip-flop cell in a first clock domain is indicative of a fault condition, the timing sensitive flip-flop cell receives data dependent on data from a source flip-flop cell that operates on a second clock domain different from the first clock domain, the combination of selectively enabled domain clock signals for the particular test pattern comprises the clocks of both the first and second domain, and the data value in the source flip-flop cell is identical to a response value captured by the source flip-flop cell for the particular test pattern.