Patent ID: 7323370

Claim:
A method of fabricating a transistor, comprising: (a) forming a gate dielectric layer on a top surface of a substrate, said substrate comprising a single-crystal silicon layer separated from a lower region of said substrate by a buried silicon dioxide layer, said buried silicon dioxide layer having a first dielectric constant, a top surface of said silicon layer being said top surface of said substrate; after (a), (b) forming a polysilicon gate electrode on said dielectric layer; after (b), (c) forming sidewall spacers on sidewalls of said gate electrode and over regions of said dielectric layer adjacent to said gate electrode; after (c), (d) forming source/drains in said silicon layer on opposite sides of said gate electrode, said source/drains extending into said silicon layer and abutting said buried silicon dioxide layer and separated by a body region of said silicon layer under said gate electrode, said body region abutting said buried oxide layer; and after (d), (e) implanting fluorine in said buried silicon dioxide layer to form a fluorinated region in said buried silicon dioxide layer where said buried silicon dioxide layer is not protected by said gate electrode and said sidewall spacers, said fluorinated region having a second dielectric constant less than said first dielectric constant, said source/drains abutting said fluorinated regions.