Patent ID: 7692989

Claim:
A memory, comprising: a first memory array; a first sense amplifier coupled to the first memory array that senses data from the first memory array; a second memory array; a second sense amplifier coupled to the second memory array that senses data from the second memory array; a verify data line coupled to a first output of the first sense amplifier and a first output of the second sense amplifier, wherein the verify data line comprises: a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output; and a second logic circuit having a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output; a program/erase controller coupled to the output of the second logic circuit; a global data line coupled to a second output of the first sense amplifier and a second output of the second sense amplifier; and a global sense amplifier coupled to the global data line.