Patent ID: 7987338

Claim:
A system, comprising: a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein the plurality of dynamically configurable communication elements are distinct from said plurality of processors; wherein, for each of the processors, the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements; wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of the plurality of said processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements; and wherein, for each of said dynamically configurable communication elements, the first memory is shared among a plurality of the processors.