Patent ID: 7002850

Claim:
A system for reducing over-erased memory cells, comprising: N sense amplifiers, N being an integer; at least one memory sector segmented by the N sense amplifiers into N erase retry units with one erase retry unit of the memory sector corresponding with one sense amplifier, the memory sector having a starting address and an ending address, at most K erase retry units can be erased concurrently during an erase process of an erase operation, K being an integer and being less than or equal to N; and at least N buffers for showing whether any of the N erase retry units of the memory sector are erased after the erase process of the erase operation, the N buffers corresponding with the N erase retry units and the N sense amplifiers with at least one buffer corresponding with one erase retry unit of the memory sector and one sense amplifier, the erase process of the erase operation being followed by a verification process of the erase operation, the erase operation including at least one erase process and at least one verification process.