Patent ID: 8222701

Claim:
A semiconductor device comprising: a silicon substrate having a first device region and a second device region; an n-channel MOS transistor that is formed at the first device region; and a p-channel MOS transistor that is formed at the second device region; wherein the n-channel MOS transistor includes a first gate electrode that is formed on the silicon substrate at the first device region via a first gate insulating film and is defined by a first sidewall face and a second sidewall face opposing each other; a first n-type diffusion region and a second n-type diffusion region respectively formed at outer sides of the first sidewall face and the second sidewall face of the first gate electrode within the silicon substrate; a first sidewall insulating film and a second sidewall insulating film respectively arranged on the first sidewall face and the second sidewall face of the first gate electrode; a third n-type diffusion region formed at an outer side of the first sidewall insulating film within the silicon substrate; and a fourth n-type diffusion region formed at an outer side of the second sidewall insulating film within the silicon substrate; wherein the p-channel MOS transistor includes a second gate electrode that is formed on the silicon substrate at the second device region via a second gate insulating film and is defined by a third sidewall face and a fourth sidewall face opposing each other; a first p-type diffusion region and a second p-type diffusion region respectively formed at outer sides of the third sidewall face and the fourth sidewall face of the second gate electrode within the silicon substrate; a third sidewall insulating film and a fourth sidewall insulating film respectively arranged on the third sidewall face and the fourth sidewall face of the second gate electrode; a first p-type epitaxial region that is formed at an outer side of the third sidewall insulating film on the silicon substrate and is arranged to be higher than the second gate electrode; and a second p-type epitaxial region that is formed at an outer side of the fourth sidewall insulating film on the silicon substrate and is arranged to be higher than the second gate electrode; and wherein a tensile stress film that stores tensile stress is continuously arranged on the silicon substrate to extend over the first device region and the second device region, the tensile stress film at the first device region being arranged to cover the third n-type diffusion region, the fourth n-type diffusion region, the first sidewall insulating film, and the second sidewall insulating film, and the tensile stress film at the second device region being arranged to cover the third sidewall insulating film, the fourth sidewall insulating film, the first p-type epitaxial region, and the second p-type epitaxial region.