Patent ID: 7723795

Claim:
A semiconductor memory device comprising: a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central area of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending laterally, fourth and fifth portions extending vertically downwardly at distal end portions of the third portion, and a sixth portion extending vertically downwardly at a central portion of the third portion; a first gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active region; a second gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active region; a third gate formed extending in a direction perpendicular to the first and second gates and overlapping of the fourth and fifth portions of the second active region; and a plurality of contacts formed at distal ends of the first portion of the first active region, at a distal end of the second portion of the first active region, at distal ends of the second active region where the fourth and fifth portions intersect the third portion, at a distal end of the sixth portion of the second active region, and in portions of the first gate and the second gate in the space between the first active region and the second active region.