Patent ID: 8518794

Claim:
A semiconductor device comprising: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall; a first insulation layer on the capping layer, a second insulation layer on the first insulation layer; and a third insulation layer spaced apart from the first insulation layer, with the second insulation layer therebetween, wherein the first void region includes a first void upper region on the first insulation layer and a first void lower region below the first insulation layer, wherein the gate electrode comprises a gate foot contacting the active layer and a gate head on the gate foot, and a width of the gate head is broader than a width of the gate foot, wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers, and wherein the second void region is defined by a space between the third insulation layer and the active layer, the second void region extends from the active layer to the third insulation layer without discontinuity, and the second void region has an upper end in contact with the third insulation layer and a lower end in contact with the active layer.