Patent ID: 7292076

Claim:
A circuit for pulling-down an output node comprising: an input node; a ground terminal; a first sub-circuit coupled to said input node, said ground terminal, and said output node, said first sub-circuit comprising: a first NMOS transistor having a first voltage threshold; and a second NMOS transistor in a compound configuration with said first NMOS transistor, wherein said second NMOS transistor has a second voltage threshold substantially equal to said first voltage threshold and said first sub-circuit provides a first current path from said ground terminal to said output node when said first and second NMOS transistors are ON; a second sub-circuit coupled to said input node, said ground terminal, and said output node, said second sub-circuit comprising: a third NMOS transistor having a third threshold voltage that is greater than said first and second voltage thresholds, wherein said second sub-circuit provides a second current path from said ground terminal to said output node when said third NMOS transistor is ON; and a fourth NMOS transistor, coupled to said third NMOS transistor in a compound configuration, having a fourth threshold voltage that is substantially similar to said third threshold voltage.