Patent ID: 7170131

Claim:
A non-volatile memory cell array of conductive floating gates formed on a semiconductor substrate surface with a gate dielectric layer therebetween, and including control gates positioned adjacent surfaces of the floating gates removed from the substrate surface with an inter-gate dielectric layer therebetween, said floating gates individually comprising a base with one side coupled to the substrate through the gate dielectric layer and a projection extending from an opposite side of the base that is thinner in a first direction than a dimension of the base in said first direction, and wherein the surfaces of the floating gates adjacent the control gates include opposing side surfaces of the projection in said first direction and a top surface of the base with the inter-gate dielectric layer therebetween, and, wherein the projections individually have a dimension in a second direction that is equal to that of their corresponding bases in the second direction, the second direction being orthogonal with the first direction across the substrate surface.