Patent ID: 8510635

Claim:
A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function, a number of the semiconductor chips being represented by M, the method comprising: applying a first read-write test operation to the semiconductor chips so that each of the semiconductor chips has a first read information and a first written information corresponding to the first read information, wherein the error checking and correcting function of each of the semiconductor chips is off, one bit of the first read information that is not in conformity with the corresponding bit of the first written information is recorded as a first failure bit, a first failure bit counting value of each of the semiconductor chips is obtained by counting the first failure bit, thereby obtaining a plurality of first failure bit counting values corresponding to the semiconductor chips; after performing the first read-write test operation, applying an aging test to the semiconductor chips; applying a second read-write test operation to the semiconductor chips after the aging test so that each of the semiconductor chips has a second first read information and a second written information corresponding to the second read information, wherein the error checking and correcting function of each of the semiconductor chips is still off, one bit of the second read information that is not in conformity with the corresponding bit of the second written information is recorded as a second failure bit, a second failure bit counting value of each of the semiconductor chips is obtained by counting the second failure bit, thereby obtaining a plurality of second failure bit counting values corresponding to the semiconductor chips; and calculating a failure rate of the semiconductor chips, the failure rate being an accumulated failure rate calculated by ∑ 1 M ⁢ P FB ⁡ ( n ) × P FD ⁡ ( n ) , wherein the P FB (n) is equal to 1/M, and the P FD (n) is a bit failure probability of each of the semiconductor chips calculated by P FD ⁡ ( n ) = 1 - ∏ i = 1 n ⁢ ⁢ N w - n b - i + 1 N w , wherein the N w represents an error checking and correcting coefficient, the n b represents an average value of the first failure bit counting values of the semiconductor chips, and the n represents a difference of the first failure bit counting value and the second failure bit counting value of each of the semiconductor chips.