Patent ID: 8030689

Claim:
A layout of an integrated circuit device, comprising: a substrate region layout that forms part of a substrate of the integrated circuit device; a first active region layout shape to be formed within the substrate region; a second active region layout shape to be formed within the substrate region; a gate electrode level region layout to be formed over the substrate region, wherein the gate electrode level region layout forms part of a gate electrode level of the integrated circuit device, the gate electrode level region layout including: first, second, third, and fourth gate electrode level layout shapes formed to extend lengthwise in a first direction over the first active region layout shape to respectively form conductive structures of first, second, third, and fourth transistors of a first transistor type that are electrically connected in a serial manner, wherein the first, second, third, and fourth gate electrode level layout shapes are the only gate electrode level layout shapes formed to extend over the first active region layout shape, and fifth, sixth, seventh, and eighth gate electrode level layout shapes formed to extend lengthwise in the first direction over the second active region layout shape to respectively form conductive structures of first, second, third, and fourth transistors of a second transistor type that are electrically connected in a serial manner, wherein the fifth, sixth, seventh, and eighth gate electrode level layout shapes are the only gate electrode level layout shapes formed to extend over the second active region layout shape, and wherein the first active region layout shape is separated by a non-active portion of the substrate region layout fro an other active region layout shape that forms another transistor of the first transistor type, and wherein the second active region layout shape is separated by a non-active portion of the substrate region layout from any other active region layout shape that forms another transistor of the second transistor type, and wherein both the first gate electrode level layout shape and the fifth gate electrode level layout shape are formed from a first linear layout shape within the gate electrode level region layout, and wherein both the fourth gate electrode level layout shape and the eighth gate electrode level layout shape are formed from a second linear layout shape within the gate electrode level region layout.