Patent ID: 7777822

Claim:
A method of forming an array substrate for use in a liquid crystal display device, comprising: forming a first metal layer and a first barrier metal layer in series on a substrate, wherein the first metal layer is one of aluminum and aluminum alloy; patterning simultaneously both the first metal layer and the first barrier metal layer using a first mask process to form a gate electrode, a gate line and a gate pad on the substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure including of the first metal layer and the first barrier metal layer; forming a gate insulation layer on the substrate to cover the double-layered gate electrode, line and pad; forming sequentially a pure amorphous silicon layer, a doped amorphous silicon layer, a second barrier layer and a second metal layer of copper on the gate insulation layer; patterning simultaneously the pure and doped amorphous silicon layers and the second barrier and second metal layers using a second mask process to form a data line, source and drain electrodes, a data pad, and silicon patterns, wherein the data line is on the gate insulation layer and crossed the gate line, wherein the data line, the source and drain electrodes, the capacitor electrode and the data pad have a double-layered structure including the second barrier metal layer and the second metal layer of copper, and wherein the silicon patterns consist of a first layer of pure amorphous silicon and a second layer of doped amorphous silicon and are disposed underneath the data line, the data pad, and the source and drain electrodes; forming a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad; patterning the passivation layer using a third mask process to form a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad, and a data pad contact hole exposing the data pad; and forming a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer using a fourth mask process, wherein a width of the gate pad contact hole is greater than a width of the gate pad, and wherein the gate pad terminal contacts an upper surface of the first barrier metal layer of the gate pad and side surfaces of the first barrier metal layer and the first metal layer of the gate pad through the gate pad contact hole.