Patent ID: 7961034

Claim:
A method for compensating negative bias temperature instability (NBTI) effects on a given model of PMOS transistors in a processor, the method comprising: monitoring a plurality of threshold voltage shifts of the PMOS transistors on an emulated time scale under accelerated stress conditions to emulate the effects of NTBI degradation of the PMOS transistors over an actual lifetime of the PMOS transistors; extrapolating a plurality of expected threshold voltage shifts of the PMOS transistors corresponding to normal operating conditions over the lifetime of the PMOS transistors based on the monitoring; determining a plurality of forward bias voltages for the PMOS transistors based on the plurality of expected threshold voltage shifts, wherein each forward bias voltage is sufficient to compensate for the corresponding one expected threshold voltage shift; storing the plurality of forward bias voltages for the PMOS transistors in a lookup table accessible by the processor; and during runtime, applying a selected forward bias voltage to the PMOS transistors, wherein the selected forward bias voltage is one of the plurality of forward bias voltages stored in the lookup table that corresponds to a time in the lifetime of the PMOS transistors corresponding to the runtime.