Patent ID: 8912521

Claim:
A semiconductor memory device comprising a memory cell array, the memory cell array comprising a plurality of first wiring lines, a plurality of second wiring lines, the first and second wiring lines crossing each other, and a plurality of memory cells, the memory cells being disposed in crossing portions of the first and second wiring lines, each memory cell comprising a variable resistance element, the memory cell array comprising: a plurality of first conductive layers, the first conductive layers extending in a first direction horizontal to a substrate as a longitudinal direction, and the first conductive layers being stacked in a direction perpendicular to the substrate; an interlayer insulating layer provided between the first conductive layers; a variable resistance layer formed continuously on side surfaces of the first conductive layers and the interlayer insulating layer; and a columnar conductive layer provided on side surfaces of the first conductive layers and the interlayer insulating layer via the variable resistance layer, the columnar conductive layer extending in a direction perpendicular to the substrate as a longitudinal direction, first side surfaces of the first conductive layers being recessed from a second side surface of the interlayer insulating layer in a direction away from the columnar conductive layer, the variable resistance layer being formed continuously on the first and second side surfaces, each variable resistance layer having a convex shape on the second side surface.