Patent ID: 7056807

Claim:
A wafer bonding method to form integrated chips, comprising: selectively depositing a plurality of metallic lines into interlevel dielectrics (ILDs) on opposing surfaces of adjacent wafers; depositing at least a barrier line on an outer edge of each of the opposing surfaces of the adjacent wafers; selectively aligning the adjacent wafers to form a stack; bonding exposed portions of the metallic lines on the opposing surfaces of the adjacent wafers to establish electrical connections between active integrated circuit (IC) devices on the adjacent wafers; and bonding the barrier lines on the opposing surfaces of the adjacent wafers to form a barrier structure on the outer edge of the adjacent wafers, wherein the bonded wafers includes a plurality of individual die and the barrier structure is formed on the outer edge of the bonded wafers to protect internal die from corrosion, contamination and crack propagation when the bonded wafers are cut into individual die.