Patent ID: 8742790

Claim:
A level shift circuit, comprising: a first latch circuit configured to receive a clock signal, a digital data signal, a first supply voltage, and a second supply voltage greater than the first supply voltage, and generate, in response to the clock signal, a first output signal based on the digital data signal, wherein the first output signal has i) a first voltage level corresponding to the first supply voltage, and ii) a second voltage level corresponding to the second supply voltage; at least one capacitor configured to i) receive the first output signal, and ii) retain a voltage value corresponding to the output signal; and a second latch circuit configured to receive the voltage value, a third supply voltage different than the first supply voltage, and a fourth supply voltage different than the second supply voltage and greater than the third supply voltage, and generate a second output signal based on the voltage value, the second output signal having i) a third voltage level corresponding to the third supply voltage and ii) a fourth voltage level corresponding to the fourth supply voltage.