Patent ID: 8546217

Claim:
A method for forming a flash memory cell, comprising: providing a substrate; successively forming a first dielectric layer, a first polysilicon layer, a second dielectric layer, a second polysilicon layer and a hard mask layer on the substrate; successively etching the hard mask layer, the second polysilicon layer, the second dielectric layer, the first polysilicon layer and the first dielectric layer to form an opening to expose a portion of the substrate; successively forming a third dielectric layer and a third polysilicon layer over the hard mask layer and the opening's sidewalls and bottom surface; etching the third polysilicon layer and the third dielectric layer to expose the hard mask layer and a portion of the substrate, the remaining third polysilicon layer and the remaining third dielectric layer forming a word line and a word line dielectric layer on each of the opening's sidewalls; implanting ions into the exposed portion of the substrate to form a source region; forming a source line on the surface of the source region of the exposed semiconductor substrate, and an isolating dielectric layer between the source line and each word line; removing the hard mask layer; forming a first spacer on a side of each word line dielectric layer away from the word line; and successively etching the second polysilicon layer, the second dielectric layer, the first polysilicon layer and the first dielectric layer with the first spacers as a mask until the substrate is exposed, to form a gate stack comprising a control gate, a control gate dielectric layer, a floating gate and a floating gate dielectric layer on each side of the source line.