Patent ID: 8111087

Claim:
A semiconductor integrated circuit comprising: an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction which has one of a high resistance state and a low resistance state and which is located between a source terminal and a drain terminal, the n-channel spin FET including a gate terminal to receive an input signal, the source terminal to receive a first power supply potential, and the drain terminal connected to an output terminal; a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential higher than the first power supply potential, and a drain terminal connected to the output terminal; a subsequent circuit connected to the output terminal; and a control circuit configured to start charging the output terminal by turning the p-channel FET on and turning the n-channel spin FET off, configured to end the charging of the output terminal by turning the p-channel FET and the n-channel spin FET off, and configured to input the input signal to the gate terminal of the n-channel spin FET after the charging ends.