Patent ID: 7515473

Claim:
A semiconductor memory device comprising: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read and write data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be connected to the verify-judge circuit, into which column separation data are written to exclude the corresponding columns from a verifying object, wherein during an initial set-up sequence at power-on, the column separation data in the data latches are first reset so that the respective columns are included in the verifying object, and then the column separation data in the data latches are automatically set so that in addition to defective columns at least a part of inaccessible columns for users are excluded from the verifying object.