Patent ID: 7599221

Claim:
A non-volatile semiconductor memory device comprising: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of said first memory cell; a second bitline connected to a diffusion layer which is used as a drain of said first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from said first bitline and connected to a diffusion layer which is used as a source of said first reference cell; a fourth bitline connected to a diffusion layer which is used as a drain of said first reference cell; a read circuit identifying data stored in said first memory cell in response to a memory cell signal received from said first memory cell through said second bitline and a reference signal received from said first reference cell through said fourth bitline; and a bitline level controller controlling a voltage level of said third bitline, wherein said bitline level controller controls said third bitline to a voltage level different from that of said first bitline in a data read operation from said first memory cell.