Patent ID: 8352815

Claim:
A circuit comprising: a plurality of flip flops, each of said flip flops including: a master latch and a slave latch; a data input and a scan input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input, a functional clock signal input configured to receive a functional clock and a scan clock signal input configured to receive a scan clock; wherein: said scan input tristateable device is clocked by said scan clock signal, said data input tristateable device is clocked by said functional clock signal, and said scan input tristateable device and said data input tristateable device are different devices; in response to a first predetermined value of said scan enable signal indicating a functional mode of operation, said scan input tristateable device is arranged to isolate said scan input from said master latch, and said master latch is arranged in response to said functional clock to receive data from said data input and to output data to said slave latch and said slave latch is arranged in response to said functional clock to receive data from said master latch and to output data at a data output; and in response to a second predetermined value of said scan enable signal indicating a scan mode of operation, said data input tristateable device is arranged to isolate said data input from said master latch, said master latch is arranged in response to said scan clock to receive data from said scan input, and said slave latch is arranged in response to said functional clock to receive data from said master latch and to output data at a scan output, said circuit further comprises a plurality of said flip flops arranged in series such that a scan output of one flip flop is connected to a scan input of a subsequent flip flop, said circuit being arranged in response to a reset signal indicating a reset mode to receive a predetermined signal value of said scan clock and a predetermined signal value of said functional clock, so as to control the state of said plurality of flip flops based on said predetermined scan clock signal value and said predetermined functional clock signal value such that the flip flops are set to a value determined by a value at the scan input of the series.