Patent ID: 8525271

Claim:
A method for fabricating a transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising: in a first region having a first doped well providing a foundation for a PMOS transistor element: ion implanting in the semiconductor substrate a first doped screening layer in contact with the first doped well, the first doped screening layer including antimony; ion implanting in the semiconductor substrate a first doped threshold voltage control layer in contact with the first doped screening layer; in a second region having a second doped well providing a foundation for an NMOS transistor element: ion implanting in the semiconductor substrate a second doped screening layer in contact with the second well; ion implanting in the semiconductor substrate a second doped threshold voltage control layer in contact with the second doped screening layer; forming a third layer on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, by way of multiple blanket undoped epitaxial growth to establish an intrinsic channel for each of the PMOS and NMOS transistor elements; wherein the third layer of the PMOS transistor element is formed with a different channel thickness than the third layer of the NMOS transistor element.