Patent ID: 8726214

Claim:
A floorplanning method for an analog integrated circuit layout, comprising a computer configured to perform the following steps: defining a first-type block as a movable and deformable block with rectangle constraint, and a second-type block as a fixed-size block without rectangle constraint; classifying each block in a floorplan to the first-type or the second-type block; a shape determination step for determining a target shape among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap between blocks in the floorplan; an overlap elimination step for analyzing neighboring blocks of each said overlap, which is then eliminated by utilizing surrounding space; and an enlargement stage step for utilizing unused space for enlarging the first-type block; wherein the shape determination step comprises: deciding a moving order and determining balance lines on specified sides in the decided moving order such that an area of a block after all edges are moved to the balance lines is consistent with an area of the block before moving the edges to the balance lines; for each said moving order, checking whether there is an obstacle block; and moving a neighboring block of the moving edge in order to decrease an amount of overlap and preserve component topology that defines relative locations of blocks present in the floorplan.