Patent ID: 8291256

Claim:
Digital VLSI circuit characterized by comprising: a plurality of arithmetic operation units executing arithmetic processing synchronized with clock working on each stage of pipeline arithmetic processing; Detection means detecting end of arithmetic processing of stage in charge in the arithmetic operation unit; and clock signal supply control means controlling supply/stop of clock by each arithmetic operation unit; wherein data of the arithmetic processing includes dynamic picture image data comprising frame data with a frame-processing period and the frame data includes a plurality of macroblock data, wherein the arithmetic processing includes encoding/decoding process of the dynamic picture images, wherein the arithmetic operation unit executes the pipeline arithmetic processing as a unit by the macroblock data, wherein the clock signal supply control means stop clock signal supply for the arithmetic operation unit in which end of arithmetic processing of the macroblock data is detected by the detection means; and wherein clock signal supply restarts for all the arithmetic operation units for the next pipeline arithmetic processing when end of arithmetic processing of the macroblock data is detected in all the arithmetic operation units by the detection means; wherein the clock signal supply control means in arithmetic processing of the last macroblock data in the frame data, continues stop of clock signal supply for all the arithmetic operation units even if end of arithmetic processing is detected in all the arithmetic operation unit by the detection means; and wherein clock signal supply restarts for all the arithmetic operation units for pipeline arithmetic processing of the next frame data after the frame-processing period.