Patent ID: 8097918

Claim:
A semiconductor arrangement, comprising: a semiconductor body; a number of transistor cells integrated in the semiconductor body, each transistor cell comprising a first active transistor region; a number of first contact electrodes, each of the first contact electrodes contacting the first active transistor region of at least one transistor cell through a contact plug; a second contact electrode contacting a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes, the first group of first contact electrode including at least two first contact electrodes; transistor cells being contacted by first contact electrode of the first group forming a load transistor, with the second contact electrode forming a load terminal of the load transistor; and transistor cells being contacted by first contact electrode of the second group forming a sense transistor, wherein the first contact electrodes are planar electrodes, and wherein the first contact electrodes have a thickness, a width and a length, with the thickness being smaller than at least one of the width and the length.