Patent ID: 7370295

Claim:
A method for compiling a user design for an integrated circuit, the method comprising: specifying a design space comprising input parameter settings; determining a probability of improvement with respect to at least one design goal for each input parameter setting of at least a first portion of the design space; selecting a second portion of the design space based on the probability of improvement associated with at least one input parameter setting of the design space; automatically performing multiple compilations of the user design using the input parameter settings of at least some of the second portion of the design space until a stopping criteria is reached; automatically evaluating the results of the multiple compilations of the user design with respect to at least one design goal to determine an optimal set of input parameter settings in the second portion of the design space; and reporting the optimal set of input parameter settings; wherein a first input parameter setting is associated with a first optimization algorithm and the probability of improvement for the first input parameter setting is determined from a correlation and results of a second optimization algorithm applied to the user design, wherein the correlation is determined from an evaluation of results of compilations of a set of sample designs with the first and second optimization algorithms.