Patent ID: 7084685

Claim:
A clock circuit for generating an output clock in a data path according to a reference clock, in which there are signals of a plurality of periods, and each period of the signals has one rising edge and one falling edge, the clock circuit comprising: a first flip-flop having a first clock port, wherein the first flip-flop generates a first signal according to triggering of the reference clock on the first clock port, and the first flip-flop changes a level of the first signal when each rising edge of reference clock occurs; a second flip-flop having a second clock port, wherein the second flip-flop generates a second signal according to triggering of the reference clock on the second clock port, and the second flip-flop changes a level of the second signal when each falling edge of reference clock occurs; and a logic module comprising an XOR gate for generating the output clock according to results of an XOR operation between the first signal and the second signal.