Patent ID: 7544552

Claim:
A method for manufacturing a junction semiconductor device, comprising: forming a first high-resistance layer on one surface of a semiconductor substrate of a first conductive type; forming a channel-doped layer on said first high-resistance layer; forming a second high-resistance layer on said channel-doped layer; forming a low-resistance layer of a first conductive type that acts as a source region directly on an upper surface of said second high-resistance layer; performing etching through said low-resistance layer and partial etching through said second high-resistance layer until a midway depth thereof so that a partially etched-out portion of the second high-resistenace layer has a bottom lying between a lower surface of the source region and an upper surface of the channel-doped layer; forming a gate region below the partially etched-out portion of the second high-resistance layer; forming a protective film on a surface of a region between said gate region and said source region; joining a source electrode on said low-resistance layer; a gate electrode on said gate region, and a drain electrode on the other surface of said semiconductor substrate; and forming an upper layer electrode above the source electrode and the gate electrode, wherein the step of forming the protective film includes forming the protective film along a bottom of the recessed-shaped etched portion, on which the gate electrode is subsequently disposed.