Patent ID: 7956424

Claim:
A semiconductor device comprising: a charge storage layer formed on a semiconductor substrate; a plurality of bit lines, each bit line of the plurality of bit lines extending inside the semiconductor substrate; a plurality of interspaces, each interspace of the plurality of interspaces being interposed between adjacent bit lines of the plurality of bit lines; a plurality of gates formed on the charge storage layer above the plurality of interspaces along a longitudinal direction of the plurality of bit lines; and a plurality of word lines electrically coupled with the plurality of gates formed on an interspace of the plurality of interspaces, each word line of the plurality of word lines extending to intersect with the plurality of bit lines, wherein a first gate of the plurality of gates is adjacent to a second gate of the plurality of gates in a width direction of a bit line, and the first gate is connected to a different word line than the second gate and wherein a word line electrically coupled with the first gate is also electrically coupled with the gate adjacent to the first gate in the width direction of the bit line at a side opposite to the first gate.