Patent ID: 7042747

Claim:
A ternary content addressable memory (TCAM) bitcell layout, comprising: a first SRAM bitcell comprising two p-type transistors and four n-type transistors, said first SRAM bitcell being connected to a wordline, source voltage Vss, drain voltage Vdd, and a first pair of complementary bitlines, such that a first bit is stored in said first SRAM bitcell; a second SRAM bitcell comprising two p-type transistors and four n-type transistors, said second SRAM bitcell being connected to said wordline, said first power line, said second power line, and a second pair of complementary bitlines, such that a second bit is stored in said second SRAM bitcell; a first comparison circuit comprising two n-type transistors that compares said first bit to a value carried by a first hitline; and a second comparison circuit comprising two n-type transistors that compares said second bit to a value carried by a second hitline; wherein active areas for said n-type transistors for said first SRAM bitcell and said second SRAM bitcell form three diffusion regions separated by two isolation regions.