Patent ID: 8223543

Claim:
A nonvolatile semiconductor memory comprising: first and second select gate transistors; memory cells connected in series between the first and second select gate transistors; a source line connected to the first select gate transistor; a bit line connected to the second select gate transistor; a selected word line which is connected to a selected memory cell as a target of a verify reading among the memory cells; a non-selected word line which is connected to a non-selected memory cell except the selected memory cell among the memory cells; a sense node connected to the bit line; a first latch circuit latching a potential of the sense node at a first point after a first term from a start point which a discharge of the sense node is started by the cell current; a second latch circuit latching a potential of the sense node at a second point after a second term longer than the first term from the start point, the sense node and the bit line being electrically connected each other at the first point regardless of data latched in the first latch circuit; and a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line.