Patent ID: 8525313

Claim:
A chip assembly, comprising: a chip having a front surface, a rear surface and a side, the chip having conductive contacts on the front surface; a conductive paddle coupled to the chip, the conductive paddle having a front surface, a rear surface and a side; a conductive interface layer disposed between the rear surface of the chip and the front surface of the conductive paddle, the conductive interface layer coupled to the rear surface of the chip and coupled to the front surface of the conductive paddle; a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the conductive paddle, an interface layer disposed between the frequency extending device and the conductive paddle; and a plurality of conductive lands disposed at least partially adjacent to the side of the conductive paddle, at least one of the conductive contacts connected to at least one of the one or more conductive traces, the at least one of the one or more conductive traces connected to at least one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that an impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires each having a length substantially equal to a distance between one of the conductive contacts of the chip and a corresponding one of the plurality of conductive lands, wherein the frequency extending device completely surrounds the side and the front surface of the chip.