Patent ID: 7983084

Claim:
A three-dimensionally stacked nonvolatile semiconductor memory comprising: a memory cell array provided in a semiconductor substrate; three or more first conductive layers stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; three or more second conductive layers which are adjacent to the first conductive layers in a first direction and which are stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; a straight bit line which is disposed on the first and second conductive layers in such a manner as to be insulated from the first and second conductive layers and which extends in the first direction; a straight source line which is provided between the bit line and the uppermost second conductive layer and which extends in a second direction intersecting with the first direction; a first semiconductor column which extends through the plurality of first conductive layers and which has an upper end connected to the bit line; a second semiconductor column which extends through the plurality of second conductive layers and which has an upper end connected to the source line and a lower end connected to the first semiconductor column; two or more first straight word lines for which the conductive layers among the three or more first conductive layers except for the uppermost conductive layer are used and which extend in the second direction; two or more second straight word lines for which the conductive layers among the three or more second conductive layers except for the uppermost conductive layer are used and which extend in the second direction; memory cells provided at intersections of the two or more first word lines and the first semiconductor column and at intersections of the two or more second word lines and the second semiconductor column, respectively; a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the first and second word lines; and a potential control circuit which controls the potentials supplied to the first and second word lines and which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.