Patent ID: 8443033

Claim:
A low-density parity check min-sum decoder including a variable node processing unit comprising N+1 inputs, at least a first bank of two-input adders and a separate last bank of two-input adders, with the banks of adders disposed in series, a sign module for outputting a sign value, and N+1outputs, where one of the outputs is the sign value, wherein N=4, the first bank of adders is designated as the Y adders and the last bank of adders is designated as the S adders, the inputs are A 1 , A 2 , A 3 , A 4 , and M, the outputs are S 1 , S 2 , S 3 , S 4 , and SIGN, and the variable node processing unit processes according to equations: y 1 =M+A 1, y 2 =M+A 2, y 3 =A 2 +A 3, y 4 =A 2 +A 4, y 5 =A 3 +A 4, S 1 =y 2 +y 5, S 2 =y 1 +y 5, S 3 =y 1 +y 4, S 4 =y 1 +y 3, and SIGN=sign( A 4 +S 4).