Patent ID: 8228113

Claim:
A power semiconductor module comprising: a normally on, controllable first power semiconductor switch, which comprises one or a plurality of first power semiconductor chips electrically connected in parallel, each of which has a first load terminal, a second load terminal, and a control terminal and also a load path formed between the first load terminal and the second load terminal of the relevant first power semiconductor chip, wherein the first power semiconductor switch has a load path formed by the parallel circuit composed of the load paths of the first power semiconductor chips; a normally off, controllable second power semiconductor switch, which comprises one or a plurality of second power semiconductor chips electrically connected in parallel, each of which has a first load terminal, a second load terminal, and also a control terminal, and also a load path formed between the first load terminal and the second load terminal of the relevant second power semiconductor chip, wherein the second power semiconductor switch has a load path formed by the parallel circuit composed of the load paths of the second power semiconductor chips; a circuit carrier, which comprises an insulation carrier having a top side and an upper metallization layer applied to the top side, said metallization layer being structured to form conductor tracks; wherein: all first power semiconductor chips are arranged on a first one of the conductor tracks; all second power semiconductor chips are arranged on a second one of the conductor tracks; the load paths of the first power semiconductor switch and of the second power semiconductor switch are electrically connected in series; the control terminals of all first power semiconductor chips are permanently electrically conductively connected to a third one of the conductor tracks; none of the first load terminals and none of the second load terminals of the first power semiconductor chips are permanently electrically conductively connected to the third conductor track; none of the first load terminals, none of the second load terminals and none of the control terminals of the second power semiconductor chips are permanently electrically conductively connected to the third conductor track; and the second load terminals of the second power semiconductor chips are permanently electrically conductively connected to a fourth one of the conductor tracks.