Patent ID: 7102947

Claim:
A semiconductor memory device comprising: a memory cell array which has a plurality of memory cells arranged in a matrix form; a plurality of first bit line pairs which transfer data among the memory cells; a plurality of second bit line pairs disposed respectively corresponding to the plurality of first bit line pairs; a plurality of variable resistance elements disposed respectively to connect the plurality of first bit line pairs to the plurality of second bit line pairs; a plurality of data line pairs disposed respectively corresponding to the plurality of second bit line pairs; a plurality of input/output gates which transfer data respectively between the plurality of second bit line pairs and the plurality of data line pairs; a plurality of sense amplifier circuits which respectively amplify data transferred to the plurality of second bit line pairs; and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements, wherein the plurality of variable resistance elements comprise a plurality of first groups respectively including at least one variable resistance element, and the bit line isolation control circuit controls the resistance values of the variable resistance elements in units of the first groups.