Patent ID: 7499352

Claim:
An integrated circuit device comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns including (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address; address decoder circuitry to generate decoded row address data in response to an applied row address; normal word line drivers, coupled to the address decoder circuitry and the plurality of normal rows of memory cells, to responsively enable one or more normal rows of memory cells using the decoded row address data; redundant word line drivers, coupled to the address decoder circuitry and the redundant row of memory cells, to responsively enable the redundant row of memory cells using the decoded row address data; and redundancy address evaluation circuitry, coupled to the address decoder circuitry, the normal word line drivers and the redundant word line drivers, to (i) store decoded redundant row address data which corresponds to the redundant row address, and (ii) in operation, determine whether the decoded row address data corresponds to the decoded redundant row address data, and, in response thereto, enable the redundant word line drivers.