Patent ID: 8837226

Claim:
A memory comprising: a storage array coupled to a first voltage supply; a plurality of wordline driver units, each including an inverter configured to provide a wordline signal to the storage array, wherein the inverter is coupled to a second voltage supply; wherein each inverter includes a p-type transistor coupled to an n-type transistor, wherein the input to the inverter is coupled to a gate terminal of each of the n-type and the p-type transistors, and an output of the inverter is a node between the n-type and the p-type transistors; wherein each wordline driver unit includes a p-type retention transistor coupled between the first voltage supply and the input to the inverter; and a control unit coupled to the plurality of wordline driver units and to the storage array, wherein the control unit is configured to provide a control signal to the p-type transistor to provide a path from the first voltage supply to the input of the inverter, and to reduce a voltage of the second voltage supply during operation in a low power mode.