Patent ID: 8896120

Claim:
An interconnect structure comprising: a cured photo-patternable low k (PPLK) material located atop a substrate, wherein said cured PPLK material is a permanent on-chip insulator and includes a plurality of conductively filled openings located therein, wherein each of said conductively filled openings of said plurality of conductively filled openings comprises a conductive material and a diffusion barrier located on sidewalls and a bottom wall of each conductive material, and wherein a topmost surface of each of said conductive material and said diffusion barrier within said conductively filled openings is co-planar with an uppermost surface of the cured PPLK material; at least one first air gap having a first depth located within said cured PPLK material and between first preselected neighboring conductively filled openings, wherein said at least one first air gap is in direct physical contact with said diffusion barrier of said first preselected neighboring conductively filled openings; at least one second air gap having a second depth located within said cured PPLK material and between second preselected neighboring conductively filled openings, wherein said first depth is different than said second depth, wherein said at least one second air gap is in direct physical contact with said diffusion barrier of said second preselected neighboring conductively filled openings; and a dielectric cap located atop the cured PPLK material as well as atop said at least one first air gap and the at least one second air gap, wherein each of said at least one first air gap and said second air gap has a bottommost surface that directly contacts a portion of said cured PPLK material which includes said plurality of conductively filled openings located therein.