Patent ID: 7842982

Claim:
A semiconductor device comprising: a semiconductor substrate having, on a surface thereof, a (110) surface of Si 1-x Ge x (0≦x≦0.90); and an n-channel MISFET and a p-channel MISFET formed on the (110) surface, each MISFET having a source region, a channel region and a drain region, the n-channel MISFET having an active region containing a facet of a (311) or (111) surface, and the source region, the channel region and the drain region being formed in this order or in reverse order in a [−110] direction of the active region, the p-channel MISFET having a linear active region which is longer in a [−110] direction than in a [001] direction and which has a facet of a (311) or (111) surface, and the source region, the channel region and the drain region being formed in this order or in reverse order in a [−110] direction of the active region, the channel region of the n-channel MISFET being formed of a group III-V compound, the channel region of the p-channel MISFET being formed of Si 1-y Ge y (x<y≦1), and the channel region of the n-channel MISFET having isotopically relaxed strain, and the channel region of the p-channel MISFET having uniaxial compressive strain in the [−110] direction of the active region.