Patent ID: 7397094

Claim:
A semiconductor device provided with a MISFET having: a silicon substrate; a gate insulating film formed over a main surface of said silicon substrate; and a gate electrode formed over said gate insulating film, wherein said gate insulating film includes a first insulating film formed over said silicon substrate and a metal silicate layer formed over said first insulating film, wherein said metal silicate layer is composed of a plurality of silicon oxide layers alternatingly laminated with a plurality of metal oxide layers, each of the plurality of silicon oxide layers being laminated so as to be adjacent to at least one corresponding metal oxide layer, wherein one of said metal oxide layers formed closest to said gate electrode is thicker than another one of said metal oxide layers formed closest to said silicon substrate, wherein a concentration of silicon in said metal silicate layer is distributed to become higher on a silicon-substrate side than on a gate-electrode side, wherein a concentration of metal in said metal silicate layer is distributed to become lower on the silicon-substrate side than on the gate-electrode side, and wherein an Equivalent Oxide Thickness (EOT) of said gate insulating film is 1.0 nm or less.