Patent ID: 6898691

Claim:
A group of instructions in a Matrix Processor that rearranges data between vector and matrix forms of an A×B matrix of data where the data matrix includes one or more 4×4 sub-matrices of data, comprising: 16 processing elements where an individual processing element (PE) comprises one or more PE register entries in a PE register file; a mesh row column interconnect that couples said processing elements into a 4×4 matrix processing array; a first, second, third, and fourth matrix register wherein an individual matrix register comprises an individual PE register entry from each said PE register file from each said individual processing element that are then combined together to from said individual matrix register; wherein said first, second, third, and fourth matrix registers simultaneously swaps row or columns between said first, second, third, and fourth matrix registers according to the instructions that perform predefined matrix tensor operations on the data matrix that includes one of the following group of operations: swapping rows between said first, second, third, and fourth matrix registers, or swapping columns between said first, second, third, and fourth matrix registers.