Patent ID: 8108626

Claim:
An apparatus of time keeping for a non-real-time Operating System (OS), the apparatus comprising: a processor for requesting performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a DPRAM R/W time interval in a Time Division Multiple Access (TDMA) scheme using a system clock and for placing guard time intervals between the plurality of R/W time intervals, wherein the guard time intervals and the R/W time intervals do not overlap; and a Field Programmable Gate Array (FPGA) for comparing, upon receipt of the DPRAM R/W operation performance request from the processor, the operation performance request time with an access time table defining a DPRAM R/W time interval for the processor, generated in the TDMA scheme using the system clock, performing the operation requested by the processor when the operation performance request has been made in the DPRAM R/W time interval of the processor and performing the operation requested by the processor and generating an alarm interrupt signal to the processor when the operation performance request has been made in the guard time interval.