Patent ID: 7701781

Claim:
A semiconductor memory device capable of simultaneously carrying out a first operation of reading data from nonvolatile memory cells and a second operation of writing data into or erasing data from the memory cells, the semiconductor memory device comprising: a memory cell array which includes the memory cells; a first control circuit which controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started; a second control circuit which controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other; a latch circuit which latches the sequence flag; a select control circuit which generates a read start pulse signal and a select control signal and which generates the read start pulse signal by delaying the read start signal, the select control signal, when the sequence flag is output, being asserted if the second operation is being carried out or being negated if the second operation has not been carried out at the time the output of the read start pulse signal ends; and a select circuit selects either the sequence flag held in the latch circuit or the data read by the first control circuit according to an instruction from the first control circuit and outputs the selected one, the first control circuit instructing the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.