Patent ID: 8289769

Claim:
A method of programming a nonvolatile memory device comprising memory cells, coupled to bit lines and word lines, and page buffers each coupled to one or more of the bit lines, the method comprising: performing a program operation and a verification operation on a first logical page of a plurality of logical pages included in memory cells selected for the program operation; loading data for the program operation for a second logical page of the plurality of logical pages into a first latch, a second latch, and a third latch of a selected page buffer of a plurality of page buffers, coupled to the selected memory cells; changing states of the data, stored in the second and third latches, according to a program state of the selected memory cells; changing a state of the data stored in the second latch according to the program state of the selected memory cells and the data state of the first latch; resetting the first latch; storing a result of the program operation for the first logical page in the first latch; and shifting a first, second, third, and fourth threshold voltage distribution according to states of the data of the first, second, and third latches; and performing verification operations using two of a plurality verification voltages for each of the second and third threshold voltage distributions.