Patent ID: 7804906

Claim:
A multicarrier transceiver comprising: a digital signal processor (DSP) configured with a plurality of memory locations; a direct memory access (DMA) coupled to the DSP, the DMA configured to send and receive data to the plurality of memory locations; a plurality of first in first out (FIFO) buffers coupled to the DMA, the plurality of FIFO buffers configured to send and receive data for communication; an encoder module coupled to receive data from the plurality of FIFO buffers; a decoder module coupled to transmit data to the plurality of FIFO buffers; a Fourier transform module coupled to the encoder to receive encoded data the Fourier transform module configured to perform inverse Fast Fourier transforms for transmit operations and to perform Fast Fourier transform (FFT) operations for receive operations; a plurality of distributed modules including the encoder module, the decoder module and the Fourier transform module, each module of the plurality of distributed modules configured with a memory port, each memory port coupled to a peripheral bus and the DMA; a plurality of memory ports coupled to each module of the plurality distributed modules, the plurality of memory ports coupled to a bus; a point-to-point bus coupled to at least two of the plurality of distributed modules, the point-to-point bus configured to enable data flow and testing and provide a bypass capability for each module of the plurality of distributed modules; and a receive FIFO coupled to the Fourier transform module, the Fourier transform module being responsive to one or more programmable watermarks that enable encoder operations to begin and function as a system timing reference.