Patent ID: 7342507

Claim:
A meter comprising first and second processors, first and second data busses, first and second memories, at least one bus arbiter responsive to said first and second processors and coupled with said first and second data busses and at least one transfer controller responsive to said first and second processors and coupled with said at least one bus arbiter, wherein each of said processors are coupled with a respective each said data busses and each of said data busses are coupled with a respective each of said memories, a method of transferring data between said first and second memories comprising: requesting, from said first processor, at least one data transfer between said first memory and said second memory; releasing control of said first data bus by said first processor; signaling by said first processor to said at least one bus arbiter to couple said first data bus to said second data bus; coupling said first data bus to said second data bus; transferring data between said first memory and said second memory under control of said at least one transfer controller; isolating said first data bus from said second data bus upon completion of said data transfer; signaling from said at least one bus arbiter that said data transfer is complete; and acquiring control of said first data bus by said first processor.