Patent ID: 7307309

Claim:
A transistor formed on a substrate having a first conductivity type, comprising: a first impurity region having a second conductivity type formed at a face of the substrate; a second impurity region having the second conductivity type formed at the face of the substrate and spaced apart from the first region; a hole formed in the face of the substrate between the first and second impurity regions, a bottom surface of the hole having direct contact with the substrate having a first conductivity type; a first dielectric region formed over the hole and over the face of the substrate above a portion of the second impurity region; and a third impurity region having the second conductivity type formed at the face of the substrate, the third region adjacent the hole and in electrical contact with the second region; wherein the first dielectric region has a variable thickness along a sidewall of the hole, the variable thickness corresponding to a net donor concentration within the third impurity region.