Patent ID: 7495312

Claim:
An integrated circuit comprising: a first vertical bipolar transistor including a base region, an emitter region and a buried collector region, wherein for the first vertical bipolar transistor the emitter region, the base region and the buried collector region are arranged such that there is no overlap between the emitter region and the buried collector region, and such that there is at least a partial overlap between the base region and the buried collector region, wherein the buried collector region is laterally separated from the emitter region, and a second vertical bipolar transistor including a base region, an emitter region and a buried collector region, wherein for the second vertical bipolar transistor the emitter region, the base region and the buried collector region are arranged such that there is at least a partial overlap between the base region and the buried collector region, wherein the emitter region for the first vertical bipolar transistor is symmetric with respect to a vertical plane, and the buried collector region for the first vertical bipolar transistor is arranged only at one side of said vertical plane.