Patent ID: 7725778

Claim:
An electronic device including a motherboard mounted with a memory controller and a memory module interfaced to said memory controller, mounted with a plurality of memories and, comprising: a first dummy wiring which simulates and feeds back a path from said memory to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory controller; and a second dummy wiring which simulates and feeds back a path from said memory controller to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory; wherein said memory includes: a first output circuit capable of variably setting signal transition time; a first signal generating circuit which generates a test signal for the use in a setting operation of said signal transition time; and a first controlling circuit which sets said signal transition time to said first output circuit based on a transmission delay time of said test signal which has been outputted from said first signal generating circuit to said first dummy wiring and fed back; and said memory controller includes; a second output circuit capable of variably setting signal transition time; a second signal generating circuit which generates a test signal for setting said signal transition time; and a second controlling circuit which sets said signal transition time to said second output circuit based on a transmission delay time of said test signal which has been outputted from said second signal generating circuit to said second dummy wiring and fed back.