Patent ID: 8320134

Claim:
An embedded semiconductor device, comprising: a first dielectric; a first patterned conductive layer disposed on the first dielectric, wherein the first dielectric defines a first opening aligned with at least a portion of the first patterned conductive layer; a second patterned conductive layer overlying the first patterned conductive layer; an electrical interconnect extending from the first patterned conductive layer to the second patterned conductive layer; a second dielectric defining a second opening extending from the first patterned conductive layer to the second patterned conductive layer, wherein the electrical interconnect substantially fills the second opening; and a semiconductor device having an upper surface, lateral surfaces, and an active surface opposite the upper surface, wherein: the upper surface and the lateral surfaces of the semiconductor device are substantially covered by the second dielectric; and the semiconductor device is disposed between the first patterned conductive layer and the second patterned conductive layer; wherein the second dielectric includes: a first dielectric layer that substantially covers the upper surface and the lateral surfaces of the semiconductor device, and that defines a first portion of the second opening; and a second dielectric layer that is disposed adjacent to the active surface of the semiconductor device, and that defines a second portion of the second opening.