Patent ID: 8642422

Claim:
A manufacturing method of a semiconductor device, the manufacturing method comprising the steps of: selectively implanting impurities on the surface of the P-type substrate; forming a gate layer on a channel region where the impurities have been implanted and on the P-type substrate where the impurities are not implanted; implanting N-type impurities for forming an N-type diffusion layer masked with the gate layer formed on the channel region and on the P-type substrate, forming a first MOS device on a surface of the P-type substrate that has a characteristic that is similar to that of a depletion mode MOS device; forming a second MOS device on a surface of the P-type substrate that has a characteristic that is similar to that of a depletion mode MOS device; and forming a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with the P-type substrate and that extends into second and third well layers, wherein the entire channel stop region lies between the second MOS device and the third MOS device.