Patent ID: 7045396

Claim:
A method of fabricating a semiconductor package, comprising the steps of: a) providing a leadframe comprising: a die paddle defining opposed, generally planar top and bottom surfaces; and a plurality of leads extending at least partially about the die paddle in spaced relation thereto, each of the leads having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions; the transition from the first end to the second end in each of the leads occurring without the lower portion reversing direction to extend along the upper portion; b) attaching a semiconductor chip to the top surface of the die paddle; c) electrically connecting the semiconductor chip to at least one of the leads; and d) at least partially encapsulating the leadframe and the semiconductor chip with a sealing material such that the bottom sides of the lower portions of the leads and the top sides of the upper portions of the leads are exposed in the sealing material.