Patent ID: 8492872

Claim:
A semiconductor device comprising: a first semiconductor substrate; one or more dielectric layers formed on the first semiconductor substrate; one or more on-chip inductors formed above the first semiconductor substrate; a first plurality of through-silicon-vias formed through the first semiconductor substrate, extended from the first semiconductor substrate through part of the one or more dielectric layers and disposed to surround the on-chip inductors in a plan view; a first shielding patterned ground (PGS) layer disposed in the dielectric layer below the one or more on-chip inductors and to surround the on-chip inductors in the plan view, the first PGS layer being connected to one end of each first plurality of through-silicon-vias that extend in the dielectric layer for providing isolation to the on-chip inductors; and a first metalized backside layer connected to other end of each of the first plurality of through-silicon-vias to be a ground.