Patent ID: 7248664

Claim:
A method of simultaneously synchronizing multiple input signals to multiple output signals, comprising: communicating a plurality of signal pairs each comprising a clock input and a signal input; providing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time phase locked loop (PLL) in hardware for calculating an output signal from an input signal; providing a control logic; providing a context memory (RAM) for storing a history for each of the respective signal pairs; and, upon receipt at the discrete-time phase detector of the clock signal of a respective one of the signal pairs, operating the control logic to retrieve from the context memory the history for the respective signal pair, to enable the discrete-time PLL to calculate from the respective input signal a respective output signal thus defining a resulting history for the respective input signal, and to store the resulting history in the context memory for use in subsequent calculations for the respective input signal pair. wherein the PLL is arranged to carry out a calculation for each of the signal pairs; and wherein the multiple input signals are simultaneously synchronized by effecting the calculations of the PLL at a rate such that every input signal pair is serviced.