Patent ID: 6998310

Claim:
Process for manufacturing a Coulomb blockade transistor comprising the following on a substrate: a stack of channel layers ( 22 , 22 i , 22 c ) forming at least one quantum box, a source ( 12 ) and a drain ( 80 , 82 , 84 ) connected to the quantum box through tunnel junctions, at least one of which is distinct from the layers of the stack, and is stacked with the channel layers, at least one grid ( 60 ) facing at least one flank of the stack, the stack of layers comprising at least one nanometric conducting island ( 22 c ) arranged between the electrically insulating layers ( 22 i ), the process comprising the following steps in sequence: deposition on an insulating substrate of a source layer ( 12 ), a tunnel-insulating layer ( 20 ) and an alternating stack of at least one conducting layer ( 22 c ) and at least one insulating layer ( 22 i ), a first etching of the stack to form a filiform tab ( 30 ), coating of the filiform tab with an electrically insulating coating material ( 40 ), a second etching of the tab of the stack to form a pillar ( 50 ), the second etching preserving the coating material ( 40 ) to define a groove ( 52 ) on each side of the pillar ( 50 ), the formation of at least one isolated grid ( 60 ) in the groove ( 52 ), the formation of a drain ( 84 ) in contact with one end of the pillar opposite the source layer, through at least one tunnel-insulating layer ( 82 ).