Patent ID: 8755626

Claim:
An image processing device comprising: a processor configured to execute an image data acquiring unit that acquires image data; a delay pixel number specifying unit that specifies the number of pixels m for securing a delay time for preventing an error diffusion process from being performed at pixels of the (N+1)-th line in which diffusion of errors from pixels of the N-th line of the image data is not completed, N being a natural number; and an error diffusion processing unit that controls starting of the error diffusion process of the (N+1)-th line of the image data to perform the error diffusion process for each line of the image data upon completion of the error diffusion process of the m-th pixel of the N-th line of the image data such that the error diffusion process of the N-th line and the error diffusion process of the (N+1)th line are performed in parallel; wherein the delay pixel number specifying unit specifies m from a relationship of (W−m)×Tmax=(W−L−1)×Tmin on the basis of the number of pixels W of one line of the image data, a maximum value L of b in a case where a pixel of coordinates (i, N) of the N-th line is a target pixel and an error diffusion range of the (N+1)-th line is a range of coordinates (i−b, N+1) to coordinates (i+a, N+1), the shortest necessary time Tmin of the error diffusion process of each pixel, and the longest necessary time Tmax of the error diffusion process of each pixel, i being a natural number, and a and b being natural numbers.