Patent ID: 8386754

Claim:
Apparatus for processing data, said apparatus comprising: a register file addressable as registers having a plurality of different sizes including a first register size and a second register size, said first register size being an integer multiple of said second register size and said register file is addressable so as to permit aliasing between registers of said first size and registers of said second size; an instruction decoder configured to be responsive to a stream of program instructions of an instruction set to generate a decoded stream of micro-operations; scheduling circuitry configured to be responsive to said decoded stream of micro-operations to detect data dependency between micro-operations whereby hazard data within said register file written as a destination operand register of a first micro-operation is at least part of a source operand register of a second micro-operation and to generated an issued stream of micro-operations responsive to said data dependency; and execution circuitry configured to be responsive to said issued stream of micro-operations to perform processing operations corresponding to said stream of program instructions; wherein said instruction decoder is configured to be responsive to a program instruction specifying a source operand register of said first size and from a first group of program instructions of said instruction set to generate, before said scheduling circuitry detects any data dependence for said program instruction, one or more corresponding micro-operations for execution by said execution circuitry and specifying said source operand register as one or more registers of said second size within said register file; said scheduling circuitry is configured to be responsive to data dependency between a destination register of said second size and a source register of said second size to generate said stream of issued micro-operations to permit issue of said second micro-operation prior to generation of said hazard data by said first micro-operation; said instruction decoder is configured to be responsive to a program instruction specifying a source operand register of said first size and from a second group of program instructions of said instruction set to generate, before said scheduling circuitry detects any data dependence for said program instruction, one or more corresponding micro-operations specifying said source operand register as a register of said first size within said register file; and said scheduling circuitry is configured to be responsive to data dependency between a destination register of said second size and a source register of said first size to generate said stream of issued micro-operations so as not to permit issue of said second micro-operation prior to generation of said hazard data by said first micro-operation.