Patent ID: 7276414

Claim:
A method of forming a NAND memory array, comprising: forming a first dielectric layer on a first portion of a semiconductor substrate; forming a second dielectric layer on a second portion of the semiconductor substrate that is adjacent to the first portion of the semiconductor substrate so that the first and second dielectric layers are adjacent to each other, wherein the first dielectric layer is thicker than the second dielectric layer and wherein the second dielectric layer is formed independently of the first dielectric layer; forming a first gate stack on the first dielectric layer to form a drain select gate; forming a string of second gate stacks on the second dielectric layer to form a NAND string of floating-gate memory cells, wherein a first memory cell of the NAND string is adjacent the drain select gate; and forming a third gate stack on the second dielectric layer to form a source select gate adjacent a last memory cell of the NAND string.