Patent ID: 7034595

Claim:
A multi-phase clock signal generator comprising: a first inverter that is configured to invert an input clock signal to generate an inverted input clock signal that is delayed with respect to the input clock signal; a duty cycle compensation circuit that is configured to receive the input clock signal and the inverted input clock signal and to generate a first compensated input clock signal and a substantially complementary second compensated input clock signal having substantially the same duty cycle and substantially the same delay with respect to the input clock signal; a first logic circuit that is configured to generate a second delayed signal using the first compensated input clock signal and a first delayed signal, the first delayed signal having a substantially same phase as a phase of the input clock signal and having a first delay with respect to the input clock signal, the second delayed signal having a substantially inverted phase with respect to the input clock signal and having a second delay with respect to the input clock signal; a second logic circuit that is configured to generate the first delayed signal using the second compensated input clock signal and the second delayed signal; a second inverter that is configured to invert the second delayed signal to generate a first output clock signal; and a third inverter that is configured to invert the first delayed signal to generate a second output clock signal, wherein the duty cycle compensation circuit includes: an input buffer that provides the input clock signal; a first set of three cascade connected inverters coupled between an output terminal of the input buffer and an input terminal of the first logic circuit; a second set of three cascade connected inverters coupled between an output terminal of the first inverter and an input terminal of the second logic circuit, a first inverter of the second set of three cascade connected inverters having an output coupled to an input of a third inverter of the first set of three cascade connected inverters and a first inverter of the first set of three cascade connected inverters having an output coupled to an input of a third inverter of the second set of three cascade connected inverters; a fourth inverter coupled between an input terminal of the first set of three cascade connected inverters and an output terminal of the first set of three cascade connected inverters; and a fifth inverter coupled between an input terminal of the second set of three cascade connected inverters and an output terminal of the second set of three cascade connected inverters.