Patent ID: 7479816

Claim:
A delay locked loop (DLL) circuit generating a plurality of delayed signals from a reference signal, each of said plurality of delayed signals being delayed by a corresponding different delay magnitude in comparison to said reference signal, said DLL circuit comprising: a first plurality of delay elements connected in series, said first plurality of delay elements receiving said reference signal and generating said plurality of delayed signals on corresponding first plurality of output paths based on a strength of a control signal; a first control loop controlling said strength of said control signal to cause synchronization of edges of said reference signal with edges of the output of a last one of said first plurality of delay elements, said first control loop containing said first plurality of delay elements; and a second control loop also controlling said strength of said control signal to avoid synchronization of edges of the output of the last one of said plurality of delay elements with edges separated by multiple time periods of said reference signal, wherein said second control loop comprises a second plurality of delay elements generating a corresponding plurality of dummy signals, and wherein the plurality of delayed signals pass through at least some of the first plurality of delay elements and wherein the plurality of delayed signals do not pass through the second plurality of delay elements.