Patent ID: 8184762

Claim:
A digital phase lock loop circuit, comprising: a phase frequency detector configured to receive a reference frequency signal, a feedback signal derived from an output signal of the digital phase lock loop circuit, and a plurality of reference clock signals, the phase frequency detector configured to determine a phase difference between the feedback signal and the reference frequency signal to generate an error signal indicative of the phase difference; a numerically controlled oscillator configured to receive the error signal and generate a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal; and a first phase accuracy extender configured to receive the first oscillator output signal, the second oscillator output signal, and the plurality of reference clock signals, the first phase accuracy extender determining a first delay amount from the second oscillator output signal and delaying the first oscillator output signal by the first delay amount to generate a phase-enhanced output signal with edges aligned with one of the plurality of reference clock signals.