Patent ID: 7304385

Claim:
An integrated circuit comprising: an aluminum bonding pad defined on a stress-buffering dielectric layer having a thickness that is greater than 2000 angstroms; an aluminum active circuit layout, wherein said aluminum active circuit layout and said aluminum bonding pad are simultaneously defined on said stress-buffering dielectric layer; a damascened intermediate copper layer fabricated in an inter-metal dielectric (IMD) layer that is under said stress-buffering dielectric layer, and said damascened intermediate copper layer being disposed directly under said aluminum bonding pad and electrically connected to said aluminum bonding pad through a plurality of via plugs integrated with said aluminum bonding pad, wherein said stress-buffering dielectric layer is structurally denser than said IMD layer; active circuit components of said integrated circuit disposed directly under said damascened intermediate copper layer; and a passivation layer comprising silicon oxide, silicon nitride and polyimide covering said stress-buffering dielectric layer and partially covering said bondable metal pad.