Patent ID: 8040163

Claim:
A bootstrap circuit configured to employ first, second, third and fourth transistors having the same conduction type wherein: (A-1) a specific one of the source and drain areas of said first transistor and a specific one of the source and drain areas of said second transistor are directly electrically connected to each other by an output section of said bootstrap circuit; (A-2) the other one of said source and drain areas of said first transistor is directly electrically connected to a clock supply line which conveys a specific one of two clock signals having phases different from each other; (A-3) the gate electrode of said first transistor and a specific one of the source and drain areas of said third transistor are directly electrically connected to each other by a node section; (B-1) the other one of said source and drain areas of said second transistor is directly electrically connected to a first voltage supply line which conveys a first predetermined voltage; (C-1) the other one of said source and drain areas of said third transistor is directly electrically connected to a signal supply line which conveys an input signal supplied to said bootstrap circuit; (C-2) the gate electrode of said third transistor is directly electrically connected to a clock supply line which conveys the other one of said two clock signals; (E-1) a specific one of the source and drain areas of said fourth transistor is directly electrically connected by a junction point to the input side of an inverter circuit, the output side of which is directly electrically connected to said gate electrode of said second transistor; (E-2) the other one of said source and drain areas of said fourth transistor is directly electrically connected to said signal supply line; and (E-3) the gate electrode of said fourth transistor is directly electrically connected to said clock supply line which conveys said other one of the two clock signals.