Patent ID: 8659141

Claim:
A microelectronic assembly, comprising: a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces, respectively; and first and second microelectronic packages each having terminals mounted to the respective panel contacts, each microelectronic package including: a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; and a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function, the microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face, the terminals of the respective microelectronic package being exposed at the second surface of the substrate and configured for connecting the respective microelectronic package with at least one component external to the respective microelectronic package, the terminals of the respective microelectronic package being electrically connected with the substrate contacts of such microelectronic package and including first terminals disposed at locations within first and second parallel grids, each grid disposed on a respective side of an axis, the first terminals of each grid being configured to carry address information usable by circuitry within the respective microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element of the respective microelectronic package, the terminals of each microelectronic package further including second terminals arranged at positions within third and fourth parallel grids, the second terminals configured to carry second information, the second information being other than the information carried by the first terminals of such microelectronic package, the second information including data signals, wherein the first and second individual columns of each microelectronic package separate the third and fourth grids of such microelectronic package from one another, the first terminals having signal assignments, wherein the signal assignments of the first terminals in the first grid of each microelectronic package are symmetric about the axis with the signal assignments of the first terminals in the second grid of such microelectronic package, such that of the first terminals of the first grid of each microelectronic package that are configured to carry address information, each of such first terminals is configured to carry the same address information as a corresponding one of the first terminals of the second grid of such microelectronic package at a position symmetric about the axis with respect to such first terminal.