Patent ID: 7941685

Claim:
A delay locked loop for an FPGA architecture comprising: a reference clock node; a reference delay line having a reference clock input coupled to the reference clock node, the reference delay line also having a plurality of delay data inputs and an output, a feedback node; a feedback delay line having a feedback input coupled to the feedback node, a plurality of delay data inputs, and an output; a phase detector having first input, a second input, an increment output, a decrement output, and a hit output, the first input coupled to the output of the reference delay line, the second input coupled to the output of the feedback delay line; a control logic circuit having a first input coupled to the increment output of the phase detector, a second input coupled to the decrement output of the phase detector, and a third input coupled to the hit output of the phase detector, the control logic circuit having a plurality of delay data outputs; a programmable delay line having a reference clock input programmably coupled to one of the external clock I/O pad and the internal clock node, a plurality of delay data inputs coupled to the plurality of delay outputs of the control logic circuit, and an output; a clock tree having an input and an output, the input of the clock tree programmably coupled to the external clock I/O pad, the internal clock node, the out put of the programmable delay line, the output of the clock tree programmably connected to the feedback node; a flip-flop having a clock input coupled to the output of the clock tree, a data input, and a data output programmably coupled to the feedback node; a first I/O pad programmably coupled to the data output of the flip-flop; and a second I/O pad programmably coupled to the clock input of the flip flop and the input to the feedback delay line.