Patent ID: 8080823

Claim:
An IC chip package in which an IC chip is mounted to a package base material via an interposer, the IC chip comprising electrodes and first positioning members on a face thereof opposite the interposer, the first positioning members indicating a combining position for the IC chip and the interposer, the interposer comprising wiring conductor and second positioning members on a face thereof opposite the IC chip, the wiring conductor having IC chip contacts electrically connected to the electrodes and package base material contacts electrically connected to the package base material, the second positioning members being provided in pairs with the first positioning members, the first positioning members being provided in the same layer as the electrodes and formed of the same material as the electrodes, wherein the first and second positioning members differ in shape and are provided so that the first and second positioning members are separated by about a distance which is in a tolerable range as the combining position when viewed from a normal to the opposing faces of the IC chip and the interposer with the IC chip and the interposer being attached at an optimal position and wherein the distance separating the first and second positioning members has at least two values, one of the values indicating a limit for positional tolerable error and being greater than the other one of the values.