Patent ID: 7114135

Claim:
A method of routing test signals from test points of an integrated circuit (IC) to output locations comprising: designating a plurality of the test points in the IC, from which the test signals are generated; designating a hierarchy of a plurality of regional levels and sub-levels within the IC, each regional level and sub-level including a portion of the test points; distributing a hierarchy of a plurality of multiplexers across the IC, each multiplexer being local to one of the regional levels and sub-levels; connecting a lowest-level portion of the multiplexers to the test points to receive the test signals therefrom; connecting a mid-level portion of the multiplexers to other multiplexers to receive selected portions of the test signals therefrom; and connecting a highest-level one of the multiplexers to output locations to supply a final one of the selected portions of the test signals thereto.