Patent ID: 7485509

Claim:
A method for manufacturing a semiconductor device including a lateral type field effect transistor and a vertical type junction field effect transistor, which are integrated in a silicon carbide substrate, the method comprising the steps of: preparing a first layer made of silicon carbide and heavily doped with a first impurity having a first type conductivity, the first layer being to be a drain of the junction field effect transistor; forming a second layer on the first layer, the second layer being made of silicon carbide and lightly doped with the first impurity and to be a channel of the junction field effect transistor; forming a second impurity diffusion region heavily doped with a second impurity having a second type conductivity, disposed in a predetermined surface portion of the second layer, and being to be a gate of the junction field effect transistor; forming a third layer made of silicon carbide, moderately doped with the first impurity, and disposed on both of the second layer and the second impurity diffusion region; and forming a first impurity diffusion region heavily doped with the first impurity, disposed in each of first, second, and third surface portions of the third layer, and being to be a source of the junction field effect transistor and a source and drain of the lateral type field effect transistor, respectively.