Patent ID: 7107190

Claim:
A circuit designing apparatus comprising: a logic verification unit configured to input a plurality of test vectors necessary for a logic verification to a circuit description defining a structure and a specification of a circuit to be designed, to compare an output signal of the circuit description with an expected value of the output signal, and to judge the validity of the circuit description in accordance with a result of the comparison; a profile information generating unit configured to detect information about a plurality of logic cones in the circuit description to be activated by the test vectors during the logic verification, for each test vector, and to generate a profile information relating the test vector to the logic cones activated by the test vector; a circuit changing unit configured to change the circuit description after the logic verification and to generate a changed circuit description; a logic cone specifying unit configured to specify changed logic cones of the changed circuit description, based on a result of a formal verification; and a test vector classifying unit configured to classify the test vectors into test vectors that activate the changed logic cones and test vectors that do not activate the changed logic cones, by searching for the test vectors related to the changed logic cones in the profile information, wherein the logic verification unit inputs the test vectors that activate the changed logic cones into the changed circuit description, compares an output signal of the changed circuit description with an expected value of the output signal, and judges the validity of the changed circuit description in accordance with a result of the comparison.