Patent ID: 6910198

Claim:
For an electronic-design-automation placer that uses a set of partitioning lines, that define a plurality of slots, to partition an integrated-circuit (“IC”) layout region into a plurality of sub-regions corresponding to said slots, a method of pre-computing placement costs for multiple wiring models, the method comprising: a) for each combination of said slots, identifying at least one connection graph that is based on a first wiring model and that represents the topology of interconnect lines necessary for connecting the combination of said slots according to the first wiring model; b) for each combination of said slots, identifying at least one connection graph that is based on a second wiring model and that represents the topology of interconnect lines necessary for connecting the combination of said slots according to the second wiring model; c) computing an attribute of each identified connection graph; and d) storing the computed attributes in a storage structure.