Patent ID: 7366051

Claim:
A system for controlling memory access, comprising: memory circuitry having a plurality of memory cells disposed in a two dimensional array of rows and columns of such memory cells and a first word line that is connected to each row of memory cells; a high voltage source; a low voltage source; and word line driver circuitry coupled to said high and low voltage sources and to said first word line, wherein said word line driver circuitry comprises: a first transistor coupled to said high voltage source and to said first word line, a second transistor coupled to said low voltage source and to said first transistor, and high impedance circuitry coupled to said first and second transistors, and to said low voltage source, and wherein said word line driver circuitry operative to selectively couple: said first word line to said high voltage source in response to a first signal, said first word line to said low voltage source in response to a second signal, and said first word line to said low voltage source through said high impedance circuitry in response to a third signal, wherein said third signal activates said first transistor and deactivates said second transistor such that said high impedance circuitry limits current flow in said first word line.