Patent ID: 8350740

Claim:
An A/D conversion circuit comprising: an input terminal configured to receive an input analog voltage; a first sampling capacitor configured to have one end connected to a first power source; a first sampling switch configured to have one end electrically connected to the input terminal and an other end electrically connected to an other end of the first sampling capacitor to control connection and disconnection between the input terminal and the other end of the first sampling capacitor in accordance with a first sampling clock, the connection being performed to track the input analog voltage to the first sampling capacitor and the disconnection being performed to hold a voltage of the first sampling capacitor; a buffer circuit configured to have a buffer input terminal electrically connected to the other end of the first sampling capacitor and a buffer output terminal, the buffer circuit operating between the first power source and a second power source so that a track/hold voltage, which is the voltage of the first sampling capacitor, received by the buffer input terminal is buffered and outputted from the buffer output terminal; a second sampling capacitor configured to have one end connected to the first power source; a second sampling switch configured to have one end electrically connected to the buffer output terminal of the buffer circuit and the other end electrically connected to an other end of the second sampling capacitor to control connection and disconnection between the buffer output terminal and the other end of an second sampling capacitor in accordance with a second sampling clock, the connection being performed to sample a voltage of the buffer output terminal to the second sampling capacitor and the disconnection being performed to hold a voltage of the second sampling capacitor; a first converter configured to read a sample/hold voltage, which is the voltage of the second sampling capacitor after being held, and convert the sample/hold voltage into a digital signal; a first reset switch configured to reset the first sampling capacitor by short-circuiting the other end of the first sampling capacitor to the first power source or the second power source in a period after the voltage of the second sampling capacitor is held and before the connection is performed by the first sampling switch; and a second reset switch configured to reset the second sampling capacitor by short-circuiting the other end of the second sampling capacitor to the first power source or the second power source in a period after the conversion by the first converter is performed and before the connection is performed by the first sampling switch.