Patent ID: 7225306

Claim:
A method of generating an address sequence, the method comprising: decomposing a Forney's (P,D,m) interleaver with delays f(i)=(im mod P)D, 0≦i<P, into a concatenation of a multiplexed interleaver with period P and delays f M (i)=q(i)P, and a block interleaver with period P and delays f B (i)=r(i)−i+P, wherein q(i) and r(i) are defined by i+f(i)=q(i)P+r(i), 0≦r(i)<P, and further wherein P is an arbitrary period, D is an arbitrary delay parameter and m is an integer greater than zero and less than P and that satisfies gcd (P,m)=1 and gcd (P,1+mD)=1; generating A+1 multiplexed interleaver addresses, wherein A is the average delay of the (P,D,m) interleaver and equals (P−1)D/2; generating 2P block interleaver addresses; generating at least one two-dimensional address array from the multiplexed interleaver addresses and the block interleaver addresse; and controlling read and write addresses associated with a sole RAM in response to the at least one two-dimensional address array such that symbols are written into and read from the sole RAM according to a periodic sequence defined by the two-dimensional address array.