Patent ID: 7078762

Claim:
A semiconductor memory device, comprising: at least one assist gate formed through a first insulator on a main surface of a first conductive type semiconductor substrate and extended in a first direction of said main surface; a plurality of word lines formed on said assist gates through a second insulator and extended in a second direction that is substantially perpendicular to said first direction; and a plurality of memory cells disposed at nodes of respective ones of said assist gates and said plurality of word lines, wherein said memory device has a memory array structure in which a second conductive type inversion layer is formed electrically on a surface of said semiconductor substrate located in the lower part of said assist gates, wherein said inversion layer comprises a wiring for connection between adjacent ones of said plurality of memory cells when a voltage is applied to said assist gates, wherein adjacent ones of said plurality of word lines are separated electrically from each other by a side wall spacer, wherein said side wall spacer comprises an insulator formed at sides at least one of even-numbered and odd-numbered ones of said plurality of word lines, and wherein the space between adjacent ones of said plurality of word lines is less than or about equal to ½ of a width of said word lines.