Patent ID: 7764568

Claim:
Address decoding apparatus for a random access memory having a plurality of memory cells, the apparatus receiving a plurality of address signals and selecting one of the plurality of memory cells based on the address signals and comprising: a plurality of switch nodes, wherein each switch node has an input and two outputs and three states including a ready state, a 0 state and a 1 state, and wherein, in the ready state, the switch node receives an address signal at the input and, based on a value of the received address signal, enters one of the 0 state and the 1 state, whereupon further signals received at the input are transferred to one of the two outputs based on the switch node state; and a plurality of links connecting the plurality of switch nodes into a binary tree structure having a root node for sequentially receiving each of the plurality of address signals and a plurality of leaf nodes, each of which is associated with two of the memory cells.