Patent ID: 8306042

Claim:
A multiprocessor architecture employing deterministic packet routing, the architecture comprising: a plurality of processors arranged in an array, each processor residing at a node of the array and operable to route message packets across the array; a plurality of memory controllers, each memory controller being directly connected to at least one of the plurality of processors and to external memory; a plurality of router switches, each router switch being coupled to one of the nodes in the array, each router switch being connected to the processor of that node, and operable to direct the message packets to an adjacent node in the array in a class-based deterministic packet routing process; wherein each router switch evaluates a received message packet to determine if it is a memory request packet or a memory reply packet, if the received message packet is a memory request packet issued from a source processor of the plurality of processors to a destination memory controller of the plurality of memory controllers, then the received memory packet is passed through selected nodes from the source processor to the destination memory controller via XY or YX routing, where X and Y are the routing directions from the selected nodes of the array, and if the received message packet is a memory reply packet issued from a source memory controller of the plurality of memory controllers to a destination processor of the plurality of processors, then the received memory packet is passed through the selected nodes from the source memory controller to the destination processor via YX or XY routing, so that if the memory request packet is passed through the selected nodes via XY routing then the memory reply packet is passed through the selected nodes via YX routing, and if the memory request packet is passed through the selected nodes via YX routing then the memory reply packet is passed through the selected nodes via XY routing.