Patent ID: 7678692

Claim:
A fabrication method for a damascene bit line contact plug, comprising the steps of: providing a semiconductor substrate having a first gate conductive structure, a second gate conductive structure, a third gate conductive structure and a fourth gate conductive structure, in which the second gate conductive structure and the third gate conductive structure are formed within an active area; forming a first conductive layer to fill the space between the second gate conductive structure and the third gate conductive structure; forming a first liner on the substrate to cover the first gate conductive structure, the second gate conductive structure, the third gate conductive structure and the fourth gate conductive structure and forming a second liner on the substrate to cover at least the first conductive layer; forming a first inter-layer dielectric to fill the space between the first gate conductive structure and the second gate conductive structure, and fill the space between the third gate conductive structure and the fourth gate conductive structure; forming a second inter-layer dielectric on the first inter-layer dielectric; forming a bit line contact hole, a gate contact hole and a source contact hole, in which the bit line contact hole exposes the top of the first conductive layer, the gate contact hole exposes the top of the first gate conductive structure, and the source contact hole exposes the substrate laterally adjacent to the fourth gate conductive structure; and forming a second conductive layer to fill the bit line contact hole, the gate contact hole and the source contact hole, in which the second conductive layer formed in the bit line contact hole is electrically connected to the first conductive layer to serve as a damascene bit line contact plug, wherein the formation of the bit line contact hole, the gate contact hole and the source contact hole comprises the steps of: forming the first inter-layer dielectric layer on the substrate to cover the second liner; performing a chemical mechanical polishing process on the first inter-layer dielectric, in which the top of the first inter-layer dielectric is leveled off with the top of the second liner; forming the second inter-layer dielectric to cover the first inter-layer dielectric and the second liner; providing a third photoresist layer having a first opening corresponding to the bit line contact hole, a second opening corresponding to the gate contact hole, and a third opening corresponding to the source contact hole; and removing the second inter-layer dielectric, the first inter-layer dielectric and the second liner exposed within the first opening, the second opening, and the third opening, thus forming the bit line contact hole, the gate contact hole and the source contact hole.