Patent ID: 7454589

Claim:
An interface circuit that is interposed between a synchronous circuit that conducts a data access in synchronization with an active edge of a clock signal and an asynchronous circuit that conducts a read access or a write access in an active period of a read control signal or a write control signal, and controls the synchronous circuit according to the read control signal or the write control signal outputted from the asynchronous circuit, the interface circuit comprising: a clock signal generating section that generates the clock signal having termination edges of the respective active periods in the read control signal and the write control signal as the active edges; a subsequent cycle address generating section that generates a present cycle address that is an address corresponding to the access from the asynchronous circuit, and a subsequent cycle address that is an address of a subsequent access cycle of the present cycle address in sequential access cycles to the synchronous circuit; and a first address selecting section that selects any one of the subsequent cycle address and the present cycle address according to a command from the asynchronous circuit as an address of the synchronous circuit, wherein the first address selecting section selectively outputs the present cycle address when the access to the synchronous circuit is the write access, and selectively outputs the subsequent cycle address when the access to the synchronous circuit is the read access.