Patent ID: 8819356

Claim:
A memory module comprising: a first rank of memory circuits comprising a first memory circuit; a second rank of memory circuits comprising a second memory circuit; an interface circuit; a first data bus that connects to the first memory circuit, the second memory circuit, and the interface circuit, the first data bus having a first data bus width; and a second data bus that connects to the interface circuit and a memory controller, the second data bus having a second data bus width, wherein the second data bus width is narrower than the first data bus width; wherein the interface circuit is operable to: receive a first read command from the memory controller to read first data stored in the first memory circuit; after receiving the first read command, receive a second read command from the memory controller to read second data that is stored in the second memory circuit; enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus; read the first data from the first memory circuit across the first data bus; transmit the first data to the memory controller across the second data bus; insert idle clock cycles, and during the idle clock cycles: (i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and (ii) enable a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus; read the second data from the second memory circuit across the first data bus; and transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data.