Patent ID: 7456447

Claim:
A semiconductor integrated circuit device comprising: a first wiring trace routed along a well of a first conductivity type in a substrate; a second wiring trace routed along a well of a second conductivity type in the substrate; a third wiring trace disposed in the same layer as said first and second wiring traces, routed in a direction that intersects said first and second wiring traces and electrically insulated from said first and second wiring traces; a first diffusion layer of the second conductivity type disposed in the well of the first conductivity type in the vicinity of a portion where the wiring directions of said first and third wiring traces intersect, and electrically connected to said first wiring trace through a contact; and a second diffusion layer of the first conductivity type disposed in the well of the second conductivity type in the vicinity of a portion where the wiring directions of said second and third wiring traces intersect, and electrically connected to said second wiring trace through a contact; wherein said first diffusion layer is used as a wiring route regarding said first wiring trace, and said second diffusion layer is used as a wiring route regarding said second wiring trace.