Patent ID: 7928503

Claim:
A memory cell, comprising: a pair of source/drain regions extending into a semiconductor substrate, the source/drain regions being spaced from one another by a channel region; a first planar surface extending across the source/drain regions and the channel region; a gate dielectric along the first planar surface, the gate dielectric having a planar upper surface which is directly over the first planar surface, the gate dielectric being a first dielectric material; a plurality of nanosized islands of charge trapping material over and directly against the planar upper surface of the gate dielectric, adjacent islands being spaced from one another by gaps; the nanosized islands forming only one layer within the memory cell, an entirety of said one layer being directly against the planar upper surface of the gate dielectric; said one layer extending entirely from one of the source/drain regions of said pair to the other of the source/drain regions of said pair; second dielectric material over and between the nanosized islands, the second dielectric material forming a container shape having an upwardly opening trough therein; and control gate material within the trough.