Patent ID: 7219292

Claim:
A method for a variable-length communications system, wherein messages to be transmitted are divided into variable-length message blocks and the system includes a convolutional encoder of a memory order j, wherein j is an integer, the method comprising: providing a cyclic redundancy check (CRC) generating polynomial g l (x), wherein l is an integer and is the order of g l (x); providing a binary flip polynomial f l (x) having an order of l−1, wherein f l (x)=f l−1 x l−1 +f l−2 x l−2 + . . . +f 0 ; and encoding a message block M of a message to be transmitted, wherein M includes k binary bits, m k−1 , m k−2 , . . . , m 0 , and wherein encoding M includes generating a parity check bit stream P, wherein P includes l parity check bits, p l−1 , p l−2 , . . . , p 0 , such that g l (x)|(x l M(x)+P(x)), wherein M(x)=m k−1 x k−1 m k−2 x k−2 + . . . +m 0 , and P(x)=p l−1 x l−1 +p l−2 x l−2 + . . . +p 0 , flipping the parity check bit stream P to generate a flipped parity check bit stream P including l flipped parity check bits p l−1 , p l−2 , . . . , p 0 , such that p l−1 =p l−1 +f l−1 , p l−2 =p l−2 +f l−2 , . . . , p 0 =p 0 +f 0 , wherein “+” is a modulo-2 addition operation, appending the flipped parity check bit stream P to the end of message block M to create a concatenated bit stream C, such that C includes k+l bits, m k−1 , m k−2 , . . . , m 0 , p l−1 , p l−2 , . . . , p 0 , and convolutionally encoding the concatenated bit stream C to generate a code word D.