Patent ID: 7235439

Claim:
A method of forming a MOS-controllable power semiconductor device for use in an integrated circuit, the device having an active region that includes a drift region, the method comprising: forming, in a layer provided on a semiconductor substrate, a power semiconductor device having an active region that includes a drift region; removing at least a portion of the semiconductor substrate below at least a portion of the drift region such that said at least a portion of the drift region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed, the membrane having opposed top and bottom surfaces, the bottom surface of the membrane not having a semiconductor substrate positioned adjacent thereto; and, connecting at least one electrical terminal directly or indirectly to the top surface of the membrane and at least one other electrical terminal directly or indirectly to the bottom surface of the membrane to allow a voltage to be applied vertically across the drift region.