Patent ID: 6905935

Claim:
A method for fabricating a vertical bipolar junction transistor on a semiconductor wafer including a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region, the method comprising: forming a third doping region of the first conductivity type in an upper portion of the second doping region; forming a shielding layer on the surface of the semiconductor wafer; removing a portion of the shielding layer to form an opening within the shielding layer to expose a portion of the third doping region; forming a doping layer of the second conductivity type on a surface of the third doping region; and performing a self-aligned silicidation process to form a silicide layer on the surfaces of the first doping region, the second doping region, the third doping region, and the doping layer, the silicide layer functioning as a contact region of the vertical bipolar junction transistor.