Patent ID: 8401138

Claim:
A serial data receiver circuit apparatus configured to receive serial data including communication data delimited by a first bit length, and control data delimited by the first bit length, the circuit apparatus comprising: a serial/parallel converter to receive the serial data, and convert the serial data into parallel data of a second bit length that is smaller than the first bit length; a plurality of registers whose bit widths are substantially equal to the second bit length, the plurality of registers to hold a plurality of parallel data converted by the serial/parallel converter in the order that the data was input; a detector to detect control data included in the data stored in the plurality of registers, and detect a delimiter position in the received serial data, the control data indicating whether the data is to be written to a clock transfer buffer; a detected position hold circuit to generate, based on information regarding the data delimiter position obtained from detection results of the detector, a select signal to select data included in the parallel data stored in the plurality of registers, the data is selected in units of the second bit length starting from the data delimiter position; and a selector to select, based on the select signal generated by the detected position hold circuit, data in units of the second bit length from among the data stored in the plurality of registers, the data is selected based on the detected delimiter position.