Patent ID: 7752353

Claim:
A bus architecture for coupling a plurality of client devices with a host computer, the bus architecture suitably configured for enabling the host computer to efficiently identify which of the plurality of client devices is requesting an interrupt, the bus architecture comprising: at least one signal line; and a plurality of client devices wherein each of the client devices includes: a number of I/O pins selected ones of which are connected to the at least one signal line, and no more than two interrupt pins, the interrupt pins including a first and a second interrupt pin wherein all but a first and a last of the plurality of client devices are hardwired to one another in a daisy chain arrangement by way of the first and the second interrupt pin separate from the at least one signal line, wherein the first client device is hardwired to the daisy chain arrangement only by way of the second interrupt pin and wherein the first interrupt pin of the first client device is connected to a node external to the daisy chain and wherein the last client device is hardwired to the daisy chain only by way of a first interrupt pin and wherein a second interrupt pin of the last of the plurality of client devices is connected to a host computer by way of an interrupt signal line separate from the at least one signal line, wherein when a requesting client device requests an interrupt, the host computer locates the requesting device using a binary search such that at least one of the plurality of client devices is not accessed by the host device during the binary search.