Patent ID: 8755232

Claim:
A memory comprising: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by: isolating a first semiconductor body region of the semiconductor body on a first side of the selected word line, and applying a pass voltage to word lines on the first side of the selected word line during a program interval, to boost the first semiconductor body region by capacitive coupling to a boosted voltage; applying a program voltage to the selected word line during the program interval; biasing a second semiconductor body region on a second side of the selected word line during the program interval, to a reference voltage level; and applying a switching voltage to a word line adjacent the selected word line, the switching voltage having a first stage and a second stage during the program interval, to isolate the memory cell corresponding to the selected word line from the reference voltage level during the first stage, and to couple the reference voltage level to the selected memory cell during the second stage.