Patent ID: 7822111

Claim:
A receiving apparatus, comprising: a clock generating unit generating a plurality of internal clock signals based on a received external clock signal; an equalization receiving unit receiving the plurality of internal clock signals, a reference signal and a data signal, the equalization receiving unit determining an offset value and an equalization coefficient in an initial setting mode and adjusting the received data signal based on the determined offset value and equalization coefficient; and a finite state machine (FSM) unit generating a first controlling signal that adjusts a phase changing value generated by the clock generating unit, a second controlling signal for adjusting the equalization coefficient and a third controlling signal for adjusting the offset value, the first, second and third controlling signals generated in response to an output signal of the equalization receiving unit, wherein a reference signal input port receives the reference signal and is connected with a data signal input port that receives the data signal in response to an offset correcting signal, the FSM unit generates the third controlling signal for controlling the output of the equalization receiving unit, the offset value is determined based on the third controlling signal generated by the FSM unit in the initial setting mode, the equalization receiving unit includes a signal input unit including the data signal input port and the reference signal input port, and the signal input unit cuts off the data signal received at the data signal input port in response to the offset correcting signal in the initial setting mode.