Patent ID: 7986567

Claim:
A buffering system for reading data from embedded non-Flash vertically stacked non-volatile memory, comprising: a silicon substrate including a logic layer having circuitry fabricated on the logic layer, the circuitry including a NOR-type interface including a buffer controller, the NOR-type interface electrically coupled with a plurality of control signals, an address register electrically coupled with the NOR-type interface, an address decoder operative to receive an address from the address register and to decode the address into a decode plane signal and a decoded array line signal, an array line driver electrically coupled with the decoded array line signal, a partition selector electrically coupled with the decode plane signal and an access unit decode signal generated by the address register, and a multiplexor circuit having a read output electrically coupled with the NOR-type interface and an input electrically coupled with a control signal from the NOR-type interface; a plurality of read buffers, each read buffer electrically coupled with the partition selector and a control signal from the NOR-type interface, each read buffer having an output electrically coupled with the multiplexor circuit; and a plurality of memory planes in direct contact with and fabricated directly above the silicon substrate, each memory plane including at least one re-writeable non-volatile two-terminal cross-point memory array embedded therein and having a plurality of first conductive array lines electrically coupled with the array line driver and a plurality of second conductive array lines electrically coupled with the partition selector.