Patent ID: 7555632

Claim:
A superscalar processing system for executing instructions, comprising: an instruction fetch unit configured to fetch a plurality of instructions from an instruction store, said plurality of instructions including more than two instructions and having a prescribed program order; a register file configured to store register data corresponding to said plurality of instructions; an instruction execution unit configured to select a subset of said plurality of instructions for execution, said instruction execution unit being configured to select said subset of said plurality of instructions from among any combination of two or more of said plurality of instructions, said instruction execution unit comprising a plurality of functional units, each of said plurality of functional units configured to execute a corresponding one of said subset of said plurality of instructions and to generate results data therefrom; a register file output bus configured to concurrently transfer register data associated with said subset of said plurality of instructions from said register file to said plurality of functional units for use in execution of said subset of said plurality of instructions; and an output bus configured to concurrently distribute said results data to said register file, wherein said register file comprises a temporary buffer and a register array; and wherein said register file output bus is configured to store results data in said temporary buffer if said results data is associated with an instruction that is not retireable upon completion and to store results data in said register array if said results data is associated with an instruction that is retireable upon completion.