Patent ID: 8427893

Claim:
A redundancy memory cell access circuit comprising: a first control unit that compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison during a test operation; at least one fuse unit that generates the unprogrammed fuse signal that represents an address of a redundancy memory cell during the test operation, and wherein the at least one fuse unit generates a programmed fuse signal that represents an address of a defective memory cell during a normal operation, and wherein the unprogrammed fuse signal is different from the programmed fuse signal; and an accessing unit that allows access to said redundancy memory cell corresponding to the address signal when the first redundancy enable signal is activated from the unprogrammed fuse signal being equal to the address signal for testing of the redundancy memory cell without the redundancy memory cell being used to replace any defective memory cell during the test operation, wherein said accessing unit substitutes said defective memory cell with said redundancy memory cell when said programmed fuse signal is equal to the address signal during the normal operation.