Patent ID: 7680976

Claim:
An integrated circuit having an embedded multiple time programmable memory, comprising: a processing core for executing stored instructions; a data memory for storing data during operation of said processing core, said data memory occupying a data memory address space of said processing core; a non-volatile memory for storing program instructions for use by said processing core during operation thereof, wherein at least portions of said stored program instructions are executed from non-volatile memory, said non-volatile memory including: a plurality of blocks of non-volatile memory, each of which can be written to once and read from many times and each having a size that is equal to or less than a program memory address space addressable by said processing core for output of data therefrom, and a reserve storage location for storing a status word defining the one of said plurality of blocks addressable by said processing core, said status word operable to be changed in response to external signals when another of said plurality of blocks is to be selected, such that once another of said plurality of blocks is selected, said status word cannot indicate as addressable by said processing core a prior one of said plurality of blocks that was defined by said status word as being previously addressable by said processing core; and an access device for enabling a program memory address within the program memory address space of said processing core to address a corresponding addressable location within the one of said plurality of blocks indicated by said status word as being accessible by said processing core.