Patent ID: 8854901

Claim:
A circuit, comprising: a memory cell array including: a first section having a plurality of memory cells and a wordline for each row of memory cells in said first section; and a second section having a plurality of read timer cells arranged in a column, each read timer cell including a reference wordline, a reference true bitline, an internal true node, an access transistor coupled between said internal true node and said reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node, wherein the reference true bitline is shared by the column of read timer cells; a reference row decoder circuit coupled to the second section of the memory cell array, said reference row decoder circuit including a reference wordline driver circuit having an output coupled to drive the reference wordline; and means for lowering a gate to source voltage of timer cell transistors by decreasing a higher voltage level corresponding to logic high that is applied on said reference wordline to actuate said at least one of said access transistor and pull-down transistor during a read operation of memory cells in the first section.