Patent ID: 8554943

Claim:
A switch, comprising: (A) a low latency packet processor for processing low latency packets; (B) a high bandwidth packet processor for processing high bandwidth packets; and (C) a plurality of input/output sections, each one of the input/output sections comprising: (i) an input section, comprising: (a) a decode logic for receiving at a common port both low latency packets and high bandwidth packets; and (b) wherein the decode logic detects whether each one of the received packets at the common port is a low latency packet or a high bandwidth packet and wherein the decode logic routes the received packets to either the low latency processor or to the high bandwidth processor selectively in accordance with whether the received packet is detected as a low latency packet or a high bandwidth packet; and (ii) an output section having a pair of inputs, one of the pair of inputs being coupled to an output of the low latency packet processor and the other one of the pair of inputs being coupled to an output of the high bandwidth packet processor; and (iii) wherein the output section: (a) interrupts transmission the high bandwidth packets processed by the high bandwidth processor for transmission of the low latency packets processed by the low latency processor; (b) inserts a start of low latency packet delimiter; (c) transmits the low latency packet: (d) inserts an end of low latency packet delimiter; (e) and then continues the interrupted transmission of the high bandwidth packet after transmission of the low latency packet to provide at a common output of the output section both the transmitted high bandwidth packets and the transmitted low latency packets.