Patent ID: 7312634

Claim:
An exclusive-OR circuit comprising: a NAND gate configured to receive a plurality of input signals; a NOR gate configured to receive the plurality of input signals; a switch configured to couple an output signal of the NAND gate to an output node when an output signal of the NOR gate is at a first logic level; and a pull-down circuit configured to pull down the output node when the output signal of the NOR gate is at a second logic level different than the first logic level; wherein the NAND gate comprises, a plurality of PMOS transistors connected in parallel between a power supply voltage and an output port of the NAND gate, wherein gates of the plurality of PMOS transistors respectively receive the plurality of input signals, and a plurality of NMOS transistors connected in series between the output port of the NAND gate and a ground voltage, wherein gates of the plurality of NMOS transistors respectively receive the plurality of input signals, wherein an electrical path between the plurality of PMOS transistors and the plurality of NMOS transistors of the NAND gate is free of the switch and the output node.