Patent ID: 7917667

Claim:
An Apparatus, comprising: a processor operable to request a processor operation Direct Memory Access (“DMA”) communication task; at least one data transfer device operable to request a defined-content DMA communication task; a memory operable to enable DMA communication with the processor and the at least one data transfer device over at least one data bus, the DMA communication having a bandwidth; and an arbitration system operating to allocate fractional concurrent shares of the DMA communication bandwidth such that the processor operation DMA communication task and the at least one defined-content DMA communication task access their respective fractional concurrent shares of the DMA communication bandwidth at the same time wherein the arbitration system includes a priority level determination circuit operable to assign one of a plurality of priority levels to each said defined-content DMA communication task, and the priority level determination circuit comprises: (a) a circuit for updating an operating time margin for one said defined-content DMA communication task; (b) a circuit for updating a remaining processing time for said defined-content DMA communication task; and (c) a priority level calculation circuit for determining a priority level based on outputs of the circuits of (a) and (b); and wherein the apparatus is operable to: determine a disparity between an initially estimated computationally expensive processing time and an actual processing time for the defined-content DMA communication task; add the determined disparity to the updated operating time margin; subtract the determined disparity from the updated remaining processing time; and update the priority level for the defined-content DMA communication task based on the adding and subtracting steps.