Patent ID: 7355910

Claim:
A semiconductor memory device including two spare memory cell rows per memory cell array and at least one defective memory cell row; wherein when the semiconductor memory device has two defective memory cell rows including a first defective memory cell row and a second defective memory cell row, the first defective memory cell row and the second defective memory cell row being replaced with a first spare memory cell row or a second spare memory cell row by cutting out an upper fuse or a lower fuse corresponding to the position of the defective memory cell rows, the first defective memory cell row positioned at a lower portion of the memory cell array being replaced with the first spare memory cell row by cutting out the upper fuse corresponding to the first defective memory cell row, and the second defective memory cell row positioned at an upper portion of the memory cell array being replaced with the second spare memory cell row by cutting out the lower fuse corresponding to the second defective memory cell row.