Patent ID: 7821436

Claim:
A method for reducing power dissipated in an analog to digital converter (ADC) comprised of a plurality of clock phases, each clock phase comprising an amplifying phase and a sample-and-hold phase for respectively amplifying and sampling an analog input signal, comprising the steps of: (a) receiving, in a current amplifying phase, a residue value output from a residue amplifier in a previous clock phase; and (b) amplifying said residue value during said current amplifying phase, thereby eliminating a load effect on said residue amplifier; (c) driving a large load on the residue amplifier and increasing a feedback factor in the sample-and-hold phase and eliminating the sampling capacitance of a previous stage during a sample-and-hold phase, thereby eliminating a low feedback factor; and (d) outputting the residue value from the residue amplifier at the termination of a sample-and-hold phase, the residue value being derived from said sampled analog input signal.