Patent ID: 7755964

Claim:
An integrated circuit comprising: a memory array comprising a plurality of rows and a plurality of columns of memory cells, a column of dummy cells, and a dummy word line, the dummy word line comprising at least one dummy cell; a plurality of sense amplifiers coupled to a plurality of bit lines for the plurality of columns of memory cells; and a timing control circuit configured to generate enable signals for the plurality of sense amplifiers, the enable signals having a configurable and selectable delay determined based in part on the column of dummy cells where the configurable and selectable delay is a fractional delay less than a delay provided by the at least one dummy cell; a plurality of word line drivers configured to drive a plurality of word lines for the plurality of rows of memory cells; and a dummy word line driver configured to drive the dummy word line for one or more dummy cells in the column of dummy cells, wherein the dummy word line driver is matched in delay to each of the plurality of word line drivers based on a pre-decoded signal generated by a decoder.