Patent ID: 8664053

Claim:
A method of manufacturing a semiconductor device provided with a MISFET, the method comprising: (a) a step of preparing a semiconductor substrate; (b) a step of forming a second material film on the semiconductor substrate; (c) a step of patterning the second material film to form a second material film pattern; (d) a step of forming a sidewall insulating film made of silicon nitride or silicon oxynitride on a sidewall of the second material film pattern; (e) a step of etching the semiconductor substrate with the sidewall insulating film and the second material film pattern as an etching mask to form a trench for device isolation in the semiconductor substrate; (f) a step of forming a silicon oxide film on the semiconductor substrate so as to fill the trench for device isolation and cover the second material film pattern and the sidewall insulating film; (g) a step of polishing the silicon oxide film until the second material film pattern is exposed, thereby forming a device isolation region which is made of the silicon oxide film embedded in the trench and whose upper portion is protruded from the semiconductor substrate; (h) after the step (g), a step of removing the second material film pattern; (i) after the step (h), a step of forming a first insulating film which is for a gate insulating film of the MISFET and contains hafnium, oxygen and a first element as main components on a region of the semiconductor substrate which is surrounded by the device isolation region and is not covered with the sidewall insulating film; (j) a step of forming a metal film for forming a metal gate electrode of the MISFET on the first insulating film; (k) a step of forming a silicon film on the metal film; and (l) a step of patterning the silicon film and the metal film to form the metal gate electrode for the MISFET, wherein, when the MISFET is an n-channel MISFET, the first element is an element belonging to any of Group 1, Group 2 and Group 3, when the MISFET is a p-channel MISFET, the first element is any of Al, Ti and Ta, wherein, at the step (i), the first insulating film is also formed over the device isolation region and the sidewall insulating film, wherein, at the step (l), the metal gate electrode is also formed over the device isolation region and the sidewall insulating film via the first insulating film, and wherein, after the step (l), in a gate width direction of the MISFET, the first insulating film and the metal gate electrode are above the device isolation region and the sidewall insulating film.