Patent ID: 8909973

Claim:
A timer unit, comprising: a first selector that receives a fixed value and a first enable signal; a second selector that receives the fixed value and a count cycle signal; a third selector that receives an output signal of the second selector, the count cycle signal, and a second enable signal; a first counter circuit that starts counting in response to an output signal of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value; a second counter circuit that starts counting in response to an output signal of the third selector, and that generates a second counter circuit output signal indicating that a count value approaches a predetermined value; a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal; and a second output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a second output signal.