Patent ID: 7714626

Claim:
An apparatus having improved pulse width modulation (PWM) frequency resolution, said apparatus comprising: a period register for storing a pulse width modulation (PWM) period value, the period register having m bits of which n bits are least significant; a delay adder coupled to the n least significant bits of the period register; a delay register coupled to the delay adder, wherein a value from the delay adder is stored in the delay register each time the delay register is clocked; a plus one effective period adder coupled to the period register and a carry-out from the delay adder, wherein when the carry-out from the delay adder is at a first logic level, one (1) is added to the PWM period value from the period register; a period comparator coupled to the plus one effective period adder and receiving the PWM period value when the carry-out from the delay adder is at a second logic level and the PWM period value plus one when the carry-out from the delay adder is at the first logic level; a clock counter for counting clock pulses from a clock source, the counter being coupled to the period comparator, wherein the period comparator compares a clock count from the clock counter with the PWM period value or the PWM period value plus one from the plus one effective period adder, whereby the period comparator resets the clock counter and clocks the delay register when the clock count is greater than or equal to the PWM period value or the PWM period value plus one; a duty cycle register for storing a PWM duty cycle; a duty cycle comparator coupled to the clock counter and the duty cycle register, wherein the duty cycle comparator compares the PWM duty cycle to the clock count and whenever the clock count is less than or equal to the PWM duty cycle a first logic level is generated from an output of the duty cycle comparator, otherwise a second logic level is generated therefrom, thereby generating a first PWM signal; a plurality of multi-tap delay elements, the plurality of multi-tap delay elements are coupled in series to produce a plurality of time delays of the first PWM signal from the duty cycle comparator, a first one of the plurality of multi-tap delay elements being coupled to the output of the duty cycle comparator; and a multiplexer coupled to the plurality of multi-tap delay elements, the output of the duty cycle comparator and an output of the delay adder, wherein the output of the delay adder controls selection of which one of the plurality of multi-tap delay elements is coupled to an output of the multiplexer to produce a second PWM signal, whereby the second PWM signal has a PWM period resolution substantially equal to a time delay of a single one of the plurality of multi-tap delay elements.