Patent ID: 7032077

Claim:
A memory architecture, comprising: at least one processor having a storage area; a cache memory in communication with the at least one processor to cache the at least one processor; a main bus in communication with the at least one processor and the cache memory to transmit and receive data to and from the cache memory and the at least one processor; a coherency control in communication with the cache and the at least one processor and configured to determine an existence or location of data in the cache or the storage area responsive to a data request from the main bus and dispatch a result indicating the existence or location of the data to the main bus, a return buffer buffering data transmission from the main bus to the cache and the at least one processor, wherein the coherency control is configured to communicate with the return buffer to determine the existence or location of the data in the return buffer; and a read queue configured to dispatch data from the cache, wherein the coherency control is in communication with the read queue to determine the existence or location of the data in the read queue; wherein the coherency control is configured to re-determine the existence or location of the data in the read queue, return buffer, storage area, and the cache if the coherency control determines that the data is in the return buffer or the read queue.