Patent ID: 7124282

Claim:
A processing device, comprising: a memory including a plurality of independently addressable memory banks for storing a set of logically successive instructions; wherein a first memory bank includes a first memory location storing a first instruction of the set of logically successive instructions, and wherein a second memory bank includes a second memory location storing a second instruction of the set of logically successive instructions, the second instruction logically succeeding the first instruction; and a read unit in electrical communication with said memory, wherein said read unit addresses the first memory location during a first clock period and addresses the second memory location during a second clock period succeeding the first clock period, wherein, in response to the addressing of the first memory location by said read unit during the first clock period, said first memory bank reads the first instruction from the first memory location, and wherein said read unit addresses the second memory location while said first memory bank reads the first instruction from the first memory location.