Patent ID: 8352685

Claim:
An apparatus comprising: a cache; a write buffer coupled to the cache and configured to buffer write operations that access the cache, wherein the write buffer comprises a plurality of entries, each entry configured to store combined write operations on a cache block granularity; and a control circuit coupled to the write buffer, wherein the control circuit is configured to cause the write buffer to transmit one or more combined write operations from one or more entries of the plurality of entries to a next level of memory below the cache responsive to one or more flush metrics applied by the control circuit and responsive to a fullness of the write buffer, and wherein the control circuit is configured to dynamically modify the one or more flush metrics responsive to activity in the write buffer, wherein dynamically modifying the one or more flush metrics changes a frequency at which the control circuit causes transmission of combined write operations from the write buffer to the next level of memory, and wherein the one or more flush metrics comprise a collapse state in each entry of the plurality of entries, wherein the collapse state indicates whether or not at least one collapsed write has been detected in the write operations combined in that entry, and wherein the control circuit is configured to cause the transmission of the one or more combined write operations responsive to the number of occupied buffer entries that are not in the collapse state reaching a threshold.