Patent ID: 8207452

Claim:
A multilayer interconnection board comprising: a plurality of laminated ceramic layers; wiring electrodes disposed on an upper principal surface of each of at least two of the plurality of laminated ceramic layers; and dot patterns defined by a plurality of dots scattered in the vicinity of the wiring electrodes on the upper principal surface of each of the at least two of the plurality of ceramic layers; wherein none of the plurality of dots on the upper principal surface of a first ceramic layer of the at least two of the plurality of laminated ceramic layers are arranged to overlap any of the wiring electrodes disposed on the upper principal surface of the first ceramic layer in a lamination direction of the plurality of laminated ceramic layers; and each of the plurality of dots is disposed on the upper principal surface of one of the at least two of the plurality of ceramic layers and none of the plurality of dots extend entirely through any of the at least two of the plurality of ceramic layers.