Patent ID: 6981132

Claim:
A processor comprising: a register file including a plurality of registers; and an execution core coupled to the register file, wherein the execution core is configured to: (i) use a value of a register address field of an instruction to select a least significant portion of one of the plurality of registers responsive to detecting a prefix field in the instruction, wherein each value encodable in the register address field results in a selection of the least significant portion of a respective one of the plurality of registers; and (ii) use the value of the register address field to select one of either a least significant portion or a second least significant portion of one of a subset of the plurality of registers responsive to detecting a lack of a prefix field in the instruction, wherein the subset excludes at least one of the plurality of registers, wherein a first value encodable in the register address field results in the selection of the least significant portion of a first register of the plurality of registers if the instruction includes the prefix field, and wherein the first value results in the selection of the second least significant portion of a second register of the plurality of registers if the instruction does not include the prefix field, and wherein the second register is different from the first register.