Patent ID: 8045074

Claim:
An array substrate comprising: a pixel that is provided on the array substrate, the pixel comprising: a scanning line; a signal line that intersects the scanning line; a thin film transistor that is connected to the scanning line and the signal line in a region surrounded by the scanning line and the signal line; a pixel electrode that is connected to the thin film transistor; and a sub-capacitance line that forms a sub-capacitance, wherein a display region, where a plurality of the pixels is disposed in a matrix-like shape, has a non-quadrangle shape, wherein a frame region on the outside of a display region comprises: a scanning lead-out line connected to the scanning line; a signal lead-out line connected to the signal line; and a common lead-out line that connects the sub-capacitance line in common to a side of a frame region where the scanning lead-out line is disposed, wherein the frame region comprises an intersection region of the scanning lead-out line and the signal lead-out line, and wherein the common lead-out line is disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line, whereas the common lead-out line is not disposed in the intersecting region.