Patent ID: 8790991

Claim:
A method of forming a shallow trench isolation region, said method comprising: forming a pad stack on an uppermost surface of a semiconductor substrate, wherein said pad stack includes, from bottom to top, a semiconductor oxide and a semiconductor nitride; forming a trench into both said pad stack and said semiconductor substrate, said trench is defined by sidewalls and a bottom wall; forming a shallow trench isolation liner directly on said sidewalls and said bottom wall of said trench, but not on any portion of the pad stack; forming a high-k liner selected from at least one of a dielectric metal oxide, a dielectric metal nitride, a dielectric metal oxynitride, a dielectric metal silicate, and a dielectric nitrided metal silicate directly on exposed surfaces of said shallow trench isolation liner, and on exposed sidewall surfaces of said pad stack and a topmost surface of said pad stack; forming a trench dielectric material in direct physical contact with exposed surfaces of the high-k liner, completely filling said trench, and having an uppermost surface that is coplanar with said topmost surface of said pad stack; removing remaining portions of said semiconductor nitride to expose a topmost surface of remaining portions of said semiconductor oxide and to provide a protruding portion of the shallow trench isolation region which extends above said topmost surface of said remaining portions of said semiconductor oxide; removing exposed portions of the high-k liner from said protruding portion of the shallow trench isolation region; and removing a remaining protruding portion of said shallow trench isolation region and said remaining portions of said semiconductor oxide.