Patent ID: 7889741

Claim:
A method executed by a processor, comprising: accessing a condition test vector based on an index value, the condition test vector including a first plurality of bit values defining a first relation, a second plurality of bit values defining a first key selector, and a third plurality of bit values defining a first condition value, the condition test vector including a fourth plurality of bit values defining a second condition relation, a fifth plurality of bit values defining a second key selector, and a sixth plurality of bit values defining a second condition value; selecting a first key from a plurality of keys based on the second plurality of bit values, each key from the plurality of keys including a combination of bit values representing a portion of a data packet; determining whether the first key selected from the plurality of keys and the first condition value satisfy the first condition relation to define a first result; selecting a second key from the plurality of keys based on the fifth plurality of bit values; determining whether the second key selected from the plurality of keys and the second condition value satisfy the second condition relation to define a second result; and sending an indication of the first result and the second result.