Patent ID: 7157970

Claim:
A buffer circuit comprising: a differential input configured to receive an input signal; a first differential stage supplied with a first reference current, the first differential stage comprising PMOS-transistors having gate terminals connected to the differential input; a second differential stage supplied with a second reference current, the second differential stage comprising NMOS-transistors having gate terminals connected to the differential input; a switching PMOS-transistor operable to, when the input signal is higher than a predetermined first threshold voltage, divert the first reference current from the first differential stage to a first current mirror circuit configured to mirror the first reference current; a switching NMOS-transistor operable to, when the input signal is lower than a predetermined second threshold voltage, divert the second reference current from the second differential stage to a second current mirror circuit configured to mirror the second reference current; a third differential stage comprising NMOS-transistors having gate terminals connected to the differential input, wherein the third differential stage is configured to receive the mirrored first reference current when the input signal is higher than the first threshold voltage; a fourth differential stage comprising PMOS-transistors having gate terminals connected to the differential input, wherein the fourth differential stage is configured to receive the mirrored second reference current when the input signal is lower than the second threshold voltage; a third current mirror circuit operably connected to receive a first output current of the third differential stage, and operable to mirror the first output current of the third differential stage to a first output current line; and a fourth current mirror circuit operably connected to receive a second output current of the third differential stage, and operable to mirror the second output current of the third differential stage to a second output current line; and wherein the third differential state comprises two NMOS-transistors having drain terminals connected to the first current mirror circuit.