Patent ID: 7206236

Claim:
An array system capable of repairing multiple independent bit line failures, the array system comprising: an array, having a first side and a second side, comprising a plurality of bit lines between the first side and the second side, the plurality of bit lines further comprising: a plurality of non-spare bit lines; and a plurality of spare bit lines; a fail map capable of storing identities of failing bit lines; a storage control that drives a plurality of data signals for storage in the array during a write to the array and which reads the plurality of data signals during a read from the array, a number of signals in the plurality of data signals being equal to a number of non-spare bit lines in the plurality of non-spare bit lines, a number of spare bit lines being equal to a difference of a total number of bit lines in the plurality of bit lines and the number of non-spare bit lines, the number of spare bit lines being two or greater; a redundancy selector, coupled to the plurality of data signals and to the plurality of bit lines, that routes each data signal in the plurality of data signals to a functional bit line in the plurality of bit lines, the redundancy selector capable of utilizing more than one of the spare bit lines if there are more than one failing bit line in the plurality of non-spare bit lines; and a select logic coupled to the fail map, and further coupled to the redundancy selector, capable of controlling the redundancy selector to route each data signal in the plurality of data signals to a functional bit line in the plurality of bit lines, and to route to each data signal in the plurality of data signals data from the functional bit line used to store data from each data signal.