Patent ID: 7622973

Claim:
A pulse control device comprising: a single fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse determined according to information on a change of process; and a pulse generator having a delay controller provided with a plurality of delay cells having a predetermined time delay for selectively increasing or decreasing the number of activated delay cells in response to the delay increase signal and the delay decrease signal to generate an internal clock of which a pulse width is controlled corresponding to the number of the activated delay cells, wherein the information on the change of process is detected in a test pattern step of testing whether or not a process of each wafer is progressed, wherein the delay controller includes: a first delay cell for delaying an inverted clock of the clock; a first NAND gate for NAND-operating the output of the first delay cell and the delay increase signal; a second NAND gate for NAND-operating the clock and the output of the first NAND gate; a second delay cell for delaying the output of the second NAND gate; a third delay cell for delaying the output of the second delay cell; a third NAND gate for NAND-operating the output of the second delay cell and the delay decrease signal; and a NOR gate for NOR-operating an inverted output of the third NAND gate and the output of the third delay cell.