Patent ID: 8592942

Claim:
A non-volatile semiconductor memory device comprising: a select transistor including source/drain regions on both sides of a channel of a semiconductor substrate and including a gate electrode on the channel via a first gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to said select transistor; an antifuse formed on the semiconductor substrate, the antifuse comprising: a lower electrode formed on the semiconductor substrate; an upper electrode formed on the semiconductor substrate in an area between said element isolation region and the lower electrode via a second gate insulating film; and side walls formed on sides of the upper electrode; and a connection contact electrically connecting one of the source/drain regions and the upper electrode and contacting said one of the source/drain regions and the upper electrode, wherein a side wall is formed on a well on the semiconductor substrate, wherein the upper electrode and the lower electrode are separated in a width of the side wall, wherein the sidewalls and a part of a top portion of the upper electrode is in direct contact with a single interlayer insulating film, and wherein the single interlayer insulating film is in direct contact with the upper electrode, at least one of the sidewalls of the upper electrode, the connection contact and the lower electrode.