Patent ID: 6900679

Claim:
A digital phase control circuit comprising: a first set of serially-connected delay buffers comprising differential delay buffers concatenated in h stages, said first set receiving a clock signal as an input signal, each said delay buffer in said first set having a first propagation time delay; h+1 sets of second voltage-controlled delay lines, wherein each of h of said h+1 delay line sets are connected to one of an output of a respective one of said stages of said first voltage-controlled delay line and a final delay line set of said h+1 delay line sets is connected to said input clock signal, each said set of said h+1 second voltage-controlled delay lines comprising differential delay buffers concatenated in j stages, each said delay buffer in said h+1 sets of second voltage-controlled delay lines having a second propagation time delay; a third voltage-controlled delay line comprising differential delay buffers concatenated in k stages, each delay buffer in said third voltage-controlled delay line having a third propagation time delay; and a selector switching circuit receiving as inputs a plurality of differential-pair input signals, said input signals being differential output signals from predetermined ones of said differential delay buffers in said h stages of said first voltage-controlled delay line and differential output signals from predetermined ones of said differential delay buffers in said h+1 second voltage-controlled delay lines, said selector switching circuit allowing a switchably selected one of said plurality of differential-pair input signals as a differential-pair of said selector switching circuit to be an input to said third voltage-controlled delay line, wherein at least one of said first, second, and third propagation time delays differs from the other of said first, second, and third propagation time delays.