Patent ID: 6992348

Claim:
A semiconductor memory device with vertical charge-trapping memory cells, the device comprising: a semiconductor body; a plurality of parallel openings arranged at intervals to each other in the semiconductor body, wherein the openings alternate between active trenches and isolation trenches; a plurality of memory cells located in a memory cell field, each memory cell being disposed in one of the active trenches, each of the memory cells including: a first source/drain region disposed in a top surface of the semiconductor body adjacent the trench; a second source/drain region disposed in the semiconductor body at a floor of the trench; a channel region disposed along a sidewall of the active trench, wherein the channel region is disposed between the first source/drain region and the second source/drain region; a gate electrode; a gate dielectric, wherein the gate dielectric separates the channel region from the gate electrode; a charge trapping region disposed between the gate electrode and a portion of the channel region, wherein the charge trapping region is provided for programming by trapping charge from the semiconductor body; a plurality of upper bit lines electrically coupling the first source/drain regions of a plurality of the memory cells to each other; a plurality of lower bit lines electrically coupling the second source/drain regions of a plurality of the memory cells to each other; a plurality of upper bitline contacts, each upper bitline contact electrically coupled to at least one of the upper bit lines at a location outside the memory cell field; and a plurality of lower bitline contacts, each lower bitline contact electrically coupled to at least one of the lower bit lines.