Patent ID: 8426257

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a substrate having a cell region and a fuse region; forming a metal interconnection in the cell region and a fuse in the fuse region, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, wherein the metal interconnection has the same structure with the fuse and is concurrently formed with the fuse; completely removing the anti-reflective layer and simultaneous etching a portion of the metal layer to expose an upper portion of the etched metal layer, thereby forming a resultant structure, wherein the anti-reflective layer and the portion of the metal layer are etched using a gas mixture of chlorine (Cl 2 ), trichloroborane (BCl 3 ), argon (Ar), nitrogen (N 2 ) and fluoroform (CHF 3 ); forming an insulation layer over a whole surface of the resultant structure including the fuse; and performing a repair-etching such that part of the insulation layer remains above the fuse, wherein the anti-reflective layer includes any one of a single-layered structure of any one selected from a Ti layer, a TiN layer, and a silicon oxynitride (SiON) layer, and a stacked structure of the Ti layer, a TiN layer, and a SiON layer.