Patent ID: 7240308

Claim:
A simulation method of a semiconductor circuit device for simulating characteristics of a circuit when a negative bias voltage and a bias free voltage are applied to a semiconductor circuit including a metal insulator semiconductor transistor by using a calculation processing means, comprising: a step of obtaining a basic deterioration amount (X D ) of characteristics of said transistor depending on a negative bias voltage applied to said transistor, an operation temperature of said transistor, and a time passed after forming said transistor; a step of calculating a deterioration amount (ΔP D ) that said transistor deteriorates along with a duration of applying a negative bias voltage in a first period wherein said negative bias voltage is applied to said transistor; a step of calculating a recovery amount (ΔP R ) that characteristics of said deteriorated transistor along with a duration of a second period wherein application of said negative bias voltage to said transistor is terminated or a bias free voltage of a higher level than that of said negative bias voltage is applied to said transistor; a step of calculating a total deterioration amount (P) by adding said basic deterioration amount (X D ) and said deterioration amount (ΔP D ) and subtracting said recovery amount (ΔP D ) from the addition result; a step of selecting only a transistor having a larger total deterioration amount than a predetermined set value from a plurality of transistors based on total deterioration amounts of the respective transistors obtained in said step of obtaining a basic deterioration; and a step of performing a characteristics simulation on the selected transistor.