Patent ID: 7167410

Claim:
A unitary memory device comprising: a memory array; a first set of one or more serial interfaces to communicate memory operations, data, and address information to the unitary memory device; a second set of one or more serial interfaces to communicate memory status and stored data from the unitary memory device; one or more ports interacting with the memory array separately from each other port within the unitary memory device; each serial interface associated with one of the memory ports; and a reference clock interface, the reference clock interface configured to receive a signal from a reference clock source; wherein at least one of the first set of one or more serial interfaces and at least one of the second set of one or more serial interfaces: performs clock multiplication on a reference clock to provide a multiplied clock; uses the multiplied clock to serialize and transmit data; uses the reference clock and received data to recover timing information; and uses the timing information to de-serialize received serial data.