Patent ID: 7586335

Claim:
A digital phase detector for the generation of a digital phase detection signal (PD_OUT), which specifies the phasing of an input clock signal (PD_IN) supplied to the phase detector with reference to a higher frequency sampling clock signal (CK_ 0 , CK_ 90 ) supplied to the phase detector, comprising: a digital adjustable phase displacement device ( 12 ) for the generation of an auxiliary sampling clock signal (CK< 1 : 8 >) as a digital adjusted phase displaced version of the sampling clock signal (CK_ 0 , CK_ 90 ), wherein the auxiliary sampling clock signal (CK< 1 : 8 >) is adjustable in steps which in each case are smaller than one period of the sampling clock signal (CK_ 0 , CK_ 90 ), a sampling device ( 14 ) for the sampling of the input clock signal (PD_IN) with the auxiliary sampling clock signal (CK< 1 : 8 >), in order to generate a first, more significant digital component (OUT 1 < 9 : 0 >) of the phase detection signal (PD_OUT), an evaluation device ( 20 , 22 ) for the evaluation of the first digital component (OUT 1 < 9 : 0 >) and for the generation of a digital control signal (s) on the basis of the evaluation result, by means of which the adjustable phase displacement device ( 12 ) is adjusted, and a second, less significant digital component (OUT 2 < 12 : 0 >) of the phase detection signal (PD_OUT) is generated, an adding device ( 18 ) for the generation of the phase detection signal (PD OUT) by an addition of the first and second digital components (OUT 1 < 9 : 0 >, OUT 2 < 12 : 0 >) inputted to the adding device ( 18 ).