Patent ID: 6838712

Claim:
A synchronous double-data-rate semiconductor device, comprising: a memory bank comprising an array of rows and columns of memory cells; input/output circuitry coupled between said memory bank and a plurality of external input/output terminals; wherein said input/output circuitry comprises a separate write path circuit coupled to each of said plurality of external input/output terminals, each write path circuit comprising: an input buffer having a data input and an output; a first delay element having an input coupled to said output of said input buffer and having an output, said first delay element responsive to a data signal at the output of said input buffer to generate a first delayed data signal; a second delay element having an input coupled to said output of said input buffer and having an output, said second delay element responsive to said data signal at the output of said input buffer to generate a second delayed data signal; a first pass gate having an input coupled to said output of said first delay element, an output, and at least one control input; a second pass gate having an input coupled to said output of said second delay element, an output, and at least one control input; wherein said first pass gate is responsive to a rising edge in at least one data strobe signal applied to said at least one control input thereof to present said first delayed data signal on said first pass gate output in; and wherein said second pass gate is responsive to a falling edge in said at least one data strobe signal applied to said at least one control input thereof to present said second delayed data signal on said second pass gate output.