Patent ID: 7337304

Claim:
A processor for executing instruction control in accordance with dynamic pipeline scheduling, comprising: an instruction issuing unit which issues instructions by in-order; an instruction executing unit which executes the instructions by out-of-order; a committing unit which discriminates a commitment of the instructions by the in-order and completes them; an instruction discriminating unit which discriminates whether all of a plurality of instructions which have simultaneously been fetched and decoded are symmetry instructions which can be arithmetically operated by different arithmetic operating units or there is an asymmetry instruction which can be arithmetically operated only by a specific arithmetic operating unit among said plurality of instructions and the residual instructions are said symmetry instructions; a symmetry instruction issuing unit which, in the case where it is determined that all of said plurality of instructions are the symmetry instructions, issues said symmetry instructions to a plurality of reservation stations provided for every different arithmetic operating units until they become full; and an asymmetry instruction issuing unit which, in the case where it is determined that the asymmetry instruction exists among said plurality of instructions and the residual instructions are the symmetry instructions, develops said asymmetry instruction into a multiflow of a previous flow and a following flow, issues said asymmetry instruction to the reservation station provided for said specific arithmetic operating unit, and issues the residual symmetry instructions to said plurality of reservation stations provided for said every different arithmetic operating units in an issuing cycle different from that of said asymmetry instruction until they become full; wherein there is a one-to-one correspondence of reservation stations to arithmetic operating unit; and wherein said asymmetry instruction issuing unit transfers the asymmetry instruction held in an instruction word register group to a multiflow instruction word register and holds it in a decoding cycle of the previous flow and issues the asymmetry instruction in said multiflow instruction word register to the corresponding reservation station in a decoding cycle of the following flow.