Patent ID: 8493811

Claim:
A memory comprising: an address input coupled to receive a read address for the memory; a static decoder coupled to receive the read address and configured to decode the address to activate a plurality of word lines to access memory cells of the memory, wherein the read address decodes to activate a first word line of the plurality of word lines; and a static output circuit coupled to the memory cells and configured to output data from the memory cells that are accessed via the first word line, the static output circuit comprising a plurality of push-pull driver circuits coupled to each of a plurality of global bit lines; wherein a read of the memory is performed in response to the read address arriving at the address input and flows through the static decoder and static output circuit independent of a clock defining a clock cycle in which the memory operates during use, and wherein the read of the memory occurs at any point in the clock cycle in response to the read address during use; wherein the memory cells are organized into pairs having first and second memory cells, wherein each of the first and second memory cells are coupled to first and second passgates, respectively, and wherein the memory further comprises a shared inverter coupled between and to each of the first and second passgates and having an input coupled to one of the plurality of word lines, and wherein the first and second passgates are configured to activate responsive to assertion of the word line coupled to the input of the shared inverter.