Patent ID: 8779820

Claim:
A cell for a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), the cell comprising: a stage configured to generate an output signal based on a provided input signal, the output signal having a selectable skew value of at least one of a rise time and a fall time of an output signal of the cell, wherein the cell has a relatively uniform cell size and terminal layout over a range of the skew values; wherein the stage is further configured to generate a delayed output signal based on the provided input signal, the delayed output signal having a programmable delay through the cell, the cell having a selectable delay value from a plurality of delay values, wherein the cell has a relatively uniform cell size and terminal layout over a range of the plurality of delay values, and wherein the selectable skew value and selectable delay value are selected by modifying a single layer of a layout of the IC, without modifying the cell size and terminal layout of the cell, thereby achieving a cell having a substantially uniform cell size and terminal layout over the range of skew values and the range of delay values.