Patent ID: 8324880

Claim:
A driving circuit with function of reducing dead-time, comprising: a dead-time detecting circuit coupled to an output of a power switch set, for detecting a switching voltage on the output of the power switch set and accordingly generating a dead-time detecting signal; wherein the output end of the power switch set is coupled to a first end of an inductive load; wherein a second end of the inductive load provides an output voltage; wherein the power switch set comprises: a first power switch having a first end coupled to a first voltage source, a second end coupled to the output end of the power switch set, and a control end for receiving a first switch-driving signal; and a second power switch having a first end coupled to a second voltage source, a second end coupled to the output end of the power switch set, and a control end for receiving a second switch-driving signal; wherein when the first switch-driving signal represents turning-on, the first power switch is turned on; wherein when the second switch-driving signal represents turning-on, the second power switch is turned on; a duty-cycle controlling circuit coupled to the second end of the inductive load for generating a set/reset signal according to the output voltage; and a switch-controlling circuit for changing the state of the power switch set from a dead-time state according to the set/reset signal and the dead-timed detecting signal, wherein the switch-controlling circuit comprises: a latch circuit, comprising: a first latch, for generating a first control signal according to a first logic signal, the set/reset signal, and the dead-time detecting signal; wherein the first logic signal represents a first predetermined logic; and a second latch, for generating a second control signal according to a second logic signal, the set/reset signal, and the dead-time detecting signal; wherein the second logic signal represents a second predetermined logic; a logic-calculating module, comprising: a first logic-calculating circuit, for generating a first switch signal according to the set/reset signal, the first control signal, and the second switch-driving signal; and a second logic-calculating circuit, for generating a second switch signal according to the set/reset signal, the second control signal, and the first switch-driving signal; and a buffer circuit, comprising: a first buffer, for generating the first switch-driving signal according to the first switch signal; and a second buffer, for generating the second switch-driving signal according to the second switch signal; wherein the first predetermined logic is different from the second predetermined logic.