Patent ID: 7419844

Claim:
A method of fabricating a stacked photodiode on a silicon-on-oxide (SOI) wafer, comprising: preparing a handle wafer, comprising: preparing a p-type bulk silicon wafer; implanting and activating a first ion into the p-type silicon layer to form a first N+ layer for a bottom photodiode cathode; implanting and activating a second ion into the p-type silicon layer on top of the first N+ layer to form a moderately doped p-layer; forming a layer of p-type epitaxial silicon on the p-type silicon layer and N+ cathode; implanting and activating a third ion into the p-type epitaxial silicon layer to form a N+ layer for a middle photodiode cathode; implanting and activating a fourth ion into the p-type epitaxial silicon layer to form a N+ surface layer for a cathode contact for the bottom photodiode; preparing a donor wafer, comprising: preparing a silicon donor wafer; thermally oxidizing the silicon donor wafer to form an oxide layer thereon; implanting ions to create a defect plane; preparing the surfaces of the donor wafer and the handle wafer for bonding; bonding the handle wafer and the donor wafer to form a combined wafer; curing the combined wafer; splitting the combined wafer, leaving a top silicon layer on the handle wafer from the donor wafer and burying the oxide layer thereunder as a buried oxide layer, thus forming a silicon-on-oxide structure; annealing the handle wafer to enhance bonding energy; forming an N+P junction in the top silicon layer to form a top photodiode cathode; forming and grounding a P+ region in the top silicon layer to form a top photodiode anode; opening the buried oxide layer to the N+ cathode of the middle photodiode and the bottom photodiode; fabricating pixel transistor(s) on the top silicon layer for each photodiode; and fabricating a CMOS peripheral control circuit.