Patent ID: 7613968

Claim:
A semiconductor device comprising: an inner circuit; first boundary scan flip-flops, coupled to the inner circuit, for a JTAG test; first external terminals coupled to the first boundary scan flip-flops for the JTAG test; second external terminals for a high-speed interface not coupled to the first boundary scan flip-flops for the JTAG test; a high-speed input and output circuit for inputting and outputting signals between at least one of the second external terminals for the high-speed interface and the inner circuit in response to a clock which has a higher frequency than a frequency of a clock for the JTAG test, and second boundary scan flip-flops provided between the inner circuit and the high-speed input and output circuit; wherein a chain used for boundary scan is prepared by the first boundary scan flip-flops and the second boundary scan flip-flops; and wherein the first and second boundary scan flip-flops are scanned with test data for a test of the semiconductor device in the JTAG test.