Patent ID: 7049648

Claim:
A semiconductor memory device comprising: an interlevel dielectric pattern and an adhesive pattern having a top surface sequentially disposed on a semiconductor substrate; a contact hole extending through both the interlevel dielectric pattern and the adhesive pattern to expose a region of the semiconductor substrate; a plug disposed within the contact hole; a lower electrode of a capacitor having bottom and side wall surfaces, wherein at least a portion of the bottom surface thereof contacts a pardon of the plug; and a leakage current preventive pattern formed on the adhesive pattern and adjacent a portion of the side wall surface of the lower electrode, wherein the leakage current preventive pattern overlaps the top surface of the adhesive pattern, wherein substantially all of the leakage current preventive pattern overlapping the top surface of the adhesive pattern directly contacts the top surface of the adhesive pattern, and wherein at least a portion of the leakage current preventive pattern is disposed between the lower electrode and the adhesive pattern, wherein the plug diseased within the contact hole projects higher than the ton surface of the adhesive pattern.