Patent ID: 7259067

Claim:
A method for manufacturing a flash memory device, comprising: forming a tunnel oxide layer and a first conductive layer on a semiconductor substrate and then performing a shallow trench isolation process to form an isolation structure that defines a first region and a second region; forming a second conductive layer on the entire structure and then patterning the second conductive layer and the first conductive layer to form a floating gate pattern; forming a dielectric layer, a third conductive layer, a fourth conductive layer and a hard mask layer on the entire structure and then patterning the hard mask layer; and forming a control gate and a floating gate by performing an etching process from the fourth conductive layer to the first conductive layer in a single etch apparatus using the hard mask layer as a mask; wherein the etching process comprises the steps of: (a) over-etching the fourth conductive layer; (b) etching the third conductive layer to expose the dielectric layer on the first region, and performing over-etch for a thickness of the third conductive layer to expose the dielectric layer on the second region; (c) etching the dielectric layer to expose a portion of the second conductive layer on the first region, and etching portions of the third conductive layer and the second conductive layer while stripping a portion of the dielectric layer on the second region; (d) stripping the third conductive layer remaining on the second region; (e) etching the second conductive layer on the first region and at the same time stripping the dielectric layer and the second conductive layer remaining on the second region; and (f) stripping the first conductive layer.