Patent ID: 7411420

Claim:
A receiver circuit which samples a pair of differential input signals, detects a level of said pair of input signals, and latches the detected level said receiver circuit comprising: an input integrating circuit including: a pair of input transistors receiving the pair of input signals at respective gates thereof, a switch transistor becoming conducting in response to a sampling clock in a sampling period so as to supply a discharge current to a common source terminal of said pair of input transistors, and a precharge circuit precharging drain terminals of said pair of input transistors in a precharge period, wherein said input integrating circuit discharges capacitors of the drain terminals by the discharge current in the sampling period succeeding the precharge period; and a differential amplifier circuit being activated after said sampling period for amplifying the drain terminals of the input integrating circuit, wherein the input integrating circuit performs precharge operation when a predetermined time elapses after the differential amplifier circuit is activated.