Patent ID: 7401308

Claim:
A timing analysis apparatus, comprising: a data extracting unit that extracts objective circuit data concerning an objective circuit to become an objective of a timing analysis and including a plurality of circuit element data from layout data indicating circuits arranged and wired on a large-scale-integration chip; a time calculating unit that calculates a delay time of the objective circuit based on the objective circuit data extracted; a parameter calculating unit that calculates a parameter indicating a size of an arrangement area of the objective circuit based on the objective circuit data extracted, using a maximum distance between two arbitrary circuit elements extracted from the circuit element data; an information calculating unit that calculates, based on the parameter, variation information concerning a variation of the delay time calculated; and a timing analyzing unit that performs the timing analysis of the objective circuit using the delay time and the variation information calculated wherein the parameter calculating unit includes a combination extracting unit that extracts a combination of two arbitrary circuit element data from the circuit element data; a distance calculating unit that calculates a distance between the two arbitrary circuit element data in the combination extracted; and a distance extracting unit that determines the maximum distance from distances calculated by the distance calculating unit for a plurality of combinations extracted by the combination extracting unit from the circuit element data.