Patent ID: 8233313

Claim:
A non-volatile memory device including a plurality of unit cells, each unit cell comprising: lower and upper electrodes over a substrate; a conductive organic material between the lower and the upper electrodes; and a nanocrystal layer located within the conductive organic material, wherein the nanocrystal layer includes a plurality of nanocrystals, each nanocrystal being surrounded by an amorphous barrier, wherein the unit cell is configured to receive a plurality of voltage ranges to perform a plurality of operations, where a read operation is performed when an input voltage coupled to the lower and the upper electrodes is in a first voltage range; a first write operation is performed for writing a first input data when the input voltage is in a second voltage range higher than the first voltage range; a second write operation is performed for writing a second input data when the input voltage is in a third voltage range higher than the second voltage range; and an erase operation is performed for erasing the first or the second input data when the input voltage is in a fourth voltage range higher than the third voltage range.