Patent ID: 7514730

Claim:
A semiconductor device on a semiconductor substrate, comprising: a silicon alloy layer on said semiconductor substrate; insulator filled openings in a top portion of said silicon alloy layer, with portions of said insulator filled openings recessed at edge of said insulator filled openings; a strained silicon shape comprised with a first segment of strained silicon shape overlying a portion of said silicon alloy layer located between said insulator filled openings, and comprised of attached second segments of said strained silicon shape located on top surface of recessed portions of said insulator filled openings; an insulator spacer located on a side of said strained silicon shape, wherein a top surface and a bottom surface of the insulator spacer is planar with a top surface and a bottom surface of the strained silicon shape respectively; a gate insulator layer on a top surface of said strained silicon shape; a conductive gate structure on said gate insulator layer in an area in which said gate insulator layer overlays a portion of said first segment of strained silicon shape; and a doped source/drain region in a portion of said strained silicon shape not covered by said conductive gate structure.