Patent ID: 7816154

Claim:
A method of manufacturing a semiconductor device comprising: a first process of forming a first semiconductor device having a first memory circuit; a second process of conducting an electrical test on the first semiconductor device to sort non-defective items; a third process of forming a second semiconductor device having a signal processing circuit carrying out signal processing according to a program and a second memory circuit; a fourth process of conducting an electrical test on the signal processing circuit and second memory circuit of the second semiconductor device to sort non-defective items; a fifth process of integrally configuring the first semiconductor device sorted in the second process and the second semiconductor device sorted in the fourth process and coupling together the respective corresponding terminals thereof; and a sixth process of mounting the semiconductor devices integrally configured in the fifth process over a board for testing, and conducting an electrical test to determine the failure/no-failure of the semiconductor devices, wherein the board for testing is provided with an oscillation circuit supplying a clock signal equivalent to the actual operation of the semiconductor devices to the semiconductor devices in common, and wherein the sixth process includes: a first operation of writing a test program for conducting a performance test on the first memory circuit of the first semiconductor device from a tester to the second memory circuit of the second semiconductor device; a second operation of conducting a performance test on the first memory circuit of the first semiconductor device according to the test program written to the second memory circuit, in accordance with the clock signal, by the signal processing circuit of the second semiconductor device; and a third operation of outputting the result of failure/no-failure determination in the second operation to the tester.