Patent ID: 7496093

Claim:
Slave circuit which can be connected in series with further slave circuits and a master circuit to form a ring structure, having: (a) a data transmission interface for processing data frames which are received from the master circuit, where the data transmission interface has an external data input for receiving the data frames from the master circuit and a data output for sending data frames to the next series connected slave circuit, where each data frame contains at least a first data field for an address and a second data field for transmitting user data; (b) an address register for storing an address, where the address register has stored, prior to the initialization of the slave circuit by the master circuit, a predetermined initialization address which is provided for all the slave circuits jointly; (c) a comparator for comparing the address stored in the address register with an address received from the data transmission interface in a data frame, where the address register stores the data transmitted in the second data field of the data frame as a future address for the slave circuit if the address transmitted in the first data field of the data frame is identical to the predetermined initialization address; (d) an indicator register which indicates the initialization of the slave circuit if the address received by the data transmission interface in the slave circuit is identical to the predetermined initialization address; and having (e) an inhibit logic unit which inhibits the data output of the data transmission interface until the indicator register indicates initialization of the slave circuit.