Patent ID: 7913259

Claim:
A non-transitory computer-readable medium containing instructions to configure a processor to perform operations comprising: providing a parent task to initiate a task graph, the parent task including a task number unique to the task graph, wherein the task number defines a head position within a hierarchy forming the task graph, the task graph defining a test sequence of an application under test; providing one or more child tasks, the one or more child tasks each including a task number to define a position within the hierarchy forming the task graph, a command to be performed during execution of one of the child tasks, one or more times associated with an execution of one of the child tasks, and a logical operand for defining, based on a return value from a higher-layer task, whether the one of the child tasks is to proceed with execution, wherein a user interface at least one of modifies and defines the task number, the command, the one or more times, and the logical operand; and enabling the parent task to initiate execution of the task graph to begin the test sequence of the application under test, wherein providing the parent task further comprises providing a last start time for the parent task and a last stop time for the parent task.