Patent ID: 8222132

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first region and a second region; forming a first gate structure over the first region and a second gate structure over the second region, the first gate structure including a first dummy dielectric and a first dummy gate, the second gate structure including a second dummy dielectric and a second dummy gate; removing the first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing the second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench; forming a gate layer to partially fill the first and second trenches, the gate layer including a high-k dielectric layer; forming a material layer to fill the remainder of the first and second trenches; removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, respectively; removing a second portion of the gate layer; removing the remaining portion of the material layer from the first and second trenches, respectively; and forming a first metal gate in the first trench and a second metal gate in the second trench.