Patent ID: 7228403

Claim:
A method for operating a processor having an architecture of a larger bit-length with a program comprising instructions compiled to produce instruction results of at least one smaller bit-length, characterized by the steps of: detecting when in program order a first instruction is to be dispatched which does not have a target register address as one of its sources, wherein the first instruction is one of the instructions compiled to produce instruction results of at least one smaller bit-length; adding an extract instruction into an instruction stream before the first instruction, the extract instruction comprising the following steps of: a. dispatching the extract instruction together with the following first instruction from an instruction queue into a Reservation Station; b. issuing the extract instruction to an Instructional Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme; c. executing the extract instruction by an available IEU; d. setting an indication that the result of said extract instruction needs to be written into a result field of the first instruction following the extract instruction, and; e. writing the extract instruction result into the result field of said first instruction, and into all fields of operands being dependent of said first instruction.