Patent ID: 7814252

Claim:
An asymmetric multiprocessor, comprising: a plurality of processor cores; a plurality of hardware accelerators; a bus that interfaces said plurality of processor cores with said plurality of hardware accelerators; a hardware resource mediator that mediates a request signal from a processor core, of said plurality of processor cores, that requests permission to use a hardware accelerator, of said plurality of hardware accelerators; and a plurality of DSP cores and a dynamically reconfigurable processor, wherein said processor core subjected to mediation of the request signal by said hardware resource mediator uses said hardware accelerator; and when a second processor core, of said plurality of processor cores, and said hardware accelerator, a DSP core, of said plurality of DSP cores, and said dynamically reconfigurable processor connected as a slave to said second processor core do not have to perform signal processing while a first processor core, of said plurality of processor cores, and said hardware accelerator, said DSP core and said dynamically reconfigurable processor connected as a slave to the first processor core do perform signal processing, said second processor core and said hardware accelerator, said DSP core and said dynamically reconfigurable processor connected as a slave to said second processor core turn OFF a power supply voltage or execute a retention function to reduce the power supply voltage to a minimum voltage at which data can be stored and held in a memory or a register.