Patent ID: 7247553

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming an N-type transistor and a P-type transistor in an intra cell region, so as to comprise a function cell; (b) forming an intra cell wiring layer connecting said N-type transistor and P-type transistor in an intra cell region; (c) forming a terminal pattern in a first wiring layer along a first direction, said terminal pattern being connected by a via to said intra cell wiring layer; and (d) forming a wiring line in a second wiring layer different from the first wiring layer along a second direction, the wiring line being connected to the terminal pattern through a hole, wherein said terminal pattern shares two or more lattice points on the first wiring layer, and further comprising: (e) forming a surplus portion at the terminal pattern in a position where the hole is formed on the same wiring layer as the terminal pattern, and wherein the surplus portion is provided so as to extend in a shorter direction of the terminal pattern or in a longer direction of the terminal pattern by a length not larger than one lattice point from a plane center of said hole.