Patent ID: 7694031

Claim:
A memory controller comprising: an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers, wherein the I/O circuit is configured to operate in one of a first mode and a second mode dependent upon a state of a mode selection signal; wherein during operation in the first mode, the I/O circuit is configured to provide a parallel interconnect for direct connection between the memory controller and one or more memory modules, wherein the parallel interconnect includes one or more clock signal paths each configured to convey a parallel clock signal from the memory controller to the one or more memory modules; wherein during operation in the second mode, the I/O circuit is configured to provide a respective serial interconnect for connection to a corresponding one of one or more buffer units interposed between the memory controller and the one or more memory modules, wherein each buffer unit is configured to buffer memory data that is being read from or written to the one or more memory modules; wherein each respective serial interconnect includes a plurality of differential bidirectional data signal paths, each configured to convey data at a first data transfer rate according to a serial clock signal between a corresponding buffer unit of the one or more buffer units and the memory controller; and wherein during operation in the first mode, each parallel clock signal operates at a second data transfer rate, wherein the first data transfer rate is faster than the second rate.