Patent ID: 8183061

Claim:
A method of fabricating a STT-MRAM on a substrate having a CMOS metal layer including a plurality of CMOS landing pads in a device region and a plurality of CMOS connection pads outside the device region that are separated by and are coplanar with a first dielectric layer, comprising: (a) sequentially forming a first etch stop layer and a second dielectric layer on the first dielectric layer and CMOS metal layer; (b) forming a plurality of intermediate via contacts (VAC) each having a first width within the first etch stop layer and second dielectric layer in the device region wherein each of said VAC is in electrical contact with an underlying CMOS landing pad, and has a top surface coplanar with said second dielectric layer; (c) forming a plurality of metal separation (VAM) pads on the second dielectric layer and separated by openings wherein each of said VAM pads has a second width greater than said first width and a bottom surface contacting and completely covering a top surface of a VAC, and forming a VAM dielectric layer that is coplanar with a top surface of each VAM pad and fills the openings between the VAM pads; (d) forming a plurality of MTJ elements each having a bottom surface that contact a top surface of an underlying VAM pad and a top hard mask surface, said MTJ elements are separated by openings that are subsequently filled with a MTJ ILD layer which is then planarized to be coplanar with said top hard mask surface; (e) sequentially depositing a second etch stop layer and a BIT ILD layer on the MTJ ILD layer and plurality of MTJ elements; and (f) performing a dual damascene process, comprising: (1) forming a plurality of BIT connection via openings in the BIT ILD layer that extend through the second etch stop layer, MTJ ILD layer, VAM dielectric layer, and second dielectric layer and stop on the first etch stop layer above each of the plurality of CMOS connections pads; (2) simultaneously forming a plurality of a first trenches in the BIT ILD layer and second etch stop layer outside the device region wherein each first trench connects with at least one BIT connection via opening, removing the first etch stop layer exposed by BIT connection via openings above the CMOS connection pads, and forming a plurality of second trenches in the BIT ILD layer and second etch stop layer in the device region wherein each second trench uncovers a top hard mask surface of a MTJ; and (3) depositing a conformal diffusion barrier layer within the first trenches, second trenches, and in the plurality of BIT connection vias, depositing a BIT metal layer on the conformal diffusion barrier layer to fill the plurality of first and second trenches and plurality of BIT connection vias, and planarizing the BIT metal layer to become coplanar with the BIT ILD layer.