Patent ID: 8028124

Claim:
A memory chip for increasing efficiency associated with data access, the memory chip comprises of: a plurality of memory units internal to the memory chip for storing data, wherein each memory unit has a set of memory cells arranged in a contiguous array of memory cells, and wherein each memory cell is configured to store a single bit of data; a word line configured to directly move a single word of data at a time to and from the contiguous array of memory cells of each memory unit of the plurality of memory units internal to the memory chip; a bit line configured to directly move only a single bit of data at a time to and from each memory cell of the contiguous array of memory cells of each memory unit of the plurality of memory units internal to the memory chip; a plurality of processing units internal to the memory chip for processing the data; the word line and the bit line configured for use by the processing units internal to the memory chip, wherein the plurality of processing units internal to the memory chip directly accesses the word line and the bit line in accessing the data; the word line and the bit line configured for use by a plurality of processing units external to the memory chip, wherein the plurality of processing units external to the memory chip directly accesses the word line and the bit line in accessing the data.