Patent ID: 8843902

Claim:
A method executable by a processor, comprising: receiving as an input: (a) a higher-level structure representing control flow through an executable program, the higher-level structure comprising multiple levels of reduced nodes, each reduced node representing internal structure comprising both a group of one or more unreduced nodes representing respective basic blocks and/or one or more other reduced nodes and one or more associated edges between those nodes, and (b) an indication of at least one start instruction and at least one end instruction; wherein said multiple levels of reduced nodes comprise first and second levels of reduced nodes and each reduced node of the second level represents a group comprising one or more reduced nodes of the first level; the method further comprising: probing the levels of the higher-level structure to extract a substructure representing a route through the program, from the start to the end instruction, by selectively extracting nodes of different levels to represent different regions along the route in dependence on a location of the start and end instructions relative to the reduced nodes, wherein said selective extraction comprises: extracting at least one reduced node of the second level and at least one reduced node of the first level, from another node of the second level and adding each of the extracted nodes to the substructure representing the route; and based on the extracted substructure, estimating an overall execution time for the entirety of the route through the program represented by the extracted substructure, and making a modification affecting the execution time in dependence on said estimation wherein the estimation of said execution time is based on a determination of an associated time for the extracted nodes.