Patent ID: 7091814

Claim:
An on-chip differential multiple layer inductor comprises: a first node on a first layer of a plurality of metal layers of an integrated circuit; a second node on the first layer; and a multi-layer winding on at least some of the plurality of metal layers, wherein the multi-layer winding is coupled to the first and second nodes, wherein the multi-layer winding is symmetrical with respect to the first and second nodes, and wherein metallization of the winding on each of the at least some of the plurality of metal layers is in an approximate range of twenty to eighty percent; first partial winding on at least one of the at least some of the plurality of metal layers; and second partial winding on at least another one of the at least some of the plurality of metal layers, wherein positioning of the second partial winding with respect to positioning of the first partial winding establishes a parasitic capacitance that, in combination with inductance of the on-chip differential multiple layer inductor, provides a resonant frequency of approximately twice an operating frequency of the on-chip differential multiple layer inductor.