Patent ID: 7603596

Claim:
A memory device capable of detecting its failure, the memory device comprising: a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for receiving the stored data from the memory cell array and the stored data from the latch section, wherein the data compressor determines whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other, wherein the latch section receives a write command signal and a read command signal, and receives and stores data output from the data input section in synchronization with the write command signal, wherein the data received and stored in the latch section remains in the latch section until the latch section receives a next write command signal, wherein the data stored in the latch section is sent to the data compressor in synchronization with the read command signal, and wherein the write command signal and the read command signal are activated at separate times.