Patent ID: 8519743

Claim:
A semiconductor integrated circuit comprising: a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal; a first P-channel field-effect transistor that inputs a data signal to the one inverter of the state holding circuit when a clock signal is in a low level; a second P-channel field-effect transistor that inputs an inverted data signal to the another inverter of the state holding circuit when the clock signal is in a low level; a first N-channel field-effect transistor that transmits one state held in the state holding circuit when the clock signal is in a high level; and a second N-channel field-effect transistor that transmits another state held in the state holding circuit when the clock signal is in a high level, wherein a gate of the first first-conductive transistor and a gate of the first second-conductive transistor are directly connected to a same node.