Patent ID: 6875650

Claim:
A method of fabricating a buried n-type layer connecting two n-wells in a p-type semiconductor region, electrically isolating the near-surface p-type semiconductor portion suitable for fabricating a high-voltage I/O nMOS transistor, comprising the steps of: depositing a photoresist layer over the surface of said p-type semiconductor region, arid opening a window in said layer, exposing the surface area between said n-wells; implanting, at low energy, n-doping ions through said window, creating shallow n-doped layers under said surface, suitable as extended source and drain of said transistor; and implanting, at high energy and high dose, n-doping ions into said p-type semiconductor through said window, creating a deep region having a net n-type doping between, and continuous with, said n-wells, and further creating a near-surface p-region having a doping concentration lower than that of the remainder of said p-type semiconductor region.