Patent ID: 6874058

Claim:
A content addressable memory comprising a CAM control logic unit and a plurality of cells connected in a chain, the cells being serially connected, each of the cells including: a memory block; a data interface and a plurality of addresses arranged to be sequentially addressed through the data interface, the plurality of addresses being coupled to a common address bus; a comparator coupled to a common data bus and to the data interface of the memory block; a switch for coupling the data interface of the memory block with the data bus; and a logic block including a Match flip-flop; the memory being operable arranged to have a search phase and an access phase so that: (a) in the search phase, a sequence of words on the common data bus is matched with the contents of a sequence of addresses in the memory blocks of the cells; and (b) in the access phase, causing the cells matched in the search phase to be serially available for access via the common address and data buses, said access phase occurring subsequent to said search phase; the logic block being arranged for cumulatively storing the results of the serial matching during the memory search phase as the matching proceeds.