Patent ID: 8836373

Claim:
A phase difference quantization circuit comprising: a path selection unit configured to transfer a first input signal to a first first-node and a second input signal to a first second-node in a normal mode and transfer the first input signal to the first first-node and the first second-node in a calibration mode; a first phase comparison unit configured to compare a phase of a signal loaded on the first first-node and a phase of a signal loaded on the first second-node and generate a first up/down signal; a first delay unit configured to transfer the signal loaded on the first first-node to a second first-node and the signal loaded on the first second-node to a second second-node, wherein the first delay unit is further configured to select one of the signal loaded on the first first-node and the signal loaded on the first second-node in response to the first up/down signal, delay the selected signal by a first delay value and transfer the delayed signal; a second phase comparison unit configured to compare a phase of a signal loaded on the second first-node and a phase of a signal loaded on the second second-node and generate a second up/down signal; a second delay unit configured to transfer the signal loaded on the second first-node to a third first-node and the signal loaded on the second second-node to a third second-node, wherein the second delay unit is further configured to select one of the signal loaded on the second first-node and the signal loaded on the second second-node in response to the second up/down signal, delay the selected signal by a second delay value and transfer the delayed signal; a first replica delay unit replicating the second delay unit and configured to transfer a signal loaded on the third first-node to a third third-node and a signal loaded on the third second-node to a third fourth-node, wherein the first replica delay unit is further configured to select one of the signal loaded on the third first-node and the signal loaded on the third second-node in response to the second up/down signal, delay the selected signal by the second delay value and transfer the delayed signal; a first delay control unit configured to compare a phase of a signal loaded on the third third-node and a phase of a signal loaded on the third fourth-node and control the second delay value of the second delay unit using a comparison result; and a third phase comparison unit configured to compare a phase of the signal loaded on the third first-node and a phase of the signal loaded on the third second-node and generate a third up/down signal.