Patent ID: 8895400

Claim:
A method of fabricating a semiconductor device, comprising: forming an isolation region in a semiconductor substrate, the isolation region defining cell active regions in a cell region and peripheral circuit active regions in a peripheral circuit region; forming a word line trench in the substrate in the cell region and an adjoining word line interconnect trench in the peripheral circuit region; forming a word line pattern in the word line trench and a word line interconnect pattern in the word line interconnect trench; forming a gate line on the substrate in the peripheral circuit region; simultaneously etching back the word line pattern and the word line interconnect pattern to form a word line extending longitudinally along a first direction in the word line trench and having a top surface lower than top surfaces of the cell active regions and a word line interconnect extending longitudinally beyond an end of the word line along the first direction in the word line interconnect trench and having a first portion connected to the word line and a top surface lower than the top surfaces of the cell active regions and a second portion extending vertically from the first portion to contact a bottom surface of the gate line overlying the first portion of the word line interconnect pattern; and forming an insulating pattern on the word line and the first portion of the word line interconnect.