Patent ID: 7501875

Claim:
A circuit arrangement for a differential voltage level shifter, comprising: first and second NFET devices coupled to one another in parallel, the first NFET device having a gate input configured to receive an input signal, and the second NFET device having a gate input configured to receive an inverted input signal; first and second PFET devices coupled to one another in parallel, the first PFET device having a gate input configured to receive the input signal, and the second PFET device having a gate input configured to receive the inverted input signal; a first transistor device coupled in series with the first and second NFET devices and coupled to a first power signal, the first transistor device having a gate input configured to receive a bias signal; a second transistor device coupled in series with the first and second PFET devices and coupled to the first power signal, the second transistor device having a gate input configured to receive the bias signal; a first load coupled intermediate a second power signal and the first NFET and second PFET devices; a second load coupled intermediate the second power signal and the second NFET and first PFET devices; and first and second outputs coupled respectively to the first and second loads.