Patent ID: 7353486

Claim:
A structure, comprising: an FPGA (Field-Programmable Gate Array) including a plurality of FPGA elements, each of the FPGA elements comprising an FPGA CLB (Configurable Logic Block), wherein each FPGA element in the FPGA is assigned an address and is configured to provide its address, wherein a first subset of the FPGA elements is configured to form a first functional block, wherein the first functional block comprises a mapped location register residing in one or more FPGA CLBs of the first functional block, and wherein the mapped location register stores the address of a current location FPGA element, the current location FPGA element being in the first functional block and the address of the current location FPGA element being specified as the location of the first functional block a first localized IO (Input/Output) circuit and a second localized IO circuit both electrically coupled to the FPGA, wherein the first functional block is formed via the first localized IO circuit, wherein the first functional block is configured to move to the second localized IO circuit, wherein a second subset of the FPGA elements are configured to form a second functional block separate from the first functional block at any time, wherein the second functional block is formed via the first localized IO circuit, and wherein the second functional block is configured to move to the second localized IO circuit.