Patent ID: 8298843

Claim:
A method of fabricating an array substrate for a liquid crystal display device, comprising: forming a first line, and a second line and a gate electrode on a substrate, the first and second lines spaced apart from each other, the gate electrode connected to the gate line, the first line, the second line and the gate electrode formed of a first metallic material; forming a gate insulating layer on the first and second lines and the gate electrode, an active layer on the gate insulating layer and an impurity-doped amorphous silicon pattern on the active layer, the gate insulating layer including a groove, the active layer and the impurity-doped amorphous silicon pattern corresponding to the gate electrode, wherein the groove exposes the substrate and is positioned between the first and second lines; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the first and second lines, the source electrode connected to the data line and spaced apart from the drain electrode; etching a portion of the impurity-doped amorphous silicon pattern using the source and drain electrode as an etching mask; forming a passivation layer, which is disposed on the data line, the source electrode and the drain electrode and includes an opening exposing a portion of the gate insulating layer and an end of the drain electrode, and a pixel electrode on the gate insulating layer and in the opening, wherein the pixel electrode contacts the end of the drain electrode; and wherein the step of forming the first line, the second line and the gate electrode includes forming a dummy metal pattern in the groove.