Patent ID: 6954105

Claim:
An amplifier comprising: an output stage comprising a first output transistor having a first conduction terminal connected to a supply voltage, a second conduction terminal, and a control terminal, and a second output transistor having a first conduction terminal connected to the second conduction terminal of said first output transistor and defining an output of the amplifier, a second conduction terminal connected to a reference voltage, and a control terminal; a biasing stage for generating first and second biasing voltages at the control terminals of said first and second output transistors, respectively, based upon the supply voltage and an input signal of the amplifier; a clamping stage comprising a first clamping transistor having a first conduction terminal connected to the control terminal of said first output transistor, a second conduction terminal connected to the reference voltage, and a control terminal connected to an upper clamping voltage, said first clamping transistor thus clamping an output of said first output transistor to the upper clamping voltage, and a second clamping transistor having a first conduction terminal connected to the supply voltage, a second conduction terminal connected to the control terminal of said second output transistor, and a control terminal connected to a lower clamping voltage, said second clamping transistor thus clamping an output of said second output transistor to the lower clamping voltage; and a saturation detector connected to said clamping stage for providing a saturation signal for at least one of the output of said first output transistor being clamped to the upper clamping voltage, and the output of said second output transistor being clamped to the lower clamping voltage.