Patent ID: 7372298

Claim:
A chip with adjustable pinout function, comprising: a plurality of chip-sides; a plurality of pinouts distributed on the plurality of chip-sides, comprising: a first pinout located at a first chip-side among the plurality of chip-sides; and a second pinout located at a second chip-side among the plurality of chip-sides; a logic circuit comprising a first port and a second port, the first and second ports being for outputting signals generated by the logic circuit, and each of the first and second ports being coupled to or decoupled from the first pinout and/or the second pinout; and a selecting circuit, coupled between the first and second ports and the first and second pinouts, for controlling the first pinout to be coupled to the first port and the second pinout to be coupled to the second port in response to a first pinout function, and controlling the first pinout to be coupled to the second port and the second pinout to be coupled to the first port in response to a second pinout function; wherein the selecting circuit further controls both of the first and second pinouts to be coupled to the first port in response to a third pinout function, and controls both of the first and second pinouts to be coupled to the second port in response to a fourth pinout function.