Patent ID: 8589842

Claim:
A method, implemented on a computer system, for performing device-based random variability modeling in a timing analysis of a digital integrated circuit having a gate-level design and a device-level custom design, the method comprising: using the computer system to perform actions including: simulating operational behavior of the digital integrated circuit; deriving an algorithm from results of simulating the operational behavior of the digital integrated circuit, the algorithm modeling random delay sensitivity of the digital integrated circuit as a function of at least one user-selected circuit parameter that influences random variability in the digital integrated circuit; performing a timing analysis of the device-level custom design part of the digital integrated circuit, the timing analysis of the device-level custom design including determining a critical device in each stack of devices in the device-level custom design for a given arc transition and applying the algorithm to a predetermined number of device characteristics associated with each of the critical devices to obtain device-level random variability sensitivity values; performing a gate-level characterization of logic gates used in the gate-level design part of the digital integrated circuit, the gate-level characterization of the logic gates including determining a critical device in each stack of devices in the logic gates for a given arc transition and applying the algorithm to a predetermined number of device characteristics associated with each of the critical devices to obtain per logic gate random variability sensitivity values wherein the device-level custom design and the gate-level design are configured for integration on the same integrated circuit chip; and performing a timing analysis of the digital integrated circuit as a function of both the device-level random variability sensitivity values and the logic gate random variability sensitivity values.