Patent ID: 8796765

Claim:
An integrated circuit chip comprising: first and second wells of first and second conductivity types, respectively, formed in an upper portion of a semiconductor substrate of the first conductivity type; a first plurality of MOS transistors having a channel of the second conductivity type formed in the first well; a second plurality of MOS transistors having a channel of the first conductivity type formed in the second well, the transistors of the second plurality being inverter-connected with the transistors of the first plurality, respectively; and a protection device configured to protect the integrated circuit chip against attacks, the protection device including: a protection layer of the second conductivity type extending under and contacting the first and second wells; a lateral insulation region between the wells, said lateral insulation region extending from an upper surface of the substrate to said protection layer, wherein said lateral insulation region includes a trench with insulated walls and filled with a conductive material; and a detector associated with said lateral insulation region, said detector being configured to detect variations of a voltage of the conductive material of said lateral insulation region.