Patent ID: 7039783

Claim:
A dual apparatus using a concurrent write function, comprising a first board having a first main memory and configured to perform a concurrent write in the first main memory and in a second main memory not on the first board according to a bus snooping result; and a second board coupled to the first board with a PCI bus, and having the second main memory, and configured to perform data synchronization with the first memory according to the concurrent write procedure of the first board, wherein the first and second boards each respectively comprise: a processor configured to output data and a control signal; the first main memory or the second main memory each respectively coupled to store the data according to the control signal; and a dual controller coupled to monitor a processor bus and perform the concurrent write procedure according to the monitoring result, wherein the dual controller comprises a concurrent write PCI bridge configured to determine whether to perform a concurrent write function by snooping the processor bus, and wherein the dual controller of the first board is configured to perform the concurrent write procedure with the second board through the PCI bus, and wherein the concurrent write PCI bridge comprises: a processor bus interface configured to monitor the processor bus of the board thereof, determine whether to perform the concurrent write function, and interface with the processor bus; a PCI bus interface configured to interface with another board using the PCI bus; a transmission buffer configured to buffer data output from the processor bus interface and output the data to the PCI bus interface; and a reception buffer configured to buffer the data output from the PCI bus interface and output the data to the processor bus interface.