Patent ID: 7433232

Claim:
An integrated memory transistor comprising: a drain terminal region and a source terminal region; a channel region arranged between the drain terminal region and the source terminal region; a control region a charge storage region arranged between the control region and the channel region; a source-side pocket doping region arranged nearer to the source terminal region than to the drain terminal region, the source-side pocket doping region comprising the same doping type as the channel region, but a different dopant concentration than the channel region; and a drain-side pocket doping region arranged asymmetrical to the source-side pocket doping region, the drain-side doping region comprising the same doping type as the channel region, but a different dopant concentration; wherein the source terminal region transports electrons to the channel region when the integrated memory transistor operates in a read mode; and wherein the source-side pocket doping region comprises a higher dopant concentration than the drain-side pocket doping region.