Patent ID: 8114725

Claim:
A method of manufacturing a MOS device having a lightly doped drain (LDD) structure, comprising: providing a first conductive type substrate; forming isolation regions in the substrate to define a device area; forming a gate structure in the device area, the gate structure having a dielectric layer, a stack layer, and subsequently forming a spacer layer on sidewalls of the stack layer; after forming the spacer layer on the sidewalls of the stack layer, implanting second conductive type impurities into the substrate with a tilt angle to form an LDD structure, wherein at least some of the impurities are implanted into the substrate through the spacer to form part of the LDD structure below the spacer layer, and the impurities are distributed with a trapezoid shape and a gradient concentration extending fully under the spacer from cross-section view, wherein the LDD structure does not exist before forming the spacer layer on sidewalls of the stack layer and no other spacer is formed after the LDD structure is formed; and implanting second conductive type impurities into the substrate to form source and drain, wherein the implanting steps to form the LDD structure and the source and drain are performed sequentially without any deposition step in between.