Patent ID: 8436685

Claim:
An oscillating circuit comprising: a variable frequency oscillating circuit configured to generate a clock signal whose frequency increases in response to an up-signal and decreases in response to a down-signal, the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency; a first delay circuit configured to output a first delayed clock signal by delaying the clock signal output from the variable frequency oscillating circuit by a first delay time; a second delay circuit configured to output a second delayed clock signal by delaying the clock signal by a second delay time longer than the first delay time; a first detection circuit configured to detect that a duration of a high level or a low level of the clock signal is equal to or less than the first delay time by comparing the clock signal with the first delayed clock signal; a second detection circuit configured to detect that the duration of the high level or the low level of the clock signal is equal to or more than the second delay time by comparing the clock signal with the second delayed clock signal; and an up/down control circuit configured to output the up-signal and the down-signal based on an output signal from the first detection circuit and an output signal from the second detection circuit, wherein the up/down control circuit outputs the down-signal to the variable frequency oscillating circuit upon detection by the first detection circuit of the duration of the high level or the low level of the clock signal being equal to or less than the first delay time, and wherein the up/down control circuit outputs the up-signal to the variable frequency oscillating circuit upon detection by the second detection circuit of the duration of the high level or the low level of the clock signal being equal to or more than the second delay time.