Patent ID: 7941687

Claim:
A timer cell comprising: a master counter having a clock input, a reload count input, direction input, a count output, and a rollover output; a count limit register having a sync control input, a rollover input, and a reload output, said count limit register reload output coupled to said master counter reload count input, said count limit register rollover input coupled to said master counter rollover output; a begin/end detection logic block having an output, said begin/end detection logic block output coupled to said master counter direction input; a one or more match registers each having a count input, each having a reload input, and each having a plurality of outputs, said one or more match registers count input coupled to said master counter count output; a one or more match reload registers each having a reload input, and each having an output, said one or more match reload registers each output coupled to a corresponding said one or more match register each reload input, said one or more match reload registers each reload input coupled to said master counter rollover output; an interrupt control logic block having a plurality of inputs and an output, said interrupt control logic block plurality of inputs coupled to said master counter rollover output and said begin/end detection logic block output and one or more of said match registers said each plurality of outputs, said interrupt control logic block output capable of generating an interrupt request; a status register having one or more inputs and one or more outputs, said status register one or more inputs coupled to one or more of said match registers said each plurality of outputs; a port register having one or more inputs, one or more I/Os (inputs/outputs), a sync control output, and a direct control input/output, said port register one or more inputs coupled to one or more of said status register one or more outputs, said port register direct control input/output capable of being coupled to a direct control logic block, said port register one or more I/Os capable of being coupled to a I/O logic block; and a sync control logic block having an input, a global sync input, and an output, said sync control logic block input coupled to said port register sync control output, said sync control logic block global sync input capable of receiving a global sync signal, and said sync control logic block sync control output coupled to said count limit register sync control input.