Patent ID: 7653805

Claim:
A semiconductor device for performing data processing by performing a plurality of computations in cycles, comprising: a pipeline comprising a first computing unit and a second computing unit connected to the first computing unit, the first computing unit comprising: a first data line for receiving data; a first control line for receiving a rule signal; a first circuit information control unit configured to store, before the data processing, first circuit information items, and to output one of the first circuit information items indicated by the rule signal received via the control line in a first cycle of the data processing; a first processing element configured to construct a first execution circuit according to one of the first circuit information items, to perform a computation using data from the data line, and to output a first computation result; a first data register for storing the first computation result, and for outputting the first computation result in a second cycle; and a first control register for storing the rule signal and for outputting the rule signal in the second cycle, the second computing unit comprising: a second data line for receiving the first computation result: a second control line for receiving the rule signal from the first control register a second circuit information control unit configured to store, before the data processing, second circuit information items, and to output one of the second circuit information items indicated by the rule signal received via the second control line in the second cycle; a second processing element configured to construct a second execution circuit according to one of the second circuit information items, to perform a computation using the first computation results, and to output a second computation result; a second data register for storing the second computation result, and for outputting the second computation result in a third cycle; and a second control register for storing the rule signal and for outputting the rule signal in the third cycle, and a controller configured to control output timing of the rule signal to the first control line and to control output timing of the data to the first data line in the first cycle, so that the first computing unit and the second computing unit are operated as a pipeline.