Patent ID: 7872542

Claim:
An integrated circuit comprising: a delay lock loop (DLL) circuit configured to generate (i) a plurality of incremental delay line signals and (ii) a delay line output signal, wherein the plurality of incremental delay line signals and the delay line output signal are generated based on a clock signal received from an oscillator; a pulse-width modulation (PWM) control module configured to generate a PWM control signal; a tunable circuit configured to tune said oscillator based on said delay line output signal, said PWM control signal, and one of said incremental delay line signals; a multiplexer configured to select a delay line signal based on said PWM control signal and one of said incremental delay line signals; a latch configured to generate an adjustment signal based on said selected delay line signal and said delay line output signal; and a switch configured to enable current flow to said tunable circuit based on said adjustment signal.