Patent ID: 7979684

Claim:
An integrated circuit comprising: a normal context circuit comprising: a normal context multiplexer including a first input, a second input, and an output; a front normal latch element including a front normal latch output, the front normal latch element operatively coupled to the output of the normal context multiplexer; and a back normal latch element operative to receive first data from the front normal latch element during a first clock phase and to transmit the first data during a second clock phase; a shadow context circuit comprising: a shadow multiplexer including a first input to receive the first data from the back normal latch element, wherein the shadow multiplexer further includes an output; a front shadow latch element operative to receive the first data from the shadow multiplexer and to output second data; and a back shadow latch element operatively coupled to the second input of the normal context multiplexer and operative to receive the second data from the front shadow latch element and to provide the second data to the normal context multiplexer; and clock logic operative to selectively provide a first clock to the front normal latch element, a second clock to the back normal latch element, a third clock to the front shadow latch element, and a fourth clock to the back shadow latch element based on a mode of operation.