Patent ID: 8339302

Claim:
An analog to digital converter, comprising: a first sample circuit having an input coupled to an analog input that takes a sample of the analog input during a first phase of a clock; a second sample circuit having an input coupled to the analog input that samples the analog input during a second phase of the clock; and a comparator having an input coupled to the output of the first sample circuit and the output of the second sample circuit wherein the comparator compares a reference to the output of the first sample circuit during a non-overlapping time between an end of the first phase and beginning of the second phase and compares the reference to the output of the second sample circuit during a non-overlapping time between an end of the second phase and beginning of the first phase; wherein the first sample circuit couples the sample of the analog input taken by the first sample circuit to the input of the comparator during the non-overlapping time between the end of the first phase and the beginning of the second phase and the second sample circuit couples the sample of the analog input taken by the second sample circuit to the input of the comparator during the non-overlapping time between the end of the second phase and the beginning of the first phase.