Patent ID: 7414275

Claim:
In an integrated circuit device having transistors and interconnecting metallization to minimize current limiting mechanisms including electromigration comprising: a plurality of transistors having first, second and third elements; interconnecting metal wires of a number of a number of levels including metal level one (M 1 ), metal level two (M 2 ), metal level three (M 3 ) and metal level four )M 4 ), and interlevel vias for connecting separately first and second elements; and a pyramid or staircase multi-level metallization with wide M 2 , M 3 and M 4 overlap metalization planes at the ends of the device and normal finger metallization M 1 , M 2 , M 3 and M 4 at the center so as to smooth the diagonal current flow from the wide overlap planes into the narrower fingers in the center of the device.