Patent ID: 8775780

Claim:
A central processing unit comprising: first internal registers configured for use in executing machine instructions; second internal registers communicably coupled to a plurality of disjoint memory space wherein the second internal registers are configured to designate one or more of the memory spaces as an active memory space and to designate one or more of the memory spaces as a standby memory space, and to switch designation of the one or more active memory spaces to standby while switching designations of the one or more standby memory space to active, wherein the respective switch in designations between the memory spaces triggers clearing of the first internal registers and loading of machine instructions into the first internal registers from the one or more of the memory space being redesignated as the active memory space, the clearing and loading occurring before the first internal registers access the memory space redesignated to active, wherein the second internal registers are further configured to direct an operating system to boot into the inactive memory space during processor idle time with respect to the active memory space.