Patent ID: 8745419

Claim:
A computer processor comprising: a pipeline including a decode pipe; and a logical power throttling unit coupled to the decode pipe and configured to receive a power throttling output signal, and control a rate of execution of instructions by the decode pipe, wherein the power throttling output signal indicates that an average number of instructions executed by a core is to be one of increased, decreased, or remain at a same value, whereupon determining that the power throttling output signal satisfies a predetermined criterion, the logical power throttling unit configures the decode pipe to one or both increase the number of idle processor cycles between processor cycles in which instructions are decoded, and decrease the number of instructions decoded in a processor cycle, to reduce, for a time period, an average number of instructions decoded per processor cycle, whereupon expiration of the time period, the power throttling output signal is determined again, and used to further control the rate of execution of instructions by the decode pipe.