Patent ID: 7159219

Claim:
An integrated circuit structure for controlling data processing by a shared network resource according to a scheduling scheme, wherein the data is supplied from a plurality of network users, each network user assigned a data processing priority, said integrated circuit structure comprising: a first circuit module capable of commanding one of a plurality of scheduling schemes responsive to control signals input thereto; a plurality of processing blocks each responsive to data supplied from a different priority user, each one of the plurality of processing blocks indicating whether data from an associated user is waiting to be processed; a second circuit module responsive to the first circuit module and the plurality of processing blocks, wherein the second circuit module commands a first, second or third scheduling scheme, wherein the first scheduling scheme processes user data according to a user's priority when user data is waiting to be processed, and wherein the second scheduling scheme processes all data of a highest priority user whenever highest priority user data is waiting to be processed followed by data of all users having data waiting to be processed according to the user's priority, and wherein the third scheduling scheme processes data from all users during a time interval.