Patent ID: 7949832

Claim:
A system comprising: a plurality of agents configured to cache data, wherein the plurality of agents are coupled to an interconnect that comprises an address interconnect and a data interconnect, and wherein the plurality of agents are configured to source memory requests on the address interconnect; a cache coupled to the interconnect; and a data arbiter configured to arbitrate requests for the data interconnect from the cache and the plurality of agents, and wherein the cache is coupled to the data arbiter and, in response to receiving from the address interconnect a memory request that is sourced by one of the plurality of agents, the cache is configured to speculatively request the data interconnect prior to determining whether or not the memory request is a hit in the cache, and wherein the data arbiter is configured to grant the data interconnect to the cache in response to the speculative request and further in response to determining that the cache wins the arbitration over one or more of the plurality of agents that are requesting the data interconnect, and wherein the cache is configured to detect the cache hit for the memory request, and wherein the cache is configured to transmit a first cache hit response prior to a response phase of the memory request on the interconnect to indicate the cache hit, and wherein the cache is further configured to transmit a second cache hit response on the interconnect during the response phase of the memory request.