Patent ID: 8426310

Claim:
A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor, a source/drain region corresponding to a second transistor, and a shallow trench isolation region extending from an edge of the source/drain region closest to the gate electrode to at least under the gate electrode, wherein the gate electrode corresponding to the first transistor, the source/drain region corresponding to the second transistor, and at least a portion of the shallow trench isolation region have an overlying dielectric layer, the method comprising: forming a first opening in the overlying dielectric layer, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor; after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor, and the second opening is aligned to avoid being over the shallow trench isolation region; and forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.