Patent ID: 8085604

Claim:
A method for preventing snap-back current in a circuit including a first N-channel MOS (NMOS) transistor having an associated parasitic bipolar transistor, the method comprising: connecting a second NMOS transistor in series with the first NMOS transistor; coupling a gate node of the second NMOS transistor to a bias node, such that the second NMOS transistor is in a continuous conductive state; and coupling a source node of the first NMOS transistor to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), and to provide a zero potential at the source of the first NMOS transistor when the first NMOS transistor is in a conducting state, wherein a combination of the second NMOS transistor in the continuous conductive state and the bias potential at the source of the first NMOS transistor when the first NMOS transistor is in a non-conducting state prevents the associated parasitic bipolar transistor from turning on.