Patent ID: 8649460

Claim:
A system for multi-wire encoding with an embedded clock, the system comprising: a first transmitter component, a first receiver component, and a first set of wires coupling the first transmitter component to the first receiver component; the first transmitter component being configured to: encode a first set of symbols by representing each symbol with a combination of signal levels transmitted on the first set of wires, and restrict the transmission of a first subset of the encoded symbols to a first portion of a clock cycle of a transmit clock and to restrict the transmission of a second subset of the encoded symbols to a second portion of the clock cycle of the transmit clock so as to embed a clock signal therein, the clock signal having a same frequency as the transmit clock; and the first receiver component being configured to: perform comparisons among the signal levels of the first set of wires, each comparison involving at least two wires, generate a receive clock from the embedded clock signal based on at least one of the comparisons, the receive clock having the same frequency as the transmit clock, and decode, under timing control of the receive clock, the encoded symbols based on the comparisons; a second transmitter component, a second receiver component, and a second set of wires coupling the second transmitter component to the second receiver component; the second transmitter component being configured to encode a second set of symbols by representing each symbol with a combination of signal levels transmitted on the second set of wires; and the second receiver component being configured to receive and decode the second set of encoded symbols under timing control of the receive clock; wherein the transmission of the first set and the second set of wires are grouped to reduce inter-symbol interference among the first set and the second set of encoded symbols.