Patent ID: 7610527

Claim:
A method of configuring a test output compaction arrangement, the arrangement receiving test response data from a circuit after a test pattern is applied to the circuit, the arrangement comprising blocking logic interposed between the circuit and a temporal compactor, the blocking logic responsive to control signals from a control signal generator so as to selectively block test response data from propagating to the temporal compactor, the method comprising: identifying unknown values and fault effects in the test response data which would propagate to the temporal compactor when a test pattern in a set of test patterns is applied to the circuit; assigning specified bits in a control pattern associated with the test pattern to block the unknown values from entering the temporal compactor and to propagate selected fault effects to the temporal compactor, the fault effects selected so as to balance the number of specified bits across the set of test patterns, the control patterns with the assigned specified bits used to compute the control signals to be generated by the control signal generator for the blocking logic.