Patent ID: 7698615

Claim:
A semiconductor memory device comprising: a memory cell array comprising a single-level cell area and a multi-level cell area; a command decoder which receives a command from an external source and decodes the command; an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area; a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result; and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signals, wherein the logic circuit comprises: a first logic circuit which generates a control signal for driving the single-level cells, in response to a first enable control signal output from the command flag generation unit; a second logic circuit which generates a control signal for driving the multi-level cells, in response to a second enable control signal output from the command flag generation unit; and an error control logic circuit which performs an error control operation in response to a third enable control signal output from the command flag generation unit.