Patent ID: 7111153

Claim:
An apparatus, comprising: a processor having a resource scheduler having one or more requests waiting for data to be loaded into a data cache including a first level cache (FLC), an instruction queue to receive the one or more requests from one or more instruction sources, one or more schedulers to schedule the one or more requests and to pass the one or more requests on to an execution unit having the data cache, a replay controller/checker (replay checker) to check contents of the data cache and to replay the one or more requests if the data is not located in the data cache, and a reorder buffer to store the one or more requests that are replay safe; and a memory controller coupled with the processor, the memory controller having an early data ready mechanism to detect readiness of the data one or more bus clocks prior to the data being ready to be transmitted to the processor, and to transmit an early data ready indication to the processor to drain the one or more requests from the resource scheduler.