Patent ID: 8426305

Claim:
A method of fabricating integrated circuitry, comprising: forming a conductive node on a substrate; forming a conductive metal line over the conductive node, the conductive node and the conductive metal line having a first interlevel dielectric therebetween, the conductive metal line having a portion having a passageway extending internally therethrough to the first interlevel dielectric, the passageway being filled with a first dielectric material; forming a second interlevel dielectric over the conductive metal line, at least one of the first interlevel dielectric, the second interlevel dielectric, and the first dielectric material comprising silicon dioxide; etching a common contact opening through the second interlevel dielectric, through the first dielectric material within the passageway, and through the first interlevel dielectric to the conductive node, the etching removing some material of the conductive metal line to enlarge the passageway; and providing interconnecting conductive material within the common contact opening including the enlarged passageway.