Patent ID: 7800696

Claim:
A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors and which is charged/discharged by turning on/off gates of the charging and the discharging MOS transistors, and wherein the plurality of switched capacitor units are connected such that the input signal is input in common to each of drains of the charging MOS transistors and such that the capacitive elements are charged as well as such that the capacitive elements are discharged to allow the output signal to be output from each of drains of the discharging MOS transistors; and a switching control unit that performs on/off control of each of gates of the charging and the discharging MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence, wherein with respect to the two adjacent switched capacitor units of the plurality of switched capacitor units, the respective charging MOS transistors are adjacent to each other and the respective discharging MOS transistors are adjacent to each other, and drains of the respective charging MOS transistors are common and drains of the respective discharging MOS transistors are common.