Patent ID: 7826583

Claim:
A clock data recovery apparatus comprising: a phase locked loop unit for outputting a plurality of clock signals having frequencies that are different from each other and lower than a frequency of data; a voltage control delay line for outputting recovered clock signals that are obtained by delaying the plurality of clock signals according to input voltage levels; a phase detection unit for outputting a plurality of recovered data in synchronization with the clock signals, respectively, and for outputting a plurality of increment signals and a plurality of decrement signals in response to a comparison of the recovered clock signals with the data, wherein the plurality of increment signals and the plurality of decrement signals have wider pulse widths than the data; a charge pump unit for driving current in response to the plurality of the increment signals and the plurality of decrement signals; and a loop filter unit for determining an amount of delay in the voltage control delay line by outputting a voltage according to the current, wherein the phase detection unit includes a latch unit for firstly latching the data in response to the plurality of clock signals, secondly latching the firstly latched data in response to the plurality of the clock signals, and outputting the secondly latched data as the plurality of recovered data.