Patent ID: 8438358

Claim:
A method for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters, the method comprising: providing an SoC with an internal hardware-enabled memory speed control logic (MSCL) core; accessing an array of SoC memory control parameter registers; selecting a set of parameters from one of the registers; delivering the selected set of parameters to an SoC memory controller, to replace an initial set of parameters; wherein delivering the selected set of parameters to the SoC memory controller includes the MSCL: asserting a hold signal, so that no new memory transactions are generated by a processor; waiting for current memory transactions to complete; sending a self-refresh command to the memory controller; writing the selected parameters into the memory controller; deasserting the self-refresh command; and, subsequent to deasserting the self-refresh command, commanding the memory controller to perform a memory test, to verify that the off-SoC memory is operational; if the memory test passes, proceeding to the deassertion of the hold signal; and, if the memory test fails, then resending the self-refresh command and reinstalling the initial set of parameters; deasserting the hold signal; the memory controller managing an off-SoC memory using the delivered set of parameters; wherein the delivered set of parameters are modified without resetting the system and without losing data in the memory.