Patent ID: 8525334

Claim:
A semiconductor package comprising: a first semiconductor device; a first patterned dielectric layer, a conductive redistribution layer in electrical contact with said first semiconductor device, and a second patterned dielectric layer disposed on said first semiconductor device; said conductive redistribution layer being selectively coupled to a first patterned conductive attach material; a second semiconductor device being in electrical contact with said first patterned conductive attach material; a second patterned conductive attach material formed over said second semiconductor device, a first layer of said second patterned conductive attach material selectively coupled to said conductive redistribution layer, a second layer of said second patterned conductive attach material selectively coupled to said second semiconductor device; a height of said first layer of said second patterned conductive attach material substantially coplanar with a height of said second layer of said second patterned conductive attach material so as to be together mechanically and electrically connectable to a printed circuit board.