Patent ID: 8719316

Claim:
A computer system, comprising: one or more hardware processors; a master data store; a plurality of non-master data stores; a write agent that is communicatively coupled to the plurality of non-master data stores and to the master data store; and a write manager that is communicatively coupled to the master data store and to the write agent, wherein the write manager is configured to perform at least the following upon determining that the master data store and the plurality of non-master data stores are to be atomically written to: instructing the write agent to delay write to one or more of the plurality of non-master data stores; after instructing the write agent to delay write, and within the period for the delay, attempting to write to the master data store; and when the attempt to write to the master data store is successful, sending a subsequent instruction to the write agent, instructing the write agent to initiate the delay write to the one or more of the plurality of non-master data stores; and wherein the write agent is configured to perform at least the following upon receiving instruction to delay write to one or more of the plurality of non-master data stores: when the subsequent instruction has been received from the write manager prior to expiration of the period for the delay, the subsequent instruction indicative of the write master having made an associated write by in the master data store, performing the write to the one or more of the plurality of non-master data stores based upon receipt of the subsequent instruction; and when the subsequent instruction has not been received from the write manager prior to expiration of the period for the delay, (i) confirming the presence of an associated write by the write master in the master data store, and (ii) when the associated write is confirmed to exist in the master data store, performing the write to the one or more of the plurality of non-master data stores.