Patent ID: 8603893

Claim:
A method for fabricating a FinFET integrated circuit comprising: providing a semiconductor substrate; forming a patterned hard mask overlying the semiconductor substrate, the patterned hard mask defining locations of a regular array of a plurality of fins; removing portions of the patterned hard mask using a cut mask to form a modified hard mask; etching the substrate using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches; at least partially removing selected ones of the plurality of fins to form isolation regions; and depositing an insulating material to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins, wherein at least partially removing selected ones of the plurality of fins comprises: etching dummy fins positioned between regions of the integrated circuit comprising transistors of opposite polarity; etching portions of ones of the plurality of fins to provide isolation between transistors of the integrated circuit of the same polarity; depositing an organic planarizing layer to fill the trenches; forming a photolithographic mask layer overlying the organic planarizing layer and exposing a portion of the organic planarizing layer overlying dummy fins and a portion of the organic planarizing layer overlying the portions of ones of the plurality of fins; etching the organic planarizing layer and a top portion of the dummy fins and a top portion of the portions of ones of the plurality of fins; removing the organic planarizing layer; partially filling the trenches with a flowable chemical vapor deposited oxide; depositing a high density plasma oxide overlying the flowable chemical vapor deposited oxide; and planarizing the high density plasma oxide and removing a top portion of the fins.