Patent ID: 7856528

Claim:
A solid state storage system comprising: a plurality of FLASH memory chips, each of the FLASH memory chips including a physical memory space that is divided into blocks, with each block being divided into a plurality of pages, with each block reflecting a grouping of memory locations that are erased at the same time and each page reflecting a memory location to which a number of bits of data can be written; a system controller; and a plurality of data buses, each data bus coupling the system controller to one or more FLASH memory chips; wherein the system controller is configured to: (i) store data in the FLASH memory chips in the form of page stripes, each page stripe comprising a plurality of pages of data stored in the FLASH memory chips, with each of the plurality of pages in the page stripe being stored in a FLASH memory chip that is different from each of the FLASH memory chips in which the other pages of data within the page stripe are stored, (ii) maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that include memory locations previously used to store data in a page stripe having a first number of pages and that are currently available for storage of data; and (iii) dynamically assemble the page stripes using the information contained in the one or more buffers, where the number of pages to be included in a page stripe is based on the information contained in the one or more buffers and the number of pages varies from the first number of pages of to a second number of pages, where the first number is different from the second number and where at least one dynamically assembled page stripe has the second number of pages and includes a storage location previously used to store data in a page stripe having the first number of pages.