Patent ID: 7973684

Claim:
An integrated circuit having an auto-calibration circuit to minimize input offset voltage in an operational amplifier, comprising: an operational amplifier having differential inputs, an output and a digitally controlled input offset voltage compensation circuit; and an auto-calibration circuit comprising a voltage comparator having first and second inputs, a voltage reference coupled to the first input of the voltage comparator, a voltage offset trim digital-to-analog converter (DAC), voltage offset calibration switches, a successive approximation register (SAR) having an input coupled to an output of the voltage comparator and outputs coupled to the voltage offset trim DAC, and calibration logic; wherein when an event occurs the calibration logic controls the voltage offset calibration switches to couple the differential inputs of the operational amplifier to the voltage reference and the output of the operational amplifier to the second input of the voltage comparator; whereby the voltage comparator causes the SAR to change output values to the voltage offset trim DAC so as to minimize an input offset voltage of the operational amplifier during an auto-calibration cycle initiated by the event.