Patent ID: 7005377

Claim:
A bimetal layer manufacturing method, comprising: providing a semiconductor substrate which has a first metal layer of a selected pattern formed thereon and forming a first dielectric layer on the surfaces of the substrate and the first metal layer; forming a SOG layer on the surface of the first dielectric layer to flatten the surface thereof; forming a second dielectric layer and forming required via holes on the second dielectric layer, the SOG layer and the first dielectric layer until reaching the first metal layer; forming a linear layer through plasma enhance chemical vapor deposition (PECVD); removing selectively the linear layer not required in downstream fabrication processes through an anisotropic plasma etching process, and maintaining the linear layer on a side wall of the via holes; and forming a second metal layer pattern to obtain a desired MIM capacitor; wherein the second metal layer forms a connection plug which is prevented from direct contact with the SOG layer by the linear layer on the side wall.