Patent ID: 7003636

Claim:
A memory control circuit enabling a memory to be accessed from a first processing device in response to a first processing request signal, and enabling the memory to be accessed from a second processing device in response to a second processing request signal, comprising: a watching circuit, which receives the first and second processing request signals, the watching circuit observing, based on these signals, whether the first and second processing devices request access to the memory, the watching circuit outputting a watched signal, an address generating circuit generating and outputting a first address signal in response to the first processing request signal, and generating a second address signal in response to the second processing request signal, a selection circuit, which is responsive to a selection signal, outputting one of the first and second address signals to the memory, and a control circuit generating the selection signal and an enable signal for enabling memory, the control circuit outputting the selection signal for selecting the first address signal prior to the second address signal when the observations of the watching circuit indicates that both of the first and second processing devices request access to the memory, wherein the enable signal has a voltage level, which designates the memory to be enabled, at the time the first and second processing request signal has the voltage level for requesting access to the memory, and wherein a period that the enable signal has the voltage level, which designates the memory to be enabled, is longer than a period that the watched signal form the watch circuit has the voltage level that both of the first and second processing devices request access to the memory.