Patent ID: 7328381

Claim:
A system for testing at least one memory module having a memory hub coupled to a communications link and a plurality of memory devices coupled to the memory hub, the system comprising: a tester coupled having a memory bus, the tester being operable to transfer memory signals to and from the memory bus; and a test interface circuit having a memory interface coupled to the tester through the memory bus, the test interface circuit being coupled to the at least one memory module through the communications link, the test interface circuit being operable to couple test signals to the memory hub in the memory module through the communications link responsive to command, address and data signals received from the tester, the test interface circuit further being operable to receive signals from the memory hub in the memory module through the communications link indicative of the response of the memory module to the test signals and to provide corresponding results data to the tester, wherein the test interface circuit comprises: a memory interface coupled to the tester through a data bus and at least one command and address bus; a cyclic redundancy generator coupled to receive signals from the memory interface and operable to generate error checking code signals corresponding thereto; a frame builder circuit coupled to receive the signals from the memory interface and the error checking code signals from the cyclic redundancy generator and to convert the signals to a write signal packet; and a frame transmitter coupled to receive the write signal packet from the frame builder, the frame transmitter being operable to transmit the write signal packet to the at least one memory module through the communications link.