Patent ID: 6994949

Claim:
A method for manufacturing multi-level interconnection lines of a semiconductor device comprising: forming a first interconnection line in a second interlayer insulating layer and a first etching stop layer sequentially formed on a first interlayer insulating layer disposed on a semiconductor substrate; forming a third interlayer insulating layer on the first interconnection line and the first etching stop layer; forming a second etching stop layer on the third interlayer insulating layer; forming a via hole exposing the first interconnection line by selectively etching the second etching stop layer and the third interlayer insulating layer; forming an etching stop pattern around an inlet of the via hole by selectively etching the second etching stop layer leaving a portion of the second etching stop layer around the inlet of the via hole and exposing a portion of the third interlayer insulating layer; forming a fourth interlayer insulating layer on the portion of the second etching stop layer disposed around the inlet of the via hole and the exposed portion of the third interlayer insulating layer and partially covering the via hole; forming a trench by selectively etching the fourth interlayer insulating layer to expose the portion of the second etching stop layer disposed around the via hole; and forming a conductive layer in the trench and in the via hole so that the conductive layer at least partially covers the portion of the second etching stop layer disposed around the inlet of the via hole.