Patent ID: 7430703

Claim:
An integrated circuit having memory, the memory accessed from data lines in multiple group increments, wherein a group has a plurality of bits, the integrated circuit comprising: first data registers coupled to the data lines, the data lines selectively coupled to a portion of the memory for a read of data stored in the portion of the memory, the data including error correction bits, the read including providing in parallel in the multiple group increments the data stored in the portion of the memory; distributed error correction coding circuitry coupled to the data lines, each of the data lines being tapped to obtain the data from the read of the portion of the memory, the data lines being selectively tapped to provide the data to flow in parallel in a first direction and in a second direction, the first direction to provide the data to the first data registers, the second direction to provide the data to be propagated in an error checking matrix of the distributed error correction coding circuitry; and wherein error checking of the data is done inline with the read of the data and not from the data as output from the first data registers.