Patent ID: 8421658

Claim:
A pipelined-compensation Successive-Approximation Register (SAR) digital-analog converter comprising: a binary-weighted X-side capacitor array having first capacitors with weighted capacitance values, wherein the first capacitors connect to a first charge-sharing line and to a plurality of first switches; a calibration Y-side capacitor array having second capacitors with weighted capacitance values, wherein the second capacitors connect to a second charge-sharing line and to a plurality of second switches; an analog comparator that compares the first charge-sharing line to the second charge-sharing line and generates a compare output; a compensation register that stores a compensation value that represents a capacitance error; calibration registers that store calibration values for capacitors in the binary-weighted X-side capacitor array, the calibration values representing capacitance errors; a compensation capacitor controller that reads the compensation value from the compensation register and applies the compensation value to the plurality of second switches to cause the calibration Y-side capacitor array to compensate for a capacitance error in the binary-weighted X-side capacitor array; a first compute engine that reads calibration values from the calibration registers and generates a predicted-0 compensation value by assuming that the analog comparator generates the compare output in a first state; a second compute engine that reads calibration values from the calibration registers and generates a predicted-1 compensation value by assuming that the analog comparator generates the compare output in a second state; a mux that receives the predicted-0 compensation value from the first compute engine and receives the predicted-1 compensation value from the second compute engine, the mux outputting as a next compensation value the predicted-0 compensation value when the compare output in the first state, and outputs as the next compensation value the predicted-1 compensation value when the compare output in the second state; wherein the next compensation value from the mux is stored into the compensation register as the compensation value for a next bit that is converted after a current bit, whereby compensation values are pre-computed based on prediction of the compare output.