Patent ID: 8406056

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines; a selection transistor configured to select the word lines; and a control circuit configured to control potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read, and erase operations of data with respect to the memory cells, wherein the memory cell array includes at least one block including at least one of the word lines, and the selection transistor is formed on a well region, wherein when a read operation is performed, a first negative voltage is supplied to a well region of a selected block, a first voltage (the first voltage>=the first negative voltage) is supplied to a selected word line of the selected block, and a second voltage (the second voltage>=the first negative voltage) is supplied to a non-selected word line of the selected block, after the select transistor of the selected block is activated, and a second negative voltage is supplied to a well region of a non-selected block, a word line of the non-selected block is set floating state after the select transistor of the non-selected block is turned off.