Patent ID: 7220990

Claim:
A system for evaluating a fabrication of a wafer that includes one or more die, the system comprising: a plurality of test structures disposed on at least some of the one or more die, wherein the plurality of test structures are identifiable as belonging to one or more classes in a plurality of classes, and wherein each class of test structures includes; a combination of device and interconnect elements that are provided on the die prior to the fabrication being completed, wherein the combination can be activated to cause an electrical activity that is detectable without affecting a usability of a chip formed from the die after fabrication is completed; wherein each combination is configured so that (i) the electrical activity of that combination identifies a value that indicates an attribute or result of one or more steps in the fabrication, and (ii) the electrical activity of that combination is not or is less indicative of an attribute or result of at least another step in the fabrication; wherein the value of each fabrication step in the class of test structures can be used, either individually or in combination with the value of one or more fabrication steps from another class of test structures, to determine information on a result of a particular fabrication step.