Patent ID: 7308540

Claim:
A computer memory arrangement, comprising a first plurality of input port facilities that are collectively coupled through a first router facility to selectively feed a second plurality of memory modules, and furthermore comprising an output port facility that is fed collectively by said second plurality of memory modules, said computer memory arrangement comprising an access detection facility for detecting simultaneous and conflicting accesses occurring through more than one of said first plurality of input port facilities for a particular memory module, and for thereupon allowing only a single one among said simultaneous and conflicting accesses while generating a stall signal for signaling a mandatory stall signal to any request source pertaining to another request, and a respective arbiter for upon finding plural concurrent access requests for access to an associated memory bank, generating an arbitrage signal that singles out a particular one of said concurrent access requests for exclusive handling thereof in preference to further access requests, and queueing said further access requests in the request queue in question, while said signaling said stall signal exclusively under control of an ORED full signalization of said request queue.