Patent ID: 7518921

Claim:
A semiconductor memory device comprising: memory cell units in which a plurality of memory cells are connected in series, the memory cells including a charge accumulation layer and a control gate formed on the charge accumulation layer; a memory cell array in which the memory cell units are disposed; a word line which is connected to the control gates of the memory cells; a bit line which is electrically connected to drains of the memory cells positioned on one end sides of the memory cell units; a source line which is electrically connected to sources of the memory cells positioned on the other end sides of the memory cell units; a sense amplifier which amplifies data read from the memory cell onto the bit line; a row decoder which selects the word line; and a source line driver circuit which is arranged in the row decoder and applies a first voltage to the source line, the source line driver being controlled by control signals independent of control of the row decoder.