Patent ID: 7473579

Claim:
A method for semiconductor chip-to-package integration comprising steps in an order of: removing a portion of a substrate to create a plurality of patterned and recessed positions for a plurality of semiconductor chips to be placed within the patterned and recessed positions, where the widths of the patterned and recessed positions are slightly larger than the widths of the semiconductor chips; flipping the substrate onto a flat surface; securing the substrate to the flat surface; placing the semiconductor chips in the patterned and recessed positions such that trench-like regions are created between the lateral sides of the semiconductor chips and the lateral walls of the patterned and recessed positions; filling the trench-like regions with a polymer-based substance; polymerizing the polymer-based substance such that the substrate and the semiconductor chips are integrated to form a multi-chip module; removing the multi-chip module from the flat surface; and depositing a thin layer of a low dielectric constant material on a top surface of the multi-chip module.