Patent ID: 7985624

Claim:
A method of manufacturing a semiconductor device, comprising: arranging a plurality of semiconductor chips planarly between a first lead frame plate and a second lead frame plate placed opposite each other to commonly connect each of the plurality of semiconductor chips to both of the first lead frame plate and the second lead frame plate; filling a resin between the first lead frame plate and the second lead frame plate to seal the plurality of semiconductor chips; performing a first dicing on a laminated body including the first lead frame plate, the resin, and the second lead frame plate, between the adjacent semiconductor chips, to separate at least the first lead frame plate by cutting; applying plating to the laminated body with at least the first lead frame plate being separated by cutting such that the plating is not provided on portions of the first lead frame plate corresponding to the semiconductor chips that exclude an electrical pathway between the first and second lead frame plates; and performing a second dicing on a remainder of the laminated body between the adjacent semiconductor chips, to separate the laminated body into individual semiconductor devices.