Patent ID: 8051395

Claim:
A method of assigning labels to nodes of integrated circuit components to indicate swappability relationships between the nodes, the method comprising the steps of: (a) identifying a first gate instance without an assigned label; (b) determining if each input node associated with the identified gate instance has a common swappability characteristic, wherein the common swappability characteristic is chosen from the group consisting of: the node is swappable with any other input node, associated with the identified gate instance, and the node is not swappable with any other input node, associated with the identified gate instance; (c) for each input node associated with the identified gate instance that is swappable with any other input node thereof, creating a common node between the swappable input nodes and linking the common node to the identified gate instance, and assigning each swappable input node a first set of swappability labels, using a computer; (d) for each input node associated with the identified gate instance that is not swappable with any other input node thereof, assigning each non-swappable input node a second set of swappability labels; and (e) repeating all previous steps for each gate instance until no gate instances remain with unassigned labels, such that labeled nodes contain information regarding the swappability of input nodes that is used for circuit analysis.