Patent ID: 7414293

Claim:
A semiconductor device comprising: an n channel conductivity type field effect transistor having a channel forming region formed in a first region on a main surface of a semiconductor substrate, wherein the n channel conductivity type field effect transistor has a source region and a drain region formed in the semiconductor substrate such that the channel forming region is formed between the source region and the drain region; a p channel conductivity type field effect transistor having a channel forming region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region, wherein the p channel conductivity type field effect transistor has a source region and a drain region formed in the semiconductor substrate such that the channel forming region is formed between the source region and the drain region; and a film for self alignment contact formed over the n channel conductivity type field effect transistor and the p channel conductivity type field effect transistor and covering a gate electrode of the n channel conductivity type field effect transistor and gate electrode of the p channel conductivity type field effect transistor, wherein a gate length of the n channel conductivity type field effect transistor is less than 0.1 μm, wherein the gate length of the p channel conductivity type field effect transistor is less than 0.1 μm, wherein the film is adapted to generate a stress to create a tensile stress in a direction of flow of a drain current in the channel forming region of the n channel conductivity type field effect transistor, and wherein the tensile stress in the direction of flow of the drain current in the channel forming region of the n channel conductivity type field effect transistor is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel conductivity type field effect transistor.