Patent ID: 7642105

Claim:
A manufacturing method for making partially-good memory modules from partially-good memory chips comprising: receiving partially-tested memory chips, wherein the partially-tested memory chips are packaged dice that have not been fully tested to detect all defects; pre-testing the partially-tested memory chips by applying initial test patterns to the partially-tested memory chips; wherein the initial test patterns test for defective memory blocks; counting a number of defective memory blocks found during pre-testing with the initial test patterns; discarding memory chips that have a number of defective memory blocks found during pre-testing that is more than a test threshold; passing memory chips as partially-good memory chips that have a number of defective memory blocks found during pre-testing that is less than the test threshold; for the partially-good memory chips, soldering the partially-good memory chips onto a memory module substrate to form a partially-good memory module; soldering a non-volatile memory chip onto the partially-good memory module; testing the partially-good memory module using module test patterns to locate defective memory locations; creating a defect map that represents the defective memory locations found by the module test patterns in the partially-good memory module; programming the defect map into the non-volatile memory chip to form a programmed partially-good memory module; inserting the programmed partially-good memory module into a module test socket on a target test system; and target-system testing the programmed partially-good memory module by initially copying the defect map from the non-volatile memory chip to the target test system, and executing a test program on the target test system, the test program generating memory accesses to the programmed partially-good memory module, the target test system redirecting memory accesses for the defective memory locations identified by the defect map, whereby partially-good memory chips are formed into the partially-good memory modules for use on target systems that read the defect map from the non-volatile memory chip on the partially-good memory module.