Patent ID: 8427582

Claim:
A video processor device comprising: a first image combiner unit to combine images configuring a video sub-divided into odd images having pixels in horizontal odd-numbered positions, and even images having pixels in horizontal even-numbered positions and each transmitted by the dual-link system over a first link and a second link, as a first link image of odd images and a second link image of even images to generate and output a first combination image; a second image combiner unit to combine the first link image of even images, and the second link image of odd images to generate and output a second combination image; an edge detector to detect, the number of triple edges including three consecutive edges along a horizontal direction and alternately arrayed as rising edges and falling edges respectively in the first combination image and the second combination image; and a judgment unit to compare the number of triple edges in the first combination image and the second combination image, and to judge the second link images as odd images when the number of triple edges is larger in the first combination image, and judge the first link images as the odd images when the number of triple edges is larger in the second combination image.