Patent ID: 8313997

Claim:
A manufacturing method for a semiconductor memory comprising: performing a first exposure to a memory cell array area provided on a semiconductor substrate using a first mask, the first mask comprising a first transparent substrate and a first light shielding portion provided on the first transparent substrate, the first transparent substrate having a pattern for the memory cell array area and a first area provided with no pattern thereon, the first area being positioned above a peripheral circuit area and a boundary area provided on the semiconductor substrate, the boundary area having a specific width provided between the memory cell array area and the peripheral circuit area, and the first light shielding portion being positioned above the peripheral circuit area; and performing a second exposure to the peripheral circuit area using a second mask, the second mask comprising a second transparent substrate and a second light shielding portion provided on the second transparent substrate, the second transparent substrate having a pattern for the peripheral circuit area and a second area provided with no pattern thereon, the second area being positioned above the memory cell array area and the boundary area, and the second light shielding portion being positioned above the memory cell array area.