Patent ID: 8760950

Claim:
An apparatus, comprising: a sense amplifier block, comprising: a first sense amplifier coupled to a first digit line on a first side of the sense amplifier block and to a second digit line on a second side of the sense amplifier block, wherein the second side is opposite to the first side; a second sense amplifier coupled to a third digit line on the first side of the sense amplifier block and to a fourth digit line on the second side of the sense amplifier block, wherein the third digit line is separated from the first digit line by a single digit line pitch; first and second memory sub-arrays, wherein a first plurality of memory cells of the first sub-array are coupled to the first digit line, a first plurality of memory cells of the second sub-array are coupled to the second digit line, a second plurality of memory cells of the first sub-array are coupled to the third digit line, and a second plurality of memory cells of the second sub-array are coupled to the fourth digit line; and an equilibrate circuit comprising an equilibration pass transistor coupled to the first digit line and located at least one of within the first memory sub-array and as an extension to the first memory sub-array, wherein the equilibration pass transistor is configured at less than the single digit line pitch.