Patent ID: 7461314

Claim:
A test device for testing an electronic device, comprising: a first reference clock generation unit operable to generate a first reference clock having a first frequency; a first test rate generation unit operable to generate a first test rate clock indicating a period with which a first test pattern is supplied to said electronic device, based on said first reference clock; a first driver unit operable to supply said first test pattern to said electronic device based on said first test rate clock; a second reference clock generation unit operable to generate a second reference clock that is variable within a predetermined frequency range; a first phase synchronization unit operable to synchronize a phase of said second reference clock with a phase of said first test rate clock; a second test rate generation unit operable to generate a second test rate clock indicating a period with which a second test pattern is supplied to said electronic device, based on said second reference clock having said phase synchronized; and a second driver unit operable to supply said second test pattern to said electronic device based on said second test rate clock.