Patent ID: 7373574

Claim:
A semiconductor testing apparatus, comprising: a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test and a comparison signal generating unit; the comparison signal generating unit that generates a comparison signal by combining a reference signal and the test signal, wherein the comparison signal comprises a superposed signal of the reference signal and the test signal; and a comparing unit that receives the comparison signal and a composite signal and offsets the test signal superposed in the comparison signal with the test signal superposed in the composite signal to obtain a comparison between the reference signal and a response signal, the response signal being output from the device under test in response to the test signal input to the device under test from the test signal generating unit, wherein the composite signal comprises the test signal and the response signal being superposed, wherein the device under test is determined to be defective or not based on a result of comparison by the comparing unit.