Patent ID: 8136065

Claim:
An integrated prototyping system (IPS) for a user to verify and validate an electronic system design (ESD) with design data provided as a plurality of hierarchical design elements HDEs each having its corresponding test bench and said HDEs further interacting with one another according to a pre-defined functional validation specification, said IPS comprising: a) a reprogrammable logic device (RPLD) having: an emulation timing base and an RPLD-interface for configuring, programming, controlling and monitoring a number of programmed HDEs under validation on the RPLD while receiving and outputting corresponding streams of exchanging vectors, said RPLD further switchably coupled to a plurality of external peripheral electronic devices (PED); b) an electronic design automation (EDA) simulator for reading the design data, simulating and then verifying, while receiving and outputting corresponding streams of exchanging vectors, selected members of said HDEs in conjunction with their test benches, said EDA simulator further comprising a simulator interface for controlling said EDA simulator's execution; and c) an IPS controller bridging the RPLD and the EDA simulator respectively through the RPLD-interface and the simulator interface, said IPS controller further comprising an IPS executive for progressively verifying and validating the design data by: c1) partitioning the ESD into a set of validated HDEs and a set of HDE candidates each being not yet verified; c2) verifying the HDE candidates in the EDA simulator and validating the HDE candidates in said RPLD against said functional validation specification; and c3) repeating steps c1) and c2) till all HDE candidates are verified in the EDA simulator and validated in the RPLD against said functional validation specification.