Patent ID: 7486086

Claim:
A method for measuring intrinsic capacitance of a metal oxide semiconductor (MOS) transistor, the MOS transistor comprising a first terminal, a second terminal, a third terminal and a fourth terminal, the first to the fourth terminals being respectively a gate, a drain, a source and a bulk of the MOS transistor, the first terminal being coupled to a charge based capacitance measurement circuit (CBCM) comprising a p-type MOS (PMOS) transistor and an n-type MOS (NMOS) transistor, the PMOS transistor having a source coupled to an operational voltage and a drain coupled to a drain of the NMOS transistor and the first terminal, and the NMOS transistor having a source that is grounded, the method comprising: (a) providing a first input signal to the second terminal and grounding the third terminal and the fourth terminal; (b) charging the first terminal to the operational voltage by using the capacitance measurement circuit and measuring a first current required for charging the first terminal to the operational voltage; (c) providing a second input signal to the second terminal, grounding the third terminal and the fourth terminal, and measuring a second current required for charging the first terminal to the operational voltage, wherein the first input signal and the second input signal have the same low level but different high levels; and (d) determining intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.