Patent ID: 8485416

Claim:
A bonding structure connecting portions of two semiconductor substrates, comprising: a first semiconductor substrate with an upper surface with an area carrying a CMOS structure; a second semiconductor substrate defining a cap encapsulating and covering the first semiconductor substrate, including the monolithically integrated component; an eutectic bond, comprised of a eutectic composition, bonding the second semiconductor to the first semiconductor, the eutectic bond defining a hermetic seal (S) along an outer perimeter of a portion the second semiconductor substrate, the seal enclosing the monolithically integrated component; a cavity defined by a depression in the cap on a lower side of the cap facing the upper surface of the first semiconductor, the cavity covering the area carrying the monolithically integrated component; signal routing lines extending from the monolithically integrated component; first metal posts located on a top surface of each routing line; and corresponding second metal posts extending downward from the lower surface of the second semiconductor substrate, the first and second posting in vertical alignment, the first and second posts forming thermo compression bonds bonding and electrically connecting the second semiconductor to the first semiconductor, the thermo compression bonds located inside the outer perimeter of the portion the second semiconductor substrate sealed by the eutectic bond, wherein the thermo compression bonds are harder than the eutectic bond.