Patent ID: 7393738

Claim:
A method of forming a semiconductor structure comprising the steps of: providing a substrate comprising a semiconductor on insulator (SOI) region comprising a first semiconductor material on a buried insulating layer, adjacent a bulk semiconductor region comprising a second semiconductor material, said SOI region separated from said bulk region by an insulating spacer; forming an insulating material layer atop said SOI region, said bulk region and said insulating spacer; forming a patterned mask over said insulating material layer comprising an isolation opening that exposes a region of said insulating material layer that defines an isolation region between said SOI region and said bulk semiconductor region, said isolation opening formed over said insulating spacer; performing a first etch to remove said exposed regions of said insulating material layer and an upper portion of said insulating spacer, to expose portions of said first semiconductor material and said second semiconductor material in said isolation opening, said first etch being selective to said first and second semiconductor materials, and so that said insulating spacer is recessed below the upper surfaces of said first and second semiconductor materials; then performing a second etch to remove said exposed portions of said first semiconductor material and said semiconductor material to expose portions of said buried insulating layer in said isolation opening, said second etch being selective to said insulating material layer, said buried insulating layer and said insulating spacer, such that a high aspect ratio gap, having an aspect ratio equal to or greater than about 3:1, is formed between a sidewall of said insulating spacer and said second semiconductor material; filling said high aspect ratio gap with a CVD oxide; and then filling the isolation opening with an HDP oxide to form an isolation region so that there are no voids in said isolation region.