Patent ID: 8023606

Claim:
A clock data restoration device which restores a clock signal and data based on an input digital signal, comprising: a sampler section, which receives an input of a clock signal CKXA, a clock signal CKXB, and a clock signal CK which have a same cycle T as well as the input digital signal, and which samples, holds, and outputs, in each nth period T(n) of the cycle T, a digital value DXA(n) of the input digital signal at a time t XA indicated by the clock signal CKXA, a digital value DXB(n) of the input digital signal at a time t XB indicated by the clock signal CKXB, and a digital value D(n) of the input digital signal at a time t C indicated by the clock signal CK (where t XA <t XB <t C , and n is an integer); a detection section, which receives an input of the digital value DXA(n), digital value DXB(n), and digital value D(n) which are output by the sampler section in each period T(n) and, in a case where ‘D(n−2)≠(n−1)’, detects a timing relation (called a ‘first timing relation’ hereinbelow) between a time indicated by the clock signal CKXA and a transition time of the input digital signal value based on digital value D(n−1), digital value DXA(n), and digital value D(n) and, in a case where ‘D(n−2)=D(n−1)’, detects a timing relation (called a ‘second timing relation’ hereinbelow) between a time indicated by the clock signal CKXB and a transition time of the input digital signal value based on the digital value D(n−1), digital value DXB(n), and digital value D(n), and detects a phase relation between the clock signal CK and the input digital signal based on the first timing relation and the second timing relation; a timing determination section which determines, based on the first timing relation and the second timing relation detected by the detection section, an interval 2τ between respective timings of the clock signal CKXA and the clock signal CKXB so that the time indicated by the clock signal CKXA is the center of the transition time distribution of the input digital signal value in a case where ‘D(n−2)≠D(n−1)’ and so that the time indicated by the clock signal CKXB is the center of the transition time distribution of the input digital signal value in a case where ‘D(n−2)≠(n−1)’; and a clock output section which adjusts cycle T or the phase based on the phase relation detected by the detection section so that a phase difference between the clock signal CK and the input digital signal decreases, and which outputs the clock signal CKXA, the clock signal CKXB, and the clock signal CK which satisfy relations ‘t XA =t c −T/2−τ’ and ‘t XB =t c −T/2+τ’ to the sampler section in accordance with the timings determined by the timing determination section.