Patent ID: 7796432

Claim:
A non-volatile memory device comprising: a plurality of stacked semiconductor layers; a plurality of NAND strings on the plurality of semiconductor layers, each of the plurality of NAND strings including a plurality of memory cells and at least one string selection transistor arranged in a NAND-cell array; a common bit line commonly connected to each of the NAND strings at a first end of the memory cells; a common source line commonly connected to each of the NAND strings at a second end of the memory cells; a plurality of string selection lines coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings; and a plurality of word lines coupled to the plurality of memory cells of each of the NAND strings, wherein a number of the plurality of word lines is equal to a number of the plurality of memory cells included in a single NAND string.