Patent ID: 7248665

Claim:
A prescaler, dividing an input signal into an output signal, comprising: a synchronous counter, including a first D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, being a chain of a plurality of DFFs and coupled to the control logic and the synchronous counter; wherein an output Q− from the stage DFF of the asynchronous counter is connected to the control logic, the output signal is not fed back to the control logic and each of the first NOR-Flip-Flop and the second NOR-Flip-Flop has two parallel transistors that are directly grounded, respectively.