Patent ID: 8461012

Claim:
A method for forming a semiconductor structure, the method comprising: forming a first isolation region and a second isolation region in a semiconductor substrate; forming a first conductive layer over the first isolation region and a second conductive layer over the second isolation region; forming a first dielectric layer over the first conductive layer and the second conductive layer; forming a first plurality of conductive vias extending through the first dielectric layer to the first conductive layer and electrically contacting the first conductive layer and a second plurality of conductive vias extending through the first dielectric layer to the second conductive layer and electrically contacting the second conductive layer; forming a second dielectric layer over the first dielectric layer; removing portions of the second dielectric layer to leave a first portion of the second dielectric layer over the first conductive layer and a second portion of the second dielectric layer over second conductive layer; and forming a conductive ground plane from a third conductive layer, using chemical mechanical processing (CMP), around the first portion of the second dielectric layer, around the second portion of the second dielectric layer, on and in electrical contact with the first plurality of conductive vias, and on and in electrical contact with the second plurality of conductive vias, wherein the CMP removes all of the third conductive layer that is over the first portion of the second dielectric layer and all of the third conductive layer that is over the second portion of the second dielectric layer and provides a planar top surface of the ground plane.