Patent ID: 7716401

Claim:
A memory module comprising: a plurality of semiconductor memory devices mounted on a memory module board of a memory module, each of the plurality of the semiconductor memory devices comprising: a data input buffer having a first input receiving data from a system data bus external to the memory module and a second input receiving a first reference voltage; a command/address input buffer having a first input receiving an internal command/address signal from an internal command/address bus and a second input receiving a second reference voltage different from the first reference voltage; and a first termination resistor unit of a first termination type comprising a first termination resistor having a first end connected to a power supply voltage and a second end connected to the first input of the data input buffer, the first termination resistor unit being configured as an on-die termination (ODT) of the semiconductor memory device; a second termination resistor unit of a second termination type connected at one end of the internal command/address bus and mounted on the memory module board, wherein the second termination type is different from the first termination type; and a command/address buffer mounted on the memory module board and configured to receive an external command/address signal from a system command/address bus external to the memory module, buffer the external command/address signal, and provide the buffered external command/address signal as the internal command/address signal via the internal command/address bus.