Patent ID: 7266707

Claim:
A low power consumption leakage pipeline circuit architecture comprising: a clock responsive input latch coupled to latch input data; a non-power-gated first pipeline stage for processing the latched input data and generating first processed output data; a power-gated second pipeline stage for processing the first processed output data and generating second processed output data, the power-gated second pipeline stage switching to power-gated states in response to a first control signal; a power-gated third pipeline stage for processing the second processed output data and generating third processed output data, the power-gated third pipeline stage switching to power-gated states in response to a second control signal; and a clock responsive output latch coupled to the third processed output data, wherein a power rail in the power-gated second pipeline stage is effectively coupled to a pipeline power supply before a power rail in the power-gated third pipeline stage, and wherein the power-gated second pipeline stage switches to a first power-gated state in response to a second logic state of the first control signal and the second logic state of a third control signal and switches to a second power-gated state in response to the second logic state of the first control signal and a first logic state of the third control signal.