Patent ID: 8237210

Claim:
A semiconductor apparatus comprising: an array of memory cells arranged in rows and columns, wherein each of said columns is isolated from a neighboring column by a non-intersecting shallow trench isolation region; a plurality of word lines equal in number to the number of said rows, each of said word lines coupled to a memory cell per column; a plurality of bit lines equal in number to the number of said columns, each of said bit lines coupled to a respective one of said columns; at least one source region coupled to a plurality of source lines in said array of memory cells; a first single content addressable memory cell comprising a first plurality of serially connected contacts coupling a first select plurality of said columns to a first path but not to a second path, wherein said first path is in addition to said word lines and said bit lines; and a second single content addressable memory cell comprising a second plurality of serially connected contacts coupling a second select plurality of said columns to said second path but not to said first path, wherein said second path is in addition to said word lines and said bit lines, wherein columns in said first select plurality are different from and interleaved with columns in said second select plurality.