Patent ID: 7142252

Claim:
An image processing apparatus for displaying a plurality of input data asynchronously input through different channels on one display device and converting frame rates of the input data in accordance with an output frame rate of the display device, the apparatus comprising: an input buffer unit for buffering input data which are externally and asynchronously input through at least two channels by different input clock signals and outputting buffered data as first data and first data enabling signals; a data synchronizing unit for synchronizing the first data output from the input buffer unit with an output clock signal in response to the input clock signals and the first data enabling signals and outputting synchronized data as second data and second data enabling signals in response to each of the first data enabling signals; a first memory for multiplexing the second data according to time sharing, storing the second data in different regions, and outputting the stored second data in response to a first memory enabling signal; a second memory for writing and reading data output from the first memory in response to a frame buffer control signal; a third memory for storing data output from the second memory and comprising a single output terminal for outputting the stored data as a display signal in response to a second memory enabling signal; and a memory control unit for (i) detecting underflow conditions in the first memory and detecting overflow conditions in the third memory, (ii) generating the first memory enabling signal that is applied to the first memory to control data flow between the first memory and the second memory, (iii) generating the frame buffer control signal that is applied to the second memory to control frame rates of the input data and to control frame rates of the display signal in response to the underflow and overflow conditions, and (iv) generating the second memory enabling signal that is applied to the third memory to control data flow between the second memory and the third memory.