Patent ID: 7399990

Claim:
A wafer-level package comprising: a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal; at least one external connection terminal electrically connected to said at least one non-test chip terminal; at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being coupled to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals; at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being coupled to said at least one testing member; an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and a test-purpose circuit provided on said semiconductor wafer, wherein said first end of said at least one redistribution trace is coupled to said test-purpose circuit, and said second end of said at least one redistribution trace is coupled to said at least one testing member.