Patent ID: 7026207

Claim:
A method of a filling bit line contact via, comprising: providing a substrate having a device region and periphery region, the device region having a transistor with a gate electrode, drain region, and source region on the substrate; forming a dielectric layer overlying the substrate, the dielectric layer having a bit line contact via exposing the drain region, and periphery contact via exposing the periphery region; conformally forming a doped conductive layer overlying the drain region, dielectric layer, and periphery contact via; etching the doped conductive layer to leave only a remaining portion of the doped conductive layer lower than the top surface of the gate electrode overlying the drain region; conformally forming a barrier layer overlying the dielectric layer, doped conductive layer, and periphery contact via; and forming a first conductive layer filling the bit line contact via and periphery contact via.