Patent ID: 7336093

Claim:
A test circuit for a flat panel display device, comprising: a substrate including at least one scan side, at least one data side and a pixel area; a plurality of pixel structures formed in the pixel area, each pixel structure having n sub-pixels, where n is a positive integer; a plurality of signal lines formed on the substrate, each signal line being connected to a corresponding sub-pixel; a plurality of shorting bar sets, being formed on at least one of the at least one scan side and the at least one data side, wherein the shorting bar sets are electrically connected to the signal lines and each shorting bar set is disconnected from each other, wherein the shorting bar sets respectively receive first testing signals corresponding to the signal lines for testing corresponding pixel structures; and a plurality of shorting bar buses being electrically connected to the shorting bar sets, wherein the shorting bar buses respectively receive second testing signals corresponding to the signal lines for testing corresponding pixel structures.