Patent ID: 7446596

Claim:
A charge pump stage, comprising: an NMOS section that includes: a first NMOS transistor coupled between an input node and an intermediate node, a second NMOS transistor coupled between a first NMOS gate of the first NMOS transistor and the input node for refreshing a voltage at the first NMOS gate of the first NMOS transistor, the second NMOS transistor having a second NMOS gate coupled to the intermediate node, a first transfer capacitor coupled between the input node and a first clock input terminal, the first transfer capacitor configured to receive a first clock input signal; a first coupling capacitor coupled between the first NMOS gate of the first NMOS transistor and a boost clock signal terminal, the first coupling capacitor configured to receive a boost clock signal; a PMOS section that includes: a first PMOS transistor coupled between the intermediate node and an output node; a second PMOS transistor coupled between a first PMOS gate of the first PMOS transistor and the output node for refreshing a voltage at the first PMOS gate of the first PMOS transistor, the second PMOS transistor having a second PMOS gate coupled to the intermediate node, a second transfer capacitor coupled between the output node and a second inverted clock input terminal, the second transfer capacitor configured to receive an inverted first clock signal; a second coupling capacitor coupled between the first PMOS gate of the first PMOS transistor and an inverted boost clock signal terminal, the second coupling capacitor configured to receive an inverted boost clock signal; and a stabilizing capacitor coupled between the intermediate node and a ground voltage reference.