Patent ID: 7394128

Claim:
A semiconductor memory device having a plurality of memory cells, said semiconductor memory device having a substrate, at least one wordline and first and second lines, wherein each memory cell of said plurality of memory cells comprises: a fin of semiconductor material, said fin having a top surface, first and second opposing sidewalls and first and second opposing ends, said fin extending along a first direction; channel regions in the first and second sidewalls of the fins, wherein the channel regions extends from the first end to the second end of the fin; a charge-trapping layer disposed adjacent said channel regions of said first and second sidewalls of said fin, wherein the charge-trapping layer is not disposed on said top surface of said fin; a patterned first insulating layer disposed on said top surface of said fin, said first insulating layer abutting said top surface of said fin and said charge-trapping layer; a first doped region coupled to said first end of said fin; and a second doped region coupled to said second end of said fin; wherein said at least one wordline covers said first insulating layer disposed on said top surface of said fin and said at least one wordline covers said charge-trapping layer disposed on said first and second sidewalls of said fin, and said at least one wordline extends along said first direction; and wherein said first and second lines extend along a second direction.