Patent ID: 7430148

Claim:
An integrated circuit comprising: an array of memory elements powered with a time-varying power supply level; power regulator circuitry that varies the power supply level between a higher power supply level used during normal operation and a lower power supply level used during data loading operations; and data loading circuitry that loads data into the memory elements while the power supply level is at the lower power supply level, wherein while the power supply level is at the higher power supply level, at least some loaded memory elements provide output signals at the higher power supply level, wherein each memory element comprises two cross-coupled inverters, wherein each inverter comprises a p-channel metal-oxide-semiconductor transistor and an n-channel metal-oxide-semiconductor transistor, wherein the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor in each inverter are connected in series between a positive power supply terminal at which the time-varying power supply level is supplied from the power regulator circuitry and a ground terminal.