Patent ID: 8253450

Claim:
A clock signal frequency dividing circuit which generates an output clock signal used in a target circuit that communicates with a partner circuit using a clock signal different in frequency from an input clock signal, by masking (M−N) clock pulses out of M successive clock pulses of the input clock signal based on a frequency division ratio defined by N/M (N is a positive integer and M is a positive integer larger than N) to divide a frequency of the input clock signal at N/M, comprising: a mask circuit which masks clock pulses of the input clock signal in accordance with an input mask signal, generating and outputting the output clock signal; and a mask control circuit which generates a mask signal that assigns mask timings to mask (M−N) clock pulses, to timings other than communication timings, out of timings of M successive clock pulses of the input clock signal, based on communication timing information indicating communication timings of data communication performed by the target circuit.