Patent ID: 7680986

Claim:
A computing system, comprising: one or more processors configured for multithreaded operation; a memory comprising program instructions executable by the one or more processors to implement: emulation of load-linked, store-conditional (LL/SC) synchronization primitives that employ only pointer-sized single-target synchronization operations to coordinate access to pointer-referenced LL/SC variables, wherein the emulation is lock-free, population-oblivious and space-adaptive; wherein to emulate LL/SC synchronization primitives, the program instructions are executable to implement: instantiating an instance of an LL/SC variable in memory, wherein the LL/SC variable includes an entry tag selective for a current one of two alternative pointers, the entry tag coding alternating from the current one to a non-current one of the two alternative pointers by operation of a particular one of the pointer-sized single-target synchronization operations.