Patent ID: 7737020

Claim:
A method of fabricating an integrated circuit (“IC”) comprising: providing a partially fabricated wafer; forming a first patterned metal layer with a first sacrificial material; forming an etch stop layer planar in shape and entirely atop the first patterned metal layer, with an entirety of the etch stop layer being parallel to the wafer; forming access holes in the etch stop layer directly above at least one portion of the first sacrificial material leaving at least a portion of the etch stop layer atop at least another portion of the first sacrificial layer; and then forming a second patterned metal layer with a second sacrificial material atop the etch stop layer; removing the first sacrificial material and the second sacrificial material so as to form a metal network without removing any portion of the etch stop layer; applying fluid dielectric material precursor to the partially fabricated wafer, the fluid dielectric material flowing through the access holes of the etch stop layer so as permeate the metal network; and curing the fluid dielectric material precursor to form fluid-based dielectric material in the first patterned metal layer and in the second patterned metal layer.