Patent ID: 8462097

Claim:
A gate drive circuit comprising a shift register in which plural stages are connected to each other in series, an (m)-th stage (‘m’ is a natural number) comprising: an output part receiving a first clock signal and outputting the first clock signal as a gate signal in response to a control signal and discharging the gate signal in response to a second input signal, the output part comprising a first transistor having a first channel length; a discharging part discharging the control signal to a second voltage level in response to the second input signal; a first holding part maintaining the control signal on a first node at the second voltage level in response to the first clock signal, the first holding part comprising a second transistor having a second channel length that is longer than the first channel length; a second holding part maintaining the control signal on the first node at the second voltage level in response to a second clock signal; and a reset part providing the second voltage to the first node of the output part in response to a reset signal, wherein the second transistor includes a source electrode connected to a gate electrode of the first transistor, and wherein the reset part is directly connected to the first node.