Patent ID: 7560760

Claim:
A memory device comprising: a plurality of word lines on a substrate and extending lengthwise along a row direction; a plurality of ferroelectric capacitors on the substrate, each of the ferroelectric capacitors comprising a bottom electrode, a ferroelectric layer and a top electrode, a level of the bottom electrode lower than a level of the top electrode; and a plate line extending lengthwise along the row direction on the ferroelectric capacitors connected to at least two of the plurality of ferroelectric capacitors arranged along a column direction and overlapping two adjacent ones of the word lines, wherein the plate line comprises a main plate and further comprising a local plate line arranged along the row direction and electrically connected to the main plate line, wherein the local plate line is between the main plate line and the at least two of the plurality of ferroelectric capacitors, and wherein the local plate line is electrically connected to the at least two of the plurality of ferroelectric capacitors.