Patent ID: 7546418

Claim:
A computer system, comprising: a processor; a cache associated with the processor; a system memory; a memory controller hub that is operable to track writes to the system memory by one or more bus masters operable to access the system memory; a write tracking buffer external to the processor, wherein the write tracking buffer is communicatively coupled to the cache via the processor and to the system memory, and wherein the write tracking buffer is operable to hold as entries the addresses of one or more writes to the system memory made during a period that the processor is in a low power state; wherein the memory controller hub is operable to: initialize the write tracking buffer when the processor enters a low power state; identify one or more writes to the system memory made during the period that the processor is in the low power state; determine if the write tracking buffer is full during the period that the processor is in the low power state; and if the write tracking buffer is not full, record the addresses of the one or more writes; and wherein the processor is operable to write to the system memory one or more lines of cache prior to the processor entering its low power state, and wherein the processor is operable to invalidate one or more lines of cache corresponding to the entries of the write tracking buffer upon the processor exiting its low power state.