Patent ID: 7619279

Claim:
An array of memory cells, comprising: a plurality of rows of memory cell pillars each pillar having a pair of memory cells formed thereon, each memory cell pillar isolated from an adjacent memory cell pillar by an isolation region within its row; wherein each memory cell pillar comprises: a substrate; two source regions and one drain region, the drain region vertically spaced apart from the source regions to define two separate channel regions; a floating gate located adjacent each channel region, each floating gate extending substantially vertically; and a control gate located adjacent to each floating gate; wherein every memory cell coupled to a first side of a word line is within one row of memory cells and every memory cell coupled to a second side of the word line is within an adjacent row of memory cells; wherein the memory cells of the one row of memory cells are coupled to alternating bit lines and the memory cells of the adjacent row of memory cells are coupled to alternating bit lines; and wherein the alternating bit lines coupled to the memory cells of the one row of memory cells are different from the alternating bit lines coupled to the memory cells of the adjacent row of memory cells.