Patent ID: 7869252

Claim:
A ferroelectric memory device comprising: a memory cell having a ferroelectric capacitor connected between a plate line and a bit line; a first node connected to the bit line through a charge transfer MISFET; a potential generation circuit that has a first capacitor having a first terminal connected to the first node and a first switching MISFET connected to a second terminal of the first capacitor, and is capable of setting the first node to a negative potential; and a sense amplifier connected to the second terminal of the first capacitor, wherein, when reading a charge stored in the ferroelectric capacitor, the potential generation circuit sets the first node at a negative potential and then sets the first switching MISFET to an off state, thereby setting the second terminal of the first capacitor to a floating state, and the sense amplifier amplifies a potential on the second terminal of the first capacitor in the floating state.