Patent ID: 7745879

Claim:
A high voltage fully depleted silicon-on-insulator (SOI) transistor, comprising: a SOI layer, disposed on an oxide layer of a substrate, the SOI layer having a region including a source region and a ballasted drain region separated by a channel therein; a gate structure disposed above the channel, wherein the gate structure comprises a gate and a spacer disposed on sidewalls of the gate; and at least one carrier recombination element disposed above the source region and abutting the gate structure, wherein the at least one carrier recombination element suppresses minority carrier current to prevent a parasitic bipolar effect from occurring during operation of the transistor, wherein the at least one carrier recombination element is physically and electrically connected to the channel, wherein the at least one carrier recombination element has a top surface having a portion embedded underneath the spacer disposed above the source region and a side surface disposed entirely against the spacer disposed above the source region.