Patent ID: 8080848

Claim:
A high voltage semiconductor device comprising: a first terminal and a second terminal both disposed at a top surface of a planar substrate, wherein a controllable current path extends between said first and second terminals and wherein said controllable current path includes a drift region between said first and second terminals, the drift region comprising; one or more field shaping regions laterally disposed between said first and second terminals and embedded in said drift region, wherein each of said field shaping regions comprises an electrically insulating region within which is disposed a plurality of electrically conductive regions that are electrically insulated from each other; and an active region disposed between said first and second terminals and embedded in said drift region, the active region being free of said electrically conductive regions that are disposed in said one or more field shaping regions and the active region being laterally spaced from said one or more field shaping regions; wherein the one or more field shaping regions are laterally capacitively coupled to the active region; and wherein each of said field shaping regions is capacitively coupled to each other to form a voltage divider dividing an electric potential between said first and second terminals, wherein one or more of said electrically conductive regions in each said field shaping region are isolated from any external electrical contact.