Patent ID: 8610187

Claim:
A semiconductor device comprising: a first transistor comprising: a channel formation region; a first impurity region and a second impurity region with the channel formation region interposed between the first impurity region and the second impurity region; a first insulating layer over the channel formation region; a first gate electrode over the channel formation region with the first insulating layer interposed therebetween; a first electrode electrically connected to the first impurity region; and a second electrode electrically connected to the second impurity region; a second transistor comprising: an oxide semiconductor layer; a third electrode and a fourth electrode, each of the third electrode and the fourth electrode electrically connected to the oxide semiconductor layer; a second insulating layer over the oxide semiconductor layer, the third electrode, and the fourth electrode; and a second gate electrode overlapping the oxide semiconductor layer with the second insulating layer interposed therebetween; a capacitor element comprising: the third electrode; the second insulating layer; and a fifth electrode overlapping the third electrode with the second insulating layer interposed therebetween, wherein the first gate electrode and the third electrode are electrically connected to each other.