Patent ID: 7417450

Claim:
An integrated circuit die, comprising: A. combinational logic core circuitry formed on the die; B. test access port (TAP) circuitry formed on the die and coupled to the combinational logic core circuitry, the test access port circuitry having a test data input (TDI) input lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data output (TDO) output lead; C. scan path circuitry formed on the die and coupled to the combinational logic core circuitry and the test access port circuitry; and D. die channel circuitry formed on the die the die channel circuitry having a Data I/O (DIO) bidirectional lead, a clock input (CLK) lead, a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead, the die channel circuitry including: i. a simultaneous bidirectional transceiver (SBT) connected to the DIO bidirectional lead and having an input connected to the TDO input lead, and a serial output lead; and ii. serial input parallel output (SIPO) circuitry having an input connected to the serial output lead of the simultaneous bidirectional transceiver, a clock input connected with the clock input lead, a TDI output connected to the TDI output lead, and a TMS output connected to the TMS output lead.