Patent ID: 7397882

Claim:
A digital phase locked circuit for synchronizing a phase of an output clock signal with a phase of an input clock signal wherein said output clock signal is generated by dividing a master clock signal, comprising: a phase comparing part comparing the phase of said output clock signal with the phase of said input clock signal; a phase comparison result detecting part referring to a comparison result from said phase comparing part and outputting a signal increasing/decreasing a division number for dividing said master clock signal when the phase of said output clock signal proceeds forward/recedes behind the phase of said input clock signal; a mask processing part identifying a single applied mask rate among a plurality of mask rates for masking a part of an increasing/decreasing (INC/DEC) request signal depending on a phase difference between the input clock signal and the master clock signal, wherein as the phase difference increases, the mask rate is made lower, and as the phase difference decreases, the mask rate is made higher, masking the output signal from the phase comparison result detecting part depending on the identified mask rate, and outputting the masked signal; and a dividing part obtaining the divided clock signal by controlling increasing or decreasing operation on the division number based on the outputted masked signal.