Patent ID: 7293158

Claim:
A counting mechanism in a network processor, comprising: a plurality of address registers sequentially connected to form an address pipeline to sequentially receive addresses; each received address giving a memory location to store a value of a counter; the address pipeline comprising a register that outputs a received address as a read address at a beginning of the address pipeline and a register that outputs the address as a write address at an end of the address pipeline; a plurality of incrementing registers sequentially connected to form a counter pipeline to sequentially receive counter values; each incrementing register forming a stage for incrementing a counter value and each counter value in the counter pipeline incremented at least one time; a plurality of comparators, one at each internal stage of the address pipeline, to perform address comparisons to determine if the write address matches one or more addresses in the address registers of the address pipeline, each comparison performed by a comparator providing a control signal to control whether to increment a counter in a corresponding stage of a counter pipeline; and a counter value modifier comprising the counter pipeline to increment a counter value from the read address once plus once for each address match determined by the comparators to produce an incremented counter value, and wherein a stage in the counter pipeline where an increment occurs is determined by a stage of the address pipeline where a match occurs.