Patent ID: 8148216

Claim:
A method of manufacturing a nonvolatile semiconductor memory comprising steps of: forming a gate electrode of a first select gate transistor on a gate insulating film deposited on a surface of a semiconductor substrate; forming a diffusion layer to serve as source and drain regions of the first select gate transistor by using the gate electrode as a mask; alternately depositing interlayer insulating films and control gate electrode material of memory cells on the gate electrode and the semiconductor substrate; forming gate electrode material of a second select gate transistor on an interlayer insulating film positioned at an end opposite to the semiconductor substrate; sequentially etching the gate electrode material of the second select gate transistor, the control gate electrode material and the interlayer insulating films and thereby exposing a top surface of the diffusion layer to serve as the drain region of the first select gate transistor; forming a first insulating film on a side surface of the control gate electrode material and the gate electrode material of the second select gate transistor; forming a charge storage layer on a side surface of the first insulating film; removing portions of the first insulating film and the charge storage layer deposited on the side surface of a gate electrode of the second select gate transistor; forming a second insulating film on the side surface of the charge storage layer and the gate electrode of the second select gate transistor; and forming a pillar-shaped semiconductor layer on a side surface of the second insulating film.