Patent ID: 8068319

Claim:
An integrated circuit, comprising: an electrostatic discharge (ESD) control line; a first circuit having a first ESD device and a second ESD device, each of said first and second ESD devices being coupled to (i) a first positive voltage rail, (ii) a first negative voltage rail, and (iii) said ESD control line, said first ESD device configured to activate an ESD control signal on said ESD control line when an electrostatic discharge occurs and to shunt current between said first positive voltage rail and said first negative voltage rail when said ESD control signal is activated, and said second ESD device configured to shunt current from a first I/O pad to said first negative voltage rail when said ESD control signal is activated, said first I/O pad and said second ESD device further being coupled to a first input/output (I/O) circuit; a second circuit having a third ESD device and a fourth ESD device, each of said third and fourth ESD devices being coupled to (i) a second positive voltage rail, (ii) a second negative voltage rail, and (iii) said ESD control line, said third ESD device configured to activate an ESD control signal on said ESD control line when an electrostatic discharge occurs and to shunt current between said second positive voltage rail and said second negative voltage rail when said ESD control signal is activated, and said fourth ESD device configured to shunt current from a second I/O pad to said second negative voltage rail when said ESD control signal is activated, said second I/O pad and said fourth ESD device further being coupled to a second I/O circuit; and an ESD tie cell coupled to (i) said first positive voltage rail, (ii) said second positive voltage rail, and (iii) said ESD control line, said ESD tie cell configured to close a circuit between said first positive voltage rail and said second positive voltage rail when said ESD control signal is activated.