Patent ID: 7296133

Claim:
A method in a shared processor data processing system for dynamically tuning an amount of physical processor capacity that is allocated to each one of a plurality of logical partitions to optimize interrupt processing and reduce interrupt latency, said method comprising: sharing a physical processor among said plurality of logical partitions; allocating a service window to each one of said logical partitions during each dispatch time slice; executing, by said physical processor, processes defined by a first one of said plurality of logical partitions during a first service window that was allocated to said first one of said plurality of logical partitions; dynamically determining during runtime whether a length of said first service window should be increased; in response to determining that said length should be increased, dynamically increasing said length of said first service window during runtime to optimize interrupt processing and reduce interrupt latency, said first one of said plurality of logical partitions being granted additional processing capacity of said physical processor; said step of dynamically determining during runtime whether said length of said first service window should be increased further includes: generating, by an input/output (I/O) device, an interrupt for said first one of said plurality of logical partitions; analyzing said I/O device to determine whether a latency-induced error has occurred in said I/O device; in response to determining that a latency-induced error has occurred in said I/O device, assigning a severity level to said error; and notifying a kernel process that said latency-induced error occurred and including said severity level in said notification.