Patent ID: 7106372

Claim:
An integrated circuit comprising: a color sensor array having a plurality of sensor elements of different first and second colors, arranged in rows and columns; a first reset shift register having a plurality of outputs, each output being coupled to control a reset of sensor elements of the first color that are in a respective one of the rows of the array; a second reset shift register having a plurality of outputs, each output being coupled to control a reset of sensor elements of the second color that are in a respective one of the rows of the array; a wordline shift register having a plurality of outputs, each output being coupled to control a readout of all of the sensor elements that are in a respective one of the rows of the array; and control logic coupled to feed (a) each of the first and second shift registers with a first reset bit and a second reset bit and (b) the wordline shift register with a read bit, and to operate the reset and wordline shift registers so that the first and second reset bits and the read bit shift through their respective registers while an image frame is being captured, with the first reset bit being one or more rows ahead of the read bit to mark the start of integration, and the second reset bit to generate a correlated double sampling pixel reset value after each pixel integrated intensity value, and wherein integration time for first color and second color can be set independently by using the control logic to control timing of the first reset bit fed to each of the first and second reset shift registers.