Patent ID: 7211857

Claim:
A non-volatile semiconductor memory device, comprising: a semiconductor substrate; an insulating film formed on said semiconductor substrate; a plurality of memory cells formed on said semiconductor substrate; a plurality of first assist gates formed on said insulating film and extending toward said memory cell; a connection portion connecting end portions of said first assist gates and formed on said insulating film; a second assist gate arranged on a side of said memory cell relative to said connection portion and extending toward said memory cell; a first select transistor controlling whether to apply a voltage to an area under said first assist gate; a second select transistor controlling whether to apply a voltage to an area under said second assist gate; and an impurity region formed between said second assist gate and said second select transistor; wherein said insulating film formed under an intersection area of said connection portion and said impurity region has a thickness larger than said insulating film formed under said first assist gate and said second assist gate.