Patent ID: 7049167

Claim:
A method comprising: manufacturing a CMOS image sensor having a test pattern for testing an active area of a unit pixel, said manufacturing including: a) forming a FOX area on a predetermined location of a semiconductor substrate, thereby defining a first active area of a unit pixel part and a second active area of a test pattern part; b) forming a gate structure in the unit pixel part and a first blocking pad in the test pattern part, the first blocking pad having a pair of sub-blocking pads which are separated by a predetermined distance from each other; c) carrying out a first ion implantation process so as to form a first ion implantation region corresponding to a deep n-type impurity region of a photodiode and lightly doped drains of transistors in the unit pixel by using the first blocking pad of the test pattern part and the gate structure of the unit pixel part as masks; d) forming a second blocking pad between the pair of sub-blocking pads in the test pattern; e) carrying out a second ion implantation process by using the first and the second blocking pads of the test pattern part and the gate structure of the unit pixel part as another masks so as to form a second ion implantation region corresponding to a shallow p-type impurity region of the photodiode and source/drain regions of the transistors in the unit pixel; and f) forming a test pad having a first and a second test pads which is electrically connected to at least one contact, the test pad for measuring the sheet resistivity of the ion implantation region.