Patent ID: 7478294

Claim:
A method to detect bit line leakage, comprising the following steps: a) activating a test mode in a semiconductor memory chip using a unique code formed by a sequence of data bits applied to a command decoder within the memory chip, whereby said memory chip conditioned to receive a first test command followed by a second test command coupled from a tester to said command decoder; b) addressing a word line; c) issuing said first test command, a word line activate command, from the tester to said command decoder of the memory chip to turn on said word line; d) waiting a predetermined amount of time to allow leakage current from said word line through defects in said memory chip to charge bit lines; e) issuing said second test command from the tester to said command decoder, wherein the second test command interpreted by the command decoder during said test mode as a command to turn on bit line sense amplifiers (BLSA); f) measuring charge accumulated on bit lines during said predetermined amount of time by detecting said charge with said BLSA and comparing said charge to a predetermined value to detect leakage from said word line; g) turning off said word line, pre-charging the bit lines and turning off the bit lines; and h) repeating steps b) through g) until all word lines have been addressed.