Patent ID: 8361860

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure; forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer; forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug; exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole; implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug; depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole; forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug by a silicide reaction between the amorphous upper portion and the lower electrode layer, the amorphous upper portion of the at least one buried contact plug being an amorphous silicon area; depositing a sacrificial layer on the ower electrode layer; forming at least one lower electrode from the lower electrode layer by patterning the second interlayer insulation layer and the sacrificial layer; and performing a heat treatment on the substrate where the at least one lower electrode is formed at a temserature within a ran e of about 500° C. to about 900° C., wherein performing the heat treatment further includes, performing a thermal nitridation process on the substrate where the at least one lower electrode is formed to improve crystallization of the at least one lower electrode, the thermal nitridation process including the use of an NH 3 gas by at least one of a rapid thermal nitridation process (RTP), a spike RTP (s-RTP), and a flash RTP.