Patent ID: 8865587

Claim:
A method of fabricating a semiconductor package, said method comprising: forming on a first semiconductor device, a first patterned dielectric layer, a conductive redistribution layer in electrical contact with said first semiconductor device, and a second patterned dielectric layer; forming a first patterned conductive attach material selectively coupled to said conductive redistribution layer; placing a second semiconductor device in electrical contact with said first patterned conductive attach material; and forming a second patterned conductive attach material over said second semiconductor device, a first layer of said second patterned conductive attach material selectively coupled to said conductive redistribution layer, a second layer of said second patterned conductive attach material selectively coupled to said second semiconductor device; said first layer of said second patterned conductive attach material being substantially coplanar with said second layer of said second patterned conductive attach material so as to be together mechanically and electrically connectable to a printed circuit board.