Patent ID: 8518786

Claim:
A method for fabricating a MOS transistor comprising the steps of: (a) providing a silicon substrate; (b) forming a dielectric gate oxide layer on the semiconductor substrate; (c) forming a conductive gate layer on the gate oxide layer; (d) forming a hard mask layer on the gate layer; (e) forming a patterned photoresist layer above the gate layer, the patterned photoresist layer having a gate electrode pattern; (f) forming recesses in the hard mask and gate layer defining raised gate electrode pillars corresponding to the gate electrode pattern; (g) implanting impurities through the recesses into the substrate to form lightly doped drain regions; (h) forming an epitaxial silicon film on the substrate between the gate electrode pillars; (i) forming sidewall spacers on the gate electrode pillars; (j) forming source and drain recesses in the silicon substrate to define source and drain regions, wherein the epitaxial silicon film is removed; and (k) depositing epitaxial silicon in the source and drain regions.