Patent ID: 8665004

Claim:
A control device ( 10 ) for a power transistor ( 5 ) formed by a channel comprising a gate, a source and a drain, the control device comprising: an amplification device ( 15 ) delivering an output control signal in order to control the gate of the power transistor ( 5 ), the amplification device comprising: a first input (NEG) connected to the drain of the power transistor so as to form a first circuit portion; and a second input (POS) connected to the source of the power transistor so as to form a second circuit portion; means for producing a biasing current (I 1 , I 2 ), the biasing current being injected into one of the first and second inputs (NEG, POS) so as to cause an offset in the drain-source voltage measurement and to preserve a linear operating mode for the output control signal before the power transistor opens; equal number N of semiconductor junctions in the first and second circuit portions; a protection device (D 4 ) on the first circuit portion; and a protection device (D 3 ) on the second circuit portion.