Patent ID: 7203085

Claim:
A semiconductor device that is incorporated into a portion of a semiconductor integrated circuit in which a plurality of first power source lines to which a first voltage is applied and a plurality of second power source lines to which a second voltage is applied are arranged in a lattice, comprising: an internal circuit that is disposed in a layer below the first and the second power source lines and operates with the first and the second voltages supplied; first internal power source lines arranged parallel to each other in a layer between a layer in which the first power source lines are arranged and a layer in which the internal circuit is disposed in order to supply the first voltage to the internal circuit; second internal power source lines arranged parallel to the first internal power source lines in a same layer as the first internal power source lines in order to supply the second voltage to the internal circuit; first and second lines arranged parallel to the first and the second internal power source lines in a layer between the layer in which the first and the second internal power source lines are arranged and the layer in which the first and the second power source lines are arranged; a plurality of third lines that are connected to the first line and extend in a direction perpendicular to the first line above an area in which the first and the second internal power source lines are present; and a plurality of fourth lines that are connected to the second line and extend in a direction perpendicular to the second line above the area in which the first and the second internal power source lines are present, wherein the first line, the third lines and the first internal power source lines are electrically connected, and the second line, the fourth lines and the second internal power source lines are electrically connected.