Patent ID: 8886512

Claim:
A non-transitory computer-readable recording medium storing a program which, when executed by a computer, causes the computer to perform a verification process, comprising: verifying one or more logical hardware models which operate by collaborating with embedded software, as a hardware simulator; and triggering the embedded software to operate, without synchronization and for each of a plurality of instructions, as a CPU model configured to be one of the one or more logical hardware models which imitates a CPU which executes the embedded software to be verified by the hardware simulator wherein a collaborative simulation of the embedded software and the one or more logical hardware models is conducted, wherein the CPU model includes a memory model, and conducts a data access by calling one of a plurality of IO functions, which corresponds to a function key, in accordance with an address, and wherein the memory model includes a function associative array for the IO functions each of which is called by being associated with predetermined bits in the address as the function key, and a pointer associative array which indicates a value of a pair of an area pointer of a memory area and an array pointer of the function associative array, the value of the pair being associated with bits other than the predetermined bits in the address as an address key; and in the case in which the area pointer and the array pointer are determined by the value of the pair given by the pointer associative array in accordance with the address, and the function key of the function associative array exists, when the value of the function associative array indicates the null pointer, the data access is conducted by calling the IO function in accordance with a greatest address among smaller addresses than the address, at each of which smaller addresses the value of the function associative array does not indicate null.