Patent ID: 8034701

Claim:
A method of forming a gate electrode comprising: forming a trench in a substrate; conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate; forming a planarized tungsten layer in the recess to form an upper surface that forms an interface including a top surface of the polysilicon conformal layer and a top surface of the planarized tungsten layer; forming a capping layer in direct contact with the top surfaces of the polysilicon conformal layer and the planarized tungsten layer; and forming a thermal oxidation layer on the vertical outer sidewall of the protrusion in contact with the capping layer.