Patent ID: 7005332

Claim:
A thin-film transistor (TFT) fabrication method, which comprises the steps of: forming a gate on a substrate; forming a gate insulation layer, a semiconductor layer and a metal layer on the substrate in sequence, which cover the gate; patterning the metal layer and the semiconductor layer to form a patterned metal layer and a patterned semiconductor layer covering the gate; forming a patterned first passivation layer on the substrate and exposing the patterned metal layer; forming a pixel electrode layer on the substrate to cover the patterned first passivation layer and the patterned metal layer; forming a patterned photoresist layer on the substrate and exposing the pixel electrode layer above the gate; etching the pixel electrode layer and the patterned metal layer above the gate to form a patterned pixel electrode layer, a source and a drain to form a channel region on the patterned semiconductor layer; forming a second passivation layer on the substrate; and removing the patterned photoresist layer to lift off the second passivation layer, thereby exposing the patterned pixel electrode layer.