Patent ID: 7283801

Claim:
A circuit arrangement for implementing a PLL in a time-division cellular network terminal in which power supply to at least some of the circuit elements of the terminal is arranged to be switched off for the duration of time slots not used in data transfer, comprising: means for receiving an external signal and processing it into a reference signal, means for indicating a signal representing a phase difference between said processed reference signal and a comparable signal generated in the circuit arrangement, means for producing, using said indicated signal, a voltage change proportional to the phase difference, a voltage controlled oscillator (VCO), for producing, on the basis of said voltage change proportional to the phase difference, an output signal having a varying frequency, and means for switching off power supply of the VCO in the PLL for the duration of time slots not used in data transfer, in which circuit arrangement a power supply voltage is arranged to be connected to the means for producing a voltage change proportional to the phase difference also during time slots not used in data transfer in order to reduce the restart time and switching noise in the PLL, wherein the means for producing an output signal having a varying frequency comprise a VCO which is arranged to be controlled using a control voltage obtained from an output of a low-pass filter, and wherein the initial value of the VCO control voltage obtained from an output of a low-pass filter is arranged to be set, at the end of each time slot used in data transfer, to a voltage value which is 100 to 200 mV above the VCO control voltage to be used in the next time slot used in data transfer.