Patent ID: 8618975

Claim:
An n-bit analog-to-digital converter (ADC) circuit for converting an analog input signal to a digital output signal by processing more than one bit per cycle in a number of successive approximation cycles, the n-bit ADC circuit comprising: a digital-to-analog (DAC) circuit including a corresponding number of capacitive elements, each of the capacitive elements configured to be pre-charged to the analog input signal to obtain an error signal, the corresponding number of capacitive elements grouped into a number of capacitive sub-DAC circuits; a plurality of comparators, each of the plurality of comparators coupled to one of the capacitive sub-DAC circuits; a plurality of first switches configured to isolate the capacitive sub-DAC circuits during one or more first cycles of the successive approximation cycles and to merge the capacitive sub-DAC circuits during one or more last cycles of the successive approximation cycles; and a successive approximation register (SAR) circuit configured to receive an output signal from the plurality of comparators and to generate at least one of the digital output signal and a number of DAC digital signals, wherein n represents a positive integer greater than one.