Patent ID: 8227893

Claim:
A semiconductor device wherein a capacitor element in which an upper electrode, a capacitor insulation film, and a lower electrode are layered in order from the top is mounted on wiring, the semiconductor device, characterized in that the lower electrode is embedded in a groove of a bilayer-structured insulation film composed of a wiring cap film and a hard mask used for processing the wiring cap film opened to a lower-layer wiring, wherein the bilayer-structured insulation film is formed on the underlying lower-layer wiring; and the lower electrode and the lower-layer wiring are in direct contact, and the upper electrode is in contact with an overlying upper-layer wiring by way of a contact plug, and comprising a multilayer wiring composed of three or more layers, the semiconductor device characterized in having a capacitor element layer on which the capacitor element is mounted between any two of the wiring layers, wherein at least two or more capacitor elements are layered; and the capacitor elements of each layer are connected in parallel by way of a wiring layer.