Patent ID: 7505328

Claim:
A method of programming an array of flash memory cells comprising: accessing an array of erased flash memory cells, wherein an erased cell comprises a first threshold voltage, wherein said first threshold voltage precludes a current from flowing through said cell; selecting a first column of said cells, wherein said first column of cells is accessed by a first bit line and a second bit line; programming said first column of cells, wherein said programming comprises: lowering a threshold voltage of a first cell in said first column of cells, wherein said lowering of said threshold voltage of said first cell permits said current to flow through said first cell; selecting said first plurality of cells in said first column, wherein said first plurality of cells are accessed by a first plurality of word lines; selecting a second plurality of cells in said first column, wherein said second plurality of cells are accessed by a second plurality of word lines; applying a first voltage to said first plurality of word lines; allowing said second plurality of word lines to float; and applying a second voltage to said first and second bit lines, wherein said second voltage is higher than said first voltage, wherein said first and second voltages are applied concurrently, and wherein said applying said first and second voltages changes the state of said first plurality of cells by lowering the threshold voltages of said first plurality of cells; subsequent to said programming said first column of cells, selecting a second column of cells, wherein said second column is adjacent to said first column; programming a second cell from said second column; and repeating said selecting and said programming until said array is programmed.