Patent ID: 7360023

Claim:
Apparatus for a Y-way set-associative cache memory (e.g., 32 ) having Y>1 blocks and X>1 sets, wherein each block y, 0≦y≦(Y−1), of each set x, 0≦x≦(X−1), is adapted to store an address tag (e.g., Tag xy ), a state (e.g., State xy ), and Z words (e.g., W xyz ), 0≦z≦(Z−1), the apparatus comprising: first circuitry (e.g., 130 and 150 ) adapted to (1) receive a fetch address, (2) determine a set associated with the fetch address, (3) read Y address tags and Y states corresponding to the associated set, (4) determine which of the Y address tags are valid based on the Y states, (5) compare the fetch address to one or more valid address tags, and (6) generate, if one of the valid address tags matches the fetch address, a first control signal (e.g., 110 ) indicating that the block associated with the matching valid address tag is a matching block; second circuitry (e.g., 132 , 138 a - d , and 134 a - d ) adapted to (1) receive the fetch address, (2) receive the first control signal generated by the first circuitry, (3) generate a second control signal (e.g., 126 e ) based on the first control signal and indicating the matching block, (4) generate block-enable control signals (e.g., 126 a - d ) for the cache memory, (5) apply the block-enable control signals to the cache memory, such that the matching block in the cache memory is enabled and the (Y−1) other blocks in the cache memory are at least partly disabled, and (6) apply the fetch address to the cache memory to read one or more associated words from the enabled matching block; and third circuitry (e.g., 112 ) connected to an output of each block of the cache memory and adapted to (1) receive the second control signal generated by the second circuitry, (2) receive the one or more associated words from the enabled matching block, and (3) select the one or more associated words for output from the cache memory based on the second control signal, wherein: the first circuitry comprises a first latch (e.g. 130 ) adapted to latch the fetch address; the second circuitry comprises: a second latch (e.g. 132 ) adapted to latch the first control signal and output the second control signal; and a plurality of other latches (e.g., 134 a - d ) adapted to latch the block-enable control signals; and the third circuitry comprises a multiplexer (e.g. 112 ) adapted to receive the outputs from the blocks and select the one or more associated words from the enabled matching block based on the second control signal from the second latch.