Patent ID: 7581033

Claim:
A host computer system comprising: a first processor; a first memory; a data storage device, the data storage device having an operating system stored thereon, the operating system executable by the first processor, the operating system creating an environment in which an application runs, the application communicating with a destination; a send work queue, stored in the first memory, the send work queue comprising at least one send work queue entry, each send work queue entry comprising at least one of a descriptor and a control-path command; a receive work queue, stored in the first memory, the receive work queue comprising at least one receive work queue entry, each receive work queue entry comprising at least one of a descriptor and a control-path command; a Network Interface Card (NIC), the NIC comprising a port through which the application communicates with the destination, the NIC further comprising a second memory and a second processor; a token table, stored in the first memory and associated with said NIC, the token table communicating descriptors and control-path commands from the send work queue and receive work queue to the NIC; a Notification Request Area (NRA), stored in the second memory, the NRA allowing the NIC to notify the operating system that a descriptor has completed; a Master Completion Queue (MCQ), the MCQ being stored in the first memory and being associated with at least one of the send work queue and the receive work queue, the MCQ comprising the completion status of descriptors posted to the associated work queue; a Memory Deregistration List (MDL), the MDL being stored in the second memory, the MDL containing memory handles to be deregistered; an MDL Insert Kernel Agent counter running in the operating system, which indicates where in the MDL a next deregistered memory handle should be inserted; a Memory Region Table (MRT), the MRT being stored in the first memory and maintained by the MDL Insert Kernel Agent, containing all registration information for all memory regions registered on the NIC; and a shadow MRT, the shadow MRT being stored in the second memory, which is a copy of the MRT entries for said NIC.