Patent ID: 8185790

Claim:
Circuitry comprising: A. plural data output paths, each path including a tri-state data output buffer having a data input, a data output, and a control input; B. a first control signal input path including a first input buffer having a signal input and a signal output; and C. a scan path between a test data input lead and a test data output lead, including: i. data scan cells, each data scan cell having a functional data input, a functional data output connected to the data input of one data output buffer, a test data input, and a test data output, the data scan cells being connected in a series with the test data input of the initial data scan cell in the series being connected to the test data input lead, and the test data output of each data scan cell being connected to the test data input of the next, successive data scan cell; ii. a control scan cell having a functional data input connected to the signal output of the first input buffer, a functional data output connected to the control inputs of the tri-state data output buffers, a test data input, and a test data output connected to the test data output lead; iii. at least one resynchronization memory having a test data input connected with the test data input lead and a test data output; and iv. multiplexer circuitry having one input connected to the test data output of the last data scan cell in the series, another input connected to the test data output of the resynchronization memory, and an output connected to the test data input of the control scan cell.