Patent ID: 8207033

Claim:
A method of fabricating a semiconductor integrated circuit device, comprising: providing a substrate with gate patterns formed on first and second regions, wherein spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region; forming source/drain trenches in the substrate on opposite sides of the gate patterns on the first and second regions; forming a first silicon-germanium (SiGe) epitaxial layer that partially fills the source/drain trenches using a first silicon source gas, wherein forming the first SiGe epitaxial layer comprises growing the first SiGe epitaxial layer on exposed portions of the substrate on the first region at a greater than the first SiGe epitaxial layer is grown on exposed portions of the substrate on the second region so that the first SiGe epitaxial layer in the source/drain trenches on the first region is thicker than the first SiGe epitaxial layer in the source/drain trenches on the second region; and forming a second SiGe epitaxial layer directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.