Patent ID: 8324053

Claim:
A method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area comprising: growing and patterning a field oxide layer in said termination area and also in said active cell area on a top surface of said semiconductor substrate using a first mask; forming a gate oxide layer on said top surface of said semiconductor substrate; depositing and patterning with a second mask a polysilicon layer on said gate oxide at a gap distance away from said field oxide layer, wherein said polysilicon layer acts as planar gates in the active area; performing a blank body dopant implant to form body dopant regions in said semiconductor substrate substantially aligned with said gap area followed by diffusing said body dopant regions into body regions in said semiconductor substrate; forming body contact regions encompassed in and having a higher dopant concentration than said body regions, wherein said field oxide layer patterned in the termination area and the active cell area reduces P-body charges in the semiconductor power device in forming the body and body contact regions; applying a source mask as the third mask to implant source regions having a conductivity opposite to said body regions with said source regions encompassed in said body regions and located above said high concentration body contact regions; depositing an insulation layer on top of said semiconductor power device and applying a contact mask as the fourth mask to open contact openings and remove said field oxide, and etching into the semiconductor substrate to form contact trenches, wherein said contact trenches further reduce the amount of P-body charges in the device; and depositing a metal layer filling in said contact trenches to contact said body regions and said source regions, and patterning said metal layer with a fifth mask.