Patent ID: 7171633

Claim:
A method of computer aided design comprising: providing a description of a first logic function using a high-level design language; synthesizing gates to obtain a first alternative netlist for the first logic function; performing a technology mapping of the first alternative netlist to obtain a first mapping netlist; synthesizing gates to obtain a second alternative netlist for the first logic function, wherein the second alternative netlist has a different gate configuration from the first alternative netlist; performing the technology mapping of the second alternative netlist to obtain a second mapping netlist; selecting one of corresponding first alternative netlist or second alternative netlist based on a comparison of the first mapping netlist with the second mapping netlist based on design criteria, wherein the selected one of the corresponding first alternative netlist or second alternative netlist is a selected netlist; optimizing the selected netlist based on the corresponding mapping netlist; and performing the technology mapping on the selected netlist after optimizing.