Patent ID: 8281060

Claim:
A system comprising: a first processor to send a message from a first process executing on the first processor to a second process executing on a second processor, wherein the first process is to send the message while the second process is in a wait state; the second processor to receive the message from the first process while the second process is in the wait state, wherein the first process is to send a wake up message to the second process based on a state of a synchronization block for the second process if the second process is in the wait state when the message is sent; and a dynamic random access memory (DRAM) coupled to the first and second processors and including instructions to create a shared memory segment having a location distributed using an out-of-band communication, the shared memory segment to store a synchronization block for the first process and store the synchronization block for the second process, wherein each synchronization block includes a wait flag to indicate that the associated process is in the wait state and a wake up counter to indicate a number of messages sent by the associated process to another process that have not been received.