Patent ID: 7548127

Claim:
A ring oscillator for generating an output signal, comprising: a plurality of serially connected main elements for selectively delaying a signal input thereto, each of the plurality of main elements having: two circuit paths, a first path including at least one time-delay element for delaying the signal input thereto to produce a delayed signal input; a second circuit path bypassing the first circuit path; a multiplexor (MUX) having a first input coupled to the first circuit path including the at least one time-delay element and a second input coupled to the second circuit path, the MUX selecting the first or second inputs and outputting an output signal; and a selector circuit for selecting the first or second input of the multiplexor, said selector circuit latching and outputting a received data signal upon receiving a clock signal, and wherein the clock signal is generated by a logic circuit receiving said signal input and said delayed signal input, whereby the clock signal is only generated to latch said received data signal when both said signal input and said delayed signal input will not cause said multiplexor to select one of said first and second inputs when a pulse is present on one of said first and second inputs.