Patent ID: 8878898

Claim:
A smart 3D HDMI video splitter that takes a video signal from a 3D video input unit, sends the video signal to a field-programmable gate array (FPGA) for conversion, uses a micro-controller to detect a type and decide an output video format, and transmits original 3D video or processed 3D video to a 3D or 2D television, display, or AVR amplifier; with the FPGA including a video input unit, a video format processing unit, a controlling unit, and a multiplexer unit; wherein the video input unit synchronizes and renormalizes the 3D video according to a command from the controlling unit; the video format processing unit uses a conversion formula to convert the 3D video format into the 3D checkboard format, frame-sequential format, line interlaced format, left-/right-eye single output format, or left-eye/right-eye dual output format, using second-generation double-speed dynamic random access memory (DDRII) as a storage medium, outputs the video to the multiplexer unit, and converts the video into the format determined by the controlling unit; the controlling unit sends command which divides the video signal into odd-numbered-pixel image and even-numbered-pixel image and outputs a video format command to the video format processing unit when the output image is in the checkboard, frame-sequential or line interlaced format; the controlling unit sends command which divides the video signal into first-half-column-pixel image and last-half-column-pixel image and outputs a video format command to the video format processing unit when the output video is in the left-/right-eye single output format or left-eye/right-eye dual output format; and the final output video is output by the multiplexer unit is either the original 3D video format or the processed video format according to whether the micro-controller detects the connected device as a 3D or 2D television, display, or AVR amplifier.