Patent ID: 8312408

Claim:
A method of designing a semiconductor integrated circuit, the method comprising: dividing a layout region of the semiconductor integrated circuit in which a wiring pattern and a special pattern are placed into a plurality of division regions, wherein a minimum pitch specified for said wiring pattern by a design rule comprises a first wiring pitch, and a minimum pitch specified for said special pattern by said design rule comprises a second wiring pitch that is larger than said first wiring pitch; extracting, as executed by a processing unit on a computer, with respect to each of said plurality of division regions, said special pattern included in a region that surrounds each said division region and has a predetermined width, wherein said extracted special pattern comprises a peripheral pattern; determining, with respect to each said division region, a dummy pattern placement region included in each said division region, wherein said dummy pattern placement region is apart from at least one of boundaries between each said division region and adjacent division regions; adding a dummy pattern in said dummy pattern placement region of each said division region, and avoiding a design rule error with said peripheral pattern existing around each said division region; and coupling said plurality of division regions to which said dummy pattern is added with each other.