Patent ID: 8755468

Claim:
A pulse-sync demodulator that receives a pulse signal of a first frequency, comprising: a clock signal generation section that generates a clock signal of a second frequency which is one-half of the first frequency; a plurality of AD conversion sections that sample the pulse signal at different sampling timings of the clock signal; a phase determination section that generates a phase control signal in accordance with magnitudes of a plurality of sampled values output from the plurality of AD conversion sections; a variable delay section that changes an amount of delay in the clock signal generated by the clock signal generation section in accordance with the phase control signal; a plurality of sampling timing adjustment sections that are provided in correspondence with the plurality of AD conversion sections, respectively, and that can individually adjust the amount of delay in the clock signal output from the variable delay section; and a level determination section that detects levels of the plurality of sampled values output from the plurality of AD conversion sections and that increases or decreases the amount of delay in the variable delay section by a predetermined amount when the levels of the plurality of sampled values become lower than a preset value, wherein a difference (Δτ) among amounts of delays in the plurality of sampling timing adjustment sections is set to values which are equal to or smaller than a half width of the amplitude of the pulse signal in a synchronization process; the amount of delay in the variable delay section is increased or decreased for a period of time corresponding to one-half of a pulse width of the pulse signal when a plurality of sampled values output from the plurality of AD conversion sections come to values which are smaller than one-half of the amplitude of the pulse signal; the plurality of AD conversion sections comprise a first AD conversion section and a second AD conversion section; the first AD conversion section samples the pulse signal of the first frequency by means of a leading edge of the clock signal of the second frequency; and the second AD conversion section samples the pulse signal of the first frequency by means of a trailing edge of the clock signal of the second frequency shifted by the difference(Δτ) between an amount of delay in a first sampling timing adjustment section and an amount of delay in a second sampling timing adjustment section; wherein the first sampling timing adjustment section adjusts the sampling timing of the clock signal input to the first AD conversion section and the second sampling timing adjustment section adjusts the sampling timing of the clock signal input to the second AD conversion section.