Patent ID: 8133780

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising steps of: providing a semiconductor substrate having a main surface, a first MISFET formed on a first MISFET forming area of the main surface, and a second MISFET formed on a second MISFET forming area of the main surface, the first MISFET having a gate electrode formed over the semiconductor substrate, a side wall spacer formed on a side surface of the gate electrode, and a source region and a drain region formed in the semiconductor substrate, the second MISFET having a gate electrode formed over the semiconductor substrate, a side wall spacer formed on a side surface of the gate electrode, and a source region and a drain region formed in the semiconductor substrate; forming a first insulating film over the first MISFET and the second MISFET so as to cover the first MISFET and the second MISFET; removing a first portion of the first insulating film such that the first MISFET is exposed and a second portion of the first insulating film such that a portion of the drain region of the second MISFET is exposed; forming a refractory metal film over the first portion, the second portion and the first insulating film such that the first insulating film covers the gate electrode of the second MISFET and exposes the second portion; and forming first silicide layers on the source region, the drain region and the gate electrode of the first MISFET and second silicide layers on the portion of the drain region of the second MISFET.