Patent ID: 7902037

Claim:
A method for fabricating an isolation structure in a memory device, the method comprising: forming a first trench in a cell region of a silicon substrate and a second trench in a peripheral region of the silicon substrate; oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS)layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride layer and the silicon oxide layer on the second trench to expose a portion of the underlying TEOS layer; coating a polysilazane-based spin-on-dielectric (SOD) to form a single insulation layer filling the first and second trenches; and curing the SOD by annealing to a temperature of 850° C., wherein the TEOS layer provides a tensile stress to compensate a compressive stress induced by a contraction of the SOD during the curing and prevent a silicon slip in the silicon substrate resulted from the compressive stress.