Patent ID: 7666790

Claim:
A method for fabricating a semiconductor structure comprising: forming a silicon-containing gate on a surface of a gate dielectric which is positioned on a semiconductor substrate and forming a source/drain region into the semiconductor substrate while using the silicon-containing gate as a mask; masking the source/drain region, without a silicide layer located thereupon, and to avoid spiking of the silicide layer into the source/drain region when partially siliciding the silicon containing gate, with a mask that exposes the silicon-containing gate; forming a metal silicide forming metal layer contacting the silicon-containing gate; annealing the metal silicide forming metal layer in contact with the silicon-containing gate to form a partially silicided gate, wherein the annealing has a timescale of about 1 to about 200 milliseconds; unmasking the source/drain region after forming the partially silicided gate; and forming a second silicide layer upon the partially silicided gate to provide a fully silicided gate and forming a second silicide layer upon the source/drain region, the partially silicided gate comprising a first metal silicide forming metal and the second silicide layer comprising a second metal silicide forming metal different than the first metal silicide forming metal.