Patent ID: 7768308

Claim:
A level shift circuit comprising: two N-type signal-receiving low-voltage transistors, which receive at their respective gates complementary first and second input signals powered by a low-voltage supply, and each of which has first and second terminals, the first terminals of the N-type signal-receiving low-voltage transistors being grounded, the second terminals of the N-type signal-receiving low-voltage transistors being connected to first and second nodes, respectively; two N-type high-voltage transistors, each of which includes first and second terminals, which receive at their respective gates the complementary first and second input signals powered by the low-voltage supply, and which turn on in a complementary manner according to the first and second input signals, the first terminals of the N-type high-voltage transistors being connected to third and fourth nodes, respectively, the second terminals of the N-type high-voltage transistors being connected to fifth and sixth nodes, respectively; a power supply circuit, which includes a first terminal connected to a high-voltage supply, a second terminal connected to the fifth node, and a third terminal connected to the sixth node, and supplies a voltage of the high-voltage supply to one of the fifth and sixth nodes, while blocking the supply of the voltage of the high-voltage supply to the other of the fifth and sixth nodes; and a protection circuit, which includes first, second, third, and fourth terminals connected to the first, second, third, and fourth nodes, respectively, and restricts voltages at the first and second nodes to not more than the voltage of the low-voltage supply, wherein the protection circuit includes two N-type protection transistors each including first and second terminals, the first terminals of the N-type protection transistors being connected to the first and second nodes, respectively, the second terminals of the N-type protection transistors being connected to the third and fourth nodes, respectively, and wherein the complementary first and second input signals are respectively input via delay circuits to the gates of the two N-type protection transistors in the protection circuit.