Patent ID: 6972981

Claim:
A semiconductor memory module comprising: a plurality of memory chips; a module-internal clock, address, command and data signal bus; at least one buffer chip that drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via the module-internal clock, address, command and data signal bus; and an interface to an external memory main bus formed by the buffer chip; wherein the memory chips are arranged in at least one row starting from the buffer chip, and are connected to the latter by means of the module-internal bus; wherein the memory chips respectively have separate writing and reading clock signal inputs for receiving the clock signals; wherein the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip; and wherein the memory chips are clocked, when writing data, by the clock signals, which originate from the buffer chip and are received at the writing clock signal inputs of said memory chips and are clocked, when reading data, by the clock signals, which travel back to the buffer chip and are received at the reading clock signal inputs of the memory chips.