Patent ID: 8830715

Claim:
A semiconductor memory device, comprising: a memory array block including: a first set of memory cells electrically connected to a first bit line extending in a first direction; a second set of memory cells electrically connected to a second bit line extending in the first direction and adjacent to the first bit line; a first word line electrically connected to a first memory cell of the first set of memory cells and extending in a second direction perpendicular to both the first direction and a vertical direction; and a second word line electrically connected to a first memory cell of the second set of memory cells and extending in the second direction, wherein each memory cell of the first set of memory cells includes a respective first cell transistor having an upper active node, a lower active node and a gate node disposed between the upper active node and the lower active node, wherein the gate node includes top surface and bottom surface, and wherein the first word line is disposed vertically above the top surface of the gate node of each of the first cell transistors and the second word line is disposed vertically below the bottom surface of the gate node of each of the first cell transistors, a bit-line sense amplifier configured to amplify a voltage difference between the first bit line and second bit line.