Patent ID: 7232723

Claim:
A method of fabricating a semiconductor device made up of memory cells each having a control gate formed above a floating gate, said method comprising steps of: forming a resist pattern having a plurality of openings on an electrically conductive film, serving as the floating gates, formed across a substrate; baking the resist pattern to thereby cause deformation due to thermal flow to occur thereto and causing the openings to undergo contraction; etching a portion of the electrically conductive film, in the respective openings after the contraction, and forming end faces of the respective floating gates, along the direction of a gate width thereof; forming the control gate, extended in the direction of the gate width of the respective floating gates, above a portion of the electrically conductive film, defining the end faces of the respective floating gates, with an insulating film interposed therebetween; and selectively etching the electrically conductive film using the control gates as masks to thereby form the floating gate under the respective control gates; wherein each respective opening of the resist pattern is slit-like with a longitudinal direction thereof crossing a respective control gate at right angles, and wherein the openings are deployed along the direction perpendicular to the direction along which the respective control gates extend in the respective memory cells.