Patent ID: 8614511

Claim:
A three dimensional semiconductor device comprising: a substrate comprising a cell array region and a contact region; an interconnection structure comprising a plurality of stacked horizontal electrodes overlying the substrate; and bit lines disposed on the cell array region, wherein widths of the horizontal electrodes decrease as the horizontal electrodes are further away from the substrate, so that the interconnection structure has a stepwise shape in the contact region, a sidewall of one of the horizontal electrodes meets the below equation L n ⁡ ( y m ) - L n ⁡ ( y 0 ) < L n ⁡ ( y 0 ) - L n + 1 ⁡ ( y 0 ) s , within a range of y m meeting the condition of |y m −y 0 |<y 1 , where y 0 is a y coordinate of a reference point, y m is a y coordinate of a measured point, L n (y m ) is a distance between a sidewall of a n-th conductive pattern in which the y coordinate is y m , and a sidewall of the bit line most adjacent to the sidewall of the n-th conductive pattern, s is a value between about 2 to 20, and y 1 is a length shorter than a length of bit line.