Patent ID: 6960935

Claim:
A method for clearing the memory of a Field Programmable Gate Array (“FPGA”) Integrated Chip (“IC”), comprised of a plurality of cores, said method comprising: clearing memory of said plurality of cores; sequentially verifying completion of said clearing memory act for each core of said plurality of cores; providing a programming ready signal to all cores of said plurality of cores when a last core of said plurality of cores has completed said clearing memory act; providing an enable memory clear query signal to a first core of said plurality of cores; clearing memory of said plurality of cores; determining whether said first core has completed its said clearing memory act; providing a first core memory cleared signal, if said first core has completed its said clearing memory act; providing a first core memory cleared out signal; repeating in a sequential manner the acts of determining whether a next core of said plurality of cores has completed its said clearing memory act, providing a said next core memory cleared signal, if said next core has completed its clearing memory act, and providing a said next core memory cleared out signal, until said last core has completed its clearing memory act; providing a said last core's memory cleared signal; and providing a said programming read signal to said all cores.