Patent ID: 8766431

Claim:
A power MOSFET package, comprising: a semiconductor substrate having a first surface and an opposite second surface, wherein the semiconductor substrate has a first conductivity type and forms a drain region; a doped region extending downward from the first surface, the doped region having a second conductivity type; a source region located in the doped region, the source region having the first conductivity type; a gate formed overlying the first surface or buried under the first surface, wherein a gate dielectric layer is located between the gate and the semiconductor substrate; a first conducting structure located overlying the semiconductor substrate and having a first terminal, the first conducting structure electrically connected to the drain region; a second conducting structure located overlying the semiconductor substrate and having a second terminal, the second conducting structure electrically connected to the source region; a third conducting structure located overlying the semiconductor substrate and having a third terminal, the third conducting structure electrically connected to the gate, wherein the first terminal, the second terminal, and the third terminal are substantially coplanar; and a protection layer located between the semiconductor substrate and the first terminal, the second terminal, and the third terminal.