Patent ID: 7895491

Claim:
An integrated circuit with low-power built-in self-test logic, the integrated circuit comprising: combinational logic; and a loading circuit operable to load a shift test pattern of data into the loading circuit without applying said data to the combinational logic of the integrated circuit, wherein the shift test pattern of data is configured to test the combinational logic for logical faults, the loading circuit comprising: a shift register comprising a plurality of flip-flops, each flip-flop comprising a data input, a scan-in input, a scan enable input and a sequential output, wherein the loading circuit is operable to receive the shift test pattern of data bit-by-bit at the scan-in input of a first flip-flop of the plurality of flip-flops and to receive a series of shift pattern signals at the scan enable input of each flip-flop of the plurality of flip-flops; and a plurality of switching elements, each receiving a sequential output of one of the plurality of flip-flops, each switching element selectably coupling the received sequential output to one of the combinational logic and a scan-in input of a next of the plurality of flip-flops.