Patent ID: 7668238

Claim:
A method of performing decision feedback equalization (DFE) of a currently received data bit, comprising: slicing an input data stream into first and second data streams using first and second shift registers; shifting the first data stream through first and second sets of latches of the first shift register, wherein the first set of latches of the first shift register is activated during a time period and the second set of latches of the first shift register is reset during the time period; shifting the second data stream through first and second sets of latches of the second shift register, wherein the first set of latches of the second shift register is reset during the time period and the second set of latches of the second shift register is activated during the time period; directly connecting, with no intervening logic, all outputs of each of the first and second sets of latches of the first and second shift registers to a summer; and simultaneously summing, with the summer, all outputs of each of the first and second sets of latches of the first and second shift registers with the currently received data bit during the time period, wherein the activated latches provide a number of consecutively received data bits prior to the currently received data bit for summation during the time period.