Patent ID: 6970382

Claim:
In a digital memory system including a memory cell arranged to store charge corresponding to a first logical value when the quantity of stored charge lies within a first range of values and corresponding to a second logical value when the quantity of stored charges lies within a second range of values, the cell being arranged to store a predetermined one of the first and second logical values in response to a range of operating voltages received by the cell, a system for controlling the logical value and the integrity of the data represented by the charge, comprising: a bit line coupled to the cell; a voltage generator arranged to generate a plurality of cell operating voltages varying in response to a voltage control signal; and a controller, wherein the controller generates the control signal, wherein the controller stores a predetermined one of the logical values in the cell by generating a series of the operating voltages, wherein the controller transmits the series of operating voltages, wherein the controller determines whether the predetermined one of the logical values has been stored in the cell in response to a voltage on the bit line, wherein the controller comprises a charge integrity estimating module, and wherein the controller determines whether the predetermined one of the logical values has been stored in the cell by initiating the operation of the charge integrity estimating module.