Patent ID: 7423288

Claim:
An arrangement of test structures provided on at least a partially completed wafer, the arrangement comprising: a plurality of test structures positioned on at least one die, and wherein individual test structures in the plurality of test structures are identifiable in formation or location as being part of any one or more of a plurality of classes, wherein each of the plurality of test structures is capable of being activated to cause an electrical activity that is detectable; wherein each test structure is configured so that (i) the electrical activity that is caused by activation of that test structure identifies a value that indicates an attribute or result of one or more steps that comprise the design or fabrication, and (ii) the electrical activity that is caused by activation of that test structure is not indicative of another step in the design or fabrication; wherein the wafer includes a class of the test structures for each step in the set of designated steps; wherein the identified value from each class of test structures can be used, either individually or in combination with the value of another class of test structures, to determine information about the design or fabrication of the wafer.