Patent ID: 7155637

Claim:
A method for testing a plurality of embedded memory sites resident on a computer chip, wherein each of the embedded memory sites is associated with a computer processor of a plurality of computer processors also resident on the computer chip, the method comprising: receiving a test program at a data flow controller resident on the computer chip; broadcasting the test program to each of the plurality of embedded memory sites on the computer chip; executing the test program at each of computer processors, wherein the test program determines a pass, fail, or repair status of a memory site, and generates a repair solution for each of the memory sites whose status is repair; providing a memory status indicator corresponding to each of the memory sites wherein the memory status indicator indicates a pass, fail, or repair status of the memory sites; for each of the memory sites indicating a repair status, retrieving a first block of memory corresponding to the repair solution for the memory sites; and providing each of the retrieved first blocks of memory corresponding to each of the repair solutions to a testing device.