Patent ID: 7053680

Claim:
A buffer circuit for receiving an input signal and for providing an output signal, the buffer comprising: a first pulse generator coupled to receive the input signal and configured to generate a first pulse responsive to a first transition edge of the input signal; a first pulse loop generator coupled to receive the first pulse from the first pulse generator and configured to generate a first pulse loop signal to deactivate the first pulse generator responsive to the first pulse; a second pulse generator coupled to receive the input signal and configured to generate a second pulse responsive to a second transition edge of the input signal; a second pulse loop generator coupled to receive the second pulse from the second pulse generator and configured to generate a second pulse loop signal to deactivate the second pulse generator responsive to the second pulse; an output stage coupled to receive the first and second pulses and configured to produce an output of first logic value for the duration of the first pulse, and of second logic value for the duration of the second pulse as the output signal from the buffer circuit; a first loop keeper circuit coupled to intercept the first pulse loop signal between the first pulse loop generator and the first pulse generator and configured to deactivate the first pulse generator responsive to receiving the first pulse loop signal, thereby blocking subsequent first pulse loop signals from reaching the first pulse generator; a reset generator coupled to receive the input signal and to output a first reset signal responsive to a falling edge of the input signal; and a first pulse reset coupled to receive the first reset signal from the reset generator and responsive to the first reset signal configured to deactivate the first loop keeper circuit and to reset the first pulse generator to respond to a subsequent rising edge in the input signal.