Patent ID: 8493775

Claim:
A semiconductor device comprising: a memory cell array including memory cells arranged in a matrix; a plurality of word lines respectively provided for rows of the matrix; and bit line pairs respectively provided for columns of the matrix, each of the memory cells including a first inverter having a first p-channel transistor and a first n-channel transistor; a second inverter having a second p-channel transistor and a second n-channel transistor, an input of the first inverter being coupled to an output of the second inverter, and an input of the second inverter being coupled to an output of the first inverter; a third n-channel transistor providing an electrical path between an output of the first inverter and one bit line of a bit line pair for a column in which each of the memory cells is arranged; and a fourth n-channel transistor providing an electrical path between an output of the second inverter and another bit line of the bit line pair for the column in which each of the memory cells is arranged with gate electrodes of the third and fourth n-channel transistors coupled to a word line for a row in which each of the memory cells is arranged; a plurality of word driver units coupled to the word lines, respectively, each activating a corresponding coupled word line; a word-line-timing generator configured to generate a word-line timing signal for determining a word-line activation time of the word lines; a comparator operable to make a comparison between the word-line timing signal and a reference signal to detect whether the word-line activation time is shorter or not than a pulse width of the reference signal; and a back-gate voltage control circuit which controls to change respective voltages of back-gates of the first to fourth N-channel transistors based on a detecting result of the comparator.