Patent ID: 8190854

Claim:
A processor comprising: a control register including a combined condition code register having multiple bits, wherein each bit in the combined condition code register is configured to be set to one of a first value corresponding to a true compare result and a second value corresponding to a false compare result, wherein each bit in the combined condition code register is set in response to execution of one of a particular scalar compare instruction and a particular vector compare instruction; a plurality of instruction execution units responsive to a sequencer and configured to execute scalar instructions and vector instructions, wherein the scalar instructions include the particular scalar compare instruction and a particular scalar instruction that is executable to perform a data operation that utilizes a single bit in the combined condition code register to generate a scalar result, and wherein the vector instruction includes the particular vector compare instruction and a particular vector instruction that is executable to generate a vector result by utilizing a first bit in the combined condition code register to generate a first part of the vector result and by utilizing a second bit in the combined condition code register to generate a second part of the vector result; a register file configured to receive results produced by execution of the particular scalar instruction and of the particular vector instruction; and a memory unit; wherein the sequencer is responsive to the memory unit and is adapted to fetch a plurality of instructions from the memory unit and to group the plurality of instructions into packets of instructions of different types to be executed in parallel by the plurality of instruction execution units.