Patent ID: 8108631

Claim:
A method of controlling memory operations in a non-coherent transactional shared memory system having a plurality of nodes connected through an interconnect network, comprising: initiating a first memory operation at a first node comprising a first processor, a first memory, a first memory controller, and a first transaction table, and a first access table, wherein the first transaction table is configured to store a mapping of the first memory operation and a list of nodes affected by the first memory operation, and wherein the list of nodes stores an entry corresponding to a second node; transmitting a plurality of memory operation data items associated with the first memory operation from the first memory controller through the interconnect network to the second node comprising a second processor, a second memory, a second memory controller, a second transaction table, and a second access table; storing the plurality of memory operation data items associated with the first memory operation to the second access table, wherein the second access table provides a mapping of memory addresses of the second memory and a list of memory operations affecting the memory addresses of the second memory, and wherein a memory address of the second memory is affected by the first memory operation; receiving, by the second node, a plurality of memory operation data items associated with a second memory operation from a third node comprising a third processor, a third memory, a third memory controller, a third transaction table, and a third access table; storing the plurality of memory operation data items associated with the second memory operation to the second access table, wherein the memory address of the second memory is affected by the second memory operation; identifying, by the second access table, a memory conflict between the first memory operation and the second memory operation in response to the second memory operation also affecting the memory address of the second memory; transmitting, in response to identifying the memory conflict, an abort signal from the second node to the third node; and receiving, by the second node, an intent to commit signal from the first node.