Patent ID: 8030983

Claim:
A clock receiver, comprising: a programmable voltage divider having an input for receiving an input signal with a cycle with a frequency and a voltage swing, and an output for outputting a modified input signal that has a same frequency as the frequency of the input signal and that has a reduced voltage swing, the modified input signal having only an alternating current (AC) component because the input capacitor blocks any direct current (DC) component of the input signal; a basic receiver including an inverter with a trip point, the basic receiver, having an input coupled to the output of the programmable voltage divider, for receiving the modified input signal, and an output for outputting an output signal having a voltage representing a logic level opposite the logic level represented by the voltage of the modified input signal at the input of the basic receiver; and a common mode setting circuit having an input coupled to the input and to the output of the basic receiver, and an output coupled to the input of the basic receiver; wherein the common mode setting circuit comprises: a first common mode setting transistor having a source coupled to the first supply potential, having a gate and a drain coupled to the input of the basic receiver, a second common mode setting transistor having a source coupled to the second supply potential, having a gate and a drain coupled to the input of the basic receiver, a first state-dependent resistive transistor having a source coupled to the first supply potential, a gate coupled to the output of the basic receiver, and a drain coupled to the input of the basic receiver, wherein a size of the first state-dependent resistive transistor and a size of the first common mode setting transistor are such that the common mode setting circuit sets, during one half cycle, the DC voltage level at the input of the basic receiver to a value between the first supply potential and the trip point, and a second state-dependent resistive transistor having a source coupled to the second supply potential, a gate coupled to the output of the basic receiver, and a drain coupled to the input of the basic receiver, wherein a size of the second state-dependent resistive transistor and a size of the second common mode setting transistor are such that the common mode setting circuit sets, during another half cycle, the DC voltage level at the input of the inverter to another value between the trip point and the second supply potential.