Patent ID: 7567099

Claim:
A frequency locked loop comprising: a digital frequency synthesizer having a first synthesizer input and being constructed and arranged to generate an output clock signal; a first counter having a first counter input to receive a reference clock signal and a second counter input to receive a system clock signal, the first counter being constructed and arranged to provide at a first counter output a first count of a number of periods of the system clock signal within at least one period of the reference clock signal; a second counter having a third counter input to receive the output clock signal and a fourth counter input to receive the system clock signal, the second counter being constructed and arranged to provide at a second counter output a second count of a number of periods of the system clock signal within at least one period of the output clock signal; and a comparator coupled to the first and second counter outputs and constructed and arranged to compare the first count with the second count and to provide at a comparator output a frequency error signal based on the comparison, wherein the comparator output is coupled to the first synthesizer input to provide the frequency error signal to the digital frequency synthesizer; and wherein the digital frequency synthesizer is constructed and arranged to adjust a frequency of the generated output clock signal based on the frequency error signal.