Patent ID: 7180332

Claim:
A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal at a relatively high clock frequency, to a second function block, which is clocked by the second clock signal at a relatively low clock frequency, where the clock synchronization circuit has: (a) a sampling unit for sampling the second clock signal using the first clock signal in order to generate samples and edge detection values of the sampled second clock signal; (b) a logic circuit which is clocked using the first clock signal and which takes an operating-mode control signal as a basis for outputting the generated samples or the generated edge detection values as a reconstructed second clock signal in the time frame of the first clock signal at an output of the logic circuit, where the output of the logic circuit is reset after outputting a value until the logic circuit receives an Enable signal, where the logic circuit generates an Edge-Too-Early signal if the generated edge detection value is at logic high before the Enable signal is received, and generates an Edge-Too-Late signal if the Enable signal is received before the generated edge detection value is at logic high, (c) and a signal delay circuit which is clocked using the first clock signal, and which delays the reconstructed second clock signal sent by the logic circuit with a variable time delay on the basis of the Edge-Too-Early signal and the Edge-Too-Late signal in order to generate the Enable signal.