Patent ID: 7800385

Claim:
A system for testing electrical assemblies comprising: a printed circuit board; a package; a plurality of electrical connections, the plurality of electrical connections electrically connecting the printed circuit board to the package; a set of electrical paths providing electrical communication between the printed circuit board and the package, the set of electrical paths including at least a first electrical path and a second electrical path; a set of interconnect paths electrically connecting individual paths of the set of electrical paths, the set of interconnect paths including at least one interconnect path electrically connecting the first electrical path and the second electrical path such that the first electrical path includes at least two first electrical path segments and the second electrical path includes at least two second electrical path segments; and a test platform configured to associate a linear equation variable with each of the at least two first electrical path segments, each of the at least two second electrical path segments, and the at least one interconnect path, the test platform further configured to employ a plurality of linear equations using the linear equation variables to identify a value for each of the least two first electrical path segments, each of the at least two second electrical path segments, and the interconnect path.