Patent ID: 8044456

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; and a cell array formed on the semiconductor substrate, including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, wherein the cell array includes: a memory cell region where the memory cells are formed; and a peripheral region that is provided around the memory cell region, in the memory cell region, the first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction, in the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line, in the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line, and the contact connecting portion is formed so as to contact with a contact plug extended in a laminating direction.