Patent ID: 7260001

Claim:
A memory for storing data comprising: a fast data reading mechanism operable to sense one or more signal values dependent upon a data value stored in said memory so as to generate a first signal transition indicative of said data value and used to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to sense said one or more signal values dependent upon said data value so as to generate a second signal transition indicative of said data value and used to generate a slow read result available after said fast read result, said slow read result being less prone to error than said fast read result; a comparator operable to compare said fast read result and said slow read result and to generate an error signal if said fast read result does not match said slow read result; and a timing checker coupled to said fast data reading mechanism and operable to detect that said first signal transition was generated within a predetermined time.