Patent ID: 7116592

Claim:
A semiconductor device comprising: a main memory cell array in which memory cells are arrayed in a matrix; a spare cell to replace a defective cell in the main memory cell array; a comparator to compare data read out from each memory cell in the main memory cell array and an expected value and determine quality of the memory cell; a control circuit configured to control repair of a defective cell detected on the basis of a comparison result of the comparator by replacing the defective cell with the spare cell; a register which stores information on the defective cell; and a determination circuit configured to determine whether a defective cell exists and whether repair is possible, on the basis of the information stored in the register, when the repair is possible, cause the control circuit to perform the control and repair the detected defective cell by replacing the defective cell with the spare cell, and when the repair is impossible, set a flag and stop the defect repair.