Patent ID: 7215576

Claim:
A data erasing method applied to a nonvolatile semiconductor memory device, comprising: setting threshold values of a plurality of memory cells at a first predetermined voltage level or more by executing programming, the programming being executed by applying a voltage to the memory cells; setting the threshold values of the memory cells at a second predetermined voltage level or less, which is lower than the first predetermined voltage level, by executing a data erasing processing to the memory cells; executing a weak programming only once by applying a voltage, which is lower than the voltage applied in the programming, to one or ones of the memory cells, the threshold values of which are lower than a third predetermined voltage level lower than the second predetermined voltage level; repeatedly executing the weak programming on one or ones of the memory cells, the threshold values of which are still lower than the third predetermined voltage level after executing the weak programming only once, until the threshold value of said one or ones of the memory cells is set to be equal to or higher than the third predetermined voltage level; and verifying whether the memory cells include a memory cell or cells the threshold values of which are higher than the second predetermined voltage level, and returning processing to be executed to the setting the threshold values of the memory cells at the second predetermined voltage level or less, when verifying that the memory cells include the memory cell or cells the threshold values of which are higher than the second predetermined voltage level.