Patent ID: 7892928

Claim:
A method, comprising: (a) forming a gate stack on a top surface of a silicon substrate, said gate stack comprising a gate dielectric layer on said substrate and an electrically conductive gate electrode on said gate dielectric layer, said gate stack having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to said sidewalls and to said top surface of said substrate; after (a), (b) forming a conformal layer over said top surface of said substrate and on said top surface and said first and second sidewalls of said gate stack; after (b), (c) tilting said substrate about an axis parallel to said longitudinal axis relative to a flux of reactive ions directed toward said top surface of said substrate said flux of reactive ions striking said conformal layer at an angle less than 90° and greater than zero degrees relative to said top surface of said substrate; after (c), (d) exposing said conformal layer to said flux of reactive ions until said conformal layer is removed from said top surface of said structure and said top surface of said substrate by said flux of reactive ions except in regions of said top surface of said substrate immediately adjacent to said sidewalls of said gate stack, said exposing leaving a first spacer on said first sidewall and a second spacer on said second sidewall; after (d), (e) etching a first trench into said substrate adjacent to said first spacer and etching a second trench into said substrate adjacent to said second spacer where said substrate is not protected by said gate stack and said first and second spacers; after (e), (f) filling said first and second trenches with silicon germanium or filling said first and second trenches with carbon doped silicon, to form respective first and second hetero-source/drains; after (f), (g) removing said first and second spacers; after (g), (h) forming a third spacer on said second sidewall of said gate stack and forming a fourth spacer on said second sidewall of said gate stack, said third spacer covering all of said first source/drain extension between said gate stack and said first hetero-source/drain, said fourth spacer covering only a portion of said second source/drain extension immediately adjacent to said second sidewall of said gate stack, said third and fourth spacers formed by blanket deposit of an additional conformal layer and reactive ion etching said additional conformal layer; and after (h), (i) performing an ion implantation or plasma doping of dopant species to form a first-diffused source/drain in said substrate adjacent to said third spacer and to form a second-diffused source/drain in said substrate adjacent to said fourth spacer.