Patent ID: 8248552

Claim:
A pixel array, comprising: a plurality of first scan lines; a plurality of second scan lines, wherein each of the second scan lines is located between two adjacent first scan lines; a plurality of data lines substantially intersected with the first scan lines and the second scan lines, wherein the second scan lines and the data lines together define a plurality of sub-pixel regions; a plurality of sub-pixels located in the sub-pixel regions, wherein each of the sub-pixels is electrically connected with one of the first scan lines, one of the second scan lines and one of the data lines respectively, and each of the sub-pixels comprises: a first switch; a second switch, wherein the first switch and the second switch are electrically connected with the same first scan line and the same data line; a first pixel electrode electrically connected with the first switch; a second pixel electrode electrically connected with the second switch, wherein the first pixel electrode and the second pixel electrode are respectively located at the opposite sides of the first scan line; and a third switch electrically connected with the second scan line and the second pixel electrode, wherein the third switch includes a capacitance coupling portion extending to be under the first pixel electrode in the neighboring sub-pixel; and a plurality of common lines, wherein the capacitance coupling portion and the common line in the neighboring sub-pixel together form a voltage adjusting capacitor.