Patent ID: 8021974

Claim:
A method of fabricating a semiconductor structure comprising: providing an interconnect structure that includes a lower interconnect level comprising a first dielectric layer having at least one conductive feature embedded therein, an upper interconnect level comprising a second dielectric having at least one via opening that exposes a portion of said at least one conductive feature located atop said lower interconnect level, said lower and upper interconnect levels are partially separated by a dielectric capping layer, and a patterned hard mask on a surface of said upper interconnect level; forming a first barrier layer on all exposed surfaces of said via opening; removing said first barrier layer at a bottom of said via opening and on said patterned hard mask while maintaining said first barrier layer on remaining sidewall surfaces of said via opening; forming a conductive protrusion in said at least one conductive feature, said conductive protrusion located at a bottom of said via opening and extends upward from bottom of said via opening and into said at least one via opening; forming a seed layer within said at least one via opening, and; filling said at least one via opening with a conductive material.