Patent ID: 6873536

Claim:
A ferro-electric memory device, comprising: an array of FeRAM memory cells associated with a plurality of word lines and plate lines and a data buffer, wherein the array is further subdivided in a word line direction into segments which are individually selectable, and wherein each segment of the array is associated with the plurality of word lines and plate lines, a pair of bitlines and a sense amplifier, and wherein each segment comprises a plurality of FeRAM memory cells which are selectable and operable to store binary data, and wherein a target memory cell of the plurality of FeRAM memory cells is selected and accessed during memory operations for the storage and retrieval of the binary data; a segment decoder operable to select a target segment of the array associated with the target memory cell; a bitline decoder operable to select the pair of bitlines associated with the sense amplifier and the target memory cell; a plate line decoder operable to select a target plate line associated with the target memory cell; a word line decoder operable to select a target word line associated with the target memory cell; and the sense amplifier associated with the target memory cell and the selected pair of bitlines, operable to determine the logic state of the target memory cell during a memory read operation; wherein the sense amplifier, segment decoder, bitline decoder, plate line decoder, and word line decoder cooperate to selectively couple and transfer binary data between the target memory cell and the data buffer, wherein the data buffer is operable to selectively couple to the target segment, thereby being shared between the segments of the array of memory cells.