Patent ID: 7068555

Claim:
A semiconductor memory device comprising: bit lines; word lines wired orthogonally on the bit lines; memory cells connected to the bit lines and the word lines, the memory cells being arranged in a matrix to form a memory block, a plurality of which are arranged in a bit line wiring direction sharing respective bit lines to form memory block columns arranged in word line wiring direction, at least one memory block column including a redundancy memory block arranged sharing bit lines with a memory block for remedying a defective memory block; a block redundancy judge section for selecting a redundancy memory block from at least redundancy memory block(s) by outputting a redundancy block select signal in case a memory block including inputted address information is a defective memory block; a block column designate section for designating a memory block column inclusive of a selected redundancy memory block by outputting a column designate signal depending on the redundancy block select signal; and a column redundancy control section for conducting column redundant control by memory block column including a redundant memory block, wherein column redundant control of a selected redundant memory block is conducted by the column redundant control section depending on the column designate signal.