Patent ID: 7947546

Claim:
A method for forming a semiconductor device comprising: providing a substrate having a device region; forming a transistor in the device region, the transistor including source and drain (S/D) regions adjacent to a gate structure, and a channel region beneath the gate structure between the source and drain regions; and forming at least a stressor region comprises forming a stressor layer having a stress in at least a portion of S/D recesses adjacent to the gate structure in the device region, the stressor region applies a strain on the channel region, wherein the stressor layer includes end of range (EOR) defects resulting from ion implantation to form the source and drain regions, and a bottom of the stressor layer is disposed below the EOR defects; and wherein the stressor layer comprises SiGe layer doped with carbon (carbon doped SiGe layer) in an amount which reduces the amount of EOR defects which resulted from the ion implantation used to form the source and drain regions in order to reduce relaxation of the stress in the stressor layer from subsequent annealing of the substrate.