Patent ID: 7494879

Claim:
A method comprising: growing a first oxide layer over a semiconductor substrate as a gate insulating layer, the substrate comprising a core power source wiring region and an input/output power source wiring region; performing a first annealing process to form a diffusion barrier layer forming an interface between the first oxide layer and the substrate; removing the first oxide layer and the diffusion barrier layer over the core power source wiring region of the substrate by masking the input/output power source wiring region; growing a second oxide layer over the core power source wiring region; and performing a second annealing process to form an Nitrogen-rich oxide gate oxide layer at an interface of the core power source wiring region, wherein the second oxide layer and the N-rich oxide gate oxide layer are formed at a position lower than the first oxide layer and the diffusion barrier layer and the top surface of the second oxide layer is in substantially a same plane as a bottom surface of the diffusion barrier layer.