Patent ID: 8689160

Claim:
A computer-implemented method for timing analysis of integrated circuit design, comprising the steps of: generating a physical layout of an integrated circuit; performing interconnect redundancy, using a computer, on the physical layout of the integrated circuit to create a plurality of redundant interconnections, wherein the interconnect redundancy is based on a physical layout of an integrated circuit to be bonded; performing a first static timing analysis to compute an first expected timing of the integrated circuit; performing a first redundant interconnections removing to remove the redundant interconnections which have timing violations according to the first expected timing; setting Manhattan distance less than or equal to a predetermined value; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting a dummy micro bump from the dummy micro bumps, which is spaced from the signal bump by the Manhattan distance; generating a routing path between the at least one interconnecting candidate and the signal bump; and outputting a chip layout through a computer.