Patent ID: 7200735

Claim:
A hybrid processor comprising: a non-configurable base processor having a base execution unit for executing base processor instructions; a configurable logic circuit having an extended execution unit for executing extended instructions different from the base processor instructions, wherein at least a single one of the extended instructions specifies at least two source operands, and at least one destination operand different from either of the source operands; and an interface circuit between the non-configurable base processor and the configurable logic circuit having: a first uni-directional datapath from the base processor to the configurable logic circuit for transfer of first data corresponding to a first one of the source operands, wherein the first data is one of a source operand specifier and a source operand value; a second uni-directional datapath from the base processor to the configurable logic circuit for transfer of second data corresponding to a second one of the source operands, wherein the second data is one of the source operand specifier and the source operand value, and a third uni-directional datapath from the configurable logic circuit to the base processor for transfer of third data corresponding to the destination operand, wherein the third data is one of a destination operand specifier and a destination operand value, wherein execution of the single extended instruction by the configurable logic circuit initiates the transfers of data on the first, second and third uni-directional datapaths, and further thereby causes the source operands to be used to compute the destination operand.