Patent ID: 6970563

Claim:
A method for parallel scrambling of a sequence of serially transmitted digital bits, said method comprising an initializing scrambling step and subsequent scrambling step; said initializing scrambling step comprising the steps of generating a scrambling bit sequence and storing said scrambling bit sequence in a scrambling register; and said subsequent scrambling step comprising: storing a sequential group of bits in the same sequence in which they were received, each of said group of bits containing the same number or fewer bits that said scrambling bit sequence; XOR-ing said sequential group of bits with corresponding bits of said scrambling bit sequence in parallel, thereby generating scrambled bits; shifting said bits in said scrambling register by a number of spaces equal to the number of scrambled bits and subsequently transmitting and storing said scrambled bits in corresponding cells of said scrambling register in lowest ordinal sequence for use in subsequent XOR-ing of a next sequential group of bits.