Patent ID: 7283405

Claim:
A semiconductor memory device comprising: a current address holding portion for holding an address for reading data, a cell array formed by memory cells arrayed in a matrix and reading out data in accordance with an address held in the current address holding portion, a reserved address holding portion receiving in advance at least a reserved address for the next read operation from outside the semiconductor memory device holding the reserved address, a data holding portion for holding the data read out from the cell array and for transferring the held data to the outside at a predetermined timing, and a control circuit for making the current address holding portion hold the reserved address held in the reserved address holding portion, making the data be read out from the cell array, and making the data holding portion hold the data when the data read out from the cell array corresponding to the address held in the current address holding portion and held in the data holding portion is ready to be transferred to the outside, wherein the control circuit outputs a busy signal indicating a busy state to the outside when preparations for transfer of the read out data have not been completed until the data is read out corresponding to the address held in the current address holding portion and the data holding portion is ready to transfer the held data to the outside, and the reserved address holding portion holds a reserved address upon receipt of the reserved address from the outside even in the busy state.