Patent ID: 7353419

Claim:
A circuit for data/clock deskewing, comprising: a clock circuit that is arranged to receive a clock select signal, wherein the clock circuit is arranged to provide a plurality of selected clock signals such that: if the clock select signal corresponds to a first logic level, a first plurality of clock signals is selected as the plurality of selected clock signals; and if the clock select signal corresponds to a second logic level, a second plurality of clock signals is selected as the plurality of selected clock signals, wherein the plurality of selected clock signals includes a first selected clock signal, a second selected clock signal, and a third selected clock signal, the second selected clock signal is delayed relative to the first selected clock signal, and wherein the third selected clock signal is delayed relative to the second selected clock signal; a data latching circuit that is arranged to provide a plurality of latched data signals by latching a selected data signal with each of the plurality of selected clock signals; and a deskew control block that is arranged to provide the clock select signal and a data delay select signal responsive to the plurality of latched data signals.