Patent ID: 8806177

Claim:
A method for translation prefetching in a computer system, comprising: instructing a prefetch engine to prefetch data, the prefetch engine being a separate processor core from a main processor and logically located between a cache hierarchy of the main processor and main memory, the prefetch engine incorporated with a system memory controller of the main processor, the data for prefetching being data that is anticipated for future access by the main processor and prefetching of the data to be performed prior to when the data is needed; searching one or more cache translation entries for a mapping of a virtual address corresponding to the prefetch data to a physical address, the step of searching performed by the prefetch engine; the prefetch engine performing address mapping translation translating the virtual address of the data to be prefetched to a physical address without interrupting the main processor and without direct operating system service, if there is no virtual to physical address mapping in the one or more cache translation entries; prefetching the data, the step of prefetching performed by the prefetch engine; and storing the translated address mapping in a respective translation table of the main processor's cache hierarchy, if there is no virtual to physical address mapping found in the one or more cache translation entries, wherein the prefetch engine is enabled to store data directly to selected levels of the main processor's cache hierarchy and maintain cache coherency of the main processor's cache hierarchy.