Patent ID: 8338911

Claim:
A semiconductor device comprising: a substrate provided with a semiconductor element; first and second interconnects provided above the substrate, each of the first and second interconnects having a line shape in a plan view, and the first and second interconnects being substantially parallel to each other; a first via plug provided above the substrate, electrically connected to a lower surface of the first interconnect on a second interconnect side, and including a first recess part at an upper end of the first via plug under a first region between interconnects, the first region between interconnects being a region between the first interconnect and the second interconnect; and a via layer insulator provided above the substrate and including the first via plug, and a first trench under the first region between interconnects, the first trench including a region adjacent to the first via plug in a width direction of the first and second interconnects, wherein an air gap is included in the first region between interconnects and in the first trench.