Patent ID: 8865599

Claim:
A method of forming a microelectronic structure, said method comprising: providing a wafer stack comprising: a substrate having a surface; and a pattern comprising a plurality of features formed in and/or on said substrate surface, wherein said features formed on the substrate surface are defined by respective sidewalls and a top surface, and wherein said features formed in the substrate surface are defined by respective sidewalls and a bottom surface; applying a planarization composition to said stack, said planarization composition covering said pattern as a non-conformal layer on said stack, wherein said planarization composition is selected from the group consisting of: (A) a composition comprising a fluorinated compound dispersed or dissolved in a solvent system, said compound comprising recurring monomeric units containing respective fluorine moieties and one or more crosslinkable functional groups; and (B) a composition comprising an acetoacetylated compound dispersed or dissolved in a solvent system; and heating said planarization composition, thereby allowing said planarization composition to self-level into a planarized layer ready for the application of subsequent layers, said planarized layer having a substantially planar surface relative to said patterned substrate wherein no etching, contact planarization, and/or polishing occurs during said self-leveling.