Patent ID: 7472327

Claim:
A pattern generator for generating a test pattern for testing an electronic device from a predetermined test data, comprising: a main memory for storing a plurality of sequence data blocks for generating the test pattern; a first sequence cache memory and a second sequence cache memory for sequentially storing the sequence data blocks; a data development section for sequentially executing the sequence data blocks stored in the first sequence cache memory and generating the test pattern; and a read-ahead means, when the data development section detects a read-ahead instruction on reading ahead the other sequence blocks during executing one sequence data block, for reading the other sequence data blocks from the main memory and storing the same in the second sequence cache memory, wherein the data development section reads the other sequence data blocks from the second sequence cache memory and executes the same when the data development section detects a jump instruction on executing the other sequence data blocks after detecting the read-ahead instruction, alternatively, reads the subsequent sequence data block from the first sequence cache memory and executes the same when the data development section does not detect the jump instruction in the one sequence data block after detecting the read-ahead instruction.