Patent ID: 8041903

Claim:
A processor comprising: a processor core; a data managing unit to read data from an external memory based on a data request command received from the processor core, and to convert the read data into batch data; and a scratch-pad memory to receive and store the converted batch data, wherein the data managing unit reads the data from the external memory using a first route which is connected with the external memory through a data cache, and wherein the scratch-pad memory comprises a first scratch-pad memory space and a second scratch-pad memory space to alternatingly store the converted batch data, and wherein when the scratch-pad memory stores the converted batch data in the first scratch-pad memory space, the processor core simultaneously processes the converted batch data stored in the second scratch-pad memory space, and wherein when the scratch-pad memory stores the converted batch data in the second scratch-pad memory space, the processor core simultaneously processes the converted batch data stored in the first scratch-pad memory space.