Patent ID: 7435658

Claim:
A method of manufacturing a metal-oxide-semiconductor (MOS) transistor, comprising the steps of: providing a substrate having a gate structure thereon; forming a first spacer on the sidewall of the gate structure; performing a pre-amorphization implantation to amorphize a portion of the substrate; performing an ion implantion to form a doped source/drain extension region in the substrate on each side of the first spacer; forming a second spacer on the sidewall of the first spacer; forming a doped source/drain region in the substrate on each side of the second spacer; performing a solid phase epitaxial process to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal; and performing a post-annealing process, wherein the annealing temperature in the post-annealing operation is higher than the operating temperature in the solid phase epitaxial process.