Patent ID: 8912575

Claim:
A semiconductor device, comprising: a semiconductor substrate including a single first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; a plurality of first contact holes passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the plurality of first contact holes to contact the first conductive layer; and a plurality of first contact plugs connected to the second conductive layer, wherein the plurality of first contact plugs are offset from the plurality of first contact holes to overlap the dielectric layer, and wherein the plurality of first contact plugs and the plurality of first contact holes are overlapped with the single first active area, and wherein the plurality of first contact plugs are connected to a single gate pattern comprised of the first conductive layer and the second conductive layer over the single first active area.