Patent ID: 7885320

Claim:
A transceiver for processing high data rate serial data, comprising: a first clock data recovery circuitry for receiving first serial data and recovering a first recovered clock from the first serial data, wherein the first clock data recovery circuitry receives the first serial data according to a first protocol; a second clock data recovery circuitry for receiving second serial data and recovering a second recovered clock from the second serial data; wherein the transceiver provides the first recovered clock, the second recovered clock, a reference clock, the first serial data and the second serial data to a plurality of clock based functionalities of the transceiver; and wherein each of the plurality of clock based functionalities performs processing of one of the first serial data and the second serial data in accordance with a clock chosen from among the first recovered clock, the second recovered clock and the reference clock, and wherein at least one of the plurality of clock based functionalities converts the first serial data to a second protocol based on the first recovered clock and transmits the first serial data, as converted, in the second protocol based on the second recovered clock.