Patent ID: 7534692

Claim:
A process for producing an integrated circuit, comprising: producing at least one lower interconnection level of the integrated circuit; producing a capacitive multilayer structure possessing a metal-insulator-metal portion which lies on a top surface of the at least one lower interconnection level and having another metal-insulator-metal portion formed in at least one capacitive trench lying within the lower interconnection level; removing a portion of an upper metal layer in the metal-insulator-metal portion to provide a metal-insulator-metal part and a laterally adjacent insulator-metal part; following removing, covering the metal-insulator-metal part and laterally adjacent insulator-metal part with an insulating protective layer; removing a part of the insulating protective layer and a vertically adjacent part of the insulator-metal portion; and then producing at least one upper interconnection level of the integrated circuit within which the metal-insulator-metal portion and insulating protective layer lie.