Patent ID: 7360128

Claim:
A test method of a memory device equipped with an internal signal generating circuit adapted to output an internal signal of a fixed cycle asynchronous with a signal from the outside, the test method comprising: generating by an entry circuit an output upon discrimination that said memory device is satisfying conditions for performing a test, when an entry information is input; generating by a gate circuit an output to activate a buffer circuit when there is generated an output of said entry circuit and a memory arrangement of said memory device is in a write enable state induced by a write enable signal, by which said internal signal is written to said memory arrangement via said buffer circuit, said write enable signal being cycled at a rate higher than the cycle of said internal signal; and then performing a measurement related to said internal signal by reading written data to the outside from said memory arrangement and detecting change points in said written data; wherein the measurement related to said internal signal is the measurement of the cycle of said internal signal.