Patent ID: 6924632

Claim:
A frequency/signal converter receiving an input clock signal and generating an output signal at an output terminal, said converter comprising: a first circuit receiving the input clock signal and generating first and second logic signals that are complementary with one another; a loop circuit that includes a first circuit line and a second circuit line that are each coupled between a first supply voltage and a second supply voltage, the first supply voltage being greater than the second supply voltage; and an integrator device, wherein a current proportional to the output signal of the converter flows in the loop circuit, the first circuit line includes a first capacitive element, and a first switch for interrupting current flow into the first capacitive element, the first switch being controlled by the first logic signal, the second circuit line includes a second capacitive element, and a second switch for interrupting current flow into the second capacitive element, the second switch being controlled by the second logic signal, and the first and second circuit lines are alternatively coupled to an input terminal of the integrator device in order to obtain a substantially constant voltage signal at the input terminal of the integrator device, the integrator device providing the output signal of the converter.