Patent ID: 7521733

Claim:
An integrated circuit, comprising: a semiconductor substrate with layers; a bipolar transistor in the semiconductor substrate; and a hetero bipolar transistor in the semiconductor substrate, wherein collector structures of the bipolar transistor and the hetero bipolar transistor are formed in different regions of the integrated circuit, and wherein the collector structures of the bipolar transistor and the hetero bipolar transistor comprise a buried layer; a collector terminal region; and an upper layer which is lower doped than the buried layer, and wherein the upper layer comprises a region, which is higher doped than a portion of the upper layer not comprising the region, the region being disposed below a base of the bipolar transistor, and below a base of the hetero bipolar transistor, wherein the base of the hetero bipolar transistor is disposed on top of the region, the base of the hetero bipolar transistor of a material different from the material from which the upper layer is made, and wherein the base layer of the bipolar transistor is implemented by a doped region in the upper layer of the collector structure, and wherein a distance between the base of the hetero bipolar transistor and the buried layer measured perpendicular to the semiconductor substrate is greater than a distance between the base of the bipolar transistor and the buried layer measured perpendicular to the semiconductor substrate.