Patent ID: 7804119

Claim:
A device structure formed in a device layer of an SOI substrate, the device structure comprising: a gate structure on a top surface of the device layer, the gate structure including a gate conductor layer with a first sidewall, a second sidewall, and a gate dielectric layer between the gate conductor layer and the top surface of the device layer; a first electrode of a first conductivity type in the device layer; and a second electrode of a second conductivity type in the device layer, the second electrode including a first doped region of the second conductivity type that is disposed in the device layer in a surrounding relationship about the first electrode, a second doped region of the second conductivity type, and a third doped region of the second conductivity type, the second doped region located in the device layer adjacent to the second sidewall of the gate structure, the third doped region extending laterally in the device layer beneath the gate structure to electrically connect the first doped region with the second doped region, the first doped region of the second electrode defining a p-n junction along a boundary shared with the first electrode, and the p-n junction including a first segment that is aligned substantially parallel to the top surface of the device layer and a second segment that extends from the first segment toward the top surface of the device layer, wherein the third doped region has a lower doping concentration than the first doped region, and the second doped region has a higher doping concentration than the third doped region.