Patent ID: 8009494

Claim:
A semiconductor memory device comprising: a bit line pair comprising a bit line and a complementary bit line; a precharge unit precharging the bit line and the complementary bit line to a voltage that is a first voltage less than a power voltage; and a sense amplifying unit comprising first and second transistors driven by a first current source and serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line, wherein the first voltage is determined by the first or the second transistor, and wherein the precharge unit includes: a third transistor connected between a node to which the first and second transistors and the first current source are connected, and a power voltage terminal, the third transistor being controlled by a first precharge signal; and a fourth transistor connected between the bit line and the complementary bit line and controlled by a second precharge signal.