Patent ID: 7518166

Claim:
A transistor of a semiconductor device, comprising: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer including a channel layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode comprising a metal thin layer diffused into a predetermined depth of the epitaxy substrate including the second conductive layer, the second Si planar doping layer, the first conductive layer and the first Si planar doping layer, the source and drain electrodes being disposed on both sides of the second conductive layer to form an ohmic contact, wherein the predetermined depth extends through a portion of the first Si planar doping layer but does not pass through the entire first Si planar doping layer, such that the source and drain electrodes are formed on the first Si planar doping layer; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer.