Patent ID: 7823100

Claim:
A computer-implemented method for generating a test case for a circuit design under test (DUT) comprising: generating a case analysis graph comprising components of each desired function of the DUT, wherein said generating is performed using the computer, the case analysis graph defines a test plan for the DUT, each component is represented in the case analysis graph by one or more goal nodes, and each goal node comprises one of a select goal for selecting one child node from a plurality of child nodes, a sequence goal for selecting each of a plurality of child nodes, and a leaf goal for providing an associated action; and selecting a sequence of the components to be exercised by the DUT as a test case, wherein said selecting is performed by traversing a path through the case analysis graph, the path comprises links coupling adjacent components in the sequence of components, each link is associated with one of a weighting factor if coupled to a select goal and a repeat count if coupled to a sequence goal, said selecting is constrained by one or more rules, said selecting comprises using weighted random selection of a link from the select goal to an associated child node from a plurality of links from the select goal to associated child nodes, each link having an associated weighting factor, and said selecting further comprises including a child node of the sequence goal in the sequence of the components a number of times corresponding to the repeat count associated with a corresponding link to the child node.