Patent ID: 7739633

Claim:
A system for generating and monitoring valid random input stimulus sequences for a logic circuit model comprising: a. a logic circuit which is initialized in one of a plurality of modes comprising one of choosing DIMM technology, choosing burst mode, choosing data flow mode, choosing latency setting, and initializing a hardware model of said logic circuit; b. an array containing an array representation of critical resource requirements, said array representing a single simulation cycle; c. said array also enumerating and generating an array representation of critical availabilities, said array representing a single simulation cycle; d. a stored matrix of a plurality of possible combinations of input stimulus sequences, weighting input sequences, wherein selecting input stimulus sequences are selected and legal times for execution of said stimulus sequences determined based on resource availability and statistically biasing input sequence execution times to provide a biased probability distribution; e. logic for parsing resource availability of a command for an available time to execute the command, and if there is no available time for executing the command, for pausing and resending the command, and if there is an available time, for selecting an optimal window and sending the command; f. logic for monitoring the critical resources to bias the input stream such that maximum utilization of all functional units within the pipeline occurs without overflow, averting delay associated with pipeline stall; and g. logic for applying the input stimulus sequence to the logic circuit model.