Patent ID: 6849895

Claim:
A non-volatile semiconductor memory device having a memory cell array of aligning plural numbers of memory cells in a matrix-like manner, each of said memory cells comprising: a source region formed in a semiconductor substrate; a drain region formed in said semiconductor substrate; a channel region formed between said source region and said rain region, and in said semiconductor substrate; a gate electrode for controlling potential of said channel region; plural numbers of charge storage grains formed between said gate electrode and said channel region, and isolated from said gate electrode and said channel region and with each other by an insulator; a first charge storage region formed with a first set of said plural charge storage grains arranged in a vicinity of said source region; and a second charge storage region formed with a second set of said plural charge storage grains arranged in a vicinity of said drain region, wherein, a first memory cell and a second memory cell neighboring with each other in the direction of channel length share said source region in common; each of said first charge storage region and said second charge storage region stores one bit of information, respectively; and each of said memory cells stores two bits of information.