Patent ID: 7464210

Claim:
A data processing system comprising: a central processing unit (CPU) which executes an interrupt exception processing each time the CPU receives an interrupt request signal, said interrupt exception processing executing another task while; a counter which retains a counter value which is a difference between a number of times of occurrence of interrupt request events and a number of times of execution of said interrupt exception processing obtained by counting up the counter value by one at each occurrence of said interrupt request events, and counting down the counter value by one at each execution of said interrupt exception processing; and an interrupt controller which immediately handles each and every interrupt request event by generating an interrupt request signal, determines a possible counter value if counting down the counter value by one, and then (1) outputs the interrupt request signal to said CPU if the possible counter value is 1 or more, and then immediately makes the CPU execute said interrupt exception processing, and (2) negates the interrupt request signal to the CPU if the possible counter value is 0 in order to avoid actually counting down the counter value to become 0.