Patent ID: 7253055

Claim:
A method of forming an array of erasable re-programmable non-volatile memory cells across at least a portion of a semiconductor substrate, comprising: forming a first layer of dielectric across at least the array portion of a surface of the substrate, forming a first layer of conductive material over the first dielectric layer across at least the array portion, forming a second layer of dielectric material over the first conductive material layer, forming a second layer of conductive material over the second dielectric layer, anisotropically etching a first set of channels through the first and second layers of conductive material, the first and second layers of dielectric material and into the substrate surface to form trenches therein, said first set of channels and trenches being elongated in one direction across the array portion and spaced apart in a second direction across the array portion, the first and second directions being orthogonal with each other, thereafter anisotropically etching a second set of channels through the first and second layers of conductive material, the first and second layers of dielectric material and into the substrate surface to form trenches therein, said second set of channels and trenches being elongated in the second direction across the array portion and spaced apart in the first direction across the array portion, thereby to leave an array of pillars across the array portion surrounded by the first and second sets of channels and trenches, and thereafter forming one set of conductors that extend across and contact the second layer of conductive material remaining as part of the pillars, said one set of conductors being elongated in the first direction and spaced apart in the second direction.