Patent ID: 7071044

Claim:
A method of making a test structure for testing to analyze characteristics of a metal oxide semiconductor transistor, comprising: forming an active device well; implanting a dopant of a first semiconductor type in the active device well including a channel region, to a concentration level specified for implantation of first semiconductor type dopant in a well of the transistor; forming a gate insulator layer over the active device well; forming a polysilcon layer on the gate insulator layer; implanting dopant of a second semiconductor type in the polysilcon layer, to a concentration level specified for a gate of the transistor; patterning the polysilcon layer to form a gate for the test structure corresponding in at least one dimension to a dimension specified for the gate of the transistor; forming insulating spacers on sidewall surfaces of the gate for the test structure; and deeply implanting dopant of the first semiconductor type into the active device well, to form regions in the test structure having concentration of dopant of the first semiconductor type substantially equal to a concentration of dopants of the second semiconductor type specified for source and drain regions of the transistor.