Patent ID: 7290239

Claim:
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs), comprising: synthesizing a design for the system; mapping components in the design onto resources on the target device; determining placement locations for the components on the target device; and restructuring the design for the system after placement locations for the components are determined and prior to routing the system to improve timing for the system by identifying critical sinks in the system, for each critical sink in the system identifying whether the critical sink has a corresponding first logic element (LE) that drives the critical sink and a second LE that is driven by the critical sink, and determining a best decomposition for each of the first and second LEs based on one of 1) swapping inputs to the first and second LEs on paths having a criticality beyond a threshold level and 2) swapping all inputs to the first and second LEs.