Patent ID: 7913126

Claim:
A semiconductor memory device in which write data of value that sets a plurality of memory cells under test to a prescribed potential in common is written to respective ones of the plurality of memory cells when a memory array is tested, said device comprising: a first circuit that compares in parallel a plurality of items of read-out data from the plurality of memory cells and expected values comprising a plurality of items of write data that set the plurality of memory cells to the prescribed potential, and outputs the test result upon compressing it to a 1-bit pass/fail signal based upon whether or not there is a match in a plurality of results of comparison relating to the plurality of memory cells; and a second circuit that forcibly sets the test result relating a memory cell under test to a value indicative of pass if the memory cell under test has been replaced with a redundant cell; wherein the parallel test of the memory array based upon comparison with an expected value is performed separate from the test of the redundant area.