Patent ID: 7397114

Claim:
A semiconductor integrated circuit device comprising: a die pad; a plurality of leads located around said die pad, each of said plurality of leads having a first surface and a second surface opposing to said first surface and a plating layer formed on said first surface of each of said plurality of leads, said plating layer providing an area for a wire bonding connection; a semiconductor chip being mounted over said die pad, said semiconductor chip having a plurality of surface electrodes; a plurality of bonding wires electrically connecting said plurality of surface electrodes of said semiconductor chip with said plurality of leads, respectively, such that one end of each of said plurality of bonding wires is contacted to said plating layer of the corresponding lead of said plurality of leads; and a resin body sealing said semiconductor chip, said plurality of bonding wires and said plurality of leads including said plating layer; wherein each of said plurality of leads has an inner lead portion sealed with said resin body and an outer lead portion exposed from said resin body; wherein, in said first surface of said inner lead portion, said inner lead portion has a first region and a second region; wherein said first region is formed with said plating layer thereon; wherein said second region is not formed with said plating layer thereon; wherein said playing layer comprises palladium; and wherein a diameter of each of said plurality of bonding wires is 30 μm or less.