Patent ID: 7026233

Claim:
A method of forming post passivation interconnects for an integrated circuit having a first plurality of contact pads in a first connection pattern, the method comprising: forming a passivation layer over the integrated circuit and over the first plurality of contact pads, wherein the first plurality of contact pads could otherwise be used to provide electrical connection to an external component in packaging the integrated circuit by the formation of wire bonds or solder balls on the first plurality of contact pads, the passivation layer being formed from a non-oxide material; forming a buffer layer over the passivation layer, the buffer layer comprising a silicon oxide layer; removing a top portion of the buffer layer; depositing a post passivation metal layer over the buffer layer after removing a top portion of the buffer layer; forming a second connection pattern in the post passivation metal layer such that portions of the second connection pattern are electrically coupled to the first plurality of contact pads, wherein the second connection pattern differs from the first connection pattern; and forming a second plurality of contact pads while forming the second connection pattern and as part of the second connection pattern.