Patent ID: 7233166

Claim:
A bus state keeper comprising: a plurality of units, each of the units comprising a multiplexer and a flip flop; wherein each of the multiplexers includes: a select input, the select input of being coupled with a respective select signal of a plurality of select signals; an output, the output being coupled to a respective bit of a first bus, the first bus being coupled to a plurality of devices, wherein the first bus is to be kept in a steady state when inactive by the plurality of units, a first input, the first input being coupled to a respective bit of a second bus, and a second input, wherein the second bus is selected as an input by the plurality of multiplexers, wherein each of the flip-flops includes: a data input, the data input coupled to each respective bit of the first bus, a data output, the data output coupled respectively to the second input of the plurality of multiplexers, and a clock input, the clock input coupled to a clock signal, wherein the plurality of flip flops are to store a state of the first bus.