Patent ID: 6920621

Claim:
A method of detecting shorts between first and second sets of interconnect lines in a device, the method comprising: driving the first and second sets of interconnect lines to a first logic level; measuring a reference current IDDQref with the first and second sets of interconnect lines at the first logic level; driving the first set of interconnect lines to the first logic level and the second set of interconnect lines to a second logic level different from the first logic level; measuring a total leakage current IDDQtot with the first set of interconnect lines at the first logic level and the second set of interconnect lines at the second logic level; determining a signature current IDDQsig equal to a difference between the IDDQtot and the IDDQref; rejecting the device if the IDDQsig exceeds a predetermined threshold; and passing the device if the IDDQsig does not exceed the predetermined threshold.