Patent ID: 7577057

Claim:
A circuit adapted to generate a write data mask signal in a synchronous memory device, comprising: an output unit adapted to control a write data mask operation for the synchronous memory device, latch a write data mask signal, and output an internal write data mask signal in response to an internal clock signal; and a reset control unit adapted to generate a reset signal for resetting the internal write data mask signal in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed, wherein the reset signal is deactivated so that the internal write data mask signal is not reset while the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, wherein the reset control unit comprises a gapless write operation detection circuit adapted to detect the gapless write operation of the synchronous memory device and to generate a detection signal, and wherein the reset control unit generates the reset signal based on a logic operation for the detection signal, the write column disable signal and a read signal indicating a read operation for the synchronous memory device.