Patent ID: 6998720

Claim:
A semiconductor package device comprising: a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval; a first planar layer formed on the semiconductor chip; a second planar layer formed on the first planar layer; an oxide layer made of polyimide based material formed on the second planar layer, wherein the bonding pads are exposed through openings in the first planar layer, the second planar layer, and the oxide layer; a seed metal layer formed on the oxide layer, on the first and second planar layers exposed in the openings, and on the bonding pads exposed through the openings; metal patterns formed on the seed metal layer, wherein each metal pattern is electrically connected to one of the bonding pads, wherein the area of each metal pattern on the oxide layer is larger than the area of the bonding pad to which the metal pattern is electrically connected, and wherein the oxide layer relieves stress on each bonding pad applied through the electrically connected metal pattern.