Patent ID: 7421558

Claim:
A memory system comprising: a memory module comprising; a plurality of memory devices configured to store data, a memory module controller configured to control interface timing associated with the plurality of memory devices in accordance with memory information and memory signal information, and a memory information storage unit configured to store the memory information and provide the memory information to the interface controller; an interface controller connecting the memory module to at least one Input/Output (I/O) device and adapted to receive the memory information from the memory module; and, a memory controller adapted to receive the memory information from the interface controller and write the memory information and the memory signal information to the memory module; wherein the memory information comprises memory initialization information and interface timing information for the plurality of memory devices, and wherein the memory module controller comprises: a transceiver configured to receive the memory signal information from the memory controller and provide the memory signal information to the memory module controller; a memory information detector configured to detect the memory information provided by the memory controller and provide the memory information to the memory device controller; a memory device controller configured to generate and control timing for a memory signal using the memory information and memory signal information; a memory interface unit configured to connect the plurality of memory devices and the memory module controller; wherein the memory device controller comprises: a memory signal generator configured to generate the memory signal using the memory signal information; a memory signal timing controller configured to control timing of the memory signal in relation to the memory information; and a memory signal buffer unit configured to buffer the memory signal and provide the memory signal to the memory interface unit.