Patent ID: 7757132

Claim:
A memory, comprising: a memory array comprising memory cells, an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells, an output register which is connected to the input/output circuit, the output register being used to output data via a data output, an input register which is connected to a data input and to the input/output circuit, the data input and the input register being used to input data into the memory cells, wherein test data is written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode and the test data is transmitted from the input register to the input/output circuit, wherein the input/output circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the input/output circuit.