Patent ID: 8009488

Claim:
A semiconductor memory device, comprising: a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array block including memory cells each having a transistor with a floating body and being configured to write/read data by performing a bipolar junction transistor operation for selected memory cells; a reference voltage generator including a reference memory cell, the reference voltage generator configured to generate a reference voltage for bit line sensing corresponding to a current flowing to the reference memory cell during a data read operation, the reference memory cell including a first terminal configured to receive a source line voltage, a gate terminal configured to receive a word line signal, and a second terminal directly coupled to a terminal of at least one of the resistors; first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation; and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.