Patent ID: 8270553

Claim:
A PLL circuit that generates a spread spectrum clock (SSC), comprising: a phase comparing unit that receives a reference clock signal and a feedback clock signal and generates a control voltage in accordance with a phase difference between the reference clock signal and the feedback clock signal; a voltage controlled oscillator that oscillates at an oscillation frequency in accordance with the control voltage and generates an output clock signal as the SSC; a phase interpolator that generates a phase-shifted signal obtained by shifting phase of the output clock signal by a phase shift amount selected from plurality of phase shift amounts mutually different by integral multiple of a basic delay amount; a frequency-dividing circuit that generates the feedback clock signal by dividing frequency of the phase-shifted signal to supply the feedback clock signal to the phase comparing unit; and controlling unit that controls the phase interpolator to gradually change a phase shift amount applied to the phase-shifted signal by a unit of the basic delay amount at timings predetermined in accordance with a modulation profile of the SSC, wherein the controlling unit controls a total phase shift amount applied to the phase-shifted signal in one period of the feedback clock signal in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of the feedback clock signal is always equal to or less than one basic delay amount, and wherein the controlling unit regularly increases or decreases the total phase shift amount applied to the phase-shifted signal in one period of the feedback clock between a first phase shift amount and a second phase shift amount in switching a modulation degree of the output clock signal from a first modulation degree to a second modulation degree, the first modulation degree being defined by the first phase shift amount corresponding to k basic delay amounts, and the second modulation degree being defined by the second phase shift amount corresponding to k+ 1 basic delay amounts.