Patent ID: 6974997

Claim:
A high-voltage MOS transistor comprising: a semiconductor substrate; a gate electrode disposed on the semiconductor substrate with an insulation film interposed therebetween; a pair of first diffusion layers formed on a surface of the semiconductor substrate and disposed apart from each other by a predetermined distance; and a pair of second diffusion layers, each adjacent to the respective first diffusion layers, facing away from the gate electrode, having a dopant dose higher than that of the first diffusion layers, wherein a source region is made up of one of the first diffusion layers and one of the second diffusion layers adjacent to the one of the first diffusion layers, while a drain region is made up of an other of the first diffusion layers and an other of the second diffusion layers adjacent to the other of the first diffusion layers, and one of the first diffusion layers extends from a region not under the gate electrode to a region under the gate electrode so as to be overlapped by the gate electrode by not less than approximately 0.5 μm such that a maximum substrate current per unit width in the semiconductor substrate is not larger than 5 μA/μm.