Patent ID: 7253039

Claim:
A method of manufacturing a CMOS transistor, comprising steps of: preparing a SOI substrate having an insulating layer between lower and upper silicon layers, a first region where an n-channel MOS transistor is to be formed, and a second region where a p-channel MOS transistor is to be formed; subsequently forming a first gate insulating layer pattern and a first gate conductive layer pattern on the upper silicon layer of the first region in the SOI substrate; forming a first source/drain region on the upper silicon layer of the first region by performing a first ion implanting process; removing the upper silicon layer of the second region, including using a mask film pattern for covering the first region as an etching mask; forming a first insulating layer on the upper silicon layer and the first gate conductive layer pattern of the first region and the insulating layer exposed in the second region; forming a second insulating layer on the first insulating layer; exposing a portion of a surface of the first insulating layer in the second region by removing a portion of the second insulating layer; forming a silicon epitaxial layer on the surface of the first insulating layer exposed in said exposing step and removing the second insulating layer; forming a second gate insulating layer pattern and a second gate conductive layer pattern on the silicon epitaxial layer; and forming second source/drain regions on the silicon epitaxial layer by performing a second ion implanting process.