Patent ID: 8448120

Claim:
An integrated circuit design method, comprising: performing a place and route operation using a place and route electronic design automation (EDA) tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device, the place and route operation being constrained by a plurality of single patterning spacer technique (SPST) routing rules, wherein the SPST routing rules cause alternating first tracks and second tracks to be laid out, and first and second patterns to be laid out along the first and second tracks respectively, such that the first patterns are to be included in the photomask, and the second patterns are to be excluded from the photomask but defined between spacers, the spacers to be formed adjacent the circuit pattern formed using the first patterns of the potomask; emulating dummy conductive fill patterns within the place and route EDA tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask; and performing RC timing analysis of the circuit pattern within the place and route EDA tool, the RC timing analysis being performed based on the preliminary layout and the emulated dummy conductive fill patterns.