Patent ID: 6885608

Claim:
A multi-port memory circuit comprising: a plurality of dynamic memory cells, each dynamic memory cell including a capacitor that forms a storage node; a first NMOS transistor having a gate electrode that serves as a write select terminal connected to a write word line, a first signal electrode connected to the storage node, and a second signal electrode connected to a write bit line to write a data bit; and a second NMOS transistor having a gate electrode that serves as a read select terminal connected to a read word select signal line that orders data word readout, a first signal electrode connected to the storage node, and a second signal electrode connected to a read bit line to read a data bit; a write address select circuit that activates the write word line when selected by a write word select signal that orders data word writing and a write bit select signal that orders data bit writing; a plurality of sense amplifier circuits that respectively amplify data bit signals that are respectively output on the read bit lines; a plurality of sense amplifier enable circuits that respectively enable the sense amplifier circuits in accordance with a sense amplifier enable signal that becomes a high level in response to activation of the read word select signal line; a plurality of refresh circuits each of which, in response to a low level output from corresponding one of the sense amplifiers, writes a low level data bit on the dynamic memory cell again via corresponding one of the read bit lines in an interval during which the sense amplifier enable signal is at a low level; and a precharge circuit that precharges the write bit lines and the read bit lines.