Patent ID: 7506081

Claim:
A system including: a Network Processor including at least one Data Flow Chip, at least one Embedded Processor Complex EPC chip, at least one Scheduler chip wherein the at least one EPC chip and the at least one Scheduler chip are operatively coupled to the at least one Data Flow Chip; a plurality of memory elements with each one coupled by a separate bus to the at least one Data Flow Chip, wherein a bandwidth on each bus is 7.75 Gbps; a first high speed data port that transmits data out of the Data Flow Chip, wherein a bandwidth of the high speed data port is 10 Gbps; and an arbiter operatively coupled to the Data Flow Chip, said arbiter being responsive to Read (R) Requests to cause multiple ones of the bus to transmit data from associated memory elements simultaneously wherein the combined data bandwidth on the multiple ones of the bus is sufficient to meet Bandwidth requirements of the high speed port.