Patent ID: 8484592

Claim:
A computer-implemented timing verification method for deterministic and stochastic networks and circuits, comprising the steps of: forming a directed acyclic graph representing portions of an electronic digital circuit having circuit elements comprised of sources and sinks, the graph having a first plurality of corresponding source and sink vertices connected by a second plurality of edges thereby creating paths which can be traversed along the directed acyclic graph; formulating a base case using valued sums of products algebra (VSOP), the base case representing a last circuit loop which takes a union of all paths ending at the sinks; inductively building from the base case a path database in a topological order of the circuit elements from vertices representing the source circuit elements; performing path queries on all paths using the VSOP algebra; wherein the path queries return a path delay timing cost for all of the electronic digital circuit; and displaying a record verifying whether the path delay timing cost is within a margin of a specified timing performance requirement of the electronic digital circuit.