Patent ID: 7405090

Claim:
A method of measuring an effective channel length and an overlap length in a MOSFET, comprising: forming a first MOSFET, a second MOSFET and a third MOSFET on a substrate, the first MOSFET including a first gate pattern that has a first length and a first effective width, the second MOSFET including a second gate pattern that has the first length and a second effective width different from the first effective width, and the third MOSFET including a third gate pattern that has a second length different from the first length and a third effective width; obtaining a parasitic capacitance between the first, second and third gate patterns and the substrate in the first, second, and third MOSFETs based on first and second capacitances, which are measured by applying a first voltage between the first and second gate patterns and the substrate; applying a second voltage between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure a preliminary third capacitance and a preliminary fourth capacitance; determining a third capacitance and a fourth capacitance by excluding the parasitic capacitance from the preliminary third capacitance and the preliminary fourth capacitance; determining overlap lengths of the first, second and third gate patterns based on the third and fourth capacitances; and determining effective channel lengths of the first, second and third gate patterns based on the overlap length.