Patent ID: 7906805

Claim:
A reduced-edge flash transistor, comprising: (a) an active region bounded by a shallow trench isolation region; (b) a control gate overlaying a portion of the active region; (c) a charge storage region disposed above the active region and aligned with and underneath the control gate for at least that portion of the control gate overlaying the active region; (d) a conductively doped source region comprising a first portion of the active region that is not overlaid by the control gate and charge storage region; and (e) a conductively doped drain region comprising a second portion of the active region that is not overlaid by the control gate and charge storage region, wherein: (i) the source region and the drain region are positioned with respect to each other so that current passes from the drain region to the source region through a channel region underneath the charge storage region when the transistor is in the on state, (ii) the current does not approach the shallow trench isolation region at edges of the channel region.