Patent ID: 7284092

Claim:
A digital data processing device, comprising: instruction logic which selects and decodes instructions for execution; execution logic which performs operations specified by said instructions; a plurality of registers storing register data which is referenced using register identifiers from said instructions, said plurality of registers being organized as a plurality of levels, including: (a) a first level having a first access latency time and a first number of registers; and (b) a second level having a second access latency time and a second number of registers, said second access latency time being longer than said first access latency time, said second number of registers being greater than said first number of registers, register data contained in said registers of said first level being a subset of register data contained in said registers of said second level; wherein at least some said instructions specify multiple registers of said second level, each specified register containing a respective operand for performing the respective operation specified by the respective instruction; wherein each register of a first subset of said first level of registers is for storing the contents of a register of a corresponding subset of a plurality of discrete subsets of registers of said second level, said corresponding subset of registers containing a plurality of registers of said second level, said first subset of registers of said first level containing a plurality of registers; and wherein each register of a second subset of said first level of registers is for storing an operand contained in a register of said second level specified by a first instruction of said at least some instructions specifying multiple registers of said second level, wherein the first instruction specifies multiple registers of the same subset of said plurality of discrete subsets of said second level, said second subset of registers of said first level containing at least one register, said first and second subsets of said first level being discrete.