Patent ID: 7439172

Claim:
A method of manufacturing a circuit, comprising the steps of: providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a first dielectric layer of first dielectric layer material above said first wiring level, said first dielectric layer having a plurality of interconnect openings and a plurality of gap openings; pinching off said interconnect openings and said gap openings with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in said gap openings; and forming: metallic conductors comprising second wiring level conductors, and interconnects at said interconnect openings while maintaining said relatively low-k volumes in said gap openings, said first wiring level conductors, said second wiring level conductors, and said interconnects forming a series of conductor structures, said gap openings with said relatively low-k volumes reducing parasitic capacitance between adjacent ones of said conductor structures as compared to an otherwise comparable circuit not including said gap openings with said relatively low-k volumes.