Patent ID: 6996760

Claim:
A built-in self-test controller, comprising: a built-in self-test engine configured to execute a built-in self-test and generate an indication of whether the executed built-in self-test is completed; and a built-in self-test signature including the indication, wherein the built-in self-test engine includes: a logic built-in self-test engine; and a logic built-in self-test signature; wherein the built-in self-test controller is configured to: enter a reset state; enter an initiate state entered from the reset state upon receipt of a logic built-in self-test run signal; scan a scan chain responsive to entering the initiate state; step to a new scan chain; and repeat the previous scanning and stepping until the content of a pattern generator in the logic built-in self-test engine of the built-in self-test controller equals a predetermined vector count.