Patent ID: 7786524

Claim:
A semiconductor device, comprising: a semiconductor substrate including a first region and a second region adjacent to the first region; a floating gate electrode formed above the semiconductor substrate in the first region, the floating gate electrode including a first upper surface and a first width; a dummy gate electrode formed above the semiconductor substrate in the second region, the dummy gate electrode including a second upper surface and a second width being greater than the first width of the floating gate electrode; a control gate electrode formed above the floating and dummy gate electrodes, the control electrode including a first lower surface facing the first upper surface of the floating gate electrode and a second lower surface facing the second upper surface of the dummy gate electrode; a first gate insulating film located between the floating gate electrode and the control gate electrode, the first gate insulating film including a first thickness; and a second gate insulating film located between the dummy gate electrode and the control gate electrode, the second gate insulating film including a second thickness being greater than the first thickness of the first gate insulating film, wherein a first distance between the first upper surface of the floating gate electrode and the first lower surface of the control gate electrode is smaller than a second distance between the second upper surface of the dummy gate electrode and the second lower surface of the control gate electrode.