Patent ID: 8421124

Claim:
A semiconductor device structure, comprising: a substrate having a first well disposed therein and having a first depth, the first well having a first conductivity type; a second well of the first conductivity type disposed in the first well and having a second depth less than the first depth, the second well being doped to a higher concentration than that of the first well, the second well surrounding part or all of a center portion of the first well; a third well having a second conductivity type disposed in the first well, filling a portion of the second well; a layer having the first conductivity type in an upper portion of the third well and having a thickness less than the second depth, an upper surface of the layer being aligned with the upper surface of the second well; an emitter region having the first conductivity type and a rectangular shape disposed in a center portion of the layer, the emitter region being doped to a higher concentration than that of the layer and extending through the layer into the third well; a base region having the second conductivity type and a shape of a rectangular ring surrounding, separated from, and concentric with the emitter region, the base region being doped to a higher concentration than that of the third well and extending through the layer into the third well; and a collector region having the first conductivity type and a shape of a rectangular ring surrounding, separated from, and concentric with the base region, the collector region being doped to a higher concentration than that of the layer and extending through the layer into the third well.