Patent ID: 7326987

Claim:
A semiconductor structure compnsing: a substrate comprising a plurality of levels formed thereupon; a metal-insulator-metal (MIM) capacitor formed on an inter-level dielectric layer in a first of the plurality of levels; a second of the plurality of levels is located between an upper surface of the substrate and the first of the plurality of levels, the second of the plurality of levels comprises a field effect transistor (FET) formed thereupon; an insulator layer selectively formed on said MIM capacitor encapsulating at least a top metal plate of said MIM capacitor and covering only a top surface and sidewalls of said top metal plate, sidewalls of a capacitor dielectric layer, and a portion of a top surface of a bottom metal plate, wherein portions of the inter-level dielectric layer are insulator layer-free, and wherein a total area of said insulator layer-free portions is at least equal to about thirty percent of a surface area of the upper surface of the substrate.