Patent ID: 6995603

Claim:
A high efficiency charge pump, comprising: a first clock signal alternately swinging between a first clock high level and a first clock low level; a second clock signal alternately swinging between a second clock high level and a second clock low level, in which the second clock high level and the first clock high level are non-overlapping in time with respect to each other; a first capacitor to which the first clock signal is applied; a second capacitor to which the second clock signal is applied; a first former-stage clock signal alternately swinging between a first former-stage clock high level and a first former-stage clock low level; a second former-stage clock signal alternately swinging between a second former-stage clock high level and a second former-stage clock low level, in which the second former-stage clock high level and the first former-stage clock high level are non-overlapping in time with respect to each other; a first former-stage capacitor to which the first former-stage clock signal is applied; a second former-stage capacitor to which the second former-stage clock signal is applied; a circuit for charging the first former-stage capacitor and the second former-stage capacitor; a first switching circuit for coupling the second former-stage capacitor with the first capacitor when turned on, such that an amount of charge is transferred between the second former-stage capacitor and the first capacitor; a second switching circuit for coupling the first former-stage capacitor with the second capacitor when turned on, such that an amount of charge is transferred between the first former-stage capacitor and the second capacitor; and a first reverse current preventing circuit for turning off the first switching circuit when the first clock signal is at the first clock high level and the second former-stage clock signal is at the second former-stage clock low level, thereby preventing a first steady-state reverse current from flowing through the first switching circuit out of the first capacitor, wherein: the first former-stage clock low level is shorter in time than the first clock low level and is completely covered in time within the first clock low level, and the second clock high level is shorter in time than the second former-stage clock high level and is completely covered in time within the second former-stage clock high level.