Patent ID: 7145491

Claim:
A time-interleaved delta-sigma modulator for converting an analog signal to a digital signal, comprising, a plurality of channel blocks, which has different phase of clock frequency, each channel block consisted of a first adder, a second adder, and a comparator, wherein, said first adder receives an input signal according to clock frequency of each channel block, and an n channel block output u n of the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output v n of the second adder is transmitted to the second adder of an n+2 block, and an output y n that passes an n block comparator is transmitted to the first adder and the second adder of an n+2 block, so that said modulator sequentially receiving output from each block comparator for generating a final output y.