Patent ID: 7333905

Claim:
A method of determining duty cycle information for a variable duty cycle circuit, the method comprising: providing, by a clock signal generator, a clock signal to the variable duty cycle circuit, the variable duty cycle circuit in response providing an output signal which exhibits a duty cycle dependent on a duty cycle index, the output signal exhibiting a first frequency; providing, by the variable duty cycle circuit, the output signal to a divider circuit which fails at a maximum frequency dependent on the duty cycle index, wherein divider circuit failure occurs when the divider circuit fails to divide the output signal of the variable duty cycle circuit; sweeping, by the clock signal generator, the frequency of the clock signal from the first frequency up to a second frequency above which divider circuit failure occurs; determining duty cycle information for the output signal from the second frequency; and determining divider circuit failure by a loss of synchronism between the clock signal and a divided output signal of the divider circuit.