Patent ID: 6873215

Claim:
A power down system for an integrated circuit that enables a power down mode to be maintained for a predetermined time; said power down system comprising: an oscillator; a low power oscillator; at least one environmental sensor; and an oscillator control circuit controlling both said oscillator and said low power oscillator and receiving data from said at least one environmental sensor; said oscillator control circuit including a real time counter; said oscillator control circuit being so configured that said oscillator is energized when said oscillator control circuit is in a normal mode; said oscillator control circuit being so configured that: when a reset signal is received: environmental data is acquired by said oscillator control circuit and stored in a first memory; and said oscillator control circuit measures an oscillation frequency of said low power oscillator and stores the frequency in a second memory; when a power down signal is received: environmental data is acquired by said oscillator control circuit and compared with the stored environmental data; should the acquired environmental data differ from the stored environmental data by at least a predetermined tolerance, said oscillator control circuit measures an oscillation frequency of said low power oscillator and overwrites the data contained in the second memory; said oscillator control circuit uses the oscillation frequency of said low power oscillator stored in the second memory to set said real time counter so as to maintain the power down mode for the predetermined time, and said oscillator control circuit turns off said oscillator and uses said low power oscillator for the duration of the power down.