Patent ID: 7603441

Claim:
A method comprising: an automatic configuration of a plurality of on-chip interconnects of an on-chip network, including, determining a topology of the on-chip network wherein the determined topology is a directed acyclic graph tree or a fully connected graph; configuring a plurality of bridge agents and core agents in the on-chip interconnects to communicate with each other based on said topology by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect, where a first bridge agent is configured to communicate from a first on-chip interconnect to a second on-chip interconnect; configuring a system address map of said network, wherein the first bridge agent and the core agents have address matching components inside the agent and check a correctness of an address by matching the address to the system address map; and configuring a plurality of signals communicated between components in the on-chip network.