Patent ID: 7840864

Claim:
An integrated circuit, comprising: a test pin, a select enable pin, a functional clock pin, a scan-in pin and a scan-out pin; a test controller having a test input connected to said test pin, a select enable input connected to said select enable pin, a functional clock input connected to said functional clock pin, and a control output; a scan chain comprised of serially connected latches and corresponding multiplexers, a first stage of each latch having an data input and a clock input, a second stage of each latch having a data output, each multiplexer having a first selectable input, second selectable input, an output and a select enable input, the clock input of each latch of said scan chain connected to functional clock pin, the select enable input of each multiplexer of said scan chain connected to said control output, the data output of a previous latch of said scan chain connected to the first selectable input of a subsequent multiplexer corresponding to an immediately subsequent latch, the output of said subsequent multiplexer connected to the data input of said immediately subsequent latch, first selectable input of a first multiplexer of said scan chain connected to said scan-in pin and the output of a last latch of said scan chain connected to said scan-out pin.