Patent ID: 8884976

Claim:
An image processing apparatus, comprising: a memory control circuit that receives a plurality of pixel data each representing a value of each of a plurality of pixels that constitute each of a plurality of frames during each of a plurality of frame periods and stores the plurality of pixel data in a frame memory; an image processing circuit that processes the plurality of pixel data stored in the frame memory to generate a plurality of processed pixel data; and an output circuit that outputs the plurality of processed pixel data, wherein the memory control circuit includes a dividing circuit that divides each of the plurality of pixel data into an upper bit portion and a lower bit portion other than the upper bit portion to generate a plurality of upper bit portions and a plurality of lower bit portions of the plurality of pixel data, an upper bit processing circuit that stores the upper bit portions in the frame memory, and a lower bit processing circuit that stores the lower bit portions in the frame memory; the image processing circuit generates the plurality of processed pixel data by using the upper bit portions of the plurality of pixel data stored in the frame memory; and the lower bit processing circuit stores the lower bit portions in the frame memory by: (i) dividing the lower bit portion of each of the plurality of pixel data into n unit portions, each unit portion including a different bit of the lower bit portion, n being an integer larger than one, and storing in the frame memory, during each frame period of n successive frame periods, a different unit portion of the n unit portions of each of the plurality of pixel data; or (ii) dividing the plurality of pixels constituting each of the plurality of frames into n groups, and storing in the frame memory during each frame period of n successive frame periods, the lower bit portions of the plurality of pixel data that represent the values of the plurality of pixels in a different group of the n groups.