Patent ID: 7335560

Claim:
A method of fabricating a nonvolatile memory device, comprising: forming a vertical structure in which a first oxide layer pattern, a nitride layer pattern, and a second oxide layer pattern are sequentially stacked on a semiconductor substrate, wherein part of the surface of the semiconductor substrate is exposed by the vertical structure, and the surface of the nitride layer pattern is exposed by the second oxide layer pattern; forming a third oxide layer on exposed surfaces of the vertical structure and the semiconductor substrate; forming a polysilicon layer on the third oxide layer; forming a control gate electrode of the polysilicon layer by performing a planarization process until the second oxide layer pattern is exposed; performing an etching process using the control gate electrode as an etching mask until part of the surface of the semiconductor substrate is exposed, wherein an ONO layer where a tunneling layer of the first oxide layer pattern, a charge trapping layer of the nitride layer pattern and a blocking layer of the third oxide layer are sequentially stacked to be aligned with a gate insulating layer is arranged; and forming a source region and a drain region by performing an ion implantation process on the semiconductor substrate exposed by the control gate electrode.