Patent ID: 8613861

Claim:
A. method of manufacturing vertical transistors, comprising the steps of: S 1 : forming a substrate with two opposing support portions spaced from each other at a selected distance to form a trench which includes a bottom wall and two side walls connecting to the bottom wall, each of the support portions including a top wall remote from the bottom wall of the trench; S 2 : covering a conductive layer on the bottom wall and the side walls of the trench and the top walls of the support portions via chemical vapor deposition; S 3 : removing the conductive layer on the bottom wall of the trench and the top walls of the support portions via anisotropic etching through an etch back process; S 4 : forming an oxidized portion in the trench which includes the conductive layer; S 5 : etching a portion of the oxidized portion until reaching a selected elevation; and S 6 : etching the conductive layer until reaching the selected elevation to form in two gates without contacting each other, wherein the step S 4 includes the steps of: S 41 : providing protective layer on surfaces of the conductive layer and the bottom wall of the trench; S 42 : filling an oxidized material in the protective layer to fOrm the oxidized portion; S 43 : annealing and hardening the oxidized portion; and S 44 : flattening the oxidized portion via chemical mechanical polishing.