Patent ID: 7337100

Claim:
A method comprising: providing a high-level design language representation of an integrated circuit design; obtaining a first netlist for the integrated circuit design from a first synthesis tool; unmapping the first netlist to obtain a gate-level representation of the first netlist; resynthesizing the integrated circuit design using a second synthesis tool to generate a second netlist; and generating a final integrated circuit design using the second netlist, the final integrated circuit design to be used in producing an integrated circuit, wherein the resynthesizing step further includes: executing a partial fit against the gate-level representation of the first netlist to determine delays for the gate-level representation; executing a resynthesis of the partially-fit gate-level representation using the gate level representation from the first tool, the determined appropriate delays from the second tool, and a different synthesis algorithm than was used to generate the first netlist, and identifying portions of the gate-level representation as timing-critical portions or timing non-critical portions; and remapping the timing-critical portions of the resynthesized gate level representation with a bias toward timing improvements and concurrently remapping the timing non-critical portions with a bias toward area minimization to generate the second netlist, the second netlist being at least partially optimized for both performance and area requirements of the integrated circuit design.