Patent ID: 8892848

Claim:
A processor comprising: a first register comprising a plurality of data fields, wherein each of the plurality of data fields in the first register corresponds to an offset for a data element to be prefetched into a cache memory, wherein for each data field in the first register, a first value indicates a corresponding element has not been prefetched into the cache memory and a second value indicates that the corresponding data element has been prefetched into the cache memory; a decode stage to decode a first instruction; and one or more execution units, responsive to the decoded first instruction, to: read the values of each of the data fields in the first register; and for each data field of the plurality of data fields in the first register having the first value, access the corresponding data element, prefetch the corresponding data element into the cache memory, and change the value of the data field in the first register from the first value to the second value.