Patent ID: 7443742

Claim:
A memory arrangement for processing data, comprising: a memory; an interface, to which read data is applied in response to a read access to said memory and to which an RDT clock signal being derived from an internal clock signal and being in synchronism with said read data is permanently applied; said interface being operatively coupled to said memory; a DLL circuit for determining an optimum sampling time for said read data; said DLL circuit providing, at a clock output, a delayed clock signal defining said optimum sampling time for said read data being applied to said interface and being in synchronism with said internal clock signal; said DLL circuit providing said delayed clock signal as a signal obtained by comparing said internal clock signal with said RDT clock signal and shifting said obtained signal if at least one of a set-up time or a hold time is violated; and at least one register device comprising a data input and a clock input; said data input being connected to said interface and said delayed clock signal being applied to said clock input in order to sample said read data being applied to said interface.