Patent ID: 7271052

Claim:
A method for forming an array of memory cells comprising: forming an arrayed plurality of pillars such that the pillars extend vertically from a substrate wherein the pillars and substrate comprise semiconductor material having a band-gap energy greater than silicon; doping the pillars and substrate a first conductivity type; forming insulator on a surface of the substrate to extend between adjacent pillars along a first direction and such that the insulator is substantially absent along the first direction between adjacent pillars in a second direction and so as to define trenches extending in the first direction and arranged between adjacent pillars and interposed insulator; doping upper regions of the pillars with dopant of a second conductivity type so as to define drain regions; doping the substrate with dopant of the second conductivity type so as to define source lines extending in the first direction wherein the doping the pillars and the substrate the first conductivity type and the doping the upper regions of the pillars and the source regions with dopant of the second conductivity type defines floating body regions within the pillars and wherein the source lines are formed such that depletion regions extend from the source lines so as to merge with depletion regions of adjacent source lines to define the floating body regions; depositing gate dielectric along first sides of the pillars; depositing capacitor dielectric along opposed second sides of the pillars; forming conductive word lines extending along the first direction atop the gate dielectric; forming body capacitor plates atop the capacitor dielectric; and forming date/bit lines interconnecting drain regions along the second direction.