Patent ID: 7003627

Claim:
A peripheral controller for coupling a peripheral to a host computing device, and for use with an optional external memory, the peripheral controller comprising: a host interface implementing an expansion bus protocol compatible with the host computing device; a memory interface implementing a memory bus protocol compatible with the external memory; a host-visible memory configured to store operational CIS data; an internal initialization memory having default CIS data; control logic coupled to the host interface, the memory interface, the host-visible memory, and the internal initialization memory wherein if the control logic determines that the external memory is presetn and programmed then the host-visible memory is initialized at least in part from the external memory; wherein if the control logic determines that the external memory is blank, then the host-visible memory is initialized at least in part from the internal intialization memory; wherein if the control logic determines that the external memory is absent and an I/O-pin configuration is in a first state, then the host-visible memory is initialized at least in part from the internal initialization memory; and wherein if the control ligic determines that the external memory is absent and the I/O pin configuration is in a second state, then the host-visible memory is initialized at least in part with FFh in the first byte of the CIS data.