Patent ID: 7558720

Claim:
A method of dynamically checking electro static discharge (ESD) guidelines for an integrated circuit (IC) design to ensure that adequate ESD protection has been provided in the IC design, the method comprising: (a) providing an ESD guidelines checker that includes a calculate function for computing a desired number of ESD devices to be provided around a selected location in the IC design and an optimum size and dispersion of said devices; (b) providing a simulation environment for the IC design based upon a process technology to be utilized in implementing the IC design; (c) utilizing the simulation environment to generate corresponding simulation runsets for the IC design; (d) utilizing a circuit simulator to simulate the simulation runsets to generate simulation results that include trigger mechanisms for invoking the calculate function; (e) processing the simulation results to identify an ESD element design for the IC design; (f) analyzing an ESD element design to determine if the ESD element design meets predefined convergence criteria utilizing a convergence function; (g) if the ESD element design meets the predefined convergence criteria, utilizing the ESD element design as an optimum ESD element design for the IC design; and (h) if the ESD element design does not meet the predefined convergence criteria, modifying the ESD element design and iteratively performing steps (c)-(g) until the modified ESD element design meets the predefined convergence criteria.