Patent ID: 8653861

Claim:
A delay circuit comprising: a control voltage generating circuit; and a delay generating unit, wherein the delay generating unit comprises: at least one third transistor controlled by the control voltage; and an inverter circuit connected to at least one of the first power supply and the second power supply via the third transistor, and wherein the control voltage generating circuit comprises: a reference voltage generating unit that includes a plurality of first transistors of a same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistors as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage generating unit, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.