Patent ID: 7184295

Claim:
A memory device, comprising: a memory cell including: a memory element which stores information according to a state of electric resistance, and a circuit element as a load connected in series to said memory element; wherein: an operation to change said memory element from a state of high resistance value to a state of low resistance value is defined as writing, and an operation to change said memory element from a state of low resistance value to a state of high resistance value is defined as erasing, a resistance value of said memory element after said writing is set to a plurality of different levels by controlling a voltage or current which is applied to said circuit element or to said memory element at a time of said writing, in said memory element, different information is assigned to each of said plurality of levels in the state of low resistance value and to the state of high resistance value after said erasing, and information of three values or more can be stored respectively in said memory element in said memory cell, wherein: said circuit element comprises a MIS transistor, access to said memory element in said memory cell is controlled by said MIS transistor, and a gate voltage applied to a gate of said MIS transistor is controlled at the time of said writing, so that a resistance value of said memory element after said writing is set to said plurality of different levels.