Patent ID: 7650440

Claim:
A direct memory access (DMA) module, comprising: an address register configured to store a memory address consisting of m least significant bits and n most significant bits, wherein the memory address word size is n+m bits; a memory port having n+m memory address connections for coupling to a random access memory (RAM), wherein n outputs of the address register are coupled to n respective ones of the memory address connections; a plurality of multiplexers, each of the plurality of multiplexers having a plurality of inputs and an output, wherein the outputs of the plurality of multiplexers are coupled to m respective ones of the memory address connections and m first inputs of the plurality of multiplexers are coupled to respective ones of m outputs of the address register; a plurality of peripheral ports, each of the plurality of peripheral ports having m or less than m address connections; the m or less than m address connections of each of the plurality of peripheral ports are connected to respective ones of the plurality of inputs of the plurality of multiplexers; and an address source select register configured to select appropriate configurations of the plurality of multiplexers so that the m or less than m address connections of the selected one of the plurality peripheral ports are coupled to m or less than m of the memory address connections of the memory port, wherein the peripheral coupled to the selected one of the plurality of peripheral ports controls m or less than m least significant bits of the address connections of the memory port, and the address register controls the address connections not controlled by the peripheral coupled to the selected one of the plurality of peripheral ports.