Patent ID: 8004900

Claim:
A method for erasing at least one set of series-connected non-volatile storage elements formed on a substrate, the method comprising: in a first time period, driving at least one select gate of the at least one set of series-connected non-volatile storage elements at a non-zero level; in a second time period which follows the first time period, ramping up an erase voltage which is applied to the substrate while continuing to drive the at least one select gate at the non-zero level; in a third time period which follows the second time period, continuing to ramp up the erase voltage, until the erase voltage reaches a final erase voltage level, while floating a voltage of a control gate of the at least one select gate; and in a fourth time period which follows the third time period, driving the erase voltage at the final erase voltage level while continuing to float the voltage of the control gate of the at least one select gate.