Patent ID: 7487317

Claim:
A method of performing computer system operations, comprising: obtaining a first thread associated with a first cache miss rate; obtaining a second thread associated with a second cache miss rate; measuring a first shared cache miss rate of the first thread and the second thread by concurrently executing the first thread and the second thread, wherein the first shared cache miss rate is a function of the first cache miss rate and the second cache miss rate; estimating the first cache miss rate from the first shared cache miss rate, wherein a value of the first cache miss rate is unknown prior to measuring the first shared cache miss rate; identifying a plurality of processing cores, wherein each of the plurality of processing cores is associated with one of a plurality of maximum cache miss rates, and wherein each of the plurality of maximum cache miss rates is not less than the first cache miss rate; identifying a lowest maximum cache miss rate of the plurality of maximum cache miss rates; selecting a processing core of the plurality of processing cores associated with the lowest maximum cache miss rate; and assigning the first thread to the processing core.