Patent ID: 8466509

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first impurity diffusion region and a second impurity diffusion region, which are formed at a distance from each other in the semiconductor substrate; a third impurity diffusion region and a fourth impurity diffusion region, which are formed at a distance from each other in the semiconductor substrate, and which have impurity concentrations lower than those of the first and second impurity diffusion regions, and the third impurity diffusion region which is formed adjacently to the second impurity diffusion region; a first thermal oxidation film formed on a part of the first impurity diffusion region and covering the second impurity diffusion region, and a second thermal oxidation film formed on the semiconductor substrate between the third and fourth impurity diffusion regions; a flash memory cell including a floating gate formed of a first conductive film formed on the first thermal oxidation film, an intermediate insulating film, and a control gate formed of a second conductive film, and the first and second impurity diffusion regions are source/drain regions of the flash memory cell; an insulating sidewall formed beside the floating gate; a MOS transistor including a gate electrode formed on the second thermal oxidation film, and the third and fourth impurity diffusion regions are source/drain regions of the MOS transistor; a first metal silicide layer formed on a second part of the first impurity diffusion region, a second metal silicide layer on the fourth impurity diffusion region, and a fourth metal silicide layer formed on the third impurity diffusion region; an interlayer insulating film which covers the flash memory cell and the MOS transistor; and a first conductive plug formed in the interlayer insulating film and reaching the first metal silicide layer, wherein a part of an upper surface of the first thermal oxidation film contacts with the interlayer insulating film.