Patent ID: 8141027

Claim:
A method of automatic calibration of a computer executable design for manufacturing (DfM) simulation tool used in semiconductor manufacturing, the method comprising: providing, as a first input to the DfM simulation tool, one or more defined rules for each of one or more semiconductor device levels to be simulated by the DfM simulation tool, and providing, as a second input to the DfM simulation tool, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures across the ranges and increments, with respect to a reference circuit design; providing, as a third input to the DfM simulation tool, the reference circuit design, which comprises a circuit design previously determined to be manufacturable; executing, with the DfM simulation tool, each of the one or more defined rules for each of the one or more semiconductor device levels to be simulated, and outputting a fail count for the reference circuit design at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit design; and providing, as a fourth input to the DfM simulation tool, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit design.