Patent ID: 8677070

Claim:
A cache memory control apparatus, comprising: a cache memory; a fetch port, including a plurality of entries, configured to hold access requests to the cache memory, and hold a requested flag that is provided for each of the plurality of entries of the fetch port indicating whether a data transfer is requested; a queue register configured to hold information that indicates an entry holding an oldest access request among the plurality of entries of the fetch port; an entry selection circuit configured to select an access request to be processed next from the access requests held in the plurality of entries of the fetch port; a cache miss determination circuit configured to determine whether there is data of the access request selected by the entry selection circuit in the cache memory; a data transfer request control circuit configured to request, when there is no data of the access request in the cache memory, data transfer to the cache memory from an outside; a data transfer request prevention determination circuit configured to prevent, when a requested flag of an entry that holds the access request selected by the entry selection circuit indicates that the data transfer is requested by the data transfer request control circuit, and when the entry is different from an entry that is indicated by information held by the queue register, the data transfer request caused by the access request by the data transfer request control circuit, and a number count circuit configured to count, for each of a plurality of cache indexes each indicating the data storage location in the cache memory, a number of times that re-requests of the data transfer are issued by the data transfer request control circuit when the cache miss determination circuit determines that there is no data of the access request in the cache memory, when the data transfer request prevention determination circuit determines that the requested flag of the entry of the fetch port holding the access request indicates that the data transfer is requested, and when the entry matches an entry that is indicated by information held by the queue register, wherein the number count circuit distinguishes a case that the access request is a load instruction and a case that the access request is a store instruction, and number count circuit counts the number of times that the re-requests of the data transfer are issued on the load instruction and the store instruction respectively.