Patent ID: 8111184

Claim:
A digital-to-analog converting circuit comprising: a decoder selecting, responsive to an input digital signal, first and second voltages out of a reference voltage family including a plurality of reference voltages that differ from one another; and an interpolation circuit receiving the first and second voltages selected by the decoder and producing a voltage level obtained by interpolating the first and second voltages with a predetermined interpolate ratio; the plurality of reference voltages of the reference voltage family being grouped into first to (3S+1)th reference voltage groups, where S is one or a prescribed positive integer of a power of 2, an i-th reference voltage group, where i is an any one of 1 to (3S+1), including [3S×(j−1)+i]th reference voltages, where j=1, 2, . . . , h, h being a prescribed positive integer, the decoder including: first to (3S+1)th subdecoders provided respectively in correspondence with the first to (3S+1)th reference voltage groups, each of subdecoders being able to select one reference voltage out of the plurality of reference voltages of the corresponding reference voltage group in accordance with values of a first bit group of the input digital signal; and a (3S+1)-input and 2-output subdecoder selecting the first and second voltages out of reference voltages selected by the first to (3S+1)th subdecoders, in accordance with values of a second bit group of the input digital signal.