Patent ID: 8248139

Claim:
A clock generator, comprising: a first input/output terminal; a second input/output terminal; a reference voltage generator coupled to the first input/output terminal, and after being enabled by a master signal, operative to generate a reference voltage; a ramp generator coupled to the second input/output terminal and the reference voltage generator, and after being enabled by the master signal, operative to provide a ramp signal applied to the second input/output terminal and to generate a first clock depending on the ramp signal and the reference voltage; a comparator coupled to the first and second input/output terminals, comparing signals at the first and second input/output terminals to generate a comparison signal; a pulse generator coupled to the comparator, responsive to the comparison signal to generate a second clock; and a multiplexer coupled to the ramp generator and the pulse generator, responsive to the master signal to select one of the first and second clocks as an output signal.