Patent ID: 7564082

Claim:
A semiconductor structure, comprising: a gettering region formed proximate to a device region in a semiconductor material; the gettering region including an arrangement of a plurality of voids having a predetermined void-to-void spacing, wherein each void has a shape and size formed through a surface transformation process, and wherein the surface transformation process includes: forming holes or trenches with predetermined dimensions and spacing though a surface of the semiconductor material; annealing the semiconductor material to transform the holes or trenches through the surface of the semiconductor material into the arrangement of the voids with the predetermined void-to-void spacing, wherein the void-to-void spacing and the shape and size of each void is controlled by the predetermined dimensions and spacing of the holes or trenches, each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region; and a transistor formed using the device region, the transistor including a gate dielectric over the device region; a gate over the gate dielectric; and a first diffusion region and a second diffusion region formed in the device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.