Patent ID: 7443940

Claim:
A method for receiving a transmission of digital data in an elastic interface system, the method comprising the steps of: receiving a clock/data group on a bus resulting in a received clock/data group, wherein the received clock/data group includes: a clock signal, wherein the clock signal includes a plurality of clock edges; and a plurality of data bits, wherein the plurality of data bits includes even data beats, odd data beats, a latest data bit, and wherein corresponding bits of the clock signal and the plurality of data bits are launched onto the bus substantially simultaneously; delaying the plurality of data bits individually to center data windows with a nearest of the plurality of clock edges, to result in a plurality of de-skewed data bits; determining the latest data bit from the plurality of de-skewed data bits; if the latest data bit was delayed to center its data windows to a rising edge of the clock signal, loading even data beats into a plurality of even FIFO latches; and if the latest data bit was delayed to center its data windows to a falling edge of the clock signal: loading even data beats into a plurality of odd FIFO latches; and delaying the latest bit by a first delay time to result in a delayed, latest bit, wherein: the first delay time facilitates loading even data beats of the delayed, latest bit into even FIFO latches in response to the plurality of rising clock edges; and the first delay time is less than or equal to three bit times of the clock signal.