Patent ID: 8358165

Claim:
A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH), the voltage level shifting circuit comprising: a first and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor; a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS; and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current between the drains of the first PMOS transistor and the first NMOS transistor when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current between the drains of first PMOS transistor and the first NMOS transistor when the first signal transitions from the logic LOW to the logic HIGH.