Patent ID: 7493517

Claim:
A fault tolerant computer system, comprising: a plurality of computers, each computer including: at least one processor; a main memory; a sync controller for reading data from the main memory of a first computer in which the sync controller is disposed and transferring the read data to the sync controller disposed in a second computer, the sync controller of an active computer of the plurality of computers sequentially transferring data from the main memory of the active computer to a standby computer of the plurality of computers when the at least one processor issues a write instruction for the main memo during an operation synchronizing the standby computer in a non-operating state with the active computer in an operating state; a routing controller having a memory access monitor unit and a counter module for determining a state of a process of a read operation when data is read via the sync controller from the main memory, and an address comparator for comparing a counter value of the counter module with a write address during a writing operation when a write instruction is issued by the at least one processor the memory access monitor unit transferring only write data of an address for which a data read operation has already been completed and write data of an address for which a data read operation is being currently conducted in accordance with a result of a comparison conducted by the address comparator to the sync controller of the active computer system; and a bridge circuit for interconnecting and controlling the at least one processor, the main memory, the sync controller and the routing controller, wherein the plurality of computers are synchronized and each computer processes the same instruction string.