Patent ID: 7978188

Claim:
A data driving circuit including n channels, where n is an integer, the data driving circuit comprising: a shift register unit receiving data during a first input period and a second input period, the shift register unit shifting and outputting the received data; a first latch unit receiving the data input during the first input period from the shift register unit, and simultaneously or substantially simultaneously outputting the data corresponding to the first input period; and a second latch unit receiving the data input during the second input period from the shift register unit, and simultaneously or substantially simultaneously outputting the data corresponding to the second input period, wherein the shift register unit includes 2 n shift registers connected in series, and wherein among the plurality of 2 n shift registers, odd numbered ones of the shift registers receive a first clock signal through a first clock terminal thereof and receive a second clock signal through a second clock terminal thereof, and even numbered ones of the registers receive the second clock signal through a first clock terminal thereof and receive the first clock signal through a second clock terminal thereof.