Patent ID: 7131092

Claim:
A clock gating circuit having a modified schematic layout, the modified schematic layout being derived from the schematic layout of a D-type flip-flop having a first latch, a second latch, a V DD terminal, a data D terminal, a clock CK terminal, a reset R terminal, and an output Q terminal, the first latch comprising a first parallel-connected reset transistor and a first series-connected reset transistor, the second latch comprising a second parallel-connected reset transistor and a second series-connected reset transistor, the schematic layout of the D-type flip-flop being configured such that the reset R terminal is connected to the first parallel-connected reset transistor, first series-connected reset transistor, second parallel-connected reset transistor, and second series-connected reset transistor, wherein the modified schematic layout is derived from the schematic layout of the D-type flip-flop by removing the connection from the reset R terminal to the first parallel-connected reset transistor and first series-connected reset transistor and tying the first parallel-connected reset transistor and first series-connected reset transistor to the V DD terminal, wherein the modified schematic layout is effective to reduce a delay of a signal between the clock CK terminal and the output Q terminal.