Patent ID: 8223530

Claim:
A variable-resistance memory device comprising: (a) memory cells each having a current path including an access transistor and a data storage element connected to said access transistor in series, the data storage element storing a data in accordance with a resistance variation thereof caused by a voltage applied to said memory cell; (b) first wires each connected to a specific one of the two ends of said current path; (c)a second wire connected to the other one of said two ends of said current path; (d) a drive/control section configured to drive and control (1) a data write operation to write data into said memory cell by applying a write pulse between said first and second wires in order to cause a write cell current to flow through said memory cell, (2) a data erase operation to erase data from said memory cell by applying an erase pulse between said first and second wires in order to cause an erase cell current to flow through said memory cell, and (3) a direct verify operation to float said first wire right after said data write operation or right after said data erase operation in order to cause a read cell current to flow through said memory cell; and (e) a sense amplifier for sensing an electric-potential change generated on said first wire caused in said direct verify operation by taking a reference voltage, which is generated by said drive/control section in accordance with the operation voltage of said write or erase pulse, as a comparison reference.