Patent ID: 8316072

Claim:
A computer, comprising: a processor; a memory system; and a co-processing unit with an associated plurality of data registers for data exchange and used as working registers by said co-processing unit, wherein said computer is controlled to implement a method of increasing efficiency in executing a processing by said co-processing unit that uses data stored in said memory system in a standard format as matrix data, said standard format comprising one of a column major format and a row major format, said method comprising: for said data stored in said standard format in said memory system, using said processor to separate said data into blocks of data, each data block having a size p-by-q, where p and q are small integers such that said data will be loaded into said data registers in increments of said data blocks; and using said processor to rearrange and store said data blocks, thereby said data is stored in said memory system in a format different from said standard format, said different format providing a mechanism to place said data into said data registers in a predetermined desired format in view of an interface with said data registers that is disadvantageous for data in said standard format.