Patent ID: 6888772

Claim:
A non-volatile memory device, comprising: a plurality of memory cells, through each of said plurality of memory cells a pass current corresponding to a stored data flowing in a data reading operation; a plurality of bit lines, at least one of said plurality of bit lines being connected to a first voltage via a selected memory cell corresponding to a selected address among said plurality of memory cells in said data reading operation; a data line commonly provided to said plurality of bit lines for electrically coupling to said at least one of said plurality of bit lines in said data reading operation; a reference current supplying unit generating a reference current used for a comparison with said selected memory cell; a differential amplifier connected to a second voltage in said data reading operation for supplying a pass current to said data line, and for reading the stored data of said selected memory cell corresponding to a current difference between said pass current and said reference current generated by said reference current supplying unit; and a level adjusting circuit provided corresponding to said data line for changing a voltage level of said data line by capacitive coupling in said data reading operation.