Patent ID: 8037258

Claim:
A design structure embodied in a machine readable medium for a first memory module, the design structure comprising: a plurality of addressable data storage locations for storing data; a first interface for receiving data access commands for accessing data stored in addressable data storage locations on at least one memory module; and control logic which supports a plurality of modes of operation of said first memory module, including: a first mode of operation, wherein each said data access command accesses data storage locations on a single memory module and at least one bit of each said data access command designates a memory module accessed by the data access command, said control logic determining whether each received data access command accesses data storage locations in said first memory module, and responsive to determining that a received data access command accesses data storage locations in said first memory module, accessing the corresponding data storage locations in said first memory module; and a second mode of operation, wherein each data access command accesses data storage locations in a set of multiple memory modules, said set including said first memory module, each module of said set containing a respective portion of the data storage locations accessed by the data access command, said control logic responding to each received data access command by accessing the respective portion of the corresponding data storage locations accessed by the data access command contained in said first memory module; wherein, in said first mode of operation, a first set of components of said first memory module operate at a first clock frequency, and wherein, in said second mode of operation, said first set of components of said first memory module operate at a second clock frequency less than said first clock frequency.