Patent ID: 8850379

Claim:
A method of generating a layout of semiconductor components in conformance with a set of design rules, said method comprising: generating, for a unit cell comprising one or more semiconductor components, the one or more semiconductor components comprising a poly region and a corresponding oxide definition region, a plurality of configurations that each satisfy a first sub-set of the design rules, the first sub-set of the design rules comprising at least three of the design rules, the at least three design rules including a poly extension rule defining a limit with respect to an amount the poly region is allowed to project in a width direction of the unit cell beyond the corresponding oxide definition region, said generating being performed by a processor; determining one or more configurations of the plurality of configurations that comprise a proposed layout that also satisfies a second sub-set of the design rules, wherein the proposed layout is a repeating pattern of the unit cell, said second sub-set satisfaction determination being performed by the processor; determining a performance property value associated with a performance factor of the one or more configurations determined to also satisfy the second sub-set of the design rules, said performance property value determination being performed by the processor; and selecting a layout generation configuration for generating the layout of the semiconductor components, the layout generation configuration being one of the one or more configurations determined to also satisfy the second sub-set of the design rules, and the layout generation configuration being the configuration providing a maximum value of the determined performance property values associated with the performance factor.