Patent ID: 7075816

Claim:
An integrated circuit package comprising: a semiconductor die; a plurality of conductive elements arranged in an array, the array including at least a first set of spaced and electrically isolated conductive elements adjacent an outer lateral periphery of the integrated circuit package and at least one other set of spaced and electrically isolated conductive elements inwardly adjacent the at least a first set of conductive elements, the at least one other set of conductive elements being located outside a lateral periphery of the semiconductor die; a dielectric encapsulant formed over the semiconductor die and defining the outer lateral periphery of the integrated circuit package, the dielectric encapsulant extending at least partially laterally about the plurality of conductive elements and leaving an outer surface of each conductive element exposed; and a recess in the dielectric encapsulant between at least one conductive element of the at least a first set of conductive elements and at least one adjacent conductive element of the at least one other set of conductive elements.