Patent ID: 7378878

Claim:
A slew rate control circuit, comprising: a first driver transistor coupled between a first supply voltage and a first node; a second driver transistor coupled between a second supply voltage and the first node; a first programmable resistance block connected to the first supply voltage, the second supply voltage, and a gate of the first driver transistor, wherein the resistance of the first programmable resistance block is set by a first control signal; and a second programmable resistance block connected to the first supply voltage, the second supply voltage, and a gate of the second driver transistor, wherein the resistance of the second programmable resistance block is set by a second control signal, wherein a speed of a first transition of a signal at an output of the circuit from a first output voltage to a second output voltage is substantially determined by the resistance of the first programmable resistance block and a gate capacitance of the first driver transistor, wherein the first control signal and the second control signal are independent from an input signal for the first driver transistor and an input signal for the second driver transistor, and wherein a speed of a second transition of the signal at the output of the circuit from the second output voltage to the first output voltage is substantially determined by the resistance of the second programmable resistance block and a gate capacitance of the second driver transistor.