Patent ID: 7297602

Claim:
A ferroelectric transistor comprising: source and drain regions provided in a substrate; and a gate structure on the substrate between the source and drain regions, the gate structure comprising a conductive oxide layer overlying the substrate selected from the group of materials consisting of: an oxide of the formula AO x , where A is a material selected from the group consisting of Mo, W, Tc, Rh, Ir, Pd, In, Zn, Sn, Sr—Ru, Nd, Nb, Sm, La, V, and NaCl; a perovskite oxide of the formula ABO 3 , where A and B are a combination selected from the group consisting of (A=Ca, Sr)(B=V, Cr, Fe, Ru), (A=La)(B=Ti, Go, Ni, Cu), (A=H, Li, Na, K)(B=Re, Mo, Nb), and (A=La 1−x Sr x )(B=V, Mn, Co); a perovskite oxide of the formula A 2 B 2 O 7 , where A and B are a combination selected from the group consisting of (A=Bi, Pd)(B=Ru 1−x Bi x , Ru 1−x Pb x ); a layered perovskite oxide selected from the group consisting of CaTiO, Ba 2 RuO 4 , and (Sr(Ru, Ir, Cr)O 3 (SrO) N ; and a high temperature superconducting oxide selected from the group consisting of La 1−x Sr x CuO 4 , Nd 1−x Ce X CuO 4 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 Ca n−1 Cu n O 2n+4 , and (Nd 1−x Ce x ) 2 CuO 4 ; a ferroelectric material layer overlying the conductive oxide layer, and a top electrode conductive layer overlying the ferroelectric material layer.