Patent ID: 8138804

Claim:
A correlated double sampling (CDS) circuit for sampling a first pixel signal, transmitted via a first data line, and a second pixel signal, transmitted via a second data line, in a pixel array, the CDS circuit comprising: a first sampling circuit and a second sampling circuit; an amplifier circuit; and a control circuit for controlling the first sampling circuit to sample a first reset level and a first data level of the first pixel signal in a first sampling period, and for controlling the second sampling circuit to sample a second reset level and a second data level of the second pixel signal in a second sampling period, wherein the control circuit is further for controlling the amplifier circuit to output a first sampling reset level and a first sampling data level sampled by the first sampling circuit in a first output period, and to output a second sampling reset level and a second sampling data level sampled by the second sampling circuit in a second output period.