Patent ID: 7105453

Claim:
A method of forming contact holes for a memory device, comprising the steps of: providing a substrate having a memory array region and a peripheral circuit region, a plurality of gate structures formed overlying the array region and the peripheral circuit region, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer; forming a first insulating layer between the gate structures; forming a second insulating layer on the gate structures and the first insulating layer; successively etching the second and first insulating layers using the gate capping layers, the gate spacers, and the substrate as stop layers to form bit line contact holes on the memory array region to expose the substrate and the gate spacers and form substrate contact holes and gate contact holes on the peripheral circuit region to expose the substrate and the gate capping layers; forming a protective spacer over each sidewall of the bit line contact holes, the substrate contact holes, and the gate contact holes; etching the gate capping layer under each gate contact hole using the protective spacer as a stop layer to expose the gate; and removing the protective spacers.