Patent ID: 7376887

Claim:
A method for verifying hardware memory which includes a data section and an Error Correction Code (ECC) bit section, wherein an Error Correction Code is used for correcting single-bit or multi-bit errors, and wherein the ECC bits cannot be accessed directly for a read or write process, said method comprising the steps of: (a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving equation (1): E*X=C, (1) wherein: E is a known n×m ECC matrix, where n is the number of data bits and m is the number of check bits, X is a data pattern consisting of n bits fulfilling said equation (1), and C is a check bit string consisting of m bits, wherein all bits have the logical value of “1”; (b) generating a data pattern P 3 in accordance with equation (2) or (2′): b1)P3=XXOR P1 or (2) b2) P3 =X XOR P2, (2′) wherein P 1 and P 2 are arbitrary data patterns of the same bit length as said X data pattern; (c) writing said data pattern P 3 into the data section of said memory unit, thus generating respective ECC data; (d) testing said ECC memory section in an ECC test run by reading out the ECC data associated with said P 3 data patterns; (e) indicating an error, if said ECC procedure leads to an incorrect result.