Patent ID: 7969777

Claim:
A memory array comprising: at least one word line; at least one bit line; at least one third line; at least one thyristor having an anode, a cathode, and at least one base region, the anode being connected to one of the at least one word line, bit line and third line, the cathode being connected to another of the at least one word line, bit line, and third line, and the at least one base region being capacitively coupled to a remaining one of the at least one word line, bit line and third line; at least one word line controller; at least one bit line controller; at least one third line controller; wherein the anode and the cathode are at least at substantially the same voltage during standby; wherein the voltage during standby for the anode is provided from one of the at least one word line controller and the at least one bit line controller; and wherein the voltage during standby for the cathode is provided from a remaining one of the at least one word line controller and the at least one bit line controller.