Patent ID: 6838906

Claim:
An I/O buffer circuit having an input signal and an output signal, comprising: a pre-driver, consisting of PMOS and NMOS transistors; at least one post-driver, consisting of PMOS and NMOS transistors; a delay circuit for delaying the input signal with a delay time; and a logic circuit, at least including first, second, third and fourth NOT gates, one NAND gate and one NOR gate, the first NOT gate connected in series between the input signal and the PMOS transistor of the pre-driver, the second NOT gate connected in series between the input signal and the NMOS transistor of the pre-driver, the third NOT gate connected in series between the input signal with the delay time and the NAND gate and the fourth NOT gate connected in series between the input signal with the delay time and the NOR gate, the output of the NAND gate connected to the PMOS transistor of the post-driver and the output of the NOR gate connected to the NMOS transistor of the post-driver; where the combination of the delay circuit and the logic circuit turns off the post-driver after the pre-driver and the post-driver work for the delay time.