Patent ID: 8390636

Claim:
A computer-implemented graphics frame buffer process, comprising: establishing, on a computing device, a graphics frame buffer that is defined by an area of memory reserved for storing one or more frames of image data and that is accessible to be written to, but not read from, by an application process and to be read from, but not written to, by a graphics server process, and wherein the graphics frame buffer comprises a plurality of frame buffer segments; establishing, on the computing device, one or more frame buffer status values that are accessible to be read and written by the application process and the graphics server process, wherein the frame buffer status values represent a status of the frame buffer and are used to control access to the frame buffer, wherein the frame buffer status values comprise a plurality of single-bit flags, and wherein a first bit of the plurality of single-bit flags indicates that a frame is ready for reading by the graphics server process, and a second bit of the plurality of single-bit flags indicates a frame buffer segment from the plurality of frame buffer segments from which a next frame is to be read; controlling, based on the values, write access to the frame buffer by the application process and read access to the frame buffer by the graphics server process; generating, in response to an access to the frame buffer, a change to the; and reading frames from the frame buffer, by the graphics server process, wherein the values are used to control access by the graphics server process to read the frames.