Patent ID: 6841446

Claim:
A fabrication method for a flash memory device, comprising: providing a substrate, wherein the substrate is divided into a memory cell region and a peripheral circuit region; forming a first oxide layer on the substrate in the memory cell region and in the peripheral circuit region; forming a first conductive layer on the first oxide layer in the memory cell region and in the peripheral circuit region; defining the first conductive layer to form a plurality of floating gates in the memory cell region; forming sequentially a second oxide layer and a silicon nitride layer on the substrate in the memory cell region and in the peripheral circuit region; removing the first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region to expose the first oxide layer; forming a photoresist layer on the silicon nitride layer in the memory cell region; performing an ion implantation process on the substrate to form a doped region in the peripheral circuit region using the first oxide layer as a sacrificial oxide layer; removing the sacrificial oxide layer; removing the photoresist layer; forming a third oxide layer on the substrate in the memory cell region and in the peripheral circuit region, wherein the third oxide layer is formed by performing a wet rapid thermal oxidation (wet RTO) having pre-mixed H 2 and O 2 for generating oxygen radicals that react with the silicon nitride layer in the memory cell region and the substrate in the peripheral circuit region to form the third oxide layer; forming a second conductive layer on the substrate; and defining the second conductive layer to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.