Patent ID: 7636803

Claim:
A method comprising: receiving a first access clock at a first clock domain to provide periodic first First In First Out memory (FIFO) access cycles at a first frequency, wherein a FIFO access cycle is a portion of a signal comprising one or more transitions for controlling an access to a FIFO; generating a first access signal comprising available first FIFO access cycles corresponding to at least a portion of the periodic first FIFO access cycles, the available first FIFO access cycles having a first frequency that is the same frequency as the periodic first FIFO access cycles; receiving a second access clock at a second clock domain to provide periodic second FIFO access cycles at a second frequency; generating a second access signal comprising available second FIFO access cycles corresponding to at least a portion of the periodic second FIFO access cycles, the available second FIFO access cycles having the same frequency as the periodic second FIFO access cycles; transferring data from the first clock domain to the second clock domain through the FIFO in response to a number of the available first FIFO access cycles and a number of the available second FIFO access cycles; and determining, in response to a fullness of the FIFO being outside a desired range, that a difference has occurred between the number of available first FIFO access cycles transferring the data and the number of available second FIFO access cycles transferring the data; and modifying generation of the first access signal, without changing the frequency of the first or second periodic FIFO access cycles, by subtracting a periodic first FIFO access cycle from the available first FIFO access cycles in response to the difference indicating a greater number of available first FIFO access cycles.