Patent ID: 7532039

Claim:
A clock signal detector, comprising: a first flip-flop, comprising an input end, and coupled to a first clock generator; a second flip-flop, comprising an input end, coupled to a first signal delayer, and further coupled to said first clock generator through said first signal delayer; a third flip-flop, comprising an input end, coupled to a second signal delayer, and further coupled to said first clock generator through said second signal delayer; a fourth flip-flop, comprising a clock input end, coupled to a third delayer, and further coupled to a second clock generator through said third signal delayer; and a fifth flip-flop, comprising a clock input end, coupled to a fourth signal delayer, and further coupled to said second clock generator through said fourth signal delayer; wherein, said clock input ends of said first flip-flop, said second flip-flop and said third flip-flop are respectively coupled to said second clock generator, said input ends of said fourth flip-flop and fifth flip-flop are respectively coupled to said first clock generator, and a detecting signal outputted from the output ends of each of said flip-flops.