Patent ID: 7649583

Claim:
A method for fabricating a semiconductor structure, comprising: forming a semiconductor layer on a substrate, the semiconductor layer disposed in an active element area and a storage capacitor area of the substrate; forming a first inter-layer dielectric layer to cover the semiconductor layer; forming a gate on the first inter-layer dielectric layer in the active element area and a first electrode on the first inter-layer dielectric layer in a storage capacitor area; performing a doping process to form a source and a drain in the semiconductor layer in the active element area, and a channel is between the source and the drain; forming a second inter-layer dielectric layer to cover the gate and the first electrode; forming a patterned conductive layer on the second inter-layer dielectric layer as a pixel electrode; forming a third inter-layer dielectric layer to cover the patterned conductive layer; patterning the third inter-layer dielectric layer to expose the patterned conductive layer and forming a plurality of contact windows in the first, second and third inter-layer dielectric layers to expose the source, the drain, a portion of the patterned conductive layer and the first electrode; and forming a second electrode on the third inter-layer dielectric layer disposed over the first electrode and electrically connected to the first electrode, and a source/drain conductive line electrically connecting the semiconductor layer with the patterned conductive layer.