Patent ID: 7349264

Claim:
A method of operating an array of memory cells connected along word lines and bit lines, comprising: selecting a multi-state memory cell for a sensing operation; discharging a sensing node of the selected memory cell to ground through the bit line along which it is connected; subsequent to discharging the sensing node of the selected memory cell: applying a first voltage level to the source of the selected memory cell; and applying a second voltage level to the word line along which the selected memory cell is connected, wherein the first and second voltage levels are independent of the data content stored within the selected cell; subsequent to applying the first and second voltage levels, allowing a corresponding voltage to develop upon the bit line along which the selected memory cell is connected; performing a first sensing operation, including comparing the voltage developed at the sensing node of the selected memory cell to a first plurality of reference values in order to determine whether the data content of the selected memory cell corresponds to one of a first subset of said multi-states; subsequent to performing the first sensing operation, applying a third voltage level to the word line along which the selected memory cell is connected, wherein the second and third voltage levels are distinct; subsequent to applying the third voltage level, allowing a corresponding voltage to develop upon the bit line along which the selected memory cell is connected; and performing a second sensing operation, including comparing the voltage developed at the sensing node of the selected memory cell to a second plurality of reference values in order to determine whether the data content of the selected memory cell corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.