Patent ID: 6881597

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a bonding pad and an extraction electrode each comprised of an uppermost layer wiring in a product circuit region; (b) forming a protection film on an upper layer of said uppermost layer wiring; and (c) partially exposing a surface of said bonding pad by removing a predetermined part of said protection film, wherein said uppermost layer wiring is formed by depositing a conductive body and then patterning by a lithography method, a plurality of logic circuits provided with said extraction electrode are formed in said product circuit region, and after partially exposing the surface of said extraction electrode by removing said protection film on said extraction electrode, a probe having a tip radius of curvature of about 0.05 μm to 0.8 μm is contacted to said extraction electrode, and then logic values of said logic circuits are evaluated.