Patent ID: 7371629

Claim:
A method of creating an integrated circuit device comprising: providing a substrate wherein said substrate comprises isolation regions and active regions; forming a transistor on said active regions, said transistor is comprised of a silicide region over a gate electrode and silicide regions over heavily doped source/drain regions; forming a silicon nitride layer on said transistor and isolation regions with a PECVD technique; depositing a dielectric layer on said silicon nitride; forming one or more contact holes in said dielectric layer and in said nitride layer; and filling said holes with a metal layer to further define said transistor, wherein the channel length between said source/drain regions is less than about 1 micron wherein said transistor is an NMOS transistor, and said silicon nitride is hydrogen rich and deposited with a gas mixture comprised of a SiH4 silicon source gas and NH3 and N2 as nitride source gases.