Patent ID: 7248194

Claim:
Bit-detection arrangement able to convert an analog signal (AS) having an amplitude into a digital signal (DS) representing a bit sequence from which the analog signal (AS) is derived, comprising: a quantizer ( 11 ) able to produce an output signal S 1 by quantizing the amplitude of the analog signal (AS), and a phase detector PD 1 ( 12 ) able to determine a phase difference ΔP 1 between the output signal S 1 and a clock signal C 2 , and able to generate an output signal PH 2 having an amplitude, where the amplitude of PH 2 indicates the phase difference ΔP 1 , an analog to digital converter ADC ( 13 ) which is able to output a processed signal (PrS) by sampling the output signal PH 2 at a sample rate controlled by a clock signal C 1 having a frequency which is equal to the frequency of clock signal C 2 divided by a factor n, a digital phase locked loop DPLL ( 2 ) able to lock on the processed signal (PrS) and able to output a phase signal PH 1 using the clock signal C 1 , and a bit decision unit ( 3 ) able to output the digital signal (DS) and a clock signal C 3 using the phase signal PH 1 , the clock signal C 1 and the output signal S 1 , comprising a sample and hold unit SH 1 able to sample the output signal S 1 , using a clock signal C SH 1 having a frequency equal to the frequency of clock signal C 2 , and to hold n samples, sample y=1 through sample y=n , of-the output signal S 1 for a clock period of clock signal C 1 , n being the division factor of clock signal C 2 , where n is an integer greater than one, characterized in that the bit decision unit further comprises at least one additional sample and hold unit SH 2 able to sample the output signal S 1 , using a clock signal C SH2 and wherein the frequency of the clock signal C SH2 is equal to the frequency of clock signal C SH1 and the phase of clock signal C SH2 is substantially different from the phase of clock signal C SH1 , and an output unit for outputting samples of either the sample and hold units SH 1 or SH 2 , wherein the samples of the sample and hold unit SH 1 are outputted when the phase signal PH 1 indicates that the phase difference ΔP 1 is in a first region and the samples of the additional sample and hold unit SH 2 are outputted when the phase signal PH 1 indicates that the phase difference ΔP 1 is in a second region.