Patent ID: 6920552

Claim:
A network device comprising: a device input; at least one port; a frequency doubler coupled to said input and configured to receive an input clock signal and output an output clock signal having double the frequency of the input clock signal; a data I/O device and configured to output data based upon a reference clock signal; and a programmable delay locked loop coupled to said device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal; wherein an external clock signal received at said device input is input to said frequency doubler as the input clock signal, said output of said frequency doubler being applied to said data I/O device as a reference clock, said data being output from said data I/O device to said at least one port, said external clock signal being input to said programmable delay locked loop, said programmable delay locked loop outputting an output clock signal having a frequency equal to a frequency of the external clock signal, said output clock signal being in synchronization with said doubled clock signal.