Patent ID: 8120174

Claim:
A semiconductor device comprising: a wiring board having a first surface and a second surface opposite the first surface; a semiconductor chip mounted over the first surface of the wiring board having an obverse surface, a reverse surface opposite the obverse surface, and a plurality of pads formed on the obverse surface thereof; and a sealing body sealing parts of the first surface of the wiring board and the semiconductor chip, wherein the wiring board includes: a plurality of electrodes which are electrically connected with the plurality of pads of the semiconductor chip respectively and formed at the first surface of the wiring board; a plurality of first lands which are electrically connected with the plurality of electrodes respectively and formed at the first surface of the wiring board; a plurality of second lands which are electrically connected with the plurality of first lands respectively and formed at the second surface of the wiring board; a plurality of vias which are disposed between the plurality of first and second lands respectively and electrically connected with the plurality of first and second lands; a solder resist layer formed on the second surface of the wiring board; and a plurality of openings which are formed at the solder resist layer, wherein the plurality of second lands are disposed in the plurality of openings respectively and top and side surfaces of the plurality of second lands are exposed from the solder resist.