Patent ID: 8030965

Claim:
A level shifter configured to receive an input signal having a level set to one from among a first lower voltage and a first upper voltage which form a voltage pair, and to level-shift the input signal thus received so as to output an output signal having a level set to one from among a second lower voltage and a second upper voltage which form a voltage pair, the level shifter comprising: an SR flip-flop configured to generate an output signal which is switched to the second upper voltage upon receiving a positive edge of a signal via a set terminal thereof, and which is switched to the second lower voltage upon receiving a positive edge of a signal via a reset terminal thereof; a first logical gate configured to generate the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, and to output the logical AND thus generated to the set terminal of the SR flip-flop; and a second logical gate configured to generate the logical NOR of the feedback signal and the input signal, and to output the logical NOR thus generated to the reset terminal of the SR flip-flop.