Patent ID: 7295482

Claim:
A semiconductor memory device with a folded bit line structure, which is operative by an input of a supply voltage and a ground voltage, comprising: a first cell array for applying a data signal onto a first bit line or a first bit line bar; a first reference cell block for applying a reference signal onto the first bit line bar when the data signal is inputted onto the first bit line, or the reference signal onto the first bit line when the data signal is inputted onto the first bit line bar; a second cell array for applying the data signal onto a second bit line or a second bit line bar; a second reference cell block for applying the reference signal onto the second bit line when the data signal is inputted onto the second bit line, or the reference signal onto the second bit line bar when the data signal is inputted onto the second bit line bar; and a bit line sense amp for sensing and amplifying a difference of the data signals applied onto one pair of bit lines that are connected to the sense amp, out of a pair of the first bit lines or a pair of the second bit lines, wherein each bit line maintains a floating state without an input of a separate pre-charge voltage upon a pre-charge operation, and the other pair of the bit lines that are not connected to the sense amp are pre-charged with the reference signal by the corresponding reference cell block.