Patent ID: 7237055

Claim:
A silo routing circuit formed upon a semiconductor substrate to route data among a number of reconfigurable computational elements, the silo routing circuit comprising: a plurality of input terminals and a plurality of output terminals, said plurality of input terminals including an input terminal and said plurality of output terminals including a first output terminal and a second output terminal; a multi-stage interconnection network (“MIN”) of a plurality of switches configurable to form data paths from any of said plurality of input terminals to any of said plurality of output terminals; and a subset of a plurality of configuration data terminals configured to select a selected subset of switches to form one path of said data paths from said input terminal to either said first output terminal or to said second output terminal, said second output terminal being at a distance from said first output terminal, said distance being defined by a bit vector applied to said subset of configuration data terminals said distance being a displacement in a quantity of output terminals from said first output terminal, each input terminal from said plurality of input terminals and each output terminal from said plurality of output terminals are uniquely identified as consecutive numbers from input zero (“P. 0 ”) to input “N” (“P.N”) and from output zero (“Q.0”) to output “N” (“Q.N”), respectively each input terminal from said plurality of input terminals and each output terminal from said plurality of output terminals are similarly numbered from a row of switches from said plurality of switches, each switch of said row of switches being a binary switch having at least a first input configured to receive data from said row of switches and a second input configured to receive data from another row of switches located 2 M−k rows from said row of switches.