Patent ID: 7328383

Claim:
A method for testing an embedded phase-locked loop (PLL) circuit comprising steps of: Providing a first clock signal to an embedded phase-locked loop (PLL) circuit to be tested; Generating a PLL clock signal of a first frequency by said embedded PLL in response to said first clock signal; Sampling said PLL clock signal of said first frequency with a second clock signal of a second frequency to generate a first sampled signal, wherein said second frequency is different from said first frequency but has a first correlation with said first frequency so that said first sampled signal toggles at a predetermined frequency when said embedded PLL circuit is in a normal operation condition; Sampling said first sampled signal to generate a second sampled signal with said second clock signal of said second frequency; Logically operating said second sample signal with said first sampled signal to generate an indication signal; and Determining said embedded PLL circuit is in an abnormal operation condition when said indication signal is at a first logic level while determining said embedded PLL circuit is in a normal operation condition when said indication signal is at a second level.