Patent ID: 7710812

Claim:
A semiconductor memory device comprising: a plurality of memory cells storing data that is readable without data destruction; a plurality of word lines connected to gates of the plural memory cells; n bit lines connected to the memory cells, where n is an integer equal to or greater than 2; a plurality of sense amplifiers connected to the bit lines, respectively, and sensing the data stored in the memory cells; refresh cells provided to correspond to the word lines, respectively, and provided to correspond to k bit lines, where k is a natural number smaller than n, one of the refresh cells storing therein refresh data indicating whether to perform a refresh operation on k memory cells out of the plural memory cells connected to a corresponding word line out of the plural word lines and connected to the k bit lines, respectively; a refresh sense amplifier reading the refresh data; and a refresh selection part provided to correspond to the refresh sense amplifier, and selecting whether to perform the refresh operation on the k memory cells according to the refresh data read by the refresh sense amplifier.