Patent ID: 7005708

Claim:
An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, said MOS transistor formed in an I/O periphery of an integrated circuit (IC) for providing ESD protection for said IC, said MOS transistor comprising: a P-substrate; a Pwell disposed over said P-substrate; said plurality of interleaved fingers each comprising: an N+ source region; an N+ drain region; and a gate region formed over a channel region disposed between said source and drain regions, wherein each source and drain comprise a row of contacts respectively formed in a row of contact holes that is shared by an adjacent finger, wherein each contact hole in each said contact row has a distance to said gate region defined under minimum design rules for core functional elements of said IC and having active-area segmentation interleaved between said contacts in each said row of contacts; and wherein said Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of said MOS transistor during an ESD event.