Patent ID: 7998787

Claim:
A method of fabricating an array substrate, comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming source and drain electrodes comprising first source and drain layers on the gate insulating layer, respectively, and second source and drain layers on the source and drain layers, respectively, and spaced apart from each other, wherein at least one of the second source and drain layers comprises indium-tin-oxide doped with at least one Group III element; forming an organic semiconductor layer on the gate insulating layer and contacting the second source and drain layers; and forming a data line connected to the source electrode, wherein the at least one Group III element includes boron (B), wherein the first source and drain layers have a resistance lower than a resistance of the second source and drain layers, wherein the second source and drain layers fully cover the first source and drain layers, respectively, wherein a top surface of the gate insulating layer is even, whereby the source and drain electrodes and the data line directly on the gate insulating layer are even, wherein the data line consists of a layer made of the same material as the first source and drain layers, and wherein a heat-treating step is conducted prior to forming the organic semiconductor layer such that surfaces of the second source and drain layers are smoothed, and a temperature of the heat-treating is equal to or less than 200 degrees centigrade.