Patent ID: 8598661

Claim:
A MOSFET semiconductor device comprising: a plurality of raised gate pillars formed on a substrate, the gate pillars including a gate oxide layer formed on the substrate and a gate layer formed on the gate oxide layer, the gate pillars having vertical sidewalls; offset vertical sidewall spacers that are provided above the gate oxide layer, the offset vertical sidewall spacers having undersides abutting the gate oxide layer, wherein the offset vertical sidewall spacers are covering the vertical sidewalls of the gate pillars; doped epitaxial silicon source and drain regions formed between the gates in the substrate; a pre-metal dielectric layer formed on the substrate between the raised gates and covering the substrate; and conductive contacts formed on the source and drain regions; wherein lateral side portions of the gate pillars are embedded in the source and drain regions and underside of the gate oxide layer below the gate layer and the offset vertical sidewall spacers has a flat surface profile, and correspondingly the undersides of the offset vertical sidewall spacers abutting the gate oxide layer have a flat surface profile, wherein the epitaxial silicon source and drain regions are substantially free of voids beneath the gate oxide layer.