Patent ID: 7805576

Claim:
An information processing system, comprising: one or more processors prejudice cache memory including a cache tag including a plurality of ways and a cache data area, executing an externally received instruction, and processing data; and a processor control device transmitting a reply to the processors at a read request from the processors, including a snoop tag as tag information corresponding to the cache tag of the processor, and including a number of ways of the snoop tag larger than a number of ways of the cache tag of the processor, wherein if a cache miss occurs in the processors, if there is a data read request from the processor to the processor control device, and if there is an available way of the snoop tag, then the processor control device updates the available way according to address information as a target of the read request, and transmits the data corresponding to the address information to the processors, wherein when the available way is updated, the processor control device does not issue to the processor a request to delete arbitrarily address information from a way storing the arbitrarily address information in the ways of the cache tag.