Patent ID: 7233471

Claim:
An integrated circuit (IC) output stage protection system, comprising: a first NMOS device, having a gate configured to be coupled to an output of an IC logic core and a source coupled to a current source; a second NMOS device, having a source coupled to a drain of said first NMOS device and a gate coupled to a biasing circuit that biases said second NMOS device so that said-first NMOS device operates in a saturation region; and one or more diodes coupled between an output node and a gate of a third NMOS device, having a source coupled to a drain of said second NMOS device and a drain coupled to said output node, wherein said one or more diodes substantially protect said NMOS devices so that they operate within a device voltage rating; wherein an operating voltage of said first NMOS device is lower than an operating voltage of said second NMOS device, and wherein said operating voltage of said first NMOS device is lower than an operating voltage of said third NMOS device.