Patent ID: 7244986

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a first diffusion region and a second diffusion region arranged in parallel on a surface of said semiconductor substrate; a first storage node adjacent to said first diffusion region; a second storage node adjacent to said second diffusion region; a first gate electrode on said first storage node; a second gate electrode on said second storage node; a first insulating film provided between said first gate electrode and said substrate; a second insulating film provided between said second gate electrode and said substrate; a third insulating film provided between said first storage node and said second storage node; a third gate electrode on said third insulating film; an insulating region provided on said third gate electrode; and a fourth insulating film provided between said first insulating film and part of said first gate electrode and between said second insulating film and part of said second gate electrode, wherein said first and second diffusion regions, said first and second storage nodes, said first and second gate electrodes, said insulating region and said third gate electrode constitute a cell for storing two bits of information; wherein said first and second gate electrodes are connected in common on said insulating region to constitute a word line electrode, and wherein said first and said second diffusion regions are formed by self-alignment.