Patent ID: 6949966

Claim:
A DLL circuit comprising: an output dummy circuit having a prescribed propagation delay; a first delay element for delaying a reference clock in accordance with a control signal and supplying a delayed signal to said output dummy circuit; a phase determination circuit for comparing the phases of said reference clock and a feedback signal that is supplied from said output dummy circuit, and based on the result of this comparison, supplying said control signal for changing the delay amount of said first delay element; a second delay element for receiving, one of said reference clock and said feedback signal, as a first signal that serves as the trigger for a phase comparison operation, and for delaying the first signal by a prescribed delay amount; a first latch circuit for latching the value of the other of said reference clock and feedback signal as a second signal that does not serve as the trigger of said phase comparison operation in synchronization with the rising edge of the output signal of said second delay element; an inverter circuit for inverting the logic output of said first latch circuit; and a second latch circuit for, during intervals in which the output signal of said inverter circuit is a logic output that indicates that said reference clock and said feedback signal are in the same phase, supplying the output of said phase determination circuit without alteration as a determination result; when the output signal of said inverter circuit becomes the other logic output that indicates that said reference clock and said feedback signal are in opposite phases, holding the value of the output signal of said phase determination circuit at that time; and, during intervals in which the output signal of said inverter circuit is said other logic output, maintaining and supplying this held value as the determination result.