Patent ID: 7838924

Claim:
An integrated circuit formed at a semiconductor surface of a substrate comprising a p-layer, comprising: functional circuitry formed on said p-layer and having a plurality of terminals; at least one ESD protection cell connected to at least one of said plurality of terminals of said functional circuitry, said protection cell comprising: an Nwell formed in said p-layer, a p-doped region within said Nwell defining with said Nwell an Nwell diode comprising an anode and a cathode; a DeNMOS transistor formed in or on said p-layer comprising an n+ source, an n+ drain formed within said Nwell and a channel region comprising said Nwell and a p-type conductivity region between said source and said drain, and a gate electrode on a gate dielectric on said channel region; wherein said at least one of said terminals of said functional circuitry is coupled to said p-doped region defining said Nwell diode and said Nwell diode is connected in series with a current path from said drain to said source of said DeNMOS transistor.