Patent ID: 7302622

Claim:
An integrated memory having a test circuit for functional testing of the memory, comprising: a plurality of memory banks, each memory bank being independently accessible; a plurality of secondary sense amplifiers for evaluation and amplification of data signals from an assigned memory bank, each secondary sense amplifier being assigned to a different one of the memory banks; read/write data lines connected to respective secondary sense amplifiers to connect the respective secondary sense amplifiers to a data output circuit of the memory, one of the read/write data lines being connected to at least two of the plurality of secondary sense amplifiers; a data generator for generating read comparison data, the data generator being connected to the read/write data lines in order to distribute the read comparison data to the memory banks for the functional testing thereof; a plurality of comparison circuits for comparison of data read from the assigned memory bank with the read comparison data, each comparison circuit being assigned to a different one of the memory banks, each comparison circuit having a respective first input, second input, and output, wherein an output signal is adapted to be tapped off depending on a result of a data comparison at the first and second inputs, the respective first input being connected to the secondary sense amplifier without interposition of the read/write data lines, the respective second input being connected to the read/write data lines to receive the read comparison data supplied by the data generator.