Patent ID: 7062344

Claim:
A fabricating method comprising the steps of: processing semiconductor wafers by a plurality of processing apparatuses each including at least one processing chamber and an interface having transporting means for transporting a semiconductor wafer to be processed into said processing chamber and for sending out a processed semiconductor wafer; and transporting semiconductor wafers from one of the processing apparatuses to another by an inter-apparatus transporter; wherein, in each of said plurality of processing apparatuses, semiconductor wafers are set at said interface by said inter-apparatus transporter, transported into said processing chamber by said transporting means, processed in said processing chamber, and transported out of said processing chamber by said transporting means; and wherein a time interval assigned for transporting the semiconductor wafers from one of said processing apparatuses to another by said inter-apparatus transporter and assigned for processing in each of said processing apparatuses including time for transporting a semiconductor wafer to be processed into said processing chamber at said interface, time for processing the semiconductor wafer in said processing chamber, and time for transporting the semiconductor wafer out of said processing chamber and sending out at said interface is set to N multiplication of a predetermined unit time, with N being a positive integer, that is common to all of said plurality of the processing apparatuses and the inter-apparatus transporter and that is longer than the shortest required time for either processing in each of the processing apparatuses or for transporting by the inter-apparatus transporter but shorter than the longest required time for either processing in each of the processing apparatuses or for transporting by the inter-apparatus transporter.