Patent ID: 8207535

Claim:
A thin film transistor substrate comprising: a gate wire and a data wire formed to cross each other on an insulating substrate and define a pixel area; a thin film transistor formed on the intersection of the gate wire and the data wire, the thin film transistor including: a gate electrode on the insulating substrate; a gate insulating layer over the gate electrode; a semiconductor layer on the gate insulating layer; and a source electrode and a drain electrode on the semiconductor layer; an inorganic insulating layer covering the thin film transistor and having a lower surface and an upper surface, the lower surface being flat and the upper surface being formed in a prominence and depression pattern; a reflective layer provided on the inorganic insulating layer, the reflective layer being contacted with the prominence and depression pattern of the upper surface of the inorganic insulating layer; and a pixel electrode on the reflective layer in the pixel area to be contacted with the drain electrode of the thin film transistor through a contact hole formed in the inorganic insulating layer, the pixel electrode being formed in the prominence and depression pattern, wherein the lower surface of the pixel electrode is contacted with the upper surface of the reflective layer, and wherein the inorganic insulating layer is formed with a mask including a blocking part, a semi-transmitting part having a plurality of slit parts and a transmitting part, the ratio of the width of the blocking part to the width of the semi-transmitting part is 3:4, and a gap between the slits is different at both sides of the center of the semi-transmitting part, and wherein the prominence and depression pattern of the upper surface of the inorganic insulating layer have a shape defined by the blocking part and the slit parts.