Patent ID: 7373475

Claim:
A method for allocating data structures to memory units in a network processor unit (NPU) packet processing environment, comprising: storing data identifying an available capacity, available bandwidth, and memory latency for each memory unit; storing data identifying a size and bandwidth usage for each data structure; performing an iterative algorithm via execution of software on a computer system, the iterative algorithm iterating over the data structures to allocate the data structures to the memory units by, retrieving the data stored for each memory unit and each data structure; attempting to allocate data structures to memory units with lower latency; and if insufficient capacity or bandwidth is available, allocating a data structure to a memory unit with a higher latency that has sufficient available capacity and bandwidth; employing a simulator to determine a packet throughput rate of a first allocation of data structures to memory units in a simulated NPU packet processing environment; generating a second allocation of data structures to memory units, the second allocation including reallocation of at least one data structure to a lower latency memory unit; employing the simulator to determine a packet throughput rate of the second allocation of data structures to memory units; and determining which of the first and second allocations provides a high packet throughput rate.