Patent ID: 8212320

Claim:
A high voltage tolerant ESD clamp comprising, an n+ region defining an anode, wherein the anode is formed in a p-region or n-region, an n+ region defining a cathode that is laterally separated from the anode, wherein cathode is formed directly in a p-region or n-region, a plurality of blocking regions in the form of multiple n-well regions or n-buried layer regions formed between the p-region in which the anode is formed and the p-region in which the cathode is formed, or in the form of multiple p-well regions or p-buried layer regions formed between the n-region in which the anode is formed and the n-region in which the cathode is formed, and an oxide isolation region formed below the n-well regions or n-buried layer regions and the p-regions in which the anode and cathode are formed, or below the p-well regions or p-buried layer regions and the n-regions in which the anode and cathode are formed, wherein the blocking regions do not include any gates formed over blocking regions and the blocking regions do not include any n+ regions or p+ regions formed in the relatively lower doped blocking regions.