Patent ID: 7725750

Claim:
A method of transitioning between an active mode and a power-down mode in a processor-based system through one or more intermediate states, the method comprising: saving a state of the active mode, including saving the state of a set of first registers of the processor-based system, and saving the state of a set of read-only registers of the processor-based system; detecting occurrence of one or more interrupt events during a transition between the active mode and the power-down mode; responding to a first set of interrupt events from amongst the one or more interrupt events, wherein the first set of interrupt events occur during the transition from the active mode to the one or more intermediate states; and restoring the state of the set of read only registers, wherein said restoring the state of the set of read-only registers comprises implementing a priority scheme for a status-event write operation and a software-restore write operation, and wherein the priority scheme is based on a functionality of the set of read-only registers.