Patent ID: 8750391

Claim:
A differential signal output device comprising: a first transmitting terminal and a second transmitting terminal that superimpose a differential signal and a common mode signal and output the superimposed signals; a differential signal generating circuit that generates the differential signal in response to a data signal and outputs the differential signal to the first transmitting terminal and the second transmitting terminal; and a common mode signal generating circuit that generates the common mode signal in response to a clock signal, outputs the common mode signal to the first transmitting terminal and the second transmitting terminal, and controls a slew rate of the common mode signal in response to a control signal, wherein the common mode signal generating circuit comprises: a first MOS transistor having a first end connected to a ground via a first current source, and having a gate receiving the clock signal; a second MOS transistor having a first end connected to the ground via a second current source, and having a gate receiving the clock signal; a third MOS transistor having a first end connected to a second end of the first MOS transistor, and having a second end connected to the first transmitting terminal; a fourth MOS transistor having a first end connected to the second end of the second MOS transistor, and having a second end connected to the second transmitting terminal; a first capacitance adjusting circuit that is connected between the first end of the third MOS transistor and the ground and has an electric capacitance adjustable in response to the control signal; and a second capacitance adjusting circuit that is connected between the first end of the fourth MOS transistor and the ground and has an electric capacitance adjustable in response to the control signal.