Patent ID: 8386712

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: an apparatus comprising: a computer system central processor and layered memory coupled to and accessible by the central processor, the layered memory including a level one cache; control logic circuitry associated with said level one cache which controls the selective storing in interchangeable locations of the level one cache of the layered memory both standard cache lines and trace lines; said control logic circuitry partitioning an instruction address presented to the level one cache; indexing the instruction address into a tag array of the level one cache; and comparing the instruction address with the tag array a first time to determine whether a match is found; and if the match is found on the first comparison, then determining whether the match is a trace line; upon determining that the match is the trace line: checking a trace length parameter in a tag associated with the trace line to determine the number of partitions required to access the trace, accessing only the required partitions, and forwarding at least one instruction associated with the required partitions for execution by the central processor; if no match is found during the first comparison: comparing the instruction address with a portion of the tag array within a selected congruence class to determine whether a different match is found, if the different match is found, determining whether the different match is associated with a second trace line, and if so, the second trace line is not transmitted to the central processor for execution.