Patent ID: 8120180

Claim:
A semiconductor device, comprising: a semiconductor substrate; an insulation pattern over the semiconductor substrate, and an etch stop layer over the insulation pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the semiconductor substrate; a first plug filled in a lower portion of the contact hole; a diffusion barrier layer formed over the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole; a second plug formed over the diffusion barrier layer and filled in the contact hole; a storage node coupled to and formed over the second plug, wherein the insulation pattern further comprises: a first insulation layer having a first sub-contact hole filled by the first plug; and a second insulation layer having a second sub-contact hole in which the diffusion barrier layer and the second plug are formed, wherein the second sub-contact hole is formed in the second insulation layer and the etch stop layer.