Patent ID: 8871604

Claim:
A method of manufacturing a semiconductor device, the method comprising: providing a workpiece; forming a trench in the workpiece; forming a bottom electrode over the trench; forming a dielectric layer over the workpiece and the bottom electrode, wherein top portions of the bottom electrode on sidewalls of the trench are substantially co-planar with a top surface of the workpiece when the dielectric layer is formed over the workpiece; forming a top electrode layer over the dielectric layer; forming a cap layer over the top electrode layer, wherein the cap layer comprises a dielectric material, and wherein at least one of a width of the trench, a thickness of the bottom electrode, a thickness of the dielectric layer, a thickness of the top electrode layer, and a thickness of the cap layer is optimized so that the cap layer completely covers the top electrode layer, using Equation 1, Equation 2, or Equation 5: w< 2×( a+b+c ); Eq. 1 w> 2×( a+b+c+d ); or Eq. 2 w< 2×( a+b+c+d ); Eq. 5 wherein w is the width of an opening of the trench proximate the top surface of the workpiece, a is the thickness of the bottom electrode, b is the thickness of the dielectric layer, c is the thickness of the top electrode layer, and d is the thickness of the cap layer; and patterning the cap layer, the top electrode layer, and the dielectric layer using a photoresist mask, wherein the patterned top electrode layer, the patterned dielectric layer, and the bottom electrode form a capacitor.