Patent ID: 7692945

Claim:
A memory system, comprising: a primary memory; and a secondary memory coupled to the primary memory; and a set of external conductor elements for connecting to at least one of the primary memory and the secondary memory; wherein: each of the primary memory and the secondary memory comprises a receiving port and a transmitting port, the transmitting port having a first predetermined number of contacts for transferring signals and the receiving port having a second predetermined number of contacts for transferring signals, the memory system further comprising: a wiring subsystem comprising a set of conductors configured to connect only one of the receiving port contacts and the transmitting port contacts to a subset of the external conductor elements such that only one of the transmitting port and the receiving port is connected to the subset of the external conductor elements, the one of the transmitting port and receiving port connected to the external conductor elements being used and the other of the transmitting port and receiving port being unused, wherein: the sum of the first predetermined number of contacts and the second predetermined number of contacts is greater than a number of external conductor elements in the subset of the external conductor elements; and the memory system is configurable to have one of a first configuration and a second configuration, wherein, in the first configuration. the set of conductors of the wiring subsystem connects the transmitting port contacts to the subset of external conductor elements, and the receiving port contacts are unused such that the receiving port contacts are not connected to any of the external conductor elements, and wherein, in the second configuration, the set of conductors of the wiring subsystem connects the receiving port contacts to the subset of external conductor elements, and the transmitting port contacts are unused and are not connected to any of the external conductor elements.