Patent ID: 7865654

Claim:
A computer system comprising: a switch that is programmable to associate each of a first plurality of virtual bridges with a respective bridge header of a plurality of bridge headers; and a first compute node coupled via the switch to each of at least a first subset of one or more shared or non-shared I/O devices and to at least a second subset of the one or more shared or non-shared I/O devices; wherein the switch includes a second plurality of virtual bridges coupling a second root port of the first compute node to at least a second subset of the one or more shared or non-shared I/O devices; and wherein the switch is configured to: receive a first packet including data which identifies a first root port of the first compute node and a first I/O device of the one or more shared or non-shared I/O devices; and route the first packet in response to comparing first data in the first packet to data in one or more of the bridge headers associated with the first plurality of virtual bridges; receive a second packet including data identifying the second root port and a second I/O device of the one or more shared or non-shared I/O devices; and route the second packet in response to comparing second data in the second packet with data in one or more of the bridge headers associated with the second plurality of virtual bridges.