Patent ID: 6856549

Claim:
A non-volatile semiconductor memory device, comprising: a plurality of memory blocks having a plurality of memory cells each arranged in matrix of rows and columns; a plurality of word lines provided corresponding to said rows in said memory cell respectively; a plurality of bit lines provided corresponding to said columns in said memory cell respectively; a data bus line transmitting a potential of said bit line; a column select circuit electrically coupling one bit line selected from said plurality of bit lines in accordance with a column select result to said data bus line; a reference memory block having a plurality of reference memory cells arranged in matrix of rows and columns; a plurality of reference word lines provided corresponding to said rows in said reference memory cell respectively; a plurality of reference bit lines provided corresponding to said columns in said reference memory cell respectively; a reference data bus line transmitting a potential of said reference bit line; a reference column select circuit electrically coupling one reference bit line selected from said plurality of reference bit lines in accordance with a column select result to said reference data bus line; and a sense amplifier arranged corresponding to said data bus line and said reference data bus line, and amplifying a potential difference between said data bus line and said reference data bus line; wherein said column select circuit precharges remainder of said bit lines in a non-selected state to a prescribed potential during a data reading period in which one of said plurality of bit lines is driven to a selected state, and said reference column select circuit precharges remainder of said reference bit lines in a non-selected state to said prescribed potential during a data reading period in which one of said plurality of reference bit lines is driven to a selected state.