Patent ID: 7554840

Claim:
A programmable memory device, comprising: a word line, a first bit line, a second bit line and a third bit line defining a first unit cell and a second unit cell connected in series, wherein the first and second unit cells respectively comprise: a select transistor comprising a select gate connected to the word line; and a stack transistor comprising a floating gate and a control gate, wherein the control gate is electrically connected to the word line, a drain electrode of the select transistor is electrically connected to a source electrode of the stack transistor, wherein the first bit line is electrically connected to a source electrode of the select transistor of the first unit cell, the third bit line is electrically connected to a drain electrode of the stack transistor of the second unit cell, the second bit line is electrically connected to the source electrode of the select transistor of the second unit cell and the drain electrode of the stack transistor of the first unit cell.