Patent ID: 7098704

Claim:
A semiconductor integrated circuit device comprising: an input node and an output node; a pre-buffer having a NAND gate circuit and a NOR gate circuit, the NAND gate circuit being inputted with an input signal from a front-stage circuit through the input node and an output enable signal, and the NOR gate circuit being inputted with an inversion signal of the output enable signal and the input signal; a drive buffer having a first PMOS transistor and a first NMOS transistor connected in series between a power supply node and a ground node, the first PMOS transistor having a gate for receiving an output signal of the NAND gate circuit of the pre-buffer, the first NMOS transistor having a gate for receiving an output signal of the NOR gate circuit of the pre-buffer, a series-connection node of the first PMOS transistor and the first NMOS transistor being connected to the output node; a back-up buffer having a second PMOS transistor and a second NMOS transistor connected in series between the power supply node and the ground node, a senes-connection node of the second PMOS transistor and the second NMOS transistor being connected to the output node, one of the second PMOS transistor and the second NMOS transistor is turned on after the other of the second PMOS transistor and the second NMOS transistor is turned off when the drive buffer is in a switching operation; a first bias circuit configured to receive a potential of the input signal of the input node and a potential of the output node to generate a first control potential; a first latch circuit configured to receive and latch the first control potential; a second bias circuit configured to receive the potential of the input signal of the input node and the potential of the output node to generate a second control potential different from the first control potential in timing of change; and a second latch circuit configured to receive and latch the second control potential, wherein the first control potential latched by the first latch circuit is inputted to a gate of the second PMOS transistor of the back-up buffer and the second control potential latched by the second latch circuit is inputted to a gate of the second NMOS transistor of the back-up buffer.