Patent ID: 8164137

Claim:
A multiple-gate MOS (metal oxide semiconductor) transistor comprising: a single crystalline active region comprising a channel region having an upper portion of a streamlined curvilinear shape (∩) obtained by patterning an upper portion of a bulk silicon substrate to form an embossed pattern, and regions formed on two sides of the channel region to be thicker and wider than the channel region, and wherein the channel region is connected to the silicon substrate; a nitride layer formed on surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid on the channel region of the exposed upper portion of the single crystalline active region, wherein the single crystalline active region further comprises: a first extension region connected to a first side of the channel region and a second extension region connected to a second side of the channel region, each gradually increasing in thickness and width going away from the channel region; and source and drain regions connected to the first and second extension regions, respectively, and being thicker and wider than the channel region and the extension regions.