Patent ID: 8804405

Claim:
A memory device comprising: a first clocked inverter configured to be controlled by a first clock signal; a first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first clocked inverter; a second clocked inverter configured to be controlled by a second clock signal, wherein an input terminal of the second clocked inverter is electrically connected to an output terminal of the first inverter, and an output terminal of the second clocked inverter is electrically connected to the output terminal of the first clocked inverter and the input terminal of the first inverter; a transistor, wherein one of a source and a drain of the transistor is electrically connected to the output terminal of the first clocked inverter, the input terminal of the first inverter, and the output terminal of the second clocked inverter; and a capacitor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor, wherein the first clocked inverter is configured to be controlled independently of the second clocked inverter, and wherein the transistor comprises an oxide semiconductor in a channel formation region.