Patent ID: 7569889

Claim:
A memory integrated circuit, in particular an SRAM memory integrated circuit, comprising: a matrix of memory cells that are arranged in rows and columns of memory cells between two bit lines via two respective access transistors, the bit lines being intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation, wherein the bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in a form of at least two partial bit lines, the memory cells of each column being implanted in a form of groups of cells connected to the partial bit lines, respectively, wherein the bit lines each comprises two partial bit lines each formed from portions of partial lines implanted alternately in a second and a fourth or a third and a fifth metallization levels of the circuit, groups of memory cells being connected to portions of bit lines that are implanted in the second metallization level or the third level.