Patent ID: 7938976

Claim:
A method for removing contaminants that are produced during the positioning and soldering of Pb-free solderballs substantially comprising Sn onto a laminiate including graphitic and/or fluorinated organic layers from a surface of semiconductor chip passivation layer selected from the group of materials consisting of polyimide, PSBI and BCB, having Si-containing organic polymers while avoiding the creation of SiO 2 particles or SnOx/organotin, said method comprising subjecting said surface to a plasma etching process solely employing an N 2 plasma under a low-power within a range of about 100- to less than 200 W and a high-pressure within a range of about 500-750 mTorr; wherein said N 2 plasma etches the surface of said chip passivation layer to a depth of within about 1-20 nm, and implementing said N 2 plasma-etching process on semiconductor wafers which are subsequently processed to form a plurality of said chips.