Patent ID: 8295093

Claim:
A multi-dot flash memory comprising: active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate; floating gates arranged in the first direction, which are provided above the active areas; a word line provided above the floating gates, which extends to the first direction; bit lines provided between the floating gates, which extend to the second direction; and a control circuit which controls potentials of the bit lines in a writing/erasing, wherein the control circuit sets a potential V n+1 of (n+1)-th bit line from a selected floating gate as a target of the writing/erasing to a value within a range of max ⁡ ( C n ⁢ V n + C pg ⁢ V pg + C AA ⁢ V AA + Q min - d n + 1 ⁢ Eth n + 1 ⁡ ( C n + C n + 1 + C pg + C AA ) C n + C pg + C AA , ( C n + 1 + C pg + C AA ) ⁢ V n - C pg ⁢ V pg - C AA ⁢ V AA - Q max - d n ⁢ Eth n ⁡ ( C n + C n + 1 + C pg + C AA ) C n + 1 , ( C n + 1 + C n + C AA ) ⁢ V pg - C n ⁢ V n - C AA ⁢ V AA - Q max - d pg ⁢ Eth pg ⁡ ( C n + C n + 1 + C pg + C AA ) C n + 1 , ( C n + 1 + C pg + C n ) ⁢ V AA - C pg ⁢ V pg - C n ⁢ V n - Q max - d AA ⁢ Eth AA ⁡ ( C n + C n + 1 + C pg + C AA ) C n + 1 ) < V n + 1 < V n when a potential V n of n-th bit line from the selected floating gate is V n >0, where n is a natural number, C n is a capacitance between BL n and FG, C n+1 is a capacitance between BL n+1 and FG, C pg is a capacitance between CG and FG, C AA is a capacitance between AA and FG, V pg is a potential of CG, and V AA is a potential of AA, where BL n is the n-th bit line, BL n+1 is the (n+1)-th bit line, FG is a floating gate between the BL n and BL n+1, CG is a control gate above FG, and AA is an active area under FG, where Q min is a minimum electric charge quantity, Q max is a maximum electric charge quantity, Eth n is a threshold value of electric field intensity in which a transfer of electric charges is generated by a tunneling phenomenon between BL n and FG, d n is a thickness of an insulating film between BL n and FG, Eth n+1 is a threshold value of electric field intensity in which a transfer of electric charges is generated by a tunneling phenomenon between BL n+1 and FG, d n+1 is a thickness of an insulating film between BL n+1 and FG, Eth pg is a threshold value of electric field intensity in which a transfer of electric charges is generated by a tunneling phenomenon between CG and FG, d pg is a thickness of an insulating film between CG and FG, Eth AA is a threshold value of electric field intensity in which a transfer of electric charges is generated by a tunneling phenomenon between AA and FG, and d AA is a thickness of an insulating film between AA and FG.