Patent ID: 7579647

Claim:
A non-volatile semiconductor memory device, comprising: a semiconductor substrate including a memory cell region and a peripheral region, the memory cell region including a plurality of first element regions and a plurality of first separate regions that insulate between the first element regions, each of the first separate regions extending toward a first direction and being embedded in the semiconductor substrate, the peripheral region including a second element region and a second separate region that surrounds the second element region to insulate the second element region and is embedded in the semiconductor substrate; a plurality of control gates, each of the control gates being formed over the first element region and the first separate region and extending toward a second direction crossing to the first direction, respectively; a plurality of charge storage portions, each of the charge storage portions being formed between the control gate and the first element region; a first insulating film formed between the semiconductor substrate and the charge storage portions and between the first separate regions; a second insulating film formed between the charge storage portions and the control gates; a third insulating film formed on the second element region between the second separate region; and a peripheral gate including an electrode portion formed on the third insulating film, wherein a first upper end portion of the first separate regions facing the control gate protrudes from a first upper surface of the semiconductor substrate, a height of the first upper end portion is lower than a height of a second upper surface of the charge storage portion, and a height of a second upper end portion of the second separate region is lower than the height of the first upper end portion.