Patent ID: 7613052

Claim:
A memory device comprising: a plurality of memory cells arranged in at least one column; at least one bit line associated with each of said at least one columns, during a memory access operation a change in voltage on said at least one bit line associated with a selected column indicating a data value for an addressed memory cell in that selected column; a supply voltage line associated with each of said at least one columns, the supply voltage line being connectable to a voltage source to provide a supply voltage to the associated column, for each column a capacitance existing between the associated supply voltage line and the associated at least one bit line; and control circuitry for controlling, for each column, connection of the voltage source to the associated supply voltage line, for a predetermined period during the memory access operation the control circuitry disconnecting the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to the change in voltage on the associated at least one bit line.