Patent ID: 7020732

Claim:
A system comprising a plurality of computer systems, the system comprising: a plurality of computing systems each located at a first location, wherein each of the computing systems includes: a CPU; a memory medium coupled to the CPU; a first I/O bus coupled to the CPU; and a first extender coupled to the first I/O bus; a plurality of human interface systems, wherein each respective one of the human interface systems corresponds to one of the plurality of computing systems, wherein each respective human interface system is located remotely from the first location, wherein each respective human interface system comprises: a second extender; a second I/O bus coupled to the second extender; human interface circuitry coupled to the second I/O bus; and one or more human interface devices coupled to the human interface circuitry; and a plurality of transmission mediums, wherein each transmission medium corresponds to a respective computing system and its respective human interface system, wherein each transmission medium couples the first extender of the respective computing system to the respective second extender; wherein each of the human interface systems is useable by a user to interface with its corresponding computing system; the system further constructed and adapted to communicate between a said first I/O bus and a said second I/O bus by: addressing interactive data from the said first I/O bus to a first bridge; passing the interactive data from the first bridge to a first logic device and in said first logic device: a) buffering the interactive data in a first FIFO; b) outputting the interactive data from the first FIFO across a clock domain barrier; and c) continuing to store the interactive data after said step b); packeting the interactive data into packet data; delivering the packet data to a proximate portion of a long distance communication medium; receiving the packet data at a distal portion of the lone distance communication medium; depacketing the packet data back into interactive data; passing the interactive data to a second logic device and in said second logic device: a) buffering the interactive data in a second FIFO; and b) outputting the interactive data from the second FIFO received across the clock domain barrier; receiving the interactive data from the second logic device at a second bridge; and addressing the interactive data from the second bridge to the second I/O bus.