Patent ID: 7661011

Claim:
A system for modifying a processing time during a processing period in a digital logic module comprising: a processing circuit configured to receive an input, manipulate the input L times, wherein L is an integer, in order to create an output, the processing circuit further comprising, a first combinatorial circuit configured to receive and manipulate the input, and produce a first intermediate output; a second combinatorial circuit coupled to the first combinatorial circuit and configured to receive and manipulate the first intermediate output, and produce a second intermediate output; and a select circuit coupled to the second combinatorial circuit and configured to receive the select signal and select either the first intermediate output or the second intermediate output, based on the select signal; a controller coupled to the processing circuit and configured to track the number of manipulations of the processing circuit, send a select signal to the processing circuit, and cause the processing circuit to create the output over N clock cycles, wherein N is an integer, N is less than or equal to L, and N varies; and an output port coupled to the processing circuit and configured to convey the output.