Patent ID: 7526626

Claim:
An apparatus comprising: a first control circuit coupled to a first data path; a second control circuit coupled to a second data path; a decode circuit coupled to receive an indication of whether or not a first memory channel and a second memory channel are ganged or not ganged and the decode circuit also coupled to receive a command to perform an access to a memory; a channel configuration register coupled to store the indication; and a data normalizer circuit coupled to the first and second control circuits respectively via the first and second data paths, the data normalizer circuit also coupled to the first memory channel and the second memory channel, wherein the data normalizer circuit to route data between the first data path and the memory via both the first and second memory channels when the indication indicates that the memory channels are ganged, but the data normalizer circuit to route data between the first data path and the first memory channel and to route data between the second data path and the second memory channel when the indication indicates that the memory channels are not ganged.