Patent ID: 8078661

Claim:
A multiple-word multiplication-accumulation (MAC) circuit that performs MAC operation on given input values each supplied as multiple-word data, comprising: a memory bus having a first bit width, directly coupled to a single-port memory configured to provide storage for a plurality of multiple-word data; a MAC operator having multiplicand and multiplier input ports with different bit widths to calculate a sum of products of the multiple-word data read out of said single-port memory; a first register configured to input a multiplicand with a second bit width to said MAC operator; a second register configured to input a multiplier with a third bit width to said MAC operator in each clock cycle; a third register configured to input a first additional value with the third bit width to said MAC operator in each clock cycle; a fourth register configured to hold an upper portion with the second bit width of said MAC operator's output, and input a second additional value with the second bit width to said MAC operator; and a fifth register configured to receive a lower portion with the third bit width of said MAC operator's output a plurality of times and to output input values of the fifth register to the single-port memory when an amount of the input values of the fifth register reaches the first bit width, wherein total amount of data of the multiplier, the first additional value, and an input value of the fifth register is equal to or smaller than the first bit width.