Patent ID: 8155903

Claim:
A circuit arrangement for measuring a capacitance of a capacitor, comprising: an evaluation circuit having an input node connected to a terminal of the capacitor, the other terminal of the capacitor being connected to a reference potential, the evaluation circuit detects an input voltage with a predetermined degree of precision only if the input voltage lies within a predetermined voltage measurement interval having an upper limit, a first switch device connecting the input node to a constant voltage potential, a second switch device coupling a resistor of predetermined size between the input node and the reference potential, a control device connected to the first and the second switch device controls the switch devices so that (a) first the input node is connected to the constant voltage potential, wherein the evaluation circuit generates an output value which assumes an extreme value when the input node is at the constant voltage potential, (b) the resistor is then connected between the input node and the reference potential for a predetermined time period so that the input voltage between the input node and the reference potential falls to a final value which lies in the predetermined voltage measurement interval, and (c) the input node is then disconnected from the reference potential and the constant voltage potential so that the input voltage is held at the final value, the evaluation circuit generating an output value which is proportional to the final value, the output of the evaluation circuit is connected to a device for storing the output value and determining an appertaining capacitance value.