Patent ID: 8731105

Claim:
A pre-distorter memory modeling apparatus, comprising: a plurality of branches, each branch receiving a different output basis function signal, at least one branch including: a down-sampler, the down-sampler down-sampling the received output basis function signal received at the branch by a down-sampling factor of 1/M k , M k being different for each of the at least one branch and being based on an evaluation period associated with the corresponding each of the at least one branch; and a memory structure, the memory structure receiving and filtering an output of the down-sampler, the memory structure including: at least one delay element, at least one of the at least one delay element delaying the output of the down-sampler according to a corresponding pre-determined delay; and a memory structure output based on an output of the at least one delay element; and an up-sampler, the up-sampler up-sampling the memory structure output by an up-sampling factor equal to M k .