Patent ID: 7920699

Claim:
An encryption operating apparatus comprising: a register that fetches data from a data input line synchronously with a clock signal, and holds the fetched data as valid code data; a control circuit that monitors signals flowing through the data input line, and alternately outputs an enable signal and a disable signal for each time when the signals are stable; a selection output circuit that outputs a valid code data held in the register corresponding to the enable signal, and outputs invalid code data other than the valid code data corresponding to the disable signal; a combinational circuit that encrypts or decrypts the valid code data output from the selection output circuit, outputs the encrypted or decrypted data to the data input line, and outputs the invalid code data output from the selection output circuit to the data input line; and a clock filter that controls the clock signal corresponding to the enable signal or the disable signal output from the control circuit, wherein the control circuit outputs the disable signal when it is determined that the valid code data is input to the data input line, and outputs the enable signal when it is determined that the invalid code data is input to the data input line.