Patent ID: 7358573

Claim:
A method, comprising: forming a P-type doped layer in a P-type silicon substrate, said P-type doped layer extending to a top surface of said substrate; forming an epitaxial layer on a top surface of said substrate to form a buried P-type doped layer from said P-type doped layer, a top surface of said buried P-type doped layer extending a first distance below a top surface of said epitaxial layer; forming an N-well and a P-well in said epitaxial layer, both said N-well and said P-well extending from a top surface of said epitaxial layer to a top surface of said buried P-type doped layer; forming a buried N-type doped layer in said P-well, a bottom surface of said buried N-type doped layer in contact with said top surface of said buried P-type doped layer, said buried N-type doped layer extending from said top surface of said buried P-type doped layer toward said top surface of said epitaxial layer a second distance, said second distance less than said first distance; forming a PFET in said N-well and forming an NFET in said P-well; forming a P-type contact in said P-well and forming an N-type contact in said N-well, both said P-type contact and said N-type contact extending from said top surface of said epitaxial layer into said epitaxial layer respective third and fourth distances, said third and fourth distances less than a fifth distance between said top surface of said buried N-type doped layer and said top surface of said epitaxial layer; and forming a gap in said buried N-type doped layer, said gap aligned under said P-type contact, said P-well contacting said top surface of said buried P-type doped layer in said gap.