Patent ID: 6993637

Claim:
A memory system for multiple processors, said system comprising: a unified memory including a plurality of memory banks; a memory controller coupled to said unified memory, said memory controller receiving requests from the multiple processors, each of the requests including information of a memory address, said memory controller selecting one of the memory banks by asserting a request signal only for a memory bank including the requested memory address, and providing the requesting processor with a requested memory operation on the selected memory bank, wherein said memory system and the multiple processors are formed on a same semiconductor substrate, and a clock signal generator, said clock signal generator generating a memory clock signal having more than one active edges during one clock cycle of a base clock signal for the multiple processors, wherein the memory clock signal is generated using a controller clock signal having a frequency of n×f, where n is the number of the multiple processors and f is a frequency of a base clock signal for the multiple processors.