Patent ID: 7028142

Claim:
A system for reducing latency for accessing a program memory shared by a plurality of processors, said system comprising: a plurality of fetch buffers, one for each of said plurality of processors, each for storing a plurality of local instructions local to an instruction being used by an associated processor; a plurality of prefetch buffers, one for each of said plurality of processors, each for storing a plurality of subsequent instructions subsequent to said plurality of local instructions stored in an associated fetch buffer; a plurality of program fetch logic units, one for each of said plurality of processors, each for determining from where to fetch a next instruction required by said associated processor; and an arbiter for arbitrating between a plurality of instruction fetch requests received for said plurality of fetch buffers and said plurality of prefetch buffers, for determining which of said plurality of instruction fetch requests will gain a next access to said program memory wherein access to said program memory is a wide interface access for retrieving at least two instructions in one cycle and each of said processors executes one instruction per cycle.