Patent ID: 7398360

Claim:
A node comprising: a plurality of processor cores, each processor core configured to have a plurality of threads active and each processor core including at least one first level cache; coherency control circuitry coupled to the plurality of processor cores and configured to manage intranode coherency among the plurality of processor cores; at least one coherence unit coupled to the coherency control circuitry and configured to couple to an external interface of the node, the coherence unit configured to transmit and receive coherence messages on the external interface to maintain coherency with at least one other node having one or more processor cores and a coherence unit; and the coherency control circuitry is configured to receive a first request from the at least one coherence unit to maintain internode coherency and a second request from one of the plurality of processor cores, and the coherency control circuitry is configured to generate communications to the first level caches in the processor cores to maintain intranode coherency in response to the second request and to maintain internode coherency in response to the first request from the at least one coherence unit.