Patent ID: 7554181

Claim:
A semiconductor device comprising: a first chip mounting section, a second chip mounting section, and a third chip mounting section, respectively disposed at predetermined intervals, with each chip mounting section being disposed so as not to overlap each of the other chip mounting sections in plan view; a plurality of external terminals disposed around the first, second, and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including control circuits which control operations of the first and second field effect transistors; and a resin body that encapsulates the first, second, and third semiconductor chips, the first, second, and third chip mounting sections and one or more of the external terminals, wherein the plurality of external terminals include a first power supply terminal that supplies an input power supply potential, a second power supply terminal that supplies a potential lower than the input power supply potential, signal terminals that control the control circuits of the third semiconductor chip, and an output terminal that outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-to-drain path series-connected between the first power supply terminal and the output terminal, wherein the second field effect transistor has a source-to-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuits of the third semiconductor chip control the gates of the first and second field effect transistors based on control signals inputted to the signal terminals, wherein the third semiconductor chip is disposed such that a closest distance between the third semiconductor chip and the first semiconductor chip is less than a closest distance between the third semiconductor chip and the second semiconductor chip, wherein the control circuits of the third semiconductor chip include a first control circuit which controls the gate of the first field effect transistor, and a second control circuit which controls the gate of the second field effect transistor, wherein the third semiconductor chip further includes a rectangular-shaped main surface, a plurality of electrodes formed over the main surface, and a third field effect transistor that includes an output stage of the second control circuit, wherein the third field effect transistor is disposed on one side of the third semiconductor chip most adjacent to the second semiconductor chip, and wherein the source electrodes connected to a source of the third field effect transistor, of the plurality of electrodes, are disposed more inwardly from a periphery of the third semiconductor chip than others of the plurality of electrodes.