Patent ID: 8330517

Claim:
A circuit having improved resistance to metastable conditions, comprising: a bistable circuit having first and second complementary output nodes and configured to latch a state of input data on a first edge of a clock signal; and a metastability correction circuit including: a power boost circuit configured to couple the first and second complementary output nodes of the bistable circuit to a power source in response to an enable signal; wherein the first and second output nodes are coupled to the power source in response to a first state of the enable signal; wherein the first and second output nodes are decoupled from the power source in response to a second state of the enable signal; and a control circuit configured to: detect whether operation of the bistable circuit is stable or unstable; and assert the enable signal in the first state in response to each first edge of the clock signal and assert the enable signal in the second state in response to detecting stable operation of the bistable circuit.