Patent ID: 8227859

Claim:
A semiconductor device, comprising: a step-type saddle fin recess pattern formed in a substrate including an active region and an isolation region; a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern; an insulation layer filling the gap; and a source region and a drain region formed in portions of the substrate at opposite sides of the recess pattern by doping impurities into the substrate, wherein the recess pattern comprises: a first pattern crossing the isolation region and the active region at the same time; a second pattern connected to a bottom of the first pattern in the active region and having the width smaller than the width of the first pattern: and a third pattern connected to the bottom of the first pattern in the isolation region, having the width smaller than the width of the first pattern, and exposing a lower surface and lower sidewalls of the second pattern with a saddle fin structure.