Patent ID: 8443121

Claim:
An electronic component comprising: an upstream interface circuit comprising an upstream interface buffer; and a downstream interface circuit comprising a downstream interface buffer; and an associated logic component that is associated with the upstream interface circuit and the downstream interface circuit of the electronic component, wherein the upstream interface circuit is configured to: transmit an upstream receive readiness signal to an upstream logic component, the upstream receive readiness signal indicative of readiness of the associated logic component, wherein the upstream interface buffer is configured to: receive an upstream transmit readiness signal from the upstream logic component; and in response to readiness of the associated logic component, receive data from an upstream logic component; buffer the received data, and transmit the data to the associated logic component; wherein the associated logic component is configured to: receive the data from the upstream interface buffer; perform one or more functions on the data; and transmit the data to the downstream interface buffer after performing one or more functions on the data and when the downstream interface buffer is ready to receive the data; and wherein the downstream interface buffer is configured to transmit the data received from the associated logic component to a downstream logic component in response to a downstream receive readiness signal from the downstream logic component.