Patent ID: 8193851

Claim:
A fuse circuit of a semiconductor device, the fuse circuit comprising: a plurality of fuse set units configured to compare an input address with address information programmed according to a fuse cutting state; and a test control unit configured to enable one or more fuse set units selected based on a number of times that a selection signal is enabled in a test mode, wherein the test control unit sequentially enables a plurality of fuse set groups, each fuse set group including a plurality of fuse set units, in response to the selection signal in the test mode, and wherein all fuse set units of the same fuse set group are enabled at the same time, wherein each of the plurality of fuse set units comprises: an enable fuse unit configured to output an enable signal corresponding to an electrical connection state of an enable fuse; an address fuse unit configured to have a plurality of address fuses, and compare the address information programmed in the plurality of address fuses with address bit signals of the input address; and a signal combination unit configured to combine a plurality of comparison result signals outputted from the address fuse unit in response to the enable signal.