Patent ID: 8030977

Claim:
A clock generating circuit comprising: a main clock circuit configured to output a main clock; and a first sub-clock circuit configured to output a first sub-clock synchronized with the main clock, based on the main clock, the main clock circuit including a first capacitor having a first end connected to a first potential, a first current supply circuit configured to supply to a second end of the first capacitor a first current for charging at a predetermined current value or a second current for discharging at a predetermined current value, a first charge/discharge control circuit configured to output a first control signal for switching between the first current and the second current when a voltage at the second end of the first capacitor has reached a first reference voltage or a second reference voltage higher than the first reference voltage, the first current and the second current supplied to the first capacitor from the first current supply circuit, and a first output circuit configured to output the main clock according to the first control signal, the first sub-clock circuit including a second capacitor having a first end to which the main clock is input, a second current supply circuit configured to supply to a second end of the second capacitor a third current for charging at a predetermined current value or a fourth current for discharging at a predetermined current value, a second charge/discharge control circuit configured to output a second control signal for switching between the third current and the fourth current when a voltage at the second end of the second capacitor has reached a third reference voltage or a fourth reference voltage higher than the third reference voltage, the third current and the fourth current supplied to the second capacitor from the second current supply circuit, and a second output circuit configured to output the first sub-clock according to the second control signal.