Patent ID: 7191418

Claim:
A method and apparatus for high-speed very-large-scale-integration comprising: (a) inputting a clock tree netlist of a clock tree having at least two paths having buffers, with the clock tree netlist including an electricity parameter of each of the paths and a buffer timing library; (b) inputting an upper limit of a clock skew; (c) preparing a delay calculator for calculating a clock delay of each of the paths of the clock tree netlist; and (d) preparing a calculating method for rapidly selecting types of buffers, outputtng a minimized clock delay and conforming to a best clock tree netlist of the clock skew when conforming to the upper limit of the clock skew, wherein the delay calculator comprises: a buffer delay calculator for calculating the delay of an original path and the delay after displacing the type of the buffer and renewing the path between the connections of the buffers; and a flip-flop path delay calculator for recording the delay of a connection between the buffer and a flip-flop and for calculating the clock delay and the clock skew.