Patent ID: 7757134

Claim:
A test apparatus for testing a memory under test, comprising: a pattern generator operable to generate a read address from which data is read from the memory under test and an expected value of the read data read from the read address of the memory under test; a logical comparator operable to compare read data read from the read address of the memory under test to the expected value and outputting fail data indicating pass/fail of every bit of the read data; a first fail memory operable to store a grouping of the read address and the fail data only in a case where the read data is not identical to the expected value; a second fail memory operable to store fail data in addresses corresponding to each address of the memory under test; and an updating section operable to update fail data stored in the second fail memory and corresponding to the read address based on the fail data read from the first fail memory that is in the same grouping as the read address.