Patent ID: 7851303

Claim:
A method of manufacturing a semiconductor device comprising: forming a source region and a drain region in a semiconductor substrate; forming a first interlayer insulating film covering the source region and the drain region; forming first and second contact electrodes provided to penetrate through the first interlayer insulating film and electrically connected to one of and the other of the source region and the drain region, respectively; forming a second interlayer insulating film covering the first and second contact electrodes; forming a third contact electrode provided to penetrate through the second interlayer insulating film and electrically connected to the first contact electrode; forming a conductive material on the second interlayer insulating film so as to be electrically connected to the third contact electrode; forming a wiring pattern extended to a first direction by patterning the conductive material by using a mask; removing the third contact electrode at a part not covered by the wiring pattern, by etching the third contact electrode by using the mask; forming a third interlayer insulating film covering the wiring pattern; and forming a fourth contact electrode provided to penetrate through the second and third interlayer insulating films and electrically connected to the second contact electrode.