Patent ID: 7615469

Claim:
A method of forming an edge seal region of a semiconductor die comprising: providing a substrate of a first conductivity type; forming an active region of a first semiconductor die on a first portion of the substrate and forming an active region of a second semiconductor die on a second portion of the substrate wherein a third portion of the substrate is positioned between the first and second portions of the substrate; forming a first dielectric layer on a surface of the substrate overlying the third portion of the substrate; forming a second dielectric layer overlying the first dielectric layer; forming a passivation layer overlying the second dielectric layer; forming an opening through a portion of the passivation layer, the second dielectric layer, and the first dielectric layer and exposing a region of the surface of the substrate that is within the third portion of the substrate wherein a first edge of the second dielectric layer is exposed along a sidewall of the opening; forming a doped region of the first conductivity type on the surface of the substrate through the opening and substantially aligned to the first edge of the second dielectric layer; and forming a metal on a portion of the doped region and abutting the first dielectric layer and the passivation layer.