Patent ID: 7940598

Claim:
An integrated circuit memory device comprising: a first plurality of memory banks; a second plurality of memory banks; and an interface circuit to receive interleaved row and column information to access the first and second plurality of memory banks, the interface circuit to alternate between accessing the first plurality of memory banks and accessing the second plurality of memory banks in response to the row and column information, wherein the interface circuit includes: a register to receive the row and column information to access the first and second plurality of memory banks; and a decode circuit to alternate between providing the row and column information to the first and second plurality of memory banks such that the decode circuit provides first row or column information to the second plurality of memory banks after providing second row or column information to the first plurality of memory banks, that the decode circuit provides the second row or column information to the first plurality of memory banks after providing third row or column information to the second plurality of memory banks, and that the decode circuit provides the third row or column information to the second plurality of memory banks after providing fourth row or column information to the first plurality of memory banks.