Patent ID: 7730371

Claim:
A test apparatus for testing and repairing a memory under test that is addressable by the number of pulses of an address signal supplied thereto, the test apparatus comprising: a pattern generating section that generates writing data to be written into the memory under test, wherein, when the test apparatus tests an address of the memory under test, the writing data is test data, wherein, when the test apparatus repairs a defective address of the memory under test, the writing data is repairing data, and wherein the pattern generating section comprises a second address generating section that generates an address signal that sequentially designates each address of the memory under test to which the test data is to be written; a first address generating section that stores thereon address information indicating the defective address of the memory under test to which the repairing data is to be written and generates an address signal based on the stored address information; an address selecting section that, when the test apparatus tests an address of the memory under test, selects the address signal generated by the second address generating section and, when the test apparatus repairs the defective address of the memory under test, selects the address signal generated by the first address generating section; and a waveform shaping section that shapes the selected address signal by outputting one or more pulses at a predetermined time interval and provides the shaped address signal to the memory under test.