Patent ID: 7684253

Claim:
A flash memory device comprising: a memory cell array configured to have a plurality of memory cells coupled to a plurality of bit line pairs; a plurality of page buffers coupled respectively to the bit line pairs, the plurality of page buffers being configured to sense data from a selected memory cell of the memory cells and to output the sensed data into first data lines in a reading operation, and input data transmitted from the first data lines to the selected memory cell of the memory cells in a data input operation; a Y-decoder section configured to couple one of the first data lines to one of second data lines by using one of internal data lines in response to a Y-decoder driving signal, thereby forming a data input path of at least one of the page buffers; a precharging section configured to precharge each of the internal data lines in response to first and second precharging signals during the data input operation; and a discharge element which is connected to the respective second data lines, wherein the discharge element discharges the internal data lines in response to a discharge signal during the data input operation.