Patent ID: 7639044

Claim:
A semiconductor integrated circuit configured with Metal Insulated Semiconductor transistors formed on a silicon substrate having a Silicon On Insulator structure, comprising a first logic gate and a second logic gate, wherein: the first logic gate takes a first potential set having a relatively small potential difference as a power supply voltage; the second logic gate takes a second potential set having a relatively large potential difference as a power supply voltage; and the semiconductor integrated circuit satisfies at least one of a condition that a substrate potential of a P-channel Metal Insulated Semiconductor transistor of the first logic gate is equal to or higher than a substrate potential of a P-channel Metal Insulated Semiconductor transistor of the second logic gate, and a condition that a substrate potential of an N-channel Metal Insulated Semiconductor transistor of the first logic gate is equal to or lower than a substrate potential of an N-channel Metal Insulated Semiconductor transistor of the second logic gate.