Patent ID: 7447830

Claim:
An information processing system, comprising: a plurality of memories to be grouped into a first memory group and a second memory group; a data processor configured to transmit a data access request to the plurality of memories; and a memory controller configured to control data transfer between the data processor and the plurality of memories, comprising: an address calculation circuit configured to calculate a second data address from a first data address included in the data access request; a control unit configured to control operation of the first memory group including the first data address to be accessed and operation of the second memory group including the second data address to be accessed, by transmitting a first control command to the first memory group and a second control command to the second memory group in different clock cycles, respectively; and a data transmission unit configured to transmit data between the memory controller and the plurality of memories, comprising: a plurality of data buffers configured to store data transmitted from the plurality of memories; and a plurality of selectors configured to select one of data transmitted from the plurality of memories and data transmitted from the plurality of data buffers, for each of the plurality of memories.