Patent ID: 7728642

Claim:
A programmable delay line that generates an output signal from an input signal, the programmable delay line comprising: a first oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a transition of the input signal; wherein the first oscillator is enabled responsive to a rising edge of the input signal; a second oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a falling edge of the input signal; a first programmable ripple counter coupled to the first oscillator, the first ripple counter counting with each successive clock cycle to a programmed count and generating a first signal in response to reaching the programmed count; a second programmable ripple counter coupled to the second oscillator, the second ripple counter counting with each successive clock cycle to the programmed count and generating a second signal in response to reaching the programmed count; and a control circuit coupled to the first oscillator and to the first programmable ripple counter, wherein the control circuit transitions the output signal and disables the first oscillator in response to the first signal, wherein the control circuit is further coupled to the second oscillator and to the second programmable ripple counter, and the control circuit transitions the output signal in response to the first and second signals.