Patent ID: 8772867

Claim:
A high voltage high side DMOS, comprising: a P-type substrate with an epitaxial layer formed on the P-type substrate; a field oxide formed on the epitaxial layer; an N-type well region formed in the epitaxial layer; a gate oxide formed on the epitaxial layer; a gate poly formed on the gate oxide and on the field oxide; a P-type base region formed in the epitaxial layer; a deep P-type region merging with the P-type base region formed in the epitaxial layer; an N-type lightly doped well region formed under the P-type base region in the epitaxial layer, wherein the N-type well region is formed in the N-type lightly doped well region; a first N-type highly doped region formed in the N-type well region; a second N-type highly doped region formed in the P-type base region; a P-type highly doped region formed in the P-type base region, the P-type highly doped region being adjacent to the second N-type highly doped region; a TEOS layer formed on the gate poly; an inter layer dielectric formed on the TEOS layer and on the gate oxide; a drain electrode contacted with the first N-type highly doped region; and a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.