Patent ID: 7888745

Claim:
A semiconductor structure comprising: a semiconductor substrate having at least a pair of first neighboring shallow trench isolation (STI) regions disposed therein, said pair of first neighboring STI regions defining an active area in said substrate; a collector disposed in a buried region in said active region of said substrate, said buried region having a graded profile of dopants; a base layer disposed atop a surface of said semiconductor substrate in said active area; a raised extrinsic base disposed on said base layer, said raised extrinsic base having an opening to a portion of said base layer; an emitter located in said opening and extending over a portion of said raised extrinsic base, said emitter is spaced apart and isolated from the raised extrinsic base, wherein a lower surface of the emitter is coplanar with an entire lower surface of the raised extrinsic base, and wherein the entire lower surface of the raised extrinsic base is planar; and a second shallow trench isolation (STI) region in said semiconductor substrate extending inward from a sidewall of each first shallow trench isolation (STI) region of the pair of said neighboring first (STI) regions, the second STI region present adjacent to each of the pair of the first neighboring STI regions and extending inwards towards said collector, wherein said second STI region does not overlie an upper surface of each of the pair of the first neighboring STI regions, and the second STI region has an inner sidewall surface in proximity to the collector that is sloped and underlying the base layer, wherein a planar surface portion of the second shallow trench isolation region is coplanar with an upper surface of the collector, and wherein said planar surface portion of the second shallow trench isolation region is parallel with a lower surface of the base layer and extends from the inner sidewall surface that is sloped towards the first trench isolation region.