Patent ID: 6855980

Claim:
An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions of a second conductivity type formed in the substrate, with a channel region therebetween; an electrically conductive floating gate disposed vertically over and insulated from a portion of said channel region and a portion of the first region; an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the floating gate, and an upper portion that extends up and over the floating gate and terminates in a first end that is disposed vertically over and insulated from the floating gate; an electrically conductive control gate having a first portion and a second portion, the first control gate portion being disposed laterally adjacent to and insulated from the floating gate, and the second control gate portion extends up and over the floating gate and terminates in a second end that is disposed vertically over and insulated from the floating gate; wherein the first and second ends are disposed laterally adjacent to and insulated from each other such that no portion of the control sate is disposed directly between the floating gate and the source region; and an insulation material disposed directly between the floating gate and the second end, and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.