Patent ID: 8901954

Claim:
An integrated circuit comprising an active shield, said active shield comprising upper layer conductive lines ( 2 ) arranged in a shielding manner to cover at least a part of a security critical circuit ( 3 ) arranged in lower layers of an integrated circuit ( 1 ); electrically controllable switching circuits arranged to select the connections of ones of said upper layer conductive lines ( 2 ) to other ones of said upper layer conductive lines ( 2 ) to form a multiplicity of data bit lines; internal data buses ( 12 ) arranged in lower layers of the integrated circuit ( 1 ); at least one transmitter ( 7 ) and a multiplicity of receivers ( 8 ), wherein the transmitter ( 7 ) is arranged to transmit test data to the receivers ( 8 ) via both the said data bit lines and said internal data buses ( 12 ), the said at least one transmitter ( 7 ) comprises means for generating a select signal ( 11 ) and means for transmitting the select signal ( 11 ) to the said receivers ( 8 ) and the said electrically controllable switching circuits ( 5 ) via a data path arranged in lower layers of the integrated circuit ( 1 ), and the said at least one transmitter ( 7 ) is arranged to change the value of the said select signal ( 11 ) in regular or random time intervals; the said electrically controllable switching circuits ( 5 ) are arranged to select different ones of said upper layer conductive lines ( 2 ) for the different values of the said select signal ( 11 ) to change the interconnection configuration ( 9 , 10 ) of the said bit lines; the said receivers ( 8 ) comprises means for reordering the said bit lines according to the said interconnection configuration ( 9 , 10 ) selected by the said select signal ( 11 ) and, the said receivers ( 8 ) are configured to compare the test data received from the said bit lines with the actual test data received from the said internal data buses ( 12 ), in order to verify the integrity of the said upper layer conductive lines ( 2 ).