Patent ID: 7135731

Claim:
A vertical dynamic random access memory (DRAM) comprising: a substrate comprising at least a deep trench having an upper trench portion and a lower trench portion; an annular spacer surrounding the upper trench portion; a trench capacitor located in the lower trench portion; a source-isolation oxide layer located on the trench capacitor; a shallow trench isolation (STI) positioned around the deep trench; and a vertical transistor located on the source-isolation oxide layer, the vertical transistor comprising: an annular source set in the substrate next to the source-isolation oxide layer, the annular source being electrically connected to the trench capacitor; a gate conductive layer filling the upper trench portion and electrically connected to a first contact plug; a cylindrical gate dielectric layer located on a surface of a sidewall of the upper trench portion and circularly encompassing the gate conductive layer; and an annular drain circularly encompassing the deep trench near a surface of the substrate, the annular drain being positioned next to the STI and electrically connected to a second contact plug, the STI completely compassing the vertical transistor and separating the annular drain from other annular drains of any adjacent vertical transistors in the substrates, the second contact plug having an asymmetric structure, which is positioned on the annular spacer and the annular drain while contacts the spacer and the annular drain at the same time.