Patent ID: 7851315

Claim:
A method of fabricating a field effect transistor, comprising: forming a dielectric isolation along an entire perimeter of a region of a silicon layer to define a silicon body in said silicon layer; forming a gate dielectric layer on said silicon body, said gate dielectric layer having a single thickness; forming an electrically conductive gate electrode on said gate dielectric layer, said gate dielectric layer having a uniform thickness after said forming said electrically conductive gate electrode, a bottom surface of said gate electrode abutting a top surface of said gate dielectric layer, said gate electrode having a first region having a first thickness and a second region having a second thickness, said first region extending along said top surface of said gate dielectric layer over a channel region of said silicon body, said second thickness greater than said first thickness; and wherein a bottom surface of an insulating layer abuts a bottom surface of said silicon body, said bottom surface of said silicon body opposite a top surface of said silicon body.