Patent ID: 8198194

Claim:
A method of forming a p-channel MOSFET, the method comprising: forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate; forming a sacrificial sidewall spacer layer on the gate electrode; patterning a mask layer on the sacrificial sidewall spacer layer; selectively etching the sacrificial sidewall spacer layer to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask; performing a PFET halo-implant into portions of the semiconductor substrate extending adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask; then etching source and drain region trenches into the semiconductor substrate, adjacent opposite sides of the gate electrode; filling the source and drain region trenches by epitaxially growing SiGe source and drain regions therein; selectively removing the sacrificial sidewall spacers from sidewalls of the gate electrode; and implanting source and drain region dopants into the SiGe source and drain regions, using the gate electrode and the first sidewall spacers as an implant mask.