Patent ID: 7423898

Claim:
A nonvolatile semiconductor memory device comprising: a memory array having a plurality of phase change memory cells arranged in rows and columns, each having a resistance value changed through application of heat to store data according to the resistance value; write current supply circuitry for supplying a write current to a selected memory cell among the memory cells in a data write operation; a plurality of bit lines, arranged corresponding to the memory cell columns, each connected to the memory cells in a corresponding column; and a plurality of source lines for forming current paths each for conducting said write current in combination with said selected memory cell and a corresponding bit line, said write current flowing through a current path formed of a bit line connected to the selected memory cell, said selected memory cell and the source line connected to said selected memory cell, and a total resistance value of the path of said write current from said write current supply circuitry to a reference voltage node except a resistance value of the selected memory cell being substantially constant independently of a position of the selected memory cell in said memory array.