Patent ID: 7428181

Claim:
A semiconductor device comprising: an interface allowing connection with an external device; a memory array for use with self refresh circuitry for producing preliminary refresh signals and location refresh signals in response to internal test control signals during a self refresh test mode of the semiconductor device, at least some of the preliminary refresh signals used in producing the location refresh signals, the preliminary refresh signals and the location refresh signals including row address strobe signals; selection circuitry connected to the self refresh circuitry for use with the memory array for selecting memory locations to be refreshed in response to the location refresh signals; and a self refresh test mode controller connected to the self refresh circuitry and the interface for receiving control signals for modifying self refreshing operations of the semiconductor device, the self refresh test mode controller for outputting the internal test control signals during the self refresh test mode of the semiconductor device, the self refresh test mode controller including circuitry for outputting indicating signals indicative of at least one refresh signal through the interface to the external device, the self refresh test mode controller controlling operation of at least one of a timer, a buffer, and a decoder in outputting self refresh timing signals, holding row addresses, and refreshing selected rows, respectively.