Patent ID: 6936874

Claim:
A multi-chip semiconductor apparatus in which a first chip and a second chip coexist and each of the first and second chips includes circuit components provided on a circuit surface, one of the first and second chips comprising: a first wiring layer provided on a semiconductor substrate; a second wiring layer provided on an insulating layer covering the first wiring layer, the second wiring layer including conductive lines each interconnecting the circuit components of said one of the first and second chips; a first electrode provided in the first wiring layer; and a plurality of second electrodes provided on each of the conductive lines, the conductive lines being configured to interconnect the first electrode and the plurality of second electrodes, wherein the plurality of second electrodes are provided such that, when the first and second chips are combined together, the plurality of second electrodes contact corresponding electrodes of the other of the first and second chips so that the conductive lines interconnect the first chip and the second chip via the plurality of second electrodes, wherein the first chip and the second chip are disposed so that the circuit surface of the first chip and the circuit surface of the second chip confront each other.