Patent ID: 7358141

Claim:
A method of fabricating a semiconductor device including a trench-gate MISFET, comprising the steps of: (a) providing a semiconductor body having a first semiconductor layer thereon; (b) forming a gate trench on a main surface of the first semiconductor layer; (c) forming a gate insulating film on an inner wall of the gate trench; (d) forming a gate electrode on the gate insulating film; (e) forming a base region in the first semiconductor layer; (f) forming a source region on the base region; (g) forming an interlayer insulating film over the source region; (h) after the step (g), forming a contact hole in the interlayer insulating film and first semiconductor layer to expose a side surface of the source region, said contact hole being extended to the base region; (i) after the step (h), etching side walls of the interlayer insulating film to enlarge the contact hole and expose an upper surface of the source region; and (j) after the step (i), forming a source wiring in the contact hole and over the interlayer insulating film, wherein the source wiring is contacted with the side and upper surfaces of the source region.