Patent ID: 6925421

Claim:
A method in a data processing system for determining the memory request load placed on one of a plurality of physically separate memory banks by a plurality of processors, said plurality of memory banks and said plurality of processors being physically distributed throughout a semiconductor substrate in said data processing system, said method comprising the steps of: one of said plurality of processors being located physically closer to one of said plurality of memory banks than to others of said plurality of memory banks, an access time for said one of said plurality of processors to access said one of said plurality of memory banks being different from an access time for said one of said plurality of processors to access said others of said plurality of memory banks; determining a relative size of one of said plurality of memory banks with respect to a total size of all of said plurality of memory banks; and estimating a load placed on said one of said plurality of memory banks by determining a number of said plurality of processors that have all of their memory requests satisfied by said one of said plurality of memory banks utilizing said determined relative size and a value of a total quantity of said plurality of processors.