Patent ID: 7752369

Claim:
A computer implemented method for verifying request-to-grant delay properties of a random priority based arbiter system, the computer implemented method comprising: determining, in terms of a number of complete random sequences, an upper bound of a request-to-grant delay of an arbiter, wherein a complete random sequence in a random number sequence is a shortest contiguous sequence of random numbers in the random number sequence having all possible unique random numbers at least once; determining, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter; and determining a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.