Patent ID: 8271746

Claim:
A computer system comprising: a plurality of clients that request access to a memory, wherein each of the plurality of clients comprises a look ahead structure and a request queue for queuing memory access requests, wherein said look ahead structure includes: a row bank direction queue having a plurality of entries, each entry indicating at least a memory row to be accessed and a read or write direction for the access; an activation selection logic circuit coupled to receive a plurality of entries from said row bank direction queue and configured to select one of said entries in said row bank direction queue as an activation candidate tier; and a precharge selection logic circuit coupled to receive said plurality of entries from said row bank direction queue and configured to select one of said entries in said row bank direction queue as a precharge candidate tier; and a memory interface coupled between said plurality of clients and said memory, wherein said memory interface comprises: a first arbiter coupled to receive said activation candidate tier from each of said clients and configured to select one of said activation candidate tiers as an activation command to be sent to said memory; a second arbiter coupled to receive said precharge candidate tier from each of said clients and configured to select one of said precharge candidate tiers as a precharge command to be sent to said memory; and a third arbiter coupled to receive a candidate memory access request from said request queue of each of said clients and configured to select one of said candidate memory access requests as a read or write command to be sent to said memory.