Patent ID: 7042092

Claim:
A multilevel metal interconnect formed on a semiconductor substrate, the semiconductor substrate having a plurality of active areas, the multilevel metal interconnect comprising: a plurality of layers of insulation material, the plurality of layers of insulation material including a first layer of insulation material and a top layer of insulation material, the first layer of insulation material being formed on the semiconductor substrate; a corresponding plurality of patterned metal layers formed on the layers of insulation material so that each patterned metal layer is formed on a corresponding layer of insulation material, a patterned metal layer including a plurality of metal lines, the plurality of patterned metal layers including a first patterned metal layer and a top patterned metal layer, the first patterned metal layer being formed on the first layer of insulation material; a plurality of contacts formed through the first layer of insulation material to make electrical connections with the active areas and the first patterned metal layer; a plurality of vias formed through the plurality of layers of insulation material other than the first layer of insulation material, the vias making electrical connections with adjacent patterned metal layers; a dielectric structure formed between laterally adjacent metal lines of a patterned metal layer, the dielectric structure being formed from a dielectric material, the dielectric material being different from one of the layers of insulation material; and a plurality of trenches formed in the layers of insulation material, each trench adjoining metal lines of the top patterned metal layer, a trench extending from the top metal layer between metal lines of the top metal layer through the top insulation layer and between metal lines of a metal layer lying below the top metal layer, each trench having a bottom surface, the trenches not including conductive material.