Patent ID: 7638404

Claim:
A method for forming a low temperature polysilicon thin film transistor with a low doped drain structure, comprising: forming a polysilicon island on a substrate; forming a dielectric layer, a metal layer and a cap layer in sequence to cover the polysilicon island, wherein the cap layer comprises silicon nitride (Si x N y ), silicon oxide (SiO z ), silicon oxynitride (SiO z N y ), or combinations thereof; forming a photo-resist patterned layer on the cap layer; removing a portion of the metal layer and a portion of the cap layer which are uncovered by the photo-resist patterned layer, so that the remaining metal layer is uncovered by the remaining cap layer with a predetermined distance at the same side, wherein the photo-resist patterned layer on the cap layer is not removed during the step of removing the portion of the metal layer and the portion of the cap layer; performing a high concentration ion-doping to form a heavily doped region in the portion of the polysilicon island uncovered by the remaining metal layer, wherein the metal layer is served as a mask in the step of performing a high concentration ion-doping; removing the portion of the remaining metal layer uncovered by the remaining cap layer to form a patterned metal layer, wherein a side of the remaining cap layer is substantially aligned with a side of the patterned metal layer at the same side; and performing a low concentration ion-doping using the patterned metal layer as a mask to form a low doped region in the portion of the polysilicon island.