Patent ID: 7447946

Claim:
A data processing apparatus comprising: a bus configured to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices; a master device configured to initiate a transaction, the transaction specifying a transaction address, the transaction address being an address in memory associated with a data value of the transaction; a cache interposed between the master device and the bus and configured to receive the transaction, the cache having a cache memory and a cache controller configured to control access to the cache memory, the cache controller comprising caching logic configured to selectively cache the data value of the transaction at a location in the cache memory chosen dependent on the transaction address so that the data value is subsequently accessible by the master device from the cache; control storage configured to identify a trace address range specifying a trace region; and trace logic configured to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range; the caching logic being configured to store the trace data at a location in the cache memory chosen dependent on the trace address for subsequent reference by an analysis tool used to analyze activities of the data processing apparatus.