Patent ID: 7696782

Claim:
An apparatus comprising: a plurality of fixed logic circuits, wherein at least a portion of the plurality of fixed logic circuits includes stages in a processing pipeline, wherein each of the plurality of fixed logic circuits is configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal, wherein a first (1st) number of input signals are selectable as input signals to a programmable logic core and a second (2nd) number of output signals are selectable to be produced by the programmable logic core instead of the combinational logic operations, and wherein the combinational logic operations are substantially fixed; the programmable logic core configured to receive a plurality of input signals, perform logic operations on the input signals, and produce at least one output signal, and wherein the logic operations are dynamically configurable; and a permutation network of switches configured to: dynamically route a selected subset of the first (1st) number of input signals of the plurality of fixed logic circuits as at least a portion of the inputs signals of the programmable logic core, dynamically route at least a portion of the output signals of the programmable logic core as a selected subset second (2nd) number of output signals of the plurality of fixed logic circuits; wherein the permutation network of switches includes: an input permutation network of switches including: a first (1st) number of inputs; and, a third (3rd) number of outputs; wherein the input permutation network of switches is configured to map of each of a portion of the first (1st) number of inputs to one of the third (3rd) number of outputs; and an output permutation network of switches including: a fourth (4th) number of inputs; and a second (2nd) number of outputs; wherein the output permutation network of switches is configured to map of each of the second (2nd) number of outputs to one of a subset of the fourth (4th) number of inputs.