Patent ID: 6975696

Claim:
A self test for a counter system in an integrated circuit comprising: a clock coupled to each counter in a plurality of counters; a first counter in the plurality of counters having a first counter output and a first counter rollover; a second counter in the plurality of counters having a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over; a comparison circuit having inputs coupled to the first and second counter outputs, wherein the comparison circuit compares the first and second counter outputs to produce a counter error output signal; and a latch coupled to the clock and having an input coupled to the counter error output signal, wherein the latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs, wherein an output of the latch is a latched counter error signal.