Patent ID: 8270221

Claim:
A nonvolatile memory device, comprising: a cell string configured to include a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and a number of memory cells coupled in series between the drain select transistor and the source select transistor; a latch unit configured to include a first latch and a second latch, the first latch storing a detection result of a threshold voltage of a second memory cell adjacent to a first memory cell selected from among the memory cells, and the second latch storing a detection result of a threshold voltage of the first memory cell; a bit line coupling unit configured to electrically couple the bit line and the latch unit together; and a first reset unit electrically coupled between the first and second latches and configured to reset the second latch, during a time in which a read operation is performed on the first memory cell, in response to a first reset signal and the detection result stored in the first latch.