Patent ID: 7388782

Claim:
A semiconductor integrated circuit device comprising: a memory cell array into which a nonvolatile semiconductor memory is integrated, and which includes a plurality of blocks; a storage unit which includes a block replacement information registration area with which it is possible to register block replacement information including address information of a defective block among said plurality of blocks, and a bad block information registration area with which it is possible to register bad block information including address information of a bad block; a block replacement information register group into which the block replacement information is set, the block replacement information register group being set in accordance with the block replacement information read out of the storage unit during a boot sequence; a bad block flag register group into which the bad block information is set, the bad block flag register group being set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence; a block redundancy judgment circuit which compares an inputted block address and the block replacement information set in the block replacement information register, and which can transfer an access destination to a redundant block serving as a replacement destination from the defective block when the defective block is accessed; a row decoder with a voltage restraining function which can restrain a voltage applied to a word line of the bad block in accordance with the bad block information set in the bad block flag register group when the bad block is accessed; a power supply detecting circuit which detects power-on; and a sequencer which executes a boot sequence after the power supply detecting circuit detects power-on.