Patent ID: 7411591

Claim:
An apparatus, comprising: a graphics memory switch coupled between a first graphics device and a root complex device, the graphics memory switch includes a first input to receive a first plurality of only contiguous virtual graphics memory addresses from the first graphics device connected to a first point-to-point, packet-based interconnect; a graphics address translator coupled to the first input to translate the first plurality of only contiguous virtual graphics memory addresses to a second plurality of non-contiguous physical memory addresses for use on a second point-to-point, packet-based interconnect to the root complex device; the graphics memory switch coupled between a second graphics device and the root complex device, the graphics memory switch includes a second input to receive a second plurality of only contiguous virtual graphics memory addresses from the second graphics device connected to a third point-to-point, packet-based interconnect; the graphics address translator coupled to the second input to translate the second plurality of only contiguous virtual graphics memory addresses to a second plurality of non-contiguous physical memory addresses for use on the second point-to-point, packet based interconnect to the root complex device; a single graphics memory page (GMP) driver comprising the graphics address translator and a graphics address remapping table driver to set up a graphics memory page table having the first plurality of only contiguous virtual graphics memory addresses contiguous with the second plurality of only contiguous virtual graphics memory addresses.