Patent ID: 7842968

Claim:
A diode formed integrally with a power integrated circuit on a substrate of a first conductivity type, comprising: a) an epitaxial layer of said first conductivity type formed on said substrate; b) a first region of a second conductivity type opposite said first conductivity type in said epitaxial layer separated from said substrate; c) a second region of said first conductivity type on above and contacting said first region such that a vertical parasitic transistor is formed spanning said epitaxial layer, said first region and said second region; d) a gate oxide on said epitaxial layer and a gate on said gate oxide; e) a channel region of said first conductivity type under said gate and which extends to a third region of said first conductivity type having a higher dopant concentration than said channel region; f) a fourth region of said second conductivity type contacting said channel region and said third region and is substantially aligned vertically with a first edge of said gate; said fourth region having a higher dopant concentration than said channel region; g) an anode terminal in contact with said gate, said third region, and said fourth region; h) a drift region of said second conductivity type extending from said channel region to a fifth region of said second conductivity type and a sixth region of said first conductivity type, said drift region having a lower dopant concentration than said fourth region, said fifth and sixth regions having higher dopant concentrations than said channel region; i) a cathode terminal in contact with said fifth and sixth regions; and j) a seventh region of said second conductivity type extending from said upper surface of said epitaxial layer downward to said first region which makes contact with said first and second regions and said third region, said seventh region having a higher dopant concentration than said first and second regions, said seventh region in contact with said anode terminal.