Patent ID: 8441841

Claim:
A semiconductor device comprising: a write word line; a read word line; a bit line; a source line; a signal line; a memory cell array including a plurality of memory cells; a first driver circuit; a second driver circuit; and a potential conversion circuit, wherein one of the plurality of memory cells comprises: a first transistor including a first gate, a first source, a first drain, and a first channel formation region; a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and a capacitor, wherein the first channel formation region comprises a semiconductor material containing silicon, and the second channel formation region comprises an oxide semiconductor material, wherein the first gate is electrically connected to one of two electrodes of the capacitor and one of the second source and the second drain, wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor, wherein the first driver circuit is electrically connected to one of the first drain and the first source through the bit line and electrically connected to the other of the second drain and the second source through the signal line, wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to the second gate through the write word line, and wherein the potential conversion circuit outputs a potential lower than a reference potential to the second driver circuit.