Patent ID: 7428568

Claim:
An apparatus comprising: a first output to provide a precharge value during a precharge phase and a true carry generate value during an evaluation phase; a second output to provide the precharge value during the precharge phase and the compliment of the true carry generate true during the evaluation phase; a current input; a first evaluation block connected to the current input and the second output and having a plurality of transistors, wherein a number of said transistors are connected in a parallel relationship and a number of said transistors are connected in a serial relationship, wherein the first evaluation block comprises a first transistor with a drain connected to the second output, a second transistor with a drain connected to the source of the first transistor and a source connected to the current input, a third transistor with a drain connected to the second output, a fourth transistor with a drain connected to the source of the third transistor and a source connected to the current input, and a fifth transistor with a drain connected to the second output and a source connected to the drain of the fourth transistor; and a second evaluation block connected to the current input and the first output and having a plurality of transistors, wherein the second evaluation block has the same number of transistors connected in a parallel relationship as the first evaluation block and the same number of transistors connected in a serial relationship as the first evaluation block.