Patent ID: 7203857

Claim:
A computing device comprising: a clock circuit for generating a first clock signal, a second clock signal, and a third clock signal; a first sub functional block (SFB) having an input port for receiving the first clock signal; a second sub functional block (SFB) having an input port for receiving the first clock signal; a first functional circuit block (FCB) including the first SFB and for operating in accordance with predetermined parameters, the first FCB having a clock control port for providing a copy of the first clock control signal, a first clock signal input port for receiving a switchably coupled second clock signal, a first FCB control input port and a first FCB control output port, the first FCB having a circuitry portion for operating in one of a normal mode of operation and in a reduced power consumption mode of operation in dependence upon the switchably coupled second clock signal; a second functional circuit block (FCB) including the second SFB and for operating in accordance with predetermined parameters, the second FCB having a second clock control port for providing a second clock control signal, a second clock signal input port for receiving a switchably coupled third clock signal, a second FCB control input port and a second FCB control output, the second FCB having a circuitry portion for operating in one of a normal mode of operation and in a reduced power consumption mode of operation in dependence upon the switchably coupled third clock signal; a first clock control circuit for receiving the second clock signal and for switchably coupling the second clock signal to the first clock signal input port in dependence upon the first clock control signal; and wherein a master-slave relationship is established by at least one of the first FCB control output port being coupled to the second FCB control input port for receiving a FCB control signal from the first FCB for enabling and disabling of the second FCB circuitry portion and the second FCB control output port being coupled to the first FCB control input port for receiving a FCB control signal from the second FCB for enabling and disabling of the first FCB circuitry portion.