Patent ID: 8232650

Claim:
A semiconductor device comprising: a chip region; a sealing ring region which surrounds the chip region in plan; and an outer region which surrounds an outer periphery of the sealing ring region in plan, the outer region comprising: a semiconductor substrate; a first laminate which is provided over the semiconductor substrate and includes a first interlayer dielectric film having a first dielectric constant; a second laminate which is provided over the first laminate and includes a second interlayer dielectric film having a second dielectric constant larger than the first dielectric constant; a plurality of first metal regions, the first metal region including a plurality of first metallic layers which are provided within the first laminate so as to mutually overlap in plan; and a plurality of second metal regions, the second metal region including a plurality of second metallic layers which are provided within the second laminate so as to mutually overlap in plan, the plurality of second metal regions are arranged in a row and column arrangement in plan comprising: at least four rows extending substantially parallel to an adjacent portion of the sealing ring region in plan, wherein a first row of the at least four rows is closest to the sealing ring region, a fourth row of the at least four rows is furthest from the sealing ring region, and second and third rows of the at least for rows are in between the first and fourth rows in plan, with the second row being closer to the first row and the third row being closer to the fourth row, and a plurality of columns extending from the first to the fourth row, wherein the columns are inclined relative to a line perpendicular to the adjacent portion of the sealing ring region.