Patent ID: 8773918

Claim:
A semiconductor memory device comprising: a memory cell; a pair of bit lines connected to the memory cell; a cell power line connected to the memory cell and having parasitic capacitors between the pair of bit lines; a first switch circuit which is connected to the pair of bit lines and a power voltage line; a second switch circuit which is connected to the cell power line and a write assist cell power line; and a write control circuit configured to control the pair of bit lines, the first switch circuit and the second switch circuit, wherein the write control circuit applies a first voltage of a high level to one bit line of the pair of bit lines and a second voltage of a low level being lower than the high level to the other bit line of the pair of bit lines, connects said one bit line to the power voltage line and disconnects said the other bit line from the power voltage line by the first switch circuit, and then connects the cell power line to the write assist cell power line by the second switch circuit, and wherein a voltage of the write assist cell power line is lower than the first voltage.