Patent ID: 7679418

Claim:
A Delay Locked Loop comprising: a voltage controlled delay line, said voltage controlled delay line including: a plurality of delay elements serially connected by a differential pair of delay lines; a bias voltage generator for providing a first bias voltage and a second bias voltage to each delay element of said plurality of delay elements; and a buffer, said buffer including: a voltage level shifting circuit, said voltage level shifting circuit including: an input circuit including a pair of input field effect transistors (FETs) of a first polarity, said input circuit receiving a differential input signal from said differential pair of delay lines and connected between a first supply voltage and a pair of output nodes, said differential input signal varying between an input high level and an input low level; and a load chain circuit including a pair of cross-coupled load chain FETs of a second polarity, respective gates of said pair of cross-coupled load chain FETs connected to respective nodes of said pair of output nodes, said load chain circuit receiving a reference voltage and including a pair of regulated current sources, said current sources regulated by said reference voltage, said load chain circuit connected directly between a second supply voltage and said pair of output nodes such that an output signal at said output nodes varies between an output high level and an output low level, where said output low level is shifted relative to said input low level; a reference voltage generator for receiving said first bias voltage and generating, based on said first bias voltage, said reference voltage received at said voltage level shifting circuit.