Patent ID: 8264903

Claim:
A memory module comprising: a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks; a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive, for a logical rank of the one or more logical ranks, a logical rank refresh command generated by the memory controller, the circuit configured to initiate, in response to the logical rank refresh command, a first refresh operation for one or more first physical ranks of the set of at least two physical ranks and a second refresh operation for one or more second physical ranks of the set of at least two physical ranks, wherein the second refresh operation is initiated after the first refresh operation; and a memory location storing a refresh time (tRFC) value based at least in part on a calculated maximum amount of time for refreshing the logical rank, wherein the tRFC value is accessible by the memory controller.