Patent ID: 7099976

Claim:
A bus arbiter for outputting a bus grant signal to a bus master granted access to a bus based on bus request signals and memory access addresses, each of which is output from respective M bus masters connected to the bus, the bus arbiter comprising; a bus request register file comprising M registers, each of the M registers for storing each of the memory access addresses output from a corresponding bus master; a bank register file comprising N registers, each of the N registers for storing a page index stored in a sense amplifier of a corresponding memory bank of an external memory device; and a comparing circuit comprising M comparators, each of the M comparators for comparing a page index stored in a register of the bank register file selected based on a corresponding memory access address with a page index stored in each of the M registers of the bus request register file and outputting a page HIT or page MISS to each of the M registers of the bus request register file according to the comparison result, wherein the bus arbiter preferentially grants a bus master causing the page HIT access to the bus.