Patent ID: 7642822

Claim:
An analog phase-locked loop arrangement, said analog phase-locked loop arrangement comprising: a) a phase detector for providing an error signal representative of the difference in phase between an input reference signal and an output signal of said analog phase-locked loop arrangement; b) a first selector for establishing a connection between said error signal and a first signal path when a first bandwidth parameter value is selected and for establishing a connection between said error signal and a second signal path when a second bandwidth parameter value is selected, wherein: i) said first signal path comprises: (1) a first first-signal-path integrator for integrating said error signal, thereby producing a first-signal-path integrated signal; (2) a second first-signal-path integrator for integrating said first-signal-path integrated signal, thereby producing a first-signal-path error-voltage signal; and (3) a first-signal-path voltage-controlled oscillator responsive to said first-signal-path error-voltage signal, thereby producing a first-signal-path output signal; and ii) said second signal path comprises: (1) a first second-signal-path integrator for integrating said error signal, thereby producing a second-signal-path integrated signal; (2) a second second-signal-path integrator for integrating said second-signal-path integrated signal, thereby producing a second-signal-path error-voltage signal; and (3) a second-signal-path voltage-controlled oscillator responsive to said second-signal-path error-voltage signal, thereby producing a second-signal-path output signal; c) a second selector for selecting said first-signal-path output signal as said output signal when said first bandwidth parameter value is selected and for selecting said second-signal-path output signal as said output signal when said second bandwidth parameter value is selected; and d) a feedback connection connecting said output signal to said phase detector.