Patent ID: 7843215

Claim:
A reconfigurable array to compute digital algorithms to operate on digital data comprising: an integrated circuit comprising: a plurality of data inputs; a plurality of data outputs; a plurality of programming inputs; a plurality of logic units arranged as a matrix array; said matrix array of logic units coupled to said data inputs and said data outputs; at least some of said logic units comprising a Boolean logic computational unit having input terminals, output terminals, and programming terminals, said programming terminals receiving a corresponding portion of said programming inputs, said computational unit being controlled by said portion of programming inputs such that digital signals at said output terminals have a predetermined Boolean combinatorial relationship to said digital signals, said logic units being operated on a clocked basis such that each said logic unit is controlled by said programming inputs; each of said logic units comprising a selector coupled to said input terminals and programmable to selectively couple input data from either said data inputs or output terminals of one or more other computational units to said computational unit; and an array of programmable interconnects interconnecting said data inputs of said matrix array and said output terminals of each of said logic units with input terminals of others of said logic units and to said data outputs of said matrix array; each of said logic units and each of said selectors and said array of programmable interconnects being operated on a clocked basis such that Boolean functionality is determined during each clock cycle.