Patent ID: 7917318

Claim:
A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a plurality of first design structure elements representing a plurality of pulse shaper elements, wherein the plurality of pulse shaper elements comprises a first input signal path and a second input signal path; a second design structure element representing a multiplexer coupled to the plurality of pulse shaper elements; a plurality of third design structure elements representing a plurality of dividers coupled to the multiplexer; and a fourth design structure element representing a controller coupled to the multiplexer, wherein the design structure is configured such that: the plurality of pulse shaper elements receive an input signal and shape a pulse of the input signal by introducing a predetermined delay τ, the multiplexer, based on control signals from the controller, selects pairs of outputs from one of the plurality of pulse shaper elements or the plurality of dividers for use in determining if one or more of the plurality of dividers fail, the controller determines a relationship of a duty cycle of the input signal to a 50% duty cycle based on the determined one or more of the plurality of dividers that fail, and the controller calculates a duty cycle of the input signal based on the determined relationship and an index of the one or more of the plurality of dividers that fail, wherein calculating the duty cycle of the input signal based on the determined relationship and the index of the one or more of the plurality of dividers that fail comprises either; calculating the duty cycle of the input signal using the following equation if the relationship of the duty cycle of the input signal to a 50% duty cycle is determined to be greater than the 50% duty cycle; Duty Cycle (in %)=50%*( n+i )/( n ) where n is a failure index for a divider in the first input path for a 50% duty cycle input signal, and n+i is the first index; or calculating the duty cycle of the input signal using the following equation if the relationship of the duty cycle of the input signal a 50% duty cycle is determined to be less than the 50% duty cycle; Duty Cycle (in %)=50%*( n′−i )/( n ′) where n′ is a failure index for a divider in the second input path for a 50% duty cycle input signal, and n′−i is the second index.