Patent ID: 7452803

Claim:
A method for fabricating a chip, comprising: providing a wafer comprising a silicon substrate, a MOS transistor in or on said silicon substrate, a metallization structure over said silicon substrate, wherein said metallization structure comprises a first thin-film circuit layer and a second thin-film circuit layer over said first thin-film circuit layer, a dielectric layer between said first and second thin-film circuit layers, a passivation layer over said metallization structure and over said dielectric layer; forming a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; forming a first metal layer on said polymer layer, wherein said forming said first metal layer comprising depositing an adhesion/barrier layer on said polymer layer and depositing a seed layer over said adhesion/barrier layer; forming a first pattern-defining layer over said seed layer, a first opening in said first pattern-defining layer exposing said seed layer; depositing a second metal layer over said seed layer exposed by said first opening; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; depositing a nickel layer over said third metal layer; forming a lead-free solder over said nickel layer, wherein said lead-free solder comprises tin and silver; after said depositing said third metal layer, removing said second pattern-defining layer; removing said first pattern-defining layer; and after said depositing said third metal layer, removing said first metal layer not under said second metal layer.