Patent ID: 7372767

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array having nonvolatile memory cells; a page buffer coupled to the memory array through first and second common bit lines and configured to map a set of first to third bit data to threshold voltage levels of a pair of first and second memory cells; and a row decoder configured to control a word line of a selected memory cell of the memory array, wherein the page buffer comprises: a switch configured to connect the first common bit line to the second common bit line; a first latch block configured to store a first latch data, the first latch block connected to the first common bit line through a first sensing node; a second latch block configured to store a second latch data, the second latch block connected to the second common bit line through a second sensing node; a dumping block configured to control a voltage level of the second sensing node according to the first latch data, and to flip the first latch data of the first latch block according to the voltage level of the second sensing node; and an output block configured to output data according to the second latch data to an internal data line.