Patent ID: 7399679

Claim:
A method to improve the threshold voltage (Vt) roll-off in an NMOS transistor that includes a shallow trench isolation feature, comprising: (a) providing a substrate having an active area where an NMOS transistor will be built; (b) forming trenches in said substrate wherein the shallow trenches separate active areas in said substrate; (c) forming a liner on the surface of said substrate and on the sidewalls and bottom of said shallow trenches; (d) forming a plug in said shallow trenches; said plug is recessed below the top of said substrate; (e) performing an angled indium implant through said shallow trenches into the substrate adjacent to top corners of the trenches; (f) removing said plug and depositing an insulator layer to fill said shallow trenches; (g) planarizing said insulator layer; and (h) forming a gate dielectric layer on said substrate and forming a patterned gate layer over said gate dielectric layer and over said insulator layer.