Patent ID: 7594056

Claim:
A PCI bridge which connects between a primary bus and a secondary bus, comprising: a PCI-to-PCI bridge unit for transferring a transaction between the primary bus and the secondary bus; a DMA accelerator; an arbiter including a first queue for said PCI-to-PCI bridge unit and a second queue for said DMA accelerator to control output from said PCI-to-PCI bridge unit and said DMA accelerator to the primary bus; and a configuration register for storing information including a device identifier, which is common to said PCI-to-PCI bridge unit and said DMA accelerator, to cause said PCI-to-PCI bridge unit and said DMA accelerator to operate as one device on a bus, wherein said DMA accelerator comprises: descriptor reading means for reading out a descriptor from a primary memory of the primary bus; status reading means for reading out a status from a secondary memory of the secondary bus; status writing means for writing, into the primary memory of the primary bus, the status read out by said status reading means, in accordance with the descriptor; and flag writing means for writing, into the primary memory of the primary bus, a flag indicating completion of the write of the status read out by said status reading means.