Patent ID: 7975131

Claim:
A data processing system comprising an embedded processor, the system having: the processor, wherein the processor has a native instruction set, the instruction set having first and second unique sets of different instructions; and internal circuitry, situated within the processor, to enable the processor to execute any instruction within the second set of instructions; such that, in response to the circuitry, the processor exhibits: a first operational mode through which the processor unconditionally provides, as a default mode, a first functionality to the system by only using the first set of instructions, wherein during the first operational mode the circuitry prevents the processor from executing any of the instructions in the second set of instructions; and a second operational mode, wherein the processor conditionally provides a second functionality to the system by using both the first and second sets of instructions, the processor assumes the second operational mode in response to a predefined control code being supplied to the processor, from a source external to the processor, such that the circuitry, acting in response to the code, enables the processor to execute any of the instructions in the second set of instructions as a result of which the processor is then able to execute any instruction in both the first and second sets of instructions.