Patent ID: 8527925

Claim:
A method for estimating a clock skew, comprising: obtaining a basic clock skew of at least one clock tree in a circuit; judging whether a first logic unit and a second logic unit in the circuit are in a same clock domain; in response to that the first logic unit and the second logic unit are in different clock domains, using a computer in estimating the clock skew between the first logic unit and the second logic unit as a larger one of basic clock skews of clock trees to which the first logic unit and the second logic unit are respectively corresponding; in response to that the first logic unit and the second logic unit are in the same clock domain, further judging whether the first logic unit and the second logic unit are in a same hierarchical logic block; in response to that the first logic unit and the second logic unit are in different hierarchical logic blocks, using a computer in estimating the clock skew between the first logic unit and the second logic unit as the basic clock skew of a clock tree common to the first logic unit and the second logic unit plus an additional clock skew caused by the different hierarchical logic blocks, wherein the first logic unit locates in a logic block of top hierarchy, and the second logic unit locates in a logic block that is n hierarchies distant from the logic block of top hierarchy, said additional clock skew caused by the different hierarchical logic blocks is a clock skew caused by the hierarchy difference between the second logic unit and the logic block of top hierarchy and wherein formula CLK=Σ i=1 n CL i is used to calculate the clock skews caused by the hierarchy difference between the logic units and the top hierarchy, wherein CL i is a clock delay caused by a clock path from the ith hierarchy logic block to the (i+1)th hierarchy logic block.