Patent ID: 8470674

Claim:
A structure, comprising: two or more first regions of an integrated circuit, each first region of said two or more first regions having a multiplicity of n-channel field effect transistors (FETs) and a multiplicity of p-channel FETs, each first region of said two or more first regions having more n-channel field effect transistors (NFETs) than p-channel field effect transistors (PFETs) or having more PFETs than NFETs; a first stressed layer over NFETs of each first region of said two or more first regions, said first stressed layer of a first stress type; a second stressed layer over PFETs of each first region of said two or more first regions, said second stressed layer of a second stress type, said second stress type opposite from said first stress type; one or more second regions of said integrated circuit, each second region of said one or more second regions not containing FETs, each second region of said one or more second regions between at least two first regions of said two or more first regions; and wherein each second region of said one or more second regions contains first sub-regions of said first stressed layer and second sub-regions of said second stressed layer, an area of said first sub-region greater than an area of said second sub-region or wherein each second region of said one or more second regions contains first sub-regions of said first stressed layer and second sub-regions of said second stressed layer, an area of said second sub-region greater than an area of said first sub-region.