Patent ID: 7149947

Claim:
A method for operating a memory system comprising: A. receiving a digital word having N bits of data and M bits for error detection; B. generating a first error correction code based on the N bits of data of the digital word; C. generating a second error correction code based on the N bits of data of the digital word; D. performing a first logic operation on the first error correction code and the second error correction code to generate a data signature representative of a comparison of the first error correction code and the second error correction code; E. performing a second logic operation on the data signature and the M bits of the digital word to generate a constant signal representing a comparison of the data signature and the M bits of the digital word; F. comparing the generated constant signal to a predetermined constant signal to determine if an error has occurred in at least one of the N bits of data in the digital word, the M bits of data in the digital word, the first error correction code and the second error correction code; and G. determining that an error has occurred in the N bits of data in the digital word, the M bits of data in the digital word, the first error correction code or the second error correction code if the generated constant signal is different from the predetermined constant signal.