Patent ID: 8110467

Claim:
A method for fabricating a FET device, comprising the steps of: patterning a plurality of fins in a silicon-on-insulator (SOI) layer each fin having a first side and a second side opposite the first side; forming a dielectric layer over each of the fins; forming a gate that surrounds at least a portion of each of the fins and is separated from the fins by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate such that a portion of the gate adjacent to the first side of each of the fins is configured to have a threshold voltage Vt 1 and a portion of the gate adjacent to the second side of each of the fins is configured to have a threshold voltage Vt 2 , wherein Vt 2 is different from Vt 1 due to the at least one band edge metal being present in the portion of the Rate adjacent to the second side of each of the fins, and wherein the step of forming the gate further comprises the steps of: depositing a first metal layer over the dielectric layer; and selectively depositing a series of second metal layers over portions of the first metal layer at the second side of each fin; and forming a source region and a drain region interconnected by the fins.