Patent ID: 8829646

Claim:
A memory device, comprising: an integrated circuit substrate including an array of access devices; a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers; an array of electrode pillars extending through and surrounded by the plurality of conductive layers, the electrode pillars in the array contacting corresponding access devices in the array of access devices, and defining interface regions between the electrode pillars and conductive layers in the plurality of conductive layers; and memory elements in the interface regions, each of said memory elements comprising a programmable element and a rectifier, the rectifier comprising first and second rectifier elements having first and second conductivity types on opposite sides of the programmable element; row decoding circuits and column decoding circuits coupled to the array of access devices arranged to select an electrode pillar in the array of electrode pillars; and plane decoding circuits coupled to the plurality of conductive layers arranged to forward bias the rectifiers in the interface regions in a selected conductive layer and to reverse bias the rectifiers in interface regions in a non-selected conductive layer.