Patent ID: 7411848

Claim:
A method of testing an integrated circuit having a plurality of memory elements, comprising: dividing the plurality of memory elements into a plurality of memory banks having a first specified number of rows and columns of memory elements; dividing each one of the plurality of memory banks into a plurality of memory blocks having a second specified number of rows and columns of memory elements; dividing each one of the plurality of memory blocks into a plurality of memory pages having a third specified number of rows and columns of memory elements; providing each one of the plurality of memory banks with one of the plurality of memory pages enabled for use as a cache memory; simultaneously storing a specified pattern of binary ones and zeroes into a selected one of the plurality of memory pages, and into the cache memory, of each individual one of the plurality of memory banks; comparing the stored pattern in the selected memory block to the stored pattern in the cache memory, and storing a value for each individual one of the plurality of memory pages indicating at least the presence and location of a difference, and measuring a writing time period for that memory page; and determining whether the stored value indicates one of a row, a column or a page failure and storing a redundant memory address to replace the failure using the cache memory as a source of redundant memory cells.