Patent ID: 8270201

Claim:
A semiconductor memory device, comprising: a memory cell array having memory cells disposed at intersections of a plurality of first lines and a plurality of second lines, each of the memory cells being configured by a rectifier and a variable resistor connected in series; and a control circuit configured to apply a first voltage to a selected one of the first lines and to apply a second voltage having a voltage value smaller than that of the first voltage to a selected one of the second lines, such that a certain potential difference is applied to a selected one of the memory cells disposed at the intersection of the selected one of the first lines and the selected one of the second lines, the control circuit comprising: a current mirror circuit configured to produce a mirror current having a current value identical to that of a cell current flowing in the selected one of the memory cells; a reference current generating circuit configured to produce a reference current, the reference current having a current value that differs from the current value of the mirror current by a certain current value, and having a timing of change that is delayed compared with that of the mirror current; and a detecting circuit configured to detect transition of a resistance state of the selected one of the memory cells based on a magnitude relation of the mirror current and the reference current, the control circuit suspending voltage application to the selected one of the first lines and the selected one of the second lines based on a detection result of the detecting circuit.