Patent ID: 7348673

Claim:
A semiconductor device comprising: a semiconductor substrate; a minute wiring structure portion provided on said semiconductor substrate and including one or more first wiring layers and one or more first insulating layers, in which each of said first wiring layers and each of said first insulating layers are alternately laminated, and each of said first wiring layers has one or more first wires and a first insulating film for insulating said first wire; a first huge wiring structure portion provided on said minute wiring structure portion and including one or more second wiring layers and one or more second insulating layers, in which each of said second wiring layers and each of said second insulating layers are alternately laminated, each of said second wiring layers has a thickness which is twice or more the thickness of said first wiring layer and has one or more second wires and a second insulating film for insulating said second wire, and each of said second insulating layers is thicker than said first insulating layer; and a second huge wiring structure portion provided on said first huge wiring structure portion and including one or more third wiring layers and one or more third insulating layers, in which each of said third wiring layers and each of said third insulating layers are alternately laminated, each of said third wiring layers has a thickness which is twice or more the thickness of said first wiring layer and has one or more third wires and a third insulating film for insulating said third wires, and each of said third insulating layers is thicker than said first insulating layer and has the elastic modulus at 25° C. not more than the elastic modulus at 25° C. of the second insulating layer, wherein the elastic modulus at 25° C. of the third insulating layers is set to 0.15 to 3 GPa.