Patent ID: 6858889

Claim:
The product produced by a process for forming a two plated capacitor in a semiconductor device comprising the steps of: (a) forming a first insulating layer on the semiconductor device, (b) forming a trench defined by an interior surface in the insulating layer, (c) forming a first low resistance metal layer covering the interior surface of the trench, (d) forming a first polysilicon layer over the first low resistance metal layer, (e) forming a dielectric layer over the first polysilicon layer, (f) forming a second polysilicon layer over the first dielectric layer, (g) forming a second low resistance metal layer over the second polysilicon layer until the trench is filled, (h) planarizing the semiconductor device to form a planarized surface wherein the first and second low resistance metal layers are exposed at the planarized surface, and (i) forming capacitor leads to the first and second low resistance metal layers.