Patent ID: 7741171

Claim:
A method of forming an integrated circuit structure, the method comprising: providing a semiconductor substrate; forming a transistor at a top surface of the semiconductor substrate comprising; forming a gate stack on the semiconductor substrate; forming a gate spacer on a sidewall of the gate stack; forming a source/drain region adjacent the gate stack; and forming a source/drain suicide region on the source/drain region; providing ionized ozone to activate exposed surfaces of the source/drain suicide region and the gate spacer; after the step of providing ionized ozone to activate exposed surfaces, blanket forming an initial layer on the exposed surfaces using process gases comprising a first oxygen-containing gas and a first tetraethoxysilane (TEOS), wherein a flow rate of the first oxygen-containing gas and a flow rate of the first TEOS have a first ratio of greater than about 8; forming a buffer layer on the initial layer using process gases comprising a second oxygen-containing gas and a second TEOS, wherein a flow rate of the second oxygen-containing gas and a flow rate of the second TEOS have a second ratio of less than about 3; and forming an inter-layer dielectric (ILD) layer comprising boronphosphosilicate glass (BPSG), wherein the buffer layer is between and adjoining the initial layer and the ILD layer.