Patent ID: 8644053

Claim:
A memory device comprising: a data writing circuit; and a plurality of memory cells, each memory cell including: a first thin film adjustable resistor; a second thin film adjustable resistor; a first thin film heating element adjacent the first thin film adjustable resistor and coupled to the data writing circuit, the first thin film heating element configured to alter the resistance of the first thin film adjustable resistor by heating the first thin film adjustable resistor; a second thin film heating element adjacent the second thin film adjustable resistor and coupled to the data writing circuit, the second thin film heating element configured to alter the resistance of the second thin film adjustable resistor by heating the second thin film adjustable resistor; and a dielectric layer separating the first thin film heating element from the first thin film adjustable resistor and separating the second thin film heating element from the second thin film adjustable resistor.