Patent ID: 6853224

Claim:
A method for reducing cycle slips in a frequency synthesizer, the frequency synthesizer comprising a voltage controlled oscillator for generating an output signal frequency, a divider for dividing said output signal into a signal pulse to be compared, a reference oscillator for generating a reference signal pulse and means for generating control voltage for the voltage controlled oscillator in response to a detected phase difference, which phase difference is the phase difference between the signal pulse to be compared and the reference signal pulse, and the method comprising the steps of receiving a first first-type signal pulse, the first-type signal pulse being either said reference signal pulse or said signal pulse to be compared, receiving a second second-type signal pulse, the second-type signal pulse being either said reference signal pulse or said signal pulse to be compared but of a different type than said first signal pulse, generating control voltage for controlling the voltage controlled oscillator in response to a phase difference between said first signal pulse and said second signal pulse, the magnitude of the phase difference being within the range of 0 to 2π, increasing the control voltage for a degree of constant voltage on receiving a third signal pulse of the first type before said second signal pulse, wherein in the method, reducing said control voltage for a degree of said constant voltage on receiving a fifth signal pulse of said second type after reception of the second signal pulse and before reception of a fourth signal pulse of the first type.