Patent ID: 6965262

Claim:
A multi-phased receiver system comprising: a set of receivers coupled to a same interface pin, each receiver configured to receive an input signal from the interface pin, the input signal comprising a stream of input symbols, each input symbol having a symbol cycle time, the set of receivers configured to be sequentially activated by a set of timing signals so as to receive respective input symbols during a sequence of symbol cycles, such that each receiver determines a logic signal representing a state of its respective input symbol during a respective symbol cycle of the sequence of symbol cycles in response to the timing signals, and the set of receivers outputs the logic signal representing the state of one of the input symbols during each symbol cycle time; wherein the receivers are integrating receivers; the set of timing signals include a start integration timing event, an end integration timing event and a sensing timing event for each integrating receiver, and each integrating receiver includes: an integrator configured to accumulate charge to produce an output voltage in accordance with the input signal during an integration time interval defined by its respective start integration timing event and end integration timing event; and a sense amplifier configured to sample and convert the output voltage from the integrator into the logic signal in response to its respective sensing timing event substantially concurrent with the respective end integration timing event.