Patent ID: 6992391

Claim:
An integrated circuit comprising: a first interlayer dielectric (ILD) consisting of only a first dielectric material, the first material having a first etchant rate when exposed to a first etchant, wherein the first ILD includes a first conductor and an underlying first via both entirely inlaid in the first dielectric material; a second ILD consisting of only a second dielectric material disposed directly on the first ILD, the second dielectric material having an etchant rate slower than the first etchant rate when exposed to the first etchant, wherein the second ILD includes a second conductor and an underlying second via both entirely inlaid in the second dilectric such that the interface between the first and second ILDs is of dielectric materials having different etch rates; a third ILD disposed directly on the second ILD consisting of only the first dielectric material, wherein the third ILD includes a third conductor and an underlying third via entirely inlaid in the third ILD consisting of the first dielectric material.