Patent ID: 7125805

Claim:
A semiconductor fabrication process comprising: forming a gate electrode overlying a substrate; forming an oxide liner on sidewalls of the gate electrode; forming an offset spacer of silicon nitride adjacent the oxide liner; forming an intermediate liner of silicon oxide adjacent the offset spacer; forming a disposable spacer of silicon nitride adjacent the intermediate liner; forming an elevated source/drain overlying the substrate and displaced laterally from sidewalls of the gate electrode by the disposable spacer; following forming the elevated source/drain removing the intermediate oxide liner and the disposable spacer to expose the upper surface of the substrate and implanting halo and extension implants into the exposed substrate; following performing the halo and extension implants, forming a replacement intermediate oxide liner and a replacement spacer located substantially where the original intermediate oxide liner and disposable spacer were located; and forming an antireflective coating (ARC) of silicon nitride overlying the gate electrode.