Patent ID: 8048739

Claim:
A method of manufacturing a flash memory device, the method comprising: sequentially forming a tunnel oxide film and a first polysilicon layer on an upper surface of a semiconductor substrate, and forming an isolation structure at a predetermined region on the semiconductor substrate, the upper surface of the semiconductor substrate having a first height; forming a second polysilicon layer over the first polysilicon layer and the isolation structure; patterning the second polysilicon layer so that the second polysilicon layer remains over the first polysilicon layer and partially overlaps with the isolation structure, wherein while the second polysilicon layer is over-etched, the isolation structure is partially etched to form a recess having a first depth in a center portion of the isolation structure, the first depth corresponding to a second height that is higher than the first height; exposing a top surface of the patterned second polysilicon layer; simultaneously etching an exposed side surface of the patterned second polysilicon layer, the exposed top surface of the patterned second polysilicon layer, and the recess of the isolation structure to extend the first depth of the recess to a second depth, the second depth corresponding to a third height that is equal to or lower than the first height; and forming a dielectric layer and a third polysilicon layer over the isolation structure including the recess having the second depth and the second polysilicon layer, the third polysilicon layer filling the recess and extending at least to an adjacent isolation structure.