Patent ID: 6870772

Claim:
A nonvolatile semiconductor memory device formed on a surface of a semiconductor substrate, comprising: a memory transistor having a floating gate and a control gate successively formed above a first well region of said semiconductor substrate, having its threshold voltage set to a first voltage for storing a data signal at a first logic level, and having its threshold voltage set to a second voltage level for storing a data signal at a second logic level; a reference transistor having a floating gate and a control gate successively formed above a second well region of said semiconductor substrate, and having its threshold voltage set to a reference voltage between said first and second voltages; a read circuit reading the threshold voltages of said memory transistor and said reference transistor; a comparison circuit comparing the threshold voltage of said memory transistor read by said read circuit with the threshold voltage of said reference transistor read by said read circuit and outputting a pulse waveform instruction signal based on a comparison result; and a data signal rewriting circuit supplying a pulse signal train having a pulse waveform in accordance with said pulse waveform instruction signal between the control gate of said memory transistor and said first well region and changing the threshold voltage of said memory transistor from said first voltage to said second voltage.