Patent ID: 8018463

Claim:
A system for processing video data, comprising: a reconfigurable digital video processor configured to perform motion estimation on a sequence of frames, wherein performing motion estimation includes comparing a block of picture elements (PELs) associated with a current frame with a block of PELs associated with a frame before the current frame or with a block of PELs associated with a frame subsequent to the current frame to identify the block of PELs with the lowest distortion, the comparison including performing a plurality of sum of absolute differences (SAD) operations, wherein the reconfigurable digital video processor includes heterogeneous processing nodes connected by a matrix interconnect network; a control processor configured to provide instructions to the reconfigurable digital video processor that dynamically configure the heterogeneous processing nodes and the matrix interconnect network included in the reconfigurable digital video processor to receive input video data associated with a first format and to generate output video data associated with a second format, wherein the instructions include information related to the first format associated with the input video data and the second format associated with the output video data, wherein the instructions include information related to both the first format and a first resolution of the input video data as well as the second format and a second resolution of the output video data, and wherein the instructions further include degree of compression information; and a plurality of memories for storing the blocks of PELs associated with each frame to enable multiple SAD operations to be performed during each clock cycle, wherein the plurality of memories includes eight node memories that allow for sixteen SAD operations to be performed during each clock cycle, wherein the eight node memories are configured to enable double buffering for overlapping data input and results output, wherein the reconfigurable digital video processor is further configured to evaluate each block of PELs by pixel positions, one at a time, performing SAD operations every clock period, each of the evaluations including calculating the SAD metric between a first block of PELs and a second block of PELs, wherein the second block of PELs is included in a larger reference block of which the first block of PELs is a part, and saving a best distortion metric and an origin of the second block of PELs associated with the best distortion metric.