Patent ID: 7795673

Claim:
A vertical non-volatile memory, comprising: a substrate; a plurality of strips of active stacked structures disposed on the substrate in parallel to a first direction, wherein each of the active stacked structures comprises: a first semiconductor layer disposed on the substrate and having a first conductive state; a second semiconductor layer disposed on the first semiconductor layer and having a second conductive state; a third semiconductor layer disposed on the second semiconductor layer and having the first conductive state; a first dopant barrier disposed between the first semiconductor layer and the second semiconductor layer; and a second dopant barrier disposed between the second semiconductor layer and the third semiconductor layer; a plurality of word lines arranged in parallel to a second direction, wherein each of the word lines crosses the active stacked structures and fills spaces among the active stacked structures; and a storage structure disposed between the word lines and the active stacked structures and conformally disposed on the active stacked structures and the substrate, wherein the first semiconductor layers of the active stacked structures are not mutually electrically connected.