Patent ID: 7129861

Claim:
A method for implementing an L:M Fractional Sample Rate Converter (F-SRC), for controlled and direct insertion and cancellation of samples in a processed data stream, the method comprising: receiving an input data stream (DATA_IN) by an input block, processing L signal samples (x(m)) having an input data rate (f IN ), in a predetermined time interval (T s ); generating an interpolated data stream (DATA_IN 1 ), upsampled times a factor P (P<M), with the input block providing signal samples (x 1 (h)) having a data rate Pf IN ; generating an intermediate data stream (DATA_IMD 1 ) with a rate adapting stage receiving the signal samples from the input block, and providing signal samples (y 1 (k)) adapted to an intermediate data rate (Pf OUT )); delivering an output data stream (DATA_OUT) with a low pass and P:1 decimation filter receiving the signal samples from the rate adapting stage, including M signal samples, z(k), having a desired output sample rate (f OUT =M/T s ); adapting the input data rate in the rate adapting stage to the output data rate by a direct insertion of repeated samples into the interpolated stream (DATA_IN 1 ) when L<M, and by a direct cancellation of samples when L>M, thus generating a provisional intermediate stream DATA_DTY of samples w 2 (k) that are already adapted to an intermediate output rate Pf OUT , although being affected by aliases falling within an output Nyquist band [−f OUT /2, f OUT /2]; and generating the intermediate stream (DATA_IMD 1 ) in the rate adapting stage by weighting the signal samples (w 2 (k)) of the provisional intermediate data stream (DATA_DTY) to suppress aliases from the output Nyquist band [−f OUT /2, f OUT /2].