Patent ID: 8704339

Claim:
A semiconductor device comprising: a first chip including: a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the plurality of second external terminals are arranged based upon the first size, a plurality of circuits formed adjacent to the external terminal area, the plurality of circuits corresponding to the plurality of second external terminals, and a plurality of wires connecting between the plurality of second external terminals and the plurality of circuits, wherein the plurality of second external terminals and the plurality of wires connected to the plurality of second external terminals constitute a plurality of interfaces, each of the plurality of interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the plurality of wires have the same time constant, and at least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.