Patent ID: 7522452

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array comprising a plurality of memory cells enabled to store multi-value data, the memory cells being arranged along a plurality of bit-lines and a plurality of word-lines; a bit-line control circuit including data storage circuits connected to the bit-lines and each storing one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines; a word-line control circuit controlling word-line voltages applied to the word-lines; and a control circuit controlling the word-line control circuit and the bit-line control circuits according to a control signal from outside, the control circuit being able to perform a mode in which, all or specific memory cells in a fault block are written so that all or specific memory cells in the fault block have a threshold voltages higher than a first voltage applied to a selected word line when reading a first page of the sets of page data.