Patent ID: 7799604

Claim:
A manufacturing method of a semiconductor device, comprising: a) forming a multi-layer wiring on a first surface of a support body; b) forming a multi-layer dielectric on a second surface of the support body, wherein the second surface is situated at a side opposite to the first surface; c) forming a first opening part exposing the second surface of the support body by piercing the multi-layer dielectric; d) forming a second opening part connecting to the first opening part and piercing the support body by using the pierced multi-layer dielectric as mask; and e) solder-connecting a semiconductor chip to a top surface of the multi-layer wiring in the second opening part; wherein the step e) includes the processes of f) forming a pad for connecting to the semiconductor chip on the first surface of the support body; g) forming a first dielectric layer covering the pad and then on the first dielectric layer reciprocally stacking a wiring layer and a dielectric layer in an alternating manner to form the multi-layer wiring on the first surface of the support body; and h) forming an electrode pad at a bottom surface of the multi-layer wiring; and wherein the step b) includes a process of i) stacking a plurality of second dielectric layers on the second surface of the support body to form the multi-layer dielectric.