Patent ID: 7463540

Claim:
A nonvolatile semiconductor memory comprising: a first memory cell array having first memory cell units, each of the first memory cell units having first memory cells and first select transistors sandwiching the first memory cells, wherein the first memory cells and the first select transistors are connected in series and each of the first memory cells has a stacked gate structure having a floating gate and a control gate; a second memory cell array having second memory cell units, each of the second memory cell units having a second memory cell and second select transistors sandwiching the second memory cell, wherein the second memory cell and the second select transistors are connected in series and the second memory cell has a stacked gate structure having a floating gate and a control gate; first bit lines connected to the first memory cell units; second bit lines connected to the second memory cell units; a first sense amplifier provided on one side of the first memory cell array and connected to the first bit lines; and a second sense amplifier provided on one side of the second memory cell array and connected to the second bit lines.