Patent ID: 8254171

Claim:
A nonvolatile semiconductor memory comprising: a first memory bank comprising a plurality of electrically writable and readable memory cells; a second memory bank comprising a plurality of electrically writable and readable memory cells; a first port to which a first control signal is serially inputted; a second port to which a second control signal is serially inputted; a mode change terminal to which a mode change signal is inputted; and a control circuit selecting a first mode in which an access to the first memory bank is enabled in response to the first control signal and an access to the second memory bank is enabled in response to the second control signal when the mode change signal is at a first level and selecting a second mode in which the access to the first memory bank and the access to the second memory bank are enabled in response to the first control signal when the mode change signal is at a second level, wherein in the second mode, the first control signal is modified to address both the first memory bank and the second memory bank as one memory.