Patent ID: 7957204

Claim:
A non-volatile memory device comprising: an array of non-volatile memory cells including a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells; logic to cause the array of non-volatile memory cells to be programmed as a programming window that includes a number of bits, the programming window being divided into a plurality of sub-windows, where, when causing the array of non-volatile memory cells to be programmed, the logic is to: determine whether first bits, of bits included in a sub-window, of the plurality of sub-windows, to be programmed correspond to a majority of the bits included in the sub-window, determine that second, different bits, of the bits included in the sub-window, are to be programmed when the first bits correspond to the majority of bits, each bit of the second bits being different than each bit of the first bits, the first bits not being programmed when the first bits correspond to the majority of the bits, and determine that a configuration bit, of the bits included in the sub-window, is to be programmed when the first bits correspond to the majority of the bits, the configuration bit indicating that the second bits are to be programmed; a voltage supply generator to generate a programming voltage for programming the plurality of the memory cells, the voltage supply generator including a plurality of charge pump groups, where the plurality of the memory cells are programmed by writing at least one of the plurality of sub-windows to the plurality of the memory cells, the at least one of the plurality of sub-windows including the sub-window, where each of the plurality of charge pump groups includes a plurality of independent charge pumps, and where a particular number of the plurality of charge pump groups are activated based on a number of the second bits and the configuration bit when the first bits correspond to the majority of bits; and select switches, connected to the voltage supply generator, to control application of a voltage from the voltage supply generator to the plurality of bit lines when writing the at least one of the plurality of sub-windows to the plurality of the memory cells.