Patent ID: 8039326

Claim:
A method for fabricating a bulk FinFET device having deep trench isolation comprising the steps of: forming one or more deep isolation trenches in a bulk silicon wafer; depositing a mandrel-forming material on the bulk silicon wafer, the mandrel-forming material also substantially filling the one or more deep isolation trenches as filler material, wherein the mandrel-forming material comprises at least one of amorphous and polycrystalline silicon; fabricating a plurality of mandrels from the mandrel-forming material and overetching the mandrel-forming material at an upper end of the one or more deep isolation trenches to form a recess; depositing a sidewall spacer material overlying the plurality of mandrels and into the recess to form a spacer therein; fabricating sidewall spacers from the sidewall spacer material, the sidewall spacers adjacent sidewalls of the plurality of mandrels; removing the plurality of mandrels using the spacer as an etch stop; etching the bulk silicon wafer to form a plurality of fin structures therefrom using the sidewall spacers as an etch mask.