Patent ID: 7358564

Claim:
A semiconductor device, comprising: a semiconductor substrate having an upper surface and a lower surface; a semiconductor layer formed on said upper surface of said semiconductor substrate; a base region of a first conduction type formed in said semiconductor layer; a source region of a second conduction type formed in said base region; a drain region of said second conduction type formed apart from said source region in said semiconductor layer; a gate electrode formed on a gate insulator above said semiconductor layer between said source region and said drain region; a first interlayer insulator formed on said semiconductor layer to cover said gate electrode; a short electrode formed to short said base region and said source region; a second interlayer insulator formed to cover said first interlayer insulator and said short electrode; a drain electrode formed over said second interlayer insulator and connected to said drain region with the use of a contact hole formed through said first and second interlayer insulators; and a source electrode formed on said lower surface of said semiconductor substrate, wherein said short electrode extends over said first interlayer insulator from said source region toward said drain region such that a side of said short electrode at least coincides with a side of said gate electrode located toward said drain region with respect to positions in a direction defined as directing from said source region toward said drain region.