Patent ID: 7986557

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of nonvolatile memory cells provided corresponding to intersections between the word lines and the bit lines, and configured to electrically store data; sense amplifiers configured to detect data of the memory cells, or to drive the bit lines in order to write data into the memory cells; a column decoder configured to select a certain bit line from the bit lines for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line from the word lines; a charge pump configured to supply power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit configured to control the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells from which data is to be read or into which data is to be written; a first power source input configured to apply a voltage to the logic circuit; and a second power source input configured to apply a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.