Patent ID: 7701840

Claim:
A multiplex switching circuit comprising: means for unifying bit widths of packets supplied from a plurality of input channels to a previously set bit width; means for establishing a synchronization among the plurality of input channels that the packets are input into, after the bit widths have been unified; means for spreading the synchronized packets by multiplying said packets by orthogonal codes corresponding to the input channels; means for multiplexing the spread packets; means for multiplying the multiplexed packets by an orthogonal code for switching corresponding to an input channel on which a packet delivered to an output channel has been supplied and as a result the input packet is reconstructed; and means for delivering the reconstructed packet to the output channel, wherein said previously set bit width comprises a bit width of at least a size of a largest packet that can be input from said plurality of input channels, and if an input packet is smaller than said previously set bit width, then residual bits of said unified bit width packets are left empty.