Patent ID: 8518768

Claim:
A method of manufacturing a CMOS device comprising: forming a PMOS transistor on a substrate, the PMOS transistor having a first quantum well structure; forming an NMOS transistor on the substrate, the NMOS transistor having a second quantum well structure; and forming an isolation layer between the PMOS transistor and the NMOS transistor, further comprising: forming a first buffer layer on first portions of the substrate; forming a first bottom barrier layer on the first buffer layer; forming a first quantum well layer on the first bottom barrier layer; forming a first top barrier layer on first quantum well layer; forming a nucleation layer on second portions of the substrate; forming a second buffer layer on the nucleation layer; forming a second bottom barrier layer on the second buffer layer; forming a second quantum well layer on the second bottom barrier layer; and forming a second top barrier layer on the second quantum well layer.