Patent ID: 7579882

Claim:
An electronic device using a three-state output buffer circuit, wherein the output buffer circuit comprises: an input circuit configured to output a first control signal and a second control signal, based on an output enable signal and an input signal; a voltage generating circuit configured to generate and output a predetermined reference voltage based upon the first control signal and a power voltage from a terminal of a positive source power voltage; and an output circuit configured to generate one of an output signal and a specific state to an output terminal of the output buffer circuit, based on the predetermined reference voltage and the second control signal, wherein the output circuit comprises: a first transistor configured to receive the predetermined reference voltage through a gate thereof from the voltage generating circuit and the power voltage from the terminal of the positive source power voltage through a substrate gate thereof, and to flow electric current to the output terminal; a second transistor connected between the first transistor and the output terminal, and configured to receive a constant voltage through a gate thereof from a constant voltage source; a third transistor configured to receive the second control signal through a gate thereof from the input circuit, and to flow electric current from the output terminal to a terminal of a negative source power voltage; a fourth transistor connected between the output terminal and the third transistor, and configured to receive a predetermined voltage through a gate thereof; and a fifth transistor configured to supply a voltage smaller than an insulated voltage of the second transistor, to the substrate gate of the second transistor.