Patent ID: 7652942

Claim:
A sense amplifier sensing data stored in memory cells of an outmost memory cell array from among a plurality of memory cell arrays, comprising: a reference signal providing unit providing a reference bit line signal in response to a reference control signal; an internal sense amplification unit, connected to the outmost memory cell array, receiving the reference bit line signal and data signals, sensing the received reference bit line signal and the data signals and amplifying the sensed signals, wherein the data signals correspond to the data stored in the memory and are received though bit lines connected to the outmost memory cell array; and a connection controller controlling a connection of the internal sense amplification unit to the bit lines and the reference signal providing unit in response to an isolation signal, wherein the connection controller comprises: a first transistor group including a first plurality of transistors that respectively correspond to the bit lines and have first terminals connected to the reference signal providing unit, second terminals connected to the internal sense amplification unit, and gates receiving the isolation signal; and a second transistor group including a second plurality of transistors that respectively correspond to the bit lines and have first terminals connected to the bit lines, second terminals connected to the internal sense amplification unit, and gates receiving the isolation signal.