Patent ID: 7084430

Claim:
A pixel structure over a substrate, the pixel structure comprising: a thin film transistor over the substrate, the thin film transistor having a gate, a channel layer and a pair of source/drain terminals; a scan line over the substrate, the scan line and the gate being electrically connected; a data line over the substrate, the data line and the source terminal being electrically connected; a patterned insulation layer configured over the substrate exclusively in patterned areas vertically corresponding to the gate, the source/drain terminals, the data line and the scan line, the patterned insulation layer covering the gate and the scan line; a passivation layer configured over the substrate exclusively in patterned areas vertically corresponding to the gate, the source/drain terminals, the data line and the scan line, the passivation layer covering the source/drain terminals and the data line, wherein a sidewall of the source/drain terminal is exposed; and a pixel electrode over the substrate, the pixel electrode being positioned close to the thin film transistor such that the pixel electrode and a sidewall of the drain terminal of the thin film transistor are electrically connected.