Patent ID: 7541866

Claim:
An amplification unit comprising: a signal splitter, wherein the signal splitter is operable to split an input signal into a first signal and a second signal such that the two resulting signal portions are in quadrature; a main amplifier, wherein the main amplifier is capable of amplifying the first signal to produce a first amplified signal; an auxiliary amplifier, wherein the auxiliary amplifier is capable of amplifying the second signal to produce a second amplified signal, and the auxiliary amplifier is substantially dissimilar from the main amplifier; and a signal combiner, wherein the signal combiner is capable of combining the first amplified signal and the second amplified signal and realigning the phase of the first amplified signal and the second amplified signal, wherein the main and auxiliary amplifiers are formed utilizing semiconductor device technologies selected from the group comprising: a laterally diffused metal oxide semiconductor (LDMOS), a complementary metal oxide semiconductor (CMOS), a metal oxide semiconductor field effect transistor (MOSFET), a metal semiconductor field effect transistor (MESFET), a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), heterojunction field effect transistor (HFET), a bipolar junction transistor (BJT), or combination thereof, wherein the main and auxiliary amplifiers are comprised of semiconductor materials selected from the group comprising: silicon (Si), indium phosphide (InP), gallium arsenide (GaAs), or gallium nitride (GaN), or combination thereof, and further comprising linearization with memory correction wherein the input signal is pre-distorted to account for device non-linearities and memory when operating within the desired range.