Patent ID: 7064988

Claim:
A synchronous semiconductor memory device in which an operation of a row-system circuit is started in response to input of a first command and an operation of a column-system circuit is started in response to input of a second command, comprising: a first circuit configured to generate a first signal for a normal operation mode based on a command detection signal which is activated in response to the first command, a second circuit configured to receive the command detection signal, an operation mode specifying signal which selectively specifies one of the normal operation mode and a test mode and a selection signal used to select at least part of the memory cells in a memory cell array and generate a second signal for the test mode which sets start timing of the operation of the row-system circuit by sequentially delaying start timing of the operation of the row-system circuit with respect to the second command in one of a half-clock unit and one clock unit and selecting a delay amount based on a timing control signal, and a third circuit configured to select the first signal output from the first circuit when the normal operation mode is specified by the operation mode specifying signal, select the second signal output from the second circuit when the test mode is specified, and generate a third signal used to activate at least part of the memory cells in the memory cell array based on a selected one of the first and second signals and the selection signal.