Patent ID: 7456063

Claim:
A layout method of a power line for a semiconductor integrated circuit, comprising the steps of: forming a decoupling capacitor on a substrate, wherein the decoupling capacitor comprises a MOS transistor having a gate and source/drain regions; laying out a first metal layer, connected to the source/drain regions of the decoupling capacitor through contacts, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed, the second metal layer being electrically connected to the gate, wherein the first metal layer comprises a slot penetrating the first metal layer and aligned with the gate of the decoupling capacitor, and a slot metal formed of the same metal as the first metal layer, formed within the slot and enclosed by the slot, the slot metal being connected to the gate of the decoupling capacitor through one or more contacts, wherein the second metal layer is separated by a predetermined distance from the first metal layer and connected to the slot metal through one or more vias.