Patent ID: 7808321

Claim:
An amplifier circuit comprising: a first n-channel metal oxide semiconductor (NMOS) transistor which includes a gate connected to receive a first input signal; a second NMOS transistor which includes a gate connected to receive a second input signal; a first p-channel metal oxide semiconductor (PMOS) transistor which includes a source connected to a source voltage, and a gate and a drain connected to a drain of the first NMOS transistor; a second PMOS transistor which includes a source connected to the source voltage, and a drain connected to the drain of the first NMOS transistor; a third PMOS transistor which includes a source connected to the source voltage, and a gate and a drain connected to a drain of the second NMOS transistor and to a gate of the second PMOS transistor; a fourth PMOS transistor which includes a source connected to the source voltage, a gate connected to the gate of the first PMOS transistor, and a drain is connected to the drain of the second NMOS transistor; and a third NMOS transistor which includes a drain connected to sources of the first and second NMOS transistors, a gate is connected to receive an enable signal, and a source connected to a ground voltage.