Patent ID: 7375411

Claim:
An integrated circuit comprising: a substrate; a plurality of integrated circuit layers formed above the substrate; an inductor at least partially formed in another integrated circuit layer above the substrate; at least one region of low conductor density vertically displaced from the inductor and including at least one portion of each of the plurality of integrated circuit layers; at least one transitional region including at least one portion of each of the plurality integrated circuit layers, the at least one transitional region disposed adjacent to the at least one region of low conductor density in each of the integrated circuit layers; at least one region of high conductor density including at least one portion of each of the plurality of integrated circuit layers, the at least one region of high conductor density disposed adjacent to the at least one transitional region, the at least one transitional region disposed between the at least one region of low conductor density and the at least one region of high conductor density; and a plurality of conductive structures formed in the at least one transitional region, the plurality of conductive structures being electrically isolated from each other; wherein the inductor is vertically displaced from the plurality of integrated circuit layers including the at least one region of low conductor density, the at least one region of high conductor density, and the at least one transitional region; wherein the at least one region of high conductor density has a conductor density in the range of 20% to 80%, wherein the at least one region of low conductor density is substantially void of conductive structures.