Patent ID: 8151126

Claim:
A data processing apparatus comprising: a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers; a communication path coupling an initiator logic element with a recipient logic element, payload data the subject of a transfer being passed over the communication path from the initiator logic element to the recipient logic element; the communication path having at least one buffer circuit provided therein for propagating at least the payload data along the communication path; a power supply for providing power to said at least one buffer circuit; and a power control circuit, associated with said at least one buffer circuit and responsive to a control signal indicative of whether the payload data on the communication path is valid, configured to cause said at least one buffer circuit to enter a power saving state by decoupling said at least one buffer circuit from said power supply when the control signal indicates that the payload data is not valid, the control signal being derived from at least one pre-existing signal associated with the transfer.