Patent ID: 8811526

Claim:
A system for communicating modulated Extremely High Frequency (EHF) signals, comprising: a modulation circuit responsive to a bi-level transmit information signal for generating a transmit output signal having an EHF frequency when the transmit information signal is at a first information state and suppressing the transmit output signal when the transmit information signal is at a second information state different than the first information state; a transmit transducer operatively coupled to the modulation circuit and responsive to the transmit output signal for converting the transmit output signal into an electromagnetic signal; an edge-detecting circuit responsive to a binary data input signal for generating the bi-level transmit information signal, the data input signal having a first binary state for a bit period of time when representative of a data bit ‘1’ and a second binary state for the bit period of time when representative of a data bit ‘0,’ there being transitions between the first binary state and the second binary state, the edge-detecting circuit generating the bi-level transmit information signal including an edge-indicating pulse generated in response to each transition in the data input signal between the first and second binary states, the first information state of the transmit information signal being the state when the edge-indicating pulse is occurring; and wherein the edge-detecting circuit includes: a D-type positive-edge flip-flop having a first D input that is at a continuous logic ‘1’ state, a first clock input for receiving the data input signal, and a first reset input for receiving the bi-level transmit information signal, the positive-edge flip-flop producing a first flip-flop output signal in response to the states of the signals on the first D input, the first clock input, and the first reset input; and a D-type negative-edge flip-flop having a second D input that is at a continuous logic ‘1’ state, a second clock input receiving the complement of the data input signal, and a second reset input for receiving the bi-level transmit information signal, the negative-edge flip-flop producing a second flip-flop output signal in response to the states of the signals on the second D input, the second clock input, and the second reset input; and an OR logic gate responsive to the first and second flip-flop output signals for producing the bi-level transmit information signal.