Patent ID: 7840917

Claim:
A method of correcting a design pattern for an integrated circuit, comprising: selecting a plurality of sample cells from a plurality of practical patterns on a substrate, the practical pattern being transcribed onto the substrate from a design pattern; storing the practical patterns in accordance with process failure types, each of the process failure types being characterized by a model pattern; generating a plurality of defect characteristic functions indicating frequencies of each of the defects that are independent from one another and cause the process failure by analyzing the practical patterns in accordance with the process failures; determining a normalization factor that indicates a correlation between the defect characteristic functions; generating a general defect characteristic function indicating a frequency of general defects that causes the same process failure as caused by each of the defects by using the defect characteristic functions and the normalization factor; and modifying the design pattern using a computer system in such a manner that the frequency of the general defects is minimized when at least one portion of the design pattern corresponding to the model pattern is transcribed on the substrate.