Patent ID: 7452780

Claim:
A method of forming a transistor, comprising: forming a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming low-energy ion implantation regions in the silicon substrate and in alignment with both sidewalls of the gate polysilicon layer by implanting impurities into the silicon substrate at an implantation energy of about 5 KeV or less; forming gate spacers on both sidewalls of the gate polysilicon layer; forming amorphous layers on surfaces of the gate polysilicon layer and the silicon substrate by implanting impurities into the gate polysilicon and the silicon substrate at an implantation energy of about 5 KeV or less, wherein the amorphous layers are formed in the silicon substrate at a depth which is shallower than a depth at which the low-enemy ion implantation regions are formed in the silicon substrate; and forming high energy ion implantation regions by implanting source/drain impurities at a high implantation energy into the silicon substrate including the gate polysilicon layer and the shallow amorphous layers.