Patent ID: 7804143

Claim:
An integrated circuit comprising: a substrate; an oxide layer extending into the substrate and having openings to the surfaces of active regions of the substrate; devices formed in the active regions of the substrate; one of the devices having a source region and a drain region spaced in one of the active regions and self-aligned with a corresponding gate, the gate including a first gate portion and a second gate portion; the first gate portion extending from the oxide layer over the substrate region between the source and drain regions and defining the length of a channel region of the device; the second gate portion being integral to the first gate portion, extending from the oxide layer over adjacent edges of the one active region and surrounding at least the drain region with the first gate portion; and a guardring region formed in an active region, the guardring having a first electrical conductivity type and surrounding the source region, the drain region and the gate, the one active region having the first electrical conductivity type, the sources region and the drain region having a second electrical conductivity type.