Patent ID: 8497565

Claim:
A semiconductor device comprising: an integrated circuit including a top metal layer; and a stacked capacitor formed within a non-conductive volume disposed over the top metal layer and comprising: multiple electrode layers conformally disposed within stack holes formed through the non-conductive volume; multiple dielectric layers conformally disposed within the stack holes alternately between the multiple electrode layers; a first electrode electrically coupled to a bottom layer of the multiple electrode layers and to a first contact node in a top metal layer of the integrated circuit by way of a first electrode via formed through the multiple electrode layers and multiple dielectric layers; a second electrode electrically coupled to a middle layer of the multiple electrode layers and to a second contact node in the top metal layer of the integrated circuit by way of a second electrode via formed through the multiple electrode layers and multiple dielectric layers; and a third electrode electrically coupled to a top layer of the multiple electrode layers.