Patent ID: 7420789

Claim:
An integrated circuit chip comprising: a first device coupled between a first core power supply bus and a core ground bus in a first power domain; a second device coupled between a second core supply bus and the core ground bus in a second power domain; an electrostatic discharge (ESD) bus coupled to the core ground bus of the first and second devices for providing a current path to dissipate an ESD current during an ESD event occurring at the first or second device; a first I/O power supply bus and a first I/O ground bus disposed in the first power domain; and a second I/O power supply bus and a second I/O ground bus disposed in the second power domain, wherein the first I/O ground bus is isolated from the second I/O ground bus and the ESD bus, respectively, wherein the ESD bus is disposed across the first and second power domains without having a diode module interposed therebetween, thereby preventing the ESD current from flowing through the first and second devices.