Patent ID: 8477527

Claim:
An apparatus, comprising: an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a plurality of true and complement bit line pairs, each bit line pair coupled to memory cells along one of the columns; sense amplifiers coupled to one of the true and complement bit line pairs for sensing a differential voltage on the bit line pair; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and the tracking circuits are coupled in series between the clock signal and the word line pulse end signal to provide a signal indicating the SRAM tracking time.