Patent ID: 7825523

Claim:
A multi-chip package comprising: a package substrate including a first surface having a plurality of bonding tips formed thereon and a second surface opposite to the first surface; two or more semiconductor chips vertically mounted on the package substrate, at least one of the chips including: a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern disposed over at least a portion of the peripheral circuit region; a passivation layer covering portions of the bond pad-wiring pattern and the semiconductor substrate; a pad-rearrangement pattern contacting the bond pad-wiring pattern, the pad-rearrangement pattern including a bond pad disposed over at least a portion of the cell region; an insulating layer disposed on the pad-rearrangement pattern; and a bonding wire electrically connected between the bonding tip and the bond pad, wherein a portion of the bond pad is exposed through the insulating layer.