Patent ID: 7863913

Claim:
An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate; C. a first bond pad formed on the substrate to input serial test input data; D. plural scan path circuits formed on the substrate, each of the scan path circuits having a serial input to receive test data, and parallel outputs coupled to the functional circuits; and E. circuitry formed on the substrate, the circuitry having a first serial input coupled to the first bond pad to receive the serial test input data from the first bond pad and plural parallel outputs, each of the parallel outputs being coupled to the serial input of a scan path circuit, the circuitry adapted to load a multi-bit test stimulus data pattern into each of the plural scan paths in parallel by repeatedly both receiving the serial test input data from the first bond pad on the first serial input and applying data bits to the serial inputs of the plural scan path circuits in parallel, the multi-bit test stimulus data pattern for one of the scan paths circuits including a subset but not all of the serial test input data received from the first bond pad on the first serial input.