Patent ID: 7321253

Claim:
A multiplier comprising: a first MOS transistor, a second MOS transistor having a drain connected to a source of said first MOS transistor, and a third MOS transistor having a drain connected to the source of said first MOS transistor; a first voltage source connected to a gate of said first MOS transistor, a second voltage source connected to a gate of said second MOS transistor, and a third voltage source connected to a gate of said third MOS transistor; and said second MOS transistor and said third MOS transistor are formed in such a manner as to have drain current coefficients substantially equal to each other and said second voltage source and said third voltage source have voltage values substantially equal to each other while all of said first to third MOS transistors are given either as NNOS transistors or as PMOS transistors, wherein an output terminal of the multiplier is provided at one of the source of the first MOS transistor, the drain of the second MOS transistor, and the drain of the third MOS transistor.