Patent ID: 7764264

Claim:
A display device comprising: a plurality of pixels; and a driving circuit for driving the plurality of pixels; wherein: the driving circuit includes a single channel bidirectional shift register adapted for bidirectional scanning in a first direction and a second direction; the single channel bidirectional shift register includes an “n” number of basic circuits tandem-connected in multiple stages (wherein “n” is equal to or greater than 2); the basic circuits each include a first circuit and a second circuit; the first circuit of each basic circuit includes a first transistor having a first electrode connected to a first node, a second electrode connected to a second scanning control line to which a second scanning direction control signal is supplied, and a control electrode connected to a first output terminal of a first basic circuit on a side of a preceding stage in the first scanning direction, and a second transistor having a first electrode connected to the first node, a second electrode connected to a first scanning control line to which a first scanning direction control signal is supplied, and a control electrode connected to a second output terminal of a second basic circuit on a side of a following stage in the first scanning direction; the second circuit of each basic circuit includes a third transistor having a first electrode connected to a second node, a second electrode connected to the second scanning control line, and a control electrode connected to a third output terminal of a third basic circuit on the side of the following stage in the first scanning direction, and a fourth transistor having a first electrode connected to the second node, a second electrode connected to the first scanning control line, and a control electrode connected to a fourth output terminal of a fourth basic circuit on the side of the preceding stage in the first scanning direction; and wherein each of the basic circuits further includes: a fifth transistor having a control electrode connected to the first node, a second electrode connected to the second node, and a first electrode connected to a reference potential line to which a reference potential is supplied; a sixth transistor having a control electrode connected to the second electrode of the fifth transistor, a first electrode connected to a clock terminal, and a second electrode connected to an output terminal of the basic circuit; and a first capacitive element connected between the second node and the output terminal of the basic circuit.