Patent ID: 7603634

Claim:
An apparatus, comprising an integrated circuit comprising: a volatile latch circuit containing one or more transistors coupled together to store and maintain a logic value, the volatile latch circuit comprising: a first power trace to supply a VSS voltage potential to a source terminal of a first transistor, a second power trace to supply a VDD voltage potential to a source terminal of a second transistor, and a third power trace to supply a third voltage potential to a well substrate of the second transistor to operate the volatile latch circuit in three or more power consumption modes, as well as three or more performance modes, wherein the volatile latch circuit further contains a buffer circuit containing the first and second transistors coupled to a slave latch sub circuit which cooperate to isolate the slave latch circuit when neighboring sub circuits are powered down, and the third power trace to supply the third voltage potential also couples to a source terminal of a third transistor in the slave latch sub circuit.