Patent ID: 7092300

Claim:
A memory apparatus, comprising: at least one cell array having a plurality of memory cells, each memory cell having an associated word line and an associated bit line; a control device having a signaling connection to a plurality of word lines and bit lines wherein the control device is configured to: execute a destructive read command for reading data from at least one memory cell, the destructive read command comprising: electrically biasing a bit line associated with the at least one memory cell; after electrically biasing, activating a word line associated with the at least one memory cell, thereby connecting the at least one memory cell to the bit line; and destructively reading data stored in the at least one memory cell, whereby the read data is destroyed as a result of reading the data; and execute a destructive write command for writing data to the at least one memory cell, the destructive write command comprising: writing dat to the at least one memory cell without first reading stored data in the memory cell.