Patent ID: 8370787

Claim:
A method for testing security of a mapping function of an integrated circuit (IC), the method comprising: receiving, by an analyzer of a processor-enabled test system, from the mapping function, a plurality of sets of response bits, wherein each set of the plurality of sets of response bits corresponds to corresponding ones of a plurality of sets of challenge bits applied to the mapping function; and analyzing, by the analyzer, at least the plurality of sets of response bits to perform a predictability test, a sensitivity test, and an emulation test to determine a level of security vulnerability of the mapping function; wherein the analyzing of at least the plurality of sets of response bits to perform the predictability test comprises determining whether there is a predictable relationship between two or more of the plurality of sets of response bits, based at least on Hamming distances between their corresponding sets of challenge bits, wherein the analyzing of at least the plurality of sets of response bits to perform the sensitivity test comprises analyzing at least the plurality of sets of response bits to determine sensitivity of the mapping function to manufacturing variability of the IC, and wherein the analyzing of at least the plurality of sets of response bits to perform the emulation test comprises analyzing at least the plurality of sets of response bits to determine redundancies in challenge-response pairs (CRP).