Patent ID: 8386753

Claim:
A method, in a processor, for thread completion arbitration, comprising: executing, by the processor, more than two threads of instructions simultaneously in the processor; selecting, by selection logic of the processor, a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor; selecting, by the selection logic, a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor; identifying, in the first thread and the second thread, instructions ready for completion; and completing, by completion logic of the processor, execution of the identified instructions in the first and second threads by committing results of the execution of the identified instructions of the first and second threads to a storage device associated with the processor, wherein: at least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads, the first subset of threads and second subset of threads have different threads from one another, and all of the more than two threads of instructions are processed through a same instruction pipeline of the processor.