Patent ID: 7535841

Claim:
A common-memory switch comprising: a number M>1 of input ports; a number N≧1 of output ports; a memory device storing data segments each having a segment size of W bits; a controller including an output flow-rate regulation device; and an input flow-rate-regulation device that regulates the rate of transfer of said information bits from each of said input ports to said memory device; wherein each of said data segments is associated with one of a plurality of predefined data streams and at least one of said data segments contains a number of information bits less than said segment size W; wherein said controller assigns a nominal flow-rate to each of said plurality of predefined data streams; and said output flow-rate regulation device uses said number of information bits and said nominal flow-rate to select at least one of said data segments for dequeueing; wherein an output port collates said information bits from selected ones of said data segments to form data bursts; wherein said at least one of said data segments containing a number of information bits less than said segment size W is padded with null bits; wherein each of said input ports receives data packets, associates each received data packet with one of said plurality of predefined data streams and delays said received data packets associated with each of said predefined data streams for a time interval not exceeding an upper bound D to accumulate sufficient data to form one of said data segments; wherein the width W of said memory device is determined as: W ≥ δ × ∑ j = 1 M ⁢ r j / ( 1 - ( N - 1 ) × N × δ / D ) , where δ is the time required to access said memory device and to write and read one of said date segments, D>N×(N−1)×δ is a permissible segment queueing delay at any of the M input ports, and r j , 1≦j≦M, is the rate at which one of said input ports transfers data to said memory device.