Patent ID: 7184332

Claim:
A method for testing memory circuit, said method comprising: providing a ROM-type memory circuit that includes: a matrix of memory cells for receiving data, the matrix being made up of rows and columns, each row allowing storage of a page of MUX words of N bits; an address decoder coupled to the matrix, the address decoder decoding addresses and determining which of the page to read; a set of N multiplexers coupled to the matrix and the output stage, each of the multiplexers having its inputs coupled to the columns that correspond to one of the bits of the output stage; and at least one inverter, each of the at least one inverters being connected to the output of a different one of the multiplexers for restoring inverted values of information to be stored to correct values, the inverted values being stored in all of the memory cells of all of the columns coupled to at least one of the multiplexers, each of the multiplexers not having one of the inverters connected to its output having a buffer connected to its output, the buffer having substantially the same transit time as the inverters; and successively testing groups of the memory cells associated with a same one of the multiplexers.