Patent ID: 7671410

Claim:
A MOS gate-controlled power device having enhanced avalanche ruggedness, the device comprising: a semiconductive substrate including a first layer ( 112 , 213 ) having a doping type of a first polarity in a first concentration (N+); a second layer ( 114 , 214 ) having a doping type of the first polarity in a second concentration (N) less than the first concentration; a body region ( 122 , 322 ) formed in the second layer having a doping type of a second polarity opposite the first polarity in a third concentration (P); a first enhanced region ( 222 , 422 ) formed in the body region having a doping type of the second polarity in a fourth concentration (P+) greater than the third concentration; a source region formed in a portion of the body region adjoining the enhanced region ( 222 , 422 ) and body region ( 122 , 322 ) having a doping type of the first polarity in a fifth concentration (N+) greater than the second concentration; an insulated gate structure formed on a surface of the second layer in position to overlie a channel portion of the body region extending along the surface between the source region and a drift region of the second layer; and a second enhanced region ( 120 , 220 ) of the doping type of the first polarity in a sixth concentration (N+) greater than the second concentration (N); the body region extending to a first depth and the first enhanced region extending to a second depth within the second layer to form a PN junction therewith; and the second enhanced region extending to a third depth within the second layer, the third depth exceeding both the first depth and the second depth so that avalanche breakdown occurs in the first enhanced region.