Patent ID: 8015329

Claim:
A device, comprising: a bus interface module comprising an input coupled to an address bus, an input coupled to a first data bus, and a plurality of enable outputs; a first data latch comprising an input coupled to the first data bus, and an output coupled to a second data bus; a first plurality of coherent access registers, each of the plurality of coherent access registers comprising a first input coupled to the second data bus, a second input coupled to a third data bus, and a first enable input coupled to a corresponding one of the plurality of enable outputs to simultaneously latch data at the output of the first data latch and on the third data bus at the corresponding coherent access register; and wherein the bus interface module further comprises: a second data latch comprising an input coupled to a fourth data bus, and an output; and a signal select multiplexer comprising a first input coupled to the output of the second data latch and an output coupled to the first data bus.