Patent ID: 8650516

Claim:
A method for design of a 3-D integrated circuit, comprising: receiving, through a computer graphical user interface, a rule at least partially defining an electrical interconnection of a design layer on a circuit level of the 3-D integrated circuit, the design layer and the circuit level being defined by a hierarchical 3-D technology file including one or more identifiers to one or more 2-D technology files supplied by a foundry, with no modification required of the one or more 2-D technology files supplied by the foundry; receiving, through the computer graphical user interface, a rule at least partially defining an alignment of the design layer on the circuit level; and performing a rule check for at least partially validating a circuit layout of the design layer on the circuit level by referencing the hierarchical 3-D technology file and using at least one of the rule at least partially defining the electrical interconnection of the design layer on the circuit level and the rule at least partially defining the alignment of the design layer on the circuit level.