Patent ID: 8659936

Claim:
A SRAM, comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that supply voltages at the power receiving terminals of the latch circuit are below a first predetermined voltage level when data is written to the latch circuit; wherein the power supplying circuit comprises: a Read Enable Bar signal transmitting line, for transmitting a Read Enable Bar signal; a plurality of power switch devices, for providing the power to the power receiving terminals of only one of the memory cell circuits, and turning on or off according to the Read Enable Bar signal; at least one power keeper device, having a first terminal coupled to the first predetermined voltage level, and a second terminal respectively coupled to the power receiving terminals; wherein the power switch device turns on when the data stored in the inverter coupled to the power receiving terminal coupled to the power switch device is read; wherein the SRAM further comprises a plurality of isolation devices, having a control terminal coupled to a Isolation Enable signal, a first terminal coupled to the power keeper device, and a second terminal coupled to the memo cell circuit, wherein the isolation devices are controlled by the Isolation Enable signal to turn on or off.