Patent ID: 8001501

Claim:
A design method, said method comprising: providing a netlist of a design; dividing the netlist into N user logics, N being a positive integer; after said dividing the netlist is performed, instantiating the N user logics in N macro test wrappers resulting in N instantiated logics; after said instantiating the N user logics is performed, processing the N instantiated logics, wherein said processing the N instantiated logics comprises a processor of a computer system performing a Random Resistant Fault Analysis (RRFA) to detect and identify signals for each instantiated logic of the N instantiated logics having a logic value of 1 or 0 with a high probability of at least 90 percent; and after said processing is performed, back-annotating a result of said processing to the netlist, wherein said result of said processing comprises the detected and identified signals.