Patent ID: 8497732

Claim:
A three-dimensional semiconductor integrated circuit, comprising: a first chip including a first semiconductor substrate, first and second transmitting circuits which are formed in the first semiconductor substrate, a first insulating layer which is formed on the first semiconductor substrate, a first electrode which is formed on the first insulating layer and is connected to the first transmitting circuit, and a second electrode which is formed on the first insulating layer and is connected to the second transmitting circuit; and a second chip including a second semiconductor substrate, a receiving circuit which is formed in the second semiconductor substrate, a second insulating layer which is formed on the second semiconductor substrate, and a via which penetrates the second semiconductor substrate and is connected to the receiving circuit, wherein the first and second chips are stacked in the same orientation, the first and second electrodes are arranged right below the via, a first electrostatic capacitance is formed between the via and the first electrode, a second electrostatic capacitance is formed between the via and the second electrode, and values of the first and second capacitances are different from each other.