Patent ID: 8836045

Claim:
An integrated circuit, comprising: a first conductive gate level feature forming both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive gate level feature providing an electrical connection between the gate electrodes of the first transistors of the first and second transistor types, the gate electrodes of the first transistors of the first and second transistor types having respective lengthwise centerlines substantially aligned; a second conductive gate level feature forming one gate electrode as a gate electrode of a second transistor of the first transistor type, each of the first and second transistors of the first transistor type formed in part by a shared diffusion region of a first diffusion type; and a third conductive gate level feature forming one gate electrode as a gate electrode of a second transistor of the second transistor type, the third conductive gate level feature electrically connected to the second conductive gate level feature, each of the first and second transistors of the second transistor type formed in part by a shared diffusion region of a second diffusion type, the shared diffusion region of the second diffusion type electrically connected to the shared diffusion region of the first diffusion type, the diffusion regions of the first diffusion type collectively separated from the diffusion regions of the second diffusion type, the gate electrodes of the second transistors of the first and second transistor types positioned on opposite sides of a gate electrode track extending along the substantially aligned lengthwise centerlines of the first transistors of the first and second transistor types.