Patent ID: 7349290

Claim:
A semiconductor memory device outputting data synchronized with a rising edge and a falling edge of a clock signal, the semiconductor memory device comprising: a first input/output control unit for changing a sensing node into a first level in response to an activation of a first enabling signal for enabling an output of a data synchronized with a rising edge of the clock signal; a second input/output control unit for changing the sensing node into a second level in response to a delay locked clock signal outputted from a delay locked loop as the second input/output control unit is enabled when the first enabling signal and a second enabling signal for enabling an output of a data synchronized with a falling edge of the clock signal are disabled; an output unit for outputting an input/output control signal corresponding to a changed state of the sensing node; and a data output driver for outputting a data as the data output driver is activated in response to a first level of the input/output control signal.