Patent ID: 7555073

Claim:
An automatic frequency control loop circuit, comprising; a clock oscillator generating a reference frequency; a frequency synthesizer which comprises: a first dividing unit dividing the reference frequency by a first division ratio; a second dividing unit dividing an oscillation frequency by a second division ratio; a phase detecting unit detecting a phase difference between a first divided frequency of the first dividing unit and a second divided frequency of the second dividing unit; a voltage-controlled oscillating unit generating the oscillation frequency based on the phase difference; and a frequency converting unit producing an output frequency based on the oscillation frequency and an input frequency; and a demodulator which comprises: an error detecting unit detecting an error by comparing the output frequency with a setup frequency; an integration unit integrating the error; and a computing unit calculating a control signal based on an integration value obtained in the integration unit, wherein the error is compensated for by changing the first division ratio or the second division ratio based on the control signal.