Patent ID: 7777522

Claim:
A circuit comprising: first circuitry having a first set of first and second power terminals for being powered by a first power supply domain, the first circuitry providing a data signal referenced to the first power supply domain; second circuitry having a second set of first and second power terminals for being powered by a second power supply domain having supply voltages that differ from the first power supply domain, the second circuitry providing the data signal referenced to the second power supply domain; and a clocked level shifter for coupling the first circuitry to the second circuitry, the clocked level shifter buffering the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage wherein voltage values on both first and second power terminals of the second set differ from the first and second power terminals of the first set, the clocked level shifter being clocked by a clock signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period, precharging the first and second nodes being used to establish a known state in the clocked level shifter.