Patent ID: 8890214

Claim:
A memory device having a memory array region and a peripheral circuit region disposed in a semiconductor device, the memory array region having a plurality of digit lines and at least one spacer formed adjacent to the digit lines, the semiconductor device, comprising: a substrate; an electronic component layer, disposed on the substrate; and at least one composite spacer disposed in the peripheral circuit region, adjacent to the electronic component layer and including: a first dielectric material, disposed adjacent to the electronic component layer; a second dielectric material, disposed adjacent to the first dielectric material; and a third dielectric material, disposed adjacent to the second dielectric material, wherein the second dielectric material is sandwiched between the first dielectric material and the third dielectric material, the first dielectric material has a protruding portion, the second dielectric material and the third dielectric material are disposed on the protruding portion, wherein an upper edge of the second dielectric material is higher than an upper edge of the first dielectric material in the peripheral circuit region.