Patent ID: 7999581

Claim:
A system for providing an output clock signal, the system comprises: a first clock divider, adapted to receive an input clock signal and to frequency divide the input clock signal to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to frequency divide the second divider input clock signal to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal, wherein the second clock driver is further adapted to select the second divider input clock signal out of a group comprising the input clock signal and multiple clock signals of different frequencies which are provided by multiple clock dividers; and a third clock divider, adapted to receive a third divider input clock signal and to frequency divide the third divider input clock signal to provide a third divider output signal having a frequency that is lower than the frequency of the third divider input clock signal, wherein the selecting of the second divider input clock signal comprises selecting the second divider input clock signal out of the input clock signal, the first divider output clock signal and the third divider output clock signal; wherein multiple clock dividers out of the first, second and third clock dividers are prevented from concurrently selecting the input clock signal and frequency dividing the input clock signal.