Patent ID: 8015476

Claim:
A cyclic redundancy check apparatus, comprising: a data input for receiving a sequence of sets of parallel data, each of said sets having a parallel data width that is at least as large as a first width and no larger than a second width that exceeds said first width; and a next state decoding portion coupled to said data input for producing a sequence of syndromes based on said received sequence of sets, said next state decoding portion configured to produce some of said syndromes based on respectively corresponding syndromes of said sets that have respective parallel data widths that are equal to said second width, and said next state decoding portion further configured to produce at least one of said syndromes based on a corresponding at least one of said sets that has a parallel data width that is less than said second width; wherein a last syndrome of said sequence of syndromes corresponds to all of said data in said sequence of sets.