Patent ID: 8242615

Claim:
A semiconductor package comprising: a base film; inner leads disposed on the base film, the inner leads at least partially defining a semiconductor chip mounting location on the base film; encoded dummy patterns disposed on the base film in an asymmetric configuration within the semiconductor chip mounting location, the dummy patterns being electrically isolated from the inner leads; a semiconductor chip including electrodes protruding from a main surface thereof, the semiconductor chip positioned proximate the semiconductor chip mounting location, where at least one of the electrodes is joined to at least one of the inner leads; and an encapsulating resin interposing the base film and the main surface of the semiconductor chip; wherein at least one of a position and a shape of at least one of the dummy patterns is a functional marker for at least one of the inner leads, and at least one of the dummy patterns is arranged in front of at least one of the inner leads in the semiconductor chip mounting location to specify a pin number of the at least one of the inner leads.