Patent ID: 8779511

Claim:
A semiconductor structure comprising a planar transistor and a finFET located on an insulator layer, wherein said planar transistor comprises: a planar semiconductor region comprising a semiconductor material and having a planar region thickness and including a planar channel region, a planar source extension region, and a drain extension region; and a gate electrode overlying said planar channel region, and said finFET comprises a semiconductor fin comprising said semiconductor material and including a center fin portion and two end fin portions adjoining said center fin portion, wherein said center fin portion has a center portion thickness greater than said planar region thickness and said two end fin portions have an end portion thickness less than said center portion thickness, and said semiconductor fin includes: a fin channel region located within said center fin portion; a fin source extension region extending through one of said two end fin portions and one end region of said center fin portion; and a fin drain extension region extending through the other of said two end fin portions and the other end region of said center fin portion.