Patent ID: 6844238

Claim:
A method for fabricating a multiple-gate device comprising the step of: providing a substrate comprising a semi-conducting layer overlaying an insulator stack, said insulator stack comprises an insulator layer overlying an etch-stop layer; patterning said semi-conducting layer forming a semiconductor fin, said semi-conductor fin having two sidewalls and a top, said fin formation process comprises a fin surface smoothing step which further comprises sub-steps of sacrificial layer oxidation arid high temperature anneal in a hydrogen ambient; etching said insulator layer at the base of said semiconductor fin forming an undercut; depositing a gate dielectric layer overlying said semiconductor fin; depositing an electrically conductive layer over said gate dielectric layer; etching said electrically conductive layer forming a gate straddling across said two sidewall surface and said top surface of the semiconductor fin; and forming a source region and a drain region in said semi conductor fin.