Patent ID: 6949426

Claim:
A method of fabricating an X-ray detector array, comprising the steps of: providing a substrate having a capacitor area and a 4 transistor area; forming a gate line transversely extending on the substrate, wherein the gate line includes a gate electrode in the transistor area; forming a gate insulation layer on the gate line, the gate electrode and the substrate; forming a semiconducting layer on the gate insulation layer; forming a first conductive layer on the semiconducting layer; using a gray-tone photolithography, removing part of the first conductive layer and the semiconducting layer to form a common line longitudinally extending on a first semiconducting island, and a source electrode, a drain electrode and a longitudinally extending data line on a second semiconducting island thereby forming a thin film transistor (TFT) structure, wherein the drain electrode electrically connects the data line; forming a second conductive on the gate insulation layer in the capacitor area and to cover the common line; forming a conformal passivation layer on the gate insulation layer, the second conductive layer, the TFT structure, the data line and the gate line; forming a first via hole penetrating the passivation layer to expose the surface of the source electrode; forming a planarization layer on the passivation layer and filling the first via hole; forming a second via hole and a third via hole penetrating the planarization layer, wherein the second via hole exposes at least the surface of the source electrode, and the third via hole exposes the surface of the passivation layer in the capacitor area; and forming a conformal third conductive layer on part of the planarization layer and electrically connecting the source electrode; wherein a storage capacitor structure is composed of the second conductive layer, the passivation layer and the third conductive layer in the capacitor area.