Patent ID: 7728628

Claim:
A level shift circuit comprising: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of one of the second operational voltage levels according to a voltage level switching at the first node, the output circuit including a first pulse generator which generates a first pulse according to the voltage level switching at the first node and a latch circuit which generates an output according to the generated first pulse, wherein the basic level shift circuit includes a pair of PMOS transistors and a pair of NMOS transistors, in which the source of each of the PMOS transistors is electrically connected with a voltage supply of the second high operational voltage via a voltage-drop circuit, and the drain of each of the PMOS transistors is electrically connected with the gate of the other of the PMOS transistors; and in which the source of each of the NMOS transistors is grounded, and the drain of each of the NMOS transistors is electrically connected with the drain of one of the PMOS transistors, respectively; the gate of one of the NMOS transistors being electrically connected with an input of one of the first operational voltage levels.