Patent ID: 8026542

Claim:
A memory device, comprising: a memory cell array comprising a wordline with an adjacent source/drain region in a silicon substrate, and a polysilicon plug over the source/drain region adjacent the wordline; a periphery area comprising an active area in the silicon substrate; a dielectric layer overlying the memory cell array and the periphery area; a bit line contact extending through the dielectric layer to the polysilicon plug in the memory cell array area, the bit line contact comprising, in sequence, a titanium layer incorporating nitrogen overlying and in direct contact with the polysilicon plug, and a metal layer overlying the titanium layer; and a contact extending through the dielectric layer to the active area in the periphery area, the contact comprising a metal silicide layer overlying the silicon substrate, a titanium layer incorporating nitrogen overlying and in contact with the metal silicide layer, and a metal layer over the titanium layer.