Patent ID: 8520464

Claim:
An interface circuit that communicates data to and from an external circuit in synchronization with an internally generated basic clock signal, the interface circuit comprising: an input/output terminal connected to the external circuit to receive a data signal output from the external circuit; a clock generator to generate a series of n+1 phase-shifted clock signals based on the basic clock signal, with “n” being an integer greater than 0; a set of n+1 data ports, each connected to the input/output terminal and the clock generator to receive the data signal in synchronization with an associated one of the n+1 phase-shifted clock signals to output a latched data signal; and a data port selector connected to the n+1 data ports to check the latched data signals to select one of the n+1 data ports that receives the data signal at a particular timing, the interface circuit loading the data signal through the selected data port in synchronization with the associated one of the n+1 phase-shifted clock signals, wherein each of the n+1 data ports includes a corresponding pair of primary and secondary D-type flip-flops connected in series between the input/output terminal and the data port selector to receive the data signal in synchronization with the associated one of the n+1 phase-shifted clock signals generated by the clock generator, and output the latched data signal to the data port selector, and wherein the data port selector detects a start bit of each of the multiple latched data signals to determine which one of the multiple data ports captures the start bit of the input data at the particular timing.