Patent ID: 7807995

Claim:
A nonvolatile semiconductor memory apparatus comprising: a semiconductor substrate; a plurality of lower-layer wires formed on the semiconductor substrate to extend in parallel with each other; a plurality of upper-layer wires formed above the lower-layer wires to extend in parallel with each other and to cross the lower-layer wires; an interlayer insulating film provided between the lower-layer wires and the upper-layer wires; and a plurality of resistance variable layers which are embedded in a plurality of contact holes formed in crossing regions where the lower-layer wires and the upper-layer wires cross each other in the interlayer insulating film and are electrically connected to the lower-layer wires and to the upper-layer wires; wherein the upper-layer wires electrically connect the plurality of resistance variable layers, and each of the upper-layer wires includes at least two layers which are a lowermost layer made of an electrically conductive material having a hydrogen barrier property and an electric conductor layer having a specific resistance which is lower than a specific resistance of the lowermost layer, and wherein, the lowermost layer is provided to completely cover an upper surface of an associated one of the resistance variable layers and to extend to a region surrounding the upper surface.