Patent ID: 7139989

Claim:
A semiconductor integrated circuit designing apparatus for automatically generating a pattern of a semiconductor integrated circuit under control of a computer, said apparatus comprising: an input means for inputting gate level logic circuit information, standard cell library information, and package information of a circuit block as a constituent of the semiconductor integrated circuit; a noise analysis means for performing noise analysis for the circuit block using the information inputted by the input means; a noise judgement means for judging whether the amount of noise that occurs in the circuit block is within a predetermined range or not, on the basis of a result of noise analysis by the noise analysis means; a processing ending means for ending the automatic generation of the pattern of the semiconductor integrated circuit, when it is judged by the noise judgement means that the amount of noise is within the predetermined range; a logic gate selection means for selecting a logic gate in the circuit block, which logic gate generates an amount of noise larger than a predetermined amount of noise, when it is judged by the noise judgement means that the amount of noise in the circuit block is out of the predetermined range; and a bypass condenser addition means for adding a bypass condenser for reducing power supply noise and substrate noise to the selected logic gate.