Patent ID: 8155317

Claim:
An encryption processing circuit configured to perform predetermined encryption computing, comprising: a decoder used for the predetermined encryption computing and configured to convert a binary input data subjected to data masking based on a first mask data into a first plurality of bit data of a constant hamming weight, regardless independently of a hamming weight of the input data and to output the first plurality of bit data as parallel data; a mask removing section connected to the decoder and configured to perform removing processing of the first mask data to the first plurality of bit data output by the decoder; a wiring network connected to the mask removing section and configured to receive the first plurality of bit data subjected to the mask removing processing by the mask removing section, the wiring network further configured, for the purpose of the predetermined encryption computing, to change a bit pattern of the received first plurality of bit data subjected to the mask removing processing by replacing bit positions of the first plurality of bit data subjected to the mask removing processing, and to generate a change bit data as parallel data; a mask adding section connected to the wiring network and configured to generate a second plurality of bit data by performing second mask data adding processing to the change bit data by using the second mask data; and an encoder connected to the mask adding section and configured to convert the second plurality of bit data into a binary output data, wherein the mask removing section is configured by a wiring network for mask processing, the wiring network connected to the decoder and configured to receive the first plurality of bit data, the wiring network further configured to change a bit pattern of the received first plurality of bit data by replacing bit positions of the first plurality of bit data, and to generate the first plurality of bit data subjected to the mask removing processing, wherein at least one of data masking by the first mask data and data masking by the second mask data is a data masking based on exclusive OR processing, wherein the wiring network for mask processing includes a plurality of selection circuits configured to change a state where two signals input into two input terminals respectively appear in two output terminals, according to a control input input into a control input terminal, and wherein outputs of the plurality of selection circuits, into which the plurality of first bit data are input, are changed by respectively inputting the first mask data as the control input into each of the control input terminals of the plurality of selection circuits, thereby replacing bit positions of the first plurality of bit data in the wiring network for mask processing.