Patent ID: 7855438

Claim:
An integrated circuit semiconductor device with interconnect wiring comprising: a substrate defining a deep via which is provided with a dielectric cladding in contact with the substrate; metal fill located within the dielectric cladding and defining an upper surface; a metal barrier layer located between the metal fill and the dielectric cladding, the metal barrier layer electrically connecting the metal fill to the interconnect wiring through at least one lateral gap in the dielectric cladding, the lateral gap being disposed along a side of the deep via below the upper surface of the metal fill such that the interconnect wiring forms an electrical connection with the metal fill at the side of the deep via and not the upper surface of the metal fill; and a dielectric layer located above the deep via, wherein the upper surface of the metal fill is recessed within the deep via to define a void between the upper surface of the metal fill and the dielectric layer, the void existing at least at normal room temperatures and normal device operating temperatures.