Patent ID: 7019530

Claim:
A method of surface preparation and imaging of integrated circuits, comprising the following steps in the recited order: a) selecting a first substrate having a top side and a bottom side and a thickness; b) cutting an opening through the entire thickness of the first substrate, wherein the opening matches the size of an integrated circuit to be analyzed, and wherein the integrated circuit includes a substrate wafer, at least one interconnect, and at least one electronic device; c) selecting a second substrate having a top side and a bottom side and a thickness; d) applying a first adhesive film having a bottom side and a top side to the top side of the first substrate, the first adhesive film covering the opening in the first substrate, and further having adhesive on both the bottom side and the top side; e) inserting the integrated circuit into the opening in the first substrate; f) attaching the integrated circuit to the bottom side of the first adhesive film; g) bonding the first substrate and the integrated circuit to the second substrate via the first adhesive film; h) thinning the bottom side of the first substrate and the integrated circuit until a user-definable portion of the integrated circuit has been removed; i) applying a second adhesive film having a bottom side and a top side to the bottom side of the first substrate, the second adhesive film covering the opening in the first substrate, and further having adhesive on both the bottom side and the top side; j) selecting a handle substrate having a top side and a bottom side and a thickness; k) bonding the first substrate and the integrated circuit to the handle substrate via the second adhesive film; l) removing the second substrate; m) if imaging of top level of integrated circuit is required, then performing an analytical imaging technique on the top side of the integrated circuit, otherwise proceeding to step (n); n) destructively processing the top side of the first substrate and integrated circuit until a user-definable portion of the integrated circuit has been removed; o) performing an analytical imaging technique on the top side of the integrated circuit; and p) if further imaging is required repeating steps (n) through (o), otherwise stopping.