Patent ID: 8441125

Claim:
A semiconductor device, comprising: a semiconductor layer having an active region; an electrode pad; a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; a bump formed in the opening and covering the active region when viewed from a top side, a first region in the semiconductor layer in a specific range positioned inward and outward from a line extending vertically downward from an edge of at least part of the bump; a first interlayer dielectric positioned between the electrode pad and the semiconductor layer, a first surface of the first interlayer dielectric facing the semiconductor layer, and a second surface of the first interlayer dielectric being opposite to the first surface of the first interlayer dielectric, the first surface being closer to the semiconductor layer than the second surface; a conductive layer positioned between the semiconductor layer and the first interlayer dielectric, the conductive layer being positioned on an insulating layer, the conductive layer having a first portion and a second portion, the second portion being connected with the first portion at a connection section, the connection section being positioned entirely outside of the first region, the first portion having a first width, and the second portion having a second width that is smaller than the first width; and a second interlayer dielectric positioned between the electrode pad and the conductive layer, the electrode pad being formed on a first surface of the second interlayer dielectric, wherein the conductive layer does not consist of a part of a transistor, wherein at least one transistor is formed in the active region, and wherein a top surface of the conductive layer is planar with a top surface of a gate of the at least one transistor.