Patent ID: 8222943

Claim:
A digital logic circuit, comprising: a logic element for providing a data signal; a clock for providing a clock signal; a master-slave flip-flop including a master latch for storing data on a master latch input at a first active edge of said clock signal and a slave latch for storing data on an output of said master latch at a second active edge of said clock signal following said first active edge; a timing error detector module for asserting an error signal in response to a change in said data signal during a detection period following said first active edge of said clock signal; and a timing correction module for selectively increasing a propagation delay of said data signal from said logic element to said master latch input in response to said error signal, wherein said timing error detector module includes an edge detector for asserting a timing signal having a duration that defines said detection period following said first active edge of said clock signal.