Patent ID: 7577895

Claim:
A method comprising accepting a variable length message; determining a seed code for at least one padding bit based on a length of the variable length message and a length of a uniform length cyclic redundancy code (CRC) calculator wherein the determining a seed code for at least one padding bit comprises: calculating a plurality of first XOR logic outputs for aligned bits of an initial code having an unasserted most significant bit (MSB) and all other bits asserted, and a CRC polynomial, wherein a least significant bit (LSB) of the initial code is aligned with a LSB of the CRC polynomial; deleting the LSB position of the first XOR logic outputs; adding an unasserted bit to a MSB+1 position of the first XOR logic outputs; then calculating a plurality of second XOR logic outputs for aligned bits of the added to first XOR logic outputs, and: the CRC polynomial, wherein the LSB+1 position of the first XOR logic outputs is aligned with a LSB of the CRC polynomial, if the bit at a LSB+1 position of the first XOR logic outputs is an asserted bit; a code having all unasserted bits, if the LSB+1 position of the first XOR logic outputs is an unasserted bit; padding a least significant bit (LSB) end of the variable length message with the at least one padding bit to form a padded message having a length equal to the length of the uniform CRC calculator; and performing a CRC calculation on the padded message using the uniform CRC calculator and the seed code as an initial code.