Patent ID: 7374990

Claim:
A method of fabricating a semiconductor structure containing a vertical transistor, the method comprising the steps of: providing a substrate wherein at least a portion of the working surface thereof is polysilicon; depositing a plurality of material layers on the substrate; forming a hole through the material layers over the polysilicon portion of the substrate surface to expose the polysilicon; epitaxially growing a polysilicon pillar from the polysilicon portion of the substrate surface through the hole; forming a protective cap layer over the pillar; removing a top one of the plurality of material layers to expose a sidewall surface of a top portion of the pillar; forming a spacer layer around the top portion of the pillar on the exposed sidewall surface; removing a second one of the plurality of material layers to expose a sidewall surface of a central portion of the pillar, the central portion being adjacent and beneath the spacer layer; depositing a dielectric layer around the central portion of the pillar on the exposed sidewall surface; and surrounding the dielectric layer of the pillar with a layer of conductive material; wherein the top portion of the pillar forms a first source/drain region of the transistor, the central portion of the pillar forms a channel region of the transistor, the bottom portion of the pillar forms a second source/drain region of the transistor, and a region of the conductive material surrounding the pillar forms a transistor gate of the transistor.