Patent ID: 8111520

Claim:
A semiconductor module comprising: a printed circuit board (PCB) having an inner space; a semiconductor package received in the inner space and electrically connected to the PCB; an electrode pattern formed on the PCB and electrically connected to the semiconductor package; an insulating layer pattern formed on the PCB in fluidic communication with the inner space, the insulating layer pattern having an opening to partially expose the electrode pattern through the insulating layer pattern; and an outer terminal mounted on the PCB to cover the inner space and the opening and to electrically connect the electrode pattern to the semiconductor package, wherein the semiconductor package comprises: a semiconductor chip having a bonding pad; a first insulating layer pattern formed on the semiconductor chip and configured to expose the bonding pad through the first insulating layer pattern; a conductive layer pattern formed on the first insulating layer pattern, the conductive layer pattern having a first end electrically connected to the bonding pad, and a second end opposite to the first end and electrically connected to the PCB through the inner space; and a second insulating layer pattern formed on the conductive layer pattern and the first insulating layer pattern, and configured to expose the second end of the conductive layer pattern through the second insulating layer pattern.