Patent ID: 8364906

Claim:
A microprocessor configured to communicate with other agents on a system bus, the microprocessor comprising: a cache memory; and a bus interface unit, coupled to the cache memory and to the system bus, configured to: receive from another agent coupled to the system bus a transaction to read data from a memory address; determine whether the cache memory is holding the data at the memory address in an exclusive state; determine whether the other agent is a priority agent; when the cache memory is holding the data at the memory address in an exclusive state and the other agent is not a priority agent, assert a hit-modified signal on the system bus and provide the data on the system bus to the other agent; and when the cache memory is holding the data at the memory address in an exclusive state and the other agent is a priority agent, assert a hit signal on the system bus and refrain from providing the data on the system bus to the other agent.