Patent ID: 7882479

Claim:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a circuit for implementing redundant memory access tangibly embodied in the machine readable medium used in the design process, said circuit including a memory; said memory including a dynamic random access memory (DRAM); said dynamic random access memory (DRAM) including a first daisy chain memory and a second daisy chain memory; a first memory controller coupled to said memory; said first memory controller using said memory as a primary address space for storage and fetches; a second redundant memory controller coupled to said memory; system control logic coupled to said first memory controller and said second redundant memory controller; said system control logic notifying said second redundant memory controller to take control of said memory; and said second redundant memory controller initializing and taking control of said memory responsive to being notified by said system control logic; and said first memory controller using said first daisy chain memory and said second daisy chain memory as a primary address space for storage and fetches during normal operation; and said first daisy chain memory and said second daisy chain memory is not used by said second redundant memory controller during normal operation; wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.