Patent ID: 7453742

Claim:
A semiconductor integrated circuit device comprising: a bit line; a sense amplifier; a charge transfer transistor provided between the bit line and the sense amplifier; and a bit line clamp voltage generating circuit which generates a bit line clamp voltage to be applied to a gate of the charge transfer transistor, the bit line clamp voltage generating circuit including a current mirror circuit having input and output stages, a resistive dividing circuit provided between the input stage of the current mirror circuit and a first reference potential node, a potential setting circuit provided between an output node of the resistive dividing circuit and the output stage of the current mirror circuit, and an operational amplifier which is configured by transistors other than intrinsic transistors and compares potential of the input stage of the current mirror circuit with a reference potential to control the current mirror circuit; wherein the potential setting circuit includes a first circuit including a first resistor and a first transistor connected in series to the first resistor, and a second circuit including a second resistor and a second transistor connected in series to the second resistor, the first transistor turns on when the bit line is charged in a readout operation to cause a first voltage drop to occur on the first resistor and adds the first voltage drop to a potential of the output node of the resistive dividing circuit, and the second transistor turns on when data is read out of a memory cell and then transferred to the sense amplifier to cause a second voltage drop, which is different from the first voltage drop, to occur on the second resistor and adds the second voltage drop to the potential of the output node of the resistive dividing circuit; wherein the bit line clamp voltage is derived from the output stage of the current mirror circuit.