Patent ID: 8762641

Claim:
A method executed by a processor for accessing a cache, wherein the cache comprises a tag array, a data array and a valid array, the method comprising: setting all entries in the valid array to a first array value; before all valid array entries are validated, reading a valid array entry from the valid array each time a data array entry from the data array is accessed, if the valid array entry is the first array value, treating access to the cache as a miss, if the valid array entry is a second array value, comparing a tag array entry in the tag array with selected bits in an address to determine if the data array entry is a hit or a miss, and in case of a miss, reloading the cache from memory, and setting the valid array entry to the second array value; establishing a valid control register for the cache, the valid control register indicating whether all valid array entries are validated; setting the valid control register to a first control value before all valid array entries are validated; monitoring the valid array entries on an entry-by-entry basis while the processor is executing a program and setting the valid control register to a second control value when it is determined that all valid array entries are validated; after the second control value is set, accessing cached data in the data array without reading the valid array at least by comparing the tag array entry with the selected bits in the address to determine if the data array entry is a hit or a miss, and in case of a miss, reloading the cache from memory, if, after the valid array entry has been set to the second array value, the data array entry subsequently becomes invalid, resetting the valid array entry to the first array value; and if the valid control register contains the second control value, resetting the valid control register to contain the first control value.