Patent ID: 7286436

Claim:
A memory module having a first memory capacity, the memory module comprising: a plurality of substantially identical memory components configured as a first rank and a second rank, the memory components of the first rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another, the memory components of the second rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another; a logic element which receives a first set of address and control signals compatible with a second memory capacity, the second memory capacity substantially equal to one-half of the first memory capacity, wherein the logic element translates the first set of address and control signals into a second set of address and control signals compatible with the first memory capacity of the memory module, the logic element transmitting the second set of address and control signals to the first rank and the second rank; and a termination bus, each pair of memory components comprising a first memory component having a first data strobe pin, a first termination signal pin in electrical communication with the termination bus, a first termination circuit, and at least one data pin, wherein the first termination circuit selectively electrically terminates the first data strobe pin and the at least one data pin of the first memory component in response to a first signal received by the first termination signal pin from the termination bus.