Patent ID: 8101458

Claim:
A method of forming a Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of: providing a semiconductor substrate selected from pre fabricated CMOS circuits, MEMS and NEMS materials on a front side and a polished backside area available for post-CMOS, micro/nano fabrication with through substrate conductive vias and the prefabricated MEMS or NEMS materials having conductive structural and dielectric layers; forming at least one opening in the polished backside of the semiconductor substrate including protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated MEMS, NEMS or CMOS chip on the filler material, the chip including a front face and a bare back face with the filler material enabling planarization of all the corners of the chip to the substrate; forming at least one metallization layer connecting the through substrate conductive vias to the at least one chip; performing at least one micro/nano fabrication etching step to release the MEMS/NEMS structural layer on the front side.