Patent ID: 7995407

Claim:
A semiconductor memory device comprising: a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second power supply voltage is supplied and a third power supply voltage is supplied; a redundant cell array that includes a redundant memory cell to which one of the first power supply voltage and the second power supply voltage is supplied and the third power supply voltage is supplied; and a power supply control circuit that controls supply of the first power supply voltage and the second power supply voltage to the regular cell array and the redundant cell array, wherein a difference between the second power supply voltage and the third power supply voltage is smaller than a difference between the first power supply voltage and the third power supply voltage, wherein the power supply control circuit supplies the regular cell array with the first power supply voltage and supplies the redundant cell array with the second power supply voltage when the redundant cell array is unused, and wherein the power supply control circuit supplies the regular cell array with the second power supply voltage and supplies the redundant cell array with the first power supply voltage when the redundant cell array is used.