Patent ID: 8867271

Claim:
A method for controlling a three-dimensional non-volatile memory device, the method comprising: performing an adjustment process for SGD transistors of a plurality of memory strings of the three-dimensional non-volatile memory device, the SGD transistors are select gate, drain transistors, the plurality of memory strings comprise one memory string and another memory string, the one memory string comprises one SGD transistor at a drain end of the one memory string, an SGS transistor at a source end of the one memory string and memory cells between the one SGD transistor and the SGS transistor, the another memory string comprises another SGD transistor at a drain end of the another memory string, and the performing the adjustment process for the SGD transistors comprises, for each SGD transistor: reading the SGD transistor at a lower control gate voltage Vth_min; reading the SGD transistor at an upper control gate voltage Vth_max, the lower control gate voltage Vth_min and the upper control gate voltage Vth_max define an acceptable range of a threshold voltage of the SGD transistor; programming the SGD transistor if the reading of the SGD transistor at the lower control gate voltage Vth_min indicates that the threshold voltage of the SGD transistor is below the acceptable range, to raise the threshold voltage to within the acceptable range; and erasing the SGD transistor if the reading of the SGD transistor at the upper control gate voltage Vth_max indicates that the threshold voltage of the SGD transistor is above the acceptable range, to lower the threshold voltage to within the acceptable range, wherein: the one SGD transistor is subject to the programming; the drain end of the one memory string is in communication with a bit line; the programming of the one SGD transistor comprises applying a program pulse to a control gate of the one SGD transistor while floating voltages of control gates of the memory cells and a voltage of a control gate of the SGS transistor, and applying a voltage to the bit line, a voltage of the program pulse is sufficiently higher than the voltage applied to the bit line to allow programming of the one SGD transistor; the another SGD transistor is not subject to the programming; the drain end of the another memory string is in communication with the bit line; and while the program pulse is applied to the control gate of the one SGD transistor, a voltage of a control gate of the another SGD transistor is not sufficiently higher than the voltage applied to the bit line to allow programming of the another SGD transistor.