Patent ID: 7032191

Claim:
A method for designing an integrated circuit (IC) comprising: providing a plurality of structural multi-project wafers (SMPWs), each SMPW comprising a plurality of pre-manufactured and pre-validated dice, each die configured to be separately programmed into a customized concept validating IC; if one of the plurality of SMPWs meets an IC designer's requirements, proceeding to a streamlined design flow and production for fabricating separate ICs from each of the concept validating ICs, the design flow having no IP integration or floor planning requirements; if one of the plurality of SMPWs is usable as an intermediate step, extracting at least one of a usable SMPW component and an SoC structure for use in a normal COT flow; and if one of the plurality of SMPWs does not meet a user's requirement and is not usable as an intermediate step, extracting at least one of a usable IP and an SoC structure from the plurality of SMPWs for use in a normal COT flow.