Patent ID: 7482657

Claim:
A semiconductor device comprising: a semiconductor region of a first conductivity type; a well of a second conductivity type that touches the semiconductor region; spaced-apart first source and first drain regions of the first conductivity type that touch the well; a first channel region that lies between and contacts the first source and first drain regions; spaced-apart first and second doped regions of the second conductivity type that touch the semiconductor region; a second channel region that lies between and contacts the first and second doped regions; an insulation region that touches the second channel region; a first gate that touches the insulation region, lies directly over the first channel region and the second channel region, and lies over the semiconductor region and well directly between the first source region and the first doped region, the first source region and the second doped region, the first drain region and the first doped region, and the first drain region and the second doped region, the first gate having a top surface and a pattern that defines a shape of the top surface; spaced-apart second source and second drain regions of the first conductivity type that touch the well; a third channel region that lies between and contacts the second source and second drain regions; spaced-apart third and fourth doped regions of the second conductivity type that touch the semiconductor region; a fourth channel region that lies between and contacts the third and fourth doped regions; an insulation region that touches the fourth channel region; and a second gate that touches the insulation region that touches the fourth channel region, lies directly over the third channel region and the fourth channel region, and lies over the semiconductor region and well directly between the second source region and the third doped region, the second source region and the fourth doped region, the second drain region and the third doped region, and the second drain region and the fourth doped region, the second gate having a top surface and a pattern that defines a shape of the top surface of the second gate, the pattern of the first gate and the pattern of the second gate having symmetry.