Patent ID: 8762907

Claim:
A method of equivalence checking a top level of a circuit design having multiple functional blocks, comprising: receiving, by a computer, a post-engineering change order (ECO) netlist of a first one of said functional blocks, wherein said post-ECO netlist has been verified employing an equivalence checker; generating a top level netlist for said circuit design including said post-ECO netlist and a block netlist for a second one of said multiple functional blocks; generating a top level register transfer level (RTL) for said circuit design including a RTL for said second functional block; and performing an equivalency check of said top level RTL to said top level netlist, wherein a RTL for said first functional block and said post-ECO netlist are black boxed for said performing, wherein said black boxed RTL for said first functional block is analyzed as a whole without examining internal circuitry thereof.