Patent ID: 6865705

Claim:
A semiconductor integrated circuit device including an internal circuit and a control circuit for controlling the internal circuit, wherein the control circuit comprises a controller capable of realizing by using a terminal defined by JTAG, at least, one of the following modes: a first mode capable of adjusting a pulse width of a word line selecting signal or a column selecting signal for selecting a memory cell included in the internal circuit; a second mode capable of adjusting a timing for activating a sense amplifier included in the internal circuit; a third mode capable of adjusting a pulse signal for selecting a word line or a column for selecting a memory cell included in the internal circuit, according to a clock signal; a fourth mode capable of adjusting a timing for equalizing a data bus for reading out data in the internal circuit; an fifth mode capable of adjusting the rising characteristic or falling characteristic of data supplied from an output circuit included in the internal circuit; a sixth mode capable of switching a simultaneous output bit structure of the data in the internal circuit; and a seventh mode capable of turning a register for data output in the internal circuit into a slew state.