Patent ID: 8252423

Claim:
A method for producing a laminate for an electronic circuit component, comprising: providing (i) a first layer construction comprising a first inorganic material layer/a first insulating layer/a second inorganic material layer or (ii) a second layer construction comprising the inorganic material layer/the first insulating layer, wherein: at least the first insulating layer has a multi-layer structure including at least a first resin layer comprising a core insulating layer and a second resin layer comprising an adhesive layer; the first resin layer has a first etching rate when etched with an alkali-aliphatic amine solution and the second resin layer has a second etching rate when etched with the alkali-aliphatic amine solution; and wet-etching the first or second layer construction with an alkali-aliphatic amine solution so that a ratio of the first etching rate to the second etching rate is from 4:1 to 1:1, thereby controlling a shape of an edge of the laminate after etching.