Patent ID: 7865859

Claim:
A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising: a primary chip including an adaptive power supply (APS); a secondary chip circuit including at least one pair of hard-wired APS setting connections; said APS providing a power supply to said secondary chip circuit; said at least one pair of hard-wired APS setting connections being coupled to said primary chip for implementing adaptive power supply (APS) system voltage level activation; each of said hard-wired APS setting connections being defined as a one value or a zero value by a selected connection to either a voltage supply connection or a ground potential connection; and a respective inverter coupling a respective control signal from each of said hard-wired APS setting connections to a power communication bus connected to said APS on said primary chip; and said APS providing a predetermined programmed system voltage level responsive to said respective control signals.