Patent ID: 8839062

Claim:
A method for an incremental modification of an error detection code (EDC) by a processor device in a computing storage environment, the method comprising: for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one of a plurality of randomly positioned sub-blocks of the data block that becomes available and modified in independent time intervals: calculating and verifying the first error detection code (EDC) value following a read operation and prior to a write operation for the data block containing the plurality of randomly positioned sub-blocks; calculating and associating one of a plurality of second EDC values for each one of the plurality of randomly positioned sub-blocks as the data block receives each one of the plurality of randomly positioned sub-blocks; recalculating the one of the plurality of second EDC values following modifications to the at least one of the plurality of randomly positioned sub-blocks associated with the one of the plurality of second EDC values by applying an incremental effect to the one of the plurality of second EDC values that is recalculated, wherein the incremental effect is a change to the one of the plurality of second EDC values each time the at least one of the plurality of randomly positioned sub-blocks is modified; and applying the incremental effect of the one of the plurality of second of EDC values to the first EDC value upon modifying or replacing at least one of the plurality of randomly positioned sub-blocks, wherein resource consumption overhead of calculating the one of the plurality of second EDC values is proportional to the size of the at least one of the plurality of randomly positioned sub-blocks that are added and modified rather than the size of the data block.