Patent ID: 7606995

Claim:
A partitionable computer system partitioned into a plurality of partitions, the computer system comprising an integrated circuit, the integrated circuit comprising: a first processor core allocated to a first one of the plurality of partitions, the first processor core comprising: means for outputting a first physical address in a first address space allocated to the first one of the plurality of partitions; first partition identification means for storing a first partition identification value identifying the first one of the plurality of partitions; and first bit substitution means, coupled to the first processor core and the first partition identification means, for producing a first partition-identifying address by appending the first partition identification value to the first physical address; a second processor core allocated to a second one of the plurality of partitions that differs from the first one of the plurality of partitions; a hardware resource coupled to the first and second processor cores; means for transmitting the first partition-identifying address from the first bit substitution means to the hardware resource; and second partition identification means for storing a second partition identification value identifying the second one of the plurality of partitions; wherein the first partition identification value has a first size and wherein the second partition identification value has a second size which differs from the first size; and wherein granularity of partitioning for the computer system is a single processor core.