Patent ID: 7107415

Claim:
A computer system, comprising: a central processing unit (“CPU”); a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising: a plurality of memory devices; and a memory hub, comprising: a link interface receiving memory requests for access to at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transmit memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a posted write buffer coupled to the link interface and the memory device interface, the posted write buffer being operable to store write memory requests and to subsequently transmit the write memory requests to the memory device interface; and a read request path operable to transmit read memory requests from the link interface to the memory device interface and to transmit read data from the memory device interface to the link interface; and a communications link coupled between the system controller and each of the memory modules for transmitting memory requests and read data between the system controller and the memory modules in the respective memory modules.