Patent ID: 8135941

Claim:
A processor, comprising: a first and second processor core, each comprising: (i) a plurality of pipelined execution units configured to respectively execute a first and second issue group of multiple instructions and (ii) at least one of an instruction queue for delaying instruction execution and a target delay queue for holding results from instruction execution; and scheduling logic configured to, when the processor is in a base mode of operation, issue the first issue group to the first processor core for execution and the second issue group to the second processor core for execution and, when the processor is in a ganged mode of operation, issue one or more vector instructions to a morphed processor core formed from the first and second processor cores wherein each issue group comprises instructions issued in a single cycle; wherein each of the first and second processor cores is configured to, when the processor is in the base mode of operation, cascade execution of its respective issue group, using at least one of the instruction queue and the target delay queue; wherein the morphed processor core is configured to, when the processor is in the ganged mode of operation, cascade execution of the one or more vector instructions by increasing a queue depth of at least one of the instruction queue and the target delay queue of at least one of the first processor core and the second processor core.