Patent ID: 7442984

Claim:
A semiconductor memory device comprising: a semiconductor substrate which includes an active region having a plurality of active column portions extending in a first direction and a plurality of active row portions extending in a second direction substantially orthogonal to the first direction, and isolation portions, wherein the active row portions are arranged between and connected to respective pairs of active column portions and wherein respective concave portions are disposed within each active row portion between corresponding pairs of the active column portions; a floating gate formed over the semiconductor substrate; a control gate formed over the floating gate as crossing and extending over the active column portions and the isolation portions; an interlayer insulating film formed over the active region; a wiring formed over the interlayer insulating film; and conductive members arranged and buried within the concave portions, the conductive members pass through the interlayer insulating film and connect to the wiring and to the active row portions between the corresponding pairs of the active column portions.