Patent ID: 8145832

Claim:
A non-volatile memory device comprising: a non-volatile memory array organized into divisions, and the non-volatile memory array being further divided into subdivisions, each in a respective division of the divisions, and the subdivisions being blocks that include a plurality of general use erase blocks and redundant erase blocks; a redundant erase block control circuit including an erase block redirect look up table configured to have a selected redirect entry programmed therein, and the redundant erase block control circuit configured to: i) receive an extended memory address referencing a first erase block in a first division of the divisions; and ii) redirect accesses, from the first erase block in the first division to a second erase block in a second division of the divisions, by referencing the selected redirect entry in the erase block redirect look up table, and the extended memory address including a first portion associated with a normal address space, and a second portion associated with general use access to available unutilized redundant erase blocks in the divisions.