Patent ID: 7910973

Claim:
A semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a capacitor element area including a capacitor element, each of the memory strings comprising: a plurality of first conductive layers laminated on a substrate; a plurality of first interlayer insulation layers formed between the plurality of first conductive layers; a semiconductor layer formed to penetrate the plurality of first conductive layers and the plurality of first interlayer insulation layers; and a charge accumulation layer formed between the first conductive layers and the semiconductor layer, the capacitor element area comprising: a plurality of second conductive layers laminated on the substrate and formed in the same layer as the first conductive layers; and a plurality of second interlayer insulation layers formed between the plurality of second conductive layers and formed in the same layer as the first interlayer insulation layers, a group of the second conductive layers laminated adjacently to form two layers being connected to a first potential, while another group of the second conductive layers laminated adjacently to form two layers being connected to a second potential different from the first potential, and the second conductive layers laminated adjacently to form two layers and the second interlayer insulation layer between the second conductive layers configuring the capacitor element.