Patent ID: 8688898

Claim:
A memory device comprising: a memory; a memory interface configured to access the memory in parallel in accordance with a plurality of access commands; a command generator configured to: speculatively issue a plurality of access commands to the memory interface in a first access process for accessing the memory in units of blocks; set, in each of a plurality of next access commands to be issued, first specification information indicating that when the next access command to be issued fails in execution, a corresponding command response should be returned; and issue the access commands with the first specification information set therein to the memory interface, when the next access commands to be issued are other than last access commands in the predetermined access process; an access command returning module configured to return access commands which have already been issued to the memory interface, and which are unexecuted at a time of occurrence of an error, wherein the access command returning module is configured to return access commands through corresponding purge responses when the error occurs in a memory access by the memory interface in accordance with the plurality of access commands; and a command progress manager configured to: manage progress of the access commands in the first access process based on command progress management information stored by the command progress manager; and update the command progress management information to indicate the oldest one of the unexecuted access commands if the unexecuted access commands have been returned, wherein the command generator is further configured to reissue the returned unexecuted access commands to the memory interface based on the updated command progress management information.