Patent ID: 8053825

Claim:
A stacked gate nonvolatile semiconductor memory comprising at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate; the memory cell transistor including: a first floating gate made of a semiconductor material; a first interlayer insulating layer made of an insulating material above the first floating gate; and a first control gate made of a silicide material above the first interlayer insulating layer, and the selective gate transistor including: a second floating gate made of the semiconductor material; a second interlayer insulating layer made of the insulating material above the second floating gate; a second control gate made of the silicide material above the second interlayer insulating layer; a trench formed from a top of the second control gate into the second floating gate through the second interlayer insulating layer; and a conductive layer in the trench made of a conductive material not subject to silicide process, and electrically connecting the second floating gate and the second control gate.