Patent ID: 7961009

Claim:
A domino logic block comprising: a pre-charge circuit to pre-charge a first electrical node and to discharge a second electrical node in response to a clock signal, an enable signal and a first input signal; and an evaluation circuit comprising a first transistor connected in parallel to a logic unit between the first electrical node and the second electrical node, the evaluation circuit to output an output signal corresponding to one of the first input signal and a second input signal, the output signal of the evaluation circuit being based on the clock signal and the enable signal, wherein the first transistor receives the enable signal as a gate input signal, the logic unit receives the second input signal as an input, and the pre-charge circuit comprises: a first logic circuit to receive the enable signal and the first input signal; a latch circuit to latch an output of the first logic circuit in response to the clock signal; a second logic circuit to receive the clock signal and an output of the latch circuit; a second transistor to pre-charge the first electrical node in response to an output of the second logic circuit; and a third transistor to discharge the second electrical node in response to the output of the second logic circuit.