Patent ID: 7384850

Claim:
A method of forming an integrated circuit device, comprising the steps of: forming an NMOS transistor having a first active region in a semiconductor substrate, said first active region having a first fin-shaped channel region therein with a first height; and forming a PMOS transistor having a second active region in said semiconductor substrate, said second active region having a second fin-shaped channel region therein with a second height unequal to the first height; wherein said step of forming an NMOS transistor comprises the steps of: selectively etching back a portion of a surface of the semiconductor substrate to define a trench therein that surrounds the first active region; filling at least a portion of the trench with an electrical isolation region that covers sidewalls of the first active region; selectively etching a first portion of the electrical isolation region to expose a portion of the sidewalls of the first active region, thereby to define the first fin-shaped channel region at a portion of the first active region having the exposed portion of the sidewalls; and forming a first gate insulating layer on the exposed portion of the sidewalls of the first active region.