Patent ID: 8129234

Claim:
A method of fabricating a semiconductor structure, comprising: forming a high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 3.9 on a surface of a semiconductor layer; removing said high-k dielectric material layer from a portion of said surface of said semiconductor layer and forming a disposable material portion on said portion of said surface of said semiconductor layer; forming a semiconductor material layer and a dielectric cap material layer over said high-k dielectric material layer and said disposable material portion; patterning said dielectric cap material layer and said semiconductor material layer to form at least one gate stack and a mesa structure that laterally surrounds a cavity, wherein said at least one gate stack includes a portion of said high-k dielectric material layer, said mesa structure comprises a remaining portion of said dielectric cap material layer and a remaining portion of said semiconductor material layer, and a top surface of said disposable material portion is exposed within said cavity; expanding said cavity by removing said disposable material portion underneath said mesa structure to expose said top surface of said semiconductor layer; and growing an epitaxial base in a portion of said cavity by selective epitaxy.