Patent ID: 7761669

Claim:
A computer system comprising a processor that issues requests for data; a first memory chip and a second memory chip coupled to a memory bus, each memory chip having a plurality of banks, wherein a dead cycle is required on the memory bus between a first cycle driven by the first memory chip and a second cycle driven by the second memory chip; a memory controller coupled to the memory bus, the memory controller further comprising a read queue configured to store requests issued by the processor, the memory controller configured to service the requests for data by opening a particular bank, reading the particular bank, and closing the bank, the memory controller configured to control dead cycles on the memory bus as a function of a number of pending requests in the read queue, the memory controller configured to provide more than two memory access modes; the memory controller further comprising: a request count that contains a current value of the number of pending requests in the read queue; a first threshold that contains a first threshold value; a second threshold that contains a second threshold value, the second threshold value greater than the first threshold value; a third threshold that contains a third threshold value, the third threshold value greater than the second threshold value; the memory controller configured to use a first memory access mode if the number of a number of pending requests in the read queue is less than the first threshold value; the memory controller configured to use a second memory access mode if the number of a number of pending requests in the read queue is greater than or equal to the first threshold value and less than the second threshold value; and the memory controller configured to use a third memory access mode if the number of a number of pending requests in the read queue is equal to or greater than the third threshold value; the memory controller in the first memory access mode configured to service an oldest request in the read queue unless a younger request can be serviced without increasing a latency of the oldest request; the memory controller in the second memory access mode configured to degrade latency of the oldest request by a first amount by servicing one or more younger requests before servicing the oldest request, whenever servicing the one or more younger requests eliminate one or more dead cycles on a memory bus; and the memory controller in the third memory access mode configured to degrade latency of the oldest request by a second amount, the second amount greater than the first amount, by servicing one or more younger requests before servicing the oldest request, whenever servicing the one or more younger requests eliminate one or more dead cycles on a memory bus.