Patent ID: 7965579

Claim:
A circuit configured to be mounted on a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another in response to a first number of chip-select signals, the first number of ranks comprising a first number of DDR memory circuits, the circuit configurable to: receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals, wherein the received set of signals are capable of controlling a memory module having a second number of ranks, each rank of the second number of ranks comprising a second plurality of DDR memory circuits that are configured to be activated concurrently with one another, the second number of ranks comprising a second number of DDR memory circuits, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory circuits smaller than the first number of DDR memory circuits; monitor command signals received by the memory module; selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals; and provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.