Patent ID: 7589391

Claim:
A semiconductor device comprising: a silicon substrate; an isolation trench formed in said silicon substrate for isolating n-type and p-type active regions in said silicon substrate, said isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate, and said active regions having flat upper surfaces; a liner insulating film formed on a surface of said isolation trench surrounding said n-type and p-type active regions and a silicon nitride film having a thickness of 2 to 8 nm; an isolation region burying said trench defined by said liner insulating film; an n-channel MOS transistor formed in said p-type active region with a first gate electrode formed over said p-type active region; and a p-channel MOS transistor formed in said n-type active region with a second gate electrode formed over said n-type active region; wherein said silicon nitride film extends from side walls of said trench to partially overlay said flat upper surfaces of the active regions; and wherein each of said gate electrodes is formed over the flat upper surface of the active region, said liner insulating film on the flat upper surface of the active region, and said isolation region so as to traverse the active region.