Patent ID: 8613111

Claim:
Tamper detection circuitry for a protected memory, comprising: a first surface layer surrounding the protected memory, the first surface layer comprising a first plurality of conductive sections; a second surface layer surrounding the protected memory, the second surface layer being located outside of the first surface layer, the second surface layer comprising a second plurality of conductive sections; a programmable interconnect located inside the first surface layer, the programmable interconnect being connected to each conductive section of the first and second plurality of conductive sections by a plurality of conductive traces, the programmable interconnect comprising a plurality of switches that are configured to group the conductive sections of the first and second plurality of conductive sections into a plurality of circuits, each of the plurality of circuits having a different respective voltage; a tamper detection and response module, the tamper detection and response module configured to detect tampering based on a conductive section that is part of a first circuit coming into physical contact with a conductive section that is part of a second circuit; and a random number generator that is internal to the programmable interconnect and located inside of the first surface layer and the second surface layer, wherein the grouping of the conductive sections of the first and second plurality of conductive sections into the plurality of circuits is determined based on an output of the random number generator.