Patent ID: 8373834

Claim:
A method of forming an array substrate for use in an in-plane switching liquid crystal display device, comprising: providing first and second substrates; sequentially forming a first barrier layer and a first low resistance metallic layer on the first substrate; simultaneously patterning the first barrier layer and the first low resistance metallic layer using a first mask process to form a gate line, a gate electrode, a gate pad and a plurality of common electrodes on the first substrate, wherein the gate line is disposed in a first direction, the gate pad is connected to one end of the gate line, the gate electrode extends from the gate line, and the plurality of common electrodes are disposed in a second direction perpendicular to an adjacent gate line, and wherein the gate electrode and the gate line have a first double-layered structure consisting of the first barrier layer and the first low resistance metallic layer; forming a gate insulating layer over the first substrate to cover the gate line, the gate electrode, the gate pad and the plurality of common electrodes; forming an active layer and an ohmic contact layer on the gate insulating layer using a second mask, the active layer and the ohmic contact layer disposed over the gate electrode; sequentially forming a second barrier layer and a second low resistance metallic layer on the gate insulating layer to cover the active and ohmic contact layers; simultaneously patterning the second barrier layer and the second low resistance metallic layer using a third mask to form a data line in the second direction, a data pad at one end of the data line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode across the gate electrode, and a plurality of pixel electrodes in the second direction and connected to the drain electrode, wherein the pixel electrodes are arranged in an alternating pattern with the common electrodes, wherein the data line defines a pixel region with the gate line, and the data line and the source and drain electrodes have a second double-layered structure consisting of the second barrier layer and the second low resistance metallic layer; forming a passivation layer over the gate insulating layer to cover the data line, the data pad, the source electrode, the drain electrode, and the plurality of pixel electrodes; attaching the second substrate to the first substrate using a sealant; cropping peripheral portions of the second substrate to expose gate and data portions; and etching a portion of the passivation layer corresponding to the gate and data portions to expose the gate and data pads.