Patent ID: 8448055

Claim:
A method for performing error correction for a synchronization frame, comprising: acquiring a receiver information sequence according to a frame structure of the synchronization frame sequence from a transmitter acquiring a syndrome sequence according to the receiver information sequence; acquiring an error pattern according to the syndrome sequence; and acquiring result of error correction according to the error pattern and the receiver information sequence, wherein the syndrome sequence is =(s 0 , s 1 . . . s N−1 ), and the acquiring a syndrome sequence according to the receiver information sequence comprising: calculating the module-2 sum of four predetermined values in the receiver information sequence every time to acquire one value in , and performing the calculation for N times to acquire the N values in the ; wherein N is a natural number and equals to the number of the bits in the error pattern is =(e 0 , e 1 . . . e N−1 ), and the acquiring the error pattern comprises: determining an index set, A(i)={j 1 , j 2 , . . . j 4 }, for each e i ; where each j x is the index of a line in a check matrix, H, and element i of the line is 1; determining whether the number of bits with a value of 1 in the s j 1 , s j 2 . . . , s j 4 in the syndrome sequence, =(s 0 , s 1 . . . s N−1 ) is larger than half of total number of the bits; and determining that e i =1 when the number of bits with a value of 1 in the s j 1 , s j 2 . . . , s j 4 in the syndrome sequence, =(s 0 , s 1 . . . S N−1 ) is larger than half of total number of the bits; or determining that e i =0 when the number of bits with a value of 1 in the s j 1 , s j 2 . . . , s j 4 in the syndrome sequence, =(s 0 , s 1 . . . s N−1 ) is less than or equal to half of total number of the bits, the acquiring the result of the error correction comprises: performing module-2 adding for the receiver information sequence, , the calculated error pattern, ; and taking the acquired =( + %2 as the result of the error correction.