Patent ID: 8813020

Claim:
A computer-implemented method comprising: storing a first layout of a circuit on a non-transitory memory medium, wherein the first layout describes a plurality of vertically stacked layers used in a fabrication process to manufacture the circuit, wherein each layer corresponds to a respective step in the fabrication process, wherein the fabrication process would modify geometries of one or more of the layers and result in an electrical connection between a first layer and a second layer of the described plurality of vertically stacked layers, wherein the electrical connection is a design feature of the circuit that is not directly specified by the first layout; applying, by the computer, a set of rules to the first layout to automatically generate a modified layout for performing an electromagnetic (EM) simulation of the circuit, wherein the modified layout specifies a vertical electrical connection between the first layer and the second layer corresponding to the electrical connection that would result from the fabrication process, wherein the set of rules is particular to the fabrication process; and storing the modified layout on the non-transitory memory medium, wherein the modified layout enables the electromagnetic (EM) simulation of the circuit to be performed, including EM simulation of the electrical connection using the specified vertical electrical connection.