Patent ID: 8649227

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a bit line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor; a word line connected to both a gate of the first memory cell and a gate of the second memory cell; a first line connected to a gate of the first transistor; a second line connected to a gate of the second transistor; and a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the bit line, a second voltage is applied to the first line and a third voltage is applied to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage.