Patent ID: 7101746

Claim:
A method of forming dual gates in the fabrication of an integrated circuit device comprising: growing a gate oxide layer overlying a substrate; depositing a polysilicon layer overlying said gate oxide layer; implanting germanium ions into a portion of said polysilicon layer not covered by a mask to form a polysilicon-germanium layer; and patterning said polysilicon layer and said polysilicon-germanium layer to form NMOS polysilicon gates and PMOS polysilicon-germanium gates wherein said NMOS polysilicon gates are thick NMOS gates having a width of more than 2400 Angstroms and thin NMOS gates having a width of less than 800 Angstroms and wherein said PMOS polysilicon-germanium gates are thin PMOS gates having a width of less than 800 Angstroms.