Patent ID: 6878623

Claim:
A method of fabricating integrated circuit metal silicide comprising: providing a semiconductor substrate having isolation regions formed therein; providing a gate structure comprised of a gate dielectric and a polysilicon gate conductor on said semiconductor substrate; implanting ions into said semiconductor substrate not covered by said gate structure, thereby forming lightly doped source and drain regions; forming first spacers along the sidewalls of said gate structure; implanting ions into said semiconductor substrate not covered by said gate structure and said first spacers, thereby forming source and drain regions; depositing a metal layer overlying said gate structure, said first spacers, said source and drain regions, and said isolation regions; simultaneously forming second spacers in a single step, etching both overlying said metal layer along said sidewalls of said gate structure and overlying said metal layer over said isolation regions; depositing a polysilicon layer overlying said second spacers and said metal layer not covered by said second spacers; thereafter thermally annealing said semiconductor substrate causing said metal layer in contact with said polysilicon layer and said source and drain region to transform into a metal silicide; etching away said polysilicon layer that was not transformed to a metal silicide during said thermal annealing; and etching away said second spacers and said metal layer that was not transformed to a metal silicide during said thermal annealing thereby completing fabrication of said integrated circuit metal silicide.