Patent ID: 8806294

Claim:
An error detection system in a memory, comprising: a tag memory configured to generate a stored tag and a stored parity associated with a request tag received in association with an access to the memory; an error detection code encoder configured to determine a request parity based on the received request tag; Error Correction Code (ECC) detection logic coupled to the tag memory and configured to determine an error correction status based on the stored tag and the stored parity; hotness logic coupled to the tag memory and the error detection code encoder and configured to receive the stored tag and the stored parity from the tag memory, receive the request tag, receive the request parity from the error detection code encoder, determine a parity hotness by comparing the stored parity and the request parity, and determine a tag hotness by comparing the stored tag and the request tag; and error status logic coupled to the hotness logic and the ECC detection logic and configured to receive the parity hotness, the tag hotness and the error correction status and determine an error status based on the parity hotness, tag hotness, and the error correction status.