Patent ID: 6862677

Claim:
An instruction execution device for use in a processor, the instruction execution device comprising: an instruction pipeline for producing a first result for a first instruction; a register file connected to the instruction pipeline, the register file including at least a first write port for storing the first result; a bypass circuit connected to the instruction pipeline, the bypass circuit for allowing access to the first result; means for indicating whether the first result is used by a subsequent instruction at any stage of the instruction pipeline that includes determining whether a same destination address for the first result is re-used by a subsequent instruction at any stage of the pipeline; and a register file control connected to the instruction pipeline and the register file, the register file control for preventing the first result from being stored in the write port when the first result has been accessed using the bypass circuit and is used only by the subsequent instruction in the instruction pipeline; wherein said register file control includes comprising means for determining that a field of an opcode instruction indicates whether the first result is subsequently used.