Patent ID: 8732716

Claim:
A multi-core processor, comprising: a set of main processing elements, each configured to generate virtualized control threads to control sub processing elements, the set of main processing elements comprising: a first main processing element located in a first physical partition, second main processing element located in a second physical partition, and a third main processing element located in a third physical partition; a logical group of sub-processing elements, wherein a first sub-processing element is located in the first physical partition, a second sub-processing element is located in the second physical partition, and a third sub-processing element is located in the third physical partition; and a first virtualized control thread generated by the first main processing element, the first virtualized control thread associating the second main processing element of the second physical partition with the logical group of sub-processing elements, wherein the first virtualized control thread is configured to: control a clock speed, power consumption and computation loading of sub-processing elements of the logical group of sub-processing elements, collect computation results from the sub-processing elements of the logical group of sub-processing elements, and send program code and data to the sub-processing elements of the logical group of sub-processing elements.