Patent ID: 8420526

Claim:
A method for producing a memory device comprising the steps of: forming a multiplicity of insular active regions in a semiconductor substrate, forming two strip-type word line stacks with a gate dielectric layer and a gate layer on the semiconductor substrate in such a way that three contact regions are formed in the insular active regions, forming a common drain region in a contact region lying between the two word line stacks and forming source regions in the remaining contact regions, forming a common nanoelement on the common drain region, and forming additional nanoelements on the source regions, embedding the common nanoelement in a dielectric layer, forming a first depression in the dielectric layer in the region of the common nanoelement, filling a bit line layer into the first depression, the bit line layer being electrically connected to the contact region lying between the two word stacks, etching the bit line layer back to form a second depression, filling completely the second depression with a dielectric filling material, and forming at least one memory element at the surface of the dielectric layer in such a way that it is electrically connected to the additional nanoelements.