Patent ID: 8378700

Claim:
A test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit comprising: a test wafer having a shape corresponding to a shape of the semiconductor wafer; a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips; and a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, each of the plurality of connection terminals being connected to a corresponding one of the test terminals, wherein each of the plurality of test circuits generates a common test signal to the two or more semiconductor chips to be tested, and substantially simultaneously supplies the test signal to the two or more semiconductor chips via connection terminals, among the plurality of connection terminals, which correspond to the two or more semiconductor chips, each of the plurality of test circuits including: a signal generating section that is provided in common to the two or more semiconductor chips to be tested, and generates the test signal; a plurality of drivers, each driver corresponding to one of the two or more semiconductor chips to be tested, receiving the test signal generated by the signal generating section in parallel, and supplying a signal corresponding to the test signal to the test terminal of a corresponding one of the two or more semiconductor chips via the connection terminal; and a timing generating section that supplies a timing signal to the plurality of drivers, and each driver outputs the signal corresponding to the test signal, in response to the timing signal.