Patent ID: 7542348

Claim:
A memory device, comprising: a memory cell, wherein a floating gate MOS transistor serves as a storage device storing low threshold data or high threshold data in a charge trap region between a body and a control gate; and a memory cell array, wherein a plurality of memory cell is connected to a local bit line, one side of the local bit line is connected to a segment write line through a write select transistor and the other side of the local bit line is connected to a segment read line through a read select transistor; and a segment write buffer driving the segment write line; and a bipolar segment read circuit, wherein drain of a pre-charge transistor is connected to the segment read line of the bipolar segment read circuit, gate of a read transistor is connected to the segment read line of the memory cell array, a select transistor is connected to the read transistor serially, and base of a bipolar transistor is connected to drain of the select transistor, where the bipolar transistor generates a current output; and a block read circuit, wherein a load transistor is connected to the bipolar transistor of the bipolar segment read circuit to receive the current output via transfer transistors, input node of a read inverter is connected to output node of the load transistor, and output node of a tri-state inverter is connected to input node of the read inverter, which read inverter generates a voltage output; and a latch circuit storing the voltage output of the block read circuit through a read path; and a latch control circuit, wherein a delay circuit generates a locking signal based on a reference signal which is generated by the memory cells storing low threshold data, and the locking signal locks the latch circuit.