Patent ID: 7590792

Claim:
A cache memory analyzing method for analyzing condition of a cache memory in a processor comprising a CPU and said cache memory, said cache memory being a set associative system cache memory having a plurality of data storage blocks for each set that is distinguished from other memory areas by a lower bit of a memory-access address, and the CPU being configured to perform recording control of the cache memory, the method comprising steps of: a reading step for reading information from the cache memory, the information containing an address of the cache memory at which a cache miss is generated; a totalizing step for totalizing numbers of cache misses generated at each of the address at which the cache miss is generated, the address being contained in the information; a sectionalizing step for sectionalizing, by each of the sets, the addresses at which the cache miss is generated and whose numbers of the cache miss are totalized; an extraction step for extracting an address group, the address group being a group of the addresses whose numbers of cache miss are equal or close to each other from a plurality of the addresses at which the cache miss is generated, the addresses being sectionalized as addresses of a same set; and a designating step for designating numbers of the data storage blocks for each set as a pre-processing of the extraction step, wherein, in the extraction step, when there is a plurality of the address groups divided in a same set, the plurality of the address groups are divided by giving high priority to the address groups that have a value of 1 or less, the value being a number that a number of the data storage block is subtracted from a number of the addresses contained in each of the address groups.