Patent ID: 8143111

Claim:
A method for manufacturing an integrated circuit (IC), the method comprising: providing a plurality of fuses on the IC, each of the plurality of fuses having an associated value; placing a configuration logic cell on the IC, the configuration logic cell being coupled to the plurality of fuses, wherein the configuration logic cell configures the IC based upon the values of the plurality of fuses; wherein the plurality of fuses includes at least one of: a physical die fuse present on a die of the IC, wherein the value of the die fuse is set to be unalterable by a process comprising laser cutting before packaging of the IC; a physical substrate fuse present on a substrate of the IC, wherein the value of the substrate fuse is set to be unalterable by a process comprising laser cutting before and after packaging of the IC; a memory component fuse comprising logic values stored in a memory location of the IC; and software fuses comprising logic values written to register bit fields in an internal register of the IC; logically combining, in the configuration logic, values of at least two of the fuses to configure the IC.