Patent ID: 7860252

Claim:
A system, comprising: a first integrated circuit that includes: a memory interface configured to receive content from a memory; a processor configured to request content from the memory; a verification block configured to maintain a first running value derived from content received from the memory and further arranged to transmit, in a form processed according to a first cryptographic process, the first running value and information representing memory addresses in the memory of the content requested by the processor; and a second integrated circuit in which security features are provided, the second integrated circuit including: a security block configured to verify content received from the first integrated circuit, to maintain a second running value derived from content received from the first integrated circuit, and to operate a second cryptographic process corresponding to the first cryptographic process to verify that the first running value corresponds to the second running value and to verify that the memory addresses of the content requested from the memory by the processor are within a specified region, the security block being further configured to impair the operation of the first integrated circuit if the first running value does not correspond to the second running value or if the memory addresses of the content requested from the memory by the processor are not within the specified region.