Patent ID: 7868660

Claim:
A circuit, comprising: a plurality of memory devices, each memory device including a first part and a second part, the first part including a one-shot device coupled to a first active pullup device, the first active pullup device coupled to a first line of a communications bus and to a first pullup resistor, the first line being capable of carrying data signals from a microcontroller to one or more of the plurality of memory devices, the second part coupled to a second line of the communications bus, the second line being capable of carrying clock signals from the microcontroller to the one or more memory devices; and wherein the one-shot device is configured to receive the data signals from the microcontroller, to detect a rising edge of the data signals and to produce a program pulse at a gate of the first active pullup device in response to the rising edge, the first active pullup device capable of being operatively coupled to the first pullup resistor thereby forming a first active pullup pair, the first active pullup device configured to produce a high logic level on the first line of the communications bus without relying on the first pullup resistor.