Patent ID: 8706952

Claim:
A data programming method for a storage device having a flash memory, wherein the flash memory comprises a plurality of memory cells, and the memory cells are divided into a plurality of physical blocks, each of the physical blocks comprises a plurality of physical addresses, and the physical addresses comprise at least one fast physical address and at least one slow physical address, and a speed for programming data into the at least one fast physical address is faster than a speed for programming data into the at least one slow physical address, each of the memory cells is used for storing n bits, wherein n is an integer greater than 1 and smaller than 5, and the data programming method comprising: at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number, and obtaining m physical blocks from the spare area, wherein m is a finite integer greater than 1 and no higher than a total block number of the spare area; configuring a plurality of logical blocks, wherein each of the logical blocks comprises a plurality of logical addresses, each of the logical blocks is mapped to one of the physical blocks in the data area, and both the at least one fast physical address and the at least one slow physical address of the physical blocks in the data area are used for programming data in a normal mode; receiving a first write command sent by a host, wherein the first write command comprises a first write data and a first logical address of the logical addresses; determining a logical address range of a buffer represented by the m physical blocks according to the first logical address and the predetermined block number, wherein the logical address range is among the logical blocks, the logical addresses in the logical address range are mapped to the at least one fast physical address and the at least one slow physical address of at least one of the physical blocks in the data area before the logical address range is determined, and are only mapped to the fast physical addresses of the m physical blocks after the logical address range is determined; determining whether all of the logical addresses to be programmed with the first write data are within the logical address range of the buffer; and using a fast mode to program the first write data into the m physical blocks when all of the logical addresses to be programmed with the first write data are within the logical address range of the buffer, wherein only the fast physical addresses of the physical addresses are used for programming data in the fast mode.