Patent ID: 8908413

Claim:
A method of operating a programmable resistance memory comprising: providing a programmable resistance memory; defining an operable resistance range for said memory, said resistance range extending from a minimum resistance to a maximum resistance; specifying a first resistance for a first memory state; specifying a second resistance for a second memory state, said second resistance exceeding said first resistance, said memory drifting from said first resistance to said second resistance in a first interval of time; programming said memory to said first memory state at a first time; reading said memory at a second time, said second time being later than said first time by less than said first interval of time; specifying a third resistance for a third memory state, said third resistance exceeding said second resistance; programming said memory to said second memory state at a third time, said second resistance drifting to said third resistance in a second interval of time; and reading said memory at a fourth time, said fourth time being later than said third time by less than said second interval of time.