Patent ID: 8097496

Claim:
A method of making a semiconductor device, comprising: providing a leadframe having a horizontal surface and first and second level downset lead extensions from the horizontal surface of the leadframe, the first level downset lead extension having vertical surfaces and horizontal surfaces parallel to and vertically offset by a first distance from the horizontal surface of the leadframe, the vertical surfaces of the first level downset lead extension being separated by a first width, the second level downset lead extension having vertical surfaces and horizontal surfaces parallel to and vertically offset by a second distance from the horizontal surfaces of the first level downset lead extension, the vertical surfaces of the second level downset lead extension being separated by a second width; mounting a quad flat nolead (QFN) semiconductor package having nolead contacts to the horizontal surfaces of the first level downset lead extension with the first width accommodating the QFN semiconductor package while reducing movement of the QFN semiconductor package and the first distance accommodating the QFN semiconductor package while reducing a height of the semiconductor device, the QFN semiconductor package including, (a) providing a first semiconductor die, (b) forming a first bond wire between the first semiconductor die and the nolead contacts, (c) mounting a second semiconductor die to the first semiconductor die, and (d) forming a second bond wire between the second semiconductor die and the nolead contacts; and mounting a flipchip semiconductor die to the horizontal surfaces of the second level downset lead extension with the second width being different than the first width to accommodate the flipchip semiconductor die while reducing movement of the flipchip semiconductor die and the second distance being different than the first distance to accommodate the flipchip semiconductor die while reducing the height of the semiconductor device.