Patent ID: 7183191

Claim:
A method of forming a semiconductor device package, comprising: providing a semiconductor substrate having an active surface including at least one layer of integrated circuitry thereon, the active surface defining a plurality of individual die locations thereon, and a plurality of bond pads associated with each of the plurality of individual die locations; forming intermediate conductive elements over the plurality of bond pads to project a height above the active surface; forming a pattern of mutually transverse channels in the active surface to a depth below the at least one layer of integrated circuitry, the pattern of mutually transverse channels circumscribing a semiconductor device location comprised of at least one individual die and exposing peripheral edges of the at least one layer of integrated circuitry; applying an encapsulant material at least over the active surface and into the pattern of mutually transverse channels to a depth exceeding the height of projection of the intermediate conductive elements; removing a depth of the encapsulant material sufficient to expose a portion of each of the intermediate conductive elements; and forming conductive traces over the encapsulant material from the exposed portions of the intermediate conductive elements to at least one mutually transverse channel of the pattern of mutually transverse channels, defining a peripheral edge of at least one individual die location of the plurality so as to define a plurality of laterally spaced edge contacts therealong, and severing the semiconductor substrate in alignment with at least some of the mutually transverse channels of the pattern including the at least one mutually transverse channel into a plurality of semiconductor elements each comprised of the at least one individual die location, wherein the exposed peripheral edges of the at least one layer of integrated circuitry remain covered with the encapsulant material and the plurality of laterally spaced edge contacts are located along a peripheral edge of a semiconductor element of the plurality.