Patent ID: 7158405

Claim:
A semiconductor memory device, comprising: memory areas at least substantially organizationally separated from one another; access line devices; memory elements provided in said memory areas, said memory elements being at least one of addressable and selectable via said access line devices at least during operation; and selection devices, each of said memory areas having, at least during operation, at least one of said selection devices in substantially direct spatial proximity assigned thereto for performing a selection, such that during operation, each of said selection devices for and assigned to a plurality of said memory areas is controllable and, as a result, in a controllable manner, at least one of an addressing and a selection in one of said memory areas of said plurality of said memory areas is be selectively controlled with each of said respective assigned selection devices during operation; said memory elements being memory cells of MRAM type; said memory areas with said memory elements, said access line devices and said selection devices together forming an MRAM memory; said memory areas being one of cell arrays and cell array regions formed by said memory elements; at least one of a bit line decoder and a word line decoder being provided as a corresponding one of said selection devices.