Patent ID: 7714618

Claim:
An output preset circuit for an output buffer, comprising: a latch having a first input terminal receiving a power on reset signal, a second input terminal receiving a voltage of the output buffer, a third input terminal receiving an internal output enable signal and an output terminal outputting a latch output signal; and an output preset device, comprising: a pull-up circuit receiving a preset enable signal and the latch output signal, wherein the pull-up circuit increases the voltage of the output buffer from a ground level to a first level when the preset enable signal is active and the latch output signal is at the high level; and a pull-low circuit receiving the preset enable signal and the latch output signal, wherein the pull-low circuit decreases the voltage of the output buffer from a power voltage level to a second level when the preset enable signal is active and the latch output signal is at the low level, and the first level and the second level are between the power voltage level and the ground level.