Patent ID: 8432494

Claim:
A video signal output circuit comprising: a clamp circuit which clamps an electric potential of an input terminal into which a video signal is inputted; a first differential amplifying circuit into which the video signal inputted from the input terminal and a predetermined reference voltage are inputted, and which amplifies and outputs the inputted video signal; a dividing circuit which generates a bias voltage supplied to the clamp circuit, and generates the reference voltage supplied to the first differential amplifying circuit or a base reference voltage of the reference voltage; and an offset circuit which adds or subtracts a predetermined offset voltage to or from the bias voltage, the reference voltage, or the base reference voltage generated by the dividing circuit so as to supply an offset voltage added/subtracted voltage to the clamp circuit or the first differential amplifying circuit, wherein the offset circuit includes a pnp bipolar transistor and an npn bipolar transistor, and outputs a difference voltage corresponding to a difference between a base-emitter voltage of the pnp bipolar transistor and a base-emitter voltage of the npn bipolar transistor.