Patent ID: 7795679

Claim:
A device structure formed in a substrate of a semiconductor material having a top surface, the device structure comprising: a first doped region of a first conductivity type defined within the semiconductor material of the substrate; a second doped region of the first conductivity type defined within the semiconductor material of the substrate; a third doped region disposed within the semiconductor material of the substrate laterally between the first doped region and the second doped region and continuously extending laterally beneath the first doped region and the second doped region, the semiconductor material of the third doped region having a second conductivity type opposite to the first conductivity type; a gate structure that directly contacts the top surface of the substrate, the gate structure having a vertically stacked relationship with the third doped region; a first crystalline damage layer within the first doped region of the substrate, the first crystalline damage layer including a first plurality of voids surrounded by the semiconductor material of the substrate, wherein at least a portion of the first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate, and the first crystalline damage layer does not extend laterally for a significant distance beneath the gate structure; a third crystalline damage layer within the third doped region of the substrate, the third crystalline damage layer including a third plurality of voids surrounded by the semiconductor material of the substrate, wherein at least a portion of the third doped region is disposed vertically between the third crystalline damage layer and a bottom the first region, and the third crystalline damage layer does not extend laterally for a significant distance beneath the gate structure.