Patent ID: 7879702

Claim:
A method for manufacturing a semiconductor device comprising consecutively: forming a doped silicon layer on a semiconductor substrate defining first, second, and third areas, said second area being disposed adjacent to said third area; patterning a first portion of said doped silicon layer formed on said first area, to form a first gate electrode; selectively implanting impurities into said first area of said semiconductor substrate, to form first source/drain regions associated with said first gate electrode; patterning a second portion of said doped silicon layer formed on said second and third areas, to form a second gate electrode; and selectively implanting impurities into said second and third areas of said semiconductor substrate, to form second source/drain regions associated with said second gate electrode, and further comprising: diffusing impurities in said first source/drain regions by using a heat treatment between said steps of selectively implanting of impurities to form said first source/drain regions and selectively implanting of impurities to form said second source/drain regions.