Patent ID: 8081010

Claim:
A network of cells which include data storage elements and combinational logic configured to tolerate transient and solid faults comprised of the following elements: a plurality of data storage cells each with the property to internally self recover from transient faults, wherein each data storage cell is configured to accept as input three signals of which a maximum of one is in error, to correct any single error input to correct the error on one of the input three signals, and to generate at least three outputs where at most only one output is in error due to a fault, further wherein each data storage cell has a plurality of state variables yk where k=1, 2, . . . , n and n is at least 3; and a plurality of combinational logic circuits coupled to the plurality of data storage cells such that each data storage cell output drives an independent combinational logic circuit, wherein the interconnection of elements is defined as follows: Let one or more data storage cells i each function as a data source and let data storage cell j function as a data sink, i. there are n combinational logic circuits coupled between data storage cell i and data storage cell j, one combinational logic circuit for each state variable yk; ii. for each state variable yk in data storage cell j, the combinational logic is derived only from one state variable yk in data storage cell i and presented as input to data storage cell j; iii. at most one combinational logic circuit can suffer from a fault; wherein the data storage cell j receives n input signals from n combinational logic circuits, each of the n input signals drive state variable nodes k, k=1, . . . , n, and the data storage cell j is configured to transition to a correct stable state when at most one of the n input signals presents a false value due to a transient fault.