Patent ID: 8634500

Claim:
A receiver circuit comprising: a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path separate from the signal path, wherein the first slicer is configured to output a logic value based on a comparison between a voltage of the data signal and the reference voltage; a reference voltage generator configured to generate the reference voltage, wherein the reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode, and further configured to provide the reference voltage as a static voltage during operation in a second mode; a second slicer coupled to receive data signals from the signal path and the reference voltage from the reference voltage path; wherein the first slicer is configured to perform a comparison of a received data signal to the reference voltage responsive to a rising edge of a clock signal, and wherein the second slicer is configured to perform a comparison of a subsequently received data signal responsive to a falling edge of the clock signal.