Patent ID: 7412556

Claim:
A system comprising: a plurality of master devices; a slave device; a bus controller coupled between the master devices and the slave device, the bus controller including: a plurality of bus signal receiving units, each corresponding to one of the master devices; a plurality of bus signal transmission units, each corresponding to one of the master devices; a bus sequencing control unit, a bus signal buffer, a select unit and a shunt circuit unit, wherein the bus signals from the master devices are transmitted to the bus signal buffer via corresponding bus signal receiving units, after storing the bus signals from the master devices, the bus signal buffer respectively transmits the bus signals to the select unit, the bus sequencing control unit controls the select unit to select the bus signal from one master device and transmit it to the slave device, the bus response signals from the slave device is transmitted to and shunted by the signal shunt circuit unit, and the shunted bus response signals are transmitted to all master devices respectively via the corresponding bus signal transmission units, wherein the bus controller is configured to receive bus signals from the master devices, select one of the bus signals from one of the master devices and forwards the selected bus signal to the slave device, after the slave device receives the bus signal from the one of the master devices, the slave device sends a bus response signal to the master devices over the bus controller, and the master device from which the bus signal is selected identifies and receives the bus response signal.