Patent ID: 7825502

Claim:
A semiconductor die package comprising: a leadframe having at least a first electrically conductive region and a second electrically conductive region; a first semiconductor die having a first surface, a second surface, and at least one electrically conductive region disposed at its first surface, wherein the first semiconductor die is disposed such that its at least one electrically conductive region is disposed opposite to the first electrically conductive region of the leadframe and is electrically coupled thereto by a body of solder material; a second semiconductor die having a first surface, a second surface, a recessed portion at its second surface, and at least one electrically conductive region disposed at its second surface, wherein the second semiconductor die is disposed such that its at least one electrically conductive region is disposed opposite to the second electrically conductive region of the leadframe and is electrically coupled thereto by a body of solder material; and wherein at least a portion of the second surface of the first semiconductor die and at least a portion of the recessed portion of the second semiconductor die face each other.