Patent ID: 7548841

Claim:
A method for logic checking to check an arbitration of an arbiter that is connected to a bus to which at least two master circuits and at least one slave circuit are connected, the method comprising the steps of: connecting at least two master models, each of which can be set to output a same signal as a corresponding one of the at least two master circuits at given times, to the bus in place of the at least two master circuits and connecting at least one slave model, which can be set to output a same signal as the at least one slave circuit at given times, to the bus in place of the at least one slave circuit, wherein a bus master model executes bus access in accordance with a bus protocol; outputting the signals at a same time from the at least two master models in accordance with the bus protocol, and outputting the signal from the slave model in response to the signals outputted by the at least two master models; and checking the arbitration of the bus access by the arbiter in response to the signals output from the at least two master models and the slave model.