Patent ID: 8854895

Claim:
A semiconductor memory device, comprising: a memory cell array configured having a plurality of bit lines and a plurality of memory cells arranged therein; a sense amplifier circuit operative to detect and amplify a signal read from the memory cell into the bit line; and a sense amplifier control circuit operative to control the sense amplifier circuit, the sense amplifier circuit being divided into a plurality of sense amplifier groups, the plurality of sense amplifier groups each being further divided into a plurality of sense units, the sense amplifier control circuit being configured to sequentially select the plurality of sense amplifier groups according to a physical address allocated to a column, and to sequentially select the plurality of sense units included in a selected sense amplifier group, and the sense amplifier control circuit being configured to, when there is a defect related to a selected sense unit in a selected first sense amplifier group, select, in place of the first sense amplifier group, a sense unit included in a second sense amplifier group selected following after the first sense amplifier group.