Patent ID: 8779954

Claim:
An AD (analog-to-digital) conversion circuit, comprising: a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, said comparator circuit being configured to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage, which increases according to an adjustment voltage input from an external device connected to the input terminal, on an input side of the sample hold circuit connected to the input terminal reaches a threshold value defined in advance relative to the reference voltage, said sampling time adjusting circuit being configured to set a time determined according to the period of time thus measured as the sampling time.