Patent ID: 8530952

Claim:
A memory cell of an array of memory cells in a memory device, comprising: a storage region operable to store an electrical charge; a pair of nodes each node capable of being respectively coupled to a voltage source; a channel extending between the pair of nodes; a select region including a gate node below the channel and capable of being coupled to a gate voltage source, the gate node operable to generate a voltage potential below the channel responsive to being coupled to the gate voltage source; a first dielectric-filled double trench including an upper portion formed adjacent a first end of the storage region and including a lower portion formed adjacent a first end of the select region, wherein the upper and lower portions of the first dielectric-filled double trench having different widths; and a second dielectric-filled double trench including an upper portion formed adjacent a second end of the storage region and including a lower portion formed adjacent a second end of the select region, wherein the upper and lower portions of the second dielectric-filled double trench having different widths.