Patent ID: 7463505

Claim:
A semiconductor memory device comprising: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; two or more third wirings connecting the third terminals of the m memory cells, the third wirings including, from among unit blocks resulting from dividing the memory cell array into q sections in the first direction and r sections in the second direction, each unit block having s memory cells arranged in the first direction and t memory cells arranged in the second direction in a grid, first to t-th wiring parts connecting the s memory cells arranged in the first direction in a first unit block, first to t-th wiring parts connecting the s memory cells arranged in the first direction in a second unit block located next to the first unit block in the first direction, and a connection wiring part connecting a u-th (1≦u≦t) wiring part from among the first to t-th wiring parts in the first unit block and a wiring part other than a u-th (1≦u≦t) wiring part from among the first to t wiring parts in the second unit block; and means for selecting a third wiring from among the third wirings, the third wiring being selected based on the result of calculation in an adder circuit and a subtractor circuit.