Patent ID: 7979745

Claim:
An on-chip debug emulator capable of connecting to the target device and a host device to perform remote debugging of a program in the target device, wherein the on-chip debug emulator comprises a debug communication control unit, the debug communication control unit including a plurality of serial communication circuits commonly provided with a clock signal, the debug communication control unit controlling communications with the target device based on commands output from the host device, wherein each of the plurality of serial communication circuits comprises a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal, wherein the debug communication control unit conforms to JTAG (Joint Test Action Group) standards, wherein the plurality of serial communication circuits include a master serial communication circuit and, a first and second slave serial communication circuits, wherein the master serial communication circuit outputs the clock signal, and transmits to the target device an operation mode control signal for controlling the operation mode of the target device while synchronized to the clock signal, wherein the first slave serial communication circuit transmits to the target device an output signal other than the operation mode control signal while synchronized to the clock signal output from the master serial communication circuit, and wherein the second slave serial communication circuit receives a signal output from the target device while synchronized to the clock signal.