Patent ID: 8125275

Claim:
An amplifier comprising: a first input pair of transistors having a first pair of terminals coupled to a pair of input nodes, a second pair of terminals coupled to a pair of intermediate nodes, and a common terminal to receive a first tail current; a second input pair of transistors having a first pair of terminals coupled to the pair of input nodes, a second pair of terminals directly coupled to the pair of intermediate nodes, and a common terminal to receive a second tail current; an output pair of transistors having a first pair of terminals coupled to a pair of output nodes, a second pair of terminals coupled to the pair of intermediate nodes, and a common terminal to receive a third tail current; and a loop amplifier having a pair of input terminals coupled to the pair of input nodes and a pair of output terminals coupled to the intermediate nodes; where at least one of the first and second tail currents may be switched to provide at least two discrete gain settings.