Patent ID: 8735239

Claim:
A method of fabricating a semiconductor device, the method comprising: forming gate patterns in an NMOS transistor region and a PMOS transistor region of a substrate; forming a spacer structure on sidewalls of the gate patterns; etching the substrate in the PMOS transistor region using the gate patterns and the spacer structure as etching masks, thereby forming a recessed region; forming a compressive stress pattern in the recessed region, wherein a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate; forming a mask oxide layer on a sidewall of the spacer structure, wherein the mask oxide layer covers a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate; forming a metal-semiconductor compound layer on the compressive stress pattern; and removing the mask oxide layer from the sidewall of the spacer structure after forming the metal-semiconductor compound layer.