Patent ID: 7215332

Claim:
A display device comprising: m display blocks, each of said m display blocks having 3n drain lines arranged adjacently to each other, n being a natural number equal to or greater than 2; a plurality of scanning lines common to said m display blocks and intersecting said drain lines of said m display blocks; a plurality of pixels disposed in vicinities of intersections of said plurality of scanning lines and said drain lines of said m display blocks, a respective one of said plurality of pixels being provided with a thin film transistor having a first terminal thereof coupled to a corresponding one of said drain lines of said m display blocks, a second terminal of said thin film transistor coupled to a corresponding one of said plurality of scanning lines, and a third terminal of said thin film transistor coupled to a pixel electrode of said respective one of said plurality of pixels; 3n bus conductors, each of said 3n bus conductors being coupled to a corresponding one of said 3n drain lines of a respective one of said plurality of display blocks via a respective first-type switch controlled by a control signal for selecting one of said m display blocks, said control signal being common to said first-type switches in said respective one of said m display blocks so that said 3n drain lines in said respective one of said m display blocks are supplied with video signals simultaneously; and k drain drivers disposed from said m display blocks with said 3n bus conductors arranged in-between, a respective one of said k drain drivers being coupled to said 3n bus conductors via a switch circuit controlled by a control signal for selecting one of said k drain drivers, said switch circuit having 3n second-type switches each connected between a corresponding one of said 3n bus conductors and a corresponding one of 3n output terminals of said respective one of said k drain drivers, where k is an integer equal to or larger than 2, wherein each of said k drain drivers is provided with an input latch circuit for receiving digital video data from an external circuit and an output latch circuit for receiving said digital video data from said input latch circuit and for outputting said digital video data, and a respective one of said k drain drivers is configured such that one of said k drain drivers receives digital video data for one of said m display blocks from the external circuit while another of said k drain drivers outputs video signals corresponding to digital video data previously received for another of said m display blocks to said 3n bus conductors.