Patent ID: 6995475

Claim:
An I/C chip suitable for wire bonding comprising: at least one conductive bond pad; at least one layer of dielectric material overlying said conductive bond pad; a surface defining an opening in said layer of dielectric material exposing said conductive bond pad; an intermediate conductive layer of TaN/Ta disposed in said opening overlying said conductive bond pad and in contact therewith and in contact with the entire surface of said opening and a top surface of said layer of dielectric material; a conductive seed layer disposed in said opening, overlying said intermediate conductive layer and in contact therewith and overlying said top surface of said layer of dielectric material, said conductive seed layer having exposed edges; two layers of Ni and Au plated on said conductive seed layer in said opening, overlying said conductive seed layer and completely covering said conductive seed layer including all exposed edges, said two layers of Ni and Au define walls in said opening in which a ball bond and wire is wholly disposed.