Patent ID: 7170126

Claim:
An integrated circuit structure comprising a vertical transistor comprising: a semiconductor wafer having a layer of SiGe alloy above and substantially parallel to a bulk semiconductor substrate; said wafer having a trench etched through the layer of SiGe into the bulk substrate; an isolating collar formed within the trench; a lower contact for the vertical transistor formed above the isolating collar, the lower contact being in contact with a portion of the SiGe layer above the isolating collar; a vertical body layer of strained silicon formed on an exposed vertical surface of the SiGe layer within the trench, said exposed vertical surface being recessed transversely from an original trench width, and said body layer extending upward substantially at said original trench width from the top surface of the lower contact, whereby the body layer of silicon is strained; a gate dielectric layer formed on an exposed vertical surface of the silicon body layer within the trench, thereby isolating the body layer from the trench interior; a gate electrode formed within the trench and separated from the body layer of silicon by the gate dielectric layer; and an upper electrode of the transistor formed in contact with the body layer of silicon, thereby establishing a path for conducting carriers from said lower contact to said upper contact through said vertical body layer.