Patent ID: 7092274

Claim:
A ferroelectric memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix form, the memory cells including a cell transistor and a ferroelectric capacitor, one of source and drain regions of the cell transistor being electrically connected to a corresponding one of a plurality of bit lines, a gate of the cell transistor being electrically connected to a corresponding one of a plurality of word lines, the other one of the source and drain regions of the cell transistor being electrically connected to one electrode of the ferroelectric capacitor, the other electrode of the ferroelectric capacitor being electrically connected to a corresponding one of a plurality of plate lines; a plurality of auxiliary word lines corresponding to the word lines and arranged in parallel to the word lines above the memory cell array; a stitch portion arranged in the memory cell array and electrically connected to the word lines and auxiliary word lines; a first dummy bit line arranged between the stitch portion and one of two bit lines disposed on both sides of the stitch portion, and separated from the bit line among the two bit lines with an interval which is the same as a pitch between the bit lines in the memory cell array, the first dummy bit line having the same width as the bit line; a first dummy memory cell electrically connected to the first dummy bit line and including a cell transistor and a ferroelectric capacitor; a second dummy bit line arranged between the stitch portion and the other one of the two bit lines disposed on both sides of the stitch portion, and separated from the other bit line among the two bit lines with the interval, the second dummy bit line having the same width as the bit line; and a second dummy memory cell electrically connected to the second dummy bit line and including a cell transistor and a ferroelectric capacitor.