Patent ID: 7046574

Claim:
A memory system comprising: a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for receiving a designating signal for designating one area out of the plural areas of said semiconductor storage device and a relative physical address independent of each of the areas, and specifying the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address, so that said semiconductor storage device is accessed, wherein, when one area out of the plural areas is designated by the designating signal, said control section becomes able to access only the designated area, wherein said semiconductor storage device includes first plural areas each of which becomes accessible when it is designated by the designating signal and a second area which becomes accessible when none of the areas is designated by the designating signal, and wherein, when one area out of the first plural areas is designated by the designating signal, said control section becomes able to access only the designated area, and when none of the areas is designated by the designating signal, said control section becomes able to access only the second area.