Patent ID: 7913207

Claim:
A computer program on a non-transitory computer-readable medium, said computer program causing said computer to perform a logic circuit verification method, comprising: using an apparatus configured to verify the logic circuit, generating a wave file using a source file representing the logic circuit, the wave file including waveforms of each node of the logic circuit, wherein the source file can take the form of an HDL code, a gate-level net-list, and a SPICE net-list; and also using the apparatus configured to verify the logic circuit, verifying the logic circuit using a design reference file and the wave file, the design reference file including ideal operations to be implemented for each node of the logic circuit, wherein the verifying includes determining whether there is a waveform corresponding to each signal node in the logic circuit, and if there is a mismatch of a waveform corresponding to each node in the logic circuit, indicating a defect or a malfunction.