Patent ID: 7580281

Claim:
A flash memory device comprising: a memory cell array comprising a plurality of memory blocks; control logic configured to control execution of a write operation directed to an identified memory block in the plurality of memory block; and a protection controller configured to generate a protection flag signal associated with the identified memory block, wherein execution of the write operation by the control logic is enabled or disabled by the protection flag signal, wherein the protection controller comprises: a latch circuit comprising a plurality of latches, each corresponding to one of the plurality of memory blocks and storing temporary protected/accessible data; a cell array comprising a plurality of non-volatile memory cells storing, each corresponding to one of the plurality of memory blocks and storing persistent protected/accessible data; an address decoder receiving an address; a write controller responsive to a received command and configured to alter the persistent protected/accessible data in relation to the address; and a latch controller responsive to a received command and configured to alter the temporary protected/accessible data in relation to the address.