Patent ID: 8881077

Claim:
A diagnosis method for enabling automated debugging of pre-fabricated and post-fabricated digital hardware designs comprising the steps of: (a) applying a sequence of values to inputs, memory elements, or other signals of said hardware designs; (b) gathering an initial error trace t_e with a predetermined number of clock cycles K_f after applying said sequence of values; (c) copying the signal and value pairs from the initial error trace t_e into a new error trace t_e_i for a predetermined number of clock cycles K_f−K_i+1 to K_f wherein the length K_i is an initial trace bound and the length t_e_i is K_i<K_f; (d) performing debugging using the new error trace t_e_i thereby generating a set of debugging results; (e) analyzing the debugging results to determine if the suspect locations returned are the actual errors; and (f) analyzing the debugging results to determine if they denote one or more error locations.