Patent ID: 7466179

Claim:
A phase-interpolation circuit for outputting a third clock signal according to a first clock signal and a second clock signal, the circuit comprising: a first inverter for receiving the first clock signal; a second inverter for receiving the second clock signal, wherein an output end of the second inverter is coupled to an output end of the first inverter to form a common output end to output the third clock signal; a first controlled switch coupled to the first inverter, the second inverter, and a power source, wherein the first controlled switch is “off” when the first clock signal is in a first state, and is “on” when the first clock signal is in a second state; and a second controlled switch coupled to the first inverter, the second inverter, and ground, wherein the second controlled switch is “on” when the first clock signal is in the first state, and is “off” when the first clock signal is in the second state; wherein the phase of the third clock signal is determined by the phase of the first clock signal and the second clock signal; and wherein the first controlled switch and the second controlled switch serve to avoid a short-circuit current of the phase-interpolation circuit.