Patent ID: 7934184

Claim:
A method for designing an integrated circuit using a library of cells, wherein at least one of said cells is modified by a process carried out by instructions stored in or on a computer-readable storage medium executed by a processor, comprising the steps of: (a) obtaining at least one parameter related to a given cell having at least one feature; (b) determining an uncertain region based on said parameter, said uncertain region being an area near said given cell where at least one feature from at least one neighboring cell, if located within said uncertain region, affects implementation of said at least one feature of said given cell; (c) determining a plurality of computer-generated features at least partially within said uncertain region to determine one or more candidate areas indicating portions of said given cell for further processing, comprising: selecting a plurality of control points of said given cell; determining a performance metric value at each control point; comparing said performance metric values to tolerances of said given cell; determining invalid control points based on said comparing; and mapping said invalid control points to candidate areas on said given cell; and (d) outputting said given cell and said candidate areas to produce a modified cell.