Patent ID: 8144480

Claim:
A method of making a multi-layer embedded capacitance and resistance substrate core, the steps comprising: a) providing a Laser drillable dielectric having an upper surface and a lower surface; b) disposing a first resistance layer on the upper surface of said Laser drillable dielectric; c) disposing a first electrically conductive layer on said first resistance layer; d) laminating said laser drillable dielectric, said first resistance layer and said first electrically conductive layer to form a first resistance structure; e) applying and developing a first resist to said first electrically conductive layer; f) selectively etching said first electrically conductive layer; g) stripping said first resist from said first electrically conductive layer; h) disposing a first copper-coated capacitance layer on said first electrically conductive layer; i) laminating said first copper-coated capacitance layer and said first resistance structure; j) applying and developing a second resist on said first resistance structure; k) stripping said second resist; and l) selectively etching said first copper-coated capacitance layer.