Patent ID: 8250403

Claim:
Device storage device using nonvolatile memories, comprising: N nonvolatile memories electrically connected to N channels, respectively, where N is a number greater than one; and a controller that controls storing, erasing and reading operations of the N nonvolatile memories, wherein the controller receives a unit of input data and divides the unit of input data into N data sub-units and stores the N data sub-units in the N nonvolatile memories, respectively, via the corresponding N channels, and wherein the controller comprises: an error correction engine that generates parity information corresponding to the unit of input data; and a direct memory access (DMA) control unit that divides the unit of input data into the N sub-units, divides the parity information into N parity sub-units, and transmits the N parity sub-units to the N nonvolatile memories, respectively, via the N channels.