Patent ID: 7924180

Claim:
A decoder for decoding an input bit stream into a plurality of symbols in parallel, comprising: a multi-length generator for receiving the input bit stream to generate a first code with a predetermined codeword length, generating an array having a plurality of second codes with the predetermined codeword length, wherein the second codes of the array are obtained by left shifting the input bit stream with respect to each of a plurality of shift bits, and the shift bits are different integers ranging from one to the predetermined codeword length, calculating a plurality of candidate codeword lengths corresponding to the plurality of second codes respectively, determining a first codeword length corresponding to a first symbol, and selecting a second codeword length corresponding to a second symbol from the plurality of candidate codeword lengths according to the first codeword length; and a processing unit obtaining the first and second symbols corresponding to the first and second codeword lengths respectively.