Patent ID: 8909844

Claim:
An inter-integrated circuit (I2C) bus interface comprising: an I2C master device coupled to an I2C slave device over an I2C bus; and an I2C bus multiplexing circuit coupled to the I2C bus between the I2C master device and the an I2C slave device, wherein the I2C bus multiplexing circuit comprises: a buffer coupled to a signal path from a I2C bus and configured to store an I2C signal from an I2C master device; a frequency detector additionally coupled to the signal path from the I2C bus configured to detect a clock frequency of the I2C signal from the I2C master device; port selection logic coupled to the frequency detector and configured to generate a select control command based on the detected clock frequency; and a multiplexer coupled to the buffer and a plurality of ports, the multiplexer configured to route the I2C signal from the I2C master device to one of the plurality of ports.