Patent ID: 7459952

Claim:
A clock signal generating device operable to supply four clock signals with a repeating first edge and second edge to a switched capacitor circuit, comprising: a common mode delayed clock signal generator operable to generate a common mode delayed clock signal having a first edge delayed a first variable discharge delay from the first edge of a common mode reference clock signal; an opposite phase delayed clock signal generator operable to generate an opposite phase delayed clock signal having a first edge delayed a second variable discharge delay from the first edge of an opposite phase reference clock signal; a common mode reference clock signal generator operable to generate a common mode reference clock signal having a second edge delayed a first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal; an opposite phase reference clock signal generator operable to generate the opposite phase reference clock signal having a second edge delayed a second variable non-superimposed delay from the first edge of the common mode delayed clock signal; and a control signal generator operable to generate a first discharge control signal for controlling said common mode delayed clock signal generator and to change the first variable discharge delay, a first non-superimposed control signal for controlling said common mode reference clock signal generator and to chance the first variable non-superimposed delay, a second discharge control signal for controlling said opposite phase delayed clock signal generator and to change the second variable discharge delay, and a second non-superimposed control signal for controlling said opposite phase reference clock signal generator and to change the second variable non-superimposed delay; wherein said common mode delayed clock signal generator generates the common mode delayed clock signal with a second edge delayed substantially the first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal, and said opposite phase delayed clock signal generator generates the opposite phase delayed clock signal with a second edge delayed substantially the second variable non-superimposed delay from the first edge of the common mode delayed clock signal.