Patent ID: 8868835

Claim:
A cache control apparatus which controls a set-associative cache memory shared by a plurality of processors, wherein the cache memory includes a plurality of ways, said cache control apparatus comprising a cache allocation control unit configured to perform a cache allocation process of allocating each of the ways to one or more of tasks which are executed by the processors, wherein: the ways are divided into groups that are memory macrocells, each of the groups including one or more of the ways, said cache allocation control unit is configured to search for an unallocated way, in a case where said cache allocation control unit finds an unallocated way which is included in one of the groups and the one of the groups includes a way allocated to one of the tasks which is executed by a corresponding one of the processors, said cache allocation control unit is configured to allocate the found unallocated way to a corresponding one of the tasks which is executed by the corresponding one of the processors, and in a case where said cache allocation control unit finds an unallocated way which is included in one of the groups and the one of the groups does not include any one of the ways allocated to the tasks, said cache allocation control unit is configured to assign one of the tasks to the found unallocated way.