Patent ID: 8205801

Claim:
A semiconductor device comprising: a circuit portion; a logic portion to which a demodulated signal is input from the circuit portion; and a memory portion connected to the logic portion through a plurality of signal lines, wherein the plurality of signal lines comprise reading signal lines and at least one writing signal line, wherein the number of the reading signal lines is greater than the number of the writing signal line, wherein the number of the reading signal lines is n (where n is an integer equal to or greater than 2), wherein the semiconductor device has a transfer rate of α bps, wherein the demodulated signal is decoded in the logic portion with use of a first clock frequency Kα Hz (where K is an integer equal to or greater than 1), and wherein data stored in the memory portion is read through the reading signal lines with use of a second clock frequency Lα/n Hz (where L is an integer satisfying L/n<K).