Patent ID: 6855979

Claim:
A memory device comprising: a substrate; a gate located over the substrate; a first charge storage structure located over an insulating layer on the substrate, at least a portion of the first charge structure located under a first portion of the gate, a second charge storage structure located over the substrate, at least a portion of the second charge storage structure located under a second portion of the gate, the second charge storage structure is located apart from the first charge storage structure; wherein the gate includes a third portion located between the first portion of the gate and the second portion of the gate; a gate dielectric, a first portion of the gate dielectric located between the substrate and the first charge storage structure, a second portion of the gate dielectric located between the substrate and the second charge storage structure, a third portion of the gate dielectric located between the substrate and the third portion of the gate, wherein the third portion of the gate dielectric at a location where the gate is closest to the substrate, has a thickness that is different from a thickness of first portion of the gate dielectric and a thickness of the second portion of the gate dielectric.