Patent ID: 7739565

Claim:
A circuit, comprising: a configuration memory coupled to an array of programmable logic and interconnect resources that is configurable to implement a selected one of a plurality of user designs, the configuration memory adapted to store configuration data that configures the array of programmable logic and interconnect resources to implement the specified user design; a checker coupled to the configuration memory and adapted to calculate a sequence of checksums from the configuration data that is stored in the configuration memory; and a redundant-logic detector coupled to the checker and adapted to indicate corruption of the configuration data stored in the configuration memory in response to at least two consecutive checksums in the sequence not matching a reference value; wherein the redundant-logic detector includes at least two counters and a voter, each counter adapted to count a number of consecutive checksums in the sequence that do not match the reference value, the voter coupled to the two counters and adapted to indicate the corruption of the configuration data stored in the configuration memory in response to at least one of the two counters having a value that is not less than a limit value.