Patent ID: 8274148

Claim:
A semiconductor module comprising: a single wiring layer having a predetermine pattern; a first bump electrode formed integrally with said wiring layer on one face of said wiring layer; a first circuit element mounted in a state such that an electrode forming surface of said first circuit element is disposed counter to the one face of said wiring layer, an element electrode directly electrically connected to said first bump electrode being provided on the electrode forming surface thereof; a second bump electrode formed integrally with said wiring layer on the one face thereof on a periphery of said first circuit element, the length of protrusion of said second bump electrode being greater than that of said first bump electrode; and a second circuit element mounted above said first circuit element in a state such that an electrode forming surface of said second circuit element is disposed counter to the one face of said wiring layer, an element electrode directly electrically connected to said second bump electrode being provided on the electrode forming surface thereof.