Patent ID: 8010591

Claim:
A single-ended multiplier circuit comprising: a current source having one terminal connected to a first reference voltage and a second terminal; a load having one terminal connected to a second reference voltage and a second terminal configured as a single-ended output terminal; a first G 4 -FET comprising a front gate, a back gate, a first junction gate, a second junction gate, a source, and a drain; and a second G 4 -FET comprising a front gate, a back gate, a first junction gate, a second junction gate, a source, and a drain; the first and second junction gates of the first G 4 -FET are connected to each other; the back gates of the first and second G 4 -FETs are connected to each other; the first and second junction gates of the second G 4 -FET are connected to each other; the sources of the first and second G 4 -FETs are connected to the second terminal of the current source; and the drains of the first and second G 4 -FETs are connected to the second terminal of the load; the single-ended multiplier circuit configured to provide as an output a signal proportional to a product of a first input voltage difference applied to the front gates of the first and second G 4 -FETs and a second input voltage difference applied to the first junction gates of the first and second G 4 -FETs.