Patent ID: 7122415

Claim:
A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising: forming a first conductive layer, the first conductive layer being to provide one or more floating gates for the nonvolatile memory; forming a multilayered dielectric layer over the first conductive layer; forming a second conductive layer separated from the first conductive layer by the multilayered dielectric layer, the conductive layer providing one or more control gates for the nonvolatile memory; wherein said forming of the multilayered dielectric layer includes: (a) forming a second dielectric layer composed of a silicon oxide insulator and having a corresponding upper surface; (b) modifying said upper surface of the second dielectric layer so as to form a hydroxy-terminated surface structure (Si—O—H) on the top of said upper surface; (c) chemisorbing to said hydroxy-terminated surface structure of the upper surface, a metal-containing and chlorine-containing precursor, where an oxide of said metal defines a high dielectric constant material whose respective dielectric constant is greater than a dielectric constant associated with said second dielectric layer; (d) purging away excess amounts of the metal-and-chlorine-containing precursor from the proximity of the surface to which said immediately previous chemisorbing was applied so as to thereby leave behind a monolayer of said precursor; (e) oxidizing the left behind monolayer of said step (d) so as to thereby produce a corresponding stoichiometric monolayer of said metal oxide adhered to the surface to which said immediately previous chemisorbing was applied; (f) chemisorbing to the monolayer of said metal oxide produced in step (e) more of said metal-containing and chlorine-containing precursor; and (g) repeating steps (d) through (f) a predefined number of times so as to produce a desired thickness of said metal oxide defining said high-k dielectric layer adhered to said second dielectric layer.