Patent ID: 7094693

Claim:
A method for manufacturing a semiconductor device, the device comprising MOSFET structure having an F-containing NiSi layer formed on diffusion regions and on gate electrodes, a depth from the bottom of the F-containing NiSi layer to the junction position of the diffusion regions being confined within the range of 20 to 100 nm, the method comprising: forming the gate electrodes above a semiconductor substrate with a gate insulation film being interposed between the semiconductor substrate and the gate electrodes; forming the diffusion regions by introducing an impurity into the semiconductor substrate with the gate insulating film and the gate electrodes being employed as a mask; forming a F-containing layer on a surface layer of a silicide-forming region by ion-implanting F atoms at a dosage of 8.0×10 13 cm −2 or more in the silicide-forming region of silicon for forming the silicide; depositing a Ni film on the F-containing layer without heat-treating the F-containing layer; heat-treating the Ni film to turn the silicon of the silicide-forming region into NiSi, thereby forming the F-containing NiSi layer on diffusion regions and on gate electrodes; and subjecting the F-containing NiSi layer to a heat treatment for a period of time equal to or shorter than, an allowable duration defined as a function of junction depth and temperature by the following formula (A): t a =Dj 2 /Exp(34.7−2.35×10 4 /Ta )+68 (A) (wherein t a is the allowable duration (minutes); Dj is a depth (nm) of the position of junction as measured from the bottom of the NiSi layer; and Ta is a heat treatment temperature (K: Kelvin)).