Patent ID: 7451360

Claim:
An apparatus monitoring an internal control signal of memory device, comprising: an input signal receiving unit for receiving a first signal generated by a burst operation command and N−1 (where, N is a burst length) second signals subsequently generated after the first signal is generated, and outputting a third signal which is synchronized with the first and second signals; a pulse width adjustment unit for receiving the third signal output from the input signal receiving unit, selecting a delay path of the third signal in accordance with a control signal which is corresponding to a variation of an operating frequency of the memory device, and outputting the third signal changed a pulse width by passing through the delay path; a signal transferring unit for buffering a signal output from the pulse width adjustment unit; an output unit for receiving a signal output from the signal transferring unit and outputting a fourth signal for controlling an operation of a data bus; and an output buffer for receiving and transferring the fourth signal externally of the memory device.