Patent ID: 8854083

Claim:
A sensing amplifier circuit, comprising a bit line, configured to receive charging and discharging signals and defining a bit line voltage (VBL); a sensing amplifier comprising a first p-channel transistor, a second p-channel transistor, a third p-channel transistor connected to the bit line, a fourth p-channel transistor, a fifth p-channel transistor, a sixth p-channel transistor, a first n-channel transistor, a second n-channel transistor, and a third n-channel transistor wherein the second, third, and fourth p-channel transistors and the first n-channel transistors are mutually connected defining a node (Q) wherein the node Q is charged to an external VDD in a pre-charge stage of operation and wherein the sensing amplifier is connected to the bit line and configured to receive the bit line voltage and a dynamic reference voltage (VREF); and a dynamic reference voltage generator comprising a seventh p-channel transistor, an eighth p-channel transistor, a ninth p-channel transistor connecting the bit line to VDD, a tenth p-channel transistor, a capacitor capacitively coupled to the bit line and VREF so as to store a voltage difference between VBL and VREF, and an inverter wherein the fifth, sixth, and seventh p-channel transistors and the third n-channel transistor are mutually connected defining a node (QB) wherein the node QB is charged to VREF in the pre-charge stage of operation and wherein the ninth and tenth p-channel transistors and the capacitor are mutually connected defining a node BLi wherein, in a read operation, when a read value is logic 1, VBL and the node Q is at VDD such that, when the ninth p-channel transistor is turned on, the node BLi is at VDD and the node QB is at VREF and, when the read value is logic 0, VBL drops to VREF and the node Q is at VREF and when the ninth p-channel transistor is turned on, the node BLi and the node QB are coupled to VDD.