Patent ID: 8479067

Claim:
A test architecture for testing of an integrated circuit design, the test architecture comprising: a plurality of scan chains; a plurality of cyclical cache chains; a decompressor for receiving scan inputs and mapping the scan inputs to the plurality of scan chains and the plurality of cyclical cache chains; a compressor for receiving outputs of the plurality of scan chains and the plurality of cyclical cache chains, and generating scan outputs; inverting logic for inverting one or more values from the cyclical cache chains, the inverting logic generating a subset of the scan inputs for the decompressor; and control logic for selecting between a linear mode and a cyclical mode, wherein in the linear mode, only top level scan inputs are mapped to the scan chains, the top level scan inputs including any external source scan inputs, and wherein in the cyclical mode, the outputs of the plurality of cyclical cache chains and the top level scan inputs are mapped to the scan chains.