Patent ID: 6912626

Claim:
An active memory device comprising: a main memory; a plurality of processing elements, each of said plurality of processing elements being coupled to a respective portion of said main memory by a single bit connection; and a circuit coupled between said main memory and said plurality of processing elements, said circuit writing data from said plurality of processing elements to said main memory in a horizontal mode and reading data stored in said main memory in a horizontal mode from said main memory to said plurality of processing elements, said circuit comprising a plurality of circuits, each of said plurality of circuits being associated with a respective one of said plurality of processing elements, each of said plurality of circuits passing data between its associated respective one of said plurality of processing elements and said main memory, each of said plurality of circuits comprising: a first multiplexer having a plurality of inputs, each of said plurality of inputs being coupled to an output of a respective one of a plurality of logic circuits, and an output coupled to its associated respective one of said plurality of processing elements; and wherein each of said plurality of logic circuits comprises: a first input, said first input being coupled to a respective one of a plurality of data buses, each of said plurality of data buses being coupled to said main memory; an output; a second multiplexer having a first input coupled to said associated respective one of said plurality of processing elements and a second input coupled to said input of said logic circuit; a first register having an input coupled to an output of said second multiplexer and an output coupled to said output of said logic circuit; a first tri-state device having an input coupled to said output of said first register and an output coupled to said respective one of said plurality of data buses; and a second tri-state device having an input coupled to said output of said first register and an output coupled to one of said plurality of data buses and a third input of said second multiplexer.