Patent ID: 8792288

Claim:
A system on chip (SoC) comprising a memory array, wherein the memory array comprises: n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data; m bit lines each coupled to a corresponding one of the m columns of bit cells; m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit, wherein the m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and wherein the m drivers are operable to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits; wherein each of the m drivers further comprise a transfer gate configured to transfer an offset voltage into a sense node of the bitcell during a read access in response to a control signal.