Patent ID: 8049526

Claim:
A method for implementing optimized speed sorting of microprocessors at a wafer level test comprising: measuring a combination of speed-predicting metrics for the microprocessors at the wafer level test in the manufacturing process of the microprocessors including measuring a quiescent current (IDDQ) for the microprocessors at the wafer level test and measuring a period of a ring oscillator test structure (PSRO) for the microprocessors at the wafer level test; and using said measured combination of speed-predicting metrics to identify defective microprocessors, and to sort microprocessors into predefined speed bins including comparing the measured quiescent current (IDDQ) with a second threshold level; and said second threshold level is a calculated value based upon the measured period of a ring oscillator test structure (PSRO) for the microprocessors at the wafer level test.