Patent ID: 8335291

Claim:
A memory controller comprising: a clock transmitting block configured to transmit a clock signal to a memory device through a clock signal line; a plurality of data transceiver blocks, each of the data transceiver blocks configured to transmit a data signal to the memory device through a respective data signal line; a phase information receiver block configured to receive phase information from the memory device through a phase information signal line that is separate from the data signal line, the phase information being generated with an edge sampling clock signal, a data sampling clock signal and the data signal, and the edge sampling clock signal having a half-period phase difference with the data sampling clock signal; and a per-pin deskew block outputting a respective phase control signal to each of the data transceiver blocks, wherein each of the data transceiver blocks is responsive to the respective phase control signal and the phase information to individually control the phase of the respective data signal transmitted by the corresponding transceiver block.