Patent ID: 8471607

Claim:
A frequency divider architecture comprising: a first loop-back flip-flop circuit comprising: a first plurality of N flip-flops connected in a first series such that a Q output of each of the N flip-flops in the first series is connected to a D input of an immediately following flip-flop in the first series of flip-flops, and wherein a first loop-back connection connects the Q output of a last flip-flop in the first series with a D input of a first flip-flop in the first series of flip-flops; a first reset signal line connected to a set input of each of the N flip-flops in the first series of flip-flops, the first reset signal line adapted to reset each of the N flip-flops to a first logic level or a second logic level in a first predetermined configuration; a clock signal input line adapted to provide an input clock signal, the clock signal input line connected to each of the N flip-flops in the first series of flip-flops such that the N flip flops in the first series of flip-flops are clocked on a rising clock edge of the input clock signal; and a first clock output line connected to the first loop-back connection; a second loop-back flip-flop circuit comprising: a second plurality of M flip-flops connected in a second series such that a Q output of each of the M flip-flops in the second series is connected to a D input of an immediately following flip-flop in the second series of flip-flops, and wherein a second loop-back connection connects the Q output of a last flip-flop in the second series with a D input of a first flip in the second series of flip-flops; a second reset signal line connected to each of the M flip-flops in the second series of flip-flops, the second reset signal line adapted to reset each of the M flip-flops to a first logic level or a second logic level in a second predetermined configuration; the clock signal input line being connected to each of the M flip-flops such that the M flip-flops are clocked on a falling clock edge of the input clock signal; and a second clock output line connected to the second loop-back connection; and an OR gate having, a first input of the OR gate connected to the first clock output line and a second input of the OR gate connected to the second clock output line, and having an output for providing an output clock signal having a period that is an integer multiple of an input period of the input clock signal provided on the clock signal input line, wherein N and M are integers greater than 1.