Patent ID: 7894255

Claim:
A memory array comprising: a plurality of memory cells, each memory cell comprising a thyristor body and a gate, the thyristor body comprising a first end region, a second end region, a first base region, and a second base region, the gate being positioned over and insulated from at least a portion of one of the first and the second base regions and offset from another of the first and the second base regions; at least one word line; at least one bit line; at least one third line; the first end region being connected to one of the at least one word line, bit line and third line, the second end region being connected to another of the at least one word line, bit line, and third line, and the gate being connected to remaining of the at least one word line, bit line and third line; wherein the memory cell is positioned between a first isolation region and a second isolation region in a substrate; wherein the thyristor body is formed in a semiconductor region of the substrate that extends from the first isolation region to the second isolation region; wherein the semiconductor region includes a well that has a same type of conductivity as the another of the first and the second base regions; wherein the thyristor body is formed in the well; and wherein a remaining portion of the well after formation of the thyristor body extends below the thyristor body.