Patent ID: 7242231

Claim:
A clock generator, comprising: a voltage controlled oscillation module, generating a plurality of first clocks (D 0 ˜D m ) with a first frequency (f 0 ), wherein the first clocks D i and D i-1 have a fixed phase difference and 1<i<m; a logic control circuit, outputting a set of corresponding clocks arranged by a corresponding sequence according to the first clocks and a binary code; a clock synthesizer generating a second clock with a second frequency (f 1 ) according to the set of corresponding clocks, wherein f ⁢ ⁢ 1 = A B ⁢ f ⁢ ⁢ 0 , A<B and A and B are positive integers, and a frequency divider receiving the second clock and one of the first clocks selectively and generating a third clock with a third frequency (f 2 ), wherein f ⁢ ⁢ 2 = 1 2 N ⁢ f ⁢ ⁢ 0 , N is a positive integer and N>1.