Patent ID: 7333106

Claim:
An apparatus, comprising: a Z-buffer memory, the Z-buffer memory comprising a plurality of elements, wherein each of the plurality of elements is configured to store data corresponding to a pixel; a set of status bits that is separate from the Z-buffer memory, each status bit of the set of bits corresponding to a block of the Z-buffer memory, wherein at least one of the blocks comprises a set of elements in the plurality of elements, and wherein the block has a size of n×m, wherein n and m are each any number greater than 1; an initialization register to store an initial Z value, wherein the initialization register is separate from the Z-buffer memory; and a control logic coupled to the Z-buffer memory, the set of status bits, and the initialization register, the control logic to retrieve the initial Z value from the initialization register when access to the block of the Z-buffer memory with a corresponding one of the set of status bits being in a first state is requested, wherein the control logic is configured to store the initial Z value into the initialization register during an initialization of the Z-buffer memory, and to set the status bits to the first state, while avoiding writing the initial Z value to the Z-buffer memory.