Patent ID: 7119856

Claim:
A demodulator connecting to a N-bits analog-to-digital converter, comprising: N 2 data pins receiving data signals from the N-bits analog-to-digital converter; a first clock pin receiving a first clock signal from the N-bits analog-to-digital converter; a first select pin receiving a first control signal from the N-bits analog-to-digital converter; a second select pin receiving a second control signal from the N-bits analog-to-digital converter to select a data signal type with the first control signal; a second clock pin transmitting a second clock signal to the N-bits analog-to-digital converter; a data select pin transmitting a data control signal to set up the N-bits analog-to-digital converter with the second clock signal; a gain control pin transmitting a gain control signal to adjust the dc gain of the N-bits analog-to-digital converter; and a voltage level control pin transmitting a voltage level control signal to adjust the voltage level of the N-bits analog-to-digital converter.