Patent ID: 7141821

Claim:
A semiconductor device including a CMOS circuit having an NTFT and a PTFT, each of the NTFT and the PTFT including an active layer, an insulation film in contact with the active layer, and a wiring in contact with the insulation film, wherein only the NTFT includes a side wall spacer on a side of the wiring, the active layer of the NTFT includes a channel forming region and at least three kinds of impurity regions each containing an element belonging to the group 15 at a different concentration, the impurity region in contact with the channel forming region among the three kinds of impurity regions overlaps by way of the insulation film with the side wall, the active layer of the PTFT includes a channel forming region and two kinds of impurity regions each containing an element belonging to the group 13 at an identical concentration, and an element used for crystallization of the active layer of the NTFT and the active layer of the PTFT is present at a concentration of 1×10 17 to 1×10 20 atoms/cm 3 in one of the impurity region most remote from the channel forming region of the NTFT and in one of the impurity region most remote from the channel forming region of the PTFT.