Patent ID: 7782667

Claim:
A method of operating a flash memory device including a multi-level cell (MLC) capable of storing plural bits of data therein, the method comprising: performing a first read operation of a main cell and a first flag cell by a first read voltage or a second read voltage that is higher than the first read voltage, wherein a first data of the main cell read by the first read voltage becomes a first bit data when the first flag cell has a non-program state, and a first data of the main cell read by the second read voltage becomes the first bit data when the first flag cell has a program state; and performing a second read operation of the main cell and a second flag cell by one or both of the first read voltage and a third read voltage that is higher than the second read voltage, wherein a second data of the main cell read by both of the first read voltage and the third read voltage becomes a second bit data when the second flag cell has a program state, or the second bit data is fixed to a predetermined set data when the second flag cell has a non-program state.