Patent ID: 7450442

Claim:
A semiconductor memory device, comprising: a data input buffer for receiving an external data in response to a driving signal; a DQS input buffer for receiving an external data strobe signal in response to the driving signal; a delay unit for delaying an output signal of the DQS input buffer by a predetermined time; a division unit for dividing an output signal of the DQS input buffer by two to output a plurality of internal data strobe signals; and a data align unit for receiving output data from the delay unit and the internal data strobe signals from the division unit, and aligning the received output data of the delay unit in response to the corresponding internal data strobe signals to output a plurality of align data, wherein the plurality of internal data strobe signals are first to fourth internal data strobe signals having two times the period of the output signal of the DQS input buffer and a phase difference of 90° of each other.