Patent ID: 8144514

Claim:
A one-transistor (1T) floating-body Dynamic Random Access Memory (DRAM) cell device having a dual gate structure, the 1T floating-body DRAM cell device comprising: a floating body which stores information in the DRAM cell device; a source and a drain formed on respective sides of the floating body; a gate insulating layer formed on the floating body; a gate electrode formed on the gate insulating layer; a gate stack formed under the floating body, the gate stack including a charge storage node which stores electric charges; and a control electrode partially or completely surrounded by the gate stack, the charge storage node completely surrounding the control electrode; wherein the DRAM cell device performs “write0” and “write1” operations by storing information in the floating body or a read operation by reading the information stored in the floating body; or wherein the DRAM cell device performs a non-volatile program operation by storing electric charges in the charge storage node of the gate stack or a non-volatile erase operation by erasing the electric charges stored in the charge storage node.