Patent ID: 7944024

Claim:
A semiconductor device including an MISFET, comprising: (a) a silicon-germanium layer formed over a semiconductor substrate; (b) a strained silicon layer formed over the silicon-germanium layer; (c) a gate insulating film formed over the strained silicon layer; (d) a gate electrode formed over the gate insulating film; and (e) a source region and a drain region; wherein the strained silicon layer is thicker than a critical film thickness at which misfit dislocations occur and the misfit dislocations exist on an interface between the strained silicon layer and silicon-germanium layer, wherein the source region includes a first region and a second region such that the second region is formed between a channel forming region and the first region, wherein the first region is formed in the strained silicon layer and in the silicon-germanium layer, wherein the second region is formed in the strained silicon layer and not formed in the silicon-germanium layer, and wherein the drain region is formed in both the strained silicon layer and the silicon-germanium layer so that the source region and the drain region are not symmetric.