Patent ID: 7523029

Claim:
A logic verification system comprising: a storage section for storing an object code compiled from an behavioral level description written in a programming language, the object code being used for specification verification by simulation on a CPU in a design phase, an RT level description generated from the behavioral level description, correspondence information which specifies information on pairs of fragments of descriptions to be compared which are included in the behavioral level description and the RT level description and which specifies information on pairs of signals to be compared for each description pair, and compile information which includes mapping information which specifies information on a pair of a description fragment of the behavioral level description and a code portion of the object code and which specifies information on a pair of a signal in the behavioral level description and a variable in the object code; a first logic cone extraction section configured to extract first logic cones of variables by: searching a code portion and the variables of the object code corresponding to each fragments of descriptions and each signals of behavioral level description to be compared which are specified by the correspondence information by referencing the compile information, setting initial symbol values in the variables, performing symbolic simulation from the start to end points of the code portion to produce symbol values when the variable symbolic simulation ends, and using the symbol values as the first logic cones of the variables; a second logic cone extraction section configured to extract second logic cones each for the signals for each fragments of description of RT level description to be compared which are specified by the correspondence information; a logic cone comparison section configured to select a corresponding logic cone, as a first logic cone, from among the logic cones extracted by the first logic cone extraction section by referencing the compile information, to select a corresponding logic cone, as a second logic cone, from among the logic cones extracted by the second logic cone extraction section by referencing the correspondence information, and to compare the first logic cone and the second logic cone, for each signal and description fragment to be compared in the behavioral level description and the RT level description which are specified by the correspondence information; and means for determining, based on the comparison of the first logic cones and the second logic cones, whether the RT level description that has been designed in a behavioral synthesis phase is acceptable to be used in a manufacturing phase for the logic circuits, wherein the RT level description that has been designed in the behavioral synthesis phase is determined to be acceptable to be used in a manufacturing phase for the logic circuits when the first logic cones are logically equivalent to the second logic cones.