Patent ID: 7765511

Claim:
A processor-based method for implementing a design in an integrated circuit, comprising: storing timing data that represents timing variations between logically-equivalent-programmable resources of the integrated circuit, the timing variations correlated to physical locations of the logically-equivalent-programmable resources; wherein the integrated circuit is a programmable logic integrated circuit (IC), and the logically-equivalent-programmable resources include configurable logic located on an integrated circuit die of the integrated circuit; identifying a plurality of groups of logically-equivalent-programmable resources that are each distinguishable from other groups of logically-equivalent-programmable resources with regard to respective timing variations, wherein plurality of groups of logically-equivalent-programmable resources are each defined by a performance parameter; comparing a respective performance parameter between logically-equivalent-programmable resources of the integrated circuit in the groups; mapping, placing and routing logic of the design on resources of the integrated circuit, wherein the mapping, placing and routing includes, for an implementation of at least one subset of logic of the design, selecting between logically-equivalent-programmable resources of the integrated circuit based on a result of the step of comparing a respective performance parameter; excluding, from the mapping, placing and routing any subset of logic of the design, one of the groups that includes one or more of the logically-equivalent-programmable resources that have timing variations exceeding a threshold level; generating an implementation of the design from the logic of the design placed and routed on the resources of the integrated circuit; and storing the implementation of the design, wherein the comparing, mapping, placing and routing, generating, and storing are performed on a processor.