Patent ID: 7325218

Claim:
A wiring method comprising: a wiring processing step wherein a first adjacent spacing condition which does not become a wiring violation is given and a wiring process is executed on the basis of a net list of a semiconductor circuit; a noise analyzing step wherein error nets in which noise errors have occurred are extracted by analyzing noises of a wiring formed in said wiring processing step; a wiring condition changing step wherein a second adjacent spacing condition for eliminating the noise errors of the error nets extracted in said noise analyzing step is set; a re-wiring processing step wherein the second adjacent spacing condition is given to said error nets, said first adjacent spacing condition is given to nets other than said error nets, and the wiring process is executed again on the basis of said net list, wherein in said wiring condition changing step, a parameter file is prepared in which the second adjacent spacing condition is set having a different value according to the priority of a net type or a wiring layer, and in said re-wiring processing step, the second adjacent spacing condition of the parameter file is given to the error nets.