Patent ID: 7943973

Claim:
An integrated circuit comprising: a first channel forming region that is undoped or doped disposed in a substrate; a first doped connection region that is doped in accordance with a first doping type and with a greater dopant concentration than the first channel forming region, the first doped connection region being disposed adjacent the first channel forming region; a second doped connection region that is doped in accordance with a second doping type that is different than the first doping type, the second doped connection region having a greater dopant concentration than the first channel forming region, the second doped connection region being disposed adjacent the first channel forming region, wherein the first channel forming region is disposed between the first doped connection region and the second doped connection region; a first control region, wherein the first control region comprises a first sidewall and an opposite second sidewall, and wherein the first sidewall is a planar surface and the second sidewall is a non-planar surface; an electrically insulating first insulation region arranged between the first control region and the first channel forming region, the first channel forming region, the first and the second doped connection regions, the first control region, and the electrically insulating first insulation region forming a first tunnel field effect transistor; a second channel forming region that is undoped or doped; a third doped connection region that is doped in accordance with the first doping type and with a greater dopant concentration than the second channel forming region; a fourth doped connection region that is doped in accordance with the second doping type the fourth doped connection region having a greater dopant concentration than the second channel forming region, wherein the second channel forming region is disposed between the third doped connection region and the fourth doped connection region; a second control region, wherein the second control region comprises a third sidewall and an opposite fourth sidewall, and wherein the third sidewall is a planar surface and the fourth sidewall is a non-planar surface; and an electrically insulating second insulation region arranged between the second control region and the second channel forming region, wherein the second channel forming region, the third and the fourth doped connection regions, the second control region, and the electrically insulating second insulation region form a second tunnel field effect transistor disposed on the substrate with the first tunnel field effect transistor.