Patent ID: 7339256

Claim:
A semiconductor device comprising: a semiconductor substrate having a main surface; a first insulating layer provided above the main surface, including one or more sub-layers and including conductive first wirings and conductive first plugs, one of the sub-layers having a relative dielectric constant smaller than 3, plural first wirings being on top of respective first plugs; a conductive chip protecting member provided in the first insulating layer, extending between a bottom and a top of the first insulating layer and having a projected shape on the main surface that surrounds a chip region; functional blocks provided in the first insulating layer in the chip region, having at least part of an electrical circuit and formed with using one or more of the first wirings and one or more of the first plugs; and a conductive block protecting member provided in the first insulating layer in the chip region and including a first part and a second part, the first part having a bottom level with the bottom of the first insulating layer and a top level with a top of each of the first plugs, the second part having a bottom level with a bottom of each of the first wirings and a top level with the top of the first insulating layer and lying on and along the first part, the block protecting member having a projected shape on the main surface that surrounds one of the functional blocks.