Patent ID: 7511376

Claim:
A chip package comprising: a metal substrate; only one die; an adhesive material adhering a bottom surface of said only one die to said metal substrate; a first polymer layer over said metal substrate, wherein said only one die is in said first polymer layer; a second polymer layer on a top surface of said only one die, on said first polymer layer and across an edge of said only one die; a circuit layer on said second polymer layer, over said top surface of said only one die, over said first polymer layer and across said edge of said only one die, wherein said circuit layer comprises an electroplated metal, wherein said circuit layer comprises a portion as a part of a capacitor, and wherein said circuit layer is connected to said only one die through an opening in said second polymer layer; and a third polymer layer on said circuit layer, on said second polymer layer, over said top surface of said only one die, over said first polymer layer and across said edge of said only one die.