Patent ID: 7825453

Claim:
A semiconductor device, comprising: a semiconductor substrate including an active area extending in a predetermined direction, the active area including a first upper surface; a plurality of memory cell transistors formed on the active area, each memory cell transistor including a memory cell gate structure having a first insulating film formed on the first upper surface of the active area, a first gate electrode formed on the first insulating film, a second insulating film formed on the first gate electrode, and a second gate electrode formed on the second insulating film, respectively; select gate transistors formed on the active area adjacent to the memory cell transistors in the predetermined direction, each of the select gate transistors including a select gate structure having a third insulating film formed on the first upper surface of the active area, and a third gate electrode formed on the third insulating film, the third gate electrode including a first and a second electrode portions formed in contact with the third insulating film, the first and second electrode portions being separated from each other in the predetermined direction, an insulator portion formed between the first and the second electrode portions, and a third electrode portion formed on the insulator portion and between the first and the second electrode portions to electrically connect the first and the second electrode portions; a first impurity diffusion layer formed in the first upper surface of the semiconductor substrate and located at a first portion which corresponds to an area between the memory cell gate structure and the first electrode portion of the select gate structure; a second impurity diffusion layer formed in the first upper surface of the semiconductor substrate and located at a second portion which corresponds to an area between the first and second electrode portions of the select gate structure; a trench formed, adjacent to the active area, on the first upper surface of the semiconductor substrate, the trench extending in the predetermined direction; and a fourth insulating film formed in the trench and extending in the predetermined direction, the fourth insulating film having an upper end portion which protrudes from the first upper surface of the semiconductor substrate, wherein the second insulating film is also formed on an upper surface of the fourth insulating film in the memory cell gate structure, the upper surface of the fourth insulating film being substantially covered by the second insulating film, and wherein a height of a second upper surface of the insulator portion is higher than a height of a third upper surface of the third insulating film relative to the first upper surface of the active area.