Patent ID: 7323932

Claim:
A differential amplifier circuit formed on a silicon-on-insulator (SOI) substrate, comprising: a bias section activated and deactivated by an enable signal, outputting a predetermined bias potential when activated, and outputting a first power-supply potential when deactivated; a first metal-oxide-semiconductor (MOS) transistor of a first channel type, having a source receiving the first power-supply potential, a gate receiving the potential output by the bias section, and a drain connected to a first node; a source-tied second MOS transistor of the first channel type, having a source connected to the first node, a gate receiving a first differential input signal, and a drain connected to a second node; a source-tied third MOS transistor of the first channel type, having a source connected to the first node, a gate receiving a second differential input signal, and a drain connected to a third node; a source-tied fourth MOS transistor of the first channel type, having a source connected to the second node, a gate receiving the enable signal, and a drain connected to a fourth node; a source-tied fifth MOS transistor of the first channel type, having a source connected to the third node and, a gate receiving the enable signal, and a drain connected to a fifth node; a source-tied first MOS transistor of a second channel type, having a source receiving a second power-supply potential, a gate connected to the fourth node, and a drain connected to the fourth node; a source-tied second MOS transistor of the second channel type, having a source receiving the second power-supply potential, a gate connected to the fourth node, and a drain connected to the fifth node; and an output section connected to the fifth node, generating an output signal from a potential of the fifth node.