Patent ID: 7479677

Claim:
A non-volatile memory system formed on a semiconductor substrate, comprising: (a) an array of charge storage transistors, comprising: a plurality of eight or more conductive word lines with lengths extending across the substrate in a first direction and neighboring each other in a second direction, the first and second directions being orthogonal with each other, and regions of dielectric charge trapping material sandwiched between the conductive word lines and a surface of the substrate in a manner to provide a plurality of eight or more series connected storage transistors in individual columns extending in the second direction between terminations thereof, and (b) circuits peripheral to the array, comprising: a programming circuit that includes a source of voltages connectable to at least the word lines to cause charge to be transferred into regions of dielectric charge trapping material along an addressed word line and within addressed columns of storage transistors by Fowler-Nordheim tunneling, and a reading circuit including a source of voltages and sensing circuits connectable to at least the word lines and terminations of the columns of storage transistors in a manner that determines a parameter related to a level of charge stored in dielectric regions along an addressed word line and within addressed columns of storage transistors.