Patent ID: 8463837

Claim:
A method for performing a bi-linear interpolation or a motion compensation of a digital image or video, the method comprising: decoding a first shuffle instruction in a computer processor including a memory and a first multiply-add instruction, each of an instruction format comprising a first operand field and a second operand field; responsive at least in part to said first shuffle instruction, generating, in said processor, a first packed data having a first plurality of byte data elements including an a 1 byte data element, and at least two copies of each a 2 , a 3 , and a 4 byte data elements; and responsive to said first multiply-add instruction, wherein the first operand field of said first multiply-add instruction specifies said first packed data and the second operand field specifies a second packed data having a second plurality of byte data elements including at least two copies of each of b 1 and b 2 byte data elements, performing, in said processor, an operation (a 1 ×b 1 )+(a 2 ×b 2 ) to generate a first 16-bit data element of a third packed data, performing an operation (a 2 ×b 1 )+(a 3 ×b 2 ) to generate a second 16-bit data element of the third packed data, and performing an operation (a 3 ×b 1 )+(a 4 ×b 2 ) to generate a third 16-bit data element of the third packed data.