Patent ID: 7488676

Claim:
A method of manufacturing a multi-layered circuit board formed by laminating and combining a plurality of substrates composed of conductive layers and insulating layers through which a connecting hole, for inserting a power terminal of an electronic part to be mounted on a surface of the multi-layered circuit board to connect with a first conductive layer, is to be formed, said method comprising: forming a detecting section having a detecting hole in a second conductive layer, the second conductive layer being positioned toward a back face of the multi-layered circuit board with respect to the first conductive layer; forming a through hole that penetrates from the surface of the multi-layered circuit board to the back face of the multi-layered circuit board so as to contact with a surface conductive layer disposed on the surface of a surface substrate, which is one of the plurality of substrates, positioned at the surface of the multi-layered circuit board and contact with the first conductive layer, the first conductive layer being located between the surface of the multi-layered circuit board and the back face of the multi-layered circuit board, and without contacting the detecting hole by having a diameter smaller than that of the detecting hole; plating an inner surface of the through hole; drilling a hole with a tool having a diameter larger than the diameter of the detecting hole along the through hole from the back side of the multi-layered circuit board while applying a predetermined voltage between the tool and the second conductive layer having the detecting section and to a predetermined depth based on detection of the detecting hole, whereby the connecting hole is formed by the through hole between the surface conductive layer and the first conductive layer where the plating is left on an inner peripheral face of the through hole; wherein the first conductive layer is on a surface side of a second substrate of the plurality of substrates adjacent to the surface substrate and the second conductive layer is on a surface side of a third substrate adjacent to a back side of the second substrate.