Patent ID: 8643121

Claim:
A semiconductor device comprising: a source region and a drain region; a channel region extending between the source region and the drain region; and a gate stack comprising: a gate insulation layer provided over the channel region; and a metal layer insulated from the channel region by the gate insulation layer, wherein the metal layer is formed of HfSi, Mo, Ru, TaC or W, wherein the metal layer contains work function modulating impurities having a concentration profile that varies along a length of the metal layer from the source region to the drain region, wherein the work function modulating impurities comprise (a) As, P, Sb or Te for n-type tuning or (b) Al or B for p-type tuning, and wherein the gate stack has a first work effective function in the vicinity of the source region and/or the drain region and a second, different effective work function toward a center of the channel region.