Patent ID: 7804110

Claim:
A field effect transistor with a heterostructure, comprising: a carrier material, wherein the carrier material includes a first relaxed monocrystalline semiconductor layer made of a first semiconductor material as a topmost layer; a second relaxed monocrystalline semiconductor layer formed on the first relaxed monocrystalline semiconductor layer, wherein the second relaxed monocrystalline semiconductor layer includes a first semiconductor alloy comprising the first semiconductor material and at least one second semiconductor material, where a proportion of the second semiconductor material to the first semiconductor material in the second relaxed monocrystalline semiconductor layer is settable; a first strained monocrystalline semiconductor layer formed on the second relaxed monocrystalline semiconductor layer, wherein the first strained monocrystalline semiconductor layer comprises the first semiconductor material; a second strained monocrystalline semiconductor layer formed on the first strained monocrystalline semiconductor layer, wherein the second strained monocrystalline semiconductor layer includes a second semiconductor alloy comprising the first semiconductor material and at least the second semiconductor material, where a proportion of the second semiconductor material to the first semiconductor material in the second strained monocrystalline semiconductor layer is settable; a gate insulation layer formed on the second strained semiconductor layer; a gate layer formed on the gate insulation layer; and drain/source regions formed laterally with respect to the gate layer at least in the second strained monocrystalline semiconductor layer to define an undoped channel region.