Patent ID: 8683141

Claim:
A semiconductor memory system, comprising: a flash memory comprising a plurality of memory chips, each of the memory chips comprising a plurality of blocks, and each of the plurality of blocks comprising physical pages to store data; and a controller configured to: control a write request to a physical page of the physical pages on the basis of a logical address comprised in the write request; relate a plurality of the physical pages to a first logical page and manage each of the physical pages related to one or more generations of the first logical page; relate a first physical page of the physical pages, which first physical page stores first new data, to a latest generation of the one or more generations of the first logical page; when the controller receives a snapshot request, relate the first physical page, which is related to the latest generation of the first logical page, to a first generation of the first logical page; when the controller receives a write request which targets the first logical page and when the controller has related the first physical page to the first generation of the first logical page, manage the first physical page as a valid page; and when the controller has not related the first physical page to the first logical page of the first generation, manage the first physical page as an invalid page.