Patent ID: 7222226

Claim:
A microprocessor, comprising: a dispatch unit configured to dispatch a plurality of different types of operations including a load operation and a register-to-register move operation, wherein for a given occurrence of a load operation, the dispatch unit is further configured to modify the given occurrence of the load operation to include a register-to-register move operation in response to an indication that a speculative result of the load operation is linked to a data value identified by a first tag, wherein the indication is determined for the given occurrence of the load operation and prior to an address of the load operation being determined for the given occurrence of the load operation; a scheduler configured to receive said plurality of different types of operations, wherein the scheduler is configured to issue the register-to-register move operation in response to availability of the data value; and an execution core configured to execute ones of said plurality of different types of operations, wherein to execute the register-to-register move operation, the execution core is further configured to output the data value and a tag indicating that the data value is the result of the load operation.