Patent ID: 7079615

Claim:
A locked loop system that synchronizes a clocked signal to a reference clock signal, comprising: a phase detector that detects a difference in phase between the clocked signal and the reference clock signal, and generates an output signal indicating the phase difference; a digital counter coupled to the phase detector and having a count value, said digital counter receiving the output signal generated by the phase detector, and in response, modifying said count value and generating a binary output signal indicating said count value; an electronic circuit coupled to said digital counter, said electronic circuit being configured to receive said binary output signal, and in response, generate a thermometer-coded output signal that corresponds to said binary output signal; and a delay line coupled to said electronic circuit, said delay line including a plurality of delay elements that are enabled by said thermometer-coded output signal; wherein said electronic circuit comprises comparator logic including a first comparator and a second comparator, and wherein said first comparator receives said binary output signal from said digital counter, and in response generates multiple threshold values.