Patent ID: 8656078

Claim:
Transaction identifier expansion circuitry for interfacing between a master device and interconnect circuitry used to couple said master device with a plurality of slave devices to enable transactions to be performed, each transaction comprising an address transfer from said master device to a target slave device within said plurality of slave devices, and one or more data transfers between said master device and said target slave device, at least one data transfer being a response transfer from said target slave device to said master device, each transaction having a transaction identifier associated therewith and the interconnect circuitry handling in order transactions having the same transaction identifier, the master device being configured to initiate a sequence of transactions and the transaction identifier expansion circuitry comprising: transaction analysis circuitry, responsive to each transaction in said sequence, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for said transaction, and to map an initial transaction identifier for the transaction to one of a plurality of revised transaction identifiers dependent on the comparison, such that the revised transaction identifier is dependent on the target slave device; and reordering circuitry having buffer circuitry for buffering response transfers received from the interconnect circuitry destined for said master device, each response transfer having the revised transaction identifier associated therewith, the reordering circuitry being configured to reorder the response transfers having regard to the original transaction order of those transactions within said sequence of transactions that had the same initial transaction identifier, prior to provision of each response transfer to said master device, wherein said at least one attribute of the transaction compared by the transaction analysis circuitry comprises an address specified by the address transfer of the transaction, wherein: at least two slave devices from said plurality of slave devices are memory devices, each memory device providing a plurality of pages of memory, and the transaction analysis circuitry is configured to compare said address with predetermined page attributes, and to map said initial transaction identifier to one of said plurality of revised transaction identifiers dependent on the comparison; whereby for transactions within said sequence that have the same initial transaction identifier but access different ones of said at least two slave devices, the transaction analysis circuitry will map the initial transaction identifier to different revised transaction identifiers.