Patent ID: 7718482

Claim:
A method of fabricating a CMOS integrated circuit, comprising: providing a substrate having a semiconductor surface; forming a gate dielectric layer on said semiconductor surface and a polysilicon layer on said gate dielectric layer; patterning said polysilicon to form a plurality of polysilicon comprising gates, wherein said polysilicon layer is patterned while being undoped; providing a first pattern to protect a plurality of PMOS devices and first n-type implanting to dope said gates and source/drain regions for a plurality of NMOS devices; providing a second pattern to protect said PMOS devices and said sources/drains and said gates for a first portion of said NMOS devices while exposing said gates of a second portion of said NMOS devices, second n-type implanting to dope said gates of said second portion of said NMOS devices using said second pattern, and completing fabrication of said integrated circuit.