Patent ID: 7370193

Claim:
A computing system comprising: a CPU communicatively connected to a memory controller being communicatively connected to a memory connected either to an external operating system or to an internal operating system, through a switching unit; an input unit that is able to input a request of switching; a first status thereof defined by states of all variable registers thereof when said computing system is only connected to said internal operating system; a second status thereof defined by states of said all variable registers when said computing system is only connected to said external operating system; a switching unit being communicatively connected to said CPU and all said switches, respectively, has backups of both said statuses, and is able to backup a current status, control said general switch to control all said switches to interrupt all serving programs, then load the other status other than said current status to the computing system, wherein said switching unit has a trigger that is able to generate a non-maskable interrupt to said CPU after said switching unit receives a command of switching from said CPU responding to said request of switching, wherein a switch program is kept in said switching unit, and which has backups of both said statuses, and which, after said CPU receives said non-maskable interrupt, is able to backup a current status, control said general switch to control all said switches to interrupt all serving programs, then load the other status other than said current status to the computing system, and finally control said switching unit to reset said trigger; and a supervising unit being able to monitor an execution process of said switch program running in said CPU, and allow said switch program to proceed if said supervising unit confirms said process has always been in a script of said switch program, or prohibit said switch control unit from any action if said supervising unit fails to confirm.