Patent ID: 8367497

Claim:
A method of manufacturing an integrated circuit, comprising: forming first trench isolation structures in a transistor region of a semiconductor substrate; forming second trench isolation structures in a dynamic random memory (DRAM) region of the semiconductor substrate; forming an etch mask over the transistor region and the DRAM region; patterning the etch mask over the second trench isolation structures to expose a portion of each of the second trench isolation structures with the transistor region remaining protected by the etch mask; removing a portion of the exposed portions to form a gate trench in each of the second trench isolation structures, wherein each of the gate trenches include a first corner formed by the semiconductor substrate and a second corner formed by the trench isolation structure; removing the etch mask from the DRAM region; rounding at least the first corner of each of the gate trenches; forming an oxide layer over a sidewall, the first rounded corner, and the semiconductor substrate adjacent each of the gate trenches; forming a gate oxide over the semiconductor substrate in the transistor region; filling each of the gate trenches with a gate material, the gate material extending over at least the first rounded corner and onto the semiconductor substrate adjacent each of the gate trenches; forming the gate material over the transistor region; patterning the gate material in the DRAM region and the transistor region to form gates; and forming source/drains adjacent the gates.