Patent ID: 8048730

Claim:
A method for manufacturing a semiconductor device, the method comprising: forming an isolation area, defining an NMOS area and a PMOS area, on a semiconductor substrate, and forming a gate insulating layer and a gate on each of the NMOS and PMOS areas; forming a primary gate spacer layer on the semiconductor substrate including the gates, and forming LDD areas at sides of the gates; forming a primary gate spacer at both sides of the gate by etching the primary gate spacer layer after forming the LDD areas; forming a secondary gate spacer layer on the semiconductor substrate including on the gates and the primary gate spacer, and forming source and drain areas at sides of the gate in the PMOS area; forming a second gate spacer at sides of the gates by etching the secondary gate spacer layer after forming the source and drain areas in the PMOS area; and forming source and drain areas at sides of the gate in the NMOS area using the second gate spacer as a mask.