Patent ID: 8726216

Claim:
A computer implemented method comprising: placing, by a place-and-route tool, executed using a computer processor, in dependence upon a cell library and a netlist for an integrated circuit, a power switch cell and a standard cell in a layout of the integrated circuit that will include a doped substrate, wherein the doped substrate will include a plurality of parallel rows of doped wells, and wherein the doped substrate is interleaved among the rows of doped wells and the doping of the wells is of a different type than the doping of the substrate; wherein placing the power switch cell and the standard cell includes: placing the power switch cell in the layout so as to bridge two parallel rows of the doped wells; and placing the standard cell in the layout in a column with the power switch cell, with a first portion of the standard cell facing the power switch cell and placed so as to be positioned on one of the rows of doped wells bridged by the power switch cell and with a second portion of the standard cell placed so as to be positioned on the doped substrate, wherein the first portion comprises logic of a type complementary to the doping of the wells, and the second portion comprises logic of a type complementary to the doping of the substrate; wherein the standard cell has a height equivalent to the height of one of the doped wells, and the power switch cell has a height greater than the standard cell's height; and generating, by the place-and-route tool based on the layout, one or more files for use in integrated circuit fabrication.