Patent ID: 7657783

Claim:
An apparatus for testing a data processing system's ability to recover from cache directory errors, said apparatus comprising: a bus; a memory connected to the bus, the memory storing program code; a CPU connected to the bus; a directory entry stored in a cache directory, said directory entry including an address tag and directory parity that is associated with said address tag; and a cache entry stored in a cache that is accessed using said cache directory, said cache entry including information and cache parity that is associated with said information, wherein said CPU executes said program code for: altering said directory parity to imply bad parity, said bad parity implying that said associated address tag is invalid; altering said information to be incorrect, said cache parity indicating good parity, said good parity implying that said information is valid; and testing said data processing system's ability to recover from errors using said directory entry and said cache entry.