Patent ID: 8707122

Claim:
A nonvolatile memory system comprising: an error correction module configured to receive a data stripe including data units and to generate an error correction code for each data unit of the data stripe for correcting data bit errors in the data unit; a data recovery module configured to generate a parity unit for the data stripe based on the data units of the data stripe for recovering a data unit of the data stripe based on other data units of the data stripe and the parity unit; a nonvolatile memory module coupled to the error correction module and the data recovery module, the nonvolatile memory module configured to store the data stripe, the parity unit, and the error correction codes; the error correction module further configured to read the data stripe and the error correction codes from the nonvolatile memory module in response to a data stripe read request, to correct data bit errors in a data unit of the data stripe if the data unit has a number of data bit errors not exceeding an error correction capacity of the error correction module to generate corrected data units and to provide the corrected data units of the data stripe to the data recovery module if the number of data bit errors of the data unit exceeds the error correction capacity of the error correction module; and the data recovery module further configured to read the parity unit from the nonvolatile memory module in response to a data stripe read request and to recover the data unit of the data stripe based on the corrected data units of the data stripe and the parity unit if the data unit has a number of data bit errors exceeding the error correction capacity of the error correction module.