Patent ID: 8900957

Claim:
A method of fabricating a semiconductor device, comprising: forming first and second gate structures over first and second regions of a substrate, respectively; forming spacers on sidewalls of the first and second gate structures; forming a first capping layer over the first and second gate structures; forming a second capping layer over the first capping layer; forming a first protection layer over the second region to protect the second gate structure; removing the first and second capping layers over the first gate structure; removing the first protection layer over the second region; epitaxially (epi) growing silicon on exposed portions of the substrate in the first region; removing the first and second capping layers over the second gate structure by wet etching, wherein the wet etching selectively removes the first and second capping layers but not the spacers disposed on the sidewalls of the first gate structure; after removing the first and second capping layers over the second gate structure by wet etching, forming a third capping layer over the first and second gate structures; forming a fourth capping layer over the third capping layer; forming a second protection layer over the first region to protect the first gate structure; removing the third and fourth capping layers over the second gate structure; etching a recess in the substrate at either side of the second gate structure; removing the second protection layer over the first region; epitaxially (epi) growing silicon germanium (SiGe) to fill the recess; and removing the third and fourth capping layers over the first gate structure by wet etching, wherein the wet etching selectively removes the third and fourth capping layers but not the spacers disposed on the sidewalls of the second gate structure.