Patent ID: 7268393

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a gate insulating layer on the substrate; a gate on the gate insulating layer; first dual spacer patterns directly on opposite side walls of the gate, the first dual spacer patterns having a notch at a lower end adjacent the substrate, wherein the notch has a size less than the thickness of the first dual spacer patterns; second spacers on outer side walls of respective ones of the first dual spacer patterns; source/drain junction regions of a second conductivity type in the substrate on opposite sides of the gate and the second spacers; LDD regions of the second conductivity type in the substrate at opposite sides of the gate and the first dual spacer patterns, each of the LDD regions having an end adjacent a respective one of the junction regions; and pocket regions of the first conductivity type in the substrate at opposite sides of the gate, each of the pocket regions having an end adjacent a respective one of the LDD regions, and each of the pocket regions having more depth under the gate than in other regions.