Patent ID: 7102404

Claim:
An interpolator circuit comprising: a replica delay line to receive an input signal and to provide a first replica delay edge and a second replica delay edge based, at least in part, on the input signal; and an interpolated delay edge generator to receive the first replica delay edge and the second replica delay edge and to provide an interpolated delay edge selectively having a value between the first replica delay edge the second replica delay edge, wherein a capacitive loading of the first replica delay edge and the second replica delay edge is substantially constant for each selected value of the interpolated delay edge and further wherein the interpolated delay edge generator includes, a pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and having as an output the interpolated delay edge, the pass-gate voltage divider selectable between an on condition and an off condition, and a replica pass-gate voltage divider having as an input the first replica delay edge and the second replica delay edge and selectable between an on condition and an off condition, wherein the replica pass-gate voltage divider is in the on condition when the pass-gate voltage divider is in the off condition to provide a substantially constant capacitive loading on the first replica delay edge and the second replica delay edge.