Patent ID: 7087459

Claim:
A method for packaging a multi-chip module, comprising the steps of: connecting wafer bumps in a peripheral region of a first chip to lower parts of inner leads of first and second TAB tapes, each of the first and second TAB tapes having an inner lead and an outer lead; connecting wafer bumps in a peripheral region of a second chip to upper parts of the inner leads of the first and second TAB tapes connected to the first chip, thereby electrical signals being communicated therebetween; mounting the outer lead of the first TAB tape on a patterned circuit; connecting a third chip having thereon wafer bumps to an upper part of the second chip; connecting an outer lead of the second TAB tape to at least one of the wafer bumps in a peripheral region of the third chip; connecting an inner lead of a third TAB tape having the inner lead and an outer lead to at least one other wafer bump in the peripheral region of the third chip; connecting wafer bumps in a peripheral region of a fourth chip to the outer lead of the second TAB tape and the inner lead of the third TAB tape; and executing at least one encapsulation step, wherein an underfill material is filled in connecting portions between the first, second and third TAB tapes and the first, second, third and fourth chips.