Patent ID: 7268779

Claim:
An apparatus comprising: Z-buffering test logic located at a front portion of a rendering pipeline to perform a Z-test on a pixel and to determine whether the pixel passes or fails the Z-test; a render cache including a Z-buffer coupled to the Z-buffering test logic such that the Z-test for the pixel is performable and the Z-buffer is updateable at the front portion of the rendering pipeline, wherein if the pixel passes the Z-test, the Z-buffering test logic further determines if the pixel is promotable or unpromotable, and if the pixel is determined to be unpromotable, the Z-buffer is not updated and the unpromoted pixel is issued to the rest of pipeline; and a scoreboard memory coupled to the rest of the pipeline and the Z-buffering test logic at the front of the pipeline, the scoreboard memory including a pixel status array for every pixel in the pipeline to designate whether a pixel is promotable or unpromoteable, the scoreboard memory to identify and track unpromoted pixels that are issued to the rest of the pipeline; wherein pixel status from the rest of the pipeline is coupled through the scoreboard memory including the pixel status array to the Z-buffering test logic at the front portion of the rendering pipeline and the Z-buffering test logic accounts for bridging conditions including forcing pixels to remain unpromoted such that pipeline coherency is ensured.