Patent ID: 7504860

Claim:
A system comprising: a sense portion comprising a NAND logic gate that receives a first input logic signal associated with a lower voltage and an output logic signal associated with a higher voltage, wherein the sense portion outputs a sense logic signal responsive to the state of the NAND logic gate; an intermediary portion comprising: a node operative to output an intermediary signal; a first pull down device connected to the node, wherein the first pull down device receives a second input logic signal associated with the lower voltage complimentary with respect to the first input logic signal; a first pull up device that receives the sense logic signal, wherein the first pull up device is connected to a power supply at the higher operating voltage and the node; and a second pull up device that receives the output logic signal associated with a higher voltage, wherein the second pull up device is connected in parallel to the first pull up device to the power supply and the first node; an inverter portion having an input connected to the node, outputting the first output logic signal associated with the higher voltage responsive to a state of the intermediary signal.