Patent ID: 7778375

Claim:
A data recovery circuit, comprising: a voltage control oscillator for generating a sampling clock and a plurality of multi-phase clocks; a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to generate a selected clock according to a selection signal; a phase detector for receiving the sampling clock and an input signal and generating a phase error signal; and a digital low-pass filter for receiving and accumulating the phase error signal and generating the selection signal, wherein when the accumulated phase error signal is less than a first threshold phase difference equal to −K, the digital low-pass filter is configured to set the selection signal to a first phase adjustment amount equal to −N and clear the accumulated phase error signal; wherein when the accumulated phase error signal is greater than a second threshold phase difference equal to K, the digital low-pass filter is configured to set the selection signal to a second phase adjustment amount equal to N and clear the accumulated phase error signal; wherein when the accumulated phase error signal ranges between the first and second threshold phase differences (−K and K), the digital low-pass filter is configured to set the selection signal to zero and maintain the accumulated phase error signal; and wherein the phase detector clears and set all calculating intermediate data therein to default values in response to a reset signal.