Patent ID: 8324674

Claim:
A semiconductor memory device comprising: a first transistor formed on an upper surface of a substrate; a first stepped portion disposed adjacent to one side of a gate of the first transistor such that the first stepped portion forms a first cavity in the upper surface of the substrate; a second stepped portion disposed adjacent to another side of the gate of the first transistor such that the second stepped portion forms a second cavity in the upper surface of the substrate; a first contact plug formed in a region of the first stepped portion, the first contact plug being partially in contact with the first stepped portion; a second contact plug formed in a region of the second stepped portion, the second contact plug being partially in contact with the second stepped portion; a first insulating film formed between the first contact plug and the gate of the first transistor, the first insulating film being partially in contact with the first stepped portion; a second insulating film formed between the second contact plug and the gate of the first transistor, the second insulating film being partially in contact with the second stepped portion.