Patent ID: 7863740

Claim:
A semiconductor device having conductive bumps, comprising: a semiconductor substrate having a plurality of solder pads and a passivation layer formed thereon, wherein the passivation layer is formed with a plurality of first openings for exposing a desired part of each of the solder pads; a first covering layer applied over the solder pads and the passivation layer for exposing parts of each of the solder pads exposed by the first openings; a first metallic layer formed over the exposed part of each of the solder pads via the first openings and the first covering layer, and electrically connected to the solder pads; a second covering layer applied over the first metallic layer and the first covering layer, the second covering layer having a plurality of second openings formed to expose predetermined parts of the first metallic layer, wherein each of the second openings is free from corresponding in position to each of centers of the solder pads, respectively; a second metallic layer formed over the second covering layer and electrically connected to the first metallic layer; a third covering layer applied over the second metallic layer and the second covering layer, the third covering layer having a plurality of third openings for exposing parts of the second metallic layer, wherein each of centers of the third openings corresponds in position to each of the centers of the solder pads, respectively; a metallic standoff formed on each of the exposed parts of the second metallic layer exposed outside the openings of the third covering layer; and a solder material formed on an outer surface of the metallic standoff.