Patent ID: 7859879

Claim:
A memory module, comprising: a memory module board; and a plurality of memory devices on the memory module board, wherein: the memory module board includes: one or more first input terminals configured to receive first signals to individually control the memory devices; and one or more second input terminals configured to receive second signals to commonly control the memory devices, each of the memory devices includes: a plurality of first signal input units configured to receive the first signals through one or more first input pins; a plurality of second signal input units configured to receive the second signals through one or more third input pins; and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more second input pins and to compensate for a signal line load, the one or more first input terminals of the memory module board are commonly connected to the one or more first input pins of each of the memory devices as well as the one or more second input pins of each of the memory devices through a plurality of first signal lines, and the one or more second input terminals of the memory module board are connected to the one or more third input pins of each of the memory devices through a plurality of second signal lines.