Patent ID: 8726039

Claim:
A method for reducing decryption latency during encryption processing in a storage system using a pool of a plurality of encryption processing cores, comprising: assigning to each one of the plurality of encryption processing cores for the processing only one of encryption operations, decryption operations, and decryption and encryption operations that are scheduled for processing; setting a maximum number of the plurality of encryption processing cores for processing only the decryption operations, thereby lowering the decryption latency; assigning the decryption and encryption operations to each of the plurality of processing cores for processing if each of the plurality of encryption processing cores have attained the busy status; classifying the decryption and encryption operations as one of at least three types of operations represented as encryption only operations (E), the decryption only operations (D), and decryption and encryption operations (D/E); scheduling the encryption operations, the decryption operations, and the decryption and encryption operations, between the pool of the plurality of processing cores, according to a thread weight value (TWV) that is assigned to each one of the plurality of processing cores having a difference in processing power; and allocating a minimal number of the plurality of encryption processing cores for processing the encryption operations, thereby increasing encryption latency, wherein upon reaching a throughput limit for the encryption operations that causes the minimal number of the plurality of encryption processing cores to reach a busy status, the minimal number of the plurality of encryption processing cores for processing the encryption operations is increased.