Patent ID: 8644080

Claim:
A memory system comprising: a plurality of charge storage cells arranged into a plurality of blocks; and a memory controller comprising a timer; a read/write controller configured to receive a read request from a host, wherein the read request designates a location to be read within a first block of the plurality of blocks, in response to the read request, (i) make measurements on the location to be read, and (ii) respond to the host based on the measurements, receive a write request from the host, wherein the write request designates a location to be written within the first block, in response to the write request, selectively erase the first block, in response to erasing the first block, reset the timer, and in response to the write request, write data from the host to the location designated to be written by the write request; and a refresh control module configured to, in response to either (i) the timer exceeding a predetermined time, or (ii) the measurements from the location to be read being outside of a predetermined range, refresh the first block and reset the timer, wherein refreshing the first block comprises adjusting charge levels in the charge storage cells of the first block without erasing the first block.