Patent ID: 8095842

Claim:
A random error signal generator, comprising: a clock circuit which outputs clocks at predetermined cycles; a first reference value generation circuit which sequentially outputs first reference values, wherein the first reference values change by a predetermined value at every input of the clocks; a second reference value generation circuit which sequentially outputs second reference values in synchronization with the clocks, the second reference values being shifted from the first reference values by a range which is determined depending on a specified error rate; an M-sequence generation circuit comprising registers, which outputs a plurality of pieces of bit data stored in the respective registers in response to the clocks; and a comparison and determination unit which outputs random error signals including an error bit or error bits in parallel, wherein the random error signals are generated based on a comparison between the bit data output from the M-sequence generation circuit and the first and second reference values, wherein the comparison and determination unit takes in, as one numeric value, the plurality of pieces of bit data sequentially output from the M-sequence generation circuit in parallel, and takes in the first reference value and the second reference value, and outputs, in synchronization with the clocks, random error signals to be error bits if the numeric value taken from the M-sequence generation circuit exists between the first reference value and the second reference value.