Patent ID: 7928772

Claim:
A method comprising: (a) filtering an input signal using an RC filter to generate a first delayed and filtered version of the input signal; (b) changing the RC time constant of the RC filter using a processor; (c) supplying the input signal onto a first input lead of a first gate; (d) supplying the first delayed and filtered version of the input signal onto a second input lead of the first gate; (e) using a signal output by the first gate to set a latch; (f) RC filtering the input signal to generate a second delayed and filtered version of the input signal; (g) supplying the input signal onto a first input lead of a second gate; (h) supplying the second delayed and filtered version of the input signal onto a second input lead of the second gate; (i) using a signal output by the second gate to reset the latch; and (j) generating a duty cycle adjusted version of the input signal by supplying the input signal onto a first input lead of a third gate, and by supplying a signal output by the latch onto a second input lead of the third gate, wherein the third gate outputs the duty cycle adjusted version of the input signal onto an output lead of the third gate.