Patent ID: 7847329

Claim:
A memory, comprising: a plurality of memory elements; and a respective plurality of selection elements arranged in a plurality of rows parallel to a source line and a plurality of columns parallel to a bit line that is perpendicular to the source line, each selection element being formed by a vertical MOSFET transistor that includes: a body of semiconductor material having a surface; a buried conductive region of a first conductivity type positioned in the body; a channel region in the body, said channel region having a top and a bottom, said bottom completely on said buried conductive region; a surface conductive region of said first conductivity type, arranged on top of said channel region and said buried conductive region; a gate insulation region extending at sides of and contiguous to said channel region; and a gate region extending at sides of and contiguous to said gate insulation region; wherein said buried conductive region is shared by a plurality of said selection elements in a row of said plurality of rows parallel to the source line, and wherein said gate insulation region completely laterally surrounds said channel region, and said gate region completely laterally surrounds said gate insulation region.