Patent ID: 7606060

Claim:
A static random access memory comprising in combination: a plurality of bi-stable memory cells arranged in rows and columns; a pair of write bit lines common to each memory cell in a column; a single pre-charged read bit line common to each memory cell in a column; each cell including a pair of write data field effect transistors respectively connecting said each cell in column to said pair of write bit lines, a gate of each of said pair connected respectively to said pair of write bit lines for writing data into each cell; a single read data field effect transistor connecting said each cell to said read bit line, with its gate coupled to a node of said each cell in a column for reading data from said cell; a single field effect transistor connected to said pair of write data field effect transistors and said read data field effect transistor with its gate coupled to a single word line to control both read access and write access to said each cell.