Patent ID: 7518843

Claim:
An electrostatic discharge (ESD) protection circuit comprising: a silicon controlled rectifier (SCR) coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event; and at least one grounded-gate MOS transistor, having a source shared with the silicon controlled rectifier, coupled between the circuit pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event, wherein the silicon controlled rectifier includes a first parasitic diode formed between a P-type doped region and an N-well and a second parasitic diode formed between an N-type doped region and a P-type substrate, wherein both the P-type and N-type doped regions are formed within the N-well and the first and the second diodes are connected in an opposite direction, between the circuit pad and the shared source of the MOS transistor, for functioning as a bipolar transistor, wherein in a layout view, a first area for placement of the first and second parasitic diodes is interposed between at least two sets of grounded-gate MOS transistor areas having a plurality of transistors jointly functioning as the MOS transistor, disposed proximately at two sides of the first area to reduce a trigger voltage of the SCR.