Patent ID: 7962838

Claim:
A memory device having an error detection and correction system constructed on a Galois finite field, wherein the error detection and correction system comprises: an encode part configured to generate check bits to be written into the memory device together with information bits; a syndrome operation part configured to calculate syndromes from read data; a syndrome element calculation part configured to perform finite field calculations based on the syndromes and to calculate intermediate values necessary in the calculation for calculating error locations; an error searching part configured to perform data reception from the syndrome element calculation part and to perform finite field calculations to produce error locations; and a clock generator configured to generate internal clocks used for making operation circuits in the syndrome element calculation part and the error searching part activated in a time-sharing mode, the syndrome element calculation part and the error searching part using expression indexes to perform multiplication and addition between finite field elements, the expression indexes, in which differing prime factors of the domain of a finite field are “p” and “q”, representing indexes of the finite field elements by combinations of numbers in mod p and numbers in mod q.