Patent ID: 8358002

Claim:
A semiconductor package comprising: a substrate having (i) a first surface: (ii) a second surface that is opposite to the first surface, and (iii) an opening formed between the first surface of the substrate and the second surface of the substrate; a semiconductor die having (i) a first surface and (ii) a second surface that is opposite to the first surface, the first surface of the semiconductor die being electrically coupled to the second surface of the substrate by one or more interconnect bumps; one or more bonding wires that electrically couple the first surface of the semiconductor die to the first surface of the substrate through the opening of the substrate; a first electrically insulative structure disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and the one or more interconnect bumps, wherein the first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate; and a second electrically insulative structure that is coupled to the second surface of the substrate and the second surface of the semiconductor die to substantially encapsulate the semiconductor die, wherein the first electrically insulative structure comprises an underfill material, and wherein the second electrically insulative structure comprises a molding compound material that is not the same material as the underfill material.