Patent ID: 7754546

Claim:
A semiconductor device manufacturing method, comprising; forming, from a semiconductor substrate, a first projecting region having a first height and a second projecting region having a second height lower than said first height, said first projecting region being separated from said second projecting region by a space; forming a first insulating film on the upper and side faces of each of said first and second projecting regions; forming a conductive film on said first insulating film; forming a gate insulating film and a gate electrode on the upper face and the side faces of each of said first and second projecting regions by patterning said first insulating film and said conductive film, the gate electrode extending continuously, from one of the side faces of said first projecting region, to the upper face of said first projecting region, to the other side face of said first projecting region, across the space separating the first projecting region from said second projecting region, to one of the side faces of said second projecting region, to the upper face of said second projecting region, and to the other side face of said second projecting region, respectively; and forming a couple of diffusion regions in two regions straddling a region underneath said gate electrode of each of said first and second projecting regions.