Patent ID: 8154972

Claim:
A storage device, the storage device comprising: a storage medium; a read/write head assembly, wherein the read/write head assembly is operable to access information stored on the storage medium and to transfer the information to an analog processing circuit, and wherein the analog processing circuit includes: a summation circuit, wherein the summation circuit is operable to subtract a low frequency offset feedback from a derivative of the information to yield a processing output; an analog to digital converter, wherein the analog to digital converter is operable to convert a derivative of the processing output to a series of digital samples; a digital processing circuit, wherein the digital processing circuit includes: a data detector circuit, wherein the data detector circuit is operable to apply a data detection algorithm to a derivative of the series of digital samples and to provide an ideal output; an error feedback circuit, wherein the error feedback circuit includes a conditional subtraction circuit that is operable to conditionally subtract an interim low frequency offset correction signal from a delayed version of the derivative of the series of digital samples to yield an interim factor; an error calculation circuit, wherein the error calculation circuit is operable to generate an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output; and a digital to analog converter, wherein the digital to analog converter is operable to convert a derivative of the interim low frequency offset correction signal to yield the low frequency offset feedback.