Patent ID: 8503534

Claim:
A multi-bus video codec architecture comprising: a plurality of processing elements; a cache that stores data used by at least one processing element, within the plurality of processing elements, to process a macroblock being encoded within the video codec architecture; at least one luma bus, coupled to at least two processing elements within the plurality of processing elements, the at least one luma bus having a first width and transporting a plurality of luma objects between the at least two processing elements; at least one chroma bus, coupled to the at least two processing elements, the at least one chroma bus having a second width and transporting a plurality of chroma objects between the at least two processing elements, a first subset of the plurality of chrome objects and a second subset of the plurality of luma objects being communicated on two separate buses for at least one process among motion prediction, residual estimation and transformation, quantization, and entropy encoding; and at least one motion vector bus, coupled to the at least two processing elements, the at least one motion vector having a third width and transporting a plurality of motion vector information between the at least two processing elements.