Patent ID: 8773183

Claim:
A fractional PLL circuit comprising: a phase comparator that detects phase difference between an input clock signal that is a reference and a feedback signal, and outputs a controlled voltage in accordance with the phase difference; a voltage-controlled oscillator that generates and outputs an output clock signal that has a frequency based on the controlled voltage; a phase-selection circuit that selects any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generates a phase-shift clock signal that has a rising edge in the selected phase, and outputs the phase-shift clock signal as the feedback signal to the phase comparator; and a phase controller that determines a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controls the phase-selection circuit so as to select the determined phase.