Patent ID: 8194465

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array including an array of memory strings, each of the memory strings including a plurality of memory cells connected in series; a first wiring electrically connected to one end of each of the memory strings and charged to a first voltage at the time of a read operation; a second wiring electrically connected to the other end of each of the memory strings and set at a second voltage lower than the first voltage at the time of a read operation; and a control circuit configured to control data write and read operations to and from the memory cells, the control circuit being configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells, and, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.