Patent ID: 8013382

Claim:
A NAND flash memory comprising: an element region and a shallow trench isolation region are formed in a line-and-space pattern in a semiconductor substrate; a first selection gate transistor formed on the element region, the first selection gate transistor having one end connected to a bit line; a second selection gate transistor formed on the element region, the second selection gate transistor having one end connected to a source line; and a plurality of memory cells formed on the element region of the semiconductor substrate and connected to each other in series between the other end of the first selection gate transistor and the other end of the second selection gate transistor, wherein each of the memory cells includes: a columnar floating gate formed on the element region with a gate insulating film interposed between the floating gate and the element region; diffusion layers formed at portions of the element region located below both sides of the floating gate; and a control gate formed so as to surround the floating gate with an inter-poly dielectric (IPD) film interposed between the control gate and the floating gate, the IPD film formed on a side surface of the floating gate.