Patent ID: 7151028

Claim:
A method for fabricating a floating gate memory cell on a substrate, said method comprising steps of: forming a first spacer adjacent to a source sidewall of a stacked gate structure, said stacked gate structure including a floating gate, said stacked gate structure being situated over a channel region in said substrate; forming a high implant energy doped region adjacent to said first spacer in a source region of said substrate; forming a recess in said source region of said substrate, said recess having a sidewall and a bottom, said sidewall of said recess being situated adjacent to a source of said floating gate memory cell, said step of forming said recess comprising removing said first spacer; forming a second spacer comprising plasma-grown oxide adjacent to said source sidewall of said stacked gate structure, said second spacer extending to said bottom of said recess; wherein said second spacer reduces oxide growth between said substrate and said floating gate from an edge toward a center of said channel region.