Patent ID: 7925863

Claim:
An accelerator circuit card assembly configured to provide hardware acceleration for a software process running on a computing device, the computing device in communication with the accelerator circuit card assembly over an I/O bus, the assembly comprising: a first accelerator configured to perform only a decompression operation; a second accelerator configured to perform only a virus detection operation; a memory on the accelerator card assembly configured to provide data between a task management unit and the first accelerator and the second accelerator; the task management unit separate and independent from the computing device and each accelerator, the task management unit in communication with the first accelerator and the second accelerator so as to receive, over the I/O bus, a playlist indicating operations to be performed by the first and second accelerators from the computing device, wherein the task management unit i) processes the received playlist and initiates the decompression operation and the virus detection based, in part, on the received playlist, and ii) operates, including initiating the decompression operation and the virus detection operation, independently of the computing device, and wherein the first accelerator is configured to, after the first accelerator operation is completed, i) store output data of the first accelerator in the memory on the accelerator card assembly, and ii) send a synchronization message to the second accelerator to perform the second accelerator operation, wherein output data from the first accelerator operation is used as input data for the second accelerator operation.