Patent ID: 7373550

Claim:
A method of generating a computer program for execution by a data processing apparatus to test for correct operation of said data processing apparatus, said method comprising: (i) forming a candidate computer program with an associated expected execution outcome; (ii) simulating execution of said candidate computer program by said data processing apparatus with a fault simulator using a circuit model of said data processing apparatus including one or more faults introduced into said circuit model by said fault simulator; (iii) generating an execution outcome from said simulated execution with said fault simulator; (iv) scoring said candidate computer program in dependence upon whether said one or more faults introduced by said fault simulator produce a detectable change in said execution outcome compared to said expected execution outcome produced by simulated execution of said candidate without said one or more faults; (v) mutating said candidate computer program to form a mutated candidate computer program with an associated execution outcome; (vi) repeating steps (ii), (iii) and (iv) in respect of said mutated candidate computer program; (vii) replacing said candidate computer program with said mutated candidate computer program if a score for said mutated candidate computer program indicates it has a higher probability of producing a detectable change in execution outcome in response to said one or more faults than said candidate computer program; and (viii) testing if one or more mutation termination conditions have been met and if said one or more mutation termination conditions have not been met then repeating steps (v), (vi), (vii) and (viii).