Patent ID: 7519496

Claim:
An electronic circuit including a sub-module assembly connected to the rest of the circuit, said sub-module assembly including: a sub-module for performing a given function, and comprising at least one scan chain, wherein said sub-module includes input pins, said input pins being isolated from the rest of the circuit by isolating cells accessible both by regular scan testing of the rest of the circuit and by self-testing of the sub-module, a built-in self test circuit including a pattern generator for applying, in test-mode, input signals to said scan chain, and a signature register for checking output signals from the scan chain, said output signals being generated by the sub-module from the input signals, wherein said scan chain, during operation thereof, is disconnected from the rest of the circuit, wherein said built-in self-test circuit is a deterministic logic built-in self-test circuit, said pattern generator being configured to generate pseudo-random test patterns, said pattern generator including a bit modifying circuit configured to convert said pseudo-random test patterns into deterministic test samples, wherein said bit modifying circuit includes a bit-flipping function circuit configured to perform an iterative algorithm that enhances said bit-flipping function circuit with each iteration such that new deterministic samples are produced while some old samples, sufficient for detecting the already-detected faults, remain unchanged.