Patent ID: 7825692

Claim:
A semiconductor memory device comprising: an I/O drive circuit; and a current supply circuit configured to supply current generated by an external voltage to the I/O drive circuit responsive to a first pattern of data input to the I/O drive circuit, and to prevent the current generated by the external voltage from being supplied to the I/O drive circuit responsive to a second pattern of data input to the I/O drive circuit, wherein the first pattern of data includes a change from a low level to a high level, and wherein the I/O drive circuit comprises a pulse generation circuit configured to generate a pulse for a predefined time when the data input to the I/O drive circuit is the first pattern of data, the pulse generation circuit comprising: a short pulse generation circuit configured to generate a short pulse, a width of the short pulse substantially corresponding to a delay time of a logic gate, the short pulse being generated responsive to a change of the data input to the I/O drive circuit from one of the low level to the high level; and a level shift circuit configured to increase a voltage level of the short pulse.