Patent ID: 8729601

Claim:
A semiconductor device comprising: a first semiconductor layer of a first conductivity type comprising a plurality of trenches formed therein, the plurality of trenches extending from a top surface to a bottom surface of the first semiconductor layer and forming mesas in the first semiconductor layer; first semiconductor regions of a second conductivity type formed on the bottom surface of the mesas of the first semiconductor layer; a first epitaxial layer of the second conductivity type formed on sidewalls of the trenches and covering at least sidewalls of the mesas of the first semiconductor layer, the first epitaxial layer being electrically connected to the first semiconductor regions formed at the bottom surface of the mesas; a first dielectric layer formed in the trenches adjacent the first epitaxial layer, the first dielectric layer filling at least part of the trenches; a gate dielectric layer formed on the sidewalls of at least a first trench above the first dielectric layer; and a gate conductive layer formed in the first trench above the first dielectric layer and adjacent the gate dielectric layer, wherein the first epitaxial layer forms parallel doped regions along the sidewalls of the trenches, the first epitaxial layer having uniform doping concentration, the first epitaxial layer having a first thickness and a first doping concentration and a mesa of the first semiconductor layer having a second thickness and a second doping concentration, the first and second thicknesses and the first doping concentration and second doping concentrations being selected to achieve charge balance in operation.