Patent ID: 8050082

Claim:
An integrated circuit device comprising: a first word-line; a second word-line; a first bit-line; a static random access memory (SRAM) cell comprising: a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor comprising a gate coupled to the second word-line, wherein each of the first and the second pass-gate transistors comprises a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node; a word-line voltage generating circuit configured to: receive first word-line signals applied on the first word-line, wherein the first word-line signals comprise rising edges and falling edges; generate second word-line signals by delaying the first word-line signals for a delay time; and output the second word-line signals to the second word-line.