Patent ID: 8819378

Claim:
A data processing apparatus comprising: processing circuitry configured to execute a sequence of instructions including a memory access instruction, the processing circuitry including memory control circuitry configured to execute said memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address; a first interface and a second interface; the memory control circuitry being configured to route each address transfer and associated data transfer via the first interface when the specified memory address is within a first memory address range, and to route each address transfer and associated data transfer via the second interface when the specified memory address is within a second memory address range; the memory control circuitry further being configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing; and the memory control circuitry further being configured, when using the second interface, to modify execution of the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the second interface with a second relative timing different to said first relative timing, wherein the memory control circuit comprises buffer circuitry selectively employed during modified execution of the memory access instruction to achieve the second relative timing of each address transfer and associated data transfer as presented at the second interface, wherein: the memory control circuitry includes an address generator configured to generate the memory address for each address transfer; and the memory control circuitry is configured for at least one type of memory transaction, when using the second interface, to buffer each memory address generated by the address generator within the buffer circuitry for at least one clock cycle, such that each address transfer and associated data transfer is presented at the second interface during the same clock cycle, wherein the memory control circuitry is configured not to buffer the memory address generated by the address generator if the memory transaction is a single-beat memory transaction comprising a single address transfer and an associated single data transfer.