Patent ID: 7616628

Claim:
A processing system comprising: a register file having an input and an output; a routing unit having an input and an output, the input of the data routing unit coupled to the output of the register file, the routing unit receiving a data signal and selectively aligning and transferring the data signal; a switch control unit having an input coupled to receive a control signal and an output coupled to provide a switch control signal, the switch control unit generating the switch control signal that specifies a routing operation or bitfield manipulation operation; a switch having a first input, a second input and an output, the first input of the switch coupled to the output of the routing unit to receive the data signal, the second input of the switch coupled to the output of the switch control unit to receive the switching control signal, the switch controlling information pathways and perform routing functions on the data signal; and an arithmetic logic unit having an input and an output, the input of the arithmetic logic unit coupled to the output of the switch and the output of the arithmetic logic unit coupled to the input of the register file.