Patent ID: 6979594

Claim:
A process for manufacturing an integrated circuit package comprising: mounting a semiconductor die to a first surface of a substrate; wire bonding said semiconductor die to ones of conductive traces at said first surface of said substrate; disposing one of a heat spreader and said substrate on a surface of a lower mold die; releasably clamping edge portions of the other of said heat spreader and said substrate by pinching said edge portions between an upper mold die and said lower mold die at a periphery of a mold cavity between said upper mold die and said lower mold die, such that said other of said heat spreader and said substrate is in contact with said upper mold die; molding the semiconductor die, the substrate, the wire bonds and said heat spreader into a mold material by molding in said mold cavity, resulting in a molded package having at least a portion of said substrate exposed and at least a portion of said heat spreader exposed from said molded package prior to singulating; forming a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces; and singulating said integrated circuit package.