Patent ID: 8541281

Claim:
A method, comprising: forming sacrificial gate structures for both a PFET transistor and an NFET transistor above a semiconducting substrate, said sacrificial gate structures for said PFET transistor and said NFET transistor being formed above a P-active region and an N-active region, respectively, of said substrate; removing said sacrificial gate structures and forming a replacement P-type gate structure for said PFET transistor and a replacement N-type gate structure for said NFET transistor; after forming said replacement P-type and N-type gate structures, forming a plurality of P-contact openings and a plurality of N-contact openings in at least one layer of insulating material, wherein said P-contact openings expose portions of said P-active region and said N-contact openings expose portions of said N-active region; forming a masking layer that covers said exposed portions of said N-active region; with said masking layer in place, performing at least one etching process though said P-contact openings in said at least one layer of insulating material to define a plurality of source/drain cavities in said P-active region proximate said P-type replacement gate structure of said PFET transistor; and performing at least one epitaxial deposition process through said P-contact openings to form source/drain regions comprised of a semiconducting material in at least said source/drain cavities of said PFET transistor.