Patent ID: 7171521

Claim:
A shared memory system comprises: a plurality of processing nodes, wherein each of the plurality of processing nodes includes a processing resource, cachc memory, and memory; and a packetized input/output (I/ 0 ) link operably coupling the plurality of processing nodes together, wherein one of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link; maintain intranode cache coherency at a symmetric multiprocessor (SMP) level; and maintain intranode cache coherency among the plurality of processing nodes at a non-uniform memory access (NUMA) level.