Patent ID: 7313011

Claim:
A ferroelectric memory device comprising: a ferroelectric memory cell coupled to a word line, a plate line, and a bit line; a plate line driver for driving the plate line; a row decoder for driving the word line in response to a row address; a sense amplifier for sensing and amplifying a voltage on the bit line; a column select circuit for selectively connecting the bit line with a data line in response to a column address; a data input circuit for transferring data from the outside to the data line; and a control logic for controlling operational timing of the plate line driver, the column select circuit, the sense amplifier circuit, and the data input circuit, wherein the control logic generates first to fourth control signals, the plate line driver enabled by the first control signal, the sense amplifier circuit enabled by the second and third control signals, and the column select circuit enabled by the fourth control signal; and wherein the fourth control signal is activated before the activation of the first control signal in a write operation.