Patent ID: 8618548

Claim:
A thin film transistor (TFT) array panel, comprising: a gate line and a data line insulated from each other on an insulating substrate; at least two pixel electrodes; at least one thin film transistor (TFT) including a gate electrode, a source electrode and a drain electrode respectively, wherein the gate electrode is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to one of the pixel electrodes; and a capacitive electrode, at least a portion of the capacitive electrode overlapping and oriented substantially parallel with the data line, wherein the capacitive electrode overlaps the pixel electrodes, and the capacitive electrode is without an opening or a slit facing the data line; a storage line which is at least approximately parallel with the gate line; and a drain extension portion extending from the drain electrode, wherein the storage line overlaps the drain extension portion wherein one of the pixel electrodes is disposed adjacent to a first side of the data line and another one of the pixel electrodes is disposed adjacent to a second side of the data line that is opposite to the first side.