Patent ID: 7482841

Claim:
A bang-bang phase detection (BBPD) circuit for use in high data-rate applications, the circuit producing two BBPD output signals each including alternating samples of a BBPD input signal, the circuit comprising: a first stage of timing circuitry comprising first, second, third, and fourth flip-flops, each flip-flop having an input and an output, each flip-flop receiving at its input the BBPD input signal, and each flip-flop being clocked by a different one of four phases of a common clock signal; and a second stage of timing circuitry comprising first, second, third, fourth, fifth, and sixth flip-flops, each flip-flop having an input coupled to an output of a flip-flop of the first stage of timing circuitry and a differential output, the first and third flip-flops of the second stage producing at their respective outputs first and second BBPD output signals, wherein the first and second BBPD output signals include alternating samples of the BBPD input signal, and wherein the fourth, fifth, and sixth flip-flops of the second stage are clocked by a second clock signal, and wherein the first, second, and third flip-flops of the second stage are clocked by a version of the second clock signal that is delayed by a half period with respect to the second clock signal.