Patent ID: 8361832

Claim:
A method of forming a memory cell, comprising: providing a substrate; providing an electrically conductive region supported by said substrate; forming a first dielectric layer over said substrate and said electrically conductive region; forming a hard mask layer over said first dielectric layer; removing a portion of said first dielectric layer and said hard mask layer to form a mesa structure of said first dielectric layer over said electrically conductive region, wherein said hard mask layer remains over said mesa structure and said mesa structure has at least one sidewall; forming a conductive layer over said sidewall of said mesa structure and at least a portion of said electrically conductive region; forming a second dielectric layer over said mesa structure, said conductive layer, and said electrically conductive region; planarizing said second dielectric layer to expose said conductive layer and remove said hard mask layer, using said mesa structure as a stop; and forming a memory element layer over said conductive layer and said mesa structure.