Patent ID: 8405427

Claim:
A circuit configured to process a differential input signal, comprising: a first floating capacitor ladder configured to receive a positive of the differential input signal, the first floating capacitor ladder being connected to a first switched capacitor network through phase one controlled switches; a second floating capacitor ladder configured to receive a negative of the differential input signal, the second floating capacitor ladder being connected to a second switched capacitor network through other phase one controlled switches; and a reference resistor ladder connected to the first switched capacitor network through phase two controlled switches to provide voltage references, the reference resistor ladder being connected to the second switched capacitor network through other phase two controlled switches to provide the voltage references; wherein in response to controlling the phase one controlled switches, the other phase one controlled switches, the phase two controlled switches, and the other phase two controlled switches, the first floating capacitor ladder is configured to output first voltage thresholds to a comparator array and the second floating capacitor ladder is configured to output second voltage thresholds to the comparator array.