Patent ID: 8704332

Claim:
A semiconductor device comprising: a semiconductor substrate including an active semiconductor region that is defined by an oxide containing isolation region; a gate structure having a length from a first end face to a second end face extending across the active semiconductor region of the semiconductor substrate, wherein the gate structure includes a high-k gate dielectric layer that is present on the active semiconductor region, the high-k gate dielectric layer includes an overhang portion that extends over the oxide containing isolation region; a source region and a drain region in the active semiconductor region on opposing sides of the gate structure, wherein a channel length perpendicular to the length of the gate structure is defined between the source region and the drain region; and an encapsulating dielectric material present on at least one of the first end face and the second end face of the gate structure, wherein the encapsulating dielectric material extends beneath an uppermost surface of the semiconductor substrate, into the oxide containing isolation region, and is in direct contact with a bottommost surface of the overhang portion of the high-k gate dielectric layer.