Patent ID: 8093647

Claim:
A nonvolatile semiconductor memory comprising: a memory cell having a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film; and an FET having a lower gate electrode, a second inter-gate insulating film with a first film thickness having an opening exposing a top surface of the lower gate electrode and arranged on the lower gate electrode, a block film with a second film thickness different from the first film thickness formed on at least the opening exposing the top surface of the lower gate electrode, and an upper gate electrode contacting to the block film, wherein the control gate electrode and the upper gate electrode have a full-silicide structure in which an entirety of them is silicided, while the lower gate electrode is not silicided, and the block film has a concave portion with a concave shape, the upper gate electrode is embedded in the concave portion and the uppermost portion of the block film is higher than an upper surface of the second inter-gate insulating film.