Patent ID: 8797783

Claim:
A system on chip (SoC) comprising a plurality of non-volatile bit cells, wherein each bit cell comprises: two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors, wherein the first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed; a first clamping circuit coupled to the node Q, wherein the first clamping circuit is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed; further comprising a transmission gate coupled between the node Q and the bitline, the transmission gate configured to isolate node Q from the bitline in response to a control signal, wherein the transmission gate comprises an NMOS device connected in parallel with a PMOS device.