Patent ID: 8704279

Claim:
A device comprising: a substrate; a buried well region of a first conductivity type over the substrate; a first High Voltage Well (HVW) region of the first conductivity type over the buried well region; an insulation region over the first HVW region; a drain region of the first conductivity type on a first side of the insulation region and in a top surface region of the first HVW region; a gate electrode comprising a first portion on a second side of the insulation region, and a second portion extending over the insulation region; a first well region and a second well region of a second conductivity type opposite the first conductivity type and on the second side of the insulation region; a second HVW region of the first conductivity type between the first and the second well regions, wherein the second HVW region is connected to the buried well region; and a source region of the first conductivity type and in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a Junction Field-Effect Transistor (JFET).