Patent ID: 6970016

Claim:
A data processing circuit comprising: a single rail bus having a single rail line for a sequence of data bits; a dual rail bus having two dual rail lines for the sequence of data bits, a first dual rail line being provided for the data bits and a second dual rail line being provided for inverted data bits; and a converter for converting signals on the single rail bus into signals on the dual rail bus and vice versa, the converter comprising: a read driver for transferring signals on the first dual rail line to the single rail bus and for ignoring signals on the second dual rail line when the read driver is active; a write driver for transferring the signals on the single rail bus to the first dual rail line when the write driver is active; a producer for producing the signals on the second dual rail line from the signals on the first dual rail line when the write driver is active; and a controller for controlling the read driver and the write driver via a read control signal and a write control signal so that at most either the read driver or the write driver is active.