Patent ID: 7489151

Claim:
A layout for devices under test formed on a semiconductor wafer for use in wafer testing, the layout comprising: a first array of devices under test, wherein a device under test in the first array is formed within a cell, wherein the device under test includes a drain, source, gate, and well, and further comprising: a first L-shaped routing structure disposed at a first corner of the cell, wherein the first L-shaped routing structure is connected to the drain; a second L-shaped routing structure disposed at a second corner of the cell, wherein the second L-shaped routing structure is connected to the source; a third L-shaped routing structure disposed at a third corner of the cell, wherein the third L-shaped routing structure is connected to the gate; and a fourth L-shaped routing structure disposed at a fourth corner of the cell, wherein the fourth L-shaped routing structure is connected to the well; a first pad set formed adjacent to the first array, the first pad set including a gate force pad, a source pad, and a drain pad, wherein each of the devices under test in the first array is connected in parallel to the source pad of the first pad set, and wherein each of the devices under test in the first array is connected in parallel to the drain pad of the first pad set; and a selection circuit connected to each of the devices under test in the first array and the gate force pad, wherein the selection circuit is configured to selectively connect each of the devices under test in the first array to the gate force pad.