Patent ID: 7155570

Claim:
A trace buffer circuit comprising: a plurality of interconnected registers, including a first end register to input and output addresses of fetched instructions during a trace operation, a second end register, and a plurality of middle registers connected between said first end register and said second end register; a write path to shift an instruction address in one of said plurality of interconnected registers by two registers toward the second end register on a write operation; a first holding register; a second holding register; a first comparator to compare a new branch target address corresponding to a loop in the first holding register to a stored branch target address in the first end register; a second comparator to compare a new branch source address corresponding to the loop in the second holding register to a stored branch source address in a first adjacent register, said first adjacent register being connected to the first end register on a read path; and a compression indication circuit to generate a compression indicator in response to the new branch target address matching the stored branch target address and the new branch source address matching the stored branch source address.