Patent ID: 7860172

Claim:
A final stage of a multi-stage stage decoder coupled to a memory array, said final stage comprising: a first stage, a second stage and the final stage each being configured as part of said multi-stage stage decoder; a local clock buffer comprising a gate configured to receive an enable signal from the first stage and a clock signal; an enable input from a communication channel connecting a most significant bit output of the first stage to a gate of the local clock buffer to communicate the enable signal from the first stage to the local clock buffer; a word line driver configured to receive at least one data input from the second stage and further configured to receive at least two output signals from said gate of the local clock buffer, said two output signals comprising a first enable output of the gate and a second inverted enable output of the gate; and a latch configured as part of said word line driver and arranged to be enabled by said second inverted enable output of the gate to communicate a word line signal to a memory array.