Patent ID: 7849256

Claim:
An integrated circuit device comprising: a central memory controller circuit coupled to at least one read bus switch and each of the one or more memory clients, and configured to route the memory request to the target memory device, wherein the memory controller circuit comprises, a switch matrix configured to transmit the memory requests from the requesting memory client to the target memory device; an arbiter circuit coupling each memory client of the one or more memory clients to a respective memory channel; a sequencer circuit coupling each arbiter to a respective read bus switch corresponding to the requesting memory client; and a client interface coupling the arbiter circuit to the requesting memory client and configured to implement a flow control protocol for the requesting memory client; a plurality of memory clients operable to send or receive data to one or more memory devices by sending memory access requests to the central memory controller circuit; and a ring bus connected between pairs of read bus switches of a plurality of read bus switches, and configured to transmit a memory read transfer between the target memory device and a requesting memory client, wherein the ring bus comprises a counter rotating ring bus coupling all of the plurality of read bus switches together in a ring topography.