Patent ID: 8359563

Claim:
A method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform, the method comprising: using a processor to perform steps comprising: computing one or more moments of the timing waveform; and defining the characterization waveform according to a functional relationship between the one or more moments and one or more parameters of the characterization waveform including a fifty-percent crossing time and a slew, wherein the fifty-percent crossing time and the slew are calculated in accordance with the one or more moments and one or more coefficients, wherein each of the one or more coefficients is associated with one of the one or more moments, and wherein the one or more coefficients are selected by: simulating the gate driven by one or more combinations of actual timing waveform and output load to generate one or more sample output waveforms; simulating the gate driven by the characterization waveform to form a characterization output waveform; measuring an L1 norm error between each of the one of more sample output waveforms and the characterization output waveform, such that at least one L1 norm error is generated; and selecting the one or more coefficients such that a largest one of the at least one L1 norm error is improved.