Patent ID: 7280416

Claim:
A nonvolatile memory system comprising: a nonvolatile memory storing programmed data; a memory bus connected to the nonvolatile memory and transferring read data corresponding to the programmed data from the nonvolatile memory; a first signal line providing a reset signal for resetting the nonvolatile memory system from outside the nonvolatile memory system; a second signal line providing an emergency stop signal for stopping an operation of the nonvolatile memory system from outside the nonvolatile memory system; an information processing bus for transferring the read data to outside the nonvolatile memory system; and a controller connected to the first signal line and to the second signal line and operating to stop an operation of transferring the read data to the information processing bus from the memory bus in response to the emergency stop signal, wherein the nonvolatile memory system is capable of transferring the read data to outside the nonvolatile memory system after completing a reset operation in response to the reset signal, and is capable of stopping the transferring operation in response to the emergency stop signal and of maintaining the stopping of the transferring operation until after a completion of the reset operation in response to an occurrence of the reset signal subsequent to the stopping of the transferring operation.