Patent ID: 8410820

Claim:
A latch circuit, comprising: a bistable latch that includes: a first bistable latch transistor and a second bistable latch transistor; a first port to receive a first input current signal and produce a first output voltage signal; and a second port to receive a second input current signal and produce a second output voltage signal; and a second latch separate from the bistable latch and connected to the first port of the bistable latch to provide a feedback signal to the first port based on the first output voltage signal, the second latch including: a first latch transistor having a source terminal configured to directly connect to a power supply voltage; and a second latch transistor having a source terminal directly connected to a ground potential, wherein the first port reaches a steady state value based on the first and second input current signals and the feedback signal, wherein a source of the first bistable latch transistor is directly connected to the ground potential, and wherein a source of the second bistable latch transistor is directly connected to the ground potential.