Patent ID: 7968886

Claim:
A SOI integrated circuit comprising: a first insulating film formed over a semiconductor substrate; an n-channel transistor formed over the first insulating film, the n-channel transistor comprising: a first semiconductor film including a first channel formation region, first source and drain regions, and lightly doped regions between the first channel formation region and the first source and drain regions formed over the first insulating film; a first gate insulating film formed over the first semiconductor film; a first gate electrode formed over the first gate insulating film; first side walls formed adjacent to side surfaces of the first gate electrode; and a second insulating film interposed between the first side walls and the side surfaces of the first gate electrode, and extending below the first side walls; and a p-channel transistor formed over the first insulating film, the p-channel transistor comprising: a second semiconductor film including a second channel formation region, and second source and drain regions formed over the first insulating film; a second gate insulating film formed over the second semiconductor film; a second gate electrode formed over the second gate insulating film; and second side walls formed adjacent to side surfaces of the second gate electrode; and a third insulating film interposed between the second side walls and the side surfaces of the second gate electrode, and extending below the second side walls, wherein the lightly doped regions of the n-channel transistor overlaps with the first side walls of the n-channel transistor, and wherein the first side walls do not overlap a top surface of the first gate electrode.