Patent ID: 8549375

Claim:
A decoder for a low-density parity check (LDPC) code constructed based on a Reed-Solomon (RS) code, comprising: a permutation circuit for providing configurable connections defined by a sub-matrix B(i 0 , j 0 ) in a parity check matrix, the parity check matrix being related to a Galois field GF(p s ), wherein p is a prime, s is a positive integer, i 0 and j 0 are integer indices ranging from 0 to (p s −1), a set of input comprising p s elements, the permutation circuit comprising: a first permutator for fixing the first element in the set of input and cyclically shifting the other (p s −1) elements in the set of input by j 0 positions, so as to generate a first set of temporary elements; a fixed routing, for rearranging the first set of temporary elements, so as to generate a second set of temporary elements; and a second permutator for fixing the first element in the second set of temporary elements and cyclically shifting the remaining (p s −1) elements of the second set of temporary elements by i 0 positions.