Patent ID: 6909644

Claim:
A semiconductor memory device comprising: a pair of bit lines; another bit line arranged parallel to and between the pair of bit lines; a pair of memory cells selected simultaneously, wherein one of the memory cells is coupled to one of the pair of bit lines and stores data, and the other of the memory cells is coupled to the other of the pair of bit lines and stores inverted data; a word line coupled in common to the pair of memory cells; a sense amplifier configured to amplify data on the pair of bit lines from the pair of memory cells in a read operation and to amplify data on the pair of bit lines to store the data in the pair of memory cells in a write operation; a column gate configured to couple the bit lines to a data bus; and a control circuit configured to turn ON the column gate before the sense amplifier is activated in the write operation, wherein no data is transferred on the another bit line when the sense amplifier is activated.