Patent ID: 7193265

Claim:
A single-poly EEPROM, comprising: a first PMOS transistor serially connected to, a second PMOS transistor, wherein the first and second PMOS transistors are both formed on an N-well of a P type substrate, and wherein the first PMOS transistor includes a floating gate, a first P + doped drain region, and a first P + doped source region, the second PMOS transistor includes a gate and a second P + doped source region, and the first P + doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor; and a diode located in the P type substrate, wherein the diode includes a P-well and an N + doped region disposed in the P-well, and wherein the floating gate of the first PMOS transistor overlaps with the N-well and the P type substrate and extends to the P-well and N + doped region, and a junction region of the P-well and the N + doped region overlapped beneath the floating gate serves as an avalanche injection point in a vicinity of the first PMOS transistor.