Patent ID: 7901984

Claim:
A wafer level method for packaging integrated circuits, the method comprising: sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, the epoxy layers including a first epoxy layer and a second epoxy layer, wherein the epoxy layers are deposited by spin coating, there being a topmost epoxy layer; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited; forming openings in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited; placing an integrated circuit within an associated one of the openings, wherein the integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the integrated circuit to thereby cover the integrated circuit; forming at least one conductive interconnect layer, wherein each interconnect layer is formed over an associated epoxy layer; forming a first passive component within at least one of the multiplicity of epoxy layers, wherein the first passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers, wherein the formation of the first passive component comprises: sputtering a ferromagnetic material on one of the sequentially deposited epoxy layers to form a magnetic core; depositing one of the sequentially deposited epoxy layers on the magnetic core; and sputtering a conductive material on the epoxy layer deposited over the magnetic core to form an inductor winding configured to be magnetically coupled with the magnetic core, wherein the first passive component is an inductor that includes the magnetic core and the inductor winding and wherein the first passive component is embedded at least in the first epoxy layer; forming a second passive component, wherein the second passive component does not directly overlie the first passive component and is positioned within an epoxy layer selected from a group consisting of the first epoxy layer and the second epoxy layer, the second epoxy layer being distinct from the first epoxy layer, wherein the second passive component is electrically coupled to at least one of the interconnect layers; and forming a multiplicity of external package contacts, wherein the integrated circuit is electrically connected to a plurality of the external package contacts at least in part through at least one of the conductive interconnect layers.