Patent ID: 8250437

Claim:
A memory system comprising: a storage apparatus including a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on 2 N (N is a natural number not smaller than 2) threshold voltage distributions; a storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that absolute values of two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are different from absolute values of the respective LLRs in the first LLR table; and a decoder configured to, when performing decoding processing through probability-based repeated calculations using an LLR calculated from the first or second LLR table and the threshold voltage, perform the decoding processing using the LLR calculated from the second LLR table and the threshold voltage if the decoding processing using the LLR calculated from the first LLR table and the threshold voltage results in an error.