Patent ID: 8345460

Claim:
A semiconductor memory device comprising: a memory cell array having memory cells, a plurality of first wirings and a plurality of second wirings; a wiring pullout portion prepared for pulling out the first wirings and the second wirings; a contact arrangement portion formed to arrange a plurality of contacts on a plane, the contacts being connected to the first wirings or the second wirings; and a probe that can move along the plane to electrically contact with either of the contacts, a plurality of the memory cell arrays being laminated on a semiconductor substrate, the wiring pullout portion being configured to pull out odd-numbered ones of the first wirings or the second wirings from a first side of the memory cell array, and pull out even-numbered ones of the first wirings or the second wirings from a second side of the memory cell array, the second side being the opposite of the first side, and the contact arrangement portion comprising a first contact arrangement portion provided at the first side and formed to arrange a plurality of contacts electrically connected to odd-numbered ones of the first wirings or the second wirings on a plane, and a second contact arrangement portion provided at the second side and formed to arrange a plurality of contacts electrically connected to even-numbered ones of the first wirings or the second wirings on a plane.