Patent ID: 7180776

Claim:
A computer readable storage medium storing an instruction for a complex programmable logic device (CPLD), the CPLD comprising a first electrically-erasable programmable read-only memory (EEPROM) array, a static random access memory (SRAM) array, a control circuit configured to load data from the first EEPROM array into the SRAM array and including a security circuit for protecting the data stored in the EEPROM array and the SRAM array, and a plurality of macrocells connected by a programmable interconnect matrix, the medium comprising: code for storing a first set of configuration data in the SRAM array to configure the plurality of macrocells and the programmable interconnect matrix to place the CPLD in a first configuration, the first set of configuration data comprising a security code used by the security circuit to prevent writing to the EEPROM array except under a set of limited circumstances; and code for programming the EEPROM array with a second set of configuration data while operating an electronic system with the CPLD in the first configuration.