Patent ID: 8081537

Claim:
A circuit configured to be part of a memory module configured to be operationally coupled to a computer system, the memory module comprising a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another for receiving and transmitting data having a bit width of the rank in response at least in part to a first number of DDR chip-select signals, the circuit including at least one configuration in which the circuit is configured to: receive a set of signals comprising address signals and a second number of DDR chip-select signals smaller than the first number of DDR chip-select signals; generate and transmit phase-locked clock signals to the DDR memory circuits of the first number of ranks; and generate the first number of DDR chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of DDR chip-select signals.