Patent ID: 7471131

Claim:
A delay locked loop (DLL) for delaying an input clock to lock a delay clock comprising: a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock; a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value; a phase detector coupled to a final delay component of the delay components for detecting a phase transition between a final delay clock of the delay clocks and the input clock; and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock to control a delay quantity of each of the plurality of the delay components; wherein the final delay clock from the final delay component lags 180 degrees behind the input clock after locking, and wherein the delay component comprises: a decoder for decoding the count value to generate a decoded signal; a plurality of code detectors for respectively detecting the count value to generate a plurality of detected signals; a plurality of delay chains respectively coupled to the decoder and the plurality of code detectors for delaying the input clock according to the plurality of detected signals and the decoded signal to generate a plurality of temporary delay clocks corresponding to different delay quantities; a second MUX coupled to the decoder and the plurality of delay chains for choosing one from the plurality of temporary delay clocks according to the decoded signal as the delay clock corresponding to the frequency of the input clock; and an output buffer coupled to the second MUX for outputting the delay clock.