Patent ID: 8688761

Claim:
An apparatus comprising: means for performing arithmetic and logic operations; means for caching data; means for programmably shifting data; a first data path comprising the means for performing arithmetic and logic operations, the means for caching data, a multiplexer, and the means for programmably shifting data; and a second data path comprising the means for performing arithmetic and logic operations, the multiplexer, and the means for programmably shifting data, wherein in an address generation mode, data flows from the means for performing arithmetic and logic operations through the means for caching data, the multiplexer, and the means for programmably shifting data to a register file via the first data path, wherein in an arithmetic mode, data flows from the means for performing arithmetic and logic operations through the multiplexer and the means for programmably shifting data to the register file via the second data path in response to a common control signal provided from an instruction cache to the means for performing arithmetic and logic operations, the multiplexer, and the means for programmably shifting data, wherein the multiplexer has a first multiplexer input to receive an arithmetic output from the means for performing arithmetic and logic operations, a second multiplexer input to receive data from the means for caching data, and a control multiplexer input to receive the common control signal, and wherein the arithmetic output received in the arithmetic mode includes data resulting from an arithmetic operation performed by the means for performing arithmetic and logic operations and bits that indicate an amount the resulting arithmetic operation data is to be shifted by the means for programmably shifting data.