Patent ID: 7079424

Claim:
A method for erasing a memory cell having a control gate and a floating gate formed over a substrate, a source region and a drain region, comprising: pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level; erasing the memory cell by applying a voltage to the memory cell to lower the threshold voltage of the memory cell to a second predetermined level; performing erase verification on the memory cell to determine whether the threshold voltage of the memory cell has been lowered to the second predetermined level; and applying a second erase voltage to the memory cell to lower the threshold voltage of the memory cell to the second predetermined level if it is determined during erase verification that the threshold voltage of the memory cell has not been lowered to the second predetermined level.