Patent ID: 8178903

Claim:
A semiconductor device comprising: an even number of transistor pairs, each transistor pair being a transistor pair in which an n-type transistor and a p-type transistor are connected in series between a power supply terminal and a ground terminal, the even number being a four or more; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the n-type transistor of one of the transistor pairs disposed in the preceding stage of one of the transistor pairs for which each connection node is provided and a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the even number of transistor pairs constitute a state storage circuit in such a manner that the transistor pairs are connected in the form of a loop, and any one of the transistor pairs is referred to as a first transistor pair, the n-type transistor of the first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed.