Patent ID: 7745335

Claim:
A method of fabricating an integrated circuit, including the fabrication of an interconnect using a damascene process, the method comprising: forming a pre-metal dielectric layer over a semiconductor device formed on a substrate; forming a contact for electrical connection to the device through the pre-metal dielectric layer; forming an inter-layer dielectric layer over the pre-metal dielectric layer and the contact; forming an interconnect opening in the inter-level dielectric layer by etching through a patterned mask down to the contact; forming a metal layer over the inter-level dielectric layer and filling the interconnect opening; performing a planarization process to remove at least a portion of the metal layer from over the inter-level dielectric layer; pre-charging a reaction chamber of a plasma deposition tool without the substrate in the chamber, by generating a first reactive species from a first source gas in the presence of a first plasma at a first temperature; the first source gas including NH 3 and the first temperature being higher than 400° C.; following planarization, introducing the substrate into the pre-charged chamber, with the first plasma terminated and the first reactive species still present in the chamber; with the substrate introduced into the pre-charged chamber, treating the substrate with a second reactive species from a second source gas in the presence of a second plasma at a second temperature; the second source gas including NH 3 and He, the second temperature being lower than 400° C., and the second reactive species being started while the first reactive species is still present in the chamber; and with the substrate still in the chamber, depositing a layer of silicon carbon nitride over a remaining portion of the metal layer using a third source gas including silicon and carbon components.