Patent ID: 7205181

Claim:
A method of fabricating a wafer scale semiconductor integrated circuit structure, the method comprising: forming holes in a solid glass sheet, wherein the holes correspond to the location of bond pads disposed on the surface of a semiconductor substrate, the semiconductor substrate having a plurality of individual semiconductor integrated circuit die disposed therein; depositing a first layer of conductive material on the surface of the solid glass sheet; etching the conductive material to create a pattern of traces for electrically connecting said holes to conductive pads on the solid glass sheet; depositing adhesive on the surface of the semiconductor substrate; forming a trench around each semiconductor integrated circuit die on the semiconductor substrate; depositing hermetic material in the trench cut around each of the semiconductor integrated circuit die; affixing the glass sheet to the semiconductor substrate such that the holes in the solid glass sheet are aligned to match the location of the bond pads on the semiconductor substrate and such that the trench around each semiconductor die in combination with the material deposited in the trench forms a hermetic seal between the solid glass sheet and the semiconductor substrate; depositing a second layer of conductive material on the surface of the solid glass sheet, wherein the second layer of conductive material electrically connects the bond pads on the semiconductor substrate to the conductive material traces on the surface of the solid glass sheet.