Patent ID: 8711160

Claim:
A method, comprising: determining a buffer sequence associated with a signal flow for an electronic circuit, wherein the signal flow includes a plurality of algorithm elements interconnected with connections and processed according to a connection sequence, and wherein the buffer sequence indicates an order of using a plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence; identifying a first algorithm element from the plurality of algorithm elements that can be processed using a processing offloader; generating a first dummy algorithm element and a second dummy algorithm, wherein each dummy algorithm element includes functions for writing to and reading from memory buffers, wherein the first dummy algorithm element is different from the second dummy algorithm element, wherein when the first dummy algorithm element is generated, offloading of the first algorithm element to the processing offloader is initiated, wherein the second dummy algorithm element is positioned to read results from the processing offloader; and modifying the buffer sequence such that the first dummy algorithm element writes to the processing offloader from one of the memory buffers before the first algorithm element is processed, and the second dummy algorithm writes to the memory buffer from the processing offloader after the first algorithm element is processed.