Patent ID: 8067950

Claim:
A semiconductor device, comprising: a board; a chip having an upper surface and a lower surface and mounted on the board, the lower surface of the chip facing the board; a pad group disposed on the lower surface of the chip and electrically connected to an internal circuit in the chip; and a test pad pattern disposed on a region of the lower surface of the chip except for a region of the lower surface of the chip where the pad group is provided, wherein: the pad group includes a plurality of pads formed on the lower surface of the chip, and a plurality of bumps respectively formed on the pads with a barrier metal layer interposed therebetween, and electrically connected to the board, the test pad pattern includes a plurality of test pads formed on the lower surface of the chip, and a plurality of test bumps respectively formed on the test pads with a test barrier metal layer interposed therebetween, and wherein a portion of the test pad pattern is disposed outside the pad group and the portion of the test pad pattern is disposed within the lower surface of the chip.