Patent ID: 7587693

Claim:
A delay calculation apparatus for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice, comprising: a storage device containing a clock circuit delay library archiving clock circuit delay data obtained by delay calculation of a clock circuit; and a delay calculation section performing delay calculation of a structured ASIC including said clock circuit to generate delay calculation result data of said structured ASIC, wherein said delay calculation section is configured to obtain at least a portion of said clock circuit delay data from said clock circuit delay library, and to merge said obtained portion into said delay calculation result data, wherein said clock circuit includes cells and interconnections connected together to form a clock tree, said cells comprising a plurality of leaf cells corresponding to leafs of said clock tree, wherein said clock circuit delay data within said clock circuit delay library includes clock circuit delay time data associated with a circuit portion of said clock circuit from a predetermined portion of said clock circuit to input terminals of said leaf cells, and wherein data of delay times of said leaf cells are excluded from said clock circuit delay library, wherein the data of a delay time of a root cell corresponding to a root of said clock tree that is excluded from said clock circuit delay library is received and stored as a user-circuit-excluded netlist, wherein data corresponding to a netlist of the ASIC designed to cause most severe capacitive coupling is stored as a user-circuit-including netlist, wherein a first and second delay calculations of clock circuits are respectively computed based on the user-circuit-excluded netlist and the user-circuit-including netlist, and wherein a delay difference between clock circuits of the first and second delay calculations is extracted and stored in the storage device.