Patent ID: 7534718

Claim:
A method for fabricating a chip, comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region between said first region and a sidewall of said first pad, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost insulating nitride layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and forming a second metallization structure in said second opening and over said polymer layer, wherein said forming said second metallization structure comprises forming a third metal layer, followed by forming a patterned photoresist layer, followed by electroplating a fourth metal layer, followed by removing said patterned photoresist layer, followed by etching said third metal layer.