Patent ID: 8450809

Claim:
A semiconductor device comprising: a substrate; cell transistors arrayed in a cell matrix shape on the substrate and comprising gate insulating patterns, gate electrodes, common source regions, drain regions and channel regions; word lines configured to electrically interconnect the gate electrodes with each other; common source lines, each common source line being shared between only a pair of the neighboring word lines and being configured to electrically interconnect the common source regions with each other; drain metal contacts and source metal contacts arranged in a straight line on the drain regions; bit lines electrically connected to the drain metal contacts; and impurity regions configured to control a threshold voltage of the channel regions, wherein the channel regions connect the common source lines to the source metal contacts, for respective ones of the common source lines the impurity regions being disposed on a portion of the channel regions connected to one of the pair of the neighboring word lines, so that the respective one of the common source lines is electrically isolated from the other of the pair of the neighboring word lines; wherein the substrate comprises a drain metal contact region where the drain metal contacts are repeatedly arrayed and a source metal contact region where the source metal contacts are repeatedly arrayed; wherein the substrate includes isolation layers and active regions, the isolation layers being disposed in both the drain metal contact region and the source metal contact region; and wherein the isolation layers are isolated in the form of an island, the active regions are formed around the isolation layers in the drain metal contact region, the isolation layers are interconnected with one another, and the active regions do not surround the isolation layers in the source metal contact region.