Patent ID: 7157930

Claim:
A scan flip flop, comprising: an input section including a plurality of nMOS transistors, which receives first logic information and outputs second logic information based on the first logic information, the first logic information including a clock signal, a data signal, a test input signal, and a test selection signal; an output section for receiving information generated based on at least the second logic information and outputting a signal based on the second logic information; a control section for outputting to the input section a control signal which is used by the input section for generating the second logic information from the first logic information; and a first node for transmitting the second logic information from the input section to the output section, wherein the input section includes a selection section for selecting, based on the test selection signal, which of the data signal and the test input signal of the first logic information is validated to generate the second logic information when the clock signal transitions from the low level to the high level, the input section outputs the second logic information to the first node as a high level signal when the clock signal is at the low level, and the number of the nMOS transistors included in a route through which an electric current flows when the first node transitions from the high level to the low level in the input section is greater when the test input signal is selected than when the data signal is selected.