Patent ID: 8521439

Claim:
A method of using a calibration system to generate a latency estimate for calibrating a stimulus-response test system, wherein the method comprises: [a] providing a calibration system comprising a stimulus sensor, a response actuator device, and a first set of one or more processors; [b] providing a stimulus-response test system comprising a stimulus output device for delivering stimuli to a subject, a response input device for receiving responses to the stimuli, a second set of one or more processors, and a response input interface for interfacing between the response input device and the second set of processors; [c] sensing, using the stimulus sensor, a stimulus output event, the stimulus output event being indicative of delivery of stimulus by the stimulus output device to a subject; [d] recording, using one or more of the first and second set of processors, a stimulus time associated with sensing the stimulus output event; [e] generating, by one or more of the first and second set of processors, a calibrator response after sensing the stimulus output event, wherein generating the calibrator response comprises: sending a response actuation signal from the first set of processors to the response actuator device, thereby causing the response actuator device to physically actuate the response input device via mechanical action, and thereby causing the response input device to provide a response input signal to the response input interface; [f] recording, using one or more of the first and second set of processors, a response time associated with generating the calibrator response; [g] determining, using one or more of the first and second set of processors, a calibrator delay (t stim/tresp ) based on a difference between the stimulus and response times; [h] receiving a test system delay (t tot ) at one or more of the first and second set of processors, the test system delay representing a time difference between generating the stimulus at the test system and recording the response at the test system; and [i] determining, using one or more of the first and second set of processors, a latency value (t lat ) based on a difference between the test system delay (t tot ) and the calibrator delay (t stim/resp ).