Patent ID: 8078792

Claim:
A processor comprising: a first page table base address register configured to store a first page table base address locating one or more first page tables in memory; a second page table base address register configured to store a second page table base address locating one or more second page tables in memory; and an execution core coupled to the first page table base address register and the second page table base address register, wherein the execution core is configured to use the one or more first page tables to translate addresses during execution of a guest, and wherein the execution core is configured to use the one or more second page tables to translate addresses during execution of a minivisor, wherein the second page table base address register is dedicated to locating the one or more second page tables for the minivisor, and wherein the minivisor is executed responsive to a first guest exit mechanism that saves a first amount of guest state, and wherein a second guest exit mechanism stores a second amount of guest state that is greater than the first amount.