Patent ID: 7569456

Claim:
A method for forming a MOS transistor having elevated source and drain structures, comprising: providing a sacrificial gate pattern on a substrate; providing an epitaxial layer on the substrate adjacent the sacrificial gate pattern; providing a first insulating layer and a second insulating layer on the epitaxial layer adjacent the sacrificial gate pattern; removing the sacrificial gate pattern to expose a portion of the substrate and wall portions of the epitaxial layer; providing a gate dielectric layer on the exposed portion of the substrate and along the wall portions of the epitaxial layer; providing a gate electrode on the gate dielectric layer; removing the second insulating layer and the first insulating layer; doping the epitaxial layer with impurities using the gate electrode as a mask to form source/drain extension regions in the epitaxial layer proximal to the gate dielectric layer; providing insulating spacers on sidewalls of an upper portion of the gate electrode; and doping the epitaxial layer with impurities using the gate electrode and insulating spacers as a mask to form deep source/drain regions adjacent the source/drain extension regions.