Patent ID: 7647518

Claim:
A processor comprising: a scheduler configured to issue a first instruction operation to be executed; and an execution core coupled to the scheduler and configured to execute the first instruction operation, wherein the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases, wherein each of the plurality of replay sources is configured to detect one or more of the plurality of replay cases; and wherein the scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay of the first instruction operation for a subset of the plurality of replay cases comprising two or more of the plurality of replay cases, and wherein the scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and wherein the scheduler is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset, and wherein the scheduler is configured to issue a second instruction operation from the scheduler that has not been replayed for any of the replay cases in the subset while the first instruction operation is inhibited from issue; and the execution core further comprises a control unit coupled to the plurality of replay sources, wherein the control unit is configured to assert a replay signal to the scheduler to signal a replay for the first instruction operation, and wherein the control unit is further configured to generate a replay type identifying at least one of the plurality of replay cases, and wherein the replay cases that are not included in the subset are grouped and indicated as a replay type that does not require an acknowledgement indication.