Patent ID: 7093061

Claim:
A rate matching circuit comprising: at least one FIFO module comprising: a memory bank having a plurality of individually addressable memory locations; a write pointer that is connected to the memory bank for addressing the memory locations to write data therein; a read pointer that is connected to the memory bank for addressing memory locations to read data therefrom; wherein the write pointer and read pointer are driven by separate clock signals; a look-ahead pointer that is coupled to the read pointer for addressing a first memory location that leads a second memory location addressable by the read pointer; a flag circuit that generates a trigger signal when a difference of addresses in the write pointer and the read pointer exceeds a predetermined threshold; and a detector that is connected to the memory bank for comparing data in the first memory location with a skip datum, the detector asserting a datum-found signal when the data in the first memory location matches the skip datum; and a rate matcher connected to the at least one FIFO module for receiving the trigger signal and the datum-found signal, and for thereby generating a control signal to advance the read pointer to skip the first memory location.