Patent ID: 8063673

Claim:
An electronic circuit comprising: a clock input stage coupled to receive a clock signal, wherein the clock signal alternates between a first logic level and a second logic level; an output stage configured to drive an output signal on an output node; an activation stage coupled to an input node, wherein the activation stage is configured to, responsive to the clock input stage detecting a transition from the first logic level to the second logic level and detecting a logical transition of an input signal on the input node, activate the output stage to drive an output signal on the output node, and wherein the activation stage is configured to inhibit the output stage from activation when the clock signal is at the first logic level; a feedback path coupled to receive the output signal from the output node and coupled to provide a feedback signal based on the output signal to the clock input stage, wherein, at a delay time subsequent to activation of the output stage, the clock input stage is configured to deactivate the activation stage responsive to receiving the feedback signal, and wherein the output stage is configured to be deactivated responsive to deactivation of the activation stage; and a storage element, wherein the storage element is configured to capture a logic value of the input signal when the clock is at the second logic level, store the logic value of the input signal after the clock signal transitions to the first logic level, and to provide the output signal on the output node when the clock signal is at the first logic level.