Patent ID: 7623408

Claim:
A semiconductor memory device outputting data in accordance with each of a first edge and a second edge of a system clock signal, the device comprising: a system clock generating the system clock signal, a first control clock signal, and a second control clock signal; a data sensing output unit respectively providing first and second data to first and second data paths, wherein the first and second data are sensed from selected memory cells; a data output circuit serially outputting the first and second data at a single data Input/Output (I/O) pad; a data transmitter operationally connecting the first data path to the data output circuit through only a single first transmission gate responsive to the first control clock signal, and operationally connecting the second data path to the data output circuit through only a single second transmission gate responsive to the second control clock signal; and a data path controller connected between the data sensing output unit and the data transmitter, and delaying the first data on the first data path by a first delay period using a first delay element and delaying the second data on the second data path by a second delay period different from the first delay period using a second delay element, wherein the first delay element is a first driver disposed along the first data path line, the second delay element is a second driver disposed along the second data path line, and the second driver is smaller than the first driver.