Patent ID: 7143326

Claim:
A method of testing an integrated circuit device having a plurality of embedded memories, each embedded memory characterized by a data width size and a pipeline depth, the method comprising: selecting one of the plurality of embedded memories to test; specifying one or more test parameters including at least one of a latency delay data and an irregular data width masking data; specifying a test pattern from among a common set of pre-generated algorithmic pattern generator test patterns; associating the one or more test parameters with the specified test pattern; and applying the associated test pattern to the selected embedded memory, wherein the irregular data width masking data is configured to be specified when the data width size of the selected embedded memory is irregular, further wherein the latency delay data corresponds to a difference between the pipeline depth of an input and an output of the selected embedded memory and the irregular data width masking data corresponds to a portion of a data access of the selected embedded memory to be masked.