Patent ID: 7123059

Claim:
Circuit comprising signal input ( 11 ) for receiving an input signal (s(t)), a digital output stage ( 15 ) being designed for operation at a supply voltage (V DD ), the output stage ( 15 ) comprising a series of two n-channel CMOS transistors (no 1 , no 2 ; nsw 1 , nsw 2 ) sensitive to voltages across transistor node pairs going beyond a voltage limit (V max ), a common node ( 17 ; SW 1 ) between the two n-channel CMOS transistors (no 1 , no 2 ; nsw 1 , nsw 2 ), an output port ( 16 ), active voltage limiting means ( 14 ; INV 3 , pdio) being arranged between the signal input ( 11 ) and the common node ( 17 ; SW 1 ) for limiting voltages (V max ) at the common node ( 17 ; SW 1 ) to the voltage limit (V max ), the voltage limiting means ( 14 ; INV 2 , pdio) being controllable by the state of the input signal (s(t)) and comprising a plurality of transistors (pd, nd, pswn; INV 3 , pdio) for providing a limited and stable output voltage (V NM ) at the common node ( 17 ; SW 1 ), wherein one of the plurality of transistors is a p-channel CMOS transistor (pswn; pdio) serving as switch, the gate ( 18 ; 38 ) of the p-channel CMOS transistor (pswn; pdio) being controlled by the state of a signal derived from the input signal (s(t)).