Patent ID: 8456193

Claim:
A gate-Q scan circuit, comprising: logic circuitry; a plurality of scan flip flops coupled to the logic circuitry; a plurality of gates coupled between the logic circuitry and the plurality of scan flip flops; and a control node coupled to a first input of each of the plurality of gates; each of the plurality of scan flip flops including a q-output coupled to a second input of a corresponding one of the plurality of gates; the plurality of gates being configured to prevent toggling of the logic circuitry while an enable signal is asserted on the control node; the plurality of gates being farther configured to output a minimal leakage state vector to the logic circuitry in response to the enable signal on the control node, and to pass through signals from each of the q-outputs to the logic circuitry in response to absence of the enable signal on the control line.