Patent ID: 8402406

Claim:
A method of controlling plating stub reflections in a chip package, the method comprising: determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate, wherein selecting a line width of an open-ended plating stub based on the performance characteristics of the bond wire includes: generating, by the resonance optimizer, an eye pattern based on the performance characteristics of the bond wire and the selected line width of the open-ended plating stub; determining, by the resonance optimizer, if the eye pattern is acceptable; if the eye pattern is acceptable, using, by the resonance optimizer, the selected line width of the open-ended plating stub in the design of the signal traces; and if the eye pattern is not acceptable, selecting, by the resonance optimizer, a new line width for the open-ended plating stub in the design of the signal traces; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.