Patent ID: 6968525

Claim:
A chip, comprising: a number 2 M of output bonding pads, where a power index M is a number of layers greater than 1; a plurality of buffering devices, including a buffering device for an i th layer, where a parameter i=1 to M and i is a positive integer, wherein one of the buffering devices for the 1 st layer is disposed at about a middle place between every two of the output bonding pads, each one of the output bonding pads is electrically connected to the corresponding one of the buffering devices for the 1 st layer, one of the buffering devices for the jth layer is disposed at about a middle place between every two of the buffering devices for the j−1th layer, each one of the buffering devices for the j−1th layer is electrically connected to the corresponding one of the buffering devices for the jth layer, wherein 1<j<M+1, and the quantity of j is a positive integer; and a signal source root, used to export a signal, the signal being transmitted to the number 2 M of output bonding pads, going through the buffering devices.