Patent ID: 8847625

Claim:
A multi-valued logic circuit comprising: a multi-valued logic (MVL) clock generator that generates a MVL clock signal comprising a first MVL level, one or more intermediate MVL levels and a Nth MVL level; a single MVL clock signal distribution network connected to the MVL clock generator; a first MVL selection circuit having a first enable/clock input connected to the single MVL clock signal distribution network, a first data input and a first output, wherein the first MVL selection circuit outputs a first binary clock signal via the first output having: (a) a first logic level whenever the MVL clock signal is equal to the first MVL level and the first data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the first MVL level and the first data input receives the second logic level, and (c) a previous logic level of the first binary clock signal whenever the MVL clock signal is not equal to the first MVL level; one or more intermediate MVL selection circuits, each intermediate MVL selection circuit having an intermediate enable/clock input connected to the single MVL clock signal distribution network, an intermediate data input and an intermediate output, wherein each intermediate MVL selection circuit corresponds to a specified intermediate MVL level selected from the one or more intermediate MVL levels and outputs an intermediate binary clock signal via the intermediate output having: (a) the first logic level whenever the MVL clock signal is equal to the specified intermediate MVL level and the intermediate data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the specified intermediate MVL level and the intermediate data input receives the second logic level, and (c) a previous logic level of the intermediate binary clock signal whenever the MVL clock signal is not equal to the specified intermediate MVL level; and a Nth MVL selection circuit having a Nth enable/clock input connected to the single MVL clock signal distribution network, a Nth data input and a Nth output, wherein the Nth MVL selection circuit outputs a Nth binary clock signal via the Nth output having: (a) a first logic level whenever the MVL clock signal is equal to the Nth MVL level and the Nth data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the Nth MVL level and the Nth data input receives the second logic level, and (c) a previous logic level of the Nth binary clock signal whenever the MVL clock signal is not equal to the Nth MVL level.