Patent ID: 8278648

Claim:
An organic thin film transistor (TFT) substrate, comprising: a gate line formed on a base substrate; a data line formed substantially perpendicularly to the gate line, the gate line defining a pixel region together with the data line; an organic TFT comprising a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; a first contact part making contact with the data line and the source electrode to connect the data line to the source electrode, wherein the first contact part is disposed between the data line and the base substrate; a pixel electrode formed in the pixel region; a second contact part making contact with the pixel electrode and the drain electrode to connect the pixel electrode to the drain electrode; and a bank insulating layer including a first contact hole through which the first contact part is connected to the organic TFT and a second contact hole through which the second contact part is connected to the organic TFT, wherein the organic TFT comprises: a gate insulating layer formed on the gate electrode; an organic semiconductor layer formed on the gate insulating layer, the source electrode, and the drain electrode, wherein at least a portion of the source electrode is disposed between the organic semiconductor layer and the first contact part; and a passivation layer formed to cover the organic TFT and a peripheral region of the organic TFT, wherein at least a portion of the organic semiconductor layer is disposed between the passivation layer and the source electrode, wherein the bank insulating layer comprises a first sub bank defining a location of the gate insulating layer, and a second sub bank defining a location of the passivation layer, wherein the first sub bank defines a line hole limiting the position of the gate insulating layer to expose the gate electrode and a peripheral region of the gate electrode, and wherein a region of the gate electrode and the peripheral region of the gate electrode exposed by the line hole has a relatively high affinity to the gate insulating layer, and the first sub bank has a relatively low affinity to the gate insulating layer.