Patent ID: 8194435

Claim:
A memory assembly, comprising: a capacitor, wherein the capacitor is charged by a data-in, and the capacitor is a volatile or a non-volatile capacitor, and the non-volatile capacitor needs refreshing through the data-in; a capacitor status circuit controlled by the status of the capacitor for reflecting the status of the capacitor, wherein the capacitor status circuit comprises a dc source, a first switch and a resistor electrically connected in series with each other, and a read signal as a voltage level is read on the capacitor status circuit to reflect the status of the capacitor, and the on or off of the first switch is controlled by the status of the capacitor; and an erasing circuit for discharging the capacitor, wherein the erasing circuit comprises the capacitor and a second switch electrically connected in series, and the erasing circuit comprises a PDR device and a NDR device electrically connected in series, and the on or off of the second switch is controlled by a control signal.