Patent ID: 8754497

Claim:
An integrated circuit containing an extended drain metal oxide semiconductor (MOS) transistor, comprising: a substrate, said substrate having a first conductivity type; a drain diffused contact region at a top surface of said substrate, said drain diffused contact region having a second conductivity type opposite from said first conductivity type; a source region at said top surface of said substrate, said source region having said second conductivity type; a drift region of said extended drain MOS transistor, said drift region being located in said substrate, in which said drift region has said second conductivity type; stressor Reduced Surface Field RESURF trenches formed in said drift region, extending through a bottom surface of said drift region into said substrate, said stressor RESURF trenches being separated by distances between 200 nanometers and 2 microns, in which said stressor RESURF trenches include: stressor elements in said stressor RESURF trenches, so that said stressor elements have stress greater than 100 megapascals (MPa); and at least one of: dielectric liners in said stressor RESURF trenches contacting said drift region, so that said stressor elements are located on said dielectric liners; and filler elements in gaps of said stressor elements.