Patent ID: 7017054

Claim:
A method of reducing power consumed by a processor in an information handling system having the processor coupled to a memory controller, the method comprising the step of: providing a processor having a lower power state and a higher power state, wherein the processor is associated with a cache and a cache tag, and wherein the processor does not perform a snoop operation while in the lower power state; and performing the snoop operation with a memory controller, wherein the memory controller performs the snoop operation when the processor is in the lower power state, wherein the performance of the snoop operation with the memory controller comprises the steps of: maintaining a mirror of the cache tag in a memory controller, wherein the mirror cache tag is a directory of memory locations in the cache memory; updating the mirror cache tag of the memory controller when information is written to the cache so that the mirror cache tag has the same content as the cache tag of the processor; and performing a snoop operation on the mirror cache tag of the memory controller by determining if an address of a memory location has a match in the mirror cache tag of the memory controller.