Patent ID: 7428630

Claim:
A method of encoding instructions for a processor having two or more external instruction formats and one or more internal instruction formats, the method comprising: (a) selecting initial encoding parameters including a number of effective opcode bits in each external and internal format and a set of mapping functions, each of said mapping functions serving to translate an opcode specified by said opcode bits in one of the external formats to an opcode specified by said opcode bits in at least one of the internal formats; (b) successively selecting first operations, and allocating to each first operation executable by the processor an opcode distinct from that allocated to each other operation in each external and internal format in which the first operation is specifiable, the allocated opcodes being such that each relevant mapping function translates an external-format opcode allocated to the first operation into such an internal-format opcode allocated to the first operation and such that all the internal-format opcodes allocated to the operation have the same effective opcode bits as their related external-format opcodes; and (c) if in the allocation (b) no opcode is available for allocation in each specifiable format for every one of said first operations, determining which of said encoding parameters is constraining the allocation (b), relaxing the constraining parameter, and then repeating the allocation (b) until all of the instructions are encoded.