Patent ID: 7642622

Claim:
A phase changeable memory cell, comprising: a lower interlayer dielectric layer formed on a semiconductor substrate; a lower conductive plug passing through the lower interlayer dielectric layer; another lower conductive plug spaced apart from the lower conductive plug; a phase change material pattern disposed on the lower interlayer dielectric layer to contact the lower conductive plug; another phase change material pattern disposed on the lower interlayer dielectric layer to contact the other lower conductive plug; an upper interlayer dielectric layer covering the phase change material pattern, the other phase change material pattern and the lower interlayer dielectric layer; and a conductive layer pattern disposed on the upper interlayer dielectric layer in direct contact with the phase change material pattern and the other phase change material pattern through plate line contact holes that penetrate the upper interlayer dielectric layer, wherein the conductive layer pattern comprises: a first upper conductive plug filling a first plate line contact hole that penetrates the upper interlayer dielectric layer and being in direct contact with the phase change material pattern; a second upper conductive plug filling a second plate line contact hole that penetrates the upper interlayer dielectric layer and being in direct contact with the other phase change material pattern; and a plate line disposed on the upper interlayer dielectric layer, wherein the first and second upper conductive plugs are in direct contact with the plate line.