Patent ID: 7517741

Claim:
A method of fabricating a semiconductor transistor, comprising: providing a first semiconductor material; providing a buried dielectric material overlying the first semiconductor material; providing a second semiconductor material overlying the buried dielectric material, wherein the second semiconductor material is electrically isolated from the first semiconductor material by the buried dielectric material; and is capable of storing a charge that represents a state of a memory device; forming a channel body including a migration barrier of a third semiconductor material, overlying the second semiconductor material; forming a capping layer of the second semiconductor material on an upper surface of the migration barrier; forming a gate dielectric overlying the capping layer; forming a gate electrode overlying the gate dielectric; and forming source/drain regions adjacent the channel body of the second semiconductor material; wherein the presence of the second and third semiconductor materials in proximity to each other creates an energy band offset wherein the potential energy level of majority carriers in the migration barrier is lower than the potential energy level of majority carriers in the capping layer.