Patent ID: 7015082

Claim:
A process of forming a semiconductor structure, comprising: forming a plurality of high and low density areas of nFETS and pFETs on a substrate, the high density areas exhibiting a gate to gate distance of 130 nanometers or less and the low density areas exhibiting a gate to gate distance of greater than 130 nanometers; forming a thin compressive film of at least one of Si x N y and Si x ON y in a range of 20 to 50 nanometers in channel regions of the high density areas of pFETs exhibiting a compressive stress of approximately −1400 MPa; forming a thin tensile film of at least one of Si x N y and Si x ON y in a range of 20 to 50 nanometers in channel regions of the high density areas of nFETs; forming a thick compressive film of at least one of Si x N y and Si x ON y in a range of 50 to 500 nanometers in channel regions of the low density areas of pFETs; forming a thick tensile film of at least one of Si x N y , and Si x ON y in a range of 50 to 500 nanometers in channel regions of the low density areas of nFETs exhibiting a tensile stress of approximately 700 Mpa, wherein the forming of the thick tensile film includes providing: a temperature of approximately 480° C., a pressure of approximately 6.25 Torr, a spacing between the substrate and electrode of 490 mils, and a flow of 300 sccm of 2% dilute SiH 4 gas, 15 sccm NH 3 gas and 1060 sccm N 2 gas using RF power of 340 watts, and wherein the forming of the thin compressive film includes providing: a temperature of approximately 480° C., a pressure of approximately 5.75 Torr, a spacing between the wafer and the electrode of 395 mils, and a flow of 3000 sccm of 2% dilute SiH 4 gas, 15 sccm NH 3 gas and 1060 sccm N 2 gas using RF power of 900 watts.