Patent ID: 7546557

Claim:
A CMOS transistor, comprising: a semiconductor substrate having a spaced apart first source region and drain region each having a first conductivity type, formed in a semiconductor substrate having a second conductivity type opposite the first conductivity type, to define a channel region therebetween; a first source region area formed at a first end of the channel region and a drain region formed at a second end of the channel region, the first source region capable of receiving a drive voltage and having a width similar to a width of the drain region; a gate electrode overlying the channel region, the gate electrode capable of receiving a control voltage to induce an electric field across the channel; and an additional source region area formed adjacent the first source region area, the first and second source region areas forming an enlarged overall source region area providing increased capacitance over the first source region area, whereby when the electric field is induced across the channel the energy stored by the enlarged overall source region area and released across the channel region is above a minimum threshold.