Patent ID: 8555230

Claim:
A computer based method to arrange signal pins for pairing in an integrated circuit, comprising: determining, in a computer system, an isolation requirement and an area for the integrated circuit; determining, in the computer system, a signal pin pattern that satisfies the isolation requirement within the area by repetitively performing operations, comprising: determining, in the computer system, available signal and ground pin pairs within the area for the integrated circuit; identifying, in the computer system, two diagonally adjacent signal pins; assigning, in the computer system, the two diagonally adjacent signal pins as a first diagonally adjacent signal pin pair; identifying, in the computer system, a diagonal reference line which extends perpendicularly from the first signal pin pair; identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line; and adding, in the computer system, the closest pair of signal pins to the layout.