Patent ID: 7457387

Claim:
A method of clock generation for a transmitter comprising: receiving an external PLL clock signal and providing a first local clock generator and a second local clock generator for respectively generating first and second divided clock signals; generating a synchronization signal for enforcing a phase relationship between the first and second divided clock signals; wherein generating said synchronization signal includes providing a data clock sampler; receiving and sampling a data synchronous clock signal with said data clock sampler and providing sample outputs, and clocking said data clock sampler with the external PLL clock signal; applying said sample outputs to a synchronization pulse generator and generating synchronization pulses; and applying said synchronization pulses to a gated synchronization repower tree, and said gated synchronization repower tree receiving and repowering said rising edge synchronization pulses; and applying said synchronization signal to said first local clock generator and said second local clock generator during a clock training period; said synchronization signal including at least one synchronization pulse applied to said first local clock generator and said second local clock generator during the clock training period.