Patent ID: 7200711

Claim:
An apparatus comprising: a memory controller to generate a first plurality of memory control signals for controlling a dynamic random access memory that has self-refresh capability; and a self-refresh circuit external to the memory controller to place the memory into a self-refresh state in response to a predetermined condition, the self-refresh circuit including a state machine to generate a second plurality of memory control signals for controlling the memory based on a plurality of input signals, each of the second plurality of memory control signals corresponding to a separate one of the first plurality of memory control signals, the self-refresh circuit to select between the first plurality of memory control signals and the second plurality of memory control signals to provide to the memory, based on the plurality of input signals, the self-refresh circuit including a clock generator to receive as input a first clock signal from the memory controller and to output a second clock signal to the memory, the clock generator including a phase locked loop maintaining the second clock signal after a stoppage of the first clock signal to enable the memory to be placed into the self-refresh state.