Patent ID: 7190742

Claim:
A receiver circuit, comprising: a clock and data recovery circuit for receiving an equalized analog data signal and processing the received equalized analog data signal to generate a recovered clock signal, a retimed digital data signal, a means for generating a phase offset enable signal in the form of a pulse coincident with an edge of the retimed data signal, and comprising a differential phase locked loop circuit including a phase frequency detector (PFD), a charge pump and a differential loop filter, the charge pump charging the loop filter by supplying a differential current into the loop filter, the magnitude and polarity of the differential current being controlled by the PFD; the differential loop filter also receiving a differential offset current; a phase offset control circuit for adjusting the phase at which the equalized analog data signal is sampled by the recovered clock signal in response to the phase offset enable signal, comprising a means for generating the differential offset current proportional to a phase offset control signal and enabled by the phase offset enable signal; and, wherein the charge pump includes first and second positive current sources and first and second negative current sources; a first differential switch between the first positive current source and the first negative current source; and a second differential switch between the second positive current source and the second negative current source, the switches being controlled by the PFD and connecting the current sources to the loop filter so as to provide one of three charging states as follows: when the differential current into loop filter is substantially zero; when differential current into loop filter is positive; and when differential current into loop filter is negative.