Patent ID: 7670911

Claim:
A method for manufacturing a vertical MOS transistor comprising: providing a mask pattern on a silicon semiconductor substrate; patterning the silicon semiconductor substrate using the mask pattern as a mask to provide a protrusion-like region protruding upward from a predetermined plane of the silicon semiconductor substrate; forming a silicon oxide film and a silicon nitride film in sequence on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate; increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate by thermal oxidation to form a first insulating film; implanting an impurity into the silicon semiconductor substrate using the mask pattern as the mask and then thermally treating to form a lower impurity diffusion region; removing the silicon oxide film except the first insulating film and the silicon nitride film to expose a silicon side of the protrusion-like region; thermally oxidizing the exposed silicon side of the protrusion-like region to form a second insulating film having a thinner film thickness than a film thickness of the first insulating film; forming a gate electrode over a side of the protrusion-like region; removing the mask pattern; and implanting an impurity into an upper portion of the protrusion-like region and then thermally treating to form an upper impurity diffusion region.