Patent ID: 7362080

Claim:
A power regulator comprising: a pass transistor configured to receive an unregulated first power supply voltage to generate a regulated output voltage varying depending upon a control signal, wherein the pass transistor comprises a first PMOS transistor having a gate coupled to an output terminal of the error amplifier, a source coupled to the first power supply voltage and a drain coupled to an output terminal of the power regulator; a feedback circuit configured to generate a feedback signal; an error amplifier configured to generate the control signal varying depending upon a voltage difference between a reference signal and the feedback signal; a protection circuit configured to scale down a first current flowing through the pass transistor by a predetermined ratio to generate a second current and configured to change a voltage level of the control signal when the scaled-down second current has a value above a predetermined value; and a feedback loop coupled to a mirror circuit, the pass transistor and a current match transistor, the feedback loop including: a second PMOS transistor having a gate coupled to a first node and a drain coupled to a second node; a third PMOS transistor having a source coupled to a drain of the first PMOS transistor, and a gate and drain commonly coupled to the first node; and a first NMOS transistor having a gate coupled to the mirror circuit, a drain coupled to the first node and a source coupled to the feedback circuit.