Patent ID: 6870263

Claim:
An integrated circuit comprising: a dielectric layer formed over a substrate; a first damascene structure in the dielectric layer, the first damascene structure comprising a bottom surface and first and second sidewalls; a first conductor located in the damascene structure, the conductor comprising a conductive material having a random grain orientation; a first liner layer lining the bottom surface and sidewalls of the first damascene structure and encapsulating the first conductor by contacting a top surface of the first conductor, wherein the first liner layer imparts the random grain orientation in the conductive material of the first conductor to improve electromigration lifetime of the first conductor; a second damascene structure in the dielectric layer, the second damascene structure comprising a bottom surface and second sidewalls and disposed above said first damascene structure; a second conductor located in the damascene structure, the conductor comprising a conductive material having a random grain orientation; a second liner layer lining the bottom surface and sidewalls of the second damascene structure and encapsulating the second conductor by contacting a top surface of the second conductor, wherein the second liner layer imparts the random grain orientation in the conductive material of the second conductor to improve electromigration lifetime of the second conductor; and wherein said second liner layer is in contact with said first liner layer.