Patent ID: 7583774

Claim:
A clock synchroniser for generating a local clock signal synchronised to a received clock signal, comprising: a reference oscillator arranged to provide a reference signal having a reference frequency; a synthesiser circuit arranged to synthesise the local clock signal from the reference signal, the synthesiser circuit comprising a phase-locked-loop circuit including a phase detector, having a first input arranged to receive the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to a second input of the phase detector, the divider being controllable to set a frequency division value N along said path to determine a ratio of a local clock frequency to the reference frequency wherein the phase locked loop circuit is a fractional-N phase locked loop circuit, the divider being controllable to achieve a non-integer average value of N; a clock comparison circuit arranged to receive the local clock signal and a received clock signal, and adapted to generate a first digital signal indicative of an asynchronism between the local and remote clock signals; and a control link linking the clock comparison circuit to the divider, the control link being arranged to receive the first digital signal and to provide a control signal to the divider to adjust the frequency division value N according to the first digital signal to alter the local clock frequency and reduce the asynchronism.