Patent ID: RE41751

Claim:
An instruction conversion apparatus that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions capable of being executed in parallel, the instruction conversion apparatus comprising: assigning means for successively assigning instructions in the instruction sequence to parallel execution codes; and control means for controlling the assigning means so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning means is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor; wherein the target processor includes (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including s decoders that correspond to 1 st to s th registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1 st to s th registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the assigning means assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, one of an opcode and an operand of the long instruction to a u th (where u is any integer such that 1<u<s) unit field between the 1 st unit field and the s th unit field, and only an operand of the long instruction to unit fields from a (u+1) th unit field to (u+k−1) th unit field.