Patent ID: 8421503

Claim:
A latch circuit comprising: an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the external input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the external input signal; and a feedback path through which the external input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a first pMOS region, a first nMOS region, a second pMOS region, and a second nMOS region are arranged in the semiconductor substrate in order, the first CMOS inverter circuit includes a first P-polarity drain formed in the first pMOS region and a first N-polarity drain formed in the second nMOS region, and the second CMOS inverter circuit includes a second P-polarity drain formed in the second pMOS region and a second N-plurality drain formed in the first nMOS region.