Patent ID: 8009500

Claim:
A semiconductor device comprising: a plurality of memory cells arranged in rows and columns; a plurality of bit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding column; a plurality of cell power supply lines, arranged corresponding to the memory cell columns, each for supplying a first power supply voltage to the memory cells on a corresponding column; and a plurality of write assist circuits, arranged corresponding to the memory cell columns, each for selectively shutting off supply of said first power supply voltage to a corresponding cell power supply line according at least to a voltage on the bit line in a corresponding column in a data write operation, wherein each of the write assist circuits further includes a clamp element for clamping the voltage on the corresponding cell power supply line at a second power supply voltage that is lower than the first power supply voltage, and the second power supply voltage is applied to the plurality of memory cells.