Patent ID: 6989582

Claim:
A method for making a chip, comprising the steps of: forming a first oxide layer over a substrate; forming a first die boundary channel in said first oxide layer that extends completely through said first oxide layer and to said substrate; forming a dielectric layer over said first oxide layer and within at least a lower portion of said first die boundary channel; defining first and second die on opposite sides of a first die boundary, wherein said first die boundary extends along at least a portion of said first die boundary channel after both have been formed, wherein each of said first and second die cornprises a microelectromechanical assembly, and wherein each of said first and second die corresponds with one field of a photolithographic stepper; forming a die boundary channel electrical trace on a portion of said dielectric layer that is within said first die boundary channel, wherein said die boundary channel electrical trace is electrically interconnected with said microelectromechanical assembly of said first die, and wherein said die boundary channel electrical trace is also electrically interconnected with said microelectromechanical assembly of said second die; and separating said first die from said second die, wherein at least part of said separating step is along at least a portion of said first die boundary channel, wherein said separating step severs said die boundary channel electrical trace into a first portion that is associated with said first die and a second portion that is associated with said second die and such that said first and second die are no longer electrically interconnected.