Patent ID: 8199550

Claim:
A magnetic memory device comprising: a plurality of MRAM cells arranged in matrix form and each having a series body of a variable magnetoresistive element and a selection transistor; a plurality of word lines disposed corresponding to respective rows of the MRAM cells and coupled with gates of the selection transistors of the MRAM cells of the corresponding rows respectively; and a plurality of piling wirings provided corresponding to the word lines and electrically coupled to the corresponding word lines at predetermined intervals, wherein at each of the MRAM cells, the selection transistor has first and second impurity regions disposed opposite to each other, wherein the corresponding word lines are disposed so as to cross between the first and second impurity regions along a row direction to thereby configure the gates, wherein the first impurity regions are disposed in separated form every MRAM cells along the row direction and electrically coupled to their corresponding variable magnetoresistive elements, wherein each of the MRAM cells has first and second adjacent MRAM cells adjacent in the directions opposite to each other in the row direction, and wherein a first distance L 1 in the row direction to each of the first impurity regions of the MRAM cell and the first adjacent MRAM cell is longer than a second distance L 2 extending along the row direction to each of the first impurity regions of the MRAM cell and the second adjacent MRAM cell.