Patent ID: 7816228

Claim:
A method of manufacturing a semiconductor device, comprising: forming a sacrificial layer and an active layer on a substrate having a first region and a second region; partially etching the sacrificial layer, the active layer and the substrate to form an isolation trench defining an isolation region and an active region; partially filling the isolation trench with a first isolation layer, the first isolation layer in the first region having a step height greater than side portions of a gate region and the first isolation layer in the second region having a step height greater than the gate region; removing the sacrificial layer to form an opening separating the substrate and the active layer; forming an insulating layer liner along the first isolation layer, sidewalls of the isolation trench and the active layer to fill the opening; completely filling the isolation trench with a second isolation layer; partially removing the insulating layer liner to expose an upper surface of the active layer in the gate region of the first region and the upper and sidewall surfaces of the active layer in the gate region of the second region; and forming a gate oxide layer and a gate electrode on the exposed active layer.