Patent ID: 7555630

Claim:
A processing unit, comprising: a first multi-threaded processing element configured to process more than one thread; and a second multi-threaded processing element configured to process more than one thread coupled to the first processing element by a first bus to enable passing of context data between threads in packet processing, the first bus comprising a control information bus to transfer control information and a data information bus to transfer data information, the second processing element comprising a first circuit to: receive control information and data information for the second processing element from the first bus, insert control information and data information for the first processing element onto an available slot on the first bus, and send on the first bus control information and data information for other processing elements connected to the first bus; wherein the control information comprises: information for a target processing element, a target thread number, a number of words for transfer, a next neighbor register number, and a signal number to target processing element to indicate transfer complete.