Patent ID: 7113435

Claim:
A method of testing a memory device, comprising: comparing data signals for a given bit location for each word of a page of output of the memory device and generating a first output signal having a first logic level if all the data signals for the given bit location have a first data value and a second logic level if any of the data signals for the given bit location have a second data value, wherein the page of output comprises two or more words and each word of the page of output comprises two or more bit locations; comparing the data signals for the given bit location for each word of the page of output of the memory device and generating a second output signal having the second logic level if all the data signals for the given bit location have the second data value and the first logic level if any of the data signals for the given bit location have the first data value; and comparing the first and second output signals and indicating a failure of the memory device if the first and second output signals have the same logic level.