Patent ID: 7254509

Claim:
A method for testing a memory of a processor, said method comprising: generating a test code segment including a number of selected opcodes; wherein generating the test code segment includes: storing a set of possible opcodes in a plurality of storage locations; iteratively generating a pseudo-random value; and after each iteration, using the resulting pseudo-random value to select an opcode from the set of possible opcodes until a number of opcodes have been selected; executing the test code segment from a particular location within the memory for a first iteration; saving within the memory, a first test result of the execution of the test code segment after the first iteration; executing the test code segment for a plurality of subsequent iterations and after each iteration of the test code segment, shifting the test code segment a predetermined number of locations from the particular location within the memory; comparing test results of each subsequent iteration with the first test result; determining whether any of the subsequent test results are different than the first test result; and providing a failure notification in response to determining that any of the subsequent test results are different than the first test result.