Patent ID: 8392905

Claim:
A compiling apparatus comprising a processor which compiles a program written in a high-level programming language or an assembly language into a machine language code on which a target processor operates, the compiling being performed by a computer, said compiling apparatus comprising: a first use instruction judger operable to judge whether or not a register of the target processor is used for a first use based on each of instructions in the program; and a second use instruction generator operable to generate the machine language code to use the register for a second use when said first use instruction judger judges that the each of instructions does not to use the register for the first use, the second use being different from the first use, wherein the second use is for a complement to an instruction of which a value operand overflows an operand width when the instruction in the program is converted into the machine language code, the complement is to divide the instruction, of which the value operand overflows the operand width, into plural instructions using the register, and wherein said first use instruction judger is operable to judge an availability of the register to be used for the first use according to an area of a value which an operand can obtain.