Patent ID: 7342286

Claim:
An electrical node of a transistor comprising: two gate patterns disposed on an active region of a semiconductor substrate, each having a first conductive layer pattern; a buried interlayer insulating layer disposed on the semiconductor substrate to cover the gate patterns having a buried contact hole on the active region between the gate patterns passing through the buried interlayer insulating layer; an etch buffer layer between the gate patterns and the buried interlayer insulating layer and between the buried interlayer insulating layer and the semiconductor substrate in a direction perpendicular to the gate patterns; an impurity region disposed in the semiconductor substrate below the buried contact hole located between the gate patterns and surrounded by the semiconductor substrate; a contact hole spacer disposed on a sidewall of the buried contact hole; and a buried conductive layer covering the contact hole spacer and filling the buried contact hole, wherein a second conductive layer pattern is disposed in the semiconductor substrate between the gate patterns, the buried contact hole is disposed on the second conductive layer pattern of the semiconductor substrate, and the sidewall of the buried contact hole is at least disposed to be aligned with a vertical plane passing through a side portion of the active region.