Patent ID: 7184302

Claim:
A method to reduce area occupied by a MRAM array having word lines whose action is local to a segment of said MRAM, comprising: providing a number of MTJs that have a common bottom electrode; providing a global word line current source; through a segmented word line select transistor, connecting a local word line to said global word line current source, said local word line being limited to interacting with only said MTJs in said segment; passing said number of global bit lines through said MRAM segment; for each global bit line in said segment, providing a local bit line, having first and second ends, that is limited to said segment and that does not overly an MTJ; providing first and second segment select bit lines disposed to lie on opposing sides of said segment; connecting said first and second ends of each local bit line to the same global bit line through transistors whose control gates are connected to said first and second segment select bit lines respectively; connecting each local bit line to said common bottom electrode through a line that allows said local bit line to interact with an MTJ; connecting said common bottom electrode to a single common isolation transistor whereby said area reduction is achieved; then activating said local bit line isolation transistor and said read selection transistor; and sending a sense current through said MRAM to a current sink via said global bit line, said local bit line isolation transistor, said local bit line, and a read selection transistor thereby sensing information stored in a single MTJ.