Patent ID: 7088626

Claim:
A bias voltage applying circuit comprising: a first bias circuit which supplies a current by applying a predetermined bias voltage to a memory cell selected from a main memory array comprising a plurality of arranged memory cells, converts a memory cell current which flows depending on a storage state of the selected memory cell to a voltage level and outputs it; and a second bias circuit which supplies a current by applying a predetermined bias voltage to a reference memory cell, converts a memory cell current which flows depending on a storage state of the reference memory cell to a voltage level and outputs it, wherein each of the first bias circuit and the second bias circuit which have the same bias circuit constitution comprises: a first active element between a power supply node and a junction node, in which a current is controlled so as to prevent a voltage level at the junction node from fluctuating; a second active element between the power supply node and an output node, in which a current is controlled such that a voltage level at the output node is changed in the direction opposite to a voltage level at the junction node of the other side of the bias circuit; a third active element between the junction node and a current supply node, in which a current from the first active element is supplied to the selected memory cell or the reference memory cell, and a voltage level of the current supply node is controlled at a predetermined level; and a fourth active element between the output node and the current supply node, in which a current from the second active element is supplied to the selected memory cell or the reference memory cell, and a voltage level of the current supply node is controlled at a predetermined level.