Patent ID: 7383421

Claim:
A data processing system, said data processing system comprising: an associative memory device containing n-cells, each of said n-cells including a processing circuit and m-bits of memory capacity, wherein each of said n-cells include a state field and a data field, said state field comprising a marker bit for encoding a local state of each of said n-cells, thereby indicating one of a marked state and a non-marked state of each of said n-cells; a controller for issuing one of a plurality of instructions to said associative memory device, the plurality of instructions comprising a ‘right limit’ command whereby a right limit of a search space is set to a leftmost cell of said n-cells in said marked state; a clock device for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second, said clock device outputting said synchronizing clock signal to said associative memory device and said controller; and wherein said controller globally communicates one of said plurality of instructions to all of said n-cells simultaneously, within one of said clock cycles.