Patent ID: 8222880

Claim:
A DC-DC conversion device, comprising: a control signal generator to generate a control signal according to a delay signal; a conversion module coupled to the control signal generator for converting an input voltage into an output voltage according to the control signal; and a comparison module coupled to the control signal generator and the conversion module for comparing an output voltage of the DC-DC conversion device with a reference voltage to generate a comparison result and outputting the delay signal according to the comparison result, an enable signal and a clock signal, wherein the comparison module comprises: a voltage divider coupled to the conversion module and the comparison module to generate a divided voltage by dividing the output voltage, wherein the voltage divider comprises: a first resistor having a first terminal coupled to the conversion module and a second terminal coupled to the comparison module; and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a grounded second terminal, wherein the first resistor and the second resistor divide the output voltage to generate and input the divided voltage to the comparison module a comparison unit coupled to the voltage divider for comparing the reference voltage and the divided voltage resulted from the voltage divider to generate a comparison signal; and at least one delay unit coupled to the comparison unit and the control signal generator to generate the delay signal according to the comparison signal, the enable signal and the clock signal, wherein the delay unit comprises: a control circuit for generating a clock input signal and a reset signal according to the comparison signal, the enable signal and the clock signal, wherein the control circuit comprises: a NAND gate for executing a NAND operation on the enable signal and the comparison signal to generate a first operation signal; a second computing unit coupled to the first computing unit for executing a second logic operation on the clock signal and the first operation signal to generate a second operation signal; a first processing unit coupled to the first computing unit for processing the first operation signal to generate the reset signal; and a second processing unit coupled to the second computing unit for processing the second operation signal to generate the clock input signal; and a processing circuit coupled to the control circuit for generating the delay signal according to the clock input signal and the reset signal.