Patent ID: 8743634

Claim:
A method for interfacing a memory controller and a source synchronous memory, comprising: generating a set of double rate strobes by gating a continuous double rate dock in order to enable said set of double rate strobes only for duration of a data transfer from a memory controller to a source synchronous memory in order to reduce power; moving data and control from a single data rate continuous clock domain to a source synchronous data rate with respect to said source synchronous memory by sampling with said set of double rate strobes; shifting a phase of said set of double rate strobes in relation to said continuous single rate clock and changing said phase of said set of double rate strobes in order to dynamically switch a phase relationship of said source synchronous data signal to said memory; and independently programming each bit-slice to generate an output to said memory at each phase relative to said controller single rate clock by said set of double rate strobes.