Patent ID: 8853832

Claim:
A method of making a MOS transistor, the method comprising: forming a conductive gate structure above a gate dielectric; and forming at least a portion of a shielding structure directly above the conductive gate structure, wherein the shielding structure includes a first shielding layer and a second shielding layer spatially-overlapping the first shielding layer, wherein the first shielding layer is associated with a first metallization layer of a plurality of metallization layers formed above the MOS transistor and the second shielding layer is associated with a second metallization layer of the plurality of metallization layers, wherein the shielding structure is electrically-coupled to a reference voltage to reduce a drain-source mutual capacitance between a drain terminal and a source terminal of the MOS transistor, wherein a width dimension of the shielding structure is less than or equal to a width dimension of the conductive gate structure.