Patent ID: 8560984

Claim:
A system for integrated circuit design, the system comprising: instructions stored in a storage device that when executed by a processor provide a synthesizer to generate a netlist to satisfy timing specifications in response to a high level description, the synthesizer including a logic synthesizer to generate functional logic and nets of the netlist in response to the high level description, and a physical layout estimator in communication with the logic synthesizer to receive one or more portions of the netlist, the physical layout estimator to further receive a physical library including parasitic capacitance and parasitic resistance information of a semiconductor manufacturing process for a physical wire-load model, for each net of the netlist the physical layout estimator to determine one or more equivalent net lengths from one or more of fanout information, area information, placement information, congestion information, aspect ratio information, height and width information representing parasitic resistances and capacitances associated with each net; generate a net length estimate in response to the respective one or more equivalent net lengths; and calculate a timing delay in response to the physical wire-load model and the net length estimate.