Patent ID: 8159446

Claim:
A gate driving circuit comprising a plurality of stages, wherein at least a first stage of the plurality of stages comprises: a first node and a second node; a pull-up driving unit which receives a first carry signal from a second stage of the plurality of stages or a start signal and outputs a control signal to the first node, the control signal having: a first voltage level during a preliminary period, a second voltage level higher than the first voltage level during a gate active period subsequent and adjacent to the preliminary period, a third voltage level lower than the second voltage level during a first gate inactive period subsequent and adjacent to the gate active period, and a fourth voltage level lower than the third voltage level during a second gate inactive period subsequent and adjacent to the first gate inactive period; a pull-up unit which receives the control signal and a clock signal and outputs a gate-on signal to the second node during the first gate active period; a carry output unit which receives the control signal and the clock signal and outputs a second carry signal to a third stage during the first gate active period; and a pull-down unit which receives a gate-off signal and the first carry signal from the second stage and outputs the control signal having the fourth voltage level to the first node during the second gate inactive period, wherein the gate circuit of a plurality of shift registers further comprises a first dummy stage, a second dummy stage and a third dummy stage, which receive the start signal.