Patent ID: 7235460

Claim:
An integrated circuit structure fabrication method, comprising: forming n-type and p-type regions within a substrate; forming an oxidation barrier layer on a surface of the substrate over the n-type and p-type regions; forming a first patterned layer exposing the oxidation barrier layer over first isolation areas in the n-type region and covering substantially all of the oxidation barrier layer over the p-type region and over active device areas in the n-type region; removing portions of the oxidation barrier layer exposed by the first patterned layer to expose the first isolation areas; implanting a first, p-type channel-stop dopant into the first isolation areas exposed by the first patterned layer and the remaining oxidation barrier layer; removing the first patterned layer; forming a second patterned layer on the remaining oxidation barrier layer over the n-type and p-type regions and on the exposed surface of the substrate in the first isolation areas, the second patterned layer exposing the remaining oxidation barrier layer over second isolation areas in the p-type region and covering substantially all of the remaining oxidation barrier layer over the n-type region and active device areas in the p-type region; removing portions of the remaining oxidation barrier layer exposed by the second patterned layer to expose the second isolation areas; implanting a second, n-type channel-stop dopant into the second isolation areas exposed by the second patterned layer and the remaining oxidation barrier layer; removing the second patterned layer; and growing a field oxide on the surface of the substrate in the first and second isolation areas where exposed by the remaining oxidation barrier layer in a single oxidation step.