Patent ID: 8111757

Claim:
A video signal processor comprising: a receiver for receiving input video data comprising a first encoded video signal and error redundancy data for a second encoded video signal, the second encoded video signal being a reduced data rate version of the first encoded video signal and the input video data not comprising the second encoded video signal; a video unit for generating the second encoded video signal from the first encoded video signal; an error unit for detecting an error for at least a first segment of the second encoded video signal in response to the error redundancy data; and a combiner for generating combined video data by combining a second segment of the first encoded video signal corresponding to the first segment and the first segment in response to the detection of the error; wherein the video unit comprises: a lossless decoding unit for generating first video encoding data for the first encoded video signal; a data reduction unit for generating second video encoding data for the second encoded signal by applying a data reduction to the first video encoding data.