Patent ID: 8399954

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor substrate; a pad comprising a top wiring line exposed at a surface of the integrated circuit device, the pad extending directly over a first region between the substrate and the pad, the first region directly under the entire pad; an electrostatic protective element electrically connected with the pad, the electrostatic protective element extending below a second region directly above the substrate and laterally separated from the first region, the second region directly above the entire electrostatic protective element; a first line electrically connected with the pad and the electrostatic protective element, and extended at least between the first and second regions; a first plug contact extending between and electrically connecting the first line and the electrostatic protective element; a second line electrically connected with the pad and the electrostatic protective element and provided above the first line, and extended at least between the first and second regions; a second plug contact, directly above the electrostatic protective element, and extending between and electrically connecting the second line and the first line; a third plug contact, different from the second plug contact, formed between the second line and the first line and is electrically connected to the second line and to the first line, respectively, and arranged at least between the first and second regions, wherein said third plug contact is arranged so as not to be directly over any electrostatic protective element; and a plurality of insulating layers formed below the first line, between the first line and the second line, and above the second line, at least one of the insulating layer containing a low dielectric constant film, the low dielectric constant film having a dielectric constant lower than a dielectric constant of silicon dioxide.