Patent ID: 8159268

Claim:
A programmable buffer of a semiconductor device comprising: an input and an output; and a programmable interconnect structure comprising: a plurality of fixed interconnects including metal and via geometries; and a plurality of selectable interconnect geometries, wherein selecting a selectable geometry connects a first of said fixed interconnects to a second of said fixed interconnects; wherein said input and said output is configured to electrically connect to a subset of said fixed interconnects by the selectable interconnect geometries; and a programmable signal restoring unit comprising a plurality of transistors, at least one said transistor having: a common gate region and a common source region; and a first drain region coupled to the programmable buffer output comprising said fixed interconnect; and a second drain region comprising said fixed interconnect, said first and second drain regions isolated from each other, wherein said selectable geometry is configured to electrically connect the first and second drain regions; wherein, selecting a subset of the selectable interconnect geometries program the programmable buffer input and output connections, and the programmable buffer signal drive strength.