Patent ID: 7760880

Claim:
A communication terminal, comprising: a decoding circuit configured to decode encoded data that as been encoded according to a coding scheme defining a parity check matrix having sets of linearly shifted parity check equations, the decoding circuit comprising: node data reordering circuitry configured to: receive channel soft input data; identify information bits of the received soft input data and arrange the identified information bits in a first order; and identify parity bits of the received soft input data and reorder and arrange the identified parity bits in a second order, the parity bits reordered to correspond to a set of linearly shifted parity check equations defined by the parity check matrix; an input buffer configured to store the information bits arranged in the first order and the parity bits arranged in the second order; a bit node processing block comprising a plurality of bit node processors, the bit node processors arranged in parallel sets of bit node processors, each parallel set of bit node processors corresponding to the set of linearly shifted parity check equations defined by the parity check matrix, the bit node processing block further configured to access the input buffer to read the information bits arranged in the first order and the parity bits arranged in the second order and generate edge data; a check node processing block comprising a plurality of check node processors, the check node processors arranged in parallel sets of check node processors according to bit node and check node edges defined by the parity check matrix, the check node processing block further configured to generate edge data; and an edge memory configured to store the edge data.