Patent ID: 7173337

Claim:
A semiconductor device comprising: a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring; a first wiring trench formed in the second insulating film; a first connection hole formed in the second insulating film to extend from the first wiring trench to the first wiring; a first dummy connection hole formed in the second insulating film to extend from the first wiring trench to a non-forming region of the first wiring; a second wiring buried in the first connection hole and the first wiring trench to be connected electrically to the first wiring and also buried in the first dummy connection hole, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface; a third insulating film formed on the second wiring to cover the second wiring; a second wiring trench formed in the third insulating film; a second connection hole formed in the third insulating film to extend from the second wiring trench in the third insulating film to the second wiring; a second dummy connection hole formed in the third insulating film to extend from the second wiring trench in the third insulating film to a non-forming region of the second wiring; and a third wiring buried in the second connection hole and the second wiring trench in the third insulating film to be connected electrically to the second wiring and also buried in the second dummy connection hole in the third insulating film, and formed such that a surface of the third wiring and a surface of the third insulating film constitute a substantially flat surface; wherein, if viewed from an upper side of the third wiring, parts of the first connection hole and the first dummy connection hole, in which the second wiring is buried, and parts of the second connection hole and the second dummy connection hole, into which the third wiring is buried, are arranged not to oppose mutually in the direction perpendicular to any one of extending directions of the second wiring and the third wiring.