Patent ID: 6987701

Claim:
A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array in response to address information; a controller responsive to control signals; an input circuit and an output circuit for inputting data to and outputting data from said array of memory cells in response to said controller; and a locked loop for providing clock signals for use in said memory device, said locked loop comprising: a delay line producing a local clock signal, said delay line being responsive to FAST and SLOW control signals for advancing and retarding, respectively, the phase of the local clock signal; a phase detector circuit capable of phase discrimination between a reference clock signal and the local clock signal down to approximately 10 picoseconds; an arbiter circuit responsive to said phase detector circuit, for generating mutually exclusive UP and DOWN signals; and a filter for receiving said UP and DOWN signals and for producing said FAST and SLOW control signals, respectively, therefrom.