Patent ID: 8904255

Claim:
An integrated circuit comprising: scan test circuitry comprising at least one scan chain having a plurality of scan cells; additional circuitry subject to testing utilizing the scan test circuitry; and a clock distribution network configured to provide a plurality of clock signals to respective portions of the integrated circuit; the clock distribution network comprising: clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal and a functional enable signal; wherein the scan shift control signal is also utilized to cause the scan cells of the scan chain to form a serial shift register during scan testing; and wherein the clock gating circuitry is configured to control delivery of the clock signals along the respective clock signal lines of the clock distribution network utilizing controllable clock gating latches serially inserted in each line in a manner that permits determination of whether a particular clock delay defect on one of the clock signal lines that causes a scan error during scan testing will also cause a functional error during functional operation.