Patent ID: 8363475

Claim:
An only-one-polysilicon layer non-volatile memory unit cell comprising: a first N-type transistor pair having a first transistor and a second transistor that are connected in series along a read path and of the same type, the first transistor and the second transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated and the charges movement are identically the same in the first floating polysilicon gate of the first transistor and the second floating polysilicon gate of the second transistor when the non-volatile memory unit cell is at write or data deleting mode; a first control gate coupled to the first floating polysilicon gate through a first capacitive coupling junction; a second control gate coupled to the second floating polysilicon gate through a second capacitive coupling junction; a first source/drain junction of the first transistor is coupled to a second source/drain junction of the second transistor, wherein the first source/drain junction and the second source/drain junction are physically isolated from external power supplies; and a P-type transistor pair having a third transistor and a fourth transistor that are connected in parallel and of the same type, the third transistor and the fourth transistor having a third floating polysilicon gate and a fourth floating polysilicon gate, respectively, wherein the third floating polysilicon gate and the fourth floating polysilicon gate are electrically or physically isolated, the third floating polysilicon gate physically coupled to the first floating polysilicon gate, the fourth floating polysilicon gate physically coupled to the second floating polysilicon gate.