Patent ID: 7724062

Claim:
An output buffer circuit comprising: a first level converter for generating a first signal based on a data input signal having an amplitude range between a first power supply potential and a ground reference potential, wherein the first signal has an amplitude range between a second power supply potential, which differs from the first power supply potential, and the ground reference potential; a second level converter for generating a second signal having an amplitude range between the second power supply potential and the ground reference potential based on a control input signal having an amplitude range between the first power supply potential and the ground reference potential, wherein the first signal falls with a delay from the second signal; an output circuit for generating an output signal having one of three values of the ground reference potential, second power supply potential, and high impedance based on the first signal and second signal; and a timing adjustment circuit for compensating for the fall delay of the first signal from the second signal during power activation and coupled to a first node of the first level converter and a second node of the first level converter, wherein a level of the first node increases according to the first power supply potential during the power activation and a level of the second node increases according to the second power supply potential during the power activation.