Patent ID: 8349694

Claim:
A method, comprising: forming a first gate electrode structure above a first semiconductor region of a semiconductor device and a second gate electrode structure above a second semiconductor region, said first and second gate electrode structures comprising a gate insulation layer, a semiconductor electrode material formed above said gate insulation layer and a dielectric cap layer formed above said semiconductor electrode material; forming a spacer structure on sidewalls of said first and second gate electrode structures; forming a mask layer above said first semiconductor region and said first gate electrode structure; performing an annealing process to densify said mask layer; forming cavities in said second semiconductor region by using said dielectric cap layer and said spacer structure of said first gate electrode structure and said densified mask layer as an etch mask; forming a strain-inducing semiconductor alloy in said cavities by using said dielectric cap layer and said spacer structure of said first gate electrode structure and said densified mask layer as a growth mask; removing said densified mask layer by using said dielectric cap layer and said spacer structure of said first and second gate electrode structures as an etch mask; and forming drain and source regions in said first and second semiconductor regions.