Patent ID: 7692285

Claim:
A semiconductor device for driving a three-phase motor, comprising: a first tab which has a main surface and a back surface on an opposite side of the main surface; a second tab which has a main surface and a back surface on an opposite side of the main surface; a third tab which has a main surface and a back surface on an opposite side of the main surface; a first semiconductor chip including a pMISFET is mounted over the main surface of the first tab; a second semiconductor chip including a pMISFET is mounted over the main surface of the second tab; a third semiconductor chip including a pMISFET is mounted over the main surface of the third tab; a fourth semiconductor chip including an nMISFET is mounted over the main surface of the first tab; a fifth semiconductor chip including an nMISFET is mounted over the main surface of the second tab; a sixth semiconductor chip including an nMISFET is mounted over the main surface of the third tab; a plurality of first leads electrically connected with each of the first, second, and third semiconductor chips; a plurality of second leads which are disposed in an opposed position of the plurality of first leads and electrically connected with each of the fourth, fifth, and sixth semiconductor chips; and a sealing portion that seals a part of the first tab, a part of second tab, a part of third tab, parts of the plurality of first leads, parts of the plurality of second leads, and the semiconductor chips, wherein the second tab is disposed between the first tab and the third tab; wherein the first, second, and third semiconductor chips are disposed nearer the plurality of first leads than the plurality of second leads; wherein the fourth, fifth, and sixth semiconductor chips are disposed nearer the plurality of second leads than the plurality of first leads; wherein a drain of the pMISFET of the first semiconductor chip and a drain of the nMISFET of the fourth semiconductor chip are electrically connected with each other through the first tab; wherein a drain of the pMISFET of the second semiconductor chip and a drain of the nMISFET of the fifth semiconductor chip are electrically connected with each other through the second tab; wherein a drain of the pMISFET of the third semiconductor chip and a drain of the nMISFET of the sixth semiconductor chip are electrically connected with each other through the third tab.