Patent ID: 7855919

Claim:
A semiconductor device comprising a non-volatile memory, the non-volatile memory comprising: a memory cell array comprising a plurality of memory cells arranged in a matrix form, each of the memory cells comprising: a memory transistor comprising a pair of electrodes, an active region, a control gate electrode, and a charge storage region between the control gate electrode and the active region; a selection transistor comprising a pair of electrodes, and a gate electrode, wherein one of the pair of electrodes of the selection transistor is electrically connected to the control gate electrode of the memory transistor, a control circuit electrically connected to at least one of the plurality of memory cells, the control circuit comprising: a constant current source electrically connected to one of the pair of electrodes of the memory transistor; and an operational amplifier comprising two inputs and an output, wherein the output is electrically connected to the other one of the pair of the electrodes of the selection transistor, and one of the two inputs is electrically connected to the one of the pair of electrodes of the memory transistor.