Patent ID: 7705654

Claim:
A fast active DCAP cell connected to a first rail and to a second rail, said fast active DCAP cell comprising: a first NMOS transistor having its drain and source connected to the first rail, and a first PMOS transistor having its drain and source connected to the second rail, wherein the gate of the first NMOS transistor is connected to the drain of a second PMOS transistor and to the drain of a third PMOS transistor, and the second and third PMOS transistors have their sources connected to the second rail, and wherein the gate of the first PMOS transistor is connected to the drain of a second NMOS transistor and to the drain of a third NMOS transistor, and the second and third NMOS transistors have their sources connected to the first rail, wherein the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor.