Patent ID: 8271240

Claim:
A method of electronic design automation implemented by a processor of a computer, the method comprising: (a) the processor determining for each of a plurality of layers of an analytical or computer model of a device residing in a memory accessible by the processor a discretized mesh of current conducting material of said layer; (b) the processor storing the discretized meshes determined in step (a) in said memory; (c) the processor determining for each discretized mesh stored in step (b) a corresponding or related impedance matrix having cells, wherein each cell of each impedance matrix includes an impedance value Z ij which is based on a potential or voltage (V i ) induced in a cell i of the corresponding discretized mesh due to an initial charge density or current (I j ) determined to exist in a cell j of the corresponding discretized mesh in response to an exemplary bias applied to said discretized mesh; (d) the processor dispatching to each of a plurality of node computers on an electronic communications network a unique subset of the cells of the impedance matrices including the impedance values determined in step (c); and (e) responsive to the dispatching in step (d) to each node computer, the processor either: (1) receiving from said node computer via the electronic communications network final charge densities or currents estimated to exist on a subset of the cells of at least one discretized mesh; or (2) determining in cooperation with said node computer via the electronic communications network final charge densities or currents estimated to exist on a subset of the cells of at least one discretized mesh.