Patent ID: 8234551

Claim:
An apparatus, comprising: an input to receive a plurality of coded blocks (CBs); a first layer cyclic redundancy check (CRC) encoding module to: jointly process the plurality of CBs using a generation polynomial to generate a first CRC field; and append the first CRC field to one of the plurality of CBs to generate a modified CB; a second layer CRC encoding module to: individually process each of the plurality of CBs, including the modified CB that includes the first CRC field, using the generation polynomial to generate a plurality of CRC fields such that each CRC field corresponds to one of the plurality of CBs, wherein the second layer CRC encoding module to begin processing at least some of the plurality of CBs before the first layer CRC encoding module generating the first CRC field; and append each respective CRC field of the plurality of CRC fields to its corresponding CB of the plurality of CBs to generate a plurality of CRC CBs; and an output to output the plurality of CRC CBs.