Patent ID: 7710376

Claim:
A display comprising: a plurality of pixels arranged in matrix; wherein each of the pixels has at least a first transistor, a second transistor, an image signal memory, an added capacitor, an electrooptical medium, and a common electrode; wherein each of the pixels is connected to at least a signal line, a scan line and a reference voltage line; wherein one of drain and source of the first transistor is connected to the signal line; wherein the other of drain and source of the first transistor is connected to a gate of the second transistor; wherein a gate of the first transistor is connected to the scan line; wherein one of drain and source of the second transistor is connected to the electrooptical medium; wherein the other of drain and source of the second transistor is connected to the reference voltage line; wherein the image signal memory is connected to a gate of the second transistor and the reference voltage line; wherein the added capacitor is connected to the gate of the second transistor and to one of drain and source of the second transistor; wherein the electrooptical medium is connected to one of drain and source of the second transistor and to the common electrode; and wherein a variation ΔV pxg of a pixel electrode voltage of the electrooptical medium connected to one of drain and source of the second transistor is expressed by the following equations (1) and (2): Δ ⁢ ⁢ V pxg = C gs ⁢ ⁢ 1 C gs ⁢ ⁢ 1 + C s + C pix + C opc ⁢ Δ ⁢ ⁢ V t ⁢ ⁢ 1 ⁢ g ( 1 ) wherein Δ ⁢ ⁢ V t ⁢ ⁢ 1 ⁢ g = C gs ⁢ ⁢ 1 C b ⁡ ( C opc + C pix + C s ) C b + C opc + C pix + C s + C m + C gs ⁢ ⁢ 1 ⁢ ( V GH - V GL ) ( 2 ) wherein C gs1 represents a parasitic capacitance, C s represents a holding capacitance, C pix represents a capacitance of the electrooptical medium, C opc represents a pixel electrode parasitic capacitance, C m represents a capacitance of the image signal memory, C b represents an added capacitance, and V GH and V GL represent a gate voltage of the first transistor.