Patent ID: 8664978

Claim:
A method, comprising: coupling a known signal to an impedance through a first logic element; observing a first current through the impedance for a number of cycles to establish a first average current corresponding to a time related parameter of the known signal; inverting a first clock signal to generate an inverted first clock signal; delaying the first clock signal to generate a delayed first clock signal, the delay of the delayed first clock signal corresponding to a delay created by inverting the first clock signal; generating a delayed signal by passing the inverted first clock signal through a device under test; generating an unknown periodic signal by logically combining the delayed signal with the delayed first clock signal, the unknown periodic signal having a logical “on” state indicating a non-overlapping time of the delayed signal compared to the delayed first clock signal; coupling the unknown periodic signal to the impedance through the first logic element, the first logic element selectively providing the unknown periodic signal or the known signal to the impedance; observing a second current through the impedance for a number of cycles to establish a second average current corresponding to a time related parameter of the unknown periodic signal; and determining a timing characteristic of the unknown signal by comparing the first and second currents, the timing characteristic being determined independent of the physical value of the impedance.