Patent ID: 6842429

Claim:
A digital signal processor comprising: a transmit path packet assembler for packetizing digitized data from a plurality of communication channels into corresponding transmit packets, and for injecting transmit control parameters into a transmit path via selected ones of the transmit packets to control the modulation of a corresponding communication channel; a receive path packet assembler for packetizing digitized data from the plurality of communication channels into corresponding receive packets, and for injecting receive control parameters into a receive path via selected ones of the receive packets to control the demodulation of the corresponding communication channel; and a plurality of modulation and demodulation modules configured to form at least a portion of the transmit path and at least a portion of a receive path for the modulation and demodulation of the transmit and receive packets respectively, and with selected ones of the modules responsive to the control parameters injected by at least one of the transmit path packet assembler and the receive path packet assembler to vary a processing of the corresponding communication channel.