Patent ID: 7371630

Claim:
A method comprising: forming a pattern over a first surface of a substrate, the substrate having a PMOS transistor region and an NMOS transistor region on a second surface, the pattern covering at least a portion of the first surface opposite the NMOS transistor region and exposing at least a portion of the first surface opposite the PMOS transistor region; inducing a stress in the PMOS transistor region by implanting Germanium in the exposed portion of the first surface opposite the PMOS transistor region; forming a second pattern over the first surface of the substrate, wherein the second pattern covers at least a portion of the first surface opposite the PMOS transistor region and exposes at least a portion of the first surface opposite the NMOS transistor region; and inducing a second stress in the NMOS transistor region by forming a nitride layer on the exposed portion of the first surface opposite the NMOS transistor region.