Patent ID: 7216322

Claim:
A method of clock tree synthesis for low power consumption and low clock skew, comprising: inputting a clock tree synthesis netlist including electric parameter data of each path of a clock tree, timing of each buffer and a power database; inputting timing standard maximum of clock skew; determining characteristics of each buffer according to a design standard via a design standard validator that calculates a timing delay of an input signal inputting from a root of the clock tree to each buffer, transfer time of a flip-flop and output load of each buffer; balancing clock tree load, and solving conditions of departing from a specific database design standard and clock tree skew greater than that of the specific database design standard; changing buffer type based on the power database for quickly searching a feasible solution for reducing power consumption of the clock tree; and using heuristic of the specific database design standard and processes of optimum based on a simulating annealing method for searching an interconnect scheme of buffers on the clock tree to gain an optimization solution of the power consumption of the clock tree in all areas.