Patent ID: 7917886

Claim:
An automatic system for providing printed circuit board (PCB) layout of a PCB to be designed to allow a high-speed signal to be transmitted through, the system comprising: an input device to receive input information of the PCB to be designed; a storage device storing a name and a thickness of each layer of each of a plurality of PCBs; and a data processing device comprising: an invoking module to read the name and thickness of each layer of the PCB to be designed from the storage device, according to the input information from the input device; a calculating module to calculate an actual length of a via stub of each layer of the PCB to be designed, according to the name and thickness of each layer of the PCB to be designed stored in the storage device, and to calculate an ideal length L MAX of the via stub of the PCB according to the input information and a preset formula L MAX = 0.59055 ɛ r × B ⁢ ⁢ R for reducing resonance reflection of the high-speed signal, wherein ε r is relative permittivity of the PCB, and BR is a transmission bit rate of the high-speed signal transmitted in the PCB, the actual length of the via stub of each layer equals the thickness of the PCB minus the thicknesses of high-speed signal layout layers through which the high-speed signal is transmitted of the PCB combined; and a determining module to set an initial layer as a current layer and determine whether a number assigned to represent the next layer to be checked is less than or equal to the number of total layers of the PCB, and compare the ideal length and the actual length of the via stub of each layer in response to that the assigned number being less than or equal the number of total layers of the PCB, wherein a layer can be used as a high-speed signal layout layer in response to the actual length of the via stub of the layer being less than or equal to the ideal length of the via stub of the PCB, while a layer cannot be used as a high-speed signal layout layer in response to the actual length of the via stub of the layer is greater than the ideal length of the via stub of the PCB; and the determining module to increment the assigned number by one in response to that the current layer cannot be used as a high-speed signal layout layer.