Patent ID: 7667502

Claim:
A Low Voltage Differential Signalling (LVDS) driver arranged to receive an input signal which switches between 1 and 0 voltage levels, the driver comprising: a pre-emphasis block for generating a pre-emphasis signal, the pre-emphasis signal having a first voltage level for a time period T 1 after each switch of the input signal from 1 to 0 or from 0 to 1, and a second voltage level at all other times; a differential pair of outputs for generating a differential output voltage across a load resistor; a driver circuit comprising two parallel branches, each branch being connected to one output of the differential pair of outputs and each branch being arranged to receive the pre-emphasis signal, wherein the LVDS driver is arranged such that the total current flowing through the driver circuit is constant, and during time period T 1 , the total current flowing through the driver circuit flows through the load resistor, thereby producing the differential output voltage across the differential pair of outputs, and at all other times, only some of the total current flowing through the driver circuit flows through the load resistor, thereby reducing the differential output voltage across the differential pair of outputs.