Patent ID: 7642164

Claim:
A method for providing self aligned contacts in an integrated MOSFET arrangement that includes an active area and a gate bus area comprising: providing a semiconductor substrate having a first surface and forming a plurality of semiconductor devices that are accessible at said first surface of said semiconductor substrate; forming contact windows in said substrate; forming a mask of silicon nitride on said substrate; forming polysilicon material on a surface of said mask of silicon nitride that forms a polysilicon plug in said gate bus area; forming an insulator on said mask of silicon nitride; forming a gate bus in said gate bus area; creating oxide spacers along walls of said contact windows formed in said substrate and etching said first surface of said substrate surface to form a contact trench in a RIE operation; and forming a contact implant at the bottom of said contact trench to increase the dopant concentration in a body well at a contact interface, wherein source regions of said integrated MOSFET arrangement are contacted along side walls of said contact trench.