Patent ID: 7957692

Claim:
An improved signal receiver circuit comprising: a first signal pathway comprising: a first polarity signal input of a low-noise block feedhorn, said first polarity signal input configured for receiving a first polarity signal, said first polarity signal being in a frequency range between 11.7 gigahertz (GHz) and 12.2 GHz; a first amplifier stage configured for pre-amplifying said first polarity signal to achieve an amplified first polarity signal; a 10.75 GHz local oscillator coupled with said first amplifier stage, said 10.75 GHz local oscillator configured for receiving said amplified first polarity signal and converting it to a second signal with a frequency range between 950 and 1450 megahertz (MHz); a first intermediate frequency amplifier coupled with said 10.75 GHz local oscillator, said first intermediate frequency amplifier configured for receiving said second signal; and a ceramic low-pass filter coupled with said first intermediate frequency amplifier; and a second signal pathway comprising: a second polarity signal input of a low-noise block feedhorn, said second polarity signal input configured for receiving a second polarity signal, said second polarity signal being in a frequency range between 11.7 GHz and 12.2 GHz; a second amplifier stage configured for pre-amplifying said second polarity signal to achieve an amplified second polarity signal; a 10.10 GHz local oscillator coupled with said second amplifier stage, said 10.10 GHz local oscillator configured for receiving said amplified second polarity signal and converting it to a third signal with a frequency range between 1600 and 2100 MHz; a second intermediate frequency amplifier coupled with said 10.10 GHz local oscillator, said second intermediate frequency amplifier configured for receiving said third signal; and a ceramic high-pass filter coupled with said second intermediate frequency amplifier.