Patent ID: 8261436

Claim:
A fabricating process of a circuit substrate, comprising: providing a base layer, a patterned conductive layer, and a dielectric layer, wherein the patterned conductive layer is disposed on the base layer and has an inner pad, and the dielectric layer is disposed on the base layer and covers the patterned conductive layer; forming a patterned metal mask on the dielectric layer, wherein the patterned metal mask has a first opening exposing a portion of the dielectric layer; removing the portion of the dielectric layer exposed by the first opening to form a dielectric opening, wherein the dielectric opening exposes the inner pad; forming a first patterned mask on the patterned metal mask, wherein the first patterned mask has a second opening exposing the inner pad; forming a conductive structure covering the inner pad, wherein the conductive structure comprises a conductive block, an outer pad, and a first metal layer, the conductive block fills the dielectric opening, the outer pad fills the first opening, and the first metal layer fills the second opening; and removing the first patterned mask, the first metal layer, and the patterned metal mask.