Patent ID: 6890820

Claim:
A method of fabricating a FLASH memory device comprising: forming trench device isolation layers on a substrate for defining a plurality of parallel first active regions, and forming a stack on the first active regions comprising a gate insulation pattern, a conductive pattern, and a hard mask pattern, wherein the stack comprises sidewalls aligned to sidewalls of the trench device isolation layers; removing the hard mask pattern at regular intervals along each of the first active regions for exposing a top of the conductive pattern; forming an oxide pattern on the top of the conductive pattern; removing the hard mask pattern; etching the conductive pattern using the oxide pattern as an etch mask for forming floating gate patterns disposed on each of the first active regions at regular intervals; forming tunnel oxide layers on sidewalls of the floating gate patterns; and forming a plurality of parallel control gate electrodes disposed on the floating gate patterns, crossing over the first active regions.