Patent ID: 8108628

Claim:
A method comprising: fetching an instruction that comprises: a first set of one or more bits identifying the instruction; and a second set of one or more bits associated with a first address value; executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test; wherein: the second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry whose location within the matrix is determined using bits that are included in the instruction as indices into the matrix.