Patent ID: 7761827

Claim:
A method, comprising: identifying at least one condition where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element, by a processor; and disabling at least one second logic element based on the identified condition, utilizing an integrated circuit; wherein the at least one condition includes an observability based clock gating condition, the observability based clock gating condition including the first input of the first logic element not being observable at the output of the first logic element based on the first input of the first logic element not being allowed to pass through the first logic element; wherein the at least one condition includes a state where the output of the first logic element is not a function of the first input of the first logic element during a first clock cycle and a number of subsequent clock cycles, due to the second input of the first logic element during the first clock cycle and the same number of subsequent clock cycles, and the at least one second logic element is disabled during at least the first clock cycle.