Patent ID: 7958470

Claim:
A computer implemented method of performing automated false path analysis for an electronic circuit design, comprising: using a processor configured for: receiving a list of one or more critical paths for the electronic circuit design; and using both implementation-specific design data and non-implementation-specific design data about the circuit design to identify one or more false paths within the list of critical paths, wherein the implementation-specific design data comprise information or data for the electronic circuit design at a first level of abstraction that comprises a gate level of abstraction, and the non-implementation-specific design data comprise information or data for the electronic circuit design at a second level of abstraction, which comprises an RTL level of abstraction, of the electronic circuit design, and the act of using both the implementation-specific design data and the non-implementation-specific design data about the circuit design to identify the one or more false paths comprises mapping the information or data between the first level of abstraction and the second level of abstraction of the electronic circuit design; and using a display apparatus configured for displaying information of the one or more false paths or using a computer readable storage medium or a computer storage device for storing the information.