Patent ID: 7279397

Claim:
A method of forming an isolation structure, comprising: forming a hard mask layer over isolation and active regions of a semiconductor body, the hard mask layer being separate from a pad oxide layer; forming a patterned resist mask over the hard mask layer, the patterned resist mask having an opening exposing a portion of the hard mask layer above the isolation region selectively providing a dopant to a portion of the active region proximate the isolation region by implanting the dopant through said opening in said patterned resist mask to create a threshold voltage compensation region; patterning the hard mask layer by etching an exposed portion of the hard mask layer through the opening of patterned resist, thereby creating the pattenerned hard mask having an opening that exposes a portion of the semiconductor body in the isolation region after creating the threshold voltage compensation region; forming a trench in the isolation region near the threshold voltage compensation region after creating the patterned hard mask; and filling the trench with a dielectric material by depositing an oxide material in the trench, and planarizing the oxide material to form an isolation structure using the hard mask as a planarization stop.