Patent ID: 8659322

Claim:
An integrated circuit comprising: a memory cell; and a sense amplifier coupled to the memory cell via a first and second bit line, comprising: a first inverter responsive to a first data signal provided by the memory cell over the first bit line, a second inverter responsive to a second data signal provided by the memory cell over the second bit line, wherein the second inverter is cross-coupled to the first inverter, a first negative bias temperature instability (NBTI) compensation transistor comprising a source electrode coupled to a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to one of the first or second data signals, a second NBTI compensation transistor comprising a source electrode coupled to the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to one of the first or second data signals, wherein the second data signal is a logical complement of the first data signal, and an equilibrium transistor comprising a first source/drain electrode coupled to the drain electrode of the first NBTI compensation transistor and the source electrode of the first inverter, a second source/drain electrode coupled to the drain electrode of the second NBTI compensation transistor and the source electrode of the second inverter, and a gate electrode coupled to receive an enable signal.