Patent ID: 8110924

Claim:
A semiconductor device comprising: a semiconductor substrate; a multilayer wiring layer provided on the semiconductor substrate and constituting, in combination with the semiconductor substrate, an output circuit including a first transistor and a second transistor and a control circuit configured to control a gate potential of the first transistor and a gate potential of the second transistor; a sealing resin layer covering the multilayer wiring layer; a first connecting member connected to one end of the first transistor; a second connecting member connected to another end of the first transistor and one end of the second transistor; a third connecting member connected to another end of the second transistor; and a fourth connecting member connected to a terminal of the control circuit, each of the first to fourth connecting members being connected to an uppermost wiring of the multilayer wiring layer, penetrating through the sealing resin layer, and having an upper end portion protruding from an upper surface of the sealing resin layer, and horizontal cross-sectional area of the first to third connecting members being larger than horizontal cross-sectional area of the fourth connecting member.