Patent ID: 8527708

Claim:
A cache memory, comprising: a data array that stores memory blocks; a directory of contents of the data array; and a cache controller that controls access to the data array, the cache controller including an address conflict detection system including a set-associative array configured to store at least tags of memory addresses of in-flight memory access transactions, wherein the set-associative array includes a plurality of sets each including multiple ways that store at least tags of memory addresses of in-flight memory access transactions; wherein the address conflict detection system accesses the set-associative array to detect if a target address of an incoming memory access transaction conflicts with that of an in-flight memory access transaction and determines whether to allow the incoming memory access transaction to proceed based upon the detection; wherein the address conflict detection system allocates a way to the incoming memory access transaction within a set of the set-associative array determined by an index field of the target address if an address conflict is not detected.