Patent ID: 8530298

Claim:
A method of forming an integrated circuit (IC), comprising: providing a substrate having a topside semiconductor surface, wherein said topside semiconductor surface includes both N+ buried layer regions and P+ buried layer regions positioned lateral to one another; growing an epitaxial layer on said topside semiconductor surface; forming pwells in said epitaxial layer; forming nwells in said epitaxial layer; forming NMOS devices in and over said pwells, forming PMOS devices in and over said nwells; wherein over said P+ buried layer regions a first portion of said pwells provide twin-well instances of said NMOS devices and a first portion of said nwells provide twin-well instances of said PMOS devices, further comprising forming a deep nwell (DNWell) in said epitaxial layer over said N+ buried layer regions, and forming Nwell sinkers that frame an outer edge of said DNWells which extend vertically from said DNWells to a top surface of said epitaxial layer, wherein over said DNWells a second portion of said pwells provide triple-well instances of said NMOS devices and a second portion of said nwells provide triple-well instances of said PMOS devices.