Patent ID: 7210084

Claim:
A built-in, on-chip test system for testing a memory array for array and tag data, and ABIST error detection, comprising: a first subsystem circuit for logically bit-wise ANDing corresponding memory array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches; a second subsystem circuit for further receiving ABIST control logic as an input to either: a. combine array valid bits and tag valid inputs to produce valid output, or b. compare array valid bits with tag valid inputs; and a logical NOR for outputs of the first and second subsystem circuits, said system implementing an n-bit compare and an x-bit logic function for a SRAM memory directory macro, the where ABIST control logic changes the logic for ABIST error detection.