Patent ID: 8193559

Claim:
A semiconductor device comprising: one semiconductor die having a first and a second side opposite each other, and comprising a first n-type channel trench FET and a second n-type channel trench FET; wherein a source of the first FET and a drain of the second FET are electrically coupled to at least one contact area at the first side of the one semiconductor die; wherein a drain of the first FET, a gate of the first FET, a source of the second FET and a gate of the second FET are electrically coupled to contact areas at the second side of the one semiconductor die; wherein the contact areas of the drain of the first FET, of the gate of the first FET, of the source of the second FET and of the gate of the second FET are electrically separated from each other; wherein each of the first FET and the second FET includes p-type body regions being part of a p-type epitaxial layer formed above an n-type semiconductor substrate of the one semiconductor die; wherein the one semiconductor die comprises a stack of the n-type semiconductor substrate, a first n-type epitaxial layer on the n-type semiconductor substrate and the p-type epitaxial layer on the first n-type epitaxial layer, the semiconductor device further comprising: conductive plugs extending through the first n-type epitaxial layer in an area of the first FET, wherein one end of the conductive plugs is in contact with the p-type body regions of the first FET and the other end of the conductive plugs is in contact with the n-type semiconductor substrate, respectively.