Patent ID: 7657808

Claim:
A test circuit comprising: A. a tap controller having a test clock input lead, a test mode select input lead, and state output leads; B. an instruction register having a test data input lead, a test data output lead, a mode output lead and control bus output leads; C. boundary scan circuitry having a test data input lead and a mode input lead connected to the respective instruction register test data input and mode output leads, having state input leads connected to the state output leads of the tap controller, and having a state clock input lead; and D. capture test strobe circuitry including a gate having a first input coupled to the test clock input lead through delay circuitry, a second input connected to a capture test scan enable lead of the control bus output leads, a third input connected to an UpdateDR lead of the state output leads, and a capture test strobe output lead coupled to the state clock input lead of the boundary scan circuitry.