Patent ID: 7793172

Claim:
A method for controlling a power supply voltage for a memory array comprising addressable units, the method comprising: detecting whether an error occurred in performing a read operation on at least one addressable unit of the memory array using a first power supply voltage coupled to at least one portion of the memory array and to a processor, wherein the first power supply voltage is generated by a core voltage generator; if an error is detected, then incrementing an error counter for tracking an error count associated with the at least one portion of the memory array; switching the at least one portion of the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the at least one portion of the memory array; continuing operation of the memory using the second power voltage independent of the error counter; and based on at least one condition independent of the error counter, switching the at least one portion of the memory array to the first power supply voltage and resetting the error counter to an initial value.