Patent ID: 8239695

Claim:
An information processing device comprising: a first processor core; a second processor core; and a bus connected to both the first processor core and the second processor core, wherein the first processor core includes a first arithmetic section for performing arithmetic operation, the second processor core includes a second arithmetic section for performing arithmetic operation, a power supply with a higher voltage than a power supply with the highest voltage that is supplied to the first arithmetic section is supplied to the bus, and a power supply with a higher voltage than a power supply with the highest voltage that is supplied to the second arithmetic section is supplied to the same, a clock with a higher frequency than a clock with the highest frequency that is supplied to the first arithmetic section is supplied to the bus, and a clock with a higher frequency than a clock with the highest frequency that is supplied to the second arithmetic section is supplied to the same, the first processor core further includes a first interface section for performing input and output of data between the bus and the first arithmetic section, the second processor core further includes a second interface section for performing input and output of data between the bus and the second arithmetic section, a first power supply and a first clock are supplied to the first arithmetic section, a second power supply and a second clock are supplied to the second arithmetic section, a third power supply with a higher voltage than those of the first power supply and the second power supply is supplied to the bus, and a third clock with a higher frequency than those of the first clock and the second clock is supplied to the same, the first power supply and the third power supply are supplied to the first interface section, and the first clock and the third clock are supplied to the same, and the second power supply and the third power supply are supplied to the second interface section, and the second clock and the third clock are supplied to the same.