Patent ID: 7894261

Claim:
A non-volatile memory integrated circuit comprising a plurality of memory cells, each memory cell comprising: a first MOS transistor; a first control capacitor; a first floating gate coupled to the first MOS transistor and the first control capacitor; a first read/write control signal having at least a first state and a second state coupled to the first MOS transistor such that when the control signal is in the first state, the memory cell is configured for readout, and when the control signal is in the second state, the memory cell is configured for writing; a second MOS transistor; a second control capacitor; and a second floating gate coupled to the second MOS transistor and the second control capacitor; wherein the first read/write control signal having at least a first state and a second state is coupled to both the first MOS transistor and the second MOS transistor such that when the control signal is in the first state, the memory cell is configured for readout, and when the control signal is in the second state, the memory cell is configured for writing, and, wherein a memory cell comprises no more than three wells, the first floating gate being formed in a first well, the second floating gate being formed in a second well, and the first and second MOS transistors being formed in a third well.