Patent ID: 7380161

Claim:
A system, comprising: a first processor; a plurality of memory buffers coupled to said first processor via n signal lines and m spare lines, wherein said plurality of memory buffers are coupled to one another via said n signal lines and said m spare lines, wherein each of said plurality of memory buffers is coupled to particular banks of a system memory, wherein each of said plurality of memory buffers comprises: an error correction code check unit configured to determine if one of said n signal lines is in error; wherein said first processor comprises said error correction code check unit; and a service processor coupled to said first processor and to said plurality of memory buffers, wherein said service processor comprises: a memory unit operable to store a computer program for switching a defective signal line with a spare signal line without shutting down said system; and a second processor coupled to said memory unit, wherein said second processor, responsive to said computer program, comprises: circuitry for monitoring outputs of said plurality of error correction code check units; circuitry for detecting a defective signal line in said n signal lines if said defective signal line has an error rate that exceeds a threshold; and circuitry for configuring switch control units in a driver/receiver pair associated with said defective signal line to execute a switching of said defective signal line with an indicated spare signal line, wherein said switch control units are configured to control switch units configured to determine which signal line to transmit and receive incoming data.