Patent ID: 8352774

Claim:
An inter-clock domain data transfer FIFO circuit, comprising: a globally asynchronous, locally synchronous system (GALS) having a scalable interconnect architecture between system on a chip (SoC) intellectual property modules (IPs); means for routing data between the SoC IPs over shared interconnect portions of the scalable interconnect architecture; means for transfer of data between IPs having disparate clock domains; and a plurality of data transfer FIFOs disposed within a polysynchronous system-on-chip (SoC); wherein the circuit comprises a plurality of two-stage asynchronous pipeline circuits, each of the two-stage asynchronous pipeline circuits having: a NoC-side controller operably connected to a first latch; a client-side controller operably connected to a second latch; a NoC-to-client synchronizer disposed between the NoC-side and client-side controllers; a client-to-NoC synchronizer disposed between the NoC-side and client-side controllers; and a data transfer pipe between the first and second latches, the data transfer pipe transferring data from the client to the NoC, wherein the NoC side controller has a TAKE input accepting signals from the NoC, an OK to TAKE output sending a signal to the NoC, a TAKE ACKNOWLEDGE output sending a signal to a left transfer synchronizer, the left transfer synchronizer having a PUT ACKNOWLEDGE output sending a signal to the client-side controller, the client-side controller having an OK to PUT output sending a signal to the client and a PUT input accepting a signal from the client, the client-side controller having a Req Out output sending a signal to the left transfer synchronizer, the left transfer synchronizer having a PUT Req output sending a signal to the NoC-side controller, the first and second latches having enable inputs accepting EN NoC and EN C (client) outputs from the NoC-side controller and the client-side controller, respectively.