Patent ID: 7005709

Claim:
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein: said basic cells comprise first, second, third, fourth and fifth P-channel MOS transistors, and first and second N-channel MOS transistors; said second and third P-channel MOS transistors and said first P-channel MOS transistor are juxtaposed; said fifth P-channel MOS transistor and said fourth P-channel MOS transistor are juxtaposed; said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed; the gates of each of said transistors are parallel; the gate of said first P-channel MOS transistor and the gate of said fourth P-channel MOS transistor are connected in a line; the gate of said second P-channel MOS transistor and the gate of said third P-channel MOS transistor and the gate of said fifth P-channel MOS transistor are connected in a line; the gate of said fourth P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line; the gate of said fifth P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line; and, the gate width W 1 of the gate of said first P-channel MOS transistor, the gate width W 2 of the gate of said second P-channel MOS transistor, the gate width W 3 of the gate of said third P-channel MOS transistor, the gate width W 4 of the gate of said fourth P-channel MOS transistor, the gate width W 5 of the gate of said fifth P-channel MOS transistor, the gate width W 6 of the gate of said first N-channel MOS transistor, and the gate width W 7 of the gate of said second N-channel MOS transistor, are selected such that W 1 :W 2 :W 3 :W 4 :W 5 :W 6 :W 7 =1:⅓:⅓:1:1:1:1.