Patent ID: 7940582

Claim:
An integrated circuit comprising: an array of memory cells; volatile storage configured to store identified addresses of defective memory cells, wherein each entry in the volatile storage includes one of the identified addresses and a volatile storage master bit; non-volatile storage configured to store the identified addresses, wherein each entry in the non-volatile storage includes one of the identified addresses and a non-volatile storage master bit; and a circuit configured to detect defective memory cells in the array of memory cells and provide captured addresses of detected defective memory cells, wherein the circuit retrieves the identified addresses from the volatile storage and compares each captured address of the captured addresses to retrieved identified addresses, and the circuit does not store a compared captured address into the volatile storage if the compared captured address matches one of the retrieved identified addresses and the circuit stores the compared captured address into the volatile storage if the compared captured address does not match one of the retrieved identified addresses, and each stored compared captured address in the volatile storage is stored into the non-volatile storage.