Patent ID: 6876565

Claim:
A semiconductor memory device comprising: a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first plugs each formed on one of the first connection lines; a plurality of second plugs each formed on one of the second connection lines; a plurality of first metal wiring lines connecting to the first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, and a product of a wiring capacitance between adjacent two of the first metal wiring lines and a wiring resistance of the first metal wiring lines being substantially the same as a product of those of the second metal wiring lines.