Patent ID: 7790516

Claim:
A method of manufacturing at least one semiconductor component, the method comprising: forming a layer structure on or above a semiconductor substrate, the semiconductor substrate comprising a first substrate region and a second substrate region wherein a gate isolation layer is formed on or above the substrate; the first substrate region is provided for manufacturing non-memory semiconductor components; the second substrate region is provided for manufacturing memory semiconductor components; patterning the layer structure, thereby exposing at least one region of the semiconductor substrate to be doped; forming a doped region by doping the exposed at least one region of the semiconductor substrate to be doped; annealing the doped region; at least partially removing the patterned layer structure only in the second substrate region, wherein the remaining patterned layer structure in the first substrate region forms the non-memory semiconductor components; forming a charge storage layer structure on or above the gate isolation layer in the second substrate region, in which the patterned layer structure has been removed, thereby forming at least one NAND-coupled semiconductor component.