Patent ID: 8745287

Claim:
A data transfer apparatus comprising: a virtual channel unit configured to time share a serial bus for a first virtual channel and a second virtual channel and include a buffering control unit configured to receive data via the first virtual channel and the second virtual channel, a first receive buffer configured to store the data received via the first virtual channel, and a second receive buffer configured to store the data received via the second virtual channel; a switching unit configured to control storing of the data received via the first virtual channel in the second receive buffer when the buffering control unit receives the data from another data transfer apparatus which is configured to use only the first virtual channel and the capacity of the first receive buffer provided to store the data is smaller than the capacity of the second receive buffer provided to store the data; and a clock generating unit that generates a clock signal to be supplied to the first receive buffer and the second receive buffer, and wherein the switching unit is configured to block supplying of the clock signal to the first receive buffer when controlling storing of the data received via the first virtual channel in the second receive buffer.