Patent ID: 7464283

Claim:
A precision timing system, comprising: a first register bank, driven by a first clock signal, that provides a first delay along a first signal path; a second register bank, driven by a second clock signal related to the first clock signal, that provides a second delay along a second signal path; and a system control that controls at least one of the first and second banks of registers to control the first and second delays, as to provide a desired skew between the output of the first signal path and the second signal path; wherein the first clock signal and the second clock signal having substantially the same frequency, and the second clock signal being phase shifted relative to the first clock signal to provide a fine range of delay to the system and further comprising: a third register bank, driven by a third clock signal, that provides a third delay along the first signal path for enabling the first delay by the first register bank, the third delay providing a coarser range of delay than the first delay; and a fourth register bank, driven by the third clock signal, that provides a fourth delay along the second signal path for enabling the second delay by the second register bank, the fourth delay providing a coarser range of delay than the second delay.