Patent ID: 7782102

Claim:
A power-on reset circuit connected between an external DC power source and at least one functional chip for generating reset signals, the power-on reset circuit comprising: a delay circuit, comprising: a first delay unit used for delaying a first power signal received from the external DC power source to output a first delaying reference signal according to the first power signal, the first delay unit comprising a first capacitor and a first resistor connected in series between the external DC power source and ground; and a second delay unit used for delaying a second power signal received from the external DC power source to output a second delaying reference signal according to the second power signal, the second delay unit comprising a second capacitor and a second resistor connected in series between the external DC power source and ground; a rectifying circuit connected to the delay circuit, comprising: a first rectifying unit connected to the first delay unit for rectifying the first delaying reference signal to output a first rectified signal; a second rectifying unit connected to the second delay unit for rectifying the second delaying reference signal to output a second rectified signal; and a logic operation circuit connected to the rectifying circuit used for outputting a reset signal according to the first rectified signal and the second rectified signal.