Patent ID: 7028281

Claim:
A field programmable gate array (FPGA) comprising: (a) a plurality of substantially same logic blocks each having plural programmable lookup tables; (b) for each of said lookup tables, at least two corresponding state-storing registers; (c) within each logic block and for each of said lookup tables of the logic block, an internal-routing circuit that is programmable to route a result signal of the respective lookup table as a register input signal to at least one of the corresponding state-storing registers so that each of the state-storing registers can output a register-output signal that defines a registered or latched version of the register-input signal; and (c1) a programmable input switch adapted to acquire a multi-bit dynamic write-enable steering signal for dynamically steering a write enable signal to a single-port or multi-port memory array overlapping with two or more of the lookup tables of the corresponding logic block.