Patent ID: 8907470

Claim:
A wafer level chip scale package (WLCSP) structure comprising: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane, wherein the signal trace connection electrically isolated from the PCB ground plane includes a conductive strip which forms a microstrip line with the PCB ground plane for carrying a signal; a signal ball contacting the signal trace connection, wherein a diameter of the signal ball controls an amount of signal loss in the WLCSP structure; a chip pad contacting the signal ball; and a signal trace connection on a chip contacting the chip pad.