Patent ID: 6933217

Claim:
A method for manufacturing a semiconductor device comprises: depositing a gate oxidation layer on a semiconductor substrate having a lower construction; forming a first contact hole for connecting elements electrically, by a wet etching of an area to be used as a ROM coding area on the gate oxidation layer; depositing a doped poly-silicon layer on a result formed with the first contact hole; forming a gate electrode and a first conductive line by patterning a part of poly-silicon layer to be used as a conductive line; performing an ion implantation of low-density impurities connecting a source/drain area whereby the source/drain impurity areas are formed on both sides of the gate electrode on the semiconductor substrate; depositing a nitride layer on an entire surface of the semiconductor substrate and forming nitride spacers at both sides of the gate electrode by etching the nitride layer; making a part for ROM coding on a result formed with the nitride spacer, and performing an ion implantation of high density impurities on an area other than a ROM coding transistor; depositing a PMD layer on the resulting structure and forming a second contact hole by a photolithography process; forming a resist pattern on the result formed with the second contact hole, and forming a ROM coding by ion implantation by using the resist pattern as a mask; and depositing a metal to be used as a metal line on the result, and forming a second metal line by patterning through a photolithography process.