Patent ID: 7623405

Claim:
A circuit, comprising: a memory cell having a high voltage supply node and a low voltage supply node; first power supply multiplexing circuitry having a first input for receiving a first high supply voltage and a second input for receiving a second high supply voltage that is less than the first high supply voltage, the first power supply multiplexing circuitry being responsive to a first control signal, wherein the first power supply multiplexing circuitry applies the first high supply voltage to the high voltage supply node if the first control signal has a first state, and applies the second high supply voltage to the high voltage supply node if the first control signal has a second state; second power supply multiplexing circuitry having a first input for receiving a first low supply voltage and a second input for receiving a second low supply voltage that is greater than the first low supply voltage, the second power supply multiplexing circuitry being responsive to a second control signal, wherein the second power supply multiplexing circuitry applies the first low supply voltage to the low voltage supply node if the second control signal has a first state, and applies the second low supply voltage to the low voltage supply node if the second control signal has a second state.