Patent ID: 7125771

Claim:
A method for fabricating a nonvolatile memory device comprising: sequentially forming a gate oxide layer, a polysilicon layer for first control gates, a buffer oxide layer, and a buffer nitride layer on a semiconductor substrate; patterning first control gates in the direction of a column by removing some portion of the buffer nitride layer, the buffer oxide layer, and the polysilicon layer for first control gates; depositing a polysilicon layer for sidewall floating gates over the semiconductor substrate including the first control gate; forming sidewall floating gates on the sidewalls of the first control gates by etching the polysilicon layer for sidewall floating gates; forming common source and drain regions in the semiconductor substrate; removing the sidewall floating gates formed between word lines by patterning the semiconductor substrate in the direction of a row; depositing and planarizing an insulating layer over the semiconductor substrate including the first control gates and the sidewall floating gates so as to fill the gap between the first control gates; removing the buffer nitride layer and the buffer oxide layer on the first control gates; depositing a polysilicon layer for second control gates over the semiconductor substrate including the first control gates and the insulating layer; forming stack gates by removing some portion of the first control gates and the polysilicon layer for second control gates in the direction of a word line, each stack gate comprising one first control gate and one second control gate; and forming sidewall spacers on the sidewalls of the stack gates.