Patent ID: 7064389

Claim:
A semiconductor device comprising: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a silicon layer formed on the insulating layer, the silicon layer having a first region and a second region, the first region of the silicon layer having a plurality of first element regions and the second region of the silicon layer having a plurality of second element regions; an element isolation layer formed on the silicon layer, the element isolation layer completely isolating the first element regions from each other and isolating the second element regions from each other only at a surface of the second region of the silicon layer, the element isolation layer additionally isolating the first region of the silicon layer from the second region of the silicon layer; a plurality of full depletion type transistors used for a first circuit each formed on the silicon layer at the first region; and a plurality of partial depletion type transistors used for a second circuit each formed on the silicon layer at the second region, the silicon layer in the second region being applied with a predetermined potential.