Patent ID: 8787568

Claim:
A cryptographic processing apparatus for performing an extended Feistel type common key blockcipher encrypting process, comprising: a processor, configured for: dividing a plain text data into a first plurality of data units, which are adjusted so that the number of bits of each of the first plurality of data units is equal to the number of bits of a round key input to an F-function, wherein the first plurality of data units includes more than two data units; and performing a plurality of rounds of processing to execute the F-function, wherein each round of processing includes: inputting the round key into at least one of the first plurality of data units to generate a first data unit; performing a non-linear transformation processing on the first data unit to generate a second data unit; and performing a linear transformation on the second data unit and performing a logic operation on a result of the linear transformation and another one of the first plurality of data units; wherein the non-linear transformation processing includes: dividing the first data unit into a second plurality of data units; and performing a plurality of small non-linear transformation processings on the second plurality of data units; wherein at least one of the plurality of small non-linear transformation processings includes: performing a first non-linear transformation processing on at least one of the second plurality of data units; performing a first linear transformation on an output of the first non-linear transformation processing; dividing output data from the first linear transformation into a third plurality of data units; and performing a second non-linear transformation processing on the third plurality of data units.