Patent ID: 8264473

Claim:
A timing controller which outputs, via a plurality of ports, video data and a reset signal for starting reading of the video data to a plurality of signal-line driving ICs having output terminals connected to signal lines, the timing controller comprising: a reset signal storage section which stores a plurality of reset signals including a normal reset signal and a specific reset signal; a reset signal setting section which sets one of the plurality of reset signals stored in the reset signal storage section for each of the plurality of ports in accordance with a signal from outside; and a reset signal synthesizing section which synthesizes the reset signals set by the reset signal setting section and the video data, and simultaneously outputs acquired data to the plurality of ports, respectively, in a case where: the plurality of signal-line driving ICs include a normal signal-line driving IC which has only a normal output terminal connected to the signal line and a specific signal-line driving IC which has a specific output terminal that is not connected to the signal line in addition to the normal output terminal; the plurality of ports include a port which does not include the specific signal-line driving IC as an output target, and a port which includes the specific signal-line driving IC as the output target; the reset signals include the normal reset signal that is used when starting reading from the video data corresponding to the normal output terminal, and the specific reset signal that is used when starting reading from the video data corresponding to the specific output terminal; and the specific reset signal is a signal which starts the reading earlier than the normal reset signal by an amount of time which corresponds to the reading of the video data corresponding to the specific output terminal.