Patent ID: 8645620

Claim:
An interfacing apparatus configured to couple a plurality of memory devices including a first memory device and a second memory device by means of an address space to a processing unit, the apparatus comprising: a first memory access unit being adapted for receiving a memory address corresponding to a first part of said address space in each of said first and second memory devices from said processing unit and for providing random access to a corresponding location in the first part of said address space based on the address provided; a second memory access unit being adapted for receiving content data from said processing unit and for controlling a search or update function accordingly for said received content data in a second part of said address space in each of said first and second memory devices; an allocation unit configured to parse memory addresses and then to allocate the first part of said address space in each said first and second memory devices to said first memory access unit and allocate the second part of said address space in each of said first and second memory devices to said second memory access unit; and said allocation unit having a plurality of address range registers provided for storing as boundary a border address of an address range of first and second address ranges corresponding to said first and second parts of said address space, respectively.