Patent ID: 7095809

Claim:
A demodulator for demodulating a set of S possible orthogonal modulation codes received serially as binary data, wherein each of said S possible orthogonal modulation codes comprises M binary bits representing an N-bit data symbol and wherein M =2 N , said demodulator comprising: a Logic 00 input detector, a Logic 01 input detector, a Logic 10 input detector and a Logic 11 input detector, wherein each of said Logic 00 input detector, said Logic 01 input detector, said Logic 10 input detector, and said Logic 11 input detector compares sequential pairs of said M binary bits of said serially received orthogonal modulation codes to a respective one of a Logic 00 value, a Logic 01 value, a Logic 10 value, and a Logic 11 value and outputs a [+1,+1] signal if a match occurs and outputs a [−1,−1] signal if a match does not occur; a summation circuit comprising S accumulators; a storage array capable of storing S Logic 00 code masks, each of said S Logic 00 code masks associated with one of said S possible orthogonal modulation codes, wherein a kth Logic 00 code mask comprises M/2 Logic 00 code mask bits, each of said M/2 Logic 00 code mask bits associated with a corresponding one of M/2 sequential pairs of M binary bits in a kth orthogonal modulation code, wherein said each M/2 Logic 00 code mask bit is a Logic 1 if said corresponding sequential pair of said M binary bits in said kth orthogonal modulation code is equal to a Logic 00 value and is equal to Logic 0 otherwise; and an input decision circuit capable of detecting a [+1,+1] signal output by said Logic 00 input detector after a comparison of a jth sequential pair of said M/2 sequential pairs of said M binary bits to a Logic 00 value and, in response to said detection, adding said [+1,+1] signal to a kth one of said S accumulators in said summation circuit if a jth one of said M/2 Logic 00 code mask bits in said kth Logic 00 code mask in said storage array is equal to Logic 1.