Patent ID: 8086832

Claim:
A design structure embodied in a machine readable, non-transitory storage medium used in a design process, the design structure comprising: a netlist describing a system for dynamically varying the pipeline depth of a computing device, depending upon at least one of computing function and workload, the system further comprising a state machine configured to determine an optimum length of a pipeline architecture based on a processing function to be performed; a pipeline sequence controller, responsive to the state machine, the pipeline sequence controller configured to vary the depth of the pipeline based on the determined optimum length; a plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, the clock splitter elements coupled to the pipeline sequence controller and adapted to, independently, from one another, operate in a functional mode, one or more clock gating modes, and a pass-through flush mode; wherein, for each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith; and wherein, for a given function type, the state machine, pipeline sequence controller and local clock splitter elements are further configured to, in cooperation with one another, dynamically increase the depth of the pipeline so as to add pipeline stages, thereby accommodating multiple repeating instances of the given function type in the event the function type is not already pipelined, and to dynamically reduce the depth of the pipeline so as to remove pipeline stages in the event the given function type is not being repeated, with a case of a single use function type versus a multiple repeating function type determined by a system compiler that looks ahead to an instruction stream and determine whether a function pipeline set is repeatedly or singly used.