Patent ID: 7098108

Claim:
A method for making a planar semiconductor device, comprising a semiconductor substrate having a first surface and second, opposite and planar surface and a lowered effective electrical resistivity, the method comprising: in the second, planar surface forming a highly doped drain region; in the first surface, forming one or more device active regions above the drain region, said device active regions comprising one or more wells of dopants of a second and opposite polarity and in said wells one or more source regions of dopants of a first polarity, the source regions laterally spaced from each other; forming gate regions over portions of the well regions between the source regions and the drain region; in the second, planar surface of the substrate after forming the highly doped drain region, forming one or more recesses extending from the second, planar surface of the substrate into interior portions of the semiconductor substrate, wherein said one or more recesses occur between planar regions of the second surface, forming resistivity-lowering bodies in said one or more recesses to fill the one or more recesses, the resistivity-lowering bodies comprising a material different than the semiconductor substrate and having an electrical resistivity lower than an electrical resistivity of the semiconductor substrate; and forming a planar electrical contact layer over said second planar surface of said substrate and in electrical contact with said one or more resistivity-lowering bodies.