Patent ID: 7919378

Claim:
A method of forming a transistor, the method comprising: integrally forming an active structure with a semiconductor substrate, the active structure comprising a central portion upwardly extending from the substrate, lateral portions horizontally extending from the central portion, and grooves formed at the lateral portions, the central portion serving as a channel region; forming an insulation layer on the substrate, the insulating layer exposing an upper face of the active structure; forming blocking regions in the grooves; partially etching the insulation layer to form an insulation layer pattern including trenches that partially expose side surfaces of the central portion of the active structure; forming a gate structure on the active structure and the insulation layer pattern, the gate structure crossing the upper face of the active structure and partially enclosing the active structure; and implanting first impurities into upper portions of the active structure to form source/drain regions adjacent to the gate structure.