Patent ID: 7400202

Claim:
A power amplification bias circuit comprising: an amplifying transistor having an emitter terminal, a base terminal, and a collector terminal; and a bias circuit for supplying a bias current to the base terminal of the amplifying transistor, the bias circuit including: a reference voltage input terminal through which a reference voltage is input from outside; a first transistor having an emitter terminal and which supplies a bias current according to the reference voltage to the base terminal of the amplifying transistor; first, second, and third resistors; a second transistor having a base terminal, an emitter terminal that is grounded, and a collector terminal that is connected to a connection point between the first transistor and the base terminal of the amplifying transistor via the first resistor; a third transistor having a base terminal connected to the reference voltage input terminal via the second resistor, the third transistor supplying a bias current according to the reference voltage to the base terminal of the second transistor; a fourth transistor having a base terminal connected to the emitter terminal of the first transistor, an emitter terminal that is grounded, and a collector terminal connected to the reference voltage input terminal via the third resistor; and a fourth resistor having a first terminal connected to the reference voltage input terminal and having a second terminal connected to the base terminal of the amplifying transistor, wherein a current is supplied from the reference voltage terminal to the base terminal of the amplifying transistor via the fourth resistor when the reference voltage is lower than a voltage at which the first transistor operates.