Patent ID: 6893921

Claim:
A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising: forming a first structure over a semiconductor substrate, the first structure comprising: a first conductive gate of a nonvolatile memory cell; and a first dielectric over the first conductive gate; forming a layer (“FG layer”) to provide a conductive floating gate for the memory cell, wherein the floating gate comprises a first portion and an upward protruding second portion, the second portion being formed over the first dielectric over at least a sidewall of the first conductive gate; forming a second dielectric over the FG layer; forming a layer G 2 over first structure, the FG layer, and the second dielectric, to provide a second conductive gate for the memory cell; removing a portion of the layer G 2 such that the top of the second conductive gate becomes not higher than the top of the floating gate.