Patent ID: 8742491

Claim:
A semiconductor device, comprising: a first and second fin on a substrate; an isolation structure interposing the first and second fin, and wherein the isolation structure abuts the lateral sides of each of the first and second fins adjacent the top surface of each of the first and second fins forming a planar surface, wherein the planar surface includes a top surface of the isolation structure and a top surface of the first and second fin; a gate structure disposed on the planar surface including the top surface of the isolation structure, the top surface of the first fin, and the top surface of the second fin; a source region disposed in a first recess of the isolation structure and on and around a first end of the first fin, wherein the source region includes an epitaxial grown region on the first end of the first fin; and a drain region disposed in a second recess of the isolation structure and on and around a second end of the first fin wherein the drain region includes an epitaxial grown region on the second end of the first fin.