Patent ID: 7662690

Claim:
A method of preparing a semiconductor substrate utilized to produce a CMOS chip whereon RF functions are integrated for system on chip applications, comprising: providing a semiconductor substrate having a resistivity of between about 20 ohm-cm and about 60 ohm-cm; forming an isolation region within the semiconductor substrate; performing a first blanket implant of p type dopant atoms into the isolation region and into first and second regions of the substrate on opposing sides of the isolation region without a mask covering the isolation region or the first and second regions of the substrate such that the p type dopant atoms are implanted under the isolation region to have a peak of a first depth that is less than a depth of the junction of subsequently formed nwell regions to mitigate leakage between at least some of the subsequently formed nwell regions; performing a second blanket implant of p type dopant atoms into the isolation region and into the first and second regions of the substrate without a mask covering the isolation region or the first and second regions of the substrate such that the p type dopant atoms are implanted under the isolation region to have a peak of a second depth that is greater than the depth of the junction of the subsequently formed nwell regions to mitigate leakage between at least some of the subsequently formed nwell regions; and performing a third implant of n type dopant atoms into the isolation region and into the first and second regions of the substrate without a mask covering the isolation region or the first and second regions of the substrate to form first and second nwell regions within the first and second regions of the substrate on opposing sides of the isolation region.