Patent ID: 7605065

Claim:
A method of manufacturing a Schottky barrier tunnel single electron transistor (SB-SET), the method comprising; (a) sequentially forming an insulating layer and a semiconductor layer on a substrate, wherein the semiconductor layer comprises an extremely low impurity concentration of less than 10 16 atoms/cm 3 ; (b) patterning the semiconductor layer to define a channel region and source and drain regions; (c) forming a gate insulating layer and a gate electrode on the channel region; (d) forming a sidewall insulating layer at both sidewalls of the gate insulating layer and the gate electrode; (e) forming and siliciding a metal material to a predetermined thickness on the entire surface of the resultant structure to form a resultant Schottky barrier between the source and drain regions wherein the forming and siliciding step is used instead of impurity injection to form the resultant Schottky barrier; (f) forming an interlayer insulating layer pattern on the silicided entire structure to expose a portion of the gate electrode and portions of the source and drain regions; and (g) forming a metal interconnection on the exposed gate electrode and source and drain regions.