Patent ID: 7399675

Claim:
A process for forming an electronic device, the process comprising: forming spaced-apart first insulating features over a substrate; forming a second insulating feature over the substrate and lying between the spaced-apart first insulating features, wherein a top surface of the second insulating feature lies at a lower elevation compared to a top surface of the spaced-apart first insulating features, wherein forming the second insulating feature comprises: depositing a first layer over the substrate including over and between the spaced-apart first insulating features; depositing a second layer over the first layer, wherein the second layer has a different composition compared to the first layer; removing portions of the second layer that overlie the spaced-apart first portions; and removing portions of the first layer to lower a top surface of the first layer below the top surface of the spaced-apart first insulating features; forming a charge storage stack overlying the second insulating feature and lying between the spaced-apart first insulating features; and forming a control gate electrode overlying the charge storage stack and the second insulating feature and lying between the spaced-apart first insulating features.