Patent ID: 7515499

Claim:
A semiconductor memory device comprising: a first memory cell array which includes a plurality of memory cells; a first decoder which selects a memory cell from the first memory cell array based on an address; a second memory cell array which includes a plurality of memory cells; a second decoder which selects a memory cell from the second memory cell array based on an address; a first sense amplifier which reads data from the memory cell selected by one of the first decoder and the second decoder; a first switch circuit which switches the supply of writing and erasing voltages or a reading voltage to the first memory cell array, the first switch circuit switching the supply of writing and erasing addresses or a reading address to the first decoder, and switching the connection of a data line connected to a bit line of the first memory cell array to the first sense amplifier; a second switch circuit which switches the supply of writing and erasing voltages or a reading voltage to the second memory cell array, the second switch circuit switching the supply of writing and erasing addresses or a reading address to the second decoder, and switching the connection of a data line connected to a bit line of the second memory cell array to the first sense amplifier; a plurality of third memory cell arrays each of which includes pluralities of word and bit lines, and a plurality of memory cells arranged in a matrix at intersections of the word and bit lines, the plurality of third memory cell arrays storing setting information to set an initial operation and a function when power is turned ON; a plurality of third decoders which select the memory cells from the plurality of third memory cell arrays based on a predetermined signal output when the power is turned ON; a second sense amplifier which reads the setting information from the memory cells selected by the plurality of third decoders; a third switch circuit which switches the supply of writing and erasing voltages or a reading voltage to one of the plurality of third memory cell arrays, the third switch circuit switching the supply of writing and erasing addresses or a reading address to one of the plurality of third decoders, and switching the connection of a data line connected to a bit line of one of the plurality of third memory cell arrays to the second sense amplifier; a latch circuit which stores the setting information read by the second sense amplifier; and a control circuit which sets the initial operation and the function in accordance with the setting information stored in the latch circuit.