Patent ID: 7285812

Claim:
A memory array comprising: a substrate having a plurality of ridges separating a plurality of trenches, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, and each trench extending from the bottom level to the shoulder; a bit line buried below the shoulder within each trench; a plurality of transistor pillars over each of the plurality of ridges, each transistor pillar extending upwardly from the shoulder of the ridge, wherein the transistor pillars include an upper active area; a plurality of lower active areas in the upper surface of each of the plurality of ridges, wherein one of the lower active areas is below each transistor pillar; a bit line link within each trench connecting each lower active area and the bit line; and a plurality of word lines, wherein each word line contacts a row of transistor pillars and crosses over at least two of the plurality of ridges.