Patent ID: 8653871

Claim:
A counter circuit comprising: a first pair of registers configured to swap contents when the counter circuit increments or decrements a counter value to a first update count, one of the first pair of registers storing the first update count; a second pair of registers configured to swap contents when the counter circuit increments or decrements the counter value to the first update count; a waveform generator configured to generate a composite signal, wherein the waveform generator is configured to cause the composite signal to invert when the counter circuit increments or decrements the counter value to the first update count, and wherein the waveform generator is configured to cause the composite signal to invert when the counter circuit increments or decrements the counter value to a first match count, one of the second pair of registers storing the first match count; and a demultiplexing circuit coupled to the waveform generator and configured to generate first and second signals from the composite signal.