Patent ID: 7957174

Claim:
A semiconductor memory comprising: first and second memory cell array areas having a memory cell; a word line driver arranged between the first and second memory cell array areas; a first word line contact area arranged between the first memory cell array area and the word line driver; a second word line contact area arranged between the second memory cell array area and the word line driver; a first word line arranged straddling the first memory cell array area and the first word line contact area; a second word line arranged straddling the second memory cell array area and the second word line contact area; a first contact hole provided on the first word line in the first word line contact area; and a second contact hole provided on the second word line in the second word line contact area, wherein a size of the first and second contact holes is larger than a width of the first and second word lines, and the lowest parts of the first and second contact holes exist at a position lower than top surfaces of the first and second word lines, and higher than bottom surfaces of the first and second word lines.