Patent ID: 7632689

Claim:
A method for controlling the profile of a trench of a semiconductor structure having a first dielectric layer, a first etch stop layer disposed on the first dielectric layer, a second dielectric layer disposed on the first etch stop layer, and a via formed at least through the second dielectric layer, the method comprising the steps of: depositing a photoresist within the via that overlies the second dielectric layer; depositing an image layer that overlies the photoresist and patterning the image layer to form a first trench within the image layer that overlies the via, wherein the first trench is defined at least partly by a first wall of the image layer disposed at a first angle, greater than about 90°, from a surface of the photoresist and a second wall of the image layer, wherein the first trench has a first width proximate to the photoresist and a second width remote from die photoresist, and wherein the first width and the second width of the first trench are not equal; dry etching the photoresist using dry etch parameters, at least one of which is selected based on the first angle and the first and the second widths of the first trench to form a second trench in the photoresist and to remove the photoresist from the via; and etching the second dielectric layer to form a third trench in the second dielectric layer.