Patent ID: 7974054

Claim:
An integrated circuit having an electrostatic discharge (ESD) protection circuit, comprising: a first power pad; a second power pad; at least one circuit module, comprising: a signal pad; an internal circuit, coupled between the first power pad and the second power pad; and a first bipolar transistor, having a base node coupled to the first power pad, and an emitter node coupled to the signal pad, wherein a first parasitic resistor is coupled between a collector node of the first bipolar transistor and the second power pad; and a power clamp circuit, coupled between the first power pad and the second power pad, the power clamp circuit comprising: at least a first metal oxide semiconductor transistor, having a control node coupled to the second power pad, a first connection node coupled to the first power pad, and a second connection node coupled to the second power pad; and at least a first parasitic bipolar transistor, having a collector node coupled to the first connection node of the first metal oxide semiconductor transistor, an emitter node coupled to the second connection node of the first metal oxide semiconductor transistor, and a base node coupled to the collector node of the first bipolar transistor and the first parasitic resistor.