Patent ID: 8885425

Claim:
A semiconductor memory comprising: a memory cell array including a main region and a redundancy region, the main region and the redundancy region including a plurality of memory cells arranged along a row direction and a column direction; a plurality of first control units configured to assign to a column of the main region; a plurality of second control units configured to assign to a column of the redundancy region; a column control circuit configured to sequentially select the first control units by using a first pointer corresponding to an address signal, and select the second control unit by using a second pointer when defect address information of the main region matches the address signal so that one of the first control units corresponding to the defect address information is replaced with one of the second control units; and a selection circuit configured to connect either one of a first data bus provided for the main region and a second data bus provided for the redundancy region to a third data bus provided for data transmission between the memory cell array and an outside of the memory cell array, based on a comparison result between the address signal and the defect address information.