Patent ID: 7280398

Claim:
A flash memory receiving control signals, and command and address signals, the flash memory comprising: an array of flash memory cells having a plurality of memory planes; a state machine operable to generate memory control signals for executing memory operations for the plurality of memory planes in response to the control, command and address signals; a plurality of memory plane control circuits, each control circuit associated with a respective one of the plurality of memory planes and coupled to the state machine to receive the memory control signals, each control circuit operable to control execution of memory operations for the respective memory plane in response to the control signals from the state machine when enabled by a respective active enable signal; a plurality of data registers, each data register associated with a respective one of the plurality of memory planes; and control circuit enable logic coupled to the state machine and coupled to the plurality of memory plane control circuits, the control circuit enable logic operable to generate respective active enable signals for the plurality of memory plane control circuits to initiate the memory operation for a first memory plane at a first time and initiate the memory operation for a second memory plane at a second time, the second time subsequent to the first time and during execution of the memory operation for the first memory plane.