Patent ID: 7782653

Claim:
A semiconductor memory device, comprising: a memory circuit containing a pair of memory nodes; a first capacitor comprising a first end and a second end, said first end being connected to one of said memory nodes; a second capacitor comprising a third end and a fourth end, said third end being connected to another of said memory nodes and said fourth end being connected to said second end; and a switch connected to said second end of said first capacitor and setting said second end at a first state when the semiconductor memory device operates in a first mode of operation and changing said second end into a second and different state when the semiconductor memory device operates in a second mode of operation having a speed different from that of said first mode, wherein said switch controls a voltage of said second end to use both of said capacitors during both of a data writing operation and a data reading operation in said second mode, and wherein said switch part brings said second end into a floating state when the semiconductor memory device operates at said second mode.