Patent ID: 8658523

Claim:
A method, comprising: following exposure of a first semiconductor surface for a first metal source and/or drain of a first field-effect transistor (FET) and a second semiconductor surface for a second metal source and/or drain of a second FET, creating a first metal layer for the first metal source and/or drain, the first metal layer having (i) a workfunction greater than an ionization potential of a semiconductor proximate to an interface between the first metal layer and a semiconductor comprising a channel of the first FET, and (ii) a thickness of at least 1 nm but no more than 100 nm; and creating a second metal layer for the second metal source and/or drain and capping the first metal layer with a thickness of no less than 1 nm, the second metal layer having a workfunction less than an electron affinity of a semiconductor comprising a channel of the second FET.