Patent ID: 7216281

Claim:
A waveform formatter circuit which generates a test pattern which is input to a DUT (device under test), comprising: a real time selector which receives a plurality of sets of waveform data output from a waveform memory, receives a plurality of sets of timing data output from a timing generator, selects and outputs predetermined waveform data and timing data, and inhibits an edge that comes immediately after a current edge and outputs a predetermined inhibiting signal when two edges with the same polarity which are continuous exist in an interval shorter than a predetermined proximity limit time in the waveform data; and a detector which receives the waveform data, the timing data and the inhibiting signal output from the real time selector, and outputs a predetermined fail signal when an edge with a polarity reverse to that of an edge inhibited by the real time selector exists in the predetermined proximity limit time before the inhibited edge.