Patent ID: 7629206

Claim:
A method of patterning a semiconductor layer to form a display backplane, comprising: forming gate, source, and drain electrodes of a transistor on a transparent substrate having a first surface and a second surface, a width of the drain electrode and a width of the source electrode greater than a width of the gate electrode, wherein forming the source and drain electrodes comprises forming data lines and pixel electrodes of the display backplane and forming the gate electrodes comprises forming enable lines of the display backplane; depositing a semiconductor layer comprising ZnO or a-Si:H proximate to the gate, source and drain electrodes; depositing photoresist over the semiconductor layer; exposing the photoresist through a mask to light directed toward the first surface of the transparent substrate; exposing the photoresist to light directed through the second surface of the transparent substrate, the gate electrode masking the photoresist from the light; and removing the semiconductor layer in regions exposed to the light.