Patent ID: 7227251

Claim:
A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip; first to third leads extending above a surface formed with bonding pads of the first semiconductor chip; and fourth to sixth leads extending above a surface formed with bonding pads of the second semiconductor chip, wherein the first lead is electrically coupled to the fourth lead, wherein the second lead is electrically coupled to the fifth lead, wherein the third lead is electrically coupled to the sixth lead, wherein the first semiconductor chip is electrically coupled to the first and second leads and is isolated from the third lead, wherein the second semiconductor chip is electrically coupled to the fourth and sixth leads and is isolated from the fifth lead, wherein the first and second semiconductor chips are operated based on a clock signal which is supplied to the first lead, wherein the first semiconductor chip changes to a low power mode based on a first clock enable signal supplied to the second lead, wherein the second semiconductor chip changes to a low power mode based on a second clock enable signal supplied to the third lead, wherein the clock signal is supplied to the fourth lead via the first lead, and wherein the second clock signal is supplied to the sixth lead via the third lead.