Patent ID: 7800560

Claim:
A driver for a display panel in which a plurality of light-emitting elements are arranged in a matrix at intersections between a plurality of row lines and a plurality of column lines, comprising: a scan unit configured to sequentially scan the plurality of row lines during a scan period by connecting a first row line to be scanned to a first reference potential, and by connecting all the other row lines excluding the first row line to a second reference potential, the second reference potential being higher than the first reference potential; a reset unit configured to connect the plurality of row lines to the first reference potential during a reset period between two scan periods for adjacent row lines; a potential control unit configured to control potentials of the other row lines excluding the first row line from the first reference potential to the second reference potential at a predetermined ratio of potential change to time or less after the reset period elapses; a plurality of timing circuits configured to start timing a first period at the end of the reset period, each of the plurality of timing circuits being provided to correspond to each of the plurality of row lines; a plurality of first transistors, each of which is connected between each of the plurality of row lines and the first reference potential, each of the plurality of first transistors being switched on during the reset period; a plurality of second transistors, each of which includes a first on-resistance, each of the plurality of second transistors being connected between each of the plurality of row lines and the second reference potential, and each of the plurality of second transistors being switched on at the end of the reset period; and a plurality of third transistors, each of which has a second on-resistance, the second on-resistance being smaller than the first on-resistance, each of the plurality of third transistors being connected between each of the plurality of row lines and the second reference potential, and each of the plurality of third transistors being switched on after the first period elapses.