Patent ID: 7636907

Claim:
A computer-implemented method of balancing logic resource usage in a circuit design for a programmable integrated circuit, the method comprising: determining that an assignment of circuit elements of the circuit design is unbalanced when a measure of usage of a first type of logic resource exceeds a measure of usage of an alternate type of logic resource within the programmable integrated circuit; generating an Integer Linear Programming (ILP) formulation specifying an assignment of circuit elements to the first type of logic resource and the alternate type of logic resource, wherein the ILP formulation comprises a timing constraint that depends upon a difference between a delay of the alternate type of logic resource and the first type of logic resource; obtaining and storing a solution for the ILP formulation within memory; re-mapping selected circuit elements of the circuit design from the first type of logic resource to the alternate type of logic resource according to the solution for the ILP formulation; and storing the circuit design specifying the re-mapped circuit elements within memory, wherein determining that an assignment of circuit elements is unbalanced, generating an ILP formulation, obtaining and storing a solution for the ILP formulation, re-mapping selected circuit elements, and storing the circuit design are performed by a computer.