Patent ID: 8552772

Claim:
A phase-locked loop circuit, comprising: a voltage-controlled oscillator (VCO) for providing a VCO output signal; an N-divider having an input for receiving the VCO output signal and for providing an N-divided output signal; a first input for receiving a signal oscillating at a reference frequency; a second input for receiving the N-divided output signal; a phase detector and charge-pump, the phase detector for comparing a phase of the first input and a phase of the second input; a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter; and a buffer in parallel with the integrator and in series with the post-filter, the buffer for receiving an output signal from the integrator and for isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal to expand a tuning range voltage at a VCO input, wherein the multiplexer comprises a selection input, wherein when the tuning range voltage is closer to VDD the plus level shift signal is selected via the selection input for passing through the multiplexer, wherein when the tuning range voltage is closer to ground the minus level shift signal is selected via the selection input for passing through the multiplexer, and wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.