Patent ID: 7801207

Claim:
A communication apparatus comprising: a radio frequency (RF) circuit configured to operate on a radio frequency signal; and a digital processing circuit coupled to the RF circuit, wherein the digital processing circuit is configured to operate in association with the RF circuit according to a time domain isolation technique; wherein the digital processing circuit includes a scheduler configured to: schedule a channel equalization task for each of one or more respective receive time slots to be performed during time slots reserved for the digital processing circuit; and schedule a decode task to obtain slot allocation information for each of the one or more respective receive time slots to be performed during the time slots reserved for the digital processing circuit; and wherein the digital processing circuit further includes a buffer control circuit coupled to the scheduler, a first buffer memory coupled to the buffer control circuit for storing results from equalization tasks performed during even numbered radio blocks and a second buffer memory coupled to the buffer control circuit for storing results from equalization tasks performed during odd numbered radio blocks.