Patent ID: 8527736

Claim:
A computer system, comprising: a translation lookaside buffer (TLB) having a plurality of entries for mapping virtual memory addresses to physical memory addresses; and logic configured to perform the following steps for a contiguous section of memory: (a) selecting a size indicator for a TLB entry of the TLB; (b) determining whether a mapping for the TLB entry is aligned with a boundary of the contiguous section of memory or a boundary for another entry of the TLB previously mapped to the contiguous section of memory without overshooting an end of the contiguous section of memory, wherein the mapping for the TLB entry maps a respective virtual memory address to each physical memory address for a chunk of the memory having a size equal to the size indicator; (c) if the mapping for the TLB entry is determined to be aligned with the boundary of the contiguous section of memory or the boundary for another entry of the TLB previously mapped to the contiguous section memory without overshooting the end of the contiguous section of memory, configuring the TLB entry by writing the mapping, including the selected size indicator, into the TLB entry; and (d) repeating steps (a) through (c) until a mapping for the TLB entry is found to be aligned with the boundary of the contiguous section of memory or the boundary for another entry of the TLB previously mapped to the contiguous section memory without overshooting the end of the contiguous section of memory, wherein the logic is configured to repeat steps (a) through (d) until the contiguous section of memory is entirely mapped to virtual addresses by entries of the TLB.