Patent ID: 7216279

Claim:
A hard macro resident on a monolithic substrate with an integrated circuit having an operational frequency, the hard macro adapted to receive a reference clock signal from a tester that is external to the substrate at a tester frequency that is below the operational frequency of the integrated circuit and produce a multiplied clock signal having a second frequency that is at least equal to the operational frequency of the integrated circuit, the hard macro comprising: a first reference clock input adapted to receive a first reference clock signal from the tester at the tester frequency and a first phase, a second reference clock input adapted to receive a second reference clock signal from the tester at the tester frequency and a second phase, where the second phase is offset by substantially ninety degrees from the first phase of the first reference clock signal, a speed select input adapted to receive a speed select signal, where the speed select signal is selectively set at one of at least a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro, and a clock multiplication circuit adapted to receive the first reference clock signal, selectively receive the second reference clock signal, and receive the speed select signal and produce the multiplied clock signal at a multiplied clock output, where the multiplied clock signal has the second frequency, which is a multiple of the tester frequency that is dependent at least in part upon the tester frequency and the setting of the speed select signal.