Patent ID: 7704850

Claim:
A semiconductor device, for determining an overlay error on a semiconductor substrate, the semiconductor device comprising a first transistor and a second transistor, wherein the first transistor comprises a first and a second diffusion region associated with a first gate, the first gate comprising a first gate portion and a second gate portion, the first gate portion and the second gate portion extending parallel to each other in a first direction, a gate length of the first gate portion being different from a gate length of the second gate portion; the second transistor comprises a third and a fourth diffusion region associated with a second gate, the second gate comprising a third gate portion and a fourth gate portion, the third gate portion and the fourth gate portion extending parallel to each other in the first direction, a gate length of the third gate portion is different from a gate length of the fourth gate portion; the second transistor arranged adjacent to the first transistor in a second direction perpendicular to the first direction; the first and second gates each having a non-uniform shape, and wherein the second gate is oriented with respect to an orientation of the first gate such that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on a corresponding device parameter of the first transistor.