Patent ID: 7698661

Claim:
A circuit automatic generation apparatus of a semiconductor integrated circuit for connecting signals of a plurality of function circuits to generate a top-layer circuit, the circuit automatic generation apparatus comprising: means for retaining data, wherein the data comprises input/output information of each of the function circuits and circuit information to which each of the function circuits is connected, test mode generation specifications for generating a test mode signal to identify a plurality of operation modes containing the usual operation time and the test operation time, test specifications added to each of the function circuits, terminal test specifications for specifying input/output directions of terminals and circuit terminal information to which the terminals are connected in response to the test mode signal, input/output information of the top-layer circuit and circuit information to which the top-layer circuit is connected, and combining mode generation specification of combining power supply control specification for specifying a power supply control method to semiconductor elements for each of power supply channels into which one power supply channel is divided; means for collating the connecting signals of each function circuit based on the retained data and determining the presence or absence of a connection defect; means for making a correction to the retained data when collating determines the presence of a connection defect; means for generating a test mode generation circuit in response to the test mode generation specifications; means for generating a function circuit to which test specifications are added in response to the test specifications added to the function circuit; means for generating a terminal test circuit in response to the terminal test specifications; means for generating the top-layer circuit from the test mode generation specifications, the terminal test specifications, the input/output information of the function circuit and circuit information to which the function circuit is connected, the test specifications added to the function circuit, and the input/output information of the top-layer circuit and circuit information to which the top-layer circuit is connected; means for generating a combining mode generation circuit in response to the combining mode generation specification; means for generating a test specification and power supply specification addition circuit from the combining mode generation specification and the input/output information of the function circuit and circuit information to which the function circuit is connected; and wherein the top-layer circuit of a hierarchical design is described in a hardware description language.