Patent ID: 8760959

Claim:
A memory device comprising: a first memory cell; a second memory cell provided in a same row as the first memory cell; a row selection line; a first column selection line; and a second column selection line, wherein the first memory cell includes a field-effect transistor comprising a first gate and a second gate and controlling at least data writing and data holding in the first memory cell by being turned on or off, wherein the second memory cell includes a field-effect transistor comprising a first gate and a second gate and controlling at least data writing and data holding in the second memory cell by being turned on or off, wherein the row selection line is electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, wherein the first column selection line is electrically connected to the second gate of the field-effect transistor included in the first memory cell, and wherein the second column selection line is electrically connected to the second gate of the field-effect transistor included in the second memory cell.