Patent ID: 6869857

Claim:
A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising: depositing an etch stop layer on the surface of a semiconductor substrate; etching a plurality of isolation trenches through said etch stop layer into said semiconductor substrate whereby narrow active areas and wide active areas of said semiconductor substrate are left between said isolation trenches; depositing an oxide layer over said etch stop layer and within said isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein after said oxide layer fills said isolation trenches, said deposition component is discontinued while continuing said sputtering component until said oxide layer is at a desired depth in said isolation trenches whereby said oxide layer within said isolation trenches is disconnected from said oxide layer overlying said etch stop layer; thereafter etching away said oxide layer overlying said etch stop layer in said wide active areas wherein oxide layer residues are left overlying said etch stop layer; and removing said etch stop layer and said oxide residues to complete planarized said shallow trench isolation regions in said manufacture of said integrated circuit device.