Patent ID: 6846712

Claim:
A method for fabricating an integrated circuit comprising a nonvolatile memory comprising a nonvolatile memory cell comprising a floating gate, a select gate, and a control gate, the nonvolatile memory further comprising a first peripheral transistor, the method comprising: (a) forming a dielectric layer on a semiconductor substrate, the dielectric layer comprising a first dielectric region (“select gate dielectric”) and a second dielectric region (“first peripheral transistor gate dielectric”), wherein the select gate dielectric and the first peripheral transistor gate dielectric are formed simultaneously; (b) forming a first layer over the dielectric layer and patterning the first layer to provide (i) the select gate on the select gate dielectric, and (ii) a gate for the first peripheral transistor on the first peripheral transistor gate dielectric; (c) after the operation (b), forming the floating gate and the control gate for the memory cell; wherein the select gate dielectric as at least as thick as a gate dielectric of any peripheral transistor in said memory.