Patent ID: 7978532

Claim:
An erase method of a flash memory device including a plurality of Multi Level Cells (MLCs) that share word lines and bit lines, the erase method comprising the steps of: selecting MLCs of the plurality of MLCs connected to a selected word line, wherein each of the plurality of the MLCs has a threshold voltage included in one of first to fourth voltage ranges and each of the selected MLCs has a threshold voltage included in the first voltage range; pre-programming the selected MLCs so that the threshold voltages of the selected MLCs are moved from the first voltage range to the fourth voltage range, wherein non-selected MLCs of the plurality of the MLCs are prohibited from being pre-programmed when the selected MLCs are pre-programmed; erasing the plurality of MLCs after performing the pre-programming step; and verifying whether the plurality of MLCs has been normally erased, wherein the pre-programming step is performed in the first place, and; wherein a highest voltage of the first voltage range is lower than a lowest voltage of the second voltage range, a highest voltage of the second voltage range is lower than a lowest voltage of the third voltage range, and a highest voltage of the third voltage range is lower than a lowest voltage of the fourth voltage range.