Patent ID: 7545009

Claim:
A word line for a memory cell, comprising: a gate dielectric layer; a silicon-containing layer overlying the gate dielectric layer; a first refractory metal material overlying the silicon-containing layer, wherein the first refractory metal material is a conductive material containing a first refractory metal and a first impurity forming a chemical bond with the first refractory metal; a second refractory metal material overlying the first refractory metal material, wherein the second refractory metal material is a conductive material containing a second refractory metal and a second impurity forming a chemical bond with the second refractory metal; a conductor layer overlying the second refractory metal material; and a silicide layer interposed between the first refractory metal material and the silicon-containing layer; wherein the silicide layer is formed after the second refractory metal material is formed; wherein the first refractory metal material contains the first impurity at a level less than a stoichiometric level; and wherein the second refractory metal material has a lower affinity for the first and second impurities than does the first refractory metal material.