Patent ID: 7499323

Claim:
A non-volatile memory device comprising: a memory cell array including a plurality of memory banks, the plurality of memory banks including first and second memory banks; an input buffer unit that receives first input data or second input data from an external device in response to a chip enable signal; a first page buffer unit that receives the first input data and transmits the first input data to the first memory bank; and a second page buffer unit that receives the second input data and transmits the second input data to the second memory bank, wherein the first page buffer unit is configured to sense and store first read data read from one of the memory banks, the second page buffer unit is configured to sense and store second read data read from one of the memory banks, the memory device further comprising: an output driver unit that receives first internal output data or second internal output data and outputs first output data or second output data to the external device, in response to a read enable control signal; a first data I/O unit that transmits the first input data, which are received from the input buffer unit, to the first page buffer unit or receives the first read data from the first page buffer unit and transmits the first internal output data to the output driver unit, in response to first control signals, first column selection signals, and a data input enable signal; and a second data I/O unit that transmits the second input data, which are received from the input buffer unit, to the second page buffer unit or receives the second read data from the second page buffer unit and transmits the second internal output data to the output driver unit, in response to second control signals, second column selection signals, and the data input enable signal, wherein the input buffer unit further receives a command signal and external address signals from the external device in response to the chip enable signal, and the external address signals include first external address signals and second external address signals, and wherein the non-volatile memory device further comprises a control signal generator that generates the first and second control signals based on some of the first external address signals, a write enable signal, and a data output enable signal.