Patent ID: 8071436

Claim:
A method of fabricating a semiconductor device, the method comprising: forming an LDMOS transistor on a substrate, the LDMOS transistor including a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source; and forming an n-type CMOS transistor on the substrate, the n-type CMOS transistor including a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source; wherein forming the LDMOS transistor and forming the n-type CMOS transistor comprise a first implant step that, without implanting into the first drain, simultaneously implants a first lightly n-doped region in the first source to overlap the first source-side n+ region and to extend beneath the first gate, and a second lightly n-doped region in the second drain to overlap the second drain-side n+ region and to extend beneath the second gate.