Patent ID: 6862251

Claim:
A semiconductor memory device comprising: a first nonvolatile memory cell; a bit line connected to the first nonvolatile memory cell; and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period “a” of time in response to transition of an input address signal, wherein the control circuit has an address transition detection circuit disposed and configured in such a manner as to receive the input address signal, thereby generating a pulse signal and a reset circuit connected to the address transition detection circuit, the bit line and the first nonvolatile memory cell, the reset circuit is disposed and configured in such a manner as to reset the bit line to the predetermined first potential state in response to the pulse signal, the reset circuit has a first transistor having a first terminal connected to the bit line, a second terminal connected to a power source terminal and a third terminal connected to the address transition detection circuit and being adapted to drive the bit line into the predetermined first potential state in response to the pulse signal and a second transistor having a fourth terminal connected to the first terminal of the first transistor, a fifth terminal connected to the bit line and a sixth terminal connected to the third terminal of the first transistor, and the first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.