Patent ID: 8339172

Claim:
A flip-flop device comprising: a multiplexing circuit configured to receive, as input, data to be latched and to be clocked by a clock signal; a first master stage configured to latch the data and to be clocked based upon a first type phase of the clock signal, said first master stage comprising a NAND logic gate having an input, a first inverter coupled to the input of said NAND logic gate, and a first loopback inverter coupled in parallel with said NAND logic gate; and a second slave stage configured to latch the data and to be clocked based upon a second type of phase of the clock signal, said second slave stage comprising a NOR logic gate having an input, second and third inverters coupled in series at the input of said NOR logic gate, and a second loopback inverter coupled in parallel with said NOR logic gate.