Patent ID: 6987702

Claim:
A method of testing multiple columns of memory concurrently, each column of memory having a pair of complementary digit lines, the method comprising: precharging first and second data nodes; concurrently coupling a first of the complementary digit lines to the first data node; performing a first boolean OR function based on logic states of all of the first of the complementary digit lines coupled to the first data node; driving the first data node to the resulting logic state of the first OR function; concurrently coupling a second of the complementary digit lines to the second data node; performing a second boolean OR function based on logic states of all of the second of the complementary digit lines coupled to the second data node; driving the second data node to the resulting logic state of the second OR function; generating an output signal having a logic state indicative of a pass-fail condition based on the logic states of the first and second data nodes.