Patent ID: 7382775

Claim:
An interconnect structure comprising: a plurality of nodes with each node having a plurality of input ports and a plurality of output ports, the plurality of nodes including a node X having an output port opx and a set of input ports IPX; a logic associated with the node X that sends messages entering an input port of the set IPX to the output port opx whereby if a message M p arrives at an input port p of input port set IPX and a path exists from the output port opx to a target of message M p , then one of multiple messages arriving at the input port set IPX is sent to output port opx so long as the output port opx is not blocked by a message traveling external to the node X; a set of output ports in the node X to which the message M p can be sent; and the logic associated with the node X that orders the output ports from most desirable to least desirable for passing the message M p , and that sends the message M p to a member of the output port set determined to be a most desirable unblocked member.