Patent ID: 6930509

Claim:
A programmable flip-flop for outputting data, the flip-flop including: a first latch for latching a first input value in response to a rising edge of a clock signal; a second latch for latching a second input value in response to a falling edge of the clock signal; selection means controlled by the clock signal for selectively supplying outputs of the first and second latches to the input of a third latch; third latch control means accepting as inputs the clock signal and an inverted clock signal; the programmable flip-flop being configurable to operate in at least first and second modes selectable by the selection means and third latch control means, such that in the first mode the output of the third latch is the first and second input values multiplexed together and output at twice the clock rate, and in the second mode one of the first and second latches is disconnected from the third latch such that the programmable flip-flop operates as a single edge-triggered register clocking out one of the first and second input values from the third latch.