Patent ID: 7373616

Claim:
A method of designing a semiconductor integrated circuit which performs a predetermined logical operation, the method comprising: synthesizing the semiconductor integrated circuit by a predetermined circuit arrangement in which a plurality of logical circuits each performing the predetermined logical operation are continuously connected; replacing the predetermined circuit arrangement in such a manner that a low-threshold-value high-speed transistor is applied to a portion required to be speeded up, and a high-threshold-value low-speed transistor is applied to a portion which is not required to be speeded up in the predetermined circuit arrangement; continuously connecting the low-threshold-value high-speed transistors to thereby detect such an inadequacy of connection that a potential of a signal propagating through stages of the circuit gradually deviates from a power voltage and a ground voltage; and replacing the low-threshold-value high-speed transistor disposed in a portion in which the inadequacy of the connection is detected with a constitution having less leak current.