Patent ID: 7709317

Claim:
A method of fabricating a semiconductor structure comprising: forming a first stress inducing liner and an overlaying hard mask on a structure including at least one nFET and at least one pFET, said first stress inducing liner having a first stress type and each FET including a device channel, a wide outer spacer and a silicided source/drain diffusion contact; selectively removing said overlaying hard mask, said first stress inducing liner, and all or part of said wide outer spacer from one of said nFETs or pFETs to form at least one spacerless FET, while maintaining said wide outer spacer on the other of said nFETs or pFETs, wherein during removal of said first stress inducing liner and said wide spacer, said silicided source/drain diffusion contact of said at least one spacerless FIST is amorphized; performing a recrystallization anneal in an inert ambient to recrystallize said amorphized silicided source/drain diffusion contact of said at least one spacerless FIST prior to formation of a second stress inducing liner; and selectively providing the second stress inducing liner of a second stress type that is different from said first stress type to said at least one spacerless FET including said recrystallized silicided source/drain diffusion contact, wherein said second stress inducing liner is positioned within 30 nm or less from the channel region of the at least one spacerless FET, wherein a portion of the second stress inducing liner and a portion of the first stress inducing linear overlap each other in an area atop an isolation region that is present in the semiconductor substrate.