Patent ID: 8279686

Claim:
A memory circuit, comprising: at least one memory cell for storing a charge representative of a datum, the memory cell being coupled with a word line and a first bit line of a bit line pair; at least one bit line equalization transistor coupled between the first bit line and a second bit line of the bit line pair; and a bit line equalization circuit coupled with the bit line equalization transistor, the bit line equalization circuit being configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell, raising the pulse from a first power voltage to a second power voltage, providing the second power voltage during a precharge period of the access cycle of the memory cell, and pulling down the second power voltage to a voltage state, wherein the voltage state is lower than the first power voltage if an array activation signal is detected during the precharge period or during a predetermined period after the precharge period, and the voltage state is substantially equal to the first power voltage if the array activation signal is not detected during the precharge period and during the predetermined period after the precharge period.