Patent ID: 8429583

Claim:
A method to design a circuit, the method comprising: selecting a target clock for a design of the circuit; determining a plurality of latencies for a portion of the circuit; determining a representation of a data flow graph for the portion of the circuit, wherein how many of extra delays are required for the data flow graph is determined based on the target clock and the plurality of latencies, wherein said determining the representation of the data flow graph comprises determining a number of extra delays required on an edge of the data flow graph, wherein the edge connects a first node and a second node of the data flow graph, the first and second nodes connected by the edge represents paths that start from and end in registers in the portion of the circuit, wherein the first node connects to a node that represents signal delay which is not smaller than signal delay on any path that contains no registers and that is between a first input of the portion of the circuit and an input of a register of the portion of the circuit; and retiming the design for the circuit to operate at the target clock based on the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor.