Patent ID: 8015359

Claim:
An instruction processing circuit for a processor, wherein the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor, wherein the instruction processing circuit comprises: a decoder and builder circuit configured to: obtain an instruction, identified by a virtual address, based on a virtual address to physical address mapping; and decode and build the instruction into a sequence of operations of a trace, wherein the trace comprises a pointer referencing an entry comprising the virtual address to physical address mapping; a cache circuit for storing the trace; a sequencer configured to specify a next instruction of which a corresponding sequence of operations is to be provided to the execution unit; and a page translation buffer coupled to the sequencer and configured to: store the entry comprising the virtual address to physical address mapping, wherein the entry is referenced based on the pointer; and identify a status of the entry in response to a cache hit of the cache, wherein the cache hit identifies the sequence of operations of the trace stored therein as the corresponding sequence of operations of the next instruction specified by the sequencer, wherein the trace is invalidated based on the status of the entry.