Patent ID: 7482233

Claim:
A method for fabricating an integrated circuit including at least one field-effect transistor and at least one non-volatile memory (NVM) cell, the method comprising: forming first and second gate structures on a substrate, the first and second gate structures being spaced apart and each of the first and second gate structures defining side walls; masking the second gate structure, and forming lightly-doped source and drain regions in the substrate such that the lightly-doped source and drain regions extend under the first gate structure; forming first sidewall spacers adjacent the side walls of the first gate structure and second sidewall spacers adjacent the side walls of the second gate structure such that a first thickness of a first oxide layer separating the first sidewall spacers and the first gate structure are greater than a second thicknesses of a second oxide layer separating the second sidewall spacers and the second gate structure, wherein the first and second sidewall spacers comprise substantially identical structures; and forming heavily-doped source and drain regions in the substrate on opposite sides of the first and second gate structures such that each of the heavily-doped source and drain regions respectively extend under the first and second sidewall spacers. wherein forming the first and second gate structures comprises: forming a polycrystalline silicon layer on a gate oxide layer; etching the polycrystalline silicon layer to form the first gate structure; forming said first oxide layer on first gate structure; etching the polycrystalline silicon layer to form the second gate structure; and forming said second oxide layer on second gate structure, wherein forming the first oxide layer comprises forming TEOS oxide layers having thicknesses of approximately 200 angstroms on both the sidewalls of the first gate structure and on first exposed surface portions of the substrate located adjacent to the first gate structure, and wherein forming the second oxide layer comprises forming an oxide layer having a thickness in the range of 30 to 200 A on second exposed portions of the substrate located adjacent to the second gate structure.