Patent ID: 8415672

Claim:
A transistor, comprising: a substrate; a crystalline semiconductor layer disposed on the substrate, the crystalline semiconductor layer comprising an upper surface, a first side surface and a second side surface; an etching stop structure disposed on the crystalline semiconductor layer, the etching stop structure comprising a first portion and a second portion; an ohmic contact layer disposed on the crystalline semiconductor layer and the etching stop structure, the ohmic contact layer comprising a first ohmic contact region and a second ohmic contact region, wherein the first ohmic contact region extends towards the crystalline semiconductor layer from an area above the first portion of the etching stop structure and overlies one side of the upper surface of the crystalline semiconductor layer, and the second ohmic contact region extends towards the crystalline semiconductor layer from an area above the second portion of the etching stop structure and overlies the other side of the upper surface of the crystalline semiconductor layer; a source overlying the first ohmic contact region; a drain overlying the second ohmic contact region; a gate insulating layer disposed on the source, the drain, and the crystalline semiconductor layer; and a gate, disposed on the gate insulating layer and corresponding to the crystalline semiconductor layer.