Patent ID: 7518245

Claim:
A semiconductor device comprising: a conductive pad formed in a non-cell area of a semiconductor substrate; a lower interlayer insulating layer formed in a cell area of the semiconductor substrate and over the conductive pad; a conductive plug formed in a contact hole extending through a portion of the lower interlayer insulating layer located in the cell area of the semiconductor substrate; a first contact pattern over the lower interlayer insulating layer, the first contact pattern having a first opening overlying a peripheral region of the conductive pad and exposing an upper surface of the lower interlayer insulating layer; a second contact pattern over the conductive plug, the second contact pattern having a second opening exposing the conductive plug; a first conductive pattern in the first opening, the first conductive pattern having a third opening to expose a region of the conductive pad adjacent to the peripheral region of the conductive pad; a second conductive pattern in the second opening; an upper interlayer insulating layer over the first conductive pattern, the upper interlayer insulating layer having a fourth opening exposing the first conductive pattern and the third opening; and a conductive contact extending through the third opening and the fourth opening, the conductive contact electrically connected to the conductive pad, wherein the first and second conductive patterns comprise the same layer of material.