Patent ID: 8680619

Claim:
A semiconductor device, comprising: a transistor, including: a first gate structure disposed over a substrate, the first gate structure including a first gate electrode of a first conductivity type; a second gate structure disposed over the substrate and spaced a distance from the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, and wherein a dielectric is disposed in the distance between the first and second gate structures, wherein a to surface of the dielectric is coplanar with a to surface of each of the first and second gate structures; a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first edge self-aligned with the first gate structure, such that the first edge of the first doped region is approximately collinear with a sidewall of the first gate structure, wherein the first doped region provides one of a source and a drain for the transistor; and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second edge self-aligned with the second gate structure, such that the second edge of the second doped region is approximately collinear with a sidewall of the second gate structure, and wherein the second doped region provides the other of the source and the drain of the transistor.