Patent ID: 7685347

Claim:
An interrupt controller for a computing system including a plurality of processors, comprising: a plurality of inputs, each for receiving a respective service request for invoking one of a plurality of service routines, each service routine having a higher priority than a plurality of priorities for executing a plurality of tasks on the processors; a plurality of registers respectively associated with the processors and each register for storing the priority of the task executing on the associated processor; a comparator coupled to the registers for determining a determined one of the processors executing a task having a lower priority among the priorities of the tasks executing on the processors; a distributor coupled to the inputs and the comparator, the distributor, in response to receiving the respective service request from each input, for generating an interrupt request for invoking the one of the service routines on the determined one of the processors, wherein the register associated with the determined one of the processors is set to the higher priority of the service routine in response to the interrupt request; a plurality of outputs, each output coupled to the distributor for transmitting the interrupt request to a respective one of the processors; and a software-interrupt generator coupled to an input of the distributor and writable by the processors with a software priority, the software-interrupt generator for generating an interrupt request that is transmitted by the distributor via the output for the determined one of the processors in response to one of the plurality of processors writing to the software-interrupt generator the software priority that is higher than the lower priority of the task executing on the determined one of the processors.