Patent ID: 7061049

Claim:
A semiconductor integrated circuit comprising: a clock signal source which outputs a clock signal; a clock distribution circuit section comprising a transistor, a first power line and a second power line, the clock distribution circuit section supplied with the clock signal and selectively outputting the clock signal in response to an operation of the transistor, the transistor comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate, a semiconductor layer provided on the insulating film, a gate insulating film provided on the semiconductor layer, a gate electrode provided on the gate insulating film, a source region and a drain region formed in the semiconductor layer to hold a body region under the gate electrode therebetween; a first potential line having a first potential, the first potential being set such that a potential of the body region in an OFF state of the transistor is the same as a potential of the body region in an ON state of the transistor; and a first switch connecting the first power line to the first potential line in the OFF state.