Patent ID: 8032737

Claim:
A method comprising: in response to a first instruction execution thread being in an active mode, fetching and issuing one or more instructions, corresponding to the first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread; switching a second instruction execution thread to the active mode when the cycle count associated with the first instruction execution thread is complete; fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread; and resetting the cycle count associated with the first instruction execution thread or the cycle count associated with the second instruction execution thread only when a master instruction execution thread is in the active mode, wherein instruction execution threads are one of either a master instruction execution thread or a child instruction execution thread, where a master instruction execution thread can access thread control registers of any one or more child instruction execution threads, and a child instruction execution thread cannot access the thread control registers of any other instruction execution threads.