Patent ID: 7634611

Claim:
A multi-master and chained two-wire serial bus, comprising: a host two-wire serial bus, including: a first master device; one or more slave devices coupled to the first master device, each slave device operable to send data to and receive data from the first master device; and one or more chained two-wire serial busses coupled to the host two-wire serial bus, comprising: a second master device, the second master device also being a slave device on the host two-wire serial bus, the second master device operable to send data to and receive data from the first master device; and one or more other slave devices coupled to the second master device, each other slave device operable to send data to and receive data from the second master device; wherein the second master device comprises an emulation memory operable to: store data received from the first master device or received from the one or more other slave devices and to emulate data stored at one or more of the other slave devices on one of the chained two-wire serial busses; and wherein the emulation memory stores the same type and amount of data and at the same address and offset as the one or more slave devices on the one of the chained two-wire serial busses.