Patent ID: 7336554

Claim:
A semiconductor memory device, comprising: an IO circuit for receiving or outputting command signals, address signals and data which are serialized, wherein the IO circuit includes: a combined terminal receiving or outputting the command signals, the address signals, and the data which are serialized; and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to an internal circuit, and serial converting parallel data applied from the internal circuit and outputting the serial converted signals to the IO circuit, wherein the IO signal control circuit includes: a serial to parallel converting portion for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to the internal circuit, wherein the serial to parallel converting portion includes: a command signal serial to parallel converting portion for acquiring and parallel converting the serialized command signals among the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted command signals to the internal circuit; an address signal serial to parallel converting portion for acquiring and parallel converting the serialized address signals among the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted address signals to the internal circuit; and a data serial to parallel converting portion for acquiring and parallel converting the serialized data among the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted data to the internal circuit.