Patent ID: 7342421

Claim:
A integrated circuit including a CMOS circuit arrangement, comprising: a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of the PMOS logic circuit; an NMOS logic circuit providing the logic function, having NMOS field effect transistors; a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal; wherein an output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another; an inverter circuit coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit; wherein at least a portion of the NMOS field effect transistors of the NMOS logic circuit have a first threshold voltage; wherein at least a portion of the PMOS field effect transistors of the PMOS logic circuit have a third threshold voltage; wherein the first clock transistor has a second threshold voltage; and wherein the first threshold voltage is lower than the second threshold voltage.