Patent ID: 7061290

Claim:
A phase locked loop (PLL) circuit, comprising: a phase comparator for mutually comparing phases of a reference clock signal and a feedback clock signal input to a pair of inputs for a comparison thereof and outputting an up signal or a down signal based on a result of the comparison; a charge pump for causing an output voltage thereof to rise or fall based on the up signal or the down signal output by said phase comparator; a low-pass filter for filtering the output voltage of said charge pump; and a voltage-controlled oscillator for generating a clock signal dependent on an output voltage of said low-pass filter and supplying the generated clock signal to said phase comparator as the feedback clock signal; wherein said PLL circuit further comprises: a dummy phase comparator simulating said phase comparator, for mutually comparing phases of a predetermined clock signal input to a pair of inputs for comparison thereof connected in common and outputting an up signal or a down signal according to a result of the comparison; a dummy charge pump simulating said charge pump, for causing an output voltage thereof to rise or fall based on the up signal or the down signal output by said dummy phase comparator; and an amplifier for detecting a difference between the output voltage of said dummy charge pump and the output voltage of said charge pump, an output voltage of said amplifier providing a signal to said phase comparator and said dummy phase comparator to control pulse widths of at least one of the up and down signals of said phase comparator and said dummy phase comparator.