Patent ID: 7924604

Claim:
A stacked single memory cell for use in a high-density static random access memory, the stacked memory cell comprising: a first pull-down transistor and a second pull-down transistor both formed in an active layer located at a surface of a semiconductor substrate, the first and second pull-down transistors including respective first and second gates located on the active layer; a first pull-up transistor and a second pull-up transistor both formed in a first channel layer located over and parallel to the active layer relative to the surface of the semiconductor substrate, the first and second pull-up transistors including respective third and fourth gates located on the first channel layer, wherein the first and second pull-up transistors are respectively connected to the first and second pull-down transistors to form an inverter latch; and a pass transistor connected between a gate of the second pull-down transistor and a bit line, and formed in a second channel layer located over and parallel to the first channel layer such the first channel layer is interposed between the active layer and the second channel layer, wherein the pass transistor includes a fifth gate located on the second channel layer and connected to a word line, wherein the pass transistor is a single pass transistor and the bit line is a single bit line.