Patent ID: 8749286

Claim:
A scannable storage circuit comprising: a scan enable input; a storage element having a node coupled to a data output buffer for driving a data output terminal, the storage element selectively coupled to a data input terminal and a scan input in response to the scan enable input, the data output buffer comprising: an inverter; transmission gate having a first MOS transistor with source and drain coupled to source and drain of a second MOS transistor, drains of the first and second MOS transistors being coupled to an output of the inverter and sources of the first and second MOS transistors being coupled to the data output terminal, gates of the first MOS transistor and the second MOS transistor being coupled to the scan enable input and an inverted scan enable input; and a third MOS transistor and a fourth MOS transistor coupled to the sources of the first and second MOS transistors, the third MOS transistor configured to pull up the data output terminal in response to a first control signal and the fourth MOS transistor configured to pull down the data output terminal in response to a second control signal, wherein a scan output is generated from the output of the inverter; a multiplexer that receives the scan enable input, data input and scan input, wherein the storage element is selectively coupled to the data input terminal and the scan input in response to the scan enable input; and wherein the storage element further comprising a master latch coupled to a slave latch wherein an input of the master latch is coupled to an output of the multiplexer and an output of the slave latch is coupled to the data output buffer.