Patent ID: 7196926

Claim:
A random access memory, comprising: wherein a capacitor stores data and a diode controls to store data “1” or “0”; diode has four terminals, wherein first terminal is p-type and serves as word line, second terminal is n-type and serves as storage node, third terminal is p-type and floating, and fourth terminal is n-type and serves as bit line; plate of capacitor couples to storage node, which plate has no coupling region to first, third and fourth terminal; and single positive supply is used for memory operation; during standby, word line and bit line stay at ground level, and plate stays at high level; word line and bit line move to high level to read or write, and plate moves to ground level to write; and a write sequence to clear the state of diode which is to turn-on diode before writing; to write data “0”, 1) word line goes up to high level, 2) plate goes down to ground level, 3) bit line goes up to high level, 4) plate returns to high level, which couples to storage node higher than supply level, 5) word line returns to ground level, and 6) finally bit line returns to ground level; to write data “1”, 1) word line goes up to high level, 2) plate goes down to ground level, 3) plate returns to high level but it can not couple storage node, 4) finally word line returns to ground level, while bit line keeps near ground level.