Patent ID: 7944488

Claim:
A circuit to correct defective pixels in an array having a plurality of pixels, comprising: a defective pixel detector including a defective pixel table storing predetermined defective pixel locations, the defective pixel detector sequentially receiving a series of pixel locations from the array; a matching unit matching respective ones of the sequentially received pixel locations with respective, stored defective pixel locations; a defective pixel corrector configured to replace selected ones of pixel values associated with the matched, defective pixel locations with replacement values; a mode setting unit to set a first mode or a second mode; wherein: (i) in the first mode, the defective pixel corrector replaces the pixel values corresponding to the matched defective pixel locations with the replacement values and outputs the replacement values, as output values; and (ii) in the second mode, the defective pixel corrector outputs the pixel values corresponding to the sequentially received pixel locations, as the output values, wherein the defective pixel corrector includes: a memory circuit buffering a pixel value of a pixel which is in a predetermined location relative to a selected pixel location, and a multiplexer for receiving a match signal in accordance with the mode set, receiving the buffered pixel value and a pixel value associated with the selected pixel location and outputting one of the buffered pixel value or the selected pixel value, as the output value; wherein the memory circuit includes a plurality of buffering elements, formed as a delay line, the buffered pixel value is a pixel value associated with another selected pixel location received by the multiplexer prior to the selected pixel value and is input to the memory circuit from the output of the multiplexer such that each respective buffered pixel value is input to the multiplexer, as one of: (1) a previously received selected pixel value or (2) a previously input buffered pixel value.