Patent ID: 8004084

Claim:
A semiconductor device comprising: a semiconductor wafer; a source region and a drain region formed within the semiconductor wafer; a gate electrode formed on the semiconductor wafer between the source region and the drain region; an interlayer film formed on the semiconductor wafer and the gate electrode; and dummy floating patterns embedded into the interlayer film, the dummy floating patterns having a film containing metal or a metallic compound having tensile stress or compressive stress, and the dummy floating patterns formed to be spaced from the semiconductor wafer and the gate electrode, wherein the semiconductor wafer has a first region formed with an n-type active device and a second region formed with a p-type active device, and the dummy floating patterns include: a first dummy floating pattern formed in the first region and having tensile stress; and a second dummy floating pattern, constructed from a film different from the first dummy floating pattern and having compressive stress or tensile stress.