Patent ID: 7216193

Claim:
A data processor formed on a semiconductor device comprising: a first internal bus; a second internal bus; a data transfer controller for transferring a data between the first internal bus and the internal second bus; a central processing unit coupled to the first internal bus; a first unit coupled to the first internal bus; a second unit coupled to the second internal bus; and a bus controller for controlling a bus arbitration for the first internal bus and the second internal bus, the data transfer controller requesting a bus right of one of the internal buses for reading data to the bus controller, accessing the one internal bus for reading data, and releasing the bus right of the one internal bus, and the data transfer controller requesting a bus right of the other internal bus for writing to the bus controller after releasing the bus right of the one internal bus, and accessing the other internal bus for writing the data in response to one data transfer start request, the central processing unit being capable of accessing to the first unit using the first internal bus in parallel with bus access to the second unit using the second internal bus by the data transfer controller in response to one data transfer start request.