Patent ID: 8239812

Claim:
A semiconductor device comprising: a plurality of core chips each including an output terminal; and an interface chip that includes an input terminal electrically connected to the output terminals in common, and a data input circuit that receives a plurality of read data supplied from the output terminals via the input terminal, the interface chip issuing at least a read command to the core chips, wherein each of the core chips includes a data output circuit that outputs the read data to the output terminal in response to the read command, and an output timing adjustment circuit that adjusts an output period from a first time to a second time, the output period being a period of time from reception of the read command to outputting of the read data from the data output circuit to the output terminal, the first time being a minimum time of the output period, the interface chip includes an input timing adjustment circuit that adjusts an input period from a third time to a fourth time, the input period being a period of time from issuance of the read command to capturing of the read data from the input terminal into the data input circuit, the third time being a minimum time of the input period, and the second times and the fourth time are substantially same as longest time among the first times and the third time.