Patent ID: 7065172

Claim:
A clock generation circuit, comprising: a phase-locked loop for generating a plurality of clock phases, the phase-locked loop comprising: a voltage controlled oscillator, for generating a plurality of clock phases at a frequency controlled by a control input to the voltage controlled oscillator; circuitry for generating the control input to the voltage controlled oscillator responsive to phase differences between a reference clock signal and a feedback clock signal; and a feedback frequency divider, for generating the feedback clock signal from one of the clock phases generated by the voltage controlled oscillator, divided by a feedback integer value; a frequency synthesis circuit, comprising: a first multiplexer, for forwarding a selected one of the plurality of clock phases responsive to a first select signal; a second multiplexer, for forwarding a selected one of the plurality of clock phases responsive to a second select signal; a first adder leg, having an input for receiving at least a portion of a frequency select integer word, for generating the first select signal corresponding to a sum of the received portion of the frequency select integer word and a accumulated value; a second adder leg, having an input for receiving at least a portion of the frequency select integer word, for generating the second select signal corresponding to a sum of the received portion of the frequency select integer word and a accumulated value; and circuitry coupled to the first and second outputs of the first and second multiplexers, for generating an output clock signal responsive to the selected clock phases.