Patent ID: 6842059

Claim:
A registered buffer chip comprising: a mode signal that indicates a muxed mode and a non-muxed mode; a differential clock input for receiving a differential clock signal; a slave clock buffer, receiving the differential clock signal, for generating a continuous slave clock that pulses during both the muxed mode and during the non-muxed mode; a first master clock buffer, receiving the differential clock signal, for generating a first clock that pulses during the non-muxed mode but does not pulse during the muxed mode; a second master clock buffer, receiving the differential clock signal, for generating a second clock that pulses during the muxed mode but does not pulse during the non-muxed mode; a dual-bit slice that comprises: a first data input; a first data buffer, receiving the first data input, for driving a first internal data signal; a second data input; a second data buffer, receiving the second data input, for driving a second internal data signal; a first muxed flip-flop receiving the first internal data signal as a first mux input and the second internal data signal as a second mux input, for generating a first data output; a second muxed flip-flop receiving the second internal data signal as both the first mux input and as the second mux input, for generating a second data output; wherein the first muxed flip-flop and the second muxed flip-flop each comprise a muxed master stage and a slave stage; wherein the muxed master stage comprises: a first transmission gate that conducts between the first mux input and a master node in response to the first clock; a second transmission gate that conducts between the second mux input and the master node in response to the second clock; a master inverting gate, having the master node as an input, for driving a coupled node; a master feedback gate, receiving the first clock and the second clock, and having the coupled node as an input, for driving the master node when neither the first transmission gate nor the second transmission gate are conducting; wherein the slave stage comprises: a slave transmission gate that conducts between the coupled node and a slave node in response to the slave clock; a slave inverting gate, having the slave node as an input, for driving an output node; and a slave feedback gate, receiving the slave clock, and having the output node as an input, for driving the slave node when the slave transmission gate is not conducting, whereby the muxed master stage has muxed inputs clocked by mode-enabled clocks so that the first data output but not the second data output is muxed during the muxed mode.