Patent ID: 7092277

Claim:
A memory device including a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element with a programmable resistivity and a unidirectional conduction access element connected in series, a plurality of word lines and a plurality of bit lines, the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means for driving the bit lines to a desired voltage, means for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit tine being forward biased and the other access elements being reverse biased, wherein the memory device further includes means for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected line and the deselected bit lines; and, wherein the bit lines are grouped into at least one sub-set and the means for biasing includes a biasing structure for each sub-set, the biasing structure including means for providing a biasing current corresponding to a total leakage current of each corresponding bit line, and means for draining the biasing current from each corresponding bit line.