Patent ID: 7192495

Claim:
A fabrication method for forming conductive interconnects on a substrate, the method comprising; forming at least one first recessed region to a first width in the substrate; forming at least one second recessed region to a second width in the substrate, wherein the second width is at least greater than the first width; forming a first conductive layer of a first material in the presence of an accelerator that promotes formation of the first conductive layer so as to at least fill the first recessed region to a first fill width; annealing the first conductive layer; forming a second conductive layer of the first material on the first conductive layer after annealing the first conductive layer so as to least fill the second recessed region to a second fill width, wherein filling the second recessed region to the second fill width over fills the first recessed region; and annealing the second conductive layer wherein the previous anneal of the first conductive layer inhibits separation of the first conductive material from the lower surface of the first recessed region during anneal of the second conductive layer.