Patent ID: 8089793

Claim:
A content addressable memory (CAM) cell comprising: a first storage element for storing a data value, wherein the first storage element comprises first and second dynamic random access memory (DRAM) cells; a second storage element for storing the data value, wherein the second storage element comprises third and fourth DRAM cells; and a compare circuit having first inputs to receive from the first storage element a first complementary data signal indicative of the data value, second inputs to receive from the second storage element a second complementary data signal indicative of the data value, third inputs to receive comparand data, and an output coupled to a match line, wherein the compare circuit comprises: first and second transistors coupled in parallel between a first node and a voltage source, the first transistor having a gate coupled to the first DRAM cell of the first memory element and the second transistor having a gate coupled to the third DRAM cell of the second memory element; third and fourth transistors coupled in parallel between a second node and the voltage source, the third transistor having a gate coupled to the second DRAM cell of the first memory element and the fourth transistor having a gate coupled to the fourth DRAM cell of the second memory element; a fifth transistor coupled between the match line and the first node, and having a gate to receive a comparand bit; and a sixth transistor coupled between the match line and the second node, and having a gate to receive a complementary comparand bit.