Patent ID: 7849345

Claim:
A storage drive comprising: a processor; a buffer, the buffer comprising one of a Double Data Rate (“DDR”) synchronous dynamic random addressable memory (“SDRAM”), Single Data Rate (“SDR”) SDRAM, Mobile DRAM, or Low Power (“LP”) DRAM; a first controller configured to transfer commands from the processor to the buffer, wherein the first controller includes a second controller comprising a first register configured to capture a lower data word based on a first clock edge of a system clock, and a second register configured to capture an upper data word based on a second clock edge of the system clock, wherein the first clock edge and the second clock edge occur sequentially; a multiplexer having at least two inputs for receiving an output of the first register and the second register and transferring the output of the first register and the second register to the buffer based on an output of a delay element, wherein the delay element receives a system clock and outputs a delayed system clock based on user-defined programmable settings; a data strobe for sampling data received by the buffer, wherein the data strobe is generated based on the system clock, and wherein sampling the data received at the buffer includes centering a rising edge of the data strobe with the center of a data valid window for the data received at the buffer; and a memory clock received by the buffer, the memory clock generated based on the system clock, wherein the memory clock and the data strobe are phase coherent.