Patent ID: 8447988

Claim:
A processor comprising a plurality of arithmetic logic units (ALUs) and a plurality of registers, wherein: the processor performs hash processing on a string message comprising N message blocks to generate a message digest from the string message; the processor uses (1) a message schedule having G message-schedule words and (2) a plurality of working variables, each working variable associated with a corresponding register of the plurality of registers; the processing of each message block of the N message blocks comprises G message-schedule iterations, each message-schedule iteration comprising: (i) processing a message-schedule word corresponding to the iteration; (ii) processing values of the working variables; (iii) updating at least one working variable based on the processed message-schedule word; and (iv)updating at least one working variable based on the processed value of one or more working variables; the processor performs, in at least one of the message-schedule iterations, at least one of: (a) generating the message-schedule word corresponding to a next message-schedule iteration; (b) pre-processing the value of at least one working variable for the next messageschedule iteration; and (c) varying, from a previous message-schedule iteration, relationships of two or more of the working variables to the corresponding registers; and the processor uses all the ALUs of the plurality of ALUs in parallel in at least one of the message-schedule iterations.