Patent ID: 6985398

Claim:
A semiconductor memory comprising: a bank of N arrays each having a corresponding array address; a bus providing an array address signal, a row address signal (RAS), and global timing signals; and N tracking circuits, each coupled between an associated different one of the N arrays and the bus, wherein a first tracking circuit, in response to receiving a first array address for a first array via the array address signal and a first active state of the RAS, couples the first array to the bus such that only the first array receives and responds to a first sequence of global timing signals associated with the first array address and first active state of the RAS and constituting a first bank transaction, and a second tracking circuit, in response to receiving a second array address for a second array via the array address signal and a second active state of the RAS, couples the second array to the bus such that only the second array responds to a second sequence of global timing signals associated with the second array address and second active state of the RAS and constituting a second bank transaction before the first bank transaction is complete.