Patent ID: 8325553

Claim:
A semiconductor device comprising: a memory cell including a first inverter having an input coupled to a first storage node and an output coupled to a second storage node, a second inverter having an input coupled to the second storage node and an output coupled to the first storage node, a first transistor coupled to the first storage node and a second transistor coupled to the second storage node, the first and second inverters each receiving a power supply voltage and a reference voltage lower than the power supply voltage; a word line coupled to gates of the first and second transistors; a data line pair, one of which is coupled to the first transistor and the other of which is coupled to the second transistor; a power supply line coupled to the first and second inverters and providing the power supply voltage; a third transistor having a source-drain path between the power supply line and a first node to which a first potential is applied; a fourth transistor having a source-drain path between the power supply line and a second node to which a second potential lower than the first potential is applied, wherein signals are applied to gates of the third and fourth transistors to establish a first state that the third and fourth transistors are made conductive and non-conductive, respectively, and a second state that the third and fourth transistors are made non-conductive and conductive, respectively; and the semiconductor device further comprising a driver providing the word line with a voltage lower than the first potential to make the first and second transistors both conductive.