Patent ID: 8687444

Claim:
A method of manufacturing a semiconductor device comprising: performing an operation test on a plurality of memory cells each accessed based on a row address and a column address; generating error pattern information and error address information when a first defective memory cell is detected in the operation test; each time one of a plurality of second defective memory cells different from the first defective memory cell is detected in the operation test, updating the error pattern information based on a relative arrangement relationship between the first and second defective memory cells and updating the error address information based on addresses of at least part of the first and second defective memory cells; and replacing the first and second defective memory cells with respective redundant memory cells based on the error pattern information and the error address information, wherein the error pattern information is updated from a first value to a second value if the first and second defective memory cells have either a same row address or a same column address, wherein the error pattern information is updated from the second value to a third value if two of three defective memory cells consisting of the first defective memory cell and two of the second defective memory cells including a predetermined defective memory cell have a same row address, and two of the three defective memory cells including the predetermined defective memory cell have a same column address, and wherein the error pattern information is updated from the third value to a fourth value if each of four defective memory cells consisting of the first defective memory cell and three of the second defective memory cells has either one of first and second row addresses and either one of first and second column addresses.