Patent ID: 8405436

Claim:
A multi-phase clock generator, comprising: a first delay locked loop, for generating 2 N phase clock signals according to an input clock signal, wherein N is a positive integer; a reference signal generator, for selecting an i th and an (i+1) th phase clock signals from the phase clock signals according to a digital signal, and during 2 M clock periods of the input clock signal, selecting and outputting one of the i th and the (i+1) th phase clock signals to serve as a reference clock signal according to the digital signal within each of the clock periods, wherein i and M are integer, 0≦i≦(2 N −1) and M>0; and a second delay locked loop, for delaying a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal, and outputting the output clock signal.