Patent ID: 8760937

Claim:
A semiconductor memory device comprising: a memory cell array including memory cells, which are electrically connected to a bit line; and a bit line control circuit including a first transistor which has a current path with one end electrically connected to the bit line, and the other end electrically connected to a first node, a second transistor which has a current path with one end electrically connected to the first node, and the other end electrically connected to a power supply voltage, and fixes a potential of the first node, a third transistor which has a current path with one end electrically connected to the first node, and the other end electrically connected to a second node, and fixes the potential of the first node, a fourth transistor which has a current path with one end electrically connected to the second node, and the other end electrically connected to the power supply voltage, and a charge control circuit configured to control gate voltages of the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively, wherein in a read operation which includes a sense operation, the charge control circuit controls the gate voltages of the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively, so that the bit line is charged in accordance with a first current driving capacity of the first transistor after starting to charge up the bit line, and the bit line is charged in accordance with a second current driving capacity of the first transistor before the sense operation, the second current driving capacity being lower than the first current driving capacity.