Patent ID: 8524002

Claim:
A method for producing a silicon single crystal wafer comprising a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids; a V1 region having a void density of over 2×10 4 /cm 3 and below 1×10 5 /cm 3 which occupies less than or equal to 20% of the total area of the silicon wafer; a V2 region having a void density of 5×10 2 to 2×10 4 /cm 3 which occupies 80% or more of the total area of the silicon wafer; and a bulk micro defect density which is 5×10 8 /cm 3 or more, and wherein the silicon single crystal wafer is doped with nitrogen, hydrogen and carbon; the method comprising: pulling a silicon single crystal in a pulling furnace with a crystal pulling speed and doping the silicon single crystal with nitrogen, carbon and hydrogen; controlling the nitrogen concentration in the silicon crystal to 3×10 13 to 3×10 15 atoms/cm 2 ; controlling carbon concentration in the silicon crystal to 1×10 15 to 9×10 15 atoms/cm 3 ; controlling a partial pressure of hydrogen in the crystal pulling furnace to 3 to 60 Pa; controlling a temperature gradient in a longitudinal direction of the silicon single crystal within a temperature range of 1100 to 1200° C. to 3.5° C./mm or more; controlling the crystal pulling speed to less than or equal to an upper limit value and greater than or equal to a lower limit value; and cutting a silicon wafer from the silicon single crystal, wherein the silicon wafer comprises a V1 region having a void density of over 2×10 4 /cm 3 and below 1×10 5 /cm 3 which occupies 20% of the total area of said silicon wafer if the single crystal was pulled with the upper limit value of the crystal pulling speed, and comprises a V2 region having a void density of 5×10 2 to 2×10 4 /cm 3 which occupies 80% of the total area of said silicon wafer if the single crystal was pulled with the lower limit value of the crystal pulling speed.