Patent ID: 8423983

Claim:
A computer program product comprising a non-transitory computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to: generate one or more instructions using a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), wherein the FP only SIMD ISA utilizes a vector register file that stores both scalar and floating point values as vectors in floating point vector registers, each floating point vector register having a plurality of floating point vector element slots, wherein, for scalar values being stored in the vector register file, the scalar values are each stored in a corresponding floating point vector register in a preferred vector element slot of the corresponding floating point vector register and other vector element slots of the corresponding point vector register store do-not-care values, wherein the one or more instructions include at least one vector floating point instruction supported by the FP only SIMD ISA; and output the one or more instructions for execution by one or more data processing devices.