Patent ID: 8803329

Claim:
A stacked semiconductor package, comprising: a first semiconductor package including: a first semiconductor element having a first signal terminal and a second signal terminal; and a first wiring board having the first semiconductor element mounted on one surface thereof, and having multiple lands for external connection formed on another surface thereof, the multiple lands for external connection being electrically connected to an outside, the one surface of the first wiring board having provided thereon: a first land and a second land for solder joining; a first wiring for electrically connecting the first signal terminal and the first land; and a second wiring for electrically connecting the second signal terminal and the second land; a second semiconductor package stacked on the first semiconductor package, the second semiconductor package including: a second semiconductor element; and a second wiring board having the second semiconductor element mounted on one surface thereof, and having a third land for connection and a fourth land for connection formed on another surface thereof, the third land for connection and the fourth land for connection being electrically connected to the first land for connection and the second land for connection provided on the first wiring board, respectively; and a solder joint portion for electrically connecting together the first land for connection on the first wiring board and the third land for connection on the second wiring board, and electrically connecting together the second land for connection on the first wiring board and the fourth land for connection on the second wiring board, wherein a length of the second wiring is larger than a length of the first wiring, and a surface area of the second land is larger than a surface area of the first land.