Patent ID: 8294216

Claim:
An integrated circuit structure comprising: a semiconductor substrate; a first metal-oxide semiconductor (MOS) device comprising: a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric, the first gate electrode having a top surface a first distance from a top surface of the semiconductor substrate; a second MOS device comprising: a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric, the second gate electrode having a top surface a second distance from the top surface of the semiconductor substrate, wherein the second distance is greater than the first distance, and wherein the second gate dielectric comprises a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode, the planar portion and the sidewall portions being parts of an uninterrupted component; and a contact etch stop layer (CESL) having a portion directly over the top surface of the first gate electrode.