Patent ID: 6897509

Claim:
A semiconductor device comprising: a semiconductor substrate; a capacitor element formed above the semiconductor substrate and including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film; a lower shield layer formed below the capacitor element; an upper shield layer formed above the capacitor element; a lower electrode lead-out interconnection layer formed between the capacitor element and the lower shield layer and electrically connected to the lower electrode; and an upper electrode lead-out interconnection layer formed between the capacitor element and the upper shield layer and electrically connected to the upper electrode, a plurality of holes being formed in each of the lower shield layer, the upper shield layer, the lower electrode lead-out interconnection layer and the upper electrode lead-out interconnection layer, an area of parts of the lower shield layer and the lower electrode lead-out interconnection layer, which are opposed to each other, and an area of parts of the upper shield layer and the upper electrode lead-out interconnection layer, which are opposed to each other being respectively set so that a parasitic capacity between the lower shield layer and the lower electrode lead-out interconnection layer and a parasitic capacity between the upper shield layer and the upper electrode lead-out interconnection layer being substantially equal to each other.