Patent ID: 7026883

Claim:
An apparatus, comprising: an inductor capacitor (LC) tank; a drive circuit including a first generator, coupled to the LC tank, to drive the LC tank, and a current source, coupled to the first generator, to provide a source current to the first generator; a feedback loop circuit including a peak detect circuit, coupled to the LC tank, to generate a peak detect voltage signal representing an oscillation amplitude of the LC tank; a reference voltage generator to generate a single reference voltage; and an operational amplifier, with a pair of input terminals coupled to the peak detect circuit and the reference voltage generator and an output terminal coupled to the current source, to compare the peak detect voltage signal and the single reference voltage signal and to generate an analog bias signal in response to a difference between the peak detect voltage signal and the single reference voltage, with the current source being adapted to adjust a magnitude of me source current in response to the analog bias signal; the LC tank further including a first tank terminal and a second tank terminal; the first generator including a negative resistance generated having a first and a second drive transistor coupled to the first and second tank terminals; the first and second drive transistors having a pair of commonly coupled terminals; the current source including a single current source transistor coupled to the commonly coupled terminals to provide the source current to the first and second drive transistors; the peak detect circuit including a first detect transistor coupled to the first tank terminal; a second detect transistor coupled to the second tank terminal and the first detect transistor; and a detect current source commonly coupled to the first and second detect transistors; the reference voltage circuit including a first reference transistor operable to receive a reference bias signal; a second reference transistor coupled the first reference transistor and operable to receive the reference bias signal; and a reference current source commonly coupled to the first and second reference transistors; and the first detect and first reference transistors being identical in design; the second detect and second reference transistors being identical in design; and the detect and reference current sources being identical in design.