Patent ID: 7332904

Claim:
An apparatus for adjusting an on-chip resistance with an off-chip resistor, comprising: a sense circuit that includes a variable resistance circuit, wherein the sense circuit is arranged to generate a first voltage across the variable resistance circuit, to generate a second voltage across the off-chip resistor, and to compare the first voltage to the second voltage to provide a status signal; an up/down counter circuit that is arranged to provide a counter signal in response to an evaluation of the status signal, wherein the variable resistance circuit of the sense circuit has a first resistance value that is adjusted in response to the counter signal; an adjusted resistance circuit that has a second resistance value that is adjusted in response to the counter signal, the adjusted resistance circuit comprising: a first resistor that is coupled between a first node and a feedback node; a second resistor that is coupled between the feedback node and a second node, wherein the first resistor and the second resistor have matched resistance values; a third resistor that is coupled between the first node and a third node; a fourth resistor that is coupled between a fourth node and the second node, wherein the third resistor and the fourth resistor have matched resistance values; and a transistor that is arranged to selectably couple the third node to the fourth node in response to a control signal, whereby the selective coupling of the first and second resistors in parallel with the third and fourth resistors provides an adjustment of a resistance value associated with the adjustable resistance circuit.