Patent ID: 8594091

Claim:
An interconnection switch for enabling a first plurality of network elements (NEs) operating at a bit rate R 1 to communicate with a second plurality of NEs operating at a bit rate R 2 via transceivers operating at the bit rate R 2 , wherein a ratio of R 2 to R 1 is represented by a ratio M:N, M and N are positive integers, the ratio M:N is non-integer, and M>N, the interconnection switch comprising: a controller; and a switching/routing unit operatively controlled by the controller to interconnect electrical lanes of a number M×K NEs of the first plurality of NEs with electrical interfaces of a number N×K of the transceivers so as to bypass communication interfaces of the M×K NEs and to enable use of at least one of the N×K transceivers to communicate data between at least one of the M×K NEs and at least one of the second plurality of NEs, wherein K is a positive integer.