Patent ID: 7652362

Claim:
A package stack comprising: at least two packages stacked one on top of the other, each package comprising: a substrate having a circuit pattern that extends a predetermined portion on a side surface of the substrate; a semiconductor chip attached and electrically connected to the substrate; and a number of through-vias formed in predetermined portions of the side surface of the package adjacent to the substrate and exposed to the outside, the lateral thickness of the respective through-vias extending from the side surface of the package to the substrate so as to expose the circuit pattern formed on the side surface of the substrate, wherein each through-via of one package is aligned with a corresponding through-via of the other stacked package to form a continues through-via on the side surfaces of the two stacked packages; a number of electrical connection members, each of which is attached to each continous through-via on the side surface of the two stacked packages so as to electrically connect the two packages to each other, each continuous through-vias being vertically positioned on a predetermined portion of the side surface of the stacked packages, wherein the connection members are electrically connected to the circuit pattern exposed by the through-vias; and a solder ball attached to a lower surface of the substrate of the lowest package.