Patent ID: 7855397

Claim:
An electronic assembly comprising: a packaging substrate having opposing first and second surfaces; an integrated circuit (IC) semiconductor chip having an active side including input/output pads thereon and a back side opposite the active side, wherein the IC semiconductor chip is arranged with the active side facing the first surface of the packaging substrate; a plurality of metal interconnection structures between the active side of the IC semiconductor chip and the first surface of the packaging substrate, wherein the plurality of metal interconnection structures provide mechanical connection between the active side of the IC semiconductor chip and the first surface of the packaging substrate; and a thermoelectric heat pump coupled to the packaging substrate, wherein the thermoelectric heat pump is configured to actively pump heat between the IC semiconductor chip and the packaging substrate, wherein the thermoelectric heat pump is between the packaging substrate and the IC semiconductor chip, wherein the thermoelectric heat pump comprises an n-type thermoelectric element electrically coupled to a first one of the metal interconnection structures and a p-type thermoelectric element electrically coupled to a second one of the metal interconnection structures, wherein the IC semiconductor chip includes an electrically conductive coupling between the first and second metal interconnection structures so that the n-type and p-type thermoelectric elements and the first and second metal interconnection structures are electrically coupled in series, wherein the n-type and p-type thermoelectric elements are thermally coupled in parallel between the IC semiconductor chip and the packaging substrate, wherein a third one of the metal interconnection structures is electrically coupled between an electronic circuit of the IC semiconductor chip and an electrically conductive trace of the packaging substrate, wherein the third metal interconnection structure is free of thermoelectric material, and wherein each of the first, second, and third metal interconnection structures includes a copper pillar and a solder material; wherein the packaging substrate includes a thermally conductive via between the first and second surfaces thereof, and wherein the thermally conductive via, and the first metal interconnection structure are thermally coupled in series between the active side of the IC semiconductor chip and the second surface of the packaging substrate; wherein the thermally conductive via is adjacent the first metal interconnection structure and spaced apart from the second metal interconnection structure in a direction that is parallel with respect to a surface of the packaging substrate.