Patent ID: 7037850

Claim:
A method for fabricating a semiconductor device, comprising: forming a hard mask insulation layer on an etch target layer; forming a hard mask sacrificial layer on the hard mask insulation layer; coating a photoresist on the hard mask insulation layer; selectively performing a photo-exposure process and a developing process to form a photoresist pattern having a first width for forming a line pattern; selectively etching the hard mask sacrificial layer by using the photoresist pattern as an etch mask to form a sacrificial hard mask having a second width; removing the photoresist pattern; etching the hard mask insulation layer by controlling excessive etching conditions with use of the sacrificial hard mask as an etch mask to form a hard mask having a third width; and etching the etch target layer by using the sacrificial hard mask and the hard mask as an etch mask to form the line pattern having a fourth width, wherein magnitudes of the first width to the fourth width are in a descending order of the first width, the second width, the third width and the fourth width.