Patent ID: 6988258

Claim:
A mask-programmable logic device comprising: an array of programmable logic sub-units, each of said programmable logic sub-units comprising: a plurality of intelligent macrocells and a plurality of gate arrays, each of said intelligent macrocells and said gate arrays having contacts for connection to an interconnect structure for connecting said programmable logic sub-units into a plurality of programmable logic device logic units and configuring said plurality of programmable logic device logic units to perform one or more logic functions, each of said intelligent macrocells including a plurality of unconnected components adapted to be connected to one another to create logic; wherein: said plurality of unconnected components in each of said intelligent macrocells comprises: a first plurality of inverters; a second plurality of NAND gates; and a third plurality of CMOS transmission pairs; wherein: each of said inverters, said NAND gates and said CMOS transmission pairs is adapted to be connected to others of said inverters, said NAND gates and said CMOS transmission pairs, and to components outside their respective intelligent macrocells, by programming metallization layers.