Patent ID: 8482991

Claim:
A semiconductor memory device, comprising: data terminals which receive data; input buffers each of which is coupled to a corresponding one the data terminals; memory banks, each of which includes a plurality of memory cells, to store data received via the data terminals; a clock terminal which receives a clock signal; and a strobe terminal which receives a data strobe signal, the data being inputted via the data terminals in synchronism with both rising and falling edges of the data strobe signal, wherein the input buffers are changed from an inactive state to an active state after the semiconductor device receives a write instruction for storing data to one of the memory banks, and are changed from the active state to the inactive state after elapse of a predetermined time period, wherein a respective through current of each input buffer is smaller in the inactive state than in the active state, wherein the predetermined time period is synchronized with the clock signal and wherein each of the input buffers includes a differential buffer having a power switch, and is changed to the active state by turning on the power switch and changed to the inactive state by turning off the power switch.