Patent ID: 7644327

Claim:
A method of providing error correction in an integrated circuit (IC) to enable the replacement of a defective logic function implemented within the IC, the method comprising: providing an embedded field programmable gate array (FPGA) in the IC to perform logic error correction; identifying a defective logic function within the IC; programming the embedded FPGA to replace the defective logic function; identifying all inputs in an input cone of logic of the defective logic function; directing all inputs in the input cone of logic of the defective logic function into the embedded FPGA, such that the embedded FPGA replaces the defective logic function with an error corrected version of the defective logic function; identifying all outputs in an output cone of logic of the defective logic function; directing an output of the FPGA to the output cone of logic of the defective logic function, such that logic error correction is provided within the embedded FPGA structure of the IC; and, evaluating error recovery of the IC chip design, wherein data errors are injected through the embedded FPGA into the IC chip, and then the logic function IC design is evaluated as to how well it handles error recovery.