Patent ID: 8000068

Claim:
An integrated circuit comprising: an analog signal input conductor; a first ground conductor; a first electrostatic discharge (ESD) protection circuit coupled to conduct a first ESD current between the first ground conductor and the analog signal input conductor; a transistor having a gate, a source, a drain, and a body, wherein the gate is coupled to receive an analog signal from the analog signal input conductor; a degeneration inductor having a first lead and a second lead, wherein the first lead is coupled to the source of the transistor; and a second ESD protection circuit coupled to conduct a second ESD current between the first ground conductor and the body of the transistor; wherein the second ESD protection circuit includes a diode having an anode coupled to the first ground conductor and having a cathode coupled to the body of the transistor, wherein the second ESD protection circuit further comprises a second diode, the second diode having a cathode coupled to the first ground conductor and having an anode coupled to the second lead of the degeneration inductor.