Patent ID: 7700397

Claim:
A process for packaging components, comprising: permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate, the back surface being on the opposite side of the base substrate from the functional side; dividing the base substrate into body regions and connection regions, the body regions in each case extending over the functional regions and forming part of the packages for the functional regions, and the connection regions being offset with respect to the contact-connection recesses; thinning the base substrate in the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined culling lines between the plurality of functional regions.