Patent ID: 7459266

Claim:
A method of fabricating a memory cell, comprising: forming a first electrode layer including a first electrically conductive material, forming an insulating layer, and forming a stencil layer having an opening, in that order, on a substrate; etching said insulating layer through said opening in said stencil layer, to expose a surface of said first electrode layer; depositing a second electrically conductive material through said opening in said stencil layer onto said surface of said first electrode layer; depositing a phase-change material layer through said opening in said stencil layer onto said second electrically conductive material; and depositing a third electrically conductive material to form a second electrode layer and a pillar structure through said opening on said phase-change material layer, using a spread-angle for deposition which is greater than a spread-angle for deposition for said phase-change material, such that said phase-change material layer is surrounded by said second and third electrically conductive materials, wherein said etching said insulating layer comprises undercut etching in which a portion of said insulating layer underneath said stencil layer is etched, such that an opening is formed in said insulating layer which has a larger diameter than said opening in said stencil layer, wherein said third electrically conductive material is deposited using a deposition beam having a spread-angle for deposition which is greater than the spread-angle for deposition for said phase-change material layer by using one of different deposition conditions, and different deposition techniques to form said phase-change material layer and said pillar structure, and wherein said depositing said phase-change material layer comprises directionally depositing said phase-change material layer, such that said phase-change material layer is deposited off center from said opening in said stencil layer.