Patent ID: 7652290

Claim:
A short DC standby current erasion circuit of a DRAM, comprising: a block detection circuit for enabling a short circuit control signal when a short circuit between bit lines and word lines of said DRAM is detected, wherein a selection line input to said block detection circuit is set to one when a short circuit is detected and is set to zero when a short circuit is not detected; and a word line driving circuit connected to said block detection circuit, said word line driving circuit setting a voltage level of the word line occurring a short circuit as a voltage level of the corresponding bit line occurring a short circuit during substantially the entire duration of a standby mode if said short circuit control signal is enabled, wherein when the selection line is zero, an output signal of said block detection circuit is equal to an input signal of said block detection circuit, and when the selection line is one, said block detection circuit inverts the input signal to obtain the output signal, such that the output signal functions as the short circuit control signal.