Patent ID: 7879720

Claim:
A method of forming an electrical interconnect, comprising: forming a copper pattern on a semiconductor substrate; forming an electrically insulating capping layer on the copper pattern; forming an interlayer insulating layer on the electrically insulating capping layer; forming a contact hole that extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern; and electroless plating a copper pattern extension onto the exposed upper surface of the copper pattern; wherein a portion of the interlayer insulating layer extending adjacent the electrically insulating capping layer has a nonuniform composition; wherein forming a contact hole comprises forming a contact hole having a non-uniform width therein with a constricted neck at an interface between the electrically insulating capping layer and the interlayer insulating layer; and wherein a minimum width of the non-uniformly wide contact hole in the electrically insulating capping layer is at the interface.