Patent ID: 8370726

Claim:
A soft output Viterbi algorithm (SOVA) decoder arranged to decode received symbols, the SOVA decoder comprising: a reliability memory unit (RMU) comprising: a plurality of RMU stages, at least some of the plurality of RMU stages comprising a plurality of logic units, the plurality of logic units of at least one RMU stage being coupled to the plurality of logic units of a subsequent RMU stage, the RMU being arranged to generate, at an output of a final RMU stage of the plurality of RMU stages, a first reliability value corresponding to a decoded data value of at least one of the received symbols, each of the plurality of logic units comprising circuitry configured to determine a second reliability value and a buffer for storing the second reliability value, the plurality of RMU stages comprising: a plurality of full RMU stages configured to be controlled based on a first set of symbols of the received symbols; and a plurality of compact RMU stages configured to be controlled based on at least one symbol received prior to the first set of symbols, each compact RMU stage comprising half or less than half a number of logic units in each full RMU stage.