Patent ID: 8217466

Claim:
A semiconductor device comprising: a semiconductor layer formed on a part of an insulating layer, said semiconductor layer having a first side surface and a second side surface, a first conductive type impurity region, a second conductive type first source region, a second conductive type second source region, a second conductive type first drain region and a second conductive type second drain region; a first gate insulating film and a second gate insulating film, respectively formed along a first portion of said first side surface and a first portion of said second side surface so as to face each other through said first conductive type impurity region; and a first gate electrode and a second gate electrode, respectively formed along said first gate insulating film and said second gate insulating film, wherein, said second conductive type first and second source regions are respectively formed on both sides of said first conductive type impurity region and are respectively formed along a second portion of said first side surface and a second portion of said second side surface so as to face each other through said first conductive type impurity region, said second conductive type first and second drain regions are respectively formed on both sides of said first conductive type impurity region and are respectively formed along a third portion of said first side surface and a third portion of said second side surface so as to face each other through said first conductive type impurity region, said first portion of said first side surface is positioned between said second portion and said third portion of said first side surface, said first gate insulating film, said first gate electrode, said first source region, and said first drain region constitute a first transistor, said first portion of said second side surface is positioned between said second portion and said third portion of said second side surface, said second gate insulating film, said second gate electrode, said second source region, and said second drain region constitute a second transistor, said first source region and said first drain region connect with a first node as a source electrode and a drain electrode of said first transistor, respectively, said second source region connects to said first node as a source electrode of said second transistor, said second drain region connects to a second node as a drain electrode of said second transistor, and electric charges that have accumulated in a channel region of said first transistor and electric charges that have accumulated in a channel region of said second transistor are exchanged in correspondence with the first transistor and the second transistor being switched to an inverse direction simultaneously with each other.