Patent ID: 7532242

Claim:
A circuit comprising a first and a second stage, the first stage comprising a first integrator having a first input for receiving a signal from a first detecting element, the first stage further comprising a first reset switch having an output coupled to a second input of the first integrator and an input coupled to a source of fixed bias voltage; and the second stage comprising a second reset switch and a second integrator, wherein the second reset switch has an input coupled to an output of the first integrator, and the second integrator has a first input for receiving a signal from a second detecting element and a second input coupled to an output of the second reset switch, wherein the second reset switch resets the second integrator to a voltage resulting from integration at the first integrator, wherein the first stage further comprises a first bi-directional control switch disposed between the source of fixed bias voltage and the first reset switch for coupling the first reset switch alternatively to the source of fixed bias voltage and an output of the second integrator.