Patent ID: 7830706

Claim:
A semiconductor device comprising: a first memory cell provided in a first layer and having a first memory element to which memory information is written by a current; a second memory cell provided in a second layer, which is formed above the first layer, and having a second memory element to which memory information is written by a current; a first address decoder which outputs a first layer select signal for selecting the first layer or a second layer select signal for selecting the second layer; and a write driver which supplies a first current to the first memory cell when first memory information is to be written to the first memory cell, and supplies a second current, which has a magnitude different from that of the first current, to the second memory cell when the first memory information is to be written to the second memory cell, wherein the write driver controls the magnitudes of the first current and the second current according to the first layer select signal and the second layer select signal.