Patent ID: 7908744

Claim:
A method for fabricating a printed circuit board having capacitance components, comprising the steps of: providing a core board, a carrier board, and a second dielectric layer, the core board having a first surface with a first wiring layer thereon and an opposed second surface with a second wiring layer thereon, the first and second wiring layers being electrically connected, the carrier board being sequentially provided thereon with a second metal layer, a high dielectric material layer, and a third wiring layer, the third wiring layer being provided with a plurality of first electrode plates; laminating the core board, the second dielectric layer, and the carrier board to one another so as for the second dielectric layer to be sandwiched between the core board and the carrier board and laminated to the second surface of the core board and the second wiring layer thereon, wherein laminating the high dielectric material layer to the second dielectric layer allows the third wiring layer to be laminated to the second dielectric layer; removing the carrier board so as to expose the second metal layer; and patterning the second metal layer so as to form a fifth wiring layer having a plurality of second electrode plates and a plurality of second conductive vias electrically connected to the third wiring layer, thereby allowing the first electrode plates of the third wiring layer, the high dielectric material layer, and the second electrode plates of the fifth wiring layer together to form a plurality of capacitance components.