Patent ID: 8130587

Claim:
A hardware arrangement for a memory bitcell, comprising: a primary decoder configured to decode a common memory address portion among a plurality of memory addresses to obtain a decoded common memory address portion; a plurality of secondary decoders each configured to decode an uncommon memory address portion of each of the plurality of memory addresses to obtain a plurality of decoded uncommon memory address portions; the memory bitcell configured to receive the decoded common memory address portion and output data from a memory entry corresponding to the decoded common memory address portion, wherein the memory bitcell comprises a single read port for outputting the data; and a modified sense amplifier (SA) configured to: receive the data output on the single read port of the memory bitcell, and directly receive the plurality of decoded uncommon memory address portions, wherein the plurality of decoded uncommon memory address portions is used to determine whether to enable the modified SA, wherein the data output from the memory bitcell is forwarded by the modified SA when the modified SA is enabled.