Patent ID: 7259060

Claim:
Method for fabricating a semiconductor structure having a plurality of memory cells which are provided in a semiconductor substrate (l) of a first conduction type (p) and comprise a plurality of planar selection transistors and a corresponding plurality of storage capacitors (TK 1 -TK 4 ; TK 1 ′-TK 4 ′) connected thereto, the selection transistors having respective first and second active regions ( 60 , 61 ; 62 , 61 ; 63 , 64 ; 65 , 64 ; 60 ′, 61 ′; 62 ′, 63 ′; 64 ′, 65 ′; 66 ′, 67 ′) of the second conduction type (n), of which the first active regions ( 60 , 62 , 63 , 65 ) are connected to the storage capacitors (TK 1 -TK 4 ; TKl′-TK 4 ′) and the second active regions ( 61 , 64 , 6 l′, 63 ′, 65 ′, 67 ′) are connected to respective bit lines, and respective gate stacks (GS 1 -GS 8 ), which are provided above the semiconductor substrate ( 1 ) in a manner insulated by a gate dielectric ( 5 ), having the following steps: providing the storage capacitors (TK 1 -TK 4 ; TK 1 ′-TK 4 ′) in the semiconductor substrate ( 1 ); providing the gate dielectric ( 5 ) above the semiconductor substrate ( 1 ); providing the gate stacks (GS 1 -GS 8 ) on the gate dielectric ( 5 ) carrying out a first introduction step (I 1 , I 2 ; I 1 ″) for introducing first doping regions ( 100 , 105 , 110 , 120 , 130 ; 105 ″, 110 ″, 120 ″, 130 ″, 140 ″) of the first conduction type (p) in a self-aligned manner with respect to edges of the gate stacks (GS 1 -GS 8 ) on the side of the second active regions ( 61 , 64 , 61 ′, 63 ′, 65 ′, 67 ′) for the purpose of increasing the doping of a channel region of the selection transistors which is spaced apart from the first active regions ( 60 , 62 , 63 , 65 ); carrying out a second introduction step (I 1 ′, I 2 ′; I 1 ′″) for introducing second doping regions ( 101 , 106 , 111 , 121 , 131 ; 106 ″, 111 ″, 121 ″, 131 ″, 141 ″), which counteract a thermal outdiffusion of the first doping regions ( 100 , 105 , 110 , 120 , 130 ; 105 ″, 110 ″, 120 ″, 130 ″, 140 ″) in the direction of the first active regions ( 60 , 62 , 63 , 65 ); providing the first and second active regions ( 60 , 61 ; 62 , 61 ; 63 , 64 ; 65 , 64 ; 60 ′, 61 ′; 62 ′, 63 ′; 64 ′, 65 ′; 66 ′, 67 ′) in a self-aligned manner with respect to edges of the gate stacks (GS 1 -GS 8 ).