Patent ID: 8410599

Claim:
A power MOSFET package, comprising: a semiconductor substrate having a first surface and an opposite second surface, wherein the semiconductor substrate has a first conductivity type and forms a drain region; a doped region extending downward from the first surface, the doped region having a second conductivity type; a source region located in the doped region, the source region having the first conductivity type; a gate formed overlying the first surface or buried under the first surface, wherein a gate dielectric layer is located between the gate and the semiconductor substrate; a first trench extending from a first side surface of the semiconductor substrate toward an inner portion of the semiconductor substrate and extending from the first surface toward the second surface; a first conducting layer located overlying a sidewall of the first trench, wherein the first conducting layer is not coplanar with the first side surface and is separated from the first side surface by a first minimum distance, the first conducting layer electrically is connected to the source region; a first insulating layer located between the first conducting layer and the semiconductor substrate; a second trench extending from a second side surface of the semiconductor substrate toward the inner portion of the semiconductor substrate and extending from the first surface toward the second surface; a second conducting layer located overlying a sidewall of the second trench, wherein the second conducting layer is not coplanar with the second side surface and separated from the second side surface by a second minimum distance, the second conducting layer electrically connected to the drain region; a second insulating layer located between the second conducting layer and the semiconductor substrate; a third trench extending from a third side surface of the semiconductor substrate toward the inner portion of the semiconductor substrate and extending from the first surface toward the second surface; a third conducting layer located overlying a sidewall of the third trench, wherein the third conducting layer is not coplanar with the third side surface and separated from the third side surface by a third minimum distance, the third conducting layer electrically connected to the gate; and a third insulating layer located between the third conducting layer and the semiconductor substrate.