Patent ID: 7821428

Claim:
An integrated circuit, comprising: a first microcontroller unit disposed on a first die for executing instructions in accordance with a first clock frequency generated on the first die, the first microcontroller unit including a first processing core for generating parallel data in accordance with the first clock frequency; first transceiver circuitry located on the first die for converting between the parallel data and a serial data stream in accordance with a second clock frequency generated on the first die that is faster than the first clock frequency; a second microcontroller unit disposed on a second die for executing instructions in accordance with a third clock frequency generated on the second die, the second microcontroller unit including a second processing core for processing parallel data in accordance with the third clock frequency; second transceiver circuitry located on the second die for converting between a serial data stream and parallel data in accordance with a fourth clock frequency generated on the second die that is faster than the third clock frequency; the first die galvanically isolated from the first die; and isolation circuitry for transmitting serial data from the first transceiver to the second transceiver across a galvanic isolation barrier such that parallel data processed by the first microcontroller unit can be received by the second microcontroller unit with the transmission across the galvanic isolation link being a serial data stream, and the first and second clock frequencies generated on the first die not synchronized with the third and fourth clock frequencies generated on the second die.