Patent ID: 8729882

Claim:
A circuit, comprising: a capacitance circuit coupled between a first node and a second node; a regulator circuit coupled to the capacitance circuit to regulate a supply voltage across the capacitance circuit with a charge current during a normal operation mode of the circuit; a slew rate control circuit coupled to the capacitance circuit and the regulator circuit, the slew rate control circuit coupled to lower a slew rate of a change in voltage over change in time between the first and second nodes during a power up mode of the circuit, wherein the slew rate control circuit includes a transistor coupled between the first and second nodes to shunt excess current that is not used to charge the capacitance circuit from the charge current, wherein the slew rate control circuit further includes a resistor coupled to the capacitance circuit, wherein a voltage drop across the resistor is limited to a base-emitter voltage drop of the transistor to lower the slew rate.