Patent ID: 7181662

Claim:
An on-chip test apparatus comprising: a first and a second data latch fabricated on-chip, each of said first and second data latches having a respective input and a respective output; a test structure fabricated on-chip; and a selective coupling means for selectively coupling the output of the first data latch to the input of the second data latch either directly or through the test structure, the selective coupling means including a first multiplexer having a pair of first mux inputs and a first mux output, and a second multiplexer having a pair of second mux inputs and a second mux output, one of said pair of first mux inputs coupled to the first data latch output, the first mux output coupled to an input of the test structure and one of said pair of second mux inputs, the other of said pair of second mux inputs coupled to an output of the test structure, the second mux output coupled to the second data latch input.