Patent ID: 6898120

Claim:
A nonvolatile semiconductor memory device comprising a memory cell array including a plurality of memory cells disposed in a row direction and a column direction, wherein each of the memory cells includes a source region, a drain region, a channel region between the source region and the drain region, a word gate, a select gate, and a nonvolatile memory element formed between the word gate and the channel region, the word gate and the select gate being disposed to face the channel region, wherein the memory cell array includes: a plurality of word lines each of which is commonly connected with the word gates of the memory cells in each row; a plurality of bit lines each of which is commonly connected with the drain regions or the source regions of the memory cells in each column; a word line driver section which drives the word lines; and a bit line driver section which drives the bit lines, wherein the word line driver section includes a plurality of unit word line driver sections, and wherein each of the unit word line driver sections drives two of the word lines connected respectively with two of the word gates adjacent to each other in the column direction.