Patent ID: 7667291

Claim:
A field programmable gate array (FPGA) structure of a semiconductor device comprising first and second metal wiring layers stacked one upon another with an inter-metal dielectric layer (IMD) interposed therebetween, the FPGA structure comprising: a pair of first vias connecting a pair of first metal wiring portions in the first metal wiring layer to a pair of corresponding second metal wiring portions in the second metal wiring layer, respectively; a first pattern having a voltage selectable conductivity and connecting the first vias; a second pattern having a voltage selectable conductivity formed on another second metal wiring portion which is not one of the second metal wiring portions corresponding to the first metal wiring portions; and a pair of second vias connecting the first and second patterns to respective third metal wiring portions of the third metal wiring layer, respectively, wherein a thickness of the first pattern is thicker than that of the second pattern.