Patent ID: 8842479

Claim:
A memory comprising: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by: applying a switching voltage to a word line and corresponding memory cell other than the selected word line and selected memory cell, the switching voltage having a first voltage level during a first time interval which blocks current flow through the corresponding memory cell, and thereafter changing to a second voltage level to enable current flow through the corresponding memory cell during a second time interval; during the first time interval, biasing one of first and second ends of the plurality of memory cells to a drain side voltage, while floating another of the first and second ends; during the first time interval, applying drain-side pass voltages to word lines between the selected word line and said one of first and second ends; during the first time interval, applying source-side pass voltages to word lines between the selected word line and said other of first and second ends; during the second time interval, applying a program voltage to the selected word line and connecting said other of the first and second ends to a source side voltage inducing current flow through the plurality of memory cells, and causing hot carrier injection in the selected memory cell.