Patent ID: 8108749

Claim:
An iterative decoder circuit operative to provide an output signal in response to a received signal, comprising: an N number of sub-decoders, N−1 of the sub-decoders each responsive to a baseband signal from one of M number of signal processing circuits, M being an integer number, where M ranges from 1 to N−1; and N being an integer number, each of the N−1 number of sub-decoders including, an inner delay responsive to a baseband signal provided by a corresponding signal processing circuit and operative to generate an inner delayed signal, a modified decoder responsive to the inner delayed signal and operative to generate a set partition signal, the set partition signal of some of the N number of modified decoders having less errors than previous set partition signals, an Nth inner delay responsive to the baseband signal provided by an Nth signal processing circuit and operative to provide an Nth inner delayed signal, an Nth modified decoder responsive to the Nth inner delayed signal and to the set partition signal and operative to provide an output signal, wherein the probability of error of the output signal is reduced by correcting errors in some of the set partition signals.