Patent ID: 7612703

Claim:
A sub-converter stage for a pipelined analog-to-digital converter, comprising: an amplifier with a dc gain A; a sub analog-to-digital converter with comparators and a digital unit; a first capacitor with capacitance 2 C, the first capacitor is selectively connected between an analog input node and an input of the amplifier or between a corresponding plurality of digital reference signals and the input of the amplifier; a second capacitor with capacitance C−ΔC, wherein ΔC is the capacitance mismatch, the second capacitor is selectively connected between a dc voltage and the input of the amplifier or between the input of the amplifier and an output of the amplifier; the dc gain A of the amplifier satisfies with an equation Δ ⁢ ⁢ C C = 3 A + 1 ; wherein during a sampling phase, the first capacitor is connected between the analog input node and the input of the amplifier and the second capacitor is connected between a dc voltage and said the input of the amplifier, and during a holding phase, the first capacitor is connected between a corresponding plurality of digital reference signals and the input of the amplifier input and the second capacitor is connected between said the input of the amplifier and the output of the amplifier.