Patent ID: 7202120

Claim:
A method of fabricating a semiconductor integrated circuit device, comprising the steps of: forming an n-channel MOS transistor having a first gate electrode and a p-channel MOS transistor having a second gate electrode respectively on first and second device regions defined on a substrate by a device isolation region; forming a stressor film accumulating therein a tensile stress on said substrate so as to cover said first and second device regions continuously including said first gate electrode and sidewall insulation films thereon and said second gate electrode and sidewall insulation films thereon; and introducing, in said second device region, an element causing relaxation of said tensile stress into said stressor film obliquely by an ion implantation process such that said stressor film undergoes stress relaxation in said second device region, said ion implantation process being conducted such an energy that said element reaches said sidewall insulation film of said second gate electrode at least in the vicinity of a base part of said second gate electrode, said method further comprising, after said ion implantation step, a step of etching said stressor film in said second device region, such that said stressor film is removed in the vicinity of said second gate electrode.