Patent ID: 7319066

Claim:
A method for fabricating a semiconductor device comprising the steps of: forming a gate electrode on one surface of a semiconductor substrate with a gate insulation film formed therebetween; forming a source/drain region in the semiconductor substrate on both sides of the gate electrode; forming a contact plug electrically connected to the semiconductor substrate; forming a first insulation film on said one surface of the semiconductor substrate, the first insulation film including multiple insulation films; and forming a multilayer interconnection buried in the first insulation film, the multilayer interconnection including multiple interconnection layers, said multiple interconnection layers being buried in said multiple insulation films, respectively; the method further comprising before the step of forming the first insulation film, the step of forming a second insulation film on the other surface of the substrate, having a stress relaxing a stress exerted by the first insulation film to the substrate, wherein in the step of forming the second insulation film, a third insulation film is formed on said one surface of the substrate, the third insulation film being used as a mask for etching the substrate.