Patent ID: 8653639

Claim:
A layered chip package comprising a main body and wiring, wherein: the main body has a main part, the main part having a top surface and a bottom surface and including a plurality of layer portions that are stacked; the wiring includes a plurality of lines that pass through all the plurality of layer portions; each of the plurality of layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface, and a second surface opposite to the first surface; the plurality of electrodes are disposed on a side of the first surface of the semiconductor chip; the plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first surfaces or the second surfaces of the respective semiconductor chips face each other; the plurality of electrodes are arranged in the same layout in the first and second layer portions; the plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts; in the first layer portion, the plurality of first connection parts are in contact with the plurality of lines; and in the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.