Patent ID: 8878792

Claim:
A clock and data recovery (CDR) circuit of a source driver, comprising: a clock recovery unit configured to receive data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and to generate a clock signal by detecting an edge of the clock code; and a delay locked loop unit configured to generate a multi-phase clock signal based on the clock signal in the display data mode, wherein the delay locked loop unit includes, a delay line configured to delay the clock signal to generate a delayed clock signal, the delay line including a plurality of delay cells, the plurality of delay cells outputting the multi-phase clock signal by sequentially delaying the clock signal, a phase-frequency detector configured to generate an up signal and a down signal based on a phase difference between the clock signal and the delayed clock signal, a control signal generator configured to generate a delay control signal for controlling a delay time of the delay line in response to the up signal and the down signal, a lock detector configured to generate a lock signal indicating whether the delay locked loop unit is locked based on the up signal and the down signal, and a clock window generator configured to generate a clock window signal by performing a logical operation on the multi-phase clock signal.