Patent ID: 7995410

Claim:
An integrated circuit comprising: a plurality of memory cells coupled to a pair of bit lines, wherein the plurality of memory cells are powered by a first power supply voltage during use; a bit line precharge circuit coupled to the pair of bit lines and powered by the first power supply voltage during use, wherein the bit line precharge circuit is coupled to receive a precharge enable signal and is configured to precharge the pair of bit lines responsive to an enabled level on the precharge enable signal; and a level shifter coupled to the bit line precharge circuit to provide the precharge enable signal, wherein the level shifter is configured to level shift an input precharge enable signal from a second voltage domain corresponding to a second power supply voltage different from the first power supply voltage to generate the precharge enable signal, and wherein the level shifter is further configured to drive a disabled level on the precharge enable signal to disable the bit line precharge circuit during times that the memory array is idle.