Patent ID: 8027219

Claim:
A method for equalizing access times for accessing memory cells within a memory cell regardless of a position of the memory cells, the method comprising: providing a decoding signal to the memory cell array through a first path without delay when the decoding signal is a signal for accessing a memory cell within a first cell array block of the memory cell array, where a path length from between the first cell array block and a decoder is longer than a path length between a second cell array block of the memory cell array and the decoder; and providing the decoding signal to the memory cell array through a second path with delay when the decoding signal is a signal for accessing a memory cell within the second cell array block; selecting at least one of at least one row and at least one column associated with the at least one memory cell of at least one of the first and second cell array blocks, wherein the providing the decoding signals to the memory cell array through the first and second paths includes: controlling a delay of an activation signal applied to the at least one of row and column by the decoder in response to a block control signal based on at least one of a position of the at least one memory cell associated with the selected at least of one of row and column and a line loading capacitance value of the selected memory cell, and wherein the controlling equalizes access times for accessing memory cells regardless of a position of the memory cells within the memory cell array.