Patent ID: 8291306

Claim:
An (n, k) cyclic code encoder (the Encoder), comprising: an input symbol signal configured to receive message symbols from an external host; a symbol counter unit configured to output a position of the codeword symbol being input, wherein the symbol counter unit may be loaded with a value by an external host and decremented for each symbol being input; a base parity unit coupled to the input symbol signal and configured to perform systematic encoding based on said (n, k) cyclic code, wherein the base parity unit may be initialized by a reset mechanism such as an input reset signal, wherein the base parity unit computes parity for each data fragment received via the input symbol signal, wherein the parity computed by the base parity unit is the base parity; a fragment parity unit coupled to the base parity unit and the symbol counter unit and configured to perform systematic encoding based on said (n, k) cyclic code, wherein the fragment parity unit computes parity for each base parity mathematically shifted to the symbol position indicated by the symbol counter unit, wherein the parity computed by the fragment parity unit is the fragment parity; a codeword parity unit coupled to the fragment parity unit and configured to perform vector sum of the fragment parities, wherein the vector sum computed by the codeword parity unit is the codeword parity; and an output symbol signal configured to output the codeword parity as the output of the Encoder.