Patent ID: 7379318

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate including an SRAM region and a ROM region; a plurality of SRAM memory cells, each of which is formed in the SRAM region and includes a flip-flop, a pair of access transistors of a first conductive type connected to the flip-flop and a pair of SRAM bit lines connected to the pair of access transistors, respectively; and a plurality of ROM memory cells, each of which is formed in the ROM region and includes a ROM transistor of the first conductive type and a ROM bit line connected to the ROM transistor, wherein a number of the SRAM memory cells connected to each pair of SRAM bit lines is smaller than a number of the ROM memory cells connected to the ROM bit line, the ROM transistor has a larger channel width than the access transistors, and the ROM transistor is implanted with impurities having substantially the same concentration as impurities implanted in the pair of access transistors of the SRAM memory cells, and wherein the semiconductor substrate further includes a ROM column switch region having a ROM column switch comprising a switching transistor of the first conductive type connected to the ROM bit line, and the switching transistor is implanted with second conductivity type impurities at a concentration different from the concentration of the ROM transistor so that the absolute value of the threshold voltage thereof is reduced.