Patent ID: 7939828

Claim:
A pixel structure, comprising: a substrate having a pixel area thereon; a patterned stacked layer disposed on the substrate, the patterned stacked layer comprising a transistor pattern, a lower capacitance pattern and a lower circuit pattern, wherein the transistor pattern and the lower capacitance pattern comprise a first metal layer, a gate insulator and a semiconductor layer, respectively, and the lower circuit pattern comprises the first metal layer; a patterned dielectric layer disposed on the substrate and covering the transistor pattern, the lower capacitance pattern and the lower circuit pattern, wherein the patterned dielectric layer exposes a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern; a patterned electrode layer disposed on the patterned dielectric layer; and a patterned second metal layer disposed on the patterned electrode layer, the patterned second metal layer comprising an upper circuit pattern, a source/drain pattern and an upper capacitance pattern, wherein the upper circuit pattern, the source/drain pattern and the upper capacitance pattern are electrically connected to the lower circuit pattern, the source/drain region and the lower capacitance pattern, respectively, a portion of the patterned electrode layer exposed by the patterned second metal layer in the pixel area is used as a pixel electrode, and the patterned second metal layer outside the pixel area further exposes a portion of the electrode layer used as a bonding pad, and the bonding pad is electrically connected to the upper circuit pattern.