Patent ID: 8341577

Claim:
A method for simulation of a circuit partitioned into a plurality of circuit partitions over a plurality of integration times, the method comprising: calculating, by a computer, a first dependency indicating that an initial condition of a second circuit partition at a given integration time depends on a solved condition of a first circuit partition according to conditions of a previous integration time; calculating, by the computer, a second dependency indicating that an initial condition of the first circuit partition at the given integration time does not depend on a solved condition of the second circuit partition according to conditions of the previous integration time; and calculating, according to the first and second dependencies and using a first hardware thread of the computer, a second solved condition of the first circuit partition according to predicted conditions of a second integration time while performing an iterative timing analysis of the circuit with the computer according to conditions of a first integration time, the iterative timing analysis comprising calculating a first solved condition of the second circuit partition as a function of a first solved condition of the first circuit partition calculated according to conditions of the first integration time, wherein at least a portion of the iterative timing analysis of the circuit according to conditions of the first integration time is performed using a second hardware thread.