Patent ID: 8085576

Claim:
A semiconductor memory device, comprising: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines, each of the memory cells being configured by a rectifier and a variable resistor connected in series; and a control circuit configured to apply a first voltage to selected one or more of the first lines, and to apply a second voltage having a value smaller than the first voltage to selected one of the second lines, such that a certain potential difference is applied to selected one or more of the memory cells disposed at respective the crossing-points of the selected one or more of the first lines and the selected one of the second lines, the control circuit adjusting the second voltage based on a position of the selected one or more of the memory cells within the memory cell array and a number of the selected one or more of the memory cells on which an operation is simultaneously executed, during application of the potential difference to the selected one or more of the memory cells.