Patent ID: 8399983

Claim:
A semiconductor assembly, comprising: a printed circuit board (PCB) having first contacts on a top surface and second contacts on a bottom surface, the first contacts being vertically aligned with the second contacts and being electrically coupled by vias in the PCB; a first integrated circuit (IC) having first terminals respectively coupled to the first contacts of the PCB, the first terminals including first input/output (IO) terminals, a first power terminal, and a first ground terminal; and a second integrated circuit (IC) having at least one companion die, and second terminals coupled to at least a portion of the second contacts of the PCB, the second terminals including second IO terminals of the at least one companion die, a second power terminal, and a second ground terminal, the second IO terminals being respectively coupled to those contacts of the second contacts that are vertically aligned with those contacts of the first contacts respectively coupled to the first IO terminals, the second power terminal being coupled to a contact of the second contacts that is vertically aligned with a contact of the first contacts respectively coupled to the first power terminal, and the second ground terminal being coupled to a contact of the second contacts that is vertically aligned with a contact of the first contacts respectively coupled to the first ground terminal, wherein: the first terminals include at least one non-shared terminal; and the second terminals include at least one terminal that is vertically aligned with, and that is not coupled to a contact of the second contacts that is vertically aligned with the contact of the first contacts that is respectively coupled to the at least one non-shared terminal, wherein the at least one non-shared terminal is coupled to a die logic of the first IC that is sensitive to extraneous loads.