Patent ID: 7238551

Claim:
A method of fabricating a semiconductor package comprising: providing a lower lead frame, said lower lead frame having at least a first contact; forming a plurality of raised mesas in said first contact, said mesas having top surfaces and being separated by valleys; dispensing a first plurality of solder paste drops only on said top surfaces of said mesas; placing a semiconductor die on said first plurality of solder paste drops; performing a first reflow of said first plurality of solder paste drops so as form a first solder layer between said die and said first contact, said first reflow causing the first solder layer to flow into said valleys thereby decreasing a separation distance between said die and said first contact; dispensing a second plurality of solder paste drops on a top surface of said die; placing an upper lead frame on said second plurality of solder paste drops, said upper lead frame comprising bent portions at opposite ends of said upper lead frame, each of said bent portions terminating in a foot, said bent portions extending downward around opposite edges of said die; performing a second reflow of said plurality of solder paste drops and said first solder layer.