Patent ID: 8735863

Claim:
A resistive memory apparatus comprising: a substrate; a first electrode formed in a portion of the substrate, wherein the portion of the substrate is doped to form a first doping type area; a resistive memory layer positioned over at least a portion of the first electrode, wherein the resistive memory layer provides a low resistivity state when a first predetermined voltage range is applied, and the resistive memory layer provides a high resistivity state when a second predetermined voltage range is applied; a second electrode positioned over at least a portion of the resistive memory layer and first electrode, wherein the second electrode is formed from a conductive layer; a first trace coupled to the first electrode; a second trace coupled to the second electrode; and a diode region formed in a portion of the substrate, wherein a doping type of the diode region is different from the first doping type area of the first electrode, and the second trace is coupled to the diode region.