Patent ID: 8760207

Claim:
A flip-flop comprising: an input stage that converts an input signal to an output signal according to a first clock signal and a second clock signal; and a latch stage that latches the output signal according to a third clock signal and a fourth clock signal; wherein, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal respectively have different phases, wherein a phase difference between the first clock signal and the second clock signal is 90 degrees, and wherein a phase difference between the third clock signal and the fourth clock signal is 90 degrees, wherein a phase difference between the first clock signal and the third clock signal is 180 degrees, and wherein a phase difference between the second clock signal and the fourth clock signal is 180 degrees, and wherein the input stage comprises: a load, coupled to a first voltage level; a signal input circuit, serially connected to the load, that generates the output signal according to the input signal; and a first control circuit, coupled between the signal input circuit and a second voltage level, that activates the signal input circuit according to the first clock signal and the second clock signal.