Patent ID: 7754564

Claim:
A method comprising: forming a capacitor dielectric layer over a first region of a semiconductor substrate; forming a first gate dielectric layer over a second region of the semiconductor substrate; forming a first set of one or more polysilicon gate electrodes over the first gate dielectric layer, each having a first width equal to or greater than a minimum gate width; forming a patterned polysilicon structure over the capacitor dielectric layer, wherein the patterned polysilicon structure includes one or more narrow polysilicon lines having a width less than the minimum gate width; and then performing a first implant, whereby impurities are simultaneously implanted into the first region and the second region of the semiconductor substrate using the patterned polysilicon structure and the first set of one or more polysilicon gate electrodes as a mask; and performing a thermal-drive in cycle, wherein the impurities implanted in the first region of the semiconductor substrate diffuse to create a continuous diffusion region under the patterned polysilicon structure, and the impurities implanted in the second region of the semiconductor substrate diffuse to create source/drain regions of a first set of one or more transistors.