Patent ID: 7495938

Claim:
A three-level power conversion system, comprising: a DC connection for receiving or supplying DC electrical power, the DC connection comprising first and second DC terminals and first and second capacitors coupled in series between the first and second DC terminals, the capacitors being coupled at a common node; a multi-phase AC connection for receiving or supplying multi-phase electrical power, the AC connection comprising first, second, and third AC terminals, and a three-level switching network comprising: a first set of switching devices coupled with the DC connection and the first AC terminal, the first set operable in one of three states to selectively electrically couple the first AC terminal to one of the first DC terminal, the second DC terminal, and the common node according to a first set of switching control signals, a second set of switching devices coupled with the DC connection and the second AC terminal, the second set operable in one of three states to selectively electrically couple the second AC terminal to one of the first DC terminal, the second DC terminal, and the common node according to a second set of switching control signals, and a third set of switching devices coupled with the DC connection and the third AC terminal, the third set operable in one of three states to selectively electrically couple the third AC terminal to one of the first DC terminal, the second DC terminal, and the common node according to a third set of switching control signals; and a switch control system providing the sets of switching control signals by space vector modulation to equalize the voltages across the capacitors in open-loop fashion during operation of the power conversion system; wherein the switch control system comprises an even-order harmonic elimination space vector modulation system coupled with the three-level switching network, the space vector modulation system providing the sets of switching control signals by space vector modulation according to an even-order harmonic elimination vector switching sequence ensuring half-wave symmetry at all times to balance the voltage at the common node.