Patent ID: 7950144

Claim:
A method for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant, the method comprising: determining a number of build-up layers required for the integrated electronic panel assembly, wherein each build-up layer contributes an amount of concavity to the integrated electronic panel assembly; predicting a level of global convex warpage on the integrated electronic panel assembly provided by the presence of an embedded ground plane (EGP) alone within the integrated electronic panel assembly and in the absence of any build-up layers, wherein the embedded ground plane includes openings therein for accepting at least one die within a corresponding opening, the global convex warpage is contributed by the embedded ground plane globally to the integrated electronic panel assembly, and the predicted level of global convex warpage is dependent upon one or more of: a gap between an edge of a die of the at least one die and an edge of the embedded ground plane opening containing the die, and a difference in width between a portion of the embedded ground plane and a local warpage control element coupled to that portion of the embedded ground plane; and determining an amount of local convex warpage to be introduced into the integrated electronic panel assembly which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly, further for counteracting a total concavity introduced subsequently by processing of the determined build-up layers sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly, wherein one or more local warpage control elements contribute the amount of local convex warpage to the integrated electronic panel assembly upon fabrication thereof.