Patent ID: 8576967

Claim:
A semiconductor device comprising: a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; a communication timing control circuit that generates a communication timing signal to control a communication timing between the first circuit and the second circuit based on a frequency ratio information and a phase relation information, the frequency ratio information setting a frequency ratio of the first clock signal to the second clock signal, the phase relation information indicating a phase relation between the first clock signal and the second clock signal; and a hold time compensation circuit that adds a delay to a communication request signal and a communication data signal, or to a communication response signal, the communication request signal being transmitted by a data transmission-side circuit which comprises one of the first circuit and the second circuit when the data transmission-side circuit requests communication from a data reception-side circuit which comprises the other of the first circuit and the second circuit, the communication data signal being the signal transferring communication data from the data-transmission side circuit to the data reception-side circuit, the communication response signal being transmitted by the data reception-side circuit to the data transmission-side circuit when the data reception-side circuit receives the communication request signal, wherein the communication timing control circuit refers to the frequency ratio information for setting the frequency ratio of the first clock signal to the second clock signal and the phase relation information indicating the phase relation between the first clock signal and the second clock signal, so as to generate the communication timing signal so that the first circuit performs communication once for each communication performed by the second circuit.