Patent ID: 7055151

Claim:
A multi-tasking processor for executing computer instructions for a plurality of tasks, the processor being operable to either suspend a task or to re-execute a task's instruction without suspending the task, the processor comprising circuitry for: scheduling tasks for execution, and executing tasks scheduled for execution; obtaining first and second indications each of which is associated with a task being executed by the processor and with an instruction being executed for the associated task, each indication being an indication that the associated instruction is not to be executed to completion; in response to each first indication, (i) suspending the associated instruction without executing the associated instruction to completion, and (ii) suspending the associated task, wherein suspended tasks are not scheduled for execution, the processor being operable to schedule another task for execution in lieu of the associated task; and in response to each second indication, suspending the associated instruction without executing the associated instruction to completion and without suspending the associated task, and re-executing the associated instruction without suspending the associated task.