Patent ID: 8295412

Claim:
An apparatus comprising: a sampler disposed to receive a signal, said sampler being adapted to produce a stream of digital samples responsive to said signal, each digital sample having a same number of bits; a plurality of buffers, each buffer having a plurality of addresses, joined to receive said stream of digital samples such that the digital sample bits from the sample are stored across the plurality of buffers in a corresponding address in each said buffer, and additional digital samples are stored in an additional corresponding address across the plurality of buffers until all addresses are full whereupon digital samples are stored replacing the oldest of said digital samples in said each of said plurality of buffers with the newest sample from said stream of digital samples; a reference signal storage means having a plurality of digital reference signals stored therein; a comparator effective to perform a bitwise chronological comparison between said each address of said plurality of buffers with each said reference signal of said reference signal storage means; an accumulator joined to said comparator capable of tabulating the bitwise chronological comparison performed by said comparator; and a processor joined to said accumulator for receiving said tabulated comparisons, said processor being capable of making determinations concerning a relationship between said reference signal and said signal based on said tabulated comparisons.