Patent ID: 8114484

Claim:
A method for forming a film stack suitable for transistor fabrication, the method comprising: positioning a substrate in a plasma enhanced chemical vapor deposition (PECVD) chamber; depositing a first silicon nitride layer on the substrate with a first deposition rate at a temperature less than about 300 degrees Celsius in the PECVD chamber, wherein the substrate is at a first spacing from a showerhead of the process chamber during deposition of the first silicon nitride layer; depositing a second silicon nitride layer with a second deposition rate on the first silicon nitride layer at a temperature less than about 300 degrees Celsius in the PECVD chamber, wherein the first deposition rate is greater than the second deposition rate and the substrate is at a second spacing from the showerhead during deposition of the second silicon nitride layer that is smaller than the first spacing; depositing a dual layer amorphous silicon film on the second silicon nitride layer at a temperature less than about 300 degrees Celsius in the PECVD chamber; and depositing a n-doped silicon film on the dual layer amorphous silicon film at a temperature less than about 300 degrees Celsius in the PECVD chamber.