Patent ID: 7140003

Claim:
A method for specifying a set of instructions selectable for generation by an instruction generator, comprising: identifying a first class name representative of a first class of instructions, said first class of instructions being a subset of an instruction set of a processor; concatenating said first class name with a unique identifier label thereby defining a unique singleton meta-mnemonic representative of a first set of instructions, said first set of instructions being a subset of said instruction set of said processor; specifying, via said singleton meta-mnemonic, said first set of instructions for selection by said instruction generator; wherein said singleton meta-mnemonic specifies a set of instructions that are a subset of said processor instruction set and are available for selection and generation by said instruction generator; identifying at least a second class name representative of at least a second class of instructions, said at least a second class of instructions being a subset of said instruction set; concatenating said first class name with said at least a second class name and a unique identifier label thereby defining a unique compound meta-nmemonic representative of at least a second set of instructions, each instruction in said at least a second set of instructions having membership in each of said classes; specifying, via said compound meta-nmemonic, said at least a second set of instructions for selection by said instruction generator; wherein said compound meta-mnemonic specifies a set of instructions that are a subset of said processor instruction set and are available for selection and generation by said instruction generator; concatenating at least one of said singleton meta-mnemonic and said compound meta-nmemonic with an exclusionary label thereby defining an exclusionary meta-nmemonic representative of a third set of instructions, each instruction in said third set of instructions having membership outside of the set of instructions defined by at least one of said singleton meta-mnemonic and said compound meta-nmemonic; specifying, via said exclusionary meta-nmemonic, said third set of instructions for selection by said instruction generator; wherein said exclusionary meta-nmemonic specifies a set of instructions that are a subset of said processor instruction set and are available for selection and generation by said instruction generator; converting at least one of said singleton, said compound, and said exclusionary meta-mnemonic into an expression containing the value of said converted meta-mnemonic; parsing the expression and creating a binary expression tree containing the values for at least one of an operator, an operand, said converted meta-mnemonic, a conditional ternary operator, and a definition of the resulting set of instructions; referencing the existing state of said processor; and determining which set of instructions to utilize based on the existing state of said processor.