Patent ID: 7114089

Claim:
A method for controlling the-operation of a processor, the processor comprising a core, two or more functional blocks, a decoder for decoding instruction words included in a program code to be run in one or more of said functional blocks, at least one of said functional blocks being provided with at least two different modes, and the mode of at least one of said functional blocks being set to one of said at least two modes at a time, the method comprising: transmitting an instruction word containing information about whether it is an instruction word relating to setting of a mode, and processing instruction words included in the program code in at least a first decoding in a first decoding block and a second decoding in a second decoding block, wherein the first decoding comprises: examining said information contained within the instruction word, and after the examination, determining whether a mode of one or more of said functional blocks is to be set or whether the second decoding is to be taken; wherein said second decoding comprises: decoding the instruction word; and executing the decoded instruction word by one or more of said functional blocks.