Patent ID: 7381605

Claim:
A method for fabricating a semiconductor device, comprising: forming a first polysilicon layer over a substrate divided into a cell region and a peripheral region, the first polysilicon layer covering the substrate in the peripheral region and opening predetermined portions of the substrate in the cell region where recesses are to be formed; etching the predetermined portions of the substrate using the first polysilicon layer as an etch mask to form recesses; forming a second polysilicon layer over the substrate in the cell region and the first polysilicon layer remaining in the peripheral region after the recesses are formed; selectively removing the second polysilicon layer formed over the remaining first polysilicon layer in the peripheral region; planarizing the second polysilicon layer in the cell region; and patterning the second polysilicon layer in the cell region and the first polysilicon layer in the peripheral region to form gate patterns in a dual poly-recess structure.