Patent ID: 7348844

Claim:
An electronic circuit, for amplifying an input signal, x 0 , comprising: a clipping unit for generating a signal, x, having a reduced peak-to-average power ratio by clipping the input signal x 0 ′; a pre-distorter for generating a pre-distorted signal, ξ, defined by an pre-distortion algorithm which is based on an amplifier model function A; a representation unit for representing the amplifier model function, A, either in terms of coefficients of polynomials, or as look-up tables; a non-linear processing unit, like a power amplifier, for generating a processed signal, z, like an amplified pre-distorted signal; a time delay unit for compensating a processing time for the pre-distorted signal ξ generating a delayed pre-distorted signal ξ′; a time delay cascade for delaying the pre-distorted signal, ξ′, at integer sample clocks 1 , 2 , . . . , n generating delayed signals ξ −1 ′,ξ −2 ′, . . . ,ξ −n ′ and an adaptation unit for learning the amplifier model function A using the processed signal, z, and the delayed signals ξ,ξ −1 ′,ξ −2 ′, . . . ,ξ −n ′ such that a measure for non-linearity L n is minimized.