Patent ID: 8796729

Claim:
An apparatus comprising: a p-type substrate; a first p-type well disposed in the p-type substrate, wherein the first p-type well comprises at least one p-type active region and at least one n-type active region electrically connected to a first terminal; a first n-type well disposed in the p-type substrate adjacent the first p-type well, wherein the first n-type well comprises at least one p-type active region and at least one n-type active region electrically connected to a second terminal; a second p-type well disposed in the p-type substrate, wherein the second p-type well comprises at least one p-type active region and at least one n-type active region electrically connected to a third terminal; and an n-type isolation layer beneath the first p-type well, the first n-type well, and at least a portion of the second p-type well, wherein the first p-type well and the first n-type well are configured to operate as a blocking diode, wherein the at least one p-type active region of the first n-type well, the first n-type well, the first p-type well, and the at least one n-type active region of the first p-type well are configured to operate as a PNPN silicon controlled rectifier, and wherein the at least one n-type active region of the first p-type well, the first p-type well, the n-type isolation layer, the second p-type well, and the at least one n-type active region of the second p-type well are configured to operate as an NPNPN bidirectional silicon controlled rectifier.