Patent ID: 7831950

Claim:
A method for designing a printed circuit board for an electronic circuit comprising: creating a timing database including terminal information, input/output attribute and timing information relating to a selected component; generating a circuit diagram based on circuit design information; extracting connection information of a component from said circuit diagram, and performing timing verification, with reference to said timing database, to check whether or not the component is connectable from timing perspective; carrying out layout design of the printed circuit board, inclusive of placement and routing of a component which is decided to be connectable as a result of said timing verification; extracting respective line lengths of a data line and a clock line in said printed circuit board obtained by said layout design from a net list and layout information thereof to derive respective wiring delay times of said data line and said clock line; and checking, with reference to the wiring delay times derived and the timing database, whether or not delays on the data line and the clock line satisfy a preset timing constraint.