Patent ID: 8347026

Claim:
A memory device from and to which data corresponding to a first size can be read and written, said memory device comprising: an address holding unit configured to hold N addresses where N is an integer of 2 or more; N read buses and N write buses, each of said N read buses and said N write buses having a bus width of a second size and including first slots, each of the first slots being a partial bus having a bus width of a third size; N memory modules each uniquely connected to a corresponding one of said N read buses and a corresponding one of said N write buses, each of said N memory modules holding data for each address designated by a corresponding one of the N addresses held in said address holding unit; an output data bus and an input data bus each having a bus width of the first size and including second slots, each of the second slots being a partial bus having a bus width of the third size; a read data processing unit configured to (i) select, from among pieces of data read from said N memory modules via said N read buses, pieces of data read via two or more first slots from among the first slots included in said N read buses, and (ii) provide the selected pieces of data to second slots from among the second slots included in said output data bus; and a write data processing unit configured to provide each of pieces of data provided via the second slots included in said input data bus, to a corresponding one of the first slots included in said N write buses, so as to write the pieces of data provided via the second slots included in said input data bus to said N memory modules.