Patent ID: 8296483

Claim:
A storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, comprising: a memory disk unit, which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; an SAS/SATA host interface unit, which interfaces between the memory disk unit and a host; and a controller unit, which adjusts synchronization of a data signal transmitted/received between the SAS/SATA host interface unit and the memory disk unit to control a data transmission/reception speed between the SAS/SATA host interface unit and the memory disk unit, wherein the controller unit includes: a memory control module, which controls data input/output of the memory disk unit; a DMA control module, which controls the memory control module to store data in the memory disk unit or reads data from the memory disk unit to provide the data to the host, according to an instruction from the host received through the SAS/SATA host interface unit; a buffer, which buffers data according to control of the DMA control module; a synchronization control module, which, when receiving a data signal corresponding to the data read from the memory disk unit by the control of the DMA control module through the DMA control module and the memory control module, adjusts synchronization of a data signal so as to have a communication speed corresponding to an SAS/SATA communications protocol to transmit the synchronized data signal to the SAS/SATA host interface unit, and when receiving a data signal from the host through the SAS/SATA host interface unit, adjusts synchronization of the data signal so as to have a transmission speed corresponding to a communications protocol used by the memory disk unit to transmit the synchronized data signal to the memory disk unit through the DMA control module and the memory control module; and a high-speed interface module, which processes the data transmitted/received between the synchronization control module and the DMA control module at high speed, includes a buffer having a double buffer structure and a buffer having a circular queue structure, and processes the data transmitted/received between the synchronization control module and the DMA control module without loss at high speed by buffering the data transmitted/received between the synchronization control module and the DMA control module using the buffers and adjusting data clocks.