Patent ID: 8669970

Claim:
A system comprising: a first pixel processing unit coupled to receive a first pixel stream and configured to perform one or more pixel operations on pixels represented in the first pixel stream to generate a first processed pixel stream; a second pixel processing unit coupled to receive a second pixel stream and configured to perform one or more pixel operations on pixels represented in the second pixel stream to generate a second processed pixel stream; wherein the first pixel processing unit and the second pixel processing unit are in a first clock domain; a first display driving circuit coupled to receive the first processed pixel stream and configured to drive a first panel to display frames described in the first processed pixel stream, wherein the first display driving circuit is in a second clock domain; and a second display driving circuit coupled to receive the second processed pixel stream and configured to drive a second panel to display frames described in the second processed pixel stream, wherein the second display driving circuit is in a third clock domain; wherein, in a mirrored mode, the first pixel stream and the second pixel stream are the same, and wherein the first display driving circuit is configured to control a synchronization interface to the second display driving circuit in the mirrored mode, and wherein the second display driving circuit is configured to trigger display of the second processed pixel stream responsive to the synchronization interface, and wherein the second display driving circuit is configured to drive the second panel responsive to the second processed pixel stream independent of the first display driving circuit, and wherein the second display driving circuit is configured to monitor the synchronization interface to remain within a threshold of synchronization with the first display driving circuit and to resynchronize to the first display driving circuit if not within the threshold.