Patent ID: 8618537

Claim:
A semiconductor device comprising: in a first region over a semiconductor substrate: a first insulating layer located over the semiconductor substrate; a first wiring embedded into the surface of the first insulating layer; a second insulating layer located over the first insulating layer; a third insulating layer located over the second insulating layer; and a via and a second wiring embedded into the second insulating layer and the third insulating layer through a barrier metal and coupled to the first wiring, and in a second region over the semiconductor substrate: the first insulating layer located over the semiconductor substrate; a gate electrode embedded into the surface of the first insulating layer; the second insulating layer located over the first insulating layer; a semiconductor layer located over the second insulating layer; the third insulating layer located over the semiconductor layer; and a first electric conductor and a second electric conductor embedded into the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.