Patent ID: 7516247

Claim:
A method comprising: receiving a completion wait command in an input/output memory management unit (IOMMU), wherein the IOMMU is configured to provide address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices, and wherein the completion wait command is defined to ensure that one or more preceding invalidation commands that were included in a sequence of commands prior to the completion wait command are completed by the IOMMU prior to a completion of the completion wait command; the IOMMU receiving a read response corresponding to each outstanding memory read operation that depends on a translation entry that is invalidated by the preceding invalidation commands; the IOMMU transmitting one or more operations upstream to ensure that each memory write operation that depends on the translation table entry that is invalidated by the preceding invalidation commands has at least reached a bridge to a coherent fabric in the computer system; and the IOMMU completing the completion wait command subsequent to completing the one or more invalidation commands, subsequent to receiving the read response, and subsequent to transmitting the one or more operations.