Patent ID: 8244926

Claim:
A single chip data processor having an operating condition and a standby condition, the single chip data processor comprising: an interface circuit including: a first interface which includes a first external terminal to be coupled to a first external bus, and a first interface circuit coupled to the first external terminal, and a second interface which includes a second external terminal to be coupled to a second external bus, and a second interface circuit coupled to the second external terminal; a first internal bus coupled to the first interface circuit; and a central processing unit coupled to the first internal bus, performing an execution of an instruction in the operating state and suspending an execution of the instruction in the standby condition, wherein the interface circuit further includes: a first function for providing first data on the first external terminal to the second external terminal without using the first internal bus in the standby condition, and a second function for providing second data on the first internal bus to the second external terminal in the operation condition, wherein the first data on the first external terminal includes a display of time in the standby condition.