Patent ID: 8604840

Claim:
An apparatus comprising: a phase frequency detector configured to receive a reference signal of frequency fref on a first line, receive a divider feedback signal (Div) of frequency fdiv on a second line, receive a VCO output signal of frequency fvco on a third line, and output an up current control signal (Up) and a down current control signal (Down), wherein the up current control signal comprises a sequence of up current control pulses, wherein the down current control signal comprises a sequence of down current control pulses, and wherein the phase frequency detector comprises: a divide by k circuit configured to receive the VCO output signal on the third line and produce a plurality of adjustment reference signals (Vars) based at least in part on the frequency fvco of the received VCO output signal; a time/digital converter configured to receive the plurality of adjustment reference signals (Vars) from the divide by k circuit and produce a delay compensation signal (Dcomp) based at least in part on the plurality of adjustment reference signals (Vars); and a delay adjuster configured to receive the delay compensation signal (Dcomp) from the time/digital converter and produce a delay adjustment signal based at least in part on the received delay compensation signal (Dcomp), wherein the phase frequency detector is further configured to control the up current control pulses to have an up pulse duration calibrated to be a fixed multiple of a period of the VCO output signal based at least in part on the delay adjustment signal; a charge pump circuit configured to receive the up current control signal and the down current control signal and to output a charge pump output current signal (Icp); a loop filter configured to receive a sum of the charge pump output current signal (Icp) and a down modification signal (ΔI) and to output a control signal (Vctl); a divider configured to receive the VCO output signal on a fourth line and to output the divider feedback signal (Div) to the phase frequency detector on the second line; a voltage controlled oscillator (VCO) configured to receive the control signal (Vctl), to output the VCO output signal to the phase frequency detector on the third line, and to output the VCO output signal to the divider on the fourth line; and a down modification signal generating circuit configured to receive an instantaneous quantization error signal (ei) and to output the down modification signal (ΔI).