Patent ID: 6880044

Claim:
A memory controller, comprising: a plurality of tag units, each tag unit including an array of tag address storage locations, the plurality of tag units to perform tag look-up operations in response a memory access request; a memory module decode unit, the memory module decode unit to perform decode operations to determine which one of a plurality of memory modules is being accessed by the memory access request substantially concurrently with respect to the tag look-up operations; and a command sequencer and serializer unit coupled to the array of tag address storage locations and the memory module decode unit, the command sequencer and serializer unit to serialize commands and address information and sequentially transmit, over a serial link of a memory bus coupling the memory control with a plurality of memory modules, to a memory module to access a data cache located on the memory module that is specified by the memory module decode unit as a result of the decode operations, if the lookup operations indicate that at least one of the tag addresses matches a memory address of the memory access request.