Patent ID: 7223651

Claim:
A semiconductor memory having a memory cell, comprising: a substrate having a substrate surface and a trench, the trench having a trench capacitor arranged therein, the trench capacitor being filled with a conductive trench filling; an insulating covering layer being arranged in the trench; a selectively grown epitaxial layer proceeding from the substrate surface, the epitaxial layer extending laterally over the insulating covering layer, the epitaxial layer being arranged on the substrate surface and the insulating covering layer, a contact trench being formed in the epitaxial layer and in the insulating covering layer, the epitaxial layer having a sidewall along the contact trench; a selection transistor, the selection transistor including a source region, a drain region, a gate oxide and a gate electrode, the source region and the drain region being arranged in the epitaxial layer, the gate oxide being arranged on the epitaxial layer, the source region extending in a vertical direction from a surface of the epitaxial layer that is remote from the substrate to the insulating covering layer such that the source region prevents uncontrolled current flow and leakage currents; a conductive contact, the conductive contact being arranged in the contact trench and on the conductive trench filling, the conductive contact connecting the source region to the conductive trench filling, a conductive connection being formed along a length of the sidewall of the epitaxial layer, the length extending from the end of the sidewall formed at the covering layer as far as the upper end of the conductive contact; and an intermediate layer disposed in the contact trench between the conductive trench filling and the conductive contact, wherein the intermediate layer is formed from an insulating material having a thickness of up to 2 nanometers so as to enable a tunneling current through the intermediate layer.