Patent ID: 8717086

Claim:
An adaptive cascode circuit, comprising: a) a main MOS transistor, wherein a source of said main MOS transistor is configured as a first terminal of said adaptive cascode circuit, and wherein a gate of said main MOS transistor is configured as a control terminal of said adaptive cascode circuit; b) n adaptive MOS transistors coupled in series to a drain of said main MOS transistor, wherein a drain of a first adaptive MOS transistor is configured as a second terminal of said adaptive cascode circuit, and wherein n is an integer greater than one; c) a shutdown clamping circuit coupled to gates of said n adaptive MOS transistors, wherein said shutdown clamping circuit comprises (n+1) shutdown clamping voltages that are less than corresponding rated drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors, wherein said shutdown clamping circuit is configured to clamp drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors to corresponding said shutdown clamping voltages when said main MOS transistor and said n adaptive MOS transistors are shutdown; and d) n conduction clamping circuits coupled to gates of corresponding said n adaptive MOS transistors, wherein said n conduction clamping circuits comprise n conduction clamping voltages greater than corresponding conduction threshold voltages of said adaptive MOS transistors, wherein said n conduction clamping circuits are configured to clamp said gate voltages of said n adaptive MOS transistors to corresponding said n conduction clamping voltages when said n adaptive MOS transistors and said main MOS transistor are conducting.