Patent ID: 7287150

Claim:
A processor, comprising: an instruction issuing unit which fetches and decodes an instruction, wherein, when a predetermined instruction is fetched and decoded, said instruction issuing unit develops said predetermined instruction operation into a multiflow including a previous flow and a following flow and said instruction issuing unit issues the instruction by an in-order process; a reservation station which holds said issued instruction; an instruction executing unit which executes the instruction held in said reservation station by an out-of-order process; a committing unit which discriminates a commitment of the instruction executed by said instruction executing unit and completes the instruction by the in-order process; a multiflow guarantee processing unit which guarantees an execution result of the previous flow by said instruction executing unit until the following flow is committed after the previous flow was committed by providing a register file, including a register undate buffer to store a plurality of register values as allocated registers, to transfer the execution result between multiflows, and said multiflow guarantee processing unit inhibits release of an execution result in an allocated register until said following flow is committed; and a renaming processing unit which renames a register used by a plurality of instructions having a dependent relationship, allocates the renamed register onto the register update buffer, and releases the register allocated on the register update buffer in accordance with the commitment of the executed instruction by said committing unit.