Patent ID: 8156465

Claim:
A layout method for an integrated circuit device in which, through a plurality of layout steps, a plurality of cells are disposed in a chip region and wires are disposed to connect said cells to each other, said cells including a normal cell and a timing adjustment cell, said layout method comprising: a placement restricted region placement step for disposing, using a microprocessor, in said chip region, a placement restricted region having a first rule of a first layout step in which placement of normal cell type is prohibited in said first layout step, and having a second rule of a second layout step, in which placement of timing adjustment cell type is permitted in said second layout step, said first and second layout steps being carried out later; the first layout step for disposing normal cells included in logical design data, in said chip region in conformity with said normal cell type that is prohibited in accordance with said first rule defined in said disposed placement restricted region; and the second layout step for disposing timing adjustment cells on a wire connecting between said normal cells to adjust a timing of a signal that is transmitted along said wire, in said chip region in conformity with said timing adjustment cell type that is permitted in accordance with said second rule defined in said disposed placement restricted region.