Patent ID: 8438326

Claim:
A memory interface system comprising: a memory controller configured to operate at a first operating frequency; and a physical interface block coupled to the memory controller, wherein the physical interface block is configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency; wherein the memory controller and the physical interface block are located within a same integrated circuit and the memory device is located within a different integrated circuit; and wherein the physical interface block comprises: a plurality of timers configured to regulate transaction processing within the physical interface block; at least one output first-in-first-out (FIFO) memory configured to receive data from the memory controller at a rate corresponding to the first operating frequency and to provide data to the memory device at a rate corresponding to the second operating frequency; at least one input FIFO memory configured to receive data from the memory device at a rate corresponding to the second operating frequency and to provide data to the memory controller at a rate corresponding to the first operating frequency; a first phaser configured to generate a clock signal at the second operating frequency controlling an output port of the at least one output FIFO memory; and at least a second phaser configured to generate a clock signal at the second operating frequency controlling an input port of the at least one input FIFO memory.