Patent ID: 7840925

Claim:
A computer-implemented method of performing timing analysis upon a circuit design comprising synchronous circuit elements, the method comprising: selecting a destination pin having a plurality of source pins, wherein each source pin of the plurality of source pins defines a data path to the destination pin; determining a slack of a selected data path of the data paths to the destination pin; comparing, via a computer, a timing adjustment of each of the plurality of source pins to the slack of the selected data path, wherein each timing adjustment is determined using static timing analysis; via the computer, selectively including, within the circuit design, a simulation node configured to perform at least one of a setup check or a hold check according to the comparison; wherein the simulation node includes a check node and a buffer coupled between one of the source pins and an input of the check node, and the check node is configured to determine whether or not a timing violation occurs for a signal output from the buffer according to a timing interval defined, at least in part, by the timing adjustment for the path defined by the one of the source pins; and outputting, via the computer, the circuit design comprising the simulation node.