Patent ID: 7927995

Claim:
A method of fabricating a semiconductor structure providing a structure including an insulator having via and line openings; forming an organic planarizing material on said structure to fill said via and line openings with said organic planarizing material; forming an oxide layer having at least one opened area for forming an anti-fuse structure, said at least one opened area is located above a pair of adjacent line openings; removing at least a portion of said organic planarizing material within said at least one opened area to expose a portion of each pair of said adjacent line openings; embedding an electrically conductive layer in said insulator between said pair of adjacent line openings; removing said oxide layer and remaining organic planarizing material; filling said vias and line openings with at least an electrically conductive interconnect material; and planarizing said electrically conductive interconnect material to an upper surface of said insulator, wherein said planarizing removes said embedded electrically conductive layer from an upper horizontal surface of said insulator forming at least a pair of adjacent interconnects comprising a buried electrically conductive layer surrounding a portion of each respective interconnect, each buried first electrically conductive layer is separated by a dielectric region which permits current flow when a bias is applied to one of said interconnects of said pair.