Patent ID: 7180893

Claim:
A packet header processing engine comprising: a first packet processing unit configured to generate first packet header information relating to a first packet header protocol; a first output buffer configured to receive the first packet header information; a second packet processing unit implemented in parallel with the first packet processing unit and including a plurality of execution sections implemented in parallel with one another, the second packet processing unit configured to generate second packet header information relating to a second packet header protocol, the second packet header protocol including layer 3 (L3) packet processing information; an instruction memory operatively coupled to the second packet processing unit, the instruction memory providing the second packet processing unit with instructions relating to processing of L3 packet header information, where each of the plurality of execution sections operate based on a portion of each instruction from the instruction memory; a second output buffer configured to receive the second packet header information; and a build component configured to unload the first and second packet header information from the first and second output buffers when generation of the first and the second packet header information is complete and to form, using the unloaded first and second packet header information, a combined packet header containing the information relating to the first packet header protocol and the second packet header protocol wherein the first packet header protocol is layer 2 (L2) packet processing information.