Patent ID: 8735970

Claim:
A semiconductor device comprising: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; a common gate section which covers side faces of the pillars; a first protruding layer comprising a gate-lifting semiconductor pillar formed near a group of the semiconductor pillars; a second protruding layer which is formed above a top face of the first protruding layer; a gate electrode which is formed along a side face of the first protruding layer and on a side face of the second protruding layer and is connected to other gate electrodes, the gate electrode not being disposed on a top face of the second protruding layer; a gate wire which is provided above the gate electrode; and a first conductive plug having a lower end which connects both to an upper end of the gate electrode formed along the side face of the first protruding layer and on the side face of the second protruding layer and to the top face of the second protruding layer, and the first conductive plug having an upper end which connects to the gate wire and overlaps a portion of the gate electrode which covers the side face of the first protruding layer, wherein the gate section includes gate electrodes which are formed over the side faces of the pillars and contact each other, and wherein a part of the side face of the second protruding layer is covered by the gate electrode, and the first conductive plug overlaps a portion of the gate electrode which covers the side face of the second protruding layer.