Patent ID: 8332784

Claim:
A semiconductor device having a physical pattern based on a designed pattern, in which: the designed pattern includes a target pattern and a correction pattern, which is designed for a pattern to be formed on a wafer; the target pattern includes a first portion of an edge with a first distance between the first portion and a pattern opposed thereto, a second portion of the edge with a second distance between the second portion and a pattern opposed thereto, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance between the first region and the pattern opposed thereto and a second region of the edge with the second distance between the second region and the pattern opposed thereto; and the correction pattern is added to at least one of the first portion of the edge, the second portion of the edge, and the third portion of the edge such that the first portion of the edge, the second portion of the edge, and the third portion of the edge are caused to differ from one another in dimensions of the designed pattern.