Patent ID: 8149606

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cell arrays stacked on said semiconductor substrate and arranged in a matrix, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing said first lines, and a plurality of memory cells arranged at intersections of said first lines and said second lines, each memory cell having one end connected to one of said first lines and the other end connected to one of said second lines; a first control circuit and a second control circuit provided on said semiconductor substrate immediately beneath one of said memory cell arrays and each having one end connected to said first lines to select and drive said first lines; a third control circuit and a fourth control circuit provided on said semiconductor substrate immediately beneath said one of said memory cell arrays and each having one end connected to said second lines to select and drive said second lines; a third line connected to said first control circuit; a fourth line connected to said second control circuit; a fifth line connected to said third control circuit; a sixth line connected to said fourth control circuit; a fifth control circuit connected to one end of said third line and one end of said fourth line to select and drive said third and fourth lines; and a sixth control circuit connected to one end of said fifth line and one end of said sixth line to select and drive said fifth and sixth lines.