Patent ID: 7378705

Claim:
A single-poly memory cell comprising: a floating polysilicon gate for storing a charge, the polysilicon gate located on top of an oxide layer grown in a gate oxidation process; a MOSFET transistor having a gate that is a first portion of the polysilicon gate and a first portion of the oxide layer; a MOS control capacitor having a top plate, a dielectric, a bottom plate and a contact, the top plate being a second portion of the polysilicon gate, the dielectric being a second portion of the oxide layer, and the bottom plate comprising a lightly doped region under the dielectric, a first doped region adjacent to the lightly doped region under the dielectric, and a second doped region adjacent to the lightly doped region under the dielectric, wherein the contact is connected to the bottom plate and is operable to receive a first voltage, and wherein the first voltage biases the control capacitor; and a MOS tunneling capacitor having a top plate, a dielectric, a bottom plate and a contact, the top plate being a third portion of the polysilicon gate, the dielectric being a third portion of the oxide layer, and the bottom plate comprising a lightly doped region under the dielectric, a third doped region adjacent to the lightly doped region under the dielectric, and a fourth doped region adjacent to the lightly doped region under the dielectric, wherein the contact is connected to the bottom plate and is operable to receive a second voltage, and wherein the second voltage biases the tunneling capacitor.