Patent ID: 7546502

Claim:
An integrated circuit comprising: A. a test clock input lead; B. a test reset input lead; C. a test data in input lead; D. a test data out output lead; E. a test mode select input lead; F. first TAP circuitry having a test data input, a test data output, a test clock input connected to the test clock input lead, a test reset input connected to the test reset input lead, and a test mode select input; G. second TAP circuitry having a test data input, a test data output, a test clock input connected to the test clock input lead, a test reset input connected to the test reset input lead, and a test mode select input; H. input linking circuitry selectively coupling the test data in input lead to the test data input of the first and second TAP circuitry and selectively coupling the test mode select input lead to the test mode select input of the first and second TAP circuitry in response to input linking control signal inputs; I. output linking circuitry selectively coupling test data outputs of the first and second TAP circuitry to the test data out output lead in response to output linking control signal inputs; and J. TAP linking module circuitry having a test data input, a test data output, a test clock input connected to the test clock input lead, a test reset input connected to the test reset input lead, a test mode select input connected to the test mode select input lead, and input and output linking control signal outputs respectively connected to the linking control signal inputs of the input linking circuitry and the output linking circuitry, the test input and the test data output being coupled in series with the test data in input lead and the test data out output lead.