Patent ID: 8432654

Claim:
An electronic assembly having therein a cascaded electrostatic discharge (ESD) clamp coupled across first and second terminals of a protected semiconductor device or integrated circuit included in the electronic assembly, comprising: at least first and second serially coupled ESD clamp stages, each ESD clamp stage comprising: an ESD transistor having source, drain, gate and body contacts; a first resistor coupled between the gate and source contacts of the ESD transistor; a second resistor coupled between the body and source contacts of the ESD transistor; and a first control transistor having source, drain and gate contacts, wherein the source and drain contacts of the first control transistor are coupled across the first resistor and the gate contact of the first control transistor is adapted to be coupled to a first bias voltage; a second control transistor having source, drain and gate contacts, wherein the source and drain contacts of the second control transistor are coupled across the second resistor and the gate contact of the second control transistor is adapted to be coupled to a second bias voltage; and wherein the source or drain contact of the ESD transistor of the first ESD clamp stage is coupled to the second terminal, the drain contact of the ESD transistor of the second ESD clamp stage is coupled to the first terminal, and the drain or source contact of the ESD transistor of the first ESD clamp stage is coupled to the source contact of the ESD transistor of the second ESD clamp stage.