Patent ID: 7014727

Claim:
A method of forming high resolution electronic circuits on a substrate, comprising the steps of: (a) laminating an upper surface of said substrate with a layer of dielectric film, said layer of dielectric film having an upper surface and a lower surface, said lower surface of said layer of dielectric film being contiguous with said upper surface of said substrate; (b) laser drilling said upper surface of said layer of dielectric film to form at least one channel in said layer of dielectric film; (c) filling said at least one channel with an electrically conductive material; (d) applying a release layer to said upper surface of said layer of dielectric film, said release layer having an upper surface and a lower surface, said lower surface of said release layer being coated with an adhesive layer, said adhesive layer being contiguous with and adhering to said upper surface of said layer of dielectric film; (e) heating said substrate, said layer of dielectric film, said electrically conductive material in said at least one channel, and said release layer to a temperature in a range of approximately 150° C.–175° C. to enhance mechanical integrity of said conductive material within said at least one channel and to create permanent adhesion between said conductive material and said upper surface of said substrate; and (f) removing said release layer and said layer of dielectric film adhered thereto from said substrate, thereby exposing said electrically conductive material formed, patterned and remaining permanently on said upper surface of said substrate.