Patent ID: 6903400

Claim:
A magnetoresistive memory apparatus having a semiconductor substrate on which are arranged a plurality of word lines and bit lines which intersect each other in a non-contact manner to constitute a matrix, and a plurality of magnetoresistive memory devices located in the vicinity of each of intersections of the plurality of bit lines and word lines, the magnetoresistive memory devices each consisting, disposed one upon another via insulating layers, of free layers having variable magnetization directions and of fixed magnetization layers having fixed magnetization directions, with magnetized information being written to the magnetoresistive memory device at an intersection selected by magnetization electric currents supplied to the bit lines and the word lines, the magnetized information being read out by detecting the resistance variance of electric currents flowing through the magnetoresistive memory device due to the tunnel effect, wherein the plurality of magnetoresistive memory devices are located at positions deviating from the intersections of the plurality of word lines and bit lines, and wherein between the bit lines and the word lines at each of the intersections are disposed in a non-contact manner free layer extended portions which are extensions from only the free layer magnetic material of each magnetoresistive memory device.