Patent ID: 7816769

Claim:
A substrate strip of a leadless three-dimensional stackable semiconductor package, the substrate strip comprising: an integrated circuit die mounting area including: a leadless outer portion, the leadless outer portion including a plurality of sections electrically isolated from each other and having a flat wire bonding area and a sidewall essentially perpendicular to the flat wire bonding area, the flat wire bonding area and the sidewall being formed from a same material, an outer side surface of the sidewall being disposed at and forming a substantially continuous outermost edge of the integrated circuit die mounting area; and an inner portion located within and electrically isolated from the outer portion, the inner portion having a thickness that is less than a height of the sidewall of the outer portion and being configured to serve as an attachment area for an integrated circuit die, the thickness of the inner portion configured such that a top surface of an attached integrated circuit die is disposed below a top of the sidewall area.