Patent ID: 8492868

Claim:
An integrated circuit structure comprising: a high-resistivity silicon (HRS) substrate layer comprising trench lattice structures and an ion impurity implant; a buried oxide (BOX) layer positioned on and contacting said HRS substrate layer, said BOX layer filing said trench lattice structures; and a circuitry layer positioned on and contacting said BOX layer, said circuitry layer comprising groups of active circuits separated by passive structures, said trench lattice structures being positioned between said groups of active circuits when said integrated circuit structure is viewed from a top view where said circuitry layer is a top of said integrated circuit structure and said HRS substrate layer is a bottom of said integrated circuit structure, such that said trench lattice structures are below said passive structures and are not below said groups of circuits when said integrated circuit structure is viewed from said top view, and said trench lattice structures surrounding said groups of active circuits when said integrated circuit structure is viewed from said top view.