Patent ID: 7123055

Claim:
An output driver circuit, comprising: a totem pole driver stage having a PMOS pull-up path and an NMOS pull-down path therein electrically connected in series between a power supply line and a reference line, said PMOS pull-up path comprising: at least one PMOS pass transistor having a drain terminal electrically coupled to an output terminal of the output driver circuit and a gate terminal responsive to a first pull-up control signal; and an array of PMOS pull-up transistors having drain terminals electrically coupled to a source terminal of said at least one PMOS pass transistor and gate terminals responsive to coarse and fine pull-up enable signals, said array of PMOS pull-up transistors comprising a coarsely tuned array of binary weighted PMOS pull-up transistors having widths in a range from W p to 2 N W p , where N is a positive integer greater than one, in parallel with a finely tuned array of at least three non-binary weighted PMOS pull-up transistors having widths in a range between W p and 2W p .