Patent ID: 8530351

Claim:
A method of fabricating a semiconductor package, comprising the steps of: forming at least a recess on the surface of a support member; forming a metal layer on the inner surface of the recess by electrolytic plating using the support member as a power feed layer; covering an insulating resin on the surface of the support member and the interior of the recess formed with the metal layer; forming, in the insulating resin in the recess, a via hole to which the metal layer is exposed; forming a conductor via in the via hole so that the conductor is electrically connected with the metal layer; forming one or a plurality of insulating resin layers and wiring layers on the insulating resin in such a manner that the wiring layers are electrically connected to the conductor via; forming, on the uppermost insulating resin layer, a terminal connected to the metal layer through the wiring layers; and removing the support member and exposing a bump filled with the insulating resin and covered with the metal layer and the insulating resin to the bottom surface of the package.