Patent ID: 7473952

Claim:
An integrated circuit comprising: a plurality of active areas formed in a semiconductor substrate with a substrate surface, each active area having two lateral sides extending along a first direction with rows of active areas being separated from each other by isolation grooves, wherein each active area includes a first source/drain region formed adjacent the substrate surface, a second source/drain region formed adjacent the substrate surface, and a channel region separating the first and second source/drain regions, each of the first and second source/drain regions being distanced from and oriented with respect to each other along the first direction; and gate electrodes disposed along the channel regions and being electrically isolated from the channel regions by gate isolating layers; and a plurality of sets of first and second word lines disposed on opposing lateral sides of each of the rows of active areas and with each of the first and second word lines including a length that extends along the first direction, wherein the first and second word lines of each set are connected with each other via the gate electrodes of a corresponding row of active areas.