Patent ID: 7577884

Claim:
A memory circuit testing system comprising: a plurality of memory circuits; and a plurality of testing circuits corresponding to the plurality of memory circuits, each testing circuit sequentially executing a first testing state for writing data to the corresponding memory circuit, a second testing state for waiting until a release signal is input and performing a refresh test for verifying a data holding time, and a third testing state for reading data from each memory circuit, wherein each of the plurality of testing circuits includes a refresh function for performing a refresh operation on a memory circuit, wherein, in the plurality of testing circuits, a testing circuit, which completes the first testing state before another testing circuit ends the first testing state, performs the refresh operation while the another testing circuit performs the first testing operation, and wherein when the plurality of testing circuits ends the first testing state, the plurality of testing circuits, which includes the testing circuit performing the refresh operation, starts executing the second testing state.