Patent ID: 8898387

Claim:
A data caching system comprising: a data storage system including: N data storage devices, and M erasure code devices; at least one processor; at least one memory architecture coupled with the at least one processor; a first software module executed on the at least one processor and the at least one memory architecture, wherein the first software module is configured to perform operations including defining a data stripe that spans one or more of the N data storage devices and one or more of the M erasure code devices; a second software module executed on the at least one processor and the at least one memory architecture, wherein the second software module is configured to perform operations including receiving a data chunk to be written to the data storage system, wherein the data chunk received is larger in size than the capacity of the data stripe; and a third software module executed on the at least one processor and the at least one memory architecture, wherein the third software module is configured to perform operations including writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices, including writing at least a portion of the data chunk to the portion of each of a plurality of data stripes that spans the one or more N data storage devices; and wherein a size of the data stripe is dynamically defined based upon, at least in part, a size of the data chunk received.