Patent ID: 6901454

Claim:
A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising: a command sequence specification receiving unit operable to receive, from the master processor, specification of a command sequence composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and an execution control unit operable to cause any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in the command sequence, wherein the execution control unit includes a concurrent execution control unit operable to, while a circuit is executing a command, detect another command that can be executed by another circuit and cause the other circuit to execute the other command concurrently, wherein the plurality of circuits includes two circuits that are different in function, the command sequence specification receiving unit receives specification of a plurality of command sequences from the master processor, the execution control unit causes any available circuits among the plurality of circuits to execute corresponding commands in a manner in which commands constituting each command sequence are to be executed one by one in order of arrangement in each command sequence, wherein the concurrent execution control unit, while one of the two circuits is executing a command in a command sequence, detects another command in another command sequence that can be executed by another one of the two circuits and causes the other circuit to execute the other command, wherein each of the plurality of circuits can access a same memory, each command sequence includes a memory access command instructing a circuit to access the memory, the execution control unit includes a memory access control unit operable to control two or more circuits that are to execute memory access commands of different command sequences concurrently, to access different areas in the memory, respectively, wherein each memory access command includes a logical address of a location to be accessed, the memory access control unit, when two or more circuits are to execute memory access commands of different command sequences concurrently, converts each logical address contained in the memory access commands to a physical address, each physical address being assigned to a different command sequence, so that the two or more circuits use physical addresses converted from logical addresses to identify areas in the memory to access, respectively.