Patent ID: 8877587

Claim:
A method for fabricating a nonvolatile memory device, comprising: forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked structure including a plurality of interlayer dielectric layers and a plurality of sacrifice layers that are alternately stacked; forming a plurality of channel layers connected to the substrate through the stacked structure of the cell area; forming a first slit in the stacked structure of the cell area so that the first slit has a sufficient depth to pass through at least the lowermost sacrifice layer; forming a second slit in the stacked structure, the second slit including a first portion having a sufficient depth to expose the source region in the cell area and a second portion in the peripheral area that has a smaller width than the first portion; removing the sacrifice layers exposed through the first and second slits; forming a plurality of conductive layers to fill spaces from which the sacrifice layers are removed; forming an insulating layer in the second slit; and forming a source contact by burying a conductive material in the first portion of the second slit having the insulating layer formed therein.