Patent ID: 7737526

Claim:
A semiconductor structure formed in a semiconductor substrate, the substrate not comprising an epitaxial layer, the semiconductor structure comprising an isolation structure, the isolation structure comprising: a floor isolation region of a first conductivity type submerged in the substrate; a filled trench extending downward from a surface of the substrate, the filled trench comprising a dielectric material, a bottom of the filled trench being located above and separated from the floor isolation region; and a sidewall isolation region of the first conductivity type extending downward from a bottom of the filled trench at least to the floor isolation region such that the sidewall isolation region overlaps the floor isolation region, the sidewall isolation region not extending to the surface of the substrate, wherein the floor isolation region, filled trench and sidewall isolation region together enclose an isolated pocket of the substrate, a portion of the substrate adjoining an outside of the isolation structure being of a second conductivity type opposite to the first conductivity type; a well located in the isolated pocket, the well comprising at least an upper portion and a lower portion, the upper portion being located above the lower portion, the lower portion having a maximum doping concentration greater than a maximum doping concentration of the upper portion; and a MOSFET, the MOSFET comprising a gate overlying a surface of the substrate and separated from the substrate by a gate dielectric layer, a body region comprising a channel region, the channel region being located adjacent the surface of the substrate below the gate, a source region located adjacent the surface of the substrate, and a drain region located adjacent the surface of the substrate, the channel region being located between the source and drain regions, the source, drain and body regions being located in the well.