Patent ID: 7683701

Claim:
A Bandgap reference (BGR) circuit configured for reducing mismatch-induced voltage and current offsets within the BGR circuit, the BGR circuit comprising: an operational amplifier having a pair of chopped stabilization input circuits for reducing a voltage offset attributed to the operational amplifier; three current mirror devices coupled for receiving an output of the operational amplifier and configured for generating three substantially identical currents therefrom; three sets of dynamically controlled switches, wherein each set of switches is coupled for receiving a different one of the three substantially identical currents; and digital control logic configured for reducing a current offset attributed to the current mirror devices by controlling the three sets of switches, so that: only one switch in each set of switches is activated for conducting current during a first phase of a multi-phase clocking signal; and only one of the switches activated during the first phase remains activated during each consecutive phase of the multi-phase clocking signal.