Patent ID: 7200021

Claim:
A stacked DRAM Memory Chip for a Dual In Line Memory Module comprising: (a) a predetermined number of at least four stacked DRAM memory dies; (b) wherein the stacked DRAM memory dies are each selectable by a corresponding internal memory rank signal; (c) wherein each DRAM memory die comprises an array of memory cells; (d) wherein a common internal address bus consisting of internal address lines is provided for addressing the memory cells and is connected to all stacked DRAM memory dies; (e) wherein internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies; wherein (f) an integrated redriving unit is provided which comprises: (f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said stacked DRAM memory chip; (f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said stacked DRAM memory chip; and (f3) a memory rank decoder for generating the internal memory rank signal to select a corresponding stacked DRAM memory die in response to external select signals applied to control pads of the stacked DRAM memory chip via an external selection signal bus, wherein a bus width S of the external selection signal bus depends on a number N of DRAM memory chips on the Dual In Line Memory Module and the predetermined number M of stacked DRAM memory dies within the DRAM memory chip as follows: 2 S =N+M.