Patent ID: 7921402

Claim:
A computer-implemented method of modeling a field programmable gate array (FPGA) subject to process variation, comprising: collecting trace-based architecture information for one device setting of an FPGA; obtaining FPGA performance and power distribution for a given set of device parameter values and architectural parameter values based on said trace-based information; and evaluating leakage distribution using a processor when obtaining FPGA performance and power distribution information in response to process variation and considering that each element has specific location variations while elements within a die share global variations; wherein said total leakage is approximated as: I chip ≈ ∑ i ⁢ N i u ⁢ E ⁡ [ I i ] + α gating ⁢ ∑ i ⁢ ( N i t - N i u ) ⁢ E ⁡ [ I i ] where I chip is total leakage and N i u is number of used circuit elements of resource type i and σ gating is average leakage ratio between a power-gated circuit element and a circuit element in normal operation and E[I i ] is expected average leakage for element type i .