Patent ID: 7203611

Claim:
A timing generator generating a timing signal of a predetermined period, comprising: a set/reset latch operable to generate a rising edge of the timing signal according to a set signal and generate a trailing edge of the timing signal according to a reset signal; a set unit operable to supply the set signal to said set/reset latch, said set unit comprising: a first variable delay circuit that delays a given reference clock to output a first set signal; a second variable delay circuit that delays the given reference clock to output a second set signal having a phase different from the first set signal; an OR circuit that computes a logical sum of the first set signal and the second set signal to generate the set signal; and a third variable delay circuit that delays the set signal output from the OR circuit to adjust a skew between the set signal and the reset signal, and a reset unit operable to supply the reset signal to said set/reset latch.