Patent ID: 6920524

Claim:
Mode detection circuitry for initiating a memory access operation in a memory device receiving memory address signals and control signals, the detection circuitry comprising: a first mode detection circuit coupled to receive the memory address signals and the control signals, and in response to receipt of a first combination of control signals and the memory address signals, generating a first mode detection signal to be provided at a first mode output node; a second mode detection circuit coupled to receive the control signals and a clock signal, and in response to receipt of a second combination of control signals and an active clock signal, generating a second mode detection signal to be provided at a second mode output node; a refresh timer having a chain of delay stages having a first delay stage coupled to the first mode output node to receive the first mode detection signal and further having a last delay stage having a timer output node at which a first mode activation signal is provided a time delay following receipt of the last received first mode detection signal, each delay stage having first and second inputs and an output and configured to delay a falling edge of a signal applied to either of the first or second inputs from propagating to its output by a stage time delay, the refresh timer further having a reset circuit coupled to the chain of delay stages and having a disable node coupled to the second mode output node, the reset circuit disabling the chain of delay stages to suppress output of the first mode activation signal in response to receipt of the second mode detection signal; and an output circuit having first and second input nodes coupled to the timer output node and the second mode output node, respectively, the output circuit further having an activation signal node at which an activation signal is provided to initiate a memory access operation in response to receipt of the first mode activation signal or the second mode detection signal.