Patent ID: 7941650

Claim:
A microprocessor based on an event-processing instruction set, comprising: an instruction memory storing a program written with an instruction set architecture provided with an event-processing instruction set; an instruction fetcher fetching instructions for executing the program from the instruction memory; an instruction decoder decoding the fetched instruction and suspending the program execution of a microprocessor being now executed when the decoded instruction is an event-processing instruction; an instruction execution unit stopping executing the decoded instruction if decoded instruction is an event processing instruction no more, processing the event by the instruction if an event is generated, in executing the decoded instruction; a register file composed of at least one event register and a general register to store information on whether or not to transmit events and information of event processing priority; and an event controller re-running the microprocessor to process the events on the basis of the information in the registers in the generation of the events wherein the event register comprises: an event priority register storing information on the processing priority of generated events for controlling transmission path of the event; and an event control register for storing information on approval for the transmission of the generated events.