Patent ID: 7246335

Claim:
A system for analyzing substrate noise (SN), the system comprising: a static timing analysis (STA) module operable to apply an STA algorithm to a description of a digital circuit, application of the STA algorithm generating timing information on one or more gates in the digital circuit; a current waveform generator operable to apply a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit, application of the CWG algorithm generating a current waveform; and a reduced model (RM) generator operable to generate an RM of the digital circuit for simulation, the RM generator generating the RM of the digital circuit according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit, simulation of the RM of the digital circuit generating an indication of noise in a substrate associated with the digital circuit.