Patent ID: 8581634

Claim:
An apparatus comprising: a biasing circuit having: a first capacitor having a first capacitance that receives a first portion of an input signal so as to receive a signal current; and a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascoded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage; a switched capacitor circuit having a second capacitance; and a source follower buffer that is coupled to the biasing circuit and the switched capacitor circuit, wherein the source follower receives the second bias voltage and receives a second portion of the input signal, and wherein the source follower includes a second capacitor having a third capacitance, and wherein the ratio of first capacitance to the combined second and third capacitances is at least one, and wherein the source follower buffer mirrors the signal current.