Patent ID: 8018044

Claim:
A semiconductor device, comprising: a die pad; a semiconductor element loaded on the die pad, having electrodes; a plurality of electrically conductive portions arranged around the die pad; wires for connecting the electrodes of the semiconductor element and the electrically conductive portions; and a sealing resin for sealing at least the semiconductor element, electrically conductive portions and wires, wherein each of the electrically conductive portions includes a metal foil, electrically conductive portion plating layers provided on both upper and lower ends of the metal foil, the die pad includes a die pad plating layer provided in the same plane as lower electrically conductive portion plating layers of the electrically conductive portions, the die pad includes a bank portion that has a concave portion formed therein, the bank portion is formed as a continuous portion so as to surround the semiconductor element as viewed from a top of the semiconductor device, and the bank portion includes a metal foil and both upper and lower plating layers, the semiconductor element is placed on the die pad plating layer in the concave portion of the bank portion, and the lower electrically conductive portion plating layers of the electrically conductive portions, the die pad plating layer of the die pad and the lower plating layer of the bank portion are exposed outside from the sealing resin at their back faces, and central portions of the metal foil in each of the electrically conductive portions and the bank portion are narrowed relative to both the upper and lower electrically conductive portion plating layers, and both the upper and lower plating layers respectively.