Patent ID: 8575954

Claim:
An apparatus for providing electrical connections between a semiconductor wafer comprising an array of semiconductor devices, and a central structure, wherein each of the semiconductor devices comprises a plurality of electrical connection terminals, the central structure having a first and a second side and an array of contact pads electrically connected to central structure through-vias on a regular grid having a pre-determined pitch extending over the usable area of the central structure, the apparatus comprising: a probe chip substrate having a usable substrate area, a probe side and a connection side opposite the probe side, and comprising an array of electrically conductive substrate through-vias and; a plurality of spring contacts on the probe side of the substrate arranged to provide electrical connections to at least one of the devices and one or more electrically conductive routing layers connecting the plurality of spring contacts to a corresponding plurality of the substrate through-vias to form a set of standard electrical connections for the at least one device; wherein the set of standard electrical connections is repeated over the usable substrate area to provide simultaneous electrical connections from the through-vias to more than one element of the array of semiconductor devices; and one or more electrically conductive routing layers on the connection side of the substrate configured to electrically connect each member of the plurality of substrate through-vias corresponding to each set of standard connections to a corresponding set of contact pads on the central structure to provide simultaneous electrical connections from the central structure contact pads over the usable area of the central structure to one or more of the semiconductor devices.