Patent ID: 7420855

Claim:
A semiconductor memory device comprising; a memory-cell matrix being configured to include a plural of memory-cells placed in matrix shape and output in parallel one-word signal of an address selected by a read-out select signal; an amplifying unit being configured to amplify said one-word signal outputted in parallel from said memory-cell matrix and generate one-word data; a data holding unit being configured to hold said one-word data generated by said amplifying unit; a data output unit being configured to output serially said one-word data held in said data holding unit according to an output timing signal; a voltage generating unit being configured to generate a voltage for generating said read-out select signal; and an activating control unit being configured to output an operation control signal for activating said voltage generating unit and said amplifying unit based on said output timing signal, during from when said read-out select signal is generated to when said one-word signal is outputted from said memory-cell matrix based on said read-out select signal and held in said data holding unit.