Patent ID: 8759217

Claim:
A method, for use with an electronic device including a stack comprising a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending to respective ones of the plurality of conductive layers, the method comprising: removing portions of the conductive layers and the dielectric layers in the stack to form landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack, wherein W is the number of conductive layers, the removing step comprising: etching the stack of dielectric/conductive layers to expose landing areas at W−1 conductive layers using a set of M etch masks, the etch masks having mask regions and spaced apart open etch regions, with M being greater than or equal to 2, and with N M being less than or equal to W, where N is an integer greater than or equal to 3; for each etch mask m in the set, where m goes from 0 to M−1: (a) form etch mask m over the contact region, the etch mask having open etch regions over some of the landing areas; (b) etch through N m conductive layers at the open etch regions of mask m; (c) trim etch mask m to increase the size of the open etch regions to overlie additional contact openings; (d) etch N m conductive layers at the increased size open etch regions; and (g) if N is greater than 3, repeat the (c) trim step and the (d) etch step N−3 times, whereby the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks.