Patent ID: 7398409

Claim:
A semiconductor integrated circuit comprising: a plurality of first functional block circuits that are controlled by a system clock to an operation state in an ordinary mode and to a deactivated state after shifting to a power-saving mode; one or more second functional block circuits that are controlled by the system clock to the operation state in the ordinary mode and to maintain the operation state after shifting to the power-saving mode; a power-saving mode signal generation unit which generates a power-saving mode signal that instructs to shift from the ordinary mode to the power-saving mode; and a power-saving control unit which controls to make clock enable signals to be inputted to each of the plurality of first functional block circuits, which make the system clock valid, inactive sequentially in synchronism with the system clock when the power-saving mode signal generated by the power-saving mode signal generation unit becomes active from inactive, wherein the power-saving control unit controls includes an ordinary mode returning control unit which controls to make the clock enable signals to be inputted to each of the plurality of first functional block circuits active sequentially in synchronism with the system clock when the power-saving mode signal generated by the power-saving mode signal generation unit becomes inactive from active.