Patent ID: 6906379

Claim:
An electrically programmable and erasable memory device, comprising: a substrate of semiconductor material having a first conductivity type and a surface; a pair of trenches formed into the substrate surface, wherein a strip of the substrate is disposed between the pair of trenches; a first region of a second conductivity type formed in the substrate strip; a pair of second regions of the second conductivity type formed in the substrate and spaced apart from the first region; a pair of channel regions each extending from the first region to one of the second regions and each having a first portion extending underneath one of the trenches, a second portion not disposed in the substrate strip and extending along the one trench, and a third portion extending along the substrate surface; a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the trenches; and a pair of electrically conductive control gates each disposed over and insulated from one of the channel region third portions.