Patent ID: 7550350

Claim:
A method of forming a flash memory device, comprising the steps of: forming a plurality of cells, a plurality of select transistors, and a transistor over a semiconductor substrate having a cell region and a peripheral region, wherein the plurality of cells and the plurality of select transistors are formed in the cell region, and the transistor is formed in the peripheral region; forming an insulating layer over the plurality of cells, the plurality of select transistors, the transistor and the semiconductor substrate; etching the insulating layer to expose a junction region adjacent to the transistor, thereby forming first contact holes; depositing a first contact material to fill the first contact holes; etching the first contact material and the insulating layer to expose a drain region adjacent to the select transistors, thereby forming a second contact hole; depositing a second contact material to fill the second contact hole; and performing a Chemical Mechanical Polishing (CMP) process to expose a top surface of the insulating layer, thereby forming a first contact and a second contact.