Patent ID: 7464229

Claim:
An apparatus that provides serial-write, random-access read, memory, comprising: a plurality of memory cells; a serial-write data path that serially couples the plurality of memory cells, wherein the serial-write data path enables writing data serially into the plurality of memory cells; wherein the set of memory bits that form the plurality of memory cells are connected in a single serial chain of memory bits; wherein writing a data word to the plurality of memory cells involves directly shifting the values for the bits of the data word into a first memory cell in the plurality of memory cells, where the first memory cell comprises a serial set of bits at the head of the single serial chain of memory bits; wherein writing a bit value to the head of the single serial chain shifts the values stored in all of the memory cells; and a parallel random-access read data path for reading data from the plurality of memory cells in parallel during a random-access read, wherein the random-access read involves selecting and returning the content of an individual memory cell in the plurality of memory cells; wherein a random-access read data output port receives the content of the individual memory cell from the individual memory cell during the random-access read.