Patent ID: 7303953

Claim:
A process for producing an integrated capacitor, comprising the following steps: forming a portion of a first conductive material above a surface of an integrated electronic circuit substrate, said portion being designed to make a first electrical connection; forming a mask on the substrate, said mask having an aperture located at least partly above the portion of the first conductive material; forming a trench extending depthwise into the substrate beneath the surface of the substrate, through the aperture of the mask by anisotropic etching, said trench having walls substantially perpendicular to the surface of the substrate; removing the mask; forming a layer of a second conductive material on the walls of the trench; depositing a layer of an insulating material on the layer of the second conductive material in the trench, followed by a layer of a third conductive material; and forming a second electrical connection connecting to the layer of the third conductive material, wherein the portion of the first conductive material is formed simultaneously with another portion intended to constitute a MOS transistor gate, and wherein the layer of the second conductive material is directly in contact with the portion of the first conductive material.