Patent ID: 8913456

Claim:
A memory comprising: an array of memory cells, wherein each memory cell of the array includes a first supply voltage terminal and a second supply voltage terminal; a plurality of word lines, wherein each memory cell of the array is coupled to a word line of the plurality of word lines; a plurality of voltage supply lines, each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array, wherein each subset of the plurality of subsets includes a plurality of memory cells; a row decoder, the row decoder controls a voltage on each of the plurality of word lines, the row decoder controls a voltage on each of the plurality of voltage supply lines, wherein during at least one mode of operation, for each voltage supply line of the plurality of voltage supply lines, the row decoder provides a low voltage state voltage on a voltage supply line of the plurality of voltage supply lines during a write operation to a subset of memory cells of the plurality of subsets coupled to the voltage supply line and the row decoder provides a high voltage state voltage to the voltage supply line during a read operation of the subset of the memory cells.