Patent ID: 8793547

Claim:
A method for determining the existence of defects in a semiconductor device by using a 3D-Assembly Built in Self-Test (BIST) scheme comprising at least one transmitting (TX) BIST module and at least one receiving (RX) BIST module, the method comprising: launching at a first TX BIST module a first test pattern into the semiconductor device at a first test clock cycle; capturing at a first RX BIST module the first test pattern after the first test pattern has passed through a portion of the semiconductor device being tested for defects; storing the captured first test pattern at a first memory location; launching at the first TX BIST module a second test pattern into the semiconductor device at a second test clock cycle; capturing at the first RX BIST module the second test pattern after the second test pattern has passed through the portion of the semiconductor device being tested for defects; storing the captured second test pattern at a second memory location; analyzing values stored in the first and second memory locations to determine whether a defect exists in the semiconductor device.