Patent ID: 8390035

Claim:
A semiconductor device with multiple die assembly comprising: a programmable semiconductor die substrate; and a context die substrate; said programmable semiconductor die substrate comprises multiple logic blocks; said context die substrate is flipped on said programmable semiconductor die substrate; said multiple logic blocks of said programmable semiconductor die substrate are electrically connected at transistor level or logic gate level, with wirebondless and bumpless electrical connections, via said context die substrate, through pads of a multiple parallel interconnect fabric; said context die substrate implements a custom application of said semiconductor device by using said multiple logic blocks via electrical connections through pads of said multiple parallel interconnect fabric to said multiple logic blocks; a programming interface; wherein said programming interface is located on opposite surface from flipped surface of said context die substrate, so that after connection, said context die substrate is programmed through said programming interface; wherein said context die substrate comprises programmable switches that electrically connect pads on said context die substrate, causing electrical connection between gates and transistors, in logic blocks, on said programmable semiconductor die substrate; wherein said programmable semiconductor die substrate comprises a platform fabric input-output; wherein said platform fabric input-output provides input and output for specific purpose function of serializer and deserializer functional blocks, to convert data between serial data and parallel interfaces in each direction for communications; said programming interface feeds into a first memory which drives said programmable switches and controlled selectors.