Patent ID: 7125807

Claim:
A method for manufacturing non-volatile memory cells on a semiconductor substrate, comprising at least the following steps: forming active areas in said semiconductor substrate, bounded by portions of an insulating layer; forming a first thin layer of tunnel oxide and depositing a first layer of conductive material on said active areas; defining a plurality of floating gate regions, wherein the definition of the floating gate regions comprises the steps of: defining said first layer of conductive material in order to form a plurality of alternated stripes which form first floating gates above pairs of active areas alternated by active areas lacking stripes; forming spacers in the shelter of the side walls of said alternated stripes, depositing a second layer of conductive material in order to fill the space between said spacers so as to form second floating gates above the active areas which previously lacked stripes, and polishing said second layer of conductive material together with said first layer of conductive material and said spacers to the same planar level.