Patent ID: 8334185

Claim:
A method comprising: forming first and second gate stacks, each with a nitride cap, on a substrate; forming an oxide liner over the first and second gate stacks; forming a nitride layer over the oxide liner; forming a resist over the first gate stack; forming nitride spacers from the nitride layer over the second gate stack; forming embedded silicon germanium (eSiGe) source/drain regions for the second gate stack; removing the nitride layer and nitride spacers; forming halo/extension regions for the first gate stack through the oxide liner, or forming oxide spacers from the oxide liner on the first gate stack, and using the oxide spacers to form the halo/extension regions for the first gate stack; forming halo/extension regions for the second gate stack independently from the halo/extension regions for the first gate stack; and removing the nitride caps with ammonia and hydrogen peroxide mixtures (APM) subsequent to forming the halo/extension regions for the first and second gate stacks.