Patent ID: 7322001

Claim:
An integrated circuit device apparatus, comprising: a duty cycle correction (DCC) circuit; a DCC circuit controller coupled to the DCC circuit; an array coupled to the DCC circuit; and a built-in self test circuit coupled to the array and the DCC circuit controller, wherein the built-in self test circuit performs a self test on the array using a current setting of the DCC circuit, the DCC circuit controller increments a setting of the DCC circuit to a next incremental setting in response to a result from the built-in self test circuit indicating a failure of the array, wherein the DCC circuit controller sets the current setting of the DCC circuit as a DCC setting for a chip in response to a result from the built-in self test circuit indicating a pass of the array, and wherein the failure of the array is determined by data that is written to the array failing to match data read from the array.