Patent ID: 8063550

Claim:
A flat panel display, comprising: an insulating substrate including a thin film transistor having at least source and drain electrodes; an insulating layer formed on the insulating substrate and having a via hole to expose one of the source and drain electrodes; an organic EL element formed on the insulating layer and connected to the exposed one electrode through the via hole, and having a lower electrode, an organic film layer, and an upper electrode; and a taper reducing layer formed on the lower electrode and contacting an upper surface of the lower electrode, an edge of the lower electrode, and the insulating layer adjacent to the lower electrode, wherein a taper angle of the taper reducing layer in the via hole has a first taper angle smaller than that of the via hole, and a taper angle of the taper reducing layer at the edge of the lower electrode has a second taper angle smaller than that of the edge of the lower electrode, and wherein the first taper angle and the second taper angle of the taper reducing layer are each greater than 0°.