Patent ID: 7804350

Claim:
A level-shifter circuit comprising: a first voltage supply node configured to receive a first voltage having a first polarity; a second voltage supply node configured to receive a second voltage having a second polarity opposite the first polarity; an input node; a first and second intermediate nodes, at least one of which being an output node; a first selectable current path configured to channel substantial current between the first intermediate node and the second voltage supply node when a signal of the first polarity is present at the input node, and configured to be substantially off when a signal of the second polarity is present at the input node; a second selectable current path configured to channel substantial current between the second intermediate node and the second voltage supply node when a signal of the second polarity is present at the input node, and configured to be substantially off when a signal of the first polarity is present at the input node; and a plurality of field-effect transistors each having a gate terminal, a source terminal, and a drain terminal, the plurality of field-effect transistors comprising: a first transistor having its source terminal connected to the first voltage supply node; a second transistor having its source terminal connected to the first voltage supply node; a third transistor having the source terminal connected to the gate terminal of the second transistor and not connected to the drain terminal of the first transistor, and a drain terminal connected to the first intermediate node; a fourth transistor having its source terminal connected to the drain terminal of the first transistor, the drain terminal of the fourth transistor connected to the first intermediate node, the gate terminal of the fourth transistor connected to the gate terminal of the third transistor and to a first bias voltage source that provides a first bias voltage; a fifth transistor having its source terminal connected to the drain terminal of the second transistor, and a drain terminal connected to the second intermediate node; and a sixth transistor having the source terminal connected to the gate terminal of the first transistor and not connected to the drain terminal of the second transistor, the drain terminal of the sixth transistor connected to the second intermediate node, the gate terminal of the sixth transistor connected to the gate terminal of the fifth transistor and to a second bias voltage source that provides a second bias voltage.