Patent ID: 7973310

Claim:
A semiconductor package structure, comprising: a substrate unit comprising a circuit structure formed thereon and a chip mounting area defined thereupon, the circuit structure having a plurality of bonding pads and a plurality of test pads, each of the bonding pads being arranged within the chip mounting area and connected to each of the test pads; and a first chip stack structure, comprising a plurality of chips, each of the chips having an upper surface, a bottom surface opposite to the upper surface, and a plurality of through silicon plugs disposed therein to form electrical interconnections between the upper surface and the bottom surface, each of the through silicon plugs comprising a first electrode jutting out from one of the upper surface or the bottom surface, and the plurality of through silicon plugs of two adjacent chips being electrically connected through the first electrodes respectively; wherein the first chip stack structure is mounted on the chip mounting area of the substrate unit and at least a portion of the through silicon plugs are electrically connected to the bonding pads, and the plurality of test pads are arranged outside of the chip mounting area.