Patent ID: 7755401

Claim:
A semiconductor device having a DLL circuit, the DLL circuit comprising: a first phase determining circuit that compares a phase of a rising edge of a first clock signal and a phase of a rising edge of a second clock signal to generate a first determining signal; a second phase determining circuit that compares a phase of a falling edge of the first clock signal and a phase of a falling edge of the second clock signal to generate a second determining signal; a first adjusting circuit that adjusts a position of an active edge of a third clock signal based on the first determining signal; a second adjusting circuit that adjusts a position of an active edge of a fourth clock signal based on the second determining signal; a clock generating circuit that generates the second clock signal based on the third and fourth clock signals; and a stop circuit that stops one of adjusting operations by the first and second adjusting circuits in response to an adjusting direction of the active edge of the third clock signal based on the first determining signal and an adjusting direction of the active edge of the fourth clock signal based on the second determining signal being opposite to each other.