Patent ID: 7491643

Claim:
A method of fabricating a semiconductor structure comprising: providing a semiconductor substrate including at least one field effect transistor disposed thereon; forming an insulating interlayer located on said semiconductor substrate and extending atop said at least one field effect transistor, said insulating interlayer having contact openings; forming a diffusion barrier located on at least wall portions of said contact openings; forming a region near a bottom portion of each contact opening that includes atomic species to minimize the Schottky barrier height at the contact opening/diffusion barrier interface, said atomic species including Al, Mo, W, Ni, Cr, Cu, Hf, Ta or Ti; and forming a single phase metal germanide-containing contact material within said contact openings, wherein said forming said single phase metal-germanide-containing contact material includes depositing, in any order, a metal layer and a Ge-containing material, optionally forming a barrier layer, annealing at a temperature of about 400° C. or less to cause reaction between said metal layer and said Ge-containing material; and removing unreacted material.