Patent ID: 6901072

Claim:
A system for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising: first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces; first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and associated first and second memory structures, the first and second FPGAs each configured to perform initial processing of packets received from the associated first and second MAC interfaces, respectively, and to schedule the transmission of packets to the first and second MAC interfaces, respectively, for transmission to one or more destination devices, the first and second FPGAs each further operative to dispatch and retrieve packets to and from the first and second memory structures, respectively; and a third FPGA coupled to the first and second memory structures and a backplane, the third FPGA operative to retrieve and dispatch packets to and from the first and second memory structures and the backplane, compute appropriate destinations for packets and organize packets for transmission.