Patent ID: 7421567

Claim:
A method for speculatively executing instructions in a microprocessor which commits results of non speculative instructions to at least one architected facility, said method comprising the steps of: determining the occurrence of a stall condition during the execution of said non speculative instructions; speculatively executing speculative instructions during said stall condition across multiple pipeline stages; determining the validity of speculative data utilized during said speculative execution; maintaining said speculative data in a non-architected facility when said speculative instructions pass a last of said multiple pipeline stages, the non-architected facility having a non-architected facility register for each register of the at least one architected facility; maintaining a modified vector, having a plurality of modified bits, associated with the non-architected facility, wherein the modified bit vector provides a modified bit for each non-architected facility register, and wherein the modified bit for a non-architected facility register is set in response to a result of a speculative instruction being written to a corresponding non-architected facility register in response to the speculative instruction passing the last of the multiple pipeline stages; tracking a modified state of said speculative data for the speculative instructions during their execution in said multiple pipeline stages of said microprocessor using the modified bit vector, wherein modified bits associated with said speculative data are provided to said speculative instructions which have a dependency on said speculative data that is determined to be modified; speculatively executing speculative instructions having a dependency on a prior speculatively executed speculative instruction utilizing said modified data from said non-architected facility when a corresponding modified bit is a first value; speculatively executing speculative instructions having a dependency on a prior speculatively executed speculative instruction utilizing said speculative data from said architected facility when said modified bit is a second value; and retrieving valid data for use by said non speculative instructions upon removal of said stall condition.