Patent ID: 7462913

Claim:
A semiconductor device comprising: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate, which are stacked in this order; a plurality of first separation trenches disposed on the SOI layer and reaching the buried oxide layer; a plurality of MOS transistors, each of which is surrounded with one of the first separation trenches so that the MOS transistor is isolated; a second separation trench disposed on the SOI layer and reaching the buried oxide layer, wherein the second separation trench includes a plurality of field trenches, which are defined as first to n-th field trenches so that the second separation trench provides n-ply field trenches, and wherein n represents a predetermined natural number; and a plurality of field regions surrounded with the second separation trench, wherein the field regions are defined as first to n-th field regions so that a k-th field region is surrounded with a k-th field trench, and wherein k is a natural number in a range between 1 and n, wherein one of the MOS transistors surrounded with one of the first separation trenches is disposed in each field region so that a k-th MOS transistor is disposed in the k-th field region, the MOS transistors are electrically connected in series between a ground potential and a predetermined power source potential, the first field region is disposed on an utmost outside and on a ground potential side, and the n-th field region is disposed on an utmost inside and on a power source potential side, the first MOS transistor in the first field region has a gate terminal, which provides an input terminal, the n-th MOS transistor in the n-th field region is electrically connected to the power source potential through an output resistor so that an output signal is retrieved from a connection between the n-th MOS transistor and the output resistor, and the n-th field region has an electric potential, which is fixed to the power source potential.