Patent ID: 6954889

Claim:
A circuit for modifying output data of storage means, the storage means outputting a data word with a width of 2^N (where N is a natural number) bytes, the data word being stored at respective addresses, starting at an address specified as a multiple of 2^N by an address signal, on the storage means, the circuit comprising: a data register for retaining correction data with the width of 2^N bytes thereon; an address register for retaining a correction address thereon; a correspondence detector, which receives the address signal and the correction address and determines whether or not correspondence is found between the correction address and one of 2^N addresses starting at, the address specified by the address signal or between the correction address and one of 2^N addresses preceding the address specified by the address signal; and a stored data selecting section for dividing a given word of the output data of the storage means and the correction data into a plurality of bytes, and selectively outputting in the same word, on a byte-by-byte basis, either an Mth byte (where M is an integer and 0<M<2^N) of the divided output data of the storage means or an Mth byte of the divided correction data in accordance with the address signal and the correction address if correspondence is found by the correspondence detector, wherein the circuit delivers the output of the stored data selecting section as modified stored data.