Patent ID: 6949803

Claim:
A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate along with non-volatile memory cells that include floating gate transistors, said process comprising at least the following steps: defining respective active areas for HV transistors and floating gate transistors in a common semiconductor substrate, with said active areas being separated from each other by insulating regions; depositing a layer of gate oxide onto said active areas; depositing a layer of polysilicon onto the gate oxide layer; first masking and then etching through the polysilicon layer to form gate regions of said HV transistors; performing a first dopant implantation to form first junction portions of the HV transistors; conformably depositing a dielectric layer onto the whole substrate to provide an interpoly layer of said floating gate transistor; forming openings at the first junction portions of the HV transitors; and performing, through said openings, a second dopant implantation to form second junction portions of the HV transistors, with perimeter areas of the gate regions and the active areas of the floating gate transistors being screened off by said dielectric layer.