Patent ID: 7366874

Claim:
A very long instruction word (VLIW) processor, comprising: a dispatch unit comprising: a packet buffer for storing sub-instructions of a VLIW instruction to be executed; and a decoding unit for decoding each sub-instruction within the VLIW instruction to be executed, wherein the dispatch unit dispatches each sub-instruction of the VLIW instruction to a corresponding functional unit (FU) based on (i) decoding results of the sub-instruction, (ii) whether the sub-instruction is stored in an odd or even position in the packet buffer; and (iii) whether the sub-instruction is located in an immediate value operation (IMM) position, a no operation (NOP) position, or an active engine control unit (ACT) position within the VLIW instruction to be executed; and at least one or more operation engines, each comprising a plurality of FUs for performing a predetermined operation in response to the sub-instructions that are dispatched by the dispatch unit, wherein the corresponding functional unit (FU) is chosen from the plurality of functional units of a same type based on the odd or even position in the packet buffer where the sub-instruction is stored.