Patent ID: 7406046

Claim:
A scheduler for a memory system for buffer storage of data processed by at least one data processing unit, comprising: a write unit for writing data objects to the memory system, said write unit: receiving data packets from at least one data source at a variable data transmission rate, the data packets having payload data; calculating attribute data for each received data packet; writing the data contained in the data packet to the memory system as a data object string including data objects linked to one another, the data object string including pointer data for linking the data objects, the attribute data calculated, and the payload data; and inserting filling objects into the memory system between the data objects linked to one another to compensate for the variable data transmission rate when writing the data object string to the memory system; a counter connected to said write unit and incremented by said write unit when the data object string is written to the memory system to correspond to an amount of data contained in the data packet and the filling data in the tilling objects; a time out signaling unit connected to said counter, said time out signaling unit: signaling, when said counter reaches a threshold value, to the data processing unit that at least one of the data object and the filling object buffer stored in the memory system is ready to be read; and subsequently decrementing said counter corresponding to the data contained in the data object provided; said write unit having a control path and a data path; said data path having a counting device incremented linearly in accordance with a linear nominal data arrival curve; and said data path having an effective data address generator calculating a time wheel distribution as a function of a calculated cumulative amount of data and of a count produced by the counting device, as follows: W α * ⁡ ( t ) = { R ′ ⁡ ( t ) if ⁢ ⁢ W α * ⁡ ( t ) > α ⁡ ( t ) max ⁡ [ R ′ ⁡ ( t ) , α ′ ⁡ ( t ) ] if ⁢ ⁢ W α * ⁡ ( t ) = α ⁡ ( t ) α ′ ⁡ ( t ) if ⁢ ⁢ W α * ⁡ ( t ) < α ⁡ ( t ) } , where R(t) is an amount of data in a received data packet, and α is the linear nominal data arrival curve.