Patent ID: 8247291

Claim:
A method of fabricating an integrated circuit device, the method comprising: providing a substrate including an insulation layer and a hard mask layer thereon; forming first and second preliminary mask structures on the hard mask layer in respective first and second regions of the substrate, the second preliminary mask structure having a greater width than the first preliminary mask structure; forming spacers on opposing sidewalls of the first and second preliminary mask structures, wherein each of the first and second preliminary mask structures comprises a sacrificial pattern and a dummy pattern thereon having an etch selectivity relative to the sacrificial pattern, wherein forming the first and second preliminary mask structures comprises: providing a sacrificial layer and a dummy layer on the hard mask layer; patterning the dummy layer using respective masks to define the respective dummy patterns of the first and second preliminary mask structures in the first and second regions; and isotropically etching the sacrificial layer using the respective dummy patterns as masks to define the respective sacrificial patterns of the first and second preliminary mask structures and such that a greater portion of the dummy pattern of the first preliminary mask structure is removed as compared to the dummy pattern of the second preliminary mask structure, and wherein forming the spacers comprises: conformally forming a spacer layer on upper surfaces and on the opposing sidewalls of the first and second preliminary mask structures; and anisotropically etching the spacer layer on the upper surfaces of the first and second preliminary mask structures to remove spacer layer therefrom and to remove the dummy pattern from the first preliminary mask structure while maintaining at least a portion of the dummy pattern of the second preliminary mask structure; selectively removing the first preliminary mask structure from between the spacers in the first region such that the second preliminary mask structure remains between the spacers in the second region; etching the hard mask layer using the spacers and the second preliminary mask structure as a mask to define a first mask pattern comprising the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern comprising the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region; patterning the insulation layer using the first mask pattern as a mask to define a first trench in the first region and using the second mask pattern as a mask to define a second trench in the second region having a greater width than the first trench; and forming first and second conductive patterns in the first and second trenches, respectively.