Patent ID: 7248535

Claim:
A semiconductor memory device, comprising: a plurality of sub-word lines; a plurality of sub-word line drivers each connected to corresponding sub-word lines, the sub-word line drivers connecting the corresponding sub-word lines to a first voltage in response to corresponding word line enable signals and sub-word line driving signals during a precharge operation; a plurality of driving signal generating circuits each connected to a corresponding sub-word line driver and configured to provide the sub-word line driving signals thereto; and word line enable drivers each connected to a corresponding sub-word line driver and configured to provide the word line enable signals thereto, wherein each of the word line enable drivers comprises: a decoder input terminal configured to receive an upper decoding signal; a decoder control terminal; a first decoder pull-down unit configured to pull down the decoder control terminal to a second voltage in response to the upper decoding signal and a predetermined leakage interruption signal; a second decoder pull-down unit configured to pull down the decoder control terminal to the first voltage in response to a preliminary signal that is used to generate the word line enable signals; a decoder pull-up unit configured to pull up the decoder control terminal in response to the upper decoding signal; and a driving unit configured to generate the preliminary signal pulled down to the first voltage in response to voltage of the decoder control terminal, wherein the leakage interruption signal is adjusted to the first voltage when each word line enable signal is activated.