Patent ID: 8041899

Claim:
A write back allocate system, comprising: a store request circuit; a processor to generate a store request that comprises an information unit and an information unit address; and a cache module, coupled to the store request circuit and to a high level memory unit; wherein a single cache module line comprises multiple segments, each segment to store a single information unit; wherein a content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that comprises multiple segment fetch operations; and wherein the store request circuit comprises a snooper and a controller; wherein the snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst; and wherein the controller is to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address and if the cache module declined a previous request to receive the information unit.