Patent ID: 7687341

Claim:
A method for fabricating a semiconductor device, comprising: forming at least one gate pattern over a substrate where a cell region and a peripheral region are defined; forming a first insulation layer over the at least one gate pattern and the substrate in the cell region and the peripheral region; etching the first insulation layer only in the peripheral region to form at least one gate pattern spacer in the peripheral region, thereby forming a first resultant structure; forming a second insulation layer over the first resultant structure in the cell region and the peripheral region; etching a portion of the second insulation layer only in the cell region, thereby forming a second resultant structure; forming an insulation structure over the second resultant structure in the cell region and the peripheral region; and etching the insulation structure, the second resultant structure and the first insulation layer only in the cell region until exposing the gate patterns to form a contact hole; wherein etching a portion of the second insulation layer only in the cell region comprises etching the second insulation layer in a manner that a total thickness of the first insulation layer and the etched second insulation layer in the cell region ranges between a minimum thickness which reduces impurity penetration while forming the insulation structure and a maximum thickness which secures a contact hole margin.