Patent ID: 7656201

Claim:
An output buffer circuit comprising: a driver circuit including a first transistor and a second transistor for outputting a driver signal to an output node, said first and second transistors being connected in series via said output node; a driver control circuit including: a first driver control circuit for controlling said first transistor based on a first input signal supplied via a first input node, and a second driver control circuit for controlling said second transistor based on a second input signal supplied via a second input node; and a capacitor circuit including: a first capacitor connected between said output node and a first intermediate node, a second capacitor connected between said first input node and said first intermediate node, a first gate circuit whose conduction status is controlled based on said first input signal and having a first terminal connected to said first intermediate node and a second terminal connected to a second intermediate node between said first driver control circuit and said first transistor, a second gate circuit whose conduction status is controlled based on said second input signal and having a first terminal connected to said first intermediate node and a second terminal connected to a third intermediate node between said second driver control circuit and said second transistor, and an inverter circuit connected between said first input node and said first capacitor.