Patent ID: 8861568

Claim:
A method of measuring clock phase error comprising: receiving, at a chirp receiver, a chirp signal consisting of a plurality of chirps that are pulsed frequency sweeps transmitted by a chirp transmitter; mixing the received chirp signal with a locally generated chirp signal that is driven into synchronism with the received chirp signal; adjusting samples of the mixed signals corresponding to multiple sweeps based on estimated clock phases and expected phase rotations of direct path signal components of the respective received chirps to align edges of adjacent chirps and concatenating the samples to produce a sinusoidal signal over a measurement epoch; processing the concatenated samples in a frequency domain and determining a frequency corresponding to a direct path signal component as the lowest frequency associated with power above a predetermined threshold; calculating a time delay associated with the lowest frequency determined for the direct path signal component and determining a clock phase error between a receiver clock and the received signal.