Patent ID: 8179720

Claim:
A NAND flash memory comprising: a NAND string in which a plurality of memory cells are connected in series to store information corresponding to an amount of charges held in a charge holding layer, the memory cells respectively comprising a semiconductor well on a surface of a semiconductor substrate, a first insulation film on the semiconductor well, the charge holding layer on the first insulation film, a second insulation film on the charge holding layer, and a control gate above the second insulation film; and a control circuit configured to control voltages applied to the control gate and the semiconductor well, wherein in a write operation, the control circuit applies a writing voltage between the control gate of a selected memory cell to be written and the semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gates of unselected memory cells not to be written.