Patent ID: 7779319

Claim:
A method for generating calibration data for a delay test on one or more input-output circuits, comprising: generating calibration data for the delay test of each input-output circuit on a chip by determining an amount of delay present in each delay testing path excluding the input-output circuit buffers themselves; and determining delay calibration data for all of the input-output circuits on the chip in a first group of two or more but less than all of a number of testable input-output circuits on the chip at the same time, where a first delay test path includes a launch bus and a capture strobe bus through a first launch register to a first capture register but excludes the input-output circuit buffers themselves that are located in a first input-output circuit, where the first input-output circuit is part of the first group of input-output circuits that are being determined at the same time, and a second delay test path includes the launch bus and the capture strobe bus through a second launch register to a second capture register but excludes the input-output circuit buffers themselves that are located in a second input-output circuit, where the second input-output circuit is part of the first group of input-output circuits that are being determined at the same time.