Patent ID: 8751714

Claim:
A system, comprising: a plurality of processors, each having a local cache and operatively coupled to a respective memory store having a portion of shared memory for the system; and Peripheral Component Interconnect Express (PCIe) interconnect and interface circuitry, operatively coupling at least two of the processors, the PCIe interface circuitry including, circuitry and logic to implement a PCIe Physical Layer (PHY) including a PCIe PHY logical sub-layer and a PCIe PHY electrical sublayer; logic to implement a protocol layer, routing layer and link layer for a QuickPath Interconnect (QPI) protocol over the PCIe PHY; logic to implement an interface between the QPI link layer and the PCIe PHY logical sub-layer under which the QPI link layer interface comprises a 160-bit (160b) interface and the PCIe PHY logical sub-layer interface comprises a 128-bit (128b) interface; a transmit port including logic to implement a 160b to 128b conversion to interface data to be transmitted via the PCIe PHY from the QPI link layer interface to the PCIe PHY logical sub-layer interface; and a receive port including logic to implement a 128b to 160b conversion to interface data received at the receive port via the PCIe PHY from the PCIe PHY logical sub-layer interface to the QPI link layer interface, wherein the at least two processors are configured to implement the QPI protocol using corresponding QPI messaging sent over PCIe interconnect and interface circuitry to support coherent memory transactions in the system.