Patent ID: 8330267

Claim:
A semiconductor package, comprising: a patterned metal foil having a first surface and a second surface opposite to the first surface; a first patterned dielectric layer disposed on the second surface of the patterned metal foil, wherein the first patterned dielectric layer has a plurality of openings exposing at least a portion of the patterned metal foil to form a plurality of contacts for downward external electrical connection; a second patterned dielectric layer disposed over the patterned metal foil, wherein the second patterned dielectric layer exposes at least a portion of the patterned metal foil to form a plurality of contacts for upward electrical connection; a chip disposed on the first surface of the patterned metal foil; an adhesive layer disposed between the chip and the patterned metal foil; a plurality of wires respectively connecting the chip and the patterned metal foil, wherein a portion of the first patterned dielectric layer is disposed below intersections between the wires and the patterned metal foil; and a molding compound disposed on the first surface, wherein the molding compound covers the chip and the wires, wherein a total thickness of the patterned metal foil, the first patterned dielectric layer, and the second patterned dielectric layer substantially ranges from 40 micrometers to 130 micrometers.