Patent ID: 7383420

Claim:
A device comprising: an interleaved multi-threaded processor comprising: at least one register file; a plurality of execution units coupled to the at least one register file; wherein the interleaved multi-threaded processor is adapted to: receive a first program instruction, the first program instruction including a first source field having a first index value and a first destination field having a second index value; process the first program instruction at the plurality of execution units; read the first index value to be used as a first index to the at least one register file, the first index value identifying a first location in the at least one register file; retrieve a first register out value from the first location of the at least one register file based on the first index value; perform an operation on the first register out value to obtain a first result; write the first result to a second location of the at least one register file based on a third index value; wherein the third index value is determined by: retrieving a second register out value from a third location of the at least one register file based on the second index value; performing an operation on the second register out value to determine the third index value; and wherein the first program instruction comprises four separate instructions and is executed in seven clock cycles, wherein the seven clock cycles comprise one clock cycle for decoding, one clock cycle for reading operands from the at least one register file, four clock cycles for executing the four separate instructions, and one clock cycle for writing results to the at least one register file.