Patent ID: 7423310

Claim:
A row of charge-trapping memory cells, each of said charge-trapping memory cells in said row comprising: a ridge of semiconductor material having a first sidewall and an opposed second sidewall, the ridge being configured as a fin structure; a source region disposed within the ridge of semiconductor material; a drain region disposed within the ridge of semiconductor material and being laterally spaced from the source region such that the source region and the drain region are arranged within the fin structure at a distance from one another along a longitudinal axis that extends parallel to an upper surface of the ridge of semiconductor material; a first memory layer sequence of dielectric material arranged on the first sidewall, the first memory layer sequence including a memory layer provided for charge-trapping between confinement layers; and a second memory layer sequence of dielectric material arranged on the second sidewall, the second memory layer sequence including a memory layer provided for charge-trapping between confinement layers; said row of charge-trapping memory cells comprising: a first conductive layer, comprising both a gate electrode and a wordline, having a surface arranged over the first memory layer sequence, said surface of said first conductive layer parallel to and extending continuously along the row of charge-trapping memory cells; and a second conductive layer, comprising both a gate electrode and a wordline, having a surface arranged over the second memory layer sequence, said surface of said second conductive layer parallel to and extending continuously along the row of charge-trapping memory cells.