Patent ID: 7072819

Claim:
A computer-implemented method for debugging a circuit design given a first set of at least one candidate branch, a second set of at least one correction probe, and a third set of at least zero restriction probe, comprising the steps of: obtaining said circuit design, said first set of at least one candidate branch, said second set of at least one correction probe, and said third set of at least zero restriction probe, whereby the existence of some functional mistake in the circuit design is clearly shown with definite boundaries; building a representation of the relationships among objects including said circuit design, said first set of at least one candidate branch, said second set of at least one correction probe, and said third set of at least zero restriction probe; and identifying combinations of behaviors at members of said first set of at least one candidate branch to make said circuit design satisfy the expectation expressed in said second set of at least one correction probe and said third set of at least zero restriction probe, whereby the information on the location of the functional mistake is derived.