Patent ID: 7853733

Claim:
An operational circuit which performs a predetermined operation on M data (M is an integer) discretely stored in an external storage device using a DMA transfer according to a descriptor, the operational circuit comprising: N address registers (N is an integer) each retaining an address on an external storage device where data associated with the address is stored, as address information in the DMA transfer; and a data register retaining data to be stored in the external storage device, wherein when M is greater than N, and a data size of each M data is greater than that of the data register, a first cycle is assigned to first to N data and a second cycle is assigned to N+1 to M data, (1) partial data of each of M data, having a data size that is smaller than or equal to that of the data register, is read from an address space specified by a corresponding one of N address registers by the DMA transfer according to the descriptor, (2) the predetermined operation is performed on the partial data and data stored in the data register, and (3) a result of the predetermined operation is stored in the data register, in the first cycle, the (1)-(3) processes are performed on partial data of the respective first to N data in this order, and when the first to N data include non-processed partial data, the (1)-(3) processes are performed on remaining partial data of the respective first to N data in this order, in the second cycle, the (1)-(3) processes are performed on partial data of the respective N+1 to M data in this order, and when the N+1 to M data include non-processed partial data, the (1)-(3) processes are performed on remaining partial data of the respective N+1 to M data in this order, and in the descriptor, a source address, a source data size, a source address number, and a destination address are included as information required for controlling the first and second cycles, the source address, the source data size, and the destination address are described cyclically utilizing a number of address registers as a unit in one descriptor, and at least one of the first and second cycles is controlled by one descriptor.