Patent ID: 8239438

Claim:
A computer-implemented method comprising: providing a computer processor comprising: a vector arithmetic unit comprising a plurality of processing lanes, each processing lane configured to, in parallel, perform one or more arithmetic operations on a predefined count of operands; and a dot product support unit comprising at least one aligner per processing lane, a compressor, and an adder; wherein the computer processor is configured to perform a dot product operation by: by the dot product support unit, aligning and then summing products generated by the plurality of processing lanes of the vector arithmetic unit; by the computer processor, receiving a single, predefined instruction for adding at most a predefined count of floating point addends, wherein the predefined count of floating point addends is equal to a product of: (i) a count of the plurality of processing lanes and (ii) the predefined count of operands; wherein the plurality of processing lanes is fewer in number than the predefined count of floating point addends, wherein the predefined instruction is identifiable by an associated opcode; and responsive to the predefined instruction for adding at most the predefined count of floating point addends, performing, by the vector arithmetic unit and the dot product support unit of the computer processor, a predefined operation to add the at most the predefined count of floating point addends using a single pass through the fewer processing lanes of the computer processor, wherein the predefined operation comprises: computing, in parallel, a first arithmetic result of adding a respective pair of floating point addends in each of one or more of a plurality of processing lanes of the vector arithmetic unit; transferring the first arithmetic result of each pair of floating point addends from the one or more processing lanes of the vector arithmetic unit to the dot product support unit; computing a second arithmetic result in the dot product support unit, the second arithmetic result being an arithmetic result of aligning, compressing, and adding each first arithmetic result received from the one or more processing lanes, to generate a normalized arithmetic result of adding at most the predefined count of floating point addends; wherein the instruction is configured to designate one or more vector arithmetic units to perform vector operations and one or more vector arithmetic units to perform scalar operations; and wherein the scalar operations are configured to perform a combination of both addition and subtraction operations.