Patent ID: 8431933

Claim:
A memory layout structure, comprising: an active area array disposed in a substrate, wherein the active area array comprises a plurality of active areas arranged into a plurality of columns of active areas and a plurality of rows of active areas, and the active areas each have a lengthwise direction, the lengthwise direction and each of the rows of active areas form an included angle not equal to zero and not equal to 90 degrees; a plurality of recessed gate structures disposed in the active areas at a middle portion respectively, and a first diffusion region and a second diffusion region disposed in each of the active areas at two sides of the middle portion respectively, wherein each of the active areas contains only one of the recessed gate structures; a plurality of word lines disposed above the columns of active areas respectively, wherein the word lines are each electrically connected to the recessed gate structures thereunder; a plurality of bit lines disposed above the rows of active areas respectively, wherein, the bit lines and the word lines cross over each other, and the bit lines are each electrically connected to the first diffusion regions thereunder; and a plurality of capacitor structures disposed above the second diffusion regions respectively and electrically connected to the second diffusion regions through self-aligned node contact plugs respectively, wherein the self-aligned node contact plugs are each disposed between two adjacent ones of the word lines and between two adjacent ones of the bit lines, and the self-aligned node contact plugs each have only a portion disposed above only a portion of the corresponding second diffusion region.