Patent ID: 8291201

Claim:
A circuit arrangement, comprising: an execution pipeline configured to execute instructions using a plurality of pipeline stages, the plurality of pipeline stages including a first pipeline stage and a second pipeline stage, the first pipeline stage including a first latch and first execution logic coupled to an output of the first latch and configured to process input data stored in the first latch, and the second pipeline stage including a second latch and second execution logic coupled to an output of the second latch and configured to process input data stored in the second latch, wherein the second latch is coupled intermediate to the first and second execution logic to latch output data from the first execution logic for use as input data by the second execution logic, and wherein the first latch is configured to be powered by a power supply signal and clocked by a clock signal; and control logic coupled to the first and second latches and configured to operate in first and second modes, wherein in the first mode the control logic clocks the first and second latches such that the first and second pipeline stages perform steps for separate instructions in each clock cycle, and in the second mode the control logic sets the second latch to a transparent state to merge the first and second execution logic together such that the first and second pipeline stages perform steps for the same instruction in each clock cycle, wherein the control logic is further configured to reduce a clock frequency of the clock signal used to clock the first latch or a voltage of the power supply signal that powers the first latch when in the second mode.