Patent ID: 8078949

Claim:
A semiconductor memory device, comprising: a parity generating circuit for generating parity data corresponding to input data; a normal memory cell array for storing the input data; a parity memory cell array for storing the parity data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result, wherein the parity data latching section outputs the data latched by the parity data latching section externally of the semiconductor memory device.