Patent ID: 8533543

Claim:
A system comprising: a first chip; a second chip; a first connection that couples a first pin of the first chip to a first pin of the second chip; a second connection that couples a second pin of the second chip to a second pin of the first chip; and a data transfer interface connection that couples a third pin of the first chip to a third pin of the second chip, the data transfer interface connection being configured to provide a plurality of enable signals indicating a plurality of data transfer windows, respectively, to transfer data between the first chip and the second chip via at least one of the first connection and the second connection, wherein the first pin of the second chip is connected via a direct on-chip connection with the second pin of the second chip, to form a return path directly connecting the first pin of the second chip to the second pin of the second chip, wherein the first connection is configured to provide an initial signal from the first chip to the second chip during a time period between two of the plurality of data transfer windows and the second connection is configured to return the initial signal received via the first connection back to the first chip, and wherein the first chip comprises circuitry configured to compare the returned signal with the initial signal.