Patent ID: 8189377

Claim:
A semiconductor device having a plurality of nonvolatile memory cells, a high breakdown MISFET, and a low breakdown MISFET having a thinner gate insulating film than a gate insulating film of the high breakdown MISFET, each of the memory cells including a control gate and a floating gate formed over a semiconductor substrate, the semiconductor device comprising: a capacitance section including first impurity regions as control gate regions formed in the semiconductor substrate and a first portion of the floating gate; a data write/erase charge injection/discharge section including second impurity regions formed in the semiconductor substrate and a second portion of the floating gate; and a data read MISFET including third impurity regions formed in the semiconductor substrate and a third portion of the floating gate, wherein a plan area of the first portion of the floating gate is greater than respective plan areas of the second and third portions, wherein structures of the third impurity regions are same as structures of source and drain regions of the low breakdown MISFET, wherein each the source and drain regions of the low breakdown MISFET has a first region of a first conductivity type, a second region of the first conductivity type having a higher impurity concentration than the first region, and a third region of a second conductivity type opposite to the first conductivity type, and wherein the first, second and third regions are formed in a well region of the second conductivity type formed in the semiconductor substrate and having a lower impurity concentration than the third region.