Patent ID: 7197445

Claim:
A method of simulating a circuit design within a logic simulation tool using inertial rejection comprising: representing a plurality of scalar signals over time as a series of transaction objects, wherein each transaction object comprises a start index, an end index, a value for each of the plurality of scalar signals, and a single time at which the value of each of the plurality of scalar signals is transacted within the logic simulation tool, wherein each scalar signal of a transaction object is associated with an index within a range specified by the start index and the end index of that transaction object, and wherein the start index and end index of each transaction object indicate non-null values for the plurality of scalar signals within each transaction object; constructing and adding a new transaction object for the plurality of scalar signals; comparing values of the plurality of scalar signals of the new transaction object with values of the plurality of scalar signals for at least one existing transaction object, wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window; modifying at least one of the scalar signals of the circuit design by manipulating at least one of the start indices or the end indices of the at least one existing transaction object; and performing functional simulation or timing simulation upon the circuit design by processing signals specified by the transaction objects.