Patent ID: 8502303

Claim:
A semiconductor device comprising: a first-conductive type first silicon pillar on a first-conductive type silicon substrate: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; and a third silicon pillar on a top of the first silicon pillar, wherein: the silicon substrate has a second-conductive type high-concentration impurity region formed in a part thereof; and the third silicon pillar including a second-conductive type high-concentration impurity region in a peripheral surface thereof except in at least a central portion of a contact surface region with the first silicon pillar, the central portion characterized by a diameter that is less than a diameter of the third silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity, where the second-conductive type is of an opposite conductivity to the first conductive type and thereby a p-n junction resides at an interface thereof, and wherein the first-conductive type impurity region has a length that extends from a base portion of the second-conductive type high-concentration impurity region to the contact surface region, and the length is greater than that of a depletion layer extending from the base portion.