Patent ID: 7169662

Claim:
A method for making a semiconductor structure in a substrate having an array area and a periphery area, the method comprising: forming a transistor in the array area and a transistor in the periphery area; forming a stopping layer over the transistors in the array area and the periphery area, the stopping layer having a characteristic to stop an etching process when consumed by the etching process; forming over the stopping layer a nonconductive layer; forming openings by etching the nonconductive layer and the stopping layer, the openings exposing a polycrystalline silicon layer of the transistor in the array area and the transistor in the periphery area; and forming a metallization layer by filling the openings with conductive substances and compounds, the metallization layer forming a local interconnect layer for the transistor in the array area and forming a strapping layer for the transistor in the periphery area.