Patent ID: 7155698

Claim:
A method for locating areas in a mask layout of an integrated circuit which are impacted by aberrations in projection printing comprising the steps of: a) generating a description of a mask layout wherein the layout is partitioned into rectangles and triangles, b) generating a description of an aberration function wherein the description of the aberration function is modeled as producing spillover between mask openings with a localized pattern that is the inverse Fourier transform of the optical path difference function in the pupil of the projection printing system, c) sequentially comparing the aberration function to the mask layout geometry as the mask layout is scanned using an algorithm based on polygons in the mask layout, the polygons in the mask layout being partitioned into rectangles and triangles and the rectangles and triangles in the mask layout being compared with the aberration function, and wherein each pixel in a rectangle or triangle has a cumulative weight based on the pattern pixel weight in the rectangular or triangular region above and to one side of the weighted pixel, and including rank ordering all mask layout edges, corners, and other geometries according to degree of similarity to the aberration function, and d) identifying any area in the mask layout tending to match the aberration function.