Patent ID: 7535392

Claim:
A continuous-time delta sigma modulator, comprising: a series of integrators, coupled in series, generating an analog output signal according to an analog input signal; a quantizer, coupled to a last integrator with the highest order in the series, quantizing the analog output signal according to a reference voltage to generate a digital output signal as the output of the continuous-time delta sigma modulator, wherein the digital output signal has N kinds of values; and a loop delay compensation circuit, coupled to the quantizer, adjusting the reference voltage of the quantizer according to the digital output signal to compensate the continuous-time delta sigma modulator for a loop delay, comprising: a N-to-1 coding circuit, coupled to the quantizer, enabling one of N selection signals according to the digital output signal; and a reference voltage selection circuit, coupled to the N-to-1 coding circuit, generating a voltage level corresponding to the enabled selection signal as the reference voltage.