Patent ID: 7504732

Claim:
A stacked integrated circuit comprising: a first thinned substantially flexible integrated circuit layer having a bottom-side surface; a second thinned substantially flexible integrated circuit layer having a top-side surface, wherein the first integrated circuit layer overlies the second integrated circuit layer such that the bottom-side surface overlies at least part of the top-side surface, and wherein at least one of the first and second thinned substantially flexible integrated circuit layers comprises a low stress dielectric layer; and an inter-layer stacked between the bottom-side surface of the first integrated circuit layer and the top-side surface of the second integrated circuit layer, wherein the inter-layer includes at least a first inter-layer portion and a second inter-layer portion that is electrically isolated from at least the first inter-layer portion, wherein each one of the first and second inter-layer portions forms a bond between the bottom-side surface of the first integrated circuit layer and the top-side surface of the second integrated circuit layer, and wherein only one of the first and second inter-layer portions forms at least one interconnection electrically coupling the first integrated circuit layer to the second integrated circuit layer for the transfer of information, wherein the at least one interconnection between the first and second integrated circuit layers is formed only on the bottom-side and top-side surfaces.