Patent ID: 6950884

Claim:
A device for a bidirectional transfer of data, comprising: a first processor; a second processor; an input memory connected to said second processor, said input memory having a plurality of memory blocks for receiving output data from said first processor; an output memory with a plurality of memory blocks for providing input data for said first processor, said output memory connected to said second processor; an input control information memory connected to said input memory and storing an item of binary control information for each of said memory blocks of said input memory; an output control information memory connected to said output memory and storing an item of binary control information for each of said memory blocks of said output memory; and at least one direct memory access (DMA) channel for writing the output data from said first processor to said input memory and for reading the input data for said first processor from said output memory, said DMA channel connected to said first processor, said input memory and said output memory, access to said input memory and said output memory being regulated such that a write access of said first processor and a read access of said second processor to said input memory is permitted on a basis of the item of control information stored in said input control information memory, and the write access of said second processor and the read access of said first processor to said output memory is permitted on a basis of the item of control information stored in said output control information memory.