Patent ID: 8054055

Claim:
A low dropout voltage regulator (LDO) comprising: a bias voltage generator producing one or more bias voltages; a differential error amplifier having one input receiving a reference voltage and a second input receiving a function of the output voltage and producing a differential output voltage; an output Driver having its input coupled to a first output of said error amplifier and its output terminal providing the output voltage with its substrate terminal capacitively coupled to the output node and resistively coupled to the input supply node; a controlled active load coupled to the output node and having its control terminal coupled to a function of the second output of said error amplifier; and a Double Ended Cascode Miller compensation block having both inputs individually capacitively coupled to the output node and its output coupled to the input of said output Driver, wherein said controlled active load comprises a PMOS sink transistor operatively coupled between the output node and the common node.