Patent ID: 7220650

Claim:
A method of forming an integrated circuit transistor, comprising: providing a semiconductor substrate with a gate structure formed thereon; forming at least one dielectric layer overlying the semiconductor substrate, wherein the at least one dielectric layer comprises at least one first portion along at least one sidewall of the gate structure, and at least one second portion outside the gate structure along the surface of the semiconductor substrate; forming at least one first doped region in the semiconductor substrate laterally adjacent to the at least one first portion of the at least one dielectric layer, wherein the at least one second portion of the at least one dielectric layer remains overlying the at least one first doped region; forming a sidewall spacer overlying the at least one dielectric layer along the at least one sidewall of the gate structure, wherein the sidewall spacer is formed using a blanket deposition process and a dry etch process; and forming at least one second doped region in the semiconductor substrate laterally adjacent to the sidewall spacer.