Patent ID: 8687739

Claim:
A circuit for demodulating an radio frequency (RF) signal to baseband comprising: a single-bit analog-to-digital (A/D) demodulator, having an input conversion bandwidth, configured to receive an RF signal, having an RF carrier frequency, quantize the RF signal based on the in-phase sampling clock to generate an in-phase digital signal, and quantize the RF signal based on the quadrature sampling clock to generate a quadrature digital signal; wherein the single-bit A/D demodulator further comprises: first through (Kâˆ’1) th summers, the i th summer being configured to receive the i th in-phase analog signal, the i th quadrature analog signal and the (i+1) th amplified error signal, and generate an i th error signal, i th being from first through (Kâˆ’1) th ; a K th summer configured to receive an input RF signal and the K th in-phase and quadrature analog signals, and generate a K th error signal; first through K th resonators, the i th resonator being configured to receive the i th error signal, and generate an i th amplified error signal, i th being from first through K th ; a first quantizer configured to receive the first amplified error signal based on the in-phase sampling clock, and generate an in-phase digital signal; a second quantizer configured to receive the first amplified error signal based on the quadrature sampling clock, and generate a quadrature digital signal; first through K th in-phase digital multipliers configured to multiply the in-phase digital signal with the in-phase sampling clock to generate first through K th up-converted in-phase signals; first through K th quadrature digital multipliers configured to multiply the quadrature digital signal with the quadrature sampling clock to generate first through K th up-converted quadrature signals; first through K th in-phase D/A converters configured to receive the first through K th up-converted in-phase signals, and generate first through K th in-phase analog signals; and first through K th quadrature D/A converters configured to receive the first through K th up-converted quadrature signals, and generate first through K th quadrature analog signals; wherein first through K th in-phase and quadrature D/A converters being single-bit converters; a sampling clock generator configured to generate an in-phase sampling clock, having an in-phase sampling clock frequency, and a quadrature sampling clock, having a quadrature sampling clock frequency; wherein the RF carrier frequency being between 0.5 GHz to 6 GHz, the input conversion bandwidth being more than 5 MHz and less than 100 MHz, the center frequency of the input conversion bandwidth being equal to the RF carrier frequency, both the in-phase sampling clock frequency and the quadrature sampling clock frequency being equal to the RF carrier frequency, the quadrature sampling clock being ninety degree out of phase with respect to the in-phase sampling clock, and both in-phase digital signal and the quadrature digital signal being bi-level digital signals.