Patent ID: 7673155

Claim:
A microprocessor, comprising: an interface configured to read execution codes and data of a program stored in an encrypted form at an external memory, in units of cache lines; a first cache memory having an offset table for storing an offset value which is a start address of the program, and configured to store the execution codes in units of cache lines; a second cache memory having an address range register for storing an address range of the data, and configured to store the data in units of cache lines; a key value table connected to the first cache memory and the second cache memory through a common bus, and configured to store an encryption key used in encrypting the program; and an encryption processing unit connected to the first cache memory, the second cache memory and the key value table through the common bus, and configured to receive the encryption key from the key value table and the offset value from the first cache memory and supply the execution codes to the first cache memory after decrypting the execution codes according to the encryption key and the offset value, and receive the encryption key from the key value table and the address range from the second cache memory and supply the data to the second cache memory after decrypting the data according to the encryption key and the address range.