Patent ID: 7315218

Claim:
A Phase Locked Loop (PLL) circuit comprising, a Voltage Controlled Oscillator (VCO) responsive to a digital control signal received on a first input node to set a frequency of the VCO to correspond to a mid-range voltage of an analog control signal received on a second input node; and a frequency calibration circuit responsive to a plurality of input signals received on a plurality of input nodes to drive an output node with the digital control signal to set the frequency of the VCO, the frequency calibration circuit comprising: a frequency detector to detect a frequency difference between a feedback signal and a reference signal and drive an output node with an output signal representative of the detected frequency difference; a counter responsive to the output signal of the frequency detector to generate and output the digital control signal; a controller configured to control a calibration process of the VCO; and a clock generator configured to generate a first clock to clock the controller and to generate a second clock to clock the frequency detector; wherein a change in the digital control signal represents a frequency shift to set the frequency of the VCO.