Patent ID: 6919931

Claim:
An array substrate, comprising: a substrate; a first gate shorting bar on the substrate, the first gate shorting bar having a plurality of first connecting contact holes; a second gate shorting bar spaced apart from and parallel to the first gate shorting bar, the second gate shorting bar having a plurality second connecting contact holes; a plurality of gate lines on the substrate and perpendicular to the first and second gate shorting bars, the gate lines comprising odd numbered gate lines and even numbered gate lines; a plurality of gate pads comprising odd numbered gate pads connected to the ends of odd numbered gate lines and even numbered gate pads connected to the ends of even numbered gate lines, wherein each gate pad of said plurality of gate pads has a corresponding gate pad contact hole; a plurality of first pad connectors, each connecting an odd numbered gate pad to the first gate shorting bar via the corresponding gate pad contact hole and via a corresponding first connecting contact hole; and a plurality of second pad connectors, each connecting an even numbered gate pad to the second gate shorting bar through the corresponding gate pad contact hole and via a corresponding second connecting contact hole.