Patent ID: 7964973

Claim:
A semiconductor chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a first dielectric layer over said silicon substrate; a first metal layer over said silicon substrate and over said first dielectric layer; a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer; a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer; a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point; and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer has a thickness between 1 and 10 micrometers, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer.