Patent ID: 7087519

Claim:
A method for forming a semiconductor device, comprising: forming an isolation layer that defines active regions on a semiconductor substrate having a cell region and a peripheral circuit region, forming a transistor on the active regions of the cell region and the peripheral circuit region; forming a first interlevel dielectric (ILD) layer overlying the transistor; forming a bit line and a bit line contact connected to a source or drain region of the transistor formed on the cell region through the first ILD layer; forming a second ILD layer overlying the bit line; forming a contact for a capacitor electrode connected to the source or drain region of the transistor formed on the cell region through the first and second ILD layers; forming a first contact hole to expose the active region of the peripheral circuit region or a gate electrode of the transistor through the first and second ILD layers; and filling the first contact hole with a porous layer having a high etch selectivity with respect to the first and second ILD layers.