Patent ID: 8339857

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array configured by NAND cell units each configured by a memory string including a plurality of memory cells connected in series, and select transistors connected to both ends of the memory string respectively; word lines each connected commonly to control gate electrodes of a plurality of memory cells included in a plurality of NAND cell units respectively; bit lines connected to first ends of the NAND cell units respectively; a source line connected to second ends of the NAND cell units; and a control circuit configured to write multi-value data in the memory cells by executing a write operation in the memory cells by applying voltages to the word lines and the bit lines such that threshold voltages of the memory cells are included in a threshold voltage distribution representing an erased state or in any of threshold voltage distributions representing different written states respectively, the control circuit being configured to: set either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the other as unselected bit lines; apply a write inhibiting voltage for inhibiting write into the memory cells to the unselected bit lines; apply a write voltage for changing the threshold voltage to the selected bit lines corresponding to unwritten memory cells to be given one of the threshold voltage distributions representing the different written states; and apply the write inhibiting voltage to the selected bit lines corresponding to unwritten memory cells to be given any other of the threshold voltage distributions representing the different written states, memory cells already written with certain data, and memory cells to be maintained in the threshold voltage distribution representing the erased state, thereby executing a write operation.