Patent ID: 7304892

Claim:
A non-volatile memory device, comprising: first and second memory cell blocks, each including a plurality of memory cells and including a local drain select line, a local source select line, and local word lines; a block selection unit to connect a given local word lines to global word lines, respectively, in response to a block selection signal; a first bias voltage generator configured to apply at least first and second erase voltages to the global word lines during an erase operation, the first erase voltage being applied to the global word lines during a first erase attempt of the erase operation, the second erase voltage being applied to the global word lines during a second erase attempt, where the second erase attempt is performed if the first erase attempt did not successfully perform the erase operation, the first and second erase voltages being positive voltages; and a bulk voltage generator to apply a bulk voltage to a bulk of the memory cells during the erase operation.