Patent ID: 6980943

Claim:
A computer-implemented method of driving the simulation testing of a design of an integrated circuit (IC) which is to be incorporated into an intended system comprising the steps of: providing an asynchronous sequence of states configured for simulating operating conditions relevant to driving sequencing of signal-exchange events with said IC; identifying first upper and first lower parameters of timing constraints imposed by said intended system with respect to enabling individual said events; forming a first synchronous sequence of states in which said states are synchronized on a basis of remaining within said first upper and first lower parameters of timing constraints; identifying second upper and second lower parameters of timing constraints imposed by said IC with respect to enabling individual said events; forming a second synchronous sequence of states in which said states are synchronized on a basis of remaining within said second upper and said second lower parameters of timing constraints; and using said second synchronous sequence as a basis for said simulation testing of said design.