Patent ID: 7945804

Claim:
A method for digitally controlled multi-frequency clocking, comprising: receiving a system reference oscillator clock frequency at a microprocessor including multiple cores, wherein the system reference oscillator clock frequency provides a reference frequency to a local oscillator, the local oscillator supplying a core clock frequency to at least one of the cores; adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the at least one of the cores; interconnecting multiple microprocessors via a communication fabric; and distributing the system reference oscillator clock frequency and the digital frequency characteristic data to the microprocessors, wherein the multiple microprocessors are grouped to form a multi-chip module (MCM), multiple MCMs are interconnected in a node supporting intra-MCM communication, and the node is one of a master processor node and a non-master processor node, the master processor node including a master reference oscillator to generate the system reference oscillator clock frequency; and a master nonvolatile memo device to hold the digital frequency characteristic data for the MCMs; and the non-master processor node including: a reference oscillator distributor to distribute the system reference oscillator clock frequency; and a data distributor to distribute the digital frequency characteristic data to the MCMs.