Patent ID: 8677166

Claim:
A semiconductor device, comprising: a power gating unit including an output electrode, the power gating unit configured to output an internal signal at the output electrode based on an input signal and an operation mode, the operation mode being based on a power control signal; a combinational logic unit including an input electrode directly connected to the output electrode of the power gating unit through a data line, the combinational logic unit configured to generate an output signal based on the internal signal received through the data line; and a clamping unit including first and second clamp switches configured to receive first and second control signals, respectively, the first and second clamp switches connected in series and configured to at least clamp the internal signal at a logic high level or at a logic low level based on the operation mode, the first control signal and the second control signal being different, one of the first control signal and the second control signal being the power control signal.