Patent ID: 7544989

Claim:
A method for programming a flash memory cell in a non-planar flash memory array comprising rows and columns of flash memory cells, each row of memory cells coupled on one of a first or a second plane, formed by pillars and trenches respectively, and each column of memory cells coupled on both the first and the second plane, each memory cell having a pair of source/drain regions, a gate insulator, a floating gate, and a control gate, the method comprising: biasing the control gate, formed only on top of a pillar or in a bottom of a trench, with a first positive voltage; biasing a first source/drain region located only in a first sidewall of the pillar with a second positive voltage; and grounding the remaining source/drain region located either only on a second sidewall of the pillar to create a hot electron injection only from a channel formed in the top of the pillar into a gate insulator of the floating gate located only over the top of the pillar or only on a second sidewall of the trench, opposite the first sidewall, to create hot electron injection only from a channel formed only in the bottom of the trench into a gate insulator of the floating gate located only over the bottom of the trench.