Patent ID: 7016041

Claim:
A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit, the method comprising: forming a first primary alignment structure in a first position of an inter-layer region of the first mask layer, forming a first secondary alignment structure in a second position of the inter-layer region of the first mask layer, forming a second primary alignment structure in a first position of an inter-layer region of the second mask layer, forming a second secondary alignment structure in a second position of the inter-layer region of the second mask layer, exposing the first mask layer and the second mask layer onto a photoresist coated substrate with a first exposure, exposing the first mask layer and the second mask layer onto the photoresist coated substrate with a second exposure, where the first position of the first primary alignment structure during the first exposure generally aligns with the second position of the second secondary alignment structure, and the second position of the first secondary alignment structure during the second exposure generally aligns with the first position of the second primary alignment structure, developing the photoresist on the substrate, and measuring offsets between the first primary alignment structure and the second secondary alignment structure and between the second primary alignment structure and the first secondary alignment structure to determine the overlay errors.