Patent ID: 7067881

Claim:
A semiconductor device comprising: an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order; element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films; a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films; a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer, wherein the part of said main surface of said semiconductor layer on which said gate structure resides forms an angle larger than 90° with a corresponding side surface of each said recess.