Patent ID: 8645878

Claim:
A method of fabricating an integrated circuit, the integrated circuit including a bit cell having a plurality of physical transistors, wherein the bit cell is an implementation of a first bit cell design initially designed for a first semiconductor process, wherein the first bit cell design is migrated to a second semiconductor process, the method comprising: a) determining the sizes of transistor representations in said first bit cell design, each of the transistors having a threshold voltage; b) determining goals for at least one of read static noise margin, write margin, read current, and cell leakage of the first bit cell design; c) selecting weights for each of the at least one of goals, the weights being associated with an objective function for optimization; d) determining a gradient of the at least one of goals as a function of a device target for each transistor; e) determining whether all of the goals have been achieved for the device target for each transistor; f) applying a gradient step to reduce the objective function if the at least one of goals at step (e) were not achieved and repeating steps (b) through (e); g) providing the device targets to the transistors for the second semiconductor manufacturing process if the at least one of goals at step (e) were achieved; and h) fabricating the integrated circuit based upon process parameters in the second semiconductor process, the process parameters being determined by the device targets.