Patent ID: 8063404

Claim:
A semiconductor memory device comprising: a substrate including a supporting insulating region and a semiconductor region disposed on the supporting insulating region; a first isolating element and a second isolating element substantially parallel to the first isolating element embedded in the semiconductor region, respectively; a carrier region disposed in the semiconductor region and between the first isolating element and the second isolating element; two source/drain regions positioned in the carrier region with an first isolating layer disposed between the two source/drain regions; a floating body region positioned in the carrier region underneath the two source/drain regions; an abrupt doping region positioned in the floating body region; a first gate dielectric layer positioned on a first side of the carrier region; a first gate positioned on the first gate dielectric layer; a first conductive line positioned below the first isolating element, and coupling to the abrupt doping region; and a second isolating layer extending from the first isolating element and the second isolating element to the supporting insulating region for isolating the floating body region.