Patent ID: 7831856

Claim:
A computer-implemented method of detecting timing errors in a configuration of a programmable logic device (PLD), the method comprising: performing a timing analysis on the PLD configuration, wherein the PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block, wherein the first and second clock signals originate from a reference clock signal; calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer, wherein the first delay and the second delay are measured relative to the reference clock signal and are provided by the timing analysis; and determining whether the PLD configuration satisfies the time constraint based on the slack value.