Patent ID: 7206230

Claim:
A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising: performing a first operation on a first group of memory cells using a first data set stored in a first plurality of the sets of data latches; and during said first operation, caching a second data set for a second operation in said first plurality of the sets of data latches, wherein the first operation includes multiple phases and wherein caching said second data includes reading the second data from a second group of memory cells distinct from the first group of memory cells, the second data set being read between phases of the first operation, wherein the first operation is a write operation having alternating program and verify phases and the first set of data is the data to be written into the first group of memory cells, wherein said memory cells are multi-level memory cells storing N bits of data, where N is greater than one, and wherein each of said sets of data latches includes N data latches and said first data set is N bit data, and wherein as bits of the N bits of data verify, data latches of said set of data latches are released and said cached data is stored in the released data latches.