Patent ID: 8751888

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of blocks, each block comprising a set of NAND cell units, each NAND cell unit comprising a memory string and a first select gate transistor and a second select gate transistor connected to the ends of the memory string, the memory string comprising a plurality of non-volatile memory cells connected in series; a word line commonly connecting control gates of the memory cells arranged in a direction intersecting the memory string; a bit line connected to a first end of the NAND cell unit; a source line connected to a second end of the NAND cell unit; a sense amplifier circuit configured to sense a potential of the bit line and determining data held in the memory cell; a control circuit configured to perform a write operation to 1-page memory cells along a selected word line, by applying a write pulse voltage to the selected word line, and then performing a verify read operation of confirming whether the data write to the 1-page memory cells is completed, and when the data write is not completed, performing a step-up operation of raising the write pulse voltage by a step-up voltage; and a bit scan circuit configured to determine whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation, the control circuit being configured to change an amount of the step-up voltage, according to the determination of the bit scan circuit.