Patent ID: 7598816

Claim:
A phase-locked loop circuit, comprising: a phase-frequency detector for comparing the input signal with a feedback signal; a charge pump controlled by first and second control outputs from said phase-frequency detector, a switched-capacitor resistance based loop filter connected to the output of said charge pump; a voltage controlled oscillator connected to the output of said switched-capacitor resistance based loop filter with its output providing said feedback signal; and a sampling clock for driving said switched-capacitor resistance; wherein: delay elements for said first and second control outputs are introduced between said phase-frequency detector and said charge pump; said sampling clock includes a set of non-overlapping clocks generated by a non-overlapping clock generator; and said non-overlapping clock generator is connected to receive from a digital logic circuit an output signal whose rising edges correspond to an earlier occurring rising edge of either of said first and second control outputs from said phase-frequency detector.