Patent ID: 7671881

Claim:
A timing detection circuit for detecting a timing of a valid edge of a synchronizing signal with respect to a reference clock having a reference frequency, the timing detection circuit comprising: a multiphase clock generation circuit that generates n (n is an integer equal to or larger than two) multiphase clocks having respective clock edges and further having a frequency of k (k is an integer equal to or larger than two) times the reference frequency and mutually difference phases; a first detection circuit that detects, among the multiphase clocks, a closest clock having the clock edge closest to the valid edge of the synchronizing signal and generates a first detect signal indicating the closest clock; and a second detection circuit that detects, among k successive cycles of a representative clock selected from the multiphase clocks, a valid cycle within which the valid edge of the synchronizing signal is located and generates a second detect signal indicating the valid cycle; wherein the second timing detection circuit includes a counter that counts cycles of the representative clock to generate count values and a selecting circuit that selects one of the count values during a first period having a first timing relationship with the valid cycle to generate the second detect signal.