Patent ID: 8263443

Claim:
A method of manufacturing a semiconductor device comprising a first conductivity type MOS transistor formed on a silicon active layer of an SOI substrate, the method comprising: forming a LOCOS isolation region having a thickness sufficient to contact a buried insulating film and define a MOS transistor region in the silicon active layer; forming a gate insulating film having a thickness of about 5 to 30 nm in the MOS transistor region by thermal oxidation; forming a polysilicon layer having a thickness of 200 to 400 nm on the gate insulating film; a first impurity doping step comprising doping an impurity in a portion of the polysilicon layer above a channel region of the silicon active layer to form: a first conductivity-type polysilicon region above the channel region of the silicon active layer, where the silicon active layer has a constant thickness; and second conductivity-type polysilicon regions above edges of the LOCOS isolation region, where the second conductivity-type is opposite to the first conductivity-type, and where a thickness of the silicon active layer decreases compared to the constant thickness; etching the polysilicon layer to form a gate electrode; a second impurity doping step comprising partially and selectively doping a first conductivity-type impurity in the silicon active layer in the MOS transistor region to define a source region and a drain region; forming an intermediate insulating layer on the SOI substrate; forming a contact hole in the intermediate insulating layer; forming a metal wiring in the contact hole; and forming a protective film.