Patent ID: 7069482

Claim:
A fuse-controlled error-correction control system for a ROM, comprising: a defective memory-cell address detector circuit (CMP) that compares input address signals for the ROM to a fuse-controlled preset static address of a predetermined defective memory cell of the ROM and that provides an address-hit output signal (ADDHIT), which indicates the occurrence of input address signals corresponding to said fuse-controlled preset static address of said predetermined defective memory cell; an (AOUT) circuit that receives the address-hit output signal ADDHIT signal and that provides a corresponding bit-reversal output signal (REV); and a data output buffer that receives data bits from memory cells of the ROM, including a bit from said predetermined defective memory cell, and that has an output terminal coupled to a data output terminal of the ROM, said data output buffer having an output-reversal control terminal for receiving the bit-reversal output signal REV, which reverses the sense of the data signal corresponding to the predetermined defective memory cell at the output terminal of the data output buffer when the address of the defective memory cell is detected by the defective memory-cell address detector circuit CMP.