Patent ID: 7564105

Claim:
A quasi-planar FinFET device comprising: a semiconductor substrate having a top wall and at least one first recessed region wherein said at least one first recessed region comprises a trench having a sidewall and a bottom wall; an insulating layer partially filling said recessed region; and a first doped region at said sidewall of said at least one first recessed region above said insulating layer adjacent said top wall, said first doped region comprising a conduction channel of said quasi-planar FinFET device, said top wall comprising a source or drain region of said FinFET device, said top wall comprises an additional recessed region juxtaposed to a top edge of said at least one recessed region sidewall, wherein said additional recessed region comprises a trench having a depth less than said at least one first recessed region and a bottom wall of said additional recessed region comprises said source or drain region.