Patent ID: 7823036

Claim:
An integrated circuit comprising: A. functional circuitry that includes functional registers; B. a number N greater than two of separate, serial scan paths formed of the functional registers being arranged in serially connected scan cells, each scan path having a serial scan input, a serial scan output, and a control input, each scan path being capable of capturing response data from the functional circuitry, shifting data along the scan path, and applying stimulus data to the functional circuitry; and C. state machine circuitry having N number of separate control output leads, each control output lead being connected to the control input of one of the scan paths, the state machine circuitry providing: i. an Idle state, ii. a Capture state, and iii. N Shift states, each Shift state being associated with one control output lead, iv. in the Idle state, the state machine circuitry remaining in the Idle state or transitioning to the Capture state, v. in the Capture state, the state machine circuitry transitioning to the Idle state or to a first Shift state, vi. in the Shift states from a first Shift state through an N- 1 Shift state, the state machine circuitry transitioning to the next Shift state, and vii. in the N Shift state, the state machine circuitry transitioning to the first Shift state or the Capture state.