Patent ID: 6865126

Claim:
A semiconductor memory device comprising: a plurality of memory cells each of which is connected between a bit line and a word line and which store cell data; a plurality of sense amplifiers which are connected to the plurality of memory cells, respectively and which read cell data from the memory cells and write cell data to the memory cells, respectively; a plurality of sense amplifier write circuits which are connected to the plurality of sense amplifiers, respectively and which write cell data to the sense amplifiers, respectively; a plurality of data lines which are connected to the plurality of sense amplifier write circuits, respectively and to which the cell data to be written to the sense amplifiers is written; a data line shift circuit which shifts one of the data lines and replaces the shifted one with a data line adjacent thereto; a plurality of internal data lines which connect the plurality of sense amplifiers and the plurality of sense amplifier write circuits; a plurality of select transistors to activate the plurality of internal data lines; a plurality of gate circuits which control the plurality of select transistors, respectively; a plurality of data mask lines each connected to one input terminal of a corresponding one of the plurality of gate circuits; and a plurality of mask circuits which are provided for a given number of data mask lines of the plurality of data mask lines and which supply a mask signal, which invalidates write of the cell data to a sense amplifier, to the gate circuits connected to the given number of data mask lines, wherein a word line of a memory cell to be accessed is activated after cell data is written to a given sense amplifier in write mode.