Patent ID: 7012289

Claim:
A memory cell, comprising: a substrate having a trench formed therein and having a given cross section; a selection transistor having a terminal region; a trench capacitor formed in said trench and having a trench filling with an upper region and a lower region; a first insulating layer disposed above said trench filling and having a contact trench formed therein, said contact trench having a cross section being smaller than said given cross section of said trench, said first insulating layer having a first thickness being less than 15 nm; a conductive filling disposed in said contact trench and surrounded by said first insulating layer, said conductive filling conductively connecting said terminal region of said selection transistor to said trench capacitor; a second insulation layer surrounding said trench filling in said upper region and adjoining said first insulation layer, said second insulating layer having a second thickness being greater than 15 nm which is greater than said first thickness, said first thickness formed for preventing a lateral current flow but a formation of a parasitic field-effect transistor being possible during operation of the memory cell; a doping region formed in said substrate in a region of said second insulation layer, said trench filling having a doping of a first conductivity type, said doping region having a doping of a second conductivity type, being opposite said first conductivity type, said second insulation layer extending over an entire width of said doping region; a third insulating layer disposed around said lower region of said trench filling; a further doping region formed in a manner adjoining said third insulating layer, said further doping region having a doping of said first conductivity type; said first thickness of said first insulating layer set for preventing the lateral current flow; during operation, a first parasitic field effect transistor formed from said terminal region of said selection transistor, said conductive filling, said first insulating layer, said substrate and said doping region being turned on; and a second parasitic field effect transistor formed from said doping region, said trench filling, said second insulating layer and said further doping region not being turned on during the operation of the memory cell.