Patent ID: 8762922

Claim:
An electronic design automation (EDA) tool for reducing leakage power of an electronic circuit design, wherein the circuit design includes a plurality of cells interconnected to form a plurality of timing paths, the EDA tool comprising: a memory that stores the circuit design; and a processor in communication with the memory, wherein the processor: selects a first timing path of the plurality of timing paths of the circuit design; determines availability of timing slack for replacing a first cell in the first timing path; selects a first replacement cell from a technology library when the timing slack is not available, wherein a type of the first replacement cell is the same as a type of the first cell and a width and threshold voltage of the first replacement cell are greater than the width and threshold voltage of the first cell; compares an overall power consumption of the first cell and the first replacement cell; determines availability of timing slack for replacing the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than the overall power consumption of the first cell; and replaces the first cell in the circuit design with the first replacement cell based on said determination.