Patent ID: 7933158

Claim:
A nonvolatile memory control unit used with a host processor and controlling a nonvolatile memory, comprising: a power voltage level detection portion; a reset signal detection portion; and a data read portion, wherein the power voltage level detection portion receives an operation voltage supplied from outside of the nonvolatile memory control unit, and outputs a first signal to the data read portion in accordance with detection that the operation voltage exceeds a predetermined voltage level, wherein the reset signal detection portion receives a first control signal supplied from outside of the nonvolatile memory control unit, and outputs a second signal to the data read portion in accordance with detection that the first control signal is enabled, and wherein in response to a read command with address information received from the host processor, the data read portion performs a read operation for reading data from an area of the nonvolatile memory corresponding to the address information, and wherein in response to receiving the second signal from the reset signal detection portion, the data read portion performs the read operation for reading data from a first area of the nonvolatile memory, which is used for storing a program executed by the host processor, and waits to output the data read from the first area until the host processor requests to read.