Patent ID: 8908452

Claim:
A semiconductor memory apparatus comprising: a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal according to an input of a count pulse after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal by the determined delay amount, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes in response to the tuning mode signal, the delay control signal, the data output control signal and the timing control signal; and a data alignment unit configured to convert parallel data into serial data, output the serial data, and change a data sequence of the serial data in response to the timing control signal.