Patent ID: 8519935

Claim:
A display device comprising: a display panel having: N main gate lines and N sub gate lines, wherein each main gate line is not directly coupled to any sub gate line; and a plurality of pixels each controlled by a corresponding main gate line among the N main gate lines and a corresponding sub gate line among the N sub gate lines; a first dummy shift register set; a second dummy shift register set; a third dummy shift register sets; a fourth dummy shift register set, wherein each dummy shift register sets includes m dummy shift registers; a first bi-directional shift register set coupled between the first dummy shift register set and the second dummy shift register set and including L bi-directional shift registers configured to drive the M main gate lines, wherein a first bi-directional shift register in the first bi-directional shift register set is coupled to the first dummy shift register set, an L th bi-directional shift register in the first bi-directional shift register set is coupled to the second dummy shift register set, an output end of a k th bi-directional shift register in the first bi-directional shift register set is directly coupled to a (k+m) th main gate line which is coupled to an input end of a (k+1) th bi-directional shift register in the first bi-directional shift register set; a second bi-directional shift register set coupled between the third dummy shift register set and the fourth dummy shift register set and including L bi-directional shift registers configured to drive the M sub gate lines, wherein a first bi-directional shift register in the second bi-directional shift register set is coupled to the third dummy shift register set, an L th bi-directional shift register in the second bi-directional shift register set is coupled to the fourth dummy shift register set, an output end of a k th bi-directional shift register in the second bi-directional shift register set is directly coupled to a (k+m) th sub gate line which is coupled to an input end of a (k+1) th bi-directional shift register in the second bi-directional shift register set; and a first directional start pulse signal generator coupled to the first bi-directional shift register in the first bi-directional shift register set and configured to enable a (1+m)th main gate line by outputting a first start pulse signal, and coupled to the (1+m−c)th dummy shift register in the third dummy shift register set and configured to enable (1+m−c)th sub gate line by outputting the first start pulse signal.