Patent ID: 8035154

Claim:
A semiconductor device comprising: a semiconductor substrate; a plurality of memory cells located in the semiconductor substrate, each of the plurality of memory cells including a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate, and a wiring layer disposed on an opposing side of the erasing electrode from the tunnel oxide layer, wherein the floating gate is configured so that a data is written into and read from the floating gate and the erasing electrode is configured to erase the data written in the floating gate; and a plurality of bit lines and a plurality of source lines, wherein each of the plurality of bit lines and each of the plurality of source lines are alternately arranged on the plurality of memory cells in parallel with each other.