Patent ID: 8244960

Claim:
A nonvolatile memory, comprising: an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together; said array being partitioned into a first group of blocks and a second group of blocks; a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel; said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data; said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; said second group of blocks having a capacity dynamically increased by allocation of blocks from said first group to said second group in response to a demand to increase the capacity; a time stamp stored with each block, said time stamp having a value that is toggled when the block was programmed; a free block list updated at predefined time intervals for listing blocks free for allocation and the time stamps of the blocks listed, such that a comparison between the time stamps of the block stored in the block and the free block list will indicate whether the block has old data or just been written with new data.