Patent ID: 7804701

Claim:
A method comprising: providing an array of memory cells arranged in a plurality of columns and rows, each of the memory cells comprising a programmable fuse connected to a predetermined bit line and in series with a select transistor, the select transistor comprising a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line and a second current electrode connected to the programmable fuse, the select transistor further comprising a semiconductor body in which the first current electrode and the second current electrode are located and separated by a channel; selecting a memory cell to identify a selected memory cell from the array of memory cells for programming; and in response to the selecting, providing a current to the semiconductor body of the select transistor of the selected memory cell to forward bias the channel to the first current electrode during programming of the programmable fuse of the selected memory cell to increase a programming current through select transistor and programmable fuse of the selected memory cell to result in programming of the selected memory cell.