Patent ID: 8610616

Claim:
An analog to digital converter, comprising: a capacitor array including: a first capacitor; a second capacitor; a third capacitor; a fourth capacitor; a first switch, wherein the first switch is coupled between a first reference node and a first terminal of the first capacitor; a second switch, wherein the second switch is coupled between a second terminal of the first capacitor and a second reference node; a third switch, wherein the third switch is coupled between the first terminal of the first capacitor and a first terminal of the second capacitor; a fourth switch, wherein the fourth switch is coupled between the second terminal of the first capacitor and the first terminal of the second capacitor; a fifth switch, wherein the fifth switch is coupled between a second terminal of the second capacitor and the second reference node; a sixth switch, wherein the sixth switch is coupled between the first terminal of the second capacitor and a first terminal of the third capacitor; a seventh switch, wherein the seventh switch is coupled between the first terminal of the third capacitor and the second terminal of the second capacitor, wherein a second terminal of the third capacitor is coupled to the second reference node; an eighth switch, wherein the eighth switch is coupled between the first terminal of the third capacitor and a first terminal of the fourth capacitor, wherein a second terminal of the fourth capacitor is coupled to the second reference node; a ninth switch, wherein the ninth switch is coupled between an output terminal of the capacitor array and a third reference node; a tenth switch, wherein the tenth switch is coupled between the output terminal of the capacitor array and the first terminal of the first capacitor; an eleventh switch, wherein the eleventh switch is coupled between the output terminal of the capacitor array and the first terminal of the second capacitor; and a twelfth switch, wherein the twelfth switch is coupled between the output terminal of the capacitor array and the first terminal of the third capacitor; a comparator, wherein a first input terminal of the comparator is coupled to an analog signal input node, a second input terminal of the comparator is coupled to the output terminal of the capacitor array, and the comparator is configured to compare signals received from the analog input node to signals received from the output terminal of the capacitor array; and a control block, wherein a feedback input terminal of the control block is coupled to an output terminal of the comparator, and the control block is configured to selectively open or close the switches, receive a comparison result from the comparator, and generate a digital output based on the comparison result.