Patent ID: 8650019

Claim:
A method of creating a timed hybrid simulation model for a module of a circuit design specification, comprising: inputting an untimed, high-level language (HLL) data-path model of the module; inputting an HLL data-path interface specification that specifies input ports of the HLL data-path model; generating, by a programmed processor, a hardware description language (HDL) control-path model of the module that specifies port attributes and associated stitching directives, wherein each stitching directive specifies a control port and an associated one of the input ports of the HLL data-path model; wherein during simulation, behavior of the data-path model is bit-accurate, timing of the data-path model is not cycle-accurate, timing of the control-path model is cycle accurate, and simulation speed of the data-path model is faster than a cycle-accurate simulation of the module; linking the HLL data-path and HDL control-path models to create the timed hybrid simulation model including an HDL wrapper; wherein the HDL wrapper during simulation sends and receives bit-accurate data values to and from the data-path model according to timing constraints provided by the control-path model and delays simulation output from the data path model according to simulated timing behavior of the control-path model; and storing the timed hybrid simulation model in a processor-readable storage medium.