Patent ID: 7915079

Claim:
A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip; at least one of the plurality of layer portions further includes a plurality of electrodes that are electrically connected to the semiconductor chip and that each have an end face located in the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is electrically connected to the end faces of the plurality of electrodes, the method comprising the steps of: forming a plurality of structures each of which includes at least one main-body-forming portion, the main-body-forming portion being intended to be the main body and having a pre-wiring surface on which the wiring is to be formed later; surrounding the plurality of structures with a jig and thereby aligning the structures so that the respective pre-wiring surfaces face upward, the jig having a top surface that is lower in level than the pre-wiring surfaces; forming a resin layer using a resin film, the resin layer covering the jig and the plurality of structures; polishing the resin layer until the pre-wiring surfaces are exposed and thereby flattening the pre-wiring surfaces and a top surface of a portion of the resin layer that remains on the top surface of the jig; forming the wiring on the pre-wiring surfaces of a plurality of main-body-forming portions included in the plurality of structures simultaneously, the step of forming the wiring being performed after the step of flattening; and separating the plurality of main-body-forming portions with the wiring formed on the respective pre-wiring surfaces from each other so as to form the plurality of layered chip packages.