Patent ID: 8809963

Claim:
An integrated circuit comprising: a matrix of memory cells, a first memory cell of the matrix of memory cells including a first pull-up transistor comprising a first source region and a first drain region within a first fin, and having a first gate electrode extending over the first fin; a first pull-down transistor comprising a second source region within both a second fin and a third fin and a second drain region within both the second fin and the third fin, and having the first gate electrode extending over the second fin and the third fin; a first pass gate transistor comprising a third source region and a third drain region within the second fin, and having a second gate electrode extending over the second fin and the third fin; a second pull-up transistor comprising a fourth source region and a fourth drain region within a fourth fin, and having a third gate electrode extending over the fourth fin; a second pull-down transistor comprising a fifth source region within both a fifth fin and a sixth fin and a fifth drain region within both the fifth fin and the sixth fin, and having the third gate electrode extending over the fifth fin and the sixth fin; a second pass gate transistor comprising a sixth source region and a sixth drain region within the fifth fin, and having fourth gate electrode extending over the fifth fin and the sixth fin; a seventh fin interjacent the second fin and the third fin; the second source region and the second drain region, respectively, extending within the seventh fin; and the third source region and the third drain region, respectively, extending within the seventh fin.