Patent ID: 7405149

Claim:
A method for fabricating an integrated circuit chip, comprising: providing a silicon wafer, a transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, wherein said contact pad has a top surface and a sidewall, wherein said top surface has a first region and a second region between said first region and said sidewall, and a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a nitride; forming a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said first region and exposes said first region, and wherein said first polymer layer has a thickness between 2 and 50 micrometers; forming a third metal layer on said first polymer layer and on said contact pad, wherein said forming said third metal layer comprises sputtering a titanium-containing layer with a thickness between 0.01 and 3 micrometers on said first polymer layer and on said first region, sputtering a seed layer with a thickness between 0.05 and 3 micrometers on said titanium-containing layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said third opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said titanium-containing layer not under said gold layer; and forming a second polymer layer on said third metal layer, on said first polymer layer, and over said silicon wafer, wherein a fourth opening in said second polymer layer is over said third metal layer and exposes said third metal layer.