Patent ID: 8572532

Claim:
A method of analyzing design and timing of an integrated circuit design, the method comprising: receiving a first netlist of a first partition block for a top level of a hierarchical design of an integrated circuit, the first partition block including at least one original clock signal with a pair of clock paths having an external common point outside a boundary of the first partition block; analyzing the pair of clock paths having the external common point to determine a first clock port and a second clock port associated with a first original clock signal at the boundary of the first partition block; for each of the first clock port and the second clock port, creating a launch clock and a capture clock, making exclusive clock groups for each of the launch clock for one clock port and the capture clock for the other clock port to avoid the launch clock and the capture clock for each port affecting any other internal data path within the first partition block, and associating common path pessimism removal (CPPR) information for the first partition block with a source latency of the capture clock so that timing is adjusted for common path pessimism at an end point of an internal data path; and wherein one or more of the receiving, the analyzing, the creating, the making, and the associating are performed with a processor.