Patent ID: 7919407

Claim:
A method for integrating a magnetic memory level with a CMOS level in an MRAM device comprising: providing the CMOS level; forming a first etch-stop/capping layer on said CMOS level; forming a first dielectric layer on said etch-stop/capping layer; forming a second etch-stop layer on said first dielectric layer; forming a second dielectric layer on said second etch-stop layer; then, in a first pattern and etch process: etching two laterally separated, parallel lines of N uniformly spaced word line connection pad vias wherein each said line of vias is disposed along a lateral edge of said CMOS level and, etching between said parallel lines an N×M two dimensional array of memory device connection vias, said etch penetrating said first and second dielectric layers and said second etch-stop layer, but stopping at and exposing said first etch stop layer; then, in a second pattern and etch process: etching, through said second dielectric layer and said second etch-stop layer but stopping at said first dielectric layer, M uniformly spaced parallel word line trenches and N uniformly spaced word line connection pad trenches, wherein said word line trenches are parallel to and between said two laterally separated lines of N word line connection pad vias, and wherein each of said N word line connection pad trenches is disposed above one of N uniformly spaced word line connection pad vias; wherein said second etch process also removes those portions of said first etch-stop layer exposed in said first pattern and etch process; then, in a first dual-damascene process, filling all trenches and vias with conducting metal; then forming a word line capping layer over said fabrication; and opening the tops of said N×M array of memory device connection vias through said word line capping layer; then forming and patterning a bottom electrode layer over said capping layer, whereby N×M individual bottom electrodes are formed and whereby each said individual bottom electrode electrically contacts one of said memory device connection vias; then forming and planarizing a third blanket dielectric layer on said bottom electrodes; and forming and patterning a memory device on each said bottom electrode layer; then depositing and planarizing a fourth blanket dielectric layer over said memory devices; then, in a dual damascene process forming a conducting via from an upper surface of each said word line connection pads through said word line capping layer and said fourth blanket dielectric layer and forming N parallel bit lines contacting said conducting via and said memory devices, wherein a single memory device is positioned at each intersection of a bit line and a word line.