Patent ID: 8185772

Claim:
An apparatus, comprising: a time determination circuit configured to determine, for each of a plurality of commands executed by a processor, a value indicative of an execution time of the command; a comparator coupled with the time determination circuit and configured to compare, for each of the commands, the value determined for the command with a threshold value; a storage circuit coupled with the comparator and configured to select a first subset of the plurality of commands depending upon an outcome of the comparison of the values and the threshold value, and to store data representing the first subset of the commands but not a second subset of the commands; and a frequency detector configured to detect a frequency of a clock of the processor or a cycle time of the clock of the processor, wherein the apparatus is configured to select the threshold value from a plurality of threshold values based on the clock frequency or the clock cycle time, the plurality of threshold values being associated with a plurality of frequencies or a plurality of cycle times.