Patent ID: 7557659

Claim:
An input stage, comprising: a complimentary differential input transconductor including a pair of differential inputs that accept a pair of voltage signals; a first pair of complimentary differential outputs that output current signals I 1 and I 2 ; and a second pair of complimentary differential outputs that output current signals I 3 and I 4 ; a first npn-pnp current mirror having an input and a pair of outputs, the input accepting the current signal I 1 , and the pair of outputs outputting current signals I 1 ′ and I 1 ″ that are proportional to the current signal I 1 ; a second npn-pnp current mirror having an input and a pair of outputs, the input accepting the current signal I 2 , and the pair of outputs outputting current signals I 2 ′ and I 2 ″ that are proportional to the current signal I 2 ; a first pnp-npn current mirror having an input and a pair of outputs, the input accepting the current signal I 3 , and the pair of outputs outputting current signals I 3 ′ and I 3 ″ that are proportional to the current signal I 3 ; and a second pnp-npn current mirror having an input and a pair of outputs, the input accepting the current signal I 4 , and the outputs outputting current signals I 4 ′ and I 4 ″ that are proportional to the current signal I 4 ; wherein the current signals I 1 ′ and I 3 ′ are added to produce a first output current (Iout) of the input stage; and wherein the current signals I 2 ′ and I 4 ′ are added to produce a second output current (Iout_bar) of the input stage.