Patent ID: 8687804

Claim:
A device comprising: one or more processors; memory coupled to the one or more processors, the memory comprising: a protocol unit that includes a first protocol module and a second protocol module; the first protocol module to communicate over at least one control channel in accordance with a message-oriented communication protocol, the second protocol module to communicate over one or more data channels in accordance with a stream-oriented communication protocol, the at least one control channel operating independently and in parallel to the one or more data channels, the one or more data channels utilized to transmit data; and a security unit comprising: a security negotiator to negotiate security requirements for a first data portion of a single data transfer request via the at least one control channel with the message-oriented communication protocol and to negotiate security requirements for a second data portion of the single data transfer request while the first data portion is transferred over the one or more data channels in accordance with the stream-oriented communication protocol; and a security implementer to bind the security requirements for the first data portion of the single data transfer request to the second protocol and to bind the security requirements for the second data portion of the single data transfer request to a different protocol that is associated with a different data channel than the stream-oriented communication protocol.