Patent ID: 7696518

Claim:
A flat panel display, comprising: a thin film transistor comprising source and drain electrodes, arranged on an insulation substrate; a gate insulation film arranged on the insulation substrate and on the thin film transistor, the gate insulation film being perforated by first and second contact holes exposing the source and drain electrodes respectively; a gate electrode, a lower electrode of a capacitor and gate lines being arranged on the gate insulation film; an interlayer insulation film arranged on the gate electrode, the lower electrode of the capacitor and the gate lines; an upper electrode of the capacitor and data lines being arranged on the interlayer insulation film; a passivation film arranged on the upper electrode of the capacitor and on the data lines a pixel electrode arranged on the passivation film and electrically connected to one of the source and drain electrodes through one of the first and second contact holes; and a power supply layer also arranged on the passivation film and electrically connected to the other one of the source and drain electrodes through the other one of the first and second contact holes.