Patent ID: 8464031

Claim:
A method for generating a result vector, comprising: in a processor, performing operations for: receiving an input vector, a control vector, and optionally receiving a predicate vector, wherein each vector includes a same number of elements; recording a base value from an element at a key element position in the input vector; and generating the result vector, wherein generating the result vector comprises, if the predicate vector is received, for each element in the result vector to the right of the key element position for which a corresponding element of the predicate vector is active, otherwise, for each element in the result vector to the right of the key element position, determining a number of relevant elements from the key element position to and including a predetermined element in the result vector, wherein a relevant element in the result vector is an element in the result vector for which the corresponding element in the control vector is active; and setting the element in the result vector equal to a result of performing a unary operation on the base value a number of times equal to the number of relevant elements.