Patent ID: 7681020

Claim:
A method for context switching between a first thread and a second thread, comprising: detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread; and in response to detecting the exception, invoking an exception handler, wherein the exception handler is configured to: execute one or more instructions removing access to at least a portion of a processor cache of a processor, wherein the portion of the processor cache contains cached information for the first thread using a first address translation, thereby preventing the second thread using a second address translation from accessing the cached information in the processor cache; and branch to at least one of the first thread and the second thread; wherein both the first thread and the second thread access the processor cache with software maintained coherency such that the processor is not configured to automatically remove access to the portion of the processor cache without executing the one or more instructions; and wherein the first address translation includes a memory coherency bit which indicates that the cached information does not use hardware maintained coherency.