Patent ID: 7384863

Claim:
A method for manufacturing a semiconductor device, in which a first semiconductor chip or substrate and a second semiconductor chip are joined to each other face-to-face via gold bumps provided on electrode terminals or wiring of the first semiconductor chip or substrate and gold bumps provided on the second semiconductor chip, each of the bumps provided on electrode terminals or wiring of the first semiconductor chip or substrate and the bumps provided on the second semiconductor chip having a substantially flat end, said method comprising the steps of: providing a tin layer on a whole surface, including a surface of the flat end and a side face of each of the gold bumps, of at least one of the first semiconductor chip or substrate and second semiconductor chip, the tin layer having a thickness of about 0.1 to about 4 μm and each of the gold bumps having a thickness of about 10 μm to about 30 μm; superposing the first semiconductor chip or substrate and the second semiconductor chip without perfect alignment between the bumps thereof, the end of the first bump facing the end of the second bump; heating the first semiconductor chip or substrate and the second semiconductor chip to a temperature at which the tin layer melts, to thereby self-align the first semiconductor chip or substrate and the second semiconductor chip and join them to each other via Au—Sn alloy layers having a thickness of about 0.8 μm to about 5 μm and filling an insulating resin into a gap between the first semiconductor chip or substrate and the second semiconductor chip after they are joined, the insulating resin having a thermal shrinkage factor of 4% or less, wherein the end of one of the first and second bumps has an area smaller than the end of the other of the first and second bumps, and a fillet of the metal having a lower melting point forms during the heating step and covers at least part of a side wall of the first or second bump with the end having the smaller area.