Patent ID: 8175172

Claim:
A high-speed digital isolator, comprising: a transmitter circuit comprising a first low-voltage differential signal (“LVDS”) interface configured to receive input differential data signals; a receiver circuit comprising a second LVDS interface configured to provide output differential data signals therefrom; a shielded twisted pair cable (“TPC”) comprising first and second electrical conductors and an electrically conductive shield disposed thereover, the TPC being disposed between the transmitter circuit and the receiver circuit and operably coupled thereto, the TPC further being configured to convey the input differential data signals from the transmitter circuit to the receiver circuit, and to provide phantom power to the transmitter circuit from the receiver circuit, via the first and second electrical conductors and the shield, the TPC having an impedance Z 0 associated therewith; first and second termination resistors operably coupled to termination ends of the first and second electrical conductors in the transmitter circuit, respectively, each termination resistor having an impedance of about Z 0 /2; and first and second source resistors operably coupled to source ends of the first and second electrical conductors in the receiver circuit, respectively, each source resistor having an impedance of about Z 0 /2; wherein the transmitter circuit is configured to provide galvanic isolation between the transmitter circuit and the receiver circuit; and wherein the transmitter circuit further comprises a voltage regulator configured to regulate power received from the receiver circuit via the TPC.