Patent ID: 7031858

Claim:
A system for measuring phase uniformity of a multi-phase clock set, where the multi-phase clock set is a set of L clocks, each having frequency f dck and each having a different phase φ m that satisfies φ m =φ offset +2π( m/L )+Δφ m , index “m” is a non-negative integer in the range {0, . . . , L−1}, φ offset is a phase, and Δφ m3 is an error term, said system including: DC phase difference signal generation circuitry, coupled and configured to generate at least one DC phase difference signal in response to a clock pair sequence, wherein the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and the at least one DC phase difference signal is indicative of the phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence; means for processing the at least one DC phase difference signal to generate an indication of the phase uniformity of the multi-phase clock set; and multiplexer circuitry having first inputs coupled to receive at least some of the clocks of the multi-phase clock set, second inputs coupled to receive at least some of the clocks of the multi-phase clock set, and a pair of outputs coupled to the DC phase difference signal generation circuitry, wherein the multiplexer circuitry is configured to assert to the outputs any selected one of the clocks received at the first inputs and any selected one of the clocks received at the second inputs.