Patent ID: 6936885

Claim:
A NAND-type flash memory device comprising: a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other; a string selection line pattern and a ground selection line pattern crossing over the plurality of isolation layers and running parallel with each other; a plurality of word line patterns arranged between the string selection line pattern and the ground selection line pattern; source regions adjacent to the ground selection line pattern and formed at active regions opposite the string selection line pattern; an interlayer insulating layer covering the entire surface of the substrate where the string selection line pattern, the ground selection line pattern, and the plurality of word lines are formed, and having a slit-type common source line contact hole exposing the source regions and the isolation layers between the source lines; a barrier insulating layer formed on sidewalls of the slit-type common source line contact hole; and a metal common source line formed in the slit-type common source line contact hole where the barrier insulating layer is formed, and electrically connected to the source regions.