Patent ID: 8482748

Claim:
An image processing apparatus comprising: a dynamically reconfigurable processor that dynamically changes a configuration thereof and that is configured to make internal data paths dynamically changeable to perform image processing in accordance with the changed configuration; a memory that stores setting information for setting a change of the configuration of the dynamically reconfigurable processor, printing information used for image processing to be performed by the dynamically reconfigurable processor, and image information generated through image processing performed by the dynamically reconfigurable processor the memory including a pre-processing information memory area storing the setting information and the printing information and post-processing information memory area storing the image information; a setting information writing unit that writes the setting information to the memory; a printing information writing unit that writes the printing information to the memory; an image information reading unit that reads the image information from the memory; and an instruction unit that instructs the dynamically reconfigurable processor to start execution of image processing, wherein in a case where the dynamically reconfigurable processor is caused to successively execute first image processing and second image processing, the setting information writing unit writes setting information corresponding to the second image processing in parallel with the first image processing, the printing information writing unit writes printing information to be used for the second image processing to the processing information memory area in parallel with the first image processing while the dynamically reconfigurable processor is executing the first image processing, the instruction unit instructs that execution of the second image processing be started after the dynamically reconfigurable processor completes the first image processing, the image information reading unit reads image information corresponding to the first image processing from the post-processing information memory area in parallel with second image processing while the dynamically reconfigurable processor is executing the second image processing, and the first image processing does not execute in parallel with the second image processing.