Patent ID: 7773169

Claim:
A flat panel display, comprising: a first substrate; two adjacent gate lines formed on the first substrate; a data line insulated from the gate lines and intersecting the gate lines; a first sub pixel electrode and a second sub pixel electrode formed on the first substrate; a coupling electrode disposed in each pixel area and overlapping the second sub pixel electrode; a first thin film transistor comprising a first terminal connected to one of the two gate lines, a second terminal connected to the data line, and a third terminal connected to the first sub pixel electrode; a second thin film transistor comprising a first terminal connected to the one of the two gate lines, a second terminal connected to the data line, and a third terminal connected to the second sub pixel electrode; and a third thin film transistor comprising a first terminal connected to the other of the two gate lines, a second terminal connected to the first sub pixel electrode, and a third terminal connected to the coupling electrode.