Patent ID: 7555091

Claim:
A test control unit within a clock and data recovery circuit that comprises a plurality of comparators, a data alignment path unit, a plurality of phase detectors, digital control circuitry, and a plurality of phase interpolators, connected in a loop configuration in which the plurality of comparators are connected to the data alignment path unit and the data alignment path unit is connected to the plurality of phase detectors and the plurality of phase detectors are connected to the digital control circuitry and the digital control circuitry is connected to the plurality of phase interpolators and the plurality of phase interpolators are connected to the plurality of comparators, wherein said test control unit comprises: test control circuitry that receives from the clock and data recovery circuit signals that indicate an operational status of the clock and data recovery circuit and that determines from the received signals whether the operational status of the clock and data recovery circuit passes or fails a test that is performed by the test control circuitry, wherein said test control circuitry comprises: first electronic circuitry that causes said clock and data recovery circuit to continuously alter a phase of an interpolated clock signal within said clock and data recovery circuit; second electronic circuitry that receives at least one preselected bit pattern from a user of said test control unit; and third electronic circuitry that imposes said at least one preselected bit pattern on an input of said plurality of phase detectors.