Patent ID: 6915470

Claim:
A data log acquisition circuit for acquiring a data log in correspondence with a test pattern in a test by using an IC tester, comprising: a number-of-patterns output section to count a number of an executed test pattern and output a count value thereof; an identity signal output section to compare one of an address of the test pattern and the count value with a predetermined reference value and output an identity signal when the one of the address and the number of the executed test pattern and the predetermined reference value are data for the same test pattern; an output flag control section to control an output flag on a basis of setting of an operation mode when the identity signal outputted by the identity signal output section is inputted; a write address output section to generate and output a write address of the data log when the output flag is inputted by the output flag control section; a data log output section to output the data log at a timing adjusted for writing the address of the test pattern as a data log; and a storage section to store the data log outputted by the data log output section together with the write address inputted from the address output section, wherein, during operation, when the operation mode is in a first state, the data log is acquired from a range of test pattern addresses so as to include an address at which a FAIL signal is generated, and when the operation mode is in a second state, the data log is acquired for all test pattern addresses in the range.