Patent ID: 7240140

Claim:
An apparatus, comprising: N bus lines, wherein N is a natural number; log 2 (N) pairs of bit lines, wherein each of said log 2 (N) pairs of bit lines includes a high bit line and a low bit line, and wherein each of said N bus lines is coupled to one of said high and low bit lines; log 2 (N) NOR gates, each having at least a first input, a second input and an output, wherein each NOR gate is associated with one of said log 2 (N) pairs of bit lines, and wherein for each NOR gate, said first input is coupled to said high bit line and said second input is coupled to said low bit line of one of said log 2 (N) pairs; and a multi-hit line coupled to each output of said log 2 (N) NOR gates.