Patent ID: 7441214

Claim:
A semiconductor integrated circuit designing apparatus for automatically generating a pattern of a semiconductor integrated circuit under control of a computer, said apparatus comprising: an input means for inputting gate level logic circuit information, standard cell library information, and package information of a circuit block as a constituent of the semiconductor integrated circuit; a noise estimation means for estimating an amount of noise that may occur in the circuit block, using the information inputted by the input means; a capacitance constraint designation means for designating a capacitance constraint that is a capacitance of a bypass condenser for reducing power supply noise and substrate noise, which bypass condenser is to be incorporated in the circuit block to restrict the amount of noise within a predetermined range, on the basis of a result of estimation by the noise estimation means; a comparison means for comparing an on-chip capacitance that is a capacitance of a bypass condenser incorporated in the circuit block, with the capacitance constraint; a processing ending means for ending the automatic generation of the pattern of the semiconductor integrated circuit, when the on-chip capacitance is larger than the capacitance constraint in the comparison by the comparison means; a logic gate selection means for selecting a logic gate in the circuit block, which logic gate generates an amount of noise equal to or larger than a predetermined amount of noise, when the on-chip capacitance is equal to or smaller than the capacitance constraint in the comparison by the comparison means; and a bypass condenser addition means for adding a bypass condenser to the logic gate selected by the logic gate selection means.