Patent ID: 7869260

Claim:
A semiconductor storage device comprising: a memory cell array having a plurality of memory cells arranged at intersections of a plurality of first wirings and a plurality of second wirings, each of the memory cells including a variable resistance element capable of taking on four or more types of resistance values; a control circuit selectively driving the first wirings and the second wirings; a sense amplifier circuit comparing, with a reference voltage, a voltage generated by a current flowing through a selected memory cell arranged at an intersection of the first wiring and the second wiring selectively driven by the control circuit; and a reference voltage generation circuit generating the reference voltage, the reference voltage generation circuit comprising: a resistance circuit including first resistive elements and second resistive elements connected in parallel, each of the first resistive elements having a resistance value substantially the same as a maximum resistance value in the variable resistance elements, and each of the second resistive elements having a resistance value substantially the same as a minimum resistance value in the variable resistance elements; and a current regulator circuit averaging currents flowing through the first resistive elements and the second resistive elements.