Patent ID: 8571159

Claim:
A clock and data recovery circuit comprising: a sampler circuit arranged to receive a data signal and a sampling clock and generate a feedback signal which is responsive to a phase of the data signal relative to the sampling clock signal; a de-multiplexer circuit arranged to de-multiplex the feedback signal and output a de-multiplexed feedback signal; a voting circuit arranged to decimate the de-multiplexed feedback signal and output a decimated feedback signal; a digital filter circuit arranged to filter the decimated feedback signal from the voting circuit and to output a filtered feedback signal; a finite state machine circuit arranged to receive the filtered feedback signal and generate an interpolator control signal; and a phase interpolator circuit arranged to generate the sampling clock responsive to a reference clock and the interpolator control signal, wherein the de-multiplexer circuit comprises higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.