Patent ID: 8339154

Claim:
A method for testing a line comprising an input/output pin of a programmable logic circuit, said line comprising at least one individual line extending from the input/output pin to a peripheral element, said input/output pin being able to be either at a high logic level or at a low logic level opposite to the high logic level, said method comprising the following steps: between an initial driving instant and a final driving instant, a step for driving the input/output pin in which a driving voltage is applied to the terminals of the input/output pin, from the final driving instant, a step for measuring the level of the input/output pin during which the pin is no longer driven and during which a measured logic level is recorded for the input/output pin at, at least one measuring instant, the measured logic level(s) is/are compared, at the respective measuring instant(s), with the theoretical logic level(s) at which the input/output pin should be at the respective measuring instant(s) in the absence of any line failure, when at least one logic level measured at a measuring instant differs from the theoretical logic level at said measuring instant, a line failure is detected.