Patent ID: 8654884

Claim:
A circuit for performing channel equalisation in a high speed transmission system comprising a transmitter and a receiver, the circuit comprising: an application specific digital signal processor, ASDSP, for performing channel equalisation and compensation on digital data received from an analogue-to digital converter of the receiver; an ASDSP register for storing equalizer parameters and bit error rate measurements, and coupled between the ASDSP and a system CPU (central processing unit) in a feedback loop for performing channel equalisation at the receiver; an ASDSP program storage memory, coupled to and accessible by the ASDSP, for storing an ASDSP micro-sequence program for controlling processing steps for channel equalisation and dataflow through the ASDSP; and wherein the ASDSP is operable to select an equalizer and or a clock and data recovery CDR function from a plurality of different equalizer and CDR algorithms, and to execute an application specific set of op-codes for performing the selected equalizer and CDR algorithms based on information received by the ASDSP pertaining to any one of: external or internal adaptations, constraints imposed by the system CPU, and selection criteria comprising optimization criterion stored in the ASDSP register.