Patent ID: 7454654

Claim:
A digital data processing apparatus, comprising: a plurality of processors, each said processor comprising a respective instruction unit for supporting execution of at least one respective thread of processor-executable instructions independently of threads being executed by any other processor of said plurality of processors; a plurality of parallel pipelines, each pipeline of said plurality of parallel pipelines having the capability to perform a set of pre-defined functions on respective input data, said plurality of pipelines including at least one redundant pipeline, said at least one redundant pipeline being shared by each said processor of said plurality of processors; and control logic controlling the routing of data to said plurality of parallel pipelines, wherein said control logic, responsive to detection of a failure of a first pipeline of said plurality of parallel pipelines, causes data intended for processing by said first pipeline to be processed by a said redundant pipeline; wherein said plurality of parallel pipelines comprises a plurality of discrete pipeline subsets, including (a) a respective discrete pipeline subset associated with each said processor of said plurality of processors, each respective discrete pipeline subset associated with a processor containing at least one said pipeline, each said pipeline of a respective subset processing data on behalf of the processor with which it is associated; and (b) a discrete pipeline subset containing at least one redundant pipeline; and, wherein said plurality of parallel pipelines are arranged in an array physically adjacent one another, wherein each said redundant pipeline is located in said array between a respective pair of said discrete pipeline subsets each associated with a respective processor.