Patent ID: 8796867

Claim:
A semiconductor package, comprising: a packaging substrate having an insulating protection layer and a circuit layer embedded in the insulating protection layer, wherein the circuit layer comprises a first sub-circuit layer, a second sub-circuit layer and a third sub-circuit layer in sequence and has opposite first and second surfaces, the first surface of the circuit layer is exposed from a surface of the insulating protection layer, and an opposite surface of the insulating protection layer has at least an opening formed therein for exposing a portion of the second surface of the circuit layer; a chip disposed on the packaging substrate and electrically connected to the first surface of the circuit layer; and an encapsulant formed on the packaging substrate for encapsulating the chip, wherein the first sub-circuit layer is made of gold or silver, the second sub-circuit layer is made of nickel, and the third sub-circuit layer is made of copper.