Patent ID: 7790610

Claim:
A method of manufacturing a memory unit, the method comprising: forming a plurality of first nanowire structures on a first substrate, each of the first nanowires including a first nanowire and a first electrode layer, the first nanowire extending in a first direction parallel to the first substrate, and the first electrode layer enclosing the first nanowire; partially removing the first electrode layers to form first electrodes beneath the first nanowires; forming a first insulation layer on the first substrate, the first insulation layer filling up spaces between structures each of which includes the first nanowire and the first electrode; forming a second electrode layer on the first nanowires and the first insulation layer; forming a plurality of second nanowires on the second electrode layer, each of the second nanowires extending in a second direction perpendicular to the first direction; and partially etching the second electrode layer using the second nanowires as an etching mask to form a plurality of second electrodes.