Patent ID: 6844769

Claim:
An amplitude expansion circuit comprising: a first DC power supply line to which a first potential is applied; a second DC power supply line to which a second potential is applied; an intermediate power supply line to which an intermediate potential between the first potential and the second potential is applied; a first inverter circuit receiving a first pulse signal changing between the first potential and the intermediate potential, the first inverter circuit operating with power supplies from the first DC power supply line and the intermediate power supply line; a second inverter circuit receiving a second pulse signal outputted from a level shift circuit, the second pulse signal changing between the second potential and the intermediate potential, the second inverter circuit operating with power supplies from the second DC power supply line and the intermediate power supply line; a first MOSFET of one conductivity connected between the second DC power supply line and the first DC power supply line, a gate of the first MOSFET receiving an output signal from the second inverter circuit; a second MOSFET of the one conductivity connected between the first MOSFET and the first DC power supply line, a gate of the second MOSFET being connected to the intermediate power supply line; a third MOSFET of the other conductivity connected between the second MOSFET and the first DC power supply line, a gate of the third MOSFET receiving an output signal from the first inverter circuit; and a fourth MOSFET of the other conductivity connected between the second MOSFET and the third MOSFET, a gate of the fourth MOSFET being connected to the a fifth MOSFET of the other conductivity connected between a common connection node of the first MOSFET and the second MOSFET and the intermediate power supply line, a gate of the fifth MOSFET being connected to the second DC power supply line; and a sixth MOSFET of the one conductivity connected between a common connection node of the third MOSFET and the fourth MOSFET and the intermediate power supply line, a gate of the sixth MOSFET being connected to the first DC power supply line. wherein a common connection node of the second MOSFET and the forth MOSFET is an output terminal of the amplitude expansion circuit.