Patent ID: 7601607

Claim:
A method of fabrication of an interconnect opening for a semiconductor device; comprising the steps of: forming a lower interconnect and an insulating layer over a semiconductor structure; forming a first hardmask over said lower interconnect and said insulating layer; forming a dielectric layer over said first hardmask layer; forming a second hardmask over said dielectric layer; in a first etch step, etching a first interconnect opening in said first hardmask, said dielectric layer and said second hardmask layer; the dielectric layer in said first interconnect opening has sidewalls; the first hardmask has an first hardmask overhang and the second hardmask has a second hardmask overhang where said first hardmask overhang and said second hardmask overhang extend out past the sidewall of the dielectric layer; in a second etch step, etching the first and second hardmask overhangs and the dielectric layer form a first overhang-less interconnect opening; the second etch step essentially removes said first and second hardmask overhangs; forming an interconnect in said first overhang-less interconnect opening.