Patent ID: 7148103

Claim:
A method of manufacturing a semiconductor device on a semiconductor substrate, comprising a first electronic circuit in a baseline technology and at least a second electronic circuit in a first option technology, said first and second electronic circuits being functional parts of a system-on-chip, said method comprising the steps of: manufacturing said first electronic circuit with at least a first conductive layer that is patterned by subjecting an exposed portion of said first conductive layer to Reactive Ion Etching; manufacturing said second electronic circuit with at least a second conductive layer that is patterned by subjecting an exposed portion of said at least second conductive layer to Reactive Ion Etching; providing at least one dummy structure; wherein the method further comprises the following steps: providing said at least one dummy structure with at least one dummy conductive layer produced in the same processing step as one of said at least second conductive layer; and exposing at least a portion of said at least one dummy conductive layer to obtain an exposed portion of said at least one dummy conductive layer, and Reactive Ion Etching of said exposed portion of said at least one dummy conductive layer too when said one of said at least second conductive layer is subjected to Reactive Ion Etching.