Patent ID: 8468273

Claim:
A memory device comprising: a first memory means; a command analysis means for analyzing at least one command from an information processing device having a second memory means and for determining whether the command should be executed by a first data transfer mode directly addressing a physical address of the second memory means or a second data transfer mode indirectly addressing a physical address of the second memory means; an information transfer control means for controlling information transfer between the first memory means and the second memory means based on the determination of the command analysis means, and further wherein in the direct transfer mode a host system directly writes transfer information to a register of the memory device and when data is transferred indirectly, the host system writes an address at which a linked list is stored in the register of the memory device, wherein the first data transfer mode is used to provide information to said information processing device if a physical space in the second memory is successive and the second data transfer mode is used to transfer information to the information processing device if the physical space in the second memory means is not successive.