Patent ID: 7262090

Claim:
A method for making random access memory (RAM) capacitors in a shallow trench isolation comprising the steps of: providing a substrate having said shallow trench isolation surrounding active device areas; forming a pad oxide layer on said substrate; forming a first hard-mask layer on said pad oxide layer; forming a photoresist mask having opening that lie over and within said shallow trench isolation areas; anisotropically etching recesses in said first hard-mask layer, said pad oxide layer, and partially into said shallow trench isolation and leaving portions of said shallow trench isolation along edges of said active device areas thereby preventing plasma-etching damage to said active device areas during said etching; isotropically etching exposed surfaces of said shallow trench isolation and removing said portions and recessing said pad oxide layer under said first hard-mask layer to expose said substrate for capacitor node contacts; depositing a conformal first conducting layer and etching back to said first hard-mask layer to form capacitor bottom electrodes in said recesses; forming an interelectrode dielectric layer over said bottom electrodes; and depositing a conformal second conducting layer to fill up said recesses.