Patent ID: 8653857

Claim:
A circuit, comprising: a first input node; a second input node; a common node; a pass gate connected to be controlled by a logic state present at the second input node, the pass gate connected to pass through a version of a logic state present at the first input node to the common node when controlled to transmit by the logic state present at the second input node; a transmission gate connected to be controlled by the logic state present at the first input node, the transmission gate connected to pass through a version of the logic state present at the second input node to the common node when controlled to transmit by the logic state present at the first input node; and pullup logic connected to be controlled by both the logic state present at the first input node and the logic state present at the second input node, the pullup logic connected to drive a state present at the common node when both the logic state present at the first input node and the logic state present at the second input node are high.