Patent ID: 7064369

Claim:
A method for fabricating a semiconductor device including a polysilicon insulator polysilicon (PIP) capacitor and a metal oxide semiconductor (MOS) transistor, comprising the steps of: depositing an isolator film on a semiconductor substrate; etching the isolator film to expose an active region of the semiconductor substrate; forming an epitaxial film on the exposed active region by performing a selective epitaxial silicon growth process thereon, wherein the epitaxial film has a thickness that is greater than the isolator film; sequentially depositing a first polysilicon film, a dielectric film and a second polysilicon film on an entire surface of the etched isolator film and the epitaxial film; forming an upper electrode of the capacitor on the etched isolator film by patterning the second polysilicon film and the dielectric film, wherein a portion of the dielectric film located below the upper electrode remains; forming a lower electrode of the capacitor and a gate electrode of the transistor by patterning the first polysilicon film on the etched isolator film and the epitaxial film, respectively; forming a source/drain region in an upper portion of the epitaxial film, the source/drain region including a source region separated from a drain region by the gate electrode; depositing an interlayer insulation film on a structure obtained at the step of forming the source/drain region and forming contact holes in the interlayer insulation film; and forming contacts connected to the upper electrode, the lower electrode, the gate electrode and the source/drain region, wherein the distance between a top surface of the substrate and a top surface of the epitaxial film is substantially identical to the distance between the top surface of the substrate and a top surface of the lower electrode of the capacitor.