Patent ID: 8081416

Claim:
A multilayer chip capacitor comprising: a capacitor body provided by a stack of a plurality of dielectric layers; a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes; and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode, wherein each of the plurality of internal electrodes comprises: a main electrode part; at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes, the lead extending to the corresponding external electrode to be inclined with respect to the main electrode part thereof, the lead has a gradually greater width at its connection portion with the corresponding external electrode and a gradually smaller width at its connection portion with the main electrode part, and all leads connected to the external electrode disposed at an end portion of the side face of the capacitor body extend toward a central portion of the main electrode part from the external electrode disposed at the end portion of the side face of the capacitor body.