Patent ID: 7990794

Claim:
A method of operating a semiconductor device including a plurality of memory cells, each memory cell including a drain region, a source region, a floating body region, and a gate electrode, the method comprising: erasing at least one of the memory cells in an erase mode and setting a data value of the at least one of the memory cells to a first state, by transitioning a drain voltage pulse applied to the drain region from an enable voltage to a standby voltage and a gate voltage pulse applied to the gate electrode from an enable voltage to a standby voltage; writing to the at least one of the memory cells in a write mode and setting the data value of the at least one of the memory cells to a second state, by transitioning a gate voltage pulse applied to the gate electrode from an enable voltage to a standby voltage and then a drain voltage pulse applied to the drain region from an enable voltage to a standby voltage; and applying a constant source voltage to the source region in the erase mode and the write mode, respectively.