Patent ID: 7196541

Claim:
An electronic circuit with an array of programmable logic cells, each of the cells comprising: an input circuit with a plurality of logic inputs; an output circuit; a plurality of programmable logic units, coupled in parallel between the input circuit and the output circuit, the input circuit being configurable between a random logic mode and a multi-bit operand processing mode, at least one of the programmable logic units comprising: a configurable look-up table circuit, having inputs coupled to receive the logic input signals from the input circuit and having an output; a controllable inverter/non-inverter circuit, having an input coupled to receive the output of the look-up table circuit, the output of the inverter/non-inverter circuit being connectable to the output circuit; and a multiplexer, having inputs coupled to receive the logic input signals from the input circuit, and having a multiplexer output connectable to the output circuit.