Patent ID: 7660562

Claim:
A method of combining impedance matching and harmonic rejection, comprising the steps of: providing an impedance matching circuit at a fundamental frequency (F o ), said matching circuit comprising: a first shunt arm having a first, impedance-matching-required, effective capacitance at said fundamental frequency, comprising, in parallel, a first shunt path having a first capacitor and a first inductor in series and a second shunt path having a second capacitor and a second inductor in series, providing rejection at a first harmonic frequency and at a second harmonic frequency; a series arm comprising a first inductive element having a first, impedance-matching-required inductance at said fundamental frequency, and a third inductor and a third capacitor in parallel, wherein said third capacitor acts as an effective open circuit at said fundamental frequency but parallel resonates with said third inductor in the vicinity of a third harmonic frequency, thereby providing rejection of said third harmonic frequency; and a second shunt arm located between said first inductive element and an output port of said impedance matching circuit, said second shunt arm comprising, in series, a fourth capacitor and a fourth inductor selected to have a second, impedance-matching-required capacitance at said fundamental frequency and harmonic rejection at a fourth harmonic frequency, wherein (i) said first shunt path provides harmonic rejection at said first harmonic frequency, (ii) said second shunt path provides harmonic rejection at said second harmonic frequency, and (iii) said first shunt path and said second shunt path in combination parallel resonate to an open circuit at a frequency substantially equal to a series resonance of said fourth capacitor and said fourth inductor in said second shunt arm.