Patent ID: 6879992

Claim:
A computing system, comprising: a rounding apparatus for rounding an input value to a nearest integer to accept an input value that is a real number represented in floating-point format, and to perform a rounding operation on the input value to generate an output value that is an integer represented in floating-point format, the rounding apparatus comprising: a sign bit extractor to determine an extracted sign bit of the input value, an adjustment generator to perform an “OR” operation on the extracted sign bit and a selected real value, generating an adjustment value, an adding unit to compute an adjusted input value by adding the adjustment value to the input value, the adjusted input value being a real number represented in floating-point format, a floating-point to integer converter to truncate a fractional portion of the adjusted input value to convert the adjusted input value to an integer represented in an integer format, and an integer to floating-point converter to convert the integer represented in an integer format to generate the output value; a memory to store a computer program that utilizes the rounding apparatus; and a central processing unit (CPU) to execute the computer program, the CPU is cooperatively connected to the rounding apparatus and the rneruozy, wherein the adjustment generator generates the adjustment value by performing a bit-wise logical OR operation on the sign bit and the selected real value, where the selected real value is 0.5.