Patent ID: 8217450

Claim:
A semiconductor device, comprising: a substrate; an insulating layer formed on the substrate; a fin formed on the insulating layer, the fin comprising a first sidewall, a second sidewall opposite the first sidewall, and a top surface, the fin having a width ranging from approximately 100 Å to 1000 Å; a first gate formed adjacent the first sidewall of the fin, the first gate comprising a conductive material and being doped with an n-type impurity without being doped with a p-type impurity; a second gate formed adjacent the second sidewall of the fin, the second gate comprising a conductive material and being doped with the p-type impurity without being doped with the n-type impurity, the first gate and the second gate being electrically separated by the fin; a third gate formed adjacent the first sidewall of the fin, the third gate comprising a conductive material, the third gate being physically separated from the first gate; and a fourth gate formed adjacent the second sidewall of the fin, the fourth gate comprising a conductive material, the fourth gate being physically separated from the second gate, and the third gate and the fourth gate being electrically separated by the fin.