Patent ID: 7472331

Claim:
A memory system comprising: a plurality of non-volatile memory cells arranged in blocks with each block including a plurality of pages of non-volatile memory cells, the plurality of non-volatile memory cells including a plurality of data blocks of non-volatile memory cells, a plurality of reserved blocks of non-volatile memory cells, and at least one management block of non-volatile memory cells; and a memory controller coupled to the plurality of non-volatile memory cells, the memory controller being configured to receive a data address for a page of non-volatile memory cells of a data block during a memory access operation, to determine if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block, and to direct the memory access operation to a page of a reserved block of non-volatile memory cells if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block wherein the memory controller is further configured to copy information from the at least one management block of non-volatile memory cells to volatile memory and wherein determining if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block includes determining if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the information copied to volatile memory.