Patent ID: 8869089

Claim:
A method of designing a semiconductor integrated circuit using a semiconductor integrated circuit (IC) design apparatus, the method comprising: accessing a first layout of a semiconductor IC from a layout database of the semiconductor IC design apparatus, the first layout stored in the layout database, the first layout including a plurality of cells arranged adjacent to each other, each one of the plurality of cells indicating structural features in the semiconductor IC in a corresponding part of semiconductor IC; creating a marking layer using a marking layer creation unit of the semiconductor IC design apparatus, the marking layer indicating at least one structural feature of the structural features in the semiconductor IC that is to be changed in at least one of width, height, and space thereof from an adjacent structural feature of the structural features in the semiconductor IC, the marking layer being based on a change in characteristics of at least one semiconductor device defined by at least one of the structure features in the semiconductor IC; and generating a second layout of the semiconductor IC by the applying the marking layer using a library creation unit of the semiconductor IC design apparatus to a selected cell of the plurality of cells in the first layout; and generating a new library of the semiconductor IC from the second layout, the new library indicating the at least one structure feature of the structural features in the semiconductor IC that is changed in at least one of width, height, and space from the adjacent structural feature in the semiconductor IC.