Patent ID: 7337415

Claim:
A method of modifying circuit design source data of a three-dimensional structure for improving integrated circuit yield, the method being implemented with computer program code and hardware and comprising the steps of: locating a problem structure using a shapes-processing tool; and implementing at least one local modification to said three-dimensional structure to perform a fix-up process on the problem structure, wherein the method comprises one from the group consising of: introduces jogs in wires of one layer arranged above wires of another layer; introduces segments of wrong-way wiring in wires of one layer arranged above wires of another layer; increases a space of minimum-spaced wires over a wider structure; forms a dummy hole in an incompatible structure component of a first layer of the problem structure to reduce manufacturing defects of a structure component in a second layer of the problem structure; and widens a trench of a lower layer of the problem structure under at least one wire of an upper layer of the problem structure.