Patent ID: 8258809

Claim:
A system on chip (SoC) comprising: a memory including a plurality of bit cells arranged to correspond to bit values of a first security key, each of the plurality of bit cells comprising an electrical fuse, wherein the plurality of bit cells are configured to output data bits corresponding to the first security key and the plurality of bit cells are configured to be programmed using the electrical fuses to output data bits corresponding to a second security key, wherein the memory of the SoC further includes a plurality of electrical fuse units corresponding to the respective bit cells each electrical fuse unit including: a master fuse including a first terminal to which a program enable signal is applied; a master fuse blow circuit coupled to a second terminal of the master fuse, the master fuse blow circuit being configured to blow the master fuse in response to a master fuse blow enable signal; a driver configured to generate a fuse blow enable signal in response to an output signal of the master fuse blow circuit; and a bit cell fuse circuit configured to program a corresponding bit cell of the plurality of bit cells in response to the fuse blow enable signal.