Patent ID: 8552490

Claim:
A nonvolatile memory device, comprising: a substrate, wherein a memory cell region is defined on the substrate; a first stacked gate structure, disposed on the memory cell region of the substrate, the first stacked gate structure from bottom to top sequentially comprising: a tunneling dielectric layer; a charge storage layer; an inter-gate dielectric layer, wherein the inter-gate dielectric layer covers the charge storage layer to form a U-shaped cross-sectional structure; a first metal gate having a first sidewall; and a barrier metal layer disposed between the first metal gate and the inter-gate dielectric layer, wherein the barrier metal layer is disposed under the first metal gate, and extends upwardly along the first sidewall of the first metal gate; a spacer disposed on the first sidewall of the first metal gate and overlapping the first sidewall, wherein the overlapped first sidewall is entirely surrounded by the inter-gate dielectric layer; and a source region and a drain region, disposed in the substrate and respectively disposed at two opposite sides of the first stacked gate structure.