Patent ID: 7491588

Claim:
A method of fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a single-crystal semiconductor layer separated from a bulk semiconductor region by a buried oxide layer, said method comprising: forming a plurality of field effect transistors (FETs) including a first FET and a second FET, each of the plurality of FETs having a channel region disposed in a common device layer within the single-crystal semiconductor layer, the first FET having a gate overlying an upper surface of the common device layer, the second FET having a gate underlying a lower surface of the common device layer remote from the upper surface, the first and second FETs sharing a common diffusion region disposed in the common device layer, the first and second FETs being conductively interconnected by the common diffusion region, the common diffusion region being operable as at least one of a source region or a drain region of the first FET and being simultaneously operable as at least one of a source region or a drain region of the second FET, wherein the CMOS circuit comprises a dynamic two-phase shift register, the gate of the first FET is connected to a first conductor for receiving a first clock signal and the gate of the second FET is connected to a second conductor for receiving a second clock signal such that the first and second FETs form the dynamic two-phase shift register.