Patent ID: 7948285

Claim:
A PLL circuit, comprising: a phase comparison unit that compares an accumulated addition value of a division ratio converted into a digital value and that of a clock count of an oscillating signal from an oscillator controlled by using the digital value in each cycle of a reference frequency; a data conversion unit that has a variable gain amplification unit to change a gain and causes output of the phase comparison unit to converge to an arbitrary setting value; an offset detection unit that detects an offset arising due to a change in gain of the variable gain amplification unit using output of the phase comparison unit; and an offset compensation unit that compensates for the offset detected by the offset detection unit in timing when the gain of the variable gain amplification unit changes, wherein the data conversion unit, comprising: a first variable gain amplification unit that amplifies the output of the phase comparison unit; an addition unit that adds the division ratio to the output of the first variable gain amplification unit; a second variable gain amplification unit that has the same gain as that of the first variable gain amplification unit and amplifies the setting value; a subtraction unit that subtracts the output of the second variable gain amplification unit from that of the addition unit; and a multiplication unit that multiplies the output of the subtraction unit by a value obtained by dividing the reference frequency by the conversion gain of the oscillator.