Patent ID: 7640486

Claim:
A method for rate matching a number of input bits in a time interval to a fixed total number of output bits in the time interval, the method comprising: providing that the input bits consist of a set of at least two different bit classes, each of the different bit classes having a certain number of bits in the time interval; and performing the rate matching in two rate matching stages; wherein a first rate matching stage punctures bits of a selection from the set of different bit classes to establish a proportion between the number of bits of the different classes; wherein a second rate matching stage repeats bits of all the different bit classes such that the proportion is at least approximately maintained after the second rate matching stage and the fixed total number of output bits consisting of bits of the different bit classes is achieved; wherein the set of different bit classes includes at least a systematic bit class with systematic bit carrying payload and at least one parity bit class with parity bits carrying checksum information; and wherein the proportion is maintained in the second rate matching stage by choosing N t , sys = ⌈ N sys · N data N sys + N p ⁢ ⁢ 1 + N p ⁢ ⁢ 2 ⌉ , ⁢ N t , p ⁢ ⁢ 1 = ⌊ N data - N t , sys 2 ⌋ ⁢ ⁢ and N t , p ⁢ ⁢ 2 = ⌊ N data - N t , sys 2 ⌋ where N data denotes the fixed total number of output bits, N t,sys is the number of output bits of the systematic bits N sys , N t,p1 is the number of output bits of a first class of parity bits N p1 and N t,p2 is the number of output bits of a second class of parity bits N p2 .