Patent ID: 8306100

Claim:
A test circuit, comprising: a data masking control unit configured to mask a part of output data in response to an activation of one of an upper data masking signal to control a group of upper data pins and a lower data masking signal to control a group of lower data pins when a test mode signal is activated at a read operation, wherein the data masking control unit comprises: a clock-control signal generating unit configured to receive a read command and generate a first clock-control signal and a second clock-control signal in response to the upper data masking signal and the lower data masking signal, respectively; a DLL clock signal generating unit configured to generate an upper data clock signal and a lower data clock signal in response to the first clock-control signal and the second clock-control signal, respectively; and a data strobe signal generating unit configured to generate an upper data strobe signal and a lower data strobe signal, which are used as reference signals for an upper data output and a lower data output, in response to the upper data clock signal and the lower data clock signal.