Patent ID: 7461215

Claim:
A method of controlling a flow of packets in an advanced processor having a plurality of processor cores, the method comprising the steps of: placing a request for data on a request ring, the request ring being one of a plurality of rings coupling a plurality of ring elements together; checking for the data in each of the plurality of processor cores; receiving the request in a memory bridge coupled to the request ring and having at least one of the plurality of ring elements; placing the data on a data ring to support a memory ordering, the data ring being one of the plurality of rings; and acknowledging, on a response ring, the placement of the data on the data ring, the response ring being one of the plurality of rings and being separate from the data ring; wherein each ring element includes: a first flip-flop configured to receive a ring input and to provide a first signal to a second flip-flop, a third flip-flop, and a first multiplexer; and a second multiplexer configured to receive a second signal from a fourth flip-flop and a third signal from a fifth flip-flop and to provide a fourth signal to the first multiplexer, the first multiplexer being configured to provide a ring output.