Patent ID: 7476922

Claim:
A logic device comprising: a semiconductor substrate; a lower interconnect layer located over the semiconductor substrate; an upper interconnect layer located over the lower interconnect layer; a plurality of U-shaped lower metal plates interposed between the lower interconnect layer and the upper interconnect layer, and spaced from each other being in contact with the lower interconnect layer; capacitor dielectric layers covering the inner surface of the respective lower metal plates and having extension portions interposed between a brim of the lower metal plates and the upper interconnect layer; upper metal plates covering the inner surface of the respective capacitor dielectric layers, wherein each of the upper metal plates is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer; a second lower interconnect layer located at the same level as the first lower interconnect layer; a second upper interconnect layer located at the same level as the first upper interconnect layer; a via plug for electrically connecting the second lower interconnect layer and the second upper interconnect layer; an interlayer insulating layer, surrounding the via plug, interposed between the second upper interconnect layer and the second lower interconnect layer; and a via diffusion barrier layer interposed between the interlayer insulating layer and the via plug, and interposed between the second lower interconnect layer and the via plug, wherein the via diffusion barrier layer is formed of a different material than the upper metal plate layer.