Patent ID: 6859870

Claim:
A computer system comprising: a processor having a very large word instruction architecture and including a plurality of clusters of functional processing units, each one cluster of the plurality of clusters comprising a common number of functional processing units, the processor comprising a first prescribed number of clusters, said very large word instruction architecture allowing an instruction to have up to a second prescribed number of subinstructions, where the second prescribed number equals the first prescribed number times the common number, each instruction to be executed by the processor comprising from one subinstruction up to the second prescribed number of subinstructions, and a set of control bits, the set of control bits including a first subset of control bits equal in number to the second prescribed number, wherein the first subset of control bits identify at least one subinstruction to be shared and a routing pattern for distributing the at least one shared subinstruction; and an instruction cache memory which stores a first VLIW instruction in a compressed format determined by a condition of the first subset of control bits, the compressed format including a at least one shared subinstruction stored in at least one given field of the first VLIW instruction, the at least one subinstruction to be shared by a plurality of the functional processing units, said plurality of functional processing units being determined by said condition of the first subset of control bits, wherein the first subset of control bits allows as many as 2 z permutations for subinstruction sharing within any given VLIW instruction, where z equals said second prescribed number.