Patent ID: 7397885

Claim:
A shift register comprising n stages outputting scan pulses that are sequentially delayed in a forward or reverse direction thereof, where n is positive integer and wherein each stage includes: a scan direction controller that provides a first or second voltage to a scan direction control node according to a first or second enable signal and controlling the forward or reverse direction output; a first node controller that controls a first node according to a voltage on the scan direction control node; a second node controller that controls a second node according to the voltage on the scan direction control node and a voltage on the first node; an output unit that outputs clock signals as scan pulse according to voltages on the first and second nodes; a third node controller that provides one of the first and second voltages to a third node according to the first and second enable signals; a first discharge circuit unit that discharges the voltage on the first node according to voltages of the second and third nodes; and a second discharge circuit unit that discharges the voltage on the third node according to one of a third enable signal and a fourth enable signal.