Patent ID: 8856456

Claim:
A processor comprising: one or more processor cores configured to operate on cache lines from memory shared by another memory-sharing device; one or more caches configured to store a plurality of the cache lines; cache snoop circuitry comprising a table of cache block tracking entries, wherein each of the cache block tracking entries comprises a respective plurality of cache status entries, wherein each cache status entry respectively tracks a status of one or more of the cache lines, and wherein the cache snoop circuitry is configured, when one of the one or more processor cores requests one of the cache lines, to determine whether to issue a snoop request to the other memory-sharing device based at least in part on the table of cache block tracking entries; and a cache block coherence interface communicably interposed between the one or more processor cores and the another memory-sharing device, the cache block coherence interface having associated therewith a second table of cache block tracking entries, each block tracking entry of the second table of cache block tracking entries respectively tracking a possibly-shared status of each of a plurality of groups of one or more cache lines of a different block of memory, wherein the cache block coherence interface is configured to attempt to maintain cache coherence between the another memory-sharing device and the one or more processor cores based at least in part on the second table of cache block tracking entries.