Patent ID: 6975149

Claim:
A data output buffer, comprising: a data driver circuit having a clock node to which a delayed clock signal is applied, an input node at which a data signal is applied, and an output node at which an output data signal is provided in response to the delayed clock signal, the data driver circuit configured to drive the output data signal according to an output drive strength of the data driver; and a delay locked loop (DLL) coupled to the data driver circuit to provide the delayed clock signal for clocking the data driver circuit, the DLL comprising: a first adjustable delay having an input to which an input clock signal is applied, an output at which a first delayed clock signal is provided, and further having a first delay control node to which a first delay control signal is applied, the adjustable delay configured to generate the first delayed clock signal having a first delay relative to the input clock signal that is controlled by the first delay control signal; a second adjustable delay having an input coupled to the output of the first adjustable delay, an output at which a second delayed clock signal is provided, and a second delay control node to which a second delay control signal is applied, the second adjustable delay configured to generate the second delayed clock signal having a second delay relative to the first delayed clock signal that is controlled by the second delay control signal, the second delay control signal indicative of the output drive strength of the data driver; a feedback delay coupled to the second adjustable delay and configured to generate a feedback clock signal responsive to the second delayed clock signal, the feedback clock signal having a model delay relative to the second delayed clock signal; and a comparison circuit having a first input to which the input clock signal is applied, a second input coupled to the feedback delay, and an output at which the first delay control signal is provided, the comparison circuit configured to generate the first delay control signal in response to the relative phases of the input and feedback clock signals.