Patent ID: 7596050

Claim:
A method for use with a memory array having a plurality of array blocks, each array block including word lines and bit lines, said method, in a first mode of operation, comprising: coupling selected bit lines of a selected block to respective data circuits by way of a first global bus generally spanning the plurality of array blocks; coupling unselected bit lines of both selected and unselected array blocks to a respective first bus segment associated with each respective array block; conveying a first unselected bit line bias condition appropriate for the first mode of operation on the respective first bus segment associated with the selected array block; and conveying a second unselected bit line bias condition appropriate for the first mode of operation on the respective first bus segment associated with unselected array blocks; said method further comprising, in a second mode of operation: coupling one or more selected bit lines of a selected array block to the respective first bus segment associated with the selected array block; conveying respective data-dependent bias conditions appropriate for the second mode of operation on the respective first bus segment associated with the selected array block; and coupling unselected bit lines of the selected array block to the first global bus.