Patent ID: 7292495

Claim:
An integrated circuit comprising: a processor; a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line, wherein each of the plurality of memory cells has a write margin and a read margin, wherein the write margin is substantially greater than the read margin, and wherein the write margin is made substantially greater than the read margin by setting a conductance ratio of the memory cell access transistors relative to the memory cell pull-up transistors; and a first power supply voltage node for receiving a first power supply voltage and a second power supply node for receiving a second power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power either all of the plurality of memory cells or at least one of the plurality of memory cells during a first access operation of the plurality of memory cells, and wherein either the first power supply voltage or the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.