Patent ID: 6861736

Claim:
A semiconductor package, which comprises: (a) a leadframe, which includes: (a1) a supporting bar; (a2) a die pad linked to the supporting bar and arranged at a downset position in relation to the supporting bar; and (a3) a plurality of leads, each lead including an outer-lead portion and an inner-lead portion wherein the outer-lead portion is levelly linked to the supporting bar, and the inner-lead portion is substantially levelly arranged in relation to the die pad and linked to the outer-lead portion via an intermediate-lead portion; (b) a chipset including at least one semiconductor chip mounted over the die pad; (c) a set of bonding wires for electrically coupling the semiconductor chip to the inner-lead portions of the leads; and (d) an encapsulation body for encapsulating the semiconductor chip, the die pad, the bonding wires, and the inner-lead portions of the leads, while exposing one surface of the outer-lead portion of each of the leads to outside.