Patent ID: 7721035

Claim:
A multiprocessor system for processing interrupts by a plurality of processors, wherein said multiprocessor system comprises: a first processor, wherein said first processor comprises: an accepting unit configured to accept a first interrupt; a management unit configured to manage a state of a second interrupt processing corresponding to the first interrupt and a state of a second processor; and an executing unit configured to execute a first interrupt processing in accordance with the first interrupt accepted by the accepting unit, wherein, in the first interrupt processing, the executing unit assigns, to the second processor, the second interrupt processing corresponding to the first interrupt accepted by the accepting unit when the second interrupt processing is in a processable state and the second processor is in a state of idle, wherein the executing unit sets the second interrupt processing to a standby state and sets the first interrupt processing to a first standby state when the second interrupt processing is in the processable state and the second processor is in a state of in use, and wherein the executing unit sets the first interrupt processing to a second standby state when the second interrupt processing is in progress based on a second interrupt or the second interrupt processing is in the standby state based on the second interrupt.