Patent ID: 6983535

Claim:
A method for reducing impedance within a reference path in a printed circuit board comprising the steps of: forming said printed circuit board comprising a plurality of conductive layers, wherein one of said plurality of conductive layers is a first layer, wherein one of said plurality of conductive layers is a second layer, wherein said printed circuit board further comprises two or more vias interconnecting two or more conductive layers of said plurality of conductive layers, wherein a first of said two or more vias is part of a signal path configured to carry said signal from said first layer to said second layer, wherein a second of said two or more vias is part of a reference path configured to carry said signal from a third layer to a fourth conductive layer; and embedding an electrical component in said second of said two or more vias between two conductive layers of said plurality of conductive layers; wherein said electrical component has a greater diameter in a center than at ends of said electrical component, wherein each end of said electrical component has a conductive cap which is tinned.