Patent ID: 7411430

Claim:
An analog output buffer circuit for a flat panel display, the analog output buffer circuit comprising: a transistor, comprising a first source/drain directly connected to a first voltage source for receiving the first voltage source continuously, a second source/drain electrically connected to a circuit output node and a gate electrically connected to a first terminal of an input capacitor; a current source, electrically connected between the circuit output node and a second voltage source, for providing a compensatory current for the transistor when a leakage current occurs; an upper switch, electrically connected between an input node and the first terminal of the input capacitor, the upper switch being turned on in a first period; a lower switch, electrically connected between the input node and a second terminal of the input capacitor, the lower switch being turned on in a second period; a first switch, electrically connected between the second terminal of the input capacitor and the circuit output node, the first switch being turned on in the first period; and a second switch, electrically connected between the circuit output node and an output node, the second switch being turned on in a second period, wherein the second period is after the first period in sequence, and a current provided by the current source remains unchanged with an operation of the upper switch and the lower switch.