Patent ID: 7605606

Claim:
A programmable logic device comprising: a plurality of programmable logic blocks; a plurality of logic block slices within each of the programmable logic blocks; an interconnect adapted to provide global routing resources within the programmable logic device; a first routing circuit, corresponding to each programmable logic block, adapted to provide global signal routing connectivity within the programmable logic device via the interconnect for the corresponding programmable logic block; and a first input routing circuit, corresponding to each programmable logic block, adapted to receive signals from the first routing circuit and route to the plurality of logic block slices within the corresponding programmable logic block, wherein the first input routing circuit comprises: a first input switch stage adapted to receive signals from the first routing circuit and provide a subset of the signals for each of the logic block slices, wherein the subset of the signals is less than a number of input ports for lookup tables within the logic block slice; and a second input switch stage, corresponding to each logic block slice, adapted to receive the corresponding subset of the signals from the first input switch stage and selectively route to the corresponding logic block slice, wherein the second input switch stage is further adapted to receive a first plurality of signals directly from the first routing circuit.