Patent ID: 7679949

Claim:
A column select multiplexer circuit for a domino random access memory array, comprising: a plurality of column selector circuits for selecting a plurality of columns of static random access memory cells (SRAM cells), wherein each of said plurality of column selector circuits comprises: a bitline precharge circuit for precharging a bitline and a bitline bar of a corresponding column of static random access memory cells (SRAM cells), said bitline precharge circuit coupled to said bitline and said bitline bar; a first access n-type field effect transistor (NFET) coupled to said bitline and to a first node for accessing said bitline; a second access NFET coupled to said bitline bar and to a second node for accessing said bitline bar; a column select line coupled to said first and second access transistors that when activated selects said column of SRAM cells for reading and writing of a selected SRAM cell in said corresponding column of SRAM cells.