Patent ID: 7768311

Claim:
An output buffer circuit to suppress ringing during state transitions, said buffer circuit comprising: a first impedance control circuit generating a first control signal, said control circuit receiving a first input from an output terminal and a second input from an input data signal, the first impedance control circuit comprising a pull-up device driven by said input data signal and a pull-down device driven by said first input from said output terminal; an NMOS transistor having a drain connected to said output terminal, a source connected to a ground voltage, and a gate connected to an output of said first impedance control circuit, said NMOS transistor receiving said first control signal for adjusting an impedance of said NMOS transistor; a second impedance control circuit generating a second control signal, said second control circuit receiving a first input from said output terminal and a second input from an second input data signal; and a PMOS transistor having a drain connected to said output terminal, a source connected to a supply voltage, and a gate connected to an output of said second impedance control circuit, said PMOS transistor receiving said second control signal for adjusting an impedance of said PMOS transistor.