Patent ID: 8871585

Claim:
A manufacturing method of a semiconductor device comprising: forming a first gate insulating film in a first region and in a second region on a semiconductor substrate in an active area, wherein the first region is a forming region of an n-channel field effect transistor and the second region is a forming region of a p-channel field effect transistor; forming a first gate electrode on the first gate insulating film in the first region; forming a first gate electrode on the first gate insulating film in the second region; forming source/drain regions by introducing impurities in the semiconductor substrate at both sides of the first gate electrode in the first region and the first gate electrode in the second region; performing heat treatment of activating the impurities in the source/drain regions; forming a stress liner film applying stress on the semiconductor substrate so as to cover a whole surface of the first gate electrode in the first region and a whole surface of the first gate electrode in the second region; removing the stress liner film at an upper portion of the first gate electrode in the second region to expose the upper portion of the first gate electrode in the second region, wherein the stress liner film formed over the whole surface of the first gate electrode in the first region remains; forming a groove for forming a second gate electrode by completely removing the first gate electrode in the second region; and forming the second gate electrode in the groove.