Patent ID: 7610438

Claim:
A flash-memory cache sub-system comprising: a flash-memory array of physical blocks of flash memory identified by a physical-block address (PBA), a physical block having a plurality of pages, a page having a data sector that can be written with arbitrary data only once before requiring an erase of the physical block; wherein the data sector is block-addressable and not randomly-addressable, wherein all bytes of the data sector are accessible together as a block an not accessible as individual bytes; a first data area formed from first physical blocks of flash memory in the flash-memory array; a second data area formed from second physical blocks of flash memory in the flash-memory array; wherein each page in the first physical blocks and each page in the second physical blocks stores host data from a host in the data sector for the page, and stores a logical-sector address (LSA) from the host, the LSA from the host being a host address for the host data from the host; and toggle means, activated when host data needs to be stored into a full physical block that has no empty pages, for toggling a full first physical block to a background area by writing data sectors from the full first physical block to an external mass storage device and erasing the full first physical block, and for selecting an empty second physical block to receive the host data; the toggle means also for toggling a full second physical block to the background area by writing data sectors from the full second physical block to the external mass storage device and erasing the full second physical block, and for selecting an empty first physical block to receive the host data.