Patent ID: 7816787

Claim:
An integrated circuit device comprising: a substrate; at least one metal pad formed on the substrate; a passivation layer having an opening formed around the at least one metal pad; a multilayered under bump metallurgy structure coupled to the at least one metal pad, the under bump metallurgy structure comprising: a first PVD thin film comprising chromium and having a first thickness; a second PVD thin film comprising copper overlying the first PVD thin film and having a second thickness, the second thickness being greater than the first thickness; a plated first layer comprising copper overlying the second PVD thin film; and a plated second layer comprising nickel overlying the plated first layer; and a termination electrode coupled to the under bump metallurgy structure, the termination electrode includes tin, wherein the plated second layer prevents formation of an intermetallic compound in proximity to the plated first layer by precluding diffusion of tin from the termination electrode to the plated first layer.