Patent ID: 7407860

Claim:
A semiconductor device fabricating method for fabricating a semiconductor device including a p-transistor formed in a first region of a semiconductor substrate, and an n-transistor formed in a second region of the semiconductor substrate, comprising the steps of: forming a first gate layer structure including a gate insulation film and a gate electrode in the first region and a second gate layer structure including a gate insulation film and a gate electrode in the second region; forming a first sidewall insulation film on both side surfaces of the first gate layer structure; performing a first surface processing in which CF 4 gas and O 2 gas are electrolytically dissociated and applied, the second region covered with a resist film, to thereby deform the surface of the semiconductor substrate outer of the first sidewall insulation film in the first region to form a first deformed film thereon; performing a second surface processing in which O 2 gas is electrolytically dissociated and applied to thereby remove the resist film in the second region, and to further deform the first deformed film to form a second deformed film and to oxide the surface of the semiconductor substrate exposed in the second region to form an oxide film thereon; forming a trench in the semiconductor substrate outer of the first sidewall insulation film with the surface of the semiconductor substrate in the first region with the first gate layer structure and the first sidewall insulation film in the first region and the second gate layer structure and the oxide film in the second region as a mask; forming a compressive stress applying portion in the trench; removing the first sidewall insulation film in the first region; forming a first junction region in the first region and the second region with the first gate layer structure and the second gate layer structure as a mask; forming a second sidewall insulation film on both side surfaces of the first gate layer structure and a third sidewall insulation film on both side surfaces of the second gate layer structure; and forming a second junction region in the first region and the second region with the first gate layer structure and the second sidewall insulation film and the second gate layer structure and the third sidewall insulation film as a mask.