Patent ID: 8063432

Claim:
A semiconductor device comprising: a memory cell transistor including: a tunnel insulation film formed on a semiconductor substrate; a floating gate electrode formed on the tunnel insulation film; an inter-electrode insulation film formed on the floating gate electrode; a control gate electrode formed on the inter-electrode insulation film; and a first nitride film which is formed between the tunnel insulation film and the floating gate electrode; and a peripheral circuit transistor including: a gate insulation film formed on the semiconductor substrate; a gate electrode formed on the gate insulation film; and a pair of second nitride films which are formed between the gate insulation film and the gate electrode and which are formed near lower end portions of a pair of side surfaces of the gate electrode, which are parallel in one of a channel width direction and a channel length direction, the pair of second nitride films being spaced apart from each other, wherein the pair of second nitride films are formed near lower end portions of a pair of side surfaces of the gate electrode, which are parallel in the channel width direction, the memory cell transistor further includes a pair of first oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in a channel width direction, the first nitride film is formed between the pair of first oxide films, the peripheral circuit transistor further includes a pair of second oxide films which are formed between the gate insulation film and the gate electrode and are formed near lower end portions of a pair of side surfaces of the gate electrode, which are parallel in the channel width direction, and the second nitride film is formed between the pair of second oxide films.