Patent ID: 7951712

Claim:
A method of forming an interconnection of a semiconductor device, the method comprising: (a) forming an interlayer insulating film of a low-dielectric-constant material on a substrate; (b) forming an opening in the shape of the interconnection by etching the interlayer insulating film; (c) forming a barrier metal layer on the resultant structure of step (b); (d) filling the opening by forming a metal layer on the barrier metal layer; (e) planarizing the resultant structure of step (d) until the interlayer insulating film is exposed; and (f) forming a capping layer covering the top surfaces of the interlayer insulating film by depositing a first layer comprising a silicon compound having a nitrogen moiety on the resultant structure of step (e) and depositing a second layer comprising a silicon compound having a carbon moiety directly on the first layer, wherein the interconnection is a dual damascene interconnection formed of a via and a wiring above the via.