Patent ID: 8253613

Claim:
An apparatus, comprising: a second-order delta-sigma analog-to-digital converter (ADC), comprising: a second-order integrator adapted to second-order integrate a value at a first node, wherein the first node is coupled to an input of the ADC; a comparator coupled to an output of the second-order integrator; and a digital-to-analog converter (DAC) coupled between an output of the comparator and the first node, wherein the DAC is adapted to receive a digital output of the comparator and to generate a first charge corresponding to a first logical value or a second charge corresponding to a second logical value, wherein the DAC includes a first charge pump adapted to generate the first charge and a second charge pump adapted to generate the second charge, wherein the value at the first node is based in part on the generated charge; wherein a magnitude of first charge is at least twice a magnitude of the second charge.