Patent ID: 7039568

Claim:
A system for testing the hardware of a digital computer; said system being comprised of: a test terminal which concurrently stores and executes a hardware test program for said digital computer, a simulated operator program for said hardware test program, and a control program for said simulated operator program; said hardware test program having an input interface which receives operator signals from a manual input device, having a test interface which tests said hardware in said digital computer in response to said operator signals, and having an output interface which sends a test program image to a monitor; said simulated operator program including a series of commands that simulate operator actions by sending said operator signals to said input interface of said hardware test program, and by identifying selectable items in said test program image; and, said control program including a means for sequentially executing said commands in said simulated operator program; a means for displaying, on said monitor, each particular command that is currently being executed; a means for slowing the execution of said commands to a rate where each displayed command can be perceived by an operator; and, a means for manually stopping said simulated operator program immediately after the displayed particular command is completely executed.