Patent ID: 7372293

Claim:
An integrated circuit comprising: an input/output (I/O) circuit to receive a command; an on-die termination (ODT) pin to receive one or more ODT signals; control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command, wherein the control logic includes ODT activation logic to detect, during a first clock, an ODT activation signal on the ODT pin, and ODT value selection logic to detect, during a second clock, an ODT value selection signal on the ODT pin and to select one of a first ODT value and a second ODT value based, at least in part, on the ODT value selection signal; and a termination resistance circuit coupled with the control logic and the I/O circuit, the termination resistance circuit to dynamically provide one of a primary ODT resistance and a secondary ODT resistance for the I/O circuit.