Patent ID: 7488428

Claim:
A method for forming stacked via-holes, said method comprising: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first metal-clad laminate on the side surface having the conductive trace; forming a plurality of first metal micro-vias in a metal layer of the first metal-clad laminate; forming a second metal-clad laminate on the surface of the metal layer of the first metal-clad laminate after having formed the first metal micro-vias in such metal layer thereof; forming a plurality of second metal micro-vias in a metal layer of the second metal-clad laminate using a first laser, each second metal micro-via being located corresponding to a location of a respective first metal micro-via, a diameter of the second metal micro-via being larger than that of the first metal micro-via; and removing corresponding resin layer portions of the first and second metal-clad laminates using a second laser, in order to yield stacked via-holes.