Patent ID: 8880851

Claim:
A microprocessor, comprising: a hardware instruction translator, the hardware instruction translator comprising logic that: pre-decodes instruction bytes received by the hardware instruction translator in accordance with whether they are part of an x86 instruction set architecture (ISA) machine language program or an Advanced RISC Machines (ARM) ISA machine language program; decodes a length of each pre-decoded instruction, providing one or more indicators of which x86 ISA or ARM ISA instruction bytes are start and/or end bytes; and translates the x86 ISA instructions and ARM ISA instructions into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are encoded in a distinct manner from the manner in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded; and an execution pipeline, coupled to the hardware instruction translator, wherein the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; wherein the hardware instruction translator directly provides the microinstructions to the execution pipeline for execution to generate the results defined by the x86 ISA and ARM ISA instructions.