Patent ID: 7232731

Claim:
A method for fabricating a transistor of a semiconductor device comprising: forming an STI structure and a well region in a silicon substrate; forming a first dummy gate electrode including spacers and a first gate oxide layer on the well region; forming source and drain regions around the first dummy gate electrode by using the first dummy gate electrode and the spacers as an ion implantation mask, and performing a thermal treatment; removing the first dummy gate electrode and the first gate oxide layer; forming a second dummy gate electrode and a second gate oxide layer; forming a thin nitride layer and a PMD on the silicon substrate including the second dummy gate electrode; performing a CMP process for the thin nitride layer and the PMD until the top of the spacers is exposed; removing the second dummy gate electrode and the second gate oxide layer; forming a third gate oxide layer and polysilicon for a gate electrode; performing another CMP process until the top of the spacers is exposed; and etching the upper portion of the gate electrode, wherein forming a first dummy gate electrode including the spacers and a first gate oxide layer on the well region comprises: forming a first gate oxide layer on the silicon substrate including the well region; depositing polysilicon for first dummy gate electrode; patterning the first gate oxide layer and the polysilicon into a first dummy gate; forming a LDD structure around the first dummy gate electrode; depositing a nitride layer on the entire surface of the substrate; and forming the spacers on the lateral faces of the first dummy gate electrode by patterning the nitride layer.