Patent ID: 7033926

Claim:
A method for fabricating an interconnect arrangement, comprising: producing at least two electrically conductive interconnects in a substrate below a substrate surface by means of a first lithography and etching method, the substrate comprising a first electrically insulating material and the interconnects comprising an electrically conductive material, and the interconnects being arranged next to one another in the substrate, producing a buffer layer made from a second electrically insulating material above the substrate surface, the buffer layer comprising a buffer-layer surface which is parallel to the substrate surface, producing a cavity, which runs between the interconnects and extends from the buffer-layer surface through the buffer layer into the substrate, by means of a second lithography and etching method, the cavity, with respect to the buffer-layer surface, extending deeper into the substrate than the interconnects, producing a covering layer made from a third electrically insulating material above the buffer layer, so that the cavity is completely closed off with respect to the buffer-layer surface, and wherein the interconnect arrangement is formed from the substrate, the interconnects, the buffer layer and the covering layer, and arranging a supporting layer made from a fourth electrically insulating material above the buffer-layer surface, the fourth electrically insulating material being different from the first, second or third electrically insulating material, the third electrically insulating material being adapted for optional selective deposition only on the fourth electrically insulating material.