Patent ID: 7682892

Claim:
A method of forming a MOS transistor, comprising the steps of: providing a semiconductor substrate; forming a gate insulator; forming a gate electrode over said gate insulator; forming a source and drain by performing a first S/D implant of a first dopant type, said source and drain separated by a channel region of a second dopant type having said gate electrode and said gate insulator thereon, and implanting a second S/D implant of said first dopant into a surface portion of said source and said drain; annealing said first and second S/D implants; depositing a metal comprising interface layer on an interface region at a surface portion of said source and said drain; performing a silicide anneal to form a silicide layer and to activate said first dopant provided by said first and second S/D implants, wherein at said interface region a total chemical dopant concentration of said first dopant is at least 5×10 20 cm −3 .