Patent ID: 7341940

Claim:
A method of forming metal wirings for a semiconductor device, comprising: depositing a first etch stop layer, an inter metal dielectric layer, a second-etch stop layer, and a wiring dielectric layer on a semiconductor substrate having a predetermined structure; forming a contact hole pattern on the wiring dielectric layer; forming a contact hole by etching the wiring dielectric layer, the second etch stop layer, and the inter metal dielectric layer exposed through the contact hole pattern; forming a trench pattern on the wiring dielectric layer after removal of the contact hole pattern; forming a trench by etching the wiring dielectric layer exposed through the trench pattern; removing the exposed first and second etch stop layers after removal of the trench pattern; depositing a barrier metal layer on inner walls of the contact hole and the trench; forming grooves on the barrier metal layer through a sputtering process; depositing a metal seed layer on the barrier metal layer; depositing a metal thin layer inside the contact hole and the trench; and removing the metal thin layer, the metal seed layer, and the barrier metal layer on the wiring dielectric layer through a chemical mechanical polishing process.