Patent ID: 8559205

Claim:
A method of manufacturing a nonvolatile semiconductor memory apparatus comprising: a step for forming stripe-shaped lower-layer electrode wires on a substrate; a step for forming an interlayer insulating layer on the substrate including the lower-layer electrode wires; a step for forming contact holes in an interlayer insulating layer at locations respectively opposite to the lower-layer electrode wires; a step for embedding resistance variable layers to fill the contact holes except for portions at an upper side of the interlayer insulating layer; a step for embedding at least one layers of laminated-layer structures respectively forming non-ohmic devices to fill the portions at the upper side of the contact holes; and a step for forming, on the interlayer insulating layer, the other layers of the laminated-layer structures respectively forming the non-ohmic devices such that the other layers have a larger area than openings of the contact holes.