Patent ID: 7389405

Claim:
A method for accessing a unified memory in a micro-processing system having a microprocessor, a one level pipeline, and a two-phase clock, such that an instruction is executed in a single instruction cycle, comprising: (a) fetching a program instruction from the unified memory; (b) determining if the fetched program instruction would require three unified memory accesses during a single instruction cycle for proper execution of the fetched program instruction, proper execution of the fetched program instruction being the microprocessor performing operations requested by the fetched program instruction in a single instruction cycle; (c) accessing the unified memory a first time, during the instruction cycle associated with the fetched program instruction, with a dummy access when it is determined that the fetched program instruction requires three unified memory accesses for proper execution of the fetched program instruction; (d) fetching a next program instruction from an instruction register, during the instruction cycle associated with the fetched program instruction from the unified memory, when it is determined that the fetched program instruction requires three unified memory accesses for proper execution of the fetched program instruction; and (e) accessing the unified memory a second time, during the instruction cycle associated with the fetched program instruction from the first access of the unified memory, with a data access when it is determined that the fetched program instruction from the first access of the unified memory requires three unified memory accesses for proper execution of the fetched program instruction from the first access of the unified memory.