Patent ID: 8877591

Claim:
A method of manufacturing a vertical structure nonvolatile memory device, comprising: forming a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked on a substrate; forming a channel hole exposing the substrate by etching the plurality of interlayer insulating layers and the plurality of sacrificial layers; forming a channel layer on a sidewall of the channel hole; forming an opening exposing the substrate by etching the plurality of interlayer insulating layers and the plurality of sacrificial layers, the opening being spaced apart from the channel hole; removing the plurality of sacrificial layers through the opening to form a plurality of trenches between two adjacent ones of the plurality of interlayer insulating layers, the plurality of trenches exposing the channel layer; forming a gate insulating layer on inner surfaces of the plurality of trenches; and forming a plurality of gate electrodes on the gate insulating layer in respective ones of the plurality of trenches, a sidewall of one of the plurality of gate electrodes comprising a recess facing the channel layer.