Patent ID: 6961793

Claim:
A bus arbiter for a plurality of masters which issue bus access requests, said bus arbiter comprising: an arbitration priority control section for outputting basic priority data for each of the plurality of masters; a plurality of arbitration priority generating sections, each arbitration priority generating section corresponding with one of the plurality of masters, for combining the basic priority data for said corresponding master with request indication data indicating existence or non-existence of a bus access request from said corresponding master, to generate arbitration priority data; an arbitration priority comparing section for comparing a plurality of the arbitration priority data for the plurality of masters with each other to determine the one of the plurality of arbitration priority data which has the highest priority, and for outputting a comparison resultant signal containing data specifying the one of the plurality of masters corresponding to the arbitration priority data with the highest priority; and an arbitration result notifying section for outputting a bus use permission signal to the master corresponding to arbitration priority data with the highest priority in response to the comparison resultant signal.