Patent ID: 8351244

Claim:
A memory cell array comprising: a semiconductor substrate; first conductive layers arranged to extend in parallel to each other on said semiconductor substrate; an interlayer insulating film formed to cover said first conductive layers; second conductive layers arranged above said interlayer insulating film to extend in parallel to each other and to three-dimensionally cross with said first conductive layers; plugs each formed to penetrate through said interlayer insulating film and to have a lower surface electrically connected to a corresponding one of said first conductive layers at a corresponding one of three-dimensional cross points between said first conductive layers and said second conductive layers; and memory cells each formed between, and electrically connected to, an upper surface of a corresponding one of said plugs and a corresponding one of said second conductive layers, at the corresponding one of three-dimensional cross points between said first conductive layers and said second conductive layers, wherein each of said memory cells includes: a current steering element formed to cover said upper surface of the corresponding one of said plugs, said current steering element having a nonlinear current-voltage characteristic, and a variable resistance element which is electrically connected in series to said current steering element and has a resistance value that reversibly changes in response to an application of a voltage pulse, said upper surface of each of said plugs is formed to have a first concave shape, said current steering element includes: a first electrode that covers said upper surface of the corresponding one of said plugs; a current steering layer formed on said first electrode; and a second electrode formed on said current steering layer, and said first electrode is thicker above a center portion than above a peripheral portion of said upper surface of the corresponding one of said plugs, by a maximum of a depth of the first concave shape.