Patent ID: 7932584

Claim:
A device, comprising: a first chip positioned on a first level; and a second chip and a third chip positioned on a second level; wherein the second chip has a first through-chip via and is coupled to the first chip through the first through-chip via; wherein at least a portion of the second chip and at least a portion of the third chip overlap the first chip; and wherein the first through-chip via includes: a first annulus of insulating material; a first annulus of a first electrically-conductive material bounding an outer surface of the first annulus of insulating material; a second annulus of a second electrically-conductive material bounding an inner surface of the first annulus of insulating material; a second annulus of insulating material within the second annulus of a second electrically-conductive material; and a third electrically-conductive material within the second annulus of insulating material.