Patent ID: 6980048

Claim:
A voltage generating circuit for generating a stable internal voltage irrespective of a variation in external voltage, the voltage generating circuit comprising: a voltage comparing circuit operating in response to an activation signal and for outputting an output voltage to a control node in response to a difference between a reference voltage and an internal voltage; an internal voltage control circuit connected to the control node, the internal voltage control circuit receiving the external voltage and controlling a level of the internal voltage, which is applied to a load, in response to a voltage level at the control node; and a clamp circuit for adjusting an amount of driving current flowing through the internal voltage control circuit by maintaining control of the voltage level at the control node below a voltage threshold, wherein the clamp circuit comprises: a first clamp PMOS transistor having a source connected to the external voltage and a gate connected to the activation signal; and a first clamp NMOS transistor having a source connected to a drain of the first clamp PMOS transistor, a gate connected to the activation signal, and a source connected to the control node.