Patent ID: 8694975

Claim:
A programming system implemented on a computer including a processor and a memory, the programming system comprising: a first compiler that generates one or more object codes from a program code for a first processor included in an arithmetic processing system to which a plurality of processors are mutually connected; a first linker that links the one or more object codes generated by the first compiler to generate an execution file for the first processor; a parameter information generation unit that generates, based on the information acquired from the first linker, parameter information as a header file to be used in combination with a program code of a second processor included in the arithmetic processing system; a second compiler that generates one or more object codes from the program code and the header file for the second processor; and a second linker that links the one or more object codes generated by the second compiler to generate an execution file for the second processor, wherein the parameter information is related to at least one of addresses of functions and of data which are commonly used by the first and second processors when the first and second processors execute respective execution files, and wherein connection between the plurality of processors in the arithmetic processing system conforms to memory mapped I/O system, and the parameter information generation unit generates, as the parameter information, a header file defining parameters that have possibility to be accessed from the second processor and from the first processor based on address information in which functions acquired from the first linker are mapped and information of address maps of registers and data memories of the first processor.