Patent ID: 7101748

Claim:
A method of forming a shallow source/drain region of an N channel, metal oxide semiconductor (NMOS) device on a second portion of a semiconductor substrate after other type devices are formed on a first portion of said semiconductor substrate, comprising the steps of: forming an N well region in a second region, and in a third region of said first portion of said semiconductor substrate; forming an electro-static discharge (ESD) device in a first region of said first portion of said semiconductor substrate; forming an input/output device in said second region of said first portion of said semiconductor substrate; forming a gate insulator layer on said third region of said first portion of said semiconductor substrate, and on said second portion of said semiconductor substrate; forming conductive gate structures on said gate insulator layer; forming insulator spacers on sides of said conductive gate structures; performing a first ion implantation procedure to form P type source/drain regions in area of said third region of said first portion of said semiconductor substrate not covered by a conductive gate structure or by insulator sidewall spacers, resulting in formation of a P channel, metal oxide semiconductor (PMOS) device in said third region of said first portion of said semiconductor substrate; forming a photoresist shape on said first portion of said semiconductor substrate, with an opening in said photoresist shape exposing said second portion of said semiconductor substrate; performing a second ion implantation procedure to form an N type, shallow source/drain region in a region of said second portion of said semiconductor substrate not covered by a conductive gate structure or by insulator spacers; performing a plasma procedure to remove said photoresist shape: and performing a wet clean procedure.