Patent ID: 7706190

Claim:
A method of operating a non-volatile memory device, the method comprising: performing a program operation on memory cells, wherein the program operation employs a first program voltage; performing a first program verify operation, employing a first verify voltage, by using a third latch according to a data state of a first latch of a page buffer coupled to the memory cells; performing a second program verify operation, employing a second verify voltage, by using a second latch of the page buffer according to a data state of the first latch, wherein the second verify voltage is higher than the first verify voltage; sequentially performing a third program verify operation, employing a third verify voltage higher than the second verify voltage, and a fourth program verify operation, employing a fourth verify voltage higher than the third verify voltage, wherein the third program verify operation and the fourth program verify operation are performed using the second latch according to a data state of the third latch of the page buffer; resetting the second latch by employing the fourth verify voltage; and performing a fifth program verify operation, employing a fifth verify voltage higher than the fourth verify voltage, wherein the fifth program verify operation is performed using the second latch according to a data state of the third latch.