Patent ID: 7208969

Claim:
A method for testing a plurality of devices in parallel, comprising: a) allocating n test sites; b) in a given test operation, allocating m connection sites, such that n<m and associating m devices of a tested object to the m connection sites; c) in said given test operation, using gathered statistics of historical testing including at least one previous wafer sort operation for identifying at least one failed device from among said m devices; d) in said given test operation, applying simultaneously a testing scheme to at most n devices from among the m devices; the up to n devices constitute tested devices and do not include any of said at least one failed device; e) in said given test operation repeatedly performing the following until all said m devices are handled: i. in response to termination of testing of a device, selecting for test at least one untested device from among the m devices by allocating thereto a respective vacant test site; said untested device is not any of said at least one failed device and is selected using a criterion for reducing the overall testing time of the m devices compared to overall time it would take to test the m devices using up to n connection sites.