Patent ID: 7404067

Claim:
A system comprising: an instruction memory to store instructions for a first thread and to store instructions for a second thread; a processor coupled to the memory, wherein the processor concurrently executes at least portions of the first and second thread, wherein the first thread executes a postfix region of the instructions to be executed by the second thread, the processor including: a storage unit to hold one or more validity indicators, where each validity indicator is associated with an architectural register defined for the processor; rename unit to generate a validity indicator value for each of one or more of the architectural registers, wherein the one or more of the architectural registers is indicated as a destination register by the current instruction; execution unit to filter the current instruction for execution based on the value of the one or more validity indicators, wherein the execution unit further determines whether the current instruction should be executed through an execution pipeline stage, based on the value of the one or more validity indicators; a thread progress beacon table to store progress information regarding the first thread; and a logic unit determining, based on the progress information, whether the first thread should be killed, said logic unit further determining whether the first thread is lagging behind the concurrent second thread, and terminating the lagging first thread.