Patent ID: 7557663

Claim:
A digital phase locked loop (DPLL) comprising: a.) a digitally implemented voltage controlled oscillator (VCO) used to output a VCO feedback signal of a given frequency; b) a phase error counter used to receive an input voltage signal from an alternating current (AC) source input, the AC input voltage signal having an input frequency, phase and period, the phase error counter including: i. a digital phase-frequency detector connected to the AC source input and used to compare the phase of the AC input voltage signal and the VCO feedback signal at an initial lock-in process and to output a first phase error signal, ii. a quadrature phase detector connected to the AC source input and used to compare the phase of the AC input voltage signal and the VCO feedback signal and to output a second phase error signal, the phase error counter further used to compare the input voltage signal frequency to the VCO feedback signal frequency and to output a combined phase error signal formed from the first phase error signal and the second phase error signal; and c. two programmable dividers, each divider used to receive the combined phase error signal, both dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with the input signal; whereby the DPLL is used for synchronizing devices connected to the AC source.