Patent ID: 7274227

Claim:
A power-on reset circuit to generate a reset signal when a power is initially turned on, the power-on reset circuit comprising: an adjusting circuit receiving and adjusting a clock signal to output a control signal, wherein a lowest level of the control signal is higher than a pre-defined level; a charging/discharging unit having a capacitor apparatus, the charging/discharging unit being coupled to the adjusting circuit to receive the control signal and determine whether to charge or discharge the capacitor apparatus based on the control signal so as to output a storage voltage of the capacitor apparatus; an output circuit coupled to the charging/discharging unit to receive the storage voltage and output the reset signal, wherein the output circuit enables or disables the reset signal according to whether the storage voltage reaches a critical voltage of the output circuit; a control switch having a first terminal, a second terminal, and a control terminal, the control switch determines whether to transmit the clock signal received by the first terminal to the second terminal, and to output the clock signal to the adjusting circuit according to the reset signal received by the control terminal; and wherein the adjusting circuit determines a duty cycle of the charging/discharging unit by adjusting a waveform and the lowest level of the control signal.