Patent ID: 7007213

Claim:
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly during self-test, where N>1, each clock domain having one or more capture clocks and one or more scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode; said method comprising the steps of: (a) generating and loading N pseudorandum stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly, by applying said shift clock pulses to all said scan cells in said scan mode for loading or shifting-in said N pseudorandom stimuli to all said scan cells, during a shift operation; (b) applying an ordered sequence of capture clock pulses to all said scan cells within said N clock domains in said normal mode during a capture operation, the ordered sequence of capture clock pulses comprising at least two capture clock pulses from two or more selected capture clocks, for controlling two or more clock domains, in a sequential order, wherein each said selected capture clock must contain at least one said capture clock pulse, and when detecting or locating selected delay faults within a clock domain, said selected capture clock controlling the clock domain contains at least two consecutive said capture clock pulses to launch the transition and capture the output response; and (c) compacting N output responses of all said scan cells to signatures, by applying said shift clock pulses to all said scan cells in said scan mode for compacting or shifting-out said N output responses to form said signatures, during a compact operation.