Patent ID: 7646644

Claim:
A memory device comprising: a plurality of groups of memory cells organized in rows and columns; a first addressing circuit for addressing said memory cells of said groups on the basis of a cell address; a plurality of sets of reference cells associated with respective sets of said memory cells, each set of reference cells including a plurality of reference cells, wherein in each set of reference cells, a read reference cell and a program verify reference cell are connected to a same first reference wordline, and an erase verify reference cell and a depletion verify reference cell are connected to a same second reference wordline, and wherein said read reference cell, said program-verify reference cell, said erase-verify reference cell, and said depletion verify reference cell are connected to respective separate bitlines; and a second addressing circuit for addressing one of said reference cells through at least one reference wordline and respective bitlines during read and verify operations of addressed memory cells, wherein said second addressing circuit comprises an addressing stage for selecting one of said reference wordlines, and a reference-selection circuit for selecting one of said reference bitlines.