Patent ID: 7761633

Claim:
An addressable serial peripheral interface bus arrangement comprising: a master; a plurality of slaves, each of said slaves having associated therewith a particular slave address; a first and a second communication link connecting said master to each of said plurality of slaves, said first communication link different than said second communication link, each of said communication links constituted of a single wire link connected to a single port of said master and in parallel to each of said plurality of slaves; a clock, associated with said master and connected to each of said plurality of slaves, operative to clock data transmitted via said first communication link out of said master and into each of said plurality of slaves; and an enable control line, responsive to said master, and connected to each of said plurality of slaves in parallel, wherein said master is operative to transmit via said first communication link, responsive to said enable control line exhibiting an active signal, a target address, and wherein each of said plurality of slaves is operative to: receive, from said master, via said first communication link said target address; compare said received target address with said associated particular slave address; and transmit, only in the event said received target address is consonant with said associated particular slave address, first data via said second communication link responsive to said enable control line exhibiting said active signal and responsive to said clock, said transmitting slave being denoted the responding slave.