Patent ID: 6851078

Claim:
A memory device testing apparatus for testing a memory device, comprising: a pattern generator which generates a control signal for controlling said memory device, an address signal for accessing said memory device, and a test data signal for representing test data to be written on said memory device; a memory device plug-in unit which enables test data to be written on said memory device and said test data to be read from said memory device by having said memory device plugged in and supplying said control signal and said address signal generated by said pattern generator to said memory device; a comparison device which compares expectation value data equal to said test data supplied to said memory device to be written on said memory device with said test data that has been read after being written on said memory device, and outputs a fail signal that indicates content of a defect when said memory device has a defective spot; a failure analysis memory unit having a data storage memory that is divided into at least two sub address spaces including an address that corresponds to an address of said defective spot of said memory device onto which said fail signal output from said comparison device is written, and a compact memory which stores failure information that indicates existence of said defective spot in said sub address space; and a memory failure remedy analysis unit to which said fail signal written on said data storage memory is transferred, wherein, based on said failure information stored in said compact memory, said fail signal written on said sub address space in which said defective spot exists is transferred to said memory failure remedy analysis unit.