Patent ID: 7711902

Claim:
A memory system comprising: a level 1 (L1) cache including L1 tag memory and L1 data memory; a level 2 (L2) cache coupled to the L1 cache, the L2 cache including L2 tag memory having X L2 tag entries and a L2 data memory having Y L2 data entries; and a memory controller coupled to the L1 and L2 caches and configured to (a) determine, in response to receiving a tag and associated data, if L2 tag entries associated with L2 data entries are unavailable, (b) determine if a first tag in a first L2 tag entry, associated with a first data in a first L2 data entry, has a corresponding more recent data or a duplicate value of the first data in the L1 data memory, and (c) move the first tag to a second L2 tag entry that is not associated with a L2 data entry, vacate the first L2 tag entry and the first L2 data entry and store the received tag in the first L2 tag entry and the received data in the first L2 data entry; wherein X is greater than Y.