Patent ID: 7181638

Claim:
An adjustable logic circuit comprising: a pulse filter and delay circuit operative to read an adjustable configuration value and to provide a delayed filtered clock signal of an internal clock, the pulse filter and delay circuit selecting either the internal clock or a complement of the internal clock in response to the adjustable configuration value and delaying a selected signal by a predetermined amount to provide the delayed filter clock signal; a state machine and combinational logic circuit, operative to provide a data select signal to select a data value from any or a plurality of stored data values to provide a data signal based upon a current state of the state machine and combinational logic circuit in response to the delayed filtered clock signal, the state machine and combinational logic circuit providing a state transition signal; and a data strobe generation circuit operative to provide a data strobe signal in response to the state transition signal, the data strobe signal indicating when both the data signal is valid and delay of the delayed filter clock signal is compatible with a predetermined component, the internal clock having a substantially same frequency as an interface frequency with the predetermined component.