Patent ID: 7435643

Claim:
A method for fabricating a DRAM array, comprising: patterning a semiconductor substrate to form rows and columns of pillars thereon; forming a capacitor on a lower portion of a sidewall of each pillar, comprising: forming a first plate in the lower portion of the sidewall of each pillar; forming a first dielectric layer at periphery of each first plate; forming a second plate as an upper electrode at periphery of each first dielectric layer; forming a second dielectric layer at periphery of each second plate; and forming a third plate at periphery of each second dielectric layer, wherein the third plate is electrically connected with a corresponding first plate to form a lower electrode; forming a vertical transistor on an upper portion of a sidewall of each pillar, the vertical transistor being coupled with a corresponding capacitor; and forming a plurality of bit lines over the substrate, wherein each bit line is coupled with one row of vertical transistors.