Patent ID: 7100065

Claim:
A controller arrangement for effectuating data transfer between a core clock domain and a bus clock domain, wherein said core clock domain is operable with a core clock signal and said bus clock domain is operable with a bus clock signal, said core and bus clock signals having a ratio, comprising: a bus clock synchronizer controller portion operating to generate a set of clock relationship control signals, wherein at least a portion of said clock relationship control signals are used in generating a set of bus domain synchronizer control signals towards a bus-to-core synchronizer and a core-to-bus synchronizer; and a core clock synchronizer controller portion operating to generate a set of core domain synchronizer control signals towards said bus-to-core synchronizer and said core-to-bus synchronizer, said core clock synchronizer controller portion operating responsive to said clock relationship control signals provided by said bus clock synchronizer controller portion and configuration information indicative of different skew tolerances and latency values associated with at least one of said bus clock and core clock signals.