Patent ID: 7281092

Claim:
A processing unit comprising: at least two processing cores; a memory hierarchy having a plurality of caches coupled to said at least two processing cores and characterized by slower response times at successively lower levels of said memory hierarchy; and a cache controller coupled to said plurality of caches, in response to selecting a data block for eviction from a source cache of said plurality of caches at a first level of said memory hierarchy, for examining a data structure to determine whether an entry exists that indicates that said data block has been evicted from any of said plurality of caches at said first level of said memory hierarchy to a slower level of said memory hierarchy and subsequently retrieved from said slower level of said memory hierarchy into any of said plurality of caches at said first level of said memory hierarchy, and in response to determining said entry exists in said data structure, for selecting another of said plurality of caches at said first level of said memory hierarchy to receive said data block from said source cache upon eviction.