Patent ID: 8154902

Claim:
An integrated circuit comprising: a plurality of bit lines; a plurality of word lines; a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell in the memory array is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines, and (ii) a corresponding word line of the plurality of word lines; and a bit line decoder in communication with the plurality of bit lines; and a word line decoder in communication with the plurality of word lines, wherein during sensing of a state of a given memory cell of the plurality of memory cells, the word line decoder is configured to activate only the word line corresponding to the given memory cell, and the bit line decoder is configured to precharge a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and precharge a second bit line of the two corresponding bit lines to which the given memory cell is coupled to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.