Patent ID: 7404169

Claim:
Clock distribution circuitry for a structured ASIC comprising: a deterministic portion that distributes a clock signal to any of a plurality of predetermined locations that are spaced from one another on the structured ASIC; a plurality of configurable portions, each of which is associated with a respective one of the predetermined locations for distributing a clock signal received from the deterministic portion at the associated predetermined location to clock utilization circuitry at any of various locations within a predetermined area adjacent to the associated predetermined location, wherein each of the predetermined areas includes a plurality of predetermined subareas, each of which includes clock utilization circuitry at any of a plurality of locations within the subarea, and wherein each configurable portion associated with an area that includes at least one subarea having clock utilization circuitry comprises: a configurable subportion associated with each of the subareas that includes clock utilization circuitry, comprising: a subportion buffer circuit; a configurable conductor from the predetermined location associated with that configurable portion to each subportion buffer circuit that is part of that configurable portion; a configurable subportion conductor from the subportion buffer circuit to each clock utilization circuitry in the subarea associated with that configurable subportion; and a two-dimensional array of logic elements, wherein circuitry of the logic elements is operable to provide the subportion buffer circuits and logic functions in response to being released from providing the subportion buffer circuits.