Patent ID: 8732493

Claim:
A semiconductor integrated circuit that sequentially performs predetermined processing on data input successively, comprising: a host CPU; a data engine that executes the predetermined processing; and a plurality of sequencers, wherein the host CPU, the data engine and the plurality of sequencers are connected in a hierarchical manner with the host CPU at top and the data engine at bottom, each of the plurality of sequencers includes a memory that stores a parameter for execution of the sequencer, a memory controller, a loop counter, a sequence controller, and an interface unit that handles transmission and reception of signals with an external unit of the sequencer, the data engine includes a memory that stores a parameter for execution of the data engine, and an interface unit that handles transmission and reception of signals with an external unit of the data engine, the host CPU includes an interface unit that handles transmission and reception of signals with an external unit of the host CPU, the interface units of the plurality of sequencers have the same specifications, each interface unit including a first master interface unit for accessing a memory in an external functional block of the sequencer, a second master interface unit for controlling execution of an external functional block of the sequencer, a first slave interface unit for allowing access to the memory of the sequencer by an external functional block of the sequencer, and a second slave interface unit for allowing control of execution of the sequencer by an external functional block of the sequencer, the interface unit of the host CPU includes a first master interface unit and a second master interface unit respectively having the same specifications as the first master interface unit and the second master interface unit of the plurality of sequencers, the interface unit of the data engine includes a first slave interface unit and a second slave interface unit respectively having the same specifications as the first slave interface unit and the second slave interface unit of the plurality of sequencers, and the host CPU, the plurality of sequencers and the data engine are connected in such a way that a higher level accesses a memory of one or a plurality of lower levels through the first master interface unit of the higher level and the first slave interface unit of the one or the plurality of lower levels, and a higher level controls execution of an immediately lower level through the second master interface unit of the higher level and the second slave interface unit of the immediately lower level.