Patent ID: 6960942

Claim:
A high speed phase selector comprising: a first circuit configured to receive a plurality of clock signals having different phases, and to frequency divide the plurality of clock signals by N, and to multiply the number of phases by N, and to output the resulting clock signals; and a second circuit configured to receive clock signals front the first circuit and to receive a first phase selection signal, to output a first clock signal having a phase corresponding to the first phase selection signal, to switch from the first clock signal to a second clock signal when a second phase selection signal is received, to prevent glitches during the transition, the second circuit synchronizing the transitions of the first and second phase selection signals to the falling edge of their corresponding clock signals, the second circuit engaging the second clock signal when selected and disengaging the first clock signal after the second clock is engaged, wherein the first circuit comprises a plurality of registers, the registers being serially coupled, each register being configured to output a different phase.