Patent ID: 7082160

Claim:
A pulse width control system comprising: a serial transmission line for receiving serial data signals; a differential pair having a first transistor and a second transistor, the first and second transistors being connected to the transmission line for respectively producing a positive data signal and a negative data signal, the first transistor being controlled by a first control signal and the second transistor being controlled by a second control signal, a differential data signal being produced by subtracting the negative data signal from the positive data signal; a first delay control cell connected to the first transistor for delaying the first control signal; a second delay control cell connected to the second transistor for delaying the second control signal; wherein delay times caused by the first and second delay control cells to delay the first and second control signals are adjusted to ensure that all data pulses of the differential data signal have uniform width, when a status of the serial transmission line remains in a transmit mode, the first and second delay control cells generate a first delay time, and when a status of the serial transmission line switches from an idle mode to the transmit mode, the first and second delay control cells generate a second delay time, the first and second delay times being unequal.