Patent ID: 7329951

Claim:
A structure, comprising: (a) a dielectric layer including a dielectric layer top surface that defines a reference direction essentially perpendicular to the dielectric layer top surface; (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the trench (i) physically surrounds a support/interface region of the patterned support/interface layer and (ii) physically isolates the support/interface region from a remainder of the patterned support/interface layer, wherein the hole is directly above the electrically conducting bond pad, wherein the patterned support/interface layer comprises a support/interface material, wherein the trench is not filled with the support/interface material, and wherein the trench is sandwiched between a first region and a second region of the patterned support/interface layer, the first and second regions residing on a same semiconductor integrated circuit (chip); and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad, wherein the patterned support/interface layer has a thickness in the reference direction in a range of 40-50 μm.