Patent ID: 8654582

Claim:
A semiconductor device comprising: a first wiring, a second wiring extending across the first wiring, a third wiring, a fourth wiring, and a fifth wiring; a memory cell comprising a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and a capacitor; a first driver circuit electrically connected to the first wiring; a second driver circuit electrically connected to the second wiring and the third wiring; a third driver circuit electrically connected to the fourth wiring; and a fourth driver circuit electrically connected to the fifth wiring, wherein: the second transistor comprises an oxide semiconductor layer comprising a channel formation region, the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, the second wiring is electrically connected to one of the first source electrode and the first drain electrode, the first wiring is electrically connected to the other of the first source electrode and the second drain electrode, the fourth wiring is electrically connected to the other of the second source electrode and the second drain electrode, the fifth wiring is electrically connected to the second gate electrode, the third wiring is electrically connected to the other of the electrodes of the capacitor, and the memory cell is provided between the first driver circuit and the third driver circuit, and between the second driver circuit and the fourth driver circuit.