Patent ID: 7917785

Claim:
A method of optimizing performance of a multi-core chip having a plurality of cores, said method comprising the steps of: determining a V dd -frequency SCHMOO characteristic for each of said plurality of cores individually; saving data indicative of said Vdd-frequency SCHMOO characteristics for each of said plurality of cores; configuring said cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on said saved data; saving said configuration such that it may be updated and used on at least one of a periodic and a continual basis; setting a given one of said cores to an extrema of frequency offset from adjacent cores; detecting an interconnect error associated with an interconnection between said given one of said cores and said adjacent cores; and setting said given one of said cores to a reduced frequency offset and repeating said detecting until no errors are noted.