Patent ID: 8896289

Claim:
A circuit, comprising: an input stage having a first input node, a first output node, and a second output node, the input stage being configured to: generate a first reference signal at the first output node of the input stage; and generate a second reference signal at the second output node of the input stage; a comparison stage having a first input node, a second input node, a first output node, and a second output node, the first input node of the comparison stage being coupled to the first output node of the input stage, and the second input node of the comparison stage being coupled to the second output node of the input stage, the comparison stage being configured to: generate a first comparison output signal at the first output node of the comparison stage in response to the first reference signal and a third reference signal; and generate a second comparison output signal at the second output node of the comparison stage in response to the second reference signal and a fourth reference signal; and a calibration stage coupled to the comparison stage and configured to generate a detection signal responsive to the presence of the first comparison output signal being an alternating current (AC) signal having a signal frequency within a predetermined frequency band; and the second comparison output signal being an AC signal having a signal frequency within the predetermined frequency band.