Patent ID: 8735291

Claim:
A method of patterning a gate stack on a substrate, comprising: preparing a gate stack on a substrate, said gate stack including a high-k layer and a gate layer formed on said high-k layer; transferring a pattern formed in said gate layer to said high-k layer using a pulsed bias plasma etching process, said pulsed bias plasma etching process comprising: coupling a first radio frequency (RF) power to an upper electrode to provide a source power for sustaining a plasma, continuously supplying said first RF power to sustain said forming plasma using a process gas composition including a halogen-containing gas and a polymerizing gas, said polymerizing gas containing a hydrocarbon, electrically biasing a substrate holder that supports said substrate with a second radio frequency (RF) power, and pulsing said second RF power for said electrical biasing; and selecting a process condition for said pulsed bias plasma etching process to achieve a silicon recess formed in said substrate having a depth less than 2 nanometer (nm).