Patent ID: 8819350

Claim:
A memory system comprising: a plurality of storage groups, each of which includes a first storing unit that is nonvolatile and includes a plurality of blocks as a unit of data erasing, a second storing unit as a buffer memory of the first storing unit, a first control circuit that controls driving of the first storing unit, and a second control circuit that controls driving of the second storing unit, the storage groups being capable of data transfer between the first storing unit and the second storing unit in each of the storage groups; an interface that is connected to a host device; and a plurality of MPUs that is bus-connected to the interface and the first control circuit and the second control circuit of each of the storage groups, and controls the first control circuit and the second control circuit of each of the storage groups, wherein a first MPU among the MPUs performs data transfer between the host device and the first storing unit of a first storage group among the storage groups via the second storing unit of the first storage group, and a second MPU among the MPUs performs maintenance control of the first storing unit of a second storage group among the storage groups when the second MPU detects a transfer instruction notification from the first MPU to the host device.