Patent ID: 8104719

Claim:
A digital interface unit (DIU) configured to be disposed on a final stage of a multi-stage missile, the DIU comprising: a gate array having plural ports, interfaces and interface logic circuits for interconnecting and disconnecting multiple processors; a first processor coupled to the gate array; and a second processor coupled to the first processor via the gate array, wherein the DIU is configured to perform guidance and navigation functions for each of the stages of the multi-stage missile and control functions for only some of the stages through a serial bus interface that provides a daisy-chain interconnection between the stages, wherein at least one of the processors is a guidance processor that is configured with stage-control instructions to perform the guidance and navigation functions of the stages, wherein the gate array is a field programmable gate array (FPGA) to configure the guidance processor with the stage-control instructions for a currently-controlled stage, wherein the guidance processor is configured to execute stage-control instructions for the currently-controlled stage prior to separation of the currently-controlled stage, wherein the DIU is configured to order stage separation and provide a stage-gone signal to the guidance processor, and wherein the stage-control instructions are configured to check for the presence of the stage-gone signal and cause the FPGA to configure the guidance processor with stage-control instructions for controlling a next stage in response thereto.