Patent ID: 8259499

Claim:
A memory apparatus, comprising: a plurality of memory cells; a plurality of word lines accessing the plurality of memory cells, the plurality of word lines divided into a plurality of erase groups, wherein responsive to an erase command an erase group is selected from the plurality of erase groups to receive an erase bias arrangement, wherein the erase group includes: at least a first outer selected word line bounding (i) the erase group of word lines selected to receive the erase bias arrangement, from (ii) unselected word lines outside the erase group, wherein the first outer selected word line neighbors a first unselected word line outside the erase group; a first plurality of multilevel contacts between (i) the first outer selected word line and (ii) the first unselected word line neighboring the first outer selected word line, and control circuitry responsive to the erase command by selecting the erase group from the plurality of erase groups to receive the erase bias arrangement, and applying the erase bias arrangement to the erase group.