Patent ID: 8860759

Claim:
An arrangement for video processing, comprising: a real time capture module that captures video signals, and a composite video module that produces primary video signals; a redisplay module connected to said composite video module and said real time capture module and comprising a memory access sequencer; and a memory component; said redisplay module being configured to: concatenate active video samples from the video signals captured by said real time capture module into a largest length that said memory component can accept in a single write, load the concatenated active video samples having the largest length into an input write register of said memory access sequencer, said memory access sequencer being configured to synchronize the concatenated active video samples and write the concatenated active video samples to said memory component such that concatenated active video samples are stored in said memory component in an order in which they would be redisplayed on a video monitor, read the stored concatenated active video samples from said memory component via said memory access sequencer and transfer data representing the stored concatenated active video samples to active video line buffers, read data simultaneously from said active video line buffers and perform line averaging to achieve a same number of active lines as a redisplay format, and output the line averaged video data to said composite video module.