Patent ID: 7488979

Claim:
An array substrate structure for a liquid crystal display device, comprising: first, second and third gate electrodes on a substrate having a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion, the first gate electrode disposed in the pixel TFT portion, the second gate electrode disposed in the n-type driving TFT portion, the third gate electrode disposed in the p-type driving TFT portion; a gate line in the display area on the substrate; a pixel electrode in the pixel electrode area on the substrate; a gate insulating layer on the first, second, and third gate electrodes, the gate line, and the pixel electrode; first, second and third semiconductor layers of polycrystalline silicon on the gate insulating layer, the first semiconductor layer disposed in the pixel TFT portion, the second semiconductor layer disposed in the n-type driving TFT portion, and the third semiconductor layer disposed in the p-type driving TFT portion; a passivation pattern on the first, second and third semiconductor layers, the passivation pattern exposing side portions of each of the first, second and third semiconductor layers; first source and drain electrodes, second source and drain electrodes, and third source and drain electrodes on the substrate, the first source and drain electrodes contacting the side portions of the first semiconductor layer, the second source and drain electrodes contacting the side portions of the second semiconductor layer, the third source and drain electrodes contacting the side portions of the third semiconductor layer; and a data line crossing the gate line and connected to the first source electrode.