Patent ID: 8134233

Claim:
Electrically isolated, closely spaced circuit sub-entities for use on a printed wiring board, comprising: a polymeric substrate selected from the group consisting of polyesters, polyimides, polyamides, polyamide-imides, polyetherimides, polyacrylates, polyethylene, polypropylene, epoxies, polyvinylidene chloride, polysiloxanes, polycarbonates, fabrics, and paper, having a layer of metal adhered to a major surface thereof; the layer of metal patterned into at least one entity; the entity having one or more fracture initiating features formed therein; one or more stress fractures in the entity, the stress fractures extending away from the fracture initiating features into an interior portion of the entity, so as to form two or more sub-entities from the entity, each sub-entity electrically isolated from an adjacent sub-entity by means of the stress fracture; and a fracture guiding feature formed in a major surface of the entity, for guiding the stress fracture in a predetermined direction.