Patent ID: 6989230

Claim:
A process for producing a patterned low k inter-layer dielectric (ILD, layer in an interconnect structure on a semiconductor body, comprising: a) providing a first ILD (inter-layer dielectric, structure comprising a metal line embedded therein; b) depositing an antireflective (ARC) etch stop layer over said first ILD and said embedded metal line; c) depositing a Si-containing resist coating or layer on the ARC layer; d) using photolithography to pattern an aperture in said Si-containing resist coating; e) affecting silylation of said Si-containing resist coating to obtain a patterned Si-rich layer by increasing Si content in the resist coating subsequent to said step of using photolithography; and f) oxidizing the patterned Si-rich film to convert said patterned Si-rich film layer to a patterned low k oxide porous second ILD layer for providing electrical isolation of active elements and/or interconnected signal paths.