Patent ID: 8625326

Claim:
A semiconductor memory device, comprising: a memory cell array having memory cells disposed at intersections of a plurality of first lines and a plurality of second lines respectively, each of the memory cells including a variable resistor; and a control circuit configured to execute a read operation by applying a certain voltage to selected one of the memory cells disposed at the intersection of selected one of the first lines and selected one of the second lines and detecting a current flowing in the selected one of the first lines, thereby determining a resistance state of the variable resistor in the selected one of the memory cells, the read operation being an operation configured to execute a sensing operation multiple times and aggregate determination results thereof, the sensing operation being configured such that a first voltage is applied to a plurality of selected ones of the first lines and a second voltage lower than the first voltage is applied to a single selected one of the second lines, the control circuit being configured to suspend application of the first voltage to the first line connected to the selected one of the memory cells determined to be in a first resistance state in one of the sensing operations, and execute the next sensing operation, the control circuit further comprising a first resistance adjusting circuit including a dummy word line, the first resistance adjusting circuit being configured to set a resistance value that differs depending on a position of the selected one of the memory cells in the memory cell array, and the control circuit applying the second voltage to the selected one of the second lines via the first resistance adjusting circuit.