Patent ID: 8745464

Claim:
A system comprising: a processing logic configured to issue a plurality of requests; a memory module having a plurality of ranks; and a memory controller logic coupled with the processing logic and the memory module, the memory controller logic configured to issue a plurality of read commands to the plurality of ranks based on the plurality of requests, wherein data corresponding to the plurality of read commands is configured to be transferred over a common memory channel, and wherein the memory controller logic comprises: a scheduling unit configured to schedule the plurality of read commands to accommodate cyclic redundancy check (CRC) processes enabled on individual ranks of the plurality of ranks; an error correction code (ECC) checker configured to perform an ECC check on data returned from a first rank of the plurality of ranks in response to a read command of the plurality of read commands and to generate an ECC check result based on the ECC check; a CRC checker configured to perform a CRC check on the data and to generate a CRC check result based on the CRC check; and a tracker configured to issue a signal to indicate that the data is valid based on both the ECC check result and the CRC check result if CRC processes are enabled for the first rank, or based only on the ECC check result if the CRC processes are not enabled for the first rank.