Patent ID: 8199577

Claim:
A method of programming memory cells in an electrically erasable programmable solid-state memory array including a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a control gate and a source/drain path in a floating-gate transistor, the method comprising the steps of: applying a first programming voltage to a word line corresponding to a first selected row of memory cells, the word line coupled to the control gate of each of the memory cells in the selected row; during the step of applying the first programming voltage and for each of a plurality of column addresses, sequentially applying a second programming voltage to one or more bit lines associated with each of the plurality of column addresses, each bit line corresponding to a column of memory cells and coupled to the source/drain path of each memory cell in that column; then removing the first programming voltage from the word line to the first selected row of memory cells; wherein the first and second programming voltages are selected so as to program each memory cell receiving the combination of the first programming voltage at its control gate and the second programming voltage at its source/drain path.