Patent ID: 7279920

Claim:
A method for testing on-wafer integrated circuits (ICs), wherein each on-wafer IC contains an antenna and a memory, the method comprising: transmitting a first instruction and a first set of data to the on-wafer ICs, wherein the first instruction commands the on-wafer ICs to store the first set of data into the memory; transmitting a second instruction and a second set of data to the on-wafer ICs, wherein the first set of data and the second set of data are the same, and wherein the second instruction commands the on-wafer ICs to compare the second set of data with the first set of data stored in the memory; reading out results of the comparisons; and marking a status of each on-wafer IC based on the result of the comparison associated with the on-wafer IC being marked wherein the marking comprises marking the on-wafer IC defective if the comparison indicates that the first set of data differs from the second set of data.