Patent ID: 7567449

Claim:
A memory cell comprising: a logic bit having a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output, and a second OTP memory element providing a second OTP memory element output; and a logic operator coupled to the first OTP memory element output and to the second OTP memory element output and providing a memory output of the memory cell, wherein the first OTP memory element is a first fuse comprising a first selected fuse type, the second OTP memory element is a second fuse comprising a second selected fuse type different from the first selected fuse type, and the logic operator is an OR gate, and wherein the first selected fuse type has a first programming process window and the second selected fuse type has a second programming process window, the first programming process window at least partially overlapping the second programming process window so as to provide a logic bit programming process window.