Patent ID: 8380922

Claim:
A data storage device comprising: a non-volatile memory; a host interface state machine operable to interface with a host by executing control structures; a host interface processor operable to execute code segments for generating the control structures for the host interface state machine; a master processor operable to execute code segments for executing access commands to the non-volatile memory; and a logical block address (LBA) register; wherein: the host interface state machine is operable to receive an access command from the host, the access command identifying a plurality of LBAs including an end LBA; the host interface processor is operable to generate at least one control structure executed by the host interface state machine in connection with servicing the access command; the host interface processor is operable to direct the master processor to execute the access command; the master processor is operable to update the LBA register in connection with executing the access command; and the host interface state machine is operable to execute the control structure to compare the end LBA to the LBA register and communicate with the host in response to the comparison.