Patent ID: 8389339

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring substrate which includes an front surface comprised of a quadrangle in a plan view, a chip-mounting region provided on the front surface, a first electrode terminal group formed on the front surface and formed along an end portion of the front surface, a second electrode terminal group formed on the front surface and formed inside of the front surface than the first electrode terminal group in the plan view, a plurality of first power supply lines coupled to a plurality of first electrodes in the first electrode terminal group, respectively, and extending from the first electrodes toward the end portion of the front surface, respectively, a plurality of second power supply lines coupled to a plurality of second electrodes in the second electrode terminal group, respectively, and extending from the second electrodes toward a first region located between the first electrode terminal group and the second electrode terminal group in the plan view, a first front surface-side insulating film having an opening portion opening the first region and formed on the front surface such that the first and second electrode terminal groups are exposed, and such that the first and second power supply lines are covered, a second front surface-side insulating film formed over the first front surface-side insulating film such that the opening portion is filled, and such that the first and second electrode terminal groups are exposed, a rear surface opposite to the front surface, a third electrode terminal group formed on the rear surface and coupled to the first and second electrode terminal groups, respectively, and a first rear surface-side insulating film formed on the rear surface such that the third electrode terminal groups are exposed; (b) mounting a semiconductor chip on the chip-mounting region of the wiring substrate, the semiconductor chip including a front surface comprised of a quadrangle in the plan view, a plurality of bonding pads formed on the front surface, and a rear surface opposite to the front surface; (c) coupling the bonding pads of the semiconductor chip and the second electrodes of the wiring substrate via a plurality of conductive members, respectively; and (d) forming a plurality of external terminals on the third electrode terminal group of the wiring substrate, respectively, wherein a plating layer is formed on a surface of each of the first and second electrode terminal groups by electrolytic plating method; wherein the first region is provided along aside of the semiconductor chip in the plan view; wherein the first region is disposed around the semiconductor chip in the plan view; and wherein the second front surface-side insulating film is circularly formed around the semiconductor chip in the plan view.