Patent ID: 7577863

Claim:
An addressing type frequency counter circuit for receiving a multiple parameter and a clock of addressing input from an external circuit, using a hardware address to perform the addressing operation for outputting a clock value, comprising; a bus; a data acquisition controller electrically connected to the bus, for receiving address and data from the bus; a plurality of control pins, used to control data transmission of the addressing type of frequency counter circuit; an addressing type input register, used to save the multiple parameter of addressing input from the external circuit and output the multiple parameter; a Down-counter used to receive the multiple parameter from the addressing type input register and a clock from the external circuit, so as to perform a clock width operation for outputting a clock width value; a clock-width register used to receive and save a clock width value from the Down-counter; an Up-counter for receiving the clock width value from the clock-width register and a local clock, comparing the clock width value with the local clock for generating a multiple clock value; a multiple-clock register for receiving and saving a multiple clock value from the multiple clock value; and an addressing type output register for receiving the multiple clock value from the multiple-clock register and outputting to the external circuit.