Patent ID: 8917280

Claim:
An apparatus for controlling display device, comprising: an image data buffer including a buffer memory, the image data buffer receiving input data including a plurality of groups of pixel data each representing values of a group of pixels that constitutes each of a plurality of lines that, in turn, constitutes each of a plurality of frames, in an order of the frames and further in an order of the lines in each of the frames, and writing the groups of pixel data in the buffer memory in synchronous with a first clock signal, wherein the input data further includes end of horizontal blanking signals that indicate ends of horizontal blanking periods in respective ones of the lines such that each of the groups of pixel data is received after the end of horizontal blanking signal in a corresponding one of the lines; a differential value calculation circuit that calculates, in each of the plurality of frames, a differential value between a number of cycles of a second clock signal during a period of a specified number of cycles of the first clock signal and an expected value thereof: and a read control circuit, that: assigns, in a first one of the frames, a period of a specified number of cycles of the second clock signal for each of the lines from a read start timing determined based on a timing of the end of horizontal blanking signal in a first one of the lines in the order of the lines; performs, in each of a second and following ones of the frames, a timing correction before the end of horizontal blanking signal in the first one of the lines based on the differential value that the differential value calculation circuit calculated in a previous frame, and subsequently assigns a period of the specified number of cycles of the second clock signal for each of the lines from a corrected read start timing in the order of the lines; and commands, in each of the first and following ones of the frames, the buffer memory to read and output to the display device, in each of the assigned periods, corresponding one of the groups of pixel data in synchronous with the second clock signal, wherein the differential value is corrected, based upon both a number of lines in the entire respective frame and a number of lines in a valid data area, to reflect an amount of change in latency in the respective frame for which the differential value is calculated.