Patent ID: 7506098

Claim:
An apparatus for data storage comprising: a plurality of flash buses; a plurality of DMA Engines coupled to at least two of the plurality of flash buses; a plurality of flash devices coupled to at least two of the plurality of DMA Engines; wherein data access performance is improved by bus interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two flash buses; wherein data access performance is improved by flash array bank interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two DMA Engines; wherein data access performance is improved by group interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two flash devices; wherein each of the plurality of flash devices further comprises a plurality of sections; wherein each section in the apparatus is operable to be accessed using a physical block address comprising a least significant portion, a second least significant portion, a third least significant portion, and a fourth least significant portion; wherein the least significant portion comprises an order according to the plurality of flash buses, the second least significant portion comprises an order according to a plurality of DMA Engines each coupled to a same flash bus, the third least significant portion comprises an order according to a plurality of flash devices each coupled to a same DMA Engine, and the fourth least significant portion comprises an order according to the plurality of sections in a same flash device; and wherein a logical block address for host data access is mapped to a physical block address according to a placement algorithm whereby host data access performance is improved.