Patent ID: 8120356

Claim:
A test apparatus for testing a characteristic of a multiple transistor devices formed in a semiconductor wafer, said test apparatus comprising: one or more first conductors connecting a first terminal of each said multiple transistor devices through one or more first switch devices that allows or prevents signals from being conducted to said transistor terminal; one or more second conductors connecting a second terminal of each said multiple transistor devices through one or more second switch devices that allows or prevents signals from being conducted to said transistor terminal; one or more third conductors connecting a third terminal of each said multiple transistor devices through one or more third switch devices that allows or prevents signals from being conducted to said transistor terminal; and, control circuit configured in said wafer for generating signals for simultaneously controlling activation of said one or more first, said one or more second switch devices and said one or more third switch devices to enable signals to conduct to each said transistor device at each respective said first, second and third terminals at predetermined times and durations, said signals providing a configuration for applying stress at each said multiple transistor devices; and, said control circuit configured for generating, at a predetermined time, a further local signal for selecting a specific one of said multiple transistor devices, and enabling, via said applied signals, local configuration of a selected transistor device to one or more conditions for obtaining said characteristic data, wherein, said control circuit is configured to enable collection of characteristic data at said selected transistor device, while simultaneous stressing remaining said transistor devices of said multiple.