Patent ID: 8655638

Claim:
A method for converting at least two instructions with base register-relative addressing in an emulation of a program code created for an original processor into a program code for a target processor, wherein the original processor uses addresses with a length of n bits in a cyclical address space, the target processor uses addresses with a length of m bits, where m is greater than n, the target processor allows a base register-relative addressing with distance values that lie between a lower value (min) and an upper value (max), and the supported address space on the original processor for the code to be emulated is limited in such a manner that the conversion of address operands as described in the following steps leads to semantically equivalent behavior on the target processor comprising: converting a first instruction for the original processor with an address operand that results from a first offset (D 1 ) relative to a base register (R), by: determining a projected address on the target processor by forming the sum of the content of the base register (R) and an offset (D) that is greater than or equal to the first offset (D 1 ) and less than the difference (max−min), and projecting the sum onto a cyclical address space with addresses having a length of n bits, determining a first address on the target processor as the sum of the projected address and the first offset (D 1 ), minus the offset (D) and executing a converted first instruction on the target processor with the first address as the address operand; and converting a second instruction for the original processor with an address operand that results from a second offset (D 2 ) relative to a base register (R), by: determining a second address on the target processor as the sum of the projected address and the second offset (D 2 ), minus the offset (D) and executing a converted second instruction on the target processor with the second address as the address operand.