Patent ID: 8898051

Claim:
An emulation method, comprising: emulating a user's logic design on an emulator chip comprising a trace array and a plurality of processor clusters each coupled with the trace array, wherein each processor cluster comprises a plurality of processors and a multiplexer coupled with each of the processors, wherein the multiplexer selects an output signal from one of the plurality of processors and outputs the selected output signal to the trace array; capturing a plurality of emulation data bits into a frame of the trace array during a first time window according to a first plurality of values of a first set of hardware control bits, wherein the first time window spans a first plurality of emulation steps; capturing a plurality of emulation data bits into the frame during a second time window according to a second plurality of values of the first set of hardware control bits, wherein the second time window spans a second plurality of emulation steps that are non-continuous with the first plurality of emulation steps; and selectively outputting the frame of data from the trace array based on a second set of hardware control bits, wherein the frame of data is one of the plurality of frames of data captured into the trace array.