Patent ID: 7088628

Claim:
A memory device comprising: first memory cells connected to a bit line; second memory cells connected to a complementary bit line; a bit-line equalization circuit which pre-charges the bit line and the complementary bit line to a power source voltage level; a sensing enable unit which changes the voltage at its output node to a ground voltage level in response to a sensing enable signal; and a bit-line sense amplifier in which when the first memory cells connected to the bit line are selected, a second addressing signal for selecting the second memory cells connected to the complementary bit line is generated with a voltage level higher than that of a first addressing signal for selecting the first memory cells connected to the bit line, thereby amplifying a voltage level of the bit line and a voltage level of the complementary bit line using a first current path and a second current path, wherein the first current path is formed between the output node of the sensing enable unit and the bit line in response to the voltage level of the complementary bit line and the first addressing signal, and the second current path is formed between the output node of the sensing enable unit and the complementary bit line in response to the voltage level of the bit line and the second addressing signal.