Patent ID: 7741224

Claim:
A method of forming an interconnect structure for an integrated circuit, comprising the steps of: providing a substrate; forming a dielectric stack on said substrate comprising an etch-stop layer, a low-k dielectric layer on said etch-stop layer, and a hardmask layer on said low-k dielectric layer; patterning a photoresist masking layer on said dielectric stack to define a plurality of feature defining regions; plasma processing said substrate in a plasma-based reactor, said processing comprising etching a plurality of features into said hardmask layer and into at least a portion of said low-k dielectric layer in said feature defining regions and performing a plasma treatment process in situ in said plasma-based reactor, said plasma treatment process comprising flowing at least one hydrocarbon into said reactor and generating a plasma, wherein a mass flow rate of hydrocarbon into said plasma based reactor is at least 0.1 sccm; and forming a metal conductor in said plurality of features.