Patent ID: 7192823

Claim:
A manufacturing method for a transistor of an electrostatic discharge protection device, comprising: providing a semiconductor base, on which basic elements are formed, comprising an isolation structure, a p-well region, a polysilicon gate structure, and doped regions for forming source/drain regions, at least one source/drain region having both light-ion doped and heavy-ion doped areas; forming a patterned resist layer used as a mask on the semiconductor base and exposing an area including a substantial portion of the polysilicon gate structure and an adjacent drain region for performing ion implantation in the exposed area so that a dopant can be implanted into the semiconductor base to form an extended drain heavy-doped region extending under the exposed portion of the polysilicon gate structure; eliminating the patterned resist layer and proceeding with heat tempering processing; and forming self-aligned salicide in the semiconductor base on the surfaces of the polysilicon gate and the source/drain regions.