Patent ID: 7236021

Claim:
An output buffer comprising: a P-channel power FET having a source connected to a supply voltage, a gate and a drain connected to an output terminal; an N-channel power FET having a drain connected to the output terminal, a gate and a source connected to ground; a first rising voltage drive circuit connected to said gate of said P-channel power FET supplying a rising voltage slope controlled gate drive to said gate of said P-channel FET when activated; a first falling voltage drive circuit connected to said gate of said P-channel power FET supplying a falling voltage slope controlled gate drive to said gate of said P-channel FET when activated; a second rising voltage drive circuit connected to said gate of said N-channel power FET supplying a rising voltage slope controlled gate drive to said gate of said N-channel FET when activated; a second falling voltage drive circuit connected to said gate of said N-channel power FET supplying a falling voltage slope controlled gate drive to said gate of said N-channel FET when activated; a first voltage sensing circuit connected to said gate of said P-channel power FET generating a first inhibit signal if a voltage on said gate of said P-channel power FET is above a first predetermined voltage; a second voltage sensing circuit connected to said gate of said N-channel power FET generating a second inhibit signal if a voltage on said gate of said N-channel power FET is above a second predetermined voltage; a logic drive circuit for alternatively activating (1) said P-channel power FET via said first rising voltage drive circuit and said first falling voltage drive circuit or (2) said N-channel power FET via said second falling voltage drive circuit and said second rising voltage circuit, said logic drive circuit including an AND gate having a first input receiving a data input signal, a second input receiving said second inhibit signal and an output supplying an activate signal to said first falling voltage drive circuit, and an OR gate having a first input receiving a data input signal, a second input receiving said first inhibit signal and an output supplying an activate signal to said second falling voltage drive circuit.