Patent ID: 7332388

Claim:
A method for use in fabrication of a semiconductor device, the method comprising: forming a first polysilicon layer over a semiconductor wafer; forming a silicidation inhibitor at a first location which comprises the first polysilicon layer to reduce a silicidation rate of the first polysilicon at the first location, leaving a second location which comprises the first polysilicon layer free from the silicidation inhibitor; forming a second polysilicon layer over the first polysilicon layer and over the silicidation inhibitor; etching the first and second polysilicon layers at the first location to define a first transistor gate structure; etching the first and second polysilicon layers at the second location to define a second transistor structure; forming a metal layer in contact with the first transistor structure and the second transistor structure; and simultaneously converting the second polysilicon layer at the first location and both the first and second polysilicon layers at the second location to silicide, wherein at least a portion of the first polysilicon layer at the first location remains unsilicided.