Patent ID: 7623364

Claim:
A semiconductor device including a semiconductor chip having a core region and an input/output region formed outside the core region, so arranged that at least an operation part and a memory for holding data from the operation part are formed in the core region, and an input/output circuit for inputting/outputting data between the operation part or the memory formed in the core region and an external source is formed in the input/output region, wherein the semiconductor chip includes: (a) a first wire for supplying power supply potential to the operation part and the memory; (b) a second wire for supplying a potential lower than the power supply potential to the operation part; (c) a third wire for supplying a potential lower than the power supply potential to the memory; (d) a reference wire for supplying reference potential; (e) a first switch for electrically coupling and decoupling the second wire and the reference wire to and from each other; (f) a second switch for electrically coupling and decoupling the third wire and the reference wire to and from each other; (g) a plurality of first pads electrically coupled with the first wire; and (h) a plurality of second pads electrically coupled with the reference wire, and wherein the first pads and the second pads are formed in the core region and the first switch and the second switch are also formed in the core region.