Patent ID: 8671323

Claim:
A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder for partial parallel decoding of low-density parity-check convolutional codes, the decoder comprising: a plurality of pipeline processors to receive channel messages and edge-messages; each processor having: a plurality of block processing units (BPUs), each BPU having a plurality of check node processors (CNPs) to process check nodes that enter into the processor and a plurality of variable node processors (VNPs) to process variable nodes that are about to leave the processor; and a plurality of Random Access Memory (RAM) blocks for dynamic message storage of the channel messages and the edge-messages; wherein in each processor, the VNPs are directly connected to corresponding RAM blocks, and the CNPs are directly connected to corresponding RAM blocks such that the connections from the VNPs and CNPs to the corresponding RAM blocks are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.