Patent ID: 8648615

Claim:
A method of testing a multi-die integrated circuit, the method comprising: testing an inter-die connection of the multi-die integrated circuit, wherein the inter-die connection comprises a bump coupling a first die to a second die; wherein the first die is bonded to the second die using a semi-permanent bonding technique; wherein the testing the inter-die connection includes: providing a first probe pad disposed on the second die, wherein the first probe pad is coupled to a first bump coupling the first die to the second die; providing a second probe pad disposed on the second die, wherein the second probe pad is coupled to a second bump coupling the first die to the second die; and loading configuration data into configuration memory cells in the first die, wherein the configuration memory cells having the configuration data establish an internal connection in the first die, coupling the first bump to the second bump; detecting whether a fault occurs during testing of the inter-die connection; responsive to detecting the fault, designating the multi-die integrated circuit as including a faulty inter-die connection; and re-processing, when the multi-die integrated circuit is designated as including a faulty inter-die connection, the inter-die connection.