Patent ID: 8296538

Claim:
Apparatus for processing data, said apparatus comprising: a memory; processing circuitry responsive to program instructions to perform processing operations, said processing circuitry having a plurality of modes of operation including one or more secure modes and one or more non-secure modes, said memory including: (i) one or more secure regions accessible in said one or more secure modes and inaccessible in said one or more non-secure modes; and (ii) one or more non-secure regions accessible in said one or more secure modes and accessible in said one or more non-secure modes; memory control circuitry responsive to page table data to manage access to said memory; wherein said page table data includes secure mode page table data used to manage access to said memory when said processing circuitry is operating in said one or more secure modes and non-secure mode page table data used to manage access to said memory when said processing circuitry is operating in said one or more non-secure modes; said secure mode page table data includes a hierarchy of page tables with associated page table levels configured such that a first-level page table at a first page table level contains page table entries pointing to respective second-level page tables at a second page table level lower in said hierarchy than said first page table level; and each page table entry of said first-level page table includes a table security field indicating whether a second-level page table pointed to by said page table entry is stored within said one or more secure regions or within said one or more non-secure regions, wherein said page table data provides attribute data associated with a memory address subject to a memory access operation, said processing circuitry is configured to execute a plurality of software processes and said attribute data for said memory address is either global attribute data for use for memory accesses from any of said plurality of software processes or non-global attribute data for use for memory accesses from an individual software process and said memory control circuitry is configured to perform a page table walk operation in which a sequence of page table entries descending through said page table levels in said hierarchy are accessed to retrieve attribute data of a memory access operation to be managed and, if any of said sequence of page table entries has a value of said table security field indicating one of said sequence of page table entries is stored within said one or more non-secure regions, then said memory control circuitry is configured to treat said attribute data as if it were non-global attribute data.