Patent ID: 7343580

Claim:
An automated method for inserting dummy surfaces into various layers of a physical design of a multilayer integrated circuit organized in interconnected units containing interconnected blocks composed of interconnected cells, implemented by an integrated circuit design system, comprising: automated implementation, layer by layer, of a multilayer integrated circuit design, stored in storage means of the integrated circuit design system, through selective insertion of patterns of dummy surfaces, said selective insertion being based on an insertion hierarchy with respect to a hierarchy of the physical design of the multilayer integrated circuit, by means of individual implementation of the interconnected blocks and first interconnection routing for said interconnected blocks, and individual implementation of the interconnected units and second interconnection routing for said interconnected units, wherein, for each interconnected block of said interconnected blocks, the patterns of dummy surfaces are established selectively based on a method used for designing said each interconnected block of the interconnected blocks of the multilayer integrated circuit, said method used for designing at least one of the interconnected blocks comprising a standard cell method or a custom cell method.