Patent ID: 8248422

Claim:
A circuit arrangement, comprising: a processing unit including a single instruction multiple data (SIMD) execution unit, the SIMD execution unit including a plurality of processing lanes and a vector register file; and program code configured to be executed by the processing unit to apply at least one texture to a plurality of pixels in a graphic image by processing pixels in groups, the program code configured to load data associated with each pixel in a group of pixels into a common vector register from the vector register file, concurrently perform at least one scalar operation for each pixel in the group of pixels by operating on the common vector register with the SIMD execution unit such that the data associated with each pixel in the group of pixels is processed in a separate processing lane in the SIMD execution unit, and perform at least one vector operation for each pixel in the group of pixels using the SIMD execution unit, wherein the program code is configured to perform the vector operation by performing a mathematical operation with a scalar value associated with one of the pixels in the group and stored in a first vector register in the vector register file and a vector value stored in a second vector register in the vector register file, wherein the program code is further configured to perform a permute operation to permute the scalar value associated with the one of the pixels in the group into multiple words in a third vector register, and perform the mathematical operation with the scalar value by performing a mathematical operation as a vector operation using the second and third vector registers.