Patent ID: 8713497

Claim:
A non-transitory computer readable medium storing computer program instructions that, when executed by a microprocessor, cause the microprocessor to perform a method of generating an integrated circuit model, comprising: generating, with the microprocessor, a circuit isolation node file according to a circuit connection net-list and an isolation cell topology, comprising: executing at least one first instruction included by an instruction set program and taking the circuit connection net-list and the isolation cell topology as arguments of executing the at least one first instruction for generating the circuit isolation node file; generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage spec file, comprising: executing at least one second instruction included by the instruction set program and taking the circuit connection net-list and the pin voltage spec file as arguments of executing the at least one second instruction for generating the interface node voltage net-list; and generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list.