Patent ID: 8126079

Claim:
Circuitry for receiving a high-speed serial data signal having any one of a plurality of different possible data rates comprising: circuitry for producing an oscillating signal of controllably variable frequency; first circuitry for dividing frequency of the oscillating signal by a first programmably selectable factor to produce a feedback input signal; a first feedback loop for comparing phase and frequency of a first signal derived from the feedback input signal to phase and frequency of a reference clock signal to produce a first control signal for indicating to the circuitry for producing how the frequency of the oscillating should be changed to improve a result of the comparing phase and frequency; and a second feedback loop for comparing phase of the serial data signal to phase of a second signal derived from the feedback input signal to produce a second control signal for indicating to the circuitry for producing how the frequency of the oscillating signal should be changed to improve a result of the comparing phase, wherein: the second feedback loop includes second circuitry for dividing frequency of the feedback input signal by a second dynamically selectable factor to produce the second signal, each possible value of the dynamically selectable factor being appropriate for use with a respective one of the possible data rates; and the second circuitry comprises circuitry for receiving a frequency selection control signal that can request a change in the dynamically selectable factor, and for controlling timing of effecting that change to avoid glitches in the second signal.