Patent ID: 7235453

Claim:
A method of fabricating a MIM capacitor, comprising the steps of: patterning a first metal layer on a first insulating layer on a substrate; forming a planarized second insulating layer having a trench exposing a first portion of the patterned first metal layer therein; forming a second metal layer within the trench; forming a first dielectric layer on the second metal layer; forming first via holes exposing second portions of the patterned first metal layer; forming first plugs filling the trench and the first via holes; forming a third metal layer over the first plugs in the trench and the first via holes; forming a second dielectric layer on the third metal layer; forming a patterned fourth metal layer on the second dielectric layer; patterning the second dielectric layer and the third metal layer; forming a planarized third insulating layer having second via holes therein over the third and fourth metal layers; and forming a patterned fifth metal layer on the third insulating layer including the second via holes.