Patent ID: 8279976

Claim:
A data receiver circuit, comprising: first and second interfaces to be coupled to first and second respective transmission lines, wherein the first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit, to receive a transmission signal from the pair of transmission lines; a common mode extraction circuit coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal, the extracted clock signal having a frequency; and a differential mode circuit, comprising: a differential mode extraction circuit coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal, the extracted data signal having a symbol rate equal to twice the frequency of the extracted clock signal; a first sampling circuit synchronized to a positive phase of the extracted clock signal to sample the extracted data signal using a first voltage offset; and a second sampling circuit synchronized to a negative phase of the extracted clock signal to sample the extracted data signal using a second voltage offset.