Patent ID: 7953511

Claim:
A method for reducing processing errors during a fabrication of a wafer of integrated circuits, the method comprising the steps of: placing the wafer in an ion implantation system, the wafer having a dot matrix wafer scribe; obtaining information about the wafer from the dot matrix wafer scribe by (i) photographing the dot matrix wafer scribe with a camera and (ii) analyzing the photograph of the dot matrix wafer scribe to obtain the information about the wafer; comparing the information about the wafer that is obtained from the dot matrix wafer scribe with information about the wafer that has been previously stored in a station controller that controls the ion implantation system; and implanting the wafer with an ion implantation process only when the information about the wafer that is obtained from the dot matrix wafer scribe matches the information about the wafer that has been previously stored in the station controller.