Patent ID: 8773914

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells, each memory cell being configured to store data; a sensing unit configured to perform a reading operation on data stored in the memory cell array by sensing at least one corresponding memory cell through a plurality of reading steps in response to a single reading command, wherein the plurality of reading steps comprises a coarse read step that performs reading with a first reading voltage, and a fine read step that performs reading with a second reading voltage higher than the first reading voltage for at least one memory cell sensed as an OFF-cell during the coarse read step, and wherein reading time taken by each reading step comprises a precharging time taken to precharge bitlines of memory cell array, a developing time taken to develop a voltage of a sensing node connected to a bitline connected to a corresponding memory cell of the at least one corresponding memory cell among the precharged bitlines, and a latch time taken to latch the developed bitline voltage; and a sensing time controller configured to differently control the precharge time taken by the coarse reading step and the fine reading step performed by the sensing unit.