Patent ID: 7470943

Claim:
A method for fabricating a semiconductor device, comprising: forming at least one p-FET precursor structure with a recessed gate electrode and at least one n-FET precursor structure with an un-recessed gate electrode; depositing a metal layer over said at least one p-FET and said at least one n-FET precursor structures; depositing a first and a second capping layers over said metal layer; annealing said at least one p-FET and said at least one n-FET precursor structures at an elevated temperature to form a first metal silicide layer in a surface of the recessed gate electrode of the at least one p-FET precursor structure, and a second metal silicide layer in a surface of the unrecessed gate electrode of the at least one n-FET precursor structure; and removing unreacted metal, the first capping layer, and the second capping layer from the at least one p-FET and the at least one n-FET precursor structures to form at least one p-FET and at least one n-FET, wherein said first metal silicide layer of said at least one p-FET is intrinsically stressed and is laterally confined by gate spacers and is arranged and constructed for creating compressive stress in a channel region of the at least one p-FET, and said second metal silicide of said at least one n-FET protrudes above one or more gate sidewall spacers.