Patent ID: 7062689

Claim:
Apparatus for processing data, said apparatus comprising: a plurality of different memories, each having a plurality of memory storage locations associated with respective memory addresses, said plurality of different memories having different mappings between physical memory locations and logical addresses associated with said physical memory locations; a self-test controller operable to control self-test of said plurality of different memories including generating physical memory address signals; and a plurality of mapping circuits, each of said plurality of mapping circuits corresponding to a respective one of said plurality of different memories and being operable to map said physical memory address signals generated by said self-test controller to corresponding logical address signals for use by said a respective one of said plurality of different memories to perform a memory test based upon a physical position of said plurality of memory storage locations; and a processor core, wherein said processor core, said plurality of different memories and said self-test controller are formed together on an integrated circuit, and wherein each of said plurality of mapping circuits is part of an interface circuit disposed between said self-test controller and said plurality of different memories, said interface circuit being operable to adapt values and timings of signals passed between said self-test controller and said plurality of different memories to accommodate differing value and timing properties of said plurality of different memories.