Patent ID: 8737560

Claim:
A shift register unit, comprising: a first thin film transistor, the drain of which is connected to a first clock signal input terminal and the source of which is connected to a gate driving signal output terminal; a second thin film transistor, the drain of which is connected to the gate driving signal output terminal, the gate of which is connected to a reset signal input terminal, and the source of which is connected to a low level signal input terminal; a third thin film transistor, the drain and gate of which are connected to a start signal input terminal and the source of which is connected to the gate of the first thin film transistor; a fourth thin film transistor, the drain of which is connected to the source of the third thin film transistor, the gate of which is connected to the reset signal input terminal, and the source of which is connected to the low level signal input terminal; a capacitor, two terminals of which are connected to the gate and the source of the first thin film transistor respectively; a pull-down unit for pulling a signal output by the gate driving signal output terminal down to a low level when the gate driving signal output terminal is needed to output a low level signal; and a driving unit for generating an alternating current driving signal for driving the pull-down unit when the gate driving signal output terminal is needed to output the low level signal, and wherein the driving unit comprises: a tenth thin film transistor, the drain of which is connected to a high level signal input terminal and the gate of which is connected to the first clock signal input terminal; a fifth thin film transistor, the drain of which is connected to the source of the tenth thin film transistor, the gate of which is connected to a second clock signal input terminal, and the source of which is connected to the low level signal input terminal; and a sixth thin film transistor, the drain of which is connected to the source of the tenth thin film transistor, the gate of which is connected to the gate driving signal output terminal, and the source of which is connected to the low level signal input terminal.