Patent ID: 7127385

Claim:
A delay time estimation method for estimating a delay time in a logic circuit that includes a MOS transistor said method comprising the steps of: constructing a delay library including function information for specifying a model of an Ids-Vds characteristic at a given gate potential and also including function information related to a slew rate specifying a fixed delay, where Ids denotes a drain-source current and Vds denotes a drain-source voltage; modeling the MOS transistor by a resistive element having fixed resistance and a power source voltage that varies with time; determining an operating current characteristic of the MOS transistor thus modeled and segmenting the operating current characteristic based upon the delay library into a first region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the MOS transistor in which region the current gradually decreases as the gate potential remains constant, and a third region corresponding to a linearity region of the MOS transistor in which region the current decreases as the gate potential remains constant; and storing the determined estimated delay time of the MOS transistor and output thereof.