Patent ID: 6968427

Claim:
A cache memory comprising: a tag array comprising a plurality of tag entry locations, each of said tag entry locations capable of being accessed by R of the M least significant bits of an N-bit received address and capable storing an address tag comprising the (N-M) most significant bits of said N-bit received address; cache hit comparison circuitry capable of comparing the (N-M) most significant bits of an N-bit received address with an address tag accessed by R of the M least significant bits of said N-bit received address and generating a HIT signal if a match occurs; and tag array test circuitry capable of: storing a copy of the last data written to said tag array; storing an address of a tag entry location to which data was last written; storing a copy of the last data read from said tag array; and determining if R of the M least significant bits of a current received address are equal to R of the M least significant bits of said stored address of said tag entry location to which data was last written.