Patent ID: 8832487

Claim:
A high-speed I/O data system, comprising: a data channel, a clock channel, a first computer chip having a first data transmission system, and a second computer chip having a first data reception system, wherein: the data channel communicates a non-return-to-zero (NRZ) data signal from the first data transmission system to the first data reception system; the clock channel communicates a forwarded clock signal from the first data transmission system to the first data reception system; the first data transmission system includes: a first data output; a first forwarded clock output; a first differential serializing transmitter to generate at the first data output the NRZ data signal, wherein said data signal is generated in part from pulsed data and the first differential serializing transmitter includes two single-ended serializing transmitters; a second differential serializing transmitter to generate at the forwarded clock output the forwarded clock signal, wherein said clock signal is generated in part from pulsed data and the second differential serializing transmitter includes two single-ended serializing transmitters; and a first multi-phase transmit clock generator to generate transmit clock signals for the first and second differential serializing transmitters; and the first data reception system includes: a first data input; a first forwarded clock input; a data receiver and first de-serializer to receive the NRZ data signal at the data input and to de-serialize said NRZ data signal; and a first multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver; and each single-ended serializing transmitter includes N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, wherein N is a positive integer, and wherein each multiplexing drive unit includes: a pulse-controlled push-pull output driver having first and second inputs, and an output coupled to an output of the multiplexing drive unit; a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver and configured to generate a first series of intermediate pulses having a first pulse width at said output, where M is two or more; and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver and configured to generate a second series of intermediate pulses having a second pulse width at said output.