Patent ID: 8464021

Claim:
A system that facilitates physical block address (PBA) and logical block address (LBA) translation in at least one memory component, comprising: the at least one memory component configured to execute at least one memory operation and includes a plurality of memory locations, a memory controller component configured to store LBA to PBA translations respectively associated with a subset of LBAs based in part on a predefined optimization criteria, wherein the optimization criteria comprises at least a number of times an LBA is presented to the memory controller component in association with the at least one memory operation; a defrag component configured to defragment a chunk of data having portions of data that are stored in nonconsecutive pages associated with the at least one memory component and store the portions of data in consecutive pages associated with the at least one memory component during time periods that overlap with execution of the at least one memory operation; and a block address cache component (BA cache component) configured to store LBA to PBA translation information associated with at least one LBA used to access the at least one memory component, wherein the defrag component reduces a size of the BA cache component that is associated with storage of the LBA to PBA translation information by aligning the portions of data in consecutive page locations and storing, in the BA cache component, a starting PBA page number associated with an LBA or a number of pages value.