Patent ID: 7287110

Claim:
A storage device for a multibus architecture, comprising: at least one memory that stores information; a memory connection having a port that is connected to the at least one memory and is selectively connected to one of a plurality of buses within the multibus architecture, at least one data line that communicates with the memory connection and the one of the plurality of buses to provide information to the memory connection to control the memory; a switching device that selectively connects the memory connection to one of the plurality of buses to transmit information between the one of the plurality of buses and the memory; and an analyzer that analyzes addresses on address lines which form a part of at least one of the plurality of buses for determining a selective access to the at least one memory by one of the plurality of buses, where the analyzer comprises an access control device that switches the switching device and a comparator that compares an address on one of the plurality of buses with a memory address of the at least one memory and controls the access control device to control the switching device as a function of the result of the comparison.