Patent ID: 7670900

Claim:
A method for forming a capacitor structure, the method comprising: providing a substrate having a surface region; forming an interlayer dielectric region overlying the surface region, the interlayer dielectric region having an upper surface and a lower surface; forming a container structure within a portion of the interlayer dielectric region, the container structure extending from the upper surface to the lower surface, the container structure having a first width at the upper surface and a second width at the lower surface, the container structure having an inner region extending from the upper surface to the lower surface, the container structure having a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface; forming a doped polysilicon layer overlying the inner region of the trench structure; forming a layer of undoped polysilicon material overlying the doped polysilicon layer overlying the inner region; forming a seed layer overlying the undoped polysilicon material; and causing formation of hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and formation of hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface of the container structure; whereupon the first grain dimension has an average size of no greater than about ½ of an average size of the second grain dimension to prevent any bridging of any portions of the hemispherical grained silicon material within the vicinity of the lower surface.