Patent ID: 7797594

Claim:
A method of testing a 3-dimensional (3D) memory including an active array and a static array, the method comprising: in a first cycle, writing data to the static array of the 3D memory, wherein the static array includes at least one write port and does not include a read port; transferring data from the static array to the active array; and reading data from the active array, wherein the 3D memory is configured such that data stored in the static array is accessible only via a transfer to and a read from the active array; for a plurality of subsequent cycles, writing data to the static array, transferring data from static array to the active array, and reading data from the active array, wherein said writing data for each subsequent cycle is performed concurrently with reading data for a previous cycle; and wherein the active array includes a write port configured to enable writes to the active array, a read port configured to enable reads from the active array, and a transfer port configured to enable the active array to receive data transferred from the static array via a transfer mechanism; and wherein the static array includes a write port configured to enable writes to the static array, and a transfer port configured to enable data to be conveyed from the static array to the active array via a transfer mechanism.