Patent ID: 7012293

Claim:
A memory device comprising a memory cell, the memory cell comprising: a first active area on oxide in a first conductive well located on a first vertical side of the memory cell; a second active area on oxide in a second conductive well located on the first vertical side of the memory cell; a third active area on oxide in the first conductive well located on a second vertical side of the memory cell; a first bitline operatively coupled to said third active area on oxide; a fourth active area on oxide in the second conductive well located on the second vertical side of the memory cell; a second bitline operatively coupled to said fourth active area on oxide; a first gate located on the first vertical side of the memory cell; a second gate located on the second vertical side of the memory cell; a first local interconnect connecting the first active area, the second active area, and the second gate via a second EC contact located on the second gate; and a second local interconnect connecting the third active area, the fourth active area, and the first gate via a first EC contact located on the first gate.