Patent ID: 7525844

Claim:
A semiconductor memory device comprising: a memory cell array in which memory cells are arranged; a plurality of first bit lines each of which connects commonly the memory cells; a second bit line which connects commonly two or more of the first bit lines; a first sense amplifier which is provided for the second bit line and which controls not only the connection between the second bit line and the first bit lines but also the potential on the second bit lines according to the data read from the memory cells onto the first bit lines; a second sense amplifier which precharges one of the first bit lines via the second bit line and the first sense amplifier and, when reading the data from the memory cells, amplifies the potential on the second bit line; word lines which connect commonly the memory cells; a row decoder which selects any one of the word lines in a read operation; and a sense amplifier control circuit which controls the operation of the first sense amplifier, wherein the row decoder and the sense amplifier control circuit are arranged so as to face each other in a direction along the word line, with the memory cell array being sandwiched between the row decoder and the sense amplifier control circuit, the first sense amplifier includes a first switch circuit which connects the second bit line to the first bit line according to control performed by the sense amplifier control circuit; a second switch circuit which connects the second bit line to the ground potential according to control performed by the sense amplifier control circuit and the potential on the first bit line; and a read control circuit which controls the operation of the second switch circuit according to the potential on the first bit line, the read control circuit includes a first inverter which has an input node connected to the first bit line and which inverts a potential on the first bit line, the second switch circuit includes a first MOS transistor one end of whose current path is connected to the second bit line, the other end of whose the current path is electrically connected to a ground potential and whose gate is connected to an output node of the first inverter the first switch circuit connects the second bit line to the first bit line while the first bit line is being precharged and disconnects the second bit line from the first bit line while data is being read from the memory cell according to a control by the sense amplifier control circuit, and the first inverter causes the first MOS transistor to have an ON state to connect the second bit line to the ground potential when “1” data is read from the memory cell.