Patent ID: 7164743

Claim:
A delay locked loop which synchronizes data and a clock input from outside, said delay locked loop comprising: a voltage controlled delay line having a plurality of delay elements sequentially delaying said clock, said plurality of delay elements arranged in groups; a slot selector selecting an output signal output from one of said groups in response to a select signal; a clock tree circuit receiving said output signal from said slot selector for outputting a plurality of clocks with the same timing; a phase control part receiving said clock input from outside and one of said clocks output from said clock tree circuit for controlling a delay time of said plurality of delay elements such that said clock output from said clock tree circuit delays a predetermined constant time from said clock input from outside; and a sensing circuit sensing a variation of resistance value of a load resistance of a differential circuit which has a delay time contributing a portion of said constant time and outputting said select signal in response to said sensed variation of resistance value, wherein said sensing circuit comprises a resistance element having one end connected to a first power source and formed to be the same resistance value as the load resistance of said differential circuit, a constant current source connected between a second power source and the other end of said resistance element, and a Schmidt comparator circuit receiving a junction potential of said resistance element and said constant current source as one input and threshold voltages having a plurality of reference potentials as other inputs and outputting said select signal as a comparison result.