Patent ID: 8035136

Claim:
A semiconductor device comprising: a semiconductor substrate including an active region and a non-active region defined by a device isolation layer, the active region including a recessed portion in the substrate; a gate electrode including a gate insulation layer on an inner sidewall and on a bottom of the recessed portion, a lower electrode on the gate insulation layer located in a lower portion of the recessed portion, an inner spacer on the lower electrode located at an upper portion of the recessed portion, and an upper electrode that is positioned on the inner spacer and electrically connected to the lower electrode; and source and drain impurity regions at surface portions of the active region of the substrate adjacent to the upper electrode, the source and drain impurity regions being electrically insulated by the inner spacer; and wherein a lower surface of the inner spacer is lower than the source and the drain impurity regions and an upper surface of the inner spacer is at a level equal to or lower than a surface of the substrate, so that the inner spacer is between the source and drain impurity regions under the upper electrode.