Patent ID: 8046563

Claim:
A method for emulating a guest instruction set architecture on an integrated circuit, the integrated circuit comprising a plurality of processor cores associated with a host instruction set architecture, the method comprising: receiving guest instructions of the guest instruction set architecture; executing each of a plurality of host processes on a respective set of one or more processor cores; a first set of one or more processor cores executing a first host process providing a high level translation function on one or more of the guest instructions to generate one or more high level instructions; a second set of one or more processor cores executing a second host process providing a low level translation function on one or more high level instructions to generate one or more low level host instructions of the host instruction set architecture; providing first high level instructions generated by the first host process from a first set of one or more guest instructions to the second host process to generate first low level host instructions, and providing second high level instructions generated by the first host process from a second set of one or more guest instructions to the second host process to generate second low level host instructions, and providing the low level host instructions to a runtime-execution system in one or more of the processor cores to execute the guest instructions.