Patent ID: 8854292

Claim:
A gate drive circuit having a plurality of stages, each stage connected one after another to each other and including a first stage in which a scan start signal is provided to an input terminal, the gate drive circuit configured to sequentially output output signals of respective stages, each of the stages comprising: a charging section that charges the scan start signal or an output signal provided from a previous stage; a driving section coupled to the charging section through a first node, and configured to pull-up a high level of a first clock signal to output a gate signal as the first node is charged to a high level; a discharging section connected to the first node, and configured to discharge a signal of the first node to a first off-voltage in response to an output signal provided from a next stage; a holding section connected to an output node and the first node, and configured to hold the signal of the first node to the first off-voltage; and a holding control section connected to the first node and the holding section, and configured to receive the first clock signal and a second clock signal, and to hold a signal of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section, the second off-voltage being only applied to the holding control section, wherein the holding section comprises: a first holding transistor having a drain connected to the first node, a gate that receives the first clock signal, and a source that receives the first off-voltage; and a second holding transistor having a drain connected to the output node, a gate connected to the gate of the first holding transistor, and a source that receives the first off-voltage, and wherein the first off-voltage and the second off-voltage have different voltage sources.