Patent ID: 7642166

Claim:
A method of forming MOS transistors, comprising: providing a semiconductor substrate, a first active region and a second active region being defined in the semiconductor substrate, each of the active regions comprising at least a gate structure, two sidewalls on each of the gate structures comprising a liner, each of the active regions comprising a source region and a drain region in the semiconductor substrate on the opposite sides of the gate structure; forming a stressed cap layer on the semiconductor substrate, covering the gate structures, the liners, the source regions and the drain regions in the first and the second active regions; performing a first etching process on the stressed cap layer to expose the gate structure, the source region and the drain region in the second active region; performing an activating process on the source regions, the drain regions and the stressed cap layer; performing a second etching process on the stressed cap layer to expose the gate structure, the source region and the drain region in the first active region; and performing a salicide process to form a silicide layer on the gate structures, the source regions and the drain regions that are not covered by the stressed cap layer in the first and the second active regions.