Patent ID: 8044689

Claim:
A semiconductor circuit comprising: an output buffer configured to allow a first current to flow to a node, wherein the buffer comprises: a first plurality of cascode-coupled transistors with said node therebetween, configured to allow the first current comprising a difference current between the first plurality of transistors to leak at said node in response to process variability in transistor characteristics at an operating point; and a compensating circuit configured to enable a second current to flow to the node, said second current compensating for the first current, wherein the compensating circuit comprises a second plurality of cascode-coupled transistors with said node therebetween, generating the second current comprising a difference current between the second plurality of transistors in response to product variability in transistor characteristics at the operating point, wherein: the buffer comprises a CMOS circuitry; and the second plurality of transistors comprises: a p-MOS transistor comprising a control electrode coupled to a first voltage, a first current conducting electrode coupled to the node, and a second current conducting electrode coupled to the first voltage; and an n-MOS transistor comprising a control electrode coupled to a second voltage, a first current conducting electrode coupled to the node, and a second current conducting electrode coupled to the second voltage.