Patent ID: 7716427

Claim:
A processor, comprising:at least one execution unit;prefetch hardware, coupled to said at least one execution unit, including: a prefetch request queue containing entries indicative of allocated data streams; a prefetch engine configured for receiving an address associated with a store instruction and allocating new entries in the prefetch request queue; wherein the prefetch engine determines whether to allocate an entry in the prefetch request queue corresponding to the store instruction by comparing entries in the prefetch request queue to a window of addresses encompassing multiple cache lines, wherein the window of addresses is derived from the received address; wherein, in response to determining that one of the entries in the prefetch request queue includes an address within the address window, the prefetch engine suppresses allocation of a new entry in the prefetch request queue and services the entry that includes the address within the address window; and wherein, in response to determining that none of the entries in the prefetch request queue includes the address within the address window, the prefetch engine allocates another entry in the prefetch request queue indicative of a new data stream corresponding to the store instruction.