Patent ID: 8593895

Claim:
A semiconductor device comprising: an array having a hierarchical bit line structure; first and second global bit lines physically adjacent to each other; a plurality of first local bit lines corresponding to the first global bit line and corresponding to a plurality of sub-arrays forming the array; a plurality of second local bit lines corresponding to the second global bit line and corresponding to the plurality of sub-arrays, the second local bit lines being physically adjacent to the first local bit lines respectively; a plurality of first hierarchical switches controlling electrical connections between the first global bit line and the first local bit lines respectively; a plurality of second hierarchical switches controlling electrical connections between the second global bit line and the second local bit lines respectively; a first precharge circuit precharging the first global bit line to a first precharge voltage; a second precharge circuit precharging the second global bit line to a second precharge voltage; a plurality of third precharge circuits precharging the first local bit lines to a third precharge voltage respectively; a plurality of fourth precharge circuits precharging the second local bit lines to the third precharge voltage respectively; and a control circuit controlling the first to third precharge circuits and voltage values of the first to third precharge voltages, wherein, when performing a test of the array, by achieving a state in which the first and second precharge voltages are set to first and second potential levels different from each other, the first and second precharge circuits are activated, the third and fourth precharge circuits are inactivated, and the first and second hierarchical switches are brought into a connected state, the control circuit controls the first and second potential level to be applied to the first and second local bit lines through the first and second global bit lines respectively.