Patent ID: 7884649

Claim:
A method, including steps of: identifying information sufficient to describe a set of clock gating elements for a set of circuit elements; and determining a set of transformations to apply to those circuit elements, with the effect that those clock gating elements are applied to those circuit elements with substantially optimal power reduction for that set of circuit elements, wherein that step of determining includes steps of: transforming that information into a data structure having properties of identifying those circuit elements which are responsive to those clock gating elements; and identifying those clock gating elements to which those circuit elements are responsive, wherein that step of identifying includes steps of: identifying a first clock gating element with substantially the best power reduction for that set of circuit elements; and identifying a second clock gating element with substantially the best gain increase when combined with that first clock gating element; and in response to those steps of identifying, combining a first data structure associated with that first clock gating element with a second data structure associated with that second clock gating element.