Patent ID: 8461893

Claim:
A delay cell for a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), the delay cell comprising: a delay stage configured to provide an output signal having a programmable delay through the delay cell, the delay cell having (i) a selectable delay value from a plurality of delay values, and (ii) relatively uniform cell size and terminal layout over a range of the plurality of delay values; an input inverter stage comprising a PMOS and NMOS transistor pair, the input inverter stage configured to transfer an input signal of the delay cell to the delay stage; an output inverter stage configured to generate a drive strength for the output signal from the delay stage, thereby to provide an output signal of the delay cell as a delayed version of the input signal of the delay cell; wherein the delay stage comprises: M series-coupled inverter stages driven between first and second voltage potentials, M a positive integer, each series-coupled inverter stage comprising N transistor pairs of stacked PMOS transistors and stacked NMOS transistors, N a positive integer, a gate node of each of the stacked PMOS transistors and the stacked NMOS transistors coupled to an input of the inverter stage, wherein the N transistor pairs comprise configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of coupled and de-coupled source-drain node connections to adjust a delay value of each of the M inverter stages.