Patent ID: 6839387

Claim:
A sigma-delta converter that includes a feedback loop and operates over a predetermined bandwidth, the sigma-delta converter comprising: a forward path including: a summer for generating a first signal; a filter for averaging the first signal to produce a second signal; a comparator for comparing the second signal to a reference level and producing a third signal based on the comparison; and a storage device, coupled to an output of the comparator, for storing the third signal for a delay period and outputting the third signal responsive to a clock signal, the storage device comprising a D flip-flop that outputs the third signal responsive to the clock signal; a feedback path providing a representation of the third signal to a negative input of the summer, wherein the summer generates the first signal by subtracting the representation of the third signal from an input signal applied to a positive input of the summer; and at least one instability generator, positioned in the forward path, for generating an instability in the feedback loop at a frequency outside the predetermined bandwidth to substantially improve signal-to-noise performance of the sigma-delta converter within the predetermined bandwidth for amplitudes of the input signal that are substantially near a low end of a dynamic range of the sigma-delta converter, the at least one instability generator including a D flip-flop coupled to an output of the storage device to produce a time-delayed representation of the third signal responsive to the clock signal.