Patent ID: 8588340

Claim:
A receiving device comprising: an equalizer circuit shaping a waveform of an input signal according to an equalizer coefficient; a Clock Data Recovery circuit recovering, from the input signal being shaped by the equalizer circuit, received data represented by the input signal and a clock signal which indicates a timing of the received data; a number counting part counting a number of times a voltage value included in a range of detection is obtained by sampling the input signal after being shaped by the equalizer circuit at the timing of the received data, the range of detection having a predetermined width; a zone scanning part scanning the range of detection in a scanning zone to make the number counting part count, in a time-division manner, a number of times of obtaining each voltage value included in the scanning zone by sampling the shaped input signal, the scanning zone being a predetermined range including a variation range of a voltage value of the input signal; a coefficient altering part altering the equalizer coefficient of the equalizer circuit; a peak detecting part detecting a maximum value of a counting result as a peak value for each equalizer coefficient being altered by the coefficient altering part, the counting result being obtained by the number counting part in a process where the range of detection is scanned; and a coefficient specifying part specifying, as a first coefficient, the equalizer coefficient, which is set to the equalizer circuit when the peak value is detected by the peak detecting part, wherein the zone scanning part scans the range of detection by changing, in every predetermined counting period and by a voltage corresponding to a width of the range of detection, a reference voltage indicating an upper limit of the range of detection; and the number counting part includes: a comparator comparing the reference voltage with the voltage value obtained by the sampling of the input signal; an upper counter counting a number of the voltage value obtained by the sampling being judged to be equal to or larger than the reference voltage by the comparator; a lower counter counting a number of the voltage value obtained by the sampling being judged to be smaller than the reference voltage by the comparator; a memory storing a counting result of the lower counter every time the counting period passes and outputting a counting result obtained by the lower counter in a last counting period; and an adder calculating a sum of a counting result obtained by the upper counter for a current counting period and the counting result obtained by the lower counter in the last counting period output from the memory as a number of times a voltage value distributed outside the range of detection corresponding to the current counting period is obtained by the sampling.