Patent ID: 7525865

Claim:
A control circuit for refreshing voltages in a non volatile memory during a standby mode, the control circuit comprising: a Resistive Capacitive (RC) oscillator capable of generating a clock pulse for enabling the control circuit; a node detector circuit comprising, a reference circuit capable of setting a voltage tolerance, the voltage tolerance set through a resistance ladder by a source voltage supply thereby generating a first node voltage and a second node voltage, a pair of capacitors capable of storing the first node voltage and the second node voltage, and a comparator for comparing the first node voltage and the second node voltage and generating an output electrical signal upon comparing the first node voltage and the second node voltage; a flip flop for latching the output electrical signal, wherein the output electrical signal acts as an input to the flip flop; a refresh pulse generator capable of generating an electrical refresh pulse upon receiving the output electrical signal from the flip flop, the electrical refresh pulse being supplied to a refresh node of a plurality of refresh nodes of the non volatile memory, thereby refreshing voltages in the non volatile memory during the standby mode; a detector circuit for enabling the comparator and the flip flop, wherein inputs to the detector circuit are the clock pulse from the RC oscillator and the electrical refresh pulse; and a sample pulse generator for generating an electrical sample pulse, the electrical sample pulse along with the electrical refresh pulse setting the flip flop, thereby causing the flip flop to latch a new output electrical signal.