Patent ID: 8706431

Claim:
A system for determining a fault location on a wire, the system comprising: a (pseudo random) PN code having a chip-time; software code for delaying the PN code a series of delays to form delayed PN samples, a sum of the series of delays being less than one chip-time; software code for summing the delayed PN samples with the PN code to form a summed sequence; software code for transmitting the summed PN sequence to a wire being tested; software code for receiving a signal from the wire being tested related to the summed PN sequence; software code for mixing the signal received from the wire being tested with a delayed copy of the summed PN sequence so as to form a mixed signal; software code for integrating the mixed signal to map faults so as to detect indications of failures; a database of known good signatures obtained from previously tested known good wires and known failure mode signatures obtained from previously tested wires with known defects: and an artificial neural network for processing the software code for integrating the mixed signal to map faults, wherein the neural network compares the map faults as a signature of the wire being tested against the database of known good signatures and failure mode signature to predict a potential failure of the wire.