Patent ID: 8900938

Claim:
A manufacturing method of an array substrate, comprising the following steps: A. adopting a first mask manufacturing process to from a scan line(s) and a thin film transistor (TFT) gate(s) on a surface of a substrate; B. successively paving an insulating layer, a second metal layer and an n+a-Si film on the substrate; then, adopting a second mask manufacturing process to form a scan line(s) and a data line(s) of the array substrate, a source electrode and a drain electrode of the thin film transistor (TFT), and a conducting channel positioned between the source electrode and the drain electrode; C. incinerating a photoresistor formed in the second mask manufacturing process to expose the n+a-Si film on both ends of the conducting channel; then, paving an a-Si film on a surface of the array substrate and forming reliably electric connection between the formed a-Si film and the n+a-Si film on both ends of the conducting channel; D. stripping the photoresistor and also removing the a-Si material covering the surface of the photoresistor; forming an undoped active layer by the remaining a-Si film; E. adopting a third mask manufacturing process, and reserving the n+a-Si film on the covering part of the undoped active layer to form a doped active layer; then, forming a transparent conducting layer on the surface of the drain electrode of the thin film transistor (TFT).