Patent ID: 8148222

Claim:
A method of forming an array of memory cells, comprising: forming a plurality of pillars comprising fabricating a shallow trench isolation structure having array trenches and an oxide in the array trenches, forming a column trench mask, and etching column trenches in the semiconductor material that space apart the columns of the pillars, wherein individual pillars have a semiconductor post formed of a semiconductor material and a sacrificial cap on the semiconductor post; forming source regions between columns of the pillars; forming a plurality of gate lines, wherein individual gate lines extend along a corresponding column of pillars and are spaced apart from corresponding source regions, and wherein each gate line surrounds a portion of the semiconductor posts along a column of pillars; selectively removing the sacrificial caps and thereby forming self-aligned openings that expose a top portion of corresponding semiconductor posts; and forming individual drain contacts in the self-aligned openings that are electrically connected to corresponding semiconductor posts.