Patent ID: 7664928

Claim:
A processor comprising: one or more user-defined interfaces, each of which are capable of reading from or writing to an associated external agent; a pipeline for executing instructions, the pipeline having a commit stage at which instructions commit; a speculation handling circuit coupled to the pipeline and having a buffer, the buffer temporarily holding data that is read from or written to a first one of the user-defined interfaces, the data being associated with a first instruction executing in the pipeline, the speculation handling circuit being adapted to control the holding and release of the data from the buffer based on whether the first instruction reaches the commit stage in the pipeline; a circuit that receives the status of an external agent associated with a second one of the user-defined interfaces, and generates a signal that indicates whether the external agent is ready, wherein the status of the signal can be read in a second instruction of the processor so as to test whether access of the second user-defined interface will succeed; and a mechanism that facilitates conditional access of the second user-defined interface by the second instruction, wherein the signal is used by the mechanism to determine whether access of the second user-defined interface by the instruction should be killed, such that the second user-defined interface is accessed if the external agent is ready, but not accessed if it is not ready.