Patent ID: 8395951

Claim:
A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising: transmit circuitry to transmit, to the DRAM: write data to be sampled by the DRAM on one or more edges of the timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM; a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data; and adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal at the DRAM is aligned with a rising edge of the first clock signal at the DRAM.