Patent ID: 7564440

Claim:
A shift register unit, comprising: a first unit comprising a first input terminal and a second input terminal coupled to a start pulse and a clock signal respectively, to output a first output pulse during a first period; and a second unit comprising a first input terminal and a second input terminal coupled to the first output pulse and an inverse signal of the clock signal respectively, to output a second output pulse during a second period, wherein the first unit comprises: a first clock inverter comprising an input terminal coupled to the clock signal to output a first signal during the first period; a second clock inverter comprising an input terminal coupled to the first output pulse to output a second signal during the second period; a first inverter coupled to the first clock inverter to convert the first signal into the first output pulse during the first period; a first NOR gate comprising a first input terminal coupled to the start pulse, a second input terminal coupled to the output terminal of the first inverter, and an output terminal; and a second inverter comprising an input terminal coupled to the output terminal of the first NOR gate, wherein the first clock inverter further comprises a first control terminal coupled to the output terminal of the first NOR gate and a second control terminal coupled to the output terminal of the second inverter, and the second clock inverter further comprises a first control terminal coupled to the output terminal of the second inverter and a second control terminal coupled to the output terminal of the first NOR gate, and the first clock inverter comprises: a first PMOS transistor comprising a first terminal coupled to a first voltage, a control terminal coupled to the output terminal of the first NOR gate, and a second terminal; a second PMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a control terminal coupled to the clock signal and a second terminal coupled to the input terminal of the first inverter; a first NMOS transistor comprising a first terminal and a control terminal coupled to the second terminal and the control terminal of the second PMOS transistor respectively, and a second terminal; and a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a control terminal coupled to the output terminal of the second inverter and a second terminal coupled to a second voltage.