Patent ID: 8867697

Claim:
A shift register comprising a plurality of stages for sequentially outputting scan pulses, wherein an nth one of the stages, where n is a natural number, the shift register comprising: a node controller for controlling voltages at a set node and a reset node; and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage in response to the voltages at the set node and the reset node, wherein the node controller of the nth stage comprises: a first switching device controlled by a voltage supplied to the reset node and connected between the set node and a second discharging voltage line transferring a second discharging voltage; a second switching device controlled by a scan pulse from an (n−p)th one of the stages, where p is a natural number less than n, and connected between a charging voltage line transferring a charging voltage and the set node; a third switching device controlled by a scan pulse from an (n+q)th one of the stages (where q is a natural number) and connected between the set node and the second discharging voltage line; a fourth switching device controlled by the scan pulse from the (n−p)th stage and connected between the reset node and the second discharging voltage line; and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a first discharging voltage to the reset node, wherein the inverter circuit comprises: a first inverting switching device controlled according to the charging voltage and connected between the charging voltage line and a common node; a second inverting switching device controlled according to a voltage at the set node and connected between the common node and a third discharging voltage line transferring a third discharging voltage; a third inverting switching device controlled according to a voltage at the common node and connected between the charging voltage line and the reset node; and a fourth inverting switching device controlled according to the voltage at the set node and connected between the reset node and a first discharging voltage line transferring the first discharging voltage, wherein the output unit of the nth stage comprises: a pull-up switching device controlled by a voltage at the set node and connected between a clock transfer line transferring any one of a plurality of clock pulses having phase differences thereamong and an output terminal of the nth stage; and a pull-down switching device controlled by a voltage at the reset node and connected between the output terminal and the first discharging voltage line, wherein the third discharging voltage is lower than the second discharging voltage, and wherein a gate electrode of the second switching device and a gate electrode of the fourth switching device are connected to each other.