Patent ID: 7136312

Claim:
A semiconductor device comprising: a plurality of memory cells; a plurality of bit line pairs respectively connected to said plurality of memory cells through transistors; a plurality of sense amplifiers respectively connected to said plurality of bit line pairs; a plurality of data line pairs respectively connected to said plurality of sense amplifiers; a plurality of main amplifiers respectively connected to said plurality of data line pairs; a plurality of switching circuits respectively provided between said plurality of sense amplifiers and said plurality of main amplifiers each for connecting/disconnecting a corresponding sense amplifier to/from a corresponding main amplifier; and a memory control circuit, wherein said memory control circuit controls said plurality of sense amplifiers, said plurality of main amplifiers and said plurality of switching circuits in such a manner as to: receive a reading row control signal, a write enable signal, a clock signal, a row address and a column address; data read from memory cells selected in response to said row address into corresponding main amplifiers through said bit line pairs, said sense amplifiers and said data line pairs in accordance with said clock signal when said reading row control signal is at active level; disconnect said plurality of sense amplifiers from said plurality of main amplifiers by opening said plurality of switching circuits after said data read from said memory cells into said main amplifiers, and precharge said plurality of bit line pairs with said data held in said plurality of main amplifiers; and output data held in said main amplifiers selected in response to said column address in accordance with said clock signal when said write enable signal is at non-active level.