Patent ID: 7394424

Claim:
A time delay circuit for imparting a time delay to a data signal associated with an antenna element in a multi-element antenna, the time delay circuit comprising: a data signal input for accepting the data signal to be delayed by the time delay circuit; a digital clock reference; a memory storing beamforming control information, wherein the beamforming control information determines physical characteristics of a beam to be formed by the multi-element antenna; a delay control coupled to the memory, where the delay control calculates the time delay to be applied to the data signal in dependence on the beamforming control information, wherein the time delay calculated by the delay control comprises a coarse delay control component expressed in terms of a number of whole clock cycles of the digital clock reference and a fine delay control component expressed in terms of a portion of a whole clock cycle of the digital clock reference, the delay control further comprising a coarse delay control signal output for conveying a coarse delay control signal corresponding to the coarse delay control component and a fine delay control signal output for conveying a fine delay control signal corresponding to the fine delay control component; a tap delay line coupled to the data signal input and the coarse delay control signal output of the delay control, the tap delay line for imparting a coarse delay to the data signal by delaying the data signal in dependence on the coarse delay control signal, the tap delay line having an output for conveying the data signal after the data signal has been delayed by the coarse delay; a programmable digital delay line coupled to the fine delay control signal output of the delay control and to the digital clock reference, the programmable digital delay line generating a digital-to-analog converter clock delay signal in dependence on the fine delay control signal, the programmable digital delay line having an output; and a digital-to-analog converter coupled to the output of the tap delay line and the output of the programmable digital delay line for performing a digital-to-analog conversion on the data signal, wherein during the digital-to-analog conversion the data signal is further delayed by a fine delay corresponding to a portion of a whole clock cycle of the digital clock reference in dependence on the digital-to-analog clock converter delay signal, the digital-to-analog converter having an output for conveying the data signal to which has been imparted the coarse delay and the fine delay.