Patent ID: 8841726

Claim:
An intermediate wafer comprising: a substrate having a dielectric layer disposed thereon, the dielectric layer having a surface upon which a structure is disposed, the structure comprised of a fin formed from a patterned portion of a silicon on insulator (SOI) layer that is disposed upon and in contact with the surface of the dielectric layer, the fin having a top surface disposed at a height (h) above the surface of the dielectric layer; a first dummy gate plug disposed upon the top surface of the fin; a second dummy gate plug disposed upon the surface of the dielectric layer, where a top surface of the first dummy gate plug is disposed above a top surface of the second dummy gate plug by at least the height (h); a first layer in which the first dummy gate plug and the second dummy gate plug are embedded, the first layer having a surface exhibiting a non-planar surface topography characterized by a depression due at least to a presence of the first dummy gate plug that is disposed upon the top surface of the fin; a second layer comprised of a material that fills the depression in the surface of the first layer, the second layer having a first surface in contact with the surface of the first layer only within the depression, the second layer having a second surface that is substantially coplanar with the surface of the first layer; and a third layer overlying and in contact with the surface of the first layer and in contact with the second surface of the second layer, the third layer being comprised of a hard mask material, the third layer having a substantially planar surface topography over the first dummy gate plug, over the second dummy gate plug, and over the depression that is filled with the material of the second layer.