Patent ID: 8400837

Claim:
A semiconductor memory device comprising: memory cells capable of holding data; a memory cell array in which the memory cells are arranged; a word line connected to gates of the memory cells; a bit line electrically connected to drains of the memory cells; a source line electrically connected to sources of the memory cells; a row decoder which selects the word line; a sense amplifier which senses and amplifies data read onto the bit line in a read operation; a first MOS transistor which is capable of connecting a well region where the memory cells are formed with the source line and which is arranged between the row decoder or the sense amplifier and the memory cell array; a second MOS transistor which is capable of supplying a voltage to the well region; and third MOS transistors which are capable of supplying a voltage to the source line, wherein the sense amplifier includes a first region and a second region which faces the first region with the memory cell array between the first and second regions, the first MOS transistor is arranged between the second region and the memory cell array, the second MOS transistor is arranged between the first region and the memory cell array, and the third MOS transistors are arranged between the row decoder and the memory cell array.