Patent ID: 7142454

Claim:
A non-volatile memory device comprising: a plurality of nonvolatile memory cells arranged in a rectangular memory array having rows and columns, each said memory cell comprising a gate, a source, and a drain, wherein said memory cells are configured as a drain-source series wherein, within each said row said sources and said drains or each said memory cell are coupled to form a linear chain having a plurality of drain-source nodes, wherein each of said plurality of non-volatile memory cells comprises a uniform symmetric structure capable of storing two bits and wherein said plurality of memory cells are configured serially to form a NOR-AND (NAND) memory array or in parallel to form a NOR memory array, wherein a common word line is coupled to each said gate of said row; a plurality of column lines including at least a first, second, third, and fourth column line, wherein each column line is coupled a drain source node; logic for selecting a first column line from said plurality of column lines, and for coupling the selected first column line to ground; logic for selecting a second column line from said plurality of column lines, and for coupling a first voltage source to the selected second column line; logic for selecting a third column line from said plurality of column lines, and for coupling a second voltage source to the selected third column line, wherein said second voltage source and said first voltage source each comprise voltages that have substantially the same value and wherein said second voltage value effectively screens said first voltage source from parasitic resistances and from parasitic capacitances associated with said memory array; and logic for selecting a fourth column line, and for allowing the selected fourth column line to float, wherein said selecting logic comprises a four column Y decoder.