Patent ID: 7996654

Claim:
A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having four or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising: receiving an issue group of instructions; determining the dependency chain depth of all the instructions in the issue group; implementing a first prioritization by scheduling the instructions in an order of the longest dependency chain depth to shortest dependency chain depth, and implementing a second prioritization of the instructions scheduled according to the first prioritization based on a class type priority, the class type priority being prioritized in the following order: loads, floating-point/multiply/shift/rotate, ALU, store, compares, branches, and any remaining instructions; forming target dependencies of all instructions and instruction queues; prioritizing the target dependencies in an upper left most of an instruction queue ensemble; determining a number of pipeline bubbles in undelayed pipelines as from the target dependencies; shifting a pipeline number right until the number of pipeline bubbles becomes less than zero; and executing the issue group of instructions in the cascaded delayed execution pipeline unit; wherein the order of the instructions is scheduled in a shortest available execution pipeline to longest available execution pipeline.