Patent ID: 7136971

Claim:
A memory controller for a processing system, the processing system having a processor, a free-running clock, and a memory subsystem having at least one memory device, the memory controller comprising: a processor interface to communicate with the processor; a memory interface having circuitry compatible with a direct electrical connection to the at least one memory device, the memory interface including request and data interface portions, and wherein some of requests sent to the memory subsystem via the request interface include random accesses and some data exchanged with the memory subsystem via the data interface is synchronized to the free-running clock; sequential transfer circuitry coupled to the memory interface; and transaction processing logic coupled to the processor interface and the sequential transfer circuitry, and wherein randomly accessed data units of a first size are synchronously exchanged between the data interface and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.