Patent ID: 8514635

Claim:
A device comprising: a plurality of memory chips, each of the memory chips comprising: a memory cell array; an access control circuit responding to receipt of an access command and accessing the memory cell array to produce read data therefrom; a plurality of data terminals; a data output circuit coupled between the memory cell array and the data terminals; and an output timing adjustment circuit producing an output clock signal in response to adjustment data stored therein, the output clock signal causing the data output circuit to drive the data terminals so that output data based on the read data appear at the output terminals after a predetermined period of time from the receipt of the access command, the predetermined period of time being adjustable in accordance with the adjustment data; and a plurality of data paths, the memory chips being connected at the data output terminals in common to the data paths such that a selected one of the memory chips is allowed to transfer the output data to the data paths via the data terminals thereof; the output timing adjustment circuits of at least two of the memory chips being stored with different adjustment data from each other so that the at least two of the memory chips are approximately equal in the predetermined period of time to each other.