Patent ID: 8327089

Claim:
An electronic system comprising: a processor, which generates and sends one or more memory access requests; and multiple memory modules, operatively coupled together through a communications bus, which return data requested in the one or more memory access requests, wherein each of the multiple memory modules is a data source, and a memory module of the multiple memory modules is configured to: determine that first source data and second source data are available, allocate one or more first contiguous lanes within a first section of a data block to at least some of the first source data, wherein the data block comprises a set of multiple lanes, and each lane includes a set of configurable bits, allocate one or more second contiguous lanes within a second section of the data block to at least some of the second source data, wherein the second section begins at a next lane, which is contiguous with the first section, send over the communications bus and during a data block transmission period, the at least a portion of the first source data within the first section of the data block, and the at least a portion of the second source data within the second section of the data block; receive downstream data from a second memory module over the communications bus, wherein the downstream data is a selected one of the first source data and the second source data; receive local data from one or more memory storage units accessible to the memory module, wherein the local data is the selected one of the first source data and the second source data; and assemble the downstream data and the local data into the data block.