Patent ID: 8350356

Claim:
An integrated circuit apparatus, comprising: a semiconductor substrate, the substrate being characterized by a first conductivity type; a well region within the semiconductor substrate, the well region being characterized by a second conductivity type, a junction between the well region and the substrate being characterized by a breakdown voltage higher than a predetermined voltage; a plurality of isolation regions; a contact region within the well region, the contact region being characterized by the second conductivity type, the contact region being configured to receive a first supply voltage; a channel region within the substrate; a drain region, the drain region being characterized by the second conductivity type, the drain region being separated from the well region by the channel region; a gate dielectric layer overlying the channel region and the contact region; a first polysilicon gate overlying the gate dielectric layer which overlies the channel region, an edge of the first polysilicon gate overlying a portion of the well region, the first polysilicon gate, the drain region, and the well region being associated with a gate region, a drain region, and a source region, respectively, of an MOS transistor; and a second polysilicon gate overlying the gate dielectric layer which overlies the contact region, the second polysilicon gate being configured to receive a second supply voltage.