Patent ID: 8168475

Claim:
A method of fabricating a semiconductor package, comprising: forming a semiconductor chip comprising a top surface and a bottom surface, the bottom surface having a plurality of bumps formed thereon; forming redistribution layer patterns comprising first and second parts, the first parts facing the bumps and the second parts electrically connected to and spaced from the first parts; forming an organic insulating layer between the redistribution layer patterns and the semiconductor chip, the organic insulating layer having electrically conductive particles distributed in the organic insulating layer to directly contact the top surfaces of first parts of the redistribution layer patterns and the bottom surfaces of the bumps forming an encapsulation layer on the sacrificial substrate to surround the semiconductor chip on which the redistribution layer patterns are formed; and forming a patterned insulating layer below the exposed redistribution layer patterns, the patterned insulating layer exposing at least parts of the second parts of the redistribution layer patterns.