Patent ID: 8478964

Claim:
A system, comprising: a plurality of processors; and a plurality of dynamically configurable communication elements, wherein each of at least a portion of the dynamically configurable communication elements comprises a memory and a routing engine; wherein at least some of the processors and at least some of the dynamically configurable communication elements are coupled together in an interspersed arrangement; wherein a source device is configurable to transfer a data item through an intermediate subset of the dynamically configurable communication elements to a destination device; wherein the source device corresponds to a particular one of the processors, a particular one of the dynamically configurable communication elements, or an input/output device; wherein the destination device corresponds to a different one of the processors, a different one of the dynamically configurable communication elements, or a different input/output device; wherein, in response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device; wherein in response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.