Patent ID: 7170439

Claim:
A self-calibration circuit for capacitance mismatch, comprising: a sample-and-hold (S/H) circuit, comprising: a compensation capacitor array; a target capacitor; a reference capacitor; a comparator; and a switch control circuit; wherein the S/H circuit provides an output voltage, the output voltage is an operation result based on the capacitance of the target capacitor, of the reference capacitor, and the equivalent capacitance of the compensation capacitor array; the comparator provides a comparison signal according to whether the output voltage of the S/H circuit is positive or negative; the switch control circuit provides a compensation control signal to the compensation capacitor array to control the equivalent capacitance of the compensation capacitor array, and adjusts the compensation control signal according to the comparison signal for each cycle of a clock signal, such that the result of the target capacitance added to the equivalent capacitance of the compensation capacitor array gradually approximates the reference capacitance with each cycle of the clock signal.