Patent ID: 8335912

Claim:
An apparatus, comprising: a processor configured to execute a set of instructions including instructions specifying as operands registers in a set of logical registers, wherein the processor includes: a set of physical registers available as rename registers; a circuit configured to store information indicating a current mapping between a) registers in the set of logical registers that are specified by instructions being executed by the processor and b) registers in the set of physical registers, wherein the circuit is further configured to use the stored information to determine that a dependency exists between: a first floating-point instruction in an instruction stream of the processor specifying a first portion but not a second portion of a first of the set of logical registers as a destination; and a second, subsequent floating-point instruction in the instruction stream collectively specifying at least the first portion and the second portion of the first logical register as a source; wherein the circuit includes a plurality of storage locations, each of which is dedicated to one of the set of physical registers and is configured to store: first and second values respectively indicative of whether first and second portions of the physical register corresponding to that storage location include valid data for a logical register that has been renamed; and information indicative of whether the physical register corresponding to that storage location includes a) only one valid portion and b) the most recent update to the value of the logical register that has been renamed.