Patent ID: 8612657

Claim:
A method for communicating on an electrical bus between a master device and a slave device, the method comprising: generating a master logical signal on the electrical bus during a bit time, wherein said generating the master logical signal is performed by the master device, the master logical signal comprises a voltage pulse defined by an increase in voltage magnitude and a decrease in voltage magnitude on the electrical bus, and the time that the voltage on the electrical bus is at a level within the bit time is dependent on the logical value of the master logical signal; generating a slave logical signal on the electrical bus during the same bit time, wherein said generating the slave logical signal is performed by the slave device the slave logical signal comprises a current signal, and the magnitude of the current signal is dependent on the logical value of the slave logical signal; and reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus substantially at the same time as the increase in voltage magnitude when a logic generator is generating a first type of logical signal and at substantially the same time as the decrease in voltage magnitude when the logic generator is generating a second different type of logical signal.