Patent ID: 8704371

Claim:
A semiconductor die, comprising: a first contact stack, including: first die pad having a first pad perimeter, a first via through a dielectric layer to said first die pad having a first via perimeter, and a first under bump metal (UBM) pad contacting said first die pad through said first via having a first UBM pad perimeter; a second contact stack, including: a second die pad having a second pad perimeter shorter than said first pad perimeter, a second via through said dielectric layer to said second die pad having a second via perimeter shorter than said first via perimeter, and a second UBM pad contacting said second die pad through said second via having a second UBM pad perimeter that is shorter than said first UBM pad perimeter; a third contact stack, including: a third die pad having a third pad perimeter, a third via through said dielectric layer to said third die pad, and a third UBM pad contacting said third die pad through said third via having a third UBM pad perimeter that is longer than said second UBM pad perimeter; and a first solder bump on said first UBM pad, a second solder bump on said second UBM pad, and a third solder bump on said third UBM pad, wherein said first solder bump, said second solder bump and said third solder bump all have different sizes, wherein said semiconductor die is configured to pass a first current through a combination of said first die pad, said first via and said first UBM with a first current density below a predetermined threshold current density per perimeter length at said first pad perimeter, at said first via perimeter and at said first UBM pad perimeter, and a third current through a combination of said third die pad, said third via and said third UBM with a third current density below said predetermined threshold current density per perimeter length, at said third via perimeter and at said third UBM pad perimeter, wherein when said first current or said third current is passed through a combination of said second die pad, said second via and said second UBM said first current and said third current would have exceeded said predetermined threshold current density per perimeter length at said second pad perimeter, at said second via perimeter, and at said second UBM pad perimeter.