Patent ID: 7463525

Claim:
A method of operating a nonvolatile memory device having an array of cells arranged in a virtual ground architecture, each cell including a gate corresponding to a wordline in the array, a selectable source/drain corresponding to a bitline in the array, and a selectable drain/source corresponding to another bitline in the array, the method comprising: selecting a target cell in the array for reading; establishing a read voltage at the wordline corresponding to the target cell; establishing a drain bias voltage at a first selectable bitline corresponding to the drain of the target cell; grounding a second selectable bitline corresponding to the source of the target cell; establishing a negative gate bias voltage at unselected wordlines corresponding to unselected cells that share the first selectable bitline and the second selectable bitline; and adjusting the negative gate bias voltage in response to the age of the nonvolatile memory device.