Patent ID: 7528038

Claim:
Method for fabricating a nonvolatile semiconductor memory cell, the method comprising the following steps: a) formation of a first insulation layer ( 2 ), an electrically non-conductive charge storage layer ( 3 ), a second insulation layer ( 4 ) and a mask layer ( 5 ) on a substrate ( 1 ); b) patterning of the mask layer ( 5 ); c) formation of sidewall layers ( 6 ) at the patterned mask layer ( 5 ); d) removal of at least a first portion of the second insulation layer ( 4 ) and a first portion of the charge storage layer ( 3 ) using the patterned mask layer ( 5 ) and the sidewall layer ( 6 ); e) formation of source and drain regions ( 7 , 8 ) in the substrate ( 1 ); f) removal of the mask layer ( 5 ); g) removal of a second portion of the second insulation layer ( 4 ), a second portion of the charge storage layer ( 3 ) and a first portion of the first insulation layer ( 2 ) using the sidewall layers ( 6 ); h) removal of the sidewall layers ( 6 ); i) formation of a third insulation layer ( 9 ); j) formation of an electrically conductive control layer ( 10 ); k) patterning of the control layer ( 10 ) in order to form word lines (WL); and l) removal of the third insulation layer ( 9 ), a third portion of the second insulation layer ( 4 ), a third portion of the charge storage layer ( 3 ) and a second portion of the first insulation layer ( 2 ) using the patterned control layer ( 10 ) in order to form locally delimited memory locations (LB, RB).