Patent ID: 7274048

Claim:
An Electro Static Discharge (ESD) network for a semiconductor device, comprising: a chip having at least one ESD circuit in or on a surface of the chip; first and second contact pads connected to the ESD circuit; a substrate for mounting of the chip, the substrate having an interconnect metal layer; a third contact pad formed in or over an ESD layer of the substrate, the third contact pad being aligned with the first contact pad; a fourth contact pad formed in or over the ESD layer, the fourth contact pad being aligned with the second contact pad; and an ESD mesh formed over the ESD layer of the substrate; wherein the fourth contact pad is connected with the ESD mesh; and wherein the ESD layer comprises a modified layer of interconnect metal, the modified layer comprising, the third and fourth contact pads and the ESD mesh, wherein the fourth contact pad is connected to the ESD mesh.