Patent ID: 7319060

Claim:
A method of manufacturing a semiconductor device, comprising: forming a pair of first source/drain regions on a silicon substrate; forming an insulation layer pattern and a first silicon epitaxial layer pattern defining a gate forming region to expose the silicon substrate between the pair of first source/drain regions; forming a first gate insulation layer on the silicon substrate in the gate forming region; forming a second gate insulation layer on a sidewall of the first silicon epitaxial layer pattern; forming a second silicon epitaxial layer pattern in the gate forming region and on the first silicon epitaxial layer pattern; implanting impurities into a periphery of the second silicon epitaxial layer in the gate forming region to form a pair of second source/drain regions; partially etching the second silicon epitaxial layer in the gate forming region to form a second silicon epitaxial layer pattern; forming a third gate insulation layer that exposes a surface of the second silicon epitaxial layer pattern in the gate forming region and that covers lateral sides of the pair of second source/drain regions; and forming a gate on an exposed surface of the second silicon epitaxial layer pattern.