Patent ID: 6859869

Claim:
A massively parallel data processing apparatus comprising: a plurality of computing cells arranged in a multidimensional matrix, the plurality of computing cells capable of simultaneously manipulating a plurality of data, each of the plurality of computing cells including: an input interface for receiving a plurality of input signals, a plurality of logic members, at least one of the plurality of logic members coupled to the input interface, at least one coupling unit selectively coupling at least one of the plurality of logic members to another of the plurality of logic members as a function of at least one of a plurality of configuration signals to arithmetic-logically configure the computing cell prior to processing the input signals, wherein coupled logic members perform at least one select arithmetic-logic operation on the input signals to process the input signals, the at least one select arithmetic-logic operation being dependent on the at least one of the plurality of configuration signals, a register unit selectively storing a portion of the processed input signals, and an output interface for transmitting the processed input signals, wherein the input interface of at least one of the plurality of computing cells is selectively coupled to the output interface of at least another of the plurality of computing cells; and a configuration interface for transmitting the plurality of configuration signals to at least some of the plurality of computing cells to arithmetic-logically configure and arithmetic-logically reconfigure the at least some of the plurality of computing cells; wherein each the plurality of computing cells includes associated internal state information, each of the plurality of computing cells being configured to enable transfer of the state information to at least one other of the plurality of computing cells.