Patent ID: 7218174

Claim:
A delay circuit comprising: first and second differential transistors coupled as a differential pair; a first cascode transistor coupled to receive a signal from the first differential transistor, the first cascode transistor having a first current carrying electrode, a second current carrying electrode, and a control electrode; a second cascode transistor coupled to receive a signal from the second differential transistor, the second cascode transistor having a first current carrying electrode coupled to the control electrode of the first cascode transistor, a control electrode coupled to the first current carrying electrode of the first cascode transistor, and a second current carrying electrode a first emitter follower transistor coupled to receive a signal from the first cascode transistor, the first emitter follower transistor having a first current carrying electrode and a second current carrying electrode; and a second emitter follower transistor coupled to receive a signal from the second cascode transistor, the second emitter follower transistor having a first current carrying electrode and a second current carrying electrode.