Patent ID: 6911389

Claim:
A method for forming a conductive interconnect comprising a trench and a via to connect a conductive feature in a first metal level with a second metal level through a first and a second inter-level dielectric layer formed over the first metal level in a semiconductor device, the method comprising: forming the first inter-level dielectric layer over the first metal level; forming a buried via mask over the first inter-level dielectric layer with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive feature of the first metal level; forming the second inter-level dielectric layer over the via mask; forming a hard mask over the second inter-level dielectric layer with openings orthogonal to the underlying rectangular windows; removing an exposed portion of the second inter-level dielectric layer through to the buried via mask to form the trench, and removing the exposed portion of the first inter-level dielectric layer underlying the rectangular windows in the buried via mask to expose a portion of the conductive feature of the first metal level and to form a via cavity; and forming a conductive material over the semiconductor device so as to fill the trench and the via cavity created by the etch process, the conductive material forming the conductive interconnect providing electrical connection to the conductive feature.