Patent ID: 7698473

Claim:
An apparatus, comprising: a plurality of parallel processors, each capable of operative communication with a shared memory, each processor including a local memory that is adapted for execution of instructions therein, and each processor including a direct memory access controller (DMAC) coupled to the local memory of such processor and each DMAC operating to facilitate transfer of a plurality of data blocks between the shared memory and the local memory of such processor in response to a single, respective DMA command issued by such processor, wherein: each of the plurality of data blocks includes a respective number of data words, the respective number being equal to a respective, specified data block size, the single DMA command of a given transfer does not include any specified data block size information for any of the plurality of data blocks, each processor is operable to establish a list within the local memory thereof including a plurality of entries, each entry being identified by a respective one of the DMA commands, each entry having at least a starting address of a block of data to be transferred and a size of the data block to be transferred in response to such DMA command, and at least some of the entries of the list being linked such that the DMAC is operable to use one entry in the list to locate another entry in the list, and the DMAC is operable to use the starting address and the size specified in each entry identified by a respective one of the DMA commands to identify a corresponding data block for transfer, and to transfer such data block, between the shared memory and the local memory of the at least one processor.