Patent ID: 6853206

Claim:
A probe card configuration for testing a plurality of integrated circuits in parallel using a test system having electrical signal lines, the probe card configuration comprising: a carrier board for receiving said electrical signal lines of said test system, said carrier board defining a plane; contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested, said contact-making needles for connection with said electrical signal lines of said test system to produce signal paths between said test system and the integrated circuits to be tested; and a plurality of active modules configured on said carrier board, each one of said plurality of said active modules being assigned to one of the integrated circuits to be tested in parallel, each one of said plurality of said active modules being inserted into ones of the signal paths that are between said test system and the respective assigned one of the integrated circuits to be tested, each one of said plurality of said active modules having a longest extent; said longest extent of each one of said plurality of said active modules being configured non-parallel with said plane of said carrier board.