Patent ID: 6938183

Claim:
A satellite system 10 comprising: a ground station 14 ; a satellite 12 in operative communication with said ground station 14 , said satellite 12 including a fault tolerant processing circuit comprising: at least three processor groupings 20 each of said at least three processor groupings 20 having a plurality of processor grouping inputs and a plurality of processor grouping outputs; a synchronizing circuit 21 comprising a plurality of output synchronizers, each output synchronizer in operative communication with a corresponding respective processor grouping for synchronizing the output of each processor grouping; a fault logic circuit 22 in operative communication with said synchronizing circuit 21 , said fault logic circuit 22 comprising a fault detection circuit and a fault mask circuit, said fault logic circuit 22 adapted to compare said plurality of processor group outputs to detect errors in any one of said plurality of processor group outputs through selecting bits from said processor group outputs, wherein bit selection is generated as a function of whether a first one of said plurality of processor group outputs is synchronous or asynchronous and whether said first one of said plurality of processor group outputs is always valid or valid based on a state of a second one of said plurality of outputs; a control logic circuit for resetting each of said at least three processor groups when none of said at least three processor groups is in a majority of said processor groups, wherein said fault mask circuit is adapted to mask the output of a respective processor grouping associated with a detected error and signal a detected error; and a system bus coupled to each of said plurality of processor group inputs and said fault logic circuit output.