Patent ID: 8135910

Claim:
A method for improving the bandwidth of a cache directory comprising the steps of: receiving a first and a second address; reading a value in a bit in each of said first and said second address; determining which of a first and a second cache directory to search for said first and said second address based on said value read in said first and said second address; wherein said first cache directory is comprised of entries indicating data stored in a cache memory at addresses with a value of zero at said bit, wherein said second cache directory is comprised of entries indicating data stored in said cache memory at addresses with a value of a logical one at said bit; sending said first address to a first multiplexer by a first unit when said value read in both said first and said second address is zero and said second address is selected to be transmitted to a second unit on a bypass path, wherein said first unit is configured to shift a cycle speed to a lower speed, wherein said second unit is configured to shift said cycle speed to a higher speed.