Patent ID: 6876659

Claim:
A system for merging a plurality of connections that share a same class of service into a single virtual circuit (VC) connecting a first switching node to a second switching node in an Asynchronous Transfer Mode (ATM) network, said system comprising: a data buffer for storing cells that constitute a packet received by a switching node; a queuing apparatus comprising: a plurality of connection queues associated respectively with each of said plurality of connections; and a scheduled queue corresponding to a particular class of service, wherein contents of said plurality of connection queues are transferred into said scheduled queue before being transmitted on said VC; a reassembly queue control block (RQCB) associated with each of said plurality of connection queues, wherein said RQCB defines a chain of buffer control blocks, wherein each buffer control block corresponds to a cell belonging to a packet transmitted in a particular connection, and wherein said buffer control block includes a next buffer address in said data buffer and a lock bit that is normally set to 1 for an incoming cell and is set to 0 for an incoming cell only if said incoming cell is a last cell of said packet; and a scheduled queue control block (SQCB) associated with said scheduled queue to which said chain of buffer control blocks is transferred in response to a determination that said lock bit of a cell stored within said data buffer ms set to 0, wherein a corresponding buffer control block is chained to said chain of buffer control blocks in said SQCB without having been previously queued in said RQCB; and an aging mechanism that is periodically activated for discarding cells that are currently engueued in a queue associated with said RQCB in response to no cell having been enqueued in said RQCB during a predetermined period of time.