Patent ID: 8487442

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first wiring layer formed on the semiconductor substrate such that an insulating film in the first wiring layer includes a film selected from a porous insulating film, SiOCH, ladder-type hydrogenated siloxane, hydrogensilsesquioxane (HSQ), methylsilsesquioxane (MSQ), methylhydrogensilsesquioxane (MHSQ), and divinylsiloxane-bis-benzocyclobutene (BCB), the first wiring layer comprising a first via having a first aspect ratio and a first wire having a second aspect ratio, the first via and the first wire comprising a dual damascene structure comprising a porous insulating film, the first wiring layer further including a second via and a second wire, the second via and the second wire comprising the dual damascene structure, the first wire and the second wire being arranged separately in a first direction such that a width, in the first direction, of the second wire is greater than a width, in the first direction, of the first wire, the second wire provided on the second via and including a taper portion being tapered at an aperture thereof, in a cross sectional view, in a via depth direction such that a tapering angle of the taper portion of the second wire is greater than a tapering angle of a taper portion of the first wire provided on the first via, and the first aspect ratio being equal to or smaller than the second aspect ratio such that a tapered portion of the first via is included in the second aspect ratio; and a second wiring layer overlying the first wiring layer, the second wiring layer comprising a third via having a third aspect ratio and a third wire having a fourth aspect ratio, the third via and the third wire comprising the dual damascene structure, and the third aspect ratio being larger than the fourth aspect ratio.