Patent ID: 8607000

Claim:
A data processing system comprising: a central processing unit executing program instructions to manipulate data; at least one first level cache connected to said central processing unit temporarily storing in a plurality of cache lines at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit, said at least one first level cache having a cache line size of less than or equal to N bits; and a second level cache connected to said first level cache temporarily storing in a plurality of cache lines at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit, said second level cache having a cache line size of 2N bits; and a cache operation unit connected to said at least one first level cache and said second level cache operable upon a cache miss in said at least one first level cache and a cache miss in said second level cache in response to a request from said central processing unit at a generated address, said cache operation unit operable to evict and allocate a cache line within said second level cache to store a cache line including said central processing unit generated address, determine from said central processing unit generated address whether said request of said central processing unit falls within a low half or a high half of said allocated cache line within said second level cache, if said request of said central processing unit falls within said low half of said allocated cache line within said second level cache (1) requesting a first N bits from an external memory corresponding to said low half of said allocated cache line within said second level cache, (2) upon receipt of said first N bits, supplying at least a subset of said N bits to said at least one first level cache and storing said first N bits in said low half of said allocated cache line within said second level cache, (3) requesting a second N bits from the external memory corresponding to said high half of said allocated cache line, (4) upon receipt of said second N bits, storing said second N bits in said high half of said allocated cache line within said second level cache, and if said request of said central processing unit falls within said high half of said allocated cache line within said second level cache (1) requesting a first N bits from an external memory corresponding to said high half of said allocated cache line within said second level cache, (2) upon receipt of said first N bits, supplying at least a subset of said N bits to said at least one first level cache and storing said first N bits in said high half of said allocated cache line within said second level cache, (3) requesting a second N bits from the external memory corresponding to said low half of said allocated cache line within said second level cache, (4) upon receipt of said second N bits, storing said second N bits in said low half of said allocated cache line within said second level cache.