Patent ID: 7024445

Claim:
A partial product bit generator circuit for use in performing multiplication to generate a product of a multiplicand and a multiplier, the multiplicand being represented by a digital signal having a plurality of bits, the multiplier being represented by a digital signal having a plurality of bits, the partial product bit generator circuit receiving a group of the multiplicand bits and a group of the multiplier bits and providing a partial product bit in response thereto, wherein the partial product bit generator circuit comprises less than six levels of combinatorial logic and further comprises: a first circuit, responsive to a group of the multiplicand bits and a first subset of a group of the multiplier bits, to output at least three digital signals; a second circuit, responsive to a second subset of the group of multiplier bits, to output at least three select signals, each of the at least three select signals being associated with a respective one of the at least three digital signals, only one of the at least three select signals having a logic state that is asserted; and a third circuit, to output a partial product bit in response to the digital signal that is associated with the select signal having the asserted logic state.