Patent ID: 8754410

Claim:
An array substrate comprising: a gate line on a substrate including a pixel region, the gate line extending in one direction; a gate electrode in the pixel region and extending from the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode; an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer; a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; and a drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode, wherein overlap area of the source electrode and the two ends of the three ends of the oxide semiconductor layer is smaller than the source electrode area, and overlap area of the drain electrode and the two ends of the three ends of the oxide semiconductor layer is smaller than the drain electrode area.