Patent ID: 7274086

Claim:
A memory assembly, comprising: a memory package having a plurality of interconnect pins; a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship; and a memory chip coupled to the plurality of leads, wherein the memory chip comprises: a substrate; a memory device fabricated on the substrate; and a plurality of chip bond pads fabricated on the substrate and coupled to the memory device; wherein at least two leads originate from a same side of the leadframe and each have terminations in multiple quadrants of the substrate and are each coupled to at least two chip bond pads located in those multiple quadrants of the substrate; wherein a first lead is coupled to chip bond pads located in a first quadrant and a fourth quadrant of the substrate, a second lead is coupled to chip bond pads located in the first quadrant and a third quadrant of the substrate, a third lead is coupled to chip bond pads in a second quadrant and the third quadrant of the substrate, and a fourth les is coupled to chip bond pads located in the first quadrant and the third quadrant of the substrate.