Patent ID: 7193260

Claim:
A semiconductor memory device comprising: a first bit line extending in a first direction; a second bit line extending in the first direction and provided separate from the first bit line; a first memory cell block including a first terminal connected to the first bit line by a first block select transistor, a second terminal, and a plurality of first memory cells connected in series between the first and second terminals in the first direction, each first memory cell including a first capacitor and a first cell transistor, which are connected in parallel, the first capacitor including a first lower electrode and a first upper electrode; a second memory cell block including a third terminal connected to the second bit line by a second block select transistor, a fourth terminal, and a plurality of second memory cells connected in series between the third and fourth terminals in the first direction, each second memory cell including a second capacitor and a second cell transistor, which are connected in parallel, the second capacitor including a second lower electrode and a second upper electrode and provided adjacent to the first capacitor in a second direction perpendicular to the first direction; a plurality of first wiring portions provided for first pairs of adjacent first capacitors, respectively, each first wiring portion electrically connecting, to each other, two first upper electrodes of the adjacent first capacitors; a plurality of second wiring portions provided for second pairs of adjacent second capacitors, respectively, each second wiring portion electrically connecting, to each other, two second upper electrodes of the adjacent second capacitors, the second pairs being provided adjacent to the first pairs in the second direction, respectively; a plurality of first contacts electrically connected to the first wiring portions and provided between the first capacitor and the second capacitor, each first contact being located on one side with respect to a line formed by connecting a first midpoint and a second midpoint, the first midpoint existing between the two first upper electrodes, and the second midpoint existing between the two second upper electrodes; and a plurality of second contacts electrically connected to the second wiring portions and provided between the first capacitor and the second capacitor, each second contact being located opposite a respective first contact on the other side with respect to the line.