Patent ID: 7239174

Claim:
A layout of a programmable interconnect structure of an integrated circuit, comprising: a first substantially rectangular semiconductor active region comprising a first direction and a second direction; and 2M gate regions where M is an integer greater than one, each gate region traversing the entire length of the first active region in the first direction, said 2M gate regions dividing the active region into (2M+1) active stripes sequentially numbered from one to (2M+1) in said second direction; and M wires in the interconnect structure, each wire coupled to at least one contact in the 2P numbered active area stripe for every integer P from one to M; and an input wire coupled to at least one contact in each of the active area stripes starting from stripe one and incrementing in four not exceeding stripe (2M+1); and an output wire coupled to at least one contact in each of the active area stripes starting from stripe three and incrementing in four not exceeding stripe (2M+1); and a buffer layout comprising one or more buffer gate regions and one or more buffer active regions; wherein, the input wire is coupled to a said buffer gate region and the output wire is coupled a said buffer active region.