Patent ID: 6859108

Claim:
A phase locked loop (PLL) circuit, wherein a voltage controlled oscillator is adjusted to generate an output frequency signal which is a selected multiple of an input reference signal, said PLL comprising: an oscillator control circuit for increasing and decreasing said output frequency signal; a phase and frequency detector for detecting a phase shift and a frequency shift between said reference signal and said output signal and producing an error signal; a bias generator responsive based on said error signal such that in a first mode of operation, a first bias current is generated, and in a second mode of operation, a second bias current is generated, wherein the first bias current is used to operate said voltage controlled oscillator in a first current range, including a first current value and a second current value, the first current value being greater than the second current value, and the second bias current is used to operate said voltage controlled oscillator in a second current range including a third current value and a fourth current value, the third current value being greater than the fourth current value, and further wherein the first current range overlaps the second current range, the first current value is outside the second current range, and the fourth current value is outside the first current range.