Patent ID: 8637918

Claim:
A memory, comprising: a substrate; one or more core memory cells that each include: a charge trapping component located on a portion of the substrate, wherein the charge trapping component includes a charge trapping layer; and a portion of a word line residing on a portion of the charge trapping component, wherein the word line includes a portion of a core polysilicon layer; and one or more peripheral devices residing on another portion of the substrate, wherein the peripheral devices include a portion of a peripheral polysilicon layer, wherein the peripheral polysilicon layer is thicker than the core polysilicon layer, wherein the portion of the core polysilicon layer has a different line profile than the portion of the peripheral polysilicon layer, and wherein a height of the one or more core memory cells relative to a surface of the substate is different from a height of the one or more peripheral devices relative to surface of the substrate.