Patent ID: 6897110

Claim:
A method of fabricating a memory array, comprising: a) partially forming said memory array during a first formation stage comprising: i) forming a plurality of bitlines in a substrate, wherein said bitlines comprise source/drain regions of memory cells; ii) forming a plurality of data storage regions above said bitlines; iii) forming a plurality of wordlines above said data storage regions, wherein said wordlines comprise gate regions of said memory cells; iv) forming a first metal region above a first of said bitlines and coupled to said first bitline; and v) forming a second metal region that is not electrically coupled to said first metal region, wherein an antenna ratio between said first of said bitlines and said first metal region is lower than if said first and second metal regions were electrically coupled; and b) forming an electrical coupling between said first metal region to said second metal region after said first formation stage, wherein said second metal region does not contribute to charge damage to said data storage regions during said first formation stage.