Patent ID: 7449788

Claim:
A chip structure with an arrangement of side pads suitable for wire bonding connection, the chip structure comprising: a substrate having an active surface; and at least an arrangement of side pads disposed on the active surface adjacent to one side of the active surface, the arrangement of side pads includes at least: an outer pad row having a plurality of outer pads disposed along the extension direction of the side, wherein the outer pads includes a plurality of outer non-signal pads; a middle pad row disposed further away from the side of the active surface than the outer pad row and having a plurality of middle pads disposed along the extension direction of the side, wherein the middle pads includes a plurality of first signal pads and a plurality of first non-signal pads, and one side of each of the first signal pads is adjacent to one of the first non-signal pads; and an inner pad row disposed further away from the side than the middle pad row and having a plurality of inner pads disposed along the extension direction of the side, wherein the inner pads includes a plurality of second signal pads and a plurality of second non-signal pads, and one side of each second signal pad is adjacent to one of the second non-signal pads, wherein the middle pads in the middle pad row and the inner pads in the inner pad row are staggered such that each of the first signal pads is adjacent to one of the second non-signal pads and each of the second signal pads is adjacent to one of the first non-signal pads.