Patent ID: 8675006

Claim:
A data processing apparatus comprising: a central processing unit (CPU) for executing a stream of instructions; a graphics processing unit (GPU) for performing graphics processing operations on behalf of the CPU; shared memory accessible by the CPU and the GPU via which data structures are shareable between the CPU and the GPU; a bus via which the CPU, GPU and shared memory communicate, the CPU routing control signals via the bus as a first mechanism for controlling the GPU; and an interface between the CPU and the GPU, the CPU providing control signals over the interface as an additional mechanism for controlling the GPU, said GPU including a scheduler for controlling a shader pipeline of the GPU to perform said graphic processing operations, said interface providing a control path via which the control signals issued by the CPU are directly injected into the scheduler of the GPU when using said additional mechanism, in order to cause processing operations defined by those control signals to be scheduled for execution within the shader pipeline, wherein said CPU is configured to use: said first mechanism to control the GPU to perform graphics processing operations which are loosely coupled with operations performed by the CPU; and said additional mechanism to control the GPU to perform processing operations which are tightly coupled with operations performed by the CPU.