Patent ID: 8422340

Claim:
A method for determining a timestamp for a signal timing edge of a signal, said method comprising the steps of: (a) providing a timer clock signal having a tinier clock period; (b) inputting said signal into a tapped delay line comprising a plurality of delay line taps in series, each of said plurality of delay line taps delaying said signal by a delay line tap time delay less than said timer clock period; (c) producing a plurality of delay line tap signals at the output of said plurality of delay line taps, wherein each of said delay line tap signals is said signal delayed by the sum of said delay line tap time delays of the preceding delay line taps in series; (d) detecting said signal timing edge; (e) detecting the next clock timing edge after said signal timing edge; (f) determining an initial time value corresponding to the timer clock cycle count at said signal timing edge or at said next clock timing edge; (g) determining the state of said tapped delay line at said next clock timing edge by determining the number of delay line tap signal timing edges that occur before said next clock timing edge; (h) determining a fractional correction time value based on said state of said tapped delay line to account for the delay between said signal timing edge and said next clock edge, wherein said fractional correction time value is a fraction of said timer clock period based on said sum of said delay line tap time delays experienced by the last of said plurality of delay line signals to have a delay line tap signal timing edge that occurs before said next clock timing edge; and (i) determining said timestamp for said signal timing edge by adjusting said initial time value by said fractional correction time value.