Patent ID: 7214587

Claim:
A method for fabricating a nonvolatile semiconductor memory cell including a selection transistor and a memory element with a solid electrolyte storage mechanism, the method comprising: forming in a surface region of a semiconductor material, source, drain, and channel regions of a field effect transistor to serve as the selection transistor; forming a sacrificial material over the surface region of the semiconductor material with a cutout in the vicinity of the channel region, the cutout being bounded by a wall region and being substantially free of the sacrificial material; forming in the cutout a gate insulation layer, a first electrode layer, a solid electrolyte layer, a second electrode layer, and a third electrode layer such that a top surface of the third electrode layer is below a top surface of the sacrificial material, wherein corresponding layers are formed on the top surface of the sacrificial material, and wherein the gate insulation layer serves as a gate insulator region of the field effect transistor, at least a portion of the first electrode layer serves as a gate electrode of the field effect transistor, at least a portion of the first electrode layer serves as a first electrode of the memory element, at least a portion of the second electrode layer serves as a second electrode of the memory element, and at least a portion of the third electrode serves as a control gate electrode of the field effect transistor; and removing the corresponding layers formed on the sacrificial material and removing the sacrificial material.