Patent ID: 7315970

Claim:
A semiconductor device having a memory circuit including a dynamic memory cell and performing a refresh operation for retaining data of said memory circuit in a standby mode, comprising: a system block for outputting a start signal and a mode selection signal indicating a parity generation mode before entering in the standby mode, entering in the standby mode when receiving an end signal after a first predetermined time and performing the refresh operation with respect to said memory circuit, then outputting a start signal and a mode selection signal indicating an error correction mode, and entering in a normal mode when receiving the end signal after a second predetermined time; a pattern generating circuit for receiving said start signal and said mode selection signal indicating said parity generation mode, and said start signal and said mode selection signal indicating said error correction mode to generate commands and addresses with respect to said memory circuit with the predetermined pattern in accordance with a mode, and outputting said end signal when the parity generating operation is finished in each mode; an error correcting circuit for receiving said start signal and said mode selection signal indicating said parity generation mode to generate a parity based on data read from said memory circuit, receiving said start signal and said mode selection signal indicating said error correction mode to perform an error correcting operation based on a parity generated with respect to data read from said memory circuit in said parity generation mode, and outputting data after error correcting; and an interface circuit for inputting said start signal and said mode selection signal indicating said parity generation mode, and said start signal and said mode selection signal indicating said error correction mode by said system block to said pattern generating circuit and said error correction circuit, supplying the commands and addresses by said pattern generating circuit to said memory circuit, inputting data read from said memory circuit to said error correcting circuit, and outputting data after an error correction mode processing by said error correction circuit to said memory circuit.