Patent ID: 7340546

Claim:
A node comprising: locations within the node in which the locations are addressed with addresses associated with a local region of the node and also addressed with addresses associated with a separate second region of the node that is aliased with the local region, in which a selected number of lower significant bits of the addresses associated with the locations in the local region to a respective same lower significant bits of the addresses associated with the locations in the second region; and a register programmable to store a value during use to configure the node, wherein the node is identified by a set of most significant bits of the addresses associated with the second region to indicate that the second region is aliased with the local region, and wherein the second region has global addressing for internode access; wherein when an agent in the node performs an access to a particular global address in the second region, respective aliased location in the local region is accessed and if the respective aliased location in the local region corresponds to an input/output or interface device within the node or corresponds to a memory location that does not require coherency, the access is performed locally through the local region, but if the respective aliased location in the local region corresponds to a memory location requiring coherency, the access is performed through the second region by generating a global coherent transaction through the second region, and wherein an access from another node to access the particular global address in the second region is performed locally through the respective aliased location if an agent of the another node has ownership of the respective aliased location in the local region, but if the agent of the another node does not have ownership of the respective aliased location, a global coherent transaction is generated to access the particular global address, in which accesses through the local region and through the second region use the same respective lower significant bits of an address to access the locations in the local region and the second region.