Patent ID: 7180115

Claim:
A circuit, comprising: at least one vertical transistor having a first source/drain region, a channel region arranged above the first source/drain region and adjoining the first source/drain region, a second source/drain region, arranged above the channel, a gate dielectric and a gate electrode; exactly one tunnel barrier layer arranged such that the second source/drain region is separated from the channel region only by the exactly one tunnel barrier layer; at least one capacitor having a first capacitor electrode arranged below the channel in a manner to be vertically opposite to the second source/drain region and connected to the first source/drain region by means of a conductive structure; and an insulating structure including the exactly one tunneling barrier layer, a capacitor dielectric and an insulation layer, the insulation layer being arranged above the first electrode in a manner to be vertically between the channel and the first electrode, whereby the insulating structure surrounds a portion of the at least one vertical transistor and the at least one capacitor and defining an insulating region, with at least the first capacitor electrode and the first source/drain region arranged in the insulating region, and at least the second source/drain region and a second capacitor electrode of the capacitor arranged outside the insulating region, the exactly one tunneling barrier layer arranged between the channel region and the second source/drain region, the gate electrode surrounds the channel region in such a way that the tunneling barrier is controllable, and the capacitor dielectric isolates the first capacitor electrode from the second capacitor electrode, and the conductive structure adjoining the side wall of the insulating layer.