Patent ID: 8122315

Claim:
A low-density parity-check (LDPC) decoding apparatus using a structuralized parity check matrix, comprising: a memory allocating means for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory blocks; an index storing means for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating means for bringing the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node in parallel; and a bit node updating means for updating a bit node based on the data stored in the memory and check node information updated in the check node updating means, wherein: the number of memory blocks are increased as many as the number of ROMs in order to allocate information data; the multiplied value is stored in the memory blocks in an order; the check node updating means and the bit node updating means sequentially update the memory blocks when each of the memory blocks includes a plurality of data symbols; and the check node updating means and the bit node updating means simultaneously update as many as the number of row weights by part parallel according to the data symbols when the date symbols are divided into the data blocks.