Patent ID: 8633535

Claim:
A nonvolatile semiconductor memory comprising: a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; control gates provided in an array form in a first direction in parallel with a surface of the semiconductor substrate and in a second direction perpendicular thereto, the control gates passing through the first semiconductor layer in a third direction perpendicular to the first and second directions; data recording layers between the first semiconductor layer and the control gates; two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer; two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer; select gate lines extending in the first direction on the first semiconductor layer; and word lines extending in the second direction on the select gate lines, wherein the select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction, each of the word lines is commonly connected to the control gates arranged in the second direction, a first memory cell array comprises the first semiconductor layer, the control gates, and the data recording layers therebetween, and the first memory cell array has NAND series including memory cells connected in series in the first direction.