Patent ID: 7443333

Claim:
A converter adapted to convert an analog input signal into a digital output signal, comprising: an analog input terminal for receiving the analog input signal; a Redundant Signed Digit (RSD) stage coupled to the analog input terminal, said RSD stage configured to: receive the analog input signal at the analog input terminal; produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle; provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle; and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits; and a digital section coupled to the digital output, the digital section configured to perform a digital alignment and correction on the first number of bits and the second number of bits to generate the digital output signal.