Patent ID: 7131114

Claim:
A host system used to debug a multi-core processor including a shared program memory into which program instructions are stored, comprising: a CPU; volatile memory coupled to said CPU used to store a plurality of instruction entries, each entry comprising an instruction, an address of said instruction, and a flag indicating a core associated with said instruction; wherein said host: receives status information regarding a core in the multicore processor that has halted execution due to encountering a breakpoint instruction in the shared program memory, the status information includes the address of the breakpoint instruction from the shared program memory; compares said address of the breakpoint instruction to addresses stored in said volatile memory associated with the halted core; if said address of the breakpoint instruction matches an address stored in said volatile memory associated with the halted core, the host performs a debugging operation on the halted core; and if said address of the breakpoint instruction does not match an address stored in said volatile memory associated with the halted core, the host overwrites the breakpoint instruction in the shared program memory with a program instruction from an instruction entry in said volatile memory matching said address of the breakpoint instruction, single steps the halted core to execute said program instruction, overwrites the program instruction with the breakpoint instruction and places the halted core in a normal execution mode to execute following instructions.