Patent ID: 7211356

Claim:
A method of patterning a substrate, comprising: fabricating a first mask, said first mask including a plurality of first features usable to pattern a plurality of regular elements and a plurality of redundancy elements of at least one of a microelectronic substrate or micro-electromechanical substrate; testing said first mask to detect one or more defects in said plurality of first features; fabricating a second mask, said second mask including a plurality of second features usable to pattern a plurality of interconnections, said plurality of interconnections including interconnections between individual ones of said plurality of regular elements and interconnections between said plurality of regular elements and said plurality of redundancy elements; patterning said regular elements and said redundancy elements of said substrate using said first mask; patterning said plurality of interconnections of said substrate using said second mask; and altering said plurality of interconnections of said substrate to correct for said detected defects in said first mask.