Patent ID: 8055966

Claim:
A multiple integrated circuit arrangement within a single package, said multiple integrated circuit arrangement including a set of electronic components, said set of electronic components including at least a set of dies, said set of dies including at least a first die and a second die, wherein said first die is coupled to a first electronic component of said set of electronic components, and wherein said first electronic component is not said first die, said multiple integrated circuit arrangement comprising: a switch coupled to at least a power supply arrangement, said first die, and said second die; a built-in-self-test (BIST) arrangement, said BIST arrangement being at least partly encapsulated within said single package, said BIST arrangement including at least a BIST die, said BIST die being coupled to said switch, said BIST die being configured to send a first control signal to said switch, said first control signal instructing said switch to power said first die and to stop powering said second die, wherein said BIST arrangement is configured for at least testing said first die; and a built-in-self-repair (BISR) arrangement, said BISR arrangement being at least partly encapsulated within said single package, wherein said BISR arrangement is configured for at least repairing said multiple integrated circuit arrangement.