Patent ID: 7187218

Claim:
A reset generator circuit for generating a reset signal, comprising: an oscillator circuit configured to output a clock signal to an output thereof; a delay circuit comprising a clock signal input connected to the output of the oscillator circuit, the delay circuit further comprising a signal output and a control input, and configured to be activated by a control signal at the control input, and output a first signal state after a first predetermined time period, and output a second signal state after a second predetermined time period after outputting the first signal state; a generator circuit comprising a signal input coupled to the signal output of the delay circuit, and a reset signal output, and configured to be activated by the control signal at a control input thereof, and further configured to output a reset signal in the event of a detection of the first signal state at the signal input thereof until a detection of the second signal state at the signal input of the generator circuit; and a comparison device configured to compare a supply potential with a potential threshold value and output the control signal to a signal output thereof when the supply potential exceeds the potential threshold value, wherein the signal output thereof is connected to the control input of the delay circuit and the control input of the generator circuit, wherein the generator circuit is further configured to output a turn-off signal to a second output thereof after the detection of the second signal state at the signal input, and the second output is coupled to a control input of the oscillator circuit, wherein the oscillator circuit is turned off in response to the turn-off signal at the control input.