Patent ID: 8055977

Claim:
A decoder for decoding an encoded data string comprising error correction code words and a parity bit that is created for a predetermined number of bits of error correcting code words, the error correction code words comprising data string and a parity of the error correcting code that is generated from data string of each block of which the data string is interleaved into n (n≧2) blocks at every m (m≧2) bits, the decoder comprising: a soft output decoder for decoding the encoded data string that is received to a code bit string and outputting the code bit string and the likelihood of each bit; and an ECC decoding circuit for repeating an error correction decoding using an error correcting code of the code bit string from the soft output decoder, and a correction decoding of the code bit string based on the likelihood according to the error detection using the parity bit, wherein the ECC decoding circuit comprises: an ECC decoder for performing error correction using the error correcting code of the code bit string of the soft output decoder; and a parity/likelihood correction unit for performing an error detection using the parity bit according to a failure of the decoding of the ECC decoder, and correcting the code bit string that is input to the ECC decoder depending on the likelihood according to the error detection result.