Patent ID: 7663634

Claim:
A drawing processing apparatus for performing multipass rendering in which drawing processing on a drawing object is divided into and processed in a plurality of operation passes, comprising: a pipeline processing mechanism having a plurality of arithmetic processing parts which process the drawing object in units of processing of respective different granularities, the arithmetic processing parts constituting a plurality of pipeline stages in descending order of processing granularities, wherein at least one of the arithmetic processing parts includes a delimiter sending part that (a) generates delimiters indicating the divisions between the units of processing of the arithmetic processing part at the prior stage in the granularity of the unit of processing of the current arithmetic processing part and sends the generated delimiters to the delimiter sending part of the subsequent arithmetic processing part, and (b) changes the granularity of the delimiters received from the delimiter sending part at the prior stage and sends the delimiters to the delimiter sending unit of the arithmetic processing part of the subsequent stage, wherein the arithmetic processing part at the final stage (a) generates determination flags for determining, in the processing granularity of the arithmetic processing part at the final stage, whether or not the respective units of processing are targeted for arithmetic processing in a subsequent operation pass; (b) binds up the determination flags based on the delimiters indicating the divisions of units of processing at respective stages, thereby generating bind flags for indicating, in the processing granularities of the arithmetic processing parts in the respective stages, whether or not the individual units of processing are targeted for arithmetic processing in a subsequent operation pass; and (c) supplies the bind flags to the arithmetic processing parts in the respective stages; and each of the arithmetic processing parts: acquires the bind flag bound into the processing granularity of that arithmetic processing part, and in the subsequent operation pass, performs the arithmetic processing on only the unit of processing targeted for the arithmetic processing with reference to the flag, and supplies data resulting from the arithmetic processing to the arithmetic processing part in the subsequent stage.