Patent ID: 7910471

Claim:
A method for fabricating a semiconductor assembly comprising the steps of: providing a semiconductor chip having a planar active surface including an integrated circuit, said integrated circuit having a metallization pattern including at least one contact pad at said planar active surface; providing a protective overcoat over said planar active surface, said protective overcoat including windows exposing said at least one contact pad, said window having sidewalls; providing an added conductive region having at least one conductive layer on said metallization pattern covering and conformal to said at least one contact pad, said sidewalls of said window and a portion of said protective overcoat surrounding said window, said added conductive region having a planar outer surface, said outer surface of said added conductive region suitable to form metallurgical bonds without melting; providing a assembly board having at least one planar, metallurgically bondable terminal pad in a distribution aligned with the distribution of said at least one contact pad; aligning said added conductive region and said at least one terminal pad so that said at least one contact pad is connected to a corresponding terminal pad; and metallurgically bonding said added conductive region and said at least one terminal pad without melting said outer surface of said added conductive region.