Patent ID: 8023320

Claim:
A resistance-change random access memory device, comprising: a resistance-change memory cell array that includes a plurality of resistance-change memory cells arranged in memory cell blocks; a plurality of word lines connected to respective first terminals of the plurality of resistance-change memory cells; a plurality of bit lines disposed perpendicular to the word lines and are connected to respective second terminals of the plurality of resistance-change memory cells, the plurality of word lines and the plurality of bit lines being configured to select resistance-change memory cells for write and read operations; and a plurality of discharge elements configured to connect and disconnect respective bit lines from a discharge voltage in response to a discharge control signal, wherein, when the discharge control signal is set to an enabled state before write and read operations, the discharge elements connect the respective bit lines of resistance-change memory cells in a selected memory cell block to the discharge voltage and the discharge elements float respective bit lines of resistance-change memory cells in a non-selected memory cell block.