Patent ID: 7751272

Claim:
A memory device for use in an arrangement of memory devices interconnected in series, the memory device comprising: a first input for receiving a command input signal containing a command having an identification number; a second input for receiving a first strobe signal indicating the start of the command; a third input for receiving clock input; a fourth input for receiving a second strobe signal, and logic circuitry configured to: de-select the memory device in response to the first strobe signal to place the memory device in a de-selected state; determine whether the identification number of the command matches a device address associated with the memory device; in response to a determination result, place the memory device in a selected state, forward the command input signal and the first strobe signal with a delay related to clock cycle latency while the memory device is in the de-selected state; refrain from for warding the command input signal and the first strobe signal while the memory device is in the selected state; and forward the second strobe signal with a delay related to a latency that is substantially equal to the latency of a delayed version of the first strobe signal, the second strobe signal containing data enabling data output from the memory device in the selected state.