Patent ID: 7790483

Claim:
A manufacturing method of a thin film transistor comprising the steps of: forming a first conductive film; forming an insulating film over the first conductive film; forming a semiconductor film over the insulating film; forming an impurity semiconductor film over the semiconductor film; forming a second conductive film over the impurity semiconductor film; forming a first resist mask over the second conductive film, the first resist mask including a first region, a second region whose thickness is larger than the thickness of the first region, and a third region whose thickness is larger than the thickness of the second region; performing first etching on the insulating film, the semiconductor film, the impurity semiconductor film, and the second conductive film using the first resist mask to expose at least a surface of the first conductive film; performing second etching in which side-etching is performed on a part of the first conductive film to form a gate electrode layer; forming a second resist mask by recessing the first resist mask to expose the second conductive film; performing third etching on the insulating film, the semiconductor film, the impurity semiconductor film, and the second conductive film using the second resist mask to remove the insulating film, the semiconductor film, the impurity semiconductor film, and the second conductive film; forming a third resist mask by recessing the second resist mask to expose the second conductive film; and performing fourth etching on a part of the semiconductor film, the impurity semiconductor film, and the second conductive film using the third resist mask to remove the part of the semiconductor film, the impurity semiconductor film, and the second conductive film, and to form a source electrode layer, a drain electrode layer, a source region and a drain region.