Patent ID: 8294238

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array area; and a peripheral circuit area formed around the memory cell array area, wherein the peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistors formed in the element regions respectively, each of the field-effect transistors including a gate electrode extending in a channel width direction, and an end portion and a corner portion of the gate electrode in the channel width direction projects from the element region, and are disposed on the element isolation region, and further, the element isolation region has a recess extends in a channel length direction orthogonal to the channel width direction and between the gate electrodes of the field-effect transistors, the gate electrodes are adjacent to each other in the channel width direction, and wherein the recess not located between the gate electrodes is deeper than the recess located between the gate electrodes.