Patent ID: 8665996

Claim:
A circuit comprising: a plurality of decoders, wherein each decoder can be assigned tasks of decoding a sequence of one or more sub-packets of a group of packets, wherein said each decoder generates a packet done indication if the decoder has completed all the assigned tasks of decoding all the sub-packets of a packet; and a control circuit that receives the packet done indication from each of the plurality of decoders and based at least in part on the packet done indications asserts an interrupt signal, wherein the interrupt signal is not asserted during a time that any decoder is decoding a sub-packet of the packet but rather is asserted only after a packet done indication has been received from every decoder that decoded any sub-packet of the packet, wherein the packet done indication includes a done signal and an end-of-packet signal, wherein the done signal and the end-of-packet signal are present on at least one conductor extending from a decoder and into the control circuit.