Patent ID: 7759986

Claim:
An integrated circuit comprising: a first input node and a second input node; an output node; a first output transistor of a first type and a second output transistor of a second type; and a first clamping transistor of the second type and a second clamping transistor of the second type, wherein the first type can be a PMOS or an NMOS and the second type can respectively be an NMOS or a PMOS, the first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal, the first input node is coupled to a gate of the first output transistor, the second input node is coupled to a gate of the second output transistor, the output node is coupled to a common node of the first output transistor and the second clamping transistor, a gate of the first clamping transistor is coupled to a first reference voltage, and a gate of the second clamping transistor is coupled to a second reference voltage; a level shifter coupled to the first input node and the second input node; a power-up circuit coupled to the level shifter and the first power supply terminal, and; a detection circuit coupled to the power-up circuit; wherein the power-up circuit has a first state when the detection circuit determines a first condition, and provides a first voltage to the level shifter; and a second state when the detection circuit determines a second condition, and provides a second voltage to the level shifter.