Patent ID: 7920664

Claim:
A clock synchronization circuit comprising: a clock generation circuit generating a sampling clock for sampling a received signal of wireless communication, from an output of a local oscillator; a phase error detection circuit finding a phase error between sampling timing of the sampling clock and ideal sampling timing; and a timing correction circuit finding a correction quantity to correct a frequency error between a frequency of the sampling clock and a frequency of the ideal sampling timing and the phase error every sampling timing of the sampling clock, and outputting a sampling value interpolated according to the found correction quantity; and wherein the timing correction circuit comprises: a storage element retaining tap coefficients respectively associated with the correction quantities beforehand; a control circuit finding the correction quantity and selecting tap coefficients associated with the correction quantity; and a filter circuit finding the interpolated sampling value by performing a convolution operation on the selected, tap coefficients and a sampling value obtained at the sampling timing of the sampling clock; and wherein when the found correction quantity becomes more than a period of the sampling clock, the control circuit outputs an enable signal for invalidating a sampling value interpolated according to the correction quantity.