Patent ID: 7208759

Claim:
A test method of testing semiconductor integrated circuit devices comprising a semiconductor substrate of a first conductivity type, at least two first well regions of a second conductivity type formed separately and adjacently and formed continuously in the semiconductor substrate, second well region of the first conductivity type formed in the first well regions, integrated circuits formed on the at least two first well regions and the second well regions, a substrate bias region formed besides at least two first well regions in the semiconductor integrated circuit device, power supply source terminals and data output terminals included in the semiconductor integrated circuit device, and a substrate bias terminal connected to the substrate bias region in the semiconductor integrated circuit device, the test method comprising: applying a substrate bias to the substrate bias terminal in the semiconductor integrated circuit device; supplying potential to each power supply source terminals of at least two of the integrated circuits simultaneously and in parallel; detecting output data waveform respectively from the data output terminals of the at least two of the integrated circuits to which the potentials are supplied to the power supply source terminal; determining whether the detected output data waveform have a defect or not; and shutting off supply of the potential to the power supply source terminals of an integrated circuit if output data therefrom is determined as having said defect.