Patent ID: 8325542

Claim:
A method of complementary pairing of memory cells comprising: providing two physical memory cells in a complementary pair, wherein said memory cells comprise nitride charge trap/insulator data storage, and wherein when a first of said memory cells in said complementary pair is programmed, a second of said memory cells in said complementary pair is erased and vice versa; performing an initialization sequence on said complementary pair to minimize the threshold voltage offset between said two cells in said complementary pair, said initialization sequence comprising: cycling together said complementary pair an N number of times wherein said cycling stabilizes program/erase operations; thereafter, programming both memory cells in said complementary pairs; and thereafter, if a difference between a first threshold voltage of one of said complementary pair and a second threshold voltage of the other of said complementary pair is greater than a given tolerance, then the memory cell with the lower threshold voltage is slightly programmed further until said difference is less than said given tolerance; and comparing said two cells in said complementary pair with each other using a sense amplifier to determine if the first or the second of said memory cells in said complementary pair is programmed or erased.