Patent ID: 8466553

Claim:
A semiconductor package, comprising: a package substrate; a semiconductor device disposed on the package substrate, and comprising: a semiconductor substrate having a front surface and a backside surface; a backside passivation disposed on the backside surface of the semiconductor substrate; a conductive via disposed in the semiconductor substrate and surrounded by a liner, the conductive via and the liner protruding from the backside passivation, and a top surface of the conductive via is substantially coplanar with a top surface of the liner; and a conductive element covering the top surface of the conductive via and the protruding portion of the liner, wherein the conductive element is a RDL; a dielectric layer disposed over the RDL and the backside passivation, and having an opening to expose part of the RDL; a seed layer disposed in the opening and on part of the dielectric layer; and a UBM disposed over the seed layer; a top semiconductor device disposed on the semiconductor device and having at least one top external connection element on a surface thereof, wherein the conductive element contacts the top external connection element, and the position of the top external connection element is aligned with the conductive via; and a molding compound encapsulating the package substrate, the semiconductor device and the top semiconductor device.