Patent ID: 7346470

Claim:
A method comprising: obtaining circuit design data for at least one mask level; correlating design shapes of the circuit design data to the at least one mask level; from the correlated design shapes, generating a risk map for the at least one mask level that identifies risk factors specific to locations of the design shapes; defining a statistical model that determines, for any individual defect, a probability that the individual defect will render a chip inoperable as a function of defect parameters and value of a risk factor of the risk map corresponding to a location of the individual defect; measuring defects and their parameters and locations on the at least one mask level of selected chips; measuring operability of the selected chips; fitting the statistical model to the measured defect parameters, corresponding values of risk factors of the risk map, and measured chip operability; from the fitted statistical model, determining a probability of a chip made from the circuit design data to be rendered inoperable; and based on the determined probability, taking corrective action on the chip or its fabrication process.