Patent ID: 8639955

Claim:
A system for controlling power and performance in a microprocessor system, comprising: a monitoring and control system integrated into a microprocessor system, the monitoring and control system including: a hierarchical architecture, which includes a plurality of layers, each layer in the hierarchical architecture being responsive to commands from a higher level, the commands providing instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally, wherein a highest level in the hierarchy includes an operating system implemented in software, which issues the commands to a global power management and control unit (PMCU) by storing data in a register at the global PMCU, wherein the higher levels are configured to control power and performance of the lower levels and the lower levels are configured to autonomously initiate an action in response to a time-sensitive, or emergency situation.