Patent ID: 8339460

Claim:
A video signal processing integrated circuit comprising: a data slicer configured to binarize a video signal through comparison with a slice level, the video signal including superimposed video additional data; a data processing circuit configured to perform data processing of binarized video additional data output by the data slicer; and an internal test signal generation circuit configured to generate an analog test signal in conformity with video additional data superimposed on a video signal and provide the test signal to the data slicer as the video signal, wherein the test signal generation circuit includes: a series connection including a transistor, a first resistor for generating one binarized level of the video additional data, and a second resistor for generating the other binarized level of the video additional data, the transistor, the first resistor, and the second resistor being connected in series between a ground potential and a power-supply potential; a first analog switch configured to select the one binarized level generated by the first resistor to be output to the data slicer; a second analog switch configured to select the other binarized level generated by the second resistor to be output to the data slicer; a third resistor, connected between the transistor and the first resistor, configured to generate a synchronization level indicating a synchronization signal of the video signal; a third analog switch configured to select the synchronization level generated by the third resistor to be output to the data slicer; and a test control circuit configured to control the transistor and the first, second, and third analog switches as to on/off.