Patent ID: 7521988

Claim:
A voltage booster for a semiconductor device having a normal mode and a power-saving mode, the voltage booster comprising: a level shifter configured to receive a power-up signal and generate a level shifter output signal in response to the power-up signal, wherein the power-up signal increases along with an internal power supply voltage generated using an external power supply voltage and makes a logical transition when the internal power supply voltage reaches an predetermined internal power supply voltage target level; an initial voltage booster configured to transmit the external power supply voltage through an initial boosting node to a voltage boosting terminal in response to the level shifter output signal during the normal mode, and to block transmission of the external power supply voltage to the initial boosting node to decrease a voltage level of the initial boosting node during the power-saving mode; and a voltage boosting circuit configured to perform a charge pumping operation in response to the power-up signal to generate a boosting voltage with an amplitude higher than an amplitude of the external power supply voltage during the normal mode and further configured to disable the charge pumping operation during the power-saving mode.