Patent ID: 7260807

Claim:
A method for designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect, the method comprising: receiving a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable fabric; wherein the description of the mask-programmable cell defines one or more pins; wherein a pin is specified as being tied to, power, ground, a route segment or another pin; wherein a pin is associated with a logic function; and wherein a pin is specified as part of a sequential element; using the description of the mask-programmable cell to generate a derived library containing cells that can be obtained by programming the mask-programmable cell; receiving a high-level design for the integrated circuit; performing a synthesis operation on the high-level design to generate a preliminary netlist for the high-level design that contains references to cells in the derived library; and converting the preliminary netlist into a netlist that contains references to the mask-programmable cell.