Patent ID: 7436689

Claim:
A non-volatile semiconductor memory, comprising: a non-volatile main memory including a plurality of rows each composed of a corresponding part of a data storing area for storing actual data and a corresponding part of a history storing area for storing access number data; an address storing/comparing circuit including a plurality of rows for storing an address; and a volatile sub memory including a plurality of rows in correspondence with the plural rows of said address storing/comparing circuit, the plurality of rows each composed of a corresponding part of a data storing area for storing actual data and a corresponding part of a history storing area for storing access number data, wherein: when said address storing/comparing circuit stores an address identical to an external input address in read operation, in a row of said sub memory corresponding to a row storing the address identical to the external input address in said address storing/comparing circuit, data is read as external output data from a corresponding part of a data storing area; and when said address storing/comparing circuit stores no address identical to the external input address in read operation, in a row of said main memory corresponding to the external input address, after data is read as external output data from a corresponding part of a data storing area, the read data is written back thereto, and after data is read from a corresponding part of a history storing area, data indicating a sum of a predetermined value and a value of the read data is written thereto; in a row of said sub memory corresponding to a selected row in said address storing/comparing circuit, after data is read from a corresponding part of a history storing area, when a value of the read data from the history storing area of said main memory is larger than a value of the data read from the history storing area of said sub memory, the data read from the data storing area of said main memory is written to a corresponding part of a data storing area, and the data indicating the sum of the predetermined value and the value of the read data from the history storing area of said main memory is written to the corresponding part of the history storing area; and in said address storing/comparing circuit, after any of the plural rows is randomly selected, the external input address is written to the selected row when the value of the data read from the history storing area of said main memory is larger than the value of the data read from the history storing area of said sub memory.