Patent ID: 7571362

Claim:
A method of managing failures in a non-volatile memory device including an array of addressable cells grouped in blocks of data storage cells, the method comprising: defining in the array a first subset of user addressable blocks of data storage cells, a second subset of redundancy blocks of data storage cells, and a third subset of non-user addressable blocks; locating blocks including one or more failed cells of the first subset during a test on wafer of the non-volatile memory device; storing, in the third subset, a bad block address table based at least in part on said locating of the blocks; copying, at power-on of the non-volatile memory device, the bad block address table from the third subset to an embedded random access memory; looking up the bad block address table copied in the embedded random access memory to determine whether a block of the first subset addressed by the user is bad and, if so, remapping access to a corresponding block of redundancy data storage cells; determining, during operation of the non-volatile memory device, a failure of a block of cells previously not marked as bad, and updating the bad block address table in the embedded random access memory based at least in part on said determining of the failure of the block.