Patent ID: 7548472

Claim:
A semiconductor integrated circuit device comprising: a plurality of memory macros having memory cells which store data, a nonvolatile storage circuit which stores a plurality of data items including a set value for an internal timer which determines timings of operations of the plurality of memory macros and voltages of internal power supplies in the plurality of memory macros, a macro-common register block provided outside the plurality of memory macros and having macro-common registers which sequentially distribute memory macro operation specifying signals, which are related to the set value for the internal timer and voltages of the internal power supplies, to the plurality of memory macros, the macro-common registers being connected in serial to the nonvolatile storage circuit to serially store, upon power on, the data items including the set value for the internal timer and voltages of the internal power supplies and stored in the nonvolatile storage circuit, and memory macro operation setting circuits which are respectively provided in the plurality of memory macros and configured to set operating states of the memory macros according to the memory macro operation specifying signals which are data related to the set value for the internal timer and voltages of the internal power supplies and which are supplied from the macro-common registers, the memory macro operation setting circuits tuning the set value for the internal timer and the voltages of the internal power supplies in the plurality of memory macros.