Patent ID: 8169392

Claim:
A display, comprising: a plurality of gate lines; a gate driver configured for receiving input pulse signals, wherein falling edges of waveforms of the input pulse signals drop gradually from a first voltage to a second voltage, the gate driver further configured for driving the gate lines; a reference voltage generator configured for outputting a reference voltage, the value of the reference voltage being between the values of the first and second voltages of the input pulse signals; a comparator configured for receiving the input pulse signals and the reference voltage, and outputting a control signal according to the input pulse signals and the reference voltage; and a timing control circuit configured for receiving the control signal from the comparator, and, according to the control signal, outputting output enable signals to the gate driver to adjust gate signals applied to the gate lines, wherein falling edges of waveforms of the gate signals drop gradually from the first voltage to the reference voltage; wherein the reference voltage is adjustable, and the reference voltage is selectively set to be a constant value according to a desired line length of the falling edges of waveforms of the gate signals.