Patent ID: 7499103

Claim:
A deinterlacing processor comprising: an input port adapted to receive an interlaced video stream and an output port adapted to communicate a deinterlaced video stream having reduced motion artifacts to an external device; said deinterlacing processor operable to perform a spatial frequency analysis upon a plurality of vertically aligned pixels of a video frame having two adjacent video fields of said received interlaced video stream in order to generate a frequency analysis result; said deinterlacing processor using said frequency analysis result to detect a motion artifact and to determine a plurality of motion artifact detection values of a motion artifact to reduce the visibility of the motion artifact in the video frame, the plurality of motion artifact detection values including a determined ultimate detection value for each of the plurality of motion artifact detection values which are each based upon a characteristic spatial frequency and a number of elements equal to the plurality of vertically aligned pixels; and said deinterlacing processor generating said deinterlaced video stream having reduced motion artifacts using said frequency analysis result and said plurality of motion artifact detection values.