Patent ID: 7123267

Claim:
A core logic chip for use in a personal computer system comprising a system memory and a display, said core logic chip being incorporated therein: a graphics accelerator; a primary memory control circuit in communication with said graphics accelerator, controlled by said graphics accelerator to assert a first read/write signal; a first data transmission channel in communication with said primary memory control circuit and said system memory, transmitting said first read/write signal to said system memory; a backup memory control circuit in communication with said graphics accelerator, controlled by said graphics accelerator to assert a second read/write signal; and a second data transmission channel in communication with said backup memory control circuit and said system memory, transmitting said second read/write signal to said system memory, wherein each of said first and said second read/write signals is a part of a specific read/write signal for obtaining a specified image data from said system memory to be processed by said graphics accelerator, wherein said system memory includes a frame buffer where said image data is stored.