Patent ID: 8209509

Claim:
A method comprising: receiving configuration information including a mapping between a plurality of first memory locations and a plurality of second memory locations, wherein the plurality of second memory locations are protected from direct access by a processor, and wherein the configuration information further includes information associated with valid unlocking keys for accessing the plurality of second memory locations; receiving a request from the processor for a memory access at a first memory location included in the plurality of first memory locations, wherein the request is associated with receiving an unlocking key from the processor associated with a memory access exclusively at the first memory location; responsive to receiving the unlocking key, determining whether the unlocking key is valid for the requested memory access at the first memory location; and responsive to determining that the unlocking key is valid for the requested memory access at the first memory location, identifying a second memory location included in the plurality of second memory locations that is associated with the first memory location based on the mapping included in the configuration information, and performing the memory access at the second memory location based on the request from the processor for the memory access at the first memory location.