Patent ID: 8564027

Claim:
A semiconductor device, comprising: a bottom gate electrode; a first insulating layer disposed over the bottom gate electrode, the first insulating layer comprising a first open cavity etched in the first insulating layer, wherein the first open cavity is aligned with the bottom gate electrode; a second insulating layer disposed over the first insulating layer, the second insulating layer comprising a second open cavity etched in the second insulating layer, wherein the second open cavity is aligned with the first open cavity; a graphene layer disposed between the first and second insulating layers and in contact with surfaces of the first and second insulating layers, wherein a portion of the graphene layer is suspended between the first and second open cavities; at least one sense electrode disposed on the graphene layer adjacent the first and second open cavities, an elongated nano-structure mounted to the portion of the graphene layer that is suspended between the first and second open cavities; and a top gate electrode disposed over the second insulating layer, the top gate electrode aligned with the bottom gate electrode and the first and second open cavities.