Patent ID: 7711761

Claim:
A method of processing digital signals in an electronic circuit, the method comprising the steps of: making the digital signals available in two's complement representation and converting the two's complement representation into Binary Canonic Signed Digit representation by a recussive detector function b n+1 =( X n +X n+1 )· b n +X n ·X n+1 where x n ,x n+1 are subsequent values of said digital signals (x) in the two's complement representation, and b n ,b n+1 are subsequent values of said detector function, and said Binary Canonic signal digit (BCSD) representation is calculated as ( X n ) B =X n {circle around (x)}( b n−1 ·X n−1 ) where (x n ) B are subsequent values of said digital signal in Binary Canonic Signed Digit (BCSD) representation; and converting the digital signals made available in the Binary Canonic Signed Digit representation into the signals in Canonic Signed Digit representation for use in processing in the electronic circuit.