Patent ID: 7153720

Claim:
A method of constructing process architecture to fabricate back-side illuminated image sensor matrices, the process architecture comprising fully-depleted CMOS devices, and photo-diodes incorporating epitaxially grown regions, the method comprising: (a) selecting a Thin-Film Silicon-On-Insulator (TF-SOI) or Thin-Film Germanium-On-Insulator (TF-GeOI or TF-GOI) substrate, comprising a top thin semiconductor film, a buried insulator comprising a back surface that faces a bottom thick semiconductor substrate; (b) fabricating the fully-depleted CMOS devices and circuitry incorporating the fully-depleted CMOS devices on the top thin semiconductor film; (c) Epitaxially growing photo-diode active layers on the top thin semiconductor film; (d) fabricating dense metal interconnects over each of the image sensor matrices, including over the photo-diode regions, on a top of the thin semiconductor film; (e) removing the bottom thick semiconductor substrate, after full processing of a front-side of the top thin semiconductor film; (f) fabricating monolithically integrated structures on the back surface of the buried insulator, aligned to the dense metal interconnects made on the top thin semiconductor film; (g) bonding to a new mechanical substrate that is transparent to wavelengths of interest, of the back surface of the buried insulator after fabricating the monolithically integrated structures; and (h) dicing and packaging each of the fully-depleted CMOS devices, or wafer-level packaging followed by separation of individual CMOS image sensor matrix chips.