Patent ID: 7511997

Claim:
A semiconductor memory device comprising: a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit; and a read/write circuit for reading data from the memory cell array and writing data into the memory cell array, wherein each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, a highest or a lowest level of the N physical quantity levels is defined as a base level, and a first of the cells of the pair cell is set to the base level and a second of the cells of the pair cell is set to a different level than the base level in two memory cells therein, thereby storing M-value data defined by M=2 n (where M=2(Nâˆ’1) and â€œnâ€ is an integer equal to two or more), the M-value data being defined by such M combination states that differences of the base level of the first of the cells and plural other levels of the second of the cells are different from each other.