Patent ID: 7515669

Claim:
A method to sample a digital input signal, said method comprising: providing a first digital buffer comprising: a first p-channel transistor; a first n-channel transistor; a first pair of p-channel transistors having drains and sources connected together; and a first pair of n-channel transistors having drains and sources connected together wherein said first p-channel transistor, said first n-channel transistor, said first pair of p-channel transistors, and said first pair of n-channel transistors are connected in series between an upper supply voltage and a lower supply voltage, wherein gates of said first p-channel and first n-channel transistor are connected to a same input signal, wherein gates of one said n-channel transistor and of one said p-channel transistor, in each said first pair of p-channel and n-channel transistors, are connected to a first control signal and gates of other said n-channel transistor and of other said p-channel transistor, in each said first pair of p-channel and n-channel transistors, are connected to an inversion of said first control signal; providing a second digital buffer comprising: a second p-channel transistor; a second n-channel transistor; a second pair of p-channel transistors having drains and sources connected together; and a second pair of n-channel transistors having drains and sources connected together wherein said second p-channel transistor, said second n-channel transistor, said second pair of p-channel transistors, and said second pair of n-channel transistors are connected in series between an upper supply voltage and a lower supply voltage, wherein gates of said second p-channel and second n-channel transistor are connected to the same input signal, wherein gates of one said n-channel transistor and of one said p-channel transistor, in each said second pair of p-channel and n-channel transistors, are connected to a second control signal and gates of other said n-channel transistor and of other said p-channel transistor, in each said second pair of p-channel and n-channel transistors, are connected to an inversion of said second control signal; sampling a digital input processed through said first digital buffer wherein said sampling is at the rising edge of a system clock; updating the switching threshold of said second digital buffer; sampling said digital input processed through said second digital buffer wherein said sampling is at the falling edge of said system clock; and updating the switching threshold of said first digital buffer.