Patent ID: 8751851

Claim:
An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a Joint Test Action Group (JTAG) interface, configured to receive control information over a standard JTAG bus, wherein said control information indicates an amount to advance a synchronous data strobe associated with a data group; a synchronous bus optimizer, configured to receive said control information, and configured to develop a value on a ratio bus that indicates said amount; a core clocks generator, coupled to said ratio bus, configured to advance a data strobe clock by said amount, said core clocks generator comprising; a phase locked loop (PLL), comprising; PLL forward elements, configured to receive a bus clock signal, and configured to generate said data strobe clock signal at a frequency multiple of said bus clock signal; a delay-locked loop (DLL), configured to receive said data strobe clock signal and said ratio bus, and configured to generate an output that comprises said data strobe clock signal delayed by said amount; and a frequency divider, configured to receive said output, and configured to generate a delayed reference signal that is equal in frequency to said bus clock signal to enable said PLL forward elements to align said output in phase with said bus clock signal, thereby causing said data strobe clock signal to be advanced by said amount; and a synchronous strobe driver, configured to receive said data strobe clock, and configured to employ said data strobe clock to generate said synchronous data strobe, wherein said synchronous data strobe, when enabled, is advanced also by said amount.