Patent ID: 7505548

Claim:
A circuit for dividing a frequency of an input signal by an integer divider value of at least two, said circuit comprising: a) a first frequency divider, including (i) a first plurality of serially connected delay elements configured to receive said input signal and (ii) a first configurable coupling circuit configured to couple one or more first outputs of said first plurality of delay elements to an input of a first of said first plurality of delay elements; b) a second frequency divider, including (i) a second plurality of serially connected delay elements configured to receive an inverse of said input signal and (ii) a second configurable coupling circuit configured to couple one or more first outputs of said second plurality of delay elements to an input of a first of said second plurality of delay elements; c) configurable logic configured to select a second output of said first plurality of delay elements and a second output of said second plurality of delay elements and producing a frequency divided output signal; and d) a programmable circuit configured to selectably configure said first and second configurable coupling circuits and said configurable logic.