Patent ID: 8314808

Claim:
An electronic system comprising: a first device, the first device including: a first memory interface having a first memory controller; the first memory interface configured to access a shared memory; and a first direct memory access (DMA) engine coupled to the first memory interface, the first DMA engine configured to determine a burst length of first data to be communicated through the first memory interface; a decoder/encoder, the decoder/encoder having: a second memory interface having a second memory controller, the second memory interface having access to the shared memory; and a second DMA engine coupled to the second memory interface, the second DMA engine configured to determine a burst length of second data to be communicated through the second memory interface; an arbiter configured to receive shared memory access requests from the first device and the decoder/encoder, the arbiter configured to arbitrate access to the shared memory; and a bus configured to pass the first data in real time between the shared memory and the first device and the bus further configured to pass the second data in real time between the shared memory and the decoder/encoder.