Patent ID: 8766407

Claim:
A semiconductor wafer comprising: a semiconductor substrate; and an interconnect layer formed on the semiconductor substrate, wherein the semiconductor substrate includes a first region located at an outer periphery of the semiconductor substrate and uncovered with the interconnect layer, the interconnect layer includes a second region where an upper surface of the interconnect layer is substantially flat, a first insulating film is formed within the first region, and the upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other, wherein the interconnect layer includes a third region located between the first region and the second region, a height of the upper surface of the third region decreases from the second region side toward the first region side, a second insulating film is formed on the third region, the upper surface of the interconnect layer within the second region is substantially flush with the upper surface of the second insulating film within the third region, and the first region includes a step region where a step is formed, on a surface on which the first insulating film is formed.