Patent ID: 8902625

Claim:
An integrated circuit comprising: a plurality of memory circuits arranged on a die along a plurality of rows and a plurality of columns, wherein each memory circuit includes a plurality of memory cells, and wherein the plurality of rows and the plurality of columns are arranged in an area of the die; and a plurality of logic circuits arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns, wherein the plurality of logic circuits are configured to communicate with one or more of the memory circuits, wherein a first logic circuit of the plurality of logic circuits shares one of the plurality of rows with two of the plurality of memory circuits, and wherein a second logic circuit of the plurality of logic circuits shares one of the plurality of columns with two of the plurality of memory circuits; and wherein one or more of a processor, an additional memory, a communication module, and a power management module of the integrated circuit are arranged (i) along a perimeter of the die and (ii) around the area.