Patent ID: 8912934

Claim:
A system comprising: a plurality of converters configured to receive (i) an analog signal, and (ii) a respective one of a plurality of clock signals, wherein each converter of the plurality of converters is configured to sample the analog signal based on the respective clock signal received by the converter to generate a respective one of a plurality of digital signals, wherein each of the plurality of clock signals is out-of-phase with other ones of the plurality of clock signals; a plurality of first modules configured to (i) receive the plurality of digital signals generated by the plurality of converters, (ii) remove bias offsets from each of the plurality of digital signals to generate a plurality of first output signals, and (iii) output each of the plurality of first output signals on a respective one of a plurality of channels; a plurality of second modules configured to (i) receive the plurality of first output signals, and (ii) based on the plurality of first output signals, remove or equalize gain mismatch between the plurality of channels to generate a plurality of second output signals; and a multiplexer configured to (i) receive the plurality of second output signals, and (ii) generate an output based on the plurality of second output signals, wherein the output of the multiplexer is a digital representation of the analog signal.