Patent ID: 7737751

Claim:
A signal network on a programmable logic device for distributing clock-type signals from peripheral input/output blocks of said programmable logic device to other portions of said programmable logic device, said signal network comprising: a device-wide dedicated, low-skew clock-type signal distribution network on said programmable logic device, arranged so that distances traveled by a signal from an entry point of said device-wide dedicated, low-skew clock-type signal distribution network to any destination on said programmable logic device are substantially equal; and a second dedicated clock-type signal distribution network on said programmable logic device, comprising: a first dedicated clock-type signal bus on said programmable logic device separate from said device-wide dedicated, low-skew clock-type signal distribution network, and having an end at a first location adjacent a first group of said peripheral input/output blocks, and a first plurality of dedicated clock-type signal lines on said programmable logic device, each dedicated clock-type signal line in said first plurality of said dedicated clock-type signal lines being separate from said device-wide dedicated, low-skew clock-type signal distribution network, having a first dedicated connection at one end thereof to a respective one of said peripheral input/output blocks in said first group of peripheral input/output blocks, and being connected at another end thereof to said first dedicated clock-type signal bus substantially at said first location; wherein: said first dedicated clock-type signal bus extends from said first location to a first clock distribution spine on said programmable logic device.