Patent ID: 8484007

Claim:
A method for a simulation model of a hardware design being verified, comprising: receiving a pipeline state for unit verification and an instruction train for hardware verification events, said instruction train including handling of instruction rejects, partial rejects, stalls, branch wrongs, and exceptions; simulating a design comprising the pipeline state and the instruction train by an instruction pipeline, the instruction pipeline comprising an instruction decode unit, an execution unit, and a plurality of instructions; monitoring correctness of the design being simulated by simulation monitors and drivers; detecting by said simulation drivers and monitors unexpected hardware signals based on hardware signal events occurring for any one of the plurality of instructions in the instruction pipeline; initiating a reject counter based on a cache reject event; continuing to advance the instruction pipeline after initiating the reject counter; and tagging each of the plurality of instructions in the pipeline with a state, the tagged states including each of cache rejects, instruction rejects, decode stalls, early and late branch wrongs and xconds.