Patent ID: 7898069

Claim:
A semiconductor system comprising: a rigid insulating interposer having a first and a second surface, a thickness, and a modulus; conductive traces on the first and the second surface; cylindrical metal-filled vias extending through the thickness from the first to the second surface, contacting the traces; an opening through the thickness, the opening having a length; a first semiconductor chip having an active and a passive surface, a thickness, and a length; a second semiconductor chip having an active and a passive surface, a thickness, and a length; the interposer thickness being equal to or greater than the thickness sum of the first and second chips; the length of the opening being greater than the length of the first and the second chip; a first insulating tape having conductive traces, a third and a fourth surface including contact pads, and a modulus; a second insulating tape having conductive traces, a fifth and a sixth surface including contact pads, and a modulus; the modulus of the first and the second tape being 50% or less of the interposer modulus; the active surface of the first chip flip-attached to the contact pads of the third surface; the active surface of the second chip flip-attached to the contact pads of the fifth surface; the attached first and second chips located inside the opening so that the first and second tapes are spaced substantially parallel to the interposer; the passive surfaces of the chips attached by a layer of an adhesive material; the first surface attached to the third surface by a layer of the same adhesive material; and the second surface attached to the fifth surface by a layer of the same adhesive material.