Patent ID: 7777526

Claim:
A single-stage buffer circuit comprising: a first differential input transistor and a second differential input transistor, each transistor having a respective gate, source, and drain; a first input connected to the gate of the first differential input transistor; a second input connected to the gate of the second differential input transistor; a first output connected to the drain of the first differential input transistor; a second output connected to the drain of the second differential input transistor; a first load resistor connected between the drain of the first differential input transistor and a power supply; a second load resistor connected between the drain of the second differential input transistor and the power supply; a first tail current source connected between the source of the first differential input transistor and ground; a second tail current source connected between the source of the second differential input transistor and ground; a degeneration resistor connected between the source of the first differential input transistor and the source of the second differential input transistor; and an equalization capacitor connected between the source of the first differential input transistor and the source of the second differential input transistor; wherein: at least one of said first and second tail current sources, said degeneration resistor and said first and second load resistors is a variable-valued circuit element.