Patent ID: 7560804

Claim:
An integrated circuit chip package, comprising: a leadframe which includes: a die pad defining opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces; a plurality of leads extending toward the die pad in spaced relation thereto, each of the leads defining opposed first and second lead surfaces and at least first and second lead side surfaces extending between the first and second lead surfaces; and recess disposed within at least a portion of the die pad and within each of the first and second lead side surfaces of each of the leads for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads; an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surface of at least some of the leads; the encapsulant material applied to the integrated circuit die, the first die pad surface and the die pad side surface of the die pad, and to the first lead surface and the first and second lead side surfaces of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.