Patent ID: 7925869

Claim:
A computer-based system for switching between program contexts comprising: a processor capable of having a first program thread and a second program thread in an execution pipeline having thread selection hardware; a first set of data storage devices capable of storing a first thread state of said processor; a second set of data storage devices capable of storing a second thread state of said processor; and a hardware thread scheduler for identifying which of said first and second program threads said processor executes and configurable to allocate available processing time of the processor among at least the first and second program threads by causing thread-switching from execution of the first program thread directly to execution of the second program thread at a fixed time according to a predetermined fixed schedule and without using interrupts by accessing one or more registers included in the first set or the second set of data storage devices based on a context number associated with an instruction included in a program thread identified for execution by the predetermined fixed schedule, said schedule specifying that the first thread should be allocated processing time every first number of cycles and that the second thread should be allocated processing time every second number of cycles, wherein said first number of cycles is not equal to said second number of cycles.