Patent ID: 7956460

Claim:
A semiconductor device comprising: a first semiconductor chip having: a first semiconductor substrate, a multilevel interconnection structure being provided on a surface of the first semiconductor substrate, an uppermost interconnection layer in the multilevel interconnection structure being partly exposed as a pad from an opening formed in a surface protective film; a first bump of a metal projecting from a surface of the first semiconductor substrate, the first bump covering the opening and projecting from a surface of the surface protective film; and a first alloy film covering an entire surface of the first bump, the first alloy film being composed of an alloy of the metal of the first bump and a second metal; and a second semiconductor chip having: a second semiconductor substrate, a multilevel interconnection structure being provided on a surface of the second semiconductor substrate, an uppermost interconnection layer in the multilevel interconnection structure being partly exposed as a pad from an opening formed in a surface protective film; a second bump of a metal projecting from a surface of the second semiconductor substrate, the second bump covering the opening and projecting from a surface of the surface protective film; and a second alloy film covering an entire surface of the second bump, the second alloy film being composed of an alloy of the metal of the second bump and a third metal; and wherein the first bump is made of the same material as that of the second bump, wherein the second alloy film is made of the same material as that of the second alloy film, and wherein the first and second semiconductor chips are bonded to each other with an active surface of the first semiconductor chip being opposed to an active surface of the second semiconductor chip.