Patent ID: 7522443

Claim:
An integrated circuit memory, comprising: a memory array including a plurality of memory cells in rows and columns, the memory array being divided into a plurality of blocks of the memory cells; wherein each of the blocks includes: a plurality of word lines arranged along the rows and coupled to the memory cells; a plurality of first and second bit lines individually and alternately allocated along every other column, each of the first bit lines for coupling to a virtual ground voltage and each of the second bit lines for coupling to a sense amplifier; a first selecting line and a second selecting line for providing a first control signal; a third selecting line and a fourth selecting line for providing a second control signal; a plurality of first selecting transistors having their gates coupled to the first selecting line to receive the first control signal and operable between ON and OFF states in response to the received first control signal, each of the first selecting transistors for coupling one of the memory cells in a selected row to one of the first bit lines in response to the first control signal, wherein two of the first selecting transistors are coupled to a same one of the first bit lines, that is coupled to the virtual ground voltage, and located on opposite sides of the one of the first bit lines; a plurality of second selecting transistors having their gates coupled to the third selecting line to receive the second control signal and operable between ON and OFF states in response to the received second control signal, each of the second selecting transistors for coupling one of the memory cells in the selected row to one of the second bit lines in response to the second control signal, wherein two of the second selecting transistors are coupled to a same one of the second bit lines, that is coupled to the sense amplifier, and located on opposite sides of the one of the second bit lines; a plurality of third selecting transistors having their gates coupled to the second selecting line to receive the first control signal, each of the third selecting transistors coupled to one of the second bit lines, each of the third selecting transistors for coupling one of the memory cells in the selected row to one of the second bit lines, that is coupled to the sense amplifier, in response to the first control signal; and a plurality of fourth selecting transistors having their gates coupled to the fourth selecting line to receive the second control signal, each of the fourth selecting transistors coupled to one of the first bit lines, each of the fourth selecting transistors for coupling one of the memory cells in the selected row to one of the first bit lines, that is coupled to the virtual ground voltage, in response to the second control signal; wherein when reading out data stored in all of the memory cells within the same block, respective lengths of read current flow paths corresponding to all of the memory cells within the same block are substantially the same.