Patent ID: 7779310

Claim:
A system for detecting a work status of a computer system comprising a Super input/output (I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset, and a device driver, wherein: the device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and driving the Super I/O chipset to periodically generate and send a test signal to the CPLD; the CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time, and sending a response signal to the Super I/O chipset and resetting the clock to start timing from the initial time when the predetermined amount of test signals have been received in the predetermined time; and the South Bridge chipset is configured for rebooting the computer system when the reboot signal is received from the CPLD.