Patent ID: 8722520

Claim:
A method, comprising: providing a substrate; forming a first trench and a second trench in the semiconductor substrate, wherein the second trench has a greater width than the first trench; growing a first epitaxy region in the first trench, wherein the epitaxy region extends beyond an opening of the first trench; concurrently with growing the first epitaxy region, growing a second epitaxy region in the second trench, wherein a first portion of the second trench is not filled with the epitaxy region; forming an amorphous layer overlying the second epitaxy region; annealing the semiconductor substrate including the amorphous layer, wherein the annealing provides a crystalline region overlying the second epitaxy region; and performing a chemical mechanical polish (CMP) after annealing the semiconductor substrate such than the first and second epitaxy regions are co-planar.