Patent ID: 8587990

Claim:
A static random-access memory (SRAM) circuitry having SRAM cells for storing data words of a length of at least one bit, wherein each bit of the data words is stored in an assigned SRAM cell, the SRAM circuitry comprising: address lines for addressing data words by address signals; a decoding unit for decoding the address signals on the address lines to generate word line signals on a word-line per addressed data word, wherein at least a portion of the address lines is decoded by the decoding unit to provide at least one decoded address line carrying at least one decoded address bit; a local bit line to be coupled to the SRAM cells of different data words with different addresses; a global bit line to be coupled to the local bit line; and a global bit line restore unit electronically coupled to the global bit line and the decoding unit for pre-charging the global bit line upon being triggered by a trigger signal based on a trailing edge of the at least one decoded address bit from the decoding unit.