Patent ID: 8656332

Claim:
A computer-performed method comprising: assigning, using a processor and a memory, placement forces to a set of moveable cells within a macro element of a semiconductor design, the semiconductor design usable to produce a semiconductor circuit, wherein the semiconductor design contains a plurality of macro elements and wherein the placement forces serves to limit movement of said set of moveable cells away from their present location in a force-directed placement algorithm; placing a new cell in the macro element in the semiconductor design; applying the force-directed placement algorithm to both the new cell and the set of moveable cells to improve placements of the new cell and the set of moveable cells, resulting in the new cell occupying a location within the macro element by displacing a moveable cell in the set of moveable cells that occupied a portion of the location before applying the force-directed placement algorithm; placing a blockage at the location of the new cell, the blockage being a blockage located within the macro element; optimizing placement of the set of moveable cells so as to avoid overlap between the set of moveable cells and the blockage, resulting in optimized placement, the blockage allowing optimization of the placement using a size for the new cell greater than an actual size of the new cell; and generating a transformed semiconductor design using the optimized placement.