Patent ID: 8683178

Claim:
A method for executing vector instructions in a processor, comprising: initializing an architectural fault-status register (FSR) and a shadow copy of the architectural FSR by setting each of N bit positions in the architectural FSR and the shadow copy of the architectural FSR to a first predetermined value; executing a first vector instruction, wherein the first vector instruction is a first-faulting or non-faulting vector instruction; and while executing the first vector instruction, executing one or more subsequent vector instructions, wherein each of the subsequent vector instructions is a first-faulting or non-faulting vector instruction; wherein executing the first vector instruction and the subsequent vector instructions comprises updating one or more bit positions in the shadow copy of the architectural FSR to a second predetermined value upon encountering a fault condition while performing a corresponding operation for the first vector instruction or one of the subsequent vector instructions; and wherein the method further comprises not updating bit positions in the architectural FSR upon encountering a fault condition while performing a corresponding operation for the first vector instruction or one of the subsequent vector instructions.