Patent ID: 7477257

Claim:
A memory hub for a graphics system, comprising: a dynamic random access memory (DRAM) interface operative to access a plurality of different types of DRAM memories each requiring a different DRAM protocol; a hub interface for accessing the memory hub via an Input/Output (I/O) bus; and logic for bridging signals between said hub interface and said DRAM interface and performing translation of signals between said hub interface and said DRAM interface; said memory hub operative for a graphics processing unit (GPU) to utilize said hub interface to access two or more DRAMs; wherein said hub interface utilizes a high speed packetized bus protocol and said DRAM interface utilizes a non-packetized protocol, said high speed packetized bus protocol having at least a factor of two faster transfer rate than said non-packetized protocol such that said memory hub reduces an I/O pin count on said GPU.