Patent ID: 7187741

Claim:
A method of passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the method comprising: linking write-address information with data in the source clock domain; generating a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock; transmitting the data with the linked write-address information and the transmit clock signal to the receive clock domain; writing the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal; and reading the data from the storage element synchronized with the receive clock; wherein the data is N bits wide and the storage element is M locations deep, and the data with the linked write-address information is communicated using at most N+2*┌log 2 (M)┐+4 electrical signal paths, M being a power of 2.