Patent ID: 7187238

Claim:
An amplifier circuit comprising: a signal input; a first multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal operably coupled to receive an input signal from the signal input and at least one control gate terminal operably coupled to receive a control signal; and a second multiple gate filed-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal connected to the signal gate terminal of the first multiple gate field-effect transistor, and a control gate terminal connected to the control gate terminal of the first multiple gate field-effect transistor, each of the multiple gate field-effect transistor further comprising a first region associated with a drain terminal or a source terminal, a second region associated with a source terminal or a drain terminal, a channel region arranged between the first region and the second region, at least one first gate structure associated with a first portion of the channel region and arranged adjacent to the first region, the first gate structure being associated with the signal gate terminal or with the control gate terminal, at least one second gate structure associated with a second portion of the channel region and arranged adjacent to the second region, the second gate structure being associated with the signal gate terminal or with the control gate terminal, wherein the second multiple gate field-effect transistor has a signal gate structure comprising that of the first or second gate structure that is associated with the signal gate terminal, the signal gate structure connected to that of the first or second region which is adjacent to the channel region of the signal gate structure, wherein in the first multiple gate field-effect transistor, the signal gate terminal is connected to the first gate structure, the control gate terminal is connected to the second gate structure, the source terminal is connected to the first region, and the drain terminal is connected to the second region, and wherein in the second multiple gate field-effect transistor, the signal gat terminal is connected to the first gate structure, the control gate terminal is connected to the second gate structure, the source terminal is connected to the second region, and the drain terminal is connected to the first region, the signal gate terminal of the second multiple gate field-effect transistor being connected to the drain terminal.