Patent ID: 7459761

Claim:
A chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a pad over said silicon substrate, wherein said pad has a top surface with a first region and a second region surrounding said first region; a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer is on said second region, and an opening in said passivation layer is over said first region, wherein said opening exposes said first region, wherein said opening has a width smaller than that of said pad, and wherein said opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a nitride layer; a polymer layer over said passivation layer, wherein said polymer layer has a thickness greater than that of said passivation layer and between 2.0 and 150 μm; a gold coil over said polymer layer, wherein said gold coil comprises an electroplated gold layer having a thickness greater than that of said pad, and wherein said gold coil is connected to said pad through said opening; and a third metal layer between said passivation layer and said polymer layer and under said gold coil.