Patent ID: 7496899

Claim:
A data processing apparatus for processing instructions, said data processing apparatus comprising: decode/issue logic configured to receive and decode an instruction to be processed by said data processing apparatus and to determine when to issue a decoded instruction for execution; execution logic configured to execute said decoded instruction; interface logic selectively operable to receive trace information relating to the state of said data processing apparatus generated in response to execution of said decoded instruction for transmission to trace monitoring infrastructure; and throttle logic configured to predict whether issuing said decoded instruction to said execution logic for execution would be likely to cause said trace information to be transmitted to said trace monitoring infrastructure to exceed a capacity of said trace monitoring infrastructure and, if so, to prevent said decode/issue logic from issuing said decoded instruction to said execution logic irrespective of whether said interface logic is selected to be operable to receive trace information such that a cycle-by-cycle timing behavior of said data processing apparatus does not substantially differ when said interface logic is enabled to receive trace information and when said interface logic is not enabled to receive trace information.