Patent ID: 7928439

Claim:
A thin film transistor (TFT), comprising: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer, the semiconductor layer including a top surface; a channel area aligned in a vertical direction with the gate electrode; a plurality of doped areas proximate to the channel area; and a plurality of non-doped areas, each non-doped area proximate to at least one of the plurality of doped areas, the channel area, the plurality of doped areas, and the plurality of non-doped areas forming a continuous layer; a source electrode on the top surface of the semiconductor layer aligned above one of the plurality of non-doped areas of the semiconductor layer; a drain electrode the top surface of the semiconductor layer aligned above another one of the plurality of non-doped areas of the semiconductor layer; and a planarization layer on the gate insulating layer, the source and drain electrodes and the semiconductor layer channel area, the planarization layer including a plurality of openings, each opening exposing at least one of the plurality of doped areas of the semiconductor layer and exposing a portion of at least one of the source electrode and the drain electrode.