Patent ID: 7227203

Claim:
A high voltage multiple output current device comprising: a substrate of a first conductivity type; a first doped region of a second conductivity type on a first portion of the substrate, the first doped region formed as a first closed geometric shape having a center and a first periphery wherein a first portion of the first periphery has a first contour and a second portion of the first periphery has a second contour and also wherein the first doped region is a drain and a source of a J-FET transistor, a drain of a first MOS transistor, and a drain of a second MOS transistor; a second doped region of the second conductivity type on the substrate and having a second periphery wherein a portion of the second periphery is juxtaposed to the first portion of the first periphery and has a third contour that is the same shape as the first contour wherein the second doped region is a source of the first MOS transistor; and a third doped region of the second conductivity type on the substrate and having a third periphery wherein a portion of the third periphery is juxtaposed to the second portion of the first periphery and has a fourth contour that is the same shape as the second contour, and wherein the third doped region is a source of the second MOS transistor.