Patent ID: 8793795

Claim:
A hardware accelerator for use with an analysis unit to analyze data on an external suspect device comprising a suspect computer or computer device, the hardware accelerator comprising: a first interface for connecting to the external suspect device, the first interface being configured to transfer the data at a first data transfer rate, the first data transfer rate being limited by the first interface and the external suspect device; a second interface for connecting to the analysis unit, the second interface being a high-speed interface comprising SATA, USB, 1394, or Ethernet and configured to transfer the data at a second data transfer rate, the second data transfer rate being limited by the second interface, the analysis unit, and the first data transfer rate; and a processing unit comprising: memory for storing instructions, firmware, or parameters received from the analysis unit via the second interface; and a microprocessor and/or field programmable gate array (FPGA) for analyzing the data according to the instructions, firmware, or parameters, wherein the microprocessor and/or FPGA is configured to: read the data from the external suspect device via the first interface at the first data transfer rate; concurrently: perform computer forensic analysis on the data, comprising searching, compressing, decompressing, or hashing the data, in accordance with the instructions, firmware, or parameters; and transmit the data to the analysis unit via the second interface at the second data transfer rate; and transmit results of the computer forensic analysis to the analysis unit, wherein the first data transfer rate and the second data transfer rate are not limited by the processing unit, and wherein the microprocessor and/or FPGA is further configured to analyze the data concurrently and without slowing the first data transfer rate or the second data transfer rate while the data passes through the hardware accelerator.