Patent ID: 7528439

Claim:
A semiconductor structure containing a vertical transistor, comprising: a substrate, wherein at least a portion of the work surface of the substrate is formed of polysilicon; a polysilicon pillar extending vertically from the polysilicon surface of the substrate, the pillar having a top end, a top portion, a central portion, and a bottom portion; a first source/drain region defined in the top portion of the pillar; a channel region defined in the central portion of the pillar; a second source/drain region defined in the bottom portion of the pillar; a dielectric layer surrounding the central portion of the pillar and being in alignment with the channel region of the transistor; a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor; and a spacer layer formed around only the top portion of the pillar and the first source/drain region.