Patent ID: 7384836

Claim:
A method of fabricating a transistor, comprising: forming a first doped well region in a first active region of a well layer; forming a temporary field oxide on the first doped well region; forming a first patterned mask over the first active region of the well layer, the first patterned mask having at least a first opening formed therein over the first active region, wherein the temporary field oxide is formed through the first opening; after forming the temporary field oxide, removing the first patterned mask; removing the temporary field oxide to form a recess in the first doped well region; forming a permanent field oxide, wherein at least part of the permanent field oxide is formed in the recess; forming a drain doped region in the recess and in the first doped well region adjacent to the part of the permanent field oxide formed in the recess; and forming a gate electrode over the first active region such that at least part of the gate electrode is adjacent to the recess, wherein the part of the permanent field oxide formed in the recess is located between the gate electrode and the drain doped region.