Patent ID: 8031020

Claim:
A circuit comprising: a first transistor having a control terminal, a drain terminal, and a source terminal; a second transistor having a control terminal, a drain terminal, and a source terminal; a first bias network having i) as first terminal coupled to the control terminal of the first transistor and ii) a second terminal coupled to the drain terminal of the second transistor, the first bias network generating a first voltage difference across a first component between i) the control terminal of the first transistor and ii) the drain terminal of the second transistor to increase a first drain voltage at the drain terminal of the second transistor, wherein the first voltage difference is set using a second component coupled to the first component; a second bias network having i) first terminal coupled to the control terminal of the second transistor and ii) a second terminal coupled to the drain terminal of the first transistor, the second bias network generating a second voltage difference across a third component between i) the control terminal of the second transistor and ii) the drain terminal of the first transistor to increase a second drain voltage at the drain terminal of the first transistor, wherein the second voltage difference is set using a fourth component coupled to the third component; and a load circuit having i) first terminal coupled to the drain of the first transistor and ii) a second terminal coupled to the drain of the second transistor.