Patent ID: 8212314

Claim:
A semiconductor device comprising: a first conductive type semiconductor substrate; a first semiconductor region provided on an upper surface of the semiconductor substrate and including a region in which first conductive type first pillar regions and second conductive type second pillar regions, each having a long side in a first direction parallel to the upper surface of the semiconductor substrate, are alternately arranged in a second direction which is parallel to the upper surface of the semiconductor substrate and which is orthogonal to the first direction; second conductive type second semiconductor regions provided on surfaces of second pillar regions in an element region in which a semiconductor element is formed so as to be in contact with first pillar regions in the element region; gate electrodes, each provided on parts of adjacent second semiconductor regions and on one of the first pillar regions interposed therebetween with a gate insulating film provided under the gate electrodes; third semiconductor regions, each functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal region, wherein, the widths of the second pillar regions provided from the element region to the terminal region are each set as a first width, the widths of the first pillar regions provided in the element region and the widths of the first pillar regions connected to the resurf region in the terminal region are each set as a second width, and the widths of first pillar regions which are provided in the terminal region and which are not provided with the resurf region thereon are each set smaller than the second width.