Patent ID: 8802561

Claim:
A method of forming features in a 3D memory array, the method comprising: forming a structure having first lines and gaps in a memory cell region; forming trenches between dummy material in a hookup region outside of the memory cell region; forming a flowable film in the memory cell region and in the hookup region, the flowable film substantially fills the gaps, the flowable film does not completely fill the trenches in the hookup region; forming an insulating film over the flowable film in the memory cell region and in the hookup region, the insulating film filling remaining portions of the trenches that are not filled by the flowable film; forming a conductive region over the insulating film that is in the trenches; and etching the conductive region in the hookup region to form conductive wires from the conductive region, the conductive wires for a given trench have a total pitch, the forming a flowable film in the hookup region leaves a gap in the given trench that is wider than the pitch of the wires.