Patent ID: 7855668

Claim:
A delta sigma A/D modulator comprising: a DAC circuit; an integration circuit for adding and integrating an input analog signal and an output signal of the DAC circuit; a variable gain circuit for changing a gain of an output signal of the integration circuit to provide an output signal; a quantizer for quantizing the output signal of the variable gain circuit; an offset addition circuit for generating an offset signal, and for adding the offset signal to the output signal of the variable gain circuit to input the resultant signal to the quantizer, thereby causing the quantizer to output a digital signal equivalent to a level of a total of the output signal of the variable gain circuit and the offset signal; an offset control circuit for outputting a control signal for controlling the offset addition circuit; an output processing circuit for generating output digital data equivalent to a value obtained by subtracting the offset signal from the output signal of the variable gain circuit based on the digital signal outputted from the quantizer and the control signal outputted from the offset control circuit; and a DAC control circuit for receiving, as an input signal, the output digital data outputted from the output processing circuit, and for controlling a level of the output signal of the DAC circuit, wherein the quantizer comprises two or more comparators for making a comparison between a level of the signal obtained by adding the offset signal to the output signal of the variable gain circuit, and each of reference voltages of a reference voltage group, wherein the offset control circuit generates a control signal for the present sampling based on the output digital data of the output processing circuit and the control signal for the preceding sampling time, which has been outputted to the offset addition circuit, wherein the offset addition circuit outputs the offset signal having a voltage responsive to the control signal outputted from the offset control circuit, and wherein the offset signal of the offset addition circuit is controlled by the offset control circuit for each sampling time so that the quantizer operates without causing a saturation operation with the output signal of the integration circuit falling within a determinable input range of the quantizer, and as a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.