Patent ID: 7444533

Claim:
A device for the sampling of data sequenced by a clock signal HA and transmitted from a unit of equipment A to a unit of equipment B with maintenance of binary integrity, the device comprising: means for synthesizing, from a reference clock signal HB, of N clock signals HLi with frequency equal to the frequency of HB, this precision being substantially equal to the precision of HB, each clock signal ranked n having a leading edge offset by a time interval Δt, respectively in advance or delayed relative to the clock signals ranked n−1 or n−1, means to deliver a local clock signal HLS, this clock signal being equal to a clock signal HL n selected from among the N synthesized clock signals HL i , the selection of the clock signal HL n being possibly modified periodically, the choice of a selected clock signal HL n being maintained between two selections, means to synthesize an advance/delay command enabling the choice of the clock signal HL i that is to be selected as a function of the result of the time difference between the leading edge of the clock signal HLS and that of the clock signal HA, and means to generate a signal enabling the periodic validation of a new selection of a clock signal HL i , as a function of the value of the advance/delay command.