Patent ID: 7671660

Claim:
A logic assembly comprising: a logic circuit comprising a plurality of switches of a single threshold and a single conductivity type, wherein the switches comprise: a first switch having a main current path and a control terminal, wherein a first end of the main current path of the first switch is coupled to a first power supply line, a second end of the main current path of the first switch is directly coupled to an output node of the logic circuit, and the control terminal of the first switch is coupled to clock circuitry to receive a first clock signal; a second switch having a main current path and a control terminal, wherein a first end of the main current path of the second switch is directly coupled to the output node of the logic circuit, a second end of the main current path of the second switch is coupled to a second power supply line, and the control terminal of the second switch is coupled to the clock circuitry to receive a second clock signal, wherein the first and second clock signals are mutually non-overlapping clock signals; an output boosting circuit coupled to the logic circuit, wherein the output boosting circuit comprises circuit elements of the single threshold and the single conductivity type to boost an output signal of the logic circuit, wherein the output boosting circuit comprises: a capacitive means for enabling supply of an additional charge to the output signal of the logic circuit; and a bootstrapping circuit coupled to the capacitive means, the bootstrapping circuit to enable an additional supply of charge to a first end of the capacitive means to generate a boosted voltage at a second end of the capacitive means.