Patent ID: 8745356

Claim:
A system comprising: a main memory; and a processor coupled to the main memory, the processor including an address translation buffer for translating a virtual address to a corresponding physical address, the address translation buffer comprising: a random access memory including a first area with a plurality of first entries storing a first plurality of address translation pairs of a virtual address to be searched and a physical address corresponding to the virtual address, each of the first address translation pairs being subjected to a index tag which is a part of the virtual address to be searched, and a second area with a plurality of second entries storing a second plurality of address translation pairs, each of the second address translation pairs being subjected to a whole part of the virtual address to be searched; a search unit that searches the first area for an address translation pair by using a index tag included in a virtual address to be translated, and searches the second area for the address translation pair by using a whole part of the virtual address to be translated; a holding unit that holds a part of the address translation pairs stored in the second area; and a second search unit that searches the holding unit for the address translation pair corresponding to the virtual address to be translated.