Patent ID: 8514386

Claim:
A method for verifying the internal microstructure of interconnects in flip-chip applications, the method comprising: providing a microelectronic assembly comprising: a substrate comprising an array of flip-chip attach pads and a process control pad; a flip chip comprising an array of solder bumps in contact with the array of flip-chip attach pads; a representative solder bump on the process control pad and positioned such as to enable top-side inspection of the representative solder bump after the microelectronic assembly has undergone a reflow cycle, the representative solder bump having substantially the same chemical composition as the array of solder bumps; applying a reflow cycle to the microelectronic assembly to melt and solidify the array of solder bumps and the representative solder bump; and optically inspecting a surface texture of the representative solder bump to determine the internal microstructure of the array of solder bumps.