Patent ID: 7589423

Claim:
A semiconductor device comprising: semiconductor elements formed in a semiconductor substrate; grooves formed in the semiconductor substrate such that the grooves define active regions, first dummy regions, second dummy regions and third dummy regions and such that the semiconductor elements are formed in the active regions; element isolation insulating films are filled in the grooves; and a first interlayer insulation film formed over the semiconductor elements, wherein a planar size of each first dummy region is larger than a planar size of each second dummy region, wherein a planar size of each third dummy region is larger than a planar size of each first dummy region, wherein each and every one of the first dummy regions has a same planar size, wherein each and every one of the second dummy regions has a same planar size, wherein each and every one of the third dummy regions has a same planar size, and wherein the first dummy regions, the second dummy regions and the third dummy regions are formed regularly, respectively, wherein first and second wirings are formed over the first interlayer insulation film, respectively, wherein the first wirings are electrically connected with the semiconductor elements, wherein the second wirings are not electrically connected with the semiconductor elements, wherein the first and second wirings are formed at a same layer, and wherein the first wirings are formed regularly.