Patent ID: 7404250

Claim:
A method of fabricating a printed circuit board having a via, the method comprising: assembling a plurality of layers configured in a stack so that the plurality of layers has a top conductive layer and the bottom conductive layer and at least one conductive layer within the stack; forming a hollow via through the plurality of layers, the hollow via having an interior surface defining a space; applying a conductive material to the interior surface, the conductive material connecting to the at least one conductive layer within the stack; within the hollow via, inserting a conductor coated with non-conductive material; covering the top conductive layer and the bottom conductive layer with dielectric layers; covering the top conductive layer and the bottom conductive layer with a masking agent; plating on the top conductive layer and the bottom conductive layer with a conductive material that physically and electrically connects to the conductor coated with nonconductive material; and removing the masking agent from the top conductive layer and the bottom conductive layer.