Patent ID: 7115501

Claim:
A method for fabricating an integrated circuit device, comprising: a) providing an electrically conductive substrate; b) depositing an insulation layer on the substrate; c) etching depressions into the insulation layer which have a structure depth corresponding to a layer thickness of the insulation layer; d) depositing a contact-making layer onto the patterned insulation layer and onto the substrate in the depressions, the depressions having first lateral dimensions which are less than a layer thickness of the contact-making layer and second lateral dimensions which are significantly greater than the layer thickness; e) etching back the contact-making layer such that e1) the contact-making layer is preserved in the structures with the depressions which have the first lateral dimensions, and e2) the contact-making layer is removed in the structures with the depressions which have the second lateral dimensions; and f) depositing a connecting layer on the substrate in the depressions which have the second lateral dimensions on the patterned insulation layer and on the etched-back contact-making layer which is included in the depressions having the first lateral dimensions.