Patent ID: 6895420

Claim:
A logic circuit for use in a multiplexer to shift data, comprising: a plurality of dual Domino complementary metal oxide semiconductor (CMOS) logic gates each logic gate receiving data inputs and control signals, wherein each data input line is connected only to a single data field effect transistor (FET), and wherein the control signals include a plurality of control lines to provide for multiple shifting operations; and a plurality of shared data lines connecting the logic gates, the shared data lines providing a portion of the data inputs for each of the logic gates by connecting data inputs among the plurality of logic gates; wherein the logic gates shift data received at the data inputs based upon the control signals and the connections of the shared data lines to produce a shifted data output, and wherein all of the plurality of logic gates share a single data transistor for each data input, and wherein each of the logic gates receives one data input using the single data transistor and receives other data inputs from adjacent logic gates using the plurality of shared data lines to reduce the number of data transistors required wherein each of the logic gates provides complementary outputs as the shifted data output.