Patent ID: 8170425

Claim:
An optical signal receiving circuit, comprising: a current-voltage conversion circuit that receives as an input a current signal outputted from a photoelectric conversion circuit for receiving and converting an optical signal into a current signal and converts the current signal into a voltage signal; a voltage generation circuit for generating a direct current voltage of the voltage signal outputted from the current-voltage conversion circuit; a differential amplifying circuit that receives as inputs a first voltage signal outputted from the current-voltage conversion circuit and a second voltage signal outputted from the voltage generation circuit and outputs a differential voltage signal by amplifying a differential component of the first and second voltage signals; an output driver circuit for driving a subsequent IC by receiving as an input the voltage signal outputted from the differential amplifying circuit; and a first feedback loop for controlling a gain of the current-voltage conversion circuit based on the first voltage signal, wherein the current-voltage conversion circuit is equipped with two sets of phase compensation circuit each consisting of a MOS transistor and a capacitance, wherein the current-voltage conversion circuit further includes an amplifying circuit made up of series connection of an inverting amplifier and a buffer circuit; a feedback resistor connected between an input and an output of the amplifying circuit; and a first MOS transistor connected in parallel to the feedback resistor, wherein a first phase compensation circuit that is one of the two sets of phase compensation circuits includes a second MOS transistor and a first capacitance that are connected between the input and output of the inverting amplifier, wherein a second phase compensation circuits that is the other of the two sets of phase compensation circuits includes a third MOS transistor and a second capacitance that are connected in parallel to a load resistor of the inverting amplifier, and wherein a direct current voltage signal according to an average level of an input current signal is applied in common on respective gates of the second and third MOS transistors.