Patent ID: 6972594

Claim:
A level-shifting circuit, comprising: a level modulating circuit having an input terminal and an inverse input terminal for respectively receiving a complementary pair of small signals, and a first output terminal for outputting a voltage level in response to the complementary pair of small signals, wherein the level modulating circuit comprises: a first PMOS transistor having a first gate coupled to the input terminal, a first source coupled to a power source and a first drain as the second output terminal; a second PMOS transistor having a second gate coupled to the inverse input terminal, a second source coupled to the power source and a second drain as the first output terminal; a first NMOS transistor having a third gate coupled to the power source, a third drain coupled to the first drain and a third source as the inverse input terminal; and a second NMOS transistor having a fourth gate coupled to the power source, a fourth drain coupled to the second drain and a fourth source as the input terminal; and an enable circuit making the first output terminal output a predetermined voltage level signal when receiving a disable signal, wherein the enable circuit comprises: a MOS transistor having a fifth source and a fifth drain coupled between an external level and one of the first output terminal and the second output terminal, and a fifth gate coupled to the disable signal; and a pair of third NMOS transistors having sixth drains respectively coupled to the input terminal and the inverse input terminal, sixth sources coupled to the complementary pair of small signals, and sixth gates coupled to the disable signal.