Patent ID: 8867282

Claim:
A semiconductor apparatus with an open bit line structure, comprising: a memory bank including a plurality of memory cell blocks and dummy mats, wherein a plurality of bit lines are formed in the plurality of memory cell blocks and dummy mats; a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference; and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode, wherein, when a test operation is performed with respect to the semiconductor apparatus, the dummy word line driving unit deactivates a dummy word line signal and applies a deactivated dummy word line signal to the dummy mat, wherein the dummy word line driving unit comprises: a complementary dummy word line signal generation section configured to generate a preliminary complementary dummy word line signal in response to a plurality of test mode signals; a level shifter section configured to shift a level of the preliminary complementary dummy word line signal, which is output from the complementary dummy word line signal generation section, and generate a complementary dummy word line signal; and a driving section configured to invert a level of the complementary dummy word line signal, which is output from the level shifter section, and generate a dummy word line signal.