Patent ID: 8451657

Claim:
A nonvolatile semiconductor memory device, comprising: an MIS transistor having nodes that are a gate node, a first drain/source node, and a second drain/source node; a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes in a first operation to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes in a second operation, with potentials applied to the first and second drain/source nodes being swapped from the first operation, to cause a second current to flow through the MIS transistor in a second direction opposite the first direction; a first capacitor connected to the MIS transistor during the first operation to be charged with the first current; a second capacitor connected to the MIS transistor during the second operation to be charged with the second current; and a sense circuit connected to the first and second capacitors and configured to produce a signal responsive to a difference between the first current and the second current.