Patent ID: 7366843

Claim:
A computer system comprising: a system memory; a first active device configured to access data stored in the system memory, wherein the first active device includes a first cache configured to store data accessed by the first active device; an address network for conveying address packets between the first active device and the system memory; a data network for conveying data packets between the first active device and the system memory; a second active device including a second cache; wherein the first cache is configured to transition an access right corresponding to a given block allocated in the first cache in response to a corresponding data packet being received by the first cache; wherein the first cache is configured to transition an ownership responsibility for the given block allocated in the first cache in response to a corresponding address packet being received by the first cache, wherein the first cache is configured to transition the access right at a different time than the ownership responsibility transitions; wherein the first cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet; and wherein the second active device is configured to assign the timestamp to the corresponding data packet and to send the timestamp and the corresponding data packet on the data network to the first active device.