Patent ID: 7900026

Claim:
An information processing system, comprising: an indirect branch instruction address received as input by a branch target buffer and a branch history table; the branch target buffer comprising a last next address for the indirect branch instruction and for providing a first predicted branch target address for the indirect branch instruction; the branch history table comprising local past target information of the indirect branch instruction and indexed by branch addresses; a next branch target table operatively coupled with the branch history table, said next branch target table comprising potential branch targets based on a branch history of previous branches and providing a second predicted branch target address; an exclusion table predictor operatively coupled with both the branch target buffer and the branch history table for keeping track of prediction accuracy of both, wherein said exclusion table predictor inhibits update of inefficient entries in both the branch target buffer and the next branch target table; and a multiplexer for: receiving the first predicted branch target address from the branch target buffer; receiving the second predicted branch target address from the next branch target table; receiving a select signal from the exclusion table predictor for selecting which of the predicted branch target addresses to provide as an output; and providing the selected predicted branch target address.