Patent ID: 7928941

Claim:
A driving circuit of an electro-optical device, the driving circuit comprising: a plurality of rows of scanning lines; a plurality of columns of data lines; a plurality of capacitive lines provided in correspondence with the plurality of rows of scanning lines; pixels provided in correspondence with intersections of the plurality of rows of scanning lines and the plurality of columns of data lines, each of the pixels including: a pixel switching element of which one end is connected to the data line corresponding thereto and which becomes a conduction state when the scanning line corresponding thereto is selected, a pixel capacitor interposed between the pixel switching element and a common electrode, and a storage capacitor interposed between one end of the pixel capacitor and the capacitive line provided in correspondence with the scanning line; a scanning line driving circuit which selects the scanning lines in predetermined order; a capacitive line driving circuit which selects a first feed line when one scanning line is selected, selects a second feed line until the one scanning line is selected again after selecting a scanning line, which is separated from the one scanning line by a predetermined row and is selected after the one scanning line, and applies voltages of the selected feed lines, with respect to the capacitive line corresponding to the one scanning line; and a data line driving circuit which supplies data signals corresponding to gradations of the pixels to the pixels corresponding to the selected scanning line via data lines, wherein the capacitive line driving circuit includes first to fourth transistors in correspondence with each of the capacitive lines, the first transistor corresponding to one capacitive line includes a gate electrode which is connected to a scanning line separated from the scanning line corresponding to the one capacitive line by a predetermined row and a source electrode which is connected to an on-voltage feed line for feeding an on voltage for turning on the fourth transistor, the second transistor includes a gate electrode which is connected to the scanning line corresponding to the one capacitive line and a source electrode which is connected to an off-voltage feed line for feeding an off voltage for turning off the fourth transistor, the third transistor includes a gate electrode which is connected to the scanning line corresponding to the one capacitive line and a source electrode which is connected to the first feed line, the fourth transistor includes a gate electrode which is commonly connected to drain electrodes of the first and second transistors and a source electrode which is connected to the second feed line, and drain electrodes of the third and fourth transistors are connected to the one capacitive line.