Patent ID: 7830922

Claim:
A receiving unit receiving packets including a device for producing, from received packets, a clock signal, the device including: a clock signal generator for generating a clock signal having a controllable frequency, a delay determining unit determining the delays of received packets in relation to the clock signal, the delays of most recently received packets forming a delay distribution ranging from a current minimum delay value to larger delay values, and an evaluating and control signal producing unit for evaluating delays and for producing a control signal provided to the clock signal generator based on the delays, the evaluating and control signal producing unit including: means for determining a characteristic delay value, which is characteristic of the delay distribution and for producing the control signal from the characteristic delay value, wherein the characteristic delay value is determined as an average of all of the time delays of the distribution less than a variable threshold value obtained for a predetermined share of received packets; and an evaluating unit including: a memory or memory cell for holding a variable threshold value, a comparing unit for comparing the determined delay of a received packet to the threshold value, an adaptation unit connected to the comparing unit for adiustinq the threshold value dependent on a result of the comparing, and an averaging unit or low pass filter connected to the comparing unit for determining an average or filtered value of delays of selected ones of received packets, the selecting being dependent on the result of the comparing, wherein the variable threshold value defines the number of time measurement values to be utilized by the averaging unit or low pass filter to determine the average or filtered value of the delays.