Patent ID: 8810289

Claim:
An apparatus comprising: a digital electronic component configured to produce a clock signal; a first counter configured to output a first count signal based on the clock signal; a second counter configured to output a second count signal based on the clock signal; and a power on reset logic configured to provide a power on reset signal based on the first count signal and the second count signal, wherein the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power; wherein the power on reset logic is configured to generate the power on reset signal upon determining: that the first counter has counted to a first pre-determined value, that the first counter has reset the second counter to a second value, that the first counter has counted to the second value, and that a difference between a value of the first counter and a value of the second counter equals a pre-determined value at a point in time that the first counter has counted to the second value.