Patent ID: 7524715

Claim:
A method of forming a memory cell transistor of a DRAM device, the method comprising the steps of: forming a gate stack pattern on a semiconductor substrate; forming source/drain ion injection regions to be electrically connected to a DC node and to a BC node, respectively, substantially under lateral side walls of the gate stack pattern and substantially in a surface of the semiconductor substrate; forming plug ion injection regions that extend no further than inner edges of the lateral side walls by implanting an impurity of substantially same type in the source/drain ion injection regions; and forming a compensation ion injection region in the plug ion injection region to be connected to the DC node, wherein source/drain junction regions comprise the source/drain ion injection regions, respectively, and plug ion injection regions, and profiles of the source/drain junction regions to be electrically connected to the DC node have different profiles than source/drain junction regions to be electrically connected to the BC node, respectively, wherein the plug ion injection region formed under the BC node is deeper than the plug ion injection region formed under the DC node.