Patent ID: 8541285

Claim:
A method for manufacturing a semiconductor memory device, the method comprising: forming a gate insulating film on a semiconductor substrate having a first region in which a first circuit element having a double-layer gate structure is formed and a second region in which a second circuit element having a single-layer gate structure is formed; forming, in the first region, a first gate electrode layer on the gate insulating film; forming, in the second region, a third gate electrode layer; forming, in the first and second regions, element isolation grooves so as to penetrate through the first and third gate electrode layers and the gate insulating film and so as to reach into the semiconductor substrate; forming, in the first and second regions, first and second element isolation insulating films in the element isolation grooves that divide the first and second device regions with each other, respectively; removing upper portions of the first and second element isolation insulating films so that upper surfaces of the first and second element isolation insulating films are aligned with an upper surface of the third gate electrode layer; selectively removing the upper portions of the first element isolation insulating films so that the upper surfaces of the first element isolation insulating films are lower than an upper surface of the first gate electrode layer; forming a first inter-electrode insulating film on the first gate electrode layer and on the first element isolation insulating films; forming a second inter-electrode insulating film on the third gate electrode layer; removing a natural oxide film formed on a surface of the third gate electrode layer; forming a second gate electrode layer on the first inter-electrode insulating film; and forming a fourth gate electrode layer on the third gate electrode layer and on the second element isolation insulating films, wherein, by the forming the third gate electrode, in a direction perpendicular to a main surface of the semiconductor substrate, a thickness of the third gate electrode layer from the gate insulating film to an under surface of the second inter-electrode insulating film that is closest to the semiconductor substrate is larger than a thickness of the first gate electrode layer from the gate insulating film to an under surface of the first inter-electrode insulating film that is closest to the semiconductor substrate, and wherein, by the forming the gate insulating film, the gate insulating film is formed completely on a single plane parallel to a surface of the semiconductor substrate between source/drain regions of the second circuit element.