Patent ID: 8811093

Claim:
A non-volatile memory device comprising: a semiconductor substrate of a first conductivity type; an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising: a first region on a surface of the semiconductor substrate of a second conductivity type; a second region on the surface of the semiconductor substrate of the second conductivity type; a channel region between the first region and the second region; a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region; a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region; a coupling gate overlying the floating gate; an erase gate overlying the second region and insulated therefrom; a bit line connected to the first region; a negative charge pump circuit for generating a first negative voltage; and a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the word line of the unselected memory cells, in response thereto.