Patent ID: 8368204

Claim:
A chip comprising: a silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug; a first dielectric layer over said silicon substrate, wherein said first dielectric layer comprises a portion between said first and second copper layers, wherein said copper plug is in said first dielectric layer; an insulating layer over said silicon substrate and over said metallization structure, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said insulating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening; a first circuit layer over said insulating layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said first circuit layer, wherein said first circuit layer comprises a first trace portion, a first via portion between said first trace portion and said first contact point and a second via portion between said first trace portion and said second contact point, wherein said first trace portion has a thickness greater than 1 micrometer, wherein said first circuit layer comprises a third copper layer and a first conductive layer under said third copper layer and at a sidewall of said first trace portion; a second circuit layer over said first circuit layer and said insulating layer, wherein said second circuit layer comprises a second trace portion, a third via portion at a bottom of said second trace portion, wherein said second trace portion has a thickness greater than 1 micrometer, wherein said second circuit layer comprises a fourth copper layer and a second conductive layer under said fourth copper layer and at a sidewall of said second trace portion; and a second dielectric layer over said insulating layer, wherein said second dielectric layer comprises a portion between said first and second circuit layers.