Patent ID: 7372341

Claim:
A clock circuit comprising: a phase detector coupled to receive a reference clock signal and an output clock signal and configured to provide a phase signal indicative of a phase difference between the reference clock signal and the output clock signal; and an output unit configured to provide the output clock signal, wherein the output unit is coupled to a first supply voltage node and a second supply voltage node, and wherein the output unit includes: a biasing circuit coupled to receive a control voltage based on the phase signal and configured to generate, based on the control voltage, a bias voltage on a bias voltage node, wherein the bias voltage is decoupled from the second supply voltage node, wherein the biasing circuit includes an amplifier having an inverting input, a non-inverting input, and an output, wherein the inverting input is coupled to receive the control voltage; and a voltage-controlled element coupled to the first supply voltage node and the bias voltage node, and wherein the voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage.