Patent ID: 7777136

Claim:
An electrical structure, comprising: a first 2S1P substructure, comprising a first dielectric layer, a first power plane within the first dielectric layer, a top signal plane on a top surface of the first dielectric layer, a bottom signal plane on a bottom surface of the first dielectric layer, and a first electrically conductive via; a second 2S1P substructure, comprising a second dielectric layer, a second power plane within the second dielectric layer, a top signal plane on a top surface of the second dielectric layer, a bottom signal plane on a bottom surface of the second dielectric layer, and a second electrically conductive via; a joining layer having first and second opposing surfaces and an electrically conductive plug therethrough, wherein the joining layer comprises a liquid crystal polymer (LCP) dielectric material, wherein the first opposing surface of the joining layer is directly bonded to the first dielectric layer of the first 2S1P substructure with no extrinsic adhesive material bonding the joining layer to the first dielectric layer, wherein the second opposing surface of the joining layer is directly bonded to the second dielectric layer of the second 2S1P substructure with no extrinsic adhesive material bonding the joining layer to the second dielectric layer, and wherein the electrically conductive plug electrically couples the first electrically conductive via to the second electrically conductive via, the LCP dielectric material being heated to a temperature less than a liquid crystal transition temperature; and the first electrically conductive via comprises a first plated through hole that electrically couples the top and bottom signal planes of the first 2S1P substructure, and the second electrically conductive via comprises a second plated through hole that electrically couples the top and bottom signal planes of the second 2S1P substructure, the first and second plated through holes being plated along a length of a thickness of each the first and second 2S1P substructures, respectively, and the first and second plated through holes contacting the top and bottom signal planes on the first and second dielectric layers, respectively.