Patent ID: 8040731

Claim:
A nonvolatile semiconductor memory comprising: a voltage step-up circuit to generate a first voltage; a voltage step-down circuit including a first circuit to achieve a first voltage drop and a second circuit to achieve a second voltage drop and configured to decrease the first voltage to a second voltage less than the first voltage; a transfer transistor to receive the first voltage at its gate and to transfer the second voltage to a word line; and a control circuit to generate the second voltage as a first write voltage by the first and second circuit in a first mode wherein the first write voltage less than or equal to a prescribed magnitude is applied to the word line, and to generate the second voltage as a second write voltage by one of the first and second circuits in a second mode wherein the second write voltage greater than the prescribed magnitude is applied to the word line; wherein the difference between the first voltage and the second voltage is greater than or equal to the threshold voltage of the transfer transistor.