Patent ID: 8731003

Claim:
An arrangement for adjusting a clock signal of a first network element of a communications network, the first network element being arranged to receive synchronisation messages from at least two other network elements and comprising an adjustable clock signal source to produce the clock signal, the arrangement comprising a processor device arranged to: produce a control variable containing information about synchronisation messages received from the at least two other network elements, adjust the clock signal based on an arithmetic difference between the control variable and a reference value of the control variable, determine which portion of the reference value of the control variable corresponds to synchronisation messages received from each of the at least two other network elements, and in response to a situation where the first network element ceases to receive from one of the at least two other network elements synchronisation messages meeting a predetermined quality criterion, change the reference value of the control variable by an amount equalling a portion of the reference value of the control variable, which portion corresponds to the network element from which the first network element has ceased to receive synchronisation messages meeting the predetermined quality criterion.