Patent ID: 7401273

Claim:
A data processing apparatus comprising: processing logic operable to perform a data processing operation; a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic and operable to sample a value of an associated digital signal generated by the processing logic at that predetermined point; each of said sampling circuits including a backup latch operable to store a backup copy of the associated digital signal value, and at least one of the sampling circuits being operable to temporally sample the value of the associated digital signal at a first time and at at least one later time and to store as the backup copy a selected one of the sampled values representing a correct value, the value of the associated digital signal sampled at the first time being initially output from that sampling circuit; the at least one of the sampling circuits being operable to determine an occurrence of an error in the value of the associated digital signal sampled at the first time, and to issue an error signal upon determination of said error, the data processing apparatus further comprising: error recovery logic operable in response to the error signal to implement a recovery procedure during which selected sampling circuits are operable to output as their sampled associated digital signal value the value stored in their backup latch.