Patent ID: 7602534

Claim:
An interface circuit device to perform input/output of a signal representing image data, comprising: a CPU, a plurality of buses for wiring said CPU and an image memory; a plurality of SSTL (stub series terminated logic) circuits each of which are provided corresponding to each of said plurality of buses; and a reference power apparatus for applying a reference voltage to each of said plurality of SSTL circuits, each of said plurality of SSTL circuits having: a receiver for comparing: i) an input voltage obtained based on an input signal inputted to a corresponding bus and said reference voltage; and ii) a comparison voltage, and outputting an output signal corresponding to a comparison result to said image memory; and a resistance for electrically connecting said reference power apparatus and a location between said receiver and said CPU on a corresponding bus, and when a SSTL circuit corresponding to said image data among said plurality of SSTL circuits is classified pixel by pixel constituting said image data, one or more SSTL circuits corresponding to either one of two adjoining pixels are provided on the input side, and have an inverting element for inverting said input signal and changing a corresponding pixel into an inverted pixel.