Patent ID: 7460406

Claim:
A method of concurrently determining the state of a plurality of multi-state memory cells from a memory array, wherein said plurality of memory cells are connected along a common word line, have sources connected to a common source line, and are formed along distinct bit lines, the method comprising: discharging the memory cells to ground through the corresponding bit lines; subsequently applying a first voltage level to the common source line; subsequently applying a second voltage level to the word line; in response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a first subset of said multi-states; subsequently applying a third voltage level to the word line, wherein the third voltage level differs from the second voltage level; and in response to applying the third voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.