Patent ID: 7030655

Claim:
A semiconductor device comprising: a transmitter capable of encoding first and second input signals as a plural-bit symbol signal responsive to first and second clocks, respectively, the first clock being out of phase from the second clock; and a receiver capable of generating first and second output signals by decoding the symbol signal responsive to third and fourth clocks, respectively, and capable of generating first and second even and odd data; where the receiver comprises: a first receiving circuit capable of generating the first output signal by manipulating the symbol signal responsive to the third and a fifth clocks, the fifth clock being out of phase from the third clock, the first receiving circuit being adapted to generate the first even and odd data responsive to the third and fifth clocks, respectively; and a second receiving circuit capable of generating the second output signal by manipulating the symbol signal responsive to the fourth and a sixth clocks, the sixth clock being out of phase from the fourth clock, the second receiving circuit being adapted to generate the second even and odd data responsive to the fourth and sixth clocks, respectively; and where the first receiving circuit comprises: a first detector capable of generating the first even and odd data according to a medium reference voltage; a second detector capable of generating first select signal by detecting midlevel data according to high and low reference voltages; and a multiplexer capable of selecting between the first even and the second odd data and the first odd and the second even data responsive to the select signal.