Patent ID: 8719748

Claim:
A method of designing VLSI clock distribution networks, comprising the steps of: (a) obtaining a set of clock distribution network design criteria; (b) laying out an initial clock grid network; (c) implementing and sizing input buffers; (d) placing and implementing LC tanks to resonate with said clock grid network laid out in step (b); (e) resizing the input buffers in view of LC tanks placed in step (d) based on the results of an AC analysis; (f) checking whether the clock distribution network design criteria are met when using the resized input buffers; (g) if the clock distribution network design criteria are met in step (f), implementing a VLSI clock distribution network using the clock grid network, resized input buffers, and placed and implemented LC tanks; and (h) if the clock distribution network design criteria are not met in step (f), looping back to step (d).