Patent ID: 8217430

Claim:
An integrated circuit (IC) chip having a plurality of memory cell array blocks, the IC chip comprising: a first memory cell array block having a first set of power lines including at least a pair of a positive high supply voltage (Vdd) line and a complementary low supply voltage (Vss) line, the Vdd and the Vss lines being formed on a first metal layer; a second memory cell array block having a second set of power lines including at least a pair of the Vdd and the Vss lines, the second memory cell array block being disposed next to the first memory cell array block, wherein the power lines have both horizontal sections and vertical sections on a same power line; a cell partition area disposed between the first and the second memory cell array blocks; and at least one signal line formed on the first metal layer, wherein no power lines serving the first or the second memory cell array block are routed across the cell partition area, such that the at least one signal line on the first metal layer is routed in both horizontal and vertical directions across the cell partition area.