Patent ID: 8836137

Claim:
A three-dimensional stacked multichip module comprising: a stack of integrated circuit die including W integrated circuit die, W being an integer greater than 1, each of the W integrated circuit die in the stack comprising a patterned conductor layer over a substrate, the patterned conductor layer comprising an electrical contact region, the electrical contact region comprising electrical conductors, at least one of the electrical conductors comprising a landing pad; the stack of die comprising a first die at one end of the stack and a second die at the other end of the stack, the substrate of the first die facing the patterned conductor layer of the second die; the landing pads on each die being aligned with those on the other die in the stack; W electrical connectors extending from a surface of the stack of die and into the stack of die to electrically contact the landing pads on the W integrated circuit die, to create a three-dimensional stacked multichip module having W die levels, the electrical connectors comprising lengths of substantially homogeneous electrically conductive material which lack physical boundaries between the die levels; and each of the W electrical connectors being electrically connected to one landing pad of one die level.