Patent ID: 6868032

Claim:
A nonvolatile memory comprising: a memory array; and a control circuit; wherein said control circuit controls performance of operations in accordance with command received from outside; said operations include a read operation, a write operation, and an erase operation; said memory array has a plurality of areas; each of said areas includes a plurality of blocks; each of said blocks includes a plurality of memory cells, each of said memory cells being capable of electrical writing and electrical erasing of data, a first area of said plurality of areas is capable of storing data received from outside to said plurality of memory cells of one block selected in accordance with a logical address received from outside; a second area of said plurality of areas is capable of storing management information, which includes address translation information for address translating said logical address received from outside to a physical address for selecting said one block in said first area in accordance with said logical address; when first address translation information for translating from a first logical address to a first physical address is already stored in a first block in said second area and said control circuit receives a first command for said write operation accompanied with a second logical address and data, said control circuit controls the following operations: reading said first address translation information from said first block in said second area; modifying said first address translation information to second address translation information for translating from said second logical address to a second physical address; and storing said second address translation information into a second block in said second area.