Patent ID: 8738312

Claim:
A phase measuring device, comprising: a buffer delay amount measuring circuit, including a plurality of buffers for being inputted with clock signals, that are synchronized with a reference signal calculated by positioning calculation, at different timings shifted by a fixed delay time, respectively, and being simultaneously inputted with a sampling reference signal of a lower frequency than the clock signals, and for respectively generating state data according to levels of the clock signals at a transition timing of the sampling reference signal, wherein the buffer delay amount measuring circuit outputs delay measurement data comprised of a group of the state data from the plurality of buffers; a phase difference measuring circuit including a first partial phase difference measuring circuit and a second partial phase difference measuring circuit, wherein the first partial phase difference measuring circuit includes a plurality of buffers for being inputted with a first measuring signal among the first measuring signal and a second measuring signal that produce a phase difference therebetween to be measured, being inputted with the clock signals at mutually different timings by the delay amount, and respectively generating state data according to the levels of the clock signals at a transition timing of the first measuring signal, and wherein the first partial phase difference measuring circuit outputs first phase difference measurement data comprised of a group of state data from the plurality of buffers, and wherein the second partial phase difference measuring circuit includes a plurality of buffers for being inputted with the second measuring signal, being inputted with the clock signals at mutually different timings by the delay amount, and respectively generating state data according to the levels of the clock signals at a transition timing of the second measuring signal, and wherein the second phase difference measurement circuit outputs second phase difference measurement data comprised of a group of the state data from the plurality of buffers; and a phase difference calculator for calculating the delay amount between the buffers based on the delay measurement data, and calculating the phase difference based on a difference value of the transition timings and the delay amounts of the clock signals of the first phase difference measurement data and the second phase difference measurement data.