Patent ID: 8635603

Claim:
A computer system comprising: at least one processor; a memory coupled to the at least one processor, the memory being divided into a plurality of memory pages; shared instructions residing in the memory; a plurality of processes residing in the memory and executed by the at least one processor, the plurality of processes executing the shared instructions; a debugger residing in the memory and executed by the at least one processor, the debugger comprising: a breakpoint processing mechanism that installs a breakpoint by recording an original instruction at a desired location in the shared instructions and writing a trap instruction to the desired location in the shared instructions, the breakpoint processing mechanism passing control to the debugger when a process that installed the breakpoint encounters the trap instruction, the breakpoint processing mechanism skipping the trap instruction and executing the original instruction using a scratchpad memory that is at least an order of magnitude smaller than a smallest size of the plurality of memory pages when a process that did not set the breakpoint at the desired location encounters the trap instruction in the shared instructions; and a reference count for the desired location that is incremented by the breakpoint processing mechanism when the breakpoint is installed, that is decremented by the breakpoint processing mechanism when the breakpoint for a given process is removed, wherein the breakpoint processing mechanism replaces the trap instruction with the original instruction in the shared instructions only when the reference count for the desired location is zero, indicating no processes have a breakpoint installed at the desired location.