Patent ID: 8504756

Claim:
A system-on-chip (SoC), comprising: one or more bus masters; at least one high bandwidth bus slave; a high bandwidth bus communicatively coupled to the one or more bus masters and the at least one high bandwidth bus slave; a low bandwidth bus; a bridge circuit coupled between the high bandwidth bus and the low bandwidth bus; and at least one low bandwidth bus slave coupled to the low bandwidth bus, wherein the one or more bus masters are configured to access the at least one low bandwidth bus slave, wherein the one or more bus masters issue an early read transaction request in advance to a scheduled read transaction request associated with one of the at least one low bandwidth bus slave, wherein the bridge circuit is configured to receive the early read transaction request and convert the early read transaction request to a low bandwidth bus read transaction request and send the low bandwidth bus read transaction request to one of the at least one low bandwidth bus slave via the low bandwidth bus to fetch data associated with the early read transaction request, and wherein the bridge circuit is further configured to receive the scheduled read transaction request and convert the scheduled read transaction request to a low bandwidth bus read transaction request, and wherein the fetched data associated with the early read transaction request corresponding to the one of the at least one low bandwidth bus slave is sent to the one or more bus masters via the bridge circuit and the high bandwidth bus upon receiving the scheduled read transaction request.