Patent ID: 6909152

Claim:
A semiconductor device comprising: a semiconductor substrate having an array region and a support region; at least one gate stack on said array region and said support region, said gate stack comprising a gate conductor, a gate cap, and sidewalls surrounded by gate spacers; a first dielectric layer over said at least one gate stack; a second dielectric layer over said first dielectric layer; first and second contact-to-diffusion openings extending through said second dielectric layer to said semiconductor substrate in said support region, wherein said first and second contact-to-diffusion openings comprise contact openings having a substantially continuous vertical wall surface through said first and second dielectric layers; at least one borderless array contact extending from said second dielectric layer to a diffusion area in said array region; and at least one contact-to-gate opening extending from said second dielectric layer between said first and second contact-to-diffusion openings, wherein said first dielectric layer and said second dielectric layer comprise a material chemically reactive with a dielectric etchant, and wherein said gate cap and spacers comprises a material that is substantially unreactive with said dielectric etchant.