Patent ID: 8264250

Claim:
A method of inspecting an array substrate that includes a pixel part disposed in a pixel area and a driving circuit disposed in a first peripheral area adjacent to a first side of the pixel area, the method comprising: applying a first inspection voltage to odd-numbered gate lines through a first inspection line of an inspection circuit during a first inspection time, the inspection circuit being disposed in a second peripheral area adjacent to a second side of the pixel area, which is opposite to the first side with respect to the pixel area; applying a second inspection voltage to even-numbered gate lines through a second inspection line of the inspection circuit during the first inspection time; applying the second inspection voltage to the odd-numbered gate lines through the first inspection line during a second inspection time; and applying the first inspection voltage to the even-numbered gate lines through the second inspection line during the second inspection time, wherein the inspection circuit further includes a third inspection line receiving the first inspection voltage during both the first inspection time and the second inspection time, the first inspection line is connected exclusively to the odd-numbered gate lines among the gate lines, the second inspection line is connected exclusively to the even-numbered gate lines among the gate lines, and an even-numbered gate line among the even-numbered gate lines is disposed between each pair of consecutively numbered odd-numbered gate lines among the odd-numbered gate lines.