Patent ID: 7728424

Claim:
A semiconductor device comprising: a semiconductor substrate that has a first electrode and a second electrode; an insulating film that is formed on a first surface of the semiconductor substrate on which the first electrode and the second electrode are formed, the insulating film having a first opening and a second opening, the first opening being positioned on the first electrode, and the second opening being positioned on the second electrode; a resin protrusion that is formed on the insulating film, the resin protrusion extending along a line and having a first sloping region of which a height decreases along the line as a distance from a center of the resin protrusion increases, the first sloping region being positioned between the center of the resin protrusion and a first end of the resin protrusion; a first interconnect that is electrically connected to the first electrode, a first portion of the first interconnect being disposed on the first electrode, a second portion of the first interconnect being disposed on the insulating film, and a third portion of the first interconnect being disposed on the first sloping region of the resin protrusion, the third portion of the first interconnect being disposed between the first portion of the first interconnect and the second portion of the first interconnect; and a second interconnect that is electrically connected to the second electrode, a first portion of the second interconnect being disposed on the second electrode, a second portion of the second interconnect being disposed on the insulating film, and a third portion of the second interconnect being disposed on the first sloping region of the resin protrusion, the third portion of the second interconnect being disposed between the first portion of the second interconnect and the second portion of the second interconnect, wherein the first interconnect is closer to the center of the resin protrusion than the second interconnect, and a highest portion of the first interconnect is higher than a highest portion of the second interconnect.