Patent ID: 8437163

Claim:
A stack of memory dies comprising: a plurality of select related connection nodes on corresponding memory dies, each being configured to receive a select signal depending on how the dies are arranged in the stack of memory dies and wherein at least one of the select related connection nodes comprises an external select connection node configured to receive a select signal; and a plurality of identification circuits, wherein each of the identification circuits corresponds to a respective one of the memory die of the stack, wherein each of the identification circuits can be coupled to one or more of the plurality of select related connection nodes, depending on how the respective die is arranged in the stack, and wherein each of the identification circuits is configured to determine an identification of its respective memory die responsive to how, if coupled, that identification circuit is coupled to the at least one of the select related connection nodes configured to receive a select signal, wherein the select nodes on one memory die are routed to select nodes on another memory die by routing which is separate from location of the identification circuits.