Patent ID: 8772878

Claim:
A method, comprising: forming a plurality of first cavities adjacent to a first gate electrode structure of a first transistor and a plurality of second cavities adjacent to a second gate electrode structure of a second transistor, said first and second transistors being of different conductivity type; forming a semiconductor material in said pluralities of first and second cavities, said semiconductor material having a first type of strain; creating lattice damage in said semiconductor material selectively in said first transistor to form a substantially relaxed semiconductor material in said plurality of first cavities of said first transistor; forming a substantially continuous strain-inducing material layer above said first transistor, said substantially continuous strain-inducing material layer continuously covering substantially all exposed surfaces of said first transistor; and annealing said substantially relaxed semiconductor material in the presence of said substantially continuous strain-inducing material layer to re-crystallize said substantially relaxed semiconductor material in said plurality of first cavities of said first transistor into a strained state, said strained state corresponding to a second type of strain that is opposite to said first type of strain.