Patent ID: 6977416

Claim:
A semiconductor device including a semiconductor substrate and a plurality of MISFETs, comprising: a first semiconductor layer of a first conduction type formed over a first surface of said semiconductor substrate; a plurality of second semiconductor layers of a second conduction type opposite to said first conduction type, each formed over said first semiconductor layer; a plurality of third semiconductor layers of said first conduction type formed over said second semiconductor layers, respectively; a gate electrode formed between coplanar, adjacent third semiconductor layers; a first insulating film formed over said third semiconductor layer and said gate electrode; a plurality of first grooves each formed in said first insulating film between non-contact, coplanar, adjacent gate electrodes and in contact with said third semiconductor layer; a fourth semiconductor layer of said first conduction type each formed between coplanar, adjacent gate electrodes and in contact with said second semiconductor layer within said first semiconductor layer; a fifth semiconductor layer of said second conduction type formed in contact with a bottom of said first groove within said second semiconductor layer; and a first electrode formed inside said first groove and electrically connected with said third semiconductor layer and said fifth semiconductor layer, wherein said first semiconductor layer and said third semiconductor layer form one selected form the group consisting of a source and drain of said MISFET, and said second semiconductor layer forms a channel-forming region, and wherein said fourth semiconductor layer has an impurity concentration higher than said first semiconductor layer.