Patent ID: 7453159

Claim:
A semiconductor multi-chip package comprising: a package substrate including a surface having a plurality of bonding tips formed thereon; and two or more semiconductor chips mounted on the package substrate surface, at least one of the chips comprising: a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on the semiconductor substrate; a pad-rearrangement pattern directly contacting the bond pad-wiring pattern, the pad-rearrangement pattern including bond pads disposed over at least a part of the cell region; and an insulating layer formed on the pad-rearrangement pattern, wherein the bond pad-wiring pattern is formed on at least a part of the peripheral circuit region, wherein the bond pads included with the pad-rearrangement pattern is exposed through the insulating layer, wherein each bonding tip is electrically connected to a corresponding one of the bond pads.