Patent ID: 8248118

Claim:
A frequency divider comprising: a least significant (LS) stage coupled to receive a first input signal, a first program bit and a first input mode signal, and to generate a first frequency-divided signal and a first output mode signal, wherein the first input mode signal and the first program bit specify a division mode to be used by the LS stage; a plurality of higher significance (HS) divider stages coupled in cascade, wherein each of the plurality of HS divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding input mode signal, wherein the plurality of HS divider stages includes a first divider stage, wherein the first divider stage is coupled to receive the first frequency-divided signal and generates the first input mode signal; and an output stage to receive the first output mode signal and a mode bit, and to generate a first output signal, wherein the output stage generates the first output signal by dividing a frequency of the first output mode signal by two if the mode bit is at one logic level, the output stage forwarding the output mode signal as the first output signal otherwise.