Patent ID: 7796463

Claim:
A memory system comprising: an array of memory cells for retaining data; and a memory read apparatus in communication with said array of memory cells for transferring selected data read from said memory comprising: a data read path circuit in communication with said memory to acquire said selected data read from said memory, synchronize said selected data, and transfer said selected data from said memory; and a memory read control apparatus in communications with said data read path circuit for selecting said data to be read from said memory, for providing self-feedback signals for synchronizing said selected data for transfer from said memory, said memory read control apparatus comprising: a data output latch control circuit receiving an external timing signal to provide a timing signal to said data output latch for synchronization of the transferring of the selected data from said memory; a sense amplifier latch control circuit in communication with said data output latch control circuit to receive a sense amplifier latch clear signal which is combined with a data line sense amplifier enable signal to generate a sense amplifier latch control signal that is communicated to said data line sense amplifier latch to synchronize the selected data read from said memory; and a sense amplifier control circuit in communication with said sense amplifier latch control circuit to provide said data line sense amplifier enable signal to said sense amplifier latch control circuit and to receive said sense amplifier latch control signal from said sense amplifier latch control circuit and in communication with a data line sense amplifier to provide said data line sense amplifier enabling signal to said data line sense amplifier and to said sense amplifier latch control circuit and receive the sense amplifier latch signal from said sense amplifier latch control circuit to indicate that said data line sense amplifier is to be disabled.