Patent ID: 8149036

Claim:
A semiconductor device comprising: a delay locked loop (DLL) configured to compare a phase of a source clock with a phase of a feedback clock and delay the source clock depending on a comparison result to output a DLL clock, the feedback clock being generated by reflecting an actual delay amount of a source clock path in the DLL clock; a phase division unit configured to divide a phase of the DLL clock according to a certain division ratio to generate a first DLL division clock; a clock delay unit configured to delay the first DLL division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second DLL division clock; a duty cycle correction clock generation unit configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first DLL division clock and the second DLL division clock; and a duty cycle correction voltage generation unit configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock.