Patent ID: 7607059

Claim:
An integrated circuit test system comprising: a plurality of scan latches configured as a single scan chain, wherein each of the plurality of scan latches is coupled to a corresponding input of target logic, wherein the plurality of scan latches are configured to receive and store bit patterns; and forcing logic coupled to a first set of the plurality of scan latches and configured to selectively force values stored in the first set of scan latches to desired values, wherein the desired values replace the values in the first set of scan latches, wherein the forcing logic comprises one or more logic gates coupled to the inputs of each of the first set of scan latches, wherein each logic gate is configured to receive as inputs a forcing signal and an output of a preceding one of the plurality of scan latches and to provide an output of the logic gate to a following one of the plurality of scan latches, wherein when the forcing signal is asserted, each of the first set of scan latches is loaded with a predetermined forced value.