Patent ID: 8097949

Claim:
An integrated-circuit device containing an interconnect stack on a substrate, the interconnect stack comprising a plurality of interconnect levels containing a bottom interconnect level at a smallest distance from a reference surface of the substrate and a top interconnect level at a largest distance from the reference surface, metal interconnect line sections, which extend parallel to the reference substrate surface and between intermetal-dielectric layer sections on a respective interconnect level, an upper etch-barrier layer, which is arranged on an upper-intermediate interconnect level below the top interconnect level and which is impermeable for a selective etchant that attacks the intermetal-dielectric layer sections, and a lower etch-barrier layer, which is arranged below the upper-intermediate interconnect level and which is impermeable for the selective etchant, wherein the upper and lower etch-barrier layers each contain at least one etch opening defined by a lateral etch-barrier liner, which extends from the etch opening in the upper etch-barrier layer to the etch opening in the lower etch-barrier layer and which is impermeable for the selective etchant, and wherein airgaps are present on one or more interconnect levels, which are arranged below the lower etch-barrier layer; and further comprising a lateral etch barrier, which is impermeable for the selective etchant, extends from the upper etch-barrier layer to the bottom interconnect level, and laterally limits a region of airgap presence; further comprising metal vias for connecting interconnect line sections of two neighboring interconnect levels, and interlevel-dielectric layer sections extending parallel to the reference substrate surface between the metal vias and between the respective neighboring interconnect levels; wherein the interlevel-dielectric layer sections are made of a material that is permeable for the selective etchant.