Patent ID: 8627172

Claim:
An error correction encoding apparatus, comprising: a data dividing module which divides a transmission data sequence into L-pieces of short sequences; a first encoding module which encodes each of the divided L-pieces of short sequences to encoded sequences of length N by an m-stage quasi-cyclic low density parity check encoding method (L, m are natural numbers, N is a multiple of m), and output those encoded sequences; and a redundant sequence output module which generates a redundant sequence based on each of the encoded sequences of length N outputted from the first encoding module, and outputs the redundant sequence in a same manner as a plurality of encoded sequences outputted from the first encoding module, wherein the redundant sequence output module includes: a data replacing module which inputs the L-pieces of encoded sequences of length N encoded by the first encoding module, and outputs each of the data sequences by changing an order thereof; and a second encoding module which encodes each of the replaced encoded sequences outputted from the data replacing module by the m-stage quasi-cyclic low density parity check encoding method, and outputs those encoded sequences, wherein the data replacing module comprises: a short sequence dividing unit which divides each of the L-pieces of data sequences encoded by the first encoding processing unit into short sequences of length m in a same number as the stage number m of the first quasi-cyclic low density parity check codes; and a data replacement processing unit which changes an order by a unit of (L×N)/m-pieces of short sequences of length m set by the division, and outputs N/m-pieces of sequences of length L×m in maximum.