Patent ID: 7172924

Claim:
A method of fabricating a semiconductor device, comprising: arranging a plurality of elongated leadframes side by side and separate from each other; mounting a plurality of semiconductor chips on the plurality of leadframes so that the semiconductor chips are spaced apart from each other along a direction of elongation of the leadframes, each of the semiconductor chips having a first main surface and a second main surface opposite the first main surface, each of the semiconductor chips having a plurality of electrode pads on the first main surface thereof, the semiconductor chips being mounted so that the second main surface of each of the semiconductor chips faces the leadframes; joining the plurality of electrode pads on the first main surface of each of the semiconductor chips to the plurality of leadframes via bonding wires; separately encapsulating each of the semiconductor chips and the bonding wires so as to form main encapsulation parts; filling a space between adjacent leadframes exposed outside of the main encapsulation parts so as to form interframe encapsulation parts; forming grooves by cutting all of the leadframes directly under the second main surface of each of the semiconductor chips in a direction orthogonal to the direction of elongation of the leadframes; and cutting the leadframes and the interframe encapsulation parts exposed between the main encapsulation parts so as to form a plurality of semiconductor devices each having a first external terminal row formed of the cut leadframes, a second external terminal row formed of the cut leadframes and facing the first external terminal row so as to sandwich one of the grooves therebetween, and one of the semiconductor chips mounted on the first external terminal row and the second external terminal row.