Patent ID: 7595253

Claim:
A method of forming a semiconductor device comprising: patterning a buffer insulation layer and a hard mask layer successively stacked on a substrate to form an opening exposing the substrate; etching the exposed substrate to form a trench defining an active region; forming a filling insulation layer on a surface of the substrate to fill the opening and the trench; planarizing the filling insulation layer until the patterned hard mask layer is exposed to form a filling insulation pattern to fill the trench; forming conformally a capping insulation layer having etch selectivity according to the filling insulation pattern on the surface of the substrate; forming a sacrificial insulation layer on the capping insulation layer, the sacrificial insulation layer filling the opening and having etch selectivity according to the capping insulating layer; planarizing the sacrificial insulation layer to form a sacrificial pattern on the capping insulation layer on the filling insulation pattern; etching the capping insulation layer and the patterned hard mask layer to expose a portion of the patterned buffer insulation layer and sidewall of the sacrificial insulation pattern leaving a capping insulation pattern below the sacrificial insulation pattern; and etching the patterned buffer insulation layer to expose the active region.