Patent ID: 7655547

Claim:
A method of forming an interconnect structure on a substrate, said method comprising: forming an insulator stack above a substrate; depositing a hardmask over said insulator stack; patterning a trough into said hardmask; depositing a photoresist layer over said trough; patterning a via in said photoresist layer such that said via is positioned within said troughs; etching said via completely through said insulator stack, wherein said via comprises a top portion, a bottom portion below said top portion, sidewalls and a bottom surface; forming a first conductive layer lining said bottom portion only of said via such that said first conductive layer comprises vertical sections adjacent to said sidewalls in said bottom portion and a horizontal section that extends between said vertical sections and covers said bottom surface; after said forming of said first conductive layer, etching said trough into said insulator stack to a depth above said bottom portion of said via and, thereby above said first conductive layer; and filling said trough and said via with a second conductive layer in order to create said interconnect structure with said first conductive layer lining said bottom portion only of said via and preventing said second conductive layer from contacting said bottom surface.