Patent ID: 8502585

Claim:
A device, comprising: a flip flop comprising a flip flop data input terminal and a flip flop clock input terminal; a control circuit comprising a control circuit data input terminal and a control circuit clock input terminal; wherein the control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal, and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal; and wherein the device is configured to set, in the Data Processing Mode and directly before switching into the Data Retention Mode, the clock signal to a value leading at the flip flop clock input terminal to a signal value equal to the second given fixed signal value, such that, when switching from the Data Processing Mode to the Data Retention Mode, the signal at the flip flop clock input terminal remains constant.