Patent ID: 7122423

Claim:
Method for fabricating a memory cell, comprising the steps of: a) etching a trench-like recess, which has side walls and a base, into a substrate; b) depositing a first protective layer at the inner surfaces of the trench-like recess; c) etching anisotropically the first protective layer, in such a manner that the first protective layer is removed at the base of the trench-like recess but is retained at the side walls of the trench-like recess; d) filling the trench-like recess with an electrically conductive material in such a manner that an electrical contact is provided between the electrically conductive material and the substrate; e) etching isotropically back the conductive material to a predetermined filling height; f) removing the first protective layer in such a manner that the conductive material is retained as a projection in the trench-like recess, spaced apart from the side walls of the trench-like recess; g) depositing a dielectric layer on the side walls of the trench-like recess, the base of the trench-like recess and the surfaces of the conductive material; and h) depositing an electrode layer on the dielectric layer, in which method, prior to step g) of depositing a dielectric layer, a second protective layer is deposited nonconformally in an upper region of the trench-like recess, an embedded electrode is produced by means of gas phase doping in the trench-like recess, and the second protective layer is removed again by wet-chemical means.