Patent ID: 8312240

Claim:
A multi chip package comprising: a system LSI chip including a common memory controller capable of controlling chips including a respective memory among different types of memories operating with different specifications, the common memory controller comprising: a first interface portion that receives a controller output signal to access the chips from a controller, and outputs a controller input signal to the controller; a second interface portion that outputs a memory input signal through a common bus terminal portion coupled to the chips and receives a memory output signal through the common bus terminal portion; an operation memory portion that outputs a first control signal including specifications of the memories; an arbiter that outputs a second control signal and a third control signal; a conversion control portion that converts the controller output signal into the memory input signal in response to at least one of the first control signal and the second control signal, and converts the memory output signal respectively into the controller input signal; and a signal holder that holds the controller output signal in response to at least one of the third control signal and a fourth control signal from the conversion control portion, wherein the memory input signal includes a first memory input signal corresponding to a first memory and a second memory input signal corresponding to a second memory, type of which is different from the type of the first memory.