Patent ID: 7368792

Claim:
A metal-oxide semiconductor (MOS) transistor having an elevated source/drain structure, comprising: a gate dielectric on an active region of a semiconductor substrate; a gate electrode on the gate dielectric; a first gate spacer on a lateral side surfaces of the gate electrode; a first epi-layer on the semiconductor substrate; a second gate spacer on lateral side surfaces of the first gate spacer; a second epi-layer on the first epi-layer; a source/drain extension layer formed by a dopant ion-implanting process, said source/drain extension layer being positioned under the first epi-layer and partially overlapped by a lower portion of the gate electrode; and a deep source/drain layer formed by deeply ion-implanting a dopant through the second epi-layer in a portion of the semiconductor substrate positioned under the second epi-layer, a boundary of the deep source/drain layer extending from an interface between the second gate spacer and the second epi-layer in a downward direction through the first epi-layer and the semiconductor substrate.