Patent ID: 7195968

Claim:
A method of fabricating a semiconductor device, comprising: forming gate insulation films in memory cell and peripheral circuit regions of a semiconductor substrate respectively, the gate insulation films having respective predetermined film thicknesses; forming gate electrodes in the memory cell and peripheral circuit regions respectively; forming an oxide film so that the gate electrodes are covered with the oxide film; forming a resist pattern so that an opening between select gates of adjacent select gate transistors is formed in the memory cell region; implanting threshold-adjusting ions under the select gate with the resist pattern serving as a mask and removing a portion of the oxide film; forming a nitride film and an interlayer insulation film after the resist pattern has been removed; forming a resist pattern used to form a contact hole between the select gates and a contact hole for a transistor to be provided in the peripheral circuit region, the transistor having a higher breakdown voltage than a memory cell transistor; and etching the interlayer insulation film, the nitride film and the gate insulation film individually with the resist pattern serving as a mask.