Patent ID: 7770042

Claim:
A microprocessor, comprising: core logic, configured to operate according to a core clock signal in order to execute program instructions; clock generation circuitry, controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two; a control circuit, coupled to the clock generation circuitry, and configured, in response to a request to operate the core logic at a destination frequency, to iteratively control the clock generation circuitry to generate the core clock signal having a new frequency on each of successive frequency iterations until the core clock signal frequency is the destination frequency, wherein the new core clock signal frequency on each of said frequency iterations is one of the N different possible frequencies monotonically closer to the destination frequency, wherein the number of said frequency iterations is between zero and N−1 depending upon the destination frequency specified and the core clock signal frequency when the request is received; and an output, configured to provide a signal for controlling an operating voltage of the microprocessor; wherein the control circuit is further configured, in response to said receiving the request, to iteratively generate the signal on the output to cause the operating voltage to have a new voltage on each of successive voltage iterations until the operating voltage is a destination voltage associated with the destination frequency.