Patent ID: 7023730

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a memory cell array including memory cells arranged in a matrix shape at the intersections of said plurality of word lines and said plurality of bit lines; a write circuit arranged per a bit line or a plurality of bit lines in order to perform batch write operation to a page including said plurality of memory cells, said write circuit comprising a plurality of latch circuits for storing data written to a plurality of pages, and bit line connection circuits for connecting said plurality of latch circuits and bit lines; a voltage generating circuit for generating a voltage necessary for write operation; and a control circuit for performing write operation to a plurality of pages by repeating continuous program operation which sequentially selects data written to a plurality of pages stored in said plurality of latch circuits while continuously operating said voltage generating circuit to cause the circuit to continuously generate a voltage necessary for program operation thereby continuously performing program operation on a plurality of pages, and continuous verify operation which sequentially selects data written to a plurality of pages stored in said plurality of latch circuits while continuously operating said voltage generating circuit to cause the circuit to continuously generate a voltage necessary for verify operation thereby continuously performing verify operation on a plurality of pages.