Patent ID: 8102043

Claim:
A method for manufacturing a stacked integrated circuit and package system comprising: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer and the first top IC is within the top substrate; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate so a flattened side of the electrical connector is coplanar with a side of the first top integrated circuit and a side of the third top integrated circuit; and mounting a bottom package to the top electrical connectors.