Patent ID: 8223568

Claim:
A read data path circuit of a semiconductor memory device, the circuit comprising: a first sense amplifier; and a precharging unit including a first conductive type precharging unit, a second conductive type precharging unit, a delay unit, a NAND gate, and an equalizing unit, the first conductive type precharging unit configured to precharge input/output lines that correspond with a second sense amplifier, the equalizing unit configured to equalize a voltage of the input/output lines of the circuit, the second conductive type precharging unit configured to precharge the input/output lines following an elapsed time after the first sense amplifier is activated and while a column selection unit is deactivated, the column selecting unit configured to operationally connect bit lines corresponding with the first sense amplifier to the input/output lines in response to a selection signal, the delay unit configured to delay an enable signal to the second sense amplifier, and the NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the equalizing unit, to produce a NAND response in order to activate the second conductive type precharging unit.