Patent ID: 8823566

Claim:
An analog-to-digital converter stage comprising: a comparator and logic circuit configured with first upper and lower unscaled voltage trip points and further configured, prior to an initial residue calculation cycle, to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit corresponding to the magnitude of the unscaled input voltage, and to generate a voltage scaling and gain control signal; a switched capacitor circuit coupled to the comparator and logic circuit, the switched capacitor circuit comprising a first voltage input, a voltage output, and a plurality of coupled capacitors and switches configured to sample the unscaled input voltage at the first voltage input to generate an unscaled input voltage sample and to receive the voltage scaling and gain control signal for selectively controlling a subset of the switches in order to scale the unscaled input voltage sample and generate an initial residue voltage having an initial residue magnitude at the voltage output during the initial residue calculation cycle; a second voltage input for receiving a reference voltage; a voltage supply node for receiving a common mode voltage; an operational amplifier having an inverting input coupled to the voltage supply node and a non-inverting input and having an output terminal coupled to the voltage output of the switched capacitor circuit; wherein the plurality of coupled capacitors comprises four capacitors; wherein the plurality of coupled switches comprises a first set of switches coupled to the first voltage input, the voltage supply node and the four capacitors, wherein the first set of switches is configured to close under the control of a sampling control clock signal to charge at least a subset of the four capacitors in order to sample the unscaled input voltage at the first voltage input; wherein a remainder of the plurality of coupled switches comprises a second set of switches that comprises the subset of the switches, wherein the second set of switches is coupled to the second voltage input, the voltage supply node, the four capacitors, and the non-inverting input and the output of the operational amplifier.