Patent ID: 8106395

Claim:
A semiconductor device comprising: a wafer having a plurality of chips, each chip having a plurality of test areas in plan view, the test areas of the chips being of same size and shape, and the test areas to be individually probe tested using a common set of test probes, each test area having a plurality of probe contact pads including a first pad and a second pad which are electrically connected to a device formed on a main surface of a substrate, and the plurality of probe contact pads being laid out at same positions in each test area such that with repeating predetermined movement of the wafer, the respective pluralities of probe contact pads of different test areas can be successively brought into coincidence with a plurality of predetermined test probe contact positions for contact with the common set of test probes, wherein the device formed on the main surface of the substrate comprises: a first electrode provided on the substrate; a hollow portion provided on the first electrode; and a second electrode provided on the hollow portion, wherein the first electrode is electrically connected to the first pad of the plurality of probe contact pads of a corresponding test area, and wherein the second electrode is electrically connected to the second pad of the plurality of probe contact pads of said corresponding test area.