Patent ID: 8336009

Claim:
A method for verifying functionality of an integrated circuit system-on-chip (SoC), the method comprising: modeling a system block in a first model at a first level and in a second model at a second level lower than the first level; generating a first stimulus transaction at a first testbench at the first level; transmitting the first stimulus transaction from the first testbench to a second testbench at the second level; transforming the first stimulus transaction into a first response transaction, using the first model, at the first level; transforming the first stimulus transaction received at the second testbench into a second response transaction, using the second model, at the second level; storing the first and second response transactions in first and second response queues, respectively and verifying functionality of the SoC at the first and second levels based on a comparison at the first testbench between head entries of the first and second response queues.