Patent ID: 8405216

Claim:
A static random access memory (SRAM) cell, comprising: a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply voltage and a complementary supply voltage, respectively; a second inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply voltage and the complementary supply voltage, respectively, wherein a drain of the first pull-down transistor is electrically connected to gates of the second pull-up and pull-down transistors, and a drain of the second pull-down transistor is electrically connected to gates of the first pull-up and pull-down transistors, wherein a source of the first pull-down transistor is electrically connected to the complementary voltage by an interconnect structure including a first metal interconnect layer, a first via contact, a second via contact, and a third via contact, wherein the first metal interconnect layer is electrically connected with the source of the first pull-down transistor, the first via contact has a top surface and a bottom surface, the bottom surface of the first via contact being disposed at least partially on the first metal interconnect layer, the second via contact has a top surface and a bottom surface, the bottom surface of the second via contact being disposed at least partially on the top surface of the first via contact, and the third via contact having a top surface and a bottom surface, the bottom surface of the third via contact being disposed at least partially on the top surface of the second via contact; and wherein a cross-sectional area of the first via contact is less than a cross-sectional area of the second via contact.