Patent ID: 8232172

Claim:
A method of fabricating a transistor device, comprising: forming a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; performing an implantation to form etch stop regions a spaced distance below an implanted top surface of the semiconductor substrate such that a top surface of etch stop regions is disposed below a top surface of the semiconductor substrate; following forming the etch stop regions, selectively etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate that undercut the dielectric spacers and define a channel region between the recessed regions comprising undercut areas, wherein a bottom of the recessed regions stops on the etch stop regions; and epitaxially growing source and drain regions in the recessed regions of the semiconductor substrate such that the source and drain regions extend underneath the dielectric spacers into the undercut areas of the channel region.