Patent ID: 8811105

Claim:
An information processing system comprising: a first device including a memory cell array that holds storage data, an input buffer circuit to which an external clock signal having a predetermined frequency is supplied, and a DLL circuit that generates an internal clock signal that is phase-controlled based on the external clock signal, the first device having a self-refresh mode in which a refresh operation of the storage data is periodically performed asynchronously with the external clock signal; and a second device issuing the external clock signal, a self-refresh command that causes the first device to enter the self-refresh mode, and a self-refresh exit command that causes the first device to exit the self-refresh mode, wherein the second device continuously issues the external clock signal to the first device while the first device is in the self-refresh mode, and the first device intermittently activates the input buffer circuit and the DLL circuit in conjunction with each other while the first device is in the self-refresh mode.