Patent ID: 7284182

Claim:
A method of performing single bit error correction on M-bit words that have been scrambled using a self synchronizing scrambler, the method comprising the steps of: a) calculating an N-bit CRC every K words of a block of J words using a generator polynomial, where J is a non-zero integer multiple of K; b) forming an M-bit word from the calculated N-bit CRCs, where M is a non-zero integer multiple of N, and appending the said M-bit word to the block of J words to form a block of J+1 words for transmission; c) calculating, responsive to receiving a block of J+1 words, another N-bit CRC every K words of the first J words of the received block of J+1 words and using, from the appended word, the N-bit CRC corresponding to the K words in each calculation; and d) correcting, responsive to one of the another N-bit CRCs, computed at a receiver, having a non-zero value, an errored bit in the received block of J+1 words, the errored bit being indicated by an entry in a table indexed according to the non-zero value.