Patent ID: 7300842

Claim:
A method of fabricating a mask ROM, comprising the steps of: forming a gate insulating layer on a semiconductor substrate divided into a device isolation area and an active area; depositing a first electrode layer, a first dielectric layer and a second dielectric layer on the gate insulating layer; forming a first electrode layer pattern, a first dielectric layer pattern and a second dielectric layer pattern, each having the same width, on a predetermined area of the gate insulating by selectively removing the first electrode layer, the first dielectric layer and the second dielectric layer; forming an impurity region by implanting impurities into an area excluding the first electrode layer pattern; forming a second electrode layer pattern on the impurity region; forming an oxide layer by oxidizing a surface of the second electrode layer pattern; removing the first and second dielectric layer patterns; forming a third electrode layer over the semiconductor substrate including the first and second electrode layer patterns; planarizing the third electrode layer; forming a word line by selectively removing the first and third electrode layers; and filling a gap between the word lines with an oxide layer.