Patent ID: 6977981

Claim:
A variable-mode digital logic circuit for accepting a parallel data word as input, the parallel data word being a plurality of data bits wide, and serializing the parallel data word, such that the parallel data word is transmitted as output from the digital logic circuit over as few as a single one-bit wide trace, wherein the digital logic circuit comprises: a plurality of parallel data traces for receiving the parallel data word, each trace dedicated to the transmission of a single bit of the parallel date word; a plurality of select-capable multiplexor circuits for sequentially activating certain ones of the parallel data traces and for multiplexing the each bit of the parallel data word, such that the parallel data word is serially output therefrom; a ring counter for controlling a frequency of specific operations performed within the digital logic circuit; and at least one additional multiplexor circuit array for receiving the data output from the plurality of select-capable multiplexor circuits, and for further serializing the received data for output on the single one-bit wide trace; and wherein the digital logic circuit is adapted to operate according to one of a plurality of variable modes wherein, and wherein during processing according to a selected mode, more than one multiplexing phase is employed at a lower frequency than a frequency assigned to a subsequent multiplexing phase, the lower frequency and the assigned frequency are proportional to each other and to a final output frequency.