Patent ID: 7009427

Claim:
A low power logic gate comprising: a precharge circuit having an input for receiving a clock signal that varies from a high voltage to a low voltage, an input for receiving a data signal, and a precharge node, the precharge circuit charging the precharge node to a voltage substantially close to the high voltage of the clock signal when the data signal is a logic low and the high voltage is present on the clock signal; a discharge circuit having an input for receiving the clock signal, an input for receiving the data signal, and a discharge node, the discharge circuit discharging the discharge node to a voltage substantially close to the low voltage of the clock signal when the data signal is a logic high and the low voltage is present on the clock signal; and an output circuit connected to the precharge node and the discharge node, and having an input for receiving the data signal and an output node for carrying a value indicative of a logic function performed on the data signal, the output value being derived from either the voltage on the precharge node or the discharge node, depending on whether the data signal is a logic high or a logic low.