Patent ID: 7115949

Claim:
A semiconductor device formed in a first semiconductor layer having a top surface and a bottom surface, wherein the semiconductor device comprises: a first semiconductor layer having a memory portion and a logic portion, wherein the logic portion is devoid of a fifth doped region opposite in conductivity to the fourth doped region and closer than the fourth conductive region to the bottom surface; a first dielectric layer over the memory portion of the first semiconductor layer; a conductive layer over the first dielectric layer; first conductive regions disposed laterally from the first dielectric layer and the conductive layer and over the first semiconductor layer; second conductive regions in the memory portion of the first semiconductor layer, wherein the second conductive regions are the same conductivity as the first conductive regions and are in contact with the top surface of the first semiconductor layer, wherein the second conductive regions are extension regions; third conductive regions in the memory portion of the first semiconductor layer, wherein the third conductive regions are opposite in conductivity to the second conductive regions and are closer than the second conductive regions to the bottom surface; a gate dielectric over the logic portion; a gate electrode over the gate dielectric; a third doped region laterally adjacent the gate dielectric and over the logic portion of the first semiconductor layer; and a fourth doped region in the logic portion of the first semiconductor layer, wherein the fourth doped region is the same conductivity as the third doped region, is within the first semiconductor layer, and at least a portion of the fourth doped region is directly under the third doped region.