Patent ID: 8493103

Claim:
An output driver circuit comprising: a first circuit that controls ON/OFF between a positive differential output node and a first power source; a second circuit that controls ON/OFF between a negative differential output node and a second power source lower in voltage than the first power source; a third circuit that controls ON/OFF between the negative differential output node and the first power source; a fourth circuit that controls ON/OFF between the positive differential output node and the second power source; a first pulse generation circuit that generates a first pulse-signal at a time when a differential input node has made a transition from a first logical level to a second logical level; a second pulse generation circuit that generates a second pulse-signal at a time when the differential input node has made a transition from the second logical level to the first logical level; a first current circuit that causes a charging current to flow to the positive differential output node; a second current circuit that causes a discharging current to flow to the negative differential output node; a third current circuit that causes a charging current to flow to the negative differential output node; a fourth current circuit that causes a discharging current to flow to the positive differential output node, wherein the first circuit and the second circuit each are controlled so as to be in the ON state and to have a first impedance at a time when the differential input node is at the second logical level while the first circuit and the second circuit each are controlled so as to be in the OFF state at a time when the differential input node is at the first logical level, wherein the third circuit and the fourth circuit each are controlled so as to be in the ON state and to have the first impedance at the time when the differential input node is at the first logical level while the third circuit and the fourth circuit each are controlled so as to be in the OFF state at the time when the differential input node is at the second logical level, wherein the first current circuit and the second current circuit each cause current to flow for a period of a pulse width of the first pulse-signal, wherein the third current circuit and the fourth current circuit each cause current to flow for a period of a pulse width of the second pulse-signal, and wherein the pulse width of the first pulse-signal and the pulse width of the second pulse-signal are each controlled so as to be variable according to setting.