Patent ID: 7315992

Claim:
A method of determining approximately whether a design of a module violates a desired criteria, said design being represented in a form of a data, said method comprising: examining said data to extract a topology of said design, wherein said topology comprises a plurality of transistors, a plurality of resistors, and a plurality of paths connecting said plurality of resistors and said plurality of transistors; generating a model of said module by replacing each of said plurality of transistors in said topology by a corresponding one of a plurality of current sources; computing a magnitude of each of said plurality of current sources by distributing an aggregate amount of current sunk by said module among said plurality of current sources, wherein said magnitude of each current source is treated proportionate to a corresponding width of the transistors by said computing; and analyzing said model to determine a corresponding current on each of said plurality of paths, wherein a determination is made as to whether said design violates said desired criteria based on said corresponding current.