Patent ID: 7834344

Claim:
A hosting structure of nanometric components comprising: a substrate having a top surface; a plurality of array levels on the top surface of said substrate, the array levels being arranged consecutively on each other and in parallel planes, each array level including a plurality of conductive spacers alternating with a plurality of insulating spacers, each conductive spacer and an adjoining insulating spacer forming a spacer pair, wherein the conductive spacer and the insulating spacer of each spacer pair contact one another along respective faces that are substantially perpendicular to the top surface of the substrate, and wherein, each two consecutive spacer pairs of the same array level define a gap therebetween, and wherein, conductive spacers of any two consecutive array levels are positioned on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to the top surface of said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component.