Patent ID: 7574547

Claim:
A microprocessor comprising: a shared resource; a plurality of requesting entities accessing the shared resource, wherein each of the plurality of requesting entities has a priority value and requests from the each of the plurality of requesting entities are assigned the priority value, the plurality of requesting entities being function units of the microprocessor; and a priority-encode arbiter with an adjustable ring counter disposed between the shared resource and the plurality of requesting entities to control overall requests of the plurality of requesting entities to the shared resource, wherein the adjustable ring counter includes arbitration logic circuitry coupled to a plurality of memory cells being coupled in series, the plurality of memory cells having a first memory cell and a last memory cell, the first memory cell being coupled to a multiplexer, the last memory cell being coupled to the shared resource, wherein the plurality of memory cells are flip/flops driven by a clock, the initial value of the plurality of memory cells being a first value, each of the plurality of the memory cells takes turns to have a second value while others have the first value as clock cycles of the clock progress, there being a plurality of return paths, each of the plurality of return paths being coupled to a unique memory cell of the plurality of memory cells at one end and the multiplexer at the other end.