Patent ID: 6963979

Claim:
A cryptographic accelerator comprising: a host interface for interfacing with a host system to receive requests for cryptographic operations and to route responses to the host system; a plurality of logical units including an exponentiation sub-system; a CPU connected between the host interface and the logical units for managing operation of the logical units; said exponentiation sub-system including, a plurality of exponentiation groups, each group having a plurality of modular exponentiators interconnected in series that define a size of each group, each exponentiator being capable of performing a multiply operation; an input buffer for the exponentiation groups; and a scheduler for delivering control instructions to the input buffer to dynamically configure the exponentiators so that they are dynamically and serially chained together within the groups, each chain having a number of exponentiators up to the size of the exponentiation groups to form at least one chain in each group.