Patent ID: 8609997

Claim:
A multilayer wiring substrate, comprising: a center wiring layer arranged in a center of the substrate in a thickness direction; wiring layers stacked on a first side of the center wiring layer via insulating layers and forming a semiconductor element mounting surface of the multilayer wiring substrate, the semiconductor element mounting surface configured to have an associated semiconductor element mounted thereon, and wiring layers stacked on a second side of the center wiring layer via insulating layers and forming a surface of the multilayer wiring substrate opposite to the semiconductor element mounting surface; and a plurality of vias, the plurality of vias electrically connecting adjacent wiring layers including the center wiring layer to each other, said vias each having a trapezoidal sectional shape with a narrow end nearer the center wiring layer than a wide end, wherein the wiring layers on the first side of the center wiring layer and the wiring layers on the second side of the center wiring layer are provided in a same layer number, the insulating layers on the first side of the center wiring layer and the insulating layers on the second side of the center wiring layer are provided in a same layer number, the insulating layers located in symmetrical positions with respect to the center wiring layer are formed on the first side and the second side of the center wiring layer such that stresses caused by the insulating layers formed on the first side and the second side of the center wiring layer are made uneven, the multilayer wiring substrate is planarized in which stresses caused by an uneven distribution of conductors in the wiring layers formed on the first side and the second side of the center wiring layer are cancelled by the insulating layers, and a number of vias connecting the wiring layers stacked on the first side of the center wiring layer and provided between the center wiring layer and the semiconductor element mounting surface is greater than a number of vias connecting the wiring layers stacked on the second side of the center wiring layer and provided between the center wiring layer and the surface of the multilayer wiring substrate opposite to the semiconductor element mounting surface, wherein the center wiring layer is formed thicker than wiring patterns formed in the wiring layers stacked on the first side and the second side of the center wiring layer.