Patent ID: 7439779

Claim:
A driver circuit for driving a load connected between an output of a first channel driver and an output of a second channel driver, the first and second channel drivers each comprising: a charging/discharging circuit comprising a switch transistor for charging and discharging each gate of upper and lower output transistors in response to a command from an input pulse, and a circuit for determining a charging/discharging speed for each gate; and a detector circuit for detecting a state of the channel driver on an opposite side, wherein a change is made to a dead time period and the speed of charging/discharging the gates of the upper and lower output transistors, according to the state of the channel driver on the opposite side, wherein the detector circuit detects a level of the input pulse on the opposite side, when the input pulse on the opposite side is set at “H”, dead time is provided only at a rising edge of an input, the gate of the lower output transistor is discharged at a lower speed, and the gate of the upper output transistor is discharged at a higher speed, and when the input pulse on the opposite side is set at “L”, the dead time is provided only at a falling edge of the input, the gate of the upper output transistor is discharged at a lower speed, and the gate of the lower output transistor is discharged at a higher speed.