Patent ID: 7664217

Claim:
A digital PLL circuit for generating an internal clock that is phase synchronized with a reference clock of a digital synchronization network, comprising: a slave oscillator to generate a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit to detect the difference in phase between the output of said slave oscillator and the inputted reference clock, and to output a digital signal of the prescribed number of bits corresponding to said detected phase difference; a memory to store the history of control values for said slave oscillator; an average value circuit to find an average value of the history of the control values stored in said memory; a rounding circuit to round the output of said average value circuit to upper N bits; and a circuit to find an oscillation characteristic of said slave oscillator during the holdover from the output of said average value circuit, and to generate a correction value providing a characteristic inverted with respect to said oscillation characteristics; and an adder circuit to add the correction value with the rounded output from the rounding circuit to be taken as a control value for said slave oscillator.