Patent ID: 7484141

Claim:
A semiconductor device, comprising: a CPU core circuit; a bus connected to said CPU core circuit; and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from said CPU core circuit through said bus; a first signal line for supplying an address signal from said memory BIST circuit to a memory; a second signal line for supplying a data signal from said memory BIST circuit to the memory; a third signal line for supplying read data from the memory to said memory BIST circuit; and one or more pipeline registers provided along a path of at least one of said first through third signal lines, wherein said first through third signal lines are separate from said bus, and wherein said memory BIST circuit includes: a register that is accessible by said CPU core circuit through said bus; and a control circuit configured to control the memory test according to what is stored in said register; and a signal analyzing unit configured to compare data read from the memory with an expected value to store a result of the comparison in said register, wherein said signal analyzing circuit includes; a comparison circuit configured to compare the read data with the expected value; and a timing adjusting circuit configured to change timing at which said expected value is supplied to said comparison circuit, the changing of the timing being made in response to a number of stages of said one or more pipeline registers provided along the path between the memory and said memory BIST circuit.