Patent ID: 7461207

Claim:
An apparatus, comprising: a first level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the first level cache memory being operable to store an address tag and data; a next lower level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the next lower level cache memory being operable to store an address tag, status flags, and data; and an additional memory associated with the next lower level cache memory and including a plurality of memory lines, wherein the number of memory lines corresponds with the number of cache lines contained in a given way set of the first level cache memory; wherein each cache line of the first level cache memory has an index associated therewith, each memory line of the additional memory includes respective L-flags for multiple cache lines of each way set of the next lower level cache memory, all L-flags associated with a given one of the indices plus any index offset from the first level cache memory are contained in a single memory line of the additional memory, and the next lower level cache memory does not include an L-flag contained within each cache line thereof; wherein each L-flag indicates whether any of the cache lines of the first level cache memory contains a copy of the data stored in a given cache line of the next lower level cache memory and respective L-flags are set to indicate whether or not corresponding cache lines of the first level cache memory have been refilled with data stored in the cache lines of the next lower level cache memory; and wherein data overwriting into the given cache line is prohibited when the L-flag of the given cache line indicates that a corresponding one the of the cache lines of the first level cache memory contains a copy of the data stored in the given cache line of the next lower level cache memory.