Patent ID: 7579975

Claim:
A stage of a pipeline analog to digital converter (ADC) processing an input signal in differential form, wherein the input signal is received across a pair of differential input terminals, the stage comprising: a sub-ADC portion to generate a sub-code of P bits representing a strength of the input signal, wherein P is an integer; a residue block to generate a residue signal by subtracting the input signal from a signal level representing the digital value, the residue block including: a differential amplifier having first input terminal and a second input terminal, the differential amplifier providing the residue signal on a first output terminal and a second output terminal; a first feedback capacitor coupled between the first output terminal and the first input terminal of the differential amplifier; a first bank of (2 (P−1) ) capacitors, a first terminal of each capacitor in the first bank of capacitors being coupled to the first input terminal of the differential amplifier; a second bank of (2 (P−1) ) capacitors, a first terminal of each capacitor in the second bank of capacitors being coupled to the second input terminal of the differential amplifier; a plurality of sampling switches, wherein each sampling switch, in a first phase connects the input signal to at least one of the capacitors from one of the first bank of capacitors and the second bank of capacitors; a plurality of positive reference switches, wherein each positive reference switch is adapted to connect at least one of the capacitors from one of the first bank and the second bank to a positive reference voltage during a second phase; and a plurality of negative reference switches, wherein each negative reference switch is adapted to connect at least one of the capacitors from one of the first and second back to a negative reference voltage during a second phase, wherein a common mode reference voltage is the average of the positive and negative reference voltages, and wherein the common mode reference voltage is generally maintained through actuation of the positive and negative reference switches; and a switch decoder that is coupled to the sub-ADC portion, wherein the switch decoder includes: a NAND gate that receives a hold signal, that receives a control signal from the sub-ADC portion that is associated with a subset of capacitors from the first and second sets of capacitors, and that outputs a signal that actuates and deactuates the negative reference switches associated with the subset, wherein the hold signal indicates the first and second phases; and a NOR gate that receives an inverse of the hold signal, that is that receives the control signal, and that outputs a signal that actuates the positive reference switches associated with the subset.