Patent ID: 8769248

Claim:
A programmable processor comprising: an instruction path and a data path; a register file having at least a source register and a result register coupled to the data path; and an execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instniction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein: in response to decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being a factor of two different than the source precision, the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register.