Patent ID: 7281070

Claim:
A multiple-master Inter Integrated Circuit (“I 2 C”) bus system, comprising: one or more slave devices electrically connected to an I 2 C bus; a first master device electrically connected to the I 2 C bus and residing within a first power boundary; and a second master device electrically connected to the I 2 C bus and residing within a second power boundary, said second master device including a processing device adapted to control the first power boundary of the first master device, detect when the first master device has powered-on and to discontinue the second master device's use of the I 2 C bus, and further includes a memory device adapted for holding a bus power control algorithm, the bus power control algorithm directing the first master device to power on, wherein: the first power boundary is initially suppressed by the processing device, the second master device polls configuration data from any of the slave devices, and subsequent to polling configuration data, the second master device activates the first power boundary to power on the first master device.