Patent ID: 7117281

Claim:
A data transfer control circuit for carrying out data transfer by using a plurality of bus masters, comprising: a data bus connected to a peripheral apparatus, said data bus having a plurality of unit data buses, each of which transfers data concurrently; a plurality of bus masters connected to each of the unit data buses and configured to send a bus request signal requesting to acquire a use of each of said unit data buses, and to transfer data on said unit data buses requested when a request by means of said bus request signal is granted; and one bus controller connected to all of the bus masters and configured to split-control said unit data buses for said plurality of bus masters by giving a grant signal to the bus masters, which grants the use of each of said unit data buses in accordance with said bus request signal, wherein the bus request signal is sent to said bus controller prior to data transfer and has a field comprising a plurality of bits for specifying necessary bit width, each of said plurality of bits identifying a respective one of said unit data buses, and said bus controller grants the use of each of said unit data buses specified by the bits of said bus request signal.