Patent ID: 7582535

Claim:
A method of fabricating a metal oxide semiconductor (MOS) transistor, comprising: forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region; forming an insulated gate pattern which crosses over the active region; forming a spacer on sidewalls of the gate pattern; forming source and drain regions in the semiconductor substrate and annealing the gate pattern and source and drain regions; forming a poly-crystalline semiconductor layer on the annealed gate pattern and a single-crystalline semiconductor layer on the annealed source and drain regions using a selective epitaxial growth process; selectively etching the semiconductor layers to form a gate-reduced pattern and elevated source and drain regions on the source and drain regions, wherein the selective etching is carried out using HCl and H 2 gases as reaction gases; and applying a silicidation process where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.