Patent ID: 6861698

Claim:
An array of electrically programmable and erasable memory devices comprising: a substrate of semiconductor material of a first conductivity type; spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; each of the active regions including a plurality of memory cells, each of the memory cells including: first and second spaced apart regions in the substrate having a second conductivity type, with a channel region defined in the substrate therebetween, an electrically conductive floating gate disposed over and insulated from a portion of the channel region, and an electrically conductive control gate disposed over and insulated from a portion of the channel region; a plurality of source line blocks of metal material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks extends over and is electrically connected to one of the first regions in each of the active regions; a first plurality of parallel spaced apart lines of conductive material formed over the substrate and electrically connected to the control gates of the memory cells; a plurality of strap regions each formed on the substrate and disposed in an interlaced fashion between selected ones of the active regions, each of the strap regions including: first strap cells through which the first plurality of conductive material lines traverse, wherein the first plurality of conductive material lines completely traverse across the strap region, a first plurality of conductive metal contacts each of which is connected to one of the first plurality of conductive material lines in one of the first strap cells, second strap cells in which the source line blocks terminate without completely traversing across the strap region, and a second plurality of conductive metal contacts each of which is connected to one of the source line blocks in one of the second strap cells.