Patent ID: 7733150

Claim:
A clock distribution circuit, comprising: a clock source that operates to produce a clock signal; a phase adjustment circuit that operates to receive the clock signal and produce a delayed, advanced, or unchanged output clock signal as a function of a control signal, and which operates to vary the phase difference between the clock signal and the output clock in a way that adheres to the following equation: φ ⁡ ( t ) = - β T 0 ⁢ ∫ ( v ⁡ ( t ) - v 0 ) ⁢ ⁢ ⅆ t where φ(t) is the phase difference in radians as a function of time variant changes in a magnitude of the power supply voltage v(t), T 0 is a cycle time of the clock signal and β is a constrained constant; and a clock distribution tree that operates to distribute the output clock signal to a plurality of areas of a digital circuit, wherein the phase adjustment circuit is that operates to vary an amount of delay or advancement between the clock signal and the output clock signal (phase difference) as a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.