Patent ID: 7548483

Claim:
A memory device, comprising: an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device; a plurality of internal address buses; an address coupling circuit operable to couple memory address signals corresponding to the memory addresses received by the external port to a selected one of the internal address buses; a plurality of banks of memory cells coupled to a respective one of the internal address buses; a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from each of the internal address buses to the respective bank; a data coupling circuit operable to couple the write data signals from the external port to the banks and to couple the read data signals from the banks to the external data port; and a control circuit coupled to the address coupling circuit, the control circuit being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select the internal address bus to which the address signals are coupled, the control circuit comprising: a flip-flop having a clock input coupled to receive a signal generated responsive to each of the memory command signals being applied to the external port; and a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal address buses each time the flip-flop toggles.