Patent ID: 8618678

Claim:
A chip package structure, comprising: a chip, comprising a plurality of pads, wherein the pads includes a plurality of first pads and a plurality of second pads alternatively disposed on the chip, the first pads have a plurality of first bonding regions respectively, and the second pads have a plurality of second bonding regions respectively; a plurality of first bumps, respectively disposed on the first bonding regions, wherein the shape of each first bump is triangular pillar or trapezoidal pillar, and a surface area of connection between each first bump and each first pad is less than each first bonding region; a plurality of second bumps, respectively disposed on the second bonding regions, wherein the shape of each second bump is triangular pillar or trapezoidal pillar, and a width of each first bump is decreased along a first direction and a width of each second bump is decreased along a second direction opposite to the first direction and a surface area of connection between each second bump and each second pad is less than each second bonding region; a plurality of first leads, respectively disposed on and electrically connected to the first bumps, wherein one terminal of each first lead connected to each first bump is located above and within each first bump; and a plurality of second leads, respectively disposed on and electrically connected to the second bumps, wherein one terminal of each second lead connected to each second bump is located above and extends beyond each second bump, a width of each first lead is larger than a width of each second lead.