Patent ID: 7662687

Claim:
A method for fabricating a semiconductor memory, comprising: providing of a substrate having a first polarity in a memory cell array region; forming of shallow trench isolations in parallel alignment at a distance of one to another in the substrate; forming of a sacrificial layered structure comprising a sacrificial mask layer above the substrate; etching of word line trenches in the sacrificial mask layer and substrate in orthogonal alignment as to the shallow trench isolations; growing of a tunneling dielectric oxide layer in the word line trenches and depositing of a charge trapping storage layer on the tunneling dielectric oxide layer; depositing of a gate dielectric on top of the storage layer; depositing of at least one gate conductor material in the word line trenches and back-etch of the gate conductor materials to form recessed portions; depositing of an electrically insulating material on the gate conductor material; forming of local interconnect isolations; etching of local interconnect openings; forming of source/drain regions; filling of local interconnect openings with electrically conductive material.