Patent ID: 7745864

Claim:
A semiconductor device comprising: a semiconductor substrate divided into a cell array region, a core region, and a peripheral region; bit lines formed over the substrate in the respective regions; an interlayer dielectric formed so as to cover the bit lines in the respective regions, the interlayer dielectric including grooves formed around the bit lines in the core region and the peripheral region; storage node contact plugs formed in the cell array region; blocking patterns formed around the bit lines in the core region and the peripheral region, the blocking patterns comprising a layer filled in the grooves of the interlayer dielectric for blocking formation of the metal contact plugs below the blocking patterns; capacitors formed in the cell array region to come into contact with the storage node contact plugs; and the metal contact plugs formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region.