Patent ID: 7824993

Claim:
A method for fabricating a field-effect transistor with local source/drain insulation, having the following steps: a) forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; b) forming source and drain depressions at the gate stack in the semiconductor substrate; c) forming a depression insulation layer at least in a bottom region of the source and drain depressions; d) filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions wherein, in step b), first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate; and wherein, in step a), an STI method is carried out for forming shallow trench isolations; an implantation is carried out for forming at least one of well or channel doping region in the semiconductor substrate; a thermal oxidation is carried out for forming the gate dielectric; a deposition of semiconductor material is carried out for forming the gate layer; a TEOS deposition is carried out for forming a hard mask layer; a lithographic method is carried out for patterning at least the gate layer using the hard mask layer, and a further thermal oxidation is carried out for forming a gate sidewall insulation layer at sidewalls of the gate layer, wherein the spacers are formed after the TEOS deposition, the lithographic method for patterning at least the gate layer and the further thermal oxidation for forming a gate sidewall insulation layer at sidewalls of the gate layer.