Patent ID: 8341300

Claim:
A memory system comprising: a plurality of non-volatile memory devices (NVMDs) coupled to a set of a plurality of memory channels to share busses, wherein each NVMD independently executes one read, write, or erase operation at a time; a first memory controller coupled to the plurality of memory channels in communication between the plurality of NVMDs, the first memory controller including a first channel scheduler to schedule control and data transfers associated with the read, write, and erase operations on a memory channel; a high priority queue coupled to the first channel scheduler to store one or more operations waiting for execution with one or more of the plurality of NVMDs; and a low priority queue coupled to the first channel scheduler to store one or more operations waiting for execution with one or more of the plurality of NVMDs; wherein the first channel scheduler to prioritize operations waiting in the high priority queue over operations waiting in the low priority queue, and wherein the first channel scheduler to further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.