Patent ID: 7570076

Claim:
An integrated circuit including a capacitor array, comprising: a first output; a second output; a plurality of capacitors coupled in parallel current paths between the first and second outputs; a plurality of transistors respectively coupled in series with the capacitors in the current paths, each transistor serving to connect or disconnect a respective capacitor into or out of its current path according to an on or off state of the transistor; a control circuit including a programmable shift register with a plurality of stages; each stage comprising: a stage output coupled to provide a control signal to a control terminal of a respective one of the transistors to control the on or off state of that transistor to connect or disconnect its corresponding capacitor responsive to a state of the control signal; a programmable fuse element; latching circuitry responsive to a setting of the fuse element for latching a normal state of the control signal to connect or disconnect the corresponding capacitor in a normal mode of operation; and shifting circuitry for shifting a test state of the control signal through the stage, with the shifting of the test state through the respective stages serving to sequentially connect individual ones of the capacitors in a test mode of operation; wherein each capacitor has a capacitance, and a total capacitance across the first and second outputs is determined by a sum of the capacitances that are connected into their respective current paths.