Patent ID: 7715500

Claim:
An FSK (Frequency Shift Keying) signal detector comprising: a binarizing circuit for receiving an FSK signal for binarizing an amplitude of the FSK signal; a first correlator for receiving the FSK signal, binarized by said binarizing circuit, for finding a correlation of the FSK signal with a first correlation signal string which is used to acquire a correlation value by one of two frequency components generated on FSK modulation; a second correlator for receiving the FSK signal, binarized by said binarizing circuit, for finding a correlation of the FSK signal with a second correlation signal string which is used to acquire a correlation value by another of the two frequency components generated on FSK modulation; and an operating circuit for performing calculation on an output of said first and second correlators to detect the FSK signal to output the FSK signal detected; wherein said first correlator includes: a first shift register, having a plurality of stages, for sequentially shifting the FSK signal; a first plurality of logical operating circuits connected to respective shift register units of said first shift register for taking exclusive OR of the FSK signal with the first correlation signal string; and a first addition circuit for adding results of exclusive OR operation generated by said first plurality of logical operating circuits; said second correlator including: a second shift register, having a plurality of stages, for sequentially shifting the FSK signal; a second plurality of logical operating circuits connected to said second shift register for taking exclusive OR of the FSK signal with the second correlation signal string; and a second addition circuit for adding results of exclusive OR operations generated by said second plurality of logical operating circuits; and wherein each of said operating circuits includes: a first adder for adding a value of −n to an output of said first correlator, where n is a natural number; a first absolute value converter for finding an absolute value of an output of said first adder; a first low-pass filter for averaging an output of said first absolute value converter; a second adder for adding the value of −n to an output of said second correlator; a second absolute value converter for finding an absolute value of an output of said second adder; a second low-pass filter for averaging an output of said second absolute value converter; and a subtractor for calculating a difference between outputs of said first and second low-pass filters.