Patent ID: 7237088

Claim:
An array processor comprising: a physical M×N array organization of at least two processing elements (PEs) and a sequence processor (SP), each of the at least two PEs having a set of PE register files and the SP having a set of SP register files, the SP and at least one PE combined to form a combined processor, the combined processor having substantially similar access to the set of SP register files and to the set of PE register files of the at least one PE that was combined to form the combined processor; and a processor state register storing a context switch bit (CSB), the CSB having a first state and a second state, the SP and each PE operating to detect the state of the CSB, the combined processor upon detection of the first state of the CSB operating in a first operating context stored in the set SP register files, the first operating context adapted for processing a first software task where the first software task is written for an M×N operating configuration which matches the physical M×N array organization including the at least one PE of the combined processor, where M represents the number of rows of PEs and N represents the number of columns of PEs, the combined processor upon detection of the second state of the CSB operating in a second operating context stored in the set of PE register files of the combined processor, the second operating context adapted for a second software task where the second software task is written for an O×P operating configuration of the physical M×N array organization where O is the number of rows of PEs and P is the number of columns of PEs, the O×P operating configuration not matching the physical M×N array organization as O+P<M+N.