Patent ID: 6974986

Claim:
A semiconductor memory device comprising: a substrate including a cell area and a peripheral circuit area; first and second transistors each including a gate electrode, a source region, and a drain region, formed on the substrate; a first interlevel dielectric layer formed over an entire surface of the substrate including the first and second transistors, and having a bit line contact hole and a lower electrode contact hole formed in the cell area and a metal wiring contact hole formed in the peripheral circuit area; a bit line connector formed within the bit line contact hole of the first interlevel dielectric layer and directly connected to the drain region of the first transistor; a bit line formed on the first interlevel dielectric layer and electrically connected to the bit line connector; a bit line capping pattern covering the bit line; a second interlevel dielectric layer covering the bit line capping pattern; a capacitor lower electrode connector, formed within the lower electrode contact hole of the first interlevel dielectric layer, that extends to a same level as the bit line capping pattern; a capacitor formed on the capacitor lower electrode connector and on the second interlevel dielectric layer, the capacitor including a lower electrode, a capacitor dielectric layer and an upper electrode; and a lower metal wiring contact plug formed within the metal wiring contact hole and connected to the drain region or the gate electrode of the second transistor.