Patent ID: 8539491

Claim:
A computer system, comprising: an integrated circuit having first and second processing cores fabricated therein, wherein the integrated circuit is configured to process a plurality of threads, wherein a subset of the plurality of threads is assigned to the first processing core based on a pre-determined criterion dependent on a sum of a plurality of predicted delay time periods each corresponding to a single thread in the subset, wherein each of the plurality of predicted delay time periods is determined by a model simulating execution of the single thread on a simulated single-threaded processor that executes the single thread to completion without concurrent execution of another thread, and wherein each of the plurality of predicted delay time periods comprises an amount of time of the execution of the single thread during which functional units of the simulated single-threaded processor are unused awaiting completion of a memory access event initiated by the single thread; and memory comprising instructions to: assign the plurality of threads to the first and second processing cores of the integrated circuit; determine a first average predicted delay time based on the sum by the model simulating execution of all threads assigned to the first processing core on the simulated single-threaded processor; and determine a second average predicted delay time by the model simulating execution of all threads assigned to the second processing core on the simulated single-threaded processor, wherein a first difference is minimized between the first average delay time and the second average delay time.