Patent ID: 8513789

Claim:
A method of making a stacked microelectronic package, the method comprising the steps of: forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements with a second subassembly including a plurality of microelectronic elements, the microelectronic elements of each subassembly having faces and being attached to one another at a plurality of saw lanes such that a first saw lane of the saw lanes extends in a first direction parallel to the faces of the microelectronic elements and separates adjacent first and second microelectronic elements of each subassembly in a second direction parallel to the faces of the first and second microelectronic elements and transverse to the first direction, wherein each of the first and second adjacent microelectronic elements of the first and second subassemblies has a plurality of electrically conductive traces extending towards the first saw lane; forming notches in the first and second subassemblies of the microelectronic assembly, the notches including a first notch having a side wall extending in the first direction along the first saw lane so as to expose the plurality of the traces of each first microelectronic element and the plurality of the traces of each second microelectronic element of each of the first and second subassemblies; and forming a lead at the side wall of the first notch, the lead being in electrical communication with at least one trace of the first and second microelectronic elements of the first and second subassemblies; and entirely dicing through the saw lanes of the first and second subassemblies to form individual stacked packages.