Patent ID: 8569142

Claim:
A method of manufacturing a thin film integrated circuit, comprising: obtaining a ceramic substrate; depositing a glass dielectric buffer layer over the substrate; smoothing the buffer layer's surface to a surface roughness (Ra) of less than or equal to 0.08 microns and substantially free of surface micropores; forming multiple layers of a thin film multi-level capacitor over the buffer layer surface, the forming of the multiple capacitor layers including providing high permittivity dielectric layers interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween, and wherein a bottom electrode of a bottom capacitor of the multiple capacitors is formed directly on the buffer layer; annealing each capacitor layer before forming the successive capacitor layer; forming a high density interconnect layer between the ceramic substrate and the buffer layer, wherein the deposited buffer layer provides electrical isolation between the high density interconnect layer and the thin film multi-level capacitor; and forming a contact via through the buffer layer and the high density interconnect layer to provide electrical contact for the thin film multi-level capacitor.