Patent ID: 8097943

Claim:
A wafer level chip scale package (WLCSP) semiconductor device, comprising: a semiconductor die having an active surface; a die extension region formed around a periphery of the semiconductor die; a wafer level conductive plane formed over a center area of the active surface of the semiconductor die to provide a first power supply potential to a first contact pad on the active surface and electrically connected to a first conductive through hole via (THV) in the die extension region; and a conductive ring formed partially around a perimeter of the wafer level conductive plane to provide a second power supply potential to a second contact pad on the active surface of the semiconductor die and electrically connected to a second conductive THV in the die extension region, wherein the first and second conductive THVs in the die extension region provide a direct path for the wafer level conductive plane and conductive ring through the WLCSP semiconductor device.