Patent ID: 8455348

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: forming a diffusion preventing film over a semiconductor substrate so as to cover a first low dielectric constant film with a copper wiring formed therein; laminating a second low dielectric constant film, a third low dielectric constant film, and a film for serving as a mask layer over the diffusion preventing film in that order; forming the mask layer by etching the film for serving as the mask layer using a first resist mask formed over the film for serving as the mask layer so as to expose the third low dielectric constant film, and by forming a wiring trench pattern whose bottom is comprised of a surface of the third low dielectric constant film in the film for serving as the mask layer; removing the first resist mask by asking; forming a wiring trench in the second low dielectric constant film and the third low dielectric constant film using the wiring trench pattern of the mask layer such that a bottom of the wiring trench is comprised of the second low dielectric constant film; charging a copper metal into the wiring trench and a via hole formed to expose a part of the copper wiring in a position where the copper metal is superimposed over the wiring trench as viewed in a planar manner; and removing at least a layer from a top surface of the copper metal to the third low dielectric constant film by a CMP method, wherein each of the first, second, and third low dielectric constant films is an insulating film having a dielectric constant lower than that of a FSG, and wherein the second low dielectric constant film is a film having the dielectric constant lower than that of the third low dielectric constant film.