Patent ID: 7178013

Claim:
A method of operating a processor to repeatedly execute an instruction in a pre-emptive multi-tasking environment, comprising: determining at run time how many times a single instruction is to be repeated; loading at run time an existing general purpose register with a count value indicative of the number of times a single instruction is to be executed; fetching and executing a REPEAT instruction, the REPEAT instruction indicating the single instruction to be repeatedly re-executed; fetching the single instruction; repeatedly executing the single instruction for a consecutive number of times as indicated by the count value without refetching the single instruction and without adding a NOP (no operation) instruction; adjusting the count value in the register each time the single instruction is executed; suspending the repeatedly executing the single instruction step while a second context executes; and resuming the repeatedly executing the single instruction after the second context executes; wherein contents of an instruction buffer containing the single instruction are locked and preserved while the second context executes.