Patent ID: 8227900

Claim:
A semiconductor device comprising: a first interlayer insulating film having a specific dielectric constant of 3 or less; a first insulating film on the first interlayer insulating film; a seal ring formed within the first interlayer insulating film and the first insulating film so as to surround a circuit formation region; a plurality of first dummy metals which are formed as a first zig zag array of columns within the first interlayer insulating film in a dicing region of a semiconductor chip and are arranged on one side of a dummy slit in a first region outside the seal ring; the dummy slit which is surrounding the first region, the seal ring and the plurality of first dummy metals and is formed within the first interlayer insulating film in the dicing region of the semiconductor chip; and a plurality of second dummy metals which are formed as a second zig zag array of columns within the first interlayer insulating film in the dicing region of the semiconductor chip and are arranged on an opposite side of the dummy slit in a second region outside the dummy slit, wherein the columns of each of the first and second zig zag arrays are disposed in mutually offset lines so that columns of one line are opposite spaces between columns in another line, and wherein each of the seal ring, the plurality of first dummy metals, the dummy slit, and the plurality of second dummy metals includes Cu material.