Patent ID: 8521951

Claim:
An apparatus, comprising: a memory device including a plurality of memory cells; and a content-addressable memory configured to store: a first address stored in the content-addressable memory and associated with one or more memory cells from a first subset of the plurality of memory cells while a first access operation is performed on the one or more memory cells from the first subset, wherein the first subset corresponds to a first memory page; and a second address stored in the content-addressable memory and associated with one or more memory cells from a second subset of the plurality of memory cells while a second access operation is performed on the one or more memory cells from the second subset, wherein the second subset corresponds to a second memory page; wherein, in response to receipt of a command to perform the second access operation having the second address, the apparatus is configured to output a signal on an output pin of the apparatus to indicate a busy state of the first subset, and wherein the outputted signal corresponds to the first address; and wherein the first and second subsets have memory cells in common.