Patent ID: 8890243

Claim:
A semiconductor device comprising: a semiconductor substrate having a main surface; a first region of a first conductivity type formed in said semiconductor substrate; a second region of said first conductivity type formed on the main surface side of said first region in said semiconductor substrate; a third region of a second conductivity type being formed on the main surface side of said second region in said semiconductor substrate and configuring a p-n junction with said second region; a fourth region of said first conductivity type being formed on the main surface side of said second region in said semiconductor substrate so as to be in contact with said second region and be adjacent to said third region and having a first conductivity type impurity concentration higher than that of said second region; a fifth region of said second conductivity type formed in said semiconductor substrate between said first region and said second region so as to electrically isolate said first region from said second region; a sixth region of the first conductivity type being formed in said semiconductor substrate between said fifth region and said second region and having a first conductivity type impurity concentration higher than that of said second region; and a drain region being formed over said main surface so as to be in contact with said third region and having a second conductivity type impurity concentration higher than that of said third region, wherein said sixth region is located at least immediately under a junction between said third region and said fourth region so as to not overlap with said drain region in a plan view.