Patent ID: 7615784

Claim:
A thin film transistor away panel comprising: a gate conductive layer formed on an insulating substrate; a gate insulating layer on the gate conductive layer; a semiconductor layer on the gate insulating layer; a data conductive layer formed at least in part on the semiconductor layer and including a data line and a drain electrode separated from each other, the data conductive layer includes a lower film and an upper film, the lower film disposed between the upper film and the insulating substrate; a passivation layer covering the semiconductor layer; and a pixel electrode contacting the drain electrode, wherein at least one portion of the semiconductor layer is formed along with the data line, and an edge of the upper film of the drain electrode overlaps the lower film of the drain electrode, such that the lower film of the drain electrode includes a portion exposed out of the upper film of the drain electrode, and the pixel electrode contacts the exposed portion of the lower film of the drain electrode and is disposed spaced apart from the upper film of the drain electrode.