Patent ID: 7398337

Claim:
A method in a data processing system that supports virtualization for performing a record operation, wherein the record operation allows a system image to record its memory addresses with a super-privileged resource, the method comprising: receiving a memory record request from the system image; translating a first memory address used by the system image into a second memory address used by one of a system processor and system input/output chips to access memory; responsive to determining that the second memory address is associated with the system image that issued the memory record request, locating a memory record entry in one of a plurality of address translation and protection tables used by the one of a system processor and system input/output chips to access host memory; creating a peripheral component interconnect bus address associated with the second memory address; recording, into the memory record entry of the one of the plurality of address translation and protection tables a memory translation required to convert the peripheral component interconnect bus address into the second memory address; recording into the memory record entry of the one of the plurality of address translation and protection tables a bus number, device number, and function number associated with one of a plurality of peripheral component interconnect bus adapters that is associated with the peripheral component interconnect bus address and second memory address; responsive to determining that the record operation is successful, returning the peripheral component interconnect bus address to the system image that issued the memory record request; creating an indirect address translation and protection table that includes a plurality of entries, each one of the plurality of entries being referenced by a bus number, device number, and function number associated with one of the plurality of peripheral component interconnect bus adapters; including, in each one of the plurality of entries in the indirect address translation and protection table, a pointer to one of the plurality of address translation and protection tables; receiving an operation from a particular one of the plurality of peripheral component interconnect bus adapters; using a bus number, device number, and function number associated with the particular one of the plurality of peripheral component interconnect bus adapters to locate a particular entry in the indirect address translation and protection table; and using a particular pointer that is included in the located particular entry to identify a particular one of the plurality of address translation and protection tables.