Patent ID: 7812657

Claim:
A method of synchronizing a clock synchronization and skew adjustment circuit with a clock signal comprising: receiving the clock signal having a clock signal time period; and reproducing the clock signal by selectively adjusting a number of serially-connected delay elements utilized by one or more delay lines to accommodate the clock signal time period within each of the one or more delay lines; wherein each of the one or more delay lines comprises a plurality of serially-connected delay elements of differing unit time delay; wherein at least one particular delay line of the one or more delay lines comprises a portion having a set of three serially-connected delay elements in which a first delay element of the set of three serially-connected delay elements has a first unit time delay, a second delay element of the set of three serially-connected delay elements has a second unit time delay and a third delay element of the set of three serially-connected delay elements has a third unit time delay; wherein the second delay element of the set of three-serially connected delay elements is interposed between the first and the third delay elements of the serially-connected delay elements in the particular delay line; and wherein a value of the second unit time delay is between a value of the first unit time delay and a value of the third unit time delay.