Patent ID: 7143329

Claim:
An error correction system for a programmable logic device (PLD), comprising: a frame circuit arranged to retrieve data from each column of configuration memory of the PLD; a check memory for storage of a plurality of check words; a buffer circuit coupled to the check memory and to the frame circuit, the buffer circuit arranged to assemble blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory; a mask memory specifying variant memory cells of the configuration memory, wherein a value in a variant memory cell is permitted to vary during operation of the PLD; and a mask circuit coupled to the mask memory and to the buffer circuit and arranged to substitute in the blocks of data a constant value for the value of each variant memory cell; a plurality of storage elements; and a check circuit coupled to the plurality of storage elements and to the buffer circuit, the check circuit arranged to check each block with an error correcting code and store data indicating detected errors in the plurality of storage elements.