Patent ID: 7447727

Claim:
A method for simplifying a combinational logic circuit comprising one or more sub-circuits, the method comprising: replacing the one or more sub-circuits within the combinational logic circuit with one or more carry-select circuits, the one or more sub-circuits being selected from a group consisting of: a NAND gate and an inverter, both of which are fed into an XOR gate; a NOR gate and an inverter, both of which are fed into an XNOR gate; a NAND gate and an inverter, both of which are fed into an XNOR gate; and a NOR gate and an inverter, both of which are fed into an XOR gate; each carry-select circuit comprising a multiplexer being fed by an inverter and a first gate, the first gate comprising either an XOR gate or an XNOR gate; continuing to replace sub-circuits with carry-select circuits until no more sub-circuits are present in the combinational logic circuit; and removing pairs of inverters from the combinational logic circuit, the pairs of inverters comprising a first inverter and a second inverter, the first inverter being fed into a first input of a particular gate, the particular gate being either an XOR gate or an XNOR gate, the second inverter being fed into a second input of the particular gate, wherein, rather than being explicitly removed, the first inverter is combined with an outside inverter to form a buffer if the first inverter also feeds into the outside inverter, and the second inverter is simply removed; wherein the number of stages of the combinational logic circuit is reduced by one when the pairs of inverters are removed.