Patent ID: 8918687

Claim:
An integrated circuit having an output circuit comprising: A. a first data out input lead; B. a second data out input lead; C. multiplexer circuitry having a first data input, a second data input, a control input, and a data output; D. a first data out enable input lead; E. a second data out enable input lead; F. an output buffer having an input connected to the data output of the multiplexer circuitry, a control input, and an output; G. a data out output lead coupled to the data output of the output buffer; H. a clock input lead; I. clock doubler circuitry having an input connected to the clock input lead and having an output; and J. gating circuitry having: i. first gating circuitry coupling the first data out input lead to the first input of the multiplexer circuitry, ii. second gating circuitry coupling the second data out input lead to the second input of the multiplexer circuitry, iii. third gating circuitry coupling the first data out enable input lead, the second data out enable input lead, and the output of the clock doubler circuitry to the control input of the output buffer, and iv. fourth gating circuitry coupling the first data out enable input lead, the second data out enable input lead, and the output of the clock doubler circuitry to the control input of the multiplexer circuitry.