Patent ID: 8629721

Claim:
A method, comprising: controlling an output amplification stage that includes complementary first and second MOS power transistors coupled between first and second power supply rails, the controlling including: coupling a bulk of the first MOS power transistor to the first rail when the first MOS power transistor is maintained in an off state; coupling a bulk of the second MOS power transistor to the second rail when the second MOS power transistor is maintained in an off state; coupling the bulk of the first MOS power transistor to a common node of said transistors, during transition periods when the first MOS power transistor switches from an off state to an on state; and coupling the bulk of the second MOS power transistor to the common node of said transistors, during transition periods when the second MOS power transistor switches from the off state to the on state, wherein the first and second MOS power transistors respectively are a P-channel MOS transistor and an N-channel MOS transistor; the first and second power supply rails respectively are a high power supply rail and a low power supply rail; the first and second transistors having respective sources that are respectively coupled to the first power supply rail and to the second power supply rail and respective drains that are coupled to the common node.