Patent ID: 7154723

Claim:
A system comprising: a first module including first and second serial bus controllers; a first serial bus coupled to the first and second serial bus controllers; a second serial bus coupled to the first and second serial bus controllers; a second module coupled to the first and second serial buses; first and second isolation switches on the first module coupled to the first and second buses respectively; and logic on the first module for causing the first and second isolation switches to open when either the first or second serial bus controller suffers a fault, such that the serial buses are isolated from the second module, wherein the logic comprises: a watchdog timer coupled to the first and second serial bus controllers for monitoring the first and second serial bus controllers to ascertain whether the first or second serial bus controller suffers a fault; a flip-flop coupled to the watchdog timer, the clock input of the flip-flop being driven by the watchdog timer such that when the watchdog timer ascertains that either the first or second serial bus controller has suffered a fault, the clock input of the flip-flop is asserted, causing an output of the flip-flop to be asserted; the output of the flip-flop coupled to the first and second isolation switches such that when the output of the flip-flop is asserted the first and second isolation switches open.