Patent ID: 7870514

Claim:
A method of designing a pattern by using a computer, in which a grid of grid interval D, which is smaller than a minimum permissible pitch d according to a design rule for a semiconductor integrated circuit, is provided in a pattern drawing, a hole pattern is arranged on a lattice point which is an intersection of said grid, and other hole patterns are not arranged on lattice points which are adjacent to, but are a single lattice point away from, said lattice point on which said hole pattern is arranged and said other hole patterns are arranged on lattice points which are adjacent to, but are two lattice points away from said lattice point on which said hole pattern is arranged, said method comprising: determining a region using the computer including a first lattice point, a second lattice point group, and a third lattice point group as an arrangement restricted region of said first lattice point, a hole pattern being arranged on said first lattice point, said second lattice point group being of a plurality of lattice points which are on the periphery of said first lattice point, and are adjacent to said first lattice point, and said third lattice point group being of a plurality of lattice points which are on the periphery of said second lattice point group, and are within a predetermined distance from said first lattice point; and setting an upper limit for the number of hole patterns to be arranged in said third lattice point group in said arrangement restricted region of said determined first lattice point, and in said pattern drawing, assigning, for each hole pattern to be arranged on said lattice point, a lattice point on which said hole pattern is arranged as said first lattice point and arranging hole patterns not more than said upper limit in said third lattice point group of said arrangement restricted region.