Patent ID: 7162563

Claim:
A semiconductor integrated circuit comprising: a controller outputting an internal address signal consisting of a plurality of bits for accessing an external memory; a data controlling unit that activates a predetermined number of data terminals among a plurality of data terminals according to a mode signal to receive/output an external data signal from/to the external memory via the activated data terminals, and that converts the external data signal to an internal data signal with a bus width corresponding to said controller in order to receive/output the external data signal from/to said controller; and an address controlling unit that selects a predetermined number of continuous bits of the internal address signal according to the mode signal, and outputs an address signal consisting of the selected bits to the external memory as an external address signal, wherein said address controlling unit sequentially selects upper bits of the internal address signal and sequentially unselects lower bits of the internal address signal when a bus width of the external data signal is sequentially increased according to the mode signal.