Patent ID: 7783444

Claim:
A method of alternative overlay calculation in a fabrication unit, the method comprising: providing a processing unit, the processing unit being capable of receiving overlay error values from an overlay measurement tool for a plurality of measurement positions on a plurality of semiconductor wafers, and alignment data from an exposure tool suitable for exposing the plurality of semiconductor wafers, the alignment data comprising active alignment values applied by the exposure tool to respective ones of the plurality of semiconductor wafers and alternative alignment values recorded by the exposure tool; calculating, with a processing unit, alignment model parameters from the active alignment values as applied by the exposure tool for the plurality of measurement positions; calculating, with a processing unit, alternative alignment model parameters from the active alignment values for the plurality of measurement positions; and calculating, with a processing unit, alternative overlay error values based on the alignment model parameters, the alternative alignment model parameters, and the overlay error values for the plurality of measurement positions, wherein the alternative overlay error values comprise alternative alignment recipes of alignment marks on the plurality of wafers with respect to the active alignment values.