Patent ID: 6990206

Claim:
An integrating apparatus comprising: a plurality of integrating circuits each operable to integrate an input signal and to output an integrated signal, said plurality of integrating circuits each having a different fall time constant; an output unit operable to selectively derive an output having a lowest level from among integrated signals output from said plurality of integrating circuits; and a plurality of first amplifiers operable to amplify the input signal and to output the amplified input signal to said plurality of integrating circuits, respectively; wherein each of said plurality of first amplifiers has an amplification factor corresponding to the fall time constant of a respective one of said plurality of integrating circuits to which the input signal is inputted such that the amplification factor is larger when the fall time constant is smaller; and wherein each of said plurality of integrating circuits comprises: an adder operable to add the amplified input signal and a feedback signal, and to output a resultant added signal; a delaying unit operable to delay the resultant added signal and to produce a delayed output signal; and a second amplifier operable to amplify the delayed output signal and to produce an amplified output signal, wherein the amplified output signal output from said second amplifier is inputted to said adder as the feedback signal, and the resultant added signal is produced as the integrated signal output from said integrating circuit.