Patent ID: 7436246

Claim:
A pin number reduction circuit and methodology providing a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and system-on-chip, comprising: a first resistor string and a first transistor connected in series between a positive power supply and a negative power supply for generating the higher pseudo power supply at any node between serially coupled components that mean the first transistor and resistors of the first resistor string in a path from the positive power supply to the negative power supply, wherein the first transistor has a drain node connected to the top node of the first resistor string; a first amplifier having a negative input that receives a top reference voltage input, a positive input that is connected to a node between serially coupled resistors of the first resistor string, and an output terminal that is connected to a gate node of the first transistor; a second resistor string and a second transistor connected in series between the positive power supply and the negative power supply for generating the lower pseudo power supply at any node between serially coupled components that mean resistors of the second resistor string and the second transistor in a path from the positive power supply to the negative power supply, wherein the second transistor has a drain node connected to the bottom node of the second resistor string; a second amplifier having a negative input that receives a bottom reference voltage input, a positive input that is connected to a node between serially coupled resistors of the second resistor string, and an output terminal that is connected to a gate node of the second transistor; and wherein the digital functional section is coupled between the higher pseudo power supply and the lower pseudo power supply.