Patent ID: 6919632

Claim:
A semiconductor integrated circuit device comprising: a chip; connection members arranged on said entire chip and connected to an external circuit of said chip; a first I/O cell which is arranged on a periphery of said chip and has a first end portion on a peripheral side of said chip and a second end portion on a center side of said chip; a second I/O cell which is arranged inside said first I/O cell and has a third end portion on the peripheral side of said chip and a fourth end portion on the center side of said chip; first terminals formed on the first end portion and connected to said connection members; second terminals formed on the second end portion and connected to and internal circuit of said chip; third terminals formed on the third end portion and connected to the internal circuit of said chip, both the second and third terminals disposed along a direction extending from the first end portion to the second end portion and opposed to each other; fourth terminals formed on the fourth end portion and connected to said connection members; a first ESD protective element provided in the first I/O cell and connected to the first terminal; and a second ESD protective element provided in the second I/O cell and connected to the fourth terminal.