Patent ID: 8242829

Claim:
A system, comprising: clock generator circuitry operable to receive an input clock representing a multichannel interpolated output signal frequency multiplied by a number of channels, generating a select signal and a plurality of output clocks; a first stage multiplexer operable to receive a multichannel input signal for sampling and a first stage shift register output, a first stage multiplexer output being based on the select signal; a first stage shift register operable to receive the first stage multiplexer output, said first stage shift register operable with said input clock to provide the first stage shift register output, said first stage shift register having a length that correlates to the number of channels; one or more next stage multiplexers operable to receive a previous stage shift register output and a respective next stage shift register output, the one or more next stage multiplexer outputs being based on a select signal; one or more next stage shift registers operable to receive a respective next stage multiplexer output and the said input clock, and to provide the respective next stage shift register output, said one or more next stage shift registers being the length of the first stage shift register, and wherein the number of shift registers and multiplexers is based upon a number of interpolation points; a data store operable to provide impulse response coefficient; a plurality of multipliers operable to multiply associated shift register output with impulse response coefficient; and an adder operable to sum multiplier outputs thereby generating the multichannel interpolated output signal.