Patent ID: 8106688

Claim:
A power-on reset circuit, comprising: a first circuit, comprising: a first NMOS transistor having a gate controlled by a low voltage supply VDD_L; a resistor connected between the source of the first NMOS transistor and a voltage supply VSS, wherein VSS is lower than VDD_L; and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor, wherein VDD_H≧VDD_L; and a second circuit, comprising: a first PMOS transistor having a source connected to VDD_L; a second PMOS transistor having a source connected to the drain of first PMOS transistor; a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, wherein the gates of the first PMOS transistor, the second PMOS transistor, and the second NMOS transistor are connected to the source of the first NMOS transistor; and an inverter having an input connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor, wherein the inverter is configured to output a signal RSTB in response to the power on and power off of the high voltage supply VDD_H and the low voltage supply VDD_L.