Patent ID: 7839317

Claim:
A folding comparator circuit comprising: an analog input signal current port and a dc reference current port and an analog output signal current port and an analog input signal current which is applied to the said analog input signal current port and a dc reference current which is applied to the said dc reference current port; and the said analog input signal current port and the said dc reference current port together also constitute a differential digital voltage output port; and a matched transistor pair consisting of a first type one and a second type one having collector of said first type one connected to the said analog input signal current port and having collector of said second type one connected to the said dc reference current port and having base of said first type one connected to base of said second type one and having emitters of said first type one and said second type one coupled through matched resistive paths to a signal ground potential; and a second transistor pair consisting of a third type one and a fourth type one having emitter of said third type one connected to emitter of said fourth type one together with the common bases of said first type one and said second type one and having collectors of said third type one and said fourth type one connected to an appropriate supply voltage and having base of said third type one coupled to the said analog input signal current port and having base of said fourth type one coupled to the said dc reference current port; whereby both said first type one and said second type one become self biased to have matched collector currents equal to the greater of the said analog input signal current or the said dc reference current; and a third transistor pair consisting of a fifth type one and a sixth type one having emitter of said fifth type one connected to the said dc reference current port and having emitter of said sixth type one connected to the said analog input signal current port and having both collectors of said fifth type one and said sixth type one coupled to said analog output signal current port and having base of said fifth type one connected to an appropriate circuit node and having base of said fifth type one connected to an optionally different appropriate circuit node; whereby the emitters of the said fifth type one or the said sixth type one will limit the voltage swing at the said differential digital voltage output port by coupling emitter currents to the connected collectors of said fifth type one and said sixth type one which couples to the said analog output signal current port a current of a value proportional to the said analog input signal current folded around the said dc reference current.