Patent ID: 8719648

Claim:
A structure, comprising: a plurality of fuse macros arranged in a serial configuration, each fuse macro organized with rows and columns having programmable fuse elements, wherein each row in a fuse macro is concatenated with a corresponding row in an adjacent fuse macro, each concatenated row across the plurality of fuse macros forming a fuse page of programmable fuses, each of the fuse pages formed across each of the rows of the plurality of fuse macros defining a plurality of fuse pages arranged in a vertical configuration; a fuse register that is shared across each of the rows of the plurality of fuse macros for each of the plurality of fuse pages in the fuse macros, wherein the fuse register is separated into segments arranged in a serial configuration that are each configured to interface with each of the rows and fuse pages in one of the plurality of fuse macros; and a fuse controller that facilitates a memory repair data compression operation and a fuse programming operation performed within the plurality of fuse macros and the fuse register on repair data stored in a repair register, the memory repair data compression operation and the fuse programming operation being performed as a single combinable operation that includes partitioning the memory repair data compression operation into a plurality of compression operations, partitioning the fuse programming operation into a plurality of fuse programming operations, and interleaving the plurality of partitioned compression operations with the plurality of partitioned fuse programming operations, wherein a first partitioned memory repair data compression operation is performed and a first partitioned fuse programming operation is performed upon completion of the first partitioned memory repair data compression operation, a second partitioned memory repair data compression operation is performed after completing the first partitioned fuse programming operation and a second partitioned fuse programming operation is performed upon completion of the second partitioned memory repair data compression operation, the interleaving sequence of performing the partitioned memory repair data compression operations with the partitioned fuse programming operations continuing until the repair data in the repair register has been exhausted and reprogrammed by the plurality of fuse macros.