Patent ID: 7948813

Claim:
A non-volatile semiconductor memory device comprising: at least one memory cell each having a non-volatile memory element; a first line to which a first end of the memory element is connected; a second line to which a second end of the memory element is connected; a first write circuit which includes a first transistor, the first transistor supplying a first write voltage to the first line; a second write circuit which includes a second transistor, the second transistor supplying a second write voltage to the second line; a third write circuit which includes a third transistor and which is controlled so as to be paired with the first write circuit in a first write operation, the third transistor supplying a third write voltage to the second line; a fourth write circuit which includes a fourth transistor and which is controlled so as to be paired with the second write circuit in a second write operation, the fourth transistor supplying a fourth write voltage to the first line; a first read circuit which includes a fifth transistor and which is controlled so as to be paired with the fourth write circuit in a read operation, the fifth transistor supplying a read voltage to the second line; an amplifier circuit which amplifies a first voltage read out from the memory element onto the second line by the read operation for supplying the read voltage to the second line by the fifth transistor and outputs a second voltage obtained by amplifying the first voltage; a comparator circuit which includes a retaining part to retain the second voltage, and which compares a third voltage appearing on the second line during the second write operation with the second voltage retained by the retaining part; and a read logic state output circuit which outputs a logic state corresponding to a state stored in the memory element before the read operation, as a read logic state on the basis of a result of the comparison performed by the comparator circuit.