Patent ID: 7282450

Claim:
A dual damascene process comprising: on a first wiring layer, providing a dielectric layer having an upper surface and a thickness; forming a via hole that extends from said upper surface to said first wiring layer; patterning and etching said dielectric layer, thereby forming a trench having a bottom surface, a mouth, and side walls, said trench being disposed so as to fully overlap said via hole and to extend a depth below said upper surface, said depth being greater than a depth of said via hole, wherein the depth of the via hole extends a distance from said trench bottom surface to the first wiring layer; by means of PVD, depositing a metal-containing layer to coat the dielectric layer; said bottom surface, and said side walls; reducing the metal-containing layer by an amount to remove any overhang present at the mouth of the trench; forming a filler layer that overfills the trench and via hole; and planarizing said filler layer to form a metal conductive via whose aspect ratio is less than about 6:1 whereby its electrical resistance is less than about 1 ohm.