Patent ID: 7148753

Claim:
An apparatus comprising: a first phase-locked loop circuit including a crystal oscillator coupled to receive a reference clock signal in normal operational mode and to supply a first phase-locked loop output signal based on the reference clock signal during the normal operational mode; a second phase-locked loop circuit coupled to utilize the first phase-locked loop output signal when generating an output clock in a holdover mode and wherein the first phase-locked loop includes a loop filter having outputs that are held in response to the holdover mode to a value corresponding to one or more clock signals received prior to entering the holdover mode and the first phase-locked loop is coupled to utilize the outputs of the loop filter that are held in response to the holdover mode while in holdover mode in generating the first-phase locked loop output signal instead of the reference clock signal; and wherein the second phase-locked loop is coupled to utilize the first phase-locked loop output signal to generate the output clock during operation in the holdover mode and during the normal operational mode.