Patent ID: 8390611

Claim:
An image display system, comprising: a gate driver circuit, comprising: a plurality of stages of gate drivers, each for generating a gate driving signal to drive a row of pixels in a pixel array, wherein each stage of the gate driver circuit receives a clock signal and a first reset signal, a first stage of the gate driver circuit receives a vertical start pulse as an input signal of the first stage, the remaining stages of the gate drivers respectively receive the gate driving signal generated by a previous stage of the gate driver circuit as the corresponding input signal of the remaining stages, and each stage of the gate drivers further receives the gate driving signal generated by a next stage of the gate driver circuit as a second reset signal, and wherein each stage of the gate driver comprises: an input circuit, comprising a first transistor directly coupled between a first supply voltage and a node and receiving the input signal; a reset circuit, directly coupled to the node and generating a control signal at the node, wherein the reset circuit comprises: a second transistor, directly coupled between a second supply voltage and the node and receiving the first reset signal; and a third transistor, directly coupled between the second supply voltage and the node and receiving the second reset signal, wherein the first transistor, the second transistor and the third transistor are turned on or off according to the input signal, the first reset signal and the second reset signal, respectively, and the control signal is generated at the node according to the first supply voltage and the second supply voltage; a storage circuit, directly coupled to the node and comprising a latch for storing the control signal; and an output circuit, directly coupled to the storage circuit and comprising: a fourth transistor, having a first terminal receiving the control signal and a second terminal receiving the clock signal; and a fifth transistor, having a first terminal receiving the control signal and a second terminal directly coupled to the second supply voltage, wherein the fourth transistor and the fifth transistor are respectively turned on or off according to the control signal, and the gate driving signal is generated according to the clock signal and the second supply voltage.