Patent ID: 8409951

Claim:
A method of forming a memory array comprising non-volatile storage elements and transistors, the method comprising: forming a first region of polysilicon for floating gates of non-volatile storage elements and for lower portions of control gates of transistors; forming a dielectric conformably over the first region of polysilicon to be used for an inter-poly dielectric of the non-volatile storage elements; forming a second region of polysilicon conformably over the dielectric, the second region of polysilicon for lower portions of control gates of the non-volatile storage elements; etching through the second region of polysilicon and the dielectric in regions in which the control gates of the transistors are to be formed to expose the first region of polysilicon; depositing sacrificial material over at least the second region of polysilicon and the exposed portion of the first region of polysilicon; forming first stacks for non-volatile storage elements from portions of the first region of polysilicon, portions of the dielectric, portions of the second region of polysilicon, and portions of the sacrificial material; forming second stacks for control gates of transistors from portions of the first region of polysilicon and portions of the sacrificial material; forming one or more insulating regions adjacent to the first stacks and the second stacks; removing the sacrificial material to reveal first openings in the first stacks and second opening in the second stacks between the one or more insulating regions; and depositing metal in the first openings and the second openings, control gates of the non-volatile storage elements are formed at least in part from the metal in the first openings and adjacent portions the second region of polysilicon, control gates of the transistors are formed at least in part from the metal in the second openings and adjacent portions of first region of polysilicon.