Patent ID: 7902598

Claim:
A memory device comprising; a semiconductor substrate; a plurality of charge storage devices coupled with the semiconductor substrate; a plurality of digit lines coupled with the semiconductor substrate; a plurality of gates each electrically interposed between a charge storage device and a digit line wherein a gate, a charge storage device and a digit line define a memory cell, wherein each of the gates is formed so as to be recessed into the semiconductor substrate such that a first depletion region is formed within the semiconductor substrate and such that, when the gate is activated, a conductive path is formed about the perimeter of the recessed gate within the semiconductor substrate to thereby allow charge to flow between the charge storage device and the corresponding digit line; a plurality of isolation structures each formed so as to be recessed within the semiconductor substrate so as to isolate adjacent memory cells and so as to define a second depletion region for each of the isolation structures within the semiconductor substrate, wherein the plurality of isolation structures are biased such that the second depletion region merges with the corresponding first depletion region to isolate adjacent cells from each other.