Patent ID: 7262452

Claim:
a DRAM device comprising: a first well having a first depth in a semiconductor substrate; a second well having a second depth shallower than the first depth in the first well; a device isolation layer in the semiconductor to define an active region; a gate pattern formed on the semiconductor substrate; a first impurity implantation region being formed in the active region at both sides of the gate pattern and having a third depth shallower than the second depth; at least one interlayer dielectric layer covering the gate pattern and the semiconductor substrate; a cup-shaped lower electrode formed through the at least one interlayer dielectric layer and through a portion of the semiconductor substrate, the cup-shaped electrode located at one side of the gate pattern, wherein an upper surface of the lower electrode has the same height as that of the interlayer dielectric layer, wherein a lowermost surface of the lower electrode is positioned in the substrate shallower than the first depth and deeper than the second depth; a dielectric layer coating an inner sidewall and a bottom of the lower electrode, and a portion of the interlayer dielectric layer around a top of the lower electrode; an upper electrode on the dielectric layer; a second impurity implantation region formed in the semiconductor substrate in contact with the lower electrode below the second depth; and a third impurity implantation region formed in the semiconductor substrate in contact with the lower electrode below the third depth and formed in the second impurity implantation region and the second well, wherein the first well, the first impurity implantation region, and the third impurity implantation region are doped with impurities of a first type, and wherein the second well and the second impurity implantation region are doped with impurities of a second type.