Patent ID: 6900681

Claim:
A phase interpolator for adjusting a phase of differential clock signals of a receiver to a phase of a data from a transmitter, the phase interpolator comprising: an integrator configured to slew output signals of a mixer connectable to the interpolator, the mixer outputting said differential clock signals and configured to change swings of the differential clock signals to change capacitance in the integrator upon receiving a signal from a controller; an output buffet configured to amplify output signals of the integrator, a duty cycle correction circuit configured to receive the amplified signals from the output buffer and adjust duty ratios of the output signals of the output buffer to output adjusted differential clock signals; and the controller configured to receive the adjusted differential clock signals and determine whether or not voltages of the adjusted differential signals are amplifiable by the output buffer, the controller configured to output the signal to the integrator to change capacitance of the integrator, wherein the controller comprises: a first comparison unit configured to determine whether or not the adjusted differential clock signals and the swings of the differential clock signals satisfy a standard voltage that the output buffer is able to amplify, wherein an output of the first comparison unit is coupled to a capacitor and an inverter to switch the inverter when a voltage of the output of the first comparison unit reaches a predetermined voltage, wherein an output of the inverter is coupled to a gate of an NMOS transistor, wherein the NMOS transistor is coupled to the capacitor in the integrator and the adjusted differential clock signal, wherein the integrator is configured to change a capacitance of a capacitor in the integrator in accordance with switching the gate of the NMOS transistor.