Patent ID: 6965540

Claim:
A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; a memory controller generating a row address having a plurality of row address bits followed by a column address having a plurality of column address bits, the memory controller generating an array select signal having either a first state or a second state; and a memory device coupled to the memory controller, the memory device comprising: a row decoder coupled to the memory controller to receive the row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address; a column decoder coupled to the memory controller to receive the column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and first and second arrays of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address, each of the first and second arrays having a respective set of row lines; a data path circuit operable to couple data signals corresponding to the data between the first and second arrays and an external data terminal; a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal; a mode select circuit' generating a mode select signal indicative of operation in either a first or a second mode; and a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.