Patent ID: 7511371

Claim:
A multiple die semiconductor package, comprising: an insulator having a first surface, a second surface opposing the first surface, and one or more through-hole vias at predetermined locations; a first leadframe at least partially overlying the first surface and having a plurality of leads, portions of the leads overlying one or more through-hole vias deflected into the one or more through-hole vias; a first integrated circuit die adjacent to and electrically coupled to at least one of the plurality of leads of said first leadframe; a second leadframe at least partially overlying the second surface and having a plurality of leads; and a second integrated circuit die adjacent to and electrically coupled to at least one of the plurality of leads of said second leadframe; wherein at least one of the plurality of said leads of said first leadframe is electrically coupled to a corresponding one of the plurality of leads of said second leadframe through one of the through-hole vias in said insulator.