Patent ID: 7647476

Claim:
An apparatus comprising: a processor socket including: a first processor core adapted on a semiconductor die to execute instructions, the first processor core including first digital interface circuitry; a second processor core adapted on the semiconductor die to execute instructions, the second processor core including second digital interface circuitry; an analog interface coupled to the first processor core via the first digital interface circuitry and to the second processor core via the second digital interface circuitry, the analog interface to communicate bus traffic between the processor socket and a computer system bus coupled thereto, the analog interface including buffer circuitry to buffer digital signals to a level for transmission along a common clock data line of the computer system bus, the interface to present a single electrical load from the first and second processor cores to the interconnect; and a common digital interface logic coupled between the first and second digital interface circuitries and the analog interface, the common digital interface logic including a multiplexer to select the bus traffic from the first processor core or the second processor core for communication on the interconnect, wherein the multiplexer has a first input to receive data of the first core, a second input to receive data of the second core, and a third input to receive an output of selection logic coupled to receive the data of the first core and the data of the second core and to emulate a wired OR bus, the multiplexer to select the data from the first input or the second input during a test mode and to select the output of the selection logic from the third input during a normal operation mode.