Patent ID: 7023284

Claim:
A dual loop PLL comprising: a frequency comparison loop which includes a frequency comparator and a phase comparison loop which includes a phase comparator, wherein in the frequency comparison loop, a frequency comparison between a reference frequency and an output frequency is performed based on a dichotomizing search method, and wherein the frequency comparison loop includes: the frequency comparator, an up/down counter for incrementing or decrementing a count value according to a comparison result from the frequency comparator, and a voltage controlled oscillator for changing the output frequency according to the count value of the up/down counter; and the up/down counter includes: a register for storing the count value, an input control circuit for outputting a positive or negative value of a ½ of a previous addition/subtraction result value according to the comparison result from the frequency comparator, and an adder for adding the count value of the register to the output of the input control circuit.