Patent ID: 7642544

Claim:
A method for fabricating a semiconductor component having a stress-absorbing semiconductor layer, comprising the steps of: a) forming a carrier material having a first lattice constant; b) forming a crystalline stress generator layer having in its final atom layer substantially a second lattice constant being different from the first lattice constant on the carrier material in order to generate a mechanical stress; c) forming an insulating stress transmission layer having a third lattice constant being matched to first lattice constant of the carrier material on the stress generator layer for transmitting the mechanical stress that has been generated; d) forming a crystalline, stress-absorbing semiconductor layer having a lattice constant different from the second lattice constant, which is different than the first lattice constant, on the stress transmission layer for the purpose of absorbing the mechanical stress; e) forming a gate dielectric on the stress-absorbing semiconductor layer; f) forming a control layer on the gate dielectric; g) patterning the gate dielectric and the control layer; and h) forming source/drain regions in the stress-absorbing semiconductor layer.