Patent ID: 6841889

Claim:
A semiconductor die, comprising: a substrate; and an integrated circuit supported by the substrate, wherein the integrated circuit includes pattern features with an overlay error that is affected by modified coordinates of a plurality of mask features within at least two zones within a field of a mask, and wherein the integrated circuit is produced by a process comprising the use of the mask, further wherein the mask is produced by a method comprising: determining overlay error variation across the field of the mask; defining the at least two zones within the field of the mask, wherein each zone is a continuous portion of the field containing substantially similar overlay error values, and wherein each zone has a nominal overlay error value; defining a correction for each of the at least two zones, wherein the correction for each zone is approximately the nominal overlay error value for that zone; mapping each of the plurality of mask features to one of the at least two zones; and modifying coordinates of each of the plurality of mask features in response to the correction for the zone in which each feature is mapped.