Patent ID: 7696972

Claim:
A single clock driven shift register, comprising: multiple stages electrically connected to each other, the (M)th stage comprising a latch unit for latching an input signal from the (M−1)th stage responsive to a clock signal; a logic unit, connected with an output terminal of the latch unit, for applying a logical operation to an output signal of the latch unit and the clock signal; and a non-overlap buffer including at least three serially connected inverters and being connected with the output terminal of the logic unit, whereby an output signal of the (odd-number)th inverter coupled to the output terminal of the logic unit is input to a latch unit of the (M+1)th stage, and an output signal of a non-overlap buffer of the (M−1)th stage is input to the non-overlap buffer to delay an output signal of the non-overlap buffer.