Patent ID: 7639801

Claim:
A method of transforming a serial scrambler to a parallel scrambler for transforming a serial scrambler to a parallel scrambler with M-bit output, the parallel scrambler comprising a plurality of XOR gates and registers, and an output of each of the XOR gates connected to an input of one of the registers, the serial scrambler having a characteristic polynomial: P ⁢ ⁢ ( x ) = ∑ q = 0 N ⁢ ⁢ c q ⁢ x ⁢ q , wherein N represents a total stage of the registers of the serial scrambler, when an output terminal of a q th -stage register is connected to the XOR gates, c q =1 or c q =0, the method of transforming the serial scrambler to the parallel scrambler comprising: setting a transformation number R, wherein R=2 t , t is an integer equal to or larger than 0 and has an initial condition 0; gaining a transformation formula b ( kN + i ) = ∑ q = 1 N ⁢ ⁢ c q ⁢ b ( ( k - R ) ⁢ ⁢ N + i + R ⁢ ⁢ ( N - q ) ) according to the characteristic polynomial to arrange parallel bits in the order of B j =[b Mj , b Mj+1 , . . . , b Mj+M−2 , b Mj+M−1 ], wherein b Mj+p represents an output of a p th bit of a j th byte from the parallel scrambler, and b Mj+p is generated from an output of one of the registers, wherein k is a quotient of Mj + p N , i is a remainder of Mj + p N , j is an integer larger than or equal to 0, and p is an integer larger than or equal to 0 and smaller than M; operating the transformation formula; adding 1 to t in R=2 t and re-counting the transformation formula when (k−R)N+i+R(N−q) is larger than Mj−1; and determining a coupling relationship between the XOR gates and the registers according to a computed result from the transformation formula.