Patent ID: 8530286

Claim:
A method for fabricating an integrated circuit having transistor devices defined on a substrate: forming a first screening layer for a first digital device, the first screening layer being positioned below a first gate of the first digital device, the first screening layer having a first dopant concentration between 1×10 18 to 1×10 20 atoms/cm 3 ; forming a second screening layer for a second device type, the second screening layer being positioned below a second gate of the second device type, the second screening layer having a second dopant concentration between 1×10 18 to 1×10 20 atoms/cm 3 ; performing an epitaxial deposition to form a common epitaxial layer for the first digital device and the second device type, the common epitaxial layer being positioned above and adjacent to the first screening layer and the second screening layer; maintaining at least a portion of the common epitaxial layer as a substantially undoped channel region for the first digital device, the substantially undoped channel region of the first digital device having a first dopant concentration less than 5×10 atoms/cm 3 ; and performing a shallow trench isolation between the first digital device and the second device type by etching the common epitaxial layer to form a trench and depositing a dielectric within the trench, the shallow trench isolation being performed after forming the common epitaxial layer, wherein the shallow trench isolation extends beyond the first screening layer and the second screening layer.