Patent ID: 6963969

Claim:
A processor comprising: a first initial setting area which is initialized based on an input of a first reset signal; a second initial setting area which is initialized based on an input of either the first reset signal or a second reset signal not overlapping with said first initial setting area; a first flag that is cleared by an input of the first reset signal and that is set when initial setting of the first initial setting area has been completed; and a second flag that is cleared by an input of either of the first and second reset signals and that is set when initial setting of the second initial setting area has been completed, wherein: when the first reset signal is input, the first input setting area is initialized after confirmation that the first flag is cleared and the second initial setting area is initialized after confirmation that the first flag is set and the second flag is cleared, and when the second reset signal is input, the second initial setting area is initialized after confirmation that the first flag is set and the second flag is cleared without clearing the first flag.