Patent ID: 7650586

Claim:
A concurrent development method for concurrent development of an ASIC and a programmable logic device, comprising: grouping/creating, by a computer, including grouping functional blocks constituting the ASIC based on port connection information, and creating a netlist, including ports of the functional blocks grouped and the port connection information, as a logic core of the programmable logic device; a logic synthesis data creating including creating logic synthesis data for the ASIC and logic synthesis data for the programmable logic device from circuit data of the functional blocks constituting the ASIC; a ROM data creating including creating ROM data by inserting the logic synthesis data for the programmable logic device relating to the functional blocks grouped, into the netlist created at the grouping/creating, wherein the ROM data is used for evaluating real machines in which a circuit of the programmable logic device is recorded; performing ASIC layout creation and timing verification concurrently with the ROM data creating, using the logic synthesis data for the ASIC created; and a difference reflecting including reflecting a change in the circuit data during the performing, based on a result of evaluating the real machine using the ROM data created.