Patent ID: 7620778

Claim:
A method for operating a cache memory in association with an addressable memory of a digital signal processor, comprising the steps of: associating a plurality of cache memory match lines with a plurality of addressable memory lines, each of said plurality of cache memory match lines associated with one of a plurality of corresponding sets of said cache memory; storing a valid indicator for each corresponding set of said cache memory wherein said valid indicator is stored separately from said corresponding set of cache memory; maintaining each cache memory match line of said plurality of cache memory match lines at a low voltage; selecting a particular set of the cache memory, the selected set determined by a set index of a memory address of data to be retrieved from the cache memory; determining whether said selected set of the cache memory contains valid data using the valid indicator corresponding to the selected set; selectively pre-charging only one of said plurality of cache memory match lines that is associated with the selected set of the cache memory and only when the valid indicator corresponding to the selected set indicates that the selected set contains valid data; and performing a comparison operation that discharges the cache memory match line that is pre-charged and that is not associated with the memory address of the data to be retrieved, wherein the pre-charged cache memory match line is returned to said low voltage following the comparison operation.