Patent ID: 8370677

Claim:
A system, comprising: a clock circuit configured to produce a clock signal; and an encoder circuit coupled to the clock circuit, the encoder circuit configured to modulate the clock signal with common time basis information to produce a modulated clock signal, the modulated clock signal comprising: a first logic value having: a first period followed by a second period, the second period followed by a third period, and the third period followed by a fourth period, wherein the first and third periods each have a first duty cycle, and the second and fourth periods each have a second duty cycle that is complementary to the first duty cycle; and a second logic value having: a fifth period followed by a sixth period, a seventh period following the sixth period, and an eight period following the seventh period, wherein: (a) the fifth and sixth periods each have the first duty cycle and the seventh and eight periods each have the second duty cycle, or (b) the fifth and sixth periods each have the second duty cycle and the seventh and eight periods each have the first duty cycle.