Patent ID: 8755428

Claim:
A feed-forward equalization circuit, comprising: delay circuitry comprising n parallel sample-and-hold circuits that are clocked by multiphase clocks to generate n time-delayed versions of an input data signal; and a current-integrating summer circuit, comprising: a first power supply node and an output node; a first switch connected between the first power supply node and the output node, wherein the first switch is responsive to a reset control signal to connect the output node to the first power supply node and precharge a capacitance of the output node during a reset period of the current-integrating summer circuit, and to disconnect the output node from the first power supply node during an integrating period of the current-integrating summer circuit; and a plurality of m transconductance amplifier circuits connected to the output node, wherein each of the m transconductance amplifier circuits receives as input a data signal that corresponds to one of the n time-delayed versions of the input data signal, and generates an output current on the output node, wherein the output currents from the m transconductance amplifier circuits collectively charge or discharge the capacitance of the output node during the integration period; wherein at least one transconductance amplifier circuit of the m transconductance amplifier circuits comprises a gating control circuit, wherein the gating control circuit is responsive to a gating control signal to disable the at least one transconductance amplifier circuit during a portion of the integration period in which the data signal input to the at least one transconductance amplifier circuit is invalid.