Patent ID: 8178369

Claim:
A method of fabricating a nanoscale multi-junction quantum dot device, the method comprising the steps of: (a) patterning a source and a drain, connected through a channel, on top silicon of a wafer, and etching the wafer; (b) doping ions into the source, the drain and the channel; (c) forming a first dielectric film on the top silicon; (d) depositing a first conductive layer to surround the first dielectric film; (e) coating a resist on the first conductive layer; (f) forming at least three resist lines by developing the resist; (g) etching the first conductive layer to the first dielectric film except for the respective resist lines, thus forming nanoscale patterns respectively having the same line width as that of the resist line; (h) forming a second dielectric film for insulation on each nanoscale pattern; (i) depositing a second conductive layer between the nanoscale patterns on which the second dielectric films are formed; (j) polishing the wafer to expose the surface of top silicon; (k) forming a dielectric film for electrical insulation on the top silicon; (l) depositing a third conductive layer on the dielectric film; and (m) patterning and etching at least two sensing elements, which corresponds to at least two quantum dots, which are formed in the channel in the polishing step (j), and are adjacent to each other.