Patent ID: 7875516

Claim:
A method of manufacturing an integrated circuit including non-volatile memory cells, comprising: providing a first gate stack comprising a gate dielectric on a first surface section of a main surface of a semiconductor substrate, wherein providing the first gate stack comprises depositing a first non-patterned gate stack on the main surface; providing a second gate stack comprising a memory layer stack on a second surface section, wherein a configuration of the memory layer stack differs from that of the gate dielectric, and wherein providing the second gate stack on the second surface section comprises: depositing a second non-patterned gate stack on the second surface section and the first gate stack; covering a section of the second non-patterned gate stack above the second surface section with a first block mask; and removing an exposed section of the second non-patterned gate stack to form the second gate stack; providing a hard mask over the first and second gate stacks, the hard mask comprising a first pattern above the first gate stack and a second pattern above the second gate stack; and transferring the first pattern into the first gate stack and the second pattern into the second gate stack, wherein sections of the main surface are exposed.