Patent ID: 7295053

Claim:
A delay-locked loop (DLL) circuit having a reference signal input for receiving a periodic reference signal and at least two signal outputs for outputting respective output signals derived from the periodic reference signal and having a desired phase relationship with one another, the DLL circuit comprising: (a) a variable delay line comprising a plurality of nominally identical delay stages connected in series, the delay at each stage being adjustable in response to a delay control signal, the variable delay line including an input node of the first of said identical stages, one or more intermediate nodes at which an output of one of said identical stages is coupled to an input of a next stage, and an end node comprising an output of a last one of said identical stages in the variable delay line; (b) a delay line input path for feeding said periodic reference signal to an input node of the delay line; (c) a plurality of delay line output paths for deriving said output signals from respective ones of said nodes; and (d) a feedback control arrangement including a phase comparator and delay control signal generator for generating said delay control signal and applying it to the variable delay line such that a total delay over a number of said stages corresponds in a known manner to a period of the periodic reference signal, wherein the feedback control arrangement further comprises stop detection circuitry for detecting automatically interruptions in said periodic reference signal and interrupting feedback control of the variable delay line by the feedback control arrangement.