Patent ID: 7343507

Claim:
An input circuit comprising: an input; a voltage divider with a center tap; a time delay element; a control device; and means for high level and low level connection, wherein a first pole of the voltage divider forms the input of the input circuit, a signal input of the time delay element is located at the center tap of the voltage divider, and an output of the time delay element is connected to the control device, wherein the means for the high level and low level connection are controlled by the control device and act on the signal input, the control device is connected to the time delay element via a clock line, and a delay time of the time delay element is influenced by means of a clock signal that is transmitted via the clock line, wherein the clock signal transmitted via the clock line acts on a counter of the time delay element, and the delay time of the time delay element is determined by the expiration of the counter, and wherein a start value or threshold value of the counter is predefined.