Patent ID: 7952411

Claim:
A method of delaying successive first and second input signal edges by first and second different selectable time periods using a programmable delay line, the method comprising: providing a control signal to each of a plurality of delay elements associated with said programmable delay line, the control signal selectively being in a first logic state or a second logic state, wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the adjacent delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the adjacent delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period, wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the first logic state to introduce the second selectable time period, wherein the control signals for the delay elements in the sequence not in the second number are set to the second logic state and wherein a reconfiguration time between outputting the delayed first input signal and receiving the second input signal is less than the maximum delay introduced by the sequence of delay elements.