Patent ID: 7344897

Claim:
A method of forming a memory device, comprising: providing a semiconductor structure; forming a first insulator layer having a flat top surface above said semiconductor structure; and, subsequently, forming a trench in said first insulator layer, wherein said trench has a depth less than the thickness of said first insulator layer; forming a first adhesion layer above said first insulator layer and in said trench; forming a first conductive layer above said first adhesion layer, wherein said first adhesion layer binds said first conductive layer to said first insulator layer; planarizing said first conductive layer and said first adhesion layer to form a first electrode in said trench, wherein the top surface of said first electrode is planar with the top surface of said first insulator layer; forming a first ferroelectric polymer layer having a flat top surface above said first electrode and said first insulator layer; forming a second conductive layer having a flat top surface above said first ferroelectric polymer layer; forming a second adhesion layer having a flat top surface above said second conductive layer; subtractively patterning said second adhesion layer and said second conductive layer to form a second electrode above said first ferroelectric polymer layer, wherein said second electrode comprises a conductive portion and an adhesion portion; forming a second insulator layer having a flat top surface above said second electrode, wherein said adhesion portion of said second electrode binds said conductive portion of said second electrode with said second insulator layer; forming a series of trenches in said second insulator layer to expose regions of said first and said second electrodes; and forming a contact conductive layer in said series of trenches to form a series of contacts to said first and second electrodes.