Patent ID: 7462523

Claim:
A method of manufacturing a semiconductor memory device, comprising: forming a first interlayer insulating structure on a semiconductor substrate; forming a plurality of first conductive layers spaced apart from each other and disposed on the first interlayer insulating structure; forming a second interlayer insulating structure on the plurality of first conductive layers, the second interlayer insulating structure comprising a lower portion and an upper portion; forming a plurality of second conductive layers spaced apart from each other and disposed on the second interlayer insulating structure; forming at least one first plug structure extending from the semiconductor substrate into the lower portion of the second interlayer insulating structure: forming a pad in the upper portion of the second interlayer insulating structure, the pad electrically connecting the at least one first plug structure and one of the second conductive layers; forming a second plug structure connecting one of the first conductive layers and the semiconductor substrate, wherein one of the first conductive layers is connected to a source area of a connection control transistor formed on the semiconductor substrate via the second plug structure, wherein one of the second conductive layers is connected to a drain area of the connection control transistor formed on the semiconductor substrate via the at least one first plug structure, wherein the one of the second conductive layers connected to the pad is not electrically connected to an adjacent second conductive layer via the pad, wherein the pad is directly on the at least one first plug structure, wherein a width of the pad is less than an upper width of the at least one first plug structure, and wherein a height of the at least one first plug structure is longer than a height of the second plug structure.