Patent ID: 8035214

Claim:
A package substrate comprising: a lower level interlayer resin insulating layer; a lower via hole formed in the lower level interlayer resin insulating layer; an outermost interlayer resin insulating layer formed over the lower level interlayer resin insulating layer; a pad structure formed on the outermost interlayer resin insulating layer; a solder resist formed on the outermost interlayer resin insulating layer and the pad structure, the solder resist having an opening exposing a partially exposed portion of the pad structure; a conductive connecting pin configured to establish an electrical connection with another substrate, the conductive connecting pin being secured to the partially exposed portion of the pad structure via a solder, the solder being disposed over at least one metal layer formed only in the partially exposed portion of the pad structure; and a via hole formed through the outermost interlayer resin insulating layer and configured to electrically connect the pad structure to at least one conductive circuit formed below the outermost interlayer resin insulating layer, the via hole being positioned directly below the pad structure and directly on the at least one conductive circuit, wherein the planar area of the pad structure is greater than the planar area of the conductive circuit.