Patent ID: 8368431

Claim:
A pulse edge selection circuit comprising: a first clock selection circuit adapted to select and output a first clock used to determine a rising edge of a pulse from among a plurality of clocks shifted in phase; a second clock selection circuit adapted to select and output a second clock used to determine a falling edge of the pulse from among the plurality of clocks; and an edge detection circuit adapted to generate the pulse using the first clock and the second clock, the edge detection circuit including a first input terminal which accepts input of the first clock from the first clock selection circuit, a second input terminal which accepts input of the second clock from the second clock selection circuit, and an output terminal which outputs the pulse, wherein each of the first clock selection circuit and the second clock selection circuit comprises an input stage to accept input of the plurality of clocks and select and pass one clock from among the plurality of clocks, and an output stage to output the selected and passed clock to the edge detection circuit, the edge detection circuit detects rising edges of the first clock and the second clock inputted to the first input terminal or the second input terminal from the first clock selection circuit and the second clock selection circuit and generates the pulse which rises on the rising edge of the first clock and falls on the rising edge of the second clock, and the output stage of each of the first clock selection circuit and the second clock selection circuit is a combination of a plurality of NOR gates having a plurality of input terminals and a plurality of NAND gates having a plurality of input terminals, the plurality of NOR gates and the plurality of NAND gates are interconnected such that an input of a NAND gate is connected to an output of a NOR gate and that the input of the NOR gate or an input of another NOR gate is connected to an output of another NAND gate, and a NAND gate is used as an output gate which outputs the first clock and the second clock.