Patent ID: 8120976

Claim:
A line defect detection circuit, comprising: a first driver disposed at one terminal end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, wherein the first driver includes a PMOS transistor in which the control signal is connected to a gate, the first voltage is connected to a source, and one end of the line is connected to a drain, and an NMOS transistor in which the control signal is connected to a gate, the second voltage is connected to the source, and one end of the line is connected to a drain; and a second driver disposed at the other terminal end of the line and configured to drive the line using a third voltage in response to a stress signal, wherein the second driver includes a PMOS transistor or an NMOS transistor in which the stress signal is connected to a gate, the third voltage is connected to the source, and the other end of the line is connected to a drain.