Patent ID: 7618864

Claim:
A method of forming a nonvolatile memory device, comprising: forming a device isolation layer in a substrate to define an active region in which a memory layer including a tunnel insulating layer, a charge storage layer, and a blocking insulating layer is formed; forming a first hard mask pattern exposing a portion of the memory layer on the substrate including the device isolation layer; etching a portion of the memory layer using the first hard mask pattern as an etching mask to expose the substrate; forming an insulating layer and a first conductive layer on the overall substrate and planarizing the first conductive layer and the insulating layer to expose the first hard mask pattern to form a middle gate having an upper surface higher than an upper surface of the memory layer and a gate insulating layer adjacent to both sides and a bottom of the middle gate in a space where the portion of the memory layer is removed; removing the first hard mask pattern; forming side gates adjacent to the gate insulating layer on both sides of the middle gate; patterning the memory layer using the side gates as an etching mask to form first and second memory cells each including the patterned memory layer and the side gates; and performing an ion implantation process to form a first impurity region on the substrate outside the first memory cell and to form a second impurity region on the substrate outside the second memory cell.