Patent ID: 7196543

Claim:
An integrated circuit, comprising: an interconnect structure; and a plurality of logic blocks coupled to the interconnect structure, each logic block comprising: a first input multiplexer circuit having a plurality of data input terminals coupled to the interconnect structure, an additional data input terminal, and an output terminal; a second input multiplexer circuit having a plurality of data input terminals coupled to the interconnect structure, an additional data input terminal, and an output terminal; a programmable logic circuit having a first input terminal coupled to the output terminal of the first input multiplexer circuit, a second input terminal coupled to the output terminal of the second input multiplexer circuit, and an output terminal coupled to the interconnect structure; and a fan multiplexer circuit having a plurality of data input terminals, and further having an output terminal coupled to the additional data input terminal of the first input multiplexer circuit and to the additional data input terminal of the second multiplexer circuit, the fan multiplexer circuit not directly driving any input terminal of the programmable logic circuit, and further not directly driving the interconnect structure.