Patent ID: 8243499

Claim:
A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory, said method comprising: storing data in a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory; and storing data in a resistance change element electrically connected to one of said first and second regions by configuring the resistance change element in one of a plurality of resistivity states, wherein each of said resistivity states corresponds to a different data value, respectively; wherein said capacitorless transistor and said resistance change element are included in a memory cell, said cell comprising said floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type; first and second regions at first and second locations of said cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; said first and second regions being located such that at least a portion of the floating body is located between said first and second locations; and a gate positioned between said first and second regions and adjacent said floating body region.