Patent ID: 8693681

Claim:
Programmable digital logic circuitry, comprising: program memory for storing a plurality of program instructions arranged in a sequence, the plurality of program instructions comprising a first program instruction corresponding to a function of a first and a second operand, the function returning a value corresponding to a data word having a first portion corresponding to a first portion of the first operand, and a second portion corresponding to the result of a sequence of operations comprising: performing a bit-wise AND function of the first portion of the first operand and a first portion of the second operand; then performing a one-bit left rotate of the result of the bit-wise AND function; and then performing a bit-wise exclusive-OR of the result of the one-bit left rotate and the second portion of the first operand; a register bank comprising register locations for storing the operands and the returned value; and a first logic circuit for executing the first program instruction upon the first and second operands stored in the register bank, wherein the first logic circuit comprises: a plurality of logic blocks, each of the logic blocks for executing the first program instruction upon a pair of operands stored in the register bank; wherein each of the first and second register locations of the register bank store a plurality of operands; and wherein, in executing the first program instruction, a plurality of operands from the first and second register locations of the register bank are applied to corresponding ones of the plurality of the logic blocks, so that the plurality of logic blocks each return a value corresponding to the result of the sequence of operations.