Patent ID: 8669162

Claim:
A method of manufacturing a semiconductor device, comprising: forming a plurality of semiconductor layers that are located at a distance from one another on a first insulating film by performing patterning on a silicon film placed on the first insulating film, each of the semiconductor layers including a first region, a second region that is formed at a distance from the first region in an extending direction of each of the semiconductor layers, and a third region provided between the first region and the second region; forming a gate insulating film that covers both side faces and an upper face of the third region of each of the semiconductor layers; forming a gate electrode that is a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a source region and a drain region in the first and second regions of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film, the portion being located above the gate electrode; siliciding the gate electrode; and forming a stress applying film that applies a stress to the third region of each of the semiconductor layers, the stress applying film being formed to cover the silicided gate electrode, the stress being applied in a direction that is perpendicular to the extending direction of each of the semiconductor layers and is parallel to an upper face of the first insulating film.