Patent ID: 7689189

Claim:
A low intermediate frequency receiver circuit, the circuit comprising: an amplifier having an input for receiving a radio frequency signal and an output for outputting the received signal; a local oscillator having a first output for providing a first clock signal corresponding to a first channel of the received signal and a second output for providing second clock signal corresponding to a second channel of the received signal; a quadrature mixer has an input coupled to the output of the amplifier, a first clock input coupled to the first output of the local oscillator, and a second clock input coupled to the second output of the local oscillator, such that the received signal is input to the quadrature mixer along with the first and second clock signals and, responsive thereto, the quadrature mixer outputs the first channel signal at a first output and the second channel signal at a second output; a pre-selectivity filter configured to filter at least an image signal and having a first resistive-capacitor network coupled to the first output of the quadrature mixer and a second resistive-capacitor network coupled to the second output of the quadrature mixer, where the first and second resistive-capacitor networks are coupled together through a first gyrator at the first and second outputs of the quadrature mixer to form a first gyrator resonator between the outputs of the quadrature mixer and the pre-selectivity filter, the pre-selectivity filter being configured to remove an image channel from the first and second channel signals; a first amplitude limiter circuit having an input coupled to the first output of the quadrature mixer and an output; a second amplitude limiter circuit having an input coupled to the second output of the quadrature mixer and an output; a selectivity filter circuit having a first input coupled to the output of the first amplitude limiter circuit and a second input coupled to the output of the second amplitude limiter circuit and first and second outputs; and a demodulator having a first input coupled to the first output of the selectivity filter circuit and a second input coupled to the second output of the selectivity filter circuit, and an output.