Patent ID: 7940244

Claim:
A driving circuit, comprising: a plurality of switches including N switch groups each of which includes a plurality of M switches, two switches of the plurality of M switches in each N switch group being adjacent to each other, the N being a natural number that is not less than 2, the M being a natural number that is not less than 2; a plurality of video signal lines transmitting a multiplexed to a degree of M of video signals to the plurality of switches of all of the N switch groups, one of the plurality of video signal lines electrically connecting to the plurality of M switches of a switch group; and a plurality of timing signals that control the plurality of switches of all of the N switch groups, N switch circuits corresponding to the timing signals being simultaneously driven, and n, n+M, . . . , n+(N−1)×Mth ones of signals for N pixels within the multiplexed video signal being output to the corresponding video signal line, the n being a natural number, and N of the plurality of switches outputting N output signals simultaneously, at least one switch of the plurality of switches except for the N of the plurality of switches being disposed between one of the N of the plurality of switches and another of the N of the plurality of switches.