Patent ID: 6996201

Claim:
A data receiving system comprising: a clock generating circuit for generating a clock whose frequency is synchronous with a frequency of a data transmission rate of a received data; a delay circuit for delaying said received data to generate a delayed data; a first sampling circuit for sampling said received data in response to at least one of leading and trailing edges of said clock and outputting a received data sampling value; a second sampling circuit for sampling said delayed data in response to at least one of leading and trailing edges of said clock and outputting a delayed data sampling value; and received data judging means for judging a received data value based on said received data sampling value and said delayed data sampling value, wherein said received data judging means comprises: first judging means for judging the received data value primarily based on either one of said received data sampling value and said delayed data sampling value; and second judging means for judging the received data value secondarily based on the other of said received data sampling value and said delayed data sampling value when said first judging means fails to judge the received data value, and said received data judging means judges the received data value with reference to same sampling values continuously appearing N times in a sampling operation, N being a natural number.