Patent ID: 7713828

Claim:
A method of forming a MOS transistor in an active region surrounded by an isolation film, the method comprising: forming a gate insulating film on a first part of the active region; forming a gate electrode on the gate insulating film; forming diffusion layers in second parts of the active region, the second parts being different from the first part; forming first silicon layers on the diffusion layers by selective epitaxial method to form source and drain regions which comprise stacks of the first silicon layers and the diffusion layers; forming an inter-layer insulator which covers the gate electrode and the source and drain regions; forming contact holes in the inter-layer insulator, the contact holes reaching the source and drain regions; forming second silicon layers in the contact holes, the second silicon layers contacting with the source and drain regions; wherein a second impurity is introduced into the second silicon layers, and the second impurity is diffused to the first silicon layer.