Patent ID: 8847326

Claim:
A semiconductor device comprising: a first transistor; an insulating layer over one of a source region and a drain region of the first transistor; and a second transistor including: a channel formation region over the insulating layer; a gate insulating layer over the channel formation region; and a gate electrode over the gate insulating layer, wherein a top surface of a gate electrode of the first transistor is in contact with a bottom surface of one of a source electrode and a drain electrode of the second transistor, wherein the gate insulating layer of the second transistor and the insulating layer satisfy a formula: t a t b · ɛ rb ɛ ra < 0.1 wherein t a represents a thickness of the gate insulating layer of the second transistor, t b represents a thickness of the insulating layer, ∈ ra represents a dielectric constant of the gate insulating layer of the second transistor, and ∈ rb represents a dielectric constant of the insulating layer.