Patent ID: 7759224

Claim:
A fabrication method of a semiconductor integrated circuit device comprising the steps of: (a) providing a semiconductor wafer having a first main surface and a second main surface which is opposite to said first main surface, said semiconductor wafer having a circuit pattern formed over said first main surface and a first thickness; (b) grinding said second main surface of said semiconductor wafer, thereby making said semiconductor wafer have a second thickness, which is thinner than said first thickness; (c) after the step (b), etching said second main surface of said semiconductor wafer to relieve stress of said second main surface of said semiconductor wafer caused by said grinding, (d) after the step (c), forcibly forming an oxidation film on said second main surface of said semiconductor wafer, so as to form a forcibly formed oxidation film; (e) after the step (d), adhering a dicing tape over said second main surface of said semiconductor wafer such that said dicing tape contacts with said forcibly formed oxidation film; (f) after the step (e), dicing said semiconductor wafer, thereby dividing said semiconductor wafer into individual chips; and (g) after the step (f), removing said individual chips from said dicing tape.