Patent ID: 8447888

Claim:
An apparatus comprising: receiving logic in a first device, the receiving logic configured to receive a first packet referencing a memory access operation on a serial, point-to-point interconnect, wherein the first packet is to include a reference to an address and a length field capable to hold a length to indicate a number of cache lines in a block, a stride field capable to hold a stride to indicate an offset to a start of a next block, and a block count field capable to hold a block count to indicate a number of blocks to prefetch; and fetch logic configured to: initate a fetch request of an element at the address in response to the receiving logic receiving the first packet and the first packet referencing the memory access operation and the address; and initiate a prefetch of an additional element in response to receiving the first packet based on one or more of the length field, the stride field, or the count field, wherein the first packet is associated with an access control hint comprising a locality hint and that is to be indicative of a location at which prefetched elements are to be cached.