Patent ID: 8284597

Claim:
An integrated circuit apparatus, comprising: a cross-point array including a plurality of bit lines and a plurality of word lines, intersections of the plurality of bit lines and the plurality of word lines including diode memory devices, the diode memory devices including: a diode including a first terminal electrically coupling a bit line of the plurality of bit lines and a second terminal electrically coupling a word line of the plurality of word lines; and a memory element between the first terminal and the second terminal of the diode, the memory element being bidirectionally switchable between a first memory state and a second memory state, wherein the diodes of the diode memory devices reduce current through unselected intersections of the intersections of the plurality of bit lines and the plurality of word lines; and control circuitry coupled to the cross-point array, the control circuitry applying bias arrangements to a selected intersection of the intersections of the plurality of bit lines and the plurality of word lines that bidirectionally switch the memory element of the diode memory device at the selected intersection.