Patent ID: 6944220

Claim:
A circuit configuration for offset compensation of a digital input signal having symbols, the circuit configuration comprising: a recursive digital filter being supplied with the digital input signal to be compensated, said recursive digital filter having at least a first time-variable filter coefficient and a second time-variable filter coefficient; said recursive digital filter including a register device outputting symbols of a digital intermediate signal; said recursive digital filter including a first multiplying device and a subtracting device, said first multiplying device multiplying the symbols of the digital input signal by the first time-variable filter coefficient to obtain a digital output signal having symbols, said subtracting device subtracting the symbols of the digital intermediate signal from the symbols of the digital output signal of said first multiplying device to obtain symbols of an offset-compensated digital output signal; said recursive digital filter including a second multiplying device and an adding device, said second multiplying device multiplying the symbols of the digital intermediate signal by the second time-variable filter coefficient to obtain a digital output signal having symbols, said adding device adding the symbols of the digital output signal of said second multiplying device to the symbols of the digital input signal to generate a digital output having symbols; and said register device receiving the symbols of the digital output signal of said adding device.