Patent ID: 8105909

Claim:
A method of fabricating a non-volatile memory device, comprising: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a zirconium-rich zirconium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a zirconium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the zirconium-rich hafnium silicon oxide layer; forming a silicon-rich zirconium silicon oxide layer over the zirconium-rich zirconium silicon oxynitride layer; forming a silicon-rich zirconium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich zirconium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich zirconium silicon oxynitride layer.