Patent ID: 8426253

Claim:
A method for manufacturing an integrated circuit device, the method comprising: arranging an electrically-conductive structure to facilitate electrical communication between a die and a first lead and a second lead, the electrically-conductive structure, the die, and the first and second leads forming a sub-assembly, wherein said die has two opposing surfaces, wherein one side of said die faces said electrically-conductive structure and the other side of said die contacts said first lead, and wherein said second lead makes direct contact with said first lead and also with a same side of said electrically-conductive structure as said die faces; providing an electrically-conductive housing having an interior surface and an exterior surface, the interior surface defining a cavity; dispensing a potting material into the cavity, the potting material having the electrically conductive structure, the die, the first lead and at least part of the second lead embedded therein, wherein said die rests on said electrically-conductive structure embedded in said potting material, wherein said electrically-conductive housing encases only the potting material, together with the electrically conductive structure, the die, the first lead and at least part of the second lead embedded therein, and is arranged to form exterior packaging of the integrated circuit device; and disposing the sub-assembly in the cavity in such a manner that space exists between the sub-assembly and the interior surface, the space occupied by the potting material, wherein heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.