Patent ID: 8649222

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array which includes a plurality of memory cells; word lines electrically connected to the memory cells; a controller configured to perform a write operation, the write operation including a first program operation, a second program operation, a third program operation, a fourth program operation, and a first verify operation, the controller configured to perform the first program operation on a condition a first voltage is applied to a selected word line, the controller configured to perform the second program operation on a condition a second voltage is applied to the selected word line after the first program operation, the second voltage being lower than the first voltage, the controller configured to perform the first verify operation on a condition a third voltage is applied to a selected word line after the second program operation, the controller configured to perform the third program operation on a condition a fourth voltage is applied to the selected word line after the first verify operation, the fourth voltage being higher than the first voltage, the controller configured to perform the fourth program operation on a condition a fifth voltage is applied to the selected word line after the third program operation, the fifth voltage being higher than the second voltage and lower than the fourth voltage.