Patent ID: 8599853

Claim:
A system for processing packets, comprising: a processor, a memory comprising a plurality of lookup tables (LUTs) and programmed instructions, wherein the processor is configured to execute the programmed instructions stored in the memory comprising: extracting K bits from an N-bit wide address of an incoming information packet; using a key to identify an entry of one of the LUTs, wherein the entry includes a pointer and the key in a first iteration includes the extracted K bits and Q bits of the (N−K) bits not extracted; determining whether the pointer is empty; returning an indication that no match was found, when it is determined that the pointer is empty; determining whether all of the (N−K) bits not extracted have been used, when it is determined that the pointer is not empty; returning the pointer, when it is determined that all of the (N−K) bits not extracted have been used, the returned pointer indicative of an exact match for the address; and repeating the using, determining, and returning steps in a pipelined manner, when it is determined that all of the (N−K) bits not extracted have not been used, wherein the key used in each subsequent iteration includes a value obtained from the pointer included in the entry identified in a previous iteration and Q bits of the (N−K) bits not extracted and not previously used.