Patent ID: 8078999

Claim:
A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising: an apparatus for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to both the first register in the second pipeline stage; wherein the design structure comprises a netlist describing the apparatus for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design.