Patent ID: 8924680

Claim:
A memory controller supporting at least two different operation modes, including a first mode in which a first memory is used for memory access, the first memory having first and second sections of memory cells, and a second mode in which the first memory and a second memory are used for memory access, the memory controller comprising: a register operable to indicate mode; and circuitry operable to direct first memory transaction requests over a first request port to the first memory, irrespective of mode, and to direct second memory transaction requests over a second request port to (i) the first memory when the register indicates the first mode, and (ii) the second memory if present when the register indicates the second mode, in a manner such that processing of the first and second memory transaction requests by the respective memories overlaps in time; where the memory controller is operable to program the first memory to, in the first mode, service the first and second memory transaction requests using the respective first and second sections of memory cells, and in the second mode to service the first memory transaction requests using an addressed one of the first and second sections of memory cells.