Patent ID: 8560990

Claim:
A method of designing an integrated circuit, comprising: modifying a design-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit; and synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit, wherein: the modifying the design-variable EM limit includes, at design start, calculating a maximum output slew or output capacitance; and the modifying the design-variable EM limit is calculated by: MTTF=A ( J−n ) e Ea/kT where, A=Constant; J=Current Density; Ea=Energy Activation; K=Boltzmans Constant; and T=temperature in Kelvin wherein at least the step of the synthesizing the integrated circuit is performed by a processor.