Patent ID: 7872514

Claim:
A latch circuit comprising: a D-type latch with a latch clock input, a data input and a corresponding data output, the D-tvpe latch containing an SR latch and a single pole double throw switch. the single pole double throw switch forming a difference detector, the difference detector having a difference output at a node common to the latch clock input and that provides a difference signal when data at the data input is different than data at the corresponding data output; and a gate or edge triggered gate having a gate clock input to which a clock signal is supplied, an output coupled to the latch clock input and gate control input coupled to the difference output of the difference detector, wherein either: the latch circuit contains the gate and when the difference signal is provided to the gate control input the gate allows a clock signal supplied at the gate clock input to determine logic values supplied to the latch clock input, thereby resulting in the data at the data input being transferred to the data output, and wherein only after the data at the data input is transferred to the corresponding data output will the gate disallow the clock signal from determining the logic values supplied to the latch clock input or the latch circuit contains the edge triggered gate and only when both a transition of the clock signal supplied at the gate clock input is detected by the edge triggered gate and the difference signal is provided to the gate control input will the edge triggered, gate allow an edge of a clock signal supplied at the gate clock input to determine logic values supplied to the latch clock input, as a result, the data at the data input is transferred to the data output.