Patent ID: 8453073

Claim:
A method of generating a mask for fabrication of a physical layer of an integrated circuit, wherein said integrated circuit comprises multiple physical layers, the method comprising the steps of: receiving an input definition of said integrated circuit comprising multiple design layers, each design layer of said multiple design layers representing a designed layout of one of said multiple physical layers, wherein said multiple design layers comprise a programmable subcomponent configuration layer, said programmable subcomponent configuration layer representing a set of physical structures in a selected physical layer of said integrated circuit, wherein a position of each physical structure of said set of physical structures determines which of a plurality of logical configurations a programmable subcomponent of said integrated circuit will have; performing a mask generation procedure on a selected design layer of said multiple design layers, said mask generation procedure comprising transforming said selected design layer into said mask for fabrication of said physical layer of said integrated circuit; and performing a mask modification procedure on said mask, said mask modification procedure comprising amending said mask to ensure that said physical layer of said integrated circuit will be reliably fabricated when using said mask, wherein said input definition of said integrated circuit further comprises a non-functional design layer, wherein said non-functional design layer does not represent one of said multiple physical layers, and wherein said non-functional design layer represents further possible positions for said set of physical structures in said selected physical layer, said further possible positions not being represented in said programmable subcomponent configuration layer, and wherein said mask modification procedure comprises treating said non-functional design layer as said programmable subcomponent configuration layer.