Patent ID: 7026685

Claim:
A semiconductor device having a non-volatile memory transistor, comprising: a semiconductor layer; a floating gate disposed over the semiconductor layer through a first dielectric layer as a gate dielectric layer; a second dielectric layer that contacts at least a part of the floating gate and is capable of functioning as a tunneling dielectric layer; a control gate formed over the second dielectric layer; and an impurity diffusion layer that forms a source region or a drain region formed in the semiconductor layer, wherein a plurality of conduction layers are formed at different levels above the floating gate, and the floating gate is entirely overlapped by the plurality of conduction layers as viewed in a plan view; and wherein at least one of the conduction layers outwardly protrudes from an end of the floating gate as viewed in a plan view, and a width of a portion of the conduction layer that outwardly protrudes from the end of the floating gate as viewed in a plan view is 0.5 μm or smaller.