Patent ID: 7015105

Claim:
A method for simultaneously fabricating a pair of insulated gate transistors comprising a first transistor having a thicker gate oxide layer than a second transistor, for each of the first and the second transistor in the pair of insulated gate transistors, the method comprising: forming at least one gate oxide layer; forming at least one gate flanked by one or more insulative lateral regions; forming at least one high-doped drain; forming one or more source regions; forming at least one low-doped source area and a drain area extending under the insulative lateral regions between the high-doped drain and the one or more source regions; wherein the step of forming at least one low-doped source area and a drain area for a second transistor includes forming at least one low-doped source area and a drain area by implanting a first dopant having a first concentration and implanting a second dopant having a second concentration lower than the first concentration; wherein the step of forming at least one low-doped source area and a drain area for a first transistor includes forming a low-doped source and a drain by implanting the second dopant and by not implanting the first dopant; and wherein the step of forming at least one gate flanked by one or more insulative regions includes implanting the first dopant on either side of the gate of the second transistor prior to forming the insulative lateral regions, and whereby an active area of the first transistor is protected by a layer of resin.