Patent ID: 7614020

Claim:
A structurally reconfigurable semiconductor circuit device for in-memory processing of stateful, transaction-oriented applications, comprising: a multiple level array of memory storage cells and logic circuits, the storage cells having multiple configurable access paths, the storage cells capable of being simultaneously accessed for being read from and written into; a plurality of configurable, packetized interface ports capable of receiving data packets, the packetized interface ports having access to the multiple level array; a plurality of configurable commute elements distributed within the multiple level array, each of the plurality of configurable commute element configured to move data within the multiple level array of storage cells through one of the multiple configurable access paths; a plurality of configurable Compute elements within the multiple level array, each of the plurality of configurable Compute elements configured to transform data within a portion of the multiple level array of storage cells via the multiple configurable access paths; and a pool of redundant features for repairing a defective feature within the multiple level array, wherein levels of the multiple level array associated with a higher defect density have more redundant features available for repair relative to levels associated with a lower defect density.