Patent ID: 8906765

Claim:
A method of making a non-volatile double-gate memory cell comprising a control transistor comprising a gate and a memory transistor comprising a control gate adjacent to the gate of the control transistor, wherein the method comprises the steps of: forming at least partly the gate of the control transistor, comprising obtaining a relief of a semiconductor material on a substrate; forming the control gate of the memory transistor, comprising a step of depositing a layer of a semiconductor material so as to cover at least the relief of the gate of the control transistor; wherein said forming of the control gate of the memory transistor additionally comprises the following steps: depositing, on the layer of semiconductor material, another layer having a thickness such that the upper face of said other layer is situated at all points above the relief of the gate of the control transistor; chemical mechanical polishing (CMP) performed so as to strip, above the relief of the gate of the control transistor, said other layer and part of the layer of a semiconductor material; stripping of the remaining said other layer on both sides of the relief of the gate of the control transistor, etching of the layer of a semiconductor material so as to strip this material above the relief of the gate of the control transistor and to leave only a pattern on at least one sidewall of the relief of the gate of the control transistor.