Patent ID: 7910430

Claim:
A method of manufacturing a NAND flash memory device having a plurality of memory cells connected in series between a drain select transistor and a source select transistor, the method comprising: forming isolation films, which define an active region, on a semiconductor substrate; forming at least one recess in the active region between the isolation films for a recessed gate of at least one of the source select transistor or the drain select transistor; forming a tunnel oxide film in the at least one recess and over the semiconductor substrate at locations of gates of the plurality of memory cells, wherein the tunnel oxide film formed in the at least one recess extends below the tunnel oxide film formed in the locations of gates of the plurality of memory cells; forming at least one floating gate over the tunnel oxide film and within the at least one recess for at least one of the drain select transistor or the source select transistor; forming a dielectric film over the at least one floating gate; and forming at least one control gate over the dielectric film for at least one of the drain select transistor or the source select transistor.