Patent ID: 7425850

Claim:
A quadrature divider, comprising a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, wherein the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,Ī, two differential outputs O,Ō and two differential clock inputs C, C , the outputs O,Ō of one flip-flop are connected to the corresponding inputs I,Ī of a subsequent flip-flop, the outputs O,Ō of the endmost flip-flop are connected inversely to the inputs I,Ī of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, C with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_ 0 , In_ 90 , In_ 180 , and In_ 270 , wherein the quadrature divider is an even number divide-by-n circuit comprising a number of 2n flip-flops and providing a number of 4n output signals having 4n equidistant phases.