Patent ID: 8010754

Claim:
A memory controller comprising: a first control component to break a first channel of a random access memory (RAM) device into first and second independently addressable subchannels, including: first assignment logic to receive a first request and a second request to access memory locations in the first channel of the RAM device; and a first transaction assembler to construct memory requests by combining the first request with one or more additional requests to access the first independently addressable subchannel within the first-channel and combining the second request with one or more additional requests to access the second independently addressable subchannel within the first channel; and a second control component to break a second channel of the RAM device into first and second independently addressable subchannels, including: second assignment logic to receive a third request and a fourth request to access memory locations in the second channel of the RAM device; and a second transaction assembler to construct memory requests by combining the third request with one or more additional requests to access the second independently addressable subchannel within the second channel and combining the fourth request with one or more additional requests to access the second independently addressable subchannel within the second channel; and a memory control component, coupled to the RAM device including a first memory controller including a first micro-tiling component to break a first channel couple into S independently addressable subchannels that are N=M/S bytes wide.