Patent ID: 8278764

Claim:
A microelectronic package, comprising: a substrate having first and second opposed surfaces and first, second, and third apertures extending between the first and second surfaces, the apertures having first, second, and third axes extending in directions of the lengths of the respective apertures, the first and second axes being parallel to one another, the third axis being transverse to the first and second axes, the second surface having a central region disposed between the first and second axes; first, second, and third microelectronic elements each having a surface facing the first surface of the substrate and a plurality of contacts at the surface of the respective microelectronic element aligned with at least one of the apertures, each microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function; a plurality of terminals exposed at the second surface in the central region thereof, the terminals configured for connecting the microelectronic package to at least one component external to the package; and leads electrically connected between the contacts of each microelectronic element and the terminals, each lead having a portion aligned with at least one of the apertures, wherein the terminals are configured to carry sufficient address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the first, second or third microelectronic elements.