Patent ID: 7405573

Claim:
A semiconductor device test apparatus to perform a high voltage test of a device under test (DUT), comprising: a plurality of source measurement units (SMUs); a plurality of SMU connectors, each SMU connector electrically connected to a corresponding separate one of the plurality of SMUs; a tester housing partially enclosing the plurality of SMUs and the plurality of SMU connectors; and a test fixture, the test fixture configured to be connected to the tester housing such that, in a closed state, the test fixture and the tester housing completely enclose the plurality of SMUs and the plurality of SMU connectors, wherein the test fixture includes a socket configured to receive pins of the DUT, a plurality of test fixture connectors, each test fixture connector corresponding to a separate pin of the DUT and configured to, via the socket and when connected by a cable to a corresponding separate one of the plurality of SMU connectors, provide a forcing signal from that test fixture connector to that separate pin of the DUT, receive a sensing signal from that separate pin of the DUT at that test fixture connector, and maintain a guard signal at that separate pin of the DUT at a same electrical potential as the forcing signal.