Patent ID: 8514855

Claim:
An extensible processing pipeline, comprising: a plurality of processing engines each including a function engine and a marking engine to process packets associated with packet flows, wherein for a given processing engine the function engine is coupled to perform a processing function on a given packet flow and the marking engine is coupled to mark at least one packet of the given packet flow to indicate to other processing engines that the given packet flow is claimed by the given processing engine for processing by the function engine of the given processing engine; a flow through data bus coupling the processing engines in series such that the packets are received on the flow through data bus and flow sequentially through each of the processing engines over the flow through data bus; and an arbitered data bus linking the processing engines for outputting processed packets after the packets are processed by the function engines, wherein the flow through data bus is coupled to sequentially communicate each of the packets that are unprocessed by the function engines to all of the processing engines but is not coupled to communicate processed results generated by the function engines, wherein the marking engines are coupled to selectively mark the packets that are unprocessed by the function engines and transmitted along the flow through data bus.