Patent ID: 6891407

Claim:
An analog signal level detecting apparatus comprising: a first voltage comparator for comparing an input signal with a reference voltage; a rectifying circuit for rectifying said input signal; a second voltage comparator for comparing an output signal of said rectifying circuit with a threshold voltage specified previously arbitrarily; an up/down counting circuit, to which a clock for an up-count operation and a clock for a down-count operation are independently provided, for selectively performing an up-count operation or a down-count operation according to an output signal of said second voltage comparator; a first latch circuit for retaining a count value of said up/down counting circuit; a timing pulse generating circuit for generating a timing pulse, which determines reset timing of said up/down counting circuit and retaining timing of said first latch circuit, based on an output signal of said first voltage comparator; a digital-analog converting circuit for converting an output signal of said first latch circuit into a direct-current voltage.