Patent ID: 7852608

Claim:
A semiconductor device, comprising: a first circuit block provided between a first power supply line and a second power supply line, a first power supply voltage supplied from the first power supply line being higher than a second power supply voltage supplied from the second power supply line; and a second circuit block provided between the second power supply line and a third power supply line, a third power supply voltage supplied from the third power supply line being different from the first power supply voltage, wherein the second circuit block includes: a second clamp circuit to clamp an overvoltage by forming an electric current path between the second power supply line and the third power supply line; and a circuit provided between the second power supply voltage line and the third power supply voltage line, wherein the first circuit block includes: a first clamp circuit to clamp the overvoltage by forming an electric current path between the first power supply line and the second power supply line; and a first protection circuit that is located on a signal line through which a predetermined signal is sent from the first power supply line to the circuit in the second circuit block, wherein the first protection circuit includes a buffer circuit, an input of which being coupled to the first power supply line.