Patent ID: 7790561

Claim:
A method for manufacturing an integrated circuit (IC), the method comprising: forming a gate oxide layer over at least a portion of a substrate; forming a gate electrode over the gate oxide layer; implanting a dopant into the substrate to form a first region and a second region that are separated from one another by a channel region, wherein the gate oxide layer and gate electrode are located between the first and second regions over at least a portion of the channel region; depositing a nitride film by plasma enhanced chemical vapor deposition (PECVD) over the first region, the second region, and the gate electrode, wherein the nitride film has at least 20 atomic percent of hydrogen, and wherein the nitride film is deposited under tensile stress; etching the nitride film to from spacers over the substrate that are substantially adjacent to the gate electrode; and annealing the IC to at least transfer the tensile stress and at least a portion of hydrogen to the channel region.