Patent ID: 8461003

Claim:
A method for fabricating a three dimensional (3D) nonvolatile memory device, comprising: forming a buried insulation layer over a substrate; forming a sub-channel on the buried insulation layer; forming an insulation layer on the buried insulation layer to electrically isolate the sub-channel from an adjacent sub-channel: forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers; selectively etching the stacked layer to form a first open region exposing the sub-channel; forming a main-channel conductive layer to gap-fill the first open region; selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels; and forming an isolation layer to gap-fill the second open region, wherein the sub-channel and the plurality of main channels form a U-shaped channel.