Patent ID: 8026549

Claim:
A semiconductor device, comprising: a deep N-well region, configured in a substrate; a P-well region, surrounding a periphery of the deep N-well region; a gate structure, disposed on the substrate of the deep N-well region, wherein the gate structure comprises a gate and a gate dielectric layer; a second N-type doped region, configured in the deep N-well region at one side of the gate structure; a first isolation structure, disposed between the gate dielectric layer and the second N-type doped region; an N-type isolation ring, configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than a doping concentration of the deep N-well region; a P-body region, configured in the deep N-well region at one side of the gate structure and between the gate structure and the N-type isolation ring; a first N-type doped region, configured in the P-body region; and an N-type lightly doped region, configured between the gate structure and the first N-type doped region.