Patent ID: 8804892

Claim:
Referenceless clock and data recovery circuitry, comprising: a first timing loop including: an oscillator to produce a plurality of first clock signals having the same frequency but differing phases in accordance with a frequency control signal; phase interpolation circuitry to receive the first clock signals and produce an output clock signal based on the first clock signals and a phase control signal; a transition density detector, coupled to the output clock signal and a data input signal, to produce a transition density signal indicative of the transition density of the data input signal relative to a frequency of the output clock signal; a frequency comparator coupled to the first clock signal and the output clock signal to produce a frequency comparison signal indicative of the relative frequencies of the first clock signals and the output clock signal; and a controller to generate the frequency control signal based on the transition density signal and the frequency comparison signal; and a second timing loop including: the phase interpolation circuitry; a phase detector to receive a data input signal and the output clock signal and to produce a phase detection signal; and a loop filter configured to produce the phase control signal by filtering the phase detection signal.