Patent ID: 7982297

Claim:
A semiconductor package comprising: a substrate including: opposed top and bottom substrate surfaces and a substrate side surface which extends between the top and bottom substrate surfaces; a conductive circuit pattern disposed on the top substrate surface; and a plurality of conductive contacts disposed on the bottom substrate surface, each of the contacts being electrically connected to the circuit pattern; at least one semiconductor die defining opposed top and bottom surfaces, the semiconductor die being electrically connected to the circuit pattern of the substrate by conductive wires; and a package body comprising separate first and second package body sections which at least partially encapsulate the semiconductor die, the conductive wires and the substrate such that at least a portion of the top surface of the semiconductor die is not covered by the first and second package body sections, and the conductive wires are covered thereby, the first and second package body sections each having a first surface which extends to the top surface of the semiconductor die, a third surface which extends to the top substrate surface of the substrate and is disposed inward of the substrate side surface, and a second surface which extends between the first and third surfaces, the top surface of the semiconductor die and the first surfaces of the first and second package body sections collectively defining a recess which is of a prescribed depth.