Patent ID: 8389383

Claim:
A method of patterning multiple regions of a semiconductor base, comprising: forming first masking features over a first of the regions, and forming second masking features over a second of the regions; forming a liner along and between the first and second masking features; forming a protective mask over the lined second masking features, while leaving the first masking features exposed; the protective mask having lateral edges; forming first spacers along sidewall edges of the first masking features, and forming second spacers along the lateral edges of the protective mask; removing the protective mask and the first masking features while leaving the lined second masking features remaining over the second region, while leaving the first spacers remaining over the first region, and while leaving the second spacers remaining over the semiconductor base; the first spacers being third masking features that are at a tighter pitch than the first masking features; and transferring patterns of the second masking features and the third masking features into one or more materials of the semiconductor base to pattern said one or more materials.