Patent ID: 7519886

Claim:
A self-test system integrated on an Application Specific Integrated Chip (ASIC), the ASIC including a primary functional logic for performing a particular application, the self-test system comprising: at least one primary interface operating in the particular application; an input interface protocol generator for generating patterns to be inserted into the at least one primary interface, the at least one primary interface generating a response resulting from the execution of the inserted patterns; an output interface protocol payload checker for determining whether the response is correct by comparing the response to an expected result; a control unit (a) for maintaining coherency between traffic of the at least one primary interface and the primary functional logic, (b) for selecting at least one of the patterns to be inserted, and (c) for controlling duration of operation of the self-test system; a user-interface for receiving a test configuration for operating the control unit and for receiving user-direction for operating the self-test system; and a signature unit for monitoring and reducing the traffic of the at least one primary interface and for generating a signature, wherein the input interface protocol generator generates the patterns at random or prescribed time intervals.