Patent ID: 7865733

Claim:
A secure processor having a core to execute an instruction code, comprising: a key memory unit configured to store a specific key in the core; an instruction code memory unit configured to store the encrypted instruction code in a non-rewritable format; an authentication processing unit configured to decrypt an electronic signature corresponding to authentication information added to a target instruction code containing the instruction code stored in the instruction code memory unit, by using an authentication key generated with the specific key, and to authenticate the target instruction code when an obtained decryption result matches a result of an operation performed on the target instruction code; and an encryption processing unit configured to encrypt the data input and output between the core and the outside, wherein the secure processor comprises as the core: a secure core configured to execute an instruction code which has been authenticated by the authentication processing unit; and a normal core configured to execute a regular instruction code which has not been authenticated by the authentication processing unit, and further comprises a normal core boot unit configured to boot the normal core after the secure core is booted using the encrypted instruction code which is stored in the instruction code memory unit.