Patent ID: 8638145

Claim:
A delay locked loop, comprising: a delay line configured to receive a clock input signal based on a reference clock and to output a delay edge signal according to a control signal adjustment; an injector configured to receive a rise edge of the reference clock and, in response to a trigger, send a single rise edge of the clock input signal to the delay line and generate a rise edge of a reference edge signal delayed by a predetermined unit of the reference clock period; a synchronizer configured to determine that the rise edge has passed through the delay line, and in response, send the injector a second trigger to send a next single fall edge of the clock input signal to the delay line; and a charge pump configured to calculate a timing difference by comparing a timing of a rise edge from the delay edge signal to a timing of a rise edge of the reference edge signal, and to send the control signal to the delay line to decrease or increase a delay setting of the delay line based on the timing difference.