Patent ID: 8000142

Claim:
A NAND flash memory device comprising: a NAND flash memory comprising a first retention region comprising one or more first memory cells, the one or more first memory cells configured to store data for a first amount of time based at least in part on a number of write cycles applied to the first retention region, and a second retention region comprising one or more second memory cells, the one or more second memory cells configured to store data for a second amount of time, the second amount of time being greater than the first amount of time; and a memory controller configured to periodically read data from the one or more first memory cells and rewrite the read data to the same one or more first memory cells as a refresh operation, wherein the memory controller is further configured to relocate data stored in the one or more first memory cells of the first retention region to the one or more second memory cells of the second retention region based at least in part on a refresh period between refresh operations, the refresh period being a predetermined amount of time that is based at least in part on the number of write cycles applied to the first retention region.