Patent ID: 8486752

Claim:
A method for manufacturing a phase change memory device, comprising the steps of: forming an interlayer dielectric applying a tensile stress on a semiconductor substrate, the semiconductor substrate having an impurity region; patterning predetermined portions of the interlayer dielectric to define contact holes exposing the impurity region; forming sidewall spacers on sidewalls of the contact holes, wherein the sidewall spacers are formed as a dielectric layer applying compressive stress; forming switching elements in the contact holes; after the step of forming the switching elements, forming an upper interlayer dielectric and heater electrodes on the interlayer dielectric; forming phase change patterns on the upper interlayer dielectric, the phase change patterns electrically connected to the heater electrodes; and forming top electrodes on the phase change patterns, wherein the interlayer dielectric is formed to apply the tensile stress to the semiconductor substrate, and the side wall spacers are formed as a dielectric layer applying the compressive stress to the semiconductor substrate.