Patent ID: 8742804

Claim:
A divider circuit comprising: a flip-flop circuit including: a first input portion configured to be supplied with a clock signal; a first output portion configured to supply a first output signal; a second output portion configured to supply an inversion signal of the first output signal; a second input portion electrically connected to the second output portion; a first transistor comprising a source and a drain, wherein one of the source and the drain is electrically connected to the second input portion, and wherein a gate of the first transistor is configured to be supplied with an inversion signal of the clock signal; a second transistor having a gate electrically connected to the other of the source and the drain of the first transistor; a third transistor having a gate electrically connected to the first input portion; a fourth transistor having a gate electrically connected to one of a source and a drain of the third transistor, wherein a channel formation region of the first transistor comprises an oxide semiconductor including indium, and wherein a channel formation region of the third transistor comprises an oxide semiconductor including indium.