Patent ID: 7492038

Claim:
A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip which is mounted on the first semiconductor chip; a first electrode group which is located on the first semiconductor chip so as to be arranged along an outer periphery of the second semiconductor chip; a second electrode group which is located on the first semiconductor chip so as to be arranged along an outer periphery of the first semiconductor chip, wherein the second electrode group surrounds the first electrode group; a third electrode group which is located on the second semiconductor chip; a plurality of first wires for electrically connecting the first electrode group and the third electrode group to each other; external connection terminals which are located around the first semiconductor chip; and a plurality of second wires for electrically connecting the second electrode group and the external connection terminals, wherein the first semiconductor chip has a first circuit element area on which the second semiconductor chip is mounted and a second circuit element area which is positioned between the first electrode group and the second electrode group, and wherein the second semiconductor chip includes a memory circuit and the second circuit element area includes a logic circuit which are susceptible to influence of noise caused outside the the logic circuit controlling the memory circuit.