Patent ID: 7030930

Claim:
A system comprising: a data processor having an I/O buffer; a memory having an I/O buffer coupled to the I/O buffer of the data processor, the memory storing code to control said data processor to: determine a delay amount, wherein the delay is associated with a difference between an amount of time to process a portion of video data to amount of time to process a portion of audio data associated with the video data; assert a transfer of processed audio data to memory through a data port; assert, after waiting the delay amount, a transfer of a representation of the processed audio data from memory to an audio output through a data port; a video processor to process the portion of video data to generate processed video data; an audio processor to process the portion of audio data to generate processed audio data; a memory controller comprising: a first register portion to enable a transfer of the processed audio data to memory; and a second register portion to enable a transfer of the representation of the processed audio data from memory to an audio output.