Patent ID: 8451971

Claim:
A clock generation circuit for a transmitter, wherein the transmitter transmits data according to an output clock signal comprising: a phase locked loop (PLL) arranged to receive a first clock signal and generate the output clock signal, wherein the PLL adjusts the frequency of the output clock signal according to a control signal; and a calibrator arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration; wherein the calibrator comprises: a frequency detector arranged to receive the output clock signal and the second clock signal, determine which one of frequencies of the output clock and second clock signals is higher, and generate a first detection signal and a second detection signal according to the determined result; and a calculation unit arranged to receive the first and second detection signals and perform subtraction calculation to the first and second detection signals to generate a calculation signal; wherein the control signal is generated according to the calculation signal.