Patent ID: 8122077

Claim:
A design verification system for a floating point computation unit, comprising a processor adapted to execute: a generator that receives a definition of a floating point operation to test, said definition comprising a first floating point operand having a first floating point input interval and a second floating point operand having a second floating point input interval, and a floating point result having a floating point output interval, said first and second floating point input intervals and said floating point output interval having respective upper and lower floating point limits, said generator operative to perform the steps of: defining a first reduced interval for said first floating point operand responsively to said upper and lower floating point limits of said second floating point input interval and said floating point output interval; selecting a first machine number in said first floating point input interval; defining a second reduced interval for said second floating point operand responsively to said first machine number and to said upper and lower limits of said floating point output interval; selecting a second machine number in said second reduced interval; and an execution engine for executing said floating point operation to test said floating point computation unit using said first machine number and said second machine number as said first floating point operand and said second floating point operand.