Patent ID: 7545653

Claim:
A semiconductor integrated circuit device, comprising: a digital circuit and an analog circuit that are formed on one semiconductor substrate and supplied with a power-supply voltage from the same power supply; a guard band formed on the semiconductor substrate in a position between the digital circuit and the analog circuit and configured to prevent noise generated in the digital circuit from being transmitted to the analog circuit; a first power supply terminal positioned on a periphery of the semiconductor substrate near the analog circuit and configured to supply the power-supply voltage to the analog circuit; a first ground terminal positioned on the periphery of the semiconductor substrate near the analog circuit and configured to supply a ground potential to the analog circuit; a second power supply terminal positioned on the periphery of the semiconductor substrate near the digital circuit and configured to supply the power-supply voltage to the digital circuit; a second ground terminal positioned on the periphery of the semiconductor substrate near the digital circuit and configured to supply the ground potential to the digital circuit; and a filter circuit positioned between the second power supply terminal, the second ground terminal, and the digital circuit and configured to remove the noise transmitted from the digital circuit, the filter circuit being provided separately from the guard band and including a first wiring pattern having a bent shape or a spiral shape and connecting the second power supply terminal and the digital circuit, a second wiring having a bent shape or a spiral shape and connecting the second ground terminal and the digital circuit, a first conductive pattern shaped like a flat rectangular plate and connected via through holes to the first wiring pattern, and a second conductive pattern shaped like a flat rectangular plate and connected via through holes to the second wiring pattern, wherein the first conductive pattern and the second conductive pattern are stacked and an insulating layer is provided between them.