Patent ID: 8048722

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring substrate having an upper surface, a plurality of bonding electrodes formed on the upper surface, a lower surface opposite to the upper surface, a plurality of land portions formed on the lower surface, a plurality of holes formed between the upper surface and the lower surface, a plurality of hole wirings formed inside of the holes, respectively, a common wiring formed inside of the holes in a plan view, a plurality of first lead-out wirings connected with the hole wirings, respectively, and extending from each of the hole wirings toward the common wiring, and a plating layer formed on each of the bonding electrodes; (b) after the step (a), mounting a semiconductor chip, having a plurality of pads, over the upper surface of the wiring substrate; (c) after the step (b), electrically connecting the pads of the semiconductor chip with the bonding electrodes of the wiring substrate via a plurality of conductive materials, respectively; and (d) after the step (c), sealing the semiconductor chip with resin, wherein after providing the plating layer, and before the step (b), each of the first lead-out wirings is electrically separated from the common wiring.