Patent ID: 6937076

Claim:
A clock signal generator for generating an output clock signal synchronized with an input clock signal having an input clock frequency, comprising: an input delay having an input to which the input clock signal is applied and further having an output at which a buffered clock signal is provided; a variable delay circuit having an input coupled to the output of the input delay and having an output at which a delayed clock signal is provided, the variable delay circuit further having a frequency controlled adjustable delay circuit to provide a first time delay based on the frequency of the buffered clock signal and further having a phase controlled adjustable delay circuit to provide a second time delay based on the phase difference between the buffered clock signal and a feedback clock signal, the feedback clock signal delayed with respect to the delayed clock signal by a model time delay, the frequency controlled adjustable delay circuit including a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency detector generating the frequency reference signal indicative of the input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and an adjustable delay circuit having a control terminal coupled to the output of the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be provided as the first time delay; and an output delay having an input coupled to the output of the variable delay circuit and an output at which the output clock signal is provided.