Patent ID: 7332938

Claim:
A domino logic circuit comprising: a dynamic node; an output inverter for inverting an output of the dynamic node; a precharge transistor for charging the dynamic node; a logic network coupled to the dynamic node for discharging the dynamic node in accordance with logic; a footer transistor for enabling and disabling the logic network; a keeper transistor coupled to the dynamic node for retaining a charge state of the dynamic node while awaiting the logic network to operate in accordance with the logic; a test transistor coupled to the dynamic node and having a test enable signal as an input and configured to not conduct for a normal mode and to conduct for a test mode based on the test enable signal, wherein the test transistor, the keeper transistor, and the output inverter form a write latch in the test mode when the test transistor conducts; and a multiplexer having the test enable signal, a clock signal, and a wait signal as other inputs and configured to: enable the normal mode and the test mode for the footer transistor; enable a precharge phase for the normal mode in which the precharge transistor charges the dynamic node and an evaluation phase for the normal mode in which the logic network operates on the dynamic node, the precharge phase and the evaluation phase determined by states of the test enable signal and the clock signal; and enable selection of another precharge phase for the test mode in which the precharge transistor charges the dynamic node, a write phase for the test mode in which the logic network operates on the dynamic node to cause a value to be written to the write latch based on the logic, and a wait phase for the test mode for which the write latch can be read to determine if the value transitions thereby indicating a fault, the other precharge phase, the write phase, and the wait phase determined by other states of the test enable signal, the clock signal, and the wait signal.