Patent ID: 7551651

Claim:
A multiplexer, comprising: a first latch having a first input for receiving a first bit stream and a second input for receiving a clock signal, wherein the first latch is an edge-triggered latch clocked in phase when the clock signal transitions into a first polarity to transmit input data from the first data stream, and latch the input data when the clock signal transitions into a second polarity; a first return-to-differential-zero latch coupled to the first latch, the first return-to-differential-zero latch having a first input for receiving an output of the first latch and a second input for receiving a clock signal, wherein the first return-to-differential-zero latch is an edge-triggered latch clocked in phase when the clock signal transitions into a second polarity to transmit output data from the first latch, and wherein the first return-to-differential-zero latch has an output comprising the value of the output of the first latch when the first return-to-differential zero latch receives a clock signal of the second polarity and comprising a neutral value when the first return-to-differential-zero latch receives a clock signal of the first polarity; a second return-to-differential-zero latch having a first input for receiving a second bit stream and a second input for receiving a clock signal, wherein the second return-to-differential-zero latch is an edge-triggered latch clocked in phase when the clock signal transitions into the first polarity to transmit input data from the second bit stream; and a selector having a first input coupled to the output of the first return-to-differential-zero latch and a second input coupled to the output of the second return-to-differential-zero latch, and a third input for receiving a select input signal.