Patent ID: 8193567

Claim:
A circuit device comprising: a microprocessor cache comprising static random access memory (SRAM) formed on a bulk semiconductor substrate, the cache further including: a first non-planar transistor, wherein the first non-planar transistor includes a first non-planar semiconductor body having a first gate-coupled sidewall height; and a second non-planar transistor, wherein the second non-planar transistor includes a second non-planar semiconductor body with a second gate-coupled sidewall height, different than the first gate coupled sidewall height, to form two multi-gate transistors of differing channel widths within the cache, wherein the first non-planar semiconductor body further comprises a first active region having a first top surface and wherein the second non-planar semiconductor body further comprises a second active area having a second top surface substantially coplanar with the first top surface; and the circuit device further comprising a microprocessor core comprising a logic region formed on the bulk semiconductor substrate, the logic region including a planar transistor, wherein the planar transistor further comprises: a third active region having sidewalls substantially covered by an adjacent third isolation region on the bulk semiconductor substrate; a third gate insulator on a top surface of the third active region; a third gate electrode on the third gate insulator; and a third pair of source/drain regions on opposite sides of the third gate electrode.