Patent ID: 8327067

Claim:
A memory system, comprising: a nonvolatile semiconductor memory comprising a plurality of memory blocks, each of the memory blocks comprising a plurality of memory cells; a plurality of I/O terminals; a command latch enable terminal; an address latch enable terminal; a write enable terminal; and a memory controller coupled to the nonvolatile semiconductor memory, the I/O terminals, the command latch enable terminal, the address latch enable terminal, and the write enable terminal, the memory controller being configured to receive a first command, a second command, a first address, count information, and a plurality of pieces of data through the I/O terminals from outside of the memory system, the memory controller being configured to receive a command latch enable signal through the command latch enable terminal from the outside of the memory system, the memory controller being configured to receive an address latch enable signal through the address latch enable terminal from the outside of the memory system, the memory controller being configured to receive a write enable signal through the write enable terminal from the outside of the memory system, the count information indicating a number of pieces of data, wherein the controller is configured to perform: latching the first command in accordance with the write enable signal while the command latch enable signal is asserted; after latching the first command, latching the count information in accordance with the write enable signal while the address latch enable signal is asserted; after latching the first command, latching the first address in accordance with the write enable signal while the address latch enable signal is asserted; after latching the count information and the first address, latching the pieces of data in accordance with the write enable signal, a number of the latched pieces of data being same as the number indicated by the latched count information; after latching the count information and the address, latching the second command in accordance with the write enable signal while the command latch enable signal is asserted; and after latching the second command, writing a first piece of data among the latched pieces of data to memory cells in the nonvolatile semiconductor memory corresponding to the latched first address.