Patent ID: 7030673

Claim:
A phase splitter circuit comprising: a first signal transfer path for receiving an input signal to generate a first output signal of which phase is equal to that of the input signal; and a second signal transfer path for receiving the input signal to generate a second output signal that is an inverted version of the first output signal, wherein each of the first and second signal transfer paths includes a plurality of cascaded logic elements, and each of which has pull-up and pull-down delay times, wherein when the input signal makes a transition, the sum of pull-down delay times of elements of the first signal transfer path is equal to the sum of pull-down delay times of elements of the second signal transfer path, and the sum of pull-up delay times of elements of the first signal transfer path is equal to the sum of pull-up delay times of elements of the second signal transfer path, and wherein a transition time of the first output signal is equal to a transition time of the second output signal.