Patent ID: 7656381

Claim:
A system for providing dual resolution control of a display panel, said system comprising: a dual resolution control circuit comprising four shift registers, each of the shift registers outputting a shifting signal; four logic gates; a switching network coupled among the shifting registers and the logic gates; wherein, in a low resolution mode, the switching network directs the shifting signals to the shift registers such that each of the first and the second shift registers outputs a first shifting signal and each of the third and the fourth shift registers outputs a second shifting signal, the switching network also directs the shifting signals to the logic gates such that each of the first and the second logic gates outputs a first panel control signal and each of the third and the fourth logic gates outputs a second panel control signal, and wherein pulses of the first and the second panel control signals do not temporally overlap, and wherein each of the shift registers receives a first clock signal and a second clock signal, receives a shifting signal from another shift register as its start pulse input, and each of output terminals of the shift registers is connected through the switching network to at least one of the logic gates, and a plurality of switches, the switches being operative to direct the first clock signal and the second clock signal to the shift registers such that: in a high resolution mode, the first shift register and the third shift register receive the first clock signal as their first inputs and the second clock signal as their second inputs, and the second shift register and the fourth shift register receive the first clock signal as their second inputs and the second clock signal as their first inputs; and in the low resolution mode, the first shift register and the second shift register receive the first clock signal as their first inputs and the second clock signal as their second inputs, and the third shift register and the fourth shift register receive the first clock signal as their second inputs and the second clock signal as their first inputs.