Patent ID: 8120075

Claim:
A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device, the semiconductor device comprising: a gate stack having first and second sidewall spacers, the gate stack being implemented above the channel region of the semiconductor device; first and second trenches formed adjacent to the gate stack, each of the first and second trenches having a first portion having a vertical sidewall which is in vertical alignment with a corresponding lightly doped drain region at an outer end of a corresponding side wall spacer, and a second portion below the first portion, the second portion being conically shaped to be wider at a top of each second portion of each trench as compared to a width of each trench below the top of each second portion of each trench, wherein the top of the second portion of the first trench is in vertical alignment with the outer end of the first sidewall spacer and the top of the second portion of the second trench is in vertical alignment with the outer end of the second sidewall spacer; strained silicon alloy formed within the first and second trenches; and wherein a stress force exerted on the channel region of the semiconductor device is maximized at a surface of the semiconductor device below the gate stack.