Patent ID: 8614475

Claim:
A memory device comprising: a plurality of memory cells formed on a substrate of the memory device; a dielectric layer deposited over a control gate of each memory cell, of the plurality of memory cells, and the substrate, the dielectric layer being deposited using an atomic layer deposition process, the dielectric layer, deposited using the atomic layer deposition process, filling spaces between adjacent memory cells of the plurality of memory cells, and the dielectric layer, deposited using the atomic layer deposition process, having a substantially uniform thickness that prevents re-entrant angles; and an interlayer dielectric deposited over the dielectric layer, the interlayer dielectric being deposited to fill, based on the substantially uniform thickness that prevents the re-entrant angles, the spaces between the adjacent memory cells, voids, in the interlayer dielectric, being eliminated based on the interlayer dielectric being deposited to fill the spaces between the adjacent memory cells.