Patent ID: 7616471

Claim:
A ferroelectric memory device comprising: a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells, wherein the sense amplifiers each include: a first n-MOS transistor, a first voltage being supplied to a source of the first n-MOS transistor; a first precharge unit precharging a drain of the first n-MOS transistor to a second voltage, which is a positive voltage that is higher than the first voltage; a transistor control unit that lowers the drain voltage that has been precharged to the second voltage by controlling a resistance between the source and the drain of the first n-MOS transistor in accordance with a voltage on a corresponding bit line, when data stored in the memory cells is read out to that bit line; and a voltage control unit that lowers the voltage of the bit line in accordance with the lowering of the voltage of the drain, wherein the transistor control unit comprises: a second precharge unit precharging a gate of the first n-MOS transistor to a predetermined positive voltage; and a first capacitor arranged between the bit line and the gate, wherein the first capacitor is a ferroelectric capacitor.