Patent ID: 8745443

Claim:
A memory system comprising: a first volatile storage area; a second nonvolatile storage area including a plurality of blocks, each one of the plurality of blocks being a data erasing unit and including a plurality of pages, and each one of the plurality of pages being a data programming unit; an address translation table stored in the second nonvolatile storage area and associating logical addresses designated by a host device with physical addresses of the second nonvolatile storage area; and a data manager configured to: transmit the address translation table stored in the second storage area to the first storage area at startup of the memory system; when an event to update the address translation table occurs, write difference logs indicating difference information before and after update of the address translation table in the first storage area; and when a predetermined condition is satisfied, write first difference logs in a first block and second difference logs having the same information as the first difference logs in a second block by a parallel page programming operation, thereafter write a first finalizing log in the first block and a second finalizing log in the second block.