Patent ID: 8691696

Claim:
A method of forming an integrated circuit, the method comprising: forming a sacrificial mandrel overlying a base substrate, the sacrificial mandrel having sidewalls; forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having a lower portion proximal the base substrate and having a substantially perpendicular outer surface relative to the base substrate and an upper portion spaced from the base substrate and having a sloped outer surface; forming a first dielectric layer overlying the base substrate and conformal to at least a portion of the upper portion of the sidewall spacers; removing the upper portion of the sidewall spacers after forming the first dielectric layer to form a recess in the first dielectric layer, the recess having a re-entrant profile corresponding to the sloped outer surface of the upper portion of the sidewall spacers; and straightening the re-entrant profile of the recess wherein forming the recess produces the first dielectric layer having a free region spaced from the lower portion of the sidewall spacers and a pinned region adjacent the lower portion of the sidewall spacers, wherein straightening the re-entrant profile comprises generating stress in the first dielectric layer that expands the recess adjacent the free region of the first dielectric layer at a greater magnitude than adjacent the pinned region.