Patent ID: 8853750

Claim:
A transistor formed on a substrate having an active semiconductor region, the transistor comprising: a channel region disposed within a bulk semiconductor region of the semiconductor substrate and having a plurality of fins, each fin having an apex extending in a first direction parallel to a major surface of the substrate, and each fin extending in a second direction downwardly away from the apex thereof; a gate overlying the apexes and extending downwardly between adjacent fins of the channel region; a plurality of dielectric regions, each dielectric region extending in the first direction and disposed between lower portions of respective adjacent fins; a semiconductor stressor region extending in at least the first direction away from the fins and being configured to apply a stress to the channel region, the semiconductor stressor region including a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region; and a source region and a drain region separated from one another in the first direction by the channel region, at least one of the source region or the drain region disposed at least partly within the semiconductor stressor region; wherein the plurality of dielectric regions do not extend to a first peripheral edge of the active semiconductor region in the first direction.