Patent ID: 7917327

Claim:
A dual-robotic parallel test system for testing semiconductor chips comprising: test boards, each having a test socket for receiving a semiconductor chip for testing by the test boards, each test board for electrically connecting a semiconductor chip inserted into the test socket; a main system interface, coupled to the plurality of test boards, for commanding the test boards to test semiconductor chips inserted into test sockets and for receiving test results from the test boards; a traveling buffer having buffer cavities for receiving semiconductor chips, the traveling buffer movable between a front position in a front roaming area and a back position in a back roaming area; a back robotic arm, movable within the back roaming area and responsive to commands from the main system interface, for inserting and removing semiconductor chips into the test sockets on the test boards and for inserting and removing semiconductor chips from the buffer cavities on the traveling buffer when traveling buffer is in the back position within the back roaming area; a front robotic arm, movable within the front roaming area and responsive to commands from the main system interface, for inserting and removing semiconductor chips from the buffer cavities on the traveling buffer when the traveling buffer is in the front position within the front roaming area; an input tray, within the front roaming area, for holding untested semiconductor chips, the front robotic arm picking a semiconductor chip from the input tray and inserting the semiconductor chip into the traveling buffer; and an output tray, within the front roaming area, for holding tested semiconductor chips.