Patent ID: 7553741

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: a forming first, second and third layers over an SOI layer of an SOI substrate which includes a laminated structure of a semiconductor substrate, an embedded insulating layer, and the SOI layer, with the third layer on the SOI layer, the first layer on the third layer, and the second layer formed over the first layer, and simultaneously patterning the first layer and the second layer; (b) forming a first trench of a predetermined number by removing a part of upper layer portions of the SOI layer exposed from the second layer as patterned, the first trench of the predetermined number leaving lower layer portions of the SOI layer under the part of upper layer portions of the SOI layer as removed; (c) forming at least one second trench that reaches the embedded insulating layer by removing a part of the second layer exposed from a patterned resist and the SOI layer of lower part of at least one of the first trenches of the predetermined number, including forming a second insulating layer in a bottom face and a side face of the first trench, and a side face of the third layer by thermal oxidation process; and forming the second trench by removing the second insulating layer and the SOI layer exposed from the patterned resist; (d) performing CMP treatment until reaching the first layer after embedding an insulating layer for isolation in the first and the second trench after removing the resist; and (e) removing the third layer collectively at a time of removal of the first layer.