Patent ID: 7640374

Claim:
A DMA apparatus which reads a descriptor and data from memory corresponding to a descriptor, comprising: a dividing unit to divide one descriptor which is read from the memory into a plurality of sub-descriptors; a plurality of DMA controllers, coupled to the dividing unit to produce a plurality of reading requests to read data corresponding to the plurality of sub-descriptors from the memory; and a memory controller to read corresponding data from the memory according to the plurality of reading requests received in parallel from the plurality of DMA controllers, wherein each of the plurality of sub-descriptors is allocated to a respective one of the plurality of DMA controllers, each of the plurality of DMA controllers reads the data corresponding to the plurality of sub-descriptors from the memory and performs an advance-preparation processing of reading data by turns, and while one of the plurality of DMA controllers performs processing of reading data from the memory, at least another of the DMA controllers performs the advance-preparation processing, and the plurality of DMA controllers perform processing of reading data continuously from the memory.