Patent ID: 7755116

Claim:
An image sensor integrated circuit, comprising: a plurality of photodetectors generating electrons excited by incident photons, each of the plurality of photo detectors including: an n-type region receiving the electrons excited by the energy of the photons; a plurality of nodes, wherein each of the plurality of photodetectors has a corresponding node of the plurality of nodes; a plurality of transfer devices controlling a transfer of the electrons from said each of the plurality of photodetectors to the corresponding node, the plurality of transfer devices having a transfer device background p-type concentration under a control terminal, each of the plurality of transfer devices including: a first terminal coupled to the n-type region of one of the plurality of photodetectors; a second terminal coupled to one of the plurality of nodes; and the control terminal receiving a control signal, wherein the transfer of the electrons occurs between the first terminal and the second terminal in response to the control signal of sufficient value applied to the control terminal; a first plurality of p-type regions having a concentration stronger than the transfer device background p-type concentration, wherein each of the first plurality of p-type regions has a lateral position only partly under the control terminal of a transfer device of the plurality of transfer devices, the first plurality of p-type regions controlling the transfer of electrons from a photodetector of the plurality of photodetectors to the corresponding node of the photodetector, and each of the first plurality of p-type regions has the lateral position at least partly under the corresponding node, and the first plurality of p-type regions has the lateral position stopping short of the plurality of photodetectors and stopping short of a plurality of reset devices; the plurality of reset devices, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active; row and column circuitry; and a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.