Patent ID: 6983382

Claim:
A computing system, comprising: a central processing unit; a host memory coupled to said central processing unit, said host memory storing instructions executed by said central processing unit and data operated upon by way of said central processing unit executing said instructions; a network interface receiving inbound IP packets and sending outbound IP packets; an offload processing subsystem, said offload processing subsystem communicatively coupled to said central processing unit and said network interface, said offload processing subsystem comprising: a) TCP/IP logic circuitry processing TCP/IP tasks on said inbound and outbound IP packets without using said central processing unit and said host memory; b) SSL decryption logic circuitry processing SSL tasks on said inbound IP packets without using said central processing unit and said host memory; c) SSL encryption logic circuitry processing SSL tasks on said outbound IP packets without using said central processing unit and said host memory; d) a storage resource comprising one or more memory chips coupled to both said SSL decryption logic circuitry and said SSL encryption logic circuitry, said storage resource storing SSL processing information; e) an offload memory coupled to said TCP/IP logic circuitry, said offload memory storing said inbound and outbound TCP/IP packets, said network interface coupled to said offload memory; f) a first direct memory access (DMA) controller retrieving said inbound IP packets from said offload memory, said first DMA controller coupled to said SSL decryption logic circuitry; g) a second direct memory access (DMA) controller retrieving said outbound IP packets from said host memory, said second DMA controller coupled to said SSL encryption logic circuitry.