Patent ID: 7323369

Claim:
A fabrication method for a thin film transistor (TFT) array substrate, the method comprising: forming a plurality of scan lines on a substrate; sequentially forming a patterned dielectric layer and a patterned semiconductor layer over the substrate for covering portions of the scan lines; sequentially forming a patterned transparent conductive layer and a patterned metal layer over the substrate, the patterned transparent conductive layer and the patterned metal layer used for defining a plurality of data lines, a plurality of source/drain electrodes, a plurality of pixel electrodes and a plurality of etching protective layers, the etching protective layers covering and being parallel electrically connected to the scan lines exposed by the patterned dielectric layer and the patterned semiconductive layer; forming a passivation layer over the substrate; and removing the passivation layer over the pixel electrodes and the patterned metal layer of the pixel electrodes for exposing the patterned transparent conductive layer of the pixel electrodes, and removing the patterned semiconductive layer over the scan lines between the etching protective layers and the data lines for exposing the patterned dielectric layer over the scan lines.