Patent ID: 7904688

Claim:
A logic board configured to be plugged into a backplane of a computer system, said logic board comprising: a board; a field-programmable gate array (FPGA) block disposed on said board and having a set of FPGA ICs; board memory disposed on said board and supporting application program execution of at least one application program by said set of FPGA ICs; memory management unit (MMU) disposed on said board, said MMU being operatively coupled to said FPGA block and said board memory, said MMU managing memory in said board memory; a first list tracking a first free memory chunk set, said first free memory chunk set including free memory chunks in said board memory; logic removing allocated memory chunks from said first free memory chunk set when said allocated memory chunks are allocated to a task, said allocated memory chucks being memory chunks of said first free memory chunk set that are allocated to said task; logic deallocating said allocated memory chunks such that said allocated memory chunks become deallocated memory chunks after said task has terminated; a second list tracking a first deallocated memory chunk set, said first deallocated memory chunk set including said deallocated memory chunks; logic determining that said first list has become empty; and logic swapping a tracking activity of said first list and a tracking activity of said second list when said first list has become empty, said second list becoming empty immediately after said swapping, wherein said first list tracks a second free memory chunk set after said swapping, said second free memory chunk set including said deallocated memory chunks, and said second list tracks a second deallocated memory chunk set after said swapping.