Patent ID: 8493541

Claim:
A manufacturing method of an array substrate, comprising: forming gate lines, data lines, pixel electrodes, and gate electrodes, active layer members, source electrodes, drain electrodes of thin film transistors (TFTs) in pixel units in a display region and farming the gate lines and the data lines in a pad region, wherein a process of forming the data lines, the active layer members, the source electrodes and the drain electrodes in the display region and simultaneously forming the data lines in the pad region comprises: sequentially forming an active layer film and a data line metal film; applying a photoresist layer on the data line metal film, and then exposing and developing the photoresist layer to form a first photoresist completely-remained region, a first photoresist partially-remained region and a first photoresist completely-removed region of the photoresist layer; performing a first wet etching process to etch away the data line metal film in the first photoresist completely-removed region and performing a first dry etching process to etch away the active layer film in the first photoresist completely-removed region, so that the data lines, the source electrodes and the drain electrodes are formed in the pixel units; ashing to remove the photoresist layer by a thickness of the photoresist in the first photoresist partially-remained region; performing a second wet etching process to etch away the data line metal film in the first photoresist partially-remained region and performing a second dry etching process to etch away a portion of the active layer film in the first photoresist partially-remained region, so that channel regions of the active layer members are defined in the pixel units and the data lines is formed in the pad region; ashing to remove the remaining photoresist layer; and etching away the remaining active layer film in the first photoresist partially-remained region in the pad region.