Patent ID: 8856468

Claim:
A memory device comprising: a memory unit; a first storage unit configured to store a logical address and an intermediate address, the intermediate address corresponding to the logical address and being used to estimate a physical address of the memory unit; a second storage unit configured to store the intermediate address and the physical address corresponding to the intermediate address; a third storage unit configured to store a flag corresponding to the logical address and the intermediate address, the flag representing whether a read of latest data by a read operation using the logical address and the intermediate address has succeeded; a data move unit configured to move data in the memory unit; and a controller configured to, when the data move unit moves the data in the memory unit, and the flag stored in the third storage unit represents a success of the read of the latest data, determine whether a write has been done for the same logical address of the memory unit during the data move, and, if the write has been done, invalidate the data move.