Patent ID: 8569110

Claim:
A method of manufacturing a substrate for an integrated circuit package, comprising the steps of: a) patterning a leadframe on a first side forming a plurality of lands and a first recessed portion between said plurality of lands; b) disposing a first bonding compound on said first side of said leadframe, said first bonding compound having a first portion filling said first recessed portion; c) patterning said leadframe on an opposing second side forming a plurality of electrically isolated routing leads and a second recessed portion between said plurality of routing leads; d) disposing a second bonding compound on said second side of said leadframe filling at least a portion of said second recessed portion; and e) disposing a plurality of bonding pads on said plurality of routing leads; whereby said first bonding compound prevents displacement of said plurality of routing leads; and combination of said first bonding material and said second bonding material hold metal features in place during assembly processes of die attach, die to substrate interconnection and encapsulation molding.