Patent ID: 7486544

Claim:
A semiconductor integrated circuit device comprising: a plurality of memory cells each comprised of a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between said storage and complementary bit lines and whose gate is connected to a word line; an address selection circuit for setting all of word lines to a non-selection level in a standby state where any of writing and reading operations is not performed on said memory cell; and a substrate bias switching circuit, wherein in normal operation, said substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed, and wherein in said standby state, said substrate bias switching circuit supplies to said N-type well a predetermined voltage which is lower than said power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased.