Patent ID: 7335950

Claim:
A semiconductor device comprising: an underlayer film over a substrate; a crystalline silicon film including a channel region, a drain region and an impurity region disposed between the channel region and the drain region over the underlayer film; a gate insulating film over the crystalline silicon film; a gate electrode covering the channel region on the gate insulating film, wherein the gate electrode does not cover the impurity region; a first interlayer insulating film over the gate electrode; a first contact hole in the gate insulating film and the first interlayer insulating film; a second interlayer insulating film over the first interlayer insulating film; and a second contact hole in the second interlayer insulating film, wherein the drain region and the impurity region include an n-type impurity and a p-type impurity, wherein a concentration of the n-type impurity included in the drain region is higher than a concentration of the n-type impurity included in the impurity region, wherein a concentration of the p-type impurity included in the drain region is substantially the same as a concentration of the p-type impurity included in the impurity region, and wherein a center of the first contact hole and a center of the second contact hole are substantially the same.