Patent ID: 7910450

Claim:
A method of fabricating a semiconductor structure comprising: forming a patterned ion implantation mask on a surface of a semiconductor substrate, said patterned ion implantation mask having an opening that exposes a region of the semiconductor substrate; forming a buried resistor following the formation of the ion implantation mask by ion implantation, the buried resistor is present beneath the surface of the semiconductor substrate and in said exposed region of the semiconductor substrate; removing said patterned ion implantation mask following the forming of the buried resistor; annealing said semiconductor substrate after removing the patterned ion implantation mask to at least heal damages in said semiconductor substrate above said buried resistor caused during said ion implantation; forming an epitaxial semiconductor layer on an upper surface of the semiconductor substrate following the annealing; forming isolation regions within the epitaxial semiconductor layer; and forming a first well region and a second well region in said semiconductor substrate and said epitaxial semiconductor layer in contact with an upper surface of said buried resistor, wherein the first well region is in contact with a first end of the buried resistor and the second well region is in contact with an opposing second end of the buried resistor, wherein said buried resistor has a sheet resistance tolerance of less than 10%.