Patent ID: 8842231

Claim:
An array substrate, comprising: a base substrate; a gate scanning line, a data scanning line, a pixel electrode and a thin film transistor, formed on the base substrate; and a light blocking layer, formed on the base substrate and corresponding to the thin film transistor and the data scanning line, wherein an active thin film pattern is formed between a first insulating layer formed on the light blocking layer or the gate scanning line and a second insulating layer formed on the data scanning line, the pixel electrode and the thin film transistor, the active thin film pattern comprises two semiconductor layers, and the two semiconductor layers are spaced from each other via a semiconductor insulating layer, in a direction perpendicular to a plane where the gate electrode is located, the two semiconductor layers are disposed in different layers and completely overlap with each other, so that a double-channel TFT structure is formed, wherein the light blocking layer comprises a gate light blocking portion and a scanning line light blocking portion, the double-channel TFT structure is a double-gate structure in which the gate electrode and the gate light blocking portion are configured as two gate electrodes of the double-channel TFT structure.