Patent ID: 8130884

Claim:
An apparatus for synchronizing a signal analyzer, the apparatus being applied to the signal analyzer for analyzing an input signal, the input signal being input from outside the signal analyzer and having a frame structure, the apparatus comprising: an Analog-to-Digital Converter (ADC) configured to convert the input signal into a corresponding digital signal; a signal storage unit configured to store the digital signal received from the ADC; a trigger signal generation unit configured to generate a trigger signal for each predetermined period; a signal acquisition control unit configured to acquire the digital signal, stored in the signal storage unit, from a signal acquisition time point that is preset on a basis of a trigger signal received from the trigger signal generation unit; signal analysis unit configured to calculate a start position of a frame from the digital signal, which is received from the signal acquisition control unit, the signal analysis unit including a synchronization acquisition algorithm, a series of algorithms for signal analysis, and a part for transmitting a signal acquisition command; and a time error control unit configured to (a) calculate a time error between a time point at which each trigger signal is generated and the start position of the frame of the digital signal, in consideration of the start position of the frame calculated by the signal analysis unit, and (b) set a subsequent signal acquisition time point based on the calculated time errors.