Patent ID: 6895515

Claim:
A computer comprising: a controller: for interrupting an input of a power-off instruction into a power management unit to supply power to the computer when the power-off instruction is output to the power unit in response to an instruction from an operating system, and for generating a hardware signal of said computer; wherein said power management unit controls a power state of said computer, said controller is disposed between said power management unit and said power unit, said contoller: interrupts the input of the power-off instruction output from said power management unit into said power unit, outputs a dummy power-on signal, representing an instruction of power-on, to said power management unit subsequent to generation of a hardware reset by outputting a dummy power state signal, representing an invalid power state, to said power management unit; and processing means for turning off the power of said computer after executing a predetermined process, said processing means being started by the hardware reset signal; and wherein said processing means enables said controller and stores predetermined information into a nonvolatile memory when the execution of a predetermined process is instructed and the execution of a power-off process of said computer by an operating system is detected, and turns off said power of said computer after executing said predetermined process and disabling the operation of said controller if said computer is started by the hardware reset and said predetermined information is stored in memory.