Patent ID: 7616029

Claim:
An integrated circuit having a signal bias monitor comprising: a first bias comparator connected to compare first and second voltages relative to a first bias point to generate a first comparison output; a first voltage-domain translator connected to convert the first comparison output from a first voltage domain to a second voltage domain; a second bias comparator connected to compare the first and second voltages relative to a second bias point different from the first bias point to generate a second comparison output; a second voltage-domain translator connected to convert the second comparison output from the first voltage domain to the second voltage domain; and logic circuitry connected to generate a signal bias monitor output signal based on the first and second comparison outputs in the second voltage domain, wherein: the signal bias monitor output signal has a first output value when the first and second comparison outputs are both equal to a first comparison result; the signal bias monitor output signal has a second output value when the first and second comparison outputs are both equal to a second comparison result; the signal bias monitor output signal changes from the first output value to the second output value only after the first and second comparison outputs both change from the first comparison result to the second comparison result; and the signal bias monitor output signal changes from the second output value to the first output value only after the first and second comparison outputs both change from the second comparison result to the first comparison result.