Patent ID: 7825430

Claim:
A semiconductor device comprising: a first semiconductor region of a first conduction type, having a main surface; a second semiconductor region of said first conduction type, serving as a drain region of a field effect transistor, said second semiconductor region extending from one side to an other side and also extending from said main surface of said first semiconductor region to a predetermined depth; a third semiconductor region of a second conduction type, provided at said one side of said second semiconductor region and extending from a surface of said first semiconductor region to a predetermined depth to space said one side of said second semiconductor region and said first semiconductor region from each other; a trench provided at said other side of said second semiconductor region at a surface of said first semiconductor region and having a predetermined depth to space said other side of said second semiconductor region and said first semiconductor region from each other; a fourth semiconductor region of said first conduction type, serving as a source region of said field effect transistor, said fourth semiconductor region being provided in a region extending from a surface of said third semiconductor region to a depth shallower than a bottom of said third semiconductor region such that said fourth semiconductor region is spaced from said first semiconductor region by said third semiconductor region; a fifth semiconductor region of said second conduction type, provided in contact with a bottom of said third semiconductor region and a bottom of said trench and extending from said bottom of said third semiconductor region to said bottom of said trench to space a bottom of said second semiconductor region and said first semiconductor region from each other; a sixth semiconductor region of said first conduction type to which a predetermined high potential is connected, said sixth semiconductor region being spaced from said trench, said sixth semiconductor region being located in a region opposite to said third semiconductor region with said trench posed therebetween, said sixth semiconductor region extending from a surface of said first semiconductor region to a predetermined depth; an electrode portion serving as a gate electrode of said field effect transistor, said electrode portion being provided on a surface of a portion of said third semiconductor region with a gate insulation film posed therebetween, said portion of said third semiconductor region being sandwiched between said second semiconductor region and said fourth semiconductor region; and an interconnect having a predetermined resistance and electrically connecting said second semiconductor region and said sixth semiconductor region together.