Patent ID: 8415749

Claim:
A semiconductor structure comprising: a substrate comprising an isolation region; a first trench recess in the substrate and spaced apart from a gate conductor overlying the substrate, the first trench recess having a bottom surface and a vertical surface; a first source/drain region formed within the first trench recess; a first seal dielectric conformally lining the first trench recess, a bottom portion of the first seal dielectric being disposed between the first source/drain region and the bottom surface, a first vertical portion of the first seal dielectric being disposed between the first source/drain region and the vertical surface, a second vertical portion of the first seal dielectric being adjacent the isolation region; an epitaxial semiconductor layer overlying the first source/drain region and the substrate, a bottom surface of the epitaxial semiconductor layer being in direct contact with an upper surface of the first vertical portion of the first seal dielectric, in direct contact with an upper surface of the first source/drain region, and in direct contact with an upper surface of the substrate underlying the gate conductor, a first portion of the epitaxial semiconductor layer forming a channel region spaced from the first trench recess and underlying the gate conductor; and a second source/drain region formed in a second portion of the epitaxial semiconductor layer at least partially overlying the first source/drain region; and a lightly doped extension region formed in the epitaxial semiconductor layer, the lightly doped extension region being in electrical contact with the second source/drain region and the channel region, the lightly doped extension region being in direct contact with the upper surface of the first vertical portion of the first seal dielectric.