Patent ID: 8683180

Claim:
A method for administering physical registers in multiple physical register sets of a processor said method comprising: during out-of-order execution by the processor of instructions referencing logical registers: recording, in entries of a unified main mapper of the processor, transient mappings between the logical registers referenced by the instructions and physical registers in the multiple physical register sets of the processor; recording, in entries of a separate architected register mapper, architected mappings between the logical registers referenced by the instructions and the physical registers of the processor; and populating entries of an intermediate register mapper with transient mappings transferred from the unified main mapper; and allocating entries in the unified main mapper to instructions following dispatch of the instructions and prior to issue of the instructions to one or more execution units of the processor for execution; wherein the populating includes the processor transferring a transient mapping for an instruction that has finished execution but has not been completed by committing its execution results to an architected state of the processor from an entry of the unified main mapper to an entry of the intermediate register mapper and releasing the entry in the unified main mapper prior to completion of the instruction, such that a number of entries in the unified main mapper available for allocation is increased.