Patent ID: 8040733

Claim:
A non-volatile memory device comprising: a first string of n memory cell transistors, where “n” is a natural number greater than 2; a second string of n memory cell transistors; a plurality of n first word lines respectively connected to gates of the first string memory cell transistors; a plurality of n second word lines respectively connected to gates of the second string memory cell transistors; wherein respective jth ones of the first and second word lines are connected to commonly receive a bias voltage, where “j” ranges from 1 to n; a first dummy cell transistor connected at a first end of the first string; a second dummy cell transistor connected at a first end of the second string; a first dummy word line connected to the gate of the first dummy cell transistor; and a second dummy word line connected to the gate of the second dummy cell transistor, wherein the first and second dummy word lines are configured to respectively receive different bias voltages independent of one another.