Patent ID: 8108816

Claim:
A computer-implemented method for adjustment of history-based delay variation during static timing analysis of an integrated circuit design, the method comprising: obtaining information through sources of variability, including at least one of characterization and simulation, of one or more history-based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories; inputting history bounds for at least one signal of the integrated circuit design; computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design using at least one computing device; evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design; and based on the evaluated device history bounds, adjusting, using the at least one computing device, at least one of a value of the history-based delay variability and propagation of timing through additional segments of the integrated circuit design.