Patent ID: 7679961

Claim:
A memory device, comprising: an array of memory cells; control logic in communication with the array of memory cells, the control logic comprising: a control state machine configured to control program and/or erase operations on the array of memory cells; a counter in communication with the control state machine; a memory in communication with the counter; compare logic coupled to the counter; and starting-voltage level control logic coupled to the counter; wherein the counter is configured to receive, from memory, a number of program/erase cycles applied to one or more memory cells of the array of memory cells and to increment that number of program/erase cycles each time a program/erase cycle is applied to the one or more memory cells; wherein the compare logic is configured to compare the incremented number of program/erase cycles to one or more numerical values; and wherein the starting-voltage level control logic is configured to adjust a program starting voltage level and/or an erase starting voltage level based on the comparison of the incremented number of program/erase cycles to the one or more numerical values.