Patent ID: 7986255

Claim:
An overlapping segmented M-bit digital to analog converter (DAC) for receiving an M-bit binary input M IN and generating a corresponding DAC current, comprising: a controller to receive M IN and generate in response, an S-bit upper range segment binary input S IN and an R-bit lower range segment binary input R IN , where R+S is greater than M, with the most significant bit of S IN having a binary weight of 2 M−1 , and the binary weight of 2 R being at least twice the binary weight of the least significant bit (LSB) of S IN an S-bit high range DAC configured to receive S IN and generate, in response, a high range DAC current proportional, by a constant K, to the summed binary weight of the S IN bits; an R-bit low range DAC configured to receive R IN and generate, in response, a low range DAC current proportional, by the constant K, to the summed binary weight of the R IN bits, and a current summer to add the high-range DAC current and the low range DAC current to generate said current.