Patent ID: 8412983

Claim:
A memory test circuit for receiving an input signal that is set to a first set value or a second set value and a clock signal that is generated in a predetermined cycle to test a memory which operates in one of first predetermined cycles and second predetermined cycles, the memory test circuit comprising: a counter circuit that outputs a set signal that is set to the first set value and a set signal that is set to the second set value alternately in a cycle of the clock signal; an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal; and a test pattern generation circuit that generates a test pattern for causing the memory to operate in the first predetermined cycles when the control signal is has a first transition pattern, and generates ea test pattern for causing the memory to operate in the second predetermined cycles when the control signal has a second transition pattern.