Patent ID: 6977845

Claim:
A semiconductor memory device comprising: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in said cell array blocks; sense amplifier circuits for reading cell data of said cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for said first area of said first cell array block and a second area of a second cell array block are simultaneously executed, while said busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of said first area held in said sense amplifier circuits to the chip external, and in a second read cycle selecting said second area in said second cell array block, after said busy signal generation circuit has output a dummy busy signal shorter in time length than said true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of said second area held in said sense amplifier circuits to the chip external.