Patent ID: 6908810

Claim:
A method of preventing threshold voltage of a MOS transistor from being decreased by formation of shallow trench isolation, the method comprising: providing a substrate comprising a plurality of shallow trench isolations to isolate a plurality of first and second active regions, wherein the first active regions are located within a core circuit region, and the second active regions are located within a peripheral circuit region; performing a first ion implantation on the first active regions and the second active regions to form a plurality of well regions in the first and second active regions, respectively; performing a second ion implantation on the second active regions and edge portions of the first active regions, so that a second channel ion implant region is formed in the second active regions and a dopant concentration of the edge portions of the first active regions is increased; and performing a third ion implantation on the first active regions to form a first channel region in each of the first active regions.