Patent ID: 7384847

Claim:
A method of forming a DRAM array, comprising: providing a semiconductor construction comprising a plurality of storage node contact locations and bitline contact locations; forming an etch stop over the storage node contact locations; forming a first electrically insulative material over the etch stop; etching a plurality of trenches extending entirely through the first electrically insulative material, each trench of the plurality of trenches comprising both a first portion extending to one of the bitline contact locations and a second portion extending to the etch stop, the second portion being over one of the storage node contact locations; forming electrically conductive material within the trenches and in electrical contact with the bitline contact locations, the electrically conductive material within the trenches defining a plurality of spaced electrically conductive lines; each of the electrically conductive lines having a pair of opposed lateral edges and a first lateral width between the opposed lateral edges; forming a plurality of spaced electrically insulative lines directly over the electrically conductive lines, within the trenches, and in a one-to-one correspondence with the electrically conductive lines, each of the spaced electrically insulative lines having opposed lateral edges and a second lateral width between the opposed lateral edges which is greater than the first lateral width; the electrically insulative lines comprising a second electrically insulative material; etching openings which extend entirely through the first electrically insulative material and etch stop to the storage node locations, the openings being aligned with the lateral edges of the spaced electrically insulative lines; and forming capacitors having storage nodes within the openings.