Patent ID: 7696799

Claim:
An analog/digital control delay locked loop (DLL) comprising: a phase detector for receiving an input clock signal and a feedback signal and detecting a phase difference between the two signals to provide one of an up detection signal and a down detection signal; a charge pump for receiving one of the up detection signal and the down detection signal and generating an adjusted output current based on the signals; a loop filter for low pass-filtering the output current to produce an analog control voltage; a voltage controlled delay line (VCDL) for receiving the analog control voltage, the input dock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to generate an output clock signal; a delay replica modeling unit formed by replicas of a delay factor for receiving the output clock signal and producing the feedback signal; and a digital code generator for generating the digital code, wherein the VCDL includes a plurality of delay cells connected in services, and each delay cell includes: a differential input transistor unit for receiving differential input clock signals; an analog control transistor unit whose one terminal is connected to a power supply terminal for adjusting a first delay amount in response to analog control voltages; and a digital control transistor unit connected between the analog control transistor unit and the differential input transistor unit for adjusting a second delay amount in response to a digital code, wherein said first delay amount is less than said second delay amount.