Patent ID: 7394708

Claim:
A system that compensates for process variations in a semiconductor device, comprising: a memory array having a plurality of memory cells formed in one or more well regions of the device; a test circuit having a test port coupled to the memory array and having an output to generate a feedback signal indicating whether one or more of the memory cells fail to operate properly in response to a testing of the operation of the memory cells; and an adjustable bias voltage circuit having an input to receive the feedback signal and having an output coupled to the one or more well regions, wherein the adjustable bias voltage circuit is configured to selectively adjust a bias voltage provided to the one or more well regions in response to the feedback signal to alter the operating characteristics of the memory cells, wherein the adjustable bias voltage circuit comprises: a control circuit having an input to receive the feedback signal and having outputs to generate a plurality of bias control signals; and a configurable voltage-divider circuit having a plurality of voltage taps selectively coupled to the one or more well regions in response to corresponding bias control signals, and wherein the control circuit is configured to selectively assert the bias control signals in response to iterative assertions of the feedback signal generated during corresponding test operations of the memory array.