Patent ID: 6898745

Claim:
An integrated device, comprising: a pad receiving, in a standard operative condition, an input signal having a first value and a second value greater than said first value, and, in a test operative condition a test voltage having a third value, higher than said second value; an input stage including an inverter and, having an input connected to said pad, said input stage comprising an electronic component which has a first and a second terminal, said first terminal being connected to said input of said input stage and said second terminal being connected, in said standard operative condition, to a reference potential line set at a reference potential; a third-level detecting stage connected to said pad, and having an output supplying a logic-type third-level signal which has a first level in the presence of said input signal and a second level in the presence of the test voltage; and biasing means including a switch having a control terminal coupled to the third-level detecting stage, the biasing means connected to said second terminal of the electronic component and supplying a biasing voltage in presence of said second level of said third-level signal, said biasing voltage being higher than said reference potential and lower than said third value of said test voltage.