Patent ID: 7968926

Claim:
A non-volatile memory cell comprising: a semiconductor substrate; a first transistor comprising: a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric; a second transistor electrically coupled to the first transistor, the second transistor comprising: a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric, wherein the first and the second floating gates are electrically disconnected; a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third, and the fourth capacitors comprises the semiconductor substrate as one of capacitor plates; a third transistor as a selector of the non-volatile memory cell, wherein the third transistor is electrically coupled to the first and the second transistors, and wherein sources of the first and the second transistors are connected to each other when the selector is turned on and when the selector is turned off, and drains of the first and the second transistors are connected to each other when the selector is turned on and when the selector is turned off; and a bit line electrically connected to a first source/drain region of the third transistor, wherein a second source/drain region of the third transistor is electrically connected to a second source/drain region of each of the first and the second transistors.