Patent ID: 6990618

Claim:
An integrated circuit, comprising: a first boundary scan cell in a plurality of boundary scan cells, the plurality of boundary scan cells being configured for boundary scan testing of the integrated circuit, the first boundary scan cell being configured to receive a first input signal and output a first output signal and a second output signal, the first input signal comprising a differential signal as received by the first boundary scan cell; a second boundary scan cell in the plurality of boundary scan cells, the second boundary scan cell being configured to receive the first output signal of the first boundary scan cell, the second boundary scan cell being configured to output a third output signal and a fourth output signal; a third boundary scan cell in the plurality of boundary scan cells, the third boundary scan cell being configured to receive the third output signal of the second boundary scan cell, the third boundary scan cell being configured to output a fifth output signal and a sixth output signal; a core logic configured to receive the second output signal of the first boundary scan cell, the fourth output signal of the second boundary scan cell, and the sixth output signal of the third boundary scan cell, wherein the second output signal of the first boundary scan cell comprises a differential signal as received by the core logic; and a first input-output (I/O) node coupled to an input of the first boundary scan cell.