Patent ID: 7668040

Claim:
A memory device that stores a plurality of data items and accesses the stored data items in response to a bank address, a row address and a column address, the memory device comprising: a plurality of banks, each of which has a memory cell array having a plurality of page areas selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals, wherein a memory unit area within each of the activated page areas is accessed based on the column address, the row controller has: a multi-bank activation controller that generates a bank activation signal for each of the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first operation code; and a row address calculator that generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address, and the plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.