Patent ID: 7230952

Claim:
A mechanism for enabling an interleaving of time-critical type-1 and delay-tolerant type-2 packets on a shared channel in a communication module having a local time counter, the module transmitting type-1 and type-2 data packet streams on a shared channel, the mechanism comprising: a type-1 packet buffer; a type-2 packet buffer; a register for storing a transfer duration of a packet waiting in the type-2 packet buffer, the transfer duration being represented by an integer X≧0; an integer value produced from the output of a time counter; a comparator for comparing said integer value of the time counter and the transfer duration and producing a two-bit output Q, the output Q being “00” if transfer duration is smaller than the integer value of the time counter, and “11” if the integer value of the time counter is zero, regardless of the value of the transfer duration; and a 2:1 selector for selecting a packet from the type-1 packet register if Q is “11”, the type-2 packet register if Q is “10”, and remaining in an idle state if Q is “00”.