Patent ID: 7499317

Claim:
A non-volatile memory system, comprising: a set of non-volatile storage elements, said set includes a first subset of non-volatile storage elements and a second subset of non-volatile storage elements; managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry erases said set of non-volatile storage elements by: applying an erase voltage to said set while enabling the first subset of said storage elements for erase and inhibiting the second subset of said storage elements from erase, applying said erase voltage to said set of non-volatile storage elements while enabling said second subset for erase and inhibiting said first subset from erase, and repeating at least one of said applying said erase voltage while said first subset is enabled for erase and said applying said erase voltage while said second subset is enabled for erase if said set is not verified as erased.