Patent ID: 7145194

Claim:
A semiconductor integrated circuit device comprising: a memory cell having first and second transfer MISFETs, first and second drive MISFETs and first and second load MISFETs, each disposed at an intersection between a pair of complementary data lines and a word line, the first drive MISFET and first load MISFET being cross-coupled with the second drive MISFET and second load MISFET, wherein the first and second transfer MISFETs and the first and second drive MISFETs are formed over the main surface of a semiconductor substrate, wherein a first insulating film is formed over the semiconductor substrate and a first opening is formed in the first insulating film, wherein a first capacitor element is formed over the sidewall and bottom of the first opening, the first capacitor element having, as a lower electrode, a first conductive film formed along the sidewall and bottom of the first opening, as a capacitor insulator film, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film, wherein a supply voltage line electrically connected to the first and second drive MISFETs and a reference voltage line electrically connected to the first and second drive MISFETs are formed over the first capacitor element, wherein the lower electrode forms a first storage node of the memory cell by electrically connecting a drain of the first drive MISFET, a drain of the first load MISFET, a gate electrode of the second drive MISFET and a gate electrode of the second load MISFET, and a second storage node of the memory cell by electrically connecting a drain of the second drive MISFET, a drain of the second load MISFET, a gate electrode of the first drive MISFET and a gate electrode of the first load MISFET, and wherein the first capacitor element is electrically connected between the first storage node and second storage node, and the supply voltage line, between the first storage node and second storage node, and the reference voltage line, or between the first storage node and the second storage node.