Patent ID: 6944748

Claim:
A signal processor for executing variable-sized instructions, each instruction comprising up to N codes with N being a positive integer greater than 1, the signal processor comprising: a program memory comprising I individually addressable, parallel-connected memory banks with I being a positive integer at least equal to N, said program memory comprising a program recorded in an interlaced fashion as a function of one code per memory bank and per address applied to said memory banks; and reading means for reading said program memory by reading a code in each of said I memory banks during a cycle for reading an instruction, with each instruction comprising a sequence of codes to be read and when a number of the sequence of codes of the instruction being read is less than I, then codes belonging to a following instruction are read, said reading means comprising address means for applying to said memory banks individual addresses generated from a collective value of a program counter that is incremented, before a beginning of the cycle for reading the instruction, by a value equal to a number of codes belonging to a previous instruction, and applying to each of said memory banks an individual read address that is based upon a result of a division by I of the collective value of the program counter, the individual read address for each respective memory bank being equal to P 0 or P 0 ±1, with P 0 being a quotient of the division by I of the collective value of the program counter, and filtering means for filtering codes that do not belong to the instruction to be read, while using parallel bits accompanying the codes.