Patent ID: 6970121

Claim:
A digital to analog converter circuit, comprising: a first MSB (most significant bits) digital to analog converter for receiving MSB data of a first digital image signal in a first clock period, and outputting a first voltage range signal according to the MSB data of the first digital image signal; a second MSB digital to analog converter for receiving MSB data of a second digital image signal in a second clock period immediately following the first clock period, and outputting a second voltage range signal according to the MSB data of the second digital image signal; a delay circuit for sampling and holding LSB (last significant bits) data of the first digital image signal in the first clock period, sampling and holding LSB data of the second digital image signal, outputting the LSB data of the first digital image signal in the second clock period, and outputting the LSB data of the second digital image signal in a third clock period immediately following the second clock period; an LSB digital to analog converter, coupled to the delay circuit, for receiving the LSB data of the first digital image signal in the second clock period, outputting first image data within the first voltage range according to the LSB data of the first digital image signal, receiving the LSB data of the second digital image signal in the third clock period, and outputting second image data within the second voltage range according to the LSB data of the second digital image signal; a first switch, coupled to the first MSB digital to analog converter and the LSB digital to analog converter and turned on in the second clock period, for providing the first voltage range signal to the LSB digital to analog converter; and a second switch, coupled to the second MSB digital to analog converter and the LSB digital to analog converter and turned on in the third clock period, for providing the second voltage range signal to the LSB digital to analog converter.