Patent ID: 7379319

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of cell transistors provided on a surface of the semiconductor substrate; a local bit line provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors; ferroelectric capacitors corresponding in number to the cell transistors, provided above the local bit line, each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of corresponding one of the cell transistors; a plate line provided above the upper electrodes and electrically connected to the upper electrodes; a reset transistor provided on the surface of the semiconductor substrate with one of a source diffusion layer and a drain diffusion layer electrically connected to the plate line and the other one electrically connected to the local bit line; and a block selection transistor provided on the surface of the semiconductor substrate with one of a source diffusion layer and a drain diffusion layer electrically connected to a bit line provided above the plate line and the other one electrically connected to the local bit line.