Patent ID: 8461887

Claim:
An integrated circuit comprising: a reference-signal source to generate a reference signal having a basic frequency; a phase locked loop including a voltage-controlled oscillator to generate a signal having a frequency corresponding to a given control voltage, a first frequency divider to carry out frequency division on the signal by N to generate a first frequency-divided signal, a phase detector to detect a phase difference between the first frequency-divided signal and the reference signal, a charge pump to generate a current signal corresponding to the phase difference, and a loop filter to generate the control voltage in accordance with the current signal; a second frequency divider to carry out the frequency division on the signal generated by the voltage-controlled oscillator by M to generate a second frequency-divided signal; and a signal processing circuit to operate in synchronization with the second frequency-divided signal, wherein a minimum absolute value of a difference between the basic frequency multiplied by “K” (“K” is an arbitrary integer equal to or higher than 1) and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.