Patent ID: 8069394

Claim:
A semiconductor memory device comprising: a semiconductor memory configured to nonvolatilely store (a) a plurality of detecting codes to respectively detect errors in a plurality of data items, (b) a plurality of first correcting codes to respectively correct errors in a plurality of first data blocks each of which comprises one of the data items and a corresponding detecting code, (c) a second correcting code to correct errors in a second data block which comprises the first data blocks, and (d) the second data block; a first corrector configured to correct errors in the first data blocks using the first correcting codes, respectively; a detector configured to detect, using the detecting codes, errors in the data items corrected by the first corrector, respectively, and generate first error information representing presence/absence of an error in each of the corrected data items; and a second corrector configured to correct errors in, of the corrected data items, a number of data items containing errors using the first error information and the second correcting code, wherein an error correction capability of the second correcting code is higher than error correction capabilities of the first correcting codes.