Patent ID: 7523151

Claim:
A method for producing a digital logic circuit for performing mathematical computations using residue arithmetic, comprising: providing a means for receiving input data in binary code, wherein the input data in binary code comprise binary operands having a plurality of bits; computing the residue modulo p i values for at least one subgroup of a plurality of bits of the binary operands for each possible input data in binary code; extracting logical equations representing the computed residue modulo p i values of the at least one subgroup of the plurality of bits of the binary operands; and mapping the logical equations to a plurality of logic gates; providing a means for converting the input data in binary code to residues, wherein the means for converting the input data in binary code to residues comprises a means for computing residue modulo p i values of at least one subgroup of the plurality of bits of the binary operands, wherein the means for converting the input computing residue modulo p i values of at least one subgroup of the plurality of bits of the binary operands comprises the plurality of logic gates, wherein the means for receiving input data in binary code and the means for converting the input data in binary code to residue are the digital logic circuit.