Patent ID: 7653523

Claim:
A method for calculating high-resolution wafer parameter profiles comprising the steps of: a) defining an appropriate product/device input dataset for a plurality of different die sizes and products, wherein the dataset comprises physical correlation reference points comprising information relating to the size of each die in two directions as well as the location of at least one of the corners of each die; b) collecting a die level yield bin dataset for one of the products/devices defined in step (a) by using the product/device input dataset to generate a table of data for the lots and wafers of said one of the products/devices with a virtual die coordinate for each die and a corresponding value; c) calculating a single composite value for each said virtual die coordinate; d) defining where on a virtual die it is desired to assign a composite value; e) calculating physical coordinates for each die value using the corresponding virtual coordinate and a physical translation key; f) repeating steps (b), (c), (d) and (e) for each of said die sizes and products defined in step (a); g) merging the data from a plurality of files into one file; h) defining a grid; i) creating a table with all possible grid coordinates that would fit on a production wafer; j) defining a smoothing algorithm; k) calculating the smoothed value for each point on the grid from the combined data; and l) plotting a wafer profile.