Patent ID: 7863197

Claim:
A method for fabricating a semiconductor structure comprising: forming a gate structure on a semiconductor substrate to provide a masked portion of the semiconductor substrate and an exposed portion of the semiconductor substrate; etching the exposed portion of the semiconductor substrate to recess the exposed portion of the semiconductor substrate relative to the masked portion of the semiconductor substrate with an etchant that is a non-plasma gaseous etchant comprising an etchant gas comprised of chlorine, fluorine, hydrogen chloride, hydrogen fluoride or a combination thereof, and a deposition gas comprised of silane, silicon fluoride, silicon chloride or a combination thereof, wherein the etchant applied to the semiconductor substrate produces a channel region in the masked portion of the semiconductor substrate having a cross-section hourglass shape; and forming source and drain regions on the exposed portions of the semiconductor substrate that have been recessed relative to the masked portion of the semiconductor substrate, wherein the source and drain regions induce a stress on the channel region.