Patent ID: 7932517

Claim:
A semiconductor device comprising: a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on a lower surface side and an upper surface side thereof, respectively; a second circuit substrate provided on a lower side of the first circuit substrate, wherein the second circuit substrate has an opening which exposes a part of the first circuit substrate, and the second circuit substrate also has, on a lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines; a first semiconductor construct which is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to lower wiring lines of the first circuit substrate; a third circuit substrate provided on an upper side of the first circuit substrate and having a plurality of lower wiring lines connected to the upper wiring lines of the first circuit substrate; and at least one of an electronic component and a second semiconductor construct which is provided on the third circuit substrate and which is connected to a plurality of upper wiring lines of the third circuit substrate, wherein said plurality of test connection pads include at least a first inspection connection pad which is configured to inspect the first semiconductor construct.