Patent ID: 8767436

Claim:
A method for non-destructive reading of data stored in a memory including a first wordline, a first bitline, a second bitline, and a first ferroelectric transistor, the first ferroelectric transistor having a first conduction terminal coupled to the first bitline, a second conduction terminal coupled to the second bitline, and a control terminal coupled to the first wordline, the first ferroelectric transistor comprising a layer of ferroelectric material in a stable state of polarization capable of assuming high and low logic values; and a second wordline and a second ferroelectric transistor, the second ferroelectric transistor having a first conduction terminal coupled to the first bitline, a second conduction terminal coupled to the second bitline, and a control terminal coupled to the second wordline, the second ferroelectric transistor comprising a layer of ferroelectric material in a stable state of polarization and capable of assuming a high logic value and a low logic value, the method comprising: biasing the control terminal of the first ferroelectric transistor to a first biasing value by applying to the first wordline a reading voltage so as to not cause a variation of the stable state of polarization of the layer of ferroelectric material; generating a sense voltage between the first and second bitlines; generating a current value of a current that flows between the first and second bitlines; comparing the current value to a plurality of comparison, values indicative of a respective number of logic data that have a high logic value or a low logic value for a column of the ferroelectric memory including the first and second ferroelectric transistors; and determining a logic value of the data based upon the comparison.