Patent ID: 8658531

Claim:
A method of forming connection holes comprising: providing a semiconductor substrate having a metal layer on the surface thereof; forming an etching stopper layer, a first dielectric anti-reflective coating layer, an interlayer dielectric layer and a second dielectric anti-reflective coating layer successively on the surface of the metal layer; forming photoresist patterns on the second dielectric anti-reflective coating layer, wherein the openings of the photoresist pattern are different in size; etching the second dielectric anti-reflective coating layer using the photoresist patterns as a mask until exposing the interlayer dielectric layer; performing a first etching process to the interlayer dielectric layer by using a first etching gas to form multiple openings of different sizes, and stopping the first etching process when the first dielectric anti-reflective coating layer is exposed through the opening of the maximum size; performing a second etching process to the interlayer dielectric layer by using a second etching gas, and stopping the second etching process when the first dielectric anti-reflective coating layer is exposed through the opening of the minimum size; performing over-etching to remove the residual first dielectric anti-reflective coating layer until exposing the etching stopper layer through all the openings to form the connection holes having different diameters.