Patent ID: 7594198

Claim:
A microchip having at least one I/O area surrounding at least one core circuit area, the I/O area comprising: a first I/O cell having a first pre-driver device area and at least one post-driver NMOS transistor area connected to a first I/O pad; a second I/O cell disposed adjacent to the first I/O cell, the second I/O cell having a second pre-driver device area and the post-driver NMOS transistor area connected to a second I/O pad, wherein the first and second I/O cells share a plurality of NMOS transistors disposed on the post-driver NMOS transistor area, but have separate pre-driver device areas; a first conductive line overlying the first I/O cell for selectively connecting some of the NMOS transistors disposed on the post-driver NMOS transistor area to the first I/O pad; a second conductive line overlying the second I/O cell for selectively connecting the rest of the NMOS transistors disposed on the post-driver NMOS transistor area to the second I/O pad; and an electrostatic discharge (ESD) cluster shared by the first I/O cell and the second I/O cell for protecting the first and second I/O cells against ESD current during an ESD event, thereby reducing a total width of the first I/O cell and the second I/O cell.