Patent ID: 7308627

Claim:
A method of locating a fault within an array of integrated circuits comprising: establishing row propagation speeds for gated timing signals passed through a number of rows of serially connected interconnect modules of an array of serially connected interconnect modules; establishing a row reference propagation speed based upon said row propagation speeds; comparing said row propagation speeds individually to said row reference propagation speed to establish a row fault criteria; establishing column propagation speeds for gated timing signals passed through a number of columns of serially connected interconnect modules of said array of serially connected interconnect modules; establishing a column reference propagation speed based upon said column propagation speeds; comparing said column propagation speeds individually to said column reference propagation speed to establish a column fault criteria; generating a matrix of row and column fault conditions based upon said row and column fault criteria; and, locating said fault within said array of interconnect modules by utilizing said row and column fault conditions within said matrix that correspond to an array location.