Patent ID: 8180966

Claim:
An intermediate node comprising: a packet buffer comprising one or more First-In-First-Out (FIFO) queues, wherein each FIFO queue is configured to hold one or more packets, and each FIFO queue comprises a high-speed portion and a low-speed portion, wherein the high-speed portion resides in high-speed memory and the low-speed portion resides in low-speed memory; and a traffic manager connected to the packet buffer and configured to enqueue and dequeue the one or more packets to and from the one or more FIFO queues, the traffic manager to enqueue the one or more packets directly to the low-speed portions of the one or more FIFO queues, without first storing the one or more packets in the high-speed portions of the one or more FIFO queues, and to dequeue the one or more packets from the high-speed portions of the one or more FIFO queues.