Patent ID: 7535781

Claim:
A semiconductor memory including a memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair through a switching element capable of ON/OFF switching in response to a value of a column selection signal and a precharge circuit for controlling an initial potential common between the data line pair, wherein the semiconductor memory comprises a precharge potential control circuit which applies, in a precharge period, a low apply voltage not higher than a first predetermined potential to the data line pair when the initial potential of the data line pair is higher than the first predetermined potential, a high apply voltage not lower than a second predetermined potential to the data line pair when the potential of the data line pair is lower than the second predetermined potential or no voltage when the potential of the data line pair is not higher than the first predetermined potential and not lower than the second predetermined potential, wherein the precharge potential control circuit includes a predetermined potential output circuit which divides a voltage between a low apply voltage generator for generating the low apply voltage and a high apply voltage generator for generating the high apply voltage to output the first and second predetermined potentials, the predetermined potential output circuit includes an n-channel MOS transistor connected to the high apply voltage generator via a drain and a gate thereof, and the predetermined potential output circuit divides a voltage between a source of the n-channel MOS transistor connected to the high apply voltage generator and the low apply voltage generator to output the first and second predetermined potentials.