Patent ID: 7307346

Claim:
A semiconductor device comprising: a substrate including an active area, said active area having at least one last metal conductor, and a portion spaced from said at least one last metal conductor; a last level interconnect capping layer disposed over the active area, including said portion spaced from said at least one last metal conductor; a first buffer layer/crack stop layer deposited on and coextensive with the last level interconnect capping layer; a first passivation layer deposited on and coextensive with the first buffer layer/crack stop layer; a second buffer layer/crack stop layer deposited on and coextensive with the first passivation layer; a second passivation layer deposited on and coextensive with the second buffer layer/crack stop layer; an aperture defined in and extending through said capping layer, said first and second buffer layers and said first and second passivation layers, said aperture located over said at least one last metal conductor; and a contact pad overlying the second passivation layer, and including a connection portion and a contact portion, said connection portion filling said aperture and in electrical contact with said at least one last metal conductor, and said contact portion extending from said connection portion such that said contact portion overlies said portion of said substrate spaced from said at least one last metal conductor, but does not overlap said at least one last metal conductor.