Patent ID: 8151025

Claim:
A fast round robin circuit, comprising: a sequential circuit including at least one stage of request flip-flops configured to contain a request signal R and to memorize the request signal; a sequential circuit including at least one stage of select flip-flops configured to output a select signal S and to memorize the select signal, the request and the select flip flops being paired and associated to every requesting entity of a plurality of requesting entities; at least one multiplexer accepting the select signal, the multiplexer selecting a highest sequential priority requesting entity among the plurality of requesting entities for data communication of the highest sequential priority requesting entity with a resource being requested by the highest sequential requesting entity among competing requests from among the plurality of requesting entities, wherein the requests are handled in a round robin manner while skipping inactive requests to handle subsequent active requests in a polling direction of the sequential circuit; and an OR gate chain configured to generate an activation signal for polling said plurality of requesting entities even if said resource is free and no select signal is present, wherein said OR gate chain comprises a plurality of OR gates, an output of one of said OR gates comprising an input of a subsequent one of said OR gates in said OR gate chain.