Patent ID: 8436668

Claim:
A flop circuit comprising: an input circuit having an input node, wherein the input circuit is configured to hold a logic value of an input signal received on the input node; a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value; and a transfer circuit coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level; wherein the transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit, and wherein the transfer circuit includes a first transistor having a gate terminal coupled to the first float node, a second transistor having a gate terminal coupled to the second float node, and a third transistor having a gate terminal coupled to receive the clock pulse, wherein the third transistor is coupled between a reference node and each of the first and second transistors.