Patent ID: 8183126

Claim:
A method comprising: providing a first semiconductor wafer with a first facing surface on which a first conductive layer is formed, the first semiconductor layer comprises an embedded silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor; attaching the first semiconductor wafer to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed, wherein the first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure; removing material from the first semiconductor layer to form a plurality of spaced apart stacked pillars of semiconductor material and each pillar comprises a resistive random access memory element; thereafter removing portions of the embedded combined conductive layer to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure, and wherein said control lines directly contact with a plurality of said resistive random access memory element and respective sets of the pillars are contactingly supported by the respective control lines and the plurality of said resistive random access memory element are formed between the metal oxide semiconductor field effect transistors and the control lines; and wherein the resistive random access memory element comprises a spin-torque transfer random access memory element connected to a channel based switching device.