Patent ID: 7596661

Claim:
A processing module with multilevel cache architecture, comprising: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache corresponds to at least one L1 cacheable range of a memory; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache corresponds to at least one L2 cacheable range of the memory, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and the memory and for transferring data between the L2 cache and the memory, wherein when the processor executes a program code, the L1 cache is utilized for caching instructions and read-only data of the program code, and the L2 cache is utilized for caching initialized read-write data and non-initialized data of the program code; when the processor sends a request to the L1 cache to retrieve data at an address falling within the L1 cacheable range, if the requested data is not in the L1 cache, the L1 cache asks the memory instead of the L2 cache for the requested data; and when the processor sends a request to the L1 cache to retrieve data at an address falling outside the L1 cacheable range, the L1 cache asks the L2 cache for the requested data, and if the requested data is in the L2 cache, the L1 cache forwards the requested data from the L2 cache to the processor without saving the requested data in the L1 cache; wherein the L1 cache comprises: at least one control register for storing cacheability information defining the L1 cacheable range; and a determining module, coupled to the control register, for determining whether the request retrieves data at an address falling within the L1 cacheable range by inspecting the cacheability information of the control register.