Patent ID: 8248835

Claim:
A semiconductor memory comprising: a plurality of memory cells aligned in a two dimensional matrix, each memory cell comprising a ferroelectric capacitor comprising a ferroelectric film between two electrodes and a cell transistor corresponding to the ferroelectric capacitor; a plurality of bit lines connected to the plurality of memory cells; a plurality of word lines connected to gate electrodes of the plurality of cell transistors; a plurality of plate lines connected to a first one of two electrodes of the plurality of ferroelectric capacitors; a plurality of sense amplifiers connected between a pair of the plurality of bit lines; at least one test pad configured to charge an external voltage to the plurality of bit lines; a plurality of test transistors corresponding to the plurality of bit lines, the plurality of test transistors connected between the test pad and the plurality of bit lines; and a fatigue test bias circuit connected to a first node between the test pad and the plurality of test transistors, wherein the plurality of test transistors are shared in a first test in which the test pad is configured to charge a first voltage to the plurality of ferroelectric capacitors and a second test in which the fatigue test bias circuit is configured to charge a second voltage to the plurality of ferroelectric capacitors.