Patent ID: 7913222

Claim:
In a computing device, a method for generating code from a model for a hardware implementation of the model, the method comprising: providing, via a processing unit associated with the computing device, a plurality of interface types for an interface between two components of the model, each of the plurality of interface types including size, clock, and power parameters for the model, the plurality of interface types further including at least two of: a first interface type where input data and output data are transferred cyclically, a second interface type where input data is transferred cyclically and output data is flow controlled by a signal to enable output, a third interface type where input data and output data transfer are flow controlled by a signal to enable a clock, a fourth interface type where input data and output data transfer are flow controlled by a signal to activate a clock, a fifth interface type where a first amount of input data and a second amount of output data are transferred per clock cycle, a sixth interface type where flow control is unidirectional, a seventh interface type where flow control is bidirectional, an eighth interface type that includes a single clock, or a ninth interface type that includes multiple clocks; receiving, via the processing unit, at least two selections, from the provided plurality of interface types, for the interface between the two components; determining, via the processing unit and from the at least two selections from the provided plurality of interface types, an interface type, for the interface between the two components, using a balancing algorithm and a weighted combination of the size, power, and clock parameters for the model; and automatically generating, via the processing unit, code representative of the determined interface type for the interface between the two components.