Patent ID: 7989289

Claim:
A method, comprising: forming a tunnel dielectric on a semiconductor substrate; and forming a floating gate structure on the tunnel dielectric, the floating gate structure comprising at least a first region having a first electron energy level or electron work function or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron work function or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron work function or carrier capture efficiency is less than the second electron energy level or electron work function or carrier capture efficiency, wherein forming the floating gate structure on the tunnel dielectric comprises: depositing a first layer of the floating gate structure to the tunnel dielectric wherein the first layer comprises polysilicon to form the first region; depositing a sacrificial layer to the first layer to provide a stop layer for chemical mechanical polishing (CMP); patterning the sacrificial layer to form one or more trenches in at least the first layer of the floating gate structure, the tunnel dielectric, and the semiconductor substrate; depositing an isolation dielectric to fill the one or more trenches; polishing the isolation dielectric; removing the sacrificial layer; and depositing a metal to the first layer to form the second region of the floating gate by silicidation of a portion of the polysilicon of the first layer.