Patent ID: 7816950

Claim:
A semiconductor integrated circuit comprising: a data input terminal; a data output terminal; a master latch circuit that has an input connected to the data input terminal, and has a first data holding terminal that holds a first logic of data that is input through the data input terminal or a second logic generated by inverting the first logic of the data; a slave latch circuit that has an input connected to an output of the master latch circuit, has an output connected to the data output terminal, and has a second data holding terminal that holds a logic being equal to a logic held by the first data holding terminal in accordance with data that is input from the master latch circuit; a clock signal generating circuit that generates and outputs a first clock signal for controlling an operation of the master latch circuit, and generates and outputs a second clock signal for controlling an operation of the slave latch circuit; a switch circuit that is connected between the first data holding terminal and the second data holding terminal; an error detection circuit that senses a logic of the first data holding terminal and a logic of the second data holding terminal, and outputs an error detection signal when a logic of the first data holding terminal and a logic of the second data holding terminal differ from each other; and a control circuit that controls the clock signal generating circuit and the switch circuit, wherein the control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data held by the second data holding terminal equal to each other, and switches on the switch circuit, and the error detection circuit senses a logic of the first data holding terminal and a logic of the second data holding terminal after switching on the switching circuit.