Patent ID: 7093107

Claim:
A data processor comprising: an instruction execution pipeline comprising: a read stage; a write stage; and a first execution stage comprising E execution units capable of producing data results from data operands; a register file comprising a plurality of data registers, each of said data registers capable of being read by said read stage of said instruction pipeline via at least one of R read ports of said register file and each of said data registers capable of being written by said write stage of said instruction pipeline via at least one of W write ports of said register file; and bypass circuitry capable of receiving data results from output channels of source devices in at least one of said write stage and said first execution stage, said bypass circuitry comprising: a first plurality of bypass tristate line drivers having input channels coupled to first output channels of a first plurality of said source devices and tristate output channels coupled to a first common read data channel in said read stage; and a first multiplexer having a first input channel coupled to said first common read data channel and an output channel coupled to a first operand channel of a first execution unit in said first execution stage.