Patent ID: 8185862

Claim:
A method to manage power in a custom integrated circuit (IC) design, comprising: a. receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage, wherein the profile comprising a data model associates an instruction's steady state probability of execution to a topology of an execution path b. creating from the data model sub-regions of a layout and for each sub-region determining a collection of intersecting execution paths yielding one or more execution path probabilities to determine a sub-region weight; c. applying sub-region weight distributions to estimate power hot-spot locations; d. automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; e. determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over the processing blocks to reduce hot spots; and f. synthesizing the generated architecture base on the sequence into a computer readable description of the custom integrated circuit for semiconductor fabrication.