Patent ID: 7120214

Claim:
A synchronous data transfer and processing device comprising: at least one data transfer path including a plurality of cascaded latch circuits each entering a transparent state of passing a received signal to an output node and a latching state of holding the received signal at said output node irrespectively of a change of the signal at the signal input node in accordance with a clock control signal applied at a clock input node, two consecutive latch circuits in said plurality of latch circuits being configured such that when one is in the latching state, another is in the transparent state; and control circuitry for generating a control signal for controlling a state of each of said plurality of latch circuits and transmitting the generated control signal to each of said plurality of latch circuits as said clock control signal, said control circuitry including a plurality of clock control circuits, arranged corresponding to the respective latch circuits, for applying the control signal to the clock input node of a corresponding latch circuit in accordance with a clock signal transmitted to the corresponding latch circuit and the clock control signal at the clock input node of the latch circuit at a next stage of the corresponding latch circuit.