Patent ID: 7660933

Claim:
A system on a chip, comprising: an embedded microprocessor that comprises a first type of cache, a second type of cache, a first type of RAM, a second type of RAM and an embedded processor core; a data bus coupled to the embedded microprocessor; and an interface coupled to the data bus, the interface configured to receive data bus requests from the data bus, wherein the data bus requests comprises memory access requests and I/O access requests, wherein the interface comprises a request splitter, a memory bridge and an I/O bridge, wherein the embedded processor core accesses a memory that is external to the system on the chip and I/O devices that are external to the system on the chip through the data bus and the memory bridge, wherein the request splitter receives the memory access requests and the I/O access requests from the data bus and routes the memory access requests and the I/O access requests to the memory bridge and the I/O bridge, wherein the request splitter separates data bus requests into the memory access requests and the I/O access requests according to a programmable address range, wherein the memory bridge comprises a first type of FIFO, a second type of FIFO, a first type of buffer and a second type of buffer, wherein the memory bridge is coupled to a memory controller that is external to the system on the chip, wherein the I/O bridge comprises a third type of FIFO, a fourth type of FIFO and a fifth type of FIFO, and wherein the I/O bridge is coupled to an I/O controller that is external to the system on the chip.