Patent ID: 8754525

Claim:
A semiconductor device comprising: a semiconductor substrate; integrated circuits formed on an upper surface of the semiconductor substrate; connection pads provided on the semiconductor substrate which are connected to the integrated circuits, the connection pads comprising common power supply voltage connection pads, common ground voltage connection pads, and normal voltage connection pads; a passivation film provided on the upper surface of the semiconductor substrate and having openings in regions corresponding to the connection pads; a protection film provided directly on an upper surface of the passivation film and having openings in regions corresponding to the connection pads; at least one first common wiring serving for a power supply voltage and provided solidly and directly on an upper surface of the protection film so as to be connected to the common power supply voltage connection pads via corresponding openings in the protection film and the passivation film; at least one second common wiring serving for a ground voltage and provided solidly and directly on the upper surface of the protection film so as to be connected to the common ground voltage connection pads via corresponding openings in the protection film and the passivation film; and at least two normal wirings each provided directly on the upper surface of the protection film so as to be connected to a normal voltage connection pad among the normal voltage connection pads via a corresponding opening in the protection film and the passivation film.