Patent ID: 8237203

Claim:
A semiconductor device having a plurality of standard cells arranged in a first direction and each having first and second peripheral edges extending in said first direction and opposite to each other, the semiconductor device comprising: a semiconductor substrate having a pMIS region and an nMIS region, said pMIS region being formed between said first peripheral edge and a boundary extending in said first direction through each of said plurality of standard cells and serving as a boundary between an n-type well and a p-type well, said nMIS region being formed between said second peripheral edge and said boundary; a first layer provided on said semiconductor substrate and having a plurality of gate wirings extending in a second direction orthogonal to said first direction; and a second layer provided on said first layer, said second layer including: a first power supply wiring extending along said first peripheral edge and electrically connected to said pMIS region; a second power supply wiring extending along said second peripheral edge and electrically connected to said nMIS region; a plurality of pMIS wirings arranged on a plurality of first virtual lines, respectively, extending between said first and second power supply wirings on said pMIS region in said first direction and arranged with a single pitch in said second direction; and a plurality of nMIS wirings arranged on a plurality of second virtual lines, respectively, extending between said first and second power supply wirings on said nMIS region in said first direction and arranged with said single pitch in said second direction, a first virtual line of said plurality of first virtual lines that is the closest to said boundary and a second virtual line of said plurality of second virtual lines that is the closest to said boundary having therebetween a spacing larger than said single pitch.