Patent ID: 7388434

Claim:
A BTL amplifier comprising: a substrate; first, second, third and fourth transistor regions on the substrate which are four rectangular regions substantially dividing a rectangular region on the substrate in lattice patterns, and each of the rectangular regions including a transistor consisting of three n-type or p-type semiconductor regions which are longitudinally or laterally parallel in each rectangular region; a power supply interconnection layer; a ground interconnection layer; first and second output interconnection layers to be connected to an external load; a first interconnection layer for connecting the first and the third transistor regions which are adjacent to each other in a lateral direction of the substrate to the power supply interconnection layer; a second interconnection layer for connecting the second and the fourth transistor regions which are adjacent to each other in a lateral direction of the substrate to the ground interconnection layer; a third interconnection layer for connecting the first and the second transistor regions which are adjacent to each other in a longitudinal direction of the substrate to the first output interconnection layer; and a fourth interconnection layer for connecting the third and the fourth transistor regions which are adjacent to each other in a longitudinal direction of the substrate to the second output interconnection layer; wherein the direction of the semiconductor regions of the first transistor region and the direction of the semiconductor regions of the third transistor region are parallel to each other, wherein the direction of the semiconductor regions of the first transistor region and the direction of the semiconductor regions of the second transistor region are perpendicular to each other, and wherein the direction of the semiconductor regions of the third transistor region and the direction of the semiconductor regions of the fourth transistor region are perpendicular to each other.