Patent ID: 7130982

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a partition manager residing in the memory and executed by the at least one processor, the partition manager managing allocation of a plurality of hardware resources to a plurality of logical partitions and managing communication between the plurality of logical partitions; an I/O adapter coupled to the at least one processor; a device driver for the I/O adapter, the device driver including an interface for performing an I/O operation on a first address of a first length by the I/O adapter, the device driver making a call to the partition manager passing the address of the first length to retrieve a corresponding address of a second length, wherein the first length is different than the second length; and a memory tag mechanism that creates a memory tag of the first length that corresponds to a second address of the second length, wherein the memory tag comprises an identifier that cannot be mapped to a corresponding location in physical memory; wherein the partition manager, when the device driver makes the call to the partition manager passing the first address of the first length to retrieve the corresponding address of the second length, detects when the first address is a memory tag by determining that the first address is in a predefined range of addresses, and if so, returns the second address of the second length that corresponds to the memory tag.