Patent ID: 7396781

Claim:
A method for semiconductor processing, comprising: providing a plurality of mandrels over a semiconductor substrate; measuring critical dimensions of the mandrels; subsequently selecting a first critical dimension of a first plurality of spacers based upon the critical dimensions of the mandrels, the spacers of the first plurality of spacers having a first predefined desired critical dimension, wherein selecting critical dimensions of the first plurality of spacers adjusts the first predefined desired critical dimensions to position centers of the spacers of the first plurality of spacers substantially at a desired first pitch; forming the first plurality of spacers of a first spacer material on sidewalls of the mandrels; selectively removing the mandrels; subsequently selecting a second critical dimension of a second plurality of spacers based upon the critical dimensions of the first plurality of spacers, the spacers of the second plurality of spacers having a second predefined desired critical dimension, wherein selecting critical dimensions of the second plurality of spacers adjusts the second predefined desired critical dimensions to position centers of the spacers of the second plurality of spacers substantially at a desired second pitch; and forming the second plurality of spacers of a second spacer material on sidewalls of the spacers of the first plurality of spacers.