Patent ID: 7836281

Claim:
A method for improving performance of a processor, comprising: executing instructions for a main thread; upon encountering a non-data dependent stall condition during execution of the main thread, wherein the non-data dependent stall condition includes a deferred buffer full condition, generating a checkpoint, which includes an architectural state of the processor, entering scout mode, wherein instructions are speculatively executed by a speculative thread to prefetch future memory references, but results are not committed to the architectural state of the processor, wherein both the main thread and the speculative thread are associated with a single software thread, and upon encountering a memory reference during scout mode, issuing a prefetch for the memory reference; and wherein if the stall condition that caused the processor to enter scout mode is resolved, the method further comprises, using the checkpoint to resume execution of the main thread from the instruction that caused the stall condition, wherein the processor reexecutes instructions executed during scout mode, and wherein results of the instructions executed during scout mode are not reused, and simultaneously continuing execution of instructions in scout mode using the speculative thread from the point where the speculative thread left off while the processor executes instructions in the main thread.