Patent ID: 7983087

Claim:
An array of NVM cells for storing information, comprising: a plurality of NVM cells forming a plurality of strings of serially connected NVM cells, each string forming a first group of serially connected NVM cells and a second group of serially connected NVM cells; a plurality of word lines each coupled to said strings, wherein each word line couples a control gate electrode of a corresponding NVM cell in each string; a plurality of bit lines each coupled to a corresponding one of said strings wherein each bit line couples to a source or drain terminal of an NVM cell in said first group within its corresponding string and a source or drain terminal of an NVM cell in said second group within its corresponding string; a first set of select transistors each coupling a corresponding one of said strings, wherein each select transistor in said first set selectably couples one source or drain terminal of an NVM cell in said first group within the corresponding string to a power supply or a ground voltage; and a second set of select transistors each coupling a corresponding one of said strings, wherein each select transistor of said second set selectably couples one source or drain terminal of an NVM cell in said second group within the corresponding string to a power supply or a ground voltage opposite that power supply or ground voltage coupled by the corresponding select transistor of said first group within the corresponding string.