Patent ID: 8194085

Claim:
A memory hub for a graphics system to be compatible with different memories, comprising: a dynamic random access memory (DRAM) interface supporting DRAM interface processes of a plurality of different types of DRAM memories with each type of DRAM memory being compliant with a specific DRAM memory standard having a signaling protocol and bus terminations defined by the specific DRAM memory standard; a hub interface; and logic for bridging signals between said hub interface and said DRAM interface and performing translation of signals between said hub interface and said DRAM interface; said memory hub being operative for a graphics processing unit to utilize said hub interface to access any type of DRAM memory within the plurality of different types of DRAM memories supported by the memory hub, said memory hub being operative to aggregate simultaneous access to multiple ones of the plurality of different types of DRAM memories to increase memory bandwidth, said hub interface being operative to utilize a high speed packetized bus protocol, and said DRAM interface being operative to utilize a non-packetized bus protocol, said high speed packetized bus protocol has at least a factor of two faster transfer rate than said non-packetized bus protocol, such that said memory hub reduces an I/O pin count on said graphics processing unit.