Patent ID: 7930674

Claim:
A method of modifying a first integrated circuit design with a first maximum operating frequency to achieve a second integrated circuit design with a second maximum operating frequency, the first integrated circuit design comprising an arrangement of a plurality of cells, each of the plurality of cells driving a respective signal through a net of other circuit elements to one or more nodes limited by respective signal timing constraints, the method comprising the steps of: assigning analytical cost functions to respective ones of the plurality of cells, each analytical cost function comprising a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design; and replacing one or more of the plurality of cells with different cells based on the determined analytical cost functions; each of the first and second integrated circuit designs comprising a physical layout of its corresponding cells; at least a given one of the analytical cost functions comprising a value that is based on a weighted combination of at least two speed-related factors using respective unequal weights, said at least two speed-related factors including at least one factor other than propagation delay, signal transition time and capacitive load, said at least one factor comprising signal delay due to crosstalk on the net of other circuit elements driven by the respective cell; wherein the assigning and replacing steps are applied to the physical layout of the first integrated circuit design and are implemented in a data processing system comprising a memory and a data processor coupled to the memory; the method further comprising the step of transforming the second integrated circuit design into integrated circuit hardware.