Patent ID: 7292500

Claim:
A read activity detector circuit for use in a random access memory array, the circuit comprising: a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals each having a frequency that is substantially the same as a frequency of a core reference clock and having different phases relative to one another, each of the synchronizer circuits, in response to a first control signal presented thereto, generating an output signal having one of a rising edge and a falling edge which is substantially aligned to one of a rising edge and a falling edge of the reference clock signal corresponding thereto; and a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array; wherein at least a given one of the synchronizer circuits comprises first and second flip-flops, a data input of the first flip-flop receiving the first control signal, a clock input of the first flip-flop receiving a first one of the reference clock signals, a clock input of the second flip-flop receiving a second one of the reference clock signals, an output of the first flip-flop being connected to a data input of the second flip-flop, and an output of the second flip-flop generating the output signal of the given one of the synchronizer circuits.