Patent ID: 8022466

Claim:
A memory cell comprising: (i) a semiconductor layer having at least two source/drain regions proximate the surface of the semiconductor layer and separated by a channel region; (ii) a lower insulating layer disposed above the channel region; (iii) a charge storage layer disposed above the lower insulating layer; (iv) an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material interposed between a first dielectric layer and a second dielectric layer of a single material layer, and the first dielectric layer of the upper insulating multi-layer structure is disposed directly on and in contact with the charge storage layer, the polysilicon layer is disposed directly on and in contact with the first dielectric layer, and the second dielectric layer is disposed directly on and in contact with the polysilicon layer; and (v) a gate disposed directly on and in contact with the second dielectric layer of the upper insulating multi-layer structure.