Patent ID: 7290156

Claim:
A frequency-voltage mechanism for power management, comprising: a first PLL that generates a first source clock signal at a first frequency based on a bus clock signal; a second PLL that generates a second source clock signal at a second frequency based on a first frequency control signal and said bus clock signal, wherein said second PLL generates a first frequency lock signal when said second source clock signal achieves a reduced frequency indicated by said first frequency control signal; select logic that selects between said first and second source clock signals to provide a core clock signal based on a select signal; clock control logic that detects power conditions via at least one power sense signal, that provides said first frequency control signal according to said power conditions, and that provides said select signal, wherein said clock control logic controls said select signal to switch said core clock signal from said first PLL to said second PLL in response to said first frequency lock signal; and voltage control logic, coupled to said clock control logic, that adjusts operating voltage commensurate with frequency of said core clock signal.