Patent ID: 8164956

Claim:
A semiconductor storage device comprising: a memory cell array having a plurality of memory strings arranged therein, each of the memory strings including a plurality of electrically rewritable memory transistors and selection transistors operative to select a memory transistor, each of the plurality of memory strings comprising: a body semiconductor layer having first and second columnar portions extending in a vertical direction to a substrate, and a joining portion formed to join the lower ends of the first and second columnar portions; an electric charge storage layer formed to surround a side surface of a respective one of the columnar portions; a first conductive layer formed to surround a side surface of a respective one of the columnar portions as well as the electric charge storage layer, and functioning as a word line connected to a control electrode of a respective one of the memory transistors; a second conductive layer formed on a side surface of a respective one of the columnar portions via an insulation film, and functioning as a selection gate line connected to a control electrode of a respective one of the selection transistors; a third conductive layer arranged with a first direction taken as its longitudinal direction, connected to one end of a respective one of the memory strings, and functioning as a bit line; a fourth conductive layer arranged with the first direction taken as its longitudinal direction so as to be inserted between a plurality of the third conductive layers, connected to the other end of a respective one of the memory strings, and functioning as a source line; and a fifth conductive layer formed on a side surface of the joining portion via an insulation film, and functioning as a control electrode of a back-gate transistor, the back-gate transistor being one of the selection transistors that is formed at one of the joining portions, at least some of the memory transistors included in a first memory string being commonly connected to the first conductive layers connected to at least some of the memory transistors included in a second memory string, the first memory string being one of the memory strings that is connected to adjacent ones of the third and fourth conductive layers, the second memory string being another one of the memory strings that is connected to the same third and fourth conductive layers that the first memory string is connected to, at least one of the memory transistors or the back-gate transistor in the first memory string and at least one of the memory transistors or the back-gate transistor in the second memory string being connected to the independent first or fifth conductive layers, respectively.