Patent ID: 6861866

Claim:
A system on chip, comprising: a plurality of pins including a test clock signal input pin, a test data input pin, a test mode signal input pin, a test reset signal input pin and a test data output pin; a plurality of circuits, each with a test clock signal input terminal, a test data input terminal, a test mode signal input terminal and a test data output terminal; a controller for receiving a serial-parallel mode control signal and selection signals externally input in response to a test clock signal and outputting the input signals in response to a test reset signal input; a first selector for outputting test output data upon receiving an output from one of the test data output terminals of the plurality of circuits through the test data output pin; and a second selector for outputting the output of the first selector as test output data when the serial-parallel mode control signal indicates a parallel test mode, and for generating the test output data serially processed by the plurality of circuits by using the test input data input from the test data input pin.