Patent ID: 6894357

Claim:
A gate electrode for high-performance sub-micron CMOS device, comprising: a silicon substrate; a layer of gate dielectric deposited over the substrate, a layer of bottom gate material deposited over the layer of gate dielectric, a layer of top gate material deposited over the layer of bottom gate material, an overetch having been applied to the layer bottom gate material, creating an overhang of the layer of top gate material; LDD implants into the substrate, self-aligned with the layers of top gate material; first gate spacers created over sidewalls of said layer of bottom and top gate material, said first gate spacers comprising air, thereby reducing the dielectric constant of the first gate spacers; second gate spacers created over said first gate spacers, thereby reducing the effective dielectric constant of the first and the second gate spacers, thereby further reducing fringe coupling capacitance of the first and second gate spacers; source/drain implants into the substrate, self-aligned with the second gate spacers; and contact surface regions of the source and drain regions and the top layer of gate material.