Patent ID: 8724765

Claim:
A locking system, comprising a digital phase discrimination and conversion unit, a digital loop filter unit and a digital voltage controlled oscillation unit which are connected in turn, wherein, the digital phase discrimination and conversion unit is configured to perform a phase discrimination and conversion process to an input signal F i of an external standard source and a feedback output signal F 0 of a local thermostatic crystal oscillator which pass through a frequency division, to generate a clock signal clk and a signal sign which is used to denote a frequency size relationship between the signal F i and the signal F 0 ; the digital loop filter unit is configured to perform a filtering process to the signal clk and the signal sign, and generate a signal ahead which is used to denote that the frequency of the signal F 0 is lower than the frequency of the signal F i and a signal lag which is used to denote that the frequency of the signal F 0 is higher than the frequency of the signal F i ; the digital voltage controlled oscillation unit is configured to perform a voltage controlled oscillation process for the signal ahead and the signal lag which are generated after the filtering process to the signal clk and the signal sign, to implement a locking of the signal F 0 and the signal F i ; wherein the digital phase discrimination and conversion unit comprises a digital stagger phase discriminator and a conversion module, wherein, the digital stagger phase discriminator is configured to perform a phase discrimination process to the signal F i and the signal F 0 , and generate a pulse signal error which is used to denote a phase relationship between the signal F i and the signal F 0 ; the conversion module is configured to calculate a pulse width of the pulse signal error according to a counting signal count, and generate the signal sign which denotes the frequency size relationship between the signal F i and the signal F 0 and a signal equ_nequ which denotes whether neighboring pulse widths are equal, and perform an AND process to the signal equ_nequ and the signal F i to generate the clock signal clk; wherein the counting signal count is implemented by way of a time interval calculation, and the signal sign denotes the frequency size relationship between the signal F i and the signal F 0 by a size relationship of neighboring pulse widths in the pulse signal error.