Patent ID: 7600078

Claim:
A processor socket comprising: at least one processor core to generate a read request; a coherent path to receive the read request and to determine coherency of the read request and route the read request to a memory controller of the processor core, the coherent path comprising a router, and a coherence controller coupled to the router, wherein the router is to route the read request to a different processor socket or the coherence controller based on an address of the read request; and a bypass path to provide a speculative request corresponding to the read request to the memory controller independently of the coherent path, the bypass path comprising a speculative router, and speculative management logic to provide the speculative request to the memory controller if a transaction level of the memory controller is less than a threshold and to drop the speculative request if the transaction level is greater than the threshold, wherein the speculative router is to route the speculative request to a different processor socket or the speculative management logic based on an address of the speculative request, wherein the speculative management logic includes a transaction identifier selector to receive an incoming prefetch transaction, allocate a read-write buffer and generate a valid prefetch request, a prefetch target address decoder to receive a system address and generate a speculative prefetch address corresponding to the valid prefetch request, and a speculative request buffer to receive the valid prefetch request and the speculative prefetch address and to provide a speculative request to the memory controller, and a bypass path to provide actual memory requests to the memory controller.