Patent ID: 7732849

Claim:
A dynamic random access memory (DRAM), comprising: a substrate, having a trench and a deep trench located on one side of the trench; a vertical transistor, a portion of which being disposed in the trench and another portion disposed over the substrate, the vertical transistor comprising: a gate structure, disposed in the trench and located over the substrate; a first doped region, disposed in the substrate on sidewalls and bottom of the trench; and a second doped region, disposed in the substrate on top of the trench, wherein the first doped region and the second doped region have opposite conductivity from a channel region of the vertical transistor; a deep trench capacitor, disposed in the deep trench, comprising: a bottom electrode, disposed in the substrate on a bottom of the deep trench; a capacitor dielectric layer, disposed on sidewalls and the bottom of the deep trench; and an upper electrode, disposed in the deep trench and located on the capacitor dielectric layer; and a buried strap, disposed in the substrate below the vertical transistor, adjoining to the first doped region and the upper electrode.