Patent ID: 8476754

Claim:
A wiring substrate comprising: an insulating layer having an insulating layer surface which defines an outer surface of the wiring substrate, the insulating layer surface defining a surface of the wiring substrate; first electrode pads embedded in the insulating layer, each of the first electrode pads having a first exposed surface and a first opposite surface opposite to the first exposed surface, the first exposed surfaces being exposed from the insulating layer at the insulating layer surface, the first electrode pads configured to have a chip mounted on the first exposed surfaces, each of the first electrode pads is provided within a different first electrode pad opening defined in the insulating layer, and all of the first exposed surfaces are recessed relative to the insulating layer surface; an electrode seal ring embedded in the insulating layer, the electrode seal ring having a second exposed surface and a second opposite surface opposite to the second exposed surface, the second exposed surface being exposed from the insulating layer at the insulating layer surface, the electrode seal ring having a frame shape and surrounding the first electrode pads, the electrode seal ring provided within a frame-shaped electrode seal ring opening defined in the insulating layer, the second exposed surface is flush with the insulating layer surface, and the electrode seal ring configured to have a lid bonded to the second exposed surface; first vias provided in the insulating layer, each of the first vias connected to a corresponding one of the first opposite surfaces of the first electrode pads; and a second via provided in the insulating layer, the second via connected to the second opposite surface of the electrode seal ring, wherein there is a level difference between the first exposed surfaces and the second exposed surface relative to the insulating layer surface, a width of each first exposed surface is less than a width of the second exposed surface, and a width of each first electrode pad opening at the insulating layer surface is less than a width of the electrode seal ring opening at the insulating layer surface.