Patent ID: 8693274

Claim:
A sensing circuit comprising: a data column including an output voltage node, a memory cell, a first PMOS transistor that is diode-connected, and a first differential threshold NMOS transistor having a drain connected to a drain of the first PMOS transistor to form the output voltage node and a source connected to a first node; and a first memory column comprising a second differential threshold NMOS transistor having a drain connected to the first node; and a second memory column connected to the first node in parallel with the first memory column, wherein each memory column includes a differential threshold MOS transistor; wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage; wherein one or more of the differential threshold transistors comprises: a substrate of semiconductor material of a first conductivity type; a first region and a second region in the substrate, wherein the first and second regions are of a second conductivity type and spaced apart from each other defining a channel region therebetween; an insulating layer disposed over the channel region of the substrate, wherein the insulating layer comprises opposed insulating portions including a first insulating portion adjacent the first region and a second insulating portion adjacent the second region; and a gate portion above the insulating layer; wherein each insulating portion characterizes a threshold voltage between the gate and the first region or the second region adjacent each insulating portion; and wherein the first insulating portion is fabricated with varying dimension including a first thickness different than a second thickness of the second insulating portion to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed insulating portion.