Patent ID: 8648423

Claim:
A semiconductor device comprising: a substrate that includes an isolation region that defines a first active region and a second active region; a bit line contact plug disposed on the first active region of the substrate; a storage contact pad disposed on the second active region of the substrate; an interlayer insulating layer disposed on the substrate, the interlayer insulating layer exposing the bit line contact plug and the storage contact pad; a first bit line structure disposed on the interlayer insulating layer, the first bit line structure including a first bit line conductive pattern and first bit line spacers that cover sidewalls of the first bit line conductive pattern; a second bit line structure that is disposed on the bit line contact plug and that is substantially parallel to the first bit line structure, the second bit line structure including a second bit line conductive pattern that includes sidewalls that are covered by second bit line spacers; and a storage contact plug disposed on the storage contact pad, the storage contact plug interposed between the first bit line spacers and the second bit line spacers, wherein the second bit line spacers expand between the bit line contact plug and the storage contact pad.