Patent ID: 7085193

Claim:
A method of switching modes of a memory system between a normal mode and a synchronous mode, comprising: supplying a clock signal, a first control signal, a second control signal, and a third control signal to the memory system; setting the mode to be the normal mode in a case in which the second control signal is of a first level, and setting the mode to be the synchronous mode in a case in which the second control signal is of a second level; fetching in an address signal in response to a transition of one of the first control signal and the third control signal at least; designating an address of a memory cell in a memory cell array after the address signal is asserted; inputting/outputting data after a predetermined time has passed since the address of the memory cell in the memory cell array is designated in the normal mode; designating the address of the memory cell in the memory cell array after the address signal is asserted, with a first clock when the second control signal is changed in level as a starting point, when the mode is set to be the synchronous mode; and obtaining a plurality of output data output from the memory cell array in synchronism with the clock signal after the address of the memory cell in the memory cell array is designated in the synchronous mode after the address signal is asserted, output of the data beginning after a number of clock cycles (latency N, N being a positive integer ≧2) of the clock signals, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output in the synchronous mode.