Patent ID: 8315090

Claim:
A non-volatile memory array comprising: a plurality of word-lines; and a plurality of columns; one of said plurality of columns further comprising: a bistable regenerative circuit having a first terminal coupled to a first signal line, a second terminal coupled to a second signal line, a third terminal coupled to a third signal line, and a fourth terminal coupled to a fourth signal line; a non-volatile memory cell having a first current carrying terminal coupled to said first signal line, a second current carrying terminal coupled to said second signal line and a control terminal coupled to one of said plurality of word-lines; a first transistor having a first current carrying terminal coupled to said first terminal of said bistable regenerative circuit, and a second current carrying terminal coupled to a fifth signal line; and, a second transistor having a first current carrying terminal coupled to said second terminal of said bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line; wherein gate terminals of said first and second transistors are coupled to a seventh signal line.