Patent ID: 8190864

Claim:
A multithreaded multicore processor comprising: an input/output advanced programmable interrupt controller (I/O APIC); and a plurality of processor cores, each including: one of a plurality of multithreaded processors configured to execute a plurality of threads; and one of a plurality of core APICs, wherein each core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs corresponding to one of the threads of the plurality of threads of the multithreaded processor, a plurality of logical destination registers (LDRs), each of the plurality of LDRs corresponding one of the threads of the plurality of threads of the multithreaded processor, the one of a plurality of core APICs coupled to the one of the plurality of multithreaded processors and to the I/O APIC, and configured to receive an interrupt request and to route the interrupt request to a lowest priority thread of the one of the plurality of multithreaded processors.