Patent ID: 7656224

Claim:
An apparatus comprising: a first MOS transistor that is coupled to an output node at its drain; a voltage divider that is coupled to the output node; an error amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the voltage divider, and wherein the second input terminal receives a reference voltage; a buffer having: a first current source; a current mirror that is coupled to the first current source; a second current source that is coupled to the gate of the first MOS transistor; a second MOS transistor that is coupled between the second current source and the current mirror and that is coupled to the output terminal of the error amplifier at its gate; a third MOS transistor that coupled in parallel to the first current source and that is coupled to the gate of the first MOS transistor at its gate; and a fourth MOS transistor that is coupled in parallel to the second current source and that is coupled to the gate of the first MOS transistor at its gate.