Patent ID: 8874982

Claim:
An integrated circuit comprising: A. functional logic; B. test circuitry having a test clock in lead, a test mode select in lead, a test data in lead, and a test data out lead, the test circuitry including a test access port controller, which includes a state machine, that is connected to the test clock in lead and the test mode select in lead and that has control outputs, an instruction register having an input connected to the test data in lead, an output coupled to the test data out lead and a control input connected to the control outputs of the controller, and a data register having a serial input connected to the test data in lead, a serial output coupled to the test data out lead, and inputs and outputs coupled to the functional logic; and C. adapter circuitry including: i. a first set of leads including: a. a clock input lead, b. a mode input and output lead, c. a test in data lead, and d. a test out data lead, ii. a second set of leads having: a. a test clock out lead carrying a test clock signal coupled to the test clock in lead of the test circuitry, b. a test mode select out lead carrying a test mode select signal coupled to the test mode select in lead of the test circuitry, c. a test in data output lead carrying a test in data signal coupled to the test data in lead of the test circuitry, and d. a test out data input lead carrying a test out data signal coupled to the test data out lead of the test circuitry; and iii. a link control register coupled to the first set of leads, the link control register having bit locations for: a. extended command pages, b. link identification numbers, c. clock controls, d. power controls, e. TAP resets, and f. normal and flattened scan paths.