Patent ID: 8922243

Claim:
An integrated circuit (IC) package comprising: a die-stacked memory device comprising: a set of one or more stacked memory dies implementing memory cell circuitry; a set of one or more logic dies electrically coupled to the memory cell circuitry, the set of one or more logic dies configured to couple to at least one device external to the die-stacked memory device and comprising a reconfigurable logic device and a memory controller, wherein the reconfigurable logic device to perform at least one data manipulation operation according to a programmed logic configuration of the reconfigurable logic device; and wherein the set of one or more stacked memory dies and the set of one or more logic dies are disposed in one of: a stacked configuration whereby the set of one or more logic dies is connected to the set of one or more stacked memory dies via a set of through silicon vias; and a side-split arrangement whereby the set of one or more logic dies is connected to the set of one or more stacked memory dies via an interposer.