Patent ID: 7756197

Claim:
A transmitter for a transceiver comprising: a test control circuit for the transmitter of the transceiver, wherein the test control circuit is at least partially responsive to one or more signals in a test access port, where the test control circuit permits control of the transmitter between at least a normal mode and a first built-in self test mode for the transmitter; and a finite impulse response (FIR) filter circuit of the transmitter of the transceiver, the FIR filter circuit having a plurality of data paths including at least a primary data path and a first delayed data path, where a gain coefficient G 1 for the primary data path is configured to vary so that in a normal mode, the gain coefficient G 1 is non-zero and in the first built-in self test mode, the gain coefficient G 1 is zero; wherein the first built-in self test mode is one of a plurality of built-in self test modes, wherein in each built-in self test mode of the plurality, a gain coefficient for only one particular delay path corresponding to the test mode is set to a non-zero value, and all other gain coefficients for other data paths of the FIR filter circuit are set to zero, wherein the plurality of built-in self test modes covers each of the data paths of the FIR filter circuit such that each data path of the FIR filter circuit can be individually verified.