Patent ID: 7380197

Claim:
A circuit for detecting corruption of data using an error correcting code (ECC), comprising: an ECC checker adapted to generate a remainder of an ECC check of the data and an ECC value generated from an uncorrupted version of the data; a memory arrangement coupled to the ECC checker, the memory arrangement configured with a set of values and arranged to receive a first portion of the remainder at a first address port and a second portion of the remainder at a second address port, wherein the memory arrangement is adapted to output a first value of the set responsive to a value of the first portion and output a second value of the set responsive to a value of the second portion; and a detection circuit coupled to the memory arrangement and adapted to generate an error indication in response to the first and second values, wherein the error indication includes a single-bit-error indicator that indicates whether a single bit of the data is incorrect.