Patent ID: 7877429

Claim:
An FIR filter apparatus, comprising: an input responsive to an input signal; an FIR filter comprising a first plurality of filter stages serially arranged; a first delay circuit having a first time delay coupled between two of the plurality of filter stages; first memory connected to the first delay circuit, the first memory configured to provide a first coefficient corresponding to the first delay; a second delay circuit having a second time delay coupled between another two of the plurality of filter stages, wherein the first time delay is different than the second time delay; second memory connected to the second delay circuit, the second memory configured to provide a second coefficient corresponding to the second delay; and a shift register connected to the first memory and the second memory, the first memory configured to store the first coefficient in response to a value received from the shift register in a first cycle, the second memory configured to store the second coefficient in response to the value received from the shift register in a second cycle subsequent to the first cycle.