Patent ID: 7633571

Claim:
A thin-film transistor, comprising: a substrate; a semiconductor layer in which a source, a drain, and a channel are formed; and a back-gate that is formed between said substrate and said semiconductor layer having interposed insulating layers and to which a prescribed voltage is applied; wherein, when: t is a film thickness of said semiconductor layer, f(t) is the ratio of occurrence of regions that is the ratio of channel width W(t) of regions having film thickness t to the channel width of the entire region Wtotal in said semiconductor layer, Vb is the voltage that is applied to said back-gate, I D (Vb, t) is a drain current that flows under conditions in which the film thickness of said semiconductor layer is t and the voltage that is applied to said back-gate is Vb, and Icrit is an OFF-leak current limit, which is the drain current that flows when said thin-film transistor is turned OFF, said ratio of occurrence f(t) of said semiconductor layer satisfies a relation: f ( t )< I crit / W total .I D ( V b , t )) wherein Icrit is 5.00E-12 A.