Patent ID: 8685853

Claim:
A method of manufacturing integrated circuit devices comprising: providing a semiconductor substrate with a surface region, the surface region comprising one or more layers overlying the semiconductor substrate; forming a copper layer overlying the surface region; forming a dielectric layer overlying the copper layer; forming a photoresist layer overlying the dielectric layer; exposing a portion of the photoresist layer by placing a reticle over the photoresist layer and transmitting light from an exposing source to the photoresist layer, the reticle possessing at least two regions with different transmission rates, a first region of the reticle being used to create a via etch pattern in the photoresist layer and a second region of the reticle being used to create a trench etch pattern in the photoresist layer; developing the photoresist layer, whereby a first portion of the photoresist layer is removed to expose a portion of the dielectric layer and a thickness of the second portion of the photoresist layer is formed; and etching the photoresist layer and the dielectric layer in a single step to create a dual damascene pattern in the dielectric layer, wherein the ratio of a thickness of the first portion of the photoresist layer and a thickness of the dielectric layer is 1:1 and the ratio of the etch rate of the photoresist layer to the dielectric layer is 1:1.