Patent ID: 8004878

Claim:
A semiconductor device comprising: an SRAM cell array; a ring oscillator formed with a plurality of cells provided on the SRAM cell array, wherein the cells used to form the ring oscillator are connected to each another through a bit line wiring provided on the SRAM cell array; wherein the ring oscillator includes a plurality of test cells consisting of six transistors respectively that are different from those of each bit cell, wherein among the plurality of test cells, those disposed on the same bit line wiring of the SRAM cell array are connected to each another through the same bit line wiring; wherein each of the test cells includes: a first access transistor that inputs a first input signal and controls whether to output the first input signal according to a second input signal; a second access transistor that inputs the second input signal and controls whether to output the second input signal according to the first input signal; a first inverter that inputs an output of the second access transistor, inverts the inputted signal, and outputs a first output signal; a second inverter that inputs an output of the first access transistor or the first output signal, inverts the inputted signal, and outputs a second output signal to be inputted to the first inverter; wherein the plurality of test cells are disposed serially, and wherein among the serially disposed test cells, the test cell in the first step replaces the output of the test cell in the final step so as to input the first output signal as the second input signal and the second output signal as the first input signal respectively.