Patent ID: 6978334

Claim:
A serial bus data control device for use with communication equipment to receive packets sent through a serial bus and each having a header, actual data positioned subsequently to said header and a footer positioned subsequently to said actual data, comprising: a preprocessing section to recognize packets received through said serial bus and to divide said header, actual data and footer contained in each of said recognized packets into pieces of unit length data each having a predetermined data length; and a storing section, coupled to said preprocessing section, to temporarily store said headers, actual data, and footers contained in packets recognized by said preprocessing section, said headers, actual data, and footers of a plurality of packets being stored in said storing section simultaneously; wherein said preprocessing section is provided with an address control circuit to assign addressing in said storing section for said storing headings, actual data, and footer footers, wherein said storage section is partitioned into a first data area to store the headers and footers of received packets and a second data area to store the actual data in the received packets, aid wherein the first data area has a first range of consecutive addresses beginning with a first start address for simultaneously storing said headers and footers of more than one packet, and a second range of consecutive time addresses beginning with a second start address for simultaneously storing said actual data of more than one packet simultaneously.