Patent ID: 7900075

Claim:
An apparatus including a computer system, comprising: system control circuitry to provide one or more processor control signals and at least one of a power management signal and a power management instruction; memory to store and provide a plurality of data and a plurality of data instructions for data processing; a display device to provide, in accordance with said at least one of a power management signal and a power management instruction, an enabled visual display corresponding to a plurality of display data, and a disabled visual display; interface circuitry, coupled to said display device, to convey one or more user commands and said plurality of display data; and integrated processor circuitry with lower and higher power operational modes, and coupled at least in part to said system control circuitry, said memory and said interface circuitry, to receive said one or more processor control signals, said at least one of a power management signal and a power management instruction, said plurality of data, said plurality of data instructions and said one or more user commands, to process said plurality of data and said plurality of data instructions and provide said plurality of display data, wherein said integrated processor circuitry includes a plurality of pipelined subcircuits at least a portion of which has active and inactive operating states corresponding to said lower and higher power operational modes, respectively, in accordance with said one or more processor control signals and said at least one of a power management signal and a power management instruction.