Patent ID: 7571338

Claim:
Apparatus comprising: buffer circuitry for receiving data to be processed by the electronic circuitry, the buffer circuitry being configured to input the received data using a first clock signal associated with a first clock domain and to output the received data using a second clock signal associated with a second clock domain, wherein the buffering of the data is associated with a buffering delay; counting circuitry for receiving at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry and for receiving at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry, wherein a count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay; and control circuitry for performing a control operation based on the accumulated count value, wherein the accumulated count value corresponding to the buffering delay represents a phase difference between the first and second clock signals, and the control circuitry is configured to compensate for the phase difference.