Patent ID: 7607055

Claim:
A semiconductor memory device comprising: a plurality of pads; at least one first built in self test (BIST) circuit configured to generate first test pattern data; and at least one second BIST circuit configured to receive the first test pattern data as received first test pattern data and compare the received first test pattern data to second test pattern data; wherein: each first BIST circuit and each second BIST circuit is coupled to a pad different from a pad coupled to another first BIST circuit or second BIST circuit; each first BIST circuit is configured to output the first test pattern data through the pad corresponding to that first BIST circuit; and each second BIST circuit is configured to receive the first test pattern data through the pad corresponding to that second BIST circuit; and wherein: each second BIST circuit is further configured to generate third test pattern data and output the third test pattern data; and each first BIST circuit is further configured to receive the third test pattern data as received third test pattern data and compare the received third test pattern data to fourth test pattern data.