Patent ID: 8510364

Claim:
A systolic array in an integrated circuit for matrix triangularization and back-substitution, comprising: boundary cells; internal cells coupled to the boundary cells; the boundary cells and the internal cells each configurable for a triangularization mode and a back-substitution mode, wherein the boundary cells and the internal cells are configurable for a selective one of the triangularization mode and the back-substitution mode in response to a mode signal input that selects one of the triangularization mode and the back-substitution mode; the boundary cells coupled to have respective first residues from a triangularization of an input matrix as part of a completion of the triangularization mode and to provide inverted residues respectively associated with the first residues; and the internal cells coupled to have respective second residues from the completion of the triangularization; wherein, for the back-substitution mode: the boundary cells are coupled to receive respective first inputs; the boundary cells are further coupled to respectively multiply the inverted residues thereof with the first inputs to provide first outputs; first multipliers of the boundary cells are used in the triangularization mode being coupled for reuse for multiplications to provide the first outputs; the internal cells are coupled to receive second inputs respectively associated row-wise with the first outputs; the internal cells are further coupled to receive respective third inputs; the internal cells are further coupled to respectively multiply the second inputs with the second residues to provide interim results; the internal cells are further coupled to respectively add the interim results with the third inputs to provide second outputs; and second multipliers and adders of the internal cells used in the triangularization mode are respectively coupled for reuse for multiplications and additions to provide the second outputs.