Patent ID: 8341588

Claim:
A method comprising: inspecting, by a computer processor of a computing device, first structures within a first semiconductor device; determining based on said inspecting said first structures, that said first semiconductor device requires a first engineering change order (ECO) in order to modify existing circuitry within said first semiconductor device to repair a design problem or implement new internal connections; determining a first additional structure layer required to implement said first ECO; selecting, based on a parasitic capacitance associated with said first semiconductor device, a first insertion point location within said first semiconductor device for inserting said first additional structure layer, wherein said selecting said first insertion point location comprises: identifying an ECO structure set, wherein said ECO structure set comprises all electrical structures within said first semiconductor device that require modification in accordance with said first ECO; inspecting layers of said first semiconductor device that comprise at least one structure of said ECO structure set to determine subsets of structures located below a selected layer of said layers; and selecting based on said inspecting, an insertion layer of said layers that is located closest to a top surface of said first semiconductor device with respect to all other layers of said layers, wherein said first insertion point is located at said insertion layer; associating said first insertion point location with a second insertion point location within a design for a second semiconductor device, wherein said second semiconductor device is associated with said first semiconductor device; and generating said second semiconductor device in accordance with said first ECO, wherein said second semiconductor device comprises second structures, wherein said second structures comprise same structures as said first structures, wherein said second structures are formed in locations within said second semiconductor device that are associated with locations in said first semiconductor device comprising said first structures, wherein said second semiconductor device comprises said first additional structure layer configured to repair said design problem or implement said new internal connections, wherein said first additional structure layer comprises first electrically conductive structures formed within a first insulator layer, wherein said first additional structure layer is located within said second insertion point location, and wherein said first electrically conductive structures are electrically connected to a first group of structures of said second structures.