Patent ID: RE39529

Claim:
A graphic processing apparatus comprising: memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data; data processing means for specifying a row address in said memory means for retrieval of data from the memory locations at the different column addresses within the specified row of memory locations and processing of the retrieved data to generate graphic signals; memory control means; a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m; said memory control means including storage means for temporarily storing data received serially on said memory data bus from memory locations at different column addresses of the memory means row corresponding with the specified row address, and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof to generate graphic signals.