Patent ID: 7525198

Claim:
A semiconductor device having a substrate and a plurality of wiring layers including first, second, third, and fourth wiring layers, comprising: a plurality of first source wirings formed in parallel with each other on the first wiring layer; a plurality of second source wirings formed in a direction intersecting at a right angle with the first source wirings on the second wiring layer, the second wiring layer being located nearer the substrate than the first wiring layer; a plurality of third source wirings formed on the third wiring layer, the third layer being located nearer the substrate than the second wiring layer; a plurality of fourth source wirings formed on the fourth wiring layer, the fourth wiring layer being located nearer the substrate than the third wiring layer; a first contact that connects one of the first source wirings and one of the second source wirings with each other at a part where the first source wiring and the second source wiring intersect with each other; a second contact that connects one of the third source wirings and at least one of the first source wirings and the second source wirings with each other; and a third contact that connects one of the third source wirings and one of the fourth source wirings with each other; wherein the number of second contacts is less than the number of third contacts, and a plurality of signal wiring layers are included between the second wiring layer and the third wiring layer, and a plurality of signal wiring layers are included between the third wiring layer and the fourth wiring layer.