Patent ID: 8212590

Claim:
A mixed-voltage input/output (I/O) buffer, comprising: an input buffer circuit, comprising: a first inverter for inverting an input signal to generate a first control signal; a first voltage level limiting circuit for limiting the voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter; a first voltage level pull-up circuit for pulling up the voltage level of the input signal inputted into the first inverter; an input stage circuit for receiving the first control signal to generate a corresponding digital signal inputted into a core circuit; and a logic calibration circuit for calibrating the voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level, the logic level calibration circuit comprising: a second inverter for inverting the input signal to generate a second control signal; and a pull-down calibration circuit controlled by the input signal and the second control signal and pulling down the voltage level of the first control signal when the first inverter mis-operates due to the input signal having the low voltage level.