Patent ID: 7539913

Claim:
A circuit for testing digital logic circuit modules of an integrated circuit chip, the circuit comprising: a storage device for storing a first N-bit group, a second N-bit group, a third N-bit group and a fourth N-bit group of a test pattern separately according to a loading signal and an address selection signal; a first multiplexing module coupled to the storage device and a first digital logic circuit module, for parallel transmitting the first N-bit group, the second N-bit group, the third N-bit group and the fourth N-bit group which will be received and executed by the first digital logic circuit module to parallel generate a first M-bit group, a second M-bit group and a third M-bit group; and a selection device coupled to the first digital logic circuit module for sequentially selecting one of the first M-bit group, the second M-bit group and the third M-bit group to output a first test result according to the address selection signal; wherein each one of the first N-bit group, the second N-bit group, the third N-bit group and the fourth N-bit group of the test pattern has N bits and each one of the first M-bit group, the second M-bit group and the third M-bit group has M bits.