Patent ID: 7060512

Claim:
A method for fabricating a semiconductor memory module on a multi-layer printed circuit board comprising the steps of: mounting a plurality of primary memory parts on said printed circuit board; testing said primary memory parts to determine Input/Output (I/O) line functionality; mounting pre-tested secondary memory parts whose operable I/O lines match failed I/O lines of said primary memory parts; positioning I/O line patching elements on said printed circuit board adjacent to said primary and secondary memory parts; matching read/write control signal lines for each respective I/O line of one of said primary memory parts with a like I/O line of an individually associated secondary memory part; patching any non-operable I/O line of a primary memory part by replacing it with a fully-operable I/O line of its associated backup memory part by selectively connecting and disconnecting patching elements corresponding to a functional I/O line of said secondary memory part and a non-functional I/O line of said primary memory part.