Patent ID: 6888399

Claim:
A semiconductor device equipped with a voltage step-up circuit, said semiconductor device comprising a switch for supplying a power supply voltage to said voltage step-up circuit after being turned on by an enable signal, and said voltage step-up circuit comprising multiple charge pump units connected in series, each charge pump unit consisting of a MOS transistor and a capacitor having one end connected to the input or output end of said MOS transistor and another end connected to a clock line supplying a clock, said multiple charge pump units adapted to step up a supply voltage in response to said clock, wherein said MOS transistor is a well separation type MOS transistor having a second-conduction type well formed in a first-conduction type substrate; a first-conduction type well formed in said second-conduction type well; a second-conduction type source region formed in said first-conduction type well; a second-conduction type drain region formed away from said source region and separated by a channel region; and a gate formed above, and separated by an insulation layer from, said channel region, wherein said second-conduction type well is connected to a high potential so that opposite biases are established between said second-conduction type well and said first-conductive type substrate and between said second-conduction type well and said first-conduction type well, wherein said well separation type MOS transistor consists of a main well separation type MOS transistor and a well separation type auxiliary MOS transistor; said capacitor consists of a main capacitor and an auxiliary capacitor; the drain of said main well separation type MOS transistor is connected to the gate of said well separation type auxiliary MOS transistor; the gate of said main well separation type MOS transistor is connected to the drain of said well separation type auxiliary MOS transistor; the source of said main well separation type MOS transistor is connected to the source of said well separation type auxiliary MOS transistor; said main capacitor is connected between said source of said main well separation type MOS transistor and a four-phase clock line; and said auxiliary capacitor is connected between said gate of said main well separation type MOS transistor and said four-phase clock line.