Patent ID: 8832616

Claim:
A computer-implemented method for performing voltage drop and surge analysis of a circuit with multi-phase sequential elements, comprising the computer implemented steps of: using timing analysis for multi-phase sequential circuit to generate critical path; and verifying the timing of a specified path by re-evaluating the new path delay and new timing constraint including new clock skew, new set up time, new hold time and new clock to output delay for sequential element in consideration of voltage drop effect for each gate along the critical path for multi-phase sequential circuit; and choosing the set of all the gates with their switching overlapping with switching for each gate along the critical path by considering functional dependence and signal propagation for multi-phase sequential circuit with non-uniform timing constraint in calculating voltage drop effect for the said gate along the said critical path for the said multi-phase sequential circuit; and pre-characterizing the timing library including power current and ground currents.