Patent ID: 8378726

Claim:
A clock signal duty correction circuit comprising: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; a differential buffer unit configured to generate the duty correction clock signal, capable of adjusting rising time or falling time, in response to the first control signal and the second control signal, and a control code generation unit configured to detect a duty of the clock signal by using the duty correction clock signal and generate the code signal corresponding to the detected duty of the clock signal, wherein the control code generation unit comprises: a phase separator configured to separate a phase of the duty correction clock signal and generate a first phase clock signal and a second phase clock signal; a duty detector configured to generate a duty detection signal by using the first phase clock signal and the second phase clock signal; and a counter configured to vary the code signal in response to the duty detection signal.