Patent ID: 8331174

Claim:
A semiconductor memory device comprising: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according to a determination as to whether the repair address signal is to be used; and a cell line decoding unit configured to select one of a normal cell region and a redundancy cell region according to the determination and select one of a plurality of local cell lines provided in the selected cell region in response to the line choice address signal, wherein the line choice address generation unit comprises: an address encoding section configured to encode the repair address signal; a repair address use judgment section configured to determine a value of a repair address use judgment signal in response to an activation of at least one bit among the respective bits of the repair address signal; and an address combination section configured to combine the first address signal and an output signal of the address encoding section according to the repair address use judgment signal and generate the line choice address signal.