Patent ID: 7619248

Claim:
An electronic device, comprising: a substrate having an electrically inert surface; a lightly doped semiconductor layer on the electrically inert surface; a dielectric film on portions of said lightly doped semiconductor layer; a gate metal layer on said dielectric film, the gate metal layer having a peripheral border; and source and drain terminals comprising a heavily doped semiconductor layer on a surface of said lightly doped semiconductor layer not covered by said dielectric film and opposite to an interface of said lightly doped semiconductor layer with said electrically inert surface, wherein region(s) of said heavily doped semiconductor layer are in an amorphous state and said heavily doped semiconductor layer contains a substantially uniformly distributed dopant throughout substantially the entire thickness of the region(s) of said heavily doped semiconductor layer in an amorphous state, each of said source and drain terminals having a border (i) closest to said gate metal layer and (ii) defined by the thickness of the heavily doped semiconductor layer, that is substantially aligned with a closest portion of the peripheral border of said gate metal layer.