Patent ID: 8410585

Claim:
A semiconductor package comprising: a chip pad; a plurality of leads each including an inner end adjacent to the chip pad, an opposite outer end, a generally planar first surface which extends to both the inner and outer ends, a generally planar second surface opposite the first surface, and a generally planar third surface which is opposite the first surface and extends to the outer end, the third surface further being recessed relative to the second surface and extending completely between the second surface and the outer end such that no portion of the second surface extends between the third surface and the outer end and the second surface is separated from the outer end by the third surface to reduce burr the formation on the second surface; a semiconductor chip mounted on the first surface of the chip pad and in an electrical connection with the first surface of at least some of the leads; and a package body of a hardened encapsulant material over the chip, the package body defining a first exterior surface, a second exterior surface which is opposite the first exterior surface, a first exterior first side surface which extends between the first and second exterior surfaces, and at second exterior second side surface which extends to the first exterior surface; wherein the third surface of each of the leads is covered by the encapsulant material to facilitate the locking of the leads thereto, the second surface of each of the leads and the second surface of the chip pad are exposed in a plane of the first exterior surface of the package body, and a portion of the first surface of each of the leads which begins at the outer end is exposed in a plane of the second exterior surface of the package body such that the exposed portion of the first surface protrudes from the second exterior side surface.