Patent ID: 7231507

Claim:
Apparatus for processing data, said apparatus comprising: a register bank having one or more registers operable to hold respective data values; a data access circuit operable to perform data access operations transferring one or more data values between said apparatus and addressed memory locations within a memory circuit; and an instruction decoder responsive to data access program instructions to control said data access circuit to perform respective data access operations, each of said data access program instructions including an address offset field that specifies an offset value and including a base register field that specifies a base address register within said register bank and specifying a manipulation to be performed upon said offset value and a base address value held in said base address register to form a memory address value to be accessed within said memory circuit upon execution of said data access program instruction, wherein: said data access program instructions have: (i) a first form including an address offset field having a first address offset field length; and (ii) a second form including an address offset field having a second address offset field length, said first address offset field length being greater than said second address offset field length and said first form being capable of specifying a lesser number of possible manipulations to be performed upon said base address value and said offset value than said second form; said apparatus can operate in a plurality of modes at least one of which is privileged and at least one of which is unprivileged, data accesses being marked either privileged or unprivileged to allow code to be given different levels of access to said memory circuit; and at least one form of said manipulation allows a memory access to be formed to be unprivileged regardless of the current mode.