Patent ID: 8767437

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array having a first line, a second line, and a memory cell arranged therein, the memory cell being connected between the first line and the second line and including a variable resistance element; a control circuit configured to apply, via the first line and the second line, a voltage required in operation of the memory cell; a current limiting circuit connected to the first line and configured to limit a current flowing in the memory cell to a certain limit value; and a current suppression circuit configured connectable to the second line and configured to suppress a current flowing in the second line according to a kind of operation on the memory cell, wherein the current suppression circuit comprises: a first current path electrically connecting a ground terminal and the second line and having a first resistance value; a second current path electrically connecting the ground terminal and the second line and having a second resistance value; and a switch circuit configured to selectively switch the first current path and the second current path to a conductive state.