Patent ID: 8378432

Claim:
A method, comprising: forming a first spacer element on at least a first portion of sidewalls of a gate stack, said gate stack formed on a semiconductor layer and comprising a gate insulation layer comprising a high-k dielectric material, a gate electrode material and a cap layer formed above said gate electrode material; forming a semiconductor alloy in said semiconductor layer laterally offset from said gate stack on the basis of said first spacer element, wherein forming said semiconductor alloy comprises forming an etch mask, forming said first spacer element on the basis of said etch mask and forming cavities in said semiconductor layer using said etch mask; forming a second spacer element on said first spacer element, said second spacer element contacting a second portion of said sidewalls of said gate stack; removing said cap layer selectively to said second spacer element and said semiconductor alloy; and forming drain and source regions in at least a portion of said semiconductor alloy on the basis of said first spacer element.