Patent ID: 7987384

Claim:
A method for handling errors in a cache memory without processor core recovery, comprising: receiving a fetch request for data from a processor; simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor, the fetched data retrieved from a higher-level cache in response to the fetch request and received into a low level cache of the processor, wherein the parity matching the parity of the fetched data prevents the processor from initiating a recovery operation; upon determining that the fetched data failed an error check, the failure indicating the fetched data is corrupted: requesting an execution pipeline of the processor to discontinue processing and flush its contents via a signal; and initiating a clean up sequence, comprising: sending invalidation requests to the low level cache causing the low level cache to remove lines associated with the corrupted data; and requesting the execution pipeline to restart; wherein requesting the execution pipeline to restart causes the execution pipeline to access a copy of the requested data from a higher-level storage location.