Patent ID: 8138105

Claim:
In an overall multi-step technique for processing a semiconductor wafer which includes a pair of opposing major surfaces one of which is a front side surface, being a device side, and the other one of which is a back side surface, a method that is performed as part of annealing said wafer in a process chamber as an intermediate part of the overall multi-step technique, said method comprising: exposing at least one of said major surfaces of the wafer to a pulse of energy having a duration of less than 100 milliseconds at any given exposed location on the major surface in said process chamber in a way that at least contributes to annealing the front side surface of the wafer and which produces a first stress response of the wafer; and subjecting the wafer to an additional source of stress to produce an overall modified stress response that compensates for said first stress response such that a modified probability of survivability of the wafer is enhanced as compared to an unmodified survivability that would otherwise be presented by the wafer resulting from only the first stress response.