Patent ID: 7553725

Claim:
A method of fabricating a nonvolatile memory cell, comprising: forming a preliminary gate pattern on a semiconductor substrate; forming an inter-gate insulating layer pattern and a word line pattern which are stacked on the preliminary gate pattern; forming first sacrificial spacers on both sidewalls of the word line pattern and on the preliminary gate pattern, thereby exposing a portion of the preliminary gate pattern; etching the exposed portion of the preliminary gate pattern using the first sacrificial spacers and the word line pattern as etch masks to form a gate pattern; removing the first sacrificial spacers to expose the portion of the gate pattern underneath where the first sacrificial spacers were positioned prior to removal; selectively forming first and second hard mask patterns on both ends of the exposed gate pattern respectively, thereby leaving the portions of the gate pattern located between the word line pattern and the first and second hard mask patterns exposed, and wherein the first and second hard mask patterns being formed substantially parallel to the word line pattern; and etching the portions of the gate pattern that are not covered by the first and second hard mask patterns using the word line pattern and the hard mask patterns as etch masks to form a floating gate under the world line pattern; and a source selection line and drain selection line under the first hard mask pattern and the second hard mask pattern, respectively, wherein the floating gate, the inter-gate insulating layer pattern and the word line pattern constitute a cell gate pattern.