Patent ID: 7355449

Claim:
Serial data transmitter circuitry on a PLD comprising: a main data signal circuit for applying a data signal to an output of the transmitter circuitry; a pre-tap signal circuit for applying an advance replica of the data signal to the output; a post-tap signal circuit for applying a delayed replica of the data signal to the output; signal strength circuitry for controlling drive strength of at least one of the main data signal circuit, the pre-tap signal circuit, and the post-tap signal circuit; slew rate control circuitry for controlling slew rate of at least one of the main data signal circuit, the pre-tap signal circuit, and the post-tap signal circuit; programmable selectable inversion circuitry for programmably selectively inverting at least one of the advance replica and the delayed replica prior to use of said at least one replica by the one of the pre-tap signal circuit and the post-tap signal circuit that applies that replica to the output; common mode voltage circuitry for controlling common mode voltage of the output; and termination circuitry for providing controllable termination resistance to the output.