Patent ID: 6956793

Claim:
A method of generating a non-integer frequency divided clock signal comprising the steps of: a) generating a number K of output signal phases P( 0 ) to P(K−1); b) outputting a present value of an integer index in response to a logic transition of a shift clock signal; c) selecting one of the K output signal phases P( 0 ) to P(K−1) corresponding to the present value of the integer index as a clock output signal using a glitch free clock selector circuit; d) clocking a synchronous divide by N counter with the clock output signal generating the non-integer frequency divided clock signal and the shift clock signal; e) determining when the synchronous divide by N counter has been clocked N times by the clock output signal, wherein the shift clock signal is generated by a transition of the clock output signal following an Nth transition of the clock output signal; f) receiving an integer fractional divisor having a value less than (K−1); and g) adding the value of the integer fractional divisor to the present value of the integer index in a modulo (K−1) adding circuit generating a new present value of the integer index.