Patent ID: 7243213

Claim:
A process for translating instructions belonging to a first set of instructions that are pipelined scalar processor instructions into instructions belonging to a second set of instructions that are VLIW processor instructions for execution on a VLIW processor that includes a core, said process comprising the following operations: providing a first set of registers corresponding to the instructions of said first set of instructions; providing a second set of registers corresponding to the instructions of said second set of instructions; mapping each register of said first set of registers in a corresponding register of said second set of registers designed to emulate the behavior of the register of said first set of registers, performing a unique independent translation of the instructions of said first set of instructions into said second set of instructions; said operations of providing the second set of registers and of mapping being obtained by adding functional units to VLIW processor and keeping said core unaltered; and performing said translation in the absence of direct access to resources of said core.