Patent ID: 8756486

Claim:
A memory device system, comprising: a plurality of memory device die coupled to each other via a first plurality of through silicon vias, wherein the plurality of memory device die are stacked on top of each other and each of the memory device die contain a plurality of memory cells; a logic die coupled to the memory device dice through a second plurality of through silicon vias through which signals are coupled to and/or from each of the memory device dice, the logic die being operable to write data to and read data from the memory device dice, the logic die including an error checking system, comprising: an error code generator coupled to receive data written to at least one of the memory device die, the error code generator being operable to generate and store an error checking code corresponding to data to be written to an address in at least one of the memory device die, the error code generator further being operable to receive data read from an address in at least one of the memory device die and to generate an error checking code corresponding thereto; an error comparator coupled to receive the stored error checking code corresponding to data written to a read address in at least one of the memory device die and the generated error checking code corresponding to the data read from the read address in at least one of the memory device die, the error comparator being operable to indicate an error if a stored error checking code corresponding to the data read from the read address does not match the error code generated corresponding to the received data; and an embedded processor or hardware state machine configured to configured to examine addresses from which data was read that resulted in an error being indicated to detect an error pattern indicative of a faulty through silicon via of the first or second plurality of through silicon vias to which the logic die applies an address bit.