Patent ID: 7281055

Claim:
A computer system comprising a plurality of processor clusters interconnected by a plurality of global point-to-point links and having a global memory address space associated therewith, each cluster including a plurality of local nodes and an interconnection controller interconnected by a plurality of local point-to-point links, each cluster having a local memory address space associated therewith corresponding to a first portion of the global memory address space, wherein the interconnection controller in each cluster is mapped by the associated local nodes to a remainder portion of the global memory address space exclusive of the first portion, each cluster having routing information associated with each of the local nodes for facilitating communication between the local nodes and the interconnection controller via specific ones of the local links identified in the associated routing information, wherein the interconnection controller in each cluster is operable to maintain at least one local routing table relating each of the local nodes to at least one of the local links, at least one global routing table relating each of the other clusters to at least one of the global links, and memory mapping information relating each of the other clusters to respective portions of the remainder portion of the global memory address space, and wherein the interconnection controller in each cluster is operable to map locally generated transmissions directed to the remainder portion of the global memory address space to the global links using the memory mapping information and the at least one global routing table, and remotely generated transmissions directed to the local nodes to the local links using the at least one local routing table.