Patent ID: 8063654

Claim:
An integrated circuit device comprising: a stacked die; a base die having a first plurality of contacts disposed on a back side of the base die, a second plurality of contacts disposed on a face side of the base die, a first plurality of through-die vias coupled to the first plurality of contacts and coupled to programmable logic of the base die; a plurality of probe pads including a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals; and test logic configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device; wherein the stacked die is stacked on the back side of the base die and connected to the first plurality of contacts; wherein the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain; and wherein the base die further includes a multiplexer having a first input coupled to the programmable logic of the base die, a second input coupled to the first probe pad with a first through-die via, and a control input coupled to the third probe pad with a second through-die via, the multiplexer being configured to select a signal from the programmable logic or test input from the first probe pad for the stacked die.