Patent ID: 8607443

Claim:
A method of manufacturing a connector chip comprising: preparing a plate-like insulating substrate material with a plurality of through hole rows arranged therein, each of the through hole rows including through holes arranged at a constant interval; forming a plurality of first base layers on one of both surfaces of the insulating substrate material, and a plurality of second base layers on the other of the both surfaces of the insulating substrate material, each of the first and second base layers being formed between each two of the through holes respectively located in each two adjoining through hole rows, the first base layers and the second base layers being formed of a metal thick film or a metal thin film; forming insulating layers between each two adjoining first base layers and between each two adjoining second base layers, respectively, the insulating layers having a property of repelling molten solder; forming third base layers over edge portions of the first base layers located on one side, internal surfaces of the through holes, and edge portions of the second base layers located on the one side, respectively, by metal vapor deposition; forming fourth base layers over edge portions of the first base layers located on the other side, the internal surfaces of the through holes, and edge portions of the second base layers located on the other side, respectively, by metal vapor deposition; cutting the insulating substrate material along substantially a middle of each of the through hole rows; and forming one or more plated layers over the first to fourth base layers.