Patent ID: 8244967

Claim:
A method to control an electronic apparatus that includes a central processing unit (CPU), a non-volatile electrically erasable and programmable read only memory (EEPROM), and a volatile random access memory (RAM), said non-volatile EEPROM including at least two blocks for storing user rewritable data, said two blocks being exclusively active under control by said CPU and each of said two blocks providing an area for base data, an area for flag data, and a plurality of areas each for difference data denoting a difference from said base data, said method comprising steps of: erasing one of said blocks which is currently inactive when said CPU detects that another block which is currently active is to be filled with data which said CPU is going to write in said active block before said CPU receives next data to be written therein; reading said base data from said area for base data and said difference data from said areas for difference data in said active block into said volatile RAM; creating new base data in said volatile RAM based on said base data, said difference data, and said next data; transferring said new base data created in said volatile RAM to said inactive block of said non-volatile EEPROM; and exchanging a mode of said blocks including a step to change said currently inactive block to be active and to change said currently active block to be inactive.