Patent ID: 7879715

Claim:
A method for forming an electronic structure comprising: forming a conductive pad on a substrate; forming an insulating layer on the substrate and on the conductive pad, the insulating layer having a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer; forming a primary conductive trace on the substrate so that the primary conductive trace is between the substrate and the insulating layer; forming an electrical coupling between the primary conductive trace and the conductive pad, the electrical coupling providing at least two separate current flow paths between the primary conductive trace and the conductive pad; forming a seed layer on the electronic substrate, wherein the seed layer is on the insulating layer, on sidewalls of the via, and on the portions of the conductive pad free of the insulating layer; forming a conductive shunt layer on portions of the seed layer, wherein the conductive shunt layer is on the seed layer opposite the portions of the conductive pad free of the insulating layer, opposite the sidewalls of the via, and opposite portions of the insulating layer adjacent the via, wherein portions of the seed layer are free of the conductive shunt layer, and wherein the conductive shunt layer comprises a first material; and forming a solder layer on the conductive shunt layer wherein the solder layer comprises a second material different than the first material.