Patent ID: 7723787

Claim:
A silicon-on-insulator (SOI) chip, comprising: a SOI substrate having an active area, wherein said SOI substrate comprises a semiconductor layer overlying an insulator layer; at least two dielectric layers resistant to silicidation over said semiconductor layer of said active area; at least one transistor located between said dielectric layers resistant to silicidation, wherein said transistor comprises a gate electrode layer over said semiconductor layer, a source region and a drain region in said semiconductor layer; at least two body contact regions in said semiconductor layer of said active area and separated from said source region and said drain region by said dielectric layers resistant to silicidation, wherein said at least two dielectric layers resistant to silicidation comprises: a first dielectric layer resistant to silicidation across one end of said gate electrode layer; and a second dielectric layer resistant to silicidation across the other end of said gate electrode layer; wherein, said gate electrode layer, said source region and said drain region are located between said first dielectric layer resistant to silicidation and said second dielectric layer resistant to silicidation, a third dielectric layer resistant to silicidation laterally adjacent to one sidewall of said gate electrode layer and connected to said first dielectric layer resistant to silicidation and said second dielectric layer resistant to silicidation; and a fourth dielectric layer resistant to silicidation laterally adjacent to the other sidewall of said gate electrode layer and connected to said first dielectric layer resistant to silicidation and said second dielectric layer resistant to silicidation; wherein, said first dielectric layer resistant to silicidation, said second dielectric layer resistant to silicidation, said third dielectric layer resistant to silicidation and said fourth dielectric layer resistant to silicidation are arranged in a form to enclose said gate electrode layer, said source region and said drain region.