Patent ID: 7487327

Claim:
A processor, comprising: a device interface configured to receive a memory access request from an input/output (I/O) device, wherein said memory access request specifies a virtual memory address to be accessed and a first requestor identifier (ID) that identifies said I/O device, and wherein said virtual memory address includes a first virtual memory unit identifier; and an I/O memory management unit coupled to said device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to said virtual memory address is stored within one of a plurality of entries of an I/O memory translation buffer, wherein said I/O memory management unit is further configured to implement a translation buffer entry replacement policy dependent upon usage history associated with each of said plurality of entries; wherein to determine whether said memory address translation is stored within said I/O memory translation buffer, said I/O memory management unit is further configured to determine whether, for any given one of said entries of said I/O memory translation buffer, a second requester ID and a second virtual memory unit identifier, each stored within said given entry of said I/O memory translation buffer, respectively match said first requester ID and said first virtual memory unit identifier specified in said memory access request; wherein, in response to determining that both said first and said second virtual memory unit identifier and said first and said second requestor ID respectively match for said given entry, said I/O memory management unit is further configured to indicate a translation buffer hit condition; and wherein, in response to determining that for any particular one of said entries, said second virtual memory unit identifier matches said first virtual memory unit identifier and said second requester ID does not match said first requester ID, said I/O memory management unit is configured to disallow said memory access request, to signal an error condition, and to preserve usage history associated with said particular entry without modification.