Patent ID: 8021942

Claim:
A method, comprising: forming a first transistor above a first device region, said first transistor comprising a first gate electrode structure and first source/drain regions; forming a second transistor above a second device region, said second transistor comprising a second gate electrode structure and second source/drain regions; forming an etch stop layer at least above each of said first and second gate electrode structures and each of said first and second source/drain regions of said first and second transistors; forming a sacrificial layer above said etch stop layer; exposing gate electrode material of each of said first and second gate electrode structures after forming said etch stop and sacrificial layers; replacing said first gate electrode structure with a first replacement gate structure comprising a high-k dielectric material and a first metal-containing gate electrode material while covering said second transistor by a mask; removing said second gate electrode structure on the basis of a first selective etch process while said first replacement gate electrode structure is also exposed to said selective etch process; forming a second replacement gate electrode structure comprising a high-k material and a second metal-containing gate electrode material; after forming said second replacement gate electrode structure, performing a second selective etch process on the basis of said etch stop layer to remove said sacrificial layer from above at least one of said first and second transistors; and after removing said sacrificial layer, removing said etch stop layer from above said at least one of said first and second transistors.