Patent ID: 7397715

Claim:
A semiconductor memory device comprising: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal in response to the operation mode selection signal and for transmitting address signals in response to the operation mode selection signal, wherein the redundancy cell test controller comprises: a test operation controller for generating the test operation control signal when the same operation mode selection signal is consecutively received and terminating the generation of the test operation control signal when the same operation mode selection signal is received once more upon generating the test operation control signal; and an address signal transmitting unit for transmitting the address signals when the test operation control signal is received; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal.