Patent ID: 7176058

Claim:
A method of fabricating a chip scale package, said method comprising the steps of: (i) preparing a wafer including a plurality of chips, said chip including a terminal on each of its upper and its lower surfaces, respectively; (ii) forming conductive layers, each formed on the upper and the lower surfaces of the wafer; and (iii) dicing the wafer into package units, each package unit including a clip, followed by forming electrode surfaces formed each of designated side surfaces of the conductive layers, wherein after the step (ii), further comprising the step of forming passivation layers, each formed on the first and the second conductive layers except for the side surfaces having the electrode surfaces, wherein the step (iii) comprises the sub-steps of: first-dicing the wafer so that one side surface of the chip scale package is formed; forming electrode surfaces on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by first-dicing the wafer; second-dicing the wafer into package units; and forming passivation layers on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by second-dicing the wafer, and wherein the step of first-dicing the wafer is the step of dicing the wafer so that scribe lines of the wafer are cut into two rows.