Patent ID: 8508458

Claim:
A shift register on an array substrate, comprising: a plurality of shift register units each connected to respective one of gate lines of the array substrate, wherein the plurality of shift register units are divided into three groups: a first group comprising the ( 8 n+ 1)th and ( 8 n +5)th shift register units corresponding to the ( 8 n+ 1)th and ( 8 n +5)the gate lines, a second group comprising the ( 8 n+ 3)th and ( 8 n+ 7)th shift register units corresponding to the ( 8 n+ 3)th and ( 8 n +7)th gate lines, and a third group comprising the ( 8 n+ 2)th, ( 8 n+ 4)th, ( 8 n+ 6)th and ( 8 n+ 8)th shift register units corresponding to the ( 8 n+ 2)th, ( 8 n+ 4)th, ( 8 n+ 6)th and ( 8 n+ 8)th gate lines, where n is 0 or a positive integer; wherein as to any two adjacent shift register units of each group, a signal output terminal of the following shift register unit is connected to a reset signal input terminal of the preceding shift register unit, and a signal output terminal of the preceding shift register unit is connected to a start voltage timing signal input terminal of the following shift register unit; wherein each group of shift register units are controlled by two clock signals, and the two clock signals alternately control two adjacent shift register units of each group; and wherein both the first shift register unit and the third shift register unit are connected to a first start voltage timing signal input terminal, and the second shift register unit is connected to a second start voltage timing signal input terminal.