Patent ID: 6996753

Claim:
A wafer burn-in test mode circuit comprising: a command decoder configured to create a plurality of command signals in response to input signals for driving a semiconductor memory device; an address latch circuit configured to latch a plurality of address signals; a register configured to store a wafer burn-in address signal for a wafer burn-in test from the address latch according to a command signal from the command decoder; a wafer burn-in test mode entry circuit configured to generate a wafer burn-in test mode entry signal for performing the wafer burn-in test according to the wafer burn-in address signal and a command signal from the command decoder; a plurality of shift registers configured to shift the wafer burn-in address signal inputted from the register according to the wafer burn-in test mode entry signal and a wafer burn-in clock signal; a wafer burn-in test priority decision circuit configured to output test priority signals according to output signals of the shift registers; and a decoder configured to decode the output signals of the shift registers according to the priority signals and configured to output wafer burn-in test signals corresponding to a wafer burn-in test item.