Patent ID: 8164973

Claim:
A storage apparatus comprising: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read, out of the plurality of storage sections; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written, out of the plurality of storage sections; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits each of which is so provided as to correspond to each of the plurality of storage sections, selects signals indicated by the selection signals for each of the plurality of storage sections out of the first and second clock signals, and outputs the selected signals to each of the plurality of storage sections.