Patent ID: 7464348

Claim:
A method for optimized mapping of source elements to destination elements as interconnect routing assignments of an electronic circuit, comprising: utilizing a chosen rule to establish a priority for mapping of a plurality of nets of electrical components which need to be electrically connected; generating a mapping assignment based on the priority for mapping, in which the act of generating a mapping assignment comprises: assigning a source element to a destination element for a first set of elements having a first priority; attempting to assign a second source element to a second destination element for a second set of elements having a second priority; identifying an unavailable destination element in the second set; and adjusting an assignment of the first set to make the unavailable destination element available; and refining the mapping assignment recursively to converge on an optimized solution by injecting an element of randomness into an assignment process, in which the act of refining comprises: selecting a set of elements in the mapping assignment; reassigning the set of elements; adjusting one or more other element assignments based on the set of elements reassigned; and determining whether a resulting adjusted assignment solution improves the established mapping assignment, wherein the resulting adjusted assignment solution becomes the established mapping assignment when there is improvement.