Patent ID: 7452777

Claim:
A method of forming a trench gate field effect transistor (FET) in a semiconductor die comprising an active region for housing active transistor cells and a termination region surrounding the active region, the method comprising: forming a well region in the active region and the termination region at the same time, the well region being formed in a silicon region having a conductivity type opposite that of the well region; simultaneously forming a plurality of active gate trenches in the active region and a non-active termination trench in the termination region, the plurality of active gate trenches and the non-active termination trench extending into and penetrating through the well region to there by divide the well region into a plurality of active body regions in the active region and a termination body region in the termination region; using a mask, forming an opening over the termination body region and an opening over the active region; implanting dopants into the active body regions through the opening over the active region and into the termination body region through the opening over the termination body region, thereby forming a first region in each active body region and in the termination body region, the first regions having a conductivity type opposite that of the well region; and recessing exposed surfaces of all first regions using a silicon etch to form a bowl-shaped silicon recess having slanted walls and a bottom protruding through each first region such that portions of each first region remain in a corresponding active body region, the remaining portions of the first regions in the active body regions forming source regions which are self-aligned to the active gate trenches.