Patent ID: 7366863

Claim:
A memory control apparatus, comprising: a memory circuit for writing data read from a memory means and storing data to be read out; a time detection means for detecting a start time to switch said memory means to an activated state from a non-activated state; a threshold value determination means for determining a threshold value for determining the start time for writing data to said memory circuit based on said start time detected by said time detection means; and a control means for writing data from said memory means to said memory circuit, wherein said time detection means detects said start time every time said memory circuit is switched from said non-activated state to said activated state for a plurality of times; and said threshold value determination means calculates standard deviation σ and an average value m of a regular distribution regulated based on said start time detected by said time detection means respectively for said plurality of times and determines said threshold value based on a start time corresponding to a position of +σ with respect to said average value or on said regular distribution.