Patent ID: 8796079

Claim:
A fabrication method of a pixel structure, comprising: forming a first patterned metal layer on a substrate, the first patterned metal layer comprising a scan line and a gate connected to the scan line; sequentially forming a first insulation layer, a semiconductor layer, and an etching stop pattern on the first patterned metal layer, and the etching stop pattern being located above the gate; forming a metal layer on the semiconductor layer and the etching stop pattern; patterning the metal layer and the semiconductor layer to form a second patterned metal layer and a patterned semiconductor layer, the second patterned metal layer comprising a data line, a source, and a drain, an extension direction of the data line intersecting an extension direction of the scan line, the source and the drain being opposite to each other and located on the etching stop pattern, the patterned semiconductor layer comprising a first semiconductor pattern completely overlapped with the second patterned metal layer and a second semiconductor pattern not overlapped with the second patterned metal layer, wherein the second semiconductor pattern comprises a channel pattern located between the source and the drain and a marginal pattern surrounding the first semiconductor pattern; forming a second insulation layer on the substrate and forming a contact opening exposing the drain in the second insulation layer; and forming a pixel electrode on the second insulation layer, the pixel electrode being electrically connected to the drain via the contact, wherein a method of patterning the metal layer and the semiconductor layer comprises: forming a patterned photoresist layer on the metal layer and the semiconductor layer, the patterned photoresist layer comprising a first photoresist pattern and a second photoresist pattern, a thickness of the first photoresist pattern being greater than a thickness of the second photoresist pattern, and the second photoresist pattern surrounding the first photoresist pattern; performing a first etching process by using the patterned photoresist layer as a mask to remove an exposed portion of the metal layer and a portion of the semiconductor layer under the exposed portion of the metal layer to form a pre-patterned metal layer and the patterned semiconductor layer; removing the second photoresist pattern and thinning the first photoresist pattern to form a third photoresist pattern exposing a portion of the pre-patterned metal layer; performing a second etching process by using the third photoresist pattern as a mask to remove the exposed portion of the pre-patterned metal layer for forming the second patterned metal layer; and opening.