Patent ID: 8115257

Claim:
A semiconductor apparatus comprising: an internal circuit; a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit; an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor; and a protection transistor with a source and a gate connected to the high-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being an P-channel type, resistance of a current path extending from the output terminal through the P-channel MOS transistor to the high-potential power supply line having a value such that, when voltage at which the protection transistor causes snapback is applied between the output terminal and the high-potential power supply line, a current flowing through the current path is lower than a breakdown current of the P-channel MOS transistor, a line connecting the output terminal to the P-channel MOS transistor passing through the inside of a region including the internal circuit, and resistance of a line connecting the output terminal to the P-channel MOS transistor being higher than resistance of a line connecting the output terminal to the protection transistor.