Patent ID: 8497830

Claim:
A liquid crystal display device comprising: a plurality of data lines comprising a first data line, a second data line, a third data line, a fourth data line and a fifth data line, being sequentially arranged and substantially in parallel with one another; a plurality of scan lines being perpendicularly crossed the data lines, one pixel area being defined as an overlapped area of the area between the two adjacent data lines and the area between the two adjacent scan lines, whereby a plurality of pixel areas are formed among the data lines and the scan lines, and the scan lines comprises a first scan line, a second scan line and a third scan line, being sequentially arranged and substantially in parallel with one another; a plurality of transistors, each of the transistors comprising a gate electrode, a source electrode and a drain electrode, the transistors being electrically connected to one of the data lines and one of the scan lines, wherein the transistors comprising: a first transistor, comprising its drain electrode electrically connected to the first data line and receive a first data signal from the first data line and its gate electrode electrically connected to the first scan line and receive a first gate signal from the first scan line; a second transistor, comprising its drain electrode electrically connected to the third data line and receive a third data signal from the third data line and its gate electrode electrically connected to the second scan line and receive a second gate signal from the second scan line; a third transistor, comprising its drain electrode electrically connected to the fourth data line and receive a fourth data signal from the forth data line and its gate electrode electrically connected to the first scan line and receive a first gate signal from the first scan line; a fourth transistor, comprising its drain electrode electrically connected to the fourth data line and receive a fourth data signal from the forth data line and its gate electrode electrically connected to the second scan line and receive a second gate signal from the second scan line, wherein each of the pixel areas has only one transistor.