Patent ID: 7650582

Claim:
A circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising: a storage unit for storing: connection information including information about kinds and numbers of said multiple components and connection relations among components; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and a data processing unit for: when inputting said connection information, said delay information about each kind of said multiple components and said chain effect propagating component information, storing these kinds of information in said storage unit; referring to information stored in said storage unit; performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and determining that a chain effect propagating component is halfway through a signal path in a total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.