Patent ID: 7961024

Claim:
A low power pulse-triggered flip-flop comprising a latch which contains a first conductive line and a first connection point, and a pulse generator linking to the latch, the pulse generator including: a first N-transistor which contains a gate, a first end and a second end, the first end being connected to the first connection point and the gate being connected to the first conductive line; a second N-transistor which contains a gate, a first end and a second end, the second end thereof being connected to the first conductive line; a third N-transistor which contains a gate, a first end and a second end, the second end thereof being connected to the first conductive line, the first end thereof being connected to a second conductive line, the second conductive line transmitting a clock signal and containing a second connection point and a third connection point, the second connection point being connected to the gate of the second N-transistor, the gate of the third N-transistor being connected to the first end of the second N-transistor through a third conductive line on the third connection point; a first P-transistor which contains a gate, a first end and a second end, the second end thereof being connected to the first conductive line; and a first inverter which is connected to the second conductive line and located between the second connection point and the third connection point.