Patent ID: 7705628

Claim:
A programmable logic device, comprising: a general interconnect; a plurality of logic array blocks (LAB) interconnected by the general interconnect; each of the plurality of logic blocks further comprising one or more logic elements, each of the logic elements comprising: a first look up table configured to generate an output signal, the first look up table having a first look up table input; a second look up table configured to receive the output signal as input; dedicated hardware within the logic element to configure the first look up table and the second look up table as a register without having to use the general interconnect; a selection device coupled to the first look up table input and configured to select between the output signal and another signal to provide the selection to the first look up table input, wherein the dedicated hardware includes a first dedicated interconnect providing a clock signal as an input to the first look up table and the second look up table respectively, wherein the first dedicated interconnect is connected to a LAB wide interconnect of the logic block, wherein the first look up table is physically arranged above the second look up table in the logic block, the dedicated hardware further configured to cascade the register formed from the first look up table and the second look up table with a second register provided in the logic block.