Patent ID: 7082489

Claim:
A data memory controller that supports a data bus invert, coupled to a data memory apparatus and a post data processor, the data memory controller comprising: an input data receiver, to receive a memory data from the data memory apparatus and then reduce a frequency of the memory data as well as increase a bandwidth of the memory data, and output a first data selected from the memory data in a way of sampling every sequential even number bit data of the memory data and a second data selected from the memory data in a way of sampling every sequential odd number bit data of the memory data; an invert bit generator, to receive the first data and the second data, and to compare the first data with a previously received second data to obtain a first invert bit, and to compare the second data with a previously received first data to obtain a second invert bit; a data access apparatus, receiving the first data, the second data, the first invert bit, and the second invert bit, and then output a fifth data, a sixth data, a third invert bit and a fourth invert bit; and an invert bit inspect apparatus, to compare an idle data and the fifth data to obtain an inspect bit, and to determine how to output the fifth data, the sixth data, the third invert bit and the fourth invert bit to the post data processor according to the inspect bit.