Patent ID: 8395455

Claim:
A ring oscillator having N inverting delay units serially connected in a form of a ring, each of the inverting delay units receiving an input signal and generating an output signal, N being a positive integer, each of the inverting delay units comprising: a buffer having an input terminal and an output terminal, the input terminal receiving the input signal, the output terminal generating a buffered input signal; and a delay circuit coupled to the output terminal of the buffer for providing a first time delay and a second time delay, the delay circuit providing a first reference voltage to generate the output signal after the first time delay or providing a second reference voltage to generate the output signal after the second time delay according to a voltage level of the buffered input signal, wherein the delay circuit comprises: a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor receiving the first reference voltage, the control terminal of the first transistor receiving the buffered input signal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor receiving the second reference voltage, the control terminal of the second transistor receiving the buffered input signal; a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor receiving the buffered input signal, the control terminal of the third transistor being coupled to the second terminal of the first transistor, the second terminal of the third transistor generating the output signal; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor receiving the buffered input signal, the control terminal of the fourth transistor being coupled to the second terminal of the second transistor, the second terminal of the fourth transistor being coupled to the second terminal of the third transistor.