Patent ID: 8569132

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor wafer having, in a first main surface of a silicon-carbide-based semiconductor substrate having a first conductivity type, a first silicon-carbide-based semiconductor layer having the same conductivity type as the first conductivity type and a concentration lower than that of the semiconductor substrate; (b) introducing, into a surface region of the first silicon-carbide-based semiconductor layer closer to the first main surface, a second-conductivity-type region having a second conductivity type opposite to the first conductivity type and serving as a channel region of a vertical power MISFET; (c) introducing a source region of the vertical power MISFET having the same conductivity type as the first conductivity type and a concentration higher than that of the first silicon-carbide-based semiconductor layer in self-aligned relation with the second-conductivity-type region; (d) after step (c), performing an activation anneal treatment for the second-conductivity-type region and the source region; and (e) after step (d), forming a gate structure of the vertical power MISFET in self-aligned relation with the source region, wherein the first silicon-carbide-based semiconductor layer is an epitaxial layer, wherein self-alignment of the source region with the second-conductivity-type region is performed using sidewalls each formed of a silicon-based insulating film, and wherein self-alignment of the gate structure with the source region is performed using an opening pattern of a carbon film.