Patent ID: 7099964

Claim:
A high speed processor having: (a) a data processing unit for processing data; (b) a data memory which is connected to the data processing unit via a data bus and can be addressed by the data processing unit via a data memory address bus in a data address space; (c) at least one input interface buffer which is connected to the data bus and has the purpose of buffering input data; (d) at least one output interface buffer which is connected to the data bus and has the purpose of buffering output data; (e) a ROM memory for storing program data, wherein the ROM memory is connected to the data processing unit via lines; (f) the input interface buffer and the output interface buffer being directly addressable by the data processing unit via an interface address bus in an independent interface address space, wherein the interface address bus is separate from the data memory address bus; and (g) wherein user data which is not to be processed by the data processing unit is passed on by the high speed processor from an addressed input interface buffer to an addressed output interface buffer without data processing when a single predetermined data transfer processor command is carried out by the data processing unit.