Patent ID: 8765491

Claim:
A method of forming a semiconductor device, the method comprising: forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate; masking the spacer layer so as to protect portions of the spacer layer over the STI regions; and subjecting exposed portions the spacer layer to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures from vertical portions of the spacer layer, and wherein a horizontal fill portion of the spacer layer remains in one more recesses present in the STI region so as to substantially planarize the STI regions prior to subsequent material deposition thereon, wherein the horizontal fill portion has a substantially flat top surface, and wherein portions of the spacer layer over the STI regions remain on top surfaces of the transistor gate structures therein, while etched portions of the spacer layer over the active regions are removed from top surfaces of the transistor gate structures therein.