Patent ID: 8115311

Claim:
A wiring structure in a semiconductor device, comprising: a first insulation layer located on a substrate; a first plug located on the substrate and extending through the first insulation layer, the first plug comprising an upper peripheral portion that defines a recess; a second plug located on the substrate and extending through the first insulation layer, the second plug being adjacent to the first plug; a second insulation layer located on the first insulation layer, the first plug and the second plug; a bit line structure located on the second insulation layer, the bit line structure being electrically connected to the first plug; a protection spacer located on the recess of the first plug and a sidewall of an opening in the second insulation layer, the opening exposing the recess of the first plug, the second plug and the sidewall of the bit line structure; and a pad located in the opening and contacting the second plug.