Patent ID: 7200059

Claim:
A burn-in test method of a semiconductor memory which has a plurality of bit line pairs composed of complementary bit lines respectively connected to memory cells, in which bit line pairs having a twist structure where said bit lines cross each other and bit line pairs having a non-twist structure where said bit lines are parallel to each other are alternately arranged, the method comprising: a first step of applying high and low voltage levels to said bit lines of each of said bit line pairs, respectively; a second step of applying same voltage levels as those in the first step to the bit line pairs having the non-twist structure, and applying voltage levels opposite to those in the first step to the bit line pairs having the twist structure; a third step of applying voltage levels opposite to those in the first step to said bit lines of each of said bit line pairs; a fourth step of applying the same voltage level as that in the third step to the bit line pairs having the non-twist structure, and applying voltage levels opposite to those in the third step to the bit line pairs having the twist structure; a fifth step of commonly applying high or low voltage level to each of said bit line pairs, and applying voltage levels opposite to each other to adjacent bit line pairs; and a sixth step of applying voltage levels opposite to those in the fifth step, wherein said bit line pairs are applied voltages for equal lengths of time in each of the first to sixth steps.