Patent ID: 8468407

Claim:
A method for adjusting a test clock domain during a layout of an integrated circuit, wherein the integrated circuit comprises a plurality of scan cells, the plurality of scan cells comprise at least a plurality of first scan cells and a plurality of second scan cells, the plurality of first scan cells are arranged to be on a first scan chain and are tested by a first test clock, the plurality of second scan cells are arranged to be on a second scan chain and are tested by a second test clock different from the first test clock, and the layout of the integrated circuit comprises a plurality of regions, and the method comprises: for a first region of the integrated circuit, determining whether the first region requires a test clock domain adjustment or not according to a density of first scan cells and a density of second scan cells of the first region; and when it is determined that the first region requires the test clock domain adjustment, the density of first scan cells of the first region is greater than a default value, and the density of second scan cells of the first region is less than the default value, rearranging at least one first scan cell of the first region on the second scan chain, and the first scan cell is then tested by the second test clock.