Patent ID: 8750049

Claim:
A word-line driver comprising: a first transistor having a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal, and a second conduction terminal coupled to a word-line; a second transistor having a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line; and a third transistor having a gate terminal driven by a third group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line, wherein the word-line driver is configured to select the word-line for a memory erase operation when the first group selection signal, the third group selection signal, the first sub-group selection signal, and the second sub-group selection signal are at a negative voltage, and the second group selection signal is at a zero voltage.