Patent ID: 8125816

Claim:
A semiconductor storage device comprising: a first memory cell array comprising: a first bit line; a first plate line; a first memory cell between the first bit line and the first plate line; a first sense amplifier connected to the first bit line; a first reference power line configured to supply a first reference voltage to the first bit line; a first switching module configured to control a connection between the first reference power line and the first bit line based on a control signal; a second memory cell array comprising: a second bit line; a second plate line; a second memory cell between the second bit line and the second plate line; a second sense amplifier connected to the second bit line; a second reference power line configured to supply a second reference voltage to the second bit line, the second reference power line being electrically separated from the first reference power line; a second switching module configured to control a connection between the second reference power line and the second bit line based on the control signal; a control module configured to generate the control signal in order to control a time difference between the first memory cell array and the second memory cell array in precharge operation of the first bit line and the second bit line.