Patent ID: 7211963

Claim:
A capacitive load driving circuit comprising: an input terminal; a front-edge delay circuit delaying a front edge of an input signal input via said input terminal; a back-edge delay circuit delaying a back edge of said input signal; an amplifying circuit amplifying a drive control signal obtained through said front-edge delay circuit and said back-edge delay circuit; and an output switch device which is driven by said amplifying circuit, wherein said front-edge delay circuit includes a first time-constant circuit comprising a first resistor and a first capacitor, said back-edge delay circuit includes a second time-constant circuit comprising a second resistor and a second capacitor, said drive control signal is generated by a signal combining circuit which combines an output signal of said first-time constant circuit with an output signal of said second-time constant circuit, and a buffer circuit is provided at a front end of either one or each of said first and second time-constant circuits.