Patent ID: 8872178

Claim:
An integrated circuit comprising: A. input pads; B. output pads, including a first output pad also receiving as an input expected test data, and a second output pad also receiving as an input mask test data; C. core circuitry having input leads and output leads coupled between the input pads and the output pads; D. output circuitry coupled between the core circuitry and the output pads, for each output pad the output circuitry including: i. a first tri-state buffer having a core input connected to a first core output lead, a data output connected to the first output pad, and a tristate enable input; ii. a second tri-state buffer having a core input lead connected to a second core output lead, a data output connected to the second output pad, and a tristate enable input; and iii. comparator circuitry having a core input connected to the first core output lead, an expected data input connected to the first output pad, a mask data input connected to the second output pad, and an enable input connected to the enable inputs of the tri-state buffers.