Patent ID: 7680238

Claim:
A frequency divider circuit comprising: a plurality of T flip-flops connected in series, wherein one of the output terminals of each T flip-flop is connected to one of the clock terminals of the following T flip-flop, the other output terminal of each T flip-flop is connected to the other clock terminal of the following T flip-flop, and the toggle terminal of each T flip-flop is connected to logic 1; an inverter with its output terminal connected to one of the clock terminals of a first T flip-flop; a first transmission gate connecting a clock signal to the other clock terminal of the first T flip-flop and the input terminal of the inverter; and a second transmission gate connecting the inverted signal of the clock signal to the other clock terminal of the first T flip-flop and the input terminal of the inverter; wherein a last T flip-flop controls the first transmission gate and the second transmission gate.