Patent ID: 7746102

Claim:
A bus-based logic block, comprising: N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another.