Patent ID: 7747011

Claim:
A cryptographic processing apparatus for performing Feistel-type common-key-block cryptographic processing, comprising: a processor that repeatedly executes an SPN-type F-function having a nonlinear conversion section and a linear conversion section over a plurality of rounds, wherein each of the linear conversion sections of an F-function corresponding to each of the plurality of rounds is configured to perform linear conversion processing of an input of n bits outputted from each of m nonlinear conversion sections, in total mn bits, as linear conversion processing that applies a square MDS (Maximum Distance Separable) matrix, at least in consecutive odd-numbered rounds and in consecutive even-numbered rounds, different square MDS matrices L a , L b are applied, and a matrix composed of m row vectors selected arbitrarily from row vectors constituting inverse matrices L a −1 , L b −1 of the square MDS matrices is linearly independent.