Patent ID: 8745556

Claim:
A method comprising: (a) using a programmed computer to generate a graph of a layout of at least a region in a layer of an integrated circuit (IC), where the layer is to have a plurality of circuit patterns to be patterned using at least three photomasks, the graph including nodes representing circuit patterns within the layout, the nodes connected to one another by edges representing respective separations between adjacent ones of the circuit patterns, wherein the separations are smaller than a threshold distance, and the graph has two or more loops; (b) checking whether any of the nodes within the graph having two or more loops is included in a respective single odd loop of the graph, and identifying each node that is included in a single odd loop as an independent node; (c) identifying, as a safe independent node, any said independent node not closer than a threshold distance from any other one of said independent nodes in another odd loop of the graph; and (d) using the programmed computer to check each odd loop of the graph to determine whether each odd loop has a safe independent node, and modify the layout, if the graph representing the circuit patterns in the layout includes any odd loop without any safe independent node, so that after the modifying, each odd loop in a graph of the modified layout has at least one safe independent node.