Patent ID: 7107504

Claim:
A test apparatus for testing a semiconductor device, comprising: an external test unit; a built in self test (BIST) circuit formed in the semiconductor device; and a built out self test (BOST) device which is coupled between the external test unit and the semiconductor device, wherein first pattern data for a pattern dependency test is previously stored in the BIST circuit and second pattern data for a timing dependency test is previously stored in the BOST device, wherein the BOST device includes a pattern generating circuit, coupled to the semiconductor device, for providing the previously stored second pattern data for the timing dependency test to the semiconductor device, and a decision circuit, coupled to the pattern generating circuit and the semiconductor device, for receiving test data originating from the second pattern data from the semiconductor device and determining the test result of the timing dependency test using the test data and the second pattern data, wherein the pattern generating circuit includes a pattern memory for storing the second pattern data for the timing dependency test, a timing generator, coupled to the pattern memory, for generating a reference clock signal and receiving the second pattern data for the timing dependency test from the pattern memory, and a wave formatter, coupled to the timing generator, for receiving the second pattern data for the timing dependency test from the timing generator in accordance with the reference clock signal and providing the second pattern data for the timing dependency test to the semiconductor device as front pattern data, wherein the wave formatter generates back pattern data by inverting the front pattern data in accordance with a control signal, wherein the decision circuit includes a measuring circuit for measuring an access time of the semiconductor device using an output signal from the semiconductor device and the clock signal output from the pattern generating circuit, and wherein the measuring circuit includes: a logic circuit for generating an EOR logical signal by performing an EOR operation on the clock signal and the output signal; and a frequency counter, coupled to the logic circuit, for measuring a time interval of the EOR logical signal.