Patent ID: 7479680

Claim:
An integrated circuit electrostatic discharge protection device that reduces parasitics on a printed circuit board to which the device is mounted, the device comprising: an integrated circuit chip that includes a plurality of ESD elements; a plurality of pads disposed on a periphery of the integrated circuit, the plurality of pads including: a first set of pads disposed on a first central peripheral region on a first side of the integrated circuit chip; a second set of pads disposed on a second central peripheral region on a second side of the integrated circuit chip, the second central peripheral region and the first central peripheral region being on opposite sides of the integrated circuit chip and being aligned with each other; a third set of pads disposed on edge peripheral regions of the integrated circuit chip; a leadframe package having pins that correspond to positions of the plurality of pads, including first symmetric central leadframe pins that correspond to the first set of pads, second symmetric central leadframe pins that correspond to the second set of pads, and third leadframe pins that correspond to the third set of pads; and a plurality of wires that each connect between one of the pads and one of the pins of the leadframe package, wherein the first and second symmetric central leadframe pins are straight and project perpendicularly from the leadframe package.