Patent ID: 7039536

Claim:
A method of analyzing a waveform of a source current in a semiconductor integrated circuit including a digital circuit having a plurality of logic gates, comprising: representing the digital circuit, according to a distribution of switching operations of the logic gates in the digital circuit, as a time-division group of parasitic capacitors comprising parasitic capacitors each connected between a source line and a ground line to be charged at a specific timing, and a group of parasitic capacitors each charged statically; generating an analysis model by coupling one end of the time-division group of parasitic capacitors, one end of the group of parasitic capacitors charged statically, and parasitic impedance of the source line, and connecting the other end of the time-division group of parasitic capacitors, the other end of the group of parasitic capacitors charged statically, and parasitic impedance of the ground line; and determining the waveform of the source current in the digital circuit from the analysis model.