Patent ID: 7721170

Claim:
An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices, comprising: a local clock splitting circuit that supplies a master clock signal and a slave clock signal to a Level Sensitive Scan Design (LSSD) latch structure under test, the local clock splitting circuit configured to selectively disable the master clock signal of the latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; the local clock splitting circuit further comprising a pair of AND gates and an edge-triggered latch coupled to inputs of the pair of AND gates, wherein the AND gates are respectively configured to selectively pass the master clock signal and the slave clock signal to the latch structure under test, depending upon an output state of the edge-triggered latch; and wherein the local clock splitting circuit utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.