Patent ID: 8637372

Claim:
A method for fabricating a FINFET integrated circuit comprising; epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate; etching the second silicon layer to form a silicon fin using the first silicon germanium layer as an etch stop; removing the first silicon germanium layer underlying the fin to form a void underlying the fin; filling the void underlying the fin with an insulating material, wherein a layer of insulating material further remains overlying an exposed portion of a surface of the silicon substrate outside of the void underlying the fin; depositing a planarizing layer overlying the silicon fin and the insulating material; etching the planarizing layer and the insulating material in an etchant that etches the planarizing layer and the insulating material at substantially the same rate and at a rate faster than the etch rate of the silicon fin; and stopping the etching when the insulating material is removed from the sidewalls and top surface of the silicon fin; and forming a gate structure overlying the fin and the layer of insulating material that remains overlying the exposed portion of the surface of the silicon substrate outside of the void underlying the fin.