Patent ID: 7349237

Claim:
A memory circuit, comprising: a plurality of memory cells arranged in rows and columns; a first conductor coupled to a plurality of the rows of memory cells; a first transistor having a current path coupled between a voltage supply terminal and the first conductor and having a control terminal coupled to receive a first control signal; a second transistor having a current path coupled between the voltage supply terminal and the first conductor and having a control terminal coupled to receive a second control signal; a reference voltage terminal; a third transistor having a current path coupled between the first conductor and the reference voltage terminal and having a control terminal coupled to receive a third control signal, said third control signal being distinct from said first and second control signals; a low voltage supply terminal; and a fourth transistor having a current path coupled between the first conductor and the low voltage supply terminal and having a control terminal coupled to receive a fourth control signal, said fourth control signal being distinct from said first, second, and third control signals.