Patent ID: 7219212

Claim:
A microprocessor comprising: a load/store unit that loads a first vector from a memory and stores a second vector to the memory, the first and second vectors having a vector size equal to an access width of the memory; a vector data register having a width equal to the vector size; and an alignment register accessible by the load/store unit and having a width smaller than the vector size, wherein when the first vector is not aligned to a word boundary corresponding to the vector size in the memory, the load/store unit is operable to combine one or more bits from the alignment register with one or more bits from memory to form the first vector loaded into the vector data register during a load operation, and when the second vector is not aligned to the word boundary in the memory, the load/store unit is further operable to combine one or more bits from the alignment register with one or more bits from the vector data register to form the second vector stored in memory during a store operation that is performed separately from the load operation.