Patent ID: 7653806

Claim:
A programmable processor comprising: an instruction path and a data path; a register file comprising a plurality of registers coupled to the data path; and an execution unit coupled to the instruction and data paths, that is operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis, dynamically partition data from an operand register in the plurality of registers according to a precision specified by a group instruction into multiple data elements having the same elemental width such that a total aggregate width of the multiple data elements equals a width of the operand register, the execution unit capable of executing group floating-point arithmetic operations in which multiple pairs of floating-point data elements stored in a pair of operand registers are arithmetically operated on in parallel to produce a catenated result comprising a plurality of individual floating-point results, wherein the execution unit is operable, in response to decoding a single group floating-point add instruction specifying: (i) a precision of a group operation corresponding to a data element width of m-bits, (ii) a first register in the register file having a width of n-bits and holding n/m floating-point data elements, and (iii) a second register in the register file having a width of n-bits and holding n/m floating-point data elements, to add each data element stored in the first register with a corresponding data element stored in the second register to produce n/m floating-point results that are returned as a catenated result to a register in the plurality of registers.