Patent ID: 7498860

Claim:
A buffer circuit selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit, the buffer circuit comprising: interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level, the output signal being a function of the second control signal in the first mode and being a function of the third control signal in the second mode; and first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry; wherein the interface circuitry comprises at least one voltage level translator circuit operative to receive, as a function of the first control signal, one of at least the second and third control signals, and to generate the output signal, the output signal of the voltage level translator circuit having a value indicative of the second control signal in the first mode of operation and having a value indicative of the third control signal in the second mode of operation.