Patent ID: 7047397

Claim:
An apparatus comprising: a scheduler to receive a first micro-instruction, said scheduler to generate a first operation and a second operation for said first micro-instruction, said scheduler to further schedule said first and second operations for execution N clock cycles apart; a staggered ALU coupled to said scheduler, said staggered ALU to execute said first and second operations, wherein said staggered ALU is a fast integer ALU comprised of a first logic to operate on lower order bits of an operand and a second logic to operate on high order bits of said operand and a flag logic to operate an flag bits, said staggered ALU wired to communicate results of said first operation from said second logic and said flag logic for use at said first logic by said second operation; an integer register file coupled to said staggered ALU and said scheduler, said integer register file to provide said operand; a checker coupled to said staggered ALU and said integer register file, said checker to check results of said first and second operations for any error; a replay mechanism coupled to said checker and said scheduler, said replay mechanism to replay said first and second operations if said checker indicates presence of an error; and retirement logic coupled to said checker, said retirement logic to retire said first micro-instruction if said checker does not indicate any errors.