Patent ID: 7670902

Claim:
A method for fabricating an integrated circuit device, the method comprising: providing a semiconductor substrate; forming a plurality of MOS transistor devices overlying the semiconductor substrate, each of the MOS transistor devices having a nitride cap and nitride sidewall spacers, each of the transistors being separated from each other by a predetermined width; forming an interlayer dielectric layer overlying the plurality of MOS transistor devices; removing a portion of the interlayer dielectric material overlying three MOS transistor devices to expose at least portions of the three MOS transistor devices and to expose at least three regions between respective MOS transistor devices; depositing polysilicon fill material overlying the exposed three regions and overlying the three MOS transistor devices; without etching back the polysilicon material, performing a chemical mechanical planarization process on the polysilicon material to reduce a thickness of the polysilicon material to expose a portion of the interlayer dielectric material; continuing the chemical mechanical planarization process to remove the interlayer dielectric material and the polysilicon film material until the cap nitride layer on each of the MOS transistors has been exposed; and using the cap nitride overlying each of the MOS transistors as a polish stop layer.