Patent ID: 6841416

Claim:
A method of fabricating a chip scale package, said method comprising the steps of: preparing a wafer including a plurality of chips, each of said chips including two upper terminals on an upper surface of the wafer and a lower terminal on a lower surface of the wafer; forming an insulating layer on the upper surface of the wafer except in areas of said upper terminals; forming an upper conductive layer on said insulating layer so as to be connected to each of said two upper terminals of each of said chips; forming a lower conductive layer on the lower surface of the wafer so as to be connected to the lower terminal of each of said chips; first dicing the wafer so that one side surface of the chip scale package is formed; forming electrode surfaces on side surfaces of the upper and the lower conductive layers, said side surfaces being defined by the side surface of the chip scale package obtained by said first dicing step; dividing the upper conductive layer of each of said chips into two areas each connected to one of said two upper terminals; and second dicing the wafer into package units.