Patent ID: 7725805

Claim:
An information apparatus, comprising: a processor; a processor bus to which the processor is coupled; a memory; a memory bus to which the memory is coupled; a communication controller that communicates with an outside of the information apparatus; a system bus to which the communication controller is coupled; and a system control unit coupled to the processor bus, the memory bus, and the system bus, wherein the system control unit controls communications between the processor, the memory, and the communication controller, wherein the system control unit determines whether to attach, to data that is transferred between the memory and the system control unit, an error detecting code for protecting the data based on an address in the memory at which the data to be transferred is read or written, wherein each address in the memory corresponds to at least one address belonging to a plurality of address spaces managed by the system control unit, wherein the plurality of address spaces include at least a first address space and a second address space, wherein when receiving a request to write data, the system control unit determines whether to attach the error detecting code to the data by determining whether the received request is a request to write the data at an address that belongs to the first address space or is a request to write the data at an address that belongs to the second address space, wherein when it is determined that the request to write the data is at the address that belongs to the first address space, the system control unit writes the data in the memory, and wherein when it is determined that the request to write the data is at the address that belongs to the second address space, the system control unit generates the error detecting code for the data, attaches the generated error detecting code to the data, and writes the error detecting code with the data in the memory.