Patent ID: 8667376

Claim:
A decoding device that decodes a quasi cyclic low density parity check code of an error correction encoding system, and outputs an estimated transmission bit sequence as a decoded result; comprising: an information memory that stores at least estimated information of a transmission bit sequence; a set of two feedback shift register type check node processing devices each including a feedback register made up of a plurality of registers interconnected to form a loop; said feedback shift register type check node processing devices each inputting said estimated information and generating a message to update the input estimated information and outputting the message generated; a multiplexer selecting one of the check node processing devices that inputs said estimated information; a demultiplexer selecting another one of the check node processing devices that outputs said message; and an addition circuit that updates said estimated information based on said message output from said check node processing device selected by said demultiplexer to output the estimated information updated; said check node processing device including a permutation circuit that permutates said estimated information, and a plurality of comparator circuits; said comparator circuits each selecting, out of two data saved in the registers of the check node processing device and data output by the estimated information, a smallest value data and a second smallest value data, and saving the data selected in registers of a next stage; each of said comparator circuits being interposed between said registers of said check node processing device.