Patent ID: 8343838

Claim:
A method for forming a semiconductor field-effect transistor device comprising: a) forming a semiconductor structure comprising a material doped of a first dopant and having a non-zero number of threading dislocations, wherein the semiconductor structure comprises a multi-layer structure including a Si layer that is present over a SiGe layer; b) implanting a blocking impurity in said semiconductor structure, said blocking impurity is In or Sb, wherein said implanting the blocking impurity in said semiconductor structure includes implanting the blocking impurity with an energy such that a peak blocking impurity concentration approximately coincides with an interface between the Si layer and the SiGe layer; c) thermally processing said semiconductor structure such that said blocking impurities segregate to said non-zero number of threading dislocations, said blocking impurities further segregating to new dislocations that may be induced by said thermal processing; d) forming a dielectric layer on top of said semiconductor structure to define a gate region, and forming a gate electrode over said dielectric region, a portion of the semiconductor structure immediately beneath the gate defining a channel region, and a portion of the semiconductor structure beneath the channel region defining a well region; and e) implanting dopants in said semiconductor structure on opposite sides of said gate region to form source and drain regions wherein the source and drain regions abut the channel region and well region on either side, and wherein a dislocation or crystal defect extends continuously from said source to drain region, and an immediate vicinity of said crystal defect is substantially occupied by said blocking impurity dopant.