Patent ID: 7956418

Claim:
An ESD protection device comprising: a substrate; a first doping region formed in the substrate and enclosing an active region, wherein the first doping region is coupled to a first node; a first MOS transistor structure on the internal of the active region, comprising: a second doping region formed in the substrate and comprising a first portion and a second portion, wherein the second doping region is coupled to the first node; a third doping region formed in the substrate; and a first gate formed on the substrate and between the second portion of the second doping region and the third doping region; a second MOS transistor structure on the internal of the active region, comprising: a fourth doping region formed in the substrate and comprising a first portion and a second portion, wherein the fourth doping region is coupled to a second node; a fifth doping region formed in the substrate; and a second gate formed on the substrate and between the first portion of the fourth doping region and the fifth doping region; wherein the third doping region is near the second portion of the fourth doping region, and the fifth doping region is near the first portion of the second doping region; a sixth doping region formed in the substrate and on one side of the first and second MOS transistor structures, wherein the sixth doping region is coupled to the second node; and a first well region on the internal of the active region, formed in the substrate and under one part of the third doping region, one part of the fifth doping region, the fourth doping region, and the sixth doping region.