Patent ID: 8422288

Claim:
A DRAM (dynamic random access memory) cell having floating body effect, comprising a buried oxide layer, a first P type semiconductor region provided on the buried oxide layer, a N type semiconductor region provided on the first P type semiconductor region, and a gate region provided on the N type semiconductor region, including a gate dielectric layer and a gate electrode on the gate dielectric layer, wherein a second P type semiconductor region is provided on one side of the N type semiconductor region and the second P type semiconductor region is communicated with the first P type semiconductor region; wherein an electrical isolation region is provided around an active region formed by the N type semiconductor region, the first P type semiconductor region and the second P type semiconductor region; wherein a depletion region is formed by the first P type semiconductor region and the N type semiconductor region, and the second P type semiconductor region and the N type semiconductor region, and a floating body is formed by the electrical isolation region and the depletion region; wherein a electrode connected to bit line is provided on the second P type semiconductor region.