Patent ID: 8232587

Claim:
A metal-insulator-metal capacitor, comprising: a semiconductor substrate having a first dielectric layer formed thereon; a stack dielectric structure overlying said first dielectric layer, wherein said stack dielectric structure comprises a plurality of second dielectric layers and a plurality of third dielectric layers alternating with each other, and a wet etch selectivity of said second dielectric layer relative to said third dielectric layer is of at least 5:1, wherein an opening has serrate sidewalls passing through said stack dielectric structure and a bottom exposing a portion of said first dielectric layer; a bottom electrode layer formed on said stack dielectric structure and said first dielectric layer along said serrate sidewalls and said bottom of said opening; an isolation layer formed between said stack dielectric structure and said bottom electrode layer; a capacitor dielectric layer formed on said bottom electrode layer; and a top electrode layer formed on said capacitor dielectric layer.