Patent ID: 7293207

Claim:
A method for testing a main memory of a computer having a central processing unit supporting either 32-bit or 36-bit memory addressing, the method comprising: determining whether the central processing unit supports 32-bit or 36-bit addressing of the main memory; in response to determining that the central processing unit supports 36-bit addressing, identifying a portion of the memory to be tested, creating a page directory containing entries for directly accessing the portion of the memory to be tested according to a maximum page size supported by the central processing unit, directly accessing the portion of the memory to be tested using the page directory, and testing the accessed memory portion; and in response to determining that the central processing unit supports 32-bit addressing, identifying a portion of the memory to be tested, dynamically creating a page directory and one or more page tables containing entries for accessing the portion of the memory to be tested according to a maximum page size supported by the central processing unit, accessing the portion of the memory to be tested using the page directory and the one or more page tables and testing the accessed memory portion.