Patent ID: 8703560

Claim:
A method for manufacturing a thin film transistor, comprising the steps of: forming a gate insulating layer over a gate electrode layer; forming a semiconductor layer over the gate insulating layer; forming an impurity semiconductor layer over the semiconductor layer; forming a conductive layer over the impurity semiconductor layer; etching portions of the semiconductor layer, the impurity semiconductor layer, and the conductive layer by using a first resist mask having a depression portion to form a patterned semiconductor layer overlapping at least a part of the gate electrode layer wherein the first resist mask is simultaneously etched so that the depression portion reaches the conductive layer, thereby forming a second resist mask; etching the conductive layer to form source and drain electrode layers by using the second resist mask over the conductive layer; etching the impurity semiconductor layer of the patterned semiconductor layer, to expose a part of the semiconductor layer so that a back channel portion in the thin film transistor is formed; removing the second resist mask after etching the impurity semiconductor layer of the patterned semiconductor layer; and performing a plasma treatment on a surface of the back channel portion to remove contamination materials from the surface of the back channel portion, after removing the second resist mask.