Patent ID: 8652924

Claim:
A method of forming a storage node in a semiconductor device, the method comprising: forming an interlayer insulation layer on a substrate; sequentially forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer; patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole; forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole; forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole; and removing the first sacrificial layer pattern, wherein the recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node.