Patent ID: 8415218

Claim:
A method of making a thin-film transistor memory cell, the method comprising: providing a substrate; forming a first insulation layer on the substrate; forming one or more source/drain regions on the first insulation layer, each of the one or more source/drain regions including an N-type polysilicon layer, a barrier layer, and a conductive layer, the N-type polysilicon layer having a first surface and being on the barrier layer, the barrier layer overlying the conductive layer; forming a second insulation layer on the first insulation layer, the second insulation layer being associated with a second surface, the second surface being substantially co-planar with the first surface; forming a first P-type epitaxial silicon layer overlying the first surface and the second surface; forming a second epitaxial silicon layer sandwiched by an upper silicon dioxide block layer and a bottom silicon dioxide tunnel layer on the first P-type epitaxial silicon layer, the second epitaxial silicon layer being capable of forming a floating gate; forming a P-type polysilicon layer on the upper silicon dioxide block layer; and forming at least one control gate by patterning the P-type polysilicon layer, wherein forming the second epitaxial silicon layer comprises: forming a hydrogenated surface on the bottom silicon dioxide tunnel layer, the hydrogenated surface having a single S—H bond; growing a first atomic layer of silicon with H-termination on the hydrogenated surface through ALD epitaxy from SiH 4 thermal cracking assisted by Ar flow and flash lamp annealing continuously, wherein the H-termination of the first atomic layer of silicon has two S—H bonds; and growing second or more atomic layers of silicon with H-termination sequentially through ALD epitaxy from SiH 4 thermal cracking assisted by Ar flow and flash lamp annealing continuously, wherein the H-termination of the subsequent second and more atomic layers of silicon has two S—H bonds.