Patent ID: 7193925

Claim:
A low power semiconductor memory device comprising: a plurality of memory cell array blocks arranged in a matrix type and each comprising a plurality of memory cells; a block selecting activation control unit for outputting a block selecting activation signal in response to a read command, a write command, and block selecting address; a sense amplifier control unit for outputting a block sense amplifier activating signal in response to a sense amplifier activating signal and the block selecting activating signal; a plurality of sense amplifier arrays connected to the memory cell array blocks and each comprising a plurality of sense amplifiers, wherein the plurality of sense amplifiers sensing and amplifying data stored in the memory cells in response to the block sense amplifier activating signal; and a sub word line driver array connected to the memory cell array blocks, comprising a plurality of sub word line drivers, wherein the plurality of sub word line drivers are activated when the block selecting activation signal is activated, and wherein the plurality of sub word line drivers are driven by a main word line to select a sub word line.