Patent ID: 6912602

Claim:
An integrated circuit comprising: a first interface circuit configured to operate as a first interface for the integrated circuit to receive and send data packets external to the integrated circuit; a second interface circuit configured to operate as a second interface for the integrated circuit to receive and send data packets external to the integrated circuit; a memory controller configured to interface to a memory; a direct memory access (DMA) circuit coupled to receive data packets from the first and second interface circuits and to perform direct memory access operation in response to a write command to the memory controller to write received data packets in to the memory, wherein the DMA circuit includes an input circuit to map received data packets from the first and second interface circuits into logical input queues; and a switch coupled to the DMA circuit and to the first and second interface circuits to switch between the first and second interface circuits for coupling to the DMA circuit to allow one DMA circuit to be employed in the integrated circuit to process multiple data interfaces of the integrated circuit, the switch to have multiple switch virtual channels to switch data packets from the first and second interface circuits to one or more logical input queues to allow data packets from the first and second interface circuits to be mapped into separate queues or merged into a selected input queue.