Patent ID: 7545691

Claim:
A measuring circuit for a memory integrated within a semiconductor device, the measuring circuit comprising: initializing means for loading two complementary values into at least two locations of the memory, the two locations being addressed by a first address and a second address; an oscillating loop comprising a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory; a first multiplexing circuit comprising first and second inputs and an output producing a first output signal, the first input receiving a clock signal for starting an oscillating mode, the first multiplexing circuit being controlled by a first control signal; and a second multiplexing circuit comprising first and second inputs and an output producing a second output signal, the first input receiving an output from the memory and the second input receiving the first output signal from the first multiplexing circuit, the second multiplexing circuit being controlled by a second control signal that determines the oscillation mode of the oscillation loop, wherein the memory comprises a clock input that receives the first output signal from the first multiplexing circuit, and an output that produces the data being read.