Patent ID: 8134412

Claim:
A method of producing an output clock signal for transmission to a device, the method comprising: generating, using an oscillating circuit, a first internal clock signal having a first frequency that is 2 n times an input frequency of an input clock signal, where n is an integer; generating, using the oscillating circuit, a second internal clock signal based on the first internal clock signal, wherein the second internal clock signal has a second frequency that is substantially the same as the input frequency; generating, using the oscillating circuit, a first output clock signal based on the second internal clock signal by applying a first time delay to the second internal clock signal such that the first output clock signal is aligned in phase with the input clock signal, wherein the first time delay is based on a phase difference between the input clock signal and the second internal clock signal; and generating, using the oscillating circuit, a second output clock signal configured to be provided to the oscillating circuit as feedback, wherein: the first output clock signal is transmitted to the device; the second output clock signal is delayed by a second time delay equal to a transmission delay associated with transmitting the first output clock signal from an output of the oscillating circuit to an input of the device; the first output clock signal is generated based on the second output clock signal; the phase of the generated first output clock signal is shifted by a time substantially equal to the transmission delay; and the first output clock signal is substantially in phase with the input clock signal when received at the input of the device.