Patent ID: 7145172

Claim:
A thin film transistor array substrate of a thin film transistor liquid crystal display, comprising: a transparent substrate; a gate and a bottom electrode respectively located on the transparent substrate; a first silicon nitride layer formed on the transparent substrate, the gate, and the bottom electrode; a dielectric layer formed on the first silicon nitride layer; a stacked layer formed on the dielectric layer over the gate, the stacked layer comprising a second silicon nitride layer and an undoped amorphous silicon layer from the bottom to the top; two doped amorphous silicon layer portions serving as lightly doped drains respectively formed on the stacked layer over both sides of the gate; a source and a drain respectively formed on the two doped amorphous silicon layer portions; a passivation layer formed over the transparent substrate, and the passivation layer having a contact window exposing the drain; and a pixel electrode, formed on the passivation layer, connecting the drain through the contact window and overlapping with the bottom electrode, wherein an etching selectivity ratio of the undoped amorphous silicon layer and the two doped amorphous silicon layer portions over the dielectric layer is not less than about 5.0.