Patent ID: 8176443

Claim:
A method of fabricating an integrated circuit comprising: forming a plurality of circuit first gate features in parallel over an active region of a semiconductor substrate, the first gate features being spaced at a first pitch from each other; forming, by using a processor, a photomask printable-gate-assist feature over the substrate in a position adjacent to and spaced from the active region, the printable-gate-assist feature being parallel to and spaced at a second pitch from an adjacent first gate feature; forming a circuit second gate feature over the active region, the second gate feature being parallel to the first gate features and having a longest dimension shorter than a corresponding longest dimension of a neighboring first gate feature; and forming a photomask printable-gate-extension feature attached to the second gate feature and spaced from the active region, the printable-gate-extension feature extending the longest dimension of the second gate feature to match the corresponding longest dimension of the neighboring first gate feature.