Patent ID: 7456769

Claim:
A sigma delta digital-to-analog converter comprising: a reference voltage generating circuit, for receiving a predetermined voltage and filtering the predetermined voltage to generate a reference voltage, the reference voltage generating circuit comprising: a first capacitor, comprising a first end and a second end; a second capacitor, comprising a third end and a fourth end, a first switch, for alternatively coupling the predetermined voltage to the second end of the first capacitor, wherein the first switch couples the predetermined voltage to the first capacitor in a first stage, and disconnects the predetermined voltage and the first capacitor in a second stage and a third stage; a second switch, for alternatively coupling the first end of the first capacitor to the third end of the second capacitor, wherein the second switch couples the third end of the second capacitor to the first end of the first capacitor in the second stage, and disconnects the first capacitor and the second capacitor in the first stage and the third stage; a third switch, for alternatively coupling the first end of the first capacitor to a reference level, wherein the third switch couples the first end of the first capacitor to the reference level in the first stage, and disconnects the first capacitor and the reference level in the second stage and the third stage; a fourth switch, for alternatively coupling the second end of the first capacitor to the reference level, wherein the fourth switch couples the second end of the first capacitor to the reference level in the second stage, and disconnects the first capacitor and the reference level in the first stage and the third stage; wherein the first capacitor samples the predetermined voltage in the first stage, and redistributes charges to the second capacitor in the second stage in order to generate the reference voltage; and a sigma delta modulator, for receiving the reference voltage from the reference voltage generating circuit and generating an analog signal according to a digital signal in the third stage.