Patent ID: 7269072

Claim:
A method for multistate memory operation, the method comprising: writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the DRAM array includes a number of source lines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the source line in a shared trench, and wherein the DRAM array includes a number of bit lines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes: biasing a source line for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD; grounding a bit line coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed; applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that the addressed MOSFETs becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction; reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes; grounding a source line for two column vertical MOSFETs sharing a trench; precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell.