Patent ID: 7133324

Claim:
A synchronous dynamic random access memory device for both DDR 1 and DDR 2 mode operations, comprising: a mode selection circuit configured to generate a first mode selection signal that activates a DDR 1 mode operation and a second mode selection signal that activates a DDR 2 mode operation; a row decoder configure to decode a row address; a column decoder configured to select two global data lines for one unit data input/output in response to the first mode selection signal, and configured to select four global data lines for said one unit data input/output in response to the second mode selection signal; a core section configured to receive data from the two global data lines arid output the data to the two global data lines in response to the first mode selection signal, and configured to receive the data from the four global data lines and output the data to the four global data lines in response to the second mode selection signal; and an input and output control circuit configured to prefetch two bits data in response to the first mode selection signal to provide the two bits data to the core section, configure to output the two bits data received from the core section in response to the first mode selection signal, configured to prefetch four bits data in response to the second mode selection signal to provide the four bits data to the core section, and configured to output the four bits data received from the core section in response to the second mode selection signal.