Patent ID: 8861250

Claim:
A mask read-only memory, comprising: a substrate; a first gate structure formed on a surface of the substrate for receiving a word line voltage during a read cycle; a second gate structure formed on the surface of the substrate for receiving a read voltage during the read cycle; a third gate structure formed on the surface of the substrate; a first diffusion region formed in the surface of the substrate and located adjacent to a first side of the first gate structure for generating a first bit line voltage during the read cycle; a second diffusion region formed in the surface of the substrate, and located adjacent to a second side of the first gate structure and extended to a first side of the second gate structure and a first side of the third gate structure; a fourth gate structure formed on the surface of the substrate for receiving the word line voltage during the read cycle; a fifth gate structure formed on the surface of the substrate for receiving the read voltage during the read cycle; a sixth gate structure formed on the surface of the substrate; a third diffusion region formed in the surface of the substrate and located adjacent to a first side of the fourth gate structure for generating a second bit line voltage during the read cycle; a fourth diffusion region formed in the surface of the substrate, and located adjacent to a second side of the fourth gate structure and extended to a first side of the fifth gate structure and a first side of the sixth gate structure, wherein the fourth diffusion region receives the read voltage during the read cycle; wherein the first bit line voltage is different from the second bit line voltage.