Patent ID: 8466728

Claim:
A buffer circuit, comprising: an input stage including at least one metal-oxide-semiconductor (MOS) device having a first threshold voltage associated therewith, the input stage being adapted to receive an input signal referenced to a first voltage supply; an output stage including at least one MOS transistor having the first threshold voltage associated therewith, an input of the output stage being connected to an output of the input stage, the output stage being operative to generate an output signal which is indicative of a logic state of the input signal; and a delay control circuit adapted for connection between at least one of: (i) the input stage and at least one of the first voltage supply and a voltage return of the buffer circuit; and (ii) the output stage and at least one of the first voltage supply and the voltage return of the buffer circuit, the delay control circuit being connected outside a signal path of the buffer circuit, the delay control circuit comprising at least one MOS device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage, the at least one MOS device in the delay control circuit receiving, as a control signal, a second voltage supply, the second voltage supply being independent of the first voltage supply and the voltage return of the buffer circuit, a delay of the buffer circuit being at least partially controlled as a function of at least one of a process parameter, the second voltage supply and a temperature of the at least one MOS device in the delay control circuit.