Patent ID: 7441215

Claim:
A method of comparing a plurality of circuit designs, said circuit designs each being described by a netlist, said netlist specifying logical devices and their interconnections, said devices being organized into a plurality of subcircuits, said subcircuits having a list of input/output port names, said subcircuits being specified by a name, said subcircuits being organized in a hierarchical order where subcircuits of a higher hierarchical order contain instantiations of subcircuits of lower hierarchical order and said devices, said method comprising: (a) reading said netlists; (b) finding subcircuits in said netlists that have the same name and same list of input/output port names; (c) leaving such subcircuits unmarked, all other subcircuits being marked; (d) starting the comparison with the most relevant unmarked subcircuit, wherein starting the comparison with the most relevant subcircuit comprises starting from a top-level subcircuit, said top-level being the highest hierarchical level of interest; (e) flattening any instantiation of marked subcircuits to devices in said subcircuit; (f) verifying logical equivalence of said subcircuit using a graph isomorphism technique; (1) assuming instantiations of unmarked subcircuits in said subcircuit are such that the same port name is connected identically inside said unmarked subcircuits in said netlists; (2) verifying each port name in said subcircuit is connected to the same devices and subcircuit instantiations in an identical way in said netlists validating said assumption; (g) finding the next unmarked subcircuit to compare; (h) continuing until all unmarked subcircuits of interest have been compared; wherein a circuit design is compared in the most relevant order in minimal time.