Patent ID: 7564299

Claim:
A regulator circuit, comprising: a first amplifier stage having: (i) an input coupled to a reference, (ii) an output, (iii) a differential amplifier with a gm reducing circuit, and (iv) an output section with at least one transistor biased to lower the output resistance of the first amplifier stage, wherein the gm reducing circuit is implemented by feeding current from a first branch of the differential amplifier to the output of a second branch of the differential amplifier and feeding current from the second branch to the output of the first branch; and a second amplifier stage having an output and an input coupled to the output of the first amplifier stage, wherein the differential amplifier comprises a tail current source to vary its strength in accordance with load changes at the output of the second amplifier stage, the tail current source comprising a transistor mirrored to a transistor in the output current path.