Patent ID: 6978426

Claim:
A method for fixed-width modified Booth multiplication, comprising: encoding a W-bit multiplier using modified Booth coding; processing the encoded multiplier and a multiplicand to generate partial products; and accumulating the partial products to generate a W-bit product, wherein said accumulating step comprises dividing truncated bits into two groups, a major least significant bit group and a minor least significant bit group, generating an approximate carry value using the bits of the minor least significant bit group, and generating an exact carry value for the major least significant bit group using the approximate carry value and the bits of the major least significant bit group, and wherein said approximate carry value is generated using a circuit designed in accordance with the steps of forming a plurality of coded values y″ w/2−2 , y″ w/2−3 , . . . , y″ 1 and y″ 0 , selecting a number (N AC ) of approximate carry signals (a_carry — 0, a_carry — 1, . . . , a_carry_N AC−1 ) to be generated by said circuit, assigning a value of 1 to an approximate carry signal (a_carry_i) if at least “2i+1” of the coded values y″ w/2−2 , y″ w/2−3 , . . . , y″ 1 and y″ 0 have a value of 1, and applying a circuit design technique to the assigned values of the approximate carry signals (a_carry — 0, a_carry — 1, . . . , a_carry_N AC−1 ) to design said circuit.