Patent ID: 7348916

Claim:
A pipeline A/D converter comprising: a plurality of stages connected in series, each of which operates for A/D conversion and outputs a digital signal; a digital computing portion that performs computation for outputting an A/D converted output signal based on the digital signal output from each of the stages; and a clock generating portion that supplies a clock signal for controlling an operation of each of the stages, each of the stages comprising: a reference signal output portion that outputs a predetermined analog reference signal in accordance with the digital signal from the preceding stage; an analog signal processing portion that adds/subtracts the analog reference signal to/from an analog output signal from the preceding stage and outputs the thus-obtained result as an analog output signal of the present stage; and a multivalued coding portion that outputs the digital signal in accordance with the analog output signal of the present stage, the analog signal processing portion comprising an operational amplifier, a first passive element, and a second passive element, the analog output signal of the preceding stage being sampled by both the passive elements in a first period while one of the passive elements is used as a feedback element of the operational amplifier in a second period so that the signal sampled by the other passive element is added/subtracted to/from the analog reference signal of the reference signal output portion by the operational amplifier, wherein the digital computing portion outputs first and second control signals for controlling the operation of each of the stages, performs computation by detecting a unique digital-conversion-error value based on the digital signal obtained by the operation of each of the stages performed based on the first and second control signals, and corrects the digital conversion error, the analog signal processing portion and the multivalued coding portion can select a test signal instead of the analog output signal in accordance with the first control signal from the digital computing portion, and the analog signal processing portion selects and uses one of the first passive element and the second passive element as the feedback element in the second period in accordance with the second control signal from the digital computing portion.