Patent ID: 7569422

Claim:
A method for fabricating a chip package, comprising: providing a semiconductor chip separated from a semiconductor wafer, wherein said semiconductor chip comprises a silicon substrate, a MOS device in or over said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second dielectric layers and over said first and second metal layers, and a metal bump connected to said second metal layer through a hole in said passivation layer, wherein said a metal bump has a thickness between 5 and 150 micrometers; adhering said semiconductor chip to a substrate; after said adhering said semiconductor chip to said substrate, forming a polymer material over said substrate, on said semiconductor chip and on said metal bump; after said forming said polymer material, polishing said polymer material and uncovering a surface of said metal bump; and after said polishing said polymer material and said uncovering said surface, forming a third metal layer over said polymer material and on said surface.