Patent ID: 7903498

Claim:
A Y-decoder applied in a memory, the memory comprising a memory array, the memory array comprising a plurality of memory cells and a plurality of column lines coupled to the memory cells, the column lines comprising a first column line, a second column line, a third column line and a fourth column line arranged successively from the first to the fourth column line, and a fifth column line spacing from the fourth column with at least one column line, the Y-decoder comprising: a selection unit, coupled to the memory array for selecting the column lines; and a Y-multiplexer (Y-MUX), coupled to the selection unit for supplying a voltage to the selected column line, the Y-MUX comprising: a first switch, a second switch, a third switch and a fourth switch coupled in parallel, wherein the first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage, the third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage; wherein the Y-decoder selects and supplies the first column line with a ground voltage, selects and supplies the second column line with the first sensing voltage by turning on the corresponding third switch, selects and supplies the third column line with the second sensing voltage by turning on the corresponding fourth switch, selects and supplies the fourth column line with the first shielding voltage by turning on the corresponding first switch, allows the at least one column line to float, and selects and supplies the fifth column line with the second shielding voltage by turning on the corresponding second switch.