Patent ID: 8468510

Claim:
A method for generating a hardware specification from a high-level language (HLL) program, comprising: determining by a computing arrangement, separate accesses in the HLL program to at least two consecutively addressed data items, and that the consecutively addressed data items can be processed on parallel data paths; compiling the HLL program into an intermediate language program by the computing arrangement, the intermediate language program including two or more instructions that perform respective functions on the at least two consecutively addressed data items and a plurality of memory access instructions, one or more of the memory access instructions addressing one of the at least two consecutively addressed data items for access to all of the consecutively addressed data items; and generating a hardware specification from the intermediate language program by the computing arrangement, the hardware specification specifying: a cache memory that caches the at least two consecutively addressed data items in one addressable word of the cache memory; respective hardware blocks that implement the respective functions of the two or more instructions in the intermediate language program; and one or more respective memory access hardware blocks that implement the one or more memory access instructions; wherein each of the memory access hardware blocks is configured to generate a respective access request, and the cache memory accesses the at least two consecutively addressed data items in response to each access request, and at least two of the hardware blocks input the at least two consecutively addressed data items in parallel in the parallel data paths.