Patent ID: 8778765

Claim:
A method of manufacturing a CMOS device, the method comprising: forming a gate material stack over a workpiece, the workpiece comprising a first region and a second region, the gate material stack including a semiconductive gate material; modifying the semiconductive gate material of the gate material stack in the first region or the second region of the workpiece; patterning the gate material stack in the first region and the second region; and forming a first transistor in the first region of the workpiece and a second transistor in the second region of the workpiece, wherein modifying the semiconductive gate material of the gate material stack in the first region or the second region of the workpiece results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage being different than the first threshold voltage, wherein modifying the semiconductive gate material comprises altering the thickness of the semiconductive gate material so that the thickness of the semiconductive gate material in the first region is different from the thickness of the semiconductive gate material in the second region, wherein patterning the gate material stack in the first region and the second region of the workpiece comprises forming a first transistor in the first region of the workpiece comprising an NMOS FET of the CMOS device and forming a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device.