Patent ID: 8686990

Claim:
A scanning signal line drive circuit provided monolithically on a substrate that constitutes a display panel, and for driving a plurality of scanning signal lines arranged on the substrate, the scanning signal line drive circuit comprising: a plurality of odd-numbered line scanning circuits configured to drive odd-numbered scanning signal lines out of the plurality of scanning signal lines; a plurality of even-numbered line scanning circuits configured to drive even-numbered scanning signal lines out of the plurality of scanning signal lines; and a selection circuit configured to select a circuit to be activated out of the plurality of odd-numbered line scanning circuits and the plurality of even-numbered line scanning circuits, wherein the plurality of scanning signal lines are divided into z blocks (z is an integer equal to or greater than 2) such that each block includes k consecutive scanning signal lines (k is an integer equal to or greater than 4), one of the odd-numbered line scanning circuits and one of the even-numbered line scanning circuits are provided for each block, the selection circuit sequentially selects the first to z-th blocks one by one, and alternately selects the odd-numbered line scanning circuits and the even-numbered line scanning circuits, each of the odd-numbered line scanning circuits sequentially and selectively drives the odd-numbered scanning signal lines that are included in the corresponding block, each of the even-numbered line scanning circuits sequentially and selectively drives the even-numbered scanning signal lines that are included in the corresponding block, the selection circuit, the odd-numbered line scanning circuits, and the even-numbered line scanning circuits are each configured by a shift register having a plurality of stages each configured to output, based on an externally inputted clock signal, a state signal indicating one of a first state and a second state, and each of the stages that constitute the shift register includes: an output node for outputting the state signal; an output-controlling switching element having a second electrode to which the clock signal is supplied and a third electrode connected to the output node; a first node connected to a first electrode of the output-controlling switching element; a capacitative element provided between the output node and the first node; a first-node charging unit configured to charge the first node based on one of a start instructing signal and the state signal outputted from the output node of a previous stage; a first-node discharging unit configured to discharge the first node based on the state signal outputted from the output node of a next stage; and an output-node discharging unit configured to discharge the output node based on the state signal outputted from the output node of the next stage.