Patent ID: 8125840

Claim:
A circuit, comprising: a first inverter device having an input node and an output node; a second inverter device having an input node and an output node; a set device including a psetn device and an nset device coupled to the first inverter device and the second inverter device, the psetn device including a pair of P-type transistors coupled together at respective gates that are configured to receive a psetn signal and the nset device including a pair of N-type transistors coupled together at respective gates that are configured to receive an nset signal, wherein the psetn device and the nset device modulate a bias level by applying a pulse to the first inverter and the second inverter, enabling each inverter to independently reach a trip point that is dependent on each specific device threshold of the inverter; a gated shunt device configured to connect and disconnect the input node of the first inverter device to the output node of the first inverter device and the input node of the second inverter device to the output node of the second inverter device; a cross-coupling switch configured to enable and disable a connection of the input node of the first inverter device to the output node of the second inverter device and the input node of the second inverter device to the output node of the first inverter device; and wherein the first inverter device, second inverter device, set device, gated shunt device and cross-coupling switch are operatively coupled to perform one of a pre-charge time operation and sense time operation on a bit line having a bit line true and bit line complement connected to a storage cell from a memory device.