Patent ID: 7170819

Claim:
Integrated semiconductor memory device for synchronization of signals with a clock signal, comprising: a clock generating circuit configured to generate a first clock signal and a second clock signal that is time-shifted with respect to the first clock signal; a first control circuit configured to generate a first control signal and to generate an internal clock signal that is delayed relative to the first clock signal, wherein the first control circuit generates the first control signal synchronous with the internal clock signal at a point in time that is dependent on a received configuration signal; a second control circuit configured to generate a second control signal synchronous with the second clock signal; and a latch circuit configured to latch a first command signal and release a second command signal, the latch circuit latching the first command signal synchronous with the internal clock signal in response to the latch circuit being actuated by the first control signal and releasing the second command signal synchronous with the second clock signal in response to the latch circuit being actuated by the second control signal.