Patent ID: 7489640

Claim:
A processor comprising: controller circuitry operative to control performance of a continuity check for each of a plurality of flows of protocol data units received by the processor; and memory circuitry comprising a continuity check cache; wherein the continuity check cache stores an identifier for each of a subset of the plurality of flows; wherein the controller circuitry controls access to a set of continuity check counters comprising a counter for each of the plurality of flows; the controller circuitry determining if a given flow for which a protocol data unit is received in the processor has a corresponding entry in the continuity check cache, and if the given flow has such an entry, preventing a corresponding one of the continuity check counters from being updated, and if the given flow does not have such an entry, clearing the corresponding one of the continuity check counters and storing a flow identifier for the given flow in the continuity check cache; wherein the continuity check cache has a capacity of M entries, a given one of which may correspond to the flow identifier, and the set of continuity check counters includes N continuity check counters, where M is substantially less than N.