Patent ID: 8536008

Claim:
A manufacturing method of a vertical channel transistor array, comprising: providing a semiconductor substrate; forming a plurality of first trenches in the semiconductor substrate, wherein the first trenches are arranged in parallel and extended along a column direction; forming a plurality of embedded bit lines at bottoms of the first trenches; forming a plurality of bit line contacts, each of the bit line contacts being formed on a side surface of one of the embedded bit lines, wherein the embedded bit lines are electrically connected to the semiconductor substrate through the bit line contacts; forming a plurality of second trenches in the semiconductor substrate, wherein the second trenches are arranged in parallel and extended along a row direction, and the semiconductor substrate is divided into a plurality of semiconductor pillars by the first trenches and the second trenches; forming a gate dielectric layer on surfaces of the semiconductor pillars; forming a plurality of embedded word lines at bottoms of the second trenches; and forming a current leakage isolation structure in the semiconductor substrate to prevent current leakage between adjacent bit line contacts, wherein the current leakage isolation structure is disposed at terminals of the embedded bit lines.