Patent ID: 6982202

Claim:
A method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions, comprising the steps of: fabricating at least one trench in the top side; providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer; depositing a material provided for the gate electrode into the trench; forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant; and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.