Patent ID: 7405103

Claim:
A process for fabricating a chip embedded package structure, comprising: disposing a stiffener on a tape, wherein the tape has at least a first alignment mark and at least a second alignment mark which are located on the both sides of the tape respectively, and the stiffener has at least a chip opening; disposing a chip on the tape inside the chip opening such that an active surface of the chip faces the tape, wherein the chip also comprises a plurality of bonding pads disposed on the active surface; forming a plurality of through holes passing the tape and exposing the bonding pads respectively, wherein the through holes are formed in the tape by using the second alignment mark as a positioning reference; depositing conductive material into the though holes to form a plurality of conductive vias which are connected to the bonding pads respectively; and forming a multi-layered interconnection structure on the tape on the opposite of the chip by using the first alignment mark as a positioning reference, wherein the multi-layered interconnection structure comprises an inner circuit which is connected to the conductive vias, and the inner circuit has a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.