Patent ID: 7885093

Claim:
A method for testing a static random access memory having a plurality of memory cells, each memory cell comprising a cross-coupled inverter pair coupled between a high potential source and a low potential source, the first inverter of the inverter pair having its control terminals coupled to a first bit line via a first enable transistor, and the second inverter of the inverter pair having its control terminals coupled to a second bit line via a second enable transistor, the first and second enable transistors having their respective control terminals coupled to a word line, the method comprising: (a) writing a first bit value into a first memory cell; (b) disabling the first and second enabling transistors of the first memory cell; (c) discharging the first bit line and the second bitline coupled to the first memory cell to a low potential; (d) activating the word line coupled to the memory cell for a predetermined period whilst keeping the first bit line coupled to the first memory cell at the low potential during a predetermined part (Δ) of said period; (e) bringing said first bit line to a high potential upon completion of the predetermined part (Δ); and (f) determining the bit value of the cell under test after the predetermined period.