Patent ID: 8359557

Claim:
A method of generating a circuit design, comprising: instantiating in the circuit design in response to user input, a plurality of components including at least one processor and at least one peripheral device, the plurality of components having requirements, capabilities, and user-specified master-slave relationships; automatically selecting, by a processor, one or more parameterizable data bus interface blocks based on the requirements, capabilities, and master-slave relationships of the components; instantiating the one or more parameterizable data bus interface blocks in the circuit design; assigning values, in response to user input, to parameters of the processor; automatically determining data bus parameter values of the plurality of components and the one or more data bus interface blocks according to the parameters of the processor and capabilities and requirements of the plurality of components and one or more data bus interface blocks by propagating values of parameters between a plurality of data bus nodes representative of the plurality of components and of the one or more data bus interface blocks, and adjusting values of parameters of the plurality of components and the one or more interface blocks based on compatibility of the propagated values of parameters with the plurality of components and with the one or more interface blocks; and parameterizing the one or more data bus interface blocks and components according to the determined data bus parameters.