Patent ID: 7197653

Claim:
A microcontroller having a processor receiving as a system clock a clock signal corresponding to frequency information among a plurality of clock signals of different frequencies that are each 1/n (n is a division ratio and an integer not less than 1) an oscillation frequency, operating in synchronism with the system clock, performing fetching and decoding of an extension code, an operation code and an operand stored in a memory by pipeline processing, on an instruction program comprising the extension code, the operation code and the operand, and executing the instruction program based on a result of the decoding, wherein the operation code is structured, by a machine code, as an instruction map comprising a plurality of pages which instruction map is classified into pages each corresponding to a division ratio, wherein the extension code pipeline-processed together with the operation code is provided with information representative of a page of the instruction map, wherein the processor outputs the frequency information corresponding to the division ratio corresponding to the page of the instruction map represented by the extension code by fetching and decoding the extension code by pipeline processing, and wherein a selector is provided that selects the extension code corresponding to the division ratio in accordance with a division ratio setting description determining the division ratio of the system clock described in a source program, selects the operation code corresponding to an instruction succeeding the division ratio setting description from the page of the instruction map represented by the extension code, and converts it into a ROM code.