Patent ID: 8832630

Claim:
A circuit design aiding apparatus, comprising: a memory configured to store information about first and second pin groups to be wired to each other, the information including logical connection data that associates pins in the first pin group with pins in the second pin group; and a processor configured to perform a procedure including: selecting a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group which are associated with each other by the logical connection data, wherein distance between the first pair of pins, as well as distance between the second pair of pins, is within a specified range; and determining which pins in the first and second pin groups are to be wired in pairs, based on the selected set of pair candidates, wherein: two pair candidates are said to be adjacent when the two pair candidates share a pin in the second pin group, and the determining includes producing a graph whose nodes respectively represent the pair candidates in the selected set and whose edges represent adjacency of the pair candidates in the selected set, choosing a first node in preference to a second node in the produced graph when a smaller number of edges extend from the first node than from the second node, and determining that the first pair of pins in the pair candidate represented by the chosen first node be wired to the second pair of pins in the pair candidate represented by the chosen first node.