Patent ID: 8477276

Claim:
A thin film transistor array substrate, comprising: a transparent substrate, and a plurality of scanning lines, a plurality of data lines and a plurality of pixel regions that are formed on the transparent substrate, wherein each pixel region is formed by two adjacent scanning lines and two adjacent data lines that intersect with each other, and comprises a pixel electrode and a thin film transistor for controlling the pixel electrode, the pixel electrode is covered with an insulation layer which is provided with a pull alignment opening, and each pixel region further comprises a first push alignment electrode and a second push alignment electrode, and wherein projections of the first and the second push alignment electrodes on the transparent substrate are respectively located at two opposite sides of the pixel electrode, and when the thin film transistor array substrate is in operation, an oblique pull electric field is formed at the pull alignment opening, and transverse push electric fields are formed between the first push alignment electrode and the pixel electrode as well as between the second push alignment electrode and the pixel electrode, respectively; and wherein the insulation layer is provided with a plurality of pull alignment openings, and the plurality of pull alignment openings are arranged in a bar shape and the projections thereof on the transparent substrate are approximately located at a central position of the pixel electrode.