Patent ID: 6898544

Claim:
An integrated circuit formed on a substrate of semiconductor material, comprising; A. application circuits formed on the substrate and having a data output lead; B. a scan data input lead formed on the substrate; C. a scan clock input lead formed on the substrate; D. a mode signal input lead formed on the substrate; E. a scan cell register formed on the substrate and having a serial data input lead coupled to the scan data input lead, a data input lead connected to the data output lead of the application circuits, and a clock signal input lead; F. an instruction register formed on the substrate and having a serial data input lead connected to the scan data input lead and a clock enable signal output lead; G. an access port formed on the substrate and having a clock input lead connected to the scan clock input lead, a mode input lead connected to the mode signal input lead, and a sync signal output lead; and H. a gate formed on the substrate and having a first input connected to the clock enable signal output lead, a second input connected to the sync signal output, a third unput connected to the scan clock input lead, and a clock output connected to the clock signal input lead of the scan cell register.