Patent ID: 7393732

Claim:
A method of forming a silicon-on-insulator (SOI) metal oxide field effect transistor (MOSFET) structure comprising: providing a structure comprising an elevated device region and a recessed device region that are separated from each other by an isolation region, said elevated device region comprising a first insulator layer located on a substrate, a first semiconductor layer located on the first insulating layer, a second insulator layer located on the first semiconductor layer, and a second semiconductor layer located on the second insulator layer, and said recessed device region comprising said first insulator layer and said first semiconductor layer; forming semiconductor devices in said elevated device region and said recessed device region, the semiconductor devices including a gate conductor and a gate dielectric, wherein the gate dielectric of the semiconductor devices in the elevated device region is formed on the second semiconductor layer and the gate dielectric of the semiconductor devices in the recessed device region is formed on the first semiconductor layer; forming source/drain regions in said elevated device region that extend from the first semiconductor layer to abut a portion of the second semiconducting layer underlying the gate dielectric of the elevated device region; and forming junctions in the elevated and recessed device regions, said junctions in the recessed device region extends from an upper surface of the first semiconductor layer down to the first insulator layer, and said junctions in said elevated device region provide electric contact between the first semiconductor layer and the second semiconductor layer.