Patent ID: 8741752

Claim:
A method, comprising: depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate; removing portions of the dummy fill material to expose portions of the substrate; forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, wherein vertical portions of the spacer material are physically separated from the gate stack by the dummy fill material; removing horizontal portions of the layer of spacer material to expose portions of the substrate and the dummy fill material; removing remaining portions of the dummy fill material; depositing a dielectric layer over the exposed vertical portions of the spacer material, the substrate, and the gate stack, wherein the vertical portions of the spacer material are physically separated from the gate stack by the dielectric layer; removing portions of the dielectric layer to expose the vertical portions of the spacer material; removing the vertical portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer; and depositing a conductive material in the at least one cavity.