Patent ID: 7346761

Claim:
An arithmetic and logic device for use in a processing unit, said processing unit comprising a register file capable of outputting at least a first source operand, a second source operand, a third source operand, and a destination operand, said processing unit capable of generating a first immediate value, said arithmetic and logic device comprising: an arithmetic and logic unit having a first input, a second input, and an output; a first auxiliary computing unit, a second auxiliary computing unit, a third auxiliary computing unit, each of which has first, second, and third inputs and an output; a control unit controlling the operation of said first, second, and third auxiliary computing units; wherein the outputs of said first and second auxiliary computing units are connected to said first and second inputs of said arithmetic and logic unit respectively, said output of said arithmetic and logic unit is connected to said first input of said third auxiliary computing unit; said first immediate value and said third source operand are fed to said second and third inputs of all said auxiliary computing units; and said first source operand is fed to said first input of said first auxiliary computing unit, said second source operand is fed to said first input of said second auxiliary computing unit, and said output of said third auxiliary computing unit is fed to said destination operand.