Patent ID: 7233480

Claim:
A capacitor including an electrode laminate portion in which a plurality of internal electrodes are arranged in layers with a dielectric layer sandwiched between opposed internal electrodes, and configured such that via electrodes extending in a laminating direction of the internal electrodes electrically and alternately interconnect the internal electrodes, the capacitor comprising: a first dielectric portion comprising a dielectric layer; and a second dielectric portion comprising a dielectric layer; wherein the electrode laminate portion comprises a laminate of first electrode layers, second electrode layers, and interelectrode dielectric layers, the first electrode layers and the second electrode layers serving as the first and second internal electrodes, respectively, and the interelectrode dielectric layers serving as the dielectric layers sandwiched between the first and second electrodes; the first dielectric portion overlies the electrode laminate portion on a side of the electrode laminate portion toward a front surface of the capacitor; the second dielectric portion overlies the electrode laminate portion, in which the first electrode layers, the second electrode layers, and the interelectrode dielectric layers are laminated, the second dielectric portion being located away from the first dielectric portion such that at least part of the electrode laminate portion intervenes between the first dielectric portion and the second dielectric portion; and the second dielectric portion has a thickness which mitigates a thickness differential occurring in the electrode laminate portion as a result of lamination of the first and second electrode layers; the first dielectric portion has a thickness which contributes toward reducing inductance of the capacitor; and first and second via electrodes extend from the first dielectric portion to electrically interconnect the first and second electrode layers, respectively, in the electrode laminate portion.