Patent ID: 7984230

Claim:
A computer system comprising: a storage system comprising a controller and a plurality of flash memory devices, each of the plurality of flash memory devices including a plurality of flash memory chips configured as enable to erase data completely on a flash memory chip basis, wherein the controller controls to providing a plurality of logical volumes with the plurality of flash memory devices to a host computer, and controls to reading or writing data stored in the plurality of logical volumes in response to a request from the host computer; and a management computer managing relation information of the plurality of logical volumes and a plurality of parity groups of the plurality of flash memory devices, in which a total storage capacity of each parity group is calculated by unallocated flash memory chips of the plurality of flash memory chips corresponding to each parity group, wherein when the management computer receives a logical volume creation request to create a first logical volume, the management computer determines whether a storage capacity of the first logical volume is less than or equal to the total storage capacity of the unallocated flash memory chips, based on the relation information, and wherein when the storage capacity of the first logical volume is less than or equal to the total storage capacity of the unallocated flash memory chips, the management computer specifies one or more flash memory chips of the unallocated flash memory chips as dedicated flash memory chips for the first logical volume, and allocates the dedicated flash memory chips to the first logical volume of a first parity group of the flash memory devices based on the relation information so that the dedicated flash memory chips are not shared between the first logical volume and other logical volumes of the plurality of logical volumes.