Patent ID: 8373209

Claim:
A semiconductor device comprising: a substrate having a first surface and made of semiconductor material; and a depletion mode JFET and an enhancement mode JFET, which are disposed in the substrate, wherein the depletion mode JFET includes: a concavity disposed on the first surface of the substrate; a channel layer epitaxially grown on the substrate and having a first conductive type, wherein the channel layer is disposed in the concavity; a first gate region epitaxially grown on the channel layer and having a second conductive type; a first source region and a first drain region disposed on respective sides of the first gate region in the channel layer, wherein each of the first source region and the first drain region has the first conductive type and an impurity concentration higher than the channel layer; a first gate electrode electrically coupled with the first gate region; a first source electrode electrically coupled with the first source region; and a first drain electrode electrically coupled with the first drain region, wherein the enhancement mode JFET includes: a convexity disposed on the first surface of the substrate; the channel layer disposed on the convexity; a second gate region epitaxially grown on the channel layer and having a second conductive type; a second source region and a second drain region disposed on respective sides of the second gate region in the channel layer, wherein each of the second source region and the second drain region has the first conductive type and an impurity concentration higher than the channel layer; a second gate electrode electrically coupled with the second gate region; a second source electrode electrically coupled with the second source region; and a second drain electrode electrically coupled with the second drain region, and wherein a thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.