Patent ID: 8175216

Claim:
A shift register circuit comprising: an input terminal; an output terminal; a clock terminal; a first transistor for charging said output terminal by providing a constant first power supply potential to said output terminal; a second transistor for discharging said output terminal; a pull-up driving circuit for driving said first transistor; and a pull-down driving circuit for driving said second transistor, wherein said pull-up driving circuit includes: a third transistor for providing a clock signal provided at said clock terminal to a first node connected to a control electrode of said first transistor; and a boosting circuit for increasing a potential at said first node, wherein a control electrode of said third transistor is charged when an input signal input to said input terminal is activated, and the control electrode of said third transistor is discharged when said first node is charged by activation of the clock signal, wherein said pull-down driving circuit discharges a control electrode of said second transistor before the charging of said first node by activation of the clock signal begins, and wherein said boosting circuit increases the potential at said first node after the control electrode of said third transistor is discharged.