Patent ID: 8492230

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing an SOI substrate including a substrate layer, a buried insulating layer formed over the substrate layer and a semiconductor layer formed over the buried insulating layer; and (b) forming a first MISFET in a first region of the SOI substrate, wherein the step (b) includes the steps of: (b1) forming a fin in a rectangular parallelepiped shape with the long side in a first direction, a first source region connected to one end of the fin, and a first drain region connected to the other end of the fin by processing the semiconductor layer of the SOI substrate; (b2) forming a first gate insulating film over the surface of the fin; (b3) forming a first conductor film covering the fin, over the SOI substrate in which the fin is formed; (b4) forming a hard mask film over the first conductor film; (b5) patterning the hard mask film; (b6) forming a first gate electrode disposed so as to cross over the surface of the fin is the first gate insulating film in a region that extends in a second direction intersecting the first direction and intersects the fin by processing the first conductor film using the patterned hard mask film as a mask; (b7) introducing conductive impurities into the fin exposed from the first gate electrode, the first source region and the second drain region; (b8) after the step (b7), forming a first insulating film over the SOI substrate; (b9) forming a second insulating film over the first insulating film; (b10) forming a third insulating film over the second insulating film; (b11) removing the third insulating film formed on the side wall of the fin while leaving the third insulating film on the side wall of the first gate electrode by subjecting the third insulating film to anisotropic etching up to the removal of the third insulating film formed on the side wall of the fin; (b12) removing the second insulating film formed on the side wall of the fin while leaving the third insulating film and the second insulating film on the side wall of the first gate electrode by etching the second insulating film using the remaining third insulating film as a mask; (b13) removing the first insulating film formed on the side wall of the fin while leaving the first insulating film, the second insulating film and the third insulating film on the side wall of the first gate electrode to form a sidewall including the first insulating film, the second insulating film and the third insulating film by etching the first insulating film using the remaining third insulating film and second insulating film as a mask; and (b14) introducing conductive impurities into the fin exposed from the sidewall, the first source region and the first drain region.