Patent ID: 7401210

Claim:
Apparatus for performing data processing operations specified by program instructions, said apparatus comprising: return logic responsive to a return instruction having an address as an input operand to trigger a return to execution of a program instruction indicated by said address; wherein (i) if said address has a value not matching any of a plurality of predetermined address values, then said return logic triggers a procedure return instruction response being a return from a procedure call and comprising one or more first return instruction response operations to yield a first returned state; and (ii) if said address has a value matching one of said plurality of predetermined address values, then said return logic triggers an exception return instruction response being a return from an exception call and comprising one or more second return instruction response operations to yield a second returned state, said one or more second return instruction response operations differing from said one or more first return instruction response operations; wherein said address when matching one of said plurality of predetermined address values includes one or more bits encoding state variables of said apparatus other than address values to be restored by said one or more second return instruction response operations.