Patent ID: 7022560

Claim:
A method of manufacturing a high voltage, high speed MOS transistor, comprising the steps of: forming in a semiconductor substrate of a first conductivity type a buried first well region of a second conductivity type, wherein the first well region is formed by high energy implantation to locate the first well region deep within the substrate, forming a second well region of the first conductivity type between the surface of the substrate and the first well region, wherein the second well region is formed by high energy implantation to locate the second well region between the surface of the substrate and the first well region, forming channel areas of the first conductivity type by ion implantation inside the second well region, forming gate regions on the surface of the substrate, forming a weakly doped extended drain region by ion implantation inside the second well region, forming source, drain and sinker regions having a heavy doping of the second conductivity type, the source regions being formed within the channel areas, and forming contact plugs of the second conductivity type extending from the surface of the substrate to the first well region by ion implantation.