Patent ID: 7391270

Claim:
A phase locked loop, comprising: a phase detector having a reference input, a feedback input, and a control output, wherein the phase detector is configured to output a control signal at the control output based on a frequency comparison of signals applied to the reference input and to the feedback input, respectively; a loop filter coupled to the control output of the phase detector and configured to produce and output a regulating signal at an output thereof; a frequency-controllable oscillator having a regulating input coupled to the output of the loop filter and configured to generate an output signal at a frequency (f out ), wherein the frequency (f out ) of the output signal is a function of the regulating signal at the regulating input thereof; a frequency divider circuit having a frequency division ratio (N) that is set at a setting input thereof, the frequency divider circuit further comprising an input connected to the output of the oscillator, and an output coupled to the feedback input of the phase detector, wherein the frequency divider circuit is configured to output a feedback signal at a frequency which is derived from the frequency (f out ) of the oscillator output signal and the frequency division ratio (N); a control circuit configured to output a setting signal to the setting input of the frequency divider circuit, wherein the control circuit is configured to produce the setting signal from a signal that defines the frequency division ratio to be set and a phase correction signal; and a phase correction apparatus configured to generate and output the phase correction signal to the control circuit, wherein the phase correction signal is derived from a time profile for a phase drift in the output signal of the oscillator.