Patent ID: 7085796

Claim:
Apparatus for use in summing at least two binary values, comprising: a binary adder circuit responsive to a first binary value, a second binary value and a carry value, and operative to generate a binary output signal S(n) representative of a summation of the first binary value, the second binary value and the carry value, the binary adder circuit having dynamic logic, without inversion of signals driving one or more dynamic nodes associated with the dynamic logic, for implementing an exclusive OR function that generates the binary output value without one of a positive and a negative complementary version of the carry value; wherein the binary output signal S(n) is implemented in accordance with an expression: ^(p(n)*C(n−1))*(p(n)+C(n−1)), where C(n−1) is a generate signal from a binary value n−1 associated with the carry value, p(n) is a propagate signal associated with the first binary value and the second binary value, ^ is a logical complement operator, * is an AND operator, and + is an OR operator.