Patent ID: 7903380

Claim:
An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an input/output pad of an electronic circuit, the ESD protection circuit comprising: an electrostatic discharge (ESD) circuit that, upon an activation, discharges an ESD from a first voltage bus to a second voltage bus, the second voltage bus being at a lower electrical potential than the first voltage bus; and an ESD discharge control circuit in electrical connection with the ESD discharge circuit, the ESD discharge control circuit controlling the activation of the ESD discharge circuit and including at least one NMOS transistor and at least one electrical node, the at least one NMOS transistor regulating a rate of voltage decay of the at least one electrical node from a predetermined high voltage level to a predetermined low voltage level, the regulation of the rate of voltage decay of the at least one electrical node being non-linear, and the activation of the ESD discharge circuit being determined by the rate of voltage decay of the at least one electrical node.