Patent ID: 7606992

Claim:
A method for communicating between an IO bus and flash memory banks DEVICE A and DEVICE B, wherein the IO bus comprises signals SYS WE (Write Enable) and SYS DATA (SYSTEM DATA), both signals being data bit streams having a period pl, the method comprising the steps of: 1) generating a WE A (WRITE ENABLE to DEVICE A) signal WE having a period pl; 2) generating a WE B (WRITE ENABLE to DEVICE B) signal having a period pl; 3) generating a DATA A (DATA TO DEVICE A) signal whose valid start time is triggered by a rising edge of SYS WE, and whose value is that of the SYS DATA signal at the time of the rising edge of SYS WE, and maintained at that value for a period 2pl; 4) writing the DATA A into DEVICE A, triggered by the WE A signal; 5) generating a DATA B signal whose valid start time is triggered by the falling edge of SYS WE, and whose value is that of the SYS DATA signal at the time of the falling edge of SYS WE, and maintained at that value for a period 2pl; 6) writing the DATA B into DEVICE B, triggered by the WE B signal; and 7) repeating steps 3) through 6 for each successive rising edge of SYS WE, so that the bits of the data bit stream of SYS DATA are alternately written into DEVICE A and then into DEVICE B, each such writing done with a period of twice that of SYS DATA, and therefore at a frequency of one-half that of SYS DATA.