Patent ID: 7940130

Claim:
A phase-locked loop (PLL), comprising: a voltage controlled oscillator (VCO) adapted to receive a control signal and in response thereto to output a VCO output signal having a VCO frequency; a plurality, N, of sampling phase detectors, each of the sampling detectors adapted to receive a sampling signal and the VCO output signal and in response thereto to output a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a phase & frequency detector adapted to receive a reference signal from a reference oscillator, and adapted to receive a combined beat signal produced by combining the beat signals output by the plurality of sampling phase detectors, and in response thereto to produce an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator adapted to receive the error signal and in response thereto to produce the control signal for the VCO; a power detector adapted to detect a power level of the combined beat signal; and at least N−1 offset voltage generators, each offset voltage generator being adapted to adjust a value of a corresponding bias voltage in response to the detected power level of the combined beat signal, and to apply the adjusted corresponding bias voltage to a corresponding one of the sampling phase detectors.