Patent ID: 8705270

Claim:
A semiconductor memory comprising: a first switch circuit having a first end connected to a first end of a first bit line; a second switch circuit having a first end connected to a first end of a second bit line; a row decoder that controls a voltage of a word line; a first writing circuit including a first signal terminal connected to a second end of the first switch circuit to input and output a writing current, a second writing circuit including a second signal terminal connected to a second end of the second switch circuit to input and output the writing current, a select transistor including a control terminal connected to the word line; and a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line, wherein the first switch circuit includes a first pMOS transistor connected between the first end of the first bit line and the first signal terminal and a first nMOS transistor connected in parallel with the first pMOS transistor between the first end of the first bit line and the first signal terminal, the second switch circuit includes a second pMOS transistor connected between the first end of the second bit line and the second signal terminal and a second nMOS transistor connected in parallel with the second pMOS transistor between the first end of the second bit line and the second signal terminal, and the first pMOS transistor is larger in size than the first nMOS transistor.