Patent ID: 7555687

Claim:
A method of testing an integrated circuit containing a plurality of portions connected by corresponding interface logics, each of said plurality of portions containing a corresponding plurality of memory elements, said method comprising: performing intra-portion testing of each of said plurality of portions separately using sequential scan techniques; forming an inter-portion scan chain containing a set of memory elements, wherein said set of memory elements is less than said plurality of memory elements, said set of memory elements containing (a) memory elements in the fan-out of the inputs to each of said plurality of portions, (b) memory elements in the fan-in of the outputs of each of said plurality of portions, (c) memory elements connected to combinatorial logic propagating data inputs to the memory elements of (a), and (d) memory elements connected to provide control signals to (a), (b) and (c); and performing testing on said inter-portion scan chain using sequential scan techniques to test inter portion logic including said interface logics.