Patent ID: 8418098

Claim:
A verification system for verifying an integrated circuit design, the verification system comprising: a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design, wherein the step of identifying comprises: traversing a hierarchy of the integrated circuit design; selecting a first and a second block in the hierarchy of the integrated circuit design; determining a first long-channel device ratio of the first block and a second long-channel device ratio of the second block, wherein the first long-channel device ratio is greater than a pre-determined reference analog device ratio, and wherein the second long-channel device ratio is no greater than the pre-determined reference analog device ratio; placing the first block into the potential sensitive circuits; and leaving the second block out of the potential sensitive circuits; a search module configured to: find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits; and an analyze module configured to: find power nodes and ground nodes of the potential sensitive circuits; and provide the power nodes and the ground nodes to the search module; and wherein the functional block finding module, the search module, and the analyze module are implemented by a computer.