Patent ID: 7454676

Claim:
A method for testing semiconductor chips, in which at least one test mode is set in a chip which is to be tested and has a test logic unit, the test mode is executed in the chip, and a status of the test mode or test results are output from the chip, the method comprising: providing the chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers, n and m being natural numbers greater than or equal to 1; programming the m different register groups by filling the m different register groups with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out the test results or the status of the n test modes, wherein at least one of the m first bit strings is provided with at least one binary check bit, a check bit in a first logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are skipped until another check bit in a second logic state is detected by the test logic unit, and a check bit in the second logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are not skipped until another check bit in the first logic state is detected by the test logic unit.