Patent ID: 7973570

Claim:
A sample-and-hold (S/H) circuit, comprising: a sample-and-hold switch, comprising: a first switch comprising a first gate, a first source and a first drain; a second switch comprising a second gate that receives a clock signal (CLK), a second source coupled in series to the first drain, a second drain, and a bulk region, the bulk region being electrically coupled to the second source; and a third switch comprising a third gate that receives an inverted clock signal (ICLK), a third drain, and a third source directly coupled to the first source; an integrator circuit for generating an output voltage (V OUT ) signal, and comprising: an output operational amplifier having an output, an inverting input (V − ) coupled to the second drain and a non-inverting input (V + ); and a hold capacitor having a first terminal coupled to the output of the output operational amplifier and a second terminal coupled to the inverting input of the output operational amplifier; and a bias voltage (V BIAS ) source coupled to the third drain and the non-inverting input (V + ) to apply a bias voltage (V BIAS ) to the third drain and the non-inverting input (V + ).