Patent ID: 8181073

Claim:
A SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising: a flip-flop circuit comprising: a master latch circuit comprising: a master feed-back circuit comprising a master storage node, and a master feed-forward circuit, wherein the master feed-forward circuit provides a control signal for writing to the master storage node, and a slave latch circuit comprising: a slave feed-back circuit comprising a slave storage node, and a slave feed-forward circuit operatively driven from the master latch, wherein the slave feed-forward circuit provides a control signal for writing to the slave storage node, a scan control circuit comprising: a scan slave feed-forward circuit providing a control signal for writing a scan data to the slave storage node, a scan latch circuit comprising: a scan feed-back circuit comprising a scan storage node, a scan feed-forward circuit operatively driven from the slave latch, wherein the scan feed-forward circuit provides a control signal for writing to the scan storage node, and a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and a scan master feed-forward circuit operatively driven from the scan latch, wherein the scan master feed-forward circuit provides a control signal for writing to the master storage node, and an output buffer circuit comprising: a master driver, with a master output port, operatively driven from the master latch, and a slave driver, with a slave output port, operatively driven from the slave latch.