Patent ID: 7266667

Claim:
A method for accessing a memory device having multiple address modes comprising: if a single address mode is selected, receiving multiple portions of a single address over first and second sets of lines, accessing first and second memory arrays of the memory device using the single address and using the first and second sets of lines to receive or transmit data; and if a multiple address mode is selected, receiving multiple portions of first and second addresses over the first and second sets of lines, accessing the first memory array using the first address and using the first set of lines to receive or transmit data, and accessing the second memory array using the second address and using the second set of lines to receive or transmit data, wherein receiving multiple portions of first and second addresses over first and second sets of lines in the multiple address mode comprises: receiving first and second portions of the first address over the first set of lines in sequential clock cycles; and receiving first and second portions of the second address over the second set of lines in a sequential clock cycles.