Patent ID: 7671641

Claim:
A frequency divider comprising, a first latch comprising a clock input for receiving a clock signal; a second latch comprising a latch circuit configured as a low-pass filter, the second latch being cross-coupled to the first latch; and wherein the second latch comprises a differential pair of transistors including a first pair of transistors comprising a first transistor coupled to a second transistor a second pair of transistors comprising a third transistor coupled to a fourth transistor each transistor having a drain, a source and a gate, the drain of the first transistor and the drain of the third transistor being coupled to the source of the second transistor and to the source of the fourth transistor respectively, the gates of the second transistor and the fourth transistor receiving a signal generated by the first latch, the gates of the first transistor and the third transistor being coupled to a control signal for determining a low-pass characteristic of the second latch, and wherein the control signal is a DC signal.