Patent ID: 7186641

Claim:
A method of forming a metal interconnection line for a semiconductor device, the method comprising: forming a first metal layer on a semiconductor substrate; forming a second metal layer comprising aluminum, aluminum alloy, copper, tungsten, or a metal silicide layer on the first metal layer. forming plugs by patterning the second metal layer; forming a glue layer comprising Ti, Ti/TiN, Ta, or Ta/TaN to cover surfaces of the plugs; forming lower metal interconnection lines by patterning the first metal layer, wherein forming the lower metal interconnection lines comprises: forming a mask pattern having larger width than that of the plug on the first metal layer to cover the plugs; etching the first metal layer using the mask pattern and plugs; and removing the mask pattern; and forming an interlayer insulating layer having a planarized surface on the substrate to fill gaps between the lower metal lines and between the plugs.