Patent ID: 8363485

Claim:
An integrated circuit comprising: a latching element comprising a data input lead, a clock input lead, a data path portion, and a clock path portion; a data terminal that is coupled to the data input lead of the latching element such that a data signal on the data terminal passes to the data input lead of the latching element and then through the data path portion of the latching element; a clock input terminal; and an open-loop replica of the data path portion of the latching element, wherein the open-loop replica is coupled such that a clock signal on the clock input terminal passes through the open-loop replica to the clock input lead of the latching element and then through the clock path portion of the latching element, wherein the latching element is a single latch, wherein an edge of the clock signal causes data information communicated by the data signal to be latched into the single latch, and wherein the single latch is a first latching element of the integrated circuit into which the data information is latched.