Patent ID: 8503323

Claim:
An integrated circuit comprising: A. processor circuitry; and B. embedded instructions for operating the embedded circuitry, the embedded instructions providing for: i. receiving in a buffer a first packet of real-time information for one communication channel; ii. determining a first deadline time for the first packet, the first packet having a first deadline time for being decoded by the processing unit, past which first deadline time the first packet is discarded if not decoded; iii. starting decoding the first packet with the processing unit; iv. receiving in the buffer a second packet of real-time information for another communication channel after the starting decoding of the first packet; v. determining a second deadline time for the second packet, the second packet having a second deadline time for being decoded by the processing unit, past which second deadline time the second packet is discarded if not decoded, and the second deadline time being before the first deadline time; vi. testing to determine whether the second packet can be decoded ahead of the second deadline time by continuing decoding the first packet and then decoding the second packet; vii. placing the second packet in a queue if the second packet can be decoded ahead of the second deadline time by continuing decoding the first packet and then decoding the second packet; and viii. stopping decoding of the first packet and starting decoding of the second packet if the second packet cannot be decoded ahead of the second deadline time by continuing decoding the first packet and then decoding the second packet.