Patent ID: 8320158

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of first and second lines intersecting each other and a plurality of memory cells provided at intersections of the first and second lines and having data written thereinto and erased therefrom upon application of voltages; and a writing circuit configured to select the first and second lines and supply a set pulse or a reset pulse to the memory cell through the selected first and second lines, in an erase operation, the writing circuit being configured to repeatedly supply the reset pulse to a selected one of the memory cells until data is erased from the selected memory cell, by increasing or decreasing the voltage level and the voltage application time of the reset pulse within a reset region, the reset region being an aggregate of combinations of voltage level and voltage application time of the reset pulse, and the reset region being a region in which the voltage level and the voltage application time are inversely correlated with each other, and in an erase operation, the writing circuit controlling the voltage level and the voltage application time of the reset pulse outside a set region which is an aggregate of combinations of voltage level and voltage application time of the set pulse.