Patent ID: 8104009

Claim:
A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD), wherein the routing graph includes routing graph wires and routing graph switches, the method comprising: maintaining in a computing system a plurality of master tiles, wherein each of the master tiles includes as data objects master wires and master switches corresponding to the routing graph wires and the routing graph switches, respectively, and also stores a pattern of connections between the master wires and master switches; and mapping in the computing system a first routing graph wire to a second routing graph wire, wherein the mapping includes: identifying a master tile that represents the connection pattern of the first routing graph wire in the routing graph; mapping the first routing graph wire to a first master wire in the identified master tile; mapping the first master wire to a master switch in the identified master tile; identifying a segmented wire connected to the master switch; mapping the identified segmented wire to a second master wire in the identified master tile; and mapping the second master wire to the second routing graph wire.