Patent ID: 7055077

Claim:
A system for testing circuitry comprising: a plurality of scan chains extending between functional logic components of a circuit to be tested, and connected to each other through the functional logic components, each of the scan chains including a plurality of scan latches disposed correspondingly to levels of functional logic; a pseudorandom pattern generator (PRPG) coupled to the scan chains and configured to generate a pseudorandom pattern of bits to be scanned into the scan chains; a controller configured to control test cycles, each of which includes a functional phase in which data is propagated between the scan chains through the functional logic components, and a scan phase in which data is shifted into and out of the scan latches through the scan chains; and a plurality of local control buffers (LCBs) coupled to the scan latches to supply the scan latches with clock signals indicating the number of levels of functional logic through which data is propagated during the functional phase, each LCB of the plurality of LCBs being configured to vary the number of levels of functional logic to be indicated.