Patent ID: 7889574

Claim:
A semiconductor memory device, comprising: a pair of data lines; a first driving unit comprising a first CMOS transistor, configured to drive an input signal to one of the pair of data lines; a second driving unit comprising a second CMOS transistor, configured to drive an input signal to the other data line; a precharging/equalizing unit comprising at least two MOS transistors, configured to precharge and equalize the pair of data lines; a first clamping unit configured to supply a source voltage of the first CMOS transistor in response to a bulk bias voltage of the first CMOS transistor; a second clamping unit configured to supply a source voltage of the second CMOS transistor in response to a bulk bias voltage of the second CMOS transistor; and a third clamping unit configured to supply a source voltage of the two MOS transistors in response to a bulk bias voltage of the two MOS transistor.