Patent ID: 7093052

Claim:
An integrated circuit comprising: a bus; and a plurality of devices coupled to the bus in which individual devices include respective agents coupled to the bus to receive a clock signal having a rising edge and a falling edge, the agents to drive an arbitration signal onto the bus responsive to one of the rising or falling edge and to sample the arbitration signal on the bus responsive to other of the falling or rising edge and to evaluate the arbitration prior to a subseciuent cycle of the clock cycle to allow one agent to request and win arbitration of the bus in one clock cycle, the one agent winning arbitration to drive an address of a transaction responsive to one of the rising or falling edge of the subsequent clock cycle and agents involved in coherency to sample and evaluate the address responsive to other of the falling or rising edge of the subsequent clock cycle and to respond with coherent response signals on the bus at a fixed number of clock cycle or cycles after the address to maintain order for coherency, but in which data driven onto the bus in response to the address need not be maintained at a fixed number of clock cycle or cycles after the address to allow data to be driven out of order on the bus.