Patent ID: 6845044

Claim:
An array of CMOS memory cells, each memory cell in the array comprising: a PMOS transistor having a source coupled to Vcc, a drain and a floating gate, the PMOS transistor having ion implantation in a substrate between its source and drain to set a first threshold value for the PMQS transistor; an NMOS transistor with a source coupled to Vss, a drain in common with the PMOS transistor and a floating gate in common with the PMOS transistor; a control capacitor having one terminal in common with the floating gate; a tunneling capacitor having one terminal in common with the floating gate and a second terminal; and a pass transistor having a source-drain path connected to the second terminal of the tunneling capacitor, wherein the first threshold value is set so that charge cannot be provided to the floating gate causing both the NMOS and the PMOS transistor to be turned on together.