Patent ID: 8841667

Claim:
A transistor structure disposed on a substrate, the transistor structure comprising: a gate electrode; a gate insulating layer overlapping the gate electrode; a channel layer overlapping the gate electrode, the gate insulating layer being located between the channel layer and the gate electrode; a first connection line overlapping the gate electrode, the first connection line being arranged along a first direction, the gate insulating layer being located between the first connection line and the gate electrode; a plurality of first electrodes and a plurality of second electrodes, the first and second electrodes overlapping the gate electrode, the gate insulating layer being located among the first electrodes, the second electrodes, and the gate electrode, the first electrodes being located at two sides of the first connection and the first connection line being located between a part of the first electrodes and another part of the first electrodes, the second electrodes being located at two sides of the first connection line and the first connection line being located between a part of the second electrodes and another part of the second electrodes, the first and second electrodes being alternately arranged along the first direction at the two sides of the first connection, the first electrodes being electrically connected to the first connection line, wherein each of the first electrodes has a first width along the first direction, each of the second electrodes has a second width along the first direction, and a ratio of the first width to the second width ranges from 2 to 20; and a second connection line arranged along the first direction and electrically connected to the second electrodes.