Patent ID: 7927940

Claim:
A method of manufacturing an integrated circuit, comprising: forming first and second isolation structures over a substrate; fabricating laterally diffused metal oxide semiconductor (LDMOS) transistors, including: forming a lightly-doped source/drain region with a first dopant within the substrate, the lightly-doped source/drain region located between the first and second isolation structures; and creating a gate over the lightly-doped source/drain region; diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel; placing a heavy concentration of the first dopant in a region adjacent the second dopant proximate a source side of the gate, and in the lightly-doped source/drain region adjacent a drain side of the gate; depositing interlevel dielectric layers over the LDMOS transistors; and creating interconnect structures in the interlevel dielectric layers and interconnecting the LDMOS transistors to form an operative-integrated circuit.