Patent ID: 7791393

Claim:
A clock generating circuit comprising: a source clock; a first clock generated from the source clock through a first header; a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock; a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge; and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge; wherein the first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain, the second delayed falling edge clock is generated from a second leading edge path and a second falling edge path, both originating from the source clock, that are inputted to a second delay chain, the first leading edge path connects the source clock to a first input of the first delay chain, the first falling edge path connects the source clock to a second input of the first delay chain through the first header and one or more inverters, the second leading edge path connects the source clock to a first input of the second delay chain through an inverter, the second falling edge path connects the source clock to a second input of the second delay chain through the second header and one or more inverters, each delay chain comprises a two-input NOR gate in series with one or more inverters, the output of the first delay chain is the first delayed falling edge clock, and the output of the second delay chain is the second delayed falling edge clock.