Patent ID: 7990189

Claim:
A power-up signal generating circuit, comprising: a detecting unit configured to receive an internal reference voltage and a deep power down (DPD) signal and to output a bias signal having a voltage level corresponding to an external power voltage in response to the internal reference voltage and the DPD signal; and a signal generating unit configured to generate a power-up signal having a logic level corresponding to the voltage level of the external power voltage in response to the DPD signal and the bias signal, wherein the internal reference voltage increases during an activation time of the power-up signal to reach a predetermined voltage level after a predetermined time and maintains a ground voltage level during an inactivation period of the power-up signal, wherein the signal generating unit includes a third PMOS transistor coupled between a power voltage terminal and a second node and configured to be controlled by the DPD signal, a second NMOS transistor coupled between the second node and a third node and configured to be controlled by the bias signal, a first inverter configured to invert a signal output from the third node, and a latch unit configured to latch an output signal of the first inverter in response to the DPD signal.