Patent ID: 8543740

Claim:
An apparatus comprising an integrated circuit (IC) that is configured to operate as an inter-integrated circuit (I2C) slave connected to a master coupled to an I2C bus, wherein the IC includes: a data-in terminal; a clock-in terminal; a data-out terminal; a clock-out terminal; a first register that is coupled to the data-in terminal and the clock-in terminal, wherein the first register is configured to store an address transmitted by the master over the I2C bus; an acknowledge circuit that is coupled to the data-in terminal and the clock-in terminal, wherein the acknowledge circuit is configured to generate a not-acknowledge signal when no other slave has acknowledged the address as its address; a logic circuit that is coupled to the acknowledge circuit, wherein the logic circuits receives the generated not-acknowledge signal; and a second register that is coupled to the logic circuit and the first register, wherein the second register is configured to receive the address from the first register when the acknowledge circuit generates the not-acknowledge signal and the IC is configured to be identified by the address when the address is stored in the second register.