Patent ID: 7035988

Claim:
A hardware queue circuit for managing a plurality of linked lists comprising: a head of queue (HOQ) memory to store information representative of a head entry associated with each of the linked lists; a tail of queue (TOQ) memory to store information representative of a tail entry of each of the linked lists; a data memory to store data associated with entries of the linked lists; a next pointer memory; an address bus configured to selectively deliver information the HOQ memory and from the TOQ memory to the data memory in order to access a memory location in the data memory and to the next pointer memory in order to access a memory location in the next pointer memory; a free pointer memory; a first data bus configured to deliver data from an accessed memory location in the next point memory to the free pointer memory and to the HOQ memory; and a second data bus configured to deliver data from an accessed memory location in the free pointer memory to an accessed memory location in the next pointer memory.