Patent ID: 8185791

Claim:
A processing stage within a data processing apparatus for processing a signal, said processing stage comprising: an input for receiving said signal, processing circuitry for processing said signal and an output for outputting said processed signal at an output time; an error detecting circuit for determining if a signal output by said processing stage between said output time and a predetermined time later does not have a stable value, said predetermined time later being before a next output time, and for signalling an error if said signal is not stable; a tuning circuit for adjusting at least one operational parameter of said processing stage, said at least one operational parameter comprising at least one of an operating voltage of said processing stage and an operating frequency of a clock clocking said processing stage; a tuning limiting circuit for providing at least one tuning limit for said tuning circuit to prevent said at least one operational parameter being adjusted beyond said corresponding at least one tuning limit, wherein when said processing stage is tuned to said tuning limit, a signal passing along a critical path of said processing stage is expected to reach said output of said processing stage at a preset time later than said output time, said preset time being less than said predetermined time.