Patent ID: 7529224

Claim:
A scheduler in a network processor, comprising: memory to store schedule control blocks in a first, second, and third linked list of schedule control blocks, each schedule control block associated with a queue and a weight and comprising a counter; first, second, and third calendar entries associated with the first, second, and third linked lists, respectively, each calendar entry adapted to store an address for a first-out schedule control block in the linked-list of schedule control blocks associated with the calendar entry; control circuitry to increment a counter of a first-out schedule control block from one of the first and second linked lists; and to move the first-out schedule control block from the one linked list to the other of the first and second linked lists if the incremented counter is less than the weight of the schedule control block, and to move the first-out schedule control block from the one linked list to the third linked list if the incremented counter equals or exceeds the weight.