Patent ID: 7237087

Claim:
A reconfigurable processor, comprising: a plurality of data buses adapted to transmit data; a plurality of addressable configurable cell units arranged as a multidimensional array, interconnected by the plurality of data buses, and adapted to process the data transmitted by the plurality of data buses, at least some of the configurable cell units including: an arithmetic-logic unit configured to perform mathematical and logical functions on the data; a function control unit in communication with the arithmetic-logic unit and adapted to control a function performed by the arithmetic-logic unit; and an interconnection control unit adapted to control interconnection of the at least some of the configurable cell units with other configurable cell units, the at least some of the configurable cell units adapted to carry out a same one of a number of possible operations in response to a same one of a number of possible instructions, a response of any one of the at least some of the configurable cell units being statical and identical to a response of any other of the at least some of the configurable cell units, wherein the plurality of configurable cell units are reconfigurable at run time in their function and interconnection; and a primary function control unit adapted to control at least some of the function control units by transmitting instructions that statically correspond to one of the possible operations and at least some of the interconnection control units; wherein the at least some of the configurable cell units are arranged to provide for a decoupling of the at least some of the configurable cell units from the plurality of data buses, and wherein a cell/bus decoupling provides for a reconfiguration at runtime of at least one of the at least some of the configurable cell units without affecting a configuration of other ones of the at least some of the configurable cell units.