Patent ID: 7370168

Claim:
A memory card conforming to a first operation standard, a second operation standard, and a third operation standard based on the first operation standard, comprising: a non-volatile semiconductor memory having a plurality of semiconductor memory cells, wherein each said memory cell is capable of storing information, and a controller that executes operation instructions to the non-volatile semiconductor memory based on received commands, wherein the controller controls a first data output timing that satisfies the first operation standard and the second operation standard, in a first operation mode, and controls a second data output timing that satisfies the third operation standard, in a second operation mode; and wherein the controller includes a data timing switching unit that outputs data at a falling edge of a clock signal in the first data output timing, and outputs data at a rising edge of a clock signal in the second data output timing; wherein the data timing switching unit includes: a timing register to which one of the first data output timing and the second data output timing is set, a first latch that latches an output data enable signal based on an inverted signal of the clock signal, a second latch that latches the data based on the inverted signal of the clock signal, a first selector that inputs the output data enable signal and a first latch signal outputted from the first latch, and selects and outputs one of the output data enable signal and the first latch signal based on a value set to the timing register, and a second selector that inputs the data and a second latch signal outputted from the second latch, and selects and outputs one of the data and the second latch signal based on the value set to the timing register, and wherein the data timing switching unit outputs: the output data enable signal and the data to an output buffer from the first selector and the second selector, respectively, when the first data output timing is set to the timing register, and the first latch signal and the second latch signal to the output buffer from the first selector and the second selector, respectively, when the second data output timing is set to the timing register, wherein the output buffer outputs the data based on the output data enable signal to output the data at the rising edge of the clock signal, and outputs the data based on the second latch signal in synchronization with the first latch signal to output the data at the falling edge of the clock signal.