Patent ID: 6990648

Claim:
A method for identifying, in a VLSI chip design, one or more circuits placed in a region of wiring congestion which can be replaced such that all associated pin to pin connections are reduced in length, including the steps of: (a) identifying one or more circuits in a region of wiring congestion whose placement can be modified in order to reduce net length on each of said circuits' net connections without increasing the length of any particular pin to pin segment and determining placement locations of all the circuits connected to a particular circuit, excluding the coordinates of that particular circuit itself, within the region of wiring congestion without increasing the length of any pin to pin connections of said that particular circuit of each of said circuits; and (b) for each of said circuits in step (a), determining placements of all circuits to which each of said circuits is connected; and (c) for each of said circuits in step (a), determining whether each of said circuits lie outside a connectivity rectangle corresponding to the circuits to which it connects.