Patent ID: 7542533

Claim:
An integrated circuit including a clock and data recovery (CDR) circuit, the CDR circuit generating a clock signal based on an input data signal having a period 2τ and including a plurality of data state transitions, the CDR circuit comprising: a first delay arrangement for generating a gating signal of duration τ based on the data state transitions of the input data signal, wherein the first delay arrangement includes a first delay element; a gated voltage-controlled oscillator coupled to the first delay arrangement in such a way that the gating signal enables the gated voltage-controlled oscillator, wherein the gated voltage-controlled oscillator, when enabled, generates the clock signal, wherein the generated clock signal has a duration τ and is synchronized to the center of the data state transitions of the input data signal, wherein the gated voltage-controlled oscillator includes a first frequency control loop that continually calibrates the frequency of the gated voltage-controlled oscillator to generate the clock signal with the duration τ, and delays the generated clock signal in such a way that the generated clock signal is synchronized to the center of the data state transitions of the input data signal; and a secondary loop coupled to the first frequency control loop of the gated voltage-controlled oscillator and coupled to the first delay element of the first delay arrangement, wherein the secondary loop includes a frequency detector that tunes the first delay element and tunes the first frequency control loop of the gated voltage-controlled oscillator based on the frequency difference between a recovered clock signal output from the gated voltage-controlled oscillator and an output frequency of a phase locked loop coupled to the frequency detector.