Patent ID: 6919254

Claim:
A process for forming a SRAM cell having an area of 8F2, or less, wherein F represents one-half of a minimum lithographic pitch of the SRAM cell, the process comprising: providing a semiconductive substrate having a first conductivity type: forming a diffusion region of a second conductivity type different than the first conductivity type in the substrate, the diffusion region being configured to act as a row address line; forming first and second dielectric pillars on the substrate, the first and second pillars having respective plan view areas of about F2 and being separated by a distance of about F, one of the first and second pillars being formed atop the diffusion region and another of the first and second pillars not being formed atop the diffusion region; and forming first and second ultrathin transistors and first and second load devices in a space between the first and second pillars, the first load device being merged with the second ultrathin transistor and the second load device being merged with the first ultrathin transistor.