Patent ID: 7310007

Claim:
A system for reducing a clock skew, comprising: a final stage buffer cell specifying unit configured to specify a final stage buffer cell supplying a clock signal in a logic circuit; an F/F specifying unit configured to specify a first flip-flop supplied with the clock signal from the final stage buffer cell; an F/F locating unit configured to locate the first flip-flop in the position adjacent to the final stage buffer cell; an F/F deleting unit configured to delete the first flip-flop from an original position where the first flip-flop is specified by the F/F specifying unit; a logic cell position discriminator unit configured to discriminate whether there is a logic cell adjacent to the final stage buffer cell; and a logic cell locating unit configured to locate the logic cell in the original position of the first flip-flop, wherein the F/F locating unit locates the first flip-flop in the position where the logic cell is determined to be adjacent to the final stage buffer cell.