Patent ID: 8136003

Claim:
A debug test system adapter comprising: A. a first set of leads including: i. a clock input and output lead, ii. a mode input and output lead, iii. a test in data output lead, and iv. a test out data input lead; B. a second set of leads including: i. a test clock input lead carrying a test clock signal coupled to the clock input and output lead, ii. a test mode select input lead carrying a test mode select signal coupled to the mode input and output lead, iii. a test in data input lead carrying a test in data signal selectively coupled to the test in data output lead and the mode input and output lead, and iv. a test out data output lead carrying a test out data signal selectively coupled to the test out data input lead and the mode input and output lead; and C. a third set of leads including first and second data transport leads selectively coupled with the mode input and output lead.