Patent ID: 8650524

Claim:
A computer-implemented method of generating scan test circuitry for insertion into an integrated circuit design, comprising: receiving an integrated circuit design for storage in a memory; instantiating in the integrated circuit design a first input pin to serially transport both scan data and a plurality of control bits, a clock pin, an output pin, a plurality of cores comprising a plurality of scan chains having a plurality of scan chain registers, and a state machine controller adapted for three external test pins and electrically connected to the plurality of scan chain registers, the first input pin, the clock pin, and the output pin; configuring the state machine controller to selectively direct, according to a control bit of the plurality of control bits to be received at the first input pin, one of the scan data to be received from the first input pin to the plurality of scan chains and the scan data to be received from a second input pin to the plurality of scan chains, wherein the scan data to be received at the first input pin and the scan data to be received from the second input pin each comprise the same test patterns to be shifted in the plurality of scan chain registers during a scan test; and configuring the state machine controller to generate a plurality of scan clocks to pulse the plurality of scan chain registers during a scan testing to shift scan data in the plurality of scan chain registers.