Patent ID: 7375563

Claim:
A duty-cycle-correcting clock generator comprising: a phase-locked loop (PLL) that generates a feedback clock, the PLL having a phase comparator that compares phases of an input clock and the feedback clock, the PLL adjusting a frequency of the feedback clock in response to phase comparison; and a clock toggler that receives the input clock and receives the feedback clock generated by the PLL, the clock toggler generating an output clock; wherein the clock toggler generates leading edges of the output clock in response to leading edges of the input clock; wherein the clock toggler generates trailing edges of the output clock in response to trailing edges of the feedback clock; wherein the clock toggler comprises: a flip-flop that receives the input clock at a clock input and generates the output clock; an edge trigger circuit that receives the feedback clock and generates a reset pulse in response to a trailing edge of the feedback clock; wherein the reset pulse is applied to a reset input of the flip-flop; wherein the flip-flop is set by the input clock to generate a leading edge of the output clock and reset by the reset pulse to generate the trailing edge of the output clock; wherein the PLL creates PLL noise that is included in the feedback clock but is not present in the input clock; wherein PLL noise is propagated to trailing edges of the output clock while leading edges of the output clock do not include PLL noise, whereby trailing edges of the output clock are generated by the PLL, and leading edges are generated by the input clock that bypasses the PLL and whereby duty cycle of the output clock is adjusted without PLL noise being added to leading edges of the output clock.