Patent ID: 7450616

Claim:
A data serializer comprising: a input terminal receiving serial bits of data in data blocks of N bits; a buffer-flip-flop having an input connected to input terminal and an output for storing a bit received at said input; a most significant bit flip-flop having an input connected to said input terminal, an output and a hold terminal for storing a bit received at said input; a multiplexer having a first input connected to said output of said buffer-flip-flop, a second input connected to said output of said most significant bit flip-flop, a control input and an output, said multiplexer selectively outputting one of said first input or said second input corresponding to a control signal at said control input; a serial chain of N−1 bit flip-flops, each bit flip-flop having a input connected to an output of a prior bit flip-flop in said serial chain for storing a bit received at said input, a first bit flip-flop of said serial chain having an input connected to said output of said multiplexer, said serial chain of N−1 bit flip-flops including a cycle input initialing transfer of data from each bit flip-flop of said serial chain of N−1 bit flip-flops to a next bit flip-flop in said serial chain; a multibit register having N parallel bit inputs, a most significant bit input connected to said output of said most significant bit flip-flop, N−1 less significant bit input connected to respective outputs of said serial chain of N−1 bit flip-flops, and a load enable input, said multibit register storing bits received at said N parallel bit input upon a load enable signal at said load enable input; a control circuit connected to said input terminal, said most significant bit flip-flop, multiplexer having a first input connected to said output of said buffer-flip-flop, a second input connected to said output of said most significant bit flip-flop, a control input and an output, said multiplexer, said serial chain of N−1 bit flip-flops and said multibit register, said control circuit on a first bit of a data block, storing said first bit of said data block in said buffer-flip-flop and holding data in said most significant bit register and said serial chain of N−1 bit flip-flops, on a second bit of a data block, supplying a control signal to said multiplexer to select said first input and supplying a cycle signal to said cycle input of said serial chain of N−1 bit flip-flops for transferring data from each bit flip-flop of said serial chain of N−1 bit flip-flops to a next bit flip-flop in said serial chain, on bits of a data block other than a first, second or last bit, supplying a control signal to said multiplexer to select said second input and supplying a cycle signal to said cycle input of said serial chain of N−1 bit flip-flops for transferring data from each bit flip-flop of said serial chain of N−1 bit flip-flops to a next bit flip-flop in said serial chain, and on a final bit of a data block supplying a load enable signal to said load enable input of said multibit register.