Patent ID: 7701251

Claim:
A semiconductor device, comprising: a first integrated circuit (IC) die having an array of tiles forming a programmable fabric; and a second IC die stacked on the first IC die and connected therewith via inter-die connections, the second IC die including banks of memory coupled to input/output (IO) data pins, the inter-die connections coupling the IO data pins to the programmable fabric such that all of the banks of memory are accessible in parallel from the programmable fabric, wherein the second IC die includes a central memory controller having control pins coupled to control resources and decoder resources, the control resources and decoder resources each coupled to each of the banks of memory, the inter-die connections coupling the control pins to the programmable fabric, or wherein each of the banks of memory includes a memory controller having the control pins coupled to the control resources and the decoder resources, the inter-die connections coupling the control pins to the programmable fabric, or wherein the first IC die includes a memory controller having the control pins coupled to the control resources and the decoder resources, the inter-die connections coupling the control pins to at least a portion of the banks of memory on the second IC die.