Patent ID: 7816243

Claim:
A method of fabricating a semiconductor device, comprising: providing a substrate, the substrate having a PMOS area and a NMOS area; forming a high-k layer on the substrate; forming a first cap layer on the high-k layer in the PMOS area and forming a second cap layer on the high-k layer in the NMOS area, wherein the first cap layer is different from the second cap layer; forming a metal layer and a polysilicon layer sequentially on the first and second cap layers; patterning the polysilicon layer, the metal layer, the first cap layer, the second cap layer and the high-k layer, so as to form a first gate structure in the PMOS area and a second gate structure in the NMOS area; and forming first source/drain regions in the substrate beside the first gate structure and forming second source/drain regions in the substrate beside the second gate structure, wherein the first source/drain regions comprise SiGe epitaxial layers and the second source/drain regions comprise doped regions.