Patent ID: 8892968

Claim:
A bit-level memory controller adaptable to managing defect bits of a non-volatile memory, comprising: a memory bus interface controller configured to control data communication in a memory bus disposed between the non-volatile memory and the memory controller; a bad column management (BCM) unit configured to retrieve a bit-level mapping table, in which defect bits are respectively marked, based on which the BCM unit constructs a bit-level script (BLS) that contains a plurality of entries denoting defect-bit groups respectively; an internal buffer configured to store data managed by the BCM unit according to the BLS; and a host bus interface controller configured to control data communication in a host bus disposed between a host and the memory controller; wherein the BCM unit, in a data read operation, aggregates non-fault data transferred only from consecutive non-defect physical memory locations separated by defect-bit locations denoted by the BLS, and moves the aggregated non-fault data to the internal buffer; wherein the BCM unit, in a data write operation, moves the data of the internal buffer toward the non-volatile memory when a target address of the data does not hit the BLS, and the BCM unit appends a dummy bit written to the non-volatile memory when the target address of the data hits the BLS.