Patent ID: 8352695

Claim:
A memory system comprising: a memory element for transferring data between a first processing element and a second processing element, wherein the memory element is configured for providing data to or for accepting data from the first processing element at a first access rate and for providing data to or accepting data from the second processing element at a second access rate; and a selection element for adjusting at least one of the first access rate and the second access rate; an identification element coupled to the to the selection element, the identification element configured to generate an identification signal that indicates an access rate of an identified processing element, wherein the selection element is arranged for selecting a further first access rate or a further second access rate depending on whether the identification signal has a first logic value or a second logic value, wherein the memory element, selection element, and identification elements together form a first modular hardware element; and a second modular hardware element coupled to the second processing element and to a third processing element and to the first processing element, wherein the second modular hardware element has an identical function as the first modular hardware element, and the second modular hardware element is disposed on a same integrated circuit as the first modular hardware element.