Patent ID: 6914465

Claim:
A PLL circuit for use with first and second reference signals, with each reference signal having a phase, cycle, and frequency, and the cycle of the second reference signal being longer than that of the first reference signal, the PLL circuit comprising: a voltage controlled oscillator for generating a clock signal in accordance with a control voltage, and the clock signal having a phase and frequency; a first loop for controlling the frequency of the clock signal in accordance with the first reference signal; and a second loop for controlling the phase of the clock signal in accordance with the second reference signal with the second loop generating the control voltage at a constant value and supplying the voltage controlled oscillator with the constant control voltage until the difference between the frequency of the first reference signal and the frequency of the clock signal converges to within a predetermined range, and thereafter the second loop generating the control voltage at a level in accordance with the difference between the chase of the second reference signal and the phase of the clock signal and supplying the voltage controlled oscillator with the control voltage at the level in accordance with said phase difference, wherein the second loop includes: a voltage generation section for generating a plurality of constant control voltages having different constant voltage values; and a decoder for selecting one of the constant control voltages in accordance with a predetermined control signal, with the second loop supplying the voltage controlled oscillator with the constant control voltage selected by the decoder until the difference between the frequency of the first reference signal and the frequency of the clock signal converges to within the predetermined range.