Patent ID: 7589368

Claim:
A memory device comprising: a first pair of bit lines; a first pair of word lines over the first pair of bit lines and configured to cross over the first pair of bit lines; a first pair of channel regions substantially parallel with the first pair of word lines and each disposed at least between the locations where a corresponding word line of the first pair of word lines crosses over the first pair of bit lines and disposed between the corresponding word line and the first pair of bit lines; a first pair of charge storage lines comprising a first set of charge storage regions each disposed at least between the corresponding word line and a corresponding channel region of the first pair of channel regions; a second pair of bit lines over the first pair of word lines and configured to cross over the first pair of word lines; a second pair of channel regions substantially parallel with the first pair of word lines and each disposed at least between the locations where the second pair of bit lines cross over the corresponding word line and disposed between the second pair of bit lines and the corresponding word line; and a second pair of charge storage lines comprising a second set of charge storage regions each disposed at least between the corresponding word line and the corresponding channel region.