Patent ID: 7299329

Claim:
A method, comprising: receiving an F-bit word using J command and address pins of a programmable memory device, wherein F and J are positive integers, wherein J is less than F, wherein the F-bit word comprises a set of command and address signals, and wherein the set of command and address signals consists of an Active command signal, Bank Address signals BA 0 -BA 2 , and Row Address signals A 0 -A 11 , comprising: receiving a first portion of the F-bit word at a first time using G command and address pins, wherein the first portion of the F-bit word comprises G-bits, wherein G is less than F, wherein G is less than or equal to J, wherein the first portion of the F-bit word consists of a set of command signals and a first subset of address signals, wherein the set of command signals includes a Chip Select (CS#) signal, a Row Address Strobe (RAS#) signal, a Column Address Strobe (CAS#) signal, and a Write Enable (WE#) signal, wherein receiving the set of command signals includes using a set of Command Pins, wherein the set of Command Pins include a CS# pin, a RAS# pin, a CAS# pin, and a WE# pin, wherein receiving the first subset of address signals includes using a set of Address Pins, and wherein the set of Address Pins include G-4 pins; and receiving a second portion of the F-bit word at a second time, wherein the second portion of the F-bit word comprises H-bits, wherein H is F-G, wherein H is less than or equal to J, and wherein the second portion of the F-bit word consists of a second subset of address signals; and performing a memory command in response to the fully-received F-bit word.