Patent ID: 7639525

Claim:
A semiconductor memory device comprising: a static memory cell including a latch portion and a transfer portion, said latch portion storing data, said transfer portion transferring said data; wherein said latch and transfer portions each include a transistor formed above a well layer; and wherein a voltage which is supplied to a well layer in a data read operation from said static memory cell is different from a voltage which is supplied to said well layer in a data write operation to said static memory cell, wherein said latch portion includes a pair of drive transistors each having a channel of a first conductive type and a pair of load transistors each having a channel of a second conductive type, each drive transistor having a source electrode connected to a source line, each load transistor having a source electrode connected to a first power supply line higher in potential than said source line; and wherein said transfer portion includes a pair of transfer transistors each having a channel of said first conductive type and connected between a bit line for accessing said memory cell and a storage node for storing data, and a gate connected to a word line across the bit line, wherein a second power supply line for applying, as necessary, the voltage to the well layer when data is written to or read from said memory cell, said well layer being made up of a conductive layer, said second power supply line extending in a direction across the word line.