Patent ID: 7817129

Claim:
A circuit for selecting lines within an active matrix array, the circuit comprising: a plurality of gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a respective gate line of a plurality of gate lines within said active matrix array and a source to receive an input signal; at least one address line transistor device corresponding to said each gate line drive transistor device, each address line transistor device having a drain coupled to a gate of said corresponding gate line drive transistor device and a gate coupled to a corresponding address line of a plurality of address lines within said active matrix array, such that by asserting a predetermined combination of voltages on said plurality of address lines, a single gate line of said plurality of gate lines is selected to receive said input signal to be transmitted to a corresponding pixel within said active matrix array; and a plurality of resistor devices, each resistor device being coupled to said drain of said at least one address line transistor device and to said gate of said corresponding gate line drive transistor device, wherein a resistance value of said each resistor device is at least one of: (1) smaller than an off-state source-drain resistance of said at least one corresponding address line transistor device by a predetermined factor, or (2) larger than an on-state resistance of said at least one corresponding address line transistor device.