Patent ID: 8340236

Claim:
A circuit comprising: a symbol counter configured to provide a system time from a plurality of counted symbols, the system time being divided into symbols; a system clock generator connectable to the symbol counter, the system clock generator having a first quartz crystal whose frequency is an integer multiple of a symbol frequency and having a frequency divider configured to output symbols that are to be counted in an operating mode by dividing the frequency of the first quartz crystal; a sleep clock generator having a second quartz crystal, an output frequency of an output clock signal of the sleep clock generator being a non-integer multiple of the symbol frequency; a switch configured to produce the symbols to be counted by blanking the output clock signal of the sleep clock generator in a sleep mode; a modulo divider connectable to an output of the sleep clock generator and switchable between at least two integer divisor values, an output of the modulo divider being connectable to a control input of the switch to blank out the output clock signal via the modulo divider; and a logic element connectable to a control input of the modulo divider, the logic element configured to control a division factor of the modulo divider by changing a division factor of the modulo divider.