Patent ID: 8392657

Claim:
An apparatus, comprising: a cache memory, wherein the cache memory comprises a total number of sets, each set including at least one cache line; and a first process resource table to maintain a first occupancy count indicating a number of cache lines, within a first subset of the total number of sets, storing information utilized by at least one of a plurality of processes; a second process resource table to maintain a second occupancy count indicating a number of cache lines, within a second subset of the total number of sets, storing information utilized by at least one of a plurality of processes; and a processor core to: update the first process resource table when the processor core changes a utilization of a cache line in the first subset from a first process to a second process; and indicate a combined number of cache lines utilized with a given process of the plurality of processes by performing an operation selected from: adding the occupancy count of cache lines utilized by the given process for the first and second process resource tables; and estimating the combined number of cache lines by extrapolating the occupancy count of cache lines utilized by the given process from the first processor resource table.