Patent ID: 7514743

Claim:
A transistor structure formed in a substrate comprising: a vertical DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, a threshold voltage applied to the gate causing a generally vertical current to flow between the source and drain with respect to a horizontal surface of the substrate; and opposing floating trench portions, comprising a conductive or semiconductor material that has no external electrical contact and being isolated from any surrounding material by a dielectric, the trench portions having a generally vertical depth dimension with respect to the horizontal surface of the substrate, and the transistor gate being in between opposing floating trench portions, wherein the opposing floating trench portions are arranged such that operating voltages applied to the body region and the drain capacitively couple a potential to the opposing floating trench portions, the potential being in between the drain voltage and the body region voltage, which creates a depletion region that merges in the drift region from opposing floating trench portions at a certain drain bias.