Patent ID: 7852757

Claim:
An integrated circuit (“IC”) with a peripheral component serial interconnect system comprising: a first data sink; a second data sink; a data source having a status-based flow control receiver and capable of providing first data packets destined for the first data sink of the interconnect system and capable of providing second data packets destined for the second data sink of the interconnect system; wherein the first data sink is configured to communicate a credit limit to the data source; wherein the data source is configured to track credits used in communicating the first data packets to the first data sink and suspend communicating the first data packets to the first data sink in response to reaching the credit limit; and a switch of the interconnect system having a first buffer queuing the first data packets from the data source, a second buffer queuing the second data packets from the data source, a status detector configured to detect a buffer condition of the first buffer and to produce a first signal when the buffer condition equals or exceeds a selected buffer threshold, and a status-based flow control transmitter configured to send a first data link layer packet (“DLLP”) to the status-based flow control receiver of the data source over a status-based flow control feedback path in response to the first signal; wherein the buffer condition is a quantity of data in the first buffer, the selected buffer threshold is a value that causes the buffer condition to equal or exceed the selected buffer threshold before the credit limit is reached by the data source, and the data source ceases providing the first data packets in response to the first DLLP.