Patent ID: 7704834

Claim:
A method comprising: forming a plurality of floating gate patterns and floating gate oxide patterns spaced apart on a semiconductor substrate; forming a trench in the semiconductor substrate in the space between the floating gate patterns; forming a control gate pattern in the trench by depositing a control gate material in the trench and then performing a first etching process on the control gate material such that after the first etching process the control gate pattern comprises a first control gate pattern portion extending parallel to the sidewalls of the floating gate patterns and a second control gate pattern portion extending perpendicular to the sidewalls of the floating gate patterns and over the floating gate patterns; forming a dielectric layer pattern on the control gate pattern after forming the trench; simultaneously forming a pair of second control gate patterns and a second trench between the second control gate patterns by performing a second etching process on the control gate pattern to expose a portion of the semiconductor substrate in the trench, wherein the dielectric layer pattern is formed before simultaneously forming the pair of second control gate patterns and the second trench; forming a first oxide layer on a respective sidewall of the second control gate patterns provided in the trench; forming a source region in the exposed portion of the semiconductor substrate in the second trench; and then forming a metal layer filling the second trench and on a portion of the uppermost surface of the second control gate patterns.