Patent ID: 7843230

Claim:
A comparator circuit comprising: a first transistor and a second transistor coupled as a first differential pair, a control terminal of the first transistor coupled to receive a first input voltage, a control terminal of the second transistor coupled to receive a second input voltage, the first differential pair coupled to pass a first current through a first terminal of the first differential pair and a second current through a second terminal of the first differential pair, the first and second currents being responsive to a comparison of the first input voltage and the second input voltage; a third transistor coupled to pass a first portion of the first current in response to a voltage at the first terminal of the first differential pair; a fourth transistor coupled to pass a first portion of the second current in response to the voltage at the first terminal of the first differential pair, a fifth transistor passing a second portion of the first current in response to a voltage at the second terminal of the first differential pair; a sixth transistor passing a second portion of the second current in response to the voltage at the second terminal of the first differential pair; a second differential pair including a first control terminal to receive a third input voltage and a second control terminal to receive a fourth input voltage, the second differential pair coupled to pass a third current through a first terminal of the second differential pair and a fourth current through a second terminal of the second differential pair, the third current and the fourth current being responsive to a comparison of the third input voltage and the fourth input voltage; a seventh transistor having a drain and a gate coupled to the first terminal of the second differential pair; an eighth transistor having a gate coupled to the first terminal of the second differential pair, and having a drain coupled to the second terminal of the second differential pair; a ninth transistor having a drain and a gate coupled to the second terminal of the second differential pair; a tenth transistor having a gate coupled to the second terminal of the second differential pair, and having a drain coupled to the first terminal of the second differential pair, wherein current through the third transistor and the fourth transistor is mirrored to a first output terminal, and current through the seventh transistor and the eighth transistor is mirrored to the first output terminal, and wherein current through the fifth transistor and the sixth transistor is mirrored to a second output terminal, and current through the ninth transistor and the tenth transistor is mirrored to the second output terminal, wherein the current flowing through the third transistor and the fourth transistor cause the comparator circuit to exhibit hysteresis.