Patent ID: 8193057

Claim:
A manufacturing method of a MOS transistor for reducing short-channel effects, the MOS transistor fabricated on a silicon substrate after an isolation module is finished, the method comprising the following steps: (1) forming a groove in the silicon substrate; (2) carrying out well implantation, anti-punchthrough implantation and threshold-voltage-adjustment implantation; (3) forming a gate stack in the groove, wherein the gate stack comprises a gate insulation layer formed on a bottom surface of the groove and a gate electrode layer formed on a top surface of the gate insulation layer; (4) carrying out lightly doped drain (LDD) implantation and halo implantation within the groove to create LDD structures and halo structures under the groove; (5) forming an insulating gate sidewall spacer with a substantial portion of the gate sidewall spacer located within the groove; (6) carrying out source and drain implantation to get source and drain areas; (7) forming a metal silicide layer on the source and drain areas.