Patent ID: 8621296

Claim:
An integrated circuit device, comprising: a first latch responsive to a clock signal, said first latch comprising a data input terminal, a scan input terminal, a scan enable terminal and an output terminal; a second latch responsive to the clock signal, said second latch comprising a data input terminal, a scan input terminal, a scan enable terminal and an output terminal; a scan path responsive to a scan enable signal, said scan path configured to selectively pass a signal from the output terminal of said first latch to the scan input terminal of said second latch when the scan enable signal is active; and a switch responsive to the scan enable signal, said switch having a first current carrying terminal electrically coupled to said scan path, said switch configured to disable said scan path from passing the signal from the output terminal of said first latch to the scan input terminal of said second latch when the scan enable signal is in an inactive state.