Patent ID: 8878860

Claim:
An apparatus for controlling vertically tiled, horizontally tiled and untiled memory access comprising: an address pre-swizzle circuit having swizzled and non swizzled operational states to produce, at an output of said address pre-swizzle circuit, conditioned address bits from address bits provided by a processor, one or the other of said output states being selected according to an access control signal that indicates: 1) vertically tiled memory access; or, 2) untiled or horizontally tiled memory access; a data steering circuit coupled to the output of the address pre-swizzle circuit, the data steering circuit to couple data to N sub-channels of memory by dynamically steering the data according to a selected one of different permutation mapping types, the selected one of the different permutation mapping types being selected as a function of the access control signal and the conditioned address bits from the output of the address pre-swizzle circuit, said different permutation mapping types corresponding to: i) untiled memory access with a first datapath and a first data unit orientation through said data steering circuit; ii) vertically tiled memory access with a second datapath and a second data unit orientation through said data steering circuit, said second data unit orientation being orthogonal to said first data unit orientation; iii) horizontally tiled memory access with said first datapath and said second data unit orientation through said data steering circuit; N respective address post-swizzle circuits coupled to the output of the address pre-swizzle circuit to generate N respective valid address bits from the conditioned address bits in response to the access control signal and sub channel identification information; and, N respective sub-channel interface circuits respectively coupled to the N respective address post-swizzle circuits and the data steering circuit, the sub-channel interface circuits to respectively generate sub-channel address bits and sub channel data for the N sub-channels.