Patent ID: 8338882

Claim:
A semiconductor memory device comprising: a base including a substrate and a peripheral circuit formed on a surface of the substrate; a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base; a memory film provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers and including a charge storage film; a channel body provided on an inside of the memory film in the memory hole; an interconnection provided below the stacked body, and electrically connecting the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region, wherein the memory cell array region having the memory film and the channel body and the peripheral circuit; and a contact plug piercing the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region; and wherein the channel body is formed in a U-shaped configuration including: a pair of columns extending in a stack direction of the stacked body; and a connection buried in the lowermost layer of the conductive layers in the memory cell array region and connecting the pair of columns.