Patent ID: 7864576

Claim:
A nonvolatile semiconductor memory comprising: plural nonvolatile memory cells arranged in matrix form; plural word lines connected to gates of said nonvolatile memory cells; plural bit lines connected to drains of said nonvolatile memory cells; plural source lines connected to sources of said nonvolatile memory cells; a word decoder which activates a word line according to an address signal, and which, when different word lines are accessed sequentially, overlaps a part of activation periods of said different word lines to perform access operations in parallel; plural cell groups each of which is a series connection of nonvolatile memory cells and which are arranged in a wiring direction of said plural word lines; and cell group pairs, each of which is a pair of adjoining cell groups arranged in said wiring direction of said plural word lines, a pair of bit lines of each of the cell group pairs being arranged so as to cross each other in zigzag form, wherein in each of said cell group pairs, confronting nonvolatile memory cell pairs are connected to different source lines and the sources of said nonvolatile memory cells in each of said cell group pairs are connected to each other, and all combinations of the bit lines and the source lines connected to the drains and the sources of said nonvolatile memory cells connected to two of said different word lines being optionally selected are different from one another.