Patent ID: 8024509

Claim:
A method of managing a plurality of non-volatile memory cells, each memory cell having a corresponding storage window divisible into a plurality of ranges of storage levels representative of N>3 bits, the method comprising: reserving a single cell of the memory cells to use as a flag storage element to represent a value of N for each of a plurality of other memory cells; selecting the value of N; and successively, for each value of n between 1 and N: setting each memory cell of said plurality of other memory cells to represent bits 1 through n of said N bits, and setting each reserved single cell to represent n; wherein said memory cells of said plurality of other memory cells are not erased between said successive settings of said memory cells of said plurality of other memory cells and wherein the single cell is maintained in a programmed state between said successive settings of the single cell until after said memory cells of said plurality of other memory cells have been set to represent bits 1 through N and the single cell has been set to represent N.