Patent ID: 7349271

Claim:
A memory array, comprising: a plurality of columns of substantially identical memory cells, wherein all memory cells within each column are commonly connected to at least one bitline of a given pair from a plurality of complementary bitline pairs; and a cascaded circuit comprising a particular memory cell from each of said plurality of columns and at least one drive device for each column for coupling at least one bitline of the corresponding bitline pair to at least one complementary next bitline of a next bitline pair, wherein a state change produced on said at least one bitline changes a state of the particular memory cell and wherein said state change is then impressed on said at least one complementary next bitline, wherein wordline inputs of the particular memory cells in the plurality of columns are maintained in an enabled state while the cascaded circuit is operating to determine a delay time of said particular memory cells, whereby said delay time is measured independent of an memory cell access device enablement delay of said particular memory cells.