Patent ID: 8461627

Claim:
A stack array structure for a semiconductor memory device, comprising: a first semiconductor layer including a plurality of first cell strings which include first cell strings extending parallel to one another in a word-line direction and first cell strings aligned in series in a bit-line direction; a second semiconductor layer including a plurality of second cell strings which include second cell strings extending parallel to one another in a word-line direction and second cell strings aligned in series in a bit-line direction, and wherein the second semiconductor layer is located over the first semiconductor layer such that the second cell strings are located over the first cell strings; a plurality of bit-line contact plugs configured to couple a bit-line to two adjacent first cell strings aligned in series in the bit-line direction, and to further couple the bit-line to two adjacent second cell strings respectively located over the two adjacent first cell strings, wherein the bit-line contact plugs are arranged to define a bit-line plug layout over the plurality of first cells strings and the plurality of second cell strings; a plurality of common source line contact plugs configured to couple a common source line to the two adjacent first cell strings and the two adjacent second cell strings; and a plurality of pocket p-well contact plugs configured to couple a pocket p-well line to the first semiconductor layer and the second semiconductor layer, the pocket p-well contact plugs being located at positions corresponding to the bit-line plug layout.