Patent ID: 7730445

Claim:
A pattern data verification method for a semiconductor device, comprising: extracting, using a computer, from design data, design data corresponding to an edge portion of a mask pattern to obtain an edge portion of a pattern on a substrate to be processed, when the pattern is obtained on the substrate to be processed by using at least two masks each having the mask pattern corresponding to the design data; setting different allowable errors with respect to the extracted design data and the design data which is not extracted, respectively, each of the allowable errors corresponding to an allowable range of a size of a pattern actually formed on a substrate with respect to a size of an ideal pattern in the design data; calculating a pattern formed on the substrate to be processed by using at least one mask by process simulation; and comparing an error between the pattern calculated by the simulation and the design data with the allowable error set for the design data, wherein a plurality of portions which are different from one another in at least one of phase and transmittance are included in the design data corresponding to the mask pattern formed on at least one of the masks, and arrangement information of said each portion in the design data is acquired from the design data of the mask pattern, and an allowable error including a variation of the design data of the mask pattern which is generated when the mask pattern is formed on the substrate to be processed is calculated based on the arrangement information.