Patent ID: 7944039

Claim:
A semiconductor device comprising: a semiconductor chip including electrode terminal bumps; a laminated wiring structure formed integrally with the semiconductor chip in direct contact with the electrode terminal bumps; a frame disposed to surround the semiconductor chip on the laminated wiring structure, and made of a material having stiffness; and a sealing resin formed to bury therein the frame and at least the periphery of a side surface of the semiconductor chip, wherein a side surface of the laminated wiring structure is exposed from the sealing resin; wherein electrical paths extend from the electrode terminal bumps of the semiconductor chip to respective pad portions, the pad portions are located on a surface of the laminated wiring structure distal from the semiconductor chip, and the electrical paths consist of wiring internal to the laminated wiring structure; wherein the sealing resin is formed to coat a top surface and an inner side surface of the frame, and a side surface of the semiconductor chip, and to expose a surface of the semiconductor chip opposite to a surface thereof on which the electrode terminals are formed; and wherein an uppermost insulating layer of the laminated wiring structure is directly disposed on the surface of the semiconductor chip on which the electrode terminals are formed, and each of the electrode terminals is connected to a wiring layer which is formed to fill a corresponding via hole formed in the uppermost insulating layer.