Patent ID: 8352671

Claim:
A memory system, comprising: a controller configured to regulate read and write access to one or more FLASH memory devices employed for random access memory applications and at least one dynamic random access memory (DRAM) buffer component, the controller comprising; a first channel configured to communicate with the one or more FLASH memory devices; and a second channel configured to communicate with the at least one DRAM buffer component; wherein the at least one DRAM buffer component operates as a write data staging area for incoming system writes, wherein at least one incoming system write is cached in the at least one DRAM buffer component before the at least one incoming system write is written to the one or more FLASH memory devices over time, the controller transfers the at least one incoming system write to the one or more FLASH memory devices based on bursting behavior considerations or based on bandwidth considerations, and a partial allocate component configured to partially allocate data from the one or more FLASH memory devices during writes to a memory subsystem, the partial allocate component copies a small section of data from the one or more FLASH memory devices into the at least one DRAM buffer component, wherein the allocated data in the at least one DRAM buffer component is updated with corresponding write data from an application and application data that is not associated with the write data and deemed not to be updated remains in the one or more FLASH memory devices, and wherein the updated write data is read from the at least one DRAM buffer component at the same time as the application data is read from the one or more FLASH memory devices.