Patent ID: 8063412

Claim:
A semiconductor device comprising: a semiconductor substrate having an active region and an isolation region; at least first, second and third gate electrodes on the substrate within the active region with a gate insulating film interposed therebetween; and a dummy pattern formed within the active region in at least a part thereof between the second and third gate electrodes, wherein, the distance between the first and second gate electrodes is D 1 , the distance between the second and third gate electrodes is D 2 , the distance between the second gate electrode and the dummy electrode is d 1 , the distance between the dummy electrode and the third gate electrode is d 2 the distance between the isolation region and the first gate electrode is d 3 , the distance between the third gate electrode and the isolation region is d 4 , D 1 is not equal to D 2 , d 2 is equal to D 1 plus a tolerance value, and when D 1 is not equal to d 3 or D 1 is not equal to d 4 , then d 3 is equal to D 1 plus the tolerance value, but d 4 is not equal to d 3 .