Patent ID: 7403417

Claim:
A non-volatile semiconductor memory device, comprising: a memory area; a circuitry area; an array of non-volatile memory cells, the array comprising a multiplicity of array columns and at least one redundant column of non-volatile memory cells adapted to replace a defective array column, wherein the memory area comprises the multiplicity of array columns and the at least one redundant column of non-volatile memory cells; a data bus coupled to the array to carry data to and from the array, the data bus connecting the memory area and the circuitry area; a column decoder coupled to the data bus, wherein the column decoder is adapted to receive an address of a memory cell to which data is to be written to or from which data is to be read, the address being received on the data bus, wherein the circuitry area comprises the column decoder; and a column redundancy unit coupled to the data bus, the column redundancy unit including a column redundancy memory and a column redundancy controller, wherein the column redundancy controller is adapted to determine whether data corresponding to the decoded address is to be written to or read from an array column or a redundant column, and wherein column redundancy data required by the column redundancy unit is stored in the column redundancy memory, which is connected to the column redundancy controller by a dedicated column redundancy bus, wherein the circuitry area comprises the column redundancy controller, the column redundancy memory, and the dedicated column redundancy bus.