Patent ID: 8836397

Claim:
A duty cycle ratio correction circuit, comprising: a duty cycle ratio controlling unit configured to generate an internal clock signal having a duty cycle ratio defined according to a first reference clock signal and a reset signal; and a reset signal generating unit configured to generate the reset signal in response to a second reference clock signal and the internal clock signal fed back thereto, wherein the duty cycle ratio controlling unit includes: a first unit configured to receive the first reference clock signal and the reset signal, and to output a control signal in response to the reset signal; and a second unit configured to receive the first reference clock signal and the control signal outputted from the first unit, to change an output node to a first level in response to the first reference clock signal and to change the output node to a second level by precharging the output node in response to the control signal, wherein the second unit comprises: a first driving unit configured to drive the output node to the first level in response to the first reference clock signal; a second driving unit configured to precharge the output node to the second level in response to the reset signal; and an enabling unit configured to enable the first driving unit in response to the control signal.