Patent ID: 7366805

Claim:
A data transfer control system for transferring data through a first bus and a second bus, the data transfer control system comprising: a buffer controller which controls access to a data buffer in which transfer data is temporarily stored; and a transfer controller which controls data transfer between a device connected to the first bus and a plurality of logical units connected to the second bus, the plurality of logical units including a first logical unit and a second logical unit, the transfer controller including: a command processing section which starts data transfer to or from the first logical unit connected to the second bus based on a command indicated by a command packet for the first logical unit when the command packet for the first logical unit is received from the device connected to the first bus, and starts data transfer to or from the second logical unit connected to the second bus based on a command indicated by a command packet for the second logical unit when the command packet for the second logical unit is received from the device connected to the first bus; and a wait processing section which waits processing of the command packet for the second logical unit that has been received, when a bus reset occurs during the processing of the command packet for the first logical unit and a command packet that is received after the bus reset occurs is the command packet for the second logical unit, the wait processing section waiting processing of the command packet for the second logical unit for a predetermined time, when a bus reset occurs during the processing of the command packet for the first logical unit and a command packet that is received after the bus reset occurs is the command packet for the second logical unit, and issuing an error status with respect to the device connected to the first bus when a wait state is not canceled even after processing has waited for the predetermined time.