Patent ID: 8519485

Claim:
A memory device, comprising: a semiconductor substrate having a surface region; a first dielectric layer overlying the surface region of the semiconductor substrate; a first wiring structure overlying the first dielectric layer, the first wiring structure having first wiring elements comprising at least a first conductor material and having a first wiring surface; a planarized second dielectric material disposed between the first wiring elements of the first wiring structure; a bottom metallic barrier material overlying at least a portion of the planarized second dielectric material and at least a portion of the first wiring structure, the bottom metallic barrier forming a metal-to-metal contact with the first wiring structure; a plurality of pillar-like structures overlying the first wiring surface, wherein a pillar-like structure comprising: a contact material overlying the bottom metal barrier material; and a switching material overlying the contact material; a conductive material overlying the switching material; a top barrier material overlying the conductive material; a planarized third dielectric material disposed between the plurality of pillar structures; a second wiring structure overlying at least the top barrier material and at least a portion of the planarized third dielectric material, the second wiring structure comprising at least a second conductor material; a CMOS device coupled to the first wiring structure and to the second wiring structure, wherein the CMOS device is configured to apply a voltage across the first wiring structure and the second wiring structure.