Patent ID: 8355289

Claim:
A semiconductor device comprising; a memory unit holding data; a first node coupled to the memory unit, an electrical level of the first node being changed in response to the data of the memory unit; a second node; a detection circuit detecting an electrical level of the second node; and a control circuit controlling an electrical level of the second node in response to the electrical level of the first node during a first time period when the semiconductor device is in a first mode, controlling the electrical level of the second node in response to the electrical level of the first node during a second time period when the semiconductor device is in a second mode, the first and second time periods being different from each other, wherein the control circuit includes a control transistor and each of a memory cell transistor of the memory unit and the control transistor comprises an N-type transistor, wherein the control transistor of the control circuit has a threshold voltage, the control circuit controlling to decrease the electrical level of the second node when the electrical level of the first node is higher than the threshold voltage of the control transistor, and the control circuit controlling to maintain the electrical level of the second node when the electrical level of the first node is lower than the threshold voltage of the control transistor.