Patent ID: 7215218

Claim:
An integrated circuit, comprising: a capacitively loaded balun, wherein said capacitively loaded balun includes: a plurality of first coupled metal traces coupled to an electrically unbalanced input of said capacitively loaded balun, wherein each of said first coupled metal traces includes a first metal trace and a second metal trace and said first metal trace and second metal trace are coupled to each other at a first end of each metal trace and wherein a second end of each second metal trace is coupled to said electrically unbalanced input, a plurality of second coupled metal traces, wherein said plurality of second coupled metal traces are coupled to ground, a first of said second coupled metal traces is coupled to a first electrically balanced output, and a second of said second coupled metal traces is coupled to a second electrically balanced output, and a capacitor coupled between a second end of said first metal trace of each of said plurality of first coupled metal traces and ground, wherein said capacitor electrically loads said plurality of first coupled metal traces so that each metal trace in said plurality of first coupled metal traces and said plurality of second coupled metal traces has a physical length less than one-quarter wavelength of an input signal received at said electrically unbalanced input of said capacitively loaded balun; a first circuit, coupled to said electrically unbalanced input of said capacitively loaded balun; and a second circuit, coupled to said first and second electrically balanced outputs of said capacitively loaded balun; wherein said electrically unbalanced input is impedance matched to said first circuit and said electrically balanced electrical output is impedance matched to said second circuit.