Patent ID: 6930005

Claim:
A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage, comprising the steps of: providing a first well of a first conductivity type, operable as the extension of the transistor drain of said first conductivity type and covered by a first insulator having a first thickness, and a second well of the opposite conductivity type, intended to contain the transistor source of said first conductivity type and covered by a second insulator thinner than said first insulator, said first and second wells forming a junction that terminates at said second insulator; depositing a photoresist layer over said wafer; patterning said photoresist layer by opening a window laterally extending from said drain to said junction termination; and implanting ions of said first conductivity type through said window into said first well, said ions having an energy to limit the penetration depth to said first insulator thickness, and a dose to create a well region of high doping concentration adjacent to said junction termination.