Patent ID: 8901675

Claim:
A method for fabricating a CMOS device, comprising: providing a semiconductor substrate having a first active region and a second active region; forming a first substitute gate electrode layer and an interlayer dielectric layer coplanar with the first substitute gate electrode layer on one surface of the semiconductor substrate; forming a second substitute gate electrode layer with a top surface coplanar with a top surface of the interlayer dielectric layer; forming a first barrier layer directly on: the second substitute gate electrode layer and the interlayer dielectric layer, that are on the second active region; forming a first trench by removing the second substitute gate electrode layer on the first active region using the first barrier layer on the second active region as a mask; forming a first work function layer on a bottom and a sidewall of the first trench of the first active region and directly on: the second substitute gate electrode layer and the interlayer dielectric layer, that are on the second active region; forming a first metal gate by completely filling the first trench; forming a second barrier layer directly on: the first metal gate and the interlayer dielectric layer, that are on the first active region; forming a second trench by removing the second substitute gate electrode layer on the second active region using the second barrier formed on the first active region as a mask; forming a second work function layer on a bottom and a sidewall of the second trench of the second active region, and directly on: the first metal gate and the interlayer dielectric layer, that are on the first active region; and forming a second metal gate by completely fill the second trench.