Patent ID: 8471644

Claim:
A gain-control circuit, comprising: a duty cycle detector having a first signal input coupled to a first output of a voltage-controlled oscillator, a second signal input coupled to a second output of the voltage-controlled oscillator, and an output, the duty cycle detector including a resistively loaded multiple stage pseudo NMOS inverter and arranged to generate an estimate of one of a first voltage present on the first signal input and a second voltage present on the second signal input; an analog-to-digital converter having an input coupled to the output of the duty cycle detector and an N-bit bus, the analog-to-digital converter generating a representation of the estimate on the N-bit bus; and a function generator coupled to the N-bit bus and arranged to receive a target value, the function generator configured to generate a corrected value as a function of the representation on the N-bit bus and to generate a control word in response to the corrected value and the target value.