Patent ID: 6955963

Claim:
A method for manufacturing a memory having a source, a drain, a floating gate, and a control gate, said method comprising: a) forming a dummy gate on a substrate; b) forming a first lateral spacer on the exterior of said dummy gate; c) forming a second lateral spacer on the exterior of said first lateral spacer; d) realizing source and drain regions on the substrate, auto-aligned on the dummy gate; e) coating the dummy gate with a coating layer and planishing said coating layer, stopping at the dummy gate; f) removing the dummy gate entirely to form at least one gate well configured to receive the floating gate and the control gate; g) depositing in the at least one gate well so formed at least a first gate layer, at least an inter-gate insulating layer, and at least a second gate layer, and forming the first gate inter-gate insulating and second gate layers to define the floating gate and the control gate separated by the inter-gate insulator, the first gate layer and the insulating inter-gate layer having an overall thickness of less than a height of the gate well, wherein the depositing g) comprises, in a following order: depositing the first gate layer and the inter-gate insulating layer; etching the layers to define their extension along the source and the drain; electrically insulation cut-out sides of the layers obtained by the etching; depositing the second gate layer having a thickness sufficient to fill the gate well; and polishing the second gate layer, the inter-gate insulating layer, and the first gate layer and stopping at the coating layer.