Patent ID: 7898851

Claim:
A semiconductor memory device comprising: a memory cell unit including a plurality of memory cells connected in series and each having a charge accumulation layer and a control gate formed on the charge accumulation layer; word lines connected to the control gates of the memory cells; a first driver circuit which, for data reading, selects one of the word lines and transfers a voltage to a selected word line and an unselected word line; and a voltage generator which generates a first voltage and a second voltage which is lower than the first voltage, the first voltage being used by the first driver circuit to transfer the voltage to the unselected word line, the second voltage being used by circuits other than the first driver circuit, wherein the voltage generator includes (i) a pump circuit which generates and outputs the first voltage to a first node; (ii) a semiconductor element which drops the first voltage to output the second voltage to a second node; and (iii) a limiter circuit which monitors a potential of the second node to control an operation of the pump circuit in accordance with the potential of the second node, the semiconductor element functions as a diode, the first driver circuit includes (i) a first MOS transistor which, for the data reading, transfers a voltage to the unselected word line; and (ii) a level shifter which uses the first voltage to generate a gate voltage for the first MOS transistor, the first MOS transistor transfers a voltage which turns on the memory cell regardless of data held in the memory cell, to the unselected word line, the semiconductor element is a second MOS transistor having one end of a current path and a gate, which are connected to the first node, and other end of the current path connected to the second node, and the second MOS transistor has a same gate length and a same gate width as those of the first MOS transistor.