Patent ID: 8148243

Claim:
A method for manufacturing a zero capacitor RAM, comprising the steps of: preparing an SOI substrate composed of a stacked structure of a silicon substrate, an embedded insulation film and a silicon layer, and forming line type active patterns by patterning the silicon layer; forming a buffer layer on the active patterns and the embedded insulation film; forming a first insulation layer on the buffer layer between the active patterns; removing a portion of the buffer layer and a portion of the active pattern which are positioned in each drain forming region of each active pattern; forming doped silicon epitaxial layers on sidewalls of the active pattern which are exposed due to removal of the portion of the active pattern which is positioned in the drain forming region; forming a metal layer to fill the removed portion of the active pattern on which the doped silicon epitaxial layers are formed on sidewall of the exposed active pattern; removing the metal layer, the buffer layer and the first insulation layer to expose the active pattern so as to form a drain made of the metal layer; forming a plurality of gates on the active pattern including the drain and on the first insulation layer to extend in a direction perpendicular to the active pattern; forming a second insulation layer to fill spaces between the gates; removing a portion of the second insulation layer which is positioned in each source forming region of each active pattern; forming a source in a portion of the active pattern which is positioned in the source forming region and is exposed due to removal of the second insulation layer; forming a contact plug on the source; forming an interlayer dielectric on the contact plug and the gates; and forming a bit line on the interlayer dielectric to come into contact with the drain and extend in a direction perpendicular to the gates.