Patent ID: 7464128

Claim:
A method for Galois field (GF(2 m )) multiplication by a logic circuit, where m is a positive integer, and the GF(2 m ) multiplication operation calculates the multiplication of two polynomials producing a product which is divided by a generator polynomial, and wherein the multiplication of the two polynomials is combined with the division operation whereby the GF(2 m ) multiplication is computed as a single function GF(2 m ) multiplication operation, the method comprising: generating x m−i polynomial coefficient terms from multiplication and division mathematical operations, where i is a variable; combining x m−i polynomial coefficient terms having the same exponents from the multiplication and division mathematical operations to generate a recurrence relation that represents the combination of the multiplication and division operations; computing the recurrence relation using the combined x m−i polynomial coefficient terms in the single function GF(2 m ) multiplication operation to produce a GF(2 m ) result; and storing the GF(2 m ) result in memory in a computer readable form.