Patent ID: 7840954

Claim:
A computer implemented method for generating code to perform scalar computations on a SIMD RISC architecture, the computer implemented method comprising: generating code directed at loading at least one scalar value; generating code using at least one vector operation to generate a scalar result, wherein all scalar computation for integer and floating point data is performed in a SIMD vector execution unit; determining whether an alignment amount can be determined statically at compile time, wherein the alignment amount can be determined statically when at least a portion of an address can be derived; in response to determining that the alignment amount can be determined statically at compile time: generating first alignment code using the alignment amount determined at compile time; and inserting the first alignment code into the code that was generated to generate a scalar result; in response to determining that the alignment amount cannot be determined statically at compile time: generating dynamic code to dynamically compute the alignment amount; generating second alignment code using the alignment amount computed dynamically; and inserting the dynamic code and the second alignment code into the code that was generated to generate a scalar result; and wherein the first and second alignment code aligns scalar data with respect to a vector register.