Patent ID: 7883965

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a recess channel structure in a semiconductor substrate having a device isolation structure defining an active region; forming a first lower gate conductive layer over the semiconductor substrate including the recess channel structure, the first lower gate conductive layer being conformal to the recess channel structure and defining a recess; forming a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, the holding layer configured to hold a shift of a seam occurring in the recess channel structure; polishing the holding layer until the first lower gate conductive layer is exposed; forming a second lower gate conductive layer over the first lower gate conductive layer and the holding layer, forming an upper gate conductive layer over the second lower gate conductive layer; and patterning the upper gate conductive layer and the first and second lower gate conductive layers to form a gate structure.