Patent ID: 8643149

Claim:
A semiconductor chip comprising: a semiconductor substrate comprising active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure comprises a layer of low dielectric constant (low-k) insulating layer; a first metal bump disposed over the semiconductor substrate and coupled to the active circuitry by way of an under bump metal structure disposed under the first metal bump; a first stress barrier structure disposed under the first metal bump, and disposed over the low-k insulating layer, wherein the first stress barrier structure distributes stress across an area larger than the first metal bump, and wherein the first stress barrier structure and the under bump metal structure are physically separate when viewed in a cross-sectional view through at least a portion of the first stress barrier structure; a second metal bump disposed over the semiconductor substrate, the second metal bump not coupled to the active circuitry; and a second stress barrier structure disposed under the second metal bump, and disposed over the low-k insulating layer.