Patent ID: 7555423

Claim:
A system for interconnecting processors in a processor-based hardware design verification system, comprising: a plurality of interconnected clusters of emulation processors, each cluster of the plurality of interconnected clusters comprising: a plurality of emulation processors that can execute Boolean equations; a shared data storage array, said shared data storage array comprising a plurality of data storage structures, each emulation processor of the plurality of emulation processors within said cluster capable of communicating with each data storage structure within said shared data storage array; an array of outputs, each output of the array of outputs generated from each emulation processor of the plurality of emulation processors; a plurality of multiplexer arrays, each multiplexer array of the plurality of multiplexer arrays comprising: a plurality of multiplexers for selecting output signals; a plurality of input arrays, each input array of the plurality of input arrays containing just one output from each cluster of the plurality of interconnected clusters; and a plurality of outputs, each output of the plurality of outputs communicating with a unique shared data storage array of each cluster of the plurality of interconnected clusters.