Patent ID: 8310875

Claim:
A semiconductor memory device comprising: memory cell units above a semiconductor substrate including serially-connected memory cells, the memory cells including a semiconductor pillar and conductive and insulation films surrounding the semiconductor pillar and configured to store data non-volatilely, the memory cell units constituting blocks each of which is the minimum unit of data erasure; a pipe layer in at least one pair of adjacent first memory cell unit and second memory cell unit of the memory cell units, the pipe layer including a semiconductor layer connected to the semiconductor pillars in the first and second memory cell units, and connected to first ends of the first and second memory cell units; a conductive plate between the first ends of the first and second memory cell units and the semiconductor substrate, the plate containing the pipe layers of at least two blocks and controlling conduction of the pipe layers; and a supply path structure connected to the plate and transmitting a potential the plate.