Patent ID: 7543294

Claim:
A device architecture comprising: a processor arranged to run an operating system (OS) comprising an OS scheduler; hardware comprising a Dynamic Configurable Hardware Logic (DCHL) layer comprised of a plurality of Logic Elements (LEs); and interposed between said OS and said DCHL layer, a TiEred Multi-media Acceleration Scheduler (TEMAS) that cooperates with the OS scheduler for scheduling the LEs of the DCHL to execute applications in accordance with inherited application priorities, where the TEMAS operates in response to configuration requests to configure and reconfigure at least some of the plurality of LEs using the inherited application priorities such that at one time a particular LE is scheduled for operation with a first algorithm logic, and at another time the same particular LE is scheduled for operation with a second, different algorithm logic, where the TEMAS is comprised of a Tier-1 scheduler that communicates with the OS scheduler to determine a difference in timing for the DCHL hardware and at least one Tier-2 scheduler interposed between the Tier-1 scheduler and one DCHL configurable device that operates in response to configuration requests from the Tier-1 scheduler.