Patent ID: 8086657

Claim:
A digital adder device comprising: a complete multiple stage digital adder circuit having at least a first, second, third and fourth stage for generating and propagating groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic CMOS logic in a carry network, said multiple digital adder circuit implementing logic functions and processing input variables from a one stage and outputting result values to a succeeding stage of said added circuit, and, while a) at least one logic stage of relatively high switching activity is implemented in static CMOS hardware logic and at least one logic stage of relatively low switching activity implemented in dynamic CMOS hardware logic, b) a plurality of subcircuits for said multiple stage adder circuit are provided for separately operating 4-bit groups of subsequent bit positions in the operands bit representation together with a footing device ( 42 ) used for enabling for efficient precharging of said dynamic hardware logic, while said multiple stage digital adder circuit has c) a predetermined stage comprising an input ( 60 , 62 ) directly coupled to a stage being positioned earlier than a preceding bypass stage to provide an output from a first stage feed directly as an input ( 60 , 62 ) to a third stage of a carry network.