Patent ID: 7975196

Claim:
Circuitry comprising: A. plural data input paths, each path including a data input buffer having a data input, and a data output; B. a first control signal output path including a first output buffer having a signal input and a signal output; C. a second control signal output path including a second output buffer having a signal input and a signal output; and D. a scan path between a test data input lead and a test data output lead, including: i. a first control scan cell having a functional data input, a functional data output connected to the signal input of the first output buffer, a test data input coupled to the test data input lead, and a test data output separate from the functional data output; ii. data scan cells, each data scan cell having a functional data input connected to the data output of one data input buffer, a functional data output, a test data input, and a test data output, the data scan cells being connected in a series with the test data input of the initial data scan cell in the series being connected to the test data output of the first control scan cell, and the test data output of each data scan cell being connected to the test data input of the next, successive data scan cell; iii. at least one resynchronization memory having a test data input connected to the test data output of the first control scan cell and a test data output; iv. multiplexer circuitry having one input connected to the test data output of the last data scan cell in the series, another input connected to the test data output of the at least one resynchronization memory, and an output; and v. a second control scan cell having a functional data input, a functional data output connected to the signal input of the second output buffer, a test data input coupled to the output of the multiplexer, and a test data output separate from the functional data output coupled to the test data output lead.