Patent ID: 8892622

Claim:
A circuit for performing a divide operation using a restoring division algorithm, the circuit comprising: a plurality of serially-connected stages, wherein each stage of said stages is configured to: receive as inputs on each clock cycle an effective divisor and a first partial remainder; generate as outputs on each clock cycle a second partial remainder and a plurality of quotient digits, wherein each generated quotient digit is selected from a set of 0 and 1, and wherein the second partial remainder is coupled to a subsequent stage; wherein each of a first and last stage of the plurality of stages comprises a restoring series architecture, wherein the restoring series architecture is a radix-4 series architecture for computing two quotient digits per clock cycle, and wherein the radix-4 series architecture comprises: a first adder that receives the first partial remainder and the effective divisor as inputs and generates a first sum and a first carry as outputs; a first multiplexer that receives the first partial remainder and the first sum as data inputs and the first carry as a select input; a second adder that receives a doubled output of the first multiplexer and the effective divisor as inputs and generates a second sum and a second carry as outputs; and a second multiplexer that receives the doubled output of the first multiplexer and the second sum as data inputs and the second carry as a select input, and wherein the output of the second multiplexer is doubled and coupled to a subsequent stage; and wherein each of one or more intermediate stages of the plurality of stages comprises a restoring parallel architecture.