Patent ID: 7350137

Claim:
An error detection circuit for detecting errors in an array of content addressable memory (CAM) cells coupled to wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching data in the CAM cells, the error detection circuit comprising: at least one row parity CAM cell per row of the array, said row parity CAM cell being coupled to the matchline of an associated row, the row parity CAM cell storing a value representing a parity of a predefined portion of an associated row; a row of column parity CAM cells, each column parity CAM cell being coupled to the bitline of an associated column and to a parity matchline, each column parity CAM cell storing a value representing a parity of a predefined portion of an associated column; a parity check circuit for comparing a calculated parity of the predefined portion of data read from a row of the array with data from the associated row parity CAM cell, a row mismatch being determined if the calculated parity mismatches the data from the associated row parity CAM cell; matchline sense amplifiers for providing matchline outputs corresponding to one of a match and a mismatch condition of the matchlines in a search and compare operation for data in one column of CAM cells of said array; a parity matchline sense amplifier for providing a parity matchline output corresponding to one of the match and the mismatch condition of the parity matchline in the search and compare operation for data in the one column of CAM cells of said array; and, a vertical parity checker for calculating a vertical parity of the matchline outputs and for comparing the vertical parity with the parity matchline output, a column mismatch being determined if the vertical parity mismatches the parity matchline output.