Patent ID: 7594047

Claim:
A buffer circuit, comprising: a flip-flop based first-in first-out (FIFO) buffer having an input and an output; selection logic coupled in series with the FIFO buffer input; a random access memory (RAM) FIFO coupled in parallel with the selection logic; wherein the selection logic is to divert incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level such that once the FIFO buffer is filled to the first capacity level the incoming data is no longer sent directly to the FIFO buffer, is to reload the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level, and is to again begin sending the incoming data directly to the FIFO buffer after the FIFO buffer has been emptied to a third capacity level less than the first capacity level and greater than zero; wherein the selection logic comprises: a multiplexer communicatively connected to an input of the FIFO buffer and to an output of the RAM FIFO; a non-multiplexer control to control diversion of the incoming data to the RAM FIFO such that the multiplexer does not control diversion of the incoming data to the RAM FIFO; and wherein data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.