Patent ID: 8866488

Claim:
An apparatus for testing 3DIC semiconductor devices comprising: a first semiconductor device under test (DUT) comprising a first terminal and a second terminal different from the first terminal, wherein the first terminal of the first DUT is connected to a first force pad on a control layer of the apparatus by a first through substrate via (TSV) stack and the second terminal of the first DUT is connected to a first sense pad on the control layer of the apparatus by a second TSV stack; and a second semiconductor DUT comprising a first terminal and a second terminal different from the first terminal, wherein the second DUT is stacked above the first DUT, wherein the first terminal of the second DUT is connected to a second force pad on the control layer of the apparatus by a third TSV and the second terminal of the second DUT is connected to a second sense pad on the control layer of the apparatus by a fourth TSV.