Patent ID: 8159030

Claim:
A CMOS device comprising: a silicon germanium on insulator (SGOI) substrate comprising: a support wafer; an insulating layer overlying the support wafer; and a layer of monocrystalline silicon germanium material having a first lattice constant on the insulating layer, the layer of monocrystalline silicon germanium material having a first P-type region and a second N-type region; a gate electrode overlying the first P-type region; a first channel region having opposing sides in the first P-type region and being located below the gate electrode; a biaxially tensile strained silicon layer interposed between the gate electrode and the first channel region and overlying a portion of the surface of the first P-type region; a gate insulator layer disposed under the gate electrode and overlying the biaxially tensile strained silicon layer; and regions of first monocrystalline semiconductor material embedded at the opposing sides of the first channel, the first monocrystalline semiconductor material comprising silicon and germanium, the first monocrystalline semiconductor material having a second lattice constant less than the first lattice constant and being doped with conductivity determining ions, wherein the first monocrystalline semiconductor material comprises: heavily doped source and drain regions formed in the first P-type region at the opposing sides of the first channel; and implanted source and drain buffer regions formed in the layer of monocrystalline silicon germanium material, wherein the implanted source and drain buffer regions underlie the heavily doped source and drain regions in the first P-type region at the opposing sides of the first channel, the implanted source and drain buffer regions extending through the layer of monocrystalline silicon germanium material to the insulating layer, oxide layers formed on sidewalls of the gate electrode; a first spacer adjacent one of the oxide layers and overlying the biaxially tensile strained silicon layer, the first spacer being in physical contact with the gate insulator layer and a portion of the first monocrystalline semiconductor material; and a liner layer interposed between the one of the oxide layers and the first spacer.