Patent ID: 7671419

Claim:
A transistor comprising: a semiconductor substrate; a well of a first conductivity type formed on the semiconductor substrate; a heavily-doped first impurity region of the first conductivity type surrounding an active region defined in the well; heavily-doped second and third impurity regions of a second conductivity type spaced apart from each other in the active region, the heavily-doped second and third regions configured to define a channel region interposed therebetween; a gate formed over the channel region to cross the active region, the gate configured to overlap at least a portion of the first impurity region and receive a first voltage; an electrode layer formed between the semiconductor substrate and the gate, the electrode layer configured to overlap a portion of the first impurity region contacting the channel region and receive a second voltage; and an insulation layer formed between the semiconductor substrate and the electrode layer, the semiconductor substrate and the gate, and the electrode layer and the gate, the insulation layer configured to surround the electrode layer.