Patent ID: 7119846

Claim:
A video signal processing circuit comprising a frame memory for storing successive frames of a video signal; a writing controller for writing a portion of effective scan lines of a video signal of a first video system having a first number of vertical scan lines into said frame memory in synchronism with vertical and horizontal synchronous signals corresponding to the video signal of the first video system; a reading controller for reading the portion of the effective scan lines of the video signal written in an effective scan line section of said frame memory in synchronism with vertical and horizontal reference signals corresponding to a video signal of a second video system having a second number of vertical scan lines; a signal selector for selectively outputting one of the video signal read out from said frame memory and a pedestal level signal, wherein said reading controller controls said signal selector so as to select the output from said frame memory in the effective scan line section or select the pedestal level signal out of the effective scan line section; and a horizontal pixel number converter for reducing or increasing a number of pixel signals pixels of each scan line of the video signal of the second video system from said frame memory in accordance with a ratio of an effective scan line number of the video signal of the first video system to an effective scan line number of the video signal of the second video system, wherein said horizontal pixel number converter includes a delay circuit for delaying the pixels of each scan line by one clock period, a plurality of coefficient multiplier means for multiplying the pixels of each scan line and the delayed pixels by predetermined coefficients, and a multiple position selector switch for successively obtaining outputs from successive ones of the plurality of coefficient multiplier means.