Patent ID: 8250328

Claim:
A buffered write command circuit for a memory, comprising: a write command buffer included in the memory and configured to buffer write commands and propagate buffered write commands therethrough in response to a clock signal; write command buffer logic included in the memory and coupled to the write command buffer and configured to generate an active clock signal to propagate the buffered write commands through the write command buffer for execution and further configured to suspend the active clock signal in response to the memory receiving a read command after the write command is received and further configured to restart the active clock upon completion of the later received read command; a column address buffer coupled to receive column addresses for write and read commands and configured to buffer column address for buffered write commands and provide the same for execution; and an input buffer coupled to receive write data for write commands and configured to buffer the same during suspension of the active clock and provide the write data for execution of the write command in response to restarting the active clock.