Patent ID: 8250295

Claim:
A memory module connectable to a computer system, the memory module comprising: a board; a plurality of double-data-rate (DDR) memory devices mounted to the board, the plurality of DDR memory devices arranged in a first number of ranks; a circuit that is coupled to said board and that receives from the computer system a set of input control signals that includes a set of first chip select signals and an address signal and that generates a set of second chip select signals based at least in part upon values of said set of first chip select signals and a portion of the address signal; wherein a number of chip select signals of the set of second chip select signals corresponds to a first number of DDR memory devices arranged in the first number of ranks; wherein a number of chip select signals of the set of first chip select signals corresponds to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks; wherein at least one signal of the set of second chip select signals has a value to selectively activate a respective rank of the first number of ranks; wherein the circuit provides one or more of the received set of input control signals to said at least one respective activated rank; wherein the set of input control signals further includes RAS, CAS, WE, BA; wherein the circuit includes an emulator and a register; and wherein the emulator receives from the computer system at least a portion of the set of input control signals that includes RAS, CAS, WE, the set of first chip select signals and the portion of the address signal; wherein the emulator generates the set of second chip select signals in response to the at least a portion of the set of input control signals received by the emulator; wherein the register receives at least another portion of the set of input control signals that includes RAS, CAS, WE, BA and the remaining portion of the address signal; and wherein the register provides one or more of the input control signals received by the register to said at least one respective activated rank.