Patent ID: 8453023

Claim:
A logic value determination method for determining a target logic value to be assigned to an unspecified bit in an input vector which is composed of specified bits of logic values 0 and 1 and unspecified bits and which is applied to a combinational circuit in a scan-designed sequential circuit or an independent combinational circuit, so that a total number of logic value differences between corresponding input and output lines of the combinational circuit increases or decreases, in accordance with an one-to-one correspondence relation provided between a part of or all of the input lines and a part of or all of the output lines, comprising: a first logic value determination step for determining, in a case where an output line has a logic value and corresponding input line has an unspecified value, the logic value of the output line as the target logic value of the input line corresponding to the output line; a second logic value determination step for determining, in a case where an output line has an unspecified value and corresponding input line has a logic value, the target logic value to be assigned to the unspecified bit in the input vector by justification that makes the logic value of the input line appear at the output line; and a third logic value determination step for calculating, in a case where an input line and corresponding output line both have unspecified values, probability of the output line to have logic value 0 and probability of the output line to have logic value 1, and determining the target logic value to be assigned to the unspecified bit in the input vector corresponding to the input line based on difference between the probabilities, wherein the third logic value determination step is repeated until the total number of logic value differences reaches a threshold value.