Patent ID: 6861347

Claim:
A method for forming a metal wiring layer in a semiconductor device, comprising the steps of: forming a stopper layer on a semiconductor substrate, on which a conductive layer is formed; forming an interlayer insulating layer on the stopper layer; forming a hard mask layer on the interlayer insulating layer; forming a first photoresist pattern on the hard mask layer, wherein the first photoresist comprises a first opening having a first width and partially exposing the surfacc of the hard mask layer; forming a partial via hole by etching the hard mask layer and portions of the interlayer insulating layer using the first photoresist pattern as an etching mask; removing the first photoresist pattern; coating the semiconductor substrate comprising the partial via hole with an organic material layer to fill the partial via hole with the organic material layer; forming a second photoresist pattern on the coated semiconductor substrate, wherein the second photoresist pattern comprises a second opening having a second width greater than the first width and being formed to be aligned with the partial via hole; etching the organic material layer and the hard mask layer on the interlayer insulating layer using the second photoresist pattern as an etching mask to form a hard mask pattern; after the hard mask pattern is formed, simultaneously removing the second photoresist pattern and the organic material layer using an oxygen-based etchant; and forming a wiring region having the second width and a via hole having the first width by etching the interlayer insulating layer using the hard mask pattern as an etching mask, wherein the second photoresist pattern is completely removed prior to etching the interlayer insulating layer to prevent contamination of the interlayer insulating layer resulting from removal of the second photoresist pattern.