Patent ID: 6956440

Claim:
A phase locked loop circuit comprising: a phase comparator for comparing a reference frequency of an external clock signal with a comparison frequency of a comparison clock signal; a filter for filtering an output signal from the phase comparator; a voltage controlled oscillator for generating a clock signal having a frequency proportional to a DC signal from the filter; a prescaler for dividing an output clock signal from the voltage controlled oscillator by using at least two division ratios; a program counter for dividing an output signal from the prescaler by a division ratio and outputting the comparison clock signal having the comparison frequency; a swallow counter for controlling the division ratio of the prescaler; a controller for controlling the prescaler by using output signals from the program counter and the swallow counter; and a control signal generator for outputting a control signal to control frequency division of the voltage controlled oscillator by using set points of the prescaler, the swallow counter, and the program counter.