Patent ID: 7968975

Claim:
A semiconductor structure comprising: at least one through substrate via (TSV) extending through a semiconductor substrate; at least one line-level metal wiring structure including an array of cheesing holes and vertically abutting said at least one TSV; a metal-wire-level dielectric layer laterally abutting said at least one line-level metal wiring structure, wherein said at least one line-level metal wiring structure and said metal-wire-level dielectric layer complementarily fill an entirety of a layer located on said at least one TSV, and wherein an entirety of sidewalls of each of said at least one TSV located in a plane including an interface between said at least one TSV and said at least one line-level metal wiring structure abuts said at least one line-level metal wiring structure; and a contact-via-level dielectric layer, wherein a bottom surface of said contact-via-level dielectric layer vertically abuts a top surface of said semiconductor substrate, and wherein each of said at least one TSV extends from a top surface of said contact-via-level dielectric layer to a bottom surface of said semiconductor substrate.