Patent ID: 7305283

Claim:
An on-vehicle electronic control device including: a main control circuit section fed with electric power by a main power supply circuit via a controllable switching element from an on-vehicle battery, and driving current consumers in accordance with an operation state of input sensors and contents of a first program memory; and a timer circuit section fed with electric power at all times via a sub power supply circuit from said on-vehicle battery, said timer circuit section measuring a time period of interruption of said main power supply circuit, and generating an arousal output signal to connect said main power supply circuit to said on-vehicle battery when said measured time period has reached a predetermined arousal target time, wherein said timer circuit section comprises: a timing counter for counting a clock signal generated by a timing clock signal generation circuit, and measuring an elapsed time period from the interruption of said main power supply circuit, in response to a start operation command from said main control circuit section; a timer start time period setting memory for storing and memorizing said predetermined arousal target time; comparison determination output means for generating said arousal output signal when said elapsed time period measured by said timing counter has reached said arousal target time of said timer start time period setting memory; output logic processing means for storing the generation of said arousal output signal, and generating a circuit-closing drive output to close the circuit of said controllable switching element provides between said main power supply circuit and said on-vehicle battery at the time the storage of said arousal output signal; and first and second reset means for erasing a storage content of said output logic processing means; wherein said first reset means is a forced stop command means for carrying out reset by a main CPU of which arousal has been started; and said second reset means is a self-reset means that operates when the reset by said first reset means is not carried out by the time a predetermined time period has passed since the generation of said arousal output signal, and resets the storage of said output logic processing means.