Patent ID: 7514320

Claim:
A method of manufacturing a semiconductor device which has a memory cell area including a capacitor for storing data, and a peripheral circuit area for accessing said memory cell area, said method comprising: forming an underlying plug in said memory cell area in an underlying insulating film formed on a substrate for connection to said capacitor; forming a first wire in said peripheral circuit area on said underlying insulating film, and forming a plate electrode of a first capacitor on said underlying plug in said memory cell area; forming a first opening through said plate electrode to reach said underlying plug; etching an upper portion of said underlying plug by a predetermined amount; forming a capacitive insulating film which covers exposed surfaces of said first wire, said plate electrode, and said underlying plug; forming an inter-layer insulating film on said capacitive insulating film; etching said capacitive insulating film and said inter-layer insulating film through a mask disposed on said inter-layer insulating film to form a second opening for exposing part of said first wire, and removing the inter-layer insulating film within said first opening to expose part of said underlying plug on the bottom of said first opening; and embedding a conductive material in said first and second openings to form a plug in said peripheral circuit area for connection between wires, and to form a storage electrode of said first capacitor in said memory cell area.