Patent ID: 7029987

Claim:
A method of manufacturing a semiconductor device having a shallow trench isolation (STI) structure, comprising: a) providing a semiconductor substrate having a field region and an active region; b) forming a first insulating layer and mask layer in that sequence on the semiconductor substrate; c) patterning the first insulating layer and mask layer, and forming a shallow trench in the semiconductor substrate; d) forming at least one step in the semiconductor substrate at the top of the shallow trench; e) forming a second insulating layer that covers an inner surface of the semiconductor substrate defining the shallow trench; f) subsequently forming a liner layer over the entire surface of the semiconductor substrate; g) subsequently forming a third insulating layer over the entire surface of the semiconductor substrate to such a thickness that the third insulating layer fills the shallow trench; h) polishing the third insulating layer, the liner layer and the mask layer to planarize the same, until a portion of the mask layer is exposed; and i) subsequently performing an etching process to remove the first insulating layer.