Patent ID: 8183602

Claim:
A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a cell array block formed on said semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing said plurality of first lines, and memory cells connected at intersections of said first and second lines between both lines; and a plurality of via-holes each extending in the stacked direction of said cell array layers to individually connect said first or second line in said each cell array layer to said semiconductor substrate, wherein each via-hole is formed continuously through said plural stacked cell array layers, said first or second lines include a step portion as a discontinuous change in width of cross-section in a stacked direction of said cell array layers where said first or second lines are connected to said via-holes, said first or second lines extending continuously to opposite sides of said via-holes, and multiple via-holes having equal lower end positions and upper end positions are connected to said first or second lines in different cell array layers.