Patent ID: 8541280

Claim:
A method for manufacturing a semiconductor structure, comprising: depositing an interlayer dielectric layer ( 105 ) on a semiconductor substrate ( 101 ) to cover a source/drain region ( 102 ) and a gate stack on the semiconductor substrate ( 101 ); etching the interlayer dielectric layer ( 105 ) and the source/drain region ( 102 ), so as to expose a part of the source/drain region ( 102 ) and form a contact hole ( 110 ) extending into the source/drain region ( 102 ); conformally forming an amorphous layer ( 111 ) on the exposed part of the source/drain region ( 102 ); forming a metal silicide layer ( 113 ) on a surface of the amorphous layer ( 111 ); and filling the contact hole ( 110 ) with a contact metal ( 114 ).