Patent ID: 8156394

Claim:
An integrated circuit comprising: A. functional circuitry; B. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; and C. test access port circuitry including: i. a state machine having an input connected to the test clock lead, an input connected to the test mode select lead and control outputs; ii. a multiplexer having data inputs, a control input connected to a control output of the state machine, and an output connected to the test data out lead; iii. a data register having an input connected to the test data in lead, connections to the functional circuitry, a first control input connected to a control output of the state machine, a second control input, and a test data output connected to a data input of the multiplexer; and iv. an instruction register having an input connected to the test data in lead, a control input connected to the a control output of the state machine, a control output connected to the control input of the data register, and a test data output connected to a data input of the multiplexer, the instruction register including a select output that is unconnected to the functional circuitry.