Patent ID: 6877102

Claim:
A chipset supporting multiple CPU's, comprising: a first system logic circuit, applicable to the chipset and connected to a first type CPU; a second system logic circuit, applicable to the chipset and connected to a second type CPU; a double defined signal pin, used as a signal transmission pin; a multiplex switch circuit, coupled to the first system logic circuit, the second system logic circuit and the double defined clock pin for establishing a first conecting between the first system logic circuit and the double defined clock pin, and for establishing a second connection between the second system logic circuit and the double defined clock pin wherein the first type CPU may transfer signals with the first system logic circuit via the first connection and the second type CPU may transfer signals with the second system logic circuit via the second connection; and an independent clock pin, coupled to the second system logic circuit as a clock signal pin, wherein the independent clock pin forms an isolation path without coming across the multiplex circuit so as to be isolated from other signal pins.