Patent ID: 7397477

Claim:
A memory system, comprising: a first block of memory having addressable memory locations at which data can be stored; a second block of memory having addressable memory locations at which data can be stored; and an address decoder coupled to the first and second blocks of memory, the address decoder having address nodes at which memory addresses are applied and configured to decode the memory addresses to access the addressable memory locations of the first block of memory in accordance with a first memory address allocation format and decode the memory addresses to access the addressable memory locations of the second block of memory in accordance with a second memory address allocation format different from the first memory address allocation format, the address decoder being further operable to decode the memory addresses to access the addressable memory locations of the first block of memory in accordance with the second memory address allocation format and decode the memory addresses to access the addressable memory locations of the second block of memory in accordance with the first memory address allocation format.