Patent ID: 6854095

Claim:
An electronic device designing method, comprising: (1) a step for dividing a layout region containing both an easy-to-polish region where a polishing speed of chemical mechanical polishing is high, and a difficult-to-polish region where the polishing speed of chemical mechanical polishing is low, into a plurality of first small regions, each of the first small regions occupying a first uniform area, (2) a step for obtaining a first area ratio of each of the first small regions, the first area ratio being a ratio of the area of a difficult-to-polish region of the first small region to the first uniform area, comparing the first area ratio with a first predetermined area ratio that secures desired planarity after polishing, adding or expanding the easy-to-polish region if the first area ratio is greater than the first predetermined area ratio, and adding or expanding the difficult-to-polish region if the first area ratio is smaller than the first predetermined area ratio, (3) a step for dividing the layout region into a plurality of second small regions, each of the second small regions occupying a second uniform area that is different from the first uniform area, and (4) a step for obtaining a second area ratio of each of the second small regions, the second area ratio being a ratio of the area of the difficult-to-polish region of the second small region to the second uniform area, comparing the second area ratio with a second predetermined area ratio that secures desired planarity after polishing, adding or expanding the easy-to-polish region if the second area ratio is greater than the second predetermined area ratio, and adding or expanding the difficult-to-polish region if the second area ratio is smaller than the second predetermined area ratio.