Patent ID: 8677100

Claim:
An apparatus, comprising: a memory integrated circuit device, including: a memory array; an interface comprising an input pin receiving an instruction; and control logic having a selectable mode of a plurality of addressing modes processing the instruction, the plurality of addressing modes including: a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length, wherein the first length of the address is different from the second length of the address, wherein: a first memory space of the memory array is addressable via the address of the first length, and a second memory space of the memory array is addressable via the address of the second length; and a column decoder and a row decoder, the column decoder and the row decoder accessing (i) all memory locations addressable via the address of the first length and (ii) all memory locations addressable via the address of the second length, wherein, a single copy of the address of the second length, which is received by the interface of the memory integrated circuit device, and which is received by the column decoder and the row decoder, is sufficient to access (i) any of the memory locations addressable by the address of the first length and (ii) any of the memory locations addressable by the address of the second length.