Patent ID: 7411823

Claim:
A memory cell transistor array comprising: a substrate comprising a plurality of trenches, a pillar formed between each pair of trenches; a lower source/drain region formed at the bottom of each trench; an upper source/drain region formed at the top of each pillar, the upper source/drain regions coupled together in series; and a gate structure formed on each sidewall of the trenches, a first trench having a polysilicon gate and gate insulator on each sidewall and a second, adjacent trench having a floating gate and control gate on each sidewall, wherein a first pillar between the first and second trenches comprises a floating body to form a DRAM cell with the gate structure on one side of the first pillar and a flash memory cell with the gate structure on the remaining side of the first pillar, the DRAM cell and the flash memory cell sharing the upper source/drain region in the first pillar.