Patent ID: 7996704

Claim:
A circuit with an asynchronous first in first out (FIFO) interface, comprising: a first circuit portion with a first signal generated by a first source; a second circuit portion, operating according to a second signal and communicating at least one data with the first circuit portion; an asynchronous FIFO interface, comprising: a first FIFO buffer, coupled between the first and second circuit portions to buffer the at least one data communicated between the first and second circuit portions; wherein the first FIFO buffer inputs the at least one data according to a write-in clock; a clock controller device, outputting at least one clock control signal according to a number of data stored in the first FIFO buffer; and a variable integer divider device, dividing the first signal to generate the write-in clock for the first FIFO buffer when the at least one data transmitted from the first circuit portion to the second circuit portion, wherein the write-in clock generated by dividing the first signal is asynchronous with the second signal, wherein the first circuit portion further comprising: a radio frequency (RF) front end receiver, receiving a RF signal, down-converting the RF signal to at least one analog signal according to at least one local signal; a analog-to-digital converter (ADC), converting the at least one analog signal to the at least one data with the write-in clock; wherein the at least one data is inputted into the first FIFO buffer according to the write-in clock and is outputted from the first FIFO buffer according to the second signal.