Patent ID: 8493306

Claim:
A method for restraining noise output by a source driver during power on/off of a power supply, the source driver including a data bus, a plurality of channels, a multiplexer and a plurality of output pads, two of the output pads being coupled via a charge sharing switch, the channels being connected to the output pads via the multiplexer, each channel having a latch unit, data being transmitted on the data bus and stored in the latch units, the source driver being powered by a first supply voltage and a second supply voltage from the power supply, the method comprising: determining whether one of the first supply voltage and the second supply voltage is insufficient by a power down detector, and when the first supply voltage or the second supply voltage is insufficient, performing the following steps: generating a control signal, wherein the control signal is generated according to a reset signal which is asserted when one of the first supply voltage and the second supply voltage is insufficient; sending the control signal to the data bus to set the data transmitted on the data bus to be a predetermined value; sending the control signal to the latch unit to keep the latch units turned on, thereby the data is sent out from the latch units; sending the control signal to the multiplexer to keep the multiplexer turned on for outputting a driving voltage based on the data via the output pads; and sending the control signal to the charge sharing switch to turn off the charge sharing switch, wherein the power down detector further comprises: a first voltage divider configured to receive the first supply voltage to generate a first divided voltage; a first comparator configured to compare the first divided voltage with a threshold voltage; a second voltage divider configured to receive the second supply voltage to generate a second divided voltage, wherein the first voltage divider and the second voltage divider are configured to respectively receive the first supply voltage and the second supply voltage at a same time; a second comparator configured to compare the second divided voltage with the threshold voltage to determine whether the second supply voltage is insufficient; and an OR gate having two input nodes respectively coupled to outputs of the first comparator and the second comparator and to output the reset signal.