Patent ID: 8592271

Claim:
A method for fabricating a metal-gate CMOS device, comprising: providing a substrate having thereon a first region and a second region; forming a first dummy gate structure and a second dummy gate structure within the first region and the second region respectively; forming a first lightly doped drain (LDD) on either side of the first dummy gate structure and a second LDD on either side of the second dummy gate structure; forming a first spacer on a sidewall of the first dummy gate structure and a second spacer on a sidewall of the second dummy gate structure; forming a first embedded epitaxial layer in the substrate adjacent to the first dummy gate structure; masking the first region with a seal layer; forming a first contact hole etch stop layer (CESL) covering the seal layer within the first region and covering the second region, wherein the first CESL does not contain stress; and thereafter forming a second embedded epitaxial layer in the substrate adjacent to the second dummy gate structure.