Patent ID: 8436421

Claim:
A semiconductor device comprising: a substrate; a device isolation region; a first and a second source region and a first and a second drain region, all of which are of a first conductivity type; a first and a second channel region of a second conductivity type located respectively between the first source region and the first drain region and between the second source region and the second drain region; a first transistor including a single trench which is formed on the substrate between the first source region and the first drain region and a first gate electrode which is formed in the single trench; and a second transistor including at least two trenches which are formed on the substrate between the second source region and the second drain region and a second gate electrode which is formed in the at least two trenches, wherein the first channel region is arranged in a first direction of a plan view of the substrate between the first source region and the first drain region, wherein the second channel region is arranged in a second direction of the plan view between the second source region and the second drain region, wherein a distance between the single trench and the device isolation region in a third direction crossing the first direction of the plan view is less than a distance between adjacent ones of said at least two trenches in a fourth direction crossing the second direction of the plan view, and wherein, in the first transistor, the device isolation region is arranged so as to surround the single trench such that the single trench is spaced apart from the device isolation region in the first and the third directions.