Patent ID: 7365728

Claim:
A shift register comprising: a plurality of bistable circuits connected in series, each of the bistable circuits having a first state and a second state and outputting a stage output signal of a logic level in accordance with the state of that bistable circuit, and all or some of the plurality of bistable circuits sequentially taking on the first state for a predetermined time each in accordance with a clock signal that is inputted from outside; a start position setting circuit for keeping the bistable circuit at a start position, which is the bistable circuit specified by a start position instruction signal that is inputted from outside, in the first state; and a reset circuit for setting the bistable circuits other than the bistable circuit at the start position to the second state, after the bistable circuit at an end position, which is the bistable circuit specified by an end position instruction signal that is inputted from outside, has been set to the first state; wherein, when the bistable circuit at the start position is kept at the first state, the bistable circuits from the start position to the end position are sequentially set to the first state for the predetermined time each in accordance with the clock signal.