Patent ID: 7376031

Claim:
A semiconductor memory device comprising: a memory cell including a floating body in an electrically floating state, a first diffusion layer and a second diffusion layer intervening the floating body, and storing data depending on the number of a plurality of majority carriers within the floating body; a word line connected to a gate of the memory cell; a data bit line connected to the first diffusion layer and transmitting the data stored in the memory cell; a reference bit line transmitting a reference voltage; a data sense node connected to the data bit line and transmitting the data in the memory cell; a reference sense node connected to the reference bit line and transmitting the reference voltage; a plurality of transfer gates connected between the data bit line and the data sense node and between the reference bit line and the reference sense node, respectively; and a current load circuit connected to each of the data sense node and the reference sense node and constituted by a transistor equal in conduction type to the memory cell.