Patent ID: 8503678

Claim:
An integrated circuit comprising: key logic to detect a signal indicating an occurrence of a boot-up sequence comprising a plurality of read and write operations and to generate first key data in response to detecting the signal, the first key data specific to the occurrence of the boot-up sequence and for use during the read and write operations of the boot-up sequence; a transmit data path to transmit data to one or more memory devices during the write operations of the boot-up sequence, the transmit data path including, scrambling logic to generate, in parallel and during the write operations of the boot-up sequence, N pseudo random outputs that are uncorrelated with each other, the generating the N pseudo random outputs based on the first key data, XOR logic having as a first input the N pseudo random outputs of the scrambling logic and having as a second input M data bits, the XOR logic to output, in parallel, M scrambled bits, and a transmitter coupled with the XOR logic, the transmitter to transmit the M scrambled bits to the one or more memory devices via a memory interconnect, wherein the M scrambled bits have a substantially pseudo random pattern; and a receive data path to receive data from the one or more memory devices during the read operations of the boot-up sequence, the receive data path including, a receiver to receive, in parallel, M scrambled bits from the memory interconnect, unscrambling logic to generate, in parallel and during the read operations of the boot-up sequence, N pseudo random outputs that are uncorrelated with each other, the generating the N pseudo random outputs by the unscrambling logic based on the first key data, and XOR logic having as a first input the M scrambled bits from the memory interconnect and having as a second input the N pseudo random outputs of the unscrambling logic, the XOR logic to output, in parallel, M unscrambled bits.