Patent ID: 7210057

Claim:
A digital interpolator comprising: a shift register comprising a plurality of flip-flops each having a Q output and a data input, the plurality of flip-flops coupled in series with the Q output of each shift register coupled to the data input of a next flip-flop in the series, the Q output of a last flip flop in the series being coupled to the data input of a first of the flip-flops in the series; a multiplexer having a plurality of inputs coupled to receive the plurality of Q outputs of the flip-flops, and having an output that produces one of the inputs based on a k-bit select input, where k is an integer and the plurality of inputs is equal to 2 k ; wherein the plurality of flip-flops is clocked by a high speed clock having a first frequency to produce a plurality of phases of a first low-speed clock having a second frequency that is substantially lower than the first frequency; and wherein a single binary bit is recirculated through the shift register to produce the positive going edge of each phase of the first low-speed clock.