Patent ID: 8112263

Claim:
A method for logic checking to check an arbitration of an arbiter that is connected to a bus to which at least two master models and at least one slave circuit are connected, wherein each of the at least two master models is set to output a same signal to the bus as a corresponding one of at least two master circuits, wherein at least one slave model is set to output a same signal to the bus as the at least one slave circuit, and wherein a bus master model executes bus access in accordance with a bus protocol, the method comprising: an outputting step of outputting requests from the at least two master models to the arbiter in accordance with the bus protocol by starting transitions of signals at a same cycle time, and outputting the signal from the at least one slave model in response to the signals outputted by the at least two master models; and a checking step of checking the arbitration of the bus access by the arbiter in response to the signals output from the at least two master models and the at least one slave model.