Patent ID: 7719510

Claim:
A shift register, adapted for driving a flat panel display, where the shift register receives an input signal and a clock signal, the shift register comprising: a delay unit, comprising an input terminal and an output terminal, and the delay unit being used to delay the input signal for a half period of the clock signal and then output the delayed input signal; and a buffer unit, receiving an output signal of the delay unit and providing an extra driving power in accordance with the received output signal, wherein, the buffer unit is operated by a fixed first voltage and a fixed second voltage; and wherein the delay unit comprises: a first switching unit, comprising a first end and a second end, wherein the first end is the input terminal of the delay unit, and the first switching unit determines whether to conduct the circuit between the first end and the second end according to the clock signal; a charge storing unit, one end of the charge storing unit being coupled to a third voltage, and another end being coupled to the second end; and a second switching unit, comprising a third end and a fourth end, wherein the third end is coupled to the second end, the fourth end is the output terminal of the delay unit, and the second switching unit determines whether to conduct the circuit between the third end and the fourth end according to the clock signal.