Patent ID: 7860251

Claim:
An encryption-decryption circuit for encrypting and decrypting data comprising: an N-bit shift register configured to store and shift an N-bit keyword; a first exclusive-OR gate array configured to receive M bits from said N-bit shift register and generate a one-bit exclusive-OR result that is shifted into an input of said N-bit shift register, wherein M is greater than one and said first exclusive-OR gate array is configured to generate said one-bit exclusive-OR result from all M bits received from said N-bit shift register; a second exclusive-OR gate array comprising K exclusive-OR gates, each of said K exclusive-OR gates configured to receive one of K bits from said N-bit shift register and one of K data bits from a received K-bit data word and generate therefrom an exclusive-OR result, said K exclusive-OR gates thereby configured to generate one of: 1) a K-bit encrypted data word and 2) a K-bit unencrypted data word, wherein K is greater than one and less than N; and a selection circuit configured to couple K bits from said N bits in said N-bit shift register to inputs of said K exclusive-OR gates in said second exclusive-OR gate array, wherein said selection circuit is configured to select said K bits responsive to a control signal.