Patent ID: 8004913

Claim:
An integrated circuit memory comprising: an array of memory cells having a plurality of columns of memory cells, including at least one redundant column of memory cells, and a plurality of bit lines, each of said plurality of bit lines being coupled to one of said columns; multiplexing circuitry coupled to said plurality of bit lines to group said plurality of bit lines into bit groups having a multiplexer width number of bit lines and responsive to an input memory address to select a bit line from each bit group to carry a signal for a corresponding data bit within a data word to be accesses; redundant column control circuitry coupled to said multiplexing circuitry and responsive to a defect signal indicative of a location of a defective column of memory cells within said array of memory cells to control said multiplexing circuitry to select said bit lines to form said bit groups such that: a set of bit lines forming a bit group that would otherwise include a bit line of said defective column instead includes one or more bit lines to one side of said defective column toward said at least one redundant column and taken from positions shifted by a shift number of bit lines, said defective column thereby being omitted from said set of bit lines and said shift number being less than said multiplexer size number; any other bit group to said one side comprises a selection of bit lines correspondingly shifted by said shift number compared to when said defective column is not present; and at least one of said bit groups extending to said one side includes at least one of said at least one redundant columns.