Patent ID: 8049760

Claim:
A graphics processing apparatus comprising: a plurality of arithmetic logic units (ALUs) configured to receive instructions and associated data configured for processing in parallel; pre-processing logic configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs based on an output of indication logic, the indication logic indicating whether a current instruction and associated data are to be processed by the plurality of ALUs in a horizontal mode or a single ALU in a vertical mode, wherein remaining ALUs are available to process additional instructions and associated data in the vertical mode, wherein the indication logic indicates whether to process in a horizontal mode or a vertical mode based on compatibility of the instructions and associated data with respect to the horizontal and vertical modes; post-processing logic configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.