Patent ID: 7414423

Claim:
A wafer-level test system comprising a probe card, a base layer, an optical layer, and a cover layer and adapted to test multiple image sensor chips of an integrated circuit wafer, wherein: said probe card comprises a detection zone and a circuit zone, said detection zone being transparent, said circuit zone comprising a plurality of electronic circuits arranged thereon and a plurality of probes suspending beneath said detection zone, said probes being electrical conductors for probing said image sensor chips of said integrated circuit wafer to electrically connect said electronic circuits of said circuit zone to said image sensor chips; said base layer is provided in said detection zone, comprising a plurality of first apertures, said first apertures being transparent and the pitch of two adjacent first apertures being equal to the pitch of two adjacent image sensor chips of said integrated circuit wafer; said cover layer is stacked on said base layer, comprising a plurality of second apertures corresponding to said first apertures of said base layer, said second apertures being transparent; said optical layer is sandwiched between said base layer and said cover layer, comprising a plurality of through holes corresponding to said first apertures, and a plurality of optical lens respectively mounted in said through holes for enabling the optical axis of each of said optical lenses to respectively pass through each of said first apertures and said second apertures.