Patent ID: 8140764

Claim:
A system for reconfiguring cache memory, comprising: lower-level cache memory comprising at least a plurality of cache lines, at least one of the cache lines divided into a plurality of sectors; an access bit associated with each of the plurality of sectors of the lower-level cache memory, the access bit representing whether data of a sector associated with the access bit was used; higher-level cache memory comprising at least a plurality of cache lines, at least one of the cache lines divided into a plurality of sectors; a granularity bit associated with each of the plurality of sectors of the higher-level cache memory, the granularity bit representing whether data of a sector associated with the granularity bit should be cached when one or more of other sectors in the same cache line are cached into the lower-level cache memory; a processor operable to use data of one or more sectors of the lower-level cache memory, the processor further operable to update one or more access bit respectively associated with the one or more sectors; and means operable to update one or more granularity bits.