Patent ID: 8384230

Claim:
A semiconductor device comprising: a semiconductor chip of a substantially rectangular shape having an obverse surface, a first long side, a second long side opposite the first long side, a first short side and a second short side, which intersect the first and second long sides, and a plurality of bump electrodes formed on the obverse surface, the plurality of bump electrodes including first bump electrodes arranged along the first long side, second bump electrodes arranged along the first long side and arranged closer to the first short side than the first bump electrodes, third bump electrodes arranged along the second long side, and fourth bump electrodes arranged along the first short side; and a wiring substrate having a main surface, a first side disposed outside of the semiconductor chip and extending substantially parallel with the first long side of the semiconductor chip, a second side disposed outside of the semiconductor chip and extending substantially parallel with the second long side of the semiconductor chip, a plurality of wirings, and a plurality of heat dissipation patterns formed on the main surface thereof, the semiconductor chip being mounted on the wiring substrate such that the obverse surface of the semiconductor chip is faced to the main surface of the wiring substrate, the plurality of wirings comprising first wirings for input signals electrically connected to the first bump electrodes, second wirings for first output signals electrically connected to the second bump electrodes, and third wirings for second output signals electrically connected to the third bump electrodes, the first wirings being extended from the first long side of the semiconductor chip toward the first side of the wiring substrate in a plan view and having first end portions along the first side of the wiring substrate, the second wirings being extended from the first long side of the semiconductor chip toward the first side of the wiring substrate, furthermore, extended toward the second side of the wiring substrate in the plan view and having second end portions along the second side of the wiring substrate, the third wirings being extended from the second long side of the semiconductor chip toward the second side of the wiring substrate in the plan view and having third end portions along the second side of the wiring substrate, the heat dissipation patterns include first heat dissipation patterns respectively having first end portions electrically connected to the fourth bump electrodes and second end portions extended outwardly from the semiconductor chip in the plan view, and a second heat dissipation pattern arranged outside of the first heat dissipation patterns, wherein the second heat dissipation pattern is disposed along the first heat dissipation patterns in the plan view, and wherein the second heat dissipation pattern is electrically separated from the semiconductor chip and the first heat dissipation patterns.