Patent ID: 7957273

Claim:
A packet processor for the transmission of packets having a header and a payload, said packet processor having: a pointer memory containing a plurality of pointers; a host memory containing data for payloads of said packets, each said packet payload data associated with a particular said pointer; a re-transmit controller reading said pointer memory which identifies a location in said host memory, thereafter reading packet data from said host memory location and transferring said packet payload data to a media access controller (MAC) adding at least a packet header to said packet payload data from said input to form a frame, placing said frame into a block buffer which is separate from said host memory, said block buffer transmitting said frame to an output interface; said re-transmit controller sending a block acknowledgement request for a plurality of frames transmitted; a receive acknowledgement input containing identifiers for acknowledged said frames; said re-transmit controller deleting frames from said block buffer after receipt of a block acknowledgement response which identifies previously transmitted frames; said re-transmit controller releasing the packet pointer memory location and host memory location associated with each frame transferred to said block buffer when each said frame is transferred; said re-transmit controller re-transmitting each frame directly from said block buffer for which an acknowledgement has not been received, said re-transmitting being performed until each said frame in said block buffer has been acknowledged; said block buffer thereby containing only complete frames to be transmitted for which receive acknowledgement identifiers have not been received.