Patent ID: 7619315

Claim:
A stack type semiconductor chip package comprising: a first wafer mold including a first chip having first pads on one surface and a first mold layer surrounding and encapsulating the first chip; a protection substrate disposed on the first wafer mold and mechanically bonded with the first wafer mold using a first adhesive layer interposed therebetween, the protection substrate having wiring layers on one surface facing the first pads and electrically connected to the first wafer mold; a second wafer mold disposed under the first wafer mold and mechanically bonded with the first wafer mold using a second adhesive layer interposed therebetween, the second wafer mold including a second chip having second pads and a second mold layer surrounding and encapsulating the second chip; first vias disposed on the sidewalls of the first wafer mold and electrically connecting the wiring layers of the protection substrate with the second pads of the second wafer mold; and second vias electrically connecting the wiring layers of the protection substrate with external connection terminals.