Patent ID: 7904696

Claim:
A hardware apparatus comprising: a first processor core to perform instructions; and an accelerator coupled to the first processor core via a first interconnect and a second interconnect, the accelerator to perform at least one operation on data received from the first processor core, the accelerator comprising a heterogeneous resource with respect to the first processor core and communication logic to enable inter-sequencer communication along the first interconnect between the first processor core and the accelerator according to a non-native communication protocol for the first interconnect, wherein the accelerator is to transmit a signal on the first interconnect to compete for a lock on the first interconnect with a plurality of other accelerators coupled to the first and second interconnects, and responsive thereto the first processor core is to select the accelerator to obtain the lock, and the accelerator is to communicate identification and capability information to the first processor core, and thereafter the first processor core is to generate an assertion signal on the second interconnect to enable the inter-sequencer communication.