Patent ID: 8773940

Claim:
A memory cell, comprising: a cross-coupled latch comprising first and second storage nodes; a first write pass gate transistor having a pair of current terminals coupled between said first storage node and one of at least one bit line and having a control terminal coupled to a write word line; a second write pass gate transistor having a pair of current terminals coupled between said second storage node and one of at least one complementary bit line and having a control terminal coupled to said write word line; a first read pass gate transistor having a pair of current terminals coupled between said first storage node and one of said at least one bit line and having a control terminal coupled to a read word line; a second read pass gate transistor having a pair of current terminals coupled between said second storage node and one of said at least one complementary bit line and having a control terminal coupled to said read word line; and wherein said first and second write pass gate transistors are implemented at a first strength level and wherein said first and second read pass gate transistors are implemented at a second strength level which is less than said first strength level.