Patent ID: 7830701

Claim:
An integrated circuit, comprising: a non-volatile two-terminal cross-point memory array including a plurality of two-terminal memory cells, each two-terminal memory cell operative to store data as a plurality of conductivity profiles; and a substrate including active circuitry in electrical communication with the non-volatile two-terminal cross-point memory array, the non-volatile two-terminal cross-point memory array is fabricated over the substrate and is in contact with the substrate, the active circuitry including: a memory access circuit configured to select at least one of the plurality of two-terminal memory cells for a read operation, a sensing circuit configured to sense a data signal from selected two-terminal memory cells, the data signal indicative of stored data in selected two-terminal memory cells, and a margin manager circuit configured to manage a read margin for selected two-terminal memory cells substantially during the read operation and operative to determine if a value of the stored data in selected two-terminal memory cells is within a specified level of the read margin.