Patent ID: 7948263

Claim:
An integrated circuit device, comprising: a logic circuit electrically coupled to a first power rail and a virtual power rail; a switching circuit electrically coupled to the virtual power rail and a second power rail, said switching circuit configured to electrically couple the virtual power rail to the second power rail to thereby power said logic circuit during an active mode of operation and further configured to electrically decouple the virtual power rail from the second power rail to thereby disable said logic circuit during a standby mode of operation; a data retention circuit electrically coupled to an output of said logic circuit, said data retention circuit configured to latch data received from the output of said logic circuit during the active mode of operation and further configured to hold previously latched data therein during the standby mode of operation while concurrently blocking changes in the output of said logic circuit from becoming latched therein; and a voltage level transition circuit responsive to a mode control signal, said voltage level transition circuit configured to electrically couple the virtual power rail to the first power rail in response to a transition of the mode control signal that reflects commencement of the standby mode of operation and further configured to decouple the virtual power rail from the first power rail in response to a transition of the mode control signal that reflects commencement of the active mode of operation.