Patent ID: 8324675

Claim:
A flash memory device comprising: a substrate extending in a first direction; a channel region having an internal space and an upper end, and extending from the substrate in a second direction perpendicular to the first direction; an insulation pillar filling the internal space of the channel region; a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction; and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of the upper end of the channel region so as to directly contact the channel region, wherein the channel region includes: a first channel region defining the internal space, and having the side wall surrounded by the bit line; and a second channel region overlapping the insulation pillar, and having the upper surface surrounded by the bit line, wherein an upper surface of the first channel region and the upper surface of the second channel region are on the same level.