Patent ID: 7368366

Claim:
A method of forming integrated circuitry, comprising: forming isolation trenches within semiconductive material of a first area of circuitry of a semiconductor substrate and within semiconductive material of a second area of circuitry of the semiconductor substrate, the first circuitry area comprising a first minimum active area spacing between the isolation trenches received therein and the second circuitry area comprising a second minimum active area spacing between the isolation trenches received therein, the first minimum active area spacing being less than the second minimum active area spacing; depositing a first insulative material to within the isolation trenches of the first circuitry area and to within the isolation trenches of the second circuitry area, the first insulative material less than filling remaining volume of the isolation trenches within the semiconductive material of the second circuitry area; and after depositing the first insulative material, depositing an insulative nitride-comprising layer to within the isolation trenches within the semiconductive material of the second circuitry area but not to within the isolation trenches within the semiconductive material of the first circuitry area, the insulative nitride-comprising layer comprising opposing sidewalls that face one another within the semiconductive material and a base surface extending from and between the opposing and facing sidewalls within the semiconductive material.