Patent ID: 7663583

Claim:
A substrate comprising: a plurality of gate and data lines crossing each other, the gate and data lines defining a plurality of pixel regions; a plurality of thin film transistors formed at crossing portions of the gate and data lines; a plurality of common lines between the gate lines, wherein the common lines alternate with the gate lines in a direction along which the data lines extend; a plurality of common electrodes projecting from the common lines; a plurality of pixel electrodes connected with drain electrodes of the thin film transistors, the pixel electrodes formed in the pixel regions between the common electrodes; a first common voltage supplying line that forms a first closed circuit by grouping adjacent odd numbered common lines; and a second common voltage supplying line that forms a second closed circuit by grouping adjacent even numbered common lines, wherein the first and second common voltage supplying lines are formed on the same layer as the data lines, and the common lines and the common electrodes are on the same layer as the gate lines, wherein the first common voltage supplying lines connected with the odd numbered common lines through first contact holes formed in an insulating layer at both ends of the respective odd numbered common lines, wherein the second common voltage supplying lines connected with the even numbered common lines through second contact holes formed in an insulating layer at both ends of the respective even numbered common lines, and wherein the first and second contact holes are formed on an outer region of a display region including the plurality of the pixel regions and are not formed in the display region, wherein the first contact holes are respectively formed at portions that the first common voltage supplying lines overlap the odd numbered common lines so that the first common voltage supplying lines directly contact with the odd numbered common lines through the first contact holes formed on the outer region, wherein the second contact holes are respectively formed at portions that the second common voltage supplying lines overlap the even numbered common lines so that the second common voltage supplying lines directly contact with the even numbered common lines through the second contact holes formed on the outer region.