Patent ID: 7221206

Claim:
Integrated circuit device comprising: a wiring; a clock signal output circuit including a ring oscillator, wherein the ring oscillator includes a plurality of delay gates, which is connected each other annularly and generates a clock signal with a frequency of a reference clock signal, and wherein the clock signal output circuit generates and outputs a multiplied clock signal obtained by multiplying the frequency of the reference clock signal with a digital phase locked ioop method on the basis of the clock signal; an internal circuit operated on the basis of the multiplied clock signal; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit, wherein the electric power is stabilized by reducing a voltage of the power from the external circuit; and a capacitor connection terminal for connecting an external noise reduction capacitor to the wiring connecting to the internal circuit, wherein the wiring connects among the clock signal output circuit, the internal circuit and the internal power supply generation circuit, the internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal, and the internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.