Patent ID: 7010740

Claim:
A system wherein data is read from, and stored in, a memory, such data having associated therewith an address/control portion, such system comprising: (A) a pair of independent controller sections, one of such sections being a primary section and the other one of the sections being a secondary section, both such sections being configured to implement identical control logic in controlling the transfer of such data between a first port connected to the pair of controller sections and a write data port, the write data port of the primary section being connected to the memory, such first port receiving the address/control portion associated with the data, the address/control portion at the first port being processed by the control logic of the primary section and the address/control portion at the first port being processed by the control logic of the secondary section; and (B) a checker producing a no-operation (NOOP) command to the memory if the address/control portions processed by the control logics of the primary and secondary sections are different from one another.