Patent ID: 7535792

Claim:
A data transmission control device comprising: a memory control unit that is connected to a DRAM, and accesses to the DRAM in accordance with a read/write request from various devices that request read/write of data from/into the DRAM; and a command control unit that issues an active command of designating a row address of the DRAM to start a memory access cycle when the read/write request is made, and issues a precharge command to the DRAM to end the memory access cycle, and that prohibits issuance of a precharge command in a previous memory cycle if the issuance of the precharge command is unnecessary, wherein the command control unit determines that the issuance of the precharge command is unnecessary if another read/write request from/into the same page as a page requested in a memory access cycle is made, and determines that the issuance of the precharge command is necessary if another read/write request from/into a page different from a page requested in a memory access cycle is made, or no read/write request is repeated with a predetermined number of times, which are equal to or greater than two, as an upper limit.