Patent ID: 7283397

Claim:
A non-volatile memory system provided on a single integrated circuit chip for storing inputted data therein, comprising: an array of electrically alterable memory cells that individually include a field effect transistor having a storage element and a threshold level that is variable in accordance with an amount of charge carried by the storage element, said array being divided into blocks of cells that are resettable together, cells within said blocks being addressable for application of programming voltage conditions to individually program them into one of more than two distinct threshold level ranges corresponding to more than one bit of input data per cell, a reset circuit that simultaneously applies reset voltage conditions to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state, a programming circuit that applies the programming voltage conditions in parallel to a plurality of addressed cells within a reset block to drive the effective threshold voltage of the addressed cells toward one of the more than two programmable threshold level ranges in accordance with a chunk of inputted data being stored therein, a reading circuit that monitors in parallel the threshold level ranges of the plurality of addressed cells, and a control circuit that individually terminates application of the programming voltage conditions to any one of the plurality of addressed cells when the reading circuit verifies that said any one cell has reached the programmable threshold level range that corresponds to the inputted data being stored therein, while enabling further application of the programming voltage conditions to others of the plurality of addressed cells that have not yet been so verified, until all of the plurality of addressed cells are verified to have correctly been programmed with the chunk of inputted data.