Patent ID: 8723550

Claim:
A semiconductor device comprising: a first transistor; a second transistor; a capacitor; a first circuit; a second circuit; a third circuit; and a fourth circuit, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein a gate of the first transistor is electrically connected to a first electrode of the capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to a second electrode of the capacitor, wherein a gate of the second transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a load, wherein the first circuit configured to control electrical connection between the source and the drain of the second transistor by a current pathway different from a channel of the second transistor; wherein the second circuit is configured to control electrical connection between the gate and the other of the source and the drain of the second transistor, wherein the third circuit is configured to control electrical connection between a current source circuit and the other of the source and the drain of the second transistor, and wherein the fourth circuit is configured to control electrical connection between a power source line and the other of the source and the drain of the second transistor.