Patent ID: 7218563

Claim:
A nonvolatile memory circuit, comprising: a virtual ground array of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns, each of the nonvolatile memory cells including: a gate, a first current carrying terminal, and a second current carrying terminal; switching circuitry coupling the current carrying terminals of the nonvolatile memory cells to reference and precharge voltages and sense amplifiers; and logic controlling the switching circuitry and the virtual ground array, the logic responding to a read command, by causing at least: coupling one of the current carrying terminals of first and second nonvolatile memory cells of the virtual ground array to the reference voltage, reducing leakage currents associated with the read command by coupling another of the current carrying terminals of the first and second nonvolatile memory cells to the precharge voltage, and measuring currents flowing through the first and second nonvolatile memory cells via sense amplifiers coupled to said another of the current carrying terminals of the first and second nonvolatile memory cells.