Patent ID: 8854065

Claim:
A circuit arrangement, comprising: a load transistor comprising a control terminal, a first load terminal and a second load terminal, wherein the load transistor is configured to be operated in an on-state or in an off-state; a sense transistor comprising a control terminal, a first load terminal and a second load terminal, wherein the first load terminal of the load transistor is coupled to the first load terminal of the sense transistor and wherein the sense transistor is configured to be operated in an on-state or in an off-state; and a measurement circuit comprising a current source configured to provide a calibration current, the measurement circuit configured to measure a first voltage between the first load terminal and the second load terminal of the sense transistor in the on-state of the sense transistor, to determine a resistance of the sense transistor based on the calibration current and the first voltage, to measure a second voltage between the first load terminal and the second load terminal of the load transistor in the on-state of the load transistor, and to determine a load current through the load transistor based on the resistance of the sense transistor and the second voltage.