Patent ID: 7949041

Claim:
A memory system supported on a printed-circuit board, the system comprising: a bidirectional communication lane having one or more circuit board traces; a memory controller integrated circuit (IC) having: a first transmitter with M filter taps and an output driver, the first transmitter to communicate first signals onto the circuit board traces of the bidirectional communication lane; and a first receiver with X filter taps, the first receiver to receive second signals from the bidirectional communication lane; and a memory device IC coupled to the communication lane to receive the first signals from the first transmitter, the memory IC having: a second receiver; a number of receive filter taps less than X; and a second transmitter, with a number of transmit filter taps less than M, coupled to the bidirectional communication lane to transmit the second signals to the first receiver; wherein the second signal is a corrupted signal that includes inter-symbol interference, and wherein the memory controller IC includes a signal monitor to provide a measure of the inter-symbol interference; and wherein the memory controller IC includes equalization control circuitry coupled between the signal monitor and the first transmitter, and wherein the equalization control circuitry adjusts at least one of the M filter taps of the first transmitter responsive to the measure of inter-symbol interference.