Patent ID: 7855120

Claim:
A method of forming a resistor for an integrated circuit device, the method comprising: forming an insulating layer on an integrated circuit substrate; forming a first conductive layer on the insulating layer; forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer, wherein the first and second conductive layers comprise different materials; forming a hole in the second conductive layer so that portions of the first conductive layer are exposed through the hole wherein remaining portions of the second conductive layer surround portions of the first conductive layer exposed through the hole; after forming the hole, forming an insulating capping layer on the second conductive layer and on portions of the first conductive layer at the formed hole; and after forming the hole and after forming the insulating capping layer, patterning the first and second conductive layers and the insulating capping layer so that the insulating capping layer is maintained on portions of the first conductive layer at the formed hole, and so that portions of the insulating layer surrounding the portion of the first conductive layer at the formed hole are free of the first and second conductive layers and the insulating capping layer.