Patent ID: 7795743

Claim:
A wiring substrate comprising: a substrate body having an upper surface and lower surface, wherein an outer periphery of the lower surface includes outer corner regions and side regions extending between the outer corner regions; a resin encapsulating area disposed on the upper surface of the substrate body and adapted to receive a semiconductor chip; conductive wiring layers having bonding pads formed inside the resin encapsulating area and electrically connectable to a semiconductor chip when disposed within the resin encapsulating area; upper ball pads formed on the upper surface of the substrate body; and lower ball pads formed on the lower surface of the substrate body, wherein at least one of the wiring layers is electrically connected to at least one of the upper and lower ball pads, wherein the lower ball pads include inner ball pads dispersed on a first area on the lower surface of the substrate opposite to the resin encapsulating area on the upper surface of the substrate, and outer ball pads dispersed on a second area on the lower surface of the substrate, wherein the second area surrounds the first area such that the outer ball pads are located in the outer periphery of the lower surface of the substrate, wherein each of the outer ball pads has a greater surface area than each of the inner ball pads, wherein the outer ball pads include first outer ball pads dispersed in each of the side regions of the outer periphery of the lower surface of the substrate, and second outer ball pads dispersed in each of the corner regions of the outer periphery of the lower surface of the substrate, and wherein each of the second outer ball pads has a greater surface area than each of the first outer ball pads.