Patent ID: 8785270

Claim:
A method for fabricating a semiconductor device, comprising: a) forming a plurality of trenches on a substrate using a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and shield electrode pickup trenches located in a termination area outside an active area containing the active gate trenches, the gate runner/termination trenches including one or more trenches that define a mesa located in an area outside an active area containing the active gate trenches; forming asymmetric sidewalls in the one or more trenches that define the mesa, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered by the second mask; b) forming a first conductive region in the one or more trenches that define the mesa; c) forming an intermediate dielectric region and a termination protection region in the one or more trenches that define the mesa using a second mask; d) forming a second conductive region in the one or more trenches that define the mesa; e) forming a first electrical contact to the second conductive regions, forming a second electrical contact to the first conductive region in the shield electrode pickup trenches located in the termination area, and forming one or more Schottky diodes within a mesa formed between termination trenches in an area outside an active area containing the active gate trenches using a third mask.