Patent ID: 8778762

Claim:
A method of forming a construction comprising vertically-stacked memory cells, the method comprising: forming a stack of alternating electrically conductive levels and electrically insulative levels over a semiconductor base; forming a first hardmask material over the stack; forming a first opening through the first hardmask material; extending the first opening through the stack; forming cavities extending into the electrically conductive levels along sides of the first opening; forming blocking dielectric material along exposed edges of the electrically conductive levels within the cavities; forming a fill material within the first opening and within the cavities; the fill material comprising a charge-storage material; forming a second hardmask material over the first hardmask material and over the fill material; forming a second opening through the second hardmask material, the second opening being narrower than the first opening; extending the second opening into the fill material to form an upwardly-opening container from the fill material; patterning the second hardmask material to form a third opening which is wider than the second opening; extending the third opening into the fill material to remove sidewalls of the upwardly-opening container while leaving the fill material within the cavities as charge-storage structures; the charge-storage structures having first sides against the blocking dielectric material and having second sides along the third opening; forming gate dielectric along the second sides of the charge-storage structures; and forming channel material along the gate dielectric and spaced from the charge-storage structures by the gate dielectric.