Patent ID: 7571284

Claim:
A single chip multithreaded processor, comprising: a plurality of processor cores, wherein each core supports multiple data processing threads; a plurality of second level cache memories coupled to said plurality of processor cores for storing or loading data; and a stream processing unit in at least one of said plurality of processor cores, comprising: a direct memory access module operable to generate a memory request to at least one of said plurality of second level caches, wherein said memory request comprises a destination queue buffer identification tag; and a circular queue module comprising a plurality of queue buffers operable to store load data returned by said at least one of plurality of second level caches in response to said memory request, wherein said returned load data is stored in a predetermined queue buffer corresponding to said destination queue buffer identification tag; wherein said direct memory access module issues a plurality of requests in a predetermined order and wherein said destination queue buffer identification tags correspond to predetermined destination queue buffers in said circular queue module for receiving load data returned by said plurality of second level caches; and wherein said circular queue module further comprises a reorder read pointer that points to a queue buffer in the circular queue module that contains last returned load data, wherein all queue buffers in front of the queue buffer pointed to by the reorder read pointer in the circular queue contain returned load data.