Patent ID: 8332701

Claim:
An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver, comprising: a basic recursive unit; and L recursive units, represented as a first unit to L-th recursive units, L≧2; based on a QPP function Π(i)=(f 1 i+f 2 i 2 ) mod k, i=0, 1, . . . , k−1, said apparatus inputs a plurality of configurable parameters, serially generates a plurality of interleaver addresses by using said basic recursive unit, and parallel generates L sets of corresponding interleaver addresses by using said first to L-th recursive units, wherein whenever said basic recursive unit or said j-th recursive unit generates an interleaver address, the interleaver address generated by said basic recursive unit is outputted to said first recursive unit, while the interleaver address generated by said j-th recursive unit is outputted to said (j+1)-th recursive unit, Π(i) is the i-th interleaved address generated by said apparatus, f 1 and f 2 are QPP coefficients, k is information block length of an input sequence, 1≦i≦k−1, 1≦j≦L−1, and mod is modulus computation.