Patent ID: 8661390

Claim:
A method of block binder extraction and its application to block placement of an integrated circuit, the method comprising: automatically extracting the block binders before block placement based on an algorithm that analyzes a net-list of the integrated circuit; packing a plurality of blocks relative to one another to form a configuration of the block binder before block placement; preparing a net-list, wherein the net-list comprises a plurality of blocks and a block area for each of the blocks and further comprising dimensions of standard cells, wherein the net-list comprises a plurality of nodes, and wherein each node represents a module, and each edge represents a parent-child relationship between two modules; processing the nodes in net-list to determine or create candidate nodes for the block binder extraction, comprising: for each node determining if the node is a candidate node: merging several nodes under a new candidate node; storing candidate node data; and skipping child nodes if a node is marked as a candidate; processing the nodes that are already marked as candidates for extraction, comprising: extracting the block binders by receiving the candidate nodes from the processing phase and creating a block binder for each candidate node; and differently extracting the candidate nodes based on master types extracting an S-M (same-master) block binder or a D-M (different-master) block binder; extracting an S-M block binder that comprises two to sixty-four blocks; and extracting a configuration of the S-M block binder that comprises an N/2×M*2 matrix, wherein the matrix is formed by N/2 rows and 2*M columns; and repeating until N/2 equals 1.0.