Patent ID: 8051341

Claim:
A semiconductor memory device comprising: a test address generating circuit configured on semiconductor memory device, the test address generating circuit configured to generate a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal, wherein the test address generating circuit comprises: a counting unit, including a plurality of counting sub-units, that generates the plurality of test addresses in response to an internal address generation signal, the plurality of counting sub-units including a first counting sub-unit that counts up from a first initial value, and that generates a plurality of test addresses, and a second counting sub-unit that counts down from a second initial value, and that generates a plurality of test addresses; an address input unit that receives the externally applied test address generation signal, and that generates the internal address generation signal to generate the test address; and a selection unit that selects one of the plurality of counting sub-units and transmits the internal address generation signal to the selected counting sub-unit.