Patent ID: 6862565

Claim:
An apparatus for pseudo-random testing binary emulation, comprising: a random code generator capable of generating an initial machine state and a binary instruction sequence; a native architecture execution engine capable of executing the binary instruction sequence to produce a first final state; a target architecture execution engine capable of executing the binary instruction sequence concurrently with the native architecture execution engine to produce a second final state, the target architecture execution engine comprising a binary emulator capable of emulating the binary instruction sequence according to the target architecture; and a verification engine capable of comparing the first final state and the second final state, wherein when the first final state and the second final state do not match, an emulation failure has occurred, wherein the verification engine pinpoints an exact machine instruction, a register number, and an input machine state that caused the emulation failure; wherein an emulated binary instruction sequence that generates the emulation failure is a sequence of binary instructions, enabling the emulation failure to be determined at a machine instruction level.