Patent ID: 7743288

Claim:
An integrated circuit device on which is implemented a bit error ratio tester that tests the bit error ratio of a device under test (DUT), comprising: a variable delay line that receives as input a first clock signal and is operative to variably phase-delay the first clock signal to produce a second clock signal having phase that steps, in time, across a data eye of a data signal containing jitter from the DUT; transmitter circuitry that receives as input the first clock signal and is operative to generate and transmit pseudo-random binary sequence (PRBS) data, synchronized with the first signal, to the DUT; and receiver circuitry that receives as input the data signal from the DUT and the second clock signal, and is operative to use the second clock signal to recover the PRBS data from the data signal and to determine, for each of the steps in the phase of the second clock signal, a bit error ratio of the recovered PRBS data, wherein the receiver circuitry comprises: circuitry that outputs a first control signal based on a frequency associated with the second clock signal, circuitry that outputs a second control signal based on the data signal, and selection circuitry that selects as output one of the first and second control signals based on the frequency associated with the second clock signal.