Patent ID: 7685482

Claim:
An integrated circuit comprising: at least one test input configured to receive test data from off chip and a test clock from off chip; a plurality of circuitry to be tested; at least one test control circuitry between said at least one test input and said plurality of circuitry to be tested, wherein said integrated circuit is arranged so that test data on a data line is clocked in with respect to a rising clock edge of said test clock and test data on said data line is clocked in with respect to a falling clock edge of said test clock; circuitry for separating test data clocked in on the rising edge of the clock signal and test data clocked in on the falling edge of said clock signal, wherein said separating circuitry comprises a plurality of flip flops, one of which is clocked by a clock signal and the other of which is controlled by an inverse of the clock signal; and a plurality of test control circuitry, wherein test data clocked in or out on the rising clock edge is directed to or from respectively a first one of said plurality of test control circuitry and test data clocked in or out on the falling clock edge is directed to or from respectively a second one of said plurality of test control circuitry, wherein test data on said data line clocked in on said rising clock edge is directed to a first one of said plurality of circuitry to be tested and test data on said data line clocked in on said falling clock edge is directed to a second one of said plurality of circuitry to be tested, wherein data is captured by oversampling, and wherein said circuit comprises a plurality of portions, each portion including test control circuitry, wherein said test data is clocked in a plurality of time slots, with test data for different ones of said plurality of portions being allocated to different time slots.