Patent ID: 8345475

Claim:
A memory cell comprising: a cell transistor including a gate region, a source region, a drain region, and a first insulating spacer proximate the drain region and abutting the gate region, wherein the cell transistor is configured to trap a first electric charge in the first insulating spacer when a first bit in the memory cell is programmed to a first binary state and release the first electric charge in the first insulating spacer when the first bit in the memory cell is programmed to a second binary state; a source-side sense amplifier configured to read a programmed state of the first bit; a drain-side write driver configured to supply a program voltage to the drain region when the first bit is programmed; a source-side transistor configured to conduct current from the source region to ground when the first bit is programmed to the first binary state, to impede current from the source region to ground when the first bit is programmed to the second binary state, and to impede current from the source region to ground when the first bit is read; and a drain-side transistor configured to conduct current from the drain region to ground when the first bit is read, and to impede current from the drain region to ground when the first bit is programmed.