Patent ID: 8199866

Claim:
A receive circuit, comprising: a receiver that samples a signal, the receiver comprising a first sampler that samples a voltage level associated with an expected edge of the signal and a second sampler that samples digital values represented by the signal, the samplers collectively generating a set of at least three samples associated with each one of plural edge crossings in the signal; a phase alignment circuit that detects an edge of the signal; and an offset-calibration circuit coupled to the phase alignment circuit to correct, responsive to correlation of specific signal patterns with edge timing represented by the signal, receiver voltage offset associated with sampling the signal in dependence upon detected correlation, wherein the offset-calibration circuit corrects the receiver voltage offset by varying the receiver voltage offset by a first polarity if a correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect to an expected edge for a second signal transition, and by a second polarity if correlation is detected that indicates that the actual edge tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition.