Patent ID: 8000471

Claim:
In an iterated block cipher, a method for round key encryption and key generation, the method comprising: providing a first function F i and a second function F j ; providing hardware implementation of the first function F i and hardware implementation of the second function F j ; providing a round key generation function, the round key generation function being operative to utilize, in any given round, exactly one of: the first function F i ; and the second function F j ; providing a round mixing function, the round mixing function being operative to utilize, in any given round, exactly one of: the first function F i ; and the second function F j ; providing an implementation of the round key generation function, the implementation of the round key generation function being operative to utilize, in any given round, exactly one of: the hardware implementation of the first function F i ; and the hardware implementation of the second function F j ; providing an implementation of the round mixing function, the implementation of the round mixing function being operative to utilize, in any given round, exactly one of: the hardware implementation of the first function F i ; and the hardware implementation of the second function F j ; utilizing the implementation of the round key generation function in at least a first round to generate a second round key for use in a second round; utilizing the implementation of the round mixing function in at least the first round to mix a first round key with a cipher state; outputting a temporal result of the round key generation function; and outputting a temporal result of the round mixing function, wherein one of the following is performed in the first round: the implementation of the round key generation function utilizes the hardware implementation of the first function F i to generate the second round key for use in the second round, substantially simultaneously with the implementation of the round key mixing function utilizing the hardware implementation of the second function F j to mix the first round key with the cipher state; and the implementation of the round key generation function utilizes the hardware implementation of the second function F j to generate the second round key for use in the second round, substantially simultaneously with the implementation of the round key mixing function utilizing the hardware implementation of the first function F i to mix the first round key with the cipher state.