Patent ID: 8766453

Claim:
A packaged integrated circuit, comprising: a package substrate; a die mounted to a first major surface of the package substrate; one or more inner solder pads on an inner portion of a second major surface of the package substrate, wherein the second major surface is opposite the first major surface, a perimeter of the inner portion is aligned with a perimeter of the die, the one or more inner solder pads are the only solder pads on the inner portion, the one or more inner solder pads number no more than five, and an average of areas of the one or more inner solder pads is an inner average; and a plurality of outer solder ball pads on an outer portion of the second major surface that comprise all of the solder ball pads on the second major surface exclusive of the one or more inner solder pads, wherein an average of areas of the plurality of outer solder ball pads is an outer average, the inner average area is at least five times the outer average, the plurality of outer solder ball pads are for receiving solder balls, the outer portion is spaced from the perimeter of the inner portion, and the outer portion and the inner portion are coplanar.