Patent ID: 8705654

Claim:
Radio frequency (RF) communications circuitry comprising: control circuitry adapted to select one of a calibration mode, a phase measurement mode, and a normal operation mode; and delay locked loop (DLL) circuitry adapted to operate in one of the calibration mode and the phase measurement mode and comprising: a digital delay line comprising a plurality of alpha digital delay elements coupled in series, such that the digital delay line is adapted to: during the calibration mode, receive and forward a reference clock signal through the plurality of alpha digital delay elements, such that a delay of each of at least some of the plurality of alpha digital delay elements is adjusted to make a phase difference between an output from one of the plurality of alpha digital delay elements and an output from another of the plurality of alpha digital delay elements equal to about zero; and during the phase measurement mode, receive and forward a feedback signal through the plurality of alpha digital delay elements, such that the feedback signal is representative of an RF output signal from an RF power amplifier; and data capture circuitry adapted to during the phase measurement mode: capture output status from each of the at least some of the plurality of alpha digital delay elements in response to a first transition of the reference clock signal, such that the reference clock signal is representative of an RF input signal to the RF power amplifier; and provide first phase difference information based on the captured output status from the each of the at least some of the plurality of alpha digital delay elements, such that the first phase difference information is indicative of a phase difference between the RF input signal and the RF output signal.