Patent ID: 7667317

Claim:
A semiconductor package comprising: a substrate having upper and lower surfaces and comprising first and second electrical paths, the first and the second electrical paths including first and second through holes, respectively, each of the first and the second through holes electrically connecting between the upper and the lower surfaces of the substrate; a semiconductor chip mounted on the upper surface and comprising a plurality of pads, the pads including a first pad to be supplied with a power supply and a second pad to be grounded; and at least one bypass capacitor mounted on the lower surface and comprising first and second terminals, the first and the second terminals being connected to the first and the second pads through the first and the second electrical paths, respectively. at least one first land formed on said lower surface of said substrate to supply a first power voltage to said first pad; and at least one second land formed on said lower surface of said substrate to supply a second power voltage to said second pad.