Patent ID: 7087533

Claim:
A method for fabricating a semiconductor device, comprising the steps of: sequentially forming a gate insulating film and a conductive layer for a gate electrode on a semiconductor substrate; forming a multi-layered hard mask layer on the conductive layer; etching the hard mask layer, the conductive layer and the gate insulting film using a gate electrode mask to form a stacked structure of a gate insulating film pattern, a gate electrode and a hard mask layer pattern serving as a gate pattern; forming an insulating film spacer on a sidewall of the stacked structure; forming an interlayer insulating film on the entire surface; etching the interlayer insulating film using a landing plug contact etching mask to form a landing plug contact hole exposing the semiconductor substrate; forming a conductive layer for a landing plug on the entire surface so as to fill the landing plug contact hole; and planarizing the conductive layer for a landing plug to form a landing plug, wherein the multi-layered hard mask layer includes a stacked structure of nitride film/oxide film/nitride film serving as a barrier layer during the etching process for a gate pattern.