Patent ID: 7302509

Claim:
A method for accessing cells in devices connected via a bus connection with a single data line carrying data signals and a single clock line carrying clock signals, wherein the devices connected to the bus are identified by device addresses, wherein a first device establishes a start condition to set up a bus connection, thereby becoming a master for the following communication, wherein the master selects a second device by its device address, the second device becoming a slave for the following communication, wherein the master selects the transmission mode read or write, and wherein the master establishes a stop condition terminating the bus connection after successful communication, the method comprising the master: transmitting a data mode signal via the single data line after addressing the slave, wherein the data mode signal includes information about the number of cell address bytes for composing the cell address inside the addressed slave device and the number of data bytes to be subsequently transmitted; transmitting via the single data line a cell address signal according to the data mode signal, wherein the cell address signal includes the bytes which form the cell address; and transmitting data to and/or receiving data from the slave according to the data mode signal.