Patent ID: 8330198

Claim:
A device for preventing current-leakage, located between a transistor and a capacitor of a memory cell, wherein the device for preventing current-leakage is a lateral silicon controlled rectifier and two terminals of the lateral silicon controlled rectifier are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor, comprising: a first structure having a first P-typed region and a first N-typed region, wherein the first P-typed region and the first N-typed region are connected with the slave terminal of the transistor; a first conducting layer connected with the slave terminal of the transistor, wherein the first structure is stacked on the first conducting layer, the first P-typed region and the first N-typed region contact the first conducting layer; a second structure stacked on the first structure, wherein the second structure has a second P-typed region and a second N-typed region, the second N-typed region contacts the first P-typed region, there is a gap between the second P-typed region and the first P-typed region, and the second P-typed region and the second N-typed region are connected with the electric pole of the capacitor; and a second conducting layer stacked on the second structure and contacting the second P-typed region and the second N-typed region, wherein the second conducting layer is connected with the electric pole of the capacitor.