Patent ID: 7478344

Claim:
A method in a data processing system, said method comprising: initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module; initializing a second variable to limit a time for satisfiability solver operations with respect to said initial design by a satisfiability solver module; initializing a third variable to limit a maximum number of rewrite iterations with respect to said initial design; increasing said first variable to limit said rewrite time for rewrite operations by said rewriting module, increasing said second variable and subsequently performing a non-time bounded satisfiability analysis; calling a timer to track said rewrite time; running a local logic rewriting operation on said initial design with said rewrite module; in response to determining that all targets for an initial design netlist are not solved, determining whether a rewrite time is expired; in response to determining that said rewrite time is not expired, running AND refactoring, wherein running said AND refactoring includes: selecting a first simplification mode for said initial design from a set of applicable simplification modes, wherein said first simplification mode is an AND/OR simplification mode; performing a simplification of said initial design according to said first simplification mode to generate a reduced design; determining whether a size of said reduced design is less than a size of said initial design; and in response to determining that said size of said reduced design is less than said size of said initial design, replacing said initial design with said reduced design; and in response to determining that said rewrite time is not expired, running XOR refactoring, wherein performing said XOR refactoring further comprises: selecting a first simplification mode for said initial design from a set of applicable simplification modes, wherein said first simplification mode is an XOR/XNOR simplification mode; performing a simplification of said initial design according to said first simplification mode to generate a reduced design containing a reduced number of XOR gates; determining whether a size of said reduced design is less than a size of said initial design; and in response to determining that said size of said reduced design is less than a said size of said initial design, replacing said initial design with said reduced design; determining one or more of: (a) whether said all targets for said initial design netlist are solved, (b) whether said rewrite time is expired, and (c) whether said variable to limit a maximum number of rewrite iterations is obtained.