Patent ID: 7169651

Claim:
A process for making a plurality of leadless semiconductor packages, comprising the steps of: providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement, a plurality of dambars between the units, and a first metal layer formed on the entire upper surface of the lead frame wherein each unit includes a die pad and a plurality of leads; attaching a plurality of chips onto the die pads of the lead frame, wherein each of the chips has a plurality of bonding pads on an active surface thereof; electrically coupling each lead of the lead frame to two different bonding pads of one of the chips; encapsulating the chips against the upper surface of the lead frame to form a molded product; selectively etching away a portion of each lead of the lead frame to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween; electroplating a second metal layer on the first connection pads, the second connection pads and the die pads exposed from the bottom of the molded product by using the first metal layer as an electrical path; removing the first metal layer located between the first connection pads and the second connection pads such that the first connection pads are electrically isolated from the second connection pads; and conducting a singulation step to obtain the leadless semiconductor packages.