Patent ID: 7101744

Claim:
A method for forming a self-aligned, dual silicon nitride liner for complementary metal oxide semiconductor (CMOS) devices, the method comprising: forming a first type nitride layer over a first polarity type device and a second polarity type device; forming a topographic layer over said first type nitride layer, including said first polarity type device and said second polarity type device; patterning and removing portions of said first type nitride layer and said topographic layer over said second polarity type device; forming a second type nitride layer over said second polarity type device, and over remaining portions of said topographic layer over said first polarity type device so as to define a vertical pillar of second type nitride material along a sidewall of said topographic layer, said second type nitride layer in contact with a sidewall of said first type nitride layer; removing said topographic layer; and removing said vertical pillar.