Patent ID: 8219864

Claim:
A circuit arrangement implemented in hardware, comprising: a functional circuit implemented in hardware with m data inputs and n data outputs for processing at least one m-dimensional binary data input to form an n-dimensional data output, wherein the functional circuit comprises at least one combinatorial circuit part; at least two registers implemented in hardware with a word length k which are coupled to at least some of the n data outputs of the functional circuit in order to store output values which are duplicated with respect to one another or are duplicated with bit-by-bit inversion with respect to one another, said output values being derived from the n-dimensional data output of the functional circuit; at least one corrector implemented in hardware with an input word length 2k and an output word length k, which is coupled to data outputs of the at least two registers and supplies a k-dimensional corrected data output (y[k](korr)=y 1 (korr), . . . , yk(korr)); and an error detection circuit implemented in hardware for detecting errors during operation of at least one of the aforementioned circuit elements: the functional circuit, the at least two registers and the corrector; wherein the following features are configured for the case where k=n: the functional circuit is a combinatorial circuit with an m-bit-wide data input and an n-bit-wide data output for forming the n-dimensional data output, and a duplicating circuit part is provided for producing from the n-dimensional data output two respectively n-bit-wide duplicate data outputs, wherein a first duplicate data output of the duplicating circuit part is passed to an n-dimensional data input of a first register and a second duplicate data output of the duplicating circuit part is passed to an n-bit-wide data input of a second register, and wherein an n-bit-wide data output of the first register and an n-bit-wide data output of the second register are passed in a positionally correct manner to a 2n-bit-wide data input of the corrector, which supplies an n-dimensional corrected data output; wherein the error detection circuit comprises a predictor, an L-bit-wide further register, a comparator and a generator, wherein L is the number of control positions of a code which is used, and in that at least one circuit configuration is formed from the following group of circuit configuration elements: the m-dimensional binary data input is passed to a data input of the predictor, an L-bit-wide data output of the predictor is connected to an L-bit-wide data input of the further register, an L-bit-wide data output of the further register is passed to a first L-bit-wide data input of the comparator, a data output of the generator is passed to a second L-bit-wide data input of the comparator, and a data input of the generator is connected to the n-dimensional corrected data output of the corrector.