Patent ID: 7605630

Claim:
A delay circuit for adjusting delay times of rising and falling edges of an input signal, comprising: a first delay line, having a first input terminal for receiving a first input signal and delaying the first input signal a first delay time to output a first delay output signal; a second delay line, having a second input terminal for receiving the first input signal and delaying the first input signal a second delay time to output a second delay output signal, wherein the first input signal is utilized as a control signal; a first logic circuit receiving the first delay output signal and outputting a first output signal according to the control signal; and a second logic circuit receiving the second delay output signal and outputting a second output signal according to the control signal; wherein the first logic circuit and the second logic circuit do not output the first output signal and the second output signal simultaneously, where if the first input signal is low voltage level, the first logic circuit is turned on to output the first output signal according to the control signal, and if the first input signal is high voltage level, the second logic circuit is turned on to output the second output signal according to the control signal.