Patent ID: 7714384

Claim:
A castellated-gate MOSFET device capable of fully depleted operation comprising: a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface, formed within a semiconductor wafer, said semiconductor wafer also having an upper portion with a top surface and a lower portion with a bottom surface; a source region, a drain region, and a channel-forming region disposed between said source and drain regions, all of which are formed in said semiconductor substrate region; trench isolation insulator islands surrounding said source and drain regions as well as said channel-forming region and having upper and lower surfaces; said channel-forming region comprising a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally said gate elements extending to a depth greater than lower surface of said shallow trench isolation islands along said device between said source and drain regions; a gate structure in the form of a plurality of spaced, castellated gate elements interposed longitudinally between and outside of said channel elements, and a top gate member interconnecting said gate elements at their upper vertical ends to cover said channel elements; a dielectric layer separating said conductive channel elements from said gate structure; a buried insulator structure having an upper portion with a top surface and a lower portion with a bottom surface; said top surface of said buried insulator structure spaced below said lower surfaces of said trench isolation insulator islands; and said bottom surface of said buried insulator structure being coincident with said bottom surface of said semiconductor wafer.