Patent ID: 7164595

Claim:
A memory cell, comprising: a first portion of the memory cell, including a first pass transistor and a first capacitor coupled in series and configured for coupling in series between a first digit line at a port of the first pass transistor and a cell plate conductor at a terminal end of the first capacitor, the first pass transistor configured to be controlled by a first wordline; a second portion of the memory cell, including a second pass transistor and a second capacitor coupled in series and configured for coupling in series between a second digit line at a port of the second pass transistor and the cell plate conductor at a terminal end of the second capacitor, the second pass transistor configured to be controlled by the first wordline, the second portion and the first portion symmetrically configured with respect to each other; and an interconnection formed on the cell plate conductor between the terminal end of the first capacitor and the terminal end of the second capacitor, the interconnection being electrically isolated from other portions of the cell plate conductor.