Patent ID: 7190078

Claim:
An interconnection structure of a microelectronic package comprising: a first conductive layer; a second conductive layer disposed at a distance with respect to the first conductive layer; a third conductive layer disposed at a distance with respect to the second conductive layer; a dielectric material comprising; a first dielectric material portion disposed between the first conductive layer and the second conductive layer; a second dielectric material portion disposed between the second conductive layer and the third conductive layer; and a pair of package vias comprising: a first package via comprising a first conductive material extending through a first via hole through the first dielectric material portion from the second conductive layer to the first conductive layer, the first package via defining a first interlocking section wider than the first via hole and extending into the first conductive layer and under the first dielectric material portion; and a second package via comprising a second conductive material extending through a second via hole through the second dielectric material portion from the third conductive layer to the second conductive layer, the second package via defining a second interlocking section wider than the second via hole and extending into the second conductive layer and under the second dielectric material portion.