Patent ID: 8569128

Claim:
A method for forming a semiconductor structure, comprising; forming first and second PMOS transistor elements and first and second NMOS transistor elements, wherein the first PMOS transistor element and the first NMOS transistor element establish a first CMOS transistor pair, and the second PMOS transistor element and the second NMOS transistor element establish a second CMOS transistor pair, by: forming a first threshold voltage setting region extending under a gate of the first and second PMOS transistor elements, the first threshold voltage region defining a depletion zone when a voltage to the transistor elements is applied; forming a second threshold voltage setting region extending under a gate of the first and second NMOS transistor elements, the second threshold voltage region defining a depletion zone when the voltage to the transistor elements is applied; forming a substantially undoped channel region, disposed above the threshold voltage setting regions and below the gates of each of the first and second PMOS and NMOS transistor elements; concurrently depositing a first gate metal only on the gate of the first PMOS transistor element of the first CMOS transistor pair and the gate of the second NMOS transistor element of the second CMOS transistor pair; and concurrently depositing a second gate metal only on the gate of the first NMOS transistor element of the first CMOS transistor pair and the gate of the second PMOS transistor element of the second CMOS transistor pair.