Patent ID: 8580665

Claim:
A method for controlling the concentration of dopant in doped conductive interconnects during fabrication of integrated circuit device on a semiconductor substrate, comprising: forming a dielectric layer over said substrate; patterning a plurality of contact trenches in said dielectric layer, the trenches having a top surface; depositing a barrier layer in said trenches; depositing a metal seed layer over said abarrier layer in said trenches; thereafter filling said trenches with metal including an overburden; using chemical mechanical planarization (CMP) to planarizing said overburden to approximately the top surface of said trenches; depositing a dopant material over said planarized overburden in the range of 2-20 nm in thickness; and diffusing substantially all of said dopant material into said metal to thereby achieve a doping concentration level in the doped metal in the range of about 0.1-1%; wherein said depositing a dopant material comprises depositing at least one of aluminum, manganese, palladium, gold, zirconium, magnesium, titanium, hafnium, vanadium, niobium, chromium, iron, cobalt, nickel, zinc, cadmium, silver, mercury, indium, gallium, thallium, boron, silicon, germanium, tin, lead, bismuth, phosphorus, and selenium.