Patent ID: 7206922

Claim:
A processing unit, comprising: a plurality of processor clusters, each processor cluster having an output to send a signal representing instruction requests, an instruction request responsive to a cache miss by a processing unit within the processor clusters; an instruction request arbiter, having an input coupled to the outputs of the plurality of processor clusters, the instruction request arbiter controlling access of the plurality of processor clusters to submit instruction requests by broadcasting a traffic mode to the plurality of processor clusters, the instruction request arbiter having a second output coupled to the inputs of the plurality of processor clusters and controlling access to instruction request submissions from the plurality of processor clusters by broadcasting a signal representing a high traffic mode responsive to an average number of instruction requests exceeding a limit, wherein during a high traffic mode, the plurality of processor clusters submit instruction requests during scheduled slots, the instruction request arbiter also detecting conflicts between the instruction requests; and an instruction memory, having an input coupled to a first output of the instruction request arbiter, the instruction memory sending a signal representing instruction data to the plurality of processor clusters responsive to receiving non-conflicting instruction requests from the instruction request arbiter.