Patent ID: 7116504

Claim:
An apparatus for removing dc offset from a digital signal, the apparatus comprising: a first detector responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector input; a circuit to produce an error signal, wherein the error signal is the difference between the second output and the sum of an uncorrected digital signal and a dc offset correction signal, wherein the uncorrected digital signal is delayed by a first amount, and wherein the dc offset correction signal is delayed by a second amount; a first dc offset correction feedback loop responsive to a first loop input, the first dc offset correction feedback loop further comprising a first loop filter; and a second dc offset correction feedback loop responsive to a second loop input and a third loop input, the second dc offset correction feedback loop further comprising a second loop filter; wherein the first loop input is the error signal, wherein the second loop input is the error signal, wherein the third loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, or the second output, wherein a dc offset correction signal is the sum of the output of the first dc offset correction feedback loop and at least a portion of the output of the second dc offset correction feedback loop, and wherein the dc offset correction signal is added to the digital signal to provide the corrected digital signal.