Patent ID: 8803542

Claim:
A method for verifying stitching accuracy of a stitched chip on a wafer, said method comprising: inserting a plurality of test structures pairs in a reticle layout, wherein said test structure pairs for evaluating stitching accuracy of a stitched chip in a X-direction include a set of J structures located on a first chip segment, each J structure having two conductive bars orthogonally connected by one conductive bar located at a boundary of said first chip segment, and a set of H structures located on a second chip segment, each H structure having two conductive bars orthogonally connected by one conductive bar located at various distances from a boundary of said second chip segment, wherein said test structure pairs for evaluating stitching accuracy of said stitched chip in a Y-direction include a first set of three conductive bars located on said first chip segment, each conductive bar being spaced a first distance from each other, a second set of three conductive bars located on said second chip segment, each conductive bar being spaced a second distance from each other, wherein said second distance is larger than said first distance; executing an exposure program to control a photolithography equipment having a stepper to perform multiple exposures of said reticle layout on a wafer to generate a stitched chip on said wafer; and performing electrical measurements on a set of stitched test structures produced using said test structures at actual stitch boundaries of said stitched chip to evaluate stitching accuracy of said stitched chip in said X-direction and said Y-direction.