Patent ID: 7285450

Claim:
A method of fabricating non-volatile memory, comprising the steps of: providing a substrate at least divided into a memory cell region and a peripheral circuit region; forming a plurality or first memory cells on the substrate in the memory cell region, wherein every pair of adjacent first memory cells has a gap; forming a second composite layer over the substrate in the memory cell region, wherein the second composite layer includes a second charge storage layer; forming a gate dielectric layer over the substrate in the peripheral circuit region; forming a conductive layer over the second composite layer and the gate dielectric layer to cover the first memory cells and fill up the gaps; forming a dielectric layer over the conductive layer; removing a portion of the dielectric layer in the peripheral circuit region and removing the dielectric layer and a portion of the conductive layer in the memory cell region to form a plurality of second gates that fills the gaps, wherein the second gates and the second composite layer form a plurality of second memory cells, and the second memory cells and the first memory cells form a first memory cell column; patterning the remaining dielectric layer and the conductive layer in the peripheral circuit region to form a plurality of gate structures in the peripheral circuit region; and forming a source/drain region in the substrate on the respective sides of the first memory cell column.