Patent ID: 7672157

Claim:
A memory integrated circuit comprising: a plurality of memory arrays in the memory integrated circuit, a memory array of the plurality of memory arrays being vertically layered with respect to other memory arrays of the plurality of memory arrays, the memory arrays of the plurality of memory arrays including: a plurality of word lines; and a plurality of bit lines, wherein intersections between the plurality of word lines and the plurality of bit lines include: a diode; and a memory state storage element, wherein the diode and the memory storage element are coupled in between a word line of the plurality of word lines and a bit line of the plurality of bit lines; and an isolation oxide between vertically adjacent memory arrays of the plurality of memory arrays, such that a first vertically adjacent memory array has the plurality of word lines on a first side of the isolation oxide, a second vertically adjacent memory array has the plurality of word lines on a second side of the isolation oxide, the first side and the second side being opposite sides of the isolation oxide.