Patent ID: 8745561

Claim:
A method for pessimism minimization in timing delay analysis for a pair of devices clocked according to a common clock root in a circuit design, the method comprising: generating a timing model for a circuit design having a clock root and a plurality of clocked devices respectively coupled thereto by a plurality of interconnection points and at least one intermediate circuit component, at least a first and second of said clocked devices being paired in actuation for launch and capture of a data signal therebetween, a first path being defined between said clock root and said first clocked device and a second path being defined between said clock root and said second clocked device; generating a lineage tag for at least one interconnection point determined to be a branching point, a branching point being defined by an interconnection point having a plurality of incoming or outgoing path segments, at least one of said lineage tags indicating a history of intervening branching points traversed by said first or second paths between said clock root and a corresponding branching point; determining at least one common path segment shared between said first and second paths based upon a comparison of at least one lineage tag from each of said first and second paths; and, using a processor to selectively set for an interconnection point of at least one of said first and second clocked devices a timing delay parameter compensated for said common path segments shared between said first and second paths, said timing delay parameter indicating a signal propagation delay, whereby common path delay pessimism is avoided for said paired clocked devices.