Patent ID: 7562318

Claim:
A reduced capacitance semiconductor test structure on a substrate to provide for the automatic dynamic stress and device characterization test of a semiconductor device for Negative Bias Temperature Instability comprising: a MOS dynamic stress test device; an input contact pad for a dynamic stress test first voltage; an inverter coupled to the input contact pad for controlling the phase relationship of said dynamic stress test first voltage; a first electronic switch device between said dynamic stress test first voltage and said MOS dynamic stress test device source element; a second electronic switch device between an inverter output and said MOS dynamic stress test device gate element; multiple contact pads for the application of second, third, fourth, fifth, and sixth voltages to the inverter, the first electronic switch, the second electronic switch, and the MOS dynamic stress test device; and the inverter including a PMOS and NMOS device employed in a CMOS inverter configuration with each device gate connected together to form the input and each device drain connected together to form the output, said PMOS device source connected to said second voltage, and said NMOS device source connected to said third voltage.