Patent ID: 7274060

Claim:
A memory cell array, comprising: a plurality of memory cells, each memory cell including a storage capacitor and an access transistor; a plurality of bit lines oriented in a first direction; a plurality of word lines oriented in a second direction, the second direction being perpendicular to the first direction; and a semiconductor substrate with a surface and a plurality of active area lines formed therein, a longer side of each active area line extending in the second direction; wherein access transistors of the memory cells are at least partially formed in the active area lines and electrically couple corresponding storage capacitors to corresponding bit lines, each access transistor including: a first source/drain region connected to an electrode of the storage capacitor, a second source/drain region adjacent to the substrate surface, a channel region connecting the first and second source/drain regions, the channel region disposed in the active area, and a gate electrode disposed along the channel region, the gate electrode controlling an electrical current flowing between the first and second source/drain regions, the gate electrode connected with one of the word lines, wherein each gate electrode includes a bottom side, each word line includes a bottom side, the bottom side of the gate electrodes being disposed beneath the bottom side of the word lines, and the word lines are disposed above the bit lines.