Patent ID: 7295486

Claim:
A memory, comprising P banks, P being integer, each bank comprising: X word lines arranged in parallel, the X word lines comprising an i-th word line, X, i being integers, i being smaller or equal to X; Y bit lines substantially perpendicular to the word lines, the Y bit lines comprising a j-th bit line, Y and j being integers, j being smaller or equal to Y; a bank select line; Y bank select MOS (Metal Oxide Semiconductor) transistors, comprising a j-th bank select MOS transistor, the j-th bank select MOS transistor being coupled to the j-th bit line and controlled by the bank select line; Y buried diffusion (BD) regions, comprising a j-th BD region, the j-th BD region being coupled to the j-th bank select MOS transistor; and X*Y memory cells in X rows and Y columns, the memory cells comprising a memory cell M (i, j) located in i-th row and j-th column, the memory cell M (i, j) having a gate(i, j), a first source/drain(i, j), and a second source/drain(i, j), the gate(i, j) being coupled to the i-th word line, the first source/drain(i, j) being coupled to the j-th BD region, the second source/drain(i, j) being coupled to the first source/drain(i, j+1); wherein when the memory cell M (i, j) is processed, the i-th word line is enabled, the first source/drain(i, j) is coupled to the j-th bit line via the j-th BD region and the j-th bank select MOS transistor, in order to compensate the voltage drop resulting from the resistance of the j-th bit line and the j-th BD region, at least one of the voltage applied to the i-th word line and the voltage applied to the j-th bit line is adjusted according to the position of the bank which the memory cell M (i, j) belongs to.