Patent ID: 7268031

Claim:
A method for fabricating a memory cell transistor, the method comprising: creating a plurality of source/drain regions in a column direction by doping portions of a substrate; creating a low dielectric constant oxide isolation area in the substrate between adjacent source/drain regions in a row direction; forming a tunnel insulator over the substrate and between adjacent oxide isolation areas, the tunnel insulator having a dielectric constant that is higher than silicon dioxide; forming a metal floating gate over the tunnel insulator; forming a metal oxide inter-gate insulator over the floating gate such that forming the inter-gate insulator comprises forming one of the following structures: Ta 2 O 5 —Ta—Ta 2 O 5 , TiO 2 —Ti—TiO 2 , ZrO 2 —Zr—ZrO 2 , or Nb 2 O 5 —Zr—Nb 2 O 5 wherein the metal oxide layers are formed by low temperature oxidation; and forming a control gate over the inter-gate insulator.