Patent ID: 8216899

Claim:
A method of manufacturing a flash memory device, comprising: providing a semiconductor substrate, comprising selection transistor regions, a memory cell region defined between the selection transistor regions, and a peripheral region; stacking a gate insulating layer and a conductive layer over the semiconductor substrate; forming trenches by etching the conductive layer, the gate insulating layer, and the semiconductor substrate, thereby forming first conductive patterns over the selection transistor regions, second conductive patterns over the memory cell region, and third conductive patterns over the peripheral region; forming first, second, and third isolation layers to a same height, wherein the first isolation layers are formed in the trenches of the selection transistor regions, the second isolation layers are formed in the trenches of the memory cell region, and the third isolation layers are formed in the trenches of the peripheral region; forming a first photoresist pattern over the first and third isolation layers, wherein the second isolation layers are exposed; lowering the height of the second isolation layers by performing an etch process using the first photoresist pattern as an etch barrier; and removing the first photoresist pattern.