Patent ID: 7873843

Claim:
A method for reducing power consumption in a computer memory system including a memory bus, an array of memory devices, a driver subsystem, and a termination voltage source, wherein the memory bus includes a multitude of bus lines connected to the memory devices, the driving subsystem is connected to the bus lines for charging the bus lines to high or low states, and the termination voltage source is connected to the bus lines through termination resistors, and wherein the memory bus has defined periods of inactivity, the method comprising the steps of: providing a register for storing a series of predetermined register bits for setting the bus lines to predetermined states during said periods of inactivity, each of said predetermined register bits being associated with one of the bus lines, and identifying one of said high or low states for said associated bus line; and during said periods of inactivity of the memory bus, driving at least some of the bus lines to high or low states in accordance with the predetermined register bits to reduce the drive current supplied by the termination voltage source during said periods of inactivity.