Patent ID: 8504868

Claim:
A computer system comprising: a processor; a submodule connected to the processor; an external access monitor configured to monitor a data transfer between the processor and the submodule; and a synchronization/desynchronization controller configured to synchronize or desynchronize a clock of the processor with respect to a clock of the submodule, depending on a result of the monitoring by the external access monitor, wherein the external access monitor includes an access measurer configured to measure the number of accesses per predetermined period between the processor and the submodule, and a comparator configured to compare a result of the measurement by the access measurer with a predetermined count value, and the synchronization/desynchronization controller, when a result of the comparison with the predetermined count value by the comparator indicates that the number of accesses per predetermined period is the predetermined count value or more, synchronizes the clock of the processor to the clock of the submodule, and when the result of the comparison with the predetermined count value by the comparator indicates that the number of accesses per predetermined period is less than the predetermined count value, desynchronizes the clock of the processor with respect to the clock of the submodule.