Patent ID: 7417837

Claim:
An integrated circuit comprising: a first device in a first power domain; a second device in a second power domain; and a buffer module coupled between the first device and the second device for allowing a signal to pass across between the first and second devices during a normal operation, and for increasing an impedance between the first and second devices during an electrostatic discharge (ESD) event, thereby reducing a possibility of having an ESD current flow from the first device to the second device, the buffer module comprising: at least one CMOS logic buffer device having a first PMOS transistor and a first NMOS transistor serially coupled to one another; one or more header PMOS transistors serially coupled between a power supply voltage and the first PMOS transistor for increasing a breakdown voltage of the first PMOS transistor during the ESD event, wherein a gate of the first PMOS transistor is not coupled to any gate of the header PMOS transistors regardless of an output voltage level of the CMOS logic buffer device, and gates of the one or more header PMOS transistors are coupled to a logic-low signal to increase an ESD trigger-on voltage of the buffer module.