Patent ID: 8588022

Claim:
An apparatus, comprising: a plurality of memory sections; and a plurality of memory section control circuits, wherein each memory section control circuit is coupled to a respective one of the plurality of memory sections, wherein each memory section control circuit comprises a plurality of access line drivers, and wherein each of the access line drivers comprises a plurality of transistors having commonly coupled gates, wherein, during an operation of the apparatus in which a memory section of the plurality of memory sections is active and a memory section of the plurality of memory sections is inactive, a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to the active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to the inactive memory section control circuit, wherein the first voltage is greater than the second voltage wherein each of the memory section control circuits comprises a plurality of global drivers configured to receive either the first voltage or the second voltage.