Patent ID: 8199589

Claim:
A shift register capable of operating in a power-saving mode or an active mode, and comprising: a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock; and a drive operation controller comprising: a first logic gate configured to receive and logically combine selected outputs from selected ones of the plurality of flip-flops to generate a gate output signal; a drive operation controller flip-flop configured to receive the gate output signal and retime the gate output signal in response to a first clock applied to a clock terminal of a first flip-flop in the plurality of flip-flops to generate a clock enable signal; an inverter configured to receive the clock enable signal and generate an inverted clock enable signal; and a second logic gate configured to receive and logically combine the first clock and the inverted clock enable signal to generate a second clock, wherein the second clock signal is applied to a clock terminal of at least one later stage flip-flop following the first flip-flop in the plurality of flip-flops.