Patent ID: 6880026

Claim:
Apparatus for implementing chip-to-chip interconnect bus initialization, said chip-to-chip interconnect bus comprising a first unidirectional bus and a second unidirectional bus for full duplex communications between two chips, said initialization apparatus comprising: a first receive initialization sequencer connected to a first end of said first unidirectional bus; a first transmit initialization sequencer coupled to said first receive initialization sequencer connected to said first end of said second unidirectional bus; a second receive initialization sequencer connected to a second end of said second unidirectional bus; a second transmit initialization sequencer coupled to said second receive initialization sequencer connected to said second end of said first unidirectional bus; each said transmit initialization sequencer including a synchronization state for transmitting predefined SYNC symbols on said connected unidirectional bus; and an idle state for transmitting IDLE symbols on said connected unidirectional bus; each said receive initialization sequencer including a synchronization state for detecting a defined number of valid SYNC or IDLE symbols; and a run state responsive to detecting said defined number of valid SYNC or IDLE symbols for triggering said coupled transmit initialization sequencer for transmitting IDLE symbols on said connected unidirectional bus.