Patent ID: 8482312

Claim:
A logic circuit comprising: a first logic element (“LE”) including a first lookup table (“LUT”), wherein said first LUT is operable to produce a carry from a first set of bits of three numbers; and a second LE including: a second LUT, wherein said second LUT is operable to produce a sum from a second set of bits of said three numbers, and an adder coupled to receive output of said first LUT directly from said first LE, and coupled to said second LUT, wherein said adder is operable to add said carry and said sum; wherein: said first LE has a first plurality of inputs for bits of said three numbers; said second LE has a second plurality of inputs for other bits of said three numbers; and said logic circuit further comprises a set of connections operable to programmably interconnect selected inputs in said first plurality of inputs to selected inputs in said second plurality of inputs, whereby when said set of connections is programmed to interconnect said selected inputs in said first plurality of inputs to said selected inputs in said second plurality of inputs, said logic circuit is operable to add only two numbers.