Patent ID: 8560756

Claim:
A semiconductor memory, comprising: a plurality of non-volatile memory banks, wherein each non-volatile memory bank comprises an array of storage cells, the plurality of non-volatile memory banks including: a first memory bank associated with a dedicated data bus and a set of dedicated buffers, wherein the first memory bank operates as a NOR-type memory bank configured to provide random access reading of data from the first memory bank to facilitate storage of programming code and execution of the programming code, and plurality of remaining memory banks comprising memory banks of the plurality of memory banks absent at least the first memory bank, the plurality of remaining memory banks being associated, collectively, with a shared data bus and a set of shared buffers, wherein the plurality of remaining memory banks operate as NAND-type memory banks configured to facilitate performance of data write operations and mass storage of data; and a shared decoder configured to be associated with the plurality of non-volatile memory banks, decode respective addresses associated the plurality of non-volatile memory banks, and be located in closer proximity, on a semiconductor chip of the semiconductor memory, to the first memory bank, as compared to respective proximities of respective remaining memory banks of the plurality of remaining memory banks, to facilitate the random access reading of the data from the first memory bank, wherein the dedicated data bus associated with the first memory bank is configured to be isolated from the shared data bus such that the dedicated data bus is not directly and not indirectly communicatively connected to the shared data bus.