Patent ID: 7697656

Claim:
A method of controlling a shift register in which a plurality of transfer unit circuits, each having a storage unit and a writing unit, are connected in series, the storage unit having a hold gate and storing a logical level of a pulse when the hold gate is in an active state, the writing unit having a writing gate and writing a pulse in the storage unit when the writing gate is in an active state, the method comprising: performing control such that the writing gate is shifted from an active state to a non-active state and then the hold gate is shifted from a non-active state to an active state; performing control such that the hold gate is shifted from the active state to the non-active state and then the writing gate is shifted from the non-active state to the active state; and shifting states of the writing gate and the hold gate in a transfer unit circuit of the current stage after detecting that the writing gate has entered a non-active state in a transfer unit circuit of the next stage provided in a transfer direction of the pulse.