Patent ID: 8045399

Claim:
A data output circuit in a semiconductor memory apparatus comprising: a pre-driving unit configured to produce a pull-up signal and a pull-down signal in response to input data; a pull-up driving unit configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level of the first node transitions; a pull-down driving unit configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level of the second node transitions; and a pad coupled to the first and second nodes to generate output data, wherein the pull-up driving unit includes a first main driver configured to pull-up drive the first node in response to the pull-up signal and a first sub driver configured to pull-up drive the first node when the voltage level of the first node transitions, the first sub driver includes a first switching unit configured to produce a first sub driving signal in response to the pull-up signal and a first driver configured to pull-up drive the first node in response to the first sub driving signal, and the first switching unit includes a first tri-state inverter which is configured to produce the first sub driving signal using an inverted signal of the voltage level on the first node.