Patent ID: 7725847

Claim:
A design support apparatus for supporting wiring design for bond wires that connect a semiconductor chip and an interposer, the design support apparatus comprising: an input control unit receiving input data including dimensions of a semiconductor chip and an interposer, and bond wire coordinate information containing arrangement positions of bond wires for connecting the semiconductor chip to the interposer; a creating unit that creates simulated design data that simulates, based on the input data, an occurrence of deviation in an arrangement position of the semiconductor chip on the interposer and an occurrence of deviation in bond wire connection terminal positions of the interposer based on the arrangement positions of the bond wires contained in the input data and the simulated deviation in the arrangement position of the semiconductor chip on the interposer, wherein the creating unit creates the simulated design data prior to arrangement of the semiconductor chip on the interposer; and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the deviation in the arrangement position of the semiconductor chip on the interposer and the deviation in the bond wire connection terminal positions of the interposer, and outputs analysis results that are used to design a semiconductor package based on the input data and the manufacturing deficiencies.