Patent ID: 7471537

Claim:
A content addressable memory (CAM) array, comprising: a plurality of rows of active CAM cells electrically coupled to a corresponding plurality of active match lines; a row of dummy cells configured to generate an always-match condition on a dummy match line when said row of dummy cells is undergoing a search operation; a match line pull-up circuit electrically coupled to the plurality of active match lines and the dummy match line and responsive to a first control signal that sets a pull-up strength of said match line pull-up circuit when the CAM array is undergoing the search operation, said match line pull-up circuit responsive to a clock signal having an active phase that sets a duration of a pull-up time interval when the CAM array is undergoing the search operation; and a sense amplifier electrically coupled to the plurality of active match lines and the dummy match line, said sense amplifier comprising a control circuit configured to adjust the first control signal to a value that causes the dummy match line to be sufficiently charged to a match level voltage during the pull-up time interval, in response to evaluating a first voltage on the dummy match line relative to a reference voltage.