Patent ID: 8487366

Claim:
A device with thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structure, the device comprising: a substrate; a dielectric layer on the substrate, the dielectric layer being associated with a first surface; one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions including an N + polysilicon layer, a diffusion barrier layer, and a first conductive layer, the N + polysilicon layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the first conductive layer, the N + polysilicon layer having a second surface substantially co-planar with the first surface; a P − polysilicon layer overlying the first surface and the second surface; an oxide-nitride-oxide (ONO) layer overlying the P − polysilicon layer; a second conductive layer overlying the ONO layer; and at least one control gate made from patterning the second conductive layer.