Patent ID: 8054256

Claim:
A driving circuit for generating a data voltage, comprising: a first decoder for receiving a first bit set of a digital data signal and outputting a first decoding signal; a first selector for receiving a third bit set of the digital data signal and the first decoding signal, the first selector outputting a first selection signal and a first sub selection signal; a switch unit for receiving the first selection signal and the first sub selection signal, the switch unit receiving a first reference voltage and a second reference voltage, magnitude of the second reference being smaller than magnitude of the first reference voltage, the switch unit outputting a first switch output voltage and a second switch output voltage, each of magnitude of the first switch output voltage and magnitude of the second switch output voltage depending on magnitude of the first selection signal; a second decoder for receiving a second bit set of the digital data signal and outputting a second decoding signal; a second selector for receiving a fourth bit set of the digital data signal and the second decoding signal, the second selector outputting a second selection signal and a second sub selection signal; a first voltage divider for receiving the first switch output voltage and the second switch output voltage, the first voltage divider receiving the second selection signal and the second sub selection signal, the first voltage divider outputting a first output voltage, magnitude of the first output voltage depending on magnitude of the second selection signal; and a second voltage divider including: a first divider unit for receiving the first switch output voltage and the second switch output voltage, the first divider unit receiving the second selection signal, the first divider unit outputting a second output voltage, magnitude of the second output voltage depending on magnitude of the second selection signal; and a second divider unit for receiving the first switch output voltage and the second switch output voltage, the second divider unit receiving the second sub selection signal, the second divider unit outputting a third output voltage, magnitude of the third output voltage depending on magnitude of the second sub selection signal.