Patent ID: 8669643

Claim:
A wiring board comprising: a silicon substrate including first and second through holes each communicating with a first surface and a second surface of the silicon substrate; an insulating film that covers the first surface, the second surface, and wall surfaces of the first and second through holes; a capacitor including a capacitor part mounted on the insulating film on the first surface, wherein the capacitor part includes a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer; a multilayer structure covering each of the wall surfaces of the first and second through holes, wherein the multilayer structure includes the insulating film on each of the wall surfaces of the first and second through holes, a first metal layer on the insulating film, wherein the first metal layer is formed from the same material as the first electrode, a second dielectric layer on the first metal layer, wherein the second dielectric layer is formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer, wherein the second metal layer is formed from the same material as the second electrode, wherein the first metal layer, the second dielectric layer and the second metal layer of the multilayer structure are spatially separated from the capacitor; first and second penetration electrodes formed in the first and second through holes each covered by the multilayer structure; a first insulating layer formed over the insulating film on the first surface of the silicon substrate to cover the capacitor; a second insulating layer laminated on a lower surface of the insulating film, which covers the second surface of the silicon substrate; a first wiring layer laminated on the first insulating layer and electrically connecting the first electrode to the first penetration electrode; a second wiring layer laminated on the first insulating layer and electrically connecting the second electrode to the second penetration electrode; a third wiring layer laminated on a lower surface of the second insulating layer and connected to a lower surface of the first penetration electrode; and a fourth wiring layer laminated on the lower surface of the second insulating layer and connected to a lower surface of the second penetration electrode; wherein upper surfaces of the first and second penetration electrodes are flush with an upper surface of the insulating film, which covers the first surface of the silicon substrate, an upper surface of the first metal layer, an upper surface of the second dielectric layer and an upper surface of the second metal layer, and wherein the lower surfaces of the first and second penetration electrodes are flush with the lower surface of the insulating film, which covers the second surface of the silicon substrate, a lower surface of the first metal layer, a lower surface of the second dielectric layer, and a lower surface of the second metal layer.