Patent ID: 7943498

Claim:
A method of forming a micro pattern in a semiconductor device, the method comprising: forming an target layer, a hard mask layer and first sacrificial patterns over a semiconductor substrate on which a cell gate region, a selective transistor region and a periphery circuit region are defined; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; removing the insulating layer and the second sacrificial layer formed in the selective transistor region and the periphery circuit region; performing a first etch process so as to allow the second sacrificial layer formed in the cell gate region to remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns in the cell gate region; etching the hard mask layer using a second etch process utilizing the first and second sacrificial patterns as the etch mask to form a hard mask pattern; and etching the target layer using a third etch process utilizing the hard mask pattern as the etch mask.