Patent ID: 7716265

Claim:
A data transformation apparatus that receives four items of vector data X 0 , Xl, X 2 , and X 3 expressed in terms of integers and obtains transformed data expressed in terms of integers, the data transformation apparatus including a circuit comprising: a register that receives and holds the vector data X 0 , Xl, X 2 , and X 3 ; a first computing unit performing an operation D 0 =X 0 +aX 1 +aX 2 +a 2 X 3 ; a second computing unit performing an operation D 1 =aX 0 −X 1 +a 2 X 2 −aX 3 ; a third computing unit performing an operation D 2 =aX 0 +a 2 X 1 −X 2 −aX 3 ; a fourth computing unit performing an operation D 3 =a 2 X 0 −aX 1 −aX 2 +X 3 wherein the coefficient “a” is an odd number larger than 1, wherein the vector data X 0 , X 1 , X 2 , and X 3 held by the register are provided to the first to fourth computing units; a corrective computing unit adding integer data smaller than half a divisor {1+a 2 } to an odd number of the data D 0 , D 1 , D 2 , and D 3 obtained by the first to fourth computing units and adding a value equal to half the divisor {1+a 2 } to the rest of the data D 0 , D 1 , D 2 , and D 3 , and thereby calculating correction data D 0 ′, D 1 ′, D 2 ′, and D 3 ′ to be divided; and a divider dividing the correction data D 0 ′, D 1 ′, D 2 ′, and D 3 ′ obtained by the corrective computing unit by the divisor {1+a 2 }, rounding results of division in such a way that resulting integers will be smaller than the results of division, and outputting the resulting integers as approximate transformed data of a matrix operation: 1 1 + a 2 ⁢ ( 1 a a a 2 a - 1 a 2 - a a a 2 - 1 - a a 2 - a - a 1 ) ⁢ ( X ⁢ ⁢ 0 X ⁢ ⁢ 1 X ⁢ ⁢ 2 X ⁢ ⁢ 3 ) .