Patent ID: 7924912

Claim:
A method of performing decision feedback equalization (DFE) of a currently received data bit, comprising: coupling input data bits having the currently received data bit to a summing circuit; propagating a first portion of the input data bits through a first plurality of latches, wherein propagating the first portion of the input data bits comprises clocking the first plurality of latches with first and second clock signals; propagating a second portion of the input data bits through a second plurality of latches, wherein propagating the second portion of the input data bits comprises clocking the second plurality of latches with the first and second clock signals; resetting a first group of the first and second plurality of latches to a zero state during a time period; activating a second group of the first and second plurality of latches during the time period, wherein a portion of the activated latches are adapted to detect multiple levels of the input data bits by comparison to a programmable threshold; combining the outputs of the activated latches during the time period; summing the currently received input data bit with the combined outputs during the time period to equalize the currently received input data bit; and generating an output data bit at an output of the summing circuit during the time period, the summing circuit being coupled to the first group of the first and second plurality of latches and the second group of the first and second plurality of latches.