Patent ID: 8301850

Claim:
A memory system comprising: a first memory chip comprising a first temporary memory and a first block; a second memory chip comprising a second temporary memory and a second block; and a memory controller that controls writing data to the first and second memory chips, wherein the first and second memory chips are each a multi-level flash memory that stores n (n is a natural number of at least 2) bits in one memory cell, the first and second blocks each comprise physical pages and the writing is executed to each physical page from a lowermost physical page to an uppermost physical page, physical pages other than the lowermost physical page and the uppermost physical page are provided as a repetition of first units, each of the first units comprises pages having a different write times, and the memory controller writes data by an interleave operation in order of the first unit by the first temporary memory and the lowermost physical page in the first block, the first unit by the second temporary memory and the lowermost physical page in the second block, the first unit in the first block, and the first unit in the second block.