Patent ID: 7595675

Claim:
A method of determining the duty cycle of a digital signal, the method comprising: operating in a calibration mode, by a duty cycle measurement (DCM) circuit, to store in a data store a plurality of voltage values and corresponding duty cycle values, each voltage value being dependent on a respective duty cycle value; operating in a test mode, by the duty cycle measurement (DCM) circuit, to determine the duty cycle of a test clock signal exhibiting an unknown duty cycle, the operating in a test mode step including: receiving, by charger circuitry in the DCM circuit, the test clock signal exhibiting an unknown duty cycle; charging, by the charger circuitry, a capacitor in the DCM circuit to a test voltage value that depends on the duty cycle of the test clock signal; and accessing, by a control mechanism, the data store to determine a duty cycle which corresponds to the test voltage value.