Patent ID: 7849293

Claim:
In a computer system, a method of speculatively generating a tagged-pointer for a dependent instruction sequence dispatched from an instruction fetch unit, comprising: decomposing a load-tagged pointer (ltptr) instruction received from an instruction fetch buffer into three internal operations (iop); a first iop (LQ2ND) loading a first word from a first effective address (EA+8) of a first memory segment into a first (target) register associated with the ltptr instruction; a second iop (LQ1ST) loading a second word from a second effective address (EA) of the first memory segment into a second register and loading a tag bit associated with the second effective address into a first bit location of a third register; and a third iop (LT_DETEXC) evaluating the contents of the second register and the first bit location of the third register and signaling an exception for a null pointer.