Patent ID: 8890787

Claim:
A liquid crystal display (LCD) apparatus comprising: an LCD panel having a plurality of pixel units, each of which includes a pixel capacitor, and a thin-film transistor (TFT) having a source terminal disposed to receive a data voltage, a gate terminal disposed to receive a gate voltage, and a drain terminal connected electrically to ground via said pixel capacitor; and a panel driving device including a timing control circuit operable for generating a gate control signal and a latch pulse signal, a gate driving circuit connected electrically to said timing control circuit for receiving the gate control signal therefrom, operable to generate a plurality of the gate voltages according to the gate control signal received by said gate driving circuit, and further connected electrically to said LCD panel for providing each of the gate voltages to said gate terminal of said TFT of a respective one of said pixel units, and a source driving circuit including a plurality of data voltage generating units, each of which includes an operational amplifier including a differential amplifier stage that is disposed to receive a bias current and an input voltage, and that is operable to generate an output voltage according to the bias current and the input voltage received by said differential amplifier stage, the output voltage generated by said differential amplifier stage of said operational amplifier of each of said data voltage generating units having a magnitude that corresponds to the input voltage received by said differential amplifier stage, and a slew rate that corresponds to a magnitude of the bias current, the data voltage received by said TFT of each of said pixel units of said LCD panel corresponding to the output voltage generated by said differential amplifier stage of said operational amplifier of a corresponding one of said data voltage generating units, and a current source that is controllable to generate the bias current and that is connected electrically to said differential amplifier stage for providing the bias current thereto, and a bias voltage generating unit connected electrically to said timing control circuit for receiving the latch pulse signal therefrom, and to said operational amplifier of each of said data voltage generating units in a current mirror configuration for generating an input bias current and controlling said current source of said operational amplifier to generate the bias current according to the latch pulse signal received by said bias voltage generating unit; wherein the slew rate of the output voltage of said differential amplifier stage of said operational amplifier of each of said data voltage generating units is higher when the input bias current is at one of high and low logic states than when the input bias current is at the other of the high and low logic states.