Patent ID: 7759241

Claim:
A method for making an electronic structure with a plurality of interconnects, comprising: forming a first dielectric layer above a substrate; forming a second dielectric layer above said first dielectric layer; forming a series of trenches in said second dielectric layer to expose a portion of said first dielectric layer; depositing a barrier layer that partially fills said series of trenches, wherein said barrier layer is adjacent to the sidewalls and above the bottoms of said series of trenches; depositing a seed layer above said barrier layer, wherein said seed layer is comprised of a metal species and a Group II element; forming a metal layer above said seed layer, wherein said metal layer completely fills the remaining portions of said series of trenches; removing said second dielectric layer to provide a series of free-standing metal interconnects; and forming a third dielectric layer above the top surfaces of said series of interconnects, wherein the regions between said first dielectric layer, said second dielectric layer and said series of metal interconnects defines a series of gaps.