Patent ID: 7360194

Claim:
A layout design apparatus comprising: a frame input unit that receives an input of a frame having a buffer tree that is clock-skew-adjusted embedded, the buffer tree including a root buffer serving as a start point and a plurality of branching buffers; a netlist input unit that receives an input of a netlist concerning an input element for inputting a clock signal and an element to which the clock signal is supplied; a placing unit that places the element and the input element in a placement area at an extremity of a buffer tree of the frame input by the frame input unit and on the frame, respectively, based on the netlist input by the netlist input unit; a determining unit that determines a wiring route from the root buffer to the element in the buffer tree where the element is placed by the placing unit; and a generating unit that generates a clock tree that starts at the input element and terminates at the elements placed in the placement area at the extremity of the buffer tree, based on the input element placed by the placing unit and the buffer tree having the wiring route determined by the determining unit.