Patent ID: 8199590

Claim:
A non-volatile memory, comprising: a plurality of multiple time programmable non-volatile memory elements, each respective multiple time programmable non-volatile memory element including: a capacitor; an access transistor electrically coupled to the capacitor at a connection node; and a plurality of one time programmable non-volatile memory cells corresponding in number to a number of times the respective multiple time programmable non-volatile memory element can be programmed to have a logic state that is either one of a first logic state and a second logic state that is logically opposite the first logic state, each of the plurality of one time programmable non-volatile memory cells being electrically coupled in parallel with one another to the connection node and including a select transistor that is electrically coupled to an antifuse element, the antifuse element being configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in the logic state of the respective multiple time programmable non-volatile memory element.