Patent ID: 8623714

Claim:
A method of forming a device comprising: forming a gate structure on a substrate, wherein the gate structure includes a spacer on a sidewall of at least a gate conductor of the gate structure; forming a source region and a drain region in the substrate; forming a metal containing layer on at least an upper surface of the gate conductor of the gate structure, the spacer, and an upper surface of one of the source region and the drain region; forming a dielectric layer over a first portion of the metal containing layer, wherein a second portion of the metal containing layer extending from at least a portion of the upper surface of the gate conductor to at least a portion of the one of the source region and the drain region is exposed; forming a semiconductor containing layer on the second portion of the metal layer and the dielectric layer; alloying the semiconductor containing layer and the second portion of the metal to provide a metal semiconductor alloy extending from said at least the portion of the upper surface of the gate conductor to said at least the portion of the one of the source region and the drain region, wherein the metal semiconductor alloy extends over an outer sidewall of the spacer; and forming an interlevel dielectric having an interconnect present in a via to at least a portion of the metal semiconductor alloy.