Patent ID: 8445974

Claim:
A semiconductor structure comprising: a semiconductor substrate including a device channel located between a source region and a drain region; at least one gate stack located atop the device channel, said at least one gate stack comprising, from bottom to top, a high k gate dielectric having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a sloped threshold voltage adjusting material layer located on said planar upper surface of the high k gate dielectric, and a gate conductor located atop an upper surface of the sloped threshold voltage adjusting material layer, wherein said sloped threshold voltage adjusting material layer provides different threshold voltage adjustment to said at least one gate stack; and a dielectric material layer located on each side of the at least one gate stack, said dielectric material layer is in direct physical contact with a sidewall of the at least one gate stack and extends across the entirety of the source region and the drain region, said dielectric material having an uppermost surface that is coplanar with an uppermost surface of said at least one gate stack.