Patent ID: 6936533

Claim:
A method of fabricating a semiconductor device having a low dielectric interlayer insulation layer, the method comprising: installing a semiconductor substrate in a chamber; introducing a layer formation source gas into the chamber, the layer formation source gas being selected to provide atoms used in forming a silicon oxycarbide layer on the substrate, the layer formation source gas comprising at least one of: (i) at least one of N 2 O and O 2 for supplying oxygen, (ii) a gas containing a methyl silane group selected from the group consisting of a gas containing a monomethyl silane group, a gas containing a dimethyl silane group, a gas containing a trimethyl silane group, and a gas containing tetramethyl silane, and (iii) another organic silicon gas; introducing a first plasma source gas into the chamber; performing plasma-enhanced chemical vapor deposition (PECVD) on the substrate in the chamber while the layer formation source gas and the first plasma source gas are being introduced into the chamber at a temperature of about 300 to 400 degrees C., the PECVD resulting in completely forming a silicon oxycarbide layer as the low dielectric interlayer insulation layer on the substrate; introducing a second plasma source gas into the chamber without the layer formation source gas at a temperature of about 250 to 400 degrees C., the second plasma source gas being at least one gas selected from the group consisting of He, H 2 , N 2 O, NH 3 , N 2 , O 2 and Ar; using the second plasma source gas, treating the completely formed silicon oxycarbide layer with plasma; and stacking photoresist on the plasma-treated oxycarbide layer and patterning the resultant structure.