Patent ID: 8039900

Claim:
A stacked semiconductor device comprising: a semiconductor substrate; a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, wherein the insulation layer patterns are vertically stacked on the semiconductor substrate and the opening is a single void structure within the multi-layered insulation layer that exposes an upper face of the semiconductor substrate; an active layer pattern on each of the insulation layer patterns, wherein a side portion of the active layer pattern is exposed by the opening; a first plug on the upper face of the semiconductor substrate to partially fill the opening, the first plug including single crystalline silicon-germanium; a second plug partially filling the opening on an upper face of the first plug, wherein the second plug has substantially the same interface as that of the first plug and includes single crystalline silicon, wherein the first and second plugs include different materials from each other; and a pad making direct contact with the first plug through the second plug, the pad sufficiently filling up the opening and including at least one of metal and metal nitride.