Patent ID: 7208779

Claim:
A semiconductor device comprising: a substrate having an insulating layer and an active layer provided on the insulating layer; a first element region provided in the active layer; an element-isolating region provided in the active layer, surrounding the first element region and reaching the insulating layer; a P-type semiconductor region provided in the first element region and reaching the insulating layer; first and second N-type semiconductor regions provided in end parts of the P-type semiconductor region, respectively, spaced apart in a first direction, provided in the first element region, and reaching the insulating layer; at least one N-type MOS transistor provided in the P-type semiconductor region and having a first gate electrode provided on the P-type semiconductor region, a direction of a channel length of the N-type MOS transistor substantially corresponding to the first direction; at least one first P-type MOS transistor provided in the first N-type semiconductor region and having a second gate electrode provided on the first N-type semiconductor region, a direction of a channel length of the first P-type MOS transistor substantially corresponding to the first direction; and at least one second P-type MOS transistor provided in the second N-type semiconductor region and having a third gate electrode provided on the second N-type semiconductor region, a direction of a channel length of the second P-type MOS transistor substantially corresponding to the first direction, wherein the element-isolating region is not provided between the P-type semiconductor region and the first N-type semiconductor region, and between the P-type semiconductor region and the second N-type semiconductor region.