Patent ID: 8364937

Claim:
A method, comprising: providing a data processor having an instruction pipeline, wherein the instruction pipeline has a plurality of instruction pipeline stages, and wherein the plurality of instruction pipeline stages comprise a first instruction pipeline stage and a second instruction pipeline stage; providing a load instruction to the instruction pipeline; providing a data-dependent instruction to the instruction pipeline; executing the data-dependent instruction in the first instruction pipeline stage if a most recently executed instruction was the load instruction and if the most recently executed instruction was for aligned memory access; executing the data-dependent instruction in the second instruction pipeline stage if the most recently executed instruction was the load instruction and if the most recently executed instruction was for misaligned memory access and if a first mode is selected; and executing the data-dependent instruction in the first instruction pipeline stage if the most recently executed instruction was the load instruction and if the most recently executed instruction was for misaligned memory access and if a second mode is selected.