Patent ID: 8551886

Claim:
A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having a substantially planar upper surface; etching the substrate to form: a first set of features that are spaced apart by first etched areas in a first region of the substrate; and a second set of features that are spaced apart by second etched areas in a second region of the substrate, the first set of features being spaced more densely than the second set of features; forming a protection layer over the first and second sets of features; forming an isolation layer over the substrate including within the first and second etched areas and over the protection layer, the isolation layer having a first thickness overlying a top plane of the protection layer in the first region and a second thickness overlying the top plane of the protection layer in the second region, and the first thickness being larger than the second thickness; performing a selective anisotropic etch followed by a global isotropic etch of the isolation layer, wherein a pattern of the anisotropic etch selectively removes portions of the isolation layer in the first region without removing portions of the isolation layer in the second region, in order to achieve via the isotropic etch a substantially uniform density of a remainder of the isolation layer overlying the top plane of the protection layer in the first and second regions; and following the etches, performing a planarization to remove the remainder of the isolation layer down to the top plane of the protection layer.