Patent ID: 8878365

Claim:
A semiconductor device, comprising: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; an electrode pad formed above the interlayer dielectric; at least one connection section at which the first conductive layer and the second conductive layer are connected in a shape of the letter “T” or “L” in plan view, wherein all of the connection sections being disposed in a specific region positioned outward from a line extending vertically downward from a first edge that is an outer edge of the electrode pad; a reinforcing section being provided at the connection section; a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad, wherein the passivation layer has a first upper surface and a second upper surface; wherein part of the second upper surface overlaps with part of the electrode pad, and the height of the second upper surface is higher than the height of the first upper surface; wherein a level difference between the first upper surface and the second upper surface corresponds to the shape of the electrode pad; a second edge of the second upper surface being formed at the location of the level difference; and wherein the specific region is positioned between the line extending vertically downward from the first edge and a line extending vertically downward from the second edge.