Patent ID: 7143411

Claim:
An apparatus for capping processor utilization in a computer system having one or more central processing units (CPUs), comprising: a scheduler coupled to each of the one or more CPUs; a process table coupled to the scheduler, wherein the process table includes identification information related to one or more application processes, and one or more cycle waster processes, and wherein the scheduler schedules a cycle waster process and the application process to operate on one or more of the one or more CPUs, wherein the cycle waster process consumes a percentage of processor resources and prevents other processes from using the percentage of processor resources; and a data provider that gathers processor data, wherein the gathered data includes CPU utilization data, and wherein the CPU utilization data is used to determine a charge for operation of the computer system, wherein a user can increase active processor resources by turning off one or more cycle waster processes, resulting in new data being transmitted to the data provider to produce a bill for the user.