Patent ID: 7955963

Claim:
A dry etching method for a semiconductor device, comprising: providing a polysilicon layer formed on a silicon substrate; implanting a first region of the polysilicon layer with N type ions and a second region of the polysilicon layer with P type ions, a further region of the polysilicon layer being left as a non-doped region; simultaneously gate-etching an N type polysilicon gate electrode from the first region, a P type polysilicon gate electrode from the second region, and a non-doped polysilicon dummy gate arrangement from the non-doped region of the polysilicon layer during a two-stage etching process; wherein the N type polysilicon gate electrode has an area that is smaller than the area of the first region of the polysilicon layer and the P type polysilicon gate electrode has an area that is smaller than the area of the second region of the polysilicon layer, wherein the etched area of the non-doped polysilicon region is larger than the sum of the etched area of the first region of the polysilicon layer and the etched area of the second region of the polysilicon layer, and wherein an end point detection of one of the stages of the etching process is based on the etching of the non-doped polysilicon dummy gate arrangement.