Patent ID: 7405949

Claim:
A memory system, comprising: first and second primary memories; first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection; a first memory module having at least two of the first and second primary and first and second secondary memories; a first connection element for connecting at least one memory of the first memory module to a mother board; a second connection element for connecting at least one of the memories except the at least two memories of the first memory module to the mother board; a controller coupled to at least one of the first and second primary memories for transmitting first signals and coupled to at least two of the first and second primary and secondary memories for receiving second signals; and wherein the second signals include data signals, a first half of the data signals being accessed is transferred to the controller by one of the primary and secondary memories, and a second half of the data signals being accessed is transferred to the controller by another of the primary and secondary memories.