Patent ID: 7282451

Claim:
A method of forming an integrated circuit device, comprising the steps of: forming a first electrically insulating layer on a semiconductor substrate; forming a second electrically insulating layer on the first electrically insulating layer; forming a first contact hole that extends through the first and second electrically insulating layers; then forming a first recess in the second electrically insulating layer, at a location adjacent the first contact hole; filling the first contact hole and the first recess with a first electrically conductive material; exposing at least a portion of the first electrically conductive material within the first contact hole by etching back a portion of the second electrically insulating layer using the first electrically conductive material within the first contact hole and within the first recess as an etching mask; and covering the exposed portion of the first electrically conductive material with a second electrically conductive material to thereby define a wiring pattern comprising the first and second electrically conductive materials.