Patent ID: 8700818

Claim:
An apparatus comprising a plurality of devices in a serial interconnection configuration, each of the plurality of devices having input and output connections, the serial interconnection configuration including at least first and second devices, the output connection of the first device being coupled to the input connection of the second device, the first device comprising: a packet based processor comprising a clock producer responsive to an input clock to produce first and second clocks at different times, the packet based processor being configured: to receive a first packet containing at least one packet start bit, an operation command for device identification production and a first device identifier number; to interpret the operation command contained in the received first packet in synchronization with the first clock; to produce a second device identifier number based on the first device identifier number in response to the at least one packet start bit contained in the received first packet and the interpreted operation command in synchronization with the second clock; and to transfer a second packet containing the second device identifier number to the second device in synchronization with the input clock.