Patent ID: 7132350

Claim:
A method for manufacturing an integrated circuit including memory cells on a substrate, where data is stored by setting a property of a selected memory cell above or below a reference level to store a data value, comprising: forming a first plurality of conductive lines on said substrate, said first plurality of conductive lines extending generally in parallel in a first direction; forming a second plurality of conductive lines over said first plurality of conductive lines, said second plurality of conductive lines extending generally in parallel in a second direction orthogonal to the first direction defining an array of intersections; forming an inter-electrode layer of material at said intersections between said first plurality of conductive lines and said second plurality of conductive lines, said inter-electrode layer of material characterized by progressive change in a property in response to stress, to form memory cells at said intersections; and providing circuitry on said substrate for applying said stress to set said property above or below said reference level to indicate data values in the memory cells, and to reset said memory cells by changing said reference level.