Patent ID: 8629553

Claim:
A 3D integrated circuit structure comprising: an interface wafer, the interface wafer including a first wiring layer; a first active circuitry layer wafer comprising a P− layer that includes active circuitry, a third wiring layer of the first active circuitry layer wafer being bonded directly to the first wiring layer of the interface wafer; a second wiring layer on the backside of the P− layer of the first active circuitry layer wafer; and a second active circuitry layer wafer comprising a P+ portion covered by a P− layer, the P− layer of the second active circuitry layer wafer including active circuitry, a fourth wiring layer of the second active circuitry layer wafer being bonded to the second wiring layer on the backside of the P− layer of the first active circuitry layer wafer.