Patent ID: 6941649

Claim:
A method of fabricating a multi-layer circuit board, the method comprising: creating a first layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of a first dielectric material; creating a second layer arrangement comprising at least four patterned power plane layers, electrically isolated from each other and form the reference plane layers, within the circuit board, each power plane layer having a thickness at least equivalent to the thickness of the three-ounces-per-square-foot-copper, stacked between layers of a second dielectric material having better void-filling capability, during lamination under similar conditions, than the first dielectric material; creating a third layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of the first dielectric material; stacking the first, second, and third layer arrangement in that order; laminating the stacked layer arrangements together such that the first and second layer arrangement interface across a reference plane layer and the second and third layer arrangements interface across a reference plane layer; and forming a large plurality of plated thru-holes distributed throughout the circuit board, the plated thru-holes electrically connecting the reference plane layers, while leaving the power plane layers electrically isolated from each other and from the reference plane layers, within the circuit board.