Patent ID: 7817466

Claim:
A semiconductor array, comprising: a matrix of cells, the matrix being arranged in rows and columns of cells; and a plurality of control lines, each cell being coupled to a number of said control lines to allow select and read/write said cell; wherein at least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix; wherein at least one cell of said at least two rows shares one of its terminals with a distinct cell in another one of said at least two rows and in a same column, wherein the shared terminal is a single terminal on a trace without an insulating region between connections of the cells sharing the terminal to the shared terminal; wherein the number of said control lines to which is coupled each cell includes at least one selection line adapted to select said cell, and at least one access line adapted to read/write said cell; and wherein two distinct selection lines are respectively coupled to the at least one cell and to the distinct cell that share said shared terminal.