Patent ID: 8268692

Claim:
A method of fabricating a memory cell, the method comprising: forming nanodots on a first dielectric material above a source region and a drain region; forming an intergate dielectric material between the first dielectric material and a control gate material, where the intergate dielectric material encases the nanodots, and where the control gate material is formed subsequent to forming the intergate dielectric material; performing a first etch process that removes a portion of the control gate material and a portion of the intergate dielectric material such that sidewalls of a cell stack are formed, wherein at least one of the sidewalls includes at least a portion of a nanodot protruding therefrom; forming a spacer material on the sidewalls of the cell stack and covering the at least a portion of the nanodot protruding therefrom; and performing a second etch process subsequent to forming the spacer material on the sidewalls of the cell stack, the second etch removing a remaining portion of the intergate dielectric material.