Patent ID: 8073892

Claim:
A multiplier, comprising: a set of multiple multipliers configured in parallel, the set of multiple multipliers having access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments; logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand, the logic configured to sequence the segments of the first and second operands supplied to the multipliers so as to produce at least one affected least significant bit and at least one unaffected least significant bit, the at least one affected least significant bit corresponding to a least significant bit or bits of a result of multiplying the single segment of the second operand and the multiple respective segments of the first operand that is/are affected by subsequent output by the multipliers, the at least one unaffected least significant bit corresponding to a least significant bit or bits of a result of multiplying the single segment of the second operand and the multiple respective segments of the first operand that is/are unaffected by subsequent output by the multipliers, the logic further configured to shift the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand; an accumulator coupled to the logic, wherein the accumulator is configured to retire only the at least one unaffected least significant bit; and logic coupled to the accumulator configured to shift unretired bits of each result of multiplying the single segment of the second operand and the multiple respective segments of the first operand that is unaffected by subsequent output by the multipliers by a number of bits corresponding to the number of bits retired.