Patent ID: 8295087

Claim:
A method for operating an array of EEPROM connected flash nonvolatile memory cells at increments of a page and block comprising: programming selected EEPROM connected flash nonvolatile memory cells by the steps of: generating a very large positive programming voltage, a high program voltage, and a very large negative programming voltage so as to prevent drain to source breakdown in peripheral row decoding and generating circuits, and applying the very large positive programming voltage to a gate of a charge retaining select transistor, the high program voltage to a drain of a charge retaining memory transistor of the selected EEPROM connected flash nonvolatile memory cells and the very large negative programming voltage to a control gate of a charge retaining memory transistor of the selected EEPROM connected flash nonvolatile memory cells to initiate a Fowler-Nordheim tunneling phenomena while minimizing operational disturbances in with in unselected EEPROM connected flash nonvolatile memory cells; and erasing selected EEPROM connected flash nonvolatile memory cells by the steps of: generating a very large positive erasing voltage and a very large negative erasing voltage to prevent drain to source breakdown in the peripheral row decoding and generating circuits, and applying the very large positive erasing voltage to the control gate of the charge retaining memory transistor of the selected EEPROM connected flash nonvolatile memory cells and the very large negative erasing voltage to a drain and source of the charge retaining memory transistor and the gate of the charge retaining select transistor of the selected EEPROM connected flash nonvolatile memory cells and to an isolation diffusion well into which the selected EEPROM connected flash nonvolatile memory cells are formed to initiate a Fowler-Nordheim tunneling phenomena while minimizing operational disturbances in with in unselected EEPROM connected flash nonvolatile memory cells; coupling a ground reference voltage level to the control gate of the charge retaining memory transistor of unselected EEPROM connected flash nonvolatile memory cells of a selected block, and disconnecting the control gate of the charge retaining memory transistor of the EEPROM connected flash nonvolatile memory cells so that the very high negative erase voltage is coupled from the isolation diffusion well to the control gate of the charge retaining memory transistor of the unselected EEPROM connected flash nonvolatile memory cells in unselected blocks.