Patent ID: 8407432

Claim:
A processor comprising: a last level cache (LLC); a set of LLC request queues to hold a number of outstanding entries of a plurality of access requests prior to scheduling of their access to the LLC; control logic to determine a utilization of the LLC at least in part from the number of outstanding entries in the set of LLC request queues; and a scheduler coupled to the LLC, the scheduler to select which outstanding entries to schedule, from the plurality of access requests in the LLC request queues, to the LLC in a round robin fashion without a priority mechanism in response to determining the LLC has a utilization below a threshold utilization, and the scheduler to grant a higher priority scheduling to an access request of the plurality of access requests than in an equal round robin scheduling of the plurality of access requests, said higher priority scheduling based on a request type of the access request, and said granting in response to determining the LLC has a utilization above the threshold utilization.