Patent ID: 7242233

Claim:
A pulse width limiting circuit, comprising: a clock signal correction block configured to receive a conditioned clock signal and generate a corrected clock output signal, wherein the clock signal comprises a train of clock pulses, each of which has a rising clock edge, a falling clock edge and a variable width; a block delay module, coupled to the clock signal correction block, configured to accept an unconditioned clock signal and introduce a specified pulse width delay to thereby generate the conditioned clock signal, wherein the block delay module comprises a plurality of delay sub-blocks of fixed delay; and a high low clock pulse shuttle circuit, coupled to the clock signal correction block, configured to accept the conditioned clock signal, wherein the high low clock pulse shuttle comprises a first field effect transistor (FET) coupled to the correction block and a second FET coupled to a conditioned clock signal output interconnect, and wherein the high low clock pulse shuttle circuit shunts the unconditioned clock signal to the block delay module if a clock pulse width of the unconditioned clock signal is outside a pulse width limit, and wherein the unconditioned clock signal is passed as the corrected clock output signal if the clock pulse width of the unconditioned clock signal is equal to or less than the pulse width limit by bypassing the high low clock pulse shuttle circuit.