Patent ID: 6907095

Claim:
A clock ride-over circuit in which an input digital signal synchronized with a first clock signal is converted into a digital signal synchronized with a second clock signal, and in which a result of conversion is output as an output digital signal, comprising: (a) a first synchronization circuit matching a phase of an input digital signal to a phase of said first clock signal to output said input digital signal phase-matched to said first clock signal; (b) a selector selecting said input digital signal phase-matched to said first clock signal or an output digital signal of the clock ride-over circuit, depending on a value of a selection signal of the same frequency as that of said first clock signal, to output a selected digital signal as an intermediate digital signal; (c) a second synchronization circuit synchronizing said intermediate digital signal to output said intermediate digital signal synchronized with said second clock signal as said output digital signal; and (d) a timing control circuit generating said selection signal based on said first clock signal and said second clock signal.