Patent ID: 8189416

Claim:
A semiconductor memory device, comprising: a first memory cell connected between a first word line and a bit line; a second memory cell connected between a second word line and an inverted bit line; a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation; a first sense amplifier including a first transistor connected between the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied, and the first sense amplifier including a second transistor connected between the inverted bit line and a second node, the second transistor including a gate to which a signal of the bit line is applied, and the first sense amplifier configured to amplify a voltage of one of the bit line and the inverted bit line to a second voltage based on the second voltage applied to one of the first node and the second node during the read operation; a bias unit configured to generate a voltage difference between the first node and the second node; and a sense amplifier driver configured to apply the second voltage to one of the first and second nodes based on the selected one of the first and second word lines during the read operation.