Patent ID: 8335125

Claim:
A method of controlling a semiconductor memory device which includes a transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS (metal-oxide-semiconductor) transistor to whose gate a drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load, and a control circuit which turns the p-type MOS transistor on and off, the method comprising: making the control circuit turn the p-type MOS transistor on to make the p-type MOS transistor transfer the first voltage to the gate of the n-type MOS transistor, thereby turning the n-type MOS transistor on; turning the n-type MOS transistor on to transfer the second voltage to the load; turning the p-type MOS transistor off in the middle of transferring the second voltage to the load, thereby making the gate of the n-type MOS transistor float at the first voltage; and making the n-type MOS transistor, being in a floating state, transfer the second voltage to the load.