Patent ID: 7031217

Claim:
A semiconductor integrated circuit device on one semiconductor substrate, the semiconductor integrated circuit device comprising: a dynamic type random access memory having: word lines; data lines; a plurality of memory cells to store data which needs to be periodically refreshed, each memory cell including: a capacitance; and a selecting MOSFET having a gate coupled to one of the word lines and a source-drain path coupled between one of the data lines and one terminal of the capacitance; a refresh timer to determine a refresh interval of the memory cells; a voltage step-down circuit which is coupled to receive a first and a second external voltage and which generates an internal supply voltage; a first volatile storage circuit coupled to the refresh timer to store first information; a second volatile storage circuit which is coupled to the voltage step-down circuit to store second information to trim a voltage level of the internal supply voltage, and electrically programmable nonvolatile elements storing the first and the second information, wherein the first and the second information are read out from the electrically programmable nonvolatile elements and are stored in the first and second volatile storage circuits in response to an initialization of the semiconductor integrated circuit device so that the refresh timer is operated in accordance with the first information and the internal supply voltage which is trimmed by the second information is supplied from the voltage step-down circuit to a dynamic type random access memory.