Patent ID: 7462539

Claim:
A semiconductor device manufacturing method comprising the steps of: (a) forming an isolation region on a semiconductor substrate, said isolation region defining a continuous active region including a select transistor region and a direct tunnel element region; (b) forming a gate insulating film on a channel region of said select transistor region; (c) forming a tunnel insulating film on a partial area of said direct tunnel element region, said tunnel insulating film having a thickness different from a thickness of said gate insulating film; (d) forming a continuous floating gate electrode layer above an area including said gate insulating film and said tunnel insulating film; (e) forming an inter-electrode insulating film on a surface of said floating gate electrode; (f) forming a control gate electrode layer on said inter-electrode insulating film; (g) patterning said control gate electrode layer, said inter-electrode insulating film and said floating gate electrode layer; and (h) forming a pair of source/drain regions on both sides of the channel region of said select transistor region, said pair of source/drain regions not overlapping said tunnel insulating film.