Patent ID: 7170783

Claim:
A memory array for a non-volatile memory device, the memory array comprising: a first memory sub-array having a first plurality of non-volatile memory cells and a first plurality of word lines coupled to the first plurality of non-volatile memory cells; a second memory sub-array having a second plurality of non-volatile memory cells and a second plurality of word lines coupled to the second plurality of non-volatile memory cells; a shared circuit region in which a first portion of a plurality of row decoder circuits and a plurality of word line driver circuits are formed, each of the first portion of row decoder circuits configured to generate a driver enable signal and each word line driver circuit coupled to at least one of the first plurality of word lines and at least one of the second plurality of word lines and configured to drive the respective word line responsive to the driver enable signal, the shared circuit region having a position relative to the first and second memory sub-arrays separating the first and second memory sub-arrays; a row decoder region in which a second portion of the plurality of row decoder circuits are formed, each of the second portion of row decoder circuits configured to decode address signals and generate a selection signal in response to receiving address signals selecting the respective row decoder circuit, the row decoder region separated from the shared circuit region by the first memory sub-array; and a plurality of conductive lines coupling the first and second portions of the plurality of row decoder circuits.