Patent ID: 8773186

Claim:
A duty cycle correction circuit, comprising: a duty cycle detector configured to generate a pair of control signals in response to a pair of internal clock signals; a filter configured to obtain average voltages of the pair of control signals; a comparator configured to compare a pair of output signals from the filter to generate a comparison result; a successive approximation register digital to analog converter (SAR DAC) configured to perform a SAR algorithm to generate a pair of analog output signals based on the comparison result; a first equalization device configured to equalize voltage levels of the pair of control signals; a pass gate circuit configured to apply the pair of control signals to a duty cycle corrector if the pass gate circuit is enabled; and a duty cycle corrector configured to receive a pair of external clock signals, the pair of analog output signals, and a pair of output signals from the pass gate circuit to generate the pair of internal clock signals with a corrected duty cycle.