Patent ID: 7965725

Claim:
A network-on-chip for interconnecting an array of resources, comprising: a physical vertical communication ring for each of M columns of the array, each physical vertical communication ring supporting at least one circulating vertical logical transport channel for conveying a packet, wherein M>2; a physical horizontal communication ring for each of N rows of the array, each physical horizontal communication ring supporting at least one circulating horizontal logical transport channel for conveying a packet, wherein N>2; a network interface associated with each resource of the array and operable to interface the communications rings with each other and to interface the resource with the communications rings, each network interface including: a first ring hop connected to the physical vertical communication ring passing through the network interface, and a second ring hop connected to the physical horizontal communication ring passing through the network interface; and a back pressure circuit for each physical vertical communication ring and each physical horizontal communication ring, wherein the back pressure circuit, which is directly connected to each of the M or N first and second ring hops, is operable to inform the each of the M or N first and second ring hops, respectively, on a given communication ring of an overflow condition on that given communication ring and thus prevent ring hop action to insert packets into the logical transport channel circulating on that given communication ring.