Patent ID: 7315971

Claim:
A method for testing a device including a nonvolatile memory cell, the method comprising: providing a device with a digital portion and an analog portion; wherein the digital portion includes: a plurality of latch devices; wherein the analog portion includes: a plurality of memory cells; a plurality of selector devices, wherein each of the plurality of selector devices is electrically coupled to a respective one of the nonvolatile memory cells; wherein each of the plurality selector devices is at least indirectly coupled to one of the plurality of latch devices; and wherein at least one of the plurality of selector devices is controlled by a selector input; applying a load clock to the plurality of latch devices, wherein a pattern is loaded into the plurality of latch devices; driving inputs of the nonvolatile memory cells with the pattern; driving the selector input to receive a derivative of the pattern from the inputs of the nonvolatile memory cells by the plurality of selectors, and the derivative of the pattern is returned to at least a subset of the plurality of latch devices; and applying a system clock to the plurality of latch devices, wherein the derivative of the pattern is loaded into the plurality of latch devices.