Patent ID: 7439151

Claim:
A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing, the method comprising: forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, said ILD layer having a first dielectric capping layer formed thereon; forming an upper ILD layer over said lower ILD layer; defining a via and an upper line structure within said upper ILD layer; filling said via and upper line structure with a planarizing layer; forming and patterning a resist layer over said planarizing layer; defining an upper capacitor electrode structure in said upper ILD layer corresponding to a removed portion of said resist layer; and filling said via, said upper line structure and said upper capacitor electrode structure with conductive material, wherein a MIM capacitor is defined by said lower capacitor electrode, said first dielectric capping layer and said filled upper capacitor electrode structure.