Patent ID: 7893536

Claim:
A semiconductor device comprising: a semiconductor substrate; an element provided on the semiconductor substrate; and a multilayer interconnect configuration formed on the element, a multilayer pad outside the multilayer interconnect configuration, the multilayer pad having a plurality of pads, each pad being located in each of a plurality of interconnect layers of the multilayer pad, and at least one of the pads having a plurality of openings formed therein, wherein: a first pad located in a highest position among the pads is configured for connection exterior to the semiconductor device, a second pad located in a lowest position among the pads is connected to the element provided on the semiconductor substrate, each of the pads except the first pad is formed in at least part of a region directly below a pad in an upper layer, the multilayer interconnect configuration has via contacts interconnecting the pads in adjacent interconnect layers, and arrangements of the via contacts and the openings are configured in a grid, wherein each of the via contacts and each of the openings are alternately arranged, and a pitch of the via contacts and a pitch of the openings are substantially equal from a perspective above the semiconductor substrate.