Patent ID: 7072355

Claim:
A signal interface, comprising: a set of signal lines having N+1 signal lines, where N is an integer; N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; an N line bus; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set to the N line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set to the N line bus; wherein for a change of (n) by switching a first particular signal path from routing to the line maintenance circuit to routing to a line in the N line bus, and a second particular signal path from routing to the line in the N line bus to the line maintenance circuit, the control logic controls the switch so that reception of data from the line in the N line bus is uninterrupted; and wherein the receivers are responsive to respective receive clocks produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit.