Patent ID: 7923982

Claim:
A semiconductor integrated circuit comprising: a signal wire; and a voltage level detector for detecting a voltage level of the signal wire, wherein: the voltage level detector detects the voltage level of the signal wire during a transition period during which the signal wire changes from an inactive voltage state to an active voltage state based on the voltage level detected by the voltage detector, the voltage level detector comprises at least a first NMOS transistor and a first PMOS transistor, the signal wire is connected to a gate of the first NMOS transistor, a first voltage is connected to a source of the first NMOS transistor, a drain of the first NMOS transistor is connected to a drain of the first PMOS transistor, a clock is inputted to a gate of the first PMOS transistor, a second voltage is connected to a source of the first PMOS transistor, a voltage larger than the first voltage is set to the drain of the first NMOS transistor prior to the transition period during which the signal wire changes from the inactive voltage state to the active voltage state, and the voltage level detector detects the drain voltage of the first NMOS transistor during the transition period.