Patent ID: 7443194

Claim:
An I/O driver with v/i characteristic control for maintaining a substantially flat output impedance response using a configuration at an I/O output pad, the configuration comprising: a linear resistive element electrically connected at the I/O output pad for limiting variations of a processed I/O signal; and an active impedance matching element for receiving and processing pull-up and pull-down array calibration words and a data signal comprising data represented by a series of voltage state transitions to generate and output the processed I/O signal to the linear resistive element such that the I/O output pad displays a substantially flat v/i response at switching of the data signal, the active impedance matching element further comprising a pull-up stage and a pull-down stage, wherein the pull-up stage comprises: a pull-up array including PFET devices connected in parallel and configured to exhibit different conductance values corresponding to binary weighted bit positions of a PFET calibration word that controls activation of the PFET devices for providing active impedance compensation at switching of the data signal from a low value to a higher value; a pull-up base circuit including a base PFET device connected in parallel with the PFET devices in the pull-up array; and a first stack of at least two series connected complementary NFETs, the first stack being connected in parallel with the base PFET device of the pull-up array; and wherein the pull-down stage comprises: a pull-down array of NFET devices connected in parallel and configured to exhibit different conductance values corresponding to binary weighted bit positions of an NFET calibration word that controls array device activation and active impedance compensation at switching of the data signal from the higher value to the low value; NFET stacks formed by connecting each of the NFET devices in series with at least a further NFET device that is enabled when the pull-down array is enabled; a pull-down base circuit including a base NFET device connected in series with at least an additional NFET device to form a second stack, the second stack being connected in parallel with the NFET stacks of the pull-down array, and at least one complementary PFET connected in parallel with the second stack including base NFET device; and a logical circuit for controlling the active impedance matching element for providing inputs to the pull-up array and the pull-down array, the inputs including the pull-up and pull-down array calibration words and inputs to the pull-up base circuit and to the pull-down base circuit; wherein during I/O operation, a combined impedance contribution from the linear resistive element and the active impedance matching element provides for the substantially flat output impedance.