Patent ID: 8686764

Claim:
A circuit for generating a clock signal, comprising: a multiplexer circuit to selectively output one of a plurality of input clock signals; and an edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is connected to an output of the multiplexer circuit, wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop circuit is connected to a select control port of the multiplexer circuit, wherein the edge-triggered flip-flop circuit detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port, wherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop circuit, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop circuit, which output clock signal is input to the select control port of the multiplexer circuit, and wherein the plurality of input clock signals are clock signals with distorted duty cycles, and wherein the circuit corrects the duty cycles of the input clock signals by using the multiplexer circuit to select transitioning edges of the input clock signals that are substantially equally spaced in time, and by using the selected transitioning edges to trigger the edge-triggered flip-flop circuit to generate an output clock signal at the output port which is substantially free of duty cycle distortion.