Patent ID: 8044745

Claim:
An apparatus for generating a clock signal, the apparatus comprising: a quadrature delay circuit having an input, a first output and a second output, the input being connected to an input clock signal, wherein the quadrature delay circuit is adapted to provide a first component of the input clock signal on the first output and a second component of the input clock signal on the second output, wherein the first component and the second component each have a different phase shift; a first amplitude modulator having an input and an output, the input being connected to the first output of the quadrature delay circuit; a second amplitude modulator having an input and an output, the input being connected to the second output of the quadrature delay circuit; and a summer having a first input, a second input and a clock output, the first input being connected to the output of the first amplitude modulator, the second input being connected to the output of the second amplitude modulator; and a storage device having a clock source connected to a plurality of serializer/deserializers, wherein the quadrature delay circuit, first and second amplitude modulators and summer are connected between the clock source and at least one of the plurality of serializer/deserializers to provide a plurality of different frequency offsets in the plurality of serializer/deserializers.