Patent ID: 7488687

Claim:
A method of forming an electrical interconnect structure, comprising the steps of: forming a first dielectric layer having a first dielectric constant on a semiconductor substrate; forming a hard mask layer having a second dielectric constant greater than the first dielectric constant, on the first dielectric layer; patterning a photoresist layer on an upper surface of the hard mask layer; selectively etching the hard mask layer to define an opening therein that exposes the first dielectric layer, using the patterned photoresist layer as an etching mask; stripping the patterned photoresist layer from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer; and selectively etching a portion of the first dielectric layer extending opposite the opening while simultaneously accumulating polymer residues directly on the upper surface of the hard mask layer, using the hard mask layer as an etching mask.