Patent ID: 7613212

Claim:
A system for distributing a master clock source over an asynchronous Ethernet transport network, comprising: a clock distribution unit comprising: a clock distribution transmitter operative to generate network timestamps derived from said master clock source and to insert said network timestamps and a clock quality indication into clock synchronization packets comprising modified Ethernet packets, said clock quality indication adapted to convey a measure of the quality of said master clock source; a distributor operative to transmit said modified Ethernet packets to a plurality of circuit emulation service (CES) modules connected to said network; each CES module comprising: a receiver operative to receive said modified Ethernet packets, extract said network timestamp therefrom; a digital time delay loop (DTLL) operative to generate a local timestamp utilizing a reconstructed clock generated by a local clock source, to initially apply quick coarse filtering followed by application of slow fine filtering to time differences between said local timestamps and said received network timestamps to generate a clock control signal thereby, and to correct the frequency of said reconstructed clock in accordance with said clock control signal, said DTLL operative to implement a closed loop tracking system whereby an equilibrium point is achieved comprising a constant value of network timestamp minus local timestamp and any deviations in the equilibrium point are corrected by said DTLL; wherein said clock control signal is generated based on only the difference between two timestamps comprising said network timestamps sent when said clock synchronization packet are transmitted by said transmitter and said local timestamps generated when said clock synchronization packets are received at said receiver.