Patent ID: 8604868

Claim:
A biasing circuit comprising: an input configured to receive a supply voltage; an output; a control stage configured to generate first and second control signals, said control stage comprising a first biasing capacitor coupled to a first internal node and configured to receive a first low voltage phase signal, a second biasing capacitor coupled to a second internal node and configured to receive a second low voltage phase signal, a first control transistor coupled between the input and the first internal node, and having a control terminal coupled to the second internal node, and a second control transistor coupled between the input and the second internal node, and having a control terminal coupled to the first internal node; and a biasing stage configured to generate on the output a biasing voltage based upon the first and second control signals, said biasing stage comprising a first buffer capacitor coupled connected to a third internal node and configured to receive the second low voltage phase signal, and a second buffer capacitor coupled to a fourth internal node and configured to receive the first low voltage phase signal, a first biasing transistor coupled between the third internal node and the output, and having a respective control terminal coupled to the fourth internal node, a second biasing transistor coupled between the fourth internal node and the output, and having a respective control terminal coupled to the third internal node, a third biasing transistor having a first conduction terminal configured to receive the first control signal, and a second conduction terminal coupled to the output, and having a respective control terminal coupled to the third internal node, and a fourth biasing transistor having a first conduction terminal configured to receive the second control signal, and a second conduction terminal coupled to the output, and having a respective control terminal coupled to the fourth internal node.