Patent ID: 8273648

Claim:
A method of fabricating a circuit structure comprising: providing a chip comprising at least one substrate, the at least one substrate comprising at least one integrated circuit and a main surface; forming multiple back-end-of-line (BEOL) layers disposed over the main surface of the at least one substrate, the multiple BEOL layers extending to a common edge of the chip which defines a sidewall of the multiple BEOL layers, the sidewall being exposed at the common edge of the chip and forming the multiple BEOL layers comprises forming at least one vertically-extending conductive pattern in the sidewall at the common edge of the chip and oriented perpendicular to the main surface of the at least one substrate thereof; and wherein the at least one vertically-extending conductive pattern in the sidewall is defined partially by dielectric material and partially by a plurality of conductive elements disposed within the dielectric material of the multiple BEOL layers, at least some conductive elements of the plurality of conductive elements being spaced apart along the sidewall in a vertical direction and a horizontal direction throughout at least a portion of the multiple BEOL layers, with at least two conductive elements of the plurality of conductive elements residing within one BEOL layer of the multiple BEOL layers at the sidewall thereof exposed at the common edge of the chip and being spaced apart by dielectric material of the one BEOL layer, and with at least two other conductive elements of the plurality of conductive elements residing within different BEOL layers of the multiple BEOL layers at the sidewall thereof exposed at the common edge of the chip and being spaced apart by dielectric material of at least a third BEOL layer of the multiple BEOL layers, and the plurality of conductive elements being sized and positioned at the sidewall in the vertical direction and the horizontal direction to block electromagnetic interference of a particular wavelength from passing therethrough from a direction intersecting the common edge of the chip.