Patent ID: 7203109

Claim:
A hardware-verifying circuit arrangement comprising: one or more configuration elements operable to configure hardware elements; one or more hardware elements electrically coupled to and configurable by the configuration elements; one or more electrically-conductive pathways coupling at least one of the configuration elements to at least one of the hardware elements; and a hardware-verification register coupled to at least one of the electrically-conductive pathways, wherein the hardware-verification register is operable to: sample a voltage level on at least one of the electrically-conductive pathways at a first time point; store in a memory one or more bits, each bit representing the voltage level on at least one of the electrically-conductive pathways at the first time point; sample a voltage level on at least one of the electrically-conductive pathways at a second time point; and compare, for at least one of the electrically-conductive pathways, the voltage level at the first time point and the voltage level at the second time point.