Patent ID: 7489724

Claim:
A system comprising: a host, a target and connection means therebetween, said host having means for providing a test clock signal, first output means for outputting said test clock signal to said target via said connection means and second output means for outputting data to said target via said connection means, said data being clocked out by said test clock signal, said target having first input means for receiving said test clock signal from said host, second input means for receiving said data from said host and first output means for outputting data to said host via said connection means, said target is arranged to clock out data to said host over said first output means using said received test clock signal, said host further comprising input means for receiving said data from said target, and oversampling means for oversampling the received data from the target and generating a control signal to control clocking in of the data received from the target by the host based on samples of the received data from the target, the oversampling means being coupled to the means for providing the test clock signal.