Patent ID: 8830733

Claim:
Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells, each MRAM cell having a first storage state with a first resistance value and second storage state with a second resistance value, said controllable readout circuit comprising: a selecting device for selecting one of the MRAM cells; and a sense circuit adapted to source a sense current for measuring the first and second resistance value of the selected MRAM cell during a first and second read cycle, respectively; the sense circuit comprising a sample and hold circuit for storing said first resistance value, and a differential amplifier circuit for comparing said second resistance value to said stored first resistance value; wherein said controllable readout circuit further comprises a control circuit adapted to provide a pulse-shaped timing signal having a pulse duration controlling the duration of the first read cycle and the second read cyclesuch that said pulse duration of said pulse-shaped timing signal is adjustable, and wherein said controllable readout ciruit further comprising a timing capacitance, a constant current source adapted to provide a constant pull up current for charging the timing capacitance, a time control device generating a time reference voltage, and a voltage comparator for comparing the voltage corresponding to the timing capacitance and the time reference voltage and outputting the timing signal; and wherein the pulse duration of the pulse-shaped timing signal being determined by the charging speed of the timing capacitance and the value of the time reference voltage.