Patent ID: 7606098

Claim:
An integrated circuit device comprising: a memory cell array including: a plurality of word lines including a first word line and a second word line; a plurality of word line segments including a first word line segment and a second word line segment, wherein each word line segment is coupled to an associated word line and wherein the first word line segment is associated with the first word line and the second word line segment is associated with the second word line; a plurality of bit lines; and a plurality of memory cells, wherein each memory cell stores at least one data state and includes a transistor, wherein the transistor includes: a first region coupled to an associated bit line; a second region; a body region disposed between the first region and the second region, wherein the body region is electrically floating; and a gate coupled to an associated word line via an associated word line segment; and wherein: a first group of memory cells is coupled to the first word line via the first word line segment and a second group of memory cells is coupled to the second word line via the second word line segment; and at least one memory cell of the first group of memory cells is adjacent to at least one memory cell of the second group of memory cells; first circuitry, coupled to (i) a first memory cell in the first group of memory cells and (ii) a first memory cell in the second group of memory cells, to sense a data state stored in the first memory cell and a data state stored in the second memory cell wherein the first memory cell in the second group of memory cells is adjacent to one of the memory cells in the first group of memory cells; and reference generator circuitry, coupled to the first circuitry, to provide a reference to the first circuitry wherein the first circuitry uses the reference to sense the data state stored in each memory cell coupled to the first and second bit lines.