Patent ID: 6981233

Claim:
A method of processing a layout design for an integrated circuit (IC), wherein the IC comprises a clock tree for delivering a clock signal from a first IC node to a first plurality of sinks within the IC and to a second IC node forming a root of a subtree of the clock tree for delivering the clock signal from the second IC node to a second plurality of sinks within the IC, the method comprising the steps of: a. providing a model of the subtree for generating estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks, wherein the estimates are functions of a measure of relative magnitudes of path delays of rising and falling edges of the clock signal from the first IC node to the second IC node, when said measure is supplied as input to the model; b. processing the layout designs, thereby generating estimates of magnitudes of path delays of rising and falling edge of the clock signal between the first IC node and the second IC node and determining therefrom the measure of the relative magnitudes of the path delays of the rising and falling edges of the clock signal from the first node to the second IC node; and c. supplying the measure determined at step b as input to the model such that the model generates the estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks.