Patent ID: 7956790

Claim:
A retimed analog to digital converter circuit, the circuit comprising: a first set of sub-level interleaves, wherein the first set of sub-level interleaves includes: a first sub-level interleave, wherein the first sub-level interleave includes a first set of comparators synchronized to a first clock phase; a second sub-level interleave, wherein the second sub-level interleave includes a second set of comparators synchronized to a second clock phase; a second set of sub-level interleaves, wherein the second set of sub-level interleaves includes: a third sub-level interleave, wherein the third sub-level interleave includes a third set of comparators synchronized to a third clock phase; a fourth sub-level interleave, wherein the fourth sub-level interleave includes a fourth set of comparators synchronized to a fourth clock phase; and a global interleave, wherein the global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and wherein the global interleave selects one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves.