Patent ID: 8756404

Claim:
A computer-implemented method of scheduling execution instructions, comprising: receiving a first issue group comprising a plurality of instructions to be issued in a single cycle to a cascaded delayed execution pipeline unit of a processor core for execution, wherein the plurality of instructions includes at least first and second instructions, wherein at least the second instruction operates on at least one operand generated by the first instruction, wherein the processor core includes a forwarding path, wherein the cascaded delayed execution pipeline unit comprises first, second, third, and fourth execution pipelines, at least three of which each includes an execution unit and further includes an instruction queue or a target delay queue, wherein the instruction queue is configured to hold instructions prior to execution by the execution unit, thereby delaying execution of the held instructions, wherein the target delay queue is configured to hold results obtained from executing instructions by the execution unit, thereby allowing other, delayed instructions to finish execution; by scheduling circuitry associated with the processor core, scheduling the first instruction for execution in the first execution pipeline and scheduling the second instruction for execution in the second execution pipeline, in which execution is delayed with respect to the first execution pipeline; and issuing the plurality of instructions in a single cycle to the cascaded delayed execution pipeline unit of the processor core for execution, in accordance with the scheduling of the first and second instructions; wherein the forwarding path of the processor core is configured to forward results generated by executing the first instruction in the first execution pipeline to the second execution pipeline for use in executing the second instruction.