Patent ID: 7672182

Claim:
A memory circuit, comprising: (a) a memory array defined by SRAM cells, the memory array having rows and columns, and wordlines for accessing selected rows through a passgate and bitlines for accessing selected columns; (b) a plurality of bitline voltage level switches connected to a low power supply and a high power supply, the bitline voltage level switches having, (i) a write operation state defined to selectively provide the high power supply to bitlines in columns in which a write operation is to occur, and provide the low power supply to bitlines in columns in which the write operation is not identified to occur; (ii) a read operation state defined to selectively provide the low power supply to bitlines in columns in which a read operation is to occur, and provide the low power supply to bitlines in columns in which the read operation is not identified to occur; (c) a column decoder for identifying columns selected for the read or write operation state; and (d) a write enable switch connected to the bitline voltage level switches, and the column decoder.