Patent ID: 8824511

Claim:
A clock synchronization system which synchronizes the clock of a slave node with the clock of a master node by use of a timestamp packet transmitted from said master node to said slave node, wherein said slave node comprises a processor and a memory storing instructions that when executed by the processor performs processing comprising: calculating a difference between a received timestamp and a timestamp generated on the slave node side; suppressing jitters and noises contained in the difference; generating a control signal configured to ultimately reduce said difference to zero; outputting a clock signal with a frequency corresponding to the generated control signal; generating a clock signal with a frequency up-converted from the frequency of said clock signal; outputting a timestamp based on the clock signal; and increasing the resolution of the timestamp, and wherein increasing the resolution comprises: obtaining a quotient by dividing the timestamp value by a magnification coefficient that represents the extent to which the resolution of the timestamp will be increased; obtaining a value by further dividing the remainder of dividing said timestamp value by said magnification coefficient, again by said magnification coefficient; and outputting a value of adding said quotient and the value obtained by dividing said remainder by said magnification coefficient.