Patent ID: 7430150

Claim:
A multi-bank memory comprising: a first bank and a second bank, the first and second banks each including at least one array and an analog sensing circuitry, each array including a plurality of memory cells, each analog sensing circuitry including at least one high voltage switch; common digital sensing circuitry coupled with the analog sensing circuitry of the first bank and analog sensing circuitry of the second bank via a single output line, the common digital sensing circuitry including a programming logic and at least one multiplexer, the at least one multiplexer driving an I/ 0 bus and the programming logic receiving data that is to be programmed to the first bank from the I/O bus and receiving verified data from the analog sensing circuitry in the first bank after a read operation, the single output line transmitting information between the analog sensing circuitry of the first bank and the common digital sensing circuitry, the single output line being shielded from a the second bank.