Patent ID: 6973613

Claim:
A memory controller comprising: a check bit encoder circuit coupled to receive a data block to be written to a memory comprising a plurality of memory devices, wherein the check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least: (i) detection and correction of a failure of one of the plurality of memory devices; and (ii) detection and correction of a single bit error in the encoded data block following detection of the failure of one of the plurality of memory devices; wherein the memory controller is configured to write the encoded data block to the memory; a check/correct circuit coupled to receive the encoded data block from the memory and configured to decode the encoded data block and perform at least the detection of (i) and (ii) on the encoded data block; and a data remap control circuit coupled to the check/correct circuit, wherein the data remap control circuit is coupled to receive an identification of a failing memory device of the plurality of memory devices, and wherein the data remap control circuit is configured, in response to the check/correct circuit detecting (i), to read each data block for which the failing memory device stores at least one bit of the data block and for which at least one other bit of the data block is stored in a different one of the plurality of memory devices, and wherein the check bit encoder circuit is configured to recode the data block to avoid storing bits in the failing memory device and to write the recoded block to the plurality of memory devices.