Patent ID: 7732272

Claim:
A method of manufacturing a semiconductor element, comprising: forming a gate electrode on a semiconductor substrate, the gate electrode having a metallic silicide layer, a metallic polysilicon layer under the metallic silicide layer, and an SiN layer on the metallic silicide layer; after said forming of the gate electrode including the SiN layer, decreasing grain boundaries on a surface of the metallic silicide layer, at least a portion of the surface of the metallic silicide layer being exposed, said decreasing of the grain boundaries comprising performing a heat treatment on the metallic silicide layer in an atmosphere consisting of a mixture gas of chief elements of nitrogen and ammonia and an oxidizable gas of less than 100 ppm; and forming a spacer consisting of an oxide film on a side wall of the metallic polysilicon layer and the metallic silicide layer of the gate electrode; wherein said decreasing of the grain boundaries is performed after performing a reduced pressure process.