Patent ID: 8112615

Claim:
A single cycle RISC processor to perform instruction execution operations, the processor comprising: a register file having a register input and a register output, the register file configured such that a signal provided to the register input is reflected at the register output after an offset delay, and configured to provide data for an instruction fetch via the register output; an instruction decoder configured to perform an instruction decode; an arithmetic logic unit coupled to the register file and to the instruction decoder, the arithmetic logic unit configured to perform an instruction execution operation based on data from the register output and to provide a resulting data output to the register input; and the RISC processor configured to perform instruction execution operation in which the instruction fetch, the instruction decode, and the instruction execution on data fetched from the register output are completed during a time period that is less than a duration of the offset delay in a clock cycle for the instruction execution operation, wherein the duration of the offset delay is less than a duration of the clock cycle.