Patent ID: 8838660

Claim:
A reduced sensitivity filter circuit, the circuit comprising: a digital filter operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output; and a filter tap adaptation circuit operable to receive an error value, a weighting control value, a first digital sample derived from the received input and a second digital sample derived from the received input; and to adaptively calculate at least one of the filter taps using the error value and the weighting control value, wherein adaptively calculating the at least one of the filter taps includes adaptively calculating an updated delta value by subtracting a modification value from a previously calculated delta value to yield the updated delta value, wherein the modification value is calculated based at least in part upon the first digital sample and the second digital sample, and wherein the filter tap adaptation circuit sets a difference between a first tap of the plurality filter taps and a second tap of the plurality of filter taps equal to the updated delta value.