Patent ID: 8710871

Claim:
A delay line, comprising: a compensating circuit having at least one transistor and being configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit; and a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and being coupled to the output node of the compensating circuit, and each of the delay stages being configured to use the bias signal provided at the output node to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes, wherein each of the delay stages is further configured to use the bias signal to maintain the gain of the respective delay stage at a substantially unity gain at a particular magnitude of an input signal applied to the respective delay stage as a transconductance of the at least one in transistor in the respective delay stage changes, and wherein each of the delay stages is further configured to have a gain of greater than unit for an input signal provided to the respective delay stage having a magnitude that is less than the particular magnitude, and a gain of less than unity for an input signal provided to the respective delay stage having a magnitude that is greater than the particular magnitude.