Patent ID: 7657708

Claim:
A method for reducing data cache access power in a processor, comprising: (1) storing base address data bits, offset data bits, a first carry bit, and way selection data bits respectively in a base register, an offset register, a carry register and a way selection register in a micro tag array; (2) invalidating entries of the micro tag array whose way selection data bits correspond to an intended refill way of the cache when a tagram write occurs; and (3) enabling a first dataram of a cache specified by way selection data bits stored in the way selection register of the micro tag array if first selected base address data bits stored in a processor pipeline register match base address data bits stored in the base register of the micro tag array, and if first selected offset data bits stored in the processor pipeline register match offset data bits stored in the offset register of the micro tag array, and if a second carry bit formed by an addition of second selected base address data bits stored in the processor pipeline register and second selected offset data bits stored in the processor pipeline register match the first carry bit.