Patent ID: 7200738

Claim:
A method of operating a pipelined computer processor, said method comprising: identifying program instructions dependent upon results of prior program instructions in a set of instructions; dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, each instruction of said set belonging to only one subset; and processing at least two of said subsets concurrently in an instruction pipeline, each of said two subsets operating on a different piece of input data, wherein said processing comprises: processing in said instruction pipeline a first subset of instructions operating on a first piece of input data during a number of clock cycles to produce a first processed piece of input data, and processing in said instruction pipeline said first subset of instructions operating on a second piece of input data and a second subset of instructions operating on said first processed piece of input data concurrently during a next number of clock cycles to generate an output.