Patent ID: 8344920

Claim:
A method of calibrating a pipeline analog-to-digital converter comprising one or more serially connected analog-to-digital pipeline stages and a back-end analog-to-digital converter, said pipeline analog-to-digital converter further including digital circuitry for receiving digital outputs of each of the one or more pipeline stages and the back-end converter, adjusting the outputs using calibration coefficients to correct additive, multiplicative, and offset errors, and combining the outputs, the method comprising the steps of: (a) for a selected pipeline stage: (i) disconnecting inputs of the pipeline stage from an immediately preceding pipeline stage, or if the pipeline stage is the first pipeline stage of the pipeline analog-to-digital converter disconnecting inputs of the pipeline stage from an input of the pipeline analog-to-digital converter; (ii) measuring values for stage gain errors, stage capacitive mismatch errors, and stage offset errors for the pipeline stage; (iii) calculating calibration coefficients for the pipeline stage based on the measured values and updating the calibration coefficients for use in correcting additive, multiplicative, and offset errors in a normal operation mode of the pipeline stage; and (iv) connecting the inputs of the pipeline stage to the immediately preceding pipeline stage, or if the pipeline stage is the first pipeline stage connecting inputs of the pipeline stage to an input of the pipeline analog-to-digital converter such that the pipeline stage can operate in a normal operation mode; and (b) if the selected pipeline stage is not the first pipeline stage, repeating steps (i)-(iv) separately for each pipeline stage immediately preceding the pipeline stage last calibrated until all pipeline stages preceding said selected pipeline stage have been successively calibrated so that the pipeline-analog-to-digital converter can be used in a normal operation mode.