Patent ID: 7659893

Claim:
A graphics processor comprising: a plane equation module to receive vertex information for a plurality of primitives, each primitive covering one or more of a plurality of tiles, and to generate a compressed Z representation corresponding to each primitive, each compressed Z representation being associated with at least one tile covered by the corresponding primitive; a first processing section subsequent to the plane equation module, the first processing section including a first arithmetic circuit to compute a first Z coordinate for a sample location within a first tile from a first compressed Z representation associated with the first tile; a second processing section subsequent to the plane equation module, the second processing section including a second arithmetic circuit to compute a second Z coordinate for a sample location within the first tile from a second compressed Z representation associated with the first tile; and a third processing section subsequent to the plane equation module, the third processing section to receive the first Z coordinate from the first processing section and the second Z coordinate from the second processing section and to compare the first Z coordinate and the second Z coordinate, wherein the first arithmetic circuit and the second arithmetic circuit are bit-identical to each other.