Patent ID: 8285939

Claim:
A method of data processing in a data processing system including a plurality of processing units each including a respective processor core and associated upper and lower level caches, said method comprising: in response to a data request of the processor core of a first processing unit among the plurality of processing units, selecting a victim cache line to be castout from the lower level cache of the first processing unit; selecting the lower level cache of a second of the plurality of processing units as an intended destination of a lateral castout (LCO) command by randomized round-robin selection; the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the lower level cache of the first processing unit and indicates the lower level cache of the second processing unit as the intended destination of the victim cache line; and in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the lower level cache of the first processing unit and holding the victim cache line in the lower level cache of one of the plurality of processing units other than the first processing unit.