Patent ID: 8509020

Claim:
An apparatus comprising: a first semiconductor device; and a second semiconductor device coupled to each other, the first semiconductor device comprising a plurality of memory blocks, each including a plurality of memory cells, and the second semiconductor device comprising a control circuit that is configured to issue an access request to the first semiconductor device with producing and supplying to the first semiconductor device a command and a burst operation mode simultaneously with each other, the command designating a data read or a data write operation, and the burst operation mode including first information and second information, the first information indicating a burst length that designates a first number of data that are to be transferred in series between the first and second semiconductor devices, and the second information indicating a block selection that designates one of the memory blocks of the first semiconductor device as a start block, wherein: when the first number is not greater than a second number, the first number of data, that are to be transferred in series between the first and second semiconductor devices, are read out from or written into the first number of memory cells each included in the start block of the memory blocks, and when the first number is greater than the second number, the first number of data, that are to be transferred in series between the first and second semiconductor devices, are read out from or written into the second number of memory cells, each included in the start block of the memory blocks, and a third number of memory cells, each included in remaining block or blocks of the memory blocks, the third number being the first number minus the second number.