Patent ID: 7321255

Claim:
A voltage generating circuit for outputting, out of a plurality of generated voltages, a generated voltage corresponding to (a+b+c) bits of digital data (where a, b, and c are positive integers), wherein low order bits of the digital data include the (b+c) bits and upper order bits of the digital data include the a bits, comprising: a first selector of a first conductive type being constituted by a first conductive type MOS transistor and outputting any of generated voltages selected corresponding to the low order bits of the digital data based on the upper order bits of the digital data; 2 a second selectors of the first conductive type, each second selector being constituted by the first conductive type MOS transistors, and each second selector outputting any of the plurality of the generated voltages, based on the low order bits of the digital data, to the first selector of the first conductive type; a first selector of a second conductive type being constituted by a second conductive type MOS transistor outputting any of generated voltages selected corresponding to the low order bits of the digital data, based on the upper order bits of the digital data; and 2 a second selectors of the second conductive type, each second selector being constituted by the second conductive type MOS transistor, and each second selector outputting any of the plurality of the generated voltages, based on the low order bits of the digital data, to the first selector of the second conductive type, wherein: a generated voltage corresponding to the (a+b+c) bits of the digital data is outputted from a first node in which an output of the first selector of the first conductive type and an output of the first selector of the second conductive type are connected.