Patent ID: 7499517

Claim:
A shift register, comprising: a switch circuit having a first output terminal and a second output terminal, and input terminals for receiving an initial pulse signal and an output signal of the shift register, wherein when one of an initial pulse signal and an output signal of the shift register is at a logic low level, said switch circuit outputs a first clock signal and a second clock signal via said first output terminal of said switch circuit and said second output terminal of said switch circuit respectively; a latch circuit, having a first input terminal, a second input terminal, a first output terminal and a second output terminal, said first input terminal of said latch circuit being coupled to said first output terminal of said switch circuit, said second output terminal of said latch circuit being coupled to said second output terminal of said switch circuit, for latching one of said first clock signal and said second clock signal; and an inverter circuit, having a first input terminal, a second input terminal, and an output terminal, said first input terminal of said inverter circuit being coupled to said first output terminal of said latch circuit, said second input terminal of said inverter circuit being coupled to said second output terminal of said latch circuit, for outputting an output signal from said output terminal of said inverter circuit, said output signal having opposite phase to a signal from the first output terminal of the latch circuit which is inputted to said first input terminal of said inverter circuit; wherein said first clock signal and said initial pulse signal have the same phase, and said first clock signal and said second clock signal have the opposite phases.