Patent ID: 7979830

Claim:
A method, performed in a processor in a computer, of designing a layout of a semiconductor integrated circuit having a hard macro, comprising: acquiring circuit information of the semiconductor integrated circuit, and an admissibility condition for permitting a wiring with respect to a given region within the hard macro to avoid a malfunction of the hard macro when wirings are arranged in the given region to pass through the hard macro; searching, using said processor, N passing wirings, N being a positive integer, which pass through the given region among wirings which are arranged in the semiconductor integrated circuit; determining whether each of the N passing wirings satisfies the admissibility condition; and wiring a normal passing wiring which satisfies the admissibility condition among the N passing wirings so as to pass through the hard macro, and a defaulting passing wiring which does not satisfy the admissibility condition so as to bypass the hard macro.