Patent ID: 8736320

Claim:
A power-on reset circuit comprising: a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply, a potential of the first power supply gradually rising when power is turned on in the power-on reset circuit, the second power supply supplying a fixed electric potential; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on a potential of a power supply is applied; a bias circuit applying the bias potential depending on the potential of the power supply to the second gate, the bias circuit having a circuit structure to supply a constant current to the second-conductive-type MOS transistor when power is turned on in the power-on reset circuit, the constant current being proportional to a current supplied from the power supply, the constant current being constant in a process that the potential of the first power supply rises gradually so that the bias potential is constant in the process that the potential of the first power supply rises gradually; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.