Patent ID: 7983018

Claim:
An arrangement for securing a wafer during processing within a plasma processing system, comprising: a power supply; an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support said wafer, said ESC including a positive terminal and a negative terminal, wherein a positive high voltage is provided to said positive terminal through an RF filter and a negative high voltage is provided to said negative terminal through said RF filter; a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for determining a value of a positive load current applied to said positive terminal; a third TIA and a fourth TIA configured to measure a second set of voltages for determining a value of a negative load current applied to said negative terminal; and a program configured to adjust a bias voltage using said value of said positive load current and said value of said negative load current for balancing said first force and said second force.