Patent ID: 7576436

Claim:
A package structure, comprising: at least a chip, comprising an active surface and a plurality of bonding pads on the active surface; a passivation layer covering the active surface of the chip and exposing the bonding pads; a redistribution layer on the passivation layer and over the bonding pads of the chip, wherein the redistribution layer comprises at least a dielectric layer and a patterned metal layer, wherein the patterned metal layer comprises a plurality of first bumping pads and at least a second bumping pad, the first bumping pads are disposed around a periphery of the second bumping pad, and the patterned metal layer is electrically connected to the bonding pads; a plurality of first bumps, respectively connected to the first bumping pads; and at least a second bump, connected to the second bumping pad, wherein a size of the second bumping pad is larger than a size of one of the first bumping pads.