Patent ID: 7091071

Claim:
A semiconductor fabrication process, comprising: forming isolation trench structures in an active layer of a silicon on insulator (SOI) wafer; thinning the active layer to form a channel structure by etching the active layer selectively with respect to the isolation trenches; forming a gate dielectric overlying the channel structure; forming a gate structure overlying the gate dielectric; using the gate structure as a mask, removing exposed portions of the gate dielectric and the underlying channel structure to expose portions of a buried oxide (BOX) layer of the SOI wafer; etching through exposed portions of the BOX layer to exposed portions of a substrate bulk of the SOI wafer, wherein the presence of the isolation trench structures overlying isolation portions of the BOX prevents the isolation portions of the BOX from being removed during said etching; and epitaxially growing semiconductor source/drain structures from exposed portions of the substrate bulk, wherein adjacent semiconductor source/drain structures are isolated from one another by the isolation portions of the BOX layer.