Patent ID: 7167403

Claim:
A semiconductor storage device comprising: a memory array including a plurality of memory cells, arrayed at points of intersection between a plurality of bit lines and a plurality of word lines, said memory cells being in need of refresh for retention of data; a storage circuit for recording the word line information associated with a row address accessed during the operation in the normal mode; an encoding circuit for generating, at the time of entry from a normal mode to a preset self refresh mode, error correcting codes for data of the memory cells connected to the word line associated with the row address accessed during the operation in the normal mode prior to the time of the entry to said self refresh mode, and for writing the so generated codes in a preset storage area; an error detected circuit for detecting an error in the data of the memory cells connected to the word line selected by a refresh address; and a decoding circuit for correcting the data of the memory cell where an error has been detected.