Patent ID: 6877142

Claim:
A timing verification system for verifying timing paths in a circuit design including a plurality of interconnected devices comprising: (A) charge determining means for determining a plurality of charges at a corresponding plurality of specific nodes within a circuit, each of the plurality of charges corresponding to a specific configuration of devices and including model generation means for generating a plurality of models corresponding to said plurality of nodes, each of said plurality of models representing defining a charge within a specific configuration based on characteristics of a device in said specific configuration, each said specific configuration including at least one MOS device having: (i) a gate connected to either one of a rising voltage input or a falling voltage input; (ii) a source and a drain at a voltage which is in an opposite direction to that to which the gate is connected; and (B) delay determining means for determining delays in paths in a selected circuit design to be verified using selected ones of said plurality of charges corresponding to one of the specific configurations representative of that circuit design.