Patent ID: 7274075

Claim:
A non-volatile semiconductor memory device, comprising: a plurality of memory cell units each comprising at least one memory cell having a laminated gate structure formed of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film and source/drain diffusion layers formed in the semiconductor substrate; and a plurality of selection gate transistors each having a gate structure formed on the semiconductor substrate through a gate insulation film formed of the same layer as the gate insulation film of the memory cell and source/drain diffusion layers one of which is connected to a corresponding memory cell unit and the other of which is connected to a corresponding bit line or a source line, wherein the plurality of selection gate transistors include first selection gate transistors and second selection gate transistors disposed in confrontation with each other through contacts connected to corresponding bit lines or the source line, and a structure of the first selection gate transistors is substantially different from that of the second selection gate transistors; a channel region of each of the first selection gate transistors has an impurity concentration constant in a gate length direction at a depth from the boundary between the semiconductor substrate and the gate insulation film, and an impurity concentration distribution of the channel region of each of the first selection gate transistors is different from that of the channel region of each of the memory cells; and a channel region of each of the second selection gate transistors has a portion in which an impurity concentration is different from that of another portion in a gate length direction at the depth from the boundary between the semiconductor substrate and the gate insulation film, and an impurity concentration of one of the portions of the channel region, which has an impurity concentration higher than the other of the portions is the same as that of the channel region of each of the first selection gate transistors at the depth from the boundary between the semiconductor substrate and the gate insulation film.