Patent ID: 7071061

Claim:
A fabrication method of a non-volatile memory, the fabrication method of a non-volatile memory comprising: forming a first dielectric layer over a substrate; forming a charge trapping layer; forming a second dielectric layer; forming a plurality of stacked gate structures above the second dielectric layer, wherein each stacked gate structures further comprises a first gate and every two of the adjacent stacked gate structures comprises a gap there between; removing the second dielectric layer not covered by the stacked gate structures to expose the charge trapping layer; forming a third dielectric layer to cover a surface of the stacked gate structures and the exposed surface of the charge trapping layer; forming a second conducting layer above the substrate; removing a portion of the second conducting layer to form a plurality of second gates which each fills the gap between the stacked gate structures, and the second gates and the stacked gate structures form a column of memory cells; and forming a source region and a drain region beside two sides of the column of memory cells in the substrate.