Patent ID: 7371646

Claim:
A method of manufacturing an insulated gate type field effect transistor comprising steps of: (a) preparing a semiconductor substrate having at least a region of a first conductivity type on a side of one principal surface; (b) forming a field insulating film on the one principal surface of said semiconductor substrate, said field insulating film having an element opening corresponding to said region; (c) forming a gate insulating film on a semiconductor surface in said element opening; (d) forming a gate electrode layer on said gate insulating film; (e) forming high impurity concentration source and drain regions of a second conductivity type opposite to the first conductivity type in said first conductivity type region on both sides of said gate electrode layer, by an impurity doping process using as an impurity mask a lamination of said gate electrode layer and said gate insulating film, and said field insulating film; (f) etching an upper surface and side walls of said gate electrode layer by an isotropic etching process to make said gate electrode layer narrow and thin; and (g) forming low impurity concentration source and drain regions of the second conductivity type in said first conductivity type region on both sides of said gate electrode layer and adjacent to said high impurity concentration source region and drain region, by an impurity doping process using as an impurity mask a lamination of said narrow and thin gate electrode layer and said gate insulating film, and said field insulating film, wherein the gate electrode layer is a polycide structure, the polycide-structured gate electrode layer being isotropically-etched to be narrow and thin and used as a mask.