Patent ID: 7738308

Claim:
A memory, comprising: a redundant row-unit having one or more rows of memory cells; a plurality of memory cells arranged according to rows, wherein the rows are arranged into a plurality of row-units such that each row-unit has the same number of rows, and wherein the redundant row-unit includes the same number of rows; a plurality of SRAM repair cells corresponding on a one-to-one basis with the plurality of row-units, each SRAM repair cell operable to store a repair true or false value signal, and wherein each SRAM repair cell is adapted to store a repair false signal in response to an assertion of a reset signal; and an X decoder for addressing the rows, the X decoder adapted to respond to an address for a row-unit having a repair memory cell storing the repair true signal by addressing a unit selected from the remaining row-units and the redundant row-unit, wherein each SRAM repair memory cell is adapted to store the repair true signal in response to an assertion of a set signal and an addressing of the corresponding row-unit.