Patent ID: 8490031

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: reading physical layout data of a circuit to be manufactured into a calculation unit and performing a calculation to modify a pattern width in the physical layout data by a predetermined amount; reading into an analysis unit a physical layout after the pattern width is modified, the physical layout being output from the calculation unit, and analyzing a surface topology above a pattern that is predicted to remain with a topological step difference of at least a predetermined amount should a planarization process be performed on a planarizing film on the pattern by a quantitative calculation using, with regard to a range of interest of the physical layout, at least one of a density of patterns, a pattern width, and a peripheral length of the range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain into a correction unit, and making a correction to determine a layout of the pattern in which the topological step difference of at least the predetermined amount does not remain, wherein, in analyzing the surface topology (a) a mesh area is selected based on having a planarizing film area to pattern area ratio outside of a first predetermined limit, and (b) the selected mesh area is identified as having the topological step difference of at least the predetermined amount when an average planarizing film area to pattern area ratio for the selected mesh area and one or more adjacent mesh areas is determined to be outside of a second predetermined limit.