Patent ID: 7895407

Claim:
A multiprocessor computing system, comprising: a memory having a plurality of target code portions stored therein, including at least a first target code portion and a second target code portion; a plurality of processors arranged to execute the plurality of target code portions stored in the memory; and a controller unit arranged to control execution of the plurality of target code portions by the plurality of processors, wherein the controller unit comprises: an address space allocation unit arranged to divide a virtual address space used to address the memory into a plurality of virtual address space regions and to control execution of the plurality of target code portions to access the memory through the plurality of virtual address space regions initially according to a first memory consistency model; a shared memory detection unit arranged to detect a memory access request made in execution of the first target code portion with respect to a shared memory area in the memory which is also accessible by at least the second target code portion and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit arranged to selectively apply a memory consistency protection to enforce a second memory consistency model in relation to accesses to the shared memory area in execution of the identified group of instructions in the first target code portion, responsive to the shared memory detection unit identifying the identified group of instructions.