Patent ID: 7596656

Claim:
A memory device, comprising: a memory having a plurality of physical memory segments each having a plurality of non-volatile memory cells and organized into logical units, wherein the memory cells each have a lifetime of a finite number rewrite cycles; rewrite circuitry connectable to said memory cells whereby the memory cells can be rewritten; and a controller, wherein the controller logically accesses the memory as having a first accessible physical memory capacity and, in response to a command from a host to which the memory device is connected, subsequently logically accesses the memory as having a second accessible physical memory capacity, where the second accessible physical memory capacity is less than the first accessible physical memory capacity; wherein the controller maintains a parameter indicative of the number of rewrites the memory cells have undergone, determines an indication of an expected amount of remaining lifetime of the memory device based on a value of said parameter, and provides said indication of the expected amount of remaining lifetime to the host, and wherein said command from the host to the memory device to reduce the accessible physical memory capacity is in response to said indication of the expected amount of remaining lifetime of the memory device.