Patent ID: 7098715

Claim:
A programmable clock circuit to generate frequencies from an input clock signal having a predetermined frequency and having a rising edge and a falling edge associated with each clock cycle of the input clock signal, the circuit comprising: a counter configured to receive the input clock signal and to generate a counter signal having a frequency of M cycles for every N cycles of the input clock signal; a comparator circuit coupled to the counter to compare a count value of the counter with predetermined count values and to generate comparator signals related to the comparison; and a control circuit to generate an output clock signal based on the comparator signals to thereby select a rising edge of the output clock signal based on a rising edge or a falling edge of the input clock signal and to select a falling edge of the output clock signal based on a rising edge or a falling edge of the input clock signal; wherein the counter is a M/N:D counter where D is related to a duty cycle of the output clock signal; wherein the control circuit generates the output clock signal with a falling edge of the output clock signal based on a rising edge of the input clock signal if the comparator signals indicate that the counter has a value greater than or equal to D and less than D+M/2.