Patent ID: 8489947

Claim:
A circuit, comprising: means for supplying to a circuit-under-test (CUT) an alternating signal that is synchronous to a first clock frequency; means for capturing samples of an output signal associated with the alternating signal, the means for capturing being controlled by a capture clock signal synchronous to a second clock frequency that is coherent to the first clock frequency; means for changing a path delay, the path delay being associated with the alternating signal traveling from the means for supplying to the means for capturing; a modulo counter unit having a modulo base equal to a fraction of or an integer multiple of the number of clock cycles in a beat period, the beat period being the smallest integer number of cycles of the first clock frequency that has a time interval equal to an interval of a different integer number of cycles of the second clock frequency; and means for conveying the samples from the means for capturing to the modulo counter unit, wherein the modulo counter unit comprises a first modulo counter configured to count the samples between when a first edge is detected in the samples and when a second edge similar to the first edge is detected to derive a delay difference count, and the means for changing is configured to change the path delay at a time between when the first edge is detected and when the second edge is detected.