Patent ID: 8759891

Claim:
A semiconductor memory device having a capacitor comprising: a semiconductor substrate having a main surface; a transistor formed on the main surface of the semiconductor substrate, the transistor having a gate electrode, a source region, and a drain region; a first insulator layer formed on the main surface so as to cover the transistor; a conductor plug electrically connected to the source region or the drain region of the transistor, the conductor plug formed in the first insulator layer; a second insulator layer formed on the first insulator layer, the second insulator layer containing nitrogen; a third insulator layer formed on an upper surface of the second insulator layer; a fourth insulator layer formed on an upper surface of the third insulator layer; and a capacitor lower electrode formed on an inside wall of an opening formed in the second insulator layer, the third insulator layer and the fourth insulator layer, the capacitor lower electrode contacting the conductor plug; wherein the opening has a first portion defined by the second insulator layer, a second portion defined by the third insulator layer, and a third portion defined by the fourth insulator layer, and wherein an opening width of the second portion is larger than an opening width of the first portion, and the opening width of the second portion is larger than an opening width of the third portion.