Patent ID: 8015538

Claim:
A method in a computer-aided design system, having at least one processor and a memory, for generating a functional design model of a semiconductor structure, the method comprising: generating, in the computer-aided design system, a functional computer-simulated representation of a deep sub-collector located in a first epitaxial layer; generating, in the computer-aided design system, a functional computer-simulated representation of a doped region located in a second epitaxial layer, which is above the first epitaxial layer; generating, in the computer-aided design system, a functional computer-simulated representation of a reach-through structure penetrating from a surface of a device through the first and second epitaxial layers to the deep sub-collector; generating, in the computer-aided design system, a functional computer-simulated representation of a trench isolation structure penetrating from a surface of the device into the reach-through structure and surrounding the doped region; and generating, in the computer-aided design system, a functional computer-simulated representation of a salicide layer located on a surface of the device above and directly in contact with the doped region.