Patent ID: 8004873

Claim:
A resistance change memory device comprising: a memory cell array, which includes a plurality of first wirings, a plurality of second wirings so disposed as to cross the first wirings, and memory cells disposed at the cross points of the first and second wirings, each of the memory cells including a diode and a variable resistance element connected in series, the diode being disposed with such a polarity that anode thereof is located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring is set at a third voltage higher than the first voltage and a selected second wiring is set at the first voltage, a selected memory cell being read or written in the access state.