Patent ID: 7501676

Claim:
An array of DRAM cells, comprising: a plurality of cross-shaped active areas, each cross-shaped active area comprising a body portion comprising a centrally located drain and four arm portions located around the body portion, each cross-shaped active area spaced apart from another cross-shaped active area by a substantially uniform distance with arms of adjacent cross-shaped active areas aligned parallel to one of two perpendicular axes; a polysilicon gate area disposed over a group of adjacent arm portions of four cross-shaped active areas, each peripheral edge of the polysilicon gate area being oriented parallel to one of the two perpendicular axes; at least one capacitor of each of the cross-shaped active areas of the four cross-shaped active areas being electrically coupled to the polysilicon gate area; a buried digit line parallel to one of the two perpendicular axes and electrically coupled to the body portion of at least one cross-shaped active area; and a buried word line positioned substantially orthogonally to the buried digit line parallel to another of the two perpendicular axes and electrically coupled with the polysilicon gate area.