Patent ID: 7453107

Claim:
A semiconductor device, comprising: a substrate formed of semiconductor material; a source region formed in the substrate and doped with a first type of impurities; a drain region formed in the substrate and doped with the first type of impurities, the drain region spaced apart from the source region; a conducting region formed between the source region and the drain region and doped with the first type of impurities, the conducting region operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state; a channel region formed in the conducting region; a gate region formed in the substrate and doped with a second type of impurities, the gate region abutting the channel region; and a stress layer deposited on at least a portion of the conducting region, wherein the stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region; the semiconductor device comprises a junction field effect transistor (JFET).