Patent ID: 8492223

Claim:
A method of manufacturing a flash memory device, the method comprising: forming a dielectric layer on an active region of a substrate; forming a floating gate on the dielectric layer; forming an isolation layer in an isolation region of the substrate; forming an insulative spacer layer directly on the floating gate and on the isolation region; performing an etch back process on the spacer layer to expose at least the floating gate; forming a nitride layer comprising a first nitride layer portion that is formed on an exposed surface of the floating gate and a second nitride layer portion that is formed on an exposed surface of the isolation layer and on an exposed surface of the spacer layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer by performing a thermal treatment process on the nitride layer and then exposing the nitride layer to a mixed solution of deionized water and at least one selected from the group consisting of ammonia and peroxide maintained at a temperature of from about 40° C. to about 100° C. in order to selectively remove the nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.