Patent ID: 8036334

Claim:
A device, comprising: a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising a filter unit to filter a phase control signal to substantially reduce a false delay lock loop state and a delay unit to provide a delay line to generate said output signal, said delay unit comprising a register to control said delay line, said register being capable of shifting left and shifting right to provide a signal to control a delay operation performed by said delay unit, said delay unit further comprising a delay logic to provide a delay path to generate a synchronized output signal and a shift logic operatively coupled to said register, said shift logic to provide a force-left shift signal to said delay logic upon initialization of said delay logic, said shift logic to also provide a DLL_ON signal to said delay logic to control an operation of said delay logic, said shift logic being at least partially controlled by a filtered phase controlled signal provided by said filter unit.