Patent ID: 8719615

Claim:
A semiconductor device including a plurality of operation circuits executing operation in synchronization with a clock signal comprising: a control unit for outputting first operation control information and second operation control information for controlling operation executed by the plurality of operation circuits; a storage unit for storing first data and second data; a first operation unit operating in synchronization with the clock signal, performing operation on the first data in accordance with the first operation control information, and outputting third data; and a second operation unit operating in synchronization with the clock signal, performing operation on the second data in accordance with the second operation control information, and outputting fourth data, the first operation unit including first to M-th (M is an integer of 2 or more) operation circuits connected in series, such that an m+1-th (m is an integer equal to or greater than 1 and equal to or less than M−1) operation circuit is configured to perform operation on an operation result provided by an m-th operation circuit, delay indexes representing amounts of delays of the first to M-th operation circuits as m 1 . . . , m M (m 1 , . . ., m M are natural numbers), respectively, the second operation unit including at least an operation circuit, the delay index of which represents the amount of delay as n (n is an integer of 1 or more), wherein a delay defined based on a summation of delay indexes of the operation circuits provided in the first operation unit (m 1 + . . . +m M ) and a delay defined based on the delay index n of the operation circuits provided in the second operation unit are equal to or less than a reference value Z defined in advance based on a cycle of the clock signal.