Patent ID: 8542519

Claim:
A semiconductor memory device comprising: a first MOSFET and a second MOSFET arranged in a first direction and provided on a semiconductor substrate; a first variable resistive element provided above the first and second MOSFETs, a lower end of the first variable resistive element being connected to drains of the first and second MOSFETs; a third MOSFET and a fourth MOSFET arranged in the first direction and provided on the semiconductor substrate; a second variable resistive element provided above the third and fourth MOSFETs, a lower end of the second variable resistive element being connected to drains of the third and fourth MOSFETs; a first wiring line extending in the first direction and connected to sources of the first and second MOSFETs; a second wiring line extending in the first direction and connected to sources of the third and fourth MOSFETs; an upper electrode connecting an upper end of the first variable resistive element and an upper end of the second variable resistive element; a third wiring line extending in the first direction and connected to the upper electrode, wherein the first wiring line, the second wiring line, and the third wiring line are provided in a same layer.