Patent ID: 8743253

Claim:
A method of controlling a read address, in a solid state imaging device comprising: generating image signals in a plurality of image elements arranged in a one-dimensional or two-dimensional array; specifying address values of the image elements from which to read at least some of the image signals in digital format comprised of bits; dividing each address value into a high order address value and a low order address value; and incrementing the high-order address value using a first counter while incrementing the low-order address values using a second counter, the first counter incrementing the high-order values such that a least number of individual bits of the high-order values are toggled, the second counter incrementing the low-order values such that the individual bits of the low-order values that are toggled is less that a number of bits of the low-order values that would be toggled using either a Gray code counter or a binary code counter.