Patent ID: 6983300

Claim:
An arithmetic unit for adding a plurality of values, each value falling within the range −2 N−1 to 2 N−1 −1, to define a result, said arithmetic unit comprising: an input for receiving said plurality of values; an adder for adding said plurality of values to define a result, said result being within a first range −2 N−1 to 2 N−1 −1; circuitry for performing a round on the result to define a rounded result, wherein the rounded result falls within a third range −2 N to 2 N −1+2 (N/2)−1 ; a detector for determining if said rounded result falls within a second range −2 N−1 to 2 N−1 −1, said second range being smaller than the third range, said detector being arranged to consider only some of the bits of said rounded result; and circuitry for modifying said rounded result in so that the result output but said arithmetic unit falls within the second range.