Patent ID: 7964919

Claim:
An integrated circuit structure comprising: (a) a first dielectric layer ( 2 ) disposed on a semiconductor layer ( 8 ); (b) a first thin film resistor ( 3 ) disposed on the first dielectric layer ( 2 ); (c) a patterned first layer of conductive material (METAL 1 ) formed on a top surface of the first dielectric layer ( 2 ) and defining a first interconnect conductor ( 5 B) contacting a first contact area ( 4 ) of the first thin film resistor ( 3 ), and a second interconnect conductor ( 5 C) contacting a second contact area ( 4 ) of the first thin film resistor ( 3 ); (d) a second dielectric layer ( 7 ) formed over the first dielectric layer ( 2 ), the first thin film resistor ( 3 ), and the first and second interconnect conductors ( 5 B, 5 C); (e) a second thin film resistor ( 10 ) disposed on the second dielectric layer ( 7 ); (f) a third dielectric layer ( 12 ) disposed on the second dielectric layer ( 7 ) and the second thin film resistor ( 10 ); and (g) a patterned second layer of conductive material (METAL 2 ) formed on a top surface of the third dielectric layer ( 12 ) and defining a third interconnect conductor ( 23 ) extending through first openings ( 16 , 18 ) in the second and third dielectric layers ( 7 , 12 ) to contact the first interconnect conductor ( 5 B), a fourth interconnect conductor ( 23 A) extending through second openings ( 16 , 18 ) in the second and third dielectric layers ( 7 , 12 ) to contact the second interconnect conductor ( 5 C), and a fifth interconnect conductor ( 24 ) extending through a third opening in the third dielectric layer ( 12 ) to contact a first contact area (left end of 10 ) of the second thin film resistor ( 10 ).