Patent ID: 8671250

Claim:
A data storage device comprising: a non-volatile memory comprising a plurality of memory segments; and control circuitry operable to: receive a write command comprising a first logical block address (LBA) and first user data, and a second LBA and second user data; map the first LBA to a first physical block address (PBA) for addressing a first memory segment; map the second LBA to a second PBA for addressing a second memory segment; generate first redundancy in response to the first user data; generate second redundancy in response to the second user data; generate parity data in response to the first and second user data; generate third redundancy in response to: at least one of the first LBA and the first PBA; and at least one of the second LBA and the second PBA; and write the first and second user data and parity data to the non-volatile memory and write the first, second, and third redundancy to the non-volatile memory.