Patent ID: 7666578

Claim:
A method for integrated circuit fabrication, comprising: patterning a first photoresist layer to form a photoresist pattern over a substrate; transferring the photoresist pattern to a hardmask layer underlying the photoresist layer and a temporary layer underlying the hardmask layer; forming spacers on sidewalls of elements in the patterned hardmask and temporary layers; depositing a second photoresist layer over the spacers and the patterned hardmask and temporary layers; patterning the second photoresist layer to expose some parts of the patterned hardmask and temporary layers and to expose some of the spacers while leaving photoresist directly over other parts of the patterned hardmask and temporary layers and over others of the spacers; subsequently preferentially removing the exposed parts of the patterned hardmask and temporary layers; and preferentially removing the second photoresist layer.