Patent ID: 7904499

Claim:
A carry generation tree for a carry look-ahead binary adder, comprising: N stages of one or more operators, and one or more reducers, wherein N is greater than or equal to 2 and: a first of the stages receives binary outputs from a series of binary adders; a last of the stages produces a carry out signal representing a carry state of the series of binary adders; each of the one or more operators combines a plurality of inputs to produce at least two outputs, and each of the one or more operators in a given stage, except for the first stage, does not receive signals from more than one other of the one or more operators in an immediately preceding stage; each of the one or more reducers combines a plurality of inputs to produce a single output in any given stage and each of the one or more reducers in a given stage, except the first stage, receives signals from one of the one or more operators and one of the one or more reducers in an immediately preceding stage.