Patent ID: 7170129

Claim:
A non-volatile memory, comprising: a substrate; a stacked structure, disposed over the substrate, wherein the stacked structure comprises a gate dielectric layer at the bottom and a control gate above it; a pair of charge storage layers, respectively covering a portion of top and sidewalls of the stacked structure, wherein a first gap exists between each of the charge storage layers; a first dielectric layer, disposed between the top of the stacked structure and each of the charge storage layers; a second dielectric layer, disposed between the sidewall of the stacked structure and each of the charge storage layers; a third dielectric layer, disposed between each of the charge storage layers and the substrate; a pair of assist gates, disposed over the substrate at two sides of the pair of charge storage layers, and separated from each of the charge storage layers by a second sap; and a fourth dielectric layer, disposed between each of the assist gates and the substrate.