Patent ID: 7890728

Claim:
A memory interface device for controlling memory access between a memory write unit that writes data into a memory and a memory readout unit that reads the data from the memory, the memory write unit being in compliance with a memory write procedure in which each time data is written into a memory by a predetermined unit amount, it is confirmed that readout of the data from the memory has been completed, and then the next memory write procedure of the data into the memory is performed, the memory interface device comprising: write detection means for detecting a memory write procedure in which the memory write unit writes the predetermined unit amount of the data into the memory; signal generation means for generating, upon detection of the writing of the predetermined unit amount of the data by the write detection means, a readout completion notice signal that notifies the memory write unit, and thereby confirms, that the readout of the data from the memory by the memory readout unit has been completed so that the memory write unit proceeds to perform a next memory write procedure of the data into the memory; data storage amount measurement means for measuring an amount of the data stored in the memory during the memory write procedures; memory readout control means for generating an interrupt signal to temporarily stop the generation of the readout completion notice signal by the signal generation means when the stored data amount measured by the data storage amount measurement means reaches a predetermined readout start storage amount, and for outputting the interrupt signal to the memory readout unit so that the memory readout unit reads out all of the data stored in the memory in accordance with the stored data amount measured by the data storage amount measurement means; and a timer that counts a period in which writing of the predetermined unit amount of the data into the memory by the memory write unit is discontinued and that outputs a timeout signal to the memory readout control means when a value of the period count reaches a predetermined timer period, the memory readout control means generating and outputting the interrupt signal to the memory readout unit even when the memory readout control means receives the timeout signal output from the timer.