Patent ID: 8026584

Claim:
A semiconductor package, comprising: a first semiconductor package comprising a first circuit board including a first through hole therein, a first conductor formed on a sidewall of the first through hole, a first semiconductor chip including a first chip pad mounted on the first circuit board, a second semiconductor chip including a second chip pad formed on the first semiconductor chip, a penetration electrode electrically connecting the first semiconductor chip with the second semiconductor chip, a first solder ball disposed in the first through hole to connect the first conductor with the first chip pad, and a sealing resin encapsulating the first circuit board, the first semiconductor chip, and the second semiconductor chip; and a second semiconductor package comprising a second circuit board including a second through hole therein, a second conductor formed on a sidewall of the second through hole, a third semiconductor chip including a third chip pad mounted on the second circuit board, a fourth semiconductor chip including a fourth chip pad formed on the third semiconductor chip, a conductive member electrically connecting the third semiconductor chip with the fourth semiconductor chip, a second solder ball disposed in the second through hole to connect the second conductor with the third chip pad, and a sealing resin encapsulating the second circuit board, the third semiconductor chip, and the fourth semiconductor chip, wherein the second semiconductor package is formed on the first semiconductor package and electrically connected with the first semiconductor package through the second solder ball.