Patent ID: 7327018

Claim:
A chip package structure, comprising: a package substrate comprising: a first substrate having at least a first circuit layer disposed on a surface thereof; at least a dielectric layer disposed on the first substrate and covering the first circuit layer, wherein the dielectric layer has an opening exposing the first substrate; a third circuit layer formed on an upper surface of the dielectric layer, an interposer comprising a second substrate and a second circuit layer formed on an upper surface of the second substrate, wherein the interposer is disposed in the opening of the dielectric layer and on the exposed first substrate, the second circuit layer further comprises a plurality of bonding pads, and a plurality of traces such that each trace is electrically connected to one of the bonding pads, wherein the second circuit layer of the interposer is physically and electrically connected to the third circuit layer, the third circuit layer is electrically connected to the first circuit layer of the first substrate and the second substrate and the first substrate are made of different materials; and a chip having a plurality of bumps thereon, disposed on the interposer such that the bumps are connected to corresponding bonding pads of the second circuit layer.