Patent ID: 8484432

Claim:
A memory system comprising: a non-volatile memory including a plurality of blocks, each one of the plurality of blocks being a data erase unit; and a controller configured to assign one part of the plurality of blocks to a main memory area and to assign another part of the plurality of blocks to a cache area, wherein each block is divided into multiple management units, a plurality of data stored in the main memory area are managed with logical addresses, each logical address representing a first management unit, a plurality of data stored in the cache area are managed with logical addresses, each logical address representing a second management unit, the size of each second management unit is smaller than the size of each first management unit and the size of each of the first and second management units is smaller than the size of the data erase unit, and the controller dynamically changes the number of the blocks assigned to the main memory area and the number of the blocks assigned to the cache area in the non-volatile memory.