Patent ID: 8633592

Claim:
A method comprising: constructing one or more interconnect structures between an integrated circuit (IC) chip and a substrate, wherein each interconnect structures comprises a plurality of materials; wherein constructing each interconnect structure comprises: dividing the interconnect structure into n sections; giving all the n sections a first material; recording a current stress level corresponding to the interconnect structure; and iteratively: for each of m sections that currently have the first material, where m≦n: assigning the section a second material; and determining the current stress level corresponding to the interconnect structure; selecting, from m determined stress levels, a lowest stress level; if the selected lowest stress level is less than the recorded stress level, then: giving a section from the m sections that corresponds to the selected lowest stress level the second material; and recording the selected lowest stress level; until the selected lowest stress level is greater than or equal to the recorded stress level.