Patent ID: 8120116

Claim:
A semiconductor device including a first p-type MISFET, a first n-type MISFET, a second p-type MISFET, and a second n-type MISFET, comprising: a semiconductor substrate having a main surface; a first p-type impurity region formed in said main surface; a first n-type impurity region formed in said main surface; a second p-type impurity region formed in said main surface; a second n-type impurity region formed in said main surface; a first gate electrode formed over said first p-type impurity region and said first n-type impurity region; a second gate electrode formed over said second p-type impurity region and said second n-type impurity region; and an insulator film formed over said first p-type impurity region, said first n-type impurity region, said second p-type impurity region, said second n-type impurity region, said first gate electrode, and said second gate electrode, wherein said first p-type MISFET includes said first p-type impurity region and said first gate electrode, wherein said first n-type MISFET includes said first n-type impurity region and said first gate electrode, wherein said second p-type MISFET includes said second p-type impurity region and said second gate electrode, wherein said second n-type MISFET includes said second n-type impurity region and said second gate electrode, wherein said insulator film has a shared contact hole reaching both said first gate electrode and said second p-type impurity region, wherein said first gate electrode includes first, second, third, and fourth sidewalls, said first and third sidewalls being located opposite to each other, said second and fourth sidewalls being located opposite to each other, wherein, in a planar view, said second sidewall in a portion that said shared contact hole of said first gate electrode reaches is shifted toward sides of said third and fourth sidewalls from a virtual extended line of said first sidewall in portions located on said channel formation regions of said first p-type MISFET and said first n-type MISFET, and wherein, in a planar view, a center line of a line width in the portion that said shared contact hole of said first gate electrode reaches is located while shifted with respect to a center line of a line width in the portion located on said channel formation regions of said first p-type MISFET and said first n-type MISFET.