Patent ID: 7728390

Claim:
A memory array comprising: a first patterned set of parallel conductive lines on an underlying layer; at least one patterned interlevel conductor on the underlying layer; a first barrier layer on the first patterned set of parallel conductive lines; a doped polysilicon layer on the first barrier layer; an antifuse layer on the doped polysilicon layer; a second barrier layer on the antifuse layer; a plurality of patterned columnar stacks of layers having one end in contact with the first patterned set of parallel conductive lines, the patterned columnar stack of layers comprising the second barrier layer, the antifuse layer, the doped polysilicon layer, and the first barrier layer; a first dielectric between adjacent ones of the plurality of patterned columnar stacks of layers, the first dielectric comprising a first material; a second dielectric between adjacent ones of the first patterned set of parallel conductive lines and also in contact with the first dielectric layer, the second dielectric comprising the first material; and a via recess for an interlevel conductor extending at least through the first dielectric and the second dielectric to a conductor formed beneath the underlying layer, and contacting a portion of the at least one patterned interlevel conductor and insulated from the second barrier layer by a portion of the second dielectric layer.