Patent ID: 7420384

Claim:
A self-testing system on a chip comprises: programmable section; and a plurality of high-speed interfaces, wherein, to facilitate testing of the plurality of high-speed interfaces, the programmable section is programmed to provide: testing of one of the plurality of high-speed interfaces at the first level testing via the programmable section, wherein the first level testing tests performance characteristics of the one of the plurality of high-speed interfaces to produce tested performance characteristics; evaluating the tested performance characteristics in accordance with prescribed performance characteristics of one of a plurality of standards to determine whether the one of the plurality of high-speed interfaces conforms with the one of the plurality of standards; when the one of the plurality of high-speed interfaces conforms with the one of the plurality of standards, facilitate configuring the plurality of high-speed interfaces for a second level testing, wherein the first level testing is more stringent than the second level testing; and facilitate testing remaining ones of the plurality of high-speed interfaces in accordance with the second level testing.