Patent ID: 7584393

Claim:
A scan test circuit, comprising: a clock control circuit generating a clock signal; a scan control circuit generating a scan shift enable signal; a clock buffer circuit section having clock buffer circuits cascade-connected to form a clock tree circuit to drive the clock signal; a replaced cell provided to replace one of the clock buffer circuits in the clock tree circuit, the replaced cell receiving the scan shift enable signal output from the scan control circuit and the clock signal output from the clock buffer circuit section and outputting a first clock signal and a first scan shift enable signal synchronized with the first clock signal; and a scan circuit receiving the first scan shift enable signal synchronized with the first clock signal output from the replaced cell, the first clock signal, a data signal, and a scan input signal, and outputting a scan test signal, wherein the replaced cell includes a clock buffer circuit driving the clock signal from the first clock control circuit and outputting the first clock signal to the scan circuit, and a flip-flop circuit receiving the scan shift enable signal and the clock signal from the clock control circuit, latching the scan shift enable signal to store and to update in the flip-flop circuit, and providing the scan circuit with the first scan shift enable signal.