Patent ID: 7825711

Claim:
A clock circuit for generating a clock signal, comprising: a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, the DLL configured to adjust the phase relationship of the output clock signal in accordance with a phase difference between a buffered reference clock signal and a DLL feedback signal, the buffered reference signal based on the reference clock signal and the DLL feedback signal based on the output clock signal; a clock tree circuit coupled to the DLL and configured, when enabled, to distribute the output clock signal from the DLL in response to receiving the same; a clock jitter feedback circuit coupled to the clock tree and the DLL, the clock jitter feedback circuit configured to synchronize a clock jitter feedback signal and the DLL feedback signal and further configured to provide the clock jitter feedback signal to the DLL for synchronization with the buffered reference clock signal, the clock jitter feedback signal based on and generated in response to receiving a distributed output clock signal from the clock tree circuit.