Patent ID: 7519772

Claim:
A method of updating a cache in an integrated circuit, the integrated circuit incorporating the cache, a memory, a processor connected to the cache, and a memory interface connected to the cache, memory and processor, the method comprising the steps of: (a) following a cache miss, requesting, using the processor, first data associated with the cache miss from a first address; (b) in response to the request, fetching, using the memory interface, the first data and second data from the memory, the second data being stored in the memory adjacent the first data; (c) updating the cache with the first and second data via the memory interface; and (d) updating the cache to mark the updated first and second data as valid, wherein the cache includes instruction and data cache, the method including performing arbitration between instruction cache misses and data cache misses such that steps (a)-(d) are performed for data cache misses before instruction cache misses.