Patent ID: 7839701

Claim:
A circuit for controlling the source node within a dynamic memory device, comprising: at least one source node signal line coupled to a source of transistors within a latched sense amplifier of a dynamic memory device; a drain comprising source transistor coupled to said source node signal line in a self-reverse biased configuration to reduce standby mode leakage current; and a control signal coupled to a gate of said source transistor which activates said source transistor when accessing a cell within said dynamic memory circuit in response to an extended voltage level, which is outside the range of V SS to V DD , to drive said source node signal line without a voltage threshold drop; wherein transistors to which said source of transistors is coupled, in said latched sense amplifier, are NMOS transistors while said source transistor is a PMOS transistor, or are PMOS transistors while said source transistor is a NMOS transistor; said extended voltage level driving said gate of said source transistor is required for overcoming said self-reverse biasing when accessing a cell within said dynamic memory circuit.