Patent ID: 8178930

Claim:
A MOS transistor comprising: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, opposite said first conductivity type and having a net impurity concentration higher than that of said substrate, disposed in a first surface portion of said substrate; a drain region of said second conductivity type, disposed in a second surface portion of said substrate and comprising a relatively lightly doped region contiguous with a relatively heavily doped region; a channel region, disposed in a third surface portion of said substrate separating said source region from said drain region; a gate dielectric layer located on the surface of said substrate between said source and drain regions, said gate dielectric film overlying said channel region; a gate electrode located upon said gate dielectric layer; a plug region of said first conductivity type comprising a portion extending into said substrate, said portion being surrounded by said lightly doped region and contiguous with said heavily doped region, said heavily doped region extending into said substrate at least as far as said portion of said plug region, said plug region aligned with said gate dielectric and gate electrode.