Patent ID: 7984240

Claim:
An apparatus comprising: a first memory including a first memory address space; a second memory including a second memory address space that is distinct from the first memory address space, wherein the second memory is operable to store data in the second memory address space in a compressed format and in an uncompressed format; a processor directly coupled via a first connection to the first memory, wherein the processor includes a first cache and a first memory management unit, the first memory management unit configured to: receive a first command from the processor that is associated with an operation involving the first memory; and execute the first command to map first data in the first memory address space and not in the second memory address space; a memory expander microchip coupled to the processor via a second connection and to the second memory via a third connection, the memory expander microchip including a second memory management unit configured to: receive a second command from the processor that is associated with an operation involving the second memory, and wherein the second memory management unit is configured to execute the second command to map second data associated with the second command in the second memory address space.