Patent ID: 8778750

Claim:
A method for fabricating a complementary metal-oxide semiconductor (CMOS) device, the method comprising the steps of: providing a wafer; using shallow trench isolation (STI) to form at least one active area in the wafer by forming STI regions in the wafer that define the active area; depositing a silicon oxide layer onto the wafer covering the active area; depositing a first high-k material onto the silicon oxide layer; selectively removing portions of the silicon oxide layer and the first high-k material exposing a surface of the wafer, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and the silicon oxide layer and the first high-k material are removed from over one or more second regions of the active area; depositing a second high-k material onto the first high-k material over the one or more first regions of the active area and onto the surface of the wafer in the one or more second regions of the active area, wherein a combination of the first high-k material and the second high-k material forms a multilayer gate dielectric over the one or more first regions of the active area and the second high-k material forms a single layer gate dielectric over the one or more second regions of the active area; and forming gates in the active area over i) the multilayer gate dielectric formed from the combination of the first high-k material and the second high-k material and ii) the single layer gate dielectric formed from the second high-k material, such that the active area will contain at least one multilayer, thick gate dielectric device and at least one single layer, thin gate dielectric device.