Patent ID: 8086974

Claim:
A hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL), wherein said fractional-N PLL comprises: a first circuit located on an integrated circuit, the first circuit including: a voltage controlled oscillator for generating a periodic output signal; a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator; a frequency divider in a feedback path for modifying a frequency of the periodic output signal; a first multiplexer; and a first random number generator; and a second circuit including: a second multiplexer; and a second random number generator operatively coupled to the first random number generator, a common signal line coupled to an input of the first random number generator, and/or the frequency divider; wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit.