Patent ID: 7414553

Claim:
A method comprising: (a) supplying a first high calibration voltage onto an input lead of an integrating analog-to-digital converter (IADC) and obtaining a first counter value, wherein the first counter value is a counter value output by a counter in the IADC; (b) determining an offset between the first counter value and a high desired ADC output value that is to be output from the IADC when the first high calibration voltage is present on the input lead; (c) supplying a second low calibration voltage onto the input lead and obtaining a second counter value from the counter value from the counter, wherein the second low calibration voltage is a voltage that is to be converted by the IADC into a low desired ADC output value; (d) using the second counter value to determine a scaling factor; (e) receiving a measurement voltage onto the input lead and obtaining a third counter value; and (f) using the offset and the scaling factor to convert the third counter value into a measurement ADC output value, wherein if the measurement voltage is equal to the high desired ADC output value, and wherein if the measurement voltage is equal to the second low calibration voltage then the measurement ADC output value is equal to the low desired ADC output value.