Patent ID: 8479014

Claim:
A method of enhancing a microprocessor which comprises a register-file and a first cache, comprising the steps of: embedding a symmetric encryption/decryption hardware into the microprocessor; embedding a symmetric key into the microprocessor for the encryption/decryption hardware, which is configured to be known only to a manufacturer of the microprocessor; embedding a second cache into the microprocessor, which is configured to be inaccessible from outside of the microprocessor, and unable to write-back or write-through to a memory outside of the microprocessor; adding an address translation table, which translates addresses of the first cache to addresses of the second cache; and adding a key selector which is configured to select from the symmetric key and an output of the symmetric encryption/decryption hardware; wherein when fetching an encrypted program from the memory, the encrypted program is decrypted using the symmetric encryption/decryption hardware and stored in the first cache after decryption, and then written to the second cache from the first cache using the address translation table, and garbage instructions are set to an area of the first cache such that when writing-back or writing-through to the memory, the garbage instructions in the area of the first cache are written to the memory.