Patent ID: 7476941

Claim:
A semiconductor integrated circuit, comprising: a substrate; first and second device regions defined on said substrate by a device isolation region; an n-channel MOS transistor formed on said first device region; and a p-channel MOS transistor formed in said second device region; said n-channel MOS transistor comprising: a first gate electrode doped to n-type and formed on said first device region in correspondence to a channel region of said n-channel MOS transistor via a first gate insulation film, said first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof; source and drain regions of n-type formed in said first device region at respective lateral sides of said first gate electrode, said p-channel MOS transistor comprising: a second gate electrode doped to p-type and formed in said second device region in correspondence to a channel region of said p-channel MOS transistor, said second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof; and source and drain regions of p-type formed in said second device region at respective lateral sides of said second gate electrode, wherein there is provided a stressor film on said substrate over said first and second device regions such that said stressor film covers said first gate electrode in said first device region including said sidewall insulation films thereof and such that said stressor film covers said second gate electrode in said second device region including said sidewall insulation films thereof, said stressor film having a first film thickness in a first part of said stressor film located in the vicinity of a base part of said second gate electrode and a second film thickness in a second part of said stressor film located outside of said first part, said first film thickness being smaller than a second film thickness.