Patent ID: 8743702

Claim:
A test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a packet library that stores, in each of a plurality of memory banks corresponding to a plurality of protocols, i) channel information indicating one of the plurality of channels and ii) command sequences for generating packets according to the protocol corresponding to the memory bank, such that command sequences for generating packets of the same type are stored at the same address in each of the plurality of memory banks; an upper sequencer that sequentially designates packets to be transmitted to and from the device under test and designates one of the memory banks for each of the designated packets; a lower sequencer that reads, from the memory banks designated by the upper sequencer, command sequences corresponding to the packets designated by the upper sequencer; and a channel selecting section that selects, from the plurality of channels, which channel each of the packets is to be transmitted through, based on the channel information stored in the memory bank from which the command sequence for generating the packet is read by the lower sequencer.