Patent ID: 7490257

Claim:
A clock distributor circuit, comprising: a first synchronous circuit for receiving a first data signal and outputting the first data signal synchronized with a first gated clock signal as a first output signal; a first clock generating circuit for receiving a first clock enable signal and generating the first gated clock signal in response to the first clock enable signal, the first gated clock signal being supplied to the first synchronous circuit; a first delay circuit for adjusting a timing at which the first clock enable signal is received by the first clock generating circuit; a second synchronous circuit for receiving a second data signal and outputting the second data signal synchronized with a second gated clock signal as a second output signal; a second clock generating circuit for receiving a second clock enable signal and generating the second gated clock signal, in response to the second clock enable signal, the second gated clock signal being supplied to the second synchronous circuit; and a second delay circuit for receiving the second clock enable signal and providing the second clock generating circuit with the second clock enable signal.