Patent ID: 8879727

Claim:
A device comprising: an integrated circuit comprising a block cipher circuit, the integrated circuit configured to selectively perform encryption and decryption using the block cipher circuit, the block cipher circuit comprising a processing pipeline, the processing pipeline comprising a plurality of round circuits that are arranged in a pipelined sequence of operatively adjacent round circuits, the round circuits for simultaneously performing rounds of encryption/decryption, and wherein the block cipher circuit is configured to use the same round circuits for both encryption and decryption; wherein the processing pipeline is configured to (1) receive data for encryption/decryption and meta-information, wherein N rounds of encryption/decryption are required to complete the encryption/decryption of the received data, the meta-information corresponding to the data for encryption/decryption and comprising a plurality of parameters, the parameters comprising (i) data indicative of whether encryption or decryption is to be performed, (ii) a round key, and (iii) a current round index, and (2) pass the data for encryption/decryption and its corresponding meta-information through the round circuits of the pipelined sequence starting from a first of the round circuits in the pipelined sequence and proceeding from round circuit to operatively adjacent round circuit within the pipelined sequence such that the meta-information corresponding to the data for encryption/decryption accompanies its corresponding data for encryption/decryption through the processing pipeline; wherein the processing pipeline comprises N round circuits to provide full pipelining of the encryption/decryption such that no round circuit in the processing pipeline is dependent upon an output of a round circuit of a subsequent round in the processing pipeline for its input or processing operations; wherein each round circuit is configured to (1) receive the data for encryption/decryption and its accompanying meta-information and (2) perform a round of encryption/decryption on the received data in accordance with the parameters of the accompanying meta-information; and wherein the processing pipeline is further configured to allow each round circuit to operate simultaneously on its received data in accordance with different parameters relative to other round circuits in the processing pipeline.