Patent ID: 8082139

Claim:
A method of simulating an electronic system in a high level modeling system (HLMS), the method comprising: selecting a design block of the electronic system; selecting a plurality of signals of the electronic system, the signals including at least one internal signal of the design block that is not a member of a plurality of ports of the design block; wherein the selecting of the design block includes generating a co-simulation block for the design block and replacing the design block in the HLMS with the co-simulation block; creating a respective extra port on the selected design block for each of the at least one internal signal in response to the selecting of the at least one internal signal; automatically generating a hardware realization of the design block; wherein the hardware realization of the design block includes each respective extra port and the plurality of ports of the design block; mapping each extra port and each of the ports of the design block to corresponding locations in a memory in a hardware-based co-simulation platform, wherein the memory is external to the hardware realization of the design block; connecting the memory location corresponding to each respective extra port and each of the ports of the design block to a signal monitor on a software-based co-simulation platform via a software signal; simulating the electronic system in the HLMS, which includes the hardware-based co-simulation platform and the software-based co-simulation platform, wherein the simulating of the electronic system includes emulating the design block in the hardware-based co-simulation platform using the hardware realization of the design block; wherein the co-simulation block is included in the software based co-simulation platform; wherein the simulating further includes: writing by the hardware realization of the design block, a respective first sequence of values to a corresponding location in the memory and a respective second sequence of values to a corresponding location in the memory, the respective first sequence of values representative of the at least one internal signal, and the respective second sequence of values representative of a signal of a port of the design block; reading by the co-simulation block the respective first sequence of values from the corresponding locations in the memory; and displaying the respective first sequence of values by the signal monitor.