Patent ID: 8564356

Claim:
A signal calibration circuit, comprising: a signal manager circuit configured to receive an externally supplied signal varying between a first logic level and a second logic level, the signal manager circuit outputting a delayed internal signal having a frequency corresponding to a frequency of the externally supplied signal and varying between the first logic level and the second logic level; a signal register circuit configured to receive the delayed internal signal from the signal manager circuit, the signal register circuit sampling a logic level of the externally supplied signal and outputting the sampled logic level of the externally supplied signal at an active edge of the delayed internal signal; and a delay generator circuit configured to receive the sampled logic level of the externally supplied signal and output a phase adjustment signal; wherein the signal manager circuit is further configured to adjust an amount of delay between an active edge of the externally supplied signal and an active edge of the delayed internal signal based on the sampled logic level of the received externally supplied signal, the delayed internal signal providing a feedback signal for the signal manager circuit.