Patent ID: 7949982

Claim:
A semiconductor integrated circuit design system comprising: a placement section configured to conduct placement of cells based on a net list and a cell library; a routing section configured to make routing between the cells based on the net list and the cell library; a layout topology analyzing section configured to evaluate fabrication easiness of a layout pattern, the placement of the cells and the routing between the cells are thus made in the layout pattern, by using a layout fabrication easiness evaluation indicator including a relationship between a predetermined pattern and an effect extent of the predetermined pattern to a yield; a shape and position coordinate extracting section configured to extract a shape and a position coordinate of the layout pattern and prepare first layout pattern data based on the shape and the position coordinate thus extracted; a dimension control rank establishing section configured to establish a dimension control rank to be given to the layout pattern which is indicative of a level of detail of dimension control, by using the net list and the cell library; a connection-permitted pattern extracting section configured to detect circuit information to have equal potential and extract connection-permitted patterns which are permitted to connect to each other in the layout pattern, by using the net list and the cell library; a disconnection-permitted pattern extracting section configured to extract disconnection-permitted patterns which exercise no effect on a circuit operation even when disconnected in the layout pattern, by using the net list and the cell library; a multicut via extracting section configured to extract a multicut via which suffices when connection is made to at least one via thereof in the layout pattern, by using the net list and the cell library; an OPC conducting section configured to conduct OPC (Optical Proximity Correction) processing on the first layout pattern data with a precision according to the dimension control rank, add a correction pattern to the layout pattern, and prepare second layout pattern data based on the layout pattern which the correction pattern is thus added to; and a lithography checking section configured to conduct LRC (Lithography Rule Check) processing on the second layout pattern data with a precision according to the dimension control rank, judge a detected error part either as a false error when the detected error part is included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, or as a true error when the detected error part is not included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, and issues a pattern correction instruction to correct the error part when the error part is judged as the true error.