Patent ID: 8451161

Claim:
A method of designing a circuit for an N-bit stage having L=2 N levels of a pipeline ADC, the circuit including: an operational amplifier; a first feedback capacitor having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal to a first input voltage and on a second clock signal to an output of the operational amplifier; a second feedback capacitor having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal to the output of the operational amplifier; and a plurality of K sampling capacitors, each sampling capacitor having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage and on the second clock signal to one of a positive and a negative reference voltage dependent on a quantised value of an analog input signal, the method comprising the steps of: for a given reference scaling factor H, determining a total capacitance value Cr of the plurality of K sampling capacitors and a capacitance value C f1 of the first feedback capacitor according to a relationship C f ⁢ ⁢ 1 = C r ⁡ ( HL K - 1 ) ; and for a given stage gain G, determining a capacitance value C f2 of the second feedback capacitor according to a relationship C f ⁢ ⁢ 2 = C r - C f ⁢ ⁢ 1 G - C f ⁢ ⁢ 1 .