Patent ID: 7583705

Claim:
A system for synchronizing clocks across a communication link having a master clock on a master side and a slave clock on a slave side, the system comprising: a master-side expected preamble module configured to provide a synchronization data pattern expected by the slave side; a master-side counter module configured to count a predetermined number of master clock periods to form an interval which is expected by the slave side between synchronization signals; a master-side buffer module configured to queue data including the expected preamble for transmission across the link, and to initiate transmission of the expected synchronization pattern after an interval from a previous synchronization pattern determined by the master clock counter module; a master-side modem module configured to modulate a synchronization signal reflecting the synchronization data pattern received from the master-side buffer module; a transmitter module configured to effect transmission across the communication link of the synchronization signal provided by the master-side modem module; a receiver module configured to receive transmissions from the transmitter module; a slave clock module configured to provide a controllable clock output at a slave clock rate and having a slave clock period; a slave-side modem module configured to demodulate signals from the receiver module; a slave-side expected preamble module configured to provide an expected synchronization data signal comparable to the synchronization signal expected from the transmitter; a slave-side counter module configured to determine an expected receipt time for each synchronization signal by counting an expected number of clock cycles of the slave clock; a burst correlator module configured to compare signals received from the slave-side modem with the expected synchronization data signal from the slave-side expected preamble module to determine the synchronization signal receipt time in terms of slave clock periods, the burst correlator module including a correlator submodule configured to provide a first correlation digital output at a sample rate of n times the slave clock rate, the first correlation digital output producing an identifiable best correlation sample indicating a sample time reflective of a closest match between the synchronization signal and the expected synchronization signal, an interpolator submodule configured to evaluate samples of the correlation digital output around the best correlation sample and to provide a plurality of interpolator outputs reflecting a synchronization signal receipt time to an interpolator resolution which is less than a sample period of 1/n slave clock periods, and a slave clock error generator submodule to provide a slave clock error signal from a difference between the determined synchronization signal receipt time and the expected synchronization signal receipt time; and a loop filter module configured to filter the slave clock error signal and apply the filtered signal to control the slave clock.