Patent ID: 8418008

Claim:
A scan clock modifier of an integrated circuit configured to receive a single test scan clock signal and scan clock control signals from test equipment for applying a test block to said integrated circuit, comprising: logic circuitry configured to receive said test scan clock signal and a first scan clock control signal from said test equipment and provide at least one selected clock signal based on said test scan clock signal, a modified test scan clock signal and said first scan clock control signal, said logic circuitry further configured to hold a state of said test scan clock signal to provide said modified test scan clock signal; and comparison logic configured to receive at least one other scan clock control signal from said test equipment and provide a single scan clock signal based on said at least one selected clock signal and said at least one other scan clock control signal, wherein said first scan clock control signal and said at least one other scan clock control signal are different scan clock control signals, wherein said single scan clock signal is derived from a single clock signal received from said test equipment, wherein said single scan clock signal has a frequency that is variable based on values of said first scan clock control signal and said at least one other scan clock control signal.