Patent ID: 7251191

Claim:
A method for controlling timing for data output of a synchronous memory device, the method comprising the step of: varying the timing of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous memory device, wherein the varying step is dependent on the CAS latency having an odd number or an even number, the varying step includes: delivering directly the internal read command of the synchronous memory device from an external device at a first time point when the internal read command corresponds to the CAS latency having an odd number defined by 2N+1 (where N=0, 1, 2, . . . ); and delaying the internal read command of the synchronous memory device from the external device at a second time point when the internal read command corresponds to the CAS latency having an even number defined by 2N+2 in which the first and second time points are substantially identical when the delivering and delaying steps share a common N value.