Patent ID: 7380187

Claim:
A boundary scan tester for a logic device, the boundary scan tester comprising: a boundary scan register coupled between core logic circuitry and I/O pins of the logic device, the boundary scan register storing a decompressed vector to be applied to the logic device and storing a test response received from the logic device; a derived boundary scan register for shifting in and storing a compressed test vector and for storing and shifting out a compressed test response; a data decompressor having an input coupled to an output of the derived boundary scan register and an output coupled to an input of the boundary scan register, the data decompressor decompressing the compressed test vector stored in the derived boundary scan register to produce the decompressed test vector, and supplying the decompressed test vector to the boundary scan register; and a data compressor having an input coupled to an output of the boundary scan register and an output coupled to an input of the derived boundary scan register, the data compressor compressing the test response stored in the boundary scan register to produce the compressed test response, and supplying the compressed test response to the derived boundary scan register.