Patent ID: 7970128

Claim:
A method executable by computing hardware for producing a hashed output of an input message according to any of a plurality of hash algorithms, each of the plurality of hash algorithms having an associated bit width such that at least one of the algorithms is associated with a first bit width and at least one of the algorithms is associated with a second bit width greater than the first bit width, wherein the computing hardware comprises a first plurality of registers and a second plurality of registers, the method comprising the steps of: receiving, at the computing hardware, the input message and a selected one of the plurality of hash algorithms; storing at least a portion of the input message in the first plurality of registers, wherein each of the first plurality of registers has a bit width equal to the first bit width; if the selected one of the plurality of hash algorithms is associated with the second bit width having the second bit width greater than the first bit width, storing a remainder of the input message in the second plurality of registers, wherein each of the second plurality of registers has a bit width equal to the first bit width, and otherwise bypassing the second plurality of registers; and computing, by the computing hardware, the hashed output according to the selected one of the plurality of hash algorithms by performing operations on only the first plurality of registers if the selected hash algorithm is associated with the first bit width and by performing operations on both the first and second pluralities of registers if the selected hash algorithm is associated with the second bit width that is greater than the first bit width.