Patent ID: 7634040

Claim:
A loop latency compensated phase-locked loop (PLL) comprising: an analog-to-digital converter (ADC) receiving an analog input signal and an output clock to generate a digital signal; a phase detector coupled to the ADC, receiving the digital signal to generate an estimated phase error; a loop filter coupled to the phase detector, receiving the estimated phase error to generate a latency compensated phase error output signal with a phase assigned by a sign-bit of the received estimated phase error, comprising: a first multiplier receiving the estimated phase error to apply a first proportional gain thereon; and a sign-bit distributor coupled to the first multiplier, receiving the estimated phase error and replacing a sign-bit of the output of the first multiplier with the sign-bit of the estimated phase error to generate a latency compensated signal; and a voltage-controlled oscillator (VCO) coupled to the loop filter, generating the output clock in response to the latency compensated phase error output signal and feeding the output clock back to the ADC.