Patent ID: 8174421

Claim:
An information processing apparatus, comprising: a plurality of processor units, arranged in a matrix pattern, respectively including a storage unit adapted to store analog information and a comparison unit adapted to compare analog information stored in the storage unit with an inputted reference analog value; an input unit adapted to input the reference analog value to the plurality of processor units while changing the reference analog value in synchronization with a clock signal; a counter unit adapted to update a count value in synchronization with the clock signal and outputting the count value when the analog information and the reference analog value become consistent at a corresponding comparison unit; an output unit which includes a bus-type wiring to be shared by the processor units belonging to the same row of the matrix and adapted to output identification information for identifying the processor unit at which the analog information and the reference analog value have become consistent; and an arbitration unit adapted to arbitrate the use of the bus-type wiring by the plurality of processor units so that the plurality of processor units belonging to the same row of the matrix at which the analog information and the reference analog value have become consistent use the bus-type wiring in sequence and output identification information of the processor units, wherein the arbitration unit includes, for each processor unit: a terminating unit adapted to terminate the connection of the bus-type wiring to a processor unit of a subsequent stage when the analog information and the reference analog value become consistent; and a reestablishing unit adapted to reestablish the terminated connection after outputting identification information of its own processor unit.