Patent ID: 8076767

Claim:
A semiconductor device including a DC-DC converter, comprising: a first die pad including an input power supply terminal; a second die pad including an output terminal; a third die pad; a wiring section including a reference potential terminal; a first semiconductor chip disposed over the first die pad, which includes a high side MOSFET of the DC-DC converter and includes a first gate electrode pad, a first source electrode pad and a first drain electrode of the high side MOSFET, the first drain electrode being coupled to the input power supply terminal; a second semiconductor chip disposed over the second die pad, which includes a low side MOSFET of the DC-DC converter and includes a second gate electrode pad, a second source electrode pad and a second drain electrode of the low side MOSFET, the second drain electrode being coupled to the output terminal; a third semiconductor chip disposed over the third die pad, which includes a first driver circuit for driving the high side MOSFET and a second driver circuit for driving the low side MOSFET, and includes a first electrode pad electrically coupled to an output of the first driver circuit and a second electrode pad electrically coupled to an output of the second driver circuit, the first electrode pad of the third semiconductor chip and the first gate electrode pad of the first semiconductor chip being coupled via a first bonding wire, the second electrode pad of the third semiconductor chip and the second gate electrode pad of the second semiconductor chip being coupled via a second bonding wire; a first metal plate wiring coupled to the first source electrode pad of the first semiconductor chip and the second die pad; a second metal plate wiring coupled to the second source electrode pad of the second semiconductor chip and the wiring section; a Schottky Barrier Diode, an anode and a cathode of the Schottky Barrier Diode being coupled to the second source electrode pad and the second drain electrode of the second semiconductor chip, respectively; and a resin body covering the first, second and third semiconductor chips.