Patent ID: 7659597

Claim:
An integrated circuit device, comprising: a substrate including a trench in active regions and a device isolation layer of the substrate, wherein the active regions are defined by the device isolation layer, and wherein the trench has a same depth in the active regions and the device isolation layer; and a conductive plug wire pattern in the trench including a recessed portion that exposes portions of opposing sidewalls of the trench and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization, wherein the recessed portion is in contact with a first sidewall of the plug portion on one of the active regions along a direction of the trench, wherein a second sidewall of the plug portion opposite the first sidewall and a bottom surface of the plug portion contact a portion of the device isolation layer adjacent to the one of the active regions along the direction, and wherein a top surface of the plug portion is at a substantially same level as top surfaces of the active regions.