Patent ID: 7662715

Claim:
A manufacturing method of a thin film transistor array panel, comprising: forming a gate line on an insulating substrate, the gate line having a first layer of an Al containing metal and a second layer of a Mo-alloy comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti), the gate line having a gate electrode, wherein the first layer and the second layer are patterned by using a single etchant; depositing a gate insulating layer, a semiconductor layer, and a ohmic contact layer on the gate line in sequence; patterning the semiconductor layer and the ohmic contact layer; forming a drain electrode and a data line having a source electrode on the gate insulating layer and the ohmic contact layer, the drain electrode facing the source electrode with a predetermined gap; forming a passivation layer having a contact hole exposing the drain electrode on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer.