Patent ID: 7221601

Claim:
A timer lockout circuit comprising: a first delay circuit for receiving and delaying a first timing signal; a first circuit for receiving said first timing signal from said first delay circuit and for latching said first timing signal; a programmable timing circuit for receiving said first timing signal from said first circuit and for delaying said first timing signal by a programmable time interval; a one-shot generator for receiving said first timing signal from said programmable timing circuit and for generating a set signal; a second circuit for receiving said set signal from said one-shot generator and for latching said set signal; a third circuit for receiving a second timing signal and for latching said second timing signal; a combinational logic circuit for receiving said set signal from said second circuit and for receiving said second timing signal from said third circuit and for generating a third timing signal; and a second delay circuit for receiving and delaying said third timing signal and for simultaneously resetting said first circuit, said second circuit and said third circuit after delaying said third timing signal.