Patent ID: 7211863

Claim:
A family of transistor devices formed in a semiconductor substrate, the substrate being doped with P-type impurity and not comprising an epitaxial layer, the family of transistor devices comprising at least a PNP bipolar transistor and a CMOS pair, the substrate comprising an isolation structure for electrically isolating transistor devices enclosed within the isolation structure from a portion of the substrate outside the isolation structure, the isolation structure comprising: a first N-type isolation region extending downward from a surface of the substrate, the first N-type isolation region comprising a first annular N well and a deep N layer, the first N-type isolation structure enclosing an isolated P region of the substrate; and a second N well having a relatively deep central portion and relatively shallow side portions, the relatively shallow side portions underlying a field oxide layer, the relatively deep central portion underlying a first opening in the field oxide layer, the second N well being electrically shorted to the first N-type isolation region; the PNP bipolar transistor being located in the isolated P region of the substrate and comprising: a first P well adjacent the surface of the substrate, the first P well forming a collector of the PNP bipolar transistor; an N-type base region located adjacent the surface of the substrate within the first P well, the N-type base region forming a base of the PNP bipolar transistor; and a P-type region located adjacent the surface of the substrate within the N-type base region, the P-type region forming an emitter of the PNP bipolar transistor; the CMOS pair comprising a PMOS and an NMOS, the PMOS being located in the second N well and comprising: a first gate separated from the substrate by a first gate oxide layer; a P-type source region located at the surface of the substrate in the second N well on one side of the first gate; and a P-type drain region located at the surface of the substrate in the second N well on an opposite the of the first gate from the P-type source region; and the NMOS being formed in a second P well, the second P well having a relatively deep central portion and relatively shallow side portions, the relatively shallow side portions underlying the field oxide layer, the relatively deep central portion underlying a second opening in the field oxide layer, the NMOS comprising: a second gate separated from the substrate by a second gate oxide layer; an N-type source region located at the surface of the substrate in the second P well on one side of the second gate; and an N-type drain region located at the surface of the substrate in the second P well on an opposite the of the second gate from the N-type source region.