Patent ID: 8552783

Claim:
A programmable delay generator of equal delay steps, comprising: a first delay line having a plurality of stages, each of the plurality of stages including a respective delay buffer and having one signal input and one signal output; and a second delay line having a plurality of stages equal in number to the plurality of stages of the first delay line, each of the plurality of stages of the second delay line including a respective selecting element and having two signal inputs, one select input for selecting one of the two signal inputs, and one signal output, wherein the first delay line and the second delay line are configured in parallel with respect to each other, are interconnected, and have a same signal stage propagation order, and wherein each of the delay steps provided by each of the plurality of stages of the second delay line is equal to a difference between a delay through one of the plurality of stages of the first delay line and a delay through one of the plurality of stages of the second delay line.