Patent ID: 7449924

Claim:
A serial output port, comprising: a plurality of flip-flop stages, connected in series with one another, and clocked by a serial clock signal; a last output latch stage, having an input connected to an output of a last one of the plurality of flip-flop stages, and comprising: (a) a latch, having an input and an output, for latching a stored state responsive to the serial clock signal; (b) an input switch, having a conduction path connected to an input of the last output latch stage, and clocked by the serial clock signal; (c) a delay element comprising a first pair of inverters having an input coupled to the input switch; (d) a cross-coupling switch, having a conduction path connected between an output of the delay element and an input of the delay element, and having a control terminal coupled to the serial clock signal, for connecting the output of the delay element to the input of the delay element while the input switch is open; (e) an output buffer coupled to the delay element, having an input connected to the output of the latch, and having an output connected to an external terminal of the serial output port; the output buffer comprising: a pull-up transistor, having a conduction path connected between a power supply node and the external terminal, and having a control terminal coupled to an output of the latch and to the output of the first pair of inverters; and at least one pull-down transistor, having a conduction path connected between the external terminal and a reference voltage node, and having a control terminal coupled to the output of the latch; wherein the latch of the last output latch stage further comprises: (f) a second pair of inverters, having an input coupled to the input switch and an output coupled to the control terminal of the at least one pull-down transistor; and (g) enable circuitry, having an input receiving an enable/disable signal, and for forcing the first pair of inverters to an output state that turns off the pull-up transistor and for forcing the second pair of inverters to an output state that turns off the at least one pull-down transistor, both responsive to the enable/disable signal in a disable state.