Patent ID: 7966429

Claim:
A phase-change-memory peripheral comprising: a peripheral phase-change-memory controller having a central processing unit (CPU) for executing instructions and a random-access memory (RAM) for storing instructions for execution by the CPU; a bus transceiver in the peripheral phase-change-memory controller for receiving peripheral commands and data from a host over a host bus; a phase-change-memory controller in the peripheral phase-change-memory controller; a plurality of phase-change memory (PCM) cells organized as phase-change-memory mass storage devices, coupled to the phase-change-memory controller, for storing non-volatile data for the host, the data in the phase-change-memory mass storage devices being block-addressable and not randomly-addressable; wherein each PCM cell in the plurality of PCM cells has a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase; a phase-change-memory bus having data lines for transferring data from the phase-change-memory controller to the phase-change-memory mass storage devices; wherein instructions are stored only in the RAM for execution, wherein the CPU executes instructions stored only in the RAM; wherein the instructions are transferred from a copy of the instructions in the phase-change-memory mass storage devices to the RAM during a power-on sequence before the CPU; and a direct-memory access (DMA) engine for transferring data among the phase-change-memory controller, the RAM, and the bus transceiver, the DMA engine being programmed for a transfer, whereby instructions are transferred from the phase-change-memory mass storage devices to the RAM for execution by the CPU and whereby the peripheral phase-change-memory controller controls the phase-change-memory mass storage devices that are block-addressable.