Patent ID: 7472054

Claim:
A system for evaluating performance of a device under test (DUT) comprising: an application module that generates transactions used to test the DUT; a plurality of hardware transactors coupled to the application module that transmit and receive data representing the transactions to and from the DUT; and an emulator coupled to the hardware transactors, the emulator including the DUT and having an emulation clock that is controlled by the application module, wherein the application module waits for events from the emulator in zero simulation time, receives timing information from the emulator concerning status of the emulation clock, and controls operation of the emulation clock by restarting the emulation clock, and wherein the hardware transactors stop the clock, gather the data while the clock is stopped, and forward the data to multiple output channels simultaneously when the clock is restarted, wherein multiple, independent parallel transactions are executed; wherein the starting and stopping of the clock is accurate to within one clock cycle; and wherein the events can be viewed in real-time or recorded for later review and comparison with a set of predicted events to evaluate performance of the DUT.