Patent ID: 8687412

Claim:
A digital memory, comprising: at least one magneto-resistive memory cell comprising a magnetic tunnel junction element with a pinned magnetic layer having a permanently oriented magnetic field and a free magnetic layer having a magnetic field component that is changeably alignable parallel to magnetic field of the pinned layer, in a state of low electrical resistance, and anti-parallel to the magnetic field of the pinned layer in a state of high electrical resistance, wherein a data value is changeably stored in the cell by alignment of the magnetic field of the free layer relative to the pinned layer, and is detectable by differences in a cell value of an electrical parameter produced by the memory cell when subjected to a cell bias current; a reference circuit comprising a high resistance reference, a low resistance reference, and at least two reference magnetic tunnel junction elements operable in tandem, one of the reference magnetic tunnel junction elements being in the high resistance state and another of the reference magnetic tunnel junction elements being in the low resistance state, wherein the reference circuit produces an electrical parameter having a reference value when subjected to a reference bias current; a comparator circuit coupled to compare the reference value versus the cell value, the comparator having an output reading out the data value corresponding to the cell value being greater than or less than the reference value; wherein the reference value represents a value falling between values of the electrical parameter produced by the memory cell in the states of high and low electrical resistance.