Patent ID: 7463692

Claim:
A symbol clock recovery device, comprising: a remained phase error remover configured to operate digital baseband real/imaginary number component signals, and to remove remained phase error; a timing error detecting part configured to operate as a nonlinear system the digital baseband real/imaginary number component signals having the remained phase error removed, and to detect symbol clock phase error information therefrom; wherein the timing error detecting part comprises: a gain controlling unit configured to control a gain of the signal having the remained phase error removed; a filter configured to filter only frequency of a specific bandwidth required in a symbol clock recovery process from the signal outputted from the gain controlling unit; a phase splitter configured to split the signal passing through the filter into the digital baseband real/imaginary number component signals; and a timing error detector configured to operate as a nonlinear system the digital baseband real/imaginary number component signals out-putted from the phase splitter, so as to generate symbol clock phase error information; and an oscillating part configured to generate a symbol clock frequency compensated to at least two times from the detected symbol clock phase error information and outputting the compensated symbol clock frequency.