Patent ID: 8748320

Claim:
A method of connecting to a first metal layer in a semiconductor flow process, comprising: etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer; depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole; and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer; wherein said etching the first portion of the viahole occurs following a first set of semiconductor process operations, comprising forming the first metal layer on a substrate, forming the gate insulation layer on the first metal layer, forming a metal oxide layer on the gate insulation layer, forming an etch stop layer on the metal oxide layer, and forming a photoresist pattern on the etch stop layer; and wherein the photoresist pattern is formed such that no photoresist material is located on an area of the etch stop layer that is to be etched to form the viahole.