Patent ID: 7831808

Claim:
A processor, comprising: a general purpose (GP) unit adapted to receive GP instructions and configured to execute the GP instructions; a single instruction multiple data (SIMD) unit adapted to receive SIMD instructions and configured to execute the SIMD instructions; an instruction unit comprising a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions; wherein the first logic unit is further configured such that a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall; wherein the first logic unit is coupled to receive GP instructions and SIMD instructions and configured to: decode the GP instructions and the SIMD instructions; check the GP instructions for dependencies; resolve any dependencies in the GP instructions; provide the GP instructions that are free of dependencies to the GP unit; and subsequent to providing the GP instructions that are free of dependencies to the GP unit, provide the SIMD instructions to the second logic unit when there are no remaining older GP instructions with dependencies; wherein the first logic unit is not configured to check the SIMD instructions for dependencies; and wherein the second logic unit is coupled to receive the SIMD instructions from the first logic unit and, subsequent to providing, by the first logic unit, the GP instructions that are free of dependencies to the GP unit, configured to: check the SIMD instructions for dependencies; resolve any dependencies in the SIMD instructions; and provide the SIMD instructions that are free of dependencies to the SIMD unit.