Patent ID: 8019561

Claim:
A method of finding a plurality of unwanted connections, hereafter referred to as shorts, between different electrical nodes in a physical layout of an integrated circuit, said layout comprising polygons and other geometrical shapes, hereafter referred to as polygons, and other cells known as subcells being part of a hierarchical layout, said method comprising: (a) reading layout design; (b) marking a user defined selection of polygons known to said user to belong to same electrical nodes; (c) determining if layout is hierarchical; (d) if said layout is hierarchical then removing all subcells from said layout and determining if said shorts are still present (1) if said shorts are still present searching for said shorts among said polygons by repeatedly excluding polygons in different parts of said layout from the electrical connectivity analysis until the group of polygons causing said shorts is identified; (2) if said shorts are not present then searching for said shorts among the subcells by repeatedly excluding different subcells from the electrical connectivity analysis until the subcells causing said shorts are identified; (e) if said layout is not hierarchical searching for said shorts among said polygons by repeatedly excluding polygons in different parts of said layout from the electrical connectivity analysis until the group of polygons causing said shorts is identified; whereby said shorts are found.