Patent ID: 8703604

Claim:
A method comprising: depositing a plurality of dielectric layers on top of a semiconductor structure, said plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of said plurality of dielectric layers down into said plurality of dielectric layers by a non-selective etching process, causing at least one of said multiple openings to have a depth below said etch-step layer through a reactive-ion-etching (RIE) lag effect, where depths of the openings depend upon the lateral size of the openings; and continuing etching said multiple openings by a selective etching process until one or more openings of said multiple openings that are above said etch-stop layer reach and expose said etch-stop layer, wherein said at least one of said multiple openings has a uniform width, after said continuing etching said multiple openings, said uniform width being same above and below said etch-stop layer.