Patent ID: 7710779

Claim:
A nonvolatile semiconductor memory comprising: a memory cell unit including a plurality of electrically connected memory cells having an electric charge accumulation layer and a control electrode stacked thereon; and a source side selection transistor electrically connected to said memory cell of one end of said plurality of memory cells; and a drain side selection transistor electrically connected to the other end of said plurality of memory cells; a plurality of word lines each of which is electrically connected to a control electrode of said plurality of memory cells; a source line which is electrically connected to said source side selection transistor; a bit line which is electrically connected to said drain side selection transistor; a gate line control circuit, in which on a data readout operation, said drain side selection transistor is operated after the operation of said source side selection transistor when a selected memory cell is adjacent to said source side selection transistor, and said source side selection transistor is operated after the operation of said drain side selection transistor when said selected memory cell is adjacent to said drain side selection transistor; and a control signal generation circuit which on a data readout operation, lowers the select voltage applied to a selected word line connected to said selected memory cell adjacent to said source side selection transistor compared to the select voltage applied to a selected word line connected to said selected memory cell adjacent to said drain side selection transistor.