Patent ID: 7670950

Claim:
A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate, and a bottom, the method comprising: immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 5 microns and 300 microns, a depth dimension between 50 microns and 250 microns, and an aspect ratio greater than about 0.3:1, the deposition composition comprising: (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) one or more organic compounds selected from among polarizers and/or depolarizers, which one or more organic compounds promotes faster copper deposition at the via bottom than at the via opening; and (d) chloride ions; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.