Patent ID: 8589934

Claim:
A data processing apparatus comprising: processing circuitry configured to process processing threads using resources accessible to said processing circuitry; a pipeline for handling at least two pending threads awaiting processing by said processing circuitry, said pipeline comprising at least one pipeline stage including at least one resource-requesting pipeline stage for requesting access to said resources for said pending threads; a pipeline controller configured to determine whether requested resources are available for a pending thread in a final pipeline stage of said pipeline, to return said pending thread to a first pipeline stage of said pipeline if said requested resources are not yet available for said pending thread, and to forward said pending thread from said pipeline if said requested resources are available for said pending thread; a priority controller for controlling priority levels of said pending threads, said priority levels defining a priority with which respective pending threads are granted access to resources, pending threads being assigned a base priority level when entering said pipeline for the first time; wherein said priority controller is configured to selectively raise the current priority level of a pending thread in said final pipeline stage if said pipeline controller returns said pending thread to said first pipeline stage, wherein said priority levels are represented by a set of discrete values including a base value representing said base priority level and at least one further value representing at least one higher priority level, and wherein said pipeline is configured to handle a maximum of N pending threads, and said set of discrete values comprises M-bit values, where M and N are integers and M<log2(N).