Patent ID: 8365056

Claim:
A receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the trellis being established on the basis of an elementary trellis comprising N starting states and N finishing states, each starting state being linked to two finishing states by labeled arcs, the signal received including a series of symbols, the receiver comprising: a programmable logic circuit, including: a source memory A and a destination memory B each comprising N rows and M+L columns respectively allocated to M fixed fields for describing the trellis, and to L variable fields, the fixed fields comprising at least two destination address fields, one per finishing state and two fields of labels of the corresponding arcs, the variable fields comprising at least one field of distance aggregated as a function of the labels of the elementary lattice and of the symbols received, and a sequence field of the S last decoded bits; and an operator able to calculate the variable fields of a memory as a function of the fixed fields of the said memory, of the symbols received and of the variable fields of the other memory and able to reverse the role of the source memory and destination memory.