Patent ID: 8471233

Claim:
A semiconductor memory comprising: a first MOS transistor having two diffusion layers formed in a semiconductor substrate; a second MOS transistor which is formed in the semiconductor substrate and has one of the two diffusion layers of the first MOS transistor as a common diffusion layer for the first and second MOS transistors; and a variable resistance element which is formed between side wall insulating films formed at respective side walls of a first gate electrode of the first MOS transistor and a second gate electrode of the second MOS transistor and is connected to the common diffusion layer, wherein, the variable resistance element comprises (a) a first electrode formed over the common diffusion layer between the side wall insulating films, (b) a variable resistance layer formed between the side wall insulating films over the first electrode, the variable resistance layer comprising (i) a storage layer formed on the side of the first electrode, and (ii) an ion source layer which supplies metallic ions to the storage layer or accepts metallic ions supplied to the storage layer, and (c) a second electrode formed over the variable resistance layer.