Patent ID: 8884356

Claim:
A nonvolatile semiconductor memory device comprising: a foundation layer; a stacked body provided on the foundation layer and including a plurality of electrode layers and a plurality of insulating layers alternately stacked; a plurality of first channel body layers extending from an upper surface of the stacked body through the stacked body to a lower surface of the stacked body; a memory film provided between each of the plurality of first channel body layers and each of the plurality of electrode layers; a first interlayer insulating film provided on the stacked body; a plurality of select gate electrodes provided on the first interlayer insulating film; a second channel body layer penetrating through each of the plurality of select gate electrodes and the first interlayer insulating film, and the second channel body layer being connected to each of the plurality of first channel body layers; and a gate insulating film provided between each of the plurality of select gate electrodes and the second channel body layer, the stacked body being bent, and each end surface of the plurality of electrode layers and each end surface of the plurality of insulating layers face upward from the foundation layer, the first interlayer insulating film including a slit extending in a direction generally parallel to the upper surface of the stacked body, and the slit extending in a direction non-parallel to a first direction in which each end surface of the plurality of electrode layers extends, and part of at least one end surface of the plurality of electrode layers being part of bottom of the slit.