Patent ID: 6917192

Claim:
For use in an operational circuit having a high impedance node, a test circuit capable of connecting said high-impedance node to an external test point when a test signal driving said test circuit is enabled, said test circuit comprising: a first transmission gate switch for coupling said high impedance node to a first internal node of said test circuit when said test signal is enabled, said first transmission gate switch comprising a first N-channel transistor having a drain coupled to said high impedance node, a gate coupled to a Logic 1 when said test signal is enabled, and a source coupled to said first internal node; a second transmission gate switch capable of coupling said first internal node to a second internal node of said test circuit when said test signal is enabled; a third transmission gate switch capable of coupling said second internal node to said external test point when said test signal is enabled; and a biasing circuit for pulling said second internal node to ground and for generating a negative Vgs bias on said first N-channel transistor when said test signal is disabled to thereby reduce leakage current in said first N-channel transistor.