Patent ID: 7394151

Claim:
A semiconductor package having a top surface and a mounting surface including: a die having processed surface facing towards the mounting surface having exposed metal connections at the processed surface; a conducting connecting material disposed on the exposed metal connections; a first deposit of a plating material contacting the conducting connecting material; a plate comprising substantially of three planar portions, wherein: the first portion of the plate is attached to the unprocessed surface of the die; the second portion of the plate is connected substantially perpendicularly to the first portion of the plate; the third portion of the plate is connected substantially perpendicularly to the second portion of the plate and is parallel to the plate of the first portion of the plate; and the third portion of the plate is attached to a second deposit of the plating material such that the second deposit of the plating material is in the same plane as the first deposit of the plating material and the third portion of the plate is parallel to but not in the same plane as the first deposit of the plating material; and an insulating material, having an exterior, formed around the conducting connecting material, wherein: the plating material extends to the exterior of the insulating material so that the plating material is exposed at least at the mounting surface of the semiconductor package; and the plating material includes a top portion, a side portion, and a bottom portion and at least two of the top portion, the side portion, and the bottom portion are at least partially enveloped by the insulating material.