Patent ID: 7522506

Claim:
A semiconductor memory comprising: a controller, a media including at least one area, each area providing at least one first group of parallel servo tracks having first information, and at least one group of data tracks parallel to and separated apart from the servo tracks, wherein the servo tracks are subdivided into first and second preamble areas adjacent to each end respectively and a rack region therebetween and each preamble area provides interleaved first and second regions transverse to the tracks, the first information perpendicularly aligned on both sides of a track in the first region and omitted from both sides of the track in the second region; for each area; at least one first read/write mechanism adjacent to the first group of parallel servo tracks, each first read/write mechanism including an electron field emitter configured to read the first information; at least one second read/write mechanism adjacent to the data track, each first read/write mechanism including an electron field emitter; flexures configured to provide relative motion between the each area and the first and second read/write mechanisms adjacent to each area; wherein for each area, the controller is configured to receive a first signal generated in response to the first information being read, and wherein the controller is configured to generate a second signal provided to the flexures to cause a position of the media to be adjusted relative to the first read/write mechanism electron emitter.