Patent ID: 8370784

Claim:
A method to automatically design a custom integrated circuit, comprising: receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a customized architecture for the computer readable code meeting constraint(s)using an Automatic Optimal Instruction Set Architecture Generator (AOISAG) working with data from both feedforward and feedback data to the AOISAG and generating custom instructions for the customized architecture, wherein the generating comprise: automatically determining an instruction execution sequence based on code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots automatically identifying potential parallel units in the computer readable code that can be executed concurrently by: from machine instructions level of the computer readable code, determining sequential statements in the computer readable code that is parallelizable, performing translation of the sequential code to machine instructions for parallel execution on different processors when the sequential code is independent of each other; and continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis until the constraints are met; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit with the customized architecture; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit with the customized architecture; and automatically synthesizing the customized architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.