Patent ID: 7930656

Claim:
A method for fabricating a semiconductor device, the method comprising: providing drawn pattern data describing first device features for forming gate structures having a first given minimum width over active regions and a second given minimum width over adjacent field regions, and second device features for gate contacts for respectively contacting the patterned gate structures; generating initial gate mask patterns for the gate structures for forming target gate structures having the first given minimum width over both the active regions and the field regions, wherein the given minimum gate structure widths of at least a first plurality of the patterned targeted gate structures are too small to fully encompass the corresponding width dimension of the gate contacts at landing locations of the gate contacts with the target gate structures; and using computer code on a computer, automatically correcting the patterns to enlarge the widths of the initial gate mask patterns for the first plurality of the patterned targeted gate structures at the landing locations of the targeted gate structures, for forming retargeted gate structures to enable the contacts to be fully encompassed at the landing locations without elsewhere enlarging the widths of those patterned targeted gate structures.