Patent ID: 7925861

Claim:
A multithreaded data processor operable to process a plurality of threads, the data processor comprising: a plurality of single instruction multiple data (SIMD) processing arrays, each processing array comprising a plurality of processing elements (PEs), each PE operable to receive a selected one of the plurality of threads; a thread manager operable to transfer the threads to an array controller, the thread manager comprising: a fetch unit operable to retrieve the threads in parallel with one another; a thread scheduler operable to schedule processing priority for each thread from among the plurality of threads; wherein the fetch unit is further operable to transfer sequentially a plurality of core instructions from each selected thread from among the plurality of threads to the array controller; and wherein; the array controller is operable to transfer each selected thread from among the plurality of threads to the plurality of SIMD processing arrays on the basis of a priority status allocated to the threads.