Patent ID: 8885431

Claim:
A device comprising: a plurality of memory areas, each of the plurality of memory areas including a plurality of memory cells required to perform a refresh of information stored in the plurality of memory cells by a plurality of sense amplifiers; a first control circuit determining a number of refresh-target memory areas among said plurality of memory areas associated with one refresh requirement signal at a time, said number is at least one and is indicative of how many of said memory areas are to be refreshed; a second control circuit controlling a refresh operation with respect to said refresh-target memory areas in accordance with said one refresh requirement signal; and a third control circuit adjusting an active time-out time interval according to the determined number of refresh-target memory areas in connection with said refresh operation, said active time-out time interval indicating a time interval from a first timing at said sense amplifiers are activated to a second timing at word lines are inactivated, said sense amplifiers and said word lines relating to said refresh-target memory areas.