Patent ID: 7164294

Claim:
A method for operating a programmable logic array, comprising: applying a number of input signals to a number of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion mode channel region therebetween, and a number of vertical gates located above different portions of the depletion mode channel region, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness, and wherein applying a number of input signals to the number of logic cells in the first logic plane includes applying a potential to the number of vertical gates in each logic cell; outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane, wherein each logic cell in the second logic plane includes a source region, a drain region, a depletion mode channel region therebetween, and a number of vertical gates located above different portions of the depletion mode channel region, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness, and wherein outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane includes applying a potential to the number of vertical gates for the logic cells in the second logic plane; and wherein the number of logic cells in the second logic plane are arranged in rows and columns to receive the output signals from the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.