Patent ID: 8880791

Claim:
A memory module comprising: a standard registered DIMM (RDIMM) interface configured to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and a host system, the first plurality of DDR SDRAM signals including at least address/control and data signals; a register coupled to the standard RDIMM interface via the first signals path, the register operable to receive DDR SDRAM address/control signals of the first plurality of DDR SDRAM signals; a volatile memory subsystem having a first storage capacity; a non-volatile memory subsystem having a second storage capacity that is at least 400percent more than the first storage capacity, wherein the memory module is configured to provide non-volatile storage via the non-volatile memory subsystem; a circuit; and a controller in communication with the circuit via a second signals path for transmitting a second plurality of DDR SDRAM signals between the controller and the circuit, the second plurality of DDR SDRAM signals including at least address/control and data signals, wherein the controller is coupled to the nonvolatile memory subsystem via a third signals path for transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem, and wherein the circuit is coupled (i) to the volatile memory subsystem via a fourth signals path for transmitting a third plurality of DDR SDRAM signals between the volatile memory subsystem and the circuit, the third plurality of DDR SDRAM signals including at least address/control and data signals, (ii) to the standard RDIMM interface via the first signals path for transmitting or receiving DDR SDRAM data signals of the first plurality of DDR SDRAM signals between the circuit and the host, and (iii) to an output of the register to receive registered DDR SDRAM address/control signals from the register, wherein in response to a first control signal from the controller the circuit (i) transmits the registered DDR SDRAM address/control signals to the volatile memory subsystem via the fourth signals path, and (ii) transfers data between the standard RDIMM interface and volatile memory subsystem using the first and fourth signals paths, wherein the controller is operable to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem, and wherein in response to a second control signal from the controller, the circuit uses the second and fourth signals paths to (i) communicate the second plurality of DDR SDRAM signals to the volatile memory subsystem, and (ii) communicate data from the volatile memory subsystem to the controller.