Patent ID: 7239005

Claim:
A semiconductor device comprising: a semiconductor substrate having first and second active regions of a first conductivity type; a first insulating layer formed on each of said first and second active regions; first and second electrode structures formed above and crossing across intermediate portions of said first and second active regions, respectively; a second insulating layer formed on said second electrode structure; a third electrode structure formed on said second insulating layer; a pair of first semiconductor regions of a second conductivity type opposite to said first conductivity type, formed in said first active region on both sides of said first electrode structure; a pair of second semiconductor regions of said second conductivity type formed in said second active region on both sides of said second electrode structure; an interlevel insulating layer formed to cover said first, second and third electrode structures; first and second power source lines formed on said interlevel insulating layer above said second active region; a first interconnection structure connecting said third electrode structure and at least one of said second semiconductor regions to said first power source line; and a second interconnection structure connecting said second electrode structure to said second power source line, wherein said first active region constitutes a MOS transistor and said second active region constitutes a bypass capacitor and induces an inversion layer of said second conductivity type under said second electrode structure when the power source lines are activated.