Patent ID: RE44590

Claim:
A clock control device, comprising: a set circuit for triggering an input address in response to an internal command signal to output a first address; a shift register including a plurality of flip-flops connected in series, wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address; an active signal generator for outputting an active signal, based on an a plurality of active control signal signals indicating whether or not each a corresponding bank of a plurality of memory banks is activated, and a plurality of precharge control signal signals indicating whether or not a corresponding bank of the plurality of memory banks is precharged ; and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.