Patent ID: 8346830

Claim:
A digital signal processing apparatus comprising: a multiplier which multiplies first and second numerical value data; a register including a plurality of flip-flop circuits each constructed to retain data of n bit (where n is an integral number equal to or greater than one) in synchronism with a clock pulse, said register retaining a multiplication result of said multiplier by means of said plurality of flip-flop circuits, n bit per flip-flop circuit; a control circuit which, for each of said first and second numeric value data, detects a number of consecutive zeros from a lowest-order bit of the data and performs control, on the basis of the number of the consecutive zeros detected by the control circuit and for each of said plurality of flip-flop circuits, as to whether or not the clock pulse should be supplied to the flip-flop circuit; and a mask circuit which masks an output value of each of the flip-flop circuits, for which supply of the clock pulse has been stopped by said control circuit, with a zero value.