Patent ID: 7139193

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, wherein the memory cell array includes a plurality of element isolation regions, wherein each of the memory cells includes a first impurity layer, a second impurity layer, a channel region located between the first impurity layer and the second impurity layer, a word gate and a select gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region, wherein a first wordline connection section, which connects at least one of a plurality of word gate interconnects with at least one of the word gates, is disposed over at least one of the element isolation regions, wherein the memory cells include a plurality of word gate rows, each of the word gate rows is formed by connecting the word gates in the memory cells arranged in the row direction, and wherein the nonvolatile semiconductor memory device further includes a plurality of common connection sections, each of the common connection sections connecting two of the word gate rows adjacent in the column direction over one of the element isolation regions on which the first wordline connection section is disposed.