Patent ID: 7015147

Claim:
A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si 1−x Ge x layer, comprising: preparing a silicon substrate; growing an epitaxial Si 1−x Ge x layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si 1−x Ge x layer; trench etching of the top silicon and Si 1−x Ge x , into the silicon substrate to form a first trench; selectively etching the Si 1−x Ge x layer to remove a portion of the Si 1−x Ge x to form an air gap; depositing a layer of SiO 2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si 1−x Ge x layer; depositing a second layer of SiO 2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.