Patent ID: 8291295

Claim:
A controller for interfacing between a host controller in a host device and a flash memory device, the controller comprising: a first NAND interface configured to transfer data between the host controller and the controller using a NAND interface protocol, wherein the first NAND interface is further configured to receive, from the host controller, (i) one of a read command and a write command and (ii) a logical address; an address conversion module configured to convert the logical address received from the host controller to a physical address of the flash memory device; a second NAND interface configured to transfer data between the controller and the flash memory device using a NAND interface protocol in accordance with the one of the read command and the write command received from the host controller; an error correction code (ECC) module configured to calculate ECC bits for data received through at least one of the first and second NAND interfaces; and an additional functionality module.