Patent ID: 7968410

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a first polysilicon layer having a first thickness in a peripheral circuit region disposed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region disposed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; forming gate electrodes by siliciding the first and second polysilicon layers; forming a plurality of gate stack structures by patterning the second polysilicon layer, the blocking insulating layer, the charge trap layer, and the first tunneling insulating layer, which are formed in the memory cell region; forming a source/drain region by implanting an impurity into a surface of the substrate exposed to both sides of the plurality of gate stack structures; forming an oxide layer between each of the plurality of gate stack structures by performing an oxidation reaction over the substrate in which the plurality of gate stack structures are formed; and removing a portion of the oxide layer between each of the plurality of gate stack structures to a height at which the blocking insulating layer is formed.