Patent ID: 7043579

Claim:
A data access ring system having a plurality of attached processor units (APUs), a local store associated with each APU, and a fixed timing protocol, comprising: a data command ring, coupled to the plurality of APUs, employable to carry indicia for a data packet of a selection of one of the plurality of APUs, wherein a data transmission may comprise multiple data packets; a data address ring, coupled to the plurality of APUs, the data address ring employable to carry indicia of a memory location for each data packet to the selected APU a predetermined number of clock cycles set by the fixed timing protocol after the data command ring carries the indicia of the selection of one of the plurality of APUs; and a data transfer ring, coupled to the plurality of APUs, the data transfer ring employable to transfer each data packet to or from the memory location associated with the APU a predetermined number of clock cycles set by the fixed timing protocol after the data address ring carries the indicia of the memory location to the selected APU.