Patent ID: 7023249

Claim:
A phase locked loop having fast tune time and low phase noise comprising: a voltage controller oscillator (VCO) for providing an output signal controlled by a tune voltage; a divider connected to the VCO for dividing the output signal from the VCO; a reference oscillator for generating a reference signal; a phase detector connected to the divider and the reference oscillator for comparing the reference signal to the divided VCO signal and generating a phase detector error signal indicating a lock condition of the phase locked loop; a fast filter having an input connected to the phase detector and having a wide bandwidth for filtering the phase detector error signal and providing a fast filter tune voltage when the phase locked loop is tuning; a pair of diodes having one end connected to the fast filter wherein one of said pair of diodes is forward biased depending on said fast filter tune voltage; a slow filter having an input connected to the phase detector and the fast filter and having a narrow bandwidth for filtering the phase detector error signal and for providing a slow filter tune voltage; and an integrator without any shared element with the slow filter comprising: an op amp having an inverting input, a non-inverting input and an output wherein the non-inverting input is connected to another end of the pair of diodes; an integrator capacitor connected to the op amp inverting input and the output; and an integrator resistor connected to the slow filter and to the op amp inverting input; wherein the integrator capacitor is rapidly charged by the fast filter tune voltage to quickly tune the phase locked loop and wherein the slow filter tune voltage tunes the VCO when the phase locked loop is locked.