Patent ID: 7965705

Claim:
A circuit to selectively couple input nodes to at least one output node, comprising: groups of input nodes configured to receive input signals; at least one unidirectional bus, having a scalable bus length, which is coupled to the at least one output node; buffers arranged along the bus, including chain buffers configured to buffer data signals on the bus and crosspoint buffers configured to buffer the input signals from the group of input nodes, wherein a depth of a given chain buffer is independent of the bus length; arbiter circuits distributed along the bus, wherein a given arbiter circuit arbitrates between the data signals input to a given chain buffer and one or more of the input signals input to a given crosspoint buffer; multiplexers, wherein a given multiplexer is coupled to a given chain buffer, a given crosspoint buffer and either the bus or, for a last multiplexer, the at least one output node; and wherein the given multiplexer is configured to selectively couple inputs to the given multiplexer, which include one or more of the input signals and data signals output from a chain buffer on the bus, to either a subsequent chain buffer on the bus or, for the last multiplexer on the bus, the at least one output node.