Patent ID: 7441210

Claim:
A method for developing a circuit design, comprising the steps of: (A) editing a file of said circuit design based on a plurality of edits received from a designer, said file containing a code written in a hardware description language; (B) characterizing said code in said file while said designer is editing said code to generate a plurality of characterization results, said characterization results identifying (i) a first of a plurality of functions in said code and (ii) a first of a plurality of coding styles being used to create said first function; and (C) generating a plurality of suggestions to said designer to modify said code based on a comparison of a plurality of goals associated with said circuit design against said characterization results, wherein (i) said suggestions comprise (a) a first code template of said first function and (b) a second of said coding styles suitable to implement said first function, (ii) said goals comprise at least two of (a) a timing goal, (b) a congestion goal, (c) an area goal, (d) a design-for-test goal, (e) a power goal and (f) a coding style goal, and (iii) all of said editing, said characterizing and said generating of said suggestions occur before any of (a) logic synthesis and (b) design rule checking are performed on said circuit design.