Patent ID: 7555416

Claim:
A computer implemented method for analyzing a circuit network having transistors, comprising: representing, using a computer, a circuit by an equivalent circuit that comprises at least one linear network and at least one nonlinear cell to interface with each other; solving, using the computer, circuit equations for the at least one linear network and circuit equations for the at least one nonlinear cell separately; matching, using the computer, solutions to the circuit equations for the at least one linear network and solutions to the circuit equations for the at least one nonlinear cell at an interface between the at least one linear network and the at least one nonlinear cell via linear nonlinear iterations; imposing, using the computer, conditions on voltages and currents in one or more internal circuit nodes in the at least one linear network, one or more nonlinear nodes in the at least one nonlinear cell, and one or more interface nodes at an interface between the at least one linear network and the at least one nonlinear cell to ensure convergence of the solutions to the at least one linear network and the at least one nonlinear cell; repeating, using the computer, the linear nonlinear iterations until the difference in the interface node voltages calculated from linear and nonlinear stages is smaller than an error tolerance at the interface node; and identifying, using the computer, operational characteristics of the circuit network from the converged values of nodal voltages and currents.