Patent ID: 7119006

Claim:
A method of forming a metal conductor in an integrated circuit, comprising the steps of: forming a via etch stop layer over a first conductor; forming an interlevel dielectric layer over the via etch stop layer; forming an intermetal dielectric layer over the interlevel dielectric layer; forming a hardmask layer over the intermetal dielectric layer; then etching through the hardmask layer and the intermetal dielectric layer at a via location; then, defining a trench location with a trench mask layer, the trench location overlapping at least partially over the etched portion of the intermetal dielectric layer, wherein the step of defining a trench location with a trench mask layer comprises: forming a masking layer comprised of photoresist over the hardmask layer; patterning the masking layer over the hardmask layer, to define the trench location; etching the hardmask layer at the trench location, using the patterned masking layer as a mask; and removing the patterned masking layer; then simultaneously etching through the intermetal dielectric layer at the trench location and through the interlevel dielectric layer at the via location, the etching at the via location effectively stopping at the via etch stop layer, the simultaneous etching forming a trench in the intermetal dielectric layer at the trench location that is contiguous with a via through the interlevel dielectric layer at the via location; removing the via etch stop layer at the via location; and then forming a second conductor within the trench and via, in contact with the first conductor.