Patent ID: 8012821

Claim:
A method for generating an embedded resistor in a semiconductor device, the method comprising: forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a first silicon layer on the pad oxide; forming a photo-resist mask on a portion of the first silicon layer disposed substantially above the STI region; etching the first silicon layer to yield a polyconductor (PC) disposed substantially above the STI region; oxidizing the PC; depositing at least one of an oxide material or a metal gate material on the oxidized surface; depositing a second silicon layer on the at least one oxide material or metal gate material; depositing additional silicon on a portion of the second silicon layer disposed substantially above the STI region; patterning a transistor gate with a photo-resist mask disposed on another portion of the second silicon layer disposed substantially away from the STI region; and etching the second silicon layer to yield at least one transistor structure disposed substantially away from the STI region and at least one resistor structure disposed substantially above the STI region.