Patent ID: 7687340

Claim:
A semiconductor structure fabrication method, comprising: providing a semiconductor structure comprising: (a) a semiconductor block comprising a first semiconductor material doped with a first doping polarity and having a first lattice orientation; (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region comprises a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation; forming first and second gate stacks on the semiconductor block and the semiconductor region, respectively, wherein the first and second gate stacks comprises first and second gate regions, respectively; simultaneously forming (i) first and second S/D regions in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block, wherein the first and second S/D regions and the first and second discharge prevention semiconductor regions are doped with the second doping polarity; forming third and fourth S/D regions in the semiconductor region on opposing sides of the second gate stack, wherein the third and fourth S/D regions are doped with the first doping polarity; and forming first, second, and third electrically conducting lines, wherein the first electrically conducting line electrically couples the first gate region to the first discharge prevention semiconductor region, wherein the second electrically conducting line electrically couples the second S/D region to the second gate region, and wherein the third electrically conducting line electrically couples the fourth S/D region to the second discharge prevention semiconductor region.