Patent ID: 7181658

Claim:
A method for testing a semiconductor memory device, comprising: a first step of generating n number of internal addresses including a first external address supplied for designating a storage region of data for 1 bit to be written into a storage unit of a semiconductor memory device, in synchronization with a high-speed clock which has a frequency n times that of an external clock, n being a natural number, and is synchronized with the external clock, generating n bits of internal write data corresponding to n number of the internal addresses in synchronization with the high-speed clock and writing the generated internal write data into the storage unit, a first data generating method of generating the n bits of the internal write data being consecutively generating n number values of “1”; and a second step of latching a second external address supplied for designating a storage region of data for 1 bit to be read from the storage unit, generating n number of second internal addresses including the second external address in synchronization with the high-speed clock, reading n bits of internal read data corresponding to n number of the second internal addresses from the storage unit in synchronization with the high-speed clock and outputting the internal read data corresponding to the second internal address, which coincides with the latched second external address, out of n number of the internal addresses.