Patent ID: 7373369

Claim:
A method of performing additive arithmetic operations on operands in a floating-point arithmetic unit, the operands including a first operand and a second operand, the first operand being a first floating-point number having a first mantissa, the second operand being a second floating-point number having a second mantissa, the second operand being greater than the first operand, the precision of the floating-point arithmetic unit exceeding the precision enabled by a bit length of data input to the floating-point arithmetic unit, said method comprising: separating the first mantissa into a high portion and a low portion and separating the second mantissa into a high portion and a low portion; loading the high portion of the first mantissa into a first operand register and loading the high portion of the second mantissa into a second operand register, the first and second operand registers each having a data width of N bits; aligning the high portion of the first mantissa with the high portion of the second mantissa; moving the aligned high portion of the first mantissa into a sum register and moving the high portion of the second mantissa into a carry register, said sum register and said carry register each having a data width of 2N bits; concatenating in the carry register the low portion of the second mantissa with the high portion of the second mantissa; aligning the low portion of the first mantissa in accordance with said aligning of the high portion of the first mantissa; concatenating in the sum register the aligned low portion of the first mantissa with the aligned high portion of the first mantissa using a hold-function multiplexing circuit; performing an additive arithmetic operation on the aligned first mantissa and the second mantissa in an adder, the adder having a data width of 2N bits.