Patent ID: 7788414

Claim:
A memory controller configured to interface with a memory to control the memory, the memory controller comprising: a control circuit configured to provide a control signal; an output interface unit; and a programmable command storage unit coupled to the control circuit and the output interface and configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit; wherein the output interface is configured to provide the selected command to the memory; wherein the programmable command storage unit is configured to store control information associated with the command and provide the control information to the control circuit; wherein the control circuit is configured to generate a new control signal based on the control information and to provide the new control signal to the programmable command storage unit to thereby cause the programmable command storage unit to output a new selected command to the output interface unit; wherein the control information comprises delay count information and the control circuit is configured to control a delay between selected commands output from the programmable command storage unit based on the delay count information.