Patent ID: 7362697

Claim:
A chip comprising: a data source; a set of drivers and a spare driver, wherein the set of drivers and the spare driver are connected to a set of switch units; wherein the set of switch units are connected to, and receive inputs from, a set of driver bit logic units, which include a spare driver bit logic unit; wherein the set of driver bit logic units are connected to and receive inputs from the data source, and wherein the set of driver bit logic units are not included in the data source; a set of bit lines and a spare bit line; wherein the set of switch units provides a connection between the set of bit lines and the set of bit logic units, and the spare bit line and the spare driver bit logic unit, and wherein the set of switch units further can reconfigure the connection to exclude a selected bit line from the set of bit lines and use the spare bit line if the selected bit line fails to carry a signal; wherein the set of driver bit logic units include corresponding shift registers and corresponding multiplexers, wherein the corresponding shift registers provide an input into the corresponding multiplexers, wherein the corresponding shift registers in the set of driver bit logic units are coupled together serially, and wherein the chip further comprises: test control logic that generates a test pattern, wherein the test control logic is coupled to only a first one of the corresponding shift registers for providing the test pattern to the first one of the corresponding shift registers.