Patent ID: 8546203

Claim:
A method of forming a semiconductor structure comprising: (a) obtaining an extra thin semiconductor on insulator (ETSOI) wafer having a PFET portion where a p-type field effect transistor (PFET) will be formed and an NFET portion where an n-type field effect transistor (NFET) will be formed; (b) forming at least one gate structure in the PFET portion and at least one gate structure in the NFET portion; (c) depositing a first high quality nitride over the PFET portion and the NFET portion, the high quality nitride being unetchable in dilute hydrofluoric acid (HF); (d) depositing a first low quality nitride over the first high quality nitride, the first low quality nitride being etchable in dilute HF; (e) etching the PFET portion to remove the first high quality nitride and first low quality nitride except for first high quality nitride and first low quality nitride adjacent to the at least one gate structure in the PFET portion; (f) etching the PFET portion and the NFET portion to remove the first low quality nitride, resulting in first high quality nitride spacers adjacent to the at least one gate structure in the PFET portion and first high quality nitride over the NFET portion; (g) forming doped faceted epitaxial silicon/germanium (SiGe) on the ETSOI adjacent to the first high quality nitride and the at least one gate structure in the PFET portion to form a faceted raised source/drain (RSD) in the PFET portion; (h) depositing a second low quality nitride over the PFET portion and the NFET portion and depositing a second high quality nitride over the second low quality nitride; (i) etching the NFET portion to remove the second high quality nitride and the second low quality nitride except for second high quality nitride and second low quality nitride adjacent to the at least one gate structure in the NFET portion; (j) ion implanting into the NFET portion to damage the first and second high quality nitrides; (k) etching the NFET portion to remove the damaged first and second high quality nitrides and the second low quality nitride resulting in first high quality nitride spacers adjacent to the at least one gate structure in thee NFET portion; (l) ion implanting to damage the second high quality nitride in the PFET portion; (m) etching to remove the damaged second high quality nitride and second low quality nitride from the PFET portion; (n) forming a faceted epitaxial silicon RSD on the ETSOI adjacent to the first high quality nitride spacers in the NFET portion; (o) performing a rapid thermal anneal; (p) ion implanting extensions into the ETSOI underneath the at least one gate structure in the NFET portion; and (q) performing a short time scale anneal to activate the NFET extension implants but not diffuse them.