Patent ID: 8230175

Claim:
A system comprising: a data storage device having a sequential data access capability and requiring no separate address bus coupled therewith; and a processor coupled to said data storage device and comprising: a data cache, wherein said data cache is enabled during read operations from said data storage device, and wherein said data cache is operable to receive sequentially read data from said data storage device during a read operation and further operable to sequentially store said sequentially read data; a cacheable address window at least twice the size of said data cache plus a page size defined for said data storage device for receiving data from said data storage device, wherein a read pointer associated with said cacheable address window is incremented upon each data being received and said data cache is flushed upon said read pointer associated with said cacheable address window wrapping around said cacheable address window; and a non-cacheable address window for issuing commands to said data storage device, for supplying addresses to said data storage device and for issuing writes to said data storage device.