Patent ID: 7679119

Claim:
A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) device including a plurality of non-volatile logic cells formed on a substrate, each non-volatile logic cell comprising: a polycrystalline silicon floating gate disposed over the substrate; a control capacitor including: a first capacitor including a first portion of the floating gate and an isolated P-well region formed in the substrate below the first portion of the floating gate; a second capacitor including a polycrystalline silicon control gate structure located adjacent to said first portion of the floating gate, a non-volatile p-channel transistor including a first source region and a first drain region disposed in an N-well region formed in the substrate adjacent to a second portion of the floating gate; wherein the isolated P-well region of the first capacitor is electrically connected to the control gate structure; and means for controlling said control capacitor and said non-volatile p-channel transistor such that band-to-band tunneling (BBT) is induced between said floating gate and one of said isolated P-well region and said non-volatile p-channel transistor during a program/erase operation.