Patent ID: 7358775

Claim:
An inverting dynamic logic register, comprising: a complementary pair of evaluation devices responsive to a clock signal; evaluation logic, coupled between said complementary pair of evaluation devices at a pre-charged node, configured to evaluate a logic function based on at least one input data signal, wherein said logic function evaluates to either a first state or a second state; delay logic, coupled to said clock signal, configured to generate a kill signal, wherein said kill signal is a delayed version of said clock signal, and wherein the delay between said clock and kill signals comprises a hold time, and wherein said hold time is shortened when said logic function evaluates to said first state; latching logic, responsive to said clock and kill signals and the state of said pre-charged node, configured to control the state of an output node based on the state of said pre-charged node during an evaluation period between an operative edge of said clock signal and the next edge of said kill signal, and configured to otherwise present a tri-state condition to said output node, wherein said latching logic comprises: a first P-channel pull-up device having a gate receiving said kill signal and a source and a drain coupled between a source voltage and a source of a second P-channel device, wherein said second P-channel device has a gate coupled to said pre-charge node and a drain coupled to said output node; and a plurality of N-channel pull-down devices, coupled between said output node and a reference voltage, and controlled by said clock signal and said pre-charged node; and a keeper circuit, coupled to said pre-charge node, and configured to preserve the state of said pre-charge node when said evaluation logic evaluates said logic function to said second state during said evaluation period and said at least one input data signal changes state thereafter.