Patent ID: 8462561

Claim:
A data transfer system comprising: a burst-read capable device that initiates a burst read request that includes a first memory address location and is connected to receive data via a local data bus; a page mode memory device that includes a main memory portion and a page buffer portion, wherein the page mode memory device provides data from the main memory portion in response to a received memory location address and data from the page buffer portion in response to a received page buffer address; and a burst read control circuit that interfaces between the burst-read capable device and the page-mode memory, wherein in response to the burst-read capable device initiating a burst read request the burst read control circuit communicates the first memory address location to the page mode memory device to read data associated with the first memory address location and to load data associated with subsequent and contiguous memory locations into the page buffer portion of the page mode memory device, the burst read control circuit automatically increments and provides a page buffer address to the page mode memory to retrieve data from the page buffer portion for provision to the burst-read capable device.