Patent ID: 7872892

Claim:
In a memory module with a plurality of memory integrated circuits providing a Unified Memory Architecture (UMA), each of the plurality of memory integrated circuits having at least two pins to couple information into each of the memory integrated circuits, method comprising: setting values of at least two identity bits respectively onto the at least two pins of each memory integrated circuit of the UMA; receiving the at least two identity bits into each memory integrated circuit of the UMA as an identity value; using a data qualifier to individually program each of the memory integrated circuits with the at least two identity bits, wherein accesses into each memory integrated circuit are micro-tile memory accesses utilizing at least the two identity bits, wherein the micro-tile memory accesses comprise independent sub-channel memory accesses into the at least one memory integrated circuit; retrieving data from at least one of the memory integrated circuits via the independent sub-channel memory accesses; and returning a cache line having the retrieved data, wherein the retrieved data comprises data from discontiguous memory locations as a single cache line.