Patent ID: 7793032

Claim:
A chip for use in a processing device, comprising: an interconnect; a first classification adapter unit circuit connected to the interconnect; and a second classification adapter unit circuit connected to the interconnect, wherein the interconnect is configured to enable the first classification adapter unit circuit and the second classification adapter unit circuit to communicate with each other, the first classification adapter unit circuit is operable to: (1) receive a block of data from an agent, (2) create a data container containing the received block of data and a directive, and (3) transmit the data container to one or more other classification adapter unit circuits, including the second classification adapter unit circuit, by providing the data container to the interconnect, the directive includes a destination identifier that is used by the interconnect to determine a port to which it should output the data container, and the directive further includes an instruction to be executed by the second classification adapter unit circuit.