Patent ID: 7752627

Claim:
An apparatus for generating a dynamic instruction dispatch priority for each of a plurality of threads concurrently executing in a multithreaded processor, the apparatus comprising for each of the plurality of threads: a storage element, for storing a dynamically updated workload level of the thread; parameter inputs, specifying a plurality of workload level ranges; comparison logic, coupled to said storage element and said parameter inputs, configured to output an instruction dispatch priority for the thread based on which of said plurality of workload level ranges said workload level falls into, wherein the workload level of the thread stored in the storage element is dynamically updated according to a leaky-bucket algorithm such that the workload level of the thread stored in the storage element increases the longer no instructions are issued from the thread; and a priority input, coupled to said comparison logic, for specifying an instruction dispatch priority; and an override input, coupled to said comparison logic, for selectively commanding said comparison logic to output said instruction dispatch priority specified on said priority input rather than outputting said instruction dispatch priority for the thread based on which of said plurality of workload level ranges said workload level value falls into.