Patent ID: 7498897

Claim:
An impedance matching circuit comprising a distributed constant line (i) constructed on a dielectric substrate and (ii) operable to output an input signal having a preset bandwidth, wherein said distributed constant line comprises: a reactance compensating distributed constant line (i) connected to a load and (ii) having a line length of a length compensating reactance of said load; a quarter-wave distributed constant line (i) connected to said reactance compensating distributed constant line, (ii) having a line length of a quarter wavelength of said input signal and (iii) having a characteristic impedance that is set to correspond to said preset bandwidth; and an impedance inverting distributed constant line (i) connected to said quarter-wave distributed constant line and (ii) including an impedance inverting circuit that corresponds to a degree of impedance of said load and that includes one of a K inverter and a J inverter selectively corresponding to said preset bandwidth, wherein said impedance inverting distributed constant line satisfies Z 1 =(π/4)×[w/(g 1 ×g 2 ×G L )], and wherein Z 1 is the characteristic impedance that is set to correspond to the preset bandwidth, w is the preset bandwidth, g 1 and g 2 are normalized element values and G L is the conductance of the load.