Patent ID: 7295055

Claim:
A semiconductor integrated circuit, comprising: an input buffer, which captures a clock signal provided from outside, thereby providing a first output signal; a first gate, which inputs the first output signal and a mask signal, which executes a logical operation between the first output signal and the mask signal, and which outputs a second output signal, the second output signal being a result of the logical operation; an integrating portion, which, when the second output signal of said first gate changes from a first logic level to a second logic level, integrates the second output signal with a prescribed time constant, when the second output signal reaches a prescribed level between the first and second logical levels, changes a delay clock from the second logic lever to the first logic level, and when the second output signal changes from the second logic level to the first logic level, changes said delay clock from the first logic level to the second logic level; a second gate, which inputs the second output signal of said first gate and said delay clock, which executes a logical operation between the second output signal and said delay clock and which outputs a result as said mask signal; and, an output buffer, which outputs, as an internal clock, the mask signal generated from said second gate.