Patent ID: 8592302

Claim:
A method of fabricating a semiconductor device, the method comprising: forming an organic planarization layer overlying a semiconductor device structure having conductive contact elements; forming an antireflective coating layer overlying the organic planarization layer; forming a photoresist layer overlying the antireflective coating layer; removing portions of the photoresist layer to create a patterned photoresist layer having openings corresponding to the conductive contact elements; plasma etching the antireflective coating layer using the patterned photoresist layer as a first etch mask, resulting in a patterned antireflective coating layer, wherein the plasma etching forms openings with inwardly tapered sidewalls in the antireflective coating layer, and wherein the openings terminate at exposed portions of an upper surface of the organic planarization layer; after the plasma etching, directionally etching the organic planarization layer using the patterned antireflective coating layer as a second etch mask, resulting in a patterned organic planarization layer having recesses formed therein, wherein the directional etching forms the recesses with vertical sidewalls defined by, and aligned with, bottom perimeter shapes of the openings in the patterned antireflective coating layer; after the directional etching, depositing a conformal liner within the recesses; and etching the conformal liner to expose an interlayer dielectric of the semiconductor device structure.