Patent ID: 7719046

Claim:
A non-volatile memory device, comprising: a memory array formed on a substrate having a plurality of columnar structures and associated intervening trenches; and a plurality of memory cell structures, each memory cell structure comprising, a first field effect transistor having a first and second source/drain regions, wherein the first field effect transistor is formed vertically on a first sidewall of a trench, a second field effect transistor having a first and second source/drain regions, wherein the second field effect transistor is formed on a second sidewall of the trench where the first sidewall of the trench and the second sidewall of the trench are opposing sidewalls of the trench, and a floating gate structure formed in the first and second field effect transistors and is common to both the first and second field effect transistors, wherein the floating gate structure is spaced apart from a channel of the first field effect transistor by a first distance and from a channel of the second field effect transistor by a second distance where the second distance is greater than the first distance.