Patent ID: 6986004

Claim:
A first-in-first-out (FIFO) memory, comprising: an array of memory cells; a write address decoder coupled to the array, the write address decoder being configured to form a write port for the array having a programmable write port data width; a read address decoder coupled to the array, the read address decoder being configured to form a read port for the array having a programmable read port data width; a write counter configured to increment a write count according to the programmable write port data width, wherein the write address decoder is configured to decode the write count into a current write address for the array, and wherein the write counter increments responsive to the write clock; a read counter configured to increment a read count according to the programmable read port data width, wherein the read address decoder is configured to decode the read count into a current read address for the array and the read counter increments responsive to a read clock; and a flag generation module configured to assert an empty flag if the amount of data stored in the array is less than a first configurable amount and wherein the read counter is disabled from incrementing the read count if the empty flag is asserted.