Patent ID: 7039735

Claim:
A computer bus system, comprising: a bus; at least one bus master device and at least one bus slave device, the bus master device and bus slave device being connected to the bus so that the bus master device may communicate with the bus slave device over the bus, wherein i) the bus has an address space with parts of the bus address space being assigned to different devices connected to the bus; ii) the bus is a multiplexed address/data bus for transferring blocks of data in a direct address protocol communication from said master device to a slave device, each of said direct address protocol communications includes one or more burst communications including an address phase followed by a data phase, the address phase including a bus space address value; iii) the bus slave device includes an indirect address device, addressable via an indirect address protocol communication, said indirect address protocol communication includes an address register load communication followed by a data register load communication; iv) the indirect address device has a memory with memory locations identified by address values; v) the address register load communication includes a destination address value for blocks of data communicated to/from the memory of the indirect address device, wherein the slave device includes a translation device between the bus and the indirect address device, the translation device configured to translate a direct address protocol communication on the bus to an indirect address protocol communication and configured to map the bus space address value in the direct address protocol communication to the destination address value in the indirect address protocol communication.