Patent ID: 8139701

Claim:
A method comprising: receiving by a primary loop N input data bit streams, each one of the N input data bit streams comprising input data bits at an input data rate, wherein the value of N is greater than zero; generating by the primary loop a recovered clock signal based on the input data bits in the N input data bit streams, the recovered clock signal having a clock frequency and a recovered clock phase; generating by each of N sub-loops a clock signal for a corresponding one of the N input data bit streams based on the recovered clock signal having the clock frequency and a respective phase at a respective phase offset relative to the recovered clock phase and such that the recovered phase of the recovered clock signal is an average of N phases of N clock signals generated by the N respective sub-loops; detecting by the primary loop a phase difference between each of the N input data bit streams and the respective one of the N clock signals generated by the corresponding one of the N sub-loops; and adjusting the phases of the N clock signals to substantially eliminate the respective phase differences, the adjusting comprising shifting one or more of the N respective clock phase offsets of the N clock signals such that each of the N clock signals is locked to the input data bits in the respective one of the N input data bit streams.