Patent ID: 8219763

Claim:
A method in a computer aided design system for generating a functional design model of a mechanism for performing cacheline polling in a data processing system having a plurality of processes, said method comprising: generating a functional computer-simulated representation of a mechanism for requesting an action by a first process to be performed by a second process and setting a reservation on a memory location via a store operation; generating a functional computer-simulated representation of a mechanism for reading a memory location by said first process via a load operation to determine whether or not said requested action has been completed by said second process; generating a functional computer-simulated representation of a mechanism for stalling said load operation until said reservation on said memory location is lost, wherein said generating a mechanism for stalling further includes generating a mechanism for preventing said load operation in a cacheline polling loop from execution until said reservation has been reset; and generating a functional computer-simulated representation of a mechanism for resetting said reservation in said memory location by said second process after said requested action has been completed.