Patent ID: 7073039

Claim:
For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising: a decoder comprising: n inputs coupled to receive one bit each of an address from which data is to be read or to which data is to be written, and 2 n outputs; a plurality of select columns in said memory, wherein each of said plurality of select columns comprises a plurality of select cells, wherein each of said plurality of select cells comprises: a first input coupled to receive one of said 2 n outputs of said decoder via a master row select line, a second input coupled to receive a value from a select cell write line, and an output; a plurality of AND gates, wherein each of said plurality of AND gates comprises: a first input coupled to receive an output of a select cell, a second input coupled to receive a value from a corresponding master row select line, and an output; and a plurality of data columns in said memory, wherein each of said plurality of data columns comprises a plurality of rows of data cells, each row of data cells corresponds to one select cell and each row of data cells comprises: an input coupled to receive an output of a corresponding AND gate, and a data path from which data is to be read or to which data is to be written.