Patent ID: 8902666

Claim:
A method of programming memory transistors of a nonvolatile memory device, comprising: applying a first program voltage to a first selected memory transistor having its threshold voltage corresponding to a first logic state among a first set of logic states, to program the first selected memory transistor to a second logic state among a second set of logic states; applying a first target verification voltage to the first selected memory cell for verifying that the first selected memory transistor is programmed to the second logic state of the second set of logic states while applying the first target verification voltage to a second selected memory transistor as a second pre-verification voltage of the second selected memory transistor; applying a second program voltage to the second selected memory transistor having its threshold voltage corresponding to a second logic state among the first set of logic states to program the second selected memory transistor to a third logic state among the second set of logic states; and after applying the first target verification voltage to the first selected memory cell, applying a second target verification voltage to the second selected memory transistor for verifying that the second selected memory transistor is programmed to the third logic state of the second set of logic states, wherein the second target verification is higher than the first target verification voltage and lower than the threshold voltages corresponding to, the third logic state of the second set of logic states, wherein the threshold voltages corresponding to the second logic state of the first set of logic states are higher than the threshold voltages corresponding to the first logic state of the first set of logic states, wherein the threshold voltages corresponding to the third logic state of the second set of logic stales are higher than the threshold voltages corresponding to the second logic state of the second set of logic states, wherein the pre-verification voltage is lower than the threshold voltages corresponding to the third logic state of the second set of logic states, and wherein the first target verification voltage is lower than the threshold voltages corresponding to the second logic state of the second set of logic states.