Patent ID: 7183162

Claim:
A method of forming a microelectronic non volatile memory cell comprising: providing a substrate; providing a pair of spaced apart isolation bodies on the substrate, the isolation bodies including respective raised isolation portions, providing the pair comprising providing a buffer layer on the substrate; providing pillar spacers on side walls of the raised isolation portions; removing the buffer layer after providing the pillar spacers; removing the pillar spacers during removing the buffer layer; providing a tunnel dielectric on the surface of the substrate after removing the buffer layer; providing a floating gate on the tunnel dielectric; reducing a height of the isolation bodies to yield corresponding isolation regions, wherein providing the pillar spacers includes: providing a conformal spacer layer on the buffer layer and on the raised isolation regions; and anisotropically etching the conformal spacer layer in a direction toward the substrate to yield the pillar spacers; providing an interpoly dielectric on the floating gate; providing a control gate on the interpoly dielectric to yield a floating gate control gate stack; and providing source and drain regions on opposite sides of the floating gate-control gate stack to yield the memory cell.