Patent ID: 7146582

Claim:
A logic circuit optimizing method, comprising: clustering logic circuits included in inputted logic circuit information to obtain primary clusters; inserting a flip-flop to a cluster whose cluster length exceeds a predetermined cluster length, the cluster being one of the primary clusters obtained in said clustering; and re-clustering the flip-flop inserted cluster to obtain secondary clusters, wherein said inserting a flip-flop to a cluster comprises: measuring a cluster length of each of the primary clusters obtained in said clustering; selecting a cluster whose cluster length exceeds the predetermined cluster length, the cluster being one of the primary clusters obtained in said clustering; and inserting the flip-flop to the selected cluster, wherein, when there exists a cluster whose cluster length exceeds the predetermined cluster length among the primary clusters obtained in said clustering, said inserting the flip-flop to the selected cluster and said re-clustering the flip-flop inserted cluster are performed.