Patent ID: 7301362

Claim:
A method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation, comprising the steps of: (a) asserting a digital signal at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; (b) inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; (c) comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and based on the result of the comparison of the output signals: (d) if said output signals are not deemed equivalent: (1) inhibiting a resultant signal from being provided as output from the stage; (2) maintaining the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; (3) continuing to compare an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and (4) continuing steps (d)(1), (d)(2) and (d)(3) until said output signals are deemed equivalent; and (e) if said output signals are deemed equivalent: (1) providing at least one resultant signal as output from the stage; and (2) permitting a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; whereby the stage comprising duplicate asynchronous digital circuit elements is active in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.