Patent ID: 7925803

Claim:
A communication system, comprising: a first communication channel configured to couple an initiator operating with an initiator clock to a target operating with a target clock, the first communication channel including: means for storing data from the initiator in a first FIFO memory with said initiator clock; means for reading data from the initiator stored in said first FIFO memory, wherein said reading is with said target clock; means for transmitting said data read from said first FIFO memory over a first mesochronous link, the means for transmitting said data read from said first FIFO memory having: a first logic gate having a first terminal to receive a target acknowledgement signal via a second mesochronous link from said target, having a second terminal to receive a request signal from said initiator, and a third terminal to provide first and second acknowledgement signals; a second logic gate coupled to said first logic gate and having a first terminal to receive said request signal, a second terminal, and a third terminal; and first and second flip-flops each clocked by said initiator clock, said first flip flop having a first terminal coupled to said third terminal of said second logic gate and having a second terminal coupled to said second terminal of said second logic gate, said second flip flop having a first terminal coupled to said second terminal of said first flip flop and having a second terminal to provide a strobe signal; and means for storing said data transmitted over said first mesochronous link in a buffer, wherein said data are made available to the target; and a second communication channel configured to couple said target to said initiator, the second communication channel including: means for transmitting data from said target over the second mesochronous link; and means for storing said data transmitted over said second mesochronous link in a second FIFO memory, wherein said storing is with said target clock, wherein said data are made available to said initiator for reading from said second FIFO memory with said initiator clock signal.