Patent ID: 7317755

Claim:
A predicted parallel branch slicer for use in an adaptive decision feedback equalizer comprising: adders of a number of an expression M k , where M is an integer base greater than one and k is an integer exponent, commonly receiving a signal to be processed and respectively receiving M k preset values, and performing respective addition operations to generate M k output signals; slicers of a number of said expression M k , in communication with said M k adders, receiving and processing said M k output signals to obtain M k signals corresponding respectively to M k levels, respectively; a multiplexer in communication with said M k slicers, receiving said M k signals; and delay units of a number k, interconnected with one another in series and being in communication with said multiplexer, and generating k selection signals of different delay time in response to an output of said multiplexer, said selection signals being provided for said multiplexer to select one of said M k signals to be outputted; wherein the preset value V e T T received by each of said M k adders at a sampled point n is equal to the product of an optimal coefficient Ve=[C1, C2, . . . Ck] and a value T=[a(n−1), a(n−2), . . . , a(n−k)], where C1, C2, . . . , Ck are constant coefficients realized according to a simulated waveform of a channel impulse response on a transmission line of Gigabit Ethernet, and a(n−1), a(n−2), . . . , a(n−k) are levels realized at preceding k time points.