Patent ID: 6868013

Claim:
A semiconductor memory device comprising: a memory transistor having a first terminal, a second terminal and a gate electrode; a bitline; a first select transistor connected between the first terminal of said memory transistor and said bitline; and a programming circuit which applies a first voltage to a gate electrode of the first select transistor at a first time of programming, applies a second voltage to the gate electrode of the memory transistor at the first time of programming, applies a third voltage to the gate electrode of the first select transistor at a second time of programming after the first time, applies a programming voltage to the gate electrode of the memory transistor at the second time of programming, applies a program inhibition voltage to the bitline from the first time to the second time when the memory transistor is to be prevented from programming, and applies a plurality of program promotion voltages at the second time when the memory transistor is to be programmed, wherein the first voltage is higher than the third and program inhibition voltages, the program promotion voltages are lower than the third and program inhibition voltages, and the second voltage is lower than the programming voltage.