Patent ID: 8164185

Claim:
A semiconductor device, comprising: a substrate; a dielectric layer provided on the substrate; a multi-layered interconnection structure embedded in the dielectric layer; a plurality of bonding pads connected to an uppermost interconnection layer of the multi-layered interconnection structure, wherein the bonding pads are spaced apart in a first direction by isolations between adjacent bonding pads; and a passivation layer having a plurality of bonding pad openings, wherein the bonding pad openings are defined by a plurality of slits, and wherein the bonding pad openings expose the bonding pads; wherein the slits overlap the isolations of the bonding pads, wherein an edge width of the slits is larger than a center width of the slits, and wherein a width of the bonding pad openings in the first direction is greater than a width of the slits in the first direction, wherein the bonding pads are rectangular, wherein the bonding pad openings are rectangles with chamfered or rounded corners, wherein a length by which the corners of the bonding pad openings are chamfered or rounded is less than about 30% of a length of the bonding pads in the first direction, wherein the bonding pad openings are arranged at a pitch of less than about 60 μm, and wherein a minimum isolation distance between a pair of adjacent bonding pad openings is less than about 24 μm.