Patent ID: 7994947

Claim:
A circuit for generating a target frequency having an over-sampled data rate using a system clock having a different frequency, the circuit, comprising: a digital phase locked loop coupled to the system clock, the digital phase locked loop having an oscillator output and an oscillator input, wherein the digital phase locked loop comprises a digital numerical controlled oscillator comprising, a multi-bit integrator having a multi-bit numerical input and a single bit overflow output, when, in operation, the multi-bit integrator is clocked by the system clock, wherein, the multi-bit integrator comprises: a multi-bit full adder having an adder output and the multi-bit numerical input; and a multi-bit register coupled to the adder output; an extra pulse eliminator coupled to the oscillator output, the extra pulse eliminator having an extra pulse eliminator output; and one or more frequency dividers coupled to an extra pulse eliminator output.