Patent ID: 8036333

Claim:
A clock and data recovery circuit, comprising: a clock generation unit including a phase-frequency detector, a charge pump, and a voltage controlled oscillator, the clock generation unit configured to generate a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit; a mirror delay unit configured to output a plurality of delayed preamble signals based on a preamble signal of the data signal during a preamble period, the delayed preamble signals having predetermined phase differences with respect to the preamble signal; a preamble phase detection unit configured to provide the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period; and a sampling unit configured to extract data from the data signal by sampling the data signal with the clock signal, wherein the phase-frequency detector is configured to output a data phase detection signal having information on a phase difference between the data signal and the clock signal, wherein the charge pump is configured to output a control voltage that is adjusted by the preamble phase detection signal during the preamble period and by the data phase detection signal after the preamble period, wherein the voltage controlled oscillator is configured to output the clock signal having a frequency that is proportional to the control voltage, and is configured to provide the preamble phase detection unit with a plurality of delayed clock signals having predetermined phase differences with respect to the clock signal, wherein the voltage controlled oscillator includes a plurality of differential delay cells, and is configured to output the delayed clock signals that are delayed by predetermined times by the differential delay cells from output terminals of the plurality of differential delay cells, and wherein each of the plurality of differential delay cells included in the voltage controlled oscillator is configured to delay the delayed clock signals by a time that is one-eighth of a period of the preamble signal.