Patent ID: 8901990

Claim:
A semiconductor integrated circuit device comprising: a circuit block; a power supply line or a ground line configured to supply power to the circuit block; at least one pair of transistors including first and second transistors connected between the power supply line and a power supply or between the ground line and a ground potential; at least one third transistor connected between the power supply line and the power supply or between the ground line and the ground potential; first to third nodes connected to gates of the first to the third transistors, respectively; a first buffer configured to output a first control signal to the first node, the first control signal controlling a conductive state of the first transistor; and a second buffer connected between the first node and the second and third nodes, the second buffer configured to receive the first control signal and to transmit a second control signal to the second and the third nodes, the second control signal being a signal delayed from the first control signal and controlling a conductive state of the second and the third transistors, wherein when supply of the power to the circuit block starts, the second control signal controls the second and the third transistors into the conductive state after the first control signal controls the first transistor to be driven in an intermediate state between the conductive state and a shutoff state.