Patent ID: 7600167

Claim:
A flip-flop, comprising: a first latch which includes a first feedback circuit which feedbacks a output signal of the first latch to an input of the first latch, and a first selecting circuit which selects a first data input signal of the first latch when a first clock signal is a first logic level and selects an output signal of the first feedback circuit when the first clock signal is a first inverted logic level of the first logic level; and a second latch which includes a second feedback circuit which feedbacks a output signal of the second latch to an input of the second latch, and a second selecting circuit which selects an output signal of the first latch when the first clock signal is the first inverted logic level and selects an output signal of the second feedback circuit when the first clock signal is the first logic level; wherein the first feedback circuit comprises a third selecting circuit which selects an output signal of the first latch when a second clock signal is a second logic level and selects a second data input signal of the first latch when the second clock signal is a second inverted logic level of the second logic level, and outputs a signal selected by the third selecting circuit to the first selecting circuit.