Patent ID: 7656970

Claim:
A signal processor for a wireless receiver, the signal processor having: an analog front end for receiving wireless signals and producing a baseband output, said wireless signals including packets having at least a preamble, header, and payload, and an interpacket gap at other times; one or more analog to digital converters (ADC), each having an analog input and a digitized output having a resolution bit width, said analog input coupled to said baseband output to sample an energy level, each said analog to digital converter having an interpacket gap sampling rate until said sampled energy level has increased; and a baseband processor coupled to at least one said analog to digital converter digital output, said baseband processor asserting a start of packet energy signal when said sampled energy level increases, thereafter increasing the sample rate of said ADC to a rate greater than said interpacket gap sample rate until said packet has been received, after which said ADC sample rate changes back to said interpacket sample rate.