Patent ID: 6900097

Claim:
A method for forming a single-level electrically erasable and programmable read only memory, the method comprising: providing a semiconductor substrate having a first well and a second well; defining and forming a plurality of isolation regions in the semiconductor substrate, and simultaneously, a first device region is formed in the first well, a second device region is formed adjacent said first well, a third device region is formed between said second well and said second device region and a fourth device region is formed in said second well; forming a first dielectric layer having a first thickness on said semiconductor substrate; performing an ion-implanting process to form a control gate in said second device region under said first dielectric layer; removing a portion of said first dielectric layer located on said semiconductor substrate of said first well and said second well; forming a second dielectric layer having a second thickness on a remaining portion of said first dielectric layer located on said first well and said second well; removing a portion of said second dielectric layer located on said fourth device region; forming a third dielectric layer having a third thickness on said first device region, said second device region and said fourth device region, wherein said third dielectric layer and said second dielectric layer are stacked from each other to form a fourth dielectric layer having a fourth thickness on said first device region; and further, said third dielectric layer and said first dielectric layer are stacked from each other to form a fifth dielectric layer having a fifth thickness on said second device region; and forming and defining a plurality of gates on these dielectric layers of said first device region, said second device region, said third device region and said fourth device region, wherein there is the same gate located on said first device region and said second device region, which serves as the floating gate.