Patent ID: 7456666

Claim:
A delay locked loop for providing an output clock signal in response to a reference input clock signal, the delay locked loop comprising: a delay line having a plurality of serially coupled delay stages, each of the delay stages providing a delay stage output; a plurality of combining circuit cells, each of the combining cells having inputs respectively coupled to ones of a predetermined number of delay stage outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stage outputs; a selector responsive to a selection control signal for selecting an output from one of a pair of complementary outputs of one of the combining cells, to produce said output clock signal; and a phase detector responsive to said output clock signal and said reference input clock signal to control to said selector for selecting an optimum complimentary output for synchronizing the reference input clock signal and said output clock signal, the delay line including N serially coupled delay stages for providing N tap outputs to N/4 combining circuit cells, the N/4 combining cells providing N/2 evenly spaced phases of the output clock signal whose frequency is twice that of the reference input clock.