Patent ID: 8655637

Claim:
A memory access address comparator apparatus, comprising: a first comparator receiving a first reference address and a first address used by a data processor to access memory, said first comparator generating a selected one of a first greater than output, a first less than output and a first equal to output depending upon a relationship between said first address and said first reference address, and said first comparator generating a first offset signal indicative of an offset between said first address and said first reference address; a second comparator receiving a second reference address and a second address used by a data processor to access memory, said second comparator generating a selected one of a second greater than output, a second less than output and a second equal to output depending upon a relationship between said second address and said second reference address, and said second comparator generating a second offset signal indicative of an offset between said second address and said second reference address; a first compare control unit coupled to said first comparator, said first compare control unit generating a first local event signal based on one of said first offset signal, said first greater than output, said first less than output and said first equal to output; and a second compare control unit coupled to said second comparator and said first compare control unit, said second compare control unit generating a second local event signal based on one of said second offset signal, said second greater than output, said second less than output and said second equal to output, wherein said first compare control unit generates a first memory access event signal based on one of said first offset signal and said second local event signal, and said second compare control unit generates a second memory access event signal based on one of said second offset signal and said first local event signal.