Patent ID: 7741182

Claim:
A method for fabricating a dual-gate FET, comprising the steps of: forming a protrusion of a first semiconductor material on a substrate, forming a first layer of a first material on sidewalls and a top surface of the protrusion, forming a second layer of a second semiconductor material on the first layer, removing a first portion of the first layer on the top surface of the protrusion and a first portion of the second layer on the first portion of the first layer to expose the top surface of the protrusion, selectively removing a portion of the first material to a predetermined depth relative to the first and the second semiconductor material, to form a trench between the protrusion and the second layer, and to form a fin adjoining the trench, the fin formed from a portion of the second layer, forming an insulation layer on the exposed surfaces of the trench and the fin, and forming a layer of a conductive material on the insulation layer, thereby forming a gate electrode.