Patent ID: 7715474

Claim:
A decision feedback equalizer (DFE), comprising: summer circuits configured to add a dynamic feedback signal representing an h 2 tap to a received input and to speculate on an h 1 tap; data slicers configured to receive outputs of the summer circuits and sample the outputs of the summer circuits in accordance with a clock signal such that first data slicers produce even data bits and second data slicers produce odd data bits; first and second multiplexers configured to receive as input, respectively, the even data bits and the odd data bits; a first clocked output latch configured to receive an output of the first multiplexer wherein a first latch output is employed to provide a select signal for the second multiplexer and to drive the dynamic feedback signal to an even half summer circuit of the summer circuits; and a second clocked output latch configured to receive an output of the second multiplexer wherein a second latch output is employed to provide a select signal for the first multiplexer and to drive the dynamic feedback signal to an odd half summer circuit of the summer circuits.