Patent ID: 7502706

Claim:
A module-testing device for testing a module, comprising: at least one module control circuit including a first programmable logic device, said at least one module control circuit feeding a component control signal to the module; an I/O port arranged to transmit a signal to and receive a signal from an external device, and the component control signal fed to the module is fed via the I/O port; a first wiring pattern circuit including a second programmable logic device, the first wiring pattern circuit including at least part of a wiring between said at least one module control circuit and the I/O port; a configuration circuit for constructing circuit configurations of said at least one module control circuit and the first wiring pattern circuit on the basis of input information; and a tester arranged to produce an input signal to the module based on a testing control signal fed from the at least one module control circuit via the I/O port; wherein the I/O port is arranged outside the at least one module control circuit; the I/O port includes a plurality of input/output terminals; the at least one module control circuit includes a plurality of input/output terminals; the first wiring pattern circuit includes a plurality of first input/output terminals connected to the plurality of input/output terminals of the I/O port and a plurality of second input/output terminals connected to the plurality of input/output terminals of the at least one module control circuit; and the first wiring pattern circuit is arranged to selectively assign the component control signal to any one of the first input/output terminals in accordance with a signal assignment for the input/output terminals of the I/O port and to selectively assign the component control signal to any one of the second input/output terminals in accordance with a signal assignment for the input/output terminals of the at least one module control circuit, so as to enable the wiring between the at least one module control circuit and the I/O port to be freely changed.