Patent ID: 7313777

Claim:
A method of designing a layout for a circuit feature, comprising: deriving a function which relates a size and a plurality of aerial image parameters of the circuit feature to a probability of a printing fault in using a lithographic process to pattern the circuit feature; creating a layout for the circuit feature; and using the function to determine a probability of a printing fault in using the lithographic process to pattern the circuit feature and adjusting the layout of the circuit feature as necessary in view of the determined probability of printing fault, and wherein the function is determined by patterning a plurality of the circuit features wherein each of the plurality of circuit features has a different size and a correspondingly different plurality of aerial image parameters, measuring the actual printing fault rates for the plurality of circuit features, and applying a curve fit to a data set that includes the plurality of sizes, the plurality of aerial image parameters and the plurality of actual printing fault rates of the plurality of circuit features.