Patent ID: 7437591

Claim:
A programmable logic device (PLD) enabled to efficiently transfer data across different clock domains, comprising: optimizing logic, the optimizing logic including, a microprocessor having access to a phase shift range; write logic enabled to receive a write logic command from the microprocessor, the write logic causing data to be written to an external device in response to a write command from the write logic; read logic enabled to read data from the external device as directed by the microprocessor, the read logic including logic for comparing the read data to the written data to determine whether the read data is correct, the read logic further including a first register receiving the read data and a second register receiving the read data from the first register, wherein the logic for comparing compares the read data from the second register to the written data; and a phase-locked loop receiving phase control instructions from the microprocessor, the phase-locked loop modifying a phase shift of a resynchronization clock signal according to the phase control instructions, wherein the microprocessor records the phase shift and corresponding correctness of the read data for multiple phase shift values to define a phase shift window within the phase shift range, the phase shift window identifying a portion of the phase shift range having correct read data.