Patent ID: 8018399

Claim:
A pixel array, comprising: a plurality of scan lines extending along a row direction in a zigzag manner; a plurality of data lines extending along a column direction and intersecting with the scan lines; a plurality of pixels connected to the scan lines and the data lines, each of the pixels aligned in an n th row comprising: a first sub-pixel comprising a first transistor and a first pixel electrode, wherein a first gate electrode of the first transistor is connected to an (n+1)th scan line and a first drain electrode of the first transistor is connected to the first pixel electrode; and a second sub-pixel comprising a second transistor and a second pixel electrode, wherein a second gate electrode of the second transistor is connected with an n th scan line, a second drain electrode of the second transistor is connected to the second pixel electrode, and a first source electrode of the first transistor and a second source electrode of the second transistor are connected to a same data line of the data lines wherein three sides of each of the first pixel electrodes or three sides of each of the second pixel electrodes are surrounded by a corresponding scan line.