Patent ID: 8363489

Claim:
A semiconductor memory device, comprising: a power source supplier configured to supply a power source of a main power source voltage terminal to a sub-power source voltage terminal in response to a mat selection signal for selecting a corresponding memory cell mat among a plurality of memory cell mats; a bit line equalization (BLEQ) signal generator configured to be coupled with the sub-power source voltage terminal and generate a BLEQ signal corresponding to a voltage level of the sub-power source voltage terminal in response to a BLEQ control signal; a bit line equalizer configured to precharge and equalize a bit line pair in response to the BLEQ signal; and a word line driver configured to be coupled with the sub-power source voltage terminal and drive a word line, wherein the BLEQ signal generator comprises: a BLEQ signal driver configured to receive a power from the sub-power source voltage terminal only in driving the BLEQ signal to the voltage level of the sub-power source voltage terminal in response to the BLEQ control signal; and a BLEQ signal reseter configured to reset the BLEQ signal to a first voltage level in response to a BLEQ off signal, wherein the BLEO signal is generated by using a leakage current caused by floating the sub-power source voltage terminal after the word line driver is inactivated.