Patent ID: 8502273

Claim:
A method of forming a transistor with increased buffer breakdown voltage comprising: forming a substrate of a first conductivity type, the substrate having a top surface; forming a well of a second conductivity type in the substrate, the well having a top surface; forming a buffer layer to touch the top surface of the substrate and the top surface of the well, the buffer layer having a top surface; forming a channel layer to touch the top surface of the buffer layer, the channel layer including a group III-nitride and having a top surface; forming a barrier layer to touch the top surface of the channel layer, the barrier layer including a group III-nitride; forming spaced-apart metal source and drain regions that make ohmic contact with the channel and barrier layers, the metal drain region lying directly over the well; wherein the well is under the drain region and not under the source region, and also wherein a junction formed by the substrate and the well form a junction isolation barrier that acts in series with, and thereby increases the buffer breakdown voltage.