Patent ID: 8707080

Claim:
An apparatus for passing a signal from a first clock domain to a second clock domain comprising: at least four bit storage devices connected in a circular buffer, and with an output of a selected bit storage device in the circular buffer connected to an input of a next selected bit storage device in the circular buffer and with an input of a first one of the bit storage devices connected to an output of a last one of the bit storage devices; a first subset of the bit storage devices having a clock input connected to a signal originating from the first clock domain; a second subset of the bit storage devices having a clock input connected to a signal originating from the second clock domain; a first output circuit, connected to at least two outputs of the first subset of the bit storage devices, and to produce a first clock domain data enable signal; and a second output circuit, connected to at least two outputs of the second subset of the bit storage devices, and to produce a second clock domain enable signal.