Patent ID: 8053310

Claim:
A method of manufacturing an integrated circuit device, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a surface region; forming a planarized dielectric layer overlying the surface region, the planarized dielectric layer having a capacitor region and a peripheral region, the peripheral region having a recessed region, the recessed region having a dimension of about 1 micron and less; forming one or more cylindrical stack capacitor structures within the capacitor region; forming a blanket rugged polysilicon material overlying the one or more cylindrical stack capacitor structures and the peripheral region, the blanket rugged polysilicon material having a portion being trapped by a portion of the peripheral region including the recessed region; forming a masking layer overlying the one or more cylindrical stack capacitor structures while exposing at least the recessed region in the peripheral region; subjecting at least the recessed region including the portion of the trapped blanket rugged polysilicon material to a plasma etching environment to cause removal of the trapped blanket polysilicon material; and processing using a chemical mechanical planarization process an upper region including at least the exposed recessed region to remove any residual blanket rugged polysilicon material and at least one other layer overlying a portion of the peripheral region.