Patent ID: 8607175

Claim:
A computer-implemented method executed by at least one processor for identifying at least one logic block in a synthesized logic design that has specified inputs, wherein the synthesized logic design includes a plurality of logic blocks and a plurality of inputs, the method comprising the steps of: providing the at least one processor that performs the steps of: specifying the specified inputs; specifying a number of levels in the synthesized logic design to analyze; performing a forward linear trace to identify inputs at each level for each logic block without regard to logical function of each logic block; identifying from the identified inputs at least one potential equivalency point from the forward linear trace; and following completion of the forward linear trace for the specified number of levels, performing a reverse logical trace from the at least one potential equivalency point to identify equivalent logic, wherein the equivalent logic comprises the identified at least one logic block in the synthesized logic design that has the specified inputs.