Patent ID: 7811937

Claim:
A method of fabricating a thin film transistor array substrate comprising: forming gate patterns including a gate line and a gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate patterns; forming source/drain patterns including a data line, a source electrode, a drain electrode and a storage electrode on the gate insulating; depositing a passivation film on the gate insulating layer and the source/drain patterns; forming a photo-resist pattern on the passivation film, and patterning the passivation film and the gate insulating layer using the photo-resist pattern as a mask to form a passivation film pattern and a gate insulating pattern so that a portion of the substrate is exposed; depositing a transparent electrode material on the substrate and the photo-resist pattern; and removing the photo-resist pattern and the transparent electrode material deposited on the photo-resist pattern to form a transparent pattern including a pixel electrode so that the transparent pattern is non-overlapped with the passivation film pattern, wherein the removing the photo-resist pattern and the transparent electrode material including: dipping the substrate having the photo-resist pattern and the transparent electrode material in a first stripper to remove the photo-resist pattern and the transparent electrode material; removing a residual photo-resist pattern and a residual transparent electrode material left on the substrate by jetting air to the substrate by using an air knife after dipping the substrate in the first stripper; and removing particles of the residual photo-resist pattern and the residual transparent electrode material left on the substrate by jetting a second stripper to the substrate by using a jet nozzle after removing the residual photo-resist pattern and the residual transparent electrode material.