Patent ID: 7919405

Claim:
A method of manufacturing a semiconductor device, comprising: a first step of forming an N-type silicon layer containing N-type impurity on an N-channel transistor forming region of a semiconductor substrate, and forming a P-type silicon layer containing P-type impurity on a P-channel transistor forming region of the semiconductor substrate; a second step of forming a first silicide layer on the N-type silicon layer, and forming a second silicide layer having a plurality of silicide grains disposed discontinuously in a direction substantially parallel with the surface of the semiconductor substrate on the P-type silicon layer; a third step of forming a continuous silicon film on the first silicide layer, on the surface of the P-type silicon layer exposed on the discontinuous part of the second silicide layer, and on the surface of the second silicide layer; a fourth step of forming a metal nitride layer on the silicon film; a fifth step of forming a metal layer on the metal nitride layer; and a sixth step of patterning the metal layer, the metal nitride layer, the silicon film, the first silicide layer, the second silicide layer, the N-type silicon layer, and the P-type silicon layer, thereby forming a first gate electrode including the N-type silicon layer in the N-channel transistor forming region, and forming a second gate electrode including the P-type silicon layer in the P-channel transistor forming region, respectively.