Patent ID: 8645897

Claim:
A design verification apparatus for verifying an integrated circuit design, wherein the integrated circuit (IC) design includes a plurality of Intellectual Property (IP) cores and the design verification apparatus includes a plurality of verification modules, the design verification apparatus comprising: a memory used to store the integrated circuit design; and a processor in communication with the memory, wherein the processor: configures a first set of connections between the plurality of IP cores and the corresponding plurality of verification modules based on a first connection database; initiates verification of each IP core independently by way of corresponding verification module, using the first set of connections and a first set of test patterns generated by the design verification apparatus; configures a second set of connections between the plurality of IP cores and the plurality of verification modules based on a second connection database generated using the first connection database; initiates verification of the plurality of IP cores together by way of corresponding plurality of verification modules, using the second set of connections and a second set of test patterns generated by the design verification apparatus; and updates the second connection database based on the verification of the plurality of IP cores together.