Patent ID: 7714394

Claim:
A Complementary Metal Oxide Semiconductor (CMOS) device, comprising: an isolation layer provided in a semiconductor substrate to define first and second active regions; a first gate pattern crossing over the first active region; a first elevated source region and a first elevated drain region disposed at both sides of the first gate pattern and provided on the first active region; a first gate spacer interposed between the first gate pattern and the first elevated source/drain region; a second gate pattern crossing over the second active region; a second elevated source region and a second elevated drain region disposed at both sides of the second gate pattern and provided on the second active region; a second gate spacer covering edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern and wherein a distance between the first gate pattern and a sidewall of the first elevated source/drain regions facing the first gate pattern is greater than a distance between the second gate pattern and a sidewall of the second elevated source/drain regions facing the second gate pattern, wherein the second gate spacer comprises: a second inner gate spacer interposed between the second gate pattern and the second elevated source/drain regions, the second inner gate spacer covering a sidewall of the second gate pattern; and a second outer gate spacer covering edges of the second elevated source/drain regions adjacent to the second inner gate spacer and an upper sidewall of the second inner gate spacer, and wherein edges of the second elevated source/drain regions have first top surfaces which are parallel to a top surface of semiconductor substrate, and wherein the first top surfaces of the edges of the second elevated source/drain regions are in direct physical contact with the second outer gate spacer of the second gate spacer; first high-concentration source/drain regions formed in the first active region under the first elevated source/drain regions; first low-concentration source/drain regions provided in the first active region under the first gate spacer, the first low-concentration source/drain regions contacting the first high-concentration source/drain regions; second high-concentration source/drain regions formed in the second active region under the second elevated source/drain regions; and second low-concentration source/drain regions provided in the second active region under a region between the second gate pattern and the second elevated source/drain regions, the second low-concentration source/drain regions contacting the second high-concentration source/drain regions.