Patent ID: 7984272

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: a processor, comprising: at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline is configured to begin executing an instruction in a common issue group after beginning to execute a corresponding instruction of the common issue group in the first pipeline; and circuitry configured to: determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, wherein determining if the first instruction being executed in the first pipeline modifies data in the data register includes decoding the first instruction and the second instruction, and providing decoding bits indicating whether the modified data should be forwarded from the first pipeline to the second pipeline, wherein decoding the first and the second instruction is performed after the first instruction and the second instruction are fetched from a level two cache and before the first instruction and the second instruction are placed in a level one cache; and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline.