Patent ID: 8722455

Claim:
A fabrication method of a phase change memory structure having low-k dielectric heat-insulating material, characterized by comprising the following steps: (1) fabricate diode array by standard CMOS process; (2) form a first low-k dielectric heat-insulating layer of a thickness in the range of 50 nm to 1000 nm on the diode array; (3) form a plurality of first holes of a diameter in the range of 30 nm to 300 nm on the first low-k dielectric heat-insulating layer, wherein the bottom of each first hole is connected to the top of each diode in the diode array; (4) fill heating electrode material in said holes, and then carry out the chemical mechanical polishing (CMP) process to remove the remaining heating electrode material from the surface so as to form the cylindrical heating electrode array; (5) form a second low-k dielectric heat-insulating layer of a thickness in the range of 50 nm to 200 nm on the cylindrical heating electrode array; form a plurality of second holes of a diameter in the range of 50 nm to 500 nm on the second low-k dielectric heat-insulating layer, wherein the bottom of each second hole is connected to the top of each cylindrical heating electrode in the cylindrical heating electrode array; (6) form an anti-diffusion dielectric layer of a thickness in the range of 1 nm to 30 nm in the second holes; (7) fill phase change material in the second holes after the formation of an anti-diffusion dielectric layer therein, and then carry out the CMP process to remove the remaining phase change material from the surface so as to form the cylindrical reversible phase change resistor array; (8) form a layer of electrode material on the cylindrical reversible phase change resistor array; (9) form top electrodes of the phase change memory cell array by lithography and wet etch.