Patent ID: 8504763

Claim:
A memory device comprising: a memory; and a controller in communication with the memory, wherein the controller is configured to: power-up in a read-only mode; receive a command from a host device to switch to a read/write mode; in response to the command from the host device, switch from the read-only mode to the read/write mode; and while in the read/write mode: receive a write command from the host device to write data to a first logical address, wherein the first logical address is mapped in the memory device's logical-to-physical address map to a first physical address of the memory; perform the write command if there is available memory space by performing the following: determine if the first physical address of the memory has already been written to; if the first physical address of the memory has not already been written to, write the data in the first physical address of the memory; and if the first physical address of the memory has already been written to: instead of writing the data to the first physical address of the memory, write the data to a second physical address of the memory, wherein the second physical address of the memory has not already been written to, and update the logical-to-physical address map so that the first logical address is mapped to the second physical address instead of the first physical address.