Patent ID: 7443221

Claim:
A method for generating a second clock from a first clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer, the method comprising: generating cycles of the second clock, utilizing rising and falling edges of the first clock, wherein said cycles of the second clock have the duration of a first number of cycles of the first clock; generating other cycles of the second clock, wherein the other cycles have the duration of a second number of cycles of the first clock; calculating a first timing error between a time associated with a first edge of the first clock and a time for an edge at the frequency for the second clock; calculating a second timing error between a time associated with a second edge of the first clock and the time for an edge at the frequency for the second clock; generating an edge at the time of the first edge if the first timing error is less than the second timing error; and generating an edge at the time of the second edge if the second timing error is less than the second timing error.