Patent ID: 7072431

Claim:
A method of regenerating a bit timing signal from an encoded digital signal in a receiver using a predetermined sample rate F s , said method comprising the steps of: generating an input pulse signal in response to predetermined transitions of said encoded digital signal; generating a clock count signal having a variable clock period according to cyclical counting of said clock count signal up to a count value S at said predetermined sample rate, said count value alternating between an upper value S u and a lower value S l so that said variable clock period has an average length substantially equal to a data bit period of said encoded digital signal; synchronizing said clock count signal with said encoded digital signal by 1) counting said input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if said pulse count is greater than a pulse threshold and said sample count is greater than a sample threshold; and resetting said clock count signal and said pulse count in response to said sync signal.