Patent ID: 8570800

Claim:
A memory, comprising: a plurality of memory cells, each of the memory cells including a memory element with first and second terminals, and first and second diodes as program selectors, the first and second diodes having a first terminal associated with a first type of dopant and a second terminal associated with a second type of dopant, the first diode having the first terminal coupled to the second terminal of the memory element, and the second diode having the second terminal coupled to the second terminal of the memory element; a plurality of local wordlines, each coupled to a plurality of the memory cells via the second terminal of the first diodes or to the first terminal of the second diode and having a first resistivity; a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity; and a plurality of bitlines, each coupled to a plurality of the memory cells via the first terminal of memory element, wherein, for each of the memory cells, the memory element is configured to be programmable by turning on the first diode while cutting off the second diode for one state and by turning on the second diode while cutting off the first diode for another state.