Patent ID: 7865325

Claim:
A semiconductor device failure parsing method, comprising: forming a plurality of defective cells to have at least one failure cause; measuring electric characteristics of each of the plurality of defective cells; storing the measured electric characteristics of each of the plurality of defective cells in a database; and judging failure causes of a failed chip of a semiconductor wafer based on the database, the judging comprising: (a) resetting a chip count number; (b) selecting a chip from the semiconductor wafer corresponding to the chip count number; (c) inputting a test pattern into the selected chip; (d) reading the input test pattern from the selected chip; (e) checking whether the selected chip is defective; (f) when the selected chip is judged to be defective, comparing electric characteristics of the selected chip with the measured electric characteristics stored in the database to judge failure causes of the selected chip; (g) outputting a comparison result responsive to the selecting and the comparing; (h) incrementing the chip count number; and (i) repeating the steps (b) to (h) until all chips on the wafer have been selected.