Patent ID: 6946731

Claim:
A power layout structure of a main bridge chip on a motherboard for providing a stable power source to the main bridge chip substrate and the motherboard, comprising: a first signal layer which is on top of the layout structure of the main bridge chip, wherein the first signal layer includes at least one power layout layer, wherein the power layout layer further includes at least one decoupling capacitor which is connected between the power layout layer and one of reference bonding pads on a side of the power layout layer; a bottom solder layer which is at bottom of the layout structure of the main bridge chip, wherein the bottom solder layer includes at least one power layout layer, wherein the power layout layer further includes at least one decoupling capacitor which is connected between the power layout layer and at least one of reference solder balls on a side of the power layout layer, where the reference bonding pads and the reference solder balls are coupled with a reference voltage source; a first voltage reference layer located underneath the first signal layer, wherein the first voltage reference layer is coupled with the reference voltage source to provide a reference voltage to the first signal layer; and a second voltage reference layer located on top of the bottom solder layer, wherein the second voltage reference layer is coupled with the reference voltage source to provide a reference voltage to the bottom solder layer.