Patent ID: 7660177

Claim:
A non-volatile memory device comprising: an interface circuit for receiving a plurality of signals, substantially simultaneously, wherein said plurality of signals for providing multiplexed address and data and command signals in a serial format; an input buffer for storing a plurality of said plurality of signals received in serial format and for reconstituting said address, data and command signals, and having an output; a command circuit for receiving the output of said input buffer for storing the command signals therefrom; an address circuit for receiving the output of said input buffer for storing the address signals therefrom; a data buffer circuit for receiving the output of said input buffer for storing the data signals therefrom; an array of non-volatile memory cells, said array for storing data from and for providing data to the data buffer circuit in response to address signals from the address circuit; a state machine connected to the command circuit for controlling said array of non-volatile memory cells; and an output buffer for receiving data from the data buffer circuit and for providing data to the interface circuit.