Patent ID: 6929973

Claim:
A method for packaging an electronic component, in which leads that are plated with solder including lead (Pb) are provided at a narrow pitch, on a printed circuit board on which lands have been formed in a pattern of arrangement that corresponds to said leads wherein said leads are soldered to said lands, said method comprising: preparing a metal mask in which openings are formed in a pattern of arrangement that corresponds to said lands; arranging said metal mask on said printed circuit board such at said openings are each positioned on said lands; filling said openings with a solder paste; removing said metal mask; mounting said electronic component on said printed circuit board such that said leads are each mounted on said solder paste; and causing reflow of said solder paste to solder said leads to respective said lands; wherein at least one of said openings of said metal mask has greater larger area than the area of the corresponding one of said lands, and a proportion of lead (Pb) melted from said leads to the total amount of solder that solders said leads to said lands is controlled in a suitable range by adjusting areas of said openings.