Patent ID: 7750975

Claim:
An apparatus comprising: a phase detector to receive a reference signal at a reference frequency and a feedback signal and to detect a phase relationship between the reference signal and the feedback signal, the phase detector being clocked by a clock signal at a clock frequency which is sufficiently higher than the reference frequency to sample the reference signal to generate a phase difference signal as an output from the phase detector to indicate the phase relationship; a digital loop filter clocked at the clock frequency to receive the phase difference signal and to filter the phase difference signal to generate an offset signal as an indication of the phase relationship between the reference signal and the feedback signal; a phase accumulator coupled to receive a value associated with a frequency of an output signal and also coupled to receive the offset signal, in which the phase accumulator provides offset adjustments to the value setting the frequency of the output signal to generate a phase corrected signal and the feedback signal; a sinusoid generator coupled to receive the phase corrected signal to generate an output signal that tracks to the reference signal; and a down sampler to down sample the output signal of the sinusoid generator to generate a down-sampled signal at a frequency lower than the clock frequency, wherein the down-sampled signal is used for generating a pilot signal for a BTSC encoder circuit.