Patent ID: 8448017

Claim:
A memory apparatus, comprising: a memory having a main memory area and a replacement area; and a memory controller having a function of issuing instructions corresponding to commands to carry out transmission and reception of data and reading of status information of said memory; said memory including a function of issuing, when busy time required for writing does not come to an end within a fixed period of time, an error notification that the memory cell is defective to said memory controller, a replacement processing function of changing over a memory cell in said main memory area with which an error has occurred with a memory cell in said replacement area and of storing an address of a defective memory cell and automatically changing over accessing to the defective memory cell upon address decoding to accessing to the replacement memory cell, and a save area having a plurality of regions each for saving an address of a defective memory cell and data in pair; said save area including, in each of the regions in each of which an address of a defective memory cell and data are saved in pair, a flag indicative of whether the region is in a used state or in an unused state; said memory further including a function of retaining, when a defective memory cell newly appears, an address of the new defective memory cell and data into one of unused regions of the save area and setting the flag to the used state, and a function of setting, when the replacement process is carried out and the information in the save area becomes unnecessary, the flag to the unused state, wherein said memory controller discriminates, from among errors included in status information outputted from said memory, any error which requires a replacement process and instructs said memory to carry out a replacement process of the defective memory cell.