Patent ID: 7028067

Claim:
A system for generating floating-point test-cases for verifying the operation of a floating-point arithmetic unit, the system comprising a processing unit which includes: (a) an exponent generator, for generating floating-point exponents; (b) a significand generator, for generating floating-point significands; and (c) a fixed-point generator coupled to said exponent generator and to said signficand generator; wherein said processing unit is configured to receive a specified arithmetic operation, a specified rounding mode, at least one input operand mask, and an output result mask; and wherein said processing unit is configured to output a set of floating-point numbers which includes at least one input operand compatible with said at least one input operand mask, and an output result compatible with said output result mask; and wherein said output result corresponds to said specified arithmetic operation on said at least one input operand for said specified rounding mode.