Patent ID: 8514607

Claim:
A semiconductor memory device comprising: a memory cell array configured of memory cells, a plurality of which is arranged respectively in a row direction and a column direction, each memory cell including a variable resistance element in which an electrode is supported at each of two terminals of a variable resistor, a resistance state is defined by a resistance property between the two terminals and transitions between two or more different resistance states by applying electric stress between the two terminals, and one resistance state after the transition is used for storing information, wherein in a random writing of one or more selected memory cells in the memory cell array, either an erasing action or a programming action is performed on each of the selected memory cells, in the erasing action, an erasing voltage pulse for transitioning the resistance states of the variable resistance elements of the selected memory cells to an erased state having a lowest resistance value is applied to the selected memory cells, regardless of the resistance states of the variable resistance elements of the selected memory cells, and in the programming action, the erasing voltage pulse is applied to the selected memory cells, and a first programming voltage pulse for transitioning the resistance states of the variable resistance elements of the selected memory cells from the erased state to a predetermined resistance state is applied to the selected memory cells, regardless of the resistance states of the variable resistance elements of the selected memory cells.