Patent ID: 8493106

Claim:
A semiconductor device comprising: a flip-flop circuit that is driven in synchronization with a clock signal and retains data according to a data retention signal; a clock control circuit that controls the clock signal supplied to the flip-flop circuit; a controller that supplies an input clock signal to the clock control circuit, supplies the data retention signal to the flip-flop circuit, and controls the clock control circuit, and an exclusive-OR circuit that receives the input clock signal output from the controller at one input and a select signal at another input, and switches between non-inversion and inversion of the input clock signal according to the select signal, wherein, when the flip-flop circuit is driven by a positive edge of the clock signal and retains data at a low level of the clock signal, the controller controls the clock control circuit so as to supply a low-level clock signal to the flip-flop circuit after the input clock signal is fixed and before the flip-flop circuit retains data, when the flip-flop circuit is driven by a negative edge of the clock signal and holds data at a high level of the clock signal, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop circuit after the input clock signal is fixed and before the flip-flop circuit retains data, the flip-flop circuit comprises a first flip-flop that is driven by a positive edge of the clock signal and is capable of retaining data when the clock signal is at the low level, the clock control circuit comprises a first clock control circuit that controls the clock signal supplied to the first flip-flop, and the controller controls the first clock control circuit so as to supply the input clock signal to the first clock control circuit, supply the data retention signal to the first flip-flop, and supply a low-level clock signal to the first flip-flop after the input clock signal is fixed and before the first flip-flop retains data.