Patent ID: 7484047

Claim:
A terminal apparatus including a main processor and a coprocessor, the main processor connected to a first data bus to control a communication function for a wireless terminal, and the coprocessor connected between the first data bus and a second data bus to perform a multimedia function for the wireless terminal under a control of the main processor, the terminal apparatus comprising: a first flash memory connected to the second data bus and having a first area storing operation programs of the main processor and a second area storing operation programs of the coprocessor; a second flash memory connected to the second data bus and having a first area storing data requiring non-volatility of the main processor, and a second area storing data requiring non-volatility of the coprocessor; a random access memory connected to the second data bus, the random access memory having a first area temporarily storing data occurring during an operation of the main processor and allowing a portion of a code which is executed in a random access memory area to be loaded in the first area of the random access memory, and having a second area temporarily storing data occurring during an operation of the coprocessor and allowing a portion of the code which is executed in the random access memory area to be loaded in the second area of the random access memory; a cache memory connected between the first data bus and the second data bus, the cache memory caching the data and the codes of the first areas of the random access memory and the flash memories; and a cache controller connected to the first data bus, the cache controller determining whether or not a cache hit or a cache miss occurs in the cache memory, controlling the main processor to access the cached data or codes when the cache hit occurs in the cache memory, and accessing at least one of the flash memories and the random access memory to store the data or the codes in the cache memory and controlling the main processor to access the cache memory when the cache miss occurs in the cache memory.