Patent ID: 8917804

Claim:
A clock data recovery circuit comprising: an oscillator configured to generate a pulse signal; a first control circuit unit configured to start and stop an operation of the oscillator according to existence or absence of an input of a Pulse Width Modulation (PWM) signal; a counter configured to count the pulse signal so as to hold a count value in N number of bit counters, wherein N is an integer greater than 1; a register including M number of bit registers, wherein M is a natural number smaller than N, the register being configured to transmit upper M bits of the count value held by the N number of bit counters, as a reference count value, in response to input of a transmission signal; a comparator configured to compare the count value held by the counter with the reference count value held by the register and output a timing clock when the count value exceeds the reference count value; and a second control circuit unit configured to be synchronized with a rising timing of the PWM signal to generate the transmission signal for transmitting the reference count value from the counter to the register and a reset signal for resetting the counter.