Patent ID: 7036038

Claim:
A converter circuit for performing transfer of control signals between a first device and a second device in connection with an interconnection bus, the first device operating according to a first clock signal at a first frequency and the second device operating according to a second clock signal at a second frequency, the clock frequencies being in one of a first ratio to one another corresponding to unity, a second ratio and a third ratio, and in which the control signals include an access-request signal to be transferred from the first device to the second device, a grant signal to be transferred from the second device to the first device, and a response-to-request signal to be transferred from the second device to the first device, the converter circuit comprising: manipulation circuit elements identifying respective propagation paths through the converter circuit for the access-request signal, the grant signal, and the response-to-request signal; and a logic network having three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing manipulation circuit elements in the propagation paths, so that a first state of the logic network corresponds to the first ratio, said manipulation elements being neutral in the propagation paths so that the access-request signal, the grant signal, and the response-to-request signal propagate through the converter circuit substantially without manipulation, a second state of the logic network corresponds to the second ratio, said manipulation elements controlling the propagation paths so that the request signal is selectively delayed in the converter circuit according to logic levels of the first clock signal and the second clock signal at an instant of receiving the request signal, the grant signal is delayed in the converter circuit according to logic levels of the first clock signal and the second clock signal at an instant of receiving the grant signal, and the response-to-request signal is delayed in the converter circuit according to the logic levels of the first clock signal and the second clock signal at an instant of receiving the response-to-request signal to prevent a setup time violation, and the response-to-request signal is shortened, and a third state of the logic network corresponds to the third ratio, said manipulation elements being neutral in the propagation path of the request signal so that the request signal propagates through the converter circuit substantially without manipulation, the grant signal being delayed in the converter circuit, and the response-to-request signal being shortened to prevent double sampling by the first device.