Patent ID: 7799650

Claim:
A method for forming a semiconductor device on a semiconductor material layer, comprising: forming a gate structure over the semiconductor material layer having a metal layer directly on a gate dielectric; forming a first nitride spacer directly on the gate structure, wherein the first nitride spacer has a width less than 90 Angstroms; forming source/drain extensions in the semiconductor material layer using the nitride spacer as a mask; forming an oxide liner overlying the gate structure and the source/drain extensions and directly on the first nitride spacer; forming a second nitride spacer directly on the oxide liner; forming source/drain regions in the semiconductor material layer using the second nitride spacer as a mask; using an etching process that is selective to the oxide liner, removing the second nitride spacer; using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner; forming silicide regions overlying the source/drain regions and the gate structure; and forming a stressor layer overlying the silicide regions and the first nitride spacer to generate stress in a channel region of the semiconductor device.