Patent ID: 8732551

Claim:
A method for validating memory codes in memory banks, comprising: reserving a block of exclusive accesses for a memory validation manager to exclusively access a logical memory bank, wherein the logical memory bank includes a plurality of memory lines of a predetermined data length, and wherein the block of block of exclusive accesses includes a first read operation of a first memory line in the logical memory bank, which is followed by a second read operation of a second memory line in the logical memory bank, which in turn is followed by a first write operation of the first memory line in the logical memory bank, which in turn is followed by a second write operation of the second memory line in the logical memory bank; determining whether an indication is received in response to the first read operation that the validation code associated with the first memory line is valid or is invalid; and if the indication that the validation code associated with the first memory line is invalid, generating validity information from stored information received during the first read operation and storing the generated validity information during the first write operation.