Patent ID: 8904192

Claim:
A method for protecting a programmable cryptography circuit, said method comprising: using gates comprising table-based cells defining the logic function of each of the table-based cells, the programmable cryptography circuit being configured to integrate a differential network configured to make calculations on binary variables, each of the binary variables comprising pairs of signals, the differential network comprising a first network of cells implementing logic functions on a first component of the pairs and of signals and a second network of dual cells operating in complementary logic on the second component of the pairs of signals, and making calculations on the binary variables during: a precharge phase, in which the binary variables are put into a known state at an input of each cell of the differential network, an evaluation phase, in which a calculation is made by each cell of the differential network, and a synchronization phase, in which multiple signals representing multiple input binary variables are received and logic takes place on the multiple input binary variables, the synchronization phase being carried out before each of the precharge and evaluation phase, and the synchronization phase being carried out on a signal of the multiple signals having a greatest delay.