Patent ID: 8084326

Claim:
A method for manufacturing a semiconductor device, the method comprising: forming first, second, and third gates each extending into a substrate; forming a first landing plug contact hole exposing the substrate between the first and the second gates and a second landing plug contact hole exposing the substrate between the second and the third gates, the first landing plug contact hole being formed in a bit line contact region and the second landing plug contact hole being formed in a storage node contact region; forming a first conductive layer over sidewalls of the first and the second landing plug contact holes, the first conductive layer being formed conformal to the first and the second landing plug contact holes; forming first and second insulating layers ( 30 ) to fill the first and the second landing plug contact holes, respectively; forming a third insulating layer ( 32 ) over the first and the second insulating layers; etching the third insulating layer over the second insulating layer to form a storage node contact hole and etching the second insulating layer to open the second landing plug contact hole, wherein the storage node contact hole is configured to have a bottom opening joined to a top opening of the second landing plug contact hole; and forming a second conductive layer in the storage node contact hole and the second landing plug contact hole to form a storage node contact plug and a landing plug, the second conductive layer having a higher conductivity than the first conductive layer.