Patent ID: 7863932

Claim:
An integrated circuit, comprising a L-level permutable switching network (L-PSN); wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches: wherein the (L+2) levels of conductors comprises: for each i=[1:L], (I[i]/D [i])>1, D[1]>1, Lâ‰§1, at least one j where D[j]>2 for a j selected from j=[1:L], the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors, wherein each of the D[i] sets of conductors comprises (I[i]/D[i]) number of conductors; an 0-th level of conductors of I[0] number of conductors, wherein (I[0]/Î i=[1:L] D[i])>1; an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors, wherein D[L+1]>2, each of the D[L+1] sets of conductors comprises (I[L+1]/D[L+1]) number of conductors and (I[L+1]/D[L+1])=Î i=[1:L] D[i]; wherein each i-th set of the (L+1) sets of switches comprises at least (T[i]Ã—D[i]) number of switches for i=[1:L+1] where T[i]=(I[iâˆ’1]âˆ’D[i]+1); wherein the Î i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module selected from switching networks and logic cells; wherein for each i=[1:L+1], at least T[i] number of conductors of the I[iâˆ’1] number of conductors of the (iâˆ’1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective plurality of at least T[i] number of switches of the i-th set of switches without requiring traversal of any other conductors.