Patent ID: 7445948

Claim:
A method of making an array of thin film transistors (TFTs) comprising: providing a substrate; forming a plurality of gate electrodes and gate address lines on the substrate, the gate address lines being connected to the gate electrodes; forming a gate insulating layer over the gate electrodes; forming a semiconductor layer over each of the gate electrodes; forming source and drain electrodes with a channel there between and a plurality of drain address lines; forming a photo-imageable insulating layer having a dielectric constant less than about 5.0 over a substantial portion of the substrate; forming a plurality of vias in the photo-imageable insulating layer, at least one via corresponding to a thin film transistor in the array; and forming a plurality of pixel electrodes over the photo-imageable insulating layer, each pixel electrode contacting a respective source electrode-of the thin film transistor through the at least one via; wherein the pixel electrode on the substrate overlaps at least one of the gate address and drain address lines whereby the pixel electrodes are insulated from the gate address and drain address lines in the overlap area by the photo-imaged insulating layer, and wherein the parasitic capacitance corresponding to an overlap of said each pixel electrode to one of the gate address and drain address lines is no greater than 0.01 pF.