Patent ID: 7675119

Claim:
A semiconductor device comprising: an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate, wherein said P-type gate electrode comprises: a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second silicon layer formed on said first silicon layer; and a first metal containing layer formed on said second silicon layer, wherein said N-type gate electrode comprises: a third silicon layer formed as the lowest layer and doped with an N-type impurity; a fourth silicon layer formed on said third silicon layer; and a second metal containing layer formed on said fourth silicon layer, wherein at least one of said second silicon layer and said fourth silicon layer is doped with no impurity or an impurity of a conductive type opposite to that of the impurity in a corresponding one of said first silicon layer and said third silicon layer, and wherein said at least one of said second silicon layer and said fourth silicon layer is configured to substantially prevent said impurity in said corresponding one of said first silicon layer and said third silicon layer from diffusing toward said corresponding one of said first metal containing layer and said second metal containing layer.