Patent ID: 7495462

Claim:
A method of manufacturing wafer-level packages for integrated circuits, the wafer-level packages comprising a base wafer that is fixedly attached to and in operational association with a cap wafer having a through-wafer electrical interconnection, the method comprising: providing cavities having low-aspect ratio side-walls on both a front surface and a back surface of a polished semiconductor substrate; providing an interconnection via between adjacent front surface cavities using a cavity disposed on the back surface; applying a highly-electrically conductive metal/solder to surfaces of the interconnection via to provide through-wafer, low aspect ratio side-wall, electrical interconnections; and fixedly attaching the cap wafer to the base wafer to form a composite wafer, wherein electrical contact points disposed on a front surface of the base wafer are electrically-coupled to the through-wafer, low aspect ratio side-wall electrical interconnections on the front surface of the cap wafer, and the through-wafer, low aspect ratio side-wall, electrical interconnections on the cap wafer are electrically-coupled to electrical contact points disposed on the rear surface of the cap wafer.