Patent ID: 7948797

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cell units each including memory cells connected in series, a plurality of bit lines each connected to one end of corresponding one of the memory cell units, and a common source line commonly connected to the other ends of the plurality of the memory cell units, each of the memory cells storing a first data state and a second data state that provides a smaller cell current than the first data state at the time of data reading; a sense amplifier operative to read data from a selected memory cell via the bit line; a control circuit operative to control a read operation of the sense amplifier; and a cell source monitoring circuit operative to detect a voltage of the common source line while the data is read from the selected memory cell, compare the detected voltage of the common source line with a reference voltage, and output a read control signal, the sense amplifier being configured to be capable of reading data from the selected memory cell through at least two cycles including a first reading cycle and a second reading cycle, the second reading cycle being to be carried out after the first reading cycle, and the control circuit being configured to perform control to determine whether the data reading is to be ended after the first reading cycle or the second reading cycle is to be carried out, based on the read control signal.