Patent ID: 7403542

Claim:
A hardware engine for completely offloading Transmission Control Protocol/Internet Protocol (TCP/IP) protocol processing both in a transmit path and a receive path from a host system software stack, comprising: an inbound MAC Receive state machine for receiving a network packet and passing the network packet to an inbound memory buffer; an inbound IP verifier hardware state machine for verifying IP packet headers if the received packet from the network is an IP packet; an inbound IP fragment processing state machine for processing and reassembling IP packet fragments into an IP datagram that is stored in a local memory for the hardware engine; wherein the inbound IP fragment processing state machine assigns a timer to each IP datagram with a timeout value, and if a timeout occurs then the entire datagram is removed from a reassembly list and storage space associated with the timed out datagram is assigned to a free buffer list that is maintained by a buffer list manager, where the buffer list manner implements a hardware state machine to manage storage space in the local memory and grants free buffer space when available to the inbound IP verifier hardware state machine; and an inbound TCP hardware state machine for (a) processing TCP segments received from an IP layer by completely offloading TCP/IP protocol stack processing from the host system software stack to hardware; (b) re-ordering out of order TCP segments and then transferring the TCP data to the host system; and (c) transferring data from an iSCSI connection to a processor that processes iSCSI frames: wherein the inbound TCP hardware state machine retrieves a network control block from a TCP table manager and updates network state information in the network control block and maintains a segment reassembly list for each network connection; wherein the inbound IP verifier state machine passes non-IP data packets to the host system via an inbound direct memory access engine (IDE).