Patent ID: 8362932

Claim:
A circuit comprising a time to digital converter ( 14 ) and an oscillator circuit having an oscillator ( 10 ) coupled to the time to digital converter ( 14 ), the time to digital converter ( 14 ) comprising: a delay circuit ( 22 ) with a delay circuit input and a plurality of taps, the delay circuit ( 22 ) being configured to output respective, differently delayed versions of a signal from the delay circuit input at said taps; a sampling register ( 24 ) with a clock input and data inputs coupled to the taps, configured to sample data from the data inputs in response to an active transition at the clock input; a feed circuit ( 20 ) coupled to the oscillator output, the delay circuit input and the clock input, configured to operate selectably at least in a normal operating mode or a calibration mode, and configured, when in the normal operating mode, to feed an oscillator signal of the oscillator circuit ( 10 ) to the delay circuit input and a reference signal to the clock input of the sampling register ( 24 ), and, when in the calibration mode, to supply signals with transitions having timing controlled by the oscillator signal to both the delay circuit input and the clock input, the feed circuit ( 20 ) being configured to provide for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input; and a control circuit ( 28 ) configured to switch the feed circuit between the normal operating mode and the calibration mode, to control the feed circuit ( 20 ) successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode, to read out resulting data from the sampling register ( 24 ) for each selection and to determine calibration data for the oscillator signal from said data.