Patent ID: 8399911

Claim:
An enhancement mode semiconductor device comprising: a first active layer on a substrate; a second active layer on the first active layer, the second active layer having a higher band-gap than the first active layer, and the second layer having a thickness of between 3 and 8 nm; a passivation layer on the second active layer; a source contact and a drain contact formed directly on and over the passivation layer; at least one hole in the passivation layer, the at least one hole being located between the source and drain contact and not protruding into the layers underlying the passivation layer; a gate contact in the hole, the gate contact having a width corresponding to the width of the at least one hole; and a two-dimensional electron gas layer present between the active layers, the electron gas layer being present outside of the location of the gate contact but not present directly underneath the gate contact when the gate and source contact are at the same voltage and the two-dimensional gas layer being present underneath the gate contact when the drain contact is at a higher potential compared to the source contact and a positive voltage is applied to the gate contact.