Patent ID: 8065506

Claim:
An application specific instruction processor comprising: a fetch unit for fetching instructions from a memory; an instruction decoder connected to said fetch unit for decoding instructions fetched by said fetch unit; a data register file including a plurality of data registers; a load/store unit connected to said instruction decoder, said data register file and an external memory, said load/store unit operable in response to a decoded load instruction to transfer data from an instruction specified address in external memory to an instruction specified one of said plurality of data registers, and in response to a decoded store instruction to transfer data from an instruction specified one of said data register to an instruction specified address in external memory; at least one general purpose functional unit connected to said instruction decoder and said data register file, said at least one general purpose functional unit operable in response to at least one instruction to recall data from at least one instruction specified data register, perform an instruction specified data processing operation and store results in an instruction specified one of said data registers; at least one special purpose functional unit connected to said instruction decoder and said data register file, said at least one special purpose functional unit operable in response to at least one instruction to recall data from at least one instruction specified data register, perform an instruction specified special purpose data processing and store results in an instruction specified one of said data registers; said fetch unit, said instruction decoder, said data register file, said load/store unit and said at least one general purpose functional unit operate in synchronism with a processor clock signal; and said at least one special purpose functional unit includes a sample unit receiving data in synchronism with a external clock signal and said external clock signal, said sample unit including a write pointer receiving external clock signal and storing a write location, said write pointer incrementing in synchronism with said external clock signal, a read pointer receiving said processor clock signal and storing a read location, said read pointer incrementing in synchronism with said processor clock signal upon a processor read request, a FIFO data register file having a plurality of data registers operating in synchronism with said processor clock signal, receiving data input in synchronism with said external clock signal, said write pointer and said read pointer, said input data register storing received data in a data register corresponding to said write pointer and outputting data from a data register corresponding to said read pointer upon a processor read request.