Patent ID: 8093107

Claim:
A method of semiconductor fabrication, comprising: forming a first well, a second well and a third well in a thyristor region within a semiconductor substrate; wherein the first well is formed above the second well; wherein the second well is formed above the third well; wherein the second well is a completely buried well; wherein the third well is located below the second well; wherein the first well and the third well have a first-type conductivity; wherein the second well has a second-type conductivity different from the first-type conductivity; forming a control gate for a thyristor over the semiconductor substrate of the thyristor region; forming gates for MOSFETs over a MOSFET region of the semiconductor substrate; forming a first dielectric layer conformally over the control gate of the thyristor in the thyristor region and the gates of the MOSFETs in the MOSFET region; forming a second dielectric layer conformally on the first dielectric layer over the control gate of the thyristor in the thyristor region and the gates of the MOSFETs in the MOSFET region; forming a third dielectric layer conformally on the second dielectric layer over the control gate of the thyristor in the thyristor region and the gates of the MOSFETs in the MOSFET region; depositing and patterning first photoresist to provide a first mask with a first window to etch exposed portions of the first dielectric layer in the MOSFET region; anisotropically etching portions of the first dielectric layer, the second dielectric layer, and the third dielectric layer in the MOSFET region through the first window of the first mask to form extension spacers against sidewalls of the gates of the MOSFETs; implanting first dopants for extension regions of the MOSFETs, the implanting to form the extension regions self-aligned with respect to the gates via the extension spacers; depositing and patterning second photoresist to provide a second mask over the thyristor region and the MOSFET region, the second mask having a second window over at least portions of the thyristor region; exposing the third dielectric layer through the second window of the second mask in the thyristor region while the second mask is not removed over the MOSFET region; anisotropically etching portions of the third dielectric layer in the thyristor region through the second window of the second mask so as to expose the second dielectric layer for implantation; implanting second dopants through the second window of the second mask for either an anode region or a cathode region for the thyristor, the implanting of the second dopants being in self-aligned relationship via the second mask; and implanting third dopants through the second window of the second mask for a first base region for the thyristor, the implanting of the third dopants being in self-aligned relationship via the second mask.