Patent ID: 7865700

Claim:
A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having four or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising: receiving an issue group of instructions; determining if at least one store instruction is in the issue group, and if so, scheduling the at least one store instruction in one of the four or more execution pipelines based upon a first prioritization scheme; determining if there is an issue conflict for one of the four or more execution pipelines; resolving the issue conflict by scheduling all but one of the at least one store instruction causing the issue conflict in a different execution pipeline; and scheduling execution of the issue group of instructions in the cascaded delayed execution pipeline unit; wherein the first prioritization scheme prioritizes the store instruction dealing with a semaphore as having a highest priority, the store instruction dealing with an update to a stack as having a second highest priority, the store instruction dealing with a dependent use of an address as having a third highest priority, the store instruction dealing with an address dependence as having a fourth highest priority, the store instruction dealing with an address conflict as having a fifth highest priority, the store instruction dealing with an update that is not to a stack as having a sixth highest priority, the store instruction dealing with a fixed, floating-point, and floating graphic instruction as having a seventh highest priority, the store instruction dealing with being an end of chain store instruction as having a eighth highest priority, and the store instruction being an independent instruction with no dependency as having a lowest priority.