Patent ID: 8681533

Claim:
A memory circuit comprising: a first circuit comprising at least two input terminals and at least one output terminal; a second circuit comprising at least two input terminals and at least one output terminal; a third circuit comprising at least two input terminals and at least one output terminal; a first switch; a first transistor comprising an oxide semiconductor; a first capacitor; a first inverter; and a second inverter, wherein one of the input terminals of the first circuit is configured to be supplied with a reading signal, the other of the input terminals of the first circuit is electrically connected to one of a source electrode and a drain electrode of the first transistor, and the output terminal of the first circuit is electrically connected to an input terminal of the first switch, wherein one of the input terminals of the second circuit is configured to be supplied with the reading signal, the other of the input terminals of the second circuit is electrically connected to an output terminal of the first switch, and the output terminal of the second circuit is electrically connected to the other of the source electrode and the drain electrode of the first transistor, wherein one of the input terminals of the third circuit is electrically connected to an output terminal of the first inverter, the other of the input terminals of the third circuit is configured to be supplied with the reading signal, the output terminal of the third circuit is electrically connected to an input terminal of the second inverter and a first control terminal of the first switch, and an output terminal of the second inverter is electrically connected to a second control terminal of the first switch, wherein a gate electrode of the first transistor is configured to be supplied with a control signal, wherein an input terminal of the first inverter is configured to be supplied with the control signal, wherein one of electrodes of the first capacitor is electrically connected to the one of the source electrode and the drain electrode of the first transistor, and the other of the electrodes of the first capacitor is grounded, wherein a low-level potential is supplied to either of the input terminals of the second circuit before supply of a power supply voltage is stopped, and wherein a high-level potential is supplied between the other of the source electrode and the drain electrode of the first transistor and the first capacitor.