Patent ID: 8901644

Claim:
A method of fabricating a field effect transistor with a vertical channel comprising: performing an isolation process on a Si substrate to define an active region; performing an implantation process to the active region to adjust a threshold; depositing a source polysilicon layer, which is to be formed as a source, on a surface of the Si substrate in the active region, and depositing a masking layer on the source polysilicon layer; performing an etching process so that a stack of the masking layer, the source polysilicon layer and the Si substrate are sequentially etched and then removing the masking layer to form a circular ring-shaped Si platform with the source polysilicon layer on top, and subsequently filling a dielectric material inside the circular ring-shaped Si platform; forming an LDD region for a drain on the surface of the Si substrate outside the circular ring-shaped Si platform; growing a gate oxide layer on surfaces of the source polysilicon layer, the Si platform and the Si substrate; depositing a gate polysilicon layer on the gate oxide layer to form a gate, and performing a heavily doping process to the gate polysilicon layer; performing an annealing process to active impurities; and then etching the gate polysilicon layer to form a polysilicon sidewall on an outer side surface of the circular ring-shaped Si platform; performing an ion implantation to the source and the drain; depositing a low-oxygen layer and performing an annealing process densification; performing an etching process for forming lead-out holes, sputtering metals, and alloying to form lead-outs of the source, the drain and the gate.