Patent ID: 7340024

Claim:
A circuit for re-sampling N data inputs comprising: a timing error detector sub-circuit having a first input coupled to a symbol rate clock and a second input coupled to a strobe; an oscillator having an input coupled to an output of the timing error-detector sub-circuit and N timing signal outputs for outputting N timing signals in parallel and a second output for outputting the strobe; and at least one fractional interpolator having parallel inputs coupled to N data inputs in parallel and to the N timing signals in parallel, for outputting N data outputs in parallel, wherein N is an integer greater than one, wherein the error detector sub-circuit operates to synchronize the strobe to a positive edge of the input that is coupled to the symbol rate clock and comprises: a first state machine for generating and outputting a pulse based on the symbol rate clock; a second and a third state machine in electrical parallel with one another, each having an input coupled to the strobe and to an output of the first state machine; and wherein the oscillator input is coupled to an output of at least one of the second or third state machines.