Patent ID: 8423703

Claim:
A memory card system, comprising: a host for issuing a read command; and a memory card including: a memory unit having a first read clock generator for generating a first read clock signal; a card controller for controlling the memory unit and having a second read clock generator for generating a second read clock signal, wherein the memory unit transfers read data for said read command and said first read clock signal generated within the memory unit to the card controller; and wherein the card controller transfers said read data from the memory unit to the host along with said second read clock signal; and a card I/O circuit for output-latching said read data to the host in synchronism with said second read clock signal, wherein the card controller upon receiving the read command controls the second read clock generator to generate the second read clock signal; and wherein the second read clock signal is transferred to the host substantially only during a read operation when read data is being transferred to the host; and wherein a time duration for sending the second read clock signal is determined from a size of the read data.