Patent ID: 7191355

Claim:
A method for maintaining clock synchronization in a network receiver having a jitter buffer and a frequency matching mechanism, said frequency matching mechanism having a primary clock recovery mechanism, a current frequency setting, a long-term frequency setting, a normal state, and an abnormal state, the method comprising the steps of: (a) setting said frequency matching mechanism to the normal state; (b) setting said current frequency setting to the frequency of said primary clock recovery mechanism; (c) checking if said frequency matching mechanism is in the normal state and (d) in the case that said frequency matching mechanism is in the normal state then setting said current frequency setting to the frequency of said primary clock recovery mechanism and (e) testing said jitter buffer so as to assess whether it is at a vulnerable state of fill and, (f) in the case that said jitter buffer is at a vulnerable state of fill then setting said current frequency setting to the sum of said long-term frequency setting and a frequency adjustment, setting said frequency matching mechanism to the abnormal state, and returning to step (c); (g) in the case that said jitter buffer is not at a vulnerable state of fill then returning to step (c); and (g) in the case that said frequency matching mechanism is not in the normal state then testing if it is true that said jitter buffer is at a vulnerable state of fill; and, (h) in the case that said jitter buffer is at a vulnerable state of fill then returning to step (c); and (i) in the case that said jitter buffer is not at a vulnerable state of fill then setting the frequency matching mechanism to normal state and returning to step (c).