Patent ID: 8165847

Claim:
A system for checking data transferred within a data processing system, said system comprising: a main processor; a processor memory coupled to said main processor; a flexible support processor coupled to said main processor via a data bus; a transfer description mailbox (TDM) associated with said flexible support processor and which stores a plurality of entries, including a status field and a device under test address field, identifying a memory location in said processor memory; a flexible support processor memory coupled to said flexible support processor, wherein said first memory embodies computer program code, said computer program code comprising instructions executable by said flexible support processor and configured for: generating a plurality of random data utilizing said flexible support processor; storing a first and second copy of said plurality of random data in a first and a second memory location of said flexible support processor memory; wherein said first memory location is a random block within said flexible support processor memory and said second memory location is a transfer block within said flexible support processor memory; configuring, via said main processor, said memory location in said processor memory for said flexible support processor to store a third copy of said plurality of random data, writing said third copy of said plurality of random data in said processor memory; said flexible support processor retrieving said third copy from said processor memory; in response to said flexible support processor retrieving said third copy from said processor memory, writing said third copy in said second memory location in said flexible support processor memory; comparing said first copy with said third copy in said second memory location in said flexible support processor memory to detect a presence of one or more inconsistencies between said first copy and said third copy in said second memory location in said flexible support processor memory; and in response to said flexible support processor detecting an inconsistency between said first copy with said third copy in said second memory location in said flexible support processor memory, writing results of said compare in a status location within said TDM associated with said flexible support processor; wherein said flexible support processor with associated TDM and flexible support processor memory provides a controller functionality of a peripheral component interconnect (PCI) direct memory access (DMA) master, which concurrently functions as both a system controller and an input/output (I/O) exerciser, wherein said I/O exerciser functions independently from a system under test (SUT) and does not require utilization of a card specifically designed to execute said I/O exerciser.