Patent ID: 7834400

Claim:
A semiconductor structure for protecting an internal integrated circuit, comprising: a substrate; a plurality of first doping regions, formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within a P-well, the second doping regions being isolated from the first doping regions; a N+ section, formed in the substrate and enclosing the N-well and the P-well, wherein the first and second doping regions located within the N+ section are isolated from the substrate by the N+ section; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; a first ground and a second ground, respectively disposed to positions corresponding to outside and inside of the N+ section, the first ground electrically connected to the internal integrated circuit and the second ground electrically connected to at least one of the second doping regions, wherein the first ground is isolated from the second ground.