Patent ID: 7758763

Claim:
A substrate processing method to remove a resist layer overlying a dielectric feature while controlling an edge facet height of the feature, the method performed in a substrate processing chamber comprising an antenna and first and second process electrodes, the method comprising: (a) placing a substrate having a resist layer overlying a dielectric feature into the chamber; (b) removing the resist layer while controlling an edge facet height of the underlying dielectric feature by: (i) introducing a process gas comprising CO 2 into the chamber; (ii) energizing the process gas by: (1) applying a source voltage to the antenna; and (2) applying to the first and second process electrodes in the chamber, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz, the ratio of the power level of the first bias voltage to the second bias voltage being at least about 1:9 and less than about 11:1, to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature; and (c) exhausting the process gas from the chamber.