Patent ID: 8557653

Claim:
A method of manufacturing a junction-field-effect-transistor (JFET) device, the method comprising the steps of: providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between the second well region and the third well region over the fourth well region; and forming a patterned conductive layer including a pair of drain terminals on the pair of first doped regions, a pair of gate terminals on the pair of second doped regions, and a source terminal on the third doped region.