Patent ID: 7386083

Claim:
A phase comparator comprising: a flip-flop circuit supplied with an input data signal and an input clock signal, said flip-flop circuit comparing said input clock signal with a leading edge and a trailing edge of said input data signal to produce a leading phase comparison result signal indicative of a leading phase comparison result related to said leading edge of said input data signal and a trailing phase comparison result signal indicative of a trailing phase comparison result related to said trailing edge of said input data signal; and a logic circuit connected to said flip-flop circuit, said logic circuit producing an output up signal when both of said leading and said trailing phase comparison result signals indicate a lag phase of the input clock signal, said logic circuit producing an output down signal when both of said leading and said trailing phase comparison result signals indicate a lead phase of said input clock signal, wherein the logic circuit produces the output up signal based on both of said leading and said trailing phase comparison result signals, and wherein the logic circuit produces the output down signal based on both of said leading and said trailing phase comparison result signals.