Patent ID: 8273658

Claim:
A method for producing an integrated circuit arrangement comprising: producing a first conductive structure; depositing at least one first dielectric layer after the production of the first conductive structure; depositing at least one hard mask layer after the deposition of the first dielectric layer; depositing at least one further dielectric layer after the deposition of the hard mask layer; patterning the further dielectric layer and of the hard mask layer by means of a photolithographic method in a first etching process with the production of a cutout in the further dielectric layer; patterning the first dielectric layer with the aid of the patterned hard mask layer in a second etching process, which differs from the first etching process, with the production of a cutout in the first dielectric layer; depositing a first metal layer at a first deposition temperature with the filling of the cutout in the first dielectric layer; after the deposition of the first metal layer, depositing a second metal layer at a second deposition temperature, which is lower than the first deposition temperature; and actively precooling the integrated circuit arrangement to the second deposition temperature prior to depositing the second metal layer.