Patent ID: 8790971

Claim:
A method of fabrication of a super junction transistor, comprising: providing a drain substrate having a first conductivity type; forming an epitaxial layer on the drain substrate, wherein the epitaxial layer has a second conductivity type; forming a plurality of trenches in the epitaxial layer; forming a buffer layer in direct contact with inner surface of the trenches; filling a dopant source layer into the trenches, wherein the dopant source layer at least has dopants with the first conductivity type; performing an etching process to form a plurality of recessed structures above the respective trenches; forming a gate oxide layer on the surface of the recessed trenches and concurrently diffusing the dopants inside the dopant source layer into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer with the first conductivity type; filling a gate conductor into the recessed structures to form a plurality of gate structure units; and forming a doped source region having the first conductivity type, wherein the doped source region is disposed in the epitaxial layer and is adjacent to each of the gate structure units.