Patent ID: 7395471

Claim:
A TAP domain comprising: A. a test data input; B. a test data output; C. a test clock input; D. a test mode select input; E. a serial instruction register having a serial data input connected to the test data input, a serial data output, an instruction register control bus output, and a control bus input; F. a serial data register having a serial data input connected to the test data input, a serial data output, and a control input connected to the instruction register control bus output; G. multiplexer circuitry coupling the serial data output of the instruction register and the serial data output of the data register to the test data output, and having a control input; H. TAP control circuitry having a clock input connected to the test clock input, a mode select input connected to the test mode select input, and a TAP control bus output connected to the control bus input of the instruction register and the control input of the multiplexer circuitry; I. at least one auxiliary interface terminal separate from the test data input, the test data output, the test clock input, and the test mode select input; and J. auxiliary circuitry having a data input coupled to the test data input, a data output coupled to the test data output, an auxiliary lead coupled to the at least one auxiliary interface terminal, instruction register control terminals connected to the instruction register control bus output, and TAP control bus terminals connected to the TAP control bus output.