Patent ID: 8462571

Claim:
A dynamic random-access memory (DRAM), comprising: a memory cell for storing a data bit; a first bit line associated with the memory cell; a local buffer coupled to the first bit line, receiving a first power voltage as power supply, providing a ground voltage to the first bit line when a first data signal is de-asserted and providing the first power voltage to the first bit line when the first data signal is asserted; a bit line sense amplifier (BLSA) coupled to the first bit line, receiving a second power voltage as power supply, providing the second power voltage to the first bit line when the first data signal and a wafer level bum-in test signal are both asserted, wherein the second power voltage is higher than the first power voltage, the wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode; a first switch, coupled between the second power voltage and the BLSA; a second switch, coupled between the BLSA and the ground voltage; and a controller, turning on or turning off the first switch and the second switch according to the wafer level burn-in test signal.