Patent ID: 7852254

Claim:
A 1-bit cell circuit used in a pipelined analog to digital converter, having a sampling phase including a first half period and a second half period and a charge transfer phase in a cycle, the 1-bit cell circuit comprising: a differential amplifier, having a positive input end, a negative input end, a positive output end and a negative output end, for outputting a residue output signal; a first capacitor, having a first plate and a second plate, and a second capacitor, having a third plate and a fourth plate, wherein said first plate is connected to a positive input signal, said third plate is connected to a negative input signal, and said second plate and said fourth plate are both connected to an input common mode reference ground during said sampling phase, and said first plate is connected to said third plate, said second plate is connected to said negative input end of said differential amplifier, and said fourth plate is connected to said positive input end of said differential amplifier during said charge transfer phase; and a third capacitor, having a fifth plate and a sixth plate, and a fourth capacitor, having a seventh plate and an eighth plate, wherein said fifth plate and said seventh plate are connected to an output common mode reference ground, and said sixth plate and said eighth plate are both connected to said input common mode reference ground during said first half period of said sampling phase; said fifth plate is connected to a first reference contact, said seventh plate is connected to a second reference contact, and said sixth plate and said eighth plate are both connected to said input common mode reference ground during said second half period of said sampling phase; and said fifth plate is connected to said positive output end of said differential amplifier, said sixth plate is connected to said negative input end of said differential amplifier, said seventh plate is connected to said negative output end of said differential amplifier and said eighth plate is connected to said positive input end of said differential amplifier during said charge transfer phase; wherein voltages of said first reference contact and said second reference contact are determined according to an input voltage and a reference voltage, and said input voltage is a voltage difference between said positive input signal and said negative input signal.