Patent ID: 8779844

Claim:
A semiconductor integrated circuit comprising: a transfer transistor including a first gate electrode; a first conductor including a first partial conductor, the first partial conductor being disposed above the first gate electrode; a second conductor including a second partial conductor, the second partial conductor being disposed above the first gate electrode, the second conductor being electrically connected to one end of the transfer transistor; and a third conductor including a third partial conductor disposed above the first gate electrode, the third partial conductor being disposed between the first partial conductor and the second partial conductor when seen from a direction in which the semiconductor integrated circuit is laminated; a first capacitor whose one end is connected to the first gate electrode and whose other end receives a clock signal, wherein a boosting circuit includes the transfer transistor; the semiconductor integrated circuit further comprising: a fourth conductor connecting the one end of the first capacitor and the first gate electrode; and a fifth conductor electrically connected to the third conductor; wherein the fifth conductor is arranged in the same layer as the fourth conductor and extends in parallel to the fourth conductor.