Patent ID: 8253182

Claim:
A non-volatile semiconductor memory device, comprising: a semiconductor substrate including a substrate surface; a first interlayer insulating film formed on the substrate surface of the semiconductor substrate; a second interlayer insulating film formed on the first interlayer insulating film; a bit line formed on the second interlayer insulating film, the bit line extending to a first direction; a first plug formed in the first interlayer insulating film, the first plug including: a lower portion having a silicon material, the lower portion having a first bottom surface contacting to the semiconductor substrate, and an upper portion located on the lower portion and having a metallic material, the upper portion having a first upper surface exposed from the first interlayer insulating film, the first upper surface having a first width along the first direction and a second width along a second direction perpendicular to the first direction; a second plug formed in the second interlayer insulating film, including a second upper surface contacting to the bit line and a second bottom surface contacting to the first upper surface of the first plug, the second bottom surface having a send third width along the first direction and a forth width along the second direction, the second plug extending in a direction parallel to the first direction as a long-side direction; and a plurality of gate electrodes of memory cell transistors formed above the substrate surface of the semiconductor substrate, each of the gate electrodes including a third upper surface; wherein the third width is larger than the first width, the fourth width is smaller than the second width, and a height of an interface between the first and second interlayer insulating films is higher than a height of the third upper surface of the gate electrodes of the memory cell transistor relative to the substrate surface of the semiconductor substrate.