Patent ID: 7586141

Claim:
A semiconductor device comprising: a semiconductor substrate having a memory formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in said memory formation region; a second impurity region formed in an upper surface of said semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of said first impurity region and having a conductivity type different from that of said first impurity region; a fourth impurity region formed in an upper surface of said second impurity region and having a conductivity type different from that of said second impurity region; a first silicide film formed in an upper surface of said third impurity region; a capacitor formed above said first silicide film and electrically connected to said first silicide film, and said capacitor having an electrode containing a refractory metal; a second silicide film formed in an upper surface of said fourth impurity region and having a larger thickness than said first silicide film; first and second gate structures formed on the upper surface of said semiconductor substrate in said memory formation region and spaced apart at a first distance from each other, and third and fourth gate structures formed on the uppers surface of said semiconductor substrate in said logic formation region and spaced apart at a second distance from each other; and wherein said first and second silicide films are provided between said first and second gate structures and between said third and fourth gate structures, respectively, and a first gate aspect ratio defined by the first distance and a height of said first and second gate structures is larger than a second gate aspect ratio defined by the second distance and a height of said third and fourth gate structures, wherein said first gate aspect ratio is larger than 0.8.