Patent ID: 7610537

Claim:
A computer implemented method for testing a first set of communication bus interfaces and a first set of processor cores in a multiprocessor, the computer implemented method comprising: initiating testing on the first set of processor cores on the multiprocessor in which the first set of communication bus interfaces is enabled to allow test results from the first set of processor cores to be communicated to a processor bus, and a second set of communication bus interfaces associated with a second set of processor cores not being tested are disabled such that the second set of processor cores can receive an input data from the processor bus but cannot send an output to the processor bus, wherein enabling the first set of communication bus interfaces and disabling the second set of communication bus interfaces are in accordance with a set of isolation test sequences; identifying a set of functional processor cores in the set of processor cores based upon the test results; and initiating a logic built-in self-test to test a communication bus interface in the first set of communication bus interfaces associated with a given functional processor core in the set of functional processor cores, wherein the communication bus interface in the first set of communication bus interfaces is enabled and wherein the logic built-in self-test determines if the communication bus interface in the set of communication bus interfaces associated with the given functional processor core in the set of functional processor cores is functional.