Patent ID: 8127188

Claim:
A semiconductor integrated circuit, comprising: a combinational logic circuit; a scan chain circuit comprising a plurality of flip-flops that are serially connected, and configured to temporarily store data that is inputted to and outputted from the combinational logic circuit during ordinary operation, and to cause the plurality of flip-flops to function as shift registers to execute a scan shift that serially transfers test pattern data for a scan test during execution of the scan test; and a clock gating circuit configured to control output of a pulse of a clock signal supplied to the scan chain circuit in accordance with a clock gating signal, whereas the clock gating signal being disabled based on a scan enable signal authorizing the scan shift, the clock gating circuit including a first clock gating circuit configured to disable the clock gating signal during the scan shift based on the scan enable signal and also to invert the clock signal to output an inverted gated-clock signal and a second clock gating circuit configured to disable the clock gating signal during the scan shift based on the scan enable signal and output a gated-clock signal without inverting, wherein the scan chain circuit is configured to operate such that part of the serially connected flip-flops execute the scan shift in accordance with the gated-clock signal and other part of the serially connected flip-flops execute the scan shift in accordance with the inverted gated-clock signal.