Patent ID: 7612620

Claim:
A method of conditioning clock signals, the method comprising: generating a plurality of pairs of complementary clock signals, each clock signal having a phase and a duty cycle; generating first and second voltages having respective magnitudes corresponding to the duty cycles of first and second clock signals in one of the pairs of complementary clock signals; comparing the magnitude of the first voltage to the magnitude of the second voltage; if the magnitude of the first voltage is greater than the magnitude of the second voltage, decreasing the duty cycle of the first clock signal and increasing the duty cycle of the second clock signal until the magnitude of the first voltage is no longer greater than the magnitude of the second voltage; and if the magnitude of the second voltage is greater than the magnitude of the first voltage, increasing the duty cycle of the first clock signal and decreasing the duty cycle of the second clock signal until the magnitude of the second voltage is no longer greater than the magnitude of the first voltage.