Patent ID: 7541840

Claim:
A buffer circuit, comprising: at least first and second circuit blocks; the first circuit block including, a first power supply pad; a first high potential power supply line connected to the first power supply pad; a second high potential power supply line a first input/output pad; a first pull up circuit and a first pull down circuit configured to selectively pull up and pull down, respectively, a voltage of the first input/output pad, and the first pull up and pull down circuits each being connected to the first and second high potential power supply lines, respectively; and the second circuit block including, a second power supply pad connected to the second high potential power supply line; a third high potential power supply line connected to the second power supply pad; a fourth high potential power supply line; a second input/output pad; a second pull up circuit and a second pull down circuit configured to selectively pull up and pull down, respectively, a voltage of the second input/output pad, and the second pull up and pull down circuits each being connected to the third and fourth high potential power supply lines, respectively; wherein the fourth high potential power supply line is connected to the first high potential power supply line.