Patent ID: 8627007

Claim:
A method comprising: receiving, at a controller of a data read/write system, first data to write to an address of a single port memory; receiving, at the controller, a request to read second data from the single port memory; determining, by the controller, a quantity of entries stored in a cache memory that is separate from the single port memory, each of the quantity of entries including a dirty bit field, the dirty bit field indicating whether data stored in a data field of an entry, of the quantity of entries, has been written back from the cache memory to the single port memory; transmitting, by the controller and when a determined quantity of entries including a dirty bit field indicating that the data stored in the data field has not been written back from the cache memory to the single port memory is greater than a threshold, a blocking notification, the blocking notification indicating that write requests will be blocked until the determined quantity is less than the threshold; writing, by the controller and when the determined quantity is greater than the threshold, an entry, of the quantity of entries, to the single port memory based on a first priority, the dirty bit field of the entry indicating that the data stored in the data field of the entry has not been written back from the cache memory to the single port memory; changing, by the controller and based on writing the entry, a value associated with the dirty bit field of the entry; storing, by the controller and when the determined quantity is less than the threshold, the first data in the cache memory based on a second priority, the second priority being less than the first priority; retrieving the second data from either the cache memory or the single port memory during a first system clock cycle; and copying the first data from the cache memory and storing the first data at the address in the single port memory during a second system clock cycle that is different than the first system clock cycle.