Patent ID: 8131944

Claim:
An apparatus comprising: a plurality of virtual channels each including: an input multiplexer to receive cache coherency messages, the cache coherency messages each having a criticality indicator associated therewith; a plurality of queues coupled to the input multiplexer to store the cache coherency messages, wherein each of the queues is associated with at least one of the criticality indicators; and an output multiplexer coupled to the plurality of queues to select an output of one of the queues based at least in part on the corresponding criticality indicator; a switch coupled to the plurality of virtual channels to output the cache coherency messages to an interconnect fabric; and a criticality logic to map a cache coherency message to a criticality indicator based on a type of the cache coherency message and to append the criticality indicator to a header of each packet of the cache coherency message, wherein the criticality logic is associated with a table to map each of a set of cache coherency messages to a criticality indicator, and to perform the mapping without a software hint from a user.