Patent ID: 8017516

Claim:
A method for forming a semiconductor in a dual damascene structure comprising: receiving a patterned semiconductor substrate, having a first conductive interconnect material filling a plurality of features in the pattern, the first conductive interconnect material having an non-planar overburden portion; planarizing the non-planar overburden portion without imparting mechanical force or imparting shearing stress to the plurality of features including: forming an additional layer on top of the non-planar overburden portion, the additional layer having a 1:1 etch selectivity with the non-planar overburden portion, wherein the additional layer is formed through a chemical conversion of a top-most portion of the overburden portion; and etching the additional layer and the overburden layer to soften a profile of the overburden portion and reduce the non-planarity of the overburden portion, wherein the etching is a chemical non-contact etch; forming a subsequent dielectric layer on the planarized overburden portion; planarizing the subsequent dielectric layer including: identifying a non-planarity in the subsequent dielectric layer; forming one or more additional dielectric layers over the subsequent dielectric layer; and planarizing at least one of the additional dielectric layers; forming a mask on the planar subsequent dielectric layer; forming one or more features in the planar subsequent dielectric layer; and filling the one or more features with a second conductive interconnect material.