Patent ID: 7670912

Claim:
A method of forming a unit cell of a metal oxide semiconductor (MOS) transistor, comprising: forming a MOS transistor on an integrated circuit substrate including an isolation layer and an active region higher than the isolation layer, the MOS transistor having a pair of junctions consisting of a vertical source region and a vertical drain region on the isolation layer, and a plurality of gates on the active region, the plurality of gates being formed simultaneously to be stacked between the vertical source region and the vertical drain region; forming a horizontal channel between the vertical source region and the vertical drain region by growing single crystalline layers vertically spaced apart from each other on the active region, the horizontal channel including at least two horizontal channel regions formed in spaced apart patterns, wherein widths of the plurality of gates that contact the at least two horizontal channel regions are substantially identical, and wherein the pair of junctions are vertically formed to cover the sides of the active region in other patterns adjacent to sides of the spaced apart patterns so that the pair of vertical junctions contact the sides of the at least two spaced apart horizontal channel regions; and forming a vertical source electrode electrically connected to the vertical source region and a vertical drain electrode electrically connected to the vertical drain region, wherein the vertical source and drain electrodes are formed on the isolation layer so that the vertical source and drain electrodes contact sides of the vertical source and drain regions, respectively.