Patent ID: 8074054

Claim:
A processing system, comprising: a plurality of digital processing units connected in a sequence having a first digital processing unit located at beginning of the sequence and a last digital processing unit located at end of the sequence, wherein each one of the plurality of digital processing units is configured to allow a packet stream to pass through and capable of reading an input data packet from the packet stream during a designated time frame; a first distribution device coupled to the plurality of digital processing units and operable to forward the packet stream to the first digital processing unit; a second distribution device coupled to the plurality of digital processing units and operable to receive the packet steam from the last digital processing unit; and a global clock tree coupled to the plurality of digital processing units and configured to distribute clock signals to the plurality of digital processing units, wherein the plurality of digital processing units is a plurality of packet-processing-engines, the first distribution device is a demultiplexer, and the second distribution device is a multiplexer.