Patent ID: 8819485

Claim:
A system for avoiding error propagation in a multi-central processing unit (CPU) system comprising: a first CPU and at least one second CPU, the at least one second CPU adapted to operate in delayed lockstep configuration with the first CPU, wherein the first CPU and the at least one second CPU operate with a comparator to detect an error by comparing an output signal delayed by a delay unit from the first CPU with an output signal from the at least one second CPU not delayed by a delay unit; and an error blocking unit coupled to the comparator and the delay unit, wherein the output signal delayed by the delay unit from the first CPU is fed to the comparator and to the error blocking unit, and wherein the error blocking unit is configured to modify the output signal delayed by the delay unit from the first CPU when the comparator detects the error, such that the detected error is kept from propagating through the system.