Patent ID: 7719873

Claim:
A memory device comprising: a plurality of memory cells, each memory cell including a memory element and a transistor connected in series with the memory element, the memory cells arranged in a matrix having rows and columns, each memory cell corresponding to one bit of information and having such characteristics that (a) when an electric signal at a voltage level equal to or higher than that of a first threshold signal is applied to the memory element of the memory cell, the resistance thereof is changed from a high value to a low value, and (b) when an electric signal at a voltage level equal to or higher than that of a second threshold signal is applied thereto, the resistance is changed from the low value to the high value, the polarities of the first and second threshold signals being different from each other; electric circuits operative for applying said electric signals to each of the memory cells and configured to perform a write operation; and respective detection units associated with each column of said matrix and operative to measure (a) a current flowing through at least one memory element or (b) a voltage applied to at least one memory element from the start of applying electric signals from an electric circuit to the memory element by comparing the current or the voltage, respectively, with a reference signal to detect whether the resistance of the memory element is high or low, wherein, each of the detection units accepts a write signal of a first level or a second level, applies a signal to a selected memory element, and detects a state of the selected memory element by comparing a voltage or current of a steady state signal returned from the selected memory element with the reference signal during the write operation, the write signal returns to a level preceding the write signal to terminate a write operation in response to a determination the steady state signal corresponds to a bit being written to the selected memory element, and one of said electric signals is applied to one of said plurality of memory cells to switch the corresponding transistor from an off-state to an on-state.