Patent ID: 7767567

Claim:
A method of forming a semiconductor memory device, the method comprising: forming gate stacks of an array of memory cells and a plurality of select transistors above a carrier; forming spacers between the gate stacks; forming an opening between the spacers in an area that is provided for a source line; applying a sacrificial layer and filling the opening with the sacrificial layer; patterning the sacrificial layer to form a patterned sacrificial layer having interspaces, the patterned sacrificial layer having a first portion filling the opening, and a second portion substantially parallel to the carrier and disposed above a top surface of the array of memory cells; filling the interspaces with a planarizing layer of dielectric material; removing the patterned sacrificial layer; applying an electrically conductive material to form the source line and a shield; and A 1 applying tetraethylorthosilicate to form a further auxiliary layer after the patterning the sacrificial layer.