Patent ID: 7410859

Claim:
A method for fabricating a stressed MOS device comprising the steps of: providing a monocrystalline semiconductor substrate having a surface and a channel region abutting the surface, the monocrystalline semiconductor substrate characterized by a first lattice constant; forming a gate electrode overlying the monocrystalline semiconductor substrate, the gate electrode having a first edge and a second edge; anisotropically etching the monocrystalline semiconductor substrate to form a first recess aligned with the first edge and a second recess aligned with the second edge; isotropically etching the monocrystalline semiconductor substrate to form a third recess in the monocrystalline semiconductor substrate extending beneath the channel region; selectively growing a stress inducing monocrystalline semiconductor material filling the first recess, the second recess, and the third recess, the stress inducing monocrystalline semiconductor material characterized by a second lattice constant greater than the first lattice constant; and ion implanting conductivity determining ions into the stress inducing monocrystalline semiconductor material filling the first recess and the second recess to form a source region and a drain region aligned with the first edge and the second edge, respectively.