Patent ID: 8234606

Claim:
A non-transitory machine readable medium embodying a design structure for designing, manufacturing, or testing a design for an integrated circuit, said design structure configured to generate a representation of said integrated circuit in a format perceptible by humans when read by a machine, and to cause said representation to comprise: a first element representing a semiconductor substrate; a second element representing at least one through substrate via (TSV) which extends through said semiconductor substrate; a third element representing a metal-wire-level dielectric layer; a fourth element representing at least one line-level metal wiring structure, wherein said metal-wire-level dielectric layer and said at least one line-level metal wiring structure complementarily fills an entirety of a layer located above said at least one TSV; and a fifth element representing an array of cheesing holes included in said at least one line-level metal wiring structure, wherein no portion of topmost edges of sidewalls of said at least one TSV contacts any cheesing hole.