Patent ID: 8200726

Claim:
A method of improving at least one of speed and efficiency when executing a linear algebra subroutine on a computer having a memory hierarchical structure including at least one cache, said method comprising: determining, based on sizes, for a level 3 matrix multiplication processing in which are involved three matrices, which matrix of said three matrices will have data for a submatrix block residing in a lower level cache of said computer and which two matrices of said three matrices will have data for submatrix blocks residing in at least one higher level cache or a memory, said lower level cache being closer to a processor of said computer than said higher level cache in said memory hierarchical structure; and streaming data from said two matrices to have data residing in said at least one higher level cache or memory, for executing said level 3 matrix multiplication processing, so that said submatrix block residing in said lower level cache remains resident in said lower level cache.