Patent ID: 7972924

Claim:
A method for manufacturing a memory, comprising: providing a substrate with a first sacrificial layer and a second sacrificial layer formed thereon; selectively removing said substrate, said first sacrificial layer and said second sacrificial layer to form a first trench disposed in said substrate, said first sacrificial layer and said second sacrificial layer and exposing said substrate; filling said first trench with a first dielectric material to form a shallow trench isolation; conformally depositing a second dielectric material on said second sacrificial layer and said first dielectric material; selectively removing said second dielectric material, said second sacrificial layer, said first sacrificial layer and said shallow trench isolation to form a second trench disposed in said second dielectric material, in said second sacrificial layer, in said first sacrificial layer and in said shallow trench isolation to expose said substrate, wherein said first trench is normal to said second trench; forming a control gate region comprising a control gate dielectric layer, a control gate and a hard mask in said second trench; removing said second dielectric material and said second sacrificial layer to form a third trench exposing said first sacrificial layer; forming a dielectric sidewall adjacent to said control gate region in said third trench and selectively removing said first sacrificial layer to expose said substrate; forming a floating gate dielectric layer on said exposed substrate; and forming a floating gate layer on said floating gate dielectric layer so that said floating gate layer is adjacent to said dielectric sidewall.