Patent ID: 8717813

Claim:
A flash memory device comprising: a memory array including a plurality of blocks of memory cells wherein the memory array includes word lines and bit lines coupled to corresponding memory cells in the given block of memory cells; and a controller including logic to perform a leakage-suppression process in response to the command, the leakage-suppression process comprising: after determining that a given block of memory cells includes one or more over-erased memory cells, performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in the given block of memory cells, the determining step comprises applying bias voltages to the word lines sufficient to turn on the over-erased memory cells, and comparing current on the corresponding bit lines to a reference to identify bit lines that are coupled to over-erased memory cells; and performing the soft program operation comprises performing the soft program operation on memory cells that are coupled to the identified bit lines to increase the threshold voltage of the over-erased memory cells and establish the erased state.