Patent ID: 7667332

Claim:
A semiconductor device, comprising: an interconnect provided in an interconnect area on a surface of an insulating film; a plug connected to a bottom surface of the interconnect in a first area within the interconnect area; first dummy interconnects provided in the first area within the interconnect area, being arranged in a two-dimensional array with a first pitch, the first dummy interconnects having a first size and a first local pattern density, the first local pattern density being defined as a fractional area occupied by one of the first dummy interconnects within an area provided by the first pitch on a surface of the first area; and second dummy interconnects provided in a second area excluding the first area within the interconnect area, being arranged in a two-dimensional array with a second pitch, the second dummy interconnects having a second size and a second local pattern density, the second local pattern density being defined as a fractional area occupied by one of the second dummy interconnects within an area provided by the second pitch on a surface of the second area, at least one of the second pitch, the second size, and the second local pattern density being different from the first pitch, the first size, and the first local pattern density, wherein the first local pattern density is greater than the second local pattern density.