Patent ID: 7446422

Claim:
A wafer level chip scale package comprising: a semiconductor die including at least one bond pad and a passivation layer formed at an outer peripheral portion of the bond pad; a first insulative layer formed on the passivation layer and having a first opening corresponding to the bond pad and a second opening spaced from the bond pad by a distance; a re-distribution layer (RDL) formed on the passivation layer so as to connect the first opening to the second opening; an under bumped metal (UBM) formed on the RDL corresponding to the second opening of the first insulative layer; a second insulative layer formed on the first insulative layer, the RDL and the UBM and having a third opening, wherein a size of the third opening is less than a size of the UBM such that a portion of the UBM is covered by the second insulative layer; and a solder ball welded to the UBM.