Patent ID: 7429873

Claim:
A circuit of a digital integrated output driver with dynamically biased cascade transistors is comprising: a level-shifter having an input and an output, wherein said input is connected to an input of said output driver and said output is connected to a gate of a first transistor of a string of any number n cascaded PMOS transistors, wherein n is more than 2; said string of any number n cascoded PMOS transistors, wherein n is more than 2 and wherein a source of said first PMOS transistor is connected to VDD voltage, the drain of each transistor is connected to a source of a next transistor and the drain of the nth transistor is connected to an output of said output driver, and wherein all said transistors, except said first and a second transistor, are dynamically biased by said output voltage via a biasing means; said biasing means, wherein said biasing means is driven from an output voltage of said output driver and does not require any switching; an NMOS output transistor, wherein its drain is connected to said output of said output driver, its gate is connected to the input of the output driver, and its source is connected to ground voltage; a string of n resistive means, wherein a first terminal of a first resistive means is connected to VDD voltage and a second terminal of the nth resistive means is connected to ground, wherein a tap between said first resistive means and a second resistive means is connected to the gate of said second transistor of said string of n cascoded transistors, a tap between said second resistive means and a third resistive means is connected via a rectifying means to a gate of a third transistor of said string of n cascaded transistors and, if n is greater than three, each following tap between neighboring resistive means is connected via a rectifying means to a gate of a correspondent transistor of said string of n cascoded PMOS transistors; and said (n−2) rectifying means, wherein each of the rectifying means connects one of the last (n−2) taps between said n resistive means with a correspondent gate of the last (n−2) transistors of said string of n cascoded PMOS transistors.