Patent ID: 6999336

Claim:
A ferroelectric memory comprising: a first bit line pair, the first bit line pair comprising a first bit line and a second bit line having a voltage level opposite to a voltage level of the first bit line; a first sense amplifier coupled to the first bit line pair; a second bit line pair, the second bit line pair comprising a third bit line and a fourth bit line having a voltage level opposite to a voltage level of the third bit line; a second sense amplifier coupled to the second bit line pair: a first word line formed across the first and second bit line pairs; a second word line formed across the first and second bit line pairs, the second word line crossing the first word line between the first and second bit line pairs; a first plate line formed straight across the first and second bit line pairs; a second plate line formed straight across the first and second bit line pairs, the second plate line being arranged parallel to the first plate line; a first ferroelectric memory cell arranged between the first and second bit lines, the first ferroelectric memory cell being coupled to the first word line and the first plate line; a second ferroelectric memory cell arranged between the first and second bit lines, the second ferroelectric memory cell being coupled to the second word line and the second plate line; a third ferroelectric memory cell arranged between the third and fourth bit lines, the third ferroelectric memory cell being coupled to the second word line and the first plate line; and a fourth ferroelectric memory cell arranged between the third and fourth bit lines, the fourth ferroelectric memory cell being coupled to the first word line and the second plate line.