Patent ID: 8661228

Claim:
A method of data processing in a processor, said method comprising: in the processor, holding operands of a plurality of hardware threads of the processor in a shared first level register file having a lower access latency and holding operands of the plurality of hardware threads in a shared second level register file having a higher access latency; in a mapper of the processor, maintaining: a first data structure including a plurality of entries each assigning an identifier of a physical register in the first-level register file to a respective one of a plurality of instructions undergoing execution, wherein the first data structure is a shared data structure concurrently containing entries for instructions in multiple of the plurality of hardware threads; and a second data structure that records variable assignments between the plurality of architected logical registers and physical registers in the first level register file; at dispatch of an instruction specifying a source logical register among the plurality of architected logical registers, the mapper initiating a swap of a first operand that is associated with the source logical register and that is held in the second level register file with a second operand in the first level register file and updating the second data structure accordingly; and thereafter, in response to a signal from the mapper indicating the first operand is present in the first level register file, issuing the instruction for execution by the processor.