Patent ID: 7986542

Claim:
A semiconductor memory device, comprising: a first memory cell array including a plurality of first word lines; a second memory cell array including a plurality of second word lines; and a row decoder being arranged between said first memory cell array and said second memory cell array, said row decoder including a plurality of first word line drivers and a plurality of second word line drivers at both sides thereof, respectively; wherein said plurality of first word line drivers and said plurality of second word line drivers are disposed within an area corresponding to a pitch of one of said plurality of first word lines and said plurality of second word lines, such that there is no need to mount one of said first word line drivers and said second word line drivers to each of said first word lines and said second word lines placed on one side of the row decoder, a number of said first word line drivers is less than a number of said first word lines, and wherein a number of said second word line drivers is less than a number of said second word lines, and an upper wiring is configured to short circuit said first and second word lines.