Patent ID: 7948288

Claim:
A digital DLL circuit comprising: a phase determination section including: a delay generation unit including a plurality of series-coupled first fixed delay elements each having a delay time that are all similar, with the plurality of first fixed delay elements being divided into 2 n series-coupled blocks which generate a delay clock signal from a clock signal, and each of the blocks including at least a given quantity of the first fixed delay elements; a determination circuit which compares the clock signal and the delay clock signal and determines the quantity of the first fixed delay elements for delaying the delay clock signal by one cycle from the clock signal to generate a phase adjustment signal; and a stage quantity control unit which generates, based on the phase adjustment signal, a selection signal for selecting the quantity of the first fixed delay elements that delay the clock signal; and a phase adjustment section which generates an output signal by delaying an input signal by a certain phase amount, the phase adjustment section including: a plurality of series-coupled second fixed delay elements each having a delay time that are all similar; and a variable delay unit which generates a variable delay time allowing the delay time of the output signal to be adjusted in steps of ½ n the delay time of one of the second fixed delay elements, wherein the phase adjustment section determines the quantity of the second fixed delay elements for delaying the input signal and the variable delay time of the variable delay unit based on the selection signal.