Patent ID: 8258547

Claim:
A semiconductor device, comprising: a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively; at least six linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first direction, the at least six linear shapes spaced apart from each other in accordance with an integer multiple of a first pitch as measured in a second direction perpendicular to the first direction between lengthwise centerlines of the at least six linear shapes, and wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors include, (a) a first N-transistor and a second N-transistor, (b) a first P-transistor and a second P-transistor, wherein the first N and first P transistors have respective gate electrodes aligned along the first direction, wherein gate defining shapes of the first N and first P transistors are separated from each other by a first line end spacing, wherein the second N and second P transistors have respective gate electrodes aligned along the first direction, wherein gate defining shapes of the second N and second P transistors are separated from each other by a second line end spacing; a first contact contacting the gate defining shape of the first N transistor; a second contact contacting the gate defining shape of the first P transistor; a third contact contacting the gate defining shape of the second N transistor; and a fourth contact contacting the gate defining shape of the second P transistor, wherein the first and third contacts are offset from each other in the first direction.