Patent ID: 8190788

Claim:
A memory controller that is connected to a volatile memory via a first bus and is connected to a non-volatile memory via a second bus and that controls data transfer from the volatile memory to the non-volatile memory, comprising: a data transfer unit that transfers data being held in a plurality of volatile memories operating in at least either a refresh operation mode or a self-refresh operation mode to the non-volatile memory; and a control unit that, when readout of data from at least one volatile memory by the data transfer unit has been finished, performs control so as to cause the volatile memory to shift from the refresh operation mode to the self-refresh operation mode, wherein the control unit, in a first mode, supplies an enable signal to the plurality of volatile memories to read out data from the plurality of volatile memories, and in a second mode, supplies the enable signal to a part of the plurality of volatile memories to perform transition to the self-refresh mode to the volatile memories that are not supplied with the enable signal.