Patent ID: 8612666

Claim:
An apparatus coupled with a processor, comprising: a NAND flash memory comprising a first memory; a logical-to-physical (LTP) address mapping structure associated with the NAND flash memory, wherein the LTP address mapping structure includes a plurality of LTP entries each providing a logical address to a physical address mapping, wherein the LTP address mapping structure is divided into a plurality of segments; a second memory storing information and instructions to be executed by the processor, wherein the second memory is operable to cache less than all the segments of the LTP address mapping structure; a lookup table having a pointer for each segment of the LTP address mapping structure cached in the second memory and a physical address of each segment of the LTP address mapping structure in the first memory not cached in the second memory; and logic coupled with the NAND flash memory to: use the lookup table to control read and write to segments of the LTP address mapping structure in the NAND flash memory and to add and remove segments of the LTP address mapping structure in the second memory; determine that one of the segments of the LTP address mapping structure not cached in the second memory comprises contiguous physical addresses for all entries in the determined segment not cached in the second memory, and store in the lookup table a physical address corresponding to a first entry of a logical address of the determined one of the segments.