Patent ID: 7583106

Claim:
A circuit comprising: clock circuitry comprising clock generating means arranged to supply a first clock signal having a first faster frequency to a first circuit portion and a second clock signal having a second slower frequency to a second circuit portion, the clock generating means being operable to vary the relative frequency of the first and second clock signals; synchronisation logic arranged to generate pulses based on the first and second clock signals, each pulse indicating when to transfer data between the first circuit portion and the second circuit portion; gating means arranged to produce a gated clock signal by gating the first clock signal, the gating means being open when said pulses are asserted; and transfer means arranged to clock data between the first circuit portion and the second circuit portion when clocked by the gated clock signal; wherein the clock circuitry comprises control logic configured to generate a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge of the first clock signal, and to generate a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge of the second clock signal, the clock generating means being configured such that a change in said relative frequency is conditional on a coincidence of the first and second control signals; and the synchronisation logic is configured to generate said pulses such that there is at least one cycle of the first clock signal between said pulses, and such that there is only one of said pulses per cycle of the second clock signal.