Patent ID: 8412855

Claim:
A method comprising: receiving a plurality of write transactions from a processor with a controller hub, the plurality of write transactions being identified as write combinable transactions, based on a per memory page attribute, and being destined for a device coupled to the controller hub; storing data associated with the plurality of write transactions to a buffer of the controller hub in response to the plurality of write transactions being identified as write combinable transactions; determining whether a latency condition exists, the latency condition including at least a delay in receiving a next combinable write transaction from the processor; flushing the data associated with the plurality of write transactions as write combined data in a single transaction to the device in response to determining the latency condition exists without receiving a flush signal from the processor; sending a write completion signal to the processor for each of the plurality of write transactions in response to the data being flushed to the device, wherein the processor is to refrain from issuing order-dependent transactions between detection of flushing the data and receipt of the write completion signal; and tagging a plurality of buffers of the controller hub with source identifiers associated with one or more write combinable write transactions to allow for ignoring of flushing signals from a non-associated processor.