Patent ID: 7635991

Claim:
An output buffer, comprising: a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage to provide buffer strength upon receipt of a first stage enable signal, and the second stage to provide buffer strength upon receipt of a second stage enable signal, wherein each output stage comprises: a complementary metal oxide semiconductor (CMOS) structure having a p-channel MOS device and an n-channel MOS device; an AND gate having an output connected to a gate of the n-channel transistor, and having two inputs, an input connected to a data signal and another input connected to one of a plurality of enable signals provided by one of a plurality of enable signal generators; and an OR gate having an output connected to a gate of the p-channel transistor, and having two inputs, an input connected to the data signal and another input connected to a complement of the one of the plurality of enable signals.