Patent ID: 7088156

Claim:
A clock generator for generating an output clock signal synchronized with an input clock signal, comprising: a first adjustable delay line configured to delay a buffered clock signal by a first variable delay based on a first adjustment signal; a model delay coupled to the first variable delay line and configured to delay an output clock signal of the first adjustable delay line by a model delay, a second adjustable delay line coupled to the model delay line and configured to delay an output clock signal of the model delay by a second variable delay based on a second adjustment signal; a phase comparison circuit having a first input at which the buffered clock signal is applied, a second input coupled to the second adjustable delay, a delay control output coupled to the second adjustable delay line to provide the second adjustment signal, and a phase output, the phase comparison circuit configured to generate the second adjustment signal to adjust the second variable delay according to the phase difference between the buffered clock signal and a clock signal output by the second adjustable delay line, the phase comparison circuit further configured to reset the second variable delay to a minimum delay in response to the buffered clock signal and the clock signal output by the second adjustable delay line being synchronized and to generate a phase signal provided to the phase output that is indicative of the phase difference between the buffered clock signal and a clock signal output by the second adjustable delay line after the second adjustable delay line is reset; and a delay controller coupled to the phase comparison circuit and the first adjustable delay line, the first delay controller configured to generate the first adjustment signal in response to the phase signal.