Patent ID: 7733141

Claim:
A semiconductor device, comprising: a delay locking unit configured to compare a phase of a feedback clock with a phase of a reference clock for achieving a delay-locking, and configured to delay an internal clock corresponding to a clock edge of the reference clock by a delay time corresponding to a comparison result to output a delay locked loop (DLL) clock; a split unit configured to receive and split the DLL clock to output a first clock corresponding to a first edge of the DLL clock and a second clock corresponding to a second edge; a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock; a voltage comparison unit configured to compare levels of the first and second voltages with each other; and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.