Patent ID: 8478947

Claim:
A memory controller for controlling a memory, said memory having a plurality of communication modes, said memory controller comprising: memory interface logic configured to interact with said memory in each of said plurality of communication modes; and memory mode change logic, in response to a memory mode change request instruction specifying a predetermined one said plurality of communication modes issued by said memory interface logic to said memory, configured to request said memory interface logic to interact with said memory in said predetermined one of said plurality of communication modes and to prevent interaction between said memory interface logic and said memory until said memory interface logic confirms that said memory interface logic is configured to interact with said memory in said predetermined one of said plurality of communication modes, wherein said plurality of communication modes includes at least a synchronous mode and an asynchronous mode and said memory interface logic comprises an interface configuration register configured to store timing parameters which configure the memory interface logic to interact with said memory in one of said synchronous mode and said asynchronous mode and a holding interface configuration register configured to store timing parameters associated with a predetermined one of said synchronous mode and said asynchronous mode, said memory mode change logic responsive to said memory mode change request instruction specifying said predetermined one of said synchronous mode and said asynchronous mode issued by said memory interface logic to said memory to request said memory interface logic to cause said timing parameters of said holding interface configuration register to transfer into said interface configuration register to cause said memory interface logic to interact with said memory in said predetermined one of said synchronous mode and said asynchronous mode.