Patent ID: 7371627

Claim:
A method of fabricating a memory array comprising: forming a plurality of data/bit lines in a surface of a semiconductive substrate so as to extend in a first direction; forming a first mask layer on the surface of the substrate; forming first elongate openings in the first mask layer so as to be aligned generally with and extending along corresponding data/bit lines; depositing sidewall material in the first openings of the first mask layer; directionally etching the sidewall material so as to form first sidewall spacers arranged against inner surfaces of the first openings and defining generally centrally arranged first trenches in the first sidewall spacers between opposed first sidewall spacers; forming first plug strips in corresponding first trenches; performing a directional etch with the first plug strips as masking structures to substantially remove the first sidewall spacers and the first mask layer and so as to define a corresponding plurality of pillar strips extending generally vertically from the surface of the substrate and substantially conforming to the contour and position of the first plug strips; filling interstitial spaces between the pillar strips with fill material; forming a second mask layer on the surface of the substrate; forming second elongate openings in the second mask layer so as to overlie in an intersecting manner and extend in a second direction across corresponding data/bit lines and the pillar strips; depositing sidewall material in the second openings of the second mask layer; directionally etching the sidewall material so as to form second sidewall spacers arranged against inner surfaces of the second openings and defining generally centrally arranged second trenches in the second sidewall spacers between opposed second sidewall spacers; forming second plug strips in corresponding second trenches; performing a directional etch with the second plug strips as masking structures to substantially remove the second sidewall spacers and the second mask layer and so as to define a corresponding plurality of pillars extending generally vertically from the surface of the substrate and substantially conforming to the contour and position of intersections of the first and the second plug strips; and forming gate structures about the pillars such that the gate structures substantially completely laterally encompass corresponding pillars.