Patent ID: 7127021

Claim:
A phase detector for Non-Return-to-Zero (NRZ) data, comprising: a first circuit for dividing an input NRZ data stream into first and second data streams corresponding to the input NRZ data stream and the inverse of the input NRZ data stream, respectively; a first series of flip-flops through which the first data stream is propagated; first and second exclusive-OR gates each having a first input coupled to said first series of flip-flops to provide first pulse-up and pulse-down signals; a second series of flip-flops through which the second data stream is propagated; third and fourth exclusive-OR gates each having a first input coupled to said second series of flip-flops to provide second pulse-up and pulse-down signals; a first delay circuit for providing the first data stream to a second, input of said first exclusive-OR gate; and a second delay circuit for providing the second data stream to a second input of said third exclusive-OR gate, wherein a second input of said second exclusive-OR gate is coupled to a data output of a fourth flip-flop in said first series of flip-flops, and wherein a second input of said fourth exclusive-OR gate is coupled to a data output of a fourth flip-flop in said second series of flip-flops.