Patent ID: 8212828

Claim:
An apparatus comprising: a processor configured to (a) process pixel data comprising eight or more bits, wherein for pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of said pixel are packed with LSBs from one or more other pixels into a second byte, and the first and the second bytes are stored, (b) retrieve said first byte and said second byte and reassemble the pixel data having bit-depths greater than eight bits from said first byte and said second byte, (c) retrieve the stored first bytes, generate a compressed bitstream using only the first bytes, and store said compressed bitstream, wherein said compressed bitstream comprises at least one of (i) a MPEG-2 compliant compressed bitstream, (ii) a MPEG-4 compliant compressed bitstream, and (iii) a H.264 compliant compressed bitstream, (d) retrieve said compressed bitstream and generate a multi-bit data stream having a bit-depth greater than eight bits using said compressed bitstream, and (e) generate a video output signal in response to (i) the original pixel data in a first mode, (ii) the reassembled pixel data in a second mode, and (iii) the multi-bit data stream in a third mode; and a memory coupled to said processor and configured to store said first byte in response to a first pointer and said second byte in response to a second pointer, wherein said first byte and said second byte are stored independently in said memory and said memory is further configured to store said compressed bitstream.