Patent ID: 8129706

Claim:
A memory device comprising: a top electrode structure vertically separated from a bottom electrode, the bottom electrode comprising a plug; an upper programmable resistive memory member having a contact surface in contact with the top electrode structure and having a bottom surface area; a lower programmable resistive memory member having a contact surface in contact with the bottom electrode and having a top surface area; a lower dielectric fill layer surrounding the bottom electrode and the lower programmable resistive memory member, the lower dielectric fill layer having a top surface; an upper dielectric fill layer having a via extending therethrough over the lower programmable resistive memory member, the via having a bottom surface area smaller than the top surface area of the lower programmable resistive memory member, the upper dielectric fill layer having a bottom surface; a first interface between the top surface area of the lower programmable resistive area and the bottom surface area of the upper programmable resistive memory member; a second interface between the top surface of the lower dielectric fill layer and the bottom surface of the upper dielectric fill layer, wherein the first interface and the second interface are coplanar; a dielectric sidewall spacer within the via and on the lower programmable resistive memory member, the dielectric sidewall spacer having an inner surface defining an opening within the via; and a kernel member comprising a programmable resistive memory material within the opening of the dielectric sidewall spacer and extending from the upper to the lower programmable resistive memory member, the kernel member having a width less than that of the upper and lower programmable resistive memory members, wherein the upper programmable resistive memory member, the lower programmable resistive memory member, and the kernel member, each have a lower thermal conductivity than the dielectric sidewall spacer.