Patent ID: 8843861

Claim:
A computer-implemented method comprising: generating, using a processing unit, a verification model that represents an electronic design including a proprietary component, the proprietary component being a pre-designed, reusable third-party component, the electronic design including design components coupled to the proprietary component, wherein the design components are not reusable, third-party components; wherein generating the verification model includes inserting an instrumentation component between the proprietary component and the design components so that the proprietary component is coupled to both the design components and the instrumentation component to passively capture signals there between; causing a verification tool to implement the verification model; determining a state of the verification model at a first point of a verification process applied to the implemented verification model by the verification tool; determining one or more signal values on one or more signal lines that interconnect the proprietary component with the electronic design from the first point during the verification process until a second point during the verification process; and generating a reference model for the electronic design from the verification model, the reference model, the determined state and the determined signal values usable to debug the proprietary component.