Patent ID: 8266380

Claim:
A cache memory control method used for controlling an access to cache memory comprising, for each entry, a data part for storing data and a tag part for storing a tag address which is for indexing the data, comprising: dividing an address for accessing the cache memory into a first field through a fourth field from an uppermost bit side, the accessing being performed for each entry in units of block data having 2 c lines×2 f pixels in the cache memory, wherein c and f are integers and are changed dynamically according to a signal sent from a processor core which corresponds to content of image processing; using the first and third fields for storing tag addresses; dividing the second field into a first subfield for storing an index address and a second subfield for storing a line address, the second subfield having c bits; and dividing the fourth field into a third subfield for storing an index address and a fourth subfield for storing a line address, the fourth subfield having f bits, wherein dividing an address for accessing the cache memory includes compounding unselected bits for an index address in the second and fourth fields as bits for a line address and the compounded result is to be output to a data selector.