Patent ID: 8134201

Claim:
A semiconductor memory device comprising: a memory cell transistor comprising a first stacked layer gate including a first insulating film formed on a first active region in a semiconductor substrate via a first gate insulating film, for accumulating charges, a second insulating film formed on the first insulating film using material having dielectric constant higher than that of the first insulating film, and a control gate electrode formed so as to include a first metal film formed on the second insulating film and a first conductive film formed on the first metal film and comprising a silicide film, and a first impurity diffusion layer functioning as a source and a drain; a first MOS transistor comprising a second stacked layer gate including a second conductive film formed on a second active region in the semiconductor substrate via a second gate insulating film, a second metal film formed on the second conductive film, and a third conductive film formed on the second metal film and comprising a silicide film, and a second impurity diffusion layer functioning as a source and a drain; and a second MOS transistor comprising a third stacked layer gate including a fourth conductive film formed on a third active region in the semiconductor substrate via a third gate insulating film, a third metal film formed on the fourth conductive film, and a fifth conductive film formed on the third metal film and comprising the silicide film, and a third impurity diffusion layer functioning as a source and a drain, wherein a thickness of the third gate insulating film is larger than that of the second gate insulating film, upper faces of the second gate insulating film and the third gate insulating film are located at a same level, and upper faces on the second metal film and the third metal film are located at a same level.