Patent ID: 7326602

Claim:
A fabricating method of a thin film transistor array, comprising: forming a first patterned conductive layer over the substrate; forming a gate insulator and a semiconductor material layer over the substrate and the first patterned conductive layer sequentially; forming an etching stop layer located above the first patterned conductive layer over a portion of the semiconductor material layer; forming a second conductive material layer over the semiconductor material layer and the etching stop layer; patterning the second conductive material layer and the semiconductor material layer to simultaneously form a second patterned conductive layer and a plurality of semiconductor layers, which are located under the etching stop layer and the second patterned conductive layer; forming a passivation layer over the substrate; removing a portion of the passivation layer, which is located on the second patterned conductive layer, to form a plurality of contact windows, and removing a portion of the passivation layer, the etching stop layer and the semiconductor layers, which are located above the first patterned conductive layer, simultaneously; and forming a plurality of pixel electrodes over the substrate, wherein each pixel electrode is electrically connected to the second patterned conductive layer through one of the contact windows, and a portion of each pixel electrode is coupled to the first patterned conductive layer through one of the openings to form a storage capacitor.