Patent ID: 6839289

Claim:
A semiconductor storage device comprising: a first bit line; a memory cell that is connected to the first bit line and stores data; a second bit line; a first reference cell that is connected to the second bit line and holds a potential corresponding to specified data; a first signal line that is connected to the first reference cell and supplies the potential held in the first reference cell; a third bit line; a second reference cell that is connected to the third bit line and holds a potential corresponding to specified data; a second signal line that is connected to the second reference cell and supplies the potential held in the second reference cell; a switch circuit that is connected between the second bit line and the third bit line and electrically connects the second bit line with the third bit line in response to a first control signal; a potential supply circuit having first and second states wherein in the first state, the potential supply circuit responds to a second control signal at a first potential level, supplies the first reference cell with a potential corresponding to first data via the first signal line, and supplies the second reference cell with a potential corresponding to second data via the second signal line; and wherein in the second state, the potential supply circuit responds to the second control signal at a second potential level, supplies the first reference cell with the potential corresponding to the first data via the first signal line, and supplies the second reference cell with the potential corresponding to the first data via the second signal line; and a data read circuit that is connected to either the second bit line or the third bit line and the first bit line and compares a potential generated on the second bit line or the third bit line with a potential generated on the first bit line.