Patent ID: 7120082

Claim:
A wordline circuitry segment in an SRAM device, the circuitry segment comprising: a first node coupled to a wordline enable signal; a second node coupled to a wordline signal; a third node coupled to a sleep mode assertion signal; a fourth node coupled to a first reference voltage; a fifth node coupled to a second reference voltage; a first transistor structure, having a first terminal coupled to the first node, a second terminal coupled to the fourth node, and a third and fourth terminal; a second transistor structure, having a first terminal coupled to the fourth terminal of the first transistor structure, a second terminal coupled to the fourth node, a third terminal coupled to the third terminal of the first transistor structure, and a fourth terminal coupled to the second node; a third transistor structure, having a first terminal coupled to the third node, a second terminal coupled to the third terminal of the first transistor structure, and a third terminal coupled to a third reference voltage; and a fourth transistor structure, having a first terminal coupled to the fifth node, a second terminal coupled to the fourth node, and a third terminal coupled to the second node.