Patent ID: 7911824

Claim:
A nonvolatile memory apparatus comprising: a plurality of memory cell arrays each including a plurality of nonvolatile memory elements having a characteristic in which a resistance value thereof changes according to electric pulses applied; and a control section which is configured to, in writing of data for the plurality of memory cell arrays, write data to a memory cell array and read data from another memory cell array such that writing of the data and reading of the data occur concurrently; wherein the control section includes: an address latch for temporarily holding address data input externally; a read data latch for temporarily holding read data which has been read from a nonvolatile memory element corresponding to the address data input externally; a write data latch for temporarily holding write data input externally; a comparator/determiner portion for comparing the write data held in the write data latch to the read data held in the read data latch; a write portion for inputting an electric pulse to the memory cell array, based on a determination result output from the comparator/determiner portion; a write switch for connecting the write portion to a specified memory cell array; a read switch for connecting the read data latch to a specified memory cell array; and an interleaving write control circuit which is configured to control the write switch to connect the write portion to a specified memory cell array at a specified timing and control the read switch to connect the read data latch to a specified memory cell array at a specified timing.