Patent ID: 7302090

Claim:
A method for determining integrity of an integrated circuit, comprising: determining a simulated resist image for an integrated circuit, wherein determining a simulated resist image involves using an equation of the form ( ∂ S ∂ x ) 2 + ( ∂ S ∂ y ) 2 + ( ∂ S ∂ z ) 2 = ( I ⁡ ( 0 ) I ⁡ ( x , y , z ) ) 2 ⁢ γ ⁢ ( 1 r 0 ) 2 , wherein I(x,y,z) is intensity used to illuminate the resist at a point (x,y,z) of the resist, I(0) is reference intensity obtainable from equation I(0)=E 0 /E, where E is incident light dose in large exposed areas of the resist and E 0 is a threshold , γ is a non-linearity parameter describing non-linearity of one of a developing or resist process, and r 0 is a factor obtainable from equation D eff =r 0 ·t, wherein D eff is effective resist thickness and t is developing time; comparing the simulated resist image of the circuit with a design of the circuit to obtain predictions about a circuit obtainable in a manufacturing process; and detecting deviations between the simulated resist image and the design which differ from a rated value by more than a tolerance value, the simulated resist image having a surface function of the form S(x,y,z) describing uniform propagation of a surface in a resist to be simulated under illumination.