Patent ID: 6946887

Claim:
A phase-locked loop circuit comprising: a voltage controlled oscillator adapted to provide a first clock signal comprising a first frequency; and a phase frequency detector adapted to compare the first clock signal comprising the first frequency to a reference clock signal comprising a reference frequency, the phase frequency detector comprising a programmable circuit adapted to vary a minimum pulse width of an increment pulse and a minimum pulse width of a decrement pulse, the programmable circuit being further adapted to reduce a static phase error of the phase locked-loop circuit, wherein the programmable circuit comprises an operational amplifier, a first capacitor, a second capacitor, and a delay line wherein the operational is adapted to compare a first analog voltage across the first capacitor to a reference voltage across the second capacitor and generate a control voltage based on the comparison, wherein the control voltage is adapted to control the delay line to vary the minimum pulse width of the increment pulse and the minimum pulse width of the decrement pulse, and wherein the minimum pulse width of the increment pulse and the minimum pulse width of the decrement pulse comprise a fixed fraction of a period of the reference clock signal.