Patent ID: 6943393

Claim:
A memory cell arrangement comprising: a memory cell array having at least one layer of magnetoresistive memory components, each of which has at least two ferromagnetic layers, first and second dielectric layers, copper first contact-making lines lying within the first dielectric layer, the first contact-making lines being connected to a first of the at least two ferromagnetic layers, copper second contact-making lines lying within the second dielectric layer, the second contact-making lines being connected to a second of the at least two ferromagnetic layers, and a silicon nitride diffusion barrier layer between the first contact-making lines and the second dielectric layer, the diffusion barrier layer being in direct contact with the magnetoresistive memory components and being configured to minimize memory drift by suppressing diffusion of copper out of the first contact-making lines into the second dielectric layer and into the magnetoresistive memory components, and by suppressing interdiffusion between the ferromagnetic layers and the first contact-making lines.