Patent ID: 7564128

Claim:
A power power semiconductor die package, comprising: a power semiconductor die sandwiched between first and second insulative thermally conductive substrates through which heat generated during testing and operation of the power semiconductor die is dissipated, the power semiconductor die having first and second oppositely disposed major faces and one or more terminals formed on each of said major faces; a set of planar surface-mount die package terminals formed on an outboard face of the second substrate to configure said power semiconductor die package as a surface-mount component; and a set of interconnect conductors formed on the first and second insulative thermally conductive substrates for electrically interconnecting each of the terminals of said power semiconductor die to the planar surface-mount die package terminals formed the outboard face of the second substrate so that said power semiconductor die is electrically testable at full power in said die package prior to surface-mounting said die package in an electronic assembly.