Patent ID: 8184499

Claim:
A semiconductor memory apparatus comprising: first and second memory banks located at a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the column areas of the first memory bank and transfer write data to the column areas of the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the column areas of the second memory bank and transfer write data to the column areas of the second memory bank, wherein the first data read/write unit and the second data read/write unit are located so as to be spaced from each other in the first direction with the memory bank interposed therebetween.