Patent ID: 8706974

Claim:
A data processing system, comprising: a system interconnect; a first master communicatively coupled to initiate a transaction on the system interconnect, the transaction having a corresponding access address; a cache coherency manager communicatively coupled to the system interconnect; and a second master, the second master comprising: a cache; and snoop circuitry which receives snoop requests from the cache coherency manager, wherein a snoop lookup in the cache is performed for received snoop requests, and, in response to each snoop lookup, a snoop response is provided to the cache coherency manager, wherein when the cache coherency manager provides a snoop request corresponding to the transaction initiated by the first master to the snoop circuitry of the second master, the snoop circuitry is configured to be capable of performing a snoop lookup operation for the snoop request corresponding to the transaction initiated by the first master after completion of the transaction initiated by the first master on the system interconnect, and wherein a second transaction subsequent to the transaction can be initiated on the system interconnect prior to the completion of the snoop lookup; the cache coherency manager is communicatively coupled to the system interconnect to snoop transactions on the system interconnect, the cache coherency manager provides a snoop request to the snoop circuitry responsive to a snooped transaction on the system interconnect.