Patent ID: 7194602

Claim:
A data processor, comprising: a first register file including a plurality of registers; a second register file including a plurality of resisters, the number of which is larger than that of the registers of the first register file; an instruction decoder; and an operation unit connected to the first and second register files so that operand data stored in the first and second register files are directly provided to the operation unit, wherein the instruction decoder receives an instruction described in a first instruction format including a register-addressing field of a predetermined size and an instruction described in a second instruction format including a register-addressing field of a size larger than the size of the register-addressing field included in the first instruction format, and said instruction decoder directly decodes each of the instructions described in the first and second instruction formats, which are formats different from each other, and the operation unit executes, when the instruction decoder decodes an instruction described in the first instruction format, the instruction described in the first instruction format, using operand data stored in the first register file, while the operation unit executes, when the instruction decoder decodes an instruction described in the second instruction format, the instruction described in the second instruction format, using operand data stored in the second register file.