Patent ID: 8405156

Claim:
A semiconductor device, comprising: a substrate; an isolation region formed in the substrate to isolate an element formation region from another region; a gate electrode formed over the element formation region to extend over each of first and second regions of the isolation region opposing each other with the element formation region interposed therebetween; and a pair of diffusion regions formed in the element formation region so as to be spaced apart from each other in a channel length direction with reference to the gate electrode, wherein at least a portion of each of upper surfaces of the first and second regions is depressed to a depth of not less than 5% of a channel width to be located under an upper surface of the element formation region, and a portion of the gate electrode is arranged in each of resultant depressions, wherein the element forming region is arranged, in a first direction, between a first region of the substrate and a second region of the substrate, wherein the element forming region is arranged, in a second direction, between a third region and a fourth region of the substrate such that the upper surface of the element forming region is higher than an upper surface of the third region and an upper surface of the fourth region, and wherein the element forming region is surrounded by the first region of the substrate, the second region of the substrate, the third region of the substrate, and the fourth region of the substrate in a plane view of the substrate.