Patent ID: 7288812

Claim:
A semiconductor memory with virtual ground architecture, the memory comprising: a plurality of memory cells, each memory cell having a respective memory transistor, the memory cells being arranged row-wise and column-wise; each memory transistor comprising a channel region between source/drain regions that are formed in a semiconductor material, each memory transistor further comprising a gate electrode, which is isolated from the channel region by a storage layer sequence that is provided for trapping charge carriers from the channel region; a plurality of word lines arranged parallel at a distance from one another, wherein each of the gate electrodes is coupled to one of the word lines, each word line overlying a row of the memory cells such that the word line is over the channel region between the source/drain regions; a plurality of bit lines running transversely with respect to the word lines, the bit lines and the word lines being operable to address the memory cells; and a plurality of insulation regions extending between no more than two of the word lines; wherein, in accordance with a consecutive numbering of the source/drain regions along a respective word line, in the case of which the source/drain regions of a single memory transistor are on different sides of the word line and lie opposite one another with respect to the word line in each case acquire the same number, a) on one side of the word line, each even-numbered source/drain region is electrically insulated from the subsequent odd-numbered source/drain region by an insulation region, b) on the opposite side of said word line, each odd-numbered source/drain region is electrically insulated from the subsequent even-numbered source/drain region by another insulation region.