Patent ID: 8735227

Claim:
A method for fabricating a semiconductor device with minimized current flow differences comprising: forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, wherein the second layer is on top of the first layer; determining a normal source pillar width of the semiconductor device being fabricated by the method, wherein the source pillar width is a cross-sectional width of the source pillar in the semiconductor device; forming a plurality of gates in the semiconductor layer stack having a second conductivity type; and forming a plurality of mesas in the semiconductor layer stack, wherein the gates are situated partially at a periphery of the mesas, wherein the plurality of mesas are source pillars of the semiconductor device and the forming a plurality of mesas includes increasing the width of each of the plurality of mesas to a width greater than the determined normal source pillar width, thereby increasing the spacing of the formed gates, wherein the forming a plurality of gates and the forming a plurality of mesas minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device by increasing the spacing between each of the gates, and wherein the forming a plurality of gates includes: masking the plurality of mesas with a plurality of masks that are each wider than each mesa, wherein the masks cover and protect the plurality of mesas from dopant implantation; implanting the semiconductor layer stack; and removing the masks.