Patent ID: 8134239

Claim:
An address line wiring structure comprising an address signal line that connects between at least three memory elements and a data transferring element for transferring data among the at least three memory elements and that transmits address signals for the memory elements, the address signal line having a stub structure including branch lines branched from a main line to the respective memory elements, wherein: an address terminal of the data transferring element has an output impedance lower than a characteristic impedance of the address signal line; a wiring length TL 0 from the data transferring element to a first branch point S 1 where a branch line is branched at a shortest distance from the data transferring element is configured to become substantially equal to or greater than a wiring length TL 1 from the first branch point S 1 to a second branch point S 2 where a second branch line is branched; and a wiring length TL 3 from the second branch point S 2 to a third branch point S 3 where a third branch line is branched is configured to become greater than the wiring lengths TL 0 and TL 1 .