Patent ID: 7298809

Claim:
A Phase-Locked Loop with multiphase clocks for use in a digital system, said Phase-Locked Loop comprising: a main loop comprising, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider; a calibration loop comprising Y Calibration Loop Filters, with Y being an integer, coupled to the Multi-Phase Voltage Controlled Oscillator, and Control Logic for controlling the Phase-Switching Fractional Divider; and a Demultiplexer coupled between an output of the Main Charge Pump and inputs of the Main Loop Filter and the Y Calibration Loop Filters, wherein the Phase Frequency Detector includes an input for receiving a Reference Frequency Signal, the Demultiplexer includes an input for receiving a control signal from the Control Logic, and the Control Logic includes a control input for receiving a Calibration Signal.