Patent ID: 7112840

Claim:
A semiconductor memory device, comprising: a plurality of plugs formed in a first inter-layer insulation layer deposited on a substrate; a second inter-layer insulation layer formed on a structure containing the plurality of the plugs; a first conductive layer electrically connected to a first group of the plugs by passing through the second inter-layer insulation layer; a first capacitor formed on a second group of the plugs adjacent to the first group of the plugs by passing through the second inter-layer insulation layer and planarized at the same plane level of the second inter-layer insulation layer and the first conductive layer; a third inter-layer insulation layer formed on a structure containing the first capacitor and the first conductive layer; a second capacitor formed on a structure containing the first conductive layer, the second capacitor electrically connected to the first conductive layer by passing through the third inter-layer insulation layer; and a second conductive layer electrically connected to the first capacitor by passing through the third inter-layer insulation layer and planarized at the same level of the second capacitor and the third inter-layer insulation layer.