Patent ID: 7392500

Claim:
A method of modifying a user circuit in a programmable logic device (PLD) to reduce power consumption, the method comprising: identifying within the user circuit a first sub-circuit including combinational logic and a first single-bit register coupled in series, wherein the combinational logic precedes the first single-bit register and provides a single output signal thereto; replacing the first sub-circuit by a second sub-circuit comprising a multi-bit register and the combinational logic coupled in series, wherein the multi-bit register precedes the combinational logic and provides a plurality of registered signals thereto; implementing the combinational logic in a lookup table (LUT) included in a programmable logic block of the PLD; implementing the multi-bit register in a plurality of input memory elements in the programmable logic block, each of the input memory elements providing a data input signal to the LUT; and outputting the user circuit for implementation in the PLD.