Patent ID: 8081019

Claim:
A device for generating a compensation signal for a power converter comprising: a) a frequency-locked clock, coupled to an AC-line having an AC-line voltage frequency, generating a frequency that is frequency locked to an integral multiple of the AC-line voltage frequency, wherein the frequency-locked clock is a phase-locked-loop configured to selectively lock to twice the AC-line voltage frequency; b) a bus-voltage sampler, operatively coupled to the frequency-locked clock and coupled to a power converter bus having a bus-voltage, generating bus-voltage data at the frequency; c) a stack of the bus-voltage data, operatively coupled to the bus-voltage sampler, wherein the stack is structured to contain the bus-voltage data sampled from a time interval of one-half cycle of an AC-line voltage; and d) a compensation module, operatively coupled to the stack and configured to generate from the bus-voltage data a compensation signal, and wherein the compensation module is configured to produce the compensation signal in which frequency components at even multiples of AC-line voltage frequency are minimized.