Patent ID: 8502575

Claim:
An apparatus including fractional-N phase-locked loop (PLL) circuitry, comprising: programmable phase comparison signal generator circuitry responsive to one or more reference control signals and a reference signal having a reference frequency F ref by providing a comparison signal having a programmable comparison frequency F pd ; phase detector circuitry coupled to said programmable comparison signal generator circuitry and responsive to said comparison signal and a feedback signal by providing a phase detection signal; controllable oscillator circuitry coupled to said phase detector circuitry and responsive to said phase detection signal by providing a PLL output signal having one F ch of a plurality of output frequencies each of which is equal to a multiple of said comparison frequency; and programmable feedback frequency divider circuitry coupled to said controllable oscillator circuitry and said phase detector circuitry, and responsive to said PLL output signal and one or more feedback control signals by providing said feedback signal; wherein said plurality of output frequencies is bounded by minimum F l and maximum F h output frequencies in relation to said one or more feedback control signals, a predetermined minimum offset frequency F os — min is defined in relation to a difference between each of said plurality of output frequencies and a respective one of a plurality of primary fractional spurious signal frequencies, and said reference frequency F ref is greater than or equal to a sum of a difference F h −F l between said maximum and minimum output frequencies, and double said minimum offset frequency 2F os — min .