Patent ID: 8645777

Claim:
A memory device comprising: a system element; and a memory stack including one or more memory die layers, each memory die layer including a plurality of input-output (I/O) cells and a boundary scan chain for the I/O cells; wherein a boundary scan chain of a memory die layer includes: a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including: a first scan logic multiplexer including a first input from the I/O cell and a second input from a prior scan chain portion in the scan chain or, if the scan chain portion is a first scan chain portion in the scan chain, a serial data input; a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer; for each I/O cell that is a data I/O cell, a second scan logic multiplexer, the second scan logic multiplexer including a first input from a memory output latch and a second input coupled with an output of the scan logic latch; and for each I/O cell that is a command address bus cell, a scan logic driver, an input of the scan logic driver being coupled to an output of the scan logic latch and an output being coupled to the I/O cell, and a decoder to provide command signals to the scan chain.