Patent ID: 7786972

Claim:
A shift register including a plurality of stages, each stage comprising: first, second, and third output nodes; first, second, and third input lines adapted to supply first, second and third clock signals; a fourth input line adapted to supply a start pulse or an output signal of a previous stage; a voltage level controller coupled between the second and fourth input lines, the voltage level controller being adapted to control voltage levels of the first and second output nodes according to the second clock signal and the start pulse or the output signal of the previous stage; a first transistor coupled between a first power supply and the third output node, the third output node being an output node of the stage, the first transistor including a gate electrode coupled to the first output node; a second transistor coupled between the third output node and the third input line, the second transistor including a gate electrode coupled to the second output node; and a third transistor coupled between the first output node and a second power supply, the third transistor including a gate electrode coupled to the first input line, the voltage level controller including: a fourth transistor coupled between the fourth input line and the second output node, the fourth transistor including a gate electrode coupled to the second input line; a fifth transistor coupled between the first power supply and the first output node, the fifth transistor including a gate electrode coupled to the fourth input line; and a sixth transistor coupled between the first power supply and the first output node, the sixth transistor including a gate electrode coupled to the second output node, the gate electrode of the sixth transistor coupled to a different node than the gate electrode of the fifth transistor.