Patent ID: 7400628

Claim:
A data processing circuit utilized for a serial interface comprising: a receiving circuit coupled to an application side which receives as input a plurality of packet data of a plurality of channels therefrom; a selection circuit having a channel identification data extracting circuit for extracting channel identification data regarding a number of selected channels in said input packet data, a comparison circuit for comparing said extracted channel identification data with channel specifying data, and a packet data validity instruction signal generation circuit for outputting a packet data validity instruction signal indicating whether said packet data is valid or not based on a result of the comparing; a circuit for providing insert data; and a transmission circuit for providing said input packet data to a data transmission path when said packet data validity instruction signal is valid, and for transmitting said insert data to said data transmission path when the instruction signal is invalid, wherein said insert data is information data regarding said selected channel, and wherein the data transmission path is an IEEE (Institute of Electrical and Electronics Engineers) 1394 serial bus.