Patent ID: 7260686

Claim:
A prefetcher for managing predictive accesses with a memory comprising: a speculator configured to generate a range of predictions, said range of predictions including a range of predicted addresses; a first cache configured to store predictions, at least one of which is addressable by a first representation of an address from said range of predictions; a second cache configured to store predictions, at least one of which is addressable by a second representation of said address from said range of predictions, wherein said first representations and said second representations of said range of predictions are compared in parallel against said stored predictions of said first cache and said second cache, respectively; a first matcher configured to compare said first representations against said stored predictions of said first cache, each of said first representations including a common portion and a delta portion; and a second matcher configured to compare said second representations against said stored predictions of said second cache, each of said second representations including a base portion, wherein said second matcher is configured to compare said base portion of an address of said range of predictions against said stored predictions of said second cache to form a group of unordered tag comparison results (“TCRs”), each of said unordered TCRs indicating whether said common portion for said address matches one of said common portions for said stored predictions; and an orderer configured to rearrange an order of valid bits to form a group of reordered valid bits for AND-ing against said group of unordered TCRs, thereby providing for ordered predictions.