Patent ID: 7075182

Claim:
A semiconductor device comprising: a first conductive pattern; a second conductive pattern formed adjacent to the first conductive pattern and being in substantially parallel with the first conductive pattern; a first conductor plug formed below a prescribed region of the first conductive pattern and connected to the first conductive pattern; a second conductor plug formed over the prescribed region of the first conductive pattern and connected to the first conductive pattern; a third conductor plug formed below a prescribed region of the second conductive pattern and connected to the second conductive pattern, the prescribed region of the second conductive pattern being adjacent to the prescribed region of the first conductive pattern; a fourth conductor plug formed over the prescribed region of the second conductive pattern and connected to the second conductive pattern; a third conductive pattern formed above the first conductive pattern and connected to the second conductor plug; and a fourth conductive pattern formed above the second conductive pattern and connected to the fourth conductor plug, the fourth conductor plug being arranged at a position which is offset from the second conductor plug.