Patent ID: 6999547

Claim:
A digital Delay-Lock-Loop (DLL) circuit comprising: a phase generator operable to produce a first clock signal having a first rising edge and a second clock signal having a second rising edge, wherein a timing difference between said first rising edge and said second rising edge is equal to a desired cycle time; a binary-weighted delay circuit operable to receive said first clock signal and to produce a delayed clock signal; a phase-shifted delay circuit connected to said binary-weighted delay circuit; and a latch element connected to said binary-weighted delay circuit, said latch element operable to cheek whether said delayed clock signal is delayed by an amount equal to said desired cycle time, wherein at said latch element, said second clock signal is used to capture a delay of said first clock signal, wherein delay elements of said binary-weighted delay circuit are intermixed with delay elements of said phase-shifted delay circuit.