Patent ID: 7244985

Claim:
A non-volatile memory array, comprising: a plurality of memory units arranged in a row/column array, and each of the memory units comprising: a first conductive type well region disposed in a substrate; a second conductive type source region, a second conductive type doped region and a second conductive type drain region disposed in the first conductive type well region; a select gate, disposed on the substrate between the second conductive type source region and the second conductive type doped region; a control gate, disposed on the substrate between the second conductive type doped region and the second conductive type drain region, wherein the select gate and the control gate are formed of same layer gate material; and a charge storage structure, wherein the charge storage structure comprises at least a charge storage layer disposed between the control gate and the substrate, and in the memory units of the same row, two adjacent memory units are arranged in a mirror symmetric manner; a plurality of source lines disposed in parallel in a column direction, connecting to the second conductive type source regions of the memory units of the same column; a plurality of bit lines disposed in parallel in a row direction, connecting to the second conductive type drain regions of the memory units of the same row; a plurality of word lines disposed in parallel in the column direction, connecting to the select gates of the memory units of the same column; a plurality of control lines disposed in parallel in the column direction, connecting to the control gates of the memory units of the same column, wherein the control lines are grouped with every n control lines in one group (n is a positive integer which is greater or equal to 2), and are electrically connected to each other.