Patent ID: 8077537

Claim:
A memory controller which controls a memory device having: a plurality of banks that respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit which controls operation of the memory cores within the plurality of banks, the memory controller comprising: a sequencer which, in response to an access request from a host device, supplies a normal operation command corresponding to the access request and the bank addresses to the memory device, and causes the memory cores within normal access target banks selected by the bank addresses to execute normal operation, the sequencer, in response to the access request, supplying, to the memory device, refresh bank information specifying banks other than the normal access target banks, and refresh burst length designating the number of times that refresh operation is performed, along with a background refresh command, and, during the normal operation, causing the memory cores within refresh target banks related to the refresh bank information to successively execute the refresh operation, in which a word line is driven so that a data stored in a memory cell connected to the word line is restored in the memory cell, a number of times corresponding to the refresh burst length.