Patent ID: 7587643

Claim:
An integrated circuit comprising: electrical circuitry; a plurality of pins/pads to interface at least a portion of the electrical circuitry; a first pin/pad of the plurality to receive a static signal for selecting a particular operative mode during a normal operation of the integrated circuit, and a serial data signal for assisting test during a sneaky JTAG test access operation of the integrated circuit; a packet decoder configured to receive serial data of the serial data signal received from the first pin/pad during the IC operability for the sneaky JTAG test access and decode JTAG (Joint Test Action Group) signals from packets of the serial data when received; a JTAG processor to act on at least a portion of the electrical circuitry dependent on the JTAG signals decoded; and a mode select controller configured to receive from the first pin/pad the static signal for selecting the particular operative mode for the integrated circuit when under the normal operation, the selecting is based on the level of the static signal received and further dependent on absence of the sneaky JTAG test access operation.