Patent ID: 8000140

Claim:
A memory device, comprising: a plurality of row lines and a plurality of column lines; a memory cell comprising an access transistor and a CMOS-compatible non-volatile storage element comprising a control gate and coupled to the access transistor in series, wherein: the CMOS-compatible non-volatile storage element is configured to hold a charge corresponding to a n-bit binary value, wherein n is an integer; the access transistor comprises a word line gate coupled to one of the plurality of row lines, a first node, a second node, and a storage node; the first node is coupled to one of the plurality of column lines; and the storage node is coupled to the second node and to the CMOS-compatible non-volatile storage element; and access circuitry coupled to the plurality of row lines and to the plurality of column lines, wherein the access circuitry is configured to, as part of a read operation: set a first select voltage on the word line gate of the access transistor; set a second select voltage on the control gate of the CMOS-compatible non-volatile storage element, wherein the first select voltage is greater than the second select voltage; and sense a resultant current corresponding to the n-bit binary value; wherein the access circuitry is further coupled to the control gate of the CMOS-compatible non-volatile storage element and to a drain line, and wherein the access circuitry is further configured to, as part of a write operation: set one of the plurality of row lines to the first select voltage; set the drain line to a programming voltage; and set the control gate to the programming voltage.