Patent ID: 8477626

Claim:
A packet processing apparatus comprising: a first packet processing apparatus; a second packet processing apparatus for processing a packet transmitted from said first packet processing apparatus, said second packet processing apparatus comprising: a packet selecting means ( 246 ) for checking whether an inputted packet is a normal packet transmitted after being processed in the second packet processing apparatus or a detour packet transmitted without being processed, and directing the packets into corresponding paths; a queue ( 254 ) for storing the detour packet transmitted from the packet selecting means; a packet scheduling means ( 247 ) for reading the detour packet stored in the queue and transmitting the detour packet to a packet processing means ( 255 ) in the rear end of the second packet processing apparatus; the packet processing means ( 255 ) for processing the detour packet transmitted from the packet scheduling means; and a detour packet scrambler means ( 267 ) for rotationally checking a buffer for each of the corresponding paths and outputting the detour packet as the normal packet; wherein the packet scheduling means generates a queue lock release packet based on field information of the detour packet and transmits the queue lock release packet to the first packet processing apparatus which transmits the detour packet.