Patent ID: 7186588

Claim:
A method of packaging integrated circuits in lead-frame based micro-array packages, the method comprising: applying B-stageable adhesive to a back surface of a semiconductor wafer; partially curing the B-stageable adhesive; dicing the semiconductor wafer to form individual semiconductor dice each having a partially-cured B-stageable adhesive layer thereon; affixing a plurality of the dice to a micro-array lead-frame panel, the micro-array lead-frame panel having an array of device areas thereon, each device area including a plurality of leads, each lead including an elongated lead trace portion and a lead contact post, wherein the lead trace portions of at least some of the leads have segments extending between lead contact posts associated with adjacent leads, and wherein each die is affixed to its associated device area of the micro-array lead-frame panel by heating the B-stageable adhesive layer to adhere the die to at least selected portions of the leads of the micro-array lead-frame panel; wirebonding bond pads on the die to leads on the micro-array lead-frame using bonding wires to electrically couple the die to the micro-array lead-frame; encapsulating the dice, the bonding wires and portions of the micro-array lead-frame, wherein after encapsulation, the lead contact posts are exposed at a bottom surface of the micro-array lead-frame panel and the lead trace portions are not exposed at the bottom surface of the micro-array lead-frame panel; attaching solder contacts to the contact posts; and sawing the micro-array lead-frame panel to singulate the device areas thereby forming a plurality of lead-frame based micro-array packages.