Patent ID: 8879328

Claim:
A memory, comprising: a plurality of load lines arranged from a first load line to a last load line; a plurality of pairs of sense amplifiers corresponding to the plurality of load lines such that each pair of sense amplifiers is configured to share the corresponding load line, wherein each pair of sense amplifiers comprises a first sense amplifier and a second sense amplifier, and wherein the first sense amplifiers are configured to sense for words of a first type and the second sense amplifiers are configured to sense for words of a second type; a redundant sense amplifier configured to drive a redundant read line; a plurality of multiplexers corresponding to the plurality of load lines, wherein a first multiplexer through a next-to-last multiplexer in the plurality of multiplexers are each configured to select between the corresponding load line and a subsequent load line, and wherein a last multiplexer in the plurality of multiplexers is configured to select between the last load line and the redundant read line; and a decoder configured to control the multiplexers to select for their corresponding load lines when a defect corresponds to one of the first sense amplifiers and a word of the second type is being read from the second sense amplifiers, the decoder being further configured to control the multiplexers to select for their corresponding load lines when a defect corresponds to one of the second sense amplifiers and a word of the first type is being read from the first sense amplifiers.