Patent ID: 7723222

Claim:
A method comprising: forming a pair of stacked gates spaced apart over a cell region of a semiconductor substrate; forming a pair of first spacers over the cell region in direct contact with at least one side of the stacked gates; forming a pair of gate electrodes spaced apart over a logic region of the semiconductor substrate; forming a pair of second spacers over the logic region in direct contact with at least one side of the gate electrodes; coating a first photoresist layer over the cell area between the first spacers and a second photoresist layer over the logic area between the second spacers, wherein the first photoresist layer and the second photoresist layer are formed to a predetermined initial thickness which is smaller than the thickness of the first spacers but sufficient to cover at least a portion of the second spacers; hardening the first photoresist layer and the second photoresist layer; and then reducing the initial thickness of the second photoresist layer using an etching process to a final thickness sufficient to protect the second spacers, wherein the thickness of the first spacer is reduced during the etching process, and wherein an upper portion of the first photoresist layer is etched during the etching process.