Patent ID: 8374017

Claim:
A semiconductor storage device comprising: a plurality of arrays of memory cells, each memory cell including a ferroelectric capacitor and a transistor, the plurality of memory cell arrays comprising: word lines operative to select memory cells in the array, plate lines operative to apply drive voltage to the ferroelectric capacitors in the array, and a pair of bit lines operative to read data from the ferroelectric capacitors in the array; a selection transistor operative to selectively connect a memory cell block to one bit line of the pair of bit lines; a dummy capacitor operative to provide a reference voltage to another bit line of the pair of bit lines, the reference voltage having a value between signals that may be read from the memory cell; a sense amplifier circuit to compare and amplify potentials between the bit lines of the pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays, the reference potential correction capacitor shifting the reference potential by changing the amount of accumulated electric charges according to the correction signal.