Patent ID: 7398380

Claim:
A system including: a plurality of compute elements included in a physically-partitionable symmetric multiprocessor, each of the compute elements being a symmetric multiprocessor and having a respective boot resource; boot circuitry enabled to: direct a portion of the compute elements to initialize coherency link interfaces included therein to isolate all of the compute elements of the portion from each other, disable all but one of the boot resources and enable the one boot resource, and direct all of the compute elements of the portion to fetch instructions; wherein the compute element having the enabled boot resource programs routing tables associated with the coherency link interfaces to enable shared-memory coherency transactions between the compute elements of the portion; wherein the compute elements having the disabled boot resources access instructions from the enabled boot resource via the enabled shared-memory coherency transactions in response to the directing to fetch instructions; and wherein the compute elements are capable of communicating inter-process data via a switch fabric.