Patent ID: 7890733

Claim:
A data processor comprising a multi-threaded controller, an array of a plurality of processing elements, memory means local to each of said plurality of processing elements, a data packet-switched network interconnecting said array of processing elements and said memory means, whereby to enable any of said processing elements to access the memory means, and means to indicate to the controller, in dependence on the activity of said network, that a thread switch may take place, wherein said means to indicate to the controller comprises a shared load store unit common to the processing elements and adapted to indicate to the controller when activity on the network has ceased; wherein the data processor further comprises accounting means to keep account of the number of transactions leaving from, and returning to, the network; wherein the accounting means comprises an end node in said packet-switched network, said end node adapted to keep account of the number of said transactions leaving from, and returning to, the network via said end node; and wherein said shared load store unit is responsive to an indication from said end node that all transactions leaving from, and returning to, the network have completed to signal to the controller that activity on the network has ceased.