Patent ID: 8176220

Claim:
A system comprising a plurality of nodes coupled using a network of processor buses, wherein the plurality of nodes comprises: a first processor node comprising one or more processing cores and main memory; and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses, the flash memory node comprising: a flash memory comprising a plurality of flash pages; a first memory comprising: a cache partition for storing cached flash pages for the plurality of flash pages in the flash memory; and a control partition for storing cache control data and contexts of requests to access the plurality of flash pages; and a logic module comprising a direct memory access (DMA) register and configured to: receive a first request from the first processor node via the first processor bus to access the plurality of flash pages, wherein the first request is received using the DMA register that is mapped into an address space of the first processor node, store one or more parameters of the first request as a first context of the contexts stored in the control partition of the first memory, schedule a DMA operation responsive to the first request, and perform the DMA operation based on the first context, wherein the DMA operation transfers data between the flash memory and the first processor node and comprises accessing the cache partition in the first memory when a portion of the plurality of flash pages is cached in the cache partition according to the cache control data.