Patent ID: 7698511

Claim:
An interface for memories having different write times comprising in combination: a latch that stores data and address information for a memory access of a processor to a first memory device; control logic that determines whether the data is to be stored in a second memory device, wherein the second memory device is a hardened latch that includes a logic circuit and a storage element, wherein an amount of energy that can be stored in the storage element is greater than an amount of energy that can be removed by an event upset, and wherein if the control logic determines that the data is to be stored in the second memory device then the control logic identifies an address in the second memory device in which to store the data, and if the control logic does not determine that the data is to be stored in the second memory device then the control logic does not identify an address in the second memory device in which to store the data and the data is discarded; enable logic configured to control the writing of the data to the second memory device, wherein the enable logic enables the data to be written into the address of the second memory device as identified by the control logic; and wherein the latch includes one or more stage devices that temporarily store the data before the data is written to the second memory device to compensate for the difference in write times between the first and second memory devices, and wherein the time required to write the data to the second memory device is greater than the time required to write the data to the first memory device.