Patent ID: 8416636

Claim:
A method for controlling a semiconductor memory device comprising: applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns, wherein applying the plurality of voltage potentials to the plurality of memory cells comprises: applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor; applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor; and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell is located between the first memory cell and the second memory cell in the row of the array; and wherein the at least one third memory cell comprises: a first region coupled to a respective source line of the array; a second region coupled to the at least one third respective bit line of the array; a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region.