Patent ID: 8762675

Claim:
A sub-system comprising: a plurality of memory devices comprising a first memory device, wherein a timing for a data burst from each of the plurality of memory devices is provided by a respective, different, data strobe (DQS) signal; an interface circuit comprising: a plurality of memory data signal interfaces comprising a first memory data signal interface, a number of the plurality of memory data signal interfaces being equal to a number of the plurality of memory devices, each memory data signal interface including a respective data (DQ) path and a respective data strobe (DQS) path coupled to a corresponding memory device of the plurality of memory devices, wherein the first memory data signal interface is coupled to the first memory device; a system control signal interface coupled to a memory controller, the system control signal interface configured to receive a first read command from the memory controller; emulation and command translation logic configured to: select the first memory data signal interface based on the first read command; receive a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a DQS signal of the first memory device; delay the first data burst to align a phase difference between the DQS signal of the first memory device and a clock signal of the interface circuit; and transmit the delayed first data burst to the memory controller; and initialization and configuration logic configured to: select the first memory data signal interface; issue a calibration read command, via the first memory data signal interface, to read test data stored at the first memory device; receive the test data from the first memory device across the first memory data signal interface; determine the phase difference between the DQS signal of the first memory device and the clock signal based on a timing of the received test data; and set a delay within the first memory data signal interface corresponding to the first memory device.