Patent ID: 7632724

Claim:
A method of fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide dielectric layer including a flowable dielectric material, the method comprising: a) forming a sacrificial stressed layer overlying a first portion of an active semiconductor region, the stressed layer not overlying a second portion of the active semiconductor region having a common boundary with the first portion; b) forming trenches extending through the stressed layer into the SOI layer, the walls of the trenches defining peripheral edges of the active semiconductor region; c) heating the SOI substrate with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion, the first stress being one of tensile or compressive, the second stress being one of tensile or compressive other than the first stress; d) depositing a dielectric material in the trenches to form isolation regions contacting the peripheral edges of the stressed active semiconductor region, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer; e) removing the stressed layer to expose the first and second portions of the active semiconductor region; and f) forming a field effect transistor (“FET”) to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.