Patent ID: 7750685

Claim:
A circuit comprising: a digital sequence generating circuit (DSGC) adapted to: receive a first signal having a first frequency; count each cycle of the first signal to generate an ongoing DSGC count; and provide a DSGC count signal based on the ongoing DSGC count; a DSGC count to binary count converter adapted to: convert the ongoing DSGC count to a binary count based on the DSGC count signal; and provide a first binary count signal based on the binary count; a first register adapted to: receive the first binary count signal and a first reference signal having a first reference frequency; and provide a second binary count signal based on clocking in the first binary count signal using the first reference signal; and first summing and difference circuitry adapted to receive the first binary count signal and the second binary count signal, and provide a measured frequency signal based on a difference between the first binary count signal and the second binary count signal, wherein the measured frequency signal is indicative of the first frequency relative to the first reference frequency.