Patent ID: 7502728

Claim:
A computer-implemented method of providing code coverage testing for use in emulation of a logic circuit design having a plurality of logic gates, the logic design represented as a plurality of modules in a source code design file, the method comprising: instrumenting a selected module of the source design file with coverage probes by instantiating a probe for each gate output; generating a hierarchical name list comprising a hierarchical name for each instantiated probe; generating a history template file from the hierarchical name list; compiling/synthesizing the instrumented source file into an instrumented gate-level netlist; generating two scripts using the list of hierarchical names from the history template file, wherein the two scripts comprise a reset trigger script and a probe value extraction script; loading the instrumented gate-level netlist onto a hardware emulator; initializing an emulation run and executing the reset trigger script to reset all branch and statement probes; driving the fully initialized design in emulation by a simulated testbench; running the generated extraction script to retrieve the probe values from the testbench emulation, wherein the retrieved probe values are used in code coverage testing; generating a temporary file to hold the retrieved probe values; populating the temporary file with the retrieved probe values; merging the history template file with the retrieved probe values from the temporary file to produce a first history file; finding unexercised logic using the instrumented gate-level netlist and generating a second history file; merging the first history file with the second history file to produce code coverage results; and producing a code coverage tool report using the code coverage results.