Patent ID: 7385836

Claim:
A ferroelectric random access memory comprising: a reference bit line connected to a sense amplifier circuit and supplying a reference potential to the sense amplifier circuit; a reference potential generating circuit which includes a transistor and a paraelectric capacitor, the transistor having one terminal and an other terminal, the one terminal connected to the reference bit line, and the paraelectric capacitor connected between the other terminal of the transistor and a dummy plate line, and generates the reference potential; a drive circuit which is connected to the dummy plate line, and drives the dummy plate line to a first voltage higher than an operating voltage of the sense amplifier circuit when the reference voltage generating circuit generates the reference potential; a step-down circuit which steps down an external power supply voltage to generate a plurality of internal voltages; and a step-up circuit which receives and steps up at least one of the internal voltages generated in the step-down circuit, wherein the drive circuit receives a step-up voltage stepped up by the step-up circuit as the first voltage.