Patent ID: 7541277

Claim:
Method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process including RIE, the method comprising: depositing a first insulating material on a substrate having a plurality of logic elements formed thereon; performing a first RIE process using CF 4 and O 2 with a concentration between 2-5% H 2 O to achieve a humidity in the O 2 using at least one of a bubbler and an atomizer to cause a roughening of a surface of the first insulating material and to create openings having a thickness between 5-30 nanometers in the first insulating material; forming the dielectric cap layer by depositing a silicon nitride (Si x N y ) cap layer to a thickness of between 100-250 Angstroms on the first insulating material; performing a second RIE process using CF 4 and O 2 with a concentration between 2-5% H 2 O to achieve a humidity in the O 2 using at least one of a bubbler and an atomizer to cause a roughening of a surface of the Si x N y cap layer and to create openings having a thickness between 5-30 nanometers in the Si x N y cap layer; evacuating a sacrificial material between the conductors of the interconnect layer; and depositing a second insulating material to seal the Si x N y cap layer, wherein a subsequent air-bridge is formed below the second insulating material while not filling the air-gap.