Patent ID: 7286572

Claim:
A serializer comprising: a serdes framer interface (SFI) circuit for recovering a first set of data channels and a reference channel and for realigning said first set of data channels relative to a reference channel to create a second set of data channels, a clock multiplier unit (CMU) coupled to said SFI circuit, said CMU for receiving a clock frequency, for translating said clock frequency to a higher clock frequency, and for providing a clock signal to said SFI circuit, a multiplexing circuit coupled to said CMU, said multiplexing circuit for receiving said second set of data channels and for merging said second set of data channels into one data channel, an output driver stage coupled to said multiplexing circuit, said output driver stage for translating said one data channel into an output data channel, a reference selection circuit coupled to said CMU, said reference selection circuit for selecting a reference clock, for filtering said reference clock, and for providing to said CMU one of said selected reference clock or a filtered reference clock, wherein a data rate of said one data channel is higher than a data rate of said second set of data channels.