Patent ID: 7289346

Claim:
A semiconductor device comprising: a plurality of first word lines extending in a first direction; a plurality of second word lines extending in the first direction; a plurality of data lines extending in a second direction which is across the first direction; a plurality of memory cells each including a data line contact; a plurality of first word line drivers coupled to the plurality of first word lines; a plurality of second word line drivers coupled to the plurality of second word lines; a plurality of first word line select lines extending in the second direction and each coupled to a corresponding one of the plurality of first word line drivers; a plurality of second word line select lines extending in the second direction and each coupled to a corresponding one of the plurality of second word line drivers; a third word line select line coupled to the plurality of first and second word line drivers; a first voltage line extending in the second direction and coupled to the plurality of first word line drivers; a second voltage line extending in the second direction and coupled to the plurality of second word line drivers; wherein the plurality of data lines is located between the plurality of first word line drivers and the plurality of second word line drivers, wherein the data line contact of each of the plurality of memory cells is located between a corresponding one of the plurality of first word lines and a corresponding one of the plurality of second word lines; and wherein one of the plurality of first and second word line drivers is selected according to a combination with a signal on the third word line select line and signals on the plurality of first and second word line select lines.