Patent ID: 8766368

Claim:
A semiconductor device comprising: a semiconductor substrate having a cell region and a peripheral region; a first conductive line and a second conductive line extending onto the semiconductor substrate of the peripheral region to constitute a peripheral circuit; a first interlayer insulation layer on the first and second conductive lines and on the semiconductor substrate; a first peripheral interconnection pattern on the first interlayer insulation layer of the peripheral region; a first contact plug disposed in the first interlayer insulation layer of the peripheral region to electrically connect the first conductive line to the first peripheral interconnection pattern; a second interlayer insulation layer on the first interlayer insulation layer and on the first peripheral interconnection pattern; second peripheral interconnection patterns on the second interlayer insulation layer of the peripheral region; a second contact plug disposed in the second interlayer insulation layer to electrically connect the first peripheral interconnection pattern to one of the second peripheral interconnection patterns; and a third contact plug penetrating the first and second interlayer insulation layers to electrically connect the second conductive line to another one of the second peripheral interconnection patterns.