Patent ID: 8362541

Claim:
A manufacturing method for DRAM, comprising: providing a substrate; forming a deep trench in the substrate; forming a deep trench capacitor in the deep trench, wherein the deep trench capacitor comprises a bottom electrode, an upper electrode and a capacitor dielectric layer; forming a buried strap in the substrate on one side of the upper electrode; forming an isolation structure on the upper electrode; removing a portion of the substrate adjacent to the isolation structure to form a trench, wherein the trench and the deep trench do not overlap along a depth direction of the trench; forming a first doped region on a bottom of the trench to electrically connect to the buried strap; forming a dielectric layer on the bottom of the trench; forming a second doped region on sidewalls of the trench to electrically connect to the first doped region; forming a gate structure on the substrate, wherein the gate structure fills the trench; and forming a third doped region in the substrate to electrically connect to the second doped region, wherein the bottom of the trench is above a surface of the upper electrode of the deep trench capacitor.