Patent ID: 8315122

Claim:
A multi-chip package (MCP) semiconductor memory device receiving first and second chip enable (CE) signals and comprising: a first memory chip comprising a first CE port configured to receive the first CE signal, a second CE port configured to receive the second CE signal, and an active termination unit associated with a data input/output (I/O) bus, wherein the first memory chip is activated/deactivated in response to the first CE signal and configured to provide data to the data input/output (I/O) bus via the active termination unit; and a second memory chip comprising a CE port configured to receive the second CE signal, wherein the second memory chip is activated/deactivated in response to the second CE signal and configured to provide data to the data input/output (I/O) bus, wherein the active termination unit in the first memory chip is turned ON only when both of the first and second memory chips are deactivated, as indicated by the first and second CE signals received at the first and second CE ports of the first memory chip, respectively.