Patent ID: 8589856

Claim:
An integrated circuit design tool apparatus for determining a minimum dimensional value for a dimension of a semiconductor device and in respect of a performance parameter, the apparatus comprising: a processing resource arranged to support a circuit simulator capable of communicating with a circuit simulator interrogator, and a well distance calculator; wherein the circuit simulator interrogator is arranged to communicate a first dimensional value to the circuit simulator and the circuit simulator is arranged to communicate a first performance parameter value to the circuit simulator interrogator in response to the first dimensional value, and the circuit simulator interrogator also being arranged to communicate a second dimensional value to the circuit simulator and the circuit simulator also being arranged to communicate a second performance parameter value to the circuit simulator interrogator in response to the second dimensional value; the well distance calculator is arranged to determine a performance parameter limit value, and to project substantially linearly a deviation factor value for the dimension in respect of the performance parameter limit value using the first performance parameter value, the second performance parameter value, the performance parameter limit value, and a trial deviation value for the dimension; and the well distance calculator is also arranged to solve a deviation factor characterisation equation for the dimension using the deviation factor value projected in order to obtain the minimum dimensional value associated with the performance parameter limit value.