Patent ID: 7130366

Claim:
An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a first equalized signal; equalization and processing circuitry, coupled to said input terminal, that selectively equalizes and processes said input data signal to provide a first processed signal; signal combining circuitry, coupled to said first adaptive equalization circuitry, that receives and selectively combines a second processed signal and said first equalized signal to provide a resultant signal; and output processing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal and said second processed signal, and includes first signal slicing circuitry, coupled between said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and slices said resultant signal to provide a first sliced signal as said output data signal, and nonlinear processing circuitry, coupled between said output terminal and said signal combining circuitry, that nonlinearly processes at least a portion of said first sliced signal to provide said second processed signal.