Patent ID: 7460388

Claim:
A semiconductor memory device comprising: a plurality of memory cells arranged in the form of a matrix; first and second global bit lines corresponding to different columns of said plurality of memory cells; a sense amplifier for differentially amplifying a voltage between said first and second global bit lines; a first local bit line connected to memory cells, out of said plurality of memory cells, belonging to said column corresponding to said first global bit line; a second local bit line connected to memory cells, out of said plurality of memory cells, belonging to said column corresponding to said second global bit line and belonging to the same rows as said memory cells connected to said first local bit line; a third local bit line connected to memory cells, out of said plurality of memory cells, belonging to said column corresponding to said first global bit line and not connected to said first local bit line; a fourth local bit line connected to memory cells, out of said plurality of memory cells, belonging to said column corresponding to said second global bit line and belonging to the same rows as said memory cells connected to said third local bit line; a first hierarchical switch for mutually connecting said first global bit line and said first local bit line; a second hierarchical switch for mutually connecting said second global bit line and said second local bit line; a third hierarchical switch for mutually connecting said first global bit line and said third local bit line; a fourth hierarchical switch for mutually connecting said second global bit line and said fourth local bit line; a first precharge circuit connected between a precharge power source and said first global bit line for precharging said first global bit line; and a second precharge circuit connected between said precharge power source and said second global bit line for precharging said second global bit line, wherein when a memory cell connected to said first local bit line is read, said third hierarchical switch enters an off state from an on state, and said first precharge circuit terminates a precharge operation thereof after said third hierarchical switch enters the off state and before a selected word line connected to said memory cell to be read is activated.