Patent ID: 8664987

Claim:
A delay locked loop comprising: a first delay unit configured to delay an input clock and generate an output clock; a second delay unit configured to delay the output clock and generate a feedback clock; a phase comparison unit configured to compare a phase of the input clock to a phase of the feedback clock; a filter unit configured to filter a comparison result of the phase comparison unit with a frequence which is determined by a lock signal and generate a filtered signal; a lock signal generation unit configured to generate the lock signal in response to the filtered signal; and a delay value control unit configured to control a delay value of the first delay unit in response to the filtered signal and the lock signal, wherein the filter unit configured to filter the comparison result of the phase comparison unit with a first frequence when the lock signal is deactivated, and filter the comparison result of the phase comparison unit with a second frequence which is lower than the first frequence when the lock signal is activated.