Patent ID: 7340583

Claim:
A method of controlling a memory device, for appropriating the memory device to a first address space and a second address space in an address space which is managed by a central processing unit, comprising the steps of: generating, when an address signal of the first address space is provided from the central processing unit, a first address signal to access the memory device from a head address in ascending order based upon the address signal to supply the first address signal to the memory device; generating, when an address signal of the second address space is provided from the central processing unit, a second address signal to access the memory device from a final address in descending order based upon the address signal to supply the second address signal to memory device; generating, when the address signal of the second address space is provided from the central processing unit, a third address signal to access the memory device from the head address in ascending order based upon the address signal; and inverting the third address signal to generate the second address signal.