Patent ID: 7420554

Claim:
A display comprising: a gate line; a drain line arranged to intersect with said gate line; and a pixel including a p-type first field-effect transistor provided with a gate connected to said gate line as well as a source and a drain, either one of which is connected to said drain line, and subjected to application of a first bias voltage in the period of an operation of holding a pixel potential and a pixel electrode connected to the other one of said source and said drain of said p-type first field-effect transistor, the display applying a second bias voltage larger than said first bias voltage to said p-type first field-effect transistor of said pixel in a prescribed period other than the period of said operation of holding said pixel potential, and setting the potentials of said gate line and said drain line to prescribed potential levels respectively so that the potential difference between said gate line and said drain line reaches said second gate-to-source voltage while controlling the potential of said pixel electrode so that the potential difference between said drain line and said pixel electrode reaches said second drain-to-source voltage when applying said second bias voltage, wherein said first bias voltage includes a first gate-to-source voltage and a first drain-to-source voltage, and said second bias voltage includes a second gate-to-source voltage larger than said first gate-to-source voltage and a second drain-to-source voltage larger than said first drain-to-source voltage.