Patent ID: 7700952

Claim:
A thin film transistor substrate, comprising: a substrate having a display region and a non-display region; a plurality of gate lines formed in one direction on the substrate; a plurality of data lines intersecting the plurality of gate lines while being insulated therefrom; a plurality of single pixels formed at intersections of the plurality of gate and data lines; and a contact pad formed in the non-display region of the substrate, wherein the contact pad comprises a first electrode pattern formed in a lattice shape and including a plurality of open portions inside so that the substrate is exposed at the open portions, an insulation layer formed on the first electrode pattern, a plurality of contact vias formed in the insulation layer to be spaced apart from one another and exposing a portion of the first electrode pattern, and a second electrode pattern formed on the insulation layer and including a plurality of single electrode patterns; and wherein the plurality of single electrode patterns are spaced apart from one another and each of the single electrode patterns is electrically connected to the first electrode pattern though a corresponding contact via, wherein a conductive contact is positioned above at least a portion of the second electrode pattern.