Patent ID: 8049555

Claim:
An electronic device including a switch comprising: a sampling capacitor having a first terminal and a second terminal connected to ground; a cascade of a plurality of transistors from a first transistor to a last transistor, each transistor having a first terminal of a source/drain channel receiving an input voltage, a second terminal of said source/drain channel, a backgate terminal and a control gate receiving a sampling clock signal, a first transistor of said cascade having said second terminal of said source/drain channel coupled to said first terminal of said sampling capacitor, each subsequent transistor of the cascade excluding said first transistor having said second terminal of said source/drain channel connected to said backgate terminal of a previous transistor in said cascade and said last transistor of said cascade having said backgate connected to a supply voltage level; and a first backgate bias transistor having a first terminal of a source/drain channel receiving said input voltage, a second terminal of said source/drain channel connected to said backgate terminal of said last transistor of said cascade and a control gate receiving said sampling clock signal; and a second backgate bias transistor having a first terminal of a source/drain channel connected to said backgate terminal of said last transistor of said cascade, a second terminal of said source/drain channel receiving said supply voltage level and a control gate receiving an inverse of said sampling clock signal.