Patent ID: 8432927

Claim:
A switch comprising: input buffers internal to a switch fabric, the input buffers configured to: receive, from external input buffers that are external to the switch fabric, fixed-size data packets at a first data rate, and output the fixed-size data packets at a second data rate, the second data rate at least twice the first data rate; output buffers internal to the switch fabric, the output buffers configured to: receive the fixed-size data packets at the said second data rate, and output, to an external output buffer external to the switch fabric, the fixed-size data packets at the first data rate; a bufferless, non-blocking interconnecting network configured to transfer the fixed-size data packets from the input buffers to the output buffers; a scheduling controller configured to: schedule a transfer of fixed-size data packets from the external input buffers to the input buffers, determine a maximal matching of input buffers to output buffers for all the fixed-size data packets that are currently queued at the input buffers, schedule a transfer, based on the determination, of the fixed-size data packets in the input buffers to the output buffers through the bufferless, non-blocking interconnecting network, the transfer identifying a matched head of line of the fixed-size data packets, and schedule the transfer of fixed-size data packets from the switch fabric to the external output buffer; and wherein the input buffers, output buffers, and bufferless, non-blocking interconnecting network emulate a buffered crossbar.