Patent ID: 7941716

Claim:
A device comprising: an interface logic, an output latching logic and an input latching logic that is coupled between the interface logic and the output latching logic, the interface logic is configured to selectively provide data or scan data to the input latching logic; a control logic comprising: an input; an output coupled to an input of the input latching logic; the control logic configured to: in a functional mode of operation, delay a clock signal received at the input by a first delay to provide a first delayed clock signal at the output; and in a scan mode of operation, introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and a start point of a second scan mode activation period of the output latching logic by delaying the clock signal received at the input by a second delay to provide a second delayed clock signal at the output; and wherein the control logic is configured to control multiple input latching logics and multiple output latching logics.