Patent ID: 7937537

Claim:
A memory switching data processing system comprising: one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules, wherein the flexibly configured memory bus switch further comprises two dual in-line memory module (‘DIMM’) cards: a first DIMM card comprising an edge connector configured to adapt the first CPU only to the first bank of memory modules; and a second DIMM card comprising an edge connector configured to adapt the first CPU to both the first bank of memory modules and also to the second bank of memory modules.