Patent ID: 6998306

Claim:
A method of forming a semiconductor memory device, comprising: forming a plurality of trench regions two-dimensionally arranged at a predetermined region of a semiconductor substrate along a row direction and a column direction, to define a mesh-shaped active region, and simultaneously sequentially stacking a gate insulating layer, a storage node layer and a multiple tunnel junction layer on the mesh-shaped active region, the multiple tunnel junction layer including semiconductor layers and tunnel insulating layers that are alternately and repeatedly stacked, and the semiconductor layer formed of a material having a faster etch rate or thermal oxidizing rate than the storage node layer; forming a plurality of island-shaped isolation patterns to fill the trench regions; forming an interconnection layer on an entire surface of the resultant structure where the isolation patterns are formed; continuously patterning the interconnection layer, the multiple tunnel junction layer, the storage node layer and the gate insulating layer to form a plurality of data lines parallel to the column direction and simultaneously sequentially stacking a gate insulating pattern, a storage node pattern and a multiple tunnel junction pattern in regions between the isolation layers under the data lines, wherein a width of the multiple tunnel junction pattern is narrower than widths of the storage node pattern and the data line in a cross-sectional view taken along the row direction; forming a conformal gate interlayer dielectric layer on an entire surface of the resultant structure having the storage node pattern; and forming a plurality of parallel word lines for crossing over the data lines on the gate interlayer dielectric layer.