Patent ID: 7122468

Claim:
A method of fabricating an integrated circuit comprising: forming a first insulating layer on a substrate; forming a first hole passing through the first insulating layer and including a floor adjacent the substrate and a sidewall, and forming a third hole passing through the first insulating layer; conformally forming a first conductive contact on the sidewall and floor to define a groove in the first hole, and simultaneously forming a third conductive contact in the third hole; forming a second insulating layer on the first insulating layer remote from the substrate; forming a second hole passing through the second insulating layer and exposing the groove; forming a third insulating layer on the second insulating layer remote from the first insulating layer that includes therein a sixth hole that exposes the second hole; forming a second conductive contact in the second hole, in the groove and in the sixth hole; forming a fifth hole in the second insulating layer; forming a fourth hole in the first insulating layer beneath the fifth hole; forming a fourth conductive contact in the fourth and fifth holes; and forming a capacitor on the second insulating layer that is electrically connected to the fourth conductive contact.