Patent ID: 8575980

Claim:
A PLL circuit, PLL standing for phase locked loop, comprising: a number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of said oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value from a digital value of one period of an output clock of said oscillation circuit, a digital value of one period of periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has, and a value obtained by counting the number of first reference clocks from starting points of periods of the periodicity which the fractional portion of the number of accumulated clocks of said oscillator circuit has; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.