Patent ID: 8762806

Claim:
A decoding circuit comprising a data buffer, comprising a plurality of storage elements for storing data symbols; a processing circuit comprising a plurality of inputs and a plurality of outputs, wherein the processing circuit is configured to process data symbols received via the plurality of inputs and output the processed data symbols via the plurality of outputs; wherein each storage element of the plurality of storage elements is coupled to an associated input of the plurality of inputs, wherein the association of the plurality of storage elements with the plurality of inputs is determined by a first decoding parameter; wherein each storage element of the plurality of storage elements is coupled to an associated output of the plurality of outputs, wherein the association of the plurality of storage elements with the plurality of outputs is determined by a second decoding parameter; wherein the first decoding parameter and the second decoding parameter are determined by a decoding rule and wherein the first decoding parameter and the second decoding parameter are not changed throughout the decoding process; and wherein the first decoding parameter and the second decoding parameter each specify a shift of a block of data symbols with respect to the plurality of inputs and the plurality of outputs.