Patent ID: 8243221

Claim:
An array substrate comprising: a pixel that is provided on the array substrate, the pixel comprising: a scanning line; a signal line which intersects the scanning line; a thin film transistor that is connected to the scanning line and the signal line in a region surrounded by the signal line and the scanning line; a pixel electrode which is connected to the thin film transistor; and a sub-capacitance line that forms a sub-capacitance, wherein a display region, where a plurality of the pixels is disposed in a matrix-like shape, has a non-quadrangle shape, wherein a frame region on the outside of a display region comprises: a scanning lead-out line connected to the scanning line; a signal lead-out line connected to the signal line; and a common lead-out line which connects the sub-capacitance line in common to a side of a frame region where the scanning lead-out line is disposed, wherein the frame region comprises an intersection region of the scanning lead-out line and the signal lead-out line, wherein the common lead-out line is disposed in a region nearer to the end of the substrate than the region of the scanning lead-out line and the region of the signal lead-out line, whereas the common lead-out line is not disposed in the intersection region, wherein a connection line which connects the sub-capacitance line and the common lead-out line via an insulating film is made of a layer different from a layer of the scanning lead-out line.