Patent ID: 7746119

Claim:
A sample and hold integrated circuit, comprising: a first switch having a first conductive terminal coupled to a buffer for receiving a buffered input signal and a second conductive terminal coupled to a first storage capacitor for sampling the buffered input signal, wherein the first switch is closed to produce a sampled input signal by sampling the buffered input signal and opened to decouple the first capacitor from the buffered input signal such that the sampled signal is held by the first capacitor, and wherein a first leakage current flows between the first and second conductive terminals of the first switch and to accumulate a first leakage charge in the first capacitor; a second switch having a first conductive terminal coupled to a voltage reference and a second conductive terminal coupled to a second storage capacitor for storing a second leakage current, wherein the second leakage current flows between the first and second conductive terminals of the second switch and to accumulate a second leakage charge in the second capacitor; and an offset circuit for producing a compensated sampled value by subtracting a quantity from a signal developed in response to the held sampled signal, wherein the quantity is developed in response to the accumulated leakage charge in the second capacitor.