Patent ID: 6934216

Claim:
A semiconductor memory device having a plurality of operation modes, comprising: a memory cell array constituted of memory cells from which and to which data is readable and writable; a command signal generating circuit configured to generate a command signal based on a plurality of kinds of control signals inputted from an external part; a timing detecting circuit configured to output a first timing signal indicating a timing at which a combination of a plurality of commands is detected, based on the command signal generated by said command signal generating circuit; a first mode designation data processing circuit configured to retain mode designation data for designating the operation mode in response to the first timing signal outputted by said timing detecting circuit, and output the retained mode designation data; a second mode designation data processing circuit configured to retain the mode designation data outputted by said first mode designation data processing circuit, at a second timing after the commands in the combination of the plural commands are completed, and output the retained mode designation data; and a data controlling circuit configured to control data read from said memory cell array and data write to said memory cell array according to the operation mode and the command signal.