Patent ID: 7688106

Claim:
High speed serial transceiver circuitry comprising: input buffer circuitry including adaptive equalization capability; data recovery circuitry for recovering data information from an output signal of the input buffer circuitry; output driver circuitry; and loop-back circuitry for selectively applying the output signal of the input buffer circuitry to the output driver circuitry, wherein the loop-back circuitry comprises: loop-back driver circuitry for adding power to and thereby strengthening the output signal of the input buffer circuitry for application to the output driver circuitry, wherein the loop-back driver circuitry is turned on when the loop-back circuitry is in use for applying the output signal of the input buffer circuitry to the output driver circuitry, and is turned off to save power when the loop-back circuitry is not in use for applying the output signal of the input buffer circuitry to the output driver circuitry.