Patent ID: 7326951

Claim:
A chalcogenide random access memory, comprising: a substrate; a first dielectric layer disposed on a surface of the substrate; a bottom electrode disposed within the first dielectric layer; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has at least one opening exposing the bottom electrode; a modified chalcogenide spacer disposed on the sidewall of the opening exposing portion of the bottom electrode, wherein the modified chalcogenide spacer exposes portion of the bottom electrode; a top electrode disposed on the bottom electrode; and a un-modified chalcogenide thin film disposed between the modified chalcogenide spacer and the top electrode and disposed between the bottom electrode and the top electrode and contacting with the bottom electrode, wherein the modified chalcogenide spacer has a better etching resistivity than the un-modified chalcogenide thin film.