Patent ID: 8871603

Claim:
A method of manufacturing an electronic device, the method comprising: depositing a first conductive layer; depositing a first intermetal dielectric layer on top of the first conductive layer; depositing a resistive layer and structuring the resistive layer for a thin film resistor; depositing a second intermetal dielectric layer on top of the resistive layer; etching a first VIA opening into the second intermetal dielectric and the first intermetal dielectric layer down to the first conductive layer; etching a second opening into the second intermetal dielectric and the first intermetal dielectric layer down to the first conductive layer, wherein a horizontal cross-sectional plane of the second opening partially overlaps the resistive layer of the thin film resistor in a first dimension and wherein the first VIA opening does not overlap the resistive layer, depositing a conductive material in the second opening so as to electrically couple the resistive layer of the thin film resistor and the first conductive layer, depositing a second conductive layer on top of the second dielectric layer, and electrically connecting the second conductive layer with the conductive material in the second opening.