Patent ID: 7508026

Claim:
A non-volatile semiconductor memory device comprising: an isolation region formed in a semiconductor substrate, and composed of plural trenches and an isolation insulating film formed in the trench, wherein an upper surface of the isolation region is higher than the surface of the semiconductor substrate and a side surface of the upper surface of the isolation region is perpendicular to the surface of the semiconductor substrate; a gate insulating film formed on the semiconductor substrate between the isolation regions; a first gate electrode formed on the gate insulating film; an intergate insulating film formed on the first gate electrode; and a second gate electrode formed on the intergate insulating film, the first gate electrode including: a first part positioned between the isolation insulating films; a second part positioned on the first part and having a partial portion positioned on the isolation region; and a third part positioned on a central portion of the second part, wherein a width of the third part is set narrower than that of the second part and a central portion of the third part is positioned on a central portion of the second part.