Patent ID: 7563639

Claim:
A method of manufacturing a semiconductor memory device, the method comprising: forming an insulating layer on a substrate including a logic region on which a first pad is provided and a cell region on which a second pad is provided to cover the first pad and the second pad, wherein the insulating layer includes a hole defined therein over the second pad and a lower electrode within the hole; etching the insulating layer to form a first insulating layer pattern, the first insulating layer pattern comprising a first opening defined therethrough to expose the first pad; forming a first plug in the first opening; etching the first insulating layer pattern having the first plug formed in the first opening to form a second insulating layer pattern comprising a second opening defined therethrough to expose the lower electrode; forming a second plug in the second opening, the second plug comprising a phase-changeable material; and forming a conductive wire and an upper electrode on the first plug and the second plug, respectively, wherein forming the second plug in the second opening comprises filling the second opening with the phase-changeable material so that a surface of the phase-changeable material is substantially coplanar with a surface of the first plug.