Patent ID: 7652498

Claim:
An integrated circuit (IC) comprising a delay select input selection circuit, said delay select input selection circuit comprising: a) a first input selection circuit; b) a first storage element; c) a second storage element; d) a first input line branching into a plurality of input lines comprising at least a second, third, and fourth input line, wherein: i) said second input line is communicably connected to a first input of said first input selection circuit; ii) said third input line enters said first storage element; iii) said fourth input line enters said second storage element; iv) an output from said first storage element is communicably connected to a second input of said first input selection circuit; and v) an output from said second storage element is communicably connected to a third input of said first input selection circuit; and e) a fifth input line for communicably connecting a fourth input of said first input selection circuit to an output of a second input selection circuit of another delay select input selection circuit, wherein said fifth input line is not connected to a branch of said first input line.