Patent ID: 7864169

Claim:
A semiconductor device comprising: a first substrate; a second substrate opposite to the first substrate; a liquid crystal arranged between the first substrate and a second substrate; a plurality of gate lines formed over the first substrate; a plurality of source lines formed over the first substrate; a plurality of pixel thin film transistors formed over the first substrate, and formed in intersections of the plurality of gate lines and the plurality of source lines; a gate line driver circuit connected to the plurality of gate lines; a source line driver circuit connected to the plurality of source lines; and a designate circuit configured to designate one of address of the plurality of pixel thin film transistors, comprising: a counter circuit comprising a first thin film transistor over the first substrate; a memory device control circuit comprising a second thin film transistor over the first substrate, configured to generate a clock signal to control read and write to an external memory device; and a standard clock generator circuit, wherein an output of the standard clock generator circuit is connected to the counter circuit and the memory device control circuit.