Patent ID: 6965979

Claim:
A host caching system, comprising: a first host including a first volatile memory and a first nonvolatile memory, wherein the first volatile memory and the first nonvolatile memory is a first physically contiguous address space; a second host including a second volatile memory and a second nonvolatile memory, wherein the second volatile memory and the second nonvolatile memory is a second physically contiguous address space; an interconnect coupling the first host and the second host; and wherein first software under control of the first host maps: the addresses of the first volatile memory to the first host, the addresses of the first nonvolatile memory to the second host, wherein second software under control of the second host maps: the addresses of the second volatile memory to the second host, the addresses of the second nonvolatile memory to the first host, wherein in response to a write request received by the first host, the first host stores the write data in the first volatile memory, transmits the write data through the interconnect, stores the write data in the second nonvolatile memory, and acknowledges the write operation is complete.