Patent ID: 8836116

Claim:
A semiconductor device package, comprising: a first substrate electrically bonded to a second substrate, wherein the first substrate having a through silicon via extending from a first surface of the first substrate to a first-level metal structure of the first substrate, wherein the through silicon via is lined with an isolation layer and a conductive layer with a copper-barrier sub-layer and a copper-seed sub-layer, and the through silicon via is partially filled with a copper layer, wherein the copper layer is deposited on the conductive layer to form a continuous layer and a redistribution layer, the redistribution layer being over and extending laterally along the first surface of the first substrate beyond the through silicon via, and wherein the through silicon via is electrically connnected to the first-level metal structure through a gate structure and a plurality of contact plugs, and the through silicon via is electrically connected to a connection structure of the semiconductor device package that enables electrical contact between the semiconductor device package and an external connection structure.