Patent ID: 8828835

Claim:
A process of forming an integrated circuit, comprising the steps: forming a bipolar transistor, by a process further including the steps: providing a base layer, said base layer having a first conductivity type; forming an isolation layer on a top surface of said base layer; removing isolation material from said isolation layer in an area of an emitter opening, so that no isolation layer material is located above said base layer in said emitter opening area; removing impurities from said top surface of said base layer in said emitter opening area; forming an emitter dopant atom layer on said top surface of said base layer in said emitter opening area, said emitter dopant atom layer having between 0.5 and 5 monolayers of dopant atoms; forming an emitter layer comprising polysilicon on a top surface of said emitter dopant atom layer in said emitter opening area prior to annealing the emitter dopant atom layer; and performing an anneal process on said integrated circuit, such that dopant atoms in said emitter dopant atom layer diffuse into said base layer so as to form an emitter diffused region, said emitter diffused region extending from said top surface of said base layer in said emitter opening area to a depth between 10 and 40 nanometers, said emitter diffused region having a second conductivity type opposite from said first conductivity type and a peak doping density greater than 1·10 20 atoms/cm 3 .