Patent ID: 8841212

Claim:
A method comprising: patterning an opening in an insulator layer of a multi-level integrated circuit structure, exposing a conductor at a bottom of said opening; in a first processing chamber: lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer; forming a Tantalum layer on said first Tantalum Nitride layer; sputter etching said opening to expose said conductor at said bottom of said opening; forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer; moving said multi-level integrated circuit structure to a second processing chamber and forming a flash layer comprising a Platinum group metal alloy on said second Tantalum Nitride layer in said second chamber; moving said multi-level integrated circuit structure to a third processing chamber and depositing a copper seed layer on said flash layer in said opening until said flash layer is coated with copper in said third chamber; and filling said opening with copper using electroplating.