Patent ID: 8289078

Claim:
A semiconductor integrated circuit comprising: a differential amplifier circuit which detects a potential difference between a first input signal and a second input signal obtained by inverting a phase of the first input signal, and outputs an output signal depending upon a result of the detection; a first MOS transistor of a first conductivity type connected at a first end thereof to a power supply and diode-connected; a constant current circuit connected between a second end of the first MOS transistor and a ground, outputting a constant current when an enable signal is at a first level, and stopping the output of the constant current when the enable signal is at a second level which is different from the first level; a second MOS transistor of the first conductivity type connected at a first end thereof to the power supply, connected at a second end thereof to the differential amplifier circuit, and connected at a gate thereof to a gate of the first MOS transistor to supply a current obtained by conducting current mirroring on a current flowing through the first MOS transistor as an operation current of the differential amplifier circuit; a third MOS transistor of the first conductivity type connected at a first end thereof to the power supply, connected at a second end thereof to the second end of the first MOS transistor, and supplied at a gate thereof with the enable signal to turn off when the enable signal is at the first level and turn on when the enable signal is at the second level; a fourth MOS transistor of the first conductivity type connected at a first end thereof to the power supply and connected at a gate thereof to the second end of the first MOS transistor; a fifth MOS transistor of a second conductivity type connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with an inverted signal obtained by inverting a phase of the enable signal to turn on when the inverted signal is at the first level and turn off when the inverted signal is at the second level; an operation circuit supplied with a signal depending upon a first voltage at a node between the fourth MOS transistor and the fifth MOS transistor and the enable signal, outputting a first operation signal to output the output signal of the differential amplifier circuit to an output terminal when the enable signal is at the first level and the first voltage is at least a prescribed voltage, and outputting a second operation signal when the enable signal is at the second level or the first voltage is lower than the prescribed voltage; and an output buffer circuit supplied with the output signal of the differential amplifier circuit and a signal output by the operation circuit, outputting the output signal to the output terminal when the first operation signal is input, and outputting a signal fixed to a certain logic to the output terminal when the second operation signal is input.