Patent ID: 7458821

Claim:
A system comprising: a double data rate dual in-line memory module; and a connector holding the memory module, the connector comprising: a first row of connectors; a first row of a first plurality of interconnect ends adjacent to a first side of the first row of connectors; a second row of a second plurality of interconnect ends adjacent to a second side of the first row of connectors; a third row of a third plurality of interconnect ends adjacent to the second row of a second plurality of interconnect ends, a second row of connectors; a fourth row of a fourth plurality of interconnect ends adjacent to the third row of a third plurality of interconnect ends and adjacent to a first side of the second row of connectors; and a fifth row of a fifth plurality of interconnect ends adjacent to the fourth row of a fourth plurality of interconnect ends and adjacent to a second side of the second row of connectors, wherein a first interconnect end of the first plurality of interconnect ends is coupled to a first connector of the first row of connectors, wherein a first interconnect end of the second plurality of interconnect ends is coupled to a second connector of the first row of connectors, wherein a first interconnect end of the third plurality of interconnect ends is coupled to a third connector of the first row of connectors and is coupled to a third connector of the second row of connectors, wherein a first interconnect end of the fourth plurality of interconnect ends is coupled to a first connector of the second row of connectors, and wherein a first interconnect end of the fifth plurality of interconnect ends is coupled to a second connector of the second row of connectors.