Patent ID: 7397081

Claim:
A semiconductor structure, comprising: (a) a substrate including a top substrate surface, wherein the top substrate surface defines a first reference direction perpendicular to the top substrate surface and pointing from within the substrate to the top substrate surface; (b) a semiconductor region, a gate dielectric region, and a gate region each being on the top substrate surface, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, and, wherein the channel region and the gate dielectric region share an interface surface which is essentially perpendicular to the top substrate surface; and (c) a dielectric channel cap region on top of the semiconductor region, the gate dielectric region, and only a portion of the gate region, and wherein a first sidewall of the dielectric channel cap region is aligned with a second sidewall of the gate region.