Patent ID: 7415678

Claim:
A method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising: synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values i) appearing in the test responses of the circuit under test and ii) being compressed; and the compressor circuit being synthesized performing: mapping the plurality of scan chains into a plurality of groups of scan chains; mapping the plurality of scan chains into a plurality of modes, wherein in one of the plurality of compressor design strategies said plurality of modes has at least two mode types, including: primary modes associated with one group of scan chains of the plurality of groups of scan chains; shrinking modes associated with an intersection of two or more groups of scan chains of the plurality of groups of scan chains; in at least one mode of the plurality of modes, selectively compressing the test responses from the plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs of the compressor circuit, such that each of the scan chains is observable at more than one output of the plurality of outputs of the compressor circuit; during testing, generating a subset of test patterns to detect a set of faults in the circuit under test targeting fault detection in a set of more restrictive modes of the plurality of modes wherein no more than one group of scan chains is selected for compression in each of the more restrictive modes; identifying positions of unknown values in the test responses by simulating the subset of the test patterns; and selecting a mode of the plurality of modes to detect any single error in test responses in one shift cycle of the plurality of shift cycles targeting fault detection in a set of less restrictive modes of the plurality of modes wherein one or more groups of scan chains are selected for compression in each of the less restrictive modes.