Patent ID: 8288213

Claim:
A method of forming a memory array, comprising: forming a construction comprising vertically-stacked semiconductor material plates; the plates being vertically spaced from one another by gaps; patterning the plates to subdivide the plates into a plurality of planar pieces having sidewall edges; the planar pieces being vertically stacked; providing insulative material spacers in the gaps; forming electrically conductive tiers along the sidewall edges of the planar pieces; the electrically conductive tiers being vertically spaced from one another; etching through the semiconductor material of the planar pieces, and through the insulative material of the spacers, to form lines that extend orthogonally to the electrically conductive tiers; some of the lines being semiconductor material lines, and others of the lines being insulative material lines; forming gate dielectric along the semiconductor material lines; forming a gate material spaced from the semiconductor material lines by the gate dielectric; forming openings passing through the semiconductor material lines to break each semiconductor material line into a pair of segments; each segment passing through the gate material, having a first end joined to an electrically conductive tier, and having a second end in opposing relation to the first end; the segments being arranged as an array that comprises vertical columns and horizontal rows; the electrically conductive tiers extending along the rows of the array of segments; forming memory cell structures at the second ends of the segments; and forming a plurality of vertically-extending electrical interconnects connected to the segments through the memory cell structures; individual vertically-extending electrical interconnects being along individual columns of the array.