Patent ID: 8275975

Claim:
A sequencer controlled system for a system-on-chip (SoC) integrated circuit design, comprising: a plurality of hardware functional units; an embedded processor operatively coupled to said plurality of hardware functional units through a bus; and a sequencer having a set of registers, said registers being configured to control the start of at least one operation of said plurality of hardware functional units with stored instructions for each of said plurality of hardware functional units, said sequencer further having a plurality of resources associated with numeric values which represent status information, the status information consisting of available direct memory access (DMA) transfer channels and others selected from the group consisting of processes running on said SoC, available memory area for storage, and available processing power, wherein the numeric values of the plurality of resources are modified based on responses received from each of the plurality of hardware functional units, wherein said sequencer sends out trigger signals concurrently, to the plurality of said hardware functional units, based on a waiting pattern programmed in said registers as a direct response to being activated by said embedded processor, and keeps track of said resources based on the responses received from each of said plurality of hardware functional units, and all of the resources corresponding to said waiting pattern are available before said trigger signal is sent.