Patent ID: 7750334

Claim:
A memory device comprising: a semiconductor substrate; a plurality of cell arrays stacked above a rectangular cell layout region on the semiconductor substrate, each cell array including a plurality of memory cells, a plurality of bit lines each commonly connecting one end of the plurality of memory cells arranged in a first direction of the cell array and a word line commonly connecting the other end of the plurality of memory cells arranged in a second direction of the cell array, the rectangular cell layout region being defined in the first direction by first and second boundaries and being defined in the second direction by third and fourth boundaries; a read/write circuit formed on the semiconductor substrate and beneath the cell arrays, the main portion of the read/write circuit being disposed within the rectangular cell layout region; first and second vertical wirings disposed on both sides of each cell array in the first direction and arranged along the first and the second boundaries to connect the bit lines to the read/write circuit; and a third vertical wiring disposed on a side of each cell array in the second direction and arranged along one of the third or the fourth boundaries to connect the word line to the read/write circuit.