Patent ID: 6961674

Claim:
A system which analyzes cache array test data, comprising: test data corresponding to testing of at least one cache array residing on a semiconductor device; a processor configured to execute logic; and a memory with the logic configured to: analyze the test data for a current period of time for a first plurality of storage elements having a common function and residing in at least one first cache array; analyze the test data for a historical period of time for a second plurality of storage elements having the common function and residing in at least one second cache array; determine a plurality of attributes for each of the first storage elements and each of the second storage elements based upon the test data, the attributes comprising one of a good condition, a defective condition, a repairable condition and a repaired condition; determine a plurality of attribute statistics corresponding to the attributes of the first storage elements and the second storage elements; and generate an output report indicating at least two of the attributes of the first plurality of storage elements and the second plurality of storage elements, and the corresponding attribute statistics; wherein, in generating the output report, the attributes of the first plurality of storage elements are indicated with a bar and the attributes of the second plurality of storage elements are indicated with an indicia.