Patent ID: 8612815

Claim:
An integrated circuit structure comprising: a test pattern generator generating and outputting a test pattern request signal and a first test pattern; an asynchronous circuit receiving said test pattern request signal and said first test pattern and, after said receiving of said test pattern request signal and said first test pattern, outputting a test pattern acknowledge signal; and a single pulse generator receiving said test pattern acknowledge signal and, in response to said receiving of said test pattern acknowledge signal, generating a single pulse, said test pattern generator further receiving said single pulse and, in response to said receiving of said single pulse, said test pattern generator performing the following: switching said test pattern request signal from a first test pattern request signal value to a second test pattern request signal value to cause said asynchronous circuit to stop receiving said first test pattern; and generating a second test pattern, said first test pattern and said second test pattern being different test patterns generated to test for faults in said asynchronous circuit.