Patent ID: 7853758

Claim:
A storage controller, comprising: a first data structure for storing an address of a first of a plurality of logical partitions (LPARs) upon receipt of a first notice from the first LPAR that an initial program load (IPL) of the first LPAR has commenced; a second data structure for storing addresses of all LPARS to which a newly initiated pack change state interrupt is directed; a processor; and a memory for storing computer-readable code executable by the processor, the code comprising instructions for: comparing the address in the first data structure with the addresses in the second data structure; removing the address of the first LPAR from the second data structure if the second data structure includes the address of the first LPAR; transmitting the pack change state interrupt to only the addresses remaining in the second data structure; and removing the address of the first LPAR from the first data structure upon receipt of receiving a second notice from the first LPAR that the IPL of the first LPAR has completed.