Patent ID: 7422942

Claim:
A method of fabricating a semiconductor device, comprising the steps of: forming a gate electrode on a substrate; forming a diffusion region in said substrate adjacent to said gate electrode; forming a side wall oxide film on a side wall of said gate electrode; forming an interlayer insulation film on said substrate such that said interlayer insulation film covers said gate electrode and further said side wall oxide film; and forming a self-aligned opening in said interlayer insulation film such that said self-aligned opening exposes said diffusion region; said step of forming said self-aligned opening comprising the steps of: forming a first insulation film of an oxide such that said first insulation film covers said side wall oxide film and said diffusion region; depositing a second insulation film having a composition different from a composition of said first insulation film, on said first insulation film; forming said interlayer insulation film on said second insulation film; forming a contact hole in said interlayer insulation film in correspondence to said diffusion region by an etching process while using said second insulation film as an etching stopper; removing said second insulation film exposed at a bottom of said contact hole by an etching process while using said first insulation film as an etching stopper; and removing said first insulation film exposed at a bottom of said contact hole selectively with respect to said diffusion region; wherein said step of forming said first insulation film is conducted by a plasma CVD process, with a high-frequency power set smaller than a high-frequency power in which said first insulation film contains H 2 O with an amount of about 2.4 wt %; and wherein said high-power frequency is smaller than 200 W.