Patent ID: 7968908

Claim:
A semiconductor structure comprising a substrate and an interconnect structure located thereupon, said substrate including: a first p-n junction between an first-conductivity-type well and a signal-side second-conductivity-type well; a second p-n junction between said first-conductivity-type well and an electrical-ground-side second-conductivity-type well, wherein said signal-side second-conductivity-type well does not contact said electrical-ground-side second-conductivity-type well; a signal-side second-conductivity-type doped region contacting said signal-side second-conductivity-type well; a signal-side first-conductivity-type doped region contacting said signal-side second-conductivity-type well and not contacting said signal-side second-conductivity-type doped region; an electrical-ground-side second-conductivity-type doped region contacting said electrical-ground-side second-conductivity-type well; and an electrical-ground-side first-conductivity-type doped region contacting said electrical-ground-side second-conductivity-type well and not contacting said electrical-ground-side second-conductivity-type doped region, and wherein said interconnect structure includes a dielectric material layer embedding a first conductive wiring structure and a second conductive wiring structure, said first conductive wiring structure providing a first conductive electrical connection between said signal-side first-conductivity-type doped region and a signal node of an electrical circuit, and said second conductive wiring structure providing a second conductive electrical connection between said electrical-ground-side first-conductivity-type doped region and electrical ground.