Patent ID: 7260166

Claim:
A system for synchronizing a reset signal to a local clock, comprising: a local clock terminal; a reset terminal; a synchronized reset output terminal; and synchronizing circuitry coupled between the clock terminal, the reset terminal, and the synchronized reset output terminal, the synchronizing circuitry comprises, a first flip-flop including: a clock input coupled to the clock terminal, a reset input coupled to the reset terminal, and a data input coupled to a fixed bias of either pull up or pull down; and a second flip-flop including; a clock input coupled to the clock terminal, a reset input coupled to the reset terminal, a data input coupled to a data output of the first flip-flop, and a data output coupled to the synchronized reset output terminal; wherein the synchronizing circuitry synchronizes a received reset signal to the local clock and outputs a synchronized reset signal on the synchronized reset output terminal.