Patent ID: 8504767

Claim:
A RAID controlled semiconductor storage device (SSD), comprising: an SSD memory disk unit comprising a plurality of memory disks provided having a plurality of semiconductor memories; a RAID controller coupled to the SSD memory disk unit; and a controller unit coupled to the RAID controller configured to adjust a synchronization of a data signal communicated between a host interface unit and the SSD memory disk unit to control a communication speed between the host interface unit and the SSD memory disk unit, wherein the controller unit comprises: a memory control module for controlling data input/output of the SSD memory disk unit; a DMA control module which controls the memory control module to store data in the SSD memory disk unit or reads data from the SSD memory disk unit to provide the data to the host according to an instruction from the host received through the host interface unit; a buffer which buffers data according to control of the DMA control module; a synchronization control module which, when receiving a data signal corresponding to the data read from the SSD memory disk unit by the control of the DMA control module through the DMA control module and the memory control module, adjusts synchronization of a data signal so as to have a communication speed corresponding to a PCI-Express communications protocol to transmit the synchronized data signal to the PCI-Express host interface unit and, when receiving a data signal from the host through the PCI-Express host interface unit, adjusts synchronization of the data signal so as to have a transmission speed corresponding to a communications protocol used by the SSD memory disk unit to transmit the synchronized data signal to the SSD memory disk unit through the DMA control module and the memory control module; and a high-speed interface module which processes the data transmitted/received between the synchronization control module and the DMA control module at high speed, including a buffer having a double buffer structure and a buffer having a circular queue structure, and processes the data transmitted/received between the synchronization control module and the DMA control without loss of high speed by buffering the data transmitted/received between the synchronization control module and the DMA control module using the buffers and adjusting data clocks.