Patent ID: 8513068

Claim:
A method for forming a nanowire field effect transistor (FET) device, the method comprising: forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a semiconductor substrate; patterning a first hardmask layer over the second SOI portion; forming, from the first SOI portion, a first suspended nanowire over the semiconductor substrate; forming a first gate structure around a portion of the first suspended nanowire wherein forming the first gate structure comprises forming a first polysilicon layer in a first series of undercut regions beneath the first SOI pad region, the second SOI pad region and the third SOI pad region; patterning a second hardmask layer over the first gate structure and the first suspended nanowire; removing the first hardmask layer; forming, from the second SOI portion, a second suspended nanowire over the semiconductor substrate; forming a second gate structure around a portion of the second suspended nanowire, wherein forming the second gate structure comprises forming a second polysilicon layer in a second undercut region beneath the second SOI pad region; and removing the second hardmask layer.