Patent ID: 6987698

Claim:
A semiconductor memory comprising: a plurality of memory regions having a plurality of memory cells positioned in a row direction and a column direction, a plurality of bit lines connected to said memory cells aligned in the column direction, respectively, and a plurality of sense amplifiers connected to said bit lines, respectively, which amplifies data on said bit lines; a plurality of word lines each wired commonly to all of said memory regions, and each directly connected to memory cells aligned in the row direction in the memory regions; a word decoder connected to said word lines, and selecting one of said word lines to connect all memory cells that are in the memory regions and that are aligned in the row direction, to said bit lines; and a plurality of dummy regions each being formed between every two of said memory regions, said dummy regions each having a dummy bit line that is set to a predetermined voltage at least during operation of said memory cell array, wherein all of said sense amplifiers of all of said plurality of memory regions operate in synchronism with the selection of one of said word lines by said word decoder, in order to amplify data on all bit lines of all said memory regions and corresponding to the selected word lines, one of said memory regions is selected during a single write or read operation, and said data is input/output from/to all bit lines in the selected memory region.