Patent ID: 7149126

Claim:
A method of erasing a MONOS memory cell, wherein said MONOS memory cell comprises: a word gate on the surface of a semiconductor substrate; sidewall control gates on sidewalls of said word gate, separated from said word gates by an insulating layer; nitride regions within an ONO layer underlying said sidewall control gates wherein electron memory storage is performed within said nitride regions; a polysilicon word line overlying and connecting said word gate with word gates in other said memory cells and overlying said sidewall control gates, separated from said sidewall control gates by an insulating layer; and bit line diffusions within said semiconductor substrate adjacent to each of said sidewall control gates; wherein said method of erasing a block of said nitride regions comprises the steps of: providing a first voltage to said bit line diffusions; and providing a second voltage opposite to said first voltage to said control gate over said bit line diffusions.