Patent ID: 8706791

Claim:
An apparatus for finite impulse response (FIR) filtering comprising: a processor having a program control unit to receive instructions from a program memory unit and a chain of two or more multiply-accumulators, each comprising a multiplier and an adder, wherein the multiply-accumulators are arranged such that an output result of a first multiply-accumulator of the chain is delivered as an input to an adder of a second subsequent multiply-accumulator of the chain and an output result of a last multiply-accumulator of the chain is delivered as an input to an adder of the first multiply-accumulator of the chain, wherein the multiply-accumulators are configured to receive in each cycle of the FIR filtering coefficients of the FIR filter and data input, and wherein the chain is configured to maintain, for a number of cycles that equals the number of multiply-accumulators, coefficients with respective indices for the multiply-accumulators, and if the number of coefficients of the FIR filter is greater than the number of multiply-accumulators, to replace the coefficients with new coefficients having new indices that equal the respective indices plus the number of multiply-accumulators.