Patent ID: 7624239

Claim:
A method of operating a non-volatile memory system comprising a controller circuit and a non-volatile flash memory circuit, where the non-volatile memory circuit is formed of a plurality of erase blocks each having one or more sectors, each sector comprising a plurality of individually programmable non-volatile memory cells and including a portion for user data portion and a portion for header data, the method comprising: managing the memory circuit by the controller by organizing the erase blocks into composite logical groups formed of multiple erase blocks according to a control data structure maintained by the controller; receiving an erase command specifying one or more sectors of the memory circuit for erase; and in response to the erase command, executing an operation comprising: determining which of the specified sectors form complete logical groups according to the control data structure and which of the specified sectors do not form complete logical groups according to the control data structure; performing a physical erase operation on those of The specified sectors determined to form complete logical groups; and performing a write operation to logically mark as erased, without performing a physical erase operation on, those of the specified sectors determined not to form complete logical groups.