Patent ID: 7565658

Claim:
A method for job start preparation in an instruction-parallel processor system having an instruction-parallel processor, said method comprising the steps of: executing, in parallel with the execution of instructions of a current job by the instruction-parallel processor, read instructions for job start preparation for at least one next job arranged in a queue of jobs to be executed, wherein the executing step includes: determining whether part of a register file of the instruction-parallel processor is no longer being utilized by the instructions of the current job; and responsive to determining that part of the register file is no longer being utilized by the instructions of the current job: reading job information related to the next job from a memory; and storing the job information in the part of the register file of the instruction-parallel processor that is no longer being utilized by the instructions of the current job; fetching, integrated with the execution of instructions of the current job, instructions related to the next job based on instruction address information in said job information; and decoding and preparing, integrated with the execution of instructions of the current job, the fetched instructions for execution; wherein the executing step is performed prior to completion of the current job, thereby hiding within the current job, a read latency associated with the next job.