Patent ID: 7749886

Claim:
A method of making a microelectronic assembly comprising: providing a microelectronic element having a first surface and contacts accessible at the first surface; providing compliant dielectric bumps over the first surface of said microelectronic element; depositing a sacrificial layer over said compliant dielectric bumps and the first surface of said microelectronic element, wherein said sacrificial layer covers said compliant dielectric bumps; grinding said sacrificial layer and said compliant dielectric bumps so as to planarize top surfaces of said compliant dielectric bumps, wherein the planarized top surfaces of said compliant dielectric bumps are exposed; after the grinding step, removing at least portions of said sacrificial layer to expose at least some of said contacts; and forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant dielectric bumps.