Patent ID: 7065054

Claim:
An apparatus for automatically activating a clock master circuit in a stack of repeaters comprising: a first repeater including a power state output pin, the power state output pin being configured to be connected to ground when the first repeater is powered on; a second repeater comprising: a first on pin having a first on pin logical state, the first on pin logical state being indicative of whether or not the second repeater is configured in the stack of repeaters so that no other repeater occupying a position in the repeater stack that is before the position of the second repeater is powered on; a voltage source connected to the first pin, the voltage being present when the second repeater is powered on and not present when the second repeater is powered off; and a clock master circuit that is enabled when the first on pin logical state indicates that no other repeater occupying a position in the repeater stack that is before the position of the second repeater is powered on; and a connector connecting the first on pin from the second repeater to the power state output pin of the first repeater; whereby the clock master circuit in the second repeater is enabled based on whether the first repeater is powered on.