Patent ID: 8462540

Claim:
A static random access memory (SRAM) cell, consisting of: a first inverter, including a first input node and a first output node; a second inverter, including a second input node and a second output node, and the second input node being coupled to the first output node, and the second output node being coupled to the first input node; a first transistor, coupled to a write word line, a write bit line and the first output node; a second transistor, coupled to a complementary write bit line, the write word line and the second output node; and a third transistor, coupled to a read bit line and a read word line and to the first input node or the second input node; wherein the third transistor has a feature of asymmetric threshold voltage having two different threshold voltages, so as to expand a read bit line swing; wherein the read bit line swing is expanded through a boosted read bit line; wherein the first inverter includes a fourth transistor and a fifth transistor, the fourth transistor is coupled to the fifth transistor through the first output node, and the first input node is coupled to a gate electrode of the fourth transistor and a gate electrode of the fifth transistor; and wherein the second inverter includes a sixth transistor and a seventh transistor, the sixth transistor is coupled to the seventh transistor through the second output node, and the second input node is coupled to a gate electrode of the sixth transistor and a gate electrode of the seventh transistor.