Patent ID: 8745446

Claim:
An integrated circuit, comprising: a bus; a processing unit configured to execute a user program; and a debugging circuit coupled to the bus, the debugging circuit comprising a command register, wherein, when the processing unit executes a command including a break factor in the user program, the processing unit halts the execution of the user program and makes a command transfer request to the debugging circuit, the debugging circuit makes a split response for freeing a use right of the bus from the processing unit, the processing unit frees the use right of the bus and enters a wait state, the debugging circuit prepares a debugging command in the command register and transfers the debugging command to the processing unit via the bus, and the processing unit restarts the execution of the halted user program after executing the debugging command, wherein the debugging circuit is settable in one of a first operation mode in which the split response is made and a second operation mode in which the split response is not made, in an initial state, a command for branching to a specific address is stored in the command register of the debugging circuit, and when the debugging circuit is set in the second operation mode, the debugging circuit immediately transfers the command for branching to the specific address to the processing unit in response to the command transfer request, wherein after the processing unit executes the command for branching to the specific address and a command that begins from the specific address, and issues a subsequent command transfer request to the debugging circuit, the debugging circuit makes the split response even when the debugging circuit is set in the second operation mode.