Patent ID: 7948461

Claim:
An image display device comprising: a plurality of pixel circuits arranged in a matrix form over a substrate and each including at least one static memory; a plurality of data lines to convey an image signal to the plurality of pixel circuits; a plurality of gate lines, intersecting the data lines, to convey a scanning pulse to the plurality of pixel circuits; and a scanning circuit to sequentially supply the scanning pulse to the plurality of gate lines, wherein the at least one static memory includes a first inverter and a second inverter, each said inverter being comprised of an n-channel transistor and a p-channel transistor, an input portion of the first inverter being connected to an output portion of the second inverter, and an input portion of the second inverter being connected to an output portion of the first inverter, wherein each of the pixel circuits includes: a first transistor to set a storing state of the static memory and a second transistor to reset a storing state of the static memory, a drain electrode of the first transistor is connected to the input portion of the first inverter, a drain electrode of the second transistor is connected to the input portion of the second inverter, a source electrode of the first transistor is connected to a corresponding one of the data lines, a gate electrode of the first transistor of a pixel circuit in a row of pixel circuits arranged parallel to the gate lines is connected to one gate line of the plurality of the gate lines, and a gate electrode of the second transistor of a pixel circuit in an adjacent row of pixel circuits is connected to the one gate line.