Patent ID: 8653829

Claim:
An auto-zero electronic circuit for eliminating an offset associated with a test electronic circuit having: a pair of input terminals coupled to a pair of input voltage signals, and a pair of output terminals, the auto-zero electronic circuit comprising: a first pair of source followers having: a first pair of input terminals coupled to the pair of output terminals of the test electronic circuit, and a first pair of output terminals; a pair of capacitors coupled to the first pair of input terminals for sampling the offset associated with the test electronic circuit; a differential pair having: a third pair of input terminals coupled to the first pair of output terminals and a third pair of output terminals; a pair of diode-connected transistors having: a fourth pair of input terminals coupled to the third pair of output terminals, and a fourth pair of output terminals configured to generate biasing voltage signals; and a pair of resistors coupled between the fourth pair of output terminals and a reference voltage; wherein the test electronic circuit includes a second pair of source followers having: a second pair of input terminals coupled to the pair of input terminals of the test electronic circuit for receiving the pair of input voltage signals, and a pair of control terminals configured to receive the biasing voltage signals eliminating the offset.