Patent ID: 8599626

Claim:
A memory device comprising: an array of memory cells, each memory cell being coupled to an associated pair of bit lines; read control circuitry configured during a read operation to activate a number of addressed memory cells in order to couple each addressed memory its associated pair of bit lines; sense amplifier circuit coupled to the bit lines and configured during the read operation to determine the data value stored in each addressed memory cell by evaluation of differential signals that develop on the associated pair of bit lines during the read operation in dependence on the data value stored in that addressed memory cell; the sense amplifier circuitry being configured in a speculative read mode of operation to evaluate the differential signals on the associated pair of bit lines for each addressed memory cell after a speculative read time period that is not guaranteed to be sufficient for the differential signals to have developed to a degree necessary for the sense amplifier circuitry to correctly determine the data value stored in each addressed memory cell; and error detection circuitry configured, in said speculative read mode of operation, to capture the differential a on the associated pair of bit lines for each addressed memory cell and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the degree necessary for the sense amplifier circuitry to correctly determine the data value stored in each addressed memory cell, and if so to assert an error signal, wherein said error detection circuitry comprises, for each pair of bit lines, comparison circuitry configured to independently compare with a reference value the value of the differential signals on the associated pair of bit lines for each addressed memory cell, in order to produce a pair of comparison outputs.