Patent ID: 7715392

Claim:
An apparatus for optimizing path compression of at least one single entry trie table in a data structure in a pipeline hardware assisted bitmapped multi-bit trie algorithmic network search engine wherein said data structure comprises at least one parent trie table entry for said at least one single entry trie table, said at least one parent trie table entry comprising a path compression pattern that represents common prefix bits of a data packet and a skip count that represents a length of said path compression pattern, said apparatus comprising: at least one PC logic unit coupled to at least one pipeline logic stage of said network search engine that is operable for detecting said path compression optimization; and wherein said at least one PC logic unit, in response to detecting said path compression optimization, is further operable for (1) suppressing a memory read operation to a memory bank associated with said at least one PC logic unit, wherein the suppression of the memory read operate prevents the transfer of memory data from the at least one PC logic unit and causes a shift in the data that represents the remainder of the compression pattern, and (2) updating a value of said skip count, and (3) sending an unprocessed portion of said path compression pattern and an updated value of said skip count to a next stage of said pipeline network search engine.