Patent ID: 8434052

Claim:
A method for determining differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit, comprising: providing a programmed processor system with one or more data files including first information representing an image of pins of the partitioned logic block in a first floorplan of an integrated circuit; providing a programmed processor system with one or more data files including second information representing an image of pins of the partitioned logic block in a second floorplan of the integrated circuit; the programmed processor system comparing the first information with the second information to determine differences between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan; and the programmed processor system processing one or more data files to substitute information representing the partitioned logic block in the second floorplan with information representing the partitioned logic block in the first floorplan if it is determined that no differences exist between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan.