Patent ID: 7263531

Claim:
A computer-implemented method for facilitating matching of blocks between a first control flow graph (CFG) representation of a portion of a first set of executable instructions and a second CFG representation of a portion of a second set of executable instructions, wherein the instructions are embodied on one or more computer-readable media, the method comprising: computing register flows for each block by analyzing a def-use chain and a use-def chain; for each block, assigning def-identifiers to definitions (“def”s) of each register; for each block, associating a use of a register in a block with the def identifier of all defs of that register that reach the use; matching blocks between the first and second CFG representations based upon the def-identifiers and use-identifiers, whereby facilitating matching of blocks between the first control flow graph (CFG) representation of the portion of the first set of executable instructions and the second CFG reoresentation of the portion of the second set of executable instructions.