Patent ID: 8216928

Claim:
A method of fabricating a semiconductor device including a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure, the method comprising: forming a first layer of dielectric material overlying the gate structure and the doped region; isotropically etching the first layer of dielectric material, wherein isotropically etching the first layer of dielectric material comprises concurrently etching a first portion of the first layer overlying the gate structure at a first etch rate and a second portion of the first layer overlying the doped region at a second etch rate, the first etch rate being greater than the second etch rate; forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer; and forming a conductive contact within the first layer and the second layer, the conductive contact being electrically connected to the doped region.