Patent ID: 6853601

Claim:
A memory system having at least one memory array for a semiconductor device, the memory system including: an enabling device for the memory system, the enabling device including at least two programmable elements selected from a group comprising a fuse and an anti-fuse; the at least one memory array comprising: a plurality of pairs of complementary digit lines; a plurality of word lines; a plurality of memory cells, each memory cell of the plurality of memory cells having a control terminal connected to one word line of the plurality of word lines and an access terminal connected to one digit line of a pair of complementary digit lines of the plurality of pairs of complementary digit lines, at least two memory cells of the plurality of memory cells connected to each digit line of a complementary pair of digit lines of the plurality of pairs of complementary digit lines, each memory cell of the plurality of memory cells having a row address; refresh counter circuitry and address buffer circuitry used to generate at least one row address for at least one memory cell of the plurality of memory cells, the refresh counter circuitry comprising CAS-Before-RAS refresh counter circuitry; row decoder circuitry connected to the plurality of word lines and the address buffer circuitry used to energize at least two word lines of the plurality of word lines in the at least one memory array in accordance with the at least one row address generated by the refresh counter circuitry and the address buffer circuitry; sense amplifier circuitry connected to the plurality of pairs of complementary digit lines used to access and refresh the plurality of memory cells coupled to each of the energized at least two word lines of the plurality of word lines; and energizing circuitry connected to the enabling device used to energize more than one word line of the plurality of word lines in the at least one memory array for the at least one row address generated by the refresh counter circuitry and the address buffer circuitry for a memory cell of the plurality of memory cells in response to the enabling device used with the memory system having the at least one memory array so that more than at least one memory cell of the plurality of memory cell accessible through the plurality of pairs of complementary digit lines may be accessed for the at least one row address generated by the refresh counter circuitry and the address buffer circuitry.