Patent ID: 8111767

Claim:
An adaptive sliding block Viterbi decoder (ASBVD), comprising: forward and backward Viterbi processors configured to generate metrics of states and of transitions between the states associated with an encoder, based on encoded input information symbols received via a communications channel, wherein each processor includes a plurality of buffers for storing information symbols so that a number of the encoded input information symbols can be concurrently decoded; a state estimator configured to estimate a current state of a code trellis based on the generated metrics, wherein the processors decode the stored information symbols based on the estimated current state; and a control unit configured to adapt the number of encoded input information symbols to be concurrently decoded based on a condition of the communications channel and to selectively control the operational state of the buffers such that buffers are enabled and disabled in accordance with the number of encoded input information symbols to be concurrently decoded, wherein each of the processors comprises: a first buffer unit including buffers for storing the encoded input information symbols; a first metric unit configured to generate the metrics of the transitions between the states based on the stored encoded input information symbols; a second metric unit configured to generate the metrics of the states based on the metrics of the transitions between the states; a second buffer unit including buffers for storing information symbols output from the second metric unit; a traceback unit configured to decode the stored information symbols output from the second metric unit based on the estimated current state and output a sequence of most likely transmitted information symbols; and a third buffer unit including buffers for storing the sequence of most likely transmitted information symbols to generate decoded output information bits.