Patent ID: 8325126

Claim:
A liquid crystal display device comprising: a gate driver for outputting a first gate driving signal and a second gate driving signal according to a first clock signal or a second clock signal, the gate driver comprising: a first output end for outputting the first gate driving signal; and a second output end for outputting the second gate driving signal; a control circuit configured to: provide a third clock signal and a fourth clock signal, wherein the third and fourth clock signals periodically switch polarities and have opposite polarities at the same time; and provide a charge sharing signal according to parasitic capacitances at the first and second output ends of the gate driver, the charge-sharing signal including: a first disable period corresponding to an output period of the first output end; and a second disable period corresponding to an output period of the second output end; wherein the parasitic capacitance at the second output end is larger than the parasitic capacitance at the first output end, and the first disable period is longer than the second disable period; and a charge-sharing circuit configured to: generate the first clock signal by performing charge-sharing on the third and fourth clock signals during the first disable period; and generate the second clock signal by performing charge-sharing on the third and fourth clock signals during the second disable period; wherein the first clock signal includes a signal falling edge which descends from a high voltage level to a first voltage level, and the second clock signal includes a signal falling edge which descends from the high voltage level to a second voltage level.