Patent ID: 7461198

Claim:
A method for configuration and management of flash memory, comprising the following steps: (a) defining a relationship among a flash memory, a virtual memory region, and a memory logical block region according to a logical block address of the write request to said flash memory; (b) defining a plurality of data access basic control units of said flash memory, including physical erase unit, segment, frame, and page, by configuring the structure of said flash memory of step (a) into said physical erase unit, said segment, said frame and said page; (c) defining a plurality of data access basic control units of the virtual memory region, including virtual erase unit and area, by configuring the structure of said virtual memory region of step (a) into said area and said virtual erase unit; (d) defining a plurality of data access basic control units of the memory logical block region, including cluster and logical block, by configuring the structure of said memory block region of step (a) into said cluster and said logical block; (e) constructing an erase unit table, a cluster table and a free segment table according to a relationship among the physical erase unit, segment, virtual erase unit, area, logical block and cluster, by using said physical erase unit, said segment of step (b), said area, said virtual erase unit of step (c), said cluster, said logical block of step (d) to construct said erase unit table, said cluster table and said free segment table; and (f) processing data access according to a relationship in said erase unit table, said cluster table, and said free segment table, by using said erase unit table, said cluster table and said free segment table of step (e) to map a read or write request to said logical block of said memory logical block region to a read or write operation to said frame of said flash memory.