Patent ID: 7616032

Claim:
An internal voltage initializing circuit for use in a semiconductor memory device, comprising: a high voltage initializing unit for selectively connecting a power supply voltage terminal to a high voltage terminal and generating a high voltage in response to a power-up signal; and a back bias voltage initializing unit for selectively connecting a ground terminal to a back bias voltage terminal and generating a back bias voltage in response to a signal produced by delaying the power-up signal by a predetermined delay time, wherein the back bias voltage initializing unit does not generate the back bias voltage until a level of the high voltage is raised to a target level and generates the back bias voltage after the level of the high voltage is raised to the target level by preventing a level of the back bias voltage from increasing until the level of the high voltage is raised to the target level, wherein the back bias voltage initializing unit includes: a delay unit for delaying the power-up signal by the predetermined delay time to prevent the level of the back bias voltage from increasing until the level of the high voltage is raised to the target level; a first buffer for buffering an output signal of the delay unit; an inverter receiving an output signal of the first buffer; and a first switch for selectively connecting the ground terminal to the back bias voltage terminal in response to an output signal of the inverter.