Patent ID: 7437689

Claim:
An Interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using interaction-based Arnoldi algorithms, comprising: a. placing parameters of passive components of the interconnect network into matrices, wherein the matrices contain resistances, capacitances, and inductances; b. building a state space-based system matrix for the original interconnect network; c. building a state space-based system matrix for a reduced interconnect network including generating an orthogonal projector by an iteration-based Krylov algorithm including: i. generating a Krylov subspace based upon the iteration-based Krylov algorithm; ii. modifying the Krylov subspace by applying a modified Gram-Schmidt orthogonal iteration process through application of an Arnoldi algorithm to generate a unit orthonormal basis; iii. creating a residual vector by iterative application of the Arnoldi algorithm; iv. comparing the residual vector with the interconnect network to determine a state of the reduced interconnect network by estimating residual error; v. outputting a resulting projection for the reduced interconnect network; and vii. using the output to deduce a lower-order system; and d. storing the state space-based system matrix for the reduced interconnect network in computer memory, wherein estimating the residual error comprises using: (a) the Arnoldi algorithm containing the iteration-based Krylov algorithm therein; (b) a perturbation system added into the interconnect network; and (c) the residual error defined as E r (s)=(I n −sA){tilde over (X)}(s)−r.