Patent ID: 8171332

Claim:
An integrated circuit with reduced electromagnetic interference induced by memory access, comprising: a random code generator for generating a plurality of random codes according to a predetermined delay parameter; a request receiver coupled to the random code generator for obtaining an input clock signal according to a plurality of data requests and spreading the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal; a memory unit for accessing image data to be displayed in response to the data requests and the output clock signal, wherein the frequency spectrum of the output clock signal is wider than that of the input clock signal, and wherein the request receiver comprises: a request sorter for providing a read flag or a write flag according to the data requests and sorting the data requests being routed to the memory unit, wherein the read flag is indicative of executing reading of the memory unit and the write flag is indicative of executing writing to the memory unit; a timing generator coupled to the request sorter for generating the input clock signal according to the data requests and the corresponding flag; and a delay generator coupled to the timing generator for generating a plurality of phase delays respectively corresponding to each random code and deriving the output clock signal applied to the memory unit by individually delaying each pulse of the input clock signal by each phase delay.