Patent ID: 8106409

Claim:
A thin film transistor array panel, comprising: a substrate; a plurality of semiconductor islands formed on the substrate, the plurality of semiconductor islands including a plurality of first extrinsic regions, a plurality of second extrinsic regions, and a plurality of intrinsic regions; a gate insulating layer covering the semiconductor islands; a plurality of gate lines formed on the gate insulating layer and including a plurality of gate electrodes overlapping the intrinsic regions; a plurality of data lines formed on the gate insulating layer and connected to the plurality of first extrinsic regions; and a plurality of pixel electrodes connected to the plurality of second extrinsic regions, wherein a plurality of protrusions are formed on the surfaces of semiconductor islands with the same material as the semiconductor islands, and a length of a semiconductor island divided by a distance between two protrusions of the plurality of protrusions is substantially equal to an integer, wherein the protrusions are spaced substantially at uniform intervals, and wherein a number of the protrusions formed on each semiconductor island is the same, and wherein the protrusions formed on each semiconductor island extend across the entire semiconductor island in a direction perpendicular to a length direction of the semiconductor islands.