Patent ID: 8392862

Claim:
An integrated chip (IC) comprising: a plurality of logic blocks, each of the plurality of logic blocks including a plurality of cells, each cell comprising a combination or a group of electrical components; and a plurality of power distribution structures, each of the plurality of power distribution structures surrounding each of the plurality of logic blocks and connecting to at least a cell of a corresponding logic block, each of the power distribution structures including: at least one enable cell connected to an enable rail transmitting a control signal, the enable rail spanning across at least three cells in each of the power distribution structures, each of the at least one enable cell comprising a combination or a group of a plurality of electrical components, at least two power gating cells comprising a first power gating cell and a second power gating cell, the first power gating cell comprising a first gating element for connecting a power rail to provide a supply voltage to at least one cell in the corresponding logic block according to the control signal received via the enable rail, the second gating cell comprising a second gating element for connecting the power rail to provide the supply voltage to the at least one cell, the first gating element and the second gating element having different voltage threshold characteristics or a different channel length, the first power gating cell and the second power gating cell available from a same cell library, and at least one filler cell comprising a gating element having a source terminal and a drain terminal not connected to the power rail but having a gate terminal connected to receive the control signal; wherein a number of the at least one enable cells, a number of the at least two power gating cells and a number of the at least one filler cell in each of the power distribution structures and voltage threshold characteristics or channel lengths of the at least two gating elements are selected to configure a current profile or voltage profile at a node in the corresponding logic block.