Patent ID: 8904260

Claim:
A memory system comprising: a first data source having N bits; a first parity generator connected to said first data source generating parity bits corresponding to said N bits; a second data source having 2N bits; a second parity generator connected to an upper half of bits of said second data source generating parity bits corresponding to N upper half bits; a third parity generator connected to a lower half of bits of said second data source generating parity bits corresponding to N lower half bits; a first multiplexer having a first input connected to said first parity generator receiving both said N bits and corresponding parity bits, a second input connected to said second parity generator receiving both said N upper half bits and corresponding parity bits and an output; a second multiplexer having a first input connected to said first parity generator receiving both said N bits and corresponding parity bits, a second input connected to said third parity generator receiving both said N lower half bits and corresponding parity bits and an output; a memory including a first memory bank having a write data input connected to said output of said first multiplexer, and a second memory bank having a write data input connected to said output of said second multiplexer; and wherein the memory system controls said first and second multiplexers to perform one of select said first input as output of said first multiplexer and select no input as output of said second multiplexer thereby storing said N bits and said corresponding parity bits of said first data source in said first memory bank, select no input as output of said first multiplexer and select said first input of said second multiplexer thereby storing said N bits of said first data source and said corresponding parity bits in said second memory bank, and select said second input of said first multiplexer and select said second input of said second multiplexer thereby storing said N upper half bits of said second data source and said corresponding parity bits in said first memory bank and storing said N lower half bits of said second data source and said corresponding parity bits in said second memory bank.