Patent ID: 7265413

Claim:
A semiconductor memory having a multiplicity of memory cells, each of the memory cells comprising: a semiconductor layer arranged on a substrate, a semiconductor surface of said semiconductor layer having at least one step between a deeper semiconductor region and a higher semiconductor region that is higher in a direction normal to the substrate; at least one conductively doped deeper contact region formed in the deeper semiconductor region, and a conductively doped higher contact region formed in the higher semiconductor region; at least one channel region extending in the semiconductor layer between the deeper contact region and the higher contact region; at least one electrically insulating trapping layer designed for trapping and emitting charge carriers, the trapping layer being arranged on a gate oxide layer adjoining the channel region; and at least one gate electrode for controlling the electrical conductivity of the channel region, the gate electrode adjoining, in a first region, a control oxide layer arranged on the trapping layer and, in a second region, the gate oxide layer arranged on the channel region.