Patent ID: 8611125

Claim:
A packaged integrated circuit device, comprising: a substrate including a conductive pad thereon; a chip stack including a plurality of chips on the substrate; a first primary conductive line directly electrically connecting the pad on the substrate to a conductive pad on a chip at a top of the plurality of chips in the chip stack; a second primary conductive line directly electrically connecting the conductive pad on the chip at the top of the plurality of chips to a conductive pad on one of the plurality of chips in the chip stack, wherein the one of the plurality of chips is not directly under the chip at the top of the plurality of chips; and secondary conductive lines directly contacting the conductive pad on the one of the plurality of chips having the second primary conductive line connected thereto and providing electrical connections to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack.