Patent ID: 8301867

Claim:
A multi-core processor system, comprising: a) a main processor, comprising: i) a processing unit configured to function as a host processor for main processor functions; ii) an offload engine operatively connected to said processing unit for routing data to and from said processing unit; iii) a plurality of main processor optical network units (ONU's) operatively connected to said offload engine; and, iv) a dual optical line terminal (OLT) operatively connected to said offload engine; b) an internal EPON bus operatively connected to said OLT; and, c) a plurality of secondary core processors, located physically separate from said main processor, each secondary core processor having a respective secondary core processor ONU being operatively connected to said main processor via said internal EPON bus, said internal EPON bus being the only connection point for the secondary core processors to the main processor, thus the internal EPON bus is configured as a separate EPON tree from an external EPON bus of the main processor.