Patent ID: 6988168

Claim:
A cache comprising: a memory including a plurality of entries, wherein each entry of the plurality of entries is configured to store a cache block; and a circuit having one or more first registers programmable to indicate a first subset of entries selectable for a first agent to store a first cache block corresponding to a first transaction initiated by the first agent and a second subset of entries selectable for a second agent to store a second cache block corresponding to a second transaction initiated by the second agent, the circuit also including one or more second registers programmable to indicate a third subset of the plurality of entries selectable to store local cache blocks and a fourth subset of the plurality of entries selectable to store remote cache blocks, and the circuit to combine indications of the first subset and the third subset to select the first entry for the first transaction if the first transaction is to a local cache block and to combine indications of the first subset and the fourth subset to select the first entry for the first transaction if the first transaction is to a remote cache block.