Patent ID: 8365012

Claim:
A method of handling a failure in a computer, the computer comprising: a memory that stores a BIOS and a device driver for controlling a PCI express device; a CPU that executes the BIOS and the device driver; and a root port connected to the CPU through a primary bus and to a PCI express path through a secondary bus, the root port functioning as a PCI express bridge; wherein: the PCI express path constitutes a PCI express tree having at least any one of the PCI express device and a PCI express switch; when detecting a failure on the PCI express path, the PCI express device or the PCI express switch transmits a signal indicating the failure to the root port; the root port transmits an SMI (System Maintenance Interrupt) to the CPU upon receipt of the signal indicating the failure; the CPU executes the BIOS, the BIOS being started in response to receipt of the SMI; the BIOS: collects a log of the PCI express path on which the failure has been detected, and analyzes the collected log to judge the type of the failure, and when the failure is judged to be a fatal failure on the PCI express path by the judgment, resets the PCI express tree downstream of the root port that received the signal indicating the failure, and when the failure is judged to be a non-fatal failure on the PCI express path by the judgment, resets the PCI express device in which the failure occurred; and the CPU disables the reset PCI express device by executing the device driver.