Patent ID: 7249268

Claim:
A method comprising: in a processing system with a processor having a plurality of processor cores in which all of the processor cores are operating at a first voltage and a first frequency and at least one of the processor cores is not idle but is executing a command that has caused a stall condition, performing performance optimization operations in response to the stall condition, the performance optimization operations comprising: placing the processor core that is executing the command that caused the stall condition into a lower power state; checking data concerning maximum values for clock frequency and power supply voltage to be provided to the processor, wherein the data concerning maximum values comprises a table with multiple entries, wherein each entry lists a predetermined voltage and corresponding predetermined frequency determined to be suitable when a specified number of processor cores is in the lower power state, and wherein the operation of checking the data comprises using the table to determine a suitable voltage and corresponding frequency, based on a current number of processor cores in the lower power state; and increasing frequency and voltage of at least one non-stalled processor core, based on the entry in the table for the current number of processor cores in the lower power state; after increasing frequency and voltage of at least one non-stalled processor core, responding to termination of the stall condition by performing operations comprising: decreasing frequency and voltage of at least one non-stalled processor core; and taking the processor core for which the stall condition has terminated out of the lower power state.