Patent ID: 7622946

Claim:
A design structure embodied in a machine readable medium used in a design process for a circuit for automatically matching impedance between a driver and a receiver, the design structure of said circuit comprising: a phase-locked loop (PLL) that includes a first input for receiving a data signal from the driver, said PLL comprising a first voltage controlled oscillator (VCO) for providing a first output frequency responsive to a first VCO control voltage generated by said PLL as a function of the data signal; and impedance matching circuitry for generating an impedance-matched signal, said impedance matching circuitry including: a second input for receiving the data signal from the driver; an output for providing said impedance-matched signal to the receiver; and a first variable-capacitance capacitor having a first capacitance controlled by said first VCO control voltage, said first variable-capacitance capacitor having an input for electrically communicating with the driver and an output for electrically communicating with the receiver.