Patent ID: 8891279

Claim:
A method, in a data processing system, for enhancing wiring structure for a cache supporting an auxiliary data output, the method comprising: splitting the data cache into a first data portion and a second data portion, wherein the first data portion provides a first set of data elements and the second data portion provides a second set of data elements; connecting a first data path to provide the first set of data elements to a primary output; connecting a second data path to provide the second set of data elements to the primary output; feeding the first data path back into the second data path and feeding the second data path back into the first data path; and connecting a secondary output to the second data path such that a first subset of the first set of data elements and a first subset of the second set of data elements are provided to the secondary output in a first configuration and a second subset of the first set of data elements and a second subset of the second set of data elements are provided to the secondary output in a second configuration.