Patent ID: 6976122

Claim:
A memory controller comprising: a threshold register configured to store a value indicating a length of time; a control unit coupled to the threshold register, wherein in response to receiving a first memory access request, the control unit is configured to generate signals configured to cause a memory device to open a page of memory, and wherein the control unit is configured to generate signals configured to cause the memory device to close the page if the page has been open for the length of time indicated by the value stored in the threshold register; wherein the control unit is configured to increase the value stored in the threshold register if a page miss for a most recently open page is detected in response to receiving a second memory access request and to decrease the value stored in the threshold register if a page conflict is detected in response to receiving the second memory access request; wherein the control unit is configured to inhibit modification of the value stored in the threshold register in response to a page hit.