Patent ID: 7577014

Claim:
A semiconductor memory device, comprising: a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a high cell power supply voltage and a low cell power supply voltage with a lower voltage potential than the high cell power supply voltage to the memory cell, wherein the memory cell power supply circuit supplies: a predetermined first power supply voltage supplied as the low cell power supply voltage in a case where the low cell power supply voltage is supplied in a data read cycle and in a case where data is not written to the memory cell to which the low cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage supplied as the low cell power supply voltage in a case where data is written to the memory cell to which the low cell power supply voltage is supplied in a write cycle, wherein: the first power supply voltage is output in response to a write disable control signal or a column non-select signal; and the second power supply voltage is output in response to a write enable control signal and a column select signal.