Patent ID: 7314814

Claim:
A method of fabricating a semiconductor device comprising: forming a first gate electrode on an active region of a semiconductor substrate; forming an etch protective layer on the first gate electrode; forming a first interlayer dielectric over the first gate electrode; forming an opening through the first interlayer dielectric and the etch protective layer, exposing a top surface of the first gate electrode; forming a second gate electrode on the first gate electrode by filling the opening with a conductive material, wherein the first and second gate electrodes together comprise a gate stack; forming a second interlayer dielectric over both the second gate electrode and the first interlayer dielectric; forming an opening through the second interlayer dielectric exposing a top portion of the second gate electrode; filling the opening to form a contact plug; and forming a metal interconnect over the second interlayer dielectric, wherein the metal interconnect is electrically connected to the second gate electrode by the contact plug.