Patent ID: 7064358

Claim:
A ESD protection device comprising: a) a n-doped region and a p-doped region in a p-well in a semiconductor structure; said n− doped region and said p-doped region are spaced; b) a n-well and a deep n-well surrounding said p-well on the sides and bottom; c) a first I/O pad connected to said n-doped region; d) a trigger circuit connected to said first I/O pad and said p-doped region; e) a second I/O pad connected to said n-well; f) a parasitic bipolar transistor is comprised of the n-doped region functioning as a collector terminal, the P− well functioning as a base terminal, and the deep p-well functioning as the emitter terminal; whereby under an ESD condition, the p-well is charged positive using the trigger circuit and said parasitic bipolar transistor can be turned on.