Patent ID: 8688428

Claim:
A performance evaluation device including a simulation unit evaluating a hardware including a processor, a data handling device and a BUS that connects the processor and the data handling device, the evaluating performed by a simulation using the simulation unit including a processor unit representing the processor, a BUS unit representing the BUS and a data handling device unit representing a data handling device comprising: a control timing model unit configured to control a first timing of inputting/outputting a first control signal between the processor unit and the data handling device unit, the first control signal being used for a request of a data handling process to the data handling device unit and an acknowledgment of the data handling process from the data handling device unit; a control signal transfer period calculation unit configured to calculate a transfer period of the first control signal between the processor unit and the data handling device unit, where a control signal transfer period is calculated from a time when a request of the data handling process is made to the data handling device to a time when the acknowledgment of the data handling process is made by the data handling device; a data timing model unit configured to control a second timing of inputting/outputting a second control signal between the processor unit and the data handling device unit, the second control signal being used for at least one of informing a data size to the data handling device unit and informing an end of the data handling process from the data handling device unit; and a data signal transfer period calculation unit configured to calculate a transfer period of the second control signal between the processor unit and the data handling device unit in accordance with the second timing, where a data signal transfer period is calculated from a time when the data handling device is informed of the data size to a time when the data handling process is ended.