Patent ID: 7443846

Claim:
Circuitry for implementing a multiplexer, the circuitry comprising: a first lookup table having four inputs and a single output, the first lookup table configured to: take as an input a first selection criterion signal and a second selection criterion signal, take as an input a first input signal and a second input signal, and output the first input signal, the second input signal, and a null signal when the first selection criterion signal is a first value and the second selection criterion is a second value, the first selection criterion signal is the second value and the second selection criterion is the first value, the first selection criterion is the second value and the second selection criterion is the second value, respectively; a second lookup table configured in a way as the first lookup table is configured; a logic gate, wherein the logic gate takes as input an output of the first lookup table and of the second lookup table; at least one additional logic gate; and at least one additional lookup table, wherein an output of each of the at least one additional lookup table is input to a distinct and respective one of the at least one additional logic gate and wherein each of the at least one additional logic gate takes as input an output of a preceding logic gate, an output of a last of the at least one additional logic gate being an output of the multiplexer.