Patent ID: 7349253

Claim:
A method for testing the operability of a memory device, a DRAM semiconductor memory device, comprising a control and a regular memory area comprising a number of regular memory cells, as well as a redundant memory area comprising a number of redundant memory cells, wherein the redundant memory cells serve to replace one or a plurality of defective memory cells from the regular memory area; the method comprising: coupling at least one regular memory cell from the regular memory area with at least one redundant memory cell from the redundant memory area via a coupling circuit; parallel loading of the regular memory area including the at least one regular memory cell along with the redundant memory area including the at least one redundant memory cell; parallel testing of the operability of the regular memory area including the at least one regular memory cell along with the redundant memory area including the at least one redundant memory cell; evaluation and case distinction on the basis of the result of the testing for operability; and deactivating of defective memory cells.