Patent ID: 8487671

Claim:
A semiconductor device comprising: a delay circuit that delays a first clock signal to generate a second clock signal; a detection-potential generation circuit that generates a detection potential corresponding to a difference between a timing of an active edge of the second clock signal and a target timing; a reference-potential generation circuit that generates a reference potential being a same potential to be obtained by the detection-potential generation circuit if a difference between a timing of an active edge of the second clock signal and the target timing is a predetermined value; and an active-edge adjusting circuit that changes an adjustment pitch of a delay amount of the delay circuit based on a relationship between the detection potential and the reference potential, the reference-potential generation circuit generates a plurality of reference potentials corresponding to a plurality of predetermined values, respectively, and the active-edge adjusting circuit changes the adjustment pitch of the delay amount of the delay circuit based on a relationship between each of the plurality of reference potentials and the detection potential.