Patent ID: 7187039

Claim:
A semiconductor integrated circuit device comprising: a first trench formed in a semiconductor substrate, said first trench surrounding active regions; a second trench formed in said semiconductor substrate, said second trench surrounding dummy regions not functioning as an element; element isolation insulating films filled in said first trench and said second trench; and dummy interconnections formed over said substrate and not functioning as an element, wherein said dummy regions are formed at a scribing area and are regularly arranged at said scribing area, wherein said dummy interconnections are formed at said scribing area and are regularly arranged over said regularly arranged dummy regions, wherein a plurality of said dummy interconnections are formed by the same level layer as a gate electrode of a MISFET, wherein at least one of said active regions serves as a part of said MISFET such that a source region and a drain region of said MISFET are formed in said at least one of said active regions, and wherein said dummy regions do not serve as a part of a MISFET.