Patent ID: 7716521

Claim:
An integrated circuit, comprising: a plurality of processor cores, wherein each of said processor cores is associated with a respective plurality of threads, and wherein each of said processor cores is configured to issue a first instruction from one of said respective plurality of threads during one execution cycle and to issue a second instruction from another one of said respective plurality of threads during a successive execution cycle; and an error processing unit coupled to said processor cores and configured to detect an error condition corresponding to a data element external to said plurality of processor cores, wherein for any given error condition corresponding to the data element, detection of the given error condition occurs independent from operation of said processor cores; wherein, in response to detecting said error condition, said error processing unit is further configured to convey an indication of said error condition to a selected one of said processor cores dependent upon an identifier of said selected processor core, wherein said indication includes an identifier of a selected thread executable on said selected processor core; and wherein said identifiers of said selected processor core and said selected thread are programmable such that: for each given detected error condition that is reportable, said error processing unit is configured to convey an indication of said given detected error condition to said selected processor core and said selected thread; and after identifiers of said selected processor core or said selected thread are programmed that differ from previously programmed identifiers, said error processing unit is configured to convey said indication of said given detected error condition to a different selected processor core or a different selected thread, wherein the different selected processor core is distinct from a previously selected processor core, and wherein the different selected thread is distinct from a previously selected thread, such that on different occasions, said error processing unit is configured to send a same indication of a same detected error condition to different ones of said processor cores or said threads, depending on how said identifiers of said selected processor core and said selected thread are programmed.