Patent ID: 8284368

Claim:
An array substrate, comprising: a plurality of gate lines; a plurality of data lines, intersecting with the gate lines to form a plurality of pixel regions; and a plurality of pixels, respectively disposed in each of the corresponding pixel regions; wherein the pixels comprise a plurality of buffering pixel units, a plurality of first pixel units, and a plurality of second pixel units, the quantity of pixels of each of the first pixel units is A, the quantity of pixels of each of the second pixel units is A, the quantity of pixels of each of the buffering pixel units is D, where A is a positive integer greater than or equal to 3, D is a positive integer smaller than A, each of the buffering pixel units is disposed between any two adjacent data lines and corresponding to an endpoint of each of the data line, the first pixel units and the second pixel units, which are disposed between any two adjacent data lines, follow each of the corresponding buffer pixel units along an extending direction of the data line, the first pixel units and the second pixel units disposed between any two adjacent data lines are arranged alternately, the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line of the two adjacent data lines.