Patent ID: 8560804

Claim:
An electronic storage device-enabled method of reducing erase cycles in an electronic storage device that uses erase-limited memory devices, including erase-limited memory devices that each include a plurality of blocks, the method comprising: creating a first flop that includes at least one flop section, including a first flop section and a second flop section; mapping a first address to said first flop; reading said flop sections from said first flop using a section selection sequence; storing data associated with said first address in said first flop by writing said data into said first flop section and storing a first value representing said first flop section location into a valid flop section location; if said data is changed, storing said changed data into said second flop section, storing and assigning said first flop section with an invalid status, storing said changed data in said second flop section, and assigning a valid status to said changed data; and limiting said data to have a data size that is no more than the flop section size of said at least one flop section.