Patent ID: 8122317

Claim:
A system for providing two-dimensional parity to facilitate error detection and correction in a memory array comprising: a first memory array having a first plurality of cells; and circuitry associated with the first memory array and adapted to: store values for bits of a plurality of super bundles in the first plurality of cells, each super bundle of the plurality of super bundles comprising a plurality of row bundles, wherein each row bundle of the plurality of row bundles comprises a row of bits and corresponding bits in each of the plurality of row bundles form a column of bits, and wherein bits for a first group of the plurality of super bundles are interleaved within a first section of the first plurality of cells in the first memory array in a manner where adjacent bits for one of the first group of the plurality of super bundles are separated by at least one bit from another of the first group of the plurality super bundles; for each row bundle, generate a row check bit value that represents a row parity value for the row of bits associated with the row bundle and store the row check bit value as a row check bit; and for each column of bits, generate a column check bit value that represents a column parity value for the corresponding bits in each of the plurality of row bundles and store the column check bit value as a column check bit.