Patent ID: 8356214

Claim:
An internal signal monitoring device in a semiconductor memory device, comprising: an internal signal input unit configured to receive an internal signal to be monitored and a test mode signal and to provide a monitor source signal in response to the test mode signal, which is activated during a test mode operation; and an internal signal output unit configured to receive the monitor source signal from the internal signal input unit and the test mode signal and to transmit the monitor source signal to a predetermined pad of the semiconductor memory device in response to the test mode signal, which is activated during the test mode operation, said predetermined pad comprising in addition receiving said monitor source signal, an address pad for receiving an address signal, a data pad for receiving or outputting data, a command pad for receiving a command signal, wherein the monitor source signal is output dependent upon the test mode activated during the test mode operation, said activated test mode signal also inhibiting said predetermined pad from i) receiving said address signal, ii) receiving or outputting data, and iii) receiving a command signal, wherein the internal signal output unit includes: a NAND gate for receiving the test mode signals and the monitor source signal; a first buffer unit for buffering an output signal of the NAND gate; a PMOS transistor, coupled to the pad, for receiving an output signal of the first buffer unit as a gate input signal; an inverter for inverting the test mode signal; a NOR gate for receiving an output signal or the inverter and the monitor source signal; a second buffer unit for buffering an output signal of the NOR gate; and an NMOS transistor, coupled to the predetermined pad, for receiving an output signal of the second buffer unit as a gate input signal.