Patent ID: 8560896

Claim:
A data processing system comprising: a central processing unit for executing instructions manipulating data; a direct memory access unit connected to said central processing unit, said direct memory access unit operating under control of said central processing unit to control data transfers including transferring data into a second level directly addressable memory; a memory attribute table storing required memory protections attributes corresponding to address ranges; a cache protection table storing required memory protections attributes corresponding to cache level; a comparator connected to said central processing unit, said direct memory access unit, said memory attribute table and said cache protection table, said comparator comparing memory protection attributes of a memory access with memory protection attributes of a corresponding address range recalled from said memory attribute table and with memory protection attributes of a corresponding cache level recalled from said cache protection table, and generating a memory access permission fault if said memory protection attributes of said memory access are insufficient to access a corresponding address range recalled from said memory attribute table and cache level; a memory error detect/correct unit generating an data exception signal upon detection of an error in data read from a memory; and an exception priority arbitration unit connected to said comparator and said memory error detect/correct unit, said exception priority arbitration unit outputting one received memory access permission fault or data exception signal according to a fixed hierarchy if received during a same cycle.