Patent ID: 6902969

Claim:
A process for forming a dual metal gate structure, comprising: providing a semiconductor substrate having a first region and a second region, wherein the first region has a first conductivity type and the second region has a second conductivity type, different from the first conductivity type; forming a dielectric layer overlying the first region and the second region of the semiconductor substrate; forming an etch stop layer overlying the first and second regions; forming a first metal-containing layer overlying the dielectric layer and the etch stop layer, wherein the first metal-containing layer overlies the first region of the semiconductor substrate; forming a second metal-containing layer overlying the first metal-containing layer, the dielectric layer, and the etch stop layer; forming a patterned masking layer overlying the second metal-containing layer; and dry etching the first and second metal-containing layers using the patterned masking layer to form a first gate electrode over the first region and a second gate electrode over the second region.