Patent ID: 6982575

Claim:
A clock ratio data synchronizer, comprising: a plurality of flip flops, the synchronizer synchronizing data received by the synchronizer from first clock domain logic at a first clock frequency to a second clock domain logic at a second clock frequency, the first clock domain logic being controlled by a first clock that generates the first clock frequency, the second cloak domain logic being controlled by a second clock that generates the second clock frequency, the first and second clocks being synchronized to each other at regular intervals and having edges that coincide at the regular intervals, Data In input logic that receives data from first clock domain logic at an input of a first one of said flip flops, the first clock domain logic being controlled by a first clock at a first clock frequency, said first one of said flip flops sampling data received at an input thereof when an edge of said first clock is received by said first one of said flip flops, said first one of said flip flops outputting the data sampled thereby from an output thereof when an edge of said first clock is received by said first one of said flip flops; synchronization logic that receives the data output from said first one of said flip flops, said synchronization logic including a first data path and a second data path, the data output from said first one of said flip flips being gated along the first and second data paths in accordance with one or more timing signals and edges of said first clock such that data from the first and second data paths is output from the synchronization logic in a predetermined order that resembles an order of the data received at the Data In input logic; and Data Out output logic that receives the ordered data from the synchronization logic in said predetermined order and outputs to ordered data from the synchronizer to second clock domain logic controlled by a second clock at a second clock frequency, the first and second clocks being synchronized to each other at regular intervals and having edges that coincide at the regular intervals; wherein the Data Out output logic includes an output flip flop that receives and samples the ordered data and that outputs the data sampled thereby at said second clock frequency when an edge of said second clock is received by said output flip flop.