Patent ID: 8564336

Claim:
A clock frequency divider circuit that generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S (N is positive integer and S is positive integer greater than N) by masking (S-N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S, the clock frequency divider circuit comprising: a mask control circuit that generates a mask signal in which a non-mask timing is preferentially assigned to a predetermined clock pulse among S clock pulses of the input clock signal, the predetermined clock pulse existing at a timing at which no clock pulse exists in a clock signal used in a circuit other than a target circuit, the target circuit using the output clock signal; and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.