Patent ID: 6995096

Claim:
A method for forming multi-layer wiring structure, wherein a lower wiring layer and an upper wiring layer are electrically connected through a via hole, comprising following steps: forming a SOG layer from a coating liquid containing 5–40 wt. % polysilazane having a weight average molecular weight in polystyrene conversion of 1500 to 5000 wherein at least part of the active hydrogen of said polysilazane is replaced with a trimethylsilil group, directly on said lower wiring layer or on a predetermined film including a hillock protection layer which is formed on said lower wiring layer in advance; forming said upper wiring layer on said SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on said upper wiring layer as a mask; conducting an ashing process to remove said patterned resist layer with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure of about 0.01 Torr; and filling said via hole with a conductive material so as to electrically connect said lower wiring layer to said upper wiring layer.