Patent ID: 6927429

Claim:
An integrated circuit comprising: a plurality of rows of cells, each row of cells of the plurality of rows of cells including a P well area and an N well area; a plurality of P well bias contacts to bias the P well areas; a plurality of N well bias contacts to bias the N well areas; a first plurality of lines to carry a first voltage; a second plurality of lines to carry a second voltage; a plurality of switching cells, each switching cell is located in a row of cells of the plurality and is coupled to a line of the first plurality of lines, a line of the second plurality of lines, an N well bias contact of the plurality of N well bias contacts, and a P well bias contact of the plurality of P well bias contacts, each of the plurality of switching cells includes a control input, wherein in response to the control input being at a first state, the switching cell couples the line of the first plurality of lines to the N well bias contact of the plurality of N well bias contacts and couples the line of the second plurality of lines to the P well bias contact of the plurality of P well bias contacts.