Patent ID: 7243292

Claim:
An error-correction apparatus for carrying out arithmetic and logical operations, the apparatus comprising: means for data input to, and data output from a general purpose processing unit, the processing unit for executing a plurality of processing operations on binary data stored in a single, hardware register, wherein the processing operations always operate on all bits of the single, hardware register simultaneously, the binary data comprising multiple coefficients of a field element of an odd-characteristic finite field GF(p k ), the field element comprising: k coefficients in a polynomial basis representation and k groups of binary data bits, each group of binary data bits comprising a corresponding one of the k coefficients, wherein k is greater than 1; and wherein the binary data is processed such that the k groups of binary data bits corresponding to the k coefficients are processed by parallel operations, each parallel operation being performed over a number of clock cycles independent of k during the plurality of operations, wherein at least one of the parallel operations is a finite field addition or multiplication of two arbitrary elements of GF (p k ) and the single, hardware register is arranged such that each parallel operation treats the k coefficients independently, wherein the field element is stored in the single, hardware register utilizing a single guard bit between each group of binary data bits to avoid carry bit problems wherein the single, hardware register is a w-bit register where w is greater than or equal to k(m+1) and m is the logarithm to base 2 of p, rounded up to the nearest integer.