Patent ID: 7843742

Claim:
A method of controlling a memory, said memory including a memory cell array and being connected to an address input and a data input/output, the method comprising the steps of: receiving a read address from the address input; receiving a write address from the address input; latching a single write data to be written into a memory cell corresponding to said write address from the data input/output; activating a memory cell corresponding to said read address; outputting a read data from said activated memory cell to said data input/output; activating the memory cell corresponding to said write address during outputting said read data to said data input/output; writing said latched single write data into said activated memory cell corresponding to said write address; comparing said write address with said read address; and replacing, if said write address matches a part of said read address, a read data of said matching address out of said read data by said latched single write data.