Patent ID: 8877608

Claim:
A method for preparing a germanium-on-insulator (GOI) chip structure, at least comprising the following steps: 1) preparing a SiGe on insulator (SGOI) structure by using a SMART CUT technique; 2) performing germanium concentration on the SGOI structure, so as to form a stacked structure, sequentially comprising a second Si substrate, an insulating buried layer BOX, a Ge layer, and a SiO 2 layer; and 2-1) putting the SGOI structure into a reaction furnace of 600° C., and then inputting 5000 ccm of N 2 as a protective atmosphere, heating up the reaction furnace at a rate of 10° C. per minute, and stopping inputting N 2 when the reaction furnace is heated up to 1050° C.; 2-2) inputting 4000 ccm of O 2 for 30 minutes, and then stopping the inputting; 2-3) inputting 5000 ccm of N 2 for 30 minutes, and then stopping the inputting; 2-4) sequentially repeating step 2-2) and step 2-3) 4 times, reducing the temperature of the reaction furnace from 1050° C. to 900° C. within an hour under the atmosphere of N 2 ; 2-5) inputting 4000 ccm of O 2 for 30 minutes, and then stopping the inputting; 2-6) inputting 5000 ccm of N 2 for 30 minutes, and then stopping the inputting; and 2-7) sequentially repeating step 2-5) and step 2-6) 4 times, reducing the temperature of the reaction furnace from 900° C. to 600° C. within an hour under the atmosphere of N 2 , implementing the germanium concentration to form the stacked structure, sequentially comprising the second Si substrate, the insulating buried layer BOX, the Ge layer, and the SiO 2 layer 3) etching off the SiO 2 layer on a surface of the stacked structure to obtain a GOI structure.