Patent ID: 7913132

Claim:
A digital system comprising: a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; at least one shadow engine, wherein the at least one shadow engine comprises a control circuit; wherein at least some of the power domains are interconnected to the scan chain with the scan enable switch; wherein the scan enable switch controls the scan mode by asserting a scan enable signal such that on each active clock edge, data of the scan data sequence is loaded or unloaded to be transferred from one sequential logic element to another in order to be scanned; wherein the at least one power gated power domain with one or more sequential logic elements to be power gated is bypassed via the at least one shadow engine, and wherein the control circuit of the at least one shadow engine overrides the scan data sequence for a number of times corresponding to the one or more sequential logic elements from the at least one power gated power domain such that when shifting the outputs from the scan chain into a register, a constant value is inserted at the location within the register corresponding to the outputs from the at least one power gated power domain for a number of scan cycles corresponding to the one or more sequential logic elements from the at least one power gated power domain.