Patent ID: 8916974

Claim:
An integrated circuit, comprising: one or more signal routing paths for transferring signals; and a dummy fill pattern, wherein the one or more signal routing paths are formed based on one or more electrical characteristics of at least one of cells and one or more metal layers defined on the integrated circuit, wherein the dummy fill pattern is determined based on one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the one or more signal routing paths, wherein the design rule specifies: determination of a metal congestion level of a window of the integrated circuit, wherein the window is a defined region of the integrated circuit; upon determining that the metal congestion level satisfies a threshold, formation of electrically connected, aligned rectangular dummy fill structures at available locations within the window; and upon determining that the metal congestion level does not satisfy the threshold, formation of floating, staggered rectangular dummy fill structures at available locations within the window.