Patent ID: 7556998

Claim:
A method of manufacturing a semiconductor device, the method comprising: preparing a semiconductor substrate in which an NMOS area, a PMOS area, an inactive area, and a test area are defined; forming an element isolating layer in the inactive area of the semiconductor substrate; forming a gate electrode in the active area of the NMOS area and the active area of the PMOS area; and forming a dummy gate electrode, which is made of the same material as the gate electrode and which is divided into a plurality of first areas and second areas, in the test area; selectively implanting N-type ions with a low concentration into a low-concentration junction region of the NMOS area and the plurality of first areas of the dummy gate electrode; selectively implanting P-type ions with a low concentration into a low-concentration junction region of the PMOS area and the plurality of second areas of the dummy gate electrode; selectively implanting N-type ions with a high concentration into the low-concentration junction region of the NMOS region and the plurality of first areas of the dummy gate electrode; selectively implanting P-type ions with a high concentration into the low-concentration junction region of the PMOS region and the plurality of second areas of the dummy gate electrode; and implanting impurity ions into a boundary region between the plurality of first areas and the plurality of second areas of the dummy gate electrode.