Patent ID: 8913447

Claim:
A memory, comprising: an input to receive command signals and chip select signals; a chip enable circuit coupled to the input and configured to receive the command signals and at least one of the chip select signals, the chip enable circuit configured to provide a memory unit enable signal responsive, at least in part, to the command signals having a first combination of states and the at least one of the chip select signals being active and further configured to not provide the memory unit enable signal responsive to the command signals having a second combination of states and the at least one of the chip select signals being active; and a command decoder coupled to the input and configured to receive the command signals and the chip select signals, the command decoder further configured to provide a memory unit command signal responsive to the command signals having the second combination of states, wherein the memory unit enable signal is provided for a first period and the memory unit command signal is provided for a second period, the second period having greater duration than the first period.