Patent ID: 7016366

Claim:
A packet switch comprising: a packet divider for dividing variable-length packets from a plurality of input lines into fixed-length packets; a plurality of input buffer sections provided corresponding to the plurality of input lines, each input buffer section having queues provided for each of mutually different priorities of a smaller number than that of QoS classes that can be designated, and for each of a plurality of output lines, for registering fixed-length packets from corresponding input lines to corresponding queues according to the output line and the QoS class; a scheduler for reading the fixed-length packets registered in the queues of the input buffer sections according to the priority given to each queue so that two or more fixed-length packets of the same output line are not read out within a unit time; a switch for routing each fixed-length packet read out by the scheduler to a designated one output line out of the plurality of output lines; and a plurality of output buffer sections provided corresponding to the plurality of output lines, for carrying out an assembling of a variable-length packet from the fixed-length packets output from the switch and for controlling the priority based on the QoS class.