Patent ID: 6947308

Claim:
A semiconductor memory comprising: one or a plurality of processor elements having arithmetic functions; a plurality of memory cells arranged in a matrix array; a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells; a plurality of sense amplifiers each connected to each bit line pair; a plurality of first gate pairs; a plurality of second gate pairs; a plurality of first data line pairs each connected with one of the bit line pairs selected via the first gate pairs, and said first data line pairs are dedicated for a predetermined column sub-block of the memory cells, on activation; and a plurality of second data line pairs each connected with one of the first data line pairs via the second gate pairs to select a predetermined row of sub-block data consisting of crossbar crosspoint, and said plurality of processor elements are connected to said plurality of second data line pairs, wherein the first data line pair and the second data line pair are arranged to intersect each other, and said first gate pairs and said second gate pairs are adjacent to said plurality of sense amplifiers.