Patent ID: 7310709

Claim:
A multiprocessor chip, comprising: a primary cache defined to include a tag structure; a secondary cache defined to include a tag directory representing the tag structure of the primary cache; a first portion of primary cache logic defined to identify a parity error in the tag structure of the primary cache; a second portion of primary cache logic defined to send a tag parity packet from the primary cache to the secondary cache in response to identification of the parity error by the first portion of primary cache logic; a first portion of secondary cache logic defined to invalidate each entry in the tag directory of the secondary cache as identified by the tag parity packet; a second portion of secondary cache logic defined to send an acknowledgment of receipt of the tag parity packet to the primary cache logic; and a third portion of primary cache logic defined to invalidate each entry in the tag structure of the primary cache associated with the parity error in response to receipt of the acknowledgement from the secondary cache.