Patent ID: 7689816

Claim:
A processor comprising: an instruction fetch unit (IFU) having: an instruction fetch address register (IFAR); a global history vector (GHV) mechanism coupled to the IFAR and which includes: an unfolded GHV having a plurality of entries for tracking groups of fetched instructions, each entry providing a bit indicating whether the group included a branch that was taken, and wherein unfolded means that no logical exclusive OR (XOR) has been performed on each entry; a folded GHV having a plurality of entries, which provides M folded entries, each entry providing a bit representing a result of folding two entries of the unfolded GHV, where M is less than N, and wherein folding means logically XORing the two entries of the unfolded GHV; first logic for folding a newly received, youngest branch result with an oldest unfolded entry in the unfolded GHV to provide a newest folded result; logic for shifting the newest folded result into the folded GHV to provide an updated folded GHV; and second logic for folding the updated folded GHV with a subset of bits from the IFAR to produce a resulting address that is utilized to address one or more branch history tables.