Patent ID: 8825463

Claim:
A logic simulation method executed by a processor, the method comprising: causing a physical specification detector to detect physical specifications of an analog circuit which is one of a PLL circuit incorporating a 1/n frequency dividing circuit and a DLL circuit incorporating the PLL circuit as a verification object described in a logic library stored in a memory; causing a monitor to monitor whether, during a logic simulation, a start reset signal, an order in which a release of a reset state of the PLL circuit or the DLL circuit and a setting of a feedback clock are to be performed, or an order in which a release of a reset state of the 1/n frequency dividing circuit and a release of a reset state of the PLL circuit or the DLL circuit are to be performed satisfies the physical specifications or not; and causing a warning section to issue a warning when the start reset signal, the order in which the release of the reset state of the PLL circuit or the DLL circuit and the setting of the feedback clock are to be performed, or the order in which the release of the reset state of the 1/n frequency dividing circuit and the release of the reset state of the PLL circuit or the DLL circuit are to be performed fails to satisfy the physical specifications, wherein: the physical specifications include a starting sequence indicating an order in which the release of the reset state of the PLL circuit or the DLL circuit and the setting of the feedback clock are to be performed, or an order in which the release of the reset state of the 1/n frequency dividing circuit and the release of the reset state of the PLL circuit or the DLL circuit are to be performed when the analog circuit is started and a pulse width of the start reset signal to be supplied when the analog circuit is started or reset; and when the monitor detects that the order in which the release of the reset state of the PLL circuit or the DLL circuit and the setting of the feedback clock are to be performed, or the order in which the release of the reset state of the 1/n frequency dividing circuit and the release of the reset state of the PLL circuit or the DLL circuit are to be performed fails to satisfy the starting sequence, the warning section issues the warning; and when the monitor detects that the start reset signal fails to satisfy the pulse width defined by the physical specifications during the logic simulation, the warning section issues the warning.