Patent ID: 8918988

Claim:
A method, comprising: (a) selecting a wiring level design of an integrated circuit design, said design defining a physical wiring level of an integrated circuit chip on a wafer, wherein said physical wiring level comprises wires comprising an electrical conductor in an interlevel dielectric layer; after (a), (b) determining if an electrical conductor shape density of said wiring level design is within a pre-defined range, said pre-defined range having a lower limit and a different upper limit; after (b), (c) if said electrical conductor shape density is below said lower limit of said range, increasing said electrical conductor shape density, if said electrical conductor shape density is between said lower limit and said upper limit not changing said electrical conductor shape density, if said electrical conductor shape density is greater than an upper limit of said range, decreasing said electrical conductor shape density; after (c), (d) fabricating said one or more of said integrated circuit chips on said wafer using said wiring level design; and wherein said decreasing said electrical conductor shape density comprises moving a shape that defines a wire of said integrated circuit from a first region of said wiring level to a second region of said wiring level.