Patent ID: 8446763

Claim:
A semiconductor memory device comprising: a first gate insulation layer and a second gate insulation layer, being spaced a predetermined distance from each other, on a portion of a semiconductor substrate; a select gate on the first gate insulation layer; a floating gate on the second gate insulation layer; a third gate insulation layer on the floating gate; a control gate on the third gate insulation layer; a first ion implantation region in the semiconductor substrate between the select gate and the floating gate; a second ion implantation region in the semiconductor substrate at a side of the select gate opposite the first ion implantation region; and a third ion implantation region in the semiconductor substrate at a side of the floating gate opposite the first ion implantation region; wherein the semiconductor memory device is configured such that during an operation of a program state for a selected unit cell, a first voltage of positive potential is applied to the control gate, the select gate is connected to a reference voltage, a first voltage of negative potential is applied to the third ion implantation region, and the second ion implantation region is connected to the reference voltage or is floated.