Patent ID: 7532696

Claim:
A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path, wherein: one dimension of the two dimensional estimation algorithm is arranged to estimate a gain mismatch between the first input path and the second input path and the second dimension of the two dimensional estimation algorithm is arranged to estimate a time delay between the first input path and the second input path; and the two dimensional estimation algorithm takes the form of: [ k ^ h ⁡ ( n + 1 ) τ ^ D ⁡ ( n + 1 ) ] = [ k ^ h ⁡ ( n ) τ ^ D ⁡ ( n ) ] + [ μ k 0 0 μ τ ] ⁡ [ - sin ⁢ { ω ⁡ ( n - τ ^ D ⁡ ( n ) - τ G ) } k ^ h ⁢ cos ⁢ { ω ⁡ ( n - τ ^ D ⁡ ( n ) - τ G ) } ] ⁢ e ^ ⁡ ( n ) where: ê(n) is a sampled tuning voltage, τ G is the approximate group delay through the low port to the sampled, digitally processed tuning voltage, ω is a test tone frequency, μ τ and μ k are scalar constants that control calibration transients, {circumflex over (τ)} D is the estimate of the high port delay and {circumflex over (k)} h is the estimate of the high port gain.