Patent ID: 8193842

Claim:
A frequency synthesizer comprising: a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; a frequency detector outputting a first control bit obtained by subtracting the count value of the counter unit from an integer value of a value obtained when a frequency channel word (FCW) command value is divided by the minimum division ratio, the FCW command value being a bit value inputted in order to obtain a desired output frequency; a phase detection unit outputting a second control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency; a mode change block connected to the frequency detector and the phase detection unit to selectively output the first control bit or the second control bit; and a loop filter unit connected between the mode change block and the frequency oscillator.