Patent ID: 7636412

Claim:
A shift register circuit comprising: first and second input terminals, an output terminal and a clock terminal; a first transistor for providing a clock signal input to said clock terminal to said output terminal; a second transistor for discharging said output terminal; first and second voltage signal terminals input with first and second voltage signals complementary to each other; a third transistor for providing said first voltage signal to a first node connected with a control electrode of said first transistor based on a first input signal input to said first input terminal; a fourth transistor for providing said second voltage signal to said first node based on a second input signal input to said second input terminal; a fifth transistor for providing said second voltage signal to a second node connected with a control electrode of said second transistor based on said first input signal; and a sixth transistor for providing said first voltage signal to said second node based on said second input signal, wherein said shift register circuit changes a shift direction of a signal at the output terminal by switching the levels of said first and second voltage signals, and wherein said third transistor connects to said first voltage signal terminal by way of a seventh transistor having a control electrode connected to a control electrode of said third transistor; said fourth transistor connects to said second voltage signal terminal by way of an eighth transistor having a control electrode connected to a control electrode of said fourth transistor; and said shift register circuit further includes a charging circuit for charging a third node, which is a connecting node of said third transistor and said seventh transistor, and a fourth node, which is a connecting node of said fourth transistor and said eighth transistor, when said output terminal is activated.