Patent ID: 7709911

Claim:
A semiconductor device comprising: a substrate of silicon; a first MIS transistor including a first gate electrode of silicon formed on the substrate, first sidewall spacers formed on both sides of the first gate electrode, first source/drain regions formed in regions of the substrate located further from the first gate electrode than the first sidewall spacers, and plasma reaction films formed in direct contact with the respective top surfaces of the first gate electrode and first source/drain regions; and a second MIS transistor including a second gate electrode of silicon formed on the substrate, second sidewall spacers formed on both sides of the second gate electrode, second source/drain regions formed in regions of the substrate located further from the second gate electrode than the second sidewall spacers, and silicide layers covering the respective top surfaces of the second gate electrode and second source/drain regions, wherein each said plasma reaction film has a thickness of 1 nm through 2 nm both inclusive.