Patent ID: 7996590

Claim:
A semiconductor memory module comprising: a memory module board comprising at least one semiconductor memory device, wherein the at least one semiconductor memory device comprises: a data input buffer receiving data via a first input terminal and receiving a first reference voltage via a second input terminal; a command/address input buffer receiving a command/address signal via a first input terminal and receiving a second reference voltage via a second input terminal; and a first termination resistor unit connected to the first input terminal of the data input buffer; an internal command/address bus providing the command/address signal to the command/address input buffer; and a second termination resistor unit located on the memory module board and connected to the internal command/address bus, wherein the first input terminal of the data input buffer has a first signal swing level based on a first termination type of the first termination resistor unit, and the first input terminal of the command/address input buffer has a second signal swing level based on a second termination type of the second termination resistor unit, wherein the first reference voltage has a first level corresponding to the first signal swing level, and the second reference voltage has a second level corresponding to the second signal swing level, and wherein at least one of the first reference voltage and the second reference voltage are obtained by performing calibration based on at least one of the first termination type and the second termination type.