Patent ID: 7788552

Claim:
A method of testing a module assembly having at least two chip modules, comprising: first transmitting a first test signal from a second chip module to a first chip module across a circuit path that includes at least first and second interposers respectively connected to the first and second chip modules, each of said chip modules having diagnostic logic for transmitting test signals and receiving reflections of the test signals to locate an open fault in the circuit path; first receiving no reflected signal of the first test signal at the second chip module within a predetermined time from said transmitting; determining from said first receiving no reflected signal that there is at least one open fault in the circuit path at the second interposer; second transmitting a second test signal from the first chip module to the second chip module across the circuit path; second receiving a reflected signal of the second test signal at the first chip module; and determining from said first receiving no reflected signal and from said second receiving the reflected signal that there is only one open fault of the circuit path and the one open fault is at the second interposer.