Patent ID: 7026709

Claim:
A chip-packaging stack structure, comprising: a plurality of chip-packaging units, suitable for stacking one over another, wherein each of the chip-packaging units comprises: a substrate, having a top surface and a corresponding bottom surface, a plurality of upper contacts disposed on the top surface, and a plurality of lower contacts disposed on the bottom surface, wherein the upper contacts are electrically connected to the lower contacts respectively; a chip disposed on the top surface of the substrate and having a plurality of inner contacts and a plurality of outer contacts, wherein the inner contacts are electrically connected to the outer contacts respectively; a plurality of wires, respectively connected to the upper contacts and the inner contacts; a molding compound coveting the wires, the chip and the upper contacts of the substrate, wherein the molding compound has an opening for exposing the outer contacts, and the outer contacts remain exposed on a surface of the chip which also serves as en external surface of the packaging unit; and a plurality of solder balls, respectively connected to the lower contacts and being corresponding to the outer contacts of other chip-packaging wilts for electrically connecting the chip-packaging units.