Patent ID: 7214983

Claim:
A non-volatile memory, comprising: a plurality of columns of source/drain regions disposed within a substrate; a plurality of columns at dielectric strips disposed over the source/drain regions; a plurality of rows of word lines disposed over the dielectric strips, wherein the word lines cross over the dielectric strips perpendicularly; a plurality of stack gate structures aligned to form a plurality of columns, wherein each column of stack gate structure is disposed between the word lines and the substrate and between the dielectric strips, and each stack gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially stacked over the substrate; a plurality of etching stopped layers disposed on the substrate between neighboring columns of stack gate structures and between the dielectric strips, wherein the sidewalls of the etching stopped layers are perpendicular to the substrate; a dielectric layer covering the dielectric strips, the word lines and the etching stopped layers; and a plurality of contacts disposed in the dielectric layer and the dielectric strips between the neighboring rows of word lines, wherein a portion of the contacts cover the etching stopped layers on each side of the dielectric strips and each contact connects electrically with a corresponding source/drain region.