Patent ID: 8227911

Claim:
A packaged integrated circuit device comprising: a semiconductor substrate having a surface region, a first portion and a second portion; one or more CMOS integrated circuit devices fabricated on a first portion of the semiconductor substrate; one or more sensitive integrated circuit modules provided on a second portion of the semiconductor substrate; a seal ring formed encircling the one or more sensitive integrated circuit modules; one or more dielectric layers overlying the one or more CMOS integrated circuit devices and the one or more sensitive integrated circuit modules to form a passivation structure overlying the one or more CMOS integrated circuit devices and the one or more sensitive integrated circuit modules; a void volume overlying the one or more dielectric layers within a vicinity of at least the one or more sensitive integrated circuit modules; and a barrier material overlying at least the void volume to hermitically seal the one or more sensitive integrated circuit modules while maintaining the void volume overlying the one or more dielectric layers, the barrier material being electrically coupled with the seal ring to shield the one or more sensitive integrated circuit modules.