Patent ID: 8743108

Claim:
A liquid crystal display, comprising: a liquid crystal panel comprising liquid crystal cells in a matrix array at crossings of data lines and gate lines; a data drive circuit configured to provide positive and negative data voltages and a black gray scale voltage to the data lines; a plurality of gate drive integrated circuits configured to provide gate signals to the gate lines; a frame frequency detector configured to detect a frame frequency of an input image by counting vertical sync signals based on a fixed clock signal irrespective of the frame frequency; and a timing controller configured to control operation timings of the data drive circuit and the gate drive integrated circuits, and to modulate gate timing control signals for controlling the gate drive integrated circuits depending on changes of the frame frequency to change a write time of the black gray scale voltage charged to the liquid crystal cells, wherein the gate timing control signals comprise a gate start pulse that is applied to one of the gate drive integrated circuits and controls black data insertion percentage in a frame, wherein the gate start pulse indicates a scan start line of a scan operation such that the one of the gate drive integrated circuits is configured to generate a first gate signal, and comprises first and second pulses each comprising a different width, wherein the gate start pulse comprises the first pulse and the second pulse of which a delay value changes depending on the black data insertion percentage, and wherein the timing controller is further configured to: reduce a time difference between the first and second pulses of the gate start pulse to reduce the write time of the black gray scale voltage when the frame frequency falls, and lengthen the time difference between the first and second pulses of the gate start pulse to increase the write time of the black gray scale voltage when the frame frequency rises after the frame frequency has fallen.