Patent ID: 8106692

Claim:
A method for tracking a delay locked loop (DLL) clock and adapted to a DDL, comprising: allowing an external clock signal to pass through delay cells of the DLL during a first period of the external clock signal when a first transition edge of a track signal applied on the DLL occurs; inhibiting the external clock signal to pass through the delay cells of the DLL and counting the number of the delay cells through which the external clock signal pass during the first period of the external clock signal when a first transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the clock external signal; and resetting a delay time of each of the delay cells such that a ratio of the delay time to the first period of the external clock signal is kept within a range when a reset signal is asserted, wherein whether the reset signal is asserted is triggered by the first transition edge of the sensing signal and the range is from 10% to 15%.