Patent ID: 7818604

Claim:
A system for increasing the data throughput of an I 2 C bus including a serial clock conductor for conducting a serial clock signal and a serial data conductor for conducting a serial data signal, the system comprising: a slave device coupled to the serial clock conductor and the serial data conductor, wherein the slave device is operable to provide an acknowledge of a transfer from a master device via the serial data conductor, and wherein the slave device includes: a clock stretch control circuit that is operable to: hold the serial clock conductor at a predetermined level to cause a master device to stop sending the serial clock signal for a stretch period extending beyond the acknowledge upon determining that a need for additional time exists, and release the serial clock conductor approximately coincident with the acknowledge upon determining that no need for additional time exists; a switch coupled between the serial clock conductor and a reference voltage conductor, and wherein the switch is controlled by an output of the clock stretch control circuit; and a processor, wherein the clock stretch control circuit includes a first circuit responsive to a start stretch signal to produce an internal stretch signal for causing closing of the switch, wherein the clock stretch control circuit further includes a second circuit for producing a stretch release signal in response to stretch release information produced by the processor, and wherein the clock stretch control circuit further includes a third circuit that functions to cause opening of the switch at least in part in response to the stretch release signal.