Patent ID: 8314424

Claim:
A thin film transistor array substrate, comprising: a plurality of pixel electrodes arranged in a matrix pattern: a plurality of source lines arranged to extend in parallel to one another and each arranged between the pixel electrodes; a plurality of gate lines arranged to extend in parallel to one another and in a direction crossing the source lines; and a plurality of thin film transistors respectively provided per each of intersections of the gate lines and the source lines, wherein the thin film transistors each include: a gate electrode connected to corresponding one of the gate lines; a first semiconductor portion formed to be island-shaped and to overlap the gate electrode having a gate insulating film interposed therebetween; a source electrode arranged to overlap the gate electrode having the gate insulating film and the first semiconductor portion interposed therebetween and connected to corresponding one of the source lines, a drain electrode arranged to overlap the gate electrode having the gate insulating film and the first semiconductor portion interposed therebetween and connected to corresponding one of the pixel electrodes; a second semiconductor portion formed to be island-shaped between the gate insulating film and the source electrode so as to overlap the gate electrode, and a conductive portion arranged to overlap the gate electrode having the gate insulating film and the second semiconductor portion interposed therebetween, and wherein the thin film transistors are each configured such that, when a short-circuit portion is formed by a short-circuit established at the source electrode and the drain electrode, the source line connected to the source electrode and the pixel electrode connected to the drain electrode are brought into conduction by a switching element including the short-circuit portion, the second semiconductor portion and the conductive portion.