Patent ID: 8181135

Claim:
A method of hold fault modeling and test generation performed by at least one computer device, the method comprising: modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of nets in an integrated circuit using the at least one computer device; testing a fast-to-rise hold fault by: setting up a logic value on each of the plurality of nets in the integrated circuit to a logic value of 0; transitioning each of the plurality of nets in the integrated circuit from a the logic value of 0 to a logic value of 1 with a single clock pulse; and determining whether the fast-to-rise hold fault occurred by determining whether the transitioning was accurately captured in all of a downstream subset of nets in the plurality of nets in the integrated circuit, wherein the fast-to-rise hold fault is indicated by the transitioning being inaccurately captured in at least one of the downstream subset of nets; and testing a fast-to-fall hold fault by: setting up a logic value on each of the plurality of nets in the integrated circuit to a logic value of 1; transitioning each of the plurality of nets in the integrated circuit from the logic value of 1 to a logic value of 0 with a single clock pulse; and determining whether the fast-to-fall hold fault occurred by determining whether the transitioning was accurately captured in all of the downstream subset of nets in the plurality of nets in the integrated circuit, wherein the fast-to-fall hold fault is indicated by the transitioning being inaccurately captured in at least one of the downstream subset of nets.