Patent ID: 8713486

Claim:
A method for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of shapes each including edges in a plurality of different orientations, each of the edges having endpoints at respective locations in the layout, endpoints of edges in a first one of the orientations being first endpoints and endpoints of edges in a second one of the orientations being second endpoints, for use by a computer system having access to a design rule data set indicating constraint values of design rules in the data set, the method comprising the steps of: the computer system scanning the layout region in a first dimension which is perpendicular to the first edge orientation, so as to encounter first endpoints of the edges having the first orientation; in response to encountering each of at least a first subset of at least two of the first endpoints, the computer system populating a layout topology database with values in dependence upon the respective first endpoint location; the computer system scanning the layout region in a second dimension which is perpendicular to the second edge orientation, so as to encounter second endpoints of the edges having the second orientation; in response to encountering each of at least a second subset of at least two of the second endpoints, the computer system populating the layout topology database with values in dependence upon the respective second endpoint location; after the layout topology database has been populated with values in dependence upon the first endpoint location of all endpoints in the first subset of endpoints, and values in dependence upon the second endpoint location of all endpoints in the second subset of endpoints, the computer system comparing values in the layout topology database to values in the design rule data set to detect any violations of design rules in the set of design rules; and where a design rule violation is detected, reporting it to a user.