Patent ID: 8312399

Claim:
A system with a plurality of processors having a computer program product embodied thereon, the computer program product comprising: computer code for generating a matrix representation of a circuit design; computer code for applying a hypergraph partitioner to the matrix representation so as to convert the matrix representation into a first bordered block diagonal (BBD) matrix having a first set of diagonal submatrices and a set of border submatrices, wherein each border submatrix from the set of border submatrices is associated with at least one of the diagonal submatrices from the first set of diagonal submatrices; computer code for reordering the first BBD matrix to generate a second BBD matrix having a second set of diagonal submatrices, a set of column border submatrices, a set of row border submatrices, and an interconnect submatrix, wherein each column border submatrix is associated with at least one of the diagonal submatrices from the second set of submatrices, and wherein the interconnect submatrix is associated with each row border submatrix; computer code for associating each of the diagonal submatrices from the second set of diagonal submatrices with at least one of the processors; computer code for solving each of the diagonal submatrices from the second set of diagonal submatrices; and computer code for solving the interconnect submatrix at least after each of the diagonal submatrices from the second set of diagonal submatrices have been solved.