Patent ID: 7888674

Claim:
A thin-film transistor (TFT) substrate, comprising: a gate wiring disposed on a substrate, the gate wiring comprising a gate electrode, a lower storage electrode, and a gate metal pad; a capacitor dielectric layer disposed on the lower storage electrode; a gate insulation layer disposed on the substrate; an active pattern including an active layer and a dummy active layer disposed on the gate insulation layer in a gate electrode region and a gate metal pad region, respectively; a data wiring comprising a source electrode, a drain electrode, an upper storage electrode, and a data metal pad, the source and drain electrodes being disposed on the active layer such that the source and drain electrodes are spaced apart from each other, a portion of the upper storage electrode being disposed on the capacitor dielectric layer exposed through a first contact hole in the gate insulation layer, the data metal pad being directly connected to the gate metal pad through a second contact hole in the gate insulation layer and the dummy active layer; a protection layer disposed on the substrate; and a pixel electrode disposed on the protection layer, the pixel electrode being connected to the drain electrode.