Patent ID: 6958500

Claim:
A semiconductor device comprising: a semiconductor substrate having a first top surface assigned in an active area and a second top surface lower than the first top surface assigned in an isolation area surrounding the active area in a top view; an isolation insulator including first insulators disposed on the second top surface, having a third top surface higher than the first top surface, and a second insulator disposed on the second top surface, partially in contact with the outer side faces of the first insulators, having a fourth top surface higher than the third top surface; a source side wall insulator including a first side wall contacted to the first top surface and the inner side face of the second insulator, and a second side wall disposed on the first top surface and having ends respectively in contact with ends of the first side wall; a drain side wall insulator including a third side wall contacted to the first top surface and the inner side face of the second insulator, and a fourth side wall disposed on the first top surface, parallel to the second side wall and having ends respectively in contact with ends of the third side wall; a gate insulation film contacted to the first top surface and the third top surface and in contact with side faces of the second insulator, the second side wall and the fourth side wall; a gate conductor disposed on the gate insulation film and having a side face in contact with the gate insulation film; a source conductor electrically connected to the first top surface, and having a side face in contact with the source side wall insulator; and a drain conductor electrically connected to the first top surface, and having a side face in contact with the drain side wall insulator.