Patent ID: 6946873

Claim:
A system for recovering and aligning synchronous data transmissions, comprising: a transmitter configured to transmit a source clock signal and a plurality of data groups over a plurality of channels, the plurality of data groups being transmitted during the same clock cycle pursuant to the source clock signal, each data group being transmitted over a corresponding channel; and a receiver configured to receive the source clock signal and the plurality of data groups over the plurality of channels, the receiver further configured to include: for each channel: (a) a local clock configured to generate a local clock signal based on the source clock signal, the local clock signal being phase-shifted from the source clock signal by a predetermined amount of phase shift, (b) a logic device configured to clock in the data group received over the channel using the local clock signal, (c) a sequence number generator configured to generate a sequence number associated with the data group, (d) a FIFO buffer configured to store and output the clocked-in data group and the associated sequence number, (e) a memory device configured to store the clocked-in data group from the FIFO buffer using the associated sequence number as a memory address, the memory device further configured to output a predetermined portion of its contents after a predetermined capacity threshold is reached.