Patent ID: 8176353

Claim:
A method for transferring data between a first clock domain having a first clock rate and at least one additional clock domain having a second clock rate, wherein the data is transferred from the first clock domain to the at least one additional clock domain, the method comprising: reading in of a data item in accordance with the first clock rate into a first memory, and locking of the first memory after saving the data item, signalizing a transfer start after saving the data item in the first memory by means of a transfer start signal, reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock rate, processing the transfer start signal according to the second clock rate for generating a transfer end signal, processing the transfer end signal according to the first clock rate for generating a release signal and releasing the first memory as a function of the release signal, wherein a level change of the transfer end signal is generated according to a default number of clock period of the second clock rate after a level change of the transfer start signal, and wherein the generating of a level change of the transfer end signal occurs utilizing a first subsidiary signal, which is generated according to a default number of clock periods of the second clock rate after a level change of the transfer start signal.