Patent ID: 7117295

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, each said memory cell including a storage element holding binary data of n bits based on 2 n (n: natural number) threshold levels, and said threshold levels respectively corresponding to ordered data obtained by rearranging a data set of said binary data of n bits in a procedure equivalent to steps of: i) associating n bit pointer variables BP(i) (i: natural number, 1≦i≦n) with n integers from zero to (n−1) arranged in arbitrary order respectively, ii) dividing said data set into two data groups according to whether data of a BP(1)-th bit is “0” or “1” and arranging said two data groups in order in a first step, and iii) dividng each of said data groups of said data set, which has been divided into 2 j−1 groups in the process up to a (j−1)th step, into two data groups further in response to whether data of a BP(j)-th bit is “0” or “1” in a j-th step (j: natural number, 2≦j=n); a cell selection circuit collectively selecting a plurality of said memory cells from said memory cell array in response to an address signal; a data read/write circuit performing a read/write operation of storage data on said selected plurality of memory cells on the basis of (2 n −1) determination levels corresponding to boundaries between groups of said threshold levels corresponding to said data groups; and a data input/output circuit for transferring said storage data between the outside of said nonvolatile semiconductor memory device and said memory cells as binary data through k input/output nodes by every k bit (k: natural number), wherein storage data held in each said memory cell is generated from n bit data transferred at different timings through the same said input/output node.