Patent ID: 8058094

Claim:
A method of fabricating a transistor, the method comprising: forming at least two polycrystalline silicon layers disposed substantially parallel to each other, each said at least two polycrystalline silicon layers including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region, and a third polycrystalline silicon layer which connects two ends of the polycrystalline said at least two silicon layers on a substrate; forming a gate insulating layer on the said at least two polycrystalline silicon layers; forming a gate material layer on the gate insulating layer; forming a gate which corresponds to the channel region of the said at least two polycrystalline silicon layers and which crosses said the at least two polycrystalline silicon layers by removing the gate material layer and the gate insulating layer in substantially the same pattern; and implanting impurities into both sides of the two polycrystalline silicon layers which are left uncovered by the gate, wherein a direction of the implanting impurities is performed at an angle to the substrate, which creates a shade region where the impurities do not directly reach the polycrystalline silicon layers, wherein low conductivity regions are formed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of the each said at least two polycrystalline layers.