Patent ID: 8906709

Claim:
A method of high productivity combinatorial (HPC) inspection of a semiconductor substrate, the method comprising: receiving the semiconductor substrate comprising a first layer and a second layer, the first layer disposed over and directly interfacing the second layer, the first layer comprising a first material, the second layer comprising a second material, the first material and the second material having at least one of a thermal mismatch, a structural mismatch, or a lattice mismatch, the first layer comprising multiple site-isolated regions (SIRs) defined thereon; performing an etch process on a portion of the first layer in each SIR, the etch process comprising exposing each of the SIRs to one of a plurality of etch process conditions, the etch process conditions being varied in a combinatorial manner between at least two of the SIRs; and inspecting each of the site-isolated regions to determine an etch-pit density (EPD) value.