Patent ID: 7932766

Claim:
A digitally controlled oscillator comprising: a phase compensation block generating a PLL signal PLLCLK and a first clock signal CLK 1 which has the same phase and frequency as the PLL signal PLLCLK, in response to a phase control signal DISABLE and a fourth clock signal CLK 4 ; a coarse block generating a second clock signal CLK 2 and a third clock signal CLK 3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK 1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m−1)-bit coarse B control signal COAR_B; and a fine block generating the fourth clock signal CLK 4 by applying interpolation to the second clock signal CLK 2 and the third clock signal CLK 3 in response to an n(integer)-bit first fine control signal FCB and a n-bit second fine control signal FC, wherein the phase compensation block comprises: a first NOR gate generating the PLL signal PLLCLK by performing an NOR operation on the phase control signal DISABLE and the fourth clock signal CLK 4 ; and a second NOR gate generating the first clock signal CLK 1 by performing an NOR operation on the phase control signal DISABLE and the fourth clock signal CLK 4 .