Patent ID: 7161833

Claim:
A method for programming a memory system, said system comprising strings of charge storage transistors for storing different charge states, each of said strings including two select transistors, each of said strings connected between one of a plurality of bit lines and a source line, said strings controlled by a common set of word lines, wherein at least a first transistor in a first string of the strings and adjacent to one of the two select transistors in the first string is in a desired charge storage state, said method comprising: applying a program voltage level through one of the word lines to a control gate that is capacitively coupled with a second transistor in a second string of the strings different from the first string to program the second transistor, said second transistor separated from the source line or the bit line connected to the second string by one or more charge storage transistors in said second string; and boosting through some of the word lines electrical potential(s) of channel regions of the first string of transistors by coupling boosting voltage levels to at least some of the transistors in the first string to reduce program disturb, wherein the electrical potential(s) of the channel regions of some of the transistors in the first string are/is boosted so that breakdown at the drain or source side of the one select transistor in the first string is reduced to such an extent that it does not result in a change of the first transistor's desired charge storage state to a different charge state.