Patent ID: 7916542

Claim:
A nonvolatile memory device comprising: a memory cell array comprising a plurality of memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line; a latch circuit for providing first page data to the first page region in response to a first address and subsequently providing second page data to the second page region in response to a second address; and a bit-line switch circuit between the memory cell array and the latch circuit, the bit-line switch circuit comprising a first bit-line switch circuit for selecting bit lines to load the first page data into the first page region in response to the first address during a programming operation, and a second bit-line switch circuit for selecting bit lines to load the second page data into the second page region in response to the second address, wherein the first address is different from the second address.