Patent ID: 8866697

Claim:
A display device, comprising: a graphic card for outputting RGB data and control signals of a transistor transistor logic (TTL) type for an image, wherein the graphic card includes a single low voltage differential signaling (LVDS) transmitting portion for converting the RGB data and the control signals into communication signals of an LVDS type; a single timing controller for converting the RGB data and the control signals into a plurality of gate signals and a plurality of data signals; a single interface board connected between the graphic card and the single timing controller, wherein the single interface board includes a single LVDS receiving portion for reconverting the communication signals of the LVDS type into the RGB data and the control signals of the TTL type; wherein the single LVDS transmitting portion transmits the RGB data and the control signals of the graphic card, and the single LVDS receiving portion receives the RGB data and the control signals and transmits the RGB data and the control signals to the single timing controller; and a plurality of display panels controlled by the single timing controller, for receiving the corresponding gate signals and data signals from the single timing controller, the plurality of display panels driven in parallel or series to display the image on a combined display area of the plurality of display panels as a whole, wherein the single timing controller comprises: a scaling unit for scaling the image to fit into the combined display area of the plurality of display panels; a dividing unit for dividing the scaled image into a plurality of sub-images corresponding to the plurality of display panels, respectively; a gate signal generating unit and a data signal generating unit generating the plurality of gate signals and the plurality of data signals for the plurality of display panels, respectively, corresponding to the plurality of sub-images; and a timing controlling unit for determining timing for outputting the plurality of gate signals and the plurality of data signals to the plurality of display panels, wherein when the plurality of display panels are driven in parallel, gate lines of a first display panel of the plurality of display panels and gate lines of a second display panel of the plurality of display panels are sequentially selected at the same time in accordance with the determination made by the timing controlling unit, wherein when the plurality of display panels are driven in series, the gate lines of the second display panel are sequentially selected after the gate lines of the first display panel are sequentially selected in accordance with the determination made by the timing controlling unit, and wherein the RGB data increases by duplication to fit a plurality of pixels arranged in a horizontal line of the plurality of display panels in the scaling unit and the control signals are divided.