Patent ID: 7567475

Claim:
A memory architecture, comprising: a matrix of memory cells structured into rows and columns of cells and including wordlines; a row decoder associated with the matrix; an array of reference cells associated with the matrix; a first detector block for the memory cells, the first detector block including a plurality of sense amplifiers associated with the matrix of memory cells in correspondence with its columns, as well as a plurality of latch registers connected to outputs of the sense amplifiers, respectively; a references bus interconnecting the latch registers; a second detector block for the reference cells, the second detector block being connected to the latch registers by the references bus and including at least one sense amplifier of the reference cells, wherein the second detector block further comprises a stabilized buffer to supply the bus with an output signal with a rise transient that is stable with respect to working conditions of the architecture; and wherein the array of reference cells is connected upstream of the wordlines of the matrix taking as reference a propagation direction of a voltage signal applied to at least one of the memory cells.