Patent ID: 7821854

Claim:
A semiconductor memory, comprising: a cell array having memory cells and word lines, bit lines coupled to the memory cells; a plurality of redundancy fuse circuits in which a plurality of defect addresses are programmed respectively; regular redundancy lines provided dedicatedly and respectively corresponding to the redundancy fuse circuits and arranged to relieve a defect; a reservation redundancy line provided in common to the redundancy fuse circuits and arranged to relieve a defect; a plurality of address comparison circuits provided corresponding to the redundancy fuse circuits respectively, each comparing one of the defect addresses programmed in the redundancy fuse circuits with an access address and outputting a redundancy signal when a comparison result is a match; a switch circuit validating in response to the redundancy signal one of a corresponding regular redundancy line and the reservation redundancy line; and a selection fuse circuit outputting a redundancy selection signal to control switching of the switch circuit.