Patent ID: 7233308

Claim:
A shift register, comprising a plurality of stages connected in cascade for shifting input signals in accordance with a plurality of phase-delayed control signals, a first supply voltage, and a second supply voltage, and for applying the shifted input signals as output signals and as input signals of the succeeding ones of stages, wherein each of plurality of stages comprises: a first controller for selectively applying an input signal and a first supply voltage to a first node arranged between first to third transistors that form a conductive path between a supply line of the input signal and an input line of the first supply voltage; a second controller for selectively applying the first supply voltage and the second supply voltage to a second node arranged between fourth and fifth transistors forming a conductive path between an input line of the second supply voltage and the input line of the first supply voltage; and an output buffer for selectively applying a predetermined control signal and the first supply voltage as an output signal to a stage output line sixth and seventh transistors forming a conductive path between the input line of the first supply voltage and an input line of the predetermined control signal, wherein the fifth transistor is controlled by a voltage of a third node arranged between the first and second transistors.