Patent ID: 8508986

Claim:
A semiconductor device comprising a memory array, in which a memory cell for magnetically storing a data signal is arranged in a matrix, the memory array being divided into a plurality of segments for each predetermined number of columns, each segment being further divided into blocks for each row, the semiconductor device further comprising: a digit line provided for each block; a plurality of bit lines provided corresponding to each column; a plurality of digit line drivers each causing a magnetizing current to flow through the digit line of one selected block; a bit line driver which causes a write current to flow in a direction corresponding to a logic of a data signal to a bit line in a selected segment and writes the data signal to a memory cell of the selected block; and a decoder which, when an address of one segment has been input from the outside, selects one segment corresponding to the address and couples the selected segment to either one of the digit line drivers, and which, when addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to different digit line drivers.