Patent ID: 6865115

Claim:
A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and an input stage for providing an output signal having a logic value based on voltage of an input signal, the input stage comprising: an input buffer having an input terminal to which the input signal is applied, an output terminal at which the output signal is provided, and a reference terminal to which a reference voltage signal is applied, the input buffer generating an output signal having a logic value based on the voltage of the input signal relative to the voltage of the reference voltage signal; and a voltage generator having an output terminal coupled to the reference terminal and further having a control terminal coupled to the output of the input buffer, the voltage generator generating as the reference voltage signal an output signal having a voltage dependence on the logic value of the output signal of the input buffer.