Patent ID: 7601572

Claim:
A method for manufacturing a semiconductor device comprising: forming a crystalline semiconductor layer on an insulating surface, wherein the crystalline semiconductor layer includes a source region, a drain region and a channel formation region; forming a gate insulating film over the crystalline semiconductor layer; forming a first interlayer insulating film over the gate insulating film; forming a second interlayer insulating film over the first interlayer insulating film; etching a portion of the second interlayer insulating film by a wet-etching, thereby eliminating the second interlayer insulating film disposed over the source region or the drain region; etching the first interlayer insulating film and the gate insulating film to form a contact hole which reaches at least one of the source region and the drain region, wherein at least one of the source region and the drain region is also etched; and forming a pixel electrode electrically connected to one of the source region and the drain region, wherein a selective etching ratio of the first interlayer insulating film to the crystalline semiconductor layer is from 12 to 15.