Patent ID: 7603523

Claim:
A system for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated therewith and operatively connected via a first communications means, said system comprising: a plurality of snoop filter devices in 1:1 correspondence with an associated processing unit, each said snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in said multiprocessor computing environment; a point-to-point interconnect means comprising communication links for directly connecting said memory writing sources to the dedicated input ports of all other snoop filter devices associated with all other processing units of said multiprocessor computing environment; each of said plurality of snoop filter devices further having a plurality of parallel operating port snoop filters in 1:1 correspondence with said plurality of dedicated input ports, each said plurality of parallel operating port snoop filters having a corresponding snoop cache adapted for tracking snoop requests from a corresponding one of said dedicated memory writing sources and recording an address of each snoop request from its corresponding memory writing source; and, and having a corresponding snoop cache logic means for comparing a received snoop request address against all addresses recorded in said corresponding snoop cache, said plurality of port snoop filter devices concurrently filter snoop requests received from respective said dedicated memory writing sources and forward a subset of those requests to its associated processing unit, whereby a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of said computing environment.