Patent ID: 7650373

Claim:
A source driver for activating plural output signals comprising a plurality of shift registers coupled in series, wherein Nth shift register among the plurality of shift registers receives both an output of a (N−1)th shift register and an output of a (N−A)th shift register and selects one of the output of a (N−1)th shift register and the output of a (N−A)th shift register according to a channel selection signal, where the A and the N are natural numbers which are greater than or equal to 2 wherein each output signal of the (N−A+1)th to (N−l)th shift registers is inactivated when the Nth shift register selects the output of the (N−A)th shift register in response to an activation of the channel selection signal, wherein the shift register receives one of the output of the (N−1)th shift register and the output of the (N−A)th shift register as a left input signal in response to the channel selection signal, or receives one of an output of a (N−1)th shift register and an output of a (N+A)th shift register as a right input signal in response to the channel selection signal; and wherein the shift register includes: an input data selection unit for outputting inputted signals as the left input signal and the fight input signal in response to the channel selection signal; a direction selection unit for selecting one of the left input signal and the right input signal in response to a direction selection signal and for outputting the selected signal; a plurality of flip-flops, each receiving an output signal of the direction selection unit in synchronization with a clock signal; and a buffer unit for generating a first active signal and an inverted first active signal by buffering an output signal of the flip-flop to thereby activate a sampling register unit and for generating a second active signal to thereby activate a next shift register wherein each of said plurality of flip flops receives as an input an output of another one of said plurality of flip flops.