Patent ID: 8809134

Claim:
A method for manufacturing a semiconductor structure, comprising: a) providing a substrate and forming a fin ( 106 ) on the substrate, wherein the fin ( 106 ) comprises a central portion ( 106 b ) for forming a channel and an end portion ( 106 a ) for forming a source/drain region and a source/drain extension region; b) forming a gate stack to cover the central portion ( 106 b ) of the fin ( 106 ), wherein the Si or metal of the gate in the gate stack does not react with the metal forming the contact layer ( 108 ); performing light doping to form a source/drain extension region ( 110 a ) in the end portion ( 106 a ) of the fin; forming a spacer ( 206 ) on sidewalls of the gate stack; performing heavy doping to form a source/drain region ( 110 b ) in the end portion ( 106 a ) of the fin; c) removing the spacer ( 206 ) completely to maximally expose the source/drain extension region ( 110 a ); and d) forming a contact layer ( 108 ) on upper surfaces of the source/drain region ( 110 b ) and all of the source/drain extension region ( 110 a ).