Patent ID: 7712101

Claim:
A method of dynamically allocating access to a memory of a multithreaded processor, comprising the steps of: configuring a multithreaded processor to execute more than one thread simultaneously; requesting memory access from the more than one thread; deriving an automatic Microprocessor without Interlocked Pipeline Stages (MIPS) allocation (AMA) metric for each thread of the more than one thread from execution metrics for said each thread; deriving an in-page metric for said each thread from a page address of a last memory access and an in-page address required for an executing thread; determining the access to the memory based on the AMA metric and the in-page metric; wherein the page address of the last memory access is stored in a register and compared with the in-page address for the executing thread to derive the in-page metric; wherein the in-page metric is used to optimize a memory latency; and wherein the AMA metric is derived by the steps of taking a bit slice from each of two or more execution metrics and combining the bit slices to derive the AMA metric.