Patent ID: 7880264

Claim:
An integrated circuit arrangement comprising: a memory array having at least a first column of memory cells and a second column of memory cells, wherein the first and second column of memory cells are EEPROM cells; a first field effect transistor electrically connected to the memory cells in at least a section of the first column; a second field effect transistor electrically connected to the memory cells in at least a section of the second column; and an isolating trench isolating the first column of memory cells from the second column of memory cells; each of the first and second transistors having a gate area extending into the isolating trench; wherein the first and second field effect transistors are selection transistors and are configured to enable simultaneous selection of the memory cells in a column or a column section of the memory cells; the first field effect transistor and the second field effect transistor has a triple gate; wherein the first transistor haying the triple gate has two mutually opposite gate areas, the two mutually opposite gate areas of the first transistor are connected by a first central gate area; wherein the second transistor haying the triple gate has two mutually opposite gate areas, the two mutually opposite gate areas of the second transistor are connected by a second central gate area; and the first transistor has a first U-shaped channel and the second transistor has a second U-shaped channel.