Patent ID: 8634221

Claim:
A memory system comprising: a circuit board comprising a substrate having at least an upper surface and a lower surface; a package mounted on the upper surface of the circuit board and electrically interconnected with the circuit board; an interposer mounted on an upper surface of the package and electrically interconnected with the package; at least a first dynamic random access memory (DRAM) chip mounted on an upper surface of the interposer and electrically interconnected with the interposer; a memory controller chip mounted on the upper surface of the interposer and electrically interconnected with the interposer, wherein the memory controller chip and the first DRAM chip are electrically interconnected with each other via the interposer, and wherein the electrical interconnection between the first DRAM chip and the interposer and the electrical interconnection between the memory controller chip and the interposer provide a first Wide input/output (I/O) interface between the first DRAM chip and the memory controller chip, the first Wide I/O interface having a bit width that is equal to or greater than 256 bits; an integrated circuit (IC) chip electrically interconnected with the circuit board; and a serializer/deserializer (SerDes) interface interfacing the IC chip with the memory controller chip to allow the IC chip and the memory controller chip to communicate with each other via the SerDes interface, the IC chip comprising a first portion of the SerDes interface and the memory controller chip comprising a second portion of the SerDes interface, and wherein the first and second portions of the SerDes interface are electrically coupled to each other via electrical conductors of the circuit board.