Patent ID: 7876128

Claim:
A voltage sequence output circuit, comprising: a sequence control circuit comprising a first NOR gate and a negatively enabled tristate buffer; the first NOR gate comprising a plurality of input terminal and an output terminal, and the negatively enabled tristate buffer comprising an input terminal coupled to a power source, a negatively enabled terminal coupled to the negative output terminal of the first NOR gate, and an output terminal; and a plurality of voltage output circuits each comprising an input terminal, an output terminal, and a positively enabled tristate buffer connected between the input terminal and the output terminal thereof; the input terminal of the voltage output circuit is coupled to the input terminal of the first NOR gate; the positively enabled tristate buffer comprising an input terminal, an output terminal, and a positively enabled terminal coupled to the output terminal of the negatively enabled tristate buffer; wherein the positively enabled terminal of the positively enabled tristate buffer of the first voltage output circuit is coupled to the negative output terminal of the first NOR gate, the output terminal of the positively enabled tristate buffer of the ith (i≧1) voltage output circuit is coupled to the positively enabled terminal of the positively enabled tristate buffer of the adjacent i+1th voltage output circuit.