Patent ID: 8120977

Claim:
A test method for nonvolatile memory devices, the method comprising: selecting a specific operation mode among a command input mode, an address input mode, a read operation mode, or a write enable mode according to a signal inputted through an I/O pin of a plurality of I/O pins in a period in which a write enable signal that is generated in response to a reference clock supplied in a test mode is inactivated, wherein the command input mode is selected when a signal of a first level is inputted through the I/O pin at a first toggling time point of the clock, the address input mode is selected when the signal of the first level is inputted through the I/O pin at a second toggling time point of the clock, the read operation mode is selected when the signal of the first level is inputted through the I/O pin at a third toggling time point of the clock, and the write enable mode is selected when the I/O pin is sustained at a second level in a period in which the write enable signal is inactivated; activating the write enable signal or a read enable signal according to the selected operation mode; inputting a command signal, an address signal, or test data in the nonvolatile memory device through the I/O pin in a period in which the write enable signal is activated; and outputting the test data to a test device through the I/O pin in a period in which the read enable signal is activated.