Patent ID: 7692943

Claim:
A semiconductor storage device comprising: a plurality of bit-line pairs extending in a first direction, each bit-line pair being coupled to a respective Y switch of a plurality of Y switches, each Y switch of the plurality of Y switches being controlled by a respective control signal; a first word line extending in a second direction that intersects the first direction; a plurality of first memory cells each including a transistor formed in a first semiconductor area of a first conductivity type, said plurality of first memory cells being provided proximate to respective intersection points by between a corresponding pair of the plurality of bit-line pairs and the first word line; a plurality of first areas for well tap that are the first conductivity type, and that have impurity concentration higher than that of the first semiconductor area, said plurality of first areas for well tap being used to supply a well potential to the first semiconductor area, wherein: the plurality of first memory cells includes a first set of memory cells that are included in a plurality of fifth areas that are each located between two adjacent first areas for well tap among the plurality of first areas for well tap, the first memory cells of the first set of first memory cells that are included in the same fifth area of the plurality of fifth areas are each assigned a distinct address, and each bit of a plurality of bits included in data to be read out is read out from the first memory cells of the first set of memory cells included in a respective distinct fifth area of the plurality of fifth areas.