Patent ID: 8909849

Claim:
An apparatus comprising: a phase change memory device comprising a plurality of phase change memory storage elements; and control logic to control two or more set pipelines to serve memory accesses in a staggered manner, such that set operations of the memory accesses begin at different times, the control logic including reset pipeline logic to control one or more reset pipelines, wherein the reset pipeline logic causes a reset staggered period to pass between reset operations; and set pipeline logic distinct from the reset pipeline logic to control the two or more set pipelines to reduce peak power when performing the set operations, wherein the set pipeline logic causes a set staggered period to pass between set operations; wherein the control logic is operable to determine which set pipelines and which reset pipelines and how many are to be in use based at least on a set period, a reset period, and a set staggered period, and wherein the reset staggered period is less than the set staggered period and an amount of data processed during a reset period is greater than an amount of data processed during a set period.