Patent ID: 6909647

Claim:
A semiconductor memory comprising: a plurality of memory mats each formed with a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells, wherein, at a memory access, one of said plurality of memory mats is selected and one of said plurality of word lines in the selected memory mat is activated; a plurality of bit line selection lines coupled to said plurality of memory mats, wherein respective ones of the plurality of bit lines in said plurality of memory mats are selected when one of said plurality of bit line selection lines is activated; a spare bit line selection line coupled to said plurality of memory mats, wherein the respective spare bit lines in said plurality of memory mats are selected when said spare bit line selection line is activated; and a pair of comparison circuits each formed with memory means and an output coupled to said spare bit line selection line, the memory means of one of said pair of comparison circuits being stored with a first defect information indicative of one of the bit line selection lines associated with a first defect and indicative of one of said plurality of memory mats associated with said first defect, the memory means of another of said pair of comparison circuits being stored with a second defect information indicative of one of the bit line selection lines associated with a second defect and indicative of one of said plurality of memory mats associated with said second defect, wherein each of said pair of comparison circuits compares the defect information with input signals including address signals indicative of selections of the memory mats and indicative of selections of the bit line selection lines.