Patent ID: 7517806

Claim:
A method of forming pairs of parallel fin-type field effect transistors (FinFETs), said method comprising: forming a semiconductor layer on a substrate; forming a masking layer on said semiconductor layer so as to form a laminated structure with said masking layer being above and in contact with said semiconductor layer, said masking layer comprising a first dielectric material; patterning said masking layer so as to form a mandrel structure having substantially vertical sidewalls; forming a series of three layers of spacers on at least one of said sidewalls of said mandrel structure, said forming of said series comprising forming said series such that each of said three layers of spacers is above and in contact with said semiconductor layer and further such that said series comprises: an inner spacer adjacent to said at least one of said sidewalls, said inner spacer comprising a second dielectric material different from said first dielectric material; a middle spacer adjacent to said inner spacer, said middle spacer comprising said first dielectric material; and, an outer spacer adjacent to said middle spacer, said outer spacer comprising said second dielectric material; selectively removing said mandrel structure and said middle spacer only to expose regions of said semiconductor layer below said mandrel structure and said middle spacer and to leave said inner spacer and said outer spacer remaining on said semiconductor layer; patterning said semiconductor layer, using said inner spacer and said outer spacer as masks such that exposed regions of said semiconductor layer are removed, such that said inner spacer and said outer spacer remain intact and such that regions of said semiconductor layer protected by said inner spacer and said outer spacer remain on said substrate as a first fin and a second fin positioned adjacent and parallel to said first fin; defining a first channel region in said first fin and a second channel region in said second fin, wherein said first channel region and said second channel region are defined to form different type transistors; forming a common gate structure for said different type transistors over said first channel region of said first fin and over said second channel region of said second fin; doping portions of said first fin and said second fin not protected by said common gate structure with different type dopants to form, for said different type transistors, first source and drain regions in said first fin and second source and drain regions in said second fin; and insulating said first source and drain regions in said first fin from said second source and drain regions in said second fin.