Patent ID: 8045706

Claim:
A system of implementing the secure hash algorithm (SHA-1) for completing an 81-step SHA-1 computation in exactly 81 clock cycles, said system comprising: an addressable quad-channel output memory (QCOM) having one data input channel and multiple data output channels for simultaneously retrieving multiple data elements from different memory locations referenced by an address value; a SHA-1 Logic Core coupled to the multiple data output channels of the QCOM to receive necessary data for the 81-step SHA-1 computation; and a central control unit (CCU) coupled to both said QCOM and said SHA-1 Logic Core for controlling the 81-step SHA-1 computation and allowing an external system to access the 81-step SHA-1 computation; wherein the SHA-1 Logic Core comprises: a first synchronous registers set and a second synchronous registers set for storing the required computation values in the 81-step SHA-1 computation, wherein the second synchronous registers set is used to store the beginning value and the end value of a 160-bit hash value, and the first synchronous registers set is used to buffer intermediate computation values of the 160-bit hash value during the 81-step SHA-1 computation; a combination of asynchronous circuits for performing the logic and mathematic operations of each step of the 81-step SHA-1 computation on stored parameters within one single clock cycle; a counter circuit; a decoder/encoder circuit and a register used together with the counter circuit for performing tracking, counting, and controlling the 81-step SHA-1 computation; and wherein the quad-channel output memory comprises: an address decoder for decoding a 4-bit address signal and a write-enable signal to create a word-line-write signal with 16-bit according to the 4-bit address signal; a memory array having sixteen 32-bit wide input word-lines all connected to a 32-bit wide data input channel, a 16-bit word-line-write input, a clock input, and a set of sixteen 32-bit wide output word-lines, wherein the 16-bit word-line-write input is connected to the output of the address decoder for receiving the word-line-write signal from the address decoder, and the clock input is connected to a clock signal, and the set of sixteen 32-bit wide output word-lines is commonly inputted to four 32-bit wide 16-input multiplexers which define the multiple data output channels of said QCOM; and at least three 4-bit adder circuits each having a first input connected to the 4-bit address signal to receive said address value, a second input hardwired to an offset value, and a 4-bit output connected to a 4-bit select input of one of the 32-bit wide 16-input multiplexers for causing the 32-bit wide 16-input multiplexer to output, to a corresponding input of the SHA-1 Logic Core, a 32-bit word stored in the memory array at an address defined by the address value plus the offset value.