Patent ID: 7911004

Claim:
A semiconductor device comprising: a semiconductor substrate, a device isolation area that isolates a surface portion of said semiconductor substrate into a P-type area and an N-type area; a gate electrode line that extends on said device isolation area, P-type area and N-type area, and is insulated from said P-type area and N-type area by a gate insulation film; source/drain diffused regions formed in each of said P-type area and N-type area to sandwich therebetween said gate electrode line, wherein: said gate electrode line includes a first silicide region formed on said N-type area and including a silicide of metal M 1 , a second silicide region formed on said P-type area and including a silicide of metal M 2 , and an impurity-doped silicon region formed on said device isolation area to separate said first silicide region and said second silicide region from each other.