Patent ID: 8518836

Claim:
A method for forming a pattern during semiconductor fabrication, comprising: forming a first photo resist (PR) region at a first PR location; forming a second PR region at a second PR location, a first gap between the first PR region and the second PR region: the first gap associated with a second spacer location, a first sub-gap, and a third spacer location; the first PR location between a first spacer location and the second spacer location; the second spacer location between the first PR location and the first sub-gap; the first sub-gap between the second spacer location and the third spacer location; the third spacer location between the first sub-gap and the second PR location; and the second PR location between the third spacer location and a fourth spacer location; forming a spacer region at least one of: above at least some of at least one of the first PR region or the second PR region; within at least some of at least one of the first spacer location, second spacer location, third spacer location, or fourth spacer location; or within at least some of the first sub-gap; removing at least some of the spacer region to form at least one of a first spacer in the first spacer location, a second spacer in the second spacer location, a third spacer in the third spacer location, or a fourth spacer in the fourth spacer location; removing at least some of at least one of the first PR region or the second PR region; filling at least some of at least one of the first PR location, the first sub-gap, or the second PR location with a block co-polymer (BCP), the BCP comprising a first polymer and a second polymer; and removing at least some of the second polymer to form a pattern comprising the first polymer and the spacer region.