Patent ID: 7417304

Claim:
An electronic device comprising: a substrate; an element formed in a chip region of the substrate; a multilayer structure composed of a plurality of interlayer insulating films formed on the substrate; a passivation film formed on the multilayer structure composed of the plurality of interlayer insulating films; a first seal ring formed to contact the substrate and to extend through the multilayer structure composed of the plurality of interlayer insulating films which is located in a peripheral portion of the chip region and to continuously surround the chip region; and a stress absorbing wall formed to contact the substrate and to extend through the multilayer structure composed of the plurality of interlayer insulating films which is located outside the first seal ring and to discretely surround the first seal ring, wherein a second seal ring is provided outside the first seal ring so as to surround the first seal ring, the passivation film has an opening on only one of the first seal ring or on the second seal ring and not the other, and a cap layer is formed in the opening.