Patent ID: 7947572

Claim:
A method of manufacturing a silicon on insulator SOI wafer having a silicon germanium SiGe layer in contact with said insulator, comprising: epitaxially growing a first SiGe layer, a silicon layer, and a second SiGe layer in sequence on a first substrate; forming an insulating layer on the second SiGe layer; implanting impurity ions into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region; bonding a second substrate to the insulating layer on the first substrate; and separating the first substrate along the impurity implantation region and removing the first substrate, wherein the epitaxially growing the first SiGe layer comprises epitaxially growing the first SiGe layer to a thickness of 10-50 Å, and the implanting impurity ions comprises implanting the impurity ions at a depth of 50-100 Å below the first SiGe layer.