Patent ID: 8383456

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring substrate having an upper surface on which a plurality of bonding leads are formed, and a lower surface on which a plurality of lands are formed, wherein the lower surface opposes to the upper surface; the wiring substrate includes a core material having an upper surface positioned on the upper surface side of the wiring substrate and a lower surface positioned on the lower surface side of the wiring substrate; the wiring substrate is a multilayer wiring substrate in which a plurality of wiring layers and a plurality of insulating layers are alternately formed on both the upper surface side of the core material and the lower surface side of the core material; the bonding leads are formed of part of the uppermost wiring layer of the wiring layers; the lands are formed of part of the lowermost wiring layer of the wiring layers; the core material is a first insulating layer containing fiber and resin; the insulating layers include second insulating layers containing fiber and resin, and third insulating layers; content of fiber in each of the third insulating layers is smaller than that of each of the first insulating layer and the second insulating layers; the second insulating layers are formed on both the upper surface side of the core material and the lower surface side of the core material; the third insulating layers are formed on both the upper surface side of the core material and the lower surface side of the core material via the second insulating layers; both the uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers, respectively; three of the wiring layers are formed on both the upper surface side of the core material and the lower surface side of the core material, the thickness of the first insulating layer is larger than the thickness of each of the second insulating layers; and the thickness of each of the second insulating layers is larger than the thickness of each of the third insulating layers, (b) after the step (a), mounting a semiconductor chip over the upper surface of the wiring substrate via a plurality of bump electrodes such that a main surface of the semiconductor chip on which a plurality of pads are formed faces the upper surface of the wiring substrate, and electrically connecting the pads of the semiconductor chip with the bonding leads of the wiring substrate through the bump electrodes; (c) after the step (b), supplying a resin between the main surface of the semiconductor chip and the upper surface of the wiring substrate; and (d) after the step (c), coupling a plurality of external terminals to the lands of the wiring substrate, respectively.