Patent ID: 8415790

Claim:
A semiconductor package, comprising: a base material, having a first surface, a second surface, at least one groove and at least one through via structure, the groove penetrating the first surface and the second surface, and the through via structure being disposed in the groove and exposed on the first surface and the second surface; a first capacitor, disposed on the first surface of the base material and comprising a first lower electrode, a first dielectric layer and a first upper electrode, the first lower electrode being disposed on the first surface of the base material, the first dielectric layer being disposed on the first lower electrode, and the first upper electrode being disposed on the first dielectric layer; a first protective layer, encapsulating the first capacitor, the first protective layer comprising a plurality of first openings, and the first openings exposing the through via structure, part of the first lower electrode and part of the first upper electrode; a first metal layer, disposed on the first protective layer, comprising a first inductor, a first interconnection metal, a second interconnection metal and a third interconnection metal, wherein the first interconnection metal directly contacts the through via structure, the second interconnection metal directly contacts the first lower electrode, and the third interconnection metal directly contacts the first upper electrode; and a second protective layer, encapsulating the first inductor.