Patent ID: 6883132

Claim:
A system comprising: (A) a general purpose DMA controller; (B) a linear feedback shift register, the linear feedback shift register being coupled to receive data from the general purpose DMA controller, the linear feedback shift register comprising a plurality of programmable polynomial building blocks, the plurality of program able polynomial building blocks being connected in a sequence with ach building block corresponding to a respective exponential term in a polynomial of a polynomial equation implemented by the linear feedback shift register, each building block comprising (1) a feedback gate, the feedback gate being coupled to an output of an adjacent polynomial building block in the sequence and to a non-adjacent polynomial building block in the sequence, (2) a multiplexer, the multiplexer being coupled to an output of the feedback gate and to the output of the adjacent polynomial building block in the sequence, the multiplexer determining whether the flip flop receives an input from an output of the feedback gate or from the output of the adjacent polynomial building block, (3) a flip flop, the flip flop having an input coupled to an output of the multiplexer, and wherein, when the flip flop receives an input from the output of the feedback gate, the respective exponential term is included in die polynomial, wherein, when the flip flop receives an input from the immediately-preceding flip flop, the respective exponential term is not included in the polynomial, and wherein the multiplexers of each of the programmable polynomial building blocks are programmable to determine which of the exponential terms are included in the polynomial of the polynomial equation.