Patent ID: 8912655

Claim:
A semiconductor memory device comprising: a lower circuit layer comprising a substrate and a first lower electrode layer and a second lower electrode layer located on the substrate; an upper circuit layer comprising a first wiring formed above the lower circuit layer and extending in a predetermined direction, a second wiring being perpendicular to the first wiring, a third wiring formed above the second wiring and extending in the predetermined direction, and memory cell layers disposed between the first wiring and the second wiring and disposed between the second wiring and the third wiring; and a first contact layer connecting the first lower electrode layer and the third wiring outside a memory cell array in which the memory cell layers are formed, a second contact layer connecting the second lower electrode layer and the first wiring outside the memory cell array, a first connection portion covering a part of the first lower electrode layer outside the memory cell array in a stacking direction of the first wiring and the second wiring, and formed in the third wiring, a second connection portion covering a part of the second lower electrode layer outside the memory cell array in the stacking direction, and formed in the first wiring, a first etching suppressing portion formed above the first connection portion, and a second etching suppressing portion formed at a height from the substrate which is between the first connection portion and the second lower electrode layer, the first contact layer being connected to an upper face and a side face of the first connection portion and the first lower electrode layer, and the second contact layer being connected to an upper face and a side face of the second connection portion and the second lower electrode layer.