Patent ID: 8012839

Claim:
A method for fabricating a transistor, the transistor characterized by a channel length and a channel width, the method comprising: providing a substrate having an active substrate region defined by isolation regions, the active region defined by a lateral channel length direction and a lateral channel width direction substantially orthogonal to the lateral channel length direction; forming a hardmask overlying the substrate and forming an opening in the hardmask exposing a portion of the active substrate region; forming an epitaxial region in the opening spanning the active substrate region and projecting above the substrate, the epitaxial region having a relatively long lateral dimension in the channel length direction and a relatively short lateral dimension in the channel width direction, wherein a lattice constant of the epitaxial region differs from a lattice constant of the substrate, such that strain is induced in regions of the substrate proximal to the epitaxial region; forming a gate dielectric layer overlying the epitaxial region; and forming a gate electrode strip overlying the gate dielectric layer, the gate electrode strip having a relatively long lateral dimension substantially orthogonal to the relatively long lateral dimension of the epitaxial region.