Patent ID: 7136297

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a pair of bit lines connected to a column of the memory cells in the memory cell array; a word line connected to a row of the memory cells in the memory cell array; a memory cell power supply terminal for supplying a power supply potential to the memory cells in the memory cell array; a control circuit for controlling operation of the memory cells in the memory cell array; and a control circuit power supply terminal for supplying a power supply potential to the control circuit, the control circuit power supply terminal being electrically separated from the memory cell power supply terminal, wherein each of the memory cells includes a pair of first and second inverters including first and second internal nodes, respectively, each one of the first and second inverters further including a resistor and a drive transistor connected in series via the first or second internal node and receiving an output from the other inverter, and first and second access transistors, one of which is interposed between one of the first and second internal nodes and one of the bit lines and the other of which is interposed between the other one of the first and second internal nodes and the other bit line, and wherein at startup, a power supply potential is supplied from the control circuit power supply terminal to the control circuit and then a power supply potential is supplied from the memory cell power supply terminal to the memory cell array.