Patent ID: 6847577

Claim:
A semiconductor memory, comprising: a memory cell array including a plurality of blocks separated in column direction every M word lines, the separated blocks-sharing N+1 virtual ground wires, which are selectively subject to ground-connection in response to address operation and N main bit lines, each of which is placed between the adjacent two of the virtual ground wires and selectively subject to sensing-connection, the separated blocks being adjacent one after another in column direction with the adjacent two in symmetric relationship around an imaginary line separating the as adjacent two blocks, each of the separated blocks including diffusion wires which are equi-distant one fourth the virtual ground wires are, and memory cells in M rows and in 4N columns grouped as a memory cell unit, each of the separated blocks including, on one end side of the diffusion wires, a bit column select line and, per each of the memory cell units, three bit column select transistors, which use a middle diffusion wire and the adjacent two diffusion wires of a set of diffusion wires provided for the memory cell unit as drains or sources, and the bit column select line as gates, each of the three bit column select transistors having diffusion layer connected to one of the main bit lines, each of the separated blocks including, on the other end side of the diffusion wires, a ground column select line and, per each of the memory cell units, three ground column select transistors, which use a boundary diffusion wire of the set of diffusion wires and the adjacent two diffusion wires as drains or sources, and the ground column select line as gates, each of the three ground column select transistors having diffusion layer connected to one of the virtual ground wires, inter-block bit wires, each connecting the middle diffusion wire for one of the memory cell units of a first block of the separated blocks and the middle diffusion wire for one of the memory cell units of an adjacent second block lying on the other end side of the diffusion wires of the first block, the first block and the adjacent second block having halves of the inter-block bit wires, respectively, inter-block ground wires, each connecting the boundary diffusion wire for the one memory cell unit of the first block and the boundary diffusion wire for the one memory cell unit of an adjacent third block lying on the one end side of the diffusion wires of the first block, the first block and the adjacent third block having halves of the inter-block ground wires, respectively.