Patent ID: 6838719

Claim:
A DRAM cell capacitor comprising: a semiconductor substrate having a planar first insulating layer thereover, said first insulating layer having a buried contact plug to an active area of said semiconductor substrate; a cup-shaped storage node electrically connected to said contact plug; said cup-shaped storage node having a bottom portion with a predetermined length and thickness and lateral edges, and a pair of substantially vertical portions having a predetermined height and thickness, lateral edges of each said vertical portions being aligned with one of lateral edges of the bottom portion, respectively, said bottom portion being disposed over said contact plug and overlapping a portion of said first insulating layer outside of said contact plug; a planar second insulating layer formed over said first insulating layer and on lateral edges of said vertical portions of said storage node with a relatively low height than that of said vertical portions; and a rough layer on inner and outer surfaces of said cup-shaped storage node; wherein said second insulating layer is made by laminating a silicon nitride layer and an HTO layer so that both said silicon nitride layer and said HTO layer provide lateral support for said vertical portions of said storage node; and wherein said silicon nitride layer has a thickness of about 70 Å and said HTO layer has a thickness in a range between about 500 Å and 1500 Å.