Patent ID: 7615449

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls of the active region; forming a hard mask layer defining a recess gate region over the semiconductor substrate and the device isolation structure; forming recess channel spacers at the sidewalls of the recess gate region; etching the semiconductor substrate exposed at the bottom of the recess gate region by using the recess channel spacers and the hard mask layer as an etching mask to form a recess that exposes a portion of the device isolation structure, wherein the recess includes a recess channel region having a vertical Silicon-on-Insulator (“SOI”) channel structure formed at a sidewall of the device isolation structure in a longitudinal direction of the gate region; removing the recess channel spacers and the hard mask layer to expose the semiconductor substrate; forming a gate insulating film over the exposed semiconductor substrate and the exposed portion of the device isolation structure; and forming a gate structure including a stacked structure of a gate hard mask layer pattern and a gate electrode filling up the recess channel region over the gate insulating film of the gate region.