Patent ID: 8005176

Claim:
A systolic polynomial nonlinear filter, comprising: a clocked register for receiving an input data sample; a finite impulse response (FIR) module receiving the input data sample from the clocked register, the FIR module having a FIR filter for producing a FIR-filtered data sample from the input data sample; and a pipeline of clocked delay-multiplication modules including a first delay-multiplication module in communication with the FIR module to receive the input data sample and the FIR-filtered data sample, the first delay-multiplication module having a delay module in communication with a multiplication module, the delay module having a first input terminal for receiving the input data sample from the FIR module, a second input terminal for receiving the FIR-filtered data sample from the FIR module, and a programmable delay circuit for delaying the input data sample, the multiplication module having a first input terminal for receiving the delayed input data sample from the delay module, a second input terminal for receiving the FIR-filtered data sample from the delay module, and a multiplier for multiplying the delayed input data sample with the FIR-filtered data sample.