Patent ID: 7498248

Claim:
A method of compensating for an alignment error during fabrication of structures on semiconductor substrates, the method comprising: forming a conductive pattern structure at a first position on a first semiconductor substrate, the conductive pattern structure including first conductive patterns and second conductive patterns, the first conductive patterns extending in a first direction and arranged substantially parallel to one another, the second conductive patterns extending in a second direction and arranged substantially parallel to one another, the first conductive patterns intersecting and connecting to the second conductive patterns and defining openings bounded by the first and second conductive patterns; forming a first conductive contact structure at a second position on the first semiconductor substrate that at least partially overlaps the conductive pattern structure, the first conductive contact structure including a plurality of conductive contacts spaced apart from one another, at least some of the conductive contacts arranged within the defined openings bounded by the first and second conductive patterns; determining whether the first conductive contact structure is electrically connected to the conductive pattern structure; and forming a second conductive contact structure having substantially the same shape as the first conductive contact structure at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure, wherein the second semiconductor substrate has substantially the same shape as the first semiconductor substrate.