Patent ID: 7227767

Claim:
A memory comprising: a semiconductor substrate including an x-direction driver set; and a y-direction driver set; a plurality of x-direction conductive array lines formed above the semiconductor substrate and above both driver sets and being electrically connected to the x-direction driver set, the electrical connection occurring substantially in a middle of the x-direction conductive array lines; an array cut in the plurality of x-direction conductive array lines, the array cut being where two contiguous x-direction conductive array lines are spaced further apart than other contiguous x-direction conductive array lines; a plurality of memory plugs formed above the semiconductor substrate and above the plurality of x-direction conductive array lines and in electrical contact with the plurality of x-direction conductive array lines; and a plurality of y-direction conductive array lines formed above the plurality of memory plugs and being electrically connected to the y-direction driver set, the electrical connection occurring over the array cut and being substantially in a middle of the y-direction conductive array lines.