Patent ID: 8125817

Claim:
A nonvolatile storage device comprising: a substrate; first wires formed parallel to each other on said substrate; second wires formed above said first wires so as to be parallel to each other on a plane parallel to a main plane of said substrate and to three-dimensionally cross said first wires; a memory cell array which includes variable resistance elements each of which (i) is provided to correspond to one of cross-points between said first wires and said second wires, (ii) is interposed between corresponding ones of said first wires and said second wires, and (iii) whose resistance state reversibly changes between a low resistance state and a high resistance state based on a polarity of a voltage applied between the corresponding ones of said first wires and said second wires, the cross-points being three-dimensional; a selection circuit which (i) includes: a first driving circuit provided with transistors each of which applies a predetermined voltage to a corresponding one of said first wires; and a second driving circuit provided with transistors each of which applies a predetermined voltage to a corresponding one of said second wires, and (ii) selects at least one of said variable resistance elements from said memory cell array, using said first driving circuit and said second driving circuit; a substrate bias circuit which applies a bias voltage to said substrate on which said transistors provided to said first driving circuit and said second driving circuit are formed; and a write circuit which provides an electrical signal for writing, to said variable resistance element selected by said selection circuit, wherein each of said transistors provided to said first driving circuit and said second driving circuit is formed in a region of a first conductivity type within said substrate and includes a first diffusion region of a second conductivity type having reverse polarity to the first conductivity type, a gate, and a second diffusion region of the second conductivity type, and when the electrical signal for writing is provided by said write circuit to said variable resistance element selected by said selection circuit, said substrate bias circuit applies the bias voltage to said region of the first conductivity type in said substrate on which at least one of said transistors provided to said first driving circuit and said transistors provided to said second driving circuit is formed, the bias voltage being applied in a forward direction with respect to said first diffusion region and said second diffusion region.