Patent ID: 8693266

Claim:
A semiconductor memory device comprising: a first voltage-to-current circuit which comprises a reference cell configured to convert a bias voltage to a reference current; a first resistor connected to the first voltage-to-current circuit for generating a reference voltage based on the reference current; a second voltage-to-current circuit configured to convert a control voltage to a first current and a second current whose value is less than the value of the first current; a second resistor connected to the second voltage-to-current circuit for generating a first voltage based on the value of the first current; a third resistor connected to the second voltage-to-current circuit for generating a second voltage based on the value of the second current; a first comparator configured to compare the reference voltage with the first voltage, and output a first comparison signal; a second comparator configured to compare the reference voltage with the second voltage, and output a second comparison signal; and a trimming circuit configured to trim the reference cell based on the first and second comparison signals; wherein the resistance of the second resistor is substantially equal to that of the third resistor; and wherein a precision resistor is disposed outside the semiconductor memory device, and the second voltage-to-current circuit generates the first current and the second current based on the value of the control voltage and the resistance of the precision resistor.