Patent ID: 7249010

Claim:
A method of estimating the susceptibility to single event upsets (SEUs) of a design implemented in a field programmable gate array (FPGA), the method comprising: determining resources of the FPGA used in the design; selecting a first one of the resources used in the design; determining a number of configuration bits associated with the first resource; setting a number of care bits to the number of configuration bits associated with the first resource; repeating, for each additional resource used in the design, the steps of: selecting another one of the resources used in the design, determining a number of configuration bits associated with the selected resource, setting a number of resource bits to the number of configuration bits associated with the selected resource, and setting the number of care bits to the previous number of care bits plus the number of resource bits; setting an SEU Probability Impact (SEUPI) value to the number of care bits divided by a total number of configuration memory cells in the FPGA; and outputting the SEUPI value as an estimated SEU susceptibility for the design implemented in the FPGA.