Patent ID: 7633818

Claim:
A semiconductor memory device, comprising: a memory cell array which includes a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells placed at crossing positions of the word lines and the lines, and a plurality of sense amplifiers connected to the bit line pairs for amplifying a potential difference of the bit line pair; a bit line transfer control circuit for controlling a bit line transfer gate which connects the bit line pair to the corresponding sense amplifier; and a word line select circuit for selecting the word line, wherein in a test mode, the word line select circuit selects a first word line corresponding to a first memory cell of a first bit line connected to a first sense amplifier among the plurality of sense amplifiers, the first sense amplifier is activated, and the first bit line is amplified to a first or second potential, then in a state where the bit line transfer control circuit disconnects the first bit line from the first sense amplifier, the word line select circuit multiple-selects a second word line of a second memory cell which is coupled to the first bit line and stores data opposite to the first memory cell, to set the potential of the first bit line to an intermediate potential, and returns the first word line to a non-select state to write the intermediate potential in the first memory cell, then the data in the first memory cell is read after precharging the first bit line.