Patent ID: 8799699

Claim:
A data processing system comprising: a plurality of master devices configured to output data transfer requests and speed grade signals indicating data transfer speeds; a plurality of arbiters each configured to arbitrate the transfer requests and the speed grade signals from the plurality of master devices; a plurality of clock enable generation circuits each configured to generate a clock enable signal, a ratio of a period of a valid level of the clock enable signal varying in accordance with one of the speed grade signals arbitrated by the arbiters; and a plurality of slave devices each provided for a corresponding one of the arbiters and a corresponding one of the clock enable generation circuits, and each configured to operate upon receiving a clock signal when a corresponding clock enable signal is at the valid level and to transfer data according to one of the transfer requests arbitrated by the corresponding one of the arbiters, wherein each of the plurality of master devices generates the speed grade signals according to a transfer mode of data with each process of generating the transfer requests.