Patent ID: 7949920

Claim:
A System-on-Chip (SOC) comprising: a top-level (glue) logic; a plurality of cores in communicating relationship with each other via the glue logic; a set of memory elements (flip-flops) in each core, wherein the set of flip-flops includes scan flip-flops in one or more of the plurality of cores, wherein the scan flip-flops is a subset of the set of flip-flops that are connected within a core scan chain; and a scan router logic coupled to the set of flip-flops that determines core scan segments from the core scan chain, wherein each core scan segment substantially include the scan flip-flops that require testing each intermediate (partial) residual test mode interaction in the SoC, and wherein the scan router logic reconfigures the determined core scan segments to form a reconfigured (reduced) core scan segment model based on connectivity and interaction within and among the plurality of cores.