Patent ID: 8453094

Claim:
A method for defining a layout for a portion of a given semiconductor chip level, comprising: (a) operating a computer to define a global placement grid for a portion of a given of a semiconductor chip, wherein the global placement grid is defined by a set of gridpoints, wherein each gridpoint in the set of gridpoints is defined by a first coordinate as measured in a first direction and a second coordinate as measured in a second direction, the first and second directions perpendicular to each other, and wherein the first coordinates of the set of gridpoints are equally spaced apart in the first direction; (b) operating the computer to identify all first direction connection coordinates associated with the portion of the given level of the semiconductor chip, wherein each first direction connection coordinate is a first coordinate of the set of gridpoints of the global placement grid that is spatially coincident with a first coordinate of an allowed contact location in a contact level of the semiconductor chip, wherein the allowed contact location corresponds to a location at which a contact structure is allowed to be positioned to physically connect with a structure in the given level of the semiconductor chip, and wherein the contact structure is any of a diffusion contact, a gate contact, and a via; (c) operating the computer to define a subgrating for the portion of the given level of the semiconductor chip as a set of the identified first direction connection coordinates that are evenly spaced apart such that a spacing between adjacent first direction connection coordinates of the subgrating is at least as large as a minimum spacing required to support a common run length of layout shapes positioned on the adjacent first direction connection coordinates of the subgrating; (d) operating the computer to repeat operation (c) until each of the identified first direction connection coordinates is part of at least one subgrating for the portion of the given level of the semiconductor chip; and (e) operating the computer to place layout shapes of electrically conductive wires in alignment with the first direction connection coordinates of the defined subgratings such that each layout shape is placed in accordance with any one subgrating.