Patent ID: 8713217

Claim:
A computer system, comprising: a master device which includes a first register for storing a first process ID associated with a software process number and which transmits the first process ID onto a system bus when generating a transaction; and a slave device which holds a second process ID for permitting access and which accepts the transaction when the first process ID and the second process ID meet a predetermined condition, wherein the slave device includes a determination section for comparing the first process ID and the second process ID with each other and permitting the access only when the first process ID and the second process ID coincide with each other, wherein the determination section includes a comparison section for comparing the first process ID and the second process ID with each other and a decoder for receiving a permission signal only when the first process ID and the second process ID coincide with each other in a comparison result, and wherein the decoder determines to correctly respond to the transaction and permits the access when the address to be accessed that has been outputted to the address bus is included in an address range assigned to the slave device and the decoder receives the permission signal from the comparison section.