Patent ID: 8686885

Claim:
A semiconductor integrated circuit device comprising: a first analog circuit which outputs a first analog signal and a second analog signal differing in phase from the first analog signal; a first A/D converter which receives the first analog signal from the first analog circuit and outputs a first digital signal; a second A/D converter which receives the second analog signal from the first analog circuit and outputs a second digital signal; a digital processing circuit which receives the first and second digital signals from the first and second A/D converters and digitally processes the first and second digital signals received; a mode setting information storing circuit for storing mode information; and a correction coefficient storing circuit which stores correction coefficients for the first and second A/D converters, wherein, when a first mode is set in the mode setting information storing circuit, a first correction coefficient for a first digital correction processing and a second correction coefficient for a second digital correction processing are calculated by having a first test signal inputted to both the first and second A/D converters, and wherein, when a second mode is set in the mode setting information storing circuit, the first and second analog signals are outputted from the first analog circuit, the first A/D converter converts the first analog signal into the first digital signal by subjecting the first analog signal to the first digital correction processing using the first correction coefficient stored in the correction coefficient storing circuit, and the second A/D converter converts the second analog signal into the second digital signal by subjecting the second analog signal to the second digital correction processing using the second correction coefficient stored in the correction coefficient storing circuit.