Patent ID: 7323278

Claim:
A method of fabricating an integrated circuit, comprising: (a) generating a photomask level design of an integrated circuit design of said integrated circuit, said photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of said photomask level design between adjacent integrated circuit element shapes, said designated regions large enough to require placement of fill shapes between said adjacent integrated circuit elements based on fill shape rules, said fill shapes not required for the operation of said integrated circuit; (c) placing one or more monitor structure shapes of a monitor structure in at least one of said designated regions, said monitor structure not required for the operation of said integrated circuit; (d) placing fill shapes in said designated regions of said photomask design level, said fill shapes not connected to said multiplicity of integrated circuit element shapes or to said one or more monitor structure shapes; (e) generating a mask data set from said photomask level design; and (f) using said mask data set to form a pattern on a wafer in order to fabricate a physical level of said integrated circuit.