Patent ID: 7579904

Claim:
A semiconductor memory device comprising: reference voltage generation means for generating a first reference voltage and a second reference voltage as control signals for internal voltage supply; first internal voltage generation means for generating a first internal voltage of a desired level in response to said first reference voltage from said reference voltage generation means; enable signal generation means for generating an enable signal by performing a logical operation in response to an active control signal indicative of an active mode and a refresh control signal indicative of a refresh mode; reference voltage transfer means responsive to the enable signal resulting from the logical operation of the active control signal indicative of the active mode and the refresh control signal indicative of the refresh mode and said first and second reference voltages from said reference voltage generation means, for transferring said first reference voltage when said memory device is in said active mode and said second reference voltage when said memory device is in any other mode including said refresh mode; second internal voltage generation means responsive to an output voltage from said reference voltage transfer means for generating a second internal voltage of the same level as that of said first internal voltage if the output voltage is said first reference voltage and a third internal voltage of a level lower than that of said first internal voltage if the output voltage is said second reference voltage; a row path and control logic supplied to said first internal voltage; and a column path and control logic and a data path and control logic supplied to said second internal voltage in said active mode, said third internal voltage in said refresh mode.