Patent ID: 8411695

Claim:
A system comprising: a first circuit board to: identify, when a second circuit board is inserted into a device connected to the first circuit board, whether the second circuit board, communicating with the first circuit board via a communication bus formed by a plurality of communication lines, is designed to communicate using a synchronous bus protocol or an asynchronous bus protocol by detecting an initial communication pattern; communicate with the second circuit board using the synchronous bus protocol when the second circuit board is designed to communicate using the synchronous bus protocol, when communicating using the synchronous bus protocol, the first circuit board being to: communicate with the second circuit board using all of the plurality of communication lines forming the bus, and configure a multiplexer of a multi-interface bus logic associated with the first circuit board to receive a clock signal from an oscillator; and communicate with the second circuit board using the asynchronous bus protocol when the second circuit board is designed to communicate using the asynchronous bus protocol, when communicating using the asynchronous bus protocol, the first circuit board being to: communicate with the second circuit board using a subset of the plurality of communication lines forming the bus, and configure the multiplexer of the multi-interface bus logic associated with the first circuit board to receive a second, different clock signal from a phase locked loop.