Patent ID: 8345504

Claim:
A Random Access Memory (RAM) comprising: a plurality of cells arranged in a column and coupled to a bit-line, each cell having a first power node, a second power node, a bit node and comprising: a first inverter with a supply source terminal, an input terminal and an output terminal respectively coupled to the first power node, a second data storage node and a first data storage node; a second inverter with a supply source terminal, an input terminal and an output terminal respectively coupled to the second power node, the first data storage node and the second data storage node; a pass-gate transistor with a terminal coupled to the bit node and an other terminal coupled to one of the first data storage node and the second data storage node; and a power controller having a supply node coupled to the first power nodes of the plurality of cells and comprising: a power-switch coupled to the bit-line and the supply node determining whether to connect the supply node to an operation voltage according to a voltage of the bit-line.