Patent ID: 6987311

Claim:
A thin film transistor liquid crystal display (TFT-LCD), the TFT-LCD comprising: at least one thin film transistor, the thin film transistor comprising: a first metal layer of a first pattern being formed in a transistor area on a surface of a substrate; a gate insulating layer of a first pattern, a light shielding layer of a first pattern, a semiconductor layer of a first patter, a doped silicon layer of a first pattern and a second metal layer of a first pattern being sequentially stacked on the first metal layer of the first pattern; a channel area separating both the second metal layer of the first pattern and the doped silicon layer of the first pattern into two sides respectively used as a source electrode and a drain electrode; a passivation layer of a first pattern covering both the second metal layer of the first pattern and the channel area, and a first contact hole being formed in the passivation layer of the first pattern; and a transparent conductive layer of a first pattern covering the passivation of the first pattern positioned above the drain electrode, and the transparent conductive layer of the first pattern being electrically connected with the drain electrode through the first contact hole; at least one capacitor, the capacitor comprising: a first metal layer of a second pattern being formed in a capacitor area on the surface of the substrate; a gate insulating layer of a second pattern, a light shielding layer of a second pattern, a semiconductor layer of a second pattern, a doped silicon layer of a second pattern and a second metal layer of a second pattern being sequentially stacked on the first metal layer of the second pattern; a passivation layer of a second pattern covering the second metal layer of the second pattern, and a second contact bole being formed in the passivation layer of the second pattern; and a transparent conductive layer of a second pattern covering the passivation layer of the second pattern, and the transparent conductive layer of the second pattern being electrically connected with the second metal layer of the second pattern through the second contact hole; at least one conductive line, the conductive line comprising: a gate insulating layer of a third pattern, a light shielding layer of a third pattern, a semiconductor layer of a third pattern, a doped silicon layer of a third pattern and a second metal layer of a third pattern being sequentially stacked on the surface of the substrate in a conductive line area; a passivation layer of a third pattern covering the second metal layer of the third pattern, and a third contact hole being formed in the passivation layer of the third pattern; and a transparent conductive layer of a third pattern covering the passivation layer of a third pattern, and the transparent conductive layer of the third pattern being electrically connected with the second metal layer of the third pattern through the third contact hole.