Patent ID: 7821350

Claim:
A phase-locked loop comprising: a clock output; a plurality of oscillator complexes operable to generate output signals; an output selector circuit configured to selectively couple an output signal of a first oscillator complex of the plurality of oscillator complexes to the clock output; a frequency selector circuit configured to change a gross output frequency of the first oscillator complex from a first gross frequency range to a second gross frequency range while unlocked from a feedback path in response to a desired operating frequency of the output signals being within the second gross frequency range and wherein the gross output frequency of the first oscillator complex is changed while the output signal of the first oscillator complex remains coupled to the clock output; and a switch configured to selectively couple the first oscillator complex to the feedback path, wherein a locked output results when the output selector circuit couples the output signal of the first oscillator complex to the clock output and the switch couples the first oscillator complex to the feedback path, and wherein an unlocked output results when the output selector circuit couples the output signal of the first oscillator complex to the clock output and the switch de-couples the first oscillator complex from the feedback path.