Patent ID: 8742791

Claim:
An apparatus comprising circuitry that includes a delay evaluation section that: receives first and second signals; stores delay information representing an expected time delay from an occurrence of the first signal to a point in time corresponding approximately to an expected occurrence of the second signal; and responds to an occurrence of the first signal by: waiting for a time interval equivalent to the expected time delay; evaluating the second signal at approximately the end of the time interval; and adjusting the stored delay information if the second signal occurred outside a time window associated with the end of the time interval; wherein the delay evaluation section includes a state machine that: carries out the evaluating by determining an actual occurrence of the second signal with respect to the time window; and thereafter generates an adjustment signal, the adjusting of the stored delay information is carried out as a function of the adjustment signal; and wherein the adjustment signal specifies the stored delay information is to be one of incremented or decremented.