Patent ID: 7373289

Claim:
A method for simulating a circuit having a hierarchical data structure, comprising: representing the circuit as a hierarchically-arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph; the hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network; wherein the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches; determining a first admittance matrix representing the first electrical network and a second admittance matrix representing the second electrical network respectively; comparing corresponding elements of the first and second admittance matrices; identifying the first and second electrical networks as electrically isomorphic networks in response to the corresponding elements of the first and second admittance matrices are substantially equivalent within a predetermined tolerance range; representing the first and second electrical networks with a single electrically isomorphic network in response to the first and second electrical networks are determined to be electrically isomorphic networks; and simulating the first and second electrical networks using the single electrically isomorphic network.