Patent ID: 8302083

Claim:
An architecture comprising: a controller, the controller configured to receive a microprogram, the microprogram configured for performing at least one of hierarchical or a sequence of polynomial computations; an arithmetic logic unit (ALU) communicably coupled to the controller, the ALU controlled by the controller; and a hierarchical function library including a memory, the hierarchical function library storing separate blocks of subprograms and subfunctions in at least four levels of subprograms and subfunctions, wherein the at least four levels include a top level for including protocols, an application level for including relatively complex operational functionality, an arithmetic level for including operational functionality, and a ground level for including initial ALU operations; wherein the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller, and wherein the plurality of binary tables includes a PROGRAM ROM binary table, a LABEL ROM binary table, a FUNCTION ROM binary table, and an F_id DECODER binary table, the PROGRAM ROM binary table including binary code of the microprogram to be executed during runtime, the LABEL ROM binary table including addresses of commands labeled in the microprogram, the FUNCTION ROM binary table including addresses of functions and subfunctions as entry points to be called during execution, and the F_id DECODER binary table including indices of functions accessible for external control for decoding.