Patent ID: 8793469

Claim:
A computer for executing instructions, comprising: an instruction decoder unit to decode a macro instruction into at least one micro-operation with a set of data fields, wherein at least one data field in the set of data fields is in a compressed form, the instruction decoder unit including: storage logic to store the at least one micro-operation with the at least one compressed-form data field; extraction logic to extract the at least one compressed-form data field into an uncompressed-form data field; and send the at least one micro-operation with the extracted uncompressed-form data field to an execution unit for execution; and an execution unit to execute the at least one micro-operation, wherein the extraction logic comprises usable space restriction logic to receive an address size data field and a scale data field, the address size data field does not include a full complement of addressable space when stored in the compressed form and the scale data field is stored with a smaller number of bits than a scaled data field of the uncompressed-form data field, the smaller number of bits corresponding to a usage model of an adjustment in scale to represent a working and usable space.