Patent ID: 8866804

Claim:
A pixel structure, comprising a first scan line, a second scan line, and a data line, characterized in that: the pixel structure further comprises: a first storage capacitor, comprising a first terminal and a second terminal, the first terminal coupled to a common line; a second storage capacitor, comprising a first terminal and a second terminal, the first terminal coupled to the common line; a first transistor, comprising a first gate, a first source, and a first drain, the first gate coupled to a first scan line, the first source and the first drain coupled to a data line and to the second terminal of the first storage capacitor, respectively, for conducting the data line and the first storage capacitor; and a second transistor, comprising a second gate, a second source, and a second drain, the second gate coupled to a second scan line, the second source and the second drain coupled to the second terminal of the first storage capacitor and to the second terminal of the second storage capacitor, respectively; wherein a first polarity voltage applied on the data line is stored into the first storage capacitor during a first time period which the first transistor is turned on, and the first storage capacitor discharges due to a connection between the first capacitor and the second capacitor during a second time period which the second transistor is turned on; a second polarity voltage applied on the data line is stored into the first storage capacitor during a third time period which the first transistor is turned on, and the first storage capacitor discharges due to a connection between the first storage capacitor and the second storage capacitor during a fourth time period which the second transistor is turned on; a polarity of the first polarity voltage is contrary to that of the second polarity voltage.