Patent ID: 7710778

Claim:
A flash memory device with NAND architecture, the flash memory device comprising: a matrix of data storage memory cells each data storage memory cell having a programmable threshold voltage, the matrix comprising: a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element receiving a shielding voltage and configured to shield the memory cells from electric fields that, during reading and program operations, arise between the string of memory cells and the first selector; and wherein: the reference voltage having a magnitude that is less than the magnitude of the shielding voltage.