Patent ID: 7325024

Claim:
A circuit comprising: a plurality of selectors, each of the selectors including a multiplexing network to select a pair of input values from among a plurality of input values, each of the selectors also including a sense amplifier coupled to the multiplexing network to generate at least one input data bit based on the pair of input values, a first multiplexer to select from a first group of input values of the plurality of input values to provide a first input value of the pair of input values, and a second multiplexer to select from a second group of input values of the plurality of input values to provide a second input value of the pair of input values; and an arithmetic unit coupled to the sense amplifier to perform an arithmetic operation on the at least one input data bit, wherein the arithmetic unit includes: a sparse carry-merge generator to generate a first number of carry signals based on the plurality of second input data bits and the least one input data bit from the sense amplifier of each of the selectors; a plurality of intermediate carry generators coupled to the sparse carry merge generator to generate a second number of carry signals; and a plurality of conditional sum generators coupled to the sparse carry-merge generator and the plurality of intermediate carry generators and to provide a sum of a first number represented by a combination of least one input data bit of each of the sense amplifiers from each of the selectors and a second number represented by the second input data bits; and a second plurality of selectors coupled to the arithmetic unit to provide a plurality of second input data bits to the arithmetic unit.