Patent ID: 8796777

Claim:
An apparatus comprising: a plurality of bit cell memory transistors, wherein each bit cell memory transistor of the plurality of bit cell memory transistors is configured to store a single data bit, wherein each bit cell memory transistor is configured to operate in a hold phase and in a write phase, and wherein each bit cell memory transistor comprises: a fin defining a source-drain channel protruding from a surface of a substrate; a first gate configured to be electrically coupled to a first bias source to receive a first gate voltage, wherein the first gate is adjacent to the fin at a first fin face, and separated from the fin by a buried oxide (BOX) layer; a second gate configured to be electrically coupled to a second bias source to receive a second gate voltage, wherein the second gate is situated adjacent to the fin at a second fin face; and a third gate configured to be electrically coupled to a third bias source to receive a third gate voltage, wherein the third gate is situated adjacent to the fin at a third fin face; a first gate write and hold logic control circuit configured to control the first gate of each bit cell memory transistor; a second gate write and hold logic control circuit configured to control the second gate of each bit cell memory transistor; and a third gate write and hold logic control circuit configured to control the third gate of each bit cell memory transistor, wherein, when a particular bit cell memory transistor operates in the hold phase, the first gate write and hold logic control circuit, the second gate write and hold logic control circuit, and the third gate write and hold logic control circuit are configured to apply low values of the first gate voltage, the second gate voltage, and the third gate voltage to the particular bit cell memory transistor.