Patent ID: 6982591

Claim:
A circuit comprising: a tunneling leakage monitor circuit, said tunneling leakage monitor circuit comprising a first PFET, a second PFET, a first NFET and a second NFET, sources of said first and second PFETS connected to a voltage source, gates of said first and second PFETs and said drain of said first PFET connected to a drain of said first NFET, a drain of said second PFET connected to a gate of said second NFET, sources of said first and second NFETs and a drain of said second NFET connected to ground; a current mirror connected to a gate of said first NFET, said current mirror adapted to force a current of a predetermined value from said gate of said second NFET, through a gate dielectric layer of said second NFET, through said source and said drain of said second NFET to ground, said current consisting of tunneling leakage current; an input of a voltage buffer connected to said gate of said second NFET, said voltage buffer adapted to generate an output voltage based on a voltage level developed across said gate dielectric layer of said second NFET when said current is at said predetermined current value; and a voltage regulator coupled to said voltage burner, said voltage regulator adapted to supply a fixed voltage to a power distribution network of an integrated circuit chip based on said output voltage of said voltage buffer.