Patent ID: 7687853

Claim:
A semiconductor device, comprising: a plurality of silicon controlled rectifier-lateral diffusion metal oxide semiconductor (SCR-LDMOS) transistors, each SCR-LDMOS transistor comprising: a SCR-LDMOS semiconductor layer of a first conductivity type; a second SCR-LDMOS region of a second conductivity type opposite the first conductivity type formed in the SCR-LDMOS semiconductor layer; a third SCR-LDMOS region of the first conductivity type formed as a well in the second SCR-LDMOS region; a SCR-LDMOS source region of the second conductivity type formed in the third SCR-LDMOS region; a SCR-LDMOS drain region of the second conductivity type formed in the second SCR-LDMOS region and spaced apart from the SCR-LDMOS source region, such that a SCR-LDMOS channel is formed between the SCR-LDMOS source region and the SCR-LDMOS drain region; a SCR-LDMOS backgate region formed in the third SCR-LDMOS region and adjacent the SCR-LDMOS source region such that the SCR-LDMOS source region separates the SCR-LDMOS backgate region and the SCR-LDMOS channel, the SCR-LDMOS backgate region being of the first conductivity type; a SCR-LDMOS anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS channel region; a SCR-LDMOS gate oxide layer over the SCR-LDMOS channel; and a SCR-LDMOS gate over at least part of the SCR-LDMOS source region and the SCR-LDMOS channel; and a plurality of lateral diffusion metal oxide semiconductor (LDMOS) transistors, each LDMOS transistor comprising: a LDMOS semiconductor layer having a first LDMOS region of the first conductivity type, the LDMOS first region having a first dopant concentration; a pair of second LDMOS regions of the first conductivity type first formed at a face of the LDMOS semiconductor layer in the first LDMOS region, the LDMOS second regions having a second dopant concentration greater than the first dopant concentration; a pair LDMOS drain regions of the first conductivity type formed at a face of the LDMOS semiconductor layer in the second LDMOS regions, the LDMOS drain regions having a third dopant concentration greater than said second dopant concentration; a third LDMOS region of the second conductivity type opposite the first conductivity type formed at a face of the LDMOS semiconductor layer in the first LDMOS region, the third LDMOS region formed between the pair of second LDMOS regions; a LDMOS source region of the first conductivity type formed at a face of the LDMOS semiconductor layer in the third LDMOS region, a pair of LDMOS channel regions defined in the third LDMOS region between an edge of each of the pair of LDMOS source regions and an associated edge of the third LDMOS region; and a LDMOS gate extending over the pair of LDMOS channel regions.