Patent ID: 8289768

Claim:
An electronic system, the system comprising: a plurality of multi-bit memory cells, wherein each of the plurality of multi-bit memory cells is operable to hold at least two bits, and wherein the plurality of multi-bit memory cells includes a first subset of the plurality of multi-bit memory cells and a second subset of the plurality of multi-bit memory cells; an encoding circuit, wherein the encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells, wherein when the encoded output is destined for the first subset of the plurality of multi-bit memory cells the encoded output is a single two bit output representing the two data bits, and wherein when the encoded output is destined for the second subset of the plurality of multi-bit memory cells the encoded output is the series of two two bit outputs representing the two data bits; and a decoding circuit, wherein the decoding circuit is operable to reverse the encoding applied by the encoding circuit.