Patent ID: 7799594

Claim:
A method for manufacturing a thin film transistor array panel comprising: disposing a first gate line comprising a gate electrode and an end portion on a substrate; disposing a gate insulating layer on the first gate line; disposing a semiconductor comprising a channel portion, a data line comprising a source electrode and an end portion, and a drain electrode on the gate insulating layer; disposing a passivation layer on the gate insulating layer, the data line, the drain electrode, and the channel portion of the semiconductor; disposing a photosensitive film on the passivation layer and exposing the photosensitive film to light using a first photo mask to form a first photosensitive film pattern, which comprises a first portion and a second portion, the second portion having a thickness which is greater than a thickness of the first portion, the first photosensitive film pattern exposing a portion of the passivation layer on a portion of the drain electrode; removing the exposed portion of the passivation layer using the first photosensitive film pattern as a mask; etching the first photosensitive film pattern to remove the first portion to form a second photosensitive film pattern; disposing a conductive layer on the second photosensitive film pattern; heating the second photosensitive film pattern to form cracks in the conductive layer; and forming a pixel electrode by removing the second photosensitive film pattern, the pixel electrode contacting a portion of the drain electrode and disposed on a portion of the passivation layer exposed by the removal of the first portion of the first photosensitive film pattern.