Patent ID: 7015729

Claim:
A circuit for sampling and holding, comprising: a processing circuit that is interleaved such that the processing circuit comprises a first processing channel and a second processing channel; a first sample-and-hold channel, comprising: a first sampling switch circuit that is coupled between a first node and a second node; a first sampling capacitor circuit that is coupled to the second node; and a first holding switch circuit that is coupled between the second node and the first processing channel; and a second sample-and-hold channel, comprising: a second sampling switch circuit that is coupled between the first node and a third node; a second sampling capacitor circuit that is coupled to the third node; and a second holding switch circuit that is coupled between the third node and the second processing channel, wherein the first sampling switch circuit is configured to be closed during a sample phase for the first sample-and-hold channel, the first sampling switch circuit is configured to be open during a hold phase for the first sample-and-hold channel, the first holding switching circuit is configured to be closed during the hold phase for the first sample-and-hold channel, a sample voltage is sampled at the second node during the sample phase for the first sample-and-hold channel, and wherein the voltage at the second node is substantially equal to the sample voltage during the hold phase for the first sample-and-hold channel.