Patent ID: 8053781

Claim:
A semiconductor device comprising: a gate wiring formed over an insulating surface; an insulating film formed over the gate wiring; a first semiconductor film formed over the insulating film; a source region and a drain region each provided in a second semiconductor film containing an impurity element of one conductivity type, formed over the first semiconductor film; a source wiring provided on the source region; an electrode provided on the drain region; and a pixel electrode formed so as to partially overlap and be in contact with the electrode, wherein at least an outer end of the first semiconductor film has a tapered shape, wherein an outer side edge of a top surface of the first semiconductor film is aligned with an outer side edge of a bottom surface of the second semiconductor film, wherein the first semiconductor film has a depression between the source region and the drain region, wherein an inner side edge of the top surface of the first semiconductor film is aligned with an inner side edge of the bottom surface of the second semiconductor film, and wherein a film thickness of the insulating film is thinner than a film thickness of the gate wiring.