Patent ID: 7509552

Claim:
A method of simulating integrated circuit performance of a scan ring having a plurality of serially connected latches including at least one L 1 latch and/or at least one L 2 latch, comprising the steps as follows: a) starting a system scan clock; b) recording a first “snap shot” of scan ring data; c) starting a scan ring; d) shifting the scan ring using the current scan data; e) stopping the system scan clock and taking a second “snap shot”; and f) comparing the first “snap shot” and the second “snap shot”; g) if both the first “snap shot” and the second “snap shot” are identical the functional scan is successful; but if the first “snap shot” and the second “snap shot” are not identical, locating a broken ring if the functional scan fails, by a method comprising the steps of as follows: 1) comparing the latches to an expected shifted value in every scan A/B clocks; 2) saving previous values of each L 2 latch; and 3) when a scan B clock is on, obtaining a current latch value and comparing it to a previous value of a precedent latch.