Patent ID: 8208287

Claim:
An integrated circuit, comprising: a silicon semiconductor substrate including active circuitry fabricated on the silicon semiconductor substrate; at least one memory layer fabricated directly above and in contact with the silicon semiconductor substrate; and at least one two-terminal cross-point memory array disposed in each memory layer, each array including a plurality of re-writeable non-volatile two-terminal memory elements, each memory element operative to store data as a plurality of conductivity profiles and configured to retain the data in the absence of electrical power, each array is electrically coupled with the active circuitry, and the active circuitry including a memory access circuit configured to select at least one of the memory elements for a read operation, a sensing circuit configured to sense a reference signal and a leakage signal during a first cycle of the read operation and to sense a read current from selected memory elements and the leakage signal during a second cycle of the read operation, the sensing circuit operative to generate a data signal indicative of stored data in selected memory elements, and a margin manager circuit configured to manage a read margin for selected memory elements substantially during the first and second cycles and operative to determine if a value of the stored data in selected memory elements is within a specified level of the read margin.