Patent ID: 7557661

Claim:
A circuit for providing a low-jitter clock output synchronized to a timing reference having jitter, said circuit comprising: a numerically-controlled signal source for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output, wherein said numerically-controlled signal source generates at least one substantially sinusoidal analog signal in conformity with said rational numeric representation and said stable clock, and converts said at least one substantially sinusoidal signal to a digital representation to produce said clock output; a counter for dividing a frequency of one of said stable clock or an output of said numerically-controlled signal source; a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference and an output of said counter; and a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled signal source.