Patent ID: 8299591

Claim:
A semiconductor package comprising: a substrate having a substrate body having a first region, a second region defined to be around the first region, and a third region defined to be around the second region; a plurality of wiring lines disposed on the substrate body, wherein respective wiring lines extend from the first region to the third region such that respective ends of the wiring lines are disposed in the third region; first connection patterns disposed in the third region and electrically connected to the respective ends of the wiring lines disposed in the third region, the first connection patterns comprising pad parts; a semiconductor chip disposed in the first region and electrically connected to the respective wiring lines; bumps formed beneath the semiconductor chip within the first region so as to electrically connect the semiconductor chip to the respective wiring lines; second connection patterns disposed on a lower surface of the substrate body; through holes passing through the substrate body and extending from an upper surface of the substrate body on which the semiconductor chip is disposed to the lower surface of the substrate body facing away from the upper surface, wherein the respective first connection patterns are disposed on inner surfaces of the substrate body within the through-holes, wherein the first connection patterns comprise pad parts formed on at least one of the upper surface and the lower surface so as to surround the through-holes; and a molding member in the first and second regions and not the third region, such that the molding member covers the semiconductor chip and not the pad parts of the first connection patterns, wherein the first region is a portion of the substrate body where the semiconductor chip is disposed, the third region is a portion of the substrate body outside of where the molding member is formed, and the second region is a portion of the substrate body between the semiconductor chip and an outer perimeter of the molding member, and the bumps are formed in the first region beneath the semiconductor chip and not in the second region.