Patent ID: 6850123

Claim:
A system for determining clock-to-out enable delay and clock-to-out enable delay and clock-to-out disable delay of a first test circuit, the system comprising: a ring oscillator having at least first and second ring-oscillator stages, wherein the first ring-oscillator stage includes a first input terminal and a first output terminal, and the second ring-oscillator stage includes a second input terminal and a second output terminal; and an oscillator enable circuit having a test enable input terminal coupled to the ring oscillator, the oscillator enable circuit for enabling oscillation of the ring oscillator responsive to the test enable input terminal; wherein the first test circuit is interposed between the first stage and the second stage, the first test circuit having a first test input terminal connected to the first output terminal, a second test input terminal connected to the second output terminal, and a first test output terminal connected to the second input terminal.