Patent ID: 8433873

Claim:
A memory controller, comprising: an interface circuit configured to receive a disposition instruction and an associated access command directed to a block of data at a logical address in a memory system managed by the memory controller, wherein the memory system includes a plurality of different types of memory having different performance characteristics, and wherein the disposition instruction is generated based on the different performance characteristics of the plurality of different types of memory; and control logic, coupled to the interface circuit, which is configured to control accesses to the memory system, wherein the control logic is configured to receive the access command and, in response to the access command, is configured to forward the access command to a first type of memory in the plurality of different types of memory; and wherein the control logic is also configured to receive the disposition instruction associated with the access command and, in response to the disposition instruction, is configured to move the block of data to a second type of memory in the plurality different types of memory to facilitate subsequent accesses to the block of data by providing a read command for the block of data to the first type of memory and a write command for the block of data to the second type of memory.