Patent ID: 7965217

Claim:
An apparatus comprising: a pipelined analog-to-digital converter comprising a control and correction circuit; and a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises: an MDAC input configured to receive an analog input voltage; and a dual latch flash analog-to-digital converter (ADC) comprising one or more dual latch comparators, each of the dual latch comparators being configured to receive the MDAC input and a respective one of different reference voltages, each of the dual latch comparators comprising: a pre-amplifier having an input coupled to the MDAC input and the respective one of different reference voltages to provide a pre-amplified MDAC input and a pre-amplified reference voltage, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output, wherein the demultiplexer is configured to provide the pre-amplified MDAC input and the pre-amplified reference voltage alternately via the first or second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch is configured to generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch is configured to generate a second digital signal, wherein the first latch and the second latch alternate analog-to-digital conversion in response to control from the control and correction circuit.