Patent ID: 8054680

Claim:
A semiconductor device comprising: memory cells each of which comprises: a source diffusion layer and a drain diffusion layer formed on a main surface of a semiconductor substrate with a predetermined distance therebetween; and a gate section that is formed by stacking a charge storage film and a gate electrode via an insulation film on an area of said semiconductor substrate sandwiched between said source diffusion layer and said drain diffusion layer; and control circuitry coupled to said memory cells to control operations of said memory cells, wherein said control circuitry is constructed and performs control such that in an erase operation, holes are supplied from said gate electrode to said charge storage film, and electrons stored in said charge storage film and holes supplied from the gate electrode combine and disappear, and such that before erase and write operation of memory cells, the memory cells subject to said erase and write operation are written, and then said memory cells are erased, and wherein each said memory cell is erased by reducing a threshold thereof, and the erase of the memory cell is stopped in response to a detection indicating that the threshold reaches a predetermined level selected to be above a threshold reduction saturation level of the memory cell.