Patent ID: 7573971

Claim:
A shift register circuit, comprising a plurality of shift registers connected in series, each said shift register comprising: a phase-shifting element, coupled to a first input, a first clock node and a second clock node, wherein the first input, the first clock node and the second clock node receive a first input signal, a first clock signal and a second clock signal, respectively, and the first clock signal and the second clock signal are complementary in phase; and a pull-high element, coupled to the phase-shifting element and an output, for pulling up an output signal of the output to a high logic level, wherein the pull-high element comprises a logic unit, and the logic unit has at least two inputs coupled to the phase-shifting element; wherein no current path is established in the logic unit when the first input signal is at a low logic level; the phase-shifting element is configured to determine a first node signal at a first node according to the first input signal and the first clock signal; the pull-high element is configured to determine a second node signal at a second node according to a second input signal, the first node signal and the second clock signal, and to determine the output signal by the first node signal and the second node signal; the pull-high element further comprises first, second and third transistors having sources and drains connected in series in the recited order; the third and second transistors together define the logic unit; the second node is between the first and second transistors; a gate of the first transistor is connected to receive the second input signal; a gate of the third transistor is connected to the second clock node; and a gate of the second transistor is connected to the first node.