Patent ID: 8643183

Claim:
An integrated circuit arrangement comprising: a conductive structure which is electrically conductive and which is structured in accordance with a grain structure; a substrate containing a multiplicity of semiconductor components; wherein the conductive structure is an interconnect arranged between the substrate and a via conductive structure, such that the interconnect adjoins the via conductive structure; wherein an amorphous barrier material is arranged at the conductive structure; wherein at a top area of the conductive structure which is remote from the substrate, the amorphous barrier material is arranged without an overhang over a first dielectric situated directly laterally with respect to the conductive structure, the amorphous barrier material having a homogeneous material composition, and the amorphous barrier material at the top area of the conductive structure being arranged between a second dielectric and the interconnect in a manner adjoining the second dielectric; wherein an electrically conductive barrier material is arranged in a grain boundary region of the conductive structure which is arranged at least 5 nanometers within the conductive structure, a sidewall of the via conductive structure adjoins a barrier material layer, and no barrier material layer is arranged between the via conductive structure and the interconnect and the grain boundary region is located at the bottom of the via conductive structure.