Patent ID: 7263122

Claim:
An equalization circuit to receive a plurality of input symbols and to generate an output signal wherein the output signal is representative of a transmitted symbol, the equalization circuit comprising: a first data slicer having a plurality of inputs and an output, wherein a first input is adapted to receive the plurality of input symbols and a second input is adapted to receive a first slicer level, and wherein the first data slicer outputs a first or second value based on the amplitude of the input symbol relative to the first slicer level; a second data slicer having a plurality of inputs and an output, wherein a first input of the second data slicer is adapted to receive the plurality of input symbols and a second input of the second data slicer is adapted to receive a second slicer level, and wherein the second data slicer outputs the first or second value based on the amplitude of the input symbol relative to the second slicer level; and logic circuitry, coupled to the first and second data slicers, to output a signal having either a first or second logic level wherein the first logic level is associated with the first value and the second logic level is associated with the second logic level, and wherein: if the data slicers output the same value, the logic circuitry outputs the logic level that is associated with the value output by the data slicers; and if the data slicers output different values, the logic circuitry outputs the complement of the logic level of the immediately preceding input symbol.