Patent ID: 8542513

Claim:
An array of vertically stacked tiers of non-volatile cross point memory cells, comprising: a plurality of horizontally oriented word lines within individual tiers of memory cells; a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells; and individual of the memory cells comprising multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones of the horizontally oriented word lines and local vertical bit line extensions comprising opposing conductive electrodes of individual memory cells where such cross, the horizontally oriented word lines at least where such cross being of a conductively filled C-shape in a vertical cross section with an outline of the C-shape comprising one conductive material with a central portion of the C-shape being filled with another conductive material of different composition from the one conductive material.