Patent ID: 7802219

Claim:
A method for placement of at least one cell in a digital integrated circuit layout, comprising: retrieving, from a computer readable medium, information regarding a digital integrated circuit; forming, using a processor, a global placement grid of coordinates for the digital integrated circuit based on the information, wherein the coordinates represent horizontal and vertical directions; forming a local placement grid of coordinates for at least one local region of the digital integrated circuit and another local placement grid of coordinates for another local region of the digital integrated circuit, wherein each of the local placement grid of coordinates and the other local placement grid of coordinates represents horizontal and vertical directions, wherein each of the at least one local region and the other local region is adapted to support non-integer multiple height rows, and wherein the local placement grid of coordinates is independent in height and width from the other local placement grid of coordinates; and associating the at least one cell with the at least one local region formed.