Patent ID: 8743647

Claim:
An electronic device comprising a semiconductor memory cell, the semiconductor memory cell comprising: a substrate; a memory cell circuitry on the substrate, the memory cell circuitry comprising: a well fabricated in the substrate, wherein a current path from a power source to the substrate runs through the well; and a junction device comprising a junction configured to be forward biased or reverse biased, wherein a reverse bias leakage current flows across the junction when the junction is reverse biased; and a switch coupled between the memory cell circuitry and a power source, wherein the switch is in series with the current path between the power source and the substrate, the switch configured to decouple the memory cell circuitry from the power source during a standby mode, whereby, in the standby mode, a current is restricted from flowing from the power source through the well to the substrate, and the reverse bias leakage current is restricted from flowing through the junction device.