Patent ID: 7531412

Claim:
A method of manufacturing a semiconductor memory device, the method comprising: forming a plurality of semiconductor material pillars in a spaced relationship on a semiconductor substrate; forming respective surrounding gate electrodes on ones of the pillars; forming a first source/drain region in the semiconductor substrate between adjacent ones of the pillars; forming a bit line in the first source/drain region and electrically coupled to the first source/drain region; and forming a second source/drain region in an upper portion of at least one of the adjacent ones of the pillars, wherein forming a plurality of semiconductor material pillars includes: forming a pad oxide film and a hard mask pattern on the semiconductor substrate; forming a plurality of pillars to a smaller width than the width of the hard mask pattern by etching the pad oxide film and the semiconductor substrate with the hard mask pattern thereon; and isolating the pillars by etching the semiconductor substrate between the pillars to a predetermined depth; and wherein forming a bit line includes forming the bit line to surround outer surfaces of ones of the pillars; and wherein the method further comprises: forming a word line in a cross-wise pattern with the bit line so that the word line is electrically connected to ones of the surrounding gate electrodes; removing the hard mask pattern; and wherein forming a second source/drain region comprises forming the second source/drain region after removing the hard mask pattern to expose the upper portion.