Patent ID: 7051186

Claim:
In a multi-operation processing system having a multi-stage execution pipeline, including a plurality of functional units and a register file having a plurality of read ports and write ports, a method for selectively bypassing the register file, comprising the steps of: determining whether results produced simultaneously in the functional units are to be used in the same functional units where the results were produced; and bypassing the register file, when the results are to be used in the same functional units where the results were produced, wherein the determining step comprises the steps of: forming a pair of vector read indexes, each vector read index formed by concatenating read indexes of each operand; forming a vector write index by concatenating the write indexes of each result; comparing each of the vector read indexes to the vector write index; and for each of the comparisons, setting a single bypass condition for all the functional units, if the result of the comparison is a match.