Patent ID: 7970290

Claim:
A digital phase estimator for generating a phase estimation signal, comprising: a first absolute value calculator, for calculating an absolute value of a first input signal; a second absolute value calculator, for calculating an absolute value of a second input signal; a first sign calculator, for obtaining a sign of the first input signal; a second sign calculator, for obtaining a sign of the second input signal; a subtracter, for obtaining a difference of subtracting the absolute value of the first input signal from the absolute value of the second input signal; and a first multiplier ( 406 ), for multiplying the difference between the absolute values of the first input signal and the second input signal with the signs of the first input signal and the second input signal, and outputting the multiplying result as the phase estimation signal; wherein an input terminal of the first absolute value calculator and an input terminal of the first sign calculator are connected to a first external input; an output terminal of the first absolute value calculator is connected to a negative input terminal of the subtracter; an input terminal of the second absolute value calculator and an input terminal of the second sign calculator are connected to a second external input; an output terminal of the second absolute value calculator is connected to a positive input terminal of the subtracter; an output terminal of the subtracter is connected to a third input terminal of the first multiplier ( 406 ); output terminals of the first and the second sign calculators are respectively connected to a first and a second input terminals of the first multiplier ( 406 ); and an output terminal of the first multiplier ( 406 ) is connected to an external output.