Patent ID: 8481348

Claim:
A method for fabricating a phase change memory, comprising: providing a substrate including a storage substrate and a peripheral substrate; forming a sacrificial dielectric layer on the peripheral substrate; etching the storage substrate and forming an N-type ion buried layer on the storage substrate; forming a plurality of vertical LEDs on the N-type ion buried layer, each vertical LED comprising an N-type conductive region containing SiC on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region, a top of P-type conductive region being flush with a top of the peripheral substrate; removing the sacrificial dielectric layer on the peripheral substrate; forming a plurality of storage STI units between the vertical LEDs, and forming a plurality of peripheral STI units in the peripheral substrate, the storage STI units having thickness substantially equal to thickness of the vertical LEDs, and the peripheral STI units having thickness substantially equal to thickness of the storage STI units; and forming a plurality of phase change layers on the vertical LEDs and between the storage STI units, and forming at least one MOS transistor on the peripheral substrate and between the peripheral STI units.