Patent ID: 7781831

Claim:
A semiconductor device comprising: a semiconductor substrate; a first insulating layer formed over a surface of the semiconductor substrate; a patterned layer of nanocrystals formed over a surface of the first insulating layer; a second insulating layer formed over the layer of nanocrystals, the second insulating layer having a nitrogen content greater than or equal to two (2) atomic percent of the second insulating layer; a third insulating layer formed on the surface of the semiconductor substrate and not over the first and second insulating layer; and a patterned polysilicon layer formed over the second insulating layer and over the third insulating layer, wherein the patterned polysilicon layer over the second insulating layer forms gate electrodes for a plurality of non-volatile memory cells, and wherein the patterned polysilicon layer over the third insulating layer forms gate electrodes for a plurality of transistors.