Patent ID: 8461812

Claim:
A shunt regulator comprising: a control circuit coupled between a first node and a ground, and configured to generate a gate control signal in response to a voltage of the first node and a reference voltage; a bypass circuit configured to form a first current path between the first node and the ground in response to the gate control signal; and a protection circuit having a PMOS transistor whose source is directly connected to the first node and whose drain is directly connected to the ground, the PMOS transistor being fully turned on in response to a current flowing through the bypass circuit, and configured to form a second current path between the first node and the ground, wherein the protection circuit comprises a CMOS inverter coupled between the first node and the ground for inverting a first voltage signal corresponding to the current flowing through the bypass circuit to generate a second voltage signal to turn on the PMOS transistor when the voltage of the first node increases above a desired voltage, and wherein the second voltage signal has substantially the same magnitude as the voltage of the first node when the first voltage signal has a logic “low” state.