Patent ID: 7329938

Claim:
A semiconductor integrated circuit including a plurality of standard cells implemented by p-wells and n-wells, extending along the row direction, the row of the p-wells and n-wells are arranged periodically and alternately along the column direction, comprising: a first cell spanning one of the p-wells and one of the n-wells adjacent to each other, and having one end on a dividing line inside the p-well and another end on a dividing line inside the n-well, and having a height determined by the one end and the another end; and a second cell, spanning another one of the p-wells and another one of the n-wells adjacent to each other, with a height covering the entire widths of the p- and n-wells measured along the column direction, wherein the height of the second cell is double that of the first cell, and one end and another end of the second cell is different from a position of a cell border in the row direction of the first cell in the column direction, and wherein a same row is included in the first cell and the second cell.