Patent ID: 8362602

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein: the main body includes: a main part that includes a plurality of layer portions stacked and has a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires; the plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body; each of the plurality of layer portions includes a semiconductor chip; in at least one of the plurality of layer portions, the semiconductor chip is electrically connected to two or more of the plurality of wires; the plurality of second terminals are electrically connected to corresponding ones of the plurality of first terminals via the respective wires to constitute a plurality of pairs of the first and second terminals, the first and second terminals in each of the pairs being electrically connected to each other; and the plurality of pairs include a plurality of non-overlapping terminal pairs, each of the non-overlapping terminal pairs consisting of any one of the first terminals and any one of the second terminals, the first and second terminals in each of the non-overlapping terminal pairs being electrically connected to each other and being positioned not to overlap each other as viewed in the direction perpendicular to the top surface of the main body.