Patent ID: 7504858

Claim:
A configurable integrated circuit (IC) comprising: a) a first array of tiles, wherein said first array of tiles comprises columns and rows of tiles; b) a first plurality of tiles within said first array of tiles, wherein each tile of said first plurality of tiles comprises a set of outputs; c) a second plurality of files within said first array of tiles, wherein each tile of said second plurality of tiles comprises a set of inputs; and d) a plurality of non-neighboring offset connections (NNOCs), wherein each NNOC of said plurality of NNOCs connects an output of a tile of said first plurality of tiles to an input of a non-neighboring offset tile of said second plurality of tiles, wherein a first particular tile is a non-neighboring offset tile of a second particular tile when said particular second tile is offset from said first particular tile by at least one row and at least two columns or by at least two rows and at least one column, wherein said NNOCs serve as a configurable data bus when a configurable resource in each of said non-neighboring offset tiles of said second plurality of tiles is configured to examine a signal supplied by the NNOC connected to said input of the non-neighboring offset tile of said second plurality of tiles, wherein each NNOC of said plurality of NNOCs is topologically parallel to each other NNOC within said plurality of NNOCs.