Patent ID: 7486143

Claim:
A circuit for biasing an amplifier transistor, the circuit comprising: a reference node operable to receive a reference current; a bias node operable to be coupled to the transistor and to carry a bias signal; first, second, third, and fourth supply nodes, the amplifier transistor operable to be coupled to the first supply node; a current source coupled between the second supply node and the reference node and operable to generate the reference current; a buffer stage having a buffer input terminal coupled to the reference node and having a buffer output terminal coupled to the bias node, wherein the buffer stage comprises a buffer transistor having a first terminal coupled to the third supply node, a second terminal coupled to the buffer output terminal, and a control terminal coupled to the buffer input terminal; a reference stage coupled to the reference and bias nodes and operable to generate the bias signal from the reference current, the bias signal operable to cause the transistor to conduct a bias current that is proportional to the reference current, wherein the reference stage comprises, a reference transistor having a first terminal coupled to the reference node, a second terminal coupled to the fourth supply node, and a control terminal, and a first impedance element serially coupled between the bias node and the fourth supply node; and wherein the feed back stage comprises, a feedback transistor having a first terminal coupled to the first supply node, a second terminal, and a control terminal coupled to the reference node, a second impedance element coupled between the second terminal of the feedback transistor and the fourth supply node, a third impedance element coupled between the second terminal of the feedback transistor and the control terminal of the reference transistor, and a fourth impedance element coupled between the control terminal of the reference transistor and the bias node.