Patent ID: 8710661

Claim:
A planarization method comprising: forming a conductive layer on a substrate; forming an etch stop layer on a top surface of the conductive layer; patterning the conductive layer and the etch stop layer on the top surface of the conductive layer to form a plurality of conductive features each covered by a portion of the etch stop layer; after the conductive layer and the etch stop layer are patterned, depositing a first dielectric layer on a top surface of the conductive features and on a top surface of the substrate between the conductive features; selectively etching a first portion of the first dielectric layer from the top surface of at least one of the conductive features and stopping on the portion of the etch stop layer without etching a second portion of the first dielectric layer that is located between the conductive features; forming a second dielectric layer on the top surface of the at least one of the conductive features and on a top surface of the second portion of the first dielectric layer; and planarizing a top surface of the second dielectric layer.