Patent ID: 8874858

Claim:
A reconfigurable interleaver, comprising: a plurality of counters, each said counter being configurable with a total count number defining a number of values to count and with a start value defining a value from which to start counting, a plurality of memories, each said memory being configured to retrieve values from memory positions in the memory indicated by a counter of the plurality of counters associated with the memory, and a plurality of computational elements configured to operate on the values retrieved from the plurality of memories, a configurable limit element, the limit element being configured to receive a limit bit and a limit value and to receive a limit input value, wherein, the reconfigurable interleaver is configured to produce a sequence of interleaved addresses, a next one of the interleaved addresses in the sequence of interleaved addresses being obtainable by advancing at least one counter of the plurality of counters and by operating at least one of the computational elements on at least a value retrieved from a memory associated with the advanced counter, wherein, by reconfiguring at least one of the counters with at least one of the total count number and the start value, the reconfigurable interleaver is configured for one of at least two different interleaving patterns, wherein the limit element is configured to perform and output a modulo operation upon the limit input value using the limit value as modulus for one value of the limit bit, wherein the limit element is configured to perform a limiting operation upon the limit input value using the limit value as limit, outputting the limit input value if the limit input value is smaller than the limit value, for one other value of the limit bit, and wherein the configuring of the reconfigurable interleaver for one of the at least two different interleaving patterns is further in dependency upon one of the limit bit and the limit value.