Patent ID: 7211844

Claim:
A vertical semiconductor device structure, comprising: a substrate defining a substantially horizontal plane; a gate electrode projecting vertically from said substrate and including a vertical sidewall; a semiconducting nanotube extending between opposite first and second ends with a substantially vertical orientation; a spacer of a dielectric material flanking said vertical sidewall and spaced horizontally from said vertical sidewall of said gate electrode to define a vertical passage having horizontal dimensions appropriate for the synthesis of said semiconducting nanotube, said semiconducting nanotube positioned in said vertical passage, and said spacer extending vertically relative to said gate electrode such that said vertical passage has a vertical dimension greater than or equal to a vertical height of said vertical sidewall of said gate electrode; a gate dielectric disposed on said vertical sidewall between said semiconducting nanotube and said gate electrode; a source electrically coupled with said first end of said semiconducting nanotube; and a drain electrically coupled with said second end of said semiconducting nanotube.