Patent ID: 8148806

Claim:
A chip package comprising: a first circuit substrate comprising a first pad at a top side of said first circuit substrate; a first solder ball contacting a bottom side of said first circuit substrate; a first chip over said top side of said first circuit substrate, wherein said first chip is connected to said first pad; a second chip over said first chip; and a portion over said top side of said first circuit substrate and over said first and second chips, wherein said portion comprises a second circuit substrate over said top side of said first circuit substrate and over said first and second chips, a third chip over a top side of said second circuit substrate, a second solder ball having a top end contacting a bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate, and a third solder ball having a top end contacting said bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate, wherein said second circuit substrate comprises a second pad at said top side of said second circuit substrate, wherein said third chip is connected to said second pad, wherein said first and second chips are directly horizontally between said second and third solder balls, wherein said first and second chips are between said top side of said first circuit substrate and said bottom side of said second circuit substrate.