Patent ID: 7599388

Claim:
A serial bus data transfer system, comprising: a serial bus interface circuit which comprises: first and second memory devices arranged to interface with a serial bus such that said first memory device receives serial data from said bus and said second memory device outputs serial data to said bus; a dual-banked shared memory comprising first and second memory banks; and a first processor arranged to interface with said first and second memory devices and said first and second memory banks such that said serial data is routed between said memory devices and said memory banks via said first processor; and a second processor arranged to interface with said dual-banked shared memory such that data can be bidirectionally exchanged between either memory bank and said second processor; said system arranged such that said first memory bank can be accessed and clocked by said first processor while said second memory bank is simultaneously accessed and clocked by said second processor, and such that said second memory bank can be accessed and clocked by said first processor while said first memory bank is simultaneously accessed and clocked by said second processor, such that data can be simultaneously transferred from said memory devices to said second processor and from said second processor to said memory devices via said dual-banked shared memory.