Patent ID: 7985622

Claim:
A method of forming collapse chip connection bumps on a semiconductor substrate, comprising: providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate; patterning a solder resist layer on the top surface of the semiconductor substrate to form a patterned solder resist layer; removing portions of the patterned solder resist layer to form a plurality of solder resist openings on the top surface of the semiconductor substrate; electrolessly plating a metal seed layer on a top surface of the patterned solder resist layer; electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate; disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate; and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.