Patent ID: 8228713

Claim:
An integrated circuit, comprising: a memory array comprising a plurality of bitcells having a static-random-access-memory (SRAM) architecture; a plurality of wordlines operatively connected to said plurality of bitcells; and wordline driver circuitry designed and configured to provide a wordline up-level voltage to each of said plurality of wordlines, said wordline driver circuitry including wordline up-level assist circuitry designed and configured to provide a plurality of selectable values for the wordline up-level voltage; wherein: said wordline up-level assist circuitry includes at least one pull-down device operatively coupled to at least one of said plurality of wordlines so that when said at least one pull-down device is activated, said at least one pull-down device pulls the wordline up-level voltage to one of said plurality of selectable values; said wordline up-level assist circuitry includes first and second pull-down devices operatively coupled to at least one of said plurality of wordlines and being independently selectable so as to provide multiple ones of said plurality of selectable values; and said first pull-down device has a pull-down strength and said second pull-down device has a pull-down strength that is about twice said pull-down strength of said first pull-down device.