Patent ID: 8037223

Claim:
A system comprising: a processor located on a system board; a system logic coupled to the processor; an input/output (I/O) connector coupled to the system logic via a host interface and configured to couple to an I/O card, the I/O card comprising a card field replaceable unit (FRU) memory and pins, the pins being configurable to allow for communication across the host interface or an external interface; and a management controller adapted to read the card FRU memory and a system FRU memory, the system FRU memory being located on the system board while the system is in a stand-by mode, the system FRU memory being separate from a main memory of the system, the card FRU memory storing configuration information for the I/O card and the system FRU memory storing configuration information for the system, where the management controller is adapted to configure the pins of the I/O card to operate with the system when the system is booted.