Patent ID: 7886244

Claim:
A computer program product comprising a computer useable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to: receive an integrated circuit design; receive a “don't care” (DC) adjusted list that identifies net segments that do not need to adhere to timing requirements; compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design; drive a value along a pathway to the at least one untimed net segment; monitor an output state value from the untimed net segment; verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment; determine whether there is a violation in the operation of the untimed net segment; determine whether downstream logic in the integrated circuit design uses the output value; and remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.