Patent ID: 6869845

Claim:
A method for manufacturing a semiconductor memory device having a memory region and a peripheral region, comprising: forming a memory cell on the memory region and a peripheral transistor on the peripheral region, the memory cell having a first gate electrode and a first diffusion layer, the peripheral transistor having a second gate electrode and a second diffusion layer; forming a silicon nitride layer above an upper surface and a side surface of the first gate electrode of the memory cell and above an upper surface and a side surface of the second gate electrode of the peripheral transistor; removing the silicon nitride layer that is formed above the upper surface of the second gate electrode of the peripheral transistor; forming an interlayer insulating film above the memory cell and the peripheral transistor; forming a first contact hole that reaches the upper surface of the second gate electrode of the peripheral transistor by removing a portion of the interlayer insulating film; and forming a conductive layer in the first contact hole that is electrically connected to the second gate electrode of the peripheral transistor.