Patent ID: 7516060

Claim:
A computer-implemented method of electronic circuit design, wherein the computer performing the following method steps, comprising: receiving a description of an electronic circuit design including a physical memory having a number of memory locations; determining a total number of memory operations that can occur in the physical memory during a predetermined period of time for simulating the electronic circuit design; initializing and storing a lookup table for modeling the physical memory in a storage memory of the computer during simulation of the electronic circuit design, the lookup table having a number of entries based on the total number of memory operations that can occur in the physical memory during the predetermined period of time; and simulating the electronic circuit design over the predetermined period of time using the description, the simulating including modeling the physical memory using the lookup table, wherein modeling the physical memory includes modeling a memory write operation to the physical memory, the modeling including: receiving a plurality of write address bits corresponding to a write address of the physical memory to which a plurality of write data bits are written by the electronic circuit design, receiving the plurality of write data bits, determining whether the lookup table includes a first entry that contains the plurality of write address bits in an address field and has a valid bit that is asserted, if the first entry contains the plurality of write address bits in its address field and has its valid bit asserted, writing the plurality of write data bits to a data field of the first entry, and if the first entry does not contain the plurality of write address bits in its address field and have its valid bit asserted: finding a second entry in the lookup table having a valid bit that is not asserted, writing the plurality of write address bits to an address filed of the second entry, and asserting the valid bit of the second entry.