Patent ID: 7057912

Claim:
A semiconductor device, comprising: a match line extending in a first direction; a first search line and a second search line extending in a second direction; a rewrite data line extending in said first direction; a comparison signal detecting circuit connected to said match line; and a plurality of memory cells each including a pair of first and second data retaining units, said first data retaining unit including a first transistor, a first storage node, and a first rewrite transistor, said second data retaining unit including a second transistor, a second storage node, and a second rewrite transistor; wherein: said first and second storage nodes each hold written entry data; said first transistor is connected to said first storage node and transfers said data held by said first storage node to said match line according to signal voltages of said search lines; said second transistor is connected to said second storage node and transfers said data held by said second storage node to said match line according to said signal voltages of said search lines; said first rewrite transistor is disposed between said first storage node and said rewrite data line; and said second rewrite transistor is disposed between said second storage node and said rewrite data line; wherein in a search operation, said semiconductor device performs steps of: generating, on said match line, a signal corresponding to a result of comparison between search key data entered from said search lines and said data held by said first and second data retaining units; and discriminating (detecting) said signal by use of said comparison signal detecting circuit; and wherein in a refresh operation on said data held by said first and second storage nodes, said semiconductor device performs steps of: sequentially activating said first and second search lines to generate, on said match line, a signal corresponding to said data held by said first and second data retaining units; discriminating said signal by use of said comparison signal detecting circuit; transferring said discriminated data to said rewrite data line; and writing said transferred data to said storage nodes through said rewrite transistors.