Patent ID: 8716083

Claim:
A method of fabricating an electrically programmable capacitor structure for an analog semiconductor integrated circuit, formed at a semiconductor surface of a body, comprising the steps of: forming isolation dielectric structures at selected locations of the semiconductor surface, the isolation dielectric structures defining active regions of the surface there between; forming a gate dielectric layer over the active regions; then forming an electrode layer comprised of polycrystalline silicon overall; removing selected portions of the electrode layer to define first and second electrodes comprised of polycrystalline silicon, the first electrode including a portion overlying an isolation dielectric structure and a plurality of portions overlying active regions; doping the polycrystalline silicon so that the first electrode has an n-type portion abutting a p-type portion at a first location; forming source and drain regions on opposite sides of a portion of the first electrode overlying a first active region; forming a layer of silicon dioxide over the first and second electrodes; removing the silicon dioxide selectively from the second electrode and from an opening at the first location of the first electrode, so that the silicon dioxide remains over the first electrode at locations other than the first location; after the step of removing the silicon dioxide, reacting exposed portions of the polycrystalline silicon, including the second electrode and at the first location of the first electrode, with a metal to form a metal silicide; then depositing a dielectric film overall; then depositing a conductor layer comprising a metal; and removing selected portions of the conductor layer to define a first conductive plate overlying a portion of the first electrode, at a location overlying an isolation dielectric structure, with the dielectric film and the silicon dioxide therebetween.