Patent ID: 8649990

Claim:
A method for detecting variation in semiconductor processes, comprising the following steps: collecting, respectively: a plurality of tool process data from a plurality of process tools, a plurality of first raw data associated with a wafer acceptance test (WAT) system, and a plurality of second raw data associated with a fault detection and classification (FDC) system; pre-processing said first raw data and said second raw data by an operation management unit; via a feature extract device, generating a plurality of correlation data by processing the first raw data using a first statistic analysis method, the first statistic analysis method being factor analysis (FA), wherein the steps of the FA for processing the plurality of first raw data comprise: selecting the plurality of first raw data, locating common potential factors causing a variation in the plurality of first raw data based on the plurality of first raw data, rotating the common potential factors of the plurality of first raw data in order to calculate the plurality of correlation data, wherein the common potential factors of the plurality of first raw data define a lowest bound of the variation in the plurality of first raw data so as to determine a number of common potential factor selection; via a latent variable extract device, identifying a plurality of global index data by processing the second raw data using a second statistic analysis method; via a variance detect device, building a plurality of interrelationship indices by processing the tool process data, global index data, and the correlation data using a third statistic analysis method; and identifying an essential reason causing such a semiconductor process variation based on the plurality of interrelationship indices by the operation management unit.