Patent ID: 7046075

Claim:
A semiconductor integrated circuit device comprising: a logic circuit including a plurality of areas, each of the areas including at least a first MOS transistor of a first conductivity type; a substrate bias control circuit to control a state of the logic circuit, an output impedance of the substrate bias control circuit to drive a substrate bias voltage of the first MOS transistor in a first state being lower than the output impedance of the substrate bias control circuit to drive the substrate bias voltage of the first MOS transistor in a second state; first and second power supply lines to supply the logic circuit with the supply voltage; a first substrate bias voltage supply line; a plurality of second MOS transistors of the first conductivity type, at least one of the second MOS transistors being provided to the plural areas; and an I/O circuit; wherein the control circuit controls the logic circuit to be in the first state when a supply voltage of the logic circuit is activated, wherein a source of the first MOS transistors is connected to the first power supply line, a drain of the first MOS transistor is connected to the second power supply line and the substrate bias voltage of the first MOS transistor is supplied via the first substrate bias voltage supply line, wherein a source-drain path of each of the second MOS transistors are provided between the first power supply line and the first substrate bias voltage supply line, wherein the plurality of the second MOS transistors are controlled to be ON state when the logic circuit is in the first state, and wherein a power source for supplying the substrate bias control circuit with a voltage to drive the MOS transistors of the first type is also used as a power source of the I/O circuit.