Patent ID: 8482988

Claim:
A method of operating a flash electrically erasable, programmable, read-only memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well terminal formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric and constructed in a manner to have an electric coupling to the charge storing layer, the method comprising the steps of: applying a first voltage bias of first polarity to the well terminal; allowing a first time period which may or may not equal zero to elapse; resetting the first voltage bias to zero while during the ramp down phase of said voltage; applying a second voltage bias of second polarity opposite to the first polarity to the control terminal; allowing a second time period to elapse; resetting the second voltage bias to zero.