Patent ID: 6870892

Claim:
In a diversity receiver with first and second channels having respective first and second digital signals therein, each of said first and second digital signals having respective first and second baud clock timing, said first baud clock timing defining the timing for sampling said first digital signal to recover a data symbol in said first channel, said second baud clock timing defining the timing for sampling said second digital signal to recover a data symbol in said second channel, said first and second baud clock timing having a common baud clock frequency, an apparatus for recovering said first and second baud timing comprising: a joint processing circuit responsive to said first and second digital signals; a first baud clock recovery circuit responsive to said joint processing circuit and said second digital signal for recovering said first baud clock timing in said first channel; a second baud clock recovery circuit responsive to said joint processing circuit and to said first digital signal for recovering said second baud clock timing in said second channel, whereby said first baud clock recovery circuit is responsive to said second baud clock recovery circuit to recover said first baud clock timing, wherein said diversity receiver further comprises a first phase detector responsive to said first digital signal for providing a first phase error signal, and a second phase detector responsive to said second digital signal for providing a second phase error signal; wherein said join processing circuit comprises: an adder having respective first and second input terminals, and an output terminal; said first phase error signal being coupled to said first input terminal of said adder; said second phase error signal being coupled to said second input terminal of said adder; and said output terminal of said adder being coupled to said first baud clock recovery circuit.