Patent ID: 7161868

Claim:
A semiconductor memory device having n ports each capable of accommodating reading and writing, n representing a natural number, comprising: a memory cell array having a plurality of memory cells arranged in a row and a column; n word lines associated with each row of said plurality of memory cells and selectively activated in accordance with a result of selection of a row in an operation performed to read and write through each of said n ports; a plurality of first bit lines having n thereof associated with each column of said plurality of memory cells, and each having corresponding column's memory cells connected thereto; and a plurality of second bit lines having n thereof associated with each column of said plurality of memory cells, and each forming a bit line pair together with one of said plurality of first bit lines, said n word lines including i first word lines selectively activated in accordance with a result of selection of a row in an operation performed to read and write through each of i ports, i being a natural number smaller than n, and (n−i) second word lines selectively activated in accordance with a result of selection of a row in an operation performed to read and write through each of (n−i) ports, each of said plurality of memory cells including a latch circuit having first and second storage nodes to hold first and second potentials complementarily, i first access transistors each arranged between said first storage node and one of i of said plurality of first bit lines and selectively turned on responsively when a corresponding one of said i first word lines is activated, (n−i) second access transistors each arranged between said second storage node and one of (n−i) of said plurality of first bit lines and selectively turned on responsively when a corresponding one of said (n−i) second word lines is activated, (n−i) second write access transistors and (n−i) second storage level drive transistors each arranged between said first storage node and said first potential in series and turned on in response to said corresponding one of said (n−i) second word lines being activated and a potential of a corresponding one of said plurality of second bit lines, respectively, and i first write access transistors and i first storage level drive transistors each arranged between said second storage node and said first potential in series, and selectively turned on in response to said corresponding one of said i first word lines being activated and a potential of a corresponding one of said plurality of second bit lines, respectively.