Patent ID: 7586780

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines arranged to correspond to the respective rows of the memory cells; and a plurality of bit lines arranged to correspond to the respective columns of the memory cells, wherein each of the memory cells has two access transistors and two inverters connected in a cross-coupled configuration to hold High data and Low data as a pair, wherein the two access transistors have respective gates connected to the corresponding word lines, respective sources, and respective drains, one of the source and the drain in each of the two access transistors being connected to the bit line and the other being connected to one of outputs of the inverter, each of the memory cells uses a potential of a High-data-holding power source for holding the High data as a first potential and uses a potential of a Low-data-holding power source for holding the Low data at any time other than a read operation as a second potential, the second potential is higher than a ground potential, and a potential of the selected one of the plurality of word lines is a fourth potential lower than a third potential obtained by adding up the second potential and a threshold voltage of each of the access transistors.