Patent ID: 8558594

Claim:
An integrated circuit comprising: a clock source configured to generate a clock signal; a clock tree configured to distribute the clock signal; and a plurality of functional units, wherein each of the plurality of functional units includes a plurality of leaf nodes each coupled to receive the clock signal from the clock tree, wherein at least one of the leaf nodes includes one or more flop circuits coupled to receive the clock signal from the clock tree, wherein each of the flop circuits includes: a data input, a data output, and a clock input, wherein the flop circuit is configured to receive, at the data input, data transmitted at a first data rate corresponding to a first clock frequency, and further configured to receive, at the clock input, the clock signal at a second clock frequency that is one half the first clock frequency; wherein the flop circuit is configured to transmit a first bit of data on the data output responsive to a first edge of the clock signal and is further configured to transmit a second bit of data on the data output responsive to a next edge of the clock signal subsequent to the first edge; wherein each of the flop circuits includes a first latch coupled to the data input and a second latch coupled to the data input, wherein the first latch is configured to latch data responsive to the first edge of the clock signal and wherein the second latch is configured to latch data responsive to the second edge of the clock signal; and wherein each of the flop circuits further comprises a multiplexer having a first input coupled to an output of the first latch and a second input coupled to an output of the second latch, wherein the multiplexer is configured to select the first input responsive to the second edge of the clock signal and further configured to select the second input responsive to the first edge of the clock signal.