Patent ID: 6934199

Claim:
A write receiver control circuit for use in a memory device to operate a plurality of write receivers in either a high-power, low write latency mode or a low-power, high write latency mode, the write receiver control circuit comprising a logic circuit receiving a first signal indicative of whether the high-power, low write latency mode has been enabled, and a second signal indicative of whether read transmitters are active, the logic circuit being operable responsive to the first signal indicating that the high-power, low write latency mode has been enabled to apply power to the write receivers when the read transmitters are not active regardless of whether the write receivers are active, and to remove power from the write receivers when the read transmitters are active, the logic circuit further being operable responsive to the first signal indicating that the high-power, low write latency mode has not been enabled to apply power to the write receivers when the write receivers are active and the read receivers are not active, and to remove power from the write receivers when either the write receivers are not active or the read transmitters are active.