Patent ID: 7587557

Claim:
A data sharing apparatus comprising: a data bus having a data width; a memory which stores data according to a first-endian byte order; a first-endian processor logically connected to said memory in the first-endian byte order via said data bus, wherein said first-endian processor executes a first program that utilizes the first endian byte order in which data is defined as being in a defined order; a second-endian processor logically connected to said memory in the first-endian byte order via said data bus, wherein said second-endian processor executes a second program that utilizes a second endian byte order in which data that is smaller than the basic word length is defined to be in an order that is reverse of the defined order of the first endian byte order; and an address conversion unit operable: (i) to invert values of two least significant bits of an address outputted from said second-endian processor and output an address including the inverted values to said memory when said second-endian processor performs a memory access for 8-bit data; (ii) to invert a value of a second least significant bit of an address outputted from said second-endian processor and output an address including the inverted value to said memory when said second-endian processor performs a memory access for 16-bit data; and (iii) to output an address from said second-endian processor to the memory without address conversion when said second-endian processor performs a memory access for data having the width of the first data bus.