Patent ID: 8138039

Claim:
A method of fabricating a vertical semiconductor transistor, said method comprises: providing a semiconductor substrate; forming a polysilicon pillar on the substrate; using the thickness of a first film layer to define a first source/drain region of the transistor as the top portion of the pillar; forming a spacer layer around the top portion of the pillar; using the thickness of a second film layer to define a channel region of the transistor as the central portion of the pillar and to align a transistor gate with the channel region of the transistor; depositing a dielectric layer on the pillar in alignment with the channel region of the transistor; forming the transistor gate in alignment with the channel region of the transistor, wherein the transistor gate is formed to surround the pillar with the dielectric layer between a conductive material and the pillar; using the thickness of the spacer layer around the top portion of the pillar to define the thickness of the transistor gate, a top portion of the transistor gate being underneath a bottom portion of the spacer layer; and defining a second source/drain region of the transistor as the bottom portion of the pillar using the thickness of a third film layer.