Patent ID: 6983361

Claim:
A method of implementing a switch instruction in an IA 64 architecture based data processing device, comprising: receiving a call to the switch instruction, the call including one or more parameters for the switch instruction, wherein the one or more parameters includes a range of branch address, the range being defined by a high value and a low value; loading a plurality of predicate registers with values associated with a plurality of branch addresses based on the one or more parameters; calling an instruction associated with one of the plurality of branch addresses based on the values of the plurality of predicate registers; determining if the low value is lower than a lowpredicate; setting a first register value to 2**(lowpredicate-low value) if the low value is lower than the lowpredicate; and setting the first register value to 2**(lowpredicate) if the low value is not zero, where lowpredicate is a predicate register number of a lowest numbered predicate register.