Patent ID: 7499372

Claim:
A semiconductor memory device, comprising: a sequentially accessed non-volatile memory array that has a plurality of data storage rows of a specified address unit; write data holding module that holds write data of a data capacity correlating to n times (n is an integer of 2 or greater) the specified address unit in the specified address units, the data being the write data to be written to the memory array; data writing module that writes in the specified address unit the held write data to the subject data storage row that is subject to writing in the memory array; data verification module that determines whether or not the already written data of the specified address unit written to the subject data storage row and the write data of the specified address unit held in the write data holding module match; and a control unit that, when the already written data and the write data do not match, does not execute writing of the remaining write data to the next data storage row of the subject data storage row using the data writing module.