Patent ID: 7941782

Claim:
A pattern layout of an integrated circuit comprising: a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed in a direction parallel to one another and uniformly and repeatedly arranged with constant width at a pitch with a constant interval and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly and repeatedly arranged, the non-uniformly repeated pattern group being positioned adjacent to an end portion of the uniformly repeated pattern group and in the parallel direction, and a second device pattern arranged adjacent to the non-uniformly repeated pattern group and opposite to the uniformly repeated pattern group with respect to the non-uniformly repeated pattern group, arranged in parallel to the first device pattern and having second lines and second spaces whose widths are larger than widths of the first lines and first spaces of the non-uniformly repeated pattern group, wherein at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group in the first device pattern is made larger than one of the width of the first line and the width of the first space of the uniformly repeated pattern group.