Patent ID: 8023909

Claim:
In a radio frequency (RF) first chip associated with a power amplifier module of a mobile wireless telecommunication device, a circuit for using a bidirectional serial interface to transfer a digital representation of an analog value, the serial interface providing a transfer clock signal only during a data transfer operation, the data transfer operation having sequential address and data portions, the circuit comprising: a timing circuit, the timing circuit receiving the transfer clock signal from a second chip of the mobile wireless telecommunication device during a read operation and generating a conversion clock signal in response to the transfer clock signal during an address portion of the read operation; an analog-to-digital converter (ADC), the ADC converting the analog value to a digital output in response to the conversion clock signal during the address portion of the read operation; and an output circuit, the output circuit transferring the digital output of the ADC to the second chip via the serial interface during a data portion of the read operation.