Patent ID: 8615640

Claim:
An apparatus comprising: a controller configured to generate control signals in response to one or more input requests, said controller including a write-back cache; and an array comprising a plurality of solid state devices, wherein said apparatus is configured to (i) read and/or write data in response to said control signals received from said controller, (ii) store all of said data in said write-back cache before writing to said array, (iii) provide a rank table to rank lines in said write-back cache from a most efficient write to a least efficient write based on a number of logical block addresses that are stored in each of said lines, (iv) store a copy of a mapping table for each of said plurality of solid state devices on said controller, and (v) distribute writes to a selected one or more of said plurality of solid state devices such that each of said solid state devices completes the most efficient write operation first by combining two or more of said writes when flushing data from said write-back cache to said selected solid state devices based on an indication of availability of storage space of said plurality of said solid state devices stored in said copy of said mapping tables and said rank table.