Patent ID: 8473891

Claim:
A method of defining the physical layout of functional blocks and one or more interconnections in an integrated circuit, comprising the steps of: arranging the layout of functional blocks in a rectangular portion of a physical layout of an integrated circuit using a computer; routing a plurality of interconnections among the functional blocks in the physical layout, each of the plurality of interconnections comprising a plurality of orthogonal wire segments, each wire segment extending parallel to a side of the rectangular portion using a computer; assigning a first reference frame extending in a first direction parallel to a side of the rectangular portion, and with which one or more functional blocks and one or more wire segments extending in the first direction within the first reference frame are associated, the first reference frame having a reference line at a specified position in a second direction perpendicular to the first direction, and the position of each of the functional blocks and wire segments associated with the first reference frame specified by respective offset values relative to the reference line using a computer; and after the routing and assigning steps, responsive to receiving a user input indicating a desired movement of the first reference frame in the second direction, adjusting the specified position of the reference line while maintaining constant the offset values of the functional blocks and wire segments associated with the first reference frame using a computer.