Patent ID: 7566650

Claim:
An integrated circuit solder bumping method, comprising: providing a substrate; forming a redistribution layer on the substrate; forming an insulation layer on the redistribution layer, the insulation layer having a plurality of openings therethrough; depositing a first UBM layer of titanium on the insulation layer and in the openings therethrough; depositing a second UBM layer of chromium/copper alloy on the first UBM layer; depositing a third UBM layer of copper on the second UBM layer; forming UBM pads of at least two different sizes from the UBM layers; printing solder paste over at least some of the UBM pads; reflowing the solder paste to form at least smaller solder bumps on at least some of the UBM pads; and forming bigger solder bumps on at least some of the UBM pads.