Patent ID: 7436203

Claim:
An integrated circuit arrangement that is arranged to receive an input signal, wherein the input signal includes a common-mode portion and a differential-mode portion, the integrated circuit comprising: a first bond pad that is coupled to a first port of the integrated circuit; a second bond pad that is coupled to a second port of the integrated circuit, wherein the first port and the second port are arranged to receive the input signal; a first terminating impedance that is coupled between a first node and a common node; a second terminating impedance that is coupled between a second node and the common node, wherein the common node is arranged as a ground reference potential; an on-chip transformer arrangement that includes a first inductor that is coupled between the first bond pad and the first node and a second inductor that is coupled between the second bond pad and the second node, wherein the first inductor is mutually inductively coupled to the second inductor, wherein the on-chip transformer is arranged such that common-mode portions of the input signal are effectively shorted through the first and second inductors to the ground reference potential via the first and second terminating impedances, and wherein the on-chip transformer is further arranged such that differential-mode portions of the input signal are effectively blocked from the first and second terminating resistors.