Patent ID: 8178918

Claim:
A charge trap type non-volatile memory device, comprising: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer directly contacting with sidewalls of the charge trap layer and provided to isolate the charge trap layer, wherein a thickness of the charge trap polysilicon thin layer is smaller than a thickness of the charge trap nitride-based layer, the charge trap polysilicon thin layer has a recess portion, the oxide-based spacer formed over the sidewalls of the charge trap layer extends inwardly to the recess portion of the charge trap polysilicon thin layer, and a lower surface of the charge trap nitride-based layer exposed by the recess portion slopes towards the charge trap polysilicon thin layer.