Patent ID: 7346757

Claim:
An advanced processor for executing software applications on different operating systems, comprising: a plurality of processor cores each configured to execute multiple threads, a memory management unit (MMU) coupled to said processor cores having first, second, and third translation-lookaside buffer (TLB) portions operable in at least a partitioned mode and a global mode; each TLB portion having a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification; wherein: the first and second TLB portions are configured to allow a thread to freely allocate entries in the respective first or second TLB portion in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode; wherein each of the plurality of processor cores includes a data cache and an instruction cache; a plurality of different operating systems each running on one of the plurality of processor cores; a data switch interconnect ring arrangement directly coupled with the data cache of each of the plurality of processor cores and configured to pass memory related information among the plurality of processor cores; and a messaging network directly coupled with the instruction cache of each of the plurality of processor cores and a plurality of communication ports.