Patent ID: 7589745

Claim:
An image signal processing circuit, comprising: a line buffer for storing image signals per each line; a frame memory capable of storing the image signals for plural lines; and a control circuit which controls the line buffer and the frame memory, wherein the control circuit performs the controlling such that the image signals for plural lines stored in the frame memory are outputted to the line buffer in an order opposite to an order of storing of lines in the frame memory, the image signals outputted from the frame memory are stored in the line buffer, and the image signals stored in the line buffer are outputted in an order opposite to the order of inputting of the image signals into the line buffer, and wherein the control circuit performs the controlling such that: (a) when the image signals stored in the frame memory are output, a part of the image signals stored is outputted to the line buffer in the same order as the order of inputting of lines into the frame memory, while the other part of the image signals is outputted to the line buffer in an order opposite to the order of inputting of lines into the frame memory; and (b) a part of the image signals stored in the line buffer is outputted in the same order as the order of inputting of lines into the line buffer, while the other part of the image signals stored in the line buffer is outputted in an order opposite to the order of inputting of lines into the line buffer.