Patent ID: 8497549

Claim:
A shielded gate field effect transistor, comprising: a trench extending into a semiconductor region; a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric comprising a shield portion of a first dielectric layer, at least a shield portion of a second dielectric layer, and a third dielectric layer, the first dielectric layer disposed in both the lower portion of the trench and an upper portion of the trench and disposed, at least in part, between the second dielectric layer and the semiconductor region, the second dielectric layer disposed, at least in part, between the first dielectric layer and the third dielectric layer, the second dielectric layer comprising a material configured to inhibit growth of oxide along a surface of the semiconductor region covered by the second dielectric layer, and the third dielectric layer disposed in the lower portion of the trench and not disposed in the upper portion of the trench; an inter-electrode dielectric disposed between the shield electrode and a gate electrode, the gate electrode being disposed in the upper portion of the trench; and a gate dielectric lining an upper portion sidewall of the trench and comprising a gate portion of the first dielectric layer, the inter-electrode dielectric having a thickness that is greater than a thickness of the gate dielectric.