Patent ID: 7560758

Claim:
A semiconductor device comprising: a metal-oxide-semiconductor field effect transistor (MOSFET) including source and drain regions located in a semiconductor substrate, the source and drain regions separated by a channel of the MOSFET, a gate structure including at least one spacer abutting the gate structure, said source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of said semiconductor substrate, the entire recesses being separated from a portion of the semiconductor substrate underlying the gate structure by another portion of the semiconductor substrate underlying the at least one spacer, and wherein a stress-inducing dielectric layer located over said one or more slanted sidewall surfaces of said recesses at said source and drain regions, wherein a portion of stress-inducing dielectric layer is located within said semiconductor substrate beneath a level of said upper surface of said semiconductor substrate and applies stress to the channel of said MOSFET.