Patent ID: 7102192

Claim:
A semiconductor nonvolatile memory cell array comprising: a plurality of semiconductor nonvolatile memory cells, each including: a semiconductor substrate of a first conductive type; a control electrode provided on said semiconductor substrate via an insulation layer; a pair of impurity diffusion regions of a second conductive type provided on said semiconductor substrate on opposite sides of said control electrode to provide first and second main electrodes; a channel region provided on said semiconductor substrate below said control electrode at a time of transistor operation; a pair of variable resistance sections of a second conductive type provided between said channel region and said impurity diffusion regions, respectively, and having an impurity density lower than that of said impurity diffusion regions; and a pair of charge storage sections provided one on each of said variable resistance sections; at least one word line electrically connected to said control electrodes of said semiconductor nonvolatile memory cells; at least one bit line provided perpendicular to said word line and composed of said impurity diffusion regions; and at least one layer insulation layer provided between said charge storage sections and said word line.