Patent ID: 7656207

Claim:
A DLL (delay locked loop) circuit comprising: a delay circuit comprising a plurality of delay cells and delaying an external clock signal by a predetermined time in response to a comparison signal to generate an internal clock signal; a replica circuit outputting a first signal that is obtained by delaying the internal clock signal by a data-path delay time; and a phase detector generating the comparison signal corresponding to a phase difference between the external clock signal and the first signal, wherein the phase detector generates a first comparison signal used by the delay circuit to delay the external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time, wherein the delay circuit comprises a plurality of shift registers corresponding respectively to the delay cells and being connected in series, and wherein the units of the first cell delay time are generated by first connections connecting the shift registers adjacent to each other, and the units of the second cell delay time are generated by a second connection connecting the shift registers spaced apart from each other.