Patent ID: 8076190

Claim:
A method of forming a semiconductor device to be used in very large scale integrated circuit (VLSI) applications, said method comprising: forming a dielectric oxide layer on a substrate and etching said dielectric oxide layer to form a pattern of parallel oxide isolations on said substrate; forming nitride spacers on each side wall of said parallel oxide isolations, such that gaps remain between adjacent ones of said nitride spacers formed on side walls of adjacent ones of said parallel oxide isolations; forming silicon pillars in said gaps; removing said nitride spacers by directional reactive ion etching, such that said silicon pillars form a plurality of planarized fin bodies, said plurality of planarized fin bodies being selectively apportioned between a first portion and a second portion of said plurality of planarized fin bodies; forming a fin field effect transistor (FinFET) from said first portion of said plurality of planarized fin bodies; forming a fin capacitor from selected ones of said second portion of said plurality of planarized fin bodies, said fin capacitor including a top electrode formed by a deposited conductor on a top surface of a planarized fin body of said selected ones said second portion of said plurality of planarized fin bodies; and forming a metal interconnect between said FinFET and said top electrode of said fin capacitor.