Patent ID: 6998348

Claim:
A method for manufacturing semiconductor-integrated electronic circuits comprising: depositing an auxiliary layer onto a substrate; depositing a layer of a screening material onto said auxiliary layer; selectively removing said layer of screening material to provide a first opening in said layer of screening material and expose an area of said auxiliary layer; removing said area of said auxiliary layer to form a second opening having sidewalls in said auxiliary layer, the second opening having a cross-section that narrows toward said substrate so that an area of said substrate is exposed, the exposed area of the substrate being smaller than the area exposed by the first opening, wherein forming said second opening in said auxiliary layer includes removing said auxiliary layer and simultaneously forming spacers effective to form the sidewalls of said second opening, wherein said auxiliary layer is removed through an anisotropic plasma etching including a component for removing said auxiliary layer and a component for micro-depositing said spacers, wherein said anisotropic plasma etching comprises using a CF 4 /CH 2 F 2 /O 2 etching plasma; and using the sidewalls of the second opening to mask a vertical etching of the exposed area of the substrate, while substantially retaining a size of the second opening.