Patent ID: 8519520

Claim:
A semiconductor package including co-packaged high-side (HS) and low-side (LS) semiconductor chips, comprising: a conductive lead frame comprising a die paddle and a plurality of pins set around the die paddle; a LS semiconductor chip comprising a top source, a top gate and a bottom drain; a HS semiconductor chip comprising a top source, a top gate and a bottom drain, wherein a plurality of conductive source balls are formed on its top source and a plurality of conductive gate balls are formed on its top gate, wherein the LS semiconductor chip is connected to a front surface of the lead frame with bottom drain of the LS semiconductor chip electrically connected to a top surface of the die paddle, and wherein the HS semiconductor chip is connected to a back surface of the lead frame with top source of the HS semiconductor chip electrically connected to a bottom surface of the die paddle through the plurality of conductive source balls; and a package body encapsulating the LS semiconductor chip, the die paddle of lead frame, and the HS semiconductor chip, wherein the backside of the HS semiconductor chip is: (a) exposed out of a backside of the package body; and (b) located substantially coplanar to the end of the lead frame pins exposed out from the semiconductor package.