Patent ID: 6951807

Claim:
A semiconductor device manufacturing method, comprising: embedding an under interconnection layer in an interlayer insulating layer such that a surface thereof is exposed to substantially the same plane as a surface of said interlayer insulating layer; forming a diffusion preventive layer to prevent diffusion of a metal included in said under interconnection layer, on at least said under interconnection layer; forming a first nitrogen-doped silicon oxide layer on said diffusion preventive layer so as to have a substantially constant refractive index falling in a range between 1.50 (inclusive) and 1.55 (inclusive) throughout said first nitrogen-doped silicon oxide layer; forming a fluorine-doped silicon oxide layer on said nitrogen-doped silicon oxide layer; forming an interconnection groove and a via hole extending from a bottom of said interconnection groove above said under interconnection layer in said fluorine-doped silicon oxide layer; and forming a plug in said via hole with a metal layer, to be in electrical contact with said under interconnection layer, and an upper interconnection layer in said interconnection groove with said metal layer, to be in electrical contact with said plug.