Patent ID: 8447931

Claim:
A processor with a register file that supports multiple-issue execution, comprising: the processor configured to issue multiple instructions simultaneously; the register file within the processor, wherein the register file contains an array of memory cells, which contain bits for architectural registers of the processor; wherein the register file includes multiple read ports and multiple write ports to support multiple-issue execution; wherein if multiple read ports simultaneously read from a given register, for each memory cell in the given register, the register file is configured to, drive a bit stored in a storage element of the memory cell from the storage element to a corresponding set of pass transistors using a driver coupled between the storage element and the set of pass transistors; selectively forward the bit from the driver through a pass transistor in the set of pass transistors to a single read bitline in a corresponding set of read bitlines; capture the bit from the read bitline using a latch; forward the captured bit from the latch to one or more multiplexers that selectively drive the bit to a corresponding read port; whereby each memory cell only has to drive the single read bitline (instead of multiple read bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.