Patent ID: 8032910

Claim:
A system comprising: at least one first input component for receiving a first transport stream from an external source; at least one second input component for receiving a second transport stream from a memory; and at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder; wherein the at least one second input component comprises: a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the second transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein: when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface, the valid signal indicates that at least one byte read from the buffer is valid, and the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.