Patent ID: 8350312

Claim:
A semiconductor device comprising: a stacked structure portion formed by sequentially laminating a first insulating film, first conductive layer, second insulating film and second conductive layer in an order described above on a semiconductor substrate, the first conductive layer and the second conductive layer being electrically connected via a groove formed in the second insulating film, an interlayer insulating film formed to electrically separate the second conductive layer into a first region of a small area including a connecting portion with the first conductive layer and a second region of a large area that does not include the connecting portion, a first element isolation insulating film formed in one peripheral portion on the second region side of the stacked structure portion, the first element isolation insulating film being buried and formed in portions of the semiconductor substrate, first insulating film and first conductive layer, a first contact plug formed on the first region, a second contact plug formed on the second region, the second contact plug being formed above the first element isolation insulating film, and a third contact plug formed on the semiconductor substrate, the third contact plug being formed in a region adjacent to a peripheral portion different from the one peripheral portion on the second region side of the stacked structure portion.