Patent ID: 8364977

Claim:
A method for processing a sequence of n-state symbols in binary form with a Linear Feedback Shift Register (LFSR), the LFSR including a plurality of outputs to provide an n-state symbol in binary form, each output enabled to provide a signal representing a bit, comprising: performing the processing belonging to the group consisting of scrambling, descrambling and sequence generation; and as part of performing the processing belonging to the group consisting of scrambling, descrambling and sequence generation, applying the LFSR for processing the sequence of n-state symbols in binary form, each n-state symbol of the sequence able to assume one of n states with n=2 p and p equal to or greater than 2 and an n-state symbol being represented by at least p bits, the LFSR implements in binary form an n-state logic function defined by an n-state truth table which determines an n-state output state of the n-state logic function as a result of a first and a second input of the n-state logic function each enabled to assume each one of n states and wherein the n-state logic function is implemented with at least one reversible binary logic function which is an EQUALITY (=) function, and wherein application of the EQUALITY function by the LFSR in performing the processing belonging to the group consisting of scrambling, descrambling and sequence generation affects an output sequence of n-state symbols that is output by the LFSR.