Patent ID: 7472329

Claim:
A shift register comprising: a plurality of blocks, each of the plurality of blocks includes a plurality of shift unit circuits for shifting a input signal in sequence in synchronization with a clock signal and an inverted clock signal thereof and outputting an output signal; and a unit control circuit that receives all signals output from or input to the plurality of shift unit circuits for specifying an operation period for which any one of the plurality of shift unit circuits is operated and for supplying the clock signal and the inverted clock signal to the plurality of shift unit circuits in the specified period, on the basis of all the signals output from or input to the plurality of shift unit circuits, the unit control circuit has clock control signal generating means for performing the logical sum operation of the periods for which the input signals and the output signals of the plurality of shift unit circuits become an active state and for generating a clock control signal for specifying the operation period based on the operation results, and supply means for supplying the clock signal and the inverted clock signal to the plurality of shift unit circuits according to the clock control signal, the start pulse becomes active at the high level, the clock control signal generating means has a plurality of NOR circuits, and a NAND circuit for performing the inverted logical product operation of the output signals output from the plurality of NOR circuits and outputting it as the clock control signal, and input terminals of the plurality of NOR circuits are supplied with all the input signals and the output signals of the plurality of shift unit circuits, respectively.