Patent ID: 6931723

Claim:
A parallel joining technology method for making a multi-layer electronic structure, the method comprising: providing a plurality of sub-composites, wherein each said sub-composite is formed by the steps of: providing a layer of dielectric material having a first surface and a second surface, wherein said first surface is selected from the group consisting of a top surface and a bottom surface, providing a layer of electrically conducting material on said first surface; forming at least one blind via comprising a passage from said second surface through said dielectric layer to expose said layer of electrically conducting material facing said dielectric layer; depositing electrically conducting metallurgical material in at least one of said blind vias wherein said electrically conducting layer is in electrical contact with said electrically conductive metallurgical material in said at least one blind via; removing portions of the layer of electrically conducting material to define a pattern of circuitry; stacking a plurality of said sub-composites, wherein a void is defined between adjacent sub-composits; aligning said plurality of sub-composites; joining said plurality of sub-composites such that the electrically conducting metallurgical material in at least one of said blind vias makes electrical contact by forming a metallurgical bond to the conductive pattern on an adjacent sub-composite; flowing an un-cured resin into said voids, and forming an electric insulator by curing said resin.