Patent ID: 8015540

Claim:
A system for intelligent placement of dummy fill patterns in an integrated circuit fabrication process, comprising: means for obtaining layout information of the integrated circuit, the integrated circuit including a plurality of layers; means for selecting a first layer and a second layer, wherein the second layer is placed successively to the first layer; means for obtaining initial layouts of metal lines on the first layer and the second layer; means for determining a first dummy fill space based on the initial layout on the first layer, the first dummy fill space suitable for including a plurality of dummy fill features on the first layer; means for determining a second dummy fill space based on the initial layout on the second layer, the second dummy fill space suitable for including a plurality of dummy fill features on the second layer; means for determining an overlap between the first dummy fill space and the second dummy fill space; and means for minimizing the overlap by arranging the plurality of first dummy fill features and the plurality of second dummy fill features, wherein the integrated circuit includes the first layer and the second layer.