Patent ID: 7053653

Claim:
A routing structure for connecting a plurality of field programmable gate array tiles wherein each of said of said plurality of field programmable gate arrays tile includes a plurality of functional groups wherein each of said plurality of functional groups is configured to receive at least one input signal, and generate at least one output signal, a plurality of interface groups wherein each of said plurality of interface groups is configured to selectively transfer signals between said routing structure and circuitry external to the field programmable gate array tile; said routing structure comprising: a primary routing structure including a horizontal bus and a vertical bus wherein the primary routing structure is coupled to said plurality of functional groups and plurality of interface groups, and is configured to receive signals from said plurality of functional groups and said plurality of interface groups and provide signals between said plurality of functional groups and said plurality of interface groups; a horizontal buffer comprising a horizontal, segmented bus; and a horizontal, non-segmented bus coupled to said horizontal buffer wherein said horizontal buffer connects a primary routing structure in a first one of said plurality of field programmable gate array tiles in a first column and to a primary routing structure in a second one of said plurality of field programmable gate array tiles in a second column adjacent to said first column, wherein said horizontal buffer is coupled to said horizontal bus in the primary routing structure in a first one of said plurality of field programmable gate array tiles in the first column and to said horizontal bus of the primary routing structure in the second one of said plurality of field programmable gate array tiles in the second column; and a vertical buffer connecting the primary routing structure in a first one of said plurality of field programmable gate array tiles in a first row to a primary routing structure in a second one of said plurality of field programmable gate array tiles in a second row adjacent to said first row.