Patent ID: 7385282

Claim:
A stacked-type chip package structure, comprising: a substrate; a first chip disposed on the substrate, the first chip having a plurality of first bonding pads disposed on an active surface thereof; a plurality of bonding wires, wherein the first bonding pads are electrically connected to the substrate through the bonding wires, wherein the bonding wires are electrically and physically attached to the first bonding pads, respectively; a second chip disposed above the first chip, the second chip having a plurality of second bonding pads disposed on an active surface thereof; and a plurality of B-stage conductive bumps, wherein the second bonding pads of the second chip are electrically connected to the first bonding pads of the first chip through the B-stage conductive bumps respectively, and each B-stage conductive bump covers a portion of the corresponding bonding wire physically attached to at the first bonding pads of the first chip.