Patent ID: 8831140

Claim:
A dedicated serial interface for use in a programmable logic device, said serial interface having a channel and operating at a clock rate, and comprising: a receiver portion in said serial interface operable under a plurality of protocols in both a first data rate mode in which data is received at a first data rate substantially equal to said clock rate and a second data rate mode in which data is received at a second data rate substantially equal to an integer multiple of said clock rate; rate negotiation circuitry in said serial interface for determining in said serial interface, without regard to which of said plurality of protocols said serial interface is operating under, which of said first and second data rate modes said receiver portion is operating in, based on a number of single-bit transitions detected in said received data within a predetermined duration; and clock data recovery circuitry in said serial interface that extracts, from said received data, a clock at said clock rate; wherein: said clock data recovery circuitry cooperates with said rate negotiation circuitry to determine which of said modes said receiver portion is operating in; said clock data recovery circuitry comprises a bang-bang phase detector; said bang-bang phase detector detects said single-bit transitions; and said bang-bang phase detector comprises: four first-stage registers, each of which is respectively clocked by a respective quadrature phase of said recovered clock, said four first-stage registers outputting four respective first-stage signals representing delayed phases of said received data, and six second-stage registers, said six second- stage registers comprising a first group of three registers clocked by a second (90°) quadrature phase of said recovered clock, and a second group of three registers clocked by a fourth (270°) quadrature phase of said recovered clock; said registers in said first group receive first, second and third ones of said delayed phases of said received data; said registers in said second group receive third, fourth and first ones of said delayed phases of said received data; and predetermined states of said six second-stage registers in one of two successive clock cycles signify to said rate negotiation circuitry that said receiver portion is operating in a particular one of said first and second modes.