Patent ID: 7995390

Claim:
A NAND flash memory array, comprising: a plurality of bit lines formed with a plurality of silicon square pillars of a specific height being in a row at specific intervals on a silicon substrate respectively, and filled with a plurality of insulating square pillars between silicon square pillars in a vertical direction with the bit lines to form a plurality of trenches having same width as the each specific interval; a plurality of cut-off gate lines formed in the lower part of the each trench, wherein a first insulating layer is placed between the each cut-off gate line and the each trench; a second insulating layer formed at the exposed parts of the each silicon square pillar and the each cut-off gate line; a plurality of charge storage layers formed over both side walls of the each silicon square pillar, wherein the second insulating layer is placed between the side wall and the charge storage layer; a third insulating layer formed on the upper part of the each charge storage layer and at the exposed parts of the second insulating layer; and a plurality of word lines formed on the upper part of the third insulating layer, filling up the each trench, wherein the upper part of the each silicon square pillar is doped with specific impurities and functions as a source or a drain.