Patent ID: 7746707

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell section including a NAND cell unit including memory cells connected in series; a plurality of word lines connected to gate electrodes of the memory cells; an erasing circuit configured to erase data stored in selected memory cells; and an erase detecting circuit configured to detect whether each of threshold voltages of the selected memory cells is negative; an over-erase detecting circuit configured to detect whether each of threshold voltages of the selected memory cells is over-erased; and a soft-programming circuit configure to perform a soft-program operation on at least a part of the selected memory cells after an erase operation by said erasing circuit, wherein the soft-program operation is performed simultaneously on both at least a part of first memory cells connected to a first word line and at least a part of second memory cells connected to a second word line, and at least one of the selected memory cells that is detected by the over-erase detecting circuit as over-erased is included in the first memory cells or the second memory cells.