Patent ID: 8028152

Claim:
A hierarchical microprocessor comprising: a plurality of second-level instruction pipeline elements, the second-level instruction pipeline elements including a second-level store buffer; a plurality of execution clusters, each execution cluster being operatively coupled with each of the second-level instruction pipeline elements and including: a plurality of first-level instruction pipeline elements, wherein each of the first-level instruction pipeline elements corresponds with a respective second-level instruction pipeline element; and one or more instruction execution units operatively coupled with each of the first-level instruction pipeline elements, wherein: the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements, the plurality of second-level instruction pipeline elements, and the plurality of execution clusters; the microprocessor is configured to virtualize one or more of the multiple execution threads to create respective virtual threads; and the microprocessor is configured to execute the virtual threads in a time-multiplexed fashion; the plurality of first-level instruction pipeline elements each include a store buffer that includes one or more entries that are capable of storing age information that comprises at least one of a definition time or a kill time; and the microprocessor is further configured to store a definition time reflecting a current time at which a respective entry is written into a first-level store buffer and to store a kill time that reflects when another entry in the first-level store buffer is subsequently written to that has a matching same address as the respective entry.