Patent ID: 7080216

Claim:
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array, wherein each memory cell comprises an array of single bit storage units; a first set of word lines extending in the first dimension, each word line of the first set of word lines running along a row and being connected to each storage unit located in that row for enabling those storage units for reading or writing; a second set of word lines extending in the second dimension, each word line of the second set of word lines running along a column and being connected to each storage unit located in that column for enabling those storage units for reading or writing; a set of bit lines running diagonally to the word lines, each bit line being connected to one storage unit in each row and to one storage unit in each column for carrying data to or from the respective storage unit; and a processing unit for executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of the second instruction part as specifying a group of cells all of which are located in the same row but in different columns, and to interpret a second form of the second instruction part as specifying a group of cells all of which are located in the same column but in different rows.