Patent ID: 8725900

Claim:
A processing pipeline having a plurality of processing stages, the processing pipeline comprising: a first processing stage circuit configured to store a data block received by the processing pipeline, the data block including i) a data packet, and ii) a dummy header portion and a dummy tail portion each added to the data packet prior to the data block entering the processing pipeline, wherein the dummy header portion and the dummy tail portion added to the data packet are empty of data, store, separately from the data block, additional information associated with the data block, the additional information indicating i) a length of the data packet within the data block, and ii) a position of the data packet within the data block with respect to the dummy header portion and the dummy tail portion, without modifying a length of the data block, either i) add data to at least one of the dummy header portion and the dummy tail portion to increase the length of the data packet, or ii) subtract data from the data packet to decrease the length of the data packet, and modify the additional information to reflect i) the data added to the at least one of the dummy header portion and the dummy tail portion, or ii) the data subtracted from the data packet; a second processing stage circuit subsequent to the first processing stage circuit, the second processing stage circuit configured to if data was added to the at least one of the dummy header portion and the dummy tail portion, selectively remove, based on the modified additional information, portions of the dummy header portion and the dummy tail portion that do not include the data added to the at least one of the dummy header portion and the dummy tail portion, and if data was subtracted from the data packet, selectively remove, based on the modified additional information, the dummy header portion, the dummy tail portion, and the portions of the data packet that corresponded to the data subtracted from the data packet; and a register configured to store i) the length of the data packet as a length n and ii) a position of the data packet within the data block with respect to the dummy header portion and the dummy tail portion as an offset m, wherein m corresponds to a length of the dummy header portion, wherein the register is configured to, to modify the additional information to reflect the data added to the at least one of the dummy header portion and the dummy tail portion, store the length of the data packet as a length n+q+p, wherein a corresponds to a length of data added to the dummy tail portion and p corresponds to a length of data added to the dummy header portion, and store the position of the data packet within the data block with respect to the dummy header portion and the dummy tail portion as an offset m−p.