Patent ID: 6917558

Claim:
A content addressable memory for making a comparison between input information and retrieval information, comprising: a memory array including a plurality of memory cell rows storing said retrieval information, and a redundant memory cell row repairing a faulty memory cell row; a first shift circuit shifting; if necessary, each of at least one memory cell row to be accessed in a first direction during data reading and data writing; a second shift circuit shifting each of said at least one memory cell row shifted in said first direction by said first shift circuit in a second direction opposite to said first direction in data retrieving; an address producing circuit producing an intended address based on information transmitted from each of said memory cell rows through said second shift circuit in said data retrieving; a plurality of stages of latch circuits provided corresponding to respective addresses of said plurality of memory cell rows, and each latching a shift signal instructing an operation of shifting the corresponding memory cell row in said first and second shift circuits; and a shift signal producing portion producing said shift signal to be latched by each of said latch circuits based on a faulty address of said faulty memory cell row.