Patent ID: 7304910

Claim:
A semiconductor device that comprises a memory array including memory cells and sense amplifiers amplifying stored data in the memory cells, input/output lines having a hierarchical structure, a sub-amplifier, a main amplifier, and a timing controller, wherein the sub-amplifier includes a variable current source that can generate a first current or a second current so that driving ability of the sub-amplifier is controlled and amplifies a voltage signal read from the memory array to a lower input/output line of the input/output lines; the variable current source generates the first current according to a first read enable signal and generates the second current according to a second read enable signal; the voltage signal of the lower input/output line amplified by the sub-amplifier is read in an upper input/output line of the input/output lines; the main amplifier amplifies a voltage signal read in the upper input/output line; and the timing controller generates the first and second read enable signals.