Patent ID: 7075850

Claim:
A multi-port memory having a common memory interface and a plurality of memory ports through which the memory is accessed, the multi-port memory comprising: a first memory cell array having memory cells arranged in at least one memory segment; a first input/output (I/O) circuit coupled to the first memory cell array and configured to couple data between the first memory cell array and a first one of the plurality of memory ports in response to accessing memory cells of the first memory cell array; a second memory cell array having memory cells arranged in at least one memory segment, the memory segment of the first memory cell array and the memory segment of the second memory cell array having the same number of memory cells; a second I/O circuit coupled to the second memory cell array and configured to couple data between the second memory cell array and a second one of the plurality of memory ports in response to accessing memory cells of the second memory cell array; and a third I/O circuit coupled to the first and second memory cell arrays and configured to couple data between one of the memory segments of the first or second memory cell array and the common memory interface in response to accessing memory cells of the first or second memory cell array through the common memory interface.