Patent ID: 8320193

Claim:
A flash memory system comprising: a first flash memory cell, the first flash memory cell including: a first control gate, the first control gate connected to a first word line; a first floating gate; a first oxide layer separating the first control gate from the first floating gate; a first source region; and a first drain region, the first drain region connected to a first bit line; a second flash memory cell, the second flash memory cell including: a second control gate, the second control gate connected to a second word line, the second word line being the same as the first word line; a second floating gate; a second oxide layer separating the second control gate from the second floating gate; a second source region; and a second drain region, the second drain region connected to a second bit line; a comparator connected to the first bit line and the second bit line and configured to receive a first input signal from the first flash memory cell through the first bit line; receive a second input signal from the second flash memory cell through the second bit line; process information associated with the first input signal and the second input signal; and determine a logic state associated with the first flash memory cell and the second flash memory cell based on at least information related to the first input signal and the second input signal; wherein the first and second flash memory cells are erased prior to programming the flash memory system, and wherein the logic state is stored within the flash memory system by programming only one of the first and second flash memory cells while the not programmed flash memory cell remains erased.