Patent ID: 7586116

Claim:
A semiconductor device comprising: a substrate; an insulating layer adjacent said substrate; a semiconductor layer adjacent a face of said insulating layer opposite said substrate; a superlattice adjacent said semiconductor layer and extending between said source and drain regions to define a channel, said superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon; spaced apart source and drain regions on said semiconductor layer for causing transport of charge carriers through said superlattice in a parallel direction relative to the stacked groups of layers; and a gate overlying said superlattice; said energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween.