Patent ID: 8400439

Claim:
An integrated circuit device comprising: a data line driving circuit that is provided for each of a plurality of data signal supply lines and supplies a multiplexed data signal to a corresponding data signal supply line among the plurality of data signal supply lines; an order offset register that stores a first order offset setting value—a p-th order offset setting value corresponding to order offsets that are offsets generated in a plurality of data signals, depending on an order of driving a first pixel—a p-th pixel, when a plurality of data signals after demultiplexing obtained by demultiplexing the multiplexed data signal with a demultiplexer are supplied to a plurality of pixels in one horizontal scanning period; an order setting circuit that sets an order of driving the first pixel—the p-th pixel by outputting an order instruction signal instructing to select a pixel in an r-th (r is a natural number less than p) place in the order; an order offset addition circuit corresponding to the data line driving circuit, wherein, when the data line driving circuit drives, among the first pixel—the p-th pixel, a q-th (q is a natural number less than p) pixel in the r-th place in the order, the order offset addition circuit processes addition of an order offset correction value based on the r-th order offset setting value among the first order offset setting value—the p-th order offset setting value to the q-th image data among the first image data—the p-th image data; and a multiplex counter that counts the number of clocks of a demultiplexing clock for demultiplexing, a horizontal synchronization counter that counts the number of horizontal synchronization signals, an addition circuit that processes addition of a count value of the multiplex counter and a count value of the horizontal synchronization counter and outputs an added count value, and a decoder that, upon receiving rotation data in which a lower bit sequence of the added count value is inverted to an upper bit sequence and an upper bit sequence of the added count value is inverted to a lower bit sequence, decodes the rotation data, and outputs the pixel selection signal.