Patent ID: 7118965

Claim:
A method of fabricating a nonvolatile memory device comprising: forming a nonvolatile memory structure, including: implanting first ions into an active region of a semiconductor substrate to form a first well and to adjust a threshold voltage of a low voltage n-type MOS transistor and a threshold voltage of a high voltage n-type MOS transistor; implanting second ions into active region of the semiconductor substrate to form a second well and to adjust a threshold voltage of a high voltage p-type MOS transistor and a threshold voltage of a low voltage p-type MOS transistor, thereby forming a conductive region; depositing an ONO layer on the semiconductor substrate; patterning and etching the ONO layer to form an ONO structure; after forming the ONO structure, forming a first gate oxide layer on the semiconductor substrate; removing the first gate oxide layer existing where the low voltage n-type MOS transistor and the low voltage p-type MOS transistor are to be formed; and forming a second gate oxide layer for the low voltage n-type MOS transistor and the low voltage p-type MOS transistor; and after forming the nonvolatile memory structure, forming a logic circuit.