Patent ID: 8188517

Claim:
A three-dimensional nonvolatile memory device, comprising: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction; a plurality of drain select transistors connected respectively to the channel layers of the channel structures; a plurality of drain select lines extending in parallel in the second direction and connected to the drain select transistors arranged in the second direction; and a plurality of bit lines extending in parallel in the first direction and connected to the channel layers of the channel structures, wherein all channel layers included in one channel structure are connected to a same bit line.