Patent ID: 8159266

Claim:
A semiconductor device, comprising: a metal programmable logic circuit; and a plurality of fixed interconnect geometries including metal and via structures; and a plurality of selectable interconnect geometries, each said selectable interconnect geometry capable of coupling a first of said fixed interconnects to a second of said fixed interconnects; and a binary bitstream, each bit in the bitstream assigned to one or more of said selectable interconnect geometries, wherein the binary state of said bit specifies if said assigned one or more selectable Interconnect geometries is included or excluded in the selection; and a computer aided design tool that identifies one or more logic functions and an interconnect pattern to fully program the metal programmable logic circuit to a user specification by identifying the bit states of said binary bitstream; and at least one custom mask comprising a portion of said fixed interconnect geometries and a portion of the bitstream selected geometries of said one or more selectable interconnect geometries, wherein the said at least one custom mask programs the metal programmable logic circuit to the customer specification during fabrication of the semiconductor device.