Patent ID: 8338225

Claim:
A method for forming a memory cell structure, the method comprising: forming a bottom electrode within a substrate, the bottom electrode being electrically conductive; depositing a first layer over the bottom electrode, the first layer having a Pilling-Bedworth ratio of at least one and one-half; depositing a sacrificial layer and a nitride layer over the first layer; etching a channel in the sacrificial layer such that a nitride layer overhang is formed above the sacrificial layer; depositing a conformal layer within the channel such that a void is formed within the conformal layer as a result of the nitride layer overhang; etching through the conformal layer and the void such that a via is formed within the first layer and substantially over the center of the bottom electrode, the via including at least one sidewall; oxidizing at least a portion of the at least one sidewall of the via such that the diameter of the via is reduced by expansion of the first layer; depositing a phase change material above the bottom electrode; and forming a top electrode above the phase change material.