Patent ID: 7386709

Claim:
Apparatus for processing data, said apparatus comprising: an instruction fetching circuit operable to fetch program instructions from a sequence of memory locations; an instruction decoder responsive to program instructions fetched by said instruction fetching circuit to control data processing operations specified by said program instructions; and an execution circuit operable under control of said instruction decoder to execute said data processing operations; a program counter register operable when said apparatus is executing said program instructions from said sequence of memory locations to store an address indicative of a memory location of a program instruction being executed within said program instructions from said sequence of memory locations; and a block counter register operable to store a block count value indicative of a location of a program instruction being executed within a block of two or more program instructions, specified by a location field within said execute block instruction; and wherein said instruction decoder is responsive to an execute block instruction to trigger fetching of a block of two or more program instructions by said instruction fetching circuit and execution of said block of two or more program instructions by said execution circuit, said block of two or more instructions containing a number of program instructions specified by a block length field within said executed block instruction and being stored at a memory location instruction; and wherein when executing said block of two or more program instructions, said program counter register is configured to store an address indicative of a memory location where said execute block instruction is stored and said block counter register is configured to store a block count value indicative of said program instruction location of a program instruction being executed within said block of two or more program instructions corresponding to said execute block instruction, the apparatus further comprising: an exception handling circuit operable upon occurrence of an exception during execution of said block of two or more instructions to store said block count value, and upon completion of handling of said exception, to restart execution of said block of two or more program instructions at a program instruction within said block of two or more instructions indicated by said block count value.