Patent ID: 7151697

Claim:
A non-volatile semiconductor memory comprising: a substrate having a substrate region; electrically insulating elements disposed in the substrate; first wells of a first doping type disposed in the substrate, wherein the first wells are separated from the substrate region and from each other by means of the electrically insulating elements; a plurality of non-volatile memory cells arranged in a plurality of sectors, wherein each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well; at least one word line, the at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors; switching elements, wherein each first well is connected to a respective switching element and wherein the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element; and control signals coupled to and controlling the switching elements of respective ones of the plurality of sectors wherein during an erase cycle a selected first well is biased to a first predetermined potential different from the potential of the wordline and at least one other first well is biased to a second predetermined potential to reduce gate disturb during the erase cycle.