Patent ID: 8427797

Claim:
An integrated circuit chip including a semiconductor die having an interior area bounded by a peripheral area, the semiconductor die comprising: at least one functional domain located in the die interior area; I/O circuitry providing I/O interconnects for the at least one functional domain, the I/O circuitry including a plurality of solder bump pads without including peripheral wire bond pads, at least a portion of the bump pads being interior bump pads distributed over the die interior area; and an ESD network to protect components of the die from electrostatic discharge, the ESD network including a plurality of ESD structures located in the die interior area, each of the ESD structures placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between the interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.