Patent ID: 7105394

Claim:
A method of manufacturing a semiconductor device having an n-channel conductivity type field effect transistor and a p-channel conductivity type field effect transistor, each formed over a semiconductor substrate, comprising steps of: (a) forming first sidewall spacers over a semiconductor region between each of gate electrodes of said n channel conductivity type and p channel conductivity type field effect transistors and an element isolation region of said semiconductor substrate in alignment with each of said gate electrodes; (b) forming, over the surface of said semiconductor region, a metal semiconductor reacted layer in alignment with said first sidewall spacers; (c) forming second sidewall spacers over said metal-semicondutor reacted layer in self-alignment with said first sidewall spacers; (d) forming, over said n-channel conductivity type and p-channel conductivity type field effect transistor, a first insulating film for generating a tensile stress in a channel formation region of said n-channel conductivity type field effect transistor so as to cover gate electrodes of said transistors; (e) selectively removing said first insulating film from the upper surface of said p-channel conductivity type field effect transistor by etching; (f) forming, over said n-channel conductivity type and said p-channel conductivity type field effect transistors, a second insulating film for generating a compressive stress in a channel formation region of said p-channel conductivity type field effect transistor so as to cover the gate electrodes of said transistors; and (g) selectively removing said second insulating film from the upper surface of said n-channel conductivity type field effect transistor, wherein said second sidewall spacers have etching selectivity over said first insulating film.