Patent ID: 7178012

Claim:
A semiconductor device comprising: an instruction memory for storing an instruction program comprising a plurality of instruction codes as data with an address; an instruction fetch block for specifying an address in the instruction memory, performing a fetch process for fetching an instruction program read out from the instruction memory, and outputting the plurality of codes; a decode block for decoding, into a control signal, each of the plurality of instruction codes outputted from the instruction fetch block, and outputting such control signal; and an execution block for executing an instruction according to a control signal outputted from the decode block, and outputting a conditional-branch-taken signal indicating a status of a conditional branch according to a result of execution of such instruction, wherein when the instruction fetch block performs the fetch process, one of an address which is a branch target address for use when a conditional branch is taken and an address for use when such conditional branch is not taken is selected according to a conditional-branch-taken signal outputted from the execution block, and supplied to the instruction memory, wherein the instruction memory comprises an X decoder, a Y decoder and a memory array comprising a plurality of memory cells identified by an output from the X decoder and an output from the Y decoder, the X decoder having an input address specified by upper bits of a fourth address outputted from the instruction fetch block, the Y decoder comprising a normal decoder for decoding lower bits of the fourth address outputted from the instruction fetch block, a branch Y decoder for decoding lower bits of the branch target address having a same bit width as that of lower bits of the fourth address outputted from the instruction fetch block, and a selector for receiving an output from the normal Y decoder and an output from the branch Y decoder, selecting one of the outputs according to the conditional-branch-taken signal outputted from the execution block and outputting selected output, wherein the lower bits of the fourth address specifying each of the memory cells of the memory array is specified by the output from the selector.