Patent ID: 8796099

Claim:
A method of forming a semiconductor structure, the method comprising: forming a transistor structure including a gate on a semiconductor substrate, a channel region in the semiconductor substrate below the gate, and a source/drain region in the semiconductor substrate adjacent to the channel region; depositing an interlevel dielectric layer above the transistor structure; etching the interlevel dielectric layer to form a contact recess, wherein the contact recess exposes a portion of the source/drain region; forming a metal-rich silicide layer on the exposed portion of the source/drain region; forming a metal contact in the contact recess region, wherein the metal-rich silicide layer is encapsulated by the formed metal contact; and converting the metal-rich silicide layer to a silicon-rich silicide layer, wherein the silicon-rich silicide layer applies tensile or compressive stress to the channel region, wherein the silicon-rich silicide layer remains encapsulated by the metal contact after converting the metal-rich silicide layer to a silicon-rich silicide layer.