Patent ID: 8138036

Claim:
A method, comprising: (a) forming a trench in a silicon substrate, said trench open to a top surface of said substrate; (b) forming a silicon dioxide layer on sidewalls of said trench, said silicon dioxide layer not filling said trench; (c) filling remaining space in said trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in said substrate; (e) completely removing said polysilicon from said trench, said silicon dioxide layer remaining on said sidewalls of said trench; (f) re-filling said trench with an electrically conductive core, said electrically conductive core extending above a top surface of said substrate; and after (f), (g) forming a stack of two or more damascene wiring levels from a first wiring level to a last wiring level over said top surface of said substrate, a wire of said first wiring level contacting a top surface of said conductive core.