Patent ID: 7989933

Claim:
A leadframe for a semiconductor package, comprising: a generally planar die pad defining multiple peripheral edge segments; a land connecting bar at least partially circumventing the die pad; a dambar connected at least partially circumventing the land connecting bar; a plurality of land leads connected to the land connecting bar and extending inwardly toward the die pad; a plurality of extension leads connected to the land connecting bar and extending outwardly toward the dambar, each of the extension leads including first and second downsets formed therein in spaced relation to each other so as to define at least first, second and third segments which reside on respective ones of three spaced, generally parallel planes; a plurality of inner leads connected to the dambar and extending inwardly toward the land connecting bar, at least some of the inner leads including a downset formed therein so as to define at least first and second segments which reside on respective ones of a spaced, generally parallel pair of planes; and a plurality of outer leads connected to the dambar and extending outwardly therefrom, each of the outer leads being aligned with and integrally connected to a respective one of the inner leads; the second and third segments of the extension leads extending in generally co-planar relation to respective ones of the first and second segments of the inner leads.