Patent ID: 8310304

Claim:
A digital power amplifier, comprising: an amplifying stage, the amplifying stage configured for applying a first level of attenuation to an RF input signal in response to a desired output power level of the digital power amplifier; a reference loop, the reference loop configured for determining an average power of a sample of the RF input signal, the reference loop further configured for providing a reference value at least partially based upon the average power of the sample of the RF input signal; a feedback loop, the feedback loop configured for applying a second level of attenuation to a sample of an output of the amplifying stage, the second level of attenuation being inversely proportional to the first level of attenuation, the feedback loop further configured for providing a feedback value indicating an average power of the attenuated sample of the output; and an error amplifier, the error amplifier configured for providing a gain control adjustment signal to the amplifying stage, the gain control adjustment signal being determined based upon the reference value and the feedback value; wherein the reference loop further comprises: an RF envelop detector configured for detecting an RF envelope of the sample of the RF input signal; an RF envelope filter configured for reducing variations of the RF envelope and determining the average power of the sample of the RF input signal; and a multiplying digital to analogue converter (MDAC) gain adjustment unit configured for calculating the reference value based upon the average power of the sample of the RF input signal and a gain control signal, the MDAC gain adjustment unit further configured for providing the reference value to the error amplifier.