Patent ID: 7906989

Claim:
A multi-interface integrated circuit (IC), comprising: a plurality of transistors, wherein at least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one other of the plurality of transistors is in communication with the first terminal and a second terminal and either the first or second lead of the multi-interface IC; a level detection block in communication with at least one of the plurality of transistors and the first and second leads, wherein the plurality of transistors includes at least one N metal oxide semiconductor (MOS) transistor and a plurality of PMOS transistors; and a detection enable block wherein the at least one NMOS transistor is connected to the detection enable block, first terminal, and the plurality of PMOS transistors, and wherein a first PMOS transistor is in communication with the second terminal, a second PMOS transistor is in communication with the second terminal, second lead and the level detection block, and a third PMOS transistor is in communication with the second terminal, first lead and the level detection block.