Patent ID: 7205819

Claim:
A system for voltage level shifting comprising: an input buffer with first supply voltage rails and an input voltage; an output buffer with second supply voltage rails; a current mirror with a high-side supply of the second supply voltage rails, wherein current mirror comprises a first p-channel MOSFET diode-connected and a second p-channel MOSFET, and the sources of each of the first and second p-channel MOSFETS are communicatively coupled with the high-side supply of the second supply voltage rails; a differential set of transistors with a low side supply of the first supply voltage rails; and a latching circuit for removing bias signal, wherein the latching circuit for a removing bias signal comprises: a bias setting buffer inverter with the second supply voltage rails; a third D-channel MOSFET with the source communicatively coupled with the high side supply of the second supply voltage rails, the drain communicatively coupled with the input of the bias setting buffer inverter, and the gate communicatively coupled with the output of the bias setting buffer inverter; and a third n-channel MOSFET with the drain communicatively coupled with the drain of the first p-channel MOSFET, the source communicatively coupled with the drain of the first n-channel MOSFET, and the gate communicatively coupled with the output of the bias setting buffer inverter; wherein a bias signal of the current mirror.