Patent ID: 8310288

Claim:
A PLL circuit comprising: a phase comparator configured to compare a phase of a reference clock signal with a phase of a feedback clock signal based on an output clock signal and outputting a control signal corresponding to a difference between the phases; a charge pump circuit configured to output an output current according to the control signal; a loop filter configured to change accumulated charges by the output current of the charge pump circuit; and a voltage controlled oscillator configured to output the output clock signal at an oscillation frequency corresponding to an input voltage based on the amount of charges accumulated in the loop filter, wherein the charge pump circuit is configured to output a first output current according to the phase difference between the reference clock signal and the feedback clock signal in a case where the phase difference is larger than a threshold value, and the charge pump circuit is configured to output a second output current larger than the first output current according to the phase difference between the reference clock signal and the feedback clock signal in the case where the phase difference is smaller than the threshold value.