Patent ID: 8897052

Claim:
A memory device comprising: a substrate; a first metal layer provided over the substrate; a second metal layer provided over the first metal layer; a third metal layer provided over the second metal layer, wherein the first metal layer, the second metal layer and the third metal layer are disposed in a substantially parallel spaced relation; first and second arrays of memory cells separated by and in communication with a throat region, said first and second arrays of memory cells being the only memory cells adjacent to and in communication with said throat region, said first and second arrays comprising a plurality of memory blocks, said throat region being positioned between the first and second arrays and consisting essentially of a datapath, said datapath comprising a plurality of IO circuits with each IO circuit being connected to and associated with a respective memory block from said first and second arrays, wherein a first portion of said plurality of IO circuits is routed through the second metal layer and a second different portion of said plurality of IO circuits is routed through the third metal layer, wherein no IO circuits are routed through the first metal layer; a first row logic circuit respectively connected to and associated with said first array and being on a first side of said first array opposite a second side of said first array, the second side of the first array adjoining said throat region, wherein said first row logic circuit provides signals to said first array in a unidirectional manner, the first array comprising a separate, independently addressable circuit comprising a set of row lines and a set of digit lines; and a second row logic circuit respectively connected to and associated with said second array and being on a first side of said second array opposite a second side of said second array, the second side of the second array adjoining said throat region, wherein said arrays are connected to a first power bus and a first ground bus, and said throat region is connected to a second power bus and a second ground bus, which are separate than the first power and ground busses, wherein said IO circuits are associated with respective IO lines, and wherein at least some of said IO lines are routed across the first and second arrays, the at least some of said IO lines running parallel to row-driver lines in the second metal layer and being routed to the third metal layer through the second metal layer over gap cells in the first and second arrays.