Patent ID: 8176354

Claim:
A selectively synchronous wave pipeline segment externally clocked by a global clock, said selectively synchronous wave pipeline segment comprising: a plurality of pipeline stages including an input stage, an output stage and one or more internal stages, said input stage and said output stage being normally opaque and said one or more internal stages being normally transparent; a plurality of local clock buffers, each local clock buffer selectively providing a local clock to one said corresponding pipeline stage, said input stage and said output stage being selectively clocked transparent and said one or more internal stages being selectively clocked opaque responsive to a corresponding said local clock; and a local clock control circuit providing internal stage clock selection control to said one or more internal stages, said internal clock selection control determining whether each internal pipeline stage is gated opaque by said corresponding local clock, multiple pipeline data items passing as data waves between said input and said output stage selectively unclocked, wherein for any sequential data items entering the pipeline and traversing the pipeline in data waves, selected internal registers are gated opaque just prior to race condition locations.