Patent ID: 8080834

Claim:
A semiconductor integrated circuit, comprising: a substrate; an oxide layer formed on an upper surface of the substrate; a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members; and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix, wherein the oxide layer includes a field oxide layer situated under the second polysilicon members and a capacitor-element oxide layer situated under the first polysilicon member, and a thickness of the capacitor-element oxide layer is smaller than a thickness of the field oxide layer.