Patent ID: 7570095

Claim:
A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter comprising: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal; wherein the first signal and the fifth signal are interpolated to generate the first internal clock signal, wherein the third signal and the fourth signal are interpolated to generate the second internal clock signal, and wherein a delay of the first buffer is the same as a delay of the second interpolating signal generator.