Patent ID: 7489204

Claim:
An integrated circuit testing structure comprising: a tester comprising: a multiplexer in a metal layer of a semiconductor chip; a ring oscillator in said metal layer electrically connected to said multiplexer; a first wire in said metal layer electrically connected to said multiplexer; and a second wire in said metal layer electrically connected to said multiplexer, wherein said first wire is longer than said second wire, and wherein said multiplexer is adapted to selectively connect said ring oscillator to one of said first wire and said second wire; a monitor electrically connected to said ring oscillator and adapted to measure a first ring frequency of said ring oscillator, when said ring oscillator is connected to said first wire, and a second ring frequency of said ring oscillator, when said ring oscillator is connected to said second wire; and a processor in communication with said monitor and adapted to determine a resistance-capacitance delay of said metal layer based upon a difference between said first ring frequency and said second ring frequency.