Patent ID: 6894556

Claim:
A current source circuit comprising: a first PMOS transistor having a source coupled to a first power source, a gate receiving a voltage from a voltage circuit, and a drain coupled to a node; and a compensation circuit comprising; more than one compensation PMOS transistors, each compensation PMOS transistor having a gate, a source coupled to the first power source, and a drain coupled to the node; and more than one subtracter, each subtracter coupled to the gate of each compensation PMOS transistor, each subtracter configured to supply voltage expressed by arithmetic series a k to the gate of each compensation PMOS transistor, where the a k is the arithmetic series equal to: V g1−kV d1 (k=1, 2, . . . , n), V d1 is the drain-source voltage of the first transistor, V g1 is the gate-source voltage of the first transistor, and n is the number of the PMOS transistors of the compensation circuit.