Patent ID: 7453909

Claim:
An arrangement for interconnection of two or more printed circuit boards communicating with each other over a time division multiplex data bus, each circuit board including a number of loads transferring data in both a receive and transmit direction, comprising: a local time division multiplex data bus in each printed circuit board to which the associated number of loads are connected, an intermediate Central Processing Unit controlled logic in each direction connecting each local time division multiplex data bus to a global time division multiplex data bus, which is a back plane time division multiplex data bus, said arrangement being implemented in a circuit switched node, and said control logic including: a First-In-First-Out buffer through which synchronous data from the respective local time division multiplex data bus or the global time division multiplex data bus is being written in and read out to the respective local time division multiplex data bus or the global time division multiplex data bus introducing a phase difference, providing a total delay for any data traveling from the respective local time division multiplex data bus to the global time division multiplex data bus and back to the respective local time division multiplex data bus, being of a controllable dimension equal to an integer number of data frames; and a first and a second time slot counter, the first counter addressing a first data location in the First-In-First-Out buffer into which, in case of receive direction, time slot data from a local time division multiplex data bus is to be written, or out of which, in case of transmit direction, time slot data to a local time division multiplex bus is to be read, the second counter addressing a second data location in the First-In-First-Out buffer into which, in case of transmit direction, time slot data from the global time division multiplex bus is to be written, or out of which, in case of receive direction, time slot data to the global time division multiplex bus is to be read, wherein the phase difference between the first and the second time slot counter represents a preferred part of said total delay caused by the logic of the respective direction.