Patent ID: 8084324

Claim:
A fabrication method for a nonvolatile semiconductor memory, which includes a cell array region, a high-voltage circuit region, and a low-voltage circuit region, the fabrication method comprising: forming a tunneling insulating film on a semiconductor substrate, a floating gate electrode layer on the tunneling insulating film, and a first stopper film on the floating gate electrode layer in the cell array region, the high-voltage circuit region, and the low-voltage circuit region; removing the first stopper film and the floating gate electrode layer only in the high voltage region; forming a high voltage gate insulating film on the semiconductor substrate, a high voltage gate electrode layer on the high voltage gate insulating film, and a second stopper film on the high voltage gate electrode layer in the high voltage region; removing portions of the second stopper film, the high voltage gate electrode layer, the first stopper film, and the floating gate electrode layer, in prospective regions, in which element isolating regions are to be formed, in the cell array region, the high-voltage circuit region, and the low-voltage circuit region; removing portions of the high voltage gate insulating film, and the tunneling insulating film in the prospective regions in which element isolating regions are to be formed, in the cell array region, the high-voltage circuit region, and the low-voltage circuit region; etching the semiconductor substrate until a depth at which the element isolating regions are to be formed and forming etching grooves in the semiconductor substrate in the cell array region, the high-voltage circuit region, and the low-voltage circuit region; filling the etching grooves with a first insulating film and forming element isolating regions in the cell array region, the high-voltage circuit region, and the low-voltage circuit region; removing the first stopper film and the second stopper film in the cell array region, the high-voltage circuit region, and the low-voltage circuit region; depositing a second insulating film on the device surface including the cell array region, the high voltage circuit region, and the low voltage circuit region; depositing a control gate electrode layer on the second insulating film including the cell array region, the high voltage circuit region, and the low voltage circuit region; and etching portions of the control gate electrode layer and the second insulating film in the cell array region, the high voltage circuit region, and the low voltage circuit region to expose the high voltage gate electrode layer.