Patent ID: 7911859

Claim:
A delay line, comprising: at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor comprising: a PMOS transistor, having a source terminal coupled to a first voltage level; and a plurality of NMOS transistors, coupled between a drain terminal of the PMOS transistor and a second voltage level, wherein the first voltage level is higher than the second voltage level, one of the NMOS transistors receives the input signal, the Pseudo NMOS transistor generates the output signal at the drain terminal of the PMOS transistor according to the input signal received by the one of the NMOS transistors, and the output signal of the Pseudo NMOS transistor is transmitted to an NMOS transistor included in a subsequent delay cell.