Patent ID: 7471546

Claim:
An SRAM memory array comprising: a plurality of memory cells, each of said plurality of memory cells further comprising: a device, each of said plurality of memory cells having six of said device; a first storage node; a second storage node; a first local bit line; a second local bit line; a first global bit line; and a second global bit line; said first storage node and said second storage node store the true and complement of the data and are constructed with four of said device forming a cross coupled flip-flop cell, said first storage node is connected through a first access pass gate to said first bit line, said second storage node is connected through a second access pass gate to said second local bit line, each of said first bit line and said second bit line are connected to eight to thirty-two other said plurality of memory cells, said first bit line is connected to a first separate read head nFET gate and said second bit line is connected to a second separate read head nFET gate effectuating discharging to ground one of two previously precharged said first global bit line or said second global bit line so as to pass the inverse of the signal on said first local bit line to said first global bit line and the inverse of the signal on said second local bit line to said second global bit line said SRAM memory array further comprising: two of said device arranged as a first pFET device and a second pFET device, said first global bit line and said second global bit line serve as sense lines by way of cross coupled said first pFET device and said second pFET device, wherein said first global bit line is connected to drain on said first pFET device and to the gate on said second pFET device, said second global bit line is connected to the drain of said second pFET device and the gate of said first pFET device, both of said first pFET device and said second pFET device having source connected to a supply voltage, only one of said first global bit line or said second global bit line is set ‘LOW’ on a ‘READ’ and the same polarity sensed on said first local bit line and said second local bit line appears on said second global bit line and said first global bit line respectively, and is sensed by global sense amplifiers.