Patent ID: 7120891

Claim:
A master slice semiconductor integrated circuit, comprising: at least two wiring layers for wiring; and a plurality of clock buffers connected by clock wirings in a form of a clock tree having at least two cascaded stages to distribute clock signals to a plurality of sequential circuits; wherein each of said clock wirings among said plurality of clock buffers comprises a wiring layer switching portion which switches a clock wiring from a lower wiring layer of said at least two wiring layers to an upper wiring layer of said at least two wiring layers and then switches said clock wiring from said upper wiring layer to said lower wiring layer; wherein said wiring layer switching portion comprises: an output wiring which is formed of said lower wiring layer and connects one end thereof to a clock output of a clock buffer of a former stage; an output side via wiring which connects one end thereof to the other end of said output wiring and connects the other end thereof to said upper wiring layer; an input wiring which is formed of said lower wiring layer and connects one end thereof to a clock input of a clock buffer of a later stage; and an input side via wiring which connects one end thereof to the other end of said input wiring and connects the other end thereof to said upper wiring layer; and wherein said upper wiring layer is a wiring layer for customized wirings, and said lower wiring layer is a wiring layer for fixed wirings.