Patent ID: 7317652

Claim:
A semiconductor memory comprising: a read control circuit which, when activated, outputs a control signal for reading out data; and an activation control circuit for activating or deactivating said read control circuit in accordance with external input, wherein said activation control circuit has a pad connected to said activation control circuit, and the external input is performed by application of a voltage to said pad, wherein said activation control circuit further comprises: a power-on reset circuit for outputting a power-on reset signal when a voltage reaches a predetermined level after the power source is turned on; and an activation determining circuit which, if the voltage input to said pad is at a first level, activates said read control circuit to output the control signal when the power-on reset signal is output, and, if the voltage input to said pad is at a second level, deactivates said read control circuit so as to not output the control signal even when the power-on reset signal is output.