Patent ID: 8631375

Claim:
A computer-implemented method for creating a multi-level integrated circuit layout, performed using at least one computing device, the method comprising: providing at least two layers of the multi-level integrated circuit layout; selecting a via for connecting the at least two layers using the at least one computing device, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias; constructing the via library prior to the selecting of the via, the constructing including: obtaining manufacturing yield data about each of the plurality of via types; prioritizing the plurality of via types using the manufacturing yield data, wherein the prioritizing further includes prioritizing according to an amount of white space used by each of the plurality of via types; and storing the plurality of vias in the library according to the prioritization.