Patent ID: 8653576

Claim:
A method of forming a SONOS gate structure, comprising: forming a gate pattern with sidewalls on a substrate, wherein said gate pattern comprises a gate dielectric layer patterned on said substrate and a gate electrode patterned on said gate dielectric layer; forming a first oxide layer on said gate pattern and said substrate; forming a first dielectric layer on said first oxide layer, wherein said first dielectric layer is formed of silicon nitride; etching back said first dielectric layer to expose said first oxide layer, leaving first dielectric spacers on said first oxide layer adjacent to said sidewalls of said gate pattern respectively; etching back said first oxide layer and said first dielectric spacers to expose said substrate and the top of said gate electrode, leaving oxide spacers along said sidewalls of said gate pattern respectively, and leaving said first dielectric spacers on said oxide spacers respectively, wherein the oxide spacers have a thickness of 70˜200 Angstroms; forming a second oxide layer on the exposed portions of said substrate, said gate electrode and said oxide spacers, wherein the thickness of the oxide spacers is thicker than that of the second oxide layer and the second oxide layer is selectively formed on the oxide spacers; forming a second dielectric layer on said first dielectric spacers and said second oxide layer; and etching back said second dielectric layer to expose said second oxide layer, leaving second dielectric spacers adjacent to said sidewalls of said gate pattern respectively.