Patent ID: 7567893

Claim:
A method of electronically simulating a digital circuit operating with one or more clock signals, a clock signal being a signal having one or more attributes that provide for determining the time of the next clock signal driven event, the method comprising: electronically forming a hardware model representing the circuit, in a simulation; scheduling one or more time-scheduled events according to the model in a time-scheduled event data structure, a time-scheduled event being an event whose occurrence time in a simulation time frame is defined by reference to a simulation time; scheduling one or more clock-scheduled events according to the model in a clock-scheduled event data structure, a clock-scheduled event being an event whose occurrence time is defined relative to one or more attributes of at least one clock signal in the circuit; electronically predicting the occurrence time of the clock-scheduled events; and at any particular simulation time, processing the time-scheduled events for the particular simulation time and clock-scheduled events predicted to occur at the particular simulation time; wherein clocked-scheduled events are distinguishable from time-scheduled events, and wherein each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.