Patent ID: 7793238

Claim:
A processor based method for improving an integrated circuit layout, the method comprising: using one or more processors programmed to perform operations including: traversing a tree-type hierarchical layout representation of the circuit design, wherein the hierarchical representation includes a plurality of blocks in block-sub-block relationships, and each block has a block type; at each block visited during the traversing, determining whether there exists an improvement opportunity for each cell associated with the block; and before continuing the traversing to another block in the tree-type hierarchical layout representation, performing further operations including: in response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, determining whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation; in response to the modification satisfying the one or more rules for every block of the block type of the first block, storing the modification to the cell, wherein the modification to the cell is applied to every block of the block type of the first block; and in response to the modification violating any of the one or more rules for any block of the block type of the first block in the hierarchical representation, discarding the modification to the cell.