Patent ID: 7133999

Claim:
A single instruction, multiple data computer system, comprising: a central control unit having an address bus, the central control unit applying global column information corresponding to a respective column address to the address bus; at least one memory device having a column selection port and an array of memory locations arranged in rows and columns; a plurality of processing elements each having a data bus coupled to the at least one memory device, each of the processing elements being coupled to memory cells in a respective group of columns of the array; a plurality of local column registers each having an input port coupled to the data bus of a respective processing element to receive and store local column information corresponding to a local column address, each of the local column registers further having an output port; and a plurality of selection devices each of which is coupled to the address bus of the central control unit and to the output port of a respective local column register, each of the selection devices being operable to couple the global column information to the column selection port of the at least one memory device in a global addressing mode, and to couple the local column information to the column selection port of the at least one memory device in a local addressing mode, the local column information coupled to the column selection port being generated without the use of any of the global column information.