Patent ID: 7227232

Claim:
A NAND Mask ROM, comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in rows and columns, wherein the memory cells include a plurality of first memory cells that have a first channel conductivity and are depletion MOS transistors, and a plurality of second memory cells that have a second channel conductivity and are enhanced MOS transistors; the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line; a constant number of continuous memory cells in the same column are grouped as a memory string, wherein a non-terminal memory cell shares a source and a drain with two adjacent memory cells in the memory string; and one terminal memory cell in the memory string is coupled to a bit line, and the other terminal memory cell is coupled to ground, wherein gate electrodes of the memory cells in the same row are coupled to a word line with contacts.