Patent ID: 8289775

Claim:
A nonvolatile memory device comprising: an array of nonvolatile memory cells arranged in rows and columns, such that the nonvolatile memory cells located on each column are connected to communicate with a local bit line associated with each column, the nonvolatile memory cells on each row are connected to communicate with a word line, and the nonvolatile memory cells on two adjacent rows are commonly connected to a source line, wherein the array of nonvolatile memory cells is partitioned into sectors, where each sector is placed in a first isolation well and each sector of the array of the nonvolatile memory cells is divided into blocks and each block is divided into pages, and each page includes one row of the nonvolatile memory cells; a plurality of peripheral circuits connected to the word lines, bit lines, and sources lines to provide biasing voltages for reading, programming, erasing, and verifying selected nonvolatile memory cells, such that the biasing voltages do not exceed a drain-to-source breakdown voltage of the peripheral circuits for eliminating high voltage transistors with larger dimensions and wherein the biasing voltages include a word line read inhibit voltage level that is applied to the word lines and a source line read inhibit voltage during a read operation and a word line program inhibit voltage level that is applied to unselected word lines and a source line program inhibit voltage level that applied to unselected source lines during a program operation to minimize a sub-threshold leakage current through each of the unselected nonvolatile memory cells.