Patent ID: 7853775

Claim:
A mixed mode parallel processor system comprising: N number of processing elements, the N number of processing elements performing parallel operations in SIMD operation; the N number of the processing elements being grouped into M (=N÷S) sets (where S and M are natural numbers not smaller than 2) of processing units, in MIMD operation, each of the M sets of processing units including S number of the processing elements, each of S number of the processing elements in each of the M sets of processing units including memory resources and general-purpose register resources, the M sets of processing units performing parallel operations with one another, and the S number of processing elements performing parallel operations with one another, wherein in MIMD operation, part of the memory resources of each of the M sets of processing units operate as an instruction cache memory; part of the general-purpose register resources in each of the M sets of processing units operate as a tag storage area of an instruction cache and each of the M sets of processing units includes a control circuit performing, for the S number of the processing elements in each of the M sets of processing units, instruction cache control and instruction sequence control.