Patent ID: 6845346

Claim:
An iterative method of estimating parasitic effects for an interconnect design in an integrated circuit, comprising: with reference to an imaginary grid system overlaying an area of the integrated circuit, estimating a geometry graph for the interconnect, wherein: for a portion of interconnect that is completely unrouted, the geometry graph is estimated according to a Steiner estimation, for a portion of the interconnect that is defined solely by identifiers of grid cells through which the interconnect extends, the geometry graph is drawn through centers of the respective grid cells, for a portion of the interconnect that is defined by identifiers of grids cells through which the interconnect is to extend and by identifiers of crosspoints between the cells, the geometry graph is drawn through centers of the respective grid cell and through the crosspoints, and for a portion of the interconnect that is completely routed, the geometry graph is taken to be the routed interconnect, and modeling parasitic effect upon the geometry graph.