Patent ID: 6977851

Claim:
A semiconductor memory device, comprising: a memory cell block having a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, wherein one of the rows is selected by a row address signal, and wherein one of the columns is selected by a column address signal; a redundant memory cell array having a plurality of redundant memory cells arranged in a plurality of redundant rows and in a plurality of redundant columns; a first fuse block having a plurality of first fuses, the first fuses corresponding to an address of the row address signal, wherein the first fuse block stores an address of a defective row of the memory cell block; a second fuse block having a plurality of second fuses, the second fuses corresponding to an address of the column address signal, wherein the second fuse block stores an address of a defective column of the memory cell block; and an address matching detector which is connected with both the first fuses and the second fuses, wherein the address matching detector checks consistency of the address of the row address signal with the address of the defective row stored in the first fuse block.