Patent ID: 7023062

Claim:
A semiconductor integrated circuit device, comprising: a first MISFET having a first gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate and a first gate electrode formed over said first gate insulating film; and a second MISFET having a second gate insulating film formed over a second element forming region of said main surface of said semiconductor substrate and a second gate electrode formed over said second gate insulating film, said second gate insulating film being thinner than said first gate insulating film, wherein said first gate insulating film includes a thermally oxidized film and a deposited film formed over said thermally oxidized film and having a thickness greater than that of said thermally oxidized film, wherein said second gate insulating film includes a thermally oxidized film, wherein a thickness of said thermally oxidized film of said first gate insulating film is thinner than that of said thermally oxidized film of said second gate insulating film, wherein said first element forming region and said second element forming region are individually isolated by an element isolation region, wherein said element isolation region is formed by forming grooves in said substrate, depositing an insulating film over said grooves by a vapor deposition method, and polishing said insulating film so as to fill said insulating film in said grooves, and wherein said deposited film extends over said element isolation region such that an edge portion of said first gate electrode is formed over said deposited film at a portion of said deposited film positioned over said element isolation region.