Patent ID: 7655534

Claim:
A method of forming a fin transistor in a semiconductor device comprising the steps of: forming a hard mask layer on a silicon substrate having an active region and a field region, wherein the hard mask layer exposes the field region; forming a trench by etching the exposed field region of the substrate; forming a liner nitride layer on surfaces of the trench; filling the trench having the liner nitride formed on surfaces thereof with an SOG layer, such that the SOG layer contacts the liner nitride layer formed on the surfaces of the trench; exposing the active region of the substrate by removing the hard mask layer; forming an epi-silicon layer on the exposed active region of the substrate; partially etching the SOG layer so that only a lower portion of the trench is filled with the SOG layer; depositing an HDP oxide layer on the etched SOG layer inside the trench having the liner nitride formed on surfaces thereof, thereby forming a field oxide layer comprised of the SOG layer and the HDP oxide layer; etching the HDP oxide layer of the field oxide layer to expose both side surfaces of the epi-silicon layer, wherein the etching the HDP oxide layer is implemented so as to not expose the SOG layer; and forming a gate on the epi-silicon layer of which both side surfaces are exposed and the field oxide.