Patent ID: 8134225

Claim:
An electronic package, comprising: a plate of material having a thickness between one surface and an opposing surface; a chip attach region and conductive lead regions around said chip attach region for connecting a chip to said conductive lead regions on said one surface of said plate of material; an array of conductive protrusions extending from said opposing surface of said plate of material, said protrusions having a rounded profile beginning at said opposing surface and extending from the plane of said opposing surface beyond said thickness of said plate of material and ending with a rounded bottom surface to provide increased surface area for solder contact and solder joint stand-off height beneath said conductive lead regions; a chip attached to said chip attach region on said one surface of said plate of material with conductive connections extending from said chip to said conductive lead regions on said one surface of said plate of material; and encapsulant material encapsulating said chip and plate of material including said conductive lead regions on said one surface of said plate of material leaving said array of conductive protrusions extending from the plane of said opposing surface therefrom free of encapsulation.