Patent ID: 7633764

Claim:
A memory system comprising: a printed circuit board, said printed circuit board comprising a first layer and a second layer; a memory controller comprising a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer; a memory comprising a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer; wherein the first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller; wherein the second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller; wherein first plurality of pins of the memory are disposed along a first edge of the memory and wherein the second plurality of pins of the memory are disposed along a second edge of the memory, and wherein the first edge of the memory is substantially opposite from the second edge of the memory; wherein the first plurality of pins of the memory controller and the second plurality of pins of the memory controller are disposed along a particular edge of the memory controller; and wherein the first plurality of pins of the memory controller are closer to the particular edge than the second plurality of pins of the memory controller, and wherein the first plurality of pins of the memory are closer to the memory controller than the second plurality of pins of the memory.