Patent ID: 7838908

Claim:
A semiconductor device, comprising: a PFET region including: a SiGe layer disposed on a substrate portion doped for the PFET, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer; and a third metallic layer disposed on the second intermediate layer; an NFET region including: the high-k dielectric layer, the high-k dielectric layer being disposed on a substrate portion doped for the NFET, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer.