Patent ID: 7492852

Claim:
A frequency divider, comprising: two pairs of flip-flops respectively triggered by an input clock and an inverted input clock, each said pair having one or a plurality of connected flip-flops; a frequency-dividing selector for selecting one output of the two pairs of flip-flops as frequency-divided output signal; two latches respectively triggered by the input clock and the inverted input clock; a modulus selector for selecting one output of the two latches; a modulus logic circuit for determining being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal, N being an integer; a frequency-dividing logic circuit for receiving output of the modulus logic circuit and an inverted frequency-divided output signal, said frequency-dividing logic circuit swallowing half the input clock per output cycle of the frequency-divided output signal in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock, and an odd/even selector for selecting either the input clock or the inverted input clock to control the frequency-dividing selector.