Patent ID: 8136069

Claim:
An apparatus for calculating an approximate electrical performance value for a target wire shape, having a left neighbor and a right neighbor shape in a chip, when using a Design Automated Application (DA application) that is limited to determining one of two possible distances to a neighbor wire shape of the target wire shape at any one time, comprising: a computer connected to a memory and to a database; and a DA application and a Bias Calculation (BC) program in the memory; wherein the BC program contains a plurality of instructions to cause a processor of the computer to interact with the DA application and to: pass a scanline over the target wire shape to generate data; determine from the data, a first separation distance from the left neighbor; responsive to determining the first separation distance, biasing a width of the target wire shape symmetrically using the first separation distance to determine a first bias width; calculate, using the first bias width, a first electrical performance value for the target wire shape; determine, from the data, a second separation distance from the right neighbor; responsive to determining the second separation distance, bias the width of the target wire shape symmetrically using the second separation distance to determine a second bias width; calculate, using the second bias width, a second electrical performance value for the target wire shape; calculate the approximate electrical performance value by averaging the first value and the second value to obtain the approximate electrical performance value; and using the approximate electrical performance value to validate a design specification of the chip.