Patent ID: 8059461

Claim:
A flash memory device, comprising: a first block switch configured to select a first memory block to drive of a plurality of memory blocks and apply a driving voltage to the first memory block, the first block switch including a first transistor for selecting a first common source line and a second transistor for selecting a second common source line thereby controlling the first common source line and the second common source line separately; a second block switch configured to select a second memory block to drive of the plurality of memory blocks and apply a driving voltage to the second memory block, the second block switch including a third transistor for selecting a third common source line and a fourth transistor for selecting a fourth common source line thereby controlling the third common source line and the fourth common source line separately; first, second, third, and fourth cell strings, wherein each of the first to fourth cell strings comprises a drain select transistor, a plurality of cell transistors, and a source select transistor connected in series; a first bit line coupled to the first and third cell strings; a second bit line coupled to the second and fourth cell strings; the first and second common source lines switched by the first block switch, the first common source line being coupled to a source of the source select transistor of the first cell string, the second common source line being coupled to a source of the source select transistor of the second cell string; the third and fourth common source lines switched by the second block switch, the third common source line being coupled to a source of the source select transistor of the fourth cell string, the fourth common source line being coupled to a source of the source select transistor of the third cell string, wherein the first and third common source lines are separated from the second and fourth common source lines by a predetermined interval respectively; drain contacts coupling the respective bit lines to the respective cell strings; and source contacts coupling the respective common source lines to the respective cell strings, wherein the drain contacts and the source contacts are alternately disposed.