Patent ID: 7816155

Claim:
A method for low-stress mounting of a planar semiconductor device, comprising: providing a heat sink having a flat surface and a submount having two opposing first and second flat surfaces, wherein two of three said surfaces have solder films adhered thereto; cold contacting the flat surface of the heat sink to the first flat surface of the submount, and cold contacting the second flat surface of the submount to a flat surface of the planar semiconductor device, so as to form a stack, wherein the solder films are disposed on both sides of the submount; melting the solder films on both sides of the submount; and allowing the solder films to cool and solidify; wherein the planar semiconductor device, the submount, and the heat sink have first, second, and third coefficients of thermal expansion CTE1, CTE2, and CTE3, respectively, wherein said coefficients of thermal expansion are measured in a direction parallel to said flat surfaces, and wherein the value of CTE1 is in between the values of CTE2 and CTE3.