Patent ID: 6884147

Claim:
A method for determining critical polish time t c using a polish pad during semiconductor manufacture of a structure having one or more mesas and one or more valleys, comprising the steps of: obtaining the value of mask-scale or reticle mask-scale M; determining a pad compression spring constant k of the polish pad; measuring on a patterned structure high feature and low feature thicknesses at one or more identifiable locations, the first such measurement (before any polish) determining the values of y m0 (high features) and y v0 (low features); determining the polish recipe value for downforce F dn pushing the structure against the polish pad; determining the planar structure polish rate R p ; and computing a critical polish time prior to encountering one of the valleys according to: t c = F d ⁢ ⁢ n - M ⁢ ⁢ k ⁢ ⁢ A w ⁡ ( y m ⁢ ⁢ o - y v ⁢ ⁢ o ) k ⁢ ⁢ A w ⁢ R p . [ M1 ]