Patent ID: 8575962

Claim:
An integrated circuit comprising: logic circuitry having a plurality of signal paths, wherein a signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths, wherein the signal path includes a plurality of components, and wherein the plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths, and wherein the signal path includes an integral flip-flop and level shifter that includes a data input; a data output; a first inverter coupled to the data input and configured to receive an input data signal at a low voltage and to output the input data signal and a logical complement of the input data signal; a plurality of latches coupled to the first inverter, wherein the plurality of latches is configured to receive the input data signal and the logical complement of the input data signal, and to perform level shifting and latching operations to shift the low voltage input data signal to the higher power supply voltage, resulting in a high voltage data signal; and a second inverter coupled between the plurality of latches and the data output, wherein the second inverter is configured to invert the high voltage data signal produced by the plurality of latches.