Patent ID: 8653592

Claim:
A non-volatile memory, comprising: a substrate; a plurality of stacking units separately disposed on the substrate; a recess formed between every two stacking units; a source region and a drain region buried in the substrate at two sides of the each stacking unit; a stop layer disposed on a lateral surface and an upper surface of the each of the plurality of stacking units and disposed on a bottom surface of the recess; a dielectric material disposed on the stop layer on the bottom surface of the recess and filled with a rest of the recess, wherein the plurality of stacking units are separated from the dielectric material by the stop layer on the lateral surface of the plurality of stacking units, and the substrate is separated from the dielectric material by the stop layer on the bottom surface of the recess, each of the plurality of stacking units has a first height, the stop layer on the lateral surface of the plurality of stacking units has a second height, the stop layer on the bottom surface of the recess and the dielectric material on the stop layer on the bottom surface of the recess has a third surface, the first height is higher than the second height and the first height is higher than the third height, the stop layer on the lateral surface of the plurality of stacking units and on the bottom surface of the recess is for isolation of two neighboring stacking units.