Patent ID: 6940353

Claim:
An amplifier circuit comprising: a first input terminal; a first output terminal; a first complementary metal-oxide-semiconductor (CMOS) inverter coupled between the first input terminal and the first output terminal; and a first bias circuit for applying linear biasing to an input of the first CMOS inverter, the first bias circuit being coupled between an output of the first CMOS inverter and the input of the first CMOS inverter, wherein the first CMOS inverter comprises: a p-type metal-oxide-semiconductor (PMOS) transistor; and an n-type metal-oxide-semiconductor (NMOS) transistor, wherein the PMOS transistor and the NMOS transistor are serially connected between an upper supply voltage and a lower supply voltage, wherein a gate of the PMOS transistor and a gate of the NMOS transistor are connected to the input of the first CMOS inverter, wherein a drain of the PMOS transistor and a drain of the NMOS transistor are connected to the output of the first CMOS inverter, and wherein the first bias circuit comprises an operational amplifier, wherein a non-inverting input of the op-amp is coupled to the output of the first CMOS inverter, wherein an output of the op-amp is coupled to the input of the first CMOS inverter, and wherein an inverting input of the op-amp is coupled to receive a reference voltage, the reference voltage being between the first supply voltage and the second supply voltage, the first supply voltage being greater than the second supply voltage.