Patent ID: 7224025

Claim:
A metal oxide semiconductor (MOS) device having a reduced drift region size according to a constrained electric field comprising: a plurality of wells, including a well of a first type and a well of a second type opposite to the first type; a gate to control the MOS device; a drain coupled to the gate formed in the well of the first type; a source to form a current path with the drain; a first field oxide disposed between the gate and the drain, wherein the gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type; and a second field oxide disposed between the drain and a base guard ring coupled to the well of the second type, wherein a dummy polysilicon layer is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer on a second portion of the well of the second type.