Patent ID: 7858520

Claim:
A method for manufacturing a semiconductor package, comprising the steps of: forming a semiconductor package module comprising: forming a plurality of circuit patterns on an upper surface of an insulation substrate; placing at least two semiconductor chips over the circuit patterns, wherein each semiconductor chip is electrically connected to each of the circuit patterns, and filling an insulation member at least in any space between any combination of the semiconductor chips and the circuit patterns; placing a cover plate on the semiconductor package module and over the semiconductor chips; the cover plate including a heat dissipation member adhered to an inner surface of the cover plate facing the semiconductor package module to dissipate heat generated from the semiconductor chip, and the heat dissipation member including a penetration hole; and forming a penetration electrode such that the penetration electrode penetrates the semiconductor package module so as to extend between upper and lower surfaces of the semiconductor package module and to penetrate at least the insulation substrate and a circuit pattern of the plurality of circuit patterns, wherein the penetration electrode penetrates through the circuit pattern between the upper and lower surfaces of the semiconductor package module so as to be electrically connected to the circuit patterns, and wherein the penetration hole is formed to have a thickness that is greater than that of the penetration electrode and the penetration electrode is formed so as to penetrate through the penetration hole in a manner such that a space is formed between the penetration hole and a portion of the penetration electrode penetrating therethrough.