Patent ID: 7506140

Claim:
An apparatus for selecting one of N functional units in a microprocessor to provide its instruction result on a data bus to a pipeline of the microprocessor, wherein a subset of the N functional units may request to provide their results in a selection cycle, the apparatus comprising: a first input, for receiving a first corresponding N-bit value specifying which of the N functional units was last selected to provide its results, wherein only one of said N bits of said first value corresponding to said last selected functional unit is true; a second input, for receiving a second corresponding N-bit value, each of said N bits of said second value being false if said corresponding one of the N functional units is requesting to provide its result; a barrel incrementer, coupled to said first and second inputs, configured to add said second value to a 1-bit left-rotated version of said first value to generate a sum and a carry-out bit, wherein said barrel incrementer includes said carry-out bit as a carry-in bit of the add to generate the sum; and hardware combinational logic, coupled to said barrel incrementer, configured to generate a third corresponding N-bit value specifying which of the N functional units is selected next to provide its result, said third value comprising a Boolean AND of said sum and an inverted version of said second value, wherein only one of said N bits of said third value corresponding to said next selected one of the N functional units is true.