Patent ID: 7624382

Claim:
A processor, comprising: fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the processor; and decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions, wherein the processor is configurable to execute the plurality of instructions and to construct a control flow graph for the plurality of instructions, wherein when the processor is configured to construct the control flow graph, each instruction in the first native instruction set of the processor is associated with a micro-sequence configured to generate a portion of the control flow graph corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the control flow graph is constructed, and when the processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction, wherein a micro-sequence is one or more instructions from a second native instruction set of the processor.