Patent ID: 7279939

Claim:
A semiconductor device comprising: a first logic element and a second logic element; at least two cross-coupled inverters connected between the first logic element and the second logic element to form a current sense amplifier, one of the at least two cross-coupled inverters having an output electrically connected to an out terminal and another output electrically connected to an out bar terminal; a decoupling mechanism connected to the at least two cross-coupled inverters, the decoupling mechanism also disposed to accept a sense enable signal that selectively enables and disables the current sense amplifier; a discharge mechanism connected to the at least two cross-coupled inverters to remove excess charge when the current sense amplifier is disabled; a selectively enabled low impedance path from at least one of the at least two cross-coupled inverters to ground; and a sense enable generating circuit to generate the sense enable signal from an equalizing signal in part by applying a delay to the equalizing signal.