Patent ID: 8526601

Claim:
A method of implementing a function by a respective logic block in a plurality of logic blocks connected in parallel to receive inputs from a plurality of registers where each register has an individual connection to each of the plurality of logic blocks, the running of the function by the respective logic block being based on an input of a first variable from a first register which may have a first or a second value, and an input of a second variable from a second register which may have a first or a second value, comprising: setting the value of the second variable from the second register to the first or the second value thereof; running the function at the plurality of logic blocks based on an input of the first variable set at the first value thereof, and an input of the second variable having said set value thereof, to provide a first output; running the function at the plurality of logic blocks based on an input of the first variable set at the second value thereof, and an input of the second variable having said set value thereof, to provide a second output, wherein the functions of the plurality of logic blocks are run simultaneously.