Patent ID: 7205612

Claim:
A device for dissipating electrostatic discharge in an integrated circuit comprising: a p-region in a semiconductor substrate; a source n-well and drain n-well in said p-region; gate oxide overlying said p-region in the space between said source n-well and said drain n-well; an n+ source region and an n+ drain region within said source n-well and said drain n-well, respectively, wherein surfaces of said n+ source region and said n+ drain region are silicided; a lightly doped source region and a lightly doped drain region within said source n-well and said drain n-well, respectively; a gate electrode overlying said gate oxide; a dielectric layer overlying said gate electrode and said source and drain regions; and conductive contacts through said dielectric layer to said silicided n+ source region and said silicided n+ drain region and electrically connecting said gate electrode to said silicided n+ source thereby completing fabrication of said device for dissipating electrostatic discharge.