Patent ID: 7589507

Claim:
A low drop out voltage regulator (LDO) that receives an input supply voltage at the input terminal and provides a regulated output voltage at the output terminal comprising: an error amplifier responsive to a difference between a predetermined reference voltage and a function of the output voltage to produce an error signal; a driver transistor responsive to said error signal to adjust the current to the output load and reduce the error signal; an NMOS current sink transistor having its drain connected to the output terminal of said LDO; a load capacitor connected to the output terminal of said LDO; and a stability compensation circuit comprising: a source follower having an input terminal connected to the output terminal of said LDO to provide a small signal gain nearly equal to one from its input to output terminal with a dc output voltage being lower than a dc input voltage; a resistor having a first terminal connected to an output of said source follower; a voltage dependent compensation capacitor having an negative terminal connected to a second terminal of said resistor, and a positive terminal connected to the output of said error amplifier, wherein said capacitor remains in an accumulation region at no load current to provide a maximum capacitance, and the capacitance of said capacitor decreases with a load current during a depletion region operation at higher load current region; and a parasitic pole reshaping PMOS transistor operating in a saturation region having a gate connected to the output of said error amplifier, a source connected to said input power supply, and a drain connected to the negative terminal of said capacitor.