Patent ID: 8339198

Claim:
A negative capacitance circuit, comprising: a first transistor (Q 1 ) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the first transistor (Q 1 ) connected to a first voltage rail; a second transistor (Q 2 ) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the second transistor (Q 2 ) connected to the first voltage rail; a third transistor (Q 3 ) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the control terminal (base or gate) of the third transistor (Q 3 ) connected to the second current path terminal (emitter or source) of the first transistor (Q 1 ), and the first current path terminal (collector or drain) of the third transistor (Q 3 ) connected to the control terminal (base or gate) of the second transistor (Q 2 ); a fourth transistor (Q 4 ) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the control terminal (base or gate) of the fourth transistor (Q 4 ) connected to the second current path terminal (emitter or source) of the second transistor (Q 2 ), and the first current path terminal (collector or drain) of the fourth transistor (Q 4 ) connected to the control terminal (base or gate) of the first transistor (Q 1 ); a first bias current source (Ibias) connected between the second current path terminal (emitter or source) of the first transistor (Q 1 ) and a second voltage rail; a second bias current source (Ibias) connected between the second current path terminal (emitter or source) of the second transistor (Q 2 ) and the second voltage rail; a third bias current source (Ibias) connected between the second current path terminal (emitter or source) of the third transistor (Q 3 ) and the second voltage rail; a fourth bias current source (Ibias) connected between the second current path terminal (emitter or source) of the fourth transistor (Q 4 ) and the second voltage rail; a first capacitor (C 1 ) connected between the second current path terminal (emitter or source) of the fourth transistor (Q 4 ) and the second voltage rail; and a second capacitor (C 2 ) connected between the second current path terminal (emitter or source) of the third transistor (Q 3 ) and the second voltage rail.