Patent ID: 8234440

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array divided into N banks, each of which includes a multi-level cell (MLC) area; N page buffers, each respectively associated with a corresponding one of the N banks and being configured to load a page data; and N caches, each respectively associated with a corresponding one of the N banks and being configured to include a part of the MLC area in the corresponding bank, wherein the page data is loaded to a corresponding page buffer among the N page buffers and then is programmed to a corresponding cache using single-level cell (SLC) programming, and the page data is read from the corresponding cache to the corresponding page buffer, wherein the page data is not transmitted to outside of the nonvolatile semiconductor, and then is programmed from the corresponding page buffer to the MLC area in a corresponding bank using multi-level cell (MLC) programming.