Patent ID: 8140921

Claim:
An elevator electronic safety system for checking the integrity of a memory system in an elevator electronic safety apparatus, comprising: a CPU having a designated address output software and a data bus malfunction check software; a main memory and an auxiliary memory arranged in parallel and sharing a same address space, the main memory being directly connected to said CPU through an address bus and a data bus, the auxiliary memory being connected to the CPU through the address bus and connected to a data buffer through the data bus, the data buffer being directly connected to the CPU and the main memory through the data bus and being configured to prevent data from both the main memory and auxiliary memory from being transmitted to the CPU to avoid data collisions between the main memory and auxiliary memory; a memory data malfunction check circuit that compares data in said main memory and data in said auxiliary memory; and a designated address detection circuit connected to said CPU through said address bus, wherein said CPU executes said designated address output software to perform a malfunction check on said address bus in a periodic manner using said designated address detection circuit to periodically detect a designated address on the address bus, and said CPU executes said data bus malfunction check software to perform a malfunction check on said data bus in a periodic manner using said main memory and said auxiliary memory.