Patent ID: 6925576

Claim:
A control unit for executing data communication between itself and another control unit, the control unit outputting a signal for resetting said another control unit through a bus line when the control unit is reset, comprising: a CPU which is operated in accordance with a prescribed program; a watchdog timer for monitoring operations of the CPU and outputting a reset signal to return the CPU to an initial condition when an abnormal state of the CPU is detected; a high frequency oscillator for producing first clock pulses for operating the CPU at a first frequency; a low frequency oscillator for producing second clock pulses for operating the CPU at a second frequency which is lower than said first frequency; exchanging means for exchanging clock pulses for operating the CPU from said first clock pulses to said second clock pulses when a prescribed condition is satisfied, thereby shifting the CPU to a low power consumed state; abnormality detecting means for detecting abnormality of the low frequency oscillator; and exchange stopping means for stopping exchange of the clock pulses by said exchanging means if said abnormality detecting means detects the abnormality when said prescribed condition is satisfied.