Patent ID: 7382159

Claim:
An input buffer circuit having an input terminal and an output terminal, comprising: a voltage limiting circuit operable to receive an input signal at a first voltage range and to limit the input signal to a safe voltage range, wherein the first voltage range is between a first supply voltage level and an electrical ground; a level detecting circuit having a pull-down component electrically coupled to the voltage limiting circuit for receiving the safe voltage level and a pull-up component electrically coupled to the input terminal for receiving the input signal to transition the input signal to the input signal at a second voltage range, wherein the second voltage range is between a second supply voltage level and the electrical ground; and a protection circuit comprising a first PMOS transistor electrically coupled between the pull-up component and the pull-down component of the voltage level detecting circuit, a gate of the first PMOS transistor electrically coupled to the level detecting circuit and the pull-down component, a drain of the first PMOS transistor electrically coupled to the output terminal, a source of the first PMOS transistor electrically coupled to the pull-up component of the level detecting circuit, a second PMOS transistor, a gate of the second PMOS transistor electrically coupled to a drain of the second PMOS transistor and to the source of the first PMOS transistor, a source of the second PMOS transistor electrically coupled to the second supply voltage level.