Patent ID: 8306803

Claim:
A computer based method for verifying, prior to fabrication, a proper operation of an integrated circuit electronic system using analog signals, comprising the steps of: identifying noise-sensitive circuits of said integrated circuit electronic system; setting an acceptable sensitivity threshold template for said noise-sensitive circuits using a circuit model; modeling noise using a circuit model; determining a function for transferring the noise to said sensitive circuits using a circuit model; comparing a level of noise reaching said noise-sensitive circuits to said acceptable sensitivity threshold template for said sensitive circuits; identifying noise generating circuits; assigning variable weights to said noise generating circuits based on their proximity to said noise-sensitive circuits; subdividing a two-dimensional space of said integrated circuit electronic system into subdivisions, wherein a pitch of a subdivision increases as a function of a distance from said noise-sensitive circuits; performing a simplification for each subdivision to retain only one equivalent contribution from all of said noise-generating circuits located in that subdivision by considering all electrical elements located between two identical nodes to be parallel, each power supply network in that subdivision to be connected to a substrate by a single virtual physical object having a given shape whose area is a sum of areas of real physical objects found in each circuit of that subdivision, and a position of the virtual physical object to correspond to a barycenter of all surfaces considered; and wherein said circuit model takes into account a coupling through a substrate, and a coupling through interconnections and through a package, the package modeled by inductor and resistor elements and the interconnections modeled by inductor, resistor and capacitor elements.