Patent ID: 7470948

Claim:
A cell array structure of a NAND flash memory, comprising: a semiconductor substrate including an active region therein and having an inner region and an outer region; a memory gate structure including a plurality of word lines crossing over the active region, the memory gate structure being disposed on the inner region; a select gate structure crossing over the active region, wherein the select gate structure comprises a plurality of string selection lines and a plurality of ground selection lines respectively disposed on opposite sides of the memory gate structure, respectively; and impurity regions disposed in the active region between the plurality of word lines, between the plurality of string selection lines, between the plurality of ground selection lines, between one of the plurality of string selection lines and an immediately adjacent one of the plurality of word lines, and between one of the plurality of ground selection lines and an immediately adjacent one of the plurality of word lines, wherein the impurity regions in the inner region have different impurity concentration distributions than the impurity regions in the outer region, and wherein one of the plurality of string selection lines and one of the plurality of ground selection lines are disposed on respective interfaces between the inner region and the outer region on the opposite sides of the memory gate structure.