Patent ID: 7085285

Claim:
A communications system comprising: a digital data buffer circuit for storing digital data, said digital data including both receive data and transmit data; and a shared signal processing circuit for performing a set of signal processing operations on both said receive data and said transmit data, said set of signal processing operations associated with a digital subscriber loop (DSL) based communications transmission, said shared signal processing circuit having computing resources shared by a receive task and a transmit task; said computing resources including a set of independent application specific (ASIC) logic circuits interconnected by a local bus and using a common clock, said set of independent ASIC logic circuits including at least one multi-tasking ASIC logic circuit, and which multi-tasking ASIC logic circuit, during a single period of said common clock, selectively performs at least one of a first signal processing operation on said receive data or a second signal processing operation on said transmit data; and wherein said multi-tasking ASIC logic circuit performs either a transport convergence transmit related operation or a transport convergence receive related operation on a DMT based symbol associated with said digital data.