Patent ID: 7151059

Claim:
A process for fabricating an integrated circuit, comprising: forming an oxide over a substrate, said oxide being defined by a width, said forming said oxide including (a) exposing said substrate to a first oxidizing ambient, wherein exposing said substrate to a first oxidizing ambient includes increasing from an initial temperature to a first temperature below a threshold temperature at a first ramp rate, increasing from said first temperature to a second temperature below said threshold temperature at a second ramp rate, and growing at least a portion of said oxide; (b) exposing said substrate to a second oxidizing ambient, wherein exposing said substrate to a second oxidizing ambient includes increasing from said second temperature to a third temperature at a third ramp rate, and increasing from said third temperature to a temperature above said threshold temperature at a fourth ramp rate; and (c) cooling said substrate to a temperature below said threshold temperature, wherein said oxide and said substrate form an interface that is substantially stress free and planar; forming within said substrate a source, a drain and a channel extending from said source to said drain, wherein said source and said drain do not include lightly doped regions; and forming a gate structure over said substrate, said gate structure having a length of approximately 1.25 μm or less and being coextensive with said width of said oxide.