Patent ID: 8211803

Claim:
A method for integrated circuit fabrication, comprising: providing a selectively definable layer above a substrate; forming a row of pillars and at least one block of selectively definable material extending along the row of pillars by patterning the selectively definable layer, wherein the block extends to contact the pillars, the pillars having a linear density Z: replacing the row of pillars with a mask having a row of holes, the mask and holes disposed on the level, the holes having a width of about 60 nm or less, at least some of the holes disposed at a location formerly occupied by a pillar, the holes having a linear density at least about 1.5 times Z; and transferring a mask pattern formed by the mask having the row of holes to the substrate to form a row of contact vias in the substrate, wherein transferring the mask pattern to the substrate comprises: transferring the mask pattern to a primary masking layer; and etching the substrate through the primary masking layer to etch the mask pattern to the substrate.