Patent ID: 7506176

Claim:
A method of encryption and decryption on a multi-core processor, said method comprising: a master core receiving a plain text and a plurality of plain-text segment lengths into a master core local memory of said master core; said master core splitting said plain text into a plurality of plain-text segments; wherein a first plain-text segment of said plurality of plain-text segments has a first length equal to a first plain-text segment length of said plurality of plain-text segment lengths; forming a first padded-plain-text segment by padding said first plain-text segment by a first number of padding bytes; wherein said first number of padding bytes is equal to a difference between a maximum transfer length and said first length; wherein said maximum transfer length is associated with a first encryption method; transferring said first padded-plain-text segment to a first local memory of a first synergistic processor element; wherein said first synergistic processor element is one of a plurality of synergistic processor elements; said first synergistic processor element encrypting said first padded-plain-text segment to a first encrypted-text segment; wherein in said encrypting step, said first synergistic processor element uses said first encryption method with an encryption key; transferring said first encrypted-text segment from said first local memory to said master core local memory; wherein said first encrypted-text segment is one of a first plurality of encrypted-text segments; said master core aggregating said first plurality of encrypted-text segments into an encrypted text; said master core transferring said encrypted text to a main memory; said master core reading said encrypted text from said main memory into said master core local memory; said master core splitting said encrypted text into a second plurality of encrypted-text segments; wherein a second encrypted-text segment is one of said second plurality of encrypted-text segments; transferring said second encrypted-text segment from said master core local memory to said first local memory; said first synergistic processor element decrypting said second encrypted-text segment to a second padded-plain-text segment; wherein in said decrypting step, said first synergistic processor element uses a first decryption method corresponding to first encryption method; transferring said second padded-plain-text segment to said master core local memory from said first local memory; forming a second plain-text segment by removing said first number of padding bytes from said second padded-plain-text segment; wherein said second plain-text segment is one of a second plurality of padded-plain-text segments; said master core aggregating said second plurality of padded-plain-text segments into said plain text; and said master core transferring said plain text to said main memory.