Patent ID: 7417505

Claim:
A memory circuit, comprising: a first bit line; a second bit line; and a sense amplifier including: a differential input circuit including: a first differential input node coupled to the first bit line; a second differential input node coupled to the second bit line; a first differential output node; a second differential output node; a first MOS input transistor having a gate terminal coupled to the first differential input node, a drain terminal coupled to the first differential output node, and a source terminal; and a second MOS input transistor having a gate terminal coupled to the second differential input node, a drain terminal coupled to the second differential output node, and a source terminal coupled to the source terminal of the first MOS input transistor, wherein the first and second MOS input transistors are approximately matched MOS transistors each having a gate-to-drain capacitance approximately equal to a first capacitance; a first voltage reference node; a load circuit coupled between the first voltage reference node and the differential input circuit; and a first compensating capacitor directly coupled between the second differential output node and the first differential input node, the first compensating capacitor having a capacitance approximately equal to the first capacitance.