Patent ID: 8667435

Claim:
A computer-implemented method of implementing a circuit design within a programmable integrated circuit, the method comprising: generating a plurality of cut sets for the circuit design; determining a number of inter-cut symmetric signal sets of each cut set; selecting a cut set from the plurality of cut sets, at least in part according to the number of inter-cut symmetric signal sets of each cut set, wherein each cut of the selected cut set represents an instantiation of at least one logic component within the programmable integrated circuit; technology mapping the circuit design according to the selected cut set; selecting, via a computer, a cone of the circuit design, wherein the cone comprises a plurality of logic components implementing a logic function of the technology mapped circuit design; performing, via the computer, functional decomposition on the cone according, at least in part, to symmetry of signals of the selected cone, to generate a decomposed logic function; assigning, via the computer, the decomposed logic function to logic components; and outputting the circuit design specifying assigned logic components for the decomposed logic function.