Patent ID: 7295640

Claim:
A phase detector, comprising: a reference signal input for receiving a reference signal and a detector input for receiving a signal to be evaluated; a memory unit connected to said detector input for storing a state of the signal to be evaluated at a storage instant, said memory unit having a first memory device and a second memory device; said first memory device having a first input for receiving and storing the signal to be evaluated; said second memory device having a first input for receiving and storing an inverted version of the signal to be evaluated; each of said first and second memory devices having a second input for receiving a signal prescribing the storage instant; an evaluation unit connected downstream of said memory unit, in a signal flow direction, and adapted to compare the stored state of the signal to be evaluated and the stored state of the inverted signal to be evaluated at an evaluation instant according to the reference signal to generate an evaluation result signal therefrom; a control unit for prescribing the storage instant and the evaluation instant, said control unit being connected to said memory unit and to said evaluation unit and configured to first prescribe the storage instant and subsequently prescribe the evaluation instant; and an output connected to said evaluation unit and carrying the evaluation result signal.