Patent ID: 8347257

Claim:
A method for reworking a plurality of cells initially placed in a circuit design, the computer implemented method comprising: a computer allocating cells to tiles, wherein some tiles have at least two cells; the computer determining a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles; the computer selecting a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile; the computer placing an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile; the computer expanding the selected cell within the bounding box to form a modified design based on the circuit design; the computer determining an aggregate routing cost for the selected tile based on the modified design and an aggregate routing cost for a target tile based on the modified design; the computer determining whether the aggregate routing cost for the selected tile is greater than the aggregate routing cost for a target tile; and the computer affirming the modified design for further processing, in response to a determination that the aggregate routing cost for the selected tile is greater than the aggregate routing cost for the target tile.