Patent ID: 6993638

Claim:
A device comprising an address history table storing in a pair at least a partial bit string of a logical address and bits of an absolute address corresponding to the partial bit string of the logical address that are needed as a retrieval key of a memory based on an absolute address; a retrieval unit retrieving data from a register file in the case of memory access, reading a value corresponding to a register number of the register file and retrieving data from the address history table using the value as the logical address and using a partial aggregate of the logical address; a memory access unit accessing a memory using a predicted absolute address obtained by retrieving data from the address history table; a Translation-Lookaside Buffer (TLB) obtaining the correct absolute address using the logical address; a memory access result confirmation unit checking for coincidence between the predicted absolute address and the correct absolute address and confirming a result of memory access made using the predicted absolute address; and a prediction unit judging whether carry crossing pages is caused from a register value as a result of the addition in a case where a value obtained by adding a displacement value to the register file value in memory access is designated as a memory access value.