Patent ID: 8537595

Claim:
A resistance change memory device comprising: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting the selected word line thereby selecting a memory cell, and to select a reference bit line at the same time, thereby selecting a reference cell connected to a selected word line connected to a selected memory cell in the same mat; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the bit line that is selected and the reference cell on the reference bit line.