Patent ID: 7523282

Claim:
A memory subsystem comprising: a memory controller coupled to one or more memory modules, each memory module comprising a buffer coupled to a plurality of memory ranks; and a clock source coupled to provide a clock signal to each of the memory modules; wherein the memory controller is configured to convey a clock enable (CKE) command to at least one of the memory modules, the CKE command including a plurality of CKE signals, each corresponding to a respective one of the plurality of memory ranks of the at least one of the memory modules; wherein in response to the CKE command: a memory module buffer is configured to convey a CKE disable signal to each memory rank for which the corresponding one of the plurality of CKE signals has a first value; and each memory rank is configured to disable operation of the clock signal within at least a portion of the memory rank, responsive to the CKE disable signal.