Patent ID: 8356143

Claim:
A bus master prefetch unit for optimizing memory bus bandwidth, the bus master prefetch unit comprising: means for receiving a request from a bus master of a plurality of bus masters for accessing a particular line of data in a memory device through a memory bus; means for verifying if the received request is for data stored in the bus master prefetch unit; means for generating at least one prefetch request for accessing at least one line of data in the memory device, the at least one line of data being next to the line of data for which the received request is received from the bus master; means for arbitrating between said request from the bus master and said at least one prefetch request; means for obtaining data from the memory device, the data corresponding to the prefetch request; and a prefetch buffer for storing the obtained data as stored data, wherein the stored data is operable to be served to the bus master when the bus master requests the stored data.