Patent ID: 7640422

Claim:
A method of reducing lookups to a branch target address cache (BTAC) using an instruction cache (I-cache), the method comprising: retrieving a first branch target address from the BTAC in response to a miss in looking up a first instruction address of a first branch instruction stored in the I-cache; and storing the first branch target address retrieved from the BTAC in the I-cache at a first location associated with the first instruction address, wherein the I-cache is configured to store a plurality of instructions including the first branch instruction, wherein the first branch target address retrieved from the BTAC and stored in the I-cache was provided to the BTAC in response to detection of a prior branch resolution of the first branch instruction in a processing stage of a pipeline; and in response to a lookup of the first instruction address at the I-cache, retrieving the first branch target address from the I-cache when the first branch target address is stored at the I-cache.