Patent ID: 8547154

Claim:
A device for generating a waveform according to a programmable duty cycle from a frequency reference signal that may be divided, said device comprising: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator further comprising: a frequency doubler that outputs clock pluses that are double a frequency of said CLOCK signal; a ½ CLOCK pulse generator that produces one ½ of a CLOCK cycle from said output of said divider and an output of said doubler at said beginning of every evaluative cycle; high and low clock pulse counters that generate high and low clock pulses, which are said double frequency of said CLOCK signal during a current evaluative cycle, said high and low pulses being gated by high and low portions of a fed back output of said waveform generator, OUT, corresponding to a duty cycle for said current evaluative cycle; a bit comparator that compares high and low clock bit counts from said high and low clock pulses, and if said duty cycle for said current evaluative cycle is less than a bit value of said programmed duty cycle, then outputs an increment signal, INC, after a last low clock pulse is counted for said current evaluative cycle and before a beginning of a next evaluative cycle; a ½ CLOCK shifter that shifts a duty cycle of OUT from said current evaluative cycle by ½ of a CLOCK cycle, upon receiving said INC signal and before said beginning of said next evaluative cycle; and a pulse width accumulator that receives said one ½ of a CLOCK cycle and said shifted duty cycle of OUT for said current evaluative cycle, and forms a pulse width of a waveform of said duty cycle of OUT, which is incremented ½ of a CLOCK cycle relative to a beginning of said duty cycle of OUT for said current evaluative cycle, at said beginning of said next evaluative cycle.