Patent ID: 6886106

Claim:
A dynamically alterable clock comprising: means for determining if an integer value generated by a microprocessor has a value of 1; if the integer value is 1, means for sending an input parent clock value to a glitchless clock and sample cycle multiplexer for outputting as an output clock value and means for sending a signal to the glitchless clock and sample cycle multiplexer to output a high signal value as a sample cycle output; and if the integer value is greater than 1, means for generating a duty-cycle-corrected clock signal from the input parent clock value that has been divided, and sending the duty-cycle-corrected clock signal to the glitchless clock and sample cycle multiplexer for outputting as an output clock value, and means for generating a sample cycle signal, and sending the sample cycle signal to the glitchless clock and sample cycle multiplexer for outputting as a sample cycle value.