Patent ID: 7162617

Claim:
A processor having changeable architecture, the processor having a processor core and having an execution unit and being connected with means, outside the processor core, for memorizing instructions, the processor comprising: means for generating instruction fetch addresses, for generating addresses of instructions to be fetched from said memorizing means; means for deciding, from among a plurality of groups, a group to which an instruction fetched from said memorizing means belongs, based on at least one property that represents a characteristic of said instruction; storing means, within the processor core, for storing processor architecture constitution information required for generating, from said fetched instructions, native instructions that said execution unit can execute directly, said storing means including an instruction merge information memory for storage of native instruction merge information derived from said means for deciding a group; means for extracting instruction parameter fields from said fetched instructions based on said native instruction merge information; means for merging the extracted instruction parameter fields and information based on said native instruction merge information, and thereby generating native instructions for execution by the execution unit; means for controlling said instruction fetch address generating means and discontinuously updating said instruction fetch addresses when instructions are branched in said execution unit; and means for designating a reference starting position to said processor architecture constitution information storing means; whereby a processor architecture can be selected from a plurality of processor architectures by updating said reference starting position, thus enabling execution of software designed for plural different processor architectures.