Patent ID: 8799843

Claim:
A method for performing buffering optimization, the method comprising: receiving a net that electrically connects an output of a driver gate with a set of sinks; determining, by computer whether or not buffering is expected to improve a delay of a path that passes through the net by at least using logical effort and parasitic delay values of the driver gate and logical effort and parasitic delay values of one or more buffers from a technology library, wherein said determining comprises: determining a first delay from an input of the driver gate to the set of sinks; determining optimal sizes for one or more candidate buffers that are being considered to be added to the net; determining a second delay from the input of the driver gate to the set of sinks assuming that the one or more candidate buffers with their optimal sizes have been added to the net; and determining whether or not buffering is expected to improve the delay of the path based on comparing the first delay with the second delay; in response to determining that buffering is expected to improve the delay of the path, performing buffering optimization on the net; and in response to determining that buffering is not expected to improve the delay of the path, skipping performing buffering optimization on the net.