Patent ID: 7874065

Claim:
A process for making a multilayer circuit board device having electrically isolated tightly spaced electrical current carrying traces, comprising: providing a substrate made of a first layer of electrical insulating material having a first layer of conductive material affixed to one side thereof to form a ground plane; providing a plurality of elongated metallic first seed layer traces on a second side of the substrate, said seed layer traces having transverse widths of approximately 25 microns or less with adjacent traces being separated from each other by first elongated spaces; developing within said first elongated spaces upstanding first ribs of photoresist forming first vertical walls rising above the upper surface of adjacent seed layer traces to a height greater than 25 microns, said first walls defining open first channels above said first seed layer traces; depositing a first conductive signal trace material having a thickness exceeding 25 microns in height into said channels and over said seed layer traces; and stripping away said ribs to leave a plurality of elongated first conductive traces having a height-to-transverse-width ratio exceeding 1, said first conductive traces being variously useful as ground lines, signal lines and/or power lines.