Patent ID: 7979821

Claim:
A method of verifying a semiconductor integrated circuit in an IO region of which a controlling cell and a controlled cell controlled by a control signal output from said controlling cell are placed, said method comprising: providing a library that includes requirement information specifying said controlling cell required by said controlled cell; obtaining a region information indicating a region within said IO region in which a signal interconnection through which said control signal is transmitted is provided; and verifying, by using a computer, whether or not said specified controlling cell is placed within said region, in a case where said controlled cell is placed within said region, wherein said library includes IO cell data of plural kinds of IO cells including said controlling cell and said controlled cell, and each of said IO cell data associated with each IO cell includes physical information indicating positions of terminals of interconnections included in said each IO cell, and wherein said obtaining said region information comprises: detecting a location of an interconnection for transmitting said control signal, by reference to said physical information of IO cells placed in said IO region; and generating said region information by extracting a region in which said interconnection for transmitting said control signal is consecutively located.