Patent ID: 7038925

Claim:
A static semiconductor memory device, comprising: a number M×N (M: integer not less than 2; N: integer not less than 2) of memory blocks each of which include a number 8×M of horizontal memory cells arranged in eight rows by M columns and which are arranged in M rows by N columns, a word line provided corresponding to each memory cell row of each memory block, first and second bit lines provided in common for the number M of memory block rows so as to correspond to each memory cell column, first and second bit line signal input/output lines provided corresponding to each memory block and connected to the first and second bit lines of a predetermined pair of the corresponding M pairs of the first and second bit lines, respectively, first and second data input/output lines provided corresponding to each memory block row for inputting/outputting data of the corresponding memory block row, first and second power supply lines provided corresponding to each memory block row, a global word line provided corresponding to each memory block row for selecting the corresponding memory block row, a global column selecting line provided in common for the number M×N of memory blocks so as to correspond to each memory cell column for selecting the corresponding memory cell column, a selection circuit responsive to an address signal for driving said word line, said global word line and said global column selecting line to select any one memory block of said number M×N of memory blocks and any one memory cell of the number 8×M of memory cells belonging to the memory block, a write/read circuit for writing/reading data of said memory cell, and a gate circuit for coupling a memory cell selected by said selection circuit to said write/read circuit through said first and second bit lines, said first and second bit line signal input/output lines and said first and second data input/output lines, wherein in each memory block column, the M sets of said first and second bit line signal input/output lines, said first and second data input/output lines, said first and second power supply lines, said global word lines and said global column selecting line are arranged above the number M of memory blocks respectively, and extend in the same direction as that of said word line, each set of said first and second bit line signal input/output lines, said first and second data input/output lines, said first and second power supply lines and said global word lines and said global column selecting lines are arranged above eight memory cell rows included in the corresponding memory block, respectively, said first power supply line is arranged between said first and second bit line signal input/output lines and said first and second data input/output lines, and said global word line, and said second power supply line is arranged between said first and second bit line signal input/output lines and said first and second data input/output lines, and said global column selecting line.