Patent ID: 8769354

Claim:
A memory architecture with a parallel interface and a serial interface which is used only during testing, comprising: a serial direct access (SDA) circuit comprising: a first set of parallel pins for parallel interface operation; an enable pin for receiving an enable bit, wherein the SDA circuit is enabled when the enable bit equals a first logic value, and is disabled when the enable bit equals a second logic value; a second set of parallel pins outputted from the SDA circuit, wherein the second set of parallel pins is arranged to relay the first set of parallel pins when the enable bit equals the second logic value; a serial pin for sequentially relaying a plurality of serial bits when the SDA circuit is enabled, such that each of the serial bits is associated with one of the second set of parallel pins; and an auto-test module for at least one of the following: performing a built-in test of the memory instructed by the serial bits when the SDA circuit is enabled, and reporting result the built-in test by the serial bits when the SDA circuit is enabled; and a memory comprising a plurality of parallel pins respectively coupled to the second set of parallel pins.