Patent ID: 6912624

Claim:
A method for maximizing the use of on-chip cache memory capacity in a chip-multiprocessors, comprising: forming a two-level cache system with an exclusive cache hierarchy in order to minimize cache line replication and on-chip traffic, the two-level cache system including a first level cache dedicated to each processor in the chip-multiprocessor and a second-level cache shared by all the processors; associating cache lines with an indication of ownership so that among one or more than one instances of each cache line present in the two-level cache system, there is only one instance that is an owner instance, the indication of ownership being provided only in a second-level cache; associating the cache lines with state information that includes the indication of ownership, the state information for cache lines present in the first-level cache being maintained in the second-level cache; and administering cache line ownership and write-backs based on a predetermined guideline.