Patent ID: 8278182

Claim:
A method of isolating active areas of a memory cell array, the method comprising: providing a plurality of memory cells formed on a substrate and being arranged into rows and columns, each memory cell comprising an access transistor and a capacitor; providing a plurality of wordlines, each wordline electrically connected to a respective access transistor in each memory cell in a row; providing a plurality of bit lines, each bit line electrically connected to a respective capacitor in each memory cell in a column through a respective access transistor in the memory cell; providing, a plurality of isolation regions, each isolation region located adjacent to a respective capacitor in at least one memory cell in a row, said isolation region comprising an isolation gate and a substrate region comprising a trench, said isolation gate comprising an isolation gate electrode and a gate dielectric comprising a layer of aluminum oxide, the gate dielectric formed over the trench; and applying a voltage potential to said gate dielectric such that said isolation region is capable of forming a hole accumulation region surrounding said trench.