Patent ID: 6930524

Claim:
A delay-locked loop, comprising: a clock multiplier that generates a multiplied clock signal responsive to an input clock signal, the multiplied clock signal having a frequency that is a multiple of a frequency of the input clock signal; a variable delay circuit coupled to the clock multiplier and operable to generate a delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal and the variable delay circuit controlling the value of the delay responsive to a delay control signal, and wherein the variable delay circuit further comprises: a clock divider that generates a divided clock signal responsive to the delayed clock signal, the divided clock signal having a frequency that is a sub-multiple of a frequency of the delayed clock signal; and a phase detection and correction circuit coupled to receive the divided clock signal and the input clock signal, the circuit operable to detect a phase difference between the two clock signals, and operable in a first mode when the detected phase equals approximately 180 degrees to generate a synchronized clock signal that is inverted relative to the divided clock signal, and operable in a second mode to provide the divided clock signal as the synchronized clock signal; and a comparison circuit coupled to the clock multiplier and to the variable delay circuit, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal.