Patent ID: 8799589

Claim:
A method in a multiprocessor data processing system including a cache memory of an affiliated processor core, the affiliated processor core, a plurality of remote processor cores, and an interconnect communicatively coupling the cache memory to receive operations initiated by the plurality of remote processor cores, the method comprising: caching data in a data array of the cache memory, wherein the data includes a cache line associated with a target address; maintaining a directory of the data held in the data array, wherein the directory includes coherence state information for the data; the cache memory processing operations snooped from the interconnect by reference to the data array and the directory, wherein the processing includes: in response to the cache memory snooping on the interconnect a first storage-modifying operation of the plurality of remote processor cores that specifies a same target address as that of a first read-type operation of the plurality of remote processor cores that was previously snooped from the interconnect is then being serviced by the cache memory, the cache memory determining whether the cache memory is designated by the coherence state information as responsible for servicing operations specifying the target address; in response to a determination that the coherence state information designates the cache memory as responsible for servicing operations specifying the target address, the cache memory providing a retry response to the first storage-modifying operation; in response to completion of servicing of the read-type operation by the cache memory, the cache memory entering a referee mode, and while in the referee mode, the cache memory maintaining designation of the cache memory by the coherence state information as responsible for servicing operations specifying the target address and temporarily dynamically increasing priority of any second storage-modifying operation of the plurality of remote processor cores snooped from the interconnect that specifies the target address in relation to any second read-type operation of the plurality of remote processor cores snooped from the interconnect that specifies the target address.