Patent ID: 7339821

Claim:
A memory circuit, comprising: first and second strings of serially connected dual-gate memory cells, wherein each dual-gate memory cell comprises a memory device and an access device sharing a common channel region between a source region and a drain region; a first word line connecting a gate electrode of a memory device in each of the first and second strings; and a second word line connecting a gate electrode of an access device in each of the first and second strings; wherein, during programming of the memory device of the first string: (1) the second word line is first brought to a first predetermined voltage, while (a) the source and drain regions of the access device connected to the second word line in the first string are configured to be brought to a second predetermined voltage less than the first predetermined voltage; and (b) the source and drain regions of the access device in the second string connected to the second word line is configured to be brought to within a predetermined value of the first predetermined voltage; and thereafter, (2) the second word line is configured to be brought to a third predetermined voltage greater than the first predetermined voltage; and (3) the first word line is configured to be brought to a fourth voltage greater than the third predetermined voltage.