Patent ID: 8368231

Claim:
A chip stack package comprising: a package substrate including: a first surface, the first surface including at least a first terminal; and a second surface, the second surface including at least a second terminal, the second terminal being in electrical contact with the first terminal, wherein the second terminal is an external terminal of the package; and a first chip stacked on the package substrate, the first chip being a lowermost chip of the chip stack package, the first chip including: a first surface; a second surface; at least a first chip pad on the first surface of the first chip; at least a first connection via formed through a portion of the first chip and separate from the first chip pad, the first connection via having an upper surface and a lower surface; and at least a first rerouting line connecting the first chip pad and the first connection via, wherein the package substrate is a wafer substrate having a size bigger than a size of the first chip.