Patent ID: 7043384

Claim:
A failure detection system, comprising: a wafer test information input unit configured to acquire pass/fail maps for respective wafers for a plurality of types of semiconductor devices, the pass/fail maps displaying failure chip areas based on results of a plurality of electrical tests performed on a plurality of chip areas assigned on the respective wafers; an analogous test information input unit configured to classify the electrical tests into a plurality of analogous electrical tests with regard to analogous failures among the plurality of types of semiconductor devices; a subarea setting unit configured to assign a plurality of subareas, each of which is common to the types of semiconductor devices on a surface of the wafer; a characteristic quantity calculation unit configured to statistically calculate characteristic quantities based on a number of the failure chip areas included in the respective subareas for each of the analogous electrical tests; and a categorization unit configured to obtain correlation coefficients between the characteristic quantities corresponding to the respective subareas of the wafers, and to classify clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold value.