Patent ID: 8588355

Claim:
A timing recovery controller capable of performing timing recovery at twice a symbol rate, comprising: a sampler, for sampling a signal sequence according to a sampling rate, to generate a sampling sequence; a timing base device, coupled to the sampler, for generating a data sequence according to a timing base and the sampling sequence, the data sequence comprising a plurality of symbol data and a plurality of transition data, where a data rate of the data sequence is twice the symbol rate of the plurality of symbol data; a timing error detector, capable of detecting timing error at twice the symbol rate, comprising: a first delay unit, coupled to the timing base device, for receiving and delaying the data sequence with a data cycle corresponding to the data rate, to output a first delay data sequence; a second delay unit, coupled to the first delay unit, for receiving and delaying the first delaying data sequence with the data cycle, to output a second delay data sequence; and a timing error calculating module, coupled to the timing base device, the first delay unit and the second delay unit, for generating a timing error value when data of the data sequence is symbol data and transition data according to the data sequence, the first delay data sequence and the second delaying data sequence, to adjust the timing base; and a timing lock detector, capable of detecting a timing lock status at twice the symbol rate, comprising: a third delay unit, coupled to the timing base device, for receiving and delaying the data sequence with the data cycle, to output a third delay data sequence; and a timing lock determination module, coupled to the timing base device and the third delay unit, for generating a timing lock determination result when data of the data sequence is symbol data and transition data according to the data sequence and the third delaying data sequence.