Patent ID: 8039903

Claim:
A tiered gate structure transistor including a source, a drain, and a gate between the source and the drain, the tiered gate structure transistor comprising: a) a gate foot having sidewalls and a top portion, the gate foot comprising a conductive layer; b) a passivation layer extending along an uppermost surface of the source to the gate foot, the passivation layer extending along an uppermost surface of the drain to the gate foot, the passivation layer extending on the gate foot such that the passivation layer extends laterally up and along the sidewalls so as to overlay the sidewalls of the gate foot, the passivation layer being recessed from the top portion of the gate foot such that the top portion is not covered by the passivation layer, the passivation layer directly contacting the uppermost surface of the source and the uppermost surface of the drain and surrounding the sidewalls of the gate foot; and c) a gate head attached to the top portion of the gate foot and a portion of the passivation layer wherein the gate head is unpassivated, wherein the passivation layer having a generally uniform thickness directly contacts the uppermost surface of the source and the uppermost surface of the drain and surrounding the sidewalls of the gate foot providing an additional support to the gate head and increasing a structure integrity of the tiered gate structure transistor, the passivation layer having a generally uniform thickness over a substrate under the gate head and around the gate foot to provide a reduced capacitance between the gate head and the source and the drain.