Patent ID: 7803666

Claim:
A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure, comprising: providing a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer; bonding a plurality of chips onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the patterned conductive layer; electrically connecting the chips to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer; forming at least one molding compound to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires; and separating the molding compound, the patterned conductive layer and the patterned solder resist layer.