Patent ID: 7472361

Claim:
A method of producing models of a design of an integrated circuit, the method comprising: providing a master model of a design of an integrated circuit; and translating the master model to at least a first model and a second model that are functionally equivalent to the master model and at different levels of abstraction from each other and wherein each of the first model and the second model include timing information of the design accurate for its respective level of abstraction; wherein the translating the master model to a first model comprises using a synthesis tool to produce a register transfer level model that includes at least one register and control logic used for scheduling: and wherein the translating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model functionally equivalent to the register transfer level model; and further comprising: in translating the master model to the register transfer level model, marking the at least one register and the control logic used for scheduling; and omitting the marked at least one register and control logic from the at least one transaction level model or cycle accurate model.