Patent ID: 8227296

Claim:
A method of manufacturing a stacked semiconductor device, comprising: preparing a circuit base having an element mounting part and a connection part; bonding a first semiconductor element on the element mounting part of the circuit base, the first semiconductor element having an upper face and an electrode pad formed on the upper face; electrically connecting the electrode pad to the connection part with a bonding wire; bonding a second semiconductor element on the upper face of the first semiconductor element via an adhesive layer with a thickness of 50 μm or more while burying an end of the bonding wire connected to the electrode pad in the adhesive layer; and sealing the first and second semiconductor elements together with the bonding wire by a sealing resin to obtain the stacked semiconductor device, wherein the adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less and greater than zero ppm, so that a tensile stress acting on the first or second semiconductor element due to the adhesive layer during a thermal cycle test of the stacked semiconductor device is controlled to 300 MPa or less and greater than zero MPa.