Patent ID: 6888761

Claim:
A memory circuit comprising: a plurality of memory cells, organized into columns and rows, that are accessed during memory access cycles, which include refresh cycles and read/write cycles, wherein the memory cells are substantially continuously refreshed using the refresh cycles; a plurality of sense amplifiers, wherein each said sense amplifier is coupled to a corresponding one of the columns of the memory cells, and is used to read data stored in the memory cells of the corresponding column during read phases of the refresh cycles and the read/write cycles; and a plurality of write amplifiers, wherein each said write amplifier is coupled to a corresponding one of the columns of the memory cells of the corresponding column, and is used to write data to the memory cells during write phases of the memory access cycles, wherein the read phases of the refresh cycles substantially coincide with the write phases of the read/write cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the read/write cycles.