Patent ID: 8156260

Claim:
A data transfer device for performing direct memory access transfer of data stored in a storage unit to other devices, the data transfer device comprising: a plurality of channel units arranged to correspond to the other devices, wherein the channel units that retain direct memory access transfer instructions, and output a number of the direct memory access transfer instructions retained; priority controllers that determine first priorities of the channel units on the basis of the number of the direct memory access transfer instructions retained in the channel units, respectively; an arbiter that selects one of the direct memory access transfer instructions retained in one of the channel units on the basis of the first priorities determined by the priority controllers; and a data transfer processor that performs direct memory access transfer of data stored in the storage unit to one of the other devices in accordance with the direct memory access transfer instruction selected by the arbiter; wherein the arbiter is arranged to correspond to the first priorities being determined on the priority controllers, the arbiter including a plurality of arbiters, the arbiter comprises first arbiters that select one of the other devices being determined a second priority in predetermined order, the second priority being one of the first priorities, second arbiters that select one of the other devices selected by the first arbiters in accordance with the first priorities except for the second priority, the second arbiters output an end signal to a target channel unit, the end signal indicating that the direct memory access transfer of data in the data transfer processor finishes, and the target channel unit stops a demand of performing the direct memory access transfer instruction until the target channel unit receives the end signal.