Patent ID: 8271916

Claim:
A method of computing a logic cell library for use by a mapping or synthesis tool, said library composed of complex functions and simple functions, said computing method comprising the steps of: storing, on a computer, a sample of circuit representations of Boolean logic functions from at least one portion of one or more integrated circuit designs, the circuit representations containing at least a plurality of sets of interconnected circuit representations, wherein each of set of interconnected circuit representations includes interconnected Boolean logic functions that contain recurring Boolean logic chains therein; using the computer to automatically identify logic function patterns within the sample, the logic function patterns including at least some of the recurring Boolean logic chains, wherein the step of identifying logic patterns further identifies a design pattern bias; using the computer to determine a set of complex functions that each occur more than a predetermined minimum number of times in the sample, wherein the set of complex functions includes a plurality of non-standard complex Boolean logic functions that are each derived from the identified logic function patterns of the recurring Boolean logic chains, wherein the step of determining the set of complex functions considers the design pattern bias in determining the set of complex functions, and wherein substantially all of the plurality of non-standard complex Boolean logic functions each have at least three inputs; and using the computer to determine a set of simple logic functions, wherein the set of simple logic functions, together with the set of complex functions, completely specify the sample and thus define the logic cell library.