Patent ID: 7688670

Claim:
A semiconductor device comprising: a first memory array selected by a first control signal and including a plurality of first memory cells and a plurality of first sense amplifiers; a second memory array selected by a second control signal which is different from said first control signal and including a plurality of second memory cells and a plurality of second sense amplifiers; first power supply lines extending in a first direction and provided above said first memory array; second power supply lines extending a second direction crossing the first direction and provided above said first memory array; third power supply lines extending in the first direction and provided above said second memory arrays; fourth power supply lines extending in the second direction and provided above said second memory arrays; a first power supply circuit having a first output node connected to one of said first supply lines, receiving a first voltage, and generating a second voltage; and a second power supply circuit having a second output node connected to said one of said second power supply lines, and receiving said first voltage, and generating said second voltage; wherein said first and second power lines are connected to each other at the intersections of said first and second power lines, wherein said third and fourth power lines are connected to each other at the intersections of said third and fourth power lines, wherein, during a first period in which said first memory array is selected, said first power supply circuit outputs said second voltage from said first output node, wherein, during a second period in which the second memory array is selected after said first memory array is selected, said first power supply circuit does not output said second voltage to said first output node.