Patent ID: 8380943

Claim:
A memory module comprising: a plurality of memory devices; and a memory buffer including: a primary data port that supports a variable number of data signal links; a plurality of secondary data ports coupled respectively by point-to-point links to the memory devices, each secondary data port coupled to a fixed number of data signal lines; and a secondary configuration memory for storing a value indicating the number of secondary data ports coupled by point-to-point links to the memory devices; and a data translator that routes data between the primary data port and a number of the secondary data ports that varies in accordance with the value indicating the number of secondary data ports stored in the secondary configuration memory and as a function of the number of data signal links available to the memory module for transmitting data through the primary data port; wherein a first subset of secondary data ports is associated with the value stored in the secondary configuration memory when the primary data port supports a first number of signal links and a second subset of secondary data ports is associated with the value stored in the secondary configuration memory when the primary data port supports a second number of signal links, and the second subset is different from the first subset.