Patent ID: 8373953

Claim:
A semiconductor device comprising: a plurality of bumps arranged on a surface of a semiconductor device; a plurality of electrostatic discharge (ESD) protection cells, wherein individual ESD protection cells couple to and are downstream of individual bumps, the plurality of ESD protection cells are co-located in groups to form at least one ESD cluster located within an interior region of a major side of the semiconductor device, the interior region away from a perimeter of the major side of the semiconductor device, the ESD clusters autarchically located with respect to the bumps, analog functional modules, and the perimeter of the major side of the semiconductor device; a plurality of analog functional modules wherein the analog functional modules couple to and are downstream of individual ESD protection cells, the ESD protection cells operable to protect circuits within the analog functional modules from ESD; and the ESD protection cells are placed proximate to communicatively coupled bumps and analog functional modules; a first power supply bus and a second power supply bus; the plurality of ESD protection cells are coupled to the first and second power supply buses; and a rail clamp coupled between the first and second power supply buses, the rail clamp provides an ESD discharge path between the first and second power supply buses.