Patent ID: 7071048

Claim:
A method of forming a semiconductor device, the method comprising: forming a fin active region by selectively etching a region of a substrate; forming a conformal liner layer on the substrate; forming an insulation layer on the liner layer to fill the etched region of the substrate; planarizing the insulation layer and the liner layer until a top surface of the fin active region is exposed to form a preliminary liner and device isolation layer sequentially stacked on a sidewall of the fin active region; forming a capping insulation layer on the top surface of the fin active region; selectively recessing the preliminary liner to form a liner on a portion of the sidewall of the fin active region for exposing an upper portion of the sidewall of the fin active region; forming a gate insulation layer on at least the exposed surface of the fin active region; and forming a gate electrode crossing over the fin active region, wherein the capping insulation layer is formed to a thickness thicker than a thickness of the gate insulation layer.