Patent ID: 7185135

Claim:
A circuit independent from a host for interfacing between a Peripheral Component Interconnect (PCI) target and a Universal Serial Bus (USB) host port of the host, said circuit comprising: an on-board processor configured to manage data flow and process data; a memory configured to store instructions and data, a portion of said memory detachably coupled to the circuit; a memory controller configured to measure time between accesses to the detachably coupled portion of the memory and to power down said portion when the measured time reaches a predetermined amount; firmware configured to translate signals between USB and PCI protocols; a PCI interface having the PCI target coupled thereto, the PCI target including a PCI-to-ATA translation unit and an Advanced Technology Attachment (ATA) interface connected to an ATA mass storage device that is configured to communicate with the circuit over the ATA interface, through the PCI target and over the PCI interface; the firmware configured to communicate with the coupled PCI target to identify a PCI-to-ATA translation function provided by the coupled PCI target; the firmware configured to send USB device descriptors to the host in response to identifying the PCI-to-ATA translation function provided by the coupled PCI target, the USB device descriptors indicating a mass storage function for the ATA mass storage device; and a USB interface for connecting to the USB host port; wherein the PCI target communicates with the host through the USB host port; wherein the USB device descriptors are configured to elicit installation of a mass storage class driver by the host.