Patent ID: 7368968

Claim:
An integrated circuit comprising: a signal offset cancellation circuit; a switching circuit having an output coupled to an input of the signal offset cancellation circuit; a first transistor having a first current-carrying terminal, a second current-carrying terminal, and a first signal terminal, wherein the first current-carrying terminal is coupled to an input of the switching circuit; a second transistor having a third current-carrying terminal, a fourth current carrying terminal, and a second signal terminal, wherein the third current-carrying terminal is coupled to another input of the switching circuit, wherein an output of the signal offset cancellation circuit is selectably coupled to either the first current-carrying terminal or the third current-carrying terminal through the switching circuit; signal select logic that controls the switching circuit and receives N control bits as input; and offset signal control logic that controls the signal offset cancellation circuit and receives a subset of the N control bits as input.