Patent ID: 8502314

Claim:
A semiconductor device comprising: a substrate; a first device surface overlying the substrate, the first device surface including at least three pads, wherein the at least three pads include: a drain pad; a gate pad; and a source pad; a plurality of trenched gate structures coupled to the gate pad, the plurality of trenched gate structures configured to control a flow of electrical current between the source pad and the drain pad when a voltage is applied to the gate pad; a first conductive layer including: a drain contact, the drain contact coupled to the drain pad; a gate runner, the gate runner coupled to the gate pad; and a source contact coupled between the source pad and the plurality of trenched gate structures; and a second conductive layer, at least a portion of the second conductive layer separated from at least a portion of the first conductive layer using a dielectric, wherein the second conductive layer includes a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner, wherein the drain conductor is coupled to the drain contact.