Patent ID: 7514738

Claim:
A memory cell, comprising: a semiconductor substrate having a doped surface layer; a gate insulation film formed on the doped surface layer of the semiconductor substrate; a gate electrode formed on the gate insulation film; a channel area disposed in the doped surface layer of the semiconductor substrate below the gate electrode; a pair of variable resistance areas formed on mutually opposite sides of the channel area in the doped surface layer, doped at a lower concentration than that of the channel area, the doping concentration in the variable resistance areas being at most five hundred quadrillion carriers per cubic centimeter (5×10 17 cm− 3 ); a pair of highly doped areas disposed on mutually opposite sides of the pair of variable resistance areas, and having a conductive type which is opposite to that of the channel area; and a pair of charge storage bodies disposed above the pair of variable resistance areas on mutually opposite sides of the gate electrode for storing charge, wherein the pair of variable resistance areas is doped with both p-type and n-type impurities, the n-type impurity having a concentration which is higher than that of the p-type impurity throughout the pair of variable resistance areas.