Patent ID: 7545175

Claim:
Output buffer for an integrated circuit, comprising: a PMOS transistor having a source coupled to an operating voltage; an NMOS transistor serially coupled between a drain of the PMOS transistor and a complementary operating voltage; a first driver coupled to a gate of the PMOS transistor for selectively turning on or off the same, wherein the first driver comprises first and second current paths coupled to the gate of the PMOS transistor for selectively pulling down a voltage thereat; a second driver coupled to a gate of the NMOS transistor for selectively turning on or off the same; and a decoder coupled to the first and second drivers for controlling the first driver or the second driver to turn on the PMOS transistor or the NMOS transistor at a high rate or a low rate in response to a slew rate control signal indicating a slew rate control mode or a non-slew rate control mode, and wherein the first driver comprises a switch device, which opens in response to the slew rate control signal indicating the slew rate control mode, for preventing the second current path from pulling down the voltage at the gate of the PMOS transistor, and closes in response to the slew rate control signal indicating the non-slew rate control mode, for allowing the second current path to pull up the voltage at the gate of the PMOS transistor.