Patent ID: 8415743

Claim:
A structure, comprising: a functional region in a semiconductor substrate having a first type of conductivity and a top surface, the functional region connected to a contact for applying a bias potential to the functional region; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer; a first transistor device disposed upon the semiconductor layer and a second transistor device disposed upon the semiconductor layer, each transistor device comprising a source, a drain and a gate stack defining a channel between the source and the drain, where the first transistor device and the second transistor device have the same type of conductivity; a first back gate region adjacent to the top surface of the functional region and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface of the functional region and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity, where the first back gate region is electrically floating and is biased by leakage and capacitive coupling to the functional region, and the second back gate region is directly connected to the functional region.