Patent ID: 7132871

Claim:
A data retaining circuit, comprising a data retaining section that takes in and retains input data in synchronization with a clock and puts out the retained data, a first correcting circuit that takes in and retains input data as a pull-up control signal in synchronization with the clock and pulls up the data retained in the data retaining section when the pull-up control signal is one of the values, and a second correcting circuit that takes in and retains input data as a pull-down control signal in synchronization with the clock and pulls down the data retained in the data retaining section when the pull-down control signal is the other value, wherein the first correcting circuit is configured so that an error in which the pull-up control signal changes from the other value to the one of the values does not occur, the second correcting circuit is configured so that an error in which the pull-down control signal changes from the one of the values to the other value does not occur, an error changing the pull-up control signal from the one of the values to the other value does not change the pull-down control signal retained in the second correcting circuit and the data retained in the data retaining section, and an error changing the pull-down control signal from the other value to the one of the values does not change the pull-up control signal retained in the first correcting circuit and the data retained in the data retaining section.