Patent ID: 7275232

Claim:
A method of producing information for specifying a configuration of a structured ASIC that will be functionally equivalent to a programmed FPGA performing a user's logic design, the structured ASIC including multiple identical instances of a mask-programmable module for use in implementing at least part of the user's logic design, the FPGA including multiple identical instances of a field-programmable module for use in implementing at least said part of the user's logic design, and each of the field-programmable modules having maximum logic capability that is greater than a maximum logic capability of one of the mask-programmable modules, the method comprising: synthesizing the user's logic design to produce a netlist that is suitable for implementing the user's logic design in the FPGA without specifying full place and route information for the FPGA implementation, the netlist including a synthesis of each of multiple portions of the user's logic design for implementation by a respective one instance of the field-programmable module; converting the netlist that results from the synthesizing to a modified netlist that is suitable for structured ASIC implementation of the user's logic design, the modified netlist including a conversion of the netlist for each of said portions of the user's logic design for implementation by a respective number of instances of the mask-programmable module, which number is different for at least some different ones of said portions of the user's logic design; performing a place and route operation on the modified netlist to produce a further synthesis adapted for placement on the structured ASIC; and further converting the further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC.