Patent ID: 6990002

Claim:
A semiconductor device comprising: a plurality of first and second word lines; a first bit line pair including a first bit line and a second bit line; a second bit line pair including a third bit line and a fourth bit line; a plurality of first DRAM memory cells provided at an intersection of said first word lines and said first bit line; a plurality of second DRAM memory cells provided at an intersection of said second word lines and said second bit line; a first MOSFET having a source and drain path coupled to said first bit line and said third bit line; a second MOSFET having a source and drain path coupled to said second bit line and said fourth bit line; a sense amplifier coupled to said third and fourth bit lines; a first control line coupled to a gate of said first MOSFET; and a second control line coupled to a gate of said second MOSFET, wherein during a rewriting operation one of said first and second MOSFETs is in on-state and the other of said first and second MOSFETs is in off-state.