Patent ID: 7075837

Claim:
A redundancy relieving circuit comprising: an array selection circuit; an address decode circuit; and a bit line selection circuit, wherein said array selection circuit comprises first and second inverters, first and second transistors, a plurality of redundancy relieving fuses and cutoff fuses, wherein the first and second transistors include one main electrodes and the other main electrodes respectively connected to one another, any of said one main electrodes being connected to a power supply terminal, wherein each of the first inverters includes an input terminal connected to the other main electrode of the second transistor and an output terminal connected to a control electrode of the second transistor, wherein each of the second inverters includes an input terminal connected to a control electrode of the first transistor and an output terminal connected to the other main electrode of the first transistor, wherein the plurality of redundancy relieving fuses are disposed in series between the output terminals of the second inverters and the other main electrodes of the first transistors respectively, wherein each of the cutoff fuses is disposed between the output terminal of the second inverter and the other main electrode of the first transistor and in parallel with the redundancy relieving fuses, wherein said address decode circuit has address decoders, and wherein said address decode circuit selectively outputs signals sent from the address decoders to said bit line selection circuit in response to potentials among the redundancy relieving fuses in said array selection circuit.