Patent ID: 8582705

Claim:
A serializer/deserializer (SERDES) circuit, comprising: input/output ports utilizing SERDES Framer Interface Level 5 (SFI 5); a clock and data recovery circuit configured to recover a clock from a Return-to-Zero input; and a clock multiplier unit configured to receive the clock and to provide the clock at a multiplied rate, wherein the clock and data recovery circuit and the clock multiplier unit are communicatively coupled to the input/output ports; wherein the input/output ports, the clock and data recovery circuit, and the clock multiplier unit are configured to provide a standard SFI-5 and an overclocked SFI-5 based on the multiplied rate, and wherein the overclocking is based on an amount of forward error correction; wherein the input/output ports, the clock and data recovery circuit, and the clock multiplier unit are configured to provide rates comprising an SFI-5 rate of 39.813 Gb/s with 16 data lanes at 2.48832 Gb/s each, an SFI-5 rate of 40.00 Gb/s with 16 data lanes at 2.500 Gb/s each, an SFI-5 rate of 43.0184 Gb/s with 16 data lanes at 2.6887 Gb/s each, an SFI-5 rate of 44.5709 Gb/s with 16 data lanes at 2.7857 Gb/s each, an overclocked SFI-5 rate of 53.5461 Gb/s with 16 data lanes at 3.347 Gb/s each, and an overclocked SFI-5 rate of 56.1899 Gb/s with 16 data lanes at 3.512 Gb/s each.