Patent ID: 7457171

Claim:
A memory device comprising: data terminals configured to apply data of a data word; a memory cell array including memory cells to store data of a data word; a data generator circuit configured to receive respective data of two successive data words, the two successive data words including a first data word including bits and a second data word including bits that are fed to the data generator circuit from the memory cell array, and to generate data of a third data word including bits and transmit the data of the third data word to the data terminals, wherein the data generator circuit is further configured to operate in one of a first operating mode where the bits of the generated third data word are non-inverted and correspond with the bits of the second data word and a second operating mode where the bits of the generated third data word are inverted with respect to the bits of the second data word, and the data generator circuit is configured to compare the bits of the first data word with the bits of the second data word and to change from one of the first and second operating modes to the other of the first and second operating modes in response to the comparison establishing that more than half of the bits of the first data word differ from the bits of the second data word; and a control terminal to apply a control signal, wherein the data generator circuit is configured to generate the control signal at the control terminal in a first state during operation in the first operating mode and to generate the control signal at the control terminal in a second state during operation in the second operating mode.