Patent ID: 7647538

Claim:
A test apparatus that tests a device under test, comprising: a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test; an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified; an instruction cache that caches the test instruction stream read from the pattern memory; a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache; a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction; and a signal output section that generates a test signal based on the test pattern and supplies the generated test signal to the device under test, wherein the pattern generating section repeatedly executes an instruction stream within the repeated interval in the test instruction stream when the repeated interval is stored on the interval register.