Patent ID: 7251799

Claim:
A method for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout, comprising: reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width, said conductive lines being separated by dielectric material; dividing the given level of metallization in the interconnect structure layout into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level; increasing the prescribed width in the lateral direction of each line in the first and second levels of metallization by a factor of at least two; and arranging the layout of lines in the second level of metallization so that they partially overlap in the vertical direction one of the lines in the first level of metallization.