Patent ID: 7058678

Claim:
A pipelined circuit apparatus for performing operations on a first binary number and a second binary number, comprising: a first arithmetic logic unit (ALU) operating on a first lower portion of the first binary number and a second lower portion of the second binary number to produce a first result and a carry out signal; a second ALU operating on a first upper portion of the first binary number and a second upper portion of the second binary number to produce a second result; and a logic circuit selecting one of the first upper portion and the second upper portion in response to the first flag bit and the second flag bit, the selected upper portion used as the second result; wherein at least one stage in the pipelined circuit stalls by one or more clock cycles in response to the carry out signal to account for additional delay introduced by incrementing the second result when the carry out signal indicates a carry; wherein the first binary number is associated with a first flag bit, the first flag bit indicating a first predetermined number of most significant bits of the first binary number are all zero; and wherein the second binary number is associated with a second flag bit, the second flag bit indicating a second predetermined number of most significant bits of the second binary number are all zero.