Patent ID: 7948791

Claim:
A memory array having a plurality of memory cells, each memory cell comprising: a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a second inverter having a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the first node being coupled to control terminals of the third transistor and the fourth transistor and the second node being coupled to control the first transistor and the second transistor; a fifth transistor coupled between a bit line and the first node, the fifth transistor being controlled by a word line; and a sixth transistor coupled between an inverted bit line and the second node, the sixth transistor being controlled by the word line; wherein the third transistor is implemented with physical dimensions which make the third transistor stronger than the first transistor, or the second transistor is implemented with physical dimensions which make the second transistor stronger than the fourth transistor.