Patent ID: 6974988

Claim:
A DRAM cell structure capable of high integration, comprising: a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate; and a transistor formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor, said transistor including, a storage node contact plug stacked over the trench-type capacitor; a source formed by being diffused into a p-well region of the silicon substrate of the trench sidewall; a poly connector stacked over the storage node contact plug, the poly connector connecting the plug and the source; a nitride film or an oxide film stacked over the poly connector to thereby isolate a gate electrode and the poly connector; a gate electrode stacked over the film, the gate electrode being connected to a word-line; a gate isolation film deposited on the silicon substrate of the trench sidewall adjacent to the gate electrode; a drain formed through an implanting process between gate electrodes, the drain being connected to a bit-line.