Patent ID: 7467304

Claim:
A host apparatus comprising: a host processor; and a memory module, comprising: a memory to maintain a host-executable code to be executed by said host processor; and a security module comprising logic to authenticate said host-executable code and to selectively allow said host processor to access said host-executable code based on an authenticity of said host-executable code; wherein said host-executable code is divided into at least two parts, wherein said security module is adapted to verify the authenticity of said host-executable code, wherein said host processor is adapted to execute the code of a first part of said at least two parts while the portion of said memory that is used to store said first part of host-executable code is protected by said security module from having its contents modified by said host processor at least during the period at which said security module verifies said first part of host-executable code, wherein said verification is performable during a time period that is at least partially overlapping the time period at which said host processor executes said first part of said host executable code; and wherein said code in said first part includes one or more instructions that disable said host processor from executing code of other parts in said memory but the said first part until said security module signals that all said host-executable code is authentic.