Patent ID: 8181064

Claim:
An information processing apparatus comprising a first system board including a first arithmetic processor and a second arithmetic processor that simultaneously execute same processing, a first control device connected to the first and the second arithmetic processors and also connected to a storing device, a second system board including a second control device, and a relay device that relays the first and the second system boards, the first system board comprising: an instruction inputting unit that inputs an instruction which is issued from any one of the first and the second arithmetic processors to the second system board via the relay device; a detecting unit that detects a break of a synchronization between the first arithmetic processor and the second arithmetic processor by detecting abnormality occurrence in any one of the first and the second arithmetic processors; an instruction issue stopping unit that instructs the instruction inputting unit to stop the issuance of an instruction from the first or second arithmetic processor as an abnormal arithmetic processor in which the abnormality is detected; an instruction inhibiting unit that inhibits an instruction input from the second control device to the first control device by continuing to input a retry packet to the second control device via the relay device; a saving unit that saves internal information held by either of the first arithmetic processor or the second arithmetic processor as a normal arithmetic processor that is in a normal condition into the storing device when the abnormality is detected in one of the first or second arithmetic processors; an initializing unit that initializes both of the first and the second arithmetic processors; a restoring unit that restores the internal information of the normal arithmetic processor saved in the storing device to both of the initialized first and second arithmetic processors; and an instruction inhibition canceling unit that cancels the inhibition of the instruction issued from the second control device to the first control device and that resumes synchronous operation of the first and second arithmetic processors, when the internal information is restored to both the first and second arithmetic processors.