Patent ID: 8031502

Claim:
A content addressable memory device comprising: rows of first matchlines precharged to a voltage level corresponding to a miss condition; ternary cells connected in parallel to each of the first matchlines; rows of second matchlines precharged to the voltage level corresponding to the miss condition; binary cells connected in parallel to each of the second matchlines, the binary cells being smaller in size than the ternary cells and operable simultaneously with the ternary cells; searchlines connected to the ternary cells of the rows of first matchlines and to the binary cells of the rows of second matchlines; a first plurality of matchline sense amplifiers connected to the rows of first matchlines for detecting one of a first miss condition or a first match condition in response to search data on the searchlines, each of the first plurality of matchline sense amplifiers providing a match output if data stored in the ternary cells of each row matches the search data, each of the first plurality of matchline sense amplifiers being maskable to search the binary cells connected to the second matchlines; and a second plurality of matchline sense amplifiers connected to the rows of second matchlines for detecting one of a second miss condition or a second match in response to search data on the searchlines, each of the second plurality of matchline sense amplifiers providing a match output if data stored in the binary cells of each row matches the search data, each of the second plurality of matchline sense amplifiers being maskable to search the ternary cells connected to the first matchlines.