Patent ID: 8912993

Claim:
A scan driving device including a plurality of scan driving blocks that are sequentially arranged, wherein the scan driving blocks respectively include: a first node configured to receive a second power source voltage according to a clock signal that is input to a first clock signal input terminal; a second node configured to receive a first power source voltage according to the clock signal that is input to the first clock signal input terminal, and to receive an input signal according to a clock signal that is input to a second clock signal input terminal; a first transistor including a gate electrode that is connected to the first node, a first electrode that is connected to the first power source voltage, and a second electrode that is connected to an output terminal; and a second transistor including a gate electrode that is connected to the second node, a first electrode for receiving a clock signal that is input to a third clock signal input terminal, and a second electrode that is connected to the output terminal, wherein, during an initial driving period, the input signal is applied with a gate off voltage, and the clock signal that is input to the first clock signal input terminal, the clock signal that is input to the second clock signal input terminal, and the clock signal that is input to the third clock signal input terminal have are applied with a gate on voltage to reset a voltage at the first node with the gate on voltage and reset a voltage at the second node with the gate off voltage, and wherein the scan driving blocks output scan signals with a gate off voltage when a voltage at the first node is reset with a gate on voltage and a voltage at the second node is reset with a gate off voltage.