Patent ID: 7071060

Claim:
A method of forming a memory structure on a substrate, comprising: forming source and drain regions in a surface of said substrate with a first conductivity type, thereby to form a memory cell channel therebetween, forming a first electron storage element over a first region of the channel adjacent the source region, forming a second electron storage element over a second region of the channel adjacent the drain region, said first and second electron storage elements being formed with a space between them over a third region of the channel positioned in between the first and second regions of the channel, forming a first control gate over the first electron storage element, forming a second control gate over the second electron storage element, forming a third control gate over the first and second control gates with a layer of dielectric therebetween and extending downward between the first and second control gates over the third region of the channel and adjacent at least edges of the first and second electron storage elements with tunneling dielectric layers therebetween, and doping the first and second regions of the channel with a first level of a second conductivity type, and doping the third region of the channel with a second level of the second conductivity type, the second level of doping being higher than the first level of doping.