Patent ID: 7594144

Claim:
A method of handling fatal computer hardware errors, the computer comprising: chips of a chipset, the chips of the chipset comprising principal integrated circuit components of a computer including one or more processors, one or more memory modules, and one or more bus adapters, the chips of the chipset communicatively connected through one or more in-band buses, the computer further comprising a programmable logic device communicatively coupled through at least one sideband bus to chips of the chipset and to an embedded system microcontroller, the method comprising: detecting, by a source chip of the chipset that is connected to an in-band bus that supports messaged interrupts, the occurrence of the fatal hardware error, including detecting a sync flood on the in-band bus; halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by the source chip of the chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to the embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.