Patent ID: 7383472

Claim:
A disk array subsystem having a storage device and a controller, wherein said controller has a cache memory unit, a plurality of host interface units, a plurality of disk interface units, and a switching unit for connecting the cache memory unit, the host interface units, and the disk interface units; and said cache memory unit has a memory device for storing data, and a memory control circuit that controls said memory device, wherein said memory control unit has a memory command output unit, a monitoring unit, an ECC error detection/correction unit, and an error status storage register, the monitoring unit: monitors a memory access state of the memory device based on memory access commands, determines timing to make a diagnosis access to the memory device based upon said monitored memory access state, and outputs a diagnosis request memory to the command output unit with the timing to make a diagnosis access, determines a non-access time of the memory device when there is no normal data access from the host interface units and the disk interface units thereinto, determines the timing to make a diagnosis access also as a time point when a previous diagnosis access to said the memory device has elapsed for a fixed period of time, or as a time point when a ratio of access time or frequency reaches or exceeds a predetermined value, said ratio is a ratio of a normal memory access time to a non-memory access time during a past time period, or a ratio of the non-memory access time to a total time during the past time period, or a ratio of a normal memory access frequency to a non-memory access frequency during a past time period the past time period, or a ratio of the non-memory access frequency to a total access frequency the past time period, and checks whether any data failure has occurred only during said non-access time of the memory device by having the memory command output unit issue a command/address of the data read to the memory device and checking the read data for responding thereto using the ECC error detection/correction unit, the ECC error detection/correction unit obtains an error status when an error is detected by checking the read data from the memory device, if said detected error is correctable, the data is corrected and the corrected data is rewritten to the memory device, and the error status storage register stores said error status received form the ECC error detection/correction unit.