Patent ID: 8810269

Claim:
A semiconductor structure, comprising: an interposer that includes routing circuitry, the routing circuitry including a plurality of signal line segments in one or more routing layers of the semiconductor structure; a plurality of micro-bump contacts disposed on a surface of the interposer and coupled to the routing circuitry; wherein each line segment of the plurality of signal line segments connects a pair of the plurality of micro-bump contacts, respectively; and a plurality of test circuits stacked on the interposer, each test circuit coupled to a subset of the plurality of signal line segments via a respective subset of the micro-bump contacts, each test circuit configured to: switchably connect a first pair of micro-bump contacts in the respective subset of micro-bump contacts to at least a second pair of micro-bump contacts in the respective subset of micro-bump contacts to form a first set of daisy chains of the subset of signal line segments and dynamically connect a third pair of micro-bump contacts in the respective subset of micro-bump contacts to at least a fourth pair of micro-bump contacts in the respective subset of micro-bump contacts to form a second set of daisy chains of the subset of signal line segments; test for short circuits between the first set of daisy chains and the second set of daisy chains; test the first and second sets of daisy chains for open circuits; in response to detecting an open circuit in a daisy chain, determine a portion of the daisy chain in which the open circuit is located; and in response to detecting a short circuit between the first set of daisy chains and the second set of daisy chains, determine a location at which the first set of daisy chains is short circuited to the second set of daisy chains.