Patent ID: 7808295

Claim:
A multiphase level shift system for performing voltage conversion with respect to output voltages of n clock signals (n is an integer of three or more) having equal cycles, an interval between phases thereof being a phase amount T (T=360°/n), comprising: n level shifters in a one-to-one correspondence with the n clock signals, wherein each of the n level shifters includes a first NMOS transistor and a first PMOS transistor, the first NMOS transistor included in each of the n level shifters is connected between an output node for outputting an output signal of said level shifter and a ground node, and a gate of the first NMOS transistor receives the clock signal corresponding to said level shifter, the first PMOS transistor included in each of the n level shifters is connected between the output node and a power supply node, and a gate of the first PMOS transistor receives an output signal from another level shifter different from said level shifter, the output signal given to the gate of the first PMOS transistor included in each of the n level shifters is an output signal of the level shifter which receives the clock signal delayed by a phase amount X (0°<X<180°) from the clock signal given to the gate of the first NMOS transistor included in said level shifter, and the phase amounts X of the n level shifters are equal to each other.