Patent ID: 8018779

Claim:
A semiconductor storage device comprising: a reference voltage circuit that supplies a reference voltage; a first memory circuit connected to a first word line; and a second memory circuit connected to a second word line, that performs a read/write operation when any one of the first memory circuit and the second memory circuit is selected, wherein the first memory circuit and the second memory circuit each comprise: a plurality of memory cells; a plurality of bit line pairs for reading data stored in the plurality of memory cells; a precharge circuit that connects the reference voltage circuit and the plurality of bit lines to precharge the plurality of bit line pairs; a sense amplifier circuit that amplifies, when making a selection, potential differences among the plurality of bit line pairs; and a pull-down circuit that lowers any one of the plurality of bit line pairs to a pull-down voltage, which is lower than the reference voltage, for a read/write operation period during which the first memory circuit is selected and the second memory circuit is non-selected, the pull-down circuit of the second memory circuit lowers the bit line pair to the pull-down voltage, and for a precharge period after the read/write operation period, the precharge circuits of the first memory circuit and the second memory circuit connect the plurality of bit line pairs to the reference voltage circuit respectively.