Patent ID: 7508806

Claim:
A system for performing a system function, comprising: a configuration processor block that is arranged for configuring two or more processing blocks; a first processing block for performing a first signal processing function that is configured by the configuration processor block, wherein the first processing block comprises a first wired logic block, a first programmable processor block configured by the configuration processor block to change an algorithm for the first signal processing function, a first memory for control accesses, a second memory for data accesses, and a first instruction set, all optimized for performing the first signal processing function by the first processing block, wherein the first instruction set includes an instruction word for directing the first programmable processor block to simultaneously execute differing operations upon differing operands related to performing the first signal processing function; a second processing block that is separate from the first processing block, wherein the second processing block is arranged for performing a second signal processing function that is different from the first signal processing function that is configured by the configuration processor block, wherein the second processing block comprises a second wired logic block, a second programmable processor block configured by the configuration processor block to change the algorithm for the second signal processing function, a third memory for control accesses, a fourth memory for data accesses, and a second instruction set, all optimized for performing the second signal processing function, and wherein the second instruction set is different from the first instruction set; and a third processing block for performing a third signal processing function that is different from the first and second signal processing function, wherein the third processing block comprises a codec communication signal processor engine that is configured to perform an error correction signal processing algorithm wherein the codec communication signal processor engine comprises a third instruction set that is optimized for the error correction signal processing algorithm and includes a common set of instruction words, and further includes an additional set of instructions words that are specialized for the associated communication signal processor engine.