Patent ID: 7863693

Claim:
A semiconductor device, comprising: a gate region; at least one source/drain region; at least one source/drain extension region situated between said gate region and said source/drain region; a conductive stud contacting said source/drain region; a protective layer formed on top of said at least one source/drain extension region at substantially close to sidewalls of said gate region with said gate region not being covered by said protective layer, said protective layer having a height less than a height of said sidewalls of said gate region, wherein said heights of said protective layer and said sidewalls of said gate region are measured in a same direction; and a dielectric stress liner situated between said protective layer and said source/drain extension region, wherein said conductive stud is not in contact with said source/drain extension region through separation by at least a portion of said protective layer applied on top of said source/drain extension region; said protective layer is an oxide layer; and said dielectric stress liner is a nitride compressive liner or a nitride tensile liner.