Patent ID: 7478301

Claim:
An integrated circuit, comprising: a multiplicity of macro-circuits, each macro-circuit of said multiplicity of macro-circuits being a logic circuit having the same function, each macro-circuit of said multiplicity of macro-circuits being identical; one or more repairable circuits; a fuse bank containing a multiplicity of fuses partitioned into a first set of fuses and a second set of fuses, states of fuses of said first set of fuses storing test data indicating at least which macro-circuits of said multiplicity of macro-circuits failed a first test, states of fuses of said second set of fuses storing test data indicating which repairable circuits of said one or more repairable circuits failed a second test; a scan multiplexer and control circuit connected to scan-in I/O pads and scan-out I/O pads and connected to each of said macro-circuits, said scan multiplexer and control circuit including means for selectively connecting said scan-in I/O pads and scan-out I/O pads to and disconnecting said scan-in I/O pads and scan-out I/O pads from each of said macro-circuits of said multiplicity of macro-circuits during testing of said multiplicity of macro-circuits; means for isolating each macro-circuit of said multiplicity of macro-circuits from any other logic circuits of said integrated circuit chip and means for connecting scan-in and scan-out pins dedicated to each macro-circuit of said multiplicity of macro-circuits to respective pads of said scan-in I/O pads and scan-out I/O pads; means for permanently preventing utilization of those macro-circuits during operation of said integrated circuit that did not pass said test during operation of said integrated circuit, said means for permanently preventing responsive to said state of fuses in said fuse bank; and means to replace failing circuit portions of said repairable circuits with redundant good circuit portions based on a state of fuses of said second set of fuses.