Patent ID: 8363505

Claim:
A memory circuit apparatus, comprising: a plurality of word line drivers electrically connected to a plurality of word lines on a memory integrated circuit, the plurality of word line drivers receiving a first word line selection signal and a second word line selection signal, the first word line selection signal and the second word line selection signal together selecting a word line from the plurality of word lines, a word line driver of the plurality of word line drivers comprising: a depletion mode p-type transistor having: a gate receiving the second word line selection signal; a first current carrying terminal receiving the first word line selection signal; and a second current carrying terminal electrically connected to an output terminal; a n-type transistor having: a gate electrically connected to the gate of the p-type transistor and receiving the second word line selection signal; a first current carrying terminal; and a second current carrying terminal electrically connected to the output terminal; and the output terminal electrically connected to the second current carrying terminal of the p-type transistor and the second current carrying terminal of the n-type transistor, the output terminal driving a corresponding word line of the plurality of word lines; and control circuitry applying bias arrangements to the plurality of word line drivers, including a first bias arrangement applying a nonpositive voltage as the second word line selection signal selecting the word line electrically connected to the word line driver.