Patent ID: 8183918

Claim:
An electronic circuit operable to substantially cancel simultaneously second and third-order nonlinearities thereof, comprising: at least two transistors coupled in parallel; a biasing circuit supplying a first gate-source voltage and a first drain-source voltage to the first transistor and a second gate-source voltage and a second drain-source voltage to the second transistor; wherein the first gate-source voltage and the second gate-source voltage are offset from each other by a gate-source voltage offset; the first drain-source voltage and the second drain-source voltage are offset from each other by a drain-source voltage offset; further wherein the electronic circuit is implemented in a Metal Oxide Semiconductor (MOS), process, wherein threshold voltages of the first and second transistors are a function of a transistor channel length; and further wherein the second transistor channel length is configured such that the threshold voltage of the second transistor is at a peak on a threshold voltages versus channel lengths curve arising from reverse short channel effects for a given semiconductor process.