Patent ID: 7682917

Claim:
A method of forming a semiconductor structure comprising: forming a stack of a gate dielectric and a gate electrode on a semiconductor substrate; forming a disposable gate spacer comprising a metal, a metal nitride, or a germanium containing alloy directly on sidewalls of said gate dielectric and said gate electrode; forming a stressed silicon nitride layer having an intrinsically compressive stress or an intrinsically tensile stress on said disposable gate spacer; transferring stress from said stressed silicon nitride layer into a portion of said semiconductor substrate by performing an anneal while said disposable gate spacer is present on said semiconductor substrate; removing said stressed silicon nitride layer; forming source and drain metal semiconductor alloy regions that are offset from said sidewalls by said disposable gate spacer on said semiconductor substrate; and removing said disposable gate spacer selective to said source and drain metal semiconductor alloy regions and said gate electrode.