Patent ID: 7991104

Claim:
A Gray code counter, comprising: a plurality of Gray code cells serially coupled from a least significant bit to a most significant bit, together forming a Gray code, said Gray code cells all identical, where each said Gray code cells is a Gray code counter bit, each said Gray code cells having a first input, a second input, a first output, and a second output, and where said second output of said Gray code cell is at a logical “1” when said Gray code cell and all previous Gray code cells in less significant positions are all “0”, each of said Gray code cells further comprising: a Toggle Flop having a data input and outputs, said Toggle Flop changing state when a locally gated clock trigger is applied to a clock terminal of said Toggle Flop, where a first output of said Toggle Flop is said first output of said Gray code cell; a control logic receiving its inputs from said first input and said second input of said Gray code cell, said control logic generating said locally gated clock trigger to said clock terminal, said control logic further signaling at said second output of said Gray code cell when to toggle a next more significant bit Gray code cell; and a Counter parity toggle flip-flop to provide counter parity for said Gray code counter, said Counter parity toggle flip-flop changing state with every clock cycle, said Counter parity toggle flip-flop coupled to a third input of said plurality of Gray code cells.