Patent ID: 8877582

Claim:
A method of forming an integrated circuit product comprised of an N-type transistor and a P-type transistor, comprising: forming a gate structure for said N-type transistor above a first active area of a semiconductor substrate, said gate structure of said N-type transistor comprising a gate insulation layer and a gate electrode comprised of a silicon-containing material; forming first sidewall spacer structures adjacent said gate structure of said N-type transistor; forming a gate structure for said P-type transistor above a second active area of said semiconductor substrate, said gate structure of said P-type transistor comprising a gate insulation layer and a gate electrode comprised of a silicon-containing material; forming second sidewall spacer structures adjacent said gate structure of said P-type transistor; forming a masking layer that allows implantation of ions into said gate electrodes of said N- and P-type transistors but not into areas of said first and second active regions where source/drain regions for said N- and P-type transistors will be formed; performing a gate ion implantation process to implant ions into said gate electrodes of both of said N- and P-type transistors to thereby form a gate ion implant regions comprised of said ions in said gate electrode for said N-type transistor and in said gate electrode of said P-type transistor; and after performing said gate ion implantation process, performing an anneal process.