Patent ID: 7439724

Claim:
An on-chip jitter measurement circuit for receiving a reference clock and at least one signal of interest, the circuit comprising: a latch for comparing the arrival time of the at least one signal of interest to the reference clock, wherein the latch comprises an edge-triggered latch; a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, at least one middle stage, and a last stage; a voltage controller in signal communication with the at least on middle stage of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller permits the first and last stages of the delay chain to retain a full voltage swing independent of the delay, and wherein the voltage controller comprises a state machine in signal communication with the ring for controlling the delay of the ring oscillator; a NAND gate in signal communication with the delay chain for converting the delay chain into a ring oscillator to calibrate the delay; a ring oscillator counter in signal communication with the ring oscillator for counting pulses of the ring oscillator to establish the calibration; a reference counter in signal communication with the reference clock for counting pulses of the received reference clock to provide a reference for the established calibration; a latch counter in signal communication with the latch for counting the instances of the reference clock latching the at least one signal of interest; a NAND gate in signal communication with the latch for resetting the input to the latch counter after each reference clock; a clock counter in signal communication with the reference clock for counting the number of reference clocks input to the latch; and a multiplexer in signal communication with the at least one signal of interest for selecting the at least one signal of interest from a plurality of potential signals of interest.