Patent ID: 8462524

Claim:
A circuit arrangement which comprises at least one 3-level pulse width modulation inverter with a snubber circuit and comprises input terminals ( 1 - 3 ) for a positive pole, a negative pole and a centre tap of an input voltage as well as an output terminal ( 4 ), wherein the pulse width modulation inverter comprises at least two outer switching elements (V 1 , V 4 ), which are connected to the input terminals ( 1 , 3 ) for the positive and the negative pole of the input voltage, and two inner switching elements (V 2 , V 3 ), which are connected to the output terminal ( 4 ), wherein the snubber circuit is formed by at least one coil (L), two capacitors (Cu, Co) and a series connection comprising four diodes (Dh 1 -Dh 4 ) poled in the same direction, wherein the two outer (Dh 1 , Dh 4 ) of the four diodes are in each case directly connected to the input terminals ( 1 , 3 ) for the positive and the negative pole of the input voltage, an electrical connection between the two inner (Dh 2 , Dh 3 ) of the four diodes is connected on the one hand via the coil (L) to the input terminal ( 2 ) for the centre tap of the input voltage and on the other hand to a middle bridge branch of the pulse width modulation inverter, and the two capacitors (Cu, Co) are in each case connected with one terminal to, in each case, an electrical connection between one of the inner (Dh 2 , Dh 3 ) and the outer (Dh 1 , Dh 4 ) of the four diodes respectively adjacent in the series connection, and with the other terminal directly or via the two inner switching elements (V 2 , V 3 ) of the pulse width modulation inverter to the output terminal ( 4 ).