Patent ID: 7215005

Claim:
An integrated vertical multiple npn transistor ESD protection structure on a semiconductor substrate, functionally connected between an integrated circuit input or output pin and ground for preventing electrostatic discharge damage to said integrated circuit comprising: a first semiconductor layer having a first conductivity dopant type; a second semiconductor layer overlying said first semiconductor layer, having a similar conductivity type as said first layer, but a different dopant concentration; a third semiconductor layer having a second conductivity dopant type opposite that of said first semiconductor layer, disposed in overlying relation to said second semiconductor layer; a plurality of first regions of said first conductivity type electrically connecting with said first semiconductor layer, having a top element making electrical contact to said first regions and said first semiconductor layer; a plurality of second regions of said second conductivity dopant type laterally spaced from said first regions, being electrically connected to said third semiconductor layer having a top element making electrical contact to said second regions and said second semiconductor layer; and a plurality of third regions of said first semiconductor layer conductivity dopant type laterally spaced and interposed between said second regions, wherein said third regions are altematingly arranged in an array within said third semiconductor layer, wherein, when “N” by definition is the number of said third regions, said third regions are electrically connected by a conductor element with N horizontal stripe conductor elements, at least two of said horizontal stripe conductor elements are connected by at least one first contact conductor element horizontally perpendicular to said horizontal stripe conductor elements at one end of said horizontal stripe conductor elements, and at least two of said horizontal stripe conductor elements are connected by at least one second contact conductor element horizontally perpendicular to said horizontal stripe conductor elements at another end of the horizontal stripe conductor elements, and wherein one of said second regions of said second conductivity dopant type is disposed between said array and a first one of said first regions and, and another of said second regions is disposed between said array and a second one of said first regions, and said first one of said first regions and said second one of said first regions are disposed at laterally opposite ends of said plurality of said first regions.