Patent ID: 8058913

Claim:
A delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from a source signal that is input from external using a voltage controlled delay line including a plurality of dummy cells, comprising: a dithering circuit configured to remove interior noise parasitic to a multiplied clock by switching between the multiplied clock before being changed and the multiplied clock after being changed at least one time even when a multiplication ratio preset by a frequency multiplier is changed, the dithering circuit including: a plurality of change detection blocks configured to detect change of a 2-bit control signal and generate a short pulse when each bit of the 2-bit control signal is changed from 1 to 0 and vice versa; a D flip-flop configured to receive the short pulse at a clock terminal and change an output value into 1 or 0; an AND gate having a first input terminal coupled to an output terminal of the D flip-flop and a second input terminal at which a reference clock signal is received; a counter configured to receive the reference clock signal, continue to operate until a counter value of an MSB address becomes 1, and output a counter value of an LSB address to the external; a multiplexer configured to output a multiplied clock before being changed upon receiving a counter value 1 of the LSB address and output a multiplied clock after being changed upon receiving a counter value 0 of the LSB address; and a rising edge detector configured to, when the counter value of the MSB address is changed from 0 to 1, further generate the short pulse to reset an output value of an output terminal of the D flip-flop and an output value of an output terminal of the counter to 0 simultaneously.