Patent ID: 8154054

Claim:
A semiconductor chip on which a semiconductor integrated circuit is mounted, the semiconductor chip comprising: an internal core region provided at a center portion of the semiconductor chip, and formed with an internal core circuit; a peripheral I/O region provided outside the internal core region, and formed with an interface circuit; and a plurality of external connection pads arranged in three or more rows in a staggered configuration at a peripheral portion of the semiconductor chip, wherein the interface circuit includes a plurality of I/O cells arranged in a first direction in which the external connection pads in any of the three or more rows are arranged, the plurality of external connection pads include: a first external connection pad which is arranged in the outermost row, and used as a power supply pad or a ground pad for the internal core circuit; and a second external connection pad which is arranged in the second outermost row, adjacent to the first external connection pad, and connected to the first external connection pad with a metal in the same layer as a pad metal, the first external connection pad and the second external connection pad fail to overlap in a second direction which is perpendicular to the first direction, and the metal extends in the second direction, the first external connection pad overlaps in the first direction with each of three I/O cells of the plurality of I/O cells and entirely overlaps in the second direction with the plurality of I/O cells, and the second external connection pad overlaps in the first direction with each of three I/O cells of the plurality of I/O cells and entirely overlaps in the second direction with the plurality of I/O cells, and the first I/O cell and the second I/O cell are adjacent to each other in the first direction.