Patent ID: 8670624

Claim:
An information processing apparatus, comprising: a first memory and a second storage memory, the first memory having a smaller capacity and allowing higher speed access than the second memory; a third memory that has a two bank configuration and that allows higher speed access than the second memory; filtering circuitry configured to recursively repeat analysis filter processing, the analysis filter processing being processing in which analysis filtering for decomposing frequency components of image signals into low frequency components and high frequency components is performed in both a horizontal direction and a vertical direction, on horizontal and vertical low frequency component coefficients obtained as a result of the analysis filter processing, until a predetermined decomposition level is reached; first controlling circuitry configured to cause coefficients obtained during a process of computation in the analysis filter processing and, except for a preset decomposition level, horizontal and vertical low frequency component coefficients obtained as a result of the computation in the analysis filter processing to be stored in the first memory independently for each decomposition level, to read the coefficients stored in the first memory, as appropriate, and to supply the read coefficients for the analysis filter processing; and second controlling circuitry configured to cause the horizontal and vertical low frequency component coefficients of the preset decomposition level, the coefficients being obtained as a result of the computation in the analysis filter processing, to be stored in the second memory, to read the coefficients stored in the second memory, as appropriate, and to supply the read coefficients for the analysis filter processing, wherein the second controlling circuitry is configured to write the coefficients, read from the second memory, alternately to memory banks in the third memory, and in parallel with the writing of the coefficients to one of the memory banks, the second controlling circuitry is configured to read the coefficients stored in the other memory bank and to supply the read coefficients for the analysis filter processing.