Patent ID: 8032850

Claim:
A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a first design structure element representing a correction circuit; a second design structure element representing a divider circuit coupled to the correction circuit; and a third design structure element representing a measurement device coupled to the divider circuit, wherein the first, second, and third design structures are operated on by at least one processor of at least one data processing system to generate a representation of an integrated circuit device, and wherein the first, second, and third design structures are configured such that, in the representation of the integrated circuit device: the correction circuit receives the input signal and generates an output signal to the divider circuit based on the input signal, the measurement device determines a setting of the correction circuit at which the divider circuit fails, and the measurement device calculates a duty cycle of the input signal based on the setting of the correction circuit at which the divider circuit fails, wherein the design structure is configured such that the measurement device determines a setting of the correction circuit at which the divider circuit fails by: sending control signals to the correction circuit to cycle through one or more correction settings of the correction circuit; monitoring an output of the divider circuit to determine, for the one or more correction settings of the correction circuit, if the divider circuit fails; and identifying a first setting of the correction circuit at which the output of the divider circuit identifies the divider circuit as having failed.