Patent ID: 7646224

Claim:
A phase/frequency locked loop (PLL) comprising: a first flip-flop having a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock; a second flip-flop having a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock; a first one-shot block adapted to generate a pulse in response to a rising edge of a reference clock, said reference clock being used to generate the feedback clock, said first one-shot block generating an output signal applied to a reset terminal of the first flip-flop; a third flip-flop having a data input terminal responsive to the voltage supply, and a clock terminal responsive to the feedback clock; a fourth flip-flop having a data input terminal responsive to an output of the third flip-flop and a clock terminal responsive to the feedback clock; wherein a reset terminal of the third flip-flop receives the output signal of the first one-shot block; and a fifth flip-flop having a data input terminal responsive to the voltage supply, and a clock terminal responsive to the inverse of feedback clock; a sixth flip-flop having a data input terminal responsive to an output of the fifth flip-flop, and a clock terminal responsive to the inverse of the feedback clock; and a second one-shot block adapted to generate a pulse in response to a falling edge of the reference clock, said second one-shot block generating an output signal applied to a reset terminal of the fifth flip-flop.