Patent ID: 7027333

Claim:
A triple redundant latch for reducing soft errors comprising: a) a first settable memory element; b) a second settable memory element; c) a third settable memory element; d) a first voting structure; e) a second voting structure; f) a third voting structure; g) a first buffer; h) wherein an identical logic value is set in each settable memory element; i) wherein inputs to the first voting structure are provided by the second settable memory element and the third settable memory element; j) wherein inputs to the second voting structure are provided by the first settable memory element and the third settable memory element; k) wherein inputs to the third voting structure are provided by the second settable memory element and the first settable memory element; l) wherein an output of the first voting structure determines a logical value held on the first settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set; m) wherein an output of the second voting structure determines a logical value held on the second settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set; n) wherein an output of the third voting structure determines a logical value held on the third settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set, o) wherein scan data or scanned into the second settable memory element; p) wherein data or scanned out of the second settable memory element into the buffer, q) wherein data or scanned from the buffer into third settable memory element; r) wherein data or scanned out of the third settable memory element; s) wherein a propagation delay through the first settable memory element is the only propagation delay of the triple redundant latch.