Patent ID: 7639766

Claim:
A circuit comprising: an analog to digital converter configured to generate a plurality of samples from a received signal in response to a reference signal; a processor configured to (i) generate third data by delaying first data by one chip period and (ii) generate a timing error signal (a) related to a difference between said first data and said third data and (b) inversely related to second data, (iii) determine a designation of an ideal sample as one of a first sample of said samples and a second sample of said samples in a first condition, said first condition having a) a first timing error between a given sample of said samples and a corresponding transmitted sample and b) said first timing error being greater than one-half a sample period of said received signal, (iv) generate a tracking signal conveying said designation and (v) generate a bias that phase shifts said reference signal to minimize a second timing error between said ideal sample and said corresponding transmitted sample; and a correlator bank configured to i) generate said first data and said second data by correlating a received pseudo-random number code with a local pseudo-random number code and ii) decimate said samples in response to said tracking signal such that said ideal sample alone is used to represent a chip of said received pseudo-random number code.