Patent ID: 7378745

Claim:
A package substrate for a semiconductor device, comprising: a plurality of thermoplastic resin layers that are stacked and bonded together and that each have conductive vias that pass through the layers in a direction of thickness; conductive patterns that are composed of metal layers provided on at least one surface of said thermoplastic resin layers; connection terminals that are exposed on one outermost layer for mounting and electrically connecting an integrated circuit element of a flip-chip connection type; and conductive ball terminals that make up a ball grid array structure and that are exposed on the outermost layer of an opposite side, wherein said package substrate for a semiconductor device has sixteen or more said thermoplastic resin layers, and an overall thickness of said stacked and bonded thermoplastic layers is 0.8 mm-2.0 mm; one or more said vias are provided in each of all said thermoplastic resin layers or in all said thermoplastic resin layers other than the outermost layers; and seventeen or more layers of said conductive patterns are provided.