Patent ID: 7541845

Claim:
A method for detecting a logic state represented by an input signal, comprising: sampling an input signal voltage; generating a reference voltage based on a most recent previously sampled input signal voltage; and determining a logic state represented by a current sample of the input signal voltage based on the generated reference signal; wherein the sampling step includes, sampling an input signal during a high period of a first clock signal to generate a first input signal voltage, and sampling the input signal during a high period of a second clock signal to generate a second input signal voltage, the second clock signal being an inverse of the first clock signal; the generating step includes, generating a first reference voltage based on the second input signal voltage during the high period of the first clock signal, and generating a second reference voltage based on the first input signal voltage during the high period of the second clock signal; and the determining step includes, determining a first logic state represented by the first input signal voltage by comparing the first input signal voltage to the first reference voltage, and determining a second logic state represented by the second input signal voltage by comparing the second input signal voltage to the second reference signal.