Patent ID: 7001812

Claim:
A method of manufacturing a semiconductor device having a high voltage transistor, a low-voltage drive transistor, and an MNOS memory transistor, comprising: forming a first mask layer above a high voltage transistor forming area wherein the high voltage transistor of a semiconductor layer is formed, a low voltage drive transistor area wherein the low voltage drive transistor is formed, and an MNOS memory transistor forming area wherein the MNOS memory transistor is formed, each forming area being of a semiconductor layer; forming a second mask layer above the first mask layer; removing the first mask layer and the second mask layer formed on a first gate insulating layer forming area of the high voltage transistor; forming a first gate insulating layer by a thermal oxidation process on the high voltage transistor forming area using the first mask layer and the second mask layer as a mask; removing the second mask layer formed on the high voltage transistor forming area, the low voltage drive transistor forming area, and the MNOS memory transistor forming area; removing the first mask layer formed on the MNOS memory transistor forming area; forming a multi-layered film, wherein at least a silicon oxide layer and a silicon nitride film are stacked, above the high voltage transistor forming area wherein the high voltage transistor of a semiconductor layer is formed, the low voltage drive transistor area wherein the low voltage drive transistor is formed, and the MNOS memory transistor forming area wherein the MNOS memory transistor is formed, each forming area being of the semiconductor layer; removing the multi-layered film formed on the low voltage drive transistor forming area; removing the first mask layer formed on the low voltage drive transistor forming area; forming a second gate insulating layer on the low voltage drive transistor forming area; forming a gate electrode on the high voltage transistor forming area, the low voltage drive transistor forming area, and the MNOS memory transistor forming area; and forming a source/drain area on the high voltage transistor forming area, the low voltage drive transistor forming area, and the MNOS memory transistor forming area.