Patent ID: 8427206

Claim:
A buffer for providing an impedance transformation for an input signal so as to output an output signal, the buffer comprising: a buffer section, including (i) a first series circuit between a High voltage source and a Low voltage source, which first series circuit is formed by two n-channel transistors connected to each other in series at a connection point, (ii) a second series circuit between the High voltage source and the Low voltage source, which second series circuit is formed by two n-channel transistors connected to each other in series at a connection point, and (iii) a first capacitor between the connection points; and an inverted-signal generating section for generating an inverted signal, the inverted-signal generating section including an n-channel transistor but no p-channel transistor, a fourth transistor and a resistor, and generating the inverted signal, a polarity of which inverted signal is opposite to the input signal and a signal level of which inverted signal is a predetermined signal level, the input signal being inputted to a gate of that one of the two n-channel transistors forming the first series circuit which is provided closer to the Low voltage source, and that one of the two n-channel transistors forming the second series circuit which is provided closer to the Low voltage source, the inverted signal being inputted to a gate of the other of the two n-channel transistors forming the first series circuit which is provided closer to the High voltage source, the output signal being outputted via the connection point at which the two n-channel transistors forming the second series circuit are connected to each other in series, the fourth transistor having a gate for receiving the input signal, the fourth transistor and the resistor connected to each other in series, a source of the fourth transistor connected to either one of a High voltage source and a Low voltage source of the inverted-signal generating section, and that end of the resistor, to which no fourth transistor is connected, connected to the other of the High voltage source and the Low voltage source of the inverted-signal generating section, and the inverted signal being outputted via the connection point at which the fourth transistor and the resistor are connected to each other in series.