Patent ID: 7502900

Claim:
A data processing integrated circuit comprising: a plurality of memories, each of the plurality of memories having an address port and a data input/output port; a memory transfer controller for sending/receiving data to/from an external memory provided external to the data processing integrated circuit; a plurality of read address storing sections that correspond respectively to the plurality of memories; a selector that selects data output from an address of the plurality of memories; and a digital signal processor (CPU) that sets an address of data in the external memory into one of the read address storing sections which corresponds to one of the plurality of memories that does not store data used by the CPU, the CPU executing a program stored in at least one of the plurality of memories, wherein: the memory transfer controller transfers the data stored at the address in the external memory to the one of the plurality of memories that does not store data used by the CPU, through the data input/output port of the one of the plurality of memories, the CPU outputs the address of data in the external memory, and outputs an address of data in the one of the plurality of memories to the address ports of the plurality of memories, in order to read the data, and the selector selects the data output from the one of the plurality of memories from a plurality of data output from the plurality of memories, based on the address of data in the external memory output from the CPU.