Patent ID: 8173501

Claim:
A method, comprising: forming a mask layer on a first active region and a second active region of a semiconductor device; forming a first etch mask so as to cover said second active region and expose said first active region; removing said mask layer selectively from said first active region by using said first etch mask; forming a recess in said first active region in the presence of said first etch mask; after forming said recess in said first active region, forming a layer of a semiconductor alloy on said first active region and using said mask layer on said second active region as a growth mask; forming a second etch mask so as to cover said first active region and expose said mask layer on said second active region; removing said mask layer from said second active region by using said second etch mask; after removing said mask layer from said second active region, recessing said second active region in the presence of said second etch mask; and after forming said recess in said first active region and after recessing said second active region, forming a first gate electrode structure of a first transistor above said first active region and a second gate electrode structure of a second transistor above said second active region, said first and second gate electrode structures comprising a metal-containing gate electrode material and a gate insulation layer comprising a high-k dielectric material.