Patent ID: 7388289

Claim:
An interconnect comprising: an insulating layer having a top surface and a final thickness; a trench in the insulating layer, the trench having a width and a depth across the width of the trench, the depth being a substantially same depth across the width of the trench, the depth being less than the final thickness and greater than a critical depth across the width of the trench, wherein the critical depth includes a vertical thickness of a first barrier layer and a vertical thickness of a seed layer and a vertical thickness of a first metal layer and a vertical thickness of a second barrier layer; the trench including within the trench and below a level coplanar with the top surface at least and no more than the first barrier layer, the seed layer above the barrier layer, and the first metal layer above the seed layer when the width of the trench is less than a first critical width defined as twice the sum of a sidewall first barrier layer thickness, sidewall seed layer thickness, and a sidewall first metal layer thickness; and the trench including within the trench and below a level coplanar with the top surface at least the first barrier layer, the seed layer above the first barrier layer, the first metal layer above the seed layer, the second barrier layer above the first metal layer, and a second metal layer above the second barrier layer when the width of the trench is greater than a second critical width defined as twice the sum of the sidewall first barrier layer thickness, the sidewall seed layer thickness, the sidewall first metal layer thickness, and a sidewall second barrier layer thickness, wherein at least the first metal layer couples a first logic device to a second logic device.