Patent ID: 8247895

Claim:
An article of manufacture comprising a 4D device structure which includes a 2D planar multi-core logic wafer and a vertically stacked 3D memory stack which further comprises a tier-1region and a tier-2 region wherein both of said tier-1 region and said tier-2 region are for secondary 3D stacking (4D), said tier-1 region produced by tier-1 bonding, said tier-1 region having a tier-1 dicing area and wherein said 3D memory stack comprises memory wafers or any of the device combination in said 3D memory stack comprising 2D-in-4D, 3D-in-4D, 2D/3D-in-4D, having a top surface and back surface, and at least one of tongue/groove or lock/key features in said tier-1 region at said top surface and back surface, so that said memory wafers or vertical component in said 3D memory stack are stacked in alignment with each other during said tier-1 bonding, and said tongue/groove, lock/key features define x and y locations in said tier-1 and tier-2 devices.