Patent ID: 7776649

Claim:
A method for fabricating a plurality of wafer level chip scale packages, comprising the following steps of providing a wafer including a plurality of chips integrally connected and having an active surface, a back surface, a plurality of bonding pads disposed on the active surface and a plurality of bumps disposed on the bonding pads; laminating the wafer to a mold plate with a protection film placed on the mold plate so that the bumps are partially embedded into the protection film and an underfill gap is formed between the wafer and the protection film; singulating the wafer into the chips, where each chip has a plurality of sides formed between the active surface and the back surface and where a filling gap is formed between the sides; forming an encapsulant on the protection film on the mold plate, where the encapsulant fills into the underfill gap through the filling gap to completely encapsulate the chips and the non-embedded portions of the bumps; separating the encapsulant encapsulating the chips from the protection film on the mold plate, where the embedded portions of the bumps are exposed and extruded from a bottom surface of the encapsulant; and singulating the encapsulant into the plurality of individual wafer level chip scale packages, where the active surface, the back surface, and the sides are still encapsulated.