Patent ID: 8048794

Claim:
A method of fabricating a thin wafer die, the method comprising the steps of: creating circuits and front-end-of-line wiring on a silicon wafer; drilling holes in a topside of said silicon wafer; depositing an insulator on said drilled holes surface to provide a dielectric insulator to the silicon; removing any excess surface deposition from the surface; putting a metal fill into said holes to form through-silicon-vias (TSV); creating back-end-of-line wiring and pads on the top surface for interconnection; attaching a glass handle to the wafer with a temporary adhesive; thinning down the wafer to expose the insulator in from the TSVs, wherein said TSVs are adapted to be contacted from a backside of said wafer; depositing an insulating layer which contacts said TSV dielectric; thinning down the backside of said silicon wafer; opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon; and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer, wherein an integrated circuit is formed on said wafer.