Patent ID: 8912539

Claim:
An array substrate comprising: a gate electrode; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer, exposing two sides of the gate insulating layer; an etch stopper on the oxide semiconductor layer and entirely over the substrate, the etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; a source electrode, a drain electrode and a pixel electrode on the etch stopper, wherein the source and drain electrodes are spaced apart from each other with the oxide semiconductor layer therebetween, wherein the pixel electrode is connected to the drain electrode; a first passivation layer on the source and drain electrodes and the pixel electrode and entirely over the substrate, the first passivation layer including a second contact hole which fully overlaps the first contact hole, has an area greater than the first contact hole, the second contact hole exposes each of both ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern contacting both the oxide semiconductor layer and the source and drain electrodes respectively.