Patent ID: 7129755

Claim:
A multiplexer, comprising: a first logic module operable to receive a first plurality of data input signals and a first set of select signals and to generate a first output signal in response thereto; a second logic module operable to receive said first set of data input signals and a first set of complementary select signals, wherein each and every one of the first set of complementary select signals is complementary corresponding to said first set of select signals and to generate a second output signal in response thereto; an output line operable to receive a plurality of output signals from said first and second logic modules; a first gate operable to receive said first output signal and to transfer said first output signal to said output line; and a second gate operable to receive said second output signal and to transfer said second output signal to said output line; wherein the capacitive loading of said first and second logic modules is isolated from said output line by said first and second gates, respectively.