Patent ID: 6965268

Claim:
A circuit, comprising: a n-channel differential amplifier having a first input transistor and a second input transistor that delivers current to a summing node, wherein the first and the second input transistors receive bias currents, and wherein the n-channel differential amplifier has a common mode output voltage; and a first n-channel common source amplifier and a second n-channel common source amplifier coupled to the n-channel differential amplifier, wherein the first and the second common source amplifiers have a first output and a second output to provide a negative common mode feedback that is coupled to the summing mode; a feedback circuit coupled to the first and the second outputs of the n-channel common source amplifier circuits, wherein the feedback circuit provides more current to the summing node if voltages at the first and the second outputs rise above a common mode reference voltage; and a biasing circuit coupled to the feedback circuit and the n-channel differential amplifier, wherein the biasing circuit provides a constant current to the summing node, wherein the bias currents through the first and the second input transistors are reduced if a common mode voltage at the first and the second outputs rise above a common mode reference voltage.