Patent ID: 7113428

Claim:
A memory cell ray comprising: a plurality of memory cells, each memory cell comprising: a channel region disposed in a semiconductor material between a source and a drain; a gate electrode electrically insulated from the channel region; and a memory layer between the channel region and the gate electrode, the memory layer being electrically insulated both from the semiconductor material and from the gate electrode; a plurality of word lines coupled to the memory cells such that gate electrodes of memory cells along a row are electrically coupled and are at a basic potential; and a plurality of bit lines coupled to the memory cells such that at least one of the source and/or the drain of memory cells along a column are electrically coupled and are at a basic potential; wherein a programming state of a memory cell is changed by an associated word line having applied to it a first electrical potential deviating from its basic potential and an associated bit line having applied to it a second electrical potential deviating from its basic potential, so that responsive to the application of the first and second electrical potentials, charge carriers of the memory layer of the memory cell tunnel through an electrically insulating region into the semiconductor material or into the gate electrode; and wherein, prior to applying the first electrical potential and the second electrical potential, applying a third electrical potential to the word line associated with the memory cell to be programmed, while the bit lines remain at their basic potential, the value of the third electrical potential lying between the basic potential of the word line and the first electrical potential.