Patent ID: 7958309

Claim:
A method of data processing in a processing unit supported by a memory hierarchy, the processing unit including a processor core and a cache memory, said method comprising: holding in the cache memory a plurality of cache lines each including multiple data granules; the processing unit performing a plurality of memory accesses to the memory hierarchy, said plurality of memory accesses including one or more memory accesses targeting a full cache line of data; the processing unit monitoring utilization of data accessed by the plurality of memory accesses, wherein said monitoring includes maintaining a first count of cache lines having multiple granules updated while the cache lines were resident in the cache memory and a second count of cache lines having only a single granule updated while the cache lines were resident in the cache memory, wherein the first count and second count are global counts across the plurality of cache lines in the cache memory; and based upon the utilization of the data as indicated by the first and second counts, the processing unit dynamically altering a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.