Patent ID: 7122904

Claim:
A semiconductor packaging device comprising: a carrier having a predetermined circuit layout therein, a first surface with a plurality of first ball pads, and a second surface with a cavity thereon, and a first insulating layer having a plurality of first bonding pads therein on said first surface of said carrier, and each plurality of first solder balls on each said plurality of said first bonding pads respectively; at least a first chip having a back surface and an active surface with a plurality of second bonding pads thereon, wherein said first chip is affixed to said cavity of said carrier to expose said active surface; a second insulating layer on said second surface of said carrier and on said active surface, said second insulating layer having a plurality of first via-conductor therein, said plurality of second bonding pads connected to said plurality of first via-conductor, and portion of said plurality of first via-conductor electrically connected to said plurality of said first bonding pads through said predetermined circuit layout within said carrier; a multi-layer structure on said second insulating layer, said multi-layer structure comprising: a plurality of circuit layouts therein; a plurality of flip-chip pads and a third insulating layer thereon, wherein said plurality of said flip-chip pads are exposed on said third insulating layer, and said third insulating layer has a plurality of second via-conductors that connected to said plurality of said flip-chip pads, and said plurality of said flip-chip pads electrically connected to said plurality of first via-conductors through said plurality of circuit layouts; a plurality of solder balls affixed to said plurality of said flip-chip pads; and at least a second chip affixed to said plurality of said plurality of said flip-chip pads through a plurality of second solder balls.