Patent ID: 8073669

Claim:
A method of power conservation in a pipeline electronic device, comprising: providing the pipeline electronic device with a plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage; simulating operation of the pipeline electronic device to determine simulation results that specify selected logic elements that may be clock-gated under predetermined conditions, the simulating operation including looking upstream and downstream in the plurality of pipeline stages to determine the selected logic elements that may provide clock gating opportunities, each clock gating opportunity corresponding to a respective clock gating opportunity type, the simulating operation including weighting the selected logic elements according to their respective clock gating opportunity types, thus indicating their respective power savings potential when clock gated, thus providing weighting results included in the simulation results; and clock-gating the selected logic elements of the pipeline electronic device based on the simulation results to achieve power conservation.