Patent ID: 6965333

Claim:
A circuit design for a delta-sigma digital-to-analog converter, the delta-sigma digital-to-analog converter being conventionally provided with integrating operational amplifier, sampling capacitors, integrating capacitor, resistor voltage divider and operational amplifier buffers, wherein a reference voltage generating circuit consisted of the resistor voltage divider and the operational amplifier buffers is replaced by a voltage divider consisting of a plurality of sampling capacitors; and three trigger signals of different phases are designed to control three sets of switches, a first trigger signal only turns on and off a first set of switches, so as to charge the plurality of sampling capacitors, a second trigger signal only turns on and off a second set of switches, so as to enable the charge on one of the sampling capacitors and the charge on the integrating capacitor to be averaged, a third trigger signal only turns on and off a third set of switches, to enable the plurality of sampling capacitors to be discharged.