Patent ID: 8700856

Claim:
A storage subsystem having a storage controller, the storage controller comprising: a first processor; a first memory coupled to the first processor; a first switch coupled to the first processor and having a first multicast function and a first non-transparent bridge; a second processor; a second memory coupled to the second processor; and a second switch coupled to the second processor and having a second non-transparent bridge; wherein the first non-transparent bridge and the second non-transparent bridge are coupled via a first link; cache memories storing user data and mirrored shared memories storing control information are formed within the first memory and the second memory; the storage controller is further equipped with a first packet redirector coupled to the first switch; the first switch has the first processor and the first non-transparent bridge set within a first multicast group; the first packet redirector causes the received packet to be transferred in the received order to the first multicast group address; and the first processor causes a packet to be transferred to the first packet redirector to thereby execute writing of data to the mirrored shared memories.