Patent ID: 8610239

Claim:
A semiconductor device, comprising: an isolation layer structure, the isolation structure including: a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, respectively, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate, the substrate being divided into an active region in which the first trench is not formed and a field region in which the first trench is formed, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region of the substrate; a well region at a portion of the active region adjacent to the lower portion of the doped polysilicon layer pattern, the well region being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to the upper portion of the doped polysilicon layer pattern, the source/drain being doped with fourth impurities of the first conductivity type.