Patent ID: 7831753

Claim:
An apparatus comprising a first serial-to-parallel interface bridge that presents a serial data storage device mode interface to a data storage host adapter; a second serial-to-parallel interface bridge that presents a serial host mode interface to a serial data storage unit; a data flow control circuit operably connected to the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge, wherein the data flow control circuit is operative to access parallel data storage interface signals from the first and second serial-to-parallel interface bridges; a controller unit, operably connected to the data flow control circuit, and the second serial-to-parallel interface bridge, the controller unit comprising a processor; wherein the controller unit is operable to access executable instructions physically stored in a memory and, when executed, operable to cause the processor to: transmit, responsive to a first data transfer command received from the data storage host adapter, a second data transfer command corresponding to the first data transfer command to the data storage unit through the second serial-to-parallel interface bridge; and wherein the data flow control circuit, responsive to control signals provided by the controller unit, is further operative to interface one or more of the parallel data storage interface signals corresponding to the data storage host adapter from the first serial-to-parallel interface bridge and one or more of the parallel data storage interface signals corresponding to the serial data storage unit from the second serial-to-parallel interface bridge.