Patent ID: 7144775

Claim:
A method of fabricating an electronic memory cell comprising: producing a first drain dopant region and a first source dopant region in an uppermost side of a semiconducting substrate, the first drain and first source dopant regions being doped to provide donor sites; producing a second drain dopant region and a second source dopant region in an uppermost side of a semiconducting substrate, the second drain and second source dopant regions being doped to provide acceptor sites; constructing a shallow trench isolation region substantially between the first drain/first source dopant regions and the second drain/second source dopant regions; coupling the first drain dopant region to the second drain dopant region to communicate electrically; fabricating a PMOS transistor from the second drain and second source dopant regions, the PMOS transistor serving as a select transistor in the memory cell, the PMOS transistor being further configured to have an essentially zero voltage drop between the second source and second drain regions when the PMOS transistor is in an activated state; and fabricating an NMOS transistor from the first drain and first source dopant regions, the NMOS transistor configured to serve as a memory transistor in the memory cell.