Patent ID: 7965808

Claim:
A frequency dividing device for performing variable frequency division, comprising: a clock source configured to generate an input clock signal; a 1/P frequency divider configured to subject the input clock signal to 1/P frequency division to obtain a 1/P frequency signal; a phase shifter configured to shift phase of the 1/P frequency signal and output a plurality of different Q-phase signals; a switch configured to perform phase switching by switching the Q-phase signals from one to another in accordance with a division ratio control signal; a 1/R frequency divider configured to subject a switched clock signal output from the switch to 1/R frequency division and output an Rth frequency clock signal; a ½ frequency divider configured to subject the Rth frequency clock signal to ½ frequency division and output a frequency divided clock signal; and a division ratio setter configured to receive a division ratio set signal indicative of an externally instructed division ratio and generate, based on the division ratio set signal, the Rth frequency clock signal and the frequency divided clock signal, the division ratio control signal for controlling the phase switching, wherein P, Q, and R are integers satisfying P≧1, Q≧3 and R≧1, and the frequency dividing device allows any one of five values indicated by P×R×2, P×R×2±1×P/Q, and P×R×2±2×P/Q to be set as the division ratio in which frequency of the input clock signal is divided, and outputs the frequency divided clock signal with the set division ratio, wherein the division ratio setter is configured to: perform three-choice selection control to select, out of two clock pulses of the Rth frequency clock signal contained in one period of the frequency divided clock signal, one or both or neither of the two clock pulses; decode the division ratio set signal to acquire a polarity bit; generate the division ratio control signal for setting the division ratio of P×R×2 when neither of the two clock pulses is selected; generate the division ratio control signal for setting the division ratio of P×R×2−1×P/Q when one of the two clock pulses is selected and also the polarity bit is “0”; generate the division ratio control signal for setting the division ratio of P×R×2+1×P/Q when one of the two clock pulses is selected and also the polarity bit is “1”; generate the division ratio control signal for setting the division ratio of P×R×2−2×P/Q when both of the two clock pulses are selected and also the polarity bit is “0”; and generate the division ratio control signal for setting the division ratio of P×R×2+2×P/Q when both of the two clock pulses are selected and also the polarity bit is “1”.