Patent ID: 8130127

Claim:
A delta-sigma modulator circuit, comprising: a loop filter having an input for receiving an analog input signal, wherein the loop filter comprises a first switched-capacitor integrator operated by a first clock signal having a first switching rate and a second integrator having an input coupled to an output of the first switched-capacitor integrator; a quantizer having an input coupled to an output of the loop filter for generating a digital output value at a quantization rate of the delta-sigma modulator circuit, wherein the quantizer is operated by a quantizer clock; a feedback path from the output of the quantizer to the loop filter, whereby analog feedback is delivered to the loop filter according to the digital output value; and a control circuit for generating the first clock signal and the quantizer clock and wherein the quantizer clock has a selectable quantization rate selected according to a control signal, wherein the first clock signal has a first switching rate, and wherein the control circuit selects different ratios of the first switching rate to the quantization rate, according to the control signal.