Patent ID: 8295180

Claim:
A method of controlling a processing rate used in a network processor having a plurality of packet processing engines, comprising the steps of: determining an aggregate rate of time critical flows received by the network processor; determining an aggregate minimum rate that will meet respective quality of service requirements of all delay tolerant flows received by the network processor; summing the aggregate rate of time critical flows and the aggregate minimum rate to obtain a summed rate; totaling respective optimal rates for energy efficiency of the packet processing engines to obtain a cumulative optimal rate; comparing the summed rate to the cumulative optimal rate; determining, responsive to the summed rate being greater than the cumulative optimal rate, a respective minimum processing rate for each packet processing engine such that a summation of the minimum processing rates is greater than or equal to the summed rate; and scheduling processing of the delay tolerant flows by the packet processing engines to meet the respective quality of service requirements of the delay tolerant flows.