Patent ID: 8415976

Claim:
A non-blocking routing network, comprising: a plurality of external inputs; a plurality of external outputs; a first plurality of routing rows, each row providing a routing path from at least one of the plurality of external inputs to at least one of the plurality of external outputs, and each row of the first plurality of routing rows including: a first multiplexer including a first set of inputs and a first internal output, the first set of inputs including two external inputs of the plurality of external inputs, the first multiplexer configured to provide a selected input of the first set of inputs to the first internal output in response to a first selection input; a second multiplexer including a second set of inputs and a second internal output, the second set of inputs including the two external inputs of the plurality of external inputs and a second internal output from a first other routing row, the second multiplexer configured to provide a first selected input of the second set of inputs to the second internal output in response to a second selection input; a third multiplexer including a third set of inputs and a first external output, the third set of inputs including the two external inputs of the plurality of external inputs, the second internal output from the first other routing row, and a second internal output from a second other routing row, the third multiplexer configured to provide a selected input of the third set of inputs to the first external output in response to a third selection input; and a fourth multiplexer including the third set of inputs and a second external output, the fourth multiplexer configured to provide a second selected input of the third set of inputs to the second external output in response to a fourth selection input; and a second plurality of routing rows that each provide a routing path from at least two of the plurality of external inputs to at least two of the plurality of external outputs, wherein a routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.