Patent ID: 6845494

Claim:
A method for budgeting timing used in producing an integrated circuit design, said circuit design having register cells and combinational logic cells, said circuit design having a representation that is hierarchically decomposed into a top-level and a plurality of blocks, at least some of the plurality of said blocks being capable of being further hierarchically decomposed, said register cells and combinational logic cells having at least one cell pin, said blocks having boundaries, said block boundaries represented by at least one block pin, said method comprising: optimizing at least one path, through block pins by zero-slack trimming that includes adjustment of gains within at least some of said cells along said at least one path to apportion slack between said cells along said at least one path, said optimization resulting in assigned gains for all said cells along said at least one path; performing timing analysis on said at least one path, said timing analysis using said assigned gains in order to generate arrival times for signals at said block pins; and deriving a timing budget by examining said generated arrival times at said block pins wherein said timing budget at said block pins is derived using said generated arrival times at block inputs and required times at block outputs.