Patent ID: 7471564

Claim:
A method for operating a flash memory array, which comprises a plurality of fin-shaped channel structures on a semiconductor substrate, the channel structures respectively having one of an n-type or p-type conductivity, a first terminal having a different conductivity type and a second terminal spaced away from the first terminal having the different conductivity type, without intervening terminals having the different conductivity type; a plurality of word lines, arranged orthogonally with respect to the plurality of fin-shaped channel structures, the plurality of word lines including at least three word lines overlying the plurality of fin-shaped channel structures between the respective first and second terminals; charge trapping structures, including a dielectric charge trapping layer between, and at the cross-points of, the plurality of word lines and the plurality of fin-shaped channel structures, so that an array of memory cells is provided; the method comprising: applying bias voltages to the respective first and second terminals of the plurality of fin-shaped channel structures and to the plurality of word lines, including biasing voltages that induce inversion regions in the fin-shaped channel structure for conducting voltages from the first and second terminals to a selected memory cell.