Patent ID: 7793048

Claim:
A cache memory comprising: a cache array having a plurality of cache lines; a cache directory which determines that the cache array does not have currently valid entries corresponding to first and second requested memory values; a first data bus that receives separate portions of the first requested memory value over a first time span of successive clock cycles; a second data bus that receives separate portions of the second requested memory value over a second time span of successive clock cycles, wherein the first time span at least partially overlaps with the second time span; and a cache controller that identifies which portions of the first and second requested memory values are being received and loads the first and second requested memory values respectively into first and second cache lines of said cache array, wherein said first and second cache lines are spread across different cache sectors of the cache array, said cache sectors having different output latencies, and the separate portions of a given requested memory value are loaded sequentially into corresponding cache sectors based on the cache sectors' respective output latencies.