Patent ID: 7947540

Claim:
A method of fabricating a multi-level semiconductor device, comprising: forming a first transistor on a semiconductor substrate, the first transistor including a first source/drain region; forming a semiconductor layer on the semiconductor substrate; forming a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer; doping impurities in a second portion of the semiconductor layer to form a contact region having a higher impurity concentration than the second source/drain region; and forming a contact pattern that extends from the first source/drain region and contacts the contact region of the semiconductor layer, wherein forming the contact region includes: forming an upper contact hole in an upper interlayer dielectric on the semiconductor layer, the upper contact hole exposing a portion of the semiconductor layer and partially overlapping a single crystalline layer in a lower interlayer dielectric; and doping the impurities in the semiconductor layer, and wherein forming the contact pattern includes: removing a portion of the lower interlayer dielectric exposed by the upper contact hole to form a lower contact hole; and forming a conductive layer in the upper and lower contact holes, the conductive layer contacting the single crystalline layer.