Patent ID: 8223106

Claim:
A display device, comprising: an input signal generator generating an input signal comprising one of a plurality of input frequencies corresponding to a respective one of a plurality of operating modes of the display device; a main operating clock generator generating a main operating clock using the input signal and a reference signal, a main frequency of the main operating clock varying in accordance with the input frequency, and a reference frequency of the reference signal being constant irrespective of the operating modes; and a control signal generator generating a control signal using the main operating clock, the control signal changing in accordance with the main frequency and including a source sampling clock (SSC), a gate shift clock (GSC), a source start pulse (SSP), a source output enable (SOE), a gate start pulse (GSP), and a gate output enable (GOE), the source sampling clock, the source start pulse, and the source output enable being transmitted to a data driver, and the gate shift clock, the gate start pulse and the gate output enable being transmitted to a gate driver, wherein the main operating clock generator includes: a divider receiving the input signal directly from the input signal generator and dividing the input frequency of the input signal by a division ratio to generate a divided signal, a phase detector comparing a frequency of the divided signal with the reference frequency of the reference signal to generate a compared signal, a pulse-to-voltage converter converting the compared signal into a control voltage, and a voltage controlled oscillator generating the main operating clock comprising the main frequency corresponding to a level of the control voltage, and wherein the control signal generator and the input signal generator forms form a timing controller.