Patent ID: 8053682

Claim:
A multilayer ceramic substrate comprising: a plurality of dielectric layers; and a circuit pattern part disposed on at least a portion of the dielectric layers, the circuit pattern part including at least one conductive via and conductive pattern, wherein the at least one conductive via comprises an outer peripheral portion and an inner peripheral portion, the outer peripheral portion being disposed along an inner wall of a via hole extending through the dielectric layers and being of a first conductive material containing a metal and at least one of silicon oxide (SiO 2 ) and glass, and the inner peripheral portion being filled inside the outer peripheral portion and being of a second conductive material having more silicon oxide (SiO 2 ) or glass than that of the first conductive material so as to have a shrinkage initiation temperature higher than a shrinkage initiation temperature of the first conductive material and equal to or higher than a shrinkage initiation temperature of the dielectric layers.