Patent ID: 7247890

Claim:
A semiconductor device comprising: a first impurity diffusion region and a second impurity diffusion region each having a first conduction type formed on one main surface of a semiconductor substrate at a predetermined distance; a channel region formed in a third impurity diffusion region of the semiconductor substrate which has a second conduction type opposite to the first conduction type and is formed between the first impurity diffusion region and the second impurity diffusion region; a fourth impurity diffusion region having the second conduction type and being formed between the first impurity diffusion region and the substrate as well as between the first and third impurity diffusion regions; and a MISFET formed by stacking a gate electrode by way of a gate dielectric film above the channel region and portions of the first impurity diffusion region and the second impurity diffusion region, wherein the first impurity diffusion region is formed with an impurity concentration higher than an impurity concentration of the second impurity diffusion region, and the third diffusion impurity diffusion region is formed with an impurity concentration lower than an impurity concentration of the fourth impurity diffusion region, and an anti-oxidation film deposited by a CVD method on a side wall of the gate electrode is formed to prevent polysilicon of the gate electrode from being oxidized during a light oxidation treatment.