Patent ID: 6876090

Claim:
A semiconductor chip, comprising: a top side with a surface; said top side having a first portion to be covered by a potting compound or encapsulation compound of a housing; said top side having a second portion to remain free at the potting compound or encapsulation compound a facilitator provided on said top side of the chip between said top side of the chip and the potting compound or the encapsulation compound, said facilitator selected from the group consisting of a material applied thereon and an areal structure formed thereon for defining a variation in a degree of wettability or adhesion characteristics relative to the potting compound or the encapsulation compound for said surface in said first portion and said surface in said second portion, said facilitator rendering wetting, flowing, or adhesion of the potting compound or encapsulation compound in said second portion of said top side more difficult than in said first portion, and promoting an application of the potting compound or encapsulation compound exclusively on said first portion.