Patent ID: 8001438

Claim:
A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design for an integrated circuit, the computer-implemented method comprising: simulating the circuit design using the test pattern to generate simulation results; determining stuck at coverage for the test pattern; calculating, by a processor, respective measures of bridge fault coverage for pairs of adjacent nets comprising a first net and a second net in the circuit design on a per-pair basis, wherein calculating comprises: for each pair of adjacent nets, performing steps including: determining from the test pattern and simulation results whether or not the test pattern tests the first and second nets of the pair for stuck at faults; in response to determining that the test pattern tests the second net of the pair for a stuck at fault, determining whether, from the simulation results, the first net is held constant while the second net toggles according to the test pattern applied to the second net; and in response to determining that the test pattern tests the first net of the pair for a stuck at fault, determining whether, from the simulation results, the second net is held constant while the first net toggles according to the test pattern applied to the first net; calculating the respective measure of bridge fault coverage for the pair of adjacent nets as a function of whether or not the first net was determined to be constant while the second net toggles, and whether or not the second net was determined to be constant while the first net toggles; determining a measure of bridge fault coverage for the entire circuit design according to the respective measures of bridge fault coverage for the pairs; and outputting the measure of bridge fault coverage.