Patent ID: 7445975

Claim:
A method for the production of a semiconductor component having a metallic gate electrode, having a gate head and a gate foot that is narrower than the gate head, which is disposed in a double-recess structure having a broad and a narrow recess, comprising the following steps: depositing a semiconductor layer sequence for a field-effect transistor, the layer sequence comprising: a channel layer; a barrier layer above the channel layer; a low-doped shielding layer above the barrier layer; a stop layer lying on top of the shielding layer; and a highly doped contact layer above the stop layer; depositing an intermediate layer and an auxiliary layer on the contact layer; producing a first opening that determines a structure of the gate foot in the auxiliary layer and the intermediate layer; transferring the first opening into the contact layer, up to the stop layer, with a structure of the narrow recess, as a first partial recess; under-etching the auxiliary layer with a structure of the broad recess, by selective etching of the intermediate layer; producing an opening in the stop layer with the first partial recess as a mask; widening the partial recess in the contact layer to form the broad recess, with the structure in the intermediate layer as a mask; exposing the narrow recess in the shielding layer up to the barrier layer, with the opening in the stop layer; and depositing gate metal for the gate foot into the narrow recess, with the opening in the auxiliary layer as a mask, and for the gate head, onto the auxiliary layer.