Patent ID: 7421540

Claim:
A method, in a data processing system, for determining cache prefetching patterns, the method comprising: identifying an instruction as a candidate for cache prefetching; placing the instruction in data gathering mode; upon executing the instruction in data gathering mode, recording, in an array of address differences, a difference between a current address being referenced and a last address being referenced, wherein the difference is determined using a cache line size; and responsive to a number of address differences being recorded in the array of address differences exceeding a threshold, determining an expected cache stride value based on the array of address differences, wherein the expected cache stride value is determined using the following equation: B = ( ( ∑ ( differences ⁡ [ i - 1 ] ) * ∑ ( i 2 ) ) - ( N * ( N + 1 ) / 2 ) * ∑ ( i * differences ⁡ [ i - 1 ] ) ) ( ( N * ∑ ( i 2 ) ) - ( N * ( N + 1 ) / 2 ) 2 ) wherein B represents an expected cache stride in terms of cache lines and wherein all sums are for i=1 to N, wherein N is the number of address differences in the array of address differences.