Patent ID: 7863745

Claim:
A semiconductor device, comprising: a semiconductor substrate in which a plurality of functional elements are formed; a multilayer interconnection layer provided over the semiconductor substrate, the multilayer interconnection layer including a plurality of wiring layers mutually connecting the plural functional elements and including a plurality of interlayer insulation layers, the multilayer interconnection layer having a structure in which the plural wiring layers and the plural interlayer insulation layers are stacked on each other; and a plurality groove forming parts provided in the multilayer interconnection layer outside a wiring region where the plural wiring layers are formed and connected to electrode pads, each of the groove forming parts positioned inside a dicing line provided along a circumference of each functional element, and each of the groove forming parts piercing the plural interlayer insulation layers in the multilayer interconnection layer to reach an upper surface of the semiconductor substrate, wherein each of the groove forming parts is filled with an organic insulation material and the organic insulation material is provided to cover an upper surface of the multilayer interconnection layer, wherein the plurality of groove forming parts is formed in the multilayer interconnection layer so as to surround the region where the wiring layer is formed.