Patent ID: 8847349

Claim:
An integrated circuit (“IC”) package comprising: an IC die having an upper surface with a plurality of contact pads thereon and a bottom surface; a patterned metal signal routing layer positioned below said bottom surface of said die and having a top surface and a bottom surface, said top surface of said signal routing layer being wire bond attached to at least one of said contact pads on said die; a polyimide tape substrate positioned below said IC die and said signal routing layer and having a top surface and a bottom surface and having a plurality of vias extending between said top and bottom surfaces thereof; at least one solder resist layer provided on one of said polyimide tape substrate and said signal routing layer; a conductive ink printed passive circuit layer printed on one of said polyimide tape substrate and said solder resist layer and electrically connected to said signal routing layer; an encapsulation layer encapsulating said IC die, said etched metal signal routing layer, said conductive ink printed layer and at least a portion of said polyimide tape substrate; and a ball grid array positioned below said polyimide tape substrate and electrically attached to said etched metal signal routing layer through said vias.