Patent ID: 7247910

Claim:
A semiconductor device comprising: a semiconductor layer which is formed on an insulating film or on an insulating substrate while being surrounded by an element-isolation insulating film, and includes a channel region and a source/drain region; a gate electrode which is formed on the channel region via a gate insulating film while being surrounded by a sidewall insulating film; and an elevated layer which is made of a conductive material and is formed on the source/drain region while being surrounded by the element-isolation insulating film and the gate electrode; wherein the elevated layer is so formed as to be buried in a depression defined by the gate electrode on which the sidewall insulating film is formed and by the element-isolation insulating film on which the sidewall insulating film is formed, while having a height different from that of the gate electrode and a surface height of the elevated layer is lower than the surface height of the element-isolation insulating film, wherein a film thickness of the elevated layer is 30 nm or less.