Patent ID: 8130825

Claim:
A system for processing video data, comprising: a reconfigurable digital video processor including an array of adders configured to perform motion estimation on a sequence of frames by performing a plurality of sum of absolute differences (SAD) operations, wherein performing motion estimation includes comparing a block of picture elements (PELs) associated with a current frame with a block of PELs associated with a frame before the current frame or with a block of PELs associated with a frame subsequent to the current frame, wherein the reconfigurable digital video processor includes heterogeneous processing nodes connected by a matrix interconnect network; and a control processor configured to provide instructions to the reconfigurable digital video processor that dynamically configure the heterogeneous processing nodes and the matrix interconnect network included in the reconfigurable digital video processor to receive input video data associated with a first format and to generate output video data associated with a second format, wherein the instructions include information related to both the first format and a first resolution of the input video data as well as the second format and a second resolution of the output video data, and wherein the instructions further include degree of compression information.