Patent ID: 8588341

Claim:
A data transfer circuit that transfers data between a first clock domain using a first clock and a second clock domain using a second clock synchronized with the first clock, comprising: a data holding circuit operating at the first clock to receive, hold, and send the data; and an enable signal generation circuit connected to the data holding circuit to generate an input enable signal allowing the data holding circuit to receive the data and an output enable signal allowing the data holding circuit to send the received data, the enable signal generation circuit being adapted to enable the input enable signal and the output enable signal so that the input enable signal and the output enable signal are enabled when edges of the first clock and the second clock align, and, for the first clock and the second clock in a case where the first clock is faster than the second clock, enable the input enable signal so that the input enable signal is enabled at a predetermined one of edges of each clock pulse of the first clock precedent to and close to a predetermined one of edges of each clock pulse of the second clock occurring after the edge alignment in an interval between the edge alignment and a next edge alignment, enable the output enable signal so that the output enable signal is enabled at a predetermined one of edges of each clock pulse of the first clock subsequent to and close to a predetermined one of edges of each clock pulse of the second clock occurring after the edge alignment, and apply the input enable signal and the output enable signal to the data holding circuit, wherein the enable signal generation circuit comprises: a timing signal holding circuit operating at the first clock to receive, hold, and send a timing signal for the time when edges of the first clock and the second clock align; an input enable signal generator operating at the first clock to receive inputs of the number of clock pulses of the first clock N 1st and the number of clock pulses of the second clock N 2nd between an edge alignment and a next edge alignment of the first clock and the second clock, and the timing signal, and generate the input enable signal; and an output enable signal generator operating at the first clock to receive inputs of the N 1st , the N 2nd , and the timing signal, and generate the output enable signal.