Patent ID: 8288813

Claim:
A memory device comprising: a plurality of storage cells arranged in rows and columns, wherein each storage cell of the plurality of storage cells comprises a tunneling field effect transistor; wherein each of the tunneling field effect transistors comprises a doped drain region and a doped source region, wherein the doped drain region is of a different doping type than the doped source region; each of the tunneling field effect transistors further comprises a floating gate; a first word line connected to a first row of storage cells; a first bit line to control a voltage of the doped drain regions of the tunneling field effect transistors of a first column of storage cells; and a second bit line that controls a voltage of the doped source regions of the tunneling field effect transistors of the first column of storage cells, wherein the second bit line is an electrically insulating well, wherein a first tunneling field effect transistor, of the tunneling field effect transistors, of a first storage cell has a first floating gate connected to a control gate of the first word line, a first doped drain region connected to the first bit line, and a first doped source region connected to the second bit line via the electrically insulating well, the first tunneling field effect transistor having a tunneling junction and a tunneling current flowing through the tunneling junction between an inversion channel formed in an intrinsic region of a p-i-n region of the first tunneling field effect transistor and one of the first doped drain region and the first doped source region, and said first tunneling field effect transistor is immediately adjacent in a column to a second tunneling field effect transistor, and the second tunneling field effect transistor is immediately adjacent in said column to a third tunneling field effect transistor, and wherein a first distance in said column between the floating gate of the first tunneling field effect transistor and the floating gate of the second tunneling field effect transistor is smaller than a second distance in said column between the floating gate of the second tunneling field effect transistor and the floating gate of the third tunneling field effect transistor, wherein at least two floating gates of the adjacent floating gates in said column are separated by lithographically dependent minimum structure widths plus a clearance distance of approximately 10% of said minimum structure width.