Patent ID: 7460387

Claim:
A DRAM memory array comprising: a plurality of memory cells, each of said plurality of memory cells further comprising: a device, each of said plurality of memory cells having one of said device organized in a row representing a plurality of word lines or a bit column representing bits of said plurality of word lines, each said bit column having more than one pair of a local bit line true, and a local bit line complement, said local bit line true and said local bit line complement are balanced, said local bit line true is connected by way of a first CMOS transistor switch to a global bit line true and said local bit line complement is connected by way of a second CMOS transistor switch to a global bit line complement, said global bit line true and said global bit line complement are balanced; a first stage differential sense amplifier, said first stage differential sense amplifier having a cross coupled differential half latch connected to each of said local bit line true and said local bit line complement, said first stage differential sense amplifier being responsive to a first timing pulse effectuating the setting of said first stage differential sense amplifier; and a second stage global sense amplifier, said second stage global sense amplifier having a full cross coupled latch connected to each of said global bit line true and said global bit line complement, said second stage global sense amplifier being responsive to a plurality of global timing pulses effectuating the setting of said second stage global sense amplifier.