Patent ID: 8418092

Claim:
A monolithic device, comprising: a first circuit operating with a first clock, a second circuit embodied as a hard core operating with a second clock that is not synchronized with the first clock, and a source-synchronous data link between the first circuit and the second circuit for communicating n-bit data elements between the first circuit and the second circuit, the source-synchronous data link including, a set of n data lines for transporting the n-bit data elements between the first circuit and the second circuit, and a source-synchronous clock line for transporting a source clock between the first circuit and the second circuit for clocking the n-bit data elements, wherein the hard core does not include a bus interface adaptor for interfacing with the source-synchronous data link; wherein the source-synchronous data link further comprises a plurality of level shifters for shifting voltage levels of data transported on the n data lines and voltage levels of the source clock transported on the source-synchronous clock line.