Patent ID: 8687428

Claim:
A system comprising: a non-volatile memory (NVM) array; a NVM reference current generator configured to generate a NVM reference current used to access the NVM array; an analog-to-digital converter (ADC), coupled to the NVM reference current generator, and configured to convert the NVM reference current to a digital NVM reference current value; a comparator, coupled to the ADC, and configured to compare the digital NVM reference current value to a target value; and trim logic, coupled to the comparator, and configured to provide a control signal for the NVM reference current generator to produce an adjusted NVM reference current if the digital NVM reference current value is outside a range of the target value, wherein a digital adjusted NVM reference current value is within the range of the target value, and the range of the target value comprises a lower limit of the range of the target value and an upper limit of the range of the target value; one or more registers, coupled to the comparator, storing the lower limit of the range of the target value and the upper limit of the range of the target value; a temperature sensor, coupled to one or more of the ADC and the one or more registers, and configured to provide temperature data to the one or more of the ADC and the registers; the ADC further configured to adjust the digital NVM reference current value in response to the temperature data, if needed; and the one or more registers further configured to adjust the lower limit of the range of the target value and the upper limit of the range of the target value in response to the temperature data, if needed.