Patent ID: 8223552

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell including: a semiconductor layer including, a channel, and a source region and a drain region provided on both sides of the channel; a first insulating film provided on the channel; a charge retention layer provided on the first insulating film; and a gate electrode provided on the charge retention layer; and a driving unit configured to perform a programming operation, in the programming operation, the driving unit is: configured to apply a first burst signal between the gate electrode and the semiconductor layer for programming charge on the charge retention layer, the first burst signal having a first constant amplitude and a first constant frequency, the first constant amplitude having a first low-level voltage and a first high-level voltage being higher than the first low-level voltage; configured to apply a first verifying signal between the gate electrode and the semiconductor layer for reading a threshold value of the memory cell after the applying the first burst signal, an absolute value of the first verifying signal being smaller than an absolute value of the first high-level voltage; and configured to apply the first low-level voltage between the gate electrode and the semiconductor layer after the applying the first burst signal and before the applying the first verifying signal.