Patent ID: 8327118

Claim:
Apparatus for processing data in response to a stream of program instructions, said apparatus comprising: a plurality of execution units responsive to said stream of program instructions to perform data processing operations specified by said stream of program instructions; and dynamic scheduling circuitry, responsive to a current state of said plurality of execution units, configured to issue, for execution during one or more processing clock cycles, program instructions of said stream of program instructions to respective execution units of said plurality of execution units; wherein at least one of said execution units is an error-detecting execution unit comprising a latch responsive to a signal generated by said error-detecting execution unit to capture at a capture time a data value and error detecting circuitry responsive to a change in said signal during an error detecting period following said capture time to trigger an error recovery response; and said scheduling circuitry suppresses issue of program instructions to said error-detecting execution unit in a current processing clock cycle where a program instruction was issued to said error-detecting execution unit in a processing clock cycle immediately preceding said current processing clock cycle.