Patent ID: 7327629

Claim:
An antifuse circuit for reading an antifuse, comprising: a first inverter having a first input node, a first output node, a first common node and a first supply node, the first common node coupled to the antifuse; a second inverter having a second input node, a second output node, a second common node and a second supply node, the first input node coupled to the second output node and the first output node coupled to the second input node; an impedance device coupled to the second common node and having an electrical impedance; an initialization circuit having a supply node, an output node and a control node to which a signal is applied, the output node coupled to the first input node, the second input node and the first and second common nodes, the initialization circuit configured to couple the output node to the supply node and decouple the output node from the supply node in response to the signal applied to the control node; and an inverter having an input coupled to the second output and further having an output at which a signal having a logic level indicative of the antifuse state is provided.