Patent ID: 7165205

Claim:
A method for operating a transmitter that generates parity-check bits (p 0 , . . . , p m−1 ) based on a current symbol set s=(s 0 , . . . , s k−L−1 ), the method comprising the steps of: receiving the current symbol set s=(s 0 , . . . , s k−L−1 ), where L is a number of bits the current symbol set is shortened, 0<=L<=k−1, and k is the length of the entire current symbol set when unshortened; using a matrix H to determine the parity-check bits, wherein H comprises a section H 1 and a section H 2 , and wherein H 1 has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlaced between the sub-matrices; and transmitting the parity-check bits along with the current symbol set.