Patent ID: 8048747

Claim:
A method of manufacturing an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device, comprising the steps of: (a) providing a dielectric isolation layer, wherein said dielectric isolation layer has a conductive layer used as a bottom gate of a gate-first structure; (b) processing thermal oxidation to obtain a bottom dielectric layer on said dielectric isolation layer, wherein said bottom dielectric layer comprises a bottom oxide layer, a nitride layer and a top oxide layer stacked one after one to obtain an oxide-nitride-oxide structure; (c) depositing a poly-silicon layer on said bottom dielectric layer; (d) obtaining a nano-wire region on said poly-silicon layer by using a first mask so that a source/drain (S/D) ion implant region on said poly-silicon layer is included in the poly-silicon layer; (e) obtaining a channel region on said S/D ion implant region of said poly-silicon layer by using a second mask to obtain an active region on said poly-silicon layer; (f) processing ion implantation to implanting ions into said S/D ion implant region of said poly-silicon layer to obtain S/D electrodes, wherein bit lines are buried in said S/D electrodes; (g) removing said second mask; and (h) after removing said second mask, activating implanted ions in said S/D electrodes of said poly-silicon layer through low-temperature annealing so that a channel is formed between said S/D electrodes in said active region on said poly-silicon layer so as to obtain a single-layer embedded MONOS memory device, wherein said nitride layer is a charge storage layer, wherein, in step (h), implanted ions in said S/D electrodes of said poly-silicon layer are activated through low-temperature annealing at a temperature between 540 and 660 Celsius degrees (° C.) for a time period between 27 and 33 minutes (min).