Patent ID: 7514977

Claim:
A clock signal generating circuit comprising: a clock signal generator for generating a first clock signal having a predetermined frequency; a frequency dividing circuit for receiving the first clock signal, for providing second clock signal with a frequency that is lower than the predetermined frequency of the first clock signal, wherein the frequency dividing circuit comprises: an NPN transistor having the emitter connected to ground, the collector connected to a voltage input, and the base connected to the clock signal generator; a programmable uni-junction transistor having the gate connected to the collector of the NPN transistor, the anode connected to a voltage input, and the cathode connected to ground; a first variable capacitor connected between the collector of the NPN transistor and the gate of the programmable uni-junction transistor; and a second variable capacitor connected between the gate of the programmable uni-junction transistor and ground; and a frequency multiplier circuit receiving the second clock signal, for providing a system clock signal resuming the predetermined frequency to a load.