Patent ID: 7459742

Claim:
A memory device, comprising: a memory array comprised of a plurality of word line structures, each of said plurality of word line structures each having a pair of homogenous first insulative sidewall spacer constructions of a first insulative material formed adjacent thereto, said homogenous first insulative sidewall spacer constructions of said first insulative material each having a first base and a first maximum thickness at the first base in a cross section within the memory array, the homogenous first insulative sidewall spacer constructions of said first insulative material being tapered in said cross section within the memory array and not being L-shaped in said cross section within the memory array; and a peripheral circuit comprised of at least one transistor having a homogenous second insulative sidewall spacer construction of said first insulative material formed adjacent thereto, said homogenous second insulative sidewall spacer construction of a said first insulative material having a second base and a second maximum thickness at the second base in a cross section within the peripheral circuit, the second maximum thickness being greater than said first maximum thickness, the homogenous second insulative sidewall spacer construction of said first insulative material being L-shaped in said cross section within the peripheral circuit and not being tapered in said cross section within the peripheral circuit.