Patent ID: 7833847

Claim:
A method of forming a semiconductor device, the method comprising: forming a lower transistor on a semiconductor substrate; forming a lower interlayer insulating layer on the lower transistor; forming an upper transistor and an upper interlayer insulating layer covering the upper transistor, on the lower interlayer insulating layer; forming a common contact hole to expose source/drain regions of the lower transistor by patterning the upper interlayer insulating layer, source/drain regions of the upper transistor, and the lower interlayer insulating layer; forming a blocking layer to cover the bottom of the common contact hole but to expose the source/drain regions of the upper transistor; forming a first ohmic layer on the exposed source/drain regions of the upper transistor; exposing the source/drain regions of the lower transistor by removing the blocking layer disposed on the bottom of the common contact hole; forming a second ohmic layer on the exposed source/drain regions of the lower transistor; and forming a common contact plug in the common contact hole.