Patent ID: 8510633

Claim:
An operation method of a semiconductor storage device which stores in a memory array, error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols, wherein said plurality of bits are stored in memory cells including any of phase change resistance elements, metal oxide resistance elements and solid electrolyte resistance elements, wherein the respective symbols are read by using different reference cells, wherein, when a correctable error is detected in read data from data cells forming said error correction codes and corresponding to an input address, (A) for a first error symbol of an one bit error pattern, a data in a data cell corresponding to the error bit is corrected, and (B) for a second error symbol related to a multi-bit error pattern, a data in a reference cell that is used to read the second error symbol is corrected, wherein after the data in the data cell associated with the first error symbol described in said (A) is corrected, a re-reading operation and an error detecting operation are performed for the data cells forming said error correction codes, and when a correctable error is detected again in the re-read data, (C) a data in a reference cell used to read said first error symbol is corrected.