Patent ID: 7856542

Claim:
A system for virtualizing a processor, comprising: a virtualization system running on a computer system and maintaining real paging structures; a Virtual Machine (VM) having at least one set of guest paging structures that correspond to guest pages in a virtualized linear address space; for each guest page that is mapped to the real paging structures, means for handling a connection structure between the guest page and a real physical address of the guest page; a set of cached paths to the real paging structures, each path being described by guest paging structure descriptors and by tie descriptors; and each path comprising a plurality of nodes connected by the tie descriptors, wherein each guest paging structure descriptor is in a node of at least one path, wherein each guest paging structure either points to other guest paging structures or to guest pages, and wherein each guest paging structure descriptor is used to map guest pages to the real paging structures.