Patent ID: 8359556

Claim:
A method, in a data processing system, for multiple patterning conflict resolution, the method comprising: receiving, by the data processing system, a design layout for an integrated circuit; performing, by the data processing system, decomposition to form at least a first mask and a second mask with stitch locations, wherein the first mask and the second mask have coloring conflicts such that at least one shape in the first mask or the second mask is too close to another shape in the same mask; defining, by the data processing system, interactions between the first mask and the second mask using a set of split level design rules, wherein the set of split level design rules comprises a rule stating that same-layer spacing equals spacing of single patterning, a rule stating that different-layer spacing equals spacing of a final layout, a rule stating that layer overlap equals a minimum overlap length, and recommendation rules for sacrificial parts; and automatically fixing, by the data processing system, native conflicts in the first mask and the second mask by modifying at least one shape in the first mask or the second mask subject to the set of split level design rules to form the final layout.