Patent ID: 8484008

Claim:
A method of performing timing sign-off of an integrated circuit design, comprising: (a) dividing the integrated circuit design into a plurality of blocks; (b) extracting a timing model for each block using static timing analysis, wherein the extracted timing model includes timing information independent of remaining blocks; (c) integrating the plurality of blocks into the integrated circuit design; (d) performing an integrated circuit level static timing analysis on the integrated circuit design using the extracted timing model of each block to obtain a first integrated circuit design timing; (e) determining whether the first integrated circuit design timing is within predetermined performance criteria; (f) if the first integrated circuit design timing is not within the predetermined performance criteria, then modifying the integrated circuit design by changing the integration of the plurality of blocks in the integrated circuit design and returning to step (d); (g) if the first integrated circuit design timing is within the predetermined performance criteria, then performing an integrated circuit level static timing analysis on the integrated circuit design without using the extracted timing model of each block to obtain a second integrated circuit design timing; (h) determining whether the second integrated circuit design timing is within the predetermined performance criteria; (i) if the second integrated circuit design timing is not within the predetermined performance criteria, then modifying the integrated circuit design by changing the integration of the plurality of blocks in the integrated circuit design and returning to step (d); and (j) if the second integrated circuit design timing is within the predetermined performance criteria, then signing off on the timing of the integrated circuit design.