Patent ID: 7045864

Claim:
A semiconductor integrated circuit device, comprising memory cells, each formed of a pair of inverters having their input and output points connected in a crisscross manner and which are each formed of an n-channel MISFET and a p-channel MISFET, said n-channel MISFET and p-channel MISFET each including: a gate electrode, which is made from a silicon film and is formed on a silicon substrate, between which a gate insulation film is interposed; source and drain regions formed in said silicon substrate on both side regions of said gate electrode; a metal silicide layer respectively formed on said gate electrode and on said source region, an interlayer insulating film formed over the source and drain regions, the gate electrode and the silicide layers; a first contact hole formed in said interlayer insulating film, exposing the silicide layer formed on the source region; a second contact hole formed in said interlayer insulating film, exposing the drain region; a first conductor film formed in said first contact hole, which is electrically connected to the source region and the silicide layer formed on the source region; and a second conductor film formed in said second contact hole, which is electrically connected to the drain region, wherein said metal silicide layer is absent on said drain region.