Patent ID: 8247288

Claim:
A method for integrating a capacitor onto a power semiconductor device comprising the steps: a. providing a first power transistor disposed on a semiconductor chip, wherein the first power transistor having a first metal electrode and a second metal electrode disposed on a top surface of the semiconductor chip; b. depositing a dielectric layer overlaying the first metal electrode and the second metal electrode, forming a plurality of conducting vias through the dielectric layer on top of the first metal electrode and the second metal electrode; c. depositing a conductive layer overlaying the dielectric layer, said conductive layer electrically connecting to the first and second metal electrodes through the conducting vias; d. patterning the conductive layer to form a capacitor plate above the first metal electrode and a second electrode extending structure above the second metal electrode; e. repeating steps b to d until a predetermined number of capacitor plate layers being provided.