Patent ID: 8638124

Claim:
A clock phase shift detector circuit, comprising a phase detector that receives a first and a second clock signal, the phase detector generating a phase signal based on a phase difference between the first and the second clock signal; a current mirror coupled to the phase detector, the current mirror having a first integrator, a second integrator, and a third integrator, wherein the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage; a first comparator coupled to the first and the third integrator, the first comparator receiving the first and the third voltage, wherein the first comparator generates a first control signal based on an amplitude comparison between the first and the third voltage; and a second comparator coupled to the second and the third integrator, the second comparator receiving the second and the third voltage, wherein the second comparator generates a second control signal based on an amplitude comparison between the second and the third voltage, wherein the generated first and second control signal detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.