Patent ID: 8010865

Claim:
A channel encoder configured to encode M data bits onto a channel for further modulation, comprising: a first cyclical redundancy check (CRC) encoding block configured to receive the M data bits, generate L CRC bits, and add the L CRC bits to the M data bits; a padding block coupled to the first cyclical redundancy check (CRC) encoding block, wherein the padding block is configured to receive the M data bits, add n bits of padding to the M data bits, and output M+n bits of data to the first CRC encoding block; a tail-biting convolutional encoder coupled to the first CRC encoding block, the tail-biting convolutional encoder configured to encode the M+L bits using a tail biting technique and generate output symbols; an interleaver coupled to the tail-biting convolutional encoder, the interleaving block configured to interleave the output symbols; and a sequence repetition block coupled to the interleaver, the sequence repetition block configured to add a repetition sequence to the output symbols.