Patent ID: 8885412

Claim:
A three-dimensional stacked non-volatile memory device, comprising: a substrate; a stacked non-volatile memory cell array carried by the substrate, the stacked non-volatile memory cell array comprising a memory string, the memory string comprising a plurality of memory cells between a first select transistor at a first end of the memory string and a second select transistor at a second end of the memory string, the first end of the memory string connected to a first control line , and the second end of the memory string connected to a second control line ; and a control circuit in communication with the stacked non-volatile memory cell array, the first control line and the second control line, the control circuit, to perform each erase iteration of a plurality of erase iterations of an erase operation for one or more memory cells of the memory string: drives a voltage of the first control line and a voltage of the first select transistor higher, such that the voltage of the first control line exceeds the voltage of the first select transistor by a sufficient margin to charge up a channel of the memory string by gate-induced drain leakage at the first select transistor, while a voltage of a control gate of each of the one or more memory cells initially floats and subsequently is driven lower, the voltage to which the first control line is driven increases in an erase iteration of the plurality of erase iterations according to a respective step size, and the voltage to which the first select transistor is driven increases in the erase iteration of the plurality of erase iterations according to a respective step size.