Patent ID: 8103924

Claim:
A processor comprising: a plurality of processor cores, wherein each of the plurality of processor cores is identical to one another, wherein each of the plurality of processor cores includes a scan chain having a plurality of serially-coupled scan elements; a pipelined test access mechanism (TAM) having a plurality of pipeline stages coupled together in a serial configuration, each of the plurality of pipeline stages corresponding to a unique one of the plurality of processor cores, wherein the pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel that is separate from the SDI channel, and a compare channel, wherein each of the plurality of pipeline stages includes a command register coupled to receive commands from upstream in the command channel, and further coupled to convey commands to a corresponding one of the plurality of processor cores and separately and concurrently convey commands downstream into the command channel, and wherein each of the plurality of pipeline stages is operable to: convey commands to its corresponding one of the plurality of processor cores via the command channel; convey scan input data to its corresponding one of the plurality of processor cores via the SDI channel; receive scan output data conveyed from its corresponding one of the plurality of processor cores, wherein the scan output data is conveyed to the SDO channel and the compare channel; and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.