Patent ID: 7459948

Claim:
A method for adjusting a phase of an output signal of a divider circuit including a state machine, the method comprising: receiving an input signal at an input of the divider circuit that receives one or more phase adjust control signals; when the one or more phase adjust control signals indicate no phase adjust, dividing the input signal by N utilizing N states of the state machine in the divider circuit to provide the output signal equal to the input signal divided by N, N being an integer greater than 2; in response to one of the one or more phase adjust signals indicating a phase adjust, implementing a phase adjust of the output signal by adjusting a number of states that occur in the state machine of the divider circuit; in response to the phase adjust being a phase decrement indication, implementing a phase decrement by bypassing at least one of the N states to generate one period of the output signal having N−1 or fewer input signal periods for the one period of the output signal; and in response to the phase adjust being a phase increment indication, implementing a phase increment by introducing at least one additional state to the N states for one period of the output signal to cause the output signal to have N+1 or more input signal periods for the one period of the output signal.