Patent ID: 8748859

Claim:
A non-volatile semiconductor memory, comprising: a substrate; a plurality of substantially parallel and substantially coplanar first conductors at a first height above the substrate, the first conductors elongated in a first direction; a plurality of substantially parallel and substantially coplanar rail stacks at a second height above the substrate, the rail stacks elongated in a second direction substantially orthogonal to the first direction, each rail stack including a second conductor and a first portion of a first diode component for a plurality of diodes associated with the rail stack; and a plurality of pillars formed between intersections of the plurality of first conductors and the plurality of rail stacks, the plurality of pillars including a first set of pillars formed at the intersection of a first rail stack and the plurality of first conductors, the first set of pillars each including a second portion of the first diode component for the plurality of diodes associated with the first rail stack, a second diode component and a state change element, the second diode component comprising heavily doped polysilicon of a first conductivity type, the first portion of the first diode component and the second portion of the first diode component comprising lightly doped polysilicon of a second conductivity type that is opposite to the first conductivity type.