Patent ID: 7268610

Claim:
A circuit for boosting the supply voltages of a CMOS switch for use in an integrated circuit designed using a sub-micron process, the circuit using voltage sources of V DD and V GND , comprising: a CMOS switch comprising a PMOS transistor coupled to a NMOS transistor, the CMOS switch comprising a PMOS gate, a NMOS gate, an input Vin and an output Vout; a first boosting circuit, separate from the NMOS transistor and coupled to the NMOS gate, the first boosting circuit providing a first capacitor ratio adapted to boost the voltage at the NMOS gate by the quantity (V DD +k 1 ×V DD ) in response to receiving first clocking signals, wherein k 1 comprises a factor determined in part by the first capacitor ratio; and a second boosting circuit, separate from the PMOS transistor and coupled to the PMOS gate, the second boosting circuit providing a second capacitor ratio adapted to reduce the voltage at the PMOS gate by the quantity (V GND −k 2 ×V DD ) in response to receiving second clocking signals, wherein k 2 comprises a factor determined in part by the second capacitor ratio; wherein the factors k 1 and k 2 allow sampling at Vout for values of Vin from V GND to V DD .