Patent ID: 7738498

Claim:
A system comprising: a memory configured to store a set of data records, wherein each of the data records is allocated to one packet stream in a set of packet streams; a digital phase-locked loop (PLL); an error calculation unit; an output timestamp generator; and a control unit configured to receive a channel indicator and a stream indicator for a current timestamp-bearing packet, generate an address based on the stream indicator and the channel indicator, and invoke a read operation from the memory based on the address, wherein the output timestamp generator is configured to (a) generate an output timestamp for the current timestamp-bearing packet equal to an expected timestamp provided by the memory as part of said read operation and (b) compute a delay count for the current timestamp-bearing packet based on a previous source frequency estimate provided by the memory as part of said read operation and on a received slot delay value; wherein the error calculation unit is configured to generate an error value and an error gradient value based on the delay count, the expected timestamp, an input timestamp and a previous error value provided by the memory as part of said read operation; wherein the digital PLL is configured to compute an updated source frequency estimate in response to receiving the error value, the error gradient value and the previous source frequency estimate.