Patent ID: 7525361

Claim:
A flip-flop comprising: a first PMOS transistor having a source to which a power supply voltage is connected and a gate to which input data is applied; a second NMOS transistor having a drain to which a drain of the first PMOS transistor is connected and a gate to which the input data is applied; a third NMOS transistor having a drain to which a source of the second NMOS transistor is directly connected, a gate to which a clock pulse signal is applied, and a source to which a ground voltage is directly connected; a first latch latching a logic level of a first node between the first PMOS transistor and the second NMOS transistor and a level of a second node between the second and third NMOS transistors in response to the clock pulse signal; a fourth PMOS transistor having a source to which the power supply voltage is connected and a gate to which the first node is connected; a fifth NMOS transistor having a drain to which a drain of the fourth PMOS transistor is directly connected and a gate to which the first node is directly connected; a sixth NMOS transistor having a drain to which a source of the fifth NMOS transistor is directly connected, a gate to which the clock pulse signal is connected, and a source to which the ground voltage is directly connected; and a second latch latching a logic level of a third node between the fourth PMOS transistor and the fifth NMOS transistor, the third node being connected to an input of the first latch to control an operation thereof, wherein a signal path is provided from the third node to the ground voltage, the signal path including the sixth NMOS transistor directly connected to the ground voltage, wherein the first latch comprises: a seventh PMOS transistor having a source to which the power supply voltage is connected and a gate to which the third node is connected; an eighth PMOS transistor having a source to which a drain of the seventh PMOS transistor is connected, a gate to which the clock pulse signal is connected, and a drain to which the first node is connected; and a ninth NMOS transistor having a drain to which the second node is connected, a gate to which the third node is connected, and a source to which the ground voltage is connected.