Patent ID: 7026849

Claim:
A reset circuit which includes a plurality of asynchronous modules and a plurality of synchronous modules from a first state to a last stage for executing desired functions, and initializes each of the pluralities of asynchronous and synchronous modules arranged in a semiconductor integrated circuit, comprising: input means for inputting a reset signal to initialize the plurality of asynchronous modules; and pulse generation means connected to the input means to generate a reset pulse based on the reset signal, wherein: the plurality of asynchronous modules include a first asynchronous module arranged at a first stage, which is connected to an output of the pulse generation means and receives the reset pulse to be initialized, and a second asynchronous module arranged at a next stage; the first asynchronous module has first control means for generating a first reset signal to initialize the second asynchronous module, and outputting the first reset signal to the second asynchronous module after initialization in the first asynchronous module; and the second asynchronous module has second control means which is connected to an output of the first asynchronous module, receives the first reset signal output from the first asynchronous module to be initialized, generates a second reset signal to initialize an asynchronous module arranged at a further next stage based on the first reset signal from the first asynchronous module, and outputs the second reset signal after initialization in the second asynchronous module, the reset circuit further comprising: clock input means for inputting a clock signal; third control means connected to the second asynchronous module to output, upon detection of the second reset signal, a control signal corresponding to the second reset signal for a period until a last delayed reset signal is input for a synchronous module of a last stage; and a plurality of delay means connected to the clock input means to delay an input signal in synchronization with the clock signal, and to output a delayed reset signal generated by the delaying, wherein: the plurality of synchronous modules are connected corresponding to the plurality of delay means, operated in synchronization with the clock signal, and initialized in synchronization with the clock signal based on the control signal and the delayed reset signal; and among the plurality of delay means, first delay means arranged at a first stage receives the control signal output from the third control means as the input signal, and each of second delay means arranged at stages thereafter receives the delayed reset signal output from delay means arranged at a previous stage as the input signal.