Patent ID: 7475191

Claim:
A processing unit for a multiprocessor data processing system, said processing unit comprising: a processor core; and a lower level cache including a reservation logic that records reservations of said processor core and that passes or fails store-conditional operations received from said processor core based upon whether said processor core has reservations for target store addresses of said store-conditional operations; wherein said processor core includes: a store-through upper level cache; a reservation register; sequencer logic that, by reference to said reservation register, fails a store-conditional operation without communication with said reservation logic; an instruction sequencing unit that fetches instruction for execution; a data register; at least one instruction execution unit coupled to said instruction sequencing unit, wherein the at least one instruction execution unit, responsive to receipt of a load-reserve instruction from said instruction sequencing unit, executes said load-reserve instruction to determine a load target address; wherein the processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing said store-through upper level cache utilizing said load target address to cause data associated with said load target address to be loaded from said store-through upper level cache into said data register and by establishing a reservation in said reservation logic of said lower level cache for a reservation granule including the load target address; and wherein, in response to said load target address hitting in said store-through upper level cache, said store-through upper level cache retains in a valid state in the store-through upper level cache a cache line containing the data associated with the load target address.