Patent ID: 7800940

Claim:
A semiconductor memory device comprising: a plurality of memory cells, each of which comprises a programmable resistance element that stores one of binary data as a first resistance state and the other of binary data as a second resistance state; and a data write control circuit performing on a memory cell designated by address information, a data write operation having first and second cycles, the data write operation being selected, in response to data currently stored into and data to be newly written into the memory cell, from a first combination of a first operation and a second operations which are carried out respectively in the first and second cycles, a second combination of the first operation and a third operation which are carried out respectively in the first and second cycles, a third combination of the third operation and the second operation which are carried out respectively in the first and second cycles and a fourth combination of the third operation which is carried out in each of the first and second cycles, the first operation being to supply the memory cell with a first set of signal voltages to cause the first resistance state, the second operation being to supply the memory cell with a second set of signal voltages to cause the second resistance state, and the third operation being to supply the memory cell with no signal voltages to cause no change in resistance state of the memory element.