Patent ID: 7910481

Claim:
A method for fabricating a semiconductor device, the method comprising: forming an interlayer dielectric layer having a plurality of contact holes over a substrate; forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer; performing a first main etch process to partially etch the conductive layer to form a first conductive layer; performing a second main etch process to etch the first conductive layer using an etch gas having a slower etch rate with respect to the first conductive layer than an etch gas used in the first main etch process until an upper surface of the interlayer dielectric layer is exposed to form a second conductive layer; and performing an over-etch process to etch a certain portion of the second conductive layer, and at the same time, to etch a certain portion of the interlayer dielectric layer to form a landing plug.