Patent ID: 7417317

Claim:
A chip structure comprising: a silicon substrate; a first I/O circuit in or on said silicon substrate, wherein said first I/O circuit comprises a first receiver; a second I/O circuit in or on said silicon substrate; a first ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first metallization structure over said silicon substrate and in said dielectric layer, wherein said first metallization structure comprises a first interconnecting structure over said silicon substrate and in said dielectric layer, a second interconnecting structure over said silicon substrate and in said dielectric layer, and a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first ESD circuit, wherein said second interconnecting structure is connected to said first I/O circuit, and wherein said third interconnecting structure is connected to said second I/O circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers; and a second metallization structure over said passivation layer, wherein said first ESD circuit is connected to said first and second I/O circuits through said second metallization structure, wherein said first ESD circuit is connected to said first I/O circuit through, in sequence, said first interconnecting structure, said second metallization structure and said second interconnecting structure, and wherein said first ESD circuit is connected to said second I/O circuit through, in sequence, said first interconnecting structure, said second metallization structure and said third interconnecting structure.