Patent ID: 7948496

Claim:
A processor comprising: a first data path having a first bit width; a bus interface unit; a first cache memory coupled to the first data path and to the bus interface unit; a second data path having a second bit width greater than the first bit width; a plurality of third data paths having a combined bit width less than the second bit width; a first wide operand storage coupled to the first data path and to the second data path for storing a first wide operand received over the first data path, the first wide operand having a size with a number of bits greater than the first bit width; a register file including registers having the first bit width, the register file being connected to the first data path and the third data paths, and including storage for a wide operand specifier which specifies an address of the first wide operand; an access unit, including an instruction fetch queue, coupled to the register file; an execute instruction queue coupled to the access unit and to the first cache memory for presenting to the register file instructions and data; and a first functional unit capable of initiating instructions, the first functional unit coupled by the second data path to the first wide operand storage and coupled by the third data paths to the register file.