Patent ID: 7793129

Claim:
A memory management method performed in a computer having at least one processor which executes basic system software, firmware and application software, a memory which is a storage area, and a memory controller coupled to the memory, wherein: the memory controller controls a memory addressing which defines an address in the memory, a memory access from the processor to the memory and a memory power state, the memory storage area is an area which can be assigned to the basic system software, the firmware and the application software, the storage area is divided into memory ranks which are units whose power can be independently controlled by the memory controller, a supplied power state of the memory is controlled, for each memory rank, to one of an active state in which the storage area included in the memory rank can be accessed from the processor, and an inactive state in which access from the processor to the storage area is delayed; the basic system software prevents fragmentation in which the allocated storage area spans a plurality of memory ranks, puts the power state of a memory rank which does not include the allocated storage area into the inactive state via the memory controller, and puts the power state of a memory rank which includes a storage area required for the allocation first into the active state, and the basic system software calculates a prediction value of an allocation area, and puts the power state of the memory rank into the active state first based on the predicted value.