Patent ID: 8692324

Claim:
A semiconductor device, comprising: a semiconductor layer having lower and upper surfaces; a first contact formed in or on said semiconductor layer; a second contact comprising: a vertical drain contact region of a first conductivity type formed in said semiconductor layer proximate the upper surface thereof and spaced from said first contact by an enhanced drain drift region of said first conductivity type formed in said semiconductor layer; a charge control implant region of a second conductivity type formed in said semiconductor layer under said enhanced drain drift region; an insulator layer formed over said semiconductor layer; and a charge control electrode formed over said insulator layer and spaced from the upper surface of said semiconductor layer by said insulator layer, the charge control electrode extending laterally over substantially all of said enhanced drain drift region, wherein a net charge across at least a portion of the enhanced drain drift region is substantially charge balanced with the charge control implant region and the charge control electrode, and wherein a conduction current is conveyed through a resistance path through the vertical drain contact region.