Patent ID: 8018067

Claim:
An electrically shielded Through-Wafer Interconnect, comprising: a wafer; a first through-wafer interconnect structure; and a second through-wafer interconnect structure; wherein the second through-wafer interconnect structure, thereby having a coincident axis, and completely surrounding the first through-wafer interconnect structure in a plane perpendicular to the coincident axis is coaxially arranged around the first through-wafer interconnect structure and wherein the wafer comprises a Complementary Metal Oxide Semiconductor structure with a first metallic region; wherein the first through-wafer interconnects structure is connected to the first metallic region of the Complementary Metal Oxide Semiconductor structure; wherein the second through-wafer interconnect structure is connected to a second metallic region of the Complementary Metal Oxide Semiconductor structure; wherein the first through-wafer interconnect structure has a first depth; and wherein the second through-wafer interconnect structure has a second depth which is smaller than the first depth.