Patent ID: 7898039

Claim:
A nonvolatile memory device, comprising: a semiconductor substrate including device isolation regions thereon defining an active region therebetween; a plurality of selection gates comprising a string selection gate and a ground selection gate on the active region of the substrate; a plurality of memory cell gates on the active region between the string selection gate and the ground selection gate; first impurity regions extending into the active region to a first depth in portions of the active region between ones of the plurality of memory cell gates and in portions of the active region between the plurality of memory cell gates and the plurality of selection gates; and second impurity regions extending into the active region to a second depth greater than the first depth in the portions of the active region between the plurality of memory cell gates and the plurality of selection gates, wherein an entirety of a surface of the active region extending from first and last ones of the plurality memory cell gates to ones of the plurality of selection gates immediately adjacent thereto is coplanar with a surface of the active region including the plurality of memory cell gates thereon, and wherein the first impurity regions have a greater impurity concentration than the second impurity regions.