Patent ID: 7569434

Claim:
A method of manufacturing a PFET on a substrate, comprising: forming a gate channel region of the PFET having a first thickness on the substrate; and forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate; wherein the at least one composite source/drain diffusion region causes a strain in the gate channel region; wherein significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET; wherein forming the gate channel region having the first thickness and forming at least one composite source/drain diffusion region having the second thickness greater than the first thickness includes forming a silicon-on-insulator (SOI) layer on the substrate; and a portion of the SOI layer in the at least one composite source/drain diffusion region is deeper than the SOI layer in the gate channel region.