Patent ID: 7546400

Claim:
Data packet buffering system comprising a data buffer for buffering data packets received from an input device on an input bus and providing data packets to an output device on an output bus, a buffer occupancy monitoring unit for monitoring a buffer occupancy determined by the analysis of write clock signals from said input device and read clock signals from said output device, a buffer management logic unit providing write grant signals to said input device when data may be read from said data buffer and sent to said output device, and a threshold determining unit providing a minimum threshold of the buffer occupancy, read grant signals being determined by comparison between a real buffer occupancy and said minimum threshold; said system being characterized in that said threshold determining unit comprises: a first counter preloaded with a data packet size and decremented at each read clock signal of a number of logical units corresponding to a width of said output bus, a second counter preloaded with the data packet size and decremented at each write clock signal of a number of logical units corresponding to a width of said input bus, the decrementation of said second counter being started at the same time as the decrementation of said first counter by a start counter signal, and a threshold unit for determining said minimum threshold from contents of said second counter when said first counter has reached zero and providing said minimum threshold to said buffer management logic unit, wherein the decrementation of said first counter and said second counter is stopped when the contents of said first counter reach zero, the count out reached by said second counter at this time being used as a theoretical threshold by said threshold unit for determining said minimum threshold.