Patent ID: 7622966

Claim:
A phase locked loop ( 12 ) with a controllable oscillator (DCO) for generating an output clock (CKout) of the phase locked loop and with a switch-over device ( 22 ) for switching over between a first clock signal (Ckin 1 ) and a second clock signal (CKin 2 ) for use as an input clock of the phase locked loop, comprising: (a) at least two phase detectors (PD 1 , PD 2 ) which can be switched between different operating modes are provided respectively for the at least two input clock signals (Ckin 1 , CKin 2 ), such that the phase detector (PD 1 or PD 2 ) for the clock signal (CKin 1 or CKin 2 ) currently being used as the input clock is put into a first operating mode and the phase detector (PD 2 or PD 1 ) for the clock signal (CKin 2 or CKin 1 ) currently not being used as the input clock is put into a second operating mode, (b) each phase detector (PD 1 , PD 2 ) in the first operating mode determines a first-mode phase difference between the clock signal (CKin 1 or CKin 2 ) currently being used as the input clock and the output clock (CKout) and provides the first-mode phase difference for the control of the oscillator (DCO) to generate the output clock (CKout) and, (c) each phase detector (PD 2 , PD 1 ) in the second operating mode determines a frequency difference between the clock signal (CKin 2 or Ckin 1 ) currently not being used as the input clock and the output clock (CKout), such frequency difference being stored and continuously updated and provided as a frequency adaptation control signal (INT_OUT) for the control of the oscillator (DCO) after the switch-over to this clock signal (CKin 2 or CKin 1 ) previously not being used as the input clock, so that any frequency jump during switch-over produces, by means of the frequency adaptation control signal (INT_OUT), a substantially immediate corresponding frequency adjustment of the oscillator (DCO), wherein each of the at least two phase detectors (PD 1 , PD 2 ) has an integrator ( 41 ) responsive to a second-mode phase difference between the clock signal (CKin 2 or Ckin 1 ) currently not being used as the input clock and the output clock (CKout) to generate the frequency adaptation control signal (INT OUT), and wherein the second-mode phase difference inputted into the integrator ( 41 ) is provided as an output signal (PD OUT) of a phase comparison device ( 32 ), which compares the phase of the clock signal (CKin 2 or Ckin 1 ) currently not being used as the input clock with a phase-shift adjusted version (CK<1:8>) of the output clock (CKout), the phase shift of the phase-shift adjusted version (CK<1:8>) of the output clock (CKout) being adjusted on the basis of the frequency adaptation control signal (INT OUT) from the integrator ( 41 ).