Patent ID: 8571822

Claim:
A method, comprising: selecting a series of at least three tests of an integrated circuit; performing, using the integrated circuit, the selected series of at least three tests on the integrated circuit, each test comprising: selecting two nodes among at least three taking nodes for taking clock signals, from the integrated circuit; taking two clock signals at the two selected taking nodes during a test duration; detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration; and determining from numbers of events counted, a test result proportional to a sum of jitter variances of the two clock signals taken during the test duration, wherein a set of two nodes selected during one of the series of tests is different from a set of two nodes selected during another one of the series of tests; and determining, using the at least one processing device of the integrated circuit, a jitter variance of each clock signal taken during the series of tests using a matrix calculation based on the results of the series of tests.