Patent ID: 8895379

Claim:
A method to fabricate a transistor device, comprising: depositing raised source drain structures adjacent to a gate stack disposed on a surface of a semiconductor material, the gate stack comprised of a gate conductor and having a gate spacer; forming a trench through a top surface of each raised source drain structure; depositing metal to cover sidewalls and a bottom of at least a portion of each trench; siliciding the deposited metal; depositing a layer of field dielectric over the gate stack and the raised source drain structures; opening apertures through the layer of field dielectric at contact locations, the apertures extending to the silicided metal at the bottom of each trench and exposing the silicided trench sidewalls; and depositing contact metal into the apertures to be in electrically conductive contact with the silicided metal at the bottom of each trench and the silicided trench sidewalls, where the contact metal is deposited to have one of tensile stress or compressive stress, where the layer of field dielectric is deposited to have one of tensile stress or compressive stress, and where the layer of field dielectric is deposited to have tensile stress when the contact metal is deposited to have tensile stress, and where the layer of field dielectric is deposited to have compressive stress when the contact metal is deposited to have compressive stress.