Patent ID: 6977535

Claim:
A differential current output unit, comprising: a difference input circuit that includes a first constant current source for providing a first constant current, a first and a second differential amplification transistors for amplifying an inputted differential voltage so as to distribute said first constant current among said differential amplification transistors, a first current mirror source transistor for generating a first voltage proportional to a first current flowing through said first differential amplification transistor, and a second current mirror source transistor for generating a second voltage proportional to a second current flowing through said second differential amplification transistor; a current subtraction circuit that includes a first mirror transistor for flowing therethrough a first mirror current that is M times said first current I 1 in response to said first mirror source voltage, with M being a first predetermined mirror ratio, and a second mirror transistor for flowing therethrough a second mirror current that is M times said second current I 2 in response to said second mirror source voltage, wherein said subtraction circuit is adapted to output a difference current that is the difference between said first mirror current and second mirror current; a delivery circuit for generating a current output instruction signals in accord with the magnitude of said difference current and for delivering said current output instruction signals in accord with the polarity of said difference current; and a current output circuit having a multiplicity of output transistor circuits each including a third mirror source transistor that is enabled by one of said current output instruction signals and a third mirror target transistor for flowing therethrough an output current that is N times the current flowing through said third mirror source transistor, with N being a second predetermined mirror ratio, wherein said current output circuit is adapted to supply an output current to a load in a positive or a negative direction in accord with the polarity and the magnitude of said current instruction signals.