Patent ID: 7304492

Claim:
An inspecting circuit layout, adapted for inspecting at least one of panel units, each of the panel units having a plurality of first signal lines and a plurality of second signal lines, the inspecting circuit layout comprising: a first multiplexer (MUX), electrically connected with the first signal lines of the panel units; a first inspecting pad, electrically connected to the first MUX, wherein the first MUX is adapted for selectively connecting the first inspecting pad with the first signal lines of a group of panel units; and a first refresh signal supplying unit, electrically connected to the first MUX; wherein the first MUX comprises: a plurality of first control transistors, each of the first control transistors comprising a drain electrode electrically connected with the first inspecting pad, and a source electrode thereof electrically connected with the first signal lines of the corresponding group of panel units; and a plurality of first refresh transistors, each of the first refresh transistors comprising a source electrode electrically connected between the source electrode of a corresponding first control transistor and the first signal lines, and a drain electrode electrically connected to the refresh signal supplying unit.