Patent ID: 8629019

Claim:
A method for providing self aligned contacts in a semiconductor device having an active area and a gate bus area comprising: forming an oxide layer on a substrate of said semiconductor device; forming a hard mask of silicon nitride on said oxide layer; etching said hard mask of silicon nitride to form trenches in said active area and said gate bus area in said substrate wherein said hard mask of silicon nitride is deposited on said oxide layer; forming a gate oxide layer on walls of said trenches; applying polysilicon to fill said trenches and to cover the surface of said hard mask of silicon nitride; removing said polysilicon from the surface of said hard mask of silicon nitride; forming and recessing polysilicon plugs in trenches that are located in said active area to form recesses above said polysilicon plugs while leaving the polysilicon coplanar with the hard mask of silicon nitride on the gate bus area; and selectively etching said hard mask of silicon nitride and forming flat, wholly planar surfaced oxide buttons to cover said trenches that are located in said active area.