Patent ID: 8354741

Claim:
A lead frame comprising: a die pad comprising first and second surfaces, at least one of the first and second surfaces being provided for installing a semiconductor chip thereon; at least one lead pattern formed around a circumference of the die pad, the lead pattern comprising first and second surfaces; an insulating material filling a space interposed between the die pad and the lead pattern and structurally supporting the die pad and the lead pattern; and pre-plating layers formed on the first surface of the die pad and the first surface of the lead pattern, the second surface of the die pad and the second surface of the lead pattern, or both the first and second surfaces of the die pad and the lead pattern, wherein the first surface of the die pad and the first surface of the lead pattern are electrically separated by the insulating material filling the space, and the second surface of the die pad and the second surface of the lead pattern are electrically separated by the insulating material filling the space, wherein, top surfaces of the pre-plating layers and a top surface of the insulating material filled in the space are disposed on a same plane, and wherein, bottom surfaces of the pre-plating layers and a bottom surface of the insulating material filled in the space are disposed on a same plane.