Patent ID: 8772754

Claim:
A semiconductor storage device comprising: a plurality of first wirings disposed in parallel; a plurality of second wirings disposed to intersect the first wirings; a memory cell array including a memory cell, the memory cell being disposed at each intersection of the first wiring and the second wiring and having a first electrode, a rectifying element, a second electrode, a variable resistor, and a third electrode connected in series; and an interlayer insulating film deposited on the memory cell array, the interlayer insulating film being made of a first insulating material, the memory cell array including: a stopper film between the third electrode and the first wiring, the stopper film being made of a first metallic material and having a polishing rate different from that of the interlayer insulating film; an adjustment film, the adjustment film being made of nitride of the first metallic material and being in contact with the first wiring; and a block film between the interlayer insulating film and the first wiring, the block film containing nitride of the first insulating material, an undersurface of the block film being higher than an undersurface of the stopper film, and the stopper film being made of tungsten.