Patent ID: 8273608

Claim:
A method of forming a semiconductor wafer comprising: forming a trace structure and a target structure to touch a passivation layer, the trace structure and the target structure each having a top surface and each including copper, the target structure having a side wall, touching a top surface of the passivation layer, and being electrically isolated from all other conductive structures, the passivation layer being non-conductive; forming a non-conductive structure to touch the passivation layer, the trace structure, and the target structure, the non-conductive structure exposing the top surface of the trace structure and the top surface of the target structure; etching the non-conductive structure to form a passivation opening that exposes the top surface of the passivation layer; wherein the passivation opening exposes the side wall of the target structure; also wherein forming the trace structure and the target structure includes forming a trace member and a target member to touch the passivation layer, the trace member and the target member each having a top surface and each including copper, the target member touching the top surface of the passivation layer; and forming the non-conductive structure includes planarizing the nonconductive structure to expose the top surface of the trace member and the top surface of the target member.