Patent ID: 8589606

Claim:
A physical layer circuit of a differential serial communication device, comprising: a differential input terminal that receives a differential serial signal from a communication counterpart, and outputs the received differential serial signal; a conversion unit that is connected to the differential input terminal and converts an output from the differential input terminal into a predetermined number of bits of parallel data, ON/OFF of a power supply of the conversion unit being controlled by a power supply control signal from an upper layer; a first detection circuit that is connected to the differential input terminal and detects a connection recognition signal indicating a start of communication, from the output from the differential input terminal, the first detection circuit outputting a first control signal for allowing the upper layer to output the power supply control signal for turning on the power supply of the conversion unit, upon detecting the connection recognition signal; a second detection circuit that is connected to the conversion unit and detects presence or absence of reception of the differential serial signal at the differential input terminal by detecting whether the predetermined number of bits of the parallel data obtained by the conversion unit has a bit configuration indicative of the presence or absence of the reception of the differential serial signal at the differential input terminal, the second detection circuit outputting a second control signal for allowing the upper layer to output the power supply control signal for turning off the power supply of the conversion unit, upon detecting the absence of the reception; and a control circuit that turns off a power supply of the first detection circuit when the second detection circuit detects the presence of the reception, and turns on the power supply of the first detection circuit when the second detection circuit detects the absence of the reception.