Patent ID: 7656211

Claim:
A dynamic floating input D flip-flop (DFIDFF), comprising: a floating input stage, for transmitting an input data to an output end thereof at a pre-charge period; a latch stage, comprising: a first string of transistors, having an input node coupled to the output end of the floating input stage, for pre-charging an output node of the first string transistors to a first level at the pre-charge period, and storing the logic status of the input data at the pre-charge period; at an evaluation period, the first string of transistors deciding the output node level of the first string of transistors in accordance with the input data logic status stored therein; and a second string of transistors, having an input node coupled to the output node of the first string of transistors and an output node providing a first output signal of the DFIDFF, and at the evaluation period, the second string of transistors deciding the output node level of the second string of transistors in accordance with the logic status of the output node of the first string of transistors; and a first NOT gate, wherein an input end of the first NOT gate is coupled to the output node of the second string of transistors, and an output end of the first NOT gate provides a second output signal of the DFIDFF, wherein the floating input stage comprises a switch, a first end of the switch receives the input data, a second end of the switch serves as the output end of the floating input stage, the switch is turned on at the pre-charge period, the switch is turned off at the evaluation period, and the switch comprises: a second NOT gate, having an input end receiving a clock signal; and an N-type transistor, wherein a source and a drain of the N-type transistor are respectively served as the first end and the second end of the switch, and a gate of the N-type transistor is coupled to the output end of the second NOT gate.