Patent ID: 8620243

Claim:
A receiver for receiving signals from plural frequency bands and plural communication protocols, comprising: an interchangeable radio frequency (â€œRFâ€) front end having an analog-to-digital (â€œA/Dâ€) converter and an electrically erasable programmable read-only memory (â€œEEPROMâ€) having calibration data, wherein said RF front end receives RF signals from said plural frequency bands and said plural communication protocols; intermediate frequency (â€œIFâ€) circuitry producing one or more common IF signals from said received RF signals and digitizing said one or more common IF signals; a common digital back end for receiving digitized versions of said IF signals and modifying IF signal bandwidth as a function of said plural communication protocols, said back end having: a host processor operatively connected to a host memory device via a host bus, one or more digital signal processors (â€œDSPâ€) each operatively connected to at least one DSP memory device via a cluster bus, and a field programmable gate array (â€œFPGAâ€) operatively connected to said host processor, said one or more DSPs, a mezzanine bus, and said IF circuitry, wherein said FPGA receives said IF signal, determines a destination for said signal for processing where said destination is one of said one or more DSPs or said host processor, and sends said IF signal to said determined destination; a global positioning system (â€œGPSâ€) receiver or a timing synchronization source for supplying timing signals to said RF front end and said common digital back end; and a flash memory device operatively connected to said host bus for supplying configuration information.