Patent ID: 7719877

Claim:
A memory cell array comprising: a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells disposed at intersecting points of the word lines and the bit lines, each of the memory cells including a select MOS transistor and an information charge storage capacitor, the select MOS transistor having a gate electrode connected to a word line, a source electrode, and a drain electrode, one of the source electrode and the drain electrode being connected to a bit line, the other of the source electrode and the drain electrode being connected to one electrode of the information charge storage capacitor, the other electrode of the information charge storage capacitor being connected to a common plate line; sense amplifiers respectively connected to the bit lines; a device which changes a voltage of the common plate line from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state; and a device which changes a voltage of the word line into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and which changes the voltage of the common plate line from the second voltage to the first voltage after the voltage of the word line has been changed into the fourth voltage.