Patent ID: 7974130

Claim:
A semiconductor memory device comprising: a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed for coupling the both ends of the NAND cell unit to a bit line and a source line, respectively, and a dummy cell disposed adjacent to at least one of the first and second select gate transistors, and a sequence controller configured to control the memory cell array such that prior to erasing the memory cells and the dummy cell in an erase unit, at least the dummy cell is subject to pre-program for boosting threshold voltage thereof as a part of an erase sequence, and after erasing the memory cells and the dummy cell in the erase unit, the memory cells are applied with a first program voltage to be subject to soft-program, and the dummy cell is applied with a first program pass voltage lower than the first program voltage as part of the erase sequence, and after the erase sequence, a selected memory cell in the memory cells is applied with a second program voltage to be subject to program, non-selected memory cells in the memory cells are applied with a second program pass voltage lower than the second program voltage, and the dummy cell is applied with a third program pass voltage lower than the second program pass voltage.