Patent ID: 7650481

Claim:
A memory system, comprising: a memory; a memory controller configured to generate a plurality of control signals to access the memory, the memory controller further being configured to adjust the timing between the control signals to change memory access speed to a first access speed if a number of commands in a command queue of the memory system rises above a first threshold and to a second access speed if the number of commands in the command queue drops below a second threshold; and wherein the number of commands in the command queue is related to the demand on the memory, and the memory access speed is further a function of the temperature of the memory system; the memory controller further comprising: a multiplexer that selects a delay value based on the demand on the memory and the temperature of the memory system; a timing parameter register that stores a timing parameter value; an adder that sums the delay value and the timing parameter value; a row access strobe generated by the memory controller that loads a counter with a resultant sum; the counter counts down with each clock cycle the resultant sum until the counter reaches zero; and logic that generates a column access strobe that is provided to the memory when the counter reaches zero.