Patent ID: 8493122

Claim:
A voltage clamping circuit for an input/output (I/O) pin of an integrated circuit, the voltage clamping circuit comprising: a first transistor having a drain terminal connected to the I/O pin and a gate terminal that receives a first voltage, wherein the first transistor generates a first intermediate signal based on an input signal provided at the I/O pin when a magnitude of the input signal exceeds a predetermined threshold; a voltage detection circuit, connected to a source terminal of the first transistor, for detecting a voltage thereon and generating a second intermediate signal having a magnitude equal to at least one of the first voltage and a second voltage; a second transistor having a gate terminal connected to the voltage detection circuit, a drain terminal connected to the source terminal of the first transistor, and a source terminal that receives the second voltage, wherein the second transistor generates a third intermediate signal based on the first and second intermediate signals; and a third transistor having a drain terminal that receives the first voltage, a source terminal connected to a node between the source and drain terminals of the first and second transistors, respectively, and a gate terminal connected to the I/O pin, wherein the third transistor provides the first voltage to the node during a nominal operation of the I/O pin.