Patent ID: 7106566

Claim:
A power interface circuit for coupling an adapter output voltage from an adapter unit to a system power input of a system comprising: switch circuitry for coupling said adapter output voltage to a said system power input in response to a first logic state of a first control signal; a reference circuit for generating first and second reference voltages and a start timer signal in response to a polarity signal generated from said adapter output voltage; a first timer circuit generating a first timer signal in response to a first logic state of said start timer signal, wherein said first timer output has a first logic state for a first time interval and a second logic state after said first time interval ends; a second timer circuit generating a second timer signal in response to said first logic state of said start timer signal, wherein said second timer output has a first logic state for a second time interval and a second logic state after said second time interval ends; circuitry for generating a power correct signal in response to said first and second reference voltages, a sense voltage corresponding to said adapter output voltage, and said first timer signal, said power correct signal having a first logic state if said adapter output voltage is within a voltage range set by said first and second reference voltages and said second timer signal has said second logic state; and logic circuitry receiving said power correct signal, said first timer signal, said second timer signal, and generating said first control signal and an out of range signal, wherein said first control signal has said first logic state if said out of range signal has a first logic state and said second timer signal has said second logic state.