Patent ID: 6838310

Claim:
A method of forming a semiconductor device interconnect comprising the steps of: providing a first semiconductor die, said die having a top surface, a bottom surface, and a plurality of side surfaces; and providing an electronic circuit located on a top surface of said die; and providing a plurality of input/output (I/O) interconnects physically located on one or more of said plurality of side surfaces; providing a plurality of I/O signal lines, each of said I/O signal lines being coupled to one or more of said plurality of said I/O interconnects; inserting said die into a mating receptacle adapted for said die, said mating receptacle including a plurality of mating interconnects adapted to form a frictional contact with corresponding ones of said plurality of I/O interconnects when said die is physically forced into said mating receptacle, so as to form a signal interconnect between said electronic circuit and a second electronic circuit which is not originally formed to be electrically connected to said semiconductor die; and wherein said signal interconnect is formed without the use of soldering, or any additional temperature treatments, including reflow.