Patent ID: 8370782

Claim:
A computer implemented method for buffer-aware routing in a design of an integrated circuit having cells, the circuit including buffers and wires, the computer implemented method comprising: receiving a route from a set of routes, the route coupling a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point; determining, using a processor and a memory, whether the route violates a set of hard constraints for a part of the circuit, wherein the set of hard constraints includes a reach length constraint, wherein the reach length constraint is a constraint on a length of routes between any two points in the circuit such that the slew and timing characteristics of a signal over a given route meets a design specification for slew and delay for the signal in the design; and selecting, responsive to the route not violating any hard constraint in the set of hard constraints, the route as a buffer-aware routing solution between the first and the second points in the circuit.