Patent ID: 8171210

Claim:
A semiconductor memory, comprising: a plurality of memory cores having memory cells; and an operation control circuit starting a first operation of any of the memory cores in response to a first operation command, starting a second operation of any of the memory cores in response to a second operation command, and terminating the first operation and disabling a termination of the second operation in response to a termination command to terminate operations of the plurality of memory cores during execution of both the first operation and the second operation, wherein the operation control circuit includes an access control circuit in each of the memory cores, and wherein the access control circuit each includes: an activation circuit activating an access signal in response to the first or second operation command to start the first operation or the second operation of a corresponding memory core; an inactivation circuit inactivating the access signal in response to the termination command to terminate the first operation when the corresponding memory core executes the first operation; an inactivation disable circuit disabling an inactivation of the access signal in response to the termination command to terminate the second operation when the corresponding memory core executes the second operation; and a disable invalidating circuit invalidating a disable operation of the inactivation disable circuit to terminate the second operation in response to the termination command when a mask signal is received.