Patent ID: 8782348

Claim:
An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level cache memory to a higher-level cache memory in the hierarchy, the apparatus comprising: an eviction status array, separate accessible from a tag array of the lower-level cache memory; wherein the tag array stores address tags for corresponding cache lines of the lower-level cache memory; wherein the eviction status array comprises an array of storage elements; wherein each of the tag array and eviction status array are accessed by an index portion of memory address; and an eviction engine, configured to move the cache line from the lower-level cache memory to the higher-level cache memory; wherein each storage element of the eviction status array is configured to store an indication for a corresponding cache line stored in the lower-level cache memory, wherein the indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level cache memory to the higher-level cache memory.