Patent ID: 7268050

Claim:
A method for fabricating a MOS transistor in a semiconductor device, comprising: subjecting a surface of a semiconductor substrate to thermal oxidation to form an oxide film; depositing a polysilicon layer on the oxide film; applying a coat of photoresist onto the polysilicon layer, and performing exposure and development using an exposure mask which defines a gate, to form a photoresist pattern covering a region of the polysilicon layer; dry etching the portions of the polysilicon layer and portions of the oxide film that are not protected by the photoresist pattern, to form a gate pattern and to expose surfaces of the semiconductor substrate adjacent to the gate pattern; annealing the semiconductor substrate in an environment including a nitrogen- and oxygen-containing gas to form a nitrided oxide film over the gate pattern and the exposed surfaces of the semiconductor substrate; forming buried lightly doped impurity ion layers on opposite sides of the gate pattern; depositing an insulating layer on the nitrided oxide film to cover the gate pattern and etching back the insulating layer to form sidewall spacers; forming buried heavily doped impurity ion layers in the semiconductor substrate at exposed active regions using the gate pattern and the sidewall spacers as an ion injection mask; and annealing the semiconductor substrate to diffuse impurity ions and form source/drain junctions and form lightly doped impurity diffusion regions.