Patent ID: 8536574

Claim:
A thin film transistor array panel, comprising: a substrate comprising a display area and a peripheral area; a gate line disposed on the substrate; a gate driver disposed in the peripheral area of the substrate to supply a gate signal to the gate line; a gate pad disposed on the substrate connecting the gate line to the gate driver; a gate insulating layer disposed on the gate line and the gate pad; a data line disposed on the gate insulating layer and comprising a source electrode; a drain electrode facing the source electrode; a height controlling member disposed on the gate insulating layer and in a location corresponding to the gate pad; a passivation layer disposed on the gate insulating layer, the data line, the drain electrode, the gate pad, and the height controlling member; an insulating layer disposed on the passivation layer; a pixel electrode disposed on the insulating layer and connected to the drain electrode; and a contact assistant connected to the gate pad and the height controlling member, wherein the height controlling member is disposed between the gate insulating layer and the contact assistant.