Patent ID: 8755244

Claim:
A multi-port memory cell of a multi-port memory array, wherein the multi-port memory cell is written using a plurality of write word lines and a plurality of write bit lines, comprising: a storage circuit comprising: a first inverter having an input and an output, wherein the first inverter is disabled by a first subset of the plurality of write word lines; and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines; a first selection circuit having data inputs coupled to a first subset of the plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter; and a second selection circuit having data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.