Patent ID: 8559252

Claim:
A memory testing device with cross interconnection of multiple drivers comprising: a first wiring bus and a second wiring bus connected to a first device area; a third wiring bus and a fourth wiring bus connected to a second device area; a first I/O driver module connected to the first wiring bus through a first driving bus, wherein the fourth wiring bus is Y-shaped connected to a node between the first driving bus and the first wiring bus; a first terminator bus connected to the first driving bus through a first grounding bus; a second I/O driver module connected to the third wiring bus through a second driving bus, wherein the second wiring bus is Y-shaped connected to a node between the second driving bus and the third wiring bus; and a second terminator bus connected to the second driving bus through a second grounding bus, wherein each of a first DUT for being mounted on the first device area and a second DUT for being mounted on the second device area has a plurality of first I/O pins and a plurality of second I/O pins, wherein the first I/O pins of the first DUT connected with the first wiring bus are different from the second I/O pins of the second DUT connected with the fourth wiring bus in pin definitions, wherein the first wiring bus and the fourth wiring bus are connected to the first I/O driver module, and wherein the second I/O pins of the first DUT connected with the second wiring bus are different from the first I/O pins of the second DUT connected with the third wiring bus in pin definitions, wherein the second wiring bus and the third wiring bus are connected to the second I/O driver module.