Patent ID: 7109537

Claim:
A pixel circuit, comprising: a P − silicon substrate; an N − well formed in said P − silicon substrate, wherein said N − well formed in said P − silicon substrate forms a PN junction which can accumulate signal-generated charge; a first P + region, a second P + region, and a third P + region formed in said N − well; a first PMOS transistor having a source, a drain, and a channel formed in said N − well, wherein said first P + region forms said source of said first PMOS transistor, said second P + region forms said drain of said first PMOS transistor, and that part of said N − well between said first P + region and said second P + region forms said channel of said first PMOS transistor; a second PMOS transistor having a source, a drain, and a channel formed in said N − well, wherein said third P + region forms said source of said second PMOS transistor, said second P + region forms said drain of said second PMOS transistor, and that part of said N − well between said second P + region and said third P + region forms said channel of said second PMOS transistor; a first gate electrode formed over a gate oxide over said channel of said first PMOS transistor forming the gate of said first PMOS transistor; a second gate electrode formed over a gate oxide over said channel of said second PMOS transistor forming the gate of said second PMOS transistor; a first NMOS transistor having a drain connected to a first output node, a gate, and a source connected to said source of said first PMOS transistor; a first N + region formed in said N − well; a second NMOS transistor having a source connected to said first N + region formed in said N − well, a drain connected to said gate of said first NMOS transistor, and a gate connected to said source of said first NMOS transistor; a third NMOS transistor having a drain connected to a second output node, a gate, and a source connected to said source of said second PMOS transistor; a second N + region formed in said N − well; and a fourth NMOS transistor having a source connected to said second N + region formed in said N − well, a drain connected to said gate of said third NMOS transistor, and a gate connected to said source of said third NMOS transistor.