Patent ID: 7268040

Claim:
A method of manufacturing a select transistor in a NAND flash memory, comprising: providing a first graph showing a relation between gate widths of a select transistor and leakage currents of the select transistor, and a second graph showing a relation between ion implant doses for controlling a threshold voltage of a memory cell arid the leakage currents of the select transistor; reading a first leakage current as a first gate width of the select transistor that is currently being used in the first graph; reading a first ion implant dose for controlling the threshold voltage of the memory cell as the first leakage current of the select transistor in the second graph; reading a second leakage current of the select transistor to meet the first ion implant dose of the memory cell in the second graph; reading a second gate width of the select transistor as the second leakage current of the select transistor in the first graph; increasing the first gate width of the select transistor to the second gate width of the select transistor; and applying the first ion implant dose to the memory cell.