Patent ID: 8144529

Claim:
A memory device comprising: a delay locked loop (DLL) circuit comprising: a delay line to receive an input clock signal and to generate an output clock signal; and a feedback circuit coupled to the delay line, the feedback circuit comprising: a phase detector coupled to the delay line to detect a phase difference between the input clock signal and the output clock signal and to generate a phase output corresponding to the phase difference; and a control logic coupled to the phase detector and the delay line to receive the phase output from the phase detector and to generate a control signal corresponding to the phase output, wherein the feedback circuit is to adjust a delay interval with the control signal to align the clock phase of the output clock signal to the clock phase of the input clock signal, and wherein the adjusted delay interval is to be locked onto the delay line; and wherein the entire feedback circuit is to be powered down after the delay interval is locked onto the delay line, and wherein the feedback circuit is to be powered on to re-align the clock phase of the output clock signal to the clock phase of the input clock signal.