Patent ID: 8300492

Claim:
A memory, comprising: a memory cell array, having a plurality of first and last bit lines, wherein the first bit lines are disposed at a side of the memory cell array, and the last bit lines are disposed at another side of the memory cell array; a word line decoder, coupled to the memory cell array, for generating a pre-word line signal and a word line signal; a first reference bit line generator, coupled to the first bit lines of the memory cell array, for detecting a voltage level variation of the first bit lines according to the pre-word line signal, so as to generate a first cut-back signal; and a second reference bit line generator, coupled to the last bit lines of the memory cell array, for detecting a voltage level variation of the last bit lines according to the pre-word line signal, so as to generate a second cut-back signal, wherein the first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits back the first and the second cut-back signals to the word line decoder, and the word line decoder generates the word line signal according to the received first and second cut-back signals and the pre-word line signal.