Patent ID: 7057948

Claim:
A semiconductor memory device comprising: at least one memory block including a plurality of memory cells and a plurality of spare cells, and having a redundancy function of replacing a fail memory cell with the spare cell if the fail memory cell exists in the plurality of memory cells; at least one determination/fail address generator circuit configured to connect to said at least one memory block, said at least one determination/fail address generator circuit being configured to determine whether or not a memory cell included in the at least one memory block is defective, said at least one determination/fail address generator circuit further being configured to generate a fail address corresponding to the memory cell determined as being defective; a first control circuit configured to connect to said at least one memory block and said at least one determination/fail address generator circuit, the first control circuit being supplied with a first clock signal having a first frequency in a test operation mode, the first control circuit being operated in synchrony with the first clock signal to control each operation of said at least one memory block and said at least one determination/fail address generator circuit; and a logic circuit configured to be supplied with a second clock signal having a second frequency in the test operation mode, the logic circuit being operated in synchrony with the second clock signal while performing data exchange with said at least one memory block in a normal operation mode.