Patent ID: 7068558

Claim:
A semiconductor memory device, comprising: a memory array block having a number of unit memory cells; command decoding means receiving external commands for generating a read signal, a write signal, a bank signal, an active signal and a refresh signal; bank controlling means for activating the bank signal as a first bank driving signal in response to the refresh signal and activating as a second bank driving signal after a delay; internal address counting means for generating an internal address in response to the refresh signal; row address latching means for selecting one of the internal address and the inputted address to output a row address; first decoding means for decoding the row address in response to the first bank driving signal to activate a word line in the memory array block; second decoding means for decoding the row address in response to the second bank driving signal to activate a word line in the memory array block; first row controlling means for activating a first sense amplifier enable signal in response to the first bank driving signal; second row controlling means for activating a second sense amplifier enable signal in response to the second bank driving signal; and a sense amplifier block for sensing and amplifying memory cell data of the activated word line in response to the first sense amplifier enable signal and the second sense amplifier enable signal.