Patent ID: 7276936

Claim:
Clock circuitry for a programmable logic device comprising: a plurality of channels of high-speed serial interface circuitry including reference clock input circuitry and phase locked loop circuitry; PLD core circuitry including circuitry for distributing at least one clock signal throughout the PLD core circuitry; selection circuitry for selecting at least one of a signal from the reference clock input circuitry and an output signal of the phase locked loop circuitry for application to the circuitry for distributing; and circuitry for sharing the signal from the reference clock input circuitry with at least a subplurality of the channels and for sharing the signal from the phase locked loop circuitry with at least a subplurality of the channels, wherein the selection circuitry is connected to the circuitry for sharing, wherein the circuitry for sharing extends approximately parallel and adjacent to a side of the programmable logic device, and wherein the selection circuitry is connected to the circuitry for sharing adjacent an approximate midpoint of that side of the programmable logic device.