Patent ID: 7844923

Claim:
A method for designing a semiconductor integrated circuit having a zigzag super cut-off CMOS structure, the semiconductor integrated circuit comprising a high potential power supply line, a low potential power supply line, a first pseudo-power supply line connected to the high potential power supply line via a first power control transistor, and a second pseudo-power supply line connected to the low potential power supply line via a second power control transistor, the method comprising: a first step of preparing a first logic gate cell and a first layout cell each having a high potential power supply end connected to the high potential power supply line and a low potential power supply end connected to the second pseudo-power supply line, and a second logic gate cell and a second layout cell each having a high potential power supply end connected to the first pseudo-power supply line and a low potential power supply end connected to the low potential power supply line, for each kind of primitive logic gate, the high potential power supply end of the second logic gate and the second layout cell and the low potential power supply end of the first logic gate cell and the first layout cell being source or drain of transistors in the primitive logic gate; a second step of performing logic simulation, by using a simulator, on an assumption of a state immediately before power cut-off using a net list representing a logic circuit to be designed, and based on a result of the simulation, determining an output state of each primitive logic gate included in the logic circuit; a third step of changing the net list by using a first logic gate cell for a primitive logic gate having an output state of “H” and a second logic gate cell for a primitive logic gate having an output state of “L” based on the output state of each primitive logic gate determined in the second step; and a fourth step of generating a layout by using the first layout cell for the first logic gate cell and the second layout cell for the second logic gate cell based on the net list changed in the third step.