Patent ID: 8902796

Claim:
A transceiver, comprising: a transmit portion, including: a transmit synthesizer; and a transmit local oscillator (LO) signal generation section; a receive portion, including: a receive synthesizer configured to generate a first clock signal; and a receive LO signal generation section configured to generate a first LO signal from the first clock signal; and a switching structure configured, in a time division duplexing (TDD) mode of the transceiver, to couple the first LO signal to a receive mixer during a receive time slot of the TDD mode and to a transmit mixer during a transmit time slot of the TDD mode, wherein, in a frequency division duplexing (FDD) mode of the transceiver, the transmit synthesizer is configured to generate a second clock signal, and the transmit LO signal generation section is configured to generate a second LO signal from the second clock signal, and wherein the switching structure comprises: a demultiplexer configured, in the TDD mode of the transceiver, to receive the first LO signal and to couple the first LO signal to the receive mixer during the receive time slot of the TDD mode and to the transmit mixer during the transmit time slot of the TDD mode; and a multiplexer configured to receive the first LO signal and the second LO signal and to couple the first LO signal to the transmit mixer in the TDD mode of the transceiver and to couple the second LO signal to the transmit mixer in the FDD mode of the transceiver.