Patent ID: 7294871

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers; a polymer layer over said passivation layer, wherein said polymer layer has a thickness greater than that of said first dielectric layer and that of said second dielectric layer; and a second metallization structure over said polymer layer, wherein said second metallization structure comprises a third metal layer over said polymer layer, and said third metal layer has a thickness greater than that of said first metal layer and that of said second metal layer.