Patent ID: 8412873

Claim:
A bridge circuit between a first data port and a second data port, said bridge circuit comprising: a first transceiver stage supplied within a first voltage range, said first transceiver stage comprising at least one input buffer having an input linked to the first data port and at least one tri-state output buffer having an output linked to the first data port, a second transceiver stage supplied within a second voltage range, said second transceiver stage comprising at least one input buffer having an input linked to the second data port and at least one tri-state output buffer having an output linked to the second data port, a first detection circuit linked to first transceiver stage for detecting the arrival of a packet by the first data port, a second detection circuit linked to second transceiver stage for detecting the arrival of a packet by the second data port, a selection circuitry for enabling the output of the tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits, a set of pull-up resistors connected to the first data port, said set of pull-up resistors being connected to the first voltage range as a function of the value of the first voltage range, a first set of pull-down resistors connected to the first data port, said first set of pull-down resistors being connected to a ground as a function of the value of the first voltage range, a second set of pull-down resistors connected to the second data port, said second set of pull-down resistors being connected to the ground as a function of the value of the second voltage range.