Patent ID: 7420796

Claim:
A multilayer capacitor comprising: a laminate including a plurality of laminated dielectric layers and having first and second side surfaces facing each other; and a plurality of external terminal electrodes disposed on the first and second side surfaces; wherein in the laminate, first and second internal electrodes are arranged to define a first capacitor portion, and third and fourth internal electrodes are arranged to define a second capacitor portion; the first and second internal electrodes include capacitor-forming portions that face each other, with a particular dielectric layer provided between the capacitor-forming portions, and at least two lead portions which lead from the capacitor-forming portions so as to be exposed from the first and second side surfaces and electrically connected to particular external terminal electrodes among the plurality of external terminal electrodes, and the lead portion of the first internal electrode and the lead portion of the second internal electrode are disposed so as to be alternately exposed along the length of each of the first and second side surfaces; the third and fourth internal electrodes include capacitor-forming portions that face each other, with a particular dielectric layer provided between the capacitor-forming portions, and at least two lead portions which lead from the capacitor-forming portions so as to be exposed from the first and second side surfaces and electrically connected to particular external terminal electrodes among the plurality of external terminal electrodes, and the lead portion of the third internal electrode and the lead portion of the fourth internal electrode are disposed so as to be alternately exposed along the length of each of the first and second side surfaces; the first and third internal electrodes are disposed so as to be arranged along the length of each of the first and second side surfaces, with a predetermined distance provided between the first and third internal electrodes; the second and fourth internal electrodes are disposed so as to be arranged along the length of each of the first and second side surfaces, with a predetermined distance provided between the second and fourth internal electrodes; and when viewed in a laminating direction of the dielectric layers, the capacitor-forming portion of the first internal electrode does not overlap with the capacitor-forming portion of the fourth internal electrode, and the capacitor-forming portion of the second internal electrode does not overlap with the capacitor-forming portion of the third internal electrode.