Patent ID: 8395186

Claim:
A method for implementing vertical transistors in a back-end-of-line (BEOL) structure of a semiconductor chip comprising: forming a metal to metal device opening in a dielectric level extending to a predefined wiring level in the back-end-of-line (BEOL) structure of the semiconductor chip; forming a vertical field effect transistor (FET) by polycrystalline depositions in a stack between planes of a respective global signal routing wire in the metal to metal device opening; said polycrystalline depositions including sequential source deposition, channel deposition and drain deposition; and forming a wire via defining a gate node by forming an etched hole through said source deposition, channel deposition and drain deposition and a dielectric layer to a signal wire in the predefined wiring level in the BEOL structure; depositing a thin dielectric in said etched opening, and removing said thin dielectric from a bottom of said etched opening, and depositing a metal in said etched opening.