Patent ID: 8566658

Claim:
An integrated circuit comprising: scan test circuitry; and additional circuitry subject to testing utilizing the scan test circuitry; the scan test circuitry comprising at least one scan chain having a plurality of scan cells, the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation; wherein at least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation; wherein the output control circuitry comprises: a first pair of devices comprising a first transistor and a second transistor; a second pair of devices comprising a third transistor and a fourth transistor; wherein the first pair of devices is configured to disable the functional data output of the given scan cell responsive to a scan enable signal being at a first binary logic level and to enable the functional data output of the given scan cell responsive to a scan enable signal being at a second binary logic level; and wherein the second pair of devices is configured to disable the scan output of the given scan cell responsive to the scan enable signal being at a second binary logic level and to enable the scan output of the given scan cell responsive to the scan enable single being at a first binary logic level.