Patent ID: 8209485

Claim:
A digital signal processing apparatus, comprising: a main memory, comprising at least R memory banks for storing a plurality of data of digital signal, where R is an integer; a processing unit, for performing Fast Fourier Transformation (FFT) operation with variable power-of-2 lengths to the data of the main memory; a cache, comprising at least R×R cache units for storing part of the data of the main memory to provide to the processing unit and temporarily storing the operation results of the processing unit; and a rotate buffer unit, coupled to the main memory and the cache, wherein the rotate buffer unit is capable of buffering and rotating the data outputted from the memory banks to write to the cache, and buffering and rotating the data outputted from part of the cache units to respectively write back to the corresponding memory banks at the same time in response to controlling and addressing for the processing unit, wherein there is no common bus among the main memory, the cache and the processing unit due to the rotate buffer unit, only a single cache is used by the digital signal processing apparatus, and each time after R data in the cache are written back to the main memory, R new data in the main memory are moved to replace the R data in the cache, until the cache is fully updated.