Patent ID: 8350344

Claim:
A semiconductor device comprising: a plurality of memory cells aligned in a first direction including a first memory cell having a charge storage structure on a substrate, the charge storage structure including a charge trap pattern; and a conductive line extending in the first direction, the conductive line including a gate on the charge storage structure, the gate including a lower portion formed of silicon and an upper portion formed of metal silicide, the conductive line being connected to the plurality of memory cells, wherein, with respect to a cross section of the gate taken in a direction perpendicular to the first direction, the upper portion of the gate formed of metal silicide has a width greater than that of the lower portion of the gate formed of silicon, wherein, with respect to the cross section of the gate taken in the direction perpendicular to the first direction, the upper portion of the gate formed of metal silicide has a first thickness in a vertical direction with respect to the substrate, and the lower portion of the gate formed of silicon has a second thickness in the vertical direction, wherein the first thickness is substantially equal to or greater than the second thickness, and wherein, with respect to the cross section of the gate taken in a direction perpendicular to the first direction, the width of the lower portion of the gate is equal to a width of an insulator pattern on the charge trap pattern and below the lower portion of the gate.