Patent ID: 8050108

Claim:
A semiconductor memory device including: a plurality of word lines; a plurality of bit lines which are provided in a direction intersecting the plurality of word lines; a plurality of memory cells which are arranged in a matrix pattern that corresponds to intersections between the plurality of word lines and the plurality of bit lines; a plurality of sense amplifiers which are associated with the plurality of bit lines on a one-on-one basis; a plurality of switch circuits each of which belongs to one of first to n-th (n is an integer equal to or larger than 2) groups, and which are associated with the plurality of bit lines and with the plurality of sense amplifiers on a one-on-one basis, each switch circuit connecting its associated bit line and sense amplifier to each other when turned on; and a timing control section for controlling at least timing of the sense amplifiers and the switch circuits which, in reading stored data out of the memory cells, executes control in which the plurality of sense amplifiers are disabled while the plurality of switch circuits are turned on for a given period of time, the plurality of switch circuits are turned off and then the plurality of sense amplifiers are enabled, and, when a given period of time elapses since the relevant sense amplifiers are enabled, the switch circuits belonging to the first to n-th groups are sequentially turned on group by group at given time intervals.