Patent ID: 8555144

Claim:
A memory system comprising: a code data generating section which generates code data based on write data; a nonvolatile semiconductor memory which stores the write data and the code data for the write data and outputs read data and the code data for the read data; a signal pin; an error correcting section which is configured to correct an error bit included in the read data using the read data and the code data for the read data; an interface section which receives the write data, a read command and a mode control command from outside of the memory system, and outputs the read data to outside of the memory system, the read command and the mode control command received via the signal pin; and a mode control section which sets the memory system in one of a first operation mode and a second operation mode based on the mode control command, wherein, the interface section outputs the read data which is read from the nonvolatile semiconductor memory and includes an error bit to outside of the memory system in response to the read command in the first operation mode, and the error correcting section corrects an error bit included in the read data read from the nonvolatile semiconductor memory and the interface section outputs the read data including the error bit corrected to outside of the memory system in response to the read command in the second operation mode.