Patent ID: 8455871

Claim:
A method for manufacturing a thin film transistor array panel, comprising: forming a gate line comprising a gate electrode on a substrate; forming a gate insulating layer on the gate line; sequentially depositing an amorphous silicon layer, a first metal layer, and a second metal layer on the gate insulating layer; forming a first photosensitive film pattern on the second metal layer, the first photosensitive film pattern comprising a first region and a second region thicker than the first region; etching the second metal layer and the first metal layer using the first photosensitive film pattern as a mask; etching the amorphous silicon layer using the first photosensitive film pattern as a mask; etching the first photosensitive film pattern to form a second photosensitive film pattern; wet-etching the second metal layer using the second photosensitive film pattern as a mask to form an upper layer of a data line and a drain electrode; dry-etching the first metal layer using the second photosensitive film pattern as a mask to form a lower layer of the data line and the drain electrode; and dry-etching the amorphous silicon layer using the second photosensitive film pattern as a mask to form a semiconductor layer, wherein each lower layer comprises a first portion that protrudes outside an edge of the upper layer, and the semiconductor layer comprises a second portion that protrudes outside an edge of the lower layer, and wherein the lower layer comprises one of titanium, tantalum, molybdenum, and alloys thereof.