Patent ID: 7143267

Claim:
An apparatus, comprising: a prefetch engine comprising a plurality of prefetch registers; and an execution unit coupled to said prefetch engine, wherein said execution unit is configured to receive prefetch instructions regarding prefetching data, wherein said execution unit is configured to load said plurality of prefetch registers with prefetch information obtained from said prefetch instructions; wherein each of said plurality of prefetch registers is available for storing said prefetch information for a first thread in a single thread mode of operation and said plurality of prefetch registers is partitioned in a first set of prefetch registers and a second set of prefetch registers in a multithread mode of operation, said first set of prefetch registers available to a predetermined one of said first thread and a second thread and said second set of prefetch registers available to a remaining one of said first thread and a second thread; and wherein a first prefetch register includes a first field configured to indicate whether said first prefetch register is reserved to be accessed by a software prefetch; wherein said execution unit comprises: logic for loading said first prefetch register with information regarding prefetching data for said first thread; wherein said first prefetch register comprises a second field configured to indicate which thread of said first and said second threads is accessing said first prefetch register, wherein a value in said first field is set to a first predetermined value to indicate said first prefetch register is reserved for a software prefetch and a value in said second field is set to a second predetermined value to indicate said first prefetch register is accessed by said first thread; and wherein said prefetch engine further comprises logic for clearing said value in said first field in said first prefetch register upon a switch of said single thread mode of operation to said multithread mode of operation or vice-versa.