Patent ID: 7605739

Claim:
A differential analog to digital converter (ADC) comprising: a first resistance ladder leg including two resistances having first ends that communicate with a middle node; a second resistance ladder leg including two resistances having first ends that communicate with a middle node; a plurality of comparators, each having first and second inputs, wherein said first input communicates with one of said two resistances of said first resistance ladder leg, and said second input communicates with one of said two resistances of said second resistance ladder leg, wherein said first and second inputs of said plurality of comparators experience a propagation delay based upon an electrical distance of said first and second inputs from a corresponding one of said middle nodes; delay elements that communicate with said first and second inputs of said plurality of comparators and that adjust aggregate delays from corresponding ones of said middle nodes to said first and second inputs of said plurality of comparators; a first amplifier that applies a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg; and a second amplifier that applies a voltage based upon a second phase of the input signal to said middle node of said second resistance ladder leg.