Patent ID: 8461669

Claim:
A semiconductor device, comprising: a first semiconductor die, having a first switching device; a second semiconductor die, having a second switching device; a third semiconductor die, having control circuits and other periphery circuits; and a lead frame structure comprising at least a first section and a second section, the lead frame structure being configured to support said first semiconductor die and said second semiconductor die; wherein, at least one of said first and second semiconductor dies has an electrically quiet surface for receiving said third semiconductor die such that said third semiconductor die is vertically stacked on said first or second semiconductor die having said surface quiet, a substrate of said third semiconductor die being attached to said electrically quiet surface; wherein said first and second sections of the lead frame structure are electrically isolated from each other; said first section of the lead frame structure further comprising a first electrical lead for electrically coupling a bottom surface of said first semiconductor die to a power supply voltage, said second section of the lead frame structure further comprising a second electrical lead for electrically coupling a bottom surface of said second semiconductor die to a switching node.