Patent ID: 8848308

Claim:
A data processing system, the data processing system comprising: an analog to digital converter circuit operable to convert an input data to a series of digital samples, wherein the input data corresponds to a first region on a storage medium; an inter-track interference compensation circuit operable to reduce inter-track interference in a data input to yield a corrected output, wherein the data input is derived from the series of digital samples, and wherein the inter-track interference corresponds at least in part to information at a second region on the storage medium; an equalizer circuit operable to equalize the corrected output to yield an equalized output; a data detector circuit operable to apply a data detection algorithm to a data detector input derived from the equalized output to yield a detected output; a data decoder circuit operable to apply a data decode algorithm to a decoder input to yield a decoded output, wherein the decoder input is derived from the detected output; a timing recovery circuit operable to phase shift the equalized output to yield a phase shifted output; and a selector circuit operable to select one of the equalized output or the phase shifted output as the data detector input.