Patent ID: 8649219

Claim:
A 3D stacked non-volatile memory device, comprising: a substrate; a stacked non-volatile memory cell array carried by the substrate, and comprising a plurality of NAND strings, and each NAND string comprises a plurality of memory cells between a drain end of the NAND string and a source end of the NAND string; a plurality of bit lines, where a respective bit line of the plurality of bit lines is connected to the drain end of each NAND string in the plurality of NAND strings; and at least one control circuit in communication with the stacked non-volatile memory cell array and the plurality of bit lines, the at least one control circuit, to perform an erase operation, performs a two-sided erase for the plurality of NAND strings until one or more NAND strings of the plurality of NAND strings pass an erase-verify test, and, when the one or more NAND strings of the plurality of NAND strings pass the erase-verify test, switches to performing a one-sided erase for remaining NAND strings of the plurality of NAND strings which have not yet passed the erase-verify test.