Patent ID: 8164962

Claim:
A semiconductor memory apparatus comprising: a plurality of SRAM (Static Random Access Memory) circuits connected to a bit line pair; a word line control circuit; a sense amplifier circuit and a write control circuit, wherein each of said plurality of SRAM circuits comprises: a plurality of first SRAM cells that store data; a second SRAM cell that amplifies a potential difference corresponding to a data status and stores the potential difference; and a sub bit line pair that connects said plurality of first SRAM cells to an inverter pair disposed in said second SRAM cell, an output of one inverter of said inverter pair being connected to an input of another inverter of said inverter pair, and an output of the other inverter of said inverter pair being connected to an input of the one inverter of said inverter pair, wherein said word line control circuit outputs a first set of control signals for selecting one first SRAM cell to be read/written the data from said plurality of first SRAM cells of said plurality of SRAM circuits, and a second set of control signals for selecting one second SRAM cell to be read/written the potential difference from the second SRAM cells of said plurality of SRAM circuits, wherein a plurality of first control signals constituting the first set of control signals are connected to respective first SRAM cells disposed in one of said plurality of SRAM circuits and also connected to respective first SRAM cells disposed in another one of said plurality of SRAM circuits, wherein said sense amplifier circuit amplifies a potential difference of a read signal, the read signal being output from a bit line pair of the second SRAM cell selected according to the second control signals, and wherein said write control circuit outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signals.