Patent ID: 8183103

Claim:
A method for manufacturing an integrated circuit structure, comprising: forming a dielectric layer on a substrate having a transistor region and a diode region; forming a contact hole and an opening in the dielectric layer simultaneously, the contact hole exposing a portion of the substrate at the transistor region, the opening exposing a portion of the substrate at the diode region, and a size of the opening being larger than that of the contact hole; forming a first metal layer on the dielectric layer and filling the contact hole and the opening; removing a portion of the first metal layer to form a contact plug above the transistor region and simultaneously form a metal spacer on a sidewall of the opening; performing an ion implantation process by using the metal spacer as a mask, so as to form a lightly doped region in the substrate at a bottom of the opening; and forming a contact metal layer on the lightly doped region.