Patent ID: 8120404

Claim:
A master-slave flip-flop circuit that receives a data input signal and a clock signal and generates an output signal and an inverted output signal, the master-slave flip-flop comprising: a master stage for receiving the data input signal and the clock signal, and generating a controlled input signal; a slave stage, connected to the master stage, for receiving the controlled input signal and generating an inverted controlled input signal; an output stage, connected to the slave stage, for generating the output signal and the inverted output signal, wherein the output stage comprises: a first field effect transistor (FET) and a second FET connected in series, wherein the inverted input signal is applied to the gate of the second FET, and the inverted output signal is generated at the drain of the second FET; and a level shifting stage connected to the slave stage and the output stage, comprising: a third FET and a fourth FET, wherein the controlled input signal is applied to the gates of the third and fourth FETs, the source of the third FET and the drain of the fourth FET are connected to the gate of the first FET, and the output signal is fed back to the source of the fourth FET; and a fifth FET connected in series with the first FET, wherein the inverted input signal is applied to the gate terminal of the fifth FET.