Patent ID: 7315473

Claim:
A nonvolatile semiconductor memory device, comprising: a nonvolatile memory cell array having at least first and second blocks, each of the first and second blocks including a plurality of columns, each of the plurality of columns including a first select gate transistor, a NAND cell, and a second select gate transistor, the first select gate transistor, the NAND cell, and the second select gate transistor are connected in series, the first block including a first page and the second block including a second page; a data latch circuit coupled to the memory cell array, the latch circuit capable of storing a chunk of data stored in the first page; a command latch configured to receive a first command, a second command, a third command, and a fourth command; and an address latch configured to receive a first page address for the first page and a second page address for the second page, wherein the nonvolatile semiconductor memory device receives the first command followed by the first page address in response to a write enable signal, after receiving the first page address, the nonvolatile semiconductor memory device receives the second command in response to the write enable signal to cause a transfer of a first chunk of data stored in the first page to the data latch circuit, after receiving the second command, the nonvolatile semiconductor memory device receives the third command followed by the second page address in response to the write enable signal, after receiving the second page address, the nonvolatile semiconductor memory device receives a modifying data to supersede at least a portion of the first chunk of data in response to the write enable signal, the third command allows a remaining portion of the first chunk of data other than the superseded portion of the first chunk of data to stay unchanged in the data latch circuit, and then the nonvolatile semiconductor memory device receives the fourth command in response to the write enable signal to cause the modifying data and the remaining portion of the first chunk of data to be transferred from the data latch circuit to the second page.