Patent ID: 7945831

Claim:
A system comprising: A. first test access port circuitry having a data input, a data output, a clock input, a mode input, and a test data out enable output; B. second test access port circuitry having a data input, a data output, a clock input, a mode input, and a test data out enable output; C. a data input lead coupled to the data input of each test access port circuitry; D. a data output lead; E. a clock lead coupled to the clock input of the first test access port circuitry and to the mode input of the second test access port circuitry; F. a mode lead coupled to the mode input of the first test access port circuitry and to the clock input of the second test access port circuitry; and G. gating circuitry having a first input coupled to the data output of the first test access port circuitry, a second input coupled to the data output of the second test access port circuitry, a control input connected with the test data out enable output of one of the first and second test access port circuitry, and an output coupled with the data output lead.