Patent ID: 8438369

Claim:
A method comprising: updating a counter in a first direction away from a default value for each cycle of a blocking stall associated with a first processing element in a subsequent stage of a processor pipeline shared by the first processing element and a second processing element; updating a storage area to hold a representation of the second processing element in response to the blocking stall being associated with the first processing element; selecting the second processing element in a preceding stage of the processor pipeline in response to the storage area holding the representation of the second processing element and the counter not holding the default value; and detecting a subsequent blocking stall associated with the second processing element in the subsequent stage of the processor pipeline; in response to detecting the subsequent blocking stall, updating the counter in a second direction towards the default value responsive to the counter not holding the default value and the storage area holding the representation of the second processing element; updating the counter in the first direction away from the default value and updating the storage area to hold a representation of the first processing element responsive to the counter holding the default value; and updating the counter in the first direction away from the default value responsive to the storage area holding a representation of the first processing element.