Patent ID: 8796785

Claim:
A semiconductor device comprising: first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period; (n+1)-th to m-th switches (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period; first to n-th signal lines; and (n+1)-th to m-th signal lines, wherein a signal is supplied to the first signal line in the first period through the first switch, and the first signal line is in a floating state in the second period, wherein a signal is supplied to the n-th signal line in the first period through the n-th switch, and the n-th signal line is in a floating state in the second period, wherein the (n+1)-th signal line is in a floating state in the first period, and a signal is supplied to the (n+1)-th signal tine in the second period through the (n+1)-th switch, wherein the m-th signal line is in a floating state in the first period, and a signal is supplied to the m-th signal line in the second period through the m-th switch, wherein the first to m-th signal lines are parallel or approximately parallel, wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line.