Patent ID: 6998304

Claim:
A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device comprising the steps of: providing a substrate comprising a first active region and a second active region, said first and second active device regions comprising a first polysilicon layer overlying the silicon substrate and a silicon nitride layer overlying the first polysilicon layer; photolithographically patterning and etching through a thickness portion of the silicon nitride layer to expose a portion of the first polysilicon layer in the second active region; forming a first portion of a dielectric layer overlying the polysilicon portion while blocking oxide growth over the first active region; etching selected portions of the silicon nitride layer and first polysilicon layer to form exposed portions of the silicon substrate over the first active region while leaving the second active region unetched; and, forming a gate dielectric layer over the exposed portions of the substrate in the first active region to a predetermined thickness while simultaneously forming a second portion of the dielectric layer over the second active region to form the dielectric layer at a final predetermined thickness.