Patent ID: 6943589

Claim:
A multiplexer circuit comprising: a first circuit coupled to receive at least a first data input and a second data input and at least a first select signal and a second select signal corresponding to said first data input and said second data input, wherein said first circuit is coupled to an output node and is configured to provide an output on said output node responsive to a corresponding one of said first select signal or said second select signal being active; and a tristate circuit coupled to receive said first and said second select signals and coupled to said first circuit, wherein said tristate circuit is configured to prevent said first circuit from providing said output on said output node by presenting a high impedance on said output node responsive to said first select signal and said second select being inactive, said tristate circuit further including a first P-channel transistor and a second P-channel transistor coupled in series, in which said first P-channel transistor is coupled to a supply source and to said second P-channel transistor, said second P-channel transistor is coupled to said first circuit, and said first P-channel transistor and said second P-channel transistor are coupled to be acted by a corresponding one of said first select signal and said second select signal.