Patent ID: 7612377

Claim:
A thin film transistor array panel comprising: a substrate; a plurality of semiconductor regions on the substrate, wherein the respective semiconductor regions include a source region and a drain region doped with an N-type impurity, a dummy region doped with a P-type impurity, and intrinsic regions comprising a storage region and a channel region, the storage region being positioned between the drain region and the dummy region; a gate insulating layer covering at least a portion of the semiconductor regions; a gate line including a gate electrode and formed on the gate insulating layer, wherein the gate electrode at least partially overlaps the channel region; a storage line including a storage electrode and formed on the gate insulating layer, wherein the storage electrode at least partially overlaps the storage region; a data line including a source electrode connected to the source region and formed on the gate insulating layer; a drain electrode directly contacting both the drain region and the dummy region and formed on the gate insulating layer; and a pixel electrode connected to the drain electrode.