Patent ID: 6999011

Claim:
A system comprising the following: a multiplexer that can receive a plurality of analog signals; an analog scaler configured to scale an analog signal that is received from the multiplexer; an analog-to-digital converter configured to convert the scaled analog signal to a digital signal; one or more processors; and a memory module having stored therein microcode that is accessible and executable by the one or more processors; wherein the microcode, when executed by the one or more processors, causes the system to perform the following: an act of determining which analog signal from the plurality of analog signals is being provided to the analog scaler by the multiplexer; an act of adjusting a scaling value of the analog scaler to allow the analog scaler to scale the analog signal using the adjusted scaling value, and to allow the analog-to-digital converter to convert the scaled signal into the digital signal representing a digital value; an act of reading the digital value; and an act of determining from the digital value whether the scaling value should be adjusted for the analog signal so that the scaled analog signal is within the input range, or further within the input range, of the analog-to-digital converter.