Patent ID: 8000477

Claim:
A data security system for an input/output (I/O) bus, comprising: a circular shift register that is operable to load an initial key value and to bit-shift the initial key value to provide a bit-shifted key value, wherein the initial key value is agreed upon by a transmitter system and a receiver system, each of which are coupled to the I/O bus, before the initial key value is loaded into the circular shift register; and a scrambler that is a physical layer component of the I/O bus and that includes a linear feedback shift register (LFSR) that is operable to be initialized by receiving the initial key value from the circular shift register; wherein the LFSR is operable, during the transmission of data over the I/O bus, to be periodically re-initialized with the bit-shifted key value provided by the circular shift register in order to scramble the data transmitted over the I/O bus.