Patent ID: 7133487

Claim:
A level shifter, comprising: a first switch circuit having a first switch and a second switch, each having a first terminal, a second terminal and a third terminal, wherein the first terminals of the first and the second switches are connected to a high voltage node; a second switch circuit having a third switch and a fourth switch, each having a fourth terminal, a fifth terminal and a sixth terminal, wherein the fourth terminal of the third switch is connected to the third terminal of the first switch and the second terminal of the second switch, the fourth terminal of the fourth switch is connected to the second terminal of the first switch and the third terminal of the second switch, the sixth terminals of the third and the fourth switches are connected to a low voltage node, the fifth terminal of the third switch receives an input control signal and the fifth terminal of the fourth switch receives an inverted input control signal; and first and second triggers having a delay unit, an inverter and an AND gate respectively and connected across the third and the fourth switches for dynamically changing respective substrate voltages of the third and the fourth switches, thereby reducing respective threshold voltages of the third and the fourth switches and turning on respective parasitic bipolar junction transistors (BJTs) on the third and the fourth switches.