Patent ID: 8891317

Claim:
A volatile memory comprising: volatile memory cells adapted to perform data write and read operations, the memory cells being arranged in rows and columns and, further, being distributed in separate groups of memory cells for each row; a first memory cell selection circuit configured to perform write operations; a second memory cell selection circuit, different from the first circuit, configured to perform read operations; wherein the first memory cell selection circuit is configured to select, for each row, memory cells from one of the group of memory cells for a write operation; wherein the first memory cell selection circuit is configured to select, for each row, memory cells from one of the groups of memory cells for a read operation; wherein the second memory cell selection circuit comprises read word lines for each row, each read word line being connected to all the memory cells of one of the groups of memory cells; wherein each memory cell comprises: first and second inverters, an output of the first inverter being connected to, an input of the second inverter and, an output of the second inverter being connected to, an input of the first inverter; a first switch connected to the output of the first inverter; a second switch connected to the output of the second inverter; a first MOS transistor having two conduction terminals and a first gate, the first gate being connected to the output of the first inverter; a second MOS transistor having two conduction terminals and a second gate, the second gate being connected to the output of the second inverter; wherein each read word line is connected to one of the conduction terminals of the first MOS transistor and to one of the conduction terminals of the second MOS transistor; and wherein the first selection circuit comprises a circuit configured to turn on the first and second switches of one of the groups of memory cells.