Patent ID: 6988181

Claim:
A processing core comprising: one or more processing pipelines having a total of N-number of processing paths, each of said processing paths for processing instructions on M-bit data words; and a plurality of register files, each having Q-number of registers, said Q-number of registers being M-bits wide; wherein said Q-number of registers within each of said plurality of register files are both private and global registers, and wherein when a value is written to one of said Q-number of said registers which is a global register within one of said plurality of register files, said value is propagated to a corresponding global register in the other of said plurality of register files, and wherein when a value is written to one of said Q-number of said registers which is a private register within one of said plurality of register files, said value is not propagated to a corresponding register in the other of said plurality of register files, wherein each of said Q-number of registers is bi-modal to programmably operate in both private and global modes.