Patent ID: 6884652

Claim:
A method for fabricating a semiconductor package, comprising the steps of: preparing a metal carrier; applying a dielectric material layer over a surface of the metal carrier, and forming a plurality of openings penetrating through tho dielectric material layer; applying a solder material in each of the openings; forming a first copper layer over the dielectric material layer and solder materials in the openings; forming a second copper layer over the first copper layer, and patterning the first and second copper layers to form a plurality of conductive traces, each of the conductive traces having a terminal, wherein the first copper layer is smaller in thickness than the second copper layer; mounting at least one chip on a predetermined portion of the conductive traces and electrically connecting the chip to the terminals; forming an encapsulant to encapsulate the chip and conductive traces; and removing the metal carrier to expose the dielectric material layer and solder materials.