Patent ID: 6892243

Claim:
A computer system comprising: a host processor; an attachment bus coupled to the host processor, the attachment bus being inside the computer system, the attachment bus being configured to receive data during time cycles of predetermined length; a peripheral device coupled to the host processor via the attachment bus, the peripheral device being configured to transfer data from a network to the host processor over the attachment bus inside the computer system using at least first and second types of data transfers, comprising: a classifying circuit configured to separate the data into a first class associated with the first type of transfer and a second class associated with the second type of transfer; a first queue connected to receive the first class of data from the classifying circuit; a second queue connected to receive the second class of data from the classifying circuit; and a control circuit configured to place data from the first queue onto the attachment bus at a higher priority than data from the second queue is placed onto the attachment bus; where the control circuit is configured to place at least a minimum amount of data from the first queue onto the attachment bus during each time cycle; where the control circuit is configured to place data from the second queue onto the attachment bus only when the attachment bus is otherwise unoccupied by first class data.