Patent ID: 7752530

Claim:
A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising: M memory banks for storing N input data samples, wherein each input data sample comprises systematic data, non-interleaved parity data and interleaved parity data, wherein the N input data samples are logically divided into M logical blocks and wherein input data samples from each of the M logical blocks are stored in each of the M memory banks; M processing units for performing MAP calculations, wherein each of the M processing units is capable of accessing each of the N input data samples in the M memory banks and wherein each of the M processing units is dedicated to processing one of the M logical blocks of input data samples; a communication switch capable of coupling the M processing units to the M memory banks; and an address generator for controlling the communication switch and the M processing units such that the M processing units simultaneously access input data samples from each of the M logical blocks in each of the M memory banks without collision.