Patent ID: 8330264

Claim:
An electronic package for containing a semiconductor chip comprising: a laminated board having a top surface and a bottom surface and at least a first and second via connectors penetrating through the laminated board between the top surface and the bottom surface wherein the top surface having at least a first top conductive plate and a second top conductive plate and the bottom surface of the laminated board having a first and a second bottom conductive plates wherein the first via connector is connected between the first top and bottom conductive plates and the second via connector is connected between the second top and bottom conductive plates; the bottom surface of the laminated board further having at least a first solder ball pad and second solder ball pad disposed on peripheral areas of the bottom surface besides the first and bottom conductive plates wherein the first and second solder ball pads is electrically connected respectively to the first and second bottom conductive plates; the semiconductor chip further comprises solder bumps connected to a first and a second top electrodes of the semiconductor chip wherein said solder bumps are soldered onto the first and second bottom conductive plates; said semiconductor chip further having a flat bottom electrode disposed on a bottom surface of the semiconductor chip opposite said first and second top electrodes; and said bottom surface of the laminated board further comprises at least two solder balls soldered unto the first and second solder ball pads on the peripheral areas of the bottom surface of the laminated board and extending downwardly to substantially a same vertical position as a bottom surface of the flat bottom electrode of the semiconductor chip.