Patent ID: 7913215

Claim:
A method for generating a circuit layout for a memory macro having at least one memory array to be used to fabricate a memory device, the memory array including a plurality of memory cells and sense amplifiers, comprising: generating a first set of memory cells and sense amplifiers comprised of regular electronic components disposed in a first area of the memory array, wherein the first area is disposed at an inner area of the memory array; and generating a second set of memory cells and sense amplifiers comprised of irregular electronic components disposed in a second area located along an edge of the memory array, the second set of memory cells and sense amplifiers comprised of irregular electronic components having different physical dimensions from those of the first set of memory cells and sense amplifiers comprised of regular electronic components to compensate for process-induced dimensional variations of the second set of memory cells and sense amplifiers, and wherein a memory compiler is used for generating the first and second sets of memory cells and sense amplifiers comprised of a predetermined number of transistors of the of the circuit layout, and wherein a channel length or width of a transistor in the second set of cells is longer than that of a transistor in the first set of cells so as to improve the operation speed of the memory device.