Patent ID: 7827461

Claim:
A low-density parity-check (LDPC) decoder apparatus, comprising: a plurality of bit node processing elements; a plurality of check node processing elements; a plurality of message passing memory blocks; a first routing matrix to couple the plurality of bit node processing elements to the plurality of message passing memory blocks; and a second routing matrix to couple the plurality of check node processing elements to the plurality of message passing memory blocks; wherein the first routing matrix and the second routing matrix are configured to couple each of a plurality of bit node processing element and check node processing element pairs to a corresponding one of the message passing memory blocks, so that, for each pair, a bit-node-to-check-node LDPC decoding message from the bit node processing element of the pair is routed to the check node processing element of the pair via the first routing matrix, the second routing matrix, and the corresponding one of the message passing memory blocks, and a check-node-to-bit-node LDPC decoding message from the check node processing element of the pair is routed to the bit node processing element of the pair via the first routing matrix, the second routing matrix, and the corresponding one of the message passing memory blocks.