Patent ID: 8521979

Claim:
A memory system comprising: a plurality of memory devices, each including a respective array of memory cells, each of the plurality of memory devices configured to access data from a respective array of memory cells in response to capturing a respective read command, each memory device further configured to capture the respective read command at least partially responsive to an array access signal and output the respective read data corresponding to the respective read command responsive to a respective output control signal; an interface coupled to each of the plurality of memory devices, the interface configured to receive the respective read data output from each of the plurality of memory devices; and a controller operating according to a controller clock signal having a controller clock period coupled to the plurality of memory devices through the interface, the controller configured to transmit the respective read commands to the plurality of memory devices, the controller further configured to transmit the array access signal to the plurality of memory devices and transmit the respective output control signal for each of the plurality of memory devices, at least partially responsive to transmitting first and second consecutive read commands to two different ones of the plurality of memory devices, the controller configured to delay a time when read data corresponding to the second consecutive read command is transmitted on the interface by less than one controller clock period.