Patent ID: 8362825

Claim:
A sub-stage for a charge pump having a first and second phase of operation, the sub-stage comprising: a dc input pin; a dc output pin; a first radio frequency (rf) input pin configured to receive a first differential signal; a second rf input pin configured to receive a second differential signal; a first transistor having a first, second and third terminal, wherein a current channel is provided between the first and second terminals of the transistor; and a second transistor having a first, second and third terminal, wherein a current channel is provided between the first and second terminals of the transistor; wherein the first terminal of the first transistor is connected to the dc input pin, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is connected to the dc output pin; wherein the first rf input pin is coupled to the second terminal of the first transistor and the first terminal of the second transistor, such that the current channel of the first transistor conducts signaling received at the first rf input pin during the first phase of operation, and the current channel of the second transistor conducts signaling received at the first rf input pin during the second phase of operation; the sub-stage further comprising a first bias voltage source and a second bias voltage source; wherein the third terminal of the first transistor is configured to receive the second differential signal from the second rf input pin and a first offset voltage signal from the first bias voltage source; and the third terminal of the second transistor is configured to receive the second differential signal from the second rf input pin and a second offset voltage signal from the second bias voltage source; the first and second bias voltage sources being dc voltage sources; the sub-stage being characterized in that the first bias voltage source is configured to provide the first offset voltage signal having a substantially constant value that is less than the threshold value of the first transistor, and the second bias voltage source is configured to provide the second offset voltage signal having a substantially constant value that is less than the threshold value of the second transistor, wherein the first and second differential signals are 180 degrees out of phase with each other.