Patent ID: 8402354

Claim:
A signal processor, comprising: a signal receiving section for receiving signals encoded under a predetermined code rule; a rule violation detecting section for detecting code rule violation included in the signals received by the signal receiving section; an error range specifying section for specifying a range in which an error bit is included out of a bit string which constitutes the signals on the basis of a position of the code rule violation detected by the rule violation detecting section; and an error correcting section for correcting one error bit in the range specified by the error range specifying section so that the code rule violation detected by the rule violation detecting section is eliminated, wherein the error correcting section includes: a correction value determination section for determining a value of a correction bit which can eliminate the code rule violation detected by the rule violation detecting section for each bit in the range specified by the error range specifying section; an amplitude difference calculating section for calculating difference between an amplitude value of the signals corresponding to a value of the correction bit determined by the correction value determination section and an amplitude value of the signals corresponding to a previous bit of the correction bit; a maximum difference selecting section for comparing difference in the amplitude values corresponding to each of the bits in the range calculated by the amplitude difference calculating section and selecting a value of a correction bit with the maximum difference in the amplitude value; and a correction processing section for correcting an error using a value of the correction bit selected by the maximum difference selecting section, and wherein at least one of the signal receiving section, the rule violation detecting section, the error range specifying section, and the error correcting section is a hardware section.