Patent ID: 7682894

Claim:
A method of manufacturing a flash memory device, comprising: forming a gate oxide layer on a semiconductor substrate and a shallow trench isolation formed in the semiconductor substrate, wherein said gate oxide layer is formed to directly contact the uppermost surface of both the semiconductor substrate and the shallow trench isolation; depositing a first polysilicon layer on the gate oxide layer; performing a first exposure and development process for a first photoresist deposited on the first polysilicon layer; forming grooves in the first polysilicon layer by etching a surface of the first polysilicon layer by using the first photoresist as a mask; removing the first photoresist; filling the grooves in the first polysilicon layer using a third photoresist; performing an etch back for the third photoresist; performing a second exposure and development process for a second photoresist deposited on the first polysilicon layer; forming a floating gate including protrusions and depressions on the uppermost surface of the floating gate by patterning the first polysilicon layer and the gate oxide layer by using the second photoresist as a mask; depositing a dielectric layer on the floating gate and the gate oxide layer, wherein said dielectric layer is formed to directly contact the shallow trench isolation, the floating gate and sidewalls of the gate oxide layer; and forming a control gate by patterning a second polysilicon layer deposited on the dielectric layer.