Patent ID: 7009228

Claim:
A field effect transistor (FET) comprising: a semiconductor substrate comprising a top surface and a bottom surface, wherein the top and bottom surfaces each comprise a heavily doped layer to provide an ohmic contact; a plurality of gate trenches formed in the top surface, each comprising a bottom, wherein a gate is disposed on the bottom of said gate trenches, forming a barrier junction, wherein said gate trenches are separated by a width W 1 ; a plurality of guard ring trenches formed in the top surface with a depth approximately equal to the depth of said gate trenches, each comprising a bottom,, wherein a guard ring is disposed on the bottom of said guard ring trenches, forming a barrier junction, wherein said guard ring trenches are separated by a width W 2 that is greater than W 1 ; a plurality of source regions on said top surface substantially surrounded by said gate trenches; a source contact disposed on the source regions; and, a drain contact disposed on the bottom surface of said substrate.