Patent ID: 8164964

Claim:
A semiconductor memory storage device comprising: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of said plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of said at least two access control lines in response to an access request, said at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing said access request and a boost signal to a selected one of said at least two access control circuits in dependence upon an address associated with said access request; wherein said at least two access control circuits are each responsive to: receipt of said access request from said routing circuitry to connect said selected access control line to a supply voltage; and receipt of said boost signal from said routing circuitry to disconnect said supply voltage from said access control line and to couple said boost signal to said access control line through said capacitor of said access control circuit to provide a boost to a voltage level on said access control line.