Patent ID: 8058114

Claim:
A method for manufacturing an array substrate, the method comprising: forming a gate line on a base substrate using an electroless plating method or an electrolysis plating method, the gate line including a first metal layer formed on the first seed layer; forming a first insulation layer on the base substrate having the gate line; forming a second seed layer on the base substrate having the first insulation layer in a direction crossing the gate line; forming a second insulation layer on the base substrate having the second seed layer, the second insulation layer having a line trench formed through the second insulation layer to expose the second seed layer; forming a second metal layer on the second seed layer of the line trench using the electroless plating method or the electrolysis plating method to form a data line including the second seed layer and the second metal layer; and forming a pixel electrode in a pixel area of the base substrate having the data line.