Patent ID: 7078952

Claim:
An integrated circuit, comprising: a clock calibration device receiving a local clock signal from an oscillator and applying a correction value to said signal to produce a corrected clock signal, the clock calibration device comprising: a frequency dividing module comprising a programmable divider and a calibration register for storing the correction value, the programmable divider receiving the local clock signal and delivering the corrected clock signal; and means for determining a new correction value using an external reference signal, the means comprise: a time base unit for producing a time base signal using a timing signal derived from the local clock signal, the time base unit comprising a counting module coupled to a load register wherein a load value is saved which determines a ratio between a frequency of the time base signal and that of the timing signal; and a computing unit external to the clock calibration device, for loading a new load value into the load register, by using the new correction value stored in the calibration register of the clock calibration device, to deduce the new load value to be loaded into the load register therefrom.