Patent ID: 7005706

Claim:
A semiconductor device comprising: a substrate having an insulating layer formed thereon; a silicon layer having a thickness ts formed on the insulating layer, the silicon layer including a first area having a first impurity concentration of Df cm −3 , and a second area having a second impurity concentration of Dp cm −3 ; a fully-depleted MOSFET formed in the first area of the silicon layer; and a partially-depleted MOSFET formed in the second area of the silicon layer, wherein the semiconductor device satisfies the following conditions: 28 nm≦ ts ≦42 nm, Df≦ 9.29*10 15 *(62.46 −ts ), Df≦ 2.64*10 15 *(128.35 −ts ), Dp≧ 9.29*10 15 *(62.46 −ts ), and Dp≧ 2.64*10 15 *(129.78 −ts ).