Patent ID: 8335110

Claim:
A semiconductor memory comprising: a non-volatile memory cell configured to include a floating gate and a memory transistor; a state machine configured to generate a normal program signal to perform a normal program operation and a verify signal to perform a verify operation in a write operation and to generate a soft program signal to perform a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a certain value in the normal program operation being checked in the verify operation; a voltage generating circuit configured to generate a normal program voltage and a verify voltage in response to the normal program signal and the verify signal respectively, and to generate a soft program voltage being lower than the normal program voltage in response to the soft program signal; and a determination circuit configured to detect a pass when the threshold voltage reaches the certain value and to detect the fail when the threshold voltage does not reach the certain value in the verify operation.