Patent ID: 8595656

Claim:
A mask build system comprising a program for configuring mask layers and a fabrication site for compiling configured mask layers, the system comprising: at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; the drawn layers including at least: a) a first drawn layer denoting at least one substantially planar interconnect; b) a second drawn layer denoting at least one substantially planar interconnect; c) a third drawn layer denoting holes to connect between the first drawn interconnect layer and the second drawn interconnect layer, the positions and shapes of geometries of the hole layer being used to affect the preparation of the mask data for the first interconnect layer; and a drawn marker layer explicitly selecting and defining all sections of the first drawn interconnect layer which the mask build system is to prepare to correctly handle all design-rule-correct positionings of all the holes as can be drawn within the drawn marker layer.