Patent ID: 8569827

Claim:
A nonvolatile memory device, comprising: a substrate having a well region of second conductivity type therein and a common source region of first conductivity type on the well region, said common source region forming a P-N rectifying junction with the well region; a recess in said substrate, said recess extending entirely through the common source region and at least partially into the well region; and a vertical stack of nonvolatile memory cells on said substrate, said vertical stack of nonvolatile memory cells comprising: a vertical stack of spaced-apart gate electrodes on said substrate; a vertical active region on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess; and gate dielectric layers extending between respective ones of the vertical stack of spaced-apart gate electrodes and said vertical active region; wherein at least one of a sidewall and bottom of said recess defines an interface between said vertical active region and the well region at a point in said substrate extending below the P-N rectifying junction between the common source region and the well region.