Patent ID: 7158415

Claim:
A system for programming reference cells in a memory device, the system comprising: a plurality of reference cells and an internal circuit embedded in and coupled to said memory device; a testing device coupled to said memory device, said testing device being configured to program at least one first reference cell to a predetermined value such that the at least one first reference cell provides a specified current I g where a specified read voltage is applied to that cell's gate; and said internal circuit being configured to set at least one of said plurality of other reference cells to specific values using said first reference cell as a comparative standard, wherein the internal circuit includes a ratio circuitry coupled to the at least one first reference cell and to sense circuitry for each of the plurality of other reference cells, the ratio circuitry configured to provide a current I g * R i to the sense circuitry for comparison with a current I refi ; provided by the at least one other reference cell, such that I refi =I g * R i where the specified read voltage is applied.