Patent ID: 6861878

Claim:
A chopper comparator having at least one logic gate in an input stage and a logic gate in an output stage, each logic gate in the input and output stages comprising: an inverter circuit; and a transistor for controlling connection and disconnection of the inverter circuit, wherein an operation signal is supplied to the transistors to control operation of the logic gates in the input and output stages, the inverter circuit becomes inactive when no operation of the chopper comparator is being performed, based on the operational signal, one of the logic gates comprises a NAND gate including a pair of P channel MOS transistors is connected in parallel and a pair of N channel MOS transistors connected in series, a first of the P channel MOS transistors and a first of the N channel MOS transistors of the NAND gate comprise the inverter circuit of the logic gate comprising a NAND gate, and the operation signal is supplied to a second of the N channel MOS transistors to control the connection and disconnection of the inverter circuit.