Patent ID: 8373432

Claim:
Automated test equipment for high-speed testing of packaged integrated circuit (IC) devices, each packaged IC device including a semiconductor IC and a package providing mechanical mounting of and external connections for the semiconductor IC, the external connections including a respective signal input terminal having package parasitic reactance, comprising: a tester channel circuit operative to generate an electrical test signal to be applied to the signal input terminal of each of the packaged ICs, the electrical test signal having a signal transition time less than 200 ps; and a contacter board configured to make physical and electrical contact with the packaged IC devices, the contacter board having a characteristic signal propagation speed, the contacter board having a signal transmission channel including (1) an electrical contact at which the electrical test signal is received, (2) conductive etch extending from the electrical contact to a plurality of isolation areas, each isolation area being adjacent to the signal input terminal of a respective one of the packaged IC devices, and (3) a plurality of embedded series isolation resistors each formed within the contacter board at a respective isolation area and being connected between the conductive etch and the adjacent signal input terminal, wherein a predetermined propagation dimension is defined as the product of the signal transition time of the electrical test signal and the signal propagation speed of the contacter board, and wherein for each isolation area the length of a respective signal path from the conductive etch to the isolation resistor, through the isolation resistor and then to the signal input terminal is less than one-fourth the predetermined propagation dimension.