Patent ID: 8106489

Claim:
A method of packaging a semiconductor device comprising steps of: forming a leadframe comprising leads, wherein each of the leads includes interlocking features extending from the lead perpendicularly to a long axis of the lead and parallel to a plane of the leadframe to lock the leads in place in a molding compound; reducing a thickness of a portion of the leads of the leadframe extending into a package being formed by etching a portion of a top surface of the leads; mounting a die on which the device is fabricated to a die paddle of the leadframe, the die extending past an edge of the die paddle into an open space created by reducing the thickness of the leads; wire bonding to form electrical connections between pads on the die and etched portions of the leads; and encapsulating the leadframe and the die mounted thereon, including the portion of the leads having a reduced thickness in the molding compound, wherein encapsulating the leadframe comprises providing substantially equal volumes of molding compound above and below the die paddle.