Patent ID: 7796629

Claim:
A packet switch, comprising: a plurality of output ports each having an output bandwidth and configured to store a bandwidth precision value for the output port indicating a number of bandwidth precision bits in a range including a number of bandwidth precision bits outside a bandwidth reservation precision range specified in a serial RapidIO 2.0 standard and to allocate at least a portion of the output bandwidth of the output port among a plurality of virtual channels based on a plurality of bandwidth allocations values of the output port corresponding to the plurality of virtual channels and the bandwidth precision value of the output port; a plurality of input ports each configured to receive a data packet identifying a virtual channel for the data packet and compliant with the serial RapidIO 2.0 standard and to identify at least one destination output port of the plurality of output ports for the data packet; an arbiter coupled to the plurality of input ports and the plurality of output ports, the arbiter configured to select at least one input port of the plurality of input ports based on the destination output ports of the data packets received by the plurality of input ports; and a switch fabric coupled to the plurality of input ports and the plurality of output ports and configured to route each data packet received by the at least one selected input port to at least one destination output port of the data packet, each output port of the plurality of output ports further configured to output each data packet received from the switch fabric by using the output bandwidth of the output port allocated to the virtual channel identified by the data packet.