Patent ID: 7746131

Claim:
A reset signal filter, comprising: a first comparator for comparing a power voltage and a first reference voltage so as to generate a first comparison signal; N flip-flops connected in series, a reset port of each flip-flop receiving the first comparison signal, an input port of each flip-flop being coupled to an output port of a preceding flip-flop, an input port of the first of the N flip-flops receiving a first reset signal, the N flip-flops connected in series registering levels of the first reset signal during N clock periods; a first logic gate, having N input ports coupled to output ports of the N flip-flops connected in series respectively, for determining if the levels of the first reset signal are identical during N clock periods and generating a logic signal; and an output flip-flop, being coupled to the first logic gate, for receiving the logic signal and outputting a second reset signal.