Patent ID: 7176061

Claim:
A method for manufacturing a semiconductor device including a semiconductor substrate having an element region and a dicing region, comprising: forming element isolation regions along a dicing line of the dicing region on the semiconductor substrate of the dicing region; forming a first dummy pattern between the element isolation regions on the semiconductor substrate; forming an insulating film above the first dummy pattern and the element region; and patterning the insulating film above the first dummy pattern so as to form a second dummy pattern, wherein the first dummy pattern is formed by patterning a gate oxide film which is formed on the element region and the dicing region, a polysilicon film which is stacked entirely on the gate oxide film, and a WSi film which is stacked entirely on the polysilicon film, and by forming a SiN film covering only a top side and both sides of the patterned polysilicon and WSi films, and not covering sidewalls of the first dummy pattern.