Patent ID: 7138823

Claim:
An output buffer, comprising: a plurality of buffer circuits, each buffer circuit having an input circuit and an output circuit, and further having an on-die termination (ODT) circuit coupled to the input and output circuits, the ODT circuit having an activation node to which an ODT activation signal is coupled to enable and disable the ODT circuit; and an ODT control circuit coupled to the plurality of buffer circuits and having an ODT mode select node to which an ODT mode select signal is applied and an ODT control node to which an ODT control signal is applied, in response to a first state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for the plurality of buffer circuits, and in response to a second state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for a first set of the plurality of buffer circuits and an inactive ODT signal for a second set of the plurality of buffers circuit.