Patent ID: 7271631

Claim:
A clock multiplication circuit for delivering an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as inputted, the clock multiplication circuit comprising: a counter for delivering a total count value by counting the total number of effective transition edges of the output clock signal, existing during a predetermined counting period given on the basis of the reference clock signal; a subtracter for delivering a difference value obtained by subtracting either the total count value or a reference value from the other; a control voltage generation circuit for delivering an analog control voltage corresponding to an integrated value of the difference value obtained by adding a new difference value to the stored integrated value; and a voltage control oscillator circuit for delivering the output clock signal at a frequency corresponding to the analog control voltage, wherein the counter is a counter for delivering the total count value by counting the total number of the effective transition edges of the output clock signal, existing during the counting period when the reference clock signal is only at a High level, and the counter, the subtracter, the control voltage generation circuit, and the voltage control oscillator circuit having response characteristics such that when the total count value is changed from a preceding total count value, the frequency of the output clock signal is changed during a period in which the reference clock signal is a Low level, after the end of the counting period and before the start of a succeeding counting period.