Patent ID: 7249300

Claim:
An integrated circuit device comprising: a core block configured for dynamic simulation testing and having an associated plurality of output ports, wherein the core block generates core output data for the plurality of output ports; an input side sub logic circuit unit configured for dynamic simulation testing and coupled to a plurality of input ports of the core block that generates sub data for the plurality of input ports of the core block responsive to data input to the input side sub logic circuit unit; and a multiplexer (MUX) unit between the core block and the input side sub logic circuit unit that selectively provides the sub data or the core output data as inputs to the input ports of the core block, without synchronizing between the MUX unit and the core block or between the MUX unit and the input side sub logic circuit, responsive to a MUX control signal, wherein the core block generates the core output data for the plurality of output ports responsive to outputs from the MUX.