Patent ID: 7698485

Claim:
A method for a first device to transmit data to a second device via a non-arbitrated digital bus comprising one or more control lines and one or more data lines, each device having a bus address and said non-arbitrated digital bus having clock cycles, the method comprising the steps of: (1) receiving a bus seize signal originating from a device other than said first device; (2) receiving a predetermined bus address originating from said device other than said first device; (3) receiving a bus release signal originating from said device other than said first device; (4) responsive to the receipt of said bus seize signal, said predetermined bus address and said bus release signal, seizing said non-arbitrated digital bus, wherein: step (4) comprises: (4a) asserting the bus address of said first device on said one or more data lines in the clock cycle immediately after the receipt of said bus release signal from said device other than said first device; and (4b) asserting a bus seize signal on said one or more control lines; and said device other than said first device is not a bus arbiter.