Patent ID: 8713398

Claim:
An error correction encoding apparatus for calculating redundant data for error correction from information data, comprising: an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data with respect to information data of a length of k×m bits (k, m and r are positive integers); and a cyclic addition apparatus including a k×m-bit shift register and an exclusive OR, wherein, the error correction encoding apparatus calculates data of a length of (r×m×(L+1)+k×m) bits (L is a positive integer equal to or smaller than k) as redundant data by adding redundant data of a length of r×m×L bits, k×m-bit data, and r×m-bit redundant data, the redundant data of a length of r×m×L bits being calculated by using the encoding apparatus L times with respect to information data of a length of k×m×L bits, the k×m-bit data being calculated by inputting the information data of the length of k×m×L bits to the cyclic addition apparatus, the r×m-bit redundant data being calculated by inputting the k×m-bit data to the encoding apparatus.