Patent ID: 7709314

Claim:
A method of fabricating a semiconductor CMOS switching device including: depositing, patterning and etching a first amorphous silicon majority carrier thin film layer on a substrate to form a contiguous first geometry; patterning and ion implantation to form an N-type and a P-type dopant implant region on the first geometry, the first geometry further comprising an implant boundary wherein the N-type and P-type implants are either adjacent to each other or over lap or merge; depositing a first dielectric layer; depositing a second amorphous silicon thin film layer; patterning and ion implantation to form N-type and P-type dopant implant second amorphous silicon regions; patterning and etching the second amorphous silicon layer to form a contiguous second geometry, the second geometry further comprising: an N-type implant region, said region fully crossing the first geometry region; and a P-type implant region, said region fully crossing the first geometry region; and an implant boundary wherein the N-type and P-type implants are either adjacent to each other or over lap or merge, said boundary occurring outside of the first geometry; cleaning and exposing the second geometry top surface and a portion of the first geometry top surface which includes the implant boundary not covered by the second geometry; depositing a metallic material for the purpose of silicide formation of first and second amorphous silicon material; providing silicide formation of the metallic material in the exposed surfaces, wherein: said second geometry surface including the implant boundary is silicided; and said exposed first geometry surface which includes the implant boundary region is silicided and wherein after etching said second amorphous silicon layer and prior to depositing said metallic material further including: patterning and ion implantation of N-type over N-type doped first geometry, and P-type over P-type doped first region to form source and drain regions; depositing a second dielectric layer; and etching the second dielectric layer to define dielectric spacer regions adjacent to the second geometry side walls.