Patent ID: 8395431

Claim:
A semiconductor integrated circuit device provided with a pulse-triggered flip-flop configured to allow the level of a state retention node to transit in a transition period and have the level of said state retention node retained in a transition-forbidden period, thereby setting, during said transition period said state retention node to a level based on a data signal inputted to a data input node, comprising: a first logic circuit configured to forcibly clear said state retention node according to a clear signal; and an AND gate configured to directly receive input data inputted to the flip-flop and said clear signal, output a result of an AND operation performed between the input data and said clear signal to said data input node of said pulse-triggered flip-flop as said data signal, and prohibit charging of said state retention node and maintain a clear state solely on the basis of said AND operation when said clear signal represents a clear period, the result of operation of the AND gate being asynchronous with a state of a clock signal inputted to the flip-flop.