Patent ID: 7558941

Claim:
A method comprising: at a starting address, writing a write cache line with a unique bit pattern into memory in a memory channel; attempting to enable independently addressable sub-channel memory accesses by setting an enable bit upon receiving a status command at each memory integrated circuit on memory modules in the memory channel supporting independently addressable sub-channel memory accesses; requesting to read a read cache line from memory in the memory channel at the starting address; comparing bit patterns of the read cache line and the write cache line to determine if independent sub-channel memory access is enabled into each memory integrated circuit; enabling independently addressable sub-channel memory access into each memory integrated circuit on memory modules in the memory channel if the bit pattern of the read cache line differs from the write cache line, wherein each memory channel includes an independent data bus and each independently addressable sub-channel includes an independent set of bits on the independent data bus from all other independently addressable sub-channels; and not enabling independently addressable sub-channel memory access into each memory integrated circuit on memory modules in the memory channel if the bit pattern of the read cache line is the same as the bit pattern of the write cache line memory integrated circuit on memory modules in the memory channel.