Patent ID: 8482990

Claim:
A circuit comprising: a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate; a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate; a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate; a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; a third NMOS transistor having a third NMOS drain, a third NMOS source, and a third NMOS gate; and a fourth NMOS transistor having a fourth NMOS drain, a fourth NMOS source, and a fourth NMOS gate, wherein the first PMOS drain, the first PMOS source, a voltage source, the second PMOS gate, and the second NMOS gate are coupled together; the first PMOS gate, the first NMOS gate, the second PMOS drain, the second NMOS drain, and the fourth NMOS source are coupled together; the third NMOS gate, the third NMOS drain, the first NMOS drain, and the second NMOS source are coupled together and serve as a first voltage reference node; the fourth NMOS drain is coupled to a second voltage reference node; a first voltage of the first voltage reference node serves as a first reference voltage of a memory cell; and a second voltage of the second voltage reference node serves as a second reference voltage of the memory cell.