Patent ID: 8234528

Claim:
A system comprising: a first memory vault comprising a first plurality of memory arrays, the first plurality of memory arrays including a first memory array and a second memory array, the first memory array located on a first die of a plurality memory stacked dies, the second memory array located on a second die of the plurality memory stacked dies; a second memory vault comprising a second plurality of memory arrays, the second plurality of memory arrays including a third memory array and a fourth memory array, the third memory array located on the first die of the plurality memory stacked dies, the fourth memory array located on the second die of the plurality memory stacked dies; a first memory vault controller located on one of the plurality of stacked memory dies and communicatively coupled to the first memory vault; a second memory vault controller located on one of the plurality of stacked memory dies and communicatively coupled to the second memory vault; and a system monitor processor located on one of the plurality of stacked memory dies and configured to monitor an operational parameter in a set of operational parameters associated with at least one of the first and second memory vaults.