Patent ID: RE44270

Claim:
An area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, comprising: a signal synchronization and detection means operable to synchronize a clock signal and a data signal, said data signal being used with said clock signal for generating status signals on a data bus ; a shift register operable to receive and retain data received from said data bus and to generate: a at least one status signal indicating the receipt of data by said area efficient system; and a reference bus address; and said data for enabling direct storage access; a comparator operably coupled to at least three storage areas and configured to compare said reference bus address with the content of at least one of said storage areas to generate an address matching signal; a control signal module connected and operable to govern a data write signal generation for said shift register responsive to said data bus ; and a sequencer configured to read data from said data retaining and processing device and writing to write data to said data retaining and processing device in a plurality of sub-cycles responsive to said status signals, data bus, said address matching signal, and said reference bus address ; , said sequencer further comprising a direct storage access controller operably coupled to at least three address registers, said address registers connected to communicate with said multiple data buffers, for enabling said direct storage access controller configured to enable data read and write operation operations of said data retaining and processing device, receiving to receive signals from said shift register for enabling speed efficient access of said a data bus to said data retaining and processing device and receiving to receive a control signal from said sequencer for generating interrupt signals and access request signals for said data retaining and processing device ; and , said serial access of said multiple data buffers being performed according to the inter-integrated circuit data transfer protocol.