Patent ID: 7969765

Claim:
A semiconductor memory device comprising: a plurality of word lines extended in a first direction; a plurality of bit line pairs extended in a second direction across the first direction; a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit line pairs, wherein each bit line pair includes upper and lower bit lines; a first local IO line coupled to the plurality of bit line pairs through a sense amplifier column, wherein the sense amplifier column includes a multiplexer circuit receiving first and second selection signals, a first read or write circuit receiving third selection signals, and a transfer gate circuit to couple the sense amplifier column to the upper and lower bit lines; wherein the plurality of bit line pairs are divided into a plurality of groups of the bit line pairs; wherein the sense amplifier column selects one of the plurality of groups of the bit line pairs based on the first and second selection signals; and wherein the sense amplifier column further selects one bit line pair included in the selected one of the plurality of groups of bit line pairs based on the third selection signals to electrically connect with the first local IO line.