Patent ID: 6842392

Claim:
A semiconductor memory device comprising: at least one memory cell block of dynamic memory cells arranged in a matrix, the memory cell block including a plurality of word lines; an address input section for input of a multiple-bit address that includes a row address for selecting one of the plurality of word lines; a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address; and a word line activation controller for controlling activation of the word lines; wherein the word line activation controller comprises: a row address transition detector for detecting whether the row address has changed; and wherein the word line activation controller is capable of: (a) in a first case that the row address transition detector does not detect a change in the row address during consecutive cycles in which at least one of read and write operations of data for the memory cells are enabled and in which an identical row address is used, maintaining an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivation thereof until a final cycle of the consecutive cycles; and (b) in a second case that a refresh operation is to be performed during a cycle among the consecutive cycles after the initial cycle, deactivating the activated word line prior to performing the refresh operation.