Patent ID: 7349510

Claim:
A memory controller comprising: a. a clock line adapted to convey a clock signal; b. a phase detector having: i. a data strobe node adapted to receive a data strobe signal; ii. a phase lock input node adapted to receive a phase lock signal; and iii. a phase detector output node adapted to provide phase information; iv. wherein the phase detector is adapted to compare the strobe signal with the phase lock signal to produce the phase information; c. a lock circuit having: i. a clock node coupled to the clock line and adapted to receive the clock signal; ii. a lock circuit input node coupled to the phase detector output node and adapted to receive the phase information; iii. a phase lock output node coupled to the phase lock input node and adapted to transmit the phase lock signal; and iv. a sampling signal output node; v. wherein the lock circuit is adapted to provide a data sampling signal on the sampling signal output node; and d. a sampling receiver having: i. a data input terminal adapted to receive a data signal; and ii. a clock input terminal coupled to the sampling signal output node and adapted to receive the data sampling signal; iii. wherein the sampling receiver samples the data signal using the data sampling signal.