Patent ID: 7838351

Claim:
A thin film transistor manufacturing method comprising the steps of: forming a gate electrode, gate insulating film and amorphous silicon film in succession on an insulating substrate; forming a channel protective film in a region which will serve as a channel region of the amorphous silicon film; forming an n+ silicon film and metal layer on top of the channel protective film and amorphous silicon film in succession; and patterning the amorphous silicon film and n+ silicon film to selectively leave a region associated with source and drain electrodes, and using the channel protective film as an etching stopper to selectively remove the region of the n+ silicon film and metal layer associated with the channel region so as to form source and drain regions from the n+ silicon film and also form source and drain electrodes from the metal layer, wherein, the channel protective film is formed so that the channel protective film has a layered structure made up of a plurality of layers having different etching rates and so that a bottom layer of the layered structure has selectivity to reset the topological etching variation of an upper layer of the layered structure such that the bottom layer is patterned differently than the upper layer.