Patent ID: 7814243

Claim:
A system, comprising: an integrated circuit having one or more data processing elements and one or more memory storage elements; and an interconnect to which the data processing elements are coupled, the interconnect to route a plurality of requests and a plurality of responses between the data processing elements and the one or more memory storage elements, wherein the interconnect implements a content addressable memory (CAM) structure that is shared storage for a plurality of logical, multi-thread ordered queues that make up entries in the CAM structure and buffer the requests from two or more threads from the data processing elements, the responses from two or more threads, or both, wherein each thread has its own unique identifier, and wherein a first multi-thread ordered queue is useable by a first request from a first thread with its own unique identifier (ID) during a first period of time and the same first multi-thread ordered queue is useable by a second request from a second thread with its own unique ID during a second period of time during the operation of the system; and wherein each of the entries in the CAM structure has a key and a data word, the key having first and second fields, the first field identifies a first multi-thread ordered queue through the unique ID, from among the plurality of multi-thread ordered queues, to which its entry is currently assigned, and the second field represents how many other entries precede this entry, in queue order, for the first multi-thread ordered queue, and the data word contains a portion of a buffered request or response.