Patent ID: 8218382

Claim:
A memory component comprising: a core of dynamic random access memory cells; a first circuit to receive, from a first external signal path, control information that specifies a write operation; a second circuit to receive, from a second external signal path, write data corresponding to the write operation; a third circuit, coupled to the second circuit, to receive a timing signal that indicates that the write data is valid write data, the third circuit being operable in a calibration mode to receive multiple delayed versions of the timing signal; a fourth circuit to receive, from a fourth external signal path, a clock signal that controls reception of the control information within the first circuit; and a fifth circuit to output signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay time between outputting the control information on the first external signal path and outputting the write data on the second external signal path, the delay time to compensate for a propagation difference between a propagation time of the control information propagating on the first external signal path and a propagation time of the write data propagating on the second external signal path.