Patent ID: 8453034

Claim:
An error detection/correction circuit comprising: a first selector configured to divide received data into p groups to output the groups based on a check matrix comprising a block made up of a unit matrix of a size p (p is an integer equal to or greater than 8) and a plurality of blocks in which each row of the unit matrix is shifted according to shift values from “1” to “p−1” when performing decoding processing on the received data coded with low density parity check codes; a second selector configured to further divide each of the groups into Y (Y is an integer equal to or greater than 2) subgroups to output the subgroups; a first memory configured to store a plurality of first variables for performing calculation processing on a probability β in association with a first address; a second memory configured to store a plurality of second variables for performing calculation processing on an external value α in association with a second address; a rotator configured to perform rotation processing with a rotation value corresponding to the shift value and the subgroup on the plurality of second variables stored in the second memory and transmits the plurality of second variables to an operation unit; the operation unit comprising (p/Y) operation circuits configured to perform parallel operation processing using the first variable and the second variable in the subgroup units in conjunction with the shift value; and a control section configured to control the first selector, the second selector and the rotator according to the shift value and the rotation value.