Patent ID: 6946356

Claim:
A method for manufacturing a capacitor, comprising the steps of: a) forming a sacrifice insulating layer on a semiconductor substrate; b) patterning the sacrifice insulating layer into a predetermined configuration to form openings; c) forming a first electrode on the sacrifice insulating layer and the openings; d) forming a grain growth preventing layer on top of the first electrode thereby filling the openings; e) performing one of a CMP and an etch back process until top of the sacrifice insulating layer is exposed; f) partially etching the grain growth preventing layer into another predetermined configuration to remain a residual grain growth preventing layer on the top of the first electrode in a bottom region of the openings; g) carrying out a first meta-stable poly silicon (MPS) grain growth process in order to grow up first MPS grains on top of the first electrode on an inner wall of the openings except the bottom region covered with the residual grain growth preventing layer; h) removing the residual grain growth preventing layer to expose the first electrode formed in the bottom region of the openings; i) removing the sacrifice insulating layer that embraces the first electrode; j) forming a dielectric layer on the first electrode; and k) forming a second electrode on the top face of the dielectric layer, wherein an etching selection ratio of the grain growth preventing layer is higher than the etching selection ratio of the sacrifice insulating layer.