Patent ID: 8332804

Claim:
An impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port, comprising: calculating a first set of impedances at a predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a first carrier coupling the core chip to the voltage source, wherein the first set of impedances comprises a self-impedance of the observation I/O port and mutual impedances of the observation I/O port with respect to other I/O ports; calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a second carrier coupling the core chip to the voltage source, wherein the second carrier is different from the first carrier and the second set of impedances comprises a self-impedance of the observation I/O port and mutual impedances of the observation I/O port with respect to other I/O ports; comparing the first set of impedances to the second set of impedances; and adjusting the impedance of the first or the second carrier according to the comparison result.