Patent ID: 8225254

Claim:
A delay analyzing apparatus for analyzing a delay that occurs in paths between flip-flops in a logic circuit of a semiconductor integrated circuit, the delay analyzing apparatus comprising: a delay calculation unit that generates delay calculation results based upon wiring and layout information with respect to the logic circuit; a delay analyzing unit that generates delay analysis results for the paths by adding delay information with respect to logic elements and flip-flops included in the logic circuit based upon the generated delay calculation results to thereby calculate sums, and by multiplying the calculated sums by a scattering coefficient; a delay analysis result sorting unit that sorts the generated delay analysis results for the paths in order of a maximum delay, thereby generating a maximum delay sorting result; a probability density path calculation unit that performs processing, by a computer, in which a respective path is selected from among the paths in order of the maximum delay based upon the maximum delay sorting result, and a probability density function is generated for the selected path, and repeats performing said processing to thereby generate probability density functions for the selected paths; and a statistical maximum value calculation unit that performs, by a computer, a statistical maximum value calculation for the generated probability density functions.