Patent ID: 8872261

Claim:
A semiconductor device, comprising: a drain electrode; a drain region of a first conductivity type electrically connected to the drain electrode; a periodic structure over the drain region, the periodic structure extending in a first direction perpendicular to an upper surface of the drain region and including semiconductor regions of the first conductivity type and semiconductor regions of a second conductivity type, the first conductivity type and the second conductivity type semiconductor regions being arranged alternately in a second direction parallel to an edge of the upper surface of the drain region; a third semiconductor region of the first conductivity type over the drain region, the third semiconductor extends in the first direction; a fourth semiconductor region of the second conductivity type located at an end of the periodic structure, a first side of the fourth semiconductor region being at the end of the periodic structure, a second side being in contact with the third semiconductor region; a drift region of the first conductivity type disposed on the first conductivity type semiconductor regions; a base region of the second conductivity type disposed on the second conductivity type semiconductor regions; a source region of the first conductivity type at disposed on upper surfaces of the base region; a gate electrode disposed above the base region; a gate insulation layer between the gate electrode and the base region; and a source electrode connected electrically to the source region, wherein each of the first semiconductor regions comprises multiple first diffusion layers stacked in the first direction, wherein all the first diffusion layers are of equal height, height being measured in the first direction, each of the second semiconductor regions comprises multiple second diffusion layers stacked in the first direction, wherein all of the second diffusion layers are of equal height, the third semiconductor region comprises multiple third diffusion layers stacked in the first direction, all of the third diffusion layers having equal height, within each of the second semiconductor regions, all of the multiple second diffusion layers are of equal width, width being measured in the second direction, within each of the second semiconductor regions, a gross amount of impurities within the individual second diffusion layers increases steadily in the first direction from the bottommost first diffusion layer to the uppermost first diffusion layer, within each first semiconductor region, all of the multiple first diffusion layers are of an equal width, all of the multiple first diffusion layers contain a same gross amount of impurities, and within the third semiconductor region, each third diffusion layer which has a higher third diffusion layer stacked thereon is wider than said higher third diffusion layer.