Patent ID: 7634037

Claim:
A digital phase-locked loop circuit, comprising: a phase detector, arranged to compare phases of a digital input signal and a digital output signal to generate a phase shift signal; a loop filter, arranged to digitally filter the phase shift signal; a digital control oscillator, arranged to generate the digital output signal according to the filtered phase shift signal; a value detector, arranged to detect the digital output signal and output a peak value or a trough value of the digital output signal; and a phase delay comparator, arranged to receive the digital input signal and the peak value or the trough value of the digital output value, and determine whether or not the most significant bit of the peak value or the trough value is identical to the most significant bit of the digital input signal simultaneously inputted into the phase delay comparator, the phase delay comparator further comprising: a most significant bit comparator, arranged to determine whether or not the most significant bit of the peak value or the trough value is identical to the most significant bit of the digital input signal simultaneously inputted into the phase delay comparator; a delay, arranged to delay the phase of the digital input signal; and a multiplexer, wherein when the most significant bit of the peak value or the trough value is different from the most significant bit of the digital input signal simultaneously inputted into the phase delay comparator, the multiplexer is arranged to selectively output the delayed digital input signal, and when the most significant bit of the peak value or the trough value is identical to the most significant bit of the digital input signal simultaneously inputted into the phase delay comparator, the multiplexer is arranged to selectively output an un-delayed digital input signal; wherein when the most significant bit of the peak value or the trough value is different from the most significant bit of the digital input signal simultaneously inputted into the phase delay comparator, the phase delay comparator is arranged to change the phase of the digital input signal inputted into the phase detector.