Patent ID: 7932547

Claim:
A nonvolatile ferroelectric memory device comprising: a silicon substrate; an insulating layer formed in an etching region, the etching region being formed by etching a portion of the silicon substrate; a bottom word line, where two adjacent bottom word lines form a pair of bottom word lines and are enclosed within the insulating layer, the insulating layer having two ends, the two ends defined by a bulk connection silicon which provides electrical connection to the silicon substrate; a floating channel layer formed over the bottom word line; an impurity layer formed at both ends of the floating channel layer, the impurity layer including a source region and a drain region as a first source/drain region and a second source/drain region, where the first source/drain region is provided directly on a portion of the insulating layer formed between the pair of bottom word lines and the second source/drain region is provided directly on the bulk connection silicon; a ferroelectric layer formed over the floating channel layer; a word line formed over the ferroelectric layer; and a bit line formed above the word line.