Patent ID: 7064584

Claim:
A P-domino latch, comprising: evaluation P-logic, coupled to a first N-channel device at a pre-charged node, configured to evaluate a logic function based on at least one input data signal; latching logic, coupled and responsive to a clock signal and said pre-charged node, configured to control the state of a latch node based on the state of said pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of said clock signal, and configured to otherwise present a tri-state condition to said latch node; keeper logic, coupled to said latch node, configured to maintain the state of said latch node when said tri-state condition is presented, and configured to provide a complementary state of said latch node at a complementary latch node; and acceleration logic, coupled and responsive to said pre-charged node and said complementary latch node, wherein an output of said acceleration logic forms an output node providing an output signal, and wherein said acceleration logic is configured to control the state of said output node.