Patent ID: 7706184

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of word lines and a plurality of bit lines; and at least first and second page buffers to which the plurality of bit lines are connected; wherein the plurality of word lines are physically divided into first and second word lines corresponding to the at least first and second page buffers; wherein the memory cell array includes a plurality of blocks, a plurality of cell strings are provided in each of the plurality of blocks, the plurality of cell strings each include a drain-side selection transistor, a preset number of memory cells and a source-side selection transistor, and the preset number of memory cells are metal oxide semiconductor (MOS) transistors with stacked gate structures in each of which data is written and erased by use of an FN current and configure NAND cells; wherein a read and verification operations are separately performed twice for the NAND cell for each of the at least first and second page buffers in units of the first and second word lines.