Patent ID: 6993640

Claim:
A computer processing apparatus, comprising: a configuration register for recording configuration information, said configuration information including a processor logical partition identifier; at least one state register for recording processor operating parameters, said at least one state register including a mode designator, said mode designator designating an operating mode; execution logic for executing instructions, said instructions including at least one instruction for altering said processor logical partition identifier, wherein said execution logic executes said at least one instruction for altering said processor logical partition identifier when in a first operating mode, and does not execute said at least one instruction for altering said processor logical partition identifier when in a second operating mode; and bus interface logic, said bus interface logic receiving bus communications on a bus, at least some of said bus communications including a respective tag, said tag being a logical partition identifier to which the bus communication pertains; wherein said processing apparatus ignores a bus communication including a tag, said tag being a logical partition identifier to which the bus communication pertains, if the tag included in the bus communication does not match said processor logical partition identifier.