Patent ID: 7426141

Claim:
A semiconductor memory device comprising: first and second cell arrays each having electrically rewritable and non-volatile semiconductor memory cells arranged therein, said first and second cell arrays being disposed in the direction of each bit line for transferring cell data and physically independent of each other; a sense amplifier disposed between said first and second cell arrays to be common to them; and a decode circuit configured to select a memory cell in said first and second cell arrays in accordance with address assigned to said first and second cell arrays in such a way that said first and second cell arrays serve as one memory plane in logic, wherein said first and second cell arrays each comprises plural blocks, each block including plural word lines, and wherein said decode circuit comprises: transferring transistor arrays each disposed on one side of the word line direction of a block in each of said first and second cell arrays for transferring word line drive voltages in the block; a block decoder configured to decode block address for selectively driving one of the transferring transistor arrays; a set of word line drivers disposed common to the entire blocks of said first and second cell arrays for outputting the word line drive voltages to be applied to word lines in a selected block; and drive signal lines disposed for transferring the word line drive voltages from the word line drivers to the respective transferring transistor arrays.