Patent ID: 6992958

Claim:
A phase-locked loop circuit for reproducing a channel clock, said phase-locked loop circuit comprising: a channel clock generation reference signal frequency divider that divides a channel clock generation reference signal; a switching frequency divider having a switch, a first switching frequency divider and a second switching frequency divider, said first and second switching frequency dividers receiving a high-frequency signal, said first switching frequency divider dividing said high-frequency signal by a first dividing ratio to generate a first divided signal, said second switching frequency divider dividing said high-frequency signal by a second dividing ratio to generate a second divided signal, said switch outputting said first divided signal during playback of a first recording medium and outputting said second divided signal during playback of a second recording medium; and a phase comparator, said phase comparator receiving said divided channel clock generation reference signal and one of said first and second divided signals, said phase comparator compares the phase of said divided channel clock generation reference signal with one of said first and second divided signals to output a phase error signal.