Patent ID: 7692972

Claim:
A split-gate memory cell, including: an n-channel split-gate non-volatile memory transistor having a source and a drain, the source and drain defining a channel, a select gate over a portion of the channel nearest the drain, and a control gate over a non-volatile charge retention structure over a portion of the channel nearest the source, the select gate and the control gate separated by a gap; a p-channel pull-up transistor having a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate; a switch transistor having a first source/drain diffusion, a second source/drain diffusion, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor; an inverting buffer having an input coupled to the second source/drain diffusion of the switch transistor, and an output; a p-channel level-restoring transistor having a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverting buffer.