Patent ID: 8216888

Claim:
A method of forming an integrated circuit structure, the method comprising: providing a substrate comprising: a first active region; a second active region adjacent to the first active region; and an insulation region between and adjoining the first active region and the second active region; forming a gate dielectric layer over the substrate; forming a gate electrode layer over the gate dielectric layer; etching the gate electrode layer, wherein remaining portions of the gate electrode layer comprise: a first gate strip over the first active region; a second gate strip over the first active region; a third gate strip over the second active region; a fourth gate strip over the second active region, wherein the first gate strip, the second gate strip, the third gate strip and the fourth gate strip are substantially parallel to each other, with each comprising a portion extending over the insulation region; and a sacrificial strip over the insulation region and having a lengthwise direction substantially perpendicular to a lengthwise direction of the first gate strip, wherein the sacrificial strip interconnects the first gate strip and the third gate strip; forming a mask layer covering portions of the first gate strip, the second gate strip, the third gate strip, and the fourth gate strip directly over the first active region and the second active region, wherein the sacrificial strip is exposed through an opening in the mask layer; and etching the sacrificial strip through the opening.