Patent ID: 8214574

Claim:
A processor comprising: a channel logic to store a set of conditions for a plurality of channels that each correspond to an architecture state, which if satisfied are to enable a yield event, wherein the set of conditions for each channel of the channel logic includes a channel identifier field to identify a corresponding channel, a scenario status field to indicate an occurrence of the scenario, a yield interrupt enable field to indicate whether a yield event is to be triggered in response to the occurrence of an architectural event, a scenario identifier field to identify the scenario, and an entry valid field to indicate whether an entry corresponding to the channel identifier field is valid; a storage unit to store event handling data in one or more entries, wherein each entry comprises a yield mask field to mask or unmask a corresponding yield interrupt, a mask field to mask or unmask a corresponding interrupt, a yield delivery status field to indicate a delivery status of a corresponding yield interrupt, a delivery status field to indicate whether an interrupt is idle or whether an interrupt is sent, a yield delivery mode field, a delivery mode field to select a delivery mode, and a vector field; a detection logic to detect whether the set of conditions are satisfied for a particular channel and to cause generation of an interrupt in response thereto to cause the yield event to occur; and a yield conversion logic to cause generation of the interrupt corresponding to the yield event at least in part based on a value stored in a yield interrupt enable field of the channel logic.