Patent ID: 8394684

Claim:
A method of fabricating a fully depleted non-planar semiconductor structure comprising: forming a plurality of parallel oriented semiconducting fins on a surface of a semiconductor substrate, wherein a gate stack is located on a portion of each of the semiconductor fins; forming at least one liner on at least an upper surface of the gate stack, wherein the at least one liner encapsulating underlying portions of each of the semiconductor fins; performing an amorphizing ion implantation process, wherein portions of each of the semiconductor fins adjacent to the gate stack have a disoriented crystal structure after performing the amorphizing ion implantation process; forming at least one stress inducing liner atop the at least one liner, wherein the at least one stress inducing liner imparts a stress to a channel region of each of the semiconductor fins that is located beneath the gate stack; performing a stress latching annealing, wherein the stress imparted to the channel region of each semiconductor fins is permanently transferred to the channel region of each semiconductor fins, while simultaneously recrystallizing the disoriented crystal structure in portions of each of the semiconductor fins; removing the at least the one stress inducing liner; and merging the recrystallized portions of each of the semiconductor fins, wherein said merging the recrystallized portions of each of the semiconductor fins comprises epitaxially growth of a semiconductor layer.