Patent ID: 8368186

Claim:
An electrostatic discharge protective device, the device comprising: a semiconductor substrate; a first N well region provided in the semiconductor substrate, the first N well region comprising: a first heavily doped P+ region and a first heavily doped N+ region, the first heavily doped N+ region being coupled to a Vdd potential; a first spacing between the first heavily doped P+ region and the first heavily doped N+ region, the first spacing being a portion of the first N well region; a second N well region provided in the semiconductor substrate, the second N well region comprising: a second heavily doped P+ region and a second heavily doped N+ region; a second spacing between the second heavily doped P+ region and the second heavily doped N+ region, the second spacing being a portion of the second N well region; a plurality of third N well regions, each of the plurality of third N well regions being disposed between the first and second N well regions at a spacing and comprising: a third heavily doped P+ region and a third heavily doped N+ region, the third heavily doped N+ region being electrically coupled to the first heavily doped P+ region, and the third heavily doped P+ region being electrically coupled to the second heavily doped N+ region; a third spacing between the third heavily doped P+ region and the third heavily doped N+ region, the third spacing being a portion of the third N well region; and a P well region provided in the semiconductor substrate abutting the second N well region; the P well region comprises: a fourth heavily doped P+ region and a fourth heavily doped N+ region, the fourth heavily doped P+ region being coupled to a Vss potential, the fourth heavily doped N+ region being coupled to the second heavily doped P+ region in common with an input/output pad of an integrated circuit; a fourth spacing between the fourth heavily doped P+ region and the fourth heavily doped N+ region, the fourth spacing being a portion of the P well region; wherein a capacitance between the input/output pad and the first heavily doped N+ region or between the input/output pad and the fourth heavily doped P+ region is less than 0.1 pF.