Patent ID: 8004049

Claim:
A power semiconductor device comprising an array of cells, each cell of the array comprising a source region formed at the substrate surface, a base region surrounding said source region in the substrate, a drain region underlying said source region and said base region, and a drain electrode contacting said drain region, a plurality of branches each extending laterally outwards towards at least one branch of an adjacent cell, the source regions in the branches of adjacent cells presenting juxtaposed ends, the base regions in the branches of the individual cells of the array comprising a corresponding plurality of base region branches each extending laterally outwards towards at least one base region in a branch of an adjacent cell, and the base regions in the branches of adjacent cells merging together adjacent and between said juxtaposed ends to form a single base region surrounding said source regions of the individual cells of said array in the substrate, with junctions that laterally are solely concave between the merged base region and the drain region defining a portion of a rounded current conduction path for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current between the source regions and the drain electrode, and a floating voltage region of opposite conductivity type to said drain region, buried in the substrate, extending beneath said merged base region and presenting a portion of a floating voltage feature and a portion of a floating island, the floating voltage regions of adjacent cells merge together to define the floating voltage feature completely surrounding laterally said current conduction path, and wherein the floating island is situation within said conduction path.