Patent ID: 7973354

Claim:
A cell array of a NAND-type non-volatile memory device, the cell array comprising: a plurality of active regions defined on a semiconductor substrate; a plurality of source and drain regions in the substrate; a plurality of selection gate lines, each between one of the source regions and one of the drain regions and crossing over the active regions of the substrate; and a plurality of word lines that cross over the active region of the substrate, wherein a plurality of the words lines are between adjacent pairs of the selection gate lines, and wherein each of the selection gate lines comprises: a lower gate pattern on the active region of the substrate; an upper gate pattern on the lower gate pattern and crossing over the active region of the substrate; a gate interlayer insulating layer between the lower gate pattern and the upper gate pattern; and a sidewall gate pattern on at least a portion of sidewalls of the upper gate pattern and the lower gate pattern, and which electrically connects the lower gate pattern and the upper gate pattern, and wherein each of the word lines comprises: a floating gate on the active region of the substrate; a control gate electrode on the floating gate and crossing over the active region of the substrate; and a gate interlayer insulating layer between the floating gate and the control gate electrode, wherein an upper edge portion of the lower gate pattern is recessed relative to a lower edge portion of the lower gate pattern to define a ledge thereon, and the sidewall gate pattern is directly on the ledge and sidewall of the recessed upper edge portion of the lower gate pattern.