Patent ID: 8173531

Claim:
A method of fabricating a semiconductor structure comprising: providing at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; forming an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of the at least one patterned gate stack; and forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material, wherein said forming the conformal nitride-containing liner comprises a thermal nitridation process that is performed at a temperature of less than 500° C. in a nitrogen-containing ambient, wherein said embedded semiconductor material is formed prior to forming the conformal nitride-containing liner, and said conformal nitride-containing liner is present only on exposed sidewalls of the patterned gate dielectric material.