Patent ID: 6891394

Claim:
Circuitry for providing low voltage differential signaling for a field programmable gate array (FPGA) comprising: a first output buffer; a second output buffer; a first output line; a second output line; a delay circuit connected to said first output line; an inverter connected to said first output line; a first multiplexer having a first input connected to an output of said delay circuit, a second input connected to said first outline and an output connected to said first output buffer, wherein said first multiplexer selectively connects said first output line and a delayed signal from said first output line to said first output buffer; a second multiplexer having a first input connected to an output of said inverter to receive an inverted signal from said first output line, a second input connected to said second input line and an output connected to said second output buffer; and control circuitry connected to said first multiplexer and said second multiplexer to determine a signal connected to said first output buffer by said first multiplexer and a signal connected to said second output buffer by said second output multiplexer.