Patent ID: 7042267

Claim:
A gated clock circuit comprising: a first logic circuit having a first input, a second input, and an intermediate output, the first logic circuit to receive a master clock signal on the first input, the master clock signal having a plurality of edges that include a first edge, a second edge, and a third edge, the first logic circuit to generate an intermediate signal on the intermediate output a time delay after the second edge of the master clock signal is detected on the first input, the intermediate signal to have a logic state defined by a logic state of a control signal on the second input; and a second logic circuit having a third input, a fourth input, and a signal output, the second logic circuit generating a gated clock signal on the signal output that has a logic state defined by the logic state of the intermediate signal on the third input when the third edge of the master clock signal is detected on the fourth input, when the control signal changes states on the second input, the control signal changes states during a time period that begins with a detection of the first edge on the first input and lasts for more than one-half of a master clock period.