Patent ID: 8456206

Claim:
A lock detect assembly comprising: a reference multiplier configured to receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output; generate a multiplied reference signal based on the reference signal and the VCO output, the multiplied reference signal having a frequency that is an integer multiple of a frequency of the reference signal, the integer having a value of at least 2; generate, using digital logic, a delayed reference signal; and generate, using digital logic, a delayed divider signal; and a lock detect in communication with the reference multiplier, the lock detect configured to detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time, the delayed reference signal and the delayed divider signal generated, using digital logic, based on the multiplied reference signal.