Patent ID: 7439539

Claim:
A flat panel display device comprising: a substrate on which a cell area and a pad area are defined; an active layer in an area of the cell area; a gate fine on the substrate including the active layer; a gate electrode overlapping the active layer; a storage electrode traversing the active layer; source and drain regions within the active layer; an insulating interlayer over the substrate having first and second contact holes on the source and drain regions, respectively; a data line arranged to define a pixel area by crossing with the gate line; a pixel electrode on the insulating interlayer of the pixel area; a protective layer over the substrate including the pixel electrode: a source electrode contacting the source region via the first contact hole; a drain electrode contacting the drain region via the second contact hole, the drain electrode on the pixel electrode, and a storage capacitor configured between the storage electrode/insulating interlayer/pixel electrode, wherein the pixel electrode is located between the insulating interlayer and the protective layer; and wherein the source and drain regions are doped and the active layer below the storage electrode is not doped.