Patent ID: 7367000

Claim:
A method for simulating a power voltage distribution, comprising the steps of: dividing a layout area of a semiconductor integrated circuit into a plurality of division units and acquiring power occupancy ratio information that expresses a power wiring density in the division units; acquiring power I/O position information, which expresses at least one position to which power is fed in the layout area; obtaining a resistance value of a model resistor, which expresses the resistance value of power wiring between the division units adjacent to each other, in response to a predetermined sheet resistance value of the power wiring and the power occupancy ratio information; and defining a division unit at least a part of which overlaps a predetermined area disposed by at least one so that the predetermined area occupies at least a part of the layout area as a division unit belonging to the predetermined area, and uniformly allotting a consumption current consumed in the predetermined area to the division units belonging to the predetermined area.