Patent ID: 8053843

Claim:
A semiconductor device, the device comprising: a semiconductor substrate including a surface region, the semiconductor substrate being characterized by a first conductivity type; a well region within the semiconductor substrate, the well region being characterized by a second conductivity type, the well region being also characterized by a first thickness; a first lightly-doped-drain (LDD) region within the well region, the first LDD region being of the first conductivity type, the first LDD region being characterized by a second thickness; an emitter region within the first LDD region, the emitter region being characterized by the second conductivity type; a drain region within the first LDD region, the drain region being characterized by the first conductivity type; a second lightly-doped-drain (LDD) region of the first conductivity type within the well region, the second LDD region being separated from the first LDD region by a channel region; a source region within the second LDD region, the source region being characterized by the first conductivity type; a gate dielectric layer overlying the surface region; a gate layer overlying the gate dielectric layer; and an output terminal coupled to both the drain region and the emitter region; wherein the first LDD region, the well region, and the substrate are associated with a first bipolar transistor, the first bipolar transistor being characterized by a first trigger voltage, and wherein the emitter region, the first LDD region, and the well region are associated with a second bipolar transistor, the second bipolar transistor being characterized by a second trigger voltage.