Patent ID: 7074700

Claim:
A method for forming an isolation layer in a vertical DRAM, comprising: providing a semiconductor substrate with a plurality of first trenches, a conformable collar dielectric layer formed on a sidewall of each, and a first conducting layer formed in each of the first trenches; forming a pattern mask layer with a plurality of openings over the semiconductor substrate, the collar dielectric layers, and the first conducting layers; etching the semiconductor substrate, the collar dielectric layers, and the first conducting layers to form a plurality of second trenches; removing the patterned mask layer; filling an insulating layer in each second trench acting as an isolation layer; etching the first conducting layers to a predetermined depth using the isolation layers acting as etching masks to form a plurality of grooves; filling a doped conducting layer in each groove; diffusing the doped conducting layers to form a doped area acting as a buried strap in the semiconductor substrate beside each groove; forming a trench top insulating layer over the first conducting layers and the doped conducting layers; and filling a second conducting layer in each trench acting as a gate.