Patent ID: 7321250

Claim:
An integrated circuit device which includes a logic circuit operating in synchronization with an internal reference clock and performing signal processing on a digital signal to generate multiple pieces of data, adjusts a phase of the internal reference clock to generate an external output clock, adjusts a phase of the data generated by the logic circuit to generate external output data, and outputs the clock and the data in parallel from a clock output terminal and data output terminals, the integrated circuit device, comprising: a delay adjustment circuit which is fed with the internal reference clock and adjusts a delay of the clock, flip-flop circuits which are fed with the data generated by the logic circuit and output the data as the external output data to the data output terminals in synchronization with a clock outputted from the delay adjustment circuit, and an inverting circuit for inverting the clock outputted by the delay adjustment circuit and outputting the clock as the external output clock to the clock output terminal.