Patent ID: 7335577

Claim:
A method for forming a crack stop for an integrated circuit (IC) chip having an active circuit area, wherein the IC chip includes metal interconnects which do not form a self-passivating oxide layer, in a low-K dielectric material, and a moisture barrier/edge seal positioned along the outer peripheral edges of the active area of the IC chip, at least one outer boundary crack stop formed by at least one trench or groove outside of the moisture barrier/edge seal on the outer periphery of the IC chip for preventing damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation performed on the wafer, the method comprising: forming the IC chip on the wafer substantially to completion but without a final top aluminum Al layer, including the steps of i) forming an edge seal region including a metal stack moisture barrier around the outer peripheral edges of the active area of the IC chip, and ii) forming a stack of metal interconnects and barrier layers outside said moisture barrier and in said edge seal region; forming a top Al layer over the IC chip, including the step of forming the Al layer on the edge seal region to protect the edge seal region from a subsequent wet etch, without forming the Al layer over said stack of metal interconnects and barrier layers; and after the step of forming said top Al layer, etching the wafer in a wet etch that removes the stack of metal interconnects and baffler layers selective to Al, to form an etched out region as a crack stop.