Patent ID: 7962694

Claim:
A method comprising: receiving a request for data from a processor of a plurality of processors; determining a cache entry location based, at least in part, on the request; storing the data in a cache corresponding to the processor at the cache entry location; storing a coherency record corresponding to the data in a snoop filter in accordance with one of the following, if there is a cache miss: at the cache entry location of a corresponding affinity in the snoop filter if the cache entry location is found in the corresponding affinity; and at a derived cache entry location of the corresponding affinity if the cache entry location is not found in the corresponding affinity; and if the cache entry location is occupied by other data, evicting the other data and sending a back invalidation message to each of the plurality of processors having a cache that includes the other data, wherein said evicting the other data comprises storing the other data in a back invalidation buffer until the back invalidation message is sent to an originating processor to ensure that the requesting processor does not rely on the other data in case the other data was not already invalidated.