Patent ID: 7716428

Claim:
A method of data processing in a cache coherent data processing system including at least first and second coherency domains, said method comprising: in a first cache memory within said first coherency domain of said data processing system, setting a coherency state field associated with a storage location and further associated with an address tag to a first data-invalid coherency state that indicates that said address tag is valid and that said storage location does not contain valid data; in response to snooping a data-invalid state update request that requests an update to one or more coherency states associated with the address tag but that does not request a memory block associated with the address tag, said first cache memory determining whether said data-invalid state update request originated within said first coherency domain; in response to the first cache memory determining that the data-invalid state update request originated within said first coherency domain, said first cache memory updating said coherency state field from said first data-invalid coherency state to a second data-invalid coherency state that indicates that said address tag is valid, that said storage location does not contain valid data, and that the memory block associated with said address tag is likely cached within said first coherency domain; and in response to a determination that said data-invalid state update request did not originate from within said first coherency domain, said first cache memory updating said coherency state field from said first-data-invalid coherency state to a third data-invalid coherency state indicating that said address tag is valid, that said data storage location does not contain valid data, that said first coherency domain does not contain a home system memory assigned the address of the memory block, and that said memory block is likely cached outside of said first coherency domain.