Patent ID: 6900081

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a first transistor of a MIS depletion type and a second transistor forming a masked ROM on a single semiconductor substrate by: forming a well region of a first-conductivity-type in a first region where the first transistor is to be formed and a second region where the second transistor is to be formed; implanting impurity ions of a first-conductivity-type in the regions where the first and second transistors are to be formed to form a first and second channel regions; implanting impurity ions of a second-conductivity-type in the first and second channel regions of the first transistor and some of the second transistors to permit current to flow when a gate-source voltage of the first transistor is zero and to change some of the second transistors into resistance, said implanting of impurity ion of said second conductivity type in both of said channel regions being carried out in the same ion implantation step; and thereafter forming first and second gate insulating films, first and second gate electrodes, and first and second source and drain regions of a second-conductivity-type in each of the first and second transistors.