Patent ID: 7074672

Claim:
A method of forming a semiconductor memory cell, comprising: forming a first region in a semiconductor substrate, wherein the substrate has a first conductivity type and the first region has a second conductivity type; forming a trench into a surface of the semiconductor substrate, wherein the trench is spaced apart from the first region; forming a second region in the substrate and underneath the trench, wherein the second region has the second conductivity type and a channel region in the substrate is defined between the first and second regions, the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the substrate surface; forming a floating gate of electrically conductive material disposed over and insulated from at least a portion of the channel region and a portion of the first region; forming a control gate of electrically conductive material having a first portion disposed in the trench; forming insulation material between the floating gate and the control nate that has a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and forming an indentation in a sidewall of the trench so that the control gate first portion includes a protruding portion corresponding to the indentation that extends over and is insulated from a portion of the floating gate.