Patent ID: 8085606

Claim:
A method for latching data in a data output circuit of a memory, comprising: driving a first data signal on an input-output line according to a first output drive setting by activating a first combination of transistors of a first set of transistors to couple the input-output line to a power supply, the first data signal representing first data; sensing the first data signal, and in response, generating an output data signal representing the first data; latching the first data; driving a second data signal on the input-output line according to a second output drive setting by a second combination of transistors of a second set of transistors to couple the input-output line to the power supply, the second data signal representing data, the first and second sets of transistors having the same sized transistors and the first and second combinations different; sensing the second data signal, and in response, generating an output data signal representing the second data; and latching the second data.