Patent ID: 8621325

Claim:
A packet switching system comprising: a forwarding processing unit determining a destination of an input packet by analyzing the input packet and outputting it as an output packet, the forwarding processing unit comprises an ingress interface card checking if the input packet has a sequential cyclic number and including an ingress side check control memory checking and controlling the sequential cyclic number, and an egress interface card creating a sequential cyclic number and including an egress side check control memory of the sequential cyclic number to assign the sequential cyclic number to the output packet, wherein the ingress interface card is coupled to the ingress side check control memory of the sequential cyclic numbers and comprises a first memory interface unit and a second memory interface unit, the ingress interface card dividing one access processing to the check control memory into a first process and a second process following right after the first process by performing the access processing at consecutive first and second memory access points, and the forwarding processing unit judges, after processing at the first memory access point by the first memory interface unit, if correction of the sequential cyclic number is necessary on results of the processing by the first memory interface unit, and the second memory interface unit corrects the sequential cyclic number read from an address space of the ingress side check control memory at the second memory access point and writes the corrected sequential cyclic number to the address space of the ingress side check control memory when it is judged by the forwarding processing unit that the correction of the sequential cyclic number is necessary.