Patent ID: 7755410

Claim:
A semiconductor integrated circuit, comprising: a first comparator that compares a first reference voltage with a first regulated voltage and outputs a first output signal; a first driving transistor having a gate terminal for receiving the first output signal of the first comparator, a source terminal for receiving an external supply voltage and a drain terminal for outputting the first regulated voltage; a first resistor coupled to the first driving transistor in parallel; a second comparator that compares a second reference voltage with a second regulated voltage and outputs a second output signal; a second driving transistor having a gate terminal for receiving the second output signal of the second comparator, a source terminal for receiving a ground voltage and a drain terminal for outputting the second regulated voltage; a second resistor coupled to the second driving transistor in parallel; and a clock buffer unit that supplies an output clock signal within a range of the first regulated voltage and the second regulated voltage, wherein the first resistor drops the external supply voltage and provides a dropped voltage to the drain terminal of the first driving transistor, and the second transistor and the second resistor boost the ground voltage and provide a boosted voltage to the drain terminal of the second driving transistor.