Patent ID: 6977408

Claim:
A process for fabricating an EEPROM device comprising: providing a substrate; forming an MOS transistor having an MOS gate electrode overlying the substrate and source and drain regions in the substrate, wherein the MOS gate electrode and the source and drain regions each have a silicide region therein; forming a floating-gate electrode overlying the substrate; forming a floating gate protection layer at least partially encapsulating the floating-gate electrode; forming a cap insulation layer contacting the silicide region in the MOS gate electrode and the source and drain regions, wherein the cap insulation layer has a thickness of about 800 angstroms to about 1200 angstroms; and forming a doped oxide layer overlying the cap insulation layer, wherein the thickness of the floating gate protection layer and the cap insulation layers is such that the floating-gate electrode is spaced apart from the doped oxide layer by at least about 1500 angstroms.