Patent ID: 8862925

Claim:
A synchronization circuit comprising: primary serial interface logic configured for coupling to a serial data receive line; a primary delay element coupled to the primary serial interface logic; secondary serial interface logic configured for coupling to the serial data receive line; a secondary delay element coupled to the secondary serial interface logic; a primary data sampler and a primary shift register coupled to the primary serial interface logic, wherein the primary data sampler is coupled to an output of the primary delay element; a secondary data sampler and a secondary shift register coupled to the secondary serial interface logic, wherein the secondary data sampler is coupled to an output of the secondary delay element; and a synchronizer coupled to the primary shift register and the secondary shift register; wherein one or more of the primary serial interface, the primary delay element, the primary data sampler and the primary shift register are configured for synchronizing the primary serial interface logic by: cycling through a plurality of delays in a data stream from the serial data receive line until a synchronization bit pattern is located; determining a minimum delay limit and a maximum delay limit for the primary serial interface logic using the bit synchronization pattern; setting a primary delay to a midpoint between the minimum delay limit and the maximum delay limit for the primary serial interface logic; and outputting received data via the primary serial interface as a function of the primary delay; and wherein one or more of the secondary serial interface logic, the secondary delay element, the secondary data sampler, and the secondary shift register are configured for synchronizing the secondary serial interface logic by: cycling through a plurality of delays in the data stream from the serial data receive line until the received data output of the secondary serial interface logic equals the received data output of the primary serial interface logic; determining a minimum delay limit and a maximum delay limit for the secondary serial interface logic by matching the received data output of the primary serial interface logic and the received data output of the secondary serial interface logic; setting a secondary delay to a midpoint between the minimum delay limit and the maximum delay limit for the secondary serial interface; performing a bit slip or bit advance process to prevent subsequent resynchronizations from requiring delays beyond what is possible of an implemented design; and outputting data via the secondary serial interface logic as a function of the secondary delay.