Patent ID: 8643099

Claim:
An integrated circuit, comprising: a semiconductor substrate having a first conductivity type; and a dual drift layer extended drain metal oxide semiconductor (MOS) transistor, including: a lower drift layer located in said substrate, said lower drift layer having an opposite conductivity type from said substrate; an upper drift layer located in said substrate over said lower drift layer, such that: said upper drift layer contacts said lower drift layer along at least 75 percent of a common length of said upper drift layer and said lower drift layer; said upper drift layer has said opposite conductivity type from said substrate; and an average doping density in said lower drift layer is between 2 and 10 times an average doping density in said upper drift layer; a body region located in said substrate adjacent to said upper drift layer and opposite from a drain section of said dual drift layer extended drain MOS transistor, such that said body region has a same conductivity type as said substrate; a gate dielectric layer located on said body region and overlapping said upper drift layer; and a gate located on said gate dielectric layer above said body region and overlapping said upper drift layer.