Patent ID: 7423902

Claim:
A storage device comprising: a plurality of memory cells disposed in a matrix, each of the plurality of memory cells including (a) a storage element having a resistance (1) which changes from a higher state to a lower state when a writing electric signal of a first threshold level or higher is applied to effect writing of information thereto and (2) which changes from the lower state to the higher state when an erasing electric signal of a second threshold level or higher is applied to effect erasing of information thereon, the polarity of the writing electric signal being opposite that of the erasing electric signal, and (b) a circuit element connected in series with the storage element, the circuit element serving as a switch and as a load, wherein, the storage device is configured such that each storage element is positioned between two voltages the selective application of the difference of which effects writing and erasing, and the storage device is configured such that in order to perform erasing on the memory cells, in a state in which an erasing electric signal is applied to a first predetermined unit including at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined period of time since the commencement of the application of the erasing electric signal to the first predetermined unit and while erasing of said at least one memory cell is on-going, an erasing electric signal is applied to second predetermined unit including at least one memory cell on which erasing is to be performed next.