Patent ID: 7829424

Claim:
A method of forming an integrated circuit package with a decoupling capacitor using a package design configured for use without decoupling capacitor, the method comprising: providing an initial design for an integrated circuit package substrate wherein the design is configured in a first circuit arrangement having an array of top mounted bond pads and a first circuit pattern arranged in a first stripline configuration, the initial design originally designed to construct the package substrate so that that does not have decoupling capacitors; providing a supplementary design for adding a capacitive element to the integrated circuit package substrate wherein the supplementary design is a modification of the initial design such that the addition of the capacitive element does not alter the first circuit pattern of the first stripline configuration and further incorporates a first dielectric layer, a supplemental plane, and at least one capacitive element into the second design; forming a multi-layer package substrate in accordance with the initial design and the second design, wherein the forming comprises; forming a base substrate formed generally in accordance with the initial design so that the base substrate is arranged in the first stripline configuration comprising a signal plane stacked between a pair of parallel reference planes, and further comprising an upper package surface having a first plane formed thereon, the first plane comprising one of the reference planes and an array of via straps that are electrically connected with the internal signal plane such that the array of via straps are arranged in place of the array of bond pads of the initial design; forming a first dielectric layer over the upper package surface wherein the first dielectric layer includes an array of conductive vias formed in registry with the array of via straps of the upper package surface; forming the supplemental plane on a top surface of the first dielectric layer, the supplemental plane having a polarity opposite of the first plane, the supplemental plane further including an array of top bond pads arranged in registry with the array of vias; and forming at least one decoupling capacitive element such that the capacitive element is electrically connected with the first plane and the supplemental plane.