Patent ID: 7492628

Claim:
A computer-readable medium encoding an apparatus, the encoded apparatus comprising: a plurality of bit line structures; a plurality of word lines structures intersecting said plurality of bit line structures to form a plurality of cell locations; a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding one of said bit line structures under control of a corresponding one of said word line structures, each of said cells in turn comprising: a first inverter having first and second field effect transistors (FETS); and a second inverter having third and fourth FETS, said second inverter being cross-coupled to said first inverter to form a storage flip-flop; wherein said second FET is configured with independent front and back gates, one of said front gate and said back gate of said second FET being configured to aid said selective coupling, another of said front gate and said back gate of said second FET being configured for said cross-coupling with said second inverter.