Patent ID: 7233618

Claim:
A circuit configuration for transmitting digital signals, comprising: a first signal line for transmitting binary signals having states and information content; a second signal line; a terminal for supplying a setting signal; a modulation unit connected to said first signal line and to said second signal line, said modulation unit: transforming received binary signals into a series of pulses having respective pulse lengths and outputting the pulses to said second signal line; modulating the pulses in the pulse length as a function of the information content of the binary signals; varying a signal level of the pulses that are to be output to said second signal line as a function of a state of one of the binary signals; having a driver circuit connected to said second signal line for outputting the pulses to said second signal line, said driver circuit having: a setting input connected to said terminal; and a resetting input; a selection circuit connected to said first signal line, said selection circuit: having an output coupled to said resetting input; receiving a number of clock signals having edges being offset chronologically with respect to one another; receiving a number of the binary signals from said first signal line; and selecting one of the clock signals as a function of the information content of the number of binary signals to be passed onto said output of said selection circuit.