Patent ID: RE43565

Claim:
A graphics system comprising: a dynamic-random-access memory (DRAM) for storing graphics data; a static random-access memory (SRAM) for storing pixels in a frame buffer; a first bus to the SRAM, a second bus to the DRAM; a refresh controller, coupled to the SRAM through the first bus, and coupled to the DRAM through the second bus, for reading pixels from the frame buffer for display to a display device; a frame-buffer extension in the DRAM, the frame-buffer extension for storing pixels read by the refresh controller for larger frame buffers; a graphics engine, coupled to the SRAM through the first bus, and coupled to the DRAM through the second bus, for reading and writing graphics data; and a dual-layer arbiter, receiving requests from the refresh controller to access the SRAM and requests from the graphics engine to access the DRAM, and also receiving requests from the refresh controller to access the DRAM and requests from the graphics engine to access the SRAM, the dual-layer arbiter allowing simultaneous access of the DRAM and SRAM when the refresh controller requests access of the SRAM and the graphics engine requests access of the DRAM, but the dual-layer arbiter delaying access of the DRAM by the graphics engine when the refresh controller access the DRAM, whereby the dual-layer arbiter allows simultaneous DRAM and SRAM access or arbitrated access of either the DRAM or the SRAM.