Patent ID: 7995367

Claim:
A circuit arrangement with a non-volatile memory cell, comprising: a symmetrically constructed comparator having a latching function, the comparator being connected in a differential current path that joins a power supply terminal to a reference potential terminal, wherein said comparator comprises: a first inverter, comprising an input and an output, connected between a supply terminal of the first inverter and the reference potential terminal, and a second inverter having an input that is connected to the output of the first inverter, and an output that is connected to the input of first inverter, and which is connected between a supply terminal of the second inverter and the reference potential terminal; the non-volatile memory cell is being connected between the supply terminal of the first inverter and the power supply terminal; a reference element connected between the supply terminal of the second inverter and the power supply terminal; a write arrangement comprising: a first switch that couples a first input of the write arrangement to the output of the first inverter, a second switch that couples the second input of the write arrangement to the output of the second inverter, and a control input that is coupled to a control terminal of the first switch and to a control terminal of the second switch; a first load transistor coupled between the output of the first inverter and the reference potential terminal; and a second load transistor coupled between the output of the second inverter and the reference potential terminal, and which has a control terminal coupled to a control terminal of the first load transistor.