Patent ID: 8670281

Claim:
An apparatus for reading and writing inverted bit values to a memory cell, the apparatus comprising: a memory cell, comprising: a first node comprising one or more field-effect transistors (FETs) and capable of storing a first bit value; a second node comprising one or more FETs and capable of storing a second bit value; a first bit line coupled to the first node of the memory cell; a second bit line coupled to the second node of the memory cell; a FET coupled to the first bit line that when activated provides a path from a first section of the first bit line to a second section of the first bit line; a FET coupled to the second bit line that when activated provides a path from a first section of the second bit line to a second section of the second bit line; a first alternative conductive path connecting the first section of the first bit line to the second section of the second bit line, the first alternative conductive path being selectable by activating a FET coupled to the first alternative conductive path; a second alternative conductive path connecting the first section of the second bit line to the second section of the first bit line, the second alternative conductive path being selectable by activating a FET coupled to the second alternative conductive path; and wherein the first alternative conductive path and the second alternative conductive path cross over each other.