Patent ID: 7888776

Claim:
An integrated circuit chip die with a scribe seal integrity detector, comprising: a scribe seal that extends along at least a portion of a periphery of the integrated chip die, wherein the scribe seal comprises an inner wall, and wherein the inner wall further comprises vertically extending alternating levels of metal and via electrically contacting one another; a detector test structure located laterally adjacent to an inner edge of the inner wall of the scribe seal facing a center portion of the integrated chip die, wherein the detector test structure and the inner wall of the scribe seal are separated by one or more dielectric materials; a first electrical connection between the scribe seal and at least one bond pad; and a second electrical connection between the detector test structure and at least one bond pad located in an active circuitry region; wherein the detector test structure is comprised of a plurality of segments, each one of the plurality of segments electrically connected to a separate bond pad located in the active circuitry region; and wherein the inner wall of the scribe seal and the detector test structure are configured proximately to allow one or more electrical parameters associated therewith, and wherein the first and second electrical connections are configured to be accessed for a monitoring of the one or more electrical parameters, wherein the one or more electrical parameters provides an indication related to a scribe seal integrity of the scribe seal.