Patent ID: 7958285

Claim:
A method of deterministically transferring data from a first clock domain to a second clock domain comprising: writing data to a buffer, wherein the buffer is accessible by both one or more devices in each of the first clock domain and the second clock domain, wherein the data is written to the buffer in an arbitrary phase relationship to at least one of the first clock domain or the second clock domain; communicating a read status from the first clock domain to the second clock domain, wherein the read status is communicated from the first clock domain to the second clock domain when the second clock domain enables the read status to be communicated from the first clock domain to the second clock domain; and reading data from the buffer into the second clock domain at a clock rate of the second domain wherein the first clock domain and the second clock domain are derived from a single test clock signal, wherein the data is read from the buffer into the second clock domain in a synchronous nature including synchronizing the first clock rate and the second clock rate at a respective rational multiple of the single test clock signal, wherein the buffer is a first-in first-out type buffer, wherein the buffer includes at least one read buffer pointer and at least one write buffer pointer to pass data between the first clock domain and the second clock domain, wherein the first clock domain is an I/O clock domain and wherein the second clock domain is a CPU clock domain.