Patent ID: 7966473

Claim:
A method for addressing in read mode a location in one of several memories by means of a coded address coming from an a first instruction, comprising: a) predicting, among the several memories, which memory corresponds to the location to be addressed, b) decoding the address of the location to be addressed and determining the memory to be addressed, c) at the end of step a), using a predicted memory obtained in step a) to determine whether a predicted read access conflicts with a known rewrite access, at least in part by determining whether the known rewrite access is directed to the predicted memory, d) controlling the addressing of the predicted memory at the end of management step c), e) at the end of step b), determining whether the memory to be addressed corresponds to the predicted memory, f) if the memory to be addressed does not correspond to the predicted memory, managing a possible read and rewrite conflict in the memory to be addressed and addressing the location of the memory to be addressed, and g) providing, during a same clock cycle as the act of decoding the address, a control signal to the predicted memory to prepare for a predicted read access directed to the predicted memory.