Patent ID: 7099983

Claim:
A data communications system comprising: a first data communications bus, a plurality of first slave devices coupled to the first data communications bus and a plurality of first master devices coupled to the first data communications bus to initiate data communications in a first format between each respective first master device and a selected first slave device, each first master device having a respective first master device address in the first format; a second data communications bus, a plurality of second slave devices coupled to the second data communications bus and a plurality of second master devices coupled to the second data communications bus to initiate data communications in a second format between each respective second master device and a selected second slave device, each second master device having a respective second master device address in the second format, the first and second formats being incompatible; and a communications module coupled as a slave device to each of the first and second data communications buses, the communications module comprising: a memory device having a plurality of individually addressable locations for storing data from a transmitting first or second master device at an addressable location identified by a second address, an address table associated with each of the addressable locations for associating addresses of the respective addressable location to addresses of respective first and second master devices, the address table being responsive to a first address to associate the second address and a third address to the first address, the first address being the address of a receiving first or second master or slave device in the format of the transmitting first or second master device, the third address being the address of the receiving first or second master or slave device in the format of the receiving first or second master or slave device, and a multiplexer responsive to the third address from a receiving first or second master or slave device for transmitting data between the location in the memory device identified by the second address and the respective first or second data communications bus.