Patent ID: 8587050

Claim:
A semiconductor memory comprising: a semiconductor substrate having a channel region; a first tunnel insulating film formed on the channel region of the semiconductor substrate; a first fine particle layer formed on the first tunnel insulating film, the first fine particle layer comprising a plurality of first conductive fine particles that meet a Coulomb blockade condition; a second tunnel insulating film formed on the first fine particle layer; a second fine particle layer formed on the second tunnel insulating film, the second fine particle layer comprising a plurality of second conductive fine particles that meet the Coulomb blockade condition, wherein a mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles; a third tunnel insulating film formed on the second fine particle layer; a third fine particle layer formed on the third tunnel insulating film, and wherein the second fine particle layer is between the first fine particle layer and the third fine particle layer, the third fine particle layer comprising a plurality of third conductive fine particles that meet the Coulomb blockade condition, wherein a mean particle diameter of the third conductive fine particles is smaller than that of the second conductive fine particles; a fourth tunnel insulating film formed on the third fine particle layer; a charge storage film formed on the fourth tunnel insulating film; a block insulating film formed on the charge storage film; and a gate electrode formed on the block insulating film.