Patent ID: 8866201

Claim:
A power integrated circuit (IC) device comprising: a substrate of a first conductivity type; a well region of a second conductivity type disposed in the substrate, the well region having first, second, and third areas, the first area being laterally adjacent to the second area, and the second area being laterally adjacent to the third area, the second area laterally and physically separating the first area from the third area; a JFET disposed in the first area of the well region, the JFET including: first and second regions of the second conductivity type; and one or more first buried regions of the first conductivity type, the one or more first buried regions defining a plurality of conduction channels that extend substantially across the first area, the first region being disposed at one end and the second region being disposed at an opposite end, of the conduction channels; a dielectric layer formed over at least the second area of the well region, the second area extending vertically from the dielectric layer to a bottom of the well region, the second area being devoid of any buried region of the second conductivity type; a layer of material formed as a resistor over the dielectric layer directly above the second area, the resistor having first and second ends; first and second electrodes, the first electrode being electrically and physically connected to the first end, and the second electrode being electrically and physically connected to the second end, of the resistor, the second electrode also being electrically connected to the second region; a third electrode electrically connected to the first region; a fourth electrode electrically connected to the substrate and to the one or more first buried regions, wherein a voltage provided at the third electrode is substantially proportional to a voltage difference between the second and fourth electrodes when the voltage difference is less than a pinch-off voltage of the JFET, the voltage provided at the third electrode being substantially constant when the voltage difference is greater than the pinch-off voltage of the JFET.