Patent ID: 6961268

Claim:
A semiconductor memory device comprising: memory cells each of which includes a first MOS transistor with a stacked gate including a floating gate formed on a first well region formed at the surface of a semiconductor substrate with a gate insulating film interposed therebetween and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween, and a second MOS transistor having a drain connected to a source of the first MOS transistor; a memory cell array which has the memory cells arranged in a matrix; word lines each of which connects in common control gates of the first MOS transistors in a same row; select gate lines each of which connects in common gates of the second MOS transistors in a same row; a first row decoder which, in a write operation, selects any one of the word lines, applies a positive potential to the selected word line and applies a negative potential to the first well region, and after the write operation, brings the selected word line and the first well region into a floating state; a second row decoder which selects any one of the select gate lines in a read operation; and a control circuit which short-circuits the selected word line and first well region in the floating state, the select gate lines being connected to a negative potential node in a write operation, and after the write operation, the select gate lines being isolated from the negative potential node and connected to the first well region.