Patent ID: 8687655

Claim:
A signal demultiplexer for demultiplexing plural low speed signal transfer frames from a signal storing area of a high speed signal transfer frame, the signal demultiplexer comprising: a terminating unit configured to terminate the high speed signal transfer frame, the high speed signal transfer frame including a first overhead area, the signal storing area, and a second overhead area, wherein a predetermined number of tributary slots for storing the plural low speed signal transfer frames are assigned to the signal storing area; a format conversion unit configured to convert a format of the high speed signal transfer frame output from the terminating unit into a format of a converted frame; a parallelization unit configured to parallelize the converted frame output from the format conversion unit into a number of data columns corresponding to the predetermined number, and to output the data columns; and a separating unit configured to separate the plural low speed signal transfer frames from the predetermined number of the data columns output from the parallelization unit, wherein the format conversion unit converts the format of the high speed signal transfer frame into the format of the converted frame by delaying the signal storing area of the high speed signal transfer frame using the first overhead area and the second overhead area, to include an â€œiâ€ th tributary slot among the predetermined number of the tributary slots assigned to the signal storing area of the high speed signal transfer frame into an arbitrary â€œiâ€ th data column among the predetermined number of the data columns created by parallelization of the high speed signal transfer frame, and to align front positions of the predetermined number of the data columns.