Patent ID: 8830740

Claim:
A semiconductor storage device comprising: a first word line; a first bit line; and N first memory cells (N is an integer of 3 or more) each comprising a first memory element in which memory information is programed by current; and a first transistor in which a source-drain path of the first transistor is connected in parallel to the first memory element, and provided between the first word line and the first bit line; wherein each of the N first memory elements is serially connected to each other; a resistivity of the first transistor is lower than that of the first memory element in a first state and higher than that of the first memory element in a second state; and in a state in which a first value is memorized in all of the N first memory elements, a control in which M first transistors (M is an integer 2 or more and less than N) in the N transistors are set to the second state, and remaining (N-M) transistors are set to the first state, and a first voltage difference is biased for memorizing a second value that is different from the first value to the M first memory elements is performed.