Patent ID: 7418679

Claim:
A method of enabling timing verification of a circuit design implemented in a device having programmable logic and a dedicated processor, said method comprising the steps of: receiving input/output timing information for all input/outputs of a processor core of said dedicated processor over various operating conditions; generating a timing model of said processor core of said dedicated processor of said device for a static timing analysis tool, wherein said timing model for said processor core is based upon data from a provider of said processor core in a first data format; generating timing data for a functional block of said dedicated processor of said device for said static timing analysis tool, wherein said timing data for said functional block is based upon data from a provider of said functional block in a second data format which is different than said first data format; coupling timing data related to said processor core and said timing data for said functional block of said dedicated processor to said static timing analysis tool; extracting resistance and capacitance data for programmable interconnect elements of interconnect circuits associated with functional blocks of said circuit design implemented in said device; coupling said resistance and capacitance data for said programmable interconnect elements of interconnect circuits to said static timing analysis tool; and verifying the performance of said circuit design and said processor core over said various operating conditions using said static timing analysis tool.