Patent ID: 7221615

Claim:
A semiconductor memory chip, comprising: a reception interface section for receiving external write data, command, and address signals in the form of serial signal frames in accordance with a predefined protocol; an intermediate data buffer configured to intermediately store write data received from the reception interface section and to be written into a memory cell array; a memory core including the bank organized memory cell array and a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data into/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more signal frames received from the reception interface section; and a frame decoder providing an interface between the reception interface section and the memory core and including: a command type decoding section arranged for decoding the types of one or more commands included in one or more frames and outputting control signals according to each decoded command type; a memory command evaluator/generator section configured to schedule and prepare single commands for the memory core; an intermediate data buffer command evaluator/generator section configured to schedule and prepare control signals for the intermediate data buffer; and a system command evaluator/generator section configured to prepare and schedule system commands, wherein the memory command evaluator/generator section, intermediate data buffer command evaluator/generator section, and system command evaluator/generator section are operated by control signals received from the command type decoding section in accordance with the decoded type of the commands, and the frame decoder includes an interface to the memory core operating in synchronism therewith by being synchronized together by a frame clock signal.