Patent ID: 7399673

Claim:
A method of forming a charge-trapping memory device having an array of memory cells, the method comprising: providing a semiconductor substrate with a main surface; forming first trenches within said semiconductor substrate, said first trenches having sidewalls; doping said sidewalls to form U-shaped channel regions; depositing a sequence of dielectric layers over the sidewalls of said first trenches, said sequence of dielectric layers comprising a bottom confinement layer, a memory layer and a top confinement layer; filling said first trenches with a conductive material that overlies said sequence of dielectric layers to form gate electrodes and word lines; doping said main surface adjacent to said first trenches to form diffusion regions, said diffusion regions serving as sources/drains of each of said memory cells; forming second trenches parallel to said first trenches, said second trenches formed within said semiconductor substrate thereby subdividing each of said diffusion regions into a first diffusion region adjacent to one of said first trenches of a first charge-trapping memory cell and a second diffusion region adjacent to another one of said first trenches of a second charge-trapping memory cell; filling said second trenches with dielectric material; and performing an implantation after forming of said second trenches and prior to filling said second trenches in order to form a buried channel stop between said U-shaped channel regions of said charge-trapping memory cells for avoiding leakage currents from channel to channel.