Patent ID: 7935593

Claim:
A method of manufacturing dual embedded epitaxially grown semiconductor transistors, the method comprising: depositing a first elongated oxide spacer over first and second transistors of different types, each having a nitride cap formed thereon; depositing a first elongated nitride spacer on the first oxide spacer; depositing a first photoresist block on the nitride spacer above the first transistor; etching the first nitride spacer above the second transistor; implanting a first halo around the second transistor; etching a first recess in an outer portion of the first halo; stripping the first photoresist above the first transistor; forming a first epitaxially grown semiconductor material in the first recess; implanting a first extension in a top portion of the first material; depositing an elongated blocking oxide over the first and second transistors and first extension; depositing a second photoresist block on the blocking oxide above the second transistor and first extension; etching the blocking oxide and first nitride spacer above the first transistor; implanting a second halo around the first transistor; etching a second recess in an outer portion of the second halo; stripping the second photoresist above the second transistor; forming a second epitaxially grown semiconductor material in the second recess; implanting a second extension in a top portion of the second material; etching the blocking oxide above the second transistor; etching the nitride caps from the first and second transistors; depositing a second elongated oxide spacer on the first and second transistors; depositing a second elongated nitride spacer on the second oxide spacer; etching the second nitride spacer to leave nitride sidewalls around gates of the first and second transistors; and implanting deep sources and drains in the first and second transistors.