Patent ID: 6949802

Claim:
A power-to-power semiconductor ESD protection structure on a semiconductor substrate comprising: at least one first doped region within said substrate having opposite dopant than said substrate; a second doped region within each said first doped region having opposite dopant type than each said first doped region; at least one third doped regions within said substrate having opposite dopant type from said substrate, each said third doped region forming a doped pair with each said second doped region; conductor elements connecting said third doped region of one said doped pair to said second doped region of a subsequent said doped pair; a conductor element from said second doped region of a first said doped pair to a first voltage source; and a conductor element from said third doped region of a last said doped pair to a second voltage source; wherein each said first doped region is substantially free of doped regions having the same dopant type as said first doped region.