Patent ID: 7236401

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having memory cells arranged in a matrix form, write/verify circuits which are connected to one-side ends of bit lines in the memory cell array and configured to write data into the memory cell and verify the written data, switching elements which divide the bit lines into plural portions, and a control circuit configured to control the write/verify circuit and switching elements, the control circuit performs a control operation to perform write and verify operations with the switching elements set in an OFF state when a memory cell of an address to be written lies on the write/verify circuit side with respect to the switching elements, writes and saves data into a memory cell lying on the write/verify circuit side with the switching elements set in the OFF state when the memory cell of the address to be written lies farther apart from the write/verify circuit than the switching elements, and then turns ON the switching elements while the write/verify circuit is not being operated and writes the saved data into a memory cell of an address to be written.