Patent ID: 7477560

Claim:
A semiconductor integrated circuit device comprising: two bit lines connected to a memory cell and making a pair; two input nodes making a pair; two sense nodes transmitting a signal difference input to the two input nodes and transmitting an amplified signal according to a signal difference between the two bit lines; an output node outputting the amplified signal from one of the two sense nodes; at least one current adjustment gate adjusting an amount of current flowing through at least one of the two sense nodes; at least one latch circuit controlling the current adjustment gate; two signal lines transmitting a power source voltage and a comparison voltage via the two input nodes respectively, the comparison voltage being obtained by subtracting an absolute value of a predetermined threshold voltage from an absolute value of the power source voltage; and two switching elements provided between the two input nodes and the two signal lines, respectively, wherein the latch circuit switches the current adjustment gate in the case where the amplified signal is an inversion signal of an amplified signal according to the threshold voltage when the power source voltage and the comparison voltage are respectively applied to the two input nodes.