Patent ID: 8208307

Claim:
A method of operating a memory device, the memory device comprising a source, a drain, a channel between the source and the drain, a charge storage layer on the channel, and a gate on the charge storage layer, the source, the drain and the channel located in a substrate, the charge storage layer having a source storage region, a drain storage region, and a channel storage region respectively corresponding to the source, the drain, and the channel, the operation method comprising the following steps: (a) applying a first positive voltage to the gate for injecting electrons into the channel storage region by FN tunneling; (b) applying a first negative voltage to the gate for removing electrons from the channel storage region by FN tunneling; (c) applying a second positive voltage and a third positive voltage to the gate and the drain respectively for injecting electrons into the drain storage region by channel hot electron injection; and (d) applying a fourth positive voltage to the drain for removing electrons from the drain storage region by FN tunneling.