Patent ID: 7049203

Claim:
A method for forming a semiconductor device, the method comprising: forming a first interlayer insulating layer on a semiconductor substrate, the first interlayer insulating layer having a contact plug therein between a pair of gate stacks; forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a contact pad therein, the contact pad electrically connected to the contact plug; forming an etch stop layer on the second interlayer insulating layer; forming a first sacrificial layer on the etch stop layer; forming a first storage node opening in the first sacrificial layer; forming a pad-shaped storage node in the first storage node opening; forming a second sacrificiallayer overlying the resulting structure including the pad-shaped storage node; forming a second storage node opening in the second sacrificial layer overlying the pad-shaped storage node; forming a cup-shaped storage node in the second storage node opening, wherein the cup-shaped storage node comprises a single cylindrically shaped structure; and removing the first and the second sacrificial layers to form a capacitor lower electrode.