Patent ID: 7236036

Claim:
A pulse generating apparatus; the apparatus receiving a clock signal at an input locus and presenting a pulsed output signal at an output locus; the apparatus comprising: (a) a latch device having a set port, a reset port and an output port; one of said set port and said reset port being coupled with said input locus; (b) a logic gate having a first logic input locus, a second logic input locus and a logic output locus; said first logic input locus being coupled with said input locus; said second logic input locus being coupled with said output port; said logic gate effecting a logical comparison of signals applied to said first logic input locus and said second logic input locus and presenting a logical result signal at said logic output locus representing said logical comparison; and (c) a delay device having a delay input locus and a delay output locus; said delay input locus being coupled with said logic output locus; said delay device receiving delay input signals at said delay input locus and presenting delayed output signals at said delay output locus; said delayed output signals being delayed by a predetermined delay interval with respect to said delay input signals; said delay output locus being coupled with said output locus and coupled with said latch device at a feedback port; said feedback port being a selected one of said set port and said reset port that is not coupled with said input locus; said logic gate and said delay device cooperating to ensure that signals provided to said feedback port are inverted with respect to signals presented at said first logic input locus.