Patent ID: 7265433

Claim:
A chip, comprising: a bond pad; at least one common node; an on-chip matching network having a first terminal conductively connected to said bond pad and a second terminal conductively connected to said common node; a wiring trace connecting said on-chip matching network to a circuit of said chip; said on-chip matching network including: an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to said bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential; a first inductor coupled to provide a first inductive path between said bond pad and said wiring trace; a termination resistor having a first terminal connected to said common node; a second inductor coupled to provide a second inductive path between said wiring trace and a second terminal of said termination resistor; and a first well having a p-type conductivity and a depletion isolation region overlying said first well, wherein said first and second inductors include first and second overlapping spiral conductors having mutual inductance, said first and second conductors overlying said depletion isolation region.