Patent ID: 7640467

Claim:
A semiconductor memory, comprising: a memory core including a plurality of memory cells; a coincidence detection circuit for making a comparison between a first portion of output data in the memory core and a second portion of output data in the memory core, thereby detecting whether or not the compared data coincides; an output data compression circuit for outputting either one of the first portion of output data or the second portion of output data when the coincidence detection circuit detects that the first portion and second portion of output data coincide, and for outputting particular data when the coincidence detection circuit does not detect that the first portion and second portion of the output data coincide; a control circuit for controlling writing of data inputted to the semiconductor memory; and a data input switching circuit for selecting first input data and second input data, the second input data having fewer bits than the first input data, the data input switching circuit for outputting to the memory core one of the first input data and second input data depending on an output from the control circuit, wherein the second input data is writable into portions of the memory core corresponding to first and second portions of input data when the data input switching circuit outputs the second input data to the memory core.