Patent ID: 8560295

Claim:
A method of simulating a circuit design, comprising using one or more processors to perform steps including: scheduling one or more processes that are specified in a hardware description language (HDL) description of the circuit design in an active process set, the active process set indicating processes to be modeled as concurrently executing processes; simulating concurrent execution of the one or more processes in the active process set, the simulating execution of each of one or more processes including: in response to a first process of the one or more processes calling a procedure specified by the HDL description: generating a second process configured to trigger execution of the procedure; halting simulation of concurrent execution of the one or more processes; replacing the first process in the active process set with the second process; and resuming simulation of concurrent execution of the one or more processes within the active process set, beginning with simulation of the second process; and in response to completing simulation of the second process: halting simulation of concurrent execution of the one or more processes; replacing the second process in the active process set with the first process; and resuming simulation of concurrent execution of one or more processes within the active process set, beginning with resuming simulation of the first process.