Patent ID: 7089368

Claim:
A microprocessor apparatus, providing for exclusive prefetch of a block of data from memory, the apparatus comprising: translation logic, configured to translate an extended block prefetch instruction into a micro instruction sequence that directs a microprocessor to prefetch a specified number of cache lines in an exclusive state, wherein said extended block prefetch instruction is encoded to direct said microprocessor to prefetch said specified number of cache lines in said exclusive state; and execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus that requests said specified number of cache lines in said exclusive state, wherein said specified number of cache lines comprises data entities that are to be subsequently modified, and wherein prefetching said specified number of cache lines in said exclusive state occurs in parallel with execution of program instructions prior to execution of subsequent store instructions that direct the microprocessor to modify said data entities.