Patent ID: 8270462

Claim:
An adaptive equalizer circuit, comprising: an equalizer circuit configured to produce an output data signal by correcting an input data signal waveform for each unit time in response to an equalizing factor; a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at a predetermined timing indicated by a clock signal synchronized with the output data signal; a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing indicated by the clock signal; and a control circuit configured to detect, multiple times, a predetermined data pattern having consecutive data items of a first logic value followed by a data item of a second logic value and further followed by a data item of the first logic value, and to adjust the equalizing factor such that a value of a detection result obtained by the data detecting circuit and a value of a detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times, the equalizing factor being adjusted such that a data width of the predetermined data pattern becomes equal to one unit time.