Patent ID: 7332392

Claim:
A method for fabricating a trench-capacitor dynamic random access memory (DRAM) device, comprising: providing a semiconductor substrate having thereon a shallow trench isolation (STI) structure; forming a pad oxide layer and a pad nitride layer over the semiconductor substrate; etching a capacitor deep trench into the pad nitride layer, pad oxide layer and the semiconductor substrate; forming a collar oxide layer on inner surface of the capacitor deep trench; etching away the collar oxide layer at a bottom of the capacitor deep trench to expose the bottom; forming a conformal first doped polysilicon layer on the collar oxide layer and on the bottom of the capacitor deep trench, wherein the first doped polysilicon layer acts as a capacitor bottom electrode; forming a capacitor dielectric layer on the first doped polysilicon layer; forming a second doped polysilicon layer on the capacitor dielectric layer, wherein the second doped polysilicon layer fills the capacitor deep trench and the second doped polysilicon layer acts as a capacitor top electrode; stripping the pad nitride layer; performing an ion implantation process to form a deep ion well in the semiconductor substrate; and forming a passing gate insulation (PGI) layer on the second doped polysilicon layer and on the STI structure.