Patent ID: 8003538

Claim:
A method of manufacturing an integrated circuit on a surface of a substrate comprising: forming a first partial structure on the surface of the substrate, the first partial structure comprising two first line elements running in parallel to each other; applying a spacer layer on the substrate and the first partial structure, thereby providing a cutout between the two first line elements; introducing filling material into the cutout in a way as to expose a surface of the spacer layer, thereby forming a second line element as part of a second partial structure; removing the spacer layer arranged between the second line element and the two first line elements; applying a further spacer layer on the substrate, thereby providing further cutouts between the second line element and each one of the two first line elements; introducing further filling material into the further cutouts in a way as to expose a surface of the further spacer layer, thereby forming third line elements as part of a third partial structure between the second line element and each one of the two first line elements; and removing the further spacer layer arranged between neighboring line elements of the first, second and third partial structure.