Patent ID: 8324735

Claim:
A semiconductor device comprising: a plurality of first output pads formed along a first edge of an outer periphery of the semiconductor device; a plurality of second output pads formed along a second edge at an opposite side of the semiconductor device from the first edge, and a third edge adjoining the first edge and the second edge; a plurality of internal circuits, each of which is provided with an output terminal connected with an output pad of one of the first output pads and the second output pads, the plural internal circuits being formed along the first edge at a central portion of the semiconductor device such that the output terminals are formed along a straight line and are respectively arranged along a side of the internal circuits at which the first edge is disposed; wherein the plurality of internal circuits comprises a leftmost internal circuit located farthest to the left of the plurality of internal circuits; a plurality of first lines, each of which connects one of the output terminals of the plurality of internal circuits with one of the plurality of first output pads; and a plurality of second lines, each of which connects one of the output terminals of the plurality of internal circuits with one of the plurality of second output pads, resistance values per unit of wiring length being lower in the second lines than in the first lines; wherein each of the plurality of second lines extends on the left of the leftmost internal circuit to reach the second output pad.