Patent ID: 7585541

Claim:
A method of producing a multilayer printed circuit board comprising: providing a structure having a substrate, at least one lower conductor circuit formed over the substrate and having a surface at least partially roughened, and an outermost insulating layer formed over the substrate and the at least one lower conductor circuit; forming at least one opening for a viahole structure extending from the outermost insulating layer to the at least one lower conductor circuit; subjecting the outermost insulating layer to an electroless plating so as to form an electroless plated film; forming a plating resist on the electroless plated film; subjecting the plating resist and the electroless plated film over the outermost insulating layer to an electrolytic plating so as to form an electrolytic plated film; removing the plating resist; etching and removing the electroless plated film exposed by a pattern of the plating resist to form at least one outermost conductor circuit comprising the electroless plated film and the electrolytic plated film, the viahole structure electrically connecting the lower conductor circuit and the outermost conductor circuit, and a pad comprising a portion of the viahole structure; roughening a surface of the pad; forming a solder resist layer having at least one opening portion on the pad and covering a peripheral edge of the pad; providing a solder on a portion of the pad exposed from the opening portion of the solder resist layer; and reflowing the substrate to form solder bumps.