Patent ID: 8704815

Claim:
A display device, comprising: a first voltage generator, configured to generate a gate high voltage, wherein the gate high voltage is a first voltage during a first period and the gate high voltage is a second voltage after the first period, and the first voltage is higher than the second voltage; a second voltage generator, configured to generate a gate low voltage; a timing controller, generating a start signal, a clock signal and an inverse signal; a level shifter, coupled to the first voltage generator, the second voltage generator and the timing controller, the level shifter shifting voltage levels of the start signal, the clock signal and the inverse signal according to the gate high voltage and the gate low voltage; and a display panel, comprising: a substrate; a pixel array, disposed on the substrate; and a plurality of shift registers disposed on the substrate, and the shift registers coupled to the level shifter respectively, the shift registers sequentially outputting a plurality of scanning signals for driving the pixel array according to the shifted start signal, the shifted clock signal and the shifted inverse signal, wherein the first voltage generator comprises: a first pulse width modulator, having a first input terminal, a second input terminal and an output terminal, the first input terminal of the first pulse width modulator coupled to a first reference voltage, the first pulse width modulator outputting a first driving signal from the output terminal thereof according to the first reference voltage and a voltage of the second input terminal thereof; a first charge pumping circuit, having an input terminal and an output terminal, the input terminal of the first charge pumping circuit coupled to the first pulse width modulator for receiving the first driving signal and outputting the gate high voltage from the output terminal thereof according to the first driving signal; a first resistance, coupled between the output terminal of the first charge pumping circuit and the second input terminal of the first pulse width modulator; a second resistance, coupled between the second input terminal of the first pulse width modulator and a ground voltage; and an adjusting circuit, coupled to the second input terminal of the first pulse width modulator for reducing the voltage of the second input terminal of the first pulse width modulator during the first period and restoring the voltage of the second input terminal of the first pulse width modulator after the first period.