Patent ID: 7139848

Claim:
A system comprising: configurable system logic having programmable logic; a direct memory access (DMA) controller adapted to operate in a descriptor mode; a configurable system interconnect coupled between the configurable system logic and the DMA controller; an input/output (I/O) device coupled to the DMA controller by way of the configurable system interconnect, wherein the I/O device is implemented in the programmable logic and the DMA controller terminates a DMA transfer and clears a current transfer counter before a terminal count is reached upon receiving an early termination request signal from the I/O device, and wherein the DMA controller sends an acknowledge signal to the I/O device in response to receiving the early termination request signal; and a descriptor table storing commands to carry out a transfer, the descriptor table being updated with a reduced transfer count in response to receiving the early termination request signal from the I/O device when the DMA controller is operating in the descriptor mode.