Patent ID: 7675581

Claim:
A thin film transistor array, comprising: a substrate; a plurality of scan lines disposed over the substrate; a plurality of data lines disposed over the substrate, wherein the scan lines and the data lines defining a plurality of pixel areas on the substrate; a plurality of thin film transistors, each of the thin film transistors being disposed in one of the pixel areas, wherein the thin film transistors are driven through the scan lines and the data lines, and each of the thin film transistors comprises a gate, a source and a drain; a plurality of common lines disposed over the substrate, each of the common lines being disposed between two adjacent scan lines; a plurality of top electrodes, each of the top electrodes being disposed in one of the pixel areas over one of the common lines, thereby forming a storage capacitor; a plurality of connection lines, each of the connection lines disposed between and electrically connected to the drain of each thin film transistor and one of the top electrodes, respectively, each of the connection lines has a first portion and a second portion, wherein each first portion is connected between the drain of each thin film transistor and one of the second portions, and the drains of the thin film transistors and the second portions are separated by the first portions; and a plurality of pixel electrodes, each of the pixel electrodes being disposed in one of the pixel areas over one of the top electrodes and one of the connection lines, wherein the drain of each thin film transistor is electrically connected to one of the pixel electrodes without the connection lines therebetween, and the first portion of each connection line is not overlapped by the pixel electrode.