Patent ID: 8111558

Claim:
A nonvolatile memory cell in an array of memory cells, comprising: a first transistor having a floating gate coupled to a gate terminal, a source terminal coupled to receive a read enable signal and a drain terminal; a first control capacitor structure having a first terminal coupled to a first data signal line and a second terminal coupled to said first floating gate; a first tunneling capacitor structure having a first terminal coupled to a tunneling control signal line and a second terminal coupled to said first floating gate; and a first readout switch having a first terminal coupled to said drain terminal of the first transistor and a second terminal coupled to a first readout node, a control node of said first readout switch coupled to a row select signal line, the first readout switch having first current at said first terminal substantially equal to drain current of the first transistor in a mode for performing a write operation on another nonvolatile memory cell in a same column of the array of the memory cells.