Patent ID: 8006031

Claim:
Memory system for reading and writing logical sectors, which is attached to a host system by means of a host bus (HB), and which contains a memory controller (FC) having an internal memory (IR) and flash memory chips (F 1 . . . Fn), which are organized in individually deletable memory blocks, said blocks containing a plurality of writeable and readable memory sectors for the storage of logical sectors, these logical sectors for communication with the host system being temporarily stored in a plurality of pairs of alternating sector buffers (SBn 1 , SBn 2 ) and being transmitted directly, by means of at least one direct-flash-access-unit (DFAn), between the sector buffers (SB 1 n, SBn 2 ) and the flash memory chips (F 11 . . . Fnx), wherein the flash memory chips (Fxy) are connected by memory buses (MBn) to several pairs of sector buffers (SB 1 n, SBn 2 ) via a matrix switch (CB), wherein the sector buffers are connected to the host bus (HB) by an input multiplexer (MUX 1 ), characterized in that a memory bus (MBn) and a direct-flash-access-unit (DFAn) are assigned to each pair of sector buffers (SBn 1 , SBn 2 ), and one sector buffer is assigned to the host bus (HB) the other sector buffer is assigned to the memory controller (FC) or to a memory bus (MBn) with a direct-flash-access-unit (DFAn), and that after each transmission of a sector the assignment of the sector buffers is switched.