Patent ID: 8890320

Claim:
A semiconductor device comprising: a first line of vias including a first via and a second via immediately adjacent to the first via; a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via; and a third line of arranged immediately adjacent to and parallel to the second line of vias, the third line of vias including a fifth via immediately adjacent to the third via and the fourth via, the third line of vias further including a sixth via immediately adjacent to the fifth via, the third via, and the fourth via, wherein the shortest distance between the second via and the fourth via is greater than the shortest distance between the first via and the third via, wherein an imaginary line connecting centers of the first via and the fifth via is positioned between the third via and the fourth via and is not perpendicular to an imaginary line connecting centers of the first line of vias, wherein the third via is position between the imaginary line connecting the centers of the first via and the fifth via and an imaginary line connecting centers of the second via and the sixth via, and wherein an imaginary line connecting centers of the second via and the third via is at an obtuse angle with respect to an imaginary line connecting centers of the third via and the fifth via.