Patent ID: 7216218

Claim:
A computer system comprising: a memory to store a program having a plurality of instructions, wherein at least one instruction implements a gather operation and at least one instruction implements a scatter operation; a decode unit for decoding instructions supplied to the decode unit from the memory, said decode unit issues an address to said memory and receives an instruction from said memory, said decode unit transmits a first instruction portion along a first execution channel of the computer system and a second instruction portion along a second execution channel, wherein each execution channel containing at least one processing unit and at least one load/store unit; a register file having a plurality of registers each having the same bit capacity and addressable via at least two register address ports, one of said at least two ports being associated with said first execution channel of the computer system and the other of said at least two ports being associated with said second execution channel of the computer system; a register address supply path for supplying said processing units and said load/store units access to said register address ports; and at least one cache memory associated with the processor holding data objects accessed by the processor; wherein each of said load/store units contains memory adapted to be directly accessible for implementing scatter and gather operations, wherein said memory of at least one of said load/store units stores instant and subsidiary data values associated with said scatter and gather operations.