Patent ID: 7477113

Claim:
A linear voltage-controlled capacitance circuit, comprising: a plurality of differentially coupled metal-oxide-semiconductor (MOS) varactor pairs, each MOS varactor pair comprising a first varactor device and a second varactor device, all varactor devices in the MOS varactor pairs operable to receive a same tuning voltage, each MOS varactor pair operable to receive a bias voltage unique to that MOS varactor pair, the circuit operable to generate a positive tank node signal and a negative tank node signal based on the tuning voltage and the bias voltages; a tuning node coupled to each of the varactor devices in the MOS varactor pairs, the tuning node operable to receive the same tuning voltage and to provide the same tuning voltage to each MOS varactor pair; a plurality of first capacitors, each first capacitor coupled to (i) a source terminal and a drain terminal of each of the varactor devices through the tuning node and (ii) a ground potential; a plurality of second capacitors, each second capacitor coupled to a gate terminal of one of the first varactor devices; and a plurality of third capacitors, each third capacitor coupled to a gate terminal of one of the second varactor devices; wherein the first capacitors are not connected to the same terminals of the varactor devices as the second and third capacitors.