Patent ID: 8654601

Claim:
A system comprising: a memory device including: non-volatile memory; a clock input configured to receive a clock signal; a common command and data input configured to receive input data and command data at different times; a first control input configured to receive a first of two control signals; a second control input configured to receive a second of the two control signals; core circuitry configured to execute an operation on the non-volatile memory corresponding to the command data; and latch circuitry configured to: latch the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common command and data input, and latch the input data in synchronization with both rising and falling edges of the clock signal; and a memory controller communicatively coupled to the memory device, and the memory controller being configured to source the input data to the memory device.