Patent ID: 8499126

Claim:
A memory control system, comprising: a first queue unit for temporarily storing a plurality of first request instructions, which corresponds to a line-by-line access to a memory; a second queue unit for temporarily storing a plurality of second request instructions, which corresponds to a block access to the memory; a first transforming unit for selectively re-assigning memory addresses corresponding to the first request instructions; a second transforming unit for selectively re-assigning memory addresses corresponding to the second request instructions; an arbiter, coupled to the first transforming unit and the second transforming unit, for performing immediate scheduling of the first request instructions and the second request instructions to the memory; and a control unit for comparing bandwidths of the first request instructions with bandwidths of the second request instructions, and controlling the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.