Patent ID: 8078828

Claim:
A memory mapped register file, comprising: an address encoder configured to receive a source index input having a length of T−1 bits, the source index input identifying one of a plurality of unbanked registers, receive a processor mode input to identify one of P processor modes, where P is greater than two, and generate an encoded address having a length of T bits based on (i) the source index input and (ii) the processor mode input; memory including the plurality of unbanked registers, wherein the encoded address identifies one of the plurality of unbanked registers associated with one of the P processor modes; a second address encoder configured to receive a write index input having a length of T−1 bits, the write index input identifying one of the plurality of unbanked registers, receive the processor mode input, and generate a second encoded address having a length of T bits based on (i) the write index input and (ii) the processor mode input; and a write data input, wherein the memory is configured to input data from the write data input to one of the plurality of unbanked registers identified by the second encoded address.