Patent ID: 6890822

Claim:
A method for manufacturing a semiconductor device, comprising: defining a first voltage region, a second voltage region, and a third voltage region on a substrate, the first, second, and third voltage regions being configured to handle first, second, and third voltage levels, respectively, that are different from each other; forming a nitride layer overlying the first, second, and third voltage regions; forming an oxide layer overlying the nitride layer; patterning the oxide layer to expose a portion of the nitride layer overlying the first voltage region; removing the exposed portion of the nitride layer using a wet etch process; forming a first gate oxide layer overlying the first voltage region; removing portions of the oxide layer and the nitride layer overlying the second and third voltage regions; selectively implanting impurities into the third voltage region while preventing the impurities from being provided in the second voltage region; and forming a second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region simultaneously, the second gate oxide being thicker than the third gate oxide.