Patent ID: 8230160

Claim:
A flash memory storage system, comprising: a flash memory chip, having a plurality of physical blocks, wherein each of the physical blocks has a plurality of physical addresses; a connector, configured to couple to a host system; a flash memory controller, coupled to the flash memory chip and the connector; and a file system analysis unit, configured in the host system, wherein the flash memory controller is configured to configure a plurality of logical addresses and map the logical addresses to at least part of the plurality of physical addresses of at least part of the plurality of physical blocks, wherein the host system uses a file system to access the logical addresses, and the file system has at least one file system space information, wherein the flash memory controller identifies at least one deleted logical address among the logical addresses and marks data in a physical address mapped to the at least one deleted logical address as invalid data, wherein data stored in the at least one deleted logical address has been deleted in the at least one file system space information, wherein the file system analysis unit scans the at least one file system space information to identify at least one idle logical address among the logical addresses, and the flash memory controller identifies the at least one idle logical address as the at least one deleted logical address.