Patent ID: 7592199

Claim:
A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising: implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate; forming at least one shallow trench isolation (STI) structure in the semiconductor substrate; forming at least one P-type well laterally separating the N+ region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region; forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface; creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion width, and the N+ region having a lower boundary more than about 0.8 microns below the surface.