Patent ID: 8214773

Claim:
A method of forming integrated circuits for a wafer, the method comprising: providing an E-Beam direct write (EBDW) system; generating a first grid for the wafer, wherein the first grid comprises grid lines; wherein the grid lines of the first grid are synchronized with grid lines of a second grid of the EBDW system, so that at least potions of grid lines of the first grid are aligned to portions of grid lines of the second grid; wherein the second grid of the EBDW system comprises grids formed of boundaries of sub-fields of the EBDW system, and wherein the grid lines of the first grid overlap at least some of the boundaries of the sub-fields; laying out an integrated cicuit for the wafer, wherein substantially non-sensitive features in the integrated circuit are placed crossing the grid lines of the first grid and sensitive features in the integrated circuit are not placed crossing the grid lines of the first grid, and wherein the sensitive features belong to sensitive cells selected from the group consisting essentially of inverters, NAND gates, NOR gates, multiplexers, latches, flip-flops, and combinations thereof, and the non-sensitive standard cells are selected from the group consisting essentially of a filler cell and a decoupling-capacitor cell; and performing an EBDW on the wafer or a mask using the EBDW system.