Patent ID: 8006212

Claim:
A computer-executed method for facilitating floorplanning for three-dimensional integrated circuits (3D ICs), the method comprising: receiving a number of circuit blocks; receiving a set of parameters for a 3D structure, wherein the parameters include one or more of: die area; maximum total wirelength; maximum number of through-silicon vias (TSVs) on a respective layer in the 3D structure; and aspect ratio of a respective layer in the 3D structure; and computing, by computer, a floorplan for the circuit blocks across a set of layers in the 3D structure by optimizing a cost function, wherein the cost function is based on a total area used by the circuit blocks, a total wirelength used by the circuit blocks, a total number of TSVs used by the circuit blocks, an aspect ratio of an area occupied by circuit blocks in each layer in the 3D structure, and a highest temperature produced by the circuit blocks for a given floorplan.