Patent ID: 6903913

Claim:
An electrostatic discharge (ESD) protection circuit, suitable for application to a mixed-voltage integrated circuit (IC), comprising: at least one cascoded transistor pair, each cascoded transistor pair comprising: a first N-type metal oxide semiconductor (NMOS) transistor, formed on a P-type semiconductor layer, having a gate region, a drain region and a source region, the drain region coupled to a pad of the mixed-voltage IC, and the gate region coupled to a low power supply of the mixed-voltage IC; and a second NMOS transistor, formed on the P-type semiconductor layer, having a gate region, a drain region and a source region, the source region of the second NMOS transistor coupled to a ground plane of the mixed-voltage IC; wherein the source region of the first NMOS transistor is coupled to the drain region of the second NMOS transistor, and the drain region of the first NMOS transistor, the P-type semiconductor layer and the source region of the second NMOS transistor form the collector, the base and the emitter of a parasitic NPN bipolar junction transistor (BJT); and a triggering current generator, for providing a triggering current to the base, to trigger the NPN BJT and release the ESD current during an ESD event, and, under normal operations, turning off the parasitic NPN; wherein the triggering current generator comprises: a current generator, having an input end coupled to the pad during an ESD event and an output end coupled to the base of the parasitic NPN BJT; and an ESD detector, with a detecting end coupled to the pad during an ESD event, for triggering the current generator when an ESD event is detected; wherein the current generator comprises: a third NMOS transistor, having a drain as the input end, and a source; and a first PMOS transistor, having a source coupled to the source of the third NMOS transistor, a drain as the output end of the current generator, and a gate.