Patent ID: 8620984

Claim:
A minimum mean square error equalization processor, comprising: a first systolic array configured to operate in first and second modes and receive an input set of time division multiplexed matrices from a plurality of channel matrices; wherein the first systolic array operating in the first mode performs triangularization on the input set of matrices to produce a first set of time division multiplexed output matrices, and operating in the second mode performs back-substitution on the first set to produce and output a second set of time division multiplexed output matrices; a second systolic array configured to operate in first and second modes and receive the second set of matrices from the first systolic array and the input set of matrices; wherein the second systolic array operating in the first mode performs left multiplication on the second set of matrices with the input set of matrices to produce a third set of time division multiplexed output matrices; wherein the second systolic array operating in the second mode: performs cross diagonal transposition on the third set of matrices to produce a fourth set of time division multiplexed output matrices; and performs right multiplication on the second set of matrices with the fourth set of matrices to produce a fifth set of time division multiplexed output matrices; wherein a set of outputs of the first systolic array is coupled to a first set of corresponding inputs of the second systolic array; and wherein the first systolic array is configured to switch from the first mode to the second mode after triangularization is completed, and the second systolic array is configured to switch from the first mode to the second mode after left multiplication is completed.