Patent ID: 7747020

Claim:
A processor comprising; a plurality of pipeline stages to perform an inner loop of a hash algorithm, the plurality of pipeline stages comprising at least as many pipeline stages as there are iterations of the inner loop to be performed and as many pipeline stages as there are chaining variables to be used in the inner loop, wherein each iteration of the inner loop is performed by a dedicated pipeline stage, each pipeline stage comprises an adder, a shifter, and logic to perform function, and the plurality of pipeline stages comprises 88 pipeline stages to process 512 bits of data, and control logic to schedule operations to be executed within the plurality of pipeline stages, wherein operations are to be scheduled by the control logic and executed by the plurality of pipeline stages so as to minimize data dependencies between iterations of the inner loop to be performed, wherein the hash algorithm is chosen from a group of secure hash algorithms (SHA) consisting of SHA-1, SHA-128, SHA-196, SHA-256, and message digest 5 (MD5), and is to be performed at an operating frequency equal to that of the adder.