Patent ID: 8275978

Claim:
An apparatus including a microprocessor, the apparatus comprising: a pipeline circuit that pipelines a plurality of instructions for the microprocessor; a branch circuit, coupled to the pipeline circuit, that operates to store a plurality of branch information, each branch information comprising operands from a conditional branch instruction including a branch position and a jump destination, the conditional branch instruction further including a condition operand; and a control circuit, coupled to the pipeline circuit and the branch circuit, that stores a first branch information from the branch position and jump destination operands of a first conditional branch instruction to the branch circuit when a condition associated with the first conditional branch instruction is met upon execution of the first conditional branch instruction, and retrieves a second branch information from the branch circuit and loads the pipeline circuit with an instruction located at the jump destination of the second branch information when the branch position of the second branch information matches a program count value, without flushing the pipeline circuit.