Patent ID: 7532496

Claim:
A memory cell of an electrically programmable read only memory (EPROM), the memory cell comprising: a select transistor that comprises an n-channel metal oxide semiconductor (NMOS) transistor having a gate oxide layer that has a first value of gate oxide thickness; a breakdown transistor connected to the select transistor, wherein the breakdown transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor having a gate oxide layer that has a second value of gate oxide thickness; and a program transistor connected to the breakdown transistor, wherein the program transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor wherein the NMOS select transistor provides a first value of voltage to the gate oxide layer of the PMOS breakdown transistor; the PMOS program transistor provides a second value of voltage to the gate oxide layer of the PMOS breakdown transistor; and the combined value of voltage of the first and second values of voltage is sufficient to cause the gate oxide layer of the PMOS breakdown transistor to break down.