Patent ID: 6887782

Claim:
A method for reducing spiking in a semiconductor device undergoing a process temperature in excess of about 400Â° C. during a process step therefor and containing at least one transistor and at least one heater resistor in a heater resistor area adjacent the transistor on a silicon semiconductor substrate, the method comprising the steps of: providing contact openings adjacent at least the one transistor for metal contacts to the at least one transistor; depositing a diffusion barrier/resistive layer in the contact openings and in the heater resistor area, the barrier/resistive layer comprising a layer selected from the group consisting of TaN, Ta/TaAl, TaN/TaAl, TiWN, TaAlN, TiN, Ta(N x , O y ), WSi(N x , O y ), TaSi, TaSiN, WSiN, and TaSi(N x , O y ); and depositing a conductive layer on the barrier/resistive layer to provide connection between a power source and the at least one heater resistor and at least one transistor, wherein a step of patterning and etching a barrier layer in the heater resistor area prior to depositing a resistive layer is avoided.