Patent ID: 7414441

Claim:
An output buffer circuit, comprising: an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and an internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and comprises a plurality of switching elements and resistors so as to detect an offset voltage to be compensated; wherein the input stage includes: a first NMOS transistor of which the gate receives the input voltage; a first PMOS transistor of which the gate receives the input voltage; a second NMOS transistor of which the gate receives the output voltage; a second PMOS transistor of which the gate receives the output voltage; a third NMOS transistor that biases the first and second NMOS transistors; and a third PMOS transistor that biases the first and second PMOS transistors.