Patent ID: 7006378

Claim:
A nonvolatile memory device comprising: a string of MONOS cells connected drain to source wherein each said MONOS cell comprises: a wordline gate overlying a channel region in a substrate; first and second control gates each overlying a channel region in said substrate wherein said wordline gate channel region is laterally between said first and second control gate channel regions, wherein an ONO layer is vertically between said control gates and said substrate, and wherein the nitride layer of said ONO layer forms a charge storage site for each said control gate; and first and second doped regions, forming a source and a drain, in said substrate wherein said wordline gate channel region and said control gate channel regions are between said first doped region and said second doped region; and first and second transistors connecting topmost said MONOS cell to a first bit line and bottom most said MONOS cell to a second bit line.