Patent ID: 8168530

Claim:
A method of forming a one transistor DRAM device, comprising: preparing a substrate with an insulating layer and a first semiconductor layer; forming a first gate pattern on the first semiconductor layer; forming a first source region and a first drain region and a first floating body in the first semiconductor layer adjacent to the first gate pattern, the first source region and the first drain region being in contact with the insulating layer and the first floating body being between the first source region and the first drain region; forming a first interlayer dielectric to cover the first gate pattern; forming a second semiconductor layer on the first interlayer dielectric; forming a second gate pattern on the second semiconductor layer; forming a second source region and a second drain region and a second floating body in the second semiconductor layer adjacent to the second gate pattern, the second source region and the second drain region being in contact with the first interlayer dielectric and the second floating body being between the second source region and the second drain region; forming a second interlayer dielectric to cover the second gate pattern; forming a bitline contact to penetrate the second interlayer dielectric and the first interlayer dielectric and electrically connect the first drain region to the second drain region; and forming a source line contact to penetrate the second interlayer dielectric and the first interlayer dielectric and electrically connect the first source region to the second source region; wherein the first gate pattern and the second gate pattern are formed on the first floating body and the second floating body, respectively, and are independently controllable.