Patent ID: 7525358

Claim:
An apparatus for adjusting a single-ended internal clock signal in an integrated circuit (IC) that receives a fully-differential external clock signal, the apparatus comprising a clock receiver circuit that is arranged to generate the single-ended internal clock signal in response to the fully-differential external clock signal, the clock receiver circuit comprising: a differential amplifier circuit that is arranged to provide a fully differential output that is continuously responsive to the fully-differential external clock signal, wherein the fully differential output corresponds to a first control voltage and a second control voltage; a first current source circuit that is responsive to the first control voltage, wherein the first current source is referenced to a power supply terminal; a second current source circuit that is responsive to the second control voltage, wherein the second current source circuit is referenced to the power supply terminal; a current mirror circuit that includes a first terminal that is coupled to the first current source and a second terminal that is coupled to the second current source, wherein the first current source circuit is arranged to couple a first current to the first terminal and the second current source circuit is arranged to couple a second current to the second terminal, wherein the internal clock signal is sensed from either the first terminal or the second terminal of the current mirror circuit; and a means for continuously adjusting either the first current or the second current in response to a first and second differential output such that an average value associated with the single-ended internal clock signal is substantially equal to a trip-point that is associated with a single-ended logic circuit that receives the single-ended internal clock signal; wherein the means for continuality adjusting includes a differential comparator that generates the first and second differential output in response to a comparison between the sensed internal clock signal and a target signal that is a substantially constant voltage associated with the trip-point.