Patent ID: 8127201

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell array including a plurality of nonvolatile memory cells; a read-out circuit outputting data stored in the memory cell array asynchronously in response to an input address signal; a data latch circuit latching the data outputted from the read-out circuit and outputting the latched data; an error correcting circuit detecting an error in the latched data, correcting the error, and outputting the corrected signal; a selection circuit outputting a selection signal for selecting a location of the memory cell to fail; and an error making circuit receiving a test mode signal, making either the data outputted from the read-out circuit or the latched data fail and transmitting the failed data to a certain circuit in the next stage in response to the selection signal when the test mode signal is activated, and transmitting either the data outputted from the read-out circuit or the latched data to the certain circuit in the next stage when the test mode signal is not activated.