Patent ID: 8227863

Claim:
A semiconductor memory device comprising: a semiconductor layer over a substrate, the semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other; a first insulating layer over and in contact with an upper surface and a side surface of the semiconductor layer; a floating gate over the channel formation region with the first insulating layer interposed therebetween; a second insulating layer over the floating gate, the second insulating layer comprising a silicon nitride layer over the floating gate and a silicon oxide layer over the silicon nitride layer, wherein a thickness of the silicon nitride layer is smaller than a thickness of the silicon oxide layer; and a control gate over the floating gate with the second insulating layer interposed therebetween, wherein the semiconductor layer has a first region having a conductivity type which is different from a conductivity type of the pair of impurity regions, wherein the first region extends from one of the pair of impurity regions to the other of the pair of impurity regions and is in contact with the channel formation region, wherein the substrate is selected from the group of a glass substrate, a plastic substrate and a quartz substrate, and wherein the floating gate includes a semiconductor material, a band gap of the semiconductor material is smaller than a band gap of the semiconductor layer.