Patent ID: 6995437

Claim:
A semiconductor device, comprising: a substrate having a core region and a periphery region; a core dielectric layer formed over core region of the substrate and a periphery region dielectric layer formed over the periphery region of the substrate; a conductive layer formed over the core region dielectric layer and the periphery region dielectric layer; and a hard mask assembly formed over the conductive layer for patterning the conductive layer to have a first pattern in the core region that has conductive layer structures separated by a space and a second pattern in the periphery region that has at least one conductive layer structure, wherein the hard mask assembly includes: a first hard mask layer patterned to define an opening corresponding to the space between conductive layer structures in the core region and the first hard mask layer disposed over the periphery region; and a second hard mask layer conforming to the pattern of the first hard mask layer in the core region to laterally reduce the size of the opening corresponding to the space and patterned in the periphery region with the first hard mask layer to form a stack having a first hard mask structure and a second hard mask structure to mask the conductive layer structure of the periphery region.