Patent ID: 7852120

Claim:
A bi-directional buffer, comprising: a pair of p-channel input transistors (Q 1 and Q 2 ) connected as a differential input pair, wherein a control terminal (gate or base) of a first one of the p-channel input transistors (Q 1 ) provides a first input/output node (node A) of the bi-direction buffer, and a control terminal (gate or base) of a second one of the p-channel input transistors (Q 2 ) provides a second input/output node (node B) of the bi-direction buffer; and a pair of n-channel output stage transistors (Q 3 and Q 4 ); wherein a current path terminal (drain or collector) of the first one of the n-channel output stage transistors (Q 3 ) is connected to the first input/output node (node A); and wherein a current path terminal (drain or collector) of the second one of the n-channel output stage transistors (Q 4 ) is connected to the second input/output node (node B); wherein when the first input/output node (node A) is pulled toward a low voltage rail, a control terminal (gate or base) of a first one of the n-channel output stage transistors (Q 3 ) is also pulled toward the low voltage rail and is turned off, resulting in the second input/output node (node B) following the first input/output node (node A); and wherein when the second input/output node (node B) is pulled toward the low voltage rail, a control terminal (gate or base) of a second one of the n-channel output stage transistors (Q 4 ) is also pulled toward the low voltage rail and is turned off, resulting in the first input/output node (node A) following the second input/output node (node B).