Patent ID: 7984357

Claim:
A method for implementing minimized latency and maximized reliability when data traverses multiple buses using a memory controller in a computer system comprising the steps of: providing a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high speed bus (HSB) ECC checking and correcting circuit in the memory controller; selectively operating the memory controller in a first mode for implementing minimized latency, said first mode including applying read data directly to the DRAM ECC checking and correcting circuit, bypassing the HSB ECC checking and correcting circuit; selectively operating the memory controller in a second mode for implementing maximized reliability, said second mode including applying read data through said HSB ECC checking and correcting circuit to the DRAM ECC checking and correcting circuit; and enabling recovery of an uncorrectable error when operating in the first mode by dynamically switching to the second mode.