Patent ID: 7688149

Claim:
A phase locked loop (PLL) circuit, comprising: a phase detector for determining a period to which an input signal belongs using a real value and an imaginary value of the input signal, and for selectively outputting one of three values of the input signal as an error signal corresponding to the input signal using the determined period, wherein the three values are an imaginary value of the input signal, a difference resulting from subtracting a real value of the input signal from the imaginary value, and a sum of the real value and the imaginary value; a loop filter for loop-filtering the error signal; and an oscillator for oscillating a predetermined frequency signal according to the loop-filtered error signal and providing the oscillated signal as the feedback signal to the phase detector, wherein the phase detector is configured to: determine that the input signal belongs to a first period if the real value of the input signal is equal to or greater than a predetermined threshold, and outputting the imaginary value as the error signal; determine that the input signal belongs to a second period if the real value of the input signal is less than the threshold and the imaginary value of the input signal is equal to or greater than 0, and outputting the difference as the error signal; and determine that the input signal belongs to a third period if the real value of the input signal is less than the threshold and the imaginary value of the input signal is less than 0, and outputting the sum as the error signal.