Patent ID: 7772631

Claim:
An integrated circuit having a memory cell arrangement with a folded bit line arrangement, comprising: a plurality of active regions along a first direction in a semiconductor body; the active regions being surrounded by isolation trenches on all sides; a plurality of parallel buried word lines along a second direction in the semiconductor body; the buried word lines running through the active regions and having an upper portion below a surface of the semiconductor body, where two of the buried word lines are spaced apart from one another and from the isolation trenches running through a respective active region, and the buried word lines being insulated from a channel region in the respective active region by a gate dielectric layer; a source region between the two buried word lines; a first drain region between one of the two buried word lines and an isolation trench portion; a second drain region between the other of the two buried word lines and another isolation trench portion; a plurality of parallel bit lines along a third direction at the surface of the semiconductor body; the bit lines running perpendicular to the second direction; wherein a bit line makes contact with the source region; a plurality of storage capacitors; a first and second storage capacitor of the plurality of storage capacitors being connected to the first and second drain regions, respectively; wherein the first direction is diagonal to the second and third directions.