Patent ID: 7031207

Claim:
A semiconductor memory device comprising: an array of memory cells that is provided for memorizing data; an address circuit responsive to an address signal inputted from an external source for addressing a memory cell in the array; a write circuit responsive to a write signal inputted from an external source for writing the data into the addressed memory cell; and a control circuit that is provided for delaying an input timing of the write signal to the write circuit by a given delay amount so as to adjust a timing of writing the data after addressing the memory cell, wherein the control circuit comprises a first register capable of registering control data from an external source for setting the delay amount, a delay circuit for delaying the write signal by the set delay amount and outputting the delayed write signal to the write circuit, a second register capable of registering control data from an external source for determining an assertion duration of the write signal, and an assertion setting circuit for setting the assertion duration of the write signal according to the registered control data so that the write circuit is activated for writing the data during the set assertion duration.