Patent ID: 7594095

Claim:
A processor comprising: a processing core configured to concurrently execute a plurality of threads arranged in a plurality of single-instruction, multiple-data (SIMD) groups, wherein the processing core is configured to execute a first SIMD group comprising a vertex data group of threads executing a vertex shader program and a second SIMD group comprising a pixel data group of threads executing a pixel shader program, each SIMD group including up to a maximum number (P) of threads, where P is at least two, wherein each of the threads in a same one of the SIMD groups executes a same program on different input data, the same program comprising a sequence of instructions; wherein the processing core includes issue logic configured to select one of the SIMD groups and to issue one of the instructions of the same program in parallel for execution in parallel by all of the threads of the selected one of the SIMD groups; and core interface logic coupled to the processing core and configured to initiate execution by the processing core of one or more SIMD groups, the core interface logic including: a first load module configured to receive vertex shader program input data for the threads of the first SIMD group and to load the vertex shader program input data into the processing core; and a second load module configured to receive pixel shader program input data for the threads of the second SIMD group and to load the pixel shader program input data into the processing core; a first launch module coupled to the first load module and configured to: determine whether a launch condition for the first SIMD group is satisfied, wherein the launch condition for the first SIMD group is satisfied upon a determination that vertex shader program input data for P threads has been received by the first load module; and signal the processing core to begin executing the first SIMD group based on the determination.