Patent ID: 7160805

Claim:
A method for forming an electrical interconnection structure for connection to large electrical contacts, the method comprising: providing a semiconductor substrate having a copper-containing pad layer formed thereon such that the copper-containing pad layer includes a plurality of elongate slots having a long axis, a short axis, and sidewalls, the slots extending through the pad layer to expose the underlying semiconductor substrate; forming, over the pad layer, a dielectric layer having a plurality of elongate openings formed therein, the elongate openings having a long axis, a short axis, and sidewalls and are configured to extend into the dielectric layer to a depth sufficient to expose the sidewalls of the slots in the copper-containing pad layer all the way down to the underlying semiconductor substrate, thereby enabling electrical connections to the underlying copper-containing pad layer; and forming elongate copper-containing contacts in the plurality of elongate openings, said contacts physically contacting the exposed portions of the sidewalls thereby establishing electrical connections to the underlying copper-containing pad layer.