Patent ID: RE41842

Claim:
A method of forming an electrical interconnect, comprising the steps of: forming a first electrically conductive layer on a semiconductor substrate; forming a first electrically insulating layer on the first electrically conductive layer; patterning the first electrically insulating layer to define a contact hole therein which exposes a portion of the first electrically conductive layer; forming a barrier metal layer extending on the first electrically insulating layer and on the exposed portion of the first electrically conductive layer; forming a second electrically conductive layer extending on the barrier metal layer and into the contact hole; polishing the second electrically conductive layer using a first slurry that can polish the second electrically conductive layer and the first electrically insulating layer at a first rate and a second rate less than the first rate, respectively; and polishing the first electrically insulating layer and the second electrically conductive layer within the contact hole using a second slurry that can polish the second electrically conductive layer and the first electrically insulating layer at a third rate and a fourth rate greater than the third rate, respectively.