Patent ID: 7076600

Claim:
A memory system comprising: a dynamic random access memory having an automatic refresh cycle; a memory data bus defining a first group of signal paths for signals including column address strobe, row address strobe and write enables signals and a second group of signal paths for signals including data signals; a memory bus interface controller configured to provide signals on said first group and said second group of signal paths to said dynamic random access memory wherein during said automatic refresh cycle access to said dynamic random access memory for signals on said first group of signal paths is allowed and access to said dynamic random access memory group for signals on said second signal paths from said memory controller is prevented; and wherein said memory bus interface controller is responsive to the commencement of said automatic refresh cycle to provide during said refresh cycle an external select signal; and an external device coupled to said memory bus interface controller for enabling, by assertion of said external select signal, access via said second group of signal paths and thereby to receive said data signals and for disabling by de-assertion of said external select signal during data access to said dynamic random access memory.