Patent ID: 7373571

Claim:
An integrated circuit comprising: a interface logic circuit; a plurality of functional block circuits connected to the interface logic circuit; a plurality of delay circuits each connected to a functional block circuits, each delay circuit including a plurality of delay elements connected in series, each of the plurality of delay elements providing a corresponding delay, a first delay element receiving an input signal from an output of a corresponding functional block circuit; and a plurality of multiplexers connected in series, each of the plurality of multiplexers receiving a signal from a previous multiplexer and a signal from a corresponding delay element, and outputting a signal according to a signal from a programmable register; and the programmable register operable to receive a digital pattern according to which the multiplexers are to be activated, thereby controlling the amount of delay of an output signal of each of the plurality of the functional blocks and thereby synchronizing the output signals of the plurality of functional blocks; and a scan combiner circuit connected to the delay circuits to receive the synchronized output signals.