Patent ID: 8015356

Claim:
A cache comprising: a tag memory configured to store tags of cache blocks stored in the cache, wherein the tag memory is coupled to receive an index corresponding to an input address and is configured to output at least one tag responsive to the index; and a comparator coupled to receive the tag from the tag memory and a tag portion of the input address, wherein the comparator is configured to compare the tag to the tag portion of the input address to generate a hit/miss indication, and wherein the comparator comprises dynamic circuitry, and wherein the comparator is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion of the input address matches the tag from the tag memory, and wherein the comparator comprises first circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result, and wherein the dynamic circuitry is coupled to receive a second control signal which, when asserted, is defined to force a second result on the hit/miss indication, wherein the second result is opposite of the first result, and wherein the dynamic circuitry is configured to change state responsive to assertion of the second control signal.