Patent ID: 8198723

Claim:
An integrated circuit chip carrier comprising: first and second groups of carrier vias extending substantially from a first side of said carrier towards a second side of said carrier, said first and second groups of carrier vias arranged in an anti-parallel tessellation at a first pitch; first and second groups of electrically conductive structures on said second side arranged in an anti-parallel tessellation at a second pitch, said first group of carrier vias electrically coupled to said first group of electrically conductive structures, said second group of carrier vias electrically coupled to said second group of electrically conductive structures; and a loop circuit having an associated loop inductance, the loop circuit defined from said first group of electrically conductive structures through said first group of carrier vias to said first side and back through said second group of carrier vias to said second group of electrically conductive structures, wherein said first and second groups of carrier vias include a substantial majority of all carrier vias for conveying respective power supply voltages and wherein the anti-parallel tessellations include respective arrangements of multiple, parallely-oriented conductors of the loop circuit wherein current flow through a first group of the conductors is in an opposing direction to the current flow through a second group of the conductors and wherein the arrangement provides for a reduction in the inductance of the loop circuit due to the mutual coupling among the conductors of the two groups and due to the multiple parallel conductors of each group.