Patent ID: 8884375

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate which includes an element region and a dummy region; an n-channel MOS transistor and a p-channel MOS transistor formed in the element region; a tensile stress film formed on the semiconductor substrate and the n-channel MOS transistor; and a compressive stress film formed on the semiconductor substrate and the p-channel MOS transistor, wherein the dummy region is covered by a combination of the tensile stress film and the compressive stress film, wherein the tensile stress film includes a first dummy pattern in the dummy region, wherein the compressive stress film includes a second dummy pattern in the dummy region, wherein one of the first dummy pattern and the second dummy pattern is surrounded by the other of the first dummy pattern and the second dummy pattern and isolated in the dummy region, and wherein in the dummy region, a ratio between a total area of the tensile stress film and a total area of the compressive stress film over a surface of the semiconductor substrate is in a range of 3/7 to 7/3.