Patent ID: 8463836

Claim:
An integrated circuit (“IC”) comprising: a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle, wherein the IC implements a design that is designed for a design clock having an associated design cycle, wherein each reconfiguration cycle has a smaller duration than the design cycle, wherein at least one operand of the mathematical operation has n bits, wherein to perform the mathematical operation, the set of reconfigurable circuits (i) receives a first configuration data set during a first reconfiguration cycle to configure said set of reconfiguration circuits to perform a first sub-operation on m of n bits and (ii) receives a second configuration data set during a second reconfiguration cycle to configure said set of reconfiguration circuits to perform a second sub-operation on p of n bits, wherein the first reconfiguration cycle and the second reconfiguration cycle are consecutive reconfiguration cycles; and at least one storage element for storing at least a portion of a result produced by the first sub-operation during the first reconfiguration cycle for use in the second sub-operation during the second reconfiguration cycle.