Patent ID: 7010632

Claim:
A hardware unit ( 2 ) for operating memory components, which hardware unit ( 2 ) comprises a memory controller, a plurality of interface pins ( 3 – 6 ) and a bus connected to said memory controller and to said interface pins ( 3 – 6 ), said memory controller determines the number of memory components ( 21 , 31 , 41 , 42 , 51 , 52 , 61 , 62 ) external to said hardware unit ( 2 ) and connected to said interface pins ( 3 – 6 ), wherein in case at least one memory component ( 21 , 31 , 41 , 42 , 51 , 52 , 61 , 62 ) is determined to be connected to said interface pins ( 3 – 6 ), said memory controller divides the capacity of said bus into as many portions as there are connected memory components ( 21 , 31 , 41 , 42 , 51 , 52 , 61 , 62 ), allocates each portion to another group of said interface pins ( 3 – 6 ) to which a separate memory component ( 21 , 31 , 41 , 42 , 51 , 52 , 61 , 62 ) is connected, and exchanges signals via said bus and said interface pins ( 3 – 6 ) separately with each connected memory component ( 21 , 31 , 41 , 42 , 51 , 52 , 61 , 62 ).