Patent ID: 8081533

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells for storing data; a refresh request circuit that internally generates a refresh request, the refresh request requesting a refresh operation of the memory cells; a command decoder that receives and decodes an external access request and the refresh request and supplies to the memory cell, the external access request requesting an access to the memory cells from outside; a refresh synchronous circuit that is provided between the refresh request circuit and the command decoder and deactivates the refresh request if the external access request is output from the command decoder; a clock phase adjusting unit that generates a delay to a clock, the delay being same or longer than time taken since the external access request is received until the external access request passes through the command decoder and the refresh request synchronized with the external access request by the refresh synchronous circuit is supplied to the memory cells, and the delay being shorter than one clock cycle; and a flip-flop that is provided between the command decoder and the memory cell array, retrieves the external access request from the command decoder at a clock timing from the clock phase adjusting unit, and supplies to the memory cell array.