Patent ID: 8442076

Claim:
A timing control system for a Time Division Synchronous Code Division Multiple Access (TD-SCDMA) and Long Term Evolution Time Division Duplex (LTE-TDD) mobile terminal, the timing control system comprising: a radio frequency integrated circuit (RFIC) in communication with an antenna; an asynchronous digital interface in communication with the RFIC; a baseband integrated circuit (BBIC) adapted to perform calculations and issue commands to the RFIC via the asynchronous digital interface; a first-in first-out (FIFO) buffer in communication with the RFIC and the BBIC for buffering transmit (TX) frame data and receive (RX) frame data; a memory for storing a plurality of timing adjust values, wherein each of the plurality of timing adjust values is associated with the beginning of a corresponding one of a plurality of frame time slots; a modulo counter having a maximum count value per counter period, the modulo counter in communication with the RFIC and the BBIC for counting an integer number of timing chips, wherein the modulo counter is initiated by an RX time accurate strobe (TAS) signal that commands an initial counter value to be recorded in the memory when an external message arrives in the FIFO buffer from the antenna after a propagation delay through the RFIC, and wherein the BBIC calculates an integer number of counter periods and a fraction of a counter period corresponding to a timing correction value received from a base station, and wherein the BBIC issues a TX TAS signal during a counter period that occurs at the integer number of counter periods, and wherein an expiration of the fraction of an ensuing counter period commands an internal message for a first one of the plurality of frame time slots to be sent from the FIFO buffer to the antenna via the RFIC.