Patent ID: 7387924

Claim:
A method for forming a junction for a MOSFET device in a Si based material, comprising: removing a volume of said Si based material at the site of said junction; filling said volume with a SiGe polycrystalline material, wherein said filling further comprises: depositing by chemical vapor deposition (CVD) alternating polycrystalline layers of Ge and Si, wherein each of said polycrystalline Ge layers is having crystals with a diameter in the range from about 1.5 nm to about 15 nm, wherein each of said polycrystalline Ge layers is deposited to a thickness of between about 2 nm to about 15 nm, and wherein each of said polycrystalline Si layers is having crystals with a diameter in the range from about 1.5 nm to about 15 nm, wherein each of said polycrystalline Si layers is deposited to a thickness of between about 2 nm to about 15 nm; in situ doping with boron (B) said polycrystalline layers of Ge and Si during said deposition; diffusing dopants from said SiGe polycrystalline material into said Si based material; and depositing a porous oxide layer on at least one of said polycrystalline Ge layers.