Patent ID: 7830738

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of global bit lines intersecting with said plurality of word lines; a plurality of local bit lines partitioned into N (N is an integer greater than or equal to two) sections along said global bit lines and aligned with a same pitch as said plurality of global bit lines; N memory cell arrays each including a plurality of memory cells each having cylindrical capacitor structure formed at intersections of said plurality of word lines and said plurality of local bit lines and being arranged corresponding to the sections of said local bit lines; a plurality of local sense amplifiers for amplifying a signal read out from a selected memory cell to said local bit line and for outputting the signal to said global bit line; and a plurality of global sense amplifiers for coupling the signal transmitted from said local sense amplifier corresponding to the selected memory cell through said global bit line to an external data line.