Patent ID: 8825978

Claim:
A memory apparatus, operating in a first read operation period, including a first command sub-period, a first dummy sub-period, and a first data transmission sub-period, the memory apparatus comprising: a host device, storing first verification data, and providing a first command indicating the first verification data; and a slave device, comprising: a memory unit; a control unit, receiving the first command in the first command sub-period, driving the memory unit to provide first storage data in the first data transmission sub-period, and further providing a first control signal in the first dummy sub-period, the first control signal indicating the first verification data; a logic unit, providing first preamble data, indicating substantially a same data value as the first verification data, in the first dummy sub-period in response to the first control signal; and an output unit, receiving the first preamble data and the first storage data, and further outputting the first preamble data and the first storage data according to an internal clock signal, wherein the host device samples the first preamble data according to an external clock signal, and determines whether the external clock signal is substantially aligned with data valid-intervals determined by the internal clock signal by comparing the first preamble data and the first verification data.