Patent ID: 8305119

Claim:
A clock generation circuit comprising: a first divider that outputs a reference clock everytime the number R (R is an integer) of input clocks are counted; a loop unit that includes a second divider which outputs a feedback clock everytime the number F (F is an integer) of output clocks are counted, and generates an output clock, which is in phase synchronization with the reference clock and has a frequency that is F times the reference clock, by controlling a frequency of the output clock based on a phase error between the reference clock and the feedback clock; a clock switching unit that selects one input clock which is designated by a clock selection command among a plurality of input clocks and supplies the selected input clock to the first divider; and a timing control unit that switches the clock selection command for the clock switching unit in accordance with switching of clock selection information which designates the input clock, switches at least one of a setting of the number R of the input clocks for outputting one reference clock to the first divider and a setting of the number F of the output clocks for outputting one feedback clock to the second divider, and starts both of a count operation by using the first divider of the input clock corresponding to the set number R after switching of the setting and a count operation by using the second divider of the output clock corresponding to the set number F after switching of the setting.