Patent ID: 7565582

Claim:
A semiconductor integrated circuit comprising: a first logic circuit for outputting an output signal in accordance with an operation pattern input signal; a first delay addition circuit for delaying the output of the first logic circuit by an amount of delay in accordance with a first delay addition signal and outputting the delayed output; an input/output terminal for outputting the output of the first delay addition circuit; a reference input/output terminal for outputting the output of the first logic circuit; a second delay addition circuit for delaying an inputted signal by an amount of delay in accordance with a second delay addition signal and outputting the delayed signal; and a second logic circuit for outputting an operation pattern output signal in accordance with two input signals, wherein the second delay addition circuit receives the output of the first logic circuit which has been looped back from the reference input/output terminal and the second logic circuit receives the output of the first delay addition circuit which has been looped back from the input/output terminal and receives the output of the second delay addition circuit.