Patent ID: 8103930

Claim:
Apparatus for implementing processor bus speculative data completion in a computer system comprising: a memory controller memory management unit (MMU) for implementing processor bus speculative data completion; said memory controller MMU including a multiplexer, an error correcting code (ECC) checking and correcting circuit, and a control logic function; said multiplexer having a first input for receiving uncorrected data from a memory and having a second input for receiving corrected data from said ECC checking and correcting circuit; said multiplexer having an output coupled to a processor bus; said ECC checking and correcting circuit applying a detected error signal to the control logic function responsive to a Single Bit Error (SBE) being detected; and said control logic function coupled to said multiplexer for applying a select signal to said multiplexer responsive to said detected error signal for selecting a multiplexer output of said second input.