Patent ID: 8151031

Claim:
Programmable digital logic circuitry, comprising: a plurality of processor clusters, each processor cluster comprising: a plurality of sub-clusters, each sub-cluster comprising an execution unit for executing an instruction; at least one local memory associated with and coupled to a single sub-cluster; and switch circuitry, coupled to each of the plurality of sub-clusters in the processor cluster; a memory resource, coupled to the switch circuitry of each of the plurality of processor clusters; and a vector memory, coupled to at least one input register, at least one output registers and to a control circuitry; comprising: a plurality of addressable memory locations arranged into a plurality of banks; input permutation circuitry, for routing each of a plurality of data elements at positions within the input register corresponding to the plurality of banks, to a different one of the plurality of banks in the vector memory, according to a permutation pattern; and output permutation circuitry, for routing the contents of an addressed location in each of the plurality of banks to a position within the output register corresponding to a different one of the plurality of banks, according to a permutation pattern.