Patent ID: 7468537

Claim:
A drain extended PMOS transistor, comprising: a gate having first and second lateral sides, the gate overlying an n-type channel region in a semiconductor body; a p-type source formed in the semiconductor body and having first and second laterally opposite sides, a first lateral side of the source being located along a first lateral side of the channel region, the source being proximate the first lateral side of the gate; a p-type drift region extending laterally in the semiconductor body under a portion of the gate and only from a second opposite lateral side of the channel region to beyond the second lateral side of the gate; a p-type drain formed in the drift region, the drain being spaced from the second lateral side of the gate; an n-type backgate formed in the semiconductor body, the backgate being spaced from or adjacent to the second lateral side of the source; an n-buried layer formed in the semiconductor body beneath at least a portion of the gate and the drain; and a p-type separation region extending in the semiconductor body between the n-buried layer and the backgate and terminating below the p-drift region within the n-buried layer, the p-type separation region effectively increasing a spacing between a bottom of the drain and the n-buried layer and thus increasing transistor breakdown voltage ratings without increasing a thickness of the semiconductor body, and wherein the n-buried layer and the backgate are electrically separated from one another by the p-type separation region.