Patent ID: 8144149

Claim:
A graphics processing apparatus comprising: a plurality of execution units; logic configured to measure an output drain rate from the pixel shader; and logic configured to assign individual ones of the execution units to perform processing tasks requested by one of a vertex shader, a geometry shader, or a pixel shader, wherein once a given execution unit is assigned to one of the vertex shader, the geometry shader, or the pixel shader, it remains assigned to that shader until reassigned, the logic being further configured to reassign individual ones of the execution units based on a relative workload of the execution units collectively performing vertex shading tasks, execution units collectively performing geometry shading tasks, and execution units collectively performing pixel shading tasks, wherein the logic configured to assign is more specifically configured to assign execution units to a bottlenecked shader unit from less busy shader units in an iterative fashion until a peak or maximal drain rate is established, wherein assigning in the iterative fashion comprises comparing the performance of the reassigned individual ones of the execution units with a plurality of recorded performance based on the peak or drain rate; and logic configured to store the plurality of recorded performance.