Patent ID: 7723725

Claim:
A semiconductor device comprising: a substrate; an insulating layer on the substrate; a transistor on the insulating layer, the transistor comprising a single crystalline semiconductor layer including a source region, a drain region and a channel region between the source region and the drain region, a gate insulating film formed over the channel region and a gate electrode formed over the gate insulating film; a leveling film over the transistor; a source wiring and a drain wiring over the leveling film, the source wiring being electrically connected with the source region and the drain wiring being electrically connected with the drain region; a storage capacitance over the source wiring and the drain wiring, the storage capacitance comprising a first electrode, an insulating film and a second electrode; an interlayer insulating film over the storage capacitance; a third electrode containing a metal over the interlayer insulating film; an EL layer over the third electrode; and a fourth electrode which is a transparent conductive film over the EL layer, and wherein one of the source wiring and the drain wiring is electrically connected to the third electrode, and wherein the other of the source wiring and the drain wiring is electrically connected to the storage capacitance.