Patent ID: 8207053

Claim:
A method for creating a layout of an integrated circuit, comprising: operating a computer to define at least six linear conductive structure shapes in a gate electrode level region layout, the at least six linear conductive structure shapes each formed to extend lengthwise in a first direction, the at least six linear conductive structure shapes including a first linear conductive structure shape including a first gate portion that forms a gate electrode of a first transistor of a first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, a second linear conductive structure shape including a gate portion that forms a gate electrode of a second transistor of the first transistor type, a third linear conductive structure shape including a gate portion that forms a gate electrode of a second transistor of the second transistor type, a fourth linear conductive structure shape including a gate portion that forms a gate electrode of a third transistor of the first transistor type, a fifth linear conductive structure shape including a gate portion that forms a gate electrode of a third transistor of the second transistor type, and a sixth linear conductive structure shape including a first gate portion that forms a gate electrode of a fourth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fourth transistor of the second transistor type, wherein at least two of the second, third, fourth, and fifth linear conductive structure shapes have different lengths as measured in the first direction.