Patent ID: 6856544

Claim:
A semiconductor memory device comprising: a memory cell having a gate, a source and a drain; at least one select gate transistor provided between a source line and the source of the memory cell; a circuit configured to rewrite data in the memory cell by applying a higher potential to the gate than a potential of the source or the drain, a first potential difference between the gate and the source or between the gate and the drain being larger than a power supply voltage, the circuit operating a first data programming mode and a second data programming mode; a first command or a first command combination which is used for the first data programming mode; and a second command or a second command combination which is used for the second data programming mode; wherein the first command or the first command combination is different from the second command or the second command combination, and the source line is set to different potentials between the first data programming mode and the second data programming mode, in a period when data is rewritten.