Patent ID: 7239669

Claim:
An integrated circuit, comprising: a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates; a plurality of clock domain converters, each clock domain converter being coupled to a corresponding one of the synchronous modules, and being operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol, each clock domain converter comprising a datapath operable to transfer a data token between the corresponding clock domain and the asynchronous domain, each clock domain converter further comprising control circuitry operable to enable transfer of the data token via the datapath in response to at least one transition of a clock signal associated with the corresponding clock domain and at least one completion of the asynchronous handshake protocol; and an asynchronous crossbar coupled to the plurality of clock domain converters, and operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.