Patent ID: 8174868

Claim:
An embedded static random access memory (SRAM) chip in a 32 nm or smaller technology generation, comprising: a first SRAM array of first SRAM unit cells, each first SRAM unit cell comprising at least six transistors forming a data latch for data storage and at least two pass gates for data reading and writing access, each unit cell occupying a cell area defined by a first X-pitch and a first Y-pitch, the first X-pitch being longer than the first Y-pitch; and a plurality of logic transistors formed outside of the first SRAM array, the plurality of logic transistors including at least a first logic transistor having a first gate pitch and a second logic transistor having a second gate pitch, wherein the gate pitches are defined between source and drain contacts of the first and second logic transistors, respectively, wherein the second gate pitch is the minimum logic gate pitch for the plurality of logic transistors, wherein the first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one.