Patent ID: 8013637

Claim:
A clock signal selection circuit comprising: a first AND circuit outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; a first gated clock buffer inputting either the input signal to the first flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the first clock signal to output a third clock signal; a second flip-flop inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal; a second gated clock buffer inputting either the input signal to the second flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the second clock signal to output a fourth clock signal; a first OR circuit outputting a logical sum signal of the third and fourth clock signals; a third flip-flop inputting the logical product signal that the first AND signal outputs and outputting an output signal in synchronization with the first clock signal; and a fourth flip-flop inputting the logical product signal that the second AND signal outputs and outputting an output signal in synchronization with the second clock signal, and wherein the first flip-flop inputs either the output signal that the third flip-flop outputs or a signal in accordance with the output signal and the second flip-flop inputs either the output signal that the fourth flip-flop outputs or a signal in accordance with the output signal.