Patent ID: 7101764

Claim:
A process for fabricating a high-voltage transistor comprising the steps of: providing a substrate having a principal surface and having a first region and a second region therein, wherein an isolation region resides within the first region; forming a gate dielectric layer overlying the principal surface; forming a gate electrode overlying a portion of the first region, a portion of the second region and a portion of the isolation region; implanting ions at an angle of incidence of more than 30° to about 55° with respect to the normal into the substrate to form a channel region in the second region and beneath the gate electrode using the gate electrode as an implant mask, wherein the ions are implanted at an angle of incidence offset from a normal of the principal surface, and wherein the ions are implanted with an implantation dose of about 1.0×10 13 to about 2.0×10 13 ions/cm 2 ; and doping the substrate to form a source region and a drain contact region in the substrate, wherein the source region resides in the second region and the drain contact region resides in the first region, and wherein the drain contact region is separated from the channel region by the isolation region and a portion of the first region.