Patent ID: 7368939

Claim:
A semiconductor memory device comprising: a memory core unit which includes a plurality of memory cells selected by an address signal; a clock synchronous circuit which receives an external clock signal and generates a plurality of internal clock signals; a control circuit which receives an external control signal in synchronism with the internal clock signal generated by the clock synchronous circuit and generates the address signal and internal control signals; a data multiplexer which includes a plurality of input parallel data lines and a plurality of output parallel data lines and is switched to one of a first output state and a second output state in accordance with the internal control signal output from the control circuit, the data multiplexer outputting parallel data, which is input to said plurality of input parallel data lines and read out from the memory core unit, to said plurality of output parallel data lines corresponding to said plurality of input parallel data lines in the first output state and selecting 1 bit data of the parallel data input to said plurality of input parallel data lines and outputting the 1 bit data to said plurality of output parallel data lines in the second output state; a conversion circuit which converts the parallel data output from the data multiplexer into serial data; and an output drive circuit which outputs the serial data converted by the conversion circuit to an external data signal line wherein the internal control signal includes a first internal control signal and a second internal control signal, and the data multiplexer comprises: a first transistor circuit which receives even numbered data of the parallel data read out from the memory core unit, outputs the even numbered data when the first internal control signal has a first voltage, and disconnects the even numbered data when the first internal control signal has a second voltage; a second transistor circuit which receives the even numbered data, outputs the even numbered data when the second internal control signal has the second voltage, and disconnects the even numbered data when the second internal control signal has the first voltage; a third transistor circuit which receives odd numbered data of the parallel data read out from the memory core unit, outputs the odd numbered data when the first internal control signal has the second voltage, and disconnects the odd numbered data when the first internal control signal has the first voltage; and a fourth transistor circuit which receives the odd numbered data, outputs the odd numbered data when the second internal control signal has the first voltage, and disconnects the odd numbered data when the second internal control signal has the second voltage.