Patent ID: 8130017

Claim:
A delay locked loop, comprising: a control voltage generator configured to generate an analog voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the analog voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal and including a delay unit, wherein the delay unit is configured to delay a first input signal to generate a variable time window that varies as process, voltage, and temperature (PVT) characteristics vary and the skew information signal generator is further configured to count a reference clock during the variable time window in generating the skew information signal.