Patent ID: 8754530

Claim:
A transistor comprising: a silicon region; a gate stack on the silicon region, the gate stack including a gate oxide layer on the silicon region and a gate electrode on the gate oxide layer, and an off-set spacer surrounding the gate stack; a first patterned sacrificial layer adjacent to a first side of the off-set spacer; a second patterned sacrificial layer adjacent to a second side of the off-set spacer, wherein each of the first and second patterned sacrificial layers substantially contacts a first and second silicided region, respectively, within the silicon region, wherein each of the first and second patterned sacrificial layers extends to the first and second silicided region, respectively, and wherein each of the first and second patterned sacrificial layers is free of contact with at least a top surface of a portion of off-set spacer in contact with the gate stack; and a first contact area and a second contact area defined by the first and second patterned sacrificial layers, respectively, where the each of the first and second contact areas comprises a height dimension defined by a thickness of the first and second patterned sacrificial layers, respectively, and wherein the first and second contact areas are above and extend to the first and second silicided region, respectively.