Patent ID: 7321165

Claim:
A semiconductor device comprising: stacked layers of the substrates each formed with insulating material and having a plurality of leads and a plurality of connection terminals, said connection terminals being disposed at the peripheral edges of the substrates; semiconductor chips mounted on said substrates, respectively; and connection means electrically interconnecting said substrates via the corresponding connection terminals, wherein one ends of said plurality of leads are connected to corresponding electrodes formed on said semiconductor chips and the other ends of said plurality of leads extend to the corresponding connection terminals, respectively on each of said substrates; wherein said plurality of leads includes a first group in which the other ends of the leads are permanently connected to the corresponding connection terminals, respectively, and a second group in which the other ends of the leads are branched to plural lines in the vicinity of the corresponding connection terminals, respectively; wherein on one of said substrates one of the branched lines is connected to the corresponding connection terminal at least at one of the branches, and another of the branched lines is finally trimmed and not connected to the corresponding connection terminal at least at said one of the branches on the same said substrate, wherein on another of said substrates one of the branched lines corresponding to said one of the branched lines on said one of the substrates is finally trimmed and not connected to the corresponding connection terminal at least at one of the branches, and another of the branched lines is permanently connected to the corresponding connection terminal at said branch, and wherein said connection means includes: first leads commonly connected to the connection terminals at said first group on all of the stacked layers of said plurality of substrates; second leads commonly connected to some of the connection terminals at said second group on predetermined ones of the layers of said plurality of substrates, the second leads not connected to said plurality of leads on the other layers; and third leads connected to the corresponding connection terminals at said second group, respectively, so as to serve as independent signal lines with respect to the corresponding layers of the said plurality of substrates.