Patent ID: 7906400

Claim:
A method of manufacturing a semiconductor device, comprising: forming over a semiconductor substrate a first mask pattern in which a first region for forming a first transistor as well as a second region for forming a second transistor having the same channel type as that of the first transistor are opened; performing a first ion implantation to implant, using the first mask pattern, a first dopant into the first region and the second region to form well regions; performing a second ion implantation to implant, using the first mask pattern, a second dopant into the first region and the second region to adjust a threshold voltage (Vth) of the first transistor; removing the first mask pattern and forming a second mask pattern in which the first region is covered and the second region is opened; performing a third ion implantation to implant, using the second mask pattern, a third dopant into the second region to adjust a Vth of the second transistor; forming a first gate insulating film in the first region and forming a second gate insulating film in the second region, the second gate insulating film being thinner than the first gate insulating film; and forming a first gate electrode over the first gate insulating film of the first region and forming a second gate electrode over the second gate insulating film of the second region, the second gate electrode having a gate length shorter than that of the first gate electrode; wherein in the second and third ion implantation, the second dopant and the third dopant are dopants comprising the same constituent element and are implanted at the same energy.