Patent ID: 6894343

Claim:
In an array of non-volatile memory cells formed in rows and columns on a semiconductor substrate with elongated source and drain diffusions extending between columns of cells and word lines extending across rows of cells, wherein individual cells have a first channel segment between adjacent source and drain diffusions in the substrate that is controlled by a floating gate and a second channel segment that is controlled by a select gate portion of one of the word lines, an improved structure comprising: trenches provided in the semiconductor substrate as part of the cells, said second channel segment of the individual cells being provided along a sidewall of one of the trenches and the select sate being positioned in the trench, and elongated third gates extending across the array along and capacitively coupled with floating gates, wherein the elongated third gates are erase gates that have lengths extending in a direction along rows of floating gates and which are individually positioned between adjacent rows of floating gates in a manner to have capacitive coupling with edges of the floating gates of at least one of said adjacent rows.