Patent ID: 8356185

Claim:
A processor, comprising: a hardware instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and a hardware functional unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more cryptographic instructions and one or more non-cryptographic instructions, wherein the hardware functional unit comprises: a cryptographic execution pipeline configured to execute the one or more cryptographic instructions with a corresponding cryptographic execution latency; a non-cryptographic execution pipeline configured to execute the one or more non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency; and a local bypass network circuit comprising one or more multiplexers, wherein the local bypass network circuit is coupled to an output of the cryptographic execution pipeline and one or more inputs of the cryptographic execution pipeline and is configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline without routing such bypassed results externally to the hardware functional unit, such that each instruction within a sequence of dependent cryptographic instructions is executable with an execution latency corresponding to the cryptographic execution latency, and wherein the local bypass network circuit is not electrically coupled to bypass the results of the cryptographic execution pipeline to any other functional unit within the processor.