Patent ID: 6989320

Claim:
A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising: forming a charge trapping dielectric layer over the substrate; forming a first poly layer over the charge trapping dielectric layer; forming a hardmask over the first poly layer; patterning the hardmask to form hardmask features having respective first spacings there-between, the first spacings having respective first widths; forming a layer of spacer material over the hardmask features; patterning the spacer material to form sidewall spacers adjacent to the hardmask features, respective pairs of sidewall spacers defining bitline openings; patterning the first poly layer to form second spacings therein, the second spacings having respective second widths substantially equal to respective widths of the bitline openings; patterning the charge trapping dielectric layer to form third spacings therein, the third spacings having respective third widths substantially equal to respective widths of the bitline openings; performing a bitline implant through the bitline openings and the second and third spacings to establish buried bitlines within the substrate having respective bitline widths corresponding substantially to respective widths of the bitline openings; performing a high temperature oxide deposition to fill in the third spacings with one or more oxide based materials; performing a high density plasma oxide deposition to fill in the second spacings with one or more oxide based materials; performing a chemical mechanical polishing to remove excess oxide based materials; forming a second poly layer over the charge trapping dielectric layer; and patterning the second poly layer to form wordlines that overlie the buried bitlines.