Patent ID: 8163610

Claim:
A method of forming a memory array, comprising: forming a sacrificial layer overlying a semiconductor substrate; forming a hard mask layer overlying the sacrificial layer; patterning the hard mask layer for exposing portions of the hard mask layer and underlying portions of the sacrificial layer and the substrate; forming trenches through the hard mask layer, the sacrificial layer, and into the substrate by removing the exposed portions of the hard mask layer and the underlying portions of the sacrificial layer and of the substrate; forming spacers on sidewalls of the trenches; extending the trenches further into the substrate by removing additional substrate material from the trenches after forming the spacers; forming isolation regions in the trenches by filling the trenches with a dielectric material; after forming the isolation regions, removing the spacers, the sacrificial layer, and the hard mask layer to form a plurality of fins in the substrate that protrude from the substrate so that each one of the isolation regions is located between successive fins of the plurality of fins in the substrate; isotropically etching the fins to reduce a width of the fins and to round an upper surface of the fins; forming a tunnel dielectric layer overlying the isotropically etched fins; forming a floating gate layer overlying the tunnel dielectric layer; forming an intergate dielectric layer overlying the floating gate layer; and forming a control gate layer overlying the intergate dielectric layer.