Patent ID: 7411402

Claim:
A method for reducing a parasitic DC bias voltage on a sensor, comprising the steps of: monitoring a parasitic DC bias voltage on a first element of a sensor; and modifying automatically a controlled bias voltage applied between the first element of the sensor and a second element of the sensor to substantially maintain the parasitic bias voltage of the first element at a desired potential, wherein the first element is an inter-digitated capacitor (IDC) element and the second element is a resistive temperature device (RTD) element and wherein the controlled bias voltage is modified to substantially maintain the parasitic DC bias voltage at zero potential in a closed loop, wherein the parasitic DC bias voltage on the IDC element is low-pass filtered, wherein the low-pass filtered parasitic DC bias voltage is coupled to an input of a control unit and an output of the control unit provides a control signal that causes the controlled bias voltage to be periodically modified, and wherein the control unit is configured as a proportional and integral controller.