Patent ID: 7229879

Claim:
A method for fabricating a microelectronic product comprising: providing a substrate having exposed therein a first contact region and a second contact region; forming a first dielectric layer and an etch stop layer sequentially over the substrate and a second dielectric layer over the etch stop layer said etch stop layer simultaneously serves as a floor of trench and passivates a sidewall of a capacitator forming said capacitor interposed between the first dielectric layer and the second dielectric layer, where the capacitor is also formed sandwiched between a first conductor stud that penetrates the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer; and forming a contiguous conductor interconnect and conductor stud layer contacting the second contact region and into a trench defined within the second dielectric layer and a contiguous via defined within the first dielectric layer.