Patent ID: 7476975

Claim:
A semiconductor device comprising; a wiring substrate including a wiring pattern; a semiconductor chip having a pad on a first surface thereof and mounted on the wiring substrate so that the first surface opposes the wiring substrate, the semiconductor chip having a linear expansion coefficient that is smaller than a linear expansion coefficient of the wiring substrate and an elastic modulus that is higher than an elastic modulus of the wiring substrate; a first resin layer covering a first part of the wiring pattern overlapping the semiconductor chip, the first resin layer including an opening disposed on a second part of the wiring pattern, the second part of the wiring pattern overlapping the pad; a second resin layer disposed between the semiconductor chip and the first resin layer, the second resin layer having a linear expansion coefficient that is smaller than a linear expansion coefficient of the first resin layer and an elastic modulus that is higher than an elastic modulus of the first resin layer; and a conductive member disposed in the opening and connecting the pad and the second part of the wiring pattern; wherein a part of the second resin layer is disposed within the opening of the first resin layer and between the first resin layer and the conductive member.