Patent ID: 8049549

Claim:
A circuit comprising: a delta phi generator having a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state, wherein the delta phi generate comprises a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode and a second current electrode coupled together, a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to the output node of the delta phi generator, a first resistive element having a first terminal coupled to the second current electrode of the second transistor at the output node, and a second terminal coupled to a second power supply voltage terminal, a third transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode of the second transistor, and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the second power supply voltage terminal; a startup circuit coupled to the delta phi generator, the startup circuit for ensuring the delta phi generator does not operate in the undesirable operating state; and a level detector comprising a comparator with an offset, the comparator having a first input coupled to the output node, a second input coupled to a reference voltage, and an output coupled to the startup circuit, the level detector for detecting the delta phi voltage, and in response, disabling the startup circuit.