Patent ID: 7608469

Claim:
A method of fabricating a integrated circuit device, the method comprising the steps of: a) providing a first electrical part, a second electrical part, and a connector; b) forming a shell, the shell having a top surface and a cavity disposed within the top surface, the first electrical part being embedded within the shell, the connector being electrically connected to the first electrical part and having an exposed portion extending into the cavity; c) providing a tester adapted to generate a first input signal and process a first response signal associated with the first input signal; d) communicating the first input signal to the first electrical part, the first electrical part being configured to generate the first response signal upon receipt of the first input signal if the first electrical part is functional; e) transmitting the first response signal from the first electrical part to the tester; f) disposing the second electrical part in the cavity and electrically connecting the second electrical part to the connector; and g) filling the cavity with a filler material to at least partially embed the second electrical part within the filler material.