Patent ID: 7570307

Claim:
A filter device comprising: a digital filter including: unit delay elements chained together and having M stages (where M is a positive integer equal to or larger than two) for shifting an n-bit (where n is a positive integer) digital input signal supplied thereto at the respective stages; M multiplier circuits connected to the outputs of said unit delay elements at the respective stages, each for multiplying an output signal of said unit delay element at a stage associated therewith by a predetermined filter coefficient; and adder circuits chained together and having (M−1) stages and connected to the outputs of said M multiplier circuits for summing output signals of said respective multiplier circuits to supply a filtered output signal; a maximum/minimum detector circuit for receiving output signals from a plurality of said unit delay elements in different stages and for detecting a maximum value and a minimum value in the received output signals from said unit delay elements having M stages to supply a maximum value detection signal and a minimum value detection signal, said output signals received by said maximum/minimum detector circuit representing values of said input signal sampled at different times; and a limiter circuit for receiving the filtered output signal supplied from said adder circuit at the (M−1)-th stage, limiting a maximum value of the filtered output signal based on the maximum value detection signal, limiting a minimum value of the filtered output signal based on the minimum value detection signal, and supplying the limited signal.