Patent ID: 7548999

Claim:
An input/output (I/O) node comprising: an I/O memory management unit (IOMMU) configured to translate memory requests, including translating addresses of memory requests; and the I/O node is configured to couple to an interconnect that comprises a plurality of links having a same protocol, and the I/O node is configured to couple to two of the plurality of links, and one of the two links is designated an upstream link and another one of the two links is designated a downstream link, and the I/O node is configured to operate as a tunnel on the interconnect, and wherein the IOMMU is configured to translate memory requests received from the downstream link and passing through the tunnel in the upstream direction on the interconnect, and the I/O node is configured to transmit the translated memory requests on the upstream link and wherein the IOMMU comprises a control register programmable with an enable indication indicating whether or not translation of the memory requests passing through the tunnel is enabled, wherein the IOMMU is configured to translate the memory requests passing through the tunnel if the enable indication indicates enabled, and wherein the IOMMU is configured to pass the memory requests unmodified if the enable indication indicates disabled, and wherein the I/O node is configured to transmit translated memory requests on the upstream link that are received from one or more I/O devices that are coupled to the I/O node separate from the interconnect, and wherein the IOMMU is configured to translate memory requests from the one or more I/O devices even if the enable indication indicates disabled.