Patent ID: 7230451

Claim:
A programmable logic device, comprising: a plurality of programmable logic blocks disposed on the device in a two-dimensional array of intersecting rows and columns; general interconnection resources configured to convey signals amongst the plurality of programmable logic blocks; a plurality of function-specific blocks (FSBs) arranged in an additional column included within the two-dimensional array, wherein each FSB includes circuitry at least partly hardwired to perform a specific function on at least one multi-bit FSB input signal to generate at least one multi-bit FSB output signal; and an input routing channel extending along the plurality of FSBs, wherein the input routing channel contains a plurality of input processing blocks, each input processing block being associated with a respective one of the FSBs and being configured to programmably selectively accept at least one signal from the general interconnection resources and to generate at least one multi-bit FSB input signal to be conveyed to an associated FSB, each input processing block containing registering logic at least two registers deep, and selection logic, wherein the registering and selection logic is configured to programmably selectively generate multi-bit FSB input signals that are at least doubly registered.