Patent ID: 8713769

Claim:
A method for manufacturing a capacitive stack with high capacitive density, comprising: forming a planar core capacitive substrate including a first dielectric core layer, having a thickness between 0.5-4 mils, sandwiched between a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer having a thickness between 0.25 and 6 mils thick, and wherein the core capacitive substrate provides structural rigidity for coupling additional conductive and dielectric layers; coating a third conductive foil with a second dielectric layer that includes an uncured or semi-cured dielectric material loaded with a nanopowder selected to achieve a desired dielectric constant; forming a pattern of one or more clearances on the first conductive layer in the core capacitive substrate; filling the one or more clearances on the first conductive layer with a non-conductive filler paste; coupling an exposed surface of the second dielectric layer to the first conductive layer; curing the dielectric material of the second dielectric layer; and sequentially testing the integrity of the second dielectric layer, and any subsequent dielectric layer, as each of these dielectric layers is stacked and formed onto the core capacitive substrate.