Patent ID: 7512917

Claim:
A verification method for verifying a safety apparatus including a programmable logic device, the programmable logic device including a plurality of functional elements, the method comprising the steps of: verifying on actual hardware that all outputs of a logic pattern are produced normally in response to all inputs of the logic pattern of each of the plurality of functional elements in advance; generating a plurality of functional elements, each the same as a different one of the plurality of functional elements verified on the actual hardware, using a predetermined hardware description language; independently logic-synthesizing each of the generated functional elements into a plurality of first net lists; generating a connection function among the generated functional elements using the predetermined hardware description language; logic-synthesizing the generated connection function into a second net list corresponding to the connection function; synthesizing the plurality of first net lists with the second net list to generate a third net list; writing a logic circuit into the programmable logic device on the basis of the third net list; and verifying on the programmable logic device including the written logic circuit that the operation of the programmable logic device is normal.