Patent ID: 6873177

Claim:
A method of reconfiguring a complex programmable logic device (CPLD) in an electronic system, the CPLD comprising an electrically-erasable programmable read-only memory (EEPROM) array, a static random access memory (SRAM) array, a control circuit for loading data from the EEPROM array into the SRAM array and including a security circuit for protecting the data stored in the EEPROM array and the SRAM array, and a plurality of macrocells connected by a programmable interconnect matrix, the method comprising: storing a first set of configuration data in the SRAM array to configure the plurality of macrocells and the programmable interconnect matrix to place the CPLD in a first configuration, the first set of configuration data comprising a security code used by the security circuit to prevent writing to the EEPROM array except under a set of limited circumstances; and programming the EEPROM array with a second set of configuration data while operating the electronic system with the CPLD in the first configuration.