Patent ID: 7785950

Claim:
A method of providing a dual stress memory technique in a semiconductor device including an nFET and a pFET, the method comprising: forming a first stress layer over the nFET and the pFET, wherein the first stress layer is an intrinsically compressive stressed layer forming an etch stop layer over the first stress layer; removing the first stress layer and the etch stop layer over the nFET forming a second stress layer over a remaining portion of the first stress layer and the nFET, wherein the second stress layer is a tensilely stressed silicon nitride layer; annealing to memorize stress in the nFET and the pFET, wherein the remaining portion of the first stress layer remains over the pFET during the annealing, and the second stress layer remains over both the nFET and the pFET during the annealing; and; removing the first and second stress layers and the etch stop layer in their entirety, wherein the memorized stress is retained in the nFET and the pFET after the annealing and the removing of the first and second stress layers.