Patent ID: 7868808

Claim:
A leakage compensated digital to analog converter comprising: a) a reference current source input; b) a plurality of digital inputs; c) a plurality of inverted digital inputs, each inverted digital input having a digital state opposite a respective one of said digital inputs; d) a plurality of MOS output current source transistors having gates connected to said reference current source input; e) a plurality of MOS output switch transistors having gates connected to respective ones of said digital inputs, and said MOS output switch transistors connected in a paired manner, source to drain in series with said output current source transistors between a common voltage supply and an output node; f) a plurality of MOS compensation current source transistors having gates connected to said reference current source input; g) a plurality of MOS off-state switch transistors having gates connected to a disabling voltage supply; h) a plurality of MOS compensation switch transistors having gates connected to respective ones of said inverted digital inputs, and said MOS compensation switch transistors connected in a set-of-three manner, source to drain in series with said compensation current source transistors and said off-state switch transistors between the common voltage supply and a compensation output node; and i) a current mirror mirroring the current on the compensation output node into the output node.