Patent ID: 7830189

Claim:
A DLL (delay locked loop) circuit comprising: a first variable delay circuit receiving an external signal to variably adjust a delay time of the external signal with a prescribed delay time unit, the first variable delay circuit producing a first set of first and second delay signals having different delay time values in association with a first transition of the external signal, the first variable delay circuit producing a second set of first and second delay signals having different delay time values in association with a second transition of the external signal; a pair of second variable delay circuits receiving the first set of the first and second delay signals and the second set of the first and second delay signals, respectively, the pair of the second variable delay circuits producing third and fourth delay signals, respectively, each delay time of the third and fourth delay signals being variably adjusted with finer resolution than the prescribed delay time unit in the first variable delay circuit; and a first synthesis circuit synthesizing the third and fourth delay signals from the pair of the second variable delay circuits to output a synthesized signal, the pair of second variable delay circuits each including: first and second one-shot pulse generating circuits, each of the first and second one-shot pulse generating circuits generating a one-shot pulse in response to a prescribed transition of each of the first and second delay signals of an associated set; first and second latch circuits receiving outputs of the first and second one-shot pulse generating circuit, respectively, the first and second latch circuits being set in response to the one-shot pulses supplied thereto from the first and second one-shot pulse generating circuit, respectively; and a second synthesis circuit receiving outputs of the first and second latch circuits, as first and second inputs, the second synthesis circuit synthesizing the first and second inputs at a prescribed ratio to output the synthesized signal, the first and second latch circuits being reset based on the output signal of the second synthesis circuit.