Patent ID: 7504862

Claim:
A level shifter translator, comprising: at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, wherein said first and second transistor have said respective circuit branches referring to a biasing circuit with current mirror; said second transistor is coupled to said biasing circuit through a third MOS transistor; an inverter is connected to an output of said biasing circuit; and the output of said inverter drives said third transistor; and wherein said biasing circuit with current mirror comprises a fourth and a fifth MOS transistor connected to common control terminals and connected towards a circuit node which is directly connected to said second circuit branch and with a first conduction terminal connected respectively to said first and second circuit branch and to a second common conduction terminal connected towards a second potential reference; wherein said second transistor is connected with a second conduction terminal to a first conduction terminal of said third transistor in correspondence with a circuit node in said circuit branch; wherein said first and second circuit branch have a first circuit node and a second circuit node in correspondence with a second conduction terminal of said third transistor and a second conduction terminal of said first transistor and in that said circuit node of said biasing circuit is directly connected to said first circuit node; wherein said first conduction terminal of said fourth transistor is connected to said second circuit node and in that said first conduction terminal of said fifth transistor is connected to said first circuit node; wherein said second circuit node is connected to said inverter supplied through said second potential reference; a sixth MOS transistor is placed in parallel to said fourth transistor driven by said output of said inverter with a first conduction terminal connected to said second circuit node and to a second conduction terminal connected towards said second potential reference; and a seventh MOS transistor is connected in series to said sixth transistor driven by said first reference potential and to a first conduction terminal connected to said second conduction terminal of said sixth transistor and with a second conduction terminal connected to said second potential reference.