Patent ID: 6853599

Claim:
A magnetic memory device, comprising: a memory cell array block having a plurality of magnetic memory cells arranged at intersections of wordlines, digit lines, and bitlines; a reference memory cell array block having a plurality of magnetic memory cells arranged at intersections of reference wordlines, the digit lines, and a reference bitline, wherein one wordline is arranged at respective two adjacent wordlines; a first bitline clamp circuit for making a predetermined first current flow to a selected magnetic memory cell in the memory cell array block through a bitline to which the selected magnetic memory cell in the memory cell array block is connected, according to data of the selected magnetic memory cell in the memory cell array block, the first bitline clamp circuit being coupled to the bitline; second and third bitline clamp circuits for making a predetermined second current flow to selected magnetic memory cells in the reference memory cell array block through the reference bitline, the second and third bitline clamp circuits being coupled to an upper end and a lower end of the reference bitline, respectively; and a sense amplifier for sensing and amplifying a third current on a first data line connected to the bitline and a fourth current on a second data line connected to the reference bitline to judge the data of the selected magnetic memory cell in the memory cell array block.