Patent ID: 8103818

Claim:
A memory module comprising: memory that has a plurality of banks containing a plurality of memory cells arranged in a matrix array, wherein each of the memory cells that is targeted for access is identified on the basis of a bank address composed of a prescribed number of bits, a row address composed of a prescribed number of bits, and a column address composed of a prescribed number of bits, the addresses being input from a memory controller; an address generator configured to be able to generate a highest order bit of a bank address to be utilized for identification of the memory cell targeted for access, using a highest order bit of a row address that is output by the memory controller, and to be able to output the highest order bit of the bank address to the memory, in case where (i) a sum of a number of bits of the bank address, a number of bits of the row address, and a number of bits of the column address that have been output by the memory controller is equal to a sum of the number of bits of the bank address, the number of bits of the row address, and the number of bits of the column address that are utilized for identification of the memory cell targeted for access; (ii) the number of bits of the row address that is output by the memory controller exceeds by one the number of bits of the row address that is utilized for identification of the memory cell targeted for access; and (iii) the number of bits of the bank address that is output by the memory controller is less by one than the number of bits of the bank address that is utilized for identification of the memory cell targeted for access; an operating mode detector configured to detect an operating mode of access to the memory by the memory controller; and an address generating controller configured to control the address generator based on the operating mode detected by the operating mode detector.