Patent ID: 8887142

Claim:
A process for loop control flow diversion, the process utilizing a device which has at least one logical processor in operable communication with at least one memory, the logical processor having at least one register, the process comprising the steps of: obtaining in the memory an executable module which includes a loop having a loop body which is not fully interruptible code and does not consist of nops, the loop also having a loop top, the module also including an indirection cell containing a loop top address, namely, an address pointing to the loop top, the loop also including a loop jump instruction sequence which references the indirection cell; a first thread of execution executing an iteration of the loop body; continuing execution flow of the first thread through the address specified in the indirection cell to the loop top; a second thread of execution altering the contents of the indirection cell such that the indirection cell contains an address other than the loop top address; diverting execution flow of the first thread through the altered indirection cell to a point away from the loop top, said diverting step not reliant upon a repeat count register of the processor; restoring the loop top address into the indirection cell; and again continuing execution flow of the first thread through the restored indirection cell to the loop top.