Patent ID: 7930462

Claim:
An apparatus comprising: a plurality of serializer/deserializer (SERDES) circuits, wherein each SERDES circuit of the plurality of SERDES circuits is configured to provide data received from a respective lane of a plurality of lanes to which the plurality of SERDES circuits are coupled during use; and a receive pipe coupled to the plurality of SERDES circuits, wherein the receive pipe comprises: a plurality of accumulate buffers, each accumulate buffer of the plurality of accumulate buffers corresponding to a respective port of a plurality of ports that are configurable over the plurality of lanes; a plurality of multiplexing levels, wherein a first level of the multiplexing levels is coupled to receive the data provided by the plurality of SERDES circuits, and wherein the each multiplexer at the first level is coupled to receive data from two neighboring lanes on one input and the data from the two neighboring lanes connected in reverse order on the other input, and wherein each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level of the plurality of levels on one input and the outputs connected in reverse order on the other input; a plurality of accumulate buffer counters, wherein each accumulate buffer counter of the plurality of accumulate buffers corresponds to a respective accumulate buffer of the plurality of accumulate buffers; a plurality of configuration registers, wherein each configuration register of the plurality of configuration registers corresponds to a respective port of the plurality of ports and is configured to indicate an initial lane of the plurality of lanes assigned to the respective port and a size of the port; and control logic coupled to the plurality of multiplexing levels, the plurality of accumulate buffer counters, and the plurality of configuration registers, wherein the control logic is configured to generate one or more first select signals for the first level responsive to a least significant bit of the plurality of buffer counters and a least significant bit of initial lane numbers corresponding to the initial lanes indicated in the plurality of configuration registers, and wherein the control logic is configured to generate each one or more second select signals for each other level of the plurality of multiplexing levels responsive to respective more significant bits of the initial lane numbers and the plurality of buffer counters.