Patent ID: 7492636

Claim:
A method for double-side-biasing (DSB) a NAND memory device having a matrix of charge trapping memory cells in a memory array, each charge trapping memory cell having a first charge trapping site for storing a first bit and a second charge trapping site for storing a second bit, the matrix of charge trapping memory cells connecting to a plurality of word lines in row directions and a plurality of bit lines in column directions, comprising: electron-injection programming the one or more selected charge trapping memory cells in the matrix of charge trapping memory by simultaneously biasing a respective source terminal and a respective drain terminal in each of the plurality of charge trapping memory cells and applying a positive gate voltage to a select word line connecting to the plurality of charge trapping memory cells; and hole-injection erasing the one or more selected charge trapping memory cells in the matrix of charge trapping memory by simultaneously biasing a respective source terminal and a respective drain terminal in each of the plurality of charge trapping memory cells and applying a negative gate voltage to the select word line connecting to the plurality of charge trapping memory cells.