Patent ID: 7995472

Claim:
A network processor dataflow chip, comprising: a plurality of on-chip data transmission circuit structures, the on-chip data transmission circuit structures comprising a plurality of selectable frame processing circuit structures and a plurality of selectable data transmission circuit structures; and a plurality of scheduling circuit structures, the plurality of scheduling circuit structures comprising a full internal scheduling circuit structure, a calendar scheduling circuit structure in communication with an external scheduler chip and an external calendar scheduling circuit structure; wherein one of the plurality of data transmission circuit structures is configured to be selected responsive to a data transmission selection indicator; wherein one of the plurality of scheduling circuit structures is configured to be selected responsive to a scheduling function selection indicator; wherein the full internal scheduling circuit structure comprises calendar and queue control circuit structures configured to be driven by the dataflow chip, and the calendar circuit structures are each defined by a plurality of dedicated physical memory areas located in data store blocks; and wherein the full internal scheduling circuit structure comprises logic configured for internal calendar functions residing in a calendar page loader and a clock element, and the calendar circuit structures each comprise a plurality of calendar pages, each of the plurality of calendar pages comprising a plurality of calendar entries, wherein the dataflow chip is configured to read a calendar page for each clock element tick; the dataflow chip scheduler circuit structure further comprising a guaranteed bandwidth scheduling circuit structure and a best effort scheduling circuit structure a round-robin LIFO buffer having a plurality of memory blocks ranked from highest to lowest priority, first weight accumulation logic for best effort bandwidth scheduling, and second weight accumulation logic for best effort bandwidth scheduling; and wherein the data flow chip is configured to provide best effort dispatching by: applying the first weight accumulation logic and the second weight accumulation logic to a data packet; selecting a memory block and placing the data packet into the selected memory block in the LIFO buffer responsive to relative amounts of first weight and second weight characteristics, wherein packets with the higher first weight relative to the second weight and placed in higher priority memory blocks; and dropping data packets from the lowest priority memory blocks.