Patent ID: 7555417

Claim:
A computer implemented method of simulating an integrated circuit comprising a plurality of cells, the method comprising: monitoring, using a computer, input signals to the plurality of cells during simulation of the integrated circuit; designating, using the computer, at least one input to the plurality of cells as a potential clock signal; monitoring, using the computer, activity status of the plurality of cells based on inputs, outputs or internal states of the cells; assigning, using the computer, an activity classification to at least one of the plurality of cells, wherein the at least one of the plurality of cells receives the potential clock signal as an input, wherein the assigned activity classification is an inactive status in the event the at least one of the plurality of cells is inactive, and wherein the assigned activity classification is an active status in the event the at least one of the plurality of cells is active; and during simulation of the integrated circuit: bypassing, using the computer, processing of at least some simulation events from said at least one of the plurality of cells when the assigned activity classification for said at least one of the plurality of cells is inactive; and processing, using the computer, simulation events for at least one of the plurality of cells when the assigned activity classification for said at least one of the plurality of cells is active.