Patent ID: 8716994

Claim:
A circuit, comprising: a steady-state block including steady-state circuitry, a load coupled to an output node of the steady-state circuitry and representing a load condition, and a steady-state bias current source configured to provide a steady-state bias current to the steady-state circuitry during steady-state operation; and a startup block including startup circuitry and a startup bias current source configured to provide a startup bias current to the startup circuitry during a startup mode, the startup bias current being significantly larger than the steady-state bias current; wherein the startup circuitry has operational characteristics substantially similar to the steady-state circuitry but without the load condition such that, during the startup mode, the startup circuitry is configured to drive a common node to which both the startup circuitry and the steady-state circuitry are connected to a desired state, the common node being different than the output node of the steady state circuitry, the desired state being substantially the same as achieved by the steady-state circuitry during steady-state operation with the load condition.