Patent ID: 8799736

Claim:
An apparatus comprising: an LDPC (Low Density Parity Check) decoder circuitry configured to decode: a first LDPC coded signal based on a first LDPC code using a first LDPC matrix, based on a first configuration of a superimposed LDPC matrix, to generate a first plurality of estimates of a first plurality of information bits encoded therein; and a second LDPC coded signal based on a second LDPC code using a second LDPC matrix, based on a second configuration of the superimposed LDPC matrix, to generate a second plurality of estimates of a second plurality of information bits encoded therein, wherein the apparatus compliant to operate based on a communication standard or recommended practice that includes a plurality of LDPC codes that includes the first LDPC code having a first code rate and the second LDPC code having a second code rate that is different than the first code rate.