Patent ID: 7437632

Claim:
A device comprising: a first supply node to provide a first voltage, and a second supply node to provide a second supply voltage, wherein the first voltage includes a supply voltage of the device, and wherein the second supply node includes a ground potential; a plurality of memory segments connected in parallel with each other between the first and second supply nodes and a plurality of internal nodes, wherein each of the internal nodes is to receive the voltage from one of the first and second supply nodes, wherein each memory segment of the plurality of memory segments includes memory cells, each of the memory cells including a first storage node and a second storage node to store data; a plurality of switching units, each of the switching units connecting in series with a corresponding memory segment of the memory segments between the first and second supply nodes and a corresponding internal node of the internal nodes, wherein within the corresponding memory segment, the corresponding internal node is coupled to the first storage node of each of the memory cells through only one first transistor, and the corresponding internal node is coupled to the second storage node of each of the memory cells through only one second transistor, wherein each of the switching units includes an input node for receiving a select signal to electrically disconnect the corresponding memory segment from the corresponding internal node based on a state of the select signal, and wherein within the corresponding memory segment, each of the memory cells is electrically disconnected from the corresponding internal node when the corresponding memory segment is electrically disconnected from the corresponding internal node; and a redundant array for replacing at least one memory segment of the plurality of memory segments.