Patent ID: 7785991

Claim:
A process for integrating a III-N component on a (001) or (100) nominal silicon substrate, the process comprising the steps of: arranging a texture of elementary areas each comprising an individual surface, the texture comprising at least one hosting area intended to receive a III-N component; depositing a mask layer on the non-hosting areas which are not intended to receive a III-N type component; locally preparing the at least one hosting area so as to generate on the surface of the hosting area one domain comprising one single type of terrace; growing by Molecular Beam Epitaxy (MBE) or Metalorganic Vapor Phase Epitaxy (MOVPE) on the at least one hosting area one intermediary AlN buffer layer, and then growing one III-N based material so as to realize a substantially monocrystalline structure; eliminating the mask layer located on the non-hosting areas and surface polycrystalline layers deposited above the mask layers; and subsequently integrating MOS/CMOS structures on at least some of the non-hosting areas.