Patent ID: 7674659

Claim:
A method for fabricating a thin film transistor comprising: providing the thin film transistor that includes a substrate, a buffer layer, an activation layer formed on said buffer layer, and a gate insulation layer formed on said buffer layer and said activation layer, with said buffer layer having a step formed between a lower part of said activation layer and a part except said lower part of said activation layer, and said step being up to a half of the thickness sum of said activation layer and gate insulation layer; forming a polycrystalline silicon layer; forming the activation layer by etching said polycrystalline silicon layer; treating a surface of said activation layer; and depositing the gate insulation layer on said substrate, with etching time being controlled in the activation layer forming process and the activation layer surface treatment process to accommodate the step between a lower part of a gate in said buffer layer and a part except the lower part of said gate having a step value corresponding up to a half of the thickness sum of said activation layer and gate insulation layer.