Patent ID: 7709323

Claim:
A method of forming a NAND-type nonvolatile memory device, the method comprising: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends in one direction; forming a first insulating layer covering an entire surface of the semiconductor substrate; patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region; forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures; patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region; forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction; forming a second insulating layer covering an entire surface of the semiconductor substrate; forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source; and forming a capping insulating layer covering an entire surface of the semiconductor substrate including an upper surface of the source line pattern; and forming a bit line plug continuously penetrating the capping insulating layer, the second insulating layer, the semiconductor pattern and the first insulating layer and connected with the first and second common drains stacked.