Patent ID: 7091116

Claim:
A method of manufacturing a semiconductor device, comprising: depositing a gate insulating layer on an active region of a self aligned silicide (salicide) region and a non-self aligned silicide (salicide) region of a semiconductor substrate; forming a gate electrode, a poly crystal silicon layer, on the gate insulating layer of the self aligned silicide (salicide) region; forming a spacer on both sidewalls of the gate electrode; depositing a suicide shielding layer on the whole surface of the semiconductor substrate including the gate electrode and spacer; forming a photoresist on the silicide shielding layer of the non-self aligned silicide(salicide) region; removing the silicide shielding layer of the self aligned silicide(salicide) region by isotropic wet etching to expose an upper surface of the gate electrode and a portion of the spacer and to leave the silicide shielding layer in the area between the gate electrodes; performing a pre-amorphization ion-implantation to render the poly crystal silicon layer of the gate electrode amorphous, without removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region, not to implant ions into the silicide shielding layer of the non-self aligned silicide(salicide) region; removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region and cleaning the semiconductor substrate; and depositing a metal layer for forming a silicide layer over the whole surface of the semiconductor substrate and then forming the silicide layer only on the gate electrode of the self aligned silicide (salicide) region by annealing the semiconductor device.