Patent ID: 7655991

Claim:
A semiconductor structure comprising: a first metal-oxide-semiconductor (“MOS”) transistor of a first type having a first channel region, a first gate having a first sidewall and a second sidewall, a first sidewall spacer disposed on the first sidewall; and a second sidewall spacer disposed on the second sidewall, wherein the first sidewall spacer and the second sidewall spacer are made of a first selectively stressed material having a first type of stress so as to promote carrier mobility in the first channel region; a second MOS transistor of a second type, the first MOS transistor and the second MOS transistor forming a complementary MOS (“CMOS”) cell, the second MOS transistor having a second channel region; a second gate having a third sidewall and a fourth sidewall; a third sidewall spacer disposed on the third sidewall; and a fourth sidewall spacer disposed on the fourth sidewall, wherein the third sidewall spacer and the fourth sidewall spacer are made of a second selectively stressed material having a second type of stress so as to promote carrier mobility in the second channel region; and residue of the second selectively stressed material on at least one of the first sidewall spacer and the second sidewall spacer, wherein the residue remains from an etching step forming the third sidewall spacer and the fourth sidewall spacer disposed on the second gate, and wherein one of the first type of stress and the second type of stress comprises a tensile stress and the other of the first type of stress and the second type of stress comprises a compression stress and the width of the first sidewall spacer and the second sidewall spacer are selected to account for the width of the second selectively stressed material on at least one of the first sidewall spacer and the second sidewall spacer.