Patent ID: 7017132

Claim:
A method for synthesizing a clock distribution circuit within an integrated circuit device, said device comprised of a plurality of functional circuits and placed on a substrate, said method comprising the steps of: allocating at least one delaying circuit within each of said functional circuits; fabricating an intra-functional clock distribution network within each of the functional circuits; fabricating an inter-functional clock distribution network between each of the functional circuits; determining a clock skew for the inter-functional clock distribution network; and compensating for the clock of said inter-functional clock distribution network by inserting said delaying circuit at a terminal of said inter-function clock distribution network wherein each of said functional circuits is connected to said inter-functional clock distribution network and said delaying circuit includes a plurality of delaying buffer circuits that are serially connected by a plurality of interconnecting wiring segments, each delaying buffer circuit having a first increment of delay and said interconnecting wiring segments having a second increment of delay.