Patent ID: 7823013

Claim:
A method for use in a computing system, the method comprising: initiating execution of a code sequence; a first processing unit utilizing a first copy of a given memory line corresponding to the code sequence during said execution, and a second processing unit utilizing a second copy of the given memory line during said execution, said given memory line comprising a plurality of subsections and a check bit for each subsection; clearing first check bits prior to utilization of the first copy by the first processing unit, and clearing second check bits prior to utilization of the second copy by the second processing unit; the first processing unit setting a first check bit of the first check bits, in response to modifying a subsection of said first copy that corresponds to the first check bit, and the second processing unit setting a second check bit of the second check bits, in response to modifying a subsection of said second copy that corresponds to the second check bit; comparing first check bits of the first copy to second check bits of the second copy; detecting a race condition, in response to determining a same check bit is set in both of the first check bits and the second check bits; and generating an interrupt in response to detecting said race condition.