Patent ID: 8909493

Claim:
A method of adaptively operating a three dimensional non-volatile memory formed in multiple layers of memory cells disposed above a substrate, comprising: operating at least some blocks of the three dimensional non-volatile memory using a sub-block erase scheme to separately erase cells of a sub-block in a block which includes other memory cells connected in series with the cells of the sub-block which retain data throughout the separate erasing of the sub-block; identifying a plurality of memory cells to be accessed in an operation, the plurality of memory cells located in a first sub-block of a target block; identifying a second sub-block that is in the target block, memory cells of the second sub-block connected in series with memory cells of the first sub-block; determining a condition of the second sub-block as written or erased; and subsequently, if the second sub-block is written then selecting a first set of parameters for accessing the plurality of memory cells in the operation; and if the second sub-block is erased then selecting a second set of parameters for accessing the plurality of memory cells in the operation, the second set of parameters being different from the first set of parameters.