Patent ID: 8044449

Claim:
A memory device, comprising: a substrate; a trench having an upper portion and a lower portion formed in the substrate; a trench capacitor formed in the lower portion of the trench; a collar dielectric layer formed on a sidewall of the trench above the trench capacitor and extending away from a top surface of the substrate; a first doping area formed on a side of the upper portion of the trench in the substrate for serving as source/drain; a conductive layer formed in the trench and electrically connected to the first doping area; a top dielectric layer formed on the conductive layer; a gate formed on the top dielectric layer; an epitaxy layer formed on both sides of the gate and on the substrate; a second doping area formed on a top of the epitaxy layer for serving as source/drain; and a channel formed between the first doping area and the second doping area, wherein in the epitaxy layer, first doping area and second doping area are arranged such that a length of the channel is controlled by a thickness of the epitaxy layer.