Patent ID: 8132131

Claim:
A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: an integrated circuit having: a set of failing address registers (FARs) and an associated set of redundant memory elements, wherein each failing address register (FAR) in the set of FARs has a one-to-one correspondence with a redundant memory element in the associated set of redundant memory elements; and control logic for performing the following: testing a set of memory elements using a built in self test (BIST) system; placing an address of each failing memory element into a corresponding FAR in the set of FARs; marking each corresponding FAR as used when a single address of a failing memory element is placed into the corresponding FAR, wherein the marking of the corresponding FAR as used includes adjusting a first status bit in the corresponding FAR, wherein the failing address remains in the corresponding FAR until the failing address is issued to a set of compare circuitry; testing each redundant memory element using the BIST system; marking at least one FAR in the set of FARs as bad when a redundant memory element corresponding to the at least one FAR fails, wherein the marking of the at least one FAR as bad includes adjusting a second status bit in the FAR; and readdressing each of the memory elements in the set of memory elements by issuing the memory element addresses to the set of compare circuitry and using an address bus to place an address of a memory element in the set of memory elements being readdressed into a new FAR in the set of FARs when the address of the memory element being readdressed matches an address stored in a FAR in the set of FARs that has been marked as bad, wherein the readdressing includes reissuing the address of each of the memory elements.