Patent ID: 7764749

Claim:
A system comprising a phase tracker for tracking a phase of received data, which phase tracker comprises: an interpolator for interpolating the received data and for generating at least two streams of interpolated samples, an error detector, in response to interpolated samples, generating error signals per stream, a combiner for combining error signals and for generating a combined error signal, and a indicator generator, in response to the combined error signal, generating an indicator signal to be supplied to the interpolator for, in response to the indicator signal, adjusting the interpolator; wherein the combiner comprises a quantizer for quantizing the error signals; wherein the combiner comprises a filter for filtering the error signals and for generating filtered error signals to be supplied to the quantizer; wherein the received data comprises in-phase data and quadrature data, with each stream of interpolated samples comprising a stream of in-phase interpolated samples and a stream of quadrature interpolated samples, and with the error detector comprising a first delay element for receiving the in-phase interpolated samples and a second delay element for receiving the quadrature interpolated samples, with an input of the first delay element being coupled to a positive input of a second adder, with an output of the first delay element being coupled to an input of a third delay element, with an output of the second delay element being coupled to an input of a fourth delay element with an output of the third delay element being coupled to a negative input of the first adder, with an output of the fourth delay element being coupled to a negative input of the second adder, with an output of the first adder being coupled to a first input of a first multiplier, with an output of the second adder being coupled to a first input of a second multiplier, with a second input of the first multiplier being coupled to the output of the first delay element, with a second input of the second multiplier being coupled to the output of the second delay element, with an output of the first multiplier being coupled to a first positive input of a third adder, with an output of the second multiplier being coupled to a second positive input of the third adder, which third adder comprises an output for generating the error signals to be supplied to the integrator.