Patent ID: 7426705

Claim:
A method for checking an integrated circuit that includes a core which contains a scan chain, a functionally reconfigurable module (FRM) coupled to the core, and a controller, in an arrangement that includes a tester coupled to said integrated circuit, comprising the steps of: (i) selecting a set of assertions with which to test said integrated circuit; (ii) replacing two or more of the assertions in the selected set of assertions with a subsuming assertion, to form thereby a reduced set of assertions, where a subsuming assertion (1) is characterized by a logic expression that contains fewer terms, or fewer variables, or both, than the logical union of the replaced assertions, and (2) assumes a given logic level whenever the logical union of the replaced assertions assumes said given logic level; (iii) configuring the reduced set of assertions in said FRM; (iv) applying a signal to said integrated circuit; (v) when said FRM indicates that one of the configured assertions fired, indicating that the assertion failed to yield an expected result, (a) determining whether the fired assertion is said subsuming assertion; (b) if said step of determining concludes that said fired assertion is said subsuming assertion, applying signals that cause said scan chain to provide data to said tester; and (c) analyzing said signals in said tester to determine whether any one of the replaced assertions also fires.