Patent ID: 8823434

Claim:
A clock correction circuit comprising: an operation clock generation circuit that calculates an accumulated value by accumulating fixed values determined by the required frequency of an operation clock on the basis of the clock pulses of a first clock, reflects an error value corresponding to frequency errors of the first clock in the accumulated value at a timing determined by the first clock, changes the state of the operation clock when the predefined bit of the accumulated value changes, and outputs a lower-bit value that is a part of the accumulated value and a value represented by the bits lower than the predefined bit as well; and a correction clock generation circuit that converts the lower-bit value into the count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, and generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the clock pulses and the clock pulses of the operation clock.