Patent ID: 8413123

Claim:
A compiling device compiling a source program written so as to use a frame memory, the compiling device comprising: a processor, the compiling device for execution on the processor; a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data to be processed by the process tasks; a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data; an instruction code converter configured to convert a plurality of the process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes; a directed graph generator configured to generate, on the basis of access states of the plurality of process tasks making access to a plurality of the frame memories, a directed graph in which nodes of the plurality of process tasks are connected to nodes of the plurality frame memories through directed edges; an access range extractor configured to extract access ranges in frame memories to which the plurality of process tasks make read access with a certain cycle; an access range adder configured to add the extracted access ranges to labels of the corresponding directed edges; a reference node determiner configured to determine as a reference node a last process task to be executed or a last frame memory to be written to in pipeline execution and to set data location information representing a reference data for the determined reference node; and a data location calculator configured to calculate data location information to be written in each of the frame memories and data location information on which each of the process tasks is executed, on the basis of the set data location information representing the reference data and to add the calculated data location information to each corresponding one of the frame memories and each corresponding one of the process tasks.