Patent ID: 8406360

Claim:
A signal generating method for clock recovery for, in order to recover a clock signal for extracting a second data of N clocks' (N: positive integer, N<M) in a first data of M clocks' (M: positive integer), generating a signal for clock recovery which is formed by alternately generating enable periods having a ratio (N/M) of the second data to the first data and disable periods, and for, when a stuff pulse to be previously inserted in the first data is detected from the first data during the enable period, adding a disable period during the enable period, wherein phases of the enable period and the disable period are presented to the signal for clock recovery and phase information corresponding to a clock signal included in the first data is provided thereto, and in order to add a disable period during the enable period, a phase corresponding to the disable period during the enable period is found based on the phase information when the stuff pulse is detected, and a phase of the disable period to be generated after the stuff pulse is detected is advanced by the found phase.