Patent ID: 8321627

Claim:
A memory controller for controlling operation of a data storage device, the memory controller comprising: a plurality of command queues, each command queue being operationally associated with one of a plurality of memory devices included in the data storage device, each of the command queues being configured to store memory operation commands pending execution by its respective memory device; and a latency manager operationally coupled with the plurality of command queues, the latency manager being configured to, respectively, for each of the plurality of memory devices: receive, from a host device, memory operation commands for execution by their respective memory device; maintain a respective cumulative latency estimate for the respective memory device, the respective cumulative latency estimate indicating an estimated amount of time that currently pending memory operation commands for the respective memory device will take to complete execution; and for each memory operation command, when received by the latency manager: compare the respective cumulative latency estimate with a latency threshold for the received memory operation command; in the event the respective cumulative latency estimate is at or below the latency threshold, provide the received memory operation command to the respective command queue; and in the event the respective cumulative latency estimate is above the latency threshold, return the received memory operation command to the host device.