Patent ID: 7820500

Claim:
A method for forming a semiconductor integrated circuit device comprising: providing a semiconductor substrate including a first well region and a second well region; forming a dielectric layer overlying the semiconductor substrate including the first well region and the second well region; forming a polysilicon gate layer overlying the dielectric layer, the polysilicon gate layer being overlying a first channel region in the first well region and a second channel region in the second well region in the semiconductor substrate; forming a hard mask layer overlying the polysilicon gate layer; patterning the polysilicon gate layer, including the hard mask layer, to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region; forming a liner layer overlying the first gate structure and the second gate structure and overlying a first source region and a first drain region in the first well region and a second source region and a second drain region in the second well region; forming a spacer dielectric layer overlying the liner layer; patterning the spacer dielectric layer to form first sidewall spacer structures on the first gate structure and to form second sidewall spacer structures on the second gate structure, the first sidewall spacer structures including the first edges and the second sidewall spacer structures including the second edges; maintaining the liner layer overlying the first source region and the first drain region and the second source region and the second drain region during at least the patterning of the spacer dielectric layer; etching a portion of each of the first source region and the first drain region adjacent to the first gate structure using the hard mask layer, a first portion of the liner layer, and the first sidewall spacers as a protective layer while protecting the second well region including the second gate structure and the second side wall spacer structures using a masking layer during the etching of the first source region and the first drain region, maintaining at least the second well region un-etched; and depositing a silicon germanium fill material into each of the etched first source region and the etched first drain region to fill each of the etched first source region and the etched first drain region and causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region while at least the second source region and the second drain region are masked by a second portion of the liner layer.