Patent ID: 8418042

Claim:
A semiconductor memory device comprising: a plurality of memory chips configured to store therein data, each of the plurality of memory chips including a plurality of second storage areas, and each of the second storage areas including a plurality of first storage areas each being a unit for storing and reading data, wherein the data includes plural pieces of first data each including plural pieces of second data to be stored, and plural pieces of third data each including plural pieces of the second data each of which is selected from each of the pieces of the first data of each of a plurality of first memory chips among the plurality of the memory chips so that the plural pieces of the second data included in one piece of the third data are different from those included in different pieces of the third data; the device further includes: a first error check code generation unit configured to generate first error check codes on a basis of respective pieces of the first data; a first error correction code generation unit configured to generate first error correction codes which are systematic codes on a basis of respective pieces of the first data and respective first error check codes; a recording unit configured to record the first data, the first error check codes, and the first error correction codes in the first storage areas of each of the plurality of the first memory chips; and a second error correction code generation unit configured to generate a redundant code that is a Reed-Solomon code for each of the plural pieces of the third data, the data further includes plural pieces of fourth data each having same size as that of the first data and including the redundant codes generated from all the plural pieces of the third data, and the redundant codes including in one piece of the fourth data are different from those included in different pieces of the fourth data; the device further includes: a second error check code generation unit configured to generate second error check codes from respective pieces of the fourth data; and a third error correction code generation unit configured to generate second error correction codes which are systematic codes on a basis of the respective pieces of the fourth data and respective second error check codes; and the recording unit further records the fourth data, the second error check codes, and the second error correction codes in a second memory chip among the plurality of the memory chips.