Patent ID: 8237648

Claim:
A liquid crystal display device having a single source printed circuit board comprising: a liquid crystal display panel including a first data line group, a second data line group, and line-on-glass (LOG) wirings separated from the first and second data line groups; a first integrated circuit (IC) group operating in accordance with timing control signals, to convert digital video data into a data voltage, and to supply the data voltage to the first data line group; a first source printed circuit board (PCB), to which ICs included in the first IC group are coupled; a second IC group receiving the timing control signals and the digital video data from the first integrated circuit group via the first source PCB and the LOG wirings, and operating in accordance with the timing control signals, to convert the digital video data into the data voltage, and to supply the data voltage to the second data line group; a second PCB, to which ICs included in the second IC group are coupled; a timing controller including a single output port to output the timing control signals and the digital vide data; a control PCB, on which the timing controller is mounted; and a connector connected to the control PCB and the first source PCB, to transfer the timing control signals and the digital video data output through the single output port of the timing controller to the first source PCB, wherein each IC of the first and second IC groups includes a polarity control signal generator for generating a polarity control signal to control a polarity of the data voltage, using a part of the timing control signals, wherein the polarity control signal generator generates the polarity control signal, using a gate start pulse indicating a start horizontal line, from which a scan operation starts in one vertical period for displaying one frame, and a source output enable signal enabling the digital video data to be output, wherein the polarity control signal generator includes a first D-flip-flop using the source output enable signal as an input clock, the first D-flip-flop generating a first polarity control signal inverted in logic state with reference to a rising edge of the source output enable signal generated for every vertical period; a second D-flip-flop using the gate start pulse as an input clock, the second D-flip-flop generating a select signal inverted in logic state with reference to the rising edge of the gate start pulse generated for every vertical period; and a multiplexer receiving the first polarity control signal and a second polarity control signal, which has a logic value opposite to the first polarity control signal, and alternately outputting the first and second polarity control signals at intervals of one vertical period, in response to the select signal, wherein the multiplexer alternately selects the first and second polarity control signals at intervals of one vertical period, in response to the select signal from the second D-flip-flop, and outputs the selected signal as a final polarity control signal.