Patent ID: 8860651

Claim:
A gate driver comprising a plurality of cascade-connected driving stages, each of the driving stages comprising: a first shift register circuit comprising: a first input unit for outputting a first control signal according to a previous stage driving signal; a first drive output unit for outputting a present stage driving signal according to the first control signal and a first driving clock signal; and a second drive output unit for outputting a next stage driving signal according to the first control signal and a second driving clock signal; and a second shift register circuit electrically coupled to the first shift register circuit, the second shift register circuit comprising: a second input unit for outputting a second control signal according to the previous stage driving signal; a first output unit for outputting a present stage gate signal according to the second control signal and a first gate clock signal; a second output unit for outputting a first next stage gate signal according to the second control signal and a second gate clock signal; and a third output unit for outputting a second next stage gate signal according to the second control signal and a third gate clock signal, wherein the first driving clock signal and the second driving clock signal have a high voltage level of a power voltage and a low voltage level of a first reference voltage, and the first gate clock signal, the second gate clock signal and the third gate clock signal have a high voltage level of the power voltage and a low voltage level of a second reference voltage, wherein the second reference voltage is greater than the first reference voltage.