Patent ID: 7545166

Claim:
A field programmable gate array comprising: a low voltage signaling driver circuit having a first input line, a second input line, a first output line, and a second output line comprising: a first output buffer having an input and an output connected to the first output line; a second output buffer having an input and an output connected to the second output line; a delay circuit responsively connected to said first input line; an inverter responsively connected to said first input line; a first multiplexer having a first input connected to an output of said delay circuit, a second input connected to said first input line, a selector, and an output connected to the input of said first output buffer; and a second multiplexer having a first input connected to an output of said inverter, a second input connected to said second input line, a selector, and an output connected to the input of said second output buffer; and programmable elements coupled to the selectors of and providing signals to control the first multiplexer and the second multiplexer.