Patent ID: 7369435

Claim:
A method of forming a memory cell, comprising: forming a floating gate transistor in a modified dynamic random access memory fabrication process, wherein forming the floating gate transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming an array plate; forming a conductive plug coupling the first source/drain region to the array plate; and forming a bitline coupled to the second source/drain region such that the memory cell can be programmed to have a trapped charge in the floating gate by biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the control gate by a wordline address, and wherein a programmed floating gate transistor will operate at reduced drain source current in a forward direction.