Patent ID: 8074133

Claim:
A method for testing at least one domain of a processor device including a plurality of domains, the method comprising: generating at least a first clock stop signal and a second clock stop signal at a clock control module; transmitting the first clock stop signal to a first gate coupled to a first one of the plurality of domains; transmitting the second clock stop signal to a second gate coupled to a second one of the plurality of domains; and serially controlling propagation of a clock signal into: the first domain at the first gate by deasserting the first clock stop signal during a first time period; and the second domain at the second gate by deasserting the second clock stop signal during a second time period; wherein the second period of time occurs after the first period of time; and wherein the first gate only controls propagation of the clock signal into the first domain, and wherein the second gate only controls propagation of the clock signal into the second domain; and serially testing the first domain and second domain by: providing a test pattern to the first domain while deasserting the first clock stop signal at the first gate; and providing a new test pattern to the second domain while deasserting the second clock stop signal at the second gate.