Patent ID: 7876139

Claim:
A semiconductor device, comprising: a delay locking unit configured to compare a phase of a feedback clock with a phase of a reference clock, and configured to delay an internal clock corresponding to a clock edge of the reference clock by a delay amount corresponding to a comparison result to output a delay locked loop (DLL) clock; a split unit configured to receive and split the DLL clock to output a first clock corresponding to a first edge of the DLL clock and a second clock corresponding to a second edge; an operation control unit configured to generate a reset signal, an enable signal and a comparison control signal in response to the DLL clock provided from the delay locking unit; a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock in response to the reset signal and the enable signal; a voltage comparison unit configured to compare a level of the first voltage with a level of the second voltage in response to the comparison control signal; and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.