Patent ID: 7487296

Claim:
A processor comprising: a cache; and a multi-stride prefetcher coupled to said cache, wherein said multi-stride prefetcher fetches information into said cache for both (1) a stream of cache misses with a plurality of strides wherein said plurality of strides includes valid different strides for different portions of said stream and (2) another stream of cache misses having a single stride, and further wherein said valid different strides for different portions of said stream includes a first valid stride for a first portion of said stream, and a second valid stride for a second different portion of said stream wherein said first and second valid strides exist simultaneously, said multi-stride prefetcher further comprising: a state machine implementation having a plurality of states for prefetching said stream with said plurality of strides, wherein said state machine implementation comprises: said first valid stride associated with a first state of said states; and said second valid stride associated with a second state of said states wherein said first and second states are different states.