Patent ID: 8312208

Claim:
A memory access controller for performing access control to a memory, comprising: a packet memory which stores a packet, the packet memory having a clock parallel outputting function of parallel-outputting, during reading of first data, the first data and a clock synchronized with the first data; an information memory which stores a read start address where head data of the packet is stored, the read start address being an address of the packet memory; a read controller which generates a read address and reads the first data from the packet memory; a clock transfer unit which performs a clock transfer operation by writing, using the clock, the first data read from the packet memory and reading second data using a system clock; and a packet assembly unit which receives the second data after the clock transfer operation and reassembles the packet, wherein: the information memory stores first packet length information indicating a length of the packet as well as storing the read start address; the read controller receives the read start address and the first packet length information, generates the read address necessary for reading one packet, and reads the first data from the packet memory; the packet memory stores head pulse information indicating the head data of the packet as well as storing the packet; and the packet assembly unit reassembles the packet by detecting the head data from the head pulse information output from the packet memory, extracting second packet length information set in a field of the head data, recognizing a data range of a reassembly target packet according to the second packet length information indicating the length of the packet, and arraying the second data contained within the data range after the clock transfer operation.