Patent ID: 7743304

Claim:
A test system, comprising: a shared processor operable to generate test data for performing tests on devices under test and to generate a respective test control signal for each of said devices under test, said test data including stimuli for the devices under test, and each said test control signal including test instructions for performing said tests; a storage device operable to store said test data associated with at least one of said devices under test, wherein the storage device is capable of simultaneously storing test data associated with multiple ones of said test instructions; and for each of said devices under test, a dedicated processor operable to receive said respective test control signal from said shared processor, and in response to said respective test control signal, transfer said test data associated with a respective one of said test instructions from said storage device to said one of said devices under test in accordance with said respective test instructions, said dedicated processor being further operable to i) receive output data from the one of the devices under test to verify the completion of said respective test instructions, and to ii) generate a test outcome signal to the shared processor in response to said output data, said test outcome signal indicating completion of the respective one of the test instructions; wherein the shared processor is operable to i) generate and store in the storage device test data for a first test instruction during a first clock cycle, and ii) generate and store in the storage device test data for a second test instruction during a second clock cycle, prior to receiving the test outcome signal indicating completion of the first test instruction from the dedicated processor for at least one of the devices under test.