Patent ID: 7135779

Claim:
A method for fabricating packaged integrated circuit dies in a wafer format, said method comprising: providing a wafer substrate, said wafer substrate having a top surface and a bottom surface; fabricating a plurality of integrated circuits on the top surface of the wafer substrate, each of the integrated circuits being separated from each other by scribe lanes; forming signal vias through the substrate relative to the integrated circuits; depositing top-side bond pads on the top surface of the substrate in contact with the signal vias, said top-side pads being in electrical contact with an integrated circuit; depositing back-side bond pads on the bottom surface of the substrate in contact with the signal vias to make an electrical connection between the top-side pads and the back-side pads; depositing a top-side protective layer on the wafer substrate to cover the top-side pads and the integrated circuits; removing portions of the substrate material in the scribe lanes from the bottom of the substrate between the integrated circuits; depositing a back-side protective layer on the wafer substrate so that the back-side layer fills the removed portions of the substrate in the scribe lanes and contacts the top-side protective layer; forming signal vias through the back-side layer to be in electrical contact with the back-side bond pads; and cutting the wafer substrate in the scribe lanes to separate the wafer into the packaged dies so that an outer surface of the packaged dies includes exposed signal vias to make electrical connections thereto.