Patent ID: 8904632

Claim:
A method of making a multilayer circuit board from a plurality of circuit board layers, each comprising a dielectric layer and conductive traces thereon comprising a first metal, the method comprising: forming a through-via in a first circuit board layer; plating the through-via with the first metal; selecting a second metal to have a melting temperature below a lamination temperature of the dielectric layers; coating the second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal of a second circuit board layer; aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer; and heating and pressing the aligned first and second circuit board layers so as to directly laminate the dielectric layers together without using adhesive material, and form a joint comprising an intermetallic compound of the first and second metals bonding adjacent metal portions together and defining electrical connection paths of the multilayer circuit board, the intermetallic compound having a melting temperature above the lamination temperature of the dielectric layers.