Patent ID: 7334061

Claim:
An interface bus comprising: a set of address lines to convey a selection of one of a plurality of memory locations as a selected memory location for a data-transfer operation on the bus, the selection being based on an address value presented on the address lines by a device coupled to the bus; at least one read/write line to convey an indication of whether a first type of data-transfer operation is to be performed on the interface bus, the first type of data-transfer operation either comprising a read operation of a selected memory location or comprising a write operation of a selected memory location; N groups of data lines for conveying the data to be transferred in a data-transfer operation involving a selected memory location, N being at least two; and g group-enable lines for conveying indications of which groups of data lines are to be used in a data-transfer operation involving a selected memory location, wherein the group-enable lines are operable to convey an indication that at least two groups of data lines are to be used together in a data-transfer operation, and further operable to convey separate indications that each of the at least two groups is to be used alone in separate data-transfer operations.