Patent ID: 6867617

Claim:
A method for deriving a fractional-rate clocked logic circuit from a full-rate clocked logic circuit comprising combinatorial functions and sequential functions for operating on block input signals to produce block output signals, wherein the sequential functions operate at a full-rate clock frequency, the method comprising: deriving combinatorial logic elements based on the combinatorial functions, each of the combinatorial logic elements responsive to a subset of the block input signals for producing combinatorial signals; deriving sequential logic elements based on the sequential functions, each of the sequential logic elements responsive to a subset of the combinatorial signals and a fractional clock signal for producing register signals, wherein a frequency of the fractional clock signal is a fraction of the full rate clock frequency, and wherein at least one of the sequential logic elements further produces a register feedback signal; wherein certain of the combinatorial logic elements are each further responsive to a subset of the combinatorial signals, and wherein at least one of the combinatorial logic elements is further responsive to the register feedback signal; and combining the register signals for producing the block output signals.