Patent ID: 8624659

Claim:
An analog multiplier comprising: a voltage controlled resistance circuit including: a first node; a second node coupled to a reference voltage; a control node coupled to a first input voltage source; a reference current source including a first node coupled to a supply voltage and a second node and configured to provide a reference current; a first transistor including a source coupled to the reference voltage, a drain, and a gate; a first resistor including a first terminal coupled to the second node of the reference current source and a second terminal coupled to the drain of the first transistor; a first operational amplifier including an inverted input coupled to the control node of the voltage controlled resistance circuit, a non-inverted input coupled to the second node of the reference current source, and an output in communication with the gate of the first transistor; a second transistor including a gate in communication with the output of the first operational amplifier, a source coupled to the reference voltage, and a drain; and a second resistor including a first terminal coupled to the drain of the second transistor and a second terminal coupled to the first node of the voltage controlled resistance circuit.