Patent ID: 7718492

Claim:
A method for fabricating a non-volatile memory cell, the method comprising: forming a first floating gate transistor of a first conductivity type on a semiconductor substrate, the first floating gate transistor having a first and a second source/drain region disposed within the substrate, a first floating gate electrode, a first floating gate dielectric disposed between the first floating gate electrode and the substrate, the first floating gate dielectric having a first thickness; forming a second floating gate transistor of the first conductivity type on the semiconductor substrate; the second floating gate transistor having a first and a second source/drain region disposed within the substrate, a second floating gate electrode electrically coupled to the first floating gate electrode, a second floating gate dielectric disposed between the second floating gate electrode and the substrate, the source/drain regions of the first floating gate transistor having fewer dopant atoms that the source/drain regions of the second floating gate transistor so that in operation and when selected a first injection current caused by impact-ionized hot electron injection (IHEI) predominates in the first floating gate transistor to inject electrons onto the first floating gate electrode and, when selected, a second injection current caused by band-to-band tunneling (BTBT) predominates in the second floating gate transistor to inject electrons onto the second floating gate electrode; forming first select circuitry on the semiconductor substrate to selectively cause IHEI in the first floating gate transistor; and forming second select circuitry on the semiconductor substrate to selectively cause BTBT in the second floating gate transistor.