Patent ID: 8194454

Claim:
A memory device, comprising: a memory array partitioned into a plurality of memory banks; a first sense amplifier including a first latch, the first sense amplifier operably coupled with a first memory bank of the plurality of memory banks; a second sense amplifier including a second latch, the second sense amplifier operably coupled with a second memory bank of the plurality of memory banks; a buffer operably coupled with the first latch and the second latch, wherein the buffer is configured to receive first data, receive second data after sending the first data to the first latch to be programmed in the first memory bank, and send the second data to the second latch to be programmed in the second memory bank; a first data comparator operably coupled with the first sense amplifier, wherein the first data comparator is configured to verify that the first data stored in the first latch matches first sensed data programmed in the first memory bank; and a second data comparator operably coupled with the second sense amplifier, wherein the second data comparator is configured to verify that the second data stored in the second latch matches second sensed data programmed in the second memory bank.