Patent ID: 8861279

Claim:
A semiconductor memory device comprising: a memory region including an array of memory cells connected via selection lines; a voltage generating circuit; and a control circuit that feeds a voltage generated by the voltage generating circuit to the memory region via selection lines; the voltage generating circuit including: a transistor with a gate electrode, a first terminal, and a second terminal, the transistor having a power supply voltage applied to the first terminal; a first resistance element with a first and a second end, the first resistance element connected on the first end to the second terminal of the transistor; a second resistance element with a third and a fourth end, the third end being connected to the second end of the first resistance element and the fourth end being connected to a ground potential; and a comparator, having an inverted input terminal to which a reference potential is input and a non-inverted input terminal connected to a node between the second end of the first resistance element and the third end of the second resistance element, and configured to compare the reference potential with a potential at the node, the first resistance element and the second resistance element each comprising first and second conductive lines electrically interconnected by a U-shaped connector that is electrically connected to the first conductive line, a second conductive portion that is electrically connected to the second conductive line, and a third conductive portion that connects the first and second conductive portions.