Patent ID: 7969338

Claim:
A decoding circuit comprising: a first decoder configured to select a predetermined number of gradation voltages from a plurality of gradation voltages, wherein the first decoder is configured to select the predetermined number of gradation voltages according to a least significant bit or least significant bits of image data; a second decoder configured to select an output gradation voltage from said gradation voltages selected by the first decoder, wherein the second decoder is configured to output the output gradation voltage to an output terminal, wherein selection and output of the output gradation voltage is in accordance with a plurality of selection signals; and a third decoder configured to output the plurality of the selection signals according to a most significant bit or most significant bits of the image data, wherein a minimum length of gates of a plurality of MOSFETs comprised in the first decoder is shorter than a minimum length of gates of a plurality of MOSFETs comprised in the second decoder, wherein the first decoder comprises a plurality of decoding groups; and each of the plurality of the decoding groups comprising a plurality of MOSFETs having a plurality of gate voltages of an identical high level and an identical low level applied thereto, and different decoding groups of the plurality of the decoding groups having gate voltages of different high levels and low levels applied thereto, wherein the circuit further comprises a plurality of level shifters configured to apply gate voltages having different high levels and low levels to the different decoding groups.