Patent ID: 8273590

Claim:
A method for manufacturing an array substrate, comprising: forming a thin film transistor, a pixel region, and a storage capacitor on a substrate, respectively; forming a passivation layer on the thin film transistor, the pixel region, and the storage capacitor; forming a first photoresist layer on the passivation layer; performing a lithography process by a first multi-tone photomask to pattern the first photoresist layer, thereby forming a first non-photoresist region, a first thin photoresist pattern, and a first thick photoresist pattern, wherein the first non-photoresist region substantially corresponds to a part of a drain electrode of the thin film transistor and a part of the storage capacitor, the first thin photoresist pattern substantially corresponds to the pixel region, and the first thick photoresist pattern substantially corresponds to the thin film transistor except for the part of the drain electrode; removing the passivation layer of the first non-photoresist region to expose the part of the drain electrode of the thin film transistor and the part of the storage capacitor; ashing the first thin photoresist pattern to expose the passivation layer of the pixel region; selectively depositing a conductive layer on the exposed part of the drain electrode of the thin film transistor, the exposed part of the storage capacitor, and the exposed part of the passivation layer; and removing the first thick photoresist pattern.