Patent ID: 7777270

Claim:
A nonvolatile semiconductor memory device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed on the first insulating film; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a charge storing layer formed on the gate insulating film, a second insulating film formed on the charge storing layer, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell, the source region being formed in the semiconductor substrate; a drain region having a metal electrode formed in the other side of the NAND cell, the drain region being formed in the semiconductor substrate; a first select gate transistor formed in a first portion of the semiconductor substrate, the first portion being located between the one end of the NAND cell and the source region; and a second select gate transistor formed in a second portion of the semiconductor substrate, the second portion being located between the other end of the NAND cell and the drain region.