Patent ID: 7414561

Claim:
A digital to analog converter that produces an analog output voltage indicative of a digital input signal, the digital input signal having a first subword of more significant bits and a second subword of less significant bits, the converter comprising: a split-core resistive element comprising at least first and second resistive strings configured in such a configuration as to provide the analog output voltage with at least partial insensitivity to error gradients; and an interpolation circuit coupled to the split-core resistive element, said interpolation circuit having at least first and second switching banks and first and second composite transistors, an output of said interpolation circuit used to generate the analog output voltage; wherein at least a first switch in said first switching bank is configured to couple one or more voltages transmitted from said first resistive string to at least a first subtransistor in said first composite transistor based at least on a least significant bit of the digital input signal; and wherein none of the switches in said second switching bank are configured to couple one or more voltages transmitted from said second resistive string to any of the subtransistors in said second composite transistor based at least on the least significant bit of the digital input signal.