Patent ID: 6996797

Claim:
A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography, the method comprising: scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image; shifting a first feature of said scaled image with respect to a second feature of said scaled image in accordance with a predetermined maximum overlay error; calculating an intersection parameter of said first and said second features of said scaled image so as to determine a yield metric of an ideal layout; shifting a first feature of a simulated wafer image of said drawn mask layout with respect to a second feature of said simulated wafer image in accordance with said predetermined maximum overlay error, wherein said first and second features of said simulated wafer image correspond to said first and second features of said scaled image; calculating an intersection parameter of said first and said second features of said simulated wafer image so as to determine a yield metric of a simulated layout; and comparing said yield metric of said simulated wafer image to said yield metric of said scaled image.