Patent ID: 6931614

Claim:
A method for placing repeating flip-flop stations on integrated circuit, comprising: receiving a layout and a netlist for the integrated circuit, wherein the layout includes a plurality of functional blocks and the netlist includes interconnection data for the plurality of functional blocks; determining a transit time for a signal on an interconnection between a first functional block and a second functional block within the plurality of functional blocks; and if the transit time exceeds an allowed time, dividing the interconnection into a first section and a second section, wherein transit times on the first section and on the second section are less than the allowed time, placing a repeating flip-flop station within an embedded channel within the functional block on the integrated circuit, wherein the repeating flip-flop station is placed in a position that allows the transit time on the first section and the second section to be met and wherein routing the first section and the second section through the repeating flip-flop station allows signal timing requirements to be met without changing circuitry within a functional block of the plurality of functional blocks, routing the first section from the first functional block to an input of a flip-flop located at the repeating flip-flop station, and routing the second section from an output of the flip-flop to the second functional block.