Patent ID: 8344266

Claim:
A printed circuit board (PCB) comprising: a first interface for a first integrated circuit (IC) having a first array of connections divided into a plurality of concentric rings organized into first, second, and third ring groups; a second interface for a second IC having a second array of connections divided into a plurality of concentric rings, the first and second interfaces disposed on a same surface of the PCB; a plurality of traces coupling the first and second interfaces; and a plurality of interconnects coupling the first and second interfaces to the plurality of traces to form a substantially pyramidal escape profile for each of the first and second interfaces, wherein a first plurality of blind microvias (μVia) of the plurality of interconnects couples all connections of the first array in the first ring group at a periphery of the array to a first plurality of the plurality of traces, wherein the first plurality of traces is routed on a surface of a first layer that is adjacent to the same surface, wherein a second plurality of blind μVias of the plurality of interconnects connected to a plurality of respective buried μVias of the plurality of interconnects couples all connections of the first array in the second ring group adjacent to and inside the first ring group to a second plurality of the plurality of traces, wherein the second plurality of traces is routed on a surface of a second layer that is adjacent to the first layer, and wherein a third plurality of blind μVias of the plurality of interconnects directly connected to a plurality of respective subcomposite vias of the plurality of interconnects couples respective connections of the first array in the third ring group adjacent to and inside the second ring group to a third plurality of the plurality of traces, wherein the third plurality of traces is routed on a surface of a third layer that is adjacent to the second layer.