Patent ID: 7627835

Claim:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of said voltage controlled oscillator coupled to an input of said feedback frequency divider, an output of said feedback frequency divider coupled to an input of said voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, said first input of said frequency divider monitor directly connected to said output of said voltage controlled oscillator and said second input of said frequency divider monitor directly connected to an output of said feedback frequency divider, wherein said frequency divider monitor including; a first and a second period generator, each said period generator having an input and an output, said input of said first period generator is said first input of said frequency divider monitor and said input of said second period generator is said second input of said frequency divider monitor; a first and a second period to voltage converter, each period to voltage converter having an input and an output, said input of said first period to voltage converter connected to said output of said first period generator and said input of said second period to voltage converter connected to said output of said second period generator; an error amplifier having a first input, a second input and an output, said output of said first period to voltage converter connected to said first input of said error amplifier and said output of said second period to voltage converter connected to said second input of said error amplifier; and a comparator having an input and an output and a plurality of threshold voltage inputs, said output of said error amplifier connected to said input of said comparator.