Patent ID: 7763965

Claim:
A structure, comprising: a carrier; a silicon interposer mechanically connected to a top surface of said carrier, said interposer having vias extending from a top surface of said interposer, through said interposer, to a bottom surface of said interposer, said vias that are exposed at said bottom surface of said interposer electrically connected to wires exposed in a top surface of said carrier; an integrated circuit chip mechanically connected to said top surface of said interposer, electrically conductive pads exposed at a surface of said integrated circuit chip electrically connected to said vias exposed in said top surface of said interposer; one or more stress relief structures formed entirely in said interposer, said one or more stress relief structures either (i) not electrically connected to said vias of said interposer or to said electrically conductive pads of said integrated circuit chip or (ii) electrically connected to ground through said vias of said interposer or through said electrically conductive pads of said integrated circuit chip; and wherein said one or more stress relief structures are in tensile stress.