Patent ID: 8139410

Claim:
An interconnect circuit, comprising: a) a first single gate nonvolatile memory transistor with a first insulator to store charge b) a second single gate nonvolatile memory transistor with a second insulator to store charge; c) a logic interconnect transistor connecting between two logic functions; d) said first and second single gate nonvolatile memory transistors connected in series between a high voltage and a low voltage, wherein the connection between the first and second single gate nonvolatile memory transistors coupled to a gate of said logic interconnect transistor through a pass gate circuit, and wherein said pass gate circuit in response to a “pass bar” signal shorts said gate of the logic interconnect transistor to ground thereby forcing the logic interconnect transistor to an off state, and couples data to program and erase said first and second nonvolatile memory transistors; and e) stored charge in said first and second insulators determines an “on” or “off” state of said logic interconnect transistor.