Patent ID: 7639088

Claim:
A method of operating a phase-locked loop (PLL) comprising a variable oscillator, the method comprising: in a first time period, programming a first reference division factor into a reference frequency divider circuit or a first feedback division factor into a feedback frequency divider circuit, the first reference division factor or the first feedback division factor causing the variable oscillator to operate outside a system operating frequency range of the variable oscillator; and in a second time period, programming a second reference division factor into the reference frequency divider circuit or a second feedback division factor into the feedback frequency divider circuit, wherein the second time period occurs immediately after the first time period, and the second reference division factor or the second feedback division factor causing the PLL to lock to a target PLL output system operating frequency, the reference frequency divider circuit is configured to divide a crystal reference frequency, and the feedback frequency divider circuit is configured to divide a frequency of the variable oscillator.