Patent ID: 7335989

Claim:
A semiconductor device, comprising: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer, the interlevel insulation film having an interlevel connection opening formed therein in an interlevel connection opening region; a barrier layer provided between the first interconnection layer and the interlevel insulation film on a region of the first interconnection layer including the interlevel connection opening region, the region having a greater area than the interlevel connection opening region; and a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film and electrically connected to the first interconnection layer via the barrier layer in the interlevel connection opening; wherein the interlevel insulation film includes a covering layer continuously extending from a side of the first interconnection layer to above the first interconnection layer, wherein the barrier layer is disposed between the covering layer and the first interconnection layer; and wherein the interlevel insulation film has a substantially flat surface.