Patent ID: 8426895

Claim:
A semiconductor device comprising: a first n-type conductive layer formed on a substrate; a p-type conductive layer formed on the first n-type conductive layer; a second n-type conductive layer formed on the p-type conductive layer; a drain electrode connected to the first n-type conductive layer on an under surface of the substrate; a source electrode in ohmic contact with the second n-type conductive layer on an upper surface of the substrate; and a gate electrode in contact with the first n-type conductive layer, the p-type conductive layer, and the second n-type conductive layer through an insulation film, wherein the gate electrode and the source electrode are alternately arranged, the p-type conductive layer and the first n-type conductive layer each comprise In y Ga 1-y N (0<y≦1), and the second n-type conductive layer comprises Al x Ga 1-x N (0<x≦1), which is different from the p-type conductive layer and the first n-type conductive layer.