Patent ID: 8335241

Claim:
A method for operating a bus system for the real-time communication of a superordinate unit with one or more subordinate units for the exchange of address information and data information and for the exchange of additional messages comprising the following procedural stages: checking whether an internal memory of a subordinate unit contains a message, whenever this subordinate unit receives a message from another subordinate unit; and entering the received message in the memory, if the memory already contains a message, and communicating the message only if all messages previously-received or entered in the memory have been communicated to the subordinate unit and communicating a message directly, whenever the message is received from a subordinate unit and the memory is empty, wherein in a serial bus system, bit information can be exchanged between units in real time via a synchronization signal, and in parallel to this, messages can be communicated in an asynchronous manner, wherein the exchange of information in real time is based upon a constantly-exchanged bit signal or clock-pulse signal between the individual units wherein data packets are transmitted in an asynchronous manner alongside the clock-pulse signal, wherein the message is bit-wise subdivided in free positions between bits of the clock pulse signal, and wherein the clock pulse signal is recognizable as an alternating sequence of X and Y.