Patent ID: 8130228

Claim:
A system for processing multiple Low Density Parity Check (LDPC) codes to encode and decode data, the system comprising: a multitude of processing units for processing said multiple codes to encode and decode data, each of said codes being used by one of the processing units at a time to encode or decode data sequences having multiple data values; a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes, the data cache including: a plurality of input ports for receiving the LDPC codes from the processing units for storage in the data cache, and a plurality of output ports for sending the LDPC codes to the processing units for use by the processing units to encode and decode data sequences; an off-chip, external memory for storing the LDPC codes, and for transmitting the LDPC codes to and receiving the LDPC codes from the processing units; and a sequence processor for controlling the transmission of the LDPC codes between the processing units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence to encode and decode the data sequences.