Patent ID: 7546435

Claim:
A memory module, comprising: an insulative substrate; first and second pluralities of memory devices each having a plurality of terminals, each terminal of the memory devices of the first plurality corresponding to an identical memory device function as a correspondingly positioned terminal of the memory devices of the second plurality, the first plurality of memory devices being mounted to the insulative substrate having at least a portion of the terminals of the memory devices in the first plurality each interconnected to one of the terminals of one of the memory devices in the second plurality and having a different memory device function therefrom; and a memory access device mounted on the substrate, the memory access device having a plurality of terminals that are coupled to respective ones of the interconnected terminals, the memory access device being operable to receive external memory requests and to couple address and control signals to the interconnected terminals responsive to the memory requests, at least one of the address signals or at least one of the control signals being dynamically coupled to the interconnected terminals in a first configuration if the first plurality of memory devices are being accessed, and the at least one of the address signals or at least one of the control signals being dynamically coupled to the interconnected terminals in a second configuration that is different from the first configuration if the memory devices of the second plurality are being accessed, the memory access device comprising: a command queue that is operable to receive the memory requests, the memory queue further being operable to convert the memory requests into respective sets of command and address signals and to output the command and address signals in the order that the respective memory requests were received; a command scheduler coupled to the command queue to receive the command and address signals from the command queue, the command scheduler arranging the timing of the command and address signals; a micro command shifter coupled to receive the command and address signals from the command scheduler after the timing of the command and address signals have been arranged, the micro command shifter being operable to output the command and address signals in synchronism with the operation of the memory devices; and a multiplexer coupled to the micro command shifter to receive the command signals or the address signals from the micro command shifter, the multiplexer being operable to arrange the command or address signals in either the first configuration or the second configuration depending on whether the memory devices of the first or second plurality are being accessed, the multiplexer being operable to couple the command or address signals in either the first configuration or the second configuration to the interconnected terminals.