Patent ID: 8468483

Claim:
A method for performing a parameterized statistical static timing analysis, said method comprising: determining an interdependence between a setup time margin and a hold time margin of a circuit block in statistical parameterized form, said setup time margin comprising a first specific period of time immediately prior to arrival at said circuit block of an active edge of a clock signal input during which a data signal input at said circuit block must be stable, said hold time margin comprising a second specific period of time immediately after said arrival of said active edge during which said data signal input must continue to remain stable, and said determining considering variations in multiple parameters; performing, by a computer system, a parameterized statistical static timing analysis of a circuit comprising said circuit block; based on said parameterized statistical static timing analysis, determining, by said computer system and in statistical parameterized form, a setup time and a hold time for said circuit block in said circuit; based on said interdependence between said setup time margin and said hold time margin, formulating, by said computer system and in statistical parameterized form, a setup time constraint and a hold time constraint for said circuit block in said circuit; and, checking, by said computer system, said setup time and said hold time against said setup time constraint and said hold time constraint.