Patent ID: 8683093

Claim:
A host system comprising: a CPU; a host controller; a system memory configured to be accessed by the CPU and the host controller, the system memory configured to store data, a first descriptor, and a plurality of third and fourth descriptors; and a memory device which is connected to the host controller through an interface, wherein the host controller includes: a register set which is configured to control a command which is issued to the memory device; and a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors in the system memory, and is configured to transfer data between the system memory and the memory device according to the first, third, and fourth descriptors, said host controller is configured to load the first descriptor which includes a set of a plurality of pointers indicating the third descriptors, each of the third descriptors including information necessary to issue the command to the memory device, and information necessary for data transfer between the host controller and the memory device, each of the third descriptors is followed by each of the fourth descriptors, and each of the fourth descriptors including information necessary for data transfer between the host controller and the system memory, and the host controller is configured (1) to set contents of each of the third descriptors to the register set, and issues the command to the memory device, (2) to execute the DMA unit to transfer data between the system memory and the memory device via the host controller in accordance with contents of each of the third descriptors and each of the fourth descriptors, and (3) to repeat (1) and (2) for each third descriptor and fourth descriptor indicated by each pointer in the first descriptor, wherein the host controller is configured to generate an interrupt signal indicating all data transfer described in the first descriptor has been completed.