Patent ID: 8279669

Claim:
A semiconductor storage device, comprising: first and second memory cell each of which includes a charge accumulating layer and a control gate, and holds two or more-level data, the second memory cell being adjacent to the first memory cell; a bit line transferring the data to the first memory cell and the second memory cell; a first buffer which is connected to the bit line and holds write data to the first memory cell and the second memory cell; a second buffer which is connected to the bit line and holds read data from the first memory cell; and a controller which controls first writing and rewriting executed for the first memory cell connected to the bit line and second writing executed for the second memory cell, wherein the write data in the first buffer is updated each time a second write signal is given, the controller executes the first writing based on the write data held by the first buffer, thereafter reads the data from the first memory cell when receiving the second write signal allows the second buffer to hold the read data, thereafter performs the second writing based on the write data updated in the first buffer, and then executes the rewriting to correct threshold distribution of the first memory cell based on the read data held by the second buffer.