Patent ID: 7577825

Claim:
A method for processing micro-operations in a computer processor comprising: determining, by a hardware processor core of the computer processor, whether a condition related to validity of data in a hardware reorder buffer of an out-of-order subsystem of the processor core is met by tracking past speculative write-back indications followed by invalid data within a register alias table, wherein said tracking comprises receiving a signal from a data cache unit indicating the validity of a write-back operation for one of said speculative write-back indications and said tracking comprises receiving from a parallel sub-circuit an indication from a youngest cancelled finder of the most recent micro-operation that was dispatched for execution and cancelled; and processing a micro-operation received at a hardware reservation station in a fast mode or slow mode state that is set according to the determination such that in fast mode state the reservation station immediately considers to dispatch said micro-operation to execution and in slow mode state the reservation station waits for a valid indication from said reorder buffer prior to immediately considering to dispatch said micro-operation to execution.