Patent ID: 7392447

Claim:
A method of using scan chains and boundary scan for power saving, in a synchronous logic ASIC having scan chains and boundary scan circuits wherein a controller is embedded for letting org_s_mode, org_s_enable, org_bs_mode, org_bs_enable, power_off, clock and reset signals of the scan chains and boundary scan circuits to be inputted into the controller and generate a new set of control signals of s_mode, s_enable, bs_mode, bs_enable, pw_switch, scan_clock, bs_clock, mem_if to control the scan chains and boundary scan circuits, the method comprising: (a) during power-off of the synchronous logic ASIC: (1) letting a clock of the synchronous logic ASIC to be gated; (2) preserving a set of primary outputs of the synchronous logic ASIC in memory devices of the boundary scan circuits, then switching the inputs of an external circuits from the primary outputs to the memory devices of the boundary scan circuit; (3) shifting out current states of internal memory devices of the synchronous logic ASIC to an external memory by the scan chains circuits; (4) powering off the synchronous logic ASIC; (b) during power-on of the synchronous logic ASIC: (1) turning on the power and resetting the power-offed circuitry; (2) shifting the stored value in the external memory through the scan chains circuit back to the internal memory devices by the scan chains circuits; (3) switching the inputs of the external circuits from the memory devices of the boundary scan circuit to the primary outputs; (4)turning on the gated clock.