Patent ID: 7203087

Claim:
A memory device having a reading configuration and comprising: a plurality of memory cells, arranged in rows and columns, wherein memory cells arranged on the same column have respective first terminals connected to a same bit line and memory cells arranged on the same row have respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in said reading configuration, said column addressing circuit being configured to bias said addressed bit line corresponding to said selected memory cell substantially at said supply voltage in said reading configuration; and a row driving circuit configured to bias said addressed word line corresponding to said selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage lower than a phase change voltage, is applied between said first terminal and said second terminal of said selected memory cell in said reading configuration.