Patent ID: 8705289

Claim:
A flash memory apparatus, comprising: a plurality of memory cells, wherein each of the memory cells receiving a programming control voltage through a control end point, and executing data programming operation according to the programming control voltage; and a plurality of programming control voltage generators, coupled to the memory cells respectively, wherein each of the programming control voltage generator comprises: a pre-charge voltage transmitter, coupled to the control end point of each of the memory cells, providing a pre-charge voltage to the control end point of corresponding memory cell according to a pre-charge enable signal during a first period of time; and a pumping capacitor, coupled between the control end point of each of the memory cells and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the corresponding memory cell; and a plurality of erasing control voltage generators, respectively coupled to the memory cells, wherein each of the erasing control voltage generators comprises: an erasing pre-charge voltage transmitter, coupled to an erase end point of each of memory cells, transmitting an erasing pre-charge voltage to the erase end point of the corresponding memory cell according to an erasing pre-charge enable signal during a third period of time; and an erasing pumping capacitor, coupled between the erase end point of each of memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing.