Patent ID: 8212545

Claim:
A reference voltage circuit, comprising: an enhancement depletion (ED) type reference voltage circuit comprising: an N-channel depletion type metal oxide semiconductor (MOS) transistor comprising: a first N-channel depletion type MOS transistor having a source and a gate connected to an output terminal; and a second N-channel depletion type MOS transistor having a gate connected to the output terminal, and a source connected to a drain of the first N-channel depletion type MOS transistor, and an N-channel enhancement type MOS transistor comprising a drain and a gate connected to the output terminal, and a source connected to a ground (GND) terminal, and a cascode circuit disposed between a power supply terminal and the ED type reference voltage circuit, wherein the N-channel depletion type MOS transistor comprises a plurality of N-channel depletion type MOS transistors connected in series, and wherein the cascode circuit comprises an N-channel depletion type MOS transistor comprising a third N-channel depletion type MOS transistor having a drain connected to the power supply terminal, and a gate connected to the drain of the first N-channel depletion type MOS transistor and the source of the second N-channel depletion type MOS transistor.