Patent ID: 7445957

Claim:
A method of fabricating a wafer level semiconductor package with a build-up layer, which comprises: preparing a module board having a plurality of rigid frames with through holes, wherein the rigid frames are arranged in arrays; placing the module board into a receiver formed by a jig; placing at least a chip into each of the through holes such that the chip is carried on the jig and a predetermined space is formed between the chip and the corresponding rigid frame of the module board; filling a low-modulus buffer material in the predetermined space such that the chip and the corresponding rigid frame are separated by the low-modulus buffer material; separating the module board from the jig; forming the build-up layer on the module board and the chip such that the build-up layer is electrically connected to the chip and a plurality of conductive elements are electrically connected to the build-up layer; and forming the wafer level semiconductor package with the build-up layer by performing a singulation process.