Patent ID: 7276934

Claim:
An integrated circuit, comprising: a plurality of substantially similar programmable tiles, each tile comprising a logic block, segments of a plurality of interconnect lines interconnecting the programmable tiles one to another, and a plurality of programmable structures directly coupled to the segments of the interconnect lines, at least a subset of the programmable structures being further directly coupled to the logic block in each tile, the tiles being arranged in rows and columns, wherein: each of a first plurality of the interconnect lines is directly coupled to a first two of the programmable structures included in two tiles located in different columns and in different rows, each of the first two of the programmable structures further being directly coupled to at least one other interconnect line included in the first plurality of interconnect lines, and the first plurality of interconnect lines includes at least two interconnect lines directly coupled to two of the programmable structures included in two of the tiles that are separated from one another by J intervening rows and K intervening columns, wherein J and K are positive integers.