Patent ID: 7180349

Claim:
A resettable flip-flop circuit comprising: an input circuit for receiving a pair of input signals having complementary logic levels and for, in response to a first transition of clock signal, inverting the logic levels to yield complementary logic states at two complementary output terminals during an active phase of operation; an input latch circuit for latching the logic states of the complementary output terminals in response to a second transition of the clock signal during the active phase of operation, the input latch circuit including two cross-coupled transistors and two control transistors, the control transistors being connected in series between the cross-coupled transistors and an enable voltage and respectively configured to receive a reset signal and the clock signal; a reset circuit for driving the complementary output terminals to preset logic states in response to the second transition of the clock signal during a reset phase of operation; and a reset latch circuit for latching the preset logic states of the complementary output terminals in response to the first transition of the clock signal during the reset phase of operation.