Patent ID: 8514005

Claim:
A circuit for generating multiphase clock signals and corresponding indication signals, comprising: a multiphase clock generation circuit configured to receive an external clock signal having a first frequency, the multiphase clock generation circuit providing a plurality of first clock signals having a second frequency lower than the first frequency, phases of which differ from one another; a delay locked loop (DLL) circuit configured to receive the external clock signal, the DLL circuit providing a second clock signal having the first frequency, the second clock signal having rising edges which lead rising edges of the external clock signal; a timing circuit configured to receive the second clock signal and a comparison signal, the timing circuit providing a plurality of indication signals in response to the second clock signal and the comparison signal, each of the plurality of indication signals having rising edges which lead the rising edges of a corresponding one of the first clock signals; and a phase comparison circuit configured to receive one of the first clock signals and a corresponding one of the indication signals, the phase comparison circuit providing the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.