Patent ID: 7575990

Claim:
An etching method of forming a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit, comprising the steps of: performing a first etching to break through a cap dielectric layer; performing a main etching to etch a dielectric layer to form a hole in the core region and a trench in the peripheral region; performing an over etching to etch a silicon nitride (SiN) liner layer on the shoulder of sidewall spacers associated with the hole and with the trench without etching the SiN liner layer at the bottom area of the hole and the trench; performing an oxygen flushing to remove polymer residues; and performing a through etching to etch through the SiN liner layer that lines the bottom area of the hole and the trench, wherein said main etching and over etching have a high selectivity with respect to said dielectric layer and said sidewall spacers.