Patent ID: 7468902

Claim:
A static random access memory (SRAM) cell comprising: a first PMOS transistor having a source coupled to a supply voltage; a second PMOS transistor having a source coupled to the supply voltage, a drain coupled to a gate of the first PMOS transistor, and a gate coupled to a drain of the first PMOS transistor; a first write switch module coupled between the first PMOS transistor and a complementary supply voltage, wherein the first write switch module comprises a first NMOS transistor and a second NMOS transistor serially coupled between the drain of the first PMOS transistor and the complementary supply voltage, the first NMOS transistor having a gate being controlled by a write bit line; and the second NMOS transistor having a gate being controlled by a write word line; a second write switch module coupled between the second PMOS transistor and the complementary supply voltage; and a read switch module coupled between the gate of the first PMOS transistor and a read bit line, wherein the first write switch module, the second write switch module, and the read switch module are controlled separately to write or read a logic value to or from one or more storage nodes at the drains of the first and second PMOS transistors.