Patent ID: 8913437

Claim:
A system comprising: a read module configured to generate first information about a first memory cell located along a first bit line and a first word line of a memory array by reading memory cells along the first word line of the memory array, the memory cells including the first memory cell, wherein the first information indicates a location of a threshold voltage distribution of the first memory cell relative to a plurality of threshold voltages applied to the first word line to read the memory cells, and generate second information about a second memory cell by reading the second memory cell, wherein the second memory cell is located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line, wherein the second information indicates a state of the second memory cell causing interference to the first memory cell; and a compensation module configured to compensate for the interference using a log-likelihood ratio corresponding to (i) the first information and (ii) a distribution number corresponding to a threshold voltage distribution of the state of the second memory cell causing the interference to the first memory cell.