Patent ID: 7586175

Claim:
A semiconductor wafer, comprising: a plurality of chip regions formed on an active surface of the wafer and separated by scribe areas, each chip region comprising an active circuit region and a moisture barrier region (MOB), and a multi-layer interconnect structure including a first metallization layer and a second metallization layer; and an embedded interconnection structure formed as part of the first metallization layer to electrically couple two or more chip regions, wherein the embedded interconnection structure provides an electrical path to conduct bulk electroplating current to each of the electrically coupled chip regions including the MOBs and to feed said electroplating current to those regions of a metallic seed layer within, or in proximity to, each of the electrically coupled chip regions, to perform an electroplating process to form the second metallization layer, wherein each chip region further comprises a crack stop region, and wherein the embedded interconnection structure comprises a continuous conductive structure that connects the crack stop regions of each of the electrically coupled chip regions.