Patent ID: 8195892

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: a symmetric multiprocessing (SMP) system comprising: a plurality of nodes, each of the nodes comprising a node controller and a plurality of processors cross-coupled to one another; at least one cache directory coupled to each node controller, wherein the at least one cache directory comprises at least one of a local cache directory and a shared cache directory; and invalid state transition logic coupled to each node controller, the invalid state transition logic comprising program code enabled to: identify an invalid state transition for a cache line in a local node, based on a received state change notification from one of the plurality of processors of the corresponding node, the state change notification transmitted responsive to a state for the cache line being set to an invalid state; evict a corresponding cache directory entry, stored in the local node, for the cache line having the identified invalid state transition; and forward an invalid state transition notification to all the node controllers in the SMP system, to evict a corresponding cache directory entry stored in a home node for the cache line.