Patent ID: 6914313

Claim:
A complimentary metal oxide semiconductor CMOS) device, featuring a P channel metal oxide semiconductor (PMOS) component in a first region of a semiconductor substrate, and featuring an N channel metal oxide semiconductor (NMOS) component in a second region of said semiconductor substrate, comprising: a P well region located in a top portion of said second region of said semiconductor substrate, and an N well region located in a top portion of said first region of said semiconductor substrate; an insulator filled, shallow trench isolation region, located in a top portion of said semiconductor substrate between said P well region and said N well region; a recessed P well region located in the perimeter of said P well region, with a non-recessed P well portion of said semiconductor substrate located in the center of said P well region, surrounded by said recessed P well region; a recessed N well region located in the perimeter of said N well region, with a non-recessed N well portion of said semiconductor substrate located in the center of said N well region, surrounded by said recessed N well region; a heavily doped P type source/drain region, located in a top portion of said recessed N well region; a heavily doped N type source/drain region, located in a top portion of said recessed P well region; first metal silicide layers located in top portions of said heavily doped P type source/drain region, and second metal silicide layers located in top portions of said N type heavily doped source/drain region; a first metal oxide gate insulator layer located overlying the top surface of said non-recessed P well portion of said semiconductor substrate, and a second metal oxide gate insulator layer overlying the top surface of said non-recessed N well portion of said semiconductor substrate; vertical P type silicon spacers located on the sides of said non-recessed N well portion of said semiconductor substrate, and located on the sides of a bottom portion of said first metal oxide gate insulator layers; vertical N type silicon spacers located on the sides of said non-recessed P well portion of said semiconductor substrate, and located on the sides of a bottom portion of said second metal oxide gate insulator layer; conductive gate structures located overlying the metal oxide gate insulator layer; an interlevel dielectric (ILD) layer located overlying said conductive gate structures; contact hole openings in said ILD layer exposing top surface of said conductive gate structures, and exposing top surface of said heavily doped P type source/drain region, and of said heavily doped N type source/drain region; and metal structures located in said contact hole openings.