Patent ID: 8781054

Claim:
A semiconductor device comprising: a clock-and-data recovery circuit comprising: a phase tracking loop that generates a phase difference signal indicating a phase-lead or a phase-delay between a reception clock generated from a transmission clock and an input signal and makes a phase of the reception clock track a phase of the input signal; a frequency tracking loop that performs a control to make a frequency of the reception clock track a frequency of the input signal, the clock-and-data recovery circuit being configured to extract a data signal and a synchronization clock corresponding to the data signal from the input signal and to control a phase and a frequency of the reception clock; a phase detector that detects a phase difference between the reception clock and the input signal and updates a polarity value indicated by the phase difference signal; a first integrator that increases or decreases a first count value based on the phase difference signal, and when the first count value reaches a predetermined value, outputs a first up-signal and a first down-signal; a second integrator that increases or decreases a second count value based on the first up-signal and the first down-signal and outputs the second count value as a frequency difference signal; a pattern generator that generates a second up-signal and a second down-signal at a predetermined interval based on the frequency difference signal; a mixer that generates a phase selection signal based on the first up-signal and the first down-signal, and the second up-signal and second down-signal; and a phase interpolator that selects a phase by interpolating a phase of the transmission clock according to the phase selection signal and outputs a resultant clock as the synchronization clock; a frequency error adjuster that increases or decreases a value indicated by a frequency adjustment signal according to the frequency difference signal generated based on the phase difference signal in the frequency tracking loop; and an oscillator that increases or decreases a frequency of the transmission clock based on the value indicated by the frequency adjustment signal, wherein the phase tracking loop comprises the phase detector, the first integrator, the mixer, and the phase interpolator, and wherein the frequency tracking loop comprises the phase detector, the first integrator, the second integrator, the pattern generator, the mixer, and the phase interpolator.