Patent ID: 8464004

Claim:
An information processing apparatus comprising: a plurality of nodes, each comprising a main memory, a processor having a cache memory, and a controller that guarantees cache coherency among the nodes, each controller comprising: a first storage that stores address information corresponding to primary data that is present in the main memory of a local node and is cached in the local node; a second storage that stores the address information corresponding to the primary data if the primary data is not cached in any of the nodes other than the local node; a local snoop control unit that performs a local snoop control operation to guarantee cache coherency at the local node, when a memory access request is generated at the local node, and target data of the memory access request corresponds to the address information stored in at least one of the first and second storages; a global snoop control unit that performs a global snoop control operation to guarantee cache coherency among the nodes; and a request transmission/reception unit that broadcasts a memory access request to the local snoop control unit in response to receiving the memory access request generated at the local node, and broadcasts a global snoop request requesting to perform the global snoop control operation to the global snoop control unit in response to receiving the global snoop request from the local snoop control unit, wherein when the target data of the memory access request corresponds to the address information stored in neither the first storage nor the second storage, the local snoop control unit transmits the global snoop request to the request transmission/reception unit.