Patent ID: 8700840

Claim:
A nonvolatile memory, comprising: an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together; said array of memory cells being partitioned into a first group of blocks and a second group of blocks; a group of read/write circuits for reading or programming in parallel a corresponding page of memory cells among said array of memory cells; said first group of blocks having first-group pages of memory cells that are each once programmable in between erasure, and each of the memory cells in the first-group pages storing one or more bit of data; said second group of blocks having second-group pages of memory cells that are each multi-time programmable with a partial page of memory cells being once programmable each time, and each of the memory cells in the second-group page storing one bit of data; and a cache memory configured from said second group of blocks to cache data being written in granularity of one or more partial page of memory cells, said cache memory archiving selected data to said first group of blocks as a function of predefined attributes of the selected data and predefined states of said first group of blocks and said second group of blocks.