Patent ID: 7217621

Claim:
A process of fabricating a NAND flash memory cell array, comprising the steps of: forming an oxide layer on an active area in a silicon substrate, forming a first silicon layer on the oxide layer, forming a dielectric film on the first silicon layer, forming a second silicon layer on the dielectric film, etching away a portion of the second silicon layer to form a row of control gates with exposed side walls, forming an oxide on the side walls of the control gates, anisotropically etching away portions of the first silicon layer and the oxide layer beneath it using the oxide on the side walls of the control gates as a mask to form floating gates which are stacked beneath, self-aligned with and of greater lateral extent than the control gates, forming diffusions in the active area between alternate ones of the floating gates, forming a thermal oxide on the side walls of the floating gates and on the surface of the substrate between the floating gates, depositing a third silicon layer over the thermal oxide, removing portions of the third silicon layer to form erase gates above the diffusions and select gates between the floating gates where there are no diffusions and at two ends of the row, forming a bit line diffusion and a common source diffusion in the active area near the select gates at the ends of the rows, and forming a bit line above the row and a bit line contact which interconnects the bit line and the bit line diffusion.