Patent ID: 7545180

Claim:
A sense amplifier circuit comprising: a latch circuit having a first inverter circuit cross coupled to a second inverter circuit; a first discharge device operatively coupled to a first latch node of said first inverter circuit; a second discharge device operatively coupled to a second latch node of said second inverter circuit; a first PMOS transistor operatively coupled between said first discharge device and a bit line; a second PMOS transistor operatively coupled between said second discharge device and a complementary bit line; a first NMOS transistor operatively coupled between said first discharge device and a ground voltage; a second NMOS transistor operatively coupled between said second discharge device and the ground voltage; a pull down circuit operatively coupled between a common node of said latch circuit and the ground voltage; and a delay circuit operatively coupled among the first PMOS transistor, the second PMOS transistor and said pull down circuit for producing a delay between a first control signal and a second control signal.