Patent ID: 7029974

Claim:
A method of fabricating a split gate type nonvolatile semiconductor memory device, the method comprising: forming a gate insulating layer and a floating-gate conductive layer on a semiconductor substrate; forming a mask layer pattern on the floating-gate conductive layer to define a first opening extending in a first direction; forming first sacrificial spacers having a predetermined width on both sidewalls corresponding to the mask layer pattern; forming an inter-gate insulating layer on the floating-gate conductive layer exposed between the corresponding first sacrificial spacers; removing the first sacrificial spacers; etching the floating-gate conductive layer using the mask layer pattern and the inter-gate insulating layer as an etching mask, until the gate insulating layer is exposed; forming a tunneling insulating layer on an exposed portion of the floating-gate conductive layer; forming a control-gate conductive layer on a surface of the semiconductor substrate having the tunneling insulating layer and the inter-gate insulating layer; forming second sacrificial spacers having predetermined widths on the control-gate conductive layer on both sidewalls of the mask layer pattern within the first opening; forming a split control gate in the first opening, by etching the exposed control-gate conductive layer such that surfaces of the mask layer pattern and the inter-gate insulating layer are exposed, using the second sacrificial spacer as an etching mask; etching the remaining mask layer pattern and inter-gate insulating layer using the second sacrificial spacers and the split control gate as etching masks until the floating-gate conductive layer is exposed; and etching the exposed floating-gate conductive layer using the second sacrificial spacer, the control gate and the inter-gate insulating layer as the etching mask, to form a split floating gate in the first opening.