Patent ID: 8735238

Claim:
A method for forming both high-voltage and low-voltage transistors on a substrate, the method comprising: forming first and second high-voltage transistor wells and first and second low-voltage transistor wells in the substrate, wherein the first high voltage well, the second high voltage well, the first low voltage well, and the second low voltage well are respectively separated by isolation structures extending a first depth into the substrate; using a first implantation process to simultaneously implant a dopant of first conductivity type to a second depth in the substrate to form a channel region in the first low-voltage transistor well and a drain region in the first high-voltage transistor well; and using a second implantation process to simultaneously implant a dopant of second conductivity type to a third depth in the substrate to form a channel region in the second low-voltage transistor well and a drain region in the second high-voltage transistor well, wherein the second depth and the third depth are each less than the first depth.