Patent ID: 7102227

Claim:
A passive element chip comprising: a substrate; an insulating layer having a first surface and a second surface opposite to the first surface, wherein the insulating layer is formed on the substrate, and wherein the second surface of the insulating layer is faced to the substrate; an inductor formed in the insulating layer by a first metal wire; a first electrode formed on the first surface of the insulating layer wherein the first electrode is coupled to the inductor; a capacitor formed in the insulating layer by a second metal wire, wherein the capacitor is isolated from the inductor; a second electrode formed on the first surface of the insulating layer, wherein the second electrode is coupled to the capacitor; a protective film formed on the first surface of the insulating layer, wherein the protective film has a first opening for exposing the first electrode and a second opening for exposing the second electrode; a first wiring pattern formed within the first opening; and a second wiring pattern formed within the second opening.