Patent ID: 8008730

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: forming a first gate electrode and a second gate electrode over a semiconductor substrate having a main surface, said first and second gate electrodes being spaced apart from each other; forming a first interlayer insulating film in a region between the first gate electrode and the second gate electrode over the semiconductor substrate by at least one of a thermal chemical vapor deposition method and a coating method in such a manner that the first interlayer insulating film is at a higher level than those of the first gate electrode and the second gate electrode; forming a second interlayer insulating film over the first interlayer insulating film by a plasma chemical vapor deposition method; forming a first plug electrode through the second interlayer insulating film and the first interlayer insulating film, said first plug electrode being electrically coupled to the semiconductor substrate; forming a third interlayer insulating film having a predetermined dielectric constant over the second interlayer insulating film by the plasma chemical vapor deposition method so as to cover the first plug electrode, a bottom portion of the third interlayer insulating film connecting to a top portion of the second interlayer insulating film; forming a wiring trench for exposing the second interlayer insulating film and the first plug electrode by etching the third interlayer insulating film; and electrically coupling a wiring to the semiconductor substrate via the first plug electrode by forming the wiring in the wiring trench, wherein in the step of forming the third interlayer insulating film, a silicon oxide carbide (SiOC) film or a silicon oxide fluoride (SiOF) film is formed as the third interlayer insulating film.