Patent ID: 8263452

Claim:
A method for manufacturing a semiconductor device having an nMIS transistor and a pMIS transistor, comprising: forming a p-type semiconductor region and an n-type semiconductor region in a surface of a substrate; forming a first gate insulating film on the p-type semiconductor region and forming a second gate insulating film on the n-type semiconductor region; forming a first metallic film made of a metal material above the second gate insulating film and forming a laminated structure of a second metallic film made of a material having a higher electronegativity than the metal material and a third metallic film made of the metal material above the first gate insulating film; performing heat treatment to form a mixed film obtained by mixing the second metallic film and a part of the third metallic film in such a manner that the mixed film comes into contact with the first gate insulating film; processing the first metallic film, the third metallic film and the mixed film to have a gate pattern to form a gate electrode for the nMIS transistor above the p-type semiconductor region and form a gate electrode for the pMIS transistor above the n-type semiconductor region, wherein a film thickness of the mixed film is one monolayer or more and 3 nm or less, and an average electronegativity of the metal material is smaller than an average electronegativity of the mixed film by 0.1 or more.