Patent ID: 8536562

Claim:
A method of forming a plurality of memory structures, comprising: forming a line of electrically insulative material over a base; the line having a first sidewall in opposing relation to a second sidewall; the base having a plurality of spaced-apart electrical contact regions along an upper surface; the first sidewall being directly over an upper surface of a first electrical contact region and the second sidewall being directly over a second electrical contact region; depositing electrode material over the line and along the sidewalls; patterning the electrode material to form a first electrode along the first sidewall and to form a second electrode along the second sidewall; the first and second electrodes being electrically coupled with the first and second electrical contact regions, respectively; forming programmable material over the first and second electrodes; and forming a top electrode over the programmable material; a first memory cell comprising the first electrode together with the programmable material and the top electrode, and a second memory cell comprising the second electrode together with the programmable material and the top electrode; the programmable material within the first and second memory cells being a continuous strap across the first and second electrodes.