Patent ID: 7928880

Claim:
A digital analog converter comprising: an input terminal receiving a digital input signal; a lower-side capacitor group of capacitors having capacitance values weighted by a binary rate and coupled to a lower-side common terminal in parallel; an upper-side capacitor group of capacitors having capacitance values weighted by a binary rate and coupled, in parallel, to an upper-side common terminal at which an analog output signal is generated; a coupling capacitor provided between the lower-side common terminal and the upper-side common terminal; a switch group of switches coupled to terminals of the lower-side capacitor group at opposite sides to the lower-side common terminal and coupled to terminals of the upper-side capacitor group at opposite sides to the upper-side common terminal, the switch group being controlled as a conduction state and a non-conduction state in accordance with the digital input signal; and an adjusting capacitor coupled to the lower-side common terminal and having a variable capacitance value, wherein the capacitance value of the adjusting capacitor is adjusted so that a first potential and a second potential are equal to each other, the first potential being defined as a potential of the upper-side common terminal when upper-side bits of the digital input signal are set to a first upper-side bit value and lower-side bits of the digital input signal are set to a first lower-side bit value at which the values of all the bits of the lower-side bits are equal to 0 or 1, and the second potential being defined as a potential of the upper-side common terminal when the upper-side bits of the digital input signal are set to a second upper-side bit value which is different from the first upper-side bit value by only the minimum bit, and the lower-side bits of the digital input signal are set to a second lower-side bit value at which the values of all the bits of the lower-side bits are equal to 1 or 0.