Patent ID: 7606059

Claim:
A programmable resistance memory device comprising: a semiconductor substrate; at least one cell array, formed above said semiconductor substrate, which comprises a plurality of bit lines arranged in parallel with each other, a plurality of word lines arranged in parallel with each other in such a direction as crossing said bit lines, and memory cells connected between the bit lines and the word lines at cross portions of the bit lines and the word lines, each said memory cell having a stack structure of a programmable resistance element and an access element, said programmable resistance element and an access element, said programmable resistance element being applied a voltage greater than a certain threshold to develop a high resistance state or a low resistance state and storing the high resistance state or the low resistance state in a non-volatile manner, said access element having a resistance value in an off-state that is ten times or more as high as that in a select state; and a read/write circuit formed on said semiconductor substrate as underlying said cell array and connected to the bit lines and word lines through vertical wirings for data reading and data writing in communication with said cell array.