Patent ID: 8703510

Claim:
A method for manufacturing an array substrate, comprising: forming a gate line, a gate electrode, a data line, an active layer with a channel, a source electrode, a drain electrode, a pixel electrode and an active layer with a channel on a base substrate, wherein the procedure for forming the data line, the active layer with the channel, the source electrode, the drain electrode and the pixel electrode comprising: forming an active layer thin film and a data line metal thin film; applying a photoresist on the data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern including a third thickness region, a second thickness region and a first thickness region whose thicknesses are successively increased, the third thickness region at least corresponding to the pixel electrode, the second thickness region corresponding to the data line, the active layer, the source electrode and the drain electrode; etching the data line metal thin film and the active layer thin film corresponding to the third thickness region; ashing and removing parts of the thickness of the photoresist so that the photoresist in the second thickness region is totally removed and the photoresist in the first thickness region at least partly remains; forming a transparent conductive thin film on the base substrate with a remaining photoresist in the first thickness region thereon; lifting off the remaining photoresist and the transparent conductive thin film formed thereon; etching the exposed data line metal thin film and etching parts of the subsequently exposed active layer thin film; and etching the remaining and exposed active layer thin film other than the channel by a patterning process so as to form the data line, the source electrode, the drain electrode, the pixel electrode and the active layer with the channel.