Patent ID: 7274602

Claim:
A storage device comprising: a memory cell array; a boosted-voltage supplying section which supplies a bias voltage to the memory cell array, the bias voltage being generated by boosting an input voltage; and a voltage regulating section which regulates a set voltage wherein the voltage regulating section sets a voltage value of the bias voltage in response to at least any one of a position in the memory cell array which is to be supplied with the bias voltage, and/or a number of times that the bias voltage is applied to the memory cell array, and a verify operation after application of the bias voltage which outputs a regulated voltage regulated in response to at least one of the set voltage and the bias voltage, wherein the boosted-voltage supplying section comprises: an error-amplification circuit which amplifies an error voltage with a value deviated from the set voltage of the bias voltage in response to the set voltage and/or the regulated voltage after regulation thereof; an inductance circuit coupled between the input voltage and a first node; a first switch circuit coupled between the first node and a reference voltage; and a rectifier circuit coupled between the first node and the memory cell array, the rectifier circuit being energized in a direction from the first node to the memory cell array, wherein the first switch circuit, or the first switch circuit and the rectifier circuit is periodically energized in response to operation of the error-amplification circuit.