Patent ID: 6975142

Claim:
A semiconductor device comprising: a first thin film transistor having a first impurity region electrically connected to a first power source; a second thin film transistor having a first impurity region electrically connected to a second power source; a third thin film transistor having a first impurity region electrically connected to the first power source; a fourth thin film transistor having a first impurity region electrically connected to the second power source, wherein: the first to fourth thin film transistors have a same conductivity type; a second impurity region of the first thin film transistor and a second impurity region of the second thin film transistor are electrically connected to one terminal of a capacitance; a second impurity region of the third thin film transistor, a second impurity region of the fourth thin film transistor, and a gate electrode of the first thin film transistor are electrically connected to the other terminal of the capacitance; a gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are electrically connected to a first input signal line; and a gate electrode of the third thin film transistor is electrically connected to a second input signal line.