Patent ID: 7932133

Claim:
A method for protecting an electrical circuit load from a high energy pulse including steps connecting a polymeric positive temperature coefficient (PPTC) resistive element in series with the electrical circuit load and an energy source; connecting a reverse breakdown overvoltage energy pulse absorbing semiconductor device as a shunt element between the electrical circuit load and the PPTC resistive element, said semiconductor device having a heat transfer surface sized in relation to, and in direct thermal contact with, the PPTC resistive element; forming the semiconductor device by steps including: (a) forming a planar substrate of semiconductor material having carriers of a first type of conductivity in a first predetermined concentration level, a first major face and a second major face opposite to said first major face, the carriers comprising a negative carrier, n-type doping material to have a doping concentration of approximately at least 10 20 n-type dopant ions/cm 3 ; (b) forming an epitaxial layer on said substrate with a negative carrier, n-type doping material having a doping concentration of approximately 5×10 17 dopant ions/cm 3 ; (c) forming at least one region at said first major face and having carriers of a second type of conductivity in a second predetermined concentration level, the at least one region having a positive carrier, p-type doping material having a doping concentration in a range between 10 20 and 10 15 dopant ions/cm 3 ; (a) forming at least one cell at said first major face and having carriers of said second type of conductivity in a third concentration level greater than said second concentration level, the at least one cell having a positive carrier, p-type doping material having a doping concentration in a range between 5×10 21 and 10 15 dopant ions/cm 3 ; (b) forming a first electrode layer at said first major face; (f) forming a second electrode layer formed at said second major face; and, (g) forming one of said first electrode layer and said second electrode layer comprising the heat transfer surface of the semiconductor device; receiving the high energy electrical pulse from the energy source into the semiconductor device thereby causing the at least one cell to become a first-level unidirectional conduction region for generating heat and transferring heat to the at least one region and thereupon causing the at least one region to become a second-level bi-directional intrinsic conduction and heat generating region; and transferring the heat from the first-level unidirectional conduction region and from the intrinsic conduction and heat generating region to the PPTC resistive element via the heat transfer surface, thereby accelerating trip of the PPTC resistive element to a high resistance state and disconnecting the electrical circuit load and the semiconductor device from the energy source.