Patent ID: 7830159

Claim:
A method for calibrating a capacitor mismatch error between a sampling capacitor and a feedback capacitor in a switched capacitor circuit, the method comprising: providing the sampling capacitor having a first plate coupled to sample an analog input voltage and a second plate coupled to a first input terminal of an amplifier; providing the feedback capacitor having a first plate coupled to the first input terminal of the amplifier, and a second plate switchably connected to an output terminal of an amplifier and further switchably connected to a ground voltage; sampling a fixed input voltage onto the sampling capacitor during a sampling phase of the switched capacitor circuit; placing the switched capacitor circuit in a hold/amplification phase of the switched capacitor circuit; providing a pair of level shift voltages alternately to the first plate of the sampling capacitor; generating a pair of output voltages at the output terminal of the amplifier, the pair of output voltages being a function of the sampled fixed input voltage, amplified by the amplifier and level shifted by the pair of level shift voltages, the pair of output voltages resembling output voltages in normal operation of the switched capacitor circuit; and comparing the pair of output voltages with respective corresponding ideal output voltages values to determine the capacitor mismatch error.