Patent ID: 7519928

Claim:
A method, in a data processing system, for modeling a circuit, comprising: providing a constant data structure identifying constant values for a plurality of stages of operation of at least one element in a net of a circuit design, wherein the constant data structure associates individual constant values to oscillating signals of the net for individual stages of a static analysis of the net; performing static analysis of the net by propagating the constant values through the net in multiple stages based on the constant data structure; and outputting results of the propagation of the constant values through the net for the multiple stages, wherein the results are indicative of valid or invalid operation of the net, wherein: the at least one element in the net of the circuit design comprises at least one sequential element, a number of stages of the static analysis is determined based on periods of a plurality of oscillating input signals to the net, and wherein the number of stages is a least common denominator number of stages determined based on the periods of the plurality of oscillating input signals, the static analysis of the net in a first stage of the multiple stages is performed based on results of the static analysis of the net in a second stage of the multiple stages that is previous to the first stage, and the propagation of the constant values through the net for the multiple stages does not model the delay timing of the elements of the net.