Patent ID: 7945867

Claim:
A method, comprising: providing a nanometric circuit architecture that includes a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above said succession of nanowires, an insulating layer; exposing a succession of exposed portions of said nanowires, one for each nanowire, by opening, in said insulating layer, a window of nanometric width b extended along a direction inclined by an angle α with respect to the direction x of the nanowires so as to substantially cross the whole succession of nanowires; realizing, above said insulating layer, a plurality of conductive dies extended along a direction y substantially orthogonal to said direction x, each of said dies overlapping in correspondence with said window onto a respective one of said exposed portions of said nanowires; and forming a plurality of contacts to couple said exposed portions of said nanowires with the conductive dies, respectively.