Patent ID: 7272526

Claim:
An apparatus for measuring the time delay between first and second phase-shifted clock signal edges, comprising: a multi-phase clock generator, said multi-phase clock generator operable to output the first and second phase-shifted clock signal edges; target and delay signal paths; a switch in communication with said multi-phase clock generator, said switch operable to alternately provide the first phase-shifted clock signal edge and said second phase-shifted clock signal edge to said target and delay signal paths, respectively; a variable delay module in said delay signal path, said variable delay module having a delay bias input; and said variable delay module further comprising: a single period delay circuit; and a variable delay cell coupled to said single period delay circuit, said delay cell having said delay bias input and said bias input signal corresponding to a variable time delay between said first and second phase-shifted clock signal edges; and a phase detector having respective inputs coupled to said target and delay signal paths; wherein said variable delay module is operable to delay said second phase-shifted clock signal edge on said delay path so that a bias input signal presented to said delay bias input, when a bias input signal is present, corresponds to the time delay between said second phase-shifted clock signal edge and said first phase-delayed clock signal edge on said target signal path.