Patent ID: 7130968

Claim:
A method of processing a memory read request from a central processing unit (CPU) of a microprocessor, the method comprising: retrieving, into the microprocessor, a cache tag associated with the memory read request from a cache memory bank that is external to the microprocessor, wherein the cache memory bank stores cache tags and cache data in separate memory locations; within the microprocessor, comparing the cache tag to a memory address associated with the memory read request to assess whether data requested by the CPU resides within the cache memory bank; and subsequent to retrieving the cache tag from the cache memory bank into the microprocessor, retrieving the cache data associated with the memory read request from the cache memory bank into the microprocessor, whereby the retrieval of the cache data into the microprocessor does not overlap in time with the retrieval of the cache tag into the microprocessor; wherein the cache tag and the cache data are retrieved in sequence from the cache memory bank over a common set of bus lines that connect the microprocessor to the cache memory bank, such that at least one bus line of the common set of bus lines is used to retrieve both the cache tag and the cache data.