Patent ID: 7219281

Claim:
A boundary scan test circuit comprising: first and second multiplexers for receiving a shift/capture control signal at a control node of each of the first and second multiplexers, and for receiving first and second input signals, respectively; first and second capture registers coupled to outputs of the first and second multiplexers, respectively; first and second update registers coupled to outputs of the first and second capture registers, respectively; third and fourth multiplexers coupled to outputs of the first and second update registers, respectively, for receiving a mode control signal at a control node of each of the third and fourth mulitplexers; a buffer section coupled to outputs of the third and fourth multiplexers and to a pad for receiving an input/output signal; and a first four-input multiplexer receiving the mode control signal at a control node of the first four-input multiplexer and having at least one input coupled to an input of the first multiplexer and at least one input coupled to an input of the third multiplexer.