Patent ID: 8060800

Claim:
An evaluation circuit for detecting and/or locating faulty data words in a data stream T n comprising: a first linear automaton circuit and a second linear automaton circuit connected in parallel, each having a set of states, wherein the first linear automaton circuit and the second linear automaton circuit each have inputs that are commonly connected for receiving a data stream T n comprising n successive data words y(1), . . . , y(n) each having a width of k bits, k>1, wherein the first linear automaton circuit can be described by the following equation z ( t+ 1)= Az ( t )âŠ• y ( t ) wherein the second linear automaton circuit can be described by the following equation z ( t+ 1)= Bz ( t )âŠ• y ( t ) where z represents state vectors and A and B represent the state matrices of the linear automaton circuits, where the state matrices A and B can be inverted, and where a dimension L of the state vectors z is â‰§k, wherein Aâ‰ B, the first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, is calculated of each data word of the n successive data words y(1), . . . , y(n), L first logic combination gates arranged downstream of the first linear automaton circuit and also L second logic combination gates arranged downstream of the second linear automaton circuit, the logic combination gates are designed such that the signature respectively calculated by the linear automaton circuit can be compared with a predeterminable good signature and a comparison value can be output.