Patent ID: 7068714

Claim:
A channel equalizer comprising: an equalizer filter for correcting an error upon receipt of a signal transmitted by a sending end; a decision-directed (DD) slicer for calculating a first error upon receipt of the corrected signal from the equalizer filter; a Sato slicer for calculating a second error upon receipt of the corrected signal from the equalizer filter; a DD error size calculation unit for taking the absolute value of a real part and an imaginary part of the first error calculated from the DD slicer, and summing the absolute value of the real part and the absolute value of the imaginary part of the first error to obtain a sum; a first multiplier to multiple the second error output from the Sato slicer by a first scale constant; and a second multiplier to multiply a resultant output of the first multiplier by the sum output from the DD error size calculation unit.