Patent ID: 7210016

Claim:
A system comprising: a first memory device and a second memory device; a first signal line coupled to the first memory device, the first signal line to provide first data, associated with a write command, to the first memory device; a second signal line coupled to the second memory device, the second signal line to provide second data, associated with the write command, to the second memory device; a control signal path coupled to the first memory device and the second memory device such that the write command propagating on the control signal path propagates past the first memory device before reaching the second memory device, and such that a first propagation time required for the write command to propagate on the control signal path from the memory controller to the first memory device is different than a second propagation time required for the write command to propagate on the control signal path from the memory controller to the second memory device; and a memory controller including: a first circuit to delay transmission of the first data to the first memory device by a first time interval that is based, at least in part, on the first propagation time; and a second circuit to delay transmission of the second data to the second memory device by a second time interval that is based, at least in part, on the second propagation time.