Patent ID: 8862963

Claim:
A nonvolatile memory comprising: a nonvolatile memory cell device configured to include at least a nonvolatile memory cell array accessible in units of a word, wherein the nonvolatile memory cell array is accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path configured to be used to access the nonvolatile memory cell array in said first access mode, wherein the first access path comprises: a first error correction code (ECC) processing part for performing error detection and correction using an ECC on a first data output from said nonvolatile memory cell array in said first access mode; and a second access path configured to be used to access the nonvolatile memory cell array in said second access mode, wherein the second access path comprises: a second ECC processing part for performing error detection and correction using the ECC on a second data output from said nonvolatile memory cell array in said second access mode.