Patent ID: 8278695

Claim:
A nonvolatile semiconductor memory device comprising: a substrate; and a plurality of memory strings arranged in a matrix shape in a row direction and a column direction, each of said plurality of memory strings comprising: a first selection transistor comprising: a first pillar shaped semiconductor formed perpendicular to said substrate; a first gate insulating film formed around said first pillar shaped semiconductor; and a first gate electrode formed around said first gate insulating film; and a plurality of memory cells comprising: a second pillar shaped semiconductor formed on said first pillar shaped semiconductor, the diameter of said first pillar shaped semiconductor being larger than the diameter of said second pillar shaped semiconductor at the part where said second pillar shaped semiconductor is connected to said first pillar shaped semiconductor; a first insulating film formed around said second pillar shaped semiconductor; a charge storage layer formed around said first insulating film; a second insulating film formed around said charge storage layer; first to nth electrodes formed around said second insulating film (n is a natural number not less than 2), said first to nth electrodes being plate shaped; and a plurality of third insulating films being plate shaped; and, a second selection transistor comprising: a third pillar shaped semiconductor formed on said second pillar shaped semiconductor; a second gate insulating film formed around said third pillar shaped semiconductor; and a second gate electrode formed around said second gate insulating film, wherein said first to nth electrodes of a first memory string which is one of said plurality of memory strings are shared as first to nth conductor layers spread in two dimensions between each of a second memory string adjacent to said first memory string in said column direction and a third memory string adjacent to said first memory string in said row direction; each of said first to nth electrodes and each of said plurality of third insulating films are vertically alternately stacked; edges of said first to nth electrodes and edges of said plurality of third insulating films are formed in a stepwise shape; and said plurality of memory cells are arranged in said first to nth electrodes and in said plurality of third insulating films with an array shape.