Patent ID: 8582665

Claim:
An image processing circuit, for receiving source image data and performing motion estimation/compensation to generate an interpolated image between two successive images, comprising: a compression circuit, for receiving source image data, and compressing the received source image data to generate a compressed image data comprising a plurality of line pixels and to generate residual image data comprising a plurality of residual line pixels, wherein the residual image data comprises a selected number of least significant bits of a word representing a given line pixel; a plurality of first line buffers, coupled to the compression circuit, for buffering the line pixels; a decompression circuit, coupled to the first line buffers, for decompressing the line pixels to generate a decompressed image data; a motion estimation/compensation circuit, coupled to the decompression circuit, for performing motion estimation/compensation to calculate motion vectors and then generate an interpolated image between the preceding and following images for frame rate up-conversion according to the decompressed image data; a plurality of second line buffers, coupled to the decompression circuit, for sequentially receiving and buffering the residual image data; and a processing circuit, coupled to the decompression circuit and the second line buffers, for adjusting the decompressed image data according to the residual image data.