Patent ID: 8779522

Claim:
A semiconductor device comprising a first MISFET and a second MISFET having a gate insulating film, a gate electrode, a sidewall, a source region, and a drain region, and further having a channel formation region in which a channel is formed during its operation over a semiconductor substrate under the gate electrode via the gate insulating film, wherein the semiconductor device further include a multilayer insulating film formed so as to cover the first MISFET and the second MISFET over the semiconductor substrate including a first region between the gate electrode of the first MISFET and the gate electrode of the second MISFET, an interlayer insulating film formed over the multilayer insulating film and having the film thickness greater than that of the multilayer insulating film, and a plurality of plugs formed in the interlayer insulating film and in the multilayer insulating film and being coupled to the source region and the drain region of the first MISFET and the second MISFET, wherein the multilayer insulating film includes a first insulating film and a second insulating film having a film thickness greater than that of the first insulating film, wherein the first and second insulating films are formed of the same material, and wherein the interlayer insulating film and the first and second insulating films are formed of a different material.