Patent ID: 8423919

Claim:
A semiconductor integrated circuit apparatus, comprising: a spare logic gate comprising a first control input and multiple data inputs; a plurality of photographic masks, each correlated to one of a plurality of metal layers of the semiconductor integrated circuit; and wherein only one metal layer is to be modified of the plurality of metal layers; wherein a single photolithographic mask of the plurality of photographic masks is correlated to the one and only one metal layer to be modified, a and the one and only one metal layer to be modified is configured to be modified to: connect a node of a target logic circuit to the first control input; and connect at least one of the data inputs to a supply voltage, wherein no other metal layer other than the one and only one metal layer is configured to be modified to: connect the node of the target logic circuit to the first control input; and connect the at least one of the data inputs to the supply voltage, wherein the modification of the single photolithographic mask either removes or inserts from the one and only one metal layer a connection between one of the via layers and the first control input of the spare logic gate, wherein all other masks of the plurality of photographic masks associated with the plurality of metal layers do not have a removal or an insertion from any of the other of the plurality of metal layers, a connection between one of the via layers and the first control input of the spare logic gate, as a modification, wherein one of a plurality of alternative logic circuits are selected, by the removal or insertion of a connection from the one and only one metal layer correlated to the single photographic mask.