Patent ID: 8869082

Claim:
A method for checking a circuit path of a circuit for adherence to set-up and hold times, the method comprising: determining minimum and maximum set-up and hold times from a plurality of set-up and hold times for the circuit path with respect to predefined failure criteria, wherein the determining minimum and maximum set-up and hold times is performed by data processing equipment; designating the timing behavior of the circuit path as being defective if a set-up timing infringement exists using the minimum set-up time or a hold timing infringement exists using the minimum hold time; and if neither the set-up timing infringement exists using the minimum set-up time or the hold timing infringement exists using the minimum hold time, designating the timing behavior of the circuit path as being correct if no timing infringement exists using a set-up time between the minimum and maximum set-up times and using a hold time between the minimum and maximum hold times; selecting a first pair of the maximum set-up time and the minimum hold time and a second pair of the minimum set-up time and the maximum hold time; determining whether set-up and hold timing infringement in the circuit path exists using the first pair and using the second pair, respectively; if set-up or hold timing infringement exists using the first or second pair: decreasing the set-up time if set-up timing infringement exists using the first pair to the larger of: a set-up time at which no timing infringement exists or the minimum set-up time, decreasing the hold time if hold timing infringement exists using the second pair to the larger of: a hold time at which no timing infringement exists or the minimum hold time, selecting the set-up time decreased to plus a first small amount as a set-up time to use for the circuit path if no set-up timing infringement exists as the set-up time has decreased and selecting the hold time decreased to plus a second small amount as a hold time to use for the circuit path if no hold timing infringement exists as the hold time has decreased, and designating the timing behavior of the circuit path as being correct if no timing infringement exists using either the first or second pair of set-up and hold times.