Patent ID: 8555001

Claim:
A cache memory, comprising: a plurality of MSHRs (Miss Status/Information Holding Registers) which are used when a memory access turns out to be a cache miss; a memory access identification unit which identifies a given memory access so that an identifier is attached to the given memory access; a memory access-MSHR correspondence table which stores, for each identifier of a memory access, a correspondence between the memory access and at least one of the MSHRs; a memory access association unit which associates the given memory access with at least one of the MSHRs by referring to the memory access-MSHR correspondence table; and an unused MSHR determination unit which determines an MSHR to be assigned to the given memory access in such a way that an unused one of at least one of the MSHRs which are associated with the given memory access is assigned to the given memory access.