Patent ID: 8395220

Claim:
A static random access memory (SRAM) cell, comprising: at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer, wherein each pass gate comprises: one or more device layers each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the pass gate device layers are doped with at least one n-type dopant; a gate common to each of the pass gate device layers surrounding the nanowire channels, wherein each inverter comprises: a plurality of device layers each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the inverter device layers are doped with at least one n-type dopant and the source and drain regions of one or more other of the inverter device layers are doped with at least one p-type dopant; and a gate common to each of the inverter device layers surrounding the nanowire channels.