Patent ID: 7653072

Claim:
A packet buffering unit for a packet switched system comprising: a packet receive unit for receiving packets from the network and for splitting these packets into Packet Data Units (PDUs); a plurality of memory banks coupled to said packet receive unit; a memory controller coupled to said packet receive unit and said plurality of memory banks for storing at least some of the PDUs of a packet over the memory banks; a packet management unit coupled to said packet receive unit for retrieving PDUs stored in the memory banks; and transmission queue memory means coupled to said packet management unit for at least temporarily storing the retrieved PDUs in the sequence they are to be transmitted; wherein the plurality of memory banks includes n memory banks partitioned into s number of memory sections, each memory section comprising memory space from each memory bank, and the memory controller stores PDUs in each section in accordance with i′=(i+k)Mod n, where n is the number of memory banks, k is the number of PDUs in a current packet, i is the section in which the current packet is stored, and i′ is the section for PDUs of the next packet.