Patent ID: 6881616

Claim:
A method of fabricating a semiconductor transistor comprising the steps of: providing a gate structure having a sidewall portion and a top portion, said gate structure formed on a substrate; forming a dielectric spacer formed over the substrate, said dielectric spacer forming an L-shape comprising a vertical portion parallel to the sidewall portion, and a horizontal portion approximately orthogonal to the sidewall portion of the gate structure; forming a source/drain extension using a first implantation step, forming a first source/drain region in the substrate during a source/drain implant using an implant species in a second implantation step of indium, wherein the first source/drain region formed underneath the horizontal portion of the L-shaped dielectric spacer; and forming a second source/drain region in the substrate during the source/drain implant using the implant species, wherein the second source/drain region is immediately adjacent the first source/drain region and has a depth greater than a depth of the first source/drain region.