Patent ID: 6839813

Claim:
A method of operating a digital system having a processor and associated translation lookaside buffer (TLB), comprising the steps of: executing a plurality of program tasks within the processor; initiating a plurality of memory access requests in response to the plurality of program tasks; caching a plurality of translated memory addresses in the TLB responsive to the plurality of memory access requests; incorporating a task identification value with each translated memory address to indicate which of the plurality of program tasks requested the respective translated memory address; incorporating a shared indicator with each translated memory address to indicate when a translated memory address is shared by more than one of the plurality of program tasks; invalidating a portion of the plurality of translated memory address in the TLB in a manner that is qualified by the shared indicator in response to an invalidate TLB entry command issued from the processor; said invalidate TLB entry command comprises an invalidate shared TLB entry command; and the step of invalidating in response to an invalidate shared TLB entry command comprises invalidating a translated memory address in the TLB only if the corresponding shared indicator indicates the translated memory address is shared by more than one of the plurality of program tasks.