Patent ID: 6977439

Claim:
A semiconductor chip stack structure comprising: a substrate including a die-mounting surface and wiring patterns adjacent the die-mounting surface; a first semiconductor chip attached to the die-mounting surface and including first electrode pads on a top surface thereof; first conductive bumps formed on the first electrode pads; first bonding wires electrically interconnecting the substrate and the first conductive bumps, the first bonding wires having an expanse substantially parallel with the top surface of the first chip; and a second semiconductor chip stacked over the first chip using the expanse of the first bonding wires, the second semiconductor chip including second electrode pads on a top surface thereof and being electrically connected to the wiring patterns, the second chip including an insulating adhesive layer on a bottom surface thereof, wherein the second chip including the insulating adhesive layer is in direct contact with the expanse, wherein at least one of the first bonding wires contacts a portion of the insulating adhesive layer, the portion directly overlying a corresponding one of the first conductive bumps, and wherein the at least one of the first bonding wires is supported by the corresponding one of the conductive bumps.