Patent ID: 6868530

Claim:
A method for fabricating an integrated semiconductor circuit, which comprises the steps of: using a computer program to define a circuit diagram by the steps of; defining surface cells for different subcircuits in the integrated semiconductor circuit; stipulating a circuit-specific uniform cell height by selecting from a set of the subcircuits having the surface cells for which a uniform cell height has been determined, the subcircuits needed for constructing the integrated semiconductor circuit and defining a least possible cell height of adequate size for all of the subcircuits selected as the circuit-specific uniform cell height for the surface cells in all the subcircuits selected; disposing the surface cells selected in one plane; computing interconnect paths between the surface cells selected; and computing the circuit diagram from the surface cells selected and having the circuit-specific cell height; fabricating the integrated semiconductor circuit on a basis of the circuit diagram; defining a first doped well and a second doped well having an opposite doping to the first doped well in the circuit diagram for each of the subcircuits disposed in a surface cell, the first doped well and the second doped well in each of the surface cells being distanced from one another until the surface cells reach a height corresponding to the circuit-specific uniform cell height; and defining a line of intersection defined between the first doped well and the second doped well in a subcircuit in the circuit diagram, and from the line of intersection the second doped well being shifted in a direction of increasing cell height.