Patent ID: 6839016

Claim:
A pipeline AD-converter comprising a cascade of AD-converter stages (ST), each having an analog input (A), a digital output (D) and a synchronous ΣΔ modulator (SM) with an input coupled to said analog input and an output coupled to said digital output of the stage, each AD-converter stage of the cascade, except the last one, further comprising an error signal generator (EG) for generating a baseband error signal from the signal applied to said analog input and the signal derived from said digital output and for applying the baseband error signal to the analog input of the next AD-converter stage in the cascade, the pipeline AD-converter further comprising a digital signal reconstruction path (R) receiving the digital outputs of the AD-converter stages (ST) and generating there from an error-reduced digital representation of the analog signal applied to the analog input (A 1 ) of the first stage in the cascade, characterized in that said error signal generator (EG) comprises an asynchronous ΣΔ modulator (AM) having an input connected to the analog input (A) of the AD-converter stage, means (S) for subtracting the signals from the outputs of the synchronous and the asynchronous ΣΔ modulators and means (F) for low pass filtering the result of the subtraction and for applying the filtered signal as error signal to the analog input of the next AD-converter stage in the cascade.