Patent ID: 7795907

Claim:
A majority gate having three inputs and an output comprising: a first N-FinFET having a source, a drain, a front gate, and a back gate; the drain of the first N-FinFET is connected to the output of the majority gate; a second N-FinFET having a source, a drain, a front gate, and a back gate, the drain of the second N-FinFET is connected to the source of the first N-FinFET; a third N-FinFET having a source, a drain, a front gate, and a back gate, the drain of the third N-FinFET is connected to the source of the second N-FinFET, the source of the third N-FinFET is connected to a low reference voltage a first P-FinFET having a source, a drain, a front gate, and a back gate; the drain of the first P-FinFET is connected to the output of the majority gate; a second P-FinFET having a source, a drain, a front gate, and a back gate, the drain of the second P-FinFET is connected to the source of the first P-FinFET; a third P-FinFET having a source, a drain, a front gate, and a back gate, the drain of the third P-FinFET is connected to the source of the second P-FinFET, the source of the third P-FinFET is connected to a high reference voltage.