Patent ID: 8081706

Claim:
Receiver circuitry comprising: a plurality of circuit lanes, each receiving a respective serial data signal, and each including controllable delay circuitry for giving the serial data signal in the associated circuit lane a controllable amount of delay to compensate for skew among the serial data signals in the plurality of circuit lanes, wherein each of the plurality of circuit lanes further includes (1) clock and data recovery (“CDR”) circuitry downstream from the controllable delay circuitry in that circuit lane for recovering both a clock signal and serial data from the serial data signal output by the controllable delay circuitry in that circuit lane and (2) further delay circuitry downstream from the CDR circuitry in that circuit lane for giving the serial data recovered by the CDR circuitry in that circuit lane a further controllable amount of delay, wherein the further controllable amount of delay is set by a control signal generated by the CDR circuitry.