Patent ID: 7109585

Claim:
An integrated circuit device, comprising: a semiconductor substrate having an interlayer insulating layer thereon; a first junction block embedded in the interlayer insulating layer, said first junction block comprising: a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces; and a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy-conductive vias connected to opposite ends of the dummy conductive trace; and a plurality of upper metallization traces routed on the interlayer insulating layer, wherein the plurality of upper metallization traces are configured to electrically connect with respective ones of the first plurality of pairs of conductive vias and maintain the dummy conductive trace and the pair of dummy conductive vias in an unused and electrically floating condition, and wherein all of the first plurality of pairs of conductive vias remain connected to ones of the plurality of upper metallization traces irrespective of the routing of the plurality of upper metallization traces on the interlayer insulating layer.