Patent ID: 7599456

Claim:
An input/output data rate synchronization system comprising: a first data buffer that receives input data at a first rate, that temporarily stores said input data, and that outputs said input data at a second rate; a data processing module that receives said input data from said first data buffer at said second rate and that outputs processed data at a third rate that is different than said second data rate; and a second data buffer that receives said processed data from said data processing module at said third rate, that temporarily stores said processed data, and that outputs said processed data at a fourth rate that is different than said third data rate, wherein said data processing module temporarily stops receiving said input data and generating said processed data when said second data buffer exceeds a first predetermined capacity, wherein said data processing module increases said second rate when said first data buffer exceeds a second predetermined capacity, wherein said first data buffer includes a read pointer and a write pointer and wherein said data processing module determines an amount of said input data in said first data buffer with respect to said second predetermined capacity by computing a difference between positions of said read and write pointers, and wherein said second rate is based on a rate of change of said difference between positions of said read and write pointers.