Patent ID: 7984216

Claim:
A system for operating circuitry in a mobile wireless communications device, comprising: one or more radio frequency integrated circuit (RFIC) chips that comprise a transmitter front end, a receiver front end and a baseband processor; and a controller integrated circuit (IC) chip coupled to the RFIC chip, the controller IC chip comprising a first processor, an RFIC controller, a general purpose input/output (GPIO) interface, a three-wire interface (TWIF) and a digital-to-analog converter (DAC) control interface, a timer and a bus, wherein the first processor, the RFIC controller, the GPIO interface, the TWIF, the DAC control interface and the timer are coupled to the bus, wherein the first processor communicates over the bus with the RFIC controller, wherein the RFIC controller communicates over the bus with the GPIO interface, the TWIF and the DAC control interface, wherein the RFIC controller communicates with the RFIC chip via at least the GPIO interface, the TWIF and the DAC control interface, and wherein the timer comprises a wideband code division multiple access (WCDMA) timer and a global system for mobile communications (GSM) timer and provides a timing count to the RFIC controller, and wherein the timing count correlates to a number of WCDMA chip periods.