Patent ID: 6895476

Claim:
In a computer system having a plurality of processors and a main memory organized into a plurality of memory blocks, the processors having one or more caches, a method for resolving a late race condition between a first processor and a second processor for a given memory block, the method comprising the steps of: forwarding from main memory to the first processor a memory request specifying the given memory block, the memory request initiated by the second processor; writing back a modified version of the given memory block from the first processor's cache to main memory; in response to the memory request, issuing a Retry command from the first processor to the second processor; in response to the Retry command, issuing a memory version request from the second processor to main memory, the memory version request specifying a selected version of the given memory block; sending the given memory block from main memory to the second processor provided that the version of the given memory block at main memory matches the selected version specified in the memory version request from the second processor.