Patent ID: 8461897

Claim:
An apparatus for biasing one or more switches, the apparatus comprising: a first complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well, the source and drain formed in the well, the gate formed adjacent the well between the source and drain, and the source configured to receive a bias voltage from a power amplifier; a gate bias control block for biasing the gate voltage of the first CMOS switch, the gate bias control block configured to bias the gate voltage of the first CMOS switch to at least two gate voltage levels; a well bias control block for biasing the well voltage of the first CMOS switch, the well bias control block configured to bias the well voltage of the first CMOS switch to at least two well voltage levels; and a buffer circuit for increasing an impedance between the well bias control block and the well of the first CMOS switch, the buffer circuit disposed in an electrical path between the well bias control block and the well of the first CMOS switch.