Patent ID: 7999719

Claim:
A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising: a first SAR ADC comprising: a first capacitor array configured to generate n-bit level voltages, a first comparator configured to compare a first analog input voltage with the n-bit level voltages, and a first SAR logic circuit configured to digitally convert the first analog input voltage into n bits using the comparison result from the first comparator where n is an integer equal to or greater than 1; a remaining voltage amplifier configured to amplify a remaining voltage output from the first SAR ADC and to output an amplified remaining voltage; and a second SAR ADC configured to digitally convert the amplified remaining voltage into m bits, where m is an integer equal to or greater than 1, wherein the first SAR ADC digitally converts a second analog input voltage while the second SAR ADC digitally converts the amplified remaining voltage, wherein the first SAR ADC and the remaining voltage amplifier operate during different periods of time, wherein the first SAR ADC, the remaining voltage amplifier, and the second SAR ADC are separated with each other.