Patent ID: 7408373

Claim:
An apparatus for testing a voltage drop suppression device for power bus of a probe card used for semiconductor wafer testing, comprising: a test circuit for simulating an impulsive load on a device under test (DUT) by said probe card, the load components being chosen to generate a voltage reduction during a time period of said impulsive load, said voltage reduction being sufficient to cause the device under test (DUT) to fail a structural test; a bypass capacitor mounted on the probe card, wherein the bypass capacitor is charged to a voltage greater than a power supply voltage VDD of the device under test being simulated by said test circuit; and an active regulation circuit controlling the discharge of the bypass capacitor to the power bus for suppressing a voltage drop on the power bus generated by a current surge during testing of the device under test, said current surge being simulated by said test circuit, wherein the active regulation circuit comprises a transistor for controlling the discharge of the bypass capacitor, wherein power flowing to the power bus flows through the transistor, and an amplifier providing feedback control of the transistor such that the transistor is turned on as the power bus voltage decreases.