Patent ID: 6914467

Claim:
A method of providing programming of dual edge programmable delay unit comprising: providing a buffer circuit which is adapted to receive a buffer input signal, with said buffer input signal falling at an input signal fall time and said buffer input signal rising at an input signal rise time; said buffer circuit providing a falling buffer output signal at an output signal fall time and a rising buffer output signal at an output signal rise time; providing a variable fall time control input; providing a variable rise time control input; providing a Fall Time Programmable Control Source (FTPCS) for programming a variable FTPCS signal to said buffer circuit as a function of said fall time control input; providing a Rise Time Programmable Control Source (RTPCS) for programming a variable RTPCS signal to said buffer circuit as a function of said rise time control input; said buffer circuit providing said buffer output signal with a fall time delay between said input signal fall time and said output signal fall time as a function of said variable FTPCS signal; and said buffer circuit providing said buffer output signal with a rise time delay between said input signal rise time and said output signal rise time as a function of said variable RTPCS signal.