Patent ID: 7078775

Claim:
A semiconductor device comprising: a substrate; a mesh-shaped gate electrode located over a surface of the substrate, the mesh-shaped gate electrode having a plurality of openings aligned over respective source/drain regions of the substrate; a gate dielectric layer interposed between the mesh-shape gate electrode and the surface of the substrate; and at least one oxide region located in the substrate below the mesh-shaped gate electrode, wherein a thickness of the oxide region is greater than a thickness of the gate dielectric layer, wherein the mesh-shaped gate electrode comprises a plurality of first elongate wirings extending parallel to one another, and a plurality of second elongate wirings extending parallel to one another, and wherein the first elongate wirings intersect the second elongate wirings to define an array of gate intersection regions over the surface of the substrate and to further define an array of source/drain regions of the substrate, and wherein the at least one oxide region comprises a plurality of elongate oxide regions extending parallel to each other and lengthwise below the first elongate wirings of the mesh-shaped gate electrode.