Patent ID: 7844021

Claim:
A method for compensating for skew among a plurality of clocks in a clock and data recovery system, wherein said clocks are applied to a plurality of latches to sample an incoming signal, said method comprising the steps of: applying a reference signal to a data input of each of said latches; evaluating statistics of “early” and “late” corrections applied to at least one of said clocks by a bang-bang phase detector in said clock and data recovery system; adjusting a delay of a clock buffer associated with said at least one of said clocks to obtain approximately a 50% early-to-late ratio for said at least one of said clocks, wherein said clock and data recovery system ensures that a sum of early-to-late ratios for said plurality of clocks is approximately 50%; and adjusting a phase of at least one sample clock, wherein said phase of at least one sample clock is adjusted by digitally re-mapping latch outputs in said bang-bang phase detector, such that one or more sample clocks become transitions clocks, and one or more transition clocks become sample clocks.