Patent ID: 8860178

Claim:
A semiconductor device, comprising a semiconductor chip having: a semiconductor substrate; a multilayered interconnect having a bottom surface contacting said semiconductor substrate and an uppermost surface opposite to the bottom surface; an inductor embedded within said multilayered interconnect and spaced apart from the bottom and uppermost surfaces; a plurality of first pads respectively physically contacting external electrode terminals on said uppermost surface of said multilayered interconnect in a region around the inductor on at least three sides thereof in a plan view, the first pads being in direct physical contact with the respective external electrode terminals; and a circuit forming region provided right under said first pads, wherein an area of said uppermost surface of said multilayered interconnect overlapping said inductor does not include any pads for physically contacting external electrode terminals, and wherein an area of an upper side of said semiconductor substrate overlapping said inductor does not include any circuit elements.