Patent ID: 6845349

Claim:
A method of designing a logic circuit to be implemented as a semiconductor integrated circuit, the method comprising steps to be executed by a designing device, the steps including: forming a binary decision diagram, based on a logic function which defines logic relationship between logic inputs and logic outputs of a logic circuit to be designed; determining a pass-transistor logic circuit corresponding to said binary decision diagram, said pass-transistor logic including a plurality of pass-transistor circuits each corresponding to one of plural nodes which compose said binary decision diagram; simulating circuit characteristic of said pass-transistor logic circuit; replacing at least one partial diagram of said binary decision diagram which influences upon circuit characteristics of said pass-transistor logic circuit by another partial diagram, if said simulated circuit characteristic does not meet a predetermined target specification; and repeating said determining step to said simulating step, with respect to said binary decision diagram after said replacing step; wherein said at least one partial diagram comprises a plurality of nodes connected in a cascade; wherein said another partial diagram comprises one node which is used instead of said plurality of nodes, and a plurality of nodes which generate logical combination of a plurality of control variables each supplied to one of said plurality of nodes included in said one partial diagram, and supplies said logical combination to said one node as a control variable.