Patent ID: 7568074

Claim:
A method of communicating data between nodes programmed into a integrated circuit using a memory switch of the integrated circuit, wherein the memory switch includes a plurality of switch input ports and a plurality of switch output ports, the method comprising: writing the data into sections of the integrated circuit memory in a timed fashion; wherein the memory has a plurality of memory input ports and a plurality of memory output ports for parallel writing data to and parallel reading data from respective sections of the memory; wherein the writing includes: striping the data by dividing the data into byte segments and storing the segments in different successive sections of the memory to limit read and write collisions between the plurality of switch input ports, wherein for each section of the memory, byte segments from different ones of the plurality of switch input ports are written to consecutive entries in that section and no consecutive entries in that section have byte segments from the same switch input port; wherein the striping includes parallel writing to two or more sections of the memory of data from respective packets at two or more of the plurality of switch input ports; storing pointers to the byte segments in one or more queues in an order that indicates relative times at which byte segments were written; locating data in the memory using the pointers; and reading the data from memory sections as located by the pointers; wherein the reading includes reading the pointers from all of the one or more queues in first-in-first-out order; wherein the reading from the memory sections includes parallel reading of data of respective packets from two or more sections of the memory referenced by the pointers for output at two or more of the plurality of switch output ports.