Patent ID: 8054396

Claim:
A display substrate comprising: a gate line formed in a first direction, the gate line comprising a first gate line and a second gate line adjacent to the first gate line; a data line formed in a second direction; a pixel electrode having a first pixel part and a second pixel part that are spaced apart from each other; a storage line overlapping the first and second pixel parts; a dual transistor electrically connected to the first gate line and the data line, the dual transistor having a first drain electrode and a second drain electrode; a connection transistor electrically connected to the second gate line; a voltage-decreasing electrode disposed on the storage line, the voltage-decreasing electrode being connected to a connection drain electrode of the connection transistor; a first contact electrode overlapping the first pixel part and electrically connected to the first pixel part, the first contact electrode being connected to the first drain electrode of the dual transistor and a connection source electrode of the connection transistor; and a second contact electrode overlapping the second pixel part and electrically connected to the second pixel part, the second contact electrode being connected to the second drain electrode of the dual transistor.