Patent ID: 8598936

Claim:
A semiconductor integrated circuit comprising: a level shift circuit including first and second PMOS transistors placed in parallel between a first power supply terminal through which a first power supply voltage at a level in accordance with a voltage condition is supplied and a ground voltage terminal, each transistor having a gate connected to a drain of the other transistor, third and fourth PMOS transistors respectively placed between drains of the first and second PMOS transistors and the ground voltage terminal, each transistor having a gate to which a clamp voltage at a level in accordance with the voltage condition is applied, first and second NMOS transistors respectively placed between drains of the third and fourth PMOS transistors and the ground voltage terminal, each transistor having a gate to which a second power supply voltage at a specified level is applied, and third and fourth NMOS transistors respectively placed between sources of the first and second NMOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in a complementary manner in accordance with an input signal; a bypass circuit including first and second bypass MOS transistors respectively placed between drains of the first and second PMOS transistors and the ground voltage terminal, each transistor having a gate to which the second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with the input signal and the voltage condition; and an output circuit including a fifth PMOS transistor placed between the first power supply terminal and an external output terminal, the transistor having a gate to which a drain voltage of the second PMOS transistor is applied, a sixth PMOS transistor placed between a drain of the fifth PMOS transistor and the external output terminal, the transistor having a gate to which the clamp voltage is applied, a fifth NMOS transistor placed between the ground voltage terminal and the external output terminal, the transistor controlled to be ON and OFF in accordance with the input signal, and a sixth NMOS transistor placed between a drain of the fifth NMOS transistor and the external output terminal, the transistor having a gate to which the second power supply voltage is applied.