Patent ID: 7451430

Claim:
A transistor model generating apparatus comprising: a transistor region extracting section configured to extract a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit; a dividing section configured to set a division line extending in a direction of a gate length of a transistor to divide said non-rectangular transistor region into a plurality of rectangular transistor regions; a relating section configured to relate said non-rectangular transistor region and said plurality of rectangular transistor regions with said mask layout data; a size calculating section configured to calculate a size data of each of said plurality of rectangular transistor regions; a correction value calculating section configured to calculate a correction value of a diffusion layer length dependency parameter to said plurality of rectangular transistor regions based on said size data; and a transistor model registering section configured to register a transistor model of said transistor for a circuit simulation based on said diffusion layer length dependency parameter and said correction value.