Patent ID: 8461586

Claim:
A semiconductor device comprising: a memory cell comprising: a first transistor including: a first channel formation region; a first gate insulating layer over the first channel formation region; a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region; a second transistor including: a second channel formation region; a source electrode and a drain electrode which are electrically connected to the second channel formation region; a second gate electrode over the second channel formation region; and a second gate insulating layer between the second channel formation region and the second gate electrode; and an insulating layer between the second channel formation region and one of the source region and the drain region, wherein the first transistor and the second transistor overlap with each other at least partly, and wherein the second gate insulating layer and the insulating layer satisfy a formula: t a t b · ɛ rb ɛ ra < 0.1 wherein t a represents a thickness of the second gate insulating layer, t b represents a thickness of the insulating layer, ∈ ra represents a dielectric constant of the second gate insulating layer, and ∈ rb represents a dielectric constant of the insulating layer.