Patent ID: 8283766

Claim:
A chip package, comprising: a set of semiconductor dies arranged in a vertical stack in a vertical direction, which is substantially perpendicular to a first semiconductor die in the vertical stack, wherein each semiconductor die, after the first semiconductor die, is offset in a horizontal direction by an offset value from an immediately preceding semiconductor die in the vertical stack, thereby defining a stepped terrace at one side of the vertical stack; and a ramp component, electrically and rigidly mechanically coupled to the semiconductor dies, wherein the ramp component is positioned on the one side of the vertical stack, wherein the ramp component is approximately parallel to a direction along the stepped terrace, which is between the horizontal direction and the vertical direction, and wherein each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction along the stepped terrace and is mechanically coupled to the ramp component.