Patent ID: 7404049

Claim:
A single internal buffer for managing a buffered program operation for a plurality of words comprising: a plurality of locations, each of the plurality of words being stored in a location of the plurality of locations, the plurality of words being associated with a plurality of internal address bits for the plurality of locations, at least one of the plurality of internal address bits being at least one group address bit corresponding to all of the plurality of words, a remaining portion of the plurality of internal address bits being associated at least one individual word in the plurality of words, the at least one group address bit and the plurality of internal address bits uniquely identifying the location of each of the plurality of words, each of the plurality of words including a plurality of bits; at least one bit location for the plurality of locations, the at least one bit location storing the at least one group address bit for the plurality of words, wherein a misaligned programming operation can be performed by storing a correct value of one address bit in the at least one group but location and the remaining values of the internal address bits are obtained by word position by the single internal buffer.