Patent ID: 8908814

Claim:
An apparatus, comprising: a set of decoders, wherein each decoder in the set of decoders is configured to decode a separate block of data according to a decoding sequence that includes a plurality of decoding iterations; and a controller configured to control each decoder from the set of decoders to independently initiate decoding while at least one other decoder in the set of decoders is decoding, wherein the controller is configured to independently initiate decoding according to a transition point that aligns with separate iterations in respective decoding sequences between the set of decoders, wherein the controller is configured to generate the transition point iteratively at iterations in the respective decoding sequences as a global transition for controlling the set of decoders to begin each iteration in the respective decoding sequences together and wherein the controller is configured to control each decoder of the set of decoders to independently initiate separate decoding sequences at different successive transition points by controlling the set of decoders together using the transition points, and wherein the apparatus is a single input multiple data (SIMD) processor.