Patent ID: 8159255

Claim:
A method for detecting defects in an integrated circuit with quiescent supply current (I DDQ ) testing, comprising: sensing a state of a plurality of addressable components respectively, of a low power semi-conductor integrated circuit; testing the plurality of addressable components with a plurality of vectors, at least one vector causing a quiescent supply current level, the at least one vector being defined as a failing vector if the quiescent supply current level is above a desired level, otherwise the at least one vector being defined as a passing vector; forming a sample pair of a failing vector and a passing vector from the plurality of vectors; and iteratively forming a probe vector as a combination of the failing vector and passing vector with additional subsets from a failing vector of a previously formed passing probe vector or additional subsets from a passing vector of a previously formed failing probe vector to converge upon a final sample pair differing by a critical bit whose state directly correlates with either a passing or failing result.