Patent ID: 8306160

Claim:
A synchronizing circuit comprising: a coarse synchronizing circuit which determines temporary reception timing using a preamble consisting of repetitions of known training signals added to a received packet; a synchronization candidate timing control section which sets up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates, a first, a second, and a third synchronization candidate from the multiple synchronization candidates set at the temporary reception timing minus a predetermined time period, at the temporary reception timing, and at the temporary reception timing plus the predetermined time period, respectively, the first, second, and third synchronization candidates processed at the same time; a signal quality monitoring section which monitors signal quality of the received signals synchronized in each of the multiple synchronization candidates; and a synchronization candidate selecting section which selects one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section.