Patent ID: 7791940

Claim:
An integrated circuit, comprising: a plurality of first memory cells, which are electrically coupled along a first line; a plurality of second memory cells, which are electrically coupled along a second line; a switching unit comprising a plurality of switching elements, each switching element comprising a first contact and a second contact; wherein the first contact of a first switching element is coupled to the plurality of first memory cells; wherein the first contact of a second switching element is coupled to the plurality of second memory cells; wherein the first contact of a third switching element is coupled to the second contact of the first switching element; wherein the first contact of a fourth switching element is coupled to the second contact of the second switching element; wherein the first contact of the second switching element and the second contact of the second switching element are electrically short-circuited; wherein the first contact of the third switching element and the second contact of the third switching element are electrically short-circuited; and wherein an electrical connection couples the second contact of the third switching element and the second contact of the fourth switching element.