Patent ID: 8767466

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory string including a plurality of memory cells connected in series, and stacked above the semiconductor substrate; a drain side select transistor connected to one end of the memory string; a source side select transistor connected to the other end of the memory string; a plurality of word lines connected to the memory cells; a plurality of bit lines connected to the drain side select transistor; a source line connected to the source side select transistor; and a control circuit configured to control voltages to be supplied to the drain side select transistor, the source side select transistor, the word lines, and the bit lines, the control circuit being configured to, when performing a data erase operation: supply positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage; supply a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period; and supply a voltage smaller than the first voltage to a second word line different from the first word line during a second time period, the second time period being different from the first time period.