Patent ID: 7728888

Claim:
A clamping circuit comprising: a subtracter for subtracting a clamping correction voltage from an input analog voltage signal; A/D converter for converting an analog voltage signal from the subtracter into a digital voltage signal of M bits; a potential difference detection circuit for detecting a potential difference between a digital voltage signal outputted from said A/D converter and a previously set clamping voltage; D/A converter for converting a digital signal of N (N<M) bits within the digital signal of M bits representing a potential difference outputted from said potential difference detection circuit into an analog signal; an adjusting voltage generation circuit for generating an adjusting voltage based on a potential difference outputted from said potential difference detection circuit and a threshold voltage set with respect to the potential difference; and an adder for adding together an output from said D/A converter and an adjusting voltage outputted from said adjusting voltage generation circuit to generate said clamping correction voltage.