Patent ID: 7254658

Claim:
Apparatus for processing data, said apparatus comprising: at least one bus master operable to generate write transactions; and at least one bus slave operable to receive said write transactions; wherein a write transaction includes transferring a write address from a bus master to a bus slave and separately transferring write data from said bus master to said bus slave; said bus slave is operable to receive a plurality of interleaved write transactions whereby the write data of a plurality of co-pending write transactions is received in a variable order, with respect to corresponding write addresses; a bus master interface circuit between said bus master and said bus slave is operable to generate a transaction identifier for a write transaction, said transaction identifier being transferred over a first identifier bus channel to said bus slave with said write address and separately over a second identifier bus channel to said bus slave with said write data; and said bus slave is responsive to respective transaction identifiers associated with interleaved write transactions to correlate received writes addresses with received write data.