Patent ID: 7629834

Claim:
A semiconductor apparatus comprising: a limiter circuit comprising: a differential amplifier circuit having a non-inverting and an inverting inputs, the inverting input fed with an input signal to the limiter circuit; a driving circuit fed with an output of the differential amplifier; a MOS transistor having a source, a drain and a gate, one of the source and the drain of the MOS transistor connected to an output of the driving circuit, the other of the source and the drain of the MOS transistor connected to the non-inverting input of the differential amplifier, the gate of the MOS transistor applied with a predetermined voltage; and a load circuit connected to the other of the source and the drain of the MOS transistor, a first voltage source being configured to supply a first operating voltage to a first operating circuit that outputs the input signal of the limiter circuit; a second operating circuit fed with an output signal of the limiter circuit; and a second voltage source being configured to supply a second operating voltage to the second operating circuit, the second operating voltage being lower than the first operating voltage, wherein: the MOS transistor is a depletion type MOS transistor such that the limiter circuit has an upper limit of an output voltage greater than the predetermined voltage.