Patent ID: 6841812

Claim:
A double-gated vertical junction field effect transistor comprising: (a) a low-voltage LJFET comprising a lateral channel double-gated by a first p+n junction and a second p+n junction along opposite sides of said lateral channel, a top gate forming said first p+n junction having a first p+ subregion formed by ion implantation, and a bottom gate forming by said second p+n junction composed of a buried p+ layer on top of an n− blocking layer, said buried p+ layer extending to a top surface along said double-gated vertical junction field effect transistor for electric connection to said top gate by implanting a second p+ subregion extending from said top surface down to said buried p+ layer; and (b) a high voltage VJFET having a vertical channel formed by converting a portion of said buried p+ layer to an n-type semiconductor by implantation, said vertical channel extending into a drift layer below said buried p+ layer.