Patent ID: 7165196

Claim:
A test system for testing a serializer/de-serializer system, the system comprising: a first serializer/de-serializer having a first serial data receive port and a first serial data transmit port the first serializer/de-serializer being placed in a loop-back mode in response to a loop-back signal fed to the first serializer/de-serializer to pass data fed to the first serial data receive port to the first serial data transmit port; a second serializer/de-serializer having a second serial data receive port and second serial data transmit port second serializer/de-serializer being placed in a loop-back mode in response to a loop-back signal fed to the second serializer/de-serializer to pass data fed to the second serial data receive port to the second serial data transmit port, the first serial data transmit port being connected to the second serial data receive port; a tester for feeding data to the first serial data receive port and for receiving data from the second serial data transmit port with both such the first and second serializers/de-serializers placed in the loop-back mode; and wherein the first serializer/de-serializer and the second serializer/de-serializer are on different integrated circuit chips.