Patent ID: 7016441

Claim:
A bit synchronizing circuit used for a reception circuit for serial communication, comprising: a polyphase clock generation circuit for generating a plurality of clocks which are out of phase with each other by a regular interval, based on an input clock, the polyphase clock generation circuit including a plurality of delay circuits connected in series and the first one of said plurality of delay circuits receiving the input clock, wherein each of said plurality of delay circuits generates one of said plurality of clocks; a detection circuit for detecting which clock has a phase shift of an integral multiple of a clock cycle among the clocks generated by the polyphase clock generation circuit with respect to the clock generated by the first delay circuit that receives the input clock; and a clock selecting circuit to which a polyphase clock is inputted from the polyphase clock generation circuit and which selects an outputted polyphase clock based on a detection result from the detection circuit.