Patent ID: 7733320

Claim:
A shift register circuit comprising: a plurality of cascade-connected signal holding circuits, each of the signal holding circuits comprising: an input control circuit to which an input signal is applied, and which fetches and holds the input signal; an output control circuit to which a first control clock signal is applied, and which outputs an output signal corresponding to timings of the held input signal and the first control clock signal; a transfer control circuit to which a second control clock signal is applied, and which outputs a shift signal corresponding to timings of the input signal held in the input control circuit and the second control clock signal, and supplies the shift signal as the input signal to the signal holding circuit on a next stage; and a reset control circuit to which a reset signal is applied, and which initializes a signal level of the input signal held in the input control circuit, wherein each of the first control clock signal and the second control clock signal has a first signal level and a second signal level which are different from each other, wherein a signal width in which the first control clock signal changes to the first signal level is the same as or shorter than a signal width in which the second control clock signal changes to the first signal level, wherein the first control clock signal is set to change from the first signal level to the second signal level prior to a timing at which the second control clock signal changes from the first signal level to the second signal level, and wherein a timing at which the output signal is terminated is set to be ahead of an application start timing of the reset signal.