Patent ID: 6895421

Claim:
An apparatus for performing a linear transformation, comprising: first and second inputs which receive input data and predetermined data; transformation circuitry which acts on the input data and predetermined data; control and address generation circuitry, connected to a first memory, which generates corresponding addresses for accessing cells of said memory, and for controlling the selection between a data receiving mode, in which data is received via said first input, and a data processing mode, in which the arrival of incoming data via said first input is blocked; and counter circuitry for controlling the timing of the operations of the apparatus; wherein the control and address generation circuitry comprises: a second memory which stores pre-programmed processing and control data; a comparator circuitry which switches between the data receiving mode and the data processing mode; a first set of multiplexers, each of which having at least one direct input for receiving transformation data, and another input, into which said transformation data is fed via a corresponding inverter, said first set being controlled to transfer transformation data or, inverted transformation data, by a predetermined value provided by said transformation data; a second set of multiplexers, each of which having at least one input connected to the output of a corresponding multiplexer selected from said first set of multiplexers, and another input, connected to said second memory, said second set being controlled by said comparator circuitry to provide a first address to the first memory by transferring the output of each multiplexer from said first set to the output of its corresponding multiplexer from said second set or, to provide at least a portion of the second address to the first memory by transferring data stored in said second memory; and a multiplexer, operating in combination with said second set of multiplexers in said data processing mode, having an unconnected input and an input connected to said second memory and controlled by said comparator circuitry, thereby providing the remaining portion of said second address.