Patent ID: 8507971

Claim:
In a non-volatile memory comprising at least one array of memory cells, wherein each of the memory cells comprise a source, a control gate, and a drain, and are capable of storing at least one bit, a method for manufacturing said array of memory cells, comprising: forming at least one row of shallow trench isolation (STI) regions in a substrate of said array of memory cells, said STI regions separating a plurality of bit lines arranged in columns; forming said plurality of bit lines in said substrate, said plurality of bit lines coupled to sources and drains of said memory cells; forming a plurality of word lines, said plurality of word lines coupled to control gates of said memory cells wherein an ONO layer is formed between said control gates and said substrate wherein said plurality of word lines are separated by SiN sidewall spacers that overlap a downward sloped portion at the left and right sides of a top surface of said STI region wherein the bottom of the downward sloped portion at the left and right sides of a top surface of said STI region contact top corners of a portion of said substrate; and forming a cobalt silicide (COSI) layer between bit line contacts and said plurality of bit lines in at least one row of contacts.