Patent ID: 8461806

Claim:
A cell balancing circuit for balancing a plurality of cells, comprising: a logic core operable for detecting if any cell is in balancing phase, reading a full charge capacity (FCC) recorded in a previous cycle for each cell when no cell is in said balancing phase, checking a timer coupled to a cell if said cell is in said balancing phase, balancing said cell while said timer is counting, and terminating said balancing phase when said timer expires, for calculating a state-of-charge (SOC) for each of said cells, for searching a minimum SOC and a maximum SOC of said cells, for detecting an unbalanced condition if a difference between said maximum SOC and said minimum SOC is greater than a predetermined threshold, and for determining a balancing time period that is proportional to said difference if said unbalanced condition occurs, wherein said cell balancing circuit enables a bypass current for a cell having said maximum SOC for said balancing time period if said unbalanced condition occurs.