Patent ID: 7595231

Claim:
A method of manufacturing a semiconductor device comprising the steps of: forming a first conductive film on a gate insulating film fanned in first and second areas of a semiconductor substrate; selectively removing the first conductive film to form a gate electrode of a first MIS transistor in the first area and a conductive pattern covering a whole surface of the second area; forming a first insulating film covering said conductive pattern in the second area and said gate electrode in the first area, covering said first insulating film in the second area with a mask, and anisotropically etching said first insulating film in the first area to form sidewall spacer insulating films made of the first insulating film on side walls of the gate electrode of the first MIS transistor; by using the gate electrode of the first MIS transistor as a mask, introducing impurities into the first area to form source/drain diffusion regions of the first MIS transistor, and leaving the first insulating film in the second area; forming a second insulating film over the semiconductor substrate including the first and second areas; selectively removing the second insulating film, the first insulating film, and the first conductive film to form a lamination pattern of a gate electrode of a second MIS transistor in the second area; by using the Lamination pattern as a mask, introducing impurities into the second area to form source/drain diffusion regions of the second MIS transistor; forming side wall spacer insulating films made of a third insulating film on side walls of the lamination pattern; and forming a second conductive film connecting at least one of the source/drain diffusion regions in the second area.