Patent ID: 7087975

Claim:
An apparatus, comprising: a semiconductor body having on a surface thereof at least one lower antifuse and at least one upper antifuse in vertically stacked relation, the upper and lower antifuse coupled to a common intermediate electrode formed between them; the lower antifuse having a source region and a drain region formed on said surface, the drain region and the source region being coupled to said common intermediate electrode, and a lower fuse element of a lower fusible insulator portion of initial high electrical resistance overlying said surface, a gate electrode in contact with the lower fusible insulator portion for interconnecting the gate electrode and the common intermediate electrode; the upper antifuse having an upper counter electrode and an upper fusible insulator portion of initial high electrical resistance defining an upper fuse element interconnecting the upper counter electrode with the common intermediate electrode; and the upper and lower antifuses being arranged to permit their selective energizing for corresponding separate or simultaneous activation to a final low resistance electrical state, in both directions between said intermediate electrode and said gate electrode and in both directions between said intermediate electrical and said upper counter electrode.