Patent ID: 7787321

Claim:
An apparatus for sensing a state in a bit line associated with a memory cell that is programmable to a first state and a second state, the apparatus comprising: an operational amplifier coupled to a reference voltage and configured to output a voltage substantially equal to the reference voltage; a switch coupled to the voltage at a first terminal and a first node at a second terminal, the switch being controlled by a first control signal; a first input terminal configured to receive the bit line, the bit line being coupled to a current generator at a second node; an amplifier including a second input terminal coupled to the first node and a third input terminal coupled to the reference voltage, the amplifier being configured to generate a first differential output signal and a second differential output signal, the first and second differential output signals having different polarities; and a comparator including a fourth input terminal coupled to the first differential output signal, a fifth input terminal coupled to the second differential output signal and a first output terminal, the comparator being configured to generate an output signal based on the polarities of the first and second differential output signals; wherein: the current generator generates a first current, the first current flowing between the current generator and the second node; the first and second nodes are directly connected; a second current flows between the first and second nodes.