Patent ID: 7491622

Claim:
A process of forming an electronic device comprising: patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer, wherein after patterning the semiconductor layer: the semiconductor layer has a sidewall and a surface; the surface is spaced apart from the insulating layer; and the sidewall extends from the surface towards the insulating layer; and chemical vapor depositing a first layer adjacent to the sidewall, wherein: the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface; and chemical vapor depositing the first layer is performed: using an inductively coupled plasma; at a pressure no greater than approximately 20 mTorr; using a chamber that is coupled to a biasing power supply and an ionizing power supply; and during chemical vapor depositing, the biasing power supply provides a first power to the chamber at a first power flux no greater than approximately 1.6 watts/cm 2 , and the ionizing power supply provides a second power to the chamber at a second power flux that is more than double the first power flux.