Patent ID: 8787436

Claim:
A communication device comprising: an analog-to-digital converter (ADC) for converting an analog input signal into a digital input signal; an equalizer module, coupled with the ADC, for processing the digital input signal to generate an equalized signal; a data slicer, coupled with the equalizer module, for generating an output signal based on the equalized signal; a timing recovering circuit for providing a working clock to the ADC; and a control unit coupled with the equalizer module and the data slicer; wherein the control unit or the equalizer module preserves at least one signal equalizing parameter of the equalizer module before the equalizer module enters power saving mode, and the equalizer module loads the at least one signal equalizing parameter to operate when the communication device receives a predetermined control signal; wherein when the communication device receives the predetermined control signal, the control unit controls the timing recovering circuit to select a clock signal from a plurality of clock signals of different phases to be the working clock according to an error value of the output signal.