Patent ID: 7939413

Claim:
A method for forming semiconductor device comprising: providing a substrate prepared with a first active region having a first gate of a first transistor and separated by first isolation regions and a second active region having a second gate of a second transistor and separated by second isolation regions, wherein the gates comprises sidewall spacers on sidewalls of the gate; lining only the first active region with a liner layer; forming recesses in source/drain (S/D) regions adjacent to the sides of the second gate in the second active region unprotected by the liner; forming doped S/D stressors in the recesses, wherein the doped S/D stressors comprise dopants of a second polarity type; and implanting dopants of the second polarity type into the doped S/D stressors to form upper doped regions in the S/D stressors, the upper doped regions enhance the dopant concentration of the doped S/D stressors, wherein the upper doped regions comprise wrap around doped regions having first and second wrap around doped sub-regions, the first wrap around sub-regions being adjacent to the gate and the second wrap around doped sub-regions being adjacent to second isolation regions, wherein the first wrap around doped sub-regions are disposed within the doped S/D stressors and the second wrap around doped sub-regions extend below the doped S/D stressors, the upper doped regions reduce external resistance of the second transistor.