Patent ID: 7882454

Claim:
A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design, the method comprising: configuring a multiplexer device to pass, to a preexisting storage latch within the IC design, a selected one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode of operation, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode of operation, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode of operation, the existing storage latch captures data from only the existing combinational logic, thereby facilitating random testing of the random resistant logic in a manner that avoids adding latch devices to the IC design.