Patent ID: 8168497

Claim:
A method of designing a semiconductor device, the method comprising: configuring a plurality of attributes of an interface between a first electrode to a semiconductor structure of the semiconductor device and a second electrode to the semiconductor structure to substantially minimize a total resistance for the semiconductor device, wherein each electrode includes a current feeding contact and a plurality of fingers extending therefrom, and wherein the plurality of fingers of the first and second electrodes are adjacent to each other in an alternating pattern, the configuring including: determining a target depth, d FING , for each of the plurality of fingers based on a characteristic contact transfer length for a junction between the fingers and the semiconductor device, L TR ; determining a target effective width, W, of each pair of adjacent fingers of the first electrode and the second electrode based on the target depth, an impedance of at least one finger per unit width, Z FING , and an impedance of a portion of the semiconductor structure between the pair of adjacent fingers per unit width, Z SC ; and determining at least one target attribute of the current feeding contact of each of the first and second electrodes based on the target depth, the target effective width, an impedance of the current feeding contact per unit width, Z CMB , and an impedance of a pair of adjacent fingers with the semiconductor structure there between per unit width, Z FINGSC .