Patent ID: 8417870

Claim:
A memory module to operate in a memory system with a memory controller, comprising: a module controller configured to receive address/control signals from the memory controller and to output module control signals based on the received address/control Signals; a plurality of sets of memory devices, each set of memory devices including at least two groups, each group including at least one memory device; and a plurality of load-reducing circuits distributed across the memory module in positions corresponding to respective sets of memory devices, each load-reducing circuit being associated with a respective set of memory devices and selecting a first group in the respective set of memory devices to communicate data with the memory controller in response to the module control signals, wherein during a write operation, each load-reducing circuit associated with a respective set of memory devices is configured to present a reduced load to the memory controller by isolating, in response to the module control signals, a second group in the respective set of memory devices from the memory controller, the reduced load being less than a load associated with both the first group and the second group; wherein the plurality of sets of memory devices communicate with the memory controller via respective sets of data lines, and wherein the load-reducing circuits are inserted into the respective sets of data lines such that, during the write operation, the memory controller sees a single memory device load from the memory module on each data line; wherein each load-reducing circuit associated with a respective set of memory devices includes a first data path coupled to a first group in the respective set of memory devices and a second data path coupled to a second group in the respective set of memory devices, the first data path including a first tristate buffer, the second data path including a second tristate buffer, wherein the first and second tristate buffers are controlled by at least one of the module control signals.