Patent ID: 7214585

Claim:
A method for fabricating an integrated circuit, the method comprising: (1) forming a first feature from a first layer in the integrated circuit, the first feature having a first edge; (2) forming a second feature from a second layer overlying the first layer, the second feature being conductive, the second feature having a second edge, wherein forming the second feature comprises: (2A) forming the second layer over the first layer, the second layer having a portion P 1 which is to provide the second feature, the second layer also having a portion P 2 adjacent to P 1 , a top surface of the portion P 1 being at least as high as a top surface of the portion P 2 ; (2B) forming a layer L 1 over the portion P 2 but not over the portion P 1 without photolithography; (2C) after forming the layer L 1 , forming a layer L 2 over the portion P 1 but not over the portion P 2 ; (2D) after the operation (2C), removing the layer L 1 over the portion P 2 and removing the portion P 2 to form the second edge at a boundary between the portions P 1 and P 2 ; wherein the method further comprises: (3) forming a dielectric over the second feature; and (4) forming an opening in the dielectric to allow an electrical contact to the second feature; wherein a top surface of the second feature has a narrower portion and a wider portion, wherein the second edge comprises an edge of the wider portion, and the opening overlies at least a part of the wider portion.