Patent ID: 7003651

Claim:
A processor comprising: a storage circuit for temporarily storing an instruction word, from which the stored instruction word is read at an instruction execution time; a decoder for receiving the instruction word and for determining whether an effective address of said instruction word is specified as a PC relative displacement value; an adder for adding of the PC relative displacement value and predetermined lower bits of the PC address, and for outputting the calculating result outputted from said adder as a portion of the effective address if said instruction word has the PC relative displacement value; a selector for replacing the displacement value in the instruction word with the calculating result outputted from said adder, and for outputting said replaced result to said storage circuit as a semiABS displacement value of the instruction word, if said instruction word has the PC relative displacement value; an effective address calculator for calculating the effective address with the semiABS displacement value at the instruction execution time; and a carry bit recovering means for recovering the disregarded carry bit of said adder, including: a comparator for comparing the semiABS displacement value and lower bits of the PC address; a decoder for receiving the comparing result, a sign bit of the semiABS displacement value, and a bit which is a digit higher than the highest bit of the lower bits of the PC address in the PC address thereby outputting a selecting signal for selecting one of +1, 0, and −1 according to a predetermined conversion table; and means for adding +1, 0, or −1 to the rest bits of the PC address then to a upper portion of the effective address with a bit number equal to the rest bits of the PC address according to the selecting signal thereby deciding a recovered carry bit, wherein said effective address calculator calculates said effective address without using the carry bit generated by said adder.