Patent ID: 8860514

Claim:
An integrated circuit comprising: a fractional-N divider circuit coupled to receive a first clock signal and supply a divided clock signal; and a digital-to-time converter circuit coupled to receive the divided clock signal and a digital value corresponding to a digital quantization error associated with the fractional-N divider circuit and supply an adjusted divided clock signal having a delay linearly proportional to the digital quantization error, the digital-to-time converter circuit including, a first capacitor and a second capacitor; and a first circuit and a second circuit selectively coupled to supply current to the first and second capacitors; wherein the digital-to-time converter circuit is configured to generate a first edge of a pulse of the adjusted divided clock signal in response to the first capacitor charging to a predetermined voltage and the digital-to-time converter circuit is configured to generate a next pulse of the adjusted divided clock signal in response to the second capacitor charging to the predetermined level.