Patent ID: 8564133

Claim:
A chip package, comprising: a semiconductor substrate having an upper surface and an opposite lower surface; a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate; a first chip disposed overlying the upper surface of the semiconductor substrate; a conducting layer overlying a sidewall of the through-hole and electrically connecting the first chip; a first insulating layer overlying the upper surface of the semiconductor substrate; a second insulating layer overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer; a bonding structure disposed overlying the lower surface of the semiconductor substrate; and a self-aligned wall located on the upper surface of the semiconductor substrate and adjacent to or contacted with the first chip, wherein a distance between a top surface of the self-aligned wall and the upper surface of the semiconductor substrate is larger than a distance between a bottom surface of the first chip and the upper surface of the semiconductor substrate.