Patent ID: 8853810

Claim:
A method for fabricating an integrated circuit comprising: fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions; after fabricating the plurality of transistors including after forming the silicide contacts, depositing a layer of hard mask material overlying the transistors; patterning the layer of hard mask material to form an opening through the layer of hard mask material in proximity to the drain region of a selected one of the transistors; etching a trench into the semiconductor substrate through the metal silicide contacts to the drain regions using the patterned layer of hard mask material as an etch mask; filling the trench with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material; after filling the trench with the layer of metal, the layer of dielectric material, and the second metal, forming a metal contact coupling the second metal to the silicide contact on the drain region of the selected one of the transistors; and forming a bit line contacting the source region of the selected one of the transistors and a word line contacting the gate structure of the selected one of the transistors.