Patent ID: 8687416

Claim:
A signal processing circuit comprising: a control unit; an arithmetic unit; and a buffer memory device, wherein the buffer memory device stores data sent from a main memory device or the arithmetic unit in accordance with an instruction from the control unit, wherein the buffer memory device comprises a plurality of memory cells, and wherein the memory cells each comprise: a first word line and a second word line; a first data line and a second data line; a first transistor comprising an oxide semiconductor in a channel formation region; a second transistor; and a memory element to which charge whose amount depends on a value of the data is supplied via the first transistor, wherein a gate of the first transistor is electrically connected to the first word line and one of source and drain of the first transistor is electrically connected to the first data line, and wherein a gate of the second transistor is electrically connected to the second word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to the memory element.