Patent ID: 7812399

Claim:
A semiconductor device comprising: a first conduction type substrate; a gate electrode of an approximately quadrangular prism, including a laminated body of a gate oxide layer provided directly on a surface of the first conduction type substrate, a gate polysilicon layer provided directly on the gate oxide layer, and a gate silicon nitride layer provided directly on the gate polysilicon layer, said gate electrode having a rectangular top face, a first side surface, a second side surface opposite to the first side surface, a third side surface located between the first side surface and the second side surface, and a fourth side surface opposite to the third side surface and located between the first side surface and the second side surface; a second conduction type implantation region provided in the first conduction type substrate including a region located outside the gate electrode, said second conduction type implantation region including a first implantation region provided in junction with the first side surface, a second implantation region provided in junction with the second side surface, a third implantation region provided in junction with the third side surface, and a fourth implantation region provided in junction with the fourth side surface; a sidewall that exposes the top face of the gate electrode and comprises a sidewall mask oxide layer covering the first side surface, the second side surface, the third side surface and the fourth side surface, an electron storage nitride layer including a first partial region opposite to the first side surface of the gate electrode, a second partial region opposite to the second side surface thereof, a third partial region opposite to the third side surface thereof, and a fourth partial region opposite to the fourth side surface thereof, and a sidewall silicon oxide layer, said sidewall mask oxide layer, said electron storage nitride layer and said sidewall silicon oxide layer being laminated directly on one another; and a source/drain diffusion layer provided in the first conduction type substrate exposed from the gate electrode and the sidewall.