Patent ID: 7941612

Claim:
A semiconductor memory device, comprising: a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors; an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors; and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors, wherein the access path forming unit comprises: a path decision unit to logically combine the external signals and generate a path decision signal; a row and column address multiplexer for selecting one row and one column address from row and column addresses respectively applied through the ports in response to the path decision signal, and applying the address to each of a row decoder and a column decoder coupled to the shared memory area; first and second global multiplexers for connecting a global input/output line of the shared memory area to a first data input/output line, or the global input/output line of the shared memory area to a second data input/output line, in response to the path decision signal; and an input/output related path unit including a first input/output related circuit coupled between the first global multiplexer and a first one of the ports, and a second input/output related circuit coupled between the second global multiplexer and a second port one of the ports.