Patent ID: 7042754

Claim:
A ferroelectric memory device comprising: a plurality of memory cells each having a ferroelectric capacitor that stores predetermined data; a plurality of word lines, a plurality of bit lines and a plurality of plate lines which are connected to each of the plurality of memory cells; a plate line control section that changes a potential on a specified one of the plate lines connected to a specified one of the memory cells, thereby discharging a data accumulation charge indicating the predetermined data accumulated in the specified one of the memory cells to a specified one of the bit lines connected to the specified one of the memory cells to thereby read out the predetermined data stored in the specified one of the memory cells, and discharges a reference accumulation charge that is a charge accumulated in the specified one of the memory cells from which the predetermined data is read out to the specified one of the bit lines; a first sense amplifier line and a second sense amplifier line; a bit line selection section that selects the specified one of the bit lines among the plurality of bit lines to be connected to the first sense amplifier line and the second sense amplifier line based on a change of the potential on the specified one of the plate lines; a bit line connection section that retains at the first sense amplifier line a potential on the specified one of the bit lines when the data accumulation charge is discharged by connecting the specified one of the bit lines to the first sense amplifier line, and retains at the second sense amplifier line a potential on the specified one of the bit lines when the reference accumulation charge is discharged by connecting the specified one of the bit lines to the second sense amplifier line; and a sense amplifier that judges the predetermined data stored in the specified one of the memory cells based on potentials on the first sense amplifier line and the second sense amplifier line.