Patent ID: 8610282

Claim:
A semiconductor device comprising: a substrate; a plurality of interconnects extending in a direction, having line shapes in plan view, and provided in the same interconnect layer above the substrate; and a plurality of insulators having line shapes in plan view and provided so as to be buried between the plurality of interconnects, wherein the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more; and wherein widths of the plurality of insulators have line width roughness (LWR), and at least one of the plurality of insulators includes: a first region having a first permittivity; and a second region having a second permittivity which is lower than the first permittivity, and located in a portion having a width locally narrowed due to the LWR, the at least one of the plurality of insulators including the first and second regions in the same cross section parallel to a principal surface of the substrate.