Patent ID: 7576400

Claim:
A gate stack, comprising: a gate oxide layer over a semiconductive substrate; a polysilicon layer on the gate oxide layer; an annealed metal silicide layer on the polysilicon layer; a layer comprising Si x N y O z :H formed over and in physical contact with the metal silicide layer, wherein x is from 0.39 to 0.65, y is from 0.02 to 0.56, and z is from 0.05 to 0.33; the annealed metal silicide layer being the product of a process in which the metal silicide layer is subjected to an anneal treatment after the layer comprising Si x N y O z :H is formed, wherein the layer comprising Si x N y O z :H protects the annealed metal silicide layer during the anneal by eliminating exposure to gaseous oxygen during the anneal, further wherein a thickness of the layer comprising Si x N y O z :H ranges between a value that is greater than about 300 Angstroms (Å) to a value of approximately 650 Å; and a silicon nitride layer on the layer comprising Si x N y O z :H and having a thickness greater than 1000 Å, wherein the polysilicon layer, the gate oxide layer, the metal silicide layer, the layer comprising Si x N y O z :H, and the silicon nitride layer are patterned to form the gate stack, further wherein the layer comprising Si x N y O z :H is configured to reduce a stress on the gate stack that is imposed by the silicon nitride layer and wherein the final thicknesses of both the silicon nitride layer and the layer comprising Si x N y O z :H are optimized in combination to minimize reflection back into a overlying layer of photoresist.