Patent ID: 6957320

Claim:
A computer system, comprising: (A) a memory system that is configured to store instructions and data; (B) a processor, coupled to said memory system, for executing said instructions, said processor including (1) an instruction fetch unit adapted to fetch instructions from said memory system and to provide a predetermined plurality of said instructions to an instruction buffer; and (2) an execution unit, coupled to said instruction fetch unit, adapted to execute said plurality of said instructions from said instruction buffer in an out-of-order fashion with respect to a predefined program order, said execution unit including a load store unit adapted to make load requests to said memory system out-of-order with respect to said predefined program order and store requests to said memory system in-order with respect to said predefined program order, said load store unit including (a) an address path adapted to manage a plurality of addresses associated with said plurality of instructions and to provide addresses to said memory system, (b) a data path adapted to transfer load and/or store data to and from said memory system and said execution unit, and (c) a load aligner, coupled to said data path, for aligning unaligned data returned from said memory system to said execution unit, said load aligner including a plurality of multiplexers and a select line coupled to each of said plurality of multiplexers for selecting bytes of said data returned from said memory system, and a data buffer for storing said selected bytes of data.