Patent ID: 7271630

Claim:
A push-pull buffer amplifier to transmit an input signal to generate an output signal, the push-pull buffer amplifier comprising: an N-type comparator comparing the input signal and the output signal, a first output terminal of the N-type comparator and a second output terminal of the N-type comparator inversed thereto outputting a comparison result, wherein N-type transistor in the N-type comparator serves as its input stage; a P-type comparator comparing the input signal and the output signal, a first output terminal of the P-type comparator and a second output terminal of the P-type comparator inversed thereto outputting another comparison result, wherein P-type transistor in the P-type comparator serves as its input stage; a first inverter; the first inverter comprising: a fifth transistor, a gate of the fifth transistor being coupled to the first output terminal of the N-type comparator, a first source/drain of the fifth transistor being coupled to a first voltage line, a second source/drain of the fifth transistor being the output terminal of the first inverter; and a sixth transistor, a first source/drain of the sixth transistor being coupled to the second source/drain of the fifth transistor, a second source/drain of the sixth transistor being coupled to a second voltage line, a gate of the sixth transistor being coupled to a third voltage line; a second inverter, an input terminal of the second inverter is coupled to the first output terminal of the P-type comparator; a first output stage comprising: a first transistor, a first source/drain of the first transistor being coupled to the first voltage line, a gate of the first transistor being coupled to the second output terminal of the N-type comparator; and a second transistor, a first source/drain of the second transistor being coupled to a second source/drain of the first transistor, a second source/drain of the second transistor being coupled to the second voltage line, a gate of the second transistor being coupled to the second output terminal of the P-type comparator; and a second output stage comprising: a third transistor, a gate of the third transistor being coupled to an output terminal of the first inverter, a first source/drain of the third transistor being coupled to the second voltage line, a second source/drain of the third transistor being coupled to the second source/drain of the first transistor, and outputting the output signal; and a fourth transistor, a first source/drain of the fourth transistor being coupled to the second source/drain of the third transistor, a second source/drain of the fourth transistor being coupled to the first voltage line, a gate of the fourth transistor being coupled to an output terminal of the second inverter.