Patent ID: 7998813

Claim:
A method comprising: forming at least two peripheral transistor gate structures within a peripheral circuitry region; forming at least two access transistor gate structures within an access circuitry region after forming the two peripheral transistors within the peripheral circuitry region, forming the peripheral transistor gate structures comprising depositing first gate oxide that extends over the access circuitry region, forming the access transistor gate structures comprising: depositing dielectric material over semiconductor material, the dielectric material being deposited over the first gate oxide; etching openings through the dielectric material to the first gate oxide; forming dielectric spacers on sidewalls of the openings; using the dielectric spacers and dielectric material as a mask, extending the openings through first gate oxide and into the semiconductive material by etching; forming a second gate oxide laterally over opposing sidewalls and over bases of the openings in the semiconductor material; and forming gate material within the openings in the dielectric material and the semiconductor material; and forming a polysilicon-comprising plug on individual of opposing lateral sides of the gate material of individual of the two access transistor gate structures, the polysilicon-comprising plugs extending laterally to beneath the dielectric spacers.