Patent ID: 8704314

Claim:
A mechanical memory element, comprising: a transistor including, a substrate having formed thereon a source region and a drain region, an oxide formed upon a portion of said source region and upon a portion of said drain region, a pull up electrode positioned above such that a gap is formed between said pull up electrode and said substrate, and a movable gate having a first position and a second position, said movable gate being located in said gap between said pull up electrode and said substrate, said movable gate being in contact with said pull up electrode when said movable gate is in said first position, said movable gate being in contact with said oxide to form a gate region when said movable gate is in said second position; a word line operatively connected to said movable gate; bit sense lines operatively connected to said source region and said drain region; and a bit pull up line operatively connected to said pull up electrode.