Patent ID: 8593848

Claim:
A programming method for programming a flash memory array structure comprising: a plurality of memory cells constituting an array, wherein word lines and bit lines cross each other but are not perpendicular to each other; each of the word lines is connected to control gates of all the memory cells in a same row of the array; each of the bit lines is connected to drain terminals of all the memory cells in a same column; and every two memory cells adjacent to each other along a channel direction share a source terminal, the programming method characterized in that: a programming is performed by involving both of two memory cells adjacent to each other along a channel direction between two adjacent bit lines and connected in series, wherein one bit line is grounded and a high bit line programming voltage is applied to the other bit line, and the common source terminal is floating, while the control gates of the two memory cells are connected to two word lines, respectively, and different voltages are applied to the two word lines when the programming is performed.