Patent ID: 7761717

Claim:
An integrated circuit, comprising: a processor; a plurality of interfaces that provide external access to the integrated circuit, the plurality of interfaces comprising a USB interface, a JTAG interface and a parallel interface; and a non-volatile memory device partitioned into a plurality of memory portions including a first memory portion and a second memory portion, where the first memory portion includes initialization executable program instructions that are executed upon power-up of the integrated circuit, and where the second memory portion includes (i) a first password, (ii) a second password, (iii) program control register data associated with enabling or disabling of the plurality of interfaces, and (iv) executable program instructions for encrypting or decrypting data, where the first and second passwords are associated with access by a user to the executable program instructions; where bit locations of the program control register data associated with the plurality of interfaces are hardwired within the integrated circuit with interface control circuitry, such that upon a reset of the processor the bit locations of the program control register data are read by the interface control circuitry to determine which of the plurality of interfaces should be enabled based upon uniquely associated control bits in the program control register data.