Patent ID: 7119703

Claim:
A die anti-tampering sensor for protecting against tampering of integrated circuits comprising: a metal wire loop located in a metallization layer above said integrated circuits, a semiconductor load device which charges said metal wire loop to a logical ‘1’ level, a multiplicity of semiconductor devices which discharge said metal wire loop to a logical ‘0’ level at certain periodic times, a NAND logic gate, with logic inputs, placed among said integrated circuits, a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said inputs of said NAND logic gate within said integrated circuit, a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said semiconductor devices which discharge said metal wire loop to a logical ‘0’ level at certain periodic times, and an output of said NAND logic gate which goes to a logic ‘1’ and activates an alarm and security action whenever any one of said NAND inputs goes to logical ‘0’.