Patent ID: 8589729

Claim:
A data preservation device comprising: a circuit board configured to releasably engage a memory bus of a computing device; a non-volatile memory storage device electrically coupled to the circuit board; a control circuit electrically coupled to the circuit board and configured to read a data portion from the computing device and write the data portion to the non-volatile memory storage device during the occurrence of a power failure event on the computing device; an independent power supply coupled to, and included within the data preservation device and configured to power the data preservation device and at least one of a microprocessor, a memory controller, an IO controller, a cache memory, and a memory module of the computing device during the power failure event; and wherein the data preservation device is configured to be positioned within a memory module slot of the computing device; wherein the data preservation device adheres to one or more memory module standards promulgated by the JEDEC Solid State Technology Association; wherein the content of the cache memory within the computing device is first copied to one or more volatile memory devices within the computing device before being copied to the non-volatile memory storage device upon receiving an indication of the power failure; and wherein pointers used to indicate a location of the content of the cache memory within the computing device are stored in the non-volatile memory storage device.