Patent ID: 8402075

Claim:
A floating point unit comprising: a floating point adder configured to perform a floating point addition operation between a first floating point number having a first exponent and a first mantissa, and a second floating point number having a second exponent and a second mantissa; and a shifter unit coupled to the floating point adder and configured to shift the second mantissa such that the second exponent value is the same as the first exponent value; an alignment shifter coupled to the shifter unit and configured to calculate a shift value corresponding to a number of bit positions to shift the second mantissa; wherein the alignment shifter is configured to detect an overshift condition, in which the shift value is greater than or equal to a selected overshift threshold value; wherein the alignment shifter is further configured to provide an overshift indication in response to detecting the overshift condition; and wherein the selected overshift threshold value comprises a base 2 number in a range of overshift values including a minimum overshift threshold value and a maximum overshift threshold value, and which has a largest number of a consecutive of bits that are zero beginning at a least significant bit.