Patent ID: 7923810

Claim:
A semiconductor device comprising: a semiconductor substrate having first and second circuit regions at a surface thereof; a first semiconductor region in the first circuit region of the semiconductor substrate wherein a P-N junction is defined between the first semiconductor region and a bulk of the semiconductor substrate in the first circuit region; a well region in the second circuit region; a second semiconductor region in the well region of the second circuit region of the semiconductor substrate wherein a P-N junction is defined between the second semiconductor region and the well region; an insulating isolation structure in the semiconductor substrate wherein the insulating isolation structure surrounds sidewalls of the first and second semiconductor regions; an interlayer insulating layer on the first and second semiconductor regions and on the insulating isolation structure, wherein the interlayer insulating layer has a first element hole therethrough exposing a portion of the first semiconductor region and a second element hole therethrough exposing a portion of the second semiconductor region; a first semiconductor pattern in the first element hole on the exposed portion of the first semiconductor region wherein a P-N junction is defined between the first semiconductor region and a portion of the first semiconductor pattern; a second semiconductor pattern in the second element hole on the exposed portion of the second semiconductor region wherein a P-N junction is defined between the second semiconductor region and a portion of the second semiconductor pattern, wherein the well region, the second semiconductor region, and the second semiconductor pattern define portions of an active electronic element.