Patent ID: 8362523

Claim:
An integrated circuit device, comprising: a substrate having a semiconductor substrate region therein; a first semiconductor well region of first conductivity type in the semiconductor substrate region, said first semiconductor well region having a first plurality of transistor regions therein arranged in a first zig-zag pattern across the semiconductor substrate region; a second semiconductor well region of second conductivity type in the semiconductor substrate region, said second semiconductor well region having a second plurality of transistor regions therein arranged in a second zig-zag pattern across the semiconductor substrate region that is intertwined with the first zig-zag pattern; a plurality of first transistors of second conductivity type in the first plurality of transistor regions; and a plurality of second transistors of first conductivity type in the second plurality of transistors regions, said plurality of second transistors comprising at least one second transistor that shares a gate electrode with a corresponding one of the plurality of first transistors.