Patent ID: 8865539

Claim:
A method comprising: forming a first mask over a first region of a semiconductor substrate; implanting a first material into a second region of the semiconductor substrate; removing the first mask; implanting a second material into the first region and into the second region of the semiconductor substrate, the implanting steps forming a buried dielectric material in the semiconductor substrate, the buried dielectric material having a first thickness in the first region and a second thickness in the second region, the buried dielectric material having a step transitioning from the first thickness to the second thickness; annealing the semiconductor substrate; forming a shallow trench isolation structure in the semiconductor substrate overlying the buried dielectric material and aligned over the step; and forming a first transistor in the first region and aligned over the buried dielectric material with the first thickness and a second transistor in the second region and aligned over the buried dielectric material with the second thickness, the shallow trench isolation structure disposed between the first transistor and the second transistor, the forming the first transistor and the second transistor comprising: forming a gate dielectric material over the first and second regions; and removing only a portion of the gate dielectric material in the second region, the gate dielectric material thereby having a third thickness in the first region and a fourth thickness in the second region; wherein the step in the buried dielectric transitioning from the first thickness and the second thickness is disposed between the first transistor and the second transistor.