Patent ID: 7649382

Claim:
An apparatus to reduce logic swing, comprising: a level shifting device including a reference potential, configured to translate a first maximum potential of an input signal to a second maximum potential and to translate a minimum potential of the input signal to the reference potential to form a level shifted input signal, wherein the reference potential is substantially equal to a difference between the first maximum potential and the second maximum potential; a control logic generator coupled to the level shifting device configured to generate a control signal in response to the level shifted input signal, wherein a minimum potential of the control signal is substantially equal to the reference potential and a maximum potential of the control signal is substantially equal to the second maximum potential; a current source configured to provide a current to an output; and a PMOS transistor, coupled between the current source and the output, configured to couple the current to the output when the control signal is substantially equal to the reference potential and to cutoff the current to the output when the control signal is substantially equal to the second maximum potential.