Patent ID: 8420469

Claim:
A method for forming a field effect transistor (FET), the method comprising: forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions comprise silicide and are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening, wherein the silicide of the source and drain regions are exposed above the channel region by the thinning of the channel region; and forming gate spacers on the supporting material over the thinned channel region, wherein the gate spacers are in direct contact with the silicide of the source and drain regions above the thinned channel region; and forming a gate in the gate opening over the gate spacers and the thinned channel region.