Patent ID: 7895374

Claim:
A communication interface device comprising: drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus; receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus, wherein the bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment, the receive-side switching logic operable to receive both a data signal on a spare link segment or a clock signal on the spare link segment, the spare link segment selected from the at least two spare link segments, and further wherein the driver multiplexers and the receiver multiplexers are configured upon at least one of initialization and run time error recovery in response to a pattern transmitted on the bus to detect one or more defective link segments; and power management circuitry to enable a circuit corresponding to an unused link segment to be place in a low power state.