Patent ID: 7725693

Claim:
A device comprising: a processor; a first and second hardware resource associated with the processor; and a processor control unit operable to fetch an instruction to be executed in the processor; apply a first resource management policy to the first hardware resource, wherein the first resource management policy is: (i) logically associated in a computer-readable medium with a first instruction group that includes the first instruction, and (ii) selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the first instruction group in response to a previous run-time execution of the first instruction group; apply a second resource management policy to the second hardware resource, wherein the second resource management policy is: (i) logically associated in a computer-readable medium with the first instruction group that includes the first instruction, and (ii) selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the first instruction group in response to a previous run-time execution of the first instruction group such that greater than a preselected level of at least one error will occur during execution of the instruction group; compare an execution of the first execution group pursuant to the first resource management policy with an execution of the first execution group pursuant to the second resource policy to determine an optimum resource management policy; and apply the optimum resource management policy to the first hardware resource, wherein the first resource management policy and the second resource management policy can be selected as the optimum resource management policy based on the comparison.