Patent ID: 8852978

Claim:
A method of fabricating a thin film transistor, the method comprising: forming a semiconductor pattern on a substrate; forming a first insulation film, a conductive film and a metal film on the substrate including the semiconductor pattern; forming a first photoresist pattern on the metal film, the first photoresist pattern having a narrower width than that of the semiconductor pattern; forming a first metal pattern and a conductive pattern by etching the metal film and the conductive film using the first photoresist pattern as a mask; forming a source region and a drain region in the semiconductor pattern by performing a first ion injection process using the first photoresist pattern as a mask; forming a second photoresist pattern from the first photoresist pattern through an ashing process, the second photoresist pattern having a narrower width than that of the first photoresist pattern; forming a second metal pattern by etching the first metal pattern using the second photoresist pattern as a mask, wherein the second metal pattern has a narrower width than that of the second photoresist pattern, and the second metal pattern and the conductive pattern form a gate electrode; performing a process that includes removing the second photoresist pattern, forming LDD (Lightly Doped Drain) regions in the semiconductor pattern, and forming GOLDD (Gate Overlap LDD) regions in the semiconductor pattern; forming a second insulation film on the substrate including the gate electrode; and forming source and drain electrodes, which are electrically connected to the source and drain regions, respectively, on the second insulation film.