Patent ID: 8299846

Claim:
A semiconductor device, comprising: a level detecting unit configured to detect a voltage level of an internal voltage terminal based on the a target level; a first driving unit configured to pull up the voltage level of the internal voltage terminal in response to an output signal of the level detecting unit; a frequency detecting unit configured to detect a frequency of an external clock and generate a periodic driving control signal having a predefined activation period in each period varying according to the detection result of the frequency detecting unit; and a second driving unit configured to pull up the voltage level of the internal voltage terminal in response to the periodic driving control signal, regardless of a level variation of the voltage level of the internal voltage terminal, wherein the frequency detecting unit comprises: a buffer configured to buffer the external clock in response to an operation control signal; a frequency divider configured to divide an output clock of the buffer by a predefined multiple; and a detection pulse generator configured to generate the periodic driving control signal having the predefined activation pulse width at each edge of a clock output from the frequency divider.