Patent ID: 8252654

Claim:
A method for manufacturing a memory cell comprising the steps of: providing a substrate; forming a doped region with a first conductive type in the substrate near a surface of the substrate, wherein a doping concentration of the doped region is higher than that of the substrate, and the method for forming the doped region comprises steps of: forming a doped polysilicon layer having a plurality of dopants with the first conductive type therein; and performing a thermal process to drive the dopants towards an interface between the substrate and the doped polysilicon layer so as to form the doped region in the substrate; removing a portion of the substrate to define a plurality of fin structures in the substrate; forming a plurality of isolation structures among the fin structures, wherein a surface of the isolation structures is lower than a surface of the fin structures; forming a gate structure over the substrate and straddling the fin structure, wherein the gate structure comprises a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate; and forming a source/drain region with a second conductive type in the fin structure exposed by the gate structure, wherein the first conductive type is different from the second conductive type.