Patent ID: 8219941

Claim:
A non-transitory computer-readable storage medium storing instructions that when executed by a processor, cause the processor to: retrieve data including a plurality of positions of a corresponding plurality of line segments in a range pattern for modeling a defect in a first integrated circuit (IC) chip, the range pattern specifying at least one set of values comprising a maximum limit and a minimum limit of said defect relative to one of said line segments and a constraint on position of at least two of said line segments, wherein said defect in said first IC chip is a portion of a layout in said first IC chip satisfying said constraint and comprising an additional line segment at a position between the maximum limit and the minimum limit; determine a match between said range pattern and a plurality of traces formed by material in a portion of a layout of a second IC chip based on said additional line segment, said match indicative of said defect; and mark said layout of the second IC chip as being selected for re-design in said portion to avoid said defect in fabrication of said plurality of traces based on said match.