Patent ID: 8009159

Claim:
A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driver circuit; and a frame rate conversion portion, wherein: each of the plurality of pixels has: a switching element; a pixel electrode; and an opposing electrode; the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs; digital image signals are written into the one RAM, or into one of the plurality of RAMs; the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice; the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion; one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted; the digital image signals output from the data format portion are input to the source signal line driver circuit; two display signals are generated by the source signal line driver circuit; the two display signals have mutually inverted polarities; the two generated display signals are input to the pixel electrodes through the switching elements; and a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.