Patent ID: 7356792

Claim:
A method of performing verification, said method comprising: creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target; unfolding said current abstraction by a selectable depth; verifying a composite target using a satisfiability solver; and in response to determining that said verifying step has hit said composite target determining whether said composite target is unreachable; in response to determining whether said composite target is unreachable, increasing said selectable depth; in response to determining that said verifying step has hit said composite target, examining a counterexample to identify one or more reasons for said first target to be asserted, wherein said counterexample is a sequence of assignments to inputs of said current abstraction in every cycle leading up to a fail event; building one or more refinement pairs by examining said counterexample; building a second abstraction by composing said refinement pairs; porting one or more learned clauses and one or more invariants encountered during verification of said current abstraction to said second abstraction to facilitate verification of said second abstraction by said satisfiability solver by reducing a number of cases said satisfiability solver examines during said verification of said second abstraction; choosing as said current abstraction said second abstraction; and verifying said current abstraction with said satisfiability solver.