Patent ID: 7902017

Claim:
A process of forming an electronic device comprising: providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region; forming a vertically-oriented conductive region extending from the primary surface to the underlying doped region, wherein forming the vertically-oriented conductive region comprises: patterning the semiconductor layer to define a trench extending from the primary surface toward the underlying doped region; and depositing a conductive layer that substantially fills the trench; forming a horizontally-oriented doped region adjacent to the primary surface, wherein in a finished form of the electronic device, the horizontally-oriented doped region extends further in a lateral direction toward a region where a source region has been or will be formed, as compared to the vertically-oriented conductive region; depositing a first conductive layer over and electrically insulated from the vertically-oriented conductive region; etching the first conductive layer to form a conductive electrode, wherein in a finished form of the electronic device, the conductive electrode is configured to be at a substantially constant voltage when the electronic device is in a normal operating state; depositing a second conductive layer over the primary surface of the semiconductor layer, wherein depositing the second conductive layer is performed after depositing the first conductive layer; and etching the second conductive layer to form a gate electrode, wherein the electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, the horizontally-oriented doped region, and the gate electrode.