Patent ID: 8020131

Claim:
A method of implementing a circuit design for an integrated circuit, comprising: translating a behavioral description of the circuit design into a logical description based on an architecture of the integrated circuit; identifying, during the translation, a chain of flip-flops in the circuit design, the chain of flip-flops including first and second control signals; instantiating, in the logical description, a shift register for the chain of flip-flops; instantiating, in the logical description, first and second control chains of flip-flops for the first and second control signals, respectively; instantiating, in the logical description, a multiplexer configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains; and generating an implementation of the circuit design for the integrated circuit from the logical description, wherein the translating, identifying, instantiating the shift register, instantiating the first and second control chains, instantiating the multiplexer, and generating are performed by a computer.