Patent ID: 6872998

Claim:
A ferroelectric memory device comprising; a plurality of ferroelectric capacitors, each including a top electrode, a common bottom electrode and a ferroelectric film interposed therebetween; a plurality of memory cell transistors, each including first and second doped layers and a gate, each of said plurality of memory cell transistors controlling a voltage supplied to the top electrode of a corresponding ferroelectric capacitor; a first interlevel dielectric film formed over the plurality of memory cell transistors and the plurality of ferroelectric capacitors; and a plurality of interconnection layers formed on the first interlevel dielectric film, each of the plurality of interconnection layers electrically connecting a memory cell transistor to a corresponding ferroelectric capacitor; wherein, in a plan view of the ferroelectric memory device, all interconnection layers formed on the first interlevel dielectric film and electrically connecting a respective memory cell transistor to a corresponding ferroelectric capacitor, each of the interconnection layers extending over only one side of the common bottom electrode and only one side of a corresponding ton electrode, and the width of a bit line formed above a respective top electrode is smaller than the distance between the respective top electrode and an adjacent top electrode.