Patent ID: 8331757

Claim:
A time code processing apparatus that, when a first video signal in 24 frame/s progressive format is subjected to a pulldown process to be converted to a second video signal in 30 frame/s interlaced format, generates second time code values for the second video signal based on first time code values that are provided in the first video signal at intervals of a given number of frames while some time code values are selectively eliminated so as to accommodate the second video signal, the apparatus comprising: a time code reading section configured to read each of the first time code values; a phase detection section configured to detect a phase in a sequence of the pulldown process; and a time code generation section configured to use the first time code value as the second time code value when both the phase detected by said phase detection section and the first time code value obtained by said time code reading section have changed, and generate the second time code value while performing an interpolation based on the first time code value when at least one of the phase detected by said phase detection section and the first time code value obtained by said time code reading section has not changed, thereby generating continuous time code values for said video signal in 30 frame/s interlaced format when time code values are set in said video signal in 24 frame/s progressive format at intervals of a given number of frames, and one or more time code values are selectively eliminated so as to accommodate the video signal in the 30 frame/s interlaced format, wherein the time code value does not change when no frame advance has occurred because of a slow playback, wherein slow playback is when the 24p video signal is played back at a slower speed than a normal speed.