Patent ID: 7752587

Claim:
A method for designing placement locations of micro vias of a via layer of a transmission line in a multi-layer ball grid away (BGA) package for a semiconductor die, comprising: determining a target impedance value for the via layer, wherein the determined target impedance value for the layer is along a smooth impedance curve between an impedance of a bump and an impedance of a ball of a BGA; determining placement location of at least one signal via of micro vias, wherein the placement location follows design constraints of manufacturing; performing an analytical calculation to determine initial placement locations of a plurality of ground vias of the micro vias of the via layer; adjusting the placement locations of the plurality of ground vias by taking the design constraints of manufacturing into consideration; and calculating an impedance of the via layer by using a simulation tool after the placement locations of the vias have been adjusted, wherein each method operation is executed through a processor.