Patent ID: 7235473

Claim:
A semiconductor fabrication process, comprising: forming a gate stack overlying semiconductor substrate, wherein the gate stack includes a conductive gate electrode; forming source/drain regions in the semiconductor substrate laterally aligned to the gate stack; forming a hard mask overlying the gate electrode of the gate stack, wherein forming the hard mask comprises: depositing an antireflective coating (ARC) on the wafer, patterning a masking structure overlying the ARC, wherein the masking structure is aligned to the gate electrode, etching the ARC and the liner oxide to expose the source/drain regions, and stripping the masking structure and remaining portions of the ARC, wherein the hard mask comprises the portion of the liner oxide overlying the upper surface of the gate electrode; selectively forming a first silicide in the source/drain regions; removing the hard mask; and selectively forming a second silicide in upper portions of the gate electrode, wherein the first silicide and the second silicide are different.