Patent ID: 7134120

Claim:
A reconfigurable computer system including control-flow dataflow pipelined loop structures, the system comprising: a multi-adaptive processor, wherein the multi-adaptive processor includes field programmable gate arrays; and a multi-adaptive processor compiler capable of creating code executable on the multi-adaptive processor, wherein the multi-adaptive processor compiler creates code forming a pipelined loop structure, the pipelined loop structure comprising; a loop body that processes an input value to generate an output value in successive iterations of the loop body, wherein the output value is captured by a circulate node coupled to the loop body; a loop valid node coupled to the loop body that determines a final loop iteration; and an output value storage node coupled to the circulate node, wherein the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred preserving a final loop value based on the final loop iteration.