Patent ID: 8269271

Claim:
A semiconductor device comprising: a FinFET (Fin Field Effect Transistor) configured to be provided on a chip; and a PlanarFET (Planar Field Effect Transistor) configured to be provided on said chip, wherein a second gate insulating layer of said PlanarFET is thicker than a first gate insulating layer of said FinFET, wherein said second, gate insulating layer exists under a second side wall provided on a side surface of a second gate electrode of said PlanarFET, wherein said first gate insulating layer does not exist under a first side wall provided on a side surface of a first gate electrode of said FinFET, wherein a gate length of said PlanarFET is longer than a gate length of said FinFET, wherein said PlanarFET includes: a second offset spacer configured to be provided between said second gate electrode and said second side wall, and wherein said FinFET includes: a first offset spacer configured to be provided between said first gate electrode and said first side wall.