Patent ID: 8756479

Claim:
An apparatus, comprising: a super-parity-check matrix, embodied on non-transitory computer-readable medium, the super matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix, the super-parity-check matrix coupled to a high throughput LDPC decoder configured to process ny codeword bits in a single time unit and a low throughput LDPC decoder configured to process no more than y codeword bits in the single time unit, wherein the super-parity-check matrix comprises n parity check matrices; wherein the parity check matrices comprise x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements, such that the super-parity-check matrix comprises nx rows corresponding to nx check node processing elements and ny columns corresponding to ny bit node processing elements; and further wherein n, x, and y are selected so that ny codeword bits corresponding to a row of the super-parity-check matrix can be processed in the single time unit by the high throughput decoder and y codeword bits corresponding to a row of a parity check matrix can be processed in the single time unit by the low throughput decoder.