Patent ID: 8879297

Claim:
A semiconductor device comprising: a memory mat having a plurality of bit lines each extending in a first direction, a plurality of word each lines extending in a second direction crossing to the first direction, and a plurality of memory cells arranged respectively at intersections of the bit lines and the word lines; a plurality of sense amplifiers coupled respectively to the bit lines, the sense amplifiers being provided in a sense amplifier area that is adjacent to the memory mat in the first direction; a plurality of column selection lines extending in the first direction as a first wiring layer; a local I/O line extending in the second direction as a second wiring layer; a plurality of main I/O lines extending in the first direction, the main I/O lines being provided as a third wiring layer over the sense amplifier area and provided as the first wiring layer over the memory mat; and a power-supply line extending in the first direction as the third wiring layer, a part of the power-supply line overlapping with the main I/O lines provided over the memory mat.