Patent ID: 7485517

Claim:
A method for fabricating a semiconductor device, comprising: providing a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon; forming a first stress layer to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor; removing the first stress layer on the core second-type MOS transistor to reserve the first stress layer on the first-type MOS transistor and the I/O second-type MOS transistor; and forming a second stress layer on the core second-type MOS transistor and the first stress layer on the I/O second-type MOS transistor and not on the first stress layer formed on the first-type MOS transistor, wherein one of the first and the second stress layers is a tensile stress layer and the other is a compressive stress layer.