Patent ID: 8564347

Claim:
A phase detector for use in a circuit comprising: a first series of delay gates receiving a system clock signal; a second series of delay gates receiving a substantially 270 degree phase shifted clock signal; a third series of delay gates receiving a substantially 540 degree phase shifted clock signal; a first flip-flop circuit receiving a delayed system clock signal and a second order delayed signal of the substantially 270 degree phase shifted clock signal; a second flip-flop circuit receiving the delayed system clock and a second order delayed signal of the substantially 540 degree phase shifted clock signal; a NOR gate receiving outputs from the first flip-flop circuit and second flip-flop circuit and generating an up control signal and a down control signal, wherein the phase detector is an edge-triggered phase detector that locks when there is a substantially 270 degree phase difference between the rising edges of the system clock input and the substantially 270 degree phase shifted clock signal.