Patent ID: 7991007

Claim:
A hardware packets reassembly apparatus, comprising: an ingress unit configured to receive a plurality of fragments corresponding to a data packet, and configured to output forwarding control information associated with the plurality of fragments; an en-queue unit configured to store the forwarding control information of each fragment from the plurality of fragments, and link related fragments from the plurality of fragments based on the forwarding control information, the en-queue unit configured to store a descriptor of the data packet in a packet descriptor buffer in response to all fragments from the data packet being received in a sequential order, the en-queue unit configured to drop out-of-order fragments that are received in an order different from the sequential order until all fragments from the data packet are received in the sequential order; a de-queue unit configured to schedule transmission of the plurality of fragments as a single unit based on the stored descriptor and based on a class of service, and configured to retrieve each fragment from the plurality of fragments based on the stored descriptor of the data packet, the descriptor including a pointer for each fragment from the plurality of fragments and the forwarding control information; and an egress unit configured to assemble the plurality of fragments corresponding to the data packet into a full data packet.