Patent ID: 8921227

Claim:
A method of manufacturing a semiconductor device assembly, comprising: a step of forming a lift-off layer and a semiconductor layer in this order on a growth substrate; a step of partially removing the semiconductor layer to form grooves in the bottom of which the growth substrate or the lift-off layer is partially exposed, thereby forming a plurality of separate semiconductor structures; a plating step of forming a conductive support for integrally supporting the plurality of the semiconductor structures by plating; and a chemical lift-off step of separating the growth substrate from the plurality of semiconductor structures by removing the lift-off layer using a given etchant, wherein the plating step is performed such that a first metal which can be dissolved in the etchant is encapsulated in a second metal which are not dissolved in the etchant in the conductive support, and through-holes communicating with the grooves are formed in the second metal, and the etchant is supplied to the grooves through the though holes in the chemical lift-off step.