Patent ID: 6900655

Claim:
A method of inspecting integrated circuits on a circuit substrate, said circuit substrate having a plurality of integrated circuits arrayed thereon, each of the integrated circuits having a plurality of electrode pads, comprising: a plurality of common interconnections connectable in common to the electrode pads of the integrated circuits; and a connection control circuit for selectively connecting and disconnecting the electrode pads and the common interconnect ions corresponding thereto, wherein the method comprises the steps of: individually inspecting the integrated circuits to determine whether the integrated circuits are acceptable or not, using said electrode pads, while the electrode pads of the integrated circuits are not being connected to said common interconnections corresponding thereto; connecting said electrode pads of the integrated circuits which have been judged as being acceptable to said common interconnections corresponding thereto; applying uniform stresses from said common interconnections to said integrated circuits; disconnecting said electrode pads from said common interconnections; and individually inspecting said integrated circuits which have been judged as being acceptable, using said electrode pads.