Patent ID: 7728381

Claim:
A semiconductor device comprising: a substrate comprising a first device region and a second device region; an isolation structure within the substrate, wherein the isolation structure comprises an isolation trench within the substrate, a first insulation layer on a bottom and a sidewall of the isolation trench and a second insulation layer on the first insulation layer and filling the isolation trench; a first active region within the first device region and a second active region within the second device region, wherein the first and second active regions are defined by the isolation structure; and a plurality of gate structures extending over the first and second active regions and the isolation structure in the first and second device regions, wherein a first portion of the first active region is a fin-shaped active region and the second active region is a substantially planar active region, wherein an uppermost portion of the first insulation layer within the isolation trench is lower than an uppermost portion of the second insulation layer within the isolation trench in the first device region and in the second device region, and wherein upper surfaces of the first and second active regions are substantially coplanar with an upper surface of the isolation structure.