Patent ID: 8370778

Claim:
A computer implemented method for verifying that a power distribution system meets a functional, timing, or power specification, comprising: using at least one processor that is to perform a process, the process comprising: performing hierarchical verification for a gate level or a higher abstraction level electronic design of the power distribution system with transistor level resolution without a need for a user provided constraint for the hierarchical verification, the act of performing the hierarchical verification comprising: performing the hierarchical verification at a first hierarchical level of the gate level electronic design; processing an output of the hierarchical verification at the first hierarchical level to generate a first power distribution system model for the gate level electronic design that is verified; and performing the hierarchical verification for a second hierarchical level by using the first power distribution system model, wherein the at least one processor that is to perform the hierarchical verification is free to traverse between the first hierarchical level and the second hierarchical level in both a top-down manner and a bottom-up manner to perform the hierarchical verification for different hierarchical levels in the gate level or a higher abstraction level electronic design.