Patent ID: 8258567

Claim:
An array of non-volatile memory cells including: a semiconductor body; a first memory-transistor well disposed within the semiconductor body and having a region of higher dopant concentration at a periphery thereof; a first switch-transistor well disposed within the semiconductor body to a first side of the first memory-transistor well, the first switch-transistor well having a region of higher dopant concentration at a periphery thereof; a first isolation region formed in the semiconductor body and surrounding the first memory-transistor well and having a doping concentration different from the semiconductor body; a first underlying deeper isolation region formed in the semiconductor body beneath the first isolation region and having a different dopant concentration from the semiconductor body and the first isolation region; a second isolation region formed in the semiconductor body and surrounding the first switch-transistor well and having a doping concentration different from the semiconductor body; a second underlying deeper isolation region formed in the semiconductor body beneath the second isolation region and having a different dopant concentration from the semiconductor body and the second isolation region; a first plurality of memory-transistors formed within the first memory-transistor well, each including spaced-apart source and drain regions; a first plurality of switch-transistors formed within the first switch-transistor well, each associated with one of the first plurality of memory-transistors and including spaced-apart source and drain regions; a floating gate associated with each memory-transistor in the first plurality of memory transistors, each floating gate insulated from and self-aligned with the source and drain regions of the memory-transistor and the one of the first plurality of switch-transistors with which it is associated; and a control gate associated with each memory-transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the memory-transistor and the switch-transistor with which it is associated.