Patent ID: 7102190

Claim:
A structure for flash memory cells, comprising: a semiconductor region within a substrate; first isolation regions, separating cells, and second isolation regions, separating programming bit line channel regions of a cell from reading bit line channel regions of a cell, delineating active regions contained within said semiconductor region; a conductive floating gate, for each cell, having a first floating gate portion disposed over the active region in the programming bit line channel region of a cell and a second floating gate portion disposed over the active region in the reading bit line channel region of the cell, both said first and said second floating gate portions being separated from said active regions by a floating gate insulator layer disposed over said active regions, and a third floating gate portion passing over said second isolation region to connect said first floating gate portion and second floating gate portion, wherein width of said first floating gate portion is narrower than width of said second floating gate portion; a conductive control gate separated from said floating gate by an intergate insulator layer and from said semiconductor region by a conirol gate insulator layer and having a first control gate portion entirely disposed over said first floating gate portion, where said first floating gate portion completely covers the space between a first source region and a first drain region, having a second control gate portion disposed over said second floating gate portion, where said second floating gate portion does not extend all the way from a second source region to second drain region, said second control gate region completing the covering of the space between said second source region and said second drain region and having a third control gate portion disposed over said third floating gate portion and connecting said first control gate portion and second control gate portion; a covering insulator layer with a programming bit line channel contact line disposed over said covering insulator layer and connecting to said first drain region through said covering insulator layer and a reading bit line channel contact line disposed over said covering insulator layer and connecting to said second drain region through said covering insulator layer.