Patent ID: 7680124

Claim:
A processing device for use in a communication system, the device comprising: scheduling circuitry configured to schedule data blocks for transmission from a plurality of transmission elements in timeslots of a frame, utilizing at least a weight table and a mapping table; the weight table comprising a plurality of entries, each of the entries identifying a particular one of the transmission elements; the mapping table comprising at least one entry specifying a mapping between a particular timeslot of the frame and an entry of the weight table; the scheduling circuitry being further configured to determine a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry and utilizing a resultant value to access the weight table; and memory circuitry associated with the scheduling circuitry and configurable to store at least a portion of at least one of the weight table and the mapping table; wherein the scheduling circuitry utilizes the resultant value, determined by accessing a corresponding mapping table entry, to identify a first entry of the weight table that is larger than or equal to the resultant value, said entry of the weight table identifying a particular one of the transmission elements.