Patent ID: 7071513

Claim:
A method of forming an integrated circuit structure that includes at least one CMOS circuit element and at least one DMOS circuit element that is electrically connected to the CMOS circuit element, the method comprises: forming a layer of epitaxial silicon having a first conductivity type on a crystalline silicon substrate having a 100 crystalline orientation; forming a trench matrix in an upper surface of the epitaxial layer to define a plurality of spaced-apart polygonal trench source cell regions in the epitaxial layer, vertical sidewalls of the trench matrix being formed at an orientation of 45° with respect to the 100 crystalline orientation of the crystalline silicon substrate; forming conductive material in the trench matrix to provide a conductive gate electrode for the DMOS circuit element; and for each polygonal trench source cell region, providing in the upper surface of the epitaxial layer (i) a source diffusion region having a second conductivity type that is opposite the first conductivity type, (ii) a body region having the first conductivity type, and (iii) a drain region having the second conductivity type, said body region being disposed between said source region and the drain region to provide a DMOS circuit element channel region between said source and drain regions.