Patent ID: 8193586

Claim:
A semiconductor device comprising: a semiconductor substrate; and a transistor formed in the substrate, the transistor including: a gate stack having a high-k dielectric and metal gate; a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, wherein the sealing layer is formed of a material having a first component and a second component such that a ratio of the first and second components changes from the inner edge to the outer edge of the sealing layer, the first and second components being different from each other and the first and second components both being present at both the inner edge and the outer edge of the sealing layer; a spacer formed on the outer edge of the sealing layer; and a source/drain region disposed at each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region having an inner edge and an opposing outer edge, the inner edge of the LDD region being aligned with the outer edge of the sealing layer such that the inner edge of the LDD region is positioned closer to the gate stack than the outer edge of the LDD region.