Patent ID: 7572700

Claim:
A method for manufacturing EEPROM, comprising: forming a first semiconductor and a second semiconductor on a substrate, wherein the first semiconductor and the second semiconductor are isolated by a trench; forming a first dielectric layer and a second dielectric layer on the first semiconductor and the second semiconductor, respectively; defining a first source region and a first drain region on the first semiconductor and processing a first ion-doping to the first source region and the first drain region; processing a second ion-doping to the second semiconductor so as to form an ion-doped region; forming a first floating gate and a second floating gate on the first dielectric layer and the second dielectric layer, respectively; forming an inter-layer dielectric layer on the substrate, the first semiconductor, the second semiconductor, the first floating gate and the second floating gate; forming lead apertures through the inter-layer dielectric layer so as to expose a portion of the first floating gate and the second floating gate; and forming a metal layer on the inter-layer dielectric layer and in interiors of the lead apertures so as to establish electric connection between the first floating gate and the second floating gate.