Patent ID: 8081527

Claim:
A device comprising: a random access memory device configured to store data; and a memory controller connected to the memory device via a plurality of data lines and a strobe line, the memory controller including: a plurality of adjustable delay circuits, each of the plurality of adjustable delay circuits being associated with one of the data lines and the strobe line, and inserting an adjustable amount of delay into a signal destined to or received from the one of the data lines or the strobe line, each of the plurality of adjustable delay circuits including: a write delay sub-circuit configured to delay a data signal being transmitted to the memory device, and a read delay sub-circuit configured to delay the data signal after the data signal is received from the memory device, the read delay sub-circuit further including: a plurality of taps located between serially connected delay elements, and a pair of buffers connected to each of the plurality of taps, and control logic to determine the delay amount for each of the plurality of adjustable delay circuits, the delay amount being determined to reduce timing skew between the data lines and the strobe line.