Patent ID: 8741719

Claim:
A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising: forming a thermally grown oxygen-containing gate dielectric over a semiconductor layer and a select gate over the thermally grown oxygen-containing gate dielectric in the NVM region while protecting the logic region; forming a high-k gate dielectric over the semiconductor layer, a barrier layer over the high-k gate dielectric, and a dummy gate over the barrier layer in the logic region, while protecting the NVM region; forming a first dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the first dielectric layer surrounds the select gate and thermally grown oxygen-containing gate dielectric in the NVM region and surrounds the dummy gate, the barrier layer, and the high-k gate dielectric in the logic region; removing the first dielectric layer from the NVM region while protecting the first dielectric layer in the logic region; forming a charge storage layer over the semiconductor layer and select gate in the NVM region, and over the first dielectric layer and dummy gate in the logic region; removing the charge storage layer from the logic region; removing the dummy gate in the logic region which results in an opening in the logic region; forming a gate layer over the charge storage layer in the NVM region and over the first dielectric layer and in the opening in the logic region; removing a top portion of the gate layer in the NVM region and the logic region, wherein a remaining portion of the gate layer in the opening and the barrier layer together form a logic gate in the logic region; and patterning a remaining portion of the gate layer in the NVM region to form a control gate in the NVM region that is laterally adjacent the select gate, wherein a top surface of the control gate is substantially coplanar with a top surface of the logic gate.