Patent ID: 7608495

Claim:
A transistor forming method comprising: forming an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate; removing some of semiconductor material of the island and forming a trench defining a fin of semiconductor material in the island, the fin having a top, opposing sidewalls, and opposing endwalls and a portion of the island remaining at a bottom of the trench; after forming the trench, forming a dielectric spacer in the trench over the bottom, the opposing sidewalls, and the opposing endwalls and laterally surrounding the fin, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness; forming line openings through the spacer and exposing through the line openings some of the semiconductor material of the island at the bottom of the trench and some of the semiconductor material of the opposing sidewalls of the fin; forming a gate line on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin; and in operational association with the gate line, forming source/drain regions in the fin.