Patent ID: 7029952

Claim:
A method of fabricating a semiconductor package containing an integrated circuit chip that has electrical connection regions on an assembly face, said method comprising the steps of: providing a first multilayer plate that includes through-holes and an assembly face coated with an adhesive layer, the trough-holes passing through the first plate and being geometrically distributed based on the distribution of the electrical connection regions of the chip; providing a second plate that includes an assembly face and a recess in the assembly face, the recess being capable of receiving the chip; placing the first and second plates together such that the chip is positioned on the assembly face of the first plate with the electrical connection regions of the chip facing the through-holes of the first plate, and such that the assembly face of the second plate is on the assembly face of the first place with the chip engaged in the recess of the second plate; and exerting pressure in a direction in which the first and second plates come together so that the chip is sandwiched between the assembly face of the first plate and a bottom of the recess of the the second plate and so that the adhesive layer is compressed between the assembly faces of the first and second plates and between the assembly face of the first plate and the assembly face of the chip, so as to activate the adhesive layer to fasten the first and second plates.