Patent ID: 7769121

Claim:
A circuit for data communications, the circuit comprising: a phase detector configured to receive an input data signal and a recovered clock signal and to generate a phase error signal comprising pulses having an amplitude indicative of a phase relationship between the recovered clock signal and a reference clock embedded in the input data signal; a clock circuit configured to generate the recovered clock signal based on the phase error signal; and a pulse shaping logic configured to adjust an amplitude of a pulse of the phase error signal to between the amplitude of the pulse of the phase error signal and zero based on a relationship between a value of the pulse of the phase error signal and a value of a pulse of a sample of the phase error signal; wherein the pulse shaping logic comprises a first circuit configured to output a plurality of binary signals based on the phase error signal and the sample of the phase error signal, and a second circuit comprising a plurality of current sources and sinks, the current sources and sinks being controllable using the binary signals.