Patent ID: 8351254

Claim:
A semiconductor device comprising nonvolatile memory cells arranged over a semiconductor substrate, wherein each of the nonvolatile memory cells comprises: an n-type first semiconductor region formed in the main surface of the semiconductor substrate; an n-type second semiconductor region formed in the main surface of the semiconductor substrate and in a place different from the place of the first semiconductor region; a selection transistor formed in the first semiconductor region; and an electric charge storage portion having a floating gate electrode and a p-type third semiconductor region, wherein the floating gate electrode is placed over the semiconductor substrate so that the floating gate electrode overlaps with part of the first semiconductor region and the second semiconductor region when the main surface of the semiconductor substrate is viewed in a plane, wherein the third semiconductor region is formed beside and under the floating gate electrode in the first semiconductor region and is so placed that the third semiconductor region partly overlaps with an end of the floating gate electrode when the main surface of the semiconductor substrate is viewed in a plane, wherein each of the nonvolatile memory cells is an element that accumulates electric charges in the floating gate electrode and thereby stores information, and wherein memory information is erased by applying positive voltage to the second semiconductor region to discharge electrons accumulated in the floating gate electrode to the second semiconductor region.