Patent ID: 7638871

Claim:
A semiconductor device formed on a semiconductor substrate comprising: a first memory array formed in a first region, the first memory array including a plurality of first word lines, a plurality of first bit lines across the plurality of first word lines, and a plurality of memory cells arranged at predetermined intersections of the plurality of first word lines and the plurality of first bit lines; a second memory array formed in a second region, the second memory array including a plurality of second word lines, a plurality of second bit lines across the plurality of second word lines, and a plurality of memory cells arranged at predetermined intersections of the plurality of second word lines and the plurality of second bit lines; a plurality of address input pads formed in a third region; and wherein the first region, the third region, and the second region are sequentially arranged in a first direction, wherein the plurality of address input pads are arranged between a center axis of the first direction of the semiconductor substrate and the first region, and wherein no address input pads are arranged between the center axis of the first direction of the semiconductor substrate and the second region.