Patent ID: 8452553

Claim:
A device, the device comprises: a processor; an interface adapted to receive a test vector and to output a test response, wherein the test vector comprises a first group of signals that comprises idle signals and at least one information frame and a second group of signals that comprises timing signals and data signals, wherein a location in time of the at least one information frame with respect to the idle signals of the first group in the test vector is shifted as compared to a location in time of a previous test vector's corresponding at least one information frame with respect to its idle signals, wherein the location in time of the at least one information within the first group of signals does not affect locations in time of the second group of signals with respect to a beginning of the first group of signals; and a receiver, coupled to the interface and to the processor, wherein the receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction; wherein the device is adapted to send the at least one instruction to at least one instruction buffer; wherein the processor is adapted to execute the at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide the test response.