Patent ID: 6954371

Claim:
A semiconductor integrated circuit device having a memory circuit comprising: a memory array including a plurality of memory cells having stack-type capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines; a sense amplifier which is provided corresponding to a pair of bit lines and senses and amplifies stored information of a memory cell of the plurality of memory cells which is read to one bit line in response to a reference voltage formed in a dummy cell, of a plurality of dummy cells, which is connected to another bit line; and a precharge circuit which supplies a precharge voltage of high level or low level corresponding to an operational voltage of the sense amplifier to the bit lines, wherein the plurality of dummy cells have the same structure as the plurality of memory cells and are formed at crossing points of dummy cell word lines and the bit lines, the plurality of dummy cells being provided at the outside of the memory array, and MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage are provided to storage nodes of the stack-type capacitors of the dummy cells, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.