Patent ID: 8631291

Claim:
A semiconductor device comprising: a clock control unit configured to receive an external test clock signal in a boundary scan test mode and generate a boundary test clock signal during the boundary scan test mode; and a plurality of latches configured to form a boundary scan path to sequentially output the plurality of stored data in the boundary scan test mode in response to the boundary test clock signal, wherein the clock control unit comprises: a clock buffer configured to buffer the external test clock signal in response to a scan test entry signal indicating an entry/exit of the boundary scan test mode and output the buffered external test clock signal as an output clock signal; and a clock transmission control signal generator configured to activate the clock transmission control signal at an activation transitioning point of the scan test entry signal and deactivate the clock transmission control signal at the later transitioning point between a deactivation transitioning point of the scan test entry signal and a deactivation transitioning point of the output clock signal of the clock buffer.