Patent ID: 7434005

Claim:
A processor for controlling a bus access device that reads out data from a main memory via a bus and for transferring the readout data to a temporary memory, comprising: a first acquiring device configured to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquired access hint information is acquired from an outside device; a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device; an identifying device configured to monitor a data transfer instruction to the bus access device and to identify data access of the data when an address of the data transfer instruction is equal to the start address of the access hint information; a determining device configured to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including at least one of: the data access interval divided by a clock speed of the processor; a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access; or a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and a first management device configured to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of the data access of the data.