Patent ID: 7380220

Claim:
A method for implementing dummy fill in an electronic circuit design of an integrated circuit, comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.