Patent ID: 7113756

Claim:
A mixer circuit comprising: a first stage including first and second transmission gates coupled with one another; a second stage including third and fourth transmission gates coupled with one another; first and second local oscillator signal terminals coupled with the first and second stages such that, in operation, the first and fourth transmission gates operate substantially in phase with one another and the second and third transmission gates operate substantially in phase with one another; first and second mixed signal terminals, the first mixed signal terminal being coupled with the first and third transmission gates and the second mixed signal terminal being coupled with the second and fourth transmission gates; first and second baseband signal terminals, the first baseband signal terminal being coupled with the first and second transmission gates and the second baseband signal terminal being coupled with the third and fourth transmission gates; a first bias-voltage terminal coupled with a transistor gate of a n-type transistor of each of the first, second, third and fourth transmission gates, the first bias-voltage terminal, in operation, receiving a first DC bias voltage that is a fraction of a nominal threshold voltage of the n-type transistors of the first, second, third and fourth transmission gates; and a second bias-voltage terminal coupled with a transistor gate of a p-type transistor of each of the first, second, third and fourth transmission gates, the second bias-voltage terminal, in operation, receiving a second DC bias voltage that is a fraction of a nominal threshold voltage of the p-type transistors of the first, second, third and fourth transmission gates.