Patent ID: 7779193

Claim:
An apparatus comprising: a processor; a memory accessible by the processor; and a logic interface coupled between the processor and the memory, the logic interface to enable access to the memory via a high-speed peripheral Input/Output (I/O) interface upon receiving an indication that a state of an external connector has transitioned from a non-active state to an active state, the indication that the state of the connector is active is based on a state of a signal received from a docking station, the high-speed peripheral I/O interface is located in the docking station, the processor to operate at a low frequency and the logic interface to allow an external host to control transfer of data directly to/from the memory via the high speed peripheral I/O interface at a faster rate than the rate at which data is stored in memory by the processor and to enable exclusive access to the memory by either the processor or the external host via the high-speed peripheral I/O interface.