Patent ID: 7869279

Claim:
A memory device, comprising: a p-doped substrate; a plurality of electrically-conductive bit lines extending along a bit line direction; a plurality of electrically-conductive word lines extending along a word line direction; a plurality of electrically-conductive erase lines extending along said word line direction; and a plurality of memory cells arranged respectively along said bit lines and said word lines, wherein each memory cell comprises: a program PMOS transistor including a first gate, and first and second P+ regions formed within an n-doped well, wherein said first P+ region is electrically connected to a corresponding bit line; an access PMOS transistor including a second gate, and third and fourth P+ regions formed within said n-doped well, wherein said third P+ region is electrically connected to said second P+ region of said program PMOS transistor, and said second gate is electrically connected to a corresponding word line; and an n-doped erase pocket including a third gate, and first and second N+ regions electrically connected to a corresponding erase line, wherein said third gate is electrically connected to said first gate of said program PMOS transistor to form a floating gate, wherein said first and second N+ regions of said n-doped erase pocket are formed directly within said p-substrate.