Patent ID: 7562271

Claim:
A system comprising: an integrated circuit buffer device including: a first interface to receive write data and control information that indicates a write operation; a second interface to convey the write data and the control information; and a register to store a value that indicates a number of integrated circuit memory devices to receive, in response to the control information, the write data; a first integrated circuit memory device to store a first portion of the write data; a first signal path coupled to the second interface and the first integrated circuit memory device, the first signal path to convey the first portion of the write data from the integrated circuit buffer device to the first integrated circuit memory device; a second integrated circuit memory device to store a second portion of the write data; a second signal path coupled to the second interface and the second integrated circuit memory device, the second signal path to convey the second portion of the write data from the integrated circuit buffer device to the second integrated circuit memory device; and a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.