Patent ID: 8018272

Claim:
A filter circuit, comprising: a flying capacitor coupled to receive an input signal at an input terminal to generate a filtered signal at an output terminal, wherein the flying capacitor maintains polarity when switching from the input terminal to the output terminal, the polarity of which is reversed when switching from the output terminal to the input terminal, and the flying capacitor switches based on clock signals provided for clock inputs on the flying capacitor; and a capacitor that is connected between the input terminal and the output terminal of the flying capacitor to provide steep attenuation characteristics of the filter circuit after cut-off frequency, wherein the flying capacitor is switched from the input terminal to the output terminal with a delay of J clocks, J being a natural number equal to or greater than 1, of a clock cycle input to the flying capacitor after the switching from the output terminal to the input terminal, and the flying capacitor is switched from the output terminal to the input terminal with a delay of K clocks, K being a natural number of equal to or greater than 1 and not equal to J, of the clock cycle after the switching from the input terminal to the output terminal.