Patent ID: 7281179

Claim:
A method of controlling an input signal of a memory device according to a test mode, the method comprising: determining whether the memory device is in a first test mode or in a second test mode; receiving the input signal through an input pin, in response to a control signal, when the memory device is in a first test mode; separating the input signal received through the input pin into a data component and an address component in response to a mode signal when the memory device is in a first test mode; receiving the input signal through the input pin and an inverting input pin, in response to the control signal, when the memory device is in a second test mode; separating the address component from the input signal received through the input pin and separating the data component from the input signal received through the inverting input pin, in response to the mode signal, when the memory device is in a second test mode; and, applying the separated data component and address component to the memory core.