Patent ID: 8877585

Claim:
A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a high voltage portion, a medium voltage portion, and a logic portion, comprising: growing a first oxide on a major surface of the substrate in the NVM portion, the high voltage portion, the medium voltage portion, and logic portion; depositing a first conductive layer over the first oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion; patterning and etching the first conductive layer to expose the high voltage portion and the medium voltage portion; growing a second oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion; masking the high voltage portion; etching the second oxide from the NVM portion, medium voltage portion, and the logic portion while the high voltage portion is masked; growing a third oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion; masking the high voltage portion and the medium voltage portion; etching the third oxide and the first conductive layer in the NVM portion and the logic portion while the high voltage portion and the medium voltage portion remain masked; growing a fourth oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion; fabricating a memory cell requiring high voltage during operation in the NVM portion, the fabricating including using a protective layer over the high voltage portion, the medium voltage portion, and the logic portion when performing an implant in a second conductive layer in the NVM portion; removing the protective layer over the high voltage portion, the medium voltage portion, and the logic portion; patterning transistor gates in the high voltage portion and the medium voltage portion; depositing a protective mask in the NVM portion, the high voltage portion, and the medium voltage portion; and forming a logic device in the logic portion while the protective mask remains in the NVM portion, the high voltage portion, and the medium voltage portion.