Patent ID: 8018785

Claim:
A semiconductor device comprising: a plurality of static memory cells arranged in rows and columns, each memory cell including first and second load transistors, a first drive transistor coupled to the first load transistor at a first storage node, a second drive transistor coupled to the second load transistor at a second storage node, a first access transistor coupled to the first storage node and a second access transistor coupled to the second storage node; a plurality of word lines provided corresponding to the rows, respectively, each word line coupled to the first and second access transistors of the memory cells in the corresponding row; a plurality of bit line pairs provided corresponding to the columns, respectively, each bit line pair coupled to the first and second access transistors of the memory cells in the corresponding column; a plurality of word line drivers coupled to the plurality of word lines, respectively, each word line driver driving the word line coupled thereto to a selected state; a driver power supply line coupled commonly to the plurality of word line drivers and applying a driver power supply voltage to the plurality of word line drivers as respective operation voltages thereof; a driver power supply circuit receiving a power supply voltage, which is higher than the driver power supply voltage, on a main power supply node and providing the driver power supply line with the drive power supply voltage, the driver power supply circuit including: a resistance element coupled between the main power supply node and a couple node, and applying a current flowing from the main power supply node to the couple node, and a pull-down circuit coupled between the couple node and a ground node, and applying a current from the couple node to a ground node to step down a voltage on the couple node from the power supply voltage, the driver power supply circuit producing the driver power supply voltage based on the couple node.