Patent ID: 7579859

Claim:
A method of determining a time dependent electrical breakdown characteristic of a dielectric layer in a semiconductor device comprising: providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor; performing a first linear regression fit on data representing a logarithm of a source/drain current density distribution and data representing a logarithm of voltages applied on said samples; performing a second linear regression fit on data representing a logarithm of a substrate current density distribution and the data representing the logarithm of voltages applied on said samples; performing a third linear regression fit on data representing a logarithm of a dielectric layer lifetime distribution and second data representing a logarithm of the source/drain current density distribution and the substrate current density distribution on said samples; deriving, from said first, second, and third linear regression fits, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon; and using said model to determine dielectric layer lifetime at a pre-determined operating gate voltage.