Patent ID: 8659457

Claim:
A self-calibrating digital-to-analog converter (DAC), comprising: at least one DAC core operable to receive digital data words and clock pulses and produce an analog output having at least one impairment; an analog function block coupled to said at least one DAC core and operable to receive and make measurements of said at least one impairment; an analog-to-digital converter (ADC) coupled to said analog function block and operable to digitize said measurements during a calibration phase of operation of said self-calibrating DAC, said ADC operating at a sampling rate that is substantially lower than the DAC's clocking rate; and a digital controller coupled to said at least one DAC core and said ADC and operable to employ said measurements to adjust at least one of said digital data words and said clock pulses to mitigate the effects of said at least one impairment by adjusting either a timing, duration, or combination thereof, of said at least one of said clock pulses in accordance with at least a remainder of a predicted error.