Patent ID: 8898504

Claim:
A communications mechanism for communicating between digital data devices, comprising: a first plurality of parallel lines supporting a parallel communications link for communicating data in a first direction from a first digital data device to a second digital data device; a calibration mechanism for periodically recalibrating each line of said first plurality of parallel lines; a switching mechanism coupled to said first plurality of parallel lines for selectively enabling each line of said first plurality of parallel lines to carry functional data; said communications mechanism supporting at least a first mode of operation wherein, with respect to each line of a first subset of said first plurality of parallel lines, at least some respective circuitry required for transmission of functional data in the respective line is powered down during respective time intervals between calibration of the respective line, said first subset containing at least one line of said first plurality of parallel lines and fewer than all of said first plurality of parallel lines, wherein corresponding respective circuitry required for transmission of functional data in each line of said first plurality of parallel lines not in said first subset is not powered down.