Patent ID: 6906566

Claim:
A delay-locked loop, comprising: a variable delay circuit for receiving an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit controlling the value of the delay responsive to a delay control signal; a fixed delay line that generates a feedback clock signal in response to the delayed clock signal, the feedback clock signal having a fixed delay relative to the delayed clock signal; a rising-edge phase detector coupled to receive the feedback clock signal and the input clock signal, and operable to generate a rising-edge delay control signal responsive to a detected phase between rising-edges of the feedback and input clock signals; a falling-edge phase detector coupled to receive the feedback clock signal and the input clock signal, and operable to generate a falling-edge delay control signal responsive to a detected phase between falling-edges of the feedback and input clock signals; and a delay controller coupled to the phase detectors and operable to develop the delay control signal responsive to the rising- and falling-edge delay control signals.