Patent ID: 8913632

Claim:
A method of synchronizing the frequency of a slave clock in a slave device to a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the time of sending of said first message; b) extracting said first time-stamp from said first message and initializing a counter in the slave device which counts an output of said slave clock; c) receiving in the slave device a second message from said master device having a second time-stamp, which is a time-stamp of said master clock indicating the time of sending said second message, and reading the value of said counter at the time of receipt of said second message; d) extracting said second time-stamp from said second message; e) determining an error signal which is representative of the difference between said value of the counter and the difference between said first and second time-stamps; and f) adjusting the frequency of said slave clock based on said error signal.