Patent ID: 7777334

Claim:
A semiconductor device comprising: a semiconductor layer including an element formation region, a first isolation region and a second isolation region which is away from the first isolation region; a first element formed in the element formation region; an interlayer dielectric layer formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric layer; a passivation layer formed above the electrode pad and having an opening which exposes at least a part of the electrode pad; and a bump formed in the opening and covering at least a part of the first element when viewed from a top side, the bump having a rectangular planar shape having a short side and a long side when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line located directly below a first edge of the short side of the bump, the second isolation region completely overlapping with the first line, the element formation region being not formed between the first isolation region and the second isolation region.