Patent ID: 8451672

Claim:
A semiconductor storage device comprising: a word line communicating with a memory cell, the memory cell comprising a first storage node and a second storage node that are configured to complementarily store data; a first bit line and a second bit line, wherein the first bit line is configured to transmit data to or from the first storage node and the second bit line is configured to transmit data to or from the second storage node; a dummy cell comprising a first dummy node and a second dummy node that are configured to complementarily store data; a first dummy bit line and a second dummy bit line, wherein the first dummy bit line is configured to transmit data to or from the first dummy cell and the second bit line is configured to transmit data to or from the second dummy node; a dummy-bit-line voltage control unit configured to control a voltage of one or both of the dummy bit lines and thereby invert data stored in one of the dummy nodes; a selection-time control unit configured to control a time for selecting the word line based on an inversion condition of the data stored in the dummy node that is subject to the data inversion; and a row decoder configured to select the word line based on selection time controlled by the selection-time control unit.