Patent ID: 8438367

Claim:
An apparatus for extracting instructions from a stream of instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length, the apparatus comprising: a queue with mutiple entries, wherein each entry of the queue is configured to store a different non-rotated line of the instruction bytes from the stream and accumulated prefix information associated with each of the instruction bytes in the line, wherein the queue has a bottom entry (BE) and a next-to-bottom entry (NTBE), and wherein subsequent logic extracts instruction bytes from the BE and NTBE; and control logic, coupled to the queue, configured to: (a) detect a condition in which the end of the BE is a prefix byte of a boundary-crossing instruction; (b) save away the number of prefix bytes of the boundary-crossing instruction that are in the BE, shift the first line in the BE out of the queue, and shift a second line of instruction bytes from the NTBE into the BE, in response to detecting the condition, but if there are unextracted non-prefix bytes in the BE, to forego shifting the first line in the BE out of the queue; (c) extract instruction bytes of the boundary-crossing instruction from the second line in the BE and extract accumulated prefix information from the second line of the BE in place of the prefix bytes of the initial portion that were already shifted out of the queue; (d) calculate the length of the boundary-crossing instruction using the saved length; and (e) extract an instruction other than the boundary-crossing instruction from the second line in the BE using the calculated length.