Patent ID: 7871892

Claim:
A method for fabricating a buried capacitor structure, comprising: providing a first dielectric layer which includes a first surface having a first metal layer formed thereon and a second surface having a capacitor embedded therein, wherein the capacitor comprises a positive electrode having a positive electrode end and a negative electrode having a negative electrode end; providing a second dielectric layer which includes a first surface having a second metal layer formed thereon and a second surface; facing the second surface of the first dielectric layer with the second surface of the second dielectric layer, and laminating the first dielectric layer having the first metal layer and the capacitor with the second dielectric layer having the second metal layer, wherein the capacitor is buried between the first dielectric layer and the second dielectric layer; penetrating the first metal layer, the first dielectric layer, the second dielectric layer and the second metal layer to form a through-hole; penetrating the second metal layer and the second dielectric layer, and forming a positive through-hole and a negative through-hole to reach the positive electrode end and the negative electrode end, respectively; filling a metal material into the through-hole to electrically connect the first metal layer with the second metal layer, and filling a metal material into the positive through-hole and the negative through-hole to form a positive lead and a negative lead, respectively, wherein the positive lead electrically connects the positive electrode end with the second metal layer and the negative lead electrically connects the negative electrode end with the second metal layer; patterning the first metal layer and the second metal layer to form a first circuit pattern and a second circuit pattern, respectively; forming a first insulating layer on the patterned first metal layer and the exposed first dielectric layer, and forming a second insulating layer on the patterned second metal layer and the exposed second dielectric layer, wherein the first insulating layer includes a plurality of first openings to expose a portion of the first metal layer and the second insulating layer includes a plurality of second openings to expose a portion of the second metal layer; and forming a third metal layer in the first openings and forming a fourth metal layer in the second openings.