Patent ID: 8338279

Claim:
A method comprising: providing a semiconductor substrate having transistor structures and test structures, wherein spacing between the transistor structures is smaller than spacing between the test structures; first iteratively performing a deposition and etch process including: depositing a first doped epitaxial layer over the semiconductor substrate, the first doped epitaxial layer having a first concentration of a dopant, and etching the first doped epitaxial layer; and second iteratively performing a deposition and etch process including: depositing a second doped epitaxial layer over the semiconductor substrate, the second doped epitaxial layer having a second concentration of the dopant that is higher than the first concentration, and etching the second doped epitaxial layer, wherein the first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures.