Patent ID: 7241648

Claim:
A method of forming an array substrate for use in a thin film transistor liquid crystal display, comprising: sequentially forming a transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer and a sacrificial layer on a substrate; forming a photoresist pattern comprising a first photoresist layer and a second photoresist layer on part of the sacrificial layer, wherein the second photoresist layer is thicker than the first photoresist layer; using the photoresist pattern as an etching mask, removing at least part of the sacrificial layer, the second insulating layer and the semiconductor layer to form a first opening and a second opening; removing the first photoresist layer; using the second photoresist layer as an etching mask, removing part of the sacrificial layer to form a remaining sacrificial layer narrower than the second photoresist layer, removing part of the second insulating layer and the semiconductor layer and causing the first and second openings exposing the substrate; removing the second photoresist layer; using the remaining sacrificial layer as an etching mask, removing part of the second insulating layer and the first insulating layer to expose a portion of the first metal layer; removing the remaining sacrificial layer and the exposed first metal layer to define a gate line comprising a gate, a channel layer located directly above the gate, a gate pad located at an end portion of the gate line, a pixel electrode and a source pad, wherein the first opening is located in the gate line near the gate; forming an insulating spacer on sidewalls of the gate and the gate line; thoroughly forming a second metal layer overlying the substrate; patterning the second metal layer to form a source line, a source and a drain, wherein the source line crosses the gate line, an end portion of the source line is electrically connected to the source pad, the source is extended from the source line and electrically connected to the channel layer and the drain is electrically connected to the channel layer and the pixel electrode.