Patent ID: 8760944

Claim:
A memory component comprising: a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals and a strobe input, each to be coupled to a respective external signaling link; data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; and CA circuitry to sample CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively.