Patent ID: 6943075

Claim:
A method for manufacturing a flash memory device, comprising the steps of: forming a tunnel oxide layer on a semiconductor substrate; forming a first silicon layer on the tunnel oxide layer; forming a pad nitride layer on the first silicon layer; patterning the pad nitride layer, the first silicon layer and tunnel oxide layer to expose an isolation region of a semiconductor substrate; forming a trench in the isolation region; forming an insulating material layer on the layered substrate and then removing the insulating material layer on the pad nitride layer, thus forming an isolation layer in the trench; removing the pad nitride layer; forming a second silicon layer whose bottom is composed of a doped silicon layer and top is composed of an undoped silicon layer on the entire structure; patterning the second silicon layer so that a central portion of the isolation layer is exposed and the edge of the isolation layer is overlapped with the isolation layer; forming an anti-oxidization layer on the entire surface of the second silicon layer; sequentially forming a dielectric layer, a third silicon layer and a silicide layer on the entire structure including the second silicon layer; and patterning the silicide layer and the second silicon layer by means of an etch process using a control gate mask to form a control gate, and then patterning the first and second silicon layers by means of a self-aligned etch process to form a floating gate.