Patent ID: 7387931

Claim:
A method of fabricating a semiconductor memory device comprising: forming a pad oxide layer and hard mask patterns arranged to be spaced apart from each other on a semiconductor substrate; forming a plurality of pillars arranged to be spaced apart from one another by etching the pad oxide layer and the semiconductor substrate to a first etching depth using the hard mask patterns; forming a first insulating layer on the semiconductor substrate to fill a space between the pillars; etching the pillars and the first insulating layer to a second etching depth that is less than the first etching depth, to form trenches extending in a first direction such that each of the pillars has a body portion and a pair of pillar portions spaced apart from each other by the trench; forming a first doped region in the body portion; forming a bitline disposed on the body portion in the trench, the bitline electrically contacting the first doped region and penetrating a space between a pair of the pillar portions of the pillars arranged along the same line of the first direction; exposing the side surface of the pillar portion; forming a gate dielectric layer surrounding the exposed side surface of the pillar portion, and forming a gate electrode surrounding the gate dielectric layer; forming a second insulating layer covering the bitline on the semiconductor between the pillars; forming a wordline electrically contacting the side surface of the gate electrode and extending in a second direction intersecting the first direction; forming a third insulating layer on the wordline and the second insulating layer; removing the hard mask patterns and the pad oxide layer to expose the upper surface of the pillar portion of the pillar; forming a second doped region on the exposed upper surface of the pillar portion; and forming a storage node electrode electrically contacting the second doped region.