Patent ID: 8203569

Claim:
A graphics processor comprising: a plurality of registers, each of which holds data for a unit of rendering, which is a data unit repeatedly used in a graphics operation; a selector, which alternately selects from the plurality of registers to create an interleave of data so as to schedule the reading of the data of the unit to be rendered that is held in the selected register; and an arithmetic unit that sequentially receives the interleaved data of the unit to be rendered that has been selected by the selector and sequentially performs an arithmetic operation on the interleave of the plurality of units to be rendered, wherein the input of the data of one register is offset in the interleave by the selector when input to the arithmetic unit by an instruction shift amount, defined as the interval between program instructions executed for the same data, and wherein the input of data is further offset in the interleave by a pixel shift amount, defined as the interval of data from one register to another when alternating among registers for one instruction.