Patent ID: 8621398

Claim:
A method of generating a layout for a semiconductor device, comprising: receiving a first layout, the first layout including an active region that has a side; defining a portion of the first layout as a FinFET region, the FinFET region including the active region; defining in the FinFET region a plurality of elongate mandrel regions that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction; defining in the FinFET region a plurality of pairs of elongate fin regions that each extend in the first direction and are separated in the second direction by a respective one of the mandrel regions; evaluating, by a computer, whether a condition has been met, where the condition is a function of a location of the side of the active region in relation to locations of the fin regions, wherein the condition is met if the side of the active region is completely disposed within one of the fin regions; resizing the active region if the evaluating reveals that the condition has been met, wherein the resizing includes expanding the active region in the second direction when the side of the active region is completely disposed within one of the fin regions such that the side of the active region is approximately aligned with an edge of the fin region within which the side was previously disposed, wherein the edge of the fin region remains stationary during the expanding of the active region in the second direction; and generating a second layout using a layout-generating machine, the second layout including the resized active region.