Patent ID: 7678656

Claim:
A process for forming an HV PMOS device, comprising: providing a semiconductor substrate having an HV well of a first polarity type, the HV well having a surface and being formed in an epitaxial layer of a second polarity; forming one or more pairs of field oxide regions on the substrate, said field oxide regions disposed at least in part over said HV well; forming one or more pairs of insulated gates over the HV well between each pair of field oxide regions, the gates having inner edges facing each other and outer edges facing a corresponding one of the field oxide regions; masking the substrate to expose predetermined outer portions of the gates and predetermined portions of the HV well surface adjacent thereto; implanting the exposed portions of the HV well to form first and second tub regions of the first polarity type therein, said tub regions being in self-alignment with the outer edges of the gates; masking the substrate to expose predetermined inner portions of the gates and the HV well surface between the gates; implanting the exposed portions of the HV well to form buffer and drift regions of the first and second polarity types, respectively, therein that are self-aligned with the inner edges of the gates; masking the substrate to expose predetermined outer portions of the gates, predetermined portions of the first and second tub regions of the first polarity type adjacent thereto, and a predetermined portion of the drift region; and implanting the exposed portions to form first and second tub regions of the second polarity type within the first and second tub regions of the first polarity type and which are in self-alignment with the outer edges of the gates, and to form a third tub region of the second polarity type within the drift region.