Patent ID: 8519933

Claim:
A shift register circuit comprising: a control circuit configured set a control line to an active potential or an inactive potential, a first input line of the control circuit being configured to receive a first latch pulse; a first switch element configured to make an electrical connection between a clock supply line and a connection terminal when said control line is at said active potential, said control circuit setting said control line to said active potential when either said first latch pulse or said second latch pulse is at a logic level state; a second switch element configured to make an electrical connection between a potential supply section and said connection terminal when said control line is at said inactive potential, said control circuit setting said control line to said inactive potential when neither said first latch pulse nor said second latch pulse is at said logic level state, wherein said connection terminal is directly electrically connected to an input of an inverter, an output of the inverter being directly electrically connected to said first input line.