Patent ID: 7502708

Claim:
A test apparatus that tests a device under test, comprising: a control processor that executes a test program to test the device under test; a test unit connected to the device under test that tests the device under test according to an instruction of the control processor; and a relay section connected to the control processor and the test unit that relays a control instruction transmitted from the control processor to the test unit, wherein the relay section includes: a buffer section that buffers the control instruction to be written to an address assigned from the control processor to the test unit; a timing storage section that stores a timing at which the control instruction should be transmitted to the test unit, the timing being designated by a command received from the control processor; and a buffer control unit that detects that the timing stored in the timing storage section comes and transmits the control instruction buffered by the buffer section to the test unit in response to detecting that the timing comes, wherein the control processor writes the timing at which the control instruction should be transmitted to the test unit to the address assigned to the relay section before writing the control instruction, the buffer section sequentially buffers a timing write command to write the timing and a control instruction write command to write the control instruction, which are received from the control processor and the buffer control unit delays processing the control instruction write command received after the timing write command until the timing comes in response to that the timing write command is fetched from the buffer section.