Patent ID: 7274067

Claim:
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein at least one logic cell includes a non-volatile memory cell including: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the floating gate; a low tunnel barrier intergate insulator formed on the first metal layer; a second metal layer formed on the intergate insulator; and a control gate formed on the second metal layer.