Patent ID: 7960273

Claim:
A method of manufacturing a metal interconnection of a semiconductor device, the method comprising: forming a base layer with at least one groove, the at least one groove having an open upper portion; forming a first metal layer in the at least one groove, the first metal layer including a first portion covering a bottom surface of the at least one groove and a second portion covering sidewalls of the at least one groove; forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on the bottom surface of the at least one groove, and the seed metal layer including sidewalls spaced apart from the second portion of the first metal layer covering the sidewalls of the at least one groove; and forming a metal pattern grown from the seed metal layer to fill the at least one groove; wherein forming the seed metal layer includes: forming a preliminary seed metal layer on the first metal layer; forming a sacrificial pattern to fill the at least one groove; selectively removing a portion of the preliminary seed metal layer using the sacrificial pattern as an etch mask to form the seed metal layer only on the bottom surface of the at least one groove and to form the sidewalls of the seed metal layer spaced apart from the second portion of the first metal layer covering the sidewalls of the at least one groove; and removing the sacrificial pattern.