Patent ID: 7807532

Claim:
A method of fabricating an integrated circuit device, the method comprising: providing a semiconductor substrate, the substrate comprising a surface region; forming a pad oxide layer overlying the surface region, the pad oxide layer having a pad oxide surface region; forming a silicon nitride layer overlying the pad oxide layer; forming a trench region extending through an entirety of a portion of the silicon nitride layer and extending into a depth of the semiconductor substrate; filling the trench region with an oxide material using a plasma deposition process, the oxide material extending from a bottom portion of the trench region to a vicinity of an upper surface region of the silicon nitride layer; selectively removing the silicon nitride layer to cause formation of an isolation structure, the isolation structure extending from the bottom portion of the trench region to a height above the pad oxide surface region; stripping the pad oxide layer; forming a tunnel oxide overlying the surface of the semiconductor substrate; depositing a conformal layer of polysilicon material overlying the isolation structure including the tunnel oxide structure; and planarizing the polysilicon layer to expose a top portion of the isolation structure and form a first electrode structure and a second electrode structure separated by a portion of the isolation structure, comprising: performing a low selectivity chemical mechanical polishing process to remove a thickness of the polysilicon material; performing a high selectivity chemical mechanical polishing process to expose a portion of the isolation material; and performing an over polishing process once a portion of the isolation material has been exposed.