Patent ID: 7792237

Claim:
A shift register for outputting an output pulse at an output end in response to a delay of an input pulse received at an input end, comprising: a first voltage supply end for providing a first supply voltage; a second voltage supply end for providing a second supply voltage; a controller electrically coupled to the input end, for generating a level switching signal in response to the input pulse, a first clock signal, and a second clock signal complementary to the first clock signal; a pre-charging switch electrically coupled to the first voltage supply end and the input end, for conducting the first supply voltage to a level shifting node in response to the input pulse; a level shifting switch electrically coupled to the controller and the level shifting node, turning on in response to the level switching signal, wherein the level shifting switch is a first transistor, and a gate, a first electrode, and a second electrode of the first transistor are respectively electrically coupled to the level switching signal from the controller, the output end, and the level shifting node; and an output generator electrically coupled to the output end and the level shifting node, for generating the output pulse at the output end in response to the second clock signal and voltage on the level shifting node, when the level shifting switch turns on.