Patent ID: 8804395

Claim:
A method for accessing data in a DRAM having hierarchical bit lines comprising: in a standby state: enabling precharge of a global bit line to a precharge voltage; enabling a redundant hierarchical switch to connect the global bit line to a redundant local bit line to which redundant memory cells are connected; and disabling a plurality of normal hierarchical switches to connect the global bit line to respective normal local bit lines to which normal memory cells are connected; upon activation: receiving an address corresponding to a selected normal memory cell; enabling a selected normal hierarchical switch to connect the global bit line to a selected normal local bit line to which the selected normal memory cell is connected; determining whether the address matches a defective address; and disabling precharge of a global bit line; if the address does not match the defective address: disabling the redundant hierarchical switch to disconnect the global bit line and the redundant local bit line; and enabling a selected normal word line connected to the selected normal memory cell; if the address matches the defective address: disabling the selected normal hierarchical switch to disconnect the global bit line and the selected normal local bit line; and enabling a selected redundant word line connected to a selected redundant memory cell.