Patent ID: 7272757

Claim:
A test arrangement for an error analysis of at least one memory chip of a memory module, comprising: a first interface configured to couple to a memory module slot of a computer system; a second interface configured to couple to a memory module comprising a first memory chip and at least one second memory chip, the first and the at least one second memory chip of the memory module comprising a plurality of addressable memory cells; a test memory chip comprising a plurality of addressable memory cells; a control device coupled to the first and the second interface and to the test memory chip; a first switching device controlled by the control device, and configured to selectively couple the test memory chip to the second interface; and a second switching device controlled by the control device and connected between the first interface and the second interface; wherein the control device is further configured to dictate a first operating state, wherein the second switching device is activated and data is written to memory cells of the first memory chip, and to memory cells of the test memory chip and, wherein the control device is configured to dictate a second operating state, wherein the first switching device is activated and data from the memory cells of the first memory chip is compared with the data from the memory cells of the test memory chip.