Patent ID: 7380221

Claim:
A method of reducing subexpressions in structural design representations, said method comprising: receiving an initial design, wherein said initial design represents an electronic circuit containing an AND gate; selecting a first simplification mode for said initial design from a set of applicable simplification modes, wherein said first simplification mode is an AND/OR simplification mode; performing a simplification of said initial design according to said first simplification mode to generate a reduced design; determining whether a size of said reduced design is less than a size of said initial design; in response to determining that said size of said reduced design is less than said size of said initial design, replacing said initial design with said reduced design; and in response to determining that said size of said reduced design is not less than said size of said initial design: selecting a second simplification mode for said initial design from said set of applicable simplification modes; and performing a simplification of said initial design according to said second simplification mode to generate a reduced design, in response to determining that said reduced design does not meet a size parameter.