Patent ID: 6920590

Claim:
A semiconductor apparatus comprising: a set of n comparators which is responsive to 2n input signals for outputting n digital result signals, wherein an i-th comparator where i is an natural number not more than n of said n comparator is responsive to a (2i−1)-th input signal and a 2i-th input signal of said 2n input signals for outputting an i-th digital result signal of said n digital result signals in synchronization with a clock signal; and an OR gate outputting a total result signal indicative of an OR of said n digital result signals, wherein said i-th comparator inverts said i-th digital result signal at a timing indicated by said clock signal while said (2i−1)-th input signal and said 2i-th input signal coincide with each other, and does not invert said digital result signal while said (2i−1)-th input signal and said 2i-th input signal do not coincide with each other.