Patent ID: 8355272

Claim:
A memory comprising: a first plurality of memory elements comprising a first row group, each of the first plurality of memory elements having a first terminal, a second terminal, and a third terminal; a second plurality of memory elements comprising a second row group, each of the second plurality of memory elements having a fourth terminal, a fifth terminal, and a sixth terminal; a first plurality of M bit lines, each configured to be coupled to one of the first terminals and one of the fourth terminals; a first local source line coupled to the second terminals; a second local source line coupled to the fifth terminals; a first word line coupled to the third terminals; a second word line coupled to the sixth terminals; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the first plurality of M bit lines and configured to apply a current of magnitude N through the memory element in the selected row group coupled to one of the first plurality of M bit lines by applying the current of magnitude less than N to two or more of the remaining M-1 bit lines.