Patent ID: 8293545

Claim:
A method of forming an integrated circuit (IC) comprising: providing a test substrate; etching the test substrate using a first etch process to form a plurality of test structures on the test substrate, wherein a test structure comprises trenches and spaces between the trenches, and different test structures of the plurality of test structures have different test structure dimensions; determining a trench critical dimension (T CD ) of trenches in a via level of the IC using the plurality of test structures on the test substrate formed by the first etch process, wherein the T CD is equal to a selected test structure dimension of a selected test structure from the plurality of test structures on the test substrate, wherein the selected test structure has trenches and vias having substantially the same depth from the first etch process; providing a partially processed substrate of the IC; depositing a dielectric layer on the partially processed substrate; forming the trenches using the T CD in a periphery of the substrate in the dielectric layer and vias in the dielectric layer, wherein the trenches and vias have substantially the same depth due to the T CD ; filling the trenches and vias with a conductive material; and continuing to process the substrate to complete forming the IC.