Patent ID: 7577224

Claim:
A method comprising: combining, in a clock and data recovery circuit, transition counts between a sampling clock and each of a first error clock and a second error clock to obtain a combined first and second error count and comparing a target error count with the combined first and second error count to obtain an error signal; digitally filtering the error signal in a first filter of the clock and data recovery circuit to obtain an offset signal; adjusting, in the clock and data recovery circuit, a phase of at least one of the first error clock and the second error clock using the offset signal by combining the offset signal with a data clock signal, and digitally filtering the data clock signal before the combining of the offset signal with the data clock signal; determining, in the clock and data recovery circuit, a difference in the transition counts; digitally filtering the difference in a second filter of the clock and data recovery circuit; and adjusting, in the clock and data recovery circuit, a phase of the sampling clock using the filtered difference.