Patent ID: 8310388

Claim:
A subrange analog-to-digital converter (ADC) with M bits, comprising: a positive and a negative input terminals; a first capacitor array having 2(2(N+1)−2) equivalent capacitors, each of which has a first and a second terminals, divided into N groups representing the first N bits of the M bits counted from a most significant bit (MSB) to a least significant bit (LSB); a successive approximation ADC (SAR ADC) including a second capacitor array having a plurality of bits and at least one capacitor with a first and a second terminals, wherein each the bit of the first and the second capacitor arrays electrically connects with at least one of the capacitors, the first terminal electrically connects with one of the positive and negative input terminals, and the second terminal switchably connects with a first and a second reference voltage sources to selectively receive a first and a second reference voltages; and a flash ADC receiving the first and the second reference voltages and a positive and a negative input voltages from the positive and the negative input terminals, generating two output signal sets, each of which has (2(N+1)−2) output signals, and simultaneously determining whether to adjust respective potential levels of the N bits represented by the N groups according to the two output signal sets.