Patent ID: 6943440

Claim:
A method comprising: forming a first unitary metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die; forming a first substantially planar dielectric layer over the first metal layer; forming vias in the first dielectric layer; forming a second base layer metallization in the vias of the first dielectric layer; and forming a unitary second metal layer over the second base layer metallization; forming a second substantially planar dielectric layer over the second metal layer; forming vias in the second dielectric layer; and forming first, second, and third bumps in the vias of the second dielectric layer, the first metal layer being operative to transfer current from the first and second bumps to the top metal layer of the integrated circuit die, the second metal layer being operative to transfer current from the first and third bumps to the top metal layer of the integrated circuit die.