Patent ID: 7813434

Claim:
A bit loading method for a multiple latency xDSL transceiver comprising: dividing a communication channel into a plurality of equal bandwidth sub-channels; determining transmission characteristics of each sub-channel; establishing at least two data paths from the sub-channels based on an identified boundary between the sub-channels associated with the data paths, wherein the data paths are characterized in having different target SNR margins; and allocating a number of bits for each sub-channel based on the transmission characteristics of each sub-channel, wherein the transmission characteristics comprise signal-to-noise ratio (SNR) gap, and capacity of each sub-channel and the SNR margin associated with the data path containing the sub-channel; directing bits of data to the data paths based on whether the bits of data are latency sensitive and based on the different target SNR margins such that different coding gains are applied to data in carriers allocated to the at least two data paths; and simultaneously transferring the bits of data over the at least two data paths.