Patent ID: 7346820

Claim:
A circuit device comprising: a circuit component having a plurality of data retention latches, each data retention latch having a scan chain component, a first latching component operated at a first voltage and a second latching component operated at a second voltage different than the first voltage; a scan controller having a first input to receive a scan test control signal, a first output coupled to the circuit component to provide a first scan chain data to the scan chain components of the plurality of data retention latches responsive to the scan test control signal, a second input coupled to the circuit component to receive a second scan chain data from the scan chain components of the plurality of data retention latches based on the first scan chain data, and a second output to provide the second scan chain data; a power controller having an input to receive a power control signal, a first output to selectively provide the first voltage responsive to the power control signal, and a second output to selectively provide the second voltage responsive to the power control signal; a test interface having a first input to receive scan test data and an output to provide test results data; a system test controller coupled to the test interface, the system test controller including a first input coupled to the second output of the scan controller to receive the second scan chain data, wherein the test results data includes the second scan chain data, a first output coupled to a third input of the scan controller to provide the scan test data, wherein the scan test data includes the first scan chain data, a second output coupled to the first input of the scan controller to provide the scan test control signal, and a third output coupled to the input of the power controller to provide the power control signal.