Patent ID: 8065478

Claim:
A system, comprising: a bus; a processor configured to execute instructions stored in a computer readable medium, the processor electrically coupled with the bus; a communications interface electrically coupled with the bus; a plurality of non-volatile third dimension two-terminal memory arrays in electrical communication with the bus, each array including a plurality of two-terminal memory elements arranged in a cross-point array configuration and to store non-volatile data as a plurality of conductivity profiles, each two-terminal memory element including an electrolytic tunnel barrier having a thickness less than 50 Å in contact with a mixed valence conductive oxide including mobile oxygen ions that are moveable between the electrolytic tunnel barrier and the mixed valence conductive oxide in response to a write voltage applied across the two-terminal memory element, a first one of the plurality of non-volatile third dimension two-terminal memory arrays is configured as non-volatile system memory and stores data including the instructions for the processor, a second one of the plurality of non-volatile third dimension two-terminal memory arrays is configured as a non-volatile storage device, and a third one of the plurality of non-volatile third dimension two-terminal memory arrays is configured as a non-volatile storage medium operative to replace a hard disk drive (HDD); and a silicon substrate including access circuitry, disk controller circuitry, the bus, the processor, and the communications interface formed on the silicon substrate, the access circuitry configured to perform data operations on the non-volatile system memory and the non-volatile storage device, the disk controller circuitry is electrically coupled with the access circuitry and the non-volatile storage medium, the disk controller circuitry configured to perform access requests on the non-volatile storage medium in response to HDD commands electrically communicated on the bus, and the non-volatile third dimension two-terminal memory arrays for at least the non-volatile system memory and the non-volatile storage, device are fabricated directly above, the silicon substrate and are electrically coupled with the access circuitry.