Patent ID: 7268604

Claim:
A comparator comprising: a differential amplifier configured to amplify a difference signal corresponding to a difference between input signals of the differential amplifier; and a hysteresis circuit configured to set up a first transition threshold voltage and a second transition threshold voltage where the second transition threshold voltage is different from the first transition threshold voltage, and configured to generate a hysteresis output signal that makes a transition at the first transition threshold voltage when the difference signal changes in a first direction, and makes a transition at the second transition threshold voltage when the difference signal changes in a second direction, the hysteresis circuit including a Schmitt trigger circuit including: an inverting unit configured to invert a first signal, the first signal to be generated by the differential amplifier, the inverting unit including: a pull-up driver configured to pull up an output terminal of the hysteresis circuit in response to the first signal, the pull-up driver including: a first PMOS transistor having a source coupled to a first supply voltage and a gate to which the first signal is applied; and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a drain coupled to the output terminal of the hysteresis circuit; and a pull-down driver configured to pull down the output terminal of the hysteresis circuit in response to the first signal, the pull-down driver including: a first NMOS transistor having a source coupled to a second supply voltage and a gate to which the first signal is applied; and a second NMOS transistor having a source coupled to a drain of the first NMOS transistor and a drain coupled to the output terminal of the hysteresis circuit; and a hysteresis-threshold setting unit configured to set the first transition threshold voltage and the second transition threshold voltage, the hysteresis-threshold setting unit including: a third PMOS transistor, coupled between the drain of the first PMOS transistor and a first node, configured to perform a switching operation in response to the voltage level of the output terminal of the hysteresis circuit; a first diode coupled between the first node and the second supply voltage; a third NMOS transistor, coupled between the drain of the first NMOS transistor and a second node, configured to perform a switching operation in response to the voltage level of the output terminal of the hysteresis circuit; and a second diode coupled between the second node and the first supply voltage; wherein the hysteresis-threshold setting unit adjusts a turn-on voltage of the pull-up driver or a turn-on voltage of the pull-down driver in response to a voltage level of the output terminal of the hysteresis circuit.