Patent ID: 7645654

Claim:
A process for manufacturing a Junction Field Effect Transistor, comprising: doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region; implanting impurities of a second conductivity type into said well region to form a channel region; implanting impurities of the first conductivity type into said well region to form a back gate region; forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region; depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact; doping the polysilicon with impurities of a first conductivity type; and annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region, wherein the top gate region makes electrical contact with the gate contact and extends far enough to make electrical contact with said back gate region.