Patent ID: 6978403

Claim:
A deskew circuit comprising: a first receiver that receives data and is provided for each bit of a data bus composed of a plurality of bits; a first variable delay circuit that is provided with an output of the first receiver; a second receiver that receives a clock transferred in parallel with the data; a second variable delay circuit that is provided with an output of the second receiver; a first delay circuit that gives a first delay to an output of the second variable delay circuit; a second delay circuit that gives a delay greater than the first delay to the output of the second variable delay circuit; a first flip-flop that receives an output of the first variable delay circuit as data and latches the data with an output timing of the second variable delay circuit; a second flip-flop that receives an output of the first variable delay circuit as data and latches the data with an output timing of the first delay circuit; a third flip-flop that receives an output of the first variable delay circuit as data and latches the data with an output timing of the second delay circuit; a first exclusive OR circuit that calculates an exclusive OR of an output of the first flip-flop and an output of the second flip-flop; a second exclusive OR circuit that calculates an exclusive OR of an output of the second flip-flop and an output of the third flip-flop; and a second module that adjusts a setting value of the first variable delay circuit when an output of the first exclusive OR circuit of the second exclusive OR circuit is at a high level.