Patent ID: 8214190

Claim:
A method carried out by a computer system for estimating correlated failure distributions of memory array designs having different groupings of memory cells connected to peripheral logic elements, the method comprising: constructing memory unit models for the different groupings of memory cells based on at least a first parameter associated with the memory cells and a second parameter associated with the peripheral logic elements; establishing failure conditions of the memory unit models; calculating fail boundaries in terms of the first and second parameters for the memory unit models based on the failure conditions by computing a center-of-gravity for corresponding failure conditions in a parametric space defined by the first and second parameters, computing an anchor point which lies on a line from an origin of the parametric space to the center-of-gravity and is a closest failing point to the origin, and computing the given fail boundary as a line which passes through the anchor point and represents a linear fit with other failure points within a close distance of the anchor point; constructing memory array models for the memory array designs characterized by the fail boundaries; simulating operation of the memory array models repeatedly with random values of the first parameter assigned to the memory cells and random values of the second parameter assigned to the peripheral logic elements to identify memory unit failures for each simulated operation; and calculating a mean and a variance of the memory unit failures for each of the memory array models.