Patent ID: 7075285

Claim:
A delay locked loop circuit comprising: an input to receive an input clock signal; a test signal source to provide a test signal; a switching mechanism connected to the input and the test signal source, the switching mechanism being configured to selectively transmit one of the input clock signal and the test signal as a selected signal; an array of delay elements connected to the switching mechanism to receive the selected signal, the delay elements being configured to selectively form a variable delay chain; a tap selector connected to the array of delay elements, the tap selector being configured to provide tap signals to columns of delay elements of the array; a test signal receiver connected to the array of delay elements to receive an output test signal from the array of delay elements, the output test signal providing information whether any of the delay elements is not properly operating; and a second test signal source connected to the array of delay elements, the second test signal source being configured to provide a second test signal to the rows of the delay elements of the array, the second test signal being differant from the test signal of the test signal source.