Patent ID: 7821316

Claim:
A multi-phase clock generator circuit, comprising: a clock input terminal that receives a clock input signal; at least two clock output terminals, each providing a clock output signal where the clock output signals collectively have substantially equal phase spacing; a voltage-controlled delay line (VCDL) comprising multiple delay stages, each delay stage of the voltage-controlled delay line comprising: an input terminal (IN); a first output terminal (OUT); a second output terminal (CLKOUT); a first control terminal (BIASG); a second control terminal (DELAY); a leading clock input terminal (CLKL); a trailing clock input terminal (CLKT); a delay control terminal (CTRL); a common delay control terminal (COMCTRL); a common-mode feedback terminal (CMFB); a voltage-controlled delay element having an insertion delay controlled by a voltage; an output level converter and buffer; a phase measurement circuit; a first voltage-controlled current-source; a second voltage-controlled current-source; and a filter capacitor; an input clock signal conditioning circuit; a phase detector; and a low-pass filter coupled between and operating in combination with the phase detector, the phase measurement circuits, and the first and second voltage-controlled current sources, to provide stable control of the insertion delay of each delay stage of the VCDL such that each insertion delay is substantially equal to the others and the phase spacing between adjacent output clock signals of the different delay stages is thereby substantially uniform.