Patent ID: 7924638

Claim:
An integrated circuit memory comprising: a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank; wherein at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells; and further comprising: redundant row control circuitry coupled to said plurality of memory banks and responsive to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group to substitute one of said at least one redundant rows of memory cells for said defective row of memory cells, wherein said redundant row control circuitry comprises address matching circuitry associated with each of said at least one redundant row of memory cells, said address matching circuitry matching an input row address with a predetermined defective row address and generating in dependence thereon a redundant row enable signal to enable a redundant row of memory cells to substitute for a defective row of memory cells having said predetermined defective row address.