Patent ID: 8031507

Claim:
A semiconductor memory device comprising: a memory cell array comprising memory cells, each of the memory cells comprising a cell transistor and a ferroelectric capacitor; a sense amplifier circuit configured to detect and amplify a signal read from the ferroelectric capacitor via a bit line pair; and a dummy capacitor configured to provide a reference voltage to the bit line pair, the dummy capacitor further comprising: a first dummy capacitor comprising a first end with a first dummy plate potential configured to set the reference voltage to a predetermined voltage, and a second end configured to connect to the bit line pair; and a second dummy capacitor comprising a first end with a second dummy plate potential configured to fine-tune the reference voltage from the predetermined voltage and a second end configured to connect to the bit line pair, wherein a capacitance of the first dummy capacitor is larger than a capacitance of the second dummy capacitor.