Patent ID: 8000519

Claim:
A method of evaluating an inline inspection recipe comprising: setting up a first inline inspection process of a patterned metal layer on a wafer according to first inline inspection parameters; inspecting the patterned metal layer to capture metal pattern defect data; processing the wafer to produce integrated circuits for electrical test, each of the integrated circuits being essentially identical; applying a test vector to the integrated circuits to capture electrical failures for a plurality of failed integrated circuits; calculating a bounding box for the plurality of failed integrated circuits in accordance with the test vector; mapping metal pattern defect data for each of the plurality of failed integrated circuits to the bounding box; calculating a first capture rate; wherein the first capture rate is calculated as a function of a total number of those of the failed integrated circuits for which the metal pattern defect data maps to the bounding box, and of a total number of the failed integrated circuits; shifting the bounding box for each of the plurality of failed integrated circuits to provide an offset bounding box for each of the plurality of failed integrated circuits; mapping metal pattern defect data to the offset bounding box for each of the plurality of failed integrated circuits; calculating a second capture rate; wherein the second capture rate is calculated as a function of a total number of those of the failed integrated circuits for which the metal pattern defect data maps to the offset bounding box, and a total number of the failed integrated circuits; comparing the first capture rate to the second capture rate to produce a difference; and adjusting the inline inspection recipe according to the difference to improve capture of killer defects.