Patent ID: 7773444

Claim:
A semiconductor memory device comprising: a memory cell array including a first memory cell array block and a second memory cell array block, the first memory cell array block including a memory cell having a floating body connected to a word line, a first bit line, and a first source line, the second memory cell array block including a reference memory cell having a floating body connected to a reference word line, a second bit line, and a second source line; a first isolation gate portion for transmitting a signal between the first bit line and an inverted sense bit line during a write operation and during a third period of a read operation, and for transmitting a signal between the first bit line and a sense bit line during a first period of the read operation; a second isolation gate portion for transmitting a signal between the second bit line and the inverted sense bit line during the first period of the read operation; a precharge portion for precharging the sense bit line and the inverted sense bit line to a precharge voltage level during a precharge operation; and a sense amplifier for amplifying voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels during the write operation and during a second and the third periods of the read operation.