Patent ID: 7574588

Claim:
A method for interleaving execution within a single processor pipeline of a head thread and a speculative thread, the method comprising: executing program instructions using the head thread which operates on primary versions of memory elements; speculatively executing program instructions in advance of the head thread using the speculative thread which operates on space-dimensioned versions of the memory elements; and if the speculative thread performs a read operation to a memory element: determining if the space-time dimensioned version of the memory element exists; if the space-time dimensioned version of the memory element exists, reading the space-time dimensioned version of the memory element; otherwise, reading the primary version of the memory element; and updating status information associated with the memory element to indicate the memory element has been read by the speculative thread; upon the head thread reaching a point in the program where the speculative thread began executing, merging the space-time dimensioned versions of the memory elements into the primary versions of the memory elements, so that updates to the space-time dimensioned versions of the memory elements are incorporated into corresponding primary versions of memory elements; and wherein instructions from the head thread and instructions from the speculative thread are interleaved in a round-robin fashion and execute concurrently through time-multiplexed interleaving in the single processor pipeline.