Patent ID: 8026536

Claim:
A semiconductor device comprising: a semiconductor substrate; a plurality of MOS transistors arranged on the semiconductor substrate in a row and each including a drain region, a pair of source regions, and a pair of normal gate electrodes, which are arranged in a direction of the row, the pair of source regions sandwiching therebetween the drain region, each of the normal gate electrodes overlying a space between the drain region and a corresponding one of the source regions; a plurality of dummy gate electrodes each overlying a space between one of the source regions of one of the MOS transistors and one of the source regions of an adjacent one of the MOS transistors, each of the dummy gate electrodes being maintained at an equi-potential with the one of the source regions of the one or the adjacent one of the MOS transistors by electrically connecting the each of dummy gate electrodes with the one of the source regions of the one or the adjacent one of the MOS transistors; and a plurality of source-side interconnects, each of the source-side interconnects being connected to adjacent two of the source regions sandwiching therebetween one of the dummy gate electrodes, the each of the source-side interconnects overlies one of the dummy gate electrodes, the each one of the source-side interconnects is disposed between each of two adjacent transistors, the each one of the source-side interconnects has a width smaller than a total width of the adjacent two of the source regions, wherein the normal gate electrodes and the dummy gate electrodes of all of the transistors have the same gate width.