Patent ID: 8234545

Claim:
A method for operating a memory that includes a plurality of memory cells, comprising: encoding input data with an Error Correction Code (ECC) so as to produce input encoded data comprising first and second sections, such that the ECC is decodable with a first error correction capability when decoded only based on the first section, and is decodable with a second error correction capability, higher than the first error correction capability, when decoded based on both the first and the second sections; storing the input encoded data in the memory cells; after storing at least part of the input encoded data, reading from the memory cells output encoded data; and evaluating a condition related to the output encoded data and reconstructing the input data using a decoding level selected, responsively to the evaluated condition, from a group of decoding levels consisting of: a first decoding level, at which a first part of the output encoded data corresponding to the first section of the input encoded data is processed so as to decode the ECC with the first error correction capability; and a second decoding level, at which both the first part and a second part of the output encoded data corresponding to the second section of the input encoded data are processed jointly so as to decode the ECC with the second error correction capability.