Patent ID: 8762804

Claim:
An error-predictive device, comprising: a first latch that is arranged to receive and latch at a first transition of a clock signal the state of an input signal that is applied to the data input of the error-predictive device, wherein the first latch has a first probability of successfully latching the state of the input signal when the error-predictive device is operating at a first operating voltage; a parametric driver that is coupled to the data input of the error-predictive device and is arranged to generate an electrically altered signal conveying the state of the input signal; a second latch that is arranged to receive and latch at the first transition of the clock signal the electrically altered signal, wherein the second latch has a second probability of successfully latching the state of the input signal when the error-predictive device is operating at a first operating voltage, and wherein the electrically altered signal is selectively altered to decrease the second probability to a probability that is less than the first probability; a comparator that is arranged to generate at a second transition having an opposite direction of the first transition of the clock signal an error-predictive warning signal that indicates the output state of the second latch is not the same as the output state of the first latch; and a voltage controller that is arranged to apply a minimum operating voltage that is selected in response to an error-predictive warning signal generated when the error-predictive device is operating at the first operating voltage, wherein the minimum operating voltage is also selected in response to a second operating voltage that is higher than the first operating voltage and when the error-predictive device is operating at the second operating voltage the second latch successfully latches at the first transition of the clock signal the state of the input signal.