Patent ID: 8089447

Claim:
A liquid crystal display comprising: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells; a data drive circuit that generates a pre-charge data voltage during pre-charge time and generates a real-charge voltage to be displayed on the liquid crystal display panel during real-charge time; a gate drive circuit that supplies a first gate pulse synchronized with the pre-charge data voltage to the gate lines during the pre-charge time while shifting the first gate pulse in a downward direction and an upward direction depending on an up/down signal two or more times within 1 frame period for every frame period, and then supplies a second gate pulse synchronized with the real-charge data voltage to the gate lines from a falling edge of the first gate pulse at intervals equal to or longer than scanning time of 1 line during the real-charge time; and a timing controller that generates a gate start pulse indicating a scan start horizontal line of a scan operation in the 1 frame period, a gate shift clock signal shifting the gate start pulse, a gate output enable signal indicating an output of the gate drive circuit, and the up/down signal indicating an output order of the first gate pulse, wherein the timing controller inverts a logic state of the up/down signal two or more times during 1 frame period and controls operation timing of the data drive circuit and the gate drive circuit, wherein a polarity of the pre-charge data voltage is opposite to or the same as a polarity of the real-charge data voltage.