Patent ID: 7745275

Claim:
A method of making an integrated circuit, said method comprising the steps of: forming on a diffusion region of a semiconductor substrate a gate electrode spaced by a gate insulator layer from said diffusion region and at least one local interconnect conductor, each local interconnect conductor respectively forming one of a source electrode and a drain electrode and said at least one local interconnect conductor extending above the diffusion region a distance comparable to a distance said gate electrode extends above the diffusion region; depositing an upper insulator layer over said diffusion region, said gate electrode and said at least one local interconnect conductor; etching through said upper insulator layer (a) at least one electrode opening, said opening reaching an upper surface of said at least one local interconnect conductor and (b) a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, etching of said gate opening being such that said gate opening has a maximum depth insufficient to reach said diffusion region; and depositing an electrode connection conductor in each of said openings.