Patent ID: 7265410

Claim:
A non-volatile memory cell capable of storing two bits of data, comprising: a semiconductor substrate; a source region and a drain region in the substrate and having a channel region therebetween; a first tunneling layer on a first portion of the substrate, the first portion of the substrate extending from the source region toward the channel region; a first charge trapping layer over the first tunneling layer, the first charge trapping layer including a first sidewall; a second tunneling layer on a second portion of the substrate, the second portion of the substrate extending from the drain region toward the channel region; a second charge trapping layer over the second tunneling layer, the second charge trapping layer including a second sidewall; a gate insulating layer between the first portion and the second portion; a blocking layer over the first and second charge trapping layers, respectively, wherein the blocking layer covers the first and second sidewalls of the first and second charge trapping layers, respectively; and a control gate over the first blocking layer, the second blocking layer, and the gate insulating layer.