Patent ID: 7390750

Claim:
A method for processing a semiconductor topography, comprising: forming a hardmask feature spaced adjacent to a patterned sacrificial structure of the semiconductor topography; selectively removing the patterned sacrificial structure to expose an underlying layer; and etching exposed portions of the underlying layer in alignment with the hardmask feature, wherein the step of forming the hardmask feature comprises: conformably depositing a spacing layer above the patterned sacrificial structure and adjacent regions of the underlying layer; blanket etching the spacing layer such that: upper surfaces of the patterned sacrificial structure and portions of the adjacent regions of the underlying layer are exposed; and portions of the spacing layer remain along one or more sidewalls of the patterned sacrificial structure; conformably depositing a hardmask material upon the semiconductor topography subsequent to the step of blanket etching the spacing layer; and blanket etching the hardmask material such that: upper surfaces of the patterned sacrificial structure and portions of the underlying layer adjacent to the etched spacing layer are exposed; and portions of the hardmask material remain along sidewalls of the etched spacing layer.