Patent ID: 6981190

Claim:
A method of testing a path in an integrated circuit, said method comprising: connecting sequentially a plurality of memory elements contained in said integrated circuit, wherein each of said plurality of memory elements comprises a data input and an output, wherein an output of each memory element is coupled to a data input of a next memory element and data — input of each memory element is coupled to one of a plurality of corresponding first multiplexors, the first multiplexor is configured to select a first data input or an output from a previous memory element as said data input for each memory element; providing a launch multiplexor coupled to the data input of a memory element of interest of said plurality of memory elements and configured to select either an output of the corresponding first multiplexor or a second input as said data input of the memory element of interest, wherein said launch multiplexor selects said output of the corresponding first multiplexor in a first configuration and the second input in a second configuration; scanning in sequentially a test pattern into said plurality of memory elements, wherein said test pattern comprises a plurality of bits, wherein said scanning is performed by providing each of said plurality of bits in a consecutive clock cycle on said data input of a first memory element, wherein said first memory element is comprised in said plurality of memory elements, wherein said launch multiplexor is placed in said first configuration when said scanning is performed; evaluating an output of said integrated circuit using said test pattern; storing a desired bit in said memory element of interest by providing said desired bit as said second input to said launch multiplexor and placing said launch multiplexor in said second configuration; and evaluating another output of said integrated circuit after said storing.