Patent ID: 7663424

Claim:
An apparatus comprising: a first transistor switch having a first resistance (R S1 ), wherein the first transistor switch is coupled to an input node, and wherein the first transistor switch is actuated by a first clock signal having a first pulse duration (ts); a second transistor switch having a second resistance (R S2 ), wherein the second transistor switch is coupled to the input node, and wherein the second transistor switch is actuated by a second clock signal having a second pulse duration (m·ts), and wherein the first pulse duration and the second pulse duration begin at substantially the same time; and a capacitor having a capacitance (C), wherein the capacitor is coupled to each of the first and second transistor switches, and wherein the capacitor is charged such that an error voltage after the second pulse duration is: er B ⁡ ( m · ts ) = ⅇ - ( ts C · m · R S ⁢ ⁢ 1 + R S ⁢ ⁢ 2 R S ⁢ ⁢ 1 · R S ⁢ ⁢ 2 ) ⁢ and such that the error voltage after the first pulse duration is: er B ⁡ ( ts ) = ⅇ - ( ts C · m · R S ⁢ ⁢ 1 + R S ⁢ ⁢ 2 R S ⁢ ⁢ 1 ⁢ R S2 + 1 - m R S ⁢ ⁢ 1 ) , and wherein R S1 , R S2 , and m are selected to have the same settling accuracy as if the first and second transistor switches were to be replaced by a single transistor switch actuated by the first clock signal and having a series resistance (R S ), and wherein R S , R S1 , R S2 , and m are related by the following expression: R S = R S ⁢ ⁢ 1 · R S ⁢ ⁢ 2 m · ( R S ⁢ ⁢ 1 + R S ⁢ ⁢ 2 ) + ( 1 - m ) · R S ⁢ ⁢ 2 .