Patent ID: 8216902

Claim:
A method for fabricating a SRAM cell, comprising the steps of: forming at least one pair of pass gates by forming, for each pass gate, one or more device layers on a wafer, each pass gate device layer including a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, and forming a gate common to each of the pass gate device layers surrounding the nanowire channels, wherein the nanowire channels are formed by forming an alternating series of silicon and sacrificial layers in a stack on the wafer, wherein one or more of the sacrificial layers comprise at least one n-type dopant and one or more other of the sacrificial layers comprise at least one p-type dopant; forming nanowire hardmasks over the silicon and sacrificial layers in regions of the cell in which the pass gates and at least one pair of inverters are to be formed, wherein the nanowire hardmasks comprise a dual hardmask structure having an oxide portion and a nitride portion over the oxide portion; forming the at least one pair of inverters by forming, for each inverter, a plurality of device layers adjacent to the pass gate device layers on the wafer, each inverter device layer including a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, and forming a gate common to each of the inverter device layers surrounding the nanowire channels; introducing at least one n-type dopant into the source and drain regions of one or more of the pass gate device layers; introducing at least one n-type dopant into the source and drain regions of one or more of the inverter device layers; and introducing at least one p-type dopant into the source and drain regions of one or more other of the inverter device layers.