Patent ID: 8558380

Claim:
A stack package comprising: a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer formed on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer; a first core layer disposed on a lower surface of the first copper foil attachment resin, and having a first surface to which the first semiconductor chip is attached and a second surface which faces away from the first surface; a second core layer disposed on an upper surface of the second copper foil attachment resin in which the second semiconductor chip is embedded, and having a third surface to which the second semiconductor chip is attached and a fourth surface which faces away from the third surface; and via patterns electrically connecting the first semiconductor chip with the first core layer; wherein the via patterns are electrically connected with the first copper foil layer which is electrically connected with the first bumps, and pass through the first surface and the second surface of the first core layer without passing through the second core layer.