Patent ID: 8755236

Claim:
A latch system applied to a plurality of banks of a memory circuit, the latch system comprising: a front latch circuit having a first input terminal for receiving a datum, a second input terminal for receiving a front latch enabling signal, and an output terminal for outputting an intermediate signal, wherein the front latch circuit generates the intermediate signal according to the datum and the front latch enabling signal, the front latch circuit comprising: a first inverter having a first terminal coupled to the second input terminal of the front latch circuit, and a second terminal for outputting an inverse front latch enabling signal, wherein the first inverter is used for inverting the front latch enabling signal to generate the inverse front latch enabling signal; a second inverter having a first terminal coupled to the first input terminal of the front latch circuit, and a second terminal for outputting a first datum, wherein the second inverter is used for inverting the datum to generate the first datum, and a phase of the first datum is opposite to a phase of the datum; a first transmission gate having a first terminal coupled to the second terminal of the second inverter for receiving the first datum, a second terminal for receiving the front latch enabling signal, a third terminal for outputting the first datum, and a fourth terminal coupled to the second terminal of the first inverter for receiving the inverse front latch enabling signal; a first latch unit having a first terminal coupled to the third terminal of the first transmission gate for receiving the first datum, and a second terminal for outputting a second datum, wherein a phase of the second datum is the same as the phase of the datum; and a third inverter having a first terminal coupled to the second terminal of the first latch unit for receiving the second datum, and a second terminal coupled to the output terminal of the front latch circuit for outputting the intermediate signal, wherein the third inverter is used for inverting the second datum to generate the intermediate signal, and a phase of the intermediate signal is opposite to the phase of the datum; and a plurality of rear latch circuits, each rear latch circuit having a first input terminal coupled to the output terminal of the front latch circuit for receiving the intermediate signal, a second input terminal for receiving a corresponding rear latch enabling signal, and an output terminal for outputting a rear latch datum to a corresponding bank, wherein the rear latch circuit generates the rear latch datum according to the intermediate signal and the corresponding rear latch enabling signal; wherein number of the plurality of banks is equal to number of the plurality of rear latch circuits, and only one rear latch enabling signal is enabled at any time.