Patent ID: 7206216

Claim:
A semiconductor device comprising a memory block, an input/output circuit connected to an external terminal, and one semiconductor substrate on which said memory block and said input output circuit are formed, wherein: said memory block includes a plurality of word lines, a plurality of bit lines crossing said plurality of word lines, and a plurality of memory cells provided at respective intersections of said plurality of word lines and said plurality of bit lines; each of said plurality of memory cells includes a first MOS transistor, a memory device, a first node to which a gate of said first MOS transistor is connected, a second and third nodes between which a source-drain path and said memory device are connected; said memory device has a resistance value which changes in accordance with a difference of currents flowing thereto; said first node is connected to a corresponding one of said plurality of word lines; said second node is connected to a corresponding one of said plurality of bit lines; said input/output circuit has a second MOS transistor connected to said external terminal; and an absolute value of a threshold voltage of said first MOS transistor is lower than an absolute value of a threshold value of said second MOS transistor.