Patent ID: 7804432

Claim:
An integrated circuit device comprising: an amplifier circuit that includes first to Nth (N is an integer equal to or larger than two) amplifiers and receives an input signal, the first to Nth amplifiers being cascaded; an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit; first to Nth offset adjustment registers that are provided corresponding to the first to Nth amplifiers and store first to Nth offset adjustment data, the first to Nth offset adjustment data being used to perform an offset adjustment of the first to Nth amplifiers; first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment based on the first to Nth offset adjustment data; first to Nth offset value storage sections that store first to Nth offset value data, the first to Nth offset value data being offset value data of the first to Nth amplifiers; and a control circuit that calculates the first to Nth offset adjustment data based on the first to Nth offset value data stored in the first to Nth offset value storage sections, and sets the first to Nth offset adjustment data in the first to Nth offset adjustment registers.