Patent ID: 7138842

Claim:
An integrated circuit, comprising: a first latch circuit having a first terminal coupled to receive an input signal, a second terminal, and a power supply voltage terminal for receiving a first power supply voltage; a second latch circuit having a first terminal coupled to the second terminal of the first latch circuit, and a power supply voltage terminal for receiving the first power supply voltage; and a third latch circuit having a first terminal coupled to the second latch circuit, a second terminal coupled to the first latch circuit, and a power supply voltage terminal for receiving a second power supply voltage, the first power supply voltage being controlled separately from the second power supply voltage; wherein during a low power mode of the integrated circuit, the third latch circuit for storing a logic state corresponding to a logic state received at the first terminal of the third latch circuit, and the first power supply voltage is not provided to the first and second latch circuits while the second power supply voltage is provided to the third latch circuit.