Patent ID: 7274738

Claim:
In a telecommunications system, an arithmetic logic unit (ALU) for processing at least one input signal, said at least one input signal including a digital signal representative of an analog signal, said ALU comprising: a standard ALU component for performing standard ALU operations on said at least one input signal; an encoding unit for selectively performing compression on said digital signal; a decoding unit for selectively performing decompression on said digital signal; an instruction decoder for receiving and decoding an ALU instruction; an output selector in parallel communication with each of said standard ALU, said encoding unit, and said decoding unit for receiving results from each of said standard ALU, said encoding unit, and said decoding unit; and said output selector including circuitry for receiving an instruction from said ALU, interpreting said ALU instruction, and for selecting a result from one of the received result from said standard ALU, said encoding unit, and said decoding unit according to the received instruction from said ALU.