Patent ID: 8495544

Claim:
A computer-implemented method for calculating crosstalk delay of an integrated circuit the method comprising: receiving information describing one or more aggressor cells comprising an aggressor cell output pin and at least one or more aggressor cell input pins, and one or more victim cells comprising a victim cell output pin and at least one or more victim cell input pins; determining, by a computer, an overall non-crosstalk voltage variation, the overall non-crosstalk voltage variation comprising a first output voltage waveform of a victim logic cell as a function of one or more process variation parameters when no aggressor cells are present; determining, by the computer, an overall crosstalk noise voltage variation, the overall crosstalk noise voltage variation comprising a second output voltage waveform of the victim logic cell as a function of one or more process variation parameters when at least one or more aggressor cells are present; determining a rate of change of the overall non-crosstalk voltage variation; determining a rate of change of the overall crosstalk noise voltage variation; and determining, by the computer, at least one or more crosstalk delay sensitivities by calculating a ratio between the sum of the overall non-crosstalk voltage variation and the overall crosstalk noise voltage variation, and the sum of the rate of change of the overall non-crosstalk voltage variation and the rate of change of the overall crosstalk noise voltage variation.