Patent ID: 8680887

Claim:
A nonvolatile configuration memory comprising: first and second output nodes; a first P-channel FET having a gate connected to the second output node, a source applied to a first potential, and a drain connected to the first output node; a second P-channel FET having a gate connected to the first output node, a source applied to the first potential, and a drain connected to the second output node; a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a storage layer which stores data in a nonvolatile manner; and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a storage layer which stores data in a nonvolatile manner, wherein threshold values of the first and second N-channel FETs change in according to the data stored in the first and second N-channel FETs respectively.