Patent ID: 7706205

Claim:
A semiconductor device comprising: a plurality of static memory cells, each of which has a first power supply node, a second power supply node and MOS transistors having gates and drains cross-coupled to each other; a first power supply line coupled to the first power supply nodes of the plurality of static memory cells; a second power supply line coupled to the second power supply nodes of the plurality of static memory cells; and a first control circuit coupled to the first power supply line and adapted to switch a state of potential of the first power supply line, wherein, when a first static memory cell of the plurality of static memory cells is selected, the state of potential of the first power supply line coupled to the first static memory cell is switched under control of the first control circuit from the state of potential of the first power supply line coupled to the first static memory cell when the first static memory cell is not selected, and further comprising: a peripheral circuit to read or write the static memory cells, wherein an absolute value of a threshold voltage of a MOS transistor used in the peripheral circuit is smaller than an absolute value of a threshold voltage of the MOS transistors having gates and drains cross-coupled to each other of the static memory cells.