Patent ID: 8350293

Claim:
A field effect transistor having a metal-oxide-semiconductor structure, the field effect transistor comprising: a buffer layer formed on a substrate; a p-type nitride compound semiconductor layer formed on the buffer layer; an n-type contact region formed by ion implantation under a source electrode and a drain electrode; and an electric-field reducing layer made of an n-type nitride compound semiconductor and epitaxially-grown on the p-type nitride compound semiconductor layer, wherein the electric-field reducing layer has a carrier density lower than that of the n-type contact region, the electric-field reducing layer includes a first end portion contacting with the n-type contact region and a second end portion overlapping a gate electrode, the n-type contact region formed under the drain electrode is formed in the electric-field reducing layer, and the carrier density of the electric-field reducing layer varies in different regions of the electric-field reducing layer to increase a resistance of the electric-field reducing layer in a direction from the first end portion toward the second end portion.