Patent ID: 6868490

Claim:
Apparatus for providing efficient context switching between software tasks in a merged sequence processor (SP) and processor element (PE) processor environment, each software task comprising a plurality of instructions, the merged SP and PE processor environment configurable to be in a first array configuration or a second array configuration, the apparatus comprising: a first set of registers stored in an SP register file; a second set of registers stored in a PE register file; an execution unit that is shared to execute SP instructions and PE instructions; a fetch controller for fetching a plurality of instructions; an instruction register for receiving each fetched instruction, the instruction register providing control information for the execution of a fetched instruction, the instruction register having a sequence processor/processing element (SP/PE) selection bit set by a fetched instruction whereby the SP/PE selection bit value can change with each fetched instruction; and a processor state register having a context select bit (CSB), a specific instruction out of the plurality of instructions setting the CSB value, the CSB being independent of bits in the instruction register, the CSB value persisting between the fetched instructions, the CSB value in conjunction with the SP/PE selection bit value selecting a context of a first software task utilizing the first army configuration or a context of a second software task utilizing the second array configuration, the first array configuration including at least one register from the second set of registers to execute sequential instructions on the execution unit, the second array configuration including at least one register from the first set of registers to execute sequential instructions on the execution unit.