Patent ID: 7968450

Claim:
A method of fabricating a hybrid interconnect structure comprising the steps of: depositing a first dielectric and patterning trenches and vias in said first dielectric on a substrate; filling said trenches and vias with a conductive barrier and a higher conductivity fill material to form interconnect wiring structures; forming a first block out resist pattern to expose only a first set of interconnect wiring structures in a first region of the substrate wherein said first region includes SRAM cells; etching said first dielectric from between said first set of interconnect wiring structures located in said first region to form etched gaps and stripping the photoresist; filling the etched gaps between said first set of interconnect wiring structures with a second dielectric having a dielectric constant higher than that of the first dielectric and planarizing it to form a coplanar structure; forming a second blockout photoresist pattern that exposes a second region of the substrate comprising a second set of interconnect wiring structures wherein said second region comprises all the area except the SRAM cells, dicing channels and the bond and test pads; etching said first dielectric from between said second set of interconnect wiring structures to form etched gaps and stripping the photoresist; and filling the etched gaps between said second set of interconnect wiring structures with a third dielectric having a lower dielectric constant than that of the first dielectric and planarizing to form a coplanar structure.