Patent ID: 8456148

Claim:
A regulator circuit comprising: a first terminal supplied with a first potential; a second terminal having a second potential, wherein the first potential is different from the second potential; a bias circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a resistor, and a bypass capacitor; and a voltage regulator electrically connected to the first terminal, the second terminal, and the bias circuit, wherein a gate of the first transistor is electrically connected to a gate of the second transistor, one of a source and a drain of the first transistor is electrically connected to the second terminal, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor, wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor, and one of a source and a drain of the fourth transistor, and the other of the source and the drain of the second transistor is electrically connected to the second terminal, wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, and the other of the source and the drain of the third transistor is electrically connected to the first terminal, wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the third transistor, wherein one terminal of the resistor is electrically connected to the gate of the third transistor, and the other terminal of the resistor is electrically connected to the first terminal, and wherein the bypass capacitor is provided between a node connected to the gate of the fourth transistor and one of the first terminal and the second terminal.