Patent ID: 6947304

Claim:
A memory module comprising: a substrate having wiring traces formed thereon, the substrate being a size for inserting into a memory module socket to receive input signals; a plurality of memory chips for storing data, including a first plurality of the memory chips and a second plurality of the memory chips; an input buffer, receiving an input signal from the memory module socket, the input buffer producing two outputs for the input signal, a first output and a second output; a first enlarged trace, between the first output and a first trace-junction, driven by the input buffer, the first enlarged trace having an enlarged cross-section greater than a minimum cross-section for the wiring traces on the memory module; a first distribution trace and a second distribution trace, each coupled to the first trace-junction, for electrically connecting to inputs to the first plurality of the memory chips; a second enlarged trace, between the second output and a second trace-junction, driven by the input buffer, the second enlarged trace having the enlarged cross-section greater than the minimum cross-section for the wiring traces on the memory module; and a third distribution trace and a fourth distribution trace, each coupled to the second trace-junction, for electrically connecting to inputs to the second plurality of the memory chips; wherein the first, second, third, and fourth distribution traces each has a cross-section substantially smaller than the enlarged cross-section of the first enlarged trace, whereby different cross-sections of wiring traces are used for inputs and outputs of the first trace-junction.