Patent ID: 6977405

Claim:
A semiconductor memory with semiconductor memory cells, comprising: a substrate, the substrate having a substrate surface; a first trench, the first trench being arranged in the substrate and having a lower region, a central region and an upper region, the first trench having a trench capacitor formed therein; a first direction and a second direction, the second direction crossing the first direction; a second trench, the second trench being arranged beside the first trench with respect to the first direction in the substrate, the second trench having a trench capacitor formed therein; a first longitudinal trench and a second longitudinal trench, the first and second longitudinal trenches being relatively arranged parallel to one another and extend along the first direction, the first longitudinal trench adjoining the first trench and the second trench, the second longitudinal trench adjoining the first trench and the second trench on the opposite side of the first trench and the second trench with respect to the first longitudinal trench; an active region, the active region being arranged between the first longitudinal trench, the second longitudinal trench, the first trench and the second trench; a first spacer word line, the first spacer word line being arranged in the first longitudinal trench laterally at the active region; a second spacer word line, the second spacer word line being arranged in the second longitudinal trench laterally at the active region; conductive connecting webs, the webs being arranged in the upper region of the first trench or of the second trench as connections between the first spacer word line and the second spacer word line; and a vertical selection transistor, which has a source doping region, a drain doping region and a channel, the channel being arranged between the source doping region and the drain doping region in the active region and the source doping region being connected to the trench capacitor and the drain doping region being connected to a bit line, the bit line being arranged on the substrate and crossing the first spacer word line wherein the thickness of the connecting webs in the direction of the first spacer word line is less than half the width of the first trench in the direction of the first spacer word line.