Patent ID: 6973608

Claim:
A method of fault tolerant operation of a field programmable gate array during normal on-line operation comprising the steps of: configuring said field programmable gate array into a self-testing area and a working area, said working area maintaining normal operation of the field programmable gate array; identifying at least one faulty programmable interconnect resource of a programmable interconnect network utilized in at least one of a plurality of signal paths and positioned within said self-testing area; determining whether utilization of said faulty programmable interconnect resource is compatible with an intended operation of the field programmable gate array; and reconfiguring at least a portion of programmable interconnect resources, including the utilization of said at least one faulty programmable interconnect resource, if said at least one faulty programmable interconnect resource is not compatible with the intended operation of the field programmable gate array, whereby said at least one faulty programmable interconnect resource may be utilized within operating configurations which are compatible with the intended operation of the field programmable gate array to provide fault tolerant operation of the field programmable gate array.