Patent ID: 8088656

Claim:
A method, comprising; simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate; simultaneously forming a third doped region of said electrostatic discharge protection device and a fourth doped region of a first low-power device by performing a second ion implantation into said semiconductor substrate, said first ion implantation different from said second ion implantation, said electrostatic discharge device being a different device type from said high-power device and said electrostatic discharge device having a different structure from said high-power device; simultaneously forming a fifth doped region of said electrostatic discharge protection device and a sixth doped region of a second low-power device by performing a third ion implantation into said semiconductor substrate, said third ion implantation different from said first, and second ion implantations; said first low-power device is a CMOS logic PFET, said second low-power device is a CMOS logic NFET, said high-power device is a lateral double diffused field effect transistor, and said electrostatic protection device is a shunt transistor; and said first doped region is a P-well of said shunt transistor, said second doped region is a P-well of said lateral double diffused field effect transistor, said third doped region is a P-body contact of said shunt transistor, said fourth doped region is a source/drain of said CMOS logic PFET, said fifth doped region is a source/drain of said shunt transistor, and said sixth doped region is a source/drain of said CMOS logic NFET.