Patent ID: 8392651

Claim:
A microprocessor comprising: an N-way cache, N being an integer greater than one; and a way prediction logic configured to receive an address and predict a first one of the N cache ways in which data associated with the address is likely to be stored; said way prediction logic further configured to supply an enabling signal to said predicted first one of the N cache ways, said way prediction logic further configured not to supply the enabling signal to a remaining (N−1) of the cache ways wherein said way prediction logic comprises: a way prediction array having a plurality of entries, each entry in the array configured to store data representative of an address identifying a cache entry, data representative of a cache way, and one or more validation bits, wherein at least one of the validation bits is associated with the data representative of the cache way; and a way prediction control unit configured to compare one or more bits of the received address with one or more bits of each of the addresses stored in the array to detect an address match, said way prediction control unit configured to generate the enabling signal in accordance with the detected address match and further in accordance with the stored validation bits wherein said way prediction logic is further configured to update the data representative of the cache way and the one or more validation bits in the way prediction array when a cache hit is detected.