Patent ID: 8877627

Claim:
A method for forming a memory array comprising: forming insulator over a substrate, the insulator formed in one or more first regions for non-volatile storage elements and in one or more second regions for transistors; forming a P− semiconductor region over the insulator in the one or more first regions and in the one or more second regions; forming a first N+ semiconductor region over the P− semiconductor region in the one or more first regions and in the one or more second regions; transforming the P− semiconductor region in the one or more second regions into a second N+ semiconductor region; forming floating gates for non-volatile storage elements in the one or more first regions from the P− semiconductor region and the first N+ semiconductor region that remains in the one or more first regions; and forming transistor gates in the one or more second regions, the transistor gates including portions of the second N+ semiconductor region and portions of the first N+ semiconductor region in the one or more second regions.