Patent ID: 7365784

Claim:
A sample and hold circuit for an imager, comprising: a selection circuit for selectively coupling a common node to a pixel output column line and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals, said selection circuit for selectively uncoupling said common node from said pixel output column line and for selectively coupling said first and second storage elements through said common node to transfer said stored respective pixel output signals to an output stage, said selection circuit selectively couples said common node to a first voltage, said selection circuit further comprises: a first switch, disposed between said common node and said column line; a second switch, disposed between said common node and said first storage element; a third switch, disposed between said common node and said second storage element; a second selection circuit for selectively coupling a second voltage to said first storage element; and a third selection circuit for selectively coupling said second voltage to said second storage element.