Patent ID: 7504302

Claim:
A process of forming a non-volatile memory cell comprising: forming an active region over a substrate; forming a first layer over the active region, wherein the first layer comprises a charge storage layer; forming a second layer over the first layer, wherein the second layer has a different composition compared to the first layer; forming a first etch mask over the second layer, wherein exposed portions of the first and second layers overlie the active region and are not covered by the first etch mask; etching part of the exposed portion of the second layer; etching part of the exposed portion of the first layer to leave a residual portion including a floating gate electrode and first capacitor electrodes, wherein the floating gate electrode overlies the active region, and the first capacitor electrodes are adjacent to opposite sides of the floating gate electrode; removing the first etch mask; forming a dielectric layer over the residual portion of the first layer; and forming a control gate electrode over the dielectric layer, wherein, from a top view in a finished device, a combination of the floating gate electrode and first capacitor electrodes laterally surrounds all sides of the active region.