Patent ID: 7945875

Claim:
A computer implemented method for conversion of a synthesized netlist circuit design from a first form into a circuit design of a second form having separable frequency/voltage domains suitable for power consumption control comprising the steps of: grouping registers within the circuit design into hierarchies of a same frequency/voltage domain; grouping input and gated clocks within the circuit design including fanin and fanout combinational logic associated with a corresponding hierarchy of registers wherein all data paths between registers of a same hierarchy are within said same hierarchy; identifying cells for duplication in the circuit design, including backward traversal from the outputs of each frequency/voltage domain, and recursively marking combinational cells on the path until all inputs of a combinational cell go back to registers or inputs of same frequency/voltage domain; duplicating the identified cells by insertion of new cells corresponding to said cells identified for duplication, said new cells connected to each other corresponding to said cells identified for duplication thereby forming a new hierarchy; creating new connections within said new hierarchy; removing redundant logic elements; and inserting level shifters and isolation cells in circuit connections which cross boundaries between frequency/voltage domains; and wherein said steps of grouping registers, grouping input and gated clocks, identifying cells for duplication, duplicating the identified cells, creating new connections, removing redundant logic elements, and inserting level shifters and isolation cells are computer implemented.