Patent ID: 7417488

Claim:
A memory circuit comprising: an inductive element to receive an input voltage; a switching transistor coupled to the inductive element; a capacitive element to store energy based on the switching transistor; and a regulation circuit to select one of a plurality of duty cycle signals and to provide a control signal to the switching transistor based on the selected one of the duty cycle signals, and the inductive element, the switching transistor and the regulation circuit to provide an output voltage at an output node, the regulation circuit including: a resistor ladder to couple to the output node to provide a plurality of different voltages based on the output voltage at the output node, a bandpass circuit to provide a reference voltage, a plurality of comparators to compare voltages from the resistor ladder with the reference voltage and to provide output signals, a first multiplexer to receive the corresponding output signals from the plurality of comparators and to provide output signals based on the received output signals, a clock generator circuit to generate the plurality of duty cycle signals, and a second multiplexer to select the one of the plurality of the duty cycle signals as the control signal.