Patent ID: 6956410

Claim:
A comparator circuit with controlled outer transistor stage bias currents, comprising: an outer transistor stage, including: a first transistor including a signal input terminal, a first output terminal and a second output terminal; and a second transistor including a reference input terminal, a first output terminal and a second output terminal, wherein the first and second output terminals of the first and second transistors are coupled across a power source, and wherein the first and second transistors of the outer transistor stage provide drive currents to transistors of an inner transistor stage; bias current control circuitry for controlling bias currents associated with the first and second transistors, wherein the bias current control circuitry minimizes the bias currents when a difference between a magnitude of an input signal at the signal input terminal and a magnitude of a reference signal applied to the reference input terminal is greater than a predetermined value, and wherein the bias current control circuitry increases the bias currents associated with the comparator circuit when the difference between the magnitude of the input signal at the signal input terminal and the magnitude of the reference signal at the reference input terminal is less than the predetermined value; and a blinding timer discharge current source configured to limit current drawn by a capacitor coupled to the input signal terminal being charged, wherein the blinding timer discharge current source is coupled across the capacitor.