Patent ID: 6873004

Claim:
A single-transistor virtual ground memory cell comprising: a semiconductor substrate; a control gate; a floating gate disposed under the control gate and separated therefrom by a dielectric; a first relatively lightly doped region disposed in the semiconductor substrate and comprising a source region; a first relatively heavily doped region disposed in the semiconductor substrate and comprising a drain region; and a channel region disposed in the semiconductor substrate under the floating gate and separated therefrom by a tunnel dielectric, the channel region being disposed between the source region and the drain region; wherein the first relatively lightly doped region is merged with a second relatively heavily doped region disposed in the substrate, and the first relatively heavily doped region is merged with a second relatively lightly doped region in the substrate; wherein the merged first relatively lightly doped region and second relatively heavily doped region are not contiguous with an overlying thermal oxide in proximity to the source region; and wherein the merged first relatively heavily doped region and second relatively lightly doped region are not contiguous with an overlying thermal oxide in proximity to the drain region.