Patent ID: 8183092

Claim:
A method of fabricating a stacked semiconductor structure, comprising the steps of: mounting and electrically connecting at least one semiconductor chip to a first substrate, disposing on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip; mounting a second substrate having a first surface and a second surface opposite to the first surface to the supporting members via the second surface, wherein a portion of the first surface is covered by a tape; connecting electrically the first and second substrates through bonding wires, wherein the first substrate having the second substrate stacked thereon is mounted inside a mold having an upper mold, with an inner top side of the upper mold abutting against the tape disposed on the second substrate; and performing a molding process to form on the first substrate an encapsulant that encapsulates the semiconductor chip, the supporting members, the second substrate, and the bonding wires, wherein a top surface of the tape is exposed and not covered by the encapsulant.