Patent ID: 8135909

Claim:
A system having a processor for executing a first program containing a first group of instructions, and a second program containing a second group of instructions, and a third program containing a third group of instructions, the system comprising: a main memory configured to store the first program, the second program and the third program; a cache memory configured to store the first program, the second program and the third program; a register configured to store one of: a first start address in the first program at which preloading of the second program starts during execution of the first program, and a second start address in the second program at which preloading of the third program starts during execution of the second program; and a preloader configured to: start to preload the second program from the main memory to the cache memory by using a program counter for preloading, when an execute address of the first program matches the first start address during execution of the first program, complete the preloading of the second program before execution of the second program, while executing a remaining portion of the first program, start to preload the third program from the main memory to the cache memory by using a program counter for preloading, when an execute address of the second program matches the second start address during execution of the second program, and complete the preloading of the third program before execution of the third program, while executing a remaining portion of the second program.