Patent ID: 7636261

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and in columns, the memory cell array having a plurality of bit lines connected to the plurality of memory cells arranged in the columns; n (n is a natural number equal to or larger than 2) data storage circuits connected to the respective bit lines, each of the data storage circuits having a first storage storing 1 bit data; a common interconnection connected to the n first storage sections; and a control section coupled to the common interconnection, wherein the control section reads data from k (k<n and is not 0) of the data storage circuits via the common interconnection when the data of a selected data storage circuit of the n data storage circuits are output to a data I/O line, wherein each of the n data storage circuits includes a second storage section storing 1 bit data, the k (k<n and is not 0) of the n second storage sections store first logical data, and (n−k) of the n second storage sections store second logical data, and the control section reads data from k (k<n and is not 0) of the data storage circuits which store the first logical data in the second storage section via the common interconnection.