Patent ID: 7908532

Claim:
A method of determining the location of a failure in a scan chain comprising the testing steps as follows: (a) starting; (b) selecting an IEEE 1149.1 compatible Joint Test Action Group (JTAG) functional test function/exercisor Logic Built-In Self-Test (LBIST) test pattern set; (c) running the selected JTAG functional test function/exercisor LBIST test pattern set through scan chains with various different flavors of LBIST functional clock sequences in a serial or a lateral broadside insertion manner across all latch system ports; (d) unloading said scan chains and store fail data therefrom into a file; (e) examining said fail data to find a last switching latch location; (f) performing a comparison of said last switching latch location with data stored from a previous run or expected results from a good reference device or a good operating region; and if results of said comparison are consistent then ending said testing steps as said location of said failure has been identified; but if results of said comparison are inconsistent, then repeating steps (b)-(f) to collect more fail data until consistent results are obtained.