Patent ID: 8782302

Claim:
An apparatus, comprising: a system-on-chip including a plurality of partitions coupled together by at least one peripheral bus such that the plurality of partitions are daisy chained together, wherein each partition comprises: a routing node having a node input configured to receive a plurality of transactions intended for a plurality of different target peripheral devices, each transaction including a target peripheral device address which specifically identifies one of the target peripheral devices within the system-on-chip, said routing node having a plurality of node outputs, wherein each node output is identified by a corresponding output identifier and wherein the node outputs include a first output coupled to another partition by the peripheral bus and a second output; at least one target peripheral device located within the partition, said at least one target peripheral device comprising an input coupled to the second output of said routing node; and an address converter configured to convert the target peripheral device address associated with each transaction to an output identifier for application to said routing node, said output identifier comprising a first identifier if the target peripheral device address is for a target peripheral device located on another partition and comprising a second identifier if the target peripheral device address is for said at least one target peripheral device located within the partition; wherein said routing node is configured to route said received transactions to the first and second outputs of the routing node whose output identifier corresponds to said first and second identifiers received from the address converter.