Patent ID: 7672455

Claim:
A block cipher hardware device used in encrypting and decrypting information in a cryptographically secured digital communication system, the block cipher device comprising: plural encryption stages that are computationally a function of an input data block, a control data block, a key data sub-block, and a key scheduler for randomizing the key data sub-block, the key scheduler further comprising: a first shift register; a first means for randomizing a portion of the key data block using the said first shift register; a first modulo two summing combiner for serially combining a serial output from the first shift register and the serial output from said first randomizing means to provide a first combined data output; a first key data sub-block derived from the contents of said first shift register; a second shift register; a second means for randomizing a portion of the key data block using the said second shift register; a second modulo two summing combiner for serially combining the serial output from the second shift register and the serial output from said second randomizing means to provide a second combined data output; a second key data sub-block derived from the contents of the second shift register; a third modulo two summing combiner for combining said first key data sub-block and said second key data sub-block to produce a third key data sub-block; a first function unit that is computationally a function of the second key data sub-block for providing a fourth key data sub-block; and circuit means for providing said first, third and fourth key data sub-blocks to different ones of said plural encryption stages.