Patent ID: 7738460

Claim:
A hardware-implemented packet header generation circuit configured to receive data packets and information associated with descriptor words that were previously prepended to the data packets, the descriptor words indicating tasks to be performed by the packet header generation circuit, the hardware-implemented packet header generation circuit comprising: an input node; a plurality of descriptor registers having one or more corresponding information inputs coupled to the input node, and configured to capture and store the information associated with the descriptor words; a control signal generator circuit configured to receive the data packets from the input node and the information associated with the descriptor words from the plurality of registers, and configured to generate the packet headers using the information associated with the descriptor words; a data encryption flag generator circuit configured to receive a first set of one or more control signals from the control signal generator; and a cyclic redundancy code (“CRC”) flag generator circuit configured to receive a second set of one or more control signals from the control signal generator; whereby the control signal generator circuit is configured to control the data encryption flag generator circuit to generate an encryption flag for a data packet when the corresponding information associated with the descriptor words indicates that the data packet is to be encrypted; whereby the control signal generator circuit is configured to control the CRC flag generator circuit to generate a CRC flag for the data packet when the corresponding information associated with the descriptor words indicates that the data packet is to include a CRC; and whereby the data packets and corresponding headers are forwarded for potential CRC processing and/or encryption, and thereafter for transmission over a wireless communication network.