Patent ID: 7411427

Claim:
A circuit comprising: a first low-pass delay element that receives a first signal and outputs a first delayed version of the first signal; a first logic gate that receives the first signal and the first delayed version of the first signal; a second low-pass delay element that receives the first signal and outputs a second delayed version of the first signal; a second logic gate that receives the first signal and the second delayed version of the first signal; a sequential logic element that is set in response to a signal output by the first logic gate, and that is reset in response to a signal output by the second logic gate; a third logic gate that has a first input lead and a second input lead, the first signal being present on the first input lead, the second input lead being coupled to receive a signal output by the sequential logic element; a fourth logic gate that has a first input lead and a second input lead, the first signal lead being present on the first input lead, the second input lead being coupled to receive the signal output by the sequential logic element; and multiplexing circuitry that has a first input lead, a second input lead, a third input lead, and an output lead, wherein the first input lead is coupled to receive a signal output by the third logic gate, wherein the second input lead is coupled to receive the signal output by the sequential logic element, and wherein the third input lead is coupled to receive a signal output by the fourth logic gate.