Patent ID: 8144089

Claim:
A liquid crystal display device comprising: a display region in which a plurality of pixel regions are arranged in a matrix, each of the pixel regions including: a gate line and a data line crossing one another; a common voltage line arranged in parallel to the gate line; a first thin film transistor connected to and formed at the crossing of the gate line and the data line; a pixel electrode connected to the first thin film transistor and formed at the crossing of the gate line and the data line to display an image corresponding to a data voltage provided from the data line through the first thin film transistor; a common electrode connected to the common voltage line for forming an electric field with the pixel electrode; and a non-display region outside the display region including a gate pad region formed at an end portion of each gate line and a data pad region formed at an end portion of the data line, wherein each gate pad region includes a dummy pixel, the dummy pixel is configured with the same circuit as the pixel region, the dummy pixel includes a second thin film transistor directly connected to the gate line and the common voltage line, respectively, wherein the second thin film transistor is a switch element for applying a common voltage to the common voltage line of the pixel region, wherein the gate pad region includes a dummy common voltage line arranged in parallel to the data line and connected to the second thin film transistor, wherein the dummy common voltage line is connected to the common electrodes of the display region, the common voltage supplied to the dummy common voltage line is supplied to the common electrodes of the display region when the second thin film transitor is turned on, wherein the data voltage charged at the pixel electrode drops by an amount equal to a kickback data voltage caused by a parasitic capacitance of the first thin film transistor, wherein the common voltage charged at the common electrode drops by an amount equal to a kickback common voltage caused by a parasitic capacitance of the second thin film transistor, wherein the second thin film transistor has substantially the same capacitance as that of the first thin film transistor, wherein the first thin film transistor has substantially the same parasitic capacitance as that of the second thin film transistor, wherein the kickback data voltage dropped from a data voltage passing through the first thin film transistor is substantially equal to the kickback common voltage dropped from the common voltage passing through the second thin film transistor, wherein the first and second thin film transistors are simultaneously switched by a scan signal supplied to the gate line.