Patent ID: 7552408

Claim:
In a computer readable medium storing a plurality of design rule check instructions, wherein the design rule check instructions being performed on a layout for an electronic circuit embodied on a substrate, the design rule check instructions comprising the steps of: (a) providing at least a first set of design rules for a first region of the layout within a first layer, including a first minimum spacing between first signal lines situated over the substrate; (b) providing at least a second set of design rules for a second region of the layout within the first layer including a second minimum spacing between second signal lines situated over the substrate; wherein said first region and said second region correspond to different types of circuitry to be embodied in the electronic circuit, and said first minimum spacing differs from said second minimum spacing; (c) processing a layer of the layout such that any said first region is checked in accordance with at least said first set of design rules, and said second region is checked in accordance with at least said second set of design rules; and generating said second set of design rules by modifying said first set of design rules in accordance with differences in sizings, spacings and/or tolerances manufacturable between said first region and said second region.