Patent ID: 7599489

Claim:
A processor for executing a secure hash algorithm (SHA) computation on a message, comprising: a core having a first execution unit and a second execution unit, wherein an output of the first execution unit is connected to an input of the second execution unit, wherein the first execution unit is defined to perform a message schedule computation on a data block of the message to generate an expanded representation of the data block from a first number of bits to a larger number of bits, wherein the first execution unit is defined to communicate a partial result of the expanded version of the data block through its output to the input of the second execution unit when the partial result becomes available and prior to completion of the message schedule computation on the data block, wherein the second execution unit is defined to perform a compression function on the partial result received from the first execution unit in parallel with the first execution unit continuing the message schedule computation on the data block, whereby the compression function is defined to iteratively consume the partial result.