Patent ID: 6978391

Claim:
An asynchronous bus interface circuit adapted to be arranged between an asynchronous bus and a macro circuit operating in synchronization with an operational clock, said interface circuit comprising: an external register for temporarily storing data transmitted through said asynchronous bus, in response to a write-request signal transmitted through said asynchronous bus, and outputting the stored data; a synchronizing buffer for temporarily storing data output from said external register, and outputting the data in synchronization with the operational clock; an arbitration circuit for initiating an internal register-write signal generating cycle in response to the write-request signal, the internal register-write signal generating cycle causing generating and outputting of an internal register-write signal in synchronization with the operational clock; and an internal register for inputting and temporarily storing the data output from said synchronizing buffer in response to the internal register-write signal, and outputting the data to the macro circuit in synchronization with the operational clock, wherein said arbitration circuit cancels an internal register-write signal generating cycle under execution without outputting the internal register-write signal, upon reception of a second write-request signal.