Patent ID: 7290089

Claim:
An apparatus for controlling execution of cache access instructions within a processor, comprising: an associative cache memory accessible either in a first mode or in a second mode having increased latency over the first mode; and a cache controller coupled to the associative cache memory and, during execution of a sequence of instructions, determining whether one or more cache access instructions may be executed with increased latency without incurring a substantial performance penalty for execution of the sequence of instructions, and responsive to determining that at least one cache access instruction within the one or more cache access instructions may be executed with increased latency but without incurring a substantial performance penalty, dynamically setting access of the cache memory to the second mode for the at least one cache access instruction, wherein the cache controller determines whether the one or more cache access instructions may be executed with increased latency but without incurring a substantial performance penalty by determining whether the sequence of instructions comprises a hardware loop.