Patent ID: 8775744

Claim:
A switch, comprising: a write port configured to receive a plurality of data units within a single switching cycle of the switch; a plurality of memories, first selected ones of the plurality of memories constituting a plurality of memory groups and second selected ones of the plurality of memories constituting a plurality of memory subsets, each of the plurality of memory groups including a corresponding one of the plurality of memory subsets, where the write port supplies each of a plurality of copies of the plurality of data units to a corresponding one of the plurality of memory subsets; a plurality of multiplexers, each of the plurality of multiplexers being associated with a corresponding one of the plurality of memory groups, each of the plurality of multiplexers being configured to selectively supply one of the plurality of copies of the data units from one of the plurality of groups of memories; and a read port associated with a subset of the plurality of multiplexers, the read port configured to receive, within a single switching cycle of the switch, one of the plurality of copies of a plurality of the data units from different ones of the plurality of multiplexers, where the received plurality of data units include a first data unit corresponding to an even numbered time slot within a sequence of time slots and a second data unit corresponding to an odd numbered time slot within the sequence of time slots, the switch further including: even memory control logic configured to lookup first information identifying the write port and a time slot number corresponding to the write port based on a desired even time slot number that is to be output from the switch; and odd memory control logic configured to lookup second information identifying the write port and a time slot number corresponding to the write port based on a desired odd time slot number that is to be output from the switch.