Patent ID: 8667300

Claim:
An apparatus for processing an image, comprising: a first acquisition device to acquire encrypted video data; a decryption device to decrypt the encrypted video data as first image data; a first secure memory to restrict an access from an outside of the apparatus to the first secure memory; a first image processing module memory to store a first image processing module used for executing image processing; a first converter to decide whether the first image processing module includes an output processing to an outside of the first secure memory, and, when the first image processing module includes the output processing, converts the first image processing module to a second image processing module including the output processing invalidated; a first processor to process the first image data using the second image processing module, by accessing the first secure memory, and generate second image data; a second secure memory to restrict an access from the outside of the apparatus to the second secure memory; a first rendering module memory to store a first rendering module used for executing rendering processing; a second converter to decide whether the first rendering module includes an output processing to an outside of the second secure memory, and, when the first rendering module includes the output processing, converts the first rendering module to a second rendering module including the output processing invalidated; a rendering device to render the second image data using the second rendering module, by accessing the second secure memory; and a display device to display the second image data rendered; and wherein, when an address of output destination of data from the first image processing module is not an address in the first secure memory, the first converter decides that the first image processing module includes the output processing to the outside of the first secure memory; and wherein the converting the first image processing module to a second image processing module includes the first converter initializing a variable “i” by substituting a value for “i” and if a confirmation of all output IF (interface) is not completed, the first converter confirms whether an address of an output destination of an output IFi is an address in the first secure memory, incrementing the variable “i” when the address of the output destination of the output IFi is the address in the first secure memory and the first converter repeats process of confirming the output IF; and if the address of the output destination of the output IFi is not the address in the first secure memory, the first converter invalidates an output of data from the output IFi.