Patent ID: 7438998

Claim:
A method of manufacturing a semiconductor device including a wiring pattern in the form of a linear line having an intermediate portion with a locally different line width, the wiring pattern being formed by using a resist pattern, the method comprising: forming the resist pattern through an exposure step using a mask pattern prepared by dividing the mask into a discontinuous pattern having a simple line portion and a separate rectangular pattern portion having a different line width, a first end of the simple line portion and a first side of the rectangular pattern portion being separated from one another by a slit having a predetermined separation width of not larger than 0.22 ×λ/NA, wherein λ represents a wavelength of exposure light, and NA represents a numerical aperture of a projection lens; and forming said wiring pattern having a continuous pattern of a simple line portion and a rectangular pattern portion, wherein: the mask pattern further includes a bias pattern for correcting extreme narrowing of the pattern in a position of the mask layout where excessive light interference occurs, said bias pattern extending across said simple line portion and being spaced from said first end.