Patent ID: 7439593

Claim:
A semiconductor device comprising: an isolation layer disposed in a semiconductor substrate, the isolation layer defining an active region; a gate pattern disposed on the active region; source/drain regions disposed in the active region at both sides of the gate pattern; sidewall spacers disposed on sidewalls of the gate pattern, the sidewall spacers comprising an inner spacer having an L-shaped cross-section that is formed on a sidewall of the gate pattern and neighboring the gate pattern, and an outer spacer having a curved sidewall that is formed on the inner spacer and covering entire sidewalls of the gate pattern; a blocking insulation layer disposed on the isolation layer and on a portion of the active region neighboring the isolation layer, the blocking insulation layer spaced apart from the sidewall spacers; and a first silicide layer disposed on the source/drain regions between the blocking insulation layer and the sidewall spacers and having a boundary aligned to edges of the blocking insulation layer and the sidewall spacer.