Patent ID: 8367493

Claim:
A method of manufacturing a memory device, the method comprising: forming a plurality of memory cells, said forming including: forming a first dielectric layer over a substrate of the memory device; forming a charge storage element over the first dielectric layer; forming a second dielectric layer over the charge storage element; forming a control gate over the second dielectric layer; depositing a dielectric layer to a thickness ranging from about 50 Å to about 500 Å over the control gate of each of the plurality of memory cells and the substrate, depositing the dielectric layer including: using an atomic layer deposition process to deposit the dielectric layer to the thickness ranging from about 50 Å to about 500 Å, the dielectric layer, deposited using the atomic layer deposition process, filling spaces between adjacent memory cells of the plurality of memory cells, and the dielectric layer, deposited using the atomic layer deposition process, having a substantially uniform thickness that prevents re-entrant angles, the dielectric layer comprising a silicon nitride; and depositing an interlayer dielectric over the dielectric layer, the interlayer dielectric comprising boro-phosphosilicate glass and being deposited to a thickness ranging from about 2,000 Å to about 11,000 Å, the interlayer dielectric being deposited to fill, based on the substantially uniform thickness that prevents the re-entrant angles, the spaces between the adjacent memory cells, voids, in the interlayer dielectric, being eliminated based on the interlayer dielectric being deposited to fill the spaces between the adjacent memory cells.