Patent ID: 8557666

Claim:
A method for fabricating an integrated circuit comprising: etching trenches into a silicon substrate and filling the trenches with an insulating material to separate spaced apart silicon fins having top surfaces and sidewalls; forming dummy gate structures overlying and transverse to the fins, the dummy gate structures overlying first regions of the fins; filling between the dummy gate structures with a back fill material, the back fill material overlying second regions of the fins; removing the dummy gate structures to expose the top surfaces of the first regions of the fins; etching the insulating material to expose the sidewalls of the first regions of the fins; depositing a high-k dielectric material and a work function determining gate electrode material overlying the top surfaces and sidewalls of the first regions of the fins; removing the back fill material to expose the top surfaces of the fins in the second regions; forming metal silicide contacts on the top surfaces of the second regions of the fins; forming conductive contacts to the work function determining material and to the metal silicide contacts; etching the top surfaces of the first regions of the fins exposed by removing the dummy gate structures to form recesses; and epitaxially growing a layer of undoped silicon to fill the recesses.