Patent ID: 8680577

Claim:
A semiconductor device, comprising: a semiconductor substrate region; a channel region positioned above the semiconductor substrate region; a source region having a first portion positioned adjacent a first side of the channel region and a second portion above the first portion and above the channel region; a drain region having a first portion positioned adjacent a second side of the channel region and a second portion above the first portion and above the channel region; a source sidewall spacer positioned laterally adjacent the second portion of the source region; a drain sidewall spacer positioned laterally adjacent the second portion of the drain region; a gate dielectric overlying the channel region and having a first end positioned adjacent the source sidewall spacer and a second end positioned adjacent the drain sidewall spacer; a gate electrode positioned overlying the channel region and positioned laterally adjacent to the second portion of the source region and laterally adjacent to the second portion of the drain region, the gate electrode having n upper surface that is approximately coplanar with upper surfaces of the source and drain regions.