Patent ID: 8133801

Claim:
A method of manufacturing a memory device, the method comprising: forming a first dielectric layer over a substrate; forming a charge storage element over the first dielectric layer in one layer; forming an inter-gate dielectric over and directly contacting the first dielectric layer and the charge storage element, where the inter-gate dielectric includes a plurality of layers; depositing a polysilicon layer directly over the inter-gate dielectric, where depositing the polysilicon control gate layer includes: providing a SiH 2 Cl 2 reactant to a deposition chamber at a first flow rate, and providing a SiH 4 reactant to the deposition chamber at a second flow rate, where the SiH 2 Cl 2 and SiH 4 reactants are concurrently provided to the deposition chamber, planarizing the polysilicon layer to form a control gate; forming an interlayer dielectric on the control gate; and forming a contact hole in the interlayer dielectric.