Patent ID: 7060573

Claim:
A method to form shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a silicon semiconductor substrate; depositing a silicon nitride layer overlying said silicon semiconductor substrate; depositing a polysilicon layer overlying said silicon nitride layer; depositing an oxidation mask overlying said polysilicon layer; patterning said oxidation mask, said polysilicon layer, said silicon nitride layer, and said silicon semiconductor substrate to form trenches for planned shallow trench isolations; oxidizing said silicon semiconductor substrate exposed within said trenches to form an oxide liner layer within said trenches wherein said oxidation mask prevents oxidation of said polysilicon layer; removing said oxidation mask; depositing a trench oxide layer overlying said oxide liner layer and filling said trenches; and polishing down said trench oxide layer and said polysilicon layer stopping at said silicon nitride layer to complete said shallow trench isolations in the manufacture of said integrated circuit device.