Patent ID: 6944840

Claim:
A method of designing a semiconductor integrated circuit, comprising the steps of: dividing a chip of a semiconductor integrated circuit into a number of areas and providing a plurality of clock pins for each of the areas; performing distribution of a clock signal from a clock source pin to each of the areas in a transmission form that is of high-speed and resistant to noise; and performing adjustment of a clock timing for each flip-flop in the semiconductor integrated circuit such that flip-flop-to-flip-flop data transmission can be performed in a target machine cycle, wherein a plurality of kinds of methods having different adjustable ranges are used as methods of adjusting timing of the clock signal input to said flip-flop, the flip-flops are grouped for each clock timing required by each flip-flop in said area, and each group of said flip-flops grouped for each clock timing is connected to a separate clock pin and adjusted in each clock timing required by each flip-flop.