Patent ID: 7943863

Claim:
A wiring substrate comprising: a first insulation layer; a connection terminal disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer and to be electrically connected with a semiconductor chip; a second insulation layer disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface; a via disposed in the second insulation layer and separated from the connection terminal; and a wiring pattern that is directly connected to the connection terminal and is disposed on the second main surface of the first insulation layer and electrically connecting the connection terminal and the via, wherein a plurality of the connection terminals are disposed in an opening formed in the first insulation layer, a surface of the connection terminal is exposed from the first main surface of the first insulation layer so that the surface of the connection terminal is made generally flush with the first main surface of the first insulation layer, the connection terminal and the wiring pattern are integrally formed such that the wiring pattern extends from the connection terminal, and the opening has a size sufficient to allow a space between adjacent connection terminals in the opening so that the second insulation layer is exposed through the first main surface of the first insulation layer in the space of the opening.