Patent ID: 6903460

Claim:
Semiconductor equipment comprising: a semiconductor substrate; a plurality of transistors having a source cell and a drain cell disposed alternately on the substrate so as to form a mesh pattern; and upper and lower layer wirings for electrically connecting the source cells and the drain cells, wherein the lower layer wiring includes a first source wiring having a plurality of stripes for connecting the neighboring source cells and a first drain wiring having a plurality of stripes for connecting the neighboring drain cells, wherein the upper layer wiring includes a second source wiring having a plurality of stripes for connecting to the first source wiring and a second drain wiring having a plurality of stripes for connecting to the first drain wiring, wherein the second source wiring has a width of the stripe, which is wider than that of the first source wiring, and the second drain wiring has a width of the stripe, which is wider than that of the first drain wiring, and wherein the stripes of the second source wiring and the second drain wiring are disposed alternately.