Patent ID: 8787091

Claim:
A nonvolatile semiconductor memory device, comprising a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to perform a pre-program operation before an erasing operation for the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block, the control circuit being configured to execute the erasing operation by applying an erasing voltage to the NAND cell units in the block, and to execute the pre-program operation by applying a certain pre-program voltage to first nonvolatile memory cells in the NAND cell units, and by applying a voltage different from the certain pre-program voltage to second nonvolatile memory cells in the NAND cell units, the second nonvolatile memory cells including at least nonvolatile memory cells at the both ends of the memory string.