Patent ID: 8384471

Claim:
A circuit comprising: a first current mirror comprising: a first PMOS transistor; and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a second current mirror comprising: a first NMOS transistor comprising a drain coupled to the drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor; a first switch coupled between, and configured to equalize, the drain of the first PMOS transistor and the drain of the second PMOS transistor; a second switch coupled between a source of the first NMOS transistor and an electrical ground; a third switch coupled between a source of the second NMOS transistor and the electrical ground, wherein the second and the third switches are configured to operate with phases opposite to phases of the first switch; and a fourth switch coupled between the drain of the first PMOS transistor and the electrical ground.