Patent ID: 7688645

Claim:
An output circuit for a semiconductor memory device comprising: an outputting transistor circuit of a push-pull structure having an outputting PMOS transistor whose source terminal is connected to a first power supply, and an outputting NMOS transistor whose source terminal is connected to a grounded power supply and whose drain terminal is connected in series to a drain terminal of the outputting PMOS transistor; and a gate level setting section that sets a voltage level of a gate terminal of the outputting PMOS transistor, and sets a voltage level of a gate terminal of the outputting NMOS transistor, wherein the gate level setting section is provided with: a standby state gate level setting section that, in a standby state in which both the outputting PMOS transistor and the outputting NMOS transistor are OFF, sets the voltage level of the gate terminal of the outputting PMOS transistor to a voltage level of a second power supply that is higher than a voltage level of the first power supply; and an active state gate level setting section that, in an active state in which either one of the outputting PMOS transistor and the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell and a signal is output from a connection point between the outputting PMOS transistor and the outputting NMOS transistor, causes the voltage level of the gate terminal of the outputting PMOS transistor to change to the voltage level of the first power supply in response to an active command or a read command issued to the semiconductor memory device, or in response to the state of the semiconductor memory device changing to the active state or a read state.