Patent ID: 7239813

Claim:
A bit synchronization circuit for synchronizing, with an internal reference clock, burst data sets received in time series order, the circuit comprising: a multiphase data sampling unit for converting each of the received burst data sets to multiphase data trains having phases different from each other; a phase determination unit for detecting, from among said multiphase data trains, an optimum phase data train having the highest phase margin over the reference clock and generating a control signal indicating the optimum phase data train; an output data selector for selectively passing, of the multiphase data trains outputted from said data sampling portion, the optimum phase data train indicated by said control signal; a data synchronization unit for converting the data train passed through said output data selector to a data train in synchronization with said reference clock and outputting the resulting data train; wherein said phase determination unit repeatedly performs the operation of detecting said optimum phase data train during a period during which the same burst data set is received and, if an optimum phase varies, said output data selector dynamically switches the optimum phase data to be supplied to said data synchronization unit in response to the control signal outputted from said phase determination unit; and means for generating a missing data supplying data train from the most-delayed-phase data train outputted from said multiphase data sampling unit and supplying, to said data synchronization unit, said missing data supplying data train in parallel relation with said optimum phase data train, wherein: said phase determination unit has means for detecting a phase variation under a specified condition which disturbs continuity of the optimum phase data and generating a data train correction signal, and said data synchronization unit is provided with data transfer control means for selecting, in response to said data train correction signal, data to be transferred as the output data train from between said optimum phase data train and said missing data supplying data train.