Patent ID: 8756263

Claim:
A method for operating a logic circuit, comprising: receiving in the logic circuit successive operand input vector pairs, each input vector pair comprising a respective first multi-bit input vector and a respective second multi-bit input vector: for each said input vector pair, receiving in the logic circuit a respective set of four binary control signal inputs (ctl 0 , ctl 1 , ctl 2 , ctl 3 ) corresponding to the input vector pair, each binary control signal input being received on a respective control signal input line of four parallel control signal lines, each said set of four binary control signal inputs specifying a respective one of sixteen possible Boolean operations to be performed in parallel on each bit pair (va, vb) of a respective bit of the first multi-bit input vector and a respective bit of the second multi-bit input vector of the respective input vector pair; applying the respective one of sixteen possible Boolean operations specified by the corresponding set of four binary control signal inputs in parallel to each bit pair (va, vb) of the respective input vector pair using a respective binary logic unit comprising a 4:1 multiplexer having four data inputs and two select inputs, wherein each control signal input of the respective set of four binary control signal inputs (ctl 0 , ctl 1 , ctl 2 , ctl 3 ) is applied to a respective one of the four data inputs of the 4:1 multiplexer and each bit of the respective bit pair (va, vb) is applied to a respective one of the two select inputs of the 4:1 multiplexer, the respective bit pair (va, vb) selecting a single control signal input from the corresponding set of four binary control signal inputs (clt 0 , clt 1 , clt 2 , clt 3 ) as an output signal (vo) of the respective binary logic unit representing the result of the respective one of sixteen possible Boolean operations specified by the corresponding set of four binary control signal inputs applied on the respective bit pair (va, vb) of the respective input vector pair.