Patent ID: 7389456

Claim:
An integrated circuit comprising: A. first TAP circuitry having a test data input, a test data output, a test clock input, and a test mode select input; B. second TAP circuitry having a test data input, a test data output, a test clock input, and a test mode select input; C. input linking circuitry selectively coupling test data input signals and test mode select signals to the first and second TAP circuitry in response to linking control signal inputs; D. output linking circuitry selectively coupling test data output signals from the first and second TAP circuitry in response to linking control signal inputs; and E. TAP linking module circuitry coupled in series with the test data inputs and test data outputs of the first and second TAP circuitry and having linking control signal outputs connected to the linking control signal inputs of the input linking circuitry and the output linking circuitry.