Patent ID: 7352169

Claim:
A method of testing an integrated circuit containing a plurality of input/output (I/O) paths, each of said I/O paths being provided between corresponding a I/O pad and an internal functional logic also contained in said integrated circuit, each of said I/O paths containing a corresponding conductor, a corresponding scan cell and a corresponding component, said method comprising: placing said scan cells in the form of a chain, wherein said scan cells contain a first scan cell having a first component as said corresponding component; scanning-in a scan vector to set each of said scan cells to a corresponding bit value, wherein said first scan cell is set to a first value; launching said first value on to said first component from said first scan cell at a first time instance; capturing in a register an output of said first component at a second time instance, wherein said second time instance is timed to correspond to an at-speed operation of said integrated circuit; comparing said output with an expected value to determine whether said first component is operating accurately at said at-speed operation.