Patent ID: 8300805

Claim:
A hardware architecture for encrypting data using a symmetric-key encryption standard, said architecture comprising: N registers configured to store N blocks of data, each register arranged to hold a block of data; a multiplexer arranged to accept one of said N blocks of data at a time and to output said block; a pipeline processing unit arranged to perform a round of processing upon said block using said symmetric-key encryption standard, said pipeline processing unit receiving a round key for each round of processing upon said block; a key round generator that generates round keys for said pipeline processing unit using a cipher key; N key memory devices, each key memory device arranged to hold said round keys; N read counters each corresponding to one of said N key memory devices, each read counter indexing one of said round keys in a corresponding one of said N key memory devices to enable said indexed round key to be input to said pipeline processing unit; and a start modulo N counter configured to repeat a cycle of counting N times lots at each key round, wherein N is an integer greater than one.