Patent ID: 8463987

Claim:
A memory scheduler comprising: first logic to: monitor a first timing parameter of one or more memory bank timing parameters corresponding to a memory bank that includes a portion of a memory device; and result in a memory request to become a candidate for scheduling to the portion of the memory device in response to satisfaction of the first timing parameter; and second logic to: monitor a second timing parameter of one or more memory rank timing parameters corresponding to a rank of the portion in the memory device, wherein each memory rank of the memory device is to correspond to a set of a plurality of memory cells that are capable of being accessed at a full data bit bandwidth of the memory device; and result in scheduling of the memory request from the first logic to the portion of the memory device in response to satisfaction of the second timing parameter, wherein the memory request is to be preempted by a different memory request based on a determination of whether the memory request is a read request that is a page hit and the different memory request is a read request that is a page miss.