Patent ID: 7739563

Claim:
A semiconductor integrated circuit comprising: a memory operating on a first clock, a test pattern generation section, operating on a second clock having half the frequency of said first clock, for generating first test data, an LSB 0 processing section for generating second test data by adding numeric value 0 to said first test data generated by said test pattern generation section as the least significant bit thereof, an LSB 1 processing section for generating third test data by adding numeric value 1 to said first test data generated by said test pattern generation section as the least significant bit thereof, a test data selection section for selectively outputting either said second or third test data being output from said LSB 0 processing section or said LSB 1 processing section, respectively, depending on the signal value of said second clock, thereby inputting the selected test data to said memory as fourth test data, and a delay circuit for generating a delay clock obtained by delaying said second clock and for supplying said delay clock to said test data selection section.