Patent ID: 8886008

Claim:
An integrated circuit comprising: a processor; a memory; a first set of terminals including first control signal terminals for receiving a first horizontal synchronizing signal, a first vertical synchronizing signal and a first data output clock signal, and first data terminals for receiving first frame data from a first sensing device; a second set of terminals including second control signal terminals for receiving a second horizontal synchronizing signal, a second vertical synchronizing signal and a second data output clock signal, and second data terminals for receiving second frame data from a second sensing device; a first interface circuit coupled to the first set of terminals and configured for receiving the first frame data and outputting a first part of the first frame data to the memory in accordance with a first instruction configured by the processor; a second interface circuit; and a selector coupled to the first set of terminals and the second set of terminals, for selectively coupling the second interface circuit to one of the first set of terminals and the second set of terminals according to a control signal, wherein the second interface circuit is configured for receiving the second frame data and for outputting a first part of the second frame data to the memory in accordance with a second instruction configured by the processor when the second set of terminals is coupled to the second interface circuit by the selector, and wherein the second interface circuit is configured for receiving the first frame data and for outputting a second part of the first frame data to the memory in accordance with a third instruction configured by the processor when the first set of terminals is coupled to the second interface circuit by the selector; wherein each of the first interface circuit and the second interface circuit comprises: an event detecting circuit which receives a horizontal synchronizing signal, a vertical synchronizing signal and a data output clock signal, detects an event in the received frame data output period according to the horizontal synchronizing signal, the vertical synchronizing signal and the data output clock signal; a plurality of counting circuit each of which counts an event detected by the event detecting circuit and operable to enable loading of data corresponding to the part of the received frame data; a control circuit which receives the part of the received frame data, and outputs the part of the frame data to the memory when one of the plurality of counting circuits outputs an enable signal or stops to output the data when all of the plurality of counting circuits do not output the enable signal; and an address generating circuit which generates an address to which the part of the received frame data outputted by the control circuit is stored and outputs the generated address to the memory.