Patent ID: 7433442

Claim:
A linear, half-rate clock and data recovery (CDR) circuit comprising: a phase detector operable to receive a data signal and generate a phase error signal representative of the phase difference between the data signal and a clock signal, the phase detector comprising: a plurality of pairs of latches operable to receive the clock signal, wherein each pair of the plurality of pairs of latches comprises a first latch, and a second latch configured in parallel with the first latch, wherein the first latch is operable to be clocked by one edge of the clock signal and the second latch is operable to be clocked by an opposite edge of the clock signal, a plurality of logic gates, wherein each of the plurality of logic gates is configured to receive an output from the first latch of a respective pair of the plurality of pairs of latches, and an output from the second latch of the respective pair of the plurality of pairs of latches, and a summing circuit operable to receive an output signal from each of the plurality of logic gates and generate the phase error signal in response to the output signals from the logic gates; a loop filter operable to receive the phase error signal and generate a voltage control signal in response to the phase error signal; and a voltage-controlled oscillator (VCO) operable to receive the voltage control signal and generate the clock signal in response to the voltage control signal, wherein the VCO is driven by the voltage control signal to align both the first and second edges of the clock signal with a baud center of the data signal.