Patent ID: 7883941

Claim:
A method for fabricating a memory cell comprising a first transistor, a second transistor, a third transistor and a thyristor, the method comprising the steps of: providing a semiconductor layer comprising first, second, third and fourth well regions of a first conductivity type in the semiconductor layer, and a first gate structure of the first transistor overlying the first well region, a second gate structure of the thyristor overlying the second well region, a third gate structure of the second transistor overlying the third well region and integral with the second gate structure, and a fourth gate structure of the third transistor overlying the fourth well region; forming sidewall spacers adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures, and an insulating spacer block overlying a portion of the first well region and a portion of the first gate structure, the insulating spacer block adjacent a second sidewall of the first gate structure; forming a first source region adjacent the first gate structure, a common drain/cathode region between the first and second gate structures, a second source region adjacent the third gate structure, a common drain/source region between the third and fourth gate structures, and a drain region adjacent the fourth gate structure; and forming a first base region that extends into the first well region under the insulating spacer block adjacent the first gate structure, and an anode region in the first well region that extends into the first well region adjacent the first base region.