Patent ID: 7809926

Claim:
A reconfigurable multiprocessor system comprising: a plurality of processor units, wherein the plurality of processor units are independent cores and dynamically fused into a single processor, wherein the single processor is dynamically split into distinct processing units at run time; and at least one cross unit connection component operatively connecting at least two processor units from said plurality of processor units, said at least one cross unit connection component reconfigurably linking one processor unit to another processor unit, thereby fusing them as a single processor, said reconfigurable linking adjusting processing to sequential when in a fused mode and to parallel when in a split mode; said at least one cross unit connection component enabling collective fetching and providing instructions to be executed collectively by said at least two processor units and collectively committing executed instructions by said at least two processor units; said collective fetching comprising cooperatively fetching an instruction block; said instruction block comprising a number of subsets, said fetching being performed cooperatively by fetching a one subset of said instruction block by each of said at least two processor units, when the processor units are in the fused mode; said instruction block comprising each subsets of instructions fetched by each of said at least two processor units; said instruction block being constructed from each subset of instructions fetched by each of said at least two processor units; said collective fetching enabling operation of said at least two processor units substantially as a single processor unit; whereby executing sequential code collectively at processor units is enabled; and when changing manner of processing from fused to split or from split to fused, bringing an internal state of said plurality of processing units to a form consistent with a new configuration, resulting from the reconfiguring of cross connection unit, and reconfiguring instruction cache memories in each processing unit and updating instruction characteristic upon change of manner of processing.