Patent ID: 7124331

Claim:
A method for providing fault-tolerance for temporary results within a central processing unit (CPU), comprising: receiving a temporary result for an in-flight instruction at an annex within the CPU; generating a parity bit for the temporary result within the annex; storing the temporary result and the parity bit in a temporary register within the annex, wherein the annex stores temporary results before they are committed to the architectural state of the processor; before the temporary result is committed to the architectural state of the CPU, checking the temporary result and the parity bit within the annex to detect a bit error; if a bit error is detected, performing a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result; if a bit error is not detected, committing the temporary result to the architectural state of the CPU; and allowing younger instructions to read temporary results from the annex instead of having to wait for the temporary results to be committed to the register file; wherein reading a specific temporary result from the annex involves performing a content addressable memory (CAM) search for a specific destination register index that is associated with the specific temporary result.