Patent ID: 7727833

Claim:
A method of fabricating a voltage reference on an integrated circuit die, said method comprising the steps of: providing an N-type well/region in a silicon semiconductor integrated circuit die; covering at least a portion of the N-type well/region with an oxide layer in an area used to form gates of P-channel metal oxide semiconductor (P-MOS) transistors for an operational amplifier; covering the oxide layer with a polysilicon layer; implanting a P − dopant into the polysilicon layer; covering a portion of the P − doped polysilicon layer with a first resist mask; implanting an N + dopant into the P − doped polysilicon layer wherever the first resist mask does not cover the P − doped polysilicon layer; removing the first resist mask; covering a portion of the N + doped polysilicon layer and a portion of the P − doped polysilicon layer with a second resist mask; and removing the N + doped polysilicon layer to form an N-type polysilicon gate where not covered by the second resist mask, the P − doped polysilicon layer to form a P-type polysilicon gate where not covered by the second resist mask, and the oxide layer where not covered by the second resist mask.