Patent ID: 8395954

Claim:
An integrated circuit comprising: a plurality of memory cells coupled to a pair of bit lines, wherein the plurality of memory cells are powered by a first power supply voltage during use; a circuit coupled to the pair of bit lines and powered by the first power supply voltage during use, wherein the circuit is coupled to receive a first control signal, and wherein the circuit is configured to maintain a precharge voltage on one bit line of the pair of bit lines responsive to the other one of the pair of bit lines being discharged during use and further responsive to a first logic level on the first control signal, and wherein the circuit is disabled responsive to a second logic level on the first control signal; and a power control unit configured to generate the first control signal, wherein the power control unit is configured to assert the second logic level on the first control signal responsive to the determining that a second power supply voltage to other circuitry in the integrated circuit is being powered down.