Patent ID: 7308607

Claim:
A method comprising: executing a leading instruction thread and a corresponding trailing instruction thread; synchronizing execution of the leading instruction thread and the trailing instruction thread in response to occurrence of a set of one or more predetermined conditions; storing, in an external memory, values stored in one or more registers providing architectural state for a processor executing the leading instruction thread and/or the trailing instruction thread by maintaining an indication of registers storing values that have been checked for faults and/or registers storing values that have not been checked for faults and causing contents of the registers storing values that have not been checked for faults to be checked for faults and stored in external memory, wherein maintaining an indication of registers storing values that have been checked for faults and/or registers storing values that have not been checked for faults includes maintaining a bit vector having a bit corresponding to a set of registers, setting a bit in the bit vector to a first value if a value in a selected register has been checked for faults, and setting a bit in the bit vector to a second value if the value in the selected register has not been checked for faults; and checking the values stored in the one or more registers with a checking mechanism used for checking results of store operations during execution of the leading instruction thread and/or the trailing instruction thread.