Patent ID: 7836323

Claim:
A clock regeneration circuit comprising: a first buffer which buffers regeneration reference synchronous information extracted from a transmission signal; a counter which counts a reception side reference clock generated based on a clock control signal; a second buffer including a register which buffers a counted value of the counter and which has a predetermined bit width; and a clock control circuit which obtains a difference between a transmission side reference clock and the reception side reference clock based on values held in the first buffer and the second buffer to generate the clock control signal, wherein when new regeneration reference synchronous information extracted from the transmission signal is input before the values held in the first buffer and the second buffer are read by the clock control circuit, the first buffer and the second buffer are not updated, when the new regeneration reference synchronous information extracted from the transmission signal is input after the values held in the first buffer and the second buffer have been read by the clock control circuit, the first buffer and the second buffer are updated, and the reception side reference clock corresponding to the transmission side reference clock using in generation processing of the transmission signal is generated in digital communication.