Patent ID: 7525341

Claim:
A multiplexer circuit comprising: a data node; first transistor circuitry coupled to a selector input, a first data input, and said data node, said first transistor circuitry comprising at least two transistors and being operative to pass a logical value derived from said first data input to said data node in response to a logical value derived from said selector input; second transistor circuitry coupled to said selector input, a second data input, and said data node, said second transistor circuitry comprising at least two transistors and being operative to pass a logical value derived from said second data input to said data node in response to another logical value derived from said selector input; and third transistor circuitry coupled to said selector input, said data node, and a data output, said third transistor circuitry being operative to hold said data output substantially constant until said transistors in said first and second transistor circuitries have switched in response to a transition of said selector input.