Patent ID: 8703573

Claim:
A method of manufacturing a semiconductor device, the method comprising: sequentially forming a first mold layer pattern, a second mold layer pattern, and a third mold layer pattern on a substrate, wherein the first to third mold layer patterns are spaced apart from each other; forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern; forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns; depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench; and forming a first lower electrode and a second lower electrode separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.