Patent ID: 8779495

Claim:
An integrated circuit comprising: a silicon substrate having a planar surface; an oxide layer directly contacting the planar surface of the substrate and having a sidewall perpendicular to the substrate; a first SONOS memory cell isolated from the substrate by the oxide layer; a second SONOS memory cell, the second memory cell stacked directly on another oxide layer directly on the first memory cell such that the first memory cell is between the substrate and the second memory cell; a hard mask material layer over the second SONOS memory cell such that the second SONOS memory cell is between the hard mask material layer and the first SONOS memory cell, the hard mask material layer having a sidewall perpendicular to the substrate; and a word line forming a gate of the first SONOS memory cell and a gate of the second SONOS memory cell, the word line directly contacting the planar surface of the substrate and the hard mask material layer, wherein each of the first memory cell and the second memory cell is individually accessible for read and write operations, and wherein the first SONOS memory cell comprises a tunnel dielectric material layer that directly contacts the sidewall of the hard mask material layer, the sidewall of the oxide layer, and the planar surface of the substrate.