Patent ID: 7759775

Claim:
A high current semiconductor power SOIC package comprising: a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die soldered thereto; a pair of lead bonding areas being disposed in a same plane of a top surface of the die; large diameter bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum; and a resin body encapsulating the die, the bonding wires, and at least a portion of the lead frame, wherein the die comprises an integrated circuit, the integrated circuit comprises an FET device, and the plurality of leads comprise a source lead, a gate lead, and a drain lead coupled respectively to the FET device's source region, gate region, and drain region, the source lead including a source lead laterally extending portion external to the resin body, and first and second portions external to the resin body and extending perpendicularly from the source lead laterally extending portion in spaced relationship one to the other.