Patent ID: 7418566

Claim:
A memory arrangement comprising: a programmable memory; a first buffer memory associated with the programmable memory, to which first buffer memory, responsive to a request for a program command which is accessed in the programmable memory, a plurality of commands following the accessed command in the programmable memory are written, wherein a first information line associated with the first buffer memory is used for command transfer, and wherein the accessed command and the plurality of commands following the accessed command are simultaneously stored in sequential memory locations of the first buffer memory; and a second buffer memory to which, responsive to a request for a datum which is accessed in the programmable memory, a plurality of data following the accessed datum in the programmable memory are written, wherein a second information line associated with the second buffer memory is used for data transfer, and wherein the accessed datum and the plurality of data following the accessed datum are simultaneously stored in sequential memory locations of the second buffer memory; wherein at least one of the first buffer memory and the second buffer memory is one of integrated in the programmable memory and connected to the programmable memory; wherein the respective ones of the plurality of commands following the accessed command are associated with respective ones of the plurality of data following the accessed datum by corresponding respective sequential positions of the respective ones of the plurality of commands within the first buffer memory and the respective ones of the plurality of data within the second buffer memory; and wherein each of the respective ones of the plurality of data is processed in accordance with the respective datum's associated command.