Patent ID: 6989843

Claim:
An adder tree for adding numbers comprising: one or more addition levels including a top addition level and a bottom addition level, wherein a summation of said numbers begins at said top level and propagates through said one or more addition levels, wherein each of said addition levels comprises one or more adder cells; wherein each of said adder cells is configured to receive a first input operand, a second input operand, a first winner-take-all (WTA) bit and a second WTA bit, and to generate a first output operand, wherein the first output operand equals the first input operand if the first WTA bit is high, wherein the first output operand equals the second input operand if the second WTA bit is high; wherein each adder cell is further configured to generate a WTA output bit which comprises the logical OR of the first WTA bit and the second WTA bit; and wherein each of said one or more adders at the top addition level receives two of said numbers as the corresponding first input operand and the second input operand.