Patent ID: 7342427

Claim:
An apparatus for enabling different power consumption states for an electronic device, comprising: a phase frequency detector that is arranged to receive a reference clock signal and a feedback clock signal, and is further arranged to output at least one error signal if a phase of the feedback clock signal lags or leads another phase of the reference clock signal; and a lost_lock detection circuit that is arranged to output a lost_lock signal based on receiving the at least one error signal, wherein the lost_lock signal is provided to the electronic device to enable a transition to a reduced power consumption state, wherein the at least one error signal includes a down logic signal and an up logic signal, and wherein the lost_lock detection circuit comprises: an OR logic device and an XOR logic device, wherein the down logic signal and the up logic signal are provided as inputs to both the OR and XOR logic devices, wherein the up and down logic signals are based on a lagging or leading indicated by the at least one error signal for the phases of the reference clock signal and feedback clock signal; a PMOS transistor coupled to the output of the OR logic device; and an NMOS transistor coupled to the output of the XOR logic device, wherein the arrangement of the PMOS and NMOS transistors are configured to share a common drain connection.