Patent ID: 7966542

Claim:
A device for use with a memory for storing a plurality of Z element vectors, each Z element vector including Z elements, each element including at least one bit to be processed, the device being for performing a low-density parity-check (LDPC) processing operation, the device comprising: a parallel LDPC processing module including Z processing element arranged to operate in parallel; and a controllable factorable permuter for coupling said memory to said parallel LDPC processing module, said controllable factorable permuter including switching circuitry, said switching circuitry being responsive to a control signal to perform a factorable permutation operation on a Z element vector being passed through said factorable permuter, said factorable permutation operation including first and second permutation operations which cause first and second re-orderings of vector elements to occur, said first and second reordering operations being performed on n equally sized vector portions of size Z/n, said first permutation operation causing a change in the order of at least two equally sized vector portions, said second permutation operation being performed on each of the Z/n sized portions to cause a change in the ordering of elements within each of said Z/n sized portions, where n is an integer greater than 1 and less than Z.