Patent ID: 8379435

Claim:
A process of writing a data bit value to an addressed SRAM cell and a half-addressed SRAM cell within an SRAM cell array of an integrated circuit, comprising: applying a positive voltage increment to an n-well of said addressed SRAM cell; applying a negative voltage increment to an n-well of said half-addressed SRAM cell; connecting a bit data line in said addressed SRAM cell to a bit-side write potential appropriate for said data bit value; and turning on a bit-side passgate transistor in said addressed SRAM cell wherein said writing said data bit value further includes the steps of forward biasing a p-well in said addressed SRAM cell and reverse biasing a p-well in said half-addressed SRAM cell; and further wherein said step of reading said data bit value further includes the steps of adjusting a bias of said p-well in said addressed SRAM cell so as to provide a desired balance between a read current and data stability in said addressed SRAM cell and reverse biasing said p-well in said half-addressed SRAM cell.