Patent ID: 8473795

Claim:
An integrated circuit test architecture comprising: A. cores of functional circuitry; B. test wrapper architectures, each test wrapper architecture being connected with one core; C. test access mechanisms, each test access mechanism being connected with one of the test wrapper architectures; D. a test access mechanism controller having a test access mechanism interface bus connected with each of the test wrapper architectures and the test access mechanisms, the test access mechanism controller having a scan data input and a scan data output, and the test access mechanism controller having an enable output lead coupled to each test wrapper architecture and test access mechanism; and E. double data rate circuitry, the double data rate circuitry having a double data rate parallel data bus input, a double data rate clock input, a clock output connected to the controller, a load instruction register output connected to the controller, three mode outputs connected to the controller, and parallel data bus outputs connected to the controller and to the test access mechanisms.