Patent ID: 6919745

Claim:
A ring-register controlled delay locked loop comprising: a phase detecting means for comparing an internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the internal clock signal with the output clock signal; a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the internal clock signal from the fine delay means in response to the bypassed control signal; an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.