Patent ID: 8187920

Claim:
A method for packaging integrated circuits, the method comprising: sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, wherein the epoxy layers are deposited by spin coating; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited; forming an opening in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited; placing a first integrated circuit within an associated one of the openings, wherein the first integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the first integrated circuit to thereby cover the first integrated circuit; forming at least one interconnect layer on one of the epoxy layers, the at least one interconnect layer including at least one conductive via; forming a first antenna on at least one of the epoxy layers, wherein the first antenna is electrically coupled with the active face of the first integrated circuit through at least one of the interconnect layers; and forming a plurality of microsystems on the substrate, each microsystem being formed substantially concurrently by said sequential depositing of layers of epoxy over the substrate, said photolithographic patterning, said forming of an opening in the at least one of the epoxy layers, said placing of the first integrated circuit, said forming of the at least one interconnect layer, and said forming of the first antenna are performed such that each microsystem includes at least one antenna, at least one integrated circuit and at least one interconnect layer.