Patent ID: 7539910

Claim:
A memory module test system, comprising: at least one memory module, including a first hub and a plurality of semiconductor memory devices; a tester which tests the at least one memory module; and a second hub, which is located between the first hub and the tester, wherein the second hub: converts a first memory command and first memory data output from the tester into first packet data; transfers the first packet data to the first hub; converts second packet data output from the first hub to the second hub into second memory data; and transfers the second memory data to the tester; wherein the first hub includes: a data divider which receives the first packet data and divides the first packet data into a first output and a second output; a first decoder, which: receives the first output of the data divider; converts the first output into a second memory command; and transmits the second memory command to at least one of the plurality of semiconductor memory devices; a second decoder, which: receives the second output of the data divider; converts the second output into second memory data; and transmits the second memory data to the plurality of semiconductor memory device; an encoder, which receives third memory data from the plurality of semiconductor memory device and converts the third memory data into the second packet data; a first connection line which transmits first packet data to an adjacent memory module; and a second connection line which receives and outputs the first packet data from the adjacent memory module.