Patent ID: 6891494

Claim:
A layout method of a comparator array of a flash type analog to digital converting circuit, the flash type analog to digital converting circuit including: (i) a reference voltage for generating (2 n −1 ) voltages and being arranged to be folded; (ii) a comparator array including (2 n −1) comparators for comparing voltage differences between the respective (2 n −b 1 ) voltages and an analog input signal to generate a digital thermometer code having (2 n −1) bits; and (iii) an encoder for encoding the digital thermometer code having (2 n −1) bits to generate an n-bit of digital signal, the layout method comprising: arranging the comparators such that the comparators of (2 n −1) th comparator to (2 n /2) th comparator are arranged in order and the comparators of (2 n /2−1) th comparator to a first comparator are arranged in a reverse fashion between the comparators of the (2 n −1) th comparator to the (2 n /2) th comparator; and arranging the comparators such that the neighboring comparators adjacent to the respective (2 n −1) comparators remains at the same state when the (2 n −1) th comparator to the (2 n /2) th comparator transit to different states respectively.