Patent ID: 7285999

Claim:
A tracking data cell ( 10 ) comprising: a pair of track and hold circuits ( 1 , 1 ′) coupled to a first multiplexer ( 5 ), wherein each of the track and hold circuits ( 1 , 1 ′) comprises: a linear amplifier ( 2 ) to receive differential analog signal (D+, D−) under control by a first binary clock signal (H+) having a first phase, the linear amplifier ( 2 ) to provide a feed-forward input signal substantial equal with the differential analog signal (D+, D−) to a pseudo latch circuit ( 3 ) in the first of the first binary clock signal (H+), the pseudo latch circuit ( 3 ) under control by a second binary clock signal (H−), the pseudo latch circuit ( 3 ) to memorize the input signal and to provide a differential output signal (LD+, LD−) substantially equal with the feed-forward input signal in a second phase of the first binary clock signal (H−), the second binary clock signal substantially in anti-phase with the first binary clock signal (H+), a clock signal (H+, H−) being inputted substantially in anti-phase in the respective track and hold circuits ( 1 , 1 ′) for determining a receipt of a data signal (D+, D−) having a rate, said track and hold circuits ( 1 , 1 ′) providing an output signal (O) having a substantially half rate relative to the rate of the data signal (D+, D−).