Patent ID: 8492802

Claim:
A semiconductor chip comprising: a first n-type transistor having a first channel and a first gate stack in contact with a surface of the first channel, the first channel comprising a first nanowire having a length l 1 along a first orientation of a crystal structure of the semiconductor chip and a thickness t C1 , wherein the thickness t C1 is less than or equal to about 20 nanometers; and a second p-type transistor having a second channel and a second gate stack in contact with a surface of the second channel, the second channel comprising a second nanowire having a length l 2 along a second orientation of a crystal structure of the semiconductor chip and a thickness t C2 , wherein the thickness t C2 is less than or equal to about 20 nanometers; wherein: the first gate stack exerts a tensile force on the contacted surface of the first channel such that electrical mobility of carriers along the first channel length l 1 is increased due to the tensile force in dependence on the first orientation; and the second gate stack exerts a compressive force on the contacted surface of the second channel such that electrical mobility of carriers along the second channel length l 2 is increased due to the compressive force in dependence on the second orientation wherein the first orientation is substantially along a <100> Miller index and the second orientation is substantially along a <110> Miller index.