Patent ID: 7687387

Claim:
A method of manufacturing a semiconductor device having an L/S (line and space) section, the method comprising: depositing a first mask layer above a substrate; depositing a second mask layer on the first mask layer; depositing a third mask layer on the second mask layer; forming a resist on the third mask layer; processing the third mask layer using the resist as a mask; processing the second mask layer using the third mask layer as a mask; slimming the second mask layer in the L/S section and out of the L/S section; peeling the third mask layer in the L/S section and out of the L/S section; forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section; covering, with a resist, the second mask layer out of the L/S section; etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section is covered with the resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains; and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.