Patent ID: 7110295

Claim:
A semiconductor data processing device comprising: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks, wherein each said erase block is further divided into a plurality of erase sectors, the said nonvolatile memory cells in the erase block instructed to be erased together; and a control circuit, wherein said control circuit controls both of two erasing voltages applied to the nonvolatile memory cells in the erase block instructed to be erased together to select one of the erase sectors from the erase block for performing erase for each erase sector one erase sector at a time, thereby performing said erase for each erase sector in the erase block instructed to be erased in time division, and wherein each said nonvolatile memory cell has a source, a drain, a channel, a control gate arranged over the channel on said drain side, and a charge storage region and a memory gate stacked over the channel on said source side such that the memory gate and the charge storage region are electrically insulated from each other, and wherein a dielectric breakdown seen from said control gate is lower than that seen from said memory gate.