Patent ID: 8030962

Claim:
A memory element comprising: an address transistor having a gate coupled to an address line, having a first source-drain coupled to a data line, and having a second source-drain coupled to a data node; a capacitor coupled between a capacitor ground terminal and the second source-drain, wherein charge stored on the capacitor represents data on the data node; first and second cross-coupled inverters, wherein the first inverter has an output coupled to the data node and has an input, wherein the second inverter has an input coupled to the data node and has an output, and wherein one of the first and second cross-coupled inverters comprises an n-channel metal-oxide semiconductor transistor having a p+ tap operable to remove injected carriers to avoid creating a latch-up condition; and an output line that is coupled to the data node, wherein the first inverter comprises a p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor that has the p+ tap coupled in series between a first positive power supply terminal and a first ground terminal, wherein the second inverter comprises a p-channel metal-oxide-semiconductor transistor and an n-channel metal-oxide-semiconductor transistor coupled in series between a second positive power supply terminal and a second ground terminal, and wherein the memory element further comprises a conductive line that couples the input of the first inverter to the output of the second inverter.