Patent ID: 7900163

Claim:
A method of configuring an integrated circuit design to support sequential flow partial scan testing, comprising: providing a plurality of memory elements in the integrated circuit design that are scannable memory elements by a computer, wherein the integrated circuit design has a specified scan coverage selecting one or more processing paths within the integrated circuit design that exceed a feature threshold for one or more characteristics based on a first selection criteria; identifying at least one of the scannable memory elements in the selected one or more processing paths criteria as being a redundant scan element that does not alter the scan coverage in excess of a fault coverage reduction threshold, wherein the selected one or more processing paths include one or more scan chains, wherein one of the scannable memory elements is identified as the redundant scan element when another scannable memory element can independently drive via combinational logic a binary value captured in the redundant scan element; converting the identified redundant scan element to memory element that is not scannable in a revised integrated circuit design; and optimizing a parameter of the revised integrated circuit design.