Patent ID: 6930527

Claim:
A triple redundant latch for reducing soft errors comprising: a) an input driver, the input driver having an input and an output; b) a first transfer gate, the first transfer gate having an input, a first control input, a second control input and an output; c) a second transfer gate, the second transfer gate having an input, a first control input, a second control input, and an output; d) a third transfer gate, the transfer third gate having an input, a first control input, a second control input, and an output; e) a first feedback inverter, the first feedback inverter having an input and an output; f) a second feedback inverter, the second feedback inverter having an input and an output; g) a third feedback inverter, the third feedback inverter having an input and an output; h) a forward inverter/majority voter, the forward inverter/majority voter having a first input, a second input, a third input and an output; i) an output driver, the output driver having an input and an output; j) wherein the input of the input driver is the input of the triple redundant latch; k) wherein the output of the input driver is connected to the input of the first transfer gate, the input of the second transfer gate, and the input of the third transfer gate; l) wherein a first control input of the triple redundant latch is connected to the first control input of the first transfer gate, the first control input of the second transfer gate, and the first control input of the third transfer gate; m) wherein a second control input of the triple redundant latch is connected to the second control input of the first transfer gate, the second control input of the second transfer gate, and the second control input of the third transfer gate; n) wherein the output of the first transfer gate is connected to the output of the first feedback inverter and to the first input of the forward inverter/majority voter; o) wherein the output of the second transfer gate is connected to the output of the second feedback inverter and to the second input of the forward inverter/majority voter; p) wherein the output of the third transfer gate is connected to the output of the third feedback inverter and to the third input of the forward inverter/majority voter; q) wherein the output of the forward inverter/majority voter is connected to the input of the first feedback inverter, the input of the second feedback inverter, the input of the third feedback inverter, and to the input of the output driver; r) wherein the output of the output driver is the output of the triple redundant latch.