Patent ID: 7729896

Claim:
A method of simulating a plurality of execution blocks in a large scale integration model in parallel, the method comprising: simulating a first and a second execution block in parallel; detecting, when a first instruction is executed by the first block that is selected from among the execution blocks, a number of cycles at a time of completion of the first instruction; judging whether a second instruction currently being executed by the second block that is selected subsequent to the first block is an instruction to access a memory model; determining, based on a result of judgment at the judging, whether a first address at which the first block has accessed the memory model coincides with a second address of the memory model, the second address included in the second instruction for the second block to access; comparing, when the first address coincides with the second address at the determining, a current number of cycles of the second block and the number of cycles detected at the detecting; and storing, based on a result of comparison at the comparing, the second address and data that has been stored at the second address, in a storage area different from the memory model.