Patent ID: 6858895

Claim:
A circuit configuration having a field-effect transistor, comprising: a semiconductor body having a trench formed therein; external gate terminals, including a first gate terminal and a second gate terminal; at least one source electrode region formed in said semiconductor body; at least one drain electrode region formed in said semiconductor body; at least two gate electrodes, including a first gate electrode and a second gate electrode, formed vertically in said trench and in & manner insulated from one another and from said source electrode region and said drain electrode region, said first and second gate electrodes being capacitively coupled to one another by a capacitance distributed over the field-effect transistor, said gate electrodes each connected separately to one of said external gate terminals; and a driver configuration connected to said external gate terminals and having driver circuits, including a first driver circuit and a second driver circuit, and a generating device, said driver configuration generating a first gate drive signal passed to said first gate terminal, and a second gate drive signal passed to said second gate terminal, said generating device generating the second gate drive signal in a delayed manner with respect to the first gate drive signal.