Patent ID: 8653856

Claim:
An electronic device comprising a buffer, the buffer having a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source, wherein the first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage, and the first current source is configured to adjust an output swing in a first operation mode and in a second operation mode, and the second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode, wherein the first current source and the second current source are configured to provide controlled series resistance in a third operation mode, and wherein the first current source and the second current source are transistors, the control gates of which are coupled to receive variable voltage levels in order to control the series resistance of the transistors in the third operation mode so as to adjust the rise and/or fall time of the signals at the first and second output node.