Patent ID: 8365116

Claim:
A method for circuit design cycle cutting using timing path analysis, the method comprising: using a computing device to perform the steps of: accessing a circuit design comprising a plurality of elements, interconnected by a plurality of edges, the circuit design further comprising timing constraints specified by a designer; identifying cycles in the circuit design; marking constrained edges by, for each timing constraint of the circuit design; identifying a set of timing paths in the circuit design that satisfy a timing constraint, selecting a timing constraint path from the identified set of timing paths using a greatest common path heuristic by identifying a shortest common path in the set of timing constraint paths, and marking input edges of elements in the selected timing constraint path as constrained; selecting cycle cuts to cut one or more of the identified cycles in the circuit design, the selection configured to preserve the timing constraints specified by the designer; and generating a directive to cause a computer-aided design (CAD) tool to implement the one or more selected cycle cuts.