Patent ID: 8884801

Claim:
An analog-to-digital conversion (ADC) system comprising for converting an analog signal to an n-bit digital signal, the system comprising: a flash ADC module being configured to perform k-bit analog-to-digital conversion, k being less than n and greater than or equal to 2, the flash ADC module having a predetermined offset value; a first sampling module configured to sample the analog signal during m/2 odd phases associated with a first plurality of channels, m being equal to n−k+2, and m being rounded to the nearest even number towards positive infinity; a second sampling module configured to sample the analog signal during m/2 even phases associated with a second plurality of channels; a first plurality of m/2 channels configured to process the m/2 phases, each of the channels corresponding to an even phase and comprising a SAR logic unit, and a comparator, each channel is configured to perform error correction using the predetermined offset value; a second plurality of m/2 channels configured to process the m/2 phases, each of the channels corresponding to an odd phase and comprising a SAR logic unit, and a comparator, each channel is configured to perform error correction using the predetermined offset value.