Patent ID: 7271617

Claim:
An electronic circuit with an array of programmable logic cells, each of the cells comprising: a plurality of programmable logic units coupled in parallel, and connected to receive input signals from an input circuit, the plurality of programmable logic units being configurable to operate in a multi-bit operand processing mode, wherein: each programmable logic unit includes: a configurable look-up table circuit that includes inputs coupled to receive the logic input signals from the input circuit and an output, the configurable look-up table providing an input output function in accordance with a predetermined number of configuration bits; and a controllable inverter/non-inverter circuit that includes an input connected to the output of the look-up table circuit and an output, the inverter/non-inverter being controllable by an input carry signal; and the predetermined number of configuration bits control the look-up tables of two or more programmable logic units in the programmable logic cells.