Patent ID: 7320081

Claim:
A clock-signal generation device for generating and outputting a clock signal, comprising: a reference-clock-signal generation circuit which generates a reference clock signal having a frequency; a frequency-division circuit which divides the frequency of the reference clock signal by using a natural number equal to or greater than one so as to generate a frequency-divided signal; a control circuit which controls the frequency-division circuit so as to modify the frequency-divided signal by inserting extension cycles into the frequency-divided signal at predetermined intervals, and output a modified, frequency-divided signal as the clock signal; an output circuit which outputs the clock signal generated by the control circuit, wherein the frequency-division circuit counts the reference-clock-signal by using a first counter outputting a count value, and divides the frequency of the reference-clock-signal by making an output signal of the frequency-division circuit “H” or “L” according to the count value of the first counter, and the control circuit inserts the extension cycles into the frequency-divided signal by temporarily suspending an operation of the first counter.