Patent ID: 8054098

Claim:
A secured integrated circuit, the integrated circuit comprising: a physical unclonable function (PUF) including an input circuit, a configurable delay circuit, and an output circuit serially coupled together; wherein the configurable delay circuit comprises one or more configurable delay chains of serially coupled configurable switching-delay elements, where each configurable delay chain comprises two parallel paths adapted to receive two signals, configurably switch and propagate the two received signals along the two parallel paths, and output two delayed signals for the output circuit; wherein the input circuit comprises an input network coupled to the one or more configurable delay chains, where the input network includes combinatorial logic, sequential logic, or another PUF configured to accept N challenge bits and to output M configuration bits for the one or more delay chains based on the N challenge bits to configure the switching-delay elements of the configurable delay chains, where N and M are integers; and wherein the output circuit comprises one or more arbiters coupled to last switching-delay elements of the one or more delay chains, where the one or more arbiters are configured to output a signal based at least in part on relative arrival of the two delayed signals output by respective ones of the coupled last switching-delay elements.