Patent ID: 7080176

Claim:
A bus control device comprising an external interface connected to an external device via an external system bus, an internal unit, a memory interface connected to an external local memory, and an internal bus at least connecting the external interface to the memory interface and connecting the internal unit to the memory interface, wherein the memory interface comprises a bus arbiter for arbitrating between a request for use of the internal bus by the external interface and by the internal unit, and a priority processing interval managing part for monitoring a usage pattern of the internal bus based on a result of an arbitration performed by the bus arbiter, the internal unit has a function of notifying the bus arbiter of an amount of data to be transferred, as well as requesting a use of the internal bus, the priority processing interval managing part notifies the bus arbiter and the external interface that only the external interface is permitted to use the internal bus, in a case where the internal unit is not using the internal bus and sets a priority processing interval during which only the external interface is capable of using the internal bus, the bus arbiter compares a previously set amount of data with the amount of data to be transferred, in a case of receiving a request for use of the internal bus and a notification of the amount of data to be transferred from the internal unit, during the priority processing interval, when the amount of data to be transferred is equal to or less than the previously set amount of data, the bus arbiter permits the internal unit to use the internal bus during the priority processing interval, and when the amount of data to be transferred exceeds the previously set amount of data, the bus arbiter prohibits the internal unit from using the internal bus while the priority processing interval is set.