Patent ID: 8327379

Claim:
A task processor comprising: a processing register that temporarily stores data for execution of a task; an execution control circuit including a memory interface with a memory that: loads an instruction and an operand from the memory interface from the memory into the processing register, and executes the task according to the instruction and operand in the processing register; a plurality of state registers that store data for respective tasks for task scheduling and respectively associated with a plurality of tasks; a task switching circuit that switches tasks; and a task selecting circuit that: receives state data output in parallel from the plurality of state registers, and selects a task according to a predetermined condition for selection, wherein the execution control circuit includes an instruction decoder that determines that the instruction to be executed is a predetermined system call instruction and transmits a predetermined system call signal to the task switching circuit when executing the predetermined system call instruction, the task selecting circuit selects a task for execution from among tasks in a READY state indicating that the task is executable and waits for execution irrespective of whether or not the predetermined system call occurs, and the task switching circuit switches between tasks by selecting a task to be executed next in accordance with an output from the task selecting circuit occurring when the system call signal is received, causes the data in the processing register to be saved in a predetermined storage area, updates the state data in the state register associated with the task being executed from RUN, indicates that the task is being executed to READY, causes data associated with the selected task and formerly saved in the storage area to be loaded into the processing register, and updates the state data in the state register associated with the selected task from READY to RUN.