Patent ID: 8819094

Claim:
A division circuit with decreased circuit area, comprising: an integrated circuit implementing multiplicative division of a dividend input and divisor input, comprising: a reciprocal circuit providing an approximation of a reciprocal of a divisor input; a plurality of multiplier circuits receiving the approximation and refining a quotient output of the dividend input and a divisor input, wherein at least one of the plurality of multiplier circuits is a squaring circuit implementing multiplication preventing the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number, wherein the plurality of multiplier circuits includes a first series of multiplier circuits with increasingly refined quotient outputs, and a second series of multiplier circuits with decreasing error adjustment outputs, and the second series of multiplier circuits includes the squaring circuit, wherein, after a first one of the increasingly refined quotient outputs, an addition of addends by the integrated circuit generates each of the increasingly refined quotient outputs, wherein a first one of the addends is a prior one of the increasingly refined quotient outputs, and a second one of the addends is a product of a first operand and a second operand, the first operand being one of the decreasing error adjustment outputs and the second operand being the prior one of the increasingly refined quotient outputs, wherein the second one of the addends has a precision, and the precision of the second one of the addends is smaller in the addition to generate any subsequent one of the increasingly refined quotient outputs, than the precision of the second one of the addends in the addition to generate any earlier one of the increasingly refined quotient outputs, wherein each of the plurality of multiplier circuits has a maximum input operand size, the maximum input operand size of any subsequent multiplier circuit in the first series of multiplier circuits is smaller than the maximum input operand size of any prior multiplier circuit in the first series of multiplier circuits, and the maximum input operand size of any subsequent multiplier circuit in the second series of multiplier circuits is smaller than the maximum input operand size of any prior multiplier circuit in the second series of multiplier circuits, wherein the squaring circuit operates on an input operand having an input width smaller than at least one of the dividend input and the divisor input, wherein the squaring circuit is computationally sufficient to compute a subsequent one of the decreasing error adjustment outputs from a prior one of the decreasing error adjustment outputs.