Patent ID: 8136001

Claim:
A method of introducing processor core functional tests into an on-chip cache operatively coupled between a processor core of a system on a chip (SoC) integrated circuit and an interface to a memory addressable by the processor core, the method comprising: scanning data pattern target and data pattern selection information from off-chip into respective fields of control registers; scanning at least a first data pattern from off-chip into on-chip data pattern storage accessible by an on-chip loader; scanning instruction target and opcode selection information from off-chip into second respective fields of the control registers; and under control of the on-chip loader, writing at least a first portion of a core functional test into the on-chip cache based on the data pattern target and the data pattern selection information scanned from off-chip, wherein the first portion of the core functional test includes at least the first data pattern scanned from off-chip, writing at least a second portion of the core functional test into the on-chip cache based on the instruction target and instruction selection information scanned from off-chip, wherein the introduced second portion of the core functional test includes at least one opcode for execution by the processor core.