Patent ID: 8687455

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array comprising: a plurality of common cell wells arranged in a first direction, each of the plurality of common cell wells being isolated from each other; a plurality of sub-blocks arranged in the first direction, each of the sub-blocks including a plurality of memory cells having a charge accumulation layer arranged in a form of a matrix of the first direction and a second direction, the second direction being perpendicular to the first direction, and the plurality of memory cells being formed in a corresponding one of the common cell wells; a plurality of word lines, each of the plurality of word lines being connected to a corresponding row of the plurality of memory cells; and a plurality of cell well driving lines, each of the plurality of cell well driving lines being electrically connected to a corresponding one of the common cell wells by contact holes formed at a plurality of points in the corresponding one of the common cell wells; a first block including a plurality of word line drivers, each of the word line drivers driving a corresponding one of the plurality of word lines, the first block being arranged at one side of the memory cell array; and a second block including a plurality of cell well drivers, each of the cell well drivers driving a corresponding one of the plurality of cell well driving lines, the second block being arranged at one side of the memory cell array, wherein the first block is arranged between the memory cell array and the second block.