Patent ID: 7145818

Claim:
A semiconductor integrated circuit device, comprising: a latch provided on an output of a memory circuit; wherein said latch includes a signal selector for switching between feedback signal of normal operation and test signal of test operation in compliance with an operation mode signal to send out to a feedback loop; wherein said latch has a first switch for sending a read-out signal from a memory cell in said memory circuit to an input terminal of a first inverter under control of a switch control signal, a second inverter for receiving an output signal of said first inverter on an input terminal, and a second switch for sending an output signal of said second inverter to the input terminal of said first inverter under control of said switch control signal, and said latch outputs a latch output signal from an output terminal of said second inverter; said signal selector has a third switch for sending an input signal fed to said memory circuit to the input terminal of said first inverter as the test signal under control of said switch control signal, and a signal generator for generating said switch control signal; and said signal generator turns off said third switch in the normal operation by said operation mode signal to perform a complementary switching control of said first and second switches by using clock pulses as said switch control signal, and turns off said first and second switches and turns on said third switch in the test operation by said operation mode signal.