Patent ID: 7275194

Claim:
A method of testing a circuit element under test comprising: generating a clocked test signal; decreasing the duty cycle of the clocked test signal until the capture register fails to receive the output of the circuit element under test; capturing an output of the element under test in a capture register at a clock edge through a multiplexer, wherein the element under test catches the clock edge and strobes an output, thereby strobing the multiplexer, said multiplexer comprising; a strobe on/off latch pair for capturing a TIMER_ON signal, a GLOBAL_CLOCK signal, and a GLOBAL CLOCK B signal, wherein the multiplexer outputs a signal to a DC MODE NAND gate and a signal to an AC MODE NAND gate; wherein the DC MODE NAND gate receives the GLOBAL CLOCK B signal and a DC MODE signal; wherein the AC MODE NAND gate receives the GLOBAL CLOCK signal and an AC MODE signal; and wherein the AC MODE NAND gate and the DC MODE NAND gate outputs being NANDED to an input of a capture register to thereby multiplex the AC mode and the DC mode of the capture register for comparison with a data output of the circuit element under test.