Patent ID: 8462141

Claim:
A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller comprising: an input memory which receives at an input of the input memory pixel data and transmits at an output of the input memory the pixel data through a main route and a secondary route; wherein, when in operation pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; the secondary route comprises a secondary memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; the display controller further comprises a detector for identifying a data feed latency event, and, in response thereto switching the transmission of the pixel data to the secondary route and processing the pixel data through the secondary route for delivery to the display such that when a data feed latency event occurs, causing missing pixel data in the main route, the stored two-dimensional section of the pixel data from the secondary route is displayed on the display to provide a two dimensional extrapolation to take the place of the missing pixel data; wherein the secondary route comprises an encoder for encoding on a line by line basis the pixel data and a decoder which can decode the stored encoded pixel data when required, and wherein the secondary memory stores encoded data: and wherein the decoder comprises an expander and an extrapolator, the extrapolator to receive at a first input of the extrapolator pixel data output from the expander and to receive at a second input of the extrapolator pixel data output from the input memory, wherein the extrapolation is based on the pixel data received at the first input of the extrapolator and the second input of the extrapolator.