Patent ID: 8217815

Claim:
A multi-path Σ-Δ modulator, comprising: a first integrator, coupled to a first path input end; a second integrator, coupled to a second path input end; a shared operational amplifier (op-amp), being alternately coupled to the first integrator and the second integrator to generate an integrated signal; two quantizers, respectively coupled to the first integrator and the second integrator, for comparing the integrated signal with a predetermined signal to output a digital signal; two digital-to-analog converters (DAC), respectively coupled between output ends of the quantizers and the first integrator and the second integrator, for converting the digital signal outputted by the quantizers into an analog signal that is fed to either the first integrator or the second integrator; and a clock signal generator, coupled to the first and second integrators and the quantizers, for providing clock signals for controlling the first and second integrators and the quantizers, wherein the shared op-amp comprises a negative input end, a positive input end and an output end, and the first integrator comprises: a first sampling component, coupled to the first path input end during a first period of a clock cycle and coupled to the negative input end of the shared op-amp during a second period of the clock cycle; and a first integrating component, coupled between the negative input end and the output end of the shared op-amp during the second period of the clock cycle; the second integrator comprises: a second sampling component, coupled to the second path input end during the second period of the clock cycle and coupled to the negative input end of the shared op-amp during the first period of the clock cycle; and a second integrating component, coupled between the negative input end of the output end of the shared op-amp during the first period of the clock cycle; wherein, the clock cycle is determined by the clock signal generator.