Patent ID: 7099426

Claim:
An elastic buffer for a stream of data blocks, each of the data blocks having a first width, the elastic buffer storing a first quantity of consecutive data blocks from the stream of data blocks in response to a write clock signal, the elastic buffer comprising: a memory space comprising a plurality of memory locations, each of the memory locations having the first width; and a controller circuit comprising: a write logic circuit for generating at least one write address in response to the write clock signal, the at least one write address corresponding to a second quantity of contiguous memory locations in the memory space for storing the first quantity of consecutive data blocks, the second quantity being the same as the first quantity; and a read logic circuit for generating a plurality of read addresses in response to a read clock signal, the plurality of read addresses corresponding to a third quantity of memory locations in the memory space, the third quantity being the same as the first quantity, wherein the third quantity of memory locations can be non-contiguous, wherein the plurality of memory locations are arranged in a fourth quantity of substantially identical memory arrays, the fourth quantity being the same as the first quantity, wherein the at least one write address corresponds to the same plurality of contiguous memory locations in each of the plurality of substantially identical memory arrays, and wherein each of the third quantity of memory locations is included in a different one of the fourth quantity of substantially identical memory arrays.