Patent ID: 7417909

Claim:
A semiconductor memory device comprising: means for precharging and equalizing a pair of bit lines; and means for generating a control signal which controls enable and disable of the precharging/equalizing means, wherein the control signal generating means includes a CMOS transistor; and a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor uses a bulk bias voltage of the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor, wherein the control signal generating means includes a PMOS transistor; and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage.