Patent ID: 7865666

Claim:
A cache memory system comprising: a central processing unit (CPU) and a first memory; a second memory positioned between the CPU and the first memory and storing at least one block of the first memory; a block quantity determination unit which determines a block quantity indicating a number of blocks of the first memory to be stored in the second memory, the block quantity being determined based on a number of times a reference address has been accessed; and a masking circuit which, based on an input address, generates a masking address, wherein if the number of times a reference address has been accessed does not exceed a reference value, one block is stored in the second memory, and if the number of times a reference address is accessed does exceed the reference value, a plurality of blocks are stored in the second memory, wherein the block quantity determination unit includes an index table including a plurality of entries, and an index comparator which compares the masking address with an index associated with each of the plurality of entries and generates a comparison signal indicating a result of the comparison, and wherein each of the plurality of entries includes an index storage unit which stores a given index and an access times storage unit which maintains a record of a number of times the given index has been accessed in response to the comparison signal by incrementing the record if the given index stored in the index storage unit matches the masking address.