Patent ID: 8839163

Claim:
A behavioral synthesis method comprising using a computer to perform the steps of: creating data flow graph information that is obtained by scheduling a timing of operation behavior of variables based on behavioral description information including the operation behavior of the variables, each of the variables being input data to operation or output data from operation; generating lifetime information for each of the variables based on the scheduled data flow graph information, the lifetime information being a period during which data needs to be held in the variable; selecting, among the variables, variables having lifetimes not overlapping on a time axis, based on the generated lifetime information; allocating a first register having a first bit width to a first variable included in the selected variables and bits of the first bit width within another variable included in the selected variables, the first variable being defined to have the first bit width; allocating a second register to bits other than the bits of the first bit width within the another variable; and outputting circuit information of a synthesized circuit including the first and second registers.