Patent ID: 7042040

Claim:
A semiconductor memory device comprising: a silicon substrate of a first conductivity type having a grid trench extending in two mutually orthogonal directions in an upper major surface of the silicon substrate, the trench having a trench width; a plurality of silicon columns formed on the major surface of the substrate and having a square upper surface defined by the trench, the square upper surface having a side length; a plurality of transistors each formed on a side surface of the respective silicon columns, each of the transistors comprising: a first impurity layer formed on the square upper surface of corresponding one of the silicon columns and serving as one of a source and a drain; a second impurity layer formed on a bottom of the trench adjacent to the corresponding one of the silicon columns and serving as the other of the source and the drain; a channel portion formed on a side surface of the corresponding one of the silicon columns between the first impurity layer and the second impurity layer; a gate insulating film formed on the channel portion; and a gate electrode formed over the channel portion with the gate insulating flim interposed therebetween; a plurality of capacitors each having two electrodes, one of the two electrodes being connected to the first impurity layer; a connection line configured to bring the second impurity layer, which is connected to the second impurity layer of an adjacent one of the transistors, out to the major surface of the silicon substrate; and a bit line formed above the major surface of the silicon substrate, wherein the connection line is insulatively buried in the trench so as to extend from the second impurity layer on the bottom of the trench to an upper side of the trench and be connected to the bit line, and wherein the plurality of silicon columns form an array of a matrix form and one pair of the silicon columns at both corners on a diagonal line of the matrix form are lacking.