Patent ID: 6839774

Claim:
A microcontroller comprising: a plurality of buses; a central processing unit (CPU) connected to said plurality of buses; a system clock input in signal communication with said CPU for receiving a system clock signal; a mode controller in signal communication with said CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection command; at least one bussed communication interface selectively connected to said plurality of buses; an electrically rewritable nonvolatile memory (NVM), being the only memory in the microcontroller, for storing data and control program; a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal; and a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said at least one bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals.