Patent ID: 7051934

Claim:
A method of forming a metal layer in an integrated circuit device, the method comprising: etching a recess in a surface of an insulating layer, the recess having a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall; etching a trench in the surface of the insulating layer on the recess that is wider than the recess, wherein the trench exposes the edge of the recess; forming a barrier metal layer in the recess and in the trench and on the insulating layer; forming a seed layer on the barrier metal layer; forming a selective electroplating mask on the seed layer on the side wall adjacent to the edge to provide a covered portion of the side wall and not on the side wall beyond adjacent to the edge to provide an exposed portion of the side wall; forming a first metal in the recess to beneath a level of the electroplating mask on the exposed portion of the side wall and not on the covered portion of the side wall; forming a second metal in the recess and in the trench on the first metal and on the selective electroplating mask; and planarizing the second metal layer to expose the selective electroplating mask.