Patent ID: 7582876

Claim:
An electronic device, comprising: an array of processing units, wherein each processing unit has an external coupling node and an internal coupling node; a binning circuit for selectively connecting the internal coupling nodes of several processing units each, wherein a set of coupled processing units constitutes a binning block; an addressing circuit for selectively addressing selected processing units; a number of signal lines, wherein the external coupling nodes of the processing units can selectively be connected to one of said signal lines under control of the addressing circuit in such a way that each of the signal lines is coupled to a different binning block; wherein the addressing circuit comprises row address lines that are connected to a selection logic in each processing unit of a corresponding row, and diagonal address lines that are connected to said selection logic in each processing unit, and wherein the selection logic is adapted to cause a connection of the external coupling node of the processing unit to a corresponding signal line if and only if both a corresponding row address line and a corresponding diagonal address line are activated.