Patent ID: 7034408

Claim:
A memory device comprising: memory cells, the memory cells being at least partially formed in a semiconductor substrate having a surface; bit lines extending in a first direction along the substrate; gate grooves extending in a second direction along the substrate, the second direction intersecting the first direction, the gate grooves being formed in the semiconductor substrate surface and including word lines disposed in the gate grooves; and peripheral circuitry comprising at least one peripheral transistor, the peripheral transistor comprising first and second peripheral source/drain regions, a peripheral channel connecting the first and second peripheral source/drain regions and a peripheral gate electrode controlling the conductivity of the peripheral channel, the peripheral gate electrode being formed of a peripheral gate stack comprising at least one layer, the peripheral circuitry being connected with the word lines and the bit lines; wherein: each of the memory cells comprises: an access transistor comprising first and second source/drain regions, a channel disposed between the first and second source/drain regions and a gate electrode that is electrically isolated from the channel and adapted to control the conductivity of the channel, the gate electrode of the access transistor forming part of the word lines and the word lines including a top surface disposed beneath the substrate surface, the access transistor being at least partially formed in the semiconductor substrate, and the first source/drain region being connected with a corresponding one of the bit lines via a bit line contact; and storage elements for storing information, the storage elements being adapted to be accessed by the access transistor; and the bit lines including the bit line contacts are made of a bit line stack comprising at least one layer that is identical to the peripheral gate stack.