Patent ID: 7461383

Claim:
A method for monitoring performance of simultaneous occurring events in a single or multiprocessor computer system comprising: counting signals representing occurrences of events from event sources at a hybrid counter array device having a first counter portion including one or more counter devices, and providing a first count value corresponding to lower order bits of a count, said hybrid counter array device having a second counter portion comprising a memory array device having addressable memory locations, each said addressable memory location for storing a second count value for a respective counter device representing higher order bits of said count, a combination of said first and second count values providing a count of a number of events received at a counter device; providing a respective overflow bit device associated with each respective counter device, and setting an overflow bit in said overflow bit device when an associated counter device reaches an overflow condition; monitoring, by a control means, each respective overflow bits of each associated overflow bit device of said first counter portion, and incrementing a value of a corresponding said second count value stored at said addressable memory location in said second counter portion in response to a respective overflow bit of an associated overflow bit device being set, and resetting said overflow bit means after said incrementing; enabling one or more of: read access or write access to both said first count value in said first counter portion and said second count value in said second counter portion, said read access or write access for purposes of initializing and determining status of said first and second count values in respective first and second counter portions for a monitored event type in response to a processor device request; providing a fast interrupt trigger signal to a processor device when one or more count values related to an event type equals a desired interrupt threshold value, said fast interrupt trigger signal provided by: comparing, at a comparison device, a second count value against a pre-determined threshold value; setting an interrupt arming device associated with a respective counter device for enabling fast interrupt indication to a processor device of said single or multiprocessor computer system in response to an associated second count value being equal to said pre-determined threshold value, said pre-determined threshold value equaling said desired interrupt threshold value decremented by one; and asserting said fast interrupt trigger signal when said overflow bit means corresponding to a counter device is set and said interrupt arming device for said counter device is set, wherein said fast interrupt trigger signal is asserted independent of a state of said control means.