Patent ID: 7877658

Claim:
A circuit comprising: A. test access port circuitry having: i. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; ii. a controller having inputs connected to the TMS and TCK leads and having a ClockDR output, a CaptureDR State output, and a ShiftDR State output; iii. an instruction register having a TDI input connected to the TDI lead and an auxiliary enable output, the instruction register including first gating circuitry having: a. a functional clock input, a ClockDR input connected with the ClockDR output, and a Clock output selectively coupled with the functional clock input and the ClockDR input; b. a gated capture input and a Capture output selectively coupled with the gated capture input and a first logic state; and c. a gated shift input and a Shift output selectively coupled with the gated shift input and a second logic state; and iv. a data register of serially connected scan cells, each scan cell having inputs connected to the Clock output, the Capture output, and the Shift output, and being coupled in series between the TDI lead and the TDO lead; B. a wrapper serial port having a capture lead, a shift lead, a WSI lead, and a WSO lead, the WSI lead being coupled to the TDI input of the data register, and the WSO lead being coupled to the TDO output of the data register; and C. second gating circuitry having: i. a CaptureDR input connected to the CaptureDR State output; ii. a ShiftDR input connected to the ShiftDR State output; iii. a shift input connected to the shift lead; iv. a capture input connected with the capture lead; v. an aux enable input connected to the aux enable output; vi. a gated capture output coupled with the CaptureDR input and the capture input and connected with the gated capture input of the first gating circuitry; and vii. a gated shift output coupled with the ShiftDR input and the shift input and connected with the gated shift input of the first gating circuitry.