Patent ID: 8358549

Claim:
A semiconductor memory device comprising: a plurality of RAM macros; and a test control circuit configured to correlate said plurality of RAM macros with a plurality of memory test execution periods, wherein said test control circuit outputs control signals to said plurality of RAM macros such that one RAM macro of said plurality of RAM macros is tested during one memory test execution period of said plurality of memory test execution periods, said one RAM macro being correlated with said one memory test execution period, wherein said plurality of RAM macros is correlated with a plurality of powers, wherein said plurality of memory test execution periods is set such that, when a plurality of simultaneous test RAM macros in said plurality of RAM macros is simultaneously tested, the sum of powers supplied to said plurality of simultaneous test RAM macros in said plurality of powers is smaller than the maximum power possible to be supplied to said plurality of RAM macros, wherein said plurality of memory test execution periods is further set such that said plurality of RAM macros is tested to minimize an amount of time for testing.