Patent ID: 8063671

Claim:
A driving circuit of switch devices, comprising a transformer, an input terminal of a driving signal and a switch device, with the input terminal of the driving signal connecting to a primary side of the transformer and the switch device connecting to a secondary side of the transformer, wherein: the number of said transformers is two; the primary sides of the two transformers are connected to two driving modulators, respectively; one terminal of the primary side of a first transformer T 1 is grounded while the other terminal is connected to an output terminal of a first driving modulator U 1 A; an input terminal of a high frequency carrier signal and the input terminal of the driving signal are connected to an input terminal of the first driving modulator U 1 A; one terminal of the primary side of a second transformer T 2 is grounded while the other terminal is connected to an output terminal of a second driving modulator U 2 A; the input terminal of the driving signal is connected to an input terminal of an inverter U 3 A; an output terminal of the inverter U 3 A and the input terminal of the high frequency carrier signal are connected to an input terminal of the second driving modulator U 2 A; a secondary side of the first transformer T 1 is connected to a power supply circuit which may provide necessary voltage for turning on the switch device during a high level period of the driving signal; and a secondary side of the second transformer T 2 is connected to a voltage discharging circuit which may discharge the turn-on voltage of the switch device into a low level during a low level period of the driving signal, wherein the number of the secondary side of said first transformer T 1 is two; said power supply circuit comprises an electrolytic capacitor C 1 and a power charging driving switch transistor Q 1 having its gate and source connected respectively to two output terminals of the second secondary side of the first transformer T 1 ; the first secondary side of the first transformer T 1 , after being rectified, is connected in parallel with the electrolytic capacitor C 1 ; a negative terminal of the electrolytic capacitor C 1 is connected to a source of a switch device QS; a positive terminal of the electrolytic capacitor C 1 is connected to a drain of the power charging driving switch transistor Q 1 ; a gate of the switch device QS is connected to a source of the power charging driving switch transistor Q 1 .