Patent ID: 8530969

Claim:
A semiconductor device, comprising: a substrate, having a deep well; a gate structure, disposed above the deep well; a source structure, disposed in the deep well, and located at a first side of the gate structure; and a drain structure, disposed in the deep well, and located at a second side of the gate structure, wherein the drain structure comprises: a first doped region of a first conductivity type, disposed in the deep well; a first electrode, electrically connected to the first doped region; and a second doped region of a second conductivity type, disposed in the first doped region and between the first electrode and the gate structure, wherein the deep well is a deep N type well, the first doped region comprises an N-grade region and a first N+ region, the first N+ regions is disposed in the N-grade region, the second doped region is a first P+ region comprising a plurality of isolated P+ sub-regions arranged in the first N+ region.