Patent ID: 8154335

Claim:
A system, comprising: a system on chip (SoC) having a digital domain; an adaptive voltage scaling circuit including a critical path replica circuit with respect to the digital domain, the critical path replica circuit configured to generate a margin signal, the adaptive voltage scaling circuit configured to vary a bias voltage applied to the digital domain of the system on chip in response to the margin signal; and a fail-safe timing sensor for a critical path circuit within the digital domain of the system on chip, the timing sensor comprising: a first delay coupled to a clock input and configured to generate a delay clock signal; a second delay coupled to a data input and configured to generate a delay data signal; a window generator configured to receive the clock input and delay clock signal and generate a timing window; and a transition detector configured to receive the delay data signal and timing window and generate a flag signal in response to the delay data signal changing state within the timing window; wherein the adaptive voltage scaling circuit is configured to vary the bias voltage applied to the digital domain of the system on chip in response to the flag signal.