Patent ID: 7023734

Claim:
A method of overerase correction for memory cells in a memory array after the memory cells have been erased, comprising the following steps: (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level; (b) applying a series of overerase correction pulses to said first selected bit line during a selected time period; (c) detecting during said selected time period whether said bit line exhibits leakage current above said threshold value; (d) if said bit line exhibits leakage current above said threshold value after said selected time period, increasing said gate voltage and repeating steps (b) and (c); and (e) if it is detected that said bit line does not exhibit leakage current above said threshold value during said selected time period, selecting a second bit line and repeating steps (a) through (d).