Patent ID: 7115447

Claim:
A manufacturing method of a semiconductor device comprising: forming a laminate layer comprising a lower first conductive layer and an upper second conductive layer over a semiconductor layer with a gate insulating film interposed between the semiconductor layer and the conductive layers; forming a mask pattern over the laminate layer; forming a first conductive layer pattern having a tapered edge by etching the second conductive layer and the first conductive layer; after forming the first conductive layer pattern, recessing an edge of the mask pattern remaining on the first conductive layer pattern; after recessing the edge of the mask pattern, forming a second conductive layer pattern by selectively etching the second conductive layer in the first conductive layer pattern in accordance with the recessed mask pattern using a processing step different from a processing step used to recess the edge of the mask pattern remaining on the first conductive layer pattern; and forming an LDD region in a region of the semiconductor layer overlapping with the first conductive layer in the second conductive layer pattern by using the second conductive layer in the second conductive layer pattern as a mask for shielding ions accelerated by an electric field.