Patent ID: 7924921

Claim:
In a computing device that implements a video encoder, the computing device including a processor and memory, a method comprising: with the computing device that implements the video encoder, in a bitstream comprising plural layers, inserting plural different entry point segment control parameters in an entry point header below sequence layer but above picture layer in the bitstream, each of the plural different entry point segment control parameters affecting decoding or display of one or more pictures in an entry point segment of the bitstream, wherein the plural different entry point segment control parameters comprise: a pan scan on/off parameter that indicates whether pan scan information is present, a reference frame distance on/off parameter that indicates whether a reference frame distance syntax element is present in respective picture headers for selected types of pictures within the entry point segment, a loop filtering on/off parameter that indicates whether loop filtering is enabled, a fast chroma motion compensation on/off parameter that controls rounding of chroma motion vectors, an extended range motion vector on/off parameter that indicates whether extended range motion vectors are enabled, a variable sized transform on/off parameter that indicates whether variable sized transform coding is enabled, an overlapped transform on/off parameter that indicates whether overlapped transforms are used, a quantization decision parameter that indicates whether quantization step size is variable within a picture, and an extended differential motion vector coding on/off parameter that indicates whether use of extended range coding of differential motion vector information is signaled for selected types of pictures within the entry point segment; and with the computing device that implements the video encoder, outputting the entry point header as part of the bitstream.