Patent ID: 8445322

Claim:
A method for fabricating a semiconductor package, comprising the steps of: providing a mother substrate having a first face, a second face facing away the first face, a first circuit pattern formed in a respective first chip region included in a respective first chip group formed over the first face, and a second circuit pattern formed in a respective second chip region included in a respective second chip group formed over the second face; attaching a first semiconductor chip to the first chip region such that the first semiconductor chip is electrically connected to the first circuit pattern; attaching a second semiconductor chip to the second chip region such that the second semiconductor chip is electrically connected to the second circuit pattern, so a unit package comprising the mother substrate, the first semiconductor chip and the second semiconductor chip is formed; covering the first and second semiconductor chips and fully filling between the first and second circuit patterns and the first and second semiconductor chips by disposing adhesive members over the first and second faces; disposing cover substrates over the first and second faces by respectively covering the adhesive members disposed thereon to be fully filled between the unit package and the cover substrates by the adhesive members; and forming a connection electrode passing through the mother substrate, the first and second circuit patterns, the adhesive members, and the cover substrates to electrically connect the first and second circuit patterns together.