Patent ID: 7855591

Claim:
A system for providing an output voltage greater than a voltage provided by a voltage supply in a semiconductor device, the system comprising: a clock coupled to provide a plurality of clock signals; a first stage including: a first pumping node coupled to a first pumping capacitor; a first input P-type device coupled between an input and the first pumping node to transfer charge from the input to the first pumping capacitor; a first middle P-type device coupled between the first pumping node and a gate of the first input P-type device to transfer charge from the first pumping capacitor to the gate of the first input P-type device to turn off the first input P-type device; and a first auxiliary device coupled to a gate of the first middle P-type device to lower a voltage at the gate of the first middle P-type device to an undershoot voltage to turn on the first middle P-type device to transfer charge from the gate of the first input P-type device to the first pumping capacitor; and a second stage coupled with the first stage and including a second pumping node, the clock being coupled to provide a first portion of the plurality of clock signals to the first stage and a second portion of the plurality of clock signals to the second stage, the first stage and the second stage being configured to alternately transfer charge to the output based on the plurality of clock signals.