Patent ID: 6917085

Claim:
A semiconductor transistor comprising: a gate pattern formed on a semiconductor substrate; an L-shaped upper spacer having a horizontal protruding portion protruding from a vertical portion thereof, the upper spacer being formed on a sidewall surface of the gate pattern; an L-shaped lower spacer having a vertical sidewall between a vertical sidewall of the L-shaped upper spacer and the gate pattern and a horizontal protruding portion protruding from the vertical sidewall thereof between the horizontal protruding portion of the L-shaped upper spacer and the substrate, the horizontal protruding portion of the L-shaped upper spacer extending beyond the horizontal protruding portion of the L-shaped lower spacer; a high-concentration junction area formed to a first depth in the substrate beyond the L-shaped upper spacer; a low-concentration junction area formed to a third depth in the substrate under the horizontal protruding portion of the L-shaped upper spacer,the first depth being greater than the third depth; and a medium-concentration junction area formed to a second depth in the substrate and positioned between the high- and low-concentration junction areas and beyond the vertical sidewall portion of the L-shaped upper spacer, the second depth being between the first and third depths.