Patent ID: 7414889

Claim:
A method for operating an AND memory array having columns of bandgap engineered SONOS (BE-SONOS) devices, each column of BE-SONOS devices corresponding to a sub-gate line and a wordline, comprising: resetting a plurality of BE-SONOS devices in the AND memory array, the plurality of BE-SONOS devices producing a self-converging reset to reset a threshold voltage Vt value; programming electrically a selected BE-SONOS device in a first column of the BE-SONOS devices, the first column of the BE-SONOS devices corresponding to a first wordline to which is applied a high voltage, the first column of the BE-SONOS devices corresponding to a first sub-gate line to which is applied a low voltage to perform source side injection; and erasing electrically the plurality of BE-SONOS devices in the AND memory array, the plurality of BE-SONOS devices producing a self-converging erase to the reset voltage threshold Vt value.