Patent ID: 8260996

Claim:
A method for handling interrupts within a multiprocessor computing system, the method comprising: establishing a preferred processor list for executing an interrupt handler within the multiprocessor computing system, wherein the preferred processor list comprises two or more processors within the multiprocessor computing system ordered by preference to execute the interrupt handler; receiving an interrupt associated with the interrupt handler; responsive to receiving the interrupt, determining an interrupt priority level of the interrupt handler; broadcasting an interrupt message containing the interrupt priority level to at least the two or more processors in the preferred processor list; receiving acceptance messages from one or more accepting processors within the multiprocessor computing system in response to the interrupt message, wherein the one or more accepting processors comprise processors that are idle or are currently executing a task having a lower priority level than the interrupt priority level; and responsive to receiving the acceptance messages, assigning, using an arbiter, the interrupt handler to a preferred processor in the one or more accepting processors having a higher preference according to the preferred processor list.