Patent ID: 8772106

Claim:
A method for manufacturing a memory cell array, the method comprising: forming a plurality of word lines comprising doped semiconductor material having a first conductivity type; forming a dielectric overlying the word lines and an array of vias in the dielectric to expose portions of the word lines; forming a plurality of doped semiconductor regions within the exposed portions of the word lines, the doped semiconductor regions having a conductivity type opposite the first conductivity type, whereby diodes are formed; forming a plurality of metal-oxide memory elements within the array of vias, the memory elements programmable to a plurality of resistance states including a first and a second resistance state; forming conductive elements underlying metal-oxide memory elements and electrically coupling the respective metal-oxide memory elements to the doped semiconductor regions, wherein the metal-oxide memory elements comprise respective metal-oxide bodies that have oxygen contents which increase with distance from the conductive elements; and forming a plurality of bit lines overlying the plurality of metal-oxide memory elements.