Patent ID: 8890588

Claim:
A circuit configured for asymmetric ageing prevention, the circuit comprising: a primary clock configured to generate a primary clock signal; a secondary clock configured to generate a secondary clock signal; a state determination circuit coupled with the primary clock and the secondary clock, the state determination circuit configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset (POR) condition in an integrated circuit (IC), the current operating state being one of a first operating state and an second operating state; a control circuit coupled with the state determination circuit and configured to generate a control signal in response to a determination that the current operating state corresponds to the first operating state, the control signal configured to facilitate a transition from the primary clock to the secondary clock upon or subsequent to the determination that the current operating state corresponds to the first operating state, the secondary clock being associated with a safe operating mode of the IC, and the control signal further configured to facilitate a transition from the safe operating mode to a normal operating mode upon or subsequent to a determination that the current operating state corresponds to the second operating state; and a reset circuit coupled with the secondary clock and the control circuit, wherein the reset circuit is configured to prevent the POR condition until the determination that the current operating state corresponds to the second operating state, wherein, the first operating state comprises a low power operating state or an invalid operating state, and the second operating state comprises a power-on operating state or a valid operating state.