Patent ID: 7797520

Claim:
A data processing apparatus, comprising: a processor for executing instructions; a prefetch unit for prefetching instructions from a memory prior to sending those instructions to said processor for execution; branch prediction logic; and a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information including, identification of an instruction specifying a branch operation, a target address for said branch operation and a prediction as to whether said branch operation is taken or not; wherein said prefetch unit is configured prior to fetching an instruction from said memory, to access said branch target cache and to determine if there is predetermined information corresponding to said instruction stored within said branch target cache and if there is to retrieve said predetermined information; said branch prediction logic is responsive to said retrieved predetermined information to predict whether said instruction specifies a branch operation that will be taken and will cause a change in instruction flow, and if so to indicate to said prefetch unit a target address within said memory from which a following instruction should be fetched; wherein said access to said branch target cache is initiated at least one clock cycle before initiating fetching of said instruction from said memory.