Patent ID: 7082517

Claim:
A superscalar processor in which instructions of the same or different types are dispatched and executed in parallel in multiple execution units, comprising: a decoder unit for decoding fetched complex and specialized multi-cycle execution instructions and for loading them into an instruction queue buffer; a dispatch unit for examining the loaded complex multifunctional or multi-cycle instructions in said instruction queue buffer and grouping them for execution, and dispatching said grouped complex multifunction and multi-cycle instructions via instruction dispatch ports to a fixed point execution unit (FXU) for execution of the dispatched instructions in parallel in multiple execution pipelines of said superscalar processor, and wherein the dispatch unit groups and dispatches the instructions upon encountering a multifunctional or multi-cycle execution instruction and dispatches it alone to a single port of the FXU but duplicates the instruction's text to other ports, and wherein the execution of the multifunctional or multi-cycle execution instruction is capable of being distributed across the multiple execution pipelines.