Patent ID: 7559000

Claim:
A semiconductor integrated circuit device comprising: a logical circuit which is a diagnosis target not yet mounted onto a disk array apparatus; and a self-diagnosis circuit; wherein the self-diagnosis circuit includes: a memory which stores, in response to a load command, a plurality of test programs each including actual in-use operating conditions of a logical circuit which is deemed to have identical hardware and software characteristics as the diagnosis target and is mounted onto the disk array apparatus which is operating; a memory control unit which configures said memory into a plurality of storage areas, and sequentially and alternately stores in said storage areas said plurality of test programs in a partially overlapping manner; an arithmetic unit which executes the test programs stored in the memory in series, in response to a diagnosis command; a pattern generation unit which generates a pattern to command the diagnosis target to operate in accordance with one of the test programs being executed by the arithmetic unit, and inputting the generated pattern to the diagnosis target; an expected value generation unit which generates an expected value as the assumed test result for the diagnosis target, corresponding to the pattern generated by the pattern generation unit; a compressor which compresses pattern data showing the test result of the diagnosis target obtained by inputting the pattern, and expected value pattern data showing the expected value generated by the expected value generation unit; and a diagnosis unit which compares the test result pattern data compressed by the compressor, with the expected value pattern data, thereby diagnosing whether or not there is an abnormality in the diagnosis target.