Patent ID: 7391075

Claim:
A non-volatile semiconductor memory device, comprising: a substrate, said substrate including a source region, a drain region and a channel region provided between said source region and said drain region; and a gate stack located above said channel region, said gate stack including a sequential stack of a tunnel layer, a charge trapping layer, a charge blocking layer and a control gate, wherein said tunnel layer is adjacent to said channel region, and wherein said control gate is metal gate comprised of a metal having a specific metal work function in the range of equal or greater than 4.9 eV to equal or less than 5.5 eV, wherein the blocking layer is a high κ dielectric having a dielectric value above 4.2, wherein the memory device is a floating gate memory device and the charge trapping layer is a floating gate, and wherein said floating gate is a metal gate comprised of a metal having a specific metal work function of equal or greater than 4.9 eV, and wherein the tunnel layer is a high-κ dielectric.