Patent ID: 8329574

Claim:
A method for fabricating a memory device comprising: forming an isolation layer in a semiconductor substrate to define active regions, the active regions including a pair of closely spaced-apart active regions in parallel with each other; forming a plurality of gate patterns crossing the active regions, each gate pattern having a gate electrode crossing the active regions; forming an insulating interlayer on the semiconductor substrate; forming a bit line contact hole exposing the active regions by patterning the insulating interlayer, the active region(s) having a first width and the bit line contact hole having a second width in a bottom portion; forming a bit line contact plug in the bit line contact hole; and forming a shared bit line on the bit line contact plug and on the insulating interlayer; wherein, when the second width is greater than the first width, the isolation layer adjacent to the active regions is recessed to expose both sidewalls of the active regions during forming the bit line contact hole.