Patent ID: 7847582

Claim:
A logic circuit comprising: a plurality of master-slave flip-flop circuits comprising: a first master latch included in one of said master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data; a second master latch included in one of said master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data; a third master latch included in one of said master-slave flip-flop circuits, the third master latch having a third scan data input operatively connected to receive an output of the second master latch, the third master latch latching the scan data inputted into the third scan data input and outputting latched scan data; and a slave latch included in one of said master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the third master latch, the slave latch latching the scan data inputted into the scan data input and outputting latched scan data: wherein a first clock signal is inputted into the first master latch, a second clock signal is inputted into the second master latch, a third clock signal is inputted into the third master latch and a fourth clock signal is inputted into the slave latch.