Patent ID: 7078280

Claim:
A process for fabricating an integrated circuit structure comprising: forming a first contact region selected from the group consisting of a source contact region and a drain contact region of a semiconductor device in a semiconductor substrate; forming a multilayer stack comprising at least three layers of material over the first contact region, wherein the second layer is interposed between the first and the third layers and wherein the first layer is proximate the first contact region; forming a window in the at least three layers of material, wherein the window does not extend into the first contact region; forming a semiconductor material along at least one vertical wall of the window, wherein the semiconductor material comprises vertically-oriented first, second and third doped regions, and wherein the first doped region is adjacent the first layer and further is in electrical contact with the first contact region, and wherein the second doped region of the semiconductor material is adjacent the second layer, and wherein the third doped region is adjacent the third layer; forming an insulating material on the inwardly-facing surface of at least the first and the third doped regions in the window; removing the second layer, thereby exposing at least a portion of the second doped region; forming a gate dielectric layer in contact with the second doped region; and forming a gate in contact with said gate dielectric layer.