Patent ID: 8527726

Claim:
A storage circuit, including: multiple storage tiles corresponding to a single level of storage access that provides for arbitrary access to any one of the multiple storage tiles, wherein values stored within the storage circuit are associated with unique corresponding ones of the multiple storage tiles, and wherein a particular one of the multiple storage tiles is a front-most tile having an interface connection at which responses to read access requests directed at any of the multiple storage tiles are provided to a requesting device from a storage within the front-most tile; and control logic for accessing the values within the multiple storage tiles, wherein the control logic moves the values among the multiple storage tiles according to a placement heuristic in response to an access to one of the multiple storage tiles while maintaining the uniqueness of the values within the multiple storage tiles to move a requested value to the front-most tile, and wherein the control logic further moves the values among the multiple storage tiles according to a global clock, whereby multiple move-to-front operations are simultaneously maintained in-progress among the multiple storage tiles; wherein the control logic is distributed at the storage tiles, and implements the placement heuristic by the response of the storage tiles to requests received at the storage tiles; and wherein the global clock controls movement of access requests and movement of the values between the storage tiles along an information pathway formed only by connections between adjacent ones of the multiple storage tiles within an array formed by the multiple storage tiles, wherein the connections between adjacent ones of the multiple storage tiles include a spiral cache pattern path from the front-most tile and a diagonal path from the front-most tile.