Patent ID: 7274066

Claim:
A semiconductor memory device having a plurality of unit cells, each unit cell comprising: a semiconductor substrate; a source region and a drain region in the semiconductor substrate and spaced from each other; first and second data lines disposed to run across and over a single channel region between the source and drain regions, and disposed adjacent to the source and drain regions, respectively; a first multiple tunnel junction (MTJ) barrier layer pattern disposed between the first data line and the channel region; a second MTJ barrier layer pattern disposed between the second data line and the channel region; a first floated storage node disposed between the first MTJ barrier layer pattern and the channel region; a second floated storage node disposed between the second MTJ barrier layer pattern and the channel region; and a word line disposed to run across and over the first and second data lines, and disposed to cover both sidewalls of the first and second MTJ barrier layer patterns and both sidewalls of the first and second storage nodes.