Patent ID: 7777539

Claim:
A delay adjusting circuit comprising: a delay part in which delay elements of n+1 (n≧2) stages are connected to each other in series, and to which a first reference signal is inputted; a first counter for counting a transition edge of a signal of an n−1-th stage of the delay part from a first logic level to a second logic level when the first reference signal is at the second logic level; a second counter for counting a transition edge of a signal of an n+1-th stage of the delay part from the first logic level to the second logic level when the first reference signal is at the second logic level; and a delay element adjusting part for outputting a correct bias signal in response to count result of the first counter and the second counter, wherein a delay time of the delay part is adjusted, in response to the correct bias signal, to the state in which the first counter does not perform counting operation and the second counter performs counting operation.