Patent ID: 8334913

Claim:
An analog-to-digital converter circuit, comprising: a comparator configured to compare a first analog signal voltage with a first reference voltage, which changes at a constant gradient from a first voltage larger than the first analog signal voltage to a voltage smaller than the first analog signal voltage, and to compare a second analog signal voltage with a second reference voltage, which changes at a constant gradient from a second voltage larger than the second analog signal voltage to a voltage smaller than the second analog signal voltage; a binary counter configured to receive an output signal of the comparator and a clock signal, and to count the clock signal based on an output signal of the comparator to generate a count output having a plurality of bits, and to count the clock signal for a first period until the first reference voltage becomes equal to the first analog signal after the comparator starts to compare the first reference voltage with the first analog signal voltage, and to invert a logic level of the count output having a plurality of bits after the first period elapses, and to count the clock signal for a second period until the second reference voltage becomes equal to the second analog signal after the comparator starts to compare the second reference voltage with the second analog signal voltage, and further, to output the count output having a plurality of bits after the second period elapses as a conversion result of a potential difference between the first and second analog signal voltages; and a control circuit configured to carry out a control for inverting the logic level of the count output of the binary counter; wherein the binary counter includes: a first logical product gate circuit configured to output the clock signal based on an output signal of the comparator; and a plurality of multi-stage connected one-bit counters corresponding to the number of bits of the count output; each of the one-bit counters including: a flip-flop circuit including a data input terminal, a clock input terminal, a data output terminal, and an inverted data output terminal, the inverted data output terminal and the data input terminal being connected; and a second logical product gate circuit configured to supply with the clock signal output from the first logical product gate circuit an inversion control signal in a least significant bit, and to supply with a signal of the inverted data output terminal of the flip-flop circuit of a lower bit an inversion control signal in each bit except the least significant bit, and to take the logical product of the two signals, and to supply the logical product to the clock input terminal of a corresponding one of the flip-flop circuits.