Patent ID: 7057405

Claim:
A wafer test method, comprising the steps of: providing a wafer integrally formed of a plurality of chips, each of the chips having an active surface and an opposite inactive surface, with a plurality of bond pads formed on the active surface; preparing a conductive interposer composed of a plurality of interposer units each corresponding to one of the chips, each of the interposer units having a first surface and an opposite second surface, wherein the first surface of each of the interposer units is formed with a solder mask having a plurality of openings and a plurality of test pads exposed via the openings of the solder mask, and the second surface of each of the interposer units is formed with a plurality of test bumps electrically connected to the test pads, the test bumps corresponding to the bond pads of the chips, and mounting the conductive interposer on the wafer such that the test bumps are in electrical contact with the bond pads to electrically connect the conductive interposer to the chips; and using test probes to contact the test pads of the conductive interposer to perform tests for the chips of the wafer.