Patent ID: 8555227

Claim:
A computer implemented method of circuit conception of a clock tree comprising: a plurality of pulse generators each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal; and a tree of buffers for supplying a clock signal to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree wherein during said clock edge timing analysis each of the buffers of said clock tree is implemented by a circuit identical to said pulse generators except that its pulse generation function is rendered inactive by said computer, and said step of replacing the final buffer before each latch by a pulse generator comprises reactivating by said computer the pulse generation function of said final buffers; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.