Patent ID: 8321622

Claim:
A storage control device, comprising: a first controller; and a second controller connected to the first controller via a first path, wherein when the first controller or the second controller receives an input/output (I/O) command issued by a host device, the controller receiving the I/O command carries out an I/O process, in accordance with the I/O command, and carries out I/O of data in accordance with the I/O command with respect to a storage device during the I/O process, the first controller includes: a first relay circuit, which is a circuit that controls data transfer; and a first processor connected to the first relay circuit via a first second path, the second controller includes: a second relay circuit, which is a circuit that controls data transfer, and which is connected to the first relay circuit via the first path; and a second processor connected to the second relay circuit via a second second path, the first processor is connected to the second relay circuit directly via a first third path which is different from the first path and the first second path, not via the first relay circuit, the first path and the first second path, while the first controller is carrying out the I/O process, when the first processor sends the first relay circuit an instruction of data transfer using a resource of the first relay circuit, the first processor accesses the first relay circuit via the first second path, and when the first processor sends the second relay circuit an instruction of data transfer using a resource of the second relay circuit, the first processor accesses the second relay circuit via the first third path, and the second processor is connected to the first relay circuit directly via a second third path which is different from the first path and the second second path, not via the second relay circuit, the first path and the second second path, when the second processor sends the second relay circuit an instruction of data transfer using resource of the second relay circuit, the second processor accesses the second relay circuit via the second second path, and when the second processor sends the first relay circuit an instruction of data transfer using resource of the first relay circuit, the second processor accesses the first relay circuit via the second third path.