Patent ID: 7728629

Claim:
An apparatus comprising a buffer having one or more buffer stages connected in series, wherein at least one buffer stage comprises: a stage input node adapted to receive a stage input signal; a stage output node adapted to present a stage output signal; a buffer circuitry connected between the stage input node and the stage output node; and at least one explicit inductor connected between the stage output node and a voltage reference node for the buffer stage, such that the at least one explicit inductor is adapted to reduce apparent load capacitance of circuitry connected to the stage output node, wherein: the at least one explicit inductor is directly connected to both (1) the stage output node and (2) the voltage reference node for the at least one buffer stage, wherein the at least one explicit inductor comprises: a first inductor connected between the stage output node and a first voltage reference node; and a second inductor connected between the stage output node and a second voltage reference node.