Patent ID: 8854890

Claim:
A three-dimensional memory device, comprising: a substrate; a plurality of sets of non-volatile storage elements formed above the substrate in multiple physical levels of a three-dimensional memory array, each of the sets having an active area comprising a channel that extends vertically through the physical levels; a plurality of bit lines associated with the plurality of sets of non-volatile storage elements; a plurality of word lines associated with the plurality of sets of non-volatile storage elements; and a circuitry in communication with the plurality of sets of non-volatile storage elements, the plurality of bit lines and the plurality of word lines, the circuitry applies a first voltage to unselected word lines during a channel pre-charge phase of a programming operation, the circuitry applies a second voltage that is greater than the first voltage to a selected word line during the channel pre-charge phase, the circuitry increases the first voltage on the unselected word lines to a boosting voltage during a boosting/programming phase of the programming operation, the circuitry increases the second voltage on the selected word line to a third voltage that is greater than the boosting voltage during the boosting/programming phase, the circuitry increases the third voltage to a program voltage on the selected word line while maintaining the boosting voltage on the unselected word lines during the boosting/programming phase.