Patent ID: 6838725

Claim:
A stacked-gate flash memory cell having a floating Poly-Si gate with multiply connected surfaces of individual shapes comprising: a semiconductor substrate having an active area; a floating Poly-Si gate with a bottom surface and a multiply connected top surface; said bottom surface being flat and overlying said active area; said multiply connected top surface overlying said bottom surface; said multiply connected top surface being defined by multiple regions of individual cross-sectional shapes, wherein the area of said multiply connected top surface overlying said active area is greater than the area of said bottom surface; wherein said individual cross-sectional shapes are selected from a group consisting of rectangular, trapezoidal and triangular shapes; a conformal inter-poly dielectric layer replicating said individual cross-sectional shapes over said floating Poly-Si gate; and a conformal Poly-Si control gate replicating said individual cross-sectional shapes over said inter-poly dielectric layer; wherein said regions of individual cross-sectional shapes have a depth between about 900 to 1000 Å.