Patent ID: 8284602

Claim:
A pipe latch circuit of semiconductor memory device, comprising: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first multiplexer for selecting a certain input data from first group of the input data in response to a first selection control signal, and a second multiplexer for selecting a certain input data from second group of the input data in response to the first selection control signal, a third multiplexer for selecting a certain input data from third group of the input data in response to the first selection control signal, and a fourth multiplexer for selecting a certain input data from fourth group of the input data in response to the first selection control signal; a second multiplexing circuit comprises a fifth multiplexer for selecting an output from the first multiplexer and the second multiplexer in response to a second selection control signal and a sixth multiplexer for selecting an output from the third multiplexer and the fourth multiplexer in response to the second selection control signal; a third multiplexing circuit for setting a sequence of output data from the second multiplexing circuit in response to a third selection control signal; and a second latch circuit comprises a third latch for latching a first output data from the third multiplexing circuit in response to a first output latch control signal and a fourth latch for latching a second output data from the third multiplexing circuit in response to a second output latch control signal.