Patent ID: 8072255

Claim:
A radio frequency mixer system comprising: a four phase clock generator to generate four phased half duty cycle clocks each being out of phase by ninety degrees from each adjacent phased half duty cycle clock; a dual differential electrical load having a first differential input and a second differential input and configured to convert the differential input signals into single ended outputs; and a four phase half duty cycle mixer having a differential input port coupled to a differential input signal, an in-phase (I) differential output port coupled to the first differential input of the dual differential load, and a quadrature-phase (Q) differential output port coupled to the second differential input of the dual differential load, the mixer further having a plurality of switches with control inputs coupled to the four phase clock generator to receive each of the four phased half duty cycle clocks, the mixer to convolve the differential input signal with the four phased half duty cycle clocks to generate a differential in-phase output signal on the in-phase differential output and a differential quadrature-phase output signal on the quadrature-phase differential output, wherein the plurality of switches includes a first plurality of pairs of serially coupled switches coupled in parallel between the differential input port and the in-phase differential output port and a second plurality of pairs of serially coupled switches coupled in parallel between the differential input port and the quadrature-phase differential output port, and wherein the plurality of switches are configured to output both differential in-phase output signals to a first set of differential inputs of the dual differential load on a first and a third phase of the phased half duty cycle clocks and to output both differential quadrature-phase output signals to a second set of differential inputs of the dual differential load on a second and a fourth phase of the phased half duty cycle clocks being out of phase by ninety degrees from each adjacent phased half duty cycle clock.