Patent ID: 7495483

Claim:
An input buffer for CMOS integrated circuits, comprising: a pair of internally generated high and low reference voltages that lie within a voltage ratings of included low voltage switching devices; an input voltage limiting circuit that utilizes said reference voltages to limit an input to said low voltage switching devices at first and second outputs; and a plurality of parallel connected inverters coupled to the first and second outputs of said input voltage limiting circuit and comprising a cascade of said low voltage switching devices biased using said reference voltages to limit supply voltage stress and compensation means for reducing effects of manufacturing process variation; wherein said parallel connected inverters comprise: a first P-type FET connected to a supply voltage at its source and connected at its gate to said second output; a first resistive P-type FET connected to a drain of said first P-type FET at its source and connected at its gate to the low reference voltage; a first resistive N-type FET connected at a first common node to a drain of said first resistive P-type FET at its drain and connected at its gate to the high reference voltage; a first N-type FET connected to a ground at its source, connected at its drain to a source of the first resistive N-type FET, and connected at its gate to said first output; a second P-type FET connected to the supply voltage at its source and connected at its gate to said second output; a second resistive P-type FET connected to a drain of said second P-type FET at its source and connected at its gate to the low reference voltage; a compensation N-type FET connected to a drain of said second resistive P-type FET at its drain and connected at its gate to a second common node at the drain of said first P-type FET and the source of said first resistive P-type FET; a compensation P-type FET connected at a third common node to the source of said compensation N-type FET at its source and connected at its gate to a fourth common node at the drain of said first N-type FET and source of said first resistive N-type FET; a second resistive N-type FET connected to a drain of said compensation P-type FET at its drain and connected at its gate to the high reference voltage; a second N-type FET connected to the ground at its source and connected to the source of said second resistive N-type FET at its drain, and connected at its gate to said first output; and a connection between the first common node and the third common node for generating the output for said parallel connected inverters.