Patent ID: 7343474

Claim:
A processor comprising: a plurality of pipeline stages; and a first circuit operable at a first pipeline stage of the plurality of pipeline stages, wherein the first pipeline stage is a stage at which instructions complete, and wherein the first circuit is configured to maintain a plurality of program counters (PCs), wherein each of the plurality of PCs corresponds to one of a plurality of threads that the processor is configured to have concurrently in process with respect to the plurality of pipeline stages, and wherein the first circuit is configured to update a given PC of the plurality of PCs responsive to each instruction that completes in the corresponding one of the plurality of threads, and wherein the first circuit is configured to provide a first PC to a second pipeline stage of the plurality of pipeline stages, wherein the first PC is derived from one of the plurality of PCs that corresponds to a first thread of the plurality of threads, and wherein a first instruction entering the second pipeline stage is from the first thread.