Patent ID: 7991020

Claim:
A circuit comprising: a first current mode driver to drive output data on an output node at an output data rate; a first N-to-one multiplexer coupled to provide the output data to the first current mode driver; a second current mode driver to drive equalization data on the output node at the output data rate; a second N-to-one multiplexer coupled to provide the equalization data to the second current mode driver; a logic circuit to receive intermediate data and drive the first and second N-to-one multiplexers with the output data and equalization data, respectively, at 1/N of the output data rate, wherein the logic circuit is to generate the output data from the intermediate data with a first clock signal of N clock signals, and the logic circuit is to generate the equalization data with a second clock signal of the N clock signals; and a parallel-to-serial converter circuit to receive data at less than 1/N of the output data rate, and coupled to provide the intermediate data to the logic circuit at 1/N of the output data rate using the N clock signals, wherein N is greater than 2.