Patent ID: 7668233

Claim:
A tester comprising: a receiver that receives a signal, comprising a first data pattern, generated at a first bit rate of a first clock; and an analysis device, which samples the signal at a test bit rate of a test clock to generate a second data pattern, the test bit rate differing from the first bit rate by a selected amount; wherein the analysis device compares the first data pattern and the second data pattern to determine differences between the first data pattern and the second data pattern; and wherein the analysis device determines jitter characteristics in the signal according to the differences between the first data pattern and the second data pattern by: aligning the first data pattern and the second data pattern to maximize a number of matching bits; identifying matching regions between the first data pattern and the second data pattern; identifying non-matching regions between the first data pattern and the second data pattern; determining an average length of the non-matching regions; and comparing the average length of the non-matching regions with an expected length of the matching regions when no jitter exists.