Patent ID: 8773157

Claim:
A method of performing at least one fault mode test on at least one of a plurality of through-silicon-vias arranged on a substrate in an integrated circuit, the method comprising: a) selecting, by a controller, a through-silicon-via to be tested from the plurality of through-silicon-vias; b) selecting, by the controller, a calibration mode (“CALIBRATE”) for the selected through-silicon-via, wherein the calibration mode comprises: c) determining, by a test circuit, a calibration current measurement for the selected through-silicon-via by measuring current through a calibration current path, the calibration current path matched to the resistance of at least one switch in a path connecting the selected through-silicon-via to a measurement current path, the calibration current measurement configured to calibrate out the resistance of the switch to the selected through-silicon-via; d) selecting, by the controller, a measurement mode (“MEASURE”) for the selected through-silicon-via, wherein the measurement mode comprises: e) determining, by the test circuit, a measurement current for the selected through-silicon-via by measuring current through the measurement current path, the measurement current path comprising the switch to the selected through-silicon-via and the selected through-silicon-via; f) determining, by the test circuit, an actual measurement current using the determined calibration current measurement and the determined measurement current; and g) comparing, by the test circuit, the actual measurement current to a threshold in accordance with a screening condition for the selected through-silicon-via.