Patent ID: 8586450

Claim:
A process for fabricating a semiconductor device, comprising: producing a first wafer comprising, at a first location, a first integrated-circuit chip and a first support layer surrounding the first location and said first integrated circuit chip, the first wafer having a frontside which comprises a frontside of the first support layer and an active side of the first integrated circuit chip; producing on the frontside of the first wafer a first electrical-connection layer having a frontside and comprising, on said first location, a first electrical-connection network configured to electrically connect one side of said first electrical-connection layer to another side of said first electrical-connection layer; installing, over said first location, a second integrated-circuit chip on said frontside of the first electrical-connection layer; forming a second support layer surrounding the second integrated circuit chip so as to form a second wafer, wherein the second integrated circuit chip has an active side facing toward and in electrical contact with the first electrical-connection layer and further having one or more through electrical-connection vias; and producing on the second wafer a second electrical-connection layer having a frontside and comprising, over said first location, a second electrical-connection network configured to electrically connect one side of said second electrical-connection layer to another side of said second electrical-connection layer.