Patent ID: 7233533

Claim:
A device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit, generating a signal adjusting an operation timing of the output driver depending on CAS latency, the CAS latency control unit comprising: a read command control unit generating first and second control signals, the first control signal being activated by a read command, the second control signal being generated in synchronization with a rising edge of a DLL clock signal generated after the first control signal; a delay unit, outputting a third control signal obtained by delaying the second control signal; a count signal generation unit which outputs fourth and fifth control signals, the fourth control signal having a pulse width enabled at a rising edge of the first control signal and disabled at a rising edge of the third control signal, the fifth control signal representing a count of the rising edges of the external clock during an enable period of the fourth control signal; a control unit for outputting a plurality of control signals using the fourth and fifth control signals; and a data output control signal generation unit that receives the second control signal and which outputs a plurality of output enable signals, wherein the first and second control signals and the plurality of output enable signals have substantially equal pulse widths, and one of the control signals outputted from the control unit is selected to select one of the output enable signals; and wherein the CAS latency control unit generates a signal for controlling the output driver by using time difference between the DLL clock signal and an external clock applied to the memory device from an exterior.