Patent ID: 7571267

Claim:
An integrated circuit device, comprising: a serial-in parallel-out (SIPO) data processing circuit configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data that are out-of-phase relative to each other and further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data; a plurality of lane FIFOs configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof; and a core clock alignment circuit electrically coupled to read ports of said plurality of lane FIFOs, said core clock alignment circuit configured to perform clock phase learning operations to generate a core clock in response to detecting a plurality of training state headers received as data by corresponding ones of said plurality of lane FIFOs and further configured to provide the core clock to the read ports of said plurality of lane FIFOs, said clock phase learning operations comprising: testing a plurality of out-of-phase core clock candidates that are generated in response to a first one of the plurality of training state headers associated with a first one of the plurality of lanes of serialized data; and selecting one of the plurality of out-of-phase core clock candidates as the core clock in response to detecting an error during an operation to read data in parallel from all of said plurality of lane FIFOs using another one of the plurality of out-of-phase core clock candidates as a read clock during the operation to read data in parallel from all of said plurality of lane FIFOs.