Patent ID: 7467253

Claim:
A flash memory array comprising: a memory chip comprising a plurality of planes, each one of the plurality of planes having dedicated row and column decoder circuits, each plane having one or more blocks, each plane of the plurality of planes having a register, each plane having an incrementing circuits, and each plane having a comparing circuit; and a controller chip comprising a memory controller that is in communication with the memory chip, the memory controller requests the memory chip to erase one or more of the blocks; the register for a first plane of the planes receives a hot count from a first block of the one or more blocks for the first plane, the hot count indicating the number of times the first block has been erased; the incrementing circuit for the first plane increments the contents of the register for the first plane in response to a request from the memory controller to erase the first block; and the comparing circuit for the first plane compares the contents of the register for the first plane with a predetermined value.