Patent ID: 7294542

Claim:
A method for fabricating a semiconductor integrated circuit comprising: a first step of simultaneously forming an N − type well of a CMOS transistor comprising an inner circuit and an N − type well for collector connection to be connected with a collector of a vertical bipolar transistor on a P type silicon substrate; a second step of simultaneously forming a collector N − type well to be a collector of said vertical bipolar transistor and an N − type well of a diode on said P type silicon substrate; a third step of simultaneously forming a P − type layer to be a base in the collector N − type well of said vertical bipolar transistor and a P − type layer to be an anode in the N − type well of said diode; a fourth step of simultaneously forming an N + type layer in a P − type well of said CMOS transistor, an N + type layer in the N − type well for collector connection of said vertical bipolar transistor, an N + type layer to be an emitter in the P − type layer of said vertical bipolar transistor, and an N + type layer to be a cathode in the P − type layer of said diode; and a fifth step of simultaneously forming a P + type layer on the N − type well of said CMOS transistor, a P + type layer on the P − type layer of said vertical bipolar transistor, and a P + type layer on the P − type layer of said diode.