Patent ID: 7211842

Claim:
A semiconductor memory device comprising: a plurality of memory arrays including a plurality of memory cells which are provided at intersections of a plurality of word lines and a plurality of bit lines and formed in a first area; a plurality of sense amplifier coupled to the plurality of bit lines and formed in a second area; a plurality of address subdecoders coupled to the plurality of word lines and formed in a third area; a plurality of first voltage lines extending in a first direction; a plurality of second voltage lines extending in a second direction; a plurality of third voltage lines extending in the first direction; a plurality of fourth voltage lines extending in the second direction; a first bonding pad connected to the plurality of first voltage lines and configured for supplying first voltage to the semiconductor memory device; a second bonding pad connected to the plurality of third voltage lines and configured for supplying a second voltage smaller than the first voltage to the semiconductor memory device; and a plurality of contacts each coupled between one of the plurality of first voltage lines and one of the plurality of second voltage lines, or between one of the plurality of third voltage lines and one of the plurality of fourth voltage lines, wherein the plurality of contacts are provided above the plurality of memory arrays at the first area.