Patent ID: 8040953

Claim:
A method for generating reliability metrics for decoded bits, the method comprising: receiving a plurality of error event patterns associated with the decoded bits and a plurality of error event reliability metrics associated with the respective plurality of error event patterns, wherein each of the plurality error event patterns includes at least two bits; selecting a bit location for one of the decoded bits; determining which of the plurality of error event patterns indicates an error in the selected bit location regardless of errors in other bit locations; for each of the determined plurality of error event patterns, providing a bit-error likelihood value indicating the likelihood of an error in the selected bit location exclusively of the other bit locations based at least in part on the error event reliability metrics associated with the respective error event patterns; and determining, as a bit-error reliability metric for the selected bit location, the smallest bit-error likelihood value provided for the selected bit location from all of the bit-error likelihood values provided for the determined plurality of error event patterns.