Patent ID: 8640074

Claim:
A digital circuit block having reducing supply voltage drop, comprising: a first conducting path having a first end coupled to a first supply voltage; a second conducting path having a first end coupled to a second supply voltage; a digital logic coupled between a second end of the first conducting path and a second end of the second conducting path; a first conducting layer; a second conducting layer; a third conducting layer being under the first conducting layer; a fourth conducting layer being between the third conducting layer and the second conducting layer; a dielectric layer being between the third conducting layer and the fourth conducting layer; a first conducting segment, having a first end electrically connected to the first conducting path, a second end not electrically connected to the second conducting path, a first portion of the first conducting segment located at the first conducting layer, and a third portion of the first conducting segment located at the third conducting layer; and a second conducting segment, having a first end electrically connected to the second conducting path, a second end not electrically connected to the first conducting path, a second portion of the second conducting segment located at the second conducting layer, and a fourth portion of the second conducting segment located at the fourth conducting layer; wherein the first portion of the first conducting segment and the second portion of the second conducting segment form a first capacitive element and the third portion of the first conducting segment, the fourth portion of the second conducting segment and the dielectric layer form a second capacitive element to reduce the supply voltage drop between the first supply voltage and the second supply voltage.