Patent ID: 7293161

Claim:
A method for deferring a store and generating a prefetch when a store buffer in a processor becomes full during program execution in an execute-ahead mode, comprising: issuing instructions for execution in program order during a normal execution mode; upon encountering an unresolved data dependency during execution of an instruction, generating a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and executing the instruction and subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; upon encountering a store during the execute-ahead mode, determining if the store buffer is full, if the store buffer is full, prefetching a cache line for the store, and deferring execution of the store, and if the store buffer is not full, executing the store; and upon encountering a non-data-dependent stall condition in normal execution mode, generating a checkpoint that can subsequently be used to return execution of the program to the point of the non-data-dependent stall condition; entering a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and when the non-data-dependent stall condition that caused the processor to move out of normal execution mode is finally resolved, using the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.