Patent ID: 7990994

Claim:
A method comprising: programmatically determining a plurality of host bus adapter channels required to meet a list of storage interface requirements, including computing how many host bus adapter channels are needed and associated bandwidths; programmatically computing a respective plurality of operational parameters for each of the host bus adapter channels; programmatically identifying a plurality of storage interfaces to implement the determined number of host bus adapter channels; programmatically computing mode information to configure the storage interfaces according to the respective pluralities of operational parameters; configuring and operating the storage interfaces in accordance with the respective pluralities of operational parameters; and wherein the storage interfaces are accessible by a plurality of processes executing on a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition comprising links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache memory coherency transactions.