Patent ID: 7495982

Claim:
An internal voltage generation device, comprising: a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal; a first control unit for controlling the first voltage drop unit; and a second control unit for controlling the second voltage drop unit; and wherein the second voltage drop amount is greater than the first voltage drop amount, wherein the first and second control units include a plurality of fuse cutting circuits for fixing output signals of the first and second control units by performing a fuse cutting operation, wherein the test mode signal is outputted from a test mode unit included for selecting a voltage drop amount according to a leakage current, and wherein the first control unit includes: a first NAND gate for receiving a first test mode signal and a first fuse cut signal of the fuse cutting circuit; a first inverter for inverting an output of the first NAND gate; a second NAND gate for receiving a second test mode signal and a second fuse cut signal; a second inverter for inverting an output of the second NAND gate; a third NAND gate for receiving each output of the first and second inverters; and a third inverter for inverting an output of the third NAND gate.