Patent ID: 7750834

Claim:
A pipelined analog-to-digital converter including a plurality of converter stages interconnected in cascade, each of said converter stages comprising: an analog-to-digital converter section for comparing an input voltage to a first reference voltage to output a first signal indicating a result of comparison, and for comparing the input voltage to a second reference voltage lower than the first voltage to output a second signal indicating the result of comparison; a digital-to-analog converter section operative in response to a combination of the first and second signals for outputting either one of a third reference voltage, a fourth reference voltage higher than the third reference voltage and a fifth reference voltage lower than the third reference voltage; an amplifier for amplifying a difference voltage between the input voltage and the one voltage output from said digital-to-analog converter section to output a resulting signal to a downstream side of said amplifier, a digital signal relevant to an analog voltage delivered to an initial converter stage of said converter stages being output in response to the first and second signals output from said analog-to-digital converter section of each of said converter stages; and an encoder for outputting, when logical incongruence resides in the combination of the first and second signals output from said analog-to-digital converter section, a signal corresponding to the combination of the first and second signals with logical congruence in the combination to cause said digital-to-analog converter to produce either one of the third reference voltage, the fourth reference voltage and the fifth reference voltage.