Patent ID: 7721172

Claim:
A method for automatically generating a virtual scan pattern at broadcast scan inputs of a broadcaster to test a scan-based integrated circuit connected to the broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, the broadcaster comprising a combinational logic network including at least one multiplexer, said at least one multiplexer being directly connected to said broadcast scan inputs, the broadcast scan inputs receiving said virtual scan pattern from an automatic test equipment (ATE) and generating a broadcast scan pattern for driving the scan inputs of said multiple scan chains embedded in the scan-based integrated circuit, said method comprising: a) directly incorporating any input constraints imposed by said combinational logic network into an automatic test pattern generation (ATPG) program for generating said virtual scan pattern for one or more selected faults in one-step; and b) providing said virtual scan pattern to said combinational logic network for driving the scan inputs of said scan-based integrated circuit.