Patent ID: 7799621

Claim:
A method of manufacturing a thin film transistor array substrate, the method comprising the steps of: forming a pattern made of a first conductive film on a substrate; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order on the first conductive film; forming a resist pattern having a step structure in a thickness direction by using a photolithography process with a photomask disposed on the resist; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of an interlayer insulating film and a pattern made of a third conductive film on the second conductive film, wherein: the thin film transistor array substrate has a conductive film connecting region in which the first conductive film and the second conductive film are in direct contact with each other through an opening formed in the gate insulating film, and in which the second conductive film is coated with an upper-layer film; the first conductive film forms a gate electrode of a thin film transistor, and forms a gate line connected to the gate electrode; the second conductive film forms each of a source electrode and a drain electrode of the thin film transistor, and forms a source line connected to the source electrode; and the third conductive film forms a pixel electrode.