Patent ID: 7200743

Claim:
An electronic device, comprising: a memory comprising at least a first memory element and a second memory element; a first plurality of initialization value sets available to be loaded into said first memory element; a second plurality of initialization value sets available to be loaded into said second memory element; a mode value that indicates a mode from among a plurality of modes of said electronic device; and a first initialization logic circuit and a second initialization logic circuit corresponding to said first memory element and said second memory element, said first and second initialization logic circuits receiving said mode value and adapted to receive a reload signal; wherein upon occurrence of said reload signal, said first initialization logic circuit selects a first predetermined initialization value set from among said first plurality of initialization value sets according to said mode value and initializes said first memory element with said first predetermined initialization value set and substantially simultaneously said second initialization logic circuit selects a second predetermined initialization value set from among said second plurality of initialization value sets according to said mode value and initializes said second memory element with said second predetermined initialization value set.