Patent ID: 7268580

Claim:
A configuration circuit to configure programmable logic in a three-dimensional semiconductor device, comprising: a plurality of memory elements, each memory element having either one or two outputs, each memory element capable of storing one of two binary data values; and a memory programming method to access each of said memory elements to alter the stored data value between said two binary data values; and a plurality of configurable control signals, either one or two control signals generated by said one or two outputs of each of the memory elements respectively, each control signal having either the same polarity of the stored memory bit or the opposite polarity of the stored memory bit, each control signal further terminating at one or more regulatory nodes of a programmable logic circuit to configure said logic circuit; wherein, the programmable logic circuit is located in a first module layer and the configuration circuit is located in a second module layer positioned substantially above the first module layer of the semiconductor device.