Patent ID: 7562206

Claim:
A computer implemented method comprising: decoding a first plurality of macro-instructions having a sequential instruction ordering into a plurality of micro-operations representing the sequential instruction ordering; dynamically predicting execution of a first set of micro-operations of the plurality of micro-operations to involve execution resources to perform memory access operations and inter-cluster communication; dynamically predicting execution of a second set of micro-operations of the plurality of micro-operations to involve execution resources to perform control branching operations and/or to depend upon an inter-cluster communication from one of said first set of micro-operations; switching a micro-operation from said first set to said second set when the micro-operation is statically predicted to perform a control branching operation and alternatively switching the micro-operation from said second set to said first set when the micro-operation is statically predicted to perform a memory access operation; and partitioning the plurality of micro-operations for execution in accordance with said predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources.