Patent ID: 8461038

Claim:
A process of forming an integrated circuit, comprising the steps of: forming a dielectric layer over a substrate; defining areas for a first plurality of parallel route tracks and second plurality of parallel route tracks on a top surface of said dielectric layer, so that instances of said second plurality of parallel route tracks alternate with instances of said first plurality of parallel route tracks; forming a first interconnect pattern creating a plurality of first exposed areas in said first plurality of parallel route tracks, said plurality of first exposed areas including a first lead pattern and a crossover pattern which extends from said first lead pattern, such that an exclusion zone is defined in an instance of said first plurality of parallel route tracks immediately adjacent to said crossover pattern opposite said first lead pattern and extends for a lateral distance of two to three times a width of said crossover pattern in a direction parallel to said first plurality of parallel route tracks, said exclusion zone being free of instances of said first plurality of exposed areas; performing a first trench etch process to form a first plurality of trenches in said plurality of first exposed areas, including a first lead trench in said first lead pattern, and a crossover trench in said crossover pattern; forming a second interconnect pattern creating a plurality of second exposed areas in said second plurality of parallel route tracks, said second plurality of exposed areas including a second lead pattern which extends to said crossover trench; wherein said first interconnect pattern and said second interconnect pattern are formed using two distinct photolithography processes; performing a second trench etch process to form a second plurality of trenches in said second plurality of exposed areas, including a second lead trench in said second lead pattern, so that said first lead trench, said crossover trench and said second lead trench form a continuous trench; and forming metal interconnect lines in said first plurality of trenches, said crossover trench and said second plurality of trenches.