Patent ID: 7130221

Claim:
A method for altering and reading the contents of a memory cell, said memory cell including in a substrate, a drain, a source and a channel therebetween, first and second charge trapping regions overlying the channel and first and second control gates proximate to respectively, the first and the second charge trapping regions, said cell being configured for independently storing a first bit, said first bit being represented by a presence or an absence of charges trapped in the first charge trapping region and a second bit, said second bit being represented by a presence or an absence of charges trapped in the second charge trapping region, the method comprising the steps of: applying programming voltages to the first control gate and to the second control gate to cause carriers to be injected and trapped in either the first charge trapping region or in the second charge trapping region, the trapped carriers representing a programmed state of a respective first bit or second bit; applying erasing voltages to the first control gate and to the second control gate to cause the trapped carriers to be removed from the first charge trapping region and/or the second charge trapping region, an absence of the trapped carriers from the first charge tapping region and/or the second trapping region representing an erased state of a respective first bit or second bit; and applying a sequence of reading voltages to the first control gate and to the second control gate for determining the state of the first bit and the state of the second bit.