Patent ID: 6915323

Claim:
A programmable logic device including a plurality of logic blocks, each logic block, comprising: a plurality of product term circuits each operable to provide a product term output; a plurality of M OR gates, wherein each OR gate is configured to receive a subset of the product term outputs and provide a sum of products output; a plurality of M macrocells corresponding to the plurality of M OR gates, wherein each macrocell is configurable to register the sum of products output from its corresponding OR gate; and a plurality of M multiplexers corresponding to the plurality of M OR gates and the plurality of M macrocells, wherein each multiplexer is configured to select between a product term output and a carry-in signal to provide a carry-out signal, and wherein the multiplexers are arranged from a first multiplexer to an Mth multiplexer to form a carry cascade such that the carry-out signal from the first multiplexer becomes the carry-in signal for the second multiplexer, the carry-out signal from the second multiplexer becomes the carry-in signal for the third multiplexer, and so on.