Patent ID: 7680872

Claim:
An apparatus comprising: an address generation circuit configured to generate a series of addresses; a lookup table configured to generate one or more coefficients in response to said addresses, each one of said coefficients having a plurality of bits; a multiplexer circuit configured to generate one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits; and an output circuit configured to (i) generate one or more component values by rounding said shifted values, (ii) negate selective ones of said component values and (iii) generate an output signal by combining said component values after said negating, wherein (a) said component values are grouped as one over power of 2 components into mutually exclusive groups, (b) each one of said groups corresponds to a respective one of said bits and (c) said output signal is suitable for use in a digital filter.