Patent ID: 7185297

Claim:
A method of diagnosing a circuit layout using a computer system, comprising the steps of: generating at least one first file, the first file containing data for a circuit layout, including data for pin pads, test pads, and nets which connect the pin pads and the test pads, wherein the test pads have a plurality of power test pads, and the power test pads are divided into several groups, each group having a different group name and input voltage; generating a second file, the second file establishing a layout arranging rule; defining a safety value for each group of the power test pads according to the layout arranging rule; and comparing the first file and the second file to determine whether the circuit layout of the first file violates the layout arranging rule of the second file, wherein the comparing step comprises: searching the first file and counting the total number of power test pads in each group; calculating the difference value between the total number of power test pads and the safety value for each group, wherein, if the difference value is greater than or equal to zero, the difference value is reset to zero; and generating a report which demonstrates the results of the comparing, searching and calculating steps.