Patent ID: 8125585

Claim:
A thin film transistor array substrate, comprising: a gate line provided on a substrate; a data line crossing the gate line to define a pixel area; a gate insulating film between the gate line and the data line at the crossing of the gate line and data line; a thin film transistor adjacent to the crossing of the gate line and the data line; a protective film covering the thin film transistor; a pixel electrode provided on the pixel area and electrically connected to a drain electrode of the thin film transistor; a gate pad connected to the gate line; a data pad connected to the data line; a lower data link electrode connected to the data line; an upper data link electrode connected to the data line and overlapping one end of the lower data link electrode; and a link electrode connecting the lower data link electrode via a first contact hole passing through the protective film and the gate insulating film at a first area of the substrate in which the protective film is directly provided on the gate insulating film, wherein the lower surface of the link electrode is connected on the upper surface of the lower data link electrode, wherein the gate insulating film and a semiconductor layer formed between the upper data link electrode and the lower data link electrode, wherein the first contact hole is formed at an end of the upper data link electrode adjacent to the data pad.