Patent ID: 7373567

Claim:
A method of providing error correction in an integrated circuit (IC) to enable the replacement of a defective logic function implemented within the IC, the method comprising: providing an embedded field programmable gate array (FPGA) in the IC to perform logic error correction; providing registers and associated circuitry designed to manipulate a scanned data stream; identifying a defective logic function within the IC; programming the embedded FPGA to replace the defective logic function; identifying all inputs in an input cone of logic of the defective logic function; directing all inputs in the input cone of logic of the defective logic function into the embedded FPGA, such that the embedded FPGA replaces the defective logic function with an error corrected version of the defective logic function, wherein said directing of all inputs in the input cone of logic of the defective logic function into the embedded FPGA includes: placing a logic macro implemented in the IC into a wait state; and scanning data from the defective logic function into the FPGA and the registers and associated circuitry to implement error correction of the defective logic function; and, identifying all outputs in an output cone of logic of the defective logic function; directing an output of the FPGA to the output cone of logic of the defective logic function, such that logic error correction is provided within the embedded FPGA structure of the IC, wherein a scan chain defines a data path through the IC, and a feedback loop is formed to direct corrected data of the scan chain to a register boundary of the defective logic function, whereupon the logic macro discontinues the wait state and resumes normal processing.