Patent ID: 7826241

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells that can be accessed by inputting an input address; a pre-decoder that pre-decodes the input address to generate a first pre-decoded address; a CAM circuit that activates a match signal in response to the input address indicating a defective memory cell; a ROM circuit that outputs a second pre-decoded address and an enable signal in response to an activation of the match signal; and a multiplexer for selecting either the first pre-decoded address or the second pre-decoded address based on the enable signal; wherein the CAM circuit includes a match line for outputting the match signal, a plurality of CAM cells each corresponding to an associated one bit of the input address, and a pre-charging circuit for pre-charging the match line, and the plurality of CAM cells includes a nonvolatile memory element and a discharge circuit that discharges the match line in response to a logical value stored in the nonvolatile element and a logical value of a corresponding bit of the input address being different.