Patent ID: 7450461

Claim:
A one-chip semiconductor memory device transmitting/receiving a data signal, an address signal and a control signal to/from a plurality of information processing devices, the device comprising a plurality of memory arrays each having an array of a plurality of nonvolatile memory cells in the chip; a plurality of sets of data terminals, address terminals and control terminals and data-related circuits, address-related circuits and control-related circuits provided individually for the plurality of memory arrays; one set of a data terminal, address terminal and control terminal placed in an input/output buffer portion at a chip external interface, the one set being shared among the plurality of memory arrays; and a plurality of signal selection circuits placed between the one set of a data terminal, address terminal and control terminal and the plurality of sets of data terminals, address terminals and control terminals and data-related circuits, address-related circuits and control-related circuits, wherein one or a plurality of array selection signals for selecting any of the plurality of memory arrays are input into the plurality of signal selection circuits via the input/output buffer portion, and signals from the one set of a data terminal, address terminal and control terminal are distributed to any of the plurality of memory arrays via the plurality of signal distribution circuits.