Patent ID: 7136388

Claim:
A clock synchronization system for use in an access network element having a primary bank and a plurality of secondary banks interlinked via an interbank communication link, comprising: a central master timing and frame alignment control block disposed in said primary bank, said central master timing and frame alignment control block operating based on a master reference clock to determine a delay preset with respect to a slave timing and frame alignment control block disposed in a first level secondary bank coupled to said primary bank; a local counter coupled to said slave timing and frame alignment control block disposed in said first level secondary bank, wherein said local counter is operable to generate an adjusted local clock based on said delay preset received from said central master timing and frame alignment control block; and a local master timing and frame alignment control block disposed in said first level secondary bank, said local master timing and frame alignment control block operating responsive to said adjusted local clock to determine a delay preset with respect to a slave timing and frame alignment control block disposed in an adjacent secondary bank immediately below said first level secondary bank, wherein a local counter coupled to said slave timing and frame alignment control block disposed in said adjacent secondary bank is operable to generate an adjusted local clock based on said delay preset received from said first level secondary bank.