Patent ID: 7372741

Claim:
A nonvolatile memory apparatus comprising: a bus; a processing unit coupled to said bus; and a plurality of nonvolatile memories coupled to said bus, wherein each of said nonvolatile memories includes a plurality of memory cells, an erase control circuit, which controls performing an erase operation and a verify operation for erasing data stored into ones of said memory cells, and an address generation circuit, which generates an address indicating a part of said ones of said memory cells, wherein in an erase operation mode, said erase control circuit repeatedly performs said erase operation and said verify operation until ones of memory cells are erased, said erase control circuit performs said verify operation to said part of said ones of memory cells addressed by said address generated by said address generation circuit in said verify operation, and performs said erase operation again when at least one memory cell in said part of ones of memory cells has not become erased, and wherein when said processing unit specifies one of said nonvolatile memories to said erase operation mode, said processing unit issues a signal for specifying said erase operation mode to said one of said nonvolatile memories while activating a chip enable signal of said one of said nonvolatile memories, and said processing unit is capable of inactivating said chip enable signal after fetching said signal for specifying said erase operation mode by said one of said nonvolatile memories and before completion of said erase operation mode of said one of said nonvolatile memories.