Patent ID: 8136084

Claim:
A method comprising: identifying, using at least one computer device, linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs, the plurality of TSVs being linearly aligned with one another, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and the identifying including: defining a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges, calculating a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and expanding each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and modifying, using the at least one computer device, at least the portion of the IC layout to reduce a number of the linearly aligned TSVs, the modifying including, in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotating the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.