Patent ID: 7111185

Claim:
A system comprising: a processor; and a memory device coupled to the processor and comprising a synchronization device having a first path and a second path, wherein the synchronization device comprises: a delay model circuit arranged at the beginning of the first path and configured to model input and output delays in the synchronization device; a first delay line coupled to the delay model circuit and comprising a plurality of delay elements, and wherein the delay line is configured to receive a first signal and add an amount of delay to the first signal to produce a second signal having a different phase than the first signal; a delay line control circuit coupled to the first delay line and configured to control the amount of delay added to the first signal by the first delay line; a first tuning element arranged in the first path and configured to receive a third signal from the delay model; and a second tuning element configured to produce the same response as that of the first tuning element and arranged in the second path.