Patent ID: 7130226

Claim:
A clock generating circuit comprising: a voltage controlled delay circuit having a delay input coupled to receive a delay input signal and a control input coupled to receive a delay control signal, the voltage controlled delay circuit being operable to generate a delayed clock signal by inverting the delay input signal and delaying the delay input signal by a delay that is determined by the delay control signal; a phase comparison circuit coupled to the voltage controlled delay circuit and configured to receive the delayed clock signal and a reference clock signal, the phase comparison being operable to generate the delay control signal as a function of the relative phases of the delayed clock and reference clock signals; a mode control circuit operable to generate a mode control signal; and a selection circuit coupled to the voltage controlled delay circuit, the selection circuit having first and second inputs coupled to receive the delayed clock signal and the reference clock signal respectively, the selection circuit having an output coupled to the input of the voltage controlled delay circuit, the selection circuit being operable to couple either the delayed clock signal or the reference clock signal to the input of the voltage controlled delay circuit responsive to the mode control signal, the clock circuit functioning as a phase-lock loop when the selection circuit is coupling the delayed clock signal to the input of the voltage controlled delay circuit and functioning as a delay-lock loop when the selection circuit is coupling the reference clock signal to the input of the voltage controlled delay circuit.