Patent ID: 7755392

Claim:
A level shift circuit, comprising: a first PMOS transistor having a gate, a source electrically connected to a high voltage terminal, and a drain; a second PMOS transistor having a gate electrically connected to a drain of the first PMOS transistor, a source electrically connected to the high voltage terminal, and a drain electrically connected to the gate of the first PMOS transistor; a third PMOS transistor having a gate electrically connected to a reference voltage terminal, a source electrically connected to the drain of the first PMOS transistor, and a drain; a fourth PMOS transistor having a gate electrically connected to the reference voltage terminal, a source electrically connected to the drain of the second PMOS transistor, and a drain; a first NMOS transistor having a gate electrically connected to a voltage source, a source, and a drain electrically connected to the drain of the third PMOS transistor; a second NMOS transistor having a gate electrically connected to the voltage source, a source, and a drain electrically connected to the drain of the fourth PMOS transistor; a third NMOS transistor having a gate electrically connected to an input terminal, a source electrically connected to a ground, and a drain electrically connected to the source of the first NMOS transistor; a fifth NMOS transistor having a gate electrically connected to the voltage source, a source, and a drain electrically connected to the source of the third PMOS transistor; a sixth NMOS transistor having a gate electrically connected to a control terminal, a source electrically connected to the source of the first NMOS transistor, and a drain electrically connected to the source of the fifth NMOS transistor; a seventh NMOS transistor having a gate electrically connected to the voltage source, a source, and a drain electrically connected to the source of the fourth PMOS transistor; and a eighth NMOS transistor having a gate electrically connected to the control terminal, a source electrically connected to the source of the second NMOS transistor, and a drain electrically connected to the source of the seventh NMOS transistor.