Patent ID: 8473673

Claim:
A system, comprising: a memory controller configured: to receive an uncompressed data block to be stored in memory; to compress in hardware the uncompressed data block into a compressed data block; to compute a size of the compressed data block; and to selectively manipulate a burst-mode protocol employed in communicating data with a random access memory (RAM), where manipulating the burst-mode protocol includes computing a burst size based on the size of the compressed data block, computing a number of bursts based on the size of the compressed data block, and computing an alignment in the RAM based on the size of the uncompressed data block; and a RAM controller operably connected to the memory controller by a bus and to the RAM by a memory interface, the RAM controller being configured: to receive the compressed data block and the size of the compressed data block from the memory controller; to write the compressed data block to the RAM via the memory interface using the burst-mode protocol, where the number of bursts required to write the compressed data block to the RAM is controllable by the RAM controller and is based, at least in part, on the size of the compressed data block, and where the compressed data block is written as one or more sub-blocks of data that are aligned on a default burst mode RAM line boundary based, at least in part, on the size of the uncompressed data block; and to store the size of the compressed data block so that it may be acquired upon a read access targeted at the compressed data block written to the RAM.