Patent ID: 6894942

Claim:
A refresh control circuit for a semiconductor memory device, the circuit comprising: a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying a first delay time and a second delay time in response to a sense amplifier enable signal and a refresh command signal, wherein the second delay time is a sum of the first delay time and a third delay time having a positive value; and a sense amplifier driver configured to output a sense amplifier driving voltage by applying the first delay time in a normal operation and the second delay time in a refresh operation, wherein the sense amplifier control circuit comprises: a refresh command signal generating unit configured to output a first refresh command signal for selectively applying the first delay time and the second delay time in response to the sense amplifier enable signal and the refresh command signal; a first sense amplifier driving signal generating unit configured to generate a first sense amplifier driving signal by logically combining the sense amplifier enable signal and the first refresh command signal; a second sense amplifier driving signal generating unit for delaying the first refresh command signal for a predetermined time and generating a second sense amplifier driving signal; and a third sense amplifier driving signal generating unit configured to generate a third sense amplifier driving signal by logically combining the first refresh command and the sense amplifier enable signal.