Patent ID: 7829466

Claim:
A method for fabricating semiconductor structures of a first width W 1 and semiconductor structures of a smaller second width W 2 , the method comprising the steps of: fabricating a first plurality of mandrels on a hard mask layer overlying a structure-forming material layer; fabricating a second plurality of mandrels on the hard mask layer; forming a first sidewall spacer-forming material overlying the first plurality of mandrels leaving the second plurality of mandrels exposed, wherein the first sidewall spacer-forming material is deposited to a thickness about equal to a difference between the first width W 1 and the second width W 2 ; forming a second sidewall spacer-forming material overlying the first sidewall spacer-forming material and the second plurality of mandrels, wherein the second sidewall spacer-forming material is deposited to a thickness about equal to the first width W 1 ; anisotropically etching the first sidewall spacer-forming material and the second sidewall spacer-forming material to form first sidewall spacers about sidewalls of each of the first plurality of mandrels and second sidewall spacers about sidewalls of each of the second plurality of mandrels, the first sidewall spacers having a base width of about equal to the first width W 1 and the second sidewall spacers having a base width of about equal to the second width W 2 ; removing the first plurality of mandrels and the second plurality of mandrels; etching the hard mask layer using the first sidewall spacers and the second sidewall spacers as an etch mask; and etching the structure-forming material layer using the etched hard mask layer as an etch mask.