Patent ID: 8359425

Claim:
A memory control device comprising: a controller configured to control a command for data access from a host to a nonvolatile memory; a command queue module configured to queue a transfer request command corresponding to the command for data access; a plurality of stage processors each configured to perform stage processing related to the transfer request command queued by the command queue module; and a skip module provided to at least one of the plurality of stage processors which performs data access process to the non-volatile memory, the skip module being configured to assign, upon receipt of a shutdown command issued by the controller, a skip flag to the transfer request command to skip the stage processing related to the transfer request command and output the transfer request command to a stage processor at a latter stage after the stage processing at the stage processor to which the skip module is provided is completed and before the transfer request command is output to the stage processor at the latter stage, the skip module being configured to output, upon receipt of the transfer request command to which the skip flag is assigned from a stage processor at an earlier stage, the received transfer request to the stage processor at the latter stage.