Patent ID: 7606086

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array in which a plurality of two-terminal structured memory cells each having a variable resistive element arranged to store information according to an electric resistance change are arranged in a row and column direction, a plurality of word lines extending in the row direction and a plurality of bit lines extending in the column direction are provided, the memory cells on a same row are connected at one end to a same word line, and the memory cells on a same column are connected at the other end to a same bit line; a first voltage supply circuit arranged to supply a first voltage to a selected bit line connected to a selected memory cell to be read; a second voltage supply circuit arranged to supply a second voltage to the word lines and unselected bit lines except the selected bit line; a current read circuit arranged to read a current flowing in the selected memory cell from a side of a selected word line connected to the selected memory cell based on a voltage difference applied to the selected memory cell; a voltage suppressor circuit arranged to suppress fluctuation of the second voltage with respect to each word line and bit line provided in the second voltage supply circuit; and a voltage control circuit arranged to apply a predetermined voltage to the selected bit line and a dummy second voltage to the unselected bit lines and the word lines, detect fluctuation of a voltage of the selected bit line depending on a data pattern stored in the memory cell array during a preset period prior to a reading period to detect the current flowing in the selected memory cell, and control the voltage suppressor circuit during the reading period so that the second voltage applied to the unselected bit lines and the word lines may fluctuate in a direction of the fluctuation which is detected.