Patent ID: 8252649

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a gate dielectric material over a workpiece, the workpiece comprising a first region, a second region, a third region, a fourth region, a fifth region, and a sixth region; forming a cap layer over the gate dielectric material; removing the cap layer from over the gate dielectric material in the first region, the fifth region, and the sixth region; forming a metal gate material over the cap layer; removing a first portion of the metal gate material in the second region and the fifth region; removing a second portion of the metal gate material in the third region and the sixth region, the second portion being larger than the first portion; forming a semiconductive gate material over the metal gate material; and patterning the semiconductive gate material, the metal gate material, the cap layer, and the gate dielectric material, forming a first transistor in the first region, a second transistor in the second region, a third transistor in the third region, a fourth transistor in the fourth region, a fifth transistor in the fifth region, and a sixth transistor in the sixth region, wherein threshold voltages for the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor are different.