Patent ID: 7363427

Claim:
A memory control apparatus in a computing system comprising: a memory controller and a buffer; said memory controller and buffer being connected by a bidirectional data bus and a control interface; said buffer being connected to a random-access memory bus for read and write operations; said buffer comprising data storage areas to buffer data between the memory controller and system memory, said buffer further comprising logical circuits to decode memory interface control commands from said memory controller; a data access and control bus connected between the buffer and the system memory to control read and write operations from and to system memory; a second buffer serving as a tag buffer, said second buffer being connected to said random-access memory bus for read and write operations; said second buffer comprising data storage areas to buffer data between the memory controller and system memory, said buffer further comprising logical circuits to decode memory interface control commands from said memory controller; and a data access and control bus connected between the tag buffer and the system memory to control read and write operations from and to system memory; and a tag control input signal designating said second buffer as the tag buffer.