Patent ID: 7613882

Claim:
A method, comprising: receiving, at a distributed memory logic circuit, a request to modify a memory block stored on a computer node that includes the distributed memory logic circuit and one or more CPUs, wherein the request is marked for fast invalidation and comes from one of the CPUs; sending probes to a distributed memory logic circuit on one or more other nodes in a computer network, if the memory block is cached on the other nodes, wherein the probes are also marked for fast invalidation, responding to the request and allowing the modification to proceed without waiting for responses from the probes; delaying for a pre-determined time period after responding to the request and then incrementing the value of a first counter; waiting until responses have been received for all of the probes and then incrementing the value of a second counter; associating data received from the CPUs with a tag including a current value of the first counter; and preventing data from leaving the node based on the value of the associated tag relative to the value of the second counter.