Patent ID: 7682757

Claim:
A pattern layout for forming an integrated circuit, the pattern layout comprising: a first device pattern including a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction; a second device pattern disposed on the fixed pitch and separated from the first device pattern in the first direction, the second device pattern including a line and a space each having a pattern width an odd-number times larger than the regular intervals of the fixed pitch, the odd-number being set to be three or more; and an auxiliary pattern disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure, the auxiliary pattern being a periodic pattern including a plurality of patterns, the plurality of patterns being formed on the line and the space of the second device pattern, the auxiliary pattern including an auxiliary space pattern and an auxiliary line pattern, the auxiliary space pattern and the auxiliary line pattern being arranged with the fixed pitch, the auxiliary pattern being arranged in parallel with the first and second device patterns.