Patent ID: 8314453

Claim:
An SRAM memory cell with four transistors provided with a counter-electrode comprising: a first area made from a semiconductor material wherein a first transfer transistor and a first driver transistor are connected in series by a first common terminal defining a first electric node, a second area made from the semiconductor material wherein a second transfer transistor and a second driver transistor are connected in series by a second common terminal defining a second electric node, the first transfer transistor and the second driver transistor are on a first side of a plane passing via the first and second electric nodes and the first driver transistor and second transfer transistor are on an other side of said plane, a support substrate separated from the first and the second areas by an insulating layer, first and second counter-electrodes formed in the support substrate, the first counter-electrode overlapping the first area and the second counter-electrode overlapping the second area, a first connection between the first counter-electrode and a gate of the first driver electrode, a second connection between the second counter-electrode and a gate of the second driver electrode, the second connection and the first connection being located on either side of an axis passing through the first and the second electric nodes.