Patent ID: 8612942

Claim:
A debugging system for debugging a program executed in a processor system equipped with a main memory, a processor equipped with a cache memory having a memory cell unit, and a bus to connect the processor and the main memory, the memory cell unit being capable of storing first tag addresses and data in association with first index addresses, respectively, the first index addresses being configured based on address information, the first tag addresses being configured based on the address information, the debugging system comprising: an inputting unit to receive designation address information to designate an address of data to be read, the inputting unit receiving an instruction to instruct an operation for debugging; a cache memory configuration information inputting unit to receive configuration information of the cache memory; an address converter to convert the designation address information to a second index address and a second tag address on the basis of the configuration information received by the memory configuration information inputting unit; a cache memory reading unit equipped with a first decoder, a comparator and a reader, the first decoder being configured to access to the memory cell unit in reference to the second index address obtained from the address converter, the comparator being configured to compare the second tag address with one of the first tag addresses stored in the memory cell unit and selected by the first decoder, the reader configured to read one of the data corresponding to the one of the first tag addresses stored in the memory cell unit and selected by the first decoder; and a cache memory display unit configured to display at least the designation address information and the one of the data read from the cache memory, wherein the cache memory reading unit is configured to read one of the data corresponding to the one of the first tag addresses stored in the memory cell unit and selected by the first decoder, when the one of the first tag addresses stored in the memory cell unit and the second tag address match as a result of comparison by the comparator so that the access to the cache memory results in a cache hit.