Patent ID: 7667274

Claim:
A semiconductor device, comprising: a silicon semiconductor substrate; a complementary type MISFET circuit including an n-channel MISFET and a p-channel MISFET, which are formed on a surface region of the silicon semiconductor substrate; an insulation film formed on the surface region of the silicon semiconductor substrate in which the complementary type MISFET circuit is formed; a first contact hole formed in the insulation film, an n-channel impurity diffused region formed at a bottom of the first contact hole; a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region with a first metal; a second contact hole formed in the insulation film, a p-channel impurity diffused region formed at a bottom of the second contact hole; a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region with a second metal; and a work function of the second metal silicide layer being higher than that of the first metal silicide layer, wherein a first contact layer embedded in the first contact hole comprises the first metal silicide layer formed on the bottom of the first contact hole, a barrier layer formed on a sidewall of the first contact hole, and a metal film formed in the first contact hole to be surrounded by a combination of the first metal silicide layer and the barrier layer.