Patent ID: 8872336

Claim:
A conductive structure for a semiconductor chip, the semiconductor chip comprising a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer, wherein the pad is disposed on the semiconductor substrate, the passivation layer is disposed on the semiconductor substrate and partially covers the pad to expose the pad through a first opening that is formed by the passivation layer, wherein the patterned insulating layer is disposed on the passivation layer and partially covers the first opening of the pad to expose the pad through a second opening that is defined by the patterned insulating layer, and the first opening is larger than the second opening, the conductive structure comprising: an under bump metal (UBM) layer, being formed in the second opening defined by the patterned insulating layer and electrically connected to the pad, wherein a first upper surface of the under bump metal layer is flush with a second upper surface of the patterned insulating layer; and a conductive bump, being formed on the under bump metal layer and electrically connected to the under bump metal layer, wherein a third upper surface of the conductive bump is higher than the second upper surface of the patterned insulating layer, and the portion of the conductive bump disposed in the second opening is covered by the under bump metal layer.