Patent ID: 8878299

Claim:
A semiconductor memory device, comprising: a first memory cell formed with a first fin shaped active region, the first memory cell including a first transistor comprising a first channel, two first source/drains and a first gate disposed at the first channel; a second memory cell formed with a second fin shaped active region, the second memory cell including a second transistor comprising a second channel, two second source/drains and a second gate disposed at the second channel; a third memory cell formed with a third fin shaped active region, the third memory cell including a third transistor comprising a third channel, two third source/drains and a third gate disposed at the third channel; a gate line disposed over the first, second and third channels extending in a first direction, the first gate, the second gate and the third gate being portions of the gate line; wherein, each of the first, second and third fin shaped active regions extend in a second direction, and each are formed of a semiconductor material and comprise: a top surface, a first sidewall extending towards the top surface, a second sidewall opposite the first sidewall extending towards the top surface, a recess being formed in the top surface of the fin shaped active region extending through the fin shaped active region in the first direction, wherein the fin shaped active region has a larger thickness at a first location below the recess than a thickness of the fin shaped active region at a second location having the same height as the first location, wherein the second transistor is located between the first transistor and the third transistor, and wherein the first fin shaped active region and second fin shaped active region are spaced a first distance apart, and the second fin shaped active region and the third fin shaped active region are spaced a second distance apart, wherein the second distance is larger than the first distance.