Patent ID: 7094688

Claim:
A method for manufacturing a semiconductor device including steps of forming a wiring by a dual damascene method, the method for manufacturing the semiconductor device comprising the steps of: forming a cap film, a first interlayer insulating film, an etching stopper film, a second interlayer insulating film, and a hard mask in this order on a conductive layer; forming a via hole which reaches the cap film in the hard mask, the second interlayer insulating film, the etching stopper film, and the first interlayer insulating film; embedding an embedded material to a level higher than the first interlayer insulating film and lower than the top surface of a layered stack composed of the first interlayer insulating film, the etching stopper film, and the second interlayer insulating film in the via hole; forming a trench in the second interlayer insulating film by etching the hard mask and the second interlayer insulating film, using a resist mask in which an opening for exposing the embedded material is formed, the whole of a bottom surface of the trench being above an upper surface of the etching stopper film and below that of the embedded material; removing the resist mask and the embedded material; etching the second interlayer insulating film again by using the hard mask as a mask after removing the resist mask and the embedded material; forming a wiring trench by removing the hard mask, and exposed parts of the etching stopper film, and the cap film; and embedded an electric conductive film in the via hole and the wiring trench.