Patent ID: 8832416

Claim:
A method of processing instructions in a processor, the method comprising: providing, by an instruction source, a group of instructions to the processor for execution, the processor including a special purpose register (SPR) bank; unlocking, by a stall analyzer external to the processor, the SPR bank; first determining, by the processor, if a particular instruction of the group of instructions is a next instruction to complete execution, thus designating the next to complete instruction; second determining, by the processor, if the next to complete instruction exhibits a stall event during its execution and, in the case of such a stall event during execution, storing in the special purpose register (SPR) bank stall information relating to a cause of the stall event for the next to complete instruction, the SPR bank including a completion stall counter register that stores a worst case clock cycle length for instruction stall evaluation, a completion event indicator register that stores a collection of stall event causes of an instruction stall for the next to complete instruction, a completion stall indicator register that stores a last completion event indicator for the next to complete instruction that exhibits a stall condition, and a stall flag register that stores a stall indicator flag that indicates if the next to complete instruction exhibits a stall event; completing execution, by the processor, of the next to complete instruction such that the next to complete instruction becomes a completed instruction; storing, in the SPR bank, stall information for the completed instruction, wherein the stall information for the completed instruction includes multiple stall event causes when the completed instruction exhibits multiple stall event causes; locking, by the processor, the SPR registers of the SPR bank; retrieving, by the stall analyzer external to the processor, stall information periodically from the SPR bank to determine a cause of each stalled completed instruction; storing, by the stall analyzer, the retrieved stall information in a system memory; third determining, by the stall analyzer, an aggregate stall count of stalled completed instructions from the retrieved stall information; fourth determining, by the stall analyzer, an instruction stall frequency of a particular instruction from the retrieved stall information, testing, by the stall analyzer, the retrieved stall information to determine if there are multiple stall event causes of a stall of a particular completed instruction, and repeating the unlocking, first determining, second determining, completing, storing in the SPR bank, locking, retrieving, and storing the retrieved stall information steps for subsequent next to complete instructions in the group of instructions to determine a stall event pattern by the stall analyzer.