Patent ID: 8169347

Claim:
A parallel-to-serial converter comprising: an input circuit that latches and outputs a plurality of data signals input in parallel in accordance with a first clock signal; a selection circuit that selects one of the plurality of data signals output in parallel from the input circuit in accordance with the first clock signal and that outputs a converted serial data signal; an output circuit that latches and outputs the data signal output from the selection circuit in accordance with a second clock signal; a frequency divider circuit that divides a frequency of a clock signal, on which the second clock signal is based, to generate the first clock signal; a replica circuit including a replica selection circuit that selects one of a plurality of data signals replica of the plurality of data signals input to the input circuit in accordance with the first clock signal and that outputs a converted serial replica data signal, a replica output circuit that latches and outputs the replica data signal output from the replica selection circuit in accordance with a replica clock signal having a cycle substantially identical to a cycle of the second clock signal, and a phase set circuit that shifts at least one of a phase of the second clock signal and a phase of the replica clock signal based on the phase of the second clock signal and the phase of the replica clock signal.