Patent ID: 7774513

Claim:
A DMA circuit, comprising: a buffer memory, which stores transfer data read from a memory; a channel manager circuit which executes a DMA transfer processing of a plurality of DMA channels each of which directly accesses said memory and transfers data in response to transfer instructions from an external device; and a control memory, which stores control information comprising a progress status of said DMA transfer processing of each of the plurality of DMA channels, wherein said channel manager circuit reads said control information of each of the plurality of DMA channels from said control memory in the order of the plurality of DMA channels, analyzes the read progress status in said control information, executes a divided processing of said DMA transfer processing in the corresponding DMA channel according to the analyzed progress status and as indicated by said control information, updates the progress status in said control information of said DMA channel to the status of the next processing following said executed divided processing of said DMA transfer processing, and writes back said control information to said control memory, said divided processing of said DMA transfer processing comprising a first processing to judge a transfer instruction from said external device, a second processing to read a descriptor from said memory after said first processing, a third processing to read transfer data from said memory according to said descriptor after said second processing, and a fourth processing to transfer said transfer data to specified said transfer destination after said third processing.