Patent ID: 8301682

Claim:
A divider for fixed point division comprising: a first storage space with a divisor; a second storage space with a dividend or revised dividend; a third storage space with a preliminary answer, initialized to zero; a subtractor for subtracting the divisor from the second storage space to produce a result; and a processor for computing an answer to the division of the divider by revising the dividend and preliminary answer during a number of iterations of the subtractor until a required precision is reached, wherein the revising includes: in the event of no overflow from the subtractor, left shifting the result 1 bit, removing the most significant bit of the result, left shifting the preliminary answer in the third storage space 1 bit, removing the most significant bit of the preliminary answer, loading the least significant bit of the result with the most significant bit of the preliminary answer, loading 1 into the least significant bit of the preliminary answer, and storing the revised result in the second storage space; in the event of overflow from the subtractor, left shifting the dividend 1 bit, removing the most significant bit of the dividend, left shifting the preliminary answer in the third storage space 1 bit, removing the most significant bit of the preliminary answer, replacing the least significant bit of the dividend with the most significant bit of the preliminary answer, loading 0 into the least significant bit of the preliminary answer, and storing the revised dividend in the second storage space; and, wherein upon completion of the iterations, the divider is adapted to output the preliminary answer in the third storage space as the answer to the division; wherein the divisor and the dividend are in the range (−1,1); and wherein the divider is adapted to insert a decimal place in the answer.