Patent ID: 7750406

Claim:
A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising: a semiconductor layer carried on a substrate, said semiconductor layer comprising a plurality of first device regions having a first crystal orientation and a plurality of second device regions having a second crystal orientation differing from the first crystal orientation; a first insulating layer between said semiconductor layer and the substrate; a second insulating layer at least partially between said first insulating layer and the substrate; a plurality of first body regions of semiconductor material between said first and second insulating layers, each of said first body regions separated from a respective one of said first device regions by a portion of said second insulating layer; and a plurality of dielectric regions extending through said semiconductor layer to said first insulating layer, each of said dielectric regions disposed between one of said first device regions and one of said second device regions, wherein each of said dielectric regions further extends from said first insulating layer to said second insulating layer, and adjacent pairs of said dielectric regions bound one of said first body regions so that each of said first body regions is aligned with a respective one of said first device regions.