Patent ID: 7298790

Claim:
A Phase-Locked Loop with multiphase clocks for use in a digital system, said Phase-Locked Loop comprising: a main loop comprising, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider; a calibration loop coupled to the Phase Frequency Detector, the calibration loop comprising a Calibration Charge Pump, a Demultiplexer and Y Calibration Loop Filters, with Y being an integer; and Control Logic for controlling the Phase-Switching Fractional Divider and the Demultiplexer, wherein the Phase Frequency Detector includes an input for receiving a Reference Frequency Signal, a Calibration Signal is coupled to the calibration loop, and the main loop further comprises a Phase-adjusting Block coupled to a Multiplexer, the Phase-adjusting Block including at least one input for receiving at least one correction signal from the calibration loop.