Patent ID: 8713345

Claim:
An electronic circuit, comprising: a digital signal processing circuit; a reference timing circuit that generates a reference timing signal; and a local timing circuit, locally connected to the digital signal processing circuit, configured to receive the reference timing signal, generate a multi-phase timing signal corresponding to the reference timing signal, and output the multi-phase timing signal to the digital signal processing circuit, wherein the reference timing circuit is disposed further than the local timing circuit from the digital signal processing circuit, wherein the reference timing signal comprises a single phase clock signal, and the local timing circuit is configured to receive a control signal that controls a differential delay of respective components of the multi-phase timing signal with reference to the single phase clock signal, and wherein the digital signal processing circuit receives the single phase clock signal and the multi-phase timing signal, and uses the single phase clock signal for low processing speed operations and the multi-phase timing signal for high processing speed operations.