Patent ID: 6948103

Claim:
A computer comprising: a controller which executes a reset process, in response to a reset signal; an oscillator oscillates a clock; and a timer which counts pulses of the clock, and outputs the reset signal to said controller, in a case where a counted value obtained by counting the pulses of the clock exceeds a predetermined limit value, wherein said controller controls said timer, and clears the countered value before the counted value exceeds the limit values and said timer begins counting the pulses of the clock in synchronization with that said controller be the reset process, thereby detecting an abnormal operation occurring in the computer during execution of the reset process, said timer has a plurality of operational modes, said controller outputs a mode of specification signal for specifying an operation mode of said timer, and wherein said timer sets an operational mode thereof, in accordance with the mode specification signal, and said timer includes a circuit, which sets the mode specification sign sent from said controller ineffective in response to setting of the operational mode of said timer.