Patent ID: 7187604

Claim:
A semiconductor memory comprising: a memory cell array including a plurality of normal memory cell rows and a redundancy memory cell row, each of said normal memory cell rows including a normal word line and a normal memory cell connected to said normal word line, said redundancy memory cell row including a redundancy word line and a redundancy memory cell that both relieve defects of said normal memory cell rows, the redundancy memory cell being connected to said redundancy word line; a shift register composed of a plurality of latches corresponding to said normal word lines and said redundancy word line, respectively, in order to sequentially activate any of said redundancy word line and said normal word lines upon every refresh request; an activation circuit that activates any of said redundancy word line and said normal word lines according to an output of said shift register; a first storing circuit that stores in advance a defect address indicating a defective normal memory cell row when there is a defect in any of said normal memory cell rows; a first comparing circuit that activates a defect coincidence signal when the output of said shift register indicates the normal word line corresponding to said defect address stored in said first storing circuit; a first activation control circuit that prohibits activation of a normal word line corresponding to said defect address stored in said first storing circuit, in response to the activation of said defect coincidence signal.