Patent ID: 7756695

Claim:
A system that enables enhanced accelerator/emulator simulation and testing of a device under test (DUT), said system comprising: a workstation executing a first code of sequential operations; an emulator/accelerator concurrently executing a similar code of sequential operations and coupled to said workstation via a first communication link, wherein the first code and similar code of sequential operations are executed in parallel; a target hardware coupled to the emulator/accelerator via a second communication link, said target hardware being the DUT and configured as a CBEA (Cell Broadband Engine Architecture)-compliant system designed with Replacement Management Tables (RMTs), said CBEA-compliant system having an N-way set-associative cache, wherein said cache includes a cache replacement algorithm that is controlled by said RMTs, which RMTs enable software to direct entries with specific address ranges at a particular subset of the cache, and enables a user to prevent overwriting data in the cache by directing data that is used only once at a particular set among the N ways and by locking data in the cache, wherein said RMTs enables code streams to be “locked” into different ways within the N-way set associative cache; and logic within the emulator/accelerator for exercising and testing said target hardware for compliance with design parameters and specifications, said logic comprising logic for: enabling a user to modify the address range of load and store operations in the similar code so that the operations each modify different partitions in the cache of the CBEA-complaint system, whereby the user is able to run code sets that generate data and cache states in each of the different sets of the N sets within the cache; and deterministically locking, via the RMTs, specific cache locations identified by user input and executing code following an RMT-directed modification of said specific cache locations by said load and store operations; wherein said workstation further comprises: logic for executing code streams in parallel that are expected to produce identical results to a cache set under separate RMTs in an accelerated simulation, logic for verifying the results by comparing each stream's cache set to a cache set outputted from a parallel code stream, wherein said verifying comprises comparing both a cache data and a cache state generated by each of the parallel code streams to determine whether there is a variation in either the cache data or in the cache state; and logic for identifying and outputting the test as a failure when a variation is found during said comparing.