Patent ID: 7879674

Claim:
A method of forming a memory cell, comprising: forming a source region, a drain region, and a channel region disposed between and separating the source and drain regions, in a semiconductor substrate; forming a gate oxide layer on and contacting the semiconductor substrate over at least the channel region and over at least portions of the source and drain regions; forming an electrically isolated floating gate on and contacting the gate oxide layer over the channel region and over at least portions of each of the source and drain regions, the floating gate formed of a mixture consisting essentially of silicon, germanium and carbon, the arrangement of the floating gate and the gate oxide layer forming a tunnel barrier having a tunneling barrier height; selecting a value for the tunneling barrier height to match an operational parameter of the channel region such that selecting the value selects an electron affinity for the mixture; controlling an amount of the carbon in the mixture to match the selected electron affinity for the floating gate; forming an inter-gate insulator over the floating gate; and forming a control gate over the inter-gate insulator and separated from the floating gate by the inter-gate insulator.