Patent ID: 6894320

Claim:
An input protection circuit comprising: a semiconductor substrate of a first conductivity type; a main circuit formed on said semiconductor substrate; an input terminal formed above said semiconductor substrate and connected to said main circuit; a well of a second conductivity type opposite to the first conductivity type formed in a principal surface of said semiconductor substrate, said well forming a pn junction together with said semiconductor substrate; a first lateral bipolar transistor having said well as a base, said semiconductor substrate as a collector, and a first emitter region of the first conductivity type formed in said well; a second lateral bipolar transistor having said well as a collector, which is thereby connected to the base of the first lateral bipolar transistor, said semiconductor substrate as a base, which is thereby connected to the collector of the first lateral bipolar transistor, and a second emitter region of the second conductivity type formed in the principal surface of said semiconductor substrate near said well; and an insulated gate electrode of a MOS transistor having said well and the second emitter region as a drain and a source respectively, said insulated gate electrode being formed on a surface of said semiconductor substrate between said well and the second emitter region, wherein said input terminal is connected to the first emitter region, said well is connected to said insulated gate electrode and is electrically floating, the second emitter region and said semiconductor substrate are connected to a reference potential, and a thyristor constituted of said first and second lateral bipolar transistors is made conductive by using as a trigger a current flowing through the MOS transistor when a surge voltage is applied from said input terminal to said insulated gate electrode only via an emitter pn junction of said first lateral bipolar transistor.