Patent ID: 8625386

Claim:
A non-volatile memory device comprising: a control unit performing a communication process with a host device; a non-volatile memory including a first memory region and a second memory region storing data to be written transmitted from the host device; and a memory control unit performing reading and writing of the non-volatile memory, wherein the first memory region and second memory region are configured by each of physical pages, wherein each of the physical pages is configured by a plurality of regions corresponding to a plurality of logical addresses, wherein the memory control unit performs control of batch erasing and batch writing on every physical page, wherein when a first physical page in the first memory region includes a first region corresponding to a first logical address, which is a target to be written, of the data to be written transmitted from the host device and when a second physical page in the second memory region includes a second region corresponding to the first logical address, which is a target to be written, the memory control unit selects either of the first physical page in the first memory region or the second physical page in the second memory region as a physical page for writing and selects the other as a physical page for reading, wherein when the first physical page is selected as the physical page for writing, the memory control unit writes the data to be written in the first region corresponding to the first logical address which is the target to be written, and wherein when the first physical page, selected as the physical page for writing, includes a third region corresponding to a second logical address which is not the target to be written and the second physical page, selected as the physical page for reading, includes a fourth region corresponding to the second logical address which is not the target to be written, the memory control unit copies and writes data stored in the fourth region corresponding to the second logical address which is not the target to be written in the third region corresponding to the second logical address which is not the target to be written.