Patent ID: 7774673

Claim:
A decoding device for a transmission system using direct sequence spread spectrum, the device being structured to decode a digital input signal in base band composed of bits, each bit being represented by one of two symbols depending on its value, each symbol consisting of a series of N symbol elements distributed on one of two different levels and output at a fixed frequency with possible individual variations in phase and duration, and the N symbol elements of the first symbol being anti-correlated to the N corresponding symbol elements in the second symbol, the device comprising: a clock circuit; a plurality M of finite response base filters each of which is configured to receive the digital input signal, wherein the clock circuit outputs a plurality M of clock signals to the M base filters respectively, with a common frequency equal to the fixed frequency and corresponding phase shifts uniformly distributed between these M clock signals, and wherein the base filters are clocked to capture the corresponding samples of the input digital signal at instants at which their corresponding clock signals reach a determined phase angle common to all the filters, wherein each base filter outputs an output signal at its output at each period of its clock signal, the amplitude of the output signal being a function of the correlation level, representing a variable resemblance between the sequence of the last N samples picked up by this base filter and the series of N symbol elements of the first symbol; an analysis circuit connected to the output from each base filter and configured to identify which of the M base filters produces an output signal with a maximum amplitude and/or a minimum amplitude, over a time interval equal to at least the duration of a symbol, and by default to specify the clock signal received by the base filter as an optimum clock signal for decoding; and an additional finite response filter receiving the digital input signal parallel to the base filters, wherein the clock circuit is controlled by the analysis circuit to output the optimum clock signal to this additional filter, the additional filter also being clocked to pick up a sample of the digital input signal at the instants at which the optimum clock signal reaches the determined phase angle common to all filters, and to produce an output signal for which the absolute value of the amplitude is at least as large as the amplitude of the output signals of the base filters, at each period of the optimum clock signal.