Patent ID: 8400803

Claim:
A content addressable memory device comprising: a first memory array comprising a plurality of content addressable memory cells arranged in a matrix; a plurality of first match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the first memory array; a plurality of first determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the first memory array, according to a voltage of the first match line; a second memory array comprising a plurality of content addressable memory cells arranged in a matrix, a plurality of second match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the second memory array; a plurality of second determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the second memory array, according to a voltage of the second match line; and a control circuit operable to direct to start searching in the second memory array after two or more cycles after searching has been started in the first memory array, and operable to direct to stop searching in the second memory array according to a voltage of the first match line after the searching in the first memory array.