Patent ID: 8462025

Claim:
An electronic device comprising: a first component configured to: generate a first sequence of bit patterns, the first sequence of bit patterns configured to control operation of a second component of the electronic device; generate a second sequence of bit patterns mapped to the first sequence of bit patterns, wherein each bit pattern in the second sequence is mapped to a bit pattern in the first sequence, and wherein fewer bits are transitioned between each pair of adjacent bit patterns in the second sequence than between the corresponding pair of adjacent bit patterns in the first sequence; and transmit the second sequence of bit patterns to the second component of the electronic device over a wired connection; and a second component operatively connected to the first component via the wired connection and configured to: receive the second sequence of bit patterns from the first component of the electronic device over the wired connection; translate the second sequence of bit patterns into a third sequence of bit patterns, wherein each bit pattern in the second sequence is translated into a corresponding bit pattern in the third sequence, and wherein more bits are transitioned between each pair of adjacent bit patterns in the third sequence than between the corresponding pair of adjacent bit patterns in the second sequence; and control operation of the second component based on the third sequence of bit patterns.