Patent ID: 7417466

Claim:
A flip-flop circuit comprising: a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals; a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows; a first load transistor that is connected between the first power supply potential and the first output terminal and whose conductive state is controlled by the signal of the second output terminal; a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal; a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by complementary first and second input pulses and complementary signals of first and second output nodes; a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows; a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows; a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node; a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node; and a second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals.