Patent ID: 8601187

Claim:
A semiconductor device comprising: a serial interface circuit for serial communication; and a CPU, wherein the serial interface circuit receives frames having field structures containing destination information and including a data field, receives a received signal via a terminal of the semiconductor device, and transmits a transmit signal via another terminal of the semiconductor device, and wherein the serial interface circuit is configured to compare the field structure of a received frame with an expected field structure specified by a control register of the serial interface circuit, and when destination information of the received frame is determined to match the expected destination information specified by the control register, the serial interface circuit outputs a request to the CPU to cause the CPU to process information of the data field, wherein the control register of the serial interface circuit includes a first register for storing information used for a comparison with information of a control field of the received frame; a second register for storing information used for a comparison with information of an address field of the received frame; and a setting region for rewritably setting first information for selecting a first or second operation, the first operation including the step of issuing a request for having the CPU handle information of a data field behind a subsequent field following a head field of the received frame in response to concurrence of a match resulting from a comparison between information of the head field, and information of the first register, and a match resulting from a comparison between information of the subsequent field and information of the second register; and a setting region of second information showing whether or not a synchronization pattern is located before the head field, wherein the second operation includes issuing a request for having the CPU handle information of the data field following the head field in response to a match resulting from a comparison between information of the head field and information of the second register, and wherein on a condition that the second information shows presence of the synchronization pattern, the serial interface circuit waits for the synchronization pattern to end, and then performs the first or second operation.