Patent ID: 8213143

Claim:
A circuit arrangement for protecting electronic device from damage due at least one of excessive current and excessive voltage upon a fault, the circuit arrangement comprising: at least one first terminal associated with the electronic device; at least one second terminal associated with the electronic device; a first interface and a second interface; a fault detection circuit region, the fault detection circuit region being configured to detect the fault and generate a fault signal indicating the fault; a fault signal processing circuit region, the fault signal processing circuit region begin configured to process or forward the fault signal and generate a disconnection signal; and a disconnection circuit region, the disconnection circuit region being configured to disconnect the electronic device from a fault source based on the disconnection signal, wherein: in a fault-free state, the at least one first terminal is coupled to the at least one second terminal, the fault detection circuit region is coupled to the fault signal processing circuit region via the first interface, the fault signal processing circuit region is coupled to the disconnection circuit region via the second interface, the disconnection circuit region is configured to disconnect at least one of the at least one first terminal and the at least one second terminal, and the fault detection circuit region, the first and second interfaces, and the disconnection circuit region are configured to be compatible with another different fault signal processing circuit region.