Patent ID: 7332799

Claim:
A packaged chip, comprising: a chip having a horizontally extending front surface and a plurality of bond pads exposed at said front surface; a package element, said package element including: a dielectric element having an inner face and an outer face remote from said inner face, a plurality of chip contacts exposed at said inner face, said plurality of chip contacts conductively connected to said plurality of bond pads of said chip, a plurality of package contacts exposed at said outer face, a metal layer exposed at one of said inner face or said outer face of said dielectric element, said metal layer including a first conductive trace and a second conductive trace, said first conductive trace having a first edge extending in a first direction and said second conductive trace having a second edge adjacent to said first edge, said second edge extending substantially in said first direction, said first conductive trace being in conductive communication with a signal-bearing chip contact of said plurality of chip contacts and with a signal-bearing package contact of said plurality of package contacts, said metal layer further including a second conductive trace in conductive communication with a ground chip contact of said plurality of chip contacts and in conductive communication with a ground package contact of said plurality of package contacts, said first and second conductive traces functioning as first and second plates, respectively, of a capacitor, said capacitor connected in parallel with a signal path through said first conductive trace.