Patent ID: 7245019

Claim:
A semiconductor device, comprising: (a) a first wiring and a second wiring extending in a first direction and being adjacent to each other; (b) a third wiring connected to the first wiring through a first connection and extending in a direction opposite to the second wiring and along a line orthogonal to the first direction, the third wiring having a first surplus portion projecting in the direction of the second wiring from the first connection; and (c) a fourth wiring connected to the second wiring through a second connection and extending along said line in a direction opposite to the first wiring, the fourth wiring having a second surplus portion projecting in the direction of the first wiring from the second connection, wherein the first, second, third, and fourth wirings are arranged such that, (d) a center of the second connection is offset in a direction opposite to the first wiring from a center of the second wiring, and (e) a projecting portion of the second wiring is disposed under the second connection, wherein a MISFET underlies the first and the second wirings, and wherein a gate electrode of the MISFET is disposed in the first direction between the first and the second wirings.