Patent ID: 8893142

Claim:
A multiprocessor system comprising a first processor element and a second processor element each independently executing a program, wherein said first processor element comprising: a central processing unit performing an information processing based upon the program; a shared resource capable of being accessed with the second processor element; and a guard unit coupled to said central processing unit that is configured to restrict an access request issued from the second processor element to the shared resource, the guard unit restricting the access request based upon an access protection range setting value that is designated by the central processing unit, wherein the guard unit comprises: a protection setting unit for holding the access protection range setting value which is sent from the central processing unit via a protection information setting bus; a judging unit for judging whether or not the access request is present within a range of the access protection range setting value based upon information held in the protection setting unit; and an exceptional access occurrence notification unit, which outputs an exceptional access notification signal to the central processing unit, if the access request is present within the range of the access protection range setting value, wherein the exceptional access notification signal is processed in an interrupt processing manner by the central processing unit and the central processing unit extends the access protection range after output of the exceptional access notification signal such that the extended access protection range is wider than the access protection range before output of the exceptional access notification signal, wherein the protection setting unit comprises a plurality of setting information holding registers for holding setting information that is different from each other, wherein said plurality of setting information holding registers comprise: protection range setting registers for holding thereinto access ranges that are protected, respectively; and enable flag registers for holding flag values which indicate that the values of the plurality of setting information holding registers are one of a valid value and an invalid value, and wherein the enable flag registers can change the flag values in response to statuses of processing under execution by the first processor element.