Patent ID: 8378431

Claim:
A semiconductor device comprising a cell array region and a peripheral circuit region provided adjacent to the cell array region with an isolation region interposed therebetween, the semiconductor device comprising: a substrate; a gate insulating film formed on the substrate; a plurality of first trenches formed in a column direction in the cell array region, the plurality of first trenches penetrating through the gate insulating film and reaching into the substrate; a plurality of first embedded insulating films embedded in the plurality of first trenches; a plurality of second trenches formed in the column direction in the peripheral circuit region, the plurality of second trenches penetrating through the gate insulating film and reaching into the substrate; a plurality of second embedded insulating films embedded in the plurality of second trenches; a third trench formed in the isolation region, the third trench reaching into the substrate; a third embedded insulating film embedded in the third trench; a plurality of gate structures formed on the gate insulating film in a row direction crossing the column direction so as to extend over the cell array region, the peripheral circuit region, and the isolation region; and a plurality of inter-gate insulating films formed in the row direction between the plurality of gate structures, the plurality of inter-gate insulating films covering the plurality of first embedded insulating films, the plurality of second embedded insulating films, and the third embedded insulating film, wherein an upper surface of the third embedded insulating film covered with each of the plurality of inter-gate insulating films is substantially flat, upper surfaces of the plurality of first embedded insulating films, upper surfaces of the plurality of second embedded insulating films, and the upper surface of the third embedded insulating film are higher than an upper surface of the gate insulating film, and the height of the upper surfaces of the plurality of first embedded insulating films and the upper surface of the third embedded insulating film is lower than the height of the upper surfaces of the plurality of second embedded insulating films.