Patent ID: 7262641

Claim:
A system comprising: a processor; and a device coupled to the processor and having a differential buffer comprising: a differential pair configured to receive a plurality of input signals and to generate a plurality of output signals; adjustment circuitry coupled to the differential pair and configured to adjust an amount of current dissipated by the differential buffer; current pulse circuitry coupled to the differential pair and the adjustment circuitry, wherein the current pulse circuitry is configured to generate a current pulse that is coincident with the switching of the differential pair; grounding circuitry coupled to the current pulse circuitry and the differential pair, wherein the grounding circuitry is configured to receive the current pulse; and a bias device that is coupled to the differential pair and the grounding circuitry and is configured to adjust an amount of current flowing through the differential pair; wherein the current pulse circuitry comprises: a first current transistor and a second current transistor coupled in series with each other, the first current transistor and second current transistor being coupled between a first voltage source and the grounding circuitry at a grounding node, a gate of the first current transistor and a gate of the second current transistor coupled to a first input terminal; and a third current transistor and a fourth current transistor coupled in series between the first voltage source and the grounding circuitry at the grounding node, a gate of the third current transistor and a gate of the fourth current transistor coupled to a second input terminal.