Patent ID: 8625332

Claim:
A semiconductor memory device comprising: a plurality of cell arrays having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between said first wirings and said second wirings, each memory cell containing a variable resistive element that is electrically rewritable and stores a resistance value as data; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit performs: a first operation of applying a voltage required for one operation selected from data write, read and erase operations to a first memory cell via a first combination of said first and second wirings, a second operation of applying a voltage required for an operation selected from the data write, read and erase operations and different from the first operation to a second memory cell via a second combination of said first and second wirings, and a third operation of applying a voltage required for an operation selected from the data write, read and erase operations and different from the first operation to a third memory cell via a third combination of said first and second wirings, and said second and third operations are performed after said first operation is initiated and before said first operation is completed, wherein the first operation and second operation are performed for different memory blocks.