Patent ID: 7361591

Claim:
A method of fabricating a semiconductor device, the method comprising: preparing a semiconductor substrate having a cell region, a core N-channel metal oxide semiconductor (NMOS) region, and a core P-channel MOS (PMOS) region; defining a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region, respectively, by forming an isolation layer in predetermined regions of the semiconductor substrate; forming a cell gate pattern, an NMOS gate pattern, and a PMOS gate pattern crossing the cell active region, the NMOS active region, and the PMOS active region, respectively; forming an interlayer-insulating layer on the semiconductor substrate having the gate patterns; simultaneously forming a storage node landing pad, a bit line landing pad, and NMOS landing pads, the storage node landing pad and the bit line landing pad in physical contact with predetermined regions of the cell active region adjacent to the cell gate pattern in the interlayer-insulating layer of the cell region, the NMOS landing pads in physical contact with predetermined regions of the NMOS active region adjacent to the NMOS gate pattern in the interlayer-insulating layer of the core NMOS region, each of the storage node, bit line, and NMOS landing pads having a top surface that is lower than a surface of the interlayer-insulating layer; and patterning the interlayer-insulating layer of the core PMOS region to form PMOS interconnection contact holes that expose predetermined regions of the PMOS active region adjacent to the PMOS gate pattern.