Patent ID: 8786109

Claim:
A conductive structure for a semiconductor chip, the semiconductor chip comprising a semiconductor substrate, a plurality of first pads, a plurality of second pads, a passivation layer and a plurality of under bump metal layers, wherein each of the first pads and each of the second pads are alternately arranged on a pad area of the semiconductor substrate, the pad area defines a first area, a second area and a third area, the first area is located between the second area and the third area, each of the first pads and each of the second pads are interlaced with each other on the first area, and the first area is extending toward the second area and the third area respectively, and wherein the passivation layer formed on the semiconductor substrate has a plurality of first openings to partially expose each of the first pads and each of the second pads, and each of the under bump metal layers is formed on the passivation layer and is electrically connected with each of the first pads and each of the second pads through each of the first openings formed in the passivation layer, the conductive structure comprising: a plurality of conductive bumps, formed on each of the first pads and each of the second pads respectively, each of the under bump metal layers being disposed under each of the conductive bumps so that each of the conductive bumps is electrically connected with each of the first pads and each of the second pads through each of the under bump metal layers, wherein each of the conductive bumps has a first bump-width in the first area and a second bump-width in one of the second area and the third area, and the first bump-width is smaller than the second bump-width.