Patent ID: 8685812

Claim:
A method of forming a logic switch, comprising: forming a first semiconductor region of a first conductivity type, the first semiconductor region being a low-doped region; forming a second semiconductor region of a second conductivity type adjacent to the first semiconductor region, the second semiconductor region being a highly-doped region, and a pn junction defined between the first and second semiconductor regions; and forming a gate overlying the pn junction and immediate junction-adjacent surfaces of the first and second semiconductor regions, the forming the gate comprising: forming a thin oxide layer on a surface of the first and second semiconductor regions; and forming a conductive gate electrode on the thin oxide layer, the conductive gate electrode having a first edge overlying an uppermost surface of the first semiconductor region and a second edge overlying an uppermost surface of the second semiconductor region, the conductive gate electrode being highly-doped with a dopant of the first conductive type.