Patent ID: 7034359

Claim:
A vertical MOS transistor comprising: a first-conductivity type semiconductor substrate forming a high concentration drain region; a first-conductivity type epitaxial growth layer forming a low concentration drain region disposed on the semiconductor substrate; a second-conductivity type body region disposed on the epitaxial growth layer; a second-conductivity type high concentration body contact region disposed on a front surface of a portion of the body region; a first-conductivity type high concentration source region formed on a region of the front surface of the body region outside of the high concentration body contact region; a first silicon trench passing completely through the body region and the high concentration source region to a depth that reaches an internal portion of the epitaxial growth layer; a second silicon trench disposed so that the high concentration body contact region contacts the second silicon trench and the high concentration source region does not contact the second silicon trench; a gate insulator film formed along a wall surface and a floor surface of each of the first and second silicon trenches; and high concentration polycrystalline silicon gates embedded within the respective first and second trenches and surrounded by the gate insulator film.