Patent ID: 8817512

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked in a vertical direction extending away from the substrate; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers, wherein each sense amplifier is connected to a respective bit line via a respective bit line connection line, the bit line connection lines having every adjacent N lines (where N is an integer of 2 or more) as one group, the sense amplifiers being arranged in a number smaller than N in a first direction that the bit line connection lines extend, an M number (M is an integer of 1 or more) of the sense amplifiers being arranged in a width of a P number (P is an integer of 1 or more) of groups in a second direction intersecting the first direction, each group of sense amplifiers corresponding to a respective group of bit line connection lines, the M number being larger than the P number, and the memory cell array comprises a column of the sense amplifiers extending in the first direction, wherein the column includes sense amplifiers connected to bit line connection lines belonging to two adjacent groups.