Patent ID: 7903449

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells each including a field-effect transistor and a capacitor, wherein gates of the field-effect transistors are connected to a plurality of word lines, drains of the field-effect transistors are connected to first electrodes of the capacitors, and sources of the field-effect transistors are connected to a plurality of bit lines; a plurality of word line drivers connected to distal ends of the word lines so as to drive the word lines; a plurality of sense amplifiers connected to distal ends of the bit lines so as to amplify read signals read from the memory cells onto the bit lines; and a plurality of first dummy capacitors which are disposed in a first boundary between the memory cell array and the word line drivers and/or a second boundary between the memory cell array and the sense amplifiers, wherein first electrodes of the first dummy capacitors are connected together and are supplied with a first potential, and wherein second electrodes of the capacitors are connected together with second electrodes of the first dummy capacitors and are supplied with a second potential.