Patent ID: 8546867

Claim:
A non-volatile memory semiconductor device, comprising: a first memory cell array region; a second memory cell array region; and an electricity supply region sandwiched by the first memory cell array region and the second memory cell array region over a semiconductor substrate, wherein the first memory cell array region, the second memory cell array region, and the electricity supply region are arranged side by side in a first direction, wherein the device includes (a) a first control gate electrode extending along the first direction from the first memory cell array region to the electricity supply region and having a first terminal end disposed within the electricity supply region; (b) a first memory gate electrode formed on a sidewall of the first control gate electrode via a first insulating film and extending in the first direction; (c) a second control gate electrode extending along the first direction from the second memory cell array region to the electricity supply region and having a second terminal end disposed within the electricity supply region; and (d) a second memory gate electrode formed on a sidewall of the second control gate electrode via a second insulating film and extending in the first direction, wherein the first control gate electrode and the second control gate electrode are arranged in a straight line and the first terminal end and the second terminal end are arranged separated from each other, wherein the device further comprises (e) an electricity supply line with one end arranged over the first terminal end and the other end arranged over the second terminal end; and (f) a plug electrically connected with the electricity supply line, wherein the electricity supply line is formed by processing a first conductive film forming the first memory gate electrode and the second memory gate electrode, wherein the first memory gate electrode and the second memory gate electrode are electrically connected via the electricity supply line, wherein a predetermined voltage is applied to the first memory gate electrode and the second memory gate electrode via the electricity supply line, and wherein the plug is formed over the electricity supply line and is disposed between the first terminal end and the second terminal end in a plan view.