Patent ID: 7701298

Claim:
A frequency locking structure applied to phase-locked loops, comprising: a first divider, for receiving an input signal and dividing the input signal by a first constant factor; a multiplexer, coupling the first divider, for receiving a signal from the first divider and multiplying the signal from the first divider together with a common factor to output a reference input signal; a phase-locked loop, coupling the multiplexer, for receiving the reference input signal and a feedback signal to output an oscillator output signal; a second divider, coupled the phase-locked loop, for receiving the oscillator output signal and dividing the oscillator output signal by a second constant factor to acquire the feedback signal, and transmitting the feedback signal into the phase-locked loop; and a third divider, coupled to the phase-locked loop, for receiving the oscillator output signal and dividing the oscillator output signal by a third constant factor to output an output signal.