Patent ID: 7661055

Claim:
An apparatus, comprising: a plurality of bit processors that is operable to: during a first time, perform bit node processing that involves updating a first plurality of bit edge messages selected from a total plurality of bit edge messages; and during a second time, perform bit node processing thereby updating a second plurality of bit edge messages selected from the total plurality of bit nodes; and a plurality of check processors that is operable to: during a third time, perform check node processing that involves updating a first plurality of check edge messages selected from a total plurality of check edge messages; and during a fourth time, perform check node processing that involves updating a second plurality of check edge messages selected from the total plurality of check edge messages; and wherein the total plurality of bit edge messages and the total plurality of check edge messages selectively connect between a plurality of bit nodes and a plurality of check nodes of an LDPC (Low Density Parity Check) bipartite graph that corresponds to an LDPC code.