Patent ID: 8611485

Claim:
A control device for controlling frequency synchronization, the control device comprising a processor configured to: form frequency-error indicators on the basis of first values of reception moments of received timing messages transmitted in accordance with a reference clock signal, the first values of the reception moments being expressed as time values based on a frequency-controlled clock signal, and control the frequency-controlled clock signal with the frequency-error indicators so as to achieve frequency-locking between the reference clock signal and the frequency-controlled clock signal, wherein the processor is configured, for the purpose of forming each of the frequency-error indicators, to calculate a first quantity that is a difference between the first values of the reception moments of two such timing messages which have experienced a substantially similar transfer delay, calculate a second quantity that is a difference between reference moments of these two timing messages, and calculate a difference between the first and second quantities, and the processor is configured, for the purpose of finding two such timing messages which have experienced a substantially similar transfer delay, to: form phase-error indicators on the basis of second values of the reception moments of the timing messages, the second values of the reception moments being expressed as time values based on a phase-controlled clock signal and each of the phase-error indicators being a difference between the second value of the reception moment of the respective timing message and a reference moment of this timing message, control the phase-controlled clock signal with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal, and select the two timing messages from among the received timing messages on the basis of the phase-error indicators of the received timing messages.