Patent ID: 7359226

Claim:
A memory comprising: an array of transistors in a substrate for selecting one of a plurality of memory cells, each memory cell coupling a transistor to a bit line via a memory element and being addressable by selecting two word lines and a bit line, the array of transistors formed by a plurality of word line trenches forming stripes of substrate material serving as active areas of the transistors, the stripes separated by pieces of insulation trenches, thus the word line trenches separating transistor cells in a first direction and the pieces of insulation trenches separating transistor cells in the direction of word line trenches; wherein one word line trench takes one word line; and wherein a first word line in a first word line trench forms a plurality of gate electrodes on one sidewall of active areas of a first and a second, adjacent row of transistor cells in word line direction; and wherein a second word line in an adjacent word line trench forms a plurality of gate electrodes on the opposite sidewall of active areas of the second and of a third row of transistor cells in wordline direction.