Patent ID: 7969698

Claim:
A system, comprising: a memory circuit, comprising: an input/output (I/O) circuit; and an electrostatic discharge (ESD) shunt circuit coupled to the I/O circuit to shunt an ESD current to ground, the ESD shunt circuit comprising: a low voltage ESD transistor having a source and a gate; a first high voltage ESD transistor coupled in series with the low voltage ESD transistor; a second high voltage ESD transistor coupled in series with the first high voltage ESD transistor; and a gate clamp circuit coupled to the low voltage ESD transistor to clamp a gate-to-source voltage of the low voltage ESD transistor, the gate clamp circuit having a low voltage output coupled to the gate of the low voltage ESD transistor and a ground reference coupled to the source of the low voltage ESD transistor, wherein the gate clamp circuit limits the low voltage output; and a trigger circuit coupled to the low voltage ESD transistor, wherein the trigger circuit is configured to trigger the ESD shunt circuit in response to an ESD event, wherein the trigger circuit is configured to maintain a bias voltage level applied to the first high voltage ESD transistor at a first voltage level during normal operation and to drive the bias voltage level to a second voltage level during the ESD event to operate the first high voltage ESD transistor as a resistive load, and wherein the first high voltage ESD transistor is configured to dissipate a sufficient portion of power caused by the ESD event to prevent an overstress of the low voltage ESD transistor.