Patent ID: 7099208

Claim:
A semiconductor memory comprising: a memory core having a plurality of normal memory cells and at least one redundancy memory cell relieving a defected normal memory cell; an internal request generator periodically generating an internal access request; a command input circuit receiving an external access request supplied through an external terminal; an arbiter judging which of said internal access request and said external access request takes higher priority, when said internal access request conflicts with said external access request; a core control circuit making said memory core carry out internal access operation and external access operation in response to each of said internal access request and said external access request; a redundancy judgement circuit carrying out redundancy judgement in order of priority judged by said arbiter in response to each of said internal access request and said external access request, said redundancy judgement judging which is to be accessed between one of said normal memory cells and said redundancy memory cell, and said redundancy judgement circuit carrying out redundancy judgement corresponding to said external access request during said internal access operation in response to said internal access request, when said arbiter gives higher priority to said internal access request than said external access request; and a hold circuit holding judged result by said redundancy judgement circuit in synchronization with the start of each of said internal and external access operation, and outputting said judged result to said memory core.