Patent ID: 7644331

Claim:
A test circuit, comprising: a delay line containing a plurality of delay elements; and a test interface circuit coupled to the delay line, the test interface circuit comprising a multiplexer circuit that includes at least one multiplexer, the multiplexer circuit configured to operate in one of a normal mode and a test mode, wherein in the normal mode of operation the multiplexer circuit is operable to route a first clock into the delay line for implementing a desired delay upon the first clock, and wherein in the test mode of operation, the multiplexer circuit is configured to provide an option for selecting and routing into the delay line one of: a) a test clock for generating a system clock having known timing parameters, or b) a first steady state signal, the first steady state signal selected to be one of a logic high level or a logic low level for placing the delay line in an all-ones or an all-zero condition respectively for carrying out one of a) a stuck-at-zero test or b) a stuck-at-one test of the delay line.