Patent ID: 8521968

Claim:
A memory controller providing a plurality of write ports that allow shared access to at least one memory device, the memory controller comprising: a plurality of write ports, at least one of the write ports having a clock frequency and comprising: a data buffer having a plurality of storage locations, wherein said data buffer is configured to allow data of a first bit width to be written to at least a first number of its storage locations at a pre-determined time; an address buffer having a plurality of address locations, the address buffer being configured to allow addresses to be written to a first number of its address locations; and an address translator configured to translate an address associated with data written to a storage location in the data buffer from an address space of the write port to an address space of at least one memory device, such that an address contained in a given address location in the address buffer relates to a memory address of at least one memory device to which data held in a corresponding storage location of the data buffer of the write port is to be written, wherein the write port is configured to determine if a plurality of translated addresses stored in the address buffer relate to a common memory address of the at least one memory device; wherein an arbiter having a clock frequency and configured to, responsive to a determination that a plurality of translated addresses stored in an address buffer relate to a common memory address of at least one memory device, read data of a second bit width, the second bit width being greater than the first bit width, from a second number of storage locations of a data buffer associated with said plurality of translated addresses at a pre-determined time and write the data that is read to said at least one memory device; wherein said data buffer is configured to allow data to be written to a first number of its storage locations during every clock cycle of the write port, and wherein said arbiter is configured to be able to read said data during every clock cycle of the arbiter, and wherein the second number of storage locations read by the arbiter, the clock frequency of the arbiter, the first number of storage locations written to said write ports and the clock frequency of said write port provide that the bandwidth of data read from said write port by the arbiter is greater than the bandwidth of data written to said write port.