Patent ID: 7910414

Claim:
A method of fabricating an array substrate, comprising: sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate where a pixel region and a switching region in the pixel region are defined, the first metal layer including a first metallic material layer and a second metallic material layer covering an upper surface of the first metallic material layer, wherein the first metallic material layer has a resistance and a melting point smaller than the second metallic material layer; crystallizing the intrinsic amorphous silicon into an intrinsic polycrystalline silicon layer; forming a gate electrode, a gate line connected to the gate electrode, a gate insulating layer and an active layer by patterning the intrinsic polycrystalline silicon layer, the first inorganic insulating layer and the first metal layer, the gate electrode, the gate insulating layer and the active layer positioned in the switching region; forming an interlayer insulating layer on the active layer and including first and second contact holes, the first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting both sides of the active layers through the first and second contact holes, a source electrode on the first ohmic contact pattern, a drain electrode on the second ohmic contact pattern, and a data line connecting the source electrode, the data line crossing the gate line to define the pixel region; forming a passivation layer on the source electrode, the drain electrode and the data line and including a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole.