Patent ID: 8913439

Claim:
A memory device comprising: a plurality of memory cells arranged in rows and columns; a plurality of main bit lines; a plurality of reference terminals; a plurality of local bit lines, wherein each column of the memory cells is associated with a respective local bit line and said plurality of local bit lines is divided into packets of local bit lines, each packet of local bit lines being associated with a respective one of said plurality of main bit lines, each of said plurality of local bit lines of each packet being selectively coupleable to its associated respective one of said plurality of main bit lines, and each local bit line being selectively coupleable to a respective one of said plurality of reference terminals for receiving a reference voltage via a corresponding discharge selector, wherein each discharge selector is active when the memory device is in a standby state; biasing circuitry configured to bias each main bit line to a pre-charge voltage during operation of the memory device; and reading circuitry configured to select and access a group of memory cells during a reading operation by at least selecting each local bit line associated with each memory cell of the group by activating a corresponding selector and disabling a corresponding discharge selector, and measuring currents flowing in the selected local bit lines for reading data stored in the memory cells of the group.