Patent ID: 7126959

Claim:
A high-speed packet memory having a write port and a read port, comprising: a plurality of N memory modules for storing fixed size cells which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells; a read-write control block for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at a memory address, the memory address being selected from a sub-set of N memory addresses, the addresses in the sub-set being related among the N memory modules according to a first relationship, and for retrieving each of said cells from the memory modules and sending said cells to the read port; a multi-cell pointer (MCP) storage for storing an MCP for each group of cells (the associated MCP), each MCP having N memory module identifiers to record the order in which said cells of said each group are stored in each of the selected different ones of the N memory modules; and the MCP being stored in the MCP storage at an MCP address which is related to one of the memory addresses in the sub-set of N memory addresses according to a second relationship.