Patent ID: 7960770

Claim:
A nonvolatile memory element array comprising a plurality of nonvolatile memory elements, each of the nonvolatile memory elements including: a lower electrode provided on a substrate; an upper electrode provided above the lower electrode; a resistance variable layer sandwiched between the lower electrode and the upper electrode; wherein the resistance variable layer includes a high-resistance layer and a low-resistance layer; wherein the resistance variable layer has a characteristic in which a resistance value of the resistance variable layer is increased or reduced by applying electric pulses between the lower electrode and the upper electrode; and wherein the resistance variable layer is connected to the upper electrode only at a portion of a main surface of the upper electrode or connected to the lower electrode only at a portion of a main surface of the lower electrode; and a first interlayer insulating layer provided on the substrate to cover the lower electrode, wherein a first contact hole is provided on the lower electrode to penetrate through the first interlayer insulating layer; wherein the low-resistance layer is provided inside the first contact hole such that low-resistance layers in adjacent nonvolatile memory elements are isolated from each other; and wherein the high-resistance layer is provided outside the first contact hole to have a size larger than a diameter of the first contact hole.