Patent ID: 8370101

Claim:
A high speed anti-radiation missile guided missile launcher test set circuit card assembly testing system comprising: a terminal computer for providing a platform for hosting a computer processor and a test software module; a user interface connected to said terminal computer for providing a set of user commands to control an operational test of said terminal computer; a plurality of bi-directional interfaces for connecting said terminal computer to a board test set; a data acquisition software module for controlling communications of a portion of said plurality of bi-directional interfaces wherein said data acquisition software module is in communication with said computer processor and said board test set; a data acquisition hardware module responsive to said data acquisition software module, said data acquisition hardware suite connected to said plurality of bi-directional interfaces and to said board test set; an emulator software module for replicating a behavior of a fielded central processing unit, wherein said behavior of the fielded central processing unit is controlled by said terminal computer wherein said emulator software module is in communication with said data acquisition software module, with said data acquisition hardware module and with said board test set when said emulator software module is active; and a card cage mounted onto said board test set for accepting a high speed anti-radiation missile guided missile launcher test set circuit card assembly, wherein said high speed anti-radiation missile guided missile launcher test set circuit card assembly is subjected to said operational test controlled by said user interface and said operational test resulting in a determination of a functional status of said high speed anti-radiation missile guided missile launcher test set circuit card assembly, wherein said functional status is reported to a user, wherein said high speed anti-radiation missile guided missile launcher set circuit card assembly has a total number of test access points built thereon, wherein said total number of test access points includes at least one external test access points not routed to a connector; and wherein said card cage is configured and mounted onto said board test set to provide direct probing accessibility to said at least one external test access points; wherein said high speed anti-radiation missile guided missile launcher test set circuit card assembly is external to said cage when said high speed anti-radiation missile guided missile launcher test set circuit card assembly is mounted to said card cage.