Patent ID: 8072242

Claim:
An apparatus; comprising: an output driver comprising: an output node, a first PMOS transistor having a source node coupled to a supply voltage, a second PMOS transistor having a source node coupled to a drain node of the first PMOS transistor and a drain node coupled to the output node, and a third PMOS transistor having a source node coupled to the supply voltage and a drain node coupled to the output node, and logic circuitry coupled to the output driver, the logic circuitry including one or more circuit elements arranged to enable the logic circuitry to be programmable to apply either: a predetermined reference voltage to a gate of the first PMOS transistor to operate the apparatus in a voltage-drive mode, or a bias voltage to the gate of the first PMOS transistor to operate the apparatus in a current-drive mode, wherein: the output driver is a first output driver; the apparatus further comprises a second output driver comprising a fourth PMOS transistor having a source node coupled to the supply voltage; the logic circuitry is coupled to the second output driver; the logic circuitry is further programmable to selectively apply the predetermined reference voltage to a gate of the fourth PMOS transistor to operate the apparatus in the voltage-drive mode; and the logic circuit is further programmable to selectively apply the bias voltage to the gate of the fourth PMOS transistor to operate the apparatus in the current-drive mode.