Patent ID: 7817075

Claim:
An apparatus for converting a MEMS inductive capacitance of a MEMS element into a digital signal, said apparatus comprising: a first-stage integral circuit including: an input module having an equivalent MEMS capacitor of said MEMS element, a first capacitor and a second capacitor, said equivalent MEMS capacitor having a first end connected to a first node and a second end connected to a second node, said first capacitor having a first end connected to said second node and a second end grounded, said second capacitor having a first end connected to said first node and a second end grounded; an integral circuit having a first integral capacitor and a first integral amplifier, said first integral amplifier having an inverted input end, a non-inverted input end and an output end, said first integral capacitor having a first end connected to said inverted input end and a second end connected to said output end, said non-inverted input end being grounded and said output end generating an output signal of said first-stage integral circuit; a reference circuit generating a first reference voltage, a low level reference voltage and a high level reference voltage; first, second, third, fourth and fifth switches, said second switch having a first end grounded and a second end connected to said first node, said third switch having a first end connected to said first node and a second end connected to said inverted input end of said first integral amplifier; a controller generating a first switch signal for controlling said first, second and fourth switches and a second switch signal for controlling said third and fifth switches, a high level of said first switch signal and a high level of said second switch signal being non-overlapping; a charge/discharge capacitor having a first end connected to said first node and a second end connected through said first switch to said high level reference voltage when said first switch signal is at high level and connected through said first switch to said low level reference voltage when said second switch signal is at high level; wherein said second node is connected through said fourth switch to said first reference voltage when said first switch signal is at high level, and said second node is connected through said fifth switch to ground when said second switch signal is at high level; a comparator; and at least a second-stage integral circuit; wherein said second-stage integral circuit receives said output signal of said first-stage integral circuit and generates an output signal to said comparator for generating said digital signal.