Patent ID: 8354340

Claim:
A method of manufacturing an electronic device, comprising: forming a first interconnect layer including an interconnect on a supporting substrate, the first interconnect layer being formed from a first resin having a first decomposition temperature, said forming said first interconnect layer including forming a first conductive via plug having sidewalls tapering along a first direction; removing said supporting substrate from said first interconnect layer, said removing said supporting substrate from said first interconnect layer including exposing an undersurface of the first interconnect layer by removing said supporting substrate and thereby exposing an undersurface of said first conductive via plug; and forming a second interconnect layer by a build-up process on the undersurface of said first interconnect layer after said supporting substrate is removed, said forming the second interconnect layer including forming a resin layer comprising a second resin having a second decomposition temperature lower than said first decomposition temperature with said resin layer contacting with the exposed undersurface of said first interconnect layer and extending to further outside than said first interconnect layer in plan view, forming a second conductive via plug in said resin layer so as to be connected to said first conductive via plug, said second conductive via plug having sidewalls tapering along a second direction different from said first direction, the second conductive via plug formed so as to extend into said first interconnect layer and to be connected to said first conductive via plug at a conductive interface buried within the first interconnect layer, and forming a build-up interconnect layer on an underside of said resin layer to form said second interconnect layer, wherein said second interconnect layer laterally extends beyond sides of said first interconnect layer.