Patent ID: 7786536

Claim:
A semiconductor device comprising a first p-type MIS transistor over a first active region of a semiconductor substrate, wherein the first p-type MIS transistor comprises: a first gate insulating film formed on the first active region; a first gate electrode formed on the first gate insulating film; a first side-wall insulating film formed on a side surface of the first gate electrode; a first p-type source/drain region in the first active region outside the first side-wall insulating film; a first contact liner film formed over the first active region to cover the first gate electrode and the first side-wall insulating film; a first interlayer insulating film formed on the first contact liner film; and a first contact plug formed to penetrate the first interlayer insulating film and the first contact liner film and reach the top surface of the first source/drain region, wherein the first contact liner film has a slit extending slantwise, around a corner at which the side surface of the first side-wall insulating film intersects the top surface of the first active region, from a corner located on the top surface of the first contact liner film toward a corner located on the bottom surface of the first contact liner film, and in the slit, the first interlayer insulating film is embedded.