Patent ID: 7989943

Claim:
A stacked semiconductor package comprising: a substrate having connection pads along an edge of an upper surface of the substrate; a plurality of semiconductor chip modules stacked together in a step wise manner, each semiconductor chip module including: a first semiconductor chip having first bonding pads placed along an edge of an upper surface of the first semiconductor chip wherein the upper surface of the first semiconductor faces the substrate and the first bonding pads are exposed such that the first bonding pads face-down towards the substrate; and a second semiconductor chip having second bonding pads placed along an edge of an upper surface of the second semiconductor chip and having a lower surface of the second semiconductor chip facing over a lower surface of the first semiconductor chip wherein the second bonding pads are exposed such that the second bonding pads face-up away from the substrate; a connection member having first terminals on a first surface and having second terminals on an opposing surface, the opposing surface of the connection member placed over the second semiconductor chip of an uppermost semiconductor chip module such that the second terminals are exposed and face-down towards the substrate and the first terminals are exposed and face-up away from the substrate; and conductive members including first conductive members that couple together the connection pads, the second bonding pads and the first terminals and second conductive members that couple together the second terminals of the connection member and the first bonding pads of the first semiconductor chip of each semiconductor chip module.