Patent ID: 7932138

Claim:
A method for manufacturing a thin film transistor, comprising forming an amorphous silicon thin film on an insulating substrate; crystallizing the amorphous silicon thin film to form a polycrystalline silicon thin film; supplying oxygen (O 2 ) gas or water (H 2 O) vapor to the surface of the polycrystalline silicon thin film to form an oxide film as a passivation film on the polycrystalline silicon thin film (first passivation); patterning the polycrystalline silicon thin film and the passivation film to transform the polycrystalline silicon thin film into an active layer; forming a gate insulating film over the polycrystalline silicon thin film and the passivation film; forming a gate electrode on the gate insulating film and dividing the polycrystalline silicon thin film into a channel region opposite to the gate electrode and first and second regions separated by the channel region; implanting a p-type or n-type dopant into the first and second regions to form source/drain regions; forming an interlayer insulating film over the gate electrode and the gate insulating film; etching the interlayer insulating film, the gate insulating film and the passivation film to form a first contact hole and a second contact hole in contact with the source and drain regions, respectively; supplying O 2 gas or H 2 O vapor to the upper surfaces of the source and drain regions to passivate the active layer (second passivation) after the step of forming the contact holes; and forming a source electrode and a drain electrode in contact with the source region and the drain region through the first and second contact holes, respectively.