Patent ID: 7492420

Claim:
A method of forming an array substrate for use in a liquid crystal display device, comprising: forming a gate electrode, a gate line and a gate pad electrode on a substrate, wherein all of the gate electrode, the gate line and the gate pad electrode have a double-layered structure including a first barrier metal layer and a first copper layer; applying heat to the double-layered gate electrode, line and pad electrode so as to form a first out-diffusion film covering and surrounding the first copper layer; forming a gate insulation layer on the substrate to cover the gate electrode, gate line and gate pad electrode which include the first barrier metal layer, the first copper layer and the first out-diffusion film; forming an active layer and an ohmic contact layer sequentially on the gate insulation layer and over the gate electrode; forming a data line, source and drain electrodes and a data pad electrode, wherein the data line is on the gate insulation layer and crossed the gate line, wherein the source and drain electrodes contact the ohmic contact layer, wherein the data pad electrode is disposed on the gate insulation layer, and wherein all of the data line, the source and drain electrodes, the capacitor electrode and the data pad electrode have a double-layered structure including a second barrier metal layer and a second copper layer; applying heat to the double-layered data line, source and drain electrodes and data pad electrode so as to form a second out-diffusion film that covers and surrounds the second copper layer; forming a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad electrode all of which have the second barrier metal layer, the second copper layer and the second out-diffusion film, wherein the passivation layer has a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad electrode, and a data pad contact hole exposing the data pad electrode; and forming a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer using a transparent conductive material.