Patent ID: 8280331

Claim:
A device for use with a clock signal, said device comprising: a divider arranged to receive the clock signal, operable to divide the clock signal and to output a divided clock signal; a delay portion operable to output a delayed signal based on the divided clock signal; and a duty cycle corrector operable to output a first signal based on the delayed signal and the divided clock signal; wherein said duty cycle corrector comprises an inverter, a first delay unit, a second delay unit and an AND gate; wherein said inverter is arranged to receive the clock signal and operable to output an inverted signal, wherein said first delay unit is arranged to receive the divided clock signal and the clock signal and to output a first delay signal, wherein said second delay unit is arranged to receive the divided clock signal and the inverted signal and to output a second delay signal, and wherein said AND gate is arranged to receive the first delay signal and the second delay signal and to output the first signal.