Patent ID: 7012285

Claim:
A semiconductor device comprising a field effect transistor (FET) having a gate electrode with a gate length of not more than 0.8 μm formed on a semiconductor substrate in which a buffer layer having an impurity concentration of at least 10 10 cm −3 and at most 10 14 cm −3 is formed in a semi-insulating semiconductor having at least 10 14 cm −3 and at most 10 16 cm −3 p-type or n-type impurities, and at least one active layer having a p-type or n-type impurity concentration of at least 10 15 cm −3 and at most 10 17 cm −3 is formed on the buffer layer, wherein n FETs are combined with each other, and when 1≦m≦n−1 (n and m are integers, n>1), a drain terminal of an m-th FET is connected to a source terminal of an (m+1)th FET, resistors are connected to the gate electrodes of all of the first to n-th FETs, and all of the other ends of the resistors are coupled to the same electric potential.