Patent ID: 7840831

Claim:
A phase correction circuit comprising: a phase corrector that is configured to generate skew-corrected first and second clock signals that correct a duty cycle of a first clock signal and a duty cycle of a second clock signal and correct phase skew between the first and second clock signals; a replication output buffer that is configured to receive replication data and to output the replication data in synchronization with the skew-corrected first and second clock signals; a phase detector that is configured to detect a phase error in data output from the replication output buffer and to generate a detection signal; and a controller that is configured to control the phase corrector in response to the detection signal, wherein the replication data has a predetermined pattern to correct the duty cycles of the first and second clock signals and the phase skew between the first and second clock signals, and wherein the replication output buffer comprises a multiplexer that is configured to multiplex the replication data in response to a plurality of signals including the skew-corrected first and second clock signals.