Patent ID: 7428178

Claim:
A memory circuit comprising at least one chain of at least three stages each having a data input, a data output, and a propagation control signal input for controlling propagation of information from the data input to the data output, each of the stages between the first stage and the last stage comprising: a first NMOS transistor having a source, a drain, and a gate connected to the propagation control signal input of the stage so as to receive a propagation control signal that controls propagation of information from the data input to the data output of the stage; and a second NMOS transistor having a source, a drain, and a gate connected to the data input of the stage, wherein the first and second NMOS transistors are serially connected between a first potential and a second potential, the common electrode of the transistors being connected to the data output of the stage, the data input of the stage is connected to the data output of a preceding one of the stages, and the data output of the stage is connected to the data input of a following one of the stages.