Patent ID: 8578315

Claim:
A computer-implemented method for scheduling parallel processing of computational loads for constraint regions of an integrated circuit design having associated placeable objects among a plurality of host processors of a computer system, comprising: first comparing a total number of the constraint regions in the design to a threshold number of regions by executing first instructions in the computer system; second comparing an average number of placeable objects per constraint region to a threshold number of objects per region by executing second instructions in the computer system; and based on said first comparing and said second comparing, selectively distributing placement computations for the constraint regions to different host processors of the computer system by (i) executing third instructions in the computer system to balance the constraint regions amongst the host processors without regard to the placeable objects, (ii) executing fourth instructions in the computer system to balance the placeable objects amongst the host processors without regard to the constraint regions, or (iii) executing fifth instructions in the computer system to balance both the placeable objects and the constraint regions amongst the host processors.