Patent ID: 7403208

Claim:
A programmable graphics processor for generating anti-aliased images utilizing a non-periodic jitter pattern that varies from pixel to pixel, comprising: a storage element configured to store programmed sub-pixel offset values, wherein the number of sub-pixel offset values stored is dependent on the resolution of the image to be displayed; an offset access unit coupled to the storage element, the offset access unit configured to read a portion of the sub-pixel offset values based on at least a portion of the coordinates of a pixel position; a sample computation unit configured to combine the pixel position and the portion of the programmed sub-pixel offset values, read from the storage element, dependent on the resolution of the image to be displayed to produce a jittered sub-pixel sample position for each and every sub-pixel sample cell within each pixel of an antialiased image so that the jitter pattern is effectively non-periodic, but is antialiased consistently from frame to frame, each sub-pixel offset value being either added to or subtracted from the pixel position coordinate to establish the sub-pixel sample position based on whether the sub-pixel sample position is in the left or right half of the cell; a rasterizer configured to produce sub-pixel coverage data associated with a fragment using the jittered sub-pixel sample positions; a shader configured to compute a depth value corresponding to the fragment depth at the pixel position; and a raster operations unit configured to produce sub-pixel depth values using the depth value corresponding to the fragment depth at the pixel position and the jittered sub-pixel sample positions.