Patent ID: 7580452

Claim:
A dynamic comparator system comprising: a first comparator comprising: a first input terminal configured to receive an input signal having amplitude level transitions representing data bit values; a second input terminal configured to receive a first threshold reference voltage V 2 at a first instant in time during a rising edge transition of said input signal; an output terminal that provides a comparator output signal having a rising edge transition in response to said input signal exceeding said first threshold reference voltage V 2 ; and a second comparator configured as a threshold reference voltage switch controller, said second comparator comprising: a first input terminal configured to receive said input signal; a second input terminal configured to receive a second threshold reference voltage V 4 that is higher in amplitude than said first threshold reference voltage V 2 ; and an output terminal that provides a switching control signal having an amplitude level transition in response to said input signal exceeding said second threshold reference voltage V 4 , said switching control signal used thereon to dynamically replace said first threshold reference voltage V 2 that is coupled into said second input terminal of said first comparator, with a third threshold reference voltage V 3 greater than said first threshold reference voltage V 2 , thereby reconfiguring said first comparator to operate upon a pre-distorted input signal provided thereafter at said first input terminal of said first comparator, for settling said comparator output signal into a steady state condition within a time delay corresponding to one data bit of said input signal.