Patent ID: 8189352

Claim:
A single stage inverter device, for converters of power from dc energy sources to an electric ac network or grid having at least one phase, of pulsation frequency ω grid , comprising switching means capable to periodically connect, with period T s lower than the period T grid corresponding to the pulsation frequency ω grid , a source, capable to output a voltage v g (t) of average value V g , to the grid so that the device output current i 0 (t) is in phase with the voltage v 0 (t) of at least one phase of the grid, the maximum value of which is V o,max , the switching means being controlled by controlling electronic means operating according to a control over a single switching cycle of the switching means, the device seeing an output inductance L, the device comprising a sensing resistor of resistance R s connected in series to the grid, the controlling electronic means comprising: a resettable integrator circuit having a time constant τ such that τ<T s , the input of which receives a voltage signal (V c −K g *V g ) equal to the difference between a control voltage V c and a voltage proportional by a first factor K g to the output voltage v g (t) of the source, comparator means, capable to output a signal indicative of the comparison of a voltage drop [R s ·i o (t)] on the sensing resistor with the sum of the output signal of the integrator circuit and a voltage [K·v o (t)] proportional by a second factor K to the voltage v 0 (t) of the grid, and generator means capable to receive the output signal from the comparator means and a signal indicative of the phase of the grid for providing one or more signals for controlling the switching means, the control voltage V c and the first factor K g being such as to fulfil the following first constraint: V c ≥ K g ⁢ V g + ( 2 ⁢ ⁢ V o , max - V g ) ⁢ R s ⁢ τ 2 ⁢ ⁢ L , wherein the device fulfils a second constraint whereby the input signal of the integrator circuit is always positive, and it fulfils a third constraint whereby, at any time instant, the input voltage of the switching means is higher than the output voltage thereof, and it fulfils a fourth constraint whereby K ⁡ ( 1 - P o ⁡ ( S ) α · P g , MPP ⁡ ( S max ) ) · ( 1 - γ ) ≤ V m V g ⁢ ❘ min ⁢ ≤ V m V g ⁢ ❘ max ⁢ ⁢ V m V g ⁢ ❘ min ⁢ ≤ V m V g ⁢ ❘ max ⁢ ≤ K ⁡ ( 1 - P o ⁡ ( S ) α · P g , MPP ⁡ ( S max ) ) · ( 1 + γ ) where: v m = ( V c - K g · v g τ ) · T s P o (S) is the device output average power for a set S of operation conditions, P g,MPP (S max ) is the maximum power deliverable by the source, α is a first coefficient of overload, with α≧1, and γ is a second coefficient, with γ<1.