Patent ID: 6924684

Claim:
A system comprising a phase shifter circuit, the phase shifter circuit comprising: an input clock terminal; an output clock terminal; an inverter having an input terminal coupled to the input clock terminal and an output terminal; a first counter circuit having a clock terminal coupled to the input clock terminal and a plurality of output terminals; a register having a plurality of data input terminals coupled to the output terminals of the first counter circuit, a clock terminal coupled to receive a clock update signal from the first counter circuit, and a plurality of output terminals; a second counter circuit having a clock start terminal coupled to the input clock terminal, a plurality of clock stop terminals coupled to the output terminals of the register, and an output terminal; a third counter circuit having a clock start terminal coupled to the output terminal of the inverter, a plurality of clock stop terminals coupled to the output terminals of the register, and an output terminal; and an output clock generator having a first input terminal coupled to the output terminal of the second counter circuit, a second input terminal coupled to the output terminal of the third counter circuit, and an output terminal coupled to the output clock terminal.