Patent ID: 7518578

Claim:
A demultiplexer for programming time-divided and secquentially input data currents to at least two signal lines, the demultiplexer comprising: first and second sample/hold circuits for sequentially sampling data currents to hold corresponding sampled data; and third and fourth sample/hold circuits for respectively sampling the data held by the first and second sample/hold circuits, the third and fourth sample/hold circuits programming the data currents which correspond to the sampled data to the two signal lines, respectively, wherein at least one of the first, second, third, and fourth sample/hold circuits each comprises: a transistor comprising a first terminal, a second terminal, and a third terminal, the first and second terminals controlling current flow to the third terminal from the second terminal according to a voltage difference between the first and second terminals; a first switch for coupling a first power source to the second terminal of the transistor in response to a first control signal; a second switch for transmitting a current to be sampled to the first terminal of the transistor in response to a second control signal; a third switch for diode-connecting the transistor in response to a third control signal; a capacitor coupled between the first and second terminals of the transistor, the capacitor for storing a voltage corresponding to the current to be sampled; a fourth switch for coupling a second power source to the third terminal of the transistor in response to a fourth control signal; and a fifth switch for holding and supplying a current which corresponds to the voltage stored in the capacitor to the second terminal of the transistor in response to a fifth control signal.