Patent ID: 7741898

Claim:
A charge pump circuit, with transistors of the MOSFET type each having source, drain and gate, being driven by a first set of control clock signals and a second set of control clock signals, comprising: a first circuit part with first through third transistors driven by said first set of control clock signals; a second circuit part with fourth through sixth transistors driven by said second set of control clock signals, both of said circuit parts together making up a first circuit stage of said charge pump circuit; the first circuit part comprising a first input and a first output terminal having their respective voltages at said terminals, also comprising said first transistor connecting said first input and output terminals, said second transistor linked between said first input terminal and the gate of said first transistor thus defining a first node including said gate, its own gate however tied to a second node which itself is connecting to said sixth transistor and a third transistor connected with its gate to said first node and itself connecting again to said first input terminal and leading to another node within the second circuit part later on introduced and named as fourth node, the second circuit part comprising a second input and a second output terminal having their respective voltages at said terminals, also comprising said fourth transistor connecting said second input and output terminals, said fifth transistor linked between said second input terminal and the gate of said fourth transistor thus defining a third node including said gate, its own gate however tied to a fourth node which itself is connecting to said third transistor within the first circuit part, and said sixth transistor connected with its gate to said third node and itself connecting again to said second input terminal and leading to said second node within the first circuit part; and wherein the transistors are implemented as isolated MOSFET components within an Integrated Circuit (IC) realization of said charge pump circuit implementing each transistor structure as completely buried within their own bulk regions enclosed in an isolated well separated from its substrate thus allowing to electrically isolate all bulk regions for each component from the potential of the substrate of the IC realization of said charge pump circuit by using separate bulk and substrate electrodes connected to said bulk regions and said substrate respectively and whereto first and second predetermined voltage levels are respectively defined as reference values, such that the gate oxide stress for the buried MOSFET transistors is relaxed during operation.