Patent ID: 7268437

Claim:
A semiconductor package with an encapsulated passive component comprising: a substrate having a surface, the substrate comprising: a solder mask formed on the surface of the substrate and having at least an opening; a first pad formed on the surface of the substrate and having an upper surface and a sidewall, wherein the upper surface of the first pad is partially exposed out of the opening, the sidewall of the first pad is partially covered by the solder mask; a second pad formed on the surface of the substrate and having an upper surface and a sidewall, wherein the upper surface of the second pad is partially exposed out of the opening, the sidewall of the second pad is partially covered by the solder mask; and a blocking bar formed between the first pad and the second pad; wherein the first pad has an exposed sidewall portion exposed out of the opening, a first flowing channel is formed between the blocking bar and the exposed sidewall portion of the first pad; a passive component mounted on the surface of the substrate, wherein the first flowing channel is located under the passive component; a plurality of solder pastes connecting the passive component with the first pad and the second pad; a chip disposed on the surface of the substrate; and a molding compound formed on the surface of the substrate, the molding compound sealing the chip and the passive component and filling the first flowing channel, wherein the blocking bar and the solder mask are integrally formed, made of a same material and formed at the same time, wherein the blocking bar and the exposed sidewall portions of the first pad are longer than the width of the passive component.