Patent ID: 8145458

Claim:
A method of automatically evaluating stress upon discrete analog components embedded in a digital electronic circuit design of a Printed Circuit Board (PCB) comprising: (a) establishing a circuit definition of the digital electronic circuit design of a PCB stored in a computer readable form; (b) partitioning said circuit definition into a plurality of circuit portions; (c) re-defining said circuit portions to form a plurality of analog topologies adapted for automatic independent analog simulation, including selectively making substitutions for digital components in each said circuit portion with at least one subcircuit incorporating a corresponding instantiation of an input output (IO) buffer model; (d) executing said automatic analog simulation upon said analog topologies in a computer based unit to generate simulated results data; and, (e) automatically postprocessing the simulated results data to generate worst-case stress measurement data for one or more critical components identified in said analog topologies.