Patent ID: 7413943

Claim:
A method of forming a gate of a fin type transistor, the method comprising: forming hard masks that mask first portions of a substrate and that expose second portions of the substrate, the hard masks defining active regions of the substrate; forming a first device separation layer on the second portions of the substrate; recessing the first device separation layer to expose sidewalls of the active regions; forming a second device separation layer filling the recessed portions, thereby forming a device isolation region including the first device separation layer and the second device separation layer; forming sidewall protection layers on sidewalls of the protruding active regions prior to forming the second device separation layer, wherein the sidewall protection layers include an insulation material with a specific etch selectivity with respect to an insulation material included in the device isolation region; selectively etching portions of the device isolation region while protecting the active regions using the hard masks and the sidewall protection layers to form a plurality of recesses crossing the device isolation region; selectively removing the hard masks and portions of the sidewall protection layers exposed by the recesses; and forming gate dielectric layers and gates filling the recesses and crossing the active regions.