Patent ID: 7642869

Claim:
A clock generator comprising a ring oscillator including an odd number of inverter gates connected in a circular chain and for outputting a basic signal from one of the inverter gates; a frequency divider circuit for dividing the basic signal by one of a first division ratio and a second division ratio, the first division ratio allowing the frequency divider circuit to generate a first clock signal having a target frequency, the second division ratio allowing the frequency divider circuit to generate a second clock signal having a different frequency than the target frequency; a first counter circuit for counting the number of pulses of the basic signal for a first predetermined period of time, the first counter circuit outputting a first count value indicative of the number of pulses counted for the first predetermined period of time; a second counter circuit for counting the number of pulses of the basic signal for a second predetermined period of time, the second counter circuit outputting a second count value indicative of the number of pulses counted for the second predetermined period of time; a calculator for calculating the first division ratio based on the first count value outputted from the first counter circuit; and a setting circuit for selecting one of the first division ratio and the second division ratio based on a temperature of the ring oscillator, the temperature being estimated from the second count value outputted from the second counter circuit, the setting circuit setting the selected one of the first division ratio and the second division ratio in the frequency divider circuit.