Patent ID: 7662681

Claim:
A method for fabricating a reverse-staggered polycrystalline silicon thin film transistor comprising the steps of: forming a buffer layer made of a phosphosilicate-spin-on-glass (P-SOG) on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film made of a phosphosilicate-spin-on-glass (P-SOG) on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer; wherein the step of crystallizing the amorphous silicon layer into a polycrystalline silicon layer includes the sub-steps: forming a cap layer on the amorphous silicon layer; depositing a metal film on the cap layer; and subjecting the amorphous silicon layer to metal-induced crystallization.