Patent ID: 6867460

Claim:
An electronic device comprising: a semiconductor device comprising: a pass gate transistor including a first fin body and a first gate, said first fin body having opposing sidewalls, each sidewall aligned in a first direction having a first majority carrier mobility, said first gate adjacent to both sidewalls or said first fin body; a pull down latch transistor including a second fin body and a second gate, said second fin body having opposing sidewalls, each sidewall aligned in a second direction having a second majority carrier mobility, said second gate adjacent to both sidewalls of said second fin body; a pull up latch transistor including a third fin body and a third gate, said third fin body having opposing sidewalls, each sidewall aligned in a third direction having a third majority carrier mobility, said third gate adjacent to both sidewalls of said third fin body; wherein all of said first, second and third directions are not the same direction; and one or more CMOS chevron logic circuits, crystal planes of bodies of transistors of said CMOS chevron logic circuits and crystal planes of said first, second and third fin bodies co-aligned.