Patent ID: 8060755

Claim:
An apparatus for performing cryptographic operations, comprising: an x86-compatible microprocessor, comprising: an instruction register within a x86-compatible microprocessor having a single, atomic cryptographic instruction disposed therein wherein said single, atomic cryptographic instruction prescribes that a user-generated key schedule be employed for execution of an encryption operation, and wherein said encryption operation that is prescribed by said single, atomic cryptographic instruction comprises encryption of a plurality of plaintext blocks to generate a corresponding plurality of ciphertext blocks; a keygen unit, operatively coupled to said instruction register, configured to direct said x86-compatible microprocessor to load said user-generated key schedule; and an execution unit, operatively coupled to said keygen unit, configured to employ said user-generated key schedule to execute said encryption operation, said execution unit comprising: a cryptography unit, configured execute a plurality of cryptographic rounds on each of a plurality of input text blocks to generate a corresponding each of a plurality of output text blocks, wherein said plurality of cryptographic rounds are prescribed by a control word that is provided to said cryptography unit, wherein said cryptography unit executes a first plurality of micro instructions generated by translation of said single, atomic cryptographic instruction: and an x86 integer unit, an x86 floating point unit, an x86 MMX unit, and an x86 SSE unit, wherein said cryptography unit operates in parallel with said x86 integer unit, said x86 floating point unit, said x86 MMX unit, and said x86 SSE unit, to accomplish said encryption operation, wherein said x86 integer unit executes a second plurality of micro instructions generated by said translation to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of said plurality of cryptographic rounds.