Patent ID: 8489819

Claim:
A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising: in response to a data request, selecting a victim cache line to be castout from the first lower level cache; selecting a target lower level cache of one of the plurality of processing units other than the first processing unit based upon architectural proximity of the target lower level cache to a home system memory to which an address of the victim cache line is assigned; the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination of the victim cache line; and in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache, wherein the first and second lower level caches are at a same cache hierarchy level.