Patent ID: 7324377

Claim:
A method, comprising: providing a virtual ground array of nitride read only memory cells without isolation regions between cells, wherein the array of cells are arranged in a substrate according to rows and columns, each cell in the array comprising: a source; a drain; a channel formed between the source and the drain; a first isolating layer formed above the channel; a charge trapping layer formed above the first isolating layer, the charge trapping layer having a first data region and a second data region; a second isolating layer formed above the charge trapping layer; and a gate formed above the second isolating layer; wherein the gates of cells in each row are coupled to a common word line, the source of each cell in a row is configured to coincide with the drain of an adjacent cell in the row, the sources of cells in a column are connected to form a common bit line; selecting a cell in the array; and erasing or programming the first data region in the selected cell while all bit lines, excluding bit lines that are connected to the selected cell and one or more cells adjacent to the selected cell, are floated, wherein the second data region in the selected cell is not erased or programmed and no data region in any unselected cell in the array is erased or programmed.