Patent ID: 7337334

Claim:
A method of controlling power state of multiple processing elements in a network processor embedded in a semiconductor chip, wherein each of the processing elements has its own characteristic power and performance curve, and at least some of the processing elements are clocked, comprising the steps of: providing each of the processing elements with a usage indication signal; using a programmable power management state machine to monitor the utilization of each of the processing elements using said usage indication signal and to output an access density signal to a storage location in a ring buffer; and utilizing said state machine and a state control algorithm to control the power state of each of the processing elements based upon its past usage and predicted future utilization, wherein the performance recovery time which is associated with each of the clocked processing elements and which specifies the time required to switch between a low power state and a higher power state, is factored into the step of controlling the power state of the respective processing element.