Patent ID: 7768128

Claim:
An integrated circuit memory device comprising: an integrated circuit substrate; a plurality of lower wiring lines on the substrate and extending in a first direction; a first interlayer insulating layer on the plurality of lower wiring lines; an upper damascene wiring line in an upper portion of the interlayer insulating layer and extending to an upper surface of the interlayer insulating layer and extending in a second direction, different from the first direction, to extend over the plurality of lower wiring lines, the upper damascene wiring line having a main region and protruded regions extending therefrom in a direction different from the second direction, the protruded regions extending over respective underlying ones of the lower wiring lines; a first via extending through the first interlayer insulating layer under a first of the protruded regions and connecting the upper damascene wiring line to a corresponding underlying first one of the plurality of lower wiring lines; a second via extending through the first interlayer insulating layer under a second of the protruded regions and connecting the upper damascene wiring line to a corresponding underlying second one of the plurality of lower wiring lines; a first active region in the integrated circuit substrate; a second active region in the integrated circuit substrate, the second active region having a type different from a type of the first active region; a gate electrode on the integrated circuit substrate that intersects the first active region and the second active region; a second interlayer insulating layer on the substrate in a region including the gate electrode and extending over the gate electrode, wherein the plurality of lower wiring lines and the first insulating layer are on the second insulating layer; and a via extending through the second interlayer insulating layer that connects the first one of the plurality of lower wiring lines to the gate electrode, wherein the first via extending through the first interlayer insulating layer is displaced further from the main region of the upper damascene wiring line than the via extending through the second interlayer insulating layer.