Patent ID: 7466595

Claim:
A circuit for reading at least one semiconductor memory cell connected to a bit line, including: at least one first reference line; a first control transistor for controlling the bit line; a second control transistor for controlling the at least one first reference line; a current mirror circuit including: at least one first reference transistor connected to the at least one first reference line by means of the second control transistor; and a write transistor of a current fixed by the at least one first reference transistor connected to the bit line by means of the first control transistor, wherein the current mirror circuit makes it possible to compare, during a memory reading phase, a discharge current of the bit line and a discharge current of the at least one first reference line; a first intermediate transistor, a gate of which is connected to a fixed potential, connected to the write transistor in parallel to the first control transistor; and a second intermediate transistor, a gate of which is connected to the same fixed potential, connected to the at least one first reference transistor in parallel to the first control transistor by being inserted between a gate and a drain of the at least one first reference transistor, with first and second polarization transistors, gates of which are connected to the same polarization potential, connected in series to the first and second intermediate transistors, respectively, enabling a constant polarization current to be superimposed on the current fixed by the at least one first reference transistor.