Patent ID: 7426583

Claim:
A method for decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges, wherein the plurality of local ranges are associated with a plurality of local memory devices coupled to a local bus and the plurality of peripheral ranges are associated with a plurality of peripheral devices coupled to a peripheral bus, the method comprising: determining decoder address bits of the address space that distinguish the local ranges from each other and that distinguish the local ranges from the peripheral ranges, wherein the local and peripheral ranges are interleaved and have a plurality of sizes, and a number of the decoder address bits is less than a number of address bits in the address space and less than a quantity that is a number of the local ranges plus a number of the peripheral ranges; issuing a first transaction with an input address on the local bus and simultaneously issuing a second transaction with the input address on the peripheral bus; determining, in response to the decoder address bits of the input address, whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges and any of the local ranges other than the one of the local ranges; and aborting processing of the transaction by the plurality of peripheral devices in response to the determining that the input address is within a portion of the address space that includes the one of the local ranges and does not include any of the peripheral ranges.