Patent ID: 7977709

Claim:
A MOS transistor, comprising: a semiconductor layer comprising a first source/drain region, a second source/drain region, and a channel region disposed between the first source/drain region and the second source/drain region; a gate structure disposed over the channel region; a first wiring structure disposed over the first source/drain region and electrically connected to the first source/drain region, the first wiring structure having a height and a width, the first wiring structure conducting a current in or a current out of only the first source/drain region; and a second wiring structure disposed over the second source/drain region and electrically connected to the second source/drain region, the second wiring structure having a height and a width, the second wiring structure conducting a current in or a current out of only the second source/drain region, wherein the width of a portion of the first wiring structure directly adjacent to and directly physically connected to the first source/drain region is larger than the width of a portion of the second wiring structure directly adjacent to and directly physically connected to the second source/drain region, and wherein the height of the first wiring structure is smaller than the height of the second wiring structure.