Patent ID: 7236411

Claim:
A programmable device comprising: a plurality of programmable logic cells adapted to perform a function specified by configuration data; a memory unit adapted to store data used by the plurality of programmable logic cells; a configurable switching circuit adapted to communicate signals at least among the plurality of programmable logic cells and the memory unit; and a configuration memory adapted to store configuration data specifying at least a portion of the characteristics of the programmable device, wherein the configuration data includes memory access parameter data; wherein the memory unit comprises: a memory array adapted to store the data; a first programmable delay unit adapted to receive a first signal and to delay the first signal for a time period specified by at least a first portion of the memory access parameter data; and a first component connected with an output of the first programmable delay unit and adapted to facilitate access to the data stored by the memory array in response to the delayed first signal from the output of the first programmable delay unit.