Patent ID: 7932105

Claim:
A method of characterizing a Nickel-silicide semiconductor manufacturing process comprising: accessing a test chip comprising a parallel coupled chain of transistors, wherein said transistors are designed for inducing stress into Nickel-silicide features of said transistors, and for increasing a probability of a manufacturing failure of said Nickel-silicide features; applying a biasing voltage to one terminal of said parallel coupled chain; grounding all other terminals of said parallel coupled chain; measuring current at each of said all other terminals of said parallel coupled chain; repeating said applying, grounding and measuring for each terminal of said parallel coupled chain; comparing measured currents from all possible conduction paths to determine a manufacturing defect in said parallel coupled chain of transistors; changing a process parameter of said Nickel-silicide semiconductor manufacturing process; and repeating said accessing, said applying, said grounding, said measuring, said repeating said applying, grounding and measuring and said comparing.