Patent ID: 8018951

Claim:
A method for pacing a data transfer between compute nodes on a parallel computer, the method further comprising: transferring, by an origin compute node, a chunk of an application message to a target compute node; sending, by the origin compute node, a pacing request to a target direct memory access (‘DMA’) engine on the target compute node using a remote get DMA operation, wherein the pacing request further comprises a pacing response data descriptor that specifies a pacing packet header for a memory first-in-first-out (‘FIFO’) data transfer from the target compute node to the origin compute node; determining, by the origin compute node, whether a pacing response to the pacing request has been received from the target DMA engine, wherein determining whether a pacing response to the pacing request has been received from the target DMA engine further comprises: receiving, by an origin DMA engine on the origin compute node from the target DMA engine in a reception FIFO for the origin DMA engine, a pacing packet having the pacing packet header specified by the pacing response data descriptor in the pacing request, and executing, by an origin processing core on the origin compute node, a pacing packet handler specified in the pacing packet header; and transferring, by the origin compute node, a next chunk of the application message if the pacing response to the pacing request has been received from the target DMA engine.