Patent ID: 8253479

Claim:
An output driver circuit comprising: a first NMOS transistor having a first terminal directly connected to a first power supply voltage, a second terminal directly connected to at least one external load circuit, and a control terminal, wherein the first NMOS transistor conducts a load current; and a second NMOS transistor having a first terminal directly connected to a first biasing current terminal and the control terminal of the first NMOS transistor, a second terminal coupled to receive an external constant input voltage reference and directly connected to a second biasing current terminal, and a control terminal; a third NMOS transistor having a control terminal directly connected to the control terminal of the second NMOS transistor, a first terminal coupled to a third biasing current terminal and the control terminal of the second NMOS transistor, and a second terminal directly connected to the second terminal of the first NMOS transistor and directly connected to a fourth biasing current terminal, wherein the second and third NMOS transistors and the biasing current terminals are configured as a low-frequency voltage follower circuit that regulates the output voltage of the output driver circuit; and the first NMOS transistor is configured as a first order gain stage high frequency feedback loop for the output driver circuit.