Patent ID: 7095083

Claim:
A circuitry module, comprising: a plurality of dies, wherein at least one die includes a memory device; a plurality of leads coupled to the plurality of dies to provide unilateral or bilateral communication and control, wherein the memory device includes first and second transistors in a periphery that are made from a method that includes: forming from a nonconductive stack a first trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line of the first transistor having a p-type strip adjoining an n-type strip and a second trench that exposes a nonconductive layer of a gate structure of the second transistor, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the first and second trenches; and filling the first and second trenches with conductive stacks to strap the dual-doped polycrystalline silicon line of the first transistor and to provide a conductive path overlying the gate structure of the second transistor, the first trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.