Patent ID: 6892269

Claim:
A nonvolatile memory device comprising: a memory core; an input address buffer; a first internal address bus connected to said input address buffer; a memory address bus connected to said memory core and to said first internal address bus; input and output data buffers; a data bus connected to said memory core and to said input and output data buffers; an input/output data management circuit connected to said data bus; a second internal data bus connected to said input/output data management circuit for transferring data on said data bus through said input/output data management circuit; a serial/parallel state machine connected to said second internal data bus and to said memory address bus, said serial/parallel state machine having inputs for receiving a clock signal and an external timing signal, and outputs for providing an internal write enable signal to said input data buffer when the nonvolatile memory device is functioning in a serial mode, an internal output enable signal to said output data buffer for data read from said memory core when the nonvolatile memory device is functioning in the serial mode, and a third signal for timing loading of addresses on said memory address bus during the nonvolatile memory device functioning in the serial mode, and for timing transfer and storage of addresses during the nonvolatile memory device functioning in a parallel mode; and circuit means having a first input for receiving the third signal and a second input for receiving an external mode command signal, and an output connected to said first internal address bus for selecting operation of the nonvolatile memory device functioning in the serial or parallel mode based upon the external mode command signal by interrupting the path of addresses from said first internal address bus to said memory address bus when the nonvolatile memory device is functioning in the serial mode.