Patent ID: 8298862

Claim:
A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip; at least one of the plurality of layer portions further includes a plurality of electrodes that are electrically connected to the semiconductor chip and that each have an end face located in the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is electrically connected to the end faces of the plurality of electrodes, the method comprising the steps of: fabricating a plurality of substructures each of which includes an array of a plurality of preliminary layer portions, each of the preliminary layer portions being intended to become any one of the layer portions included in the main body, the substructures being intended to be cut later at a position of a boundary between every adjacent preliminary layer portions; fabricating a layered substructure by using the plurality of substructures, the layered substructure including the plurality of substructures stacked; and producing the plurality of layered chip packages by using the layered substructure, wherein: the layered substructure includes a plurality of pre-separation main bodies arranged in a plurality of rows, the plurality of pre-separation main bodies being intended to be separated from each other later into individual main bodies; the plurality of rows of the pre-separation main bodies in the layered substructure include a plurality of types of rows that include respective different numbers of pre-separation main bodies, the numbers being no smaller than three; the step of producing the plurality of layered chip packages includes the steps of: forming a plurality of blocks by cutting the layered substructure, each of the plurality of blocks including a row of a plurality of pre-separation main bodies; forming the wiring on the plurality of pre-separation main bodies included in each of the blocks simultaneously; and separating the plurality of pre-separation main bodies each provided with the wiring from each other so as to form the plurality of layered chip packages; and each of the plurality of blocks formed by cutting the layered substructure includes a row of three, four, or five pre-separation main bodies, the plurality of blocks including at least one block that includes three pre-separation main bodies, at least one block that includes four pre-separation main bodies, and at least one block that includes five pre-separation main bodies.