Patent ID: 8020120

Claim:
A system for assessing and enforcing layout quality in terms of uniformity of gate lengths derived from wafer shapes in very large scale integrated chip (VLSI) design, the system comprising: a processor configured for: receiving as input a layout of a VLSI chip; obtaining a description of a plurality of gates on the layout, comprising obtaining a threshold value for a predetermined uniformity of gate length; and obtaining a description of process variability specifying process conditions; a shape processor configured for obtaining wafer shapes to compute gates over the layout for each process point in a process window; the processor further configured for: describing the layout by measuring the device dependent electrically-equivalent gate lengths of said plurality of gates from their corresponding wafer shapes; measuring the device dependent electrically-equivalent gate lengths of said plurality of gates from their corresponding wafer shapes that are equivalent with respect to device off-current; determining any gate within said plurality of gates that violates the predetermined uniformity of gate length threshold; and flagging the gates that violate the threshold as outliers, wherein the flagging comprises placing a marker on the layout where the outlier is located; and a tool for generating a histogram of gate lengths across the layout and across the process window, wherein a number and magnitude of the violation serves as a layout quality gauge.