Patent ID: 7852119

Claim:
An SR flip-flop comprising: a first lower terminal to which a first lower voltage is to be applied; a first upper terminal to which a first upper voltage is to be applied, which forms a pair with the first lower voltage; a second lower terminal to which a second lower voltage is to be applied; a second upper terminal to which a second upper voltage is to be applied, which forms a pair with the second lower voltage; a set terminal to which a set signal is to be input; a reset terminal to which a reset signal is to be input; a cross-coupled inverter arranged between the second lower terminal and the second upper terminal, and configured including a first inverter and a second inverter cross-coupled such that an output terminal of each inverter is connected to an input terminal of the other inverter; a set unit configured including a first set transistor and a second set transistor configured as N-channel MOSFETs arranged in series between the first lower terminal and the input terminal of the first inverter, and a third set transistor and a fourth set transistor configured as P-channel MOSFETs arranged in series between the input terminal of the second inverter and the first upper terminal, and configured such that the set signal is input to the gate of the first set transistor, and the signal complementary to the set signal is input to the gate of the fourth set transistor; and a reset unit configured including a first reset transistor and a second reset transistor configured as N-channel MOSFETs arranged in series between the first lower terminal and the input terminal of the second inverter, and a third reset transistor and a fourth reset transistor configured as P-channel MOSFETs arranged in series between the input terminal of the first inverter and the first upper terminal, and configured such that the reset signal is input to the gate of the first reset transistor, and the signal complementary to the reset signal is input to the gate of the fourth reset transistor, wherein the gate of the second set transistor and the gate of the third reset transistor are connected to the output terminal of the second inverter, and wherein the gate of the third set transistor and the gate of the second reset transistor are connected to the output terminal of the first inverter.