Patent ID: 7134000

Claim:
An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture, comprising: a current instruction buffer and a next instruction buffer in a pipeline stage n; an aligned instruction buffer in a pipeline stage n+1; instruction fetch logic for loading instructions into the current instruction buffer from a memory or from the next instruction buffer and for loading instructions into the next instruction buffer from the memory; and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer, wherein the alignment control logic comprises predecoders for predecoding the instructions to provide instruction length information, instruction length registers for holding the predecoded instruction length information, one instruction length register corresponding to each register in the current instruction buffer, and pointer generation logic responsive to the instruction length information for generating a current instruction pointer for controlling transfer of instructions from the current instruction buffer and, if necessary, from the next instruction buffer to the aligned instruction buffer, wherein the pointer generation logic includes next pointer selection logic for selecting a next instruction pointer from the instruction length registers in response to the current instruction pointer, and current pointer selection logic for selecting the current instruction pointer from the next instruction pointer, wherein the current pointer selection logic comprises a status latch containing a status bit that is set when low order bits of the next instruction pointer are zero and selection logic for selecting upper order bits of the next instruction pointer as the current instruction pointer when the status bit is set.