Patent ID: 7924086

Claim:
A boosting circuit having backflow preventing cells arranged in M parallel sequences (M≧4), the backflow preventing cells performing a boosting operation in synchronization with a plurality of clock signals having different phases, wherein the backflow preventing cell provided in a K-th sequence (1≦K≦M), includes: an input terminal for receiving a voltage from a stage preceding the backflow preventing cell; an output terminal for supplying a voltage to an output terminal of the booting circuit; an intermediate terminal for supplying a voltage to another backflow preventing cell; a charge transfer unit provided between the input terminal or the output terminal, and the intermediate terminal; a boosting capacitance having two ends, one end being connected to the intermediate terminal of the backflow preventing cell, and the other end receiving a clock signal corresponding to the backflow preventing cell; a charge transfer transistor connected between the input terminal and the output terminal of the backflow preventing cell, and for transferring charges from the input terminal to the output terminal when the charge transfer transistor is in a conductive state; and a state control unit for controlling the charge transfer transistor, depending on an intermediate terminal voltage of a backflow preventing cell in a KA-th sequence (KA=(K−A) when (K−A)>0, and KA=(M−|K−A|) when (K−A)≦0) located A sequences before the K-th sequence (1≦A≦M/2−1: A is a natural number).