Patent ID: 7779240

Claim:
A data processor having a clustered architecture that comprises an instruction cache and a plurality of clusters, each cluster comprising an instruction execution pipeline, each instruction execution pipeline comprising a plurality of processing stages, each processing stage capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters, the data processor comprising: a power-down controller capable of monitoring each instruction execution pipeline and the instruction cache to identify one or more power-down conditions associated therewith, wherein the power-down controller is also capable of: (i) bypassing performance of at least a portion of subsequent ones of the processing stages associated with an executing instruction; (ii) powering down the instruction cache; and (iii) powering down the data processor, and wherein the power-down controller, in response to an identified power-down condition, is further capable of at least one of: (i) bypassing performance of at least the portion of subsequent ones of the processing stages associated with the executing instruction; (ii) powering down the instruction cache; and (iii) powering down the data processor.