Patent ID: 7847379

Claim:
A through-silicon via stack package comprising: at least two package units stacked upon each other wherein the top package unit among any two stacked package units is referred to as “the upper stacked package unit” and wherein the lower package unit among any two stacked package units is referred to as “the lower stacked package unit,” each package unit comprising: a semiconductor chip having an upper surface and a lower surface; at least one through-silicon via formed between the upper surface and the lower surface of the semiconductor chip, wherein each through-silicon via is filled with a conductive material; a first metal line formed at least on a portion of the upper surface of the semiconductor chip to be brought into contact with a portion of the conductive material filled in the through-silicon via; and a second metal line formed at least on the lower surface of the semiconductor chip to be brought into contact with a portion of the conductive material filled in the through-silicon via, wherein one upper stacked package unit and one lower stacked package unit are stacked such that the second metal line formed on the lower surface of the upper stacked package unit contacts the conductive material filled in the through silicon via of the lower stacked package unit, wherein the first metal line formed on the upper surface of the lower stacked package unit contacts the conductive material filled in the through-silicon via of the upper stacked package unit, and wherein the first metal line formed on the upper surface of the lower stacked package unit is fitted with the second metal line formed on the lower surface of the upper stacked package unit such that the first and second metal lines are co-planar.