Patent ID: 8261120

Claim:
An apparatus, comprising: a clock integrated circuit, comprising: a timing circuit having an output alternating between a first reference signal and a second reference signal at a rate determined by a time constant determining timing of a clock signal output of the clock integrated circuit, the second reference signal including a varying noise signal; clock power and reference circuitry having the varying noise signal, the clock power and reference circuitry generating the second reference signal with a first version of the varying noise signal, the clock power and reference circuitry generating a level switching reference signal with a second version of the varying noise signal, the first version of the varying noise signal synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal; and a level switching circuit comparing an output of the timing circuit with the level switching circuit reference signal, an output of the level switching circuit determining the clock signal output of the clock integrated circuit.