Patent ID: 7193914

Claim:
An open digit line array architecture, comprising: a first plurality of sense of amplifiers, each sense amplifier of the first plurality coupled to a first digit line of a first memory sub-array and a second digit line of a second memory sub-array; a second plurality of sense amplifiers, each sense amplifier of the second plurality coupled to a first digit line of the first memory sub-array and a second digit line of a third memory sub-array; a common reference line; a first voltage supply line coupled to the sense amplifiers of a first group of sense amplifiers of the second plurality of sense amplifiers; a first voltage supply switch having a first node coupled to the first voltage supply line and a second node, the first voltage supply switch configured to couple the first voltage supply line to a voltage applied to the second node; a second voltage supply line coupled to the sense amplifiers of a second group of sense amplifiers of the second plurality of sense amplifiers; a second voltage supply switch having a first node coupled to the second voltage supply line and a second node, the second voltage supply switch configured to couple the second voltage supply line to a voltage applied to the second node a first plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the first plurality of sense amplifiers and further coupled to the common reference line, each switch configured to selectively couple the respective first digit line to the common reference line; and a second plurality of switches coupled to a respective one of the first digit lines of the first group of sense amplifiers of the second plurality of sense amplifiers and the common reference line, the second plurality of switches configured to selectively couple the respective first digit lines to the common reference line; and a third plurality of switches coupled to a respective one of the first digit lines of the second group of sense amplifiers of the second plurality of sense amplifiers and the common reference line, the second plurality of switches configured to selectively couple the respective first digit lines to the common reference line.