Patent ID: 8086814

Claim:
A semiconductor integrated circuit apparatus comprising: a first function block that comprises an internal memory storing an operation program and a processor that performs the operation program; a second function block that comprises a first clock generation circuit including a first phase locked loop circuit; and a third function block that comprises a second clock generation circuit including a second phase locked loop circuit, wherein: the internal memory stores, in a form of a program, work contents of the second and third function blocks, an operating frequency for executing each of the work contents in a predetermined time, a power supply voltage that operates the second and third function blocks at the operating frequency, and a frequency division ratio of a phase locked loop to set in the first and second clock generation circuits so that the second and third function blocks operate at the operating frequency; when the work content of the second function block is determined, the processor directs a power regulator to supply a necessary power supply voltage to the second function block with reference to the operation program stored in the internal memory, and sets the frequency division ratio of the phase locked loop in the first clock generation circuit of the second function block so that the second function block operates at the operating frequency of the work content; when the work content of the third function block is determined, the processor directs the power regulator to supply a necessary power supply voltage to the third function block with reference to the program stored in the internal memory, and sets the frequency division ratio of the second phase locked loop in the second clock generation circuit of the third function block so that the third function block operates at the operating frequency of the work content; and the first and second clock generation circuits generate a clock of a necessary operation frequency, using a clock signal from a main clock generation circuit, based on a frequency division ratio of the phase locked loop set by the processor.