Patent ID: 7136314

Claim:
A memory device comprising: a plurality of cell arrays each comprising a plurality of memory cells and a plurality of normal sub word lines which are arranged in a matrix; a plurality of bit line sense amplifiers for sensing and amplifying data in a plurality of bit lines; a plurality of bit line switches for selectively connecting the bit lines of the bit line sense amplifier to those of the cell array selected in response to a bit line separation control signal in a normal mode, selectively separating the bit lines of the bit line sense amplifier from those of the unselected cell array, and selectively separating the bit lines of the bit line sense amplifier from those of the cell array in response to the bit line separation control signal in a test mode; a plurality of dummy bit line switches each for selectively connecting dummy bit lines of the bit line sense amplifier to those of the cell array selected in response to the separation control signal in the normal mode, selectively separating the dummy bit lines of the bit line sense amplifier from those of the unselected cell array, and selectively separating the dummy bit lines of the bit line sense amplifier from those of the cell array in response to the separation control signal in the test mode; and a separation control unit for disabling the bit line separation control signal in response to a test mode signal in the test mode.