Patent ID: 8886511

Claim:
A method of modeling output delay of at least one clocked storage element, comprising: determining a first arrival time of a clock signal input into at least one clocked storage element; determining a second arrival time of an input data signal input into the at least one clocked storage element; determining a differential timing between the first arrival time and the second arrival time; and determining a unified model output delay of the at least one clocked storage element, the unified model output delay covering both (1) when arrival of the clock signal input precedes arrival of the input data signal and (2) when arrival of the clock signal input follows arrival of the input data signal as a function of one of: a first piecewise function of a “clk to q” delay and a difference between the “clk to q” delay and the differential timing; and a second piecewise function of an “a to q” delay and a difference between the “a to q” delay and the differential timing.