Patent ID: 8921189

Claim:
A method for fabricating a semiconductor device including a first region and a second region, wherein a pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region, the method comprising: providing a substrate including the first region and the second region; forming an etch target layer over the substrate, wherein the etch target layer comprises a stacked layer of a gate insulation layer, a gate conductive layer, a gate metal layer and a gate hard mask layer; forming a hard mask layer over the gate hard mask layer; etching the hard mask layer to form first and second hard mask patterns in the first and the second regions, respectively, wherein the first hard mask pattern has a first width and a first thickness and the second hard mask pattern has a second width larger than the first width and a second thickness same as the first thickness; forming a photoresist patterns covering the first region and exposing the second region; and etching the second hard mask pattern using the photoresist pattern as an etch mask to form a reduced second hard mask pattern which has a third width smaller than the second width and a third thickness smaller than the second thickness while maintaining the first width and the first thickness of the first hard mask pattern covered by the photoresist pattern, wherein the third width is larger than the first width and the third thickness is smaller than the first thickness.