Patent ID: 7612394

Claim:
A thin film transistor (TFT) array substrate, comprising: a substrate; a patterned composite layer, comprising a first conductive layer, an insulating layer and a channel layer, used to form a plurality of gate lines parallel to each other on the substrate, wherein the insulating layer is located exclusively on the first conductive layer, and the channel layer is formed exclusively on the insulating layer, each of the gate lines has a gate terminal port at a terminal, and the gate terminal port has an opening for exposing the first conductive layer; a plurality of color filter patterns disposed over the substrate for exposing the composite layer; a plurality of data lines disposed on the color filter patterns and intersected with the gate lines for forming a plurality of sub-pixel areas on the substrate; a plurality of pixel electrodes disposed in the corresponding sub-pixel areas and located on the corresponding color filter patterns; a plurality of sources/drains corresponding to the sub-pixel areas and disposed over the corresponding gate lines to form TFTs with the first conductive layer and the channel layer, wherein the sources/drains are connected to the corresponding data lines and the corresponding pixel electrodes respectively; and a black matrix disposed over the substrate and exposing the pixel electrodes.