Patent ID: 8390560

Claim:
A level shift circuit, comprising: a first output transistor driven to be turned ON to output a voltage derived from a first power source voltage; a second output transistor driven to be turned ON to output a voltage derived from a second power source voltage; a first input transistor having an output terminal, and driven, based on a first input pulse signal, to be turned ON to output a first voltage, the first voltage being a basis of a drive voltage which allows the first output transistor to turn ON; a second input transistor having an output terminal, and driven, based on the first input pulse signal, to be turned ON to output a second voltage, the second voltage being a basis of a drive voltage which allows the second output transistor to turn OFF; a third input transistor having an output terminal connected the output terminal of the first input transistor, and driven, based on a second input pulse signal, to be turned ON to output a third voltage, the third voltage being a basis of a drive voltage which allows the first output transistor to turn OFF; a fourth input transistor having an output terminal connected to the output terminal of the second input transistor, and driven, based on the second input pulse signal, to be turned ON to output a fourth voltage, the fourth voltage being a basis of a drive voltage which allows the second output transistor to turn ON; a first bootstrap circuit enlarging an amplitude of the first voltage, to supply the enlarged first voltage to the first output transistor; and a first voltage compensation circuit making a voltage change based on a third input pulse signal, a direction of the voltage change being opposite to a direction of a voltage fluctuation which is caused in the first voltage at an end timing of the first input pulse signal due to a parasitic capacitance in the first input transistor.