Patent ID: 7696033

Claim:
A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT), comprising: forming a buffer layer on an entire surface of a substrate; forming a polysilicon layer and a photoresist layer on the entire surface of the substrate having the buffer layer; exposing and developing the photoresist layer to form a first photoresist pattern having a first thickness in a first region where a semiconductor layer of a first TFT is to be formed, a second thickness in a second region where a channel and a Lightly Doped Drain (LDD) region of a second TFT is to be formed, and a third thickness in a third region where source and drain regions of the second TFT is to be formed; etching the polysilicon layer using the first photoresist pattern as a mask to form the semiconductor layer of the first TFT and the semiconductor layer of the second TFT; performing a first ashing process on the first photoresist pattern to form a second photoresist pattern where the third region having the third thickness has been removed from the first photoresist pattern; implanting a first impurity into the source and drain regions of the second TFT using the second photoresist pattern as a mask; performing a second ashing process on the second photoresist pattern to form a third photoresist pattern where the second region having the second thickness has been removed from the first photoresist pattern; and implanting a second impurity into the second TFT using the third photoresist pattern as a mask to perform channel doping on the second TFT.