Patent ID: 7636253

Claim:
A semiconductor device comprising: first and second memory array forming regions including a plurality of nonvolatile memory cells, wherein each of the nonvolatile memory cells includes a charge storage layer formed over a semiconductor substrate and a memory gate formed over the charge storage layer; and a shunt region formed between the first and second memory array forming regions, wherein the shunt region is a region for supplying voltage to the memory gates of the nonvolatile memory cells; wherein the memory gates of the nonvolatile memory cells are extended in a first direction, respectively, and are arranged in parallel, wherein, in the shunt region, a plurality of wirings for supplying voltage are formed over the memory gates and extended in a second direction substantially perpendicular to the first direction; wherein, in the shunt region, a plurality of the plugs are formed between the memory gates and the wirings, wherein each of the memory gates is respectively connected to one of the wirings through one of the plugs; wherein one of the plugs is connected to a first contact section of one of the memory gates, wherein another one of the plugs is connected to a second contact section of another one of the memory gates, and wherein the first and second contact sections are shifted relative to each other in the first direction.