Patent ID: 7844763

Claim:
A flash memory card comprising: a predetermined pin assignment based on a pin count of the flash memory card, the pin assignment including a set of pins for connected to two pairs of differential serial data lines, wherein each pair of the differential serial data lines carry a positive (+) signal and a negative (−) signal; a flash memory array; a protocol controller for accessing the flash memory array; and a differential datapath capable of converting an incoming differential signal into a status signal for the protocol controller and an incoming data signal for the protocol controller, and capable of converting a control signal from the protocol controller and an outgoing data signal from the protocol controller into an outgoing differential signal, wherein the differential datapath comprises: a differential transceiver for converting the incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into the outgoing differential signal; and a differential serial interface engine for converting the incoming multipurpose serial signal into at least one of the status signal and the incoming data signal, and for converting at least one of the control signal and the outgoing data signal into the outgoing multipurpose serial signal, wherein the differential serial interface engine comprises: a synchronization detector for identifying a synchronization field in the first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal; a write first-in-first-out (FIFO) memory for storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal; a CRC (cyclic redundancy check) detector for performing a CRC check on the first set of signals in response to the start signal; a command/data detector for determining whether the first set of signals are one of command signals and data signals in response to the start signal and providing that determination to the CRC detector; a start-of-frame (SOF) detector for detecting SOF fields in the first set of signals in response to the start signal and, upon such detection, triggering a local clock generation; and an end-of-packet (EOP) detector for detecting an EOP field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to the write FIFO, the CRC detector, the command/data detector, and the SOF detector; wherein the flash memory card comprises one of a MultiMediaCard, a Secure-Digital card, a CompactFlash card, and a Memory Stick.