Patent ID: 7853860

Claim:
A programmable signal processing circuit, comprising an operand storage circuit ( 22 ); an instruction processing circuit ( 23 , 24 , 26 ), for executing instructions that address operand locations and result locations in the operand storage circuit ( 22 ), an instruction set of the instruction processing circuit ( 23 , 24 , 26 ) comprising a depuncture instruction, the instruction processing circuit ( 23 , 24 , 26 ) having an operand input ( 36 a ) for receiving a bit metric operand from a bit metric operand location indicated by the depuncture instruction and a result output ( 39 ) for writing a depuncture result to a result location indicated by the depuncture instruction, the instruction processing circuit ( 23 , 24 , 26 ) being arranged to form the depuncture result by copying bit metrics from the bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result, changing the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.