Patent ID: 7192830

Claim:
A method for fabricating a memory cell, the method comprising: forming a gate electrode and an underlying a gate dielectric on an upper surface of a semiconductor body, the gate electrode including first and second sidewall portions; forming a storage layer including a first portion adjacent the first sidewall portion of the gate electrode and a second portion adjacent the second sidewall portion of the gate electrode, the forming of the storage layer further comprising forming a base layer over the semiconductor body, forming the storage layer over the base layer, and forming a covering layer over the storage layer; forming a first sidewall spacer adjacent the first sidewall portion of the gate electrode and a second sidewall spacer adjacent the second sidewall portion of the gate electrode, the first sidewall spacer overlying the first portion of the storage layer and the second sidewall spacer overlying the second portion of the storage layer; and forming a first doped region adjacent the first sidewall portion of the gate electrode and a second doped region adjacent the second sidewall portion of the gate electrode; wherein the base layer is formed over the region of the semiconductor body spaced from the gate electrode, the storage layer and the covering layer are all formed over a top surface of the gate electrode, the method further comprising removing the storage layer and the covering layer from the gate electrode by forming an auxiliary layer over the covering layer, removing an upper portion of the auxiliary layer so as to expose a portion of the covering layer over the gate electrode without exposing a portion of the covering layer over the semiconductor body at a region laterally spaced from the gate electrode, and removing the storage layer and the covering layer from the top surface of the gate electrode by chemical-mechanical polishing the auxiliary layer, and etching portions of the storage layer adjacent the upper portions of the sidewalls of the gate electrode using portions of the auxiliary layer as a mask.