Patent ID: 7910991

Claim:
A power transistor, comprising: a gate dielectric layer overlying an upper surface of a semiconductor substrate; a first gate electrode overlying the gate dielectric and laterally positioned overlying a first region of the substrate, the first region having a first doping type selected from an n-type doping and a p-type doping; a second gate electrode overlying the gate dielectric and laterally positioned over a second region of the substrate, the second region having a second doping type selected from an n-type doping and a p-type doping, wherein the first type and the second type are different; a drift region within the substrate, laterally positioned between the first and second substrate regions, the drift region underlying a lateral gap defined between the first and second gate electrodes wherein a boundary of the drift region is aligned to the first gate electrode, the drift region having the second doping type; a first source/drain region in the substrate, the first source/drain region having the second doping type, wherein a boundary of the first source/drain region is aligned to the first gate electrode; and a second source/drain region in the substrate, the second source/drain region having the second doping type, wherein a boundary of the second source/drain region is aligned to the second gate electrode.