Patent ID: 7535789

Claim:
A concatenated first-in-first-out memory circuit (FIFO), comprising: a first FIFO having a plurality of data input terminals, a plurality of data output terminals, a write clock input terminal coupled to receive a write clock signal for the concatenated FIFO, and a read clock input terminal; a second FIFO having a plurality of data input terminals coupled to the data output terminals of the first FIFO, a plurality of data output terminals, a write clock input terminal, and a read clock input terminal coupled to receive a read clock signal for the concatenated FIFO; and a control circuit coupled to the first FIFO and to the second FIFO, the control circuit having a local clock input terminal coupled to the read clock input terminal of the first FIFO and to the write clock input terminal of the second FIFO, wherein the local clock input terminal of the control circuit, the read clock input terminal of the first FIFO, and the write clock input terminal of the second FIFO are all coupled to receive one of the read clock signal or write clock signal for the concatenated FIFO.