Patent ID: 8400855

Claim:
A semiconductor device, comprising: a data transmission line; a data transmission line precharge circuit that sets a precharge potential of the data transmission line to a first potential at a time of a first write ode in which data masking is not performed, and to a potential different from the first potential at a time of a second write mode in which data masking is performed; a write amplifier that discharges the data transmission line, which has been precharged at the time of the first write mode, to a second potential; a memory cell array; and a plurality of selection switches, which are placed between the data transmission line and the memory cell array, that connects the data transmission line to a corresponding bit line of said memory cell array when turned ON; wherein at the time of the second write mode, said data transmission line precharge circuit sets the precharge potential of the data transmission line to an intermediate potential that is intermediate the first and the second potential.