Patent ID: 7944278

Claim:
A circuit for generating negative voltage of a semiconductor memory apparatus, comprising: a first detecting unit configured to generate a first detecting signal by detecting a first negative voltage level; a first negative voltage generating unit configured to generate the first negative voltage when the first detecting signal is enabled, and stop generating the first negative voltage when the first detecting signal is disabled; a second detecting unit configured to generate a second detecting signal by detecting a second negative voltage level; a timing controlling unit configured to output the second detecting signal as an enable signal when a power up signal is enabled and the first detecting signal is disabled, and maintain the enable signal at a disabled state until the first detecting signal is disabled after the power up signal is enabled; and a second negative voltage generating unit configured to generate a second negative voltage in response to the enable signal when the first detecting signal is disabled after the power up signal is enabled, and stop generating the second negative voltage regardless of the second detecting signal until the first detecting signal is disabled after the power up signal is enabled.