Patent ID: 7266010

Claim:
A memory cell comprising: a static random access memory (SRAM) circuit comprising a storage node, wherein the SRAM circuit comprises: a first negative differrential resistance (NDR) transistor connected between an upper supply voltage line and the storage node; a second NDR transistor connected between the storage node and a lower supply voltage line; and an access transistor connected between a bit line and the storage node, the access transistor having a gate connected to a word line; and a programmable resistor, the programmable resistor comprising: a first terminal connected to the storage node; and a second terminal coupled to receive a programming voltage, the programmable resistor being configured to be programmed to a first resistance state when a storage voltage at the storage node is greater than the programming voltage, and the programmable resistor being configured to be programmed to a second resistance state when the storage voltage at the storage node is less than the programming voltage.