Patent ID: 8804377

Claim:
A circuit, comprising: a control circuit having: a set-reset flip-flop having a set input terminal, a reset input terminal, and first and second output terminals; a control signal generator that includes: an integrator circuit having first and second input terminals and configured to receive at least one input signal on the first input terminal and to generate an integrated signal; and a first comparator having a first input terminal structured to receive only the integrated signal from the integrator circuit, a second input terminal structured to receive a control voltage, and an output terminal coupled to the reset input terminal of the set-reset flip-flop, the first comparator structured to generate on the output terminal a first control signal; a switching control circuit that includes: first and second constant current generators connected in series at a common point and between a voltage source and a ground reference potential; a capacitor coupled between the common point and the ground reference potential; and a second comparator having a first input terminal directly connected only to the common point, a second input terminal coupled to a reference voltage source, and an output terminal coupled to the set input terminal of the set-reset flip-flop.