Patent ID: 7247252

Claim:
A method for avoiding plasma arcing during a reactive ion etching (RIE) process comprising: providing a semiconductor wafer comprising a process surface for depositing a dielectric insulating layer; depositing at least a portion of the dielectric insulating layer according to plasma assisted chemical vapor deposition (CVD) process, the dielectric insulating layer comprising an electrical charge imbalance, said dielectric insulating layer selected from the group consisting of silicon dioxide, carbon doped oxide (C-oxide), organo-silicate glass (OSG), and undoped silicate glass (USG); treating the dielectric insulating layer surface according to a hydrogen containing plasma treatment consisting of hydrogen gas and an inert gas, said plasma treatment further comprising a biasing power to reduce the electrical charge imbalance; and, carrying out a subsequent reactive ion etching process to etch openings in the dielectric insulating layer.