Patent ID: 6907659

Claim:
A method for manufacturing and packaging an integrated circuit comprising the steps of: pressuring a continuous pin material area and a base board area, a plurality of pins being arranged linearly on said pin material area, said base board area including a plurality of base boards at a central portion of said base board area; cutting off said pin material area into a plurality of first pin units based on a required number of pins; accommodating each of said plurality of first pin units into a corresponding mould; injecting a plastic to fill a gap of said corresponding mould thereby forming a plurality of second pin units; cutting off a waste part of said pin material area after removing said mould; placing four of said plurality of second pin units on four sides of a rectangular mould and placing one of said plurality of boards at a central portion of a rectangle mould; injecting the plastic into a gap of said rectangle mould; cutting off a waste of said one base after removing said rectangle mould, thereby obtaining an integrated circuit socket; placing an integrated circuit chip at a central portion of said one base board; connecting a plurality of connection points of said grated circuit chip to said pins on said four second pin units, respectively; and covering a panel at a top of said integrated circuit socket.