Patent ID: 7783942

Claim:
An integrated circuit device comprising: a memory having: a first port to input a first clock signal, and a second port to input a second clock signal; and a built-in self test circuit having: a first signal generating circuit to input the first clock signal and which operates in accordance with the first clock signal and generates and outputs a signal for testing the memory, a second signal generating circuit to input the second clock signal and which operates in accordance with the second clock signal and generates and outputs a signal for testing the memory, a clock selecting circuit to input the first and second clock signals and which selects and outputs one of the input clock signals, and a controlling circuit, which outputs a clock requesting signal requesting one of the first and second clock signals to the clock selecting circuit, operates in accordance with the clock signal selected and output by the clock selecting circuit, and outputs a controlling signal for controlling one of the first and second signal generating circuits.