Patent ID: 7177314

Claim:
A system for multiplexing input data from a plurality of channels onto a selected one of a plurality of SONET/SDH frames having different sizes, comprising: a calendar configured to selectively multiplex the input data received from the plurality of channels; a processor configured to receive the multiplexed input data and re-arrange the multiplexed input data onto the selected SONET/SDH frame using virtual concatenation or contiguous concatenation or a combination of both; and a terminator configured to terminate overhead bytes within the selected SONET/SDH frame, wherein the processor further comprises: an input RAM configured to receive and output the multiplexed input data; a crossbar configured to receive and re-arrange the multiplexed input data outputted from the input RAM; an output RAM configured to receive the re-arranged multiplexed data from the crossbar; and a copy machine configured to control and coordinate operation of the input RAM, the crossbar and the output RAM, wherein the copy machine is further configured to control and coordinate the operation of the input RAM, the crossbar and the output RAM in accordance with a schedule; wherein the overhead bytes include sequence numbers; and wherein the calendar, the schedule and the sequence numbers are each double buffered and switched in a predetermined sequence so as to allow hitless re-provisioning.