Patent ID: 8686496

Claim:
A semiconductor device comprising: a semiconductor substrate having a first gate groove having first and second side walls facing to each other; a first gate insulating film covering the first and second side walls of the first gate groove; a first gate electrode on the first gate insulating film, the first gate electrode being in a lower portion of the first gate groove; a first burying insulating film that buries the first gate groove, the first burying insulating film covering the first gate electrode; a first diffusion region adjacent to a first upper portion of the first gate insulating film, the first upper portion being on an upper portion of the first side wall of the first gate groove; and a second diffusion region in contact with an entire portion of the second side wall of the first gate groove; an inter-layer insulating film over the first burying insulating film; a contact plug contacting the first diffusion region, the contact plug being in the first burying insulating film and the interlayer insulating film; a contact pad over the interlayer insulating film, the contact pad contacting an upper surface of the contact plug; and a capacitor electrically coupled to the contact pad.