Patent ID: 7941730

Claim:
A memory system comprising: a semiconductor memory having a memory cell array with memory cells, the memory cell array being accessed using a first memory interface; and a field programmable unit in which logic to inter-convert external signals and internal signals is programmed, the internal signals being input/output to/from the memory cell array, the external signals being input/output to/from the memory system; a nonvolatile program memory unit storing therein a program for constructing the logic of the field programmable unit; and external command terminals that receive external command signals as the external signals, respectively, the external command terminals including second memory interfaces being different from the first memory interface and the external command signals indicating access requests for the memory cell array which are supplied from a plurality of controllers, wherein the internal signals include internal command signals for accessing the memory cell array; the second memory interfaces vary depending on the controllers; and the logic programmed in the field programmable unit has a command conversion unit which converts the external command signals received by the external command terminals into the internal command signals, and an arbiter which determines, when the external command signals compete with each other, an order in which the command conversion unit outputs the internal command signals in response to the external command signals.