Patent ID: 8739103

Claim:
A method comprising: placing a digital portion of an electronic design for a programmable chip, wherein the programmable chip comprises multiple fixed-function blocks and a plurality of pins, wherein each one of the multiple fixed-function blocks can be coupled only to a respective subset of the plurality of pins, and wherein placing the digital portion comprises: placing a particular fixed-function block (FFB) instance on a particular fixed-function block of the multiple fixed-function blocks; wherein the particular fixed-function block can be coupled only to a particular subset of the plurality of pins in the programmable chip; wherein the particular FFB instance is connected to a particular input-output (IO) instance in the electronic design; and placing the particular IO instance on a particular pin from the particular subset of the plurality of pins; wherein placing the particular FFB instance and placing the particular IO instance are performed simultaneously; wherein placing the digital portion of the electronic design is performed by one or more computer systems.