Patent ID: 7534716

Claim:
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate having a top surface and a bottom surface, and having portions that form an opening through said substrate; applying at least one metal layer to said substrate to form a plurality of electrical conductors; mounting an integrated circuit die within said opening through said substrate and electrically connecting said integrated circuit die to said plurality of electrical conductors of said at least one metal layer; depositing a solder mask over portions of said at least one metal layer to define a plurality of metal layer portions of said at least one metal layer around said opening on said bottom surface of said substrate, wherein said solder mask is formed defining a plurality of solder mask vents around said opening; and soldering, using solder material, a lid to said plurality of metal layer portions such that said plurality of solder mask vents form a plurality of vapor pressure vents through said solder material into a cavity between at least part of the integrated circuit die and said lid over said opening.