Patent ID: 8154122

Claim:
A semiconductor package, comprising: a first package substrate including a base substrate having one surface on which a connection terminal is formed and a molding layer covering the base substrate, and a second package substrate which faces the first package substrate and is combined with the first package substrate, wherein the molding layer has a side surface facing a circumference of the connection terminal and is not in contact with the second package substrate, wherein the side surface includes a first surface and a second surface having circumferences of a different size, wherein the connection terminal is comprised of a first solder portion joined to the first package substrate and a second solder portion joined to the second package substrate, wherein the first surface is formed to surround a circumference of the first solder portion and the second surface is formed to surround a circumference of the second solder portion, wherein the circumference of the second surface is greater than the circumference of the first surface.