Patent ID: 7783693

Claim:
A reconfigurable circuit comprising: a plurality of processing elements, each of the processing elements includes an arithmetic unit respectively; a sequencer to control an operation of the arithmetic unit; and a network connected to the plurality of processing elements, the processing element includes, a first arithmetic unit to perform addition or subtraction of a first input data and a second input data and outputting output data; and a first selector to select the output data of the first arithmetic unit or a third input data, a second selector to select the selected data by the first selector in counter mode and a fourth input data in ALU mode, and to output the selected one as the first input data to the first arithmetic unit, and a third selector to select a step size of a counter in counter mode and a fifth input data in ALU mode, and to output the selected one as the second input data to the first arithmetic unit, wherein the first selector selects, in the counter mode, the third input data as an initial value at initial time, in other cases selects the output data of the first arithmetic unit, and outputs the selected one to the second selector.