Patent ID: 7313036

Claim:
A memory device having an open bit line architecture, comprising: first and second edge sub-arrays in which normal bit lines and dummy bit lines are interleaved, the normal bit lines being connected to memory cells that store data during normal operation, the dummy bit lines being connected to memory cells that do not store data during normal operation, the first and second edge sub-arrays including redundant word lines and redundant memory cells connected to the redundant word lines; and at least one normal sub-array which is arranged between the first and second edge sub-arrays, and in which normal bit lines connected to a first sense amplifier area and normal bit lines connected to a second sense amplifier area are interleaved with each other, the first sense amplifier area being arranged on a first side of the normal sub-array, the second sense amplifier area being arranged on a second side of the normal sub-array, wherein the normal sub-array is implemented so that memory cells connected to the normal bit lines connected to the first sense amplifier area are replaced with the redundant memory cells that are connected to the redundant word lines and that are included in the first edge sub-array by controlling an open or closed state of first fuses corresponding to addresses of the replaced memory cells connected to the normal bit lines connected to the first sense amplifier area, and memory cells connected to the normal bit lines connected to the second sense amplifier area are replaced with the redundant memory cells that are connected to the redundant word lines and that are included in the second edge sub-array by controlling an open or closed state of second fuses corresponding to addresses of the replaced memory cells connected to the normal bit lines connected to the second sense amplifier area, wherein the open or closed state of the first and second fuses are controlled at a repair control unit that corresponds to the first and second edge sub-arrays.