Patent ID: 7644237

Claim:
A microprocessor based system comprising: a memory controller coupled to a plurality of microprocessors and to a memory shared by the microprocessors; a plurality of memory caches, each respective memory cache of the plurality of memory caches associated with a respective microprocessor of the plurality of microprocessors; a global arbiter, coupled to each microprocessor and to said memory controller; and a plurality of buses: each respective bus of the plurality of buses coupling a respective microprocessor of the plurality of microprocessors to the global arbiter; each bus implementing a bus protocol that is different from the bus protocol of at least one other bus of the plurality of buses; and each bus exhibiting a latency for memory transactions that is different from the latency of at least one other bus of the plurality of buses; wherein: the plurality of microprocessors are configured to send a plurality of requests for memory transactions to the global arbiter; and said global arbiter is configured to: receive via the plurality of buses the plurality of requests for memory transactions from the plurality of microprocessors; assign a global order to each request of the plurality of requests; execute according to the global order, a snoop phase for each request of the plurality of requests, wherein each snoop phase comprises determining whether one or more of the plurality of microprocessors has memory cache data associated with a corresponding request; wait for all responses to come back in response to all the snoop phases of the plurality of requests; and respond according to the global order to the plurality of requests after the responses are received for all the snoop phases of the plurality of requests; whereby said global ordering of the plurality of requests results in data coherence among the plurality of caches, said data coherence being latency independent of the latency differences between the plurality of buses.