Patent ID: 7343472

Claim:
A processor comprises: instruction memory operably coupled to temporarily store an instruction, wherein the instruction includes an operational code, destination information, and source information; a plurality of arithmetic logic units (ALUs); a plurality of finite field arithmetic units, each having a plurality of multiplier cells arranged in a L×L square array structure of L rows and L columns with a feedback cell in each row, to multiply a first data vector and a second data vector in accordance with a polynomial value to produce a product, the polynomial value being selected for the multiplier array, the square array structure also configured to add the product to a third data vector to generate a product and sum resultant, in which the feedback cells in the array structure are coupled to receive a respective bit of the first data vector as a first input and a respective bit of the second data vector as a second input and a control signal as a third input, wherein when the control signal is in a first state, the feedback cells perform a Galois field addition of the respective first and second inputs to produce a first feedback signal to the array structure for the array structure to perform a Reed/Solomon operation using a Galois field multiply function and when the control signal is in a second state, the feedback cells pass only the first input to the array structure for the array structure to perform a cyclic redundancy check (CRC) operation; at least one digital storage device; and instruction decoder operably coupled to decode the instruction to: identify at least one of the plurality of the ALUs and the plurality of the finite field arithmetic units to perform a function specified by the operational code; identify at least one destination location in the at least one digital storage device based on the destination information to store the resultant; and identify at least one source location in the at least one digital storage device based on the source information, wherein, when one of the finite field arithmetic units is selected to perform the function specified by the operational code, the selected finite field arithmetic unit performs a finite field arithmetic function upon one or more data vector stored in the at least one source location.