Patent ID: 7322002

Claim:
A memory system, comprising: at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments, where each data segment contains an ECC code; and a memory control circuit coupled to the at least one memory device, wherein the memory control circuit comprises, a data buffer, a host transfer circuit coupled to the data buffer, and one or more ECC checker circuits, where the data buffer and the one or more ECC checker circuits are coupled to receive a selected read data segment; wherein N is a maximum number of bad bits recorded for each segment of the at least one memory device; and wherein the memory control circuit is adapted to correct the selected read data segent as it is read from the at least one memory device utilizing the one or more ECC checker circuits such that the one or more ECC checker circuits evaluate the selected read data segment with differing states of the N bad bits and where the memory control circuit selects the state of the N bad bits and selected read data segment that correctly evaluated in an ECC checker to transfer through the host transfer circuit.