Patent ID: 8732512

Claim:
A semiconductor device comprising: a clock control circuit outputting an internal clock signal obtained by delaying an external clock signal based on at least a first feedback clock signal; a plurality of data input/output terminals; a plurality of output buffers outputting a plurality of data to the data input/output terminals, respectively in synchronization with the internal clock signal, and each of the output buffers defining a first delay time as a time period from an input of the internal clock signal thereto to an output of the data therefrom, the first delay times of the output buffers being substantially equal to each other; a first replica circuit generating the first feedback clock signal based on the internal clock signal, and defining a second delay time as a time period from an input of the internal clock signal thereto to an output of the first feedback clock signal therefrom, the second delay time being substantially equal to the first delay time of each of the output buffers; and a clock tree circuit including a plurality of first multi-buffer transmission paths that transmit the internal clock signal from the clock control circuit to the output buffers, respectively, and a second multi-buffer transmission path that transmits the internal clock signal from the clock control circuit to the first replica circuit, wherein the clock tree circuit is configured such that signal line loads on the first multi-buffer transmission paths and the second multi-buffer transmission path are substantially equal to one another.