Patent ID: 7184317

Claim:
A method of programming a memory cell in a multi-bit charge-trapping memory cell array, the method comprising: providing an array of charge-trapping memory cells arranged in rows and columns, the array including a plurality of bitlines running in the direction of the columns, each memory cell having a first source/drain coupled to one of the bitlines and a second source/drain coupled to an adjacent one of the bitlines such that each of the source/drain regions located between two adjacent columns of the memory cells is coupled by a bitline, the bitlines being arranged in groups of bitlines, each of the groups comprising every other bitline that is arranged in succession within a section; applying an inhibit voltage to at least each bitline in the section that is not coupled to a memory cell that is to be programmed; and after applying the inhibit voltage, applying a lower programming voltage to the first source drain region of the memory cell that is to be programmed and applying an upper programming voltage to the memory cell that is to be programmed.