Patent ID: 7707355

Claim:
A system comprising: a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules, each bus being adapted to transmit corresponding ones of the address signals, the command signals, and the select signals to the corresponding memory module, wherein each of the memory modules includes: a plurality of memory devices; and a register adapted to receive and buffer the corresponding command and address signals transmitted to the memory module, and adapted to transmit the buffered command signal to a memory device which is to be accessed, in response to the corresponding select signal for selecting the memory device to be accessed among the memory devices, wherein the register includes: a buffer adapted to receive and buffer the corresponding command signal; a first latch connected to the buffer and adapted to latch an output signal of the buffer in response to the select signal; and a second latch adapted to transmit an output signal of the first latch to the selected memory device in response to a clock signal.