Patent ID: 7703076

Claim:
A graphics rendering engine stored on memory and executable by a computer, the graphics rendering engine comprising: source code represented as a first sequence of instruction addresses for display upon a screen accessible to a user, wherein the screen comprises a graphical user interface (GUI) for receiving user input to select one of the instruction addresses; a sequence of processor pipeline stages attributable to respective ones of the instruction addresses, wherein the screen displays: a breakpoint field that upon receiving the user input: selects a particular instruction address within the first sequence of instruction addresses shown in a particular processor pipeline stage of the processor pipeline; and displays all instruction addresses of the first sequence along with corresponding stages of the processor pipeline during a clock cycle in which the particular instruction address is within the particular processor pipeline stage; a designator for at least one of the instruction addresses to denote that a corresponding designated instruction address will proceed to a succeeding stage in the processor pipeline during a next clock cycle; a non-designator for another at least one instruction address of the first sequence of instruction addresses to denote that a corresponding non-designated instruction address will not proceed to the succeeding stage in the processor pipeline during the next clock cycle; and an instruction address field that, upon selection by a user, allows the user to move said another at least one instruction address to a different location within the first sequence of instruction addresses, wherein the instruction address in the instruction address field is selected by activating the breakpoint field to freeze a clock cycle and examine instruction addresses within the processor pipeline; and a scheduler that responds to the moved another at least one instruction address to form a second sequence of instruction addresses that has a higher instruction throughput in the processor pipeline than the first sequence of instruction addresses.