Patent ID: 7302633

Claim:
An LSI design system including logic correction support equipment for supporting logic correction of a logic circuit, said logic correction support equipment comprising: listing means that generates a first list of redundant faults of a register transfer level before the logic correction and a second list of redundant faults of the register transfer level after the logic correction; and finding means that finds a difference between the first list and the second list; wherein said listing means comprises: first hierarchical means that generates a hierarchical old register transfer level by hierarchically decomposing the register transfer level before said logic correction so that one sentence thereof may be on a single hierarchical level; first logic synthesis means that generates an old hierarchical logic circuit by logic-synthesizing the hierarchical old register transfer level while information of the hierarchical level is maintained; first detection means that detects and generates the first list of redundant faults of said old hierarchical logic circuit; second hierarchization means that generates a hierarchical new register transfer level by hierarchically decomposing the register transfer level after said logic correction so that one sentence thereof may be on a single hierarchical level; second logic synthesis means that generates a new hierarchical logic circuit by logic-synthesizing the hierarchical new register transfer level while information of the hierarchical level is maintained; and second detection means that detects and generates the second list of redundant faults of said new hierarchical logic circuit.