Patent ID: 7284142

Claim:
A timer module for generating interrupts to a system using a dedicated real-time interrupt clock signal, comprising: a prescale counter receiving the real-time interrupt clock and incremented by the real-time interrupt clock signal; a prescale compare value register storing a configurable value; a comparator connected to said prescale counter and said prescale compare value register for comparing the current count of the prescale counter with the stored configurable value and generating a match signal upon detection of a match; a free running counter connected to said comparator and incremented by said match signal from the comparator; and a plurality of interrupt generation units, each interrupt generation unit including an input receiving the current count of the free running counter, a compare value register for storing a compare value, an interrupt generator comparator connected to said input receiving the current count of the free running counter and the compare value register for comparing the compare value from the respective compare value register with the current count of the free running counter and generating an interrupt signal when the current count matches the compare value; an update value register storing an update value, and an adder for adding the update value to the compare value after each match detected by said interrupt generator comparator.