Patent ID: 7676286

Claim:
A system, comprising: a central node including a first microcontroller and a second microcontroller separate from the first microcontroller; one or more subsystem nodes disposed at one or more subsystems, and a single subsystem node is disposed at a single subsystem, and each subsystem node includes a first microcontroller and a second microcontroller separate from the first microcontroller; a data bus connecting the central node with each subsystem node; wherein the first microcontroller and the second microcontroller in each node are configured to output data to the bus, or receive data from the bus, or output data to and receive data from the bus, and to provide control signals, and wherein the second microcontroller in each node is configured to monitor the output data to the bus of the first microcontroller in each node and wherein the second microcontroller in each node is configured such that if the second microcontroller in each node determines that the first microcontroller in each node is providing improper output data to the bus, at least part of the output data to the bus of the first microcontroller in each node is nullified, overridden or superseded by a nullification output from the second microcontroller in each node.