Patent ID: 8072797

Claim:
A Static Random Access Memory (SRAM) cell comprising a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages, the transistors comprising: at least one bitline transistor configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column; at least one wordline transistor configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column; and at least two supply transistors configured to selectively couple corresponding ones of the storage nodes to a supply voltage; the bitline transistor being further configured to actively maintain a logic value at the one of the storage nodes and the wordline transistor being further configured to actively maintain a complementary logic value at the other of the storage nodes.