Patent ID: 8174095

Claim:
A semiconductor device comprising: an insulator layer; a first semiconductor region formed in a linear shape having two side surfaces, an upper surface and a lower surface along a <110> direction on the insulator layer, one of the upper surface and each of the two side surfaces having a (110) surface, and the first semiconductor region being made of Si having a uniaxial tensile strain in the <110> direction; an n-channel MIS transistor formed in the first semiconductor region, the n-channel MIS transistor including a first gate electrode formed on the two side surfaces, the upper surface, and the lower surface of the first semiconductor region through a first gate insulating film and having the <110> direction as a channel length direction thereof and a first source/drain region formed on the first semiconductor region to interpose the first gate electrode therebetween; a second semiconductor region having two side surfaces, an upper surface and a lower surface along the <110> direction on the insulator layer, one of the upper surface and each of the two side surfaces having a (110) surface, and the second semiconductor region being made of SiGe or Ge having a uniaxial compressive strain in the <110> direction; and a p-channel MIS transistor formed on the second semiconductor region, the p-channel MIS transistor including a second gate electrode formed on the two side surfaces, the upper surface and the lower surface of the second semiconductor region through a second gate insulating film and having the <110> direction as a channel length direction thereof and a second source/drain region formed on the second semiconductor region to interpose the first gate electrode therebetween.