Patent ID: 7684251

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array; the memory cell array comprising: a plurality of non-volatile memory cells each including a source region and a drain region formed in a semiconductor substrate so as to be separated from each other, a gate insulation film formed on a region of the semiconductor substrate which serves as a channel region between the source region and the drain region, a floating gate formed on the gate insulation film, an inter-electrode insulation film formed on the floating gate, and a control gate formed on the inter-electrode insulation film; bit lines, to each of which the drain regions of the non-volatile memory cells in an identical column direction are connected in common, the source regions of the non-volatile memory cells in an identical column direction being connected to ground in common; word lines, to each of which the control gates of the non-volatile memory cells in an identical row direction are connected in common; a word line drive circuit configured to select one of the word lines based on a row address signal and apply a predetermined voltage to the selected word line; and a write circuit configured to generate a write voltage on the basis of write data, select one of the bit lines on the basis of a column address signal, and apply the write voltage to the selected bit line, wherein the word line drive circuit applies the predetermined voltage to the selected word line during a write operation, and then opens the voltage applied to the selected word line.