Patent ID: 7551167

Claim:
A shift register, comprising: memory devices formed in a shape of an m-row×n-column matrix and shifting data synchronized with a clock signal; a first switching unit that selectively inverts n-bit data in accordance with a first switching control signal and inputs the inverted data to a first row memory device of each column of said memory devices; a second switching unit that selectively inverts n-bit data shifted by said memory devices and output to each column of m-th row in accordance with a second switching control signal and outputs the inverted data; a shift comparing unit that outputs a flag signal while outputting a first switching control signal to said first switching unit when data state of the first row memory devices changes, by utilizing n-bit data being input to said first switching unit and output data of the first row memory device included in said memory devices; and a shift comparing shift register having m-numbers of memory devices arranged in line and that shifts the flag signal output from said shift comparing unit to be synchronized with shift of said memory devices and outputs a second control signal to said second switching unit.