Patent ID: 8604469

Claim:
A thin film transistor array panel, comprising: a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor; a data line formed on the semiconductor and including a source electrode, the data line extending substantially in a longitudinal direction in a layout view to intersect the gate line; and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode in a width direction of the channel of the thin film transistor, the width direction extending along the longitudinal direction of the data line in the layout view, and wherein opposing sides of the gate line across from each other in the longitudinal direction of the data line in the layout view are covered by the channel of the thin film transistor.