Patent ID: 7525630

Claim:
A method of manufacturing an array substrate for a liquid crystal display device, the method comprising: forming a gate electrode, a gate line, and a gate pad on a substrate; disposing a first metal mask directly on the gate pad, the first metal mask contacting a top surface of the gate pad; forming a gate insulating layer, an amorphous silicon layer, a doped silicon layer, and a metal layer on the substrate; removing the first metal mask; forming a photoresist (PR) layer on the metal layer and the gate pad; exposing and developing the PR layer using a diffraction exposure technique to form first, second and third PR patterns, the first PR pattern corresponding to a center of the gate electrode and having a first thickness, the second PR pattern corresponding to both sides of the first PR pattern and having a second thickness, and the third PR pattern corresponding to the gate pad and having a third thickness, wherein the second thickness is greater than the first thickness and smaller than the third thickness; patterning the metal layer, the doped silicon layer and the amorphous silicon layer using the first to third PR patterns as an patterning mask to form a metal pattern, a doped silicon pattern and the amorphous silicon pattern under the first and second PR patterns; ashing the first to third PR patterns to remove the first PR pattern to expose a portion of the metal pattern; patterning the exposed metal pattern and the doped silicon pattern under the exposed metal pattern to form source and drain electrodes, a data line, a data pad, an ohmic contact layer, and an active layer; removing the second and third PR patterns; forming a pixel electrode contacting the drain electrode; forming a gate pad terminal and a data pad terminal covering the gate pad and the data pad, respectively, the gate pad terminal and the data pad terminal being made of a transparent conductive material, wherein the gate pad terminal covers an upper surface and side surfaces of the gate pad, and the data pad terminal covers an upper surface and side surfaces of the data pad; disposing second and third metal masks on the gate pad and data pad terminals, the second and third metal masks contacting top surfaces of the gate and data pad terminals, respectively; forming a passivation layer on the substrate; and removing the second and the third metal masks, wherein the source and drain electrodes, the data line and the data pad are formed from the metal layer, and a material of the metal layer is different from the transparent conductive material, and wherein the gate pad terminal and the data pad terminal are formed of the same material and at the same layer as the pixel electrode.