Patent ID: 7067372

Claim:
A method for fabricating a memory cell, which comprises the steps of: providing a substrate; forming a trench in the substrate, the trench having a lower region, a central region, an upper region, and an inner wall; subsequently forming an insulation collar in the central region on the inner wall of the trench; forming a dielectric layer at least in the lower region of the trench; forming a conductive trench filling in the lower region of the trench on the dielectric layer and at least partly in the central region of the trench on the insulation collar; forming a barrier layer on the conductive trench filling by thermally growing a thermal silicon nitride, a thermal silicon oxide, or a thermal silicon oxynitride and the conductive trench filing being completely covered by the barrier layer; and growing epitaxially a layer in the upper region of the trench, on the inner wall of the trench, and on the conductive trench filling, the barrier layer being overgrown laterally, proceeding from the inner wall of the trench, during epitaxial growing of the layer, the barrier layer serving as a barrier with respect to impurities and dislocations migrating from the conductive trench filing into the epitaxially grown layer, and simultaneously the barrier layer allowing transmission of electric charges stored in the conductive trench filing.