Patent ID: 7795948

Claim:
A circuit comprising: a first multi-tanh cell having a first common-emitter node to receive a first bias current; a first extra transistor coupled to the first common-emitter node to dynamically divert a portion of the first bias current from the first multi-tanh cell; a second multi-tanh cell having a second common-emitter node to receive a second bias current; a second extra transistor coupled to the second common-emitter node to dynamically divert a portion of the second bias current from the second multi-tanh cell; and first and second input networks arranged to cause the first and second multi-tanh cells to operate as multipliers; where: the outputs of the first and second multi-tanh cells are coupled together; the first multi-tanh cell is arranged to multiply a first input signal and a second input signal; the second multi-tanh cell is arranged to multiply a third input signal and a feedback signal; the outputs of the first and second multi-tanh cells are coupled together in a summing configuration; the circuit further comprises an integrating buffer to generate an output signal in response to the outputs of the first and second multi-tanh cells; and the circuit further comprises a summing circuit to generate the feedback signal in response to the output signal and a fourth input signal.