Patent ID: 6941535

Claim:
A design system of a semiconductor integrated circuit element, comprising: an input/output-block arrangement unit for determining arrangement of an input/output block; a function-block arrangement unit for determining arrangement of all function blocks which include an analog-signal-circuit block; a unit-capacity-cell arrangement unit for arranging a plurality of unit capacity cell blocks in adjacency to each other in a latticed pattern, at least, an interstice between the input/output block and the analog-signal-circuit block within that open region of an element region which does not belong to either the input/output block or the function blocks; the unit capacity cell blocks symbolizing unit capacity cells each of which includes a unit capacitor composed of a first electrode to be set at a first power source potential, a dielectric layer, and a second electrode opposing to the first electrode through the dielectric layer and to be set at a second power source potential, and which have such a connection wiring pattern that, when the unit capacity cells are arranged in adjacency to each other, the first electrodes of the adjacent unit capacity cells can be electrically connected to each other, while the second electrodes thereof can be electrically connected to each other, wherein the unit capacity cell is a rectangular-shaped unit capacity cell which is shaped rectangular when viewed in plan, and in which the first electrode and the second electrode are electrically lead out to every side, and lead-out positions of the first electrode and the second electrode are held in a relationship of a mirror image between opposing sides, and the unit-capacity-cell arrangement unit arranges rectangular-shaped unit capacity cell blocks symbolizing a plurality of such rectangular-shaped unit capacity cells, in adjacency to each other in the latticed pattern; an analog-wiring arrangement unit for determining arrangement of wiring lines between the input/output block and the analog-signal-circuit block; and a via-conductor arrangement unit for determining arrangement of at least one first via-conductor which is electrically connected with the first electrode while extending from at least one first power source wiring line to be set at the first power source potential, among the wiring lines, and at least one second via-conductor which is electrically connected with the second electrode while extending from at least one second power source wiring line to be set at the second power source potential, among the wiring lines.