Patent ID: 7317335

Claim:
A voltage level shift circuit, comprising: a first PMOS transistor having a gate which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, having a source connected to a first node, and having a drain connected to a first output node; an inverter having an input connected to the gate of the first PMOS transistor; a second PMOS transistor having a gate connected to an output of the inverter; having a source connected to a second node, and having a drain connected to a second output node; a first NMOS transistor having a gate connected to the drain of the second PMOS transistor, having a source connected to a first reference potential VBB, where VBB<Vss, and having a drain connected to the drain of the first PMOS transistor; and a second NMOS transistor having a gate connected to the drain of the first PMOS transistor, having a source connected to the first reference potential VBB, and having a drain connected to the drain of the second PMOS transistor; wherein at least one of (a) the second node is connected to the gate of the first PMOS transistor, and (b) the first node is connected to the gate of the second PMOS transistor.