Patent ID: 7499340

Claim:
A semiconductor device formed in a rectangle region on a semiconductor substrate, said rectangle region comprising a first region extending along a first center line which intersects a middle point of a first side of said rectangle region, wherein said first region divides said rectangle region to form a second region and a third region, said semiconductor device comprising: a first memory array comprising a plurality of first dynamic memory cells of N bits, the first memory array being formed in said second region; a second memory array comprising a plurality of second dynamic memory cells of N bits, the second memory array being formed in said third region; a plurality of bonding pads formed in said first region; and a voltage generating circuit for receiving a first voltage and for generating a second voltage which is different from said first voltage, said voltage generating circuit being formed in said first region, wherein the first memory array further includes: a plurality of word lines coupled to the plurality of first and second dynamic memory cells; a plurality of bit lines coupled to the plurality of first and second dynamic memory cells; and a plurality of sense amplifiers connected to said plurality of bit lines, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein said N bits obtained through said activated sense amplifiers are output as data, and wherein said N is one of numbers in a progression expressed as 2 k , k=2, 3, 4, - - - .