Patent ID: 8458444

Claim:
An apparatus comprising: an execution unit; a predictor table that includes a plurality of storage elements, including a storage element configured to store information indicative of a first execution dependency between a first floating-point instruction and a second floating-point instruction in an instruction stream; wherein an initial one of the first and second floating-point instructions in the instruction stream specifies a first portion of a logical register as a destination, and the other, subsequent one of the first and second floating-point instructions collectively specifies at least the first portion and a second portion of the logical register as a source; wherein the apparatus is configured, in response to information indicative of the first execution dependency stored in the storage element, to: insert one or more instructions into the instruction stream between the first and second floating-point instructions; and execute the inserted one or more instructions along with unmodified versions of the first and second floating-point instructions; wherein at least one of the inserted one or more instructions specifies the first and second portions of the logical register as a destination; wherein the inserted one or more instructions are executable by the execution unit to cause a physical register within the apparatus to receive first and second floating-point values that are to be used collectively as a value of the source specified by the subsequent floating-point instruction; and wherein the predictor table is configured to store a plurality of addresses, each of which corresponds to a respective instruction in the instruction stream detected to exhibit an execution dependency.