Patent ID: 7792037

Claim:
A synchronization apparatus comprising: a serial-to-parallel conversion device having a serial data input and a parallel data output, the parallel data output being connected to a parallel data input of a memory array, and additionally having a parallel S/P clock input for receiving a plurality of clock signals which are phase-shifted relative to one another; a parallel-to-serial conversion device having a parallel data input and a serial data output, the parallel data input being connected to a parallel data output of the memory array, and additionally having a parallel P/S clock input for receiving the plurality of clock signals which are phase-shifted relative to one another; a PLL having a clock input and a parallel clock output for producing and outputting the plurality of clock signals which are phase-shifted relative to one another via the parallel clock output, the parallel clock output being connected to the serial-to-parallel conversion device and to the parallel-to-serial conversion device; a write FIFO for clock domain conversion of write data signals; a latency counter FIFO for clock domain conversion of read signals with simultaneous shifting through a particular number of clock cycles: and a common counter device which is actuated using a clock signal from a first domain and which is used for actuating both an input pointer input of the write FIFO and an output pointer input of the latency counter FIFO.