Patent ID: 8461460

Claim:
A microelectronic interconnect element, comprising: a plurality of first metal lines each having a lower surface whose width and length extend within a reference plane, an upper surface remote from the reference plane, and edges extending between the upper and lower surfaces, a first distance between the upper and lower surfaces of such first metal line defining a thickness of such first metal line; a plurality of second metal lines interleaved with the first metal lines in a direction of the width of the first metal lines, each of the second metal lines having an upper surface whose width and length extend within the reference plane and a lower surface remote from the reference plane, a second distance between the upper and lower surfaces of such second metal line defining a thickness of such second metal line; and a dielectric layer separating a metal line of the first metal lines from an adjacent metal line of the second metal lines, wherein a pitch between the first metal line and the second metal line adjacent thereto is smaller than a first pitch between adjacent ones of the first metal lines and is smaller than a second pitch between adjacent ones of the second metal lines, and wherein the first pitch is equal to at least twice a width of one of the first metal lines, and second pitch is equal to at least twice a width of one of the second metal lines, such that, in a direction of the widths of the first metal lines, at least some of the first metal lines are insulated and spaced from at least some of the second metal lines by less than the width of one of the first metal lines.