Patent ID: 7075136

Claim:
A system on chip (SOC) containing a DRAM and an analog device, comprising: a substrate; a lower part on the substrate containing circuitry; a first interlayer insulating layer on top of the lower part; a first conductive layer on the first interlayer insulating layer, the first conductive layer forming a lower electrode for the DRAM, a first dielectric layer formed on the first conductive layer; a second conductive layer on the first dielectric layer and forming an upper electrode of the DRAM, the second conductive layer having holes therein; a second dielectric layer covering the second conductive layer; a third conductive layer covering the second dielectric layer, and performing as another lower electrode of the DRAM, the third conductive layer filling the holes of the second conductive layer; a second interlayer insulating layer covering third conductive layer; a first metal pattern formed on the second interlayer insulating layer connecting to the upper electrode through a first contact plug which is formed in the second interlayer insulating layer; and a second metal pattern formed on the second interlayer insulating layer connecting to the lower electrode through a second contact plug.