Patent ID: 7319620

Claim:
A buffer circuit comprising: a first differential amplifier circuit having a first topology; and a second differential amplifier circuit having a second topology that is the mirror image of the first differential amplifier circuit, the first differential amplifier circuit being coupled to the second differential amplifier circuit in a manner that results in the buffer circuit having a symmetrical topology, each of the first and second differential amplifier circuits comprising: a first pair of transistors coupled in a current mirror configuration whose gates are coupled to each other and coupled to the drain of one of the first pair of transistors, and further having its sources coupled to a first supply voltage; a second pair of transistors each configured to receive an input signal at its gate, wherein the input signals are differential input signals, the second pair of transistors further having its sources coupled to each other and its drains respectively coupled to the drains of the first pair of transistors; and a third pair of transistors whose drains are coupled to the sources of the second pair of transistors and whose sources are coupled to a second supply voltage.