Patent ID: 7334171

Claim:
A test pattern generating apparatus adapted to generate test patterns of a circuit, said apparatus comprising: a circuit data read in section that reads in circuit data and divides the circuit data into a plurality of functional blocks; a correspondence setting up section that sorts the plurality of functional blocks into test pattern generating object blocks that are objects of the operation of generating a test pattern of each of the test pattern generating object blocks and test pattern copying object blocks other than the test pattern generating object blocks that are configurationally identical with the test pattern generating object blocks and sets up correspondence of the test pattern generating object blocks to the test pattern copying object blocks; a test pattern generating section that generates the test pattern of each of the test pattern generating object blocks; and a test pattern copying section that, based upon the correspondence setting, copies the test pattern of each of the test pattern generating object blocks that correspond to the test pattern copying object blocks, as test patterns of each of the test pattern copying object blocks.