Patent ID: 7516271

Claim:
A content addressable memory (CAM), comprising: a CAM array that stores entries in P memory locations that each have a location width and that stores, for each memory location, a suppress value, the CAM array providing, for each memory location, a match signal indicating whether the location has a stored entry satisfying a match criterion and suppress signals based on locations' suppress values; match combining circuitry that responds to the match signals and to a signal indicating a search width that is a multiple of the location width, the match combining circuitry providing P/Q combined match signals, each combined match signal indicating a combination of a group of Q match signals, the combination depending on the indicated search width; and search results circuitry that responds to the combined match signals and to the suppress signals, providing an address code of a memory location, the memory location storing at least part of an entry of the indicated search width that satisfies the match criterion.