Patent ID: 7057437

Claim:
A method of reducing electromagnetic interference in a clock generating circuit, the method comprising: providing a first clock signal pair consisting of a first positive clock and a first negative clock, the first positive clock being substantially 180 degrees out of phase with the first negative clock; subtracting the first negative clock from the first positive clock to create a first differential clock; generating a first start pulse based on the first differential clock; providing a second clock signal pair consisting of a second positive clock and a second negative clock, the second positive clock being substantially 180 degrees out of phase with the second negative clock; subtracting the second negative clock from the second positive clock to create a second differential clock; and generating a second start pulse based on the second differential clock; wherein the first positive clock is 180 degrees out of phase with the second positive clock and the first negative clock is 180 degrees out of phase with the second negative clock.