Patent ID: 8043912

Claim:
A semiconductor device manufacturing method comprising: forming element-isolating insulation films in element isolation regions of a semiconductor substrate; continuously forming a polysilicon layer on the semiconductor substrate such that the polysilicon layer is formed on the element-isolating insulation films and on an element region surrounded by the element-isolating insulation films; introducing impurities into the element region of the semiconductor substrate, using the polysilicon layer as a mask; forming a spacer which is in contact with a side wall of the polysilicon layer; forming a mask layer having an opening in which the spacer in each of the element isolation regions is exposed; etching the spacer, using the mask layer as a mask, such that shoulder portions which are near the spacer in each of the element isolation regions and the polysilicon layer in each of the element isolation regions are exposed, each exposed area includes the polysilicon layer, the shoulder portions, and the element isolation regions; forming a silicide layer on the polysilicon layer by a salicide process and permitting a silicide layer to grow on the exposed shoulder portions of the polysilicon layer such that the silicide layer is thicker in each element isolation region than in the element region, the silicide layer having thick film in the element isolation region is connected with that having thin film in the element region in a plane.