Patent ID: 7856532

Claim:
Cache logic for use in a data processing apparatus, the cache logic comprising: a cache storage comprising a plurality of cache lines configured to store data values; and control logic, in response to an access request issued by a device of the data processing apparatus identifying a memory address of a data value to be accessed, configured to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage, the control logic configured, if the data value is not stored in the cache storage, to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request, whilst the eviction is taking place, the control logic configured to allow the current content of the selected cache line to be accessed within the selected cache line by subsequent access requests seeking to read a data value within that current content, but to prevent the current content of the selected cache line being accessed by subsequent access requests seeking to write a data value within that current content, wherein the linefill process further comprises issuing a linefill request to the memory to obtain the new content, and the current content is kept valid in the selected cache line until the new content is available for storing in the selected cache line, even if the eviction has been completed.