Patent ID: 7092689

Claim:
A phase-locked loop (PLL) for producing sampling points for high-speed serial data, comprising: a clock and data recovery (CDR) module coupled to receive the high-speed serial data, the CDR module producing phase information; a charge pump for producing an error current that reflects a phase difference between a feedback signal and a phase of the high-speed serial data based on the phase information; a loop filter coupled to receive the error current, wherein the loop filter converts the error current to a voltage signal; a voltage controlled oscillator (VCO) coupled to receive the voltage signal, wherein the VCO produces a local oscillation that corresponds to the voltage signal and further wherein the local oscillation is produced to the CDR module as the feedback signal; and wherein the charge pump further includes adjustment circuitry for selectively adjusting the error current to cause the feedback signal to be phase adjusted to any desired point within a period of each bit of the high-speed serial data.