Patent ID: 7863186

Claim:
A method of forming fully and uniformly silicided gate conductors on a semiconductor device, comprising the steps of: providing a semiconductor device comprising a silicon substrate and one or more gate stacks formed on the silicon substrate, said one or more gate stacks each further comprising a gate conductor overlying a thin gate dielectric, said thin gate dielectric spacing the gate conductor away from a corresponding channel region defined in the silicon substrate; disposing a layer of a self-assembling diblock copolymer overlying the one or more gate conductors; annealing the diblock copolymer layer to cause it to organize itself into a repeating pattern of nanometer-scale polymer structures; developing the diblock copolymer layer to form a repeating pattern of nanometer-scale openings therein; selectively etching, using the developed copolymer layer as an etching template, to form nanometer-scale perforations extending into the one or more gate conductors, then filling the nanometer-scale perforations with a silicide-forming metal by depositing the silicide-forming metal over the one or more gate conductors; and saliciding to convert said one or more gate conductors to silicide.