Patent ID: 7297606

Claim:
A method of forming a metal-oxide-semiconductor (MOS) device, the method comprising the steps of: forming source and drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the source and drain regions being spaced apart relative to one another; forming a gate proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions; forming a buried lightly-doped drain (LDD) region of the first conductivity type in the semiconductor layer between the gate and the drain region, the buried LDD region being formed below at least a portion of the drain region and extending laterally from the drain region to below at least a portion of the gate; and forming a second LDD region of the second conductivity type in the buried LDD region and proximate the upper surface of the semiconductor layer, the second LDD region being self-aligned with a first alignment structure formed substantially concurrently with the gate in a same processing step, the second LDD region being spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.