Patent ID: 7894281

Claim:
A redundancy circuit, comprising: an address redundancy circuit block configured to compare column address information of a defective memory cell and an external input column address and output a redundancy column activation signal; and an input/output (IO) redundancy circuit block coupled with the address redundancy circuit block, the IO redundancy circuit block configured to control whether to activate a global IO line connected to an IO pad of a sub-block in response to IO fuse information including information related to the sub-block in which a column line of the defective memory cell is arranged and the redundancy column activation signal, wherein the IO redundancy circuit block comprises: an IO redundancy control section configured to use the IO fuse information as redundancy address and sub-block information in response to the redundancy column activation signal; an IO decoder coupled with the IO redundancy control section, the IO decoder configured to decode the redundancy address and sub-block information and activate a global redundancy line; and a global redundancy line controller coupled with the IO decoder, the global redundancy line controller configured to activate a specific write global redundancy line and a specific read global redundancy line according to the activated global redundancy line.