Patent ID: 7130946

Claim:
A configuration, comprising: at least one first device; a cross bar; at least one second device connected to said at least one first device through said cross bar, said at least one first device accessing said at least one second device through said cross bar to at least one of read data from said at least one second device and write data to said at least one second device; a first multiplexer associated with each of said at least one first device, each first multiplexer having input connections connecting directly or via a pipeline stage to all of said at least one second device through read data buses and an output connection connecting to the associated one of said at least one first device through a read data bus; an arbiter associated with each of said at least one second device, each arbiter having input connections connecting directly or via a pipeline stage to all of said at least one first device through address buses and an output connection connecting to the associated one of said at least one second device through an address bus; and a second multiplexer associated with each of said at least one second device, each second multiplexer having input connections connecting directly or via a pipeline stage to all of said at least one first device through write data buses and an output connection connecting to the associated one of said at least one second device through a write data bus; wherein said pipeline stage is not one of said first multiplexers, one of said arbiters, or one of said second multiplexers.