Patent ID: 8159889

Claim:
A solid state drive controller comprising: a first data transfer block connected to a first port; a second data transfer block connected to a second port; a buffer memory electrically connected between the first and second data transfer blocks, and configured to store the write data transferred between the first and second ports; a central processing unit connected to the first and second data transfer blocks through a CPU bus; and a buffer controller/arbiter block configured to transfer the write data between the first and second data transfer blocks bypassing the CPU bus, and further configured to control read and write operations of the buffer memory, wherein write data is transferred between the first port and the second port through the first and second data transfer blocks bypassing the CPU bus based on a control of the central processing unit, wherein the write data transferred from the first or second data transfer block is stored into the buffer memory, and the write data read from the buffer memory is transferred to the first or second data transfer block, and wherein the buffer controller/arbiter block is configured to control the read and write operations of the buffer memory based on the control of the central processing unit through the CPU bus.