Patent ID: 8320208

Claim:
A sense amplifier circuit of a single-ended type amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising: a first MOS transistor driving the bit line to a predetermined voltage and switching connection between the bit line and a sense node in response to a gate voltage; a second MOS transistor having a gate connected to the sense node and amplifying the signal transmitted from the bit line via the first MOS transistor; a first precharge circuit precharging the bit line to a first potential in response to a first control signal; and a second precharge circuit precharging the sense node to a second potential higher than the first potential in response to a second control signal, wherein, before a sensing operation, the gate voltage is set to a second voltage in a predetermined period in a state where the bit line is maintained at the first potential, and thereafter the bit line is driven to the predetermined voltage by setting the gate voltage to a first voltage lower than the second voltage in a state where the sense node is maintained at the second potential, and the predetermined voltage is set to a value such that a required voltage difference at the sense node between high-level data and low-level data read out from the memory cell can be obtained in a vicinity of a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.