Patent ID: 8400137

Claim:
A reference voltage generation circuit for generating a reference voltage, comprising: a current-mirror circuit including a first MOS (Metal Oxide Semiconductor) transistor, a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor, and an output MOS transistor including a source terminal connected to a power source, a gate terminal connected to the gate terminal of the first MOS transistor, and a drain terminal for outputting the reference voltage; and a control circuit for controlling the current-mirror circuit so that an output current of the current-mirror circuit is converted to the reference voltage, said control circuit including a first transistor and a voltage decrease prevention circuit, said first transistor including a collector terminal connected to a drain terminal of the second MOS transistor, said voltage decrease prevention circuit being connected between the gate terminal of the output MOS transistor and the collector terminal of the first transistor, wherein said voltage decrease prevention circuit includes a second transistor including a base terminal connected to the collector terminal of the first transistor.