Patent ID: 8365109

Claim:
A method, comprising: receiving a circuit design having a plurality of components, each component having a data terminal connected to a data terminal of another one of the components; for each of the data terminals, determining a respective list of dimensions of data used by the data terminal; and performing on at least one programmed processor, operations including: generating a plurality of exchange orderings, each exchange ordering indicating an order in which dimensions are exchanged between the lists of dimensions; for each exchange ordering: exchanging dimensions between the lists in the order indicated by the exchange ordering to produce a set of supplemented lists of dimensions; determining a set of buffers for buffering data between connected ones of the data terminals based on the supplemented lists of dimensions; and determining memory requirements for the set of buffers corresponding to each exchange ordering; and modifying the circuit design to include the one of the determined sets of buffers having a lowest memory requirement.