Patent ID: 8239660

Claim:
A system for executing a plurality of instructions, the system comprising: a processor having a plurality of terminals comprising a first terminal and a second terminal, each of the plurality of terminals comprising at least one functional unit, the processor comprising: a loader for: loading into the first terminal a plurality of instructions having a first tag associated therewith, each instruction of the plurality of instructions being representative of an expression and comprising an indication of at least one subsequent instruction that uses as an operand a result of evaluation of the expression, the indication comprising a terminal indicator indicating a terminal of the plurality of terminals in which the at least one subsequent instruction will be executed; a first functional logic of the first terminal for evaluating the first expression based on a first instruction from the first plurality of instructions to generate a first result; and at least one control component for determining a destination for the first result based on the indication in the first instruction of the at least one other instruction that will use the first result as an operand, wherein the destination comprises at least one of an operand storage memory of the first terminal, a first transfer memory of the first terminal, a second transfer memory of the second terminal, and an input of the first functional logic of the first terminal, wherein: the first transfer memory of the first terminal is adapted to receive a result of an operation from the second terminal and the second transfer memory of the second terminal is adapted to receive a result of an operation from the first terminal.