Patent ID: 8671254

Claim:
An integrated circuit comprising: a first memory having a first read port and a first write port for concurrent read and write, the first memory having memory locations for data accessible by asserting respective addresses to the first memory through the first read port and the first write port; a second memory having a second read port and a second write port for concurrent read and write, the second memory having memory locations for data accessible by asserting respective addresses to the second memory through the second read port and the second write port; and address generation circuitry respectively coupled by address lines to said first memory and to said second memory and operable to generate address bits representative of odd and even addresses, said first memory responsive only to the even addresses and said second memory responsive only to the odd addresses; and wherein said first memory is operable, in response to said address generation circuitry, to either read or write a first data quantity responsive to an even address during a same clock cycle said second memory is operable, in response to said address generation circuitry, to perform at least one of a read at a same time as a read of said first memory, or a write at a same time as a write of said first memory, a second data quantity, differing from said first data quantity, responsive to an odd address.