Patent ID: 8438429

Claim:
A storage control apparatus comprising: a first memory area; a second memory area; and a controller that is coupled to the first memory area and the second memory area, wherein, when the controller writes first data to the first memory area, the controller is configured to add error detecting code of the a first kind to a first data element that is an element of the first data and is configured to then write the first data to the first memory area, and wherein the controller is further configured to add error detecting code of a second kind to the first data; wherein, when the controller writes the second data to the second memory area, the controller adds is further configured to add an error detecting code of the first kind to a second data element that is an element of the second data and is further configured to then write the second data to the second memory area, wherein the first memory area comprises at least one first memory module group, each of the at least one first memory module group comprises at least one first memory module, and each of the at least one first memory module is provided with comprises a plurality of memory chips, the second memory area comprises at least one second memory module group, each of the at least one second memory module group comprises at least one second memory module, and each of the at least one second memory module comprises a plurality of memory chips, wherein, (A) the first memory module includes exactly one error chip: when the error chip is correctable, the controller is further configured to manage a first memory module group that comprises the error chips, and when the error chips is not correctable, the controller is further configured to not manage the first memory module group that comprises the error chip, wherein, (B) the second memory module includes exactly one error chip, the controller is configured to manage a second memory module group that comprises the error chip, wherein (C) the first memory module group comprises more than one error chip or the second memory module group comprises more than one error chip, the controller is configured to not manage the first or second memory module group that comprises the more than one error chip, wherein the first data is user data that is write target data or read target data and the error detecting code of the second kind that is added to the user data, and the second data is the control data to which an error detecting code is not added, wherein data size of the first data is the same as that of the second data, wherein a first number of memory chips that configure the second memory module group is larger than a second number of memory chips that configure the first memory module group, wherein a third number of data transfer cycles from the controller to the second memory module group is smaller than a fourth number of data transfer cycles from the controller to the first memory module group.