Patent ID: 8557652

Claim:
A method of fabricating a semiconductor structure comprising: forming a high k gate dielectric atop a semiconductor substrate including a first device region and a second device region; selectively forming a first surface threshold voltage adjusting region beneath an upper surface of the high k gate dielectric, yet located within 3 nm or less from the upper surface of the high k gate dielectric, in either the first device region or the second device region utilizing a cluster ion beam implant process, said cluster ion beam process introduces first threshold voltage adjusting metal particles into said high k gate dielectric in said first or second device region; and selectively forming a second surface threshold voltage adjusting region beneath the upper surface of the high k gate dielectric, yet located within 3 nm or less from the upper surface of the high k gate dielectric, in the other of the first device region or the second device region not including the first surface threshold voltage adjusting region utilizing another cluster ion beam implant process, said another cluster beam processes introduces second threshold voltage adjusting metal particles into said high k gate dielectric in the other of said first or second device region not including the first surface threshold voltage adjusting region.