Patent ID: 7397271

Claim:
A semiconductor integrated circuit device comprising: a combinational logic circuit including one or plural logic cells connected in series, wherein at least one of the logic cells includes a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal, a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state, and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state; a first flip-flop circuit including a data input terminal to which an output signal of the combinational logic circuit is inputted and a clock input terminal to which a clock signal is inputted; a second flip-flop circuit to which a clock control signal controlling whether the clock signal is supplied is inputted, the second flip-flop circuit outputting the clock control signal as an output signal in synchronization with a system clock signal; an OR circuit to which the output signal of the second flip-flop circuit and the system clock signal are inputted, the OR circuit outputting the clock signal; and an inverter circuit to which the output signal of the second flip-flop circuit is inputted, the inverter circuit outputting a signal obtained by inverting the inputted signal as the circuit control signal.