Patent ID: 6849553

Claim:
A method of manufacturing a semiconductor device, which comprises a memory area having a non-volatile memory device and a logic circuit area including a peripheral circuit of the non-volatile memory device formed on a chip, the manufacturing method comprising the steps of: (a) providing a semiconductor substrate, which includes a semiconductor layer, a first insulating layer formed on the semiconductor layer, a first conductive layer formed on the first insulating layer, and a stopper layer formed on the first conductive layer; (b) patterning the stopper layer and the first conductive layer in the memory area on the chip; (c) forming control gates as side walls on both side faces of the patterned first conductive layer via an oxide nitride oxide (ONO) membrane in the memory area on the chip; (d) etching out the stopper layer in the logic circuit area on the chip; (e) patterning the first conductive layer in the logic circuit area on the chip to form a gate electrode of an insulated gate field effect transistor; (f) forming a second insulating layer over whole surface of the semiconductor substrate; and (g) polishing the second insulating layer to expose the stopper layer in the memory area, the manufacturing method further comprising the step of: (h) patterning at least the first conductive layer on a peripheral portion of the chip or in a scribing area between adjoining chips to form a gate layer as a dummy circuit, wherein the step (h) is carried out prior to the step (f).