Patent ID: 7315158

Claim:
A PWM circuit comprising: a counter counting reference clocks; a cycle register in which a set value indicating a cycle is registered; a cycle detector comparing an output value of said counter and the set value registered in said cycle register indicating a cycle; a pulse width register in which a set value indicating a pulse width is registered; a pulse width detector comparing the output value of said counter and the set value registered in said pulse width register indicating a pulse width; a voltage generator generating a plurality of voltages; a selector selecting a voltage from the plural voltages generated by said voltage generator and outputting the voltage; an additional pulse register in which a first voltage of a first additional pulse is registered, the first additional pulse being to be added to said pulse width; and a voltage controller that controls the voltage outputted by said selector and a period in which the voltage is output, according to a cycle detection signal outputted by said cycle detector, a pulse width detection signal outputted by said pulse width detector, and the first voltage outputted by said additional pulse register, wherein said voltage controller controls said selector so as to add the first additional pulse to an end of said pulse width.