Patent ID: 8101435

Claim:
A fabrication method for a semiconductor device having a layered structure, the fabrication method comprising: preparing a first layered structure, the first layered structure including a support substrate, a semiconductor chip on the support substrate, a lower insulation layer over the semiconductor chip, a basic conductive element that penetrates through the lower insulation layer and reaches the semiconductor chip, and a basic interconnection pattern on the lower insulation layer such that the basic interconnection pattern is connected with the semiconductor chip via the basic conductive element; inspecting characteristics of the semiconductor chip via at least a part of the basic interconnection pattern; forming an upper insulation layer on a remaining part of the lower insulation layer when it is determined that the semiconductor chip possesses predetermined characteristics, the upper insulation layer having the same thickness as the basic interconnection pattern on the lower insulation layer; forming another layered structure on the upper insulation layer and the basic interconnection pattern, said another layered structure including another semiconductor chip on the upper insulation layer and the basic interconnection pattern, an additional lower insulation layer over said another semiconductor chip and the upper insulation layer, an additional conductive element that penetrates through said additional lower insulation layer and reaches the another semiconductor chip, a connection conductive element that penetrates through said additional lower insulation layer and reaches the basic interconnection pattern, and an additional interconnection pattern that is connected with said another semiconductor chip via said additional conductive element and connected with the basic interconnection pattern via the connection conductive element; inspecting characteristics of said another semiconductor chip via at least a part of said additional interconnection pattern; and forming an additional upper insulation layer having the same thickness as said additional interconnection pattern on said additional lower insulation layer when it is determined that said another semiconductor chip possesses predetermined characteristics.