Patent ID: 8828743

Claim:
A method for fabricating a memory array device comprising: forming a plurality of field effect transistor (FET) layers over a substrate; forming a plurality of memory element layers over the plurality of FET layers, wherein each of the memory element layers is epitaxially grown; forming a plurality of memory cell pillars by etching a plurality of column trenches and row trenches through the memory element layers and FET layers, such that each memory cell pillar includes a FET and a memory element, the row trenches configured along a first axis in parallel and the column trenches configured along a second axis in parallel, wherein the first axis is perpendicular to the second axis; forming a plurality of gate conductors within the row trenches, such that each FET of the memory cell pillars is adjacent to two gate conductors; forming a plurality of bit lines configured along the second axis in parallel, wherein each bit line is electrically coupled to a plurality of memory elements along the second axis forming a seed layer over the FET layer; epitaxially growing a free-magnetic layer over the seed layer, the free-magnetic layer including a ferromagnetic material; epitaxially growing a tunnel barrier over the free-magnetic layer, the tunnel barrier including a multiferroic material, wherein the tunnel barrier being situated between the free-magnetic and fixed-magnetic layers; and epitaxially growing a fixed-magnetic layer over the tunnel barrier, the fixed-magnetic layer including at least one of a ferromagnetic material and an antiferromagnetic material.