Patent ID: 7966446

Claim:
A memory system, comprising: a controller for generating a control signal; and a memory module, the memory module comprising: a primary memory, directly coupled to the controller external to the memory module, for receiving the control signal from the controller using a first signal transfer protocol; and a secondary memory coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory using a second signal transfer protocol, and communicating with the controller through the primary memory; wherein: the control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be simultaneously performed by the other of the primary and secondary memories, wherein the control signal comprises a packet that includes a first command that is executed by the primary memory to perform the one of the background operation and the foreground operation and a second command that is executed by the secondary memory to simultaneously perform the other of the background operation and the foreground operation, and the first and second signal transfer protocols are different, wherein the first signal transfer protocol transfers a first quantity of bits substantially simultaneously, and the second signal transfer protocol transfers a second quantity of bits substantially simultaneously, and wherein the first quantity of bits are transferred by the first signal transfer protocol between the primary memory and the controller, and the second quantity of bits are transferred by the second signal transfer protocol between the primary memory and the secondary memory in a same clock cycle, wherein the second signal transfer protocol is an at least partially serialized version of the first signal transfer protocol.