Patent ID: 8861611

Claim:
A method of operation within an integrated circuit device having a plurality of processing lanes, the method comprising: summing a first number of bits among one or more first data words associated with a first processing lane of the plurality of processing lanes; summing a second number of bits among one or more second data words associated with a second processing lane of the plurality of processing lanes; determining whether the first number of bits is an exact multiple of a predetermined data word length; in response to determining that the first number of bits is not an exact multiple of the predetermined data word length, combining certain bits of the first processing lane with bits of the second processing lane; generating a first sub-stream of data in the first processing lane of the plurality of processing lanes; generating a second sub-stream of data in the second processing lane of the plurality of processing lanes, wherein the first and second sub-streams are of variable lengths; and outputting at least the first and second sub-streams as a single bitstream; wherein: generating the first sub-stream of data comprises packing first consecutive data words among the one or more first data words associated with the first processing lane, excluding the certain bits combined with bits of the second processing lane, into one or more first packs associated with the first processing lane, wherein a third number of bits of the one or more first packs associated with the first processing lane is the exact multiple of the predetermined data word length; and generating the second sub-stream of data comprises packing second consecutive data words among the one or more second data words associated with the second processing lane, including the certain bits combined with bits of the second processing lane, into one or more second packs associated with the second processing lane; the method further comprising: determining a first number of packs among the one or more first packs associated with the first processing lane; associating the first number of packs with a first used field of the first processing lane; determining a second number of packs among the one or more second packs associated with the second processing lane; and associating the second number of packs with a second used field of the second processing lane; wherein outputting at least the first and second sub-streams as the single bitstream comprises storing the one or more first packs of the first sub-stream in a variable record length memory based at least in part on the first used field of the first processing lane; and wherein outputting at least the first and second sub-streams as the single bitstream further comprises storing the one or more second packs of the second sub-stream in the variable record length memory based at least in part on the second used field of the second processing lane.