Patent ID: 8081503

Claim:
Circuitry, comprising: address decoder and data register circuitry responsive to control signals; and an array of memory elements, each memory element having only five transistors, wherein the five transistors in each memory element include an address transistor and four transistors configured to form a bistable memory element that is addressed by the address transistor, wherein the address decoder and data register circuitry is configured to clear the array of memory elements by loading a given data value into the memory elements, wherein the address decoder and data register circuitry includes an address decoder having a control input path operable to receive a clear control signal and has a plurality of address output lines that are coupled to the address transistors, wherein the address decoder comprises a decoder output stage operable to receive an address output enable signal, and wherein the address decoders supplies a first logic value to all of the plurality of address output lines when the address output enable signal is deasserted and supplies a second logic value different than the first logic value to all of the plurality of address output lines when the address output enable signal is asserted.