Patent ID: 8418102

Claim:
A method of reducing sequential overhead in a latching circuit design by adjusting rising and falling data setup times and clock to Q delays of rising and falling data transitions in a computer, wherein said computer performs the processes comprising: creating an initial latching circuit design in said computer using a device library; using library test cells of said device library in said computer to determine slew rates for combinational logic in said initial latching circuit; using said slew rates for said combinational logic of said initial latching circuit to determine said rising and falling data setup times and clock to Q delays of said rising and falling data transitions in said computer; altering device widths of said combinational logic of said initial latching circuit design in said computer to alter said slew rates so that said rising and falling data setup times are substantially equal, said clock to Q delays are substantially equal for said rising and falling data transitions, and said clock to Q delays are not increased by more than approximately ten percent, to generate a latching circuit design in said computer that is substantially polarity independent and has reduced sequential overhead.