Patent ID: 7194650

Claim:
A system for coordinating synchronizer controllers disposed in a clock synchronizer arrangement, said clock synchronizer arrangement for effectuating data transfer between a core clock domain and a bus clock domain wherein said core clock domain is operable with a core clock signal and said bus clock domain is operable with a bus clock signal, said core and bus clock signals having a ratio, comprising: means disposed in a bus clock synchronizer controller portion for generating a set of inter-controller clock relationship control signals, said means in said bus clock synchronizer controller portion being operable responsive to a SYNC pulse that is sampled in said bus clock domain by said bus clock signal; and means disposed in a core clock synchronizer controller portion operating responsive to said set of inter-controller clock relationship control signals for synchronizing cycle and sequence information associated with said core clock signal relative to said bus clock signal, wherein said means in said core clock synchronizer controller portion is operable responsive to said SYNC pulse that is sampled in said core clock domain by said core clock signal.