Patent ID: 7319611

Claim:
A memory array comprising: a buried diffusion region; a first source line that supplies electrical power to the buried diffusion region; a second source line that supplies electrical power to the buried diffusion region, the second source line being generally parallel to and spaced apart from the first source line; a first bitline transistor having a first channel width, the first bitline transistor being disposed between the first and second source lines and proximate to the first source line and being electrically coupled to a first memory cell disposed in the buried diffusion region; and a second bitline transistor having a second channel width, the second bitline transistor being proximate to the first bitline transistor and being electrically coupled to a second memory cell disposed in the buried diffusion region, the second bitline transistor being disposed between the first and second source lines farther from the first source line than the first bitline transistor, the second channel width being greater than the first channel width.