Patent ID: 7370132

Claim:
A bus interface for an integrated circuit, comprising: a plurality of serial data lanes in which each serial data lane that is active requires a clock signal for operation; a link state machine for implementing a bus protocol to associate said serial data lanes to form a data link with a corresponding bus interface of a link partner; a link width controller for adjusting the link width of said data link; a clock tree having a sequence of clock buffers and taps for distributing clock signals from a master clock to said plurality of serial data lanes; and a buffer controller controlling individual clock buffers in said clock tree; said bus interface having a mode of operation in which, for a link width less than a maximum link width, clock buffers not required to service active data lanes are placed in a quiescent state; wherein for said mode of operation said bus interface generates an assignment of active data lanes to reduce clock buffer power in which a logical-to-physical lane reassignment is performed to reduce the number of buffers required to be in an active state while maintaining a logical assignment of data lanes.