Patent ID: 7410856

Claim:
A method of forming a vertical transistor comprising: forming a first semiconductive pillar elevationally above a first transistor source/drain in a semiconductive substrate and laterally between a second semiconductive pillar and a third semiconductive pillar, the first pillar being closer to the second pillar than to the third pillar, thus, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars; forming a gate insulator over opposing sidewalls of the first pillar within the first and second recesses; forming a transistor front gate and a transistor back gate over the gate insulator and over respective opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material in a manner such that residual gate conductor material substantially fills the first recess, forming the back gate, and only partially fills the second recess, forming the front gate; forming element isolation material within the second recess between the front gate and the third pillar and elevationally above the front gate and the back gate; and forming a second transistor source/drain elevationally above the first source/drain and providing a transistor channel in the first pillar, the channel being operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.