Patent ID: 7707536

Claim:
A method for selecting routes for nets interconnecting terminals of circuit devices within an area of an integrated circuit, the method comprising the steps of: a. iteratively partitioning the area into progressively smaller tiles utilizing a computer, at least three times, until the tiles reach a predetermined minimum size, b. after each partitioning iteration at step a, selecting each net that must pass between tiles and has not yet been routed, determining whether each selected net can be routed without altering routing of any previously routed net and, if so, selecting a route for the selected net, c. following step b, iteratively merging tiles into progressively larger tiles at least three times until the tiles reach a predetermined maximum size; and d. before each merging iteration at step c, selecting each net that need not pass between tiles and has not yet been routed, determining whether each selected net can be routed if routing of a previously routed net is altered and, if so, altering the routing of said previously routed net to accommodate a route for the selected net and selecting a route for said selected net.