Patent ID: 7339831

Claim:
A non-volatile semiconductor memory device having a normal writing mode and an accelerated writing mode, comprising: a memory block including a plurality of memory cells storing data in a non-volatile manner; a buffer storage having write data initially set in writing and temporarily holding data; a verify circuit outputting information for applying a writing pulse to said memory block upon receiving read data from said memory block and a value held in said buffer storage, said verify circuit performing a first operation to compare said value held in said buffer storage with said read data for update of the value held in said buffer storage so as to output said information and a second operation to output said value held in said buffer storage as it is as said information; and a control portion controlling said verify circuit wherein said control portion causes output of said information for a first writing pulse by causing said verify circuit to perform said first operation in said normal writing mode, and causes output of said information for the first writing pulse by causing said verify circuit to perform said second operation in said accelerated writing mode.