Patent ID: 7573739

Claim:
A memory device comprising: a substrate; a bit line on the substrate extending in a first direction; a first word line structure on the bit line and spaced apart from, and insulated from, the bit line, the first word line structure extending in a second direction transverse to the first direction; an electrode coupled to the bit line extending over the first word line structure and spaced apart from the first word line structure by a first gap; and a second word line structure over the electrode and spaced apart from the electrode by a second gap, the second word line structure extending in the second direction, wherein the electrode is cantilevered between the first word line structure and the second word line structure such that the electrode deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.