Patent ID: 7321142

Claim:
A field effect transistor, comprising: a semiconductor substrate having a main surface; a first semiconductor layer of a first conductivity type formed on the main surface of said semiconductor substrate; a second semiconductor layer of a second conductivity type formed on said first semiconductor layer; a third semiconductor layer of the first conductivity type formed on said second semiconductor layer; a pair of source and drain region layers formed in said third semiconductor layer separated by a prescribed distance from each other; and a gate region layer formed at a part of a region of said third semiconductor layer between said pair of source and drain region layers, wherein said first semiconductor layer includes a buffer layer formed on a side where said third semiconductor layer is positioned and having a first impurity concentration, and an electric field relaxation layer formed at a region between said buffer layer and said semiconductor substrate so as to contact said semiconductor substrate and having a second impurity concentration being higher than said first impurity concentration.