Patent ID: 8687450

Claim:
A semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address, the semiconductor device comprising: a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted, a toggle control unit configured not to toggle a sub word line driving signal when the activated toggle control signal is inputted and toggle the sub word line driving signal when the deactivated toggle control signal is inputted in case where a mat select signal of a corresponding mat is activated.