Patent ID: 7730456

Claim:
A method, in a computer system having at least a processor and memory, the method comprising: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective participating sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; issuing one or more requests for response from the main processing unit associated with the given sub-processing unit to one or more of the participating sub-processing units; receiving one or more responses at the main processing unit from one or more of the participating sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more of the participating sub-processing units that responded to the requests for response based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; performing at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit; determining communications requirements, including at least one of communication bandwidth and communication latency, needed between the given sub-processing unit and the participating sub-processing units to share processing results with the given sub-processing unit; accumulating communications information in one or more of the requests for response, the communications information being indicative of at least one of communications latencies and communications bandwidths associated with any communications interfaces encountered by the respective requests for response as they travel from the main processing unit to the one or more of the participating sub-processing units; and selecting one or more of the participating sub-processing units for re-allocation of the processor tasks of the given sub-processing unit based on a comparison of the processor loads of the processor tasks of the given sub-processing unit, the respective processor loads for the participating sub-processing units issuing responses, the communications requirements, and the accumulated information.