Patent ID: 8190839

Claim:
A multi-processor computer system for managing physical memory domains, the system comprising: a processor having an address interface for sending a memory access message including an address in physical memory and a domain identification (ID); a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses; a domain mapping unit (DMU) having an interface to accept the memory access message from the processor, the DMU using the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain; and, wherein the DMU accents a first memory access message from a first processor, with a first address in physical memory and a first domain ID. and a second memory access message from a second processor, with a second address in physical memory and a second domain ID, the DMU using the first and second domain IDs to access the permission list, and granting access to the first and second addresses in response to the permission list locating the first and second addresses in a shared domain cross-referenced to the first and second domain IDs.