Patent ID: 8248132

Claim:
An oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch, the oscillation signal generator comprising: a first latch configured to generate an I oscillation signal; a second latch that is cross-coupled with the first latch and generates a Q oscillation signal; and a phase compensator connected to at least one of the first latch or the second latch, wherein the first latch comprises: a first I differential transistor pair configured to operate in response to a clock signal; and a second I differential transistor pair configured to operate in response to a complementary clock signal, the second latch comprises: a first Q differential transistor pair configured to operate in response to the complementary clock signal; and a second Q differential transistor pair configured to operate in response to the clock signal, and the phase compensator complementarily adjusts a bias current of the first I differential transistor pair and a bias current of the second I differential transistor pair and/or complementarily adjusts a bias current of the first Q differential transistor pair and a bias current of the second Q differential transistor pair, wherein the phase compensator comprises: a first offset current source that is connected to a first common node of the first I differential transistor pair and supplies a first offset current to the first common node; and a second offset current source that is connected to a second common node of the second I differential transistor pair and supplies a second offset current to the second common node.