Patent ID: 7057964

Claim:
A semiconductor memory device comprising: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses from the plurality of address input pads and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part to output the first addresses as the data access addresses or to output a combination of the first addresses and the second addresses as the data access addresses.