Patent ID: 8058689

Claim:
A method of RF isolating a semiconductor feature of an integrated circuit comprising: forming a buried insulation layer over a semiconductor substrate; forming a first semiconductor feature in one or more semiconductor layers so that the first semiconductor feature is formed over a first portion of the buried insulation layer, wherein the buried insulation layer has a first trench therethrough down to the semiconductor substrate that substantially encloses the first portion of the buried insulation layer, wherein the one or more semiconductor layers has a first trench therethrough that substantially encloses the semiconductor feature, and wherein the first trench through the one or more semiconductor layers substantially aligns with the first trench through the buried insulating layer; filling the first trench through the one or more semiconductor layers and the first trench through the buried insulating layer with conducting material having low resistivity so that a first conductive guard ring substantially surrounds the first semiconductor feature; forming a second semiconductor feature in the one or more semiconductor layers so that the second semiconductor feature is formed over a second portion of the buried insulation layer, wherein the buried insulating layer has a second trench therethrough down to the semiconductor substrate that substantially encloses the second portion of the buried insulation layer, wherein the one or more semiconductor layers has a second trench therethrough that substantially encloses the second semiconductor feature, and wherein the second trench through the one or more semiconductor layers is substantially aligned with the second trench through the buried insulating layer; filling the second trench through the one or more semiconductor layers and the second trench through the buried insulating layer with conducting material having low resistivity so that a second conductive guard ring substantially surrounds the second semiconductor feature; and forming a third conductive guard ring between the first and second conductive guard rings, the third conductive guard ring being in contact with the semiconductor substrate.