Patent ID: 8119454

Claim:
A method of manufacturing a fan-out wafer level package, the method comprising: forming a cavity in a substrate, the cavity having an opening, sidewalls, and a top surface; affixing double-sided tape to at least a portion of a bottom surface of an integrated circuit, wherein there is a bond pad on a top surface of the integrated circuit; placing the integrated circuit having the double-sided tape within the opening of the cavity and forming gaps between the sidewalls of the cavity and adjacent sidewalls of the double-sided tape, wherein at least a portion of the double-sided tape contacts at least a portion of the top surface of the cavity in a central region of the cavity, and wherein the sidewalls of the cavity are spaced from the adjacent sidewalls of the double-sided tape; forming a first dielectric layer that covers substantially all of a top surface of the substrate and that fills the gaps between the sidewalls of the cavity and the adjacent sidewalls of the double-sided tape; forming a redistribution layer over at least a portion of the first dielectric layer, wherein the redistribution layer is configured to electrically couple the bond pad of the integrated circuit to a redistributed bond pad; and forming a bump at the redistributed bond pad.