Patent ID: 8030113

Claim:
A method of fabricating a semiconductor structure, comprising the steps of: providing a first chip with at least one first electronic device; providing a second chip with at least one second electronic device and a through silicon via electronically connected to said at least one second electronic device; forming a thermoelectric plate with a through silicon via, said thermoelectric plate located between said first and second chip and separated from said first chip by a first coupling layer and separated from said second chip by a second coupling layer; depositing a first conducting layer on top of said first coupling layer and a thermoelectric material on top of said first conducting layer; forming a thermoelectric plate core, by creating a plurality of openings that expose said first coupling layer at locations reserved for N-type and P-type semiconductor regions and a location reserved for said through silicon via of said thermoelectric plate, said location reserved for said through silicon via of said thermoelectric plate aligned with both said first electronic device and said through silicon via connected to said second electronic device; filling said openings with dielectric; doping said thermoelectric layer at either side of locations reserved for N-type and P-type semiconductor regions with one of P-type elements and N-type elements; and depositing a second conducting layer on top of said formed thermoelectric plate core.