Patent ID: 7006403

Claim:
A CMOS bit decoder comprising: a pulse stretcher stretching clock pulses; a dynamic bit decode selectively passing stretched said clock pulses responsive to a column address, said dynamic bit decode comprising: an n bit address decode connected between a decode node and a common source node, a restore FET connected between a supply and said decode node, a complementary pair of enable FETs, a first of said complementary pair being connected between said supply and a decode out of said bit decode, a second of said complementary pair being connected between a supply return and said common source node, the gate of said restore FET and of each of said complementary pair being connected to an output of said pulse stretcher, a decode out FET connected between said decode out and said common source node, said decode node being connected to the gate of said decode out FET, and a first pseudo latch FET connected between said supply and said decode node and gated by said decode out; and a column driver receiving passed said stretched clock pulses and driving said column select pulses responsive to received said stretched clock pulses.