Patent ID: 7148536

Claim:
Dynamic random access memory circuitry comprising: a semiconductor substrate; word lines received over the semiconductor substrate; an insulative layer received over the word lines and the substrate, the insulative layer having at least a single well formed therein, the well comprising a base of said insulative layer received directly over the word lines, the insulative layer within which said well is formed peripherally defining an outline of a memory array area, area peripheral to the well comprising memory peripheral circuitry area, said insulative layer of the well having a substantially planar base; a plurality of memory cell storage capacitors received within said single well, the memory cell storage capacitors respectively comprising a storage node, the storage node comprising a portion having a container shape, said container-shaped portion of the storage node being received partially within the insulative layer through the insulative layer base of the well; and peripheral circuitry within the peripheral circuitry area operatively configured to write to and read from the memory array.