Patent ID: 7646623

Claim:
A ferroelectric memory device comprising: a memory cell having a transistor and a ferroelectric capacitor connected in series between a bit line and a plate line, and a connecting section below the ferroelectric capacitor; a dummy cell having a transistor, a ferroelectric capacitor and a connecting section, the dummy cell having an electrically disconnected section among the bit line, the transistor, the ferroelectric capacitor, the connecting section and the plate line, and the transistor of the dummy cell having a gate electrode, an isolation dielectric film formed below the gate electrode, and a source/drain region formed on each side of the gate electrode, a width of the isolation dielectric film being greater than a width of the gate electrode such that an end section of the gate electrode is separated from an end section of the source/drain region by a distance corresponding to a difference between the width of the isolation dielectric film and the width of the gate electrode.