Patent ID: 6930904

Claim:
An electronic circuit comprising: a memory controller mounted on a printed circuit board (PCB) having a first plurality of transmission lines; a memory module, the memory module coupled to the memory controller by the first plurality of transmission lines, wherein the memory module includes: a first memory bank coupled to the first plurality of transmission lines by a second plurality of transmission lines, wherein the first plurality of transmission lines is coupled to the second plurality of transmission lines by a connector; a second memory bank coupled to the first memory bank by a third plurality of transmission lines; a fourth plurality of transmission lines coupled to the second memory bank, wherein each of the fourth plurality of transmission lines is terminated with a resistor; and a buffer circuit, and wherein each of the plurality of control lines and each of the plurality of address lines is coupled between the connector and the buffer circuit by a first pair of transmission stubs and a damping resistor between each of the first pair of transmission stubs, wherein the buffer circuit is coupled to the first memory bank by a second pair and a third pair of transmission stubs, wherein each of the third pair of transmission stubs is coupled to a pin of a first memory chip; wherein the PCB and the memory module each include a plurality of control lines and a plurality of address lines, wherein each of the control and address lines is coupled between the memory controller and the memory module, wherein each of the plurality of control lines and plurality of address lines of the PCB is coupled to one of the plurality of control lines and one of the plurality of address lines on the memory module by the connector; and wherein each of the first, second, and third plurality of transmission lines is part of a bus.