Patent ID: 7580496

Claim:
A circuit for receiving digital data arriving in series comprising: a circuit for generating a reference clock, comprising two settable delay means receiving a base clock, the difference between the maximum and minimum delays of each delay means being greater than one period of the base clock, a multiplexer selecting the output signal of one or the other of the delay means, control means for, according to whether the reference clock frequency must be smaller or greater than the base clock frequency, increasing or decreasing at the rate of the base clock or at a multiple of this rate the delay of the selected delay means, and controlling a minimum or maximum delay for the non-selected delay means, and a phase comparator capable of changing the multiplexer selection when the transitions of the signals output by the delay means corresponding to a same transition of the base clock are shifted by a duration greater than or equal to one period of the base clock; a circuit for oversampling the received data memorizing the samples sampled at the rate of several clocks phase-shifted with respect to the reference clock, the oversampling circuit comprising means for selecting and providing as output data samples representative of the received data; and a detection circuit identifying the variations of the phase shift between the reference clock edges and the transitions of the received data by analyzing the memorized samples, the detection circuit controlling a variation of the reference clock frequency when the phase shift variations are repeated over several sampling cycles.