Patent ID: 8456901

Claim:
A memory system comprising: a processor; and a memory array communicatively connected to the processor, the memory array comprising: a first memory cell comprising: a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT E ) and a second terminal; and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device; and a second memory cell comprising: a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT 0 ) and a second terminal; and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.