Patent ID: 7061815

Claim:
A semiconductor memory device providing row/column redundancy, comprising: a plurality of data latches arranged in a row-column matrix connected to a set of bitlines/global bitlines interfacing to read/write circuitry; at least two redundant rows/columns connected to a bitline/global bitline and to at least two redundant wordlines; first means for providing a first faulty row/column address in said row-column matrix; second means for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from one of the addresses provided by the first means; a comparison circuitry receiving its inputs from the accessed row/column address and the faulty row/column addresses and; a control block connected to the said comparison circuitry that receives a control signal to enable/disable one of the redundant rows/columns and/or another memory cell row/column corresponding to the other faulty row/column addresses depending upon signals received from said comparison circuitry and a control signal for normal operation of the memory device.