Patent ID: 7378320

Claim:
A method for fabricating a MOS (metal oxide semiconductor) transistor, comprising: forming a gate structure within a trench that is formed within a well doped with a first dopant of a first conductivity type; forming a gate dielectric at walls of the trench such that the gate dielectric is disposed between the gate structure and the well within the trench; implanting a second dopant of the first conductivity type to form a channel stopping region at a first side of the trench, wherein the depth of the channel stopping region extends beyond the depth of the trench, and wherein the channel stopping region is formed to abut the gate dielectric down to the whole death of the trench; and implanting a third dopant of a second conductivity type that is opposite of the first conductivity type to form a first source/drain within the channel stopping region; wherein a portion of the trench abuts the well for forming a channel of the MOS transistor.