Patent ID: 7394696

Claim:
A NAND type non-volatile memory device comprising: a plurality of active regions arranged at equal intervals on a substrate, extending along a first direction, and doped with a first conductive type dopant; first and second select gate lines, running substantially parallel to each other, crossing over the plurality of active regions; a plurality of cell gate lines crossing over the plurality of active regions between the first and second select gate lines; a cell doping region formed at each of the plurality of active regions on two sides of each of the plurality of cell gate lines, and doped with a second conductive type dopant; a plurality of contact plugs penetrating an interlayer insulation layer covering the substrate to contact the plurality of active regions respectively at one side of the first select gate line, and arranged at the equal intervals along a second direction perpendicular to the first direction; and a plurality of wiring lines arranged at the equal intervals on the interlayer insulation layer, substantially parallel to the plurality of active regions, and connected to the plurality of contact plugs respectively, the wiring lines including bit lines, and one or more well bias lines adjacent thereto.