Patent ID: 8318559

Claim:
A method of fabricating CMOS transistor, comprising: providing a substrate comprising a first conductive type MOS device region and a second conductive type MOS device region, the substrate further comprising a second conductive type well disposed in the first conductive type MOS device region, and a first conductive type well disposed in the second conductive type MOS device region; forming a plurality isolation structures on the surface of the substrate; forming a gate structure in the first conductive type MOS device region and a gate structure in the second conductive type MOS device region; forming two lightly doped drains in the second conductive type well by both sides of the gate structure in the first conductive type MOS device region by implanting; forming two second conductive type pocket doped regions in the second conductive type well by both sides of the gate structure in the first conductive type MOS device region by implanting; forming two second conductive type deep halo doped regions spaced apart from said two lightly doped drains in the second conductive type well by both sides of the gate structure in the first conductive type MOS device region by implanting; forming spacers along both sides of the gate structure in the first conductive type MOS device region and along both sides of the gate structure in the second conductive type MOS device region; and forming two source/drain doped regions in the second conductive type well by both sides of the spacers of the gate structure in the first conductive type MOS device region by implanting.