Patent ID: 7296128

Claim:
A nonvolatile memory comprising: a plurality of pages storing data; a page buffer temporarily storing data by the page; a correction circuit for correcting a bit error of source data of a specific one of the pages; a transferring circuit configured to provide the source data to the correction circuit from the page buffer and to provide amended data to the page buffer from the correction circuit after the correction circuit has corrected the bit error; and a replicating circuit configured to copy the source data into the page buffer and to store the amended data into another page from the page buffer; wherein: the source data contains old parities; the correction circuit for generating new parities from the source data, and compares the new parities with the old parities; the correction circuit comprises a circuit for generating column parities for bits composing one byte of the source data; and a circuit for generating line parities for bytes of the source data; and for a one bit error in the source data, the line parities indicate a binary weighted line address and its complement of the one bit error in the page buffer, and the column parities indicate a binary weighted column address and its complement of the one bit error in the page buffer.