Patent ID: 6954091

Claim:
A phase-locked loop (PLL) comprising: a range select input; a clock output; a phase/frequency detector having a reference input and a feedback input; a charge pump coupled to an output of the phase/frequency detector; a loop filter coupled to an output of the charge pump; a voltage-controlled oscillator CVCO) circuit coupled to the loop filter and comprising a plurality of VCOs, which are selectively coupled between the loop filter and the clock output as a function of the range select input and have different output frequency ranges; and a plurality of voltage level shifters, wherein each voltage level shifter is coupled between a respective one of the VCO's and the clock output and is adapted to convert differential signals produced at an output of the respective VCO into a digital logic level signal, and wherein each voltage level shifter comprises a power down input and at least one current source or voltage bias generator, which is enabled and disabled by the power down input.