Patent ID: 7709319

Claim:
A method of manufacturing a semiconductor device, comprising: forming a mold layer on a substrate on which a cell area, a peripheral area and a boundary area separating the cell area and the peripheral area are defined; etching the mold layer to form a first mold pattern including electrode openings in the cell area that expose regions of the substrate, a boundary opening in the boundary area that exposes an extended region of the substrate adjacent the peripheral area and a residual mold layer remaining in the peripheral area; forming a layer of a first conductive material on inner sidewalls of the electrode openings and on an extended inner sidewall of the boundary opening; forming a sacrificial layer on the first conductive material; removing an upper portion of the sacrificial layer and an upper portion the first conductive material to expose a top surface of the first mold pattern and a top surface of the residual mold layer and to isolate portions of the first conductive material in the electrode openings and the boundary opening; forming a hard mask pattern that covers the residual mold layer and exposes residual portions of the sacrificial layer formed in the boundary area and the cell area and the first mold pattern formed in the boundary area and the cell area; removing the residual portions of the sacrificial layer formed in the boundary area and the cell area and the first mold pattern formed in the boundary area and the cell area using the hard mask pattern as an etch mask, thereby exposing the first conductive material and forming lower electrodes in the electrode holes and a dummy pattern in the boundary opening; removing the hard mask pattern to expose the residual mold layer and form a second mold pattern; and sequentially forming a dielectric layer and an upper electrode on the lower electrodes and the second mold pattern.