Patent ID: 7282443

Claim:
A method of forming a low electrical resistance metal silicide, comprising: forming a first metal silicide layer over a substrate, the first metal silicide layer having a melting point higher than 1700° C. and being metal-enriched, the first metal silicide layer having a thickness of at least about 50 Å and comprising a predominate metal; depositing a metal-containing layer directly against the first metal silicide layer; the metal of the metal-containing layer predominately being a metal different than the predominant metal of the first metal silicide; forming a silicon-containing layer directly against the metal-containing layer and on an opposing side of the metal-containing layer from the first metal silicide layer; after forming the silicon-containing layer, converting the metal of the metal-containing layer to metal silicide to convert the metal-containing layer to a second metal silicide layer over the substrate; the second metal silicide layer having a bulk resistance of less than 30 micro-ohms-centimeter; the conversion of the metal of the metal-containing layer to the second metal silicide layer comprising incorporation of silicon from the silicon-containing layer into the second metal silicide layer; and patterning the first metal silicide layer, second metal silicide layer and silicon-containing layer into a line having substantially vertical sidewalls extending along the first metal silicide layer, second metal silicide layer and silicon-containing layer.