Patent ID: 8908352

Claim:
A chip type laminated capacitor comprising: a first outer electrode covering a first end of a ceramic body; a second outer electrode covering a second end of the ceramic body; a first inner electrode including a first capacitance forming part and a first leading part, the first leading part being connected to the first outer electrode; and a second inner electrode including a second capacitance forming part and a second leading part, the second capacitance forming part being overlapped with the first capacitance forming part, the second leading part being connected to the second outer electrode, wherein a margin unbalance rate X on an L-W plane of the ceramic body satisfies the following Equation: 5%≦X=|M1 /A 1 −M 2 /A 2 |/ave ( M 1 /A 1 ,M 2 /A 2)≦40% wherein M 1 represents a length of a first margin defined by a length between an end of the first capacitance forming part and the second end of the ceramic body on the L-W plane, M 2 represents a length of a second margin defined by a length between an end of the second capacitance forming part and the first end of the ceramic body on the L-W plane, A 1 and A 2 represent a length of first and second band parts of the first and second outer electrodes formed inwardly from the first and second ends of the ceramic body, respectively, on the L-W plane and ave is a function representing an average, ave (X, Y)=(x+y)/2.