Patent ID: 7307906

Claim:
A semiconductor storage device for rewritably storing data to each of unit blocks into which a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines is divided, comprising: two rows of sense amplifiers arranged on one side and an other side of said plurality of bit lines in each said unit block and each including a plurality of sense amplifiers for amplifying data of said plurality of memory cells through said plurality of bit lines; a switch means for switching a connecting state between one of said two rows of sense amplifiers and one side of said plurality of bit lines and switching a connecting state between an other of said two rows of sense amplifiers and an other side of said plurality of bit lines; a control means which sets at least one of said two rows of sense amplifiers as a cache memory, and when performing refresh operation of said unit block in a state in which said row of sense amplifiers to be used as said cache memory holds data, controls said switch means so that said row of sense amplifiers to be used as said cache memory is disconnected from said plurality of bit lines and only said row of sense amplifiers not to be used as said cache memory is used in refresh operation.