Patent ID: 7583538

Claim:
A semiconductor memory comprising a memory cell which is a MOSFET formed on an SOL substrate and having a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region, wherein an operation of reading out data written in said memory cell is performed under a biasing condition by which relationships Vd>Vg−Vth 0 and Vth 1 Vg≦Vth 0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth 1 of said MOSFET when a predetermined amount of holes are stored in a body region of said memory cell, and a threshold voltage Vth 0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in said body region.