Patent ID: 7387934

Claim:
A method for manufacturing a semiconductor memory comprising a memory cell matrix including a plurality of cell columns arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors serially arranged along a column-direction, the method comprising: forming a cell site gate insulator on a surface of a semiconductor substrate; forming a first conductive layer on a surface of the cell site gate insulator; selectively etching the first conductive layer, the cell site gate insulator and an upper portion of the semiconductor substrate so as to form a plurality of device isolation grooves running along the column direction, defining a plurality of ridges arranged alternatively between the device isolation grooves, each of the ridges made of the first conductive layer, the cell site gate insulator and the upper portion of the semiconductor substrate; filling a plurality of device isolation films in the device isolation grooves so as to isolate electrically the cell columns; forming a plurality of lower inter-electrode dielectrics on the corresponding first conductive layers so that each of the lower inter-electrode dielectrics is isolated from other lower inter-electrode dielectrics belonging to other cell columns, each of the lower inter-electrode dielectrics is made of insulating material containing at least silicon and nitrogen; forming an upper inter-electrode dielectric arranged both on the device isolation films and the lower inter-electrode dielectric so that the upper inter-electrode dielectric can be shared by different cell columns, the upper inter-electrode dielectric is made of insulating material different from the lower inter-electrode dielectrics; and forming a second conductive layers on the upper inter-electrode dielectric.