Patent ID: 7746722

Claim:
A computer-implemented method of implementing a self-timed memory in an integrated circuit comprising: receiving design characteristics for an integrated circuit application requiring a memory space; providing an integrated circuit layout of a memory array having a first side; selecting a portion of the memory array to be used as the memory space for the integrated circuit application; receiving a desired word size for the memory space; generating a programmable logic circuit coupled to the portion of the memory array such that the programmable logic circuit allows the portion of the memory array to be accessed using the desired word size; incorporating into the integrated circuit layout a self-timing signal-producing circuit located at the first side; incorporating into the integrated circuit layout a self-timing signal-reading circuit located at the first side; and incorporating into the integrated circuit layout a routing path connecting the self-timing signal-producing circuit to the self-timing signal-reading circuit, wherein the routing path extends into the memory array for a sufficient length such that a signal produced by the self-timing signal-producing circuit and detected by the self-timing signal-reading circuit approximates timing behavior of the memory array.