Patent ID: 8455312

Claim:
A multiple-exposure patterning method using a single photomask for forming a T-gate or inverted L-gate structure for an electronic device and a circuit, comprising: a) providing a semiconductor substrate having a semiconductor layer structure, b) depositing a first resist layer having a first thickness and a first minimum development dosing requirement on said semiconductor substrate, c) depositing a second resist layer having a second thickness and a second minimum development dosing requirement on said first resist layer, thereby forming a dual resist layer, d) providing a single photomask having a transparent window, said transparent window being aligned to a first region on a surface of said second resist layer, e) providing a light beam having a length and a width to said first region, said length and width being defined by said transparent window of said photomask, to a region on the surface of said second resist layer; f) first exposing a first portion of said dual resist layer by shining said light beam on said first region of said second resist layer surface to achieve a first exposure dose in said first portion of said dual resist layer to define a first cavity in the first resist layer for a stem portion of said gate structure, wherein said first exposure dose exceeds the first and the second minimum development dosing requirements; g) then shifting said semiconductor substrate by a distance not greater than said beam length so that said photomask window and said light beam are aligned to a second region on said second resist layer surface, exposing a second portion of said dual resist layer by shining said light beam on said second region of said second resist layer surface at a second exposure dose, wherein said second exposure dose exceeds said second minimum development dosing requirement and is below said first minimum development dosing requirement, h) aligning and exposing a plurality of second portions of said dual resist layer at the second exposure dose by repeating step g) in a successive manner on said second resist layer to define a second cavity for a head portion of said gate structure, i) developing the dual resist layer in a second developer to remove second resist material from said exposed plurality of portions of said second resist layer and to form said second cavity, j) developing the dual resist layer in a first developer to remove first resist material from said first portion of said first resist layer and to form said first cavity, k) depositing gate metal layers in the first and second cavities to form said gate structure, and l) carrying out a liftoff process to further form said gate structure.