Patent ID: 6838326

Claim:
A method for manufacturing a semiconductor device comprising the steps of: providing a semiconductor substrate having an element isolating film defining an active region; forming a dummy gate comprising a gate oxide film, a first polysilicon layer and a hard mask layer sequentially stacked on the active region; performing a thermal oxidation process to the overall surface to form a thermal oxide film on the sidewalls of the first polysilicon layer and on the both sides of the gate oxide film, wherein the thermal oxidation film on the both sides of the gate oxide film is thicker than the gate oxide film; forming a low concentration impurity region by performing a first ion implantation process on the entire surface including the dummy gate; forming an insulating film over the resulting structure; etching back the insulating film and the thermal oxide film on the semiconductor substrate to form an insulating film spacer on the sidewall of the dummy gate; forming a high concentration impurity region in the semiconductor substrate on the both sides of the dummy gate electrode by performing a second ion implantation process; forming a planarized interlayer insulating film for exposing the upper portion of the dummy gate; removing the hard mask layer to form groove exposing the first polysilicon layer; forming a Vth ion implantation region in a channel region of the semiconductor substrate by performing a third ion implantation process; subjecting the resultant structure to a thermal annealing process; sequentially forming a second polysilicon layer on the entire surface and a metal layer filling the groove; etching back the metal layer to form a recessed metal pattern in the groove; forming a third polysilicon layer overall surface of the resulting structure so as to fill the recess region in the groove; and planarizing the resultant to expose the interlayer insulating film.