Patent ID: 7687915

Claim:
A semiconductor device comprising: a semiconductor substrate having a crack stop region surrounding an active region; a plurality of interlayer insulating layers on the semiconductor substrate; first dual damascene patterns in the plurality of interlayer insulating layers, the first dual damascene patterns aligned perpendicularly to and exposing a first portion of the semiconductor substrate in the active region; a first opening extending through the plurality of interlayer insulating layers and exposing a second portion of the semiconductor substrate in the crack stop region; first dual damascene metal wirings disposed in the first dual damascene patterns, at least one of the first dual damascene metal wirings contacting the exposed first portion of the semiconductor substrate; and a single body first crack stop structure disposed in the first opening, the first crack stop structure contacting the exposed second portion of the semiconductor substrate, wherein each of the plurality of interlayer insulating layers includes a lower interlayer insulating layer and an upper interlayer insulating layer, and each of the first dual damascene patterns includes a first via in the corresponding lower interlayer insulating layer and a first trench in the corresponding tipper interlayer insulating layer.