Patent ID: 6840666

Claim:
A test configuration comprising: a. a display panel including: i. a plurality of source lines; ii. a plurality of control lines; iii. a plurality of common lines; iv. a two-dimensional array of display elements, each display element including a transistor and a capacitor, wherein the transistor has a first current-handling terminal connected to one of the source lines, a second current-handling terminal, and a control terminal connected to one of the control lines, and wherein the capacitor has a first capacitor terminal connected to the second current-handling terminal and a second capacitor terminal connected to one of the common lines; and v. a defect amid surrounding features; b. an infrared detector positioned to receive infrared radiation from the display panel, including infrared radiation from the defect and surrounding features; c. a signal generator having: i. a first test-signal output terminal connected to at least one of the source lines; ii. a second test-signal output terminal connected to at least one of the control lines; and iii. a third test-signal output terminal connected to at least one of the common lines; iv. wherein the signal generator simultaneously applies a first test vector on the first test vector output terminal, a second test actor on the second test-signal output terminal, and a third test vector on the third test-signal output terminal; v. wherein application of the first, second, and third test vectors heats the defect and surrounding features; and vi. wherein the detector captures a thermal image of the heated display, the thermal image including defect data representative of the defect and defect-artifact data representative of the surrounding features; and d. an image processor analyzing the defect-artifact data to locate the defect data within the defect-artifact data.