Patent ID: 7853954

Claim:
A microprocessor comprising: a pipeline, having a plurality of units, configured to process tasks; a task identification register configured to hold current task identification information; a task register configured to hold register information that is used while the plurality of units processes a task; a task completion detector configured to detect that the pipeline completes processing a first task that has already entered in an execution unit among of the plurality of units, if a switch instruction to a second task has is issued while the execution unit executes the first task; a task register manager configured to switch values of the task register to second register information, which is used while the second task is executed, if the task completion detector detects that the pipeline has completed processing the first task; a task manager configured to switch a value of the task identification information register to a second task identification information to identify the second task and to grant each of the units permission to execute the second task, if the task register manager switches to the second register information; a task setting device configured to set the units to stall an instruction fetch until the task register manager completely switches to the second register information after the switch instruction has issued; a switch flag specifying device configured to specify a switch flag to the first task, which is executed by the execution unit, after the switch instruction has issued, wherein the execution unit sends the first task and the switch flag to a next unit, and the task completion detector detects that the execution of the first task is completed if a last unit of the pipeline acquires the switch flag.