Patent ID: 7370182

Claim:
A method of handling branching instructions using a processor comprising a program memory storing program instructions, and a processor core comprising a plurality of processing units and a central unit connected thereto, the processing units comprising a first processing unit including at least one address-pointing register, the central unit issuing instructions to the processing units based upon the program instructions, the method comprising: clocking the processor core with a clock signal; receiving a branching instruction in the course of a current clock cycle, the branching instruction using a content of the at least one address-pointing register; executing the received branching instruction in the course of the current clock cycle; and checking validity of the content of the at least one address-pointing register at a start of the current clock cycle so that the branching instruction is received by the central unit and executed if the content is declared valid, and, in an opposite case, the branching instruction is kept on hold for executing until the content is declared valid.