Patent ID: 7816725

Claim:
A semiconductor device comprising: a dielectric film and an active pattern that are stacked in sequence on a substrate; a gate electrode crossing over the active pattern; a gate insulation film interposed between the gate electrode and the active pattern; a pair of impurity layers formed in the active pattern at both sides of the gate electrode, respectively, and defining a channel region in the active pattern under the gate electrode, the bottoms of the impurity layers contacting with the top of the dielectric film; and a field isolation film filling a trench formed in the substrate around the active pattern and covering sidewalls of the dielectric film and the active pattern, wherein excessive charges are stored in the channel region, such that the channel region is a data storage field of a volatile memory cell and the substrate is supplied with a voltage to provide attraction for the excessive charges stored in the channel region, wherein the top of the field isolation film is partially leveled lower than the top of the dielectric film and forms the bottom of a recess region, a sidewall of the recess region partially including a sidewall of the active pattern, and wherein the dielectric film partially extends along the bottom and sidewall of the recess region.