Patent ID: 7948588

Claim:
A thin film transistor (TFT) array panel comprising: a substrate; a gate line formed on the substrate and having a gate electrode; a storage electrode line formed on the substrate and having a storage electrode; a gate insulating layer formed on the storage electrode line and the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a data line formed on the gate insulating layer, connected to a source electrode extending over the semiconductor and extending substantially perpendicularly to the gate line; a drain electrode formed on the semiconductor, the drain electrode being positioned across the semiconductor from the source electrode and overlapping the storage electrode; a first insulating layer formed on the data line and the drain electrode and having a first contact hole extending through the first insulating layer to the drain electrode; a transmissive electrode formed on the first insulating layer and connected to the drain electrode via the first contact hole; a second insulating layer formed on the first insulating layer; a first reflective electrode connected to the transmissive electrode and defining a first reflective region; and a second reflective electrode separated from the transmissive electrode and the first reflective electrode and capacitively coupled to the drain electrode, the second reflective electrode defining a second reflective region, wherein the storage electrode and the drain electrode are located both in the first reflective region and the second reflective region, and wherein the second reflective electrode overlaps the drain electrode with the first and second insulating layers positioned therebetween, so as to form an auxiliary capacitor.