Patent ID: 8427876

Claim:
A semiconductor storage device comprising: a memory cell array comprising: a source line arranged in a row direction; a plurality of bit lines arranged in a column direction perpendicular to the row direction; a plurality of cell units arranged in the column direction, each of the cell units comprising: a memory cell group comprising a plurality of nonvolatile memory cells connected in series in the row direction; a first selection gate transistor connected to one end of the memory cell group such that the memory cell group is connected to a corresponding one of the bit lines; and a second selection gate transistor connected to the other end of the memory cell group such that the memory cell group is connected to the source line; a plurality of word lines arranged in the row direction, wherein control gates of the memory cells of the plurality of cell units, which are arranged in the same line, are connected through a corresponding one of the word lines; a selection gate line, wherein gates of the first or second selection gate transistors of the cell units are connected through the selection gate line; a high voltage generator that generate a high voltage from a supply voltage supplied from outside and provides the high voltage to the respective word lines; and a controller that controls the high voltage generator, wherein when a word line to which a data read voltage is to be applied is selected from the plurality of word lines, the controller controls the high voltage generator to: apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line; apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage; and apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word lines and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.