Patent ID: 7367009

Claim:
A method of performing optical and process correction (OPC) on two or more reticle layouts that are used to print a target layout of features on a wafer with a photolithographic process, comprising: dividing regions within the two or more reticle layouts into a number of edge fragments; dividing a target layout into a number of edge fragments; mapping edge fragments within the two or more reticle layouts to edge fragments in the target layout by: selecting a reticle edge fragment in one of the two or more reticle layouts; determining a point on the target layout that corresponds to a point on the selected reticle edge fragment; determining edge fragments within the target layout that are within a predetermined distance of the determined point on the target layout as potential edge fragments to map to the selected reticle edge fragments; and selecting one or more of the potential edge fragments within the target layout to map to the selected reticle edge fragment; simulating how the two or more reticle layouts will print the target layout on a wafer and determining an error of a target layout edge fragment in the simulated printing; and performing optical process and correction (OPC) to move the position of the mapped edge fragments in the two or more reticle layouts to reduce the error.