Patent ID: 7689942

Claim:
A method for optimizing an integrated circuit design, the method comprising: establishing an acyclic timing graph comprising a plurality of nodes and a plurality of directed edges, each node corresponding to a set of channel-connected components in an integrated circuit design and each directed edge corresponding to a path between a given pair of nodes; converting the timing graph to a move graph comprising a plurality of move nodes and the plurality of directed edges by converting each timing graph node to a corresponding move node and maintaining the directed edges between given pairs of timing graph nodes between the corresponding move nodes, each move node corresponding to a single design change in at least a portion of one of the channel-connected components in the corresponding timing graph node, the single design change affecting power consumption of the integrated circuit design; using the move graph to identify modifications to components in the integrated circuit design that reduce power consumption in the integrated circuit design without creating a timing violation; and modifying the integrated circuit design in accordance with the identified modifications.