Patent ID: 8405460

Claim:
Amplifier circuitry, comprising: first and second transistors that each have a gate terminal and that are coupled together in series between a positive power supply terminal at a first voltage and a ground terminal at a second voltage; bias circuitry that applies a third voltage to the gate terminals of the first and second transistors, wherein the third voltage is approximately midway between the first and second voltage; an input terminal that is coupled between the first and second transistors, wherein the input terminal is electrically isolated from the bias circuitry; a first resistor that is coupled in series between the positive power supply terminal and a first source-drain region of the first transistor; a second resistor that is coupled in series between a first source-drain region of the second transistor and the ground terminal; a third resistor that is coupled between a second source-drain region of the first transistor and the input terminal; a fourth resistor that is coupled between the input terminal and a second source-drain region of the second transistor, wherein the first transistor comprises a PMOS transistor, wherein the second transistor comprises a NMOS transistor; an output terminal; a third transistor coupled between the positive power supply terminal and the output terminal a fourth transistor coupled between the output terminal and the ground terminal, wherein the second source-drain region of the first transistor is coupled to a gate of the third transistor, wherein the second source-drain region of the second transistor is coupled to a gate of the fourth transistor; a first capacitor coupled between the input terminal and the gate of the third transistor; and a second capacitor coupled between the input terminal and the gate of the fourth transistor.