Patent ID: 8564050

Claim:
A three dimensional (3D) semiconductor device comprising: memory cells arranged in a plurality of layers vertically stacked on a substrate, wherein the memory cells are series connected by a vertical channel extending from a lower end proximate the substrate and coupled to a lower non-memory cell to an upper end coupled to an upper non-memory cell, wherein the plurality of layers collectively forms a stair-stepped structure and each one of the plurality of layers comprises a successively exposed end portion serving as a pad, and at least one of the upper non-memory cell and the lower non-memory cell comprises a plurality of vertically stacked non-memory cells arranged in vertically stacked layers connected by a conductive interconnect extending from an upper portion of a first one of the vertically stacked layers to a lower portion of a second one of the vertically stacked layers such that the vertically stacked non-memory cells are connected as one conductive piece.