Patent ID: 8599617

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to execute a pre-program operation, an erase operation and a soft program operation, the control circuit being configured to execute the pre-program operation before an erase operation, and execute the soft-program operation after the erase operation, the control circuit being configured to, when a characteristic of the nonvolatile memory cells is determined as being in a first state, execute the soft program operation by applying a first voltage to at least one of first word lines of the word lines except a second word line connected to a nonvolatile memory cell at one of the ends of the NAND cell unit, and applying a second voltage higher than the first voltage to the second word line, and the control circuit being configured to, when the characteristic of the nonvolatile memory cells is determined as being in a second state, execute the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line, wherein the control circuit determines whether the characteristic of the nonvolatile memory cells is in the first state or the second state based on number of times a pulse has been applied in the erasing operation.