Patent ID: 8693270

Claim:
A semiconductor apparatus comprising: a memory block configured to have a normal cell array and a redundancy cell array; a column address buffer configured to compare a plurality of input column addresses with a fail column address signal pre-stored in a fuse array, and thus to generate a column enable signal or a fail column enable signal; a column decoder configured to decode the column enable signal, and thus to generate and output a column selection signal to the normal cell array; and a column redundancy controller configured to generate a redundancy control signal in response to the fail column enable signal, to allow one redundancy bit line to be substituted according to the redundancy control signal when two or more bit fails occur in one normal array, wherein the column redundancy controller comprises: a fuse set group configured to comprise a fuse set corresponding to the memory cell array, and to generate a redundancy signal having information on a redundancy bit line to be substituted according to the fail column address; and a redundancy signal controller configured to generate the redundancy enable signal, which activates the redundancy bit line to be substituted, in response to the redundancy signal received from the fuse set group, and to provide the generated redundancy enable signal to the redundancy cell array wherein the fuse set group comprises: one enable fuse configured to generate a fuse enable signal; and a plurality of address comparison fuses coupled to the fail column address in one-to-one correspondence, and configured to generate the redundancy signal in response to the fuse enable signal of the one enable fuse, and wherein the one enable fuse comprises: a first input unit configured to be activated in response to a pre-charge signal; a first fuse blowing check unit configured to receive a memory block enable signal which activates the normal cell array as a gate signal; and a first latch unit configured to generate a fuse enable signal according to whether the first input unit and the first fuse blowing check unit are activated, and to latch and output the generated fuse enable signal.