Patent ID: 7666729

Claim:
A method for forming a silicide on a gate of a transistor, comprising: providing a semiconductor substrate; forming a gate dielectric layer over said semiconductor substrate; forming a gate electrode layer over said gate dielectric layer; performing an Ar + ion implant within a top portion of said gate electrode layer and leaving a bottom portion of said gate electrode free of Ar + ions from said Ar + ion implant; etching said gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric; forming extension sidewalls coupled to said gate stack; implanting extension regions within a top surface of said semiconductor substrate; forming source/drain sidewalls coupled to said extension sidewalls; implanting source/drain regions within a top surface of said semiconductor substrate; annealing said semiconductor substrate to recrystallize a surface region of said gate electrode modified by said Ar + ion implant; forming an interface layer over said semiconductor substrate, said interface layer including Ni; and performing a rapid thermal anneal to create a nickel silicide within said surface region of said gate electrode.