Patent ID: 8242007

Claim:
A method of fabricating a semiconductor device using a doped polysilicon process, the method comprising: forming a first insulating layer on a portion of an active region of a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer and the first insulating layer; implanting high concentration impurities of a second conductivity type into a first portion of the conductive layer over the first insulating layer and second portions of the conductive layer, which are disposed in both sides of the first insulating layer, and implanting high concentration impurities of the first conductivity type into a third portion of the conductive layer, which is spaced from one of the second portions; forming a gate structure, which comprises the first insulating layer and a gate including the first portion disposed on the first insulating layer, by patterning the conductive layer, and forming first conductive layer patterns that are spaced from the gate structure and including the second portions in both sides of the gate structure, and a second conductive layer pattern including the third portion, which is spaced from one of the first conductive layer patterns, on the epitaxial layer; forming a second insulating layer on the epitaxial layer including the gate structure and the first and second conductive layer patterns, forming high concentration first impurity regions of the second conductivity type spaced from the gate structure on the epitaxial layer, below the first conductive layer patterns, and forming a high concentration second impurity region of the first conductivity type on the epitaxial layer, below the second conductive layer pattern; and forming low concentration third impurity regions of the second conductivity type by implanting low-concentration impurities of the second conductivity type into the epitaxial layer between the gate structure and the highly concentrated first impurity regions.