Patent ID: 8618580

Claim:
An integrated circuit chip comprising: a semiconductor substrate; a first analog circuit in said semiconductor substrate, wherein said first analog circuit comprises a first NMOS transistor, wherein a ratio of a physical channel width of said first NMOS transistor to a physical channel length of said first NMOS transistor ranges from 0.1 to 10; a second analog circuit in said semiconductor substrate, wherein said second analog circuit comprises a second NMOS transistor, wherein a ratio of a physical channel width of said second NMOS transistor to a physical channel length of said second NMOS transistor ranges from 0.1 to 10; a dielectric structure coupled to said semiconductor substrate; a first interconnecting structure coupled to said semiconductor substrate and in said dielectric structure, wherein said first interconnecting structure is coupled to a first node of said first analog circuit; a first pad coupled to semiconductor said semiconductor substrate, wherein said first pad is to said first node of said first analog circuit through said first interconnecting structure; a second interconnecting structure coupled to said semiconductor substrate and in said dielectric structure, wherein said second interconnecting structure is coupled to a first node of said second analog circuit; a second pad coupled to said semiconductor substrate, wherein said second pad is coupled to said first node of said second analog circuit through said second interconnecting structure; a passivation layer coupled to said dielectric structure, wherein a first opening in said passivation layer exposes said first pad, and a second opening in said passivation layer exposes said second pad; a third interconnecting structure coupled to said passivation layer and said first and second pads, wherein said third interconnecting structure comprises a first patterned circuit layer and a second patterned circuit layer coupled to said first patterned circuit layer, wherein said first patterned circuit layer comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer, and an electroplated conductive layer on said seed layer, wherein said electroplated conductive layer has a thickness between 2 and 30 micrometers, and wherein said first node of said first analog circuit is coupled to said first node of said second analog circuit through, in sequence, said first interconnecting structure, said first pad, said third interconnecting structure, said second pad and said second interconnecting structure to provide an analog path; and a polymer layer between said first and second patterned circuit layer.