Patent ID: 8435900

Claim:
A method for manufacturing a transistor, comprising: providing a substrate having a plurality of transistors formed thereon, wherein each transistor comprises a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers the gates on the substrate, wherein after the patterning process, a height of a top surface of the residual sacrificial layer is approximately equal to a height of a top surface of the stressed layer located on the gates, and a height of a bottom surface of the residual sacrificial layer is approximately equal to a height a top surface of the gate; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the first oxide layer and the residual second oxide layer; and performing a third planarization process to remove the stressed layer located on the gates of the transistors and the residual sacrificial layer.