Patent ID: 8824229

Claim:
A semiconductor memory apparatus comprising: a bit line coupled to a plurality of memory cells; a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated; and a bit line discharge block coupled to the bit line and configured to discharge the bit line when the bit line discharge signal is enabled, wherein the discharge controller enables the bit line discharge signal in response to a bit line discharge enable signal when an active mode signal is enabled, and enables the bit line discharge signal in response to a first signal when the active mode signal is disabled, wherein the discharge controller comprises: a first logic circuit unit configured to receive an active mode signal and a bit line discharge enable signal, and output a low level signal when each of the active mode signal and the bit line discharge enable signal is at a high level; a second logic circuit unit configured to receive an active mode bar signal and a first signal, and output a low level signal when each of the active mode bar signal and the first signal is at a high level; and a third logic circuit unit configured to receive output signals of the first and second logic circuit units.