Patent ID: 7569877

Claim:
A system for selecting one wire from a plurality of wires, the system comprising: a plurality of semiconductor wires, two adjacent semiconductor wires of the plurality of semiconductor wires being associated with a separation smaller than or equal to 100 nm; a plurality of address lines, each of the plurality of address lines including a gate region and an inactive region and intersecting the plurality of semiconductor wires at a plurality of intersections; wherein the plurality of intersections includes a first intersection and second intersection, the first intersection associated with the gate region, the second intersection associated with the inactive region; wherein at the first intersection the each of the plurality of address lines is separated from a first semiconductor wire by a first dielectric layer, and at the second intersection the each of the plurality of address lines is separated from a second semiconductor wire by a second dielectric layer; wherein the each of the plurality of address lines is free from any gate region associated with a dimension smaller than the separation, the dimension being related to a first direction of the each of the plurality of address lines.