Patent ID: 7999303

Claim:
A NAND-type nonvolatile semiconductor memory device comprising, a semiconductor substrate, a plurality of memory cell transistors connected to each other in series formed on the semiconductor substrate, and a select transistor provided at each end of the plurality of memory cell transistors formed on the semiconductor substrate, wherein the memory cell transistor comprises: a first insulating film on the semiconductor substrate; a charge trapping layer on the first insulating film; a second insulating film made of aluminum oxide on the charge trapping layer; a first control gate electrode on the second insulating film; and a first source/drain region formed in the semiconductor substrate on both sides of the first control gate electrode, and the select transistor comprises: a third insulating film on the semiconductor substrate; a fourth insulating film on the third insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen); a second control gate electrode on the fourth insulating film; and a second source/drain region formed in the semiconductor substrate on both sides of the second control gate electrode.