Patent ID: 7889591

Claim:
An ASIC including embedded non-FLASH re-writable non-volatile memory, comprising: a silicon substrate including active circuitry fabricated in a logic plane of the silicon substrate, the active circuitry including a processor, and control logic block circuitry in electrical communication with the processor and configured specifically to emulate one or more memory types and to perform data operations on the one or more memory types; and a first memory plane fabricated directly in contact with the silicon substrate and vertically disposed directly over the active circuitry in the logic plane, the first memory plane including at least one two-terminal cross-point memory array embedded in the first memory plane and including a plurality of first conductive array lines and a plurality of second conductive array lines that are electrically coupled with the control logic block circuitry, and a plurality of re-writable non-volatile two-terminal memory elements, each re-writable non-volatile two-terminal memory element is positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and includes a first terminal electrically coupled with its respective first conductive array line and a second terminal electrically coupled with its respective second conductive array line, and wherein at least a portion of the control logic block circuitry is specifically configured to emulate a FLASH memory type in the at least one two-terminal cross-point memory array, non-volatile data stored in the plurality of re-writable non-volatile two-terminal memory elements comprises system boot data for use by the processor during system boot, and the system boot data is retained the absence of electrical power.