Patent ID: 7356673

Claim:
A computer-implemented method for processing a first instruction set and a second instruction set in a processor comprising the steps of: providing a program of instructions comprising a plurality of instructions of the first instruction set and a plurality of instructions of the second instruction set, wherein the plurality of instructions of the first instruction set are decoded by a decoder in an execution pipeline and the plurality of instructions of the second instruction set are predecoded by a compiler, wherein the second instruction set is a logical subset of the first instruction set, and wherein the instructions of the second instruction set are control signals generated by the compiler and are not decoded during a runtime of the program; storing the plurality of instructions of the second set in a plurality of buffers proximate to a plurality of execution units; executing at least one instruction of the first instruction set in response to a first counter; and executing at least one instruction of the second instruction set in response to at least a second counter, wherein the second counter is invoked by a branch instruction of the first instruction set, wherein the step of executing at least one instruction of the second instruction set further comprises the steps of de-gating a plurality of execution queues storing the plurality of instructions of the first instruction set, and pausing a fetching of the first instruction set from a memory.