Patent ID: 7426603

Claim:
An apparatus comprising: a memory bus configured to transmit N memory transaction items at a time; a queue configured to store more than N memory transaction items; a memory circuit coupled to the memory bus, wherein the memory circuit comprises more than N memory banks, and wherein each memory transaction item is addressed to a memory bank; a multiplexer comprising at least N multiplexer inputs and a multiplexer output, wherein each multiplexer input is coupled to one of the memory transaction items, and wherein the multiplexer output is coupled to the memory bus; a state machine coupled to the multiplexer output, wherein the state machine is configured to generate a bank readiness signal that identifies the readiness of a memory bank to accept a memory transaction item that is addressed to the memory bank; and an arbiter controller coupled to the state machine and a selection input of the multiplexer, wherein the arbiter controller is configured to activate the selection input of the multiplexer to select a memory transaction item to transmit from the queue to the addressed memory bank that is identified by the bank readiness signal.