Patent ID: 6879650

Claim:
A circuit for detecting clocking errors in the synchronization of a DTE (data terminal equipment) data signal with a DCE (data communication equipment) clocking signal in a communication environment wherein the DCE interfaces the DTE to a communication channel at an interface rate determined by the DCE clocking signal, the circuit comprising: a clock generating circuit configured to generate a master clock signal, a DCE clocking signal, and an internal clocking signal, each of the DCE clocking signal and internal clocking signal having a first frequency that is a fraction of the frequency of the master clock signal; a sample enable generator configured to receive the master clock signal and the internal clocking signal and to generate a first sample enable signal at a first time and a second sample enable signal at a second time, the second time being subsequent to the first time; and a sample comparator having inputs that receive said first sample enable signal, said second enable signal and said DTE data signal, the sample comparator configured to sample the DTE data signal at the first time and sample the DTE data signal at the second time, the sample comparator further configured to compare the DTE data signal sampled at the first time with the DTE data signal sampled at the second time and determine, from the comparison, whether the DTE data signal has undergone a transition during the time interval between said first time and said second time.