Patent ID: 7442651

Claim:
A plasma etching method in manufacturing a MOS transistor, a workpiece being placed on a lower electrode located in a vacuum processing vessel, said workpiece having a lamination of (a) a layer for a gate electrode for said MOS transistor, said layer containing therein a transition metal element, and (b) an underlying dielectric material layer made of a high dielectric constant insulator, to form a metal gate structure for said MOS transistor, comprising: while introducing a processing gas into said vacuum processing vessel and supplying high-frequency electrical power to inside of said vacuum processing vessel, performing plasma conversion of the processing gas introduced to thereby etch a surface of said workpiece, said processing gas including hydrogen chloride; performing a main etching process to etch a part of the layer for the gate electrode for said MOS transistor on said underlying dielectric material layer, with applying a first power of RF bias to said lower electrode; and performing an overetching process to etch the layer for the gate electrode for exposing said underlying dielectric material layer, with applying a second power of RF bias to said lower electrode, wherein said second power is equal to or less than said first power, in milliwatts per square centimeter, so as to enhance the selectivity of etching the layer for the gate electrode relative to etching the underlying dielectric material layer.