Patent ID: 8525561

Claim:
A phase lock loop (PLL) comprising a PLL feedback circuit including a feedback divider receiving a PLL output signal and outputting a PLL feedback signal to said PLL feedback circuit, said feedback divider comprising: a first dynamic latch receiving said PLL output signal as a PLL clock signal, a first feedback signal, and a seed signal, said first dynamic latch outputting a first data signal; a first logic circuit operatively connected to said first dynamic latch, said first logic circuit receiving said first data signal and a second feedback signal, and outputting a first logic signal; a second dynamic latch operatively connected to said first logic circuit, said second dynamic latch receiving one of said seed signal and said first logic signal from said first logic circuit and outputting a second data signal; a plurality of serially connected dynamic latches operatively connected to said second dynamic latch, each of said serially connected dynamic latches receiving and forwarding additional data signals to subsequent ones of said serially connected dynamic latches in series, a second-to-last dynamic latch outputting a fourth data signal to a last dynamic latch, said last dynamic latch receiving said fourth data signal and outputting a fifth data signal, a first feedback loop receiving said fourth data signal from said second-to-last dynamic latch and said fifth data signal from said last dynamic latch, said first feedback loop comprising a NAND circuit that combines said fourth and fifth data signals, and said first feedback loop outputting said first feedback signal; and a second feedback loop receiving said fourth data signal from said second-to-last dynamic latch and said fifth data signal from said last dynamic latch, said second feedback loop comprising a NOR circuit that combines said fourth and fifth data signals, and a generic latch, and said second feedback loop outputting said second feedback signal.