Patent ID: 7413929

Claim:
A method for fabricating a chip package, comprising: joining a first side of a die and a substrate using an adhesive material; after said joining said first side of said die and said substrate, forming a first polymer layer over a second side of said die, over said substrate and across an edge of said die, wherein said first and second sides are opposite to each other; after said forming said first polymer layer, forming a circuit layer on said first polymer layer, over said second side of said die, over said substrate and across said edge of said die, wherein said forming said circuit layer comprises a copper electroplating process, and wherein said circuit layer comprises a portion as a part of an inductor; after said forming said circuit layer, forming a second polymer layer on said circuit layer, on said first polymer layer, over said second side of said die, over said substrate and across said edge of said die; after said forming said second polymer layer, forming a metal bump over said substrate, wherein said metal bump is connected to said die through said circuit layer; and after said forming said metal bump, cutting said substrate.