Patent ID: 7502270

Claim:
A semiconductor memory device comprising: a first memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the first memory cell; a first bit line connected to the first memory cell to transmit the data stored in the first memory cell; a second bit line transmitting reference data used to detect the data stored in the first memory cell; a first sense node and a second sense node transmitting the data stored in the first memory cell and the reference data, respectively; a first short-circuiting switch provided between the first sense node and the second sense node; and a first flip-flop detecting a potential difference generated between the first sense node and the second sense node in a data read operation, wherein in the data read operation, the first short-circuiting switch is in a turn-on state at a time when the first flip-flop is actuated to start detecting the potential difference, and the first short-circuiting switch is turned off while the first flip-flop is in an active state.