Patent ID: 8045387

Claim:
A memory device, comprising: a memory cell array comprising a plurality of memory cells arranged in relation to a plurality of word lines including a selected word line and a plurality of non-selected word lines, and a plurality of bit lines; a high voltage generator configured to generate a program voltage applied to the selected word line, a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and a local voltage applied to at least one of the non-selected word lines in a local self-boosting scheme; and control logic configured to control the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and further configured to control the generation of the pass voltage, such that the pass voltage is incrementally increased in response to the program voltage, and still further configured to control the generation of the local voltage to decrease the local voltage in response to the increasing program voltage.