Patent ID: 7177364

Claim:
A decoder for decoding at least one quadrature amplitude modulated (QAM) signal into at least one n-bit digital signal, said decoder comprising: at least one integrator configured for integrating the at least one QAM signal; and at least one tapped-delay line filter comprising at least one delay element, wherein said at least one tapped-delay line filter is configured for receiving the integrated at least one QAM signal and thereafter outputting a representation of each bit of the at least one n-bit digital signal, wherein the at least one QAM signal is capable of being transmitted at a rate of t, wherein the at least one QAM signal includes at least one in-phase portion modulated by at least one carrier signal at a carrier frequency of f c , wherein at least one integrator is configured for integrating the in-phase portion of the at least one QAM signal, wherein at least one tapped-delay line filter is configured for receiving the integrated in-phase portion of the at least one QAM signal and thereafter outputting a representation of at least one bit of the at least one n-bit digital signal, and wherein the number of delay elements of the at least one tapped-delay line filter is based on the number of bits n, the transmission rate t and the carrier frequency f c .