Patent ID: 8618538

Claim:
A thin film transistor array panel, comprising: a gate electrode disposed on a substrate; a gate insulating layer disposed on the gate electrode; an oxide semiconductor disposed on the gate insulating layer; a blocking layer disposed on the oxide semiconductor; a source electrode and a drain electrode disposed on the blocking layer; a passivation layer disposed on the source electrode and drain electrode; and a pixel electrode disposed on the passivation layer, wherein, the blocking layer comprises a first portion that is covered by the source electrode and the drain electrode, and a second portion that is disposed on a channel region of the oxide semiconductor, the first portion of the blocking layer pattern comprises a silicide or amorphous silicon, the second portion of the blocking layer pattern comprises silicon oxide (SiO x ), and the silicon oxide (SiO x ) content of the second portion is greater than the silicon oxide (SiO x ) content of the first portion.