Patent ID: 7285856

Claim:
A package for a semiconductor device comprising: a laminate of many layers, as a whole-layer build-up substrate, including a plurality of conducting layers and a plurality of insulating resin layers that are alternately laminated one upon other; a semiconductor element mounting portion formed on one surface of the laminate to connect to a semiconductor element; one of the insulating resin layers defining the one surface of the laminate on which said semiconductor element mounting portion is formed being constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer impregnated with an insulating resin; the other insulating resin layers being constituted by only insulating resin; an external connecting portion formed on an opposite surface of the laminate; and a thermal expansion coefficient of the semiconductor element mounting portion being closer to that of the semiconductor element than to that of the insulating resin layers.