Patent ID: 8035486

Claim:
A power-on reset circuit, comprising: a first transistor having a source coupled to receive a supply voltage fluctuating within a predetermined range and a drain coupled to a first node to provide a current dependent on the supply voltage; a first circuit having an input node coupled to receive the supply voltage and an output node for providing a first current that remains substantially constant across the predetermined range of the supply voltage; a second circuit having a second transistor and a third transistor, a source of the second transistor connected to the first node and a drain of the second transistor connected to a second node, a gate of the third transistor coupled to the second node to generate a second current through a source of the third transistor wherein the second current increases or decreases according to fluctuation of the supply voltage within the predetermined range; and an output circuit generating a power-on reset signal based on the first current and the second current.