Patent ID: 7288951

Claim:
A burn-in system for testing integrated circuits comprising: a testing stage configured to stress test an integrated circuit; a first power stage comprising: a first pulse width modulator controller having a first error input, the first pulse width modulator controller configured to produce a first control signal in response to a signal received at the first error input; and a first pulse width modulator configured to produce a first power output in response to the first control signal; a second power stage comprising: a second pulse width modulator controller having a second error input, wherein the second pulse width modulator controller is configured to produce a second control signal in response to a signal received at the second error input; and a second pulse width modulator configured to produce a second power output in response to the second control signal; a first single mode power control circuit comprising: a current control circuit configured to generate a first single mode current error signal based on a first measured load current, which is indicative of the current supplied by the first power output; and a voltage control circuit coupled to the first single mode current error signal and configured to generate a first single mode voltage error signal; a first dual mode power control circuit comprising: a current control circuit configured to generate a first dual mode current error signal based on at least one of the first measured load current and a second measured load current, which is indicative of the current supplied by the second power output; and a voltage control circuit coupled to the first dual mode current error signal and configured to generate a first dual mode voltage error signal; wherein: the burn-in system comprises a single power mode, in which the first single mode voltage error signal is coupled to the first error input and the first power output is coupled to the testing stage; and the burn-in system comprises a dual power mode, in which the first dual mode voltage error signal is coupled to the first and second error inputs, and the first and second power outputs are coupled to the testing stage.