Patent ID: 7656206

Claim:
A phase-locked loop circuit comprising: input clock frequency detecting means for detecting whether a frequency of an input clock has become equal to or lower than a predetermined frequency and for outputting a PLL control signal based on a result of the frequency detection; a PLL unit that includes phase frequency comparing means for detecting a phase difference between a phase of the input clock and an output signal from a voltage controlled oscillator, error signal generating means for generating an error signal in accordance with the detected phase difference, and the voltage controlled oscillator that outputs, based on the error signal, an oscillation signal having a predetermined frequency; and oscillator input voltage fixing means for fixing, in a case where the frequency of the input clock has become equal to or lower than the predetermined frequency, an input voltage of the voltage controlled oscillator so as to be a predetermined high voltage that is specified in advance, based on the PLL control signal, wherein: the input clock frequency detecting means includes a logical operation circuit that performs a logical operation on an external control signal and the result of the frequency detection, the external control signal being input from outside in order to control an operation of the PLL unit; the PLL control signal is an output signal from the logical operation circuit; in the case where the frequency of the input clock has become equal to or lower than the predetermined frequency or in a case where the external control signal is a control signal for causing the PLL unit to stop, the oscillator input voltage fixing means fixes the input voltage of the voltage controlled oscillator so as to be the predetermined high voltage that is specified in advance; the input clock frequency detecting means includes power supply voltage detecting means for detecting whether a power supply voltage has exceeded a reference voltage that is higher than a PLL-ON voltage which is a voltage with which the PLL unit is able to oscillate properly even if starting from a low voltage state; the logical operation circuit performs the logical operation based on the external control signal, the result of the frequency detection, and a result of the power supply voltage detection; and the oscillator input voltage fixing means fixes, based on the PLL control signal, the input voltage of the voltage controlled oscillator so as to be the predetermined high voltage that is specified in advance, until the power supply voltage exceeds the reference voltage that is higher than the PLL-ON voltage which is the voltage with which the PLL unit is able to oscillate properly even if starting from the low voltage state.