Patent ID: 8650527

Claim:
A method comprising: receiving results of simulating one or more circuit designs used in an integrated circuit (IC), the results generated by a circuit simulator executed on a computer system, the circuit simulator operating on one or more files stored on the computer system and representing the one or more circuit designs, and the circuit simulator further operating on input stimulus provided to the circuit simulator to apply to the one or more circuit designs as represented in the one or more files; using the simulation results to compute a respective individual failure rate for one or more circuit devices used in the one or more circuit designs, wherein the individual failure rate for a given circuit device indicates an expected failure rate for a single instance of the given circuit device in a single instance of the respective circuit design in which the given circuit device is used; for each respective circuit device of the one or more circuit devices, computing a scaled failure rate for the respective circuit device based on the individual failure rate for the respective circuit device and a number of instances of the circuit design in which the respective circuit device is used; and predicting a failure rate of the IC based on the scaled failure rates of the one or more circuit devices.