Patent ID: 7053450

Claim:
A semiconductor device comprising: a substrate; a semiconductor layer of a first conductivity type provided on the substrate; a gate insulating film provided on the semiconductor layer; a gate electrode provided on the gate insulating film; sidewalls composed of an insulator provided on each of side surfaces of the gate electrode; lightly doped source/drain diffusion layers each of a second conductivity type formed in respective regions of the semiconductor layer located laterally below the gate electrode; heavily doped source/drain diffusion layers formed in respective regions of the semiconductor layer located laterally below the sidewalls and each containing an impurity of the second conductivity type at a concentration higher than in each of the lightly doped source/drain diffusion layers; a source-side pocket diffusion layer of the first conductivity type formed in the semiconductor layer to cover at least a part of a side surface of the lightly doped source diffusion layer and a bottom surface thereof; a drain-side pocket diffusion layer of the first conductivity type formed in the semiconductor layer to cover at least a part of a side surface of the lightly doped drain diffusion layer and a bottom surface thereof; a source-side threshold control layer formed in a region of the semiconductor layer located above the source-side pocket diffusion layer and containing an impurity of the first conductivity at a concentration different from a concentration in the source-side pocket diffusion 1 ayer; and a drain-side threshold control layer formed in a region of the semiconductor layer located above the drain-side pocket diffusion layer and containing an impurity of the first conductivity at a concentration different from a concentration in the drain-side pocket diffusion layer, wherein the source-side pocket diffusion layer and the drain-side pocket diffusion layer are in contact or overlapping relation with each other below a central portion of the gate electrode in a gate length direction, a depth of each of the source-side pocket diffusion layer and the drain-side pocket diffusion layer in the semiconductor layer becomes smaller from below an edge of the gate electrode toward below the center portion of the gate electrode, and the source-side threshold control layer and the drain-side threshold control layer are in contact or overlapping relation with each other below the central portion of the gate electrode in the gate length direction.