Patent ID: 7890732

Claim:
A memory system comprising: a nonvolatile semiconductor memory which includes a plurality of blocks each having a plurality of pages, in which data is erasable in units of blocks, an erase block size of the nonvolatile semiconductor memory being larger than an erase block size of a memory assumed by a host device; eight input/output terminals to input/output a command, an address, and data from/to an outside of the memory system; and a ready/busy terminal to inform the outside of the memory system of an internal state of the memory system, the memory system being configured to perform processing of: in one write operation, capturing a first command, an address, and data, with 8-bit width via the eight input/output terminals, managing a first table for converting a first physical address of the memory assumed by the host device into a first logical address of the memory assumed by the host device, and a second table for converting the first logical address into a second physical address of the nonvolatile semiconductor memory, the first table and the second table being provided in a RAM, converting the first physical address into the second physical address using the first table and the second table when accessing the nonvolatile semiconductor memory, and writing the data to the nonvolatile semiconductor memory while assuring that a plurality of data items, which are captured via the eight input/output terminals by a plurality of write operations, are stored in one page, and the memory system being further configured to perform processing of: upon receiving an erase command from the host device, notifying the host device that data corresponding to the erase command has been erased, while not actually erasing the data corresponding to the erase command.