Patent ID: 7781289

Claim:
A method comprising: performing multiple implantations in a first portion of a substrate and in a second portion of the substrate, the first and second portions associated with a memory cell being fabricated; and forming an oxide over the first and second portions of the substrate and over a third portion of the substrate, the oxide thicker over the first and second portions of the substrate than over the third portion of the substrate; wherein performing the multiple implantations comprises performing a deep N-well (DNW) implantation, a high-energy N-well (HiNWell) implantation, a high-energy P-well (HiPWell) implantation, and a P-well implantation; and wherein the HiNWell implantation is also used to form a high-energy N-well for a high-energy PMOS (HiPMOS) transistor in the third portion of the substrate, the HiPWell implantation is also used to form a high-energy P-well for a high-energy NMOS (HiNMOS) transistor in the third portion of the substrate, and the P-well implantation is also used to form a P-well for an NMOS transistor in the third portion of the substrate.