Patent ID: 7916720

Claim:
A slave network interface circuit for improving the parallelism of an On-Chip network, comprising: a MUX for selecting a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module of a plurality of slave modules, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputting the selected address to the anyone slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network; wherein the slave network interface circuit transmits and receives data through a slave module interface signal, which is defined at an On-Chip network, between the slave modules, and transmits and receives the data through a forward path signal, which is transmitted from a slave network interface to the on-Chip network, and a backward paths signal, which is transmitted from the On-Chip network to the slave network interface, between the On-Chip network; the forward path signal includes a FHOLDMS signal, a FBST signal, a FAEN signal, a FA signal, a FDEN signal, and a FDATA signal; and the FHOLDMS signal is a signal for stopping transmission of data received through a forward path, the FBST signal is a signal for operating as a burst mode, the FAEN signal is a signal informing that the FA signal is valid, the FA signal denotes an address to store data, the FDEN signal denotes that the FDATA signal is valid, and the FDATA signal denotes data to be transmitted and stored from the slave network interface to the On-Chip network.