Patent ID: 7094683

Claim:
A method for forming a dual damascene opening to protect a low-K dielectric insulating layer from an ashing process comprising the steps of: providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer; depositing a first dielectric layer stack comprising at least one dielectric layer over the at least one dielectric insulating layer to seal the upper portion of the via opening; blanket depositing a second dielectric layer stack comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack; the first and second dielectric layer stacks are formed according to a first and second CVD process respectively, the first CVD process comprises a CVD deposition process comprising at least one of a lower temperature and a higher pressure compared to the second CVD process, photolithographically patterning an overlying photoresist layer and reactive ion etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed; removing the photoresist layer according to an ashing process with the via opening sealed; and reactive ion etching through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.