Patent ID: 7605081

Claim:
A method of forming patterned features in a device structure, comprising: forming a lithographically patterned mask layer on an upper surface of an interlevel dielectric material that is located atop a semiconductor device including a source region and a drain region located within a semiconductor substrate, wherein said lithographically patterned mask layer comprises one or more mask openings of a diameter d and is formed by lithography and etching, said etching does not remove any portion of the interlevel dielectric material; applying a layer of a block copolymer over the lithographically patterned mask layer, wherein said block copolymer comprises at least first and second polymeric block components A and B, respectively, that are immiscible with each other, said block copolymer comprising polystyrene-block-polymethylmethacrylate (PS-b-PMMA) having a PS:PMMA weight ratio ranging from about 80:20 to about 60:40; annealing the block copolymer layer by thermal annealing or UV treatment to form a single unit polymer block comprising a single cylinder that stands perpendicular to the upper surface of the device structure and having a diameter w inside each single one of said mask openings, wherein w<d, and each single unit polymer block cylinder is self-aligned to each single mask opening in the lithographically patterned mask layer and comprises the second polymeric block component B and is embedded in a polymeric matrix that comprises the first polymeric block component A; selectively removing the second polymeric block component B relative to the first polymeric block component A to form a single opening of the diameter w in the polymeric matrix inside each of said mask openings; and patterning the interlevel dielectric material exposing one of the source region and the drain region using the single openings of diameter w.