Patent ID: 7906838

Claim:
An electronic component package substructure used for manufacturing a plurality of electronic component packages, each of the electronic component packages comprising: a base having a top surface and a side surface; and a plurality of layer portions stacked on the top surface of the base wherein: the base includes a plurality of external connecting terminals and a retainer for retaining the plurality of external connecting terminals; each of the external connecting terminals has an end face located at the side surface of the base; each of the electronic component packages has a top surface and a bottom surface that are opposite to each other, the bottom surface corresponding to a bottom surface of the base; and, of terminals or electrodes that are electrically connected to any of the plurality of external connecting terminals, none are exposed in either the top surface or the bottom surface of each of the electronic component packages, the electronic component package substructure comprising: a wafer that incorporates a plurality of sets of the external connecting terminals corresponding to the plurality of electronic component packages and a wafer main body for retaining the plurality of sets of the external connecting terminals, the wafer including a plurality of pre-base portions configured to be separated from one another later so that each of them will thereby become the base; and a plurality of sets of the layer portions of the plurality of layer portions the disposed on the wafer such that the layer portions of each set of the plurality of sets of the layer portions are stacked on a corresponding one of the plurality of pre-base portions of the wafer, wherein: each of the plurality of layer portions includes at least one electronic component chip; at least one of a plurality of electronic component chips that the plurality of layer portions include is electrically connected to at least one of the external connecting terminals; and the wafer has a bottom surface corresponding to the bottom surface of the base, and none of the plurality of sets of the external connecting terminals are exposed in the bottom surface of the wafer.