Patent ID: 8824226

Claim:
A method comprising: determining a plurality of critical charges; determining a plurality of capacitances corresponding to the plurality of critical charges; determining a target critical charge based on a soft error rate of a memory element; based on the target critical charge, the plurality of critical charges, and the plurality of capacitances, determining a target capacitance; and based on the target capacitance, forming a capacitor having: a first plurality of conductive bars in at least one conductive layer of a semiconductor structure, the first plurality of conductive bars being arranged in parallel with a base layer of the semiconductor structure; and a second plurality of conductive bars in at least one other conductive layer of the semiconductor structure, the second plurality of conductive bars being arranged in parallel with the base layer of the semiconductor structure, wherein the first plurality of conductive bars runs in a first direction, the second plurality of conductive bars runs in a second direction, the second direction is perpendicular to the first direction; and each of the first plurality of conductive bars being arranged to be directly over or directly under corresponding portions of at least one of the second plurality of conductive bars.