Patent ID: 6980461

Claim:
A semiconductor dynamic random access memory device comprising: a plurality of bit lines, including a first bit line; a plurality of memory cells, including a first memory cell coupled to the first bit line, each memory cell includes: at least one transistor including a source region, a drain region, a body region disposed between the source and drain regions, and a gate spaced apart from and capacitively coupled to the body region, wherein the body region is electrically floating; and a first data state and a second data state, wherein the memory cell is in (1) the first data state when the transistor includes a first charge in the body region, and (2) the second data state when the transistor includes a second charge in the body region; a sense amplifier, having first and second inputs, wherein the first input is coupled to the first bit line; and a digitally controlled reference current generator, coupled to the second input of the sense amplifier, to generate a reference current in response to a reference current control word, wherein the sense amplifier uses the reference current to sense the data state of the first memory cell.