Patent ID: 7615822

Claim:
A transistor comprising: a drain including: a first impurity region of a first conductivity type having a first volume and a first surface area on a surface of the transistor, a second impurity region of the first conductivity type with a lower concentration of impurities than the first impurity region, the second impurity region having a second volume and a second surface area on the surface of the transistor, wherein the second volume surrounds and abuts the first volume and extends below the first volume, and the second surface area is adjacent to the first surface area, a third impurity region of the first conductivity type with a lower concentration of impurities than the second impurity region, the third impurity region having a third volume and a third surface area on the surface of the transistor, wherein the third volume surrounds and abuts the second volume, and has a lower boundary that is vertically aligned with a lower boundary of the second volume, and wherein the third surface area is adjacent to the second surface area, and a fourth impurity region of the first conductivity type with a lower concentration of impurities than the second impurity region, the fourth impurity region having a fourth volume, wherein the fourth volume extends below the second volume and has an upper boundary that abuts the lower boundary of the second volume and an outer boundary that is laterally aligned with an outer boundary of the second volume; a source including a fifth impurity region with a fifth volume and a fifth surface area on the surface of the transistor; and a gate to control a depletion region between the source and the drain, wherein the fourth impurity region has a lower concentration of impurities than the third impurity region.