Patent ID: 7084698

Claim:
A band-gap reference circuit that generates a band-gap reference voltage, the band-gap reference circuit comprising: a first inversely proportional to absolute temperature (IPTAT) current generator that generates a first current; a second IPTAT current generator, connected in parallel with the first IPTAT current generator, that generates a second current; a third IPTAT current generator, connected in series with the first IPTAT current generator, that generates a third current; and a resistor, connected in series with the first and second IPTAT current generators and in parallel with the third IPTAT generator, wherein the band-gap reference voltage is generated across the resistor, wherein each of the first, second, and third IPTAT current generators comprises: a first PMOS transistor having a source connected to a supply voltage, a drain and a gate; a second PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the first PMOS transistor at a PBIAS node, and a drain; a third PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the second PMOS transistor at the PBIAS node, and a drain from which the current generated by the IPTAT is drawn; a third capacitor having a first terminal connected to the supply voltage, and a second terminal connected to the gate of the third PMOS transistor; a PNP transistor having an emitter connected to the drain of the first PMOS transistor, a base connected to a reference voltage, and a collector connected to the reference voltage; a comparator circuit having a first input coupled to the emitter of the PNP transistor, a second input coupled to the drain of the second PMOS transistor, and an output connected to the gates of the first and second PMOS transistors at the PBIAS node, the output providing a bias voltage to the first, second, and third PMOS transistors; a fourth capacitor having a first terminal connected to the emitter of the PNP transistor, and a second terminal connected to the reference voltage; a fifth capacitor having a first terminal connected to the drain of the second PMOS transistor, and a second terminal connected to the reference voltage; and a switched capacitor resistor having a first node connected to the drain of the second PMOS transistor, and a second node connected to the reference voltage.