Patent ID: 7411947

Claim:
An interface module for connecting a computer system element to a first external transmission path and a second external transmission path, comprising: a first signal transceiver to be connected to said first external transmission path; a second signal transceiver to be connected to said second external transmission path; an interface processing unit; and a selector for selectively connecting one of said serial signal transceivers to said interface processing unit, wherein said interface processing unit comprises: a serializer/deserializer circuit to convert serial signals received from said serial signal transceivers into parallel signals, convert parallel signals to be transmitted to said external transmission paths into serial signals and output the serial signals to one of said serial signal transceivers; an encoder/decoder connected to said serializer/deserializer circuit; and a protocol processing unit which is connected to said encoder/decoder for selectively performing at least two kinds of protocol processing, wherein said selector selects one of said serial signal transceivers to be connected to said interface processing unit based on a given instruction issued from said computer system element, wherein said interface unit switches reference clock to be supplied to said serializer/deserializer circuit from one to another based on said given instruction, wherein said computer system element is a first storage control unit, said first signal transceiver is connected to a host unit via said first external transmission path, and said second signal transceiver is connected to a second storage control unit via said second external transmission path, wherein said given instruction is issued so that said first storage control unit is connected to one of said host unit and second storage control unit in a time division manner, and wherein said protocol processing unit further comprises: a first protocol processing part for Fibre Channel; and a second protocol processing part for Gigabit Ethernet, wherein, if said given instruction specifies protocol processing for the Fibre Channel, said selector selects said first serial signal transceiver for transmitting and receiving packets according to the Fibre Channel protocol and said interface processing unit directs said protocol processing unit to select said first protocol processing part and supplies a clock with 106.25 MHz to said serializer/deserializer circuit, if said given instruction specifies protocol processing for the Gigabit Ethernet, said selector selects said second serial signal transceiver for transmitting and receiving packets according to the Gigabit Ethernet protocol and said interface processing unit directs said protocol processing unit to select said second protocol processing part and supplies a clock with 125 MHz to said serializer/deserializer circuit.