Patent ID: 8711629

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array having a plurality of nonvolatile memory cells arranged using a virtual ground, a word line for control of a gate and first and second bit lines being connected to each of the nonvolatile memory cells; a first selective transistor group for selecting the first bit line; a first selective transistor drive circuit configured to drive gates of the first selective transistor group; a second selective transistor group for selecting the second bit line; a second selective transistor drive circuit configured to drive gates of the second selective transistor group; a first voltage switch configured to select a voltage to be supplied to the first selective transistor drive circuit depending on an operation of the memory array; and a second voltage switch configured to select a voltage to be supplied to the second selective transistor drive circuit depending on the operation of the memory array, wherein a transistor constituting the first selective transistor drive circuit is different in structure from a transistor constituting the second selective transistor drive circuit.