Patent ID: 7348803

Claim:
A bus buffer including circuitry adapted to generate a logic high level on a first bi-directional signal path, one or more first stations connected to the first bi-directional signal path adapted to monitor a logic level on said first path, and to generate a logic low level on said first path; an interface device operatively coupled to the first bi-directional signal path, said interface device having a first receive input and a first transmit output; and circuitry adapted to generate a logic high level on a second bi-directional signal path; and one or more second stations connected to the second bi-directional signal path and adapted to monitor the logic level on said second path, and to generate a logic low level on said second path; the second bi-directional signal path being operatively connected to a second receive input and a second transmit output of the interface device, the interface device further including first electronic circuitry adapted to ensure that an output voltage on the second signal path follows an input voltage on the first signal path, interposing an offset voltage between said input and output voltages such that the voltage on the second signal path exceeds the voltage on the first signal path by the magnitude of said offset voltage; and second electronic circuitry adapted to ensure that an input voltage on the second signal path follows an output voltage on the first signal path, interposing an offset voltage between said input and output voltages such that the voltage on the first signal path exceeds the voltage on the second signal path by the magnitude of said offset voltage; and the first and second electronic circuitry further adapted such that when both the first and second signal paths are at an equal voltage, the interface device does not act to drive the first or the second signal path.