Patent ID: 7848131

Claim:
A memory device, comprising: a memory cell including a pass transistor and a ferroelectric capacitor based on a ferroelectric material, wherein the ferroelectric capacitor is composed of a first plate connecting to the pass transistor and a second plate connecting to a plate line; and a non-inverting local sense amp including a first inverting amplifier and a second inverting amplifier, wherein the first inverting amplifier includes an inverter having a first amplify transistor and a pull-up transistor for reading the memory cell through a local bit line when reading, a local pre-charge transistor for pre-charging the local bit line, and a write transistor for driving the local bit line when writing; and the second inverting amplifier includes a second amplify transistor for reading an amplify node connecting to an output node of the inverter, and a local enable transistor is serially connected to the second amplify transistor for enabling, where the local enable transistor is connected to a global bit line; and a global sense amp for reading an output from the non-inverting local sense amp through the global bit line, wherein the global sense amp includes a global reset transistor for resetting the global bit line, a cross coupled inverter latch for storing an output from a bit read circuit connecting to the global bit line and for sending a write data to a bit write circuit driving the global bit line, a data transfer circuit for transferring a read output from the cross coupled inverter latch to a forwarding read line through a read selector and a read buffer, and a data receive circuit for sending a write input to the cross coupled inverter latch from a forwarding write line through a receive switch; and a locking signal generator for locking the bit read circuit with a locking signal which is generated by a delay circuit receiving the read output from the cross coupled inverter latch.