Patent ID: 6906960

Claim:
A semiconductor memory device comprising: a plurality of banks with electrically rewritable memory cells arranged therein, said banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for said plurality of banks; a read-use data bus commonly disposed for said plurality of banks; a write circuit connected to said write-use data bus; a read circuit connected to said read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, said bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between said external bank address signals and said internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by said bank address decoder circuit, wherein said bank address decoder circuit comprises: a write-use bank address decoder configured to convert first external bank address signals selecting a bank to be rewritten to first internal bank address signals based on one of said plural kinds of address conversions, and decode said first internal bank address signals; and a read-use bank address decoder configured to convert second external bank address signals selecting a bank to be read to second internal bank address signals based on one of said plural kinds of address conversions, and decode said second internal bank address signals.