Patent ID: 6980026

Claim:
A programmable logic device (PLD), comprising: a programmable interconnect structure; and an array of programmable logic blocks having input terminals coupled to the programmable interconnect structure and further having output terminals coupled to the programmable interconnect structure, wherein each programmable logic block comprises: a lookup table (LUT) having a plurality of data input terminals and further having an output terminal coupled to the output terminal of the programmable logic block; a plurality of input multiplexers, each input multiplexer having a plurality of input terminals coupled to the input terminals of the programmable logic block and further having an output terminal; a plurality of input memory elements, each input memory element having a data input terminal coupled to the output terminal of an associated input multiplexer and further having a registered data output terminal; and a plurality of LUT multiplexers, each LUT multiplexer having a first input terminal coupled to the output terminal of an associated one of the input multiplexers, a second input terminal coupled to the registered data output terminal of an associated one of the input memory elements, a select terminal, and an output terminal coupled to an associated one of the data input terminals of the LUT without traversing the programmable interconnect structure.