Patent ID: 8181126

Claim:
A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing comprising: providing a design of an integrated circuit layout having a plurality of segments of critical width on a computer; creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, the first mask design meeting predetermined manufacturability design rules; creating a second mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, the second mask design meeting predetermined lithographic design rules in regions local to the critical width segments; identifying on the computer design features of the second mask design that violate the predetermined manufacturability design rules; creating on the computer a third mask design derived from the second mask design wherein the mask features of the second mask design that violate the predetermined manufacturability rules are selectively replaced by mask features from the first mask design so that the third mask design meets the predetermined manufacturability design rules.