Patent ID: 8185782

Claim:
A test device for controlling a hierarchical test architecture, comprising: a top test level, comprising: a top level data register; and a top level test controller, obtaining a plurality of test control signals and generating a plurality of control signals, wherein the control signals comprise a first set of control signals and a second set of control signals, and controlling the top level data register using the first set of control signals; and a next test level, composed of one or more cores having a test wrapper, wherein the core is controlled by the top level test controller using the second set of control signals, an instruction decoder, an instruction register, a multiplexer and a state register, wherein the instruction register receives the data from a test data input signal and stores the data from the test data input signal as a test instruction, the instruction decoder is connected to output ports of the instruction register for receiving the test instruction, and the multiplexer selects a register connected to the standard test output port of the controller based on the test instruction and the value of the state register.