Patent ID: 8773449

Claim:
A circuit arrangement, comprising: hardware logic disposed in an integrated circuit device and configured to host a multithreaded rendering software pipeline using a plurality of parallel threads of execution, the multithreaded rendering software pipeline including a plurality of stages configured to render a stereoscopic image; first and second rendering channels implemented in the multithreaded rendering software pipeline, the first and second rendering channels respectively configured to render left and right views for the stereoscopic image; transformation logic implemented in the multithreaded rendering software pipeline, the transformation logic configured to receive vertex data for a scene, to apply a first transformation to at least a portion of the vertex data to generate first transformed vertex data for use by the first rendering channel in rendering the left view for the stereoscopic image, and to apply a second transformation to at least a portion of the vertex data to generate second transformed vertex data for use by the second rendering channel in rendering the right view for the stereoscopic image; wherein the multithreaded rendering software pipeline includes a shared grouper stage and a shared geometry engine stage configured to generate a common model including the vertex data for the scene, and wherein the first and second rendering channels each include respective first and second dedicated post GE stages, the first dedicated post GE stage of the first rendering channel configured to receive the vertex data of the common model from the shared geometry engine stage and apply the first transformation to the vertex data of the common model, and the second dedicated post GE stage of second first rendering channel configured to receive the vertex data of the common model from the shared geometry engine stage and apply the second transformation to the vertex data of the common model.