Patent ID: 7333366

Claim:
A memory device comprising: a first plurality of wells comprising a first type conductivity material formed in a second type conductivity substrate; a second plurality of wells comprising the second type conductivity material, each or the second plurality of wells located within a different one of the first plurality of wells; a plurality of memory array blocks each having a NAND architecture and arranged in rows, each row of memory array blocks coupled together by a different set of word lines of a plurality of sets of word lines, each memory array block located within a different one of the second plurality of wells wherein a voltage differential of 5V is applied between the first plurality of wells and the second plurality of wells of an unselected memory array block during an erase operation; and a plurality of row decoders each coupled to a different row of memory array blocks by a different set of word lines, external address signals coupled to the plurality of row decoders.