Patent ID: 8373435

Claim:
A system comprising: a first signal processor and a second signal processor, each of the first and second signal processor comprises a plurality of flip-flop elements arranged to form a scan chain when the respective signal processor is configured to operate in a mismatch handling mode; and a mismatch handler logic module, the mismatch handler logic module to detect a mismatch between outputs of the first and second signal processor, the mismatch between outputs indicating a failed operation, the mismatch handler logic further comprising: a first state analyzer logic module operably coupled to the first signal processor, and a second state analyzer logic module operably coupled to the second signal processor, wherein in response to detection of the mismatch the first and second state analyzer logic module are to analyze an internal state of the first and second processors respectively and are to generate a state signature value for the first and second signal processor respectively based at least on states of the respective plurality of flip-flop elements and to, upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and second signal processors.