Patent ID: 8707130

Claim:
A device, comprising: a plurality of memory cells operable to store a corresponding plurality of charges to provide a corresponding plurality of memory cell voltages within ranges that correspond to values of two bits stored in individual ones of the plurality of memory cells; a circuit operable to: determine a state of a first bit of the two bits of a corresponding one of the plurality of memory cells by application of a first voltage to the one of the plurality of memory cells, with the first voltage having a value to cause the one of the plurality of memory cells to provide an output indicative of the state of the first bit; select between a second voltage and a third voltage based on the output; and determine a state of a second bit of the two bits of the one of the plurality of memory cells by application of the selected voltage to the one of the plurality of memory cells, with the selected voltage having a value to cause the one of the plurality of memory cells to provide an output indicative of the state of the second bit.