Patent ID: 6907439

Claim:
A method for generating a sequence of FFT data addresses for an FFT circuit for operation on a P-point signal, wherein the operation includes n computation stages and m computation steps per computation stage, comprising: in a first computation stage: providing a computation stage value; providing a computation step value; generating a first pair of data addresses in parallel by inserting a logical “1” at a bit insertion position in one copy of a binary word and a logical “0” at the same bit insertion position in another copy of the binary word, wherein the computation stage value determines the bit insertion position and the computation step value determines the binary word; providing additional computation step values and generating additional pairs of data addresses in parallel by inserting a logical “1” at the bit insertion position in one copy of a binary word and a logical “0” at the same bit insertion position in another copy of the binary word, wherein the bit insertion position is unchanged but each binary word is determined by an additional computation step value; and repeating the above steps for additional computation stages, wherein the bit insertion position is determined by an additional computation stage value.