Patent ID: 7489560

Claim:
A method of programming a nonvolatile memory device having an array of cells arranged in a virtual ground architecture, each cell including a gate corresponding to a wordline in the array, a selectable source/drain formed in a semiconductor substrate and corresponding to a bitline in the array, and a selectable drain/source formed in the semiconductor substrate and corresponding to a bitline in the array, the method comprising: selecting a target cell in the array for programming; applying a positive programming voltage to the wordline corresponding to the target cell; applying a positive drain bias voltage to a first selectable bitline corresponding to the drain of the target cell; grounding a second selectable bitline corresponding to the source of the target cell; adjusting a negative substrate bias voltage in response to a write cycle status of the target cell and in response to the age of the nonvolatile memory device; and controlling bitline leakage current with the negative substrate bias voltage at the semiconductor substrate of the target cell.