Patent ID: 8773799

Claim:
An apparatus, comprising: read channel circuitry; and signal processing circuitry associated with the read channel circuitry, the signal processing circuitry comprising: frontend processing circuitry comprising a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal; backend processing circuitry comprising a backend detector, an interleaver, a backend decoder, and a de-interleaver, the backend processing circuitry being configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal; wherein the frontend processing circuitry is controlled by a first clock having an associated first clock rate and wherein the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate, the second clock rate being determined at least in part by the first clock rate and a maximum clock rate.