Patent ID: 8735903

Claim:
An essentially planar inverter circuit comprising: an n-channel transistor employing a first layer structure comprising: a first semiconductor layer having a conduction band minimum E C1 ; a second semiconductor layer having a first discrete hole level H 0 ; a first wide band gap semiconductor barrier layer disposed between the first and the second semiconductor layers; a first gate dielectric layer disposed above the first semiconductor layer; and a first gate metal layer disposed above the first gate dielectric layer; wherein the first discrete hole level H 0 is positioned below the conduction band minimum E c1 for zero bias applied to the first gate metal layer; and a p-channel transistor employing a second layer structure comprising: a third semiconductor layer having a second discrete hole level H 0 ; a fourth semiconductor layer having a conduction band minimum E C2 ; a second wide band gap semiconductor barrier layer disposed between the third and the fourth semiconductor layers; a second gate dielectric layer disposed above the third semiconductor layer; and a second gate metal layer disposed above the second gate dielectric layer; wherein the second discrete hole level H 0 is positioned below the conduction band minimum E c2 for zero bias applied to the second gate metal layer.