Patent ID: 8312307

Claim:
An Ethernet controller, comprising: at least one Media Access Controller (MAC); at least one interface to at least one PHY; and circuitry arranged to, when operational: cause generation of a signal for a first link partner signaling a first low power state; enter the first low power state, the first low power state to cause a reduction in power consumed by transmit circuitry during the first low power state; cause generation of a signal for the first link partner signaling end of the first low power state; await a first predefined period of time; after the first predefined period of time, cause transmission, in a first active power state, of at least one Ethernet data frame to the first link partner, the first active power state being a higher power consumption state of the transmit circuitry than the first low power state; receive an indication of a signal of the first link partner signaling a second low power state; enter the second low power state, the second low power state to cause a reduction in power consumed by receive circuitry during the second low power state; receive an indication of a signal of the first link partner signaling end of the second low power state; and enter a second active power state, the second active power state being a higher power consumption state of the receive circuitry than the second low power state and after a second predefined period of time, receive at least one Ethernet data frame from the first link partner.