Patent ID: 8236654

Claim:
A method, comprising: forming a layer of a silicon-containing semiconductor alloy on a first silicon-containing crystalline semiconductor region and a second silicon-containing crystalline semiconductor region; removing said layer of silicon-containing semiconductor alloy selectively from said second silicon-containing crystalline semiconductor region; forming a first gate electrode structure of a first transistor on said layer of a silicon-containing semiconductor alloy, said first gate electrode structure comprising a high-k dielectric gate insulation layer and a metal-containing gate electrode material formed on said high-k dielectric gate insulation layer; forming a second gate electrode structure of a second transistor above said second silicon-containing crystalline semiconductor region, said second gate electrode structure comprising a high-k dielectric gate insulation layer and a metal-containing gate electrode material formed on said high-k dielectric gate insulation layer of said second gate electrode structure; and forming source and drain regions of the first and second transistors in the first and second silicon-containing crystalline semiconductor regions, respectively.