Patent ID: 8799876

Claim:
A method comprising: linking a single first entry point of a first kernel to a dummy entry having a single entry point and a single exit point, the first kernel comprising a sequence of instructions including the single first entry point to a first instruction of the sequence of instructions and a single first exit point from a last instruction of the sequence of instructions; linking a single second entry point of a second kernel to the dummy entry, the second kernel comprising a second sequence of instructions including the single second entry point to a first instruction of the second sequence of instructions and a single second exit point from a last instruction of the second sequence of instructions, the single entry point of the dummy entry being a new single entry point for the first kernel and the second kernel; and compiling the first kernel and the second kernel to link the single first entry point of the first kernel and the single second entry point of the second kernel to the dummy entry to create a single compilation unit including the first kernel and the second kernel that permits seamless register usage of subroutines amongst the first and second kernels by a register allocation framework, the single first entry point of the first kernel and the single second entry point of the second kernel being linked to the single exit point of the dummy entry and the entry point of the compilation unit being the single entry point of the dummy entry.