Patent ID: 7042893

Claim:
A double data rate SMII circuit to communicate data synchronous with a clock signal having a rising edge and a falling edge, comprising: a transmit circuit, responsive to the clock signal, to sample serial transmit data on the clock rising edge to generate a first transmit serial stream, the transmit circuit, responsive to the clock signal, to sample the serial transmit data on the clock falling edge to generate a second transmit serial stream; a receive circuit, responsive to the clock signal, to generate a receive serial stream from two receive data streams, the receive serial stream having a first operating frequency, each of the two receive data streams having a second operating frequency, the first operating frequency being about twice the second operating frequency; a transmit port corresponding to the transmit circuit, including a single pin to communicate the serial transmit data to the transmit circuit; and a receive port corresponding to the receive circuit, including a single pin to communicate the receive serial stream from the receive circuit.