Patent ID: 8032783

Claim:
A memory apparatus having a function to notify a host of a memory capacity of user-accessible area of said memory apparatus, said memory apparatus comprising: a flash memory having a plurality of nonvolatile memory cells and being capable of storing data; and a controller to provide instructions to operate said flash memory based on externally issued commands, wherein said controller registers, as a faulty block, any block of said nonvolatile memory cells determined to be faulty in writing at a time of writing data into said flash memory, wherein said controller executes, after registering a block determined to be faulty, a determination test to perform at least one of write and read comparison on said block determined to be faulty, and if said block is found to be normal based on said determination test, said controller determines said block to be a good block for re-registering said block as a normal block, wherein said flash memory further comprises: a writable block management table indicating a plurality of said blocks into which data can be written; and an address conversion table indicating a plurality of addresses of blocks into which data have been written, wherein said controller performs an arbitrary one of a data erase operation, a data read operation, and a data write operation by a process using said writable block management table and said address conversion table, and wherein said controller executes a power on reset sequence after altering the memory capacity of said user-accessible area to a reduced memory capacity.