Patent ID: 8161361

Claim:
A signal processing apparatus comprising: an input to receive a signal, wherein the signal from the input comprises an analog signal; an analog-to-digital converter (ADC) to convert the analog signal to a digital signal; a buffer responsive to the ADC to store the digital signal; a filter in communication with the ADC to produce a filtered digital signal based on the digital signal; a detector responsive to the filter to interpret the filtered digital signal as discrete values; an averaging circuit in communication with the buffer and the detector to cause interpretation, by the detector during a retry mode, of a new signal comprising an average that is determined responsive to a group of signals, the group of signals comprising one or more previous signals stored in the buffer and a current signal; a control circuit that determines whether the discrete values are adequately indicated based on output of the detector, that initiates the retry mode when the discrete values are not adequately indicated, and that determines whether the discrete values are adequately indicated from the interpretation of the new signal in the retry mode based on a measurement of differences between hard decisions indicated by the new signal and hard decisions indicated by the current signal; and an error correction circuit in communication with the detector and the averaging circuit to provide a signal quality metric that is based on output of the detector, wherein the control circuit uses the signal quality metric to selectively exclude a signal of the group of signals from the average.