Patent ID: 7603589

Claim:
An integrated circuit device comprising: a processing circuit configured to execute a target program, the processing circuit having a plurality of registers; a trace system operatively coupled to the processing circuit, the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program; a first memory operatively coupled to the processing circuit, the first memory comprises a plurality of overlay regions; a memory subsystem operatively coupled to the processing circuit, the memory subsystem comprises a plurality of overlay programs, wherein the processing circuit is configured to execute overlay programs from the plurality of overlay regions; and a memory location operatively coupled to the trace system, the memory location writable by the target program; wherein the trace system is configured to send a value stored in the memory location to a host computer only when the value is newly written, the value stored in the memory location is indicative of which of the plurality of overlay programs have been executed by the processing circuit.