Patent ID: 7907472

Claim:
A semiconductor integrated circuit for fetching read data from DDR-SDRAMs operating in synchronization with a clock, and transferring the read data, the semiconductor integrated circuit comprising: read buffers each of which is coupled to a corresponding one of data strobe signals from a corresponding one of the DDR-SDRAMs, and configured to fetch read data from the corresponding one of the DDR-SDRAMs and to transfer the read data; latch timing control circuits each of which is coupled to the corresponding one of data strobe signals from the corresponding one of the DDR-SDRAMs, and configured to control a latch timing with which each read buffer fetches the read data from the corresponding one of the DDR-SDRAMs based on the corresponding one of the data strobe signals from the corresponding one of the DDR-SDRAMs; and a read timing control circuit for controlling a read timing with which each read buffer transfers the read data based on the latch timing of the corresponding latch timing control circuit, wherein: each latch timing control circuit and each read buffer are coupled to the corresponding one of the data strobe signals from the corresponding one of the DDR-SDRAMs, and the read timing control circuit controls the respective read timings for the read buffers.