Patent ID: 8477879

Claim:
A decoder system that decodes a bi-phase modulated signal, wherein each bit-window of the bi-phase modulated signal represents a single logic bit with each bit-window beginning with a logic transition, having a first logic state represented by substantially constant logic state through the bit-window and a second logic state represented by additional logic state transition in the approximate center of the bit-window, to generate an output code, the decoder system comprising: a first finite impulse response (FIR) filter associated with the first logic state configured to generate a first statistical value of a plurality of consecutive digital samples of the bi-phase modulated signal relative to a respective plurality of tap weights of the first FIR filter; a second FIR filter associated with the second logic state configured to generate a second statistical value of the plurality of consecutive digital samples of the bi-phase modulated signal relative to a respective plurality of tap weights of the second FIR filter; and a comparator connected to receive signals representative of the first and second statistical values and configured to compare the first and second statistical values and to provide the output code as a bit having one of the first logic state and the second logic state based on the comparison, wherein the plurality of tap weights of the first FIR filter comprises a range of values that are greater than or equal to a reference value, and wherein the plurality of tap weights of the second FIR filter comprises a first range of values corresponding to a first portion of the plurality of consecutive digital samples of the bi-phase modulated signal that are greater than the reference value and a second range of values corresponding to a second portion of the plurality of consecutive digital samples of the bi-phase modulated signal that are less than the reference value, the plurality of tap weights of each of the first and second FIR filters being normalized.