Patent ID: 7474004

Claim:
A stacked integrated circuit comprising: an integrated circuit; a plurality of thinned substantially flexible integrated circuits, wherein at least one of the plurality of thinned substantially flexible integrated circuits comprises a low stress dielectric layer, further comprising: a first substantially flexible integrated circuit having a first surface, wherein a plurality of first interconnections are located on the first surface; a second substantially flexible integrated circuit having a second surface, wherein a plurality of second interconnections are located on the second surface, said first and second surfaces face each other, said plurality of first interconnection and said plurality of second interconnections are substantially aligned with each other, and said plurality of first interconnections and said plurality of second interconnections are electrically coupled together to form a plurality of vertical interconnections, including redundant vertical interconnections; and a third interconnection electrically coupling the integrated circuit and at least one of the plurality of thinned substantially flexible integrated circuits, wherein the integrated circuit and the plurality of thinned substantially flexible integrated circuits are positioned in a stacked relation to one another, and wherein at least one of the substantially flexible integrated circuits comprises a substrate formed of a single crystal semiconductor.