Patent ID: 7176076

Claim:
A method of fabricating a semiconductor device comprising: forming well regions and isolation regions within a semiconductor body defining PMOS and NMOS regions of first and second regions; forming a first dielectric layer on the semiconductor body within the first region and the second region; removing the first dielectric layer from the first region; forming a second dielectric layer within the first region; forming a barrier layer over the first and second regions; patterning the barrier layer to cover the PMOS region of the first region, to cover the PMOS and NMOS regions of the second region, and to expose the NMOS region of the first region; removing the second dielectric layer from the NMOS region of the first region; forming a high-k dielectric layer over the first and second regions; selectively removing the high-k dielectric layer from the PMOS region of the first region and the PMOS and NMOS regions of the second region; and stripping the barrier layer.