Patent ID: 8692601

Claim:
A signal delay circuit comprising: a voltage detection unit configured to generate a detection signal in response to a result of comparing an external voltage level with a reference voltage, wherein the detection signal is determined by a variation of the external voltage level; and a signal delay unit configured to control a delay amount of an input signal in response to the detection signal and to include a first delay selector configured to be enabled to select a delay amount having a first delay time in response to the level of the detection signal and a second delay selector configured to be enabled to select a delay amount having a second delay time in response to the level of the detection signal, wherein the first delay time is set to be larger than the second delay time, wherein when the detection signal is at a low level, the first delay selector is enabled, and when the detection signal is at a high level, the second delay selector is enabled, wherein the voltage detection unit generates a high-level detection signal when the external voltage level is lower than the reference voltage.