Patent ID: 7839670

Claim:
A method for reading a 1T1C F-RAM device containing a plurality of F-RAM cells comprising; precharging a first bitline and a second bitline; precharging a first local I/O and a second local I/O; applying a WL signal to connect a F-RAM cell from said plurality of F-RAM cells to said first bitline which is coupled by a first current mirror to said first local I/O; applying a SA signal to connect a sense amp to said first local I/O and to said second local I/O; applying a YSEL signal to connect said first local I/O to said first current mirror; applying a reference signal to a complementary read path consisting of said second bitline, a second current mirror, and said second local I/O; applying a PL signal to read a data value from said F-RAM cell; removing said YSEL signal to disconnect said first local I/O from said first current mirror; applying a SAEN signal to activate said sense amp; and applying a WB signal to connect said first bitline to said second local I/O to rewrite said data value into said F-RAM cell.