Patent ID: 8436429

Claim:
A method for manufacturing stacked power semiconductor device with dual lead frame, comprising: providing a bottom lead frame comprising a first, a second and a third bottom bases; providing a bottom semiconductor chip having a first and a second electrodes on its front surface and a third electrode on its back surface, flip-chip mounting the bottom semiconductor chip on the bottom lead frame with the first and second electrodes electrically connected to the first and second bottom bases of the bottom lead frame; stacking a mounting clip on the back surface of the bottom semiconductor chip, the mounting clip having a downward extending part extending to and electrically connected to the third bottom base of the bottom lead frame; providing a top lead frame comprising a first and second top bases; providing a top semiconductor chip having a first and a second electrodes on its front surface and a third electrode on its back surface, mounting the top semiconductor chip on the top lead frame with the third electrode of the top semiconductor chip electrically connected to the first top base; flipping and stacking the top lead frame and the top semiconductor chip assembly on the mounting clip such that the first electrode of the top semiconductor chip electrically connected to the mounting clip ; encapsulating the bottom lead frame, the bottom semiconductor chip, the mounting clip, the top lead frame and the top semiconductor chip using a molding compound; and wherein the step of mounting the top semiconductor chip on the top lead frame further comprising wire bonding the second electrode of the top semiconductor chip to the second top base of the top lead frame.