Patent ID: 8178980

Claim:
A device, comprising: a semiconductor substrate having a top surface and an opposing bottom surface; a first conductive layer disposed on the top surface of the semiconductor substrate; a second conductive layer on the first conductive layer and electrically coupled to the first conductive layer; a passivation layer formed on the second conductive layer, the passivation layer including a passivation opening; a bond pad on the second conductive layer and disposed in the passivation opening, wherein a first surface of the bond pad provides a bonding region; and a connective layer interposing the first and second conductive layer, wherein the connective layer includes a contiguous, conductive structure providing a continuous, planar path of conductive material from a first point on a first lateral sidewall of the connective layer to a second point on a second lateral sidewall of the connective layer and wherein the connective layer further comprises at least one spacer interposing the first lateral sidewall and the second lateral sidewall, wherein the first point, the second point, and the at least one spacer are co-planar and wherein the first lateral sidewall and the second lateral sidewall of the connective layer are substantially perpendicular the top surface of the semiconductor substrate and substantially perpendicular to the first surface of the bond pad; a conductive via in the at least one dielectric spacer, wherein the dielectric spacer surrounds the lateral sidewalls of the conductive via, the lateral sidewalls of the conductive via being substantially parallel to the first lateral sidewall and second lateral sidewall.