Patent ID: 8209590

Claim:
An apparatus, comprising: a log-likelihood ratio (LLR) circuitry that is operative to calculate a plurality of LLRs corresponding to each respective bit location of a received bit sequence; an LDPC (Low Density Parity Check) decoder circuitry that is operative to: employ the plurality of LLRs as a first plurality of variable node edge messages in accordance with a first decoding iteration to generate a first plurality of variable node soft information values; perform chase combining of a first subset of the first plurality of variable node soft information values with a second subset of the first plurality of variable node soft information values thereby generating a modified first plurality of variable node soft information values; employ the modified first plurality of variable node soft information values to calculate a second plurality of variable node edge messages; employ the second plurality of variable node edge messages in accordance with a second decoding iteration to generate a second plurality of variable node soft information values; and perform chase combining of a first subset of the second plurality of variable node soft information values with a second subset of the second plurality of variable node soft information values thereby generating a modified second plurality of variable node soft information values; and a hard limiter that is operative to employ the modified second plurality of variable node soft information values to make bit estimates corresponding to the received bit sequence.