Patent ID: 8464201

Claim:
A simulation method for checking power loss of a printed circuit board (PCB) to be manufactured being performed by execution of instructions by a processor of an electronic device, the method comprising: reading a layout file of the PCB from a storage device of the electronic device; obtaining length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB by analyzing the layout file; calculating theoretical power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load located on the PCB; determining whether the theoretical power loss of each of the one more layers falls outside a preset range; and indicating precise locations of the power source areas and the ground trace areas of each of the one or more layers in the layout file, in warning that one or more copper cladding distributions in the power source areas and the ground trace areas needs to be amended, in response to the determination that the theoretical power loss in each of the one or more layers falls outside the preset range.