Patent ID: 7903017

Claim:
A comparator for a pipelined ADC comprising: a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal, and for sampling the plurality of differential reference voltages according to a second clock signal, the sampling circuit comprising a plurality of input voltage sampling switches, each input voltage sampling switch coupled to a corresponding one of the plurality of differential input voltages and controlled by the first clock signal; a plurality of reference voltage sampling switches, each reference voltage sampling switch coupled to a corresponding one of the plurality of differential reference voltages and controlled by the second clock signal; a plurality of first capacitors, each first capacitor comprising one terminal coupled to a corresponding one of the plurality of input voltage sampling switches and a corresponding one of the plurality of reference voltage sampling switches, and another terminal coupled to a corresponding one of the input terminals of the preamplifier; and a plurality of second capacitors, each second capacitor comprising one terminal coupled to a corresponding one of the plurality of input voltage sampling switches, a corresponding one of the plurality of reference voltage sampling switches, and a corresponding one of the plurality of first capacitors, and another terminal coupled to a ground; a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages; and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.