Patent ID: 7956665

Claim:
An integrated circuit, comprising: at least one functional unit configured to operate at a first frequency; at least one frequency divider configured to receive a first clock signal at a second frequency and generate a plurality of second clock signals, each having a third frequency; at least one first interconnect coupling a contact pad of the integrated circuit with an input of the frequency divider, wherein the at least one first interconnect is configured to transfer the first clock signal from the contact pad to the frequency divider; and at least one second interconnect coupling an output of the frequency divider with an input of the functional unit, a total length of the second interconnect being less than a total length of the first interconnect, wherein the at least one second interconnect is configured to transfer the plurality of second clock signals to the at least one functional unit, wherein the functional unit operates at the first frequency triggered by at least one of the leading edge and trailing edge of the plurality of second clock signals, wherein the frequency divider operates at a resonance frequency to recover a signal attenuation in the first interconnect coupling.