Patent ID: 7910923

Claim:
A semiconductor device, comprising: a plurality of inner switch structures arranged in parallel and integrated in an inner portion on one semiconductor chip, each switch structure including: a semiconductor substrate formed from a first semiconductor material; a hetero semiconductor region formed from a second semiconductor material having a band gap width different from that of the first semiconductor material, the hetero semiconductor region being hetero-adjoined with the semiconductor substrate; a gate insulation film adjoined to a heterojunction of the semiconductor substrate and the hetero semiconductor region; a gate electrode adjoined to the gate insulation film; a source electrode connected to a source contact portion of the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; and an outer switch structure arranged at an outermost portion of the semiconductor chip and not forming one of the plurality of inner switch structures, the outer switch structure including: an outer hetero semiconductor region formed of a third semiconductor material having different conductive-type impurities than the second semiconductor material and hetero-adjoined with the semiconductor substrate; an outer gate insulation film adjoined to a heterojunction of the semiconductor substrate and the outer hetero semiconductor region; and an outer gate electrode adjoined to the outer gate insulation film; wherein the source electrode of one of the plurality of inner switch structures is connected to a source contact portion of the outer hetero semiconductor region; and wherein the outer switch structure is a current-resistant structure configured to reduce current flowing at the outer switch structure when the inner switch structures are conducting the current.