Patent ID: 8432030

Claim:
A power electronic package comprising: first and second high thermal conductivity insulating non-planar substrates; and a plurality of semiconductor chips and electronic components, which are disposed between the first and second high thermal conductivity insulating non-planar substrates, wherein each of the first and second high thermal conductivity insulating non-planar substrates includes a plurality of electrical insulator layers and patterned electrical conductor layers, which are alternately stacked, the electrical conductor layers are connected to the electronic components with mechanical and electrical connection, each of the first and second high thermal conductivity insulating non-planar substrates further includes a plurality of recesses or wells, the recesses or wells are disposed on predetermined regions of at least one of the first and second high thermal conductivity insulating non-planar substrates, the predetermined regions on which the electronic components are located, the first and second high thermal conductivity insulating non-planar substrates are mechanically and electrically bonded with a plurality of bonding regions, and the electrical conductor layers are separated and isolated one another so that a plurality of electric circuits is provided on at least one of the first and second high thermal conductivity insulating non-planar substrates.