Patent ID: 8677201

Claim:
A semiconductor integrated circuit configured so that a transition scan test can be performed thereon, comprising: a plurality of logic circuit blocks having different operation frequencies; a clock supply unit for supplying a plurality of clock signals having frequencies corresponding to the operation frequencies of the logic circuit blocks from a clock supply source; a compression scan circuit including a plurality of scan chains formed of a plurality of flip-flop circuits, a pattern deployment circuit connected to the scan chains on an input side thereof, and a pattern compression circuit; and a clock control unit for controlling the clock supply unit to stop supplying the clock signals to specific ones of the flip-flop circuits of the scan chains when a capture operation is performed during a transition scan test, wherein said clock control unit includes a clock control flip-flop circuit so that the clock control unit controls the clock supply unit to stop supplying the clock signals to the specific ones of the flip-flop circuits according to a first specific value set to the clock control flip-flop circuit.