Patent ID: 7423574

Claim:
An analog-to-digital converter designed as a semiconductor integrated circuit, the analog-to-digital converter comprising: a pulse delay circuit provided with a plurality of delay units, the plurality of delay units each including at least one logic gate and operating based on a level of an input signal, the pulse delay circuit being configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units, a delay time of each of the plurality of delay units depending on the level of the input signal, the at least one logic gate being composed of at least one first transistor, the at least one first transistor having a first threshold voltage; and a generating circuit configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate digital data based on the obtained number, the generating circuit being composed of at least one second transistor, the at least one second transistor having a second threshold voltage, the first threshold voltage of the at least one first transistor being lower than the second threshold voltage of the at least one second transistor.