Patent ID: 8427355

Claim:
An analog-to-digital converter (ADC) circuit, comprising: multiple time-interleaved successive approximation register (SAR) ADCs, each of the multiple time-interleaved SAR ADCs comprising: a first stage SAR sub-ADC for coarse conversion, the first stage SAR sub-ADC receiving and converting an analog input signal to generate a first digital code and a residue signal; a residue amplifier for amplifying the residue signal generated by the first stage SAR sub-ADC to output a amplified residue signal, wherein the residue amplifier is shared between the multiple time-interleaved SAR ADCs; a second stage SAR sub-ADC for fine conversion, the second stage SAR sub-ADC receiving and converting the amplified residue signal to generate a second digital code; and a digital error correction logic for receiving and combining the first digital code generated by the first stage SAR sub-ADC and the second digital code generated by the second stage SAR sub-ADC to generate digital representation of the analog input signal; wherein the residue amplifier is a single-stage operation amplifier having a low gain and operating in sub-threshold.