Patent ID: 8171191

Claim:
A data processing chip comprising: a bus interconnect device formed of a parallel plate waveguide comprising parallel plates, said parallel plates separated by a distance in a first dimension orthogonal to said plates, said plates extending in second and third dimensions, said second and third dimensions orthogonal to each other; a plurality of at least three devices forming a plurality of functional blocks of the data processing chip that are coupled together by the bus interconnect device, each device being coupled into the parallel plate waveguide at a chosen location within one of the parallel plates, wherein the relative positioning of each device with respect to the other at least two devices is arbitrary in said second and third dimensions; said plurality of at least three devices being arranged to communicate via radio frequency (RF) signals propagated through the parallel plate waveguide as waves radiated between the parallel plates in said second and third dimensions, allowing direct simultaneous communications between devices of said at least three devices, wherein: the plurality of functional blocks includes an array of processing elements, the plurality of functional blocks being further coupled via a wired bus network, the parallel plate waveguide is useable for global communication among the array of processing elements, and the wired bus network is useable for inter-neighbor communication between the processing elements.