Patent ID: 7985652

Claim:
A method of manufacturing a semiconductor device comprising: providing a substrate, wherein the substrate includes a source/drain for an NMOS transistor and a source/drain for a PMOS transistor; forming a first barrier layer on the substrate; forming a first stressor-material on the first barrier layer; selectively removing the first stressor-material from the PMOS transistor; selectively removing the first barrier layer from the PMOS transistor; annealing the substrate in a dopant activation anneal; removing the remaining first stressor-material; removing the remaining first barrier layer, thereby implementing a first stress process; following the first stress process, forming a second barrier layer on a metal silicide layer formed on the substrate; depositing a second stressor-material on the second barrier layer; performing a second silicide anneal on the substrate; and selectively removing the second stressor-material.