Patent ID: 7904603

Claim:
A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising: a plurality of functional units configured to perform a digital operation; one or more data address generators coupled to the memory bus; a configurable data path configurably coupled to the one or more data address generators and the plurality of functional units, the configurable data path being configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between the one or more data address generators and the plurality of functional units, the data path configuration including the configured or reconfigured interconnections; wherein the one or more data address generators are coupled to the memory bus and the configurable data path, each of the one or more data address generators being configurable in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration; and wherein the second configuration information includes predication information, the generation of the memory addresses in response to the second configuration information being conditioned upon the predication information.