Patent ID: 7348256

Claim:
A method of fabricating an electronic device, the method comprising: forming a gate oxide on an uppermost side of a substrate; forming a first polysilicon layer over the gate oxide; forming a first dielectric layer over the first polysilicon layer, the first dielectric layer being of a first dielectric type; forming a second dielectric layer over the first dielectric layer, the second dielectric layer comprised of a material that may be selectively etched at a rate different from the first dielectric layer; forming a third dielectric layer over the second dielectric layer, the third dielectric layer being of a same or similar dielectric as the first dielectric layer; etching shallow trenches through the gate oxide layer, the polysilicon layer, each of the dielectric layers, and into the substrate; filling the etched trenches with a fourth dielectric layer; forming the fourth dielectric layer to be substantially coplanar with an uppermost surface of the third dielectric layer; removing the first dielectric layer; removing the second dielectric layer; and removing the third dielectric layer, removal of the first, second, and third dielectric layers thereby exposing an uppermost sidewall area of the fourth dielectric layer; and forming a second polysilicon layer.