Patent ID: 8296708

Claim:
A computer-implemented method for generating at least one placement for an integrated circuit (IC), wherein the integrated circuit (IC) comprises a plurality of device modules, the method comprising using a computer to perform the steps of: a. receiving a plurality of constraints for generating at least one placement for the integrated circuit (IC), wherein each constraint is assigned a priority; b. forming, using the computer, a constraint hierarchy tree comprising a root node, a plurality of internal nodes and a plurality of leaf nodes according to the plurality of constraints, wherein the root node represents the placement of the integrated circuit (IC), each of the internal nodes represents a constraint for its corresponding set of the device modules respectively and each of the leaf nodes represents its corresponding device module respectively, the step comprising the sub-steps of: b1. building an initial hierarchy tree comprising the root node and the plurality of leaf nodes; and b2. selecting each of the plurality of constraints in descending order of assigned priorities, and for each selected constraint, inserting an internal node representing the said constraint into the hierarchy tree, wherein if a conflict is found between the said constraint and any of the other constraints in the hierarchy tree, discard the said constraint to remove the conflict, and remove the said internal node; and c. generating at least one placement for the integrated circuit (IC) by satisfying each of the constraints in the hierarchy tree from the bottom to the top of the tree sequentially.