Patent ID: 7385838

Claim:
A semiconductor device comprising a memory block and an input/output circuit, wherein: said memory block includes a memory array including a plurality of word lines, a plurality of bit lines crossing said plurality of word lines, and a plurality of memory cells provided at respective intersections of said plurality of word lines and said plurality of bit lines; and each of said plurality of memory cells includes a MOS transistor, a memory device, a first node connected to a corresponding one of said plurality of word lines and a gate of said MOS transistor, a second and third nodes between which a source-drain path of said MOS transistor and said memory device are connected, and said memory device being connected to said third node; and in a case where first information is written into said memory device, a current flows from said second node to said third node, and in a case where second information is written into said memory device, a current flows from said third node to said second node.