Patent ID: 7170313

Claim:
An apparatus for calibrating termination voltage of an on-die termination for a semiconductor memory device having a DLL circuit, the apparatus comprising: the DLL circuit receiving a DLL RST input signal, which is enabled when a predetermined signal including a signal DLL Reset EMRS is applied; an on-die termination enable signal generating part for outputting an ODT enable signal for driving the on-die termination (ODT) when the signal DLL Reset EMRS is applied; a counter circuit for outputting a plurality of counter signals; an on-die termination (ODT) part including a variable resistor part controlled by the counter signals outputted from the counter circuit and outputting a variable termination voltage according to a resistance value of the variable resistor part; and a first control part for comparing a reference voltage with the termination voltage and outputting a control signal for controlling the counter circuit according to a comparison result.