Patent ID: 8884353

Claim:
A semiconductor memory device comprising: first and second memory cells including: a source region and a drain region formed separately from each other in a surface of a semiconductor substrate; a channel region formed in the semiconductor substrate and located between the source region and the drain region; a charge storage layer formed on the channel region with a first insulating film interposed therebetween; and a control gate electrode formed on the charge storage layer with a second insulating film interposed therebetween, and including a semiconductor layer formed on the second insulating film and a metal silicide layer formed on the semiconductor layer, the metal silicide layer including an upper area having a first width, and a lower area having a second width wider than the first width, the metal silicide layer having a dented shape including an area having a third width which is most narrow in the metal silicide layer, and a corner portion of the dented shape of the control gate electrode having a rounded shape, wherein the drain regions of the first and second memory cells are connected to each other, and a height of the semiconductor layer is higher than a distance from a lowest surface of the metal silicide layer to a position of the metal silicide layer at the third width.