Patent ID: 7243324

Claim:
A method comprising steps of: (a) receiving as input an integrated circuit design comprising a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying a candidate leaf node in the tree network, the candidate leaf node having a required pin-specific target delay that is less than a selected minimum delay; (d) inserting a buffer between a first node that is traversed by a path from the candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from a second node upstream from the first node; (f) separating the buffer from the first node and reconnecting the buffer to a buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.