Patent ID: 8458446

Claim:
A processor, comprising: an instruction fetch unit configured to issue instructions for execution, wherein the instructions are selected from a plurality of threads, wherein each given instruction has a corresponding thread identifier identifying the given instruction's associated thread, and wherein at least some of the instructions specify one or more operands via one or more of a plurality of register identifiers; and a register file configured to store operands usable by said instructions during execution, wherein said register file comprises a plurality of banks, wherein each of said banks corresponds to a respective one of the register identifiers, wherein each of said banks comprises a plurality of entries corresponding to said plurality of threads, wherein the entries are configured to store data values; wherein in response to receiving a request to read a particular register identifier, wherein the request corresponds to a given thread identifier, the register file is configured to: decode the given thread identifier to generate a selection signal coupled to each of the plurality of banks to retrieve entries from the plurality of banks that correspond to the given thread identifier, wherein the selection signal selects a particular entry from each of the plurality of banks; and from among the retrieved entries, select a data value corresponding to the particular register identifier to be output as a result of said request.