Patent ID: 7146486

Claim:
A scalar processor comprising: a plurality of scalar arithmetic logic units, wherein each of the scalar units is operative to perform, in a different time interval, the same operation on a different data item, each different time interval being one of a plurality of successive, adjacent time intervals, wherein each unit provides an output data item in the time interval in which the unit performs said operation and each unit provides a processed data item in a last one of the successive, adjacent time intervals; a multiplexer configured to provide the output data item from a selected one of the scalar units; and a single special function unit operable to provide a special function computation for the output data item of a selected one of the scalar units, in the time interval in which the selected scalar unit performs said operation, so as to avoid a conflict in use among the scalar units; wherein each scalar unit has an address and control path for carrying address and control information that commands said operation, said address and control path including a delay element having a delay equal to the time interval, said address and control paths being connected in series such that the address and control information arrives at each unit in the time interval in which the scalar unit performs said operation; and wherein each scalar unit has a data processing path and one or more delay paths, each including a delay element having a delay equal to the time interval, connected in series with the data processing path such that each different data item arrives in the scalar unit in the interval in which the unit performs said operation and such that the processed data item from each unit is available in the last of the successive time intervals.