Patent ID: 7969203

Claim:
A sample/hold feed switch for switchably connecting and isolating an input node connectable to signal source for receiving an input signal, to and from an output node connectable to a sampling capacitor for holding a sample of the input signal, comprising: a first signal branch connected at one end to the input node and at the other end to the output node, having a first PMOS signal switch FET and a first PMOS dummy FET, the first PMOS signal switch FET having a corresponding switch FET body connection and the first PMOS dummy FET having a corresponding dummy FET body connection, a first gate-to-source capacitance connected to the first PMOS signal switch FET, a first gate-to-drain capacitance connected to the first PMOS signal switch FET, a second gate-to-source capacitance connected to the first PMOS dummy FET, and a second gate-to-drain capacitance connected to the first PMOS dummy FET; a second signal branch connected at one end to the input node and at the other end to the output node, having a second PMOS signal switch FET and a second PMOS dummy FET, the second PMOS signal switch FET having a corresponding switch FET body connection and the second PMOS dummy FET having a corresponding dummy FET body connection, a third gate-to-source capacitance connected to the second PMOS signal switch FET, a third gate-to-drain capacitance connected to the second PMOS signal switch FET, a fourth gate-to-source capacitance connected to the second PMOS dummy FET, and a fourth gate-to-drain capacitance connected to the second PMOS dummy FET; a switch FET bias switching sequencer connected to the switch FET body connections to switch the switch FET body connections of the PMOS signal switch FETs between the input node and a V DD supply; a dummy FET bias switching sequencer connected to the dummy FET body connections to switch the dummy FET body connections of the PMOS dummy FETs between the output node and the V DD ; and a clock generator circuit, connected to the switch FETs and to the gates of the dummy FETs, that generates a clock signal (CLK) switching between a sample state voltage and a hold state voltage, generates an inverse of the CLK (NCLK), and inputs to said switch FETs and said dummy FETs CLK and NCLK to control the switch FETs and to control the dummy FETs to switch from a first operation state to a second operation state; wherein the sampling capacitor, the first and third gate-to-source capacitances, and the first and third gate-to-drain capacitances produce a switch offset voltage, the sampling capacitor, the second and fourth gate-to-source capacitances, and the second and fourth gate-to-drain capacitances produce a dummy offset voltage, and the dummy offset voltage is approximately equal to the switch offset voltage.