Patent ID: 7240163

Claim:
A microprocessor, comprising: a cache memory, having a plurality of sets each configured to store at least one cache line; a prefetch buffer, coupled to said cache memory, for receiving a prefetched cache line from a system memory, wherein said prefetch buffer is unassociated with any particular one of said plurality of sets of said cache memory, but rather said prefetched cache line may be selectively retired from said prefetch buffer to any of said plurality of sets depending upon a memory address of said prefetched cache line; a prefetch address register, configured to store said memory address of said prefetched cache line stored in said prefetch buffer; and control logic, coupled to said prefetch buffer, for selectively retiring said prefetched cache line into a candidate set of said plurality of sets of said cache memory based on accesses to said prefetched cache line contemporaneous with prefetching said prefetched cache line into said prefetch buffer, wherein said candidate set is one of said plurality of sets selected by said memory address of said prefetched cache line.