Patent ID: 8623739

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a device isolation layer in a substrate including a first region and a second region to define a plurality of active regions in the substrate; forming a plurality of sacrificial layer patterns on the first region and the second region of the substrate, respectively; forming a plurality of insulating spacers on a sidewall of the sacrificial layer patterns in the first region and the second region; filling an insulating layer between spaces defined by the insulating spacers between the sacrificial layer patterns; removing the sacrificial layer patterns from the first region and the second region, so that the active regions of the substrate are exposed through a first space in the first region and a second space in the second region, respectively formed between an adjacent two of the insulating spacers; conformally forming a gate insulating layer to cover exposed surfaces of the first space in the first region and the second space in the second region; forming a first metal stack layer on the gate insulating layer in the first region and the second region; forming a p-type metal-oxide semiconductor (PMOS) work function metal layer on the first metal stack in the first region and the second region; forming a protective layer covering substantially an entire upper surface of the PMOS work function layer in the first region and the second region; forming a resist pattern covering the protective layer in the second region and exposing a surface of the protection layer in the first region; bringing a descum solution into contact with the exposed surface of the protection layer in the first region and with the resist pattern, wherein the descum solution comprises a water soluble polymer and a solvent; performing a baking process on the descum solution; removing the descum solution from the resist pattern and the exposed surface of the protection layer; removing the protection layer exposed in the first region by using the resist pattern as an etching mask; removing the resist pattern in the second region; removing the PMOS work function metal layer in the first region using the protection layer remaining in the second region as an etching mask; removing the protection layer remaining in the second region; forming a second metal stack layer constituting an n-type metal-oxide semiconductor (NMOS) work function metal layer on the first region and the second region; sequentially forming a third metal stack layer and a capping layer on the second metal stack layer in the first region and the second region; and performing a planarization process on the capping layer until an upper surface of the insulating layer is exposed in the first region and the second region, such that a first gate stacked structure is formed which remains in the first space in the first region and a second gate stacked structure is formed which remains in the second space in the second region.