Patent ID: 7737554

Claim:
An integrated circuit structure comprising: a memory array comprising memory cells formed in rows and columns; contacts connected to the memory array; a first bottom metallization (M 1 ) layer over the semiconductor substrate, wherein the first M 1 layer comprises first metal lines, each of the first metal lines having a plurality of first contacts; and a second M 1 layer over the first M 1 layer, wherein the second M 1 layer comprises second metal lines substantially parallel to the first metal lines, each of the first metal lines having a plurality of second contacts, and wherein the first metal lines and the second metal lines alternate in a plan view, and wherein the second contacts electrically coupled to the second metal lines that are adjacent to a selected one of the second metal lines are not in a plane that is orthogonal to the second metal lines and that intersects any of the second contacts in the selected one of the second metal lines.