Patent ID: 6876074

Claim:
A unit package comprising: a semiconductor chip having an active surface; and a double wiring substrate, the double wiring substrate including, a flexible tape having, an upper surface with a first electrically conductive layer affixed thereon, said first electrically conductive layer defining a first wiring pattern; a lower surface with a second electrically conductive layer affixed thereon, said second electrically conductive layer defining a second wiring pattern; a plurality of vias electrically connecting portions of said first wiring pattern to portions of said second wiring pattern; and an adhesive film having a first side affixed to said second electrically conductive layer and a second side with at least a portion thereof affixed to said active surface of said semiconductor chip; and the double wiring substrate defining a window exposing a portion of the active surface through which a plurality of bonding wires electrically connect the active surface to the first wiring pattern; wherein a portion of said flexible tape extends around an edge of and to a bottom surface of said semiconductor chip with said adhesive film.