Patent ID: 7713801

Claim:
A method for making a semiconductor structure, the method comprising: providing a wafer with a transistor comprising a control electrode overlying a substrate and having a sidewall; forming a sidewall spacer liner in contact with the sidewall of the control electrode to protect the control electrode; forming a sidewall spacer adjacent to the sidewall; forming a layer of material over the wafer including over the sidewall spacer and over the control electrode having the sidewall, the layer of material having a varying thickness wherein a thickness on all horizontal regions is substantially twice or more than a thickness on all vertical regions; etching the layer with a first wet etch, wherein the etching (i) leaves at least portions of the sidewall spacer exposed and (ii) leaves a portion of the layer located over the control electrode having a sidewall, wherein the portion of the layer located over the control electrode having a sidewall is reduced in thickness by the etching; removing with a second wet etch that is selective to the sidewall spacer liner the sidewall spacer after the etching the layer to expose the sidewall spacer liner, the control electrode being protected from the wet etch by both the portion of the layer located over the control electrode and the sidewall spacer liner; and protecting the control electrode from subsequent processing of the wafer with both the portion of the layer located over the control electrode and the sidewall spacer liner.