Patent ID: 7017070

Claim:
A signal phase shifting circuit operative to shift the phase of a STROBE signal based on a clock signal comprising: a clock signal period dividing circuit having: a first input that receives the clock signal, a second input that receives a feedback control signal, a phase shift generating circuit operatively responsive to the clock signal and the feedback control signal; an output that provides a voltage controlled delay control signal for a variable delay circuit, and a feedback delay matching array operatively coupled to an output of the phase shift generating circuit, that produces the feedback control signal; and the variable delay circuit including an input that receives the STROBE signal and being operatively responsive to the delay control signal, to provide a phase shifted output signal of the STROBE signal associated with a double data rate communication; and wherein the phase shift generating circuit includes a delay lock loop circuit operatively responsive to the clock signal and the feedback control signal and wherein the feedback delay matching array includes buffer stages that compensate for delay variations associated with a phase shifted output signal drive buffer and multiplexing circuit in a STROBE signal receive path.