Patent ID: 8144046

Claim:
A linearity enhancement circuit comprising: a first shift amount creation block configured to create a first shift amount in keeping with the immediately preceding output code of an n-bit analog/digital converter; a first shifter circuit configured to bit-shift input code data by said first shift amount that has been supplied, said first shifter circuit further outputting the bit-shifted input code data; a register configured to store the output of said first shifter circuit in order to output the stored data as said input code data to said first shifter circuit thereby forming a loop circuit in conjunction with said first shifter circuit, said register further outputting the stored code data as a second shift amount; and a second shifter circuit configured to bit-shift the output code of said analog/digital converter by said second shift amount that has been supplied, said second shifter circuit further outputting the bit-shifted output code to an n-bit digital/analog converter.