Patent ID: 8399926

Claim:
A semiconductor device comprising: a semiconductor substrate; first semiconductor layers having fin-shapes formed at an upper part of the semiconductor substrate, each of the first semiconductor layers having a first top surface with a (100) plane and a first side face with a (100) plane; and pMISFETs, wherein each of the pMISFETs has a first channel region formed at least at the first side face, a first gate dielectric film formed at least on the first side face, a first gate electrode covering the first channel region with the first gate dielectric film being sandwiched therebetween, and first source/drain regions formed within each of the first semiconductor layers in such a way as to interpose the first channel region therebetween, the first gate electrode is located above the first semiconductor layers as well as between the first semiconductor layers, the first gate electrode includes a first semiconductor film having an impurity concentration higher in portions above the first semiconductor layers than in portions between the first semiconductor layers, and the first channel region is applied a compressive strain in a direction perpendicular to a surface of the semiconductor substrate.