Patent ID: 7943405

Claim:
A method of fabricating a liquid crystal display device, comprising: forming a gate pattern including a gate line, a first gate electrode of a sensor thin film transistor, a second gate electrode of a first thin film transistor, and a third gate electrode of a second thin film transistor on a first substrate; forming a gate insulating film on a substrate provided with the gate pattern; forming a first semiconductor pattern overlapped with the first gate electrode, a second semiconductor pattern overlapped with the second gate electrode, and a third semiconductor pattern overlapped with the third gate electrode on the gate insulating film; forming a source/drain pattern including a data line crossing the gate line, a first source electrode and a first drain electrode connected to a first semiconductor pattern, and positioned in such a manner to oppose to each other, a second source electrode and a second drain electrode connected to a second semiconductor pattern, and positioned in such a manner to oppose to each other, and a third source electrode and a third drain electrode connected to a third semiconductor pattern, and positioned in such a manner to oppose to each other with the gate insulating film therebetween to provide a sensor thin film transistor, and a first and second thin film transistors; forming a protective film having a first hole for exposing the second drain electrode of the first thin film transistor; and forming a pixel electrode connected, via the first hole, to the second drain electrode, wherein the first source electrode of the sensor thin film transistor and the second source electrode of the first thin film transistor are connected to the data line, respectively, forming a second storage capacitor for storing a signal sensed by the sensor thin film transistor, wherein said forming the gate pattern comprises: forming a driving voltage supply line formed in parallel to the gate line to supply a driving voltage to the sensor thin film transistor, and forming a first lower storage electrode in parallel to the gate line and extended from the driving voltage supply line, wherein said forming the source/drain pattern comprises: forming a first upper storage electrode formed in such a manner to overlap with the first lower storage electrode with the gate insulating film to consist of the first lower storage electrode and the first storage capacitor, wherein said step of forming the source/drain pattern comprises: forming a sensing signal transmitting line positioned in parallel to the data line and connected to the third drain electrode of the second thin film transistor.