Patent ID: 8097917

Claim:
A silicon carbide semiconductor device comprising: a semiconductor substrate including a silicon carbide substrate having a first conductive type or a second conductive type, a first semiconductor layer made of the first conductive type silicon carbide and having an impurity concentration lower than an impurity concentration of the silicon carbide substrate, a second semiconductor layer made of a second conductive type silicon carbide, and a third semiconductor layer made of the first conductive type silicon carbide, which are stacked in this order from the semiconductor substrate to the third semiconductor layer; a trench disposed in a cell region of the semiconductor substrate and penetrating the second and the third semiconductor layers to contact the first semiconductor layer; a channel layer having the first conductive type and disposed on a sidewall and a bottom of the trench; an oxide film disposed on the channel layer in the trench and including a part for functioning as a gate oxide film; a gate electrode disposed on a surface of the oxide film in the trench; a first electrode electrically connecting to the third semiconductor layer; and a second electrode electrically connecting to the silicon carbide substrate, wherein any position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film in the trench, the silicon carbide substrate has the first conductive type, a plurality of second trenches are disposed in the silicon carbide substrate, each second trench being disposed from a backside of the silicon carbide substrate to the first semiconductor layer, each of the second trenches is embedded with an impurity layer having the second conductive type, and the second electrode contacts the silicon carbide substrate and the impurity layer in each of the second trenches, and wherein each of the second trenches penetrates the silicon carbide substrate so that the impurity layer in each of the second trenches contacts the first semiconductor layer.