Patent ID: 8854754

Claim:
A data processing circuit, the data processing circuit comprising: a data decoder circuit operable to perform a number of local iterations on a decoder input to yield a data output; a local iteration adjustment circuit operable to generate a limit on the number of local iterations performed by the data decoder circuit; a data detector circuit operable to apply a data detection algorithm to a received input to yield the decoder input, wherein processing through both the data detector circuit and the data decoder circuit is a global iteration; and wherein the data detector circuit and the data decoder circuit are operable to apply: a first global iteration the received input; a second global iteration to the received input; wherein the limit on the number of local iterations performed by the data decoder circuit is a first limit corresponding to the first global iteration; and wherein the local iteration adjustment circuit is further operable to generate a second limit on the number of local iterations performed by the data decoder circuit corresponding to the second global iteration.