Patent ID: 7679397

Claim:
An integrated circuit comprising: a plurality of parallel output transistors coupled between an external terminal and a power supply rail, each of said output transistors receiving a different control signal at its gate terminal so as to selectively drive the external terminal; a feedback circuit having a first input coupled to the external terminal and a second input coupled to receive a reference signal, and to generate an analog calibration signal; and a calibration circuit having an analog input coupled to receive the analog calibration signal, a plurality of control input terminals coupled to receive a respective plurality of control signals, and a plurality of outputs coupled to the plurality of parallel output transistors, respectively, the calibration circuit comprising a voltage divider circuit, the voltage divider circuit to divide the analog calibration signal voltage and provide the divided analog calibration signal voltage as one of the plurality of outputs to one of the plurality of parallel output transistors, wherein, in response to the plurality of control signals, the calibration circuit enables a selected number of the plurality of parallel output transistors.