Patent ID: 7315957

Claim:
A method of changing a frequency of a memory clock signal provided to a memory, the method comprising: generating a first clock signal having a first clock frequency using a first clock source; generating a second clock signal having a second clock frequency using a second clock source; selectively providing the first clock signal having the first clock frequency to the memory; determining a start time for a first vertical synchronizing signal; determining a start time for a second vertical synchronizing signal; and if the difference in start times for the first and second vertical synchronizing signals is below a first value; then selectively providing the second clock signal having the second clock frequency to the memory; and changing the first clock frequency of the first clock signal to a third clock frequency; else continuing to selectively provide the first clock signal having the first clock frequency to the memory; and after selectively providing the second clock signal having the second clock frequency to the memory; then determining a start time for a first vertical synchronizing signal; determining a start time for a second vertical synchronizing signal; and if the difference in start times for the first and second synchronizing signals is below a first value; then selectively providing the first clock signal having the third clock frequency to the memory, else continuing to selectively provide the second clock signal having the second clock frequency to the memory.