Patent ID: 7606111

Claim:
A page-mode phase-change memory (PCM) comprising: a data input that receives a write data word in response to a write request and a write address; a data output that outputs a read data word in response to a read request and a read address; a host write buffer, coupled to the data input, for storing the write data word; a host read buffer, coupled to the data output, for storing the read data word; a plurality of PCM cells each having a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase; a cache for storing copies of data lines stored in the plurality of PCM cells, the cache having lines of data and tags of addresses for the lines of data; a plurality of banks, each bank comprising: an array of the plurality of PCM cells; a row decoder, receiving a row portion of the write address or receiving a row portion of the read address, for selecting a row of the plurality of PCM cells selected by an activated word line selected from a plurality of word lines in the array; a column decoder, receiving a column portion of the write address or receiving a column portion of the read address, for selecting a column of the plurality of PCM cells in the array as selected PCM cells; local sense amplifiers for reading read data stored in the selected PCM cells in response to the read address; local write drivers for driving a set pulse for a set period of time to the selected PCM cells that are being written to a first logical state, and for driving a reset pulse for a reset period of time to the selected PCM cells that are being written to a second logical state; a multi-line page buffer, coupled between the local sense amplifiers for the plurality of PCM cells and the cache, for storing multiple lines of data read from the plurality of PCM cells for storage in the cache, and coupled between the local write drivers for the plurality of PCM cells and the cache, for storing multiple lines of data to be written into the plurality of PCM cells for storage; write data lines coupled between the host write buffer and the cache, for initially storing the write data word in the cache; and read data lines coupled between the host read buffer and the cache, for reading the read data word from the cache when a tag portion of the read address matches a tag in the cache, whereby set and reset pulses are driven to the selected PCM cells from the write data word initially stored in the cache, freeing the write data lines for other data transfers when the set and reset pulses are applied.