Patent ID: 7317208

Claim:
A thin film transistor array panel for a liquid crystal display, comprising: a gate line formed on a substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line formed at least in part on the semiconductor layer; a drain electrode formed at least in part on the semiconductor layer and spaced apart from the data line; a first insulating layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second insulating layer formed on the first insulating layer and having a second contact hole exposing the drain electrode and aligned with the first contact hole, wherein the aligned first and second contact holes form a structure having a width and a height, wherein the width varies along the height of the structure; and a pixel electrode formed on the second insulating layer and connected to the drain electrode through the first and the second contact holes, wherein at least one of the gate insulating layer and the first inslulating layer has a third contact hole exposing a portion of the gate line or a portion of the data line and further comprising: a contact assistant including the same layer as the pixel electrode and electrically connected to either of the gate line or the data line.