Patent ID: 7916541

Claim:
A NAND flash memory in which all bit lines are pre-charged and simultaneously read, comprising: a memory cell array including a plurality of blocks each of which includes: a memory cell unit, which includes a plurality of electrically rewritable memory cells connected in series to each other and each of which is formed in a p-type well surrounded by a n-type well formed in a p-type semiconductor substrate, a drain-side select gate transistor that is connected to a drain-side select gate line at the gate thereof and that connects the memory cell unit to a bit line, and a source-side select gate transistor that is connected to a source-side select gate line at the gate thereof and that connects the memory cell unit to a source line; a row decoder that is connected to word lines connected to gates of the memory cells, the drain-side select gate line and the source-side select gate line, that makes a selection from the blocks by controlling the voltage applied to the drain-side select gate line and the source-side select gate line, and that selects the memory cell for operation by controlling the voltage applied to the word line; and a sense amplifier that is connected to the bit lines of the memory cell array and that detects data in the selected memory cell, wherein in a read operation, the p-type semiconductor substrate is set at a ground potential, the bit line is charged to a first voltage, the source line, the n-type well and the p-type well are charged to a second voltage, which lies between the ground potential and the first voltage, and in the block not selected by the row decoder, the source-side select gate transistor is cut off.