Patent ID: 7561459

Claim:
A semiconductor memory device comprising: a ferroelectric capacitor including a ferroelectric between a first electrode and a second electrode; a cell transistor having a source connected to the first electrode; a cell array in which a plurality of memory cells including the ferroelectric capacitors and the cell transistors are arranged in a matrix on a semiconductor substrate; a plurality of bit lines provided to correspond to columns of the memory cells and connected to a drain of the cell transistor; a plurality of word lines provided to correspond to rows of the memory cells and connected to a gate of the cell transistor; n plate lines corresponding to n column blocks and connected to the second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.