Patent ID: 8190858

Claim:
An interface device for interfacing a main processor and a processing engine, the interface comprising a settings storage to store variables of the processing engine, the variables including a translation of instructions into an operation code set of the processing engine a conversion of operands into a format of the processing engine a pin map of the processing engine a clock rate of the processing engine a main processor interface having a first pipe to couple to a first bus, the main processor interface to receive messages via the first bus from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate a decoder coupled to the settings storage to separate the messages into instructions and operands translate the instructions to the operation code set of the processing engine according to the translation variable stored in the settings storage convert the operands to the format of the processing engine according to the conversion variable stored in the settings storage a processing engine interface having a second pipe to couple to a second bus, the processing engine interface to send translated operation codes and converted operands via the second bus to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate to be used in conformance with the processing engine pin map and the processing engine clock rate.