Patent ID: 7115460

Claim:
An apparatus, comprising: a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein the first and second doped wells have opposite dopant types, and wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential; and a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potentials, wherein the first tap cell doped region has the same dopant type as the first doped well but a higher dopant concentration relative to the first doped well, and wherein the second tap cell doped region has the same dopant type as the second doped well but a higher dopant concentration relative to the second doped well.