Patent ID: 8097498

Claim:
A method of making a device, comprising: providing a first device level comprising first semiconductor rails separated by first insulating features, the first semiconductor rails extending in a first direction; forming a sacrificial layer over the first device level; patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level; forming second insulating features between the plurality of second rails; removing the sacrificial layer; forming second semiconductor rails extending in the second direction between the second insulating features in a second device level over the first device level; patterning the second semiconductor rails and the second insulating features located between the second semiconductor rails to form a plurality of third rails extending in the first direction; forming third insulating features between the plurality of third rails to form second pillar-shaped non-volatile memory cells separated by insulating material of the second and third insulating features, wherein each of the second pillar-shaped nonvolatile memory cells comprises a diode and a switching material located above or below the diode; recessing the second semiconductor rails to form rail shaped openings after forming the second semiconductor rails between the second insulating features; and forming the switching material in the rail shaped openings over the second semiconductor rails.