Patent ID: 8384148

Claim:
An integrated circuit, comprising: a memory cell formed between and self-aligned with adjacent shallow-trench isolation (STI) regions on a substrate, the memory cell including a source region; a drain region; a body region disposed between the source and drain regions; a first gate insulator disposed over the body region; a floating gate disposed over and in contact with the first gate insulator, the floating gate being a single element and having a continuous portion comprising a base and a pair of side extensions, the pair of side extensions extending above the base, each side extension having an inner sidewall and an outer sidewall, the inner sidewalls of the side extensions extending towards one another as the side extensions extend away from the base, the adjacent STI regions contacting at least a portion of the outer sidewall of each of the side extensions proximate to the base of the floating gate; a second gate insulator disposed over the floating gate, directly on the single element comprising the base; and a control gate disposed over the second gate insulator.