Patent ID: 7727802

Claim:
A method of fabricating an electronic component embedded substrate including an electronic component that is embedded within a plurality of buildup layers, each buildup layer comprising an insulation layer and a wiring layer, the method comprising: a stopper layer forming step of forming a stopper layer on a core substrate at a position corresponding to a formation position of a cavity; a first buildup layer lamination step of laminating a plurality of first buildup layers on the core substrate such that a total thickness of the laminated first buildup layers corresponds to a thickness of the electronic component; a cavity formation step of forming the cavity through the laminated first buildup layers by laser processing, said cavity having a depth corresponding to the thickness of the electronic component, wherein the laser processing has a greater processing speed for the first buildup layers than a processing speed for the stopper layer; an accommodating step of accommodating the electronic component within the cavity; and a second buildup layer lamination step of laminating one or more second build up layers on the laminated first buildup layers and the electronic component.