Patent ID: 7386705

Claim:
A system for encrypting data comprising: a single multistage pipe-line encryption processor including a processor array of serial encryption processing stages configured to serially process independent blocks of data; and, a memory circuit in electrical communication with the processor array, the memory circuit including: a first data storage area and a second data storage area for storing independent blocks of data for independent serial processing in the encryption processor; a first status indicator storage location in each data storage area for storing a status indicator value for indicating that an independent block of data stored within the data storage area is ready for processing by the processor array, the status indicator value operable by a client station; and a second status indicator storage location in each data storage area for storing a status indicator value for indicating completion of processing of an independent block of data stored within the data storage area, the second status indicator value operable by the encryption processor; the memory circuit successively switching from a first mode to a second mode relative to the processor array, such that in a first mode the first data storage area is available to the encryption processor for processing a block of data and the second data storage area is available to a client station, and in the second mode the second data storage area is available to a client station and the first data storage area is available to the encryption processor for processing a block of data, wherein prior to completing the serial processing of the current data within the first data storage area, the processor array determines a status of an indicator value within the first status indicator storage location for the second data storage, such that in use upon completion of processing the current data within the first data storage area and absent communication external to the encryption processor, the processor array immediately begins a subsequent serial processing operation of a subsequent independent block of data within the second data storage area in dependence upon the first indicator value in the second data storage area.