Patent ID: 7646829

Claim:
A composite data detector comprising: a first data detector, the first data detector receiving a sequence of bits, the first data detector being configured to generate hard bit estimates as to whether each bit in the sequence corresponds to a 1 or a 0 and to generate a respective confidence factor associated with each hard bit estimate, each confidence factor indicating whether or not the respective hard bit estimate is unreliable; and a second data detector, the second data detector receiving said sequence of bits a predetermined delay period after the first data detector receives said sequence of bits, the second data detector responsive on a bit-by-bit decision basis to the hard bit estimates and the confidence factors generated by the first data detector, the second data detector being configured to process unreliable hard bit estimates in accordance with a branch metrics processing algorithm to generate new hard bit estimates, said second data detector being turned on a bit-by-bit decision basis when at least one of said confidence factors indicates that at least one respective hard bit estimate generated by the first data detector is unreliable, and wherein the second data detector is turned off on a bit-by-bit decision basis when the second data detector has generated new hard bit estimates for any unreliable bit estimates received by the second data detector.