Patent ID: 7939390

Claim:
A semiconductor structure fabrication method, comprising: providing a structure which includes a dielectric layer which includes a top surface, wherein the top surface defines a reference direction perpendicular to the top surface; forming a bottom capacitor plate and an electrically conductive line on the dielectric layer, wherein the bottom capacitor plate comprises a first electrically conductive material, and wherein the electrically conductive line comprises a second electrically conductive material; after said forming the bottom capacitor plate and the electrically conductive line is performed, forming a top capacitor plate on top of the bottom capacitor plate, wherein the top capacitor plate comprises a third electrically conductive material, and wherein the top capacitor plate overlaps the bottom capacitor plate in the reference direction; after said forming the top capacitor plate is performed, forming a gap region, wherein the gap region is sandwiched between the bottom capacitor plate and the top capacitor plate, and wherein the gap region does not comprise any liquid or solid material; and after said forming the gap region is performed, forming a solder ball on the dielectric layer, wherein the solder ball comprises a fourth electrically conductive material, wherein the solder ball is electrically connected to the electrically conductive line, and wherein the top capacitor plate is disposed between the dielectric layer and the solder ball.