Patent ID: 8304820

Claim:
A semiconductor device comprising a plurality of memory cells over a semiconductor substrate, wherein a first well of a first conductivity type is formed in the semiconductor substrate, wherein the plurality of memory cells are formed over the first well, wherein each of the memory cells comprises: a gate insulating film formed over the first well, the gate insulating film including an electric charge storage film; and a gate electrode formed over the gate insulating film, the gate electrode being formed of a first conductive film, wherein the gate electrodes of the memory cells extend in a first direction and are arranged in a second direction perpendicular to the first direction such that the plurality of memory cells are arranged in an array, wherein a pair of first dummy gate pairs extend in the first direction with the array being interposed therebetween, wherein a pair of second dummy gate pairs extend in the second direction with the array being interposed therebetween, wherein a second well of a second conductivity type opposite to the first conductivity type is formed in the semiconductor substrate, the second well being formed deeper than the first well, wherein a third well of the second conductivity type is formed in the semiconductor substrate, the third well being formed so as to be electrically coupled to the second well and to be overlapped in plan view with a first region including the pair of first dummy gate pairs formed therein, wherein an interlayer insulating film is formed over the plurality of gate electrodes, the pair of first dummy gate pairs and the pair of second dummy gate pairs, and wherein a first plug is formed in the interlayer insulating film so as to be electrically coupled to the third well.