Patent ID: 7982246

Claim:
A selection transistor formed on an active region in a semiconductor substrate, the selection transistor comprising: a gate electrode including recessed portions of a sidewall of the gate electrode recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode; and a tunnel insulating layer between the gate electrode and the active region, wherein the recessed portions of the gate electrode are each filled with a blocking insulating layer and a lower insulating layer, which are vertically stacked; wherein a side surface of the blocking insulating layer and the lower insulating layer, which faces the gate electrode, is self-aligned by the recessed portion of the gate electrode; wherein the lower insulating layer comprises an inner insulating layer formed adjacent to the recessed portion of the gate electrode, an external insulating layer formed along an external surface of the lower insulating layer, and a charge storage layer formed between the inner insulating layer and the external insulating layer.