Patent ID: 7678623

Claim:
A method of manufacturing a poly-Si TET structure, wherein the structure comprises a stacked source/drain and a thin channel, wherein the steps comprise: (1) a step of re-crystallizing a a-Si layer to form a poly-Si layer: first, deposit an a-Si layer on-top of a substrate, followed by carrying out a general exposure lithography and using etching technique to define a-Si islands with higher regions and lower regions, followed by annealing, in order to re-crystallize the a-Si layer to form a poly-Si layer ( 02 ); (2) a step of defining a gate region, source/drain region and channel region: respectively stack a gate oxide layer ( 04 ) and a poly-Si thin film, followed by carrying out general lithography and using etching to define a gate region ( 05 ), source/drain region ( 07 ) and channel region; (3) implementation step: ionic implantation technique is used to form a heavy doped gate region ( 05 ) and source/drain region ( 07 ), and ionic activation is carried out; and (4) connection step: deposit a SiO 2 protection layer and open a contact window ( 14 ), and carry out a connection of a conducting line ( 10 ).