Patent ID: 7941781

Claim:
An on-chip test circuit for testing a system-on-chip integrated circuit, the on-chip test circuit comprising: a programming control unit having an input/output port adapted to receive an operation command, the programming control unit operable in a test-input mode to apply a plurality of command signals on a first control port in response to the operation command; an execution and reporting unit coupled to the programming control unit through the first control port, the execution and reporting unit operable responsive to the command signals to apply a plurality of control signals on a second control port during the test-input mode; and an interface unit coupled to the execution and reporting unit through a second control port and having an interface port adapted to be coupled to an intellectual property (IP) core, the interface unit operable responsive to the control signals to apply interface control signals on the interface port to control the IP core during the test-input mode; wherein the operation command comprises a command packet that includes: an operation code field that defines an operation to be performed by the on-chip test circuit; a data field containing data to be supplied to the IP core during the test-input mode; an expected time field containing an expected time to completion of the operation code; and an expected data field containing expected core data corresponding to the expected values of core data to be received from the IP core.