Patent ID: 8040730

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array comprising a plurality of memory cells for storing data; and a control circuit configured to control a reading operation for reading data from the memory cell array and a programming operation for inputting data to the memory cell array, wherein the control circuit comprises: a first unit configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater then n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits which are input for a designated address; and a second unit configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.