Patent ID: 7555045

Claim:
A MPEG video decoder comprising: a picture decoding section for starting to decode a MPEG bit-stream in response to a decoding start command; a decoding frame buffer for storing picture data decoded by said picture decoding section; a display control section for analyzing parameters of the picture data for each picture, said picture data being decoded by said picture decoding section, and controlling a transfer of said picture data from said decoding frame buffer to a display unit in accordance with an analysis result of said parameters; and a decoding control section for outputting said decoding start command based on the parameters of said picture data; wherein said display control section determines the number of display fields of each of said pictures based on said parameters for each picture, and allowing said pictures to be displayed on said display unit for a predetermined period of time equivalent to said number of display fields; and said display control section includes four shift registers of a re-order register for storing a parameter of either an I picture or a P picture and a bank address thereof, a current register for storing a parameter of a picture and a bank address thereof, the picture being subsequently displayed, a field delay register for delaying the parameter and the bank address shifted from said current register by one field time, and a display register for storing a parameter of a picture and a bank address thereof, which is being displayed.