Patent ID: 6888753

Claim:
A memory cell array, comprising: a plurality of memory transistors arranged in a two-dimensional array wherein the two-dimensional array is defined by a first direction and a second direction, each memory transistor having two source/drain regions arranged in a first direction of the memory cell array with a channel substrate region therebetween, and a gate structure arranged above the channel substrate region, said source/drain regions and channel substrate regions being formed in a substrate arranged on an insulating layer, and the channel substrate regions of memory transistors adjacent each other in the first direction being separated from each other by respective source/drain regions extending down to the insulating layer, wherein said source/drain regions and channel substrate regions of memory transistors adjacent each other in a second direction of the memory cell array are isolated from each other by trenches filled with insulating material and formed in the substrate so as to extend down to the insulating layer.