Patent ID: 8667223

Claim:
A cache for use in a central processing unit (CPU) of a computer, comprising: a data array; a tag array configured to hold a list of addresses corresponding to each data entry held in the data array; a least recently used (LRU) array configured to hold data indicating least recently used data entries in the data array; a line fill buffer configured to receive data corresponding to the cache miss from an address in main memory that is located externally to the cache based on detection of the cache miss; a shadow register associated with the line fill buffer, wherein the shadow register is configured to hold LRU data indicating a current state of the LRU array; and replacement logic configured to manage the shadow register by: writing data indicating the current state of the LRU array into the shadow register based on detection of the cache miss; and updating the shadow register to reflect the current state of the LRU array based on the LRU array being updated based on a read or write operation that is performed in the cache after detection of the cache miss, wherein the updating of the shadow register is performed before the data corresponding to the cache miss in the line fill buffer is written into the data array at an entry indicated by the LRU data in the shadow register.