Patent ID: 8184473

Claim:
A memory device comprising: a substrate; first and second lower electrodes formed on the substrate, the first and second lower electrodes being separate from each other by a gap; a first nanowire extending in a first direction parallel to a top surface of the substrate and connecting the first and second lower electrodes; a first upper electrode formed over the first lower electrode to partially overlap the first lower electrode in a second direction perpendicular to the substrate; a second upper electrode formed over the second lower electrode to overlap the second lower electrode in the second direction; and a second nanowire extending in the first direction and connecting the first and second upper electrodes, wherein the first and second upper electrodes are separate from the first and second lower electrodes by a gap having the same distance as the gap between the first and second lower electrodes, and wherein an insulating layer exists between the first lower electrode and the first upper electrode, and between the second lower electrode and the second upper electrode so as to electrically insulate the first lower electrode from the first upper electrode in a first state if the first and second nanowires do not electrically contact each other, and wherein the first and second nanowires are capable of contacting each other in a second state such that the first lower and first upper electrodes are electrically connected to each other.