Patent ID: 8627241

Claim:
An integrated circuit (IC) method comprising: receiving an IC design layout having a plurality of non-overlapping IC regions, each of the IC regions including a same initial IC pattern, and wherein each of the plurality of IC regions is associated with a different IC die; performing a dissection process to the IC design layout; performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect, wherein the correction process includes: performing a first correction step to a first IC region of the plurality of IC regions, thereby modifying the initial IC pattern to result in a first corrected IC pattern in the first IC region, copying the first corrected IC pattern to a second IC region of the plurality of IC regions, thereby replacing the initial IC pattern of the second IC region with the first corrected IC pattern; and after copying, performing a second correction step to the second IC region of the plurality of IC regions, wherein the performing the second correction step includes starting with the copied first corrected IC pattern and resulting in a second corrected IC pattern; and taping-out the second corrected IC pattern to provide a taped-out pattern accessible by at least one of a mask making tool and an e-beam lithography tool.