Patent ID: 7661043

Claim:
A test apparatus for testing a memory-under-test, comprising: an address control apparatus comprising: a pattern memory for storing data patterns to be inputted to said memory-under-test; an address generating section for outputting sequential addresses of said memory-under-test into which said data patterns are written; a pointer section for pointing to sequential addresses of said pattern memory to cause said pattern memory to output said data patterns corresponding to the addresses of said memory-under-test outputted by said address generating section; a bad block memory for storing quality information for data blocks of a storage area of said memory-under-test, said data blocks corresponding to said addresses of said memory-under-test; and a pointer control section for, when a data block corresponding to the address of said memory-under-test generated by said address generating section is indicated as a bad block based on the quality information stored in said bad block memory, causing said address generating section to output a next sequential address of said memory-under-test while holding the address of said pattern memory to which said pointer section points, the holding being performed by inhibiting said pointer section from incrementing the address of said pattern memory; a pattern generating section for generating test patterns; a data selecting section for selecting either said test patterns generated by said pattern generating section or said data patterns outputted by said pattern memory to input to said memory-under-test; and a judging section for reading data written in each address of said memory-under-test to judge whether a block corresponding to the address is good or bad based on the read data, wherein said address generating section further generates random addresses of said pattern memory, said pointer section generates sequential addresses of said pattern memory, and said test apparatus further includes a pattern memory address selecting section for selecting either said random addresses generated by said address generating section or said sequential addresses generated by said pointer section to input to said pattern memory.