Patent ID: 7867819

Claim:
A method of forming a semiconductor package, comprising the steps of: (a) forming a conductance pattern on a surface of a substrate, the conductance pattern including a cluster of contact pads; (b) affixing a controller die to the surface of the substrate in a flip chip arrangement with a cluster of die bond pads on the controller die electrically coupling with the cluster of contact pads on the substrate; (c) affixing a first flash memory die directly to the surface of the substrate, the first flash memory die positioned next to the controller die; (d) affixing at least a second flash memory die on top of the controller die and first flash memory die bonded in said steps (b) and (c); (e) wirebonding the at least second flash memory die affixed in said step (d) to the substrate; (f) encapsulating the flip chip controller die, the first flash memory die and the at least second flash memory die in a molding compound and wherein said step (c) comprises the step of wire bonding the first flash memory die to the substrate.