Patent ID: 8234544

Claim:
A data access apparatus, comprising: a processor; a flash memory controller; a mirror means; a first flash memory, including at least one data region; a second flash memory, including at least one data region, wherein an accessing error probability for the first flash memory is lower than which of the second flash memory; and a third flash memory, including at least one mirror region for the second flash memory; wherein when the processor detects data transmitted from external to the data access apparatus is written to the data region of the second flash memory, the mirror means copies the data to form mirror data to the mirror region; where when the processor detects the data is written to the data region of the first flash memory, the mirror means does not copy the data to form mirror data to the mirror region; wherein the flash memory controller reads the mirror data to replace the data when the flash memory controller determines that the data include error(s) when the data is read.