Patent ID: 8515059

Claim:
A cryptographic processor comprising: an interface for receiving input data blocks and returning cryptographically processed data blocks; a memory for storing an encryption state; a pseudorandom permutation block for generating transformed data blocks, the input to the pseudorandom permutation block is at least a portion of the encryption state which is modified for each input data block by at least one of the input data block and previously transformed data block; and control logic for routing data in the cryptographic processor to return cryptographically processed data blocks at the interface and updating the memory with the next encryption state using transformed data blocks from pseudorandom permutation block; wherein the cryptographic processor is a rotor cryptographic processor and the memory for storing the encryption state comprises rotor state registers; wherein the rotor state registers are pipelined and each one of rotor state register is updated in sequential clock cycles; and wherein the interface returns a data block within 20 clock cycles from receiving an input data block.