Patent ID: 8127078

Claim:
A cache memory device comprising: an address decoder configured to decode line index bits in a memory address and select a target cache line from a plurality of cache lines; a first cache array coupled to the address decoder, the first cache array configured to output a first cache entry associated with the target cache line; a second cache array coupled to the address decoder, the second cache array configured to output a second cache entry associated with an alignment cache line; an alignment unit coupled to the address decoder, the alignment unit configured to select either the target cache line or a neighbor cache line proximate the target cache line in the second cache array as output to the alignment cache line, selection of either the target cache line or the neighbor cache line being based on an alignment bit in the memory address; and a tag selector configured to output at least one target cache tag entry associated with the target cache line and, if bits in the memory address indicate a neighbor cache line is selected by the alignment unit and the neighbor cache lines contains data addressed by byte offset bits in the data address, to output a neighbor cache tag associated with the neighbor cache line.