Patent ID: 7899957

Claim:
A memory controller, comprising: at least one bus interface, each bus interface being for connection to at least one respective device for receiving memory access requests; a memory interface, for connection to a memory device over a memory bus; a plurality of buffers in the memory interface, each of the plurality of buffers sized to store a data burst for a memory access request, each of the plurality of buffers further including a plurality of sub-buffers; and control logic, for placing received memory access requests into a queue of memory access requests, wherein, in response to a received memory access request requiring multiple data bursts over the memory bus, each of said multiple data bursts is assigned by the control logic to a respective buffer of the plurality of buffers in the memory interface, and data from each of said multiple data bursts is stored by the memory interface in the respective buffer, wherein, for a wrapping memory access request requiring multiple buffers of the plurality of buffers, data required for each of a beginning and an end of the wrapping memory access request are assigned to respective sub-buffers of a single respective buffer by the control logic, a beginning data and an end data for the wrapping memory access request being stored concurrently from a single data burst in the respective sub-buffers of the single respective buffer by the memory interface, the storing of the beginning and end data in the single respective buffer avoiding the need for an additional data burst to obtain the end data, wherein the control logic records a value of a pointer indicating a first sub-buffer of the single respective buffer storing the end data, such that the control logic is able to return to the indicated first sub-buffer to retrieve the end data from the single respective buffer, and wherein when accessing the single respective buffer comprising a first part and a second part to return data to the respective device from which a wrapping memory read request requiring multiple data bursts over the memory bus was received, the beginning data is read out from the first part of the single respective buffer, the second part of the single respective buffer is skipped to read out subsequent data from at least one other of said multiple buffers, and the multiple buffers are wrapped around to read out the end data from the second part of the single respective buffer.