Patent ID: 8884671

Claim:
A phase-locked loop system, comprising a controlled oscillator configured to provide an output clock signal (SOUT) on the basis of an oscillator control signal; a feedback path configured to provide a feedback signal (SFB) on the basis of the output clock signal (SOUT); a phase detector configured to provide a phase dependent signal on the basis of the feedback signal (SFB) and a reference clock signal (SREF); a phase evaluation block configured to provide the oscillator control signal on the basis of the phase dependent signal; a frequency detector configured to determine whether a frequency ratio between the output clock signal (SOUT) and the reference clock signal (SREF) has a desired value (N); and a control logic, which is configured, during a start-up period, to disable the phase evaluation block upon determination of the desired value (N) of the frequency ratio in order to keep the oscillator control signal basically constant; to detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal (SREF); and to enable, in response to the detection of the subsequent clock edge, the phase evaluation block in order to allow a variation of the oscillator control signal.