Patent ID: 7450424

Claim:
A method for reading a memory array, the memory array comprising a right data line, a left data line, a column of select gates having gates coupled together, a plurality of right floating gates each coupled between a corresponding select gate and the right data line, a plurality of left floating gates each coupled between a corresponding select gate and the left data line, and a plurality of word lines each coupled to a corresponding right floating gate and left floating gate, the method comprising: turning on the column of select gates; preprogramming a first right floating gate to a high threshold and a first left floating gate coupled to a same first word line as the first right floating gate to a low threshold; charging a voltage of the right data line to a first predetermined value; charging a voltage of the first word line to a second predetermined value which is between the high threshold of the first right floating gate and the low threshold of the first left floating gate; charging a voltage of a second word line coupled to a second right floating gate to a third predetermined value; and comparing a current of the left data line with a fourth predetermined value.