Patent ID: 6971038

Claim:
A processor comprising: an execution circuit configured to execute an instruction, the execution circuit including at least a first subcircuit and a second subcircuit; an issue circuit coupled to the execution circuit, wherein the issue circuit is configured to issue an instruction to the execution circuit, the issue circuit including a counter which is initialized to count a latency value of the instruction at issuance of the instruction and to generate a control signal to the execution circuit to control clock gating in the execution unit responsive to the latency value initialized in the counter; and a clocking circuitry to provide a plurality of clocks for the execution circuit, the plurality of clocks including at least a first clock clocking the first subcircuit and at least a second clock clocking the second subcircuit, the clocking circuitry coupled to receive the control signal for collectively conditionally gating the plurality of clocks, and to individually conditionally gate at least some of the plurality of clocks responsive to activity in the respective subcircuits of the execution circuit.