Patent ID: 8320191

Claim:
A memory cell arrangement, comprising: a substrate; at least one memory cell, comprising a charge storing memory cell structure and a select structure; a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well; and a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well, wherein the control circuit comprises an erase circuit that is configured to provide at least one electric potential to the memory cell such that charge carriers stored in the charge storing memory cell structure are drained via at least the first doping well, wherein the erase circuit is configured to provide the same electric potential to the first, second and third doping wells.