Patent ID: 7724043

Claim:
A common mode controller circuit ( 60 ) for maintaining a common mode voltage (Vcm) at a first node ( 52 ) and a second node ( 54 ) in a sample-and-hold circuit ( 50 ), the first node and the second node receiving a pair of AC coupled differential input signals (Vinp, Vinn), the common mode controller circuit comprising: a first resistor (R 1 ) and a second resistor (R 2 ) connected in series between the first node and the second node; a third resistor (R 3 ) and a fourth resistor (R 4 ) connected in series between the first node and the second node; and a low gain differential amplifier (A 1 ) having an inverting input terminal coupled to a third node ( 62 ) between the first resistor and the second resistor, a non-inverting input terminal coupled to a reference voltage (Vref) and an output terminal coupled to a fourth node ( 64 ) between the third resistor and the fourth resistor, the low gain differential amplifier (A 1 ) providing an output current being a sourcing current at the output terminal, wherein the common mode voltage (Vcm) is sampled at the third node ( 62 ) and the low gain differential amplifier (A 1 ) provides an output current indicative of the difference between the sampled common mode voltage and the reference voltage to drive the fourth node ( 64 ), thereby maintaining the common mode voltage at a predetermined value; wherein the low gain differential amplifier comprises: an input differential pair of first and second transistors (M 1 , M 2 ) receiving the sampled common mode voltage and the reference voltage as input signals, a drain terminal ( 108 ) of the second transistor providing a first output current; a third transistor (Mtail) providing a tail current to the input differential pair; a fourth transistor (M 3 ) being diode-connected and coupled to the first transistor to provide loading; a fifth transistor (M 4 ) being diode connected and coupled to the second transistor to provide load; and a sixth transistor (M 5 ) configured as a current mirror of the fifth transistor, the sixth transistor providing a second output current being the output current of the low gain differential amplifier, the second output current being a sourcing current; and wherein the first node and the second node comprise the differential input nodes ( 52 , 54 ) of an analog-to-digital converter (ADC) ( 5 ) including the sample-and-hold circuit ( 50 ) as an input stage where the sample-and-hold circuit receives a pair of differential input signals through AC coupling; and the first node is connected to a first input capacitor (C 3 ) of the sample-and-hold circuit through a first switch (S 1 ) and the second node is switchably connected to a second input capacitor (C 4 ) of the sample-and-hold circuit through a second switch (S 2 ), the first and second switches being controlled by a clock signal.