Patent ID: 7248085

Claim:
An internal reset signal generator for use in a semiconductor memory device, said internal reset signal generator is configured to be supplied with a power source voltage, when applied said power source voltage reaching a stable state after a period of time, said internal reset signal generator comprising: a first circuit adapted to divide a power source voltage and to amplify said power source voltage when said power source voltage is first supplied, said first circuit is configured to output a first control signal until said power source voltage reaches said stable state, and is configured to output a second control signal when said power source voltage reaches said stable state; a delay circuit adapted to generate an internal reset signal and an internal reset disable signal, a reset circuit adapted to generate a reset completion signal, said delay circuit and said reset circuit being connected in a feedback loop, said delay circuit is configured to be responsive to said first and second control signals outputted from said first circuit and to said reset completing signal from said reset circuit, said delay circuit is configured to generate said internal reset disable signal only when the second control signal and a reset completion signal from said reset circuit are inputted simultaneously, and in other cases, is configured to generate said internal reset signal; said reset circuit including a resettable high voltage device having a high threshold voltage, said reset circuit is configured to reset said high-voltage device in response to said internal reset signal generated by said delay circuit and is configured to generate a reset completion signal only when said high voltage device is reset.