Patent ID: 7721173

Claim:
A broadcaster having broadcast scan inputs that accepts virtual scan patterns via its said broadcast scan inputs for generating broadcast scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said broadcaster comprising: (a) an XOR network directly connected to said broadcast scan inputs, said XOR network comprising a plurality of broadcast scan outputs and logic gates, said logic gates comprising one or more XOR gates, XNOR gates, buffers, or inverters, or any combination of said logic gates, wherein said plurality of logic gates are connected between said broadcast scan inputs and said XOR network outputs to form a means for mapping said virtual scan patterns onto broadcast scan patterns at said XOR network outputs solely by using said combinational logic; (b) a first scan connector connected to said XOR network outputs for connecting the outputs of said XOR network and selected scan cell outputs in all said scan chains to selected scan inputs of all said scan chains, wherein said first scan connector further comprises one or more second logic gates, selected from AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, lock-up latches, or any combination of the above.