Patent ID: 8427892

Claim:
A device comprising: a memory to store data; and a memory controller connected to the memory via a plurality of data lines and a strobe line, the memory controller using the plurality of data lines to write a data burst as a plurality of data signals, the memory controller using the strobe line to transmit a strobe signal, the strobe signal being used to control writing of the data signals to the memory, and the memory controller including: a plurality of write data generation circuits that each transmit one of the plurality of data signals on one of the plurality of data lines, the plurality of write data generation circuits being controlled by write enable signals, and a write strobe generation circuit to generate the strobe signal and the write enable signals, the write strobe generation circuit including: a first flip-flop and a second flip-flop, a logic OR gate connected to receive an output of the first flip-flop and an output of the second flip-flop, a third flip-flop connected to receive an output of the logic OR gate, a first logic NAND gate connected to receive the output of the logic OR gate and a clock signal, a second logic NAND gate connected to receive the output of the first flip-flop and an inverted output of the second flip-flop, a fourth flip-flop connected to receive an output of the second logic NAND gate, and a third logic NAND gate connected to receive an output of the first logic NAND gate and an output of the fourth flip-flop, logic to generate a first signal that defines portions of the strobe signal, the logic to generate the first signal including: a first pair of serially connected flip-flops that receive the output of the third flip-flop, the first pair of serially connected flip-flops being clocked by a clock that has a frequency that is twice a write frequency for the memory, and a delay chain to: receive an output of the first pair of serially connected flip-flops, and output the first signal based on the received output of the first pair of serially connected flip-flops, a buffer to receive the first signal, and logic to generate, based on an output of the third logic NAND gate, a second signal that is an input to the buffer.