Patent ID: 7096414

Claim:
A method for in-line error detection and correction using wires 0 to k−1, and symbols 0 to n, said method comprising steps of: calculating a horizontal parity (HP[i]) for i=0 to n−2, where n is a number of symbols used, and HP ⁡ [ i ] = ⊕ k - 1 x = 0 ⁢ b ⁡ [ x ] ⁡ [ i ] , and k is a number of wires used; calculating an extended parity ( EP ) = ∑ x = 0 k - 1 ⁢ ⁢ ∑ y = 0 n - 1 ⁢ ⁢ b ⁡ [ x ] ⁡ [ y ] ⁢ α ( x + y + B ) , where B a degree of primitive polynomial+1 and a number of bits in a syndrome; sending contents of the horizontal parity along wire 0 of k wires, where HP[0] is in symbol 0 , HP[1] is in symbol 1 , . . . , HP[n−2] is in symbol n−2; calculating an overall parity (OP) where the OP is an exclusive-or of the horizontal and extended parities; sending check bits along the wires in symbol 0 , wherein the check bits comprise the extended parity, the horizontal parity and the overall parity; sending information bits in symbols 1 . . . n−1, wherein symbol[i] carries bits b[k−1 . . . 0][i]; determining whether check bits have an error; calculating a syndrome 0 and a syndrome 1 , wherein syndrome 0 is a B-bit quantity {eB−1, . . . , e2, e1, e0} such that e ⁡ [ i ] = ⊕ k x = 0 ⁢ b ⁡ [ x ] ⁡ [ i + 1 ] ⊕ HP ⁡ [ i ] , where HP[i]=b[i+1][0 . . . 7], and wherein syndrome 1 is a summation of the extended parity and seven degree polynomial; determining whether bit i in wire j contains an error; and if bit i in wire j contains an error, then fixing the bit error by flipping the erroneous bit.