Patent ID: 8536924

Claim:
An integrated circuit comprising: a network, the network including: an anti-parallel diode pair coupled between first and second nodes, the anti-parallel diode pair including: a P+/N WELL junction configured to form a first diode of the anti-parallel diode pair; and an N+/P WELL junction configured to form a second diode of the anti-parallel diode pair; wherein the first and second diodes include a common substrate; wherein a P+ portion of the P+/N WELL junction of the first diode and an N+ portion of the N+/P WELL junction of the second diode are directly coupled to the first node: and wherein a P WELL portion of the of the N+/P WELL junction of the second diode and an N WELL portion of the P+/N WELL junction of the first diode are directly coupled to the second node.