Patent ID: 8058916

Claim:
A circuit for synchronizing a first processor and a second processor, comprising: a first phase comparator having a first input coupled to an output of the first processor and a second input coupled to an output of the second processor; a first phase-locked loop circuit having an input coupled to a clock source generator, an output coupled to a clock input of the first processor, and a control input coupled to an output of the phase comparator; and wherein the first phase comparator is configured to selectably operate in one of a first mode or a second mode; wherein, while operating in the first mode, the first phase comparator: determines a first phase difference between synchronization waveforms output from the first and second processors; outputs a signal indicative of the first phase difference to the control input of the first phase-locked loop circuit; and in response to the first phase difference being less than a selected value: outputs a signal to the first and second processors indicating the first and second processors are synchronized; and enters the second mode; and wherein, while operating in the second mode, the phase comparator: determines a second phase difference between signals received by the first and second inputs; and in response to the second phase difference being less than a selected value, outputs a signal to the first and second processors indicating the first and second processors are synchronized.