Patent ID: 8526551

Claim:
An integrated circuit, comprising: an input node configured to receive an analog signal; an equalizer, coupled to the input node, wherein the equalizer is configured to equalize the analog signal and to output an equalized analog signal; and an oscilloscope circuit that includes: the phase rotator coupled to a first comparator and a second comparator, wherein the phase rotator is configured to output an oscilloscope clock signal based on a clock signal, wherein the phase rotator is capable of varying the phase of the oscilloscope clock signal with respect to the phase of the clock signal; an offset circuit, coupled to the first comparator and the second comparator, wherein the offset circuit is configured to output a voltage offset; the first comparator, coupled to the input node, the offset circuit, and the phase rotator, wherein the first comparator is configured to output first digital values corresponding to the analog signal based on the voltage offset and the oscilloscope clock signal; the second comparator, coupled to the equalizer, the offset circuit, and the phase rotator, wherein the second comparator is configured to output second digital values corresponding to the equalized analog signal based on the voltage offset and the oscilloscope clock signal; a first counter, coupled to a given comparator, configured to sum given digital values, wherein the given comparator can be one of the first comparator and the second comparator, and wherein the given digital values can be one of the first digital values and the second digital values; and a second counter, coupled to the phase rotator, configured to count a number of cycles of the clock signal while the first counter is summing the given digital values.