Patent ID: 7982268

Claim:
A dual-gate transistor, comprising: a substrate; a first gate formed on the substrate; a first dielectric layer covering the first gate and the substrate; a semiconductor layer formed on the first dielectric layer over the first gate, and two opposite sides of the semiconductor layer having at least one first doping region; a second dielectric layer formed on the semiconductor layer and the substrate; a second gate formed on the second dielectric layer over the semiconductor layer; a third dielectric layer covering the second gate and the substrate; and first and second electrodes formed on the third dielectric layer and electrically connected to the first doping regions of the semiconductor layer, respectively, wherein, the first and second electrodes are separated by an interval therebetween and both of the first and second gates have two opposite end sections, the respective one end sections of the first gate and the second gate at the same side both are overlapped with the first doping region and the respective another end sections of the first gate and the second gate at the same side both are non-overlapped with the first doping region.