Patent ID: 8482057

Claim:
A three dimensional array of non-volatile memory storage cells, comprising: a substrate; and a plurality of memory layers overlying the substrate, each of the memory layers comprising: at least one bit line formed from a uniformly doped silicon region having a plurality of spaced apart memory cell regions formed within it, each memory cell region comprising a source region, a drain region and a channel region between the source and drain regions; a select device region comprising a source region, a drain region and a channel region between the source and drain regions, the source, drain and channel regions being formed of the uniformly doped silicon region of the at least one bit line; a ground device region comprising a source region, a drain region and a channel region between the source and drain regions, the source, drain and channel regions being formed of the uniformly doped silicon region of the at least one bit line; charge trapping storage dielectrics formed over each of the memory cell regions, the select device region and the ground device region, and overlying the channel region of the respective memory device region, select device region and the ground device region; conductive gate electrodes formed overlying the charge trapping storage dielectric for each of the memory cell regions, the select device region and the ground device region; and a dielectric layer overlying the gate electrodes and separating the respective memory layers in a vertical direction.