Patent ID: 7295466

Claim:
A memory array comprising: a) a plurality of memory cells; b) a plurality of array bitlines, each of the plurality of memory cells coupled to a unique one of the plurality of array bitlines, each odd bitline coupled to a unique recovery transistor which is configured to be coupled to a first voltage and a second voltage, each even bitline coupled to a unique recovery transistor which is configured to be coupled to the first voltage and a third voltage, each of the recovery transistors configured to be coupled to an unselected bitline configured to be active during a write operation and a recovery operation, each of the recovery transistors configured to be coupled to a selected bitline configured to be active during the recovery operation, and each of the recovery transistors configured such that each unselected bitline is configured to be coupled to the first voltage during a write operation, the first voltage sufficient to prevent parasitic coupling between the selected bitlines and unselected bitlines during the write operation.