Patent ID: 7428674

Claim:
A circuit for monitoring a state vector for a test access port (TAP), comprising: a TAP controller including the state vector and coupled to the test access port, the test access port providing a test clock (TCK) signal, a test mode select (TMS) signal, a test data input (TDI) signal, and a test data output (TDO) signal, wherein the TAP controller is adapted to update the state vector from a first value to a second value responsive to a transition of the TCK signal, the second value being a function of the first value and a value of the TMS signal; a storage circuit coupled to the state vector of the TAP controller, the storage circuit adapted to store a value of the state vector responsive to a transition of the TCK signal while a write enable is enabled; and a sampling circuit coupled to the test access port and the storage circuit, the sampling circuit adapted to generate the write enable responsive to at least one of the TCK signal, the TMS signal, the TDI signal, and the TDO signal, wherein the sampling circuit is further adapted to generate the write enable during a sample interval responsive to a trigger that is a plurality of transitions of the TDI signal of the test access port during an interval in which the TMS signal and the TCK signal of the test access port have no transitions.