Patent ID: 8492658

Claim:
An apparatus, comprising: a multi-layer printed circuit board having at least three conductor layers and a dielectric material layer between each of the conductor layers; a laminate capacitor stack arranged transversely through the printed circuit board, where the laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.