Patent ID: 7872941

Claim:
A nonvolatile memory device, comprising: a page buffer unit comprising first to N th page buffer blocks, wherein each of the first to N th page buffer blocks comprises m page buffers, divided into first to k th page buffer groups, and first to k th pass/fail check units configured to output respective verification signals, each indicative of a program pass or a program fail, according to data stored in latches of the page buffers included in each of the page buffer groups, wherein N and k are natural numbers; first to k th logic combination units each configured to perform a logical AND operation on verification signals respectively output from i th pass/fail check units (where i=1 to k) included in the first to N th page buffer blocks and to output respective first to k th pass/fail determination signals; and a control unit configured to check a page buffer group in which a program fail has occurred based on the first to k th pass/fail determination signals and to check failed-state bits by scanning page buffers included in the page buffer group in which the program fail has occurred.