Patent ID: 6953709

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: providing a semiconductor chip including a main surface, a plurality of semiconductor elements formed over the main surface, and a plurality of electrodes; providing a wiring substrate including a flexible filmy insulating base layer provided with a main surface and a back surface, a plurality of wiring lines formed over the main surface of the insulating base layer, and through holes formed in the insulating base layer; forming gold salient electrodes respectively over the electrodes of the semiconductor chip; disposing the wiring substrate over the main surface of the semiconductor chip through an adhesive interposed between the back surface of the insulating base layer and the main surface of the semiconductor chip; thereafter, applying pressure to the wiring substrate to bring the gold salient electrodes and the wiring lines into mutual contact in the interiors of the through holes, and applying heat to the adhesive to let the adhesive cure; and forming a plurality of solder salient electrodes over the main surface of the wiring substrate in such a manner that the solder salient electrodes are connected to the plural wiring lines, wherein the plural solder salient electrodes are arranged in a lattice shape of plural rows and columns at a pitch larger than a minimum pitch of the electrodes of the semiconductor chip, and wherein the solder salient electrodes are arranged over the main surface of the semiconductor chip through the adhesive and the insulating base layer.