Patent ID: 7078947

Claim:
A phase-looked loop having spread spectrum clock, comprising a phase-locked loop and a spread spectrum clock generator; wherein input signal to said phase-locked loop is from a reference clock source and output signal of said phase-locked loop is used as output standard clock signal of said phase-locked loop on the one hand and is supplied to said spread spectrum clock generator on the other hand; said spread spectrum clock generator comprising: a clock frequency divider to generate, based on output of said phase-locked loop at least two of a divided-by-M frequency, a divided-by-M+1 frequency and a divided-by-M−1 frequency; to a multiplexer to accept said at least two frequency signals of said clock frequency divider and to output one of said at least two frequency signals to said phase-locked loop; and a counter to accept said frequency signal of said multiplexer and to generate phase selection step according to count number of said counter to select said at least one frequency signal as output of said multiplexer.