Patent ID: 7732889

Claim:
A semiconductor device comprising: an integrated circuit formed on a substrate and comprising a signal interface with at least one isolator capacitor, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics with selected thickness of the thick passivation layer being greater than thickness sufficient for isolation so that testing for defects is eliminated; and a thick metal layer formed on the thick passivation layer, the at least one isolator capacitor formed comprising the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator; the integrated circuit divided into first and second dies; an isolation barrier between the first and second dies; a plurality of capacitors respectively formed on separate dies; a converter in the first die configured to track process characteristics across the isolation barrier and modify amplitude of a fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier; and a differentiator in the second die configured to differentiate the fast differential edge modulation on a receiving side of the isolation barrier whereby differentiation bandwidth tracks slope rate of the differential edge modulation.