Patent ID: 6925017

Claim:
A semiconductor device comprising: a plurality of word lines; a plurality of data line pairs; a plurality of memory cells provided at the intersections between the plurality of word lines and the plurality of data line pairs; the plurality of data line pairs including a first data line pair connected to a first data input/output line pair by a first select line and a second data line pair connected to the first data input/output line pair by a second select line; a first sense amplifier connected to the first data line pair; a second sense amplifier connected to the second data line pair; a first switch comprising a first MISFET (metal insulator semiconductor field effect transistor) that is controlled by a first control line, and that is connected to a first node of the first sense amplifier to supply a first power source to the first sense amplifier; and a second switch comprising a second MISFET that is controlled by the first control line, and that is connected to a second node of the second sense amplifier to supply the first power source to the second sense amplifier, wherein the first node and the second node are electrically isolated from each other, and at the time of writing data from the first data input/output line pair to the first data line pair, the first select line is enabled earlier than the first control line.