Patent ID: 7489535

Claim:
A one-time programmable memory comprising: a trim element comprising a forward-biased trim diode connected between a voltage supply Vcc and a ground voltage; a SCR drive circuit connected in series to said trim element wherein said SCR drive circuit provides a trimming current to trim said trim element; a P-type semiconductor substrate for supporting and integrating said forward biased trim diode and a SCR-MOS transistor functioning as said SCR drive circuit as an integrated circuit (IC) manufactured thereon; said SCR-MOS transistor is further disposed on said P type semiconductor substrate for supporting a low voltage P-well (LVPW) encompassing a N-source and a N-drain of a lateral MOS transistor and a low voltage N-well (LVNW) disposed next to said LVPW to encompass part of said N-drain and a N+ region and a P+ region therein thus constituting a PNPN SCR device integrated with said lateral MOS device; and said N+ region and P+ region encompassed within said LVNW forming a forward biased diode.