Patent ID: 8365120

Claim:
A method, in a data processing system, for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs, the method comprising: receiving, by a processor, a request to either generate a new IC design or fix an existing IC design; responsive to the request being to generate the new IC design, for each net in a plurality of nets in the new IC design, determining, by the processor, whether the net is mutable through a cell in a plurality of cells between a starting location and a destination location associated with the net using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold; responsive to a net being able to be routed through the cell with the coupling capacitance associated with the net being equal to or below the predetermined coupling capacitance threshold, assigning, by the processor, the net to at least one track within the cell; repeating, by the processor, the processes of determining and assigning for each cell in the plurality of cells between the starting location and the destination location associated with the net using a cost function associated with said each cell; and responsive to all nets in the plurality of nets in the new IC design being routed, generating, by the processor, the new IC design with a complete routing of all of the plurality of nets.