Patent ID: 7804732

Claim:
A memory circuit having a plurality of memory cells for storing data, said memory circuit comprising: at least two virtual supply lines each shared by a respective group of said memory cells; at least two switches configured to selectively switch a supply signal to a respective one of said at least two virtual supply lines; at least two control circuits configured to receive (i) a global activity control signal used for setting said memory circuit either into a standby or into an active state and (ii) a local data retention indication signal, the at least two control circuits further configured to control the switching state of an allocated one of said at least two switches based on said global activity control signal and said local data retention indication signal; and at least two additional switches configured to selectively switch a second supply signal to said respective one of said at least two virtual supply lines, wherein the switching state of an allocated one of said at least two additional switches is controlled based on an additional local or global control signal.