Patent ID: 7734001

Claim:
A fractional frequency divider circuit comprising: an integer frequency divider circuit; and a logic circuit, wherein said integer frequency divider circuit comprises multiple master-slave flip-flops connected in series and each of the master flip-flops in the multiple master-slave flip-flops receives a first clock signal and each of the slave flip-flops in the multiple master slave flip-flops receives a clock signal which is 180 degrees out of phase with the first clock signal, said integer frequency divider circuit frequency-divides the first clock signal with a frequency-division ratio of 1/N where N is an integer, and said logic circuit receives a plurality of signals output from master stages and slave stages of said multiple master-slave flip-flops, and said logic circuit comprising a first data latch which receives a clock signal which is 90 degrees out of phase with the first clock signal and a second data latch which receives a clock signal which is 270 degrees out of phase with the first clock signal, and outputs a signal with a duty ratio of 50% obtained by frequency-dividing said first clock signal with a frequency-division ratio of 2/N.