Patent ID: 8895434

Claim:
A method of fabricating a replacement metal gate structure for a CMOS device on a semiconductor substrate comprising: forming a dummy gate structure on an nFET portion of the CMOS device and on a pFET portion of the CMOS device, each of the dummy gate structures comprising a layer of oxide, a layer of polysilicon or amorphous silicon and a nitride hard mask; forming spacers on the dummy gate structures; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess bounded by the spacers on the nFET portion and a recess bounded by the spacers on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET portion and pFET portion; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET portion and pFET portion; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET portion and pFET portion directly on and in direct physical contact with the layer of tantalum nitride in the nFET portion and directly on and in direct physical contact with the second titanium nitride in the pFET portion; depositing titanium aluminum onto the third layer of titanium nitride in the recesses on the nFET portion and pFET portion; and filling the remainder of the cavity on the nFET portion and pFET portion with a metal different from titanium aluminum.