Patent ID: 7427877

Claim:
A level shift circuit, comprising: a circuit input and a circuit output; a first circuit portion, comprising a CMOS inverter, connected to a first high potential power source and a first low potential power source and configured to produce, in response to an input signal being received at the circuit input, a first output voltage having an H level that is equal to or close to a respective voltage supplied by the first high potential power source and having an L level that is equal to or close to a respective voltage level supplied by the first low potential power source; a second circuit portion connected to receive the first output voltage from the first circuit portion, the second circuit portion comprising a first single channel MOS inverter and being connected to a second high potential power source supplying a respective voltage that is higher than the respective voltages supplied by the first high potential power source and the first low potential power source, the second circuit portion producing, in response to receiving the first output voltage, a second output voltage having an H level that is equal to or close to the respective voltage level supplied by the second high potential power source and having an L level that is equal to or close to the respective voltage supplied by the first low potential power source; and a third circuit portion connected to receive the second output voltage from the second circuit portion, the third circuit portion comprising a second single channel MOS inverter and being connected to the second high potential power source and to a second low potential power source, the second low potential power source supplying a respective voltage that is lower than the respective voltage supplied by the first low potential power source, the third circuit portion producing, in response to receiving the second output voltage, a third output voltage having an H level that is equal to or close to the respective voltage supplied by the second high potential power source and having an L level that is equal to or close to the respective voltage supplied by the second low potential power source, the third output voltage being delivered to the circuit output; wherein the first single channel MOS inverter comprises a respective NMOS transistor as a respective drive element; and the second single channel MOS inverter comprises a respective PMOS transistor as a respective drive element.