Patent ID: 7152154

Claim:
An apparatus in a pipelined microprocessor for invalidating a redundant entry for the same branch instruction in a set associative branch target address cache (BTAC), the apparatus comprising: a way specifier, generated in a first pipeline stage, for specifying one of a plurality of ways of the BTAC for storing a target address of a branch instruction present in a cache line specified by an instruction cache fetch address missing in the BTAC; a request, generated in a second pipeline stage, for requesting the BTAC to write a resolved target address of said branch instruction into said one of said plurality of ways specified by said way specifier in said first pipeline stage, wherein said second pipeline stage is subsequent to said first pipeline stage and said first and second pipeline stages are separated by at least three pipeline stages; a status indicator, for indicating whether at least two ways of a set of the BTAC selected by an instruction cache fetch address contain a valid branch target address for a same branch instruction; and control logic, coupled to said status indicator, for invalidating one of said at least two ways of said selected set if said status indicator indicates at least two ways of said selected set contain a valid branch target address for a same branch instruction.