Patent ID: 8026748

Claim:
A delay locked loop circuit, comprising: a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal, the phase detecting unit generates and transmits the initial phase detection signal by comparing the reference clock signal to the feedback clock signal generated when the reference clock signal is delayed by the delay line set to the minimum initial delay value, and the delay control unit is configured to select and activate any one of the two or more initial activation points of the delay line in response to the initial phase detection signal generated by comparing the reference clock signal to the feedback clock signal generated by the minimum initial delay value, wherein the two or more activation points include a first activation point and a second activation point, and the delay control unit is configured to select the first activation point when the initial phase detection signal indicates a first degree of delay and is configured to select the second activation point when the initial phase detection signal indicates a second degree of delay less than the first degree of delay.