Patent ID: 8098523

Claim:
An operating method for a memory system including a semiconductor memory device which has a plurality of memory cell transistors each of which is capable of holding M bits (M is a natural number greater than or equal to 2) of data, first and second word lines which connect gates of the memory cell transistors, and a plurality of memory blocks each of which includes the memory cell transistors and is an erase unit of the data, and each of which includes a first memory region and a second memory region, the first memory region being a memory space which is formed by the M bits in each of the memory cell transistors connected to the first word lines or the M bits in each of the memory cell transistors connected to the first word lines and j bits (j is a natural number satisfying j<M) of the M bits in each of the memory cell transistors connected to the second word lines and which is capable of holding L bits (=2 k , where k is a natural number) in a data size, and the second memory region being a memory space formed by the M bits or (M−j) bits in each of the memory cell transistors connected to the second word lines, the method comprising: receiving first data from a host apparatus; writing the first data to the first memory region of the semiconductor memory device; generating second data which is information on the memory blocks; and writing the second data to the second memory region of the semiconductor memory device.