Patent ID: 8736470

Claim:
An A/D converter comprising: M unitary A/D conversion units different in phase and equal in sampling rate, where M is an integer equal to or larger than 2, the A/D conversion units being connected in parallel; a reference A/D conversion unit connected in parallel to the M unitary A/D conversion units and having an operation clock frequency set to 1/N of an overall sampling rate of the A/D converter; and M calibration units each performing calibration at an output of a corresponding unitary A/D conversion unit, and each having a sampling-timing calibration unit adapted to correct an input-signal bandwidth of the corresponding unitary A/D conversion unit so as to be equal to an input-signal bandwidth of the reference A/D conversion unit, wherein each of the sampling-timing calibration units comprises: a subtracting unit adapted to calculate a conversion error signal which is a difference between an output of the calibration unit and an output of the reference A/D conversion unit; a time differentiation deriving portion that derives a time differentiation of an input signal to the sampling-timing calibration unit; a multiplier adapted to multiply the conversion error signal and the time differentiation; and an accumulator integrating an output of the multiplier, wherein M and N are relatively prime to each other, and wherein each of the sampling-timing calibration units performs calibration by using an output of the accumulator.