Patent ID: 7687899

Claim:
A semiconductor package comprising: a bottom substrate including: opposed top and bottom substrate surfaces; a plurality of top contacts disposed on the top substrate surface; and a plurality of bottom contacts disposed on the bottom substrate surface, each of the bottom contacts being electrically connected to at least one of the top contacts; at least one electronic component attached to the top substrate surface of the bottom substrate and electrically connected to at least one the top contacts; an interposer electrically connected to at least some of the top contacts of the bottom substrate; a top substrate including: opposed top and bottom substrate surfaces; a plurality of top contacts disposed on the top substrate surface; and a plurality of bottom contacts disposed on the bottom substrate surface, each of the top contacts being electrically connected to at least one of the bottom contacts, with at least some of the bottom contacts being electrically connected to the interposer; and a package body defining a side surface, the package body at least partially encapsulating the top and bottom substrates, the interposer and the electronic component such that at least the bottom substrate surface of the bottom substrate and the top substrate surface of the top substrate are not covered by the package body.