Patent ID: 7242209

Claim:
An integrated testing system for testing circuitry of a device under test (DUT) via an interface board having a first socket for receiving the integrated testing system and a second socket for receiving the DUT, the integrated testing system comprising: a module operatively configured to engage the first socket of the interface board and including: a) at least one measurement engine operatively configured to electrically excite the circuitry with at least one analog stimulus signal, measure at least one analog response of the circuitry to said at least one analog stimulus test signal and generate measurement data when the integrated testing system is engaged with the first socket and the DUT is engaged with the second socket; and b) a compute engine operatively configured to perform at least one computation on said measurement data, said compute engine comprising a micro-code processor operatively configured to execute one or more programs that control said at least one measurement engine and said compute engine so that the integrated testing system performs the testing.