Patent ID: 7024520

Claim:
An apparatus for use with a computer system having a plurality of processors and a shared memory accessible by the processors, the shared memory organized into a plurality of memory blocks, each processor having a cache with a plurality of lines for storing selected memory blocks, the apparatus comprising: a duplicate tag (DTAG) that holds information for a given processor, the DTAG having first and second regions, each of the first and second regions having a plurality of entries, and each entry of each region stores an address and one or more states for a cache line at the given processor, whereby for each of a plurality of cache lines at the given processor there is a matching entry in both the first and the second DTAG regions; and a controller operatively coupled to the DTAG, wherein the controller loads the address and the one or more states into the DTAG entries of the first and second regions, and for each of two or more cache lines, the address loaded into the two matching entries at the first and second regions is different.