Patent ID: 8546944

Claim:
A memory device comprising: a top metal interconnect; a bottom metal interconnect running substantially perpendicular to the top metal interconnect; a first dielectric barrier region between the top metal interconnect and the bottom metal interconnect, the first dielectric barrier region having a first thickness and having first dielectric barrier sidewalls; a second dielectric barrier region between the top metal interconnect and the first dielectric barrier region, the second dielectric barrier region having a second thickness different from the first thickness and having second dielectric barrier sidewalls; and an interlayer dielectric adjacent to first dielectric barrier sidewalls and second dielectric barrier sidewalls; wherein first dielectric barrier sidewalls and second dielectric sidewalls are substantially aligned; wherein the interlayer dielectric comprises Si and O; wherein the top metal interconnect and the bottom metal interconnect each comprises a metal chosen from the group consisting of W, Al, or Cu.