Patent ID: 8151240

Claim:
A computer implemented method to determine metal oxide semiconductor (MOS) gate functional limitations, the computer implemented method comprising: obtaining a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length; determining a current for each slice based on a slice gate length of the slice to form a length-based current for each slice, wherein the current is in a channel adjacent the slice; determining a length-based current for the MOS gate by summing the length-based current for each slice; calculating a stress profile for each slice; determining a slice carrier mobility for each slice based on the stress profile of each slice; determining a carrier mobility-based current for each slice based on each slice carrier mobility; determining a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice; and determining an effective length for the MOS gate based on the length-based current and the carrier mobility for the MOS gate.