Patent ID: 8412992

Claim:
An integrated circuit comprising: A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; B. a test access port controller having inputs connected to the TMS and TCK leads and having a ClockDR output, a ShiftDR output, and an UpdateDR output; C. instruction register circuitry having a Mode- 1 output and an ATC enable output, the instruction register circuitry including a first gate with a ClockDR input connected to the ClockDR output and a Clock- 1 output, and a second gate with a gated UpdateDR input and an Update- 1 output; D. data register circuitry having a TDI input connected to the TDI lead, a TDO output selectively coupled to the TDO lead, a Mode- 1 input connected to the Mode- 1 output, a Clock- 1 input connected to the Clock- 1 output, a Shift- 1 input, and an Update- 1 input connected to the Update- 1 output; and E. ATC gating circuitry having an ATC enable input connected to the ATC enable output, a ShiftDR input connected to the ShiftDR output, a Capture input, and a Shift- 1 output connected to the Shift- 1 input.