Patent ID: 7929572

Claim:
A code division multiplex signal transmitter comprising: an arithmetic processor for producing from a plurality N of channels of encoded data to be transmitted, where N is a natural number more than unity, pieces of output data, a number of which is equal to a number M of bit positions of a binary representation of a number of channels N, where M is a natural number; an amplifier comprising amplifying circuits, of which a number is equal to the number M, wherein a k-th amplifying circuit amplifies k-th one of the output data, where k is a natural number less than M, to output k-th amplified data having an amplitude level of 2 k−1 , and M-th one of the amplifying circuits outputs M-th amplified data having an amplitude level of 2 M−1 −A, where A is an offset-adjusting value defined by A=2 M −(N+1); and a multiplexer for multiplexing the first to M-th amplified data to develop a code division multiplex signal, said arithmetic processor adding up the encoded data to thereby produce added data, said arithmetic processor producing, when the added data is less than a first threshold value of 2 M−1 −A, the first to M-th output data representing values of respective bit positions of a binary representation of the added data, said arithmetic processor selecting, when the added data is equal to or more than the first threshold value but is equal to or less than a second threshold value of 2 M−1 −1, either of the added data and shifted data, obtained by adding the offset-adjusting value A to the added data, at an equal probability to produce the first to M-th output data representing the values of the respective bit positions of the binary representation of the added data or shifted data selected, said arithmetic processor producing, when the added data is more than the second threshold value, the first to M-th output data representing the values of the respective bit positions of the binary representation of the shifted data.