Patent ID: 8035425

Claim:
An electronic circuit comprising: an activation stage including a first activation circuit and a second activation circuit each coupled to receive an input signal on an input node; an output stage including a first output circuit and a second output circuit, wherein the first output circuit is configured to drive, when activated, an output signal on an output node, wherein the first activation circuit is configured to activate the first output circuit responsive to the input signal transitioning from a first logic level to a second logic level; an echo stage including a first echo circuit and a second echo circuit, wherein the first echo circuit is configured to drive the input node responsive to activation of the first output circuit; and a deactivation stage including a first deactivation circuit and a second deactivation circuit, wherein the first deactivation circuit is configured to deactivate the first output circuit at a first delay time subsequent to activation of the first output circuit, wherein the first echo circuit is configured to be deactivated responsive to deactivation of the first output circuit.