Patent ID: 8357570

Claim:
A method for fabricating a pixel structure, comprising: providing a substrate, wherein the substrate has a pixel area; forming a first metal layer, a gate insulator and a semiconductor layer on the substrate sequentially; patterning the first metal layer, the gate insulator and the semiconductor layer to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern, wherein the transistor pattern and the lower capacitance pattern comprise the first metal layer, the gate insulator and the semiconductor layer, respectively, and the lower circuit pattern comprises the first metal layer; forming a dielectric layer and an electrode layer sequentially on the substrate, wherein the dielectric layer and the electrode layer cover the transistor pattern, the lower capacitance pattern and the lower circuit pattern; patterning the dielectric layer and the electrode layer to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern; forming a second metal layer on the electrode layer and electrically connecting the second metal layer to the lower circuit pattern, the lower capacitance pattern and the source/drain region of the transistor pattern; and patterning the second metal layer and the electrode layer to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern, wherein a portion of the electrode layer exposed by the second metal layer in the pixel area is used as a pixel electrode, and the patterned second metal layer outside the pixel area further exposes a portion of the electrode layer used as a bonding pad, the bonding pad electrically connecting the upper circuit pattern.