Patent ID: 7473633

Claim:
A method of making an integrated circuit chip, comprising the steps of: providing a first chip layer having a plurality of electrical contacts for coupling to electrical conductors in a second chip layer; forming a dielectric layer over said first chip layer, said dielectric layer having a plurality of cavities corresponding to respective electrical contacts of said plurality of electrical contacts in said first chip layer; growing a plurality of carbon nanotubes in each of said plurality of cavities, said step of growing a plurality of carbon nanotubes leaving voids within each said cavity between said carbon nanotubes; filling substantially all of the volume of said voids throughout the length of each said cavity with a conductive metal to form a respective electrically conductive via in each said cavity, each said electrically conductive via forming a respective portion of a respective electrical logic circuit path to one or more of a plurality of active devices of said integrated circuit chip; and forming said second chip layer over said dielectric layer.