Patent ID: 8234450

Claim:
A method for caching data in a microprocessor configured to access an external memory, the microprocessor having a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory, the method comprising: generating, by the second-level cache, a first request to the BIU to fetch a cache line from the external memory, wherein the BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache; detecting, by the second-level cache, the generation of second and third requests to the same cache line while the first request is still outstanding, wherein the second request is a snoop request generated by the BIU and the third request is generated by the first-level cache; determining, by the second-level cache, whether a possibility still exists that a transaction on the bus to fulfill the first request will be retried; generating a miss response, if a possibility still exists that the transaction will be retried; and generating a hit response, if no possibility still exists that the transaction will be retried.