Patent ID: 8350249

Claim:
A semiconductor device, comprising: a plurality of first conductivity type semiconductor nanowire cores located over a support; a continuous second conductivity type semiconductor layer extending over and around the cores; a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores; a first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids; and at least one quantum well shell located around the cores and surrounded by a first portion of the second conductivity type semiconductor layer which completely fills interstitial spaces between the cores and by a second portion of the second conductivity type semiconductor layer which does not completely fill the interstitial spaces to leave the interstitial voids in the interstitial spaces; wherein the cores are positioned such that a non-tessellated configuration is provided as the second conductivity type semiconductor layer extends around the cores to form the interstitial voids.