Patent ID: 8841171

Claim:
A method of making a thermally enhanced stackable semiconductor assembly, comprising: providing a bump, a flange, an adhesive and a conductive layer with an aperture, wherein the bump defines a cavity that faces in a first vertical direction, covers the cavity in a second vertical direction opposite the first vertical direction, is adjacent to and integral with the flange and extends from the flange in the second vertical direction, and the flange extends laterally from the bump in lateral directions orthogonal to the vertical directions; then attaching the flange and the bump to the conductive layer via the adhesive between the flange and the conductive layer and between the bump and the conductive layer, including aligning the bump with the aperture; then mounting a semiconductor device that includes a contact pad on the bump at the cavity; providing a first build-up circuitry on the semiconductor device and the flange that extends from the semiconductor device and the flange in the first vertical direction and is electrically connected to the semiconductor device; providing a second build-up circuitry that extends beyond the bump, the adhesive and the conductive layer in the second vertical direction; and providing a plated through-hole that extends through the adhesive in the vertical directions to provide an electrical connection between the first build-up circuitry and the second build-up circuitry.