Patent ID: 8473724

Claim:
A method for use in a processor, the method comprising: supplying information derived from a plurality of instructions of an instruction stream to at least some of one or more execution units; executing, in a first execution mode, the plurality of instructions by the at least some of the one or more execution units; executing a user-defined instruction sequence (UDIS) embedded within the instruction stream, wherein the instruction stream comprises a reference to a machine state register comprising the instruction sequence definition, wherein the machine state register specifies at least a second execution mode of the user-defined instruction stream and a constraint on the statistical behavior of the processor when executing the user-defined instruction stream, wherein the statistical behavior is at least one selected from a group consisting of a number of instructions and a number of a particular type of instruction, wherein the UDIS executes in the second execution mode specified by the instruction sequence definition, wherein the second execution mode disables an interrupt handler, and wherein the UDIS comprises some of the plurality of instructions; recognizing, while executing the UDIS in the second execution mode, an asynchronous event; completing the UDIS; and returning, in response to completing the UDIS, to the plurality of instructions executing in the first execution mode, wherein the interrupt handler is enabled in the first execution mode.