Patent ID: 8241926

Claim:
A method of testing the electrical characteristics of a plurality of semiconductor integrated circuits formed on a wafer, the method being carried out as part of a packaging process, the method comprising: forming a plurality of conductive posts on the wafer, the conductive posts making electrical contact with interconnection wiring of the integrated circuits; forming a sealing layer on the wafer, the sealing layer covering the interconnection wiring and exposing ends of the conductive posts; mounting a first probe card in a testing machine, the first probe card having probe pins disposed in first positions to make electrical contact with the ends of at least some of the conductive posts; using the first probe card to measure a first set of electrical characteristics of each of the semiconductor integrated circuits; After measuring the first set of electrical characteristics, forming terminals on the ends of the conductive posts; mounting a second probe card in a testing machine, the second probe card having probe pins disposed in second positions, differing at least in part from the first positions, to make electrical contact with at least some of the terminals formed on the conductive posts; and using the second probe card to measure a second set of electrical characteristics of at least some of the semiconductor integrated circuits.