Patent ID: 7999875

Claim:
A solid-state imaging device comprising: a plurality of pixel units that are arranged in a matrix; column signal lines that are each provided for a different one of columns of the matrix to carry a pixel signal from a pixel unit which belongs to a corresponding column; and column amplifier units that are each provided for a different one of said column signal lines, wherein each of said column amplifier units includes: a constant current circuit that supplies a constant current; an amplifier circuit that is connected in series with said constant current circuit, and amplifies a pixel signal from a corresponding column signal line and outputs the amplified signal from a point of connection with said constant current circuit; and a resistor circuit that is connected in parallel with said amplifier circuit and has a constant resistance, wherein said constant current circuit includes at least one transistor as a constant current supply, wherein said amplifier circuit includes an amplifier transistor having a gate to which the pixel signal is input, and a source and a drain from one of which the amplified signal is output, and wherein said resistor circuit includes a resistor transistor having a gate to which a bias voltage corresponding to a linear region is applied, wherein said at least one transistor in said constant current circuit comprises two cascode-connected pMOS transistors, wherein the solid-state imaging device further comprises a bias circuit that controls an amount of constant current flowing in each of said column amplifier units, wherein said bias circuit includes: a first load nMOS transistor having a drain connected to a constant current source, a gate short-circuited with the drain, and a source connected to a ground; a first circuit that forms a current mirror with said first load nMOS transistor; and a second circuit that forms a current mirror with said first load nMOS transistor, said first circuit supplies a first bias voltage to a gate of one of said two cascode-connected pMOS transistors, said second circuit supplies a second bias voltage to a gate of an other one of said two cascode-connected pMOS transistors, and a ratio between a length and a width of a region of said amplifier transistor, which is a MOS transistor, is equal to a ratio between a length and a width of a region of said first load nMOS transistor, on a semiconductor substrate on which said solid-state imaging device is provided.