Patent ID: 6913957

Claim:
A method of fabricating a thin film transistor array substrate, comprising: forming a plurality of gates and a plurality of scan lines electrically connected to the gates on a substrate; forming a gate insulating layer covering the gates and the scan lines; forming a channel layer and an ohmic contact layer on the gate insulating layer above the gates; forming a transparent conductive layer over the substrate; forming a metal layer on the transparent conductive layer; patterning the metal layer and the transparent conductive layer to form a plurality of source/drain regions, a plurality of data lines and a plurality of pixel regions; forming a passivation layer over the substrate exposing the metal layers on the pixel regions; and removing the metal layer exposed by the passivation layer to expose the transparent conductive layer on the pixel regions, using the passivation layer as a mask, wherein the transparent conductive layer on the pixel regions serves as a plurality of pixel electrodes.