Patent ID: 7465641

Claim:
A method for manufacturing a semiconductor device, comprising: forming an insulation film pattern on a semiconductor layer having a first region and a second region; forming a first semiconductor film on the semiconductor layer; forming a second semiconductor film having an etching rate smaller than an etching rate of the first semiconductor film; removing the insulation film pattern that has been formed on the semiconductor layer; forming a first exposing region by referring to the second semiconductor film as an alignment mark, the first exposing region being formed by etching the second semiconductor film and the first semiconductor film; forming a supporter on the second semiconductor film having an etching rate smaller than an etching rate of the first semiconductor film, the supporter being formed such that the supporter supports the second semiconductor film in the second region; forming a second exposing region that exposes a side of the first semiconductor film, the second exposing a region being formed by referring to the alignment mark; forming a cavity by removing the first semiconductor film through the second exposing region; forming a buried oxide in the cavity; forming a first gate insulation film on the second semiconductor film; forming a first gate electrode on the gate insulation film, the first gate electrode being formed by referring to the alignment mark; and forming a first source region and a drain region in the second semiconductor film.