Patent ID: 8537689

Claim:
A method for minimizing undetectable errors in a set of packets received in a receiver of a communication system of an application, wherein each packet includes a payload and a cyclical redundancy check, comprising the steps of: receiving a set of packets; verifying the CRC in each packet; setting a CRC flag to 0 to indicate success and passing the payload of each packet and the CRC flag to the application if each CRC is verified; setting the CRC flag to 1 to indicate failure of the verifying passing only the CRC flag to the application if all the packets fails the verifying, and if at least one packet in the set of packets fails the verifying further comprising the steps of: generating an error pattern E for each packet that fails the CRC verification by comparing each packet that fails the CRC verification with one packet that passed the CRC verification; comparing the error pattern to a set of known error patterns, where the subscript index is in the range [0, K], and T 0 is an all zero pattern, and the other K patterns include all valid codewords with weights less than a predetermined value; setting a CRC flag to 0 to indicate success and passing the payload of each packet and the CRC flag to the application if the difference is less than a predetermined threshold, and otherwise, setting the CRC flag to 1 to indicate failure of the verifying passing only the CRC flag to the and application, wherein the steps are performed in the receiver.