Patent ID: 7656229

Claim:
An electronic device for reducing intermodulation distortion, comprising: an amplifier circuit having an input and an output, the amplifier circuit having a first transistor, the amplifier circuit configured to receive a first input signal comprising at least a first frequency and a second frequency, the amplifier circuit configured to generate a first output signal, the first output signal comprising a delta frequency signal at a delta frequency, the delta frequency comprising a difference between the first frequency and the second frequency; and a linearizer having an input and an output, the input of the linearizer coupled to the amplifier circuit, the output of the linearizer coupled to the input of the amplifier circuit, the linearizer comprising: a signal detector circuit coupled to the amplifier circuit, the signal detector circuit having an input and an output, the signal detector circuit having a second transistor, the signal detector circuit configured to generate a second output signal, the second output signal comprising at least the delta frequency; a current-mirror circuit coupled to the signal detector circuit, the current-mirror circuit configured to adjust an amplitude of an input signal of the current-mirror circuit; a low pass filter coupled to the current-mirror circuit, the low pass filter configured to eliminate a portion of the second output signal having a frequency or frequencies that are greater than the delta frequency; a phase shifter having an input and an output, the output of the phase shifter coupled to the output of the linearizer, the phase shifter configured to adjust a phase of an input signal of the phase shifter, the phase shifter configured to generate a third output signal, the third output signal comprising a feedback signal corresponding to the delta frequency signal, an amplitude and/or a phase of the feedback signal being different from an amplitude and/or a phase of the delta frequency signal generated by the amplifier circuit, respectively; and a bias circuit configured to provide a bias current or a bias voltage to allow a DC voltage level of an output signal of the linearizer to be at a DC voltage level of the input of the amplifier circuit.