Patent ID: 8711980

Claim:
A receiver, comprising: a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal; and an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal, the ADC having a signal transfer function with a transmission zero at a desired frequency; the ADC comprising: a plurality of integrators, each integrator configured to convert a sum of current-mode signals received at its input to a voltage-mode signal indicative of an integral over time of the sum of current-mode signals, the plurality of integrators comprising at least: a first-stage integrator configured to receive at its input the current-mode baseband signal; and a final-stage integrator configured to produce at its output a final-stage analog signal; wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator via a resistor such that the resistor carries a first current-mode signal to the input of the subsequent integrator; a quantizer configured to convert the final-stage analog signal to the digital output signal; a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC; a feedforward path from the output of a first integrator of the plurality of integrators to the input of a second integrator of the plurality of integrators, the feedforward path comprising a capacitor have a capacitance selected to provide the transmission zero in the signal transfer function of the ADC at the desired frequency; and a delay compensation DAC configured to convert the digital output signal into a third current-mode signal such that the third current-mode signal is carried to the input of the final-stage integrator.