Patent ID: 7666742

Claim:
A method of fabricating a semiconductor device, comprising: forming an isolation layer in a substrate to define an active region; forming a recessed region on at least one edge of the active region adjacent to the isolation layer, the recessed region having a first top surface lower than a second top surface of a central portion of the active region; forming a gate electrode crossing over the active region; and forming a source region and a drain region in the active region on both sides of the gate electrode, respectively, wherein a top surface of the active region has a first length between the source region and the drain region crossing the recessed region longer than a second length between the source region and the drain region crossing the central point, wherein a first channel length of the at least one edge of the active region is longer than a second channel length of the central portion, and wherein a gate extension is formed in the recessed region to contact the gate electrode.