Patent ID: 8468294

Claim:
A method of operating a memory system including a controller and a non-volatile memory circuit, the non-volatile memory circuit having a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format, and the controller managing the storage of data on the non-volatile memory circuit and the transfer of data between the memory system and a host system, the method comprising: receiving data from the host; performing a binary write operation of the received data to the first section of the non-volatile memory circuit; subsequently folding portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes: reading the portions of the data from multiple locations in the first section into the read/write registers; and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory, determining in the controller to operate the memory system according to one of a plurality of modes, including a first mode, wherein the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, wherein the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher rate than in the first mode; operating the memory system according to determined mode; wherein the non-volatile memory circuit comprises a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bits lines formed as plurality of erase blocks, and wherein the physical pages of the first and second portions belong to differing erase blocks that share a common set of bit lines; and wherein the memory system operates according to the second mode based on the number of available blocks in the first portion; and wherein multi-state programming operations include a first phase and a second phase, and during the first mode one or more binary write operations to the first section of the memory are performed between the phases of the multi-state programming operations.