Patent ID: 7265023

Claim:
Fabrication method for a semiconductor structure having the steps of: (a) providing a semiconductor substrate; (b) providing and patterning a silicon nitride layer on the semiconductor substrate as topmost layer of a trench etching mask; (c) forming a trench in a first etching step by means of the trench etching mask; (d) depositing conformally a liner layer made of silicon oxide above the resulting structure, which leaves a gap reaching into the depth in the trench; (e) carrying out a V plasma etching step for forming a V profile of the liner layer in the trench; wherein (i) the liner layer is pulled back to below the top side of the silicon nitride layer; (ii) an etching gas mixture comprises C 5 F 8 , O 2 and an inert gas is used in the V plasma etching step; (iii) the ratio of C 5 F 8 /O 2 lies between 2.5 and 3.5; and (iv) the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.