Patent ID: 7038669

Claim:
A video display system that transmits a gain control signal from a video display adapter to a video display, comprising: a pixel clock signal configured to provide a reference at a predetermined fraction of a display pixel clock rate onto a vertical sync signal; a clock enable line configured to enable a display to signal when the display can accept the pixel clock signal; a vertical sync signal line, configured to transmit the pixel clock signal for a plurality of predetermined time intervals; a vertical sync signal comprised of a null pulse on the vertical sync signal line which occurs in a vertical sync signal time between each of the plurality of predetermined time intervals of the pixel clock signal; a video data line configured to carry video image data; a pin in one video data line that is grounded in order to signal to the video display adapter that a gain reference amplitude pulse can be sent; a gain reference amplitude pulse that is transmitted on the video data line during the vertical sync signal time when the vertical sync signal is occupying the vertical sync signal line.