Patent ID: 7439783

Claim:
A phase-locked loop (PPL) circuit comprising a phase detector adapted to receive a reference signal and a feedback signal and in response provide a plurality of control signals including an UP signal and a DN signal; a voltage controlled oscillator adapted to provide at an output the feedback signal for the phase detector; and charge pump coupled between the phase detector and the VCO, the charge pump comprising: a loop filter having first and second loop filter nodes coupled to inputs of the VCO; an amplifier having an output and first and second differential inputs respectively coupled to the first and second loop filter nodes; a first current source coupled to the amplifier output and the first loop filter node; a second current source coupled to the amplifier output and the second loop filter node, wherein the first and second current sources are responsive to the amplifier output to continuously adjust a common mode voltage of the loop filter nodes in response to a signal received from the amplifier output; a third current source coupled to the first loop filter node and controlled by the control signals of the phase detector; and a fourth current source coupled to the second filter node and controlled by the control signals of the phase detector, wherein the third and fourth current sources are electrically isolated from the loop filter nodes if the UP and UN signals are not asserted by the phase detector.