Patent ID: 8086925

Claim:
A method for logic built-in self-test (LBIST) testing an electronic circuit, comprising: selecting a first log interval; selecting a first subset range of LBIST patterns from a plurality of LBIST patterns arranged in an order; wherein each LBIST pattern of the first subset range of LBIST patterns causes an associated output of an electronic circuit; selecting a first log start pattern from the first subset range of LBIST patterns; selecting a first log end pattern from the first subset range of LBIST patterns; testing an electronic circuit in a first test by applying to the electronic circuit the first subset range of LBIST patterns sequentially in the order, thereby generating a first plurality of associated outputs; storing a first subset of associated outputs based on the first plurality of associated outputs, the first log interval, the first log start pattern, and the first log end pattern; and comparing the first subset of associated outputs with known outputs to identify a first output mismatch.