Patent ID: 6992920

Claim:
A nonvolatile semiconductor memory device comprising: a memory array formed of a plurality of memory cells, each having a variable resistive element of which the resistance value is changed in a reversible manner by applying a voltage, aligned in the directions of rows and columns, respectively, in a manner where one end of each memory cell in the same row is connected to the same word line while the other end of each memory cell in the same column is connected to the same bit line; a word line voltage application circuit formed so that one type of word line voltage can be selected from among a plurality of types to be applied to each of said word lines; and a bit line voltage application circuit formed so that one type of bit line voltage can be selected from among a plurality of types to be applied to each of said bit lines, wherein said word line voltage application circuit selects a first word line voltage at the time of programming or erasing operation so that the first word line voltage is applied to the selected word line that is connected to a selected memory cell to be programmed or erased, and selects a second word line voltage so that the second word line voltage is applied to the unselected word lines other than said selected word line, said bit line voltage application circuit selects a first bit line voltage at the time of programming or erasing operation so that the first bit line voltage is applied to the selected bit line that is connected to a selected memory cell to be programmed or erased, and selects a second bit line voltage so that the second bit line voltage is applied to the unselected bit lines other than said selected bit line, and said first word line voltage, said second word line voltage, said first bit line voltage and said second bit line voltage have particular voltage values in accordance with the programming or erasing operation so that the voltage difference between said first word line voltage and said first bit line voltage is set at a value equal to or more than a first voltage difference which allows the resistance value of said variable resistive element to exceed a predetermined value as a result of a change in the case where the first voltage difference is applied across both ends of said variable resistive element and so that the voltage difference between said first word line voltage and said second bit line voltage, the voltage difference between said second word line voltage and said first bit line voltage and the voltage difference between said second word line voltage and said second bit line voltage are respectively set at values equal to or less than a second voltage difference which does not allow the resistance value of said variable resistive element to exceed a predetermined value as a result of a change in the case where the second voltage difference is applied across the both ends of said variable resistive element.