Patent ID: 7714590

Claim:
A method for testing a built-in component including multiple terminals in a multi-layered circuit board, comprising: providing a signal pad on a top surface of the multi-layered circuit board; electrically connecting the signal pad to a first terminal of the multiple terminals of the built-in component at a first location; providing a test pad on the top surface of the multi-layered circuit board; electrically connecting the test pad to the first terminal of the built-in component at a second location; applying a first probe to the signal pad and a second probe to the test pad; and determining a connection status of an electric path extending from the signal pad to the test pad, the electric path extending through the first terminal of the multiple terminals to which the signal pad and test pad is electrically connected, by applying a signal to the first probe and detecting the presence or absence of the signal at the second probe, detection of the presence or absence of the signal being indicative of the connection status.