Patent ID: 8373459

Claim:
An integrated circuit providing a power on reset (POR) signal with respect to a supply voltage comprising: a bias current generating (BCG) stage generating a bias current (Ibias), including a first MOS transistor (M 7 ) having a source connected to a first voltage source (Vcc), a gate and a drain, a first diode connected MOS transistor device (MD) having a plurality of MOS transistors connected in series having a drain and common gates connected to said drain of said first MOS transistor (M 7 ) and a source connected to a second voltage source (OS), a second diode connected MOS transistor (M 6 ) having a source connected to said first voltage source (Vcc) and a commonly connected gate and drain, a second MOS transistor (M 5 ) having a drain connected to said commonly connected gate and drain of said second diode connected MOS transistor (M 6 ), a source, and a gate connected to said drain of said first MOS transistor (M 7 ), a resistor connected between said source of said second MOS transistor (M 5 ) and said second voltage source (OS), a third MOS transistor (M 4 ) having a gate connected to a POR output node (POROUT) and a source-drain path connected in parallel with at least one of said plurality of MOS transistors of said first diode connected MOS transistor device (MD); and an output stage (OS) having a fourth MOS transistor (M 1 ) having a source connected to a said first voltage source (Vcc), a gate connected to said gate of said first MOS transistor (M 7 ) and a drain, a fifth MOS transistor (M 2 ) having a source connected to said drain of said fourth MOS transistor (M 1 ), a gate connected to said drain of said first MOS transistor (M 7 ) and a drain connected to said POR output node (POROUT), and a sixth MOS transistor (M 3 ) having a drain connected to said drain of said fifth MOS transistor (M 2 ), a gate connected to said gate of said fifth MOS transistor (M 2 ), and a source connected a second voltage source (OS).