Patent ID: 8779821

Claim:
A signal delay circuit, comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first input signal to generate a second delay signal; wherein the signal delay circuit selectively enables the delay units of the first delay stage or the second delay stage; and wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled; wherein the first delay stage has a first delay unit and a second delay unit, the second delay stage has a third delay unit, a fourth delay unit and a fifth delay unit; wherein an input terminal of the first delay unit and an input terminal of the third delay unit receive the first input signal, an input terminal of the second delay unit receives an output of the first delay unit and an output of the fifth delay unit, an input terminal of the fourth delay unit receives an output of the third delay unit, and an input terminal of the fifth delay unit receives an output of the fourth delay unit.