Patent ID: 7676922

Claim:
A method of forming a semiconductor structure on a semiconductor device having a first non-conductive region and a first via, the method comprising: forming a first conductive plate that lies over and touches the first non-conductive region and the first via, the first conductive plate having a first region and a second region, the first region having a bottom surface and a top surface, the second region having a bottom surface and a top surface; forming a conductive structure, the conductive structure having a second conductive plate and a side wall, the second conductive plate having a first region that lies directly over the first region of the first conductive plate, and a second region that lies directly over the second region of the first conductive plate, the first region of the second conductive plate having a bottom surface and a top surface, the second region of the second conductive plate having a bottom surface and a top surface, the side wall extending from the bottom surface of the second region of the second conductive plate to the top surface of the second region of the first conductive plate, the first conductive plate being electrically connected to only the first via and the side wall of the conductive structure; forming a second non-conductive region that touches the second conductive plate; and forming a second via in the second non-conductive region that lies above and touches the conductive structure, the conductive structure both touching and being electrically connected to only the first conductive plate and the second via.