Patent ID: 7759745

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a gate insulating film formed on said semiconductor substrate; a plurality of gate electrodes formed on said gate insulating film; a pair of diffusion layers formed at both sides of at least one of the plurality of the gate electrodes and in a surface layer of said semiconductor substrate; and a pair of sidewall films formed on side surfaces of each of the plurality of the gate electrodes, wherein said pair of diffusion layers has one diffusion layer and the other diffusion layer; the one diffusion layer is composed of a single diffusion layer formed to be aligned with at least one of the plurality of the gate electrodes at a depth from the surface of said semiconductor substrate, the other diffusion layer includes a first doped impurity region formed to be aligned with at least one of the plurality of the gate electrodes and having a first depth from the surface of said semiconductor substrate, and a second doped impurity region formed to be aligned with said sidewall film and having a second depth from the surface of said semiconductor substrate which is deeper than the first depth, wherein the second doped impurity region is provided between the sidewall film of at least one of the plurality of the gate electrodes and sidewall film of the other of the plurality of the gate electrodes.