Patent ID: 8068083

Claim:
A display apparatus comprising: a display panel; and a data driver configured to output drive voltages from a plurality of output nodes to drive said display panel, wherein said data driver comprises: a plurality of output amplifiers, each of which is configured to receive a gradation voltage corresponding to a pixel data and to output said drive voltage in response to said gradation voltage; and a driver-side demultiplexer configured to connect said plurality of output amplifiers selection output nodes selected from among said plurality of output nodes, wherein said display panel comprises: a plurality of data lines; and a panel-side demultiplexer configured to connect selection data lines selected from among said plurality of data lines with said plurality of output nodes, wherein said data driver further comprises: a plurality of digital-to-analog (D/A) converters configured to receive a plurality of gradation voltages and to output gradation voltages, corresponding to said pixel data, of said plurality of gradation voltages; a multiplexer configured to connect outputs of selection D/A converters selected from among said plurality of D/A converters, with said plurality of output amplifiers; and a direct switch configured to connect the outputs of said plurality of D/A converters with said plurality of output nodes, wherein said plurality of output nodes comprises first and second output nodes, wherein said of output amplifiers comprises a first output amplifier, wherein said plurality of D/A converters comprises a first D/A converter and a second D/A converter, wherein said multiplexer connects an output of one of said first and second D/A converters with an input of said first output amplifier, wherein said driver-side demultiplexer connects an output of said first output amplifier with one of said first and second output nodes, wherein said direct switch connects said first and second D/A converters with said first and second output nodes, respectively, wherein said driver-side demultiplexer connects the output of said first output amplifier with said first output node in a first period in a horizontal period, wherein said driver-side demultiplexer connects the output of said first output amplifier with said second output node in a second period subsequent to said first period in said horizontal period, and wherein said direct switch connects the output of said first D/A converter with said first output node.