Patent ID: 7830899

Claim:
A buffer circuit for use in a node in a network-based data transport system, the buffer circuit being configurable for providing channel status information of substantially all of a plurality of channels associated with a given signal in the network-based data transport system, the buffer circuit comprising: a memory; and a controller coupled to the memory, the controller being operative: (i) to receive channel status information from a plurality of different channel status sources; (ii) to select one of the plurality of channel status sources for supplying the channel status information at a given point in time; and (iii) to store the channel status information corresponding to the selected channel status source in the memory; wherein the plurality of channel status sources comprises at least a first channel status source and a second channel status source, the first channel status source comprising at least one internal monitor and the second channel status source comprising at least one of an external monitor and a processor interface associated with the circuit.