Patent ID: 8154125

Claim:
A chip package structure, comprising: a carrier; a plurality of first sub-bumps on the carrier, wherein the first sub-bumps are arranged in an array; a plurality of second sub-bumps stacked on the first sub-bumps respectively; a chip having an active surface, wherein the chip is flip-chip bonded and electrically connected to the carrier through the first sub-bumps and the second sub-bumps such that the active surface of the chip faces the carrier and a periphery of the chip is at the exterior of the array and neighboring to both ends of the array; and an underfill layer formed on the carrier between the chip and the carrier by dispensing an underfill material over the carrier and then curing the underfill material before each of the second sub-bumps is disposed on the corresponding first sub-bump by depositing a solder material over the first sub-bump, reflowing, melting and transforming the solder material, wherein a periphery of the underfill layer is at the exterior of the array and neighboring to the both ends of the array, and the periphery of the chip is aligned with the periphery of the underfill, and a gap is maintained between the underfill layer and the chip, and the underfill layer is directly in contact with each of the first sub-bumps and coheres to each of the first sub-bumps.