Patent ID: 8395424

Claim:
A semiconductor device, comprising: an internal terminal; a first transistor of a first conductivity type that is coupled between a first reference potential and the internal terminal, and that includes a first control terminal; a second transistor of a second conductivity type that is coupled between a second reference potential and the internal terminal, and that includes a second control terminal; an oscillator that includes an output terminal to output a clock signal; and a comparator that is coupled to the internal terminal, and that compares a potential of the internal terminal when the internal terminal is coupled to the first reference potential with a potential of the internal terminal when the internal terminal is coupled to the second reference potential, wherein each of the first and second control terminals is coupled to the output terminal to commonly receive the clock signal, and wherein the first and second transistors exclusively operate in response to the clock signal, wherein the internal terminal comprises a first internal terminal, wherein the comparator comprises a first comparator, wherein the semiconductor device further comprises: a second internal terminal; a third transistor of the first conductivity type that is coupled between the first reference potential and the second internal terminal, and that includes a third control terminal; a fourth transistor of the second conductivity type that is coupled between the second reference potential and the second internal terminal, and that includes a fourth control terminal; a second comparator that is coupled to the second internal terminal, and that compares a potential of the second internal terminal when the second internal terminal is coupled to the first reference potential with a potential of the second internal terminal when the second internal terminal is coupled to the second reference potential; and an internal circuit, wherein each of the third and fourth control terminals is coupled to the output terminal to commonly receive the clock signal, wherein the third and fourth transistors exclusively operate in response to the clock signal, and wherein the internal circuit determines an operation mode based on an output of the first comparator and an output of the second comparator.