Patent ID: 7984268

Claim:
A single-chip telecommunications processor, comprising: a plurality of processor cores configured to execute multiple threads; at least one scheduler being coupled to the plurality of processor cores, wherein the at least one scheduler configured to receive a plurality of packet segments arranged in a plurality of packet threads of the multiple threads and to provide a single issue thread of the plurality of packet segments by issuing a packet segment from each of the plurality of packet threads in a sequence, a subsequent packet segment is chosen from a first positional packet thread for each of a first predetermined number of cycles, the subsequent packet segment is chosen from a second positional packet thread for each of a second predetermined number of cycles prior to reaching the first predetermined number of cycles, if a stall condition is detected in the first positional packet thread, rather than from an empty thread among the multiple threads, and the single-chip telecommunications processor is configured for allowing for restarting from a pipeline stall point rather than flushing the pipeline to effect a pipeline stall when the pipeline stall is needed or requested; a first-in first-out buffer that is coupled to a fetch module and is configured to receive the plurality of packet segments arranged in the plurality of packet threads, in which at least one of the plurality of packet segments in the first-in first-out buffer is scheduled out of a first-in first-out order by the at least one scheduler based at least in part upon a signal set by the fetch module to the first-in first-out buffer; and a hazard detection logic module coupled to the fetch module and is configured to determine whether a stall is needed or requested, wherein if a stall is needed or requested, the hazard detection logic module sends a signal to the first-in first-out buffer to restart execution from the pipeline stall point, and if no stall is needed or requested, one of the plurality of packet segments that causes the pipeline stall is discarded from the first-in first-out buffer.