Patent ID: 6989689

Claim:
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal, wherein the regions are disposed on the device in a two-dimensional array of intersecting rows and columns of the regions; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the second high-speed portion substantially directly connects the output terminal of one of the regions to at least one of the input terminals of a subset of immediately adjacent logic regions.