Patent ID: 8415217

Claim:
A method of making a capacitor over a capacitor region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising: forming a first dielectric layer on the substrate in the capacitor region and the NVM region; forming a first conductive layer on the first dielectric layer; performing a patterned etch of the first conductive layer in the capacitor region to form a bottom capacitor layer having a first side and a second side in the capacitor region; forming a second dielectric layer on the bottom capacitor layer; forming a second conductive layer on the second dielectric layer and extending past the first side and the second side of the bottom capacitor layer; performing a patterned etch of the second conductive layer that leaves a patterned second conductive layer having a first side and a second side, wherein a top portion of the bottom capacitor layer is exposed between the first side of the patterned second conductive layer and the first side of the bottom capacitor layer and the second side of the patterned conductive layer extends past the second side of the bottom capacitor layer; forming a first mask over the capacitor region having a first pattern, wherein the first pattern is of a top capacitor electrode region and a second mask over the NVM region having a second pattern, wherein the second pattern includes a pattern of a control gate of an NVM bit cell; and performing an etch through the patterned second conductive layer, the second dielectric layer, and the bottom capacitor layer to leave the top capacitor electrode region from the patterned second conductive layer that extends past the bottom capacitor layer on the second side of the bottom capacitor layer, wherein third sides of the bottom capacitor layer and the top capacitor electrode region are aligned, fourth sides opposite from the third sides of the bottom capacitor layer and the top capacitor electrode region are aligned, and to leave the control gate from the patterned second conductive layer over a floating gate.