Patent ID: 8587908

Claim:
A semiconductor device comprising: a high potential power source line; a first power source line pad connected to the high potential power source line; a low potential power source line; a second power source line pad connected to the low potential power source line; a signal line; a signal pad connected to the signal line; a main protection circuit part configured to discharge an ESD surge applied to a first pad which is any of the first power source line pad, the second power source line pad, and the signal pad to a second pad which is any of the first power source line pad, the second power source line pad, and the signal pad and other than the first pad; and a sub protection circuit part; and a protection target circuit, wherein the protection target circuit comprises: an output MOS transistor whose drain is connected to the signal line, and whose source is connected to one power source line being one of the high potential power source line and the low potential power source line; and a circuit element connected between a gate of the output MOS transistor and the one power source line and configured to function as a resistive element, and the sub protection circuit comprises a first PMOS transistor being connected between the signal line and the gate of the output MOS transistor and whose gate and back gate are connected to the high potential power source line.