Patent ID: 7122876

Claim:
A transistor of an integrated circuit, comprising: a well layer formed on a substrate, the well layer having an upper surface; a first insulating region formed in the well layer to define a first active region in the well layer; a first doped well region formed in the well layer at the first active region, at least part of the first doped well region being adjacent to a gate electrode of the transistor; a recess formed in the first doped well region; a second insulating region formed on the upper surface of the well layer at least partially over the first isolation region; a third insulating region formed at least partially in the recess of the first doped well region, such that at least part of the third insulating is lower than the second insulating region; and a drain doped region formed in the recess of the first doped well region adjacent to the lower part of the third insulating region, such that the third insulating region is located between the gate electrode and the drain doped region.