Patent ID: 7542369

Claim:
An integrated circuit, comprising: a plurality of memory cells organized in rows and columns, each of the plurality of memory cells comprising a power supply voltage node for receiving a memory cell power supply voltage, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line; a discharge circuit, coupled to the power supply voltage node of each of the plurality of memory cells, the discharge circuit for changing a voltage on the power supply voltage nodes of a selected plurality of memory cells during a first portion of a write operation from the first power supply voltage to a predetermined voltage lower than the first power supply voltage; and a memory cell power supply multiplexing circuit, coupled to the power supply voltage node of each of the plurality of memory cells, the memory cell power supply multiplexing circuit for providing a first power supply voltage to the power supply voltage node of the selected column of memory cells during the write operation, the memory cell power supply multiplexing circuit for providing a second power supply voltage greater than the first power supply voltage to the power supply voltage node of all of the unselected columns during the write operation.