Patent ID: 8493810

Claim:
Memory circuitry comprising: a memory cell; a plurality of bit line pairs coupled to said memory cell, each of said plurality of bit line pairs providing part of a data access path to said memory cell; write boost circuitry coupled to a bit line pair of said plurality of bit line pairs and configured apply a boost voltage to a bit line of said bit line pair so as to increase a write voltage difference applied to said memory cell by said bit line pair for a boost portion of a write access so as to assist writing of a bit value to said memory cell; collision detection circuitry configured to detect a collision when said write access at least partially overlaps in time with a read access to said memory cell via a further bit line pair of said plurality of bit lines; and write assist circuitry coupled to said further bit line pair and said collision detection circuitry and configured to respond to detection of said collision to drive a write assist voltage difference applied to said memory cell by bit lines of said further bit line pair with a polarity matching said write voltage difference and a magnitude less than said write voltage difference with said boost voltage applied, said write assist circuitry driving of said further bit line pair independently of said write boost circuitry applying said boost voltage to said bit line pair such that said boost voltage is undiminished by action of said write assist circuitry.