Patent ID: 7620867

Claim:
Test circuitry comprising: A. a test data input external terminal; B. a test clock external terminal; C. a test mode select external terminal; D. a test reset external terminal; E. a test data output external terminal; F. test access port circuitry having: i. an internal test data register, ii. a test data input connected to the test data input external terminal and to the internal test data register, iii. a test clock input connected to the test clock external terminal, iv. a test mode select input connected to the test mode select external terminal, v. a test reset input connected to the test reset external terminal, vi. a test data output connected to the test data output external terminal and coupled to the internal test data register, vii. an external register present input, viii. an external data output separate from the internal test data register, ix. an external data input separate from the internal test data register, x. internal control leads connected to the internal test data register; and xi. external control outputs.