Patent ID: 8154114

Claim:
A semiconductor module comprising: a multilayer substrate comprising a plurality of metal layers and a plurality of ceramic layers, wherein the plurality of ceramic layers comprises a first ceramic layer and a second ceramic layer, wherein each of the plurality of metal layers comprises a thickness in the range from 0.05 mm to 2 mm, wherein the plurality of metal layers comprises at least a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer is a topmost layer of the multilayer substrate and the third metal layer is a bottommost layer of the multilayer substrate, wherein the second metal layer is arranged between the first metal layer and the third metal layer, wherein the first ceramic layer is arranged between the first metal layer and the second metal layer, wherein the second ceramic layer is arranged between the second metal layer and the third metal layer, and wherein the first metal layer and the second metal layer are electrically connected by a via; a power semiconductor chip arranged on the first metal layer and comprised in an electric power circuit; and a housing cover comprising a side wall, where the side wall comprises a bottom surface facing towards the multilayer substrate; wherein the multilayer substrate forms a base plate of the semiconductor module, wherein the multilayer substrate has an area greater than 6 cm×8 cm, wherein the multilayer substrate is configured to press toward a heat sink by a down pressure exerted by the bottom surface of the side wall on a border area of the multilayer substrate, and wherein the second metal layer and the third metal layer are electrically insulated from the electric power circuit.