Patent ID: 7627798

Claim:
A method for performing a series of test cycles using pseudorandom patterns of bits in a logic built-in self test (LBIST) system, wherein the LBIST system includes a plurality of scan chains and a pseudorandom pattern generator (PRPG), wherein the plurality of scan chains extend between portions of functional logic of a device under test and are connected to each other through the portions of functional logic, each of the scan chains including a plurality of scan latches disposed correspondingly to levels of functional logic, and wherein the PRPG is coupled to the plurality of scan chains and configured to generate pseudorandom patterns of bits to be scanned into the scan chains, the method comprising, in each of the test cycles: executing a functional phase in which functional operations are performed, including propagating data through the portions of functional logic of the device under test; executing a first hold phase following the functional phase, wherein in the first hold phase functional operations are suspended and data propagated through the portions of functional logic of the device under test is held; executing a scan shift phase in which scan shift operations are performed, including scanning data into and out of the scan latches through the plurality of the scan chains; and executing a second hold phase following the scan shift phase in which functional operations and scan shift operations are suspended, data scanned out of the plurality of scanned chains is analyzed, and a determination is made, based on the analyzed data scanned out of the plurality of scanned chains, whether to resume functional operations and scan shift operations for a subsequent test cycle, wherein, when the determination is to resume functional operations and scan shift operations for the subsequent test cycle, functional operations and scan shift operations for the subsequent test cycle are resumed without re-initializing the LBIST system.