Patent ID: 8255856

Claim:
A computer implemented method for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing at least a portion of a higher level circuit within the hierarchical representation of the circuit design that includes a reference potential connection, to identify a port of a call within the higher level circuit to a first lower level circuit within the hierarchical representation of a circuit design that is DC path connected to the reference potential; wherein the call represents the first lower level circuit and each port of the call to the first lower level circuit represents a port of the first lower level circuit; identifying a first DC you group that includes each port of the call to the first lower level circuit that represents a port of the first lower level circuit that is DC path connected to the port of the first lower level circuit represented by the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; traversing at least a portion of the first lower level circuit to identify a circuit path within the first tower level circuit that is DC path connected to a marked port of the first lower level circuit; and storing the identified circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit in a non-transitory readable storage media.