Patent ID: 7146490

Claim:
A computer system for processing instructions of a computer program, comprising: a plurality of registers; a plurality of connections corresponding respectively with said registers; at least one pipeline configured to process and execute said instructions; decoding circuitry coupled to said at least one pipeline, said decoding circuitry configured to decode a plurality of encoded register identifiers associated with said instructions into a plurality of decoded register identifiers, one of said decoded register identifiers having a plurality of bits identifying at least one of said registers, each bit of said one decoded register identifier corresponding with a respective one of said plurality of registers; a scoreboard coupled to said plurality of connections and said decoding circuitry, said scoreboard having a plurality of bits corresponding respectively with said plurality of registers, said scoreboard configured to transmit each of said bits across a different one of said connections, each of said bits indicative of whether a pending write to a corresponding one of said registers exists, said scoreboard configured to update at least one of said bits of said scoreboard based on said one decoded register identifier; and hazard detection circuitry coupled to each of said plurality of connections and to said decoding circuitry, said hazard detection circuitry configured to receive each of said decoded register identifiers from said decoding circuitry and to detect data hazards by comparing bits of said decoded register identifiers, including at least one bit of said one decoded register identifier, to said transmitted by said scoreboard.