Patent ID: 8508978

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix shape in a row direction and a column direction, each memory cell comprising a memory element and a cell transistor, wherein the memory element has two input/output terminals so that information is stored using a difference in electrical properties between the two terminals and the stored information is written by applying a writing voltage across the two terminals, the cell transistor has two input/output terminals and one control terminal, and a first end of the input/output terminals of the memory element and a first end of the input/output terminals of the cell transistor are connected; word lines extending in the row direction for connecting the control terminals of the cell transistors in the memory cells arranged in same rows to each other; first bit lines extending in the column direction for connecting second ends of the input/output terminals of the cell transistors in the memory cells arranged in same columns to each other, the second ends of the input/output terminals of the cell transistors being not connected to the memory elements; second bit lines extending in the column direction for connecting second ends of the input/output terminals of the memory elements in the memory cells to each other, the second ends of the input/output terminals of the memory elements being not connected to the cell transistors; a word line voltage applying circuit for applying a voltage to the word line connected to the memory cell selected to be written; a first voltage applying circuit for applying the writing voltage to the first bit line connected to the selected memory cell; and a second voltage applying circuit for applying a pre-charge voltage to both the first bit line and the second bit line connected to the selected memory cell before application of the writing voltage, and applying the pre-charge voltage to the second bit line connected to the selected memory cell while the writing voltage is applied to the first bit line connected to the selected memory cell, wherein each of the cell transistors is a vertical field effect transistor including the first end of the input/output terminals, a channel region, and the second end of the input/output terminals arranged in a third direction that is vertical to the row direction and the column direction, in each of the memory cells, the memory element and the cell transistor are arranged in the third direction, and the word lines, the first bit lines, and the second bit lines are formed apart from each other in the third direction.