Patent ID: 7388252

Claim:
A non-volatile memory array comprising: a semiconductor substrate having a main surface; a first source/drain region in a portion of the semiconductor substrate proximate the main surface; a second source/drain region in a portion of the semiconductor substrate proximate the main surface, the first source/drain region being spaced apart from the second source/drain region; a well region disposed in a portion of the semiconductor substrate proximate the main surface between the first source/drain region and the second source/drain region; and a plurality of memory cells disposed on the main surface of the substrate above the well region and between the first source/drain region and the second source/drain region, each memory cell including: a first oxide layer formed on the main surface of the substrate, the first oxide layer disposed on a portion of the main surface proximate the well region; a charge storage layer disposed above the first oxide layer relative to the main surface of the semiconductor substrate; a second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate; and a plurality of wordlines that are each disposed above the second oxide layer relative to the main surface of the semiconductor substrate and between the first source/drain region and the second source/drain region.