Patent ID: 6998664

Claim:
An integrated semiconductor circuit, comprising: a cell array, the cell array having a plurality of memory cells, each memory cell having a selection transistor and a storage capacitor and capable of being driven electrically by bit lines and word lines; the storage capacitors, the bit lines, and the word lines being arranged in different planes on or in a semiconductor substrate; a plurality of electrical contact structures, the electrical contact structures being arranged at the level of the word lines, the contact structures electrically connecting the bit lines to the selection transistors of the memory cells, the contact structures leading past the word lines and being insulated from the word lines by lateral insulations; and in each case, at least two bit lines being connected to a common signal amplifier, wherein at least one first and a second additional word line are provided, which cannot be used for driving selection transistors, each bit line extending as far as the first or second additional word line and is connected to an additional contact structure, the additional contact structure leading which leads laterally past one of the two additional word lines and representing a dummy contact, additional contact structures of two bit lines leading past different additional word lines, in each case, the two bit lines being connected to the same signal amplifier.