Patent ID: 8193841

Claim:
An apparatus comprising: a voltage rail; a trigger stage having: a PMOS transistor that is coupled to the voltage rail at its source; a voltage divider that is coupled drain of the PMOS transistor; a first NMOS transistor that is coupled to the voltage divider at its gate; a first resistor that is coupled between the voltage rail and the first NMOS transistor at its drain; a first inverter that is coupled to the drain of the first NMOS transistor; and a second NMOS transistor that is coupled to the first inverter at its gate; a second inverter that is coupled to the gate of the PMOS transistor and the drain of the second NMOS transistor, wherein the second inverter includes a switch that is coupled to the first inverter; a third inverter that is coupled to the gate of the PMOS transistor and the drain of the second NMOS transistor; and an output buffer that is coupled to the third inverter.