Patent ID: 7920424

Claim:
A method of operating a non-volatile memory cell having an access transistor and a non-volatile memory transistor, the method comprising: erasing the non-volatile memory cell by applying a first control voltage to a control gate of the non-volatile memory transistor, and applying a second control voltage to a well region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a first direction in the non-volatile memory transistor; programming the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor, and applying the first control voltage to the well region and a drain region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistor; and reading the non-volatile memory cell by turning on the access transistor and monitoring a current flow through the non-volatile memory transistor and the access transistor; maintaining a control gate of the access transistor at the second control voltage during the erase operation; and maintaining the control gate of the access transistor at the first control voltage during the programming operation.