Patent ID: 7644329

Claim:
An integrated circuit testing method, comprising: connecting a plurality of pads in a chip to respectively generate a plurality of scan chains, wherein the plurality of scan chains include at least a first scan chain and a second scan chain, the first scan chain connects a first scan-in pad, a first scan-out pad and at least a first flip-flop, and the second scan chain connects a second scan-in pad, a second scan-out pad and at least a second flip-flop; providing at least a selecting unit; if the second scan-in pad does not connect to a pin of a package when the chip is packaged, the selecting unit selecting a first scan-in signal from the first scan chain and transmits the first scan-in signal to the second flip-flop; and if the second scan-in pad connects to a pin of the package when the chip is packaged, the selecting unit selecting a second scan-in signal from the second scan chain and transmits the second scan-in signal to the second flip-flop.