Patent ID: 8258631

Claim:
A pad layout structure of a semiconductor chip for preventing lead-broken problem of the semiconductor chip, wherein the semiconductor chip has a rectangular shape of which longitudinal length is greater than its transverse length, the pad layout structure comprising: a plurality of IO (input/output) pads arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, wherein the plurality of IO pads include first IO pads that are arranged along the upper and lower sides having the longitudinal length of the semiconductor chip, and second IO pads that are arranged along the left and right sides having the transverse length of the semiconductor chip, wherein the first IO pads each have a width in a direction of the longitudinal length of the semiconductor chip, and first IO pads disposed at edges of the upper and lower sides have widths greater than widths of first IO pads disposed at a center area of the upper and lower sides.