Patent ID: 7132688

Claim:
A method of fabricating a thin film transistor substrate structure which uses a horizontal electric field, comprising the steps of: forming a gate line, a gate electrode connected to the gate line, and a common line being parallel to the gate line by patterning a first conductive layer formed on a substrate; coating a gate insulating film on the substrate, the gate line, the gate electrode, and the common line; forming a semiconductor pattern on a portion of the gate insulating film; forming a data line crossing the gate line and the common line to define a pixel area, a source electrode connected to the data line, and a drain electrode by patterning a second conductive layer, the source electrode and the drain electrode opposing each other on the semiconductor pattern; forming a pixel electrode connected to the drain electrode at the pixel area; coating a protective film on the pixel electrode, the data line, the common line, the source electrode, and the drain electrode; patterning the protective film and the gate insulating film using a photo-resist pattern to provide a hole through the protective film and the gate insulating film exposing a portion of the common line at the pixel area; forming a third conductive layer on the exposed portion of the common line and the photo-resist pattern; and removing the photo-resist pattern covered with a portion of the third conductive layer to form a common electrode connected to the exposed portion of the common line through the hole such that the common electrode is disposed within the hole, wherein the common electrode and the pixel electrode are disposed to define a horizontal electric field.