Patent ID: 8482009

Claim:
A method, comprising: providing a silicon-on-insulator substrate, said silicon-on-insulator substrate comprising a silicon layer separated from a silicon substrate by a buried dielectric layer and including a doped layer in said substrate, said doped layer adjacent to said buried dielectric layer, said doped layer not formed by ion-implantation of a dopant species through said silicon layer; forming dielectric isolation in said silicon layer, said dielectric isolation separating said silicon layer into electrically isolated silicon islands; forming dynamic random access memory (DRAM) cells in respective silicon islands, each DRAM cell comprising a field effect transistor (FET) and a respective trench capacitor, each trench capacitor of said respective trench capacitors comprising a dielectric layer isolating a doped polysilicon inner plate from a diffused outer plate, said diffused outer plate formed in said doped layer and said substrate, said doped layer electrically contacting said outer plate, and forming an electrically conductive contact extending through said trench isolation and said buried dielectric layer into said doped layer.