Patent ID: 7095346

Claim:
An analog to digital converter comprising: a sample and hold circuit operable to sample an input signal; a comparator unit operable to compare the input signal to a reference signal, and to provide a digital output value based upon the comparison; a digital to analog converter (DAC) including a calibration capacitor and a plurality of DAC capacitors, the DAC operably connected to the comparator unit to receive the digital output value, the DAC operable to convert the digital output value into an analog signal; a subtractor operably connected to receive the sampled input from the sample and hold circuit and the digital output value from the DAC, the subtractor operable to subtract the analog signal from the sampled input signal and to generate a remainder based thereon; an amplifier operably connected to receive the remainder from the subtractor and operable to output an amplified remainder based upon the remainder; a weighting unit operable to receive the digital output value from the comparator and operable to provide a weighted digital output value by multiplying the digital output with a received multiplier signal; a switch device operable to switch a received calibration signal to the calibration capacitor and further to each of the plurality of DAC capacitors; and a calibration unit operably connected to receive the calibration signal and the output of the amplifier and operable to control the switch device and to calculate the respective signal gains of each of the plurality of DAC capacitors in order to calculate information representative of a transfer error.