Patent ID: 8149986

Claim:
A shift register circuit, comprising: an input terminal; an output terminal; a clock terminal; a first transistor for supplying to said output terminal a clock signal input to said clock terminal; a second transistor for discharging said output terminal; a pull-up driving circuit for driving said first transistor by charging and discharging a first node connected to a control electrode of said first transistor; and a pull-down driving circuit for driving said second transistor by charging and discharging a second node connected to a control electrode of said second transistor, wherein said pull-up driving circuit includes: a third transistor for charging said first node in accordance with activation of an input signal input to said input terminal; and a boosting unit for boosting, in accordance with the activation of said input signal, a third node being connected to a control electrode of said third transistor, so that a voltage of said third node becomes larger than an amplitude of said input signal; and wherein said boosting unit includes: a charging circuit for charging said third node in accordance with the activation of said input signal, and a boosting circuit for increasing the level of said third node after a predetermined period of time passes since said charging circuit began to charge said third node.