Patent ID: 7620101

Claim:
An equalizer circuit, comprising: a first filter coupled to a transmission line and having a frequency response substantially inverse to that of the transmission line, wherein the first filter comprises adjustable weights for adapting to a plurality of cable lengths, wherein an error signal is used to adjust the weights; a second filter coupled to an output of the first filter and having a frequency response that allows passage of relatively low frequency signals; a voltage detector coupled to an output of the second filter for measuring a peak-to-peak amplitude of the relatively low frequency signals; a slicer circuit coupled to the output of the first filter for producing a first logic value when the output of the first filter exceeds a threshold voltage and for producing a second logic value when the output is less than the threshold voltage; wherein the peak-to-peak amplitude is forwarded by the voltage detector to the slicer circuit to adjust an output amplitude from the slicer circuit, so that the output amplitude substantially matches a maximum peak amplitude of a communication signal forwarded to the transmission line; a first loop configured to match the first filter output with an output of the slicer circuit, wherein the first loop comprises the first filter, the slicer circuit, and an integrator; and a second loop configured to adjust the output amplitude from the slicer circuit, wherein the second loop comprises the second filter, the voltage detector, and the slicer circuit.