Patent ID: 7526584

Claim:
A method for setting up a serial communication port configuration, the serial communication port configuration comprising a hardware circuit of a motherboard having a plurality of digital logic gates and a plurality of chips disposed thereon, said method comprising steps of: initiating a process when said digital logic gates receive a high or low electric potential signal inputted by general programmable input/output (GPIO), and transmitting a processed high or low electric potential signal to said chips for further processing and out-putting the same to execute setting up of the serial communication port configuration; wherein said digital logic gates comprise a first digital logic gate, a second digital logic gate, a third digital logic gate and a fourth digital logic gate; said chips comprise a first chip and a second chip; a GPIO RS-485 port is respectively electrically connected to said first digital logic gate and said third digital logic gate; a GPIO RS-232 port is respectively electrically connected to said first digital logic gate and said second digital logic gate; a GPIO RS-422 port is respectively electrically connected to said fourth digital logic gate and said second chip; said first logic gate is electrically connected to said first chip; said second logic gate is electrically connected to said third digital logic gate; said third logic gate is electrically connected to said fourth digital logic gate; said fourth logic gate is electrically connected to said first chip.