Patent ID: 8377782

Claim:
A method for fabricating a non-volatile memory device comprising: forming gate stacks on a semiconductor substrate; implanting impurity ions at a predetermined tilt angle in the semiconductor substrate wherein each gate stack is laterally spaced at a predetermined interval, wherein a portion of the semiconductor substrate is disposed in a space between adjacent ones of the gate stacks and no gate stack structures are disposed on the portion of the semiconductor device, and wherein each gate stack comprises a tunneling layer disposed on the semiconductor substrate, a charge trapping layer disposed on the tunneling layer, a blocking layer disposed on the charge trapping layer to block charge transfer, and a control gate disposed on the blocking layer; and performing a thermal treatment process to form source/drain junctions between adjacent gate stacks, wherein the source/drain junctions each comprise a first edge portion that overlaps an edge of the one of the plurality of gate stacks and a second edge portion on a side opposite the first edge portion, wherein the second edge portion does not overlap the one of the plurality of gate stacks or an adjacent one of the plurality of gate stacks to be apart from the opposite edge of the gate stacks, and the second edge portion overlaps the portion of the semiconductor substrate in which no gate stack structures are disposed.