Patent ID: 8372698

Claim:
A method of fabricating a semiconductor device having a modified recess channel gate, comprising: forming a device isolation layer for defining an active region over a semiconductor substrate, the active region extending in a major axis direction and a minor axis direction, wherein a width of the active region is defined in the minor axis direction; forming a mask pattern extending in the major axis direction over the semiconductor substrate to expose a specified portion of the active region, the specified portion extending in the major axis direction; forming a stepped surface in the active region in the minor axis direction by etching the semiconductor substrate in the portion of the active region exposed by the mask pattern; forming a trench in the active region of the semiconductor substrate, wherein the trench comprises a step formed at a bottom surface of the trench, the step comprising a lower surface, an upper surface, and a vertical surface, the vertical surface being connected substantially vertically between the lower surface and the upper surface, whereby the vertical surface is substantially perpendicular to the lower surface and the width of the active region; and forming a recess gate filling the trench, wherein the trench comprising the step having the vertical surface increases an effective channel width of the recess gate relative to the width of the active region and increases an effective channel length of the recess gate relative to a depth of the trench.