Patent ID: 7759676

Claim:
A thin film transistor array panel comprising: a substrate; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, wherein the plurality of gate lines and the plurality of data lines form a matrix pattern and wherein the gate lines and the data lines together define four pixels as a 2×2 matrix; a plurality of thin film transistors in the pixels connected to the gate lines and the data lines, wherein each of the plurality of thin film transistors includes an organic semiconductor, wherein the plurality of thin film transistors comprises a first thin film transistor is disposed in a lower right corner of the upper left pixel in the 2×2 matrix, a second thin film transistor is disposed in a lower left corner of the upper right pixel in the 2×2 matrix, a third thin film transistor is disposed in upper left corner of the lower right pixel in the 2×2 matrix, and a fourth thin film transistor is disposed in a upper right corner of the lower left pixel in the 2×2 matrix.