Patent ID: 7158424

Claim:
A semiconductor memory device, comprising: a plurality of memory cells for storing information by storing an electric charge; an access transistor having one source/drain terminal connected to the memory cell and the other source/drain terminal connected to a bit line; a word line connected to a gate terminal of the access transistor; a sense amplifier for amplifying a voltage of the bit line; a first power supply circuit for generating a first supply voltage which is used for driving the word line; and a second power supply circuit for generating a second supply voltage which is used for driving the sense amplifier, wherein the first power supply circuit increases a supply voltage supplied from an external power supply, the second power supply circuit decreases the supply voltage supplied from the external power supply the sense amplifier includes a sense amplifier transistor; the access transistor and the sense amplifier transistor are formed by transistors having gate insulating films of different thicknesses; and the gate insulating film of the access transistor is thicker than that of the sense amplifier transistor.