Patent ID: 8214723

Claim:
A method of encoding an input bit sequence (S 0 ) to yield a coded bit sequence (S), said method comprising: a first coding step (E 1 ) applied to the bits of the input bit sequence (S 0 ) using a first code to generate an output bit sequence; an interleaving step (E 3 ) in which interleaving means ( 33 ) interleave the bits of the output bit sequence obtained using said first code; and a second coding step (E 4 ), referred to as a parity step, applied to the bits obtained from said interleaving means ( 33 ) using a second code to generate said coded bit sequence (S); wherein said parity, second coding step (E 4 ) begins after a predetermined number Δ of bits have been interleaved without waiting for the end of the interleaving step (E 3 ), said predetermined number Δ of bits being less than a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E 3 ), such that the first higher number Δs of bits is less than or equal to a length of the output bit sequence generated by the first coding step.