Patent ID: 8334707

Claim:
A storage circuit with fault detection, comprising: first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state; a data input; a circuitry configured to cause the first fault detection circuit to assume the first stable state and the second fault detection circuit to assume the second stable state to store a data signal applied to the data input; and a first output indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicates a fault, wherein the first fault detection circuit comprises a first reset-set latch and wherein the second fault detection circuit comprises a second reset-set latch, and wherein the circuitry comprises a first inverter coupling an output of the first reset-set latch to a set input of the second reset-set latch and a second inverter coupling an output of the second reset-set latch to a set input of the first reset-set latch.