Patent ID: 8713237

Claim:
An apparatus comprising: a printed circuit board; a transceiver device mounted on the printed circuit board and configured to selectively transmit and receive signals at a first data rate according to a first Physical Coding Sublayer (PCS) protocol or signals at a second data rate according to a second PCS protocol; an X2 form factor pluggable connector configured to plug into an X2 port of a system device, the pluggable connector being disposed at one end of the printed circuit board and comprising: first dedicated pins configured to convey signals at the first data rate between the transceiver device and the system device, and second dedicated pins configured to convey signals at the second data rate between the transceiver device and the system device, wherein the second dedicated pins are distinct from the first dedicated pins; a port device disposed at an opposite end of the printed circuit board and configured to receive a transmission cable, the transmission cable conveying signals at the first data rate or at the second data rate and conveying signals between the transceiver device and a network device; and a management circuit mounted on the printed circuit board and configured to determine which of the first and second data rates is selected based on transmissions between the system device and the network device; wherein the printed circuit board comprises first dedicated signal paths coupling the first dedicated pins of the X2 form factor pluggable connector to the transceiver device and second dedicated signal paths coupling the second dedicated pins of the pluggable connector to the transceiver device, wherein no portions of the second dedicated signal paths overlap portions of the first dedicated signal paths, and the first and second dedicated pins of the X2 form factor pluggable connector have a one-to-one correspondence with pins of the transceiver device, the management circuit being configured to control the transceiver device to transmit and receive signals via the first dedicated pins at the first data rate and to transmit and receive signals via the second dedicated pins at the second data rate.