Patent ID: 8343796

Claim:
A method of fabricating a thin film transistor, comprising: preparing a substrate; forming a buffer layer on the substrate; forming an amorphous semiconductor layer on the buffer layer; patterning the amorphous semiconductor layer to form an amorphous semiconductor layer pattern; forming a gate insulating layer on the amorphous semiconductor layer pattern; forming a gate electrode overlapping the amorphous semiconductor layer pattern on the gate insulating layer; forming an interlayer insulating layer on the entire surface of the substrate; patterning the interlayer insulating layer to form first contact holes partially exposing the amorphous semiconductor layer pattern and a second contact hole at least partially exposing the gate electrode on the gate insulating layer; forming a metal layer on the entire surface of the substrate, the metal layer filling the first contact holes and the second contact hole; applying an electrical field to the metal layer such that a semiconductor layer is formed by crystallization of the amorphous semiconductor layer pattern; and after applying the electrical field to the metal layer, patterning the metal layer such that first portions of the metal layer remain in the first contact holes and a second portion remains in the second contact hole, top surfaces of the first portions being aligned with a top surface of the second portion, and the first portions corresponding to source and drain electrodes that are insulated from the gate electrode and that are electrically connected with the semiconductor layer through the first contact holes.