Patent ID: 8222941

Claim:
A phase selector, comprising: a plurality of first buffers, wherein each of the first buffers provides a clock signal, and the clock signals have different phases; a multiplexer, coupled to the first buffers, for selectively outputting one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal, and the first control signal includes a least significant bit (LSB) of the selecting signal; a first inverter, having an input terminal for receiving a second control signal, wherein the second control signal is second portion of bits of the selecting signal and an output terminal for outputting an inverted signal, and the second control signal is a most significant bit (MSB) of the selecting signal; and a selecting circuit, controlled by the switch signal, for transmitting the second control signal of the selecting signal to an output terminal of the phase selector when the switch signal is in a first logic state and transmitting the inverted signal to the output terminal of the phase selector when the switch signal is in a second logic state.