Patent ID: 8056023

Claim:
A method for determining manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device, comprising: selecting a plurality of target edge pairs from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask, the mask layout data comprising a plurality of polygons, each polygon having a plurality of edges, each target edge pair defined by two of the edges of one or more of the polygons; reducing a number of the target edge pairs to decrease computational volume in determining the manufacturing penalty in making the lithographic mask; determining the manufacturability of the lithographic mask, by a computer, including determining the manufacturing penalty in making the lithographic mask, where determining the manufacturing penalty is based on the target edge pairs as reduced in number; and, outputting the manufacturability of the lithographic mask, by the computer, where the manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask, wherein reducing the number of the target edge pairs comprises: where the mask layout data comprises first and second polygons and first and second mirrored polygons, and where the first and second mirrored polygons are symmetrically laid out in a mirrored manner with respect to the first and second polygons, ignoring the target edge pairs including the edges of the second mirrored polygon related to a manufacturing gap penalty between the first polygon and the second mirrored polygon, and wherein the manufacturing gap penalty relates to a penalty incurred in manufacturing the lithographic mask due to a gap between the first polygon and the second mirrored polygon.