Patent ID: 8296520

Claim:
A method for allocating data in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs, the method comprising: selecting, by a first PU, a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache; sending, by a first downstream link of the first PU, a request to a second PU, wherein the second PU is a neighboring PU of the first PU, the request comprising a first address and first coherency state of the selected castout cache line; wherein the first downstream link couples the first PU to the second PU; determining, by the second PU, whether the first address matches a second address, the second address corresponding to a cache line in a second cache of the second PU; sending, by the second PU, a response to the first PU, based on a coherency state of each of a plurality of cache lines in the second cache and whether the first address matches the second address; determining, by the first PU, whether to transmit the castout cache line to the second PU based on the response; and in the event the first PU determines to transmit the castout cache line to the second PU, transmitting, by the first PU, the castout cache line to the second PU.