Patent ID: 7701249

Claim:
An integrated circuit comprising: A. functional core logic having a data output lead, a data input lead, and control outputs; B. a data input and output lead; C. tristate output buffer circuitry having an input lead, an output lead, and a tristate control input, the output lead being connected to the data input and output lead; D. first switch circuitry connected in series between the data output lead of the core logic and the input lead of the tristate buffer circuitry, the first switch circuitry having a control input connected with a control output of the core logic; E. first holding circuitry connected in series between the data input and output lead and the first switch circuitry; F. second switch circuitry connected in series between a control output of the core logic and the tristate control input of the tristate buffer circuitry, the second switch circuitry having a control input connected with a control output of the core logic; G. input buffer circuitry having an input lead and an output lead, the output lead being connected to the data input lead of the core logic; H. third switch circuitry connected in series between the data input and output lead and the input of the input buffer circuitry, the third switch circuitry having a control input connected with a control output of the core logic; and I. second holding circuitry connected in series between the data input lead of the core logic and the third switch circuitry.