Patent ID: 7993981

Claim:
A method of manufacturing an electronic device package, comprising: coating a first side of a metallic layer with a first insulating layer; coating a second opposite side of said metallic layer with a second insulating layer; patterning said first insulating layer to expose bonding locations on said first side of said metallic layer; patterning said second insulating layer such that remaining portions of said second insulating layer on said second opposite side are located directly opposite to said bonding locations on said first side; selectively removing portions of said metallic layer that are not covered by said remaining portions of said second insulating layer on said second opposite side to form separated coplanar metallic layers, wherein said separated coplanar metallic layers include said bonding locations; and selectively removing said remaining portions of said second insulating layer thereby exposing second bonding locations on said second opposite sides of said separated coplanar metallic layers.