Patent ID: 7020042

Claim:
A multi-port memory having a common memory interface and a plurality of memory ports through which the memory is accessed, the multi-port memory comprising: a first memory cell array having memory cells arranged in at least one memory segment; a first address decoder circuit coupled to the first memory cell array and configured to decode first address signals for accessing memory cells of the first memory cell array; a second memory cell array having memory cells arranged in at least one memory segment, the memory segment of the first memory cell array and the memory segment of the second memory cell array having the same number of memory cells; a second address decoder circuit coupled to the second memory cell array and configured to decode second address signals for accessing memory cells of the second memory cell array; and a third address decoder circuit coupled to the first and second memory cell arrays and configured to decode third address signals for accessing memory cells of the first or second memory cell array, each set of third address signals decoded to access memory cells of one of the memory segments of the first or second memory cell array.