Patent ID: 6972260

Claim:
A method of fabricating a flash memory cell, comprising the steps of: providing a substrate; forming a patterned mask layer over the substrate; etching the substrate using the patterned mask layer as an etching mask to form a trench in the substrate; forming a first dielectric layer over the substrate; forming a first gate and a second gate beside respective sidewalls of the trench, wherein the first gate and the second gate are at a distance from each other and expose a portion of the first dielectric layer at a bottom of the trench; forming a first source/drain region in the substrate at the bottom of the trench; forming a second dielectric layer over the substrate; forming a passivation layer over the second dielectric layer; removing a portion of the passivation layer, the second dielectric layer and the first dielectric layer to expose a substrate surface at the bottom of the trench; forming a third gate that completely fills the trench; removing the patterned mask layer; forming a third dielectric layer over the substrate; forming a fourth gate and a fifth gate beside respective sidewalls of the first gate and the second gate; and forming a second source/drain region in the substrate on one side of the fourth gate and the fifth gate.