Patent ID: 7969217

Claim:
A slew-rate enhancement output stage, comprising: a first slew-rate enhancement circuit receiving a first control voltage and outputting a first voltage, comprising: a first current source coupled to the high voltage source; a second PMOS transistor comprising a third first terminal coupled to the first current source, a third control terminal for receiving the first control voltage, and a third second terminal; a second current source coupled between the third second terminal of the second PMOS transistor and the low voltage source; a second NMOS transistor comprising a fourth first terminal coupled to the first control terminal, a fourth control terminal coupled to the third second terminal of the second PMOS transistor, and a fourth second terminal coupled to the low voltage source; and a third current source coupled between the high voltage source and the first control terminal, wherein the voltage level of the voltage output terminal varies according to the first control voltage; a second slew-rate enhancement circuit receiving a second control voltage and outputting a second voltage; a first PMOS transistor comprising a first first terminal coupled to a high voltage source, a first control terminal for receiving the first voltage, and a first second terminal coupled to a voltage output terminal; and a first NMOS transistor comprising a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source, wherein the first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.