Patent ID: 7897902

Claim:
A single chip integrated circuit suitable for use in an imaging system and comprising: a CMOS integrated circuit having integrally formed thereon: an at least two dimensional array of photosensors; at least one A/D converter receiving outputs from said at least two dimensional array of photosensors; a plurality of digital registers temporarily storing the outputs of said at least one A/D converter; a digital memory storing image data provided; and a plurality of digital adders adding digital values held in said digital registers to corresponding image data stored in said digital memory, such that image data stored in said digital memory is repeatedly summed with the digital values held in said digital registers, and the image data stored in said digital memory comprises a composite sum of the digital values held in said digital registers; and a row timing block controlling said two dimensional array of photosensors, said digital memory, and said plurality of digital adders, and generating an input pointer and an array clock; wherein, at each cycle of the array clock, the digital values held in said digital registers are summed by the adders with image data stored in memory cells of said digital memory determined by said input pointer.