Patent ID: 8198664

Claim:
A semiconductor memory device, comprising: a plurality of supports extending parallel to each other in a first direction on a semiconductor substrate; capacitor lower electrode rows including a plurality of capacitor lower electrodes arranged in a line along the first direction between two adjacent supports from among the plurality of supports, each capacitor lower electrode including outside walls, and a plurality of bit lines extending parallel to each other in the first direction on the semiconductor substrate, wherein the capacitor lower electrode rows are disposed above the plurality of bit lines in regions between two adjacent bit lines from among the plurality of bit lines, wherein each of the capacitor lower electrodes includes two support contact surfaces on the outside walls of the capacitor lower electrode, the support contact surfaces respectively contacting the two adjacent supports from among the plurality of supports, wherein a distance from the semiconductor substrate to an upper surface of each capacitor lower electrode is less than or equal to a distance from the semiconductor substrate to an upper surface of each support, and wherein each of the plurality of supports has a first width in a second direction perpendicular to the first direction, each of the plurality of bit lines has a second width in the second direction, and the first width is greater than the second width.