Patent ID: 7269809

Claim:
An arrangement for performing the design, layout and verification of a monolithic integrated circuit structure comprising at least one digital electronic element, at least one analog/mixed signal element and at least one opto-electronic element, the arrangement comprising: a plurality of design modules for defining and synthesizing in separate ones of said plurality of design modules the at least one digital element, the at least one analog/mixed signal element and the at least one opto-electronic element in terms of behavioral/logic design requirements; a co-simulation module, responsive to the logic design outputs from the plurality of design modules, for simultaneously simulating each type of element and assessing the logical proficiency of the combination; a plurality of physical layout modules, each responsive to the logic design output from an associated design module of the plurality of design modules, for converting each logic design into an associated physical layout arrangement; a co-verification module, responsive to the plurality of physical layout outputs from the plurality of physical layout modules, for simultaneously verifying the physical placements of each type of element and assessing the performance of the combination of elements; and a comparator responsive to the outputs from the co-simulation and co-verification modules for determining if a satisfactory correlation between the logical proficiency and physical placement outputs has been reached, allowing for a final tape-out to be performed.