Patent ID: 7558279

Claim:
An apparatus for reducing transmission delay of packet data, the apparatus comprising: a first memory having a first memory area for storing first packet data to be transmitted, and a second memory area for temporarily storing the first packet data and for combining the first packet data with subsequent second packet data; a second memory for receiving and storing a copy of the first packet data temporarily stored in the second memory area, and transmitting the first packet data to a destination according to a link state; and a frame processor for copying the first packet data from the first memory area to the second memory area, storing a copy of the first packet data stored in the second memory area according to a state of the second memory, deleting the first packet data stored in the second memory area when the copy of the first packet data stored in the second memory is transmitted, determining whether packet data combining is possible according to a state of the second memory area, and combining packet data stored in the first memory area with packet data stored in the second memory area and storing the combined packet data in the second memory if packet data combining is possible.