Patent ID: 7615408

Claim:
A method of manufacturing a semiconductor device comprising a plurality of semiconductor chips including an electrode pad, a semiconductor substrate having a plurality of semiconductor chip forming regions in which the semiconductor chips are formed, an internal connecting terminal provided on the electrode pad, and a wiring pattern which is electrically connected to the internal connecting terminal, the method comprising the steps of: forming the internal connecting terminal on the electrode pads of the semiconductor chips; preparing a support plate having a metal layer in which a metal layer to be a base material of the wiring pattern is provided on a support plate; forming a penetrating portion on the support plate having a metal layer in a part opposite to the semiconductor chips; forming a conductive terminal on the metal layer in a part opposite to the internal connecting terminal; disposing the semiconductor chips and the support plate having a metal layer opposite to each other in such a manner that the internal connecting terminal and the conductive terminal are opposed to each other and pressing the support plate having a metal layer to pressure bond the internal connecting terminal to the metal layer; sealing a portion between the semiconductor chips and the support plate having a metal layer and the penetrating portion with a resin after the pressure bonding step; removing the support plate and forming a protruded portion on the resin in a part corresponding to the penetrating portion of the support plate after the sealing step; forming a resist film covering the metal layer in a part corresponding to a region in which the wiring pattern is formed by using the protruded portion as an alignment mark; and etching the metal layer by using the resist film as a mask to form the wiring pattern.