Patent ID: 7079055

Claim:
A serializer for multiplexing 2 N data streams, each data stream having a frequency of f/(2 N ), N being a positive integer, the serializer comprising: one less than 2 N instances of a dual edge multiplexer flip-flop circuit, each dual-edge multiplexer flip-flop circuit functioning in one of N frequency domains including a first frequency domain having a frequency f/2 N and a last frequency domain having a frequency f/2, wherein each dual-edge multiplexer flip-flop circuit is configured to receive a clock signal and two input data signals each having a frequency of the frequency domain in which that dual-edge multiplexer flip-flop circuit functions and is configured to generate an output data signal having a frequency approximately twice the frequency of the input data signals and the clock signal, wherein the highest clock signal frequency input into the serializer is f/2, the serializer being configured to generate an output signal representing a serialized data stream at frequency f; wherein each dual-edge multiplexer flip-flop circuit comprises a plurality of transistors propagating a first data signal of the two input data signals and a second data signal of the two input data signals to a common output node, wherein each of the first and second data signals is applied to a respective master latch, each of which has a respective node that is in communication with a respective slave latch, the slave latches cooperating as a multiplexer to pass the first data signal from one of the two master latch nodes when the clock signal is in a first state and to pass the second data signal from the other of the two master latch nodes when the clock signal is in a second state, thereby generating an output data stream having a frequency that is approximately twice the frequency of the input data signals.