Patent ID: 7120892

Claim:
A process for processing one or more data structures which define a physical hierarchy of pblocks that contain all instances from a logical netlist and which together comprise a floorplan when an instance from a logical netlist is moved from one pblock to another, comprising the following steps: automatically updating one or more data structures which define a physical hierarchy as instances are moved from one pblock of said physical hierarchy to another pblock so as to create a data structure which accurately reflects which instances of a logical netlist are assigned to which pblocks of said physical hierarchy; automatically making sure that all instances from said logical netlist are included in some pblock of said physical hierarchy; automatically creating or updating one or more data structures which define said physical hierarchy so as to delete conductive paths (hereafter referred to as nets) on said integrated circuit to which said floorplan pertains to eliminate predetermined nets and, create new boundary pins on said pblocks and create new nets which make appropriate connections so as to maintain the same connectivity in said physical hierarchy as is defined in said logical netlist to replace the connectivity of nets which have been eliminated or modified.