Patent ID: 7512012

Claim:
A non-volatile memory, comprising: a memory cell, disposed on a substrate, the memory cell comprising: a first unit, comprising: a first gate; and a first charge trapping layer and a second charge trapping layer, respectively disposed at both sides of the first gate; a semiconductor layer, disposed on the substrate and covering the first unit, the lateral dimension of the semiconductor layer being greater than the lateral dimension of the first unit; a second unit, disposed on the semiconductor layer, the second unit being in mirror symmetry to the first unit with the semiconductor layer as a symmetry axis, the second unit comprising: a second gate, disposed on the semiconductor layer; and a third charge trapping layer and a fourth charge trapping layer, respectively disposed at both sides of the second gate; and a doped region, disposed in both sides of the semiconductor layer and serving as a common source/drain region of both the first unit and the second unit.