Patent ID: 8299535

Claim:
A semiconductor structure comprising: at least one FET gate stack located on an upper surface of a semiconductor substrate, the at least one FET gate stack including a source extension region and a drain extension region located within the semiconductor substrate at a footprint of the at least one FET gate stack, and a device channel located between the source extension region and the drain extension region and beneath the at least one gate stack; embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate, wherein each embedded stressor element includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, wherein the first layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the second layer of the second epitaxy doped semiconductor material, and a delta monolayer of dopant located on the upper surface of the second layer of the second epitaxy dopant semiconductor material; and a metal semiconductor alloy located on an upper surface of the delta monolayer of dopant.