Patent ID: 7563719

Claim:
A dual damascene process, comprising: providing a semiconductor substrate comprising a dielectric layer formed thereon; forming a first photoresist layer overlying said dielectric layer, wherein said first photoresist layer comprises a first opening corresponding to a trench pattern; performing a hardening process on said first photoresist layer to form a harden layer; after performing the hardening process, forming a second photoresist layer overlying said first photoresist layer and a portion of said dielectric layer, wherein said second photoresist layer comprises a second opening corresponding to a via pattern smaller than said trench pattern, said second opening is positioned over said first opening, and said second photoresist layer has a material characteristic different from that of said first photoresist layer; performing a via etching process using said second photoresist layer as a mask to form a via hole passing through said dielectric layer; performing a photoresist ashing process to remove said second photoresist layer; and performing a trench etching process using said first photoresist layer as a mask to form a trench in the upper portion of said dielectric layer; wherein, said via etching process, said photoresist ashing process and said trench etching process are performed in one chamber.