Patent ID: 7425742

Claim:
A NAND architecture floating gate memory cell string, comprising: a single continuous channel region formed on a substrate; and a plurality of depletion mode floating gate memory cells formed on the single continuous channel region; wherein the plurality of depletion mode floating gate memory cells have a native UV erased threshold voltage (UV-Vth) that is negative such that a pre-existing channel of carriers is formed in a depletion channel in the single continuous channel region formed under the plurality of floating gate memory cells of the NAND architecture floating gate memory cell string; and wherein the NAND architecture floating gate memory cell string is adapted to program a selected floating gate memory cell by applying a floating gate programming voltage on a control gate of the selected floating gate memory cell and applying a program voltage or a program-inhibit voltage that is selectively coupled to the pre-existing depletion channel in the NAND architecture floating gate memory cell string.