Patent ID: 7599979

Claim:
An apparatus for hybrid multiplication comprising: a matrix Z generation unit generating a matrix Z of dimensions for the partial multiplication unit, wherein an m-bit multiplier a(x) and an m-bit multiplicand b(x) is multiplied from an coefficient matrix of a(x) in GF(2 m ), and wherein the m-bit multiplicand b(x) is divided by k bits (k≦┌m/2┐); a partial multiplication unit performing the partial multiplication ┌m/k┐k−1 times in units of rows of the matrix Z to calculate an (┌m/k┐k−1)-th partial multiplication value and a final result value of the multiplication; and a reduction unit receiving the (┌m/k┐k−1)-th partial multiplication value fed back from the partial multiplication unit and performing reduction of the value in order to obtain a partial multiplication value next to the (┌m/k┐k−1)-th partial multiplication value.