Patent ID: 8705284

Claim:
A nonvolatile memory device, comprising: a memory cell array comprising a plurality of memory cells arranged in rows connected to a plurality of wordlines, wherein the plurality of wordlines are configured to be grouped into a plurality of groups comprising a first and a second wordline group and each row of memory cells is configured to store three pages of data; a voltage generation circuit configured to generate a program voltage, a plurality of register sets comprising a first and a second register set wherein the first and the second register set are assigned to the first and the second wordline group respectively, and; a program voltage controller configured to detect a program characteristic of a first memory cells connected to a first wordline, and to store a first program code to the first register set with a modified value corresponding to a first program voltage applied to the first memory cells in a program loop where a first off-cell is detected during programming of a first page of data in the first memory cells, wherein after programming of the first page of data in the first memory cells, the program voltage controller is configured to detect a program characteristic of a second memory cells connected to a second wordline adjacent to the first wordline and to store a second program code to the second register set with a modified value corresponding to a second program voltage applied to the second memory cells in a program loop where a first off-cell is detected during programming of a first page of data in the second memory cells, wherein after programming of the first page of data in memory cells connected to the first wordline, the program voltage controller is configured to control a start level of a program voltage to be applied in a program operation used to store a second or a third page of data in the memory cells connected to the first wordline based on the first program code stored in the first register set assigned to the first wordline group including the first wordline, wherein after programming of the first page of data in the second memory cells, the program voltage controller is configured to detect a program characteristic of third memory cells connected to a third wordline and to overwrite a third program code to the first register set with a modified value corresponding to a third program voltage applied to the third memory cells in a program loop where a first off-cell is detected during programming of a first page of data in the third memory cells, wherein the first wordline and the second wordline is included in the first and the second wordline group respectively and the third wordline is included in the first wordline group.