Patent ID: 8384454

Claim:
A delay locked loop (DLL) circuit with dynamic phase-chasing function, comprising: a voltage control delay line (VCDL) circuit for receiving an input clock signal and a control voltage, and delaying the input clock signal according to the control voltage to generate an output clock signal; a predetermined delay circuit for delaying the output clock signal for a predetermined period to generate a feedback clock signal; a divisor-adjustable frequency-dividing circuit for dividing frequencies of the input clock signal and the feedback clock signal, respectively, to generate a divided input clock signal and a divided feedback clock signal, the divisor-adjustable frequency-dividing circuit comprising a timer for counting time to determine if the DLL circuit is in a detecting period, phase-chasing period, or a phase-locking period, wherein the DLL circuit releases a pulse signal in the input clock signal in the detecting period; a phase/frequency detector for comparing phases of the divided input clock signal and the divided feedback clock signal to generate an up signal or a down signal; and a charge pump for adjusting the control voltage according to the up signal and the down signal; wherein the divisor-adjustable frequency-dividing circuit detects an overall loop delay of the input clock signal in the DLL circuit to generate an optimal divisor, and divides the frequencies of the input clock signal and the feedback clock signal according to the optimal divisor.