Patent ID: 8212349

Claim:
A semiconductor package having chip using copper process, comprising: a substrate having a core layer, a copper circuitry including at least a connecting pad, a patterned diffusion barrier on the copper circuitry, and a solder mask, wherein the copper circuitry is formed on the core layer, the patterned diffusion barrier has such a pattern identical to the copper circuitry that an upper surface of the copper circuitry is completely covered, wherein the solder mask covers the patterned diffusion barrier and the core layer and has an opening to expose a portion of the patterned diffusion barrier on the connecting pad, the substrate further has a bonding layer formed on the portion of the patterned diffusion barrier inside the opening; a first chip using copper process disposed on the substrate, the first chip having a first copper pad, the first chip including a first semiconductor layer, a first adhesive layer, and a first barrier layer, wherein the first barrier layer is disposed between the first semiconductor layer and the first adhesive layer to completely cover a backside of the first semiconductor layer; and a first electrical connecting component connecting the first copper pad to the bonding layer.