Patent ID: 7353438

Claim:
A method of testing a semiconductor memory having transparent error correction, the method comprising: providing a test data pattern to the semiconductor memory; generating a corresponding error correction code (ECC) value in response to the test data pattern; storing the test data pattern and the corresponding ECC value in a memory array; reading the test data pattern and the corresponding ECC value from the memory array; passing the test data pattern unmodified as an output data value if no errors exist in the test data pattern and the corresponding ECC value read from the memory array; correcting a single-bit error in the combination of the test data pattern and the corresponding ECC value read from the memory array, if such a single-bit error exists, and passing the resulting test data pattern as an output data value; and ensuring that an erroneous test data pattern having one or more error bits is provided if the combination of the test data pattern and the corresponding ECC value read from the memory array includes a multiple-bit error, and passing the erroneous test data pattern as an output data value, wherein the ECC values are not accessible from outside the semiconductor memory.