Patent ID: 8631380

Claim:
A method of generating a hardware design for a pipelined parallel stream processor, the method comprising: defining, on a computing device, a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor; specifying, on a computing device, at least one propagation rule for said processing operation; defining, on a computing device, a graph representing said processing operation as a parallel structure, said graph comprising at least one data path to be implemented as a hardware design for said pipelined parallel stream processor and comprising a plurality of parallel branches, at least some of said branches being configured to enable, when formed in hardware, data values to be streamed through a plurality of parallel branches simultaneously, the or each data path being represented as comprising: at least one data path input; at least one data path output; and at least one discrete object corresponding directly to a hardware element to be implemented in hardware as part of said pipelined parallel stream processor, the or each discrete object comprising an input for receiving at least one input variable represented in a fixed point format; an operator for executing a function on said input variable or variables; and at least one output for outputting an output variable represented in a fixed point format; optimizing, on a computing device, the number of bits, the offset, the number format and the rounding mode for each output variable from each discrete object in dependence upon the specified propagation rule or rules to produce an optimized graph; and utilizing, on a computing device, said optimized graph to define an optimized hardware design for implementation in hardware as said pipelined parallel stream processor.