Patent ID: 8050012

Claim:
A multilayer chip capacitor comprising: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode, wherein the first capacitor part comprises first and second inner electrodes alternately disposed to be opposite to each other, interposing the dielectric layer therebetween in the capacitor body; the second capacitor part comprises a plurality of third and fourth inner electrodes alternately disposed to be opposite to each other, interposing the dielectric layer therebetween in the capacitor body; and the first outer electrode is connected to the first inner electrode, the second outer electrode is connected to the second inner electrode, the third outer electrode is connected to the third inner electrode, and the fourth outer electrode is connected to the fourth inner electrode.