Patent ID: 8073241

Claim:
A defect source analysis method comprising: storing a first result of a first inspection of a wafer, a second result of a second inspection of the wafer and data of a shape of a conductive pattern by a defect source analysis apparatus, the first inspection performed by a first inspecting apparatus before forming the conductive pattern on the wafer and the second inspection performed by a second inspecting apparatus after forming the conductive pattern on the wafer; establishing a defect source analysis area based on the shape of the conductive pattern by the defect source analysis apparatus; and comparing the first result and the second result with each other in the defect source analysis area by the defect source analysis apparatus; wherein: the conductive pattern is an inspection pattern formed in a chip on the wafer and connected to the wafer, and is a combtoothed pattern including a plurality of sub-patterns arranged in one direction that are electrically connected to each other; and the establishing includes establishing the defect source analysis area that includes only one sub-pattern among the plurality of sub-patterns, wherein the one sub-pattern has a nonconductive area determined from the second result of the second inspection among the plurality of sub-patterns.