Patent ID: 7633118

Claim:
An integrated circuit structure comprising: first and second areas; a semiconductor layer having a major surface formed along a plane in first and second areas; a first doped region of a first conductivity type in the first area of the integrated circuit structure; multiple layers over the first doped region in the first area of the integrated circuit structure, wherein the multiple layers have a window therein extending to the first doped region; a second doped region of a second conductivity type in the window formed in the first area of the integrated circuit structure; a third doped region of the first conductivity type over the second doped region; a gate oxide adjacent the second doped region; a first conductive layer comprising a first laterally disposed electrically continuous region in the first area of the integrated circuit structure and a second laterally disposed electrically continuous region in the second area of the integrated circuit structure, wherein the first laterally disposed electrically continuous region is adjacent the gate oxide in the first area of the integrated circuit structure, and wherein the second laterally disposed electrically continuous region is spaced apart from the gate oxide and in the second area of the integrated circuit structure and wherein the first and second laterally disposed electrically continuous regions are laterally separated by at least an insulating material that defines a separation between the first and second areas of the integrated circuit structure; a first dielectric layer over the second laterally disposed electrically continuous region in the second area of the integrated circuit structure, wherein the first dielectric layer is laterally spaced apart, and separate from the gate oxide; a second conductive layer over the first dielectric layer and wherein the second laterally disposed electrically continuous region in the second area of the integrated circuit structure, the first dielectric layer and the second conductive layer form a capacitor and wherein the first laterally disposed electrically continuous region in the first area of the integrated circuit structure is interposed between the first dielectric region and the gate oxide.