Patent ID: 7825696

Claim:
An even-number-stage pulse delay device comprising: a ring delay line constituted of an even number of inverter circuits connected in a ring, each of said inverter circuits being configured to perform an inverting operation to invert an input signal passing therethrough, a first one of said inverter circuits serving as a first starting inverter circuit which performs said inverting operation when applied with a first control signal, a second one of said inverter circuits excluding said first starting inverter circuit and excluding one of said inverter circuits immediately following said first one of said inverter circuits serving as a second starting inverter circuit which performs said inverting operation when applied with a second control signal; a second-control-signal inputting section configured to cause an edge of a first pulse as a main edge and an edge of a second pulse as a reset edge which inverts in an opposite direction as said main edge to circulate together around said ring delay line, said first pulse being generated by applying said first control signal to said first starting inverter circuit to cause said first starting inverter circuit to perform said inverting operation, said second pulse being generated by applying said second control signal to said second starting inverter circuit during a time period after said main edge is generated at said first starting inverter circuit and before said main edge reaches said second starting inverter circuit from said first starting inverter circuit; and an operation monitoring section configured to detect whether or not said main and reset edges are circulating around said ring delay line.