Patent ID: 8806149

Claim:
A logic verifying apparatus for carrying out logic verification on a system including a first processor and a plurality of first controllers that control a first access that the first processor makes to a memory, the access being made by the first processor using a verification model, the logic verifying apparatus comprising: a second processor corresponding to the first processor; and one or more second controllers corresponding to the first controllers, the number of which is less than that of the first controllers, each controls a second access to the memory, the access being made by the second processor, the second processor and the second controllers serving as elements in the verification model, and the second processor including: a storing unit that stores information for assigning one or more of the second controllers that is to be used as the verification model, wherein the second processor converts a first address indicating an entity that the second processor is to access through the one second controller assigned by the information stored in the storing unit, into a second address, such that the second processor access the memory, by converting one or more assigning address bits that assign the one second controller through which the second processor makes the access into a value indicating the one second controller assigned by the information stored in the storing unit, and the one second controller interleaving-controls the second access that the second processor makes to the memory, based on the values of one or more assigning address bits in the second address, wherein the second processor converts the address by: fixing at least one of the assigning address bits of the first address, wherein the assigning address bits are not the most significant bit of the first address, to a value of an assigned address bits that specifies the one second controller assigned by the information stored in the storing units; discarding the number of bits which is reduced from the most significant bit of an address bit representing a memory region of the memory by fixing the at least one of the assigning address bits; and shifting, by the number of the discarded bits, bits in the first address indicates the entity that the first processor accesses between an address bit corresponding to a fixed pattern in the assigning address bits and a bit lower by the number of the discarded bits than the most significant bit.