Patent ID: 7864894

Claim:
A receiver circuit which receives serial data transmitted from a transmission circuit, comprising: a clock generator which generates n (n represents an integer of 2 or more) clock signals at the same frequency as that of the serial data with a phase shift of 1/n cycles between the clock signals; a data acquisition unit which acquires the serial data at a timing of each of the n clock signals; a phase detection unit which detects the phase of the transition edge of the serial data using the n bits of data acquired by said data acquisition unit; an effective bit number determination unit which determines an effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step; a data-bit output unit which receives the n bits of data acquired by said data acquisition unit, and which selects from among the n bits of data the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data, and which outputs the bits of data thus selected; a counter which counts values that correspond to the effective bit numbers created every time the bits of data are acquired; a shift register which has stages, the number of which is greater than the number of bits of transmission unit of the serial data, and which sequentially stores the bits of data output from said data-bit output unit, with a variable shift amount which is adjusted according to the effective bit number; and a data output unit which determines the position of the first bit of the serial data in the bit stream stored in said shift register based upon the count value counted by said counter, and which outputs the serial data in a predetermined format.