Patent ID: 7917740

Claim:
A processor comprising: one or more registers configured to store: (i) a floating point error indication that corresponds to a floating point error output signal transmitted by the processor external to the processor to indicate a floating point exception, and (ii) an ignore error indication that corresponds to an ignore error input signal to the processor, wherein an asserted ignore error input signal indicates that the floating point error signal is to be ignored; and an execution core coupled to the one or more registers, wherein the execution core is configured to update the floating point error indication and the ignore error indication to track a state of the floating point error output signal and to emulate the ignore error input signal, respectively, and wherein the execution core is configured to execute floating point instructions, and wherein the execution core is configured to detect a floating point instruction in a guest for which execution would be frozen if the floating point error signal is asserted and the ignore error signal is deasserted, and wherein the execution core is configured to exit the guest responsive to detecting the floating point instruction and responsive to the floating point error indication and the ignore error indication.