Patent ID: 7209404

Claim:
A memory array optimized for power consumption and performance, the memory array comprising: a configuration wherein the memory array is separated into sub-arrays; a facility for monitoring power and ground voltage levels of each sub-array; a facility for controlling power and ground voltage supply lines of each sub-array, wherein: a predetermined power voltage level and a predetermined ground voltage level are provided to any sub-array that is being accessed; and another predetermined power voltage level and predetermined ground voltage level are provided to any sub-array that is not being accessed; and a sequentially accessible memory buffer, wherein: a copy of contents of an accessed memory and nearby memory cells is temporarily stored in the buffer; and during a memory addressing operation, at first the buffer is checked and: if a copy of the content of the addressed memory is in the buffer, the buffer content is outputted; and if a copy of the content of the addressed memory is not in the buffer, then the addressed memory itself is accessed and copies of the contents of the accessed memory and the nearby cells are stored in the buffer and is outputted.