Patent ID: 7920423

Claim:
A non-volatile memory (NVM) circuit, comprising: a first NVM sub-array having first memory cells; a second NVM sub-array having second memory cells constructed differently from the first memory cells; and a support circuit shared by the first and the second NVM sub-arrays, wherein one of the first memory cells includes a first programming transistor with a first programming active area and a first read-out transistor with a first read-out active area, there being defined a first quotient of the first read-out active area over the first programming active area, and wherein one of the second memory cells includes a second programming transistor with a second programming active area and a second read-out transistor with a second read-out active area, there being defined a second quotient of the second read-out active area over the second programming active area different in size from the first quotient by at least 15%.