Patent ID: 6862296

Claim:
A receive deserializer circuit which frames data, comprising: a sampling flip flop for receiving serial data including a data reference pattern, wherein said sampling flip flop retimes said serial data to a recovered clock as sampled serial data; a demultiplexer for deserializing said sampled serial data into a parallel data word timed to a word clock from a clock generator; a comparator for making a comparison of said parallel data word with a preset data reference pattern until said comparison results in a match; a logic controller for interpreting whether the output of said comparator results in said match and for generating a shift pulse following each of said comparisons which do not result in said match; and said clock generator for dividing said recovered clock into phase clocks, said word clock being one of said phase clocks, and for disabling said phase clocks for a period of one bit upon receipt of said shift pulse, thereby creating a one bit shift in the alignment of said parallel data word being generated on said word clock by said demultiplexer.