Patent ID: 8305121

Claim:
A circuit for generating a signal having a desired phase delay comprising: a first delay chain including M delay cells to generate a first phase shift control setting, said first delay chain comprising: M identical delay cells connected in series, each delay cell having a first input for receiving a clock signal and a second input for receiving a digital value that is the phase shift control setting and an output for outputting a delayed clock signal; a phase detector that measures a phase difference between a signal received at a first input terminal and a signal received at a second input terminal wherein the signal received at the first input terminal is a clock signal that has not been delayed by the first delay chain and the signal received at the second input terminal is a clock signal that has been delayed by at least one of the delay cells of the first delay chain; and a digital counter that updates the phase shift control setting in accordance with the phase difference measured by the phase detector and applies the updated phase shift control setting to at least one of the second inputs of the delay cells; a circuit for forming a second phase shift control setting; and a second delay chain including N delay cells that is configured to receive the first phase shift control setting and the second phase shift control setting to produce the desired phase delay in the signal.