Patent ID: 8320484

Claim:
A data processing apparatus operable to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising: an interleaver configured to read-into an interleaver memory the predetermined number of the input data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the interleaver memory the input data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals; and an address generator configured to generate the set of addresses, an address being generated for each of the input data symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator including: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is less than one thousand and twenty four, the linear feedback shift register has nine register stages with a generator polynomial for the linear feedback shift register of R′ i [8]=R′ i−1 [0]⊕R′ i−1 [8], and the permutation order forms, with an additional bit, a ten bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] in accordance with a code defined by the table: R′ i bit positions 8 7 6 5 4 3 2 1 0 R i bit positions 4 3 2 1 0 5 6 7 8.