Patent ID: 7940578

Claim:
A flash memory device, comprising: first and second memory cell array blocks, the first and second memory cell array blocks each including a plurality of wordlines and a plurality of bitlines, wherein a plurality of memory cells serially connected to each bitline constitute a single string, a plurality of memory cells connected to each wordline constitute a page, and a plurality of pages constitute a block; and a row decoder coupled to the first memory cell array block and the second memory cell array block, wherein the row decoder includes: a block decoder configured to provide a block selection signal in response to a first block signal and a second block signal, wherein the first block signal selects the first memory cell array block, and the second block signal selects the second memory cell array block, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to the block selection signal received from the block decoder, a first pass transistor unit configured to provide first driving voltages to the wordlines of the first memory cell array block in response to the block wordline signal received from the single high voltage level shifter, and a second pass transistor unit configured to provide second driving voltages to the wordlines of the second memory cell array block in response to the block wordline signal received from the single high voltage level shifter.