Patent ID: 8880772

Claim:
An information handling system comprising: one or more processors; a memory controller coupled to the one or more processors; a channel buffer coupled to the memory controller, wherein the channel buffer is configured to receive control information from the memory controller; and a plurality of memory modules coupled to the channel buffer by a first plurality of point-to-point control distribution paths and by a first plurality of point-to-point data paths, wherein the channel buffer is further configured to transmit two or more copies of replicated control information to two or more of the plurality of memory modules; wherein at least one of the plurality of memory modules comprises: a module buffer, wherein the module buffer transceives the two or more copies of replicated control information via gated copy lines which are disposed to distribute the copies; and a plurality of ranks, wherein the module buffer provides additional levels of fan-out via the gated copy lines disposed to provide distribution to a plurality of the plurality of ranks; wherein at least one of the ranks comprises: a buffer configured to receive control information from the module buffer; and a plurality of memory devices coupled by a second plurality of point-to-point control distribution paths to the buffer and by a second plurality of point-to-point data paths directly to the module buffer, wherein the buffer is further configured to transmit two or more copies of replicated control information to two or more of the plurality of memory devices.