Patent ID: 7151300

Claim:
A phase-change memory device comprising: a semiconductor substrate having a bottom structure; a dielectric interlayer formed on the semiconductor substrate to cover the bottom structure; contact plugs formed within the dielectric interlayer; bottom electrodes formed on the contact plugs, each of the bottom electrodes having both side surfaces in contact with a first oxide layer, a phase-change layer, a nitride layer, and a second oxide layer; top electrodes formed on portions of the dielectric interlayer between the contact plugs, respectively, each of the top electrodes having both side surfaces in contact with the first oxide layer, the phase-change layer, the nitride layer, and the second oxide layer; the phase-change layer formed between the first oxide layer and the nitride layer while being in contact with the side surfaces of the bottom electrodes and the top electrodes; a third oxide layer formed on the bottom electrodes and the top electrode and having a contact hole for exposing the top electrode; and a metal wire formed in the contact hole and on the third oxide layer while being in contact with the top electrode.