Patent ID: 7797550

Claim:
A system for securely buffering content, comprising: a signal processor; and a memory coupled to the signal processor, wherein the memory and the signal processor are part of an integrated chip, wherein the signal processor is configured to decrypt, to parse, to filter and to decode content, wherein, before the content leaves the signal processor for the memory, the signal processor secures the content during intermediate stages of processing, wherein, after the secured content enters the signal processor from the memory, the signal processor recovers the content from the secured content, wherein the signal processor is configured to use encryption if an output signal of the signal processor is digital and is configured to degrade signal resolution if the output signal of the signal processor is analog, wherein the signal processor is configured to degrade video content by degrading I-frames in the video content to satisfy a particular threshold level, wherein the signal processor comprises a first processor and a second processor, the first processor being coupled to the second processor, wherein the first processor comprises a transport processor, wherein the second processor comprises a video decoder, wherein, before the content leaves the transport processor for the memory, the transport processor secures the content, and wherein, after the video decoder receives the content secured by the transport processor, the video decoder recovers the content from the secured content.