Patent ID: 7234038

Claim:
A computer system comprising: a plurality of processors; a memory operatively connected to the plurality of processors; a storage device; and software instructions stored on the storage device for enabling the computer system to: place a first mapping entry in a first translation lookaside buffer (TLB) associated with a first processor, wherein the first processor is one of the plurality of processors and wherein the first mapping entry is associated with: a virtual memory address, a first physical memory address corresponding to the virtual memory address, and a first page mapping cookie value associated with the first physical memory address; place the first page mapping cookie value and the first physical memory address in a page mapping cookie buffer (PMCB), wherein the PMCB is adapted to communicate with the plurality of processors; receive a memory operation comprising the virtual memory address by a second processor, wherein the second processor is one of the plurality of processors and wherein the second processor is associated with a second TLB; translate the virtual memory address to obtain a second physical memory address using a second mapping entry associated with the virtual memory address, wherein the second mapping entry is located in the second TLB; extract a second page mapping cookie value from the second mapping entry; determine whether the second page mapping cookie value is equal to the first page mapping cookie value in the PMCB; if the second page mapping cookie value is equal to the first page mapping cookie value, complete the memory operation using the second physical memory address; and if the second page mapping cookie value is not equal to the first page mapping cookie value, restart the memory operation.