Patent ID: 7539042

Claim:
A semiconductor device comprising: a memory cell which comprises a switch which is an MOS transistor and a capacitor, and in which a first source-drain region of the MOS transistor is connected to one electrode of the capacitor; and a control circuit for recording one bit of memory data by storing charge in the capacitor or discharging stored charge, and reading one bit of memory data by reading a potential of the capacitor, the semiconductor device further comprising: a storage circuit for recording a back bias potential value to be applied to a back gate of the MOS transistor; and a back gate potential generation power supply which generates a back bias potential based on the back bias potential value, and supplies the back bias potential to the back gate, wherein, when a threshold of the MOS transistor is greater than a target threshold value of the MOS transistor, the back bias potential value which is shallower than a target back bias potential is recorded in the storage circuit.