Patent ID: 6870777

Claim:
A semiconductor memory device, comprising: a data access path for accessing a memory cell; a signal drive circuit which drives a signal on said data access path; a dummy path that emulates said data access path; and a dummy drive circuit which emulates said signal drive circuit, wherein said dummy path has a smaller load than said data access path, and said dummy drive circuit has a smaller drive capacity than said signal drive circuit; and further comprising: a control circuit which generates a timing control signal in response to a signal having propagated through said dummy path; and an input/output circuit which amplifies a signal at timing responsive to the timing control signal, wherein a point farthest away on said dummy path from said control circuit is closer to said control circuit than is a point farthest away on said data access path from said control circuit, wherein said data access path and said signal drive circuit include: a decoder circuit which is driven by said control circuit; and a memory cell array which includes word lines, memory cells, and bit lines driven in response to said decoder circuit, and wherein said dummy path and said dummy drive circuit include: a dummy word decoder which emulates said decoder circuit; a dummy word line circuit which emulates at least one of said word lines; a dummy memory cell which emulates at least one of said memory cells; and a dummy bit line circuit which emulates the bit lines, wherein said dummy word decoder, said dummy word line circuit, said dummy memory cell, and said dummy bit line circuit are situated at a corner of said memory cell array closest to said decoder circuit and said input/output circuit.