Patent ID: 8223528

Claim:
A control method for at least one memory cell comprising a transistor and a resistor connected to the transistor in series between a first node and a second node, comprising: programming the memory cell in a programming mode, wherein the step of programming the memory cell comprises: providing a first controlling voltage to a gate of the transistor; providing a first setting voltage to the first node; and providing a second setting voltage to the second node; determining whether the memory cell has been successfully programmed; when the memory cell has been successfully programmed, impedance of the memory cell is in a first state, and when the memory cell has not been successfully programmed, a specific action is executed, wherein the specific action is to reset the memory cell, and the step of resetting the memory cell comprises: providing a second controlling voltage to the gate of the transistor, wherein the first controlling voltage is less than the second controlling voltage; providing a first reset voltage to the first node; and providing a second reset voltage to the second node, wherein the impedance of the memory cell is in a second state after the step of resetting the memory cell, and wherein the impedance of the memory cell in the second state is higher than the impedance of the memory cell in the first state.