Patent ID: 8892923

Claim:
A data processing apparatus comprising: a counting circuit for maintaining a time count value for said data processing apparatus, said counting circuit comprising a main counter and a further counter; and a counter controller configured to control said counting circuit; wherein: said counting circuit has a plurality of modes of operation including: (i) a normal mode of operation in which said main counter is configured to increment said time count value in response to clock edges of a main clock signal; and (ii) a power saving mode of operation in which said main clock signal is disabled, and said further counter is configured to count a number of elapsed clock edges of a further clock signal having a lower frequency than said main clock signal; wherein: on switching from said normal mode to said power saving mode, at least one of said counting circuit and said counter controller is configured to store, as a reference time count value, a current value of said time count value at a timing triggered by a first edge of said further clock signal; and on switching from said power saving mode to said normal mode, said counter controller is configured to set said time count value of said main counter to an expected time count value calculated based on said reference time count value and the number of elapsed clock edges of said further clock signal counted by said further counter since said timing triggered by said first edge, and to control said main counter to restart incrementing of said time count value from said expected time count value at a timing triggered by another edge of said further clock signal.