Patent ID: 8881301

Claim:
An integrated circuit comprising: a data in port; a data out port; a plurality of data path storage units, each data path storage unit comprising a shift register; a data path passing serially from the data in port to each of the data path storage units to the data out port, wherein: the data in port, the data path storage units, and the data out port are all elements in the data path; and in response to a shift signal, each data path storage unit is configured to: transmit a value stored in its shift register to the next element in the data path; receive a new value from the previous element in the data path; and store the new value in the shift register of the data path storage unit; one or more segment storage units, each segment storage unit comprising a shift register; and a data path segment passing serially through each of the one or more segment storage units; wherein the data path storage units comprise: a gateway storage unit further comprising an update register; a set of one or more key storage units, each key storage unit further comprising an update register, each key storage unit configured to, in response to an update signal, store a value stored in its shift register in its update register; and wherein: each of the one or more key storage units is configured to, in response to its update register storing a key value, transmit a key signal to the gateway storage unit; and the gateway storage unit is configured to, in response to the gateway storage unit receiving a key signal from each of the set of key storage units and the gateway storage unit receiving an update signal, store a value stored in its shift register in its update register; and the gateway storage unit is configured to, in response to the gateway storage unit update register storing a gateway value, insert the data path segment in the data path.