Patent ID: 7474575

Claim:
An apparatus for testing a memory of an integrated circuit for a defect, the apparatus comprising: a test unit for testing whether a memory element in the memory is failing and generating a fail signal in response thereto, a redundant memory element being tested only when the redundant memory element has been enabled to replace a failed memory element; a failing address register for containing an address location of a failing memory element to be replaced by a redundant memory element, the failing address register having an enable bit for controlling whether the memory element whose address location is contained in the failing address register is to be replaced with a corresponding redundant memory element and having a temporary enable bit for holding a value to be loaded into the enable bit upon a load-enable signal; and a load-enable signal activator for providing a load-enable signal to load the value of the temporary enable bit into the enable bit so as to enable the redundant memory element.