Patent ID: 7051138

Claim:
A data processing system comprising: a set of memory modules for storing program instructions and data, the set of memory modules comprising at least one low-speed memory and at least one high-speed memory, the low-speed and high-speed memories both storing an interrupt vector table individually for recording at least one entry instruction of an interrupt service routine; and a microprocessor comprising: a central processing unit (CPU) for executing program instructions and calculating data, wherein the CPU is designed to fetch the program instructions in the low-speed memory when an interruption occurs; and a memory controller to enable the CPU, under the memory controller's control, to fetch the program instruction and access the data in the set of memory modules, the memory controller also comprising a first re-addressing device; wherein, when the interruption occurs, the CPU generates an interrupt vector address for the memory controller, and when re-addressing device of the memory controller identifies that the interrupt vector address falls within the address range of the interrupt vector table, the re-addressing device sending an enable signal to the high-speed memory enabling the CPU to fetch the corresponding entry instruction of the interrupt service routines stored in the high-speed memory, instead of the predetermined low-speed memory, so as to reduce the interrupt latency when fetching the program instruction.