Patent ID: 7454671

Claim:
A test system for testing a memory device, comprising: a signal generator to initially generate and output from the test system sets of memory write command signals and sets of address signals and to output from the test system respective sets of write data signals along with each of the sets of the memory write command signals, the signal generator further subsequently generating and outputting from the test system sets of memory read command signals and sets of address signals, the command and address signals being generated in a manner that requires all of the memory cells being tested to be accessed during a test only once for writing data and only once for reading data; a comparator coupled to the signal generator, the comparator being to receive each set of read data signals received by the test system responsive to each set of the memory read command signals and each set of the address signals output from the test system, the comparator comparing each set of received read data signals to a corresponding set of the write data signals, the comparator outputting a fail data signal responsive to at least one signal in the received set of read data signals not matching a corresponding signal in the set of write data signals; and a repair analyzer coupled to the signal generator and the comparator, the repair analyzer receiving the sets of address signals from the signal generator and the fail data signal from the comparator, the repair analyzer being responsive to each fail data signal to capture a corresponding set of address signals, analyze the captured address signals to identify addresses corresponding to a failing group of memory cells based on the number of subgroups of memory cells in group that have failed and determine from the identified addresses while the addresses signals are being captured a repair solution.