Patent ID: 8765497

Claim:
A method comprising: placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component, wherein each of the plurality of bottom units comprises: a package substrate comprising: dielectric layers; metal features on opposite sides of the package substrate; metal lines and vias in the dielectric layers, wherein the metal lines and vias electrically inter-couple the metal features on the opposite sides of the package substrate; and a solder ball facing the jig; and a die bonded to the package substrate; placing a plurality of upper component stacks onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units; and performing a reflow to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls, wherein during the reflow, the solder ball is spaced apart from the jig.