Patent ID: 8464199

Claim:
A method for designing an integrated circuit, the method comprising the steps of: a computer determining, for one or more paths in a circuit design, for a value of a design variable at which timing closure of the circuit design is achieved, an approximate slope of a function representing path delay as a function of the design variable; the computer determining that one of the one or more approximate slopes is not within a defined slope range; the computer determining a slope adjustment direction and a path slack adjustment value based in part on the magnitude by which the one approximate slope is not within the defined slope range, such that when the path slack adjustment value is applied to the slack of the path associated with the one approximate slope, the associated path does not meet timing closure; and the computer changing the circuit design of the path associated with the one approximate slope, based in part on the adjustment direction and the slack of the path associated with the one approximate slope with the path slack adjustment value applied, to affect the adjusted path slack of the associated path to cause the associated path to meet timing closure, whereby the design changes to affect the adjusted path slack of the associated path cause the one approximate slope to be within the defined slope range.