Patent ID: 7657857

Claim:
A method for generating a connectivity diagram for a circuit design, comprising: specifying a circuit design hierarchy level at which electrical connectivity is to be analyzed; operating a computer system to visually render in a graphical display a geometric shape representing each entity present within the specified circuit design hierarchy level, a size of each geometric shape being defined to represent an amount of electrical connectivity present within the corresponding entity represented by the geometric shape relative to an amount of electrical connectivity present within the entities represented by other geometric shapes, wherein a shape and the size of a given geometric shape does not correspond to an actual shape and an actual size of a given entity represented by the given geometric shape, wherein the visual rendering of geometric shapes by the computer system is performed automatically based on analysis by the computer system of electrical connectivity within the specified circuit design hierarchy level; operating a computer system to visually render in the graphical display a number of lines extending between one or more pairs of the geometric shapes, each line representing electrical connectivity between the entities represented by the pair of geometric shapes associated with the line, wherein an attribute of each line is defined to represent an amount of electrical connectivity present between the entities represented by the pair of geometric shapes relative to an amount of electrical connectivity present between entities represented by other pairs of geometric shapes, wherein the visual rendering of the number of lines by the computer system is performed automatically based on analysis by the computer system of electrical connectivity between entities represented by the one or more pairs of geometric shapes, wherein the connectivity diagram is an abstraction of the circuit design and is not a layout of a chip.