Patent ID: 7820552

Claim:
A method of patterning a gate stack comprising: providing an unpatterned gate stack including, from bottom to top, a high-k gate dielectric, a high-k gate dielectric capping layer which includes at least one element selected from Group 2, 3, and 13 of the Periodic Table of Elements, and a Si-containing conductor on a surface of a semiconductor substrate; and patterning said unpatterned gate stack to form at least one patterned gate stack on said surface of said semiconductor substrate utilizing a dry etching process followed by a wet etching process, wherein said dry etching process patterns the Si-containing conductor, the high-k gate dielectric capping layer and the high-k gate dielectric, stops on a surface of said high-k gate dielectric capping layer, and converts the at least one element within said high-k gate dielectric capping layer to a soluble compound, wherein an underlying portion of said high-k gate dielectric is covered by said soluble compound and is not exposed after said dry etching process and before said wet etching process, said soluble compound having a different composition than said high-k gate dielectric, and said wet etching process subsequently removes the soluble compound and said underlying portion of said high-k gate dielectric from the surface of the substrate.