Patent ID: 8618651

Claim:
An interposer suitable for use in a packaging substrate, comprising: a substrate comprising a silicon material, a bottom surface of the substrate defining a PCB mounting surface; an interconnect layer disposed on the substrate, the interconnect layer comprising conductive and dielectric layers patterned to form a plurality of top wires, a top surface of the interconnect layer defining a chip mounting surface; a plurality of through-vias formed through the substrate in an isolated region of the substrate, at least one of the plurality of conductive vias electrically coupled to at least one of the top wires; a plurality of blind-vias formed through the substrate in a dense region of the substrate, the through-vias and blind vias formed during a common etching step, at least one blind-via comprising: (a) a dielectric material lining the blind-vias; and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.