Patent ID: 7548470

Claim:
A memory control method, comprising: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results, wherein the phase detection results represent the phase difference between the data strobe signal and the clock signal, and the delay amount of the odd/even data corresponds to the phase detection results.