Patent ID: 8446187

Claim:
A circuit for power-on detection, comprising: a power-on reset circuit that is arranged to provide a power-on reset signal such that the power-on reset signal is unasserted approximately when a power supply voltage reaches a predetermined level, wherein the power-on reset circuit includes: a first current source circuit that is arranged to provide a first current such that the first current varies based on the power supply voltage; a second current source circuit that is arranged to provide a second current such that the second current is substantially independent of the power supply voltage; and a comparison circuit that is arranged to compare the first current to the second current, and to provide a comparison output signal based on the comparison, wherein the power-on reset signal is based, at least in part, on the comparison output signal, wherein the power-on reset circuit is arranged to receive the power supply voltage at a first node; the first current source includes: a first transistor having at least a gate, a drain, and a source, wherein the drain of the first transistor is coupled to a second node, and the source of the first transistor is coupled to a third node; and a second transistor having at least a gate, a drain, and a source, wherein the drain of the second transistor is coupled to the third node, a first resistor that is coupled between the first node and the second node, wherein the first resistor is arranged to received the power supply voltage at the first node, wherein the first current is the current through the first resistor, and wherein the gate of the first transistor is coupled to the second node, and the second current source includes: a third transistor having at least a gate, a drain, and a source, wherein the gate of the third transistor is coupled to the third node, the drain of the third transistor is coupled to a fourth node, and the gate of the second transistor is coupled to the fourth node; wherein the source of the third transistor is coupled to a fifth node; the second current source further includes: a second resistor that is coupled between the fifth node and a sixth node, wherein the second current is the current through the second resistor, wherein the second current source further includes: a fourth transistor having at least a gate, a drain, and a source; wherein the gate of the fourth transistor is coupled to the second node, the drain of the fourth transistor is coupled to a seventh node, and the source of the fourth transistor is coupled to the fourth node, wherein the second current source further includes: a third resistor that is coupled between the source of the fourth transistor and the fourth node, such that the source of the fourth transistor is coupled to the fourth node via the third resistor, wherein the third resistor is a diffusion resistor, and wherein the third transistor has a positive temperature coefficient.