Patent ID: 7505282

Claim:
A laminated bond of multilayer circuit board having embedded chips comprising a bottom multilayer circuit board comprising multiple conductive wires; an insulating layer formed under and covering parts of the conductive wires; a frame mounted under the insulating layer and having multiple enclosures; multiple chips mounted under the insulating layer, being respectively enclosed by one enclosure and respectively electronically connected to the exposed conductive wires; a press laminate formed on the frame and in the enclosures to encapsulate the chips; a patterned conductive layer adhered under the frame by the press laminate; and at least one inner contact via formed through the conductive wires, the insulating layer, the frame, the press laminate and the patterned conductive layer to electronically connect the conductive wires to the patterned conductive layer; an upper multilayer circuit board mounted on the bottom multilayer circuit board and comprising multiple conductive wires; an insulating layer formed on and covering parts of the conductive wires in the upper multilayer circuit board; a frame mounted on the insulating layer in the upper multilayer circuit board and having multiple enclosures; multiple chips mounted on the insulating layer in the upper multilayer circuit board, respectively enclosed by one enclosure in the upper multilayer circuit board and respectively electronically connected to the exposed conductive wires in the upper multilayer circuit board; a press laminate formed on the frame and in the enclosures in the upper multilayer circuit board to encapsulate the chips in the upper multilayer circuit board; a patterned conductive layer adhered to the frame by the press laminate in the upper multilayer circuit board; and at least one inner contact via formed through the conductive wires, the insulating layer, the frame, the press laminate and the patterned conductive layer to electronically connect the conductive wires to the patterned conductive layer in the upper multilayer circuit board; a glue layer formed between and sticking the bottom and the upper multilayer circuit boards together; multiple contact vias formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards; and two insulating lacquer layers respectively coated under portions of the patterned conductive layer in the bottom multilayer circuit board and on portions of the patterned conductive layer in the upper multilayer circuit board to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.