Patent ID: 7379006

Claim:
A converter responsive to a multi-bit input signal, the converter including: an input signal line carrying the multi-bit input signal; an input signal value buffer coupled to the input signal line; a first position indicator buffer of a first indicator designating a first ordinal position in a circularly ordered set having at least as many elements as there are allowable discrete values of the multi-bit input signal; first logic coupled to the first position indicator buffer, adapted to periodically shift the first ordinal position designated by the first indicator; second logic coupled to the input signal line and the input signal value buffer adapted to calculate an input signal difference between the multi-bit input signal and a buffered prior input signal; third logic coupled to the second logic, adapted to adjust at least one of the first indicator or a second indicator designating a second ordinal position in the ordered set responsive to the input signal difference, wherein an indicator difference between the first and second ordinal positions corresponds to the value of the multi-bit input signal; and fourth logic coupled to the first position indicator buffer, adapted to output a signal having at least as many bits as there are allowable discrete values of the input signal, the bits corresponding to respective positions in the circularly ordered set, values of bits in the output signal responsive to a containment relationship between the first and second indicators and the respective positions.