Patent ID: 8860511

Claim:
A frequency divider comprising: an oscillation circuit having M delay elements connected so that an output signal of a previous stage is input as an input signal of a subsequent stage, an output signal of a final stage is input as an input signal of an initial stage, and the input signal of the initial stage is reversed from the output signal of the final stage, wherein M is even integer not less than 2; and at least one locked signal injection circuit configured to generate a locked signal from an input oscillation signal, which regulates the change in the state of the delay elements, and to inject the generated locked signal into at least part of the delay elements, a frequency-divided signal of the input oscillation signal being output from the oscillation circuit, wherein, the delay elements have a division transistor, the division transistor having a control terminal and two controlled terminals, wherein an input signal is input to the control terminal, wherein an output is obtained from one of the controlled terminals, and wherein the other controlled terminal is an injection node, and wherein the locked signal injection circuit has: an injection differential pair having two auxiliary injection transistors provided in parallel so as to be connected to the injection node of the division transistor of two of the delay elements of the oscillation circuit, wherein the two of the delay elements are apart from each other with M/2-1 of the delay elements arranged therebetween; and a signal injection transistor connected to the injection differential pair so that a differential signal of the input oscillation signal is generated at a connection node connected to the injection node of the injection differential pair, the signal injection transistor capable of inputting the input oscillation signal to the control terminal.