Patent ID: 7389390

Claim:
A method of operating a microprocessor system provided with safety functions, which comprises two or more processor cores ( 1 , 2 ) on a joint chip carrier, the microprocessor system comprising periphery elements ( 5 , 7 ) to which the cores can have access for write or read operations, including the steps of making a distinction between algorithms for safety-critical functions and algorithms for comfort functions, storing safety-critical data in critical-data ranges, storing comfort-related data in uncritical-data ranges ( 12 ), generating, by means of the safety-critical functions, input/output operations for a first type of devices intended for safety functions, and generating, by means of the comfort functions, input/output operations for a second type of devices intended for comfort functions wherein exclusively critical algorithms are stored in two or more first separate chip ranges or components ( 20 ) of two or more read-only memories ( 5 and 8 ) or corresponding partial ranges of respectively contiguous joint read-only memories ( 5 , 7 and 8 , 9 ), and exclusively comfort algorithms are stored in two or more other separate chip ranges or components ( 21 ) of the read-only memory ( 7 and 9 ) or in corresponding other partial ranges of respectively contiguous joint read-only memories ( 5 , 7 and 8 , 9 ).