Patent ID: 8823001

Claim:
A method for manufacturing a thin film transistor (TFT) array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process, and forming a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process, and forming a first via hole in the passivation layer located above the source electrode and a second via hole in the passivation layer located above the drain electrode; and depositing stacked layers of a pixel electrode layer and a data line layer in this order, performing a third photolithograph process, and forming a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole, wherein the step of depositing a pixel electrode layer and a data line layer in this order, performing a third photolithograph process, and forming a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole comprises: depositing the pixel electrode layer and the data line layer in this order, and performing the third photolithograph process by using a third photo mask; etching the stacked layers to form a pixel electrode pattern and the data line which is connected to the source electrode through the first via hole; and etching the data line layer located above the pixel electrode pattern so as to form the pixel electrode which is connected to the drain electrode through the second via hole.