Patent ID: 7563663

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a second NMOS region for forming a second NMOS transistor with a higher operating voltage than said first NMOS transistor; (b) selectively forming a first gate insulating film in both said first NMOS region and said second NMOS region; (c) selectively forming a first gate insulating film greater in thickness than said first gate insulating film on said second NMOS region; (d) forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and on said second gate insulating film of said second NMOS region, respectively; (e) forming a first silicon oxide film whole surface of the silicon substrate and anisotropically etching back the first silicon oxide film to form a first offset sidewall on side surface of said first and second gate electrodes; (f) ion implanting a N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode; (g) forming a second offset sidewall with a silicon oxide film on said first offset sidewall; (h) ion implanting said N-type impurity into said second NMOS region using said second gate electrode and said first and second offset sidewall as implant masks to form second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.