Patent ID: 7365596

Claim:
A circuit comprising: a first power domain including circuitry coupled to receive a first power supply signal; and a second power domain including circuitry coupled to receive both the first power supply signal and a second power supply signal, the second power domain including a buffer, the buffer comprising: a first buffer portion coupled to receive the second power supply signal, the first buffer portion including a buffer data input; and a second buffer portion coupled to receive the first power supply signal, the second buffer portion including a buffer data output, wherein one of the first and second power supply signals is configured to be selectively enabled independently from the other of the first and second power supply signals; wherein: each of the first and second buffer portions includes a data path portion coupled in series between the buffer data input and the buffer data output; the second buffer portion includes a feedback portion which is coupled to receive a power gate indicator to enable the feedback portion during a power saving mode; and the data path portion of the first buffer portion is an inverter which is disabled by the power gate indicator during the power saving mode.