Patent ID: 7123533

Claim:
A memory circuit comprising; an array of memory cells, each memory cell operable to store an information item for a duration of a data retention time, the information item stored in the memory cells being refreshed in the context of a read, write and refresh operation; a refresh control circuit for driving a memory cell array to access ones of the memory cells for a refresh process; and a storage circuit, which is assigned to at least one of the memory cells, for storing a time information item with regard to a last previous access to the memory cell assigned to the storage circuit during the operation of the memory, the storage circuit having a register for storing a register bit; wherein the time information item stored in the storage circuit is altered, proceeding from an initial value, in such a way that the register bit of the storage circuit is set at the latest after the data retention time of the memory cell assigned to the storage circuit has elapsed; wherein the refresh control circuit evaluates the register bit of the storage circuit and accesses the memory cell array in the case of a set register bit in such a way that the memory cell assigned to the storage circuit is refreshed; and wherein the time information item stored in the storage circuit is reset to the initial value after a read, write and refresh operation at the memory cell assigned to the storage circuit and the register bit of the storage circuit is erased.