Patent ID: 8829582

Claim:
A semiconductor device comprising: element regions each of which is surrounded by an element isolation region, the element regions having transistor regions and capacitor regions; MOS transistors each of which is formed on one of the transistor regions, each of the MOS transistors having two gates on an associated one of the element regions and three first impurity-doped regions in the associated one of the element regions, a first one of the gates formed between a first one of the first impurity-doped regions and a second one of the first impurity-doped regions, a second one of the gates formed between the second one of the first impurity-doped regions and a third one of the first impurity-doped regions, the first impurity-doped regions functioning as either of a source and a drain; capacitor elements each of which is formed on one of the capacitor regions; a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to one of the MOS transistors via either of the source and the drain thereof, the voltage generating circuit outputting a voltage from a first MOS transistor in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second MOS transistor in a previous stage in the series connection; second impurity-doped regions which are formed on the first impurity-doped regions; contact plugs which are formed on the second impurity-doped regions to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between one of the gates and one of the second impurity-doped regions which is adjacent to the one of the gates for the first MOS transistor being larger than that for the second MOS transistor; and a memory cell which is capable of holding data, the voltage output by the voltage generating circuit being applied to the memory cell.