Patent ID: 7435618

Claim:
A method to manufacture a coreless packaging substrate, the steps comprising: (A) providing a carrier board and forming a first dielectric layer on one surface of the carrier board, and forming a first resistive layer on a surface of the first dielectric layer, wherein a plurality of first openings are formed in the first resistive layer to expose parts of the carrier board; (B) forming a first metal layer in each of the first openings, and removing the first resistive layer; (C) forming a built-up structure on the surfaces of the first dielectric layer and the first metal layers, wherein the built-up structure includes at least a dielectric layer, at least a second metal layer of patterned circuit, a plurality of conductive vias, as well as a plurality of conductive pads; (D) removing the carrier board; (E) forming a first solder mask on a surface of the built-up structure and forming a second solder mask on the surface of the first dielectric layer, wherein a plurality of second openings are formed in the first solder mask to expose the conductive pads of the built-up structure, and a plurality of third openings are formed in the second solder mask to expose parts of the first dielectric layer, and the third openings correspond to the first metal layers; (F) forming a plurality of fourth openings in the exposed first dielectric layer to expose parts of the first metal layers; and (G) forming a plurality of solder bumps in the second openings in the first solder mask, and forming a plurality of solder layers in the third openings in the second solder mask.