Patent ID: 8237861

Claim:
A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, comprising: a filter circuit outputting a wide bandwidth filtered signal and a narrow bandwidth filtered signal of the received video signal; a dynamic slicer threshold generator generating a slicer threshold according to the wide bandwidth filtered signal within a time window; a timing recovery circuit generating a phase error and the line timing signal according to the wide bandwidth filtered signal and the slicer threshold; a phase error statistics circuit averaging the phase error to generate an average phase error; a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal; and a finite state machine (FSM) controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker according the status of the video horizontal synchronizer and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.