Patent ID: 7253524

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first metal layer formed overlying the semiconductor substrate; a composite etch stop layer, comprising a first etch stop layer overlying a second etch stop layer, formed overlying the first metal layer and the semiconductor substrate; a dielectric layer formed overlying the etch stop layer; and a second metal layer penetrating the dielectric layer and the etch stop layer and electrically connected to the first metal layer; wherein, the etch stop layer has a dielectric constant smaller than 3.5; wherein, the dielectric layer has a dielectric constant smaller than 3.0; wherein the dielectric layer has a tensile stress approximating to the compressive stress of the etch stop layer; wherein the first etch stop layer is a SiCO film, and the second etch stop layer is a SiCO film; wherein a first etching selectivity S 1 of the first etch stop layer to the dielectric layer, and a second etching selectivity S 2 of the second etch stop layer to the dielectric layer satisfy the formula: S 1 ≠S 2 .