Patent ID: 7304347

Claim:
A power semiconductor device made in accordance with a method comprising the steps of: A. providing a substrate of a first conductivity type; B. forming a voltage sustaining region on said substrate; 1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type; 2. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween; 3. depositing a barrier material along the walls and bottom of said trench; 4. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer; 5. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer; 6. depositing a filler material in said terraced trench to substantially fill said terraced trench; and C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.