Patent ID: 8265195

Claim:
A hybrid data transmission circuit, comprising: a data transmitter having a parallel-to-serial conversion function; and a PLL (phase-locked loop) circuit unit configured to supply a clock to the data transmitter, wherein the data transmitter includes a first parallel-to-serial conversion circuit configured to receive a first multiphase clock, and to perform parallel-to-serial conversion based on a first conversion ratio, and a second parallel-to-serial conversion circuit configured to receive a second multiphase clock, and to perform parallel-to-serial conversion based on a second conversion ratio, which is different from the first conversion ratio, and the PLL circuit unit includes a multiphase VCO (voltage-controlled oscillator) circuit configured to generate and output the first multiphase clock, and a multiphase clock generator configured to generate and output the second multiphase clock based on a clock output from the multiphase VCO circuit.