Patent ID: 7426254

Claim:
A shift register comprising: a register flip-flop group circuit comprising a plurality of series connection register flip-flops, wherein the register flip-flop group circuit receives input data and shifts the input data in response to a clock signal; and, a plurality of output circuits respectively receiving a plurality of enable signals, wherein each output circuit comprises: a fuse control flip-flop receiving a register output signal and one of the plurality of enable signals, wherein the register output signal is output by one of the plurality of register flip-flops and the fuse control flip-flop is adapted to output a fuse control signal in response to the one enable signal; an electrical fuse receiving the fuse control signal and outputting an electrical fuse mode signal; and, a multiplexer receiving the register output signal, the electrical fuse mode signal, and the one enable signal, wherein the multiplexer is adapted to output either the register output signal or the electrical fuse mode signal as a final output signal in accordance with the one enable signal.