Patent ID: 8743116

Claim:
An apparatus comprising: a processor; and memory coupled to the processor, the memory comprising executable instructions that when executed by the processor cause the processor to effectuate operations comprising: constructing a graph representing a first configuration of shader nodes of a plurality of shader nodes, each shader node of the plurality of shader nodes being indicative of renderable shading functionality and being compatible with a plurality of renderers, wherein a renderer renders a shading effect; traversing the graph in reverse order by: selecting an output shader node; pre-pending to the selected output shader node, at least one input shader node; executing central processing unit orchestration code encapsulated inside the selected output shader node for reading one or more input pins of the selected output shader node; and updating a value of at least one output pin of the selected output shader node based on reading the one or more input pins; invoking shading functionality of a selected shader node; and rendering the shading effect on a display device in accordance with the invoked shading functionality.