Patent ID: 8022523

Claim:
A multi-chip stack package, comprising: a first wiring substrate with a front side and a rear side, the first wiring substrate comprising a first solder ball and a second solder ball disposed on the rear side of the first wiring substrate; a first chip disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate, the first chip having a first active surface, the first chip further comprising a first bonding pad and a second bonding pad disposed on the first active surface, wherein the first bonding pad is electrically connected to the first solder ball, and the second bonding pad is electrically connected to the second solder ball; a second wiring substrate disposed on the first active surface of the first chip and electrically connected to the first wiring substrate; and a second chip disposed on the second wiring substrate and electrically connected to the second wiring substrate, wherein the second active surface of the second chip faces the first active surface of the first chip.