Patent ID: 7663397

Claim:
A semiconductor device comprising: an on-die termination (ODT) control circuit configured to generate a termination resistance control signal in response to a first clock signal and a first ODT signal; and a termination resistance generator configured to generate termination resistance in response to the termination resistance control signal, wherein the ODT control circuit includes, a clock buffer configured to buffer the first clock signal so as to output a second clock signal, a delay-locked loop configured to receive the first clock signal and to output a third clock signal synchronized with the first clock signal, an ODT buffer configured to buffer the first ODT signal so as to output a second ODT signal, and a control block configured to generate the termination resistance control signal based on the second clock signal, the third clock signal and the second ODT signal, and wherein the control block includes a pipe line structure in a path of the second ODT signal, the pipe line structure changing in response to a frequency of the second clock signal.