Patent ID: 7353326

Claim:
A flash memory device supporting a cache read operation comprising a series of consecutive data read operations, the flash memory device comprising: first and second buffer memories; a non-volatile memory core comprising: a non-volatile memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of pages; and a page buffer adapted to read data from a selected memory block; a first register adapted to store address and command information; a control logic circuit comprising a second register and adapted to generate an enable signal upon detecting that command information is written into the first register; and a copy circuit adapted to copy the address and command information stored in the first register to the second register in response to the enable signal; wherein the control logic circuit controls the first and second buffer memories and the non-volatile memory core based on the address and command information stored in the second register; and address information for a next data read operation is stored in the first register.