Patent ID: 7791388

Claim:
A method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal, the method comprising: detecting a time difference between high- and low-portions of the first clock signal by measuring the high-portion and the low-portion of the first clock signal, the high-portion of the first clock signal is the time of a clock period the clock signal is high and the low-portion of the first clock signal is the time of the clock period the clock signal is low; generating signals indicative of incremental increases and decreases in the difference between the high- and low-portions of the first clock signal; generating the correction signal to change the phase relationship of the first and second complementary clock signals by increasing or decreasing the phase by an incremental change in response to the signals indicating a time difference between the high- and low-portions of the first clock signal of two incremental increases or decreases; counting occurrences of the signals indicative of incremental increasing and decreasing differences between the high- and low-portions of the first clock signal in a first direction in response to the signals indicative of an increasing time difference between the high- and low-portions of the first clock signal; and counting occurrences of the signals indicative of incremental increasing and decreasing differences between the high- and low-portions of the first clock signal in a second direction in response to the signals indicative of decreasing time difference between the high- and low-portions of the first clock signal.