Patent ID: 7646052

Claim:
A semiconductor device, comprising: a substrate having a first region, a second region and a third region, a DRAM formed in the first region, an SRAM formed in the second region, said SRAM including two access transistors, gate electrodes of said access transistors being separated from each other, a logic formed in the third region, a first wiring layer which comprises a lowest metal layer, a first insulating layer formed on the first wiring layer, a second wiring layer formed on the first insulating layer, a second insulating layer formed on the second wiring layer, and a third wiring layer formed on the second insulating layer, wherein said SRAM is connected to said first and second wiring layers, but not said third wiring layer, and whereby intermacro connections between the DRAM, logic and SRAM need not bypass the second region containing the SRAM; wherein said DRAM cell is formed on a substrate, said DRAM cell having a transistor connecting to a bit line and capacitor having a lower electrode, a dielectric film and an upper electrode; and said SRAM cell is formed on the substrate, said SRAM cell having a cross couple connection; wherein said cross couple connection is formed in a layer formed between said dielectric film and a layer of a plug which connects to said bit line.