Patent ID: 7372311

Claim:
A delay locked loop (DLL), comprising: a clock delay unit for receiving an external clock and an external clock bar signal to generate an internal falling clock and an internal rising clock having a predetermined delay amount; a duty control unit for controlling each duty rate of the internal falling clock and the internal rising clock based on an extended mode register set (EMRS) input or a fuse option; and a DLL clock driving unit for driving output clocks of the duty control unit to generate a DLL clock, wherein the duty control unit includes: a rising timing control for outputting a rising control pulse signal to control a point of a rising time of its own output clock by delaying the internal falling clock and the internal rising clock; a delay control signal generator for receiving the fuse option or the EMRS input to generate first to third delay control signals; a falling timing control unit for outputting a falling control pulse signal to control a point of a falling time of its own output clock by delaying the internal falling clock and the internal rising clock according to the first to third delay control signals; and a signal generator for generating its own output clock in response to the rising and the falling control pulse signals.