Patent ID: 7269130

Claim:
An apparatus comprising: (1) a first line transceiver bank; (2) a second line transceiver bank; (3) a first switching unit comprising: (a) a first input for receiving a first line signal from said first line transceiver bank, (b) a first output for transmitting a second line signal to said second line transceiver bank, (c) a second input for receiving a third line signal from said second line transceiver bank, and (d) a second output for transmitting a fourth line signal to said first line transceiver bank; and (4) a second switching unit comprising: (a) a first input for receiving said first line signal from said first line transceiver bank, (b) a first output for transmitting a fifth line signal to said second line transceiver bank, (c) a second input for receiving said third line signal from said second line transceiver bank, and (d) a second output for transmitting a sixth line signal to said first line transceiver bank; wherein: said first switching unit further comprises: (e) a first constituent add/drop multiplexor: (f) a second constituent add/drop multiplexor, wherein said first and second constituent add/drop multiplexors are identical integrated circuits: (g) a third line transceiver bank comprising: (i) at least one deserializer for deserializing said first line signal, (ii) at least one serializer for serializing said fourth line signal, and (iii)at least one multiplexor for selectively sending said fourth line signal to said first constituent add/drop multiplexor as said first line signal, and (h) a fourth line transceiver bank comprising: (i) at least one deserializer for deserializing said third line signal, (ii) at least one serializer for serializing said second line signal, and (iii)at least one multiplexor for selectively sending said second line signal to said second constituent add/drop multiplexor as said third line signal.