Patent ID: 8574979

Claim:
A method for manufacturing a semiconductor device, comprising: providing a substrate having a P-type metal oxide semiconductor (PMOS) device region and an N-type metal oxide semiconductor (NMOS) device region; forming a first gate structure over the substrate in the PMOS device region and a second gate structure over the substrate in the NMOS device region; forming recessed epitaxial silicon germanium regions in the substrate in the PMOS device region on opposing sides of the first gate structure; forming first source/drain regions including first source/drain implants in the recessed epitaxial silicon germanium regions on opposing sides of the first gate structure, and forming second source/drain regions including second source/drain implants on opposing sides of the second gate structure; annealing the first source/drain regions and the second source/drain regions including annealing the first source/drain implants and the second source/drain implants to form activated first source/drain regions and activated second source/drain regions; and after the annealing, forming recessed epitaxial carbon doped silicon regions in the substrate in the NMOS device region on opposing sides of the second gate structure, wherein the recessed epitaxial carbon doped silicon regions replace portions of the activated second source/drain regions, and other portions of the activated second source/drain regions remain which are not located within the recessed epitaxial carbon doped silicon regions.