Patent ID: 7926014

Claim:
A clock-gating circuit insertion method comprising: executing by a computer processor the operations of: detecting a position where a clock-gating circuit is inserted based on a circuit data and a delay data, inserting the clock-gating circuit into the position, performing timing analysis of an enable signal for the clock-gating circuit, calculating an upper limit of delay variations for the enable signal to satisfy setup conditions on the basis of the result of the timing analysis, and inserting a selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit into the position for insertion, wherein the selector circuit selects and outputs the enable signal when delay variations are not above the upper limit, and selects and outputs a signal designating a clock signal when the delay variations are above the upper limit, and the clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.