Patent ID: 7680962

Claim:
A stream processor comprising: a plurality of array type processors, each array type processor including: a data path unit for executing a processing of data, and a state management unit for controlling a state of said data path unit in accordance with a command supplied to the state management unit specifying processing which should be executed on the data; a descriptor management table, said table to receive and store descriptors which include information used to identify data; an input DMA circuit, said DMA circuit including an input coupled to a memory space and including outputs coupled to inputs of the data path units and inputs of the state management units and the descriptor management table; and a memory access control circuit, said memory access control circuit having inputs coupled to the descriptor management table and to outputs of the data path units and having an output coupled to a memory space, wherein the input DMA circuit reads a descriptor and associated data from the memory space, extracts a command from the descriptor, transfers the command to the state management units, registers the descriptor in the descriptor management table and supplies the associated data to data path units.