Patent ID: 7420280

Claim:
A semiconductor die, comprising: a plurality of contact pads formed on the die; a plurality of under bump structures, each under bump structure including a metal layer and an uppermost passivation layer having a plurality of vias formed therein, wherein each via extends through the uppermost passivation layer to an associated contact pad such that the plurality of vias are associated with at least some of the contact pads, and wherein the metal layer extends through the vias such that the metal layer is in substantial contact with the associated contact pad, whereby at least some of the contact pads have under bump structures with a plurality of metallized vias; and a plurality of solder bumps, each solder bump being formed on an associated under bump structure, wherein within each under bump structure, the metal layer extends over at least portions of the passivation layer to form a unified under bump metallization pad over the associated contact pad and wherein a width of the via cross sections is in the range of about 2-100 micrometers.