Patent ID: 8745555

Claim:
A method for designing an integrated circuit comprising an integrated circuit physical design, wherein the integrated circuit physical design comprises a plurality of layers, and wherein each layer in the plurality of layers comprises a number of patterns, the method comprising: establishing a preferred diagonal direction for patterns on a designated layer in the plurality of layers, wherein the designated layer is for purposes other than interconnections between different standard cells; creating a standard cell physical design of a standard cell circuit element, the standard cell physical design comprising: a plurality of manhattan layers, wherein a majority of patterns on each manhattan layer of the standard cell physical design are manhattan patterns, and the designated layer comprising a plurality of minimum-width patterns, wherein a majority of the minimum-width patterns on the designated layer of the standard cell physical design are in the preferred diagonal direction with respect to the manhattan patterns; and creating the integrated circuit physical design, wherein the integrated circuit physical design comprises: the standard cell physical design, including the minimum-width patterns in the preferred diagonal direction on the designated layer of the standard cell physical design.