Patent ID: 8615771

Claim:
A system, comprising: one or more processors; a memory coupled to said one or more processors, said memory including a computer useable medium tangibly embodying at least one program of instructions executable by said one or more processors to perform operations for managing all read-copy update reader tasks that have been preempted while executing in a read-copy update read-side critical section on some or all of said one or more processors, said operations comprising managing a single blocked-tasks list associated with said some or all of said one or more processors to track said preempted read-copy update reader tasks that are blocking an asynchronous grace period, preempted read-copy update reader tasks that are blocking an expedited grace period, and preempted read-copy update reader tasks that require priority boosting, wherein an expedited grace period forces or simulates a context switch on some or all of said one or more processors to preempt all read-copy update reader tasks.