Patent ID: 7459382

Claim:
A method for fabricating a field effect transistor comprising: forming an extension region into a semiconductor substrate which includes at least a gate electrode stack thereon, the gate electrode stack serving as a mask, the gate electrode stack comprising a reduced thickness silicon gate electrode, an etch stop layer thereupon and a vertical spacer layer further thereupon; forming an intrinsic source/drain region into the semiconductor substrate while using the gate electrode stack and a horizontal spacer layer formed adjacent thereto as a mask; forming a raised source/drain layer upon the semiconductor substrate while using the gate electrode and the spacer layer as a mask, said raised source/drain layer comprising a semiconductor material that is different from the intrinsic source/drain region and wherein a top surface of the raised source/drain layer is higher than a top surface of the reduced thickness gate electrode; stripping the vertical spacer layer from the gate electrode stack while using the etch stop layer as a stop layer, and then further stripping the etch stop layer to expose the reduced thickness silicon gate electrode; reacting the exposed reduced thickness silicon gate electrode with a metal silicide forming metal to form a silicide gate electrode; and forming a silicide layer upon the raised source/drain layer.