Patent ID: 8867280

Claim:
A 3D stacked NAND flash memory array comprising: a plurality of active lines formed at regular intervals in a first horizontal direction with a plurality of semiconductor layers vertically stacked having insulating films between upper and lower layers on a substrate; a plurality of word lines formed at regular intervals in a second horizontal direction to be vertically aligned to each of the active lines and to pass by the plurality of semiconductor layers with insulating layers including a charge storage layer between each of the world lines and the semiconductor layers; and a plurality of string selection lines formed at regular intervals in the second horizontal direction to be parallel to each of the word lines on one side of the plurality of word lines and to pass by the plurality of semiconductor layers with insulating layers including a charge storage layer between each of the string selection lines and the semiconductor layers, wherein each of the string selection lines forms a plurality of string selection transistors vertically stacked passing by the plurality of semiconductor layers, wherein the plurality of string selection transistors vertically stacked have three or more different threshold voltages to be increased or decreased toward the lower ones by programming the charge storage layer interlaid between each of the string selection lines and the semiconductor layers, and wherein the different threshold voltages are reversely increased or decreased toward the lower ones between adjacently and vertically stacked string selection transistors among the plurality of string selection transistors.