Patent ID: 7868422

Claim:
A laterally-diffused MOS (LDMOS) transistor with a high voltage isolation structure, comprising: an N-type buried layer (NBL) formed on a semiconductor substrate; an isolation ring formed on the NBL; an EPI layer formed on the NBL and surrounded by the isolation ring, the EPI layer further comprises: a first P-type epitaxial region and a second P-type epitaxial region, both formed on the NBL; and an N-type epitaxial region formed between the first and second P-type epitaxial regions; a first P-well formed on the first P-type epitaxial region; a second P-well formed on the second P-type epitaxial region; an N-well formed on the N-type epitaxial region, wherein the N-type epitaxial region is in direct contact with the NBL and the N-well for preventing a leakage current from flowing between the first and second P-wells; and a gate dielectric layer formed on the N-well, and a gate structure atop the gate dielectric layer, wherein the EPI layer has a predetermined thickness for preventing a punch-through between the P-wells and the substrate.