Patent ID: 8436356

Claim:
A method for fabricating a thin film transistor substrate comprising steps of: forming a substrate comprising a plurality of grooves having different depths, respectively, to have a multi-step structure, wherein the substrate comprises first to fourth grooves having different heights, respectively, and a first horizontal surface of the substrate is exposed by the first groove and a second horizontal surface of the substrate is exposed by the second groove having a lower depth than the first groove and a third horizontal surface of the substrate is exposed by the third groove having a lower depth than the second groove and a fourth horizontal surface of the substrate is exposed by the fourth groove having a lower depth than the third groove; and forming gate and data lines, alternatively crossed to form a plurality of pixel areas, and thin film transistors, formed in cross portions of the gate and data lines, in the grooves of the substrate; wherein active layers of the thin transistor are formed along the gate lines and gate electrodes, the active layers separated from active layers of neighboring pixel areas having the data line located therebetween; wherein the step of forming the gate and data lines and the thin film transistors in the grooves of the substrate comprises steps of: forming the gate lines and gate electrodes of the thin film transistors on the first and second horizontal surfaces and on side surfaces located between each two of the first to third horizontal surfaces, using first etch resist patterns; forming a gate insulator layer on a front surface of the substrate; forming the active layers on the second horizontal surface of the substrate and on the gate insulator layer corresponding to a side surface located between the second and third horizontal surfaces, the active layers overlapped with the gate electrodes with the gate insulator layer located there between to form channels between the source and drain electrodes; and forming source electrodes, drain electrodes and data lines on the third and fourth horizontal surfaces of the substrate and one side surfaces located between each two of the second to fourth horizontal surfaces; and wherein the step of forming the active layers comprises steps of: forming a second etch resist pattern on the first horizontal surface of the substrate having the gate insulator layer formed thereon; forming first and second silicon layers on the substrate having the second etch resist pattern formed thereon; removing the second etch resist pattern, the first and second silicon layers on the second etch resist pattern in a lift-off process; forming a third etch resist pattern to cover the first and second horizontal surfaces and the side surface located between each two of the first to third horizontal surfaces; and forming the active layers and an ohmic contact layer on the active layers by etching the first and second silicon layers, using the third etch resist pattern as mask.