Patent ID: 8492257

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a plurality of first active pillars by etching a substrate using a pad layer as an etch barrier; forming a plurality of gate conductive layers surrounding sidewalls of the first active pillars and the pad layer; forming a plurality of word lines buried between the gate conductive layers to connect the adjacent gate conductive layers; removing the pad layer; forming a plurality of vertical gates by etching upper portions of the gate conductive layers to partially expose sidewalls of the word lines; forming an etch barrier layer over a resulting structure including the vertical gates; forming an interlayer dielectric layer over the etch barrier layer; forming a plurality of contact holes by etching the interlayer dielectric layer, where the etching stops at the etch barrier layer; etching the etch barrier layer under the contact holes to expose surfaces of the first active pillars; and forming a plurality of second active pillars over the exposed first active pillars.