Patent ID: 7380066

Claim:
A method of prefetching for store streams in a processor, comprising: identifying a store data stream without consulting a cache miss queue, wherein the store data stream comprises a sequence of memory addresses, which reference two or more contiguous cache, lines; determining a depth associated with the store data stream based upon prefetch factors including the number of concurrent data streams and data consumption rates associated with the concurrent data streams; determining whether to allocate a new entry in a prefetch request queue by comparing entries in the prefetch request queue to a multiple cache line address window derived from an address associated with a current store instruction; in response to determining that one of the entries in the prefetch request queue includes an address within the address window, suppressing allocation of a new entry in the prefetch request queue and servicing the entry that includes the address within the address window; and in response to determining that none of the entries in prefetch request queue includes an address within the address window, allocating an entry in the prefetch request queue indicative of a new data stream corresponding to the store instruction to reflect the determined depth of the store data stream.