Patent ID: 6951709

Claim:
A method of fabricating a semiconductor multilevel interconnect structure, said method comprising: forming a first layer comprising a first intermetal dielectric layer and a metal portion; depositing on said first layer a first protective layer; depositing on said first protective layer a second intermetal dielectric layer; depositing on said second intermetal dielectric layer a second protective layer; depositing on said second protective layer a layer of amorphous carbon as a first hardmask layer; depositing on said amorphous carbon layer a second hardmask layer; depositing on said second hardmask layer a first layer of photoresist; forming a first portion of a via by etching said second hardmask layer; forming a second portion of said via by etching the amorphous carbon layer and thereby removing the first layer of photoresist; depositing on said etched second hardmask layer a second layer of photoresist; forming a first portion of a trench by etching said etched second hardmask layer; forming a third portion of said via by etching the second protective layer and the second intermetal dielectric layer; forming a second portion of said trench by etching the etched amorphous carbon layer; forming a third portion of said trench by etching the etched second protective layer and the etched second intermetal dielectric layer and thereby removing all of the etched second hardmask layer; removing said etched amorphous carbon layer; and removing said etched second protective layer, and said first protective layer from above the metal portion.