Patent ID: 8884431

Claim:
A packaged semiconductor device, comprising; a redistribution layer (RDL), the RDL comprising: a first surface; a second surface opposite the first surface; and a plurality of interlayer dielectrics (ILDs) each having a respective one of a plurality of first metallization layers disposed therein, a topmost ILD of the plurality of ILDs disposed at the first surface of the RDL and a bottommost ILD of the plurality of ILDs disposed at the second surface of the RDL, inner ILDs of the plurality of ILDs disposed between the topmost ILD and the bottommost ILD, each of the inner ILDs directly adjacent to two other ILDs of the plurality of ILDs; at least one first integrated circuit mounted on the first metallization layer disposed in the topmost ILD and coupled to the first surface of the RDL; a plurality of metal bumps coupled to first regions of the second surface of the RDL, the second surface of the RDL having a top surface of a topmost ILD with exposed second regions; a first molding compound disposed over the at least one first integrated circuit and the first surface of the RDL; traces in a second metallization layer and disposed directly on a top surface of the first molding compound, the traces electrically coupled to at least one of the RDL and the first integrated circuit by a plurality of connections disposed in the first molding compound; at least one second integrated circuit mounted on the traces, the at least one second integrated circuit being electrically coupled to the RDL through the traces; and a second molding compound disposed over the at least one second integrated circuit and contacting the first molding compound.