Patent ID: 8407627

Claim:
A computer implemented method for performing a metrology operation on a lithography photomask which comprises a plurality of mask features for fabricating an electronic circuit or on a semiconductor substrate which comprises a plurality of circuit features of the electronic circuit, comprising: using a processor to perform a process, the process comprising: generating design data; using context information from the design data to perform the metrology operation on the plurality of mask features of the lithography photomask or on the plurality of circuit features of the semiconductor substrate by at least assigning priorities to at least some of a plurality of features corresponding to the plurality of mask features or the plurality of circuit features, wherein the action of using the context information comprises at least an action of identifying, to one or more of the plurality of features, information relating to at least some features of the plurality of features that are intended to be produced from the plurality of features as defined in the design data; and the context information is used to determine sensitivity of the metrology operation, the context information is used to determine an order in which the metrology operation is to be performed on the plurality of features by identifying, from the plurality of features, a higher priority feature associated with a higher priority upon which the metrology operation is to be performed before the metrology operation is to be performed upon a lower priority feature associated with a lower priority, and the metrology operation is to be performed on both the higher priority feature and the lower priority feature in the order that is determined by using at least the context information obtained from the design data.