Patent ID: 7226854

Claim:
A method of forming metal lines in a semiconductor device, the method comprising: forming lower metal lines and forming an insulation layer on the lower metal lines; partially etching said insulation layer to a depth which upper metal lines are to be formed; depositing a material for the upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines; exposing the lower metal lines by forming a photoresist pattern on the entire surface of the resultant structure, performing a dry etching process on the upper metal lines and said insulation layer using an etchant having about 1:1 selectivity between said upper metal line and said insulation layer until said lower metal lines are exposed to form contact holes through said upper metal lines and the insulation layer, and removing said photoresist pattern; and depositing a material for contact plugs on entire exposed surfaces of said upper metal lines, said insulation layer, and said contact holes, and planarizing the material for said contact plugs to form the contact plugs, wherein the material for contact plugs is deposited in the contact hole while the upper surfaces of the upper metal lines are completely exposed, thereby placing the material for the contact plugs in contact with exposed surfaces of said upper metal lines and said insulation layer, and forming an electrical connection between the lower and the upper metal lines via the contact plugs.