Patent ID: 7145344

Claim:
A method of monitoring a manufacturing process for a plurality of programmable logic devices (PLDs) of a PLD type, each of the PLDs including a first collection of interconnect resources occupying a first conductive layer and a second collection of interconnect resources occupying a second conductive layer, the method comprising: for each of the PLDs: instantiating a number of test circuits on the PLD, the test circuits including test-circuit interconnect resources selected from the first and second collections of interconnect resources; activating the test circuits to pass signals through the test-circuit interconnect resources; monitoring the activated test circuits to identify failed test circuits; and for each of the failed test circuits, storing data representative of the test-circuit interconnect resources of the failed test circuit, the data differentiating the test-circuit interconnect resources selected from the first collection of interconnect resources from the test-circuit interconnect resources selected from the second collection of interconnect resources; and calculating the probability of failures in the first conductive layer using the stored data of a plurality of the failed test circuits identified during the monitoring of the activated test circuits.