Patent ID: 8461934

Claim:
An integrated circuit configured to receive an external-clock signal or generate an internal-clock signal, the integrated circuit comprising: a first pad and a second pad, wherein: the first pad is configured to receive the external-clock signal from an external oscillator, the first pad and the second pad are configured to be coupled to a crystal oscillator and each receive a reference-clock signal from the crystal oscillator, and the second pad is configured to be grounded; an internal oscillator configured to generate the internal-clock signal; a crystal-oscillator detector coupled to the second pad, wherein the crystal-oscillator detector includes a transistor having a gate coupled to the second pad and the transistor is configured to pull a first source-drain region of the transistor to a first state if the second pad receives the reference-clock signal or allow the first source-drain region to be pulled to a second state if the second pad is grounded, wherein the first state and the second state are different states; and a buffer configured to transfer the first state to the internal oscillator for keeping the internal oscillator enabled and transfer the second state to the internal oscillator for disabling the internal oscillator.