Patent ID: 8200948

Claim:
A data processing apparatus comprising: a register data store having a plurality of registers for storing data; processing logic circuitry configured to perform a sequence of operations on data including at least one re-arrangement operation, the processing logic circuitry comprising scalar processing logic circuitry configured to perform scalar operations and SIMD (single instruction multiple data) processing logic circuitry configured to performer SIMD operations; the SIMD processing logic circuitry is configured to be responsive to a re-arrangement instruction specifying a family of re-arrangement operations to perform a selected re-arrangement operation from that family on a plurality of data elements constituted by data in one or more of said registers identified by the re-arrangement instruction, the selected re-arrangement operation being dependent on at least one parameter provided by the scalar processing logic circuitry, the at least one parameter identifying a data element width for the data elements on which the selected re-arrangement operation is performed.