Patent ID: 7418626

Claim:
An information processing apparatus comprising: a first computer module which includes a first controller and a second computer module which includes a second controller, wherein: said first computer module includes a first processor, a first main-memory and a first sub-memory; said second computer module includes a second processor, a second main-memory and a second sub-memory; said first processor and said second processor operate substantially simultaneously and are substantially synchronized with each other; said first controller writes data to said first main-memory and said second sub-memory according to a first write request of said first processor, and at the substantially same time, said second controller writes data to said second main-memory and said first sub-memory according to a second write request of said second processor; wherein: said first and second write requests are associated with the same data; said first controller controls so that while said first processor and said second processor are synchronized, read access from said first processor is carried out as against said first main-memory and write access from said first processor is carried out as against said first main-memory and said second sub-memory and write access from said second processor is carried out as against said first sub-memory, and said first controller controls so that, when said first processor fails to be in synchronism with said second processor, read access from said first processor is carried out as against said first sub-memory and write access from said first processor is carried out as against said first main-memory, said first sub-memory and said second sub-memory; and said first controller copies the contents of said first sub-memory to said first main-memory when said first processor fails to be in synchronism with said second processor.