Patent ID: 7146547

Claim:
A semiconductor device, comprising: a memory; a normal operation path on an input side, formed by a flip-flop on an input side and a combination circuit on the input side with respect to the memory; a normal operation path on an output side, formed by a combination circuit on an output side and a flip-flop on the output side with respect to the memory; a memory BIST circuit with respect to the memory; a first selection circuit which selects either the normal operation path on the input side or the input path from the memory BIST circuit, and connects the resulting path to the input of the memory; a control-use flip-flop which supplies a scanning-use test pattern to the normal operation path on the output side at a time of a scanning test; a second selection circuit which selects either the output of the memory or the output of the control-use flip-flop, and connects the resulting output to the normal operation path on the output side and the input of the memory BIST circuit; and a third selection circuit which selects one of the output of the first selection circuit and the output of the memory, wherein the output of the third selection circuit is connected to the input of the control-use flip-flop so that the control-use flip-flop is formed into a control, observing and pipeline shared-use flip-flop that is also used as both an observing-use flip-flop and a pipeline-use flip-flop.