Patent ID: 8462283

Claim:
A pixel structure, disposed on a substrate having a first sub-pixel region, a second sub-pixel region and a third sub-pixel region, the pixel structure comprising: at least one first sub-pixel electrode, at least one second sub-pixel electrode and at least one third sub-pixel electrode, respectively disposed on the substrate in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region, the second sub-pixel electrode being disposed between the first sub-pixel electrode and the third sub-pixel electrode; at least one common line, disposed on the substrate and passing through the first sub-pixel region, the second sub-pixel region and the third sub-pixel region, the common line overlapping and being coupled with the first sub-pixel electrode to form at least one first storage capacitor, the common line overlapping and being coupled with the second sub-pixel electrode to form at least one second storage capacitor, and the common line overlapping and being coupled with the third sub-pixel electrode to form at least one third storage capacitor, wherein the second storage capacitor is larger than the first storage capacitor and the third storage capacitor; at least one first transistor, at least one second transistor and at least one third transistor, disposed on the substrate, the first transistor being electrically connected to the first sub-pixel electrode, the second transistor being electrically connected to the second sub-pixel electrode, the third transistor being electrically connected to the third sub-pixel electrode, the first transistor having a first adjusting capacitor, the second transistor having a second adjusting capacitor, and the third transistor having a third adjusting capacitor, wherein the first adjusting capacitor is larger than the second adjusting capacitor and the third adjusting capacitor is larger than the second adjusting capacitor; and a scan line, disposed on the substrate and substantially passing through the first sub-pixel region, the second sub-pixel region and the third sub-pixel region, the scan line being electrically connected to the first transistor, the second transistor and the third transistor.