Patent ID: 7024524

Claim:
A semiconductor storage comprising first and second memory cell arrays, said first memory cell array including: a plurality of first memory cells arranged in at least one column over a plurality of rows; and a plurality of first word lines to be connected to said first memory cells on a row unit, said second memory cell array including: a plurality of second memory cells arranged in a matrix, said second memory cells including a different number of elements than said first memory cells; a plurality of second word lines to be connected to said second memory cells on a row unit; a plurality of third word lines connected to said second memory cells on a row unit and not connected to any of said plurality of first memory cells; a plurality of first bit lines provided corresponding to said second memory cells on a column unit and being accessible to said second memory cell connected to said second word line in a selection state out of said plurality of second word lines; and a plurality of second bit lines provided corresponding to said second memory cells on a column unit and being accessible to said second memory cell connected to said third word line in a selection state out of said plurality of third word lines, said semiconductor storage further comprising: a first row decoder configured to select, so that a period wherein any of said first word lines is brought into a selection state based on a first address signal and a period wherein any of said second word lines is brought into a selection state based on said first address signal are overlapped.