Patent ID: 7719323

Claim:
A signal receiver circuit in a semiconductor integrated circuit comprising: a first level detecting unit configured to offset-control a first output node in response to a pair of first reference signals and a power down signal; and a second level detecting unit configured to offset-control a second output node in response to a pair of second reference signals and the power down signal, wherein the first level detecting unit comprises: a signal processor configured to respond to a clock and control the voltage level of the first output node corresponding to the voltage levels of the first and second nodes; a first input unit configured to control the voltage level of the first node in response to a main input signal of the pair of input signals; a second input unit configured to control the voltage level of the second node in response to a sub-input signal of the pair of input signals; a controller configured to control the first input unit and the second input unit in response to the clock and the power down signal a first offset unit configured to control the voltage level of the first node in response to a main reference signal of the pair of the first reference signals; and a second offset unit configured to control the voltage level of the second node in response to a sub-reference signal of the pair of the first reference signals.