Patent ID: 7186484

Claim:
A method for determining the relative positional accuracy of two structure elements imaged onto a wafer from a respective mask, the method comprising: providing the wafer with a substrate, on which a conductive layer and a resist are arranged: projecting a first structure element from a first mask, thereby exposing the resist in a first patch; developing and transferring the patch into the conductive layer, thereby forming an electrically conductive structure; removing the first resist and applying a second resist; projecting a second structure element from a second mask to expose the resist in a second patch above the electrically conductive structure with an offset with respect to the electrically conductive structure, said offset being dependent on an imaging error; developing and transferring the second patch into the conductive layer, thereby removing a portion of the electrically conductive structure, a size of the removed portion representing a size of the offset; carrying out an electrical measurement of the line width at the electrically conductive structure; and calculating the offset from the result of the electrical measurement of the line width in order to determine positional accuracy.