Patent ID: 7935543

Claim:
A method of manufacturing an integrated circuit, comprising: forming a first contact plug over a substrate; forming a FeRAM capacitor stack over the first contact plug, including: forming a bottom electrode layer over the first contact plug; forming a PZT ferroelectric core over the bottom electrode layer; and forming a top electrode layer over the PZT ferroelectric core; and forming a second contact plug over the top electrode layer; wherein the first and second contact plugs comprise materials having coefficients of thermal expansion larger than a coefficient of thermal expansion of the PZT ferromagnetic core; the first and second contact plugs have areas perpendicular to a stack axis that are about the same as or greater than a corresponding area of the PZT ferroelectric core; the first and second contact plugs are deposited at temperatures at least about 50° C. above a Curie temperature of the PZT ferromagnetic core; and the stack is cooled using a temperature program that cools the stack past the Curie temperature and, after dropping to the Curie temperature, keeps the stack within about 100° C. of the Curie temperature for at least about 40 minutes.