Patent ID: 8067807

Claim:
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a first principal surface and a second principal surface; (b) a first MISFET group formed at the first principal surface; and (c) a second MISFET group formed at the first principal surface, and being lower in breakdown voltage than the first MISFET group, wherein each MISFET belonging to the first MISFET group includes (i) a first source region and a first drain region which are formed in a surface region of the first principal surface to oppose each other with a first channel region being interposed therebetween; (ii) a first gate insulating film deposited by CVD over the first principal surface so as to cover the first channel region, and to reach a surface portion of a first field insulating film around an entire periphery of the first channel region; (iii) a first gate electrode film formed over the first gate insulating film so as to cover the first channel region, and to reach an outside of the region covered with the first gate insulating film; and (iv) a first gate contact portion provided over the first gate electrode film outside the region covered with the first gate insulating film, wherein an end portion of the first gate insulating film is disposed over the first field insulating film around an entire periphery thereof.