Patent ID: 6967873

Claim:
A method of erasing a flash electrically erasable programmable read only memory (EEPROM) device which includes a plurality of memory cells each having a charge storing layer including at least a first charge storing cell and a second charge storing cell, the charge storing layer being disposed between a top dielectric layer and a bottom dielectric layer, and a gate electrode disposed above the top dielectric layer, the bottom dielectric layer disposed above a substrate having a first conductive region adjacent the first charge storing cell and a second conductive region adjacent the second charge storing cell, said method comprising: (a) applying an erase pulse to the plurality of memory cells; (b) erase verifying the plurality of memory cells to determine if there are any undererased memory cells in the plurality of memory cells; and (c) applying a positive gate stress to the plurality of memory cells to reduce the amount of positive charge within the charge storing layer.