Patent ID: 8054667

Claim:
A multilevel one-time programmable memory device including a plurality of memory cells, wherein each of the plurality of memory cells comprises: a first electrode to which a first voltage is applied; a second electrode to which a second voltage is applied; and a first fuse line, a second fuse line and a third fuse line performing a fusing operation according to a voltage difference between the first electrode and the second electrode, wherein the first fuse line, the second fuse line and the third fuse line are connected to each other in parallel between the first electrode and the second electrode in a multilayer structure, and wherein the first fuse line, the second fuse line and the third fuse line have different resistances from each other, and wherein the multilayer structure of each of the memory cells comprises: a first insulation layer formed on a substrate and the third fuse line formed on the first insulation layer, a second insulation layer formed on the third fuse line, the second fuse line formed on the second insulation layer, a third insulation layer formed on the second fuse line, and the first fuse line formed on the third insulation layer, and wherein the second electrode is foamed on the first insulation layer and the first electrode is formed on the substrate.