Patent ID: 7564717

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells each having a charge storage layer and a control gate formed on an inter-gate insulating film on the charge storage layer are arranged in a matrix; word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array; a row decoder which selects a word line, and applies a voltage to the selected word line; and a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage, the voltage generator including: a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal; a constant current circuit which generates a first control signal in accordance with the comparison result signal output from the comparator; a first delay circuit which generates a second control signal by delaying the comparison result signal output from the comparator; and a charge pump circuit which generates the boosted voltage in response to the first control signal and the second control signal.