Patent ID: 7378712

Claim:
A semiconductor structure, comprising: (a) a semiconductor region; (b) a gate stack on top of the semiconductor region, the gate stack including (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region, the second gate polysilicon region being doped; (c) a dielectric spacer layer in direct physical contact with the semiconductor region, the gate dielectric region, and the first and second gate polysilicon regions, wherein a reference direction is defined as being perpendicular to a first common interfacing surface of the first gate polysilicon region and the dielectric spacer layer and being parallel to a second common interfacing surface of the gate dielectric region and the semiconductor region, wherein a first thickness in the reference direction of the dielectric spacer layer measured through a first point of the dielectric spacer layer is less than a second thickness in the reference direction of the dielectric spacer layer measured through a second point of the dielectric spacer layer, wherein a first straight line goes through both the first point of the dielectric spacer layer and a third point inside the first gate polysilicon region and is parallel to the reference direction, and wherein a second straight line goes through both the second point of the dielectric spacer layer and a fourth point inside the second gate polysilicon region and is parallel to the reference direction.