Patent ID: 8638284

Claim:
A gate signal line driving circuit which applies a HIGH voltage drive signal to a gate signal line during a signal HIGH period, and applies a LOW voltage drive signal to the gate signal line during a signal LOW period which is a period other than the signal HIGH period, comprising: a plurality of LOW voltage applying switching elements which are connected in parallel with respect to the gate signal line, and which apply the LOW voltage drive signal to the gate signal line in an ON state respectively; and a plurality of AC voltage lines, each of the plurality of AC voltage lines being directly connected with a source/drain terminal of one of the plurality of LOW voltage applying switching elements and each supplying a HIGH voltage and a LOW voltage periodically and alternately to the source/drain terminal of the one of the plurality of LOW voltage applying switching elements, wherein: at least one of the plurality of LOW voltage applying switching elements is brought into an ON state in response to the signal LOW period and at least one of the plurality of AC voltage lines being connected with the at least one of the plurality of LOW voltage applying switching elements is the LOW voltage; and at least one of the plurality of LOW voltage applying switching elements is brought into an OFF state within the signal LOW period.