Patent ID: 6928634

Claim:
A method for improving the manufacturability of objects to be created on a semiconductor wafer, comprising: receiving a target layer that defines a number of objects to be lithographically created on a semiconductor wafer, each object having a number of edges and two or more objectives for each edge that can be optimized wherein the two or more objectives for each edge include edge placement error (EPE) and slope; creating a mask layout for one or more masks to be used in creating the objects on the wafer, the mask layout having a number of fragments some of which correspond to the edges to be created on the wafer; performing a simulation of the mask layout to predict how the edges will be created on the wafer; determining relationships that predict how movement of the fragments in the mask layout will affect the two or more objectives of a number of edges to be created on the wafer wherein the relationships are gradient matrices that estimate the change in EPE and slope of edges versus a change in position of a fragment in the mask layout; and selecting an objective for each edge to optimize using a defined tolerance, and using the relationships to determine how one or more fragments should be moved in the mask layout to optimize the selected objective of each edge.