Patent ID: 7867858

Claim:
A method for making an integrated circuit using a semiconductor substrate and for operating the integrated circuit, comprising: forming a first transistor by: forming a first gate over a first region of the substrate and on first gate dielectric having a first thickness; and implanting a first source/drain dopant into the first region using the first gate as a mask while masking the first region; forming a second transistor by: forming a second gate over a second region of the substrate and on a second gate dielectric having a second thickness; and implanting the first source/drain dopant into the second region using the second gate as mask while implanting the first source/drain dopant into the first region; forming a third transistor by: forming a third gate over a third region of the substrate and on a third gate dielectric having the second thickness; and implanting a second source/drain dopant into the third region using the third gate as mask and while masking the first and second regions; forming a logic circuit using the first transistor having a connection for coupling to a first power supply terminal; using the second transistor to couple the logic circuit to the first power supply terminal during a power-up mode of the integrated circuit and decouple the logic circuit from the first power supply terminal during a power-down mode of the integrated circuit; and using the third transistor to interface externally to the integrated circuit.