Patent ID: 8497511

Claim:
An array substrate, comprising: a substrate; a plurality of scan lines disposed on the substrate in a first direction; and a plurality of data lines disposed on the substrate in a second direction, the data lines being electrically insulated and intersected with the scan lines thereby defining a plurality of pixel structures, the first and second directions being mutually perpendicular, and each the pixel structure comprising: a first thin film transistor disposed on the substrate and comprising: a first gate connected to the corresponding scan line; a first source disposed above the first gate and partially overlapping the first gate, one end of the first source being connected to the corresponding data line; and a first drain disposed above the first gate and comprising at least one first concavity, and a portion of the first source being disposed in the at least one first concavity; a second thin film transistor disposed on the substrate and comprising: a second gate connected to the corresponding scan line; a second source disposed above the second gate and connected to the first drain, the second source comprising at least one second concavity; and a second drain disposed above the second gate and partially overlapping the second gate, and a portion of the second drain being disposed in the at least one second concavity; and a pixel electrode connected to the second drain.