Patent ID: 8732227

Claim:
A method for implementing a characteristic-2-multiplication of at least two input bit strings each having a number N of bits by means of a processor unit suitable for carrying out an integer multiplication, comprising the following steps: a) masking of the respective input bit string with at least two different masks by a respective bitwise AND operation of the respective input bit string with the respective mask in order to generate at least two first intermediate bit strings for the respective input bit string, wherein the respective first intermediate bit string has no adjacent one-bits; b) linking the at least two first intermediate bit strings by the integer multiplication of the processor unit for generating at least one second intermediate bit string; and c) transforming the at least one second intermediate bit string by means of a second transformation for generating a result bit string; wherein the respective sequence with a number K of zero bits in each case forms a mask window in the respective predetermined mask with a number N of bits, wherein K fulfills the following condition: ⌊ log 2 ⁢ ⌈ N K + 1 ⌉ ⌋ ≤ K .