Patent ID: 8325175

Claim:
A liquid crystal display device, comprising: a gate high voltage generating circuit for generating a gate high voltage by using n pumping units and supplying the gate high voltage through an output line, where n is a natural number greater than unity; a voltage stabilizing unit for generating a gate high voltage within a range of a highest preset value by using an output voltage of the (n−1)th pumping unit in a case the gate high voltage generated at the gate high voltage generating circuit exceeds the highest preset value; and a gate voltage modulating circuit for modulating the gate high voltage within the range of the highest preset value in response to a gate modulating control signal to provide a modulated gate high voltage even in a case in which a data enable signal is not normal, which is identical to a case in which the data enable signal is normal, wherein a high state and a low state of the gate modulating control signal alternates repeatedly, regardless of whether the data enable signal is normal or not, and wherein the gate high voltage generating circuit comprises: first and second diodes connected in series, first and second capacitors connected between an input terminal of a pulse signal and a node between the first and second diodes in series, third and fourth diodes connected between the output line and a cathode terminal of the second diode in series, a third capacitor comprising: one terminal commonly connected to an anode terminal of the first diode and an analog driving voltage, and another terminal commonly connected to an anode terminal of the third diode and the voltage stabilizing unit, fourth and fifth capacitors connected between the input terminal of the pulse signal and a node between the third and fourth diodes in series, a sixth capacitor comprising: one terminal commonly connected to the cathode terminal of the second diode and the anode terminal of the third diode, and another terminal commonly connected to the cathode terminal of the fourth diode and the output line, and a seventh capacitor connected between the one terminal of the third capacitor and the other terminal of the sixth capacitor.