Patent ID: 8095744

Claim:
A memory access device for controlling access of a plurality of masters to a shared memory, the shared memory having a plurality of banks, each of the plurality of banks having a plurality of pages, the device comprising: a plurality of command division sections provided for the plurality of masters; a plurality of inter-master arbitration sections provided for the plurality of banks; and a memory control section, wherein each of the plurality of command division sections divides a command issued by the corresponding master into a plurality of micro-commands when an access region of the command is over two or more banks among the plurality of banks, each of the plurality of micro-commands being a command accessing only one of the two or more banks, and sends each of the micro-commands to an inter-master arbitration section corresponding to the bank including an access region of the micro-command, each of the plurality of inter-master arbitration sections arbitrates micro-commands given from the plurality of command division sections to select one of the micro-commands, and the memory control section selects one of the plurality of micro-commands selected by the plurality of inter-master arbitration sections to perform memory access.