Patent ID: 8040340

Claim:
A control circuit for a start-up circuit that induces current flow in a bandgap circuit during a start-up phase, comprising: a comparator configured to pass a power supply to the start-up circuit according to an internal node of the bandgap circuit after the start-up phase, the comparator comprising: a first PMOS transistor having a gate connected to a first node of the bandgap circuit, and a source connected to a positive power supply; a first branch including serial-connected second PMOS transistor and third NMOS transistor, wherein a source of the second PMOS transistor is connected to a drain of the first PMOS transistor, and a source of the third NMOS transistor is connected to a base power supply; and a second branch including serial-connected fourth PMOS transistor and fifth NMOS transistor, wherein a source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor, and a source of the fifth NMOS transistor is connected to the base power supply; wherein a gate of the third NMOS transistor is connected to a drain of the fifth NMOS transistor, and a gate of the fifth NMOS transistor is connected, to a drain of the third NMOS transistor; and an activating circuit for activating the comparator to obtain the power supply at an, output earlier than another output node of the comparator, the activating circuit comprising: a serial-connected sixth PMOS transistor and seventh NMOS transistor, an interconnected node between the sixth PMOS transistor and the seventh NMOS transistor being connected to a gate of the second PMOS transistor, wherein a gate of the sixth PMOS transistor is connected to the first node of the bandgap circuit, and a gate of the seventh NMOS transistor is connected to a second node of the bandgap circuit; and a serial-connected eighth PMOS transistor and ninth NMOS transistor, an interconnected node between the eighth PMOS transistor and the ninth NMOS transistor being connected to a gate of the fourth PMOS transistor, wherein a gate of the eighth PMOS transistor is connected to the first node of the bandgap circuit, and a gate of the ninth NMOS transistor is connected to the second node of the bandgap circuit; wherein the first node of the bandgap circuit reaches a specified low-level voltage and the second node of the bandgap circuit reaches a specified high-level voltage higher than the low-level voltage after the start-up phase; and wherein the seventh NMOS transistor and the ninth NMOS transistor are asymmetrical such that the gate of the second PMOS transistor obtains the power supply earlier than the gate of the fourth PMOS transistor does; wherein the passed power supply shuts down the start-up circuit after the start-up phase such that an output of the start-up circuit is electrically disconnected from the bandgap circuit that generates a fixed reference voltage.