Patent ID: 8357552

Claim:
A method for manufacturing a light emitting diode chip, comprising the steps of: providing a substrate; forming an epitaxial layer structure on the substrate, the epitaxial layer structure including a first type semiconductor layer different in material composition from the substrate formed on an upper surface of the substrate, a second type semiconductor layer disposed above the first type semiconductor layer, and a light emitting layer sandwiched between the first and second type semiconductor layers; etching the epitaxial layer structure to expose portions of said upper surface of the substrate and to form epitaxial layer units, each epitaxial layer unit being formed with inclined sidewalls extending in inclined fashion downwardly and outwardly at opposite sides of said each epitaxial layer unit; etching the upper surface of said substrate at said exposed portions thereof to form substrate cavities extending in said substrate, where each of said substrate cavities has at least one substrate inclined wall extending in said substrate; forming two electrode units, each on a respective one of said inclined walls of said each epitaxial layer unit, said each electrode unit including an electrode disposed on and connected to a respective one of the first and second type semiconductor layers, and a first conductive portion formed simultaneously and integrally with said electrode and extending along a corresponding one of the inclined sidewalls of said each epitaxial layer unit to and along said at least one substrate inclined wall of a respective one of the substrate cavities beyond said epitaxial layer unit; before the step of forming said two electrode units, forming an insulating layer disposed between the first conductive portion of one of the two electrode units connected to the second type semiconductor layer, and a corresponding one of the inclined sidewalls of said each epitaxial layer unit; and polishing a bottom surface of the substrate until the first conductive portions of the two electrode units are exposed at the polished bottom surface.