Patent ID: 8222957

Claim:
A differential amplifying circuit comprising: a first differential transistor pair of PMOS transistors that have gates connected with a non-inversion input and an inversion input, respectively; a first constant current source section configured to supply a first bias current to said first differential transistor pair; a second differential transistor pair of NMOS transistors that have gates connected with said non-inversion input and said inversion input, respectively; a second constant current source section configured to supply a second bias current to said second differential transistor pair; a first current mirror circuit connected with said first differential transistor pair; a second current mirror circuit connected with said second differential transistor pair; a PMOS output transistor connected between a positive power supply line and an output terminal and having a gate connected with an output of said second current mirror circuit; an NMOS output transistor connected between a negative power supply line and said output terminal and having a gate connected with an output of said first current mirror circuit; and a feedback circuit configured to perform a feed-back operation to said first current mirror circuit to restrain reduction of the gate voltage of said NMOS output transistor, and perform a feed-back operation to said second current mirror circuit to restrain increase of the gate voltage of said PMOS output transistor, wherein said first constant current source section is configured to increase said first bias current in response to reduction of a gate voltage of said PMOS output transistor, and said second constant current source section is configured to increase said second bias current in response to increase of a gate voltage of said NMOS output transistor.