Patent ID: 8193067

Claim:
A method of forming an integrated circuit structure, said method comprising: forming, in a mask layer on a substrate, a first pattern and a second pattern, said first pattern being for a first trench of a deep trench isolation structure and said second pattern being for a second trench of a deep trench capacitor; performing an etch process to form, in said substrate, said first trench and said second trench; forming a buried capacitor plate for said deep trench capacitor in said substrate adjacent to a lower portion of said second trench; forming a conformal insulator layer that lines said first trench and said second trench; depositing a layer of conductive material onto said conformal insulator layer to fill said first trench and said second trench level with a top surface of said substrate; forming a conductive strap electrically connecting said conductive material in said second trench to a portion of said substrate adjacent to said second trench, said forming of said conductive strap comprising: removing said conductive material from an upper portion of said second trench only; removing an exposed portion of said conformal insulator layer from said upper portion of said second trench; and depositing an additional layer of said conductive material to re-fill said upper portion of said second trench level with said top surface of said substrate; forming a shallow trench isolation structure above said conductive material in said first trench such that said shallow trench isolation structure in combination with said conformal insulator layer encapsulates said conductive material in said first trench; and forming devices in said substrate such that one of said devices is electrically connected to said conductive material in said second trench.