Patent ID: 7023053

Claim:
A differential transistor pair comprising a first and second transistor, said first and second transistors comprising at least one transistor cell provided in a substrate, the at least one cell comprising: a first and a second drain/collector region belonging to the first transistor of said differential transistor pair and arranged separated from each other, a third drain/collector region belonging to the second transistor of said differential transistor pair, and arranged between said first and second drain/collector regions, a first source/emitter region arranged between said first drain/collector region and said third drain/collector region, and a second source/emitter region arranged between said second drain/collector region and said third drain/collector region, said source/emitter regions being common to both transistors of the differential transistor pair, a first and a second gate/base region belonging to the first transistor of said differential transistor pair, said first gate/base region being arranged between said first drain collector region and the first source/emitter region, and said second gate/base region being arranged between said second drain/collector region and the second source/emitter region, and a third and a fourth gate/base region belonging to the second transistor of said differential transistor pair, said third gate/base region being arranged between said third drain/collector region and the first course/emitter region, and said fourth gate/base region being arranged between said third drain/collector region and the second source/emitter region.