Patent ID: 7555617

Claim:
An electronic data processing device, comprising a data processing member, provided for processing first encoded data, obtained by encoding first data, input by a user and second encoded data, read from a carrier comprising a first memory for storing identification data, said data processing member being provided for controlling, based on said first and second data, a secured operation initiated by said user, said device further comprising a second memory accessible by said processing member, said second memory being configurable in order to delimit at least one secured memory part within said second memory, to each of said secured memory parts there being assigned a dedicated address range, said data processing member comprises N (N≧2) processing units of which M (M≦N−1) processing units are provided to process said secured operation and at least one of the remaining N-M processing units is provided for processing application data related to said operation, to each of said M processing units there is assigned at least one of said secured memory parts, each of said N processing units being each connected to a memory access control member, said second memory being also connected to said memory access control member, which is provided for controlling accesses to said second memory, said memory access control member being provided for storing memory address ranges assigned to said M processing units and for detecting an access request to a protected memory address, belonging to said ranges, when issued by one of said N-M processing units and for overruling a detected access request to said protected memory address, characterised in that each of said processing units being each connected to said memory access control member by means of a dedicated internal bus and in that said memory access control member comprises a configuration element connected to a selected one of said M processing units by means of the internal bus dedicated to said selected processing unit, said configuration element being provided for generating, under control of said selected processing unit, said address ranges indicating said secured memory parts assigned to each of said M processing units, said memory access control member comprises a memory protection member connected via their dedicated internal buses to each of said N-M processing units, said configuration element having an output connected to said memory protection member for supplying generated address ranges.