Patent ID: 8493785

Claim:
A nonvolatile memory device comprising: a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines; a data output line which outputs data read from the memory cell array; a plurality of page buffers which are operatively connected between the memory cell array and the data output line; and a data input line connected to a page buffer among the plurality of page buffers, wherein the data input line is electrically isolated from the data output line, wherein the page buffer comprises a latch circuit configured to store data read from the memory cell array; a first transistor having a gate terminal connected to the latch circuit and a source terminal connected to a ground voltage; and a second transistor having a gate terminal connected to an address line, a source terminal electrically connected to a drain terminal of the first transistor, and a drain terminal connected to the data output line.