Patent ID: 7109536

Claim:
A memory embedded semiconductor device comprising: a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate, wherein the logic transistor comprises: a first gate electrode formed on the semiconductor substrate; first source/drain diffusion layers each formed in the semiconductor substrate; and a first silicide film formed on the first source/drain diffusion layers, wherein the memory transistor comprises: a second gate electrode formed on the semiconductor substrate; second source/drain diffusion layers each formed in the semiconductor substrate; a second silicide film formed on the second source/drain diffusion layers to be thinner than the first silicide film; and a first ion implanted region formed in the second source/drain diffusion layers and beneath the second silicide film, wherein the first ion implanted region suppresses a silicide reaction when the second silicide film is formed, and wherein the first ion implanted region suppressing the silicide reaction is not formed in the first source/drain diffusion layers nor beneath the first silicide film.