Patent ID: 7910477

Claim:
A method of manufacturing an integrated circuit, comprising forming a dual damascene interconnect structure, including: forming an etch-stop layer over a conductive feature formed on a semiconductor substrate; forming a dielectric layer over the etch-stop layer; the dielectric layer comprising a first dielectric layer, a cap layer overlying the first dielectric layer, and an underlayer material layer overlying the cap layer; forming a first resist layer over the dielectric layer; patterning the first resist layer to define a via opening; forming a via cavity by a first etch of the dielectric layer though the via opening, down to the etch-stop layer; removing the patterned first resist layer, following the first etch; forming an organic film over the dielectric layer and within the via cavity; forming a second resist layer over the organic film; patterning the second resist layer to define a trench opening over the via cavity; forming a trench cavity by a second etch of the organic film and dielectric layer through the trench opening, down to the cap layer; removing the patterned second resist layer, following the second etch; following removal of the patterned second resist layer, performing a third etch to extend the trench cavity into the first dielectric layer, removing remaining portions of the underlayer material layer and leaving a remaining portion of the organic film at a bottom of the via cavity; performing an ash operation to remove the remaining portion of the organic film from the via cavity and to remove resist residues from the first and second etches; the ash operation including a first portion performed for a first time until monitoring of a chemical level or an emitted light wavelength indicates that substantially all of at least one of the organic film or resist residues has been removed, and a second portion performed after the first portion and for a second time equal to at least 50% of the first time; following the ash operation, extending the via cavity through the etch-stop layer by a fourth etch to expose the conductive feature; and following the fourth etch, forming a diffusion barrier layer within the via and trench cavities; forming a copper seed layer over the diffusion barrier within the via and trench cavities; and depositing copper fill material over the copper seed layer to fill the via and trench cavities.