Patent ID: 8004346

Claim:
A semiconductor integrated circuit apparatus, comprising: a first first main conductivity MIS transistor with a source connected to a first power supply; a second first main conductivity MIS transistor with a source connected to a drain of the first first main conductivity MIS transistor, a drain connected to a first current source, and a gate connected to a gate of the first first main conductivity MIS transistor and the first current source; a current mirror circuit that has a third first main conductivity MIS transistor with a source connected to the first power supply and that takes a drain potential of the first first main conductivity MIS transistor as a gate potential, and amplifies or attenuates a drain current of the third first main conductivity MIS transistor to a current value of an arbitrary ratio α; and a leakage current detection first main conductivity MIS transistor that takes an output potential of the current mirror circuit as a gate potential, and has a substrate connected to a substrate of a first main conductivity MIS transistor of an internal circuit, wherein: the current mirror circuit satisfies the following equation when the drain current of the third first main conductivity MIS transistor is amplified α times, I L . LSI I L . LCM = W LSI W LCM · W 1 W 2 · 1 α where: I L.LSI is a leakage current of the first main conductivity MIS transistor of the internal circuit; I L.LCM is a leakage current of the leakage current detection first main conductivity MIS transistor; W LSI is a channel width of the first main conductivity MIS transistor of the internal circuit; W LCM is a channel width of the leakage current detection first main conductivity MIS transistor; W 1 is a channel width of the first first main conductivity MIS transistor; W 2 is a channel width of the second first main conductivity MIS transistor; and the first and second first main conductivity MIS transistors operate in a sub-threshold region in such a manner that an absolute value of a difference between a gate potential of the first first main conductivity MIS transistor and the second first main conductivity MIS transistor, and a potential of the first power supply, becomes equal to or smaller than a threshold voltage of the first and second first main conductivity MIS transistors.