Patent ID: 7625798

Claim:
A method of producing a semiconductor memory including a plurality of memory cell transistors formed on a semiconductor substrate, each of said memory cell transistors including a laminated gate formed of a floating gate and a control gate, comprising the steps of: forming a plurality of element separation regions in the semiconductor substrate in a row direction and a column direction for separating the memory cell transistors; forming a gate oxide film on the semiconductor substrate; forming a first conductive layer on the gate oxide film; etching the first conductive layer to form a plurality of slits; forming spacers on sidewall portions of each of the slits; forming a first insulating film on the first conductive layer, the spacers, and the semiconductor substrate; forming a second conductive layer on the first insulating film; etching the first conductive layer, the second conductive layer, and the first insulating film using one single mask to form the laminated gate; implanting a conductive impurity into the semiconductor substrate exposed on both sides of the laminated gate to form a drain/source region; forming an interlayer insulating film; and forming a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate.