Patent ID: 8878186

Claim:
A semiconductor device comprising: a substrate; a semiconductor layer formed above the substrate; a first insulating layer foamed above the semiconductor layer; a first conducting layer formed above the first insulating layer; a second insulating layer formed above the first conducting layer; a second conducting layer formed above the second insulating layer; a third insulating layer formed above the second conducting layer; a third conducting layer formed above the third insulating layer; a gate line; and a source line provided crossing the gate line; wherein the semiconductor layer includes at least a channel region and a contact region, the first insulating layer has a first contact hole formed at a position which overlaps with the contact region, the first contact hole connecting a pattern for the second conducting layer or a pattern for the third conducting layer and the contact region of the semiconductor layer, a pattern for the first conducting layer is disposed at a position which overlaps with at least the channel region, the second insulating layer has: a second contact hole formed connected to the first contact hole, the second contact hole connecting the pattern for the second conducting layer and the contact region of the semiconductor layer or the pattern for the third conducting layer and the contact region of the semiconductor layer; and a third contact hole formed at a position which overlaps with the pattern for the first conducting layer, the third contact hole connecting the pattern for the second conducting layer and the pattern for the first conducting layer or the pattern for the third conducting layer and the pattern for the first conducting layer, the third insulating layer has a fourth contact hole, the gate line is formed in one of the second conducting layer and the third conducting layer, and connected to the pattern for the first conducting layer through at least the third contact hole, the source line is formed in the other of the second conducting layer and the third conducting layer, and connected to the contact region through any of the first to fourth contact holes, and the first conducting layer or the semiconductor layer includes a height-adjustment layer formed at a position which overlaps with the fourth contact hole.