Patent ID: 8140768

Claim:
In data processing system comprising a processor, and a memory subsystem with at least one cache and a memory configured with memory pages for storing data, a method comprising: issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem, wherein the prefetch request has a first real address corresponding to a memory location within a first memory page; determining when a next prefetch request of the first prefetch stream targets a next real address that crosses a page boundary of the first memory page, wherein the next prefetch targets data on a next sequential memory page; moving the first prefetch stream from an active streams table to a second table, wherein prefetch streams are scheduled to be issued when within the active streams table and are not scheduled when in the second table; and in response to an effective address of a subsequent memory access instruction being equal to a next effective address corresponding to the next real address, automatically reinserting the first prefetch stream into the active streams table from the second table.