Patent ID: 8483327

Claim:
A process of reducing frame error rate in frames of communication data, comprising: A. receiving communication data that is protected by convolutional encoding, the data including, in sequence, class 1a bits that are additionally protected by a cyclic redundancy check, cyclic redundancy check bits, and class 1b tail bits that are protected only by the convolutional encoding; B. Viterbi decoding the data in a reverse direction starting with the class 1b tail bits and proceeding to the class 1a bits to determine paths in the class 1b tail bits, the cyclic redundancy check bits, and the class 1a bits; and C. serial list Viterbi decoding in a forward direction of the data beginning with the class 1a bits and the cyclic redundancy check bits up to a boundary between the cyclic redundancy check bits and the class 1b tail bits to determine a path that may satisfy the cyclic redundancy check bits.