Patent ID: 7739538

Claim:
A method for clocking synchronous data on a chip between an input port coupled to a double data rate bus and output port coupled to a double data rate bus, including the steps of: latching a first half of the synchronous data in an L1 stage of a first input L1/L2 latch on a leading edge of a local clock signal; latching said first half of the synchronous data signal latched in the L1 stage in the just previous latching step in the L2 stage of the first input L1/L2 latch on the next trailing edge of the local clock signal; processing said first half of said synchronous data and latching the processed first half of the synchronous data in a first L1/L2 output latch on the next leading edge of said local clock signal; launching the processed first half of the synchronous data on said double data rate bus on the next trailing edge of the local clock signal; latching the second half of the synchronous data in a second L1/L2 input latch one half local clock signal after said first half of said synchronous data is latched in the L1 stage of the first input L1/L2 latch; processing said second half of the synchronous data and latching the processed second half of the synchronous data in a second L1/L2 output latch one half of a local clock cycle after said first half of the synchronous data is latched in said first L1/L2 output latch; and latching the output from the second L1/L2 output latch in a third L1/L2 output latch one half of a local clock cycle after the second half of the data is latched in the second L1/L2 output latch; and launching the processed second half of the synchronous data via said output port on said double data rate bus as soon as it is latched in the third L1/L2 output latch whereby the on chip latency is one local clock cycle.