Patent ID: 8803854

Claim:
A gate driver, comprising: a scan signal generating unit having a plurality of output channels, used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse; and a compensation unit coupled to the output channels, used for compensating a total resistance of each of the output channels through a buffering means, a switching means and a resistance-supply means, and sequentially receiving and transmitting the scan signal to a display panel, wherein the buffering means comprises at least one buffer, wherein the switching means comprises a combination of at least one switch and at least one digital logic gate, wherein the resistance-supply means comprises at least one line resistance, wherein the compensation unit comprises a first sub-compensation unit coupled to a portion of the output channels, and wherein the first sub-compensation unit comprises: a first line resistance; a second line resistance; and a plurality of first compensation circuits respectively corresponding to the portion of the output channels, each of the first compensation circuits comprising: a first buffer having an input terminal used for receiving the corresponding scan signal; a first NOT gate having an input terminal coupled to the input terminal of the first buffer; a first switch having a first terminal coupled to an output terminal of the first buffer a second terminal coupled to the display panel, and a control terminal coupled to an output terminal of the first NOT gate; a second switch having a first terminal coupled to the output terminal of the first buffer, and a second terminal coupled to the first line resistance; a third switch having a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the first line resistance; a fourth switch having a first terminal coupled to the output terminal of the first buffer, and a second terminal coupled to the second line resistance; a fifth switch having a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second line resistance; a second NOT gate having an input terminal used for receiving a first external configuration signal; a first tri-state gate having an input terminal coupled to the input terminal of the first buffer, an output terminal coupled to control terminals of the second and third switches, and an enable terminal coupled to the output terminal of the second NOT gate; and a second tri-state gate having an input terminal coupled to the input terminal of the first buffer, an output terminal coupled to control terminals of the fourth and fifth switches, and an enable terminal coupled to the input terminal of the second NOT gate.