Patent ID: 8730624

Claim:
An electrostatic discharge (ESD) power clamp circuit, comprising: a trigger circuit comprising a junction field effect transistor (JFET) and a capacitor; a buffer circuit having a single input; said JFET connected between a power pad and directly to a first plate of said capacitor and directly connected to said single input of said buffer circuit, said input of said buffer circuit connected to said first plate of said capacitor; said JFET having a single internal diode, a cathode of said internal diode connected to said power pad and an anode of said single internal diode connected to a gate of said JFET; a current by-pass device connected between said power pad and ground and to an output of said buffer circuit; a second plate of said capacitor connected to ground; and a false-trigger suppression circuit connected between a gate of said JFET and a drain of said JFET, said false trigger suppression circuit comprising a NAND gate having a first input, a second input and an output, said second input of said NAND gate connected to a pin configured to receive a power-on-signal and a p-channel field effect transistor (PFET), a gate of said PFET connected to said output of said NAND gate, a source of said PFET connected to said first input of said NAND gate, said drain of said JFET and to said power pad, a drain and body of said PFET connected to said gate of said JFET, said input of said buffer circuit and to said first plate of said capacitor.