Patent ID: 7701750

Claim:
A memory device comprising: a memory cell comprising a first electrode, a second electrode, and phase change material having first and second active regions arranged in series along an inter-electrode current path between the first electrode and the second electrode; bias circuitry adapted to apply bias arrangements to the memory cell to store a bit, the bias arrangements including: a first bias arrangement adapted to establish a high resistance state in the memory cell by inducing a high resistance condition in both the first and second active regions to store a first value of the bit in the memory cell, the high resistance state having a minimum resistance indicating that at least one of the active regions is in the high resistance condition, and a second bias arrangement adapted to establish a low resistance state in the memory cell by inducing a low resistance condition in both the first and second active regions to store a second value of the bit in the memory cell, the low resistance state having a maximum resistance indicating that both the first and second active regions are in the low resistance condition; and sense circuitry to sense the value of the bit in the memory cell by determining whether the memory cell has a resistance corresponding to the low resistance state or to the high resistance state.