Patent ID: 7804341

Claim:
A processor, comprising: a clock source that is configured to generate an input clock signal having an input frequency; a forward path portion that is configured to receive the input clock signal at a first input and generate a first signal having a variable amplitude and a first frequency, the first signal being based on the input clock signal; a level restorer, coupled to an output of the forward path portion, that is configured to convert the first signal to a second signal having the first frequency and a level-restored amplitude that can be a value that is either greater or less than the variable amplitude of the first signal; a feedback path, coupled between the level restorer and a second input of the forward path portion, that is configured to return the second signal to the forward path portion, and that includes a divide-by-N circuit that dives the first frequency by a predetermined frequency divisor; and an output buffer, coupled to the level restorer, that is configured to generate a clock output signal having greater power transfer capacity than the level restorer.