Patent ID: 7577823

Claim:
Multi-processor computer system comprising at least two processors ( 1 ) for parallel execution of processes, at least two cache memory units ( 2 ), each being associated with and connected to a separate processor ( 1 ) of the at least two processors, a connection bus ( 4 ) connecting said processors ( 1 ) and said cache memory units ( 2 ), and a process list unit ( 3 ) connected to said connection bus ( 4 ) for storing a process list of processes to be available for execution by said processors ( 1 ), wherein said processors ( 1 ) are adapted for loading a global wake-up variable signaling process additions of processes to said process list into their associated cache memory unit ( 2 ), for switching into a low-power mode if said process list contains no process for execution by said processors ( 1 ) and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.