Patent ID: 7493549

Claim:
Assembly of electronic circuits, comprising: at least one memory and means for detecting and correcting errors in the data supplied by the memory during a read operation, the output of the memory being connected in parallel to an input of an error detection circuit, to an input of an error correction circuit, and to the input of a first stage, the error detection circuit controlling transmission of the corrected data to the first stage after an error has been detected; the assembly wherein further comprises the memory being serially connected with a plurality of successive stages, and the output of the detection circuit controls decontamination means of the successor stages liable to be contaminated by an error before detection of the latter; wherein each stage further comprises at least one latch, the output of the memory is connected to the input of the first stage by means of a first multiplexing circuit having an output connected to the input of the first stage, a first input connected to the output of the memory and a second input connected to the output of the correction circuit, and the output of the detection circuit being connected to a control input of the first multiplexing circuit and to a hold input of the latches of the successor stages so that detection of an error by the detection circuit simultaneously causes transmission of the data corrected by the correction circuit to the latch of the first stage by the first multiplexing circuit and holding of the latches of the successor stages.