Patent ID: 8381147

Claim:
A modeling method comprising: accessing, by a computer from a memory, a formula for determining total parasitic resistance (R tot ) associated with a diffusion region of a semiconductor device, said diffusion region being contacted by a number N of contacts, said contacts being connected by a wire to a common node line and said formula being based on a sum of resistance contributions from segments of said wire, from said N contacts, and from N partitions of said diffusion region and on electric current flow; arbitrarily establishing, by said computer, a position of each dividing line separating adjacent partitions, said position being between adjacent contacts; using, by a computer, said formula to determine a first value for said total parasitic resistance given said position of each dividing line; and iteratively adjusting, by said computer, said position of each dividing line in order to achieve a second value for said total parasitic resistance (R tot ) that is less than said first value.