Patent ID: 7482840

Claim:
A semiconductor integrated circuit comprising: a first transistor of a first conductivity type connected between a first power supply and an output node, the first transistor being turned ON according to a first clock to put the output node to a first logic level; a second transistor of a second conductivity type, connected in a series to the first transistor, the second transistor being turned ON according to an input signal; a third transistor of the second conductivity type connected in series to the second transistor, the third transistor being turned ON according to a second clock; a fourth transistor of the first conductivity type connected between the first power supply and the output node, the fourth transistor being turned ON according to a feedback signal; an inverter for outputting a signal inverted in logic level from the output node; a fifth transistor of the first conductivity type connected between the first power supply and the output node, the fifth transistor being turned ON according to an output of the inverter; a decode circuit for determining whether or not an input value matches with a predetermined value and outputting the determination result; and a delay circuit for delaying the signal indicating the determination result from the decode circuit and outputting the delayed signal as the feedback signal, wherein the second and third transistors are connected between the output node and a second power supply, and the fourth transistor is turned from ON to OFF after both the second and third transistors are turned ON, and where the signal indicating the determination result from the decode circuit is used as the input signal.