Patent ID: 8421081

Claim:
A memory device comprising: a memory cell comprising a first transistor, a second transistor, and a first insulating film, wherein the first transistor comprises: a first oxide semiconductor layer including a first channel formation region; a first electrode connected to the first oxide semiconductor layer; a second electrode connected to the first oxide semiconductor layer; a first gate electrode overlapping with the first channel formation region; and a second insulating layer interposed between the first gate electrode and the first oxide semiconductor layer, wherein the second transistor comprises: a second gate electrode; a third insulating film over the second gate electrode; a second oxide semiconductor layer including a second channel formation region over the third insulating film; a third electrode connected to the second oxide semiconductor layer; a fourth electrode connected to the second oxide semiconductor layer; a fourth insulating film over the second oxide semiconductor layer, the third electrode, and the fourth electrode; and a third gate electrode over the fourth insulating film, wherein the second gate electrode, the third gate electrode, and the second channel formation region are overlapped with each other, wherein the first oxide semiconductor layer is located above the third gate electrode, and wherein the first oxide semiconductor layer is located above the first insulating film, and the second oxide semiconductor layer is located below the first insulating film.