Patent ID: 8072254

Claim:
A phase locked loop, comprising: a phase comparator for comparing a reference clock with a feedback clock; a control voltage generator for generating a control voltage in response to an output of the phase comparator; and a voltage controlled oscillator for generating an internal clock having a frequency corresponding to the control voltage and one or more frequency range selection signals, wherein the feedback clock is generated in response to the internal clock, wherein the voltage controlled oscillator includes one or more delay cells connected in series, wherein each of the delay cells include: a first current controller configured to supply first and second currents to first and second nodes in response to the control voltage; a signal input unit configured to output differential output signals in response to differential input signals and in response to total currents flowing through the first and second nodes, respectively; and a second current controller configured to selectively add third and fourth currents to the first and second nodes, respectively, in response to one or more frequency range selection signals, wherein the second current controller receives a supply voltage, makes a current path between the supply voltage and the first and second nodes and generates the third and fourth currents in response to a predetermined bias voltage, which is different from the control voltage and the supply voltage, and supplies the third and fourth currents to the first and second nodes respectively depending on whether the one or more frequency range selection signals are activated or inactivated.