Patent ID: 7907451

Claim:
A semiconductor storage device that operates by being connected to a positive power supply and a negative power supply, comprising: a plurality of memory cells each comprising: a p-type semiconductor channel, a first n-type region formed in the channel, a second n-type region formed in the channel, a first insulator formed on a surface of the channel, a first control gate formed by a n-type semiconductor formed on a surface of the first insulator, a second insulator formed on a surface of the first control gate, a floating gate formed on a surface of the second insulator and to stores data according to whether or not electrons being stored therein, a third insulator formed on a surface of the floating gate, and a second control gate formed on a surface of the third insulator; and a control circuit that: applies a predetermined positive voltage to the first control gate and applies a positive voltage to the second control gate to control a potential barrier between the channel and the floating gate so as to facilitate passage of electrons therethrough in order to store data in each of the plurality of memory cells for each of the plurality of memory cells; applies a ground voltage to the first control gate to control the potential barrier between the channel and the floating gate so as to have the passage of electrons therethough be difficult in order to retain data in each of the plurality of memory cells for each of the plurality of memory cells; and places the first control gate in a floating state in which the first control gate is electrically isolated from all other components in order to read out data from each of the plurality of memory cells when a positive voltage is applied to the first n-type region for each of the plurality of memory cells; wherein the first insulator and the second insulator have the floating gate store electrons to store data only when a positive voltage being applied to the first n-type region in each of the plurality of memory cells.