Patent ID: 7477558

Claim:
A semiconductor memory device, comprising: a local input/output line connected to a bit line coupled with a memory cell, through a column selection transistor, the local input/output line providing a transmission path on which to transmit a data signal through the bit line to a local sense amplifier; and a local precharge circuit configured to adjust a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal, wherein the local precharge circuit maintains the precharge voltage level at the first voltage level during a first period of time and the second voltage level during a second period of time, the first period of time spanning from a start point of the active mode until the column selection signal transitions to a first logic level, and the second period of time spanning from when the column selection signal transitions to a second logic level from the first logic level until an end point of the active mode.