Patent ID: 7613211

Claim:
A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B1) obtaining said FIFO depth B by subtracting modulo B for each said stored symbol said symbol output address from said symbol input address; (B2) inputting said FIFO depth B into a programmable LUT; (B3) obtaining a phase detector error signal; (B4) scaling said phase detector error signal to obtain a scaled error factor, wherein said scaled error factor is normalized by using a set of parameters selected from the group consisting of: {a ratio of said input symbol rate to said reference clock; and a damping factor configured to compensate for latency of said frequency lock loop (FLL)}; (B5) adding said scaled error factor to a nominal phase step to obtain a phase update; (C) obtaining a smoothed symbol rate; and (D) reading out each output symbol from said FIFO under control of an output FIFO address control register at said smoothed symbol rate.