Patent ID: 7697313

Claim:
An integrated circuit, comprising: an arrangement of memory cells, wherein each memory cell is connected to a programming current path used for programming the memory cell, and a sensing current path used for sensing a memory state of the memory cell, wherein the programming current path and the sensing current path are at least partially separated from each other, wherein the memory cells are thermal selectable magneto-resistive memory cells, or the memory cells are spin injection current switching selectable memory cells, wherein each memory cell comprises a storage memory element and a sensing memory element that is spatially separated from the storage memory element, wherein the programming current path runs through the storage memory element, and wherein the sensing current path runs through the sensing memory element; and a second conductive line disposed above a first conductive line or disposed above a conductive plate, wherein one of the sensing memory element and the storage memory element is electrically connected between the first conductive line and the second conductive line, or is electrically connected between the conductive plate and the second conductive line, and wherein the other one of the sensing memory element and the storage memory element is disposed below the first conductive line or the conductive plate, and is electrically connected to the first conductive line or the conductive plate.