Patent ID: 7698625

Claim:
A parity circuit, comprising: a buffer for storing information as a set of symbols, said information comprising a plurality of data, a plurality of first parities, and a plurality of second parities; a first calculator, coupled to said buffer, for receiving said set of symbols from said buffer and for supplying a first calculated result to said buffer; a second calculator, coupled to said buffer, for receiving said set of symbols from said buffer and for supplying a second calculated result to said buffer; a programmable logic circuit, coupled to said first and second calculators, for controlling said first and second calculators, said programmable logic circuit providing logic to said first and second calculators to allow the calculation of parity generation, parity update, and data regeneration for a RAID storage system with a plurality of data disks and parity disks; wherein at least one of said first and second calculators comprise: a first data transfer circuit, for receiving symbols from said buffer; a plurality of calculation circuits, the plurality of calculation circuits being equal in number to the plurality of data disks in the RAID storage system, each one of calculation circuits receiving symbols from said first data transfer circuit; a second data transfer circuit for receiving symbols from said plurality of calculation circuits and sending symbols to said buffer; and a control sequencer coupled to receive control signals from said programmable logic circuit and for controlling said first data transfer circuit, said plurality of calculation circuits, and said second data transfer circuit.