Patent ID: 8581825

Claim:
A driving circuit for a flat panel display device, comprising: a generation unit for generating n-phase form generation clocks; a drain voltage terminal and a source voltage terminal; and a plurality of shift register stages for sequentially generating a plurality of gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stages including: first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor; third to at least eighth transistors, each transistor having gate, drain and source terminals; and ninth and tenth transistors, wherein a source of the ninth transistor and a drain of the tenth transistor are connected to a node between the ninth and tenth transistors, wherein the node between the ninth and tenth transistors is directly connected to one of the subsequent shift register stages, wherein a gate of the ninth transistor is connected to a gate of the first transistor, wherein each gate line is connected to a node between the first and second transistors, and wherein each of the n-phase form generation clocks has one of a shape of two separate square waves having different pulse widths, a shape of two separated square waves having identical or equal pulse widths and a shape of a sum of indefinite sinusoidal waves having different amplitudes and periods.