Patent ID: 7305543

Claim:
A microcontroller architecture comprising: a processor for processing of instruction data comprising memory access instructions for accessing of a memory circuit, the processor operating responsive to a clock circuit for providing clock cycles; at least a pointer memory circuit for storing of a pointer address forming part of the instruction data; at least a pointer register for storing a duplicate of the pointer address; a control circuit for determining whether one of a read operation from the at least a pointer memory circuit and a write operation to the at least a pointer memory circuit is to take place; wherein the clock circuit is coupled to the at least a memory circuit, the at least a pointer register and the control block, and the read operation accesses a region in the memory circuit that is addressed by a target pointer address within a single clock cycle or determining a read operation is to take place, and wherein for a write operation the control circuit stores the pointer address in the at least a pointer memory circuit and automatically stores a duplicate in the at least a pointer register and where for a read operation the control circuit utilizes the at least a pointer register to access data pointed to by the target pointer address derived from the pointer address stored therein without accessing the at least a pointer memory; the microcontroller architecture further comprising a pointer multiplexer block having at least an input port coupled to the at least a pointer register for receiving a pointer address and an output port for providing the target pointer address used for indirect addressing operations of data stored within the memory circuit; and a source select block having a first input port for receiving a next program address derived from a current program counter value plus a length of a current instruction, a second input port for receiving the target pointer address from the pointer multiplexer block, a third input port for receiving a selection signal from the control circuit for determining which data bits from the at least one of the input signals received at the first and second input ports are to be used for providing of pointer data output signals from output ports of the source select block.