Patent ID: 7287205

Claim:
A method for testing signals of integrated circuits (ICs), comprising the steps of: successively driving, by a first IC chip, a plurality of test patterns one at a time; receiving, at a second IC chip, and latching in the test patterns one by one; determining, by the second IC chip, whether a currently latched test pattern is correct; if at least an error bit occurs in the currently latched test pattern, the second IC chip indicating that there exists noise interference in a signal trace corresponding to the error bit; repeating the above steps until the first IC chip finishes driving the test patterns; and if the currently latched test pattern is incorrect, the second IC chip adjusting a reference voltage level in accordance with the type of the corresponding test pattern to change an input threshold of the second IC chip, wherein the reference voltage level is decreased to lower the input threshold of the second IC chip if the corresponding test pattern belongs to the power bounce type.