Patent ID: 6874110

Claim:
A self-testing programmable logic array (PLA) system, comprising: an array of programmably interconnected logic cells; a built-in self-test (BIST) structure interconnected with the logic cells; and a BIST engine having an initiation input; characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test memory of the logic cells, programmable interconnections between the logic cells, and functional logic of the logic cells of the self-testing PLA system and wherein the programmable logic cells of the array of programmable interconnected logic array includes logic cells arranged along lines and are addressed by an address line, the BIST structure including at least: a sample line sampling outputs of programmable logic cells, a vector line for sending an input vector to programmable logic cells, a force line controlling whether the input vector is sent to the programmable logic cells, and a plurality of compare blocks wherein each compare block is associated with a different one of the lines and comprises: an element for controlling the sample line and the force line; an element for address decoding that generates address line signals; and a compare element for comparing outputs of programmable logic cells.