Patent ID: 8730717

Claim:
A semiconductor device comprising: a respective plurality of memory cell groups arranged at each of a plurality of intersections between a plurality of word lines and a plurality of bit lines intersecting the word lines, wherein each of the memory cell groups includes first and second memory cells connected in series, wherein each of the first and second memory cells includes a select transistor and a resistive storage device, wherein the select transistor and the resistive storage device are connected in parallel, wherein a gate electrode of the select transistor in the first memory cell is connected to a first gate line, wherein a gate electrode of the select transistor in the second memory cell is connected to a second gate line, wherein a first circuit block for driving the word lines, a second circuit block for driving the first and second gate lines, and the plurality of memory cell groups are arranged in line with extending direction of the word lines, and wherein the first circuit block is arranged between the second circuit block and the plurality of memory cell groups.