Patent ID: 7915929

Claim:
A high speed clock frequency-divider/splitter comprising: a first AND Inverted (AI) gate having an input that is coupled to an inverted BC clock order control signal (BC signal), wherein the BC signal exhibits a time-phase order between a B clock and a C clock that are output from a high speed clock leaf clock frequency-divider/splitter; a second AI gate having inputs that are coupled to the BC signal and a chopped oscillator signal; a third AI gate having inputs from an output of the first AI gate and an output of the second AI gate, wherein the third AI gate outputs the C clock; a fourth AI gate having inputs coupled to the chopped oscillator signal and to a B clock gate; and a fifth AI gate having inputs coupled to an output of the fourth AI gate and to a Level-Sensitive Scan Design (LSSD) C clock control signal (LSSDC), wherein the fifth AI outputs the B clock.