Patent ID: 7257752

Claim:
A built-in self-test (BIST) circuit for serving to self test a circuit-under-test in a system, wherein the system further comprises a unit circuit having a plurality of input terminals such that the input terminals are coupled to a plurality of signal paths respectively and an output terminal is coupled to the circuit-under-test for providing the circuit-under-test with necessary signals, the BIST circuit comprising: a BIST controller for generating a test signal to test the circuit-under-test when the system operates in a test mode; and a selection and activation circuit, wherein an output terminal of the selection and activation circuit is coupled to one of the input terminals of the unit circuit, one of the input terminals of the selection and activation circuit is coupled to a corresponding non-timing-critical path of the signal paths, and another input terminal of the selection and activation circuit receives the test signal so that the test signal can be output to the output terminal of the selection and activation circuit for transmitted through the unit circuit to test the circuit-under-test when the system operates in a test mode.