Patent ID: 6914840

Claim:
A semiconductor memory circuit comprising: a memory cell that includes: a first capacitor for storing therein electric charge corresponding to stored data, and a first transistor whose gate is connected to a word line and one of whose source and drain is connected to a first bit line, while the other of whose source and drain is connected to the first capacitor; a dummy cell that includes: a second capacitor having smaller capacitance than the first capacitor, a second transistor whose gate is connected to a dummy word line, and one of whose source and drain is connected to a second bit line, while the other of whose source and drain is connected to the second capacitor, and a third transistor for electrically connecting the second capacitor with a voltage line in accordance with a precharge signal when the dummy word line is inactive, the voltage line supplying a first voltage; a precharge circuit for precharging the first and second bit lines to a second voltage when the word line and the dummy word line are inactive; and a sense amplifier for detecting a potential difference caused between the first and second bit lines when the word line and the dummy word line are activated to electrically connect the first and second capacitors to the first and second bit lines, respectively, and for amplifying the voltages of the first and second bit lines either to the first voltage and to the second voltage, or to the second voltage and to the first voltage, respectively, wherein the transitions of the word line and the dummy word line from the inactivation voltage level to the activation voltage level are both in a direction from the second voltage to the first voltage, wherein the capacitance of the second capacitor is substantially half of the capacitance of the first capacitor, and wherein the first and second capacitors are both stacked capacitors, and the first capacitor is formed to have HSG structure.