Patent ID: 7245518

Claim:
A ferroelectric memory comprising: a memory cell array having a plurality of memory cells with ferroelectric capacitors arranged therein, a plurality of word lines, a plurality of plate lines, and a plurality of plate line selection circuits, wherein an L-th plate line selection circuit among the plurality of plate line selection circuits includes a first transistor that is provided between an L-th plate line and a supply node for supplying an I-th plate line selection signal and turns on when a K-th word line is set to a selection voltage to thereby supply the I-th plate line selection signal to the L-th plate line, and a second transistor that is provided between the L-th plate line and a first power supply and turns on when the K-th word line is set to a non-selection voltage to thereby set the L-th plate line to a voltage level of the first power supply, and an M-th plate line selection circuit among the plurality of plate line selection circuits includes a third transistor that is provided between an M-th plate line and a supply node for supplying a J-th plate line selection signal and turns on when the K-th word line is set to a selection voltage to thereby supply the J-th plate line selection signal to the M-th plate line, and a fourth transistor that is provided between the M-th plate line and the first power supply and turns on when the K-th word line is set to a non-selection voltage to thereby set the M-th plate line to the voltage level of the first power supply.