Patent ID: 8427861

Claim:
A semiconductor memory device comprising: a cell array having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between said plurality of first wirings and said plurality of second wirings, each containing a variable resistive element; and a control circuit for selectively driving said plurality of first wirings and said plurality of second wirings; wherein said control circuit applies a first voltage for a first operation to a first select wiring selected of said plurality of first wirings and applies a second voltage for a second operation different from said first operation to a second select wiring selected of said plurality of first wirings and applies a third voltage for the first and second operation to a third select wiring selected of said plurality of second wirings, said first operation is completed before said second operation is completed, and said control circuit applies a fourth voltage for a third operation to a forth select wiring selected of said plurality of first wirings before said second operation is completed.