Patent ID: 7012455

Claim:
A frequency divider dividing an original clock into a target clock, the frequency of the target clock being equal to the frequency of the original clock divided by M, M being a positive odd integer equal to or greater than 3, the frequency divider comprising: a front set circuit comprising: a first clock generator with a clock input end connected to a trigger clock having a frequency the same as that of the original clock and a trigger phase; and a first logic gate with a first input end connected to an output end of the first clock generator, and a second input end connected to a signal input end of the first clock generator; a middle set circuit comprising: a second clock generator with a clock input end connected to the trigger clock; and (M−3)/2 serially connected first sets of clock generators with a clock input end of each first set of clock generators connected to the trigger clock, a signal input end of the first clock generator within the (M−3)/2 first sets of clock generators connected to an output end of the first logic gate in the front set circuit, and an output end of the last clock generator within the (M−3)/2 first sets of clock generators connected to a signal input end of the second clock generator in the middle set circuit; and a rear set circuit comprising: a third clock generator with a clock input end connected to the trigger clock, and a signal input end connected to an output end of the second clock generator in the middle set circuit; and a second logic gate with a first input end connected to an output end of the third clock generator in the rear set circuit, a second input end connected to the output end of the second clock generator in the middle set circuit, and an output end for outputting the target clock.