Patent ID: 7114025

Claim:
A semiconductor memory comprising: a memory core having a plurality of memory cells, a bit line connected to said memory cells, and a sense amplifier connected to said bit line; a command control circuit for outputting an access request signal for accessing said memory cells in response to an access request supplied through a command terminal; a refresh timer for generating an internal refresh request at predetermined cycles; an arbiter for determining order of precedence between an access operation corresponding to said access request and a refresh operation corresponding to said internal refresh request when a conflict occurs between said access request and said internal refresh request, and for sequentially outputting a refresh control signal and an access control signal in accordance with the order of precedence; an operation control circuit for making said memory core perform an access operation in response to said access control signal, and making said memory core perform a refresh operation in response to said refresh control signal; and a detecting circuit for outputting a detection signal indicating that said refresh operation is yet to be performed when a new internal refresh request occurs before said refresh operation corresponding to said internal refresh request is performed, said detecting circuit operating in a test mode.