Patent ID: 8867275

Claim:
A flash memory device array comprising: a memory cell array including a main region and a buffer region separately designated from the main region and configured to temporarily store buffer data to be programmed to the main region, wherein the buffer region is divided into a first buffer region and a second buffer region; a page buffer configured to program buffer data to the buffer region; and control logic configured to control operation of the page buffer during the programming of the buffer data to the buffer region, wherein upon a determination by the control logic of a reliability mode the buffer data is stored in the first buffer region and upon a determination of a high-speed mode the buffer data is stored in the second buffer region, wherein the memory cell array is configured with M-bit, multi-level flash memory cells (MLCs), where M is an integer greater than 1, and the buffer data is programmed to the buffer region as 1-bit buffer data during the high-speed mode and the reliability mode, and wherein the buffer data is programmed during the high-speed mode and the reliability mode using an Incremental Step Pulse Programming (ISPP) pulse, such that an increment of the ISPP pulse during the high-speed mode is larger than an increment of the ISSP pulse during the reliability mode.