Patent ID: 8610240

Claim:
An integrated circuit comprising: a substrate; at least two pairs of adjacent shallow trench isolation (STI) structures formed in the substrate, wherein each pair of adjacent STI structures has a first STI structure formed to a first bottom depth at a first distance from a top surface of the substrate and a second STI structure formed to a second bottom depth at a second distance from the top surface of the substrate, wherein the first depth and the second depth are different depths; an oxide fill disposed in each pair of adjacent STI structures, wherein the oxide fill fills each pair of adjacent STI structures; and semiconductor devices disposed on the substrate between the at least two pairs of adjacent STI structures, wherein the semiconductor devices are partitioned into groups based on function, and wherein the at least two pairs of group STI structures have different bottom depths, and wherein the first depth and the second depth for each pair of adjacent STI structures are based on semiconductor device characteristics of the semiconductor devices.