Patent ID: 8552779

Claim:
A synchronizer latch circuit that facilitates resolving metastability, comprising: a data input; a clock input; a first output; a second output; a set of two or more cross-coupled transistors, wherein the gate of a first cross-coupled transistor is coupled to the second output, the gate of a second cross-coupled transistor is coupled to the first output, the drain of the first cross-coupled transistor is coupled to the first output, and the drain of the second cross-coupled transistor is coupled to the second output; and a third transistor, wherein the data input is coupled to the gate of the third transistor; wherein, upon receiving a synchronization signal, the data input activates the third transistor to change a voltage of the first output and create a voltage difference between the first output and the second output, and wherein the cross-coupled transistors amplify the voltage difference to generate valid logic output voltages even when the data input arrives within a setup-and-hold time window of the synchronizer latch circuit.