Patent ID: 8389403

Claim:
A method for manufacturing a semiconductor device, comprising: forming an impurity region by introducing impurities into a semiconductor substrate; forming an interlayer insulating film over the semiconductor substrate; forming a contact hole reaching the impurity region in the interlayer insulating film; forming a first conductive adhesive layer covering a wall surface of the contact hole; forming a conductive plug by burying a conductive material in the contact hole; forming a second conductive adhesive layer on the interlayer insulating film and the conductive plug; forming a copper film on the second conductive adhesive layer and the interlayer insulating film; planarizing the copper film by low-pressure chemical mechanical polishing (CMP) or electro chemical mechanical polishing (ECMP); sequentially forming a lower electrode material film, a dielectric film made of a ferroelectric or a high dielectric, and an upper electrode material film in this order on the copper film; forming a capacitor by patterning the upper electrode material film, the dielectric film, and the lower electrode material film; forming a protective film over the copper film and on the capacitor; and leaving only a part of the protective film, a part of the copper film and a part of the second conductive adhesive layer, the part of the protective film covering the capacitor, the part of the copper film which is formed under the capacitor and the part of the protective film and which is larger in width than the capacitor, and the part of the second conductive adhesive layer which is formed under the part of the copper film and which is larger in width than the capacitor, by patterning the protective film, the copper film and the second conductive adhesive layer.