Patent ID: 6950440

Claim:
A system for connecting peripheral devices to a computer, comprising: a host computer system, wherein said host computer system includes a CPU and memory; a first parallel bus coupled to the host computer system; a primary bridge coupled to the first parallel bus, wherein said primary bridge includes parallel interface circuitry for interfacing to the first parallel bus; a second parallel bus located remotely from said host computer system; one or more peripheral devices coupled to the second parallel bus; and a secondary bridge coupled to said second parallel bus, wherein said secondary bridge is located remotely from said host computer system, wherein said secondary bridge includes parallel interface circuitry for interfacing to said second parallel bus; and a serial bus coupled between said primary bridge and said secondary bridge, wherein the serial bus includes a first end and a second end, wherein said first end of said serial bus is coupled to said primary bridge and said second end of said serial bus is coupled to said secondary bridge; wherein said primary bridge and said secondary bridge are configured to transmit a parallel bus cycle over said serial bus, wherein said parallel bus cycle includes an address phase and a data phase, wherein said address phase includes a command value and an address value, and wherein said data phase includes a first set of byte enable values and a data value; wherein said primary bridge is configured to receive said parallel bus cycle, wherein said primary bridge is configured to generate a first command packet that corresponds to said address phase, wherein said primary bridge is configured to generate a plurality of data packets that each correspond to said parallel bus cycle, wherein said first command packet includes a second set of byte enable values, and wherein said primary bridge is configured to set said second set of byte enable values to a set of predetermined values prior to generating said plurality of data packets, wherein said predetermined values comprise predicted values of the first set of byte enable values.