Patent ID: 8451037

Claim:
A duty cycle correction circuit, comprising: a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal; a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal; and a control signal generation unit configured to generate the control signal in response to the detection signal, wherein the duty cycle control unit comprises: a delay circuit configured to delay the input clock signal by a delay time and output a delayed signal; a clock signal output circuit configured to output the corrected clock signal in response to the input clock signal and an output clock signal of the delay circuit; and a control circuit configured to control a transition timing of the corrected clock signal in response to the control signal, wherein the control circuit mixes the input clock signal with the output clock signal of the delay circuit for the delay time of the delay circuit.