Patent ID: 8436477

Claim:
A microelectronic package, comprising: a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function, the microelectronic element including a plurality of stacked electrically interconnected semiconductor chips; a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto; and a plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the terminals electrically connected with the substrate contacts and including first terminals arranged at positions within first and second parallel grids, the first terminals of each of the first and second grids being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, wherein the signal assignments of the first terminals in the first grid are a mirror image of the signal assignments of the first terminals in the second grid.