Patent ID: 7802021

Claim:
An apparatus for programming a plurality of electrically separable in-system programmable (ISP) devices, comprising: a processor configured to communicate with an application development system including a selector for selecting a type of ISP device from a library of ISP devices in order to receive a device algorithm that specifies a sequence of steps to be performed when programming a selected type of in-system programmable device, data to be programmed into each of the plurality of in-system programmable devices, and a selected bus algorithm to communicate with the type of in-system programmable device to be programmed; an FPGA circuit that is configurable by the processor to implement the selected bus algorithm received from the application development system; and a communication interface that is configured to allow the plurality of electrically separable in-system programmable devices to be connected to and disconnected from the FPGA; wherein the processor is configured to provide the data received from the application development system to be programmed into each in-system programmable device to the FPGA in accordance with the device algorithm and the FPGA is configured by the processor to transfer the data simultaneously to the plurality of in-system programmable devices in accordance with the selected bus algorithm, wherein the processor, FPGA and communication interface are included in combination with an automatic test equipment fixture and wherein the plurality of in-system programmable devices are mounted on circuit boards and are programmed while in the automatic test equipment fixture.