Patent ID: 8724680

Claim:
A transceiver, comprising: a transceiving unit comprising a phase-locked loop, wherein the phase-locked loop is used for generating a first clock, and the transceiving unit exchanges data with a link partner according to the first clock; and a clock generation unit, comprising: a clock generator for generating and outputting a second clock to the transceiving unit; a multiplexer comprising a first input terminal for receiving a calibration clock, a second input terminal for receiving a receiver clock of the link partner, and an output terminal for outputting the calibration clock or the receiver clock of the link partner; and a frequency difference detector coupled to the clock generator and the output terminal of the multiplexer for generating a difference signal according to a difference between the calibration clock and the second clock within a predetermined period, or a difference between the receiver clock of the link partner and the second clock within the predetermined period; wherein the transceiver does not include a crystal oscillator.