Patent ID: 7649961

Claim:
A digital amplifier comprising: a first variable frequency suppressed carrier (VFSC) pulse width modulation (PWM) generator operative to produce an in-phase differential signal dependent on an in-phase signal; a second variable frequency suppressed carrier (VFSC) pulse width modulation (PWM) generator operative to produce a quadrature-phase differential signal dependent on an quadrature-phase signal; a mixer operative to produce a mixed signal dependent on the in-phase and quadrature-phase differential signals; a decoder operative to produce switching signals dependent on the mixed signal; and a power stage operative to produce an amplified signal dependent on switching signals from the decoder; wherein each of the first and second VFSC PWM generators comprises: an integrating error amplifier operable to produce an error signal dependent on an input signal and the differential signal produced by the VFSC PWM generator, the input signal comprising the in-phase signal and the quadrature-phase signal; a duty ratio quantizer operable to produce the plurality of duty ratios dependent on the error signal; a random period generator operable to provide a variable frequency signal controlling a total number of available pulses of the plurality of duty ratios in each period; and a pulse width modulation counter operable to produce a plurality of pulse width modulated signals dependent on the duty ratios, wherein the differential signal produced by the VFSC PWM generator is based on the plurality of pulse width modulated signals.