Patent ID: 8569121

Claim:
A method of fabricating a transistor device, comprising the steps of: providing a transparent substrate; forming a channel material on the substrate; forming source and drain electrodes over, and in contact with, the channel material; depositing a photoresist on the channel material and on the source and drain electrodes; developing the photoresist using UV light exposure through the transparent substrate, wherein exposure of portions of the photoresist is blocked by the source and drain electrodes; removing developed portions of the photoresist exposing portions of the channel material, wherein undeveloped portions of the photoresist remain over the source and drain electrodes; depositing a dielectric layer on the channel material and on the undeveloped portions of the photoresist to a thickness of from about 1 nm to about 100 nm, wherein the dielectric layer is deposited after the photoresist has been developed through the substrate and after the developed portions of the photoresist have been removed; depositing at least one gate metal on the dielectric layer; and removing the undeveloped portions of the photoresist along with portions of the gate metal and portions of the dielectric layer over the source and drain regions, wherein a remaining portion of the gate metal between the source and drain region electrodes forms a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.