Patent ID: 8014219

Claim:
A semiconductor memory device comprising: a memory cell configured to store data, comprising a resistance configured to vary based on the stored data; a bit line connected to the memory cell; a first Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) configured to hold the bit line to a read voltage while reading data; a sense amplifier configured to detect the stored data in the memory cell based on a current flowing through the bit line; a first switch configured to connect the sense amplifier to a drain of the first MOSFET; a second switch configured to connect a source of the first MOSFET to the bit line; a third switch configured to connect the drain of the first MOSFET to a ground terminal; and a fourth switch configured to connect the source of the first MOSFET to a ground terminal, wherein the first and second switches are on and the third and fourth switches are off when the sense amplifier is active, and the first and second switches are off and the third and fourth switches are on when the sense amplifier is inactive.