Patent ID: 8339880

Claim:
A circuit for controlling redundancy in a semiconductor memory apparatus, the circuit comprising: a peripheral circuit redundancy control block configured to generate a global address; and a memory bank redundancy control block which receives the global address corresponding to a second internal command to selectively activate a redundancy word line or a main word line, wherein the peripheral circuit redundancy control block includes: a first flip-flop unit which receives a buffering address, a buffering command, a refresh signal, and the global address to generate a first latch address; a fuse set unit which compares the first latch address with an output signal of each fuse circuit provided therein to generate a repair determination signal; a second flip-flop unit which latches a delay buffering address in accordance to a clock; a third flip-flop unit which latches a delay buffering command in accordance to the clock to generate a first internal command; a global address generating unit which receives a second latch address and the output signal of each fuse circuit of the fuse set unit to generate the global address in accordance to the repair determination signal, the first internal command, and the refresh signal; and a command converting unit which receives a bank address and the first internal command to generate the second internal command.