Patent ID: 7668029

Claim:
A method for accessing a memory array, the method comprising: beginning a bit line precharge operation based on a clock edge of an external clock signal, wherein the clock edge comprises one of a group consisting of a logic low to logic high transition and a logic high to logic low transition; terminating the bit line precharge operation a first predetermined duration after the clock edge that is independent of a clock period of the external clock signal; enabling a word line after the terminating of the bit line precharge operation; beginning a sense operation after the enabling the word line, the sense operation for sensing a logic state of a memory cell; and outputting a data bit from the memory array corresponding to the sensed logic state of the memory cell; wherein: the method is characterized as being self-timed from the step of beginning the bit line precharge to the step of beginning the sense operation and based on the clock edge of the external clock signal; and the step of beginning the sense operation is further characterized by beginning a second predetermined duration after the step of enabling the word line begins and by the sense operation having a variable duration.