Patent ID: 7795661

Claim:
A semiconductor device comprising: at least one trench capacitor located in a bottom portion of a trench that is present in a semiconductor substrate, wherein the at least one trench capacitor comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode; and at least one vertical transistor located over the at least one trench capacitor that is present in an upper portion of the trench, wherein said at least one vertical transistor comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode, wherein the channel region, the source region, and the drain region of the at least one vertical transistor are located in a single layer of a tensilely or compressively strained semiconductor material that is oriented perpendicularly to and in direct contact with a surface of the semiconductor substrate, the single layer of the tensilely or compressively strained semiconductor material having a different lattice constant than the semiconductor substrate, wherein the single layer of the tensilely or compressively strained semiconductor material including the source region and the drain region is embedded and in direct contact with an insulator structure present in a portion of a sidewall of the trench that is located over the semiconductor substrate, so that the at least one vertical transistor has a semiconductor-on-insulator (SOI) configuration, wherein the single layer of tensilely or compressively strained semiconductor material extends along sidewalls and a bottom wall of the trench that is present in the semiconductor substrate.