Patent ID: 7956642

Claim:
A level shifter circuit comprising: a cross-coupled level shifting latch having a first input node, a second input node, a first differential output node and a second differential output node; a set-reset (SR) logic gate latch having a reset input node, a set input node, and an output node, wherein the reset input node is coupled to the second differential output node of the cross-coupled level shifting latch, and wherein the set input node is coupled to the first differential output node of the cross-coupled level shifting latch; and an inverting circuit for mitigating duty cycle distortion skew by matching propagation delays of signals passing through the level shifter circuit, the inverting circuit supplying a digital signal onto the first input node of the cross-coupled level shifting latch, and supplying an inverted version of the digital signal onto the second input node of the cross-coupled level shifting latch, wherein the inverting circuit comprises: a non-inverting digital logic circuit comprising at least two buffering components to set a propagation delay of a first signal passing through the non-inverting digital logic circuit to the output node of the SR logic gate latch, the non-inverting digital logic circuit having an input node and an output node, wherein the output node is coupled to the first input node of the cross-coupled level shifting latch; and an inverting digital logic circuit comprising at least one buffering component to match a propagation delay of a second signal passing through the inverting digital logic circuit to the output node of the SR logic gate latch with the propagation delay of the first signal passing through the non-inverting digital logic circuit to the output node of the SR logic gate latch, the inverting digital logic circuit having an input node and an output node, wherein the input node of the inverting digital logic circuit is the input node of the non-inverting digital logic circuit, wherein the output node is the second input node of the cross-coupled level shifting latch, and wherein the buffering components of the non-inverting digital logic circuit and the inverting digital logic circuit are not shared.