Patent ID: 7685454

Claim:
A signal buffering and retiming (SBR) circuit for buffering and retiming signals for parallel application to a plurality of memory devices, the SBR circuit comprising: a PLL-based clock generator adapted to generate a set of phase-shifted clock signals from an input clock signal; a plurality of phase selectors, each phase selector adapted to independently select a subset of contiguous clock signals from the set of phase-shifted clock signals; a set of one or more output clock verniers, each output clock vernier adapted to (1) receive a corresponding subset of contiguous clock signals from a corresponding phase selector, (2) select one of the contiguous clock signals as its retiming clock, and (3) generate, using its retiming clock, an output clock signal for at least one of the memory devices; a set of one or more feedback clock verniers, each feedback clock vernier adapted to (1) receive a corresponding subset of contiguous clock signals from a corresponding phase selector, (2) select one of the contiguous clock signals as its retiming clock, and (3) generate, using its retiming clock, a feedback clock signal provided to the PLL-based clock generator; and one or more sets of non-clock verniers, each non-clock vernier adapted to (1) receive a corresponding subset of contiguous clock signals from a corresponding phase selector, (2) select one of the contiguous clock signals as its retiming clock, (3) receive a bit of address or control data, and (4) generate, using its retiming clock, a retimed bit signal from the bit of address or control data for at least one of the memory devices.