Patent ID: 8452831

Claim:
A floating-point circuit, comprising: a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor; and a divide engine coupled to the floating-point operand normalization circuit; wherein in response to determining that one or more of the input floating-point operands is a denormal number, the floating-point operand normalization circuit is further configured to: normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine; dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ); wherein the divide engine is configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.