Patent ID: 7394307

Claim:
A voltage regulator having a voltage input terminal and a voltage output terminal, comprising: a first p-channel MOS transistor and a second p-channel MOS transistor connected in series between the voltage input terminal and the voltage output terminal, the first p-channel MOS transistor having a drain connected to the voltage input terminal and a gate to which a voltage less than or equal to a threshold voltage is applied, the second p-channel MOS transistor having a drain connected to the voltage output terminal; and a voltage regulator circuit comprising an operational amplifier, a reference voltage circuit, and a resistance voltage divider; wherein the voltage regulator circuit and the second p-channel MOS transistor are driven by a current flowing through the first p-channel MOS transistor; and wherein said voltage regulator further comprises a cut-off circuit including an equalizer that equalizes gate and source voltages of the first p-channel MOS transistor to stop a current from the voltage output terminal to the voltage input terminal when a voltage at the voltage output terminal is higher than a voltage at the voltage input terminal.