Patent ID: 7102408

Claim:
An information processing apparatus, comprising: a system clock generator which oscillates a system clock; a first unit having a clock gate generating unit which generates a clock gate signal for controlling supply and stop of the system clock, a clock control unit which controls the supply and stop of the system clock on the basis of said clock gate signal, and a clock distributing unit which distributes the system clocks outputted from said clock control unit to a control circuit unit and makes said control circuit unit operative; one or a plurality of second units each having a clock generator which uses the system clock outputted from said first unit as a reference clock, feeds back the system clock at a predetermined circuit position, and generates phase-coincident system clocks, a clock control unit which controls the supply and stop of said system clock outputted from said clock generator on the basis of said clock gate signal obtained from said first unit, and a clock distributing unit which distributes the system clock outputted from said clock control unit to said control circuit unit and makes the control circuit unit operative; a system board on which said system clock generator, said first unit, and said second unit are mounted and which has board lines for individually supplying each of the system clock and the clock gate signal which are outputted from said first unit to the first unit itself and the second unit; a first delay setting unit which is provided for a signal supply line of the system clock in the first unit to the second unit and in which a variation and delay elements which are equivalent to those of said clock distributing unit of said first unit have been set; and a second delay setting unit which is provided for a signal supply line of the clock gate signal in the first unit to said second unit and in which the variation and the delay elements which are equivalent to those of the clock distributing unit of said first unit have been set.