Patent ID: 7825885

Claim:
A display device comprising: a pixel section having a plurality of pixel circuits, each writing video pixel data propagated through a switching element over a signal line, arranged in a matrix, a plurality of scan lines arranged so as to correspond to an array of rows of the pixel circuits and control conduction of the switching elements, a plurality of capacity lines arranged so as to correspond to an array of rows of the pixel circuits, a drive circuit for selectively driving the plurality of scan lines and the plurality of capacity lines, a generation circuit for generating a common voltage signal switched in level at a predetermined cycle, and a correction circuit for correcting the signals driving the capacity lines of the drive circuit, wherein each pixel circuit arrayed at the pixel section includes a display element having a first pixel electrode and second pixel electrode and a holding capacitor having a first electrode and second electrode, a first pixel electrode of the display element pixel cell and a first electrode of the holding capacitor are connected to one terminal of the switching element, a second electrode of the holding capacitor is connected to the capacity line arrayed at a corresponding row, a second pixel electrode of the display element is supplied with the common voltage signal, the drive circuit has a capacity line driver which drives a corresponding capacity line independently for each row based on a polarity signal at the time of a pixel write operation wherein values for corrected signals driving the capacity lines are determined at least in part based upon a predetermined temperature relationship; and further wherein the common voltage signal is a small amplitude signal; the drive circuit has a capacity line driver which determines a polarity of a signal driving a capacity line based on the polarity at the time of a pixel write operation; the drive circuit has a scan line driver including a shift register for shifting a predetermined signal in a column direction and a buffer receiving the signal of the shift register and driving the corresponding scan line, and the capacity line driver includes a first latch latching the polarity signal based on an output signal of the shift register to the buffer and a second latch latching and outputting the polarity signal latched by the first latch based on a shift signal to a next stage of the shift register.