Patent ID: 8558579

Claim:
A digital glitch filter for filtering an input signal, comprising: a first flip-flop for generating a first intermediate signal based on detection of a negative glitch in the input signal, wherein the input signal is provided to at least one of a set terminal and a reset terminal of the first flip-flop; a second flip-flop for generating a second intermediate signal based on detection of a positive glitch in the input signal, wherein an inverted input signal is provided to at least one of a set terminal and a reset terminal of the second flip-flop; and a synchronizer, connected to the first and second flip-flops, for generating a filtered output signal based on the first and second intermediate signals, wherein the synchronizer includes, a first logic gate connected to at least one of an output terminal and an inverted output terminal of the first flip-flop; a second logic gate connected to at least one of an output terminal and an inverted output terminal of the second flip-flop and an output terminal of the first logic gate; a third flip-flop, having an input terminal connected to an output terminal of the second logic gate and an output terminal connected to an input terminal of the first logic gate, for generating a third intermediate signal based on the first and second intermediate signals; and a fourth flip-flop, having a data input terminal connected to the output terminal of the third flip-flop, for generating the filtered output signal based on the third intermediate signal.