Patent ID: 8354748

Claim:
A method of using a memory apparatus, the method comprising: accessing a memory chip from a processor, wherein the processor is coupled to a mounting substrate, the mounting substrate including: a die side ( 412 ) and a land side ( 414 ) and at least one interconnect ( 420 ) on the die side; a chip footprint on the die side to accept a chip on the die side; a microelectronic first die ( 418 ) embedded in the mounting substrate, wherein the microelectronic first die is coupled to at least one processor interconnect, wherein the microelectronic first die is embedded at least in part in the mounting substrate; a microelectronic subsequent die ( 419 ), ( 444 ), ( 446 ) is directly attached to the microelectronic first die, wherein the microelectronic subsequent die is also at least partially embedded in the mounting substrate; and operating the memory chip at an I/O rate between 10 Gb/s and 1 Tb/s.