Patent ID: 7836385

Claim:
A system for detecting and correcting bit errors comprising: one or more circuits for computing event weights, using as inputs: an output, ν, provided by a Viterbi detector, said Viterbi detector receiving one or more codewords transmitted through a communication channel in the presence of additive white Gaussian noise, each of said one or more codewords comprising a number of parity bits; and said one or more codewords; said one or more circuits for computing parity syndrome values associated with each of said one or more received codewords, said one or more circuits using said output, ν; said one or more circuits for determining preferred error events that have the smallest event weight for each parity syndrome of each codeword of said one or more codewords, and for computing one or more cumulative event weights associated with said one or more codewords, using as inputs: said event weights; and said parity syndrome values; and said one or more circuits used for correcting said one or more codewords using said one or more cumulative event weights and said output, ν.