Patent ID: 8407271

Claim:
A processor comprising: a decode unit; and a floating point unit configured to receive from the decode unit an instruction; wherein in response to determining the instruction corresponds to a floating point round to nearest integer instruction for a floating point number, the floating point unit is configured to: retrieve a binary source operand corresponding to the instruction; compute an unbiased exponent value; generate a binary mask based at least in part on said unbiased exponent value, wherein said mask indicates a least significant digit of a nearest integer value to the floating point number; compute a first intermediate result equal to a bitwise OR of the source operand with the binary mask; compute a second intermediate result based at least in part on said first intermediate result; compute a bitwise inverse of the binary mask; and generate a rounded floating point number by performing a bitwise AND of the inverse of the binary mask and the second intermediate result, wherein the rounded floating point number is a floating point number with an integer value.