Patent ID: 8054664

Claim:
A memory module comprising: a plurality of DRAMs mounted on a board; two connectors mounted on the board for receiving data; a buffer device mounted on the board for redriving data applied to said two connectors to supply the data to said plurality of DRAMs, wherein said buffer device is located near the center of the board on which said two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on an opposite side to said connector; a DRAM arranged on the left side of said buffer device, as viewed from a top surface of the board, for receiving DQ[63:32], DQS[7:4], DQS[16:13] and /DQS[7:4], /DQS[16:13]; and a DRAM arranged on the right side of said buffer device for receiving DQ[31:0], CB[7:0], DQS[3:0], DQS[12:9], DQS 8 and DQS 17 and /DQS[3:0], /DQS[12:9], /DQS 8 and DQS 17 , wherein two said buffer devices are allotted with DQ[31:0], CB[7:0], DQS[3:0], DQS[12:9], DQS 8 and DQS 17 and /DQS[3:0], /DQS[12:9], /DQS 8 and DQS 17 , and DQ[63:32], DQS[7:4], DQS[16:13] and /DQS[7:4], /DQS[16:13] from the connectors, for application to the DRAMs.