Patent ID: 7763398

Claim:
A layout method for a mask comprising: forming a cell including a first main pattern; forming a second main pattern in a main chip layout; inserting the cell into the main chip layout; forming a dummy pattern inhibiting region on the basis of the first main pattern and the second main pattern; forming plural dummy patterns having a single common shape over the entire main chip layout into which the cell is inserted; and removing dummy patterns overlapping the dummy pattern inhibiting region, wherein forming the plural dummy patterns having the single common shape comprises: forming a plurality of mother dummy patterns while maintaining a second spacing therebetween; and forming a plurality of child dummy patterns by dividing the mother dummy patterns into the child dummy patterns, wherein the child dummy patterns of each of the plurality of mother dummy patterns are spaced apart from each other by a first spacing, wherein forming the plurality of child dummy patterns comprises: forming a third pattern with a width and a height of the same size as the first spacing by reducing a first mother dummy pattern; forming a fourth pattern with a height of the same size as the first mother dummy pattern by expanding the third pattern in a vertical direction; forming a fifth pattern with a width a size as the first mother dummy pattern by expanding the third pattern in a horizontal direction; and using the fourth pattern and/or the fifth pattern to form the child dummy patterns.