Patent ID: 8902664

Claim:
A semiconductor memory device, comprising: a semiconductor substrate including a plurality of active areas formed in the semiconductor substrate to extend in a first direction; a plurality of word lines provided on the semiconductor substrate to extend in a second direction; a plurality of bit lines connected respectively to the active areas; a source line connected to the plurality of active areas; charge storage layers disposed between the active areas and the word lines; and a control circuit, memory cell transistors being formed at intersections between the active areas and the word lines, the memory cell transistors being configured to be programmed with data having values of multiple levels, the control circuit being configured to apply a pass potential to a first word line and apply a preliminary read-out potential to a second word line coupled with a second memory cell transistor programmed with data after a first memory cell transistor coupled with the first word line is programmed, the pass potential being configured to switch the memory cell transistors to an ON state regardless of the programmed value, the second word line being disposed adjacently to the first word line, the control circuit being configured to read the data from the first memory cell transistor at a first condition in a case where the second memory cell transistor has been switched to the ON state based on a value of the second memory cell transistor by the applying of the preliminary read-out potential, the first condition being configured to enable the discrimination of a value of the first memory cell transistor in a case where the first memory cell transistor has a threshold voltage in a relatively low distribution, the control circuit being configured to read the data from the first memory cell transistor at a second condition in a case where the second memory cell transistor has been switched to an OFF state based on a value of the second memory cell transistor by the applying of the preliminary read-out potential, the second condition being configured to enable the discrimination of a value of the first memory cell transistor in a case where of the first memory cell transistor has a threshold voltage in a relatively high distribution.