Patent ID: 7511988

Claim:
An SRAM array comprising: an array of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein each of the SRAM cells comprises: a load device; a pull-down transistor; and a switch-box coupled between the load device and the pull-down transistor; a plurality of wordlines connected to the rows of SRAM cells of the array with a wordline connected to SRAM cells in a same row; a plurality of bitlines connected to the columns of SRAM cells of the array with a bitline connected to SRAM cells in a same column; a plurality of switch control lines connected to switch-boxes of the SRAM cells, wherein the plurality of switch control lines comprises: a first group of switch control lines connected to the rows of SRAM cells of the array with a switch control line connected to SRAM cells in a same row; and a second group of switch control lines connected to the columns of SRAM cells of the array with a switch control line connected to SRAM cells in a same column; and a switch control circuit connected to the plurality of switch control lines and configured to: turn off a switch-box of an SRAM cell during a read operation of the SRAM cell, and turn on the switch-box during a write operation of the SRAM cell; turn off switch-boxes of SRAM cells connected to a same wordline as the SRAM cell when the read operation is performed on the SRAM cell; and when the read operation is performed on the SRAM cell, turn off all switch-boxes of SRAM cells of the array not connected to the same wordline as the SRAM cell.