Patent ID: 7656203

Claim:
A receiving circuit, for receiving a first data signal and a clock signal to generate a first output data signal to a data driver, the first data signal and the clock signal being both reduced swing differential signals (RSDSs), the receiving circuit comprising: a first data comparator, driven by a data bias current, for receiving the first data signal to generate a first compared data signal; a first data intermediate circuit, for receiving the first compared data signal; a clock comparator, driven by a clock bias current, for receiving the clock signal to generate a first compared clock signal; a first clock intermediate circuit, for receiving the first compared clock signal; and a first flip-flop, for receiving the first compared data signal, transmitted from the first data intermediate circuit, and the first compared clock signal, transmitted from the first clock intermediate circuit, so as to generate the first output data signal; wherein at least one of the clock bias current and the data bias current is adjusted such that the setup time and the hold time formed by the first compared data signal and the first compared clock signal match the setup time and the hold time required by the first flip-flop.