Patent ID: 6972985

Claim:
A memory comprising: address lines operable to carry addresses; control lines operable to carry control signals; data lines operable to carry data; array lines; an address decoder that decodes the address on the address lines and activates certain array lines; drivers that, as a function of the control signals, can cause some array lines to be placed at a first write voltage, a second write voltage, or a read voltage; two-terminal memory plugs, each two-terminal memory plug electrically connected to at least one array line, the two-terminal memory plug being able to be reversibly written to a first resistive state when the some array lines are at the first write voltage, reversibly written to a second resistive state when the some array lines are at the second write voltage, and have its resistive state undisturbed when the some array lines are at the read voltage; wherein the two-terminal memory plugs include memory elements that have island structures of a first material within the bulk of a second material.