Patent ID: 7372736

Claim:
A method for operating a nonvolatile memory array comprising the steps of: forming said nonvolatile memory array on a substrate, said forming comprising the steps of: arranging a plurality of nonvolatile memory cells in rows and columns, each nonvolatile memory cell comprising: a source region placed within a surface of said substrate, a drain region placed within the surface of said substrate at a distance from said source region, a tunneling insulation layer placed on said surface in a channel region between said source region and drain region, a floating gate placed over said tunneling insulation layer, said floating gate aligned with an edge of said source region and an edge of said drain region and having a width defined by a width of said edge of said source and said edge of said drain, and a control gate place over said floating gate and isolated from said floating gate by an insulating layer; connecting at least one of the nonvolatile memory cell serially to a gating transistor having a source connected to the drain region of one nonvolatile memory cell of the at least one nonvolatile memory cells, a drain connected to the bit line, and a gate connected for receiving a select gate signal to selectively apply a bit line voltage signal to the drain region; forming a plurality of bit lines, each bit line in communication with the drain region of all nonvolatile memory cells of one column of nonvolatile memory cells; forming a plurality of source lines, each source line connected to the source region of all nonvolatile memory cells on one row of nonvolatile memory cells; forming a plurality of word lines, each word line connected to the control gate of all nonvolatile memory cells one row of the nonvolatile memory cells; forming a plurality of select lines, each select line connected to the gate of the gating transistor of the at least one nonvolatile memory cell of one row of nonvolatile memory cells; and programming a selected nonvolatile memory cell is to place a charge upon the floating gate of said selected nonvolatile memory cell by the steps of: applying a moderately high positive voltage to the word line connected to the control gate of said selected nonvolatile memory cell; applying an intermediate positive voltage to the bit line in communication with the drain region of said selected nonvolatile memory cell such that the intermediate positive voltage is transferred to said drain region; applying a ground reference voltage the source line connected to the source of the selected nonvolatile memory cells; applying the ground reference voltage to the substrate such that the channel between the source region and the drain region is at the ground reference voltage and the moderately high positive voltage is applied between the control gate and the channel region of the selected nonvolatile memory cell; applying a very large positive voltage of from approximately +15V to approximately +22V to the select line connected to the gate of the gating transistor of the selected nonvolatile memory cell.