Patent ID: 8859912

Claim:
A coreless package substrate, comprising: a circuit buildup structure comprising at least a dielectric layer, at least a circuit layer provided respectively on the at least a dielectric layer, and a plurality of conductive elements formed in the at least a dielectric layer and electrically connected to the at least a circuit layer; a plurality of first electrical contact pads embedded in a lowermost one of the at least a dielectric layer and electrically connected to part of the conductive elements, wherein the first electrical contact pads are exposed from a surface of the lowermost dielectric layer; a plurality of metal bumps formed on an uppermost one of the at least a circuit layer; a dielectric passivation layer applied on an uppermost one of the at least a dielectric layer, the uppermost circuit layer and the metal bumps, and having a plurality of recesses from which the metal bumps are exposed, wherein the metal bumps are protruded from bottoms of the recesses; and second electrical contact pads formed in the recesses, engaged with the metal bumps, and being in contact with a top surface and a part of side surfaces of the metal bumps, wherein the second electrical contact pads are electrically connected to the metal bumps, for being electrically coupled to a semiconductor chip.