Patent ID: 7741882

Claim:
An output buffer circuit, comprising: an input node operable to receive an input signal associated with an input voltage range; a first output transistor of a first conductivity type having a source terminal connected to a voltage supply and a drain terminal connected to an output node, wherein the first output transistor is operable, when the input signal is at a high voltage in the input voltage range, to couple the output node to the voltage supply and wherein the voltage supply provides a voltage that exceeds the high voltage in the input voltage range; a second output transistor of a second conductivity type having a drain terminal connected to the output node and a source terminal connected to ground, wherein the second output transistor is operable, when the input signal is at a low voltage in the input voltage range, to couple the output node to ground; a current-limiting circuit coupled to a gate terminal of the first output transistor and operable to limit a current flowing through the gate terminal when the first output transistor is turned on, wherein the current-limiting circuit comprises: a first transistor having a source terminal connected to the supply voltage and a drain terminal connected to a first terminal of a high-impedance element; a second transistor having a drain terminal connected to a second terminal of the high-impedance element and a source terminal connected to ground; and the high-impedance element, which comprises at least a portion of a current mirror; and the output node operable to output an output signal associated with an output voltage range, wherein a high voltage of the output voltage range is substantially equal to the voltage provided by the voltage supply.