Patent ID: 7492658

Claim:
A dynamic random access memory (DRAM) device comprising: an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column; and refresh circuitry for refreshing data stored in the DRAM cells coupled to wordlines of a first set of rows as main data and for overwriting assistant data into the DRAM cells coupled to wordlines of a second set of rows in a self-refresh mode, the assistant data being opposite data to the main data and each row of the second set being adjacent to each row of the first set, the refresh circuitry including a mode entry detector for detecting an entry into the self-refresh mode to retain the main data and to overwrite the assistant data, the mode entry detector producing a first self-refresh mode signal when entry into the self-refresh mode is detected, a refresh producer for detecting a starting refresh address provided by an address counter for operation of the self-refresh mode in response to the first self-refresh mode signal, the refresh producer changing the address counter when the detected starting refresh address mismatches a predetermined address.