Patent ID: 7432567

Claim:
A semiconductor structure comprising: a semiconductor substrate including at least one nFET device region and at least one pFET device region, said device regions are separated by an isolation region; a first gate dielectric stack having a net dielectric constant greater than silicon dioxide located on a surface of said substrate and within said at least one nFET device region; a second gate dielectric stack having a net dielectric constant greater than silicon dioxide located on a surface of said substrate and within said at least one pFET device region, wherein said first gate dielectric stack is different from said second gate dielectric stack and wherein said first gate dielectric stack contains no net negative charge and said second gate dielectric stack contains no net positive charge; and a single metal layer located on said first gate dielectric providing an nFET gate stack having a band edge workfunction and said single metal layer is also located on said second gate dielectric stack providing a pFET gate stack having a ¼ gap workfunction.