Patent ID: 7208786

Claim:
A memory device comprising: a plurality of first electrodes; a plurality of second electrodes; a plurality of third electrodes; and a two-dimensional array of memory cells provided corresponding to intersections between the plurality of first electrodes and the plurality of second electrodes and to intersections between the plurality of second electrodes and the plurality of third electrodes; wherein each of the memory cells includes a first layer that includes a piezoelectrie material and a second layer including a ferroelectric material, one second electrode of the plurality of the second electrodes is provided between the first layer and the second layer, and the first layer and the second layer are provided between one first electrode of the plurality of first electrodes and one third electrode of the plurality of third electrodes; the memory device further comprising: a plurality of comparators, each of which is provided corresponding to a pair of one first electrode of the plurality of first electrodes and one third electrode of the plurality of third electrodes, one comparator being thereby provided for each row of the memory cells, each of the comparators having a first input and a second input that are directly connected to the one first electrode and the one third electrode, respectively.