Patent ID: 7212031

Claim:
A semiconductor device comprising: a plurality of universal logic cells; a power supply line; a ground line; a first interconnection; and a second interconnection, wherein each of said plurality of universal logic cells includes: an inverter whose input is connected to a first node; a first P-channel transistor whose gate, source and drain are connected to a second node, said power supply line and a fourth node, respectively; a first N-channel transistor whose gate, source and drain are connected to said second node, said ground line and a fifth node, respectively; a first transfer gate including a P-channel transistor whose gate is connected to said first node, wherein an input and an output of said first transfer gate are connected to said fourth node and an output terminal, respectively; a second transfer gate including an N-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said second transfer gate are connected to said fifth node and said output terminal, respectively; a second P-channel transistor whose gate, source and drain are connected to a third node, said power supply line and a sixth node, respectively; a second N-channel transistor whose gate, source and drain are connected to said third node, said ground line and a seventh node, respectively; a third transfer gate including a P-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said third transfer gate are connected to said sixth node and said output terminal, respectively; and a fourth transfer gate including an N-channel transistor whose gate is connected to said first node, wherein an input and an output of said fourth transfer gate are connected to said seventh node and said output terminal, respectively, wherein said first interconnection connects said third node, said fourth node and said fifth node of a first universal logic cell of said plurality of universal logic cells, and said second interconnection connects said power supply line and said first node of said first universal logic cell.