Patent ID: 7395538

Claim:
A data processing architecture, comprising: a plurality of processors connected in series and configured to process data, where the processors include a plurality of processing resources arranged in resource groups; a load balancer connected to a first one of the processors and configured to: receive data, and distribute the data across the processors for processing; and reorder logic connected to a last one of the processors and configured to: receive the data processed by the processors, reorder the data, and output the reordered data; where the first processor is configured to: receive the data from the load balancer, determine whether the data is intended for the first processor, process the data when the data is intended for the first processor, and forward the data to a second one of the processors without processing the data when the data is not intended for the first processor, where the first processor includes a bypass path for bypassing the processing of the data when the data is not intended for the first processor.