Patent ID: 8722489

Claim:
A method of fabricating a non-volatile memory, comprising: sequentially forming a tunneling dielectric layer and a first patterned conductive layer on a substrate; sequentially stacking a patterned inter-gate dielectric layer and a second patterned conductive layer on a first surface of the first patterned conductive layer and exposing a second surface of the first patterned conductive layer, the second surface being adjacent to the first surface; covering the substrate by a passivation layer and exposing a first sidewall of the first patterned conductive layer; forming a recess on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner; forming a source region in the substrate adjacent to the first sidewall of the first patterned conductive layer; removing a portion of the passivation layer on the second surface, such that the sharp corner of the first patterned conductive layer is exposed; and forming a drain region in the substrate outside a second sidewall of the first patterned conductive layer.