Patent ID: 7437696

Claim:
A method for determining a time response of a digital circuit, the time response dependent on a data delay of a data path of the digital circuit and on a clock delay of a clock signal, which causes storage of a data item on the data path, the method comprising determining the time response as a time difference between the data delay and the clock delay taking into account a check, and determining the check dependent on a data slew of a signal on the data path and a clock slew of the clock signal such that a positive time difference ensures the correct saving of the data item; and wherein the time difference is a hold time difference and the check is a hold timing check, the hold time difference being determined from a difference between the data delay and a sum of the clock delay and the hold timing check, the hold timing check being a maximum of a hold time function, which is dependent on the data slew and the clock slew.