Patent ID: 7138322

Claim:
A fabrication method for a semiconductor device comprising the steps of: (a) forming a gate electrode on a semiconductor region of a first conductivity type with a gate insulating film interposed therebetween; (b) forming extension implanted layers in the semiconductor region by implanting first impurities of a second conductivity type in the semiconductor region using the gate electrode as a mask and forming pocket implanted layers in the semiconductor region by implanting second impurities of the first conductivity type in the semiconductor region using the gate electrode as a mask; (c) after the step (b), forming fluorine implanted layers in upper portions of the extension implanted layers by implanting fluorine in the semiconductor region using the gate electrode as a mask; (d) after the step (c), forming extension diffused layers of the second conductivity type made from diffusion of the first impurities in top portions of the semiconductor region by performing first heat treatment and forming pocket diffused layers of the first conductivity type made from diffusion of the second impurities in portions of the semiconductor region under the extension diffused layers by performing the first heat treatment, (e) after the step (d), forming sidewalls made of an insulating film on walls of the gate electrode; (f) forming source/drain implanted layers in the semiconductor region by implanting third impurities of the second conductivity type in the semiconductor region using the gate electrode and the sidewalls as a mask; and (g) after the step (f), forming source/drain diffused layers of the second conductivity type made from diffusion of the third impurities in portions of the semiconductor region on the outer sides of the sidewall.