Patent ID: 8319281

Claim:
A semiconductor device comprising: a groove portion formed on a main surface of a semiconductor substrate; an insulating film formed on a surface of said groove portion; a gate electrode so formed as to be in contact with said insulating film in said groove portion; a source impurity region so formed as to be adjacent to said groove portion, and a drain impurity region so formed as to be vertically adjacent to said source impurity region, wherein upper ends of said gate electrode, which are portions in contact with said insulating film, are each located at a position identical with or deeper than the range Rp of an impurity introduced from the main surface of said semiconductor substrate with respect to said insulating film in order to form said source impurity region and above a lower surface of said source impurity region, and said range Rp is positioned at a depth apart from a depth position of an upper surface of said source impurity region in a depth direction, and said upper ends of said gate electrode, which are the portions in contact with said insulating film, are each positioned between a depth position of said range Rp and a depth position of said lower surface of said source impurity region.