Patent ID: 8334197

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming an interfacial layer on the semiconductor substrate; forming a high-k dielectric layer over the interfacial layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming a capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer after performing the annealing process; forming a metal layer over the barrier layer filling in a remainder of the trench after removing the capping layer; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.