Patent ID: 7737735

Claim:
An output circuit comprising: an output block having a first output transistor of a first conductivity type and a second output transistor of a second conductivity type which are connected in series between a common potential line and a source potential line; a predrive block for driving the output block based on an input signal; a first voltage source for generating a first bias voltage from the common potential; and a second voltage source for generating a second bias voltage from the source potential, wherein the predrive block has a first transistor of the first conductivity type driven by a first signal generated from the input signal to short-circuit a gate terminal of the first output transistor and the common potential line, a second transistor of the second conductivity type driven by a second signal generated from the input signal to short-circuit a gate terminal of the second output transistor and the source potential line, and a clamp unit connected between the gate terminal of the first output transistor and the gate terminal of the second output transistor to limit a potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit a potential of the gate terminal of the second output transistor to a value of not less than a second potential, a potential difference between the first potential and the common potential is not more than a gate-source breakdown voltage of the first output transistor, a potential difference between the second potential and the source potential is not more than a gate-source breakdown voltage of the second output transistor, the clamp unit has a third transistor of the first conductivity type controlled with the first bias voltage and a fourth transistor of the second conductivity type controlled with the second bias voltage, the third transistor and the fourth transistor are connected in this order between the gate terminal of the first output transistor and the gate terminal of the second output transistor, a difference between the first bias voltage and a threshold voltage of the third transistor is not more than the gate-source breakdown voltage of the first output transistor, and a difference between the second bias voltage and a threshold voltage of the fourth transistor is not more than the gate-source breakdown voltage of the second output transistor.