Patent ID: 7403146

Claim:
A decoder circuit having a plurality of grayscale voltage input terminals for receiving respective grayscale voltages, a plurality of digital signal input terminals receiving respective bit signals, and an output terminal, the grayscale voltages being divided into a first group and a second group, each of the grayscale voltages in the first group being higher than all of the grayscale voltages in the second group, the decoder circuit comprising: a first selection circuit having a plurality of transistors interconnected to select one of the grayscale voltages in the first group according to the bit signals and conduct the selected grayscale voltage to the output terminal; and a second selection circuit having a plurality of transistors interconnected to select one of the grayscale voltages in the second group responsive to the bit signals and conduct the selected grayscale voltage to the output terminal; wherein the transistors in the first selection circuit operate in a first substrate biased at a first potential and the transistors in the second selection circuit operate in a second substrate biased at a second potential lower than the first potential.