Patent ID: 7211466

Claim:
A method of making a stacked multichip package comprising the steps of: attaching a bottom integrated circuit die to a base carrier, the bottom die having a top surface and a bottom surface, wherein the bottom surface is attached to a top side of the base carrier and wherein the bottom die top surface has a central area and a peripheral area, the peripheral area including a plurality of first bonding pads; electrically connecting the bottom die to the base carrier by wirebonding first wires to the plurality of first bonding pads of the bottom die and to corresponding first leads on the top side of the base carrier; forming a continuous bead of adhesive material between the central area and the peripheral area on the top surface of the bottom die, wherein the bead has a predetermined height and wherein the bead does not extend to the first bonding pads; filling the central area on the top surface of the bottom die with a second adhesive material, wherein the second adhesive material is surrounded by the bead; attaching a bottom surface of a top integrated circuit die to the top surface of the bottom die with the adhesive material bead and the second adhesive material, wherein the bead causes the top die to be spaced from the bottom die such that the top die does not contact the first wires and wherein the top die has substantially the same length and width as the bottom die; and electrically connecting the top die to the base carrier by wirebonding second wires to second bonding pads located on a top surface of the top die and to corresponding second leads on the base carrier.