Patent ID: 7466615

Claim:
A data path coupled to a read/write circuit, comprising: a local input/output (LIO) line having first and second signal lines coupled to the read/write circuit; a global input/output (GIO) line having first and second signal lines; and a source follower circuit, wherein the source follower circuit includes: first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively, a gate coupled to the first and the second signal lines of the LIO respectively, and a source coupled together; a third NMOS transistor having a source coupled to the source of the first and the second NMOS transistors and a gate coupled to a reference voltage supply; and a fourth NMOS transistor having a drain coupled to a drain of the third NMOS transistor, a gate to which a selection signal is applied, and a source coupled to a ground.