Patent ID: 8214777

Claim:
A method for determining leakage current in a digital circuit integrated on a die, the method comprising: first providing, on the die and separate from the digital circuit, a first leakage monitor comprising at least one N-type transistor having a drain terminal connected to a first voltage source through a first branch of a first current mirror and having gate and source terminals connected to ground of the integrated circuit and corresponding to a first logical state of the digital circuit corresponding to an off state for a first plurality of N-type transistors in the digital circuit, wherein the first leakage monitor further comprises a first differential amplifier connected to the first voltage source through a second branch of the first current mirror such that current through the second branch of the first current mirror mirrors current through the at least one N-type transistor, wherein a total area of the at least one N-type transistor is determined in proportion to a total area of the first plurality of N-type transistors in the digital circuit, wherein the first differential amplifier generates a first leakage current value; second providing, on the die and separate from the digital circuit, a second leakage monitor comprising at least one P-type transistor having a drain terminal connected, through a first branch of a second current mirror, to ground and having gate and source terminals connected to a second voltage source of the integrated circuit, corresponding to a second logical state of the digital circuit corresponding to an off state for a second plurality of P-type transistors in the digital circuit, wherein the second leakage monitor further comprises a second differential amplifier connected to ground through a second branch of the second current mirror such that current through the second branch of the second current mirror mirrors current through the at least one P-type transistor, wherein a total area of the at least one P-type transistor is determined according to a total area of the second plurality of P-type transistors in the digital circuit, wherein the second differential amplifier generates a second leakage current value; and measuring the first leakage current value and the second leakage current value to determine a leakage current result based on the first leakage current value and the second leakage current value.