Patent ID: 7376817

Claim:
A processor comprising: a prediction circuit configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution, wherein a PSTLF event occurs for the first load instruction when a plurality of bytes accessed during execution of the first load instruction include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation; and a circuit coupled to the prediction circuit and coupled to receive the first load instruction, wherein the circuit is configured to generate one or more load operations responsive to the first load instruction and further responsive to the prediction from the prediction circuit, wherein the load operations are to be executed in the processor to execute the first load instruction, and wherein a number of the load operations is dependent on the prediction by the prediction circuit, and wherein, responsive to the prediction that the PSTLF event occurs, two or more load operations are generated, and wherein each load operation accesses a different portion of the plurality of bytes that are accessed responsive to the first load instruction, and wherein each load operation is independently executable in the processor to access the different portion of the plurality of bytes, and wherein the two or more load operations are generated prior to executing any of the two or more load operations and wherein, responsive to generating more than one load operation for the first load instruction, the circuit is configured to generate one or more arithmetic/logic unit (ALU) operations to merge the results of the two or more load operations to produce the result of the first load instruction.