Patent ID: 8442075

Claim:
An integrated circuit comprising: a core circuit to operate in a first clock domain; and an input/output (I/O) circuit to operate in a second clock domain different than the first clock domain, the I/O circuit to include a sequential circuit to send data to and receive data from the core circuit, and a control circuit to control operation of the sequential circuit via a timing offset signal; the core circuit to further transmit a test data sequence to the I/O circuit, receive a delayed transmission of the test data sequence from the sequential circuit of I/O circuit, compare the timing offset of the delayed transmission with a stored timing offset determined during a link training between the core and I/O circuit, and adjust the timing offset signal of the control circuit included in the I/O circuit if the timing offset of the delayed transmission and the stored timing offset differ; wherein the first clock domain comprises at least one of a different phase or a different frequency than the second clock domain.