Patent ID: 7546446

Claim:
An apparatus, providing for macro instruction level control of interrupt suppression within a microprocessor, the apparatus comprising: fetch logic, for fetching an extended macro instruction from memory, wherein said extended macro instruction comprises: instruction entities according to an existing instruction set, wherein said instruction entities comprise a first opcode within said existing instruction set that specifies first operations to be executed by the microprocessor, and wherein a pending interrupt would otherwise be processed prior to completing execution of corresponding micro instructions; an extended prefix, for specifying that interrupt processing be suppressed until execution of said first operations is completed, wherein suppression of interrupt processing is specified at an application program privilege level, and wherein said application program privilege level precludes execution of operating system level instructions; and an extended prefix tag, configured to indicate said extended prefix, wherein said extended prefix tag comprises a second opcode within said existing instruction set, and wherein said second opcode, according to conventional translation rules, specifies second operations to be executed by the microprocessor; a translator, coupled to said fetch logic, for translating said extended macro instruction into said corresponding micro instructions; and extended execution logic, coupled to said translator, for receiving said corresponding micro instructions, and for completing execution of said corresponding micro instructions to perform said first operations prior to processing a pending interrupt.