Patent ID: 6868017

Claim:
An integrated circuit device, comprising: a first memory that for inputting data into and/or outputting data from a second memory; and a processing unit in which at least one data flow is formed and in which at least part of the at least one data flow is reconfigurable, wherein the processing unit includes: a data processing section that processes data that is inputted from and/or outputted to the first memory; a first address outputting section that outputs a first address of data that is inputted and/or outputted between the first memory and the data processing section; and a second address outputting section that outputs a second address of data that is inputted and/or outputted between the first memory and the second memory, and wherein an accessing for the first memory and/or the second memory is determined by reconfiguring at least a part of a dataflow relating to the first address outputting section and/or the second address outputting section according to configuration of data flows configured in the data processing section or processing results of the data flows.