Patent ID: 7362630

Claim:
A semiconductor memory circuit on a semiconductor substrate comprising: a plurality of memory blocks on the semiconductor substrate, each of which includes a real cell array, a row redundancy cell array having at least a redundant word line, and a column redundancy cell array having at least a redundant column line; a plurality of row redundancy circuits on the semiconductor substrate, each of which is coupled to a corresponding memory block and includes a comparator configured to compare a failure row address with a row address signal including a block address signal and output a row hit signal to select a corresponding redundant word line when the row address signal coincides with the failure row address, the block address signal indicating one of the plurality of memory blocks; a plurality of column redundancy circuits on the semiconductor substrate, each of which is coupled to a corresponding memory block, configured to operate in response to an enable signal, and includes a comparator configured to compare a failure column address with a column address signal and output a column hit signal to select a corresponding redundant column line when the column address signal coincides with the failure column address; and a column redundancy selection circuit configured to receive the row hit signal and the block address signal, wherein the column redundancy selection circuit (i) outputs the enable signal to activate the memory block corresponding to the block address signal when the row hit signal is deactivated and (ii) outputs the enable signal to activate the memory block corresponding to the row hit signal when the row hit signal is activated.