Patent ID: 8305831

Claim:
A memory comprising: a first supply voltage node; a memory macro comprising bit cells and at least one logic device; a first circuit coupled to the memory macro, the first circuit comprising: a first regulator built from a first manufacturing process; and a second regulator built from a second manufacturing process different from the first manufacturing process; a first device coupled to the first supply voltage node and to the first circuit; and a second device coupled to the first supply voltage node and to the memory macro, wherein a second supply voltage node of the memory macro is configured to selectively receive power from the first supply voltage node through the first circuit and the first device, or through the second device, and the memory is configured to satisfy at least one of the following conditions: (1) the first regulator comprises: a first N-type device; and a first P-type device, wherein the first N-type device and the first P-type device are built from the first manufacturing process and configured to compensate for the bit cells; and (2) the second regulator comprises: a second N-type device; and a second P-type device, wherein the second N-type device and the second P-type device are built from the second manufacturing process and configured to compensate for the at least one logic device.