Patent ID: 8524548

Claim:
A method of forming a DMOS transistor comprising: providing a silicon-on-insulator (SOI) structure which includes a bulk region having a top surface; an insulator layer that touches the top surface of the bulk region, the insulator layer having a top surface and a bottom surface; and a single-crystal semiconductor region which includes: forming a doped body region, of a first conductivity type that touches the insulator layer, and a drift region of a second conductivity type that touches the insulator layer; forming a trench isolation structure that extends through the single-crystal region to touch the insulator layer forming a plurality of isolated regions of single-crystal semiconductor region; depositing a layer of pad oxide onto the single-crystal semiconductor region, followed by depositing a silicon nitride layer onto the pad oxide layer; forming a patterned photoresist layer on the top surface of the silicon nitride layer to form exposed regions on the silicon nitride layer; forming a hard mask by using the patterned photoresist layer as a mask to etch the exposed regions on the silicon nitride layer and the pad oxide layer to result in the formation of exposed regions on the surface of the single-crystal semiconductor region; using the hard mask, selectively etching the exposed regions on the surface of the single-crystal semiconductor region to form a plurality of openings through the single-crystal semiconductor region and the insulator layer, and thereby exposing a corresponding plurality of regions on the top surface of the bulk region of the silicon-on-insulator (SOI) structure, the plurality of openings having a plurality of side walls; forming a plurality of side wall spacers that touch the plurality of side walls of the plurality of openings; wet etching the bulk region through the plurality of openings to form a single cavity that lies below each of the plurality of openings; wherein the single cavity exposes a portion of the bottom surface of the insulator layer, the portion of the bottom surface of the insulator layer lying directly vertically below the drift region; forming a capping oxide layer that covers, but does not fill the plurality of openings; and planarizing the top surface of the silicon-on-insulator (SOI) structure to remove the pad oxide layer and portions of the capping oxide layer until the top surface of the single-crystal semiconductor region is exposed.