Patent ID: 8552493

Claim:
An apparatus comprising: a plurality of transistor segments arranged on a die, each transistor segment having an elongated annular shape with a length elongated in a first lateral direction and a width in a second lateral direction, each transistor segment including: a pillar of a semiconductor material, the pillar including a drift region that extends in a vertical direction through the die; a first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar; first and second field plates respectively disposed in the and second dielectric regions; wherein the transistor segments are arranged into a plurality of sections, a first section comprising a first row of transistor segments arranged in a side-by-side relationship in the second lateral direction with the second dielectric region of each transistor segment of the first section being merged, a second section comprising a second row of transistor segments arranged in the side-by-side relationship in the second lateral direction with the second dielectric region of each transistor segment of the second section being merged, the merged second dielectric region of the first section being separated from the merged second dielectric region of the second section in the first lateral direction by a dummy pillar of the semiconductor material, the dummy pillar having a width in the first lateral direction that is substantially smaller than the length of each transistor segment.