Patent ID: 8304755

Claim:
A three-dimensional (3D) semiconductor structure, comprising at least: a first cell, comprising: a first conductive line; a second conductive line; and a first doped region; and a second cell, stacked on the first cell, and the second cell comprising: another first conductive line, opposite to the first conductive line of the first cell; the second conductive line, formed between said two first conductive lines of the first and second cells, and the first and second cells sharing the second conductive line when the 3D semiconductor structure is programming and erasing; and a second doped region, the first and the second doped regions respectively directly contacting a bottom and a top of the second conductive line; wherein the first doped region and the second conductive line form a first diode of the first memory cell, and the second doped region and the second conductive line form a second diode of the second memory cell.