Patent ID: 7514757

Claim:
A semiconductor structure comprising: a static random access memory (SRAM) cell comprising a first pull-up MOS device, a first pull-down MOS device and a first pass-gate MOS device; a first metallization layer; an inter-layer dielectric (ILD) underlying the first metallization layer, wherein the ILD comprises an upper portion and a lower portion; a first first-layer contact in the lower portion of the ILD and connecting at least two of the first pull-up MOS device, the first pull-down MOS device and the first pass-gate MOS device, wherein the first first-layer contact is physically isolated from additional contacts in the upper portion of the ILD; a second first-layer contact in the lower portion of the ILD, wherein the semiconductor structure is free from materials of the ILD directly underlying, and contacting, the first first-layer contact; and a second-layer contact having at least a portion on the second first-layer contact, wherein the second-layer contact electrically connects the second first-layer contact to a bit-line or a power line.