Patent ID: 7080334

Claim:
A computer implemented method of deriving gated clock circuitry in an integrated circuit design comprising: identifying a sequential element in the design; identifying multiple respective feedback loops in the design associated with the identified sequential element; wherein each respective identified feedback loop alternatively provides load data or provide reload data to their associated sequential elements; for each respective identified feedback loop, producing a feedback loop signature associated with such sequential element, that indicates respective feedback elements associated with the feedback loop, indicates respective feedback positions at the indicated feedback elements associated with the feedback loop and indicates respective feedback control signals applied to the indicated feedback elements associated with the feedback loop; evaluating the respective feedback loop signatures so as to generate associated stimulus logic that receives as input at least one associated feedback loop control signal; provides as output an associated clock control signal that has a clock enable value during clock intervals when an associated load value would be provided to such sequential element by its associated feedback loop and that has a clock disable value during clock intervals when an associated reload value would be provided to such sequential element by its associated feedback loop; generating associated load logic, that receives as input at least one associated feedback loop control signal; and provides as output at least one load data signal during clock intervals when the associated stimulus logic signature produces an associated clock control signal with a clock enable value.