Patent ID: 8713417

Claim:
A memory system, comprising: first and second memory devices; and a memory controller configured during a read operation to read encoded data stored in both of the first and second memory devices via respective first and second communication channels, wherein the first communication channel communicates a first data set of the encoded data from the first memory device to the memory controller in parallel with the second communication channel communicating a second data set of the encoded data from the second memory device to the memory controller, the memory controller comprising: a first error detector dedicated to the first communication channel and configured to generate first values indicating first errors in the first data set, and a second error detector dedicated to the second communication channel and configured to generate second values indicating second errors in the second data set in parallel with the generation of the first values; a multiplexer that selects between the first and second values to generate multiplexed error detection information; and an error corrector configured to correct the first and second errors in the first and second data sets in response to the multiplexed error detection information.