Patent ID: 7020005

Claim:
A method for operating a ferroelectric or electret memory device employing passive matrix addressing, wherein said memory device comprises cells in the form of a ferroelectric or electret thin-film polarizable material exhibiting hysteresis, particularly a ferroelectric or electret polymer thin film, and a first and second set of respective parallel electrodes, wherein the electrodes of the first set, termed word lines (WL), are provided in substantially orthogonal relationship to the electrodes of the second set, termed bit lines (BL), wherein the electrodes of said first and second set are provided in direct or indirect contact with the thin-film material of the memory cells, wherein a cell in the device can be set to a polarization state X or Y or switched between these by applying a switching voltage (V s ) larger than a coercive voltage (V c ) corresponding to a coercive field (E c ) of the polarizable material between a word line (WL) and a bit line (BL) addressing the cell, wherein the method comprises a voltage pulse protocol with at least one disturb generating operation cycle for switching selected addressed cells (Ax) to polarization state X, the disturb generating operation cycle involving selected addressed cells located in or at the crossing of addressed word lines (AWL) and selected bit lines (BLx), non-selected addressed cells (Ay) located in the intersection of the addressed word lines and non-selected bit lines (BLy), unaddressed cells (Dx) located in the intersection of unaddressed word lines (UWL) and the selected bit lines, and unaddressed cells (Dy) located in the intersection of the unaddressed word lines and the non-selected bit lines, wherein during the disturb generating operation cycle the potential difference between the addressed word lines and the selected bit lines is equal to the switching voltage, and the potential difference between the addressed word lines and the non-selected bit lines is less than the magnitude of the coercive voltage, and wherein the method is characterized by introducing a pre-disturb and/or post-disturb cycle before and after the disturb generating operation cycle respectively, during which cells along unaddressed word lines receive non-switching voltages and at least some non-zero voltages, producing pre- and/or post-disturb cell voltage pulses in the respective pre- and/or post disturb cycle by keeping the potential difference between unaddressed word lines and the addressed word line equal to or less than twice the magnitude of the coercive voltage, selecting the selected bit line potentials and non-selected bit line potentials such that the difference to the unaddressed word line potential is less than the magnitude of the coercive voltage and selecting the addressed word line potential such that the addressed cells only may receive voltages with magnitudes larger than the coercive voltage in the direction of the polarization state already set in the addressed cells.