Patent ID: 7803673

Claim:
A method of manufacturing a thin film transistor substrate, the method comprising: sequentially forming a gate insulating film and an active layer on a substrate, the substrate having a gate wire including a gate line and a gate electrode connected to the gate line formed thereon; forming a data metal layer on the active layer, the data metal layer including a first metal layer, a second metal layer and a third metal layer disposed, in sequence; forming a first photoresist pattern on the data metal layer, the first photoresist pattern having a thinner thickness at a channel region than at an adjacent region; dry-etching the third metal layer by using the first photoresist pattern; simultaneously dry-etching the second metal layer and the first metal layer by using the first photoresist pattern to form a data line; dry-etching the active layer by using the first photoresist pattern; removing a portion of the first photoresist pattern to form a second photoresist pattern by which the channel region is removed; and forming a source electrode connected to the data line and a drain electrode spaced apart from the source electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.