Patent ID: 8539315

Claim:
A semiconductor storage device comprising a nonvolatile semiconductor memory, a power supply unit, and a first controller, wherein the nonvolatile semiconductor memory comprises: a memory cell array including blocks each including memory cells; and a second controller configured to control writing of data to, reading of data from, and erasing of data from the memory cells, the memory cell array comprises: a firmware area capable of storing firmware used to execute either a normal mode in which the first controller performs an operation corresponding to an instruction from a host device or an autorun test mode in which the first controller conducts a specific test, regardless of an instruction from the host device; and a user area capable of storing user data, the power supply unit configured to receive a power supply from outside the semiconductor storage device and to supply a specific voltage to the nonvolatile semiconductor memory and the first controller, the first controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode when having received a voltage from the power supply unit, and performs a first process, a second process, and a third process in that order when the firmware has been set in the autorun test mode, the first process includes writing data to a block in the user area using a first cell applied voltage higher than a voltage used in the normal mode, and not entering a block where an error has occurred as a bad block even when the error has occurred at the time of the writing, the second process is used in the normal mode and includes repeating erasing and writing in each block in the user area using a second cell applied voltage lower than the first cell applied voltage, and not entering a block where an error has occurred as a bad block even when the error has occurred at the time of the writing, and the third process includes repeating erasing, writing, and reading in each block in the user area using the second cell applied voltage, and entering a block where an error has occurred as a bad block when the error has occurred at the time of erasing or when the error has occurred at the time of the writing.