Patent ID: 7373458

Claim:
A cache memory system comprising: a first cache memory; a second cache memory; a first port arranged to receive a request for a first item and determine whether the first item is in the first cache memory; a second port arranged to receive a request for a second item and determine whether the second item is in the second cache memory, wherein the first port is arranged to receive one of tagged and untagged requests and the second port is further arranged to receive the other of tagged and untagged requests, wherein the request for the first item and the request for second item can be simultaneously received at the first port and the second port, respectively, and the second port is arranged to determine whether the second item is in the second cache memory while the first port is determining whether the first item is in the first cache memory, and wherein the cache memory system is arranged such that if the second item is determined not to be in the second cache memory, a request for the second item is sent to the first port; and a third port associated with the second cache memory and arranged to receive the request for the first item and to determine whether the first item is in the second cache memory, wherein the first and third ports are arranged such that they can receive the request for the first item substantially simultaneously.