Patent ID: 7531878

Claim:
A semiconductor device comprising: an SOI substrate in which a support substrate, an SOI layer and an oxide film layer formed between said support substrate and said SOI layer, said SOI layer having a semiconductor surface of a first crystal plane, and a <100> crystal direction of said SOI layer is aligned with a <110> crystal direction of the support substrate; and a P-channel MIS transistor including a gate insulating film formed on said semiconductor surface of said SOI layer, a gate electrode extending in a first direction and formed on said gate insulating film, P-type active layers aligned in a second direction which is perpendicular to said first direction and formed at both sides of said gate electrode, and a N-type body layer formed under said gate electrode and between said P-type active layers; a N-type active layer for body voltage application which is formed on said crystal plan of said SOI layer; a N-type path portion connecting said N-type body layer and said N-type active layer for body voltage application; and said second direction is aligned to said <100> crystal direction of said SOI layer; and said support substrate having a semiconductor surface which is the equal crystal plane as said crystal plane of said SOI layer, and said oxide film is formed on said semiconductor surface of said support substrate; wherein said first crystal plane is (100) plane, further comprising: a first insulating film formed between said N-type path portion and said gate electrode, wherein said first insulating film is thicker than said gate insulating film.