Patent ID: 8300483

Claim:
A timing adjustment circuit comprising: a determination unit configured to output delay information corresponding to a period of a first input signal; a storing unit configured to store a plurality of correction values in accordance with a circuit included in the determination unit; a correction unit configured to correct the delay information based on a correction value selected from the plurality of the correction values, in accordance with the delay information; and a first delay line configured to delay a second input signal corresponding to the first input signal, in accordance with the delay information corrected by the correction unit, wherein the determination unit includes a second delay line and a wire coupled to the second delay line, and wherein the plurality of correction values are generated based on a difference between a first delay amount corresponding to the period of the first input signal and a second delay amount corresponding to the period of the first input signal, the first delay amount being measured based on a timing of the first input signal and a timing of a signal transmitted through the second delay line and the wire, and the second delay amount being measured based on the timing of the first input signal and a timing of a signal transmitted through the second delay line.