Patent ID: 7768754

Claim:
A device comprising: a ceramic substrate having a top surface and a bottom surface, the ceramic substrate providing electrostatic discharge (ESD) protection of a semiconductor device mounted over the top surface, the ceramic substrate comprising a first layer containing a first metal oxide, a first surface of the first layer being the top surface of the ceramic substrate, the first layer forming a metal oxide varistor that provides electrostatic discharge (ESD) protection of the semiconductor device mounted over the first surface of the first layer, the ceramic substrate also comprising a second layer containing a ceramic second material that does not contain any first metal oxide, the second layer not forming a varistor, a second surface of the second layer forming the bottom surface of the ceramic substrate; a first metal layer overlying a portion of the first surface of the first layer; a second metal layer in contact with the first layer between the first layer and the second layer; a first electrode area electrically coupled to the first metal layer to which a first electrode of the semiconductor device is electrically connected when mounted over the first surface; a second electrode area electrically coupled to the second metal layer to which a second electrode of the semiconductor device is electrically connected when mounted over the first surface, whereby the first metal layer, the first layer, and the second metal layer form a low resistance path between the first electrode area and the second electrode area when a voltage between the first electrode area and the second electrode area exceeds a threshold.