Patent ID: 7802213

Claim:
A method to design a circuit module, the method comprising: generating a plurality of circuit designs for a module, the plurality of the circuit designs corresponding to the module with a plurality of different latencies; determining a plurality of admissible clocks for the plurality of circuit designs, each of the plurality of admissible clocks representing a feasible clock period for a corresponding one of the plurality of circuit designs; and generating design data to relate the plurality of admissible clocks with the plurality of different latencies to determine a circuit design having latency suitable for a desired clock of a larger circuit design including the module, wherein the generating a plurality of circuit designs, the determining a plurality of admissible clocks, and the generating design data are performed on a representation of circuit design, the representation being stored in a memory of a data processing system which includes a processor which performs the generating circuit designs, the determining admissible clocks, and the generating design data.