Patent ID: 7185042

Claim:
An adder circuit comprising: a first adder cell having: a first logic gate having a first input that receives a first input signal, a second input that receives a second input signal, and a first output that generates a first logic signal, the first input signal, the second input signal, and the first logic signal each having a logic state, the first logic gate generating the first logic signal in response to the logic states of the first and second input signals, the first logic gate generating an inverted first input signal in response to the first input signal; a first inverter circuit having a third input that receives a third input signal, a fourth input connected to receive the first logic signal, a first output that generates an inverted third signal, and a second output that generates an inverted first logic signal; a first carry out circuit having a first control input connected to receive the first logic signal, a second control input connected to receive the inverted first logic signal, and an output, the carry out circuit including a first multiplexer that passes a first received signal to the output of the first carry out circuit when the first logic signal has a first logic state, and passes a second received signal to the output of the first carry out circuit when the first logic signal has a second logic state, the first received signal being the first input signal; and a first sum circuit having a first control input connected to receive the first logic signal, a second control input connected to receive the inverted first logic signal, a first sum input connected to the third input signal, a second sum input connected to the inverted third signal, and an output, the second sum input and the output of the first sum circuit not be directly connected together.