Patent ID: 8650382

Claim:
A processor, comprising: instruction fetch circuitry to fetch a first instruction and a second instruction, the instruction format of the first instruction indicating a first packed source register to store a first packed source operand and indicating a first packed destination register to store a first packed result operand, the instruction format of the second instruction indicating a second packed source register to store a second packed source operand and a second packed destination register to store a second packed result operand; instruction decode circuitry to decode the first instruction and the second instruction; instruction execution circuitry to execute the first instruction and the second instruction, the instruction execution circuitry to generate the first packed result operand in response to the first instruction and to generate the second packed result operand in response to the second instruction, the execution of the first instruction to copy bits [ 31 - 0 ] of the first packed source operand to bits [ 63 - 32 ] and [ 31 - 0 ] of the first packed result operand and to copy bits [ 95 - 64 ] of the first packed source operand to bits [ 127 - 96 ] and [ 95 - 64 ] of the first packed result operand, the execution of the second instruction to copy bits [ 63 - 32 ] of the second packed source operand to bits [ 31 - 0 ] and [ 63 - 32 ] of the second packed result operand and to copy bits [ 127 - 96 ] of the second packed source operand to bits [ 95 - 64 ] and [ 127 - 96 ] of the second result operand wherein the instruction format of the first instruction and the instruction format of the second instruction do not include respective input operand information to specify the above copy patterns performed by the instruction execution circuitry.