Patent ID: 8026602

Claim:
A fabrication method of a semiconductor device having conductive bumps, comprising the steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with the semiconductor substrate covered by and a portion of the solder pad exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the passivation layer and the first metal layer; forming an aperture on the covering layer for exposing a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad, and a deviation distance between the centers of the aperture and the solder pad is smaller than half a width of the solder pad; disposing a metal pillar on the portion of the first metal layer; and disposing a solder material on the metal pillar.