Patent ID: 8318603

Claim:
A method of forming patterns for a semiconductor device, the method comprising: forming a first layer on a substrate comprising a first region and a second region, wherein the first layer covers the first region and the second region; forming both a first blocking pattern covering a portion of the first layer in the first region and a second blocking pattern covering a portion of the first layer in the second region simultaneously; forming a sacrificial layer over the first and second regions, including: over the first layer and the first blocking pattern in the first region and over the second blocking pattern in the second region; patterning the sacrificial layer exclusively in the first region to form a sacrificial mask pattern on the first layer and on the first blocking pattern in the first region, segments of the sacrificial mask pattern being integrally connected to each other; using a single spacer layer to form a plurality of spacers covering exposed sidewalls of the sacrificial mask pattern; removing the sacrificial mask pattern from the first and second regions; and etching the first layer in the first and second regions by using the plurality of spacers and the first blocking pattern as etch masks in the first region and using the second blocking pattern as an etch mask in the second region.