Patent ID: 7885612

Claim:
A semiconductor device comprising: an antenna; a demodulation circuit operationally connected to the antenna; a clock generation circuit operationally connected to the demodulation circuit; a modulation circuit operationally connected to the antenna; and a switch operationally connected to the clock generation circuit, wherein the clock generation circuit comprises a PLL circuit, an oscillator circuit and a determination circuit, wherein, in a signal input portion, the determination circuit is a circuit which determines a first period from receiving a reception start signal to receiving a reception end signal and a second period except for the period from receiving a reception start signal to receiving a reception end signal by the clock generation circuit, and wherein the switch selects an input signal in the first period to be inputted to a signal input portion of the PLL circuit and a signal of the oscillator circuit in the second period to be inputted to the signal input portion of the PLL circuit.