Patent ID: 7049875

Claim:
A circuit for providing automatic setting and linearization of the resistance of on-chip MOS resistors of a first conductivity type for processing a differential signal having a common mode reference voltage comprising an integrated circuit having: a FET of the first conductivity type having a source, a drain, a gate and a substrate; and, control circuitry coupled to the FET and adapted to be responsive to a control resistance to apply a voltage differential between the source and drain centered about a common mode reference voltage, and to control the gate to provide a current I through the FET, whereby a control resistance may set the resistance of the FET at the voltage differential divided by the current I through the FET; the substrate of the FET being coupled to the same voltage as the substrates of the on-chip MOS resistors, the gate of the FET being coupled to gates of the on-chip MOS resistors.