Patent ID: 7975253

Claim:
A circuit board power supply noise analysis model generating method executed by a computer, the method comprising: extracting, by a computer, power supply pairs, each of the power supply pairs including an overlapping part of power supply islands in different layers of the circuit board, a first power supply pair being one of the power supply pairs, the first power supply pair between a first power supply island on a first layer and a second power supply island on a second layer, a second power supply pair being one of the power supply pairs, the second power supply pair between the second power supply island and a third power supply pair on a third layer, the second layer between the first layer and the third layer; arranging nodes in each of the power supply pairs based on CAD data of the circuit board, first nodes being some of the nodes, the first nodes in the first power supply pair, second nodes being some of the nodes, the second nodes in the second power supply; setting the first nodes and the second nodes to the second power supply; calculating impedance between the nodes; and creating a circuit board power supply noise analysis model based on the calculated impedance between the nodes.