Patent ID: 7596022

Claim:
A method for programming multi-level non-volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells, each of the plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data, the data represented by a least significant bits (LSBs) and a most significant bits (MSBs), the method comprising: programming the storage cells first with LSBs and then with MSBs such that each of the programmed storage cells: has a threshold voltage lower than a voltage VR 1 when it is desired that the storage cell store a first value; has a threshold voltage greater than the voltage VR 1 and lower than a voltage VR 2 when it is desired that the storage cell store a second value; has a threshold voltage greater than the voltage VR 2 and lower than a voltage VR 3 when it is desired that the storage cell store a third value; and has a threshold voltage greater than a voltage VR 3 when it is desired that the storage cell store a fourth value; wherein VR 1 <VR 2 <VR 3 ; and programming the flag cell to have a threshold voltage greater than the voltage VR 3 to indicate that the MSBs have been programmed.