Patent ID: 7526350

Claim:
A digital processing integrated circuit to process media data, the integrated circuit including: a data path arranged within the integrated circuit in a ring configuration to communicate the media data at different sampling rates synchronized with a sample-locked rate; a plurality of processing modules positioned within the data path to process the media data; a routing controller; and a digital interface to communicate with a device external to the integrated circuit, wherein the data path comprises a plurality of separate portions to communicate data between adjacent of the processing modules, the separate portions of the data path to couple the adjacent processing modules in series to communicate the media data between the adjacent processing modules, wherein the routing controller is configured to clock the media data in time-slots between the adjacent processing modules around the separate portions of the data path to provide communications from a source processing module to a target processing module, wherein a number of the time-slots available for each of the different sampling rates is inversely related to each different sampling rate, and wherein each processing module is assigned a fixed output time-slot and a variable input time-slot.