Patent ID: 7923828

Claim:
A chip package comprising: an integrated circuit chip having terminals exposed at an exterior thereof; and an interconnect element external to said integrated circuit chip and mounted to said terminals of said chip with a bond metal, said interconnect element comprising: a dielectric element external to said chip, said dielectric element having a first major surface, a second major surface remote from said first major surface, and a plurality of recesses extending inwardly from said first major surface; a plurality of metal traces embedded in said plurality of recesses, said metal traces having outer surfaces substantially co-planar with said first major surface and inner surfaces remote from said outer surfaces, said plurality of metal traces including a first metal; a plurality of posts extending from said inner surfaces of said plurality of metal traces through said dielectric element, said plurality of posts having tops exposed at said second major surface and said plurality of posts including a second metal, at least one of said plurality of metal traces or said plurality of metal posts being exposed at one of said first or second major surfaces of said interconnect element; a plated metal layer including a third metal adjacent surfaces of said posts and being disposed between each of said plurality of posts and said plurality of metal traces, said plated metal layer having a composition and sufficient thickness such that said plated metal layer is capable of protecting said surfaces of said posts from attack during an etching process in which an etchant which attacks said second metal is used to remove a portion of said second metal not protected by said plated metal layer, and a bond metal electrically connecting said at least one of said plurality of said metal traces or said plurality of said metal posts with said terminals of said integrated circuit chip.