Patent ID: 8218386

Claim:
An application specific integrated circuit (ASIC) device comprising a DRAM embedded within the ASIC device, said DRAM further including: a) a plurality of memory arrays including: i. word lines extending in a first direction, ii. bit lines extending in a second direction orthogonal to the first direction, and iii. charge storage cells formed at intersections of said word lines and said bit lines; b) a plurality of strips of bit line sense amplifiers extending in the first direction, the bit line sense amplifiers electrically connected to said bit lines; c) a plurality of pairs of data bus lines extending in the second direction; d) array select circuitry to apply data to or from a selected one of said strips of sense amplifiers from or to said pairs of data bus lines; e) a plurality of inputs or outputs; and f) a plurality of data bus sense amplifiers, each data bus sense amplifier electrically connected between one of said pairs of data bus lines and one of said inputs or outputs that is distinct to said one of said pairs of data bus lines.