Patent ID: 8890607

Claim:
A stacked chip system, comprising: a first chip; a second chip; a first group of through silicon vias (TSVs) connecting the first chip and second chip, comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV; a second group of through silicon vias (TSVs) connecting the first chip and second chip, comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.