Patent ID: 8667450

Claim:
A method of validating integrated circuit designs built with encrypted silicon IP blocks comprising: a computer system comprising a processor, a memory, and a bus connecting said memory to said processor; said processor parsing a design rule check (DRC) rule file; said processor reading an integrated circuit design layout database; said processor finding encrypted structures (said encrypted silicon IP blocks) and unencrypted structures from said integrated circuit design layout database; said processor decrypting said encrypted structures to get decrypted structures; said processor extracting polygons and texts from said decrypted structures and said unencrypted structures; said processor performing design rule checks on said polygons and said texts and finding rule violations based on a scan-line algorithm; and said processor writing said rule violations to a partially encrypted violation database, and when writing, said rule violations generated from said polygons and said texts from said decrypted structures are encrypted and saved in an encryption section of said partially encrypted violation database.