Patent ID: 8310889

Claim:
A semiconductor device comprising: a plurality of memory cells arranged in a matrix pattern; a write amplifier which writes write data to one of the memory cells in synchronization with a clock; a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock; a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier; a column address decoder which sets a column select switch corresponding to a memory cell of one column among the plurality of the memory cells to a conductive state based on a column address; a row address decoder which activates memory cells of one row among the plurality of the memory cells based on a row address; and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal, wherein the test write circuit includes a driving unit and outputs the test signal to the driving unit when the test mode signal is in an enable state, the test write circuit and the write amplifier use the driving unit in common.