Patent ID: 8117583

Claim:
An integrated circuit layout design supporting device for building a chip by dividing the chip into a plurality of macro blocks, which are pieces of a design unit of the chip, and performing layout processing of each of the macro blocks in parallel, comprising: a center point coupling function calculating part which treats, as individually identifiable specific macro blocks, same-function macro blocks among the plurality of macro blocks as targets of layout, and draws coupling lines connecting between each of center points of hierarchy macro blocks that are in a connected relation; an intersection coordinate calculating part which calculates intersection points at which the coupling lines drawn by the center point coupling function calculating part intersect with boundary lines of the macro blocks or intersection parts at a vicinity area thereof; a terminal arrangement processing part which performs processing for arranging macro terminals to the intersection points or the intersection parts calculated by the intersection coordinate calculating part; and a layout processing control unit which performs, to build the chip, wiring processing of the macro blocks once on all macro terminals set at different coordinates of the specific macro blocks, and deletes extra wiring whose connection between the macro blocks is uncompleted.