Patent ID: 7434185

Claim:
A method for distributed processing of IC graphical design data to verify or check an IC physical design that partitions the IC graphical design data into pieces that support scaling in view of available network resources for processing the pieces, the method comprising steps of: partitioning the IC graphical design data into files by a host machine, wherein the files correspond to regions of interest within the IC graphical design data; dispersing the partitioned IC graphical design data files to available CPUs within a network; processing of each job by one of the available CPUs receiving the partitioned IC graphical design data files, wherein artifacts arising from bisection of partitioning margins during the partitioning, which could generate cut-induced false errors if not removed from the partitioned IC graphical design data files, are detected and removed, and shape-altering effects of such artifact errors are minimized; and transmitting results of the processing at each CPU to the host machine for aggregate processing, wherein smaller jobs support improved scalability and shorter aggregate real check times.