Patent ID: 7180788

Claim:
A non-volatile semiconductor memory device, comprising: plural memory cells situated at respective intersections of plural word lines extending in a first direction of a memory mat and plural local bit lines extending in a second direction, perpendicular to the first direction, wherein one end of each of two local bit lines that are disposed adjacent to each other, among the plural local bit lines, are connected with one global bit line at the end of the memory mat, and one of the two local bit lines that are adjacent to each other is selected by a selection MOS transistor connected to each of the plural local bit lines, and wherein plural memory mats, each having an identical constitution, are situated along the second direction, and two local bit lines, which are adjacent to each other and are formed in one of the memory mats, and two local bit lines, which are adjacent to each other and are formed in another memory mat, are connected with one global bit line at the boundary between the two memory mats.