Patent ID: 8664070

Claim:
A method for fabricating an integrated circuit device, the method comprising: providing a substrate; forming a gate structure that includes a dummy gate over the substrate; forming a heavily doped source/drain feature in the substrate adjacent the dummy gate; after forming the heavily doped source/drain feature in the substrate adjacent the dummy gate, forming a first interlevel dielectric layer over the substrate including over the gate structure, such that the dummy gate is exposed, wherein the first interlevel dielectric layer completely covers the heavily doped source/drain feature; performing a gate replacement process that replaces the dummy gate of the gate structure with a gate, wherein the gate replacement process includes a first annealing process, wherein the first interlevel dielectric layer completely covers the heavily doped source/drain feature while performing the gate replacement process; after the first annealing process, forming a second interlevel dielectric layer over the first interlevel dielectric layer; removing portions of the first interlevel dielectric layer and the second interlevel dielectric layer to form a contact opening that extends through the first interlevel dielectric layer and the second interlevel dielectric layer to expose a portion of the substrate; forming a silicide feature on the exposed portion of the substrate through the contact opening that extends through the first interlevel dielectric layer and the second interlevel dielectric layer, wherein forming the silicide feature includes depositing a metal layer on the exposed portion of the substrate and performing a second annealing process to form the silicide feature; and filling the contact opening to form a contact to the exposed portion of the substrate.