Patent ID: 7739638

Claim:
A method for analyzing a signal propagation delay of a circuit part including a plurality of input nodes and a plurality of output nodes, the method comprising: inputting a first input signal pattern to an input port of a circuit part to be analyzed; inputting a second input signal pattern to a node of a peripheral circuit that is peripheral to the circuit part to be analyzed, the node of the peripheral circuit being a node that does not logically affect an operation of the circuit part to be analyzed but is configured to affect a signal propagation delay of the circuit part to be analyzed; analyzing, by a computer, a signal propagation delay of the circuit part to be analyzed corresponding to the first input signal pattern inputted to the circuit part to be analyzed and the second input signal pattern inputted to the peripheral circuit; extracting a node of the peripheral circuit, the node to be extracted being a node that does not logically affect the operation of the circuit part to be analyzed but is configured to affect a signal propagation delay of the circuit part; and inputting the second input signal pattern to the extracted node of the peripheral circuit.