Patent ID: 7881146

Claim:
A semiconductor memory apparatus comprising: a first bank block; a second bank block; an address decoding unit configured to receive an address signal and to provide a decoded row address signal, a first decoded bank address signal group for providing the first bank block, and a second decoded bank address signal group for providing the second bank block; a first switching unit coupled with the address decoding unit, the first switching unit configured to receive the decoded row address signal, to transmit the decoded row address signal into the first bank block when the first decoded bank address signal group is activated, and to block the decoded row address signal when the first decoded bank address signal group is deactivated; and a second switching unit coupled with the address decoding unit, the second switching unit configured to receive the decoded row address signal, to transmit the decoded row address signal into the second bank block when the second decoded bank address signal group is activated, and to block the decoded row address signal when the second decoded bank address signal group is deactivated.