Patent ID: 7906422

Claim:
A method for fabricating a chip, comprising: providing a silicon substrate, a transistor in or on said silicon substrate, a first metal layer over said silicon substrate, a second metal layer over said first metal layer and said silicon substrate, a dielectric layer between said first and second metal layers, a conductive pad over said silicon substrate, and a passivation layer over said silicon substrate, said first and second metal layers and said dielectric layer, wherein a first opening in said passivation layer is over a contact point of said conductive pad, and said contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers; forming a first organic layer on said passivation layer, wherein said first organic layer has a thickness between 1 and 100 micrometers, wherein a second opening in said first organic layer is over said contact point; forming a third metal layer on a top surface of said first organic layer and on said contact point, wherein said third metal layer comprises titanium; forming a photoresist layer on said third metal layer, wherein a third opening in said photoresist layer exposes a region of said third metal layer; electroplating a fourth metal layer on said region, wherein said fourth metal layer comprises copper; after said electroplating said fourth metal layer, removing said photoresist layer; and after said removing said photoresist layer, removing said third metal layer not under said fourth metal layer.