Patent ID: 7936594

Claim:
A semiconductor memory device comprising: a data input/output line; a plurality of memory banks each comprising a plurality of memory cells; a first global bit line and a second global bit line which are connected to the plurality of memory banks; and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively, wherein each of the memory banks comprises: a first cell area connected with the first global bit line; and a second cell area connected with the second global bit line, wherein in a normal write mode, either of the first or second cell areas is selected in one of the plurality of memory banks and data is written to a memory cell in the selected cell area, and wherein in a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, the semiconductor memory device further comprising: a plurality of first local bit lines connected with the first cell area and selectively connected with the first global bit line; a plurality of second local bit lines connected with the second cell area and selectively connected with the second global bit line; a first local selection circuit configured to select a local bit line in one of the first or second cell areas based on an address signal and a first area selection signal; and a second local selection circuit configured to select a local bit line in the other of the first or second cell areas based on the address signal and a second area selection signal.