Patent ID: 7026225

Claim:
A method for precluding stress-induced void formation in a semiconductor component, comprising: providing a semiconductor substrate; forming a first portion of a metallization system above the semiconductor substrate, the first portion vertically spaced apart from the semiconductor substrate by a first distance, wherein forming the first portion includes: forming a first layer of dielectric material over the semiconductor substrate; forming a first opening in the first layer of dielectric material, the first opening having a surface, wherein at least one dielectric protrusion extends from the surface of the first opening; forming a second opening in the first layer of dielectric material, the second opening having a surface, wherein at least one dielectric protrusion extends from the surface of the second opening; and forming an electrically conductive material in the first and second openings; and forming a second portion of the metallization system, the second portion coupled to the first portion and vertically spaced apart from the semiconductor substrate by a second distance, the second distance different from the first distance, wherein said at least one dielectric protrusion extends from the first layer of dielectric material only from the bottom of the at least one dielectric protrusion.