Patent ID: 8345583

Claim:
An Ethernet channel impairment enhancement apparatus, comprising: a transmitter with a first channel and other channels; a receiver; an adder configured to couple the receiver; an echo canceller configured to couple between the first channel of the transmitter and the adder and having an echo cancellation filter coefficient; a near-end cross talk canceller configured to couple between the other channels of the transmitter and the adder and having a near-end cross talk cancellation filter coefficient; an analog to digital converter configured to output a signal to the adder according to a clock signal; and a clock generating unit configured to selectively output a timing recovery signal or a phase increment signal as the clock signal; wherein the clock generating unit further comprising: a clock phase controller configured to generate the phase increment signal according to a continuous incremental phase sequence; a timing recovery circuit configured to generate the timing recovery signal; and a multiplexor configured to selectively switch between the timing recovery signal and the phase increment signal so as to adjust the predetermined phase of the clock signal, wherein the multiplexor outputs the phase increment signal before the receiver receives data from another transmitter, and outputs the timing recovery signal after the receiver receives the data from the another transmitter; and wherein the clock signal has a predetermined phase.