Patent ID: 7163890

Claim:
A method for fabricating a semiconductor device, the method comprising the steps of: sequentially forming an etch-stop layer end an interlayer dielectric layer on a semiconductor substrate having a lower conductive layer; exposing portions of the etch-stop layer by selectively etching the interlayer dielectric layer; forming a step in the etch-stop layer by removing portions of the exposed etch-stop layer, the step being formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer; exposing portions of the raised portion by removing portions of the interlayer dielectric layer; and forming an interconnection hole having a slope at lower sides of the interconnection hole by anisotropically etching the exposed recessed end raised portions to expose the lower conductive layer.