Patent ID: 6876040

Claim:
A SRAM cell fabricated in SSOI (selective silicon on insulator) comprising: cross coupled pnp pull-up devices P 1 , P 2 having sources, drains and gates and npn pull-down devices N 1 , N 2 having sources, drains and gates, with the P 1 , P 2 devices being connected to a power supply and the N 1 , N 2 devices being connected to a ground; a first passgate NL coupled between a first bitline and the junction of devices P 1 and N 1 , with its gate coupled to a wordline, and a second passgate NR coupled between a second bitline and the junction of devices P 2 and N 2 , with its gate coupled to the wordline, and the passgates having sources, drains and gates: wherein each of the pull-up devices P 1 , P 2 , the pull-down devices N 1 , N 2 , and the first and second passgates NL, NR are fabricated with their sources, drains and gates being selectively provided with SOI or being fabricated over bulk silicon without SOI, with the drains of the pull-up devices P 1 and P 2 and the pull-down devices N 1 and N 2 being provided with selective SOI to reduce the capacitance of the drains to allow the potential of the drains to be moved/changed faster to increase the circuit speed.