Patent ID: 8447953

Claim:
A multiprocessor system, comprising: a single instruction multiple data (SIMD) array comprising a plurality of processing elements, wherein each processing element comprises components including an arithmetic logic unit (ALU), a register file and an internal memory; an instruction controller operable to receive a plurality of instruction streams associated with processing threads; and a plurality of sub controllers which are each linked to a specific component within a processing element, so that a first sub controller is linked to an ALU, a second sub controller is linked to a register file and a third sub controller is linked to an internal memory, wherein each sub controller is operable to, receive instructions of a specific type from the instruction controller, prioritize the received instructions, which involves executing an instruction from another stream if a current instruction is waiting for a preceding instruction to complete, and send the received instructions to a specific component that the sub controller is linked to within each processing element in the SIMD array, wherein the specific component is operable to process instructions of that specific type; wherein the components within each processing element are operable to process respective instructions in parallel with one another.