Patent ID: 7864950

Claim:
A data transformation apparatus having a data processing unit for inputting data to be transformed and a key, and performing encryption or decryption of the data to be transformed, the data processing unit comprising: a divider for dividing the data to be transformed into first data and second data and forwarding the first and second data along first and second data pathways, respectively; a normal data transformation unit connected to the first pathway for receiving and transforming the first data; an inverse data transformation unit connected to the second pathway for receiving and transforming the second data by performing an inverse transformation of a transformation by the normal data transformation unit; a non-linear data transformation unit connected to the first and second pathways for receiving and processing the first and second data, wherein the non-linear data transformation unit is configured to process the first data before or after the first data is transformed by the normal data transformation unit, and wherein the non-linear data transformation unit is configured to process the second data before or after the second data is transformed by the inverse data transformation unit; and a combining unit for combining the processed and transformed first data from the first pathway with the processed and transformed second data from the second pathway, thereby producing ciphertext or plaintext depending on whether encryption or decryption, respectively, is being performed, wherein the combination of non-linear transformation unit, normal data transformation unit, and inverse data transformation unit is configured in such a manner that the data processing unit is capable of: receiving and encrypting particular plaintext data to produce particular ciphertext data, and receiving and decrypting the particular ciphertext data to produce the particular plaintext data, and wherein each of the normal data transformation unit, inverse data transformation unit, and non-linear transformation unit is implemented using at least one of a computer processor and a logical operation circuit.