Patent ID: 7477075

Claim:
An I/O buffer circuit comprising: a driver circuit containing a first pull-up device in a first floating well, a first pull-down device in a second floating well, a second pull-up device in an output stage and a second pull-down device in the output stage; first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the I/O buffer circuit; a first feedback loop operative to raise a gate voltage of the second pull-up device when a PAD voltage exceeds 3.3 volts; a second feedback loop operative to lower a gate voltage of the second pull-down device when the PAD voltage is less than ground; and a first and second tracking circuits to bias each of the second pull-up and the second pull-down devices in response to voltages internal and external to the I/O buffer circuit in a shutdown mode, wherein the first and second tracking circuits are operative to prevent greater than 3.3 volts across nodes in the first and second floating wells.