Patent ID: 6855976

Claim:
A semiconductor device comprising: a supporting substrate including a first region and a second region, a surface of the second region having a position lower than a position of a surface of the first region; a buried oxide layer formed on the first region of the supporting substrate; a semiconductor layer formed on the buried oxide layer; a first element formed in the semiconductor layer; an epitaxial layer formed on the second region of the supporting substrate, an interface between the supporting substrate and the epitaxial layer being located at a deeper position than the position of the surface of the first region; a second element formed in the epitaxial layer, the second element including a memory cell of a DRAM, the memory cell including a cell transistor and a trench capacitor, and the trench capacitor being formed across the interface between the supporting substrate and the epitaxial layer; and a first element isolation region interposed between the epitaxial layer and the semiconductor layer, the first element isolation region extending from an upper surface of the semiconductor layer to a position deep into the semiconductor layer, at least to an upper surface of the buried oxide layer, and the buried oxide layer and the first element isolation region jointly serving to electrically insulate the semiconductor layer from the epitaxial layer and the supporting substrate.