Patent ID: 7949844

Claim:
A memory device comprising: an array of memory cells; control logic; first and second address control circuits; and buffer circuits to store data retrieved from the array; wherein the first address control circuit is configured to provide a first array address sequence and the second address control circuit is configured to provide a second array address sequence; wherein the second address control circuit is configured to provide the second array address sequence using a starting address independent of a starting address used by the first address control circuit to provide the first array address sequence; wherein the control logic is configured to start a first output operation in response to receiving a starting address used by the first address control circuit; wherein the control logic is configured to start a second output operation in response to receiving a starting address used by the second address control circuit; and wherein the control logic is configured to hold the first address control circuit in response to receiving the starting address used by the second address control circuit, thereby interrupting a first output operation at an address of the first array address sequence, and to permit restarting of the first address control circuit, thereby restarting the first output operation at a next subsequent address of the first array address sequence, after completing the second output operation.