Patent ID: 7519139

Claim:
An integrated circuit comprising: a phase detector circuit adapted to receive an input signal and sample the input signal over time to provide five or more binary state signals; wherein the phase detector circuit comprises: a limiter; and a plurality of registers coupled to the limiter, wherein the limiter and the plurality of registers provide interleaved sampling to provide the binary state signals; and a signal monitoring circuit, coupled to the phase detector circuit, adapted to decode the binary state signals and provide output signals indicating for the input signal at least one of a path equalization and a duty cycle distortion; wherein the signal monitoring circuit comprises: a first comparator adapted to receive the binary state signals to compare to a first defined bit pattern to provide a first comparator output signal; a second comparator adapted to receive the binary state signals to compare to a second defined bit pattern to provide a second comparator output signal; and logic gates adapted to receive the first and second comparator output signals and provide output signals indicating for the input signal at least one of the path equalization and the duty cycle distortion.