Patent ID: 7109735

Claim:
A metrology system comprising: means for supplying a set of charge quantities to each of a set of test patterns in a non-functional region of a test sample, wherein each of the set of test patterns includes a set of semiconductor fins and a conformal dielectric layer formed over the set of semiconductor fins, wherein each semiconductor fin has a fin height, a fin width, and an inter-fin spacing on the order of tri-gate transistors in a functional region of the test sample, and wherein each set of semiconductor fins is dimensionally different than each other set of semiconductor fins; means for measuring a surface voltage at each of the set of test patterns for each of the set of charge quantities to generate a set of charge-voltage curves for the dielectric layers; means for deriving a relationship between dielectric layer properties and at least one of fin height, fin width, and inter-fin spacing based on the set of charge-voltage curves and fin dimensions for the set of test patterns; and means for estimating dielectric properties for individual tri-gate transistors in the functional region of the test sample based on the relationship.