Patent ID: 8314807

Claim:
A memory controller comprising: an agent interface unit coupled to receive a plurality of memory operations from one or more sources, each memory operation of the plurality of memory operations accompanied by a quality of service (QoS) parameter specifying a requested quality of service for the memory operation, wherein the agent interface unit comprises at least one memory channel interface unit configured to schedule the memory operations to access the memory, wherein scheduling decisions in the memory channel interface unit are responsive to the QoS parameters associated with the memory operations, and wherein the plurality of memory operations comprise operations of at least a real time (RT) type and a non-real time (NRT) type, wherein the QoS parameters are defined differently for each of the RT type and the NRT type, and wherein the memory channel interface unit is configured to rank the differently-defined QoS parameters with respect to each other in order to make the scheduling decisions, and wherein RT QoS parameters corresponding to the RT type comprise values that reflect different levels of urgency in a given RT source with respect to occurrence of erroneous operation in the given RT source due to not completing the corresponding memory operations, and wherein different ones of the memory operations from the given RT source have different RT QoS parameters dynamically assigned by the given RT source dependent on a current level of urgency in the given RT source at a time that the different memory operations are issued.