Patent ID: 7898630

Claim:
A pixel structure, comprising: a data line and at least a scan line, disposed over a substrate; a first thin film transistor, a second thin film transistor and a third thin film transistor, electrically connected with the data line and the scan line respectively, and the first, second, and third thin film transistors respectively have a first width-to-length ratio, a second width-to-length ratio and a third width-to-length ratio, wherein the first width-to-length ratio, the second width-to-length ratio and the third width-to-length ratio are the same; an impedance layer, connected with the first thin film transistor in series; a first pixel electrode, a second pixel electrode and a third pixel electrode, electrically connected with the first, second and third thin film transistors respectively; and a first common line, a second common line and a third common line, disposed below the first, second and third pixel electrodes respectively, wherein the first and second common lines are electrically connected to a first voltage and the third common line is electrically connected to a second voltage.