Patent ID: 8296120

Claim:
A system for pipelined simulated annealing on Field Programmable Gate Array (FPGA) comprising: a Memory Multiplexer comprising FPGA gates; a Main controller comprising FPGA gates and communicatively coupled to said Memory Multiplexer; at least five Memory modules communicatively coupled to said Memory Multiplexer, each Memory module comprising a FPGA Random Access Memory (RAM) block and storing a solution and a solution score of the solution, each solution comprising a plurality of events, a first Memory module storing a current solution and a current solution score; a Copy processor comprising FPGA gates and communicatively coupled to said Memory Multiplexer and to said Main controller, and copying the current solution to a second Memory module; an Alter processor comprising FPGA gates, communicatively coupled to said Memory Multiplexer and to said Main controller, and processing the current solution in the second Memory module to generate a next solution; an Evaluate processor comprising FPGA gates, communicatively coupled to said Memory Multiplexer and to said Main controller, and computing a next solution score for the next solution stored in the second Memory module; an Accept processor comprising FPGA gates, communicatively coupled to said Memory Multiplexer and to said Main controller, and processing the next solution stored in the second Memory module with an annealing calculation; an Adjust Temperature processor comprising FPGA gates, communicatively coupled to said Accept processor and to said Main controller, and adjusting a temperature of the annealing calculation; wherein the Copy processor iteratively copies the current solution from the first Memory module to a third, a fourth, and a fifth Memory module subsequent to copying the current solution to the second Memory module, and the Alter processor, the Evaluate processor, the Accept processor, and the Adjust Temperature processor each iteratively processing the solution stored in the third, the fourth, and the fifth Memory modules such that the solution stored in the third, the fourth, and the fifth Memory modules are processed concurrently with the solution stored in the second Memory module.