Patent ID: 8780372

Claim:
An image processing apparatus including at least one processor and memory communicatively-coupled via a bus, comprising: an image input unit configured to input image data; an image processing unit configured to perform an image processing on the image data; a detection unit configured to detect embedded information from the image data; a restriction unit configured to restrict an execution of an image processing involving a loss of the embedded information from the image data to be performed by the image processing unit in a case where the detection unit detects the embedded information from the image data; and a determining unit configured to determine whether information indicating the embedded information is able to be added to image data on which the image processing involving a loss of the embedded information has been performed, wherein in a case where the determining unit determines that information indicating the embedded information is able to be added to image data on which the image processing involving a loss of the embedded information has been performed, the restriction unit does not restrict the execution of the image processing involving the loss of the embedded information.