Patent ID: 8201134

Claim:
Method to avoid malconnections with respect to voltage levels of electronic components of a circuit board during circuit board design characterized by the steps of: creation of a Component Specification Library (CSL) comprising at least distinct pin names and assigned voltage data, and saving the CSL in a computer database, each pin of each component is associated with a Physical Pin Name (PPN) and a Logical Pin Name (LPN) within the CSL, wherein the LPN identifies a logical function associated with each pin; creation of groups of pins of components to be connected with each other on a particular voltage level according to the circuit board design with a computer processor; verification of the voltage data of the pins of the components within a particular group with the computer processor the verification of the voltage data of the pins of the components within the particular group is performed by comparing the assigned voltage values of the pins within one group with each other, wherein a verification is performed, if all components within a group match with an associated component specification in the CSL, including the tolerances defined in the CSL; and outputting an error report to a user if a voltage level of a first pin within the particular group does not match the particular voltage level of the particular group.