Patent ID: 7613049

Claim:
A method for simultaneous read/write operation in an integrated circuit which includes a memory device, a clock signal, a plurality of pins, and a configuration register, the configuration register including a wait cycle count, a burst read length, and a wrap around indicator , the method comprising: entering a read command into the memory device using a second input pin; transmitting a read address to the memory device using a first input pin and the second input pin concurrently, the read address being associated with a location in the memory device, the read address including at least a first address bit and a second address bit, the first address bit being transmitted using the first input pin, the second address bit being transmitted using the second input pin; accessing read data associated with the read address in the memory device; transferring the read data in burst mode from the memory device using a first output pin and a second output pin concurrently, a length of the read data being associated with the burst read length; and performing a write operation in the memory device using the first input pin and second input pin while continuing to transfer the read data in burst mode using the first output pin and the second output pin, the write operation including at least one of the following processes: entering a write command into the memory device using the second input pin; transferring a write address to the memory device using the first input pin and the second input pin concurrently; and transferring write data to the memory device using the first input pin and the second input pin concurrently.