Patent ID: 6918019

Claim:
A networking system comprising: a first computing device; a second computing device; a first network processing engine (NPE), configured to communicate with the first computing device, and configured to read from and write to a first random access memory (RAM) device comprising: a memory; and a memory controller, wherein the memory controller is configured to: buffer a plurality of incoming requests; prioritize the incoming requests into a final order, as needed, to maximize overlap of incoming requests' timing cycles; and submit the incoming requests to the memory in the final order; a second NPE, configured to communicate with the second computing device, and configured to read from and write to a second RAM device comprising: a memory; and a memory controller, wherein the memory controller is configured to: buffer a plurality of incoming requests; prioritize the incoming requests into a final order, as needed, to maximize overlap of incoming requests' timing cycles; and submit the incoming requests to the memory in the final order; a third NPE, configured to communicate with the first NPE, configured to communicate with the second NPE, and configured to read from and write to a third RAM device comprising: a memory; and a memory controller, wherein the memory controller is configured to: buffer a plurality of incoming requests; prioritize the incoming requests into a final order, as needed, to maximize overlap of incoming requests' timing cycles; and submit the incoming requests to the memory in the final order; at least one processor client, configured to support NPE network services.