Patent ID: 7193445

Claim:
A non-inverting domino register, comprising: a complementary pair of evaluation devices responsive to a clock signal; evaluation logic, coupled between said complementary pair of evaluation devices at a pre-charged node, that evaluates a logic function based on at least one input data signal; a storage stage driving a first preliminary output node, said storage stage comprising a first pull-up device and a first pull-down device both responsive to said pre-charged node, and a second pull-down device responsive to said clock signal; a keeper circuit having an input coupled to said first preliminary output node and an output that drives a second preliminary output node; and an output stage driving an output node, said output stage comprising a second pull-up device and a third pull-down device both responsive to said pre-charged node and a third pull-up device and a fourth pull-down device both responsive to said second preliminary output node.