Patent ID: 7130218

Claim:
A data processing unit comprising: a nonvolatile memory array having a plurality of memory cells each of which is capable of erasing data electrically and programming data electrically; a voltage generator which generates a high voltage to be supplied to one or more of the plurality of memory cells and which changes a voltage generating speed of said high voltage in accordance with a frequency of a first clock signal; and a control circuit including a clock generating circuit which generates said first clock signal, wherein said control circuit controls said frequency of said first clock signal such that said control circuit sets said frequency of said first clock signal to a first frequency when a first number of memory cells is to be supplied said high voltage, and wherein said control circuit sets said frequency of said first clock signal to a second frequency when a second number of memory cells is to be supplied said high voltage, wherein said first number of memory cells is less than said second number of memory cells and said first frequency is higher than said second freguency.