Patent ID: 7739576

Claim:
A memory system, comprising: one or more memory devices, wherein the one or more memory devices each contain a memory array with a plurality of memory cells arranged in a plurality of sectors, each sector of the plurality of sectors having an associated ECC code, and where a size of the associated ECC code is selectable from two or more differing numbers of ECC check bytes; and a memory control circuit coupled to the one or more memory devices, wherein the memory control circuit comprises, an ECC generator/checker circuit, where the ECC generator/checker circuit is adapted to error check a selected sector read from the one or more memory devices utilizing the selected number of ECC check bytes contained in the associated ECC code; wherein the memory control circuit is adapted to select the size of an associated ECC code based on a bit error rate and/or use level of the sector having the associated ECC code or based on one of a data type and a memory device type while a data size of the sector having the associated ECC code stays the same.