Patent ID: 8117250

Claim:
A VDSL2 transmitter architecture, comprising a IFFT engine for performing inverse fast Fourier transforms, the IFFT engine having: a IFFT counter; a frequency data SRAM; a bit reverse logic used to reverse the order of the IFFT counter; seven stages, each stage except for the last including type 1 butterfly circuit and type 2 butterfly circuit; the last stage only including the type 1 butterfly circuit; each stage having a stage pipeline control generating circuit, which is basically a combination logic used to subtract some fixed pipeline latency from previous stage from the IFFT counter; wherein: a top-level signal (fd_fm_start) generated based on the pipeline control counter and the configured IFFT size, and used to synchronize the next module in the VDSL2 transmitter; for the first six stages, the complex data passes through type 1 and type 2 butterfly circuits; the output complex vector of butterfly type 2 is multiplied with the twiddle factor ROM output and the address of the twiddle factor ROM is generated through the pipeline control generating circuit for that stage; the IFFT output being taken from the output of butterfly type 2 of the stage 3, stage 5, stage 6, and stage 7 respectively.