Patent ID: 8587063

Claim:
A semiconductor wafer structure for integrated circuit devices, comprising: a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation; a plurality of shallow active area level STI recesses formed through the hybrid semiconductor-on-insulator layer; and one or more deep back gate level STI recesses formed through the upper insulating layer and the back gate layer, the one or more deep back gate level STI recesses having portions thereof self-aligned to portions of one or more of the shallow active area level recesses; wherein both the shallow active area STI recesses and the one or more self-aligned deep back gate level STI recesses are filled with one or more insulating materials.