Patent ID: 8461881

Claim:
A solid state relay comprising: (a) a first semiconductor device including a first terminal, a second terminal arranged for conductive connection to a load and a third terminal, an impedance between said first terminal and said second terminal substantially reduced by application of a first gate potential to said third terminal; (b) a first gate driver conductively connected to said third terminal and arranged to transmit said first gate potential to said third terminal in response to a first gate driver input; (c) a first delay device arranged to transmit said first gate driver input to said first gate driver in response to an isolator signal and to temporally delay said transmission; (d) a second semiconductor device including a fourth terminal conductively interconnected with said first terminal of said first device, a fifth terminal arranged for conductive connection to said load and a sixth terminal, an impedance between said fourth terminal and said fifth terminal substantially reduced by application of a second gate potential to said sixth terminal; (e) a second gate driver conductively connected to said sixth terminal and arranged to transmit said second gate potential to said sixth terminal in response to a second gate driver input; and (f) a second delay device arranged to transmit said second gate driver input to said second gate driver in response to said isolator signal and to temporally delay said transmission; (g) wherein at least one of said second terminal and said fifth terminal have modified voltages based upon at least one of said first gate potential and said second gate potential; (h) an isolator outputting said isolator signal in response to a control signal.