Patent ID: 7907033

Claim:
A plurality of tunable impedance matching networks connected in an in-line series combination, each of the tunable impedance matching networks comprising: (a) a substrate having an impedance element, the impedance element being connected between first and second nodes for communicating signals between the first and second nodes; (b) a first capacitor connected in parallel with the impedance element, wherein the first capacitor is tunable; (c) a second capacitor comprising first and second terminals, wherein the first terminal of the second capacitor is connected to the first node, wherein the second terminal of the second capacitor is connected to a third node, and wherein the third node is a ground; and (d) a third capacitor comprising first and second terminals, wherein the first terminal of the third capacitor is connected to the second node, wherein the second terminal of the third capacitor is connected to a fourth node, and wherein the fourth node is a local voltage reference for the second node; wherein at least one of the first, second, and third capacitors comprises a micro-electro-mechanical system (MEMS) variable capacitor; wherein at least one of the first, second, and third capacitors is flip-chipped onto the substrate; and wherein adjacent networks in the series are connected at the first node of one network and the second node of an adjacent network.