Patent ID: 8922406

Claim:
A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, comprising taps of a capacitive network wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i , comprising: for taps corresponding to bits with higher significance than the bit b i : connecting each tap to a different floating node; or connecting all taps to the same floating node; sampling a first electrical value representative of the bit weight w i ; and performing a first analog-to-digital, A/D, conversion using the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i to obtain a first digital word of said bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i representing said first electrical value; estimating the value of the bit weight w i expressed in terms of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i based at least on said first digital word, wherein the resulting estimated value of the bit weight w i is one of the at least one calibration value.