Patent ID: 8638130

Claim:
A line driver circuit configured to regulate output voltage and common mode voltage, comprising: a first transistor and a second transistor, where the first and second transistors are matched; a third transistor and a fourth transistor, where the third and fourth transistors are matched; a first impedance and a second impedance, where the first and second impedances are matched; a first driver control circuit configured to apply control signals to the gates of the first and second transistors in response to a digital input; and a second driver control circuit configured to apply control signals to the gates of the third and fourth transistors in response to the digital input; wherein the first and third transistors are configured as a pair of stacked transistors connected between a first voltage supply (Vdd) and a second voltage supply (Vss); wherein the second and fourth transistors are configured as a pair of stacked transistors connected between the first voltage supply (Vdd) and the second voltage supply (Vss); wherein the matched impedances are connected in series between a node formed by the connection between the first and third transistors and a node formed by the connection between the second and fourth transistors; wherein the first driver control circuit and the second driver control circuit regulate the voltage drop across the pair of matched impedances and the common mode voltage at a node between the first and second impedances; and wherein the first driver control circuit and the second driver control circuit are configured to regulate the line driver circuit such that the current flowing through the impedances is matched to a reference current (Iref) and the common mode voltage is matched to a reference voltage (Vref).