Patent ID: 7193554

Claim:
A quantizer generating a first bit, a second bit and a third bit respectively indicating whether an input signal has a strength greater than a first strength, a second strength and a third strength respectively, wherein said third strength is between said first strength and said second strength, said quantizer comprising: a first pre-amplifier receiving said input signal on one of an inverting terminal and a non-inverting terminal and a first reference signal having said first strength on the other one of said inverting and non-inverting terminal and generating a first signal and a second signal as a first differential output signal, wherein a first bit is generated from said first differential output signal; a second pre-amplifier receiving said input signal on one of an inverting terminal and a non-inverting terminal and a second reference signal having said second strength on the other one of said inverting and non-inverting terminal and generating a third signal and a fourth signal as a second differential output signal, wherein a second bit is generated from said second differential output signal; a first transistor receiving one of said first signal, second signal, third signal and fourth signal and generating a first current; a second transistor receiving another one of said first signal, second signal, third signal and fourth signal and generating a second current; and a current latch receiving a first primary current and a second primary current and generating a latch output wherein said latch output is at a first value when said first current is greater than said second current, and at a second value otherwise, wherein said first primary current and said second primary current respectively contain said first current and said second current, wherein said latch output represents a third bit between said first quantized value and said second quantized value.