Patent ID: 8751551

Claim:
A digital signal processing (“DSP”) circuit block comprising: first multiplier circuitry that performs a first multiplication of two inputs each of a first size; second multiplier circuitry that performs a selectable one of (1) a second multiplication of two inputs each of the first size and (2) a multiplication of a first input of a second size smaller than the first size by a second input of a third size larger than the first size and a multiplication of a third input of the second size by a fourth input of the first size; shifting circuitry that shifts outputs of the first multiplier circuitry by a selectable one of (1) zero bit positions and (2) a number of bit positions, equal to the first size, toward greater arithmetic significance; first addition circuitry that additively combines outputs of the second multiplier circuitry and the shifting circuitry; first routing circuitry that routes outputs of the first addition circuitry to a first other DSP circuit block; and second addition circuitry that additively combines outputs of the first addition circuitry and outputs received from a second other DSP circuit block.