Patent ID: 7042373

Claim:
An error measuring method for a pipeline ADC, the pipeline ADC including a plurality of analog-to-digital converting units cascaded in series to form a pipeline structure, the error measuring method comprising the following steps: providing to the input of one of the analog-to-digital converting units a plurality of predetermined biasing voltage combinations; in accordance with each predetermined biasing voltage combination, switching to change capacitance allocation of said analog-to-digital converting unit to perform measurement by measuring an output value of the pipeline structure to generate a first measurement value when the analog-to-digital converting unit is at a first capacitance allocation, and measuring an output value of the pipeline structure to generate a second measurement value when the analog-to-digital converting unit is at a second capacitance allocation, wherein at the first capacitance allocation a first capacitor is electrically connected to a first node and a second capacitor is electrically connected to a second node, and at the second capacitance allocation the first capacitor is electrically connected to the second node and the second capacitor is electrically connected to the first node; and calculating a calibration constant according to the first and second measurement values, the calibration constant corresponding to art error of the analog-to-digital converting unit.