Patent ID: 8145961

Claim:
A Random Access Memory Controller logic for a memory unit comprising a data section and an Error Correction Code (ECC) memory section, the Random Access Memory Controller logic comprising a functional hardware component implementing a functional component for performing: (a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving equation (1): E*X=C, (1) wherein: C is a check bit string consisting of m bits, wherein all bits have a logical value of “1”, X is a data pattern consisting of n bits fulfilling said equation (1), E is a known n×m ECC matrix, and wherein n is a number of data bits and m is a number of check bits; (b) generating a data pattern P 3 by calculating a term (2) or (2′): P 3 =X XOR P 1 or (2) P 3 =X XOR P 2, (2′) wherein P 1 and P 2 are arbitrary data patterns of a same bit length as said X data pattern; (c) writing said data pattern P 3 into the data section of said memory unit, thus generating respective ECC data; (d) testing said ECC memory section in an ECC test run procedure by reading out the ECC data associated with said P 3 data patterns; and (e) indicating an error, if said ECC test run procedure leads to an incorrect result.