Patent ID: 8667443

Claim:
A method for defining a multiple patterned cell layout for use in an integrated circuit design, comprising: defining a layout for a level of a cell, the layout defined by a number of linear-shaped layout features commonly oriented to extend lengthwise in a same direction, each of the number of linear-shaped layout features devoid of a substantial change in direction along its length; splitting the layout into a plurality of sub-layouts for the level of the cell, such that each of the number of linear-shaped layout features in the layout is allocated to any one of the plurality of sub-layouts, and wherein each of the plurality of sub-layouts is defined on a separate mask, and wherein each separate mask for the plurality of sub-layouts corresponds to a same portion of the level of the cell; and storing the plurality of sub-layouts for the level of the cell in a digital data format on a data storage device.