Patent ID: 7157771

Claim:
A NAND architecture floating gate memory cell string, comprising: a substrate, comprising two or more raised areas, defining trenches therebetween; a plurality of floating gate memory cells, wherein the floating gate memory cells are formed vertically on the sidewalls of the trenches; wherein the plurality of floating gate memory cells are coupled in a serial string by source/drain regions formed at the top of the two or more raised areas and at the bottom of the one or more trenches; wherein one or more source/drain regions formed at the bottom of the one or more trenches have first and second edges that extend beyond opposite sidewalls of their respective trenches; wherein a first floating gate memory cell is coupled to a first select gate, where the first select gate is formed vertically on a sidewall of a selected trench; and wherein the NAND architecture floating gate memory cell string is formed in a P-well defined by isolation regions formed on either side of the NAND architecture floating gate memory cell string which extend into the substrate.