Patent ID: 7301107

Claim:
A semiconductor device having an interconnect structure comprising: a. a lower metal layer comprising a low-k dielectric material and a plurality of conductive lines disposed within said low-k dielectric material; b. an upper metal layer comprising a low-k dielectric material and a plurality of conductive lines disposed within said low-k dielectric material; c. an insulating layer, disposed between the lower metal layer and the upper metal layer, and comprising a low-k dielectric material; d. a plurality of metal-filled vias extending through the insulating layer and interconnecting the conductive lines of the lower metal layer to the conductive lines of the upper metal layer; e. a porous ultra low-k dielectric material regions disposed within the low-k dielectric material of the upper metal layer and the lower metal layer between adjacent conductive lines, and within the low-k dielectric material in the insulating layer; f. a first barrier layer interposed between the lower metal layer and the insulating layer, said first barrier layer separating the ultra low-k material regions of the lower metal layer from the ultra low-k material regions of the insulating layer; and g. a second barrier layer disposed over the upper metal layer, wherein said first barrier layer and said second barrier layer each have a first film and a second film disposed over the first film, wherein said first film covers the conductive lines and said porous ultra low-k dielectric material regions extend through said first film to said second film, which covers said ultra low-k dielectric material regions.