Patent ID: 8261224

Claim:
A computer program product for inserting components into a current chip design that is cell-based with multiple levels of nested hierarchy, the computer program product comprising: a non-transitory computer-readable storage medium readable by a processing circuit and storing instructions, which when executed by the processing circuit perform a method comprising: receiving a selection of components having various silicon densities to insert into the current chip design; inserting, during a first phase, a second phase, and a third phase, components into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design, wherein the components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities; wherein inserting during the first phase comprises inserting highest silicon density decoupling capacitors around the existing circuits or silicon shapes to create a halo of empty space around the existing circuits or silicon shapes in which no highest silicon density decoupling capacitors are inserted into the halo; wherein, responsive to completion of the first phase, inserting during the second phase comprises inserting medium silicon density decoupling capacitors into the halo of empty space left around the existing circuits or silicon shapes in which no highest silicon density decoupling capacitors are inserted; wherein, responsive to completion of the second phase, inserting during the third phase comprises inserting low silicon density decoupling capacitors in any empty space left after inserting the medium silicon density decoupling capacitors into the halo; wherein inserting components into the current chip design comprises: selecting a place in the current chip design for inserting each component, based on a silicon density of each component, each place having coordinates; and collecting obstruction shapes representing the existing circuits or silicon shapes in the current chip design, wherein the obstruction shapes only contain the existing circuits or silicon shapes and do not contain any silicon density decoupling capacitors, each obstruction shape having coordinates; determining whether to expand the obstruction shapes, the determining responsive to across chip line variation ground rules; in response to a determination to expand the obstruction shapes, expanding the obstruction shapes; wherein expanding the obstruction shapes comprises increasing a boundary by a specified value for the obstruction shapes; and wherein the expanded obstruction shapes only contain the existing circuits or silicon shapes and do not contain any silicon density decoupling capacitors.