Patent ID: 7197073

Claim:
An MPEG data processing circuit which processes inputted MPEG data to produce outputted MPEG data, comprising: V-ES detecting section which judges said inputted MPEG data to output video stream status signal indicating output status of system stream data and video elementary data within said system stream data; a memory which stores non-video elementary data portion from said V-ES detecting section; a barrel shifter which divides video elementary data portion from said V-ES detecting section into bit units and which stores the bit units of said video elementary data portion; a variable length decoder which is connected to an output of said barrel shifter; a data replacing section which is connected to an output of said variable length decoder; a variable length encoder which is connected to an output of said data replacing section; a bit packer section which is connected to an output of said variable length encoder; a data combining section which combines an output of said bit packer section and an output of said memory to produce said outputted MPEG data in an original order; a control section which controls input and output of data in said barrel shifter and said data replacing section based on a first control signal from said V-ES detecting section, a signal from said variable length decoder, and a signal from said data combining section; and a memory control section which controls input and output of data in said memory based on said first control signal from said V-ES detecting section and which outputs a second control signal to said control section.