Patent ID: 7142458

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array equipped with a plurality of memory cells arranged in a matrix, a plurality of word lines, a plurality of bit lines, and a plurality of source lines; a word line control circuit to control the plurality of word lines; and a line control circuit to control the plurality of bit lines and the plurality of source lines; each of the plurality of memory cells including a gate electrode connected to a word line, a first impurity region connected to a bit line, a second impurity region connected to a source line, and an electron trap region, which is positioned between the gate electrode and a substrate, and is formed at least at a first impurity region side of both the first impurity region and second impurity region; at a time when a writing operation is performed for a selected memory cell, the word line control circuit providing a selected word line connected to the selected memory cell with a selection voltage, and the word line control circuit providing a non-selected word line connected to a non-selected memory cell that is connected in common to a bit line connected to the selected memory cell with a first mis-erasing prevention voltage; and at a time when a writing operation is performed for a selected memory cell, the line control circuit providing a bit line connected to the selected memory cell with a program voltage, the line control circuit providing a source line connected to the selected memory cell with a source voltage for a program, the line control circuit providing a bit line connected to the non-selected memory cell that is connected in common to a bit line connected to the selected memory cell with a program voltage, and the line control circuit providing a source line connected to the non-selected memory cell with a second mis-erasing prevention voltage.