Patent ID: 7557038

Claim:
A method for fabricating a self-aligned contact hole in a semiconductor device, comprising the steps of: (a) forming an oxide layer covering a gate structure on a semiconductor substrate, the gate structure including a gate oxide pattern, a gate electrode pattern, a hard-mask nitride pattern, and a spacer nitride on sidewalls thereof; (b) forming a mask pattern on the oxide layer; (c) forming a contact trench by removing a portion of the exposed oxide layer to a predetermined depth, wherein the predetermined depth of the contact trench is less than a total thickness of the oxide layer; (d) forming a buffer layer by plasma enhanced chemical vapor deposition (PECVD) on the oxide layer including in the contact trench; (e) etching the buffer layer such that portions of the buffer layer remain on an upper horizontal surfaces of the oxide layer and sidewalls of the contact trench, and an entire portion of the buffer layer at a bottom of the contact trench is removed to expose a portion of the oxide layer; and (f) forming the self-aligned contact hole by etching the exposed portion of the oxide layer using the remaining portions of the buffer layer as an etching mask to expose portions of the hard-mask nitride pattern, the spacer nitride, and the substrate, wherein the exposed portions of the hard-mask nitride pattern are in contact with the remaining portions of the buffer layer.