Patent ID: 7318125

Claim:
A method, comprising: receiving a first process, comprising successive computational phases, to be executed by a processor in a data processing system; assigning the first process to run on a first processor; determining a first prefetch status for the first process at each of successive times when the first process is running, wherein each determined first prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the first process; setting a first hardware prefetch state on the first processor based on each determined first prefetch status to correspondingly enable or disable said hardware prefetch; receiving a second process, comprising successive computational phases, to be executed by a processor in the data processing system; assigning the second process to run on a second processor; determining a second prefetch status for the second process at each of successive times when the second process is running, wherein each determined second prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the second process; and setting a second hardware prefetch state on the second processor based on each determined second prefetch status, to correspondingly enable or disable said hardware prefetch.