Patent ID: 6961231

Claim:
A structure, comprising: a packaged integrated circuit (IC) having a plurality of package pins, the package pins including at least one ground pin and at least one power pin; and a capacitive interposer structure directly coupled to the packaged IC and having a comparable footprint to the packaged IC, the capacitive interposer structure comprising: a body having upper and lower surfaces, the body comprising a plurality of alternating conductive layers and dielectric layers, the outermost layers comprising dielectric layers; a plurality of lands disposed upon the upper surface of the body, each land being coupled to one of the package pins of the packaged IC; a plurality of terminals disposed upon the lower surface of the body; and a plurality of vias through the body and orthogonal to the upper and lower surfaces, each via providing an electrically conductive path between an associated land and an associated terminal, wherein: each conductive layer in the body comprises one or more electrically insulating keepouts disposed around at least a subset of the vias, one or more conductive layers are coupled to the ground pin of the packaged IC, and one or more conductive layers are coupled to the power pin of the packaged IC.