Patent ID: 7928871

Claim:
A successive approximation A/D converter, comprising: a capacitive D/A converter that includes a plurality of capacitors for storing a charge based on an input voltage supplied to an input node, and generates, at an output node, a voltage based on the input voltage and a first digital signal including J bits, where J is a natural number, by switching connections of the plurality of capacitors according to the first digital signal; a resistive D/A converter that generates a voltage based on a second digital signal by voltage division using a resistor string; a capacitor that capacity-couples the voltage generated by the resistive D/A converter to the output node; a comparator that generates a comparison result signal based on the voltage output at the output node; a control circuit that supplies the first digital signal corresponding to upper-order J bits of digital data generated by the A/D converter to the capacitive D/A converter according to the comparison result signal and outputs a third digital signal indicating a capacitance error correction value for the plurality of capacitors and a fourth digital signal corresponding to lower-order K bits of the digital data generated by the A/D converter, where K is a natural number; and a digital calculating circuit that adds the third digital signal and the fourth digital signal to generate the second digital signal, which includes at least K bits, and supplies the second digital signal to the resistive D/A converter, wherein a bit digital data is generated based on the input signal.