Patent ID: 7323918

Claim:
A delay-locked loop (DLL) circuit for generating a plurality of delayed clock signals in response to an applied reference clock signal, the DLL circuit comprising: a delay cell chain including a plurality of series-connected delay cells, each delay cell of the delay cell chain includes generating means for generating one or more of said delay clock signals; and an outer feedback loop circuit having a first input terminal coupled to the applied reference clock signal, a second input terminal coupled to receive a selected delay clock signal generated by a last-sequential delay cell of the delay cell chain, and means for generating a delay control signal V DEL−CNTL and for transmitting the delay control signal to each of the plurality of delay cells in the delay cell chain, wherein said delay cell chain further comprises at least one sub-loop feedback line extending from a first delay cell to a second delay cell of said delay cell chain, and wherein said generating means of said first delay cell includes means for interpolating a first delay clock signal and a second delay clock signal, the first delay clock signal being received from a preceding delay cell of the delay cell chain, and the second delay clock signal being received from said second delay cell of the delay cell chain via said at least one sub-loop feedback line.