Patent ID: 7701800

Claim:
A multi-port memory device, comprising: a plurality of port for performing a serial data transmission with external devices; a plurality of banks for performing a parallel data transmission with the ports; a global data bus for transmitting between the ports and the banks; an input/output (I/O) controller for transmitting a test signal, input through a plurality of first pads in parallel, to the global data bus in response to a mode register enable signal; a mode register set for generating a test enable signal in response to the mode register enable signal and outputting a mode selection signal which determines a data transmission mode of a test I/O signal input through a plurality of second pads in response to the test signal; a clock generator for receiving an external clock and generating an internal clock based on the external clock in response to the mode selection signal; a test I/O controller, enabled by the test enable signal, for inputting and outputting the test I/O signal in synchronism with the internal clock, wherein the mode register enable signal is active during a test operation mode for testing a core area of the banks.