Patent ID: 7626412

Claim:
A method of testing a plurality of consecutively indexed wafer sites on a semiconductor wafer that includes a plurality of integrated circuit die formed thereon, the wafer sites being arranged as an array of rows and columns of such wafer sites, the method comprising: for each row of consecutively indexed wafer sites, (a) beginning with the first wafer site in said row, applying a complete set of test stimuli to a first predefined number of consecutive wafer sites in said row; (b) in the event that a defective wafer site is not identified in the first predefined number of consecutive wafer sites, applying a reduced set of test stimuli to a second predefined number of consecutive wafer sites in said row following the first predefine number of wafer sites; (c) in the event that no defective wafer sites are identified in the first and second predefined number of wafer sites, repeating steps (a)-(c) until a defective wafer sites is identified; (d) in the event that a defective wafer site is identified, applying a full set of test stimuli to wafer sites subsequent to the defective wafer site until a third predefined number of consecutive non-defective wafer sites has been identified; and (e) after the third predefined number of consecutive non-defective wafer sites has been identified, resume repeating steps (a)-(c).