Patent ID: 6907552

Claim:
A system to deskew a parallel data link having a plurality of channels for exchanging digital data, the link comprising: source and destination nodes with an interconnect medium there between; a Source Synchronous Driver (SSD) at the link source node to format “M” bits of input data received from core logic and to drive “M” data channels onto the link along with a link clock; a Dynamic Skew Compensation (DSC) architectural block at the link destination node to receive the “M” data bits and link clock and to compensate for skew, recenter the link clock edge relative to the bits of data, and output “M” bits of data, the DSC block comprising: a DSC bundle consisting of a plurality of DSC Modules interconnected with a Bundle Interface Module, wherein the DSC Modules perform adjustments to compensate for channel-to-channel skew and substantially center the link clock edge with respect to the data bits; wherein each DSC Module comprises a plurality of DSC Data Channels and a DSC Clock Channel; and wherein the DSC Clock channel comprises a Clock Channel Front-End block, Built-In Self-Test Logic, and a utility block.