Patent ID: 8183906

Claim:
An arrangement comprising: at least two logarithmizing units, wherein each logarithmizing unit: has an input and an output, is connected by the input to a first terminal of a voltage source, wherein the voltage source provides an input voltage and has a second terminal which is connected to reference-ground potential, has a transistor device semiconductor component which comprises a field effect transistor and has an operating point setting unit configured to set an operating point in a sub threshold voltage range of a drain current-to-gate voltage input characteristic curve of the semiconductor component so that a logarithmized sub threshold voltage value is available at the output of each logarithmizing unit, a subtracting unit having a first input, a second input and an output, wherein a respective one of the inputs of the subtracting unit is connected to one of the outputs of the logarithmizing units, and wherein the subtracting unit is configured to subtract the logarithmized sub threshold voltage values output by the at least two logarithmizing units to generate a voltage value tapped off at the output of the subtracting unit which is linearly proportional to absolute temperature, and an evaluation unit connected downstream of the subtracting unit, the evaluation unit configured to detect the voltage value tapped off at the output of the subtracting unit and determine the absolute temperature of each field effect transistor by means of a calculation unit within the evaluation unit, wherein the voltage value tapped off at the output of the subtracting unit is dependent on depletion zone capacitances of the field effect transistors, the Boltzmann constant, the elementary charge and the natural logarithm of a resistance ratio within the logarithmizing unit.