Patent ID: 8629692

Claim:
A circuit comprising: two cross-connected PMOS transistors; first, second, and third NMOS transistors coupled to the two cross-connected PMOS transistors, wherein the second NMOS transistor is connected to an input terminal of the circuit, and wherein a drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the two cross-connected PMOS transistors; an inverter circuit coupled to the first and second NMOS transistors and to the input terminal; and an output transistor connected to the two cross-connected PMOS transistors and to an output terminal of the circuit, wherein the inverter circuit is connected between a first power supply and a first base voltage, and wherein the two cross-connected PMOS transistors, the first, second, and third NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage, wherein the two cross-connected PMOS transistors include a first PMOS transistor and a second PMOS transistor, wherein a gate terminal of the first PMOS transistor is connected to a drain terminal of the second PMOS transistor, and wherein a gate terminal of the second PMOS transistor is connected to a drain terminal of the first PMOS transistor, wherein the gate terminal of the first PMOS transistor is connected to a drain terminal of the second NMOS transistor, wherein the gate terminal of the second PMOS transistor is connected to a drain terminal of the first NMOS transistor, wherein the gate terminal of the first PMOS transistor is connected to a drain terminal of the output transistor, and wherein a gate terminal of the output transistor is connected to the output terminal of the circuit.