Patent ID: 8164495

Claim:
A method for use with a digital-to-analog converter (DAC), the method comprising: (a) determining Integrated Non-Linearity (INL) values for a plurality of sub-segments of the DAC that is adapted to accept N bit digital input codes; (b) determining a first set of correction codes that can be used to reduce to a range of INL values, to thereby improve linearity of the DAC; (c) storing the first set of correction codes in non-volatile memory associated with the DAC so that the first set of correction codes can be accessed during digital-to-analog conversions; (d) determining Differential Non-Linearity (DNL) values for the plurality of sub-segments for which INL values were determined at step (a); (e) determining a second set of correction codes that can be used to ensure that all values of DNL>−1, to thereby ensure that the DAC is monotonic; and (f) storing the second set of correction codes in non-volatile memory associated with the DAC so that the second set of correction codes can be accessed during digital-to-analog conversions.