Patent ID: 7924259

Claim:
A shift register array comprising a plurality of shift registers, at least one shift register comprising: a first transistor comprising a gate, a first electrode, and a second electrode, wherein the gate and the first electrode of the first transistor receive an input signal; a second transistor comprising a gate, a first electrode, and a second electrode, wherein the gate of the second transistor is coupled to the second electrode of the first transistor, the second electrode of the second transistor generates an output signal, and the first electrode of the second transistor receives a first clock signal; a third transistor comprising a gate, a first electrode, and a second electrode, wherein the first electrode of the third transistor is coupled to the gate of the second transistor, the second electrode of the third transistor is coupled to a power source, and the third transistor is for pulling down a voltage level at the gate of the second transistor; and a driving circuit comprising: a fourth transistor comprising a gate, a first electrode, and a second electrode, wherein the second electrode of the fourth transistor is coupled to the gate of the third transistor, and the first electrode of the fourth transistor receives a second clock signal; a fifth transistor comprising a gate, a first electrode, a second electrode, wherein the gate of the fifth transistor receives the input signal, the second electrode of the fifth transistor is coupled to the power source, and the first electrode of the fifth transistor is coupled to the gate of the third transistor; a sixth transistor comprising a gate, a first electrode, a second electrode, wherein the gate of the sixth transistor receives the output signal, the second electrode of the sixth transistor is coupled to the power source, and the first electrode of the sixth transistor is coupled to the gate of the third transistor; and a seventh transistor comprising a gate, a first electrode, and a second electrode, wherein the gate and the first electrode of the seventh transistor receive the second clock signal, and the second electrode of the seventh transistor is coupled to the gate of the fourth transistor; wherein the driving circuit is configured to determine an on/off status of the third transistor in response to the input signal and the output signal and generate another output signal that is directly connected to the gate of the third transistor to drive the third transistor.