Patent ID: 8327303

Claim:
A system to process behavioral models of a transistor level design, the system comprising: a model generation function configured with a plurality of templates to a plurality of circuits, the plurality of templates including a template that corresponds to a circuit of the plurality of circuits, wherein the model generation function is configured to: receive selection of a template from the plurality of templates, wherein the template corresponds to the transistor level design, receive a plurality of parameters, and generate a first model according to the template customized with the plurality of parameters, wherein the first model is configured to take into account analog behavior of the transistor level design; an analog EDA tool configured to generate real number calibration information according to the plurality of parameters, wherein the real number calibration information is indicative of analog operation of the transistor level design; and a behavioral EDA tool configured to: automatically receive the real number calibration information, and simulate the transistor level design as a function of the real number calibration information.