Patent ID: 6999985

Claim:
Apparatus for data processing, said apparatus comprising: (i) a shifting circuit; (ii) an arithmetic circuit; and (iii) an instruction decoder responsive to an instruction to control said shifting circuit and said arithmetic circuit to perform an operation using a first input data word and a second different input data word, wherein said operation yields a result value given by: (iv) selecting a plurality of non-adjacent multibit portions of said first input data word to form a plurality of multibit portions each of bit length A; (v) optionally shifting said plurality of non-adjacent multibit portions by a common shift amount to shifted bit positions; (vi) promoting each of said plurality of non-adjacent multibit portions from said bit length of A to a bit length of B to form a plurality of promoted multibit portions, such that said promoted multibit portions may be abutted to form a promoted data word; and (vii) performing a plurality of independent arithmetic operations using as input operands respective bit position portions of bit length B from both said promoted data word and said second different input data word to form a result data word.