Patent ID: 8266369

Claim:
A peripheral interface circuit for interfacing between a computer processor and a flash memory circuit communicatively connected to the interface by a peripheral interface bus, for storing and providing access to data that is stored on the flash memory circuit and mapped as a portion of main processor memory, the interface circuit comprising: a first-in, first-out (FIFO) buffer coupled to receive data from and store data for the flash memory circuit and to provide read access to the stored data; and an interface controller configured to communicate with the flash memory circuit via the peripheral interface bus, initialize the flash memory circuit for providing data to the FIFO buffer as a portion of the main memory, in response to a request for data starting at an address in a portion of main memory and having at least a portion thereof stored in the FIFO buffer, control the FIFO buffer to provide access to the stored data and control the flash memory circuit to provide additional data from subsequent addresses in the flash memory circuit to the FIFO buffer, and in response to a request for data starting at an address in portion of main memory and not stored in the FIFO buffer, control the flash memory circuit to provide the requested data and additional data from subsequent addresses in the flash memory circuit to the FIFO buffer.