Patent ID: 6923918

Claim:
A method for fabricating an intermediate structure for a cathode array of a flat panel display comprising: depositing a passivation layer of substantially nitride of silicon upon a base structure comprising an oxide of silicon inter-layer dielectric disposed upon a glass substrate, wherein said interlayer dielectric covers a first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor, said second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium; patterning said passivation layer according to a first pattern; in response to a determination that said passivation layer is to be etched without selectivity to nitrides of silicon with respect to oxides of silicon, further patterning said layer of chromium according to said first pattern; in response to a determination that said passivation layer is to be etched with selectivity to nitrides of silicon with respect to oxides of silicon sufficient to avoid undesirable etching of said interlayer dielectric layer, patterning said layer of chromium according to a second pattern, wherein said second pattern is separate from said first pattern; upon said patterning said layer of chromium according to said first pattern, etching said passivation layer using an etching technique selected from the group consisting of at least one of nitride of silicon dry etching, reactive ion etching, gaseous etching, and plasma assisted dry etching; upon said patterning said layer of chromium according to said second pattern, etching said passivation layer using nitrides of silicon dry etching; etching said layer of chromium; and etching said inter-layer dielectric using an inter-layer dielectric wet etch.