Patent ID: 7852707

Claim:
A data output control circuit, comprising: an output control signal generator configured to be responsive to a read command to output a plurality of first output source signals corresponding to rising edges of a system clock and a plurality of second output source signals corresponding to falling edges of the system clock; an output enable signal generator configured to generate a first rising enable signal using the first output source signals, to generate a second rising enable signal using the second output source signals, and to generate a falling enable signal using the first output source signals, wherein the falling enable signal is activated later than the first rising enable signal by one cycle of the system clock; a latch controller configured to enable a pipeline latch in response to the first rising enable signal and a delay locked loop (DLL) clock; a driver controller configured to enable a data output driver in response to the second rising enable signal, the falling enable signal and the DLL clock; and a strobe generator configured to output rising and falling data output signals in response to the second rising enable signal, the falling enable signal and the DLL clock.