Patent ID: 8006147

Claim:
An integrated circuit having at least one processing stage comprising: a speculative node; a checker node; precharge circuitry coupled to said speculative node and to said checker node to precharge said speculative node and to precharge said checker node; logic circuitry responsive to one or more input signals to provide a discharge path in dependence upon values of said one or more input signals; evaluation control circuitry responsive to at least one evaluation control signal to couple said speculative node to said logic circuitry to be discharged through said discharge path in dependence upon said one or more input signals and subsequently to couple said checker node to said logic circuitry to be discharged through said discharge path in dependence upon said one or more input signals; and error detection circuitry coupled to said speculative node and to said checker node to detect an error when any one of: (i) said speculative node is discharged and said checking node is undischarged; (ii) said speculative node is undischarged and said checking node is discharged; and (iii) said speculative node is partially discharged.