Patent ID: 7105440

Claim:
A method for forming a silicided gate structure in an FET device fabrication process, the gate structure having a gate dielectric on a substrate, the fabrication process including at least one high-temperature process, the method comprising the steps of: forming a first layer of silicon material overlying the gate dielectric; forming a layer of metal on the first layer; forming a second layer of silicon material on the metal layer, and performing the high-temperature process subsequent to said forming steps, wherein the high-temperature process is effective to form a first silicide layer in contact with the gate dielectric by reaction of the metal with the silicon material in the first layer, the silicon material in the first layer thereby being replaced by silicide material in the first silicide layer, wherein the first layer, the layer of metal and the second layer are formed with thicknesses so that as a result of the high-temperature process, substantially all of the first layer and at least a portion of the second layer are reacted with the metal to form the silicide material.