Patent ID: 7629778

Claim:
A voltage converter, comprising: a pulse width modulation controller chip comprising: a plurality of pins, the plurality of pins comprise a Vcc pin connected to a chip power supply, a BOOT pin connected to the Vcc pin via a first zener diode for receiving power from the chip power supply, a PHASE pin acting as a multi-function pin and connected to the BOOT pin via a capacitor, a UGATE pin, a LGATE pin, and a GND pin that is grounded; a gate control logic circuit for outputting a first drive signal and a second drive signal that is the inverse of the first drive signal; a first gate driver comprising an input terminal for receiving the first drive signal, a positive power supply terminal connected to the BOOT pin, a negative power supply terminal connected to the PHASE pin, and an output terminal for outputting a third drive signal corresponding to the first drive signal; a second gate driver comprising an input terminal for receiving the second drive signal, a positive power supply terminal connected to the Vcc pin, a negative power supply terminal connected to the GND pin, and an output terminal for outputting a fourth drive signal corresponding to the second drive signal, the fourth drive signal is the inverse of the third drive signal; a current source connected to a first node which is also connected to the cathode of a second zener diode, and the anode of the second zener diode is grounded; a first resistor with one terminal connected to the first node, and the other terminal connected the PHASE pin; a first comparator for generating a control signal when a voltage at the first node is higher than a first reference voltage; and a power-on reset circuit for generating a power-on reset signal in response to the control signal; a pull-up transistor comprising a gate connected to the UGATE pin for receiving the third drive signal, a source connected to a converter power supply, and a drain connected to the PHASE pin; a pull-down transistor comprising a drain connected to the PHASE pin, a gate connected to the LGATE pin for receiving the fourth drive signal, and a source that is grounded; and a low pass filter comprising an input terminal connected to the PHASE pin, and an output terminal serving as an output terminal of the voltage converter; wherein the gate control logic circuit generates the first and second drive signals in response to the power-on reset signal to switch the pull-up transistor and the pull-down transistor via the first and second gate driver, respectively.