Patent ID: 8065449

Claim:
A Direct Memory Access (DMA) device, comprising: a first buffer which holds a first transfer information required for a first transfer request; a second buffer which holds a second transfer information required for a second transfer request; a transfer request comparison circuit which determines whether or not a current transfer request, which is newly inputted, matches with the first transfer request or the second transfer request; a priority determination circuit that, in case where the transfer request comparison circuit determines that the current transfer request is not matched with the first transfer request or the second transfer request, updates the second transfer information to a transfer information for the current transfer request when a priority of the current transfer request is higher than a priority of the second transfer request, and updates the first transfer information to the transfer information for the current transfer request when the priority of the current transfer request is lower than the priority of the second transfer request; and a DMA transfer control circuit which carries out a DMA transfer using the transfer information held in the first buffer or the second buffer updated by the priority determination circuit.