Patent ID: 8087024

Claim:
An apparatus, comprising: multiple multi-threaded processors integrated on a single die, each of the multiple multi-threaded processors comprising an L1 instruction cache that stores instructions of a program to be executed, each of the multiple multi-threaded processors sharing an L2 instruction cache, each of the multiple multi-threaded processors configured to perform a fetch of instructions of the program from the L2 instruction cache to the multi-threaded processor's L1 instruction cache (1) in response to an explicit instruction of the program to perform a fetch of instructions; and (2) to perform a fetch of instructions from the L2 instruction cache if a cache miss of the L1 instruction cache occurs; and an arbiter to prioritize requests received from the multiple multi-threaded processors to fetch instructions from the L2 cache based on the whether a received instruction fetch request has been issued in response to an explicit instruction to perform a fetch of instructions or a received instruction fetch request from the L2 instruction cache has been issued in response to a cache miss of a multi-threaded processor's L1 instruction cache; wherein the L2 instruction cache comprises at least two queues to store fetch requests from the multiple multi-threaded processors, a first of the two queues to store fetch requests issued in response to an explicit instruction to perform a fetch of instructions, and a second of the two queues to store fetch requests issued in response to a cache miss of a multi-threaded processor's L1 instruction cache.