Patent ID: 7961014

Claim:
An electronic device comprising: a multi-mode driver configured to receive a first clock signal, and to output a second clock signal at least partly in response to the first clock signal; a first controller configured to provide one or more control signals to the multi-mode driver; and wherein the multi-mode driver comprises a circuit that is configured to selectively output one of different clock signals in response to the one or more control signals provided by the first controller; wherein the different clock signals comprise one or more of a clock signal having characteristics in compliance with the low voltage differential signaling (LVDS) standard, a clock signal having characteristics in compliance with the positive emitter-coupled logic (PECL) standard, a clock signal having characteristics in compliance with the low-voltage positive emitter-coupled logic (LVPECL) standard, or a clock signal having characteristics in compliance with the complementary metal-oxide-semiconductor (CMOS) standard; wherein the different clock signals further comprise a clock signal having characteristics in compliance with at least some conditions of the High-Speed Transceiver Logic (HSTL) standard; wherein the circuit of the multimode driver comprises: an H-bridge circuit; a first transistor coupled between the H-bridge circuit and a first voltage source; a second transistor coupled between the H-bridge circuit and a second voltage source; a first switch coupled between the H-bridge circuit and the first voltage source, wherein the first switch is coupled to the first transistor in parallel; and a second switch coupled between the H-bridge circuit and the second voltage source, wherein the second switch is coupled to the second transistor in parallel; wherein the H-bridge circuit comprises: a third transistor; a fourth transistor; a fifth transistor coupled to the third transistor in series; and a sixth transistor coupled to the fourth transistor in series, wherein the fourth and sixth transistors are coupled to the third and fifth transistors in parallel; and a current source controller, wherein the current source controller is configured to receive a control signal from the first controller, and wherein the current source controller comprises an output coupled to the gate of a seventh transistor.