Patent ID: 7804926

Claim:
A Phase Locked Loop, for synchronization of a clock signal with an incoming data signal, comprising a frequency detector including an unbalanced quadricorrelator, the quadricorrelator including a first multiplexer, a second multiplexer, and double edge clocked bi-stable circuits, supplied by incoming mutually quadrature phase shifted signals and coupled to the first multiplexer and to the second multiplexer, the first and second multiplexers controlled by a signal having a same bit-rate as the incoming signal; and a first phase detector that includes a D flip-flop that receives, as a data input, a first signal pair provided by the first multiplexer and that is clocked by a second signal pair provided by the second multiplexer; a first transistor pair receiving the second signal pair on respective gates for determining a state ON or OFF of a current through the first transistor pair; and a second transistor pair biased by current through the first transistor pair and receiving the first signal pair and generating an output signal indicative for a frequency error between the incoming data signal and the clock signal.