Patent ID: 7724861

Claim:
A digital phase lock loop, comprising: a first input to receive a first clock signal; an output to provide a second clock signal, the second clock signal based on the first clock signal; and a dividerless initial clock rate determination module to calculate an initial clock rate value based on a reciprocal of a measured pulse length of the first clock signal, wherein the dividerless initial clock rate determination module comprises an accumulator and a comparator; wherein in a first mode of operation the accumulator and the comparator are operable to calculate the initial clock rate value and wherein in a second mode of operation the accumulator and the comparator are operable to perform a digital filtering operation; and wherein the dividerless initial clock rate determination module includes a register to store a step size, an adder to subtract the step size from an initial value stored in the accumulator, and wherein the comparator compares an output of the adder to a predetermined adjustment value, wherein the step size is adjusted based on an output of the comparator.