Patent ID: 8514000

Claim:
A flip-flop having a data input terminal, a data output terminal and a clock terminal, the flip-flop comprising: a master latch having a master latch input coupled to the data input terminal and having a master latch output, wherein a master feedforward path is coupled between the master latch input and master latch output, wherein the master latch further comprises a master feedback path coupling an output end of the master feedforward path to an input end of the master feedforward path; a slave latch having a slave latch input coupled to the master latch output and having a slave latch output coupled to the data output terminal, wherein a slave feedforward path is coupled between the slave latch input and slave latch output, and the slave latch further comprises a slave feedback path coupling an output end of the slave feedforward path to an input end of the slave feedforward path; and an isolation element coupled between the master latch output and the input end of the slave feedforward path, the isolation element arranged to isolate capacitive loading seen by the output of the master latch that comes from the slave latch; wherein the master feedforward path includes a master forward drive element and one or more master forward drive enhancement elements; and wherein the master feedback path includes a master feedback drive element and one or more master feedback drive enhancement elements.