Patent ID: 6946353

Claim:
A method of manufacturing a semiconductor transistor of a first conductivity type, comprising: providing a semiconductor substrate; isolating an active region on the semiconductor substrate; forming a first structure on the active region, said first structure comprising a gate; forming a second structure on the semiconductor substrate, said second structure having a height (H) and being formed at a distance (S) from said first structure; implanting a dopant of said first conductivity type into the active region to form a source/drain region of said first conductivity type in said substrate between said first and second structures; implanting a dopant of a second conductivity type through said source/drain region so as to reduce the threshold voltage and parasitic junction capacitance of said transistor, wherein said dopant of second conductivity type is implanted at an angle with respect to the surface of said substrate such that the amount of dopant of second conductivity type implanted increases approaching said first structure and said second structure from a point in the active region about one-half the distance (S) between said first structure and said second structure.