Patent ID: 8700975

Claim:
A storage system comprising: a plurality of flash memory packages, each of the flash memory packages includes: a plurality of flash memory chips for storing data; and a memory controller configured to control reading/writing data to the plurality of flash memory chips, and a system controller including: a processor configured to control the plurality of flash memory packages as a RAID group; a cache memory coupled to the processor via an internal network; and a buffer memory, coupled to the processor and the cache memory via the internal network and coupled to each of the plurality of flash memory packages, and temporarily storing data to be transferred among the plurality of flash memory packages, and wherein: the processor: stores new data, which is sent from a host computer for updating old data stored in a first flash memory package included in the RAID group, into the cache memory; and transfers the new data from the cache memory to the first flash memory package, a first memory controller of the first flash memory package: stores the new data into a flash memory chip of the first flash memory package; and generates an intermediate parity from the new data and the old data; and transfers the intermediate parity from the first flash memory package to the buffer memory, while the memory controller maintains the new data and the old data as a valid status, the processor: transfers the intermediate parity to a second flash memory package storing old parity, which is to be updated according to updating of the old data, via the buffer memory without storing the intermediate parity into the cache memory, a second memory controller of the second flash memory package: receives the intermediate parity, generates a new parity from the intermediate parity and the old parity and stores the new parity into a flash memory chip of the second flash memory package, and the processor: sends a commit command to the first flash memory package for invalidating the old data after storing the new parity into the flash memory chip of the second flash memory package.