Patent ID: 7385859

Claim:
A semiconductor memory device, comprising: a column enable signal generator for generating a latency control signal, the latency control signal being activated after being delayed during a clock cycle corresponding to a latency signal when a read command is applied and deactivated after maintaining the activation state during a clock cycle corresponding to a burst length signal, and generating a buffered clock signal as a column enable signal in response to the latency control signal; a row enable signal generator for generating a row enable signal, the row enable signal being activated when a first time period lapses after a read command is applied and deactivated when a second time period lapses after the read command is applied; and a final column enable signal generator for generating a first signal in response to the column enable signal, the first signal being activated after being delayed during a first clock cycle from a time when the column enable signal is activated, generating a second signal in response to the row enable signal, outputting the second signal as a first final column enable signal, and outputting the first signal as a second final column enable signal.