Patent ID: 8304263

Claim:
A process of forming an integrated circuit, comprising the steps of: forming a test circuit by a process further including the steps: forming an oscillator having an oscillator output node; forming a calibration divider circuit having a calibration divider input node and a calibration divider output node, such that said calibration divider input node is connected to said oscillator output node; forming a starter divider circuit having a starter divider input node and a starter divider output node, such that said starter divider input node is connected to said oscillator output node; forming a test gate chain containing a number, N TEST , of test gates, wherein said test gates are connected in series between a test gate chain input node and a test gate chain output node, and wherein said test gate chain input node is connected to said starter divider output node; forming a reference gate chain containing a number, N REF , of reference gates, wherein said reference gates are connected in series between a reference gate chain input node and a reference gate chain output node, and wherein said reference gate chain input node is connected to said starter divider output node; forming a start/stop decoder circuit including a test input, a reference input, a start output and a stop output, wherein said test input is connected to said test gate chain output, wherein said reference input is connected to said reference gate chain output; and forming a counter circuit including a start input, a stop input, a clock input and a plurality of count outputs, wherein said start input is connected to said start output of said start/stop decoder circuit, said stop input is connected to said stop output of said start/stop decoder circuit, said clock input is connected to said oscillator output node; measuring a change in a gate delay time due to an applied stress, by a process further including the steps: calibrating an oscillator; measuring a first test gate chain delay time; measuring a second test gate chain delay time; and determining said change in a gate delay time.