Patent ID: 7071746

Claim:
A variable delay circuit for delaying and outputting a reference clock signal or a data signal, comprising: plural stages of first variable delay elements coupled in series for sequentially delaying said reference clock signal or data signal; a second variable delay element coupled in parallel to said plural stages of first variable delay elements for delaying said reference clock signal; a phase comparator for comparing a phase of said reference clock signal delayed by said plural stages of first variable delay elements with a phase of said reference clock signal delayed by said second variable delay element, said phase comparator inputting output signals of both said first variable delay elements and said second variable delay element; a delay amount control unit connecting to an output of said phase comparator for controlling a delay amount of each of said plural stages of first variable delay elements based on a comparison result of said phase comparator in order that said phase of said reference clock signal delayed by said plural stages of first variable delay elements is substantially the same as said phase of said reference clock signal delayed by said second variable delay element after predetermined cycles; and a selector for selecting one reference clock signal among a plurality of said reference clock signals or data signals outputted by each of said plural stages of first variable delay elements and supplying said one reference clock signal to said phase comparator, while selecting one reference clock signal among a plurality of said reference clock signals or data signals outputted by each of said plural stages of first variable delay elements in a reciprocally independent manner and outputting said one reference clock signal out of said variable delay circuit.