Patent ID: 8711077

Claim:
A driving circuit, comprising: a plurality of shift register units among which an N th -stage shift register unit includes: a node; an input circuit configured to maintain a voltage level of the node according to signals received from an X th -stage shift register unit among the plurality of shift register units; a pull-up circuit configured to selectively couple a first clock signal to an output end of the N th -stage shift register unit according to the voltage level of the node; and a pull-down circuit configured to selectively couple a second clock signal to a Y th -stage shift register unit among the plurality of shift register units according to the voltage level of the node, wherein a duty cycle of the second clock signal is larger than a duty cycle of the first clock signal, N is an integer larger than 1, X is a positive integer smaller than N, and Y is an integer larger than N; and an adjusting circuit configured to gradually shorten the duty cycle of the second clock signal after the driving circuit has been activated over a predetermined period of time.