Patent ID: 6845050

Claim:
A signal delay control circuit for use in a semiconductor memory device, the signal delay control circuit comprising: a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive an operation of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to respective ones of the internal circuits, wherein each of the reference voltages is set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits; wherein the impedance circuits comprises: a resistive circuit in circuit with the first and second reference voltage generating units for generating the plurality of reference voltages; and a plurality of data output units for outputting data bits from the semiconductor memory device in response to a respective one of the reference voltages, each of the reference voltages corresponding to a distance between the control signal generating unit and a respective one of the data output units.