Patent ID: 7590006

Claim:
A semiconductor memory device comprising: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data storage circuit configured to store data simultaneously read from or written into the memory cell array, the data constituting a page; and a data state judgment circuit configured to sequentially judge the data states of multiple divided areas, which are obtained by dividing the page, the data storage circuit comprising data latches prepared in a sense amplifier circuit for sensing data of the memory cell array, and the data state judgment circuit being a verify-judge circuit configured to sequentially verify-judge the divided areas based on verify-read data stored in the data latches, thereby to judge write completion or erase completion, the verify-judge circuit comprising: fail detection circuits disposed in the divided areas and configured to detect a fail number for the corresponding divided area; and a division control circuit configured to selectively activate the fail detection circuits.