Patent ID: 8589854

Claim:
A method to manage power in a custom integrated circuit (IC) design, comprising: a. receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; b. automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop (CIL) to compile, assemble and link code for each processor architecture iteration, the processor architecture generated by the CIL having one or more processing blocks and one or more power domains; c. generating functional block usage statistics from the profile and tracking usage of different processing blocks as a function of time; d. determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and e. gating the power domains with power based on the code profile; and f. identifying from the generated iterations the optimal architecture and synthesizing the optimal architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.