Patent ID: 8653862

Claim:
A frequency divider, comprising: a phase selection circuit, arranged to receive a plurality of input signals with different phases, and to generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals; a control circuit, arranged to receive the output signal to generate a plurality of control signals; and a retiming circuit, arranged to retime the control signals to generate the retimed signals according to the input signals; wherein the retiming circuit comprises a plurality of D latches, arranged to retime the control signals, respectively, wherein each of the D latches has an clock terminal arranged to receive a clock signal referenced from a corresponding input signal, a data terminal arranged to receive a data input referenced from a corresponding control signal, so as to output a corresponding retimed signal at an output terminal according to the clock input and the data input, and each of the D latches senses the data input referenced from the corresponding control signal for a first time interval to generate the retimed signal according to the data input when the clock signal referenced from the corresponding input signal is a first voltage level; and the D latch holds the retimed signal for a second time interval when the clock signal referenced from the corresponding input signal changes to a second voltage level different from the first voltage level.