Patent ID: 7100099

Claim:
A test apparatus for testing a device under test for synchronizing a data signal with a clock signal and outputting the same, comprising: a data sampler for sequentially sampling the data signals outputted from the device under test to acquire a plurality of data sample values; a data change point detection section for detecting a data change point at which the data signal is changed based on the plurality of data sample values acquired by the data sampler; a data change point storage section for writing the data change point detected by the data change point detection section based on a first clock signal and reading the same based on a second clock signal of which period is approximately same as the first clock signal and of which phase is different from the first clock signal; a clock sampler for sequentially sampling the clock signals outputted from the device under test to acquire a plurality of clock sample values; a clock change point detection section for detecting a clock change point at which the clock signal is changed based on the plurality of clock sample values acquired by the clock sampler; and a clock change point storage section for writing the clock change point detected by the clock change point detection section based on a third clock signal and reading the same based on the second clock signal; a phase difference detection section for comparing the data change point and the clock change point which are simultaneously read from the data change point storage section and the clock change point storage section based on the second clock signal and detecting the phase difference between the data signal and the clock signal; and a spec comparison section for comparing the phase difference detected by the phase difference detection section with a predetermined spec to determine that the device under test is passed or failed.