Patent ID: 8062962

Claim:
A method of forming a P-channel semiconductor device with good negative bias temperature instability (NBTI) reliability, the method comprising: providing a P-channel semiconductor device comprising a P-channel layer, and a control electrode on the semiconductor P-channel layer comprising at least a gate dielectric layer, the gate dielectric layer having an exponentially-shaped distribution of defect levels E(defect) in the energy bandgap, the exponentially-shaped distribution of defect levels having a lower concentration of defect levels at the center of the bandgap and a higher concentration of defect levels at the edges of the bandgap; and selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels deviates from the energy level at the center of the bandgap of a layer adjacent the gate dielectric layer at the same side of the gate dielectric layer as the P-channel layer, with a value not more than about 49% of that bandgap in eV.