Patent ID: 7049874

Claim:
A digital delaying device for delaying an input signal with digital type, the digital delaying device comprising: a ring oscillator having a plurality of delay cells connected in a loop, for outputting an oscillation clock; a calibration unit for receiving a reference clock and the oscillation clock and calculating a pulse number of the oscillation clock corresponding to each reference clock period, the pulse number serving as a period reference pulse number; at least one delay number calculation unit for receiving the period reference pulse number and a signal delay value, calculating a signal delay number corresponding to the signal delay value according to the period reference pulse number, and outputting a selection signal; a set of flip-flop for synchronously outputting the selection signal and an input signal; and at least one delay channel comprising a plurality of cascaded delay cells, the cascaded delay cells receiving the input signal output from the set of flip-flop, generating a plurality of delay signals with different delay timings, and selecting and outputting one of the delay signals as an output signal according to the selection signal output from the set of flip-flop.