Patent ID: 7721181

Claim:
A 1-bit error correction method performed on data in a memory, comprising: receiving at least one piece of data fragment, wherein the size of the data fragment is 2 n bits, n is an integer greater than or equal to 0; generating an error correction code, a parity code and a data code according to the data fragment; writing the data fragment, the error correction code, the parity code and the data code in a memory; reading the data fragment from the memory as a read data fragment, wherein the size of the read data fragment is 2 n bits; generating a new error correction code, a new parity code and a new data code according to the read data fragment; determining whether the read data fragment has a 1-bit error corresponding to the data fragment by comparing the error correction code and the new error correction code, the parity code and the new parity code, and the data code and the new data code, respectively; and correcting the 1-bit error according to the error correction code and the new error correction code, and the data code and the new data code if the read data fragment has the 1-bit error.