Patent ID: 8799841

Claim:
A method of designing an analog circuit, the method comprising: determining a first pareto-optimal design point for a first analog component within a circuit based on a parameter of the first analog component and a performance metric for the first analog component using a first simulation of a low level modeling simulation type; determining, using a processor, a second pareto-optimal design point for a second analog component using a second simulation that excludes the first analog component, the second simulation being of the low level modeling simulation type used for the first simulation, the second analog component being coupled to the first analog component within the circuit and the second pareto-optimal design point being based on a parameter of the second analog component, a performance metric for the second analog component, and a first constraint resulting from the first pareto-optimal design point; and selecting a first value for the parameter of the first analog component at least partially based on the first pareto-optimal design point.