Patent ID: 8035169

Claim:
A semiconductor device including a plurality of memory cells of SRAM, comprising: a semiconductor substrate; an element isolation region formed by filling a trench formed in the semiconductor substrate with an insulating film; a first active area which is defined by the element isolation region, which is formed by implanting a first conductive impurity into the semiconductor substrate and which extends in a first direction so as to span two or more of said memory cells; a second active area which is defined by the element isolation region, and which is formed by implanting the first conductive impurity into the semiconductor substrate, and which extends in the first direction so as to span two or more of said memory cells and which is isolated from the first active region by the element isolation region; a plurality of first n-type MISFETs and a plurality of second n-type MISFETs formed over the first active area, wherein first gate electrodes of the first n-type MISFETs extend in a second direction perpendicular to the first direction and wherein second gate electrodes of the second n-type MISFETs extend in the second direction; and a plurality of third n-type MISFETs and a plurality of fourth n-type MISFETs formed over the second active area, wherein third gate electrodes of the third n-type MISFETs extend in the second direction and wherein fourth gate electrodes of the fourth n-type MISFETs extend in the second direction, wherein each of the memory cells includes one of the first n-type MISFETs, one of the second n-type MISFETs, one of the third n-type MISFETs, and one of the fourth n-type MISFETs, wherein a width in the second direction of a first terminal section of the first active area is larger than a width in the second direction of the first active area where the first and second n-type MISFETs are formed, and wherein a width in the second direction of a second terminal section of the second active area is larger than a width in the second direction of the second active area where the third and fourth n-type MISFETs are formed.