Patent ID: 7286409

Claim:
A nonvolatile memory integrated circuit, comprising: nonvolatile memory cells, including: a plurality of data cells with a first operating margin, wherein the plurality of data cells are arranged into a plurality of data groups; and a plurality of margin detection cells with a second operating margin narrower than the first operating margin, the plurality of margin detection cells storing default data, wherein each data group of the plurality of data groups has at least one corresponding margin detection cell in the plurality of margin detection cells; one or more comparison memory cells storing the default data; one or more sets of sense amplifiers to sense the plurality of data cells and the plurality of margin detection cells; and control circuitry responding to a memory user mode command by applying bias arrangements to the plurality of data cells and the plurality of margin detection cells, wherein the bias arrangements are applied to: 1) at least one data cell of at least one data group of the plurality of data groups, 2) at least one corresponding margin detection cell of said at least one data group storing the default data, and 3) at least one of the comparison memory cells storing the default data, and wherein the control circuitry refreshes at least part of one or more data groups of the plurality of data groups, in response to a failure by said at least one corresponding margin detection cell to agree with said at least one of the comparison memory cells.