Patent ID: 8392867

Claim:
An integrated circuit performance modeling system comprising: an integrated circuit layout analyzer segmenting a layout of an integrated circuit into a plurality of sub-circuits, each sub-circuit comprising a group of a given type of active devices sharing electrical sub-circuit terminals and being subjected to approximate equal parasitic resistances; a netlist extractor in communication with said analyzer and extracting, from said layout, full netlists corresponding to said sub-circuits; a netlist condenser in communication with said netlist extractor and condensing each full netlist corresponding to a specific sub-circuit into a condensed netlist for said specific sub-circuit, said condensed netlist comprising: a single active device of said given type; and a plurality of parameterizable resistors, each parameterizable resistor electrically connected to a corresponding terminal of said single active device; and a simulator in communication with said condenser and simulating all condensed netlists for all of said sub-circuits over a full range of operating temperatures for said integrated circuit and over a full range of operating power supply voltages for said integrated circuit in order to generate a performance model for said integrated circuit.