Patent ID: 7088161

Claim:
A semiconductor integrated circuit comprising: a first flip-flop circuit which holds first input data in response to a first control signal; a second flip-flop circuit which holds second input data in response to a second control signal; a control circuit configured to generate a third control signal when at least one of the first and second flip-flop circuits holds the data; a combination circuit connected to an output terminal of said first and second flip-flop circuits, said combination circuit having an active state where power is supplied thereto and an inactive state where said power is interrupted, said combination circuit being set to said active state in response to a third control signal to hold data fed from said first and second flip-flop circuits; and a first logic circuit which has input terminals supplied with a fourth control signal and a clock signal and which has an output terminal connected to a clock signal input terminal of said first flip-flop circuit, said fourth control signal having a width equal to a period of said clock signal and rising immediately before said clock signal rises, said first logic circuit outputting said first control signal for a period when said fourth control signal is active.