Patent ID: 8030964

Claim:
A level shifter circuit comprising: an input circuit operable to generate a pull-up signal in response to an input signal using charge from a supply voltage; an inverter operable to invert the input signal to generate a pull-down signal, wherein the inverter comprises first and second complementary transistors operable to receive charge from the supply voltage; a pull-up circuit operable to pull a level shifted output signal at an output terminal of the level shifter circuit to the supply voltage in response to the pull-up signal; and a pull-down circuit operable to pull the level shifted output signal to a low voltage in response to the pull-down signal, wherein the pull-down circuit comprises a third transistor operable to receive the pull-down signal at a control input and a fourth cascode transistor coupled between the third transistor and the output terminal of the level shifter circuit, and wherein the fourth cascode transistor is operable to receive a first bias voltage at a control input that equals 50% or less of the supply voltage.