Patent ID: 7998795

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a lead frame comprising a chip mounting section, a plurality of suspension leads connecting to the chip mounting section, and a plurality of leads, wherein the chip mounting section has an upper surface and a lower surface opposing to the upper surface; (b) mounting a first semiconductor chip over a first area of the upper surface of the chip mounting section, wherein the first semiconductor chip has a first main surface, a first rear surface opposing to the first main surface, and a plurality of first pads formed on the first main surface; (c) mounting a second semiconductor chip over a second area of the upper surface of the chip mounting section, wherein the second semiconductor chip has a second main surface, a second rear surface opposing to the second main surface, and a plurality of second pads formed on the second main surface, and wherein the second area is adjacent to the first area; (d) disposing the chip mounting section on a heating jig such that the lower surface of the chip mounting section is supported by a surface of the heating jig, wherein the surface of the heating jig is substantially flatly formed; (e) electrically connecting the plurality of first pads of the first semiconductor chip with the plurality of second pads of the second semiconductor chip via a plurality of first wires, respectively; (f) electrically connecting the plurality of first pads of the first semiconductor chip with the plurality of leads via a plurality of second wires, respectively; (g) sealing the first semiconductor chip, the second semiconductor chip, the plurality of first wires and the plurality of second wires with resin such that a part of each of the plurality of leads is exposed from the resin; and (e) separating each of the plurality of leads from the lead frame, wherein the semiconductor device comprises a Quad Flat Package.