Patent ID: 8797110

Claim:
A system for managing a reference clock signal, the system comprising: a crystal oscillator (XO); a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first integrated circuit (IC) coupled to the signal buffer, the first IC comprising: an XO input buffer configured to receive the reference clock signal, wherein the XO input buffer is configured to be in an enabled, operational state or to be in a disabled state, and wherein the XO input buffer has a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state, and to be in a disabled state when the XO input buffer is in its enabled state, wherein the impedance equivalence circuit has a second operational impedance while operating in the enabled state that is substantially equivalent to the first operational impedance, wherein the impedance equivalence circuit is configured to consume less current in its enabled state than the XO input buffer is configured to consume in its enabled state; and a control mechanism coupled to the XO input buffer and the impedance equivalence circuit and configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.