Patent ID: 7281090

Claim:
A memory apparatus, comprising: an irreversibly writeable memory; a data processor operable to receive a request from a host processor for data stored at a logical address and to calculate a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation; and a table storage unit operable to store a block correlation table that includes block addresses of only unusable block portions in said irreversibly writeable memory and addresses of substitute block portions in said irreversibly writeable memory each associated with a specific one of the block addresses of the unusable block portions; said data processor being further operable to compare the physical address with the block address in the block correlation table, to reference the irreversibly writeable memory to read data stored at the physical address when the physical address does not match any of the block addresses in the block correlation table, to reference the irreversibly writeable memory to read data stored at the address of the associated substitute block portion when the physical address matches one of the block addresses in the block correlation table, and to transmit the read data to the host processor.