Patent ID: 8020163

Claim:
A system having computation resources and an on-chip communications network that interconnects said computation resources of said system, at least part of said computation resources comprising a processor, said system running an application and an operating system, said on-chip communications network comprising: a first on-chip data traffic network, interconnecting said computation resources, handling communication of the application data between said computation resources; a second on-chip control traffic network, separate from the data traffic network, interconnecting said computation resources, handling operation and management communications between said computation resources by the operating system, said first and second on-chip networks being physically separated; and a management resource that in at least one operation mode runs an operating system for said arrangement, at least part of said computation resources and said management resource being located on a same chip or on a single die, wherein at least part of said computation resources and said management resource are connected by the first on-chip data traffic network and the second on-chip control traffic network, wherein to each of said computation resources a communication resource is assigned, said communication resource including a control network interface component, providing information to said operating system via said second on-chip control traffic network, wherein said control network interface component sets and enforces an injection rate control mechanism on said data network interface component, under supervision of said operating system.