Patent ID: 8318571

Claim:
A method for forming a MOS device with an ultra shallow lightly doped diffusion region, the method comprising: providing a semiconductor substrate including a surface region; providing a gate dielectric layer overlying the surface region; forming a gate structure overlying a portion of the gate dielectric layer; performing a first implant process using a germanium species to form an amorphous region within a lightly doped drain region in the semiconductor substrate using the gate structure as a mask; performing a second implant process in the lightly doped drain region using a P type impurity and a carbon species using the gate structure as a mask; performing a first thermal process to activate the P type impurity in the lightly doped drain region; forming side wall spacers overlying a portion of the gate structure; performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region of the semiconductor substrate adjacent to the gate structure using the gate structure and the side wall spacers as a masking layer; and performing a second thermal process to activate the first impurity in the active source/drain regions; wherein the P type impurity is provided using a BF 2 precursor at an implant energy of 4.5 KeV to 10 KeV; wherein the first thermal process is a spike anneal process provided at a temperature ranging from 650 degrees Celsius to 800 degrees Celsius, wherein the second thermal process is a rapid thermal process provided at a temperature ranging from 700 degrees Celsius to 1000 degrees Celsius for a time period of 5 seconds to 10 seconds.