Patent ID: 6956923

Claim:
A phase locked loop circuit comprises: a phase detector operably coupled to produce phase information and transition information based on a feedback signal and an input data signal, wherein the phase detector includes: a first latch operably coupled to latch the input data signal based on a half-rate clock signal to produce a first latched signal; a second latch operably coupled to latch the first latched signal based on a complimentary half-rate clock signal to produce a second latched signal; a third latch operably coupled to latch the input data signal based on the complimentary half-rate clock signal to produce a third latched signal; a fourth latch operably coupled to latch the third latched signal based on the half-rate clock signal to produce a fourth latched signal; and combinational logic circuitry operably coupled to the first, second, third, and fourth latches to produce the phase information and the transition information, wherein the phase information is partially based upon the transition information and is reliably timed to a middle of the first bit period and the transition information is reliably timed for a beginning of the second bit period; an error signal generation module operably coupled to generate an error signal based on the phase information and the transition information; a controlled oscillation module operably coupled to convert the error signal into an oscillating signal; and a feedback module operably coupled to generate the feedback signal based on the oscillating signal and a divider value.