Patent ID: 7613110

Claim:
A storage device or memory storing one or more sequences of instructions, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform steps comprising: at a first network device, segregating received packets of best efforts traffic from received packets of one or more delay-sensitive flows; performing multilink processing for the best efforts traffic; wherein performing the multilink processing comprises: fragmenting a plurality of the packets of the best efforts traffic into fragments; encapsulating the fragments for transmission and adding fragment sequence numbers to headers of the encapsulated fragments; and transmitting the encapsulated fragments from the packets of the best efforts traffic over multiple communication links of a bundle of data communication links; wherein the bundle of data communication links is operable to connect the first network device to a second network device; performing per-flow load balancing for the one or more delay-sensitive flows; wherein performing the per-flow load balancing includes: encapsulating the packets of the one or more delay-sensitive flows for transmission without adding fragment sequence numbers to headers of the encapsulated packets; assigning each packet of a particular delay-sensitive flow, of the one or more delay-sensitive flows, to a single communication link of the bundle of data communication links, wherein the single communication link for the particular delay-sensitive flow is determined at least in part by hashing header information from the packet; and transmitting the encapsulated packets of the particular delay-sensitive flow over the single communication link by interleaving the encapsulated packets between those encapsulated fragments from the packets of the best efforts traffic that are transmitted on the single communication link.