Patent ID: 8901974

Claim:
A phase locked loop (PLL) comprising: a phase frequency detector (PFD) adapted to receive a feedback clock (SYSCLK) and a reference clock (REFCLK) and adapted to provide UP pulses and DOWN pulses for controlling the oscillation frequency of a controlled oscillator (VCO) in response to a phase and/or frequency difference between the feedback clock and the reference clock; a first charge pump (CP 1 ) adapted to receive the UP pulses and DOWN pulses from the phase frequency detector (PFD), wherein the first charge pump (CP 1 ) is further adapted to provide a first analog control signal to a first control input (PROP) of the controlled oscillator (VCO) to control its oscillation frequency in response to the UP pulses and DOWN pulses from the phase frequency detector (PFD), a second charge pump (CP 2 ) adapted to receive the UP pulses and DOWN pulses from the phase frequency detector (PFD), wherein the second charge pump (CP 2 ) is further adapted to provide a first analog storage control signal (FAST) and a second analog storage control signal (SLOW) corresponding to the UP pulses and DOWN pulses from the phase frequency detector (PFD) to a control stage (DCONT); said control stage (DCONT) adapted to provide a second analog control signal (D) to a second control input (VSUP) of the controlled oscillator (VCO) to control its oscillation frequency in response to the first analog storage control signal (FAST) and a second analog storage control signal (SLOW); said controlled oscillator (VCO) adapted to output an output signal (OUTVCO) with a desired oscillation frequency in response to the first analog control signal (ICH) received at the first control input (PROP) and the second analog control signal (D) to the second control input (VSUP); and a feedback loop adapted to feedback the output signal (OUTVCO) of the controlled oscillator (VCO) to the input of the phase frequency detector (PFD) as said feedback clock (SYSCLOCK); wherein the control stage (DCONT) comprises a plurality of storage elements (S 1 , S 2 ), a counter, and a digital-to-analog converter (DAC); wherein the control stage (DCONT) is adapted to continuously charge and reset, or discharge and reset each of the storage elements in respective cycles and in response to the first analog storage control signal (FAST) and a second analog storage control signal (SLOW), respectively; wherein the counter is adapted to increase or decrease its counter value in response to the number of charging cycles or discharging cycles performed by the storage elements (S 1 , S 2 ), respectively; wherein the digital-to-analog converter (DAC) is adapted to convert the counter value of the counter to a control current; and wherein the control stage (DCONT) is adapted to provide the control current of the digital-to-analog converter superimposed with currents representing the respective charging/discharging state of the respective storage elements as the second analog control signal (D) to the second control input (VSUP) to the controlled oscillator (VCO).