Patent ID: 7405124

Claim:
A fabricating method of a non-volatile memory, comprising: providing a substrate having a plurality of isolation structures extending in a first direction already formed thereon, the isolation structures protruding from the surface of the substrate, and a first mask layer formed on the substrate between the isolation structures; forming a second mask layer on the substrate; patterning the second mask layer and the first mask layer to form a plurality of openings extending in a second direction, the openings exposing a portion of the surface of the substrate and a portion of the surface of the isolation structures, wherein the first direction and the second direction are interlaced; forming a tunneling dielectric layer on the substrate; forming a first conductive layer on the substrate, the first conductive layer filling the openings and the first conductive layer being divided into blocks by the isolation structures, the second mask layer and the first mask layer; forming an inter-gate dielectric layer on the substrate; forming a second conductive layer on the substrate, the second conductive layer filling up the openings; and forming a plurality of doped regions in the substrate on both sides of the second conductive layer.