Patent ID: 7984226

Claim:
Routing circuitry for automatically routing either a first set of USB signals derived from an Ethernet local area network (LAN) at an Ethernet connector or a second set of USB signals derived from a USB host at a USB connector to an output connector which can interface with a data processing device comprising: a) USB supply voltage selection circuitry that passes a USB supply voltage from the first set of USB signals, or the second set of USB signals, or isolates the USB supply voltages from the first and second set of USB signals from the output connector in response to two or more first input signals; b) USB data selection circuitry that passes USB data signals from the first set of USB signals or the second set of USB signals to the output connector in response to one or more second input signals; and c) USB supply voltage detection circuitry that detects if the USB supply voltage from the second set of USB signals is present, and generates the two or more first input signals and the one or more second input signals in response to the detection; d) wherein the USB supply voltage detection circuitry generates a first set of first input signals which isolates the USB supply voltages from the first and second set of USB signals from the output connector when there is a change in the USB supply voltage from the second set of USB signals, and later generates a second set of first input signals to pass the USB data signals from the first set of USB signals or the second set of USB signals to the output connector, wherein the USB supply voltage detection circuitry includes a first node that changes from one of a high voltage state or low voltage state to the other of the high voltage state or low voltage state if there is a change in the USB supply voltage present on the USB connector, said first node coupled to said first and second set of input signals, wherein the USB supply voltage detection circuitry includes a delay circuit with an input coupled to the first node and an output coupled to a first of said first input signals, wherein the delay circuit includes delay stages wherein an output of a first delay stage is a second of the first input signals and the one or more second input signals, and an output of a last delay stage is the first of said first input signals.