Patent ID: 7196534

Claim:
A semiconductor test apparatus characterized by comprising: a first time interpolator to which clocks output from a device under test are input and which obtains the clocks by a plurality of strobes having constant timing intervals and which outputs the clocks as time-sequential level data; a second time interpolator to which output data output from the device under test are input and which obtains the output data by a plurality of strobes having constant timing intervals and which outputs the output data as time-sequential level data; and a first selection circuit which receives the time-sequential level data output from the first and second time interpolators, thereby selecting the output data input to the second time interpolator at edge timing of the clocks input to the first time interpolator, and outputting the selected data as measurement data of the device under test, the first and/or second time interpolator being equipped with an edge selector to which the time-sequential level data obtained by the plurality of strobes are input and which selectively outputs level data indicating timing of rising edges and/or falling edges of the level data.