Patent ID: 8352670

Claim:
A processor comprising: an execution core configured to execute instructions; and a register configured to store an execute-only valid indication indicative of whether or not execution of instructions is permitted in pages that are indicated as execute-only in a set of page tables used by the processor for address translation; wherein the execution core is configured, responsive to a fetch within an execute-only page, to signal a fault responsive to the execute-only valid indication indicating that execution is not permitted in the execute-only page, and wherein the execution core is configured to permit the fetch within the execute-only page responsive to the execute-only valid indication indicating that execution is permitted in the execute-only page, and wherein the execution core is configured to set the execute-only valid indication to a state indicating that execution is permitted in the execute-only page responsive to at least one predefined transition mechanism, and wherein the execution core is further configured to detect a return to code that initiated the predefined transition mechanism, wherein the execution core is configured to set the execute-only valid indication to a state indicating that execution is not permitted from the execute-only page.