Patent ID: 7826610

Claim:
A method to secure an electronic assembly having a processor and a storage means implementing a calculation process that calculates the result of a calculation that includes an elementary operation f(x) of a cryptography algorithm without performing the calculation f(x) thereby avoiding analysis of the operation of the electronic assembly using knowledge of the calculation f(x), the method comprising: operating the processor of the electronic assembly according to instructions stored in the storage means to perform an additional calculation by a verification function on at least one intermediate result in order to obtain a calculation signature; operating the processor of the electronic assembly according to instructions stored in the storage means to obtain the result of the elementary operation f(x) by performing a modified calculation in lieu of the elementary operation f(x) using a super-function operation acting from and/or to a larger set wherein a super-function f′ of a function f is defined as a function f′ such that h 2 (f′(h 1 (x)))=f(x) wherein h 1 is only a one-to-one mapping between a set E and a set E′ and h 2 is only an onto mapping of a set F′ in a set F, wherein x is a member of E and f(x) is a member of the set F; and operating the processor of the electronic assembly according to instructions stored in the storage means to perform an additional calculation by the verification function using the result obtained by the super function in order to obtain the calculation signature.