Patent ID: 7489178

Claim:
A level shifter circuit for receiving an input signal in a first voltage domain and generating an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said level shifter circuit comprising: a first buffer circuit operating in said first voltage domain and responsive to said input signal to generate an intermediate signal having either said first voltage level or said common voltage level; a second buffer circuit operating in said second voltage domain and responsive to said intermediate signal to generate said output signal having either said second voltage level or said common voltage level; and a feedback circuit operating in said second voltage domain and responsive to a feedback signal driven to said first voltage level by a circuit in said first domain, when said first buffer circuit generates said intermediate signal having said first voltage level, to boost said feedback signal to said second voltage level; wherein said second buffer circuit is coupled to said first buffer circuit so as to directly receive said intermediate signal and to be responsive to said intermediate signal having said common voltage level so as substantially to switch off current flow through said second buffer circuit and to generate an output signal having one of said second voltage level and said common voltage level; said second buffer circuit is coupled to said feedback circuit so as to receive said feedback signal and to be responsive to said feedback signal boosted to said second voltage level so as substantially to switch off current flow through said second buffer circuit and to generate an output signal having another of said one of said second voltage level and said common voltage level, and said feedback circuit is coupled to said second voltage supply by one or more supply interrupting transistors controlled by said input signal to temporarily interrupt feedback operation of said feedback circuit an thereby reduce said feedback circuit resisting changes in said feedback signal as driven by said circuit in said first domain driving said feedback signal.