Patent ID: 8455306

Claim:
A method of forming a voltage limiting device, comprising: providing a substrate having a first semiconductor region of a first conductivity type extending to a first surface; forming a buried layer of a second, opposite conductivity type; forming a first well region of the first conductivity type in the first region and extending to a first depth from the first surface, wherein the first well region overlies the buried layer; forming a second well region of the second conductivity type in the first region and extending to a second depth from the first surface, wherein the second well region overlies the buried layer and is electrically coupled to the buried layer, wherein the first and second well regions are on opposite sides of a PN junction located therebetween, wherein the first well region is configured to function as a first base of a first bipolar transistor of a first kind and as a second collector of a second bipolar transistor of a second, opposite, kind, and wherein the second well region is configured to function as a second base of the second bipolar transistor and as a first collector of the first transistor; providing a first more highly doped region of the second conductivity type in the first well region and a second more highly doped region of the second conductivity type in the second well region, wherein the first more highly doped region is configured to function as a first emitter of the first bipolar transistor and the second more highly doped region is configured to serve as a first collector contact of the first bipolar transistor; providing a third more highly doped region of the first conductivity type in the second well region and a fourth more highly doped region of the first conductivity type in the first well region, wherein the third more highly doped region is configured to function as a second emitter of the second bipolar transistor and the fourth more highly doped region is configured to serve as a second collector contact of the second bipolar transistor; providing a further well region of a third depth within the second well region, wherein the third depth of the further well region is less than the second depth of the second well region, and wherein the further well region is more heavily doped than the second well region; forming a first resistance electrically coupled between the first more highly doped region and the fourth more highly doped region; and forming a connection between the third more highly doped region and the second more highly doped region.