Patent ID: 7610417

Claim:
A memory module comprising: a. a variable-width data port, supporting first and second data widths, and an external address port; b. a memory die having a plurality of physical address locations, a data-mask terminal, and a fixed-width data port supporting a third data width wider than the first data width; and c. a data-width translator coupled between the variable-width data port and the fixed-width data port and between the external address port and the data-mask terminal, the data-width translator supporting multiple data-width configurations, the configurations including: i. a first data-width configuration in which the data-width translator translates first external data of the first data width on the variable-width data port to first internal data of the third data width on the fixed-width data port and translates address signals on the external address port to data-mask signals on the data-mask terminal of the memory die, wherein the data-mask signals are timed to divide the physical address locations of the memory die into temporal subsets of the physical address locations; and ii. a second data-width configuration in which the data-width translator translates second external data of the second data width on the variable-width data port to second internal of the third data width on the fixed-width data port.