Patent ID: 7094648

Claim:
A method for fabricating an NROM memory cell array, the method comprising: introducing dopant at a top side of a semiconductor body, in order to form source/drain regions; etching trenches arranged parallel at a distance from one another into the semiconductor body; forming bit lines running parallel to the trenches and arranged between adjacent ones of said trenches on the top side of the semiconductor body, each bit line being electrically conductively connected to source/drain regions located between the adjacent ones of the trenches; forming supporting structures outside a memory cell array region, the supporting structures being formed concurrently with the bit lines; applying a covering layer on the top side of the bit lines; applying a storage layer to the walls of the trenches; filling the trenches with conductive gate electrode material; after filling the trenches, removing the top side of said conductive gate electrode material in a planarizing manner until a top side of the covering layer is reached, wherein the supporting structures serve to support the planarizing outside the memory cell array region; after removing the material, depositing conductive word line material; and patterning the conductive word line material to form word lines that run transversely with respect to the direction of the bit lines, the word lines being electrically conductively coupled to gate electrode disposed within the trenches.