Patent ID: 7576582

Claim:
A clock gating circuit including a first inverter, a second inverter, a third inverter, an AND gate, a power terminal, a data terminal, a clock terminal, a sleep control terminal, and an output terminal, the clock gating circuit comprising: a first PMOS transistor electrically connected between the power terminal and the first inverter, a second PMOS transistor electrically connected between the power terminal and the second inverter, and a third PMOS transistor electrically connected between the power terminal and the AND gate wherein each of the first through third PMOS transistors is controlled by a sleep control signal applied via the sleep control terminal, each PMOS transistor having a high threshold voltage; and a first NMOS transistor electrically connected between a ground and the first inverter, a second NMOS transistor electrically connected between the ground and the second inverter, and a third NMOS transistor electrically connected between the ground and the AND gate wherein each of the first thorough third NMOS transistors is controlled by the sleep control signal, each NMOS transistor having a high threshold voltage; and a fourth PMOS transistor electrically connected between the output of the second inverter and the third inverter and having a high threshold voltage; and a fourth NMOS transistor electrically connected between the ground and the second inverter and having a high threshold voltage, wherein the first inverter receives and inverts a data signal to output the inverted signal of the first inverter under control of the sleep control signal, the second inverter for inverting the output signal from the first inverter to output the inverted signal of the second inverter under control of the sleep control signal, the AND gate circuit for receiving the output signal of the second inverter and a clock signal and outputting a gated signal under control of the sleep control signal, and the third inverter for inverting and outputting the output signal of the second inverter, wherein the output signal of the second inverter is inputted to the third inverter for inverting the output signal from the second inverter to output the inverted signal to the second inverter as a feedback signal under control of the clock signal.