Patent ID: 8856588

Claim:
An information processing apparatus comprising: a plurality of nodes that each comprise a storage device; and an interconnect that connects between the plurality of nodes, wherein at least one node of the plurality of nodes comprises: a detecting unit that detects a correctable error in data stored in a shared memory area included in a storage device of the one node or other node, the shared memory area being an area to which the one node and the other node access, and the correctable error being (i) an error which occurs more than a predetermined number of times within a predetermined time period or (ii) an error which occurs at a single location in the shared memory area; a prevention control unit that, when the detecting unit detects the correctable error, performs control to prevent the one node and the other node from accessing the shared memory area by deleting, from first address converting information which associates a virtual address used for memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the one node, an entry which associates a virtual address with a physical address in the shared memory area in which the correctable error is detected and by transmitting, to the other node, an instruction to delete the entry from second address converting information which associates the virtual address used for the memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the other node; a recovering unit that recovers the data stored in the shared memory area in a memory area different from the shared memory area; a notifying unit that notifies information about the different memory area to the other node; and a resumption control unit that performs control to resume the access to the recovered data from the one node and the other node.