Patent ID: 8552763

Claim:
A switch array comprising: a switch unit provided on a substrate, including; a first switch provided in the switch unit and including first and second memory cell transistors and a first pass transistor, the first memory cell transistor provided in a first active region in the substrate and including a first source, a first drain, and a first gate, the second memory cell transistor provided in the first active region adjacent to the first memory cell transistor in a channel length direction of the first memory cell transistor and including the first drain shared with the first memory cell transistor, a second source, and a second gate, and the first pass transistor provided in a second active region in the substrate and including a second drain, a third source, and a third gate connected to the first drain; and a second switch provided in the switch unit and including third and fourth memory cell transistors and a second pass transistor, the third memory cell transistor provided in the first active region adjacent to the second memory cell transistor in the channel length direction of the first memory cell transistor and including the second source shared with the second memory cell transistor, a third drain, and a fourth gate, the fourth memory cell transistor provided in the first active region adjacent to the third memory cell transistor in the channel length direction of the first memory cell transistor and including the third drain shared with the third memory cell transistor, a fourth source, and a fifth gate, and the second pass transistor provided in the second active region adjacent to the first pass transistor in the channel length direction of the first pass transistor and including a fourth drain, a fifth source, and a sixth gate connected to the third drain, wherein the first and second active regions are adjacent to each other in a channel width direction of each transistor.