Patent ID: 8893064

Claim:
A system comprising: a memory storing a design for a complex semiconductor structure, said complex semiconductor structure comprising multiple electrically connected multi-terminal semiconductor devices having first terminals connected to a first node by first interconnects, second terminals connected to a second node by a second interconnects, and third terminals connected to a third node by a third interconnects; and at least one processor accessing said design in said memory and comprising: a parasitic extraction tool generating a full resistor network for said complex semiconductor structure and modifying said full resistor network multiple discrete times to generate at least a first modified resistor network wherein said second terminals and said second node are electrically shorted, a second modified resistor network wherein said first terminals and said first node are electrically shorted and a third modified resistor network wherein said first terminals and said first node are electrically shorted and said second terminals and said second node are electrically shorted; and a simulation tool performing multiple simulations comprising at least a first simulation using said first modified resistor network to obtain a first result, a second simulation using said second modified resistor network to obtain a second result, and a third simulation using said third modified resistor network to obtain a third result, and said simulation tool further determining a first merged resistance value associated with said first terminals based on said first result, a second merged resistance value associated with said second terminals based on said second result, and a third merged resistance value associated with said third terminals based on said third result.