Patent ID: 7123252

Claim:
A liquid crystal display device with a multi-timing controller, comprising: a liquid crystal display panel having a display standard; an interface receiving a timing data inputted from the exterior thereof and a control signal corresponding to the display standard; a timing controller for latching and outputting the timing data inputted from the interface, and for generating and outputting timing signals for driving the liquid crystal display panel based on the control signal; and a driving circuit for receiving the timing signals outputted from the timing controller to display a picture corresponding to the display standard, wherein said timing controller includes a decoder and a timing generator, wherein timing generation information corresponding to a plurality of display standards is stored by the decoder, wherein the decoder outputs, to the timing generator, timing information corresponding to the timing data, wherein the timing generator outputs timing signals corresponding to the timing information and the control signal, wherein the timing generator includes a first controller for generating the timing signal corresponding to the timing information selected from the decoder and a second controller for generating a liquid crystal polarity inversion signal indicating a driving voltage polarity of the liquid crystal provided on the liquid crystal display panel and a gate drive starting signal for notifying a first drive line of a field from one vertical synchronizing signal, a third controller for generating a signal information a sampling start of a data and a source sampling clock for latching a data at the rising or falling edge during one horizontal synchronization period, a fourth controller for deforming a gate output enable signal generated from the first controller by making the gate output enable signal into a high state during a certain time so as to prevent a latch-up badness in which all the outputs of a gate drive integrate circuit goes to a high state thereby disabling the gate drive integrated circuits, and a fifth controller for always equally keeping the polarity of the horizontal/vertical synchronizing signal.