Patent ID: 6849503

Claim:
A method for forming metal interconnections for a flash memory device, which comprises the steps of: providing a semiconductor substrate having cell and peripheral regions defined therein; forming gates on the substrate; forming a source and a drain in the substrate at both sides of each of the gates; partially etching the gate of the peripheral region to form a first contact hole; successively forming a silicon nitride film and a first oxide film on the entire surface of the gate including the first contact hole; selectively etching the first oxide film using the silicon nitride film as an etch stopper, to form a second contact hole exposing the source of the cell region; forming a first plug filling the second contact hole; forming a second oxide film on the substrate including the first plug; selectively etching the second and first oxide films to form third contact holes which expose the drain of the cell region, the source of the peripheral region, end the first contact hole in the gate of the peripheral region, respectively; forming second plugs filling the third contact holes; forming a third oxide film on the substrate including the second plugs; selectively etching the third oxide film to form third contact holes of a dual damascene trench type, which expose the first plug, the second plugs, and a portion of the second oxide film corresponding to the drain of the peripheral region, respectively; etching the second and first oxide films using the third oxide film as a mask, to form fourth contact holes which expose the first plug, the second plugs and the drain of the peripheral region; and forming metal interconnections filling the fourth contact holes.