Patent ID: 8054109

Claim:
A differential input buffer, comprising: a buffer circuit having separate p- and n-channel differential amplifiers arranged to each receive a pair of input signals, the p- and n-channel differential amplifiers each being at least partially self-biased; first and second pairs of enabling series transistors, wherein the p- and n-channel differential amplifiers are each coupled to a respective one of the first and second pairs of enabling series transistors, each of the first and second pairs of enabling series transistors comprising: a pair of n-channel transistors coupled to ground, and a gate for receiving an enabling signal; at least one of the p-channel differential amplifier and n-channel differential amplifier being coupled to an enable transistor; and a first output terminal for combining outputs of the p- and n-channel differential amplifiers to form a first output of the differential input buffer, the first output terminal being coupled to at least one pair of output series transistors.