Patent ID: 7254208

Claim:
A frequency extension circuit, comprising: a first delay line having a plurality of taps, and receiving a reference clock at an input thereof, wherein the reference clock has a clock rate of F REF , and wherein the first delay line is situated within a feedback loop of a delay locked loop and thereby locked to F REF with a total delay of the first delay line being adjusted under feedback control from the delay locked loop; a second delay line having a plurality of taps, and receiving the reference clock at an input thereof; and a logic circuit that combines signals from the delay line taps of the first delay line with signals from the delay line taps of the second delay line such that the n th tap of the first delay line is combined with the n- 1 st tap of the second delay line for each of a plurality of N taps in the first delay line, wherein the logic circuit produces, as an output thereof, a collection of clock pulses having a clock rate of multiples of F REF *N.