Patent ID: 7724586

Claim:
A static random access memory (SRAM) local evaluation circuit enabling read and write operations of an associated SRAM cell group comprising: a precharge write signal; a first precharge device being connected between a voltage supply VDD and a true bitline; a second precharge device being connected between the voltage supply VDD and a complement bitline; a precharge signal disabling said first and second precharge devices during read and write operations; a first passgate device being connected between the complement bitline and a true write data propagation input; a second passgate device being connected between the true bitline and a complement write data propagation input; said true and complement write data propagation inputs being held high during read operations; said complement write data propagation input transitioning low before a write zero operation and being held high during a write one operation, and said true write data propagation input transitioning low before the write one operation and being held high during the write zero operation; said precharge write signal disabling said first passgate device and said second passgate device during read operations; said precharge write signal enabling said first passgate device and said second passgate device during write operations.