Patent ID: 6992522

Claim:
A negative voltage boosting circuit comprising: at least five boosting unit circuits, each including a MOS transistor for transferring charge, the source or the drain of which is connected to an input terminal of the boosting unit circuit and the other of the source or drain of which is connected to an output terminal of the boosting unit circuit, wherein the boosting unit circuits are connected in series between an input terminal of the negative voltage boosting circuit and an output terminal of the negative voltage boosting circuit for generating negative voltage at the output terminal, wherein a well region forming a channel region of the MOS transistor for one boosting unit circuit for transferring charge, is biased by electric potential at the output terminal of another boosting unit circuit in an output direction, and wherein: at least one boosting unit circuit connected in series after a fourth boosting unit circuit in an output direction from a first boosting unit circuit connected to the input terminal of the negative voltage boosting circuit comprises: a first capacitative element to one end of which a first clock signal is applied and the other end of which is connected to the gate of the MOS transistor for transferring charge of the at least one boosting unit circuit; a second capacitative element to one end of which a second clock signal is applied and the other end of which is connected to the input terminal of the at least one boosting unit circuit; and a second MOS transistor the gate of which is connected to the input terminal of the second boosting unit circuit in an input direction, the source of which is connected to the gate of the MOS transistor for transferring charge of the at least one boosting unit circuit and the drain of which is connected to the output terminal of the at least one boosting unit circuit.