Patent ID: 7539811

Claim:
A scaleable memory system, comprising: a plurality of memory circuits, each memory circuit is fabricated on a substrate and includes a register for storing a unique address; a bus, an input bus logic coupled with the bus and operative to receive a data access request on an input port and to communicate the data access request to the bus, an output bus logic coupled with the bus and operative to output data access requests from the bus on an output port, the input bus logic and the output bus logic are operable to be electrically coupled with other memory devices, and at least one memory bank having at least one memory array fabricated above the substrate; and a memory controller coupled with the input port of one of the plurality of memory circuits, a remainder of the plurality of memory circuits are chained together by coupling the output port of one memory circuit with the input port of another memory circuit, the memory controller operative to receive a data access request, decode the request to determine if an incoming address included in the request matches the unique address of any one of the plurality of memory circuits, directing the data access request to the memory circuit whose unique address matches the incoming address, or passing the request to the outgoing bus of a last of the plurality of memory circuits, wherein the memory controller is an embedded controller coupled with a controller enable node, the controller enable node operative to allow internal control of the incoming bus logic by the embedded controller when enabled and to allow external control of the incoming bus logic by the memory controller when disabled, and the embedded controller, when enabled, is operative to control which data access requests received by the incoming bus logic are passed through the bus to the plurality of memory arrays and which data access requests received by the incoming bus logic are passed through to the bus to the outgoing bus logic.