Patent ID: 7187210

Claim:
A P-domino register, comprising: a domino stage, coupled to a pulsed clock signal, and for evaluating a logic function according to the states of at least one data signal and said pulsed clock signal, wherein said domino stage pre-charges a pre-charged node low when said pulsed clock signal is high, and discharges said pre-charged node to a high state if said logic function evaluates when said pulsed clock signal is low, and keeps said pre-charged node low if said logic function fails to evaluate when said pulsed clock signal is low, wherein a setup state of said at least one data signal is provided to said domino stage when said pulsed clock signal is high; a write stage, coupled to said domino stage and responsive to said pulsed clock signal, which pulls a first preliminary output node low if said pre-charged node goes high and which pulls said first preliminary output node high if said pre-charged node stays low; an inverter having an input coupled to said first preliminary output node and an output coupled to a second preliminary output node; a low keeper path which keeps said first preliminary output node low when enabled, wherein said low keeper path is enabled when said pulsed clock signal and said second preliminary output node are both high and which is otherwise disabled; a high keeper path which keeps said first preliminary output node high when enabled, wherein said high keeper path is enabled when said second preliminary output node and said pre-charged node are both low and which is otherwise disabled; and an output stage which provides an output signal based on states of said pre-charged node and said second preliminary output node.