Patent ID: 7412669

Claim:
A processor-implemented method for generating a block diagram of an electronic circuit design, comprising: identifying by a processor from an input textual description of the electronic circuit design, each multi-master bus, bus master of a multi-master bus, bus slave of a multi-master bus, memory, co-processor and input/output port; representing in a memory coupled to the processor, diagrammatic placement of each input/output port about a perimeter of a first area; representing in the memory, a bus area, a master area, and a slave area within the first area; representing in the memory, placement in the bus area of each multi-master bus; representing in the memory, placement in the master area of each bus master, wherein no bus master is placed between another bus master and a multi-master bus; representing in the memory, a group of bus slaves of a multi-master bus, wherein each bus slave in the group has a slave connection to the multi-master bus and no other connection to any bus master of the multi-master bus; representing in the memory, placement of the group of bus slaves as a single block in the bus area, wherein the group is diagrammatically aligned with a bus master of the multi-master bus to which the group of bus slaves is connected; representing in the memory, connections between each multi-master bus and each bus master of the multi-master bus and a connection between the multi-master bus and the group of bus slaves with respective connection lines; and outputting a diagrammatic representation consistent with the representations of the placement of each identified multi-master bus, bus master, bus slave, and connections.