Patent ID: 7724591

Claim:
A semiconductor memory device, comprising: a memory cell array that is arrayed on a plurality of mats; an even number of redundancy Y switch signal lines that are provided in three mat units and arranged in the bit line direction on the mat that is positioned in the middle among the three mats that are disposed continuously in the word line direction; a local input/output (LIO) line that is connected to a sense amplifier portion of the three mats, extends in the word line direction, and is divided in two in a redundancy area that is a part of the even number of redundancy Y switch signal lines; and a plurality of bit line selecting Y switch signal lines that connect bit line output of the memory cell array on the three mats to the local input/output line; wherein 8-bit data prefetch is performed from the three mats by selecting the plurality of bit line selecting Y switch signal lines and turning them ON simultaneously so as to connect the selected bit line output to each local input/output line divided in two.