Patent ID: 7435990

Claim:
A semiconductor wafer, comprising: a semiconductor substrate; a plurality of integrated circuit chips formed in said substrate; said plurality of integrated circuit chips formed on said semiconductor substrate and arranged in a plurality of rows and columns; said rows being separated one row from the other by a respective row kerf there between and said columns separated one column from the other by a respective column kerf; a first tester interface circuit on said wafer adjacent said rows of said integrated circuit chips; said first tester interface circuit coupled through a first respective wiring path in respective row kerfs to each chip adjacent to said respective row kerfs; and a second tester interface circuit on said wafer adjacent said columns of said integrated circuit chips; said second tester interface circuit coupled through a second respective wiring path in respective column kerfs to each chip adjacent to said respective column kerfs on said wafer; said first wiring path including a plurality of distinct stimulus busses in each said row kerf area for providing each integrated circuit chip with power, parallel serial scan data, clock, control, chip enable data enable signals and an output means for obtaining the response of said integrated circuit chips to such signals; said second wiring path including a plurality of distinct stimulus busses in each said column kerf area for providing each integrated circuit chip with power, parallel serial scan data, clock, control, chip enable data enable signals and an output means for obtaining the response of said integrated circuit chips to such signals.