Patent ID: 8295098

Claim:
A memory device comprising: a memory array having a plurality of data lines; a first sense circuit coupled to the plurality of data lines and configured to sense a first and a second group of memory cells of the memory array; and a second sense circuit coupled to the plurality of data lines and configured to receive data transferred from the first sense circuit; wherein the first or second circuits comprise: a pair of inverters configured as a latch circuit; a pair of transistors coupled to an output of the latch circuit as an output circuit; first and second transistors coupled in series and further coupled to an input of the latch circuit; a pull-up transistor coupled between the first and second transistor and coupled to a voltage source; and a pair of series coupled transistors coupled between a ground potential and an input of the first or second sense circuits, a first transistor of the series coupled transistors having a gate coupled to an input of the latch circuit.