Patent ID: 7420831

Claim:
A semiconductor chip comprising: a memory cell array adapted to store data; a control circuit adapted to control an operation mode of the memory cell array in accordance with a plurality of signals received from outside of the semiconductor chip; and, a chip selection signal generating circuit electrically connected to first and second option pads, wherein: the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal; the dual chip enable signal is set to a default logic level when the semiconductor chip is in a power up mode; the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit; the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with a first voltage signal received through the first option pad and a second voltage signal received through the second option pad, or in accordance with a chip selection address signal received through the first option pad and a third voltage signal received through the second option pad; the chip selection signal generating circuit is also adapted to generate a chip selection signal having a first logic level when the first voltage signal is received through the first option pad and the second voltage signal is received through the second option pad; the chip selection signal generating circuit is also adapted to generate a chip selection signal having the first logic level or a second logic level in accordance with a logic level of the chip selection address signal and a logic level of the third voltage signal when the chip selection address signal is received through the first option pad and the third address signal is received through the second option pad; and, the control circuit is enabled when the control circuit receives the chip selection signal having the first logic level.