Patent ID: 7799678

Claim:
A method of forming a through substrate via comprising: providing a substrate having at least one transistor device, at least one insulating layer, and an interlevel dielectric (ILD) formed overlying the at least one insulating layer and the at least one transistor device; selecting a desired location of a through substrate via on the substrate; determining that an insulating layer of the at least one insulating layer at the desired location is subject to forming a recess greater than a threshold amount during a subsequent reactive ion etching step for forming a portion of the through substrate via; implementing through substrate via compensation, wherein the through substrate via compensation includes one selected from the group consisting of (i) forming the through substrate via at the desired location, (ii) relocating placement of the through substrate via from the desired location to another location, and (iii) locally replacing the insulating layer of the at least one insulating layer at the desired location with an insulating layer not subject to forming a recess greater than the threshold amount; forming an opening in the ILD and the at least one insulating layer at one of (i) the desired location and (ii) a location determined as a function of implementing the through substrate via compensation, wherein a portion of the at least one insulating layer at the desired location or at the location determined as a function of implementing the through substrate via compensation is exposed within the opening; etching the substrate with a reactive ion etch to form a via portion of the through substrate via; forming a conformal dielectric liner overlying a top surface of the semiconductor substrate and within the via; and forming a conductive material within the via portion.