Patent ID: 7356553

Claim:
A data processing apparatus for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent, the data processing apparatus comprising: processing logic providing multiple processing paths which are selectable to perform the data processing operation, including a first processing path operable to perform the data processing operation if a predetermined alignment condition exists; at least one detector logic unit operable to receive both said first exponent and said second exponent, and to detect the presence of said predetermined alignment condition, each detector logic unit comprising: half adder logic operable to perform a number of half adder operations to logically subtract one of the first and second exponents from the other of the first and second exponents to produce at least a sum data value; and generation logic operable to receive the sum data value and to generate a select signal which is set if the sum data value has a predetermined value indicating the existence of said predetermined alignment condition; the processing logic being operable to select the first data processing path to perform the data processing operation if the select signal from one of said at least one detector logic unit is set.