Patent ID: 8482074

Claim:
A semiconductor device, comprising: a trench formed at a prescribed element isolation region on a substrate, the trench having its inside filled with an element isolation film; a first gate oxide film formed on a first active region, the first active region being at least a part of a plurality of active regions partitioned by the element isolation film; a first transistor formed in each of the active regions in the first active region, the first transistor having a source region and a drain region each formed at a part of a region of a surface of the substrate, a channel region between the source region and the drain region, and a gate electrode formed over the channel region having the first gate oxide film interposed therebetween; and a second gate oxide film formed on a second active region, the second active region being at least a part of a prescribed region other than the first active region among the plurality of active regions partitioned by the element isolation film, the second gate oxide film having a thickness smaller than that of the first gate oxide film, wherein a top surface of the first gate oxide film is located at a position lower than a top surface of the element isolation film, the top surface of the first gate oxide film being flat over each of the entire active regions in the first active region, the closer a bottom surface of the first gate oxide film at a peripheral portion of each of the active regions is to a boundary between the active region and the element isolation region, the more it is inclined downward, and the first gate oxide film at the peripheral portion of the active region and the element isolation film adjacent thereto are free of a void.