Patent ID: 7400683

Claim:
A device comprising: a decode processor configured to (i) divide a first picture from a video signal into a plurality of picture segments, (ii) divide each one of said picture segments into a plurality of tiles and (iii) generate a list associating each one of said tiles to a corresponding one page of a plurality of pages in a corresponding one bank of a plurality of banks in a first memory such that each one of said picture segments has (a) at least a first one of said tiles associated with a first of said banks and (b) at least a second one of said tiles associated with a second of said banks; a direct memory access unit configured to store said first picture in said first memory according to said list; and a memory manager configured to (i) generate a map allocating space in said first memory to store said first picture and (ii) transfer an identification value identifying said map to said decode processor, wherein (a) said decode processor is further configured to transfer said identification value to said direct memory access unit and (b) said direct memory access unit is further configured to use said identification value to locate said map.