Patent ID: 8400857

Claim:
A sensing circuit for sensing a content of a memory cell, the sensing circuit comprising a sense node connectable to the memory cell so that a signal indicative of the content of the memory cell is made available at the sense node, wherein the sense node is between first and second cascade transistors arranged in series, and the series arrangement of cascade transistors connects to the memory cell, characterised in that the circuit comprises: a logic gate having a first input, a second input and an output, wherein a reference signal is provided to the first input, wherein the sense node is coupled to the second input, a first feedback loop for coupling the output of the logic gate to the second input of the logic gate so that; during sensing the content of the memory cell, an electrical potential at the sense node is kept at a constant value derived from the output voltage of the logic gate and a switch for controlling the connection between the sense node and the memory cell, the switch being in series with the first and second cascade transistors; and a second feedback loop providing a signal which depends on a signal provided at the output of the logic gate for controlling the switch so that the logic gate is disconnectable from the memory cell.