Patent ID: 7456486

Claim:
A semiconductor integrated circuit device comprising: a logic element of a microprocessor; and a memory cell of a static random access memory, the memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first transfer MISFET and a second transfer MISFET, the first n-channel MISFET and the second n-channel MISFET each having a gate electrode formed over a semiconductor substrate, and a source region and a drain region in the semiconductor substrate, the first p-channel MISFET and the second p-channel MISFET each having a gate electrode over the semiconductor substrate, and a source region and a drain region in the semiconductor substrate, the first transfer MISFET and the second transfer MISFET each having a gate electrode over the semiconductor substrate, and a source region and a drain region in the semiconductor substrate such that a first silicide layer, a second silicide layer and a third silicide layer are located over the gate electrode, the source region and the drain region, respectively; a first insulating film over the MISFETs; a first conductive film and a second conductive film on the first insulating film and comprised of a different conductive layer from the gate electrodes of the MISFETs, the first conductive film electrically connected to the drain region of the first n-channel MISFET, the drain region of the first p-channel MISFET, the gate electrode of the second n-channel MISFET, the gate electrode of the second p-channel MISFET, and one of the source region and the drain region of the first transfer MISFET, the second conductive film electrically connected to the drain region of the second n-channel MISFET, the drain region of the second p-channel MISFET, the gate electrode of the first n-channel MISFET, the gate electrode of the first p-channel MISFET, and one of the source region and the drain region of the second transfer MISFET; a second insulating film over the first conductive film and the second conductive film; a power source line over the second insulating film and electrically connected to the source region of the first p-channel MISFET and the source region of the second p-channel MISFET; and a reference voltage line over the second insulating film, formed from the same level layer as the power source line and electrically connected to the source region of the first n-channel MISFET and the source region of the second n-channel MISFET.