Patent ID: 8115526

Claim:
A PLL oscillator circuit, comprising: a voltage controlled oscillator that generates a frequency signal for oscillation in accordance with an input control voltage; a PLL-IC that receives an external reference signal and an oscillatory output signal from the voltage controlled oscillator as input, compares phase between the external reference signal and the oscillatory output signal to detect a phase difference therebetween, and outputs a phase differential signal corresponding to the phase difference, while outputting a lock detection signal indicating a lock state where the signals are locked or an unlock state where the signals are not locked; a loop filter that cancels noise of a high-frequency component in the phase differential signal from the PLL-IC; and a processor that receives a lock detection signal from the PLL-IC, sets data for unlock alarm test at the PLL-IC, the data turning a lock state into an unlock state, when determining an unlock state with the lock detection signal from the PLL-IC, outputs an unlock alarm output signal to the outside, determines whether or not the unlock state continues for a first time period, and when the unlock state continues for the first time period, executes retry to set data for relock at the PLL-IC.