Patent ID: 7696567

Claim:
A memory device comprising; a recessed gate that is recessed in a semiconductor material, wherein the recessed gate has first and second lateral sides; a first source/drain formed in the semiconductor material adjacent a first lateral side of the recessed gate, the first source/drain having an upper surface and a lower surface in the semiconductor material; a second source/drain formed in the semiconductor material adjacent a second lateral side of the recessed gate, the second source/drain having an upper surface and a lower surface in the semiconductor material, wherein the application of voltage to the gate results in the formation of a conductive channel between the first and second source/drains along a path that is recessed into the semiconductor material; a charge storage device formed above the semiconductor material, wherein the charge storage device is electrically coupled to the first source/drain; and a conductive data line interposed between the charge storage device and the semiconductor material, the conductive data line being electrically coupled to the second source/drain, wherein an upper surface of the gate is elevationally below the first and second source/drain upper surfaces, the upper surface of the gate being elevationally closer to the second source/drain lower surface than to the second source/drain upper surface.