Patent ID: 8091014

Claim:
An electronic apparatus comprising a first microcomputer and a second microcomputer coupled for communication with one another, wherein said first microcomputer is configured to repetitively execute a first calculation procedure of successively setting predetermined bit patterns in respective registers of a CPU (central processing unit) core of said first microcomputer and executing predetermined calculation processing which utilizes said registers, said bit patterns and calculations being predetermined such that a specific fixed value is obtained as a final result from said calculations when each of said registers are functioning normally, a second calculation procedure of updating a variable value and adding said final result to said updated variable value, to obtain a sum value, and a transmission procedure of transmitting information expressing said sum value, and information expressing said variable value which was utilized in calculating said sum value, to said second microcomputer; and wherein said second microcomputer is configured to execute a subtraction procedure of operating on said information expressing said sum value and said variable value, for subtracting said variable value from said sum value to thereby obtain a subtraction value, and a judgement procedure of judging whether or not said subtraction value is identical to said specific fixed value, and determining whether or not abnormal operation of said first microcomputer is occurring, based on results of said judgement.