Patent ID: 8799565

Claim:
A memory controlling device comprising: a request generating section configured to generate memory requests from a data access request to a memory controlled in each of memory banks; a row selecting information retaining section configured to retain a plurality of opcodes, memory bank numbers specifying said memory banks, and row addresses specifying row addresses in said memory banks in said memory requests as row selecting information while maintaining input order of said memory requests; a column selecting information retaining section configured to separately retain a plurality of said opcodes, said memory bank numbers, column addresses specifying column addresses in said memory banks, and data lengths of data to be accessed according to said memory requests in said memory requests as column selecting information while maintaining the input order of said memory requests; a memory bank information managing section configured to manage a state of operation of said memory as memory bank information for each of said memory banks; a command generating section configured to generate a plurality of commands designating operation related to said memory banks at a frequency lower than frequency of a memory clock of said memory on a basis of said row selecting information, said column selecting information, and said memory bank information; and a command aligning section configured to align said plurality of generated commands in synchronism with said memory clock.