Patent ID: 8327081

Claim:
An information processing apparatus including a system controller and a main memory and a plurality of processors connected each other and connected to the main memory via the system controller, the processor comprising: a cache memory that holds a part of data stored in the main memory for each data block of a cache line, and that holds cache state information indicating each state of each data block held in the cache line; and a cache controller that controls the cache memory by using the state of the data block by six states of an invalid state, a shared state, an exclusive state, a modified state, a shared modified state, and a writable modified state, wherein the system controller comprises a snoop control unit that receives a data transfer reply upon completion of a snooping process by the system controller, performs address locking on an object data block until the next state is determined, receives an object data block causing a cache hit and cache state information indicating a new state of a data block replaced by the object data block in a cache memory included in a processor of a data transfer destination from a processor transmitting the object data block when the next state of the replaced data block is not determined upon completion of the snooping process by the system controller, and changes a state of the replaced data block into the new state by using the received cache state information.