Patent ID: 8294151

Claim:
A thin film transistor (TFT) array panel comprising: an insulating substrate; a first gate line and a second gate line formed on the insulating substrate, the second gate line adjacent to the first gate line; a gate insulating layer formed on the first and second gate lines; a semiconductor layer formed on the gate insulating layer and overlapping a portion of the second gate line; a first data line formed on the semiconductor layer and including a source electrode; a drain electrode including a first portion facing the source electrode with respect to the semiconductor layer, and a second portion extending parallel with and adjacent to the first data line, the second portion extending from the first portion toward and proximate the first gate line; a conductive layer directly connected to the drain electrode and proximate the first gate line; an insulating layer formed on the semiconductor layer, the first data line, the drain electrode, and the conductive layer; and a pixel electrode formed on the insulating layer and electrically connected to the conductive layer through a contact hole proximate the first gate line, wherein the second portion of the drain electrode is located near a boundary of the pixel electrode and is covered by a black matrix.