Patent ID: 8178879

Claim:
An array substrate for a display device, comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode and having the same plane area and the same plane shape as the gate electrode; an active layer on the gate insulating layer and exposing an edge of the gate insulating layer; an interlayer insulating layer on a surface of the substrate including the active layer formed thereon and including first and second active contact holes, the first and second active contact holes respectively exposing both sides of the active layer; first and second ohmic contact layers contacting the active layer through the first and second active contact holes, respectively; a source electrode on the first ohmic contact layer; a drain electrode on the second ohmic contact layer; a data line on the interlayer insulating layer and connected to the source electrode; a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon, the first passivation layer, the interlayer insulating layer and the gate insulating layer have a first gate contact hole exposing a portion of the gate electrode; a gate line on the first passivation layer and contacting the gate electrode through the first gate contact hole, the gate line crossing the data line; a second passivation layer on a surface of the first passivation layer including the gate line formed thereon, the first passivation layer and the second passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the second passivation layer and contacting the drain electrode through the drain contact hole.