Patent ID: 8427496

Claim:
A system for data transfer across a graphics bus in a computer system, comprising: a bridge; a system memory coupled to the bridge; a graphics bus coupled to the bridge; and a graphics processor coupled to the graphics bus, wherein the graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge, wherein the bridge is configured to divide the graphics data into a plurality of system memory aligned tiles and store the tiles into the system memory, wherein the system memory aligned tiles are aligned with a minimum data access size, and wherein the graphics data is compressed to at least a four to one ratio; wherein the graphics processor includes a transfer logic unit for merging the compressed graphics data into tiles of pre-existing graphics data stored in the system memory; and wherein a data merge is performed by a transfer logic unit fetching and decompressing pre-existing graphics data from tiles, decompressing the compressed graphics data from the GPU, and generating merged data therefrom, wherein the system memory is used as temporary storage, and wherein the merged data is then compressed by the transfer logic unit and stored, in alignment, in the tiles of the system memory.