Patent ID: 7773153

Claim:
A frame-based phase-locked display controller for displaying a plurality of image frames in a video signal, the display controller comprising: a frame-based phase-locked loop for receiving an oscillating signal and an input vertical synchronous signal to generate an output clock signal based on said image frames, the frame-based phase-locked loop comprising: an active pixel region generator for receiving the input vertical synchronous signal to generate a reference signal associated with an active pixel region; a phase frequency detector, for detecting a phase difference between the reference signal and an output display enable (DE) signal to convert said phase difference into an up/down signal; a first PLL for receiving said oscillating signal; a frequency synthesizer, coupled to said first PLL, for receiving said up/down signal; and a second PLL, coupled to said frequency synthesizer, for generating said output clock signal; and a synchronization signal generator, coupled to said frame-based phase-locked loop, for receiving said output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and the output display enable (DE) signal.