Patent ID: 7460630

Claim:
A data transmitter for transmitting parallel data of plural bits to a receiver, the data transmitter comprising: a synchronous signal generating circuit which generates a transmitter synchronous signal using a reference signal; a pattern generating circuit which generates a training pattern for each bit of the parallel data, in synchronization with the transmitter synchronous signal; and an output circuit which transmits the training pattern and the parallel data bit by bit to the receiver, in which a receiver synchronous signal is generated using the reference signal, a memory position of a data buffer circuit is initialized upon detection of the training pattern, an adjusted clock signal for each bit of the parallel data is generated by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for each one-bit data signal, each one-bit data signal is loaded into the data buffer circuit in accordance with the adjusted clock signal, a predetermined number of bits of the data consecutive in time is held in the data buffer circuit, and data of plural bits stored in the data buffer circuit is selected in time sequence and read out as parallel data, in accordance with a second clock signal and in synchronization with the receiver synchronous signal.