Patent ID: 6851096

Claim:
A wafer testing apparatus comprising: a sample chuck having a flat surface for supporting a wafer positioned thereon, said sample chuck having a base structure manufactured of a conductive metal and having a semiconductor layer secured to the base structure defining the flat surface of the sample chuck, said base structure having a plurality of passages therein that are connected to a vacuum source, there being a plurality of tiny openings extending through the semiconductor layer in communication with the passages in the base structure, said sample chuck having a reference origin and axis, and means for orienting a wafer relative to the reference origin and axis; an electrical test probe arranged to make contact with the flat surface of the semiconductor layer and the surface of a wafer positioned thereon; semiconductor layer test means associated with the electrical test probe for determining and recording electrical properties of the semiconductor layer and base structure data at a plurality of locations arrayed over the semiconductor layer surface; wafer test means associated with the electrical test probe for determining electrical property data at a location on the surface of a wafer positioned on the sample chuck; and means for establishing a correction factor based upon the data recorded by the semiconductor layer test means corresponding to a location on the semiconductor layer surface to be used with the wafer test means to report an electrical property at a location on the wafer substantially unaffected by the electrical properties of the semiconductor layer and base structure below that location.