Patent ID: 7692983

Claim:
A memory system, comprising: a first buffer chip directly mounted on a motherboard; at least one first memory chip coupled to the first buffer chip and directly mounted on the motherboard; a plurality of first signal traces routed on the motherboard to the first buffer chip and the at least one first memory chip; and a first phase locked loop directly mounted on the motherboard and capable of generating a first clock signal on a second clock trace responsive to a system clock signal on a first clock trace, wherein the first buffer chip is capable of buffering signals outputted from a memory controller and providing them to the at least one first memory chip, wherein the at least one first memory chip is operated in synchronization with the first clock signal, wherein the memory controller generates a command and address signal, and also generates the system clock signal and a data signal, and is mounted directly on the motherboard, wherein the system eliminates signal reflection caused by signal trace discontinuities of the first buffer chip and the at least one first memory chip by directly mounting the first buffer chip and the at least one first memory chip on the motherboard without an intervening socket.