Patent ID: 7392347

Claim:
A system for processing memory transaction requests, comprising: a controller for storing and retrieving cache lines to and from a plurality of memory components through at least one bus; and a buffer communicatively coupled to said controller and said at least one bus; wherein said controller formats cache lines into a plurality of portions, implements an error correction code (ECC) scheme to correct a single-byte error in an ECC code word for pairs of said plurality of portions, stores respective pairs of plurality of portions such that each single-byte of at least one of said respective pairs of said plurality of portions is stored in a different one of said plurality of memory components; and wherein when said controller processes a memory transaction request that modifies tag data without modifying cache line data, (i) said controller communicates new tag data to said buffer and (ii) said buffer calculates new ECC data utilizing previous ECC data, previous tag data, and said new tag data without requiring communication of cache line data.