Patent ID: 8421243

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes: a main part that includes a plurality of layer portions stacked and has a top surface and a bottom surface; and a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the wiring; the plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion; each of the first-type and second-type layer portions includes a semiconductor chip; the first-type layer portion further includes a plurality of first-type electrodes that are electrically connected to the semiconductor chip and to the wiring; the second-type layer portion further includes a plurality of second-type electrodes that are electrically connected to the wiring and not to the semiconductor chip; and the plurality of first terminals are formed by using the plurality of first-type or second-type electrodes of the uppermost one of the layer portions.