Patent ID: 6967506

Claim:
A circuit arrangement, in particular, an integrated circuit arrangement, for the discrete-time comparison of input signals (ip, vrefp; ip, vrefp, in, vrefn) and for making available a pair of complementary binary output potentials (vdd, vss) that corresponds to the result of the comparison on a pair of lines (P, N), comprising a reset circuit ( 12 ) for balancing potentials in a first section (p 1 , n 1 ) of the line pair (P, N) during the first time interval (reset), an input circuit ( 14 ), to which the input signals (ip, vrefp; ip, vrefp, in, vrefn) are applied, wherein said input circuit serves for generating a potential difference on the first section (p 1 , n 1 ) of the line pair (P, N) in accordance with an input signal difference at the beginning of a second time interval (phase 1 ), a first bistable flip-flop ( 16 ) for connecting one (p 1 or n 1 ) of the two line sections of the first section (p 1 , n 1 ) of the line pair (P, N) to a first supply potential (vdd) in accordance with the generated potential difference, a connecting circuit ( 18 ) for connecting the first section (p 1 , n 1 ) of the line pair (P, N) to a second section (p 2 , n 2 ) of the line pair (P, N) during a third time interval (phase 2 ), and a second bistable flip-flop ( 20 ) for connecting one (n 2 or p 2 ) of the two line sections of the second section (p 2 , n 2 ) of the line pair (P, N) to a second supply potential (vss) in accordance with the generated potential difference, characterized by a third bistable flip-flop ( 30 ) for connecting one (P or N) of the two lines (P, N) to the first supply potential (vdd) in accordance with the generated potential difference during the third time interval (phase 2 ).