Patent ID: 8276015

Claim:
A method for managing a power-performance range of a processor core, the method comprising: receiving a maximum processor frequency value and a minimum processor frequency value; setting the maximum processor frequency value in a first hardware register associated with a first processor core, and setting the minimum processor frequency value in a second hardware register associated with the first processor core, the first and second hardware registers operatively coupled to automatically direct power-performance control circuitry; executing, on the first processor core, instructions associated with a first software application; while executing the instructions associated with the first software application and independent of such execution, using the power-performance control circuitry to determine a processor core activity level of the first processor core, and control an operating frequency of the first processor core based on changes in the processor core activity level, with the power-performance control circuitry controlling the operating frequency of the first processor core to be in a range between the maximum processor frequency value and the minimum processor frequency value utilizing the first and second hardware registers; and adjusting a digital phase-locked loop circuit using the power-performance control circuitry.