Patent ID: 7525464

Claim:
An apparatus including a sigma-delta modulator, comprising: an input electrode to convey an analog input signal; one or more output electrodes to convey one or more digital output signals; one or more adder circuits, wherein a first adder circuit is coupled to said input electrode to receive said analog input signal and one of one or more analog feedback signals and provide a first one of one or more summation signals, and each remaining one of said one or more adder circuits is to receive a respective upstream one of one or more integration signals and a respective additional one of said one or more analog feedback signals and provide a respective additional one of said one or more summation signals; one or more integrator circuits, wherein a first integrator circuit is coupled to said first adder circuit to receive said first one of said one or more summation signals and provide a first one of said one or more integration signals, and a last integrator circuit is coupled to a last one of said one or more adder circuits to receive a last one of said one or more summation signals and provide a last one of said one or more integration signals; analog-to-digital converter (ADC) circuitry coupled to said last integrator circuit and responsive to said last one of said one or more integration signals by providing an N-bit digital signal; truncation circuitry coupled between said ADC circuitry and said one or more output electrodes and responsive to said N-bit digital signal by providing said one or more digital output signals including an M-bit digital signal, wherein N>M; and digital-to-analog converter (DAC) circuitry coupled between said one or more output electrodes and each of said one or more adder circuits to receive at least one of said one or more digital output signals and provide said one or more analog feedback signals.