Patent ID: 8283729

Claim:
A semiconductor device comprising: a first MIS transistor having a first gate insulating film, a first gate electrode formed above the first gate insulating film and a first source/drain regions near the first gate electrode in a first region; a second MIS transistor having a second gate insulating film thicker than the first gate insulating film, a second gate electrode formed above the second gate insulating film and a second source/drain regions near the second gate electrode in a second region; an ESD protection element including a resistor connected to the second MIS transistor; a salicide block insulating film formed over the resistor with an insulating film thinner than the second gate insulating film interposed therebetween; and a silicide film formed on the first source/drain regions and the second source/drain regions; wherein the resistor includes at least two different impurity diffusion profiles, wherein one of the two different impurity diffusion profiles having a peak near a region beneath the insulating film.