Patent ID: 8004066

Claim:
A method of manufacturing a semiconductor device, the method comprising: manufacturing a plurality of integrated circuits on a semiconductor wafer, each integrated circuit of the plurality of integrated circuits comprising a peripheral region proximate an edge; forming a barrier structure comprising a integrated moisture barrier and a crack stop proximate the peripheral region of each of the plurality of integrated circuits, the barrier structure comprising discrete conductive features, wherein a length of the discrete conductive features is larger than a width or a height of the discrete conductive features, wherein the discrete conductive features are arranged around each of the integrated circuit along the length in a plurality of parallel rows in a plane disposed parallel to a top surface of the semiconductor device, wherein the discrete conductive features are discontinuous along the length, wherein the discrete conductive features comprises first horseshoe-shaped features arranged in a first row and second horseshoe-shaped features arranged in a second row, the second row being parallel to the first row, wherein each of the first horseshoe-shaped features has an opening in a direction opposite to an opening of at least one adjacent second horseshoe-shaped feature of the second horseshoe-shaped features; and separating the plurality of integrated circuits from one another proximate the barrier structure of each integrated circuit.