Patent ID: 8247863

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series; and select transistors each connected to one of the ends of the memory strings, each of the memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion joining lower ends of the pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer and functioning as a control electrode of the memory cells, and each of the select transistors comprising: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer and functioning as a control electrode of the select transistors, the first semiconductor layer being formed continuously in an integrated manner with the second semiconductor layer, and the first insulating layer being formed continuously in an integrated manner with the third insulating layer.