Patent ID: 7202131

Claim:
A method of fabricating a semiconductor device, comprising the steps of: forming a gate insulating layer on a semiconductor substrate; after forming said gate insulating layer, forming a channel ion area in the substrate; after forming said channel ion area, forming a gate electrode on the gate insulating layer; implanting first ions at a low dose in to substrate using the gate electrode as a mask prior to forming a sidewall insulating layer or a spacer on sidewalls of the gate electrode; after implanting said first ions, forming the sidewall insulating layer on the gate elcetrode; implanting second ions at a low dose into the substrate to form lightly doped regions in the substrate adjacent to the channel ion area and aligned with to gate electrode; forming a spacer insulating layer on the sidewall insulating layer forming spacers on sidewalls of the gate electrode by etching to spacer insulating layer and the sidewall insulating layer; and forming heavily doped regions in the substrate aligned wit the spacers.