Patent ID: 8249099

Claim:
A device for managing data for a digital signal processor, comprising: external random access memory (RAM), configured to store channel specific data for plural different channels; and a microprocessor, in communication with the external RAM through a cache; and wherein the microprocessor is configured to facilitate: when receiving the packet, in a transport layer processing the packet, determining a channel of the plural different channels corresponding to an indication in a transport layer header of the received packet fetching channel specific data specific to the channel into an internal memory internal to the microprocessor from the external RAM, by the transport layer, before the packet is passed to an application layer, thereby avoiding a wait for reading the packet at the application layer; and regrouping channel specific data within the channel specific buffers to group pre-determined data together, the pre-determined data being pre-determined to be most frequently used by an application, the pre-determined data requiring plural cache lines when ungrouped and requiring fewer cache lines when regrouped.