Patent ID: 7333663

Claim:
An apparatus for encoding image data, comprising: discrete-wavelet transform (“DWT”) coefficient words converted into sign-magnitude format to provide bit-planes organized as predefined data units, the data units being multi-bit words wherein each of the multi-bit words holds a respective multi-bit stripe for each bit-plane of the bit-planes; a memory configured to store the bit-planes associated with the image data, the memory configured to store the bit-planes as multi-bit stripes, the multi-bit stripes being for each of the bit-planes; a bit modeler coupled with the memory, the bit modeler configured to produce modeled data in response to each of the data units for each of the bit-planes; the bit modeler configured to process the bit-planes of the data units in parallel to produce the modeled data; the bit modeler configured to model each of the multi-bit stripes of each of the bit-planes in a plurality of coding operations performed in parallel on each of the data units processed; the modeled data being decision/context pairs; the bit modeler having a plurality of output terminals, wherein each of the output terminals is configured to provide a plurality of the decision/context pairs for each of multi-bit stripes; the bit modeler having a multiplexer circuitry, window logic circuits, and modeling circuits; the multiplexer circuitry having input terminals respectively associated with the bit-planes and output terminals respectively associated with at least two of the bit-planes; the multiplexer circuitry configured to multiplex stripes of a magnitude portion of the bit-planes to output selected stripes; the window logic circuits respectively coupled to the output terminals of the multiplexer circuitry; the window logic circuits configured to window the selected stripes responsive to a sign portion of the bit-planes and significance flags respectively associated with the selected stripes to provide the bit planes with context information; the modeling circuits respectively coupled to the window logic circuits; the modeling circuits capable of performing three coding passes in parallel on each of the bit planes wherein each pass thereof includes performing one of four coding primitives responsive to the context information to generate the plurality of the decision/context pairs; an arithmetic coder coupled to receive the plurality of the decision/context pairs from the bit modeler, the arithmetic coder configured to produce coded data in response to the modeled data produced; and the arithmetic coder configured to process the plurality of the decision/context pairs for the bit-planes associated therewith in parallel.