Patent ID: RE43947

Claim:
A delay locked loop for providing a delay for a reference clock signal, the delay locked loop having a plurality of at least one potential lock point s at plural delays , and the delay locked loop comprising: a lock point proximity detector which detects proximity to the at least one potential lock points point ; an initialization control circuit coupled to an output of the lock point proximity detector , said initialization control circuit being connected to a multiplexer ; a voltage controlled delay line; and an inverting circuit being connected to the voltage controlled delay line, and connected to the multiplexer, the inverting circuit capable of outputting at least that includes a multiplexer and at least one inverter having an output coupled to an input of said multiplexer, said inverting circuit for enabling selection of a single one of two clock signals , based on an output of the initialization control circuit , to vary the delay of the reference clock signal ; and a variable delay line having an output coupled to said inverting circuit .