Patent ID: 7810061

Claim:
A computer implemented method of determining a useful skew for a circuit design, comprising: using a computer configured for: identifying a plurality of sequential cells in the circuit design; determining an input slack value at an input pin and an output slack value at an output pin of each of the plurality of sequential cells along a path in the circuit design, wherein the input slack value comprises a required time and an arrival time at the input pin of the each of the plurality of the sequential cells; identifying one or more modifiable sequential cells from the plurality of sequential cells in the circuit design; discarding one or more of the plurality of sequential cells based at least in part on whether a clock tree is already built; determining a target slack value for each of at least some of the one or more modifiable sequential cells, wherein the target slack value comprises a statistical measure of the input slack value and the output slack value for the each of the at least some of the one or more modifiable sequential cells; comparing the target slack value with one or more previously determined target slack values to determine a minimum target slack value; and determining an amount of delay for the each of the at least some of the one or more modifiable sequential cells based at least in part on the minimum target slack value, in which the action of determining the amount of delay is characterized by being capable of being performed regardless of whether or not a clock tree for the circuit design has been built.