Patent ID: 7463278

Claim:
A pixel clock generation circuit, comprising: a high frequency clock generation unit configured to generate a high frequency clock; a clock modulation data generation unit configured to generate clock modulation data based on pixel clock phase data indicating timing of a transition in the pixel clock; a modulation clock generation unit, including a shift register, configured to load the clock modulation data to the shift register in response to a load signal, to shift the clock modulation data based on the high frequency clock outputted from the high frequency clock generation unit, and to modulate the phase of the pixel clock based on a high frequency clock and the shifted clock modulation data to generate a modulated pixel clock; and a phase adjustment unit that adjusts the phase of an output from each shift register of the pixel clock generation circuit; the phase adjustment unit comprising M×N registers (N columns), and where the output from each shift register is latched to each register for a first stage based on high frequency clocks the phase of which is the same, and then shifted using high frequency clocks the phase of which is different from each other.