Patent ID: 7529132

Claim:
A single-poly non-volatile memory, comprising a plurality of non-volatile memory cells, the non-volatile memory cells comprising: a first N-type transistor having a source, a gate and a drain, wherein the source connects to a source line; a second N-type transistor having a source, a gate and a drain, wherein the drain connects to a bit line, the source commonly shares the drain of the first transistor, and the gate connects to a word line; a third N-type transistor having a source, a gate and a drain; a fourth N-type transistor having a source, a gate and a drain, wherein the source commonly shares the drain of the third transistor, the drain connects to a control line, and the gate connects to the word line; and a floating gate connected to the gates of the first and third N-type transistors; wherein the ratio of the gate capacitance of the first N-type transistor to that of the third N-type transistor is smaller than 2:3.