Patent ID: 8486834

Claim:
A method for manufacturing a memory device, comprising: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide; forming an oxide layer on the substrate after performing the oxidation process; forming a patterned photoresist layer on the oxide layer, exposing the top surface of the oxide layer directly over the polysilicon plug etching the oxide layer with the patterned photoresist layer as a mask, exposing the top surface of the polysilicon plug; and forming a conductive layer to electrically connect with the polysilicon plug.