Patent ID: 7129116

Claim:
A method of forming a plurality of electronic packages using partially patterned lead frames comprising the steps of: providing a film having a top surface and a bottom surface; partially patterning the film from the top surface but not entirely through to the bottom surface in a first region, leaving a second region on the film not partially patterned from the top surface, the second region forming a plurality of partially patterned lead frames, each having chip receiving area for supporting an integrated circuit (IC) chip and a plurality of electrical leads for providing electrical connections to the IC chip; the first region forming a webbed structure interconnecting the chip receiving areas and electrical leads of each lead frame and connecting the plurality of lead frames to one another in street portions of the film; providing a plurality of chips each having a plurality of electrical terminals for attachment to a corresponding lead frame; attaching each chip to the chip receiving area on a corresponding lead frame; forming an electrical connection between at least one terminal of each chip and one of the electrical leads of the lead frame; encapsulating the lead frames by applying an encapsulant material over the lead frames and the street portions of the film; back patterning from the bottom surface of the film the first region to remove the webbed structure and the street portions of the film; and singulating the encapsulant material disposed over the street portions of the film to form individual chip scale packages.