Patent ID: 7463681

Claim:
A method of designing a system configuration for a decision feedback equalizer (DFE) for handling an incoming signal, comprising the steps of: providing a buffer for receiving said incoming signal; providing an inter symbol interference (ISI) loop for addressing removal of ISI caused on symbols, using symbol decisions; providing an inter chip interference (ICI) loop for addressing removal of ICI caused on chips, using chip decisions; and, using buffer and chip management based on timing delay in a feedback loop for selecting a system configuration for said DFE to remove ISI and ICI, wherein said incoming signal is encoded with complementary code keying (CCK) symbols, said incoming signal has code-words/symbols each having chips, and said step of using buffer and chip management allows for symbol decision based cleaning for ISI removal by the ISI loop, followed by chip decision based cleaning for ICI removal by the ICI loop.