Patent ID: 7894260

Claim:
A synchronous semiconductor memory device comprising: an on-die termination (ODT) circuit configured to generate ODT up and down signals for performing an ODT operation synchronously to an external clock in response to the ODT up and down signals, wherein the on-die termination (ODT) circuit comprises: a plurality of unit drivers, wherein each of said unit drivers comprises, at least one pull-up resistive element having a first end directly connected to a common node of said unit driver, at least one pull-down resistive element having a first end directly connected to the common node of said unit driver, at least one pull-up transistor having a drain connected to a second end of the pull-up resistive element, a source connected to a power voltage, and a gate configured to respond to the ODT up signal, and at least one pull-down transistor having a drain connected to second end of the pull-down resistive element, a source connected to a ground voltage, and a gate configured to respond to the ODT down signal, wherein the common nodes of the unit drivers are coupled together to an output pad of the device.