Patent ID: 8049330

Claim:
A light emitting diode (LED) wafer-level chip scale packaging, comprising: an LED with a positive electrode and a negative electrode disposed on one side thereof; a carrier substrate having a plurality of through holes, which are filled with an electrically and thermally conductive material, wherein the positive electrode and the negative electrode of said LED are attached to a first surface of said carrier substrate, wherein the positive electrode is electrically and thermally connected to a first one of said through holes and the negative electrode is electrically and thermally connected to a second one of said through holes; a thermally conductive area filled with a thermally conductive dielectric material, which is confined in an area surrounded by said LED and said carrier substrate and is contacted with at least a third one of said filled through holes; and at least one fill channel within said carrier substrate, said fill channel contacting said thermally conductive area and filled with said thermally conductive dielectric material.