Patent ID: 6924221

Claim:
A method in dual damascene processing, for fabrication of trench and via openings, the method comprising: providing an insulating layer overlying a semiconductor substrate; providing a patterned metal wiring layer over said insulating layer; depositing a first passivating layer over said metal wiring layer; depositing a first low dielectric constant layer over said first passivating layer; depositing a second passivating layer over said first low dielectric constant layer; depositing a second low dielectric constant layer over said second passivating layer; forming via and trench openings in said first and second low dielectric constant layers; blanket depositing by plasma enhanced chemical vapor deposition, a SiN conformal layer over said via and trench openings; etching back of said SiN conformal layer forming a plasma enhanced SiN spacer at the bottom of the via opening and exposing a portion of the first passivating layer; providing patterned photoresist to expose the SiN spacer at the bottom of the via and expose a portion of the first passivating layer; removal of the SiN spacer at the bottom of the via, and the exposed portion of the first passivating layer, thus forming properly shaped trench and via openings in dual damascene.