Patent ID: 7989309

Claim:
A method of forming a graded trench for a shallow trench isolation region comprising: providing a semiconductor substrate with a substrate region; forming a pad oxide layer overlying the substrate region; forming an etch stop layer overlying the pad oxide layer; patterning a photoresist layer overlying the etch stop layer; etching a portion of the etch stop layer and a portion of the pad oxide layer using the patterned photoresist layer to expose a surface region of a portion of the substrate region; forming a trench within the portion of the substrate region, the trench having first sidewalls and a bottom and a first depth; forming a dielectric layer overlying at least the first trench sidewalls, the trench bottom, and mesa regions adjacent to the trench; removing a first portion of the dielectric layer from the trench bottom to expose a bottom substrate region while a second portion of the dielectric layer remaining on the first sidewalls of the trench; etching the exposed bottom substrate region to increase the depth of at least a portion of the trench to a second depth and to expose second sidewalls of the trench, the second portion of the dielectric layer remaining on the first sidewalls of the trench being a masking layer, removing the second portion of the dielectric layer from the trench to expose the first sidewalls and the second sidewalls; forming a second dielectric layer overlying the exposed first and second sidewalls, the trench bottom, and the mesa regions adjacent to the trench; removing a first portion of the second dielectric layer from the trench bottom to expose the substrate region with a second portion of the second dielectric layer remaining on the first and the second sidewalls of the trench; etching the substrate region to increase the depth of at least a portion of the trench to a third depth, and removing the second portion of the second dielectric layer from the trench.