Patent ID: 7573932

Claim:
A spread spectrum clock generator, comprising: a delay circuit to receive a fixed clock signal and to delay a delay time of the fixed clock signal by repetitively increasing from a minimum delay time to a maximum delay time and decreasing from the maximum delay time to the minimum delay time in response to a control code to generate a spread spectrum clock signal; a register circuit to store control codes and to receive an address signal to generate a control code corresponding to the address signal; and a control circuit receiving the fixed clock signal to vary and generate the address signal for the register circuit using the fixed clock signal, the control circuit comprising: a frequency divider to receive the fixed clock signal to generate a frequency-divided clock signal; and an address generator to generate the address signal in response to the frequency divided clock signal, wherein the address generator comprises: an overflow detection and shift register configured to shift the address signal in a forward direction when a forward shift control signal is generated, to shift the address signal in a backward direction when a backward shift control signal is generated to generate the address signal, to generate the address signal once more when one of (a) a most significant and (b) a least significant bit of the address signal is activated, and to generate an overflow detection signal when an overflow of the address signal is detected; and a forward and backward control signal generator configured to toggle the forward shift control signal and the backward shift control signal when the overflow detection signal is generated.