Patent ID: 8648339

Claim:
A semiconductor device, comprising: a plurality of first terminals and a plurality of second terminals; a first semiconductor chip that comprises a plurality of first pads connected respectively with the first terminals, a first test circuit and a first memory portion, the first semiconductor chip outputting first data of the first memory portion to the plurality of first terminals through the plurality of first pads during a normal operation, and the first test circuit generating a first test result in response to the first data during a test operation; and a second semiconductor chip that comprises a plurality of second pads connected respectively with the plurality of second terminals, a second test circuit, a third test circuit and a second memory portion, the second semiconductor chip outputting a plurality of second data of the second memory portion to the plurality of second data terminals through the plurality of second data pads during the normal operation, and the second test circuit generating a second test result in response to the second data, the third test circuit generating a third test result in response to the second test result and the first test result supplied from the first test circuit of the first semiconductor chip, and the third test result outputting to one of second terminals through a corresponding one of second data pads during the test operation.