Patent ID: 6909316

Claim:
A variable delay circuit comprising: a delay selection circuit comprising: a digital input device having a number (N+1) of pairs of complementary select outputs; and a digital-to-analog converter (DAC) having (N+1) pairs of inputs connected to the (N+1) pairs of complementary select outputs of the digital input device, the DAC further comprising outputs that provide control voltages V 1 and V 2 ; and a delay interpolation circuit having inputs that receive the control voltages V 1 and V 2 from the DAC, the delay interpolation circuit further comprising: a delay range limitation circuit having a differential waveform input that receives a differential waveform, the delay range limitation circuit having first and second differential output branches, the first differential output branch having a long time delay and the second differential output branch having a short time delay; and a delay mixing circuit having control inputs, differential inputs, and a differential output, the differential inputs connected to the first and second differential output branches, the control inputs configured to receive the control voltages V 1 and V 2 ; wherein the DAC further comprises: (N+1) binary weighted current source p-type MOSFETs; (N+1) complementary pairs of selection MOSFETs, each complementary pair of selection MOSFETs connected to a respective one of the (N+1) binary weighted current source p-type MOSFETs, each complementary pair of selection MOSFETs comprising a true bit MOSFET and a complementary bit MOSFET; a first control voltage terminal connected to the true bit MOSFETs of the complementary pairs of selection MOSFETs, the first control voltage terminal providing the control voltage V 1 ; and a second control voltage terminal connected to the complementary bit MOSFETs of the complementary pairs of selection MOSFETs, the second control voltage terminal providing the control voltage V 2 .