Patent ID: 7777536

Claim:
A synchronization circuit comprising: a first flip-flop circuit configured to hold an input signal which is asynchronous to a timing of a clock signal at the timing of the clock signal, and output an output signal; a second flip-flop circuit configured to hold the input signal at a timing of a signal of an opposite phase to the clock signal and output a signal; a comparing unit configured to compare the input signal and the output signal of the first flip-flop circuit and output a signal with a high or low level depending on whether the input signal and the output signal of the first flip-flop circuit have the same level; a selection unit configured to select one of the output signal of the first flip-flop circuit and the output signal of the second flip-flop circuit in response to the level of the signal outputted by the comparing unit; and a third flip-flop circuit configured to output the output signal selected by the selection unit.