Patent ID: 8255621

Claim:
A multiprocessor system, comprising: a first processor that executes a first program; a second processor that brings the first processor to a reset state and releases the first processor from the reset state, and executes a second program independently of the first processor; a read-only memory for storing the first program and the second program; a random access memory including a memory area in which the first program and the second program are expanded and stored; and an arbitration circuit that allows the first processor and the second processor to access the random access memory, and adjusts and gives a bus citizenship between the processors, wherein the random access memory includes a shared area which can be accessed by both of the processors, the shared area being used for interprocessor communication, wherein the second processor directly expands the program for the first processor stored in the read-only memory into the memory area in the random access memory, and performs validity check of the expanded program, and wherein the first processor is maintained in the reset state until the validity check of the program expanded by the second processor is completed, and, after the program is confirmed to have been expanded without problems, the first processor is released from the reset state by control of the second processor and starts executing the program expanded in the random access memory.