Patent ID: 7265638

Claim:
A ring oscillator circuit comprising: a ring of cascade-coupled delay stages controlled by a plurality of multiplexers and fed back by a feedback logic gate having an input terminal coupled to an output terminal of said ring oscillator circuit, said ring oscillator circuit receiving a control word and emitting on said output terminal a clock signal; a plurality of control blocks receiving respective bits of said control word and coupled to said delay stages of said ring, each control block comprising a bistable element capable of receiving, storing and sending a bit of said control word to a multiplexer coupled to a respective delay stage in stable operating conditions of said ring; a plurality of logic gates, each of said plurality of logic gates being associated with one of the control blocks; and a plurality of multiplexers, wherein each of the plurality of logic gates following a first of said plurality of logic gates is inserted between a respective multiplexer and a following delay stage in said ring, and coupled to an input terminal of a respective bistable element to stop transmission of a respective bit of said control word up to the switching of said bistable element and wherein said first logic gate is an OR gate having the first input terminal connected to the first input terminal of said bistable element, a second input terminal coupled to an output terminal of a feedback delay stage, and coupled in turn to an output terminal of said feedback logic gate, as well as an output terminal connected to the second input terminal of said first multiplexer of said plurality of multiplexers.