Patent ID: 8037386

Claim:
A test interface comprising: A. control circuitry having a gated mode select input, a clock input, and control outputs; B. a first shift register having a serial data input, control outputs, a serial data output, and a control input connected with the control outputs of the control circuitry; C. a second shift register having a serial data input connected with the serial data input of the first shift register, parallel data outputs, a serial data output, and control inputs connected with the control outputs of the control circuitry and the control outputs of the first shift register; D. a multiplexer having a first input connected with the serial data output of the first shift register, a second input connected with the serial data output of the second shift register, a control input connected with the control outputs of the control circuitry, and a serial data output; and E. a select output from one of the first shift register and the second shift register and separate from the control outputs of the first register connected to the second shift register and separate from the parallel data outputs of the second register.