Patent ID: 7080234

Claim:
A very long instruction word (VLIW) processing core comprising: a processing pipeline having N-number of processing paths for processing an instruction comprising N-number of P-bit instructions appended together to form a VLIW, said N-number of processing paths process said N-number of P-bit instructions in parallel on M-bit data words; and one or more register files having Q-number of general purpose registers, said Q-number of general purpose registers being M-bits wide; wherein a first one of said Q-number of general purpose registers in at least one of said one or more register files is a dedicated program counter register which stores a current program counter value; wherein a second one of said Q-number of general purpose registers in said at least one of said one or more register files is hardwired to a set value; and wherein said processing core is fabricated on a single silicon die.