Patent ID: 7755381

Claim:
An integrated circuit (“IC”) comprising: a voltage supply; a data source; a first data destination; a first tunable interconnect driver between the data source and the first data destination drawing a first peak supply current from the voltage supply when transmitting a datum from the data source to the first data destination; a first data path between the first tunable interconnect driver and the first data destination having a first nominal data transmittal time; a second data destination; a second tunable interconnect driver between the data source and the second data destination drawing a second peak supply current from the voltage supply when transmitting the datum from the data source to the second data destination; a second data path between the second tunable interconnect driver and the second data destination having a second nominal data transmittal time shorter than the first nominal data transmittal time; and an interconnect driver control circuit providing an interconnect driver control signal to the second tunable interconnect driver to de-tune the second tunable interconnect driver so as to reduce noise on the voltage supply when the datum is sent from the data source to the first data destination and to the second data destination.