Patent ID: 7119440

Claim:
A method of forming a multi-level semiconductor device wiring interconnect structure according to a low temperature process comprising the steps of: a) forming a dielectric insulating layer over a conductive portion; said conductive portion comprises silicide electrical contact areas comprising a CMOS transistor portion selected from the group consisting of a gate electrode and source and drain regions; b) forming a via opening in closed communication with the conductive portion; c) forming a first barrier layer to line the via opening; d) then forming a layer of AlCu to fill the via opening to form an AlCu via including a portion of said AlCu layer overlying the dielectric insulating layer; and, e) forming an AlCu interconnect line from said portion of said AlCu layer over the AlCu via, wherein a second barrier layer is optionally formed on said AlCu interconnect line; wherein process steps c) and d) are carried out at a temperature of less than about 400 degrees Centigrade.