Patent ID: 7664891

Claim:
A system on chip (SoC) integrated circuit, comprising: a plurality of computational blocks, each computational block having a port with an associated global port address; and a data transfer architecture interconnecting ports of the plurality of computational blocks for intra-chip data communications, the data transfer architecture comprising a plurality of communications tiles, the plurality of communications tiles being interconnected with each other, with certain ones of the communications tiles being interconnected to ports of the plurality of computational blocks; wherein each communications tile includes a plurality of communications ports, certain ones of the communications ports being connected to communications ports of adjacent communications tiles in the data transfer architecture; wherein the plurality of communications ports for each communications tile include initiator ports and target ports interconnected with each other through a data steering unit, the initiator ports receiving a data communication addressed for transmission toward the port of an addressed destination computational block which is assigned a destination computational block global port address; and wherein each communications tile includes a port mapper, the port mapper operating to map the destination computational block global port address from the data communication received at that communications tile to a communications tile local target port address for a selected one of the target ports included in that same communications tile from which the initiator port received data communication is to be output for communication through the data transfer architecture towards the port of the destination computational block; and an arbitration unit at each communications tile controlling the operation of the data steering unit in response to the communications tile local target port address mapped by the port mapper so as to interconnect the initiator port to the selected target port.