Patent ID: 7659170

Claim:
A method, comprising: forming a first trench isolation structure to define a first active semiconductor area in a silicon-containing semiconductor layer formed above a substrate; forming a second trench isolation structure to define a second active semiconductor area in said silicon-containing semiconductor layer; forming a first sub-layer of a gate insulation layer on said first semiconductor area and on said second active semiconductor area; exposing a portion of a sidewall of said first active semiconductor area, a non-exposed portion of said sidewall forming an interface with said first trench isolation structure; removing a portion of said first sub-layer in said first active semiconductor area; forming a second sub-layer of said gate insulation layer on said first and second active semiconductor areas, wherein exposing said portion of said sidewall of said first active semiconductor area is performed after forming said first sub-layer and prior to forming said second sub-layer; and forming a metal silicide for a circuit element in said silicon-containing semiconductor layer.