Patent ID: 8633582

Claim:
A chip package, comprising: a carrier substrate; at least one semiconductor chip disposed above the carrier substrate, wherein the semiconductor chip comprises a plurality of conductive pads; a plurality of first redistribution layers disposed on the semiconductor chip and electrically connected to the plurality of conductive pads; a single-layer insulating structure disposed on and in direct contact with the carrier substrate, covering the semiconductor chip, and crossing the plurality of first redistribution layers, wherein the single-layer insulating structure has a plurality of first openings exposing the plurality of first redistribution layers; a plurality of second redistribution layers disposed on the single-layer insulating structure and electrically connected to the plurality of first redistribution layers through the plurality of first openings; a first passivation layer disposed on the single-layer insulating structure and the plurality of second redistribution layers and having a plurality of second openings exposing the plurality of second redistribution layers; and a plurality of conductive bumps correspondingly disposed in the plurality of second openings and electrically connected to the plurality of second redistribution layers.