Patent ID: 8067959

Claim:
A programmable clock delay line compensated for process, voltage, and temperature in an integrated circuit, comprising: a delay-locked loop having a reference input, a feedback input, and a clock output, and a control output wherein the delay-locked loop feedback input is coupled to the delay-locked loop output; a phase-locked loop having a reference input, a feedback input, and an output, wherein the phase-locked loop output is coupled to the delay-locked loop reference input and the phase-locked loop feedback input; a reference clock coupled to the phase-locked loop reference input; first and second sources of programming data; and a signal delay line with a control input coupled to the delay-locked loop control output, wherein: the signal delay line either is coupled between the reference clock and the phase-locked loop reference input or is coupled between the phase-locked loop output and the phase-locked loop feedback input according to the first source of programming data and the delay of the signal delay line is determined according to the second source of programming data.