Patent ID: 8150019

Claim:
A method of hardware efficient communication interconnection comprising the steps of: accepting a first plurality of communication pathways, each having an individual connection locale; accepting a second plurality of communication pathways, each also having an individual connection locale; multiple alternative output switching between any two of said individual connection locales; and establishing a fully unconstrained interconnect between said any two of said individual connection locales; and further comprising the steps of: establishing a collective of superfluous capability side stage sub arrays capable of transmitting a communication; establishing a collective of balanced connectivity side stage sub arrays capable of transmitting a communication; establishing a collective of center stage sub arrays capable of transmitting a communication; and configuring at least one of said superfluous capability side stage sub arrays, said balanced connectivity side stage sub arrays, and said center stage sub arrays to communicate between at least one of said first plurality of communication pathways and another communication pathway; and wherein said step of establishing a collective of superfluous capability side stage sub arrays comprises the step of establishing a collective of superfluous capability outer side stage sub arrays.