Patent ID: 7650465

Claim:
A processor that implements load and store instructions, comprising: a cache that includes a plurality of datarams; a processor pipeline register that stores base address data bits and offset data bits; and a micro tag array, coupled to the cache and the processor pipeline register, wherein the micro tag array comprises: a base register configured to store base address data bits, an offset register configured to store offset data bits, a carry bit register configured to store a first carry bit, and a way selection register configured to store way selection data bits and wherein the micro tag array is configured to invalidate, upon a tagram write, an array entry whose way selection data bits correspond to an intended refill way of the cache, and if first selected base address data bits stored in the processor pipeline register match base address data bits stored in the base register of the micro tag array, and if first selected offset data bits stored in the processor pipeline register match offset data bits stored in the offset register of the micro tag array, and if a second carry bit formed by an addition of second selected base address data bits stored in the processor pipeline register and second selected offset data bits stored in the processor pipeline register match the first carry, the micro tag array outputs an enable signal that enables a first dataram of the cache specified by way selection data bits stored in the way selection register of the micro tag array.