Patent ID: 7664118

Claim:
A method for high precision clock recovery over a packet switched network, said method comprising the steps of: generating packets at a local unit carrying information to a remote unit using a local clock signal, wherein each generated packet carries a transmitted timestamp; generating a remote timestamp at said remote unit for each said generated packet; providing a minimum network delay estimation for filtering out network jitter, wherein said minimum network delay estimation is defined as a time delay in which a packet remains in the packet switched network, assuming that all transmission queues through which said packet passes through are empty; reconstructing a received clock signal based on a time difference between said transmitted timestamp and said remote timestamp; and providing a latency estimation for detecting minimum delay values, wherein each of said minimum delay values is said time difference between said transmitted timestamp and said remote timestamp over a time window, wherein said latency deviation estimation comprises the steps of: obtaining an array containing 2N last minimum delay values, wherein N is an integer number; applying two linear regression procedures on said array, wherein a first regression procedure is applied on N first minimum delay values and a second regression procedure is applied on N last minimum delay values; calculating middle height difference of each of said two regression procedures; and detecting a latency deviation occurrence by checking whether said middle height difference is continuously increased x times and then continuously decreased y times, wherein x and y are threshold values, wherein a latency deviation value is defined as a peak value received from said two regression procedures.