Patent ID: 8610196

Claim:
A memory, comprising: at least one SRAM cell including: a first inverter including a first P-channel transistor and a first N-channel transistor; a second inverter including a second P-channel transistor and a second N-channel transistor, the second inverter being cross-coupled to the first inverter; a third N-channel transistor including a source/drain and a gate, one of the source/drain of the third N-channel transistor being connected to an output node of the first inverter, the other one of the source/drain being connected to a first interconnect, the gate of the third N-channel transistor being connected to a second interconnect; and a fourth N-channel transistor including a source/drain and a gate, one of the source/drain of the fourth N-channel transistor being connected to an output node of the second inverter, the other one of the source/drain being connected to a third interconnect, the gate of the fourth N-channel transistor being connected to the second interconnect, each of the first and second P-channel transistors being formed on a first semiconductor region and including: a first insulating film formed on the first semiconductor region; a first floating gate formed on the first insulating film; a second insulating film formed on the first floating gate; a second floating gate formed on the second insulating film; a third insulating film formed on the second floating gate; and a first control gate formed on the third insulating film, each of the first and second N-channel transistors being formed on a second semiconductor region and including: a fourth insulating film formed on the second semiconductor region; a third floating gate formed on the fourth insulating film; a fifth insulating film formed on the third floating gate; a fourth floating gate formed on the fifth insulating film; a sixth insulating film formed on the fourth floating gate; and a second control gate formed on the sixth insulating film, and each of the third and fourth N-channel transistors being formed on the second semiconductor region and including: a seventh insulating film formed on the second semiconductor region; a fifth floating gate formed on the seventh insulating film; an eighth insulating film formed on the fifth floating gate; a sixth floating gate formed on the eighth insulating film; a ninth insulating film formed on the sixth floating gate; and a third control gate formed on the ninth insulating film.