Patent ID: 8723233

Claim:
An integrated circuit comprising: a substrate comprising a first layer bonded to a second layer, wherein the first layer comprises a first crystalline orientation and the second layer comprises a second crystalline orientation that is different from the first crystalline orientation, where the first layer is situated above a top surface of the second layer; a volume of material formed in a region of a surface of the first layer, wherein the volume of material extends through the first layer from the second layer up to the surface of the first layer, wherein the material has a crystalline orientation that substantially matches the crystalline orientation of the second layer; a first plurality of fins formed in areas of the surface of the first layer that are outside of a region of the surface of the first layer comprising the volume of material, wherein each of the first plurality of fins extends from the top surface of the second layer of the substrate; a second plurality of fins formed from the volume of material within the region of the surface of the first layer, wherein the first and second plurality of fins are parallel to each other, wherein each of the second plurality of fins extends from the top surface of the second layer of the substrate; a spacer formed around each fin in the first plurality of fins and second plurality of fins, wherein a bottom portion of the spacer contacts the top surface of the second layer; an oxidized base with exposed sidewalls formed under each fin in the first plurality of fins and the second plurality of fins, wherein the oxidized base is formed within the second layer; and an oxidized set of exposed regions between each fin in the first and second plurality of fins, the oxidized base and the oxidized set of exposed regions forming an isolation layer between and under each fin in the first plurality of fins and the second plurality of fins, wherein the oxidized base is thicker than the oxidized set of exposed regions.