Patent ID: 7827016

Claim:
A system comprising: a network; a plurality of computing devices, coupled to the network; and a circuit simulation block comprising: a system tearing block to identify each branch of a given resistance-capacitance-inductance (RCL) circuit network graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the graph, and the tree comprises no loops, divide the tree into at least a first subtree and a second subtree, wherein each the first and second subtrees comprises no loops, and identify links of the given RCL circuit network graph as at least one of a global link or a local link, wherein a global link forms a path from a branch of the first subtree to a branch of the second subtree, a global link forms a loop with branches of the first and second subtrees, the first subtree is formed by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a predefined count and there are branches in the tree which have not yet been assigned to a subtree, and the second subtree is formed by repeatedly adding branches of the tree, not already assigned to the first subtree, to the second subtree when a number of branches in the first subtree is less than the predefined count and there are branches in the tree which have not yet been assigned to a subtree, and the loop with the global link and branches of the first and second subtrees has a voltage drop of 0; and a subblock solver block to send the first subtree, without any global links, through the network to a first computing device of the plurality of computing devices for calculation and the second subtree, without any global links, through the network to a second computing device of the plurality of computing devices for calculation.