Patent ID: 6936892

Claim:
A semiconductor device comprising: a layer with low electrical resistance; a semiconductive substrate region on the layer with low electrical resistance, the semiconductive substrate region providing a current path when the semiconductor device is ON and being depleted when the semiconductor device is OFF, the semiconductive substrate region comprising regions of a first conductivity type and regions of a second conductivity type, and the regions of the first conductivity type and the regions of the second conductivity type being arranged alternately with each other; a first major surface above the surface of the semiconductive substrate region; a second major surface on the back surface of the layer with low electrical resistance, wherein a net impurity concentration distribution within at least one of the regions of the first conductivity type and the regions of the second conductivity type along a direction crossing the first major surface and the second major surface peaks approximately at the first major suface; and an electrical resistive region existing between the layer and the regions of the first conductivity type and the regions of the second conductivity type, the electrical resistive region being a different region from the layer and regions.