Patent ID: 7745344

Claim:
A method comprising: providing a substrate having a first defined area for formation of a non-volatile memory cell having a select gate that is laterally adjacent a control gate and having a second defined area that is electrically separated from the first defined area, the second defined area being for formation of a transistor having a gate electrode; providing a first layer of gate material overlying the substrate in both the first defined area and the second defined area; providing multiple adjoining planar sacrificial layers respectively containing overlying nitrogen, oxygen and nitrogen in both the first defined area and the second defined area and overlying the first layer of gate material; using the multiple adjoining planar sacrificial layers to form the select gate and the control gate in the first defined area wherein the nitrogen underlying the oxygen of the multiple adjoining planar sacrificial layers is not completely removed and the oxygen and overlying nitrogen are removed; after formation of the select gate and control gate, using the nitrogen layer of the adjoining planar sacrificial layers to pattern the gate electrode of the transistor in the second defined area; and completing formation of transistors in both the first defined area and the second defined area.