Patent ID: 8587367

Claim:
A voltage pumping circuit, for pumping an input voltage to generate an output voltage, comprising: a first voltage pumping path including a first number of pumping stages; a second voltage pumping path including a second number of pumping stages, wherein the second number is less than the first number; wherein only one of the first voltage pumping path and the second voltage pumping path is activated according to at least one path selecting signal to pump the input voltage to generate the output voltage; a first pumping stage; a second pumping stage; a third pumping stage; and a pre-charge circuit coupled to the second pumping stage; wherein the first pumping stage, the second pumping stage and the third pumping stage sequentially form the first voltage pumping path; where the pre-charge circuit, part of the second pumping stage and the third pumping stage sequentially form the second voltage pumping path; wherein the first pumping stage is not included in the second voltage pumping path; wherein at least one of the first pumping stage, the second pumping stage and the third pumping stage includes: a first switch, having a first terminal, a second terminal receiving the input voltage or output from a previous pumping stage, and having a control terminal; a second switch, having a first terminal, having a control terminal coupled to the first terminal of the first switch, and having a second terminal coupled to the second terminal of the first switch; a third switch, having a first terminal for outputting the output voltage or for outputting to the next pumping stage, and having a second terminal coupled to the first terminal of the second switch; a first capacitor, having a first terminal, and having a second terminal coupled to the first terminal of the second switch; a first inverter, having an output terminal coupled to the first terminal of the first capacitor; a second capacitor, having a first terminal coupled to the control terminal of the second switch, and having a second terminal; and a second inverter, for receiving the path selecting signal, having an output terminal coupled to the second terminal of the second capacitor.