Patent ID: 7910447

Claim:
A method of manufacturing a self aligned bipolar transistor comprising the steps of: forming an active region of the transistor; forming a silicon nitride sacrificial emitter above the active region of the transistor; depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter using a physical vapor deposition process; exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process; performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window; depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window; forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose an underlying base portion of the transistor.