Patent ID: 7023746

Claim:
A synchronous semiconductor memory device in which read and write operations are synchronized to an externally supplied clock signal, comprising: a memory cell array including a plurality of memory cells for storing data; a pair of read data bus lines; a read column selection gate for selectively connecting the pair of read data bus lines to the memory cell array to receive the data stored in the memory cells; a pair of write data bus lines; a write column selection gate for selectively connecting the pair of write data bus lines to the memory cell array to write data into the memory cells; a column address decoder including a column selection signal generator for generating a read column selection signal to control the read column selection gate and a write column selection signal to control the write column selection gate; a read data bus equalizer for equalizing the pair of read data bus lines to mutually identical potentials; a write data bus equalizer for equalizing the pair of write data bus lines to mutually identical potentials; a data bus equalization controller including an equalizing signal generator for generating a read equalization signal to control the read data bus equalizer, and a write equalization signal to control the write data bus equalizer; a read amplifier for amplifying the data on the pair of read data bus lines; a read amplifier controller for generating a read amplifier control signal to control the read amplifier; and a column control clock generator for generating a column control clock signal responsive to the externally supplied clock signal and the read amplifier control signal, and supplying the column control clock signal to the column address decoder and the data bus equalization controller.