Patent ID: 8018005

Claim:
A semiconductor structure, comprising: a first semiconductor region ( 110 a ) and a second semiconductor region ( 110 b ); a first gate dielectric region ( 114 a ) on the first semiconductor region ( 110 a ); a second gate dielectric region ( 114 b ) on the second semiconductor region ( 110 b ), wherein the second semiconductor region ( 110 b ) includes a first top surface shared by the second semiconductor region ( 110 b ) and the second gate dielectric region ( 114 b ), and wherein the first top surface of the second semiconductor region ( 110 b ) defines a reference direction ( 175 ) perpendicular to the first top surface of the second semiconductor region ( 110 b ) and pointing from inside the second semiconductor region ( 110 b ) toward the second gate dielectric region ( 114 b ); a shallow trench isolation (STI) region ( 112 ) disposed between the first semiconductor region ( 110 a ) and the second semiconductor region ( 110 b ), wherein a top surface of the STI region ( 112 ) is above the first top surface of the second semiconductor region ( 110 b ) in the reference direction ( 175 ); an electrically conductive layer ( 120 ) on the first gate dielectric region ( 114 a ); a first poly-silicon region ( 150 a ) on the electrically conductive layer ( 120 ); a second poly-silicon region ( 150 b ) on the second gate dielectric region ( 114 b ); a first hard mask region ( 160 a ) on the first poly-silicon region ( 150 a ); and a second hard mask region ( 160 b ) on the second poly-silicon region ( 150 b ), wherein the first poly-silicon region ( 150 a ) and the first hard mask region ( 160 a) are exposed to a surrounding ambient, wherein the second poly-silicon region ( 150 b ) and the second hard mask region ( 160 b ) are exposed to the surrounding ambient, wherein the entire first poly-silicon region ( 150 a ) overlaps the electrically conductive layer ( 120 ) in the reference direction ( 175 ), and wherein the second poly-silicon region ( 150 b ) does not overlap the electrically conductive layer ( 120 ) in the reference direction ( 175 ).