Patent ID: 7293120

Claim:
A DMA module, comprising: an address generator that implements an access to one of a plurality of first addressable locations each uniquely associated with different DMA processes, where each of the first addressable memory locations is within an addressable memory connected to the address generator via a bus, where the address generator comprises a register that contains an address value indicative of a starting address of a DMA vector table located in the addressable memory, where each of the plurality of first addressable locations located within the DMA vector table includes (i) a uniquely associated DMA block starting address and (ii) a count value indicative of the length of the DMA block from the uniquely associated DMA block starting address; and means for receiving a DMA request, for determining the originating DMA process associated with the DMA request and for providing an originating DMA process signal indicative thereof; where the address generator receives the originating DMA process signal and determines which of the plurality of first addressable locations is associated with the originating DMA process, and initiates DMA access to the DMA block starting address associated with the first address location associated with the originating DMA process.