Patent ID: 8332794

Claim:
A method for producing an integrated circuit using an electronic design automation (EDA) system, comprising: providing a system design in a high level language description; performing a logic synthesis using an automated logic synthesis tool to produce a technology independent model and netlist from the high level language description; performing a technology mapping using an automated technology mapping tool to produce a netlist of circuits formed as logic transistor units (LTUs) to replace the technology independent model and netlist; using an automated placement tool, placing the LTUs in an array of rows and columns; using an automated routing tool, routing the LTUs to form a physical model of the netlist; using an automated placement tool, performing an LTU placement function by forming a pattern of a first level of metallization pattern on basic transistor units (BTUs) arranged to form the LTUs, the BTUs being transistor cells having conductors running in a first direction and gate conductors running in the first direction and having source and drain regions and contacts to couple the gate conductors, conductors, and source and drain regions to the first level of metallization pattern; using an automated routing tool, performing an LTU routing function by forming a pattern of a second level of metallization pattern on the BTUs, the second level of metallization pattern coupling portions of the first level of metallization pattern to form circuitry; providing a semiconductor substrate with the BTUs disposed thereupon; and forming at least one first level of metallization and one second level of metallization to complete the integrated circuit.