Patent ID: 7271788

Claim:
An interface circuit for processing an input signal comprising: a phase locked loop (PLL) circuit adapted to generate a plurality of phased signals from a synchronizing signal that is associated with the input signal, wherein the PLL is arranged to provide each phased signal of the plurality of phased signals on at least one corresponding separate signal line of a plurality of signal lines; a phase adjuster including: a first phase selector for selecting a first one of the phased signals; a second phase selector for selecting a second one of the phased signals; and a phase mixer for multiplying the first selected phased signal with a first weight, multiplying the second selected phased signal with a second weight, and adding together the first and the second multiplied phased signals to derive an adjustable delay signal, wherein the first selected phased signal, the second selected phased signal, and at least one selected phase information signal are received into the phase mixer, wherein at least one simulated phase signal is selected as an adjustment to the synchronizing signal.