Patent ID: 7986561

Claim:
A semiconductor memory device comprising: a plurality of memory cells, each memory cell including a selection transistor and a memory transistor, the memory transistor having a source and having a control gate which is coupled to the selection transistor; a plurality of selection gate lines coupled to a gate of the selection transistor; a plurality of control gate lines coupled to the control gate of the memory transistor; a plurality of source lines coupled to the source of the memory transistor; a plurality of bit lines that intersect the plurality of selection gate lines and are coupled to the selection transistor; a selection gate line driver circuit that drives the plurality of selection gate lines; a control gate line driver circuit that drives the plurality of control gate lines; and a source line driver circuit that drives the plurality of source lines, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprise a second transistor including a second gate insulation film and, respectively, drive the control gate line and the source line with a boost voltage higher than the first driving voltage.