Patent ID: 7940588

Claim:
A chip testing circuit, comprising: a plurality of write units coupled to at least one internal circuit of the chip and divided into a first write group and a second write group; a first interface circuit coupled to the plurality of write units for receiving a test signal and transmitting the test signal to the plurality of write units to input the test signal into the internal circuit of the chip; a first switch disposed between the first write group and the second write group for selectively coupling the first write group and the second write group; a plurality of read units coupled to at least one internal circuit of the chip for receiving cell signals from the circuit of the chip wherein the plurality of read units are divided into a first group of read units and a second group of read units; a first compressing circuit coupled to the plurality of read units of the first group of read units for compressing the cell signals outputted from the plurality of read units to generate a first compressing signal; a second compressing circuit coupled to the plurality of read units of the second group of read units for compressing the cell signals outputted from the plurality of read units to generate a second compressing signal; a second interface circuit for generating a first determining signal according to the cell signals outputted from the first group of read units and the first compressing signal, or for generating a second determining signal according to the cell signals outputted from the second group of read units and the second compressing signal; a first multiplexer disposed among the second interface circuit, the first group of read units, and the second group of read units for selectively coupling the second interface circuit to the first group of read units or the second group of read units; and a second multiplexer disposed among the second interface circuit, the first compressing circuit, and the second compressing circuit for selectively coupling the second interface circuit to the first compressing circuit or the second compressing circuit.