Patent ID: 8422269

Claim:
A semiconductor memory device, comprising: a memory cell array having memory cells disposed at intersections of a plurality of first lines and a plurality of second lines, each of the memory cells being includes by a rectifier and a variable resistor connected in series; a control circuit configured to apply a first voltage to selected one of the first lines and to apply a second voltage having a voltage value smaller than that of the first voltage to selected one of the second lines, such that a certain potential difference is applied across the memory cell disposed at the intersection of the selected one of the first lines and the selected one of the second lines; and a current limiting circuit configured to set a compliance current defining an upper limit of a cell current flowing in the memory cell, and to perform a control such that the cell current flowing in the memory cell does not exceed the compliance current, the current limiting circuit comprising: a current generating circuit configured to generate a first current having a current value equal to a current value of the cell current at a certain timing multiplied by a certain constant; and a first current mirror circuit configured to mirror the first current to a current path supplying the first voltage to the first lines.