Patent ID: 6975545

Claim:
A method for writing a memory cell comprising: providing a memory cell comprising an N-type well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first gate formed on the first stacked dielectric layer, a second stacked dielectric layer formed on the N-type well and between a second doped region and a third doped region from among the three P-type doped regions, a second gate formed on the second stacked dielectric layer; applying a common voltage to the N-type well, the first doped region and the second gate; applying a voltage less than the common voltage to the first gate in order to erase charges stored in the first stacked dielectric layer; applying a first voltage to the first gate and a second voltage larger than the first voltage to the second gate, in order to conduct respectively P-type channels between the first doped region and the second doped region and the second doped region and the third doped region; applying a voltage larger than the second voltage to the N-type well and the first doped region; and applying a voltage less than the second voltage to the third doped region in order to inject channel hot hole induced hot electrons into the second stacked dielectric layer formed on the N-type well and between the second doped region and the third doped region.