Patent ID: 7665002

Claim:
An integrated circuit, comprising: a plurality of logic cores; a debug controller coupled to each of the plurality of logic cores; a test access port coupled to the debug controller and configured to provide an external interface to the debug controller; and a core mask register configured to store a value indicating a selected one or more of the plurality of logic cores, wherein the core mask register is writable via the test access port; wherein the debug controller is configured to switch the selected one or more logic cores from a normal mode of execution to a debug mode; wherein, while in the normal execution mode, each of the logic cores is configured to execute program instructions; wherein, while in the debug mode, each of the logic cores is configured to perform debug operations controlled by the debug controller according to commands received via the test access port; and wherein each of the logic cores is capable of operating in the normal execution mode simultaneously with at least another one of the logic cores operating in the debug mode.