Patent ID: 8395428

Claim:
A frequency domain digital phase locked loop (DPLL), comprising: a digitally controlled oscillator (DCO) operative to generate a clock signal having a frequency responsive to an applied digital control input; a delay modulator circuit operative to receive a reference frequency clock signal, and to randomize the timing of state transition edges in the reference frequency clock signal, generating a randomized reference frequency clock signal having the same long-term frequency; a sampler circuit operative to sample the randomized reference frequency clock signal at the DCO clock signal frequency; a period determining circuit operative to determine the period of the randomized reference frequency clock signal; a comparator operative to compare the determined period of the randomized reference frequency clock signal with a frequency control word representing the period of a desired frequency, and to generate a frequency error signal; and a loop filter operative to integrate the frequency error signal and to generate a digital control input operative to drive the DCO to generate an output signal at the desired frequency.