Patent ID: 8020054

Claim:
A test apparatus that tests a plurality of memories under test storing data in block-units, comprising: an address generating section that is provided in common to the plurality of memories under test, and that sequentially generates addresses to be tested in the memories under test; a plurality of buffer memories that are provided to correspond respectively to the plurality of memories under test, and that each store addresses to be independently supplied to the corresponding memory under test; a reading section that outputs, to each of the plurality of memories under test, a read command for reading block data stored at each address generated by the address generating section; a plurality of comparing sections that are provided to correspond respectively to the plurality of memories under test, and that each compare (i) the block data output by the corresponding memory under test in response to the read command to (ii) an expected value of this block data, for each address generated by the address generating section; a plurality of bad block storage control sections that are provided to correspond respectively to the plurality of memories under test, and that each sequentially store, in the buffer memory provided to the corresponding memory under test and in response to the comparing section detecting a discrepancy in the comparison, the address generated by the address generating section for reading the block data; a disabling section that outputs, in parallel to the plurality of memories under test, a disable command for writing disable data that disables blocks corresponding to the addressees stored in the buffer memories, these addresses being included in the disable command as individual addresses; and a buffer section that buffers addresses generated by the address generating section and sequentially updates the buffered addresses each time the address generated by the address generating section changes, wherein the address generating section supplies the buffer section with an address corresponding to a read command from when the read command is output to when a subsequent read command is output, and each bad block storage control section, in response to the corresponding comparing section detecting a discrepancy in the comparison, reads the address from the buffer section and sequentially stores this address in the buffer memory provided to the corresponding memory under test.