Patent ID: 7477537

Claim:
A semiconductor integrated circuit provided with a SRAM comprising: a plurality of word lines; a plurality of complimentary bit lines; a plurality of static memory cells for being allocated in correspondence with the plurality of word lines and the plurality of complimentary bit lines; a plurality of memory cell voltage lines for supplying an operational voltage to each of the plurality of memory cells connected to the plurality of complimentary bit lines each; a plurality of power supply means for supplying the operational voltage to the plurality of memory cell voltage lines each; a pre-charge unit for supplying a pre-charge voltage corresponding to the operation voltage to the complimentary bit lines, and a word line selection means for selecting one of the plurality of word lines, wherein the memory cell voltage lines have coupling capacitances to thereby transmit a write signal of corresponding complimentary bit lines, wherein each of the power supply means is constructed by a resistive means, wherein the operational voltage is a positive potential, wherein the memory cells include a storage means and selection MOSFETs, wherein the storage means is cross-coupled inputs and outputs of two CMOS inverters, wherein the selection MOSFETs is arrayed between the storage means and the complimentary bit lines, and has a gate for coupling to the word line, wherein the resistive means includes a P-channel MOSFET having a gate supplied a ground voltage, and wherein the word line selection means includes: first and second MOSFETs of a first conductive type, connected in series between the operational voltage and an output terminal; and third and fourth MOSFETs of a second conductive type, connected in parallel between the ground voltage and the output terminal.