Patent ID: 8248136

Claim:
An integrated circuit having a configurable delay element connected to generate an output signal (e.g., Z) as a delayed version of an input signal (e.g., A), the delay element comprising: a first stage comprising: a first delay chain (e.g., 210 ) having N buffers connected to receive the input signal and generate N differently delayed versions of the input signal; and an (N×1) first mux (e.g., 220 ) connected to receive the N versions of the input signal and output one of the N versions of the input signal as a first-stage output signal; and a second stage comprising: a second delay chain (e.g., 230 ) having N(M−1) buffers connected to receive the first-stage output signal and organized into (M−1) sub-chains (e.g., 232 _ 1 to 232 _ 3 ) to generate M differently delayed versions of the first-stage output signal; and an (M×1) second mux (e.g., 240 ) connected to receive the M versions of the first-stage output signal and output one of the M versions of the first-stage output signal as a second-stage output signal.