Patent ID: 7895005

Claim:
A method, in an integrated circuit device, for determining a duty cycle elan input signal, comprising: receiving the input signal in a duty cycle measurement circuit having a plurality of dividers, wherein the input signal is received as an input to a plurality of pulse shaper elements, wherein each pulse shaper element delays a poise of the input signal by a predetermined delay amount τ, wherein the plurality of pulse shaper elements comprises a first input signal path and a second input signal path; determining if one or more of the plurality of dividers fail; determining a relationship of a duty cycle of the input signal to a 50% duty cycle based on the determined one or more of the plurality of dividers that fail; and calculating the duly cycle of the input signal based on the determined relationship and an index of the one or mere of the plurality of dividers that fail, wherein calculating the duty cycle of the input signal based on the determined relationship and the index of the one or more of the plurality of dividers that fail comprises either: calculating the duty cycle of the input signal using the following equation if the relationship of the duty cycle of the input signal to a 50% duty cycle is determined to be greater than the 50% duty cycle: Duty Cycle (in %)=50%*( n+i )/( n ) where n is a failure index for a divider in the first input path for a 50% duty cycle input signal, and n+i is the first index: or calculating the duty cycle of the input signal using the following equation if the relationship of the duty cycle of the input signal to a 50% duty cycle is determined to be less than the 50% duty cycle; Duty Cycle (in %)=50%*( n′−i )/( n ′) where n′ is a failure index for a divider in the second input path for a 50% duty cycle input signal, and n′−i is the second index.