Patent ID: 8315272

Claim:
A multilane to single lane digital interface translator, comprising: multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard using a coding scheme; an auxiliary channel input configured to receive an auxiliary data channel; and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard; wherein the multilane to single lane digital interface translator is configured to encode the received data to produce code groups, where the same type of code group is on each lane at any given time, and the type of the code group is determined by the coding scheme used to encode the received data; wherein the multilane to single late digital interface translator is configured to interleave the code groups by mapping the code groups to packets, where each packet includes a specific type of code group; wherein the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate; and wherein the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard.