Patent ID: 7767478

Claim:
A method for manufacturing a thin film transistor array (TFT) panel, comprising: forming a gate line on an insulating substrate, the gate line having a first layer including Al, a second layer including Cu and is thicker than the first layer, and a gate electrode; sequentially depositing a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate line; patterning the semiconductor layer and the ohmic contact layer; forming a drain electrode and a data line having a source electrode on the gate insulating layer and the ohmic contact layer, the drain electrode facing the source electrode with a gap formed therebetween; forming a passivation layer having a contact hole that exposes the drain electrode, the passivation layer being formed on the data line and the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode being coupled with the drain electrode through the contact hole, wherein the second layer is formed to be more than four times thicker than the first layer.