Patent ID: 8495122

Claim:
An integrated circuit comprising: a plurality of configurable blocks; configurable interconnect resources programmably interconnecting the plurality of configurable blocks; a dedicated signal line that is non-programmable; a plurality of configurable digital signal processing (DSP) elements each having an adder/subtractor circuit, the plurality of DSP elements including a first DSP element and a second DSP element, the second DSP element including: a product generator having an output port; an element output port; a register coupled between an output of the adder/subtractor circuit and the element output port; and multiplexing circuitry having: a feedback port connected to the element output port; a cascade input port connected to a first end of the dedicated signal line, wherein a second end of the dedicated signal line is connected to an element output port of the first DSP element; a product generator port; a multiplexing-circuitry output port coupled to the adder/subtractor circuit of the second DSP element; and a select port receiving mode control signals; wherein the multiplexing circuitry connects at least one of the feedback port and the cascade input port to the multiplexing-circuitry output port in response to the mode control signals, and wherein the multiplexing circuitry comprises a first multiplexer which enables the coupling of either the product generator port or the feedback port to a first addend port of the adder/subtractor circuit and a second multiplexer which enables the coupling of either the feedback port and the cascade input port to a second addend port of the adder/subtractor circuit, and wherein data output by the adder/subtractor circuit and stored in the register may be coupled to the first addend port of the adder/subtractor circuit and the second addend port of the adder/subtractor circuit.