Patent ID: 7934185

Claim:
A method of testing a design in a high level modeling system of unidirectional elements, comprising: identifying a bus-block; representing the bus-block within the design and associated with a bus; and interfacing a tap to the bus in the design via the bus-block, wherein the representing and interfacing comprise: representing the tap with unidirectional input and output tap lines coupled to the bus-block, wherein unidirectional input and output tap lines simulate a bi-directional tap line; substituting, using a processor, for a first port of the bus within the design a first representation of unidirectional, oppositely directed, input and output lines simulating a bi-directional implementation of the first port coupled to the bus-block; and substituting for a second port of the bus within the design a second representation of unidirectional, oppositely directed, input and output lines simulating a bi-directional implementation of the second port coupled to the bus-block, wherein the tap is independent of the first port and the second port coupled to the bus-block.