Patent ID: 8072198

Claim:
A voltage regulator, in which an output terminal is connected to a load capacitor, and a voltage detection circuit section for detecting an overshoot at the output terminal controls a control transistor connected to the output terminal so as to suppress the overshoot at the output terminal, wherein the voltage detection circuit section comprises: a first transistor for detecting the overshoot at the output terminal; a second transistor having a gate and a drain which are connected to a drain of the first transistor, and a source connected to the output terminal; a third transistor having a gate connected to the gate of the second transistor, and a source connected to the output terminal; and a fourth transistor having a drain connected to a drain of the third transistor, and a gate connected to a reference voltage terminal, the fourth transistor having a threshold lower than a threshold of the first transistor, and wherein the overshoot at the output terminal is detected by a parasitic capacitance between the drain and the source of the third transistor before the first transistor detects the overshoot at the output terminal.