Patent ID: 7336113

Claim:
A pulse width controller circuit for generating a periodic digital output signal, the controller circuit comprising: a voltage controlled current source; a timing capacitor connected to said current source; a reset switch connected in parallel with said timing capacitor; said reset switch being adaptable for receiving a master clock signal; a first invert gate having an input connected to said current source and said timing capacitor; a low pass filter connected to an output of said first invert gate; a reference pulse generator adaptable for receiving the master clock signal and generating a reference pulse; and an integrator having an inverting input connected to said low pass filter, a non-inverting input connected to said reference pulse generator so as to receive said reference pulse, said non-inverting input being adaptable for connection to a source of a ratio control voltage, and an output connected to said voltage controlled current source; said circuit being adaptable for producing an output signal from said first invert gate having a pulse width in linear proportion to said ratio control voltage.