Patent ID: 8108647

Claim:
A memory apparatus for a computer system, comprising: a memory module daisy chain containing a plurality of memory modules arranged sequentially; a plurality of primary communications links, each primary communications link providing bi-directional communication between a respective pair of devices, wherein a first primary communications link is configured to provide communication between a memory accessing device and a first memory module in said memory module daisy chain, said first memory module being located at the first sequential position in said memory module daisy chain, and each subsequent primary communication link is configured to provide communication between a respective memory module in said memory module daisy chain and a next succeeding memory module in said memory module daisy chain; a plurality of alternate communications links, each alternate communications link providing bi-directional communication between a respective pair of devices, wherein a first alternate communications link is configured to provide communication between a memory accessing device and a memory module in said memory module daisy chain other than said first memory module, and each subsequent alternate communications link is configured to provide communication between a respective memory module in said memory module daisy chain and a memory module in said memory module daisy chain other than the memory module next succeeding the respective memory module; said plurality of primary and alternate communications links being configured to provide, in the event of failure of any single module of said memory module daisy chain, at least one respective path which does not traverse the failing module from a memory access device to each module of said memory module daisy chain other than the failing module.