Patent ID: 8836692

Claim:
An image display device comprising: a display panel configured to selectively display a 2D image and a 3D image, the display panel including a plurality of pixels; a patterned retarder configured to divide light from the display panel into first polarized light and second polarized light; and a control voltage generation circuit configured to generate a 2D control voltage at an off-level and generate a 3D control voltage alternately having a slight-on level and the off-level every predetermined period of time, the slight-on level being higher than the off-level and being lower than a full-on level, wherein each of the plurality of pixels includes: a main display unit including a first pixel electrode connected to a data line through a first switch and a first common electrode which is opposite to the first pixel electrode and is connected to a common line; and a subsidiary display unit including a second pixel electrode connected to the data line through a second switch, a second common electrode which is opposite to the second pixel electrode and is connected to the common line, and a discharge control switch which selectively connects the second pixel electrode to the common line in response to the 2D control voltage and the 3D control voltage, and wherein the discharge control switch is continuously held in an off-state based on the 2D control voltage in a 2D mode for a display of the 2D image and is alternately held in a slight-on state and the off-state based on the 3D control voltage in a 3D mode for a display of the 3D image, wherein a scan pulse for switching the first and second switches swings between a gate high voltage with the full-on level and a gate low voltage with the off-level, wherein the slight-on level is higher than the gate low voltage of the scan pulse and is lower than the full-on level of the scan pulse, and wherein when the discharge control switch is held in the slight-on state by the 3D control voltage having the slight-on level, the discharge control switch partially opens and partially allows a current path between the second pixel electrode and the common line, and when the discharge control switch is held in the off-state by the 3D control voltage having the off-level, the discharge control switch completely closes and cuts off the current path between the second pixel electrode and the common line.