Patent ID: 7112847

Claim:
A semiconductor device comprising: an insulator; a semiconductor fin formed on the insulator; a source region adjacent a first end of the fin formed on the insulator; a drain region adjacent a second end of the fin formed on the insulator; a first sidewall spacer formed adjacent a first side of the fin, the first sidewall spacer having a substantially triangular shaped cross-section; a second sidewall spacer formed adjacent a second side of the fin, the second sidewall spacer having a substantially triangular shaped cross-section; and a gate formed over the fin and the first and second sidewall spacers, and in contact with the first and second sidewall spacers, in a channel region of the semiconductor device, wherein the first and second sidewall spacers are formed to a width ranging from about 150 Å to about 1000 Å and wherein the first and second sidewall spacers cause a topology of the gate to smoothly transition over the fin and the first and second sidewall spacers to reduce micromasking effects during etching of the gate.