Patent ID: 7257808

Claim:
A method comprising: identifying a plurality of fork subgraph structures within a graph structure constructed for a plurality of source code instructions; identifying, prior to register allocation, a plurality of unifiable variables within each fork subgraph structure of said plurality of fork subgraph structures, which are not simultaneously used in said plurality of source code instructions; constructing a dependence graph of said plurality of source code instructions; using said dependence graph to identify at least two unifiable instructions of said plurality of source code instructions, within said plurality of fork subgraph structures, said at least two unifiable instructions containing at least one unifiable variable of said plurality of unifiable variables; unifying each unifiable variable within said at least two unifiable instructions to generate a corresponding unified instruction for each of the at least two unifiable instructions; and transferring said at least two unifiable instructions of said plurality of source code instructions from respective tines of corresponding fork subgraph structures of said plurality of fork subgraph structures to store a matching unified instruction within a handle corresponding to said fork subgraph structures, if the corresponding unified instructions of said at least two unifiable instructions match.