Patent ID: 7701997

Claim:
A frequency synthesizer, comprising: a table adapted to store a plurality of oscillator tuning words (OTW); means for splitting said OTW into an integer portion and a fractional portion; an all digital phase locked loop (ADPLL), comprising: a digitally controlled oscillator (DCO) coupled to said table, said DCO operative to generate local oscillator (LO) signals whose frequency is determined in accordance with said integer portion of said OTW outputted from said table; a feedback circuit coupled to the output of said DCO, said feedback circuit operative to calibrate the frequency output of said DCO; and calibration means having an output coupled to an input of said table, having another output coupled to an input of said feedback circuit, and having an input coupled to an output of said feedback circuit, said calibration means operative to configure open and closed modes of operation of said frequency synthesizer.