Patent ID: 7892945

Claim:
A method of forming a semiconductor structure comprising: providing a plurality of patterned hard masks atop a patterned material stack including alternating layers of semiconductor material and sacrificial material, wherein the bottommost layer of the patterned material stack is a top semiconductor layer of a semiconductor substrate; forming at least one dummy gate over a central portion of each of said plurality of patterned hard masks; forming a sacrificial material layer abutting said at least one dummy gate; removing the at least one dummy gate to form at least one trench in the sacrificial material layer, each trench centered over the central portion of the plurality of patterned hard masks, that distinguishes a fin region from source and drain regions; etching a plurality of fins within said at least one trench in the patterned material stack using the plurality of patterned hard masks as an etch mask; removing the plurality of patterned hard masks and each layer of sacrificial material within said at least one trench to form a plurality of vertically stacked and vertically spaced apart semiconductor nanowires within said at least one trench; and filling the at least one trench with at least a gate region.