Patent ID: 7007124

Claim:
A data processing system, comprising: at least one function module connected to a single system bus; a data transfer controller which outputs a first bus use permission request signal based on a data transfer request signal output from the at least one function module; a central processing unit connected to the system bus which outputs a second bus use permission request signal; an arbitration controller for determining, based on the first and second bus use permission request signals, which of the data transfer controller and the central processing unit should obtain a permission to use the system bus; a section for setting a first data amount which can be continuously transferred by the at least one function module; a section for suspending an output of the first bus use permission request signal to the arbitration controller for at least one clock cycle after a data transfer by the at least one function module is completed; and a section for giving the permission to use the system bus to one of the data transfer controller and the central processing unit in such a manner that the data transfer controller has a priority over the central processing unit during a period when the first bus use permission request signal is being issued.