Patent ID: 7476939

Claim:
An integrated circuit comprising: a semiconductor memory cell comprising an electrically floating body transistor comprising: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region and separated therefrom by a gate dielectric; and wherein the memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing carriers from the body region through the gate; and control circuitry, coupled to the memory cell, to generate control signals, including first control signals, to program one of a plurality of data states into the memory cell, wherein, in response to the first control signals applied to the memory cell, the electrically floating body transistor provides the second charge in the body region by removing carriers from the body region through the gate.