Patent ID: 8190825

Claim:
A processor connected to a memory unit, the processor comprising: a first processing unit; a second processing unit; and a common cache memory control unit that controls a common cache memory shared by the first and second processing units, wherein the first processing unit has a first cache memory and issues a prefetch request to selected one of the common cache memory and the memory unit to read the data into the first cache memory beforehand, the second processing unit has a second cache memory and issues a prefetch request to selected one of the common cache memory and the memory unit to read the data into the first cache memory beforehand, and the common cache memory control unit includes a prefetch processing unit that processes the prefetch request to the common cache memory, a first prefetch memory unit that stores only the prefetch request from the first processing unit and issues the prefetch request from the first processing unit to the prefetch processing unit, a second prefetch memory unit that stores only the prefetch request from the second processing unit and issues the prefetch request from the second processing unit to the prefetch processing unit, and a common prefetch memory unit which, when the prefetch request issued from selected one of the first and second prefetch memory units to the prefetch processing unit cannot be completed, stores the uncompleted prefetch request in an entry and issues the uncompleted prefetch request to the prefetch processing unit.