Patent ID: 8053306

Claim:
A method comprising: providing an implanted substrate including an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region; forming a mask over the NMOS region; epitaxially growing a layer including silicon and doping or implanting the layer including silicon to form a doped band engineered p-type field effect transistor (PFET) threshold voltage (Vt) work function tuning layer over the PMOS region only; removing the mask to expose the NMOS region of the implanted substrate; forming a high dielectric constant layer over the NMOS region of the implanted substrate and the PFET Vt work function tuning layer; forming an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; forming a metal layer over the NFET Vt work function tuning layer; and patterning a first gate over the NMOS region and a second gate over the PMOS region, the second gate including the doped band engineered PFET Vt work function tuning layer directly over the PMOS region, the high dielectric constant layer directly over the doped band engineered PFET Vt work function tuning layer, and the NFET Vt work function tuning layer directly over the high dielectric constant layer.