Patent ID: 8659970

Claim:
An apparatus, comprising: a first set of transistors including a first transistor and a second transistor, a gate of the first transistor to couple to a first signal and a gate of the second transistor to couple to a second signal, the first signal indicating whether a first supply voltage for a first circuit of a memory device reaches a first threshold voltage to power on the first circuit and the second signal indicating whether a second supply voltage for a second circuit of the memory device reaches a second threshold voltage to power on the second circuit; a second set of transistors including a third transistor and a fourth transistor, a gate of the third transistor to couple to a first inverted version of the first signal and a gate of the fourth transistor to couple to a second inverted version of the second signal, an outcome signal of the second set of transistors indicating a power-on state of the memory device responsive to power states of the first and second signals; and a pull-up path including a fifth transistor and a sixth transistor, a gate of the fifth transistor coupled to at least one of the second set of transistors and a gate of the sixth transistor coupled to at least one of the first set of transistors.