Patent ID: 7526746

Claim:
A method of automatically optimizing an initial geometrical layout of an integrated circuit design according to one or more optimization requirements, the method comprising: selecting one or more portions of the initial geometrical layout for geotopological optimization; constructing a geotopological encoding graph of each of the portions that encodes unmodifiable nets of the initial geometrical layout geometrically and encodes modifiable nets of the initial geometrical layout topologically; generating a geotopological layout of each of the portions that represents the unmodifiable nets with geometrical wiring paths and represents the modifiable nets with topological wiring paths; modifying the geotopological layout of each of the portions in accordance with the optimization requirements; transforming the modified geotopological layout of each of the portions to generate an intermediate geometrical layout of each of the portions; and combining the intermediate geometrical layout of each of the portions with unselected portions of the initial geometrical layout to provide an optimized geometrical layout of the integrated circuit design.