Patent ID: 7496734

Claim:
A data processor wherein comprising: a register stack comprising a plurality of physical registers operable to store operands required by instructions executed by the data processor, wherein the plurality of physical registers appear as a plurality of architectural registers to the instructions; an instruction execution pipeline comprising a plurality of processing stages, each of the processing stages operable to perform one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and a first mapping register associated with a first one of the processing stages and a second mapping register associated with a second one of the processing stages, wherein the first mapping register is operable to store first mapping data used to determine a first physical register associated with a first architectural register accessed by a first instruction being processed in the first processing stage, wherein the first mapping register is operable to transfer the mapping data stored therein to the second mapping register when the pending instruction is transferred from the first processing stage to the second processing stage; and wherein the second mapping register is operable to store second mapping data used to determine a second physical register associated with a second architectural register accessed by a second instruction being processed in the second processing stage.