Patent ID: 7861058

Claim:
A memory device comprising: a memory array, wherein the memory array is organized into logical units, wherein each logical unit is associated with a sideband area and wherein each logical unit can be partially written into, whereby multiple write operations can be performed to each logical unit before the logic unit is full; and a controller in communication with the memory array, wherein the controller is operative to: (a) receive a request from a host device in communication with the memory device to write data to a first address in the memory array; (b) write the data to a second address instead of the first address; (c) update a file system structure in the memory array to indicate that the second address is no longer free; and (d) write either the second address or an address to a remap table in a sideband area of the first address; wherein the controller is further operative to write ECC data in a sideband area for a logical unit when a last write operation is made to the logical unit.