Patent ID: 7650453

Claim:
An information processing apparatus comprising: multiple information processing units; at least one shared resource accessed by said multiple information processing units; multiple bus interfaces connecting said multiple information processing units and said shared resource to a bus; and an arbiter arbitrating multiple access requests issued by said multiple information processing units, wherein the at least one shared resource is connected to multiple bus interfaces via said arbiter and each of said bus interfaces has a read buffer temporarily holding read data to be returned in response to the access request from at least one information processing unit of said multiple information processing units and a write buffer temporarily holding write data received from at least one information processing unit of said multiple information processing units, wherein when one bus interface of said multiple bus interfaces receives the access request from said at least one information processing unit, said one bus interface compares an address of an access destination for said access request and an address of an access destination corresponding to data previously held in said read buffer and in said write buffer; and if the access request is the access request with respect to the same address as the address of the access destination corresponding to the data held in said read buffer or in said write buffer, said one bus interface sends said access request to said arbiter, after storing said read data in said read buffer from said shared resource is completed, or after writing the write data held in said write buffer to said shared resource is completed.