Patent ID: 8456890

Claim:
A multi-level resistance change memory comprising: a memory cell comprising a first resistance change film, one end of the first resistance change film connected to a first node, and the other end of the first resistance change film connected to a second node; a second resistance change film, one end of the second resistance change film connected to a third node, and the other end of the second resistance change film connected to the second node; and a capacitor connected between the first and second nodes; a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor; and a control circuit which controls an operation to store multi-level data in the memory cell by using the first and second voltage pulses in a writing.