Patent ID: 6931087

Claim:
A clock circuit comprising: first and second clock sources; a multiplexer having a first input coupled to the first clock source, a second input coupled to the second clock source, and an output selectively couplable to said first and second inputs; a clock detection circuit having an output representing a presence of said first clock source; said multiplexer having a selection input coupled to said clock detection circuit output such that said multiplexer selects said first clock source as its output when said first clock source is present; a phase-locked loop circuit (“PLL”) having an input coupled to said multiplexer output; and a frequency output; said PLL including a feedback filter circuit; and feedforward circuitry coupled to said feedback filter circuit and to said clock detection circuit output, said feedforward circuitry selectively coupling at least one circuit element to said feedback filter circuit, wherein said feedforward circuitry selective coupling is controlled by said clock detection circuit output.