Patent ID: 7307558

Claim:
An apparatus for serializing input data, comprising: a timing control circuit that is arranged to provide a first clock in response to a reference clock, and also arranged to provide a second clock in response to the reference clock, wherein the first clock signal and the second clock signal are each operated at a frequency that is substantially M/2 times the reference clock frequency, and wherein M corresponds to a multiplication factor associated with the timing control circuit; a first shift register circuit that is arranged to load a first N-bits of parallel input data according to a first clock signal at a first time, wherein the first shift register circuit is arranged to provide a first serial data stream that transitions in response to the first clock signal at a second time that is subsequent to the first time; a second shift register circuit that is arranged to load a second N-bits of parallel input data according to a second clock signal at a third time, wherein the second clock signal substantially 180 degrees out of phase with the first clock signal at the third time, the second time is different from the first time, and wherein the second shift register circuit is arranged to provide a second serial data stream that transitions in response to the second clock signal at a fourth time that is subsequent to the third time; and a multiplexer circuit that is arranged to couple one of the first serial data stream and the second serial data stream to an output node during a first time period, and also couple the other of the first serial data stream and the second serial data stream to the output node during a second time period, such that a serial data stream with a speed corresponding to M times the speed of the reference clock is provided at the output node.