Patent ID: 8081018

Claim:
A multi-modulus divider (MMD) circuit configured for operation at high frequencies, comprising: a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal; and a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal, wherein the pulse stretching circuit comprises an RS-latch; wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits; wherein the MMD circuit is configured for an operating frequency of at least 4 GHz; and wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are organized so that there are no more than two gate delays between a rising edge of the input clock signal a the rising edge of the output clock signal.