Patent ID: 8121186

Claim:
A decision feedback equalizer circuit, the circuit comprising: a comparator, wherein the comparator is operable to compare an input with a selected adjustment value corresponding to a first bit period, and to provide a decision output based at least in part on the comparison of the input with the selected adjustment value; a storage device operable to store a prior output of the comparator; a first adjustment calculation circuit that is operable to calculate a first adjustment feedback value based at least in part on the prior output of the comparator; a second adjustment calculation circuit that is operable to calculate a second adjustment feedback value based at least in part on the prior output of the comparator; a selector circuit, wherein the selector circuit is operable to select the first adjustment feedback as the selected adjustment value when the decision output is the first logic level, and wherein the selector circuit is operable to select the second adjustment feedback as the selected adjustment value when the decision output is the second logic level; and wherein at least one of the first adjustment feedback value and the second adjustment feedback value includes the prior output multiplied by an inter symbol interference value corresponding to a bit period of the prior output.