Patent ID: 7467178

Claim:
A system for overflow and saturation processing, comprising: an adder, operatively connected to receive first and second operands, and connected to add the operands to produce a result of the added operands; an accumulator, operatively connected to store at least a portion of the result of the added operands or at least a portion of a selected one of predetermined constants based on control signals; guard bits, operatively connected to store the remaining portion of the result of the added operands or the remaining portion of the selected one of predetermined constants based on the control signals; overflow logic operatively connected to the accumulator and to the guard bits so as to indicate overflow of the accumulator; saturation logic, operatively connected to the adder, to the guard bits, and connected to provide the control signals based on at least a portion of the result of the added operands and at least a portion of the guard bits; and wherein the saturation logic comprises a plurality of AND logic gates and a plurality of inverting logic gates, the pluralities of AND gates and the plurality of inverting logic gates configured to compare most significant bits of the guard bits and most significant bits of the result of the added operands, and further configured to generate the control signals in accordance with the comparison.