Patent ID: 7388800

Claim:
A memory control device comprising: a memory controller for controlling an operation of a DRAM and for directly outputting a clock enable signal to said DRAM without any intervening switches; a power controller for controlling supply of power to said DRAM from a main power supply or a back-up battery power supply and for monitoring the voltage of said main power supply; and pull-down resistance for pulling down the clock enable signal to low level; wherein if said power controller detects that the voltage of said main power supply is reduced below a predetermined value during a normal operation, said power controller is configured to switch a power supply for said DRAM from said main power supply to said battery power supply and to instruct a self-refresh mode to said memory controller, so that said memory controller changes the clock enable signal for said DRAM to the low level to establish the self-refresh mode of said DRAM, and wherein said power controller is further configured to stop the supply of power to said memory controller after said DRAM is set to the self-refresh mode, and, even after the supply of power to said memory controller has been stopped, the clock enable signal is maintained to the low level by said pull-down resistance, thereby maintaining the self-refresh mode.