Patent ID: 8642471

Claim:
A method for manufacturing a semiconductor structure, comprising: a) providing a substrate ( 100 ), and forming a dummy gate stack on the substrate ( 100 ), sidewall spacers ( 240 ) on sidewalls of the dummy gate stack, and source/drain regions ( 110 ) at both sides of the dummy gate stack, wherein the dummy gate stack comprises a dummy gate ( 220 ); b) forming a first contact layer ( 111 ) on surfaces of the source/drain regions ( 110 ); c) forming an interlayer dielectric layer ( 300 ) to cover the first contact layer ( 111 ); d) removing the dummy gate ( 220 ) or the dummy gate stack to form an opening ( 260 ), filling the opening ( 260 ) with a first conductive material ( 280 ) or with a gate dielectric layer ( 270 ) and a first conductive material ( 280 ) so as to form a gate stack structure, then performing annealing operation under 600° C.-800° C.; e) forming through holes ( 310 ) within the interlayer dielectric layer ( 300 ), so that at least a portion of the first contact layer ( 111 ) or at least portions of both the first contact layer ( 111 ) and the source/drain regions ( 110 ) are exposed in the through holes ( 310 ); f) forming a second contact layer ( 112 ) on the exposed portion of the first contact layer or on said exposed portions of both the first contact layer ( 111 ) and the source/drain regions ( 110 ); and g) filling the through holes ( 310 ) with a second conductive material to form contact vias ( 320 ), wherein the first contact layer ( 111 ) has a thickness less than 15 nm, the thickness of the second contact layer ( 112 ) is greater than the thickness of the first contact layer ( 111 ).