Patent ID: 7817657

Claim:
A circuit for processing network packets, comprising: a plurality of ports, the ports being identified in a first specification of the processing of the network packets, the first specification specifying a plurality of handlers that each include a plurality of actions and at least one collection of the actions, the first specification specifying a dependency between each pair of a first and second one of the handlers for which the actions of the first handler include a handle action for invoking the second handler, wherein the ports include at least one input port for receiving a first plurality of network packets and at least one output port for transmitting a second plurality of network packets; and at least one parallel unit coupled to the ports for processing the first plurality of network packets and generating the second plurality of network packets, each parallel unit corresponding to a respective independent set of the handlers, each parallel unit having a corresponding architecture that is a selected one of a first pipeline or a cluster of threads, each parallel unit including a concurrent unit for each collection of the actions of each handler in the respective independent set for the parallel unit, each concurrent unit being a second pipeline for implementing the actions of the collection for the concurrent unit.