Patent ID: 7714447

Claim:
A semiconductor chip arrangement, comprising: first and second semiconductor chips permanently fastened on top of one another and electrically conductively connected to one another; a ROM memory cell array comprising a connecting area, a matrix-like arrangement of cutouts formed in the connecting area, and respective memory contact areas arranged in at least a portion of the cutouts and fastening together the first and second semiconductor chips, wherein a respective memory cell is configured to be programmed by means of the presence or absence of a memory contact area in a respective cutout; and at least one read-out circuit located in at least one of the semiconductor chips and configured to apply an electrical potential to and read a respective memory cell, wherein the read-out circuit comprises two field effect transistors having sources and drains coupled in series between two potentials of a supply voltage, and having gates coupled to one of the two potentials via a resistor if a memory contact area assigned to the relevant memory cell is not present, and the gates coupled to the other potential via this memory contact area if a memory contact area assigned to the relevant memory cell is present.