Patent ID: 7382668

Claim:
A memory device having an open bit line architecture, comprising: a plurality of dummy memory cells; a plurality of dummy bit lines connected to the dummy memory cells, the dummy bit lines to connect the dummy memory cells to a fixed voltage during a normal operation mode; a first voltage bus connected to a first subset of dummy bit lines, the first subset including at least one dummy bit line of the dummy bit lines; a second voltage bus connected to a second subset of dummy bit lines, the second subset including at least one dummy bit line of the dummy bit lines, each of the dummy bit lines connected to either the first or second voltage bus; and a voltage controller connected to the first voltage bus and the second voltage bus, the voltage controller to provide a first variable control voltage to a first subset of the dummy bit lines during a test mode and to provide a second variable control voltage to a second subset of the dummy bit lines during the test mode, at least one of the first variable control voltage and the second variable control voltage having a voltage level that is different from a voltage level of the fixed voltage.