Patent ID: 8848419

Claim:
An integrated circuit memory, comprising: a bit cell storing a logical bit value in a state of a memory element that has a changeable resistance, the memory element being coupled to a bit line at least when the bit cell is addressed during a read operation; a sense circuit coupled to the bit line for reading the logical bit value from the bit cell during the read operation, wherein addressing the bit cell couples said changeable resistance of the memory element onto the bit line; wherein the sense circuit comprises a sense circuit latch, and two level detectors that are switchable for controlling a logic state of the sense circuit latch; wherein one of the level detectors of the sense circuit is coupled to the bit line and another of the level detectors is coupled to a reference bit line providing a resistance that is greater and less than the changeable resistance and a changeable current amplitude when the bit cell is storing different said logical bit values; wherein level coupled to the level detectors by the respective bit line and reference bit line ramp to a switching threshold of the level detectors at rates that differ with the changeable resistance of the memory element of the bit cell; and, wherein the logic state of the sense circuit latch is set by the first of the bit line and the reference bit line to meet the switching threshold.