Patent ID: 7535112

Claim:
A semiconductor construction comprising: a semiconductor substrate, the semiconductor substrate comprising a metal-containing layer; a wire bonded to a bonding region of the metal-containing layer; an electrically insulative layer over the metal-containing layer, and having an opening extending therethrough to the wire-bonding region; a multi-level pattern of radiation-imageable material over the electrically insulative layer, the multi-level pattern of radiation-imageable material having a first topographical region and a second topographical region which are each defined by substantially-horizontal uppermost surfaces, the substantially-horizontal uppermost surface of the first topographical region being elevationally below the substantially-horizontal uppermost surface of the second topographical region by at least about 2 microns, and the first topographical region being between the second topographical region and the bonding region; the electrically insulative layer having an entirely planar upper surface under the first topographical region of the radiation-imageable material; and the wire extending vertically from the bonding region, and not having any portion directly over the first topographical region.