Patent ID: 8679915

Claim:
A method of manufacturing a semiconductor device in which a non-volatile memory cell is formed in a memory cell region and a MOS transistor is formed in a logic region, the method comprising the steps; (a) forming a first gate dielectric film over a semiconductor substrate; (b) forming a first conductive film over the first gate dielectric film; (c) forming a first dielectric film over the first conductive film; (d) forming a select gate comprising a multilayer of the first conductive film and the first dielectric film by patterning the first conductive film and the first dielectric film in the memory cell region; (e) after the step (d), forming a second gate dielectric film including a charge trapping film over the semiconductor substrate; (f) forming a second conductive film over the second gate dielectric film; (g) forming a memory gate of the non-volatile memory cell formed on a side of the select gate by etching the second conductive film using an anisotropic etching and removing the second conductive film in the logic region, the select gate formed as a side wall structure; (h) forming a gate electrode of the MOS transistor comprising the first conductive film by patterning the first conductive film in the logic region; and (i) forming a first impurity region of the memory cell and a second impurity region of the MOS transistor over the semiconductor by using an ion implantation, wherein the first dielectric film formed over the logic region is removed prior to the step (h).