Patent ID: 7308667

Claim:
An LSI physical designing method comprising: a floor plan processing step wherein a floor plan for arranging a plurality of circuit blocks, including a circuit block of a non-rectangular area, in a chip is formed; a layout step wherein the circuit block of said non-rectangular area is divided into a plurality of rectangular areas that are arranged in said chip so as to be adapted to said floor plan; and a wiring step wherein said plurality of circuit blocks, including the circuit block of said non-rectangular area divided into the plurality of rectangular areas, having been arranged in said chip, are mutually wired, wherein in said floor plan processing step, after the plurality of circuit blocks, including the circuit block of the non-rectangular area divided into the plurality of rectangular areas, are arranged in said chip, a pair of adjacent circuit blocks having empty areas are searched, a self rectangular empty area is deleted from a part of an opposite side of one of said circuit blocks, a self rectangular empty area is deleted from a residual portion of an opposite side of the other circuit block, and a pair of non-rectangular areas having concave/convex fitting shapes are formed.