Patent ID: 7538602

Claim:
A semiconductor memory device comprising: a memory core circuit that includes at least a word line a peripheral circuit; a Vpp generating circuit configured to receive an external power supply voltage to generate a stepped-up voltage higher than the external power supply voltage; a Vii generating circuit configured to generate a predetermined voltage lower than the stepped-up voltage; a first internal power supply line coupled between the Vpp generating circuit and the memory core circuit to supply the stepped-up voltage to at least the word line; a second internal power supply line coupled between the Vii generating circuit and the memory core circuit and between the Vii generating circuit and the peripheral circuit to supply the predetermined voltage to both the memory core circuit and the peripheral circuit; wherein the Vpp generating circuit includes; a pump circuit configured to receive the external power supply voltage to generate the stepped-up voltage; and a detector circuit, coupled to the pump circuit, configured to detect the stepped-up voltage generated by the pump circuit, to output to the pump circuit an activation/deactivation signal that controls activation/deactivation of said pump circuit, and to adjust an amount of a bias current of the detector circuit in response to the activation/deactivation signal; wherein the Vii generating circuit includes: a voltage generating circuit configured to generate a reference voltage; an NMOS transistor configured to receive at a gate node thereof the reference voltage, to receive at a drain node thereof the external power supply voltage, and to generate at a source node thereof the predetermined voltage; and a PMOS transistor, provided between the drain node of the NMOS transistor and the external power supply voltage, configured to receive at a gate thereof a power-down signal indicative of a power-down mode, wherein the reference voltage applied to the gate node of the NMOS transistor is set to LOW in response to a HIGH state of the power-down signal applied to the gate node of the PMOS transistor.