Patent ID: 7144816

Claim:
A method for fabricating a semiconductor structure, comprising: depositing a polysilicon layer on the semiconductor substrate; removing a portion of the polysilicon layer to form a high region and a low region; forming a suicide layer over the semiconductor substrate; selecting chemical mechanical polishing parameters to remove the silicide layer at a first rate and to remove the polysilicon layer at a second rate, where the first rate is higher than the second rate; removing a portion of the suicide layer by chemical mechanical polishing at the first rate; forming a dielectric layer over the silicide layer; removing a portion of the dielectric layer to expose the portion of the silicide layer before removing the portion of the silicide layer; and forming a top layer after forming the dielectric layer and removing a portion of the top layer before removing the portion of the dielectric layer, in which the top layer comprises a titanium nitride layer.