Patent ID: 8701074

Claim:
A computer-implemented method for identifying modes from a plurality of modes of a circuit that can be merged, the method comprising: receiving information describing a plurality of modes of a circuit, the information describing each mode comprising constraints, each constraint applicable to one or more paths; determining whether pairs of modes from the plurality of modes are mergeable, comprising: selecting a pair of modes comprising a first mode and a second mode; selecting a first constraint from the first mode, the first constraint applicable to a first set of paths; comparing the selected first constraint to constraints in the second mode to find a corresponding constraint, the corresponding constraint applicable to a second set of paths; transforming the selected first constraint such that the transformed constraint is applicable to a subset of paths of the first set of paths, the subset of paths of the first set of paths excluding at least one path of the second set of paths; and determining that the pair of modes is mergeable responsive to the transforming; identifying a subset of modes from the plurality of modes, such that every pair of modes in the subset is determined to be mergeable; and storing, in a non-transitory computer storage device, information indicating that modes from the subset of modes can be merged into a merged mode such that static timing analysis of the merged mode is equivalent to static timing analysis of the subset of modes.