Patent ID: 8456434

Claim:
A capacitance measurement circuit comprising: a reference signal generator for generating a reference signal; a fixed delay chain for delaying the reference signal for a time corresponding to a reference delay value, and outputting the delayed reference signal; a variable delay chain for delaying the reference signal for a time corresponding to a code value, and outputting the delayed reference signal; a first delay unit for delaying an output signal of the fixed delay chain for a fixed time, and outputting a fixed delay signal; a second delay unit including a pad through which a capacitance is externally applied, the second delay unit being configured to variably delay the output signal of the variable delay chain in response to the capacitance applied through the pad and output a sensing signal; and a data generator for increasing or reducing and outputting the capacitance value in response to a difference in delay time between the fixed reference signal and the sensing signal, and varying and outputting the code value in response to the increased or reduced capacitance value; wherein the data generator comprises: a phase detector for outputting a detection signal in response to the difference in delay time between the fixed reference signal and the sensing signal; and a delay pump for gradually increasing or decreasing and outputting the capacitance value according to predetermined rules in response to the detection signal, varying the code value in response to the capacitance value, and outputting the varied code value to the variable delay chain; wherein the delay pump comprises: a counter for gradually increasing or decreasing and outputting the capacitance value according to predetermined rules in response to the detection signal; and a subtracter for subtracting the capacitance value from the reference delay value and outputting the code value.