Patent ID: 8741727

Claim:
A method of manufacturing a semiconductor device comprising: forming a first insulating film in a first region, a second region, and a third region of a semiconductor substrate; forming a flash memory cell including a floating gate, a second insulating film, and a control gate on the first insulating film in the first region; forming a first electrode of a capacitor on the first insulating film in the second region; forming a first silicon oxide film, a silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the silicon nitride film as the second insulating film on the first electrode and on the first insulating film in the third region; selectively dry-etching the second insulating film on a partial region of the first electrode to remove the silicon nitride film and the second silicon oxide film with the first silicon oxide film on the partial region of the first electrode being left; selectively wet-etching and removing the first insulating film and the second insulating film in the third region with the first silicon oxide film on the partial region of the first electrode being covered by a mask and thereby being left; forming a third insulating film by subjecting a surface of the semiconductor substrate in the third region to thermal oxidation after the selectively wet-etching and removing the first insulating film and the second insulating film; forming a first gate electrode on the third insulating film; forming a second electrode of the capacitor on a region of the second insulating film on the first electrode other than the partial region; etching and removing the first silicon oxide film in the partial region after forming the second electrode; forming a fourth insulating film in the first region, the second region, and the third region after forming the second electrode and the first gate electrode; forming a hole in the fourth insulating film in the partial region; and forming a conductive plug in the hole.