Patent ID: 7586794

Claim:
A method of operating a memory device including a memory cell array arranged in a plurality of sections of memory cells, with each section of memory cells including a plurality of sub-sections of memory cells, the method comprising: providing a current memory address for a current read operation from a controller, wherein the current memory address includes a current section address portion and a current sub-section address portion; comparing the current section address portion and a previous section address portion of a previous read operation; when the current and previous section address portions are different, enabling a wait signal at the controller; while enabling the wait signal at the controller, copying a section of data from the memory cell array to a section buffer wherein the section of data is copied from a section of memory cells defined by the current section address portion of the current memory address; and after copying the section of data to the section buffer, transmitting a sub-section of the data from the section of data in the section buffer to the controller.