Patent ID: 7215312

Claim:
A semiconductor device comprising: a first input circuit which receives only one clock signal supplied from outside; a second input circuit which receives a data signal supplied from outside, in response to said clock signal received by said first input circuit; a signal processing circuit which performs signal processing based on said data signal received by said second input circuit; a first output circuit which inverts said clock signal received by said first input circuit, and outputs the inverted clock signal; and a second output circuit which delays said data signal received by said second input circuit by a half cycle of the clock signal, and outputs the delayed data signal only in response to said clock signal, wherein said second output circuit delays said data signal by using a latch circuit, and wherein said data signal carries a pair of information pieces at positions corresponding to a leading edge and a trailing edge of said clock signal, said signal processing circuit captures a preceding one of said pair of information pieces from the data signal after said preceding one of said pair of information pieces is output from a delay circuit, and a following one of said pair of information pieces from the data signal before said following one of said pair of information pieces is input to said delay circuit.