Patent ID: 7471528

Claim:
A parallel operating system of operating in parallel a multiplicity (N) of controller ICs, each controller IC comprising: an oscillator block for generating a triangular wave signal and a clock signal when connected to a frequency determination capacitor and a first frequency determination resistor, a logic block receiving said clock signal and outputting a signal obtained by frequency-dividing said clock signal; a first external terminal connected to said frequency determination capacitor and adapted to serve as an output terminal when said triangular wave signal is generated, but serve as an output terminal for receiving an external triangular wave signal when said triangular wave signal is not generated; a second external terminal connected to said first frequency determination resistor; a third external terminal adapted to serve as an input terminal of a startup signal; and a mode circuit for outputting signal, which enables said oscillator block and said logic block when said first frequency determination resistor is connected to said second external terminal, and which disables said oscillator and said logic block when said first frequency determination resistor is not connected.