Patent ID: 8195926

Claim:
In a processor having a branch history table, a pattern history table and a global history register, a branch predictor method, comprising: storing a plurality of encountered branch instructions in the branch history table; indexing the branch history table by a branch instruction address; in response to a completion of a branch instruction, modifying an entry of the branch history table; indexing the pattern history table; selecting at least one of a branch history entry and a pattern history table entry as a prediction for the branch instruction, wherein the pattern history table entry is selected as the prediction for the branch instruction in response to the branch history entry being in a state specifying to use the pattern history table entry; maintaining a parameterized accuracy threshold in a gshare accuracy register; maintaining a parameterized count threshold in the gshare accuracy register; comparing a pattern history table accuracy to the parameterized accuracy threshold; and in response to the pattern history table accuracy falling below the parameterized accuracy threshold, and in response to a count of completed pattern history branches in the gshare branch count register is above the parameterized count threshold, purging the pattern history table by removing branch history table entries from the pattern history table state and preventing branch history table entries from transitioning into the pattern history table state until a stopping condition is met to stop purging the pattern history table, wherein the stopping condition is met in response to a stop threshold, wherein the gshare accuracy register is incremented if the pattern history table prediction is correct and is decremented if the pattern history table prediction is incorrect.