Patent ID: 7337419

Claim:
An integrated circuit comprising: an aggressor signal path extending from a first node to a second node; a victim signal path adjacent to the aggressor signal path; a first transistor having a first control input for controlling the conduction of current between first and second terminals of the first transistor, wherein the first control input is coupled to an aggressor line transition sensing node, wherein the aggressor line transition sensing node is electrically coupled to signals on the aggressor signal path; a second transistor having a second control input for controlling the conduction of current between first and second terminals of the second transistor, wherein the second transistor is connected in series with the first transistor to form a transistor conduction path; an inverting delay circuit having an input connected to the aggressor line transition sensing node, and having a delay output signal connected to the second control input of the second transistor; and a counteracting voltage source connected to one end of the transistor conduction path, and wherein the victim signal path is connected to the other end of the transistor conduction path wherein upon the aggressor line transition sensing node sensing a voltage change on the aggressor signal path that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim signal path, the induced voltage pulse is counteracted by coupling the victim signal path to the counteractive voltage source, and wherein after a delay determined by the inverting delay circuit, the coupling of the counteractive voltage source is removed from the victim signal path.