Patent ID: 6968483

Claim:
A circuit for testing a data memory, comprising: a processing unit connected to the data memory, said processing unit configured for: applying a first function to a predetermined test pattern for generating therefrom data items to be written to the data memory; reading the data items from the data memory and applying a second function to the data items read from the data memory for generating therefrom test data items, the second function being a reciprocal function of the first function and a number of the data items being greater than a number of test data items; a test device connected to and outputting to said processing unit function data items defining the first function and the second function for said processing unit; and a comparison device: being connected to said processing unit and to said data memory; receiving test data from the data memory; and determining if the data memory is faulty based upon a comparison of the test data items produced by said processing unit with each other and with the predetermined test pattern upon which the first function has not been applied.