Patent ID: 8044724

Claim:
A LC-based phase-locked loop circuit, comprising: a charge pump coupled to receive an error signal that is proportional to a phase difference between a reference clock and a feedback clock, wherein the charge pump generates an output signal in response to the error signal, wherein the charge pump comprises a capacitor; a loop filter that removes high frequency components above a predetermined threshold from the output signal, thereby creating a voltage control signal, wherein the loop filter comprises: an adjustable capacitor coupled between an output of the charge pump and a voltage supply terminal; an adjustable resistor coupled between the output of the charge pump and a first node; and a fixed capacitor coupled between the first node and the voltage supply terminal; a feedback loop that provides a feedback voltage from the loop filter to the charge pump, wherein the feedback loop comprises a buffer having an input coupled to the first node and an output connected to the capacitor of the charge pump, wherein the feedback voltage reduces jitter in the phase-locked loop circuit; and a voltage controlled oscillator that generates a clock signal having a frequency based on the voltage control signal.