Patent ID: 8103791

Claim:
A data processing system, comprising: a plurality of processing units coupled for communication, said plurality of processing units including at least a local master processing unit and multiple local hub processing units each coupled to the local master processing unit by a respective one of a plurality of communication links, wherein said local master processing unit includes: a master that initiates memory access requests; a snooper that receives memory access requests; and interconnect logic coupled to the plurality of communication links, wherein said interconnect logic includes request logic that synchronizes internal delivery of a memory access request of said master to said snooper with delivery, via the plurality of communication links, of the memory access request to snoopers in the plurality of local hub processing units, wherein the request logic synchronizes the internal delivery by applying a greater delay to the memory access request to be delivered to the snooper than to that to be delivered to the plurality of local hub processing units, wherein the request logic applies the delay to the memory access request to be delivered to the snooper after transmission by the request logic of the memory access request to the plurality of local hub processing units and prior to delivery of the memory access request to the snooper.