Patent ID: 7809929

Claim:
A method for universal register renaming, the method comprising: allocating a destination tag for an instruction being issued in a microprocessor; setting a first destination type and a second destination type for the instruction in a logical register array in the microprocessor; asserting a first rename buffer bit if a result of the instruction is written to a rename buffer corresponding to the first destination type; asserting a second rename buffer bit if a result of the instruction is written to a rename buffer corresponding to the second destination type; in an issue queue, determining whether an issuing instruction depends on a younger instruction; if the issuing instruction does not depend on a younger instruction, asserting a first architected register bit corresponding to the first destination type or a second architected register bit corresponding to the first destination type in the issue queue for the issuing instruction; if the issuing instruction depends on a younger instruction, de-asserting the first architected register bit or the second architected register bit in the issue queue for the issuing instruction; for an issuing instruction with the first rename buffer bit asserted or the second rename buffer bit asserted, sending a logical register target, one or more dispatching source register addresses, a dispatching destination tag, a first source destination tag corresponding to the first destination type, a first rename buffer bit corresponding to the first destination type, a second source destination tag corresponding to the second destination type, and a second rename buffer bit corresponding to the second destination type for the issuing instruction to a corresponding execution unit; writing a result of execution into a rename buffer corresponding to the first destination type or a rename buffer corresponding to the second destination type of the executing instruction using the execution destination tag as a write address; at completion time, sending completing destination tag for a completing instruction to the issue queue and the rename stage; using the completing destination tag to read out completing register target fields and destination type bits from the logical register array; using the completing destination tag to read out a result from a rename buffer corresponding to the first destination type or a rename buffer corresponding to the second destination type of the completing instruction; and writing the result to an architected register corresponding to the first destination type or an architected register corresponding to the second destination type of the completing instruction.