Patent ID: 7205807

Claim:
A method for controlling harmonic content in a digital signal driver circuit, having a digital input signal applied to an input node associated with said driver circuit and generating a corresponding digital output signal on an output node associated with said driver circuit, said method comprising the steps of: connecting two or more MOS devices in cascode connection with each other and with said input node and said output node, wherein a first of the MOS devices is configured in a common source arrangement having a gate that receives the digital input signal, and a second of the MOS devices is configured in a common gate arrangement such that a source of the second MOS device is electrically connected to a drain of the first MOS device; connecting an added capacitance element between a source of the first MOS device and a source of one of the MOS devices other than the first MOS device; and controlling a slew rate of at least one of leading and trailing edge transitions associated with said output signal based on the added capacitance element in combination with one or more parasitic capacitances associated with said two or more cascode connected MOS devices, wherein said parasitic capacitances includes at least capacitance as a by-product of fabrication.