Patent ID: 7023238

Claim:
A programmable logic integrated circuit comprising: a plurality of programmable interconnect lines; a plurality of logic array blocks, programmably coupled to the programmable interconnect lines; and a plurality of input blocks, programmably coupled to the plurality of logic array blocks, wherein signals output from the input blocks are programmably coupled using the programmable interconnect lines to input to the plurality of logic array blocks, an input block comprising: a first buffer configured to receive an input signal and to provide a first output signal having a first polarity when the input signal is below a first switching threshold level, and provide a second polarity when the input signal is above the first switching threshold level; a second buffer configured to receive the input signal and to provide a second output signal at third polarity when the input signal is below a second switching threshold level, and provide the output signal at a fourth polarity when the input signal is above the second switching threshold level, wherein the second switching threshold level is different from the first switching threshold level; a first multiplexer having inputs coupled to the first and second buffers; and a third buffer coupled to an output of the multiplexer, wherein an output of the third buffer is programmably coupled to a control input of the first multiplexer, wherein the third buffer is programmably coupled to an output of the first buffer or an output of the second buffer though the first multiplexer.