Patent ID: 7230853

Claim:
A selective erase method for a flash memory device including a group of memory cells arranged in rows and columns, the method comprising: performing a Negative Gate and Bulk Erase (NGBE) operation on the group of memory cells by applying an electric field between control gates and a substrate of the flash memory device; verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells; identifying at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage; performing a further Negative Gate and Bulk Erase (NGBE) operation on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage; verifying the further erase operation; and repeating performing a further erase operation and verifying the further erase operation until all memory cells of the group of memory cells have threshold voltages lower than the desired erase threshold voltage; and wherein performing the further erase operation includes at least one of the following: applying a positive voltage exceeding a selected level to control gates and bulks of the memory cells of the at least one row of memory cells during the further erase operation; applying a negative voltage exceeding a selected level to control gates and bulks of the memory cells of the at least one row of memory cells during the further erase operation; applying a negative voltage exceeding a selected level to control gates of the memory cells of the at least one row of memory cells and a high voltage exceeding a selected level to sources of the memory cells of the at least one row of memory cells during the further erase operation; or applying a negative voltage exceeding a selected level to control gates of the memory cells to be re-erased during the further erase operation and a positive voltage exceeding a selected level to bulks of the memory cells to be re-erased during the further erase operation during the further erase operation.