Patent ID: 7332389

Claim:
A method of manufacturing a memory cell comprising an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact, said method comprising the steps of: forming said charge storage structure so as to be conductively coupled to said bit line via said transistor structure and said bit line contact; forming said transistor structure so as to be conductively coupled to said word line; forming said bit line contact by forming a conductively doped polysilicon plug within a contact hole bounded by insulating side walls, wherein said contact hole is filled with said doped polysilicon plug by partially filling said contact hole through an initial deposition technique and subsequently topping off said partial fill through selective doped polysilicon growth; and forming said doped polysilicon plug by filling said contact hole with said conductively doped silicon plug such that said plug defines an upper plug surface profile substantially free of concavities in contact with said bit line.