Patent ID: 8102194

Claim:
A dual frequency divider circuit comprising: a first input which receives a first clock signal; a second input which receives a second clock signal having a frequency equal to that of the first clock signal and out of phase with the first clock signal; a first divider circuit connected to said first and second inputs which generates a first divided signal having a frequency less than that of the first clock signal, said first divider circuit including a first transmission gate controlled by said first input, a first storage cell connected to an output of said first transmission gate, a first inverter having an input connected to said output of said first transmission gate, a second inverter having an input connected to an output of said first inverter, a second transmission gate having an input connected to an output of said second inverter, and controlled by said second input, a second storage cell connected to an output of said second transmission gate, a third inverter having an input connected to said output of said second transmission gate, and an output connected to an input of said first transmission gate, and a first divider output connected to said output of said first inverter; and a second divider circuit connected to said first and second inputs which generates a second divided signal having a frequency equal to that of the first divided signal and out of phase with the first divided signal, said second divider circuit including a third transmission gate controlled by said second input, a third storage cell connected to an output of said third transmission gate, a fourth inverter having an input connected to said output of said third transmission gate, a fifth inverter having an input connected to an output of said fourth inverter, a fourth transmission gate having an input connected to an output of said fifth inverter, and controlled by said first input, a fourth storage cell connected to an output of said fourth transmission gate, a sixth inverter having an input connected to said output of said fourth transmission gate, and an output connected to an input of said third transmission gate, and a second divider output connected to said output of said fourth inverter.