Patent ID: 7791613

Claim:
A system, comprising: a first graphics device connected to a first point-to-point, packet-based interconnect; a graphics memory switch device coupled between the first graphics device and a root complex device, the graphics memory switch device including a first input to receive a first plurality of only contiguous virtual graphics memory addresses from the first graphics device over the first point-to-point, packet-based interconnect, and a graphics memory translator coupled to the first input to translate the first plurality of only contiguous virtual graphics memory addresses to a first plurality of non-contiguous physical memory addresses for use on a second point-to-point, packet-based interconnect; the graphics memory switch coupled between a second graphics device and the root complex device, the graphics memory switch includes a second input to receive a second plurality of only contiguous virtual graphics memory addresses from the second graphics device connected to a third point-to-point, packet-based interconnect; the graphics address translator coupled to the second input to translate the second plurality of only contiguous virtual graphics memory addresses to a second plurality of non-contiguous physical memory addresses for use on the second point-to-point, packet based interconnect to the root complex device, the graphics address translator including a single graphics memory page table; and the root complex device to receive the first and second plurality of non-contiguous physical memory addresses from the graphics memory switch device over the second point-to-point, packet based interconnect.