Patent ID: 7394414

Claim:
A method of error reduction in a digital-to-analog converter (DAC), the DAC having a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals wherein mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block and mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units, the method comprising: grouping sets of selectable source units from the plurality of selectable source units based upon the errors occurring in the plurality of selectable source units, wherein the sets of selectable source units include a first set of one selectable source unit and a plurality of sets, each set having two or more selectable source units; generating the mapping control signals from the mapping input signals, the mapping control signals selecting one or more set of the sets of selectable source units, wherein, for an incremental increase in a digital value of the digital input signals, sets of the plurality of sets of two or more selectable source units are successively switched on while alternating with switching on and off the first set of one selectable source unit; wherein, at least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.