Patent ID: 7960832

Claim:
An integrated circuit arrangement comprising: an electrically conductive conduction structure; and a layer stack arranged between the conduction structure and a dielectric positioned at a side wall of the conduction structure, wherein the layer stack comprises: an electrically conductive first conduction layer consisting of a first material; an electrically conductive first interlayer comprising a different material from the first conduction layer, and the first interlayer having a higher electrical resistivity than the first conduction layer, wherein the first conduction layer is arranged between the first interlayer and the dielectric; an electrically conductive second conduction layer comprising a different material from the first interlayer, and the second conduction layer having a lower electrical resistivity than the first interlayer; an electrically conductive second interlayer; and an electrically conductive third conduction layer comprising a first end in contact with the second interlayer and a second end coupled with the conduction structure, the electrically conductive third conduction layer consisting of the first material.