Patent ID: 6870776

Claim:
A data output circuit in a combined single data rate/double data rate (SDR/DDR) semiconductor memory device, the data output circuit comprising: a first and a third data latch that latch even data in response to an even clock and generate a first pull-up control signal and a first pull-down control signal, respectively, in a DDR mode, and that latch first data in response to a data output clock and generate the first pull-up control signal and the first pull-down signal, respectively, in an SDR mode; a second and a fourth data latch that latch odd data in response to an odd clock and generate the first pull-up control signal and the first pull-down control signal, respectively, in the DDR mode, and that latch second data in response to the data output clock and generate a second pull-up control signal and a second pull-down signal, respectively, in the SDR mode; a first data output driver that drives a first output pad to a predetermined voltage level in response to the first pull-up control signal and the first pull-down control signal; and a second data output driver that drives a second output pad to a predetermined voltage level in response to the second pull-up control signal and the second pull-down control signal.