Patent ID: 8291195

Claim:
A processor comprising: an executing unit to execute instructions included in a thread having a plurality of instructions; a supplying unit to supply the instructions to the executing unit; a buffer unit to retain the instructions to be supplied to the executing unit, the buffer unit including a plurality of buffers, each of the plurality of buffers including a plurality of entries to retain the instructions and a pointer unit to define a serial linking relationship between the buffers by setting a pointer of a first buffer to point an entry of a second buffer; and a control unit to control each of the plurality of buffers by use of a thread allocating unit to allocate a thread to which subsequent instructions to be retained next belongs, to a next buffer to retain the subsequent instructions to be retained next to the instructions already retained in the buffer unit, to make a serial linking relationship between buffers to which the thread is allocated within the buffer unit having an other serial linking relationship between buffers to which an other thread is allocated.