Patent ID: 7383587

Claim:
Apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; said processor is responsive to one or more exception conditions for triggering exception processing; and said processor is responsive to plural programmable parameters stored in an exception trap mask register, each of said plural programmable parameters respectively specifying whether a corresponding exception should he handled by a secure mode exception handler executing in a secure mode or should be handled by an exception handler executing in a mode within a current one of said secure domain and said non-secure domain when that exception occurs.