Patent ID: 7426683

Claim:
A method of correcting data in a semiconductor device comprising the steps of: storing a data word at a first address in a main memory array; generating a parity word from the data word, the parity word having fewer bits than the data word; storing the parity word at a second address in a sub-memory array, the sub-memory array having a different structure than the main memory array; reading the data word from the first address in the main memory array; reading the parity word from the second address in the sub-memory array; generating an error correction code in response to the data word from the main memory array and the parity word from the sub-memory array; generating a corrected data word from an exclusive-OR of the data word from the main memory and the error correction code; amplifying the data word from the main memory with a sense amplifier; and not amplifying the parity word from the sub-memory with a sense amplifier.