Patent ID: 7305607

Claim:
A nonvolatile ferroelectric memory device comprising: a main memory cell array including a plurality of nonvolatile ferroelectric memory cells configured as a plurality of main cell array groups; a horizontal parity check cell array adapted and configured to determine a parity of a horizontal portion of the plurality of main cell array groups and store the determined parity as code data in a horizontal parity memory array; a vertical parity check cell array adapted and configured to determine a parity of a vertical portion of the plurality of main cell array groups and store the determined parity as code data in a vertical parity memory array; and an error correcting code processing unit adapted and configured to compare data stored in the main cell array groups, the code data stored in the horizontal parity check cell array and the code data stored in the vertical parity check cell array and to correct error data generated from a corresponding column into normal data.