Patent ID: 8181054

Claim:
A circuit arrangement, comprising: a plurality of hardware resources, wherein each hardware resource has a power mode configurable between at least first and second power consumption states; and a programmable multi-media processor circuit, including separate circuits on respective circuit paths for processing video and audio, coupled to the plurality of hardware resources, the processor circuit configured to process program code that includes at least one power control instruction that includes an operand having power control information disposed therein, and a guard that specifies a condition, whereby processing of the power control instruction selectively sets power modes of at least two hardware resources among the plurality of hardware resources based upon the power control information disposed in the power control instruction and in response to an occurrence of the condition, the processor circuit being further configured to maintain the power modes of the at least two hardware resources in respective power-consumption states according to a resource power-management schedule that indicates when less-than all of the plurality of resources are to be disabled, including sleep and fully-off states, while processing at least one subsequent instruction in the program code.