Patent ID: 8399344

Claim:
A method of fabricating a semiconductor device comprising a gate stack of a gate dielectric layer and a gate electrode, the method comprising the steps of: forming the gate dielectric layer over a semiconductor substrate, the gate dielectric layer being a first metal oxide or first semimetal oxide having a first electronegativity value; forming a dielectric V T adjustment layer over the gate dielectric layer, the dielectric V T adjustment layer being a second metal oxide or second semimetal oxide having a second electronegativity value; and forming the gate electrode over the gate dielectric layer and the dielectric V T adjustment layer; wherein an Effective Work Function value of said gate stack is a function of a thickness and composition of the dielectric V T adjustment layer, and wherein the second electronegativity value is higher than both the first electronegativity value and an electronegativity value of Al 2 O 3 .