Patent ID: 8492792

Claim:
A semiconductor device comprising: a first conductive first semiconductor region; a plurality of second conductive second semiconductor regions formed at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive of the first semiconductor region; a plurality of the first conductive third semiconductor regions formed on a main surface of the second semiconductor region, the plurality of the first conductive third semiconductor regions being separated from each other; a gate electrode formed via a gate insulation film and arranged across one of the third semiconductor regions of one of the second semiconductor regions and one of the third semiconductor regions of another adjacent one of the second semiconductor regions; a source electrode electrically connected to the main surface of the second semiconductor region and the third semiconductor region; a plurality of holes formed at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other; second conductive fourth semiconductor regions mutually connected at bottom parts of the holes; and a drain electrode filling the holes to establish electric connection between the drain electrode and the fourth semiconductor regions.