Patent ID: 7079447

Claim:
A circuit, realizing a Sense Electronics Endowed (SEE) memory device with dynamical adapting of memory sense amplifiers, comprising: a memory array for realizing an SEE-memory device with dynamical adapting of memory sense amplifiers using a virtual sense amplifier with response speed control facility controlled by a “System Clock” signal and having external Address and Data I/O bus system connections; a virtual sense amplifier with read data input and output as well as a response speed control input, whereby a response speed control signal for said response speed control input is delivered from a Selection Controller unit; a Selection Controller unit with Address Change detect signal input generating a time dependent response speed control signal as output; and an address transition detection logic delivering said Address Change detect signal for said selection controller unit, whereby said Address Change detect signal is generated from an address being altered on said external Address bus system, then causing the reading of memory data from a memory address location as addressed via said Address bus system with a fully powered virtual sense amplifier and putting said memory data on said external data I/O bus, whereas said virtual sense amplifier is now modified into a reduced response speed mode configuration in order to reduce its power consumption according to a dynamical response speed control scheme established within said Selection Controller unit until the next Address Change detect signal is furnished by said address transition detection logic and said dynamical response speed control scheme for application within a read cycle operation governed by said “System Clock” signal; the dynamical response speed control scheme being generated so, that the response speed is controlled by said Address Change detect signal and defined in a time dependent manner reducing after a certain time the response speed characteristic of said virtual sense amplifier.