Patent ID: 8019585

Claim:
A computer system, comprising: a debug tool to produce a scan mismatch of a circuit, wherein the scan mismatch is due to one of a speedpath and a defect of the circuit; a circuit pruner to generate an input cone to the location of the scan mismatch, wherein the input cone comprises elements of the circuit that may cause the scan mismatch; a simulator to simulate logic values of the input cone to identify a subset of the elements of the circuit that may cause the scan mismatch and unrelated elements that do not contribute to the scan mismatch; a circuit pruner is configured to separate the unrelated elements from the subset of the elements for a correlation of the subset of elements to a physical layout of the circuit, wherein at least one of the circuit pruner, the simulator, and the circuit pruner comprise instructions stored in memory of the computer system, the instructions which when executed by a processor cause the processor to perform operations for at least one of generating the input cone, simulating the logic values, and separating the unrelated from the subset of the elements; and an infrared emission microscope (IREM) tool to locate, via locations of polygons of the subset of elements imported and overlayed to the physical layout, at least one element of the subset of the elements that contributes to the scan mismatch, wherein the location of the at least one element of the subset is determined via an observation from the IREM of the polygons for a plurality of cycles of operation of the circuit.