Patent ID: 7326631

Claim:
A method of manufacturing a semiconductor device with MOS transistors comprising gate electrodes formed in a packet of metal layers deposited upon one another, in which method, on a surface of a silicon body on which border active regions of silicon and field isolation regions insulating these regions with respect to each other, a layer of a gate dielectric is formed at the location of the active regions, after which a layer of a first metal is deposited wherein nitrogen is introduced at the location of a part of the active regions, after which a layer of a second metal is deposited on the layer of the first metal, and subsequently the gate electrodes are etched in the packet of superposed metal layers, characterized in that before nitrogen is locally introduced into the layer of the first metal, an auxiliary layer of a third, nitrogen-permeable metal is formed on this layer, characterized in that the nitrogen is locally introduced into the layer of the first metal by diffusion from a solid substance that contains an excess of nitrogen and is locally provided on the auxiliary layer.