Patent ID: 7490119

Claim:
An apparatus comprising circuitry for use as a floating point adder configured to compute a result of a floating-point operation, wherein the apparatus receives an aligned addend comprising a plurality of bits and a plurality of products, the apparatus comprising: a first circuit configured as a compound incrementer coupled to receive at least some of the plurality of bits of the aligned addend and a control signal, and configured to produce an output dependent upon the received bits of the aligned addend and the control signal; a second circuit configured as a compression counter coupled to receive at least some of the plurality of bits of the aligned addend and the products and configured to produce an output dependent upon the received bits of the aligned addend and the received products; a third circuit configured as a compound adder coupled to receive the output of the compression counter of the second circuit and configured to produce an output dependent upon the output of the compression counter of the second circuit; a fourth circuit configured as a carry network coupled to receive sign bits of the products and the output of the compression counter of the second circuit and configured to produce an output signal and a carry signal dependent upon the received sign bits of the products and the received output of the compression counter of the second circuit; a fifth circuit configured as a selector coupled to receive at least some of the plurality of bits of the aligned addend and the output signal and the carry signal produced by the carry network of the fourth circuit, wherein the selector is configured to produce a selection signal dependent upon the received bits of the aligned addend, the received output signal, and the received carry signal; and a sixth circuit configured as a plurality of multiplexers (muxes) coupled to receive the output of the compound incrementer of the first circuit, the output of the compound adder of the third circuit, and the selection signal produced by the selector of the fifth circuit, and configured to produce the result by selecting between the received output of the compound incrementer of the first circuit and the received output of the compound adder of the third circuit dependent upon the selection signal produced by the selector of the fifth circuit.