Patent ID: 6979607

Claim:
A method for operating a memory cell, comprising: applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes: a first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a work function greater than 4.1 eV; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a gate having a work function greater than 4.1 eV; a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; coupling the n-type well to a positive voltage which is less than a power supply voltage; and reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a work function greater than 4.1 eV.