Patent ID: 8587342

Claim:
A semiconductor integrated circuit including a logic circuit, the logic circuit comprising: a comparator configured to compare potentials of two output nodes; a charge holding portion electrically connected to the comparator, the charge holding portion comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor; and an output-node-potential determining portion, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor and one of the two output nodes, wherein the other of the source and the drain of the first transistor is electrically connected to the other of the two output nodes, wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and drain of the seventh transistor and the output-node-potential determining portion, wherein the other of the source and the drain of the third transistor is electrically connected to the output-node-potential determining portion, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor, wherein the other of the source and the drain of the second transistor is configured to receive a first signal input, wherein the other of the source and the drain of the fourth transistor is configured to receive a second signal input, wherein the other of the source and the drain of the sixth transistor is configured to receive a third signal input, and wherein the other of the source and the drain of the eighth transistor is configured to receive a fourth signal input.