Patent ID: 7460395

Claim:
A memory array comprising: at least one word line; at least one bit line; at least one third line; at least one thyristor having an anode, a cathode, and at least one base region, the anode being connected to one of the at least one word line, bit line and third line, the cathode being connected to another of the at least one word line, bit line, and third line, and the at least one base region being capacitively coupled to remaining of the at least one word line, bit line and third line; a word line controller selectably operable to apply a word line bias to the at least one word line; a sense amp and bit line controller selectable operable to sense/apply a bit line bias of/to the at least one bit line; a write enable controller selectably operable to apply a write-enable bias to the at least one third line; and a read/write controller operable to periodically select and drive the word line controller, the sense amp and bit line controller and the write enable controller to refresh the at least one thyristor and restore the respective state of its then first or second operative states.