Patent ID: 7119593

Claim:
Circuitry for delaying a signal, comprising: a phase-locked loop comprising a plurality of separate output nodes for outputting a plurality of separate phase-locked loop output signals in response to a reference signal; a plurality of separate buffers coupled to the separate output nodes of the phase-locked loop for receiving separate phase-locked loop output signals, and comprising a plurality of separate output nodes for outputting separate buffered output signals on separate paths; a multiplexing element for receiving the separate buffered output signals on the separate path and a control signal, wherein the multiplexing element selects one of the separate buffered output signals on the separate paths as an operative buffered output signal in response to the control signal; and a delay line receiving a delay control input signal and the operative buffered output signal from the multiplexing element; wherein the delay line outputs a delayed output signal in response to the delay control input signal, wherein the delay line includes a plurality of delay elements, wherein the delay control input signal selects a combination of delay elements to define a delay independent from delay in the phase-locked loop.