Patent ID: 6947077

Claim:
A N-bit proportional bit counting circuit comprising: N counter cells, at least M of said counter cells comprising, (a) a first input element that receives a plurality of independent break-in signals to change a counting operation; and (b) a bit processing element coupled to the first input element and configured to receive a clock signal and further configured to, on each pulse of said clock signal: (1) enable counting if all of the break-in signals are de-asserted; and (2) disable counting if at least one of the break-in signals is asserted; wherein N is an integer greater than or equal to 3, M is an integer greater than or equal to 2 and less than N, said M counter cells form a sequence of adjacent bits of said counter, and in each of said M counter cells, said first input element receives a same number of said independent break-in signals.