Patent ID: 7106629

Claim:
A split-gate flash memory cell comprising: an N-type well, region formed in a substrate, the N-type well region having formed therein a P+ source, a P+ drain, and a channel region extending between the P+ source and the P+ drain; a first insulating layer disposed over the well region; a polysilicon floating gate comprising a lower portion and a top portion to form a polysilicon-polysilicon interface, said floating gate disposed over the first insulating layer, wherein the floating gate is positioned over a first portion of the channel region but not a second portion of the channel region; a second insulating layer disposed over floating gate; a control gate including a first portion disposed over the first insulating layer, the first portion of the control gate being positioned over the second portion of the channel region, the control gate including a second portion disposed over the second insulating layer; and wherein the cell is operable to be programmed by a band-to-band hot electron (BBHE) technique and erased by a polysilicon to polysilicon tunneling technique comprising said interface.