Patent ID: 8898674

Claim:
A system comprising: a plurality of memory controllers each configured to maintain memory databus utilization by a corresponding processor managed by a respective memory controller at or below a threshold set for each respective processor to maintain memory databus utilization of the system at or below a system threshold, wherein the memory databus utilization threshold for each respective processor is a quantity of memory accesses within a time window of a certain quantity of memory clock cycles; and a service processor configured to receive memory databus utilization data from the memory controllers and programmed to, in response to determining that memory databus utilization for at least one of the processors is below its respective threshold, reallocate at least a portion of unused databus utilization from the at least one processor to at least one of the other processors by increasing the memory databus utilization threshold of the at least one of the other processors, wherein the memory databus utilization data are memory clock cycles currently utilized divided by the certain quantity of memory clock cycles within the time window.