Patent ID: 7141469

Claim:
A method of forming poly insulator poly capacitors by using a self-aligned salicide process, comprising: providing a semiconductor substrate having a shallow trench isolation structure and a transistor structure thereon, wherein a polysilicon gate of the transistor structure being formed while forming a first polysilicon layer on the shallow trench isolation structure, the first polysilicon layer is used as a lower electrode of a capacitor; forming an oxide layer on a surface of the semiconductor substrate, the first polysilicon layer, the shallow trench isolation structure and the transistor structure, the oxide layer is used as a self-aligned salicide block and; forming a second patterned polysilicon layer on a surface of the oxide layer, the second patterned polysilicon layer being on the first polysilicon layer and the surface of the oxide layer is used as an upper electrode of the capacitor; removing a portion of the oxide layer on the transistor structure, leaving a residual oxide layer on and directly contacting the shallow trench isolation structure and a top surface of, the first polysilicon layer, the residual oxide layer, being used as a dielectric layer; and performing a self-aligned salicide process to form a self-aligned salicide on a surface of the transistor structure on the semiconductor substrate and top surface and sidewall surfaces of the second patterned polysilicon layer, performing the self-aligned salicide process including the steps of; forming a metal layer on the semiconductor substrate, the transistor structure and the second patterned polysilicon layer; performing a rapid thermal anneal heating process, resulting in a silicidation reaction on a junction between the metal layer and the transistor structure and the second patterned polysilicon layer, forming a self-aligned salicide; and removing unreacted portions of the metal layer.