Patent ID: 7068551

Claim:
A semiconductor memory device, comprising: a plurality of memory cells; a first pair of bit lines provided correspondingly to said plurality of memory cells; an amplifier circuit which amplifies signals on said first pair of bit lines; and a signal transmission line for transmitting signals amplified by said amplifier circuit, wherein said first pair of bit lines is formed in a first layer on a main face of a semiconductor substrate and arranged to extend in a first direction of said main face, wherein said signal transmission line is formed in a second layer positioned above said first layer and is arranged to extend in said first direction, wherein said signal transmission line is so arranged as to substantially equalize a capacitance between one of said first pair of bit lines and said signal transmission line to a capacitance between the other of said first pair of bit lines and said signal transmission line, wherein a part of said signal transmission line is bent over said first pair of bit lines and arranged over a second pair of bit lines which are different from said first pair of bit lines, wherein a part of said signal transmission line which is not arranged over said first pair of bit lines and said second pair of bit lines is not arranged in parallel with said first pair of bit lines and said second pair of bit lines, wherein a part of said signal transmission line which is not arranged over said first pair of bit lines and said second pair of bit lines does not cross at right angles with said first pair of bit lines and said second pair of bit lines.