Patent ID: 7400328

Claim:
A graphics system comprising: a graphics first-in-first-out (FIFO) for storing graphics pixels that are computer-generated; a memory fetch controller that reads graphics pixels from a frame-buffer memory and writes the graphics pixels to the graphics FIFO; a video FIFO that buffers video pixels for display in a video-overlay window; a multiplexer that sends graphics pixels from the graphics FIFO to a display in response to a mux signal in a first state and sends video pixels from the video FIFO to the display in response to the mux signal in a second state; a comparator, receiving graphics pixels from the graphics FIFO, for activating the mux signal in the second state when a graphics pixel matches a predetermined color key; a row index register having a plurality of row indicator bits, each row indicator bit for a group of M display lines of pixels; a column index register having a plurality of column indicator bits, each column indicator bit for a group of N display columns of pixels; and a fetch inhibitor that disables the memory fetch controller from reading graphics pixels from the frame-buffer memory for a block of N×M graphics pixels when a row indicator bit and a column indicator bit for the block both indicate that the block contains only graphics pixels that match the pre-determined color-key; wherein M and N are whole numbers of at least 2, whereby fetching of the frame-buffer memory is disabled in response to row and column indicator bits.