Patent ID: 7145242

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on said semiconductor substrate; a gate electrode of a MIS transistor formed on said gate insulating film; first and second impurity diffusion regions constituting source and drain of said MIS transistor formed in said semiconductor substrate on both sides of said gate electrode; a first insulating film formed on said semiconductor substrate inclusive of said gate electrode and said first and second impurity diffusion regions; a second insulating film of a silicon nitride film formed on said first insulating film; first and second contact holes formed in and through said first and second insulating films and respectively reaching said first and second impurity diffusion regions; first and second conductive plugs embedded in said first and second contact holes and connected to said first and second impurity diffusion regions, respectively, an upper surface of the first and second conductive plugs being substantially at the same level with an upper surface of the second insulating film; a third insulating film formed on said second insulating film and the upper surface of the first and second conductive plugs; a third contact hole formed through said third insulating film and reaching said first conductive plug; a first conductive layer connected to said first conductive plug via said third contact hole; and a fourth insulating film made of a silicon nitride film and formed to cover said first conductive layer, wherein said fourth insulating film is thicker than said second insulating film.