Patent ID: 7843069

Claim:
A structure, comprising: an interlevel dielectric layer on a top surface of a substrate; a plurality of electrically conductive wires in said interlevel dielectric layer, top surfaces of said wires coplanar with a top surface of said interlevel dielectric layer; a dielectric passivation layer on said interlevel dielectric layer and covering said plurality of electrically conductive wires, a top surface of each wire of said plurality of electrically conductive wires exposed in a respective via opening in said dielectric passivation layer; a plurality of electrically conductive wire bond pads on said dielectric passivation layer, said wire bond pads spaced apart, each wire bond pad of said plurality of wire bond pads having first and second ends, said first ends of each wire bond pad of said plurality of electrically conductive wire bond pads extending over a respective via opening and contacting a respective wire; a terminal dielectric passivation layer on said dielectric passivation layer, said terminal dielectric passivation layer filling spaces between adjacent wire bond pads of said plurality of wire bond pads, top surfaces of said terminal dielectric passivation layer in said spaces about coplanar with top surfaces of each wire bond pad of said plurality of wire bond pads, said terminal dielectric passivation layer on top surfaces of and overlapping said first and second ends of each wire bond pad of said plurality of wire bond pads, and said terminal dielectric passivation layer overlapping at least three sides of each wire of said respective wires; and openings in said terminal dielectric passivation layer, regions of said top surfaces of each wire bond pad of said plurality of wire bond pads exposed between respective first and second ends of each wire bond pad of said plurality of wire bond pads in said openings.