Patent ID: 6857039

Claim:
A bi-directional bus circuitry shared among a plurality of circuit blocks, comprising: a data bus divided into (J+1) (J: natural number being 1 or more than 1) bus nodes, each of said plurality of circuit blocks being connected to one of said (J+1) bus nodes; a potential fixing circuit provided corresponding to one of said (J+1) bus nodes, for setting potential level of corresponding said bus node to a prescribed potential when data is input to/output from none of said plurality of circuit blocks; J repeater circuits provided between adjacent said bus nodes respectively, each repeater circuit having a first signal transmitting circuit transmitting data from one to the other of said adjacent bus nodes, and a second signal transmitting circuit transmitting data from said the other to said one of said adjacent bus nodes; and an arbiter circuit receiving circuit block information for specifying a circuit block which is an object of data output, and controlling activation of said first and second signal transmitting circuits, said arbiter circuit activating, when said data is input to/output from none of said plurality of circuit blocks, either one of said first and second signal transmitting circuits in each repeater circuit, so that potential level of said bus node corresponding to said potential fixing circuit is transmitted to said data bus entirely.