Patent ID: 7391638

Claim:
A memory device having an array of memory elements accessible via at least one bitline and at least one wordline, comprising: a first field-effect transistor having first, second and third terminals, the first terminal connected to a first potential; a second field-effect transistor having first, second and third terminals, the first terminal connected to the second terminal of said first field-effect transistor, and the second terminal connected to a bitline; a memory element connected to a wordline and to the bitline; a third field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a first node, and the third terminal connected to the third terminal of the first field-effect transistor; a fourth field-effect transistor having first, second and third terminals, the first terminal connected to the first node, the second terminal connected to a second potential; a fifth field-effect transistor having first, second and third terminals, the first terminal connected to a first current source, the second terminal connected to the second potential, and the third terminal is connected to the third terminal of the fourth field-effect transistor, the first terminal further being connected to the third terminal; a sixth field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a second node, and the third terminal connected to the third terminal of the first field-effect transistor; a seventh field-effect transistor having first, second and third terminals, the first terminal connected to the second node, the second terminal connected to the second potential; an eighth field-effect transistor having first, second and third terminals, the first terminal connected to a second current source, the second terminal connected to the second potential, and the third terminal is connected to the third terminal of the seventh field-effect transistor, the first terminal further being connected to the third terminal; program control circuitry connected to the second node; and a ninth field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to the third terminal of the first field-effect transistor, and the third terminal connected to the program control circuitry, wherein the third terminal of the second field-effect transistor is connected to the first node.