Patent ID: 7284097

Claim:
In a data processing system having a coherent memory hierarchy that includes a memory and a plurality of caches each assigned to particular ones of a plurality of devices that generate cache access operations, a method of maintaining cache coherency comprising: generating a first-type address operation for a speculatively-issued cache line overwrite operation; speculatively issuing the first-type address operation for sole ownership of the cache line; when a first device issues the first-type address operation, which operation requests sole ownership of a cache line and indicates that said first device intends to overwrite the cache line in a first cache, changing a coherency state of the cache line within said first cache to a first coherency state, which indicates that the first device has sole ownership of the cache line AND may not overwrite the cache line, wherein said first-type address operation further causes a second device that has a most coherent copy of the cache line to not issue the most coherent copy of the cache line on the system bus; in response to snooping said first-type address operation, changing a coherency state of the cache line in a second cache associated with a snooping device to a second state without sending data from said cache line in the second cache to the first cache, wherein a default response to a snoop of a different-type address operation requesting the cache line automatically triggers a return of the cache line from the second cache when the second cache has the most coherent copy of the cache line; wherein sole ownership of said cache line is provided to said first device without data being sourced to said first cache from another cache; and determining whether said cache line overwrite operation was correctly speculated, wherein said first coherency state is changed to another coherency state depending on whether said cache line overwrite operation was correctly speculated, and when said operation was correctly speculated: determining that said cache line overwrite operation was correctly speculated; initiating a write of said cache line with data provided by said first device; and changing said first state to a third state indicating that a most coherent copy of said data exists within the cache line of the first cache.