Patent ID: 6867082

Claim:
A method of fabricating nonvolatile memory cells comprising: forming a device isolation layer at a predetermined region of a semiconductor substrate to define a plurality of parallel active regions; selectively etching a portion of each of the active regions to form cell trench regions, the respective cell trench regions including a pair of first sidewalls being parallel with the direction that crosses the active regions, a pair of second sidewalls being parallel with the active regions, and a bottom surface; forming insulated floating gates on the first sidewalls; selectively etching the device isolation layer between the cell trench region to form source line trench regions between the cell trench regions; forming source regions at the bottom surfaces of the cell trench regions; forming a sidewall insulation layer on sidewalls of the floating gates; forming common source lines in the cell trench regions between the floating gates and in the source line trench regions, the common source lines being electrically connected to the source regions and crossing the active regions; forming insulated word lines covering the active regions adjacent to the floating gates and being parallel with the common source lines; and forming drain regions in the active regions adjacent to the word lines, the drain regions being located opposite the common source lines.