Patent ID: 7348805

Claim:
A chip-to-chip digital transmission circuit, comprising: a differential driver portion, comprising a pull up device configured between a voltage supply rail and a pair of driver side load resistors, said driver side load resistors connected to opposing legs of the differential driver portion, a pair of driver pull down devices connected to the opposing legs of the differential driver portion, wherein gate terminals of the pair of driver pull down devices comprise the driver side input node, and a first adjustable current source configured to provide current through a conducting one of the opposing legs of the driver portion; a pair of differential signal transmission lines connected to the driver portion; a receiver portion connected to the transmission lines, an output node of which substantially reproduces a digital bit stream originally presented to a driver side input node, wherein the receiver portion further comprises a pair of impedance matching load resistors connected at first ends thereof to a corresponding one of the differential signal transmission lines, said pair of impedance matching load resistors connected to one another at second ends thereof so as to define a common mode voltage node, a pair of common mode voltage load resistors coupled at first ends thereof to the common mode voltage node, and at second ends thereof, to a pair of receiver pull down devices in opposing legs of the receiver portion, the pair of receiver pull down devices having gate terminals capacitively coupled to the differential signal transmission lines, and a second adjustable current source configured to provide current through a conducting one of the opposing legs of the driver portion; wherein the transmission lines carry both transmitted signal information and DC power for the receiver portion, and wherein the voltage of the common mode voltage node is adjustably controlled by the pull up device of the differential driver portion.