Patent ID: 8859348

Claim:
A method for fabricating field effect transistors, the method comprising: patterning a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region comprising at least a first portion of the strained silicon layer; patterning the strained silicon layer into at least one PFET region comprising at least a second portion of the strained silicon layer; forming a masking layer over the first portion of the strained silicon layer; transforming, after forming the masking layer and while maintaining at least a top portion of the second portion of the strained silicon layer exposed, the second portion of the strained silicon layer into a relaxed silicon layer; epitaxially growing, after the second portion of the strained silicon layer has been transformed into the relaxed silicon layer, a silicon germanium layer on the relaxed silicon layer; and transforming, while maintaining at least a top surface of the silicon germanium layer exposed, the relaxed silicon layer and the silicon germanium layer into a strained silicon germanium layer.