Patent ID: 8028214

Claim:
A low density parity check codes decoder for decoding a low density parity check code constituted by a base matrix of Mb (where Mb<=Mbmax) rows and Nb (where Nb<=Nbmax) columns and a permutation matrix of R rows and R columns as an element of said base matrix, comprising: Nbmax data storage and column processing calculation sections for taking in and storing channel data in parallel and executing parallel column processing for permutation matrices on the same row of the base matrix in accordance with a Belief Propagation (BP) algorithm; a row processing calculation section for receiving column processing results of said all data storage and column processing calculation sections and executing row processing in accordance with the BP algorithm; and a decoding control section for dividing inputted channel data per permutation matrix size R, giving the data to said respective data storage and column processing calculation sections, then generating column addresses corresponding to said respective data storage and column processing calculation sections and a row address common to said all data storage and column processing calculation sections, giving the column addresses to said respective data storage and column processing calculation sections, letting said data storage and column processing calculation sections iterate row processing and column processing in accordance with the BP algorithm, and generating decoding data based on log likelihood ratios for said all data storage and column processing calculation sections at the time when the number of times of decoding iteration reaches a predetermined number of times, said decoding control section including: a parity check matrix information storing section for storing Mbmax×Nbmax validity/invalidity flags and shift amounts of permutation matrices that are cyclic shift matrices, each of whose validity/invalidity flag is valid, determined depending on a check matrix for a processing target low density parity check code; a permutation matrix size storing section for storing a permutation matrix size R in the processing target low density parity check code; and a base matrix row number storing section for storing the number of rows of a base matrix Mb in the processing target low density parity check code, wherein said column addresses and said row address are generated by utilizing said validity/invalidity flags, said shift amounts, said permutation matrix size, and said number of rows of a base matrix, wherein at least either each of said data storage and column processing calculation sections or said row processing calculation section has an invalidation means for invalidating processing in accordance with said invalid validity/invalidity flags.