Patent ID: 8849881

Claim:
A logic circuit for computing first and second modal interval (MI) result values of at least first and second different MI functions responsive to respectively, first and second values of a selector signal, said computing based on at least one MI operand value encoded in an operand signal, each MI value comprising first and second multi-bit set theoretical numbers (STN) defining first and second end points of a range of real numbers, and further encoding one of the universal and existential quantification values, comprising: a) at least first and second arithmetic functional units (AFUs) each connected to receive the operand signal, and performing an arithmetic operation using as the arguments therefor, each MI operand value encoded in the operand signal, and respectively providing the first and second MI result values in first and second result signals; b) a multiplexer having a selector input receiving the selector signal, having a multibit output port for providing an output signal encoding a MI result value, and having at least first and second multi-bit input ports, said first and second input ports connected to receive respectively the first and second result signals provided as the operand signals by the first and second AFUs, and each input port associated with a single selector signal value, said multiplexer supplying, encoded in an output signal provided by the output port, the MI result value provided at the input port thereof associated with the current selector signal value; and c) a result register for storing each MI result value, and connected to receive the values respectively provided by the multiplexer output port.