Patent ID: 7397292

Claim:
A circuit for deglitching and delaying a digital signal, comprising: a slow-charge circuit configured to receive the digital signal and provide a first signal at a first node in response to a transition in the digital signal, wherein the digital signal includes at least one glitch; a fast comparator circuit coupled to the slow-charge circuit at the first node, wherein the fast comparator circuit is configured to transition an output signal in response to the first signal reaching a predetermined threshold; a first switch coupled to the first node, wherein the first switch is configured to reset the first signal to an initial value after each glitch in the digital signal, wherein the first switch includes a first pair of serially coupled transistors configured to provide the high supply voltage to the first node, a first inverter coupled between an input node and a gate of one of the first pair of transistors, and a second inverter coupled between an output node and a gate of another of the first pair of transistors; and a second switch coupled to the first node, wherein the second switch is configured to set the first signal to a high supply voltage value when the output signal and the digital signal are both at a high level.