Patent ID: 7642649

Claim:
A semiconductor device comprising: a substrate; a plurality of substantially non load bearing inter-level dielectric (ILD) layers each formed of a dielectric material having a low dielectric constant (k); at least one load bearing support structure disposed in each of the ILD layers at locations overlying each other so that the support structures are vertically aligned with each other through the plurality of layers to mitigate structural damage of the plurality of ILD layers caused by stresses to the plurality of ILD layers; at least one additional ILD layer having a dielectric constant which is higher than the plurality of ILD layers, the at least one additional ILD layer overlying the plurality of ILD layers; and a bond pad overlying the at least one additional ILD layer and the support structures, each of the vertically aligned load bearing support structures substantially aligned with a center axis of the bond pad; wherein the at least one support structure is a plurality of support structures, the plurality of support structures being located directly underneath the bond pad.