Patent ID: 7733145

Claim:
A nonvolatile latch circuit comprising: an input node receiving an input signal; a first gate part controlling to load or intercept the input signal based on a first gate signal; a first logic gate connected to a driving power supply and a grounding power supply, and having a first input terminal to receive the input signal and a second input terminal to receive a first control signal, the first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate connected to the driving power supply and the grounding power supply, and having a first input terminal to receive the output of the first logic gate and a second input terminal to receive the first control signal, the second logic gate functioning as an inverter or a gate outputting the constant voltage in response to the first control signal; a second gate part controlling to load or intercept the output of the second logic gate based on an inverted signal of the first gate signal and sends the output of the second logic gate to the first input terminal of the first logic gate; a first spin injection type MTJ element provided between the driving power supply and the first logic gate and changing in resistance depending upon a current flow direction; a second spin injection type MTJ element provided between the driving power supply and the second logic gate and changing in resistance depending upon the current flow direction; a third gate part having an input terminal to receive a data write signal and an output terminal connected to a node between the first spin injection type MTJ element and the first logic gate, and controlling to load or intercept the data write signal based on a second gate signal different from the first gate signal; a fourth gate part having an input terminal to receive an inverted signal of the data write signal and an output terminal connected to a node between the second spin injection type MTJ element and the second logic gate, and controlling to load or intercept the inverted signal of the data write signal based on the second gate signal; a first output node outputting the output of the second logic gate as an output signal; a second output node outputting the output of the first logic gate as an inverted signal of the output signal; and a first transistor short-circuiting the first and second spin injection type MTJ elements to the driving power supply based on the first control signal; and second and third transistors short-circuiting terminals of the first and second logic gates to the driving power supply based on a second control signal.