Patent ID: 7055069

Claim:
An integrated circuit (“IC”) package, comprising: a plurality of input/output (“I/O”) pins; at least one no-connect (“NC”) pin; a resident IC configured to process data; an I/O buffer circuit having a plurality of data paths, each data path providing a data connection between and I/O node of the resident IC and a corresponding I/O pin; and a spare I/O buffer circuit having: a pin selection circuit configured to generate a pin selection signal associated with a data path of the I/O buffer circuit, the pin selection circuit including a memory configured to store the address of a data path of the I/O circuit to be replaced, and a demultiplexer circuit coupled with the memory and configured to provide the pin selection signal to at least one of the multiplexer circuits of the I/O path converter circuit being associated with a data path to be replaced, and an I/O path converter circuit configured to couple an I/O node of the resident IC with the NC pin in response to the pin selection signal, the I/O path converter circuit including a multiplexer circuit associated each with data path of the I/O circuit, the multiplexer circuit having a first input coupled with the NC pin, a second input coupled with the associated data path of the I/O circuit, and an output coupled with the associated an I/O node of the resident IC, wherein the multiplexer circuit couples the NC pin to the I/O node in response to the pin selection signal.