Patent ID: 8482058

Claim:
A semiconductor device including a power MISFET, comprising: a semiconductor substrate; a gate insulating film of the power MISFET formed over the semiconductor substrate; a gate electrode of the power MISFET formed over the gate insulating film; a first impurity region of a first conductive type formed in the semiconductor substrate and formed at one side of the gate electrode; a second impurity region of the first conductive type formed in the semiconductor substrate and formed at the other side of the gate electrode; a channel region of a second conductive type opposite to the first conductive type formed in the semiconductor substrate, formed under the gate electrode and formed between the first and second impurity regions; and an offset region of the first conductive type formed between the channel region and the first impurity region and having lower impurity concentration than the first impurity region, wherein an interlayer insulating film is formed over the semiconductor substrate, wherein a first plug is formed in the interlayer insulating film and is connected with the first impurity region, wherein a second plug is formed in the interlayer insulating film and is connected with the second impurity region, wherein a first wiring is formed over the interlayer insulating film and is connected with the first plug, wherein a second wiring is formed over the interlayer insulating film and is connected with the second plug, wherein a field plate is formed over the interlayer insulating film and is arranged over the offset region in planar view, and wherein the field plate and the second wiring are electrically connected to each other and are formed in the same wiring layer.