Patent ID: 7531445

Claim:
A method of providing through-wafer interconnections in a semiconductor wafer having first and second sides, the method comprising: etching the second side of the wafer to form one or more micro-vias; providing an etch stop layer over the second side, wherein the etch stop layer covers surfaces in the one or more micro-vias; etching the first side of the wafer to form a cavity in the wafer to a depth that exposes portions of the etch stop layer on the surfaces of the one or more micro-vias; depositing metallization over one of the first and second sides of the wafer; subsequently removing regions of the etch stop layer from areas corresponding to where the one or more micro-vias were etched; and depositing metallization over the other one of the first and second sides of the wafer so that the metallization deposited over the first side is in contact with the metallization deposited over the second side to form the through-wafer interconnections in areas corresponding to where the one or more micro-vias were etched.