Patent ID: 7514978

Claim:
A system for receiving digital data, the system comprising: (a) an input buffer including at least a first differential amplifier; (b) a comparator, and (c) a compensation mechanism separate from said comparator, wherein respective differential outputs of said first differential amplifier are drivingly connected to corresponding inputs of said comparator, and wherein respective outputs of said compensation mechanism are also drivingly connected to corresponding said inputs of said comparator, said outputs of said compensation mechanism being operational to drive corresponding compensation currents into said respective inputs of said comparator so as to substantially cancel an offset voltage of said differential amplifier, and wherein said compensation currents are determined using feedback from said comparator after application of power to the system, and wherein said compensation mechanism includes: (i) a first resistor; (ii) a second resistor; (iii) a current source; (iv) a first voltage multiplexer, and (v) a second voltage multiplexer, wherein a first terminal of said first resistor is connected to a voltage source, a second terminal of said first resistor is connected to a first terminal of said second resistor, a second terminal of said second resistor is connected to said current source, said first terminal of said second resistor is also connected to a first terminal of said first voltage multiplexer and to a first terminal of said second multiplexer, said second terminal of said second resistor is connected to a second terminal of said first multiplexer and to a second terminal of said second multiplexer, and wherein a control input of said first multiplexer is operated in a complementary fashion to operation of a control input of said second multiplexer, and wherein outputs of said multiplexers are drivingly connected to said outputs of said compensation mechanism.