Patent ID: 8154108

Claim:
A dual-leadframe multi-chip package, comprises: a first leadframe and a second leadframe, whereas the first leadframe comprising a first die pad and multiple outer pins, whereas the second leadframe comprising a second die pad and a three-dimensional connecting plate formed as an integrated body with the second die pad; a first semiconductor chip mounted on the first die pad with a bottom contact area of the first chip electrically connecting to the first die pad, a second semiconductor chip mounted on the second die pad with a bottom contact area of the second chip electrically connecting to the second die pad; wherein the three-dimensional connecting plate electrically connecting a first top contact area of the first chip to the second die pad therefore establishing an electrical connection between the first top contact area of the first chip and the bottom contact area of the second chip, and a top connecting plate electrically connecting a top contact area of the second chip to an outer pin of the first leadframe.