Patent ID: 7420430

Claim:
A method for generating an output clock signal with adjustable phase relation, comprising: a) receiving a plurality of originating input clock signals, the plurality of originating input clock signals being of any one of a plurality of arbitrary waveforms, the plurality of originating input clock signals having a predetermined phase relationship with each other; b) forming a plurality of input clock signals having non-arbitrary waveforms from the plurality of originating input signals; c) weighting the plurality of input clock signals with respective weighting factors corresponding to a select phase relation; d) adding the weighted input clock signals to generate a summation clock signal; e) integrating the summation clock signal; f) amplifying the integrated summation clock signal such that the output clock signal adopts a saturation value at absolute values of the integrated summated clock signal that are smaller than an absolute value of a maximum value of the integrated summated clock signal; and g) generating the output clock signal using the amplified integrated summation clock signal.