Patent ID: 8069400

Claim:
A communication device, comprising: a processing module; and a memory, coupled to the processing module, that is operable to store operational instructions that enable the processing module to: encode information bits in accordance with a first constituent code thereby generating systematic bits and first redundancy bits; interleave the information bits in accordance with a quadratic polynomial permutation (QPP) interleave thereby generating interleaved information bits; encode the interleaved information bits information bits in accordance with a second constituent code thereby generating second redundancy bits; and apply circular buffer rate matching to at least one of the systematic bits, the redundancy bits, and the second redundancy bits using thereby generating an encoded block; and wherein: the encoded block undergoes modulation to generate a turbo coded signal that comports with a communication channel; the turbo coded signal is launched into the communication channel; and the circular buffer rate matching is operable to employ an offset index, δ, of 3 and a skipping index, σ, of 3.