Patent ID: 7060584

Claim:
A method of forming a capacitor in an integrated circuit comprising: (a) forming a lower electrode layer on a semiconductor body; (b) forming a dielectric layer over a portion of said lower electrode layer; (c) forming an upper electrode layer over a portion of said dielectric layer; (d) removing a portion of said upper electrode layer to expose a portion of said dielectric layer, thereby forming an upper electrode with a lateral boundary, wherein a portion of said dielectric layer is disposed in an inter-electrode region, said inter-electrode region disposed within said lateral boundary of said upper electrode and between said lower electrode layer and said upper electrode; (e) subsequently removing a portion of said exposed portion of said dielectric layer to expose a portion of said lower electrode layer, wherein a portion of said dielectric layer is removed from said inter-electrode region; (f) subsequently forming a conformal insulating layer over a portion of said exposed portion of said lower electrode layer proximate to said portion of said dielectric layer disposed in said inter-electrode region, whereby a portion of conformal insulating layer is formed in said inter-electrode region; and (g) forming an anti-reflective layer (ARL) for use in a photolithographic process over a portion of said conformal insulating layer.