Patent ID: 7786604

Claim:
A semiconductor device package having a first side, a second side, a third side, and a fourth side, the semiconductor device package comprising: a first leadframe; a first semiconductor die having a first drain region attached on the first leadframe, a first source region, and a first gate region; a second leadframe electrically insulated from the first leadframe and electrically connected to the first source region; a second semiconductor die having a second drain region attached on the second leadframe, a second source region, and a second gate region; a first pin bonded directly to the first leadframe; a second pin bonded directly to the first gate region; a third pin bonded directly to the second leadframe; a fourth pin bonded directly to the second source region; and a fifth pin bonded directly to the second gate region; wherein the first and fourth pins are on the first side of the semiconductor device package, and the second, third and fifth pins are on the second side of the semiconductor device package.