Patent ID: 8379000

Claim:
A digital-to-analog converting circuit comprising: a decoder that selects, responsive to an input digital signal, first and second voltages out of a plurality of reference voltages that differ from one another; and an amplifying circuit that receives the first and second voltages selected by the decoder and that outputs an output voltage level obtained by interpolating the first and second voltages, wherein the plurality of reference voltages are grouped into first to (S+1)th reference voltage groups, where S is an integer that is a power of 2 and greater than or equal to 4, wherein the first to (S+1)th reference voltage groups are respectively assigned to rows and orderings of the reference voltages, which belong to each of the reference voltage groups, within the each of the reference voltage groups being respectively assigned to columns, thereby forming a two-dimensional array of (S+1) rows and h columns, where h is an integer greater than or equal to 2, wherein an array element of an ith row and jth column in the two-dimensional array, where i is an integer greater than or equal to 1 and less than or equal to (S+1) and j is an integer greater than or equal to 1 and less than or equal to h, corresponding to a [(j−1)−S+i]th reference voltage, and wherein the decoder includes: first to (S+1)th subdecoders provided in correspondence with the first to (S+1)th reference voltage groups, the first to (S+1)th subdecoders selecting from the reference voltages of the first to (S+1)th reference voltage groups, reference voltages assigned to a column in the two-dimensional array, the column corresponding to a value of a first bit group on an upper bit side of an input digital signal; and an (S+1)-input and 2-output type subdecoder which receives outputs from the first to (S+1)th subdecoders, and which selects and outputs the first and second voltages, out of the reference voltages selected respectively by the first to (S+1)th subdecoders, in accordance with a value of a second bit group on a lower bit side of the input digital signal.