Patent ID: 7733152

Claim:
A method of utilizing a clock signal generating circuit, said clock signal generating circuit comprising: a pulse delay circuit comprising a plurality of delay elements sequentially connected in a ring configuration and configured to successively transfer a pulse signal through said delay elements, with traversal signals being thereby successively produced by said delay elements; period measurement circuitry coupled to receive a reference signal having a predetermined fixed value of period, configured to detect said value of period of the reference signal as a number of stages of said delay elements that are traversed by said pulse signal and for generating period data expressing said value of period in units of an average delay time of said delay elements; a register having stored therein a predetermined set value; control circuitry configured to multiply said period data by said set value when a value of period of said clock signal is required to be determined by frequency division of said reference signal and to divide said period data by said set value when said value of period of the clock signal is required to be determined by frequency multiplication of said reference signal, for thereby obtaining control data expressing said required value of clock signal period; and output circuitry configured to generate said clock signal based on said traversal signals, with said clock signal having said value of period that is expressed by said control data; wherein said method comprises utilizing a real number as said set value; obtaining said control data as a real number comprising an integer part and a fractional part; during each period of said clock signal, selectively performing a first adjustment operation of setting a selection value as said integer part of said control data and a second adjustment operation of setting said selection value as said integer part incremented by one, with a ratio of occurrences of said first adjustment operation to occurrences of said second adjustment operation being determined based on said fractional part of the control data; selecting a specific one of said delay elements in accordance with said selection value; and generating said clock signal based on respective timings of traversal signals produced from successively selected delay elements.