Patent ID: 8866556

Claim:
An electronic circuit, comprising: a phase lock loop circuit including a feedback path that flows from an output of an oscillator of said phase lock loop circuit to a first input of a phase detector of said phase lock loop circuit, said feedback path including a first phase shift circuit and a first divider, said first divider between said first phase shift circuit and said first input of said phase detector, said first phase shift circuit to shift a digital feedback signal's phase in one or more increments of said digital feedback signal's cycle time such that said shift of said digital feedback signal's phase is substantially not a function of manufacturing process variations and is substantially not a function of voltage and temperature variations; a reference path that flows into a second input of said phase detector of said phase lock loop circuit, said reference path including a second phase shift circuit and a second divider, said second divider between said second input of said phase detector of said phase lock loop circuit and said second phase shift circuit, said second phase shift circuit to shift a digital reference signal's phase in one or more increments of said digital reference signal's cycle time such that said shift of said digital reference signal's phase is substantially not a function of manufacturing process variations and is substantially not a function of voltage and temperature variations; and, a phase shift control signal feedback path that flows from said output of said oscillator into respective phase shift control inputs of said first and second phase shift circuits, the phase lock loop circuit including the feedback path, the reference path and the phase shift control signal feedback path to adjust a phase of a signal at said output of said oscillator in an increment less than a cycle time of said signal at said output of said oscillator responsive to said signal at said output of said oscillator, said increment being a function of a steady state difference between said digital feedback signal's cycle time and said digital reference signal's cycle time wherein said increment is substantially not a function of manufacturing process variations and is substantially not a function of voltage and temperature variations.