Patent ID: 6998924

Claim:
A synthesizer comprising: a phase lock loop circuit; a microcontroller, coupled to and configured for optimizing a bandwidth characteristic of said phase lock loop over a range of variable output frequencies; said microcontroller further configured for carrying out a self-calibration procedure for said phase lock loop; said self-calibration procedure involving a monitoring of a tune voltage for a voltage-controlled oscillator and manipulation of inputs into said chase lock loop circuit; wherein said inputs include a variable loon division ratio; an integrator within said phase lock loop circuit; wherein said microcontroller computes an integrator gain for said integrator and a tune sensitivity characteristic for said voltage controlled oscillator; wherein said integrator further comprises an integrator op-amp, an integrator resistor and an integrator capacitor; and further comprising a multiplexer for providing variable resistance paths into a first input of said op-amp, where said multiplexer is controlled by said microcontroller.