Patent ID: 7106109

Claim:
A biasing circuit receiving an input current and a reference voltage, the biasing circuit, comprising: a delay circuit, having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, an output terminal, wherein the first input terminal is adapted for receiving the input current, the second input terminal is grounded, the third input terminal is adapted for receiving the reference voltage; a compensation circuit, coupled to the output terminal of the delay circuit, for outputting a compensation voltage according to a differential voltage at the output terminal of the delay circuit; and a comparison circuit, having a first input terminal, a second input terminal and an output terminal, the first input terminal of the comparison circuit coupled to a node between the compensation circuit and the output terminal of the delay circuit to receive the compensation voltage, the second input terminal of the comparison circuit receiving the reference voltage, the comparison circuit comparing the compensation voltage and the reference voltage to output a comparison signal from the output terminal of the comparison circuit to the fourth input terminal of the delay circuit, wherein the delay circuit outputs the differential voltage from the output terminal of the delay circuit according to the input current and the comparison signal.