Patent ID: 7555631

Claim:
A microprocessor for executing a set of instructions, comprising: a register file including a first plurality of registers and a second plurality of registers; a first functional unit that executes an integer operation in response to a first instruction, wherein said first instruction specifies a register to access within said first plurality of registers or said second plurality of registers, and wherein said first functional unit is adapted to access said first plurality of registers or said second plurality of registers as specified by said first instruction, to read an integer operand from either said first plurality of registers or said second plurality of registers as specified by said first instruction, and to write a result value to said first plurality of registers or said second plurality of registers as specified by said first instruction; and a second functional unit that executes a floating point operation in response to a second instruction, wherein said second instruction specifies a register to access within said second plurality of registers, and wherein said second functional unit is adapted to access said second plurality of registers as specified by said second instruction, to read a floating point operand from said second plurality of registers as specified by said second instruction, and to write a result value to said second plurality of registers as specified by said second instruction.