Patent ID: 7911221

Claim:
A semiconductor device comprising: a first logic circuit; a second logic circuit disposed in a subsequent stage of the first logic circuit and transmitted with first data outputted from the first logic circuit; and a speed performance measurement circuit disposed between the first logic circuit and the second logic circuit and performing speed performance measurement; wherein the speed performance measurement circuit includes a first flip flop that stores the first data in synchronization with a clock signal; a first delay circuit that delays the first data and generates second data; a second flip flop that stores the second data in synchronization with the clock signal; a comparator circuit that compares an output of the first flip flop with an output of the second flip flop; a third flip flop that stores data of an output signal from the comparator circuit in accordance with timing of the clock signal; and a fourth flip flop, wherein when an output logic state of the comparator circuit is a high level, the fourth flip flop keeps an output state at a high level until receiving a reset signal.