Patent ID: 6878596

Claim:
A method of forming a high voltage junction in a semiconductor device, comprising the steps of: forming a double diffused drain (DDD) junction in a junction region of a semiconductor substrate on which a gate oxide film and a gate electrode are stacked; exposing the double diffused drain junction at a region where a contact plug will be formed; implanting an impurity having a higher atomic weight than an impurity implanted into the double diffused drain junction and simultaneously making amorphous the double diffused drain junction up to a first depth to inhibit a diffusion of an impurity which will be implanted by a subsequent second ion implantation process, by means of a first ion implantation process, wherein the first depth is the same as or shallower than the depth of the double diffused drain junction and the amorphous region is formed within said double diffused region; implanting an impurity having a lower atomic weight than the impurity implanted by means of the first ion implantation process up to a second depth shallower than the first depth by means of a second ion implantation process so that the concentration of the impurity becomes a target value; and activating the impurities implanted into the double diffused drain junction by means of an annealing process.