Patent ID: 7340577

Claim:
A system comprising: a memory comprising: a memory controller; and a memory core interfacing with said memory controller, wherein said memory operates with a read data latency and a similar write data latency, and wherein further said memory immediately processing a read in a read-after-write situation; a control circuit for controlling said memory, said control circuit for detecting an address collision based on bank and column bits between said read and a previously issued write and, in response thereto, said control circuit for stalling said memory by delaying issuance of said read to said memory until after said previously issued write completes, and wherein said address collision is detected by using pointers to hashed address values of said read and said previously issued write; a history buffer for storing a plurality of previously issued writes and a plurality of write enables corresponding to said previously issued writes, said history buffer adjustable in accordance with said stalling such that each of said plurality of previously issued writes is within a window of N clock cycles before said read.