Patent ID: 7760799

Claim:
Circuitry for controlling the amount of gain provided to a data signal that has experienced attenuation, the circuitry comprising: an equalization stage configured to provide a gain to the data signal, wherein the gain is responsive to a control signal; a comparator configured to produce an output that indicates whether the gain is less than or more than the amount of gain that is necessary to compensate for the attenuation of the data signal; a counter configured to adjust a counter value based on the output of the comparator; hysteresis circuitry configured to selectively apply a clock signal to the counter; and a digital-to-analog converter configured to produce the control signal based on the counter value; wherein: the hysteresis circuitry controls application of the clock signal to the counter, to adjust the counter value at certain transitions in the clock signal, based on the output of the comparator over a predetermined plurality of clock cycles prior to application of the clock signal to the counter.