Patent ID: 8131975

Claim:
An integrated circuit comprising: a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch configured to direct inter-processor communications within the microprocessor matrix; and a mapping unit configured to generate a data switch functionality map for a plurality of data switches in the microprocessor matrix by sending a first message through the microprocessor matrix, upon receiving a reply to the first message from a first data switch through the microprocessor matrix, setting a first functionality status designation for the first data switch in the data switch functionality map, wherein the first functionality status designation for the first data switch is an enabled or disabled status designation for an entire inter-processor message category selected from a group consisting of all messages, broadcast messages, and processor-to-processor messages; and setting a second functionality status designation for a second data switch upon failing to receive a reply from the second data switch within a predetermined period.