Patent ID: 8901607

Claim:
A semiconductor device comprising: a substrate having an N-type field-effect transistor (N-FET) region; a gate region in the N-FET region; source and drain (S/D) regions separated by the gate region in the N-FET region; a first portion of a fin structure in the gate region of the N-FET region, the first portion of the fin structure including: a first semiconductor material layer as a lower portion of the first portion of the fin structure; a semiconductor oxide layer as a middle portion of the first portion of the fin structure; and a second semiconductor material layer as an upper portion of the first portion of the fin structure; a second portion of the fin structure in the S/D regions of the N-FET region, the second portion of the fin structure including: the first semiconductor material layer as a lower portion of the second portion of the fin structure; the semiconductor oxide layer as a first middle portion of the second portion of the fin structure, wherein the first middle portion of the second portion of the fin directly contacts the middle portion of the first portion of the fin structure in the gate region; the first semiconductor material layer as a second middle portion beside the first middle portion of the second portion of the fin structure; and the second semiconductor material layer as an upper portion of the second portion of the fin structure; source/drain features on top of the upper portion of the second portion of the fin structure in the source/drain region; and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first portion of the fin structure in the gate region.