Patent ID: 7365667

Claim:
An analog-to-digital converter circuit, comprising: an analog loop filter; a quantizer having an input coupled to an output of said analog loop filter; a digital low-pass filter having an input coupled to an output of said quantizer and an output for providing an output of said analog-to-digital converter circuit; sample rate selection logic for receiving a selection corresponding to one of a higher sample rate and a lower sample rate of said output of said analog-to-digital converter; and control logic, coupled to said sample rate selection logic, wherein in response to selection of said higher sample rate, provides substantially continuous clock signals at a sampling clock rate to said quantizer, and wherein in response to selection of said lower sample rate, provides periodic bursts of said clock signals at said sampling clock rate to said quantizer and resets said analog loop filter prior to each of said periodic bursts, whereby power consumption of said analog-to-digital converter is reduced when said lower sample rate is selected.