Patent ID: 8399932

Claim:
A semiconductor device, comprising: a silicon substrate; an element isolation region formed in the silicon substrate; an element region including a first well having a first conductivity type; a contact region having the first conductivity type, the element region and the contact region being defined by the element isolation region; a gate electrode formed on the silicon substrate via a gate insulating film and extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region formed in the first well and having a second conductivity type that is opposite to the first conductivity type; a drain diffusion region formed in the first well and having the second conductivity type; a first insulating region formed in the silicon substrate and disposed to contact a lower end of the source diffusion region; a second insulating region formed in the silicon substrate and disposed to contact a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region, wherein the first well is disposed below the gate electrode between the first insulating region and the second insulating region; the first well is electrically connected with the contact region via the silicon substrate under the sub-region; upper ends of the first and second insulating regions are located higher than a lower end of the first well; lower ends of the first and second insulating regions are located lower than the lower end of the first well; a lower end of the element isolation region except the sub-region is located lower than the lower end of the first well; and the sub-region is in contact with the first and second insulating regions at a position higher than the lower end of the first well.