Patent ID: 7054898

Claim:
A processor comprising: at least one local storage designed to contain a plurality of floating point values; at least one floating point execution unit, said floating point execution unit further including a separator configured to retrieve said plurality of floating point values from said local storage and make available a mantissa portion from and corresponding to each of said plurality of floating point values, said floating point execution unit further including at least one adder unit configured to receive said mantissas in an order and number determined by said adder unit; a compare unit operatively coupled to said at least one local storage further comprising a separator configured to retrieve said plurality of floating point values from said local storage and make available at least a mantissa portion of each of said floating point values, and the compare unit configured to make available a carry-out bit value resulting from an addition of said mantissas portions; an end-around-carry bit calculator unit operatively coupled to said compare unit and configured to provide a correct value of an end-around-carry calculation available as output, based on values received from said compare unit; and a rounding calculator operatively coupled to the end-around-carry bit calculator to calculate a rounding choice upon having the adder unit complete the addition and communicating the choice to the adder unit.