Patent ID: 7307307

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate including a memory cell region and a peripheral transistor region, the memory cell region including a plurality of first element regions and a plurality of first separation regions which insulate between the first element regions, the peripheral transistor region including a plurality of second element regions and a plurality of second separation regions which insulate between the second element regions; a memory cell array formed on the memory cell region and including a memory cell having a first source region, a first drain region, a first gate insulating film having a first film thickness, a first stacked gate formed on the first gate insulating film, and a first contact member; a peripheral transistor formed on the second element region and including a second source region, a second drain region, a second gate insulating film having a second film thickness thicker than the first film thickness, and a second stacked gate; a gate barrier film covering a whole of the second stacked gate and formed integrally on the second source region and the second drain region, the gate barrier film having a third film thickness; a contact barrier film covering the gate barrier film and the second separation regions, and having a fourth film thickness, thinner than the second film thickness; and a second contact member connected to at least one of the second source and drain regions of the peripheral transistor, the second contact member contacting the gate barrier film and the contact barrier film, wherein a first upper end portion of the first separation regions protrudes from an upper surface of the semiconductor substrate and is higher than a second upper end portion of the second separation regions.