Patent ID: 7102203

Claim:
A semiconductor device comprising: a pair of source/drain regions formed on the main surface of a silicon region at a prescribed interval to define a channel region and lifted up in an elevated structure; a gate insulator film, formed on said channel region, consisting of a high dielectric constant insulator film having a dielectric constant larger than 3.9; a gate electrode including a first metal layer coming into contact with said gate insulator film and having a work function controlled to have a Fermi level around the energy level of a band gap end of silicon constituting said source/drain regions; and source/drain electrodes, formed on the upper surfaces of said pair of source/drain regions having the elevated structure to be in contact with the upper surfaces of said pair of source/drain regions without interposition of metal silicide films, including third metal layers having a work function controlled to have a Fermi level around the energy level of the band gap end of silicon constituting said source/drain regions, wherein said source/drain regions include n-type source/drain regions; said source/drain electrodes include said third metal layers having said work function controlled to have a Fermi level around the energy level of the conduction band of silicon; and said third metal layers include Hf layers.