Patent ID: 7243280

Claim:
A semiconductor circuit apparatus comprising: at least one combinational circuit for executing predetermined logical operations; at least one sequential circuit disposed at an output stage of the combinational circuit, and in a test mode supplying test data to the combinational circuit and capturing test results from the combinational circuit; and a clock enable control circuit provided at the output stage of the combinational circuit, controlling whether the enable signal is supplied to an enable terminal of the corresponding one of the sequential circuits; wherein the clock enable control circuit includes; a first OR circuit for generating an OR between an enable signal output from the combinational circuit and a substitute enable signal, wherein an external controller provides the substitute enable signal when operating in a test mode; a latch circuit for latching an output signal from the first OR circuit; and an AND circuit for generating an AND between an output of the latch circuit and the clock signal and supplying the AND as an enable clock signal.