Patent ID: 8494108

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a system clock and an Nth driving control voltage, wherein the Nth gate line is employed to transmit the Nth gate signal; a first input unit, electrically connected to the pull-up unit, for outputting the Nth driving control voltage according to an (N−1)th driving control signal and an (N−1)th gate signal of the gate signals, the first input unit comprising: a first transistor having a first end electrically connected to an (N−1)th shift register stage of the shift register stages for receiving the (N−1)th gate signal, a gate end electrically connected to the (N−1)th shift register stage for receiving the (N−1)th driving control signal, and a second end; and a second transistor having a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the Nth driving control voltage; wherein the first end of the first transistor is electrically connected to an (N−1)th shift register stage of the shift register stages for receiving an (N−1)th gate signal of the gate signals, and the gate end of the first transistor is electrically connected to the (N−1)th shift register stage for receiving an (N−1)th driving control voltage, and a high voltage level of the (N−1)th driving control voltage is higher than a high voltage level of an (N−1)th gate signal.