Patent ID: 7711976

Claim:
A data processing device formed on a one semiconductor chip, to be coupled to an external bus coupled to a synchronous dynamic random access memory including a mode register, the data processing device comprising: a first data processing module outputting both first address signals and first data; a second data processing module outputting second address signals and second data; a memory interface module coupled to receive both the first address signals and the first data from the first data processing module and to receive both the second address signals and the second data from the second data processing module and, said memory interface being capable of outputting a control signal and both the first address signals and the first data or both the second address signals and the second data to the external bus, the memory interface module being capable of outputting a mode register value to be set to the mode register in the synchronous dynamic random access memory to address terminals of the synchronous dynamic random access memory via an external address bus included in the external bus.