Patent ID: 7197581

Claim:
An integrated circuit comprising: a first bus; a processor operable to connect with said first bus; a first DMA controller operable to connect with said first bus; a second bus; a second DMA controller operable to mutually connect said first bus and said second bus; a first connecting unit comprising a first buffer memory and operable to connect with said second bus; and a second connecting unit comprising a second buffer memory and operable to connect with said second bus, wherein said first bus is further operable to connect with a first memory that is externally installed and accessible by said processor, said second bus is further operable to connect with a second memory that is externally installed, wherein said first DMA controller is operable to arbitrate data transfer between said first memory and said second memory, after requesting said second DMA controller, and wherein said second DMA controller is operable to arbitrate data transfer between said second memory and said first buffer memory and data transfer between said second memory and said second buffer memory.