Patent ID: 8010917

Claim:
A computer implemented method for utilizing locks to process circuit designs, comprising: identifying a portion of an electronic design that is to be operated upon to process the electronic design, the electronic design corresponding to multiple design layers; identifying a lock that corresponds to a purpose pair of the portion of the electronic design, the lock being a member of a set of locks that is used to lock the electronic design, the set of locks organized at levels of granularities such that the lock corresponds to its own purpose pair associated with a specific layer and a specific purpose; acquiring the lock for the purpose pair on behalf of a first processing entity, wherein there are a plurality of processing entities concurrently operating using one or more processors to process the electronic design, the lock corresponding to the purpose pair of a layer and a purpose on the layer related to the portion of the electronic design; and processing, by using the first processing entity, the portion of the electronic design once the lock has been acquired.