Patent ID: 7236002

Claim:
A circuit, capable of realizing an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range or domain for operating standard CMOS devices and a high-voltage range or domain providing voltages exceeding said standard CMOS low-voltage operating range significantly, comprising: a low-voltage circuit block being operated at said low-voltage domain and having a low-voltage input and a low-voltage output; a high-voltage input port or terminal for input signals including voltages up to said high-voltage range thus operating in said high-voltage domain; a protection switch in form of an extended-drain enhanced low-voltage CMOS FET for said high-voltage input port and designated as HV-CMOS port FET connected with its drain to said high-voltage input and with its source to said low-voltage input; a gate voltage circuit for setting the gate voltage of said HV-CMOS port FET and connected to said gate of said HV-CMOS port FET; a pull-up circuit or component for clamping the source voltage of said HV-CMOS port FET to a secure state in case said HV-CMOS port FET is switched off and thus connected to said source of said HV-CMOS port FET; an enable circuit for controlling said pull-up component for said HV-CMOS port FET and thus connected on one side to said pull-up circuit or component and on another side to enable LV circuit components; power supply terminals providing low-domain voltages for feeding said gate voltage, said enable, and said low-voltage circuit blocks as well as said pull-up circuit or component; ground terminals for said circuits and components; and the setting of said gate voltage for said HV-CMOS port FET to a value where said low-voltage input follows the voltage at said high-voltage input for voltages below values ‘gate voltage minus threshold voltage’ (Vgate−Vth) of the HV-CMOS port FET.