Patent ID: 8650355

Claim:
An apparatus comprising a 3D encapsulated integrated chip package adapted to communicate with a separate non-volatile main memory, the package comprising a first semiconductor substrate on which is formed a processing circuit, and a second semiconductor substrate affixed to the first semiconductor substrate to form an axially aligned stack of said substrates within said package, wherein a non-volatile resistive sense memory (RSM) on-chip cache memory is formed on the second semiconductor substrate, the cache memory comprising a non-volatile word memory array of RSM cells, a non-volatile index array formed of RSM cells, and a volatile index array formed of volatile memory cells, wherein the RSM cells of the non-volatile word memory array are adapted to locally cache word data which are used by the processing circuit and separately stored on the main memory, the RSM cells of the non-volatile index array are adapted to store tag data associated with the word data cached in the non-volatile word array, and the tag data are concurrently stored in the respective non-volatile index array and the volatile index array, wherein the tag data stored in the non-volatile index array are copied to the volatile index array upon a reinitialization operation, and the second semiconductor substrate does not have volatile memory cells capable of storing a copy of the word data in the non-volatile word array, wherein the cache memory is configured as an L2 cache for the processing circuit, wherein the processing circuit generates a greater amount of heat than the L2 cache, and the first and second semiconductor substrates are respectively ordered within the package to place the first semiconductor substrate closer to an external heat sink than the second semiconductor substrate, the external heat sink separate from the package and adapted to provide a primary heat conduction path to remove heat generated during operation of the package.