Patent ID: 8809933

Claim:
A semiconductor device, comprising: a substrate, having a plurality of trenches therein; a plurality of stacked gate structures, disposed on the substrate between the trenches; a plurality of doped regions, disposed in the substrate at sidewalls or bottoms of the trenches; a plurality of liner layers, disposed on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches in the substrate; a plurality of conductive layers, disposed in the trenches and a bottom of each of the plurality of conductive layers electrically connected to the doped regions, and sidewalls of the plurality of conductive layers disposed in the trench in the substrate insulated from the plurality of doped regions by the plurality of liner layers; a plurality of dielectric layers, disposed on the conductive layers and between the stacked gate structures; and a plurality of word lines, disposed on the substrate and electrically connected to the stacked gate structures.