Patent ID: 8094503

Claim:
A method of programming at least one of a plurality of memory segments in a memory array comprising a plurality of P-wells in a deep N-well within a P-type substrate, wherein each of the plurality of memory segments resides within a respective one of the plurality of P-wells, said method comprising the steps of: setting the deep N-well to a positive voltage; setting a selected one of the plurality of P-wells to a first negative voltage; setting unselected ones of the plurality of P-wells to a second negative voltage; setting a selected one of a plurality of word lines to the positive voltage; setting unselected ones of the plurality of word lines to the second negative voltage; setting a selected at least one of a plurality of bit lines to the first negative voltage; setting unselected ones of the plurality of bit lines to a third voltage; setting first source select gate lines of the selected one of the plurality of P-wells to the first negative voltage; setting first source select drain lines of the selected one of the plurality of P-wells to the first negative voltage; setting second source select gate lines of the unselected ones of the plurality of P-wells to the second negative voltage; and setting second source select drain lines of the unselected ones of the plurality of P-wells to the second negative voltage, wherein the selected at least one of the plurality of memory segments coupled to the selected one of the plurality of word lines and the selected at least one of the plurality of bit lines is programmed.