Patent ID: 7385275

Claim:
A method for forming a semiconductor structure, comprising: providing a silicon substrate; forming, within said a silicon substrate, a shallow trench isolation (STI) structure comprising a dielectric liner formed in a trench within said silicon substrate, a conductive STI fill structure formed over said dielectric layer, and a dielectric cap layer formed over and in contact with a top surface of said conductive STI fill structure; forming within said bulk silicon substrate, a first field effect transistor (FET) and a second FET, wherein said first FET comprises a channel region formed from a portion of said silicon substrate, a source structure formed adjacent to said channel region, a drain structure formed adjacent to said channel region, a gate dielectric formed over said channel region, and a gate electrode formed over said gate dielectric, wherein a bottom surface of said gate electrode is in direct physical contact with said gate dielectric, wherein said channel region comprises a first corner device and a second corner device, wherein a top surface of said channel region is located within a first plane, wherein said bottom surface of said gate electrode is located within a second plane, wherein said shallow trench isolation (STI) structure is located adjacent to and in contact with said channel region, wherein said STI structure isolates said first FET from said second FET, wherein said top surface of said conductive STI fill structure is above said first plane by a first distance D 1 and is above said second plane by a second distance D 2 that is less than D 1 , and wherein said gate dielectric is formed over and in contact with said dielectric cap layer of said STI structure.