Patent ID: 8352764

Claim:
An apparatus comprising: a squelch mode control register to enable control of power to at least one squelch detect circuit associated with an interconnect according to a first mode or a second mode, the first mode corresponding to a software mode and the second mode corresponding to a combined hardware and software mode; a second register coupled to the squelch mode control register to receive software settings to indicate which of a plurality of squelch detect circuits, each associated with a corresponding lane of the interconnect, is to be disabled in a low power state of the interconnect; a detector coupled to the squelch mode control register, the detector to dynamically detect a logical lane zero of the interconnect responsive to determination of operation in the second mode from the squelch mode control register; and a logic to combine control signals from the second register and an output of the detector in the second mode to selectively enable at least one of the squelch detect circuits in the low power state.