Patent ID: 7328314

Claim:
An apparatus comprising: a plurality of processing units; a memory structure comprising a number of simultaneously accessible memory sections, the number of memory sections being at least equal to a number of the processing units, the memory structure holding software comprising a plurality of sequential parts with the parts distributed between the memory sections such that sequential parts are in sequential memory sections; a program counter associated with each of the processing units; and, a memory section access control connected between the processing units and the memory structure, the memory section access control configured to permit, on each of a plurality of successive memory access cycles, each of the processing units to retrieve one of the parts of the software from a different one of the memory sections, the memory section access control permitting at least one of the processing units to retrieve sequential ones of the parts of the software from sequential ones of the memory sections on sequential memory access cycles, wherein the memory section access control is configured to permit each of the plurality of processing units to retrieve successive ones of the parts of the software from successive ones of the memory sections on successive memory access cycles, wherein the memory section access control comprises a plurality of input multiplexers, one of the plurality of multiplexers associated with each of the memory sections, each of the input multiplexers having a plurality of inputs connected to receive values from each of the program counters and an output connected to provide the value from one of the program counters to the associated memory section, and wherein each of the input multiplexers comprises a control input and the memory section access control is configured to provide a memory section selection value to each of the input multiplexer control inputs input in each of the memory access cycles, the memory section selection value at each of the control inputs corresponding to a different one of the processing units, the memory section selection value at each of the input multiplexer control inputs changing in each memory access cycle and cycling through values corresponding to all of the processing units.