Patent ID: 8595554

Claim:
A multiprocessor system, comprising: a single system clock; facilities for generating a plurality of system wide synchronization events; a plurality of units running in parallel, each unit being characterized by the following features: deterministic start state; at least one deterministic interface; a clock generator unit receiving a system clock, wherein all clocks within the unit are derived from the system clock and are phase aligned relative to the system clock; zero-impact communication with the other units; and facilities adapted to precisely stop the unit in conjunction with the other units of the system, said facilities comprising a local timer device in each unit coupled to said clock generator unit, said local timer device being set to a stop time threshold value and, responsive to reaching said stop time threshold value, said local timer providing a stop timer signal to said clock generator to responsively halt one or more pre-selected clocks within the unit, and extraction facilities adapted to scan system state responsive to such precise stopping.