Patent ID: 7970985

Claim:
A non-volatile memory system, comprising: a memory circuit including: a plurality of subarrays, each formed of a plurality of erase blocks each having a plurality of re-writable non-volatile memory cells; erase circuitry connectable to the erase blocks whereby the erase blocks may be selectively erased; and read and write circuitry selectively connectable to the memory cells whereby each of the subarrays is independently accessible; and a controller circuit connected to the memory circuit to manage the storage of data on the memory circuit, where the controller circuit accesses the memory circuit using multi-block composite logical structures, such that the erase blocks of the individual composite logical structures are each from a different one of the subarrays, wherein in response to the controller circuit determining that a first erase block of a corresponding composite logical structure is bad, replacing the first erase block in the corresponding logical structure with an alternate erase block from the same subarray as that of the first erase block, wherein determining that a first erase block is bad includes determining that the first erase block is defective, and wherein the first erase block has a grown defect.