Patent ID: 8339158

Claim:
A dynamic high-speed comparative latch, comprising: a pre-amplifier unit for enlarging input differential signals; a regenerating latch unit for latching outputted differential signals that come from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle; and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state, wherein the pre-amplifier unit, comprising only one input clock signal, is connected with the regenerating latch unit; and the regenerating latch unit is connected with the latch unit; wherein the regenerating latch unit consists of a FET M 7 controlled by one output node PA 1 of the pre-amplifier unit, a FET M 8 controlled by one output node NA 1 of the pre-amplifier unit, a pair of clock-controlled FET M 9 and M 10 , and a group of FET M 11 , M 12 , M 13 and M 14 ; the circuit structure is completely symmetrical.