Patent ID: 6967858

Claim:
A nonvolatile ferroelectric memory device comprising: a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells; a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column; a plurality of sub bitlines connected with one terminal of the unit cells to induce a voltage in the unit cells and arranged along the main bitlines; a sensing amplifier block comprising a plurality of sensing amplifiers comparing multiple-level signals from a main bitline and sensing them in a multiple-bit state, the sensing amplifiers being commonly used in the cell array blocks to feed the sensed multiple-bit states back and restore them in the cells; and switching transistors respectively arranged per sub bitline to current-sense multiple-level data values of the unit cells by controlling a current flow depending on multiple-level voltages induced in the sub bitline and transmitting the multiple-level voltages to the main bitlines, each of the switching transistors having a gate connected with one of the sub bitlines, a drain connected with one of the main bitlines, and a source connected with a ground voltage terminal.