Patent ID: 7315191

Claim:
A digital storage element, comprising: a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled thereto, said first transistor also coupled to a voltage source; and a slave transparent latch coupled to the master transparent latch, said slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop, said second transistor coupled to the voltage source or a different voltage source; wherein, when a clock signal is in a first state, the first single transistor is activated to reset the digital storage element; wherein, when the clock signal is in a second state, the second single transistor is activated to reset the digital storage element; a third transistor coupled to the data input port, said third transistor inactivated when the first transistor is activated, wherein the third transistor protects the digital storage element from a short circuit condition.