Patent ID: 8329523

Claim:
A method of fabricating an array substrate for a display device, comprising: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region, edge portions of the gate electrode exposed through the active layer; forming an interlayer insulating layer of an inorganic insulating material on the active layer, the interlayer insulating layer including active contact holes exposing the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer, wherein the source barrier pattern, the drain barrier pattern and the first dummy pattern include intrinsic amorphous silicon, wherein the source ohmic contact layer, the drain ohmic contact layer and the second dummy pattern include impurity-doped amorphous silicon, wherein the source and drain barrier patterns are connected to the active layer through the active contact holes, and wherein the data line is connected to the source electrode; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon, the first passivation layer and the interlayer insulating layer including a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, the gate line connected to the gate electrode through the gate contact hole and crossing the data line to define the pixel region; forming a second passivation layer on a surface of the first passivation layer including the gate line formed thereon, the second passivation layer and the first passivation layer including a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.