Patent ID: 8183631

Claim:
A semiconductor device comprising: a semiconductor substrate having an upper main surface and a lower main surface, said semiconductor substrate including: a drain layer of a first conductivity type formed in said upper main surface, a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, an underpad base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, exposed to said upper main surface and not coupled to said main base region, and a distance between said main base region and said underpad base region along said drain layer is larger than a size of said main base region, a source region of a first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface, and a peripheral base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, exposed to said upper main surface, said peripheral base region being positioned between said main base region and said underpad base region, not having a semiconductor region of a first conductivity type provided therein, and is not coupled to said underpad base region; a first main electrode connected to said main base region, said peripheral base region and said source region and not connected to said underpad base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an exposed surface of said underpad base region in said upper main surface with an insulating layer interposed therebetween and said conductive gate pad is connected to said gate electrode; a conductive layer buried in the insulating layer to be opposed to said upper main surface in a vertical position closer to the upper main surface than the conductive gate pad, the conductive layer being extended to reach a location above the peripheral base region; and a second main electrode connected to said lower main surface, wherein a maximal depth of the main base region from the upper main surface of the substrate is shallower than a maximal depth of the underpad base region.