Patent ID: 8124533

Claim:
A method of manufacturing a power semiconductor device, comprising: preparing a semiconductor substrate having one main surface and an other main surface, and including a first layer having a first conductivity type and located at a side of said one main surface; forming a mask layer having a plurality of openings on said first layer; forming a second layer having a second conductivity type different from said first conductivity type on said first layer by introducing impurities using said mask layer; forming a third layer having said first conductivity type on said second layer by introducing impurities using said mask layer; forming a trench extending through said second layer and said third layer to said first layer by carrying out etching using an etching mask including at least said mask layer; forming a gate insulation film covering a sidewall of said trench; forming a trench gate filling said trench on said gate insulation film; and after said forming said second layer, forming a sidewall film on a sidewall of said mask layer in order to narrow said plurality of openings, wherein said etching mask includes said sidewall film.