Patent ID: 7884910

Claim:
A liquid crystal display device, comprising: a gate line formed on a first substrate; first and second data lines crossing the gate line to form adjacent pixel regions in a direction of the gate line; a first pixel electrode line parallel to the first data line and spaced apart from the first data line by a first isolation distance; a second pixel electrode line spaced apart from the second data line by a second isolation distance, the second pixel electrode line being extended along the data line to be substantially parallel to the data line; a first common line parallel to the first data line and spaced apart from the first data line by a third isolation distance; a second common line spaced from the second data line by a fourth isolation distance; a plurality of pixel electrodes extended along the gate line in each pixel region, one end portion of the plurality of pixel electrodes within the pixel region being connected to one first pixel electrode line and other end portion of the plurality of pixel electrodes within the pixel region being connected to one second pixel electrode line; a plurality of common electrodes extended along the gate line in each pixel region, the common electrodes being connected to the first common line and the second common line; and an alignment film having a rubbing direction perpendicular to the first data line, wherein the first isolation distance is shorter than the second isolation distance, and a parasitic capacitance between the first pixel electrode line and the first data line is greater than a parasitic capacitance between the second pixel electrode line and the second data line, wherein the length of the first common line is substantially same as the length of the first pixel electrode line and the length of the second common line is substantially same as the length of the second pixel electrode line, wherein the first common line and the first pixel electrode line overlap each other to form a first storage capacitor and the second common line and the second pixel electrode line overlap each other to form a second storage capacitor, a first overlapped region of the first common line and the first pixel electrode line and a second overlapped region of the second common line and the second pixel electrode line being extended along the data line.