Patent ID: 7510939

Claim:
A method for fabricating a semiconductor structure comprising: forming a semiconductor fin over a substrate utilizing lithography and etching; forming a gate dielectric layer having a thickness from about 20 to about 70 angstroms on sidewalls of said semiconductor fin utilizing a thermal oxidation process; forming a patterned capping layer located aligned upon a patterned mandrel layer, said patterned mandrel, layer encapsulates a portion of the semiconductor fin and the gate dielectric layer; activating the patterned mandrel layer by treating the patterned mandrel layer with a compound containing an amine functionality; forming a spacer layer over the substrate and also adjoining a pair of opposite sidewalls of said activated patterned mandrel layer; forming a pair of gate electrodes on lateral sidewalls of said spacer layer, wherein the spacer layer is adjacent a sidewall of the gate electrode, but not completely covering a sidewall of the semiconductor fin remote from the gate electrode; and stripping the activated patterned mandrel layer.