Patent ID: 6931479

Claim:
A memory device, comprising: a plurality of address input terminals; a memory array having at least one bank of memory cells, the memory cells arranged in rows and columns of memory cells; a row address decoder coupled to the address input terminals and the memory array for selecting a row of memory cells of the bank to be accessed corresponding to a memory address provided by a first set of input signals applied to the address input terminals; a command decoder coupled to at least one of the plurality of address input terminals and the first address decoder, the command decoder generating internal command signals and providing the internal command signals to the row address decoder circuit to activate portions of the row of memory cells to be accessed, the activated portion corresponding to a selection signal applied to at least one of the address input terminals along with a second set of input signals applied to at least a portion of the remaining address input terminals, the second set of input signals having less input signals than the first set of input signals.