Patent ID: 8372732

Claim:
A method for fabricating a non-volatile memory device, comprising: alternatively stacking a plurality of interlayer dielectric layers and a plurality of gate conductive layers for memory cells on a substrate; etching the interlayer dielectric layers and the gate conductive layers for memory cells to form cell channel holes that expose the substrate; forming a protective layer along a surface of a resultant structure including the cell channel holes; forming a capping layer on the protective layer to fill the cell channel holes; planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers for memory cells is exposed; forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure including the exposed uppermost interlayer dielectric layer after the planarizing of the protective layer and the capping layer; etching the interlayer dielectric layer for select transistors and the gate conductive layer for select transistors to form select transistor channel holes that expose the capping layer while the capping layer buried in the cell channel holes is removed; and removing the protective layer.