Patent ID: 8102168

Claim:
A circuit for regulating power, comprising: a regulator controller that is arranged to perform steady-state regulation of an output power signal based, at least in part, on a reference signal, wherein the regulator controller includes: a under-voltage lock-out (UVLO) circuit that is arranged to monitor a status of an input power signal and to provide a status signal to indicate the status of the input power signal, wherein the regulator controller is arranged to be disabled while the status signal is deasserted, and wherein the UVLO circuit is further arranged to provide a UVLO reference power signal; an amplifier circuit that is arranged to receive the UVLO reference power signal and to provide a reference generator power signal; and a reference generator that is arranged to provide the reference signal such that the reference signal is maintained at a substantially constant value, wherein the reference generator is arranged to be powered from the reference generator power signal, and wherein the reference generator circuit includes at least one of a band-gap reference circuit, a Zener diode, a gas filled tube, or a digital-to-analog converter.