Patent ID: 7453760

Claim:
A method for accessing a dual-port memory connecting a first central processing unit and a second central processing unit for reading/writing data, the method comprising steps of: (a) performing a data writing process, comprising steps of: determining a data block for the first central processing unit to write a first variable data in according to a first status flag; writing the first variable data in the first data block and resetting the first status flag to indicate a second data block is busy by the first central processing unit if the first status flag indicates the first data block is busy; and writing the first variable data in the second data block and resetting the first status flag to indicate the first data block is busy by the first central processing unit if the first status flag indicates the second data block is busy; and (b) performing a data reading process, comprising steps of: determining a data block for the second central processing unit to read the first variable data from according to the first status flag; reading the first variable data from the second data block by the second central processing unit if the first status flag indicates the first data block is busy; and reading the first variable data from the first data block by the second central processing unit if the first status flag indicates the second data block is busy.