Patent ID: 7177181

Claim:
In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of: biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the memory cells comprise an amorphous solid.