Patent ID: 7191205

Claim:
A function block comprising: first to fourth multiplexers; a first exclusive OR circuit for performing an exclusive OR function on output signals of the first and second multiplexers; a second exclusive OR circuit for performing an exclusive OR function on output signals of the third and fourth multiplexers; a third exclusive OR circuit for performing an exclusive OR function on output signals of the first and second exclusive OR circuits; a 4-2 carry block for generating a 4-2 carry output signal from at least, an output signal of one of the first and second multiplexers and an output signal of one of the third and fourth multiplexers; a fifth multiplexer for selecting one of output signals of the first and second multiplexers depending on a first control signal; a sixth multiplexer for selecting one of output signals of the third and fourth multiplexers depending on a second control signal; a seventh multiplexer for selecting a signal from a first multiple-signal group including a logical input signal and a 4-2 carry input signal; an eighth multiplexer for selecting a signal from a second multiple-signal group including output signals of the sixth and seventh multiplexers; a ninth multiplexer for selecting a signal from a third multiple-signal group including a third control signal and an output signal of the third exclusive OR circuit; a tenth multiplexer which is controlled by an output signal of the ninth multiplexer and selects a signal from a fourth multiple-signal group including output signals of the fifth and eighth multiplexers to output it as a carry output signal; and a fourth exclusive OR circuit for performing an exclusive OR function on output signals of the third exclusive OR circuit and the seventh multiplexer to produce an addition output.