Patent ID: 8445948

Claim:
A semiconductor structure comprising: a semiconductor substrate; an insulator layer located on a topmost semiconductor surface of said semiconductor substrate; semiconductor nanowires located atop the semiconductor substrate and surrounded by a gate dielectric, wherein said gate dielectric includes a surface that is direct contact with an upper surface of said insulator layer; and at least one patterned gate conductor having a first portion located on top of a first segment of the semiconductor nanowires and a second portion located adjacent said first segment of semiconductor nanowires; and in contact with sidewall surfaces of said gate dielectric, wherein no residue gate material is present beneath other segments of the semiconductor nanowires and there is no consumption of the at least one patterned gate conductor, and wherein an uppermost surface of said first portion of said at least one patterned gate conductor is coplanar with an uppermost surface of said second portion of said at least one patterned gate conductor.