Patent ID: 7087489

Claim:
A method of forming a nonvolatile memory device on a semiconductor substrate with a peripheral circuit region composed of a high voltage transistor region and a low voltage transistor region and with a cell array region, comprising: forming a cell gate insulating layer in contact with the semiconductor substrate at least in the cell array region, the cell gate insulating layer composed of a lower insulating layer, a charge storage layer, and an upper insulating layer that are sequentially stacked; forming a sacrificial layer on the cell gate insulating layer, the sacrificial layer composed of at least one material having an etch selectivity with respect to the upper insulating layer; forming a photoresist pattern exposing the sacrificial layer in the peripheral circuit region; etching the exposed sacrificial region by using the photoresist pattern as an etch mask to form a sacrificial pattern covering the cell gate insulating layer in the cell array region; and simultaneously etching the cell gate insulating layer in the peripheral circuit region using the sacrificial pattern as a sacrificial etch mask.