Patent ID: 6981204

Claim:
In a data communications controller receiving asynchronous input data signals comprised of bits having a duration and varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals, a method for filtering glitches, comprising reversals of signal level superimposed on the input data signals as transmitted and having a glitch duration less than the predetermined bit period, on the input data signals, comprising the steps of: detecting glitches in the input data signals by detecting reversals of signal level during the duration of the bits and having a predetermined duration less than the predetermined input bit period; determining a glitch time value corresponding to the glitch duration; setting a sampling clock rate at a rate determined from the glitch time value; sampling the input data signals at the sampling clock rate to generate a sequence of input data samples; monitoring a predetermined voting number of input data samples and providing an output signal representing the value of a majority of the samples in the sequence of input data samples; and monitoring a voting number of subsequent input data samples and providing an output signal representing the value of a majority of those subsequent input data samples.