Patent ID: 7528641

Claim:
A delay circuit comprising: modified inverters each having first and second MOS transistors of first conduction type connected in series between a first power supply terminal to which a first power supply voltage is applied and an output node, and a third MOS transistor of second conduction type connected between the output node and a second power supply terminal to which a second power supply voltage is applied, said first and third MOS transistors each having a gate electrode connected to an input node and said second MOS transistor having a gate electrode supplied with a control signal for delay control; and a correction circuit having a fourth MOS transistor of said first conduction type and a first resistor connected in series between the first power supply terminal and an internal node used for outputting the control signal, second and third resistors connected in series between the internal node and the second power supply terminal, and a fifth MOS transistor of said first conduction type connected in parallel with the second and third resistors, said fourth MOS transistor being diode-connected in a forward direction and said fifth MOS transistor having a gate electrode connected to a connecting point of the second and third resistors.