Patent ID: 7015587

Claim:
A stacked multi-chip semiconductor package comprising: a first die having a first plurality of bond pads exposed on a first surface of the first die; a first set of electrical connectors electrically coupled to selected bond pads on the first die; a first encapsulant that covers portions of the first set of electrical connectors and completely exposes some of the bond pads of, the first die, the first encapsulant including a support surface; a second die that is supported by the support surface of the first encapsulant, the second die having a second plurality of bond pads; a second set of electrical connectors electrically coupled to selected bond pads on the second die, wherein at least one of the second set of electrical connectors electrically connects the second die directly to at least one of the exposed bond pads of the first die; and a second encapsulant that at least partially encapsulates the first and second dice, and the first and second sets of electrical connectors, whereby a stacked multi-chip semiconductor package is provided that includes a direct die to die electrical connection.