Patent ID: 7082518

Claim:
Digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means; the digital signal processing apparatus further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means, wherein in case of an interrupt the state of all of said limited subset of hardware resource means are stored within a single clock cycle using a plurality of flip-flops and all hardware resource means under control of said first instruction set means have their state frozen; and wherein at least a part of such hardware resource means which are not directly accessible and not included in said predetermined limited subset of said hardware resource means are chained together in a first scan chain means and at least a part of such hardware resources which are not directly accessible and included in said predetermined limited subset of said hardware resource means are chained together in a second scan chain means.