Patent ID: 8326904

Claim:
A computer system comprising a processor core, wherein the processor core comprises: a decoder, wherein the decoder performs a decoding of a vector instruction that comprises an operation code and a predetermined exponent adjustment value; a vector floating point execution unit coupled to the decoder, wherein the vector floating point execution unit comprises: a register file configured to store vector operands, a trigonometric functional block for determining trigonometric values of data from the vector operands, and a leading zero anticipator for detecting any zeros before a leading “1” in a mantissa of a trigonometric functional block output, wherein the leading zero anticipator outputs a dynamic shift amount that is based on how many zeros are detected before a leading “1” for each output mantissa from the trigonometric functional block outputs; a normalizer for converting each trigonometric functional block output into a normalized number, wherein the normalized number has a leading “1”; and an exponent adjustment adder coupled to the decoder and the leading zero anticipator, wherein the exponent adjustment adder uses the predetermined exponent adjustment value and the dynamic shift amount to produce an adjusted result exponent for a trigonometric output from the trigonometric functional block.