Patent ID: 8174532

Claim:
A data processing method in a video signal processor (VSP), the method comprising: receiving commands from an external signal processor; dispatching the received commands to a first separate command sequencer (PSQ), a second separate command sequencer (PSQ 2 ) and a third separate command sequencer according to different command types, the first and second separate command sequencers for performing task parallelism and the third command sequencer for performing Input/output (IO) operation; the first and second separate command sequencers packing the received commands into a plurality of instruction packets; and the first and second separate command sequencers respectively sending the instruction packets to a plurality of arithmetic function units with a first type and a plurality of arithmetic function units with a second type, wherein two of the instruction packets from the first separate command sequencer (PSQ) are dispatched and executed in the same cycle according to one of the following combinations: SPU|VALU VMAC|VALU DFXU|VALU SPU|VMAC SPU|DFXU SPU|SAD, wherein “|” means that the combination of two instruction packets, the SPU means the instruction packets for a scalar processing unit, VALU means the instruction packets for a vector arithmetic logic unit, VMAC means the instruction packets for a vector multiplication and accumulation operation unit, DFXU means the instruction packets for a data fetch and exchange unit, and SAD means the instruction packets for a sum of absolute difference Unit.