Patent ID: 7868453

Claim:
A method, comprising: forming an electrically conductive wire in an interlevel dielectric layer on a substrate; forming a dielectric passivation layer on a top surface of said wire and on a top surface of said interlevel dielectric layer; forming a first opening in said dielectric passivation layer, wherein a central region of a top surface of said wire is exposed in said first opening; forming an electrically conductive terminal pad on said central region of said top surface of said wire and on a region of a top surface of said dielectric passivation layer surrounding said first opening; forming an organic dielectric passivation layer on said dielectric passivation layer and terminal pad; forming a second opening in said organic dielectric passivation layer, a central region of a top surface of said terminal pad exposed in said second opening, said organic passivation extending over and in contact with a peripheral region of terminal pad; forming an electrically conductive current spreading pad on a top surface of said organic dielectric passivation layer, said spreading pad in contact with a central region of said terminal pad in said second opening; forming an electrically conductive solder bump pad comprising one or more layers on a top surface of said current spreading pad; and forming an electrically conductive solder bump on a top surface of said solder bump pad, said solder bump containing tin, said current spreading pad comprising one or more layers, at least one of said one or more layers consisting of a material that will not form an intermetallic with tin or at least one of said one or more layers is a material that is a diffusion barrier to tin and is a layer adjacent to said solder bump pad.