Patent ID: 7462911

Claim:
An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; a third semiconductor layer of the first conductivity type on the second semiconductor layer; trenches formed through the third semiconductor layer down to the second semiconductor layer to divide the third semiconductor layer into multiple semiconductor regions; fourth semiconductor layers of the second conductivity type selectively formed at least in the surface portions of some of the semiconductor regions; a control electrode formed in each of the trenches with an insulator film interposed between the control electrodes in the trenches; a runner on the third semiconductor layer in the active region, in which current flows in the semiconductor device, with an insulator film interposed between the runner and the third semiconductor layer, and the runner being connected electrically to the control electrodes; a first main electrode on the third and fourth semiconductor layers with an interlayer insulator film interposed between the first main electrode and the third and fourth semiconductor layers, the first main electrode being in contact with the third semiconductor layer and the fourth semiconductor layers in the semiconductor regions that have the fourth semiconductor layers formed therein, through the interlayer insulator film, and the first main electrode being in contact with the third semiconductor layer in some of the semiconductor regions that do not include any fourth semiconductor layer, via contact holes formed in the vicinities of the terminal ends of the trenches and in the vicinities of the runner through the interlayer insulator film; and a second main electrode connected electrically to the first semiconductor layer.