Patent ID: 7881894

Claim:
A method for generating a calibrated clock signal (CKU) in an integrated circuit, the calibrated clock signal being suitable for input as a clock signal to a communications interface, the calibrated clock signal (CKU) having successive active edges, wherein the method comprises the steps of: providing at least one oscillator signal (φ( 0 ) to φ( 2 i −1)) having a basic Step of Time, said oscillator signal having oscillator periods corresponding to a free running frequency; measuring an rational number of Step of Time of a bit duration inside a received flow of bits; after each generation of an active edge of the calibrated clock signal, computing an integer number and a fractional number of Step of Time that corresponds to the separation time before the next active edge; transforming the oscillator signal (φ( 0 ) to φ( 2 i −1)) into a clock signal (CK) having active edges of said clock signal in phase with at least one oscillator signal (φ( 0 ) to φ( 2 i −1)), two consecutive active edges being separated by a time duration proportional to the integer number of Step of Time; computing a time delay proportional to the fractional part of Step of Time corresponding to the fractional number of Step of Time; delaying the next active edge of the clock signal (CK) by said computed delay to produce the calibrated clock signal (CKU) wherein said next active edge being desynchronized from the at least one oscillator signal; and providing the calibrated clock signal (CKU) by clock recovery circuit to the communications interface.