Patent ID: 7248091

Claim:
A semiconductor device comprising: a delay chain coupled to receive a reference clock signal and coupled to receive a control signal for controlling the delay chain, wherein the delay chain delay the reference clock signal; a clock driver having an output port and coupled to receive an output signal of the delay chain, wherein the clock driver outputs an internal clock signal; a phase detector having input ports and coupled to receive the reference clock signal and a compensated internal clock signal, wherein the phase detector detects a difference between the phase of the reference clock signal and the phase of the compensated internal clock signal; a control circuit coupled to receive an output signal of the phase detector, wherein the control circuit generates the control signal; a feedback path between the output port of the clock driver and the input port of the phase detector, wherein the feedback path receives the internal clock signal, and outputs the compensated internal clock signal; an input and output circuit configured to receive and output data; a clock distribution path between the output port of the clock driver and an input port of the input and output circuit; a first delay drift compensation circuit formed as part of the feedback path, wherein when a power supply voltage increases the first delay drift compensation circuit reduces a delay time of the feedback path, and wherein when a temperature increases the first delay drift compensation circuit increases the delay time of the feedback path; and a second delay drift compensation circuit formed as part of the feedback path, wherein when a temperature increases the second delay drift compensation circuit increases the delay time of the feedback path.