Patent ID: 7843052

Claim:
A semiconductor device comprising: a first semiconductor die comprising: a first surface; a second surface opposed to the first surface; third surfaces perpendicular to the first surface and the second surface; and bond pads formed on the first surface; a stack of second semiconductor dies electrically interconnected to one another by electrically conductive through vias and electrically connected to the bond pads of the first semiconductor die, wherein the first semiconductor die has a larger width than the second semiconductor dies; conductive connection members comprising: first conductive connection members interposed between and electrically interconnecting the first semiconductor die and the lowest one of the second semiconductor dies; and second conductive connection members interposed between and electrically interconnecting the adjacent second semiconductor dies; an encapsulant encapsulating the first semiconductor die, the second semiconductor dies and the conductive connection members, wherein the encapsulant covers the first surface, the second surface and the third surfaces being exposed to the outside of the encapsulant, the encapsulant comprising side surfaces in a same plane as the third surfaces; redistribution layers electrically connected to the through vias of the second semiconductor dies; and solder balls electrically connected to the redistribution layers.