Patent ID: 7297588

Claim:
A process for forming an electronic device comprising: forming a gate dielectric layer over a first portion and a second portion of the substrate; forming a first layer of a gate stack over the gate dielectric layer, wherein the first layer comprises a first element that is a metallic element, and lies immediately adjacent to the gate dielectric layer over the first portion of the substrate; incorporating an impurity into the first layer after forming the first layer over the gate dielectric layer, wherein the impurity comprises a second element within Group 2 or 13 of the Periodic Table; forming a second layer of the gate stack over gate dielectric layer, wherein the second layer lies immediately adjacent to the gate dielectric layer over the second portion of the substrate, and after forming the first layer and forming the second layer, the second layer overlies the first layer over the first portion of the substrate; forming a third layer of the gate stack over the first layer and the second layer; patterning the gate stack, wherein after patterning the gate stack, a first gate electrode overlies the first portion of the substrate, and a second gate electrode overlies the second portion of the substrate; forming a first source/drain region over the first portion of the substrate, wherein after forming the first source/drain region, a first transistor lies over the first portion of the substrate and includes the first source/drain and the first gate electrode; and forming a second source/drain region over the second portion of the substrate, wherein after forming the second source/drain region, a second transistor lies over the second portion of the substrate and includes the second source/drain and the second gate electrode.