Patent ID: 7215593

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix form; a plurality of word lines connected to the memory cells; first and second address control circuits which produce first and second address signals for selecting the word lines; a signal generating circuit which is responsive to an externally applied activation signal for activating the memory cell array to produce a second signal for placing the memory cell array in an active state or a precharged state; and a row decoder including a plurality of decode sections each of which is provided for a respective one of the word lines and includes first and second MOS transistors connected in series, the first MOS transistor having its gate electrode connected to receive the first address signal, the second MOS transistor having its gate electrode connected to receive the second address signal, the row decoder outputting a first signal for controlling the word lines, wherein the first address control circuit outputs the first address signal when the activation signal is activated, and the second address control circuit outputs the second address signal when the second signal indicating the active state is activated.