Patent ID: 8271732

Claim:
An apparatus comprising: a first data array including a first plurality of entries corresponding to a first group of ways for a plurality of sets; a second data array including a second plurality of entries corresponding to a second group of ways for the plurality of sets; and a tag array addressed using a first linear address portion corresponding to a memory request to identify a set, the tag array including a plurality of entries each to store a way vector to identify a way of the first data array or the second data array of the identified set to be selected and to output a first portion of the way vector to the first data array and to output a second portion of the way vector to the second data array, wherein only the first plurality of entries corresponding to the group of ways of the first data array or the second plurality of entries corresponding to the group of ways of the second data array is to be accessed based on a second linear address portion corresponding to the memory request.