Patent ID: 8806411

Claim:
A device comprising: a circuit unit comprising; a first circuit cell array extending in a first direction, a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array, first and second power lines each of which extends in the first direction and arranged over the first circuit cell array, third and fourth power lines each of which extends in the first direction and arranged over the second circuit cell array, a first transistor coupled between the second and third power supply lines, a plurality of first logic circuits arranged in the first cell array, each of the first logic circuits includes first and second power nodes coupled respectively to the first and second power lines, a plurality of second logic circuits arranged in the second cell array, each of the second logic circuits includes third and fourth power nodes coupled respectively to the third and fourth power lines, a first interconnection connecting an output node of a first one of the first logic circuits to an input node of a first one of the second logic circuits, and a second interconnection connecting an output node of the first one of the second logic circuits to an input node of a second one of the first logic circuits.