Patent ID: 7466031

Claim:
A structure of redistributing circuit traces, comprising: a wafer having a bonding pad thereon; a passivation layer formed on said wafer, wherein said passivation layer exposes a portion of said bonding pad; a first dielectric layer formed on said passivation layer exposing said exposed portion of said bonding pad; a conductive layer comprising a first portion and a second portion, wherein said first portion of said conductive layer is on and contacted said exposed portion of said bonding pad and said first dielectric layer, said second portion of said conductive layer is on and contacted said first dielectric layer, and there is no electrical connection between said first portion and said second portion, and said second portion is a full-piece metal layer and not connected to said bonding pad; a second dielectric layer formed on said conductive layer exposing a portion of said first portion, wherein said exposed portion of said first portion is in an offset relationship with respect to said exposed portion of said bonding pad; and a conductive bump formed on said exposed portion of said first portion.