Patent ID: 7680140

Claim:
An apparatus comprising: a receive circuit coupled to receive packets on one of a plurality of input virtual channels and to use a hash and route circuit to separate the packets based on destinations for the packets, the hash and route circuit to select a different one of a plurality of switch virtual channels for each different destination of the packets and to send the packets to the destinations on the selected switch virtual channels based on the destinations; a transmit circuit to retransmit corresponding separated packets of the received packets, in which the transmit circuit is selected as a destination; a direct memory access (DMA) circuit to couple the corresponding separated packets of the received packets to a memory controller for coupling to a memory, in which the DMA circuit is selected as a destination; and a switch coupled to the receive circuit, the transmit circuit and the DMA circuit to switch corresponding separated packets on a switch virtual channel destined for the transmit circuit to the transmit circuit, switch corresponding separated packets on a switch virtual channel destined for the DMA circuit to the DMA circuit, and the switch to also merge other packets destined for the transmit circuit with the corresponding separated packets from the receiver which are destined for the transmit circuit; wherein the receive circuit, the transmit circuit, the DMA circuit and the switch are integrated onto an integrated circuit.