Patent ID: 7022559

Claim:
A method of making complementary FETs, comprising: forming a first doped region of a first conductivity type in a substrate; forming a second doped region of a second conductivity type in the substrate; forming a gate insulator layer over the first and second doped regions; depositing a conductive barrier layer on the gate insulator layer to protect the gate insulator layer; depositing a layer of a first metal over the barrier layer, the first metal having a first work function; modifying a portion of the layer of the first metal such that the modified portion has a second work function; after the modifying, forming a layer of copper over the first layer of the first metal, including over the modified portion of the layer of the first metal; patterning the layer of copper over the layer of the first metal including the modified portion, to form gate electrodes, wherein the layer of copper is to further reduce sheet resistance of the gate electrodes; and forming source/drain junctions aligned to the gate electrodes, wherein the depositing the conductive barrier layer is performed to a thickness less than 5 nm to keep the work functions of the gate electrodes over respective portions of the layer of the first metal intact.