Patent ID: 6839265

Claim:
A method for reducing differential noise in a semiconductor device having an integrated circuit memory having a plurality of memory cells, comprising: fabricating a first digit line having a width and a second digit line having a width, the first digit line and the second digit line extending in a first conductive level and a second conductive level above a plane extending along a portion of a surface of the integrated circuit memory such that the first digit line and the second digit line are substantially vertically aligned within the widths thereof and vertically stacked one atop the other in the plane; providing a vertical conductive twist to locate a portion of each of the first digit line and the second digit line in both the first conductive level and the second conductive level; coupling an equal number of the plurality of memory cells of the integrated circuit memory to portions of the first digit line and the second digit line located in a lower conductive level of the first conductive level and the second conductive level; electrically balancing the first digit line and the second digit line when vertically stacked one atop the other; and isolating a plurality of adjacent memory cells of the plurality of memory cells using an isolation region.