Patent ID: 8144296

Claim:
A method of forming an array substrate for use in an in-plane switching liquid crystal display device, comprising: sequentially forming a first barrier layer and a first low resistance metallic layer on a substrate; simultaneously patterning the first barrier layer and the first low resistance metallic layer using a first mask process to form a gate line, a gate electrode, a gate pad and a plurality of common electrodes on the substrate, wherein the gate line is disposed in a first direction, the gate pad is connected to one end of the gate line, the gate electrode extends from the gate line, and the plurality of common electrodes are disposed in a direction perpendicular to an adjacent gate line, and wherein the gate electrode and the gate line have a first double-layered structure consisting of the first barrier layer and the first low resistance metallic layer; forming a gate insulating layer over the substrate to cover the gate line, the gate electrode, the gate pad and the plurality of common electrodes; forming an active layer and an ohmic contact layer on the gate insulating layer using a second mask, the active layer and the ohmic contact layer disposed over the gate electrode; sequentially forming a second barrier layer and a second low resistance metallic layer on the gate insulating layer to cover the active and ohmic contact layers; simultaneously patterning the second barrier layer and the second low resistance metallic layer using a third mask to form a data line in a second direction, a data pad at one end of the data line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode across the gate electrode, and a plurality of pixel electrodes in the direction perpendicular to the adjacent gate line and arranged in an alternating pattern with the common electrodes, wherein the data line defines a pixel region with the gate line, the pixel electrodes are connected to the drain electrode, and the data line and the source and drain electrodes have a second double-layered structure consisting of the second barrier layer and the second low resistance metallic layer; forming a passivation layer over the gate insulating layer to cover the data line, the data pad, the source electrode, the drain electrode, and the plurality of pixel electrodes; and patterning the passivation layer using a fourth mask to form a gate pad contact hole and a data pad contact hole, the gate pad contact hole exposing the gate pad and the data pad contact hole exposing the data pad.