Patent ID: 7221682

Claim:
A controller for a packet radio network comprising: a processor comprising a plurality of processor resources for processing a plurality of packet classes, each packet class having a different delay sensitivity associated therewith; said processor allocating to each packet class at least a portion of at least one processor resource based on the delay sensitivities; wherein said processor resources has a respective processing threshold; wherein said processor initially allocates each processor resource to a respective packet class; wherein said processor determines based upon arriving packets whether at least one processor resource will exceed its processing threshold, thereby defining at least one overloaded processor resource; and wherein said processor reallocates at least a portion of at least one processor resource to process packets for the at least one overloaded processor resource, thereby defining at least one reallocated processor resource; wherein the at least a portion of at least one processor resource reallocated to process packets for the at least one overloaded processor resource comprises a portion determined based on the delay sensitivity associated with the packet class processed by said at least one overloaded processor resource and the delay sensitivity associated with the packet class initially to be processed by said at least one reallocated processor resource.