Patent ID: 8461687

Claim:
A semiconductor device comprising: a semiconductor substrate; a cell insulating isolation region disposed within the semiconductor substrate in a cell area of the semiconductor device, and delimiting a cell active region of the semiconductor substrate in the cell area; a word line extending in the semiconductor substrate in the cell area of the semiconductor device; a bit line contact plug disposed on the cell active region; a bit line disposed on the bit line contact plug and comprising a bit line electrode; a peripheral insulating isolation region disposed within the semiconductor substrate in a peripheral area of the semiconductor device, and delimiting a peripheral active region of the semiconductor substrate in the peripheral area; and a peripheral transistor comprising a peripheral transistor lower electrode and a peripheral transistor upper electrode disposed on the peripheral active region of the semiconductor substrate, wherein the bit line contact plug occupies the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode occupies the same level in the semiconductor device as the peripheral transistor upper electrode, wherein the bit line further comprises a bit line barrier layer on which the bit line electrode is disposed, and a bit line capping layer disposed on the bit line electrode.