Patent ID: 6849537

Claim:
A method for forming a plurality of electrically conductive lines, the method comprising: forming a dielectric layer upon a semiconductor substrate having a plurality of electrically active regions therein; forming a plurality of recesses in the dielectric layer each terminating at a respective active region in the semiconductor substrate; forming a first refractory metal material upon the dielectric layer, within each said recess, and upon each said active regions; forming a conductive layer over the first refractory metal, said conductive layer having a top planar surface; forming an antireflective layer upon the conductive layer, wherein the antireflective layer has a plurality of recesses therein corresponding to the plurality of recesses in the dielectric layer; forming co-planar opposing pairs of side walls on each of the first refractory metal material, the conductive layer, and the antireflective layer, each said side wall beginning at a top surface of the dielectric layer and extending above the plurality of recesses, wherein the width between each said opposing pair of side walls is greater that the width of each said recess; forming a second refractory metal material on a top surface of the antireflective layer, and upon the co-planar opposing pairs of side walls on each of the first refractory metal material, the conductive layer, and the antireflective layer; and removing said second refractory metal material to: expose the top surface of the antireflective layer; and form therefrom a spacer upon each said co-planar opposing pair of side walls on each of the first refractory metal material, the conductive layer, and the antireflective layer.