Patent ID: 7470973

Claim:
A semiconductor device comprising: a silicon substrate of a (100) surface orientation; a device isolation structure formed in said silicon substrate to define a first device region and a second device region in said silicon substrate; a n-channel MOS transistor formed in said first device region of said silicon substrate; and a p-channel MOS transistor formed in said second device region of said silicon substrate, said n-channel MOS transistor comprising a first gate electrode extending over said silicon substrate via a first gate insulation film in said first device region in a <100> direction of said silicon substrate and a pair of n-type diffusion regions formed in said silicon substrate in said first region at respective lateral sides of said first gate electrode, said p-channel MOS transistor comprising a second gate electrode extending over said silicon substrate via a second gate insulation film in said second device region in a <100> direction of said silicon substrate and a pair of p-type diffusion regions formed in said silicon substrate in said second region at respective lateral sides of said second gate electrode, a first stressor film accumulating therein a tensile stress being formed over said silicon substrate to cover at least said device isolation structure, said device isolation structure comprising a device isolation trench formed in said silicon substrate and a device isolation insulator filling said device isolation trench, a second stressor film accumulating therein a tensile stress being formed over a surface of said device isolation trench such that said second stressor film is interposed between said silicon substrate and said device isolation insulator, said first stressor film covering said first device region and said second device region continuously.