Patent ID: 8753969

Claim:
A method for fabricating a MOS device on and within a semiconductor substrate comprising: forming a gate structure including a cap having a top and sidewalls overlying a top of a gate electrode, wherein the gate structure overlies the semiconductor substrate; depositing a liner over the gate structure, wherein a selected portion of the liner abuts each sidewall of the cap; forming first spacers adjacent the selected portion of the liner; simultaneously etching the cap and the first spacers and simultaneously exposing interior surfaces and exterior surfaces of needles formed by the selected portion of the liner, wherein the interior surface of each needle faces the other oxide needle and each exterior surface is opposite a respective interior surface; depositing an additional liner on the exposed interior surfaces and exposed exterior surfaces of the needles and over the top of the gate electrode; forming a second spacer adjacent each exterior surface of the needle; depositing a stress-inducing layer over the additional liner, wherein depositing the stress-inducing layer includes depositing the stress-inducing layer over the second spacers such that the second spacers are interposed between the stress-inducing layer and the exterior surfaces of the needle; annealing the semiconductor substrate and expanding the stress-inducing material outwardly into the needles; and removing the stress-inducing layer.