Patent ID: 8432303

Claim:
An electronic apparatus comprising: a clock signal generating circuit which generates a clock signal; a shift/hold signal generating circuit which generates a shift/hold signal of a predetermined cycle; a second parallel/serial converting device which includes a second clock input terminal through which the clock signal generated in the clock signal generating circuit is input and a plurality of second parallel input terminals through which a plurality of second digital signals is input in parallel, which operates by a second operation voltage which is input, which retains the respective second digital signals input through the second parallel input terminals according to the shift/hold signal, and which sequentially shift-outputs the retained respective second digital signals in synchronization with the clock signal input through the second clock input terminal; a first parallel/serial converting device which includes a first clock input terminal through which the clock signal generated in the clock signal generating circuit is input, a plurality of first parallel input terminals through which a plurality of first digital signals is input in parallel, and a first serial input terminal through which the signals output from the second parallel/serial converting device are input, which operates by a first operation voltage which is input, which retains the respective first digital signals input through the first parallel input terminals according to the shift/hold signal, which sequentially shift-outputs the retained respective first digital signals in synchronization with the clock signal input through the first clock input terminal, and which sequentially shift-outputs the respective digital signals input through the first serial input terminal in synchronization with the clock signal input through the first clock input terminal, subsequent to the shift output of the respective first digital signals; a mask circuit which non-masks a clock signal portion used for shift-outputting the respective first digital signals by the first parallel/serial converting device and masks the remaining clock signal portion, in the clock signal supplied to the first and second parallel/serial converting devices from the clock signal generating circuit, when the apparatus is in a first mode, and non-masks the entire clock signal supplied to the first and second parallel/serial converting devices from the clock signal generating circuit, when the apparatus is in a second mode; and a power supply circuit which outputs the first operation voltage and does not output the second operation voltage in the first mode, and outputs the first and second operation voltages in the second mode.