Patent ID: 6845059

Claim:
A memory array comprising: a plurality of single-ended, dual-port, destructive-write memory cells arranged in an array formation of rows and columns, each cell having a read port consisting of a read data terminal and a read activation terminal, and further a write port consisting of a write data terminal and a write activation terminal, the read data terminal being accessed by asserting the cell read activation terminal and the write data terminal being accessed by asserting the cell write activation terminal, wherein in each column of cells, a read bitline connects all the read data terminals of each cell, each read bitline having a read sense amplifier connected thereto, and a write bitline with an associated write data driver connected to the write data terminal of the memory cells, and wherein when the read activation terminal is asserted, the read data terminal presents data depending upon the stored content of the memory cell, and when the write activation terminal is asserted, the content of the memory cell is set according to the state of the write data terminal; and a circuit associated with each of the read sense amplifiers and each of the write data drivers for holding data sensed by the read sensing amplifier, making data read by the read sense amplifier available to the write data driver.