Patent ID: 7054195

Claim:
A nonvolatile semiconductor memory having a plurality of common control gate lines, a plurality of bit lines and a source line comprising: a memory cell array including a memory cell block comprising a plurality of memory cell units arranged in parallel with each other in a row direction, each of the memory cell unit comprising: a plurality of memory cell transistors arranged in a column line; a first select gate transistor connected to the bit line at a first end of each of the memory cell transistors; and a second select gate transistor connected to the source line at a second end of each of the memory cell transistors so that the memory cell transistors arranged in a row can be connected to the common control gate line; and a control gate line drive circuit configured to simultaneously write-in all of the memory cell transistors connected to a selected control gate line, wherein different types of voltages incapable of write-in applied at least once to all or a part of the control gate lines before applying a high plus voltage for write-in to the selected control gate line.