Patent ID: 7890685

Claim:
A multi-core LSI, comprising: a plurality of CPUs coupled to a first shared bus; one or more modules coupled to a second shared bus; a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating access to said one or more modules by the plurality of CPUs; and a system controller comprising an interrupt control register and configured to monitor whether or not a response signal to an access request signal of the CPU is output from the module to be accessed, wherein the system controller is configured to issue an interrupt signal to a first CPU that issued the access request signal to the first shared bus, or to a second CPU that did not issue the access request signal, in accordance with the interrupt control register if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.