Patent ID: 7451274

Claim:
A memory control device provided between a main storage and a command processing device and an operation device included in a central processor, the memory control device controlling reference from the command processing device and the operation device to data stored in the main storage, the memory control device comprising: a plurality of caches that store data stored in the main storage and address information corresponding to the data; and a plurality of cache buffers that hold address information of requests of the caches for reference to data stored in the main storage, wherein the central processor executes at least a load command to store data from the caches or the main storage into the operation device, a store command to write a result of an operation carried out by the operation device into the caches or the main storage, and a prefetch command to store data stored in the main storage into the caches, based on an out-of-order processing for processing commands by changing the order of executing the commands, and the memory control device includes: a valid move-in buffer detector that detects a number of the cache buffers that hold requests of the cache for reference to data stored in the main storage; and a buffer controller that controls to hold in the cache buffers the reference requests according to the load command or the store command in preference to the reference requests according to the prefetch command, when the detected number of the cache buffers reaches a predetermined number, a fetch port as a buffer that holds a fetch processing request to fetch data from the caches or the main storages; and a command execution monitoring unit that monitors the execution of the fetch processing request held in the fetch port, wherein when the command execution monitoring unit detects a predetermined time delay in the fetch processing, the buffer controller controls to hold in the cache buffer the reference request according to a fetch processing request that is stored for the longest time in the fetch port among the fetch processing requests, and when the command execution monitoring unit does not detect a predetermined time delay in the fetch processing, the buffer controller controls to hold in the cache buffers the reference requests according to the fetch processing request.