Patent ID: 8780624

Claim:
A memory array, comprising: a plurality of memory cells; a plurality of paralleled bit lines formed on a semiconductor substrate, and a plurality of word lines perpendicular to the bit lines, wherein each bit line is connected to a source and a drain of adjacent memory cells; a part of a word line between adjacent bit lines is connected to a gate of a memory cell; wherein, the memory cells are split-gate memory cells, each comprising a first memory bit cell arranged between a word line and a source of the memory cell, and a second memory bit cell arranged between the word line and a drain of the memory cell, the first and the second memory bit cells comprising a first control gate and a second control gate, respectively; the memory array further comprises a plurality of first control lines and second control lines connected to the first control gates and the second control gates, respectively, each pair of first control line and second control line being arranged on both sides of a word line and being parallel to the word line; wherein the first and second memory bit cells share one word line; reading voltages are applied to the word line, the first control gate, the second control gate, and the bit lines connected to the source and the drain to read the memory bit cells; during a reading operation to the first memory bit cell, reading voltages applied to the word line, the first control gate, the second control gate, the bit line connected to the source and the bit line connected to the drain are from 0.5 V to 5 V, from 0 V to 3 V, from 0 V to 6 V, from 0 V to 0.5 V and from 0.8 V to 3 V, respectively; and wherein during a reading operation to the second memory bit cell, reading voltages applied to the word line, the first control gate, the second control gate, the bit line connected to the source and the bit line connected to the drain are from 0.5 V to 5 V, from 0 V to 6 V, from 0 V to 3 V, from 0.8 V to 3 V and from 0 V to 0.5 V, respectively.