Patent ID: 7941728

Claim:
A hardened store-in cache mechanism, comprising: a store-in cache having lines of a first linesize stored with checkbits, wherein said checkbits comprise byte-parity bits; and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of said store-in cache, wherein said ancillary store-only cache (ASOC) includes fewer lines than said store-in cache, each line of said ancillary store-only cache (ASOC) having said first linesize stored with said checkbits, said checkbits of said ancillary store-only cache (ASOC) being doubleword Error Correcting Code (ECC) for each doubleword within said stored-to lines, and said stored-to lines being marked as being modified within said store-in cache when said stored-to lines are stored to using a modified indicator.