Patent ID: 8525563

Claim:
A semiconductor device comprising: a coarse adjusting circuit generating first and second clock signals having different phases from each other; and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal, wherein the fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal, the fine adjusting circuit controls the phase of the third clock signal in 2 m +n steps by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes, where m is a natural number and n is a natural number equal to or smaller than 2 m , smallest one of the first transistors in size enables to change the phase of the third clock signal by one step, and largest one of the first transistors in size enables to change the phase of the third clock signal by smaller than 2 m steps, and smallest one of the second transistors in size enables to change the phase of the third clock signal by one step, and largest one of the second transistors in size enables to change the phase of the third clock signal by smaller than 2 m steps.