Patent ID: 7603600

Claim:
A timing failure remedying apparatus for an integrated circuit having a plurality of logic circuits of the same logic, comprising: a pattern generator for generating a test pattern to be inputted to each of said plural logic circuits; a plurality of inputting scan chains for inputting the test pattern generated by said pattern generator to said plural logic circuits, respectively; a plurality of taking-out scan chains for taking out values resulting from the test pattern from said plural logic circuits, respectively; a first clock signal applying unit for applying a first clock signal in a first cycle to a processing core for reference having one of said plural logic circuits functioning for reference, one of said plural inputting scan chains (hereinafter referred to as an inputting scan chain for reference) corresponding to said logic circuit for reference and one of said plural taking-out scan chains (hereinafter referred to as a taking-out scan chain for reference) corresponding to said logic circuit for reference; a second clock signal applying unit for applying a second clock signal in a second cycle differing from the first cycle to a processing core to be tested having another one of said plural logic circuits functioning to be tested, another one of said plural inputting scan chains (hereinafter referred to as an inputting scan chain to be tested) corresponding to said logic circuit to be tested and another one of said plural taking-out scan chains (hereinafter referred to as a taking-out scan chain to be tested) corresponding to said logic circuit to be tested; a first comparator for comparing a value captured in said taking-out scan chain for reference from said logic circuit for reference through an operation of said processing core for reference according to the first clock signal applied by said first clock signal applying unit with a value captured in said taking-out scan chain to be tested from said logic circuit to be tested through an operation of said processing core to be tested according to the second clock signal applied by said second clock signal applying unit; a diagnosing unit for diagnosing a timing failure in said logic circuit to be tested on the basis of a result of comparison made by said first comparator; and an adjuster for, when said diagnosing unit pronounces a diagnosis that a timing failure occurs, adjusting at least either the second cycle or a delay amount of the second clock signal to be applied to said processing core to be tested by said second clock signal applying unit to remedy the timing failure.