Patent ID: 7425474

Claim:
A method of manufacturing a transistor, comprising: forming a source electrode and a drain electrode over a substrate by an electroless plating method, the source electrode having a thickness in the range of 30 nm to 300 nm; forming an organic semiconductor layer over the source electrode and the drain electrode; forming an insulating layer over the semiconductor layer; and forming a gate electrode over the insulating layer, wherein the electroless plating method includes: attaching charge control agents to a first region of the substrate, each of the charge control agents being a cationic surfactant; irradiating a first part of the first region with a light using a photomask to remove a part of the charge control agents on the first part of the first region; attaching at least one of a catalytic agent and a precursor of the catalytic agent to a second part of the first region, which is different from the first part of the first region; and depositing a metallic layer from a metal salt solution on the second part of the first region attached with one of the catalytic agent and the precursor of the catalytic agent to form the source electrode and the drain electrode.