Patent ID: 8531208

Claim:
A flip-flop, comprising: a first latch circuit configured to latch a data signal in response to a plurality of first control signals and to latch a scan input signal in response to a plurality of second control signals; and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals, wherein the first latch includes a first tri-state inverter configured to connect an input terminal of the second latch circuit and to invert the data signal in response to the first control signals; a second tri-state inverter configured to invert the scan input signal in response to the second control signals; a third tri-state inverter having an input terminal connected to an output terminal of the first tri-state inverter and having an output terminal connected to an output terminal of the second tri-state inverter; and a fourth tri-state inverter having an input terminal connected to the output terminal of the second tri-state inverter and having an output terminal connected to the output terminal of the first tri-state inverter.