Patent ID: 6847640

Claim:
An interface for transferring data between a network switching router for fast path processing of network data packets and at least one memory device, comprising: an external portion having a clock source for generating a continuous cyclic signal, a clock buffer coupled to said clock source for registering said continuous cyclic signal and providing a plurality of timing control signals and said at least one memory device; and an internal portion having an input cell, a phase locked loop, at least one multiplexer, and a plurality of controlled latches, said input cell is coupled to said clock buffer for receiving one of said timing control signals and transforming said timing control signals into pulses, said phase locked loop coupled to said input cell for receiving said pulses, said phase locked loop maintaining a timing pulse frequency in response to said pulses, said at least one multiplexer configured to gate data transfer to and from said internal portion and said external portion, said controlled latches responsive to said timing pulse frequency for coupling said switching router to said at least one multiplexer, such that said switching router stores and retrieves data to and from said at least one memory device at a rate about 10 gigabits per second, wherein said at least one memory receives another one of said timing control signals from said clock buffer; and wherein said timing pulse frequency provides synchronization between said external portion and said internal portion.