Patent ID: 8576839

Claim:
A switching node comprising: a plurality of contention-free switch modules, each having a shared memory device, m inlets, and m outlets, m>1, each inlet having cyclic exclusive access to said shared memory device and each outlet having cyclic exclusive access to said shared memory device, said switch modules arranged into: m primary switch modules; m secondary switch modules; and m ternary switch modules; and a plurality of consolidation units arranged into: a set of primary consolidation units, each connected to a respective inlet of one of said primary switch modules and configured to: receive data segments destined to outlets of at least one ternary switch module; and assemble said data segments into primary data blocks each containing at most m data segments; a set of secondary consolidation units each connecting a respective primary switch module to one of said secondary switch modules and configured to: disassemble primary data blocks switched through said respective primary switch module into constituent data segments; and reassemble said constituent data segments into secondary data blocks each containing at most m data segments destined to outlets of only one ternary switch module; and a set of ternary consolidation units each connecting a respective secondary switch module to a respective ternary switch module and configured to: disassemble secondary data blocks switched through said respective secondary switch module into component data segments; and reassemble said component data segments into ternary data blocks each containing at most m data segments destined to only one outlet of said respective ternary switch module.