Patent ID: 8760338

Claim:
A comparator, comprising: a differential amplifier circuit configured to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit configured to operate based on the first intermediate output and the second intermediate output, the differential latch circuit comprising: a first line comprising a first PMOS transistor and a first NMOS transistor coupled in series; a second line, coupled to the first line, comprising a second PMOS transistor and a second NMOS transistor coupled in series, wherein a gate of the first PMOS transistor and the first NMOS transistor is coupled to a coupling node of the second PMOS transistor and the second NMOS transistor and the gate of the second PMOS transistor and the second NMOS transistor is coupled to the coupling node of the first PMOS transistor and the first NMOS transistor; and a third PMOS transistor provided between a source of the first PMOS transistor and the second PMOS transistor and a high potential power supply, a gate of a third PMOS transistor receiving a reverse signal of the clock signal.