Patent ID: 7355665

Claim:
A thin film transistor array panel, comprising: a plurality of gate lines formed on an insulating substrate and including a plurality of gate electrodes; a gate insulating layer covering the gate lines; a semiconductor layer formed on the gate insulating layer; a plurality of data lines having source electrodes formed at least on the semiconductor layer and intersecting the gate lines; a plurality of drain electrodes separated from the data lines and opposite to the data lines with respect to the gate electrode; a passivation layer covering the portion of the semiconductor layer that is not covered with the data lines and the drain electrodes; a plurality of linear pixel electrodes formed on the passivation layer and coupled to the drain electrodes, at least two of the linear pixel electrodes disposed in each pixel area; and a plurality of common electrodes formed on the passivation layer, alternately arranged with the pixel electrodes, substantially parallel to the pixel electrodes; a plurality of storage electrode lines formed on the substrate and extending substantially parallel to the gate lines, the storage electrode line comprising a storage electrode that are wider than the other portions; wherein the pixel electrodes and the common electrodes are neither perpendicular nor parallel to the data lines, wherein the pixel electrodes and the common electrodes are symmetrically arranged with respect to a transverse center line of the pixel, and wherein storage electrodes are disposed on the transverse center of the pixel and shaped like triangle or trapezoid.