Patent ID: 7064591

Claim:
A fractional-N frequency synthesizer comprising: a phase lock loop (PLL); and coarse tuning circuitry coupled to the PLL and adapted to control the PLL such that the PLL operates in an integer division mode during coarse tuning and a fractional-N division mode during normal operation, wherein the coarse tuning circuitry comprises divide value generation circuitry adapted to: provide an integer divide value to a divider of the PLL when operating in the integer division mode; and provide a fractional sequence of divide values to the divider of the PLL when operating in the fractional-N division mode, wherein the PLL comprises a controlled oscillator (CO) and the coarse tuning circuitry further comprises: an M divider adapted to divide a reference signal from the PLL by a factor M to provide an divided reference signal; and tuning logic adapted to: compare a frequency of the divided reference signal and a frequency of a divided controlled oscillator (CO) signal during coarse tuning, wherein the divided CO signal is a CO signal from the CO divided by the integer divide value; and provide a tuning curve control signal to select a tuning curve for a CO of the PLL based thereon to effect coarse tuning of the CO.