Patent ID: 8458565

Claim:
A circuit for emulating bit-level erasable non-volatile memory, comprising: an emulator that is arranged to activate a first virtual sector of a bit-level programmable, block-level erasable non-volatile memory, the first virtual sector arranged to store received write requests having an address and a record to be written to the received address, the emulator arranged to store in the first virtual sector in a linked list of records each subsequent record received in subsequent write requests having the received address, wherein a separate thread in the linked list is maintained for each different received address, the emulator arranged to copy the last record subsequently received for each of the received addresses to a linked list of a second virtual sector when a first operating parameter has been exceeded, and the emulator arranged to deactivate and erase the active virtual sector when the last records subsequently received for each of the received addresses in the linked list active virtual sector have been copied to the second virtual sector.