Patent ID: 7586773

Claim:
A first device level formed above a substrate comprising a plurality of vertically oriented p-i-n diodes, each p-i-n diode comprising a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region, wherein each p-i-n diode has the form of a pillar, wherein, for at least 99 percent of the p-i-n diodes, current flowing through the p-i-n diodes when a voltage between about 1.5 volts and about 3.0 volts is applied between the bottom heavily doped p-type region and the top heavily doped n-type region is at least 1.5 microamps, wherein the p-i-n diodes comprise deposited silicon, germanium, or silicon-germanium, wherein the first plurality of p-i-n diodes includes every p-i-n diode in the first device level.