Patent ID: 6959365

Claim:
A microcomputer, comprising: a CPU configured to execute instructions; a flash memory portion divided into a plurality of blocks; and a flash memory control circuit for controlling a rewrite operation to said flash memory portion, wherein said CPU is configured to execute a predetermined program stored in at least one of said plurality of blocks, said predetermined program including instructions for rewriting a block other than said at least one of said plurality of blocks in said flash memory portion; said flash memory portion is configured to execute the rewrite operation in said block other than said at least one of said plurality of blocks based on a rewrite command, and to output a ready status signal indicating whether said rewrite operation is being executed; said flash memory control circuit is configured to receive said ready status signal, whereby when said ready status signal indicates that said rewrite operation is to be executed, said flash memory control circuit provides a hold signal to said CPU, wherein said hold signal indicates that predetermined signals required for said CPU to access said flash memory portion should be fixed to constant values; said predetermined signals include an address signal, a data signal, and a control signal of said flash memory control circuit; said flash memory control circuit is configured to set a pre-hold signal active after a beginning of receipt of said rewrite command and before an end of the receipt of said rewrite command; and said flash memory control circuit is configured to output said hold signal indicating said predetermined signals should be fixed to the constant values when said pre-hold signal is active at the end of the receipt of said rewrite command.