Patent ID: 7795101

Claim:
A method of forming a MOS transistor, comprising: providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween; pre-amorphizing the source region and the drain region to form amorphized regions; performing a first ion implantation to implant a first dopant in the source region and the drain region to form a first doped region; forming at least a spacer on the sidewalls of the gate; performing a second ion implantation to implant a second dopant in the source region and the drain region to form a second doped region; annealing the source region and the drain region to activate the first dopant, regrow the amorphized regions to a substantially crystalline form, and form a junction profile; and performing a co-implantation process, after pre-amorphizing the source region and the drain region and before annealing the source region and the drain region, to implant a carbon co-implant in the source region and the drain region, wherein the carbon co-implant is from a precursor comprising CO or CO 2 .