Patent ID: 7688299

Claim:
A display apparatus comprising: a memory that stores an image signal in one frame unit, in which an image signal of a previous frame (a previous image signal), which is previously stored, is read out from the memory during a present frame, and an image of the present frame (a present image signal) is written into the memory; a look-up table that stores plural reference data and receives the previous image signal from the memory and the present image signal to output reference data corresponding to high order bits of the present image signal and high order bits of the previous image signal; and a timing controller that receives low order bits of the present image signal, low order bits of the previous image signal, and the reference data to output a corrected image signal, and receives a control signal from an external device to output a data control signal and a gate control signal, in which the timing controller applies a first second-order interpolation equation when the high order bits of the present image signal are identical to the high order bits of the previous image signal and applies a second second-order interpolation equation, which is different from the first second-order interpolation equation, when the high order bits of the present image signal are different from the high order bits of the previous image signal; a data driving circuit that receives the corrected image signal in synchronization with the data control signal and converts the corrected image signal into data voltage to output the data voltage; a gate driving circuit that sequentially outputs gate pulses in synchronization with the gate control signal; and a display panel that receives the data voltage in response to the gate pulse to displays an image thereon.