Patent ID: 8669975

Claim:
A driving circuit of an electro-optical device, comprising: a plurality of scanning lines; a plurality of data lines; capacitance lines provided correspondingly to the scanning lines respectively; pixels provided respectively at intersections between the scanning lines and the data lines; a scanning-line-driving circuit selecting the scanning line in a predetermined order; a data-line-driving circuit supplying a data signal of voltage in accordance with gray scale of a pixel through the data line to the pixel corresponding to the selected scanning line; and a capacitance-line-driving circuit shifting voltage of a capacitance line to one voltage of two-value voltage when corresponding scanning line is selected and to the other voltage of the two-value voltage after the selection period of the corresponding scanning line is terminated, wherein each pixel includes, a pixel switching element, one end of which is connected to the data line, and when the corresponding scanning line is selected, the one end and the other end is electrically connected, a pixel capacitance, one end of which is connected to the other end of the pixel switching element, and the other end of which is connected to a common electrode, and an auxiliary capacitance interposed between one end of the pixel capacitance and the capacitance line provided correspondingly to the scanning line, and the capacitance-line-driving circuit includes a unit control circuit provided correspondingly to the capacitance line at both end portions of the capacitance line, and wherein the unit control circuit includes: a latch circuit holding a logic level at one level for at least a period of the scanning line corresponding to the one capacitance line being selected, a switch provided between the capacitance line and a signal line supplying a capacitance signal in which the two-value voltage is switched over at a predetermined cycle, the switch being electrically connected when the logic level is one level and electrically disconnected when the logic level is the other level, wherein the capacitance signal has a first capacitance signal and a second capacitance signal, voltage of the first capacitance signal is switched over at the time when none of the scanning line is selected in a cycle of selecting a polarity of the scanning lines by two rows at a time, the second capacitance signal has a phase difference of 90 degrees from the first capacitance signal, the switch of the unit control circuit of an odd-numbered row is interposed between the capacitance line and a signal line supplying the first capacitance signal, and the switch of the unit control circuit of an even-numbered row is interposed between the capacitance line and a signal line supplying the second capacitance signal.