Patent ID: 7411242

Claim:
A non-volatile semiconductor memory device comprising: a first pattern portion provided above a semiconductor substrate as a charge storage region; a second pattern portion provided above the semiconductor substrate to one side of the first pattern portion; and a third pattern portion provided above the semiconductor substrate to another side of the first pattern portion, wherein the first pattern portion is formed so as to cover a lateral surface of the second pattern portion and a lateral surface of the third pattern portion, wherein one end of the first pattern portion is positioned on an upper surface of the second pattern portion, wherein another end of the first pattern portion is positioned on an upper surface of the third pattern portion, wherein the first pattern portion is positioned in a gap region between the second pattern portion and the third pattern portion, a part of the first pattern portion being concave, and wherein the first pattern portion satisfies the relationship A>B+C+D, where a sidewall area of the first pattern portion within the gap region is A, a bottom surface area of the first pattern portion within the gap region is B, an upper surface area of a part of the first pattern portion over a top of second pattern portion is C, and a side wall area of the part of the first pattern portion over the top of the second pattern portion is D.