Patent ID: 8909874

Claim:
A memory system comprising: at least one memory device having a plurality of individually accessible ranks; a memory controller coupled to the at least one memory device and controlling the scheduling of memory access operations, wherein the memory controller comprises logic that: tracks a time remaining before a scheduled time for initiating a high priority, high latency operation at a first memory rank of a plurality of memory ranks of the memory system, wherein the plurality of memory ranks that are individually accessible by different memory access operations scheduled from a command re-order queue of the memory controller, wherein the scheduled time of the high priority, high latency operation is a future time, and wherein the command re-order queue contains memory access operations targeting the plurality of memory ranks; in response to the time remaining reaching a pre-established early notification time before the scheduled time for initiating the high priority, high latency operation; biases the command re-order queue to prioritize scheduling of any first memory access operations that target the first memory rank; and schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the command re-order queue that target other memory ranks of the plurality of memory ranks, wherein the scheduling of the first memory access operations to the first memory rank for early completion causes the first memory access operations to be completed before performing the high priority, high latency operation at the first memory rank; and performs the high priority, high latency operation at the first memory rank at the scheduled time; wherein the biasing of the command re-order queue and scheduling of the first memory access operations triggers a faster reduction of first memory access commands remaining within the command re-order queue before the high priority, high latency operation is performed at the first memory rank.