Patent ID: 7251805

Claim:
A mega-ASIC comprising: (a) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; (b) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks, wherein the excess and different I/O blocks include a first set of front-end I/O blocks and a second set of, back-end I/O blocks, and where the mega-ASIC further includes: programmable, block activating/de-activating means capable of selectively activating one or more of the front-end I/O blocks and of selectively activating one or more of the back-end I/O blocks.