Patent ID: 7049878

Claim:
A down-converter comprising an on-chip bias circuit for enhancing symmetry and linearity, the down converter comprising: an input stage and a bias circuit unit, comprising a radio frequency signal input terminal, the input stage and the bias circuit unit converting a single-end voltage signal to a differential current signal, the input stage and the bias circuit unit further comprising: a first transistor, comprising a drain, a gate and a source, the drain being coupled to the radio frequency signal input terminal, the source being coupled to a ground terminal; a second transistor, comprising a drain, a gate and a source, the source being coupled to the drain of the first transistor and to the radio frequency signal input terminal; a third transistor, comprising a drain, a gate and a source, the gate being coupled to the gate of the first transistor and to the radio frequency signal input terminal, the source being coupled to the source of the first transistor and to the ground terminal; a fourth transistor, comprising a drain, a gate and a source, the gate being coupled to the drain of the fourth transistor and to the gate of the second transistor; a fifth transistor, comprising a drain, a gate and a source, the gate being coupled to the drain of the fifth transistor, and to the gate of the first transistor and to the source of the fourth transistor, the source being coupled to the source of the first transistor and to the ground terminal; a noise suppressing unit, coupled to the input stage and the bias circuit unit; and a frequency conversion operation unit, coupled to the input stage and the bias circuit unit, the frequency converting operation unit comprising a local vibration signal buffer having two input terminals to receive a local vibration signal, a first output terminal and a second output terminal.