Patent ID: 7307002

Claim:
A method of defining a poly-1 layer of a semiconductor chip, said semiconductor chip comprising a core memory area and a peripheral region, comprising: depositing a thick nitride barrier level above a substrate of said semiconductor chip; etching shallow isolation trenches into said nitride layer and said substrate; filling said shallow isolation trenches with oxide material; removing excess of said oxide material from on top of remainder of said nitride layer; depositing a first non-critical mask on said core memory area, leaving said peripheral region exposed; recessing said oxide material in said exposed peripheral region by an amount approximately equal to a final polysilicon thickness; stripping said first non-critical mask; stripping a remainder of said nitride barrier layer, thereby leaving mesas of oxide material in said core memory area; depositing a layer of polysilicon, called the poly-1 layer, over said core memory area and said peripheral region; depositing a thin hard mask over said core memory area and said peripheral region; depositing a second non-critical complimentary mask over said peripheral region; etching away an exposed portion of said thin hard mask over said core memory area; polishing an exposed core memory area to remove said polysilicon from on top of said mesas of field oxide in said core memory area; stripping said complimentary mask; stripping a remaining portion of said thin hard mask.