Patent ID: 8466505

Claim:
A semiconductor device comprising: a substrate; a gate structure comprising: a tunnel oxide over the substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric; a source region doped with a dopant of a first type adjacent to the gate structure; a drain region doped with a dopant of a second type opposite the first type adjacent to the gate structure; a first source spacer and a first drain spacer having substantially an equal width on opposite sides of the gate structure, wherein the first source spacer comprises an inner edge contacting a first edge of the gate structure, and an outer edge substantially aligned to an inner edge of the source region; and wherein the source, the drain and the substrate directly under the first source spacer are doped at a concentration sufficient to result in surface avalanche at a channel surface in the substrate when a voltage around 0.8 volts is applied across the source and drain, and wherein an inner edge of the drain region is substantially aligned to a second edge of the gate structure.