Patent ID: 7517816

Claim:
A method, comprising: forming a first dielectric layer above a first transistor element and a second transistor element, said first dielectric layer having a first specified intrinsic mechanical stress; forming a first liner on said first dielectric layer above said first and said second transistor elements, said liner being selectively etchable with respect to said first dielectric layer; selectively etching said first liner above said first transistor element while covering said second transistor element with a first resist mask; removing said first resist mask and removing a first portion of said first dielectric layer from above said first transistor element by selectively etching said first dielectric layer with a wet etch process while using said first liner over said second transistor element as an etch mask; forming a second dielectric layer above said first transistor element and a second portion of said first liner and said first dielectric layer formed above said second transistor element, said second dielectric layer having a second intrinsic stress differing from said first intrinsic stress; and selectively modifying said second intrinsic stress in a second portion of said second dielectric layer above said second portion of said first dielectric layer and said second transistor element by performing an ion bombardment process on said second portion of said second dielectric layer.