Patent ID: 7266009

Claim:
A ferroelectric memory comprising: a plurality of normal memory cells each including a ferroelectric capacitor which stores data fed from an exterior; a second memory cell including a ferroelectric capacitor which stores inverted data of first data stored in a first memory cell of said normal memory cells; bit lines individually connected with said normal memory cells and said second memory cell; current feed circuits which feed electric currents to said bit lines for a predetermined period from a start of a read operation; and a read control circuit which decides logic values of data read from said normal memory cells to said bit lines, in the read operation in a predetermined time after a voltage of any of said bit lines connected with said first and second memory cells first exceeds a threshold voltage, wherein said predetermined time is set to be a time from when a voltage of one of said bit lines connected with said first and second memory cells exceeds a threshold voltage to when a voltage of the other one of said bit lines connected with said first and second memory cells exceeds the threshold voltage.