Patent ID: 7338890

Claim:
A process for fabricating a circuit component, comprising: providing a silicon substrate, a contact pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said contact pad; depositing a first metal layer over said passivation layer and over said contact pad; forming a first pattern-defining layer over said first metal layer, wherein an opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said opening in said first pattern-defining layer; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, wherein an opening in said second pattern-defining layer exposes said second metal layer; depositing a copper layer over said second metal layer exposed by said opening in said second pattern-defining layer; depositing a nickel layer over said copper layer in said opening in said second pattern-defining layer; depositing a solder layer over said nickel layer in said opening in said second pattern-defining layer; removing said second pattern-defining layer; and removing said first metal layer not under said second metal layer and reducing a transverse dimension of said copper layer.