Patent ID: 8437178

Claim:
A static random access memory cell, comprising: a latch unit including: a bi-inverting circuit having a first terminal and a second terminal; and a switching circuit electrically connected between the first terminal and the second terminal, and including a first pass transistor and a second pass transistor, wherein the first pass transistor is connected with the bi-inverting circuit in parallel and has a first control terminal and a p-type conductivity, and the second pass transistor is connected with the first pass transistor in parallel and has a second control terminal and an n-type conductivity; a row wordline; a row write-bar wordline electrically connected to the second control terminal; a virtual common line: a single bitline; a column write wordline electrically connected to the first control terminal; and an auxiliary circuit electrically connected to the latch unit, the single bitline, the row wordline, the column write wordline and the virtual common line for controlling the latch unit, wherein: when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the static random access memory cell to write a first data bit to the latch unit.