Patent ID: 8917538

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including first lines extending in a first direction, second lines extending in a second direction crossing the first direction, and memory cells provided at intersections of the first and second lines and having a variable resistance element; and a control circuit configured to, when the memory cells include a selected memory cell, the first lines include a selected first line connected to the selected memory cell and an unselected first line other than the selected first line, and the second lines include a selected second line connected to the selected memory cell and an unselected second line other than the selected second line, supply a first voltage to the selected first line, and supply a second voltage to the unselected first line, the memory cell array including a third line, a fourth line and a first diode, and the control circuit being configured to, when the third line is connected to the selected second line via the first diode and the fourth line, supply a third voltage to the third line.