Patent ID: 8079006

Claim:
A simulation method, to be implemented in a computer, for carrying out a simulation of a semiconductor integrated circuit by the computer, said simulation method comprising: a first analyzing procedure, executed by the computer, carrying out a layout analysis based on layout data of a circuit formed by cells, and storing values of first layout parameters that are obtained by the layout analysis and represent a first layout into a storage part; an extracting procedure, executed by the computer, extracting basic cell characteristics of the cells from a net list, representing the extracted basic cell characteristics by second layout parameters that represent a second layout different from the first layout, and storing the basic cell characteristics represented by the second layout parameters into the storage part, said basic cell characteristics including at least one of a noise characteristic and a leak current; an acquiring procedure, executed by the computer, reading the values of the first layout parameters from the storage part, substituting the read values into the basic cell characteristics represented by the second layout parameters to obtain cell characteristics, and storing the cell characteristics in the storage part; and a second analyzing procedure, executed by the computer, analyzing an operation of the circuit using the cell characteristics obtained by the acquiring procedure, wherein the second layout parameters represent the second layout which is used to form the basic cell characteristics into a function by varying values of the second layout parameters within a range tolerable by the layout analysis with respect to the first layout to which first analyzing procedure carries out the layout analysis.