Patent ID: 7166892

Claim:
A DMOS structure comprising: a semiconductor substrate; and a region of a first type of conductivity in said semiconductor substrate and comprising a gate layer, and drain and source regions spaced apart in a first direction; each source region formed based upon a defined opening through said gate layer, the opening being elongated in the first direction and comprising a body diffusion region of a second type of conductivity implanted in self-alignment to edges of the opening through said gate layer, a first source diffusion region of the first type of conductivity implanted in self-alignment to the edges of the opening through said gate layer, spacers adjacent the edges of the opening through said gate layer, a second source diffusion region of the first type of conductivity implanted in self-alignment to edges of said dielectric spacers, a central area in said second source diffusion region void of a second source diffusion implant used for defining said second source diffusion region, a body connection plug diffusion region of the second type of conductivity in said central area and extending down to said body diffusion region, a silicide layer on said first and second source diffusion regions and on said body connection plug diffusion region, a source contact on said silicide layer and over said body connection plug diffusion region, and said central area in the form of a strip orthogonal to the first direction and extending across the opening in said gate layer, said central area and an area of said body connection plug diffusion region along a central axis of the opening through said gate layer having a same linewidth of definition as said source contact.