Patent ID: 7284166

Claim:
A built-in self-test and self-repair (BISR) structure for a plurality of different memory arrays embedded in an integrated device, the different memory arrays being different in at least one of type and size, the BISR structure comprising: a built-in self-test (BIST) block programmable to execute at least one test algorithm on each different memory array; a self-repair block processing fault address information for allocating redundant resources, a nonvolatile memory on which final redundancy address information is stored, a redundancy register loaded at each power-on with the final redundancy address information and a controller for managing data transfer with external circuitry; a nonvolatile memory containing information on at least one of logic addresses and data bus size, aspect ratio, capacity, multiplexing and scrambling parameters and corresponding test algorithm instructions for each of the different memory arrays; and a multiple frequency clock generator for providing a respective operating clock frequency for each different memory array.