Patent ID: 7362867

Claim:
A method for generating a primary scrambling code, the method comprising the steps of: generating a first m-sequence from a first m-sequence generator including first shift registers having first shift register values a i , wherein i=0 to c−1 and where c is the total number of the registers; generating a second m-sequence from a second m-sequence generator including second shift registers having values b j , wherein j=0 to c−1, and where c is the total number of the registers; masking the first shift register values a i with a first set or mask values K i , wherein i=0 to c−1 to generate a third m-sequence; adding the first m-sequence with the second m-sequence to generate a primary scrambling code; and adding the third m-sequence and the second m-sequence to generate a secondary scrambling code; wherein, the masking step shifts the first m-sequence cyclically by L chips to generate an L th secondary scrambling code associated with the primary scrambling code.