Patent ID: 7218145

Claim:
A level conversion circuit comprising: an input circuit which includes a pair of first transistors, each having a first gate, a first drain and a first source, and receives complementary input signals having a first amplitude through the first gates; a latch circuit, which includes a pair of second transistors, each having a second gate, a second drain and a second source, and converts the amplitude of each of the input signals into a second amplitude higher than the first amplitude and then outputs the converted signal through the second drain of one of the second transistors as an output signal, the second drains being connected to the first drains, respectively, and the second gate of one of the second transistors being connected to the second drain of the other of the second transistors; and a current mirror circuit which includes a pair of third transistors, each having a third gate, a third drain and a third source, the third drains being connected to the second sources, respectively, the third sources being connected to a high-level power supply line to which a high-level power supply voltage being a voltage of a high logic level of the second amplitude is applied, and the pair of the third gates being connected to the third drain of one of the third transistors.