Patent ID: 8280940

Claim:
A data processing apparatus, comprising: a register bank, comprising a plurality of registers respectively for storing a plurality of operands, the registers comprising a first register, a second register and a third register, the operands comprising a first operand, a second and a third operand, wherein the registers are n-bit registers, n is a natural number, and wherein the first operand is stored in the first register, the second operand is stored in the second register, and the third operand is stored in the third register; a shadow register, for storing the first operand as a first backup operand in response to a first control signal; and an operation unit, for multiplying the second operand by the third operand and adding the result to the first operand to obtain operational data, and storing the operational data in the first register in response to an arithmetic operation command after the first operand is backed up; wherein the register bank further comprises a fourth register, and the data processing apparatus further comprises a logic unit for providing the operational data of the first register to the fourth register in response to a second control signal, and then providing the first backup operand stored in the shadow register to the first register.