Patent ID: 7318124

Claim:
A cache hit ratio estimating apparatus including a computer comprising (1) a CPU section including a CPU, a RAM, a graphic controller, and display device interconnected through a host controller; (2) an input/output section including a communication interface, a hard disk drive and a CD-ROM drive, which are connected to the host controller through an input/output controller, and (3) a legacy input/output section including a ROM, a flexible-disk drive, and an input/output chip, which are connected to the input/output controller; said computer adapted for estimating the cache hit ratio of a caching device caching access target data accessed by a requesting device, wherein: at least one of a plurality of access target data has a different cache miss access cost compared to any other data of said plurality of access target data, said apparatus comprising: an access request arrival frequency obtaining section for obtaining an average arrival frequency by measuring access requests for each of said plurality of access target data; an access request arrival probability density function generating section for generating an access request arrival probability density function which is a probability density function of the arrival time intervals of access requests for each of said plurality of access target data, on the basis of the average arrival frequency of access requests for said each of said plurality of access target data; and a cache hit ratio estimation function generating section for generating an estimation function of the cache hit ratio for each of said plurality of access target data, on the basis of said access request arrival probability density function for said plurality of access target data.