Patent ID: 7741172

Claim:
A method of manufacturing a positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode comprising: providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate being of a first conductivity; forming at least one trench in the first main surface, the at least one trench extending to a first depth position in the semiconductor substrate, the at least one trench defining at least one mesa in the first main surface; doping with a first dopant of a second conductivity the first main surface and the at least one trench to form a first anode/cathode layer, the first anode/cathode layer being of a second conductivity opposite to the first conductivity; and doping with a second dopant of the first conductivity the second main surface to form a second anode/cathode layer, the second anode/cathode layer being of the first conductivity; lining the at least one trench with a first passivation material; and lining the at least one mesa with a second passivation material, wherein the first passivation material and second passivation material are the same material and are applied in the same processing step.