Patent ID: 8723051

Claim:
A wiring substrate comprising: a substrate body formed of silicon and including a first surface and a second surface; a first trench including an inner bottom surface and an inner side surface and being formed in a first surface side of the substrate body; a second trench including an inner bottom surface and an inner side surface and being formed in a second surface side of the substrate body; a penetration hole including an inner side surface and penetrating through the substrate body; an insulating film formed on the first surface of the substrate body, the second surface of the substrate body, the inner bottom surface and the inner side surface of the first trench, the inner bottom surface and the inner side surface of the second trench, and the inner side surface of the penetration hole; a first plane layer filling the first trench and being substantially flush with an upper surface of the insulating film that covers the first surface of the substrate body; a second plane layer filling the second trench and being substantially flush with the upper surface of the insulating film that covers the second surface of the substrate body; and a penetration wiring filling the penetration hole and being substantially flush with the upper surface of the insulating film that covers the first and second surfaces of the substrate body; wherein multiple insulating lavers and multiple wiring layers are formed on the first surface side of the substrate body and the second surface side of the substrate body, wherein the first plane layer is a reference potential layer, wherein the second plane layer is a power supply layer.