Patent ID: 8653530

Claim:
A thin film transistor array panel comprising: a substrate; a semiconductor layer formed on the substrate, including a source region, a drain region, and a channel region positioned between the source region and the drain region, and made of polysilicon; a first insulating layer formed on the semiconductor layer; a gate electrode overlapping the channel region of the semiconductor layer on the first insulating layer; a second insulating layer formed on the gate electrode; a first contact hole and a second contact hole exposing at least portions of the source region and the drain region of the semiconductor layer and formed in the first insulating layer and the second insulating layer; a source electrode enclosing an outer part of the first contact hole without extending thereinto, and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole without extending thereinto, and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.