Patent ID: 7286195

Claim:
A method for fabricating an interconnect structure on a TFT-array substrate of a flat panel display, comprising: forming a plurality of first metal lines in a non-display area of the TFT-array substrate; forming a first insulating layer on the TFT-array substrate to cover the first metal lines; forming a plurality of second metal lines on the first insulating layer, wherein each second metal line corresponds with one first metal line; forming a second insulating layer covering the second metal lines and the first insulating layer; forming a passivation structure on the second insulating layer with openings therein to expose one end of every first and its corresponding second metal lines; forming a plurality of first and second via holes in the first and second insulating layers inside the opening of the passivation structure to expose the first and second metal lines respectively; forming an ITO (indium tin oxide) layer on the second insulating layer, filling the first and second via holes to connect the first and second metal lines; forming a patterned photoresist layer on the ITO layer, masking the ITO layer inside the opening of the passivation structure; etching the ITO layer with the patterned photoresist layer as a mask to form ITO wiring to connect the first metal line with the second metal line, remaining a residual ITO ring along an inner foot of the opening; and removal of the remaining photoresist layer.