Patent ID: 7518402

Claim:
An integrated circuit (IC) comprising: a) an arrangement of tiles comprising a plurality of configurable tiles and a plurality of sides that define a boundary of the arrangement, wherein a first set of tiles among said plurality of configurable tiles each comprise: i) a configurable logic circuit, and ii) a plurality of input-select circuits; and b) a set of direct connections connecting said plurality of input-select circuits of a first tile to a set of outputs of a second set of tiles, wherein the second set of tiles is located in asymmetrical positions with respect to said first configurable tile, wherein the second set of tiles is located in asymmetrical positions with respect to the first particular tile because: i) at least one direct connection connects the first particular tile to a second particular tile in the second set, the second particular tile offset from the first particular tile in the arrangement, ii) the arrangement includes a symmetrical set of tiles, wherein each tile of said symmetrical set of tiles has a positional relationship with the first particular tile that is symmetrical to a positional relationship that the second particular tile has with respect to the first particular tile, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the first particular tile, and iii) no direct connection connects the first particular tile with any of the symmetrical set of tiles.