Patent ID: 7451425

Claim:
A processor-implemented method for determining a plurality of controlling pins for a tile module of a programmable logic device (PLD) design, the method comprising: inputting a netlist that describes the PLD design; inputting an identification of the tile module; inputting characterization data for each of at least one sub-module of the tile module, the characterization data specifying at least one select input pin that controls a programmable function of the sub-module, wherein each sub-module is one of a multiplexer module and a logic site module, and a logic-site module provides programmable logic resources; inputting characterization data for each of at least one configuration-memory-cell module of the tile module, the characterization data specifying a data output pin of the configuration-memory-cell module; determining a controlling pin for each select input pin of each instance of the at least one sub-module of the tile module, wherein the controlling pin for one select input pin is the data output pin of an instance of the at least one configuration-memory-cell module of the tile module; and for each select input pin of each instance of the at least one sub-module of the tile module, outputting a specification of the select input pin and the controlling pin for the select input pin; wherein the determining the controlling pin for each select input pin of each instance of the at least one sub-module of the tile module includes: searching the netlist from each select input pin of each instance of the at least one sub-module of the tile module to at least one reachable pin that is functionally connected to the select input pin, each reachable pin and the select input pin being functionally connected if a logical value of the reachable pin is equal to a logical value of the select input pin during operation of the PLD design; and determining the controlling pin as the reachable pin that is one of an input pin of the tile module and the data output pin of an instance of the at least one configuration-memory-cell module of the tile module.