Patent ID: 8675444

Claim:
A multi-processor system, comprising: multiple processors; a partitioned memory subsystem; multiple memory controllers coupling the multiple processors to the partitioned memory subsystem, wherein the multiple memory controllers includes a master memory controller that is configured to: accept a synchronization command, wherein the synchronization command includes command data that includes an associated synchronization indication for each of the multiple memory controllers, and wherein each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem; in response to receiving the synchronization command, forward the synchronization command to the multiple memory controllers; in response to receiving the forwarded synchronization command, de-assert an associated status bit; in response to receiving the forwarded synchronization command, determine whether the associated synchronization indication is asserted; in response to the associated synchronization indication being asserted, transmit the forwarded synchronization command to associated power control logic; and in response to the associated synchronization indication not being asserted, refrain from transmitting the forwarded synchronization command to the associated power control logic.