Patent ID: 7484028

Claim:
A bus bridge for coupling a device to an interface bus, the interface bus having address lines, data lines, and at least one read/write line, the device having a memory unit, the interface bus having a first address space assigned to the memory unit, the bus bridge comprising: a memory bus to couple to the memory unit and having a second address space assigned to the memory unit; a transaction buffer; a read buffer; a write buffer; a bus-interface manager that monitors signals of the interface bus for a bus request to read data from the first address space or to write data to the first address space, the bus-interface manager storing a transaction request to the transaction buffer in response to receiving a bus request and also storing the values of the data lines to the write buffer if the bus request is a request to write data, the transaction request having an address value to the second address space and an indication of whether the transaction request is a read request or a write request; and a memory-interface manager that reads the transaction request from the transaction buffer, and when the transaction request is a write request, reads the write data from the write buffer and outputs it onto the memory bus with an indication that it be stored in at least one memory location identified by the address value in the second address space, and when the transaction request is a read request, generates a request on the memory bus to read data from at least one memory location identified by the address value in the second address space and thereafter copies the read data to the read buffer; and wherein the bus-interface manager transfers the stored read data from the read buffer to data lines of the interface bus.