Patent ID: 7480177

Claim:
A multi-bit nonvolatile semiconductor memory device, comprising: a memory cell array including a bit line connected to a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are programmable into more than two threshold voltage states in order to store more than one bit of data; a page buffer circuit which stores a logic value as main latch data and which is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line; and a sub-latch circuit which stores a logic value as sub-latch data and which is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line; wherein the page buffer circuit and the sub-latch circuit are connected to the bit line at opposite sides of the memory cell array.