Patent ID: 7723198

Claim:
A method for producing an integrated semiconductor cascode circuit having an emitter layer, a first base region, a second base region, a collector region, and an intermediate region of a semiconductor material having a conductivity that is opposite a conductivity of the second base region, the first base region being provided between the emitter layer and the intermediate region, and the second base region being provided between the intermediate region and the collector region, the method comprising: defining at least one dielectrically delimited active collector region in a semiconductor body; generating, on the collector region, a layer sequence from the second base region and a second subregion of the intermediate region; generating, on the second subregion, a dielectric layer having a central opening and an outer edge; generating, on the dielectric layer and on a second subregion that is exposed inside the central opening and outside the outer edge, a layer sequence from the first subregion of the intermediate region and the first base region; generating the emitter layer on the first base region; etching a mesa structure with a first cross section by using a first mask, a second mask resting offset on one side on the first mask, and a third mask defined by the outer edge of the dielectric layer, wherein the etching removes material in the dielectric area; and increasing a dopant concentration in a first terminal region and in a second terminal region.