Patent ID: 8912517

Claim:
A memory cell comprising: a first resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal; a second resistive switching element comprising a second high resistance state and a second low resistance state and having a first terminal and a second terminal; and a transistor including a first terminal, a second terminal, and a third terminal, the first terminal of the transistor coupled to the first terminal of the first resistive switching element, the second terminal of the transistor coupled to the first terminal of the second resistive switching element, the third terminal of the transistor coupled to a word line, wherein the first terminals of the first and the second resistive elements are anode or cathode terminals, wherein the second terminals of the first and the second resistive elements are cathode or anode terminals, wherein the first and the second terminals of the transistor are both coupled to anode terminals of the first and the second resistive switching elements or to cathode terminals of the first and the second resistive switching elements.