Patent ID: 7877531

Claim:
An image processing apparatus comprising: an input section configured to have a total of m channels with input means for admitting pixel data output by imaging means on a pixel-by-pixel basis and in parallel, m being a positive integer, and arithmetic means arithmetically processing said pixel data input to said input means; a bus configured to be connected to said input section, said bus being further configured to transmit said pixel data processed arithmetically by said arithmetic means; a memory interface configured to be connected to said bus, said memory interface being further configured to write to a memory said pixel data arithmetically processed by said arithmetic means, said memory interface being further configured to control access to said memory in accordance with an access request from a processing unit connected to said bus; an output section configured to be connected to said memory interface through said bus, said output section being further configured to request said memory interface for access to said memory in order to read the pixel data therefrom for output to the outside; and a control section configured to change at least one of three parameters including a parallelly processed pixel count, a data bus width, and a memory interface data width in accordance with the number of the pixels represented by the pixel data which are acquired by said imaging means and input parallelly to said input section, said parallelly processed pixel count being the number of the pixels represented by the pixel data which are processed parallelly by said arithmetic means, said data bus width being one over which said bus transmits data, said memory interface data width being one over which said memory interface gains access to said memory.