Patent ID: 8153484

Claim:
A method comprising the steps of: forming first and second source/drain regions of a given transistor in a semiconductor layer, the first and second source/drain regions being of a first conductivity type and the semiconductor layer being of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and spaced apart relative to one another; and forming a gate of the given transistor above and electrically isolated from the semiconductor layer, the gate being formed at least partially between the first and second source/drain regions; wherein at least a given one of the first and second source/drain regions of the given transistor is formed having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region; and wherein the step of forming at least the given source/drain region of the given transistor comprises forming a plurality of trenches within the given transistor in the semiconductor layer proximate the upper surface of the semiconductor layer.