Patent ID: 6921946

Claim:
A test structure for testing misalignment between adjacent implanted regions of opposite conductivity type in a semiconductor device, said test structure ( 1 ) being arranged on a semiconductor substrate, comprising a first triple well-structure and a second triple well-structure, said second triple well-structure adjacent to said first triple well-structure in a first direction along the surface of said substrate, each triple well-structure comprising a lower buried n-well region, a high voltage p-well region, a p + -region, a high voltage n-well region and a n + -region, said lower buried n-well region being arranged on said semiconductor substrate, said high voltage p-well region being arranged on top of said buried n-well region, said p + -region being arranged on top of said high voltage p-well region as emitter, said high voltage n-well region being arranged on top of said semiconductor substrate and laterally adjacent to said high voltage p-well region, said n + -region being arranged on top of high voltage n-well region as base, characterized in that in said test structure a central portion of said base and a central portion of said high voltage n-well region are common to said first and said second triple well structure, said second triple well-structure being mirrored in said first direction relative to said first triple well-structure using said central portion of said base as a symmetry line running in a second direction perpendicular to said first direction, said symmetry line having a width and between said central portion of said base and said high voltage p-well region in said first triple well-structure a first overlay distance in said first direction is provided, and between said central portion of said base and said high voltage p-well region in said second triple well-structure a second overlay distance in said first direction is provided.