Patent ID: 7406669

Claim:
A method for enabling clock reconvergence pessimism removal (CRPR) in an extracted timing model (ETM), the method comprising: locating a plurality of clocks defined within a core; determining if one of the plurality of clocks are clocking data both within the core and outside of the core, said determining if one of the plurality of clocks are clocking data both within the core and outside of the core comprising: connecting input pins with input ports and output pins with output ports; defining standard time constraints and chip level constraints; applying global timing derating; activating a CRPR algorithm; and generating a timing report on each of the output ports; generating a CRPR clock for an output pin of a last cell in a clock path common to an internal register clock pin and one of the plurality of clocks clocking data both within the core and outside of the core; and utilizing a static timing analysis tool to calculate the CRPR from the CRPR clock.