Patent ID: 7078970

Claim:
An operational amplifier comprising: a Class AB output stage having an output terminal and an input stage driving the output stage, said Class AB output stage comprising a pair of p-channel and n-channel output transistors (MP 0 , MN 0 ) series-connected between the VDD and VSS supply terminals of a power supply, each of said output transistors having associated driving and biasing circuitry with a pair of differential driving inputs (VP 1 i , VP 2 i ; VN 1 i , VN 2 i ) and a biasing input (VPi; VNi); and said input stage comprising driving outputs (VP 1 o , VP 2 o , VN 1 o , VN 2 o ) connected to corresponding driving inputs (VP 1 i , VP 2 i ; VN 1 i , VN 2 i ) of said output stage, each driving output being derived from the drain of a MOS transistor (MN 21 , MP 20 , MN 19 , MP 19 ) connected in series with a diode connected MOS transistor (MP 23 , MN 17 , MP 24 , MN 16 ) between the VDD and VSS supply terminals, wherein said input stage has a pair of biasing outputs (VPo, VNo) each connected to a corresponding one of the pair of biasing inputs (VPi, VNi) of the output stage, a first one (VPo) of said biasing outputs being derived from the connected drains of a complementary MOS transistor pair connected in series between the VDD and VSS supply terminals, a first one of said transistor pair being a diode connected MOS transistor (MP 25 ) and a second one (MN 22 ) being connected as an inverter and having a control gate connected to the drain of a bias current control transistor (MN 14 ) the drain of which is supplied with a bias current (IBIAS).