Patent ID: 7760567

Claim:
A semiconductor memory comprising: a plurality of memory cells provided at positions where a plurality of word lines and a bit line pair intersect with each other, respectively; a word line driving circuit activating one of the plural word lines in accordance with transition from a standby period to an active period; a first precharge circuit coupling the bit line pair to a precharge voltage line in the standby period, and separating at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of the word line driving circuit; a sense amplifier amplifying a voltage difference of a node pair corresponding to the bit line pair after the operation start of the word line driving circuit; and a switch circuit provided between the bit line pair and the node pair, wherein the switch circuit includes a first switch circuit and a second switch circuit, wherein the first switch circuit couples the access side of the bit line pair to an access side of the node pair, based on a first control signal, at a timing of the operation start of the word line driving circuit, and the second switch circuit separates a non-access side of the bit line pair from a non-access side of the node pair, based on a second control signal, at a timing of operation start of the sense amplifier.