Patent ID: 8134418

Claim:
A varactor circuit, comprising: a first varactor, a second varactor, a third varactor, and a fourth varactor; wherein a first source-drain node of the first varactor is coupled to a first input node; a second source-drain node of the second varactor is coupled to the first input node; a first gate node of the first varactor is coupled to a first output node; a second gate node of the second varactor is coupled to a second output node; a third gate node of the third varactor is coupled to a second input node; a fourth gate node of the fourth varactor is coupled to the second input node; a third source-drain node of the third varactor is coupled to the first output node; a fourth source-drain node of the fourth varactor is coupled to the second output node; a resistance bridge coupled to the first gate node, the second gate node, the third source-drain node, and the fourth source-drain node; the resistance bridge including at least one common mode voltage node; and capacitors coupled for DC decoupling of a common mode voltage at the at least one common mode voltage node from a first sinusoidal voltage and a second sinusoidal voltage respectively at the first output node and the second output node; wherein the resistance bridge includes: a first resistor and a second resistor coupled to one another between the first gate node and the third source-drain node; a third resistor and a fourth resistor coupled to one another between the second gate node and the fourth source-drain node; the first resistor, the second resistor, the third resistor, and the fourth resistor connected to one another at the at least one common mode voltage node to couple the common mode voltage to each of the first gate node, the second gate node, the third source-drain node, and the fourth source-drain node; and wherein the capacitors include: a first capacitor coupled between the first output node and the first gate node: a second capacitor coupled between the second output node and the second gate node; a third capacitor coupled between the first output node and the third source-drain node; and a fourth capacitor coupled between the second output node and the fourth source-drain node.