Patent ID: 8693796

Claim:
An image processing apparatus comprising: a memory configured to store a plurality of data in a plurality of memory locations, wherein an ordinally specified data is in a corresponding ordinal memory location; and an arithmetic operation unit configured to receive data from the memory, and updating the memory with results of arithmetic operations performed on the at least one of the plurality of data, wherein in a first stage the arithmetic operation unit is configured to update for use in a second stage: a first memory location with a sum of first and eighth data, a second memory location with a sum of second and seventh data, a seventh memory location with a difference between the second and the seventh data, and an eighth memory location with a difference between the first and the eighth data, wherein in the second stage the arithmetic operation unit is configured to update for a third stage: a third memory location with a sum of third and sixth data, a fourth memory location with a sum of fourth and fifth data, a fifth memory location with a difference between the fourth and the fifth data, and a sixth memory location with a difference between the third and the sixth data, and wherein, at the third stage the arithmetic operation unit is configured to update for a fourth stage: the fifth memory location with a sum of the fifth and the sixth data, the sixth memory location with a sum of the sixth and the seventh data, and the seventh memory location with a sum of the seventh and the eighth data.