Patent ID: 7366306

Claim:
A programmable logic device (PLD) comprising: configuration memory; programmable logic circuitry coupled to the configuration memory; programmable routing circuitry coupled to the configuration memory and configured to inter-couple the programmable logic circuitry; an access port adapted to receive encrypted configuration data; a decryptor adapted to receive the encrypted configuration data and to execute a decryption algorithm for decrypting the encrypted configuration data to produce decrypted configuration data; a key memory connected to the decryptor and having first and second decryption-key storage locations identified by respective first and second decryption-key addresses; and a secure-key address register adapted to receive one of the first and second decryption-key addresses to provide access to the one of the first and second decryption-key addresses; wherein the first decryption-key storage location stores a first decryption key for decrypting a first subdesign included in the encrypted configuration data; wherein the second decryption-key storage location stores a second decryption key for decrypting a second subdesign included in the encrypted configuration data; configuration logic coupled to the configuration memory and to the decryptor, the configuration logic adapted to write decrypted configuration data to the configuration memory; and a secure-key-flag register coupled to the key memory, wherein responsive to a first value in the secure-key-flag register and an address loaded in the secure-key address register, key memory at the address is cleared before permitting read and write access to the key by the configuration logic, and responsive to a second value read and write access to the key memory by the configuration logic is disabled.