Patent ID: 8471302

Claim:
An apparatus comprising: a first back-gate region; a first MOS transistor that is adjacent to the first back-gate region; a second MOS transistor, wherein the gate of the first MOS transistor is coupled to the gate of the second MOS transistor; a second back-gate region located between the first and second MOS transistors; an isolation region that is adjacent to the second MOS transistor; a third back-gate region; a third MOS transistor that is adjacent to the third back-gate region, wherein the drain of the third MOS transistor is coupled to the drain and source of the second MOS transistor; a fourth MOS transistor that is adjacent to the isolation region, wherein the gate of the fourth MOS transistor is coupled to the gate of the third transistor, and wherein the drain and source of the fourth MOS transistor are the drain of the first MOS transistor; and a fourth back-gate region formed between the third and fourth transistors, and wherein the first, second, third, and fourth back-gate regions are coupled together.