Patent ID: 7649780

Claim:
A semiconductor memory device comprising: a memory cell array having memory cells or memory cell units including at least one memory cell, the memory cells or the memory cell units being arranged in an array form; a bitline connected to at least one of the memory cells or the memory cell units; a read circuit including a precharge circuit; and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor during a first period, a second voltage is applied to the gate of the first transistor during a second period after the first period, a third voltage is applied to the gate of the first transistor during a third period after the second period, the bitline is precharged to a fourth voltage by the precharge circuit via the first transistor during the first period, the first voltage is higher than the third voltage, the second voltage is lower than the third voltage, and the read circuit senses a change in a voltage of the bitline during the third period or after the third period.