Patent ID: 7836262

Claim:
A processor comprising: A data cache; and An interface unit comprising a memory request buffer coupled to receive a victim block evicted byte the data cache to be written back to memory, wherein the memory request buffer is further coupled to receive a first cache fill request corresponding to a load memory operation that missed in the data cache, wherein the memory request buffer is configured to store the first cache fill request awaiting transmission to memory to read data from the memory, and wherein the interface unit is configured to convert the victim block writeback into a second cache fill for the data cache responsive to detecting at least one store memory operation to the victim block prior to writing the victim block to memory and subsequent to the victim block being evicted from the data cache, and wherein the interface unit is configured to return the victim block to the data cache as the second cache fill in response to detecting the at least one store memory operation, and wherein the interface unit is configured to transmit the first cache fill request to memory and to return the read data as a first cache fill to the data cache in response to receiving the read data from memory.