Patent ID: 8890119

Claim:
A vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the transistor comprising: a group IV or group III-V epitaxial source semiconductor layer vertically aligned with an epitaxial group IV or group III-V drain semiconductor layer along the longitudinal axis; a group IV or group III-V epitaxial channel semiconductor layer disposed between source and drain semiconductor layers, the channel semiconductor layer having an epitaxial film thickness, wherein the source semiconductor layer has a lower effective mass along a transport direction and/or a higher density of states mass in the plane perpendicular to the transport direction than that of the channel and drain semiconductor layers; and an annular gate electrode surrounding a sidewall of the semiconductor channel layer, separated by an annular gate dielectric layer, and wherein the composition of at least one of the gate electrode or the semiconductor layers varies along the longitudinal axis.