Patent ID: 7254067

Claim:
In a memory device having a plurality of write receivers to which respective write data bits may be applied from a plurality of respective data bus terminals and a plurality of read transmitters that may apply respective read data bits to the respective data bus terminals, a method of operating the write receivers in either a first mode or a second mode, the method comprising: applying power to the write receivers regardless of whether the write data bits are being applied to the write receivers when the read transmitters are not active when the write receivers are being operated in the first mode; removing power from the write receivers when the read transmitters are active when the write receivers are being operated in the first mode; applying power to the write receivers when the write data bits are being applied to the write receivers when the write receivers are being operated in the second mode; and removing power to the write receivers when either the write data bits are not being applied to the write receivers or the read transmitters are active when the write receivers are being operated in the second mode.