Patent ID: 8572299

Claim:
A hardware accelerator module driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the system processor, the hardware accelerator module comprising: a register interface block adapted to receive at least one parameter set from the system processor; an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by the at least one parameter set, and to output the processed streaming data; and a parameter buffering block to receive the at least one parameter set from the register interface block, adapted to consecutively store the at least one parameter set, and to sequentially provide the at least one parameter set to the accelerator core as a function of a busy state received from the accelerator core; the parameter buffering block further adapted to provide a signal to the system processor indicative of a non-busy state of the accelerator core when the parameter buffering block is empty and the accelerator core is idle; the parameter buffering block including first and second finite state machines, a buffer for storing the at least one parameter set, and a parameter output register coupled to the buffer and to receive the at least one parameter set, the parameter output register to provide the at least one parameter set to the accelerator core.