Patent ID: 7359279

Claim:
An integrated circuit comprising: a memory array having a respective plurality of array lines of a first type for each of at least one memory layer; a plurality of I/O bus lines; a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines, said plurality of layer selector circuits comprising: layer selector circuits of a first type for coupling array lines on a first memory layer to a first group of said I/O bus lines; layer selector circuits of a second type for coupling array lines on a second memory layer, if such second memory layer is present, to the first group of said I/O bus lines; layer selector circuits of a third type for coupling array lines on the first memory layer to a second group of said I/O bus lines; and layer selector circuits of a fourth type for coupling array lines on the second memory layer, if such second memory layer is present, to the second group of said I/O bus lines; and control circuitry for selectively enabling certain layer selector circuits, said control circuitry configured, and said layer selector circuits arranged, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether the second memory layer is present.