Patent ID: 8665629

Claim:
An integrated circuit comprising: a memory cell comprising a resistivity changing memory element and a first select transistor electrically coupled to the resistivity changing memory element, wherein the first select transistor comprises a FinFET comprising a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain, the fin structure comprising a channel area extending in a direction substantially parallel to the surface of the substrate, wherein one of the source and drain is electrically coupled to the resistivity changing memory element, wherein a dielectric layer is formed around at least a portion of the channel area such that an effective channel width of the first select transistor depends at least in part on a height of the fin structure, wherein a maximum switching current of the resistivity changing memory element depends at least in part on the height of the fin structure, and wherein a single gate surrounds the dielectric layer, the single gate controlling a flow of current through the channel area.