Patent ID: 7212432

Claim:
A resistive memory cell random access memory device comprising: a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split current lines; and an array of resistive memory cells arranged in columns defined by the first current lines and rows defined by the third current lines, each resistive memory cell including a resistive memory element and an access transistor connected in series, each memory cell being connected between one of the first current lines and a reference potential, wherein the access transistors being FinFET-type field effect transistors, each one having two independent gates and a common floating body, and wherein each third current line being connected to one of the two independent gates of each one of the access transistors of a row of said array and being connected to one of the two independent gates of each one of the access transistors of an adjacent row of the array; wherein the first current lines being bit lines, the second current lines being write word lines, and the third current lines being word lines.