Patent ID: 7649769

Claim:
A circuit array, comprising: a plurality of cells arranged in an organization of words, each word having a plurality of bits; a plurality of bit lines, a plurality of word lines, and a plurality of reference lines, wherein each word line of the plurality of word lines and each bit line of the plurality of bit lines are shared among at least a subset of cells of the plurality of cells; each cell of the plurality of cells being coupled to a bit line of the plurality of bit lines, a word line of the plurality of word lines, and a reference line of the plurality of reference lines, the cell including a field effect transistor and a nanotube switching element, wherein the nanotube switching element includes a nanotube article positioned between a set electrode and a release electrode, wherein the plurality of cells are arranged in a plurality of pairs of cross-coupled cells, each pair of cross-coupled cells being constructed and arranged such that the set electrode of a first cell of that pair is coupled to the release electrode of a second cell of that pair, the release electrode of the first cell of that pair is coupled to the set electrode of the second cell of that pair, the source of the first cell of that pair is coupled to the set electrode of the first cell of that pair, the source of the second cell of that pair is coupled to the release electrode of the second cell of that pair, and the nanotube articles of the pair are coupled to a reference line of the plurality of reference lines.