Patent ID: 7433257

Claim:
A semiconductor memory device with a power supply voltage control function, comprising: a plurality of word lines; a plurality of bit lines; a plurality of power supply lines; a plurality of memory cells connected to the word lines, the bit lines and the power supply lines; a plurality of word line driver circuits, each of which drives each of the corresponding word lines; and a plurality of memory cell power supply voltage control circuits each of which supplies a predetermined power supply voltage via a power supply line to the memory cell that is connected to a word line being active, and supplies, via a power supply line to a memory cell that is connected to a word line being inactive, a voltage that is lower than the predetermined power supply voltage and is greater than or equal to a lowest possible level with which the memory cells can hold data, wherein: the number of gates provided between an input and an output of each word line driver circuit is larger than the number of gates provided between an input and an output of each memory cell power supply voltage circuit; the memory cell power supply voltage control circuit includes first to third transistors; the first transistor is connected to a power supply terminal, to which the predetermined power supply voltage is applied, and the second transistor; the second transistor is connected in a diode-type gate connection between the first transistor and the third transistor; the third transistor is connected to the second transistor and a ground terminal; and the first and third transistors are controlled based on an external addressing signal.