Patent ID: 8154084

Claim:
A method, comprising: forming a spacer layer above a first gate electrode structure of a first transistor and a second gate electrode structure of a second transistor, said first gate electrode structure comprising a first cap layer and said second gate electrode structure comprising a second cap layer; forming an etch stop layer above said spacer layer; forming a first mask above said etch stop layer, said first mask covering said second transistor and exposing said first transistor; after forming said first mask, removing said etch stop layer from above said first transistor; after removing said etch stop layer from above said first transistor, forming a first sidewall spacer at sidewalls of said first gate electrode structure from said spacer layer, and thereafter forming first cavities in first drain and source areas of said first transistor using said first sidewall spacer and said first cap layer as a mask; forming a first strained semiconductor material in said first cavities; after forming said first strained semiconductor material, forming a second sidewall spacer at sidewalls of said second gate electrode structure from said spacer layer, and thereafter forming second cavities in second drain and source areas of said second transistor using said second sidewall spacer and said second cap layer as a mask; and forming a second strained semiconductor material having a different material composition than said first strained semiconductor material in said second cavities.