Patent ID: 6912558

Claim:
A multiplication module, including a first input unit and a second input unit, for multiplying in bits of data in a Galois field GF(2 m )(m≧1), comprising: first and second power arithmetic means for receiving the first m bits of data from said first input unit; first multiplication means for receiving said first m bits of data and the output of said first power arithmetic means; second multiplication means for receiving second in bits of data from said second input unit and the output of said second power arithmetic means; selection means for receiving an output signal from said second multiplication means and said second in bits of data; and control means for outputting a control signal to said first power arithmetic means, said second arithmetic means and said selection means, wherein said first power arithmetic means receives a first control signal, said second power arithmetic means receives a second control signal, and said selection means receives a third control signal, for controlling the output of said selection means, while said first multiplication means outputs a first output signal, and said selection means outputs a second output signal.