Patent ID: 7477714

Claim:
A phase adjusting circuit ( 12 ) for the generation of a clock output signal (CLK out ) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals, said circuit having an interpolator unit ( 30 ) which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, the interpolator unit being controlled externally by a control signal (PH fine ) to execute a phase step when the phase of the clock output signal is to be shifted, wherein the phase adjusting circuit ( 12 ) comprises a synchronization unit ( 40 ) which synchronizes the phase step with the clock output signal, wherein the synchronization unit ( 40 ) comprises a command input ( 42 ) for receiving a phase step command, a detector for detecting when the phase of the clock output signal is within a phase window (Δφ) in which a phase step can be executed without adding phase jitter to the clock output signal, and a latch ( 50 ) for forwarding the phase step command to the interpolator when the phase of the clock output signal is within said phase window.