Patent ID: 8819398

Claim:
A circuit comprising: a pipeline having a plurality of stages linked in series by a plurality of registers, said registers being governed by a clock signal having (i) a first frequency in a first mode and (ii) a second frequency in a second mode; a first configuration circuit disposed in said pipeline, said first configuration circuit bypassing a first particular one of said registers while in said second mode to form a first combined stage, said first combined stage comprising a first of said stages adjoining said first particular register and a second of said stages adjoining said first particular register; and a controller configured to operate said pipeline in a third mode in response to an assertion of a control signal, wherein (i) said third mode transitions said pipeline from said first mode to said second mode, (ii) said clock signal is halted during all of said third mode, (iii) said third mode is at least as long as a period of said second frequency and (iv) said pipeline is filled with a plurality of non-operation commands by an end of said first mode in preparation to enter said third mode.