Patent ID: 8289788

Claim:
A system comprising: a control section; and a plurality of memory devices that are bus connected to the control section with a clock signal line and a data signal line, each of the plurality of memory devices prestoring identification information for distinguishing the memory device from the other memory devices, wherein the control section performs a write operation, in synchronism with a clock signal, for transferring write data to one of the plurality of memory devices, utilizing: (i) an identification information transmission period during which the control section sends the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device; (ii) a write data transmission period during which the control section sends a single set of write data having a prescribed size to the selected single memory device; and (iii) a response period during which the selected single memory device responds to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data, wherein communications between the control section and the selected memory device during the write data transmission period and the response period are repeatedly performed for each transmission of one of plural sets of write data having the prescribed size, and the control section sets a frequency of the clock signal during the response period to a lower value than that of the clock signal during the write data transmission period.