Patent ID: 7369456

Claim:
A DRAM memory, comprising: at least one memory cell bank comprising memory cells which can be activated by means of internal row and column access instructions; each memory cell bank comprising an associated autoprecharge (APC) counter for delaying a column access instruction with autoprecharge; a command decoder generating, dependent on an external memory access instruction, at least one column access instruction within a first decoding time and at least one row access instruction within a second decoding time; and a clock signal delay circuit for delaying an external clock signal with the first decoding time in order to generate an internal column clock signal and for delaying the external clock signal with the second decoding time in order to generate an internal row clock signal; wherein each of the column access instructions generated by the command decoder are respectively delayed by an associated shift register being clocked by the internal column clock signal in order to generate the internal column access instructions, and wherein the APC counter is clocked by the internal row clock signal and delays each of the column access instructions generated by the command decoder in accordance with an associated programmable count in order to produce an internal autoprecharge instruction for the associated memory cell bank.