Patent ID: 8365133

Claim:
A testing apparatus comprising: a vector memory unit to store original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described; a vector generator to generate, from the original test vector data stored in the vector memory unit, generated test vector data different from the original test vector data; an output part to output test vector data to be inputted to the circuit subjected to inspection; a fault occurrence rate memory unit to store a fault occurrence rate of the input signal; a random number generator to generate random number data; and a comparison part to compare the fault occurrence rate of the input signal stored in the fault occurrence rate memory unit with the random number data; wherein the vector output part outputs the generated test vector data in a case that the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data in a case that the random number data is larger than the fault occurrence rate of the input signal; further comprising a program memory unit to store a conversion program in which is described a conversion rule to generate verification test vector data from the standard test vector data, the verification test vector data describing an input signal different from the standard input signal that can be inputted to the circuit subjected to inspection, the standard test vector data describing the standard input signal to be inputted to the circuit subjected to inspection, wherein the vector generator executes the conversion program to generate the generated test vector data from the original test vector data; wherein the vector memory unit stores a plurality of items of the original test vector data in which a plurality of input signals to be inputted to the circuit subjected to inspection are described; the fault occurrence rate memory unit stores, as a fault occurrence rate of the input signal described in one original test vector data item of the plurality of original test vector data items, a low fault occurrence rate in a case that no fault occurs in another original test vector data item and a high fault occurrence rate in a case that a fault occurs in the other original test vector data item; and the comparison part compares the low fault occurrence rate with the random number data in a case that no fault occurs in the another original test vector data item, and compares the high fault occurrence rate with the random number data in a case that a fault occurs in the another original test vector data item.