Patent ID: 8041929

Claim:
An apparatus for processing a thread of a plurality of threads that share a core processor, comprising: an instruction random access memory (IRAM) for storing one or more sequences of instructions; a bank of registers for storing data that is used as operands and results of the one or more series of instructions for a plurality of threads, said bank of registers including a bank address input for accessing a register in the bank of registers; a thread ID input channel that has a width of T bits for receiving data that indicates a current thread identifier (ID) of a plurality of up to 2 T threads, said thread ID input channel connected to T bits of the bank address input; a core processor for executing the one or more sequences of instructions for a current thread of the plurality of threads by accessing contents of a register for up to 2 c registers for the current thread in the bank of registers; a core register access channel with a width of C bits, which connects the core processor to C bits of the bank address input different from the T bits to which the thread ID input channel is connected, wherein the bank of registers includes a plurality of registers, the bank address input includes a number C+T bits, and an intra-thread register indicated by the core processor has an intra-thread address that has C bits, whereby, for a particular intra-thread register indicated on the core register access channel, a particular register accessed by the bank address input holds data that indicates contents for the particular intra-thread register for a thread having the current thread ID; a data random access memory (data RAM) for storing additional data for the plurality of threads, said data RAM including a data RAM address input for accessing contents of a location in the data RAM; and a core data RAM channel with a width of D bits, which connects the core processor to D bits of the data RAM address input.