Patent ID: 7478213

Claim:
A computer memory system comprising: a controller capable of producing memory control data; an interface coupled to the controller and capable of propagating in a single input-output data bus reset and mode information on a single line; one or more memory devices coupled to the interface and each one capable of managing data storage by receiving the memory control data; a reset circuit within each of the one or more memory devices, the reset circuit coupled to the interface and configured to produce at least one of a reset signal and a mode assertion signal; a decoder within each of the one or more memory devices, the decoder coupled to the interface and configured to receive address, data, and command information over the single input-output data bus; and a set of control circuitry within each of the one or more memory devices, each set of control circuitry coupled to a respective decoder and capable of producing signaling to control reading, erasing, and programming operations wherein the decoder is capable of decoding command information that is encoded to contain a succession of group code fields each adjoining a control data field, the decoder configured to decode the group code fields to direct placement of each corresponding control data field into control groups within a control word in the one or more memory devices.