Patent ID: 6869807

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming a thin film on a substrate to be subjected to light exposure; applying resist on the substrate; exposing a product circuit pattern on an exposure original plate on the substrate having said resist applied thereon; developing the exposed resist to form a pattern of the resist, and etching said substrate with use of the developed resist pattern as a mask to form a pattern of said thin film, wherein said light exposure step further includes: a first step of previously acquiring differences in the quantity of exposure light and focus between the product circuit pattern within said exposure original plate and a test pattern; a second step of linking a sectional shape of the test pattern or a signal waveform associated with the sectional shape to deviations from the optimum values of the exposure light quantity and focus and storing them as linked information; a third step of measuring the sectional shape of said test pattern formed on said substrate through said light exposure step or the signal waveform associated with the sectional shape; a fourth step of calculating deviations from optimum values of the exposure light quantity and focus of said test pattern in said light exposure step on the basis of said sectional shape of said test pattern or said signal waveform associated with the sectional shape measured in said third step and on the basis of said linked information of said second step; a fifth step of calculating deviations from the optimum values of the exposure light quantity and focus of said product circuit pattern on the basis of said deviations from the optimum values of the exposure light quantity and focus relating to said test pattern obtained in said fourth step and on the basis of said differences in the optimum values of the exposure light quantity and focus between said product circuit pattern and said test pattern obtained in said first step; and a sixth step of feeding said deviations from the optimum values of the exposure light quantity and focus of said product circuit pattern calculated in said fifth step back to said light exposure step.