Patent ID: 8756558

Claim:
An apparatus comprising: a first array segment having: an first array of ferroelectric memory cells arranged into a first set of rows and a first set of columns, wherein each row from the first set of rows is associated with at least one bitline from a first set of bitlines and at least one plateline from a first set of platelines, and wherein each column from the first set of columns is associated with at least one wordline from a first set of wordlines; and a first set of bitline cells, wherein each bitline is coupled to at least one bitline from the first set of bitlines; a second array segment having: an second array of ferroelectric memory cells arranged into a second set of rows and a second set of columns, wherein each row from the second set of rows is associated with at least one bitline from a second set of bitlines and at least one plateline from a second set of platelines, and wherein each column from the second set of columns is associated with at least one wordline from a second set of wordlines; and a second set of bitline cells, wherein each bitline is coupled to at least one bitline from the second set of bitlines; a sensing circuit that is located between the first array segment and the second array segment, wherein the second circuit includes a plurality of sense amplifiers, and wherein each sense amplifier is coupled to at least one bitline from the first set of bitlines and it coupled to at least one bitline from the second set of bitlines; a first plate driver that is coupled to each plateline from the first set of platelines and that is located substantially adjacent to the first array segment; a second plate driver that is coupled to each plateline from the second set of platelines and that is located substantially adjacent to the second array segment; a first row interface circuit that is coupled to each wordline from the first set of wordlines and that is located substantially adjacent to at least one of the first plateline drivers and the first array segment; a second row interface circuit that is coupled to each wordline from the second set of wordlines and that is located substantially adjacent to at least one of the second plateline drivers and the second array segment; a wordline boost circuit that is coupled to the first and second row interface circuits and that is between the first and second row interface circuits; an input/output (IO) bus that is coupled to each sense amplifier and that is located substantially adjacent to at least one of the first and second array segments; an error correcting code (ECC) logic circuit that is coupled to and is substantially adjacent to the IO bus; and a controller that is coupled to the IO bus, the ECC logic, the sensing circuit, the first row interface circuit, and the second row interface circuit, wherein the controller is substantially adjacent to at least one of the first and second row interface circuits, the IO bus, and the ECC logic circuit.