Patent ID: 7478346

Claim:
A method for designing and debugging an IC comprising the steps of: a. generating a register transfer level (RTL) design for the IC, wherein the RTL design describes the IC as comprising a hierarchy of logic modules communicating via signals, and describes the logic modules according to their behavior by describing logical relationships between signals they transmit and receive; b. processing the RTL design to synthesize a gate level design for the IC, wherein the gate level design describes the logic blocks as comprising instances of cells communicating via signals; c. processing the gate level design to produce a first gate level dump file referencing signals of the gate level design and indicating how the signals of the gate level design would behave over a period of time in response to time-varying signals supplied as inputs to the IC; d. processing the first gate level dump file to produce a first RTL dump file referencing signals of the RTL design and indicating how the signals of the RTL design would behave in response to the time-varying signals supplied as inputs to the IC; and e. processing the first RTL dump file to produce displays depicting behavior of signals of the RTL design indicated by the first RTL dump file.