Patent ID: 7547932

Claim:
A vertical gate-depleted single electron transistor device, comprising: a substrate; a plurality of layers of basic materials and tunneling barriers fabricated on top of the substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials; a mesa fabricated on top of the layers of basic materials and tunneling barriers; an ohmic contact fabricated on top of the mesa; and one or more gate Schottky contacts fabricated on top of the layers of basic materials and tunneling barriers; wherein: a source voltage is applied to the ohmic contact and the source voltage is set as zero; a drain voltage is applied to the substrate and the drain voltage is set to less than 0.1; a gate voltage is applied to at least one of the gate Schottky contacts and the gate voltage is set as negative; so that a depletion region expands toward a center of the device and forms a lateral confinement to a quantum well and a quantum dot is obtained within the quantum well.