Patent ID: 6993641

Claim:
A processor comprising: a plurality of pipeline clusters, each cluster having a plurality of pipelines and each pipeline having a plurality of pipeline stages for executing an instruction on successive clock cycles; and stall control circuitry which controls the stalling of instructions in the pipelines in response to a stall signal generated in any one of the pipelines; the stall control circuitry being adapted to stall the execution of an instruction in a pipeline not generating the stall signal at least one clock cycle later than the execution of an instruction in a pipeline generating the stall signal, and to release the stall in the pipeline not generating the stall signal at least one clock cycle later than the stall in the pipeline generating the stall signal, the stall control circuitry being operable, when a pipeline of one cluster becomes locally stalled, to cause a global stall signal to be generated by that cluster and to be propagated to the other clusters to bring about stalling of the execution of instructions in the pipelines of those other clusters said one or more clock cycles after the stalling of said one cluster, and being further operable to inhibit a first cluster, having such a locally-stalled pipeline, from generating the global stall signal if a global stall signal generated by another locally-stalled pipeline in a second cluster is being propagated down the first cluster.