Patent ID: 7155561

Claim:
An integrated circuit memory device, comprising: at least one primary memory of the type that must be refreshed; a second memory of the type not required to be refreshed; an address decoder coupled to receive a memory address and being operable to decode the address and generate decoded address signals corresponding thereto; an input/output circuit coupled to the at least one primary memory, the second memory, and the address decoder, the input/output circuit being operable to respond to a first control signal by coupling write data from an external data terminal to a location in the at least one primary memory corresponding to the decoded address signals, or to respond to a second control signal by coupling write data from the external data terminal to a location in the second memory, or to respond to a third control signal by coupling data from the second memory to a location in the at least one primary memory corresponding to the decoded address signals; and a control circuit coupled to the at least one primary memory, the second memory, the address decoder, and the input/output circuit, the control circuit being operable to generate the first control signal when the location in the at least one primary memory corresponding to the decoded address signals is not being refreshed, to generate the second control signal when the location in the at least one primary memory corresponding to the decoded address signals is being refreshed, and to generate the third control signal when the location in the at least one primary memory corresponding to the decoded address signals that was being refreshed when the data was stored in one of the second memory is no longer being refreshed.