Patent ID: 7541855

Claim:
An electronic circuit arrangement, comprising: a current mode logic (CML) delay cell having a tuning voltage input on a gate of a first and second transistor, contributing to a load of the CML delay cell switching transistors, and a bias voltage input on a gate of a third transistor, as a current source I 0 ; and a compensation circuit having a plurality of switching point optimized inverters having a first plurality of transistors having a transconductance β pN and a second plurality of transistors having a transconductance β nN , wherein respective ratios of β nN /β pN determine an inverter switching point of a respective one of the switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M 0N comprising a third plurality of transistors that supply additional currents to the current source I 0 at a drain node of the third transistor.