Patent ID: 8114737

Claim:
A method for fabricating a memory array, comprising: fabricating first and second successively adjacent rows of memory cells on a first row of pillars, each pillar of the first row of pillars having one memory cell of the first row of memory cells and one memory cell of the second row of memory cells on opposite sides thereof; fabricating third and fourth successively adjacent rows of memory cells on a second row of pillars successively adjacent to the first row of pillars, each pillar of the second row of pillars having one memory cell of the third row of memory cells and one memory cell of the fourth row of memory cells on opposites side thereof, wherein the second and third rows of memory cells are successively adjacent to each other; fabricating a control gate between the first and second rows of pillars, the control gate to control the memory cells of the second and third rows of memory cells; fabricating a word line coupled to the control gate so that all of the memory cells of the second row of memory cells are coupled to one side of the word line and all of the memory cells of the third row of memory cells are coupled to an opposite side of the word line; and forming alternating first bit lines so that each of the memory cells of the second row of memory cells is coupled to a respective one of the alternating first bit lines and forming alternating second bit lines so that each of the memory cells of the third row of memory cells is coupled to a respective one of the alternating second bit lines; wherein the alternating first bit lines are different from the alternating second bit lines; and wherein an alternating second bit line is between a pair of alternating first bit lines and is successively adjacent to the alternating first bit lines of the pair of alternating first bit lines.