Patent ID: 7737756

Claim:
A level shift circuit which receives an input signal and outputs an output signal obtained by converting a logic level of the input signal, the level shift circuit comprising: a low voltage side circuit unit, operated by a first power supply voltage, for outputting the input signal and a reverse signal of the input signal as a pair of complementary signals; and a high voltage side circuit unit, operated by a second power supply voltage that is higher than the first power supply voltage and including a pair of n-type transistors for receiving the pair of complementary signals output from the low voltage side circuit unit at their gates, respectively, for outputting the output signal, wherein each of the pair of n-type transistors includes: a doped region which provides a plurality of drains and sources of the each of the pair of n-type transistor, the doped region having shorter sides along a first direction and longer sides along a second direction which is perpendicular to the first direction; and a plurality of gates arranged across the doped region, and aligning along the second direction which corresponds to a gate length direction, each of the plurality of gates extending along the first direction which corresponds to a gate width direction, the plurality of gates are electrically connected with one another, the plurality of drains are electrically connected with one another, and the plurality of sources are electrically connected with one another, the plurality of gates and the doped region are disposed in a rectangular area having a width W along the first direction and a height H along the second direction, the plurality of gates are arranged so that a total gate width which is a sum of gate widths of the plurality of gates disposed over the doped region is smaller than a sum of gate widths of a hypothetical n-type transistor, wherein the hypothetical n-type transistor includes at least one drain and at least one source provided in a hypothetical doped region, and at least two gates each extending along the second direction, aligning along the first direction and disposed across the hypothetical doped region, the hypothetical doped region and the at least two gates are disposed in a rectangular area having the width W along the first direction and the height H along the second direction, and the at least one drain, at least one source and at least two gates are arranged under the same design rule as the each of the pair of n-type transistors, and the design rule defines at least one of a gate length, a gate protruding length from the dopes region, a space between the gates and a width of source and drain.