Patent ID: 8923090

Claim:
A memory device comprising: a memory array comprising a plurality of memory cells; and a decoder to decode an address for accessing a memory cell in the memory array, wherein the decoder comprises: address latch circuitry which receives as input an address signal and generates address holding signals during a setup period of the memory array, wherein the address latch circuitry latches the address holding signals during an address hold period following the setup period; inverter circuitry which receives as input the address signal and generates a complementary address signal; and first address pre-decode circuitry which receives as input the address signal, the complementary address signal and the address holding signals, wherein the first address pre-decode circuitry decodes the address signal and the complementary address signal during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry, and wherein the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.