Patent ID: 8805917

Claim:
A circuit for performing a decimal fused-multiply-add (FMA) calculation, comprising: a partial product generation module comprising: a multiples generator unit configured to generate a plurality of multiples of a multiplicand for the decimal FMA calculation, wherein the multiplicand is in a m digit binary coded decimal (BCD) format; a recoding unit configured to generate n+1 signed digits (SD) sets from a multiplier sum vector and a multiplier carry vector of a multiplier for the decimal FMA calculation; and a multiples selection unit configured to generate a plurality of partial product vectors from the plurality of multiples of the multiplicand based on the n+1 SD sets and a sign of the FMA calculation; and a carry save adder (CSA) tree coupled to the partial product generation unit and configured to add the plurality of partial product vectors and an addend for the FMA calculation to generate a result sum vector and a result carry vector in a m+n digit BCD format, wherein m and n are integers, and wherein the FMA calculation comprises a calculation of a×b±c, where a represents the multiplicand, b represents the multiplier, c represents the addend, × represents a multiplication operator, and ± represents one of an addition operator and a subtraction operator.