Patent ID: 7305515

Claim:
A compiler contained in a computer for building at least one compilable DRAM unit including at least one compilable sub-array, the compiler comprising: an algorithm for receiving input data; and an algorithm for determining a number of DRAM memory units for at least one DRAM unit, an I/O configuration for the number of DRAM memory units of the at least one DRAM unit, and for compiling the at least one DRAM unit having at least one corresponding support unit to provide the at least one compilable DRAM unit, wherein the at least one compilable DRAM unit conforms to the received input data, wherein the at least one corresponding support unit includes a redundancy circuit block and a DC generator and refresh block, and wherein the compiler compiles one or more sample wordlines and one or more real wordlines, determines timing of the compilable DRAM unit using at least one of the one or more compiled sample wordlines, and adjusts timing of the DRAM unit based on a propagation delay through the compiled sample wordline element.