Patent ID: 7539915

Claim:
An integrated circuit comprising: a plurality of logic circuits comprising: a first logic circuit; and a second logic circuit connected to the first logic circuit, wherein at least one of logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the first logic circuit is greater than that of the second logic circuit; and a scan chain configured to test the plurality of logic circuits, the scan chain comprising: a first scan chain portion in communication with the first logic circuit for testing thereof based on a test pattern provided thereto; a second scan chain portion in communication with the second logic circuit for selectively testing thereof based on the test pattern provided thereto from the first scan chain portion; and a switching unit configured to select the test pattern output from one of the first scan chain portion and the second scan chain portion, wherein the second scan chain portion is configured not to test the second logic circuit when the switching unit selects the test pattern output from the first chain portion.