Patent ID: 7436712

Claim:
A nonvolatile memory device comprising: a decoder selectively selecting at least one word line out of a plurality of word lines, based on an address input from an outside; a plurality of drivers provided to correspond to said plurality of word lines, respectively, and each driving the corresponding word line, wherein each of said drivers includes first and second transistors electrically coupling said corresponding word line to a first power supply voltage and a second power supply voltage lower than said first power supply voltage in a complementary manner, respectively, in response to a signal from said decoder, said decoder outputs a first logic level signal to the driver corresponding to the selected word line to turn on said first transistor in a normal operation, said first transistor is connected to a third power supply voltage lower than said first power supply voltage and higher than said second power supply voltage, instead of said first power supply voltage, in a verify operation, said decoder outputs said first logic level signal to the driver corresponding to the selected word line to turn on said first transistor in said verify operation, and a voltage level of said first logic level signal is set such that the voltage level of said first logic level signal differs between in said normal operation and in said verify operation and that a drive capability of said first transistor is more increased in said verify operation than in said normal operation.