Patent ID: 8318287

Claim:
An integrated circuit chip package, comprising: a die pad defining opposed first and second die pad surfaces, and a die pad side surface extending to at least the first die pad surface; at least one connector integrally connected to the die pad; a plurality of leads, wherein all of the leads in the integrated circuit chip package are electrically isolated from the die pad and the connector, each of the leads defining opposed first and second lead surfaces, first and second lead side surfaces which each extend to at least the first lead surface, a first end portion defining a first end surface which extends to at least the first lead surface, and a second end portion defining a second end surface which extends between the first and second lead surfaces; at least one reentrant portion extending fully around the die pad side surface and through the connector; at least one reentrant portion extending within at least portions of the first end surface and the first and second lead side surfaces of each of the leads, the reentrant portions of the die pad and the leads being used for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads; and an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads; the encapsulant material being applied to at least portions of the integrated circuit die, the connector, the first die pad surface and the die pad side surface of the die pad, and the, first lead surface, the first end surface, and the first and second lead side surfaces of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.