Patent ID: 7560818

Claim:
A stacked structure of chips, comprising: a first chip; a second chip attached to the first chip, wherein the back surface of the second chip faces an active surface of the first chip, and the second chip comprises a first contact disposed on an active surface of the second chip; an insulation layer disposed on the active surface of the first chip, wherein the second chip is encapsulated in the insulation layer; a first conductive element formed in the insulation layer for electrically connecting one end of the first conductive element to the first contact and the other end of the first conductive element exposed outside the insulation layer; and a second conductive element, wherein the first chip comprises a second contact disposed on the active surface of the first chip and outside the coverage of the second chip, the second chip comprises a third contact and a fourth contact, and the second contact and the third contact are electrically connected to the fourth contact, the second conductive element is formed in the insulation layer for electrically connecting one end of the second conductive element to the third contact and the other end of the second conductive element exposed outside the insulation layer.