Patent ID: 8207017

Claim:
A method of fabricating a stacked dual MOSFET die package comprising the steps of: forming a first conductive tab; stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab; stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, wherein the second conductive tab comprises a thin portion and a thick portion, wherein the thick portion has a top surface coplanar to a top surface of the thin portion; and stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab, wherein the first conductive tab and the second conductive tab are thermally conductive.