Patent ID: 7189607

Claim:
A method of making a CMOS' device having standard and low voltage threshold gates for both PMOS and NMOS transistors comprising: forming isolation regions in a substrate; forming at least two N-type wells in said substrate; forming at least two P-type wells in said substrate; forming a sacrificial oxide layer over said substrate; providing a first mask over said substrate overlying at least one of said N-type wells defining a standard voltage threshold PMOS region; performing an NMOS voltage threshold adjustment ion implantation; removing said first mask from said substrate; providing a second mask over said substrate overlying at least one of said P-type wells defining a standard voltage threshold NMOS region; performing a PMOS voltage threshold adjustment ion implantation; forming an NMOS transistor over each of said P-type wells; and forming a PMOS transistor over each of said N-type wells, wherein one or more of said P-type wells are formed by performing retrograde P-type ion implantation or one or more of said N-type wells are formed by retrograde N-type ion implantation.