Patent ID: 7145365

Claim:
A logic processing apparatus including as a component a semiconductor device that has a chip sealed in a package, on which a logic circuit is mounted where data held in the front stage flip-flop is processed at a logic gate circuit network and then the processed data is held in the rear stage flip-flop, the logic circuit comprising: flip-flops that hold data and processed data synchronously with rising or falling of a clock signal at the front stage and rear stage, respectively, in a state in which the power is constantly supplied; a logic gate circuit network, which processes data held in the front stage flip-flop and outputs the processed data to the rear stage flip-flop, in a state in which the power is supplied only during a predetermined period of time including rising or falling of said clock signal; wherein, when said logic gate circuit network is divided into n (n: an integer of two or more) blocks along the processing direction, while (n−1) kinds of delayed clock signal each having a different phase from said clock signal are generated, intermediate stage flip-flops are disposed between n blocks of logic gate circuit networks, respectively; said clock signal is supplied as a clock signal to the front stage flip-flop and rear stage flip-flop; power is supplied to the final stage logic gate circuit network block by the clock signal; and each of said (n−1) kinds of delayed clock signal is supplied as a clock signal to a corresponding intermediate stage flip-flop and a power is sequentially supplied to the corresponding block of logic gate circuit network except the final block by the delayed clock signal.