Patent ID: 6940438

Claim:
A second order modulator circuit, comprising: an input node Vin; a signal node Vx; an output node Yout a first signal processing circuit block with a transfer function (H 3 ) and an input and output; a second signal processing circuit block with a transfer function (H 2 *H 3 ) and an input and output; the signal node Vx being coupled to the input of the first signal processing circuit block and the input of the second signal processing circuit block; a first, second, third and fourth summing nodes; a first buffer “a” with an input and output, the input of the first buffer “a” being adapted to receive input signal Vin, the output of the first buffer “a” being coupled to the first summing node; the output of the first signal processing circuit block being coupled to the third summing node; the output of the second signal processing circuit block being coupled to the fourth summing node; an n-bit quantizer with an input and output; the quantizer output being coupled to the fourth summing node; a first integrator circuit with a transfer function (H 1 ) and an input and output; a second buffer “b” with an input and output, the input of the second buffer being coupled to the output of the first integrator, the output of the second buffer “b” being coupled to the second summing node; the second summing node being coupled to the third summing node; a second integrator circuit with a transfer function (H 2 ) and an input and output; the input of the second integrator being coupled to the third summing node; the output of the second integrator being coupled to the input of the quantizer; a first m-bit DAC with an input and output; a second m-bit DAC with an input and output; a third buffer “c” with an input and output, the input of the third buffer being coupled to the output of the first DAC, the output of the third buffer “c” being coupled to the first summing node; a fourth buffer “d” with an input and output, the input of the fourth buffer “d” being coupled to the output of the second DAC, the output of the fourth buffer “d” being coupled to the second summing node; the output of the first signal processing circuit block being coupled to the third summing node; the fourth summing node coupled to the output node Yout; the circuit output Yout being coupled to the input of the first DAC and the input to the second DAC completing a feedback loop; the first DAC and third buffer “c” forming a feedback loop to the first integrator from Yout; the second DAC and fourth buffer “d” forming a feedback loop to the second integrator from Yout; and the quantizer swing reduction circuit operable to keep the input/output swing of the quantizer within the limit of finite quantization levels.