Patent ID: 8614488

Claim:
A chip package, comprising: a first semiconductor substrate; a drain region and a source region located in the first semiconductor substrate; a gate located on the first semiconductor substrate or at least partially buried in the first semiconductor substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the first semiconductor substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second semiconductor substrate laterally disposed beside the first semiconductor substrate; a second drain region and a second source region located in the second semiconductor substrate, wherein the second drain region is electrically connected to the source region in the first semiconductor substrate; a second gate located on the second semiconductor substrate or at least partially buried in the second semiconductor substrate; a second source conducting structure and a second gate conducting structure disposed on the second semiconductor substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain conducting structure, the source conducting structure, the gate conducting structure, the second source conducting structure, and the second gate conducting structure are substantially coplanar; and a redistribution layer located on the second semiconductor substrate and extending onto the first semiconductor substrate to electrically connect the second drain region to the source region, wherein a portion of the redistribution layer is sandwiched between the source conducting structure and the source region.