Patent ID: 8107586

Claim:
A shift register comprising a plurality of stages, wherein stages of the plurality of stages are connected to each other and a current stage thereof generates an output signal in response to any one of a plurality of clock signals, wherein each of the stages comprises: a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, and which generates the output signal in response to any one of the clock signals; and a discharge unit which discharges the predetermined voltage in response to an output signal of a next stage, wherein the driving unit comprises: an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous stage; and an output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals, wherein each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals, wherein the output signal of the output unit is transmitted to a gate line and the next stage, wherein each of high levels of the clock signals do not overlap each other, and wherein the clock signals for some stages disposed on left side of the panel or the other stages disposed on right side of the panel have high value with a frequency of every 4 horizontal periods.