Patent ID: 8237481

Claim:
A programmable local clock buffer comprising in combination: an inverter coupled between a clock input terminal and a delayed clock output terminal and controlled by a control element coupled between the inverter and ground; a transistor switch coupled to said inverter responsive to a delay input signal that modulates the inverter between a state in which a clock signal coupled to the clock input terminal is transmitted to the delayed clock output terminal and a state in which the clock signal coupled to the clock signal input terminal is not transmitted to the delayed clock output terminal; a multi stage delay circuit coupled to said clock input terminal to generate said delay input signal in response to a plurality of delay select bits, the delay circuit including at least two stages, each stage being formed by at least two transistor stacks each including two serially coupled transistors and selected by the delay select bits, the at least two stages including a first stage having a first transistor, a second transistor, a third transistor and a fourth transistor, the second and third transistors being serially coupled and coupled between the first and fourth transistors, the first transistor being coupled to power and the fourth transistor being coupled to ground, the second stage having a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the sixth and seventh transistor being serially coupled between the fifth an eighth transistors and the sixth transistor being coupled directly to the fifth transistor, the fifth transistor being coupled to power and the eight transistor being coupled to ground, the first and seventh transistors having gates coupled directly to each other, the first and seventh transistors having gates coupled to the gates of the second and third transistors, the fifth and sixth transistors are directly coupled to the control element of the inverter, wherein the number of transistor stacks selected by the delay select bits determines an amount of delay imparted to the delay input signal.