Patent ID: 7433221

Claim:
A memory system comprising: a ferroelectric memory having a cell driving block and a data amplifying block, the cell driving block applying voltage to a data retention element and the data amplifying block amplifying readout data from the data retention element; a data latch circuit retaining output timings and pulse widths of control signals respectively controlling the cell driving block and the data amplifying block; a timing generating circuit respectively outputting the control signals to the cell driving block and to the data amplifying block according to the output timings and the pulse widths of the control signals retained in the data latch circuit; and a power supply potential-detecting circuit detecting a power supply potential supplied to the ferroelectric memory and outputting a selecting signal corresponding to the detected power supply potential to the data latch circuit; wherein: the data latch circuit retains, as the output timings and the pulse widths of the control signals, a plurality of different output timings and a plurality of different pulse widths that correspond to power supply potentials, and selects an output timing or a pulse width corresponding to the selecting signal from the power supply potential-detecting circuit; and at least one of operation timings or operating periods of the cell driving block and the data amplifying block of the ferroelectric memory is varied according to the power supply potential supplied to the ferroelectric memory.