Patent ID: 7443715

Claim:
A six transistor SRAM cell, comprising: a pair of cross coupled inverters, wherein each inverter includes an NMOS transistor and a PMOS transistor, and wherein at least one of the PMOS transistors includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; and a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; a pair of bitlines coupled to the pair of cross inverters at a pair of voltage nodes; wherein the floating gate is adapted to be programmed with a respective charge state such that the SRAM cell has a definitive asymmetry; and wherein the low tunnel barrier intergate insulator includes a metal layer in contact with one of the floating gate and the control gate.