Patent ID: 8587998

Claim:
A memory device comprising: a block of memory cells comprising a plurality of levels, each level comprising strips of memory cells extending in a first direction between first and second ends of the block of memory cells; a first bit line structure at each level at the first end of the block of memory cells, each first bit line structure operably coupled to a first string of memory cells extending from said first end; a second bit line structure at each level at the second end of the block of memory cells, each second bit line structure operably coupled to a second string of memory cells extending from said second end; a plurality of bit line pairs extending in the first direction comprising at least first and second bit line pairs, each bit line pair comprising an odd bit line and an even bit line; odd bit line connectors connecting the odd bit lines to the second bit line structures; even bit line connectors connecting the even bit lines to the first bit line structures; and each bit line for a series of bit line pairs being separated by a bit line of an adjacent pair of bit lines.