Patent ID: 8558580

Claim:
A data channel circuit comprising: an analog to digital converter configured to, based on a first clock signal, convert an analog signal into a digital signal; a control circuit configured to (i) receive the digital signal from the analog to digital converter, and (ii) generate a second clock signal based on the digital signal; an interpolator circuit configured to receive the second clock signal, and generate a reference clock signal based on a selected one of (i) the second clock signal or (ii) the second clock signal delayed by a predetermined amount of phase delay, wherein the second clock signal has glitches, and wherein each of the glitches is a pulse with a duration less than a predetermined duration; and a deglitch circuit comprising a first plurality of transistors configured to generate the first clock signal based on the reference clock signal, wherein the first clock signal does not include the glitches, and a first capacitance configured to charge based on current received from an output of the first plurality of transistors, wherein the first plurality of transistors are configured to generate the first clock signal based on a charged state of the first capacitance.