Patent ID: 8464093

Claim:
A memory array comprising: N uniformly-sized memory elements, each of the N uniformly-sized memory elements having a memory of M bits for storing non-redundant data bits and one or more corresponding error check (EC) bits derived from the non-redundant data bits, wherein M is an integer and N is an integer greater than one, wherein M is greater than N, and wherein M is an integer multiple of N; a first logic unit for computing parity bits by performing a first bitwise exclusive OR (XOR) operation on each of the non-redundant data bits stored in each of the N uniformly-sized memory elements; an N+1th memory element having the memory of M bits for storing the parity bits computed by the first logic unit and for storing one or more EC bits corresponding to the parity bits computed by the first logic unit, the N+1th memory element being a redundant memory element; a logic unit for computing the one or more EC bits corresponding to the parity bits computed by the first logic unit and for storing the one or more EC bits corresponding to the parity bits in a portion of the M bits of the N+1th memory element, wherein the logic unit is further operable to detect faulty bits in the parity bits stored in the portion of the M bits of the N+1th memory element using the one or more EC bits corresponding to the parity bits, wherein the logic unit is further operable to correct faulty bits in the parity bits; a second logic unit for detecting faulty data bits stored in each of the N memory elements, the second logic unit is configured to operate on the corresponding EC bits stored in each of the N uniformly-sized memory elements to detect whether any one of the N uniformly-sized memory elements is storing faulty data in its data bits; and a third logic unit for recovering the faulty data detected by the second logic unit, wherein the third logic unit is configured to perform a second bitwise XOR operation on all the data bits from the remaining N−1 memory elements and with the parity bits stored in the N+1th memory element, the N−1 memory elements having fault free data bits in there corresponding M bits.