Patent ID: 8904071

Claim:
A method of retrieving data retrievals from a memory apparatus on a data processing system, said method comprising: issuing a read command from a processor of said data processing system to a memory controller to read data stored at a designated address on a memory apparatus; receiving, in an interface chip of said memory apparatus, a read command from said memory controller, said interface chip being associated with at least one core chip; communicating a data request from said interface chip to a selected one of said at least one core chip associated with said interface chip, to read information at a designated address on said selected core chip; generating a timing control signal on said selected core chip, based on receiving said data request; employing said generated timing control signal to enable data stored at said designated address on said selected core chip to be communicated to said interface chip; communicating said generated timing control signal to said interface chip from said selected core chip, to serve as a timing signal to receive said stored data at said interface chip from said selected core chip; receiving said data stored at said designated address in said interface chip, in a parallel format; converting said received data stored at said designated address into a serial format; and transmitting said data stored at said designated address to said process in said serial format.