Patent ID: 8373229

Claim:
An integrated circuit device comprising: a semiconductor substrate; a fin structure disposed on top of the semiconductor substrate, the fin structure having a collector portion, an emitter portion, and a base portion disposed between the collector and emitter portions, wherein: the collector portion is a first doped region including a first type dopant, the collector portion being coupled with a first terminal for electrically biasing the collector portion, the emitter portion is a second doped region including the first type dopant, the emitter portion being coupled with a second terminal for electrically biasing the emitter portion, and the base portion is a third doped region including a second type dopant opposite the first type, the base portion being directly connected to a third terminal for electrically biasing the base portion; and a gate structure disposed on top of the base portion of the fin structure, the gate structure being coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion, wherein the gate structure includes a portion disposed below a bottom surface of the fin structure.