Patent ID: 7046048

Claim:
An electronic device comprising: a clock loss sense circuit coupled to receive signals indicative of at least a first clock signal and a second clock signal, the clock loss sense circuit also being coupled to provide a first clock loss signal indicative of whether or not the first clock signal is bad and a second clock loss signal indicative of whether or not the second clock signal is bad; a clock switchover circuit coupled to receive the first clock loss signal, the second clock loss signal, a lock signal indicative of whether or not a primary clock signal is phase-locked, and a switch command signal indicative of a switch command, the clock switchover circuit also being coupled to provide a first clock switch signal responsive to a one of the first and second clock loss signals corresponding to a one of the first and second clock signals, the first clock switch signal also being responsive to the switch command signal; and a first multiplexor coupled to receive the first clock switch signal and the first and second clock signals, the first multiplexor also being coupled to provide a selected one of the first and second clock signals to clock circuitry driving at least a portion of the electronic device, the first multiplexor selecting the one of the first and second clock signals in response to the first clock switch signal.