Patent ID: 7561455

Claim:
A memory system comprising: a memory device which includes a memory unit to store data; a controller to access said memory unit; and an optical transmission line which is provided between said memory unit and said controller, wherein said controller comprises: a first serial converting unit which converts a parallel command signal, address signal, and write signal into a first serial signal in order to read/write data from/to said memory unit; a first optical converting unit to output to said memory device said first serial signal as a first optical signal with a single wavelength via said optical transmission line; and a first parallel converting unit to convert a second optical signal supplied from said memory device into a parallel read data signal, and said memory device comprises: a second parallel converting unit to convert said first optical signal into the original parallel command signal, address signal, and write data signal and output the converted parallel signals to said memory unit; a second serial converting unit to convert a parallel read data signal from said memory unit into a second serial signal; and a second optical converting unit to output to said controller said second serial signal as said second optical signal with a single wavelength via said optical transmission line, and wherein: before starting reading/writing data from/to said memory unit, said controller outputs, as said first optical signal, to said memory device, a first synchronous clock to synchronize an operation of said memory device with an operation of said controller; said memory device generates a second synchronous clock synchronized with said first synchronous clock and outputs the generated second synchronous clock as said second optical signal; and said controller starts reading/writing data from/to said memory unit in response to reception of said second synchronous clock.