Patent ID: 8271926

Claim:
A semiconductor integrated circuit, comprising: a first wiring formed on a first wiring layer and prolonged in a first direction; a second wiring formed on a second wiring layer and prolonged in a second direction; a third wiring formed on the first wiring layer and prolonged in the first direction; a fourth wiring formed on the second wiring layer and prolonged in the second direction; a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction; and a single-cut via formed to connect the third wiring to the fourth wiring, wherein a first overhang formed with respect to the first via is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang formed with respect to the second via in the first direction, wherein the second overhang is smaller than a third overhang formed with respect to the single-cut via in the first direction, and wherein a distance between the first via and the second via is longer than a width of the second wiring.