Patent ID: 7095099

Claim:
A semiconductor device, comprising: first and second semiconductor die, each having a drain electrode on one surface and a gate electrode and a source electrode on another opposing surface thereof; a lead frame including first and second separate die pad areas, the first semiconductor die being disposed on and electrically coupled to the first die pad area and the second semiconductor die being disposed on and electrically coupled to the second die pad area; at least first and second terminal leads, the at least first terminal lead being in permanent electrical connection with the first die pad and the at least second terminal lead being in permanent electrical connection with the second die pad; a third plurality of terminal leads being separated from one another, from the at least first and second terminal leads, and from the first and second die pads; first bonding wire connecting the gate electrode of the first semiconductor die to at least one of the plurality of terminal leads; second bonding wire connecting the gate electrode of the second semiconductor die to at least another one of the plurality of terminal leads; and a housing for encapsulating the at least first and second semiconductor die and the bonding wire, and wherein all terminal leads extend beyond a periphery of the housing along a single common edge.