Patent ID: 8532240

Claim:
An apparatus comprising: a receiver comprising: an eye monitor configured to generate a data eye from a data stream subject to equalization, the eye monitor including at least one error sampler, at least one transition sampler, and at least one data sampler; a clock and data recovery (CDR) circuit configured to generate a transition clock for each transition sampler based on data transitions in the data eye, wherein the CDR shifts, in phase, the transition clock with a fixed phase offset to generate an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler, and an adaptation module configured to adaptively set parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler, wherein, at a subsequent time, the CDR decouples the error clock and the data clock to generate a relative optimum phase for the decoupled data clock for each data sampler.