Patent ID: 7587580

Claim:
A processor, comprising: an instruction execution pipeline; an instruction cache coupled to a memory subsystem; a branch prediction mechanism operative to predict the evaluation of a branch condition associated with a conditional branch instruction and output a weighted branch prediction value; and an instruction prefetching mechanism operative to selectively prefetch instructions from the instruction cache and, in the case of an instruction cache miss, to prefetch the instructions from the memory subsystem, in response to the weighted branch prediction value and whether the prefetch hits in the instruction cache, said instruction prefetching mechanism is halted thereby stopping the prefetch of the instructions from the memory subsystem in the case of a weakly weighted branch prediction and a cache miss, wherein the instruction prefetching mechanism is halted until the branch condition is evaluated in the instruction execution pipeline, and the instruction prefetching mechanism is performed in the case of either a strongly weighted branch prediction or a weakly weighted branch prediction and an instruction cache hit.