Patent ID: 8166226

Claim:
A chip set electrically connected to a central processing unit (CPU) and a peripheral device, comprising: a south bridge electrically connected to the peripheral device, the south bridge having a register for storing a plurality of pre-fetched data to provide the pre-fetched data to the peripheral device while being requested, wherein an adjoining data of a peripheral data is fetched as the pre-fetched data, and the peripheral data is requested by the peripheral device, and the addresses of the pre-fetched data and the addresses of the peripheral data are sequential; and a north bridge electrically connected to the CPU and the south bridge, the north bridge comprising: an address queue module for storing addresses of the pre-fetched data; and a snooping module for snooping a cache in the CPU according to the addresses of the pre-fetched data in the address queue to determine whether the pre-fetched data is updated and to ensure data coherence between the register and the cache.