Patent ID: 8023352

Claim:
A semiconductor storage device comprising: a memory cell array formed using a vertical transistor which has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a pillar-shaped semiconductor layer and a gate electrode surrounds the pillar-shaped semiconductor layer; first bit lines formed by a first layer, said first bit lines being wired in a row direction so that each first bit line is connected to a sense amplifier; second bit lines formed by a second layer, said second bit lines being wired in the row direction so that each second bit line is connected to a sense amplifier; and a plurality of vertical transistors formed on each first bit line, said vertical transistors including a first transistor for selecting a memory cell and a second transistor for connecting the first bit line and a corresponding one of the second bit lines, wherein a gate electrode of the first transistor is connected to a corresponding one of first word lines wired in a column direction, and a gate electrode of the second transistor is connected to a corresponding one of second word lines wired in the column direction, wherein when a first word line is selected, a corresponding second word line is also selected so that a second transistor connected to the corresponding second word line is conducted and a first bit line and a second bit line are therefore connected through the second transistor connected between the first and second bit lines.