Patent ID: 7492199

Claim:
A method for architecting a delay locked loop clock signal circuit comprising: providing at least one clock signal to a clock signal splitter; alternately outputting said at least one clock signal from said clock signal splitter on at least two matched delay lines; and alternately propagating every other clock pulse of said at least one clock signal down each of said at least two matched delay lines by said signal splitter, specifying a delay period for each of said at least two matched delay lines with a control signal; updating said at least two matched delay lines with said control signal when a fixed update window is always present on said at least two matched delay lines; distributing said control signal to synchronously update said at least two matched delay lines; and combining said pulses from the output of said two matched delay lines, wherein a delayed a delayed version of said at least one clock signal is recovered, wherein said synchronous update occurs with said fixed update window, said fixed update window is equal to at least a mimic delay of a circuit reduced by a duty cycle tolerance of said at least one clock signal.