Patent ID: 8035436

Claim:
A phase-interpolator circuit, comprising: a first input node configured to receive a first reference signal, wherein the first reference signal has a fundamental frequency and a first phase; a second input node configured to receive a second reference signal, wherein the second reference signal has the same fundamental frequency and a second phase; a weighting circuit with an output and inputs, electrically coupled to the first input node and the second input node, wherein the weighting circuit is configured to provide a contribution of the first reference signal to the output based on a first impedance value in the weighting circuit, and is configured to provide a contribution of the second reference signal to the output based on a second impedance value in the weighting circuit, wherein the weighting circuit comprises a capacitor that is selectively coupled to the first input node and to the second input node so that, at a given time, only one of the first reference signal and the second reference signal is coupled to the capacitor; and a biasing circuit, electrically coupled to the weighting circuit, configured to provide a DC bias to the weighting circuit and configured to amplify the output of the weighting circuit to provide an output of the phase-interpolator circuit.