Patent ID: 7553743

Claim:
A method of wafer bonding for a system in package, comprising: forming a first via hole on a first semiconductor substrate; forming a first photoresist pattern around the first via hole; forming a first plating layer on the first via hole, wherein an upper surface of the first plating layer is above an upper limit of the first via hole; forming a second via hole on a second semiconductor substrate; forming a second photoresist pattern around the second via hole; forming a second plating layer on the second via hole, wherein an upper surface of the second plating layer is above an upper limit of the second via hole; bonding the first plating layer to the second plating layer; and exposing the second via hole on a rear surface of the second semiconductor substrate, wherein the upper surface of the first plating layer is lower than an upper surface of the first photoresist pattern; and wherein the upper surface of the second plating layer is lower than an upper surface of the second photoresist pattern.