Patent ID: 7119999

Claim:
An apparatus comprising a reverse current blocking circuit devoid of PMOS, bipolar PNP, and external circuit protection devices, wherein the reverse current blocking circuit is operational to protect the apparatus against reverse current flow; wherein the reverse blocking circuit comprises: an N-channel MOS isolation transistor; and an N-channel MOS blocking transistor, wherein a reverse supply voltage connection operates to turn-on the N-channel MOS isolation transistor, and further wherein the turn-on of the N-channel MOS isolation transistor operates to turn-off the N-channel MOS blocking transistor to prevent the flow of reverse current there through in response to the reverse supply voltage connection; a regulated voltage output node; a voltage regulator output N-channel MOS transistor having its drain coupled to the drain of the N-channel MOS blocking transistor, and further having its source connected to the output node; a bias generator operational to generate a bias current for the voltage regulator output N-channel MOS transistor; and a regulator operational to control the gate of the voltage regulator output N-channel MOS transistor to hold the regulated voltage output node at a desired regulation point.