Patent ID: 7269681

Claim:
A method in an integrated PCI bridge device coupled to a PCI bus having PCI data lines, the method comprising: receiving PCI data from the PCI bus supplied at one of a double data rate mode or a quad data rate mode; and latching the PCI data based on: (1) supplying prescribed groups of the PCI data lines to respective PCI bus latching modules in the integrated PCI bridge device, each PCI bus latching module having a plurality of data line latch modules, each data line latch module configured for latching from a corresponding PCI data line, according to the one data rate mode, first and second PCI data values based on respective locally-generated first and second PCI strobe signals, (2) generating, in each PCI bus latching module, the corresponding locally-generated first and second PCI strobe signals based on supplying respective first and second PCI bus strobe signals received from the PCI bus to respective buffers, and supplying the same locally-generated first and second PCI strobe signals from the respective buffers to each of the data line latch modules in the corresponding PCI bus latching module, and (3) holding, in each data line latch module, the first and second PCI data values for at least a clock cycle of the respective locally-generated first and second PCI strobe signals.