Patent ID: 7820510

Claim:
A method for fabricating a flash memory, comprising: providing a substrate sequentially covered by a first dielectric layer, a first conductive layer, a first mask layer and a second mask layer; forming a first trench in the second mask layer, the first mask layer, the first conductive layer, the first dielectric layer and the substrate, wherein the first trench partly formed in the second mask layer has a first width, and the first trench partly formed in the first mask layer, the first conductive layer, the first dielectric layer and the substrate has a second width, wherein the first width is wider than the second width; filling up the first trench by an insulating material, the top surface of the insulating material being on the same plane with the top surface of the second mask layer; removing the second mask layer and a part of the first mask layer, and exposing the first conductive layer; forming a second conductive layer covering the first conductive layer and the insulating layer; forming a second trench in the second conductive layer, and exposing the top surface of the insulating material; forming a second dielectric layer conformally covering the surface of the second trench and the surface of the second conductive layer; and forming a third conductive layer covering the second dielectric layer and filling up the second trench.