Patent ID: 7777753

Claim:
An electronic system comprising: a bus; a main memory coupled to the bus having stored therein data corresponding to video images; a video circuit coupled to the bus, the video circuit configured to receive data from the main memory corresponding to a current video image to be decoded and to output decoded video data corresponding to the current video image to be displayed on a display device, the current video image to be displayed adapted to be stored in the main memory; a processor coupled to the main memory, the processor for storing non-image data in the main memory and retrieving non-image data from the main memory; and an arbiter circuit coupled to the processor and to the video circuit, the arbiter circuit configured to receive requests for access to the main memory from the video circuit and the processor and to control access to the main memory by: providing access to the main memory for a request for access to the main memory when the arbiter circuit is in an idle state; queuing a request for access to the main memory when the arbiter circuit is in a busy state; and queuing a request for access to the main memory in an order based on a priority of the request and a priority of each of one or more other requests for access to the main memory that are currently queued when the arbiter circuit is in a queue state.