Patent ID: 8129255

Claim:
A process wherein at least two processed semiconductor wafers having electrically active structures thereon that are located in a central area of a stack of wafers, and wherein in an operation of a mechanical connecting, electrically insulating connections and electrically conductive connections are produced between said at least two processed semiconductor wafers each one thereof having a wafer surface to be connected, said process comprising: providing an electrically non-conducting glass paste and an electrically conducting glass paste; applying patterned layers of the electrically non-conducting glass paste and the electrically conducting glass paste on said wafer surfaces; thereafter conditioning and pre-melting the electrically non-conducting glass paste and the electrically conducting glass paste; thereafter providing geometrical alignment of the at least two processed semiconductor wafers to be connected; and thereafter bonding the at least two processed semiconductor wafers at a first processing temperature of the electrically non-conducting glass paste and at a second processing temperature of the electrically conducting glass paste using a mechanical pressure.