Patent ID: 7514912

Claim:
A power factor correction apparatus, the apparatus comprising: a multiplier component being configured to receive a first input signal and a second input signal and generate a first output signal based on at least information associated with the first input signal and the second input signal, the first input signal being associated with a rectified AC signal; a comparator component being configured to receive the first output signal and a third input signal and generate a second output signal based on at least information associated with the first output signal and the third input signal; a timing component being configured to receive a fourth input signal at a first time from a flip-flop component and generate a third output signal at a second time based on at least information associated with the fourth input signal; an AND gate being configured to receive the second output signal and the third output signal and generate a fourth output signal based on at least information associated with the second output signal and the third output signal; a zero current detector being configured to receive a fifth input signal and generate a fifth output signal based on at least information associated with the fifth input signal; the flip-flop component being configured to receive the fourth output signal at a first terminal and the fifth output signal at a second terminal and output a sixth output signal at a third terminal; a driver component being configured to receive the sixth output signal and output a seventh output signal, the seventh output signal being at least capable of causing a switch to be turned off; wherein: a time difference between the first time and the second time is predetermined based on at least a characteristic of the apparatus; the second terminal is a “set” terminal for the flip-flop component; the fifth output signal is capable of setting the flip-flop component; the first terminal is different from the second terminal; the fourth output signal is capable of resetting the flip-flop component.