Patent ID: 8043920

Claim:
A method, comprising: (a) forming two or more silicon fins on a top surface of an insulating layer on a silicon substrate, each fin of said two or more fins having a central region between and abutting first and second end regions and opposite sides; (b) forming a gate dielectric layer on said opposite sides of each fin of said two or more fins; (c) forming an electrically conductive gate over said gate dielectric layer over said central region of each fin of said of two or more fins; (d) removing said gate dielectric layer from said first and second end regions of each fin of said two or more fin and removing said end regions of each of said two or more fins to form exposed opposite first and second ends of said central regions of each fin of said two or more fins; after (d), (e) removing said insulating layer to expose first and second regions of said substrate on opposite sides of said gate; and after (e), (f) simultaneously growing epitaxial silicon from said first and second regions of said substrate and from said first and second ends of said central regions of each fin of said two or more fins to form respective first and second merged source/drains.