Patent ID: 7570530

Claim:
A nonvolatile memory device comprising: a memory cell array having a plurality of nonvolatile memory cells; a selection circuit coupled to the memory cell array and configured to select at least one of the plurality of nonvolatile memory cells; and a data read circuit coupled to the memory cell array, the data read circuit configured to read data from the selected nonvolatile memory cell, the data read circuit including: a clamping unit coupled between a sensing node and a bit line associated with the selected nonvolatile memory cell, the clamping unit configured to clamp the bit line to a predetermined bias level in response to a clamping control signal; a precharge unit coupled to the sensing node and configured to precharge the sensing node in response to a precharge signal; a read bias supply unit coupled to the sensing node and configured to supply a read bias to the sensing node in response to a read bias control signal; a sense amplifier coupled to the sensing node and a reference level, the sense amplifier configured to compare a level of the sensing node with a reference level and output a comparison result; and a first decoupling unit coupled to the clamping control signal or the read bias control signal, and configured to reduce noise in the clamping control signal or the read bias control signal.