Patent ID: 6954161

Claim:
A cascade delta-sigma modulator comprising: a first-stage delta-sigma modulation quantization loop comprising a first integration circuit to which a first analog input signal, the maximum voltage of which is specified, and a first feedback reference voltage are input, a first local quantizer for quantizing the output of said first integration circuit into a digital signal, and a first DA converter for generating said first feedback reference voltage from the digital output of said first local quantizer, one or more delta-sigma modulation quantization loops, that is, second-stage and subsequent delta-sigma modulation quantization loops, each comprising a second integration circuit to which a second analog input signal formed of the difference signal between the input of the local quantizer and the output of the DA converter of the previous-stage delta-sigma modulation quantization loop and a second feedback reference voltage are input, a second local quantizer for quantizing the output of said second integration circuit into a digital signal, and a second DA converter for generating said second feedback reference voltage from the digital output of said second local quantizer, said second-stage and subsequent delta-sigma modulation quantization loops being cascade-connected to said first-stage delta-sigma modulation quantization loop, and a noise reduction circuit, in said first-stage, second-stage and subsequent delta-sigma modulation quantization loops, for canceling the quantization noise of each of said delta-sigma modulation quantization loops by adding the output obtained by delaying the output of said local quantizer of each of said delta-sigma modulation quantization loops using a delay device to the output obtained by differentiating the output of said local quantizer of the next-stage delta-sigma modulation quantization loop using a differentiator and by using the value obtained by the addition as the output signal thereof, said cascade delta-sigma modulator further comprising gain limiting means for limiting the gain of each of said delta-sigma modulation quantization loops by setting the feedback reference voltage of each of said delta-sigma modulation quantization loops at the specified maximum voltage or more of said analog input signal and by setting the feedback reference voltage of each of said delta-sigma modulation quantization loops so as to be independent of the feedback reference voltages of the other delta-sigma modulation quantization loops, and scale compensating means for compensating the gain limited in each of said delta-sigma modulation quantization loops by independently setting the gain in said noise reduction circuit for each of said delta-sigma modulation quantization loops.