Patent ID: 6943402

Claim:
A nonvolatile semiconductor memory device comprising: memory cells each of which includes a first MOS transistor having a charge accumulation layer and a control gate formed on the charge accumulation layer with an inter-gate insulating film interposed therebetween; and a boosting circuit which generates a voltage supplied to the memory cells and includes a capacitor element, the capacitor element including a first and a second semiconductor layer which are formed on a semiconductor substrate and separated from each other, a capacitor insulating film which is formed on the top and side of each of the first and second semiconductor layers and on the semiconductor substrate between the first and second semiconductor layers and which is made of the same material as that of the inter-gate insulating film, and a third semiconductor layer which is formed on the capacitor insulating film and which is connected electrically to the first semiconductor layer and isolated electrically from the second semiconductor layer.