Patent ID: 8860477

Claim:
A receiver circuit comprising: a data interpolator configured to interpolate an input data signal and generate an interpolation data signal; a data determination unit configured to determine a data determination result of the interpolation data signal; a clock recovery unit configured to detect phase information based on a data determination result of the data determination unit and output an interpolation code to the data interpolator based on the detected phase information, the interpolation code determining an interpolation rate of the data interpolator; a first interpolator for an eye pattern monitor configured to interpolate the input data signal and generate an interpolation data signal for the eye pattern monitor; a first determination unit for the eye pattern monitor configured to compare the interpolation data signal for the eye pattern monitor with a reference voltage; a match determination unit configured to determine whether the data determination result of the data determination unit matches a comparison result of the first determination unit for the eye pattern monitor; and an eye pattern regenerator configured to generate an eye pattern based on the phase information and a determination result of the match determination unit.