Patent ID: 8724272

Claim:
A circuit comprising: a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection, wherein the anode connection is coupled to a power rail, and the cathode connection is coupled to a ground rail; and a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, the first drain being coupled to the first control connection, the first source being coupled to the ground rail, and the first gate being coupled to a program circuit, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low, wherein the tunable holding voltage control unit further includes a second NMOS having a second gate, a second drain, and a second source, the second drain being coupled to the first control connection, the second source being coupled to the ground rail, and the second gate being coupled to the program circuit, and wherein during an ESD event, the first and second NMOS are turned off and the holding voltage of the SCR is low.