Patent ID: 7206800

Claim:
A method of clamping fixed-point multipliers, comprising: providing a first and second input operand; determining a desired number of output bits; where any of the first and second input operands are positive, counting a number of leading logical zeros in the positive operands; where any of the first and second input operands are negative, counting a number of leading logical ones in the negative operands; summing the number of leading logical zeros of the positive operands with the number of leading logical ones in the negative operands; determining a clamping decision based on the summing to yield a simple clamp predictor representative of the clamping decision; computing a product of the first operand and the second operand such that the product has the desired number of output bits plus one additional bit; and logically ORing the simple clamp predictor with a most significant bit of the product to produce a final clamping predictor bit wherein the product and determining steps occur substantially in parallel to avoid overflow.