Patent ID: 7404044

Claim:
A data processing system, comprising: a first integrated circuit, comprising: at least one memory module; a first bus having a first memory coherency protocol for managing data transfers therein; a first plurality of processors operably coupled to said first bus; a second bus having said first memory coherency protocol for managing data transfers therein; a second plurality of processors operably coupled to said second bus; a switch operably coupled to said memory module; a first controller for operably coupling said first bus to said switch, thereby establishing a first level of coherency between individual processors in said first plurality of processors using said first memory coherency protocol and a second level of coherency between individual processors in said first plurality of processors and individual processors in said second plurality of processors using a second memory coherency protocol; and a second controller for operably coupling said second bus to said switch, thereby establishing said first level of coherency between individual processors in said second plurality of processors using said first memory coherency protocol and said second level of coherency between individual processors in said second plurality of processors and individual processors in said first plurality of processors using said second memory coherency protocol.