Patent ID: 6970530

Claim:
A high-reliability shift register circuit which is composed of several stages, wherein the stages are connected in serial and send output signals to gate lines of a panel, comprising: a serial-in signal is fed into a first stage, and input signals for every additional stage are from an output signal of a first previous stage respectively, wherein the shift register circuit is controlled by first and second clock-pulse signals, which are out of phase; each odd stage of the stages comprises: a first transistor whose gate connects to the output signal of the first previous stage and whose drain connects to a high-level supply voltage; a second transistor whose gate connects to an output signal of the first subsequent stage or to an output signal of a second subsequent stage whose source connects to a low-level supply voltage, and whose drain and the source of the first transistor form a first node; a third transistor whose gate connects to the first node and whose drain connects to the first clock-pulse signal; a fourth transistor whose gate connects to the output signal of the first subsequent stage or to the output signal of the second subsequent stage, whose source connects to the low-level supply voltage, and whose drain and the source of the third transistor form the output terminal of each odd stage; a fifth transistor whose gate and drain connect to the high-level supply voltage; a sixth transistor whose gate connects to the output signal of the first subsequent stage or to the output signal of the second subsequent stage, whose drain connects to the high-level supply voltage, and whose source and a source of the fifth transistor form a second node; a seventh transistor whose gate connects to the first node, whose source connects to the low-level supply voltage, and whose drain connects to the source of the fifth transistor, where the fifth transistor and the seventh transistor form an inverter; an eighth transistor whose gate connects to the second node, whose source connects to the low-level supply voltage, and whose drain connects to the first node; a ninth transistor whose gate connects to the second node, whose source connects to the low-level supply voltage, and whose drain connects to the output terminal of each odd stage.