Patent ID: 8242012

Claim:
A method of forming an integrated circuit structure incorporating a back end of the line (BEOL) redistribution layer with top surface and sidewall passivation provided by metal, said method comprising: forming a seed layer on a substrate; forming a mask layer on said seed layer; forming a trench extending through said mask layer to said seed layer and having first sidewalls; forming spacers within said trench on said seed layer and positioned laterally adjacent to said first sidewalls such that a first portion of said seed layer remains exposed; forming a first metal layer for said redistribution layer on said first portion of said seed layer; after said forming of said first metal layer, removing said spacers so as to expose second sidewalls of said first metal layer and second portions of said seed layer adjacent to said second sidewalls; forming, for said top surface and sidewall passivation of said redistribution layer, a second metal layer on said second portions of said seed layer, said second sidewalls of said first metal layer and on a top surface of said first metal layer, said second metal layer comprising a different metal material than said first metal layer and said forming of said second metal layer comprising performing a selective electroplating process; removing said mask layer to expose third portions of said seed layer adjacent to said second portions; and performing an etch process to remove said third portions in order to complete said redistribution layer with said top surface and sidewall passivation; and forming a blanket polymide layer over said second metal layer and exposed portions of said substrate following removal of said third portions.