Patent ID: 6873147

Claim:
A method for assigning tester interface pins to tester fixture probes in a constrained pin-to-probe assignment problem describing a printed circuit board tester environment, said constrained pin-to-probe assignment problem defined by a set of constraints, said set of constraints including: a set of nodes each needing at least one resource, a plurality of tester resources wherein said plurality of resources may comprise a plurality of non-disjoint groupings of resources wherein each grouping realizes a test, a plurality of tester interface pins each connectable to one or more of said tester resources and may be physically grouped into one or more tester modules, said plurality of tester interface pins comprising a plurality of disjoint pin groupings wherein each pin grouping comprises a plurality of tester interface pins that are multiplexed together and that cannot be used simultaneously in any given test, a plurality of probes each connectable to at least one node and to only one of said tester interface pins to deliver a single tester resource to said node during any given test and the same or a different tester resource for any other given test, and wherein no two nodes can share a pin, and a plurality of tests which may include a subset of tests where each test in said subset of tests requires tester resources to be delivered and/or measured from said tester interface pins from a single given module of said one or more tester modules, said method comprising: modeling said constrained pin-to-probe assignment problem as a Matching Problem that satisfies said set of constraints; and solving said Matching Problem that satisfies said set of constraints to generate a solution to said constrained pin-to-probe assignment problem.