Patent ID: 7856464

Claim:
A digital decimation filter, comprising: circuitry configured to implement: an input to receive a digital data stream; a control input to receive a desired decimation rate; an integrator stage responsive to the input, the integrator stage including an adder and a delay element; a variable rate down sampling module responsive to an output of the integrator stage, wherein the variable rate down sampling module has an adjustable decimation rate based on an adjustable rate decimation signal derived from the control input, and wherein the adjustable decimation rate is dynamically adjusted by adding a first offset based on the desired decimation rate to the output of the integrator stage; an output adjustment module to add an adjustment factor to an output of the variable rate down sampling module, wherein the adjustment factor is based on a change in the adjustable rate decimation signal multiplied by an output of the adder, the output adjustment module to compensate for adjustment to the adjustable decimation rate of the variable rate down sampling module; and a differentiator stage responsive to an output of the output adjustment module.