Patent ID: 8711572

Claim:
A circuit board having a semiconductor chip embedded therein, comprising: a core board having opposing first and second surfaces and a through-hole penetrating the first and second surfaces; the semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein a plurality of first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer disposed on the first surface of the core board and the first active surface of the semiconductor chip and fills a gap between the through-hole and the semiconductor chip so as for the semiconductor chip to be fixed in position the through-hole; a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with a plurality of first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads provided on the semiconductor chip, wherein the first circuit layer has a plurality of series-connection portions; and a build-up structure provided on the second surface of the core board, the build-up structure comprising: a dielectric layer having a plurality of vias and a plurality of trenches; a circuit layer disposed in the trenches of the dielectric layer and being flush with the dielectric layer; and a plurality of conductive vias disposed in the vias of the dielectric layer and electrically connected to the circuit layer; and further comprising another build-up structure disposed on the first dielectric layer and the first circuit layer, the another build-up structure comprising: a second dielectric layer having another plurality of vias and another plurality of trenches; a second circuit layer disposed in the another trenches of the second dielectric layer and being flush with the second dielectric laver; and a plurality of second conductive vias disposed in the another vias of the second dielectric layer, allowing the second conductive vias to be electrically connected to the first and second circuit layers, the second circuit layer on the top of the another build-up structure to be provided with electrical contact pads, the another build-up structure to be covered with a solder mask layer, and a portion of a surface of the electrical contact pads to be exposed from a plurality of solder mask layer openings in the solder mask layer.