Patent ID: 8276027

Claim:
A semiconductor memory having an operation mode externally settable, the memory comprising: a plurality of registers for holding operation mode information for the semiconductor memory; a command generation section for generating a test start command in response to a control signal externally inputted; a data pad compression circuit for generating the operation mode information to be written to the plurality of registers by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent; a mask control circuit for generating a mask signal by which only updating of the operation mode information in an unupdated register out of the plurality of registers is permitted and the updating of the operation mode information in remaining registers out of the plurality of registers is skipped, at the time of updating the operation mode information; and a register control circuit for performing an update process in which the updating of the operation mode information in the remaining registers designated by the mask signal is skipped and the operation mode information generated according to the code is written to the unupdated register permitted by the mask signal, at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, wherein: the command generation section generates the test start command again if there is an unupdated register out of the plurality of registers after the update process; the data pad compression circuit inputs another code and changes the operation mode information; and the register control circuit performs the update process by using the operation mode information changed.