Patent ID: 7187046

Claim:
A FINFET complimentary metal oxide semiconductor (CMOS) device structure, comprising: an insulator layer on a semiconductor substrate; a first raised silicon on insulator (SOI), FINFET structure on said insulator layer; a second raised SOI FINFET structure on said insulator layer, parallel in direction to said first raised SOI FINFET structure; a gate insulator layer on the sides of a center portion of said first raised SOI FINFET structure, and on sides of a center portion of said second raised SOI FINFET structure; insulator shapes on a top surface of said center portion of said first raised SOI FINFET structure, and on a top surface of said center portion of said second raised FINFET structure; a conductive gate structure traversing said first raised SOI FINFET structure and said second raised SOI FINFET structure, with said conductive gate structure interfacing said gate insulator layer located on sides of the raised SOI FINFET structures, and overlying said insulator shapes located on the top surface of center portions of said raised SOI FINFET structures; insulator spacers, on sides of said raised SOI FINFET structures, and on sides of said conductive gate structure, each insulator spacer having a convex wall, comprised of silicon nitride, and at a thickness between about 300 to 5000 Angstroms; a first source/drain region of a first conductivity type in portions of said first raised SOI FINFET structure not covered by said gate structure, and a second source/drain region of a second conductivity type in portions of said second raised SOI FINFET structure not covered by said conductive gate structure; and metal shapes on said first source/drain region and on said second source/drain region; wherein a portion of the insulator spacers substantially surrounds the first source/drain region and another portion of the insulator spacers substantially surrounds the second source/drain region.