Patent ID: 8504854

Claim:
A computing system comprising: one or more functional blocks within a processor core, each configured to produce data corresponding to an activity level of a respective block, wherein each functional block is configured to operate at one or more discrete power-performance states (P-state); and a power manager within the processor core coupled to the one or more functional blocks, wherein the power manager is configured to: determine a virtual P-state corresponding to a desired power consumption, wherein the virtual P-state is not a supported discrete P-state; determine a respective minimum residency time to be used for each of a lower P-state lower than the virtual P-state and a higher P-state higher than the virtual P-state; and alternately select and convey the lower P-state and the higher P-state using the respective minimum residency times in order to produce an average power consumption over time that more closely corresponds to the desired power consumption than a power consumption corresponding to either the lower P-state or the higher P-state.