Patent ID: 7305641

Claim:
A method of redistributing white space within an integrated circuit floorplan to realize an efficiently arranged integrated circuit, comprising the steps of: providing the integrated circuit floorplan within which are located a plurality of circuit blocks to be efficiently arranged on the integrated circuit; determining where to place the circuit blocks on the integrated circuit using a min-cost flow based approach such that white space is minimized in the floorplan, said step of determining further comprising constructing a pair of network graphs G H and G V , applying the min-cost flow algorithm on G H and G V deriving residual graphs of G H and G V and applying a shortest path algorithm on the residual graphs to compute the positions of the circuit blocks within the integrated circuit floorplan; and redistributing the circuit blocks within the integrated circuit floorplan to obtain a minimal total wire length and optimized circuit block arrangement for the integrated circuit based on said determining.