Patent ID: 8395935

Claim:
A programmable memory device, comprising a semiconductor substrate body having a substrate surface including a periphery region and a memory array region, a plurality of trench isolation structures in the substrate body in both the periphery region and the memory array region, each trench isolation structure extending into the substrate body, and having a top surface that is above the substrate surface, so that inter-trench regions bounded by a plane level with the top surfaces of adjacent trench isolations structures, by sides of adjacent trench isolation structures and by the substrate surface are defined in both the periphery region and the memory array region, a programmable memory array in the memory array region and transistors at the substrate surface in the periphery region, the transistors at the substrate surface including gates inside the inter-trench regions, the memory array region having insulating material with pores in the inter-trench regions, the memory array comprising access devices in the substrate body and programmable memory elements over the substrate surface, wherein the access devices and memory elements are aligned at cross-points of bit lines and word lines, and at least one of a electrode element connecting the memory element with a corresponding access device, and at least a part of the memory element fill said each of said pores.