Patent ID: 7953505

Claim:
A digital filter device that filters a digital sound signal input to an input terminal and outputs an output digital signal from an output terminal, comprising: a first gain register stores a first gain multiplier value set for adjusting a gain characteristic of said output digital signal; a first coefficient register stores a plurality of filter coefficients set for said gain multiplier value; an IIR digital filter has at least a first adder that performs an arithmetic operation on signals and outputs the sum, a first multiplier that multiplies said digital sound signal input via said input terminal by a coefficient corresponding to a filter coefficient stored in said first coefficient register and outputs the product to said first adder, a first delay circuit that delays said digital sound signal input via said input terminal and outputs the delayed signal, a second multiplier that multiplies the signal output from said first delay circuit by a coefficient corresponding to a filter coefficient stored in said first coefficient register and outputs the product to said first adder, a second delay circuit that delays the output signal of the first adder and outputs the delayed signal, and a third multiplier that multiplies the signal output from said second delay circuit by a coefficient corresponding to a filter coefficient stored in said first coefficient register and outputs the product to said first adder; a gain multiplier multiples the signal output from said first adder by a gain multiplier value; a second adder adds said digital sound signal and the signal output from said gain multiplier and outputs the sum to said output terminal; a second gain register stores a newly set second gain multiplier value; a second coefficient register stores a plurality of new filter coefficients set for said second gain multiplier value; and a peak value controlling circuit controls said first coefficient register and said second coefficient register and adjusts a peak value of said output digital signal by shifting said gain multiplier value applied to said gain multiplier from said first gain multiplier value to said second gain multiplier value, wherein said peak value controlling circuit compares said first gain multiplier value and said second gain multiplier value with each other, and replaces said filter coefficients stored in said first coefficient register with said new filter coefficients stored in said second coefficient register at a timing when the gain multiplier value applied to said gain multiplier becomes zero or becomes closest to zero for the first time during shifting the gain multiplier value from said first gain multiplier value to said second gain multiplier value if said first gain multiplier value and said second gain multiplier value are different in sign.