Patent ID: 7154799

Claim:
A semiconductor memory comprising: a plurality of volatile memory cells; a plurality of word lines connected to said memory cells, respectively; a plurality of memory cell groups each constituted of said memory cells connected to a predetermined number of said word lines, respectively; a control circuit executing operations of a first memory mode and a second memory mode, the first memory mode being a mode in which each of the memory cells independently retains data and the second memory mode being a mode in which each of the memory cells in each of said memory cell groups retain same data; a plurality of flags corresponding to said memory cell groups, respectively, and indicating as a set state that said memory cells store data in the second memory mode; and a flag reset circuit that, in a changing operation of changing states of all of said memory cells from the second memory mode to the first memory mode, resets each of said flags in response to a first access to a corresponding memory cell group among said memory cell groups.