Patent ID: 7684533

Claim:
A jitter measurement circuit comprising: an input for receiving a reference signal whose jitter is to be measured; a clock input for receiving a clock signal having a series of cycles; and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement, said measurement circuit comprising; a plurality of n stages, each stage comprising a delay element having an input, the second and later delay elements having their inputs connected to the output of the previous stage and the first delay element having an input for receiving said reference signal, a latch connected to the input of a corresponding one of the delay elements, each latch having a clock input for receiving said clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal, and an analysis logic circuit having a plurality of n inputs connected to the outputs of said latches, said analysis logic circuit analyzing the values on said latches to give a measure of jitter, said analysis logic circuit comprising a priority encoder having a plurality of n inputs, each input connected to a respective one of said latch outputs, said priority encoder having a plurality of m outputs, said m outputs providing a binary number representing the signals on the priority encoder inputs, said analysis logic circuit further comprising a decoder having a plurality of m inputs, each decoder input connected to a respective one of the outputs of said priority encoder, a plurality of m AND circuits, each AND circuit having a first input for receiving the clock signal and a second input connected to a respective one of the outputs of said decoder, and a plurality of m incrementer circuits having a input connected to the output of a respective one of the outputs of said m AND circuits such that said incrementers present a histogram of the where the edge of the clock signal is located.