Patent ID: 6970899

Claim:
A calculating unit, comprising: a plurality of adder blocks, wherein each adder block comprises a plurality of single adders, a carry input, a carry output and a carry pass output, wherein a total number of single adders of the plurality of adder blocks is greater than a number of digits of an operand to be subtracted, wherein a signal at the carry pass output of one of the adder blocks is indicative of a carry passing through the respective adder block; a clock generator for feeding the adder blocks with operands to be processed according to a clock; a controller for controlling the clock generator such that the clock with which the operands to be processed are fed in, is decelerated, when the signal at the carry pass output is active; a unit for determining in which adder block of the adder blocks a least significant bit of the operand to be subtracted is disposed; a unit for deactivating the carry pass output of one or several adder blocks, which are provided for lower order digits with respect to the adder block in which the least significant bit of the operand to be subtracted is disposed; and a unit for feeding in a carry into the carry input of the adder blocks in which the least significant bit of the operand to be subtracted is disposed.