Patent ID: 7516379

Claim:
A circuit for determining operating speed of a clock associated with an integrated circuit (IC), comprising: an IC logic element located on the integrated circuit; a scan chain located on the integrated circuit; and a calibration circuit located on the integrated circuit and coupled to the IC logic element and to the scan chain, the calibration circuit comprising a first plurality of flip-flops and a combinational delay line, in which the calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode by measuring a difference in clock speed caused by power supply voltage drop between functional test mode and scan test mode and wherein the calibration circuit continuously compares a delay of the combinational delay line with a clock period of the clock signal, in which a digital delay provided by the combinational delay line is dynamically reconfigurable and in which the digital delay is used to choose a scan test frequency that tests the IC at a designed clock speed.