Patent ID: 7965809

Claim:
A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of said plurality of bits being lower order than a second part of said plurality of bits, said counter circuit comprising: a first counter configured to add said first part of said plurality of bits and said second value in response to said clock signal to output a third value regarding a result of adding said first and said second values; a second counter configured to add said second part of said plurality of bits and a fourth value in response to said clock signal; and a clock transmission control circuit coupled to said first and second counters to receive said clock signal and said third value, and to control whether or not to supply said clock signal to said second counter in accordance with said received third value; wherein said first counter comprises a flip-flop configured to latch one bit among said plurality of bits, and wherein said third value is said one bit latched by said flip-flop; and wherein said one bit is a least significant bit of said plurality of bits.