Patent ID: 7219324

Claim:
In an integrated circuit organized in rows of macro cells, a layout architecture, comprising: first, second, and third adjacent metal layers extending across the integrated circuit, wherein the first metal layer is disposed between the second metal layer and a layer of transistors in the macro cells, and the second metal layer is disposed between the third metal layer and the first metal layer; and a plurality of traces carrying three or more different potentials of voltage are routed in the metal layers parallel to the rows of macro cells, the plurality of traces comprising: a first power trace to supply a VDD voltage potential, a second power trace to supply a VSS voltage potential, and a third power trace to supply a third voltage potential, wherein the first, second, and third power traces connect to one or more transistors in a first macro cell, and at least one of the first, second, and third power traces is shared between adjacent rows of macro cells.