Patent ID: 7495610

Claim:
A system for decimating a sampling rate of an input signal comprising: a) filtering circuitry adapted to perform a number (N) of integrations of samples of the input signal for each of a plurality of code chips, such that the number (N) of integrations has a common integration period and different integration start times and each of the number (N) of integrations provides one of a number (N) of output samples of the input signal for one of a number (N) of chip-phases; and b) processing circuitry adapted to receive the number (N) of output samples for each of the plurality of code chips and process one of the number (N) of output samples corresponding to a select one of the number (N) of chip-phases for each of the plurality of code chips, such that the sampling rate of the input signal is reduced from a first sampling rate to a second sampling rate.