Patent ID: 7990191

Claim:
A digital phase-locked loop circuit comprising: a first counter which counts a first clock; a second counter which counts a third clock in which a second clock is divided by a predetermined number; a first phase detector which detects a relative phase difference between the first and the third clocks according to a first comparison result that clocks in which the third clock is sequentially delayed are compared with the first clock and a second comparison result that clocks in which the first clock is sequentially delayed are compared with the third clock; a second phase detector which measures the period of the second clock; a phase error calculating unit which calculates a phase difference between the first and the third clocks according to the value that the result detected by the first phase detector is normalized by the result detected by the second phase detector and the count values of the first and the second counters; and a digital control oscillator which outputs the second clock according to the result calculated by the phase error calculating unit.