Patent ID: 7075546

Claim:
A central processing unit (CPU), comprising: a chip select module, the chip select module defining a chip select signal, the chip select signal associated with an external device, the chip select module further including, an address space configured to store addresses associated with the external device, the address space providing an address section associated with the external device, the address section being subdivided into address sub-sections, each of the address sub-sections associated with an address range indicating an access to one of a memory region, a register region, or a first-in-first-out buffer region within the external device, the address range being assigned through the chip select signal for accessing the external device, the address sub-sections configured to determine a bus cycle based on an association with one of the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states; and wherein the monitoring of the wait line between the CPU and the external device and the CPU waiting for the number of wait states are mutually exclusive, and wherein the number of wait states is generated internally within the CPU.