Patent ID: 7418585

Claim:
A multiprocessing system, comprising: a multithreading microprocessor, comprising: a plurality of hardware thread contexts (TCs), each configured to store an execution state of a respective thread, each TC having a program counter register and a general purpose register set; a set of hardware execution units, shared by said plurality of TCs, configured to concurrently execute instructions of said threads having execution states stored in said plurality of TCs; and a set of exception state storage hardware, configured to store an exception state of an exception raised to the microprocessor, shared by said plurality of TCs rather than being replicated for each of said plurality of TCs such that a ratio of said plurality of TCs to said set of exception state storage hardware is greater than one; and wherein said microprocessor is configured to suspend issuing to the shared set of hardware execution units instructions of said threads executing on said plurality of TCs in response to receiving an exception; and a multiprocessor operating system (OS), configured to view each of said plurality of TCs as a distinct CPU, even though said set of exception state storage hardware is shared by said plurality of TCs rather than being replicated for each of said plurality of TCs such that a ratio of said plurality of TCs to said set of exception state storage hardware is greater than one.