Patent ID: 8304867

Claim:
An integrated circuit (IC) device, comprising: a substrate having a top surface including active circuitry including a plurality of input/output (I/O) nodes, and a plurality of die pads coupled to said plurality of I/O nodes; a first dielectric layer including first dielectric vias over said plurality of die pads; a redirect layer (RDL) including a plurality of RDL capture pads coupled to said plurality of die pads over said first dielectric vias; a second dielectric layer including second dielectric vias over said plurality of RDL capture pads, wherein at least one of said second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of said IC die and is oriented along a line from said neutral stress point to said crack arrest via to face in a range of ±30 degrees from said line; under bump metallization (UBM) pads coupled to said plurality of RDL capture pads over said second dielectric vias, and metal bonding connectors on said UBM pads.