Patent ID: 7911436

Claim:
A shift register comprising: a plurality of stages connected to one another and configured to sequentially generate output signals, wherein each of the stages of the plurality of stages has first and second output terminals configured to alternately output a first output voltage, and wherein each of the stages comprises: an output unit comprising a transistor and a capacitor connected between two terminals of the transistor; a pull-up driver charging the capacitor; and a pull-down driver discharging the capacitor, wherein each of the stages further comprises an output switching unit configured to receive an output of the output unit and output the first output voltage and the second output voltage alternately to the first output terminal and the second output terminal, wherein the output switching unit comprises: a first transistor configured to switch the output of the output voltage generator according to a first switching signal, a second transistor configured to switch the output of the output voltage generator according to a second switching signal, a third transistor configured to pass or cut off the second output voltage to the first output terminal according to the second switching signal, and a fourth transistor configured to pass or cut off the second output voltage to the second output terminal according to the first switching signal, wherein an input terminal of the third transistor is directly connected to a control terminal of the first transistor, and an input terminal of the fourth transistor is directly connected to a control terminal of the second transistor.