Patent ID: 8883644

Claim:
A method for fabricating an integrated circuit, comprising: forming a first tiered mandrel, the first tiered mandrel comprising: a laterally-elongated first terminal section; and a plurality of laterally-elongated first extensions extending transverse to the first terminal section; forming a second tiered mandrel, the second tiered mandrel comprising: a laterally-elongated second terminal section; and a plurality of laterally-elongated second extensions extending transverse to the second terminal section, wherein the first and the second extensions are interdigitated, and wherein the first and second terminal sections are disposed on opposite sides of the interdigitated first and second extentions; forming spacers on sidewalls of the first and second tiered mandrels; selectively etching the first and second tiered mandrels relative to the spacers to form a spacer pattern defined by the spacers; and processing an underlying layer through a mask defined by the spacer pattern.