Patent ID: 7325173

Claim:
A semiconductor memory, comprising: a first regular memory block to which write data of a plurality of bits are written, said write data being received by a first data terminal group including a first data terminal; a second regular memory block to which write data of a plurality of bits are written, said write data being received by a second data terminal group including a second data terminal; a parity operational unit which generates parity data of a plurality of bits corresponding to said write data of at least one of the first and second regular memory blocks; a parity memory block to which said parity data are written; a first distribution unit which outputs first test data supplied to said first data terminal as common write data to said first regular memory block; a second distribution unit which outputs second test data supplied to said second data terminal as common write data to said second regular memory block and said parity memory block; a data restoration unit which corrects an error of data of a plurality of bits which are read from said first and second regular memory blocks with parity data of a plurality of bits which are read from said parity memory block and outputs the resultant data as correction data of a plurality of bits; a first coincidence detection unit which detects coincidence or dissidence of data of a plurality of bits which are read from said first regular memory block; a second coincidence detection unit which detects coincidence or dissidence of data of a plurality of bits which are read from said second regular memory block and said parity memory block; and a test control unit which enables functions of said first and second distribution units and said first and second coincidence detection units and disables functions of said parity operational unit and said data restoration unit during a first data compression test mode which disables an error correction function, and enables functions of said first distribution unit, said first coincidence detection unit, said parity operational unit, and said data restoration unit, a first output function which outputs said second test data to said second regular memory block, said first output function being included in said second distribution unit, and a first detection function which detects coincidence or dissidence of correction data which are output from said data restoration unit, said first detection function being included in said second coincidence detection unit, and disables a second output function which outputs said second test data to said parity memory block, said second output function being included in said second distribution unit, and a second detection function which detects coincidence or dissidence of parity data which are read from said parity memory block, said second detection function being included in said second coincidence detection unit, during a second data compression test mode which enables the error correction function.