Patent ID: 6981089

Claim:
A memory system comprising: an address/command bus; a multidrop data bus having a predetermined number of data signaling lines; a memory controller to transmit address and command signals on the address/command bus, and to transmit and receive data signals on the multidrop data bus corresponding to the address and command signals; first and second memory units, each connected to both the address/command bus and the multidrop data bus, at least the second memory unit comprising controllable termination circuitry having on and off states and coupled to the multidrop data bus and termination control logic to set the state of the termination circuitry according to decoded commands received on the address/command bus; wherein each memory unit comprises a programmable configuration register to configure the termination control logic according to stored termination control parameters, the memory controller having a termination configuration mode for transmitting termination control parameters to each of the memory units separate from the decoded commands for storage in that unit's configuration register.