Patent ID: 7512915

Claim:
A design structure instantiated in a machine readable medium for design and manufacturing a test circuit, the test circuit comprising: a plurality of device under test (DUT) structures; a control block for controlling testing of the DUT structures; a logic controller having a decoder which activates at least one DUT structure; a decode level translator which provides a required gate voltage to one or more of the DUT structures; at least one protect circuit coupled to at least one supply circuit, the supply circuit further coupled to at least one isolation circuit and to at least one of the DUT structures; and a control circuit for controlling the protect circuit, the isolation circuit, and the supply circuit; the protect circuit comprises a first logic gate coupled to an nFET and a second logic gate coupled to a pFET, the protect circuit protects the supply circuit from excessive source to drain, and gate to drain potential differences when high voltages are applied; the isolation circuit comprises a level translator comprising a plurality of pFETs, a plurality of nFETs, and a Vdd powered inverter; the isolation circuit electrically isolates the DUT structures so that no functional circuitry is affected during a test, nor is the functional circuitry affected by a leakage current while the test circuit is not in operation.