Patent ID: 7456058

Claim:
A method for fabricating a stressed MOS device comprising the steps of: forming a gate insulator layer overlying a surface of a semiconductor substrate; depositing a layer of gate electrode material having a first Young's modulus onto the gate insulator layer; patterning the layer of gate electrode material to form a first portion of a gate electrode having a top and having opposing sidewalls spaced apart by a first width; depositing a layer of spacer forming material and etching the layer of spacer forming material to form spacers adjacent the opposing sidewalls; ion implanting conductivity determining ions to form at least a portion of a source region and at least a portion of a drain region using the spacers as ion implantation masks; removing the spacers; depositing a layer of material having a second Young's modulus less than the first Young's modulus overlying the first portion of the gate electrode and the portion of the source region and the portion of the drain region; removing a portion of the layer of material to expose the top of the first portion of the gate electrode; depositing a second layer of gate electrode material overlying the layer of material and contacting the top of the first portion of the gate electrode; patterning the second layer of gate electrode material to form a second portion of the gate electrode contacting the top of the first portion of the gate electrode, the second portion having a second width greater than the first width; and depositing a tensile contact liner overlying the second portion of the gate electrode.