Patent ID: 7119395

Claim:
A memory cell comprising; first and second source/drain regions disposed at a top side of a semiconductor body through the introduction of dopant, a channel region provided between the first and second source/drain regions; a gate dielectric and a gate electrode arranged on the channel region, said gate electrode defining a source-side flank and a drain-side flank and arranged in a word line web comprising at least two word line layers; electrically conductive spacers arranged on said source-side flank and said drain-side flank of said gate electrode and electrically connected thereto, said electrically conductive spacers are arranged at the flanks of a first word line layer, further arranged at the bottom of the word line web and having at least one second word line layer projecting over said electrically conductive spacers; and a storage layer disposed above the transition or boundary between a channel region and at least one of the source/drain regions, the storage layer being interrupted above an intervening, central part of the channel region and, the storage layer being formed as a portion of the gate dielectric and containing nanocrystals or nanodots.