Patent ID: 7030674

Claim:
A multiphase clock generator, comprising: a first clock divider having a first input for receiving a first input clock signal, a second input for receiving a reset signal and an output for providing a first output clock signal; a second clock divider having a first input for receiving the first input clock signal, a second input for receiving a reset signal and an output for providing a second output clock signal; a third clock divider having a first input for receiving a second input clock signal, a second input for receiving a reset signal and an output for providing a third output clock signal; and a fourth clock divider having a first input for receiving the second input clock signal, a second input for receiving a reset signal and an output for providing a fourth output clock signal; wherein the reset signal for the first clock divider is generated from a first reset signal; wherein the reset signal for the second clock divider is generated from the first reset signal and the first output clock signal; wherein the reset signal for the third clock divider is generated from the first reset signal, the second output clock signal and the second input clock signal; and wherein the reset signal for the fourth clock divider is generated from the first reset signal and the third output clock signal.