Patent ID: 7657773

Claim:
A clock distribution (CD) chip comprising: first and second input pins adapted to receive first and second input clock signals corresponding to either a differential input clock signal or two single-ended (SE) input clock signals; input buffer circuitry adapted to receive and handle the input clock signals from the input pins; clock generation and distribution circuitry adapted to receive a reference clock signal and one or more other clock signals from the input buffer circuitry and programmably generate (i) any of zero, one, or more zero-delay (ZD) clock signals based on the reference clock signal and (ii) any of zero, one, or more non-zero-delay (NZD) clock signals based on the one or more other clock signals, wherein the clock generation and distribution circuitry comprises: a phase-locked loop (PLL) adapted to generate a PLL clock signal based on the reference clock signal and the feedback clock signal; a multiplexer (mux) adapted to receive and select between (i) the reference clock signal and (ii) a clock signal derived from the PLL clock signal to provide a mux clock signal; one or more clock dividers each adapted to divide the mux clock signal by a specified divisor value; and a programmable switch fabric adapted to (i) receive a divided clock signal from each clock divider, a first other clock signal derived from the first input clock signal, and a second other clock signal derived from the second input clock signal and (ii) generate each ZD clock signal and each NZD clock signal in a non-blocking manner, such that each output clock signal may be either a ZD clock signal or an NZD clock signal independent of whether any other output clock signal is a ZD or NZD clock signal; fanout circuitry adapted to generate an output clock signal for each of the ZD and NZD clock signals; a plurality of output pins adapted to present the output clock signals; a feedback pin adapted to receive one of the output clock signals presented at one of the output pins; and feedback buffer circuitry adapted to derive a feedback clock signal from the output clock signal presented at the feedback pin and provide the feedback clock signal to the clock generation and distribution circuitry for use in generating each ZD clock signal.