Patent ID: 8437989

Claim:
A simulation method for a semiconductor circuit comprising: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt 0 of the terminal region between the plurality of contacts and the main body by a first formula Rt ⁢ ⁢ 0 = ρ 0 × ( L ′ + L 0 ′ ) L ′ × ( W ′ + W 0 ′ ) , wherein ρ 0 , L′ 0 , W′ 0 are fitting parameters obtained by predetermined approximations of the formula to measured data of the well resistor; wherein L′ is a length of the terminal region in a longitudinal direction of the well resistor; and wherein W′ is a width of the terminal region in a width direction of the well resistor.