Patent ID: 8214573

Claim:
A computing device comprising: a plurality of processor cores; a memory device coupled to the plurality of processor cores, the memory device having stored therein a plurality of instructions to be executed by at least one of the plurality of cores; logic to allocate at least two processor cores to a first group for managing interrupt handling, wherein processor cores not allocated to the first group form a second group; and a chipset to generate at least one of a system management interrupt and platform management interrupt, collectively referred to as a management interrupt, the management interrupt directed to one or more of the processor cores of the first group, wherein the one or more of the processor cores of the first group are configured to receive the management interrupt for handling and also configured to broadcast at least one of the management interrupt, or a new interrupt in response to the management interrupt, to at least one processor core of the second group, when further handling is to be performed by the at least one processor core of the second group.