Patent ID: 7301804

Claim:
A method for forming a multistate memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the gate of each transistor along columns of the memory array; forming a number of source lines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the source line in a shared trench such that a multistate cell transistor and a reference cell transistor share a common source line; and wherein the number of vertical pillars can be programmed in a reverse direction to have a one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region by biasing a source line to a voltage higher than VDD, grounding a bit line, and selecting a gate by a word line address.