Patent ID: 7158420

Claim:
An integrated circuit memory, comprising: a semiconductor body having a first conductivity type; a plurality of word lines overlying the semiconductor body; an array of memory cells between the plurality of word lines and the semiconductor body, the array including at least one sector, and the memory cells including respective control gates contacting word lines in the plurality of word lines, and charge trapping structures between the control gates and the semiconductor body; a plurality of current control lines arranged generally orthogonally with respect to the plurality of word lines, between columns of memory cells in the array, and overlying the semiconductor body, arranged to induce inversion bit lines in the semiconductor body in response to bias voltages applied to the current control lines; control circuitry coupled to the plurality of current control lines, the plurality of word lines and the semiconductor body, the control circuitry applying biasing arrangements for programming and erasing data by charge storage in the memory cells, and for reading stored data; wherein the biasing arrangement for programming a bit of data on a left side of a particular memory cell in the array induces source side hot electron injection on the left side of the charge trapping structure via inversion bit lines to establish a high threshold state for reads of the left side; the biasing arrangement for programming a bit of data on a right side of the particular memory cell in the array induces source side hot electron injection on the right side of the charge trapping structure via inversion bit lines to establish a high threshold state for reads of the right side; the biasing arrangement for erasing data in the at least one sector includes inducing charge balancing, by applying a negative voltage between at least one word line coupled to the memory cells in the sector and the semiconductor body sufficient to induce FN tunneling between the charge trapping structure and the semiconductor body balanced by FN tunneling between the control gate and the charge trapping structure, until a target low threshold voltage is established in the memory cells in the sector; the biasing arrangement for reading a bit of data on one of a left side and a right side of a particular memory cell in the array induces relatively conductive inversion bit lines on the left and right sides of the particular memory cell and applies a read bias voltage to the word line coupled to the control gate of the particular memory cell.