Patent ID: 8258831

Claim:
A clock generator comprising: a phase lock loop configured to generate an output clock; and a lock detector coupled to the phase lock loop, the lock detector configured to generate a lock signal based on control signals generated by the phase lock loop, the control signals controlling a characteristic of the output clock, the lock signal indicating a lock-state of the output clock, the lock detector including: a mismatch detector configured to detect a difference between a phase of a reference clock and a phase of the output clock and generating a mismatch signal based on the difference; and a lock-signal-generator coupled to the mismatch detector, the lock-signal-generator configured to generate the lock signal based on the mismatch signal, the lock-signal-generator having: a mismatch-signal-sampler configured to output a sample_mismatch signal; and a lock-counter coupled to the mismatch-signal-sampler, the lock-counter configured to be clocked by at least one of the control signals and cleared by the sample_mismatch signal, the lock-signal-generator outputting the lock signal based on an output of the lock-counter.