Patent ID: 8738349

Claim:
A method for logic simulation of a connectivity level description of an integrated circuit, where the connectivity level description comprises a plurality of logic elements, the method comprising: in a first processor, clustering logic elements into cluster groups each comprising at least one of the plurality of logic elements, where the cluster groups are sized such that, during a simulation cycle, each cluster group is capable of being simulated on a different processor block of a second processor, wherein processing units of the second processor is configured for simultaneous operation, and wherein each cluster group is defined by a height corresponding to a number of logic levels of the cluster group and a width corresponding to a number of logical outputs of the cluster group, where the height and width of the cluster group define the size of the cluster group, and wherein the height and width combination of at least one cluster group differs from the height and width combination of at least one other cluster group; and in the second processor, simultaneously simulating a plurality of the cluster groups each being simulated on a different one of the processing units.