Patent ID: 7577027

Claim:
A multi-state NAND memory cell comprising: a substrate comprising a first conductive material; first and second active areas within the substrate, the first and second active areas comprised of a second conductive material; a control gate above and between the first and second active areas, the control gate comprising an extension; and a discontinuous trapping layer between the control gate and the substrate such that the trapping layer is isolated from the control gate by a first dielectric layer and from the substrate by a continuous second dielectric layer and the control gate extension extends into and separates the trapping layer but not the continuous second dielectric layer, wherein the trapping layer is configured for asymmetrical charge trapping, in response to asymmetrical biasing of the first and second active areas and a negative control gate voltage of between −10V and −15V, of a first data bit adjacent the first active area and a second data bit adjacent the second active area.