Patent ID: 7138709

Claim:
A microelectronic package array, comprising: a first microelectronic package including a first carrier substrate having a first die side and a first non-die side, a first die electrically coupled to the first die side, and a land pad on the first die side; an encapsulation material encasing the first die, the encapsulation material having a form factor with a peripheral surface opposite of the die that intersects the first die side of the first carrier substrate; a second microelectronic package comprising a second carrier substrate having a second die side and a second non-die side, a second die electrically coupled to the second die side, and a bond pad on the second non-die side; and an intermediate substrate having a first side and a second side, the first side being directly coupled to the first die side of the first carrier substrate and located external of the peripheral surface of the encapsulation material, the second side being directly coupled to the second non-die side of the second carrier substrate, the intermediate substrate comprising of a substantially solid core having a first side and a second side, the substantially solid core comprising of a C-stage resin reinforced with a matrix to increase rigidity of the microelectronic packages and control the coefficient of thermal expansion of the intermediate substrate.