Patent ID: 7233513

Claim:
A semiconductor memory device comprising: a plurality of memory cells each of which includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor having a drain connected to a source of the first MOS transistor; a memory cell array in which the memory cells are arranged in a matrix on a semiconductor substrate; bit lines each of which connects the drains of the first MOS transistors in a same column; word lines each of which is formed by connecting commonly the control gates of the first MOS transistors in a same row; select gate lines each of which is formed by connecting commonly the gates of the second MOS transistors in a same row; a row decoder which selects any one of the word lines and any one of the select gate lines; first metal wiring layers which are provided for the word lines in a one-to-one correspondence and which are electrically connected to the corresponding ones of the word lines and transmit a first row select signal for the row decoder to select one of the word lines; an interlayer insulating film which is formed on the semiconductor substrate so as to cover the memory cells; and metal wiring lines which are formed at a plurality of levels in the interlayer insulating film, the first metal wiring layers being made of the metal wiring lines located at the level of the lowest layer.