Patent ID: 8053897

Claim:
A method of forming an electrical carrier wafer contact together with an isolation trench in an SOI wafer for integrated circuits, the method comprising the following steps: forming with a masking layer a first trench having a first width for the isolation trench and forming a second trench for a carrier wafer contact, said second trench having a second width being greater than said first width, wherein said first and second trenches extend to a buried insulating layer; forming an insulating layer on each sidewalls of the first and second trenches; filling a first fill material into said first and second trenches, whereby said first trench is filled and said first fill material only covers the sidewalls and a trench bottom of said second trench having said greater width; etching said first fill material until said fill material is removed from the trench bottom of said second trench thereby forming lateral spacers in said second trench, said spacers being comprised of said first fill material; further etching to downwards extend said second trench to reach down to the carrier wafer; depositing a second conductive fill material to fill said downwards extended second trench, the steps commonly performed for said electrical carrier wafer contact and said isolation trench.