Patent ID: 7242611

Claim:
A nonvolatile semiconductor memory device comprising: a memory array including a plurality of nonvolatile memory cell transistors arranged in rows and columns, and each storing a logical value of N bits according to a threshold voltage; a memory array sense amplifier operating for lower foot verify to provide a logical value of N bits by determining N times a range of a threshold voltage of a selected memory cell by binary chop searching based on sections of a threshold voltage for the lower foot verify, and operating for upper foot verify to provide a logical value of N bits by determining N times the range of a threshold voltage of the selected memory cell by the binary chop searching based on the sections of a threshold voltage for the upper foot verify; a first buffer having N bits each storing a write target value for a corresponding memory cell: a second buffer storing in each bit a value determining processing to be effected on a corresponding memory cell; a write driver selecting application of a write pulse when the bit in the second buffer corresponding to said selected memory cell indicates a first value; and a verify circuit comparing a logical value of the N bits provided from said memory array sense amplifier with the write target value of the corresponding N bits in said first buffer, providing a signal indicating success of the verify when a result of the comparison indicates matching, and providing a signal indicating failure of the verify when a result of the comparison indicates mismatching, wherein when the result of comparison indicates the matching, and the bit in said second buffer corresponding to said selected memory cell indicates the first value, said verify circuit changes the said bit in said second buffer to indicate a second value.