Patent ID: 6978390

Claim:
An apparatus including integrated processor circuitry, said apparatus comprising: a plurality of interface electrodes to convey at least a plurality of incoming instructions, including a power management instruction, from at least one signal source; a plurality of subcircuits coupled to at least a portion of said plurality of interface electrodes and including pipeline subcircuitry responsive to a first clock signal having active and inactive states by selectively operating on one or more of said plurality of incoming instructions for data processing, wherein a first portion of said pipeline subcircuitry is responsive to said active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of said one or more of said plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to said power management instruction, and a second portion of said pipeline subcircuitry is coupled to said first pipeline subcircuitry portion and responsive to said active first clock signal by executing said one or more decoded instructions; control circuitry coupled to said plurality of subcircuits and responsive to said one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to said one or more first selected assertion and de-assertion states of said one or more local control signals with said second selected assertion and de-assertion states following reception of said power management instruction; and clock circuitry coupled to said control circuitry and said plurality of subcircuits, and responsive to said one or more clock control signals by providing at least said first clock signal with said first clock signal inactive state corresponding to said one or more second selected assertion and de-assertion states of said one or more clock control signals.