Patent ID: 7729415

Claim:
A high-speed interface for implementation in a programmable device, comprising: multi-gigabit transceivers of the programmable device each including locked-loop circuitry to provide transmit and receive lock signals; the multi-gigabit transceivers configured with inputs for a reference transmit clock signal and a reference receive clock signal; one of the multi-gigabit transceivers configured to provide a first transmit clock signal, a first receive clock signal, and a second receive clock signal; the first transmit clock signal provided responsive to the reference transmit clock signal; the first receive clock signal and the second receive clock signal provided responsive to the reference receive clock signal or derived from received data; the first receive clock signal having a first frequency; the second receive clock signal having a second frequency different from the first frequency of the first receive clock signal; the multi-gigabit transceivers coupled to obtain the first transmit clock signal and the first receive clock signal to include feed back of the first transmit clock signal and the first receive clock signal to the one of the multi-gigabit transceivers; the first transmit clock signal for providing a transceiver reference clock signal to each of the multi-gigabit transceivers for referencing the multi-gigabit transceivers to the one of the multi-gigabit transceivers for synchronizing the multi-gigabit transceivers to control lane-to-lane skew; a data rate converter coupled to obtain a second transmit clock signal and configured to fractionally multiply the second transmit clock signal to provide the reference transmit clock signal; a skew synchronization block coupled to obtain the transmit and receive lock signals from each of the multi-gigabit transceivers; the skew synchronization block configured to provide respective receive and transmit synch adjustment signals to each of the multi-gigabit transceivers; and the receive and transmit synch adjustment signals for respectively adjusting synchronous operation of the multi-gigabit transceivers in receive and transmit directions to maintain the lane-to-lane skew for the high-speed interface within a target range.