Patent ID: 7812386

Claim:
A semiconductor memory device comprising: a memory cell unit including at least one memory cell transistor, the memory cell transistor including: first and second semiconductor regions with a first conductivity which are formed apart from each other in a surface of a semiconductor layer with a second conductivity opposite to the first conductivity; a multi-layer gate which is formed on the semiconductor layer between the first and second semiconductor regions with a first gate insulating film interposed therebetween, the multi-layer gate electrode including a charge accumulation layer and a control gate; and a first insulating film formed on the first and second semiconductor regions; a select transistor which selects the memory cell unit, the select transistor including: third and fourth semiconductor regions with the first conductivity which are formed apart from each other in a surface of the semiconductor layer, the fourth semiconductor region being deeper than the third semiconductor region in the semiconductor layer; a gate electrode which is formed on the semiconductor layer between the third and fourth semiconductor regions with a second gate insulating film interposed therebetween; and a second insulating film formed on the third semiconductor region, an interface between the third semiconductor region and the second insulating film being located in a same plane as an interface between the semiconductor layer and the second gate insulating film; a contact plug formed on the fourth semiconductor region, an interface between the fourth semiconductor region and the contact plug being positioned low to have a stepped portion with respect to the interface between the semiconductor layer and the second gate insulating film, the first contact plug being electrically connected to one of bit and source lines; and a memory cell array in which a plurality of memory cell units and a select transistor are formed.