Patent ID: 8704350

Claim:
A stacked wafer level package comprising: a rearrangement wiring layer; an external connector disposed on a bottom of the rearrangement wiring layer and electrically connected to the rearrangement wiring layer; a chip connector and an internal connector disposed above the rearrangement wiring layer and electrically connected to the rearrangement wiring layer; a semiconductor chip mounted on the rearrangement wiring layer and electrically connected to the chip connector by a connection terminal; a mounting layer connecting the semiconductor chip mounted on the rearrangement wiring layer and the internal connector; a solder ball, a bottom part of the solder ball being electrically connected to the internal connector; a sealing member to seal the semiconductor chip and the solder ball and having a contact hole to expose upper portions of the solder ball; a metal post filled in the contact hole through the sealing member, a bottom part of the metal post being electrically connected to an upper part of the solder ball, the metal post being made of conductive material; and an electronic component stacked on the sealing member and electrically connected to the metal post.