Patent ID: 8429367

Claim:
An integrated circuit comprising: scheduler logic to schedule a next request from pending requests for any one of a plurality of ranks of memory in a memory channel, each one of the plurality of ranks of memory representing a set of memory devices sharing a same chip select signal; clock enable (CKE) coordination logic to control a CKE signal to a rank of memory in coordination with the scheduler logic, the CKE coordination logic to: formulate a prediction as to whether the scheduler logic will or will not schedule the next request to the rank of memory, the prediction based on a combination of conditions that indicate the prediction is likely, the combination of conditions related to any two or more of: the other rank has reached its electrical throttling limit, the rank's minimum CKE delay has elapsed, thermal throttling is not de-asserting the rank's CKE, the scheduler logic has not shifted major mode since an immediately preceding scheduled request, and the other rank has a pending request of the same type; determine that the CKE signal to the rank of memory is de-asserted and assert the CKE signal to the rank of memory when the prediction is that the scheduler logic will schedule the next request to the rank of memory; and determine that the CKE signal to the rank of memory is asserted and de-assert the CKE signal to the rank of memory when the prediction is that the scheduler logic will not schedule the next request to the rank of memory.