Patent ID: 8566485

Claim:
A direct memory access (DMA) controller, comprising: a control circuit configured to retrieve DMA transmit data; a converter configured to receive the DMA transmit data from the control circuit and convert the DMA transmit data into transformed data for transmission to at least one DMA channel interface circuit; wherein the converter includes: an offload engine configured to receive the DMA transmit data; an exclusive-OR (XOR) circuit configured to receive the DMA transmit data; an XOR first-in first-out (FIFO) circuit coupled to the output of the XOR circuit; an offload FIFO circuit coupled to the output of the offload engine; a copy FIFO circuit configured to receive the DMA transmit data; and an arbitration circuit configured to select one of the XOR FIFO circuit, offload FIFO circuit, or copy FIFO circuit.