Patent ID: 8890163

Claim:
A semiconductor device, comprising: a memory device including a field effect transistor (FET), the memory device comprising: a gate stack disposed on a channel region in a silicon substrate; a lightly doped drain junction region disposed underneath the gate stack and adjacent to a side thereof in the channel region; a crystallized silicon layer disposed on the silicon substrate; a metal silicide layer disposed on the crystallized silicon layer and extending into the lightly doped drain junction region, wherein the metal silicide layer includes an upper portion and a lower portion, wherein an uppermost surface of the lower portion of the metal silicide layer is disposed at a lower level than a top surface of the lightly doped drain junction region and wherein the upper portion of the metal silicide layer extends into an upper portion of the lightly doped drain junction region; an insulating layer disposed on the metal silicide layer; and a contact plug disposed substantially vertically through the insulating layer and the metal silicide layer, the contact plug having a metal barrier layer lining in the insulating layer and physically connecting with the metal silicide layer, wherein the metal barrier layer lining of the contact plug is filled with a conductive material.