Patent ID: 7190071

Claim:
A stackable semiconductor package comprising: a substrate having a first surface, an opposite second surface, and central throughhole between the first and second surfaces; a plurality of electrically conductive circuit patterns on each of the first and second surfaces of the substrate, wherein the circuit patterns of each of the first and second surfaces of the substrate include a plurality of lands, the circuit patterns of the first surface also include a plurality of bond fingers, and at least some of the circuit patterns of the first surface are electrically connected through the substrate to some of the circuit patterns of the second surface; a semiconductor chip in said throughhole and electrically connected to the bond fingers, wherein the semiconductor chip has a first surface with bond pads thereon, and an opposite second surface, the first surface of the semiconductor chip faces in a same direction as the first surface of the substrate, and the second surface of the semiconductor chip is flush with the second surface of the substrate, wherein the second surface of the semiconductor chip is exposed; and a hardened encapsulant within said through hole and covering the semiconductor chip and the bond fingers, wherein the lands of each of the first and second surfaces are outward of a perimeter of the encapsulant.