Patent ID: 7761762

Claim:
A process of operating an adapter and test access port circuitry, the adapter having a first set of interface leads and a second set of interface leads, the first set of interface leads including a clock lead, a data in lead, and a data out lead, the second set of interface leads including a TCK lead, a TMS lead, a TDI lead, and a TDO lead, the second set of interface leads being coupled with the test access port circuitry, the test access port circuitry having a TAP controlling operation of the test access port circuitry in first states and in second states, in the first states the TAP controls shifting data from the TDI lead to the TDO lead, and in the second states the TAP controls no shifting of data from the TDI lead to the TDO lead, the process comprising: A. coupling data from the data in lead to the TDI lead and from the TDO lead to the data out lead while the TAP is in the first states; and B. shifting data on one of the data in lead and the data out lead while not coupling data from the data in lead to the TDI lead and from the TDO lead to the data out lead while the TAP is in the second states.