Patent ID: 8665354

Claim:
A solid-state image pickup device comprising: a pixel array including a plurality of pixels arrayed in a matrix form, each pixel having a photoelectric conversion element and an electric charge accumulation section; a plurality of column signal lines respectively provided in correspondence with columns of the pixel array; and a row selection circuit selecting a row of the pixel array and activating a reset signal and a transfer signal outputted to each pixel at the selected row in order just mentioned, when the inputted reset signal is in an active state, each pixel at the selected row initializing the electric charge accumulation section and outputting to the corresponding column signal line, as a first analog signal, a signal in accordance with an amount of electric charges in the electric charge accumulation section in an initial state; and when the inputted transfer signal is in an active state, each pixel at the selected row transferring to the electric charge accumulation section the photoelectric charges generated by the photoelectric conversion element and outputting to the corresponding column signal line, as a second analog signal, a signal in accordance with the amount of electric charges in the electric charge accumulation section after the transfer of the photoelectric charges, the solid-state image pickup device further comprising: a plurality of analog-to-digital converters respectively in correspondence with the columns of the pixel array, each of the analog-to-digital converters digitally converting the first and second analog signals received via the column signal lines at the corresponding columns to respectively output first and second digital signals; and a plurality of data holding sections respectively provided in correspondence with the columns of the pixel array, wherein each of the data holding sections includes: a first latch circuit taking in and holding the first digital signal outputted from the analog-to-digital converter provided at the corresponding column based on a first pulse signal generated during a period from when the reset signal outputted to the currently selected row turns to an inactive state to when the transfer signal subsequently turns to an active state; a second latch circuit taking in and holding the first digital signal held at the first latch circuit based on a second pulse signal generated during a period from when the transfer signal outputted to the currently selected row turns to an inactive state to when the reset signal outputted to the next selected row turns to an active state; and a third latch circuit taking in and holding the second digital signal outputted from the analog-digital converter provided at the corresponding column based on a third pulse signal generated during a period from when the transfer signal outputted to the currently selected row turns to an inactive state to when the reset signal outputted to the next selected row turns to an active state.