Patent ID: 7730287

Claim:
A method of processing data in a programmable processor, the method comprising: decoding instructions for execution using an execution unit coupled to a register file comprising a plurality of registers, the execution unit operable to execute instructions by partitioning data stored in registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions; in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways and returning the re-arranged data to a register in the register file; and in response to decoding different group arithmetic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the group arithmetic instructions include first, second, and third group multiply-and-add instructions each of which (i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements and partitions data in a third register in the register file into a third plurality of data elements which are equal in size to one another, (ii) multiplies each data element in the first register with a corresponding data element in the second register to produce a plurality of products, (iii) adds each product in the plurality of products to a corresponding data element in the third register to produce the plurality of individual results, and (iv) provides the plurality of individual results as the catenated result, wherein the first group multiply-and-add instruction multiplies data elements of 8-bit integer data and adds data elements of 16-bit integer data, the second group multiply-and-add instruction multiplies data elements of 16-bit integer data and adds data elements of 32-bit integer data, and the third group multiply-and-add instruction multiplies data elements of 32-bit floating point data and adds data elements of 32-bit floating-point data.