Patent ID: 8058128

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a mask pattern on an active region of a substrate defined by an isolation region, the mask pattern including an opening therein exposing a portion of the active region; etching the exposed portion of the active region to define a preliminary gate trench therein, wherein portions of the mask pattern extend to edges of the active region outside the preliminary gate trench; performing an annealing process on the preliminary gate trench and the portions of the mask pattern extending to the edges of the active region outside the preliminary gate trench to form a gate trench from the preliminary gate trench, wherein the gate trench and the preliminary gate trench have a substantially similar width defined between the edges of the active region including the portions of the mask pattern thereon; prior to performing the annealing process, performing a cleaning process on the substrate including the preliminary gate trench therein, wherein the cleaning process reduces a thickness of the mask pattern without substantially increasing a width of the opening therein to define the portions of the mask pattern extending to the edges of the active region outside the preliminary gate trench, wherein the annealing process is performed at a temperature sufficient to substantially remove portions of the active region on opposing sidewalls of the preliminary gate trench to form the gate trench, wherein opposing sidewalls of the gate trench are substantially defined by portions of the isolation region; and forming a gate electrode in the gate trench.