Patent ID: 8039302

Claim:
A method of making a semiconductor package, comprising: providing a substrate; mounting a first semiconductor die on the substrate; forming first and second conductive vias through the substrate on opposite sides of the first semiconductor die; forming first intermediate conduction layers on a first surface of the substrate in electrical contact with the first and second conductive vias and contact pads of the first semiconductor die; forming second intermediate conduction layers on a second surface of the substrate opposite the first surface of the substrate in electrical contact with the first and second conductive vias; forming a first passivation layer over the first surface of the substrate; forming a second passivation layer over the second surface of the substrate; removing a portion of the first and second passivation layers outside a footprint of the first semiconductor die to form openings in the first and second passivation layers on opposite sides of the first semiconductor die which expose the first and second intermediate conduction layers; forming bonding pads within the openings of the first and second passivation layers to electrically contact the exposed first and second intermediate conduction layers, the bonding pads following a contour of the openings, wherein the bonding pads on opposing surfaces of the substrate are aligned; depositing a bump material within the openings in the first and second passivation layers; and reflowing the bump material to form bumps which extend into the openings of the first and second passivation layers.