Patent ID: 6927442

Claim:
A semiconductor device comprising: a single crystalline semiconductor substrate of a first conductivity type; a first epitaxial semiconductor layer of a second conductivity type grown on the single crystalline semiconductor substrate; a second epitaxial semiconductor layer of the second conductivity type stacked on the first epitaxial semiconductor layer; a well region of the first conductivity type formed in the second epitaxial semiconductor layer; a first buried layer of the first conductivity type abutting on a bottom of the well region of the first conductivity type; a second buried layer of the second conductivity type abutting on a bottom of the first buried layer of the first conductivity type and electrically isolating the well region of the first conductivity type from the single crystalline semiconductor substrate; an MOS transistor formed in the well region of the first conductivity type, wherein a drain layer of the MOS transistor and the well region of the first conductivity type are electrically connected; and a diffusion layer of the first conductivity type formed in the well region of the first conductivity type, wherein the diffusion layer and the drain layer of the MOS transistor are electrically connected.