Patent ID: 8330201

Claim:
A non-volatile semiconductor memory comprising: a semiconductor substrate having a source region, a drain region, and a channel region located between the source region and the drain region; and a gate multi-layer formed on the channel region and obtained by sequentially stacking the following: a first insulating layer that is formed on the channel region; a charge accumulation layer that is formed of an oxide dielectric film, at least one of titanium (Ti), zirconium (Zr) and hafnium (Hf) which is present as a base material in the oxide dielectric film is substituted by at least one of Tc, Re, Ru, Os, Rh, Ir, Pd, Pt, Co and Ni which is introduced as an additive substance; a second insulating layer; and a memory gate electrode, wherein an area density of the additive substance Tc, Re, Ru, Os, Rh, Ir, Pd, Pt, Co or Ni introduced into the oxide dielectric film falls within the range of 1×10 12 to 2×10 14 cm −2 and a thickness of the first insulating layer is 0.5 to 5 nm.