Patent ID: 7277308

Claim:
A write/search bit line decoder and driver circuit for a TCAM cell comprising: a data decoding circuit coupled to receive input signals from an I/O driver via a control circuit; and a write/search bit line driver and block associated with each read/write bit line and each complement read/write line of a TCAM cell coupled between the data decoding circuit and the associated read/write bit line and the complement read/write line; wherein each write/search bit line driver and block comprises: a first NOR gate having a first input, a second input and an output, wherein the first input of the first NOR gate coupled to receive a read enable signal from the control circuit and wherein the second input of the first NOR gate is coupled to receive a write/search bit line driver signal from the control circuit; a NAND gate having a first input, a second input and an output, wherein the first input of the NAND gate is coupled to receive the write/search bit line driver signal and wherein the second input of the NAND gate is coupled to receive a data input from data decoding circuit; a second NOR gate having a first input, a second input and an output, wherein the first input of the second NOR gate is coupled to receive the data input signal and wherein the second input of the second NOR gate is coupled to receive the read enable signal; a third NOR gate having a first input, a second input, and an output, wherein the first input of the third NOR gate is coupled to the output of the second NOR gate and the second input of third NOR gate is coupled to the output of the first NOR gate; an inverter having an input and an output, wherein the input of the inverter is coupled to the output of the NAND gate; a PMOS transistor having a first electrode to couple to a supply voltage (VDD), a second electrode coupled to the associated read/write bit line and the associated search bit line, and a control electrode coupled to the output of the third NOR gate; and a NMOS transistor having a first electrode to couple to the associated read/write bit line and the associated search bit line, a second electrode is coupled to a ground (GND), and a control electrode coupled to the output of the inverter.