Patent ID: 7612412

Claim:
A booster circuit, comprising: a first N-channel field-effect transistor, wherein a first pulse is inputted to a gate; a first P-channel field-effect transistor that is serially coupled to the first N-channel field-effect transistor, wherein the first pulse is inputted to a gate; a second N-channel field-effect transistor, wherein a gate is coupled to a drain of the first N-channel field-effect transistor; a second P-channel field-effect transistor that is serially coupled to the second N-channel field-effect transistor; a third N-channel field-effect transistor, wherein a second pulse, which has an opposite phase to the first pulse, is inputted to a gate and a source is coupled to a drain of the second N-channel field-effect transistor; a third P-channel field-effect transistor that is serially coupled to the third N-channel field-effect transistor, wherein a source is coupled to a source of the second N-channel field-effect transistor and the second pulse is inputted to a gate; a fourth N-channel field-effect transistor wherein a gate is coupled to a drain of the third N-channel field-effect transistor and a source is coupled to a source of the second N-channel field-effect transistor; a fourth P-channel field-effect transistor that is serially coupled to the fourth N-channel field-effect transistor, wherein: a gate is coupled to a drain of the third P-channel field-effect transistor, a source is coupled to the source of the third P-channel field-effect transistor, and a drain is coupled to a source of the first P-channel field-effect transistor; a first capacitor that is coupled to the drain of the second N-channel field-effect transistor, whereto the first pulse is inputted; a second capacitor that is coupled to a drain of the fourth N-channel field-effect transistor, whereto the second pulse is inputted; and a supporting substrate, on which the first to fourth N-channel field-effect transistors; the first to fourth P-channel field-effect transistors; and the first and second capacitors are provided, that supports the first to fourth N-channel field-effect transistors and the first to fourth P-channel field-effect transistors so that each of the first to fourth N-channel field-effect transistors and the first to fourth P-channel field-effect transistors becomes warpable in a channel direction.