Patent ID: 8586414

Claim:
A method of manufacturing semiconductor chip package comprising the following steps: providing a lead frame array comprising a first lead frame and a second lead frame each comprising a die pad, a first lead and a second lead disposed on one side the die pad, the first lead frame and the second lead frame being next one another forming mirror image of each other connecting to the lead frame array; disposing a first semiconductor chip having a first electrode and a second electrode on its top surface and a third electrode on its bottom surface on the first die pad with the bottom third electrode electrically attached to a top surface of the first die pad through a conductive adhesive; disposing a second semiconductor chip having a first electrode and a second electrode on its top surface and a third electrode on its bottom surface on the first die pad with the bottom third electrode electrically attached to a top surface of the second die pad through a conductive adhesive; providing a connection plate comprising a first metal plate and a second metal plate each having a bent extension at an end of the connection plate, the first metal plate and the second metal plate join together in a middle section of the connection plate as a mirror image of each other; attaching the first metal plate to the first electrode of the first chip with bent extension connecting the first lead of the first lead frame and attaching the second metal plate to the first electrode of the second chip with bent extension connecting the first lead of the second lead frame; applying a molding compound to encapsulate the first and second lead frames, the first and second chips, the first and second metal plates; sawing through the middle section of the connection plate, the lead frame array and the molding compound to obtain cingulated semiconductor package.