Patent ID: 7046575

Claim:
A bus connection circuit for a read operation of a multi-port memory device, comprising: a read data sensing/latching means for sensing/latching a read data applied on a local data bus in response to a read data strobe signal; and a read data driving means for driving a latched data in the read data sensing/latching means to a global data bus in response to a read data driving pulse, and for connecting or disconnecting a path of current flowing to the global data bus according to a logic level of the latched data, wherein the read data sensing/latching means includes: a differential-input flip-flop for sensing/latching the read data applied on the local data bus in response to the read data strobe signal; a transfer inverter configured to receive differential output signals of the differential-input flip-flop; and an inverter latch for latching an output of the transfer inverter.