Patent ID: 8910001

Claim:
A method for testing a memory under test comprising a plurality of memory cells, the method comprising: reading a set of GME-MBIST commands from a Command Memory, executing the set of GME-MBIST commands, which includes a test having a finite sequence of Generic March Elements (GME's), each GME being a march element comprising a finite sequence of operations applied to a memory cell in the memory under test before progressing to the next memory cell and specifying operations and generic data values of the march element, wherein the GME-MBIST commands are executed by operations on a Generic March Element Register (GMER) and a March Element Stress Register (MESR), the GMER specifying one of a set of Generic March Elements (GME's), and the MESR specifying the stress conditions to be applied, and performing the associated GME specified by the GMER and MESR to memory cells of the memory under test, the set of GME-MBIST commands defining a specific test comprises the commands: INIT, comprising an Opcode field, and fields for initializing the values of the parameters Addressing Order (AO), Data Value (DV), combination of Counting method and Address Direction (CM&AD), and Data Background (DB), which when executed sets the relevant fields in the MESR and clears the GMER to point at a first GME out of the set of GME's; SGME, comprising an Opcode field, fields for setting the value of the parameter Address Order (AO) and Data Value (DV), and a field for specifying an index (GME#) for a GME, which when executed sets the relevant fields in the MESR and the GMER, or a REP command, which comprises an Opcode, a field (RCNT#) specifying the number of times a Block of Commands (BoC) comprising one or more GME's which have to be repeated, and for each repeat, two plus two bit fields specifying the required Counting Method and Address Direction parameter (CM&AD) and Data Background parameter (DB).