Patent ID: 7225214

Claim:
A digital FIR filter of order N receiving an input signal with a predetermined sampling rate and outputting an output signal with said predetermined sampling rate, comprising: a combining unit having: a first buffer which receives the input signal and outputs each of the second half of the last N received input samples, whereby in case of odd N input samples the middle sample is doubled, of each input signal in the time inverted order of reception before a next input sample is supplied to the FIR filter, a second buffer which outputs each of the first half of the last N received input samples, whereby in case of odd N input samples the middle sample is doubled, of each input signal in the order of reception during the time in which the actual input sample is supplied to the FIR filter, and a first adder which receives and adds the same clock cycle output samples of the first and second buffer ( 2 , 3 ) which have to be subjected to equal filter coefficients, and outputs a combined output signal, a multiplier receiving the combined output signal and multiplying each sample thereof with a respective corresponding filter coefficient, and an integrator receiving the multiplied samples of the combined output signal, integrating them before the next input sample is supplied to the FIR filter, and providing the actual output sample at the end of said first time period, characterized in that said buffer includes: a first switch receiving the input signal at a first fixed terminal and providing the output samples of the first buffer at a variable terminal thereof, a first delay element connected to said variable terminal of said first switch and providing delayed input samples to the second buffer, and a second delay element connected to the output of the first delay element and providing further delayed input samples to a second fixed terminal of said first switch, and that said second buffer comprises: a second switch receiving the delayed input samples at a first fixed terminal, and a third delay element connected to a variable terminal of said second switch and providing the output samples of the second buffer which are additionally supplied to a second fixed terminal of said second switch, wherein said variable terminal of said first switch and said variable terminal of said second switch are connected to the respective first signal sample and are connected to the respective second fixed terminal during a third time period to calculate and output said combined output signal.