Patent ID: 7504303

Claim:
A method of forming a shielded gate field effect transistor, comprising: forming a hard mask over a silicon region, the hard mask comprising a protective layer; patterning the hard mask to define openings therein; etching the silicon region through the openings in the hard mask to thereby form trenches extending into the silicon region; forming a shield dielectric layer lining sidewalls and bottom of each of the trenches; forming a shield electrode in a bottom portion of each of the trenches, the shield electrode being insulated from the silicon region by the shield dielectric layer; forming protective spacers along upper sidewalls of each of the trenches; forming an inter-electrode dielectric over the shield electrode in each of the trenches, the protective spacers and the protective layer of the hard mask preventing formation of inter-electrode dielectric along the upper sidewalls of each of the trenches and over mesa surfaces adjacent each the trenches; and forming a gate electrode in each of the trenches and over the inter-electrode dielectric.