Patent ID: 8635431

Claim:
A vector gather buffer (VGB) for use in a processor, comprising: a plurality of multi-line load units (LUs), each including a plurality of buffer entry lines, each buffer entry line comprising a data field including a plurality of data items; at least one write port for loading data into the buffer entry lines from a memory unit, such that each buffer entry line receives consecutive data from the memory unit, and each buffer entry line of a multi-line load unit receives separately addressed data; at least one read port operative to read a plurality of data items from buffer entry lines of a single multi-line load unit and store said data items in an output vector register, such that the output vector register receives data items from a plurality of different buffer entry lines of the multi-line load unit; and control circuitry configured to: receive indication of a plurality of memory addresses to be fetched together, determine whether the content of the plurality of memory addresses are all currently stored in a single multi-line load unit in a manner retrievable through the at least one read port, load one or more buffer entry lines with the content of one or more of the plurality of addresses, from the memory unit, so that the content of all the memory addresses are stored in a single multi-line load unit in a manner retrievable through the at least one read port, if required according to the determination; and provide the content of the plurality of memory addresses through the at least one read port to the output vector register.