Patent ID: 7548104

Claim:
A delay cell, the delay cell comprising: a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal; a first transistor including a drain, a gate, and a source, wherein the drain of the first transistor is electrically connected to the drain of the current source, the gate of the first transistor receives an input clock signal that drives the delay cell, and the source of the first transistor is electrically connected to a power supply terminal; a second transistor including a drain, a gate, and a source, wherein the drain of the second transistor is electrically connected to the source of the current source, the gate of the second transistor receives the input clock signal, and the source of the second transistor is electrically connected to a ground terminal; a third transistor including a drain, a gate, and a source, wherein the gate of the third transistor is electrically connected to the drain of the current source, and the source of the third transistor is electrically connected to the power supply terminal; a fourth transistor including a drain, a gate, and a source, wherein the drain of the fourth transistor is electrically connected to the drain of the third transistor, the gate of the fourth transistor is coupled to an output of an another delay cell, and the source of the fourth transistor is electrically connected to the ground terminal; and a load capacitor having a first terminal and a second terminal, wherein the first terminal is electrically connected to the drain of the current source, and the second terminal is electrically connected to the ground terminal.