Patent ID: 7368346

Claim:
A method for forming a gate structure in a flash memory device, comprising: forming device isolation insulation layers passing through an insulation layer and a substrate; removing a predetermined portion of the insulation layer and the device isolation insulation layers after planarizing the device isolation insulation layers until the insulation layer is exposed; removing the insulation layer; isolating a gate oxide layer and a first conductive layer sequentially formed over the device isolation insulation layers; removing portions of the device isolation insulation layers to increase an effective area of the first conductive layer; forming a laminated layer over the gate oxide layer and the first conductive layer that are isolated; removing a predetermined portion of the laminated layer; forming a second conductive layer over a remaining portion of the laminated layer, filling a gap created by removing the predetermined portion of the laminated layer; and removing predetermined portions of the second conductive layer, thereby forming gate structures.