Patent ID: RE39578

Claim:
A pipelined incrementer , comprising: count registers for storing a current count of the pipelined incrementer, the count registers receiving sum bits that are stored as the current count in response to a clock input; pre-carry registers, receiving pre-carry signals that are stored as pipelined carry lookahead signals in response to the clock input; pre-carry logic, receiving at least some of the sum bits, for generating the pre-carry signals as a function of a next count indicated by the sum bits, the next count being after the current count in a pre-determined sequence; and sum logic, receiving the current count from the count registers, and receiving the pipelined carry lookahead signals from the pre-carry registers, for generating the sum bits that indicate the next count, whereby carry signals are generated from the sum bits that indicate the next count, stored in the pre-carry register, and used by the sum logic in a following clock cycle.