Patent ID: 8368212

Claim:
A semiconductor package, comprising: a semiconductor substrate having a plurality of transistors; an intermediate routing structure to provide electrical interconnects to the plurality of transistors, the intermediate routing structure including an outermost conductive layer; a passivation layer formed over the intermediate routing structure, the passivation layer having a plurality of openings positioned over a portion of the intermediate layer routing structure; an under-bump-metallization (UBM) stack including a conductive base layer formed over the passivation layer and electrically connected to the outermost conductive layer through the plurality of opening in the passivation layer, and a conductive layer formed on the base layer, wherein a portion of the UBM stack over the passivation layer electrically connects portions of the intermediate routing structure through different openings of the plurality of openings in the passivation layer; and a conductive bump positioned on and directly contacting a portion of the conductive layer of the UBM stack configured to carry current laterally between the different openings in the passivation layer.