Patent ID: 8264264

Claim:
A multiple phase pulse generator comprising n stages, where ‘n’ is greater than one, and each ith stage, for all ‘i’ such that 1≦i≦n, comprises: a first substage having a first memory element; and a second substage having a second memory element; wherein the first memory element of each jth stage, for all ‘j’ such that 1<j≦n is arranged to be set by the (j−1)th stage, the first substage of each ith stage being arranged to supply a stage output pulse while the first memory element is set and a clock pulse from a clock input is in a high state, wherein the second memory element of each ith stage is arranged to be set by the stage output pulse, and the second substage of each ith stage being arranged to hold the first memory element reset after the stage output pulse while the second memory element is set and from a timing at which the clock pulse is switched from the high state to a low state, and wherein the first substage of the ith stage has a set input that is connected to an output of an OR gate, which has an input that is connected to an output of the second substage of the (i−1)th stage and an output of the second substage of the (i+1)th stage.