Patent ID: 7159102

Claim:
A branch control memory for assisting in prefetching operations between an instruction cache, a branch target instruction buffer and a branch target address buffer used in a processor, the branch control memory comprising: a first buffer having a first field for identifying whether a target instruction within the branch target instruction buffer is valid; a second buffer having a second field for identifying whether a branch target address within the branch target address buffer can be used for preloading a branch target instruction; a third buffer having a third field for identifying whether said branch target address within said branch target address buffer is likely to be used by a branch instruction executed by the processor; wherein in response to an evaluation by the processor of whether a branch target instruction in said branch target instruction buffer is valid, whether said branch target address is likely to be used, and whether said branch target address can be used for preloading, the processor pre-loads one or more instructions from the instruction cache into the branch target instruction buffer, said one or more instructions having addresses associated with said branch target address.