Patent ID: 7356654

Claim:
A flexible multi-area memory comprising a storage area with a given capacity, the storage area comprising: a first area accessed only by a first processor; a second area accessed only by a second processor; a common area having two ports, shared by the first and the second processors, and simultaneously accessible via the two ports; a memory cell array comprising a plurality of memory cells corresponding to the capacity of the storage area; a first decoder selecting an address of one port of a memory cell assigned to the common area or an address of a memory cell assigned to the first area according to access from the first processor; and a second decoder selecting an address of the other port of the memory cell assigned to the common area or an address of a memory cell assigned to the second area according to access from the second processor, wherein each memory cell comprises a transfer gate ON/OFF controlled according to access from the first processor or the second processor and a capacitor charged when the transfer gate is ON to store information, and each memory cell is located in each crossing point between a plurality of word lines and a plurality of bit lines orthogonal to the word lines, the common area is configured by connecting in parallel capacitors of two memory cells connected to different word lines and bit lines, the first decoder controls ON/OFF of a transfer gate of the memory cell assigned to the first area or the common area, and the second decoder controls ON/OFF of a transfer gate of the memory cell assigned to the second area or the common area.