Patent ID: 7617467

Claim:
A processor-implemented method for verifying electrostatic discharge (ESD) device connectivity in an integrated circuit, the method comprising the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least the identified ESD devices in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the identified ESD devices; and performing by at least one processor a linear network analysis for each identified ESD test based at least in part on the file; wherein the step of performing the linear network analysis for each identified ESD test comprises the steps of: evaluating the identified ESD test under ESD conditions, wherein the identified ESD devices are removed from the evaluation; based at least in part on the evaluation, identifying one or more conductive connections included in the identified ESD test as prone to failure; and outputting one or more representations of the one or more conductive connections identified as prone to failure; wherein the one or more conductive connections are identified as prone to failure responsive to one or more of: the one or more conductive connections having current densities greater than a first prescribed threshold; and the one or more conductive connections having voltage drops greater than a second prescribed threshold; wherein the step of identifying ESD devices comprises using at least one ESD trigger layer included in the layout parameters to create at least one ESD device identification region in the integrated circuit; and wherein the step of extracting devices and parasitic elements in at least a portion of the integrated circuit comprises the steps of: performing a first device extraction in which a given ESD identification region is extracted to represent a source terminal of a given ESD device; and performing a second device extraction in which the given ESD identification region is extracted to represent a sink terminal of the given ESD device.