Patent ID: 7289543

Claim:
A method of controlling clock-data phase relationship in a high-speed data conversion circuit, comprising the steps of: receiving a data signal at the data conversion circuit; recovering a high-speed clock signal having a first clock rate from the data signal; receiving multiple-phase input clock signals having a second clock rate at an interpolator, wherein the interpolator functions in either a normal mode of operation or a testing mode of operation, wherein in the testing mode of operation the first clock rate and second clock rate differ; rotating with the interpolator the phase of the multiple-phase input clock signals to produce multiple-phase output clock signals at the second clock rate, wherein the multiple-phase output clock signals input into a slicer; sensing a phase difference between the data signal and the multiple-phase output clock signals at the slicer, wherein the phase difference generates a feedback signal used by the interpolator to adjust the multiple-phase output clock signals; and slicing the data signal with the multiple-phase output clock signal about midway between crossing points of the multiple-phase output clock signals to produce at least one output data signal.