Patent ID: 8134389

Claim:
A clock divider comprising: a divisor register configured to store a divisor by which an input clock signal is to be divided in the clock divider to produce an output clock signal, and wherein a least significant bit (LSB) of the divisor indicates whether the divisor is even or odd; a counter unit coupled to receive a counter value derived from the divisor at the beginning of a division phase, wherein the counter unit is configured to, during the division phase, decrement the counter value to a trigger value responsive to the input clock signal, wherein the trigger value is dependent on the LSB of the divisor; a detection unit, wherein the detection unit is configured to detect that the counter value is at the trigger value, wherein the detection unit is configured to assert a toggle signal and one of a first trigger signal and a second trigger signal responsive to detecting the trigger value, wherein the counter unit is configured to reload the divisor into the counter unit from the divisor register responsive to receiving either the first trigger signal or the second trigger signal, wherein the first trigger signal is asserted if the divisor is odd and the second trigger signal is asserted if the divisor is even; and an output unit, wherein the output unit is configured to toggle the output clock signal responsive to receiving the asserted toggle signal.