Patent ID: 8860116

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array provided in a semiconductor substrate; three or more first active areas which are provided in the memory cell array side-by-side in a first direction, each of the first active areas extending in a second direction intersecting with the first direction; a plurality of second active areas provided between the first active areas adjacent in the first direction, respectively and along the first direction; a memory cell unit which is provided in each of the three or more first active areas and which includes memory cells and select transistors, current paths of the memory cells and current paths of the select transistors being connected in series along the second direction; a linear contact which is connected to a source of the memory cell unit and which extends in the first direction and has a linear planer shape; a source line connected to the linear contact and extending in the first direction; and a dummy active area provided at the end of the memory cell array in the first direction, wherein an area in which the linear contact is provided is one semiconductor region to which the three or more first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar and contacts all of the first and second active areas in the one semiconductor region, the end of the linear contact in the first direction is located on the dummy active area in the first direction, and a width of the dummy active area in the first direction is larger than that of the first active area in the first direction.