Patent ID: 7573311

Claim:
A method of creating a delayed digital signal that differs from an input signal having a frequency by a programmable amount of delay, the method comprising the steps of: determining an actual phase difference between the input signal and an output signal delayed by the programmable amount; providing a delay adjust signal as a function of a difference between a commanded delay and the actual phase difference; generating a ramp signal having a ramp signal frequency and an amplitude bias, wherein the ramp signal frequency is based upon the frequency of the input signal and the amplitude bias is based upon the programmable amount of delay; comparing the ramp signal to a reference value to create a trigger signal based upon the whether the ramp signal is greater than or less than the reference value; applying the trigger signal as a clock to thereby create the delayed digital signal; and adjusting the amplitude bias of the ramp signal in response to the delay adjust signal to thereby change the amount of delay between the input signal and the delayed digital signal.