Patent ID: 7640391

Claim:
A random access memory integrated circuit, comprising: a dynamic memory bank configured to be periodically refreshed to maintain data; and a refresh control circuit comprising: a wraparound refresh request counter configured to increment in response to a received signal; a wraparound refresh address counter configured to hold a refresh address; a comparator coupled to the wraparound refresh request counter and to the wraparound refresh address counter, wherein the comparator is configured to compare the contents of the wraparound refresh request counter to the contents of the wraparound refresh address counter and to output a pending refresh signal if the wraparound refresh request counter and the wraparound refresh address counter differ in contents; and a refresh controller coupled to the comparator and to the dynamic memory bank, wherein the refresh controller is configured to receive the pending refresh signal and, in response, to issue a refresh command to the dynamic memory bank on a clock cycle when the dynamic memory bank is not busy with an access operation.