Patent ID: 8675403

Claim:
A memory array comprising: a plurality of gated diode memory cells formed in the memory array and connected by a plurality of word lines and a plurality of bitlines, each of the plurality of gated diode memory cells comprising: a first transistor; a gate diode, wherein the gate diode is a directional device comprising an implementing FET having a source terminal, a drain terminal and a gate terminal, the source terminal of the implementing FET being connected to the plurality of word lines and the drain terminal of the implementing FET being shorted to the source terminal of the implementing FET; and a second transistor, wherein the first transistor is in signal communication with the gate diode and the second transistor, and wherein a drain of the first transistor and a drain of the second transistor are connected to a common bitline of the bitlines, and wherein a source of the second transistor is connected to a ground line and a source of the first transistor is in signal communication with a gate terminal of the gate diode, and wherein gates of the first transistors of the gated diode memory cells are connected by the wordlines.