Patent ID: 8107305

Claim:
An apparatus comprising: a memory cell included in a device; a control line configured to receive a control signal to access the memory cell, the control signal having a first level during a first time interval and a second level during a second time interval of a memory operation of the device; a first line configured to transfer information to and from the memory cell; a second line included in the device; a first transistor including a first node coupled to the second line, a second node coupled to a node of the device, and a gate to receive a first signal; second transistor having a first node coupled to the first line, a second node coupled to the second line, and a gate to receive a second signal; and a module configured to reduce a difference between a value of a voltage on the second line and a value of a voltage on the node of the device during a first time portion of the second time interval, wherein the module is configured to cause the second signal to have a second level during the first time interval and a third level during the second time interval, and to cause the first signal to have a third level during the first time interval and the first time portion of the second time interval and a fourth level during a second time portion of second time interval.