Patent ID: 8576606

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including memory cells arranged therein, each of the memory cells being provided between a first line and a second line and including a variable resistor; a control circuit configured to apply through the first and second lines a voltage necessary for a forming operation of a memory cell; and a current limiting circuit configured to limit a value of a current flowing across the memory cell during the forming operation to a current limit value, wherein the control circuit is configured to repeat an operation of applying the voltage while setting the current limit value to a certain value and an operation of changing the current limit value when the current flowing across the memory cell during the forming operation has reached the current limit value, when the voltage for the forming operation has reached a voltage upper limit value, the control circuit executes an operation of stopping application of the voltage for the forming operation and changing the current limit value, and after stopping application of the voltage for the forming operation, the control circuit executes a reading operation in the memory cell, and when a resistance value of the memory cell is higher than a first value, executes an operation of changing the current limit value, whereas when the resistance value of the memory cell is equal to or lower than the first value, completes the forming operation.