Patent ID: 8258493

Claim:
A nonvolatile semiconductor memory apparatus comprising: a substrate; stripe-shaped lower-layer electrode wires provided on the substrate; an interlayer insulating layer which is disposed on the substrate including the lower-layer electrode wires and is provided with contact holes at locations respectively opposite to the lower-layer electrode wires; resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers such that the non-ohmic devices are respectively connected to the resistance variable layers; wherein the non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer; and wherein one layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.