Patent ID: 8189383

Claim:
A multi-level cell programming method of a non-volatile memory device, the method comprising: providing a page buffer including a first register connected to a first memory cell block group and a second register connected to a second memory cell block group, wherein the first register and the second register are disposed between the first memory cell block group and the second memory cell block group; performing a least significant bit (LSB) program of each memory cell included in the first memory cell block group through the first register and performing the LSB program of each memory cell included in the second memory cell block group through the second register; setting most significant bit (MSB) data in each of a first node of a data latch unit of the first register and the second register; performing an MSB program to the memory cell included in the first memory cell block group through the first register and performing the MSB program to the memory cell included in the second memory cell block group through the second register; setting a first data in the first node, when a threshold voltage of the memory cell is higher than a first verify voltage, wherein the first data is set at a first voltage level; setting a second data in the first node, when a threshold voltage of the memory cell is higher than a second verify voltage, wherein the second data is set at a second voltage level, the second voltage level being opposite to the first voltage level; setting the first data in the first node, when a threshold voltage of the memory cell is higher than a third verify voltage; and repeating the MSB program through the first and the second register according to the data set in the first node.