Patent ID: 8138800

Claim:
A phase detecting circuit comprising: a latch circuit configured to switch, based on an OR signal and a NAND signal of two clock signals wherein the two clock signals are subjected to phase comparison, an output of the latch circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states, wherein the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises: first and second inverters configured to respectively logically invert and output the two clock signals corresponding thereto; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the two clock finals to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the two clock signals corresponding thereto.