Patent ID: 8095691

Claim:
A system, comprising: a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes; and node management code executed by at least one processor card in each of the first and second nodes to perform operations, the operations comprising: detecting a failure of one processor card in one of the first or second node; determining whether the node including the failed processor card includes at least one operational processor card; reconfiguring the first or second node including the failed processor card to operate without the failed processor card in response to the determining that the node includes at least one operational processor card; and performing a failover to use the first or second node that does not include the failed processor card in response to the determining that the node does not include at least one operational processor card.