Patent ID: 7372128

Claim:
An integrated circuit anti-interference outline structure surrounding a periphery of a partial circuit in the integrated circuit, comprising a Vcc metal strip connected to a Vcc positive voltage and a GND metal strip connected to a GND ground, wherein both the metal strips being connected to partial elements of a CMOS structure are made up by PNP structures, and the PNP structures further comprising: a deep N-well layer formed on a P-substrate, an N-well layer formed on the deep N-well layer, a P+ layer, an N− layer and poly layers disposed at the N-well layer, contact holes disposed at the N− layer for forming a positive voltage zone by connecting to a metal layer (metal 1 ) and the deep N-well layer, respectively, contact holes disposed at the P+ layer for connecting to the metal layer (metal 1 ) that is further connected to the Vcc metal strip through contact holes, and to the other Vcc metal strip (metal 2 ) through contact holes at the N− layer in order to form a source and a drain; and a GND metal layer (metal 1 ) connected to poly layers below through contact holes for forming a gate.