Patent ID: 8247861

Claim:
A semiconductor device comprising: an active region disposed in a semiconductor body; a source region, a channel region and a drain region disposed in the active region, the source region being spaced from the drain region by the channel region, the source, the channel, and the drain regions being formed along a first plane of the semiconductor body; a floating gate electrode overlying the channel region and separated therefrom by a dielectric layer; an inter-level dielectric layer surrounding the floating gate electrode; a first metal layer overlying the active region, the first metal layer including a first metal feature electrically coupled to the floating gate electrode and a second metal feature coupled to a control gate node, wherein the second metal feature is isolated from the floating gate electrode by the inter-level dielectric layer; and a second metal layer overlying the first metal layer, the second metal layer including a third metal feature electrically coupled to the first metal feature and a fourth metal feature electrically coupled to the second metal feature, whereby the floating gate electrode, the first metal feature, and the third metal feature form at least a portion of a floating gate and the second metal feature and the fourth metal feature form at least a portion of a control gate of a non-volatile memory cell, wherein regions of the control gate disposed in the first metal layer surround regions of the floating gate disposed in the first metal layer from all directions when viewed from a second plane, wherein the second plane is parallel to the first plane, wherein along the second plane, at any point on an outer surface of the regions of the floating gate in the first metal layer, a closest distance between an inner surface of the regions of the control gate in the first metal layer to the outer surface of the regions of the floating gate in the first metal layer is substantially equal to the closest distance from any other point on the outer surface of the regions of the floating gate in the first metal layer to the inner surface of the regions of the control gate in the first metal layer, and wherein the closest distance is measured along a line perpendicular to the outer surface of the regions of the floating gate in the first metal layer.