Patent ID: 7553738

Claim:
A method of fabricating a microelectronic device comprising: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure including: an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer, where in said patterning comprises: patterning the top electrode layer to form a top electrode opening that exposes a portion of the capacitor dielectric layer; and patterning the capacitor dielectric layer to form a capacitor dielectric opening in registration with the top electrode opening that exposes a portion of the bottom electrode layer; and over-etching the bottom electrode layer comprises wet etching the bottom electrode layer through the top electrode opening and the capacitor dielectric opening to define an opening in the bottom electrode layer that is wider than the capacitor dielectric opening; after patterning the top electrode layer and the capacitor dielectric layer; providing a patterned resist layer onto the top electrode layer such that the resist covers side walls of the top electrode opening and the capacitor dielectric opening and further defines a resist opening exposing a portion of the bottom electrode layer, the resist opening being in registration with the top electrode opening and the capacitor dielectric opening; wet etching the bottom electrode layer through the resist opening to define a bottom electrode opening in the bottom electrode layer wider than the capacitor dielectric opening; and removing the patterned resist layer after wet etching.