Patent ID: 7767532

Claim:
A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor, the method comprising the steps of: (a) providing a semiconductor substrate covered with a stack of first and second layers, the first layer being insulating; (b) forming at least one first opening in the second layer; (c) forming, in the first layer, a second opening continuing the first opening; (d) enlarging the first opening by isotropic etching; (e) forming a first doped region in the substrate by implantation through the first enlarged opening, the first doped region taking part in the forming of the transistor drain or source; (f) forming, in the second opening, a thinned-down insulating portion thinner than the first layer; and (g) forming a gate of the MOS transistor at least partially extending over the thinned-down insulating portion.