Patent ID: 8451034

Claim:
A test apparatus comprising: an oscillator configured to generate a first clock; and a clock hand-off circuit configured to receive input data that is in synchronization with the first clock, and to hand off the input data to the second clock; wherein the clock hand-off circuit comprises: a first latch configured to latch input data using a first clock; a frequency dividing circuit configured to divide a frequency of a second clock to generate a third clock, the frequency of the second clock being N times that of the first clock, where N represents an integer; a second latch configured to latch output data of the first latch using the third clock; a third latch configured to latch output data of the second latch using the second clock; and a frequency multiplying circuit configured to generate the second clock by multiplying the frequency of the first clock by N; wherein the phase of the third clock obtained by dividing the frequency of the second clock can be adjusted in increments of the period of the second clock.