Patent ID: 8041880

Claim:
An apparatus comprising: a memory including a data area and an additional data area; and a memory controller configured to access said data area and said additional data area respectively, wherein said data area stores a first k-bit data (k is a natural number) and a second k-bit data, wherein said additional data area stores a first additional m-bit data (m is a natural number) and a second additional m-bit data, wherein at least a part of an address of said first additional data is the same as an address of said first data corresponding to said first additional data, and at least a part of an address of said second additional data is the same as an address of said second data corresponding to said second additional data, wherein said first data, said second data, said first additional data, and said second additional data are included in a data group, wherein said second data in said data group is an identification number (ID) for identifying said first data, wherein said second additional data indicates that said second data corresponding to said second additional data is said ID, wherein said first additional data indicates that said first data corresponding to said first additional data is not said ID, and wherein the memory controller accesses said additional data area based on a first address, to read said second additional data, and accesses said data area based on a second address which is same as at least a part of said first address, to read said ID corresponding to said read second additional data.