Patent ID: 7790619

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate; selectively etching the insulation layer for the gate hard mask and the conductive layer for the gate electrode to expose a first region of the substrate, thereby forming an initial gate line; forming a first insulation layer over a resultant structure where the initial gate line is formed; performing a planarization process until the insulation layer for the gate hard mask is exposed; forming a photoresist pattern after performing the planarization process; and selectively etching the insulation layer for the gate hard mask and the conductive layer for the gate electrode by using the photoresist pattern to expose a second region of the substrate, the second region being not overlapped with the first region, thereby forming a final gate line having a line width smaller than the initial gate line.