Patent ID: 7843243

Claim:
A flip-flop circuit comprising: a precharge transistor configured to precharge an internal node to a first power supply voltage in response to a clock signal; a first pull-down unit configured to pull down a voltage of the internal node to a second power supply voltage, the second power supply voltage being lower than the first power supply voltage; a pull-up transistor configured to pull up a voltage of an output node to the first power supply voltage in response to the voltage of the internal node; and a second pull-down unit configured to pull down the voltage of the output node to the second power supply voltage, wherein the first pull-down unit includes: a first pull-down transistor configured to pull down the voltage of the internal node in response to an input data signal; and a second pull-down transistor configured to pull down the voltage being pulled down by the first pull-down transistor to the second power supply voltage in response to a first pulse signal, and to not pull down the voltage being pulled down by the first pull-down transistor in response to the output signal.