Patent ID: 7673188

Claim:
A system for testing a processor, the system comprising: a gold processor; a test access port (TAP) coupled to the gold processor and a device under test (DUT), wherein the DUT is a processor; an interface control unit coupled to the TAP; a switch coupled between the TAP and each of the gold processor and the DUT, wherein the switch is controllable by the interface control unit, wherein the interface control unit is configured to cause the TAP to: in a first mode, simultaneously provide a plurality of test signals to both the gold processor and the DUT such that, during testing, the gold processor and the DUT operate in synchronous functional lockstep with respect to each other; in a second mode, provide the plurality of test signals exclusively to the gold processor; and in a third mode, to provide the plurality of test signals exclusively to the DUT; and a host computer coupled to the interface control unit, wherein the host computer is configured to execute a software application in order to cause the TAP, via the interface control unit, to drive the plurality of test signals in accordance with one of the first, second, or third modes, and to access test output data from the gold processor and the DUT independently of one another.