Patent ID: 7929328

Claim:
A storage device, comprising: a memory comprising: a plurality of word lines sequentially disposed in parallel; a first bit line, a second bit line, and a third bit line sequentially disposed in parallel and vertical with the word lines; and a plurality of cells, each corresponding to one word line and one bit line, wherein the word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line; and a read circuit coupled to the memory for reading the data stored in the memory, wherein each cell comprises a transistor, and wherein a first cell among the cells corresponds to the first bit line and comprises a first transistor, which comprises a control terminal coupled to a corresponding word line, a first electrode receiving a grounding level, and a second electrode wherein when the second electrode is electrically un-connected to the first bit line, it indicates that the first cell stores 1.