Patent ID: 6925624

Claim:
A circuit modification method of modifying a circuit by inserting one or more buffers into a predetermined wire located within the circuit, the method comprising the steps of: determining whether a glitch error is caused in said predetermined wire by one or more aggressors each comprised of one or more other wires; when determining that a glitch error as caused in said predetermined wire by one or more aggressors, determining one or more positions where one or more buffers are to be inserted into said predetermined wire based on a coupling capacity between each of said one or more aggressors and said predetermined wire, wherein said insertion position determining step includes the steps of, when determining that a glitch error is caused in said predetermined wire by only one aggressor, calculating a target coupling capacity using the coupling capacity between said aggressor and said predetermined wire, and, when dividing said predetermined wire into a plurality of wire segments, determining one or more internal points of division of said predetermined wire so that a coupling capacity between each of said plurality of wire segments and said aggressor does not exceed said target coupling capacity, and setting said one or more internal points of division to said one or more positions where said one or more buffers are to be inserted into said predetermined wire.