Patent ID: 8163606

Claim:
A method of manufacturing a liquid crystal display device comprising: preparing a substrate defined into a P-channel thin film transistor formation region and an N-channel thin film transistor formation region; forming first and second active patterns on the P-channel and N-channel thin film transistor formation regions of the substrate using a first masking process, respectively; forming a first insulation film and a first conductive film on the substrate provided with the first and second active patterns; forming a first gate electrode, which is consisted of the first conductive film, on the P-channel thin film transistor formation region of the substrate using a second masking process; forming a P drain region, a P source region, and a P channel region between the P drain and source regions on the first active pattern using the first gate electrode; forming a second gate electrode, which is consisted of the first conductive film, on the N-channel thin film transistor formation region of the substrate using a third masking process; forming an N drain region, an N source region, and an N channel region between the N drain and source regions on the second active pattern using the second gate electrode; forming a second insulation film on the substrate with the N drain, source, and channel regions; selectively removing the first and second insulation films using a fourth masking process to form first contact holes partially exposing the respective N and P source regions and second contact holes partially exposing the respective N and P drain regions; forming a second conductive film on the substrate provided with the first and second contact holes; forming N and P source electrodes, which are electrically connected to the N and P source regions through the first contact holes, and N and P drain electrodes which are electrically connected to the N and P drain regions through the second contact holes, using a fifth masking process; forming a third insulation film and a third conductive film on the substrate provided with the N and P drain electrodes; forming third contact holes, which pass through the third insulation film, and a common electrode on the third insulation using a sixth masking process; forming a fourth insulation film on the substrate provided with the third contact holes and the common electrode; forming fourth contact holes, which pass through the fourth insulation film and expose the respective N and P drain electrodes, using a seventh masking process; forming a fourth conductive film on the substrate with the fourth contact holes; and forming a pixel electrode, which is electrically connected to the N and P drain electrodes through the fourth contact holes, using a eighth masking process.