Patent ID: 6983354

Claim:
A system for coupling memory device signals from an electronic system to a memory device, comprising: a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals; a sequencer load unit coupled to receive the memory device signals from the electronic system, the sequencer load unit coupled to the sequence state matrix to load the memory device signals into the sequence state matrix at locations in the matrix corresponding to the times that the memory device signals will be coupled to the memory device, the sequencer load unit loading the memory device signals into the sequence state matrix at a rate corresponding to a frequency of a system clock signal controlling the operation of the electronic system; a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix at respective times corresponding to the locations into which the memory device signals were loaded, the FIFO buffer receiving the memory device signals from the matrix at a rate corresponding to the frequency of the system clock signal; and a command selector coupled to the FIFO buffer to receive the memory device signals from the FIFO buffer and transfer the memory device signals to the memory device, the command selector transferring the memory device signals to the memory device at a rate corresponding to the frequency of a memory clock signal controlling the operation of the memory device.