Patent ID: 8724496

Claim:
A switch having integrated line-rate application recognition in a switch ASIC, comprising: a flow tracker session table, said flow tracker session table having a plurality of entries, each of said plurality of entries being associated with a distinct flow of packets, wherein a flow of packets is distinguished based on at least common source and destination addressees that are shared by a plurality of packets; a flow tracker that reviews packets that enter the switch at an ingress pipeline, said flow tracker creating an entry in said flow tracker session table on identification of a new flow of packets to be tracked, said flow tracker reviewing a packet associated with said identified flow and generating flow information to be forwarded with said reviewed packet to a memory management unit in the switch, said flow information including a flow index that identifies a particular flow of packets to which said reviewed packet is associated; and a signature matching engine that receives said reviewed packet and said flow information from said memory management unit in the switch, said signature matching engine examining said reviewed packet using expression matching state machines that search for known signatures, wherein results from said expression matching state machines are included by said signature matching engine in a response packet that is sent by said signature matching engine to said ingress pipeline, wherein said flow tracker uses said flow index contained in said response packet received at said ingress pipeline to update said entry in said flow tracker session table to indicate that a policy is to be applied to subsequent packets reviewed by said flow tracker that are associated with a flow of packets associated with said entry in said flow tracker session table.