Patent ID: 8797800

Claim:
A non-volatile memory device, comprising: a substrate; a plurality of memory cells formed above the substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory; alternating dielectric layers and conductive layers in a stack, the plurality of memory cells are in communication with the conductive layers, and a columnar active area of the plurality of memory cells is formed in the stack; a source-end select gate transistor at a source end of the plurality of memory cells; one or more drain-end select gate transistors at a drain end of the plurality of memory cells, the one or more drain-end select gate transistors comprise a first control gate material which has a relatively higher work function and a second control gate material which has a relatively lower work function, and the first control gate material is before the second control gate material relative to the drain end; and circuitry in communication with the plurality of memory cells.