Patent ID: 8136097

Claim:
A thread debugging device, comprising a processor for debugging at least one thread among a plurality of threads which are executed in association with each other on a computer and adapted to sequentially execute respective predetermined command sequences of threads, said thread debugging device having a stored algorithm that includes instructions for performing thread debugging features comprising: causing the computer to execute at least some processing of at least one target thread to be debugged among the plurality of threads; causing the computer to execute non-target threads, which are threads other than the at least one target thread among the plurality of threads, during execution of the at least one target thread while restricting advance of processing of the command sequences of the non-target threads; and when debugging a target thread, embedding a command in each non-target thread to execute processing to jump to itself, wherein the advance of processing of the command sequences of the non-target threads is restricted by causing the non-target threads to execute the embedded command, wherein the plurality of threads are respectively allocated to a plurality of processors within the computer and executed, and these threads map hardware resources in the processors to which the respective threads are allocated to an address space referred to by each thread such that the hardware resources can be referred to by each thread.