Patent ID: 8549216

Claim:
A method for increasing the speed of writing data to a destination memory bank employing a content addressable memory addresses scheme comprising: segmenting said data into a plurality of portions for use as payloads for a plurality of fragments; adding overhead information to said payloads to form the plurality of fragments, said overhead information including a common destination address for said plurality of fragments; sending each of said plurality of fragments to at least one of the plurality of memory banks; evaluating, at each one of said plurality of memory banks, said overhead information associated with each one of said plurality of fragments received to determine said destination memory bank; forwarding each one of said plurality of fragments which arrive at memory banks other than said destination memory bank to said destination memory bank; reassembling, at said destination memory bank, the payloads of said plurality of fragments into said data; and storing said data in said destination memory bank; wherein said content addressable memory address scheme defines said destination address of said plurality of fragments based on a content addressable memory address uniquely identifying said data.