Patent ID: 7812415

Claim:
An apparatus comprising: a gate insulating layer formed over a semiconductor substrate, the gate insulating layer partially exposing an uppermost surface of the semiconductor substrate; a gate insulating layer pattern formed over a part of the exposed uppermost surface of the semiconductor substrate along the same horizontal plane as the gate insulating layer; an isolation insulating layer formed over the gate insulating layer; a plurality of first gate conductive patterns formed over the gate insulating layer and the gate insulating layer pattern; a source/drain formed over a part of the uppermost surface of the semiconductor substrate that is exposed between the gate insulating layer and the gate insulating layer pattern; a second gate conductive pattern formed over one of the plurality of the first gate conductive patterns that is provided over the gate insulating layer pattern; a plurality of salicide layers formed over the second gate conductive pattern, the source/drain and at least one of the plurality of first gate conductive patterns that are provided over the gate insulating layer; and a pair of spacers formed over the gate insulating layer pattern and on sidewalls of one of the plurality of first gate conductive patterns that is provided over the gate insulating layer pattern, the second gate conductive pattern, and the plurality of salicide layers, wherein one of the plurality of salicide layers is formed between the isolation insulating layer and one of the pair of spacers, wherein said one of the plurality of salicide layers is in direct contact with the source/drain, the isolation insulating layer, and said one of the pair of spacers, wherein an uppermost surface of the isolation insulating layer is formed along the same horizontal plane as an uppermost surface of said one of the plurality of salicide layers, and wherein an uppermost surface of one of the first gate conductive patterns that is provided over the gate insulating layer pattern is formed along the same horizontal plane as the uppermost surface of the isolation insulating layer.