Patent ID: 7453112

Claim:
An integrated circuit memory cell comprising: a single material forming a combined first capacitor electrode and first transistor source/drain and lacking a material-to-material interface between the first electrode and first source/drain; a second capacitor electrode; a capacitor dielectric between the first and second electrodes; a vertical transistor above and including the first source/drain, the vertical transistor also including a transistor channel above the first source/drain and a gate conductor around the channel; and another single material forming a combined digit line inner conductor and second transistor source/drain directly above the channel and lacking a material-to-material interface between the digit line inner conductor and second source/drain, the digit line inner conductor connecting a digit line to the channel and cell size being 1.5F×1.5F, where F is feature size of the capacitor dielectric and the first capacitor electrode considered in combination.