Patent ID: 7185324

Claim:
A compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an address of a data item stored in a memory area, comprising: an allocation data selecting unit operable to sequentially select a data item from a group X composed of a plurality of data items each having a plurality of data attributes, the selection being made based on a descending order of an alignment of each data item, the alignment being a value representing a strength of a constraint on an allocatable location of a corresponding data item in a memory area; an allocation judging unit operable to judge, each time a data item is selected, whether the selected data item is allocatable within a predetermined address range from the starting address of the memory area, which corresponds to the address range being accessible with a single instruction; and an exclusion data specifying unit operable to specify, when the judgment is negative, a data item to be excluded from the group X out of all data items having been selected, the specification being made based on a descending order of a size of each data item, wherein the allocation data selecting unit repeats the selection from data items that remain in the group X after excluding all data items having been specified to be excluded, until all the remaining data items are judged to be allocatable to the memory area.