Patent ID: 7301838

Claim:
An integrated circuit device comprising: a bit line having a plurality of memory cells coupled thereto wherein each memory cell includes an electrically floating body transistor including: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region; and wherein each memory cell includes: a first data state representative of a first charge in the body region of the transistor; and a second data state representative of a second charge in the body region of the transistor; a cross-coupled sense amplifier including first and second input nodes, each input node having an intrinsic capacitance, wherein the cross-coupled sense amplifier includes: a first transistor having first and second regions and a gate, wherein the first region is connected to or forms a part of the first input node, and wherein the first input node is coupled to the bit line to receive a current which is representative of a data state of a selected memory cell, wherein the selected memory cell is one of the plurality of memory cells which are coupled to the bit line; and a second transistor having first and second regions and a gate, wherein the first region of the second transistor is connected to or forms a part of the second input node, and wherein the second input node receives a reference current; and reference current generation circuitry, coupled to the second input node of the sense amplifier, to generate a current that is representative of the reference current; write back circuitry, coupled to the first and second input nodes of the cross-coupled sense amplifier, to restore the data state of the selected memory cell or write a different data state into the selected memory cell; and wherein, in operation, the cross-coupled sense amplifier determines the data state of the selected memory cell based on voltages developed on the first and second input nodes.