Patent ID: 7107502

Claim:
A method of identifying one or more defective shift register latches in a scan chain, the method comprising: electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input; placing the scan chain circuit into an operating region; loading a scan test pattern into the scan chain circuit; placing the scan chain circuit into a failing region; applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the failing region; placing the scan chain circuit into an operating region; unloading the scan chain circuit; and identifying at least one defective shift register latch in the scan chain circuit.