Patent ID: 8299455

Claim:
A semiconductor structure having reduced contact resistance comprising: at least one field effect transistor located upon and within a surface of a semiconductor substrate, said at least one field effect transistor including source and drain diffusion regions located within said semiconductor substrate at a footprint of a patterned gate conductor, said source and drain diffusion regions each have an ordered, nanosized pattern located therein, said ordered, nanosized pattern comprising a plurality of openings located within said source and drain diffusion regions, wherein each of said plurality of openings has vertical sidewalls portions that are in contact with a planar bottommost surface portion, and each of said plurality of openings having a width from one vertical sidewall to an opposing vertical sidewall of less than 50 nm; and a conductive material located upon said source and drain diffusion regions including said ordered, nanosized pattern, wherein said conductive material is only partially present in each of said vertical sidewall portions and said planar bottommost surface portion of each of said openings.