Patent ID: 7774519

Claim:
An apparatus comprising a channel subsystem coupled to a central processing complex and a plurality of communication channels, the central processing complex comprising an I/O processor and a host system memory area located therewith, the apparatus comprising: at least one input queue and at least one output queue each for holding data sent by one of the central processing complex and communication channel destined for the other one of the central processing complex and communication channel, the at least one input queue and the at least one output queue maintained in the host system memory area, the at least one input queue comprising a plurality of slots for holding data from the communication channel destined for the I/O processor, the plurality of slots being configured in FIFO order for processing by the I/O processor, at least one of the slots includes a lock to be set by the communication channel to indicate whether data is present for processing by the I/O processor, the at least one input queue having a queue header for indicating which slots are to be processed and unlocked by the I/O processor; the I/O processor configured to write to the at least one output queue at the same time that the communication channel writes to the at least one input queue, and the I/O processor is configured to read from the at least one input queue at the same time that the communication channel reads from the at least one output queue; and the communication channel configured to determine which of the slots that the communication channel can write or if the at least one input queue is full, and alert the I/O processor whether the at least one input queue has data to be processed by the I/O processor.