Patent ID: 8039968

Claim:
A semiconductor integrated circuit device, comprising: a substrate; three or more wiring layers on the substrate; a dummy via between adjacent first and second wiring layers of the three or more wiring layers; a dummy wire formed in the second wiring layer and connected to the dummy via; and one or more stacked via structures formed in the three or more wiring layers, each of the one or more stacked via structures including an intermediate wire in the second wiring layer, a first via between the first wiring layer and the second wiring layer, and a second via between the second wiring layer and a third wiring layer, the first via and the second via being connected to the intermediate wire, the first via and the second via at least partially overlapping with one another in plan view, wherein a protrusion amount of the dummy wire is smaller than a protrusion amount of the intermediate wire in any of the stacked via structures.