Patent ID: 8645886

Claim:
A method for verifying power management in an electronic circuit design using an external design verification apparatus, wherein the electronic circuit design includes a first voltage regulator for regulating a supply voltage, a second voltage regulator for regulating the supply voltage when the supply voltage drops below a first predetermined low threshold, and a plurality of modules that are clocked using a clock having a clock frequency, and wherein the electronic circuit design is operable in at least a low power mode and a high power mode, the method comprising: generating, using the design verification apparatus, an estimated a current load requirement of the plurality of clocked modules based on the clock frequency and a predefined current load model, wherein the predefined current load model ensures that a reset is caused only due to a failure in response time of both the first and second voltage regulators during a transition of the electronic circuit from low power mode to high power mode or high power mode to low power mode; testing, using the design verification apparatus, the electronic circuit design with the external design verification apparatus using the estimated current load requirement by executing predetermined test patterns and during said testing, monitoring the supply voltage of the electronic circuit design, wherein the supply voltage is regulated with the first voltage regulator; verifying, using the design verification apparatus, that the supply voltage regulation performed by the first voltage regulator, which is based on the estimated current load requirement, does not deviate from a predetermined operating voltage of the electronic circuit design; and changing the electronic circuit design if the verifying step determines that the supply voltage regulation deviates from the predetermined operating voltage.