Patent ID: 8140801

Claim:
A method in a processor for semi-synchronously copying data from a first portion of a single volatile memory to a second portion of the single volatile memory, the method comprising: receiving, in a processor, a call for a semi-synchronous memory copy operation comprising operational code and a set of operands, wherein the set of operands comprises at least a first operand identifying a virtual source address corresponding to a source location in a section of a single volatile memory, a second operand identifying a virtual target address corresponding to a target location in the section of the single memory volatile, and a third operand that identifies a number of bytes to be copied, wherein the semi-synchronous memory copy operation preserves temporal persistence of validity for the virtual source address and the virtual target address by setting a flag bit, wherein preserving temporal persistence of validity includes preventing a load operation to the source location corresponding to the virtual source address, preventing a load operation and a store operation to the target location corresponding to the virtual target address, and while allowing a load operation to other locations outside of the virtual target address, and a store operation to other locations outside of the virtual source address and the virtual target address, during the semi-synchronous memory copy operation, wherein the semi-synchronous memory copy operation operates semi-synchronously with the processor to provide maximum processor utilization such that the processor is able to execute at least one additional instruction on another section of the single volatile memory during the semi-synchronous memory copy operation; placing in a queue the memory copy operation for execution by a memory controller, wherein the queue is coupled to the memory controller; and continuing to execute at least one subsequent instruction during the semi-synchronous memory copy operation as the subsequent instruction becomes available from an instruction pipeline.