Patent ID: 7355231

Claim:
Memory circuitry comprising: a semiconductor substrate; an insulative layer received over the substrate, the insulative layer comprising at least a single well formed therein, the insulative layer within which said well is formed peripherally defining an outline of a memory array area, area peripheral to the well comprising memory peripheral circuitry area, the well having a base of said insulative layer, the insulative layer having an outermost surface laterally external of the well, an oxygen diffusion barrier layer received directly over the insulative layer base of the well, the oxygen diffusion barrier layer extending from over the insulative layer base of the well to over said outermost surface laterally external of the well; a plurality of memory cell storage capacitors received within said single well, the memory cell storage capacitors respectively comprising a storage node which is received within the insulative layer through the oxygen diffusion barrier layer and through the insulative layer base of the well, the memory cell storage capacitors comprising a capacitor dielectric layer, the capacitor dielectric layer extending to be received over a portion of the oxygen diffusion barrier layer which is received over said outermost surface laterally external of the well, the memory cell storage capacitors comprising a capacitor cell electrode that is common to the memory cell storage capacitors, the capacitor cell electrode having a lateral outermost extent over said outermost surface, the oxygen diffusion barrier layer extending laterally outward over said outermost surface laterally beyond said lateral outermost extent of the capacitor cell electrode; and peripheral circuitry within the peripheral circuitry area operatively configured to write to and read from the memory array.