Patent ID: 8181035

Claim:
A computing device comprising: a main memory storing at least a part of a first computer program comprising data blocks having a length in bytes, the data blocks comprising first data comprising information fields, second data comprising executable instructions and third data usable to verify at least the second data, the information fields of the first data comprising a first information field identifying the format of the data block, a second information field identifying a first cryptographic key and a third information field identifying a first cryptographic algorithm usable to verify at least the second data using the first cryptographic key and the third data; and a processor comprising a first core having a L1 instruction cache memory comprising cache lines with a length in bytes that is the same length in bytes as the data blocks of the first computer program, the L1 cache memory adapted to store a data block of the first computer program in a cache line, the first core comprising a security component adapted to read the information of the data block stored in the cache line and to access inside the processor the first cryptographic key identified in the second information field of the data block and use the first cryptographic key and the third data in the execution of the first cryptographic algorithm to verify at least the second data, the first core adapted to execute the executable instructions of the data block stored in the cache line only upon the security component verifying at least the second data of the data block, the first cryptographic key is a public key associated with a private key and the first cryptographic algorithm is an asymmetric cryptographic algorithm, the security component adapted to verify the second data using the public key and the asymmetric cryptographic algorithm, the private key being stored inside the processor.