Patent ID: 6883104

Claim:
A process for automatically reducing the power usage of a microprocessor comprising the steps of: continuously generating monitor interrupt signals for monitoring the operations of the microprocessor at predetermined intervals of time, searching within an instruction stream of the microprocessor for a plurality of instructions executed by the microprocessor upon the occurrence each of said monitor interrupt signals by means of a monitoring circuit; comparing said plurality of searched instructions with a predefined list of instructions stored in memory comprising wired connections to determine when at least one of said searched instructions constitutes a predefined instruction, supplying at least a first operation frequency to said microprocessor upon the occurrence of said predefined instruction, and a reduced second operation frequency to said microprocessor upon the non-occurrence of said predefined instruction, wherein the power usage of said microprocessor is reduced according to the occurrence or non-occurrence of said predefined instruction by reduction of the operation frequency supplied to said microprocessor, said searching step including searching for defined interrupts, and said supplying step including supplying the first operating frequency to the microprocessor in response to a defined interrupt and a reduced second operation frequency to said microprocessor upon the non-occurrence of said defined interrupt.