Patent ID: 8022393

Claim:
A method, comprising: disposing a mask on a semiconductor upper layer of a multi-layer substrate, the semiconductor upper layer being adjacent to an insulator lower layer, and removing areas of the upper layer not covered by the mask in a first lithography, wherein the mask comprises a first and a second conductive pads separated by a distance, and a nanowire in contact with the first and the second conductive pads across the distance, wherein the nanowire comprises a shell made of an insulating material and a core made of a conductive or a semiconductive material, said nanowire being in contact with the first and the second conductive pads across the distance and extending beyond one of the conductive pads as an extended section, and wherein the method further comprises: removing an area of the upper layer covered by the extended section of the nanowire in a second lithography, removing a part of the shell at the extended section to expose the conductive or semiconductive core, and disposing a third conductive pad in contact with the exposed core, wherein the first and the second conductive pads form a source terminal and a drain terminal, respectively, and the third conductive pad forms a gate terminal, of a field effect transistor.