Patent ID: 8120183

Claim:
A semiconductor device, comprising: a substrate; a first conductive layer formed over a surface of the substrate; a resistive layer formed over the substrate and first conductive layer; a dielectric layer formed over the substrate, first conductive layer and resistive layer; a first passivation layer formed over the dielectric layer and substrate, wherein a first opening is formed through the first passivation layer to expose the dielectric layer and a plurality of second openings is formed through the first passivation layer and dielectric layer to expose the resistive layer and first conductive layer; a second conductive layer formed in the first opening in contact with the exposed dielectric layer and sidewalls of the first opening, wherein a portion of the first conductive layer, resistive layer, dielectric layer, and second conductive layer constitutes a metal-insulator-metal capacitor; a third conductive layer formed in the first opening over the second conductive layer and further formed in the second openings over the exposed resistive layer and the exposed first conductive layer; a fourth conductive layer formed over the third conductive layer; and a second passivation layer formed over the fourth conductive layer and first passivation layer.