Patent ID: 7977248

Claim:
A method comprising forming a hard mask layer having a first thickness on a semiconductor substrate; patterning a first resist layer on the hard mask layer, wherein the first resist layer includes a first plurality of lines, and wherein adjacent lines of the first plurality of lines are separated by a first pitch; etching the hard mask layer to remove a first portion thereof not covered by the first resist layer to create a first plurality of fins in alignment with the first plurality of lines; removing the first resist layer; patterning a second resist layer on the hard mask layer, wherein the second resist layer includes a second plurality of lines, wherein adjacent lines of the second plurality of lines are separated by a second pitch, wherein the second plurality of lines are patterned in same direction and are interwoven with the first plurality of fins; and etching the hard mask layer to remove a second portion thereof not covered by the second resist layer to create a second plurality of fins in alignment with the second plurality of lines, wherein a remaining portion of the hard mask layer includes the first plurality of fins and the second plurality of fins interwoven and having a second thickness, and wherein a pitch between fins of the first plurality of fins and adjacent fins of the second plurality of fins is less than the first pitch or the second pitch.