Patent ID: 8884445

Claim:
A semiconductor chip comprising: a substrate having one surface, an other surface which substantially faces away from the one surface, bonding pads formed on the one surface of the substrate, and a circuit block electrically connected with the bonding pads and configured to store, process, or transmit data, wherein the substrate is divided into a first region in which the bonding pads and the circuit block are disposed and a second region which is defined outside the first region; at least two alignment bumps formed on the one surface of the substrate in the second region and having different diameters; at least two alignment grooves defined on the other surface of the substrate in the second region and having different diameters; and through electrodes passing through the one surface and the other surface of the substrate in the first region, wherein an alignment bump and an alignment groove with a smallest diameter among the alignment bumps and the alignment grooves have a diameter smaller than the through electrodes, and wherein heights from the at least two alignment bumps to a bottom portion of the substrate are different from heights from the at least two alignment grooves to the bottom portion of the substrate, wherein at least two alignment bumps have different heights and at least two alignment grooves have different depths.