Patent ID: 7023079

Claim:
A stacked semiconductor chip package comprising: a substrate having a top surface; a first chip on the top surface of the substrate and electrically connected to the substrate; a second chip disposed above the first chip and electrically connected to the substrate and having two opposed longitudinal sides defining a first length; and a plate between the first chip and the second chip, physically connected to the first chip and the second chip directly by adhesive, and having two opposed longitudinal sides corresponding to the two longitudinal sides of the second chip, the plate defining a second length, the second length being larger than the first length to expose the opposed longitudinal sides of the plate and to expose the adhesive between the plate and the second chip, wherein the portion of the plate under the second chip is wrapped in the adhesive, and the adhesive is exposed at the corner formed by the plate and second chip along the longitudinal side of the plate.