Patent ID: 8536660

Claim:
A semiconductor structure comprising: a semiconductor substrate; a first MOS device comprising a first gate, wherein the first gate comprises: a first high-k dielectric over the semiconductor substrate; a second high-k dielectric over the first high-k dielectric, wherein the first and the second high-k dielectrics comprise different materials; a first metal layer over the second high-k dielectric, wherein the first metal layer has a thickness great enough for dominating a work-function of the first MOS device; and a second metal layer over the first metal layer, wherein the first and the second metal layers comprise different materials; and a polysilicon layer between the first metal layer and the second metal layer; and a second MOS device comprising a second gate, wherein the second gate does not comprise any polysilicon layer, and wherein the second gate comprises: a third high-k dielectric over the semiconductor substrate, wherein the third high-k dielectric comprises same materials as one of the first high-k dielectric and the second high-k dielectric, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the first metal layer comprise same materials, wherein a combined thickness of dielectric layers between the third metal layer and the semiconductor substrate is less than a combined thickness of dielectric layers between the first metal layer and the semiconductor substrate; and a fourth metal layer over the third metal layer, wherein the third and the fourth metal layers comprise different materials, and the fourth metal layer further comprises a sixth metal layer having a thickness great enough for dominating a work function of the second MOS device, a barrier layer over the sixth metal layer; and a metal re-flow layer over the barrier layer, wherein the metal re-flow layer is configured to be re-flowable.