Patent ID: 6924686

Claim:
A synchronous mirror delay, comprising: a first input buffer for receiving applied clock signal and operable to generate a buffered clock signal in response to the applied clock signal; a first model delay line coupled to the first input buffer to receive the buffered clock signal and operable to generate an input clock signal in response to the buffered clock signal, the input clock signal having a model delay relative to the buffered clock signal; a first group of bi-directional delay lines, each delay line operable to generate a delayed signal having a delay relative to an applied signal; a first clock distributor circuit coupled to the first input buffer and first model delay line and to the first group of bi-directional delay lines, the clock distribution circuit operable apply respective edges of the input clock signal to selected bi-directional delay lines; a second input buffer for receiving a complementary applied clock signal and operable to generate a complementary buffered clock signal in response to the complementary applied clock signal; a second model delay line coupled to the second input buffer to receive the complementary buffered clock signal and operable to generate a complementary input clock signal in response to the complementary buffered clock signal, the complementary input clock signal having a model delay relative to the complementary buffered clock signal; a second group of bi-directional delay lines, each delay line operable to generate a delayed signal having a delay relative to an applied signal; a second clock distributor circuit coupled to the second input buffer and second model delay line and to the second group of bi-directional delay lines, the clock distribution circuit operable apply respective edges of the complementary input clock signal to selected bi-directional delay lines; and an output circuit coupled to the first and second groups of bi-directional delay lines, the output circuit operable in response to the delayed signals from the bi-directional delay lines to generate a synchronized clock signal having rising and falling edges that are synchronized with rising and falling edges of the applied clock signal.