Patent ID: 8093929

Claim:
A programmable digital clock signal frequency divider module with a module clock input, module clock output, a scaling factor input, two programming inputs and a tertiary input, the programmable digital clock signal frequency divider comprising: a primary divider module that includes a first primary module latch circuit with an input coupled to a first one of the programming inputs, a second primary module latch circuit with an input coupled to a second one of the programming inputs, and a third primary module latch circuit with an input coupled to the scaling factor input, wherein an output of the third primary module latch circuit provides a primary divider module output, and wherein the module clock input is coupled to clock inputs of the first, second and third primary module latch circuits; and a secondary divider module that includes a multiplexer and a divide by two latch, wherein the divide by two latch has a latch clock input coupled to the primary divider module output, and wherein the multiplexer that has a multiplexer output that provides the module clock output, a multiplexer control input coupled to the tertiary input, a first multiplexer data input coupled to an output of the divide by two latch and a second multiplexer data input coupled to the primary divider module output, wherein in operation the scaling factor input and the two programming inputs control a transfer of data between the first, second and third primary module latch circuits resulting in the primary divider module processing a first sequence of cycles of a primary digital clock signal with a primary digital clock signal period, supplied to the module clock input, into a first base clock signal with a first base clock signal period of at least twice the primary digital clock signal period and processing a subsequent second sequence of cycles of the primary digital clock signal into a second base clock signal with a second base clock signal period of at least twice the primary digital clock signal period, and wherein the first and second base clock signals provide a sequence of clock pulses to the secondary divider module, and edges of the sequence of clock pulses trigger the divide by two latch resulting in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch, and wherein the tertiary input selects one of the sequence of clock pulses and the latch output clock signal to be a module clock output signal at the module clock output.