Patent ID: 8183662

Claim:
A compact semiconductor package with integrated bypass capacitor, the compact semiconductor package comprising: a circuit substrate having a plurality of terminal leads for external electrical connection; a number of semiconductor dies whose bottom surfaces are bonded atop the circuit substrate; a plurality of elevation-adaptive interconnection plates for bonding and interconnecting the top contact area of each of said semiconductor dies with said circuit substrate while being three dimensionally formed to accommodate for elevation difference there between whereby electrically connecting said top contact area with said terminal leads; a first member of said elevation-adaptive interconnection plates further comprises a first flat-top area and a second member of said elevation-adaptive interconnection plates further comprises a second flat-top area in level with the first flat-top area; a bypass capacitor, having two end capacitor terminals, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area; and a first molding encapsulant extending from a bottom of the circuit substrate to a surface coplanar with the first flat-top area and the second flat-top area plus a second molding encapsulant extending from the surface coplanar with the first flat-top area and the second flat-top area to a surface coplanar with a top surface of the bypass capacitor whereby compactly integrating the bypass capacitor into the semiconductor package with reduced interconnection parasitic impedance.