Patent ID: 7882384

Claim:
A circuit comprising: a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency F P and a secondary clock having a frequency F S′ , wherein the primary data is received over a fixed periodic interval T I and at a rate equal to F P , wherein N is the known amount of primary data received over T I , wherein the data relay stage is further configurable to provide secondary data via a secondary data interface based on the known amount of primary data received over T I and the secondary clock, wherein the F S′ is equal to or greater than the minimum frequency necessary to transmit the secondary data within the fixed periodic interval T I ; and a phase-locked loop (PLL) circuit configurable to receive a data enable signal having a frequency F I equal to 1/T I , the data enable signal marks the beginning and the end of the fixed periodic interval T I , the PLL circuit being further configurable to provide the secondary clock based on the data enable signal, wherein the data relay stage is coupled to receive the secondary clock output by the PLL circuit, wherein the frequency of the secondary clock is independent of the frequency of the primary clock; wherein the data relay stage has a frequency gain G D , wherein the primary data interface has a word width P, wherein the secondary data interface has a word width Q, wherein F S′ =F I NG D P/Q.