Patent ID: 8198724

Claim:
An integrated circuit device having a multi-layer substrate coupled to receive an integrated circuit die and enabling fixed voltage reference signals of a power distribution network and input/output signals to be routed in the integrated circuit device, the multi-layer substrate comprising: a first metal layer having a first plurality of conductive traces extending outward from a region for receiving the integrated circuit die toward an end of the multi-layer substrate; a dielectric layer positioned on the first metal layer; and a second metal layer, which is positioned on the dielectric layer and adjacent to the first metal layer, having a second plurality of conductive traces extending outward from the region for receiving the integrated circuit die toward the end of the multi-layer substrate, wherein the first and second metal layers are separated only by the dielectric layer; wherein each of the first plurality of conductive traces and the second plurality of conductive traces comprises conductive traces for coupling input/output signals and at least one of a first fixed voltage reference signal and a second fixed voltage reference signal; wherein each conductive trace for coupling an input/output signal of the first plurality of conductive traces and the second plurality of conductive traces has adjacent, on each side, a conductive trace for coupling one of the first fixed voltage reference signal and the second fixed voltage reference signal; and wherein the first plurality of conductive traces and the second plurality of conductive traces are staggered in the region for receiving the integrated circuit die so that conductive traces routing input/output signals of the first plurality of conductive traces are not vertically aligned with conductive traces routing input/output signals of the second plurality of conductive traces, and any pair of conductive traces having a conductive trace of the first plurality of conductive traces and a conductive trace of the second plurality of conductive traces in the region for receiving the integrated circuit die which is vertically aligned includes only one conductive trace for routing an input/output signal.