Patent ID: 6853171

Claim:
A low loss multiple output stage of a DC-to-DC converter comprises: first load transistor having a gate, a drain, and a source, wherein the gate of the first load transistor is operably coupled to receive a first output regulation signal, the source of the first load transistor is coupled to a first output, and the drain of the first load transistor is operably coupled to an inductor; sink transistor having a gate, a drain, and a source, wherein the drain of the sink transistor is coupled to the drain of the first load transistor, the source of the sink transistor is coupled to a return potential and the gate of the sink transistor is operably coupled to receive a sink output regulation signal; second load transistor having a gate, a drain, and a source, wherein the gate of the second load transistor is operably coupled to a second output regulation signal, the source of the second load transistor is coupled to a second output, and the drain of the second load transistor is operably coupled to the inductor; and gate logic module operably coupled to: provide a voltage corresponding to the first output to the gate of the second load transistor when the first output regulation signal is active and the sink output regulation signal is inactive, provide the second output regulation signal to the gate of the second load transistor when the second output regulation signal is active and the sink output regulation signal in inactive.