Patent ID: 7350005

Claim:
An interrupt controller for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level, the interrupt controller comprising: request logic operable to receive an indication of unserviced interrupt requests, to apply predetermined criteria to determine which of said plurality of data processing units are candidate data processing units for servicing at least one of said unserviced interrupt requests, and to issue a request signal only to each said candidate data processing unit; priority encoding logic operable to determine a highest priority unserviced interrupt request based on the associated priority levels of the unserviced interrupt requests; and handshake logic for receiving acknowledgement signals associated with said candidate data processing units replying to said request signals issued by the request logic, and, upon receipt of a first acknowledgement signal, for allocating to the candidate data processing unit associated with said first acknowledgement signal the highest priority unserviced interrupt request as indicated by the priority encoding logic.