Patent ID: 8853029

Claim:
A method of forming a vertical MOSFET, comprising: providing a semiconductor layer over a substrate, said semiconductor layer having a trench formed therein; forming a gate dielectric on a top portion of a sidewall of said trench; forming a field plate dielectric on a bottom portion of said sidewall, said field plate dielectric having a first portion with a first thickness at a first depth of said trench, and a second portion with a greater second thickness at a greater second depth of said trench; and filling said trench with a field plate material, wherein forming said field plate dielectric comprises: forming a dielectric layer on said sidewall; filling said trench with a sacrificial filler material; removing a first portion of said sacrificial filler material, thereby exposing an upper portion of said dielectric layer; and at least partially removing said exposed upper portion of said dielectric layer, removing a second portion of said sacrificial filler material, thereby exposing a lower portion of said dielectric layer and leaving a remaining portion of said sacrificial filler material; partially removing said exposed lower portion of said dielectric layer, leaving a remaining portion of said dielectric layer on said sidewalls; and removing said remaining portion of said sacrificial filler material.