Patent ID: 8878253

Claim:
A semiconductor device, comprising: a substrate comprising a plurality of first active regions and a second active region disposed between two of the first active regions, the substrate being lightly doped with p-type impurities; an isolation layer on the substrate, the isolation layer defining the first and second active regions; a plurality of gate structures disposed respectively on the plurality of first active regions; a dummy gate structure disposed on the second active region, a first voltage being applied to the dummy gate structure, and an impurity region disposed in a portion of the second active region, a top surface of the impurity region being lower than a top surface of the substrate and a bottom surface of the impurity region being lower than a bottom surface of the isolation layer, and the impurity region contacting a lower portion of the isolation layer, being heavily doped with p-type impurities and having a first side contacting the isolation layer and a second side opposite the first side contacting the isolation layer such that the impurity region extends beneath the dummy gate structure.