Patent ID: 8023322

Claim:
A method of programming a plurality of non-volatile memory cells in parallel with reduced error due to perturbing electric fields from neighboring memory cells, comprising: (a) organizing said plurality of memory cells into a page of contiguous memory cells linked by a word line; (b) coupling a read/write circuit to each memory cell of said page of contiguous memory cells; (c) sensing said page of contiguous memory cells in parallel to verify said page of memory cells relative to respective target states by sensing currents flowing through each memory cell of the page, wherein each memory cell is coupled to a bit line and wherein the bit line voltage of each said bit line is controlled to be constant during sensing; (d) inhibiting said each memory cell among said page that has been verified; (e) applying a programming pulse to said page of contiguous memory cells; and (f) repeating steps (c)-(e) until all memory cells of said page have been verified.