Patent ID: 6983436

Claim:
A method for correcting crosstalk in layout designing of a semiconductor integrated circuit, comprising: a step of a first checking of a parallel wiring length, wherein data of a parallel wiring length allowable value and layout data regarding crosstalk are input to extract information of parallel wiring length infringement based on both the input data; a step of searching for an empty space, wherein cell area information is input and the empty space is searched for on an infringing wiring route included in the information of parallel wiring length infringement while referring to the cell area information to extract empty space information; a step of creating a candidate for buffer division, wherein a plurality of inverters to be divided from a driving buffer of an infringing wiring part or a driving buffer at the next stage are extracted as a candidate for crosstalk correction; a step of arranging and wiring, wherein the inverters as the candidate for crosstalk correction are arranged and wired in the empty space included in the empty space information; and a step of a second checking of the parallel wiring length, wherein the parallel wiring length infringement is checked with respect to the inverters newly arranged.