Patent ID: 7868671

Claim:
A delay locked loop, comprising: a period locked loop portion including a delay, the delay including an even number of delay cells dependently connected in the form of a ring configured to generate an even number of delay clock signals, wherein transition of at least one delay clock signal of the even number of delay clock signals is configured to be controlled in response to an activated one first selecting signal of an even number of first selecting signals, transition of the remaining clock signals is configured to occur in response to the at least one delay clock signal, the period locked loop portion further includes, a period portion controller configured to compare a phase of an input clock signal and a phase of one delay clock signal of the even number of delay clock signals to generate period portion up and down signals, configured to detect at least one of a rising edge and a falling edge of the input clock signal to generate a pulse signal, and configured to vary a first control signal in response to the period portion up and down signals, and the period portion controller includes, a period portion phase difference detector configured to compare the phase of the input clock signal and the phase of the one delay clock signal, configured to generate the period portion up signal if the phase of the input clock signal is in advance of the phase of the one delay clock signal, and configured to generate the period portion down signal if the phase of the one delay clock signal is in advance of the phase of the input clock signal, a first control signal generator configured to increase the first control signal in response to the period portion up signal and configured to decrease the first control signal in response to the period portion down signal, and a pulse generator configured to detect at least one of the rising edge or the falling edge of the input clock signal to generate the pulse signal.