Patent ID: 7206252

Claim:
A circuit for generating word line control signals in response to external address signals, a refresh count signal, and a row address setup signal, said circuit comprising: a first address buffer configured to latch said external address signals and to output row address signals corresponding to each of said external address signals; a pre-decoder unit configured to pre-decode said row address signals and to output pre-decoded row address signals; a second address buffer configured to delay said refresh count signal for a predetermined time, to generate an enable signal having a predetermined pulse width in response to said row address setup signal and said delayed refresh count signal, and to latch said pre-decoded row address signals to output decoded row address signals in response to said enable signal; a main decoder configured to generate a word line enable signal in response to at least one signal of said decoded row address signals; and a circuit for generating a word-line boosting signal in response to at least one of said decoded row address signals.