Patent ID: 7538622

Claim:
A system, comprising: (a) a phase-locked loop (PLL) comprising: a phase detector including a phase detector input; a charge pump; a loop filter; a voltage controlled oscillator; a frequency divider; a summing circuit; a random number generator; wherein the voltage controlled oscillator is configured to output a VCO output signal having an operating frequency Fvco and resulting from a serially connected circuit path and a feedback circuit path, wherein the serially connected circuit path comprises the phase detector, the charge pump, the loop filter, and the voltage controlled oscillator electrically coupled together in series; wherein the feedback circuit path comprises the frequency divider through which the VCO output signal is fed back to the phase detector; and (b) a multiplexer, wherein the multiplexer includes a multiplexer output electrically coupled to the phase detector input, wherein the multiplexer further includes M multiplexer inputs, M being an integer greater than 1, wherein each multiplexer input of the M multiplexer inputs is configured to receive a multiplexer input signal having a multiplexer input reference frequency, wherein the multiplexer is configured to electrically couple one multiplexer input of the M multiplexer inputs to the multiplexer output, wherein the multiplexer cannot simultaneously electrically couple more than one multiplexer input of the M multiplexer inputs to the multiplexer output, wherein the multiplexer is further configured to carry on the multiplexer output a multiplexer output signal having a reference frequency Fref, wherein the phase detector is configured to receive the multiplexer output signal via the phase detector input, wherein the random number generator is configured to receive the multiplexer output signal such that the multiplexer output is directly coupled to an input of the random number generator, wherein the random number generator is further configured to output a signal u responsive to the multiplexer output signal and a K-bit input signal, wherein the summing circuit is configured to receive the signal u from the random number generator and to sum the signal u with a signal N generated from a counter, wherein the frequency divider is configured to receive an output of the summing circuit, wherein Fvco and Fref are such that Fvco=(N+u)*Fref, wherein N is an integer, wherein u = ∑ i = 1 L ⁢ P ⁡ ( i ) L wherein P(i) is a signed pseudo random number sequence generated by the random number generator, wherein L is a large positive integer, and wherein|u|≦0.5.