Patent ID: 7898343

Claim:
A circuit comprising: a variable frequency oscillator (VFO) adapted to receive a control signal and provide an output signal based on the control signal, such that: during a first calibration mode, the output signal has a first calibration frequency; and during a phase-locked loop (PLL) mode, the output signal has a locked frequency; and loop control circuitry adapted to: during the first calibration mode, form a frequency-locked loop (FLL) using the VFO, and regulate the first calibration frequency based on a first calibration frequency setpoint by controlling the control signal, which is associated with a first control value, such that calibration information is based on the first control value and the first calibration frequency setpoint; and during the PLL mode, form a PLL using the VFO, and regulate the locked frequency based on a locked frequency setpoint by controlling the control signal, such that the PLL has a PLL loop gain, which is based on the calibration information; wherein: the loop control circuitry is further adapted to receive a first reference signal having a reference frequency and a second reference signal having a reference phase; the regulation of the first calibration frequency is further based on a frequency difference associated with the first calibration frequency and the reference frequency; during the PLL mode, the output signal has the locked frequency and a locked phase; and the regulation of the locked frequency is further based on a phase difference associated with the locked phase and the reference phase; wherein the loop control circuitry comprises a frequency reduction circuit adapted to: receive the output signal; and provide a frequency reduced output signal based on applying a frequency reduction to the output signal, wherein: during the first calibration mode, the frequency reduced output signal has a first reduced calibration frequency; the regulation of the first calibration frequency is further based on a frequency difference associated with the first reduced calibration frequency and the reference frequency; during the PLL mode, the frequency reduced output signal has a reduced locked frequency and a reduced frequency locked phase; the regulation of the locked frequency is further based on a phase difference associated with the reduced frequency locked phase and the reference phase; a calibration division ratio is about equal to the first calibration frequency divided by the first reduced calibration frequency; a PLL division ratio is about equal to the locked frequency divided by the reduced locked frequency; and a PLL-to-calibration ratio is about equal to the PLL division ratio divided by the calibration division ratio.