Patent ID: 7134004

Claim:
An information processing device which reads, buffers, decodes, and executes instructions from an instruction store portion ( 11 ) by pipeline processing, comprising: an instruction reading request portion ( 17 ) which assigns a read address to said instruction store portion; an instruction buffering portion ( 12 ) including a plurality of instruction buffers (e- 1 , e- 2 ) which buffer instruction sequences read from said instruction store portion; an instruction execution unit ( 20 ) which de and executes instructions buffered by said instruction buffering portion ( 12 ); a branching instruction detection portion ( 14 ) which detects a branching instruction inside the instruction sequences read from said instruction store portion; and a branch target address information buffering portion ( 15 ) including at least first and second branch target address information buffers (b- 1 , b- 2 ) which, when said branching instruction detection portion has detected a branching instruction, buffer a branch target address information for generating a branch target address of said branching instruction; wherein: when said branching instruction detection portion ( 14 ) detects a first branching instruction ( 02 ) in a first instruction sequence being processed (C 1 ) which is stored in one of said plurality of instruction buffers (e- 1 ), a branch target instruction sequence (C 2 ) of said first branching instruction ( 02 ) is stored in the other one of said plurality of instruction buffers (e- 2 ), and said first instruction sequence (C 1 ) and said branch target instruction sequence (C 2 ) are fetched from said instruction store portion ( 11 ) and stored in said plurality of instruction buffers (e- 1 , e- 2 ) sequentially, when said branching instruction detection portion ( 14 ) detects a next branching instruction ( 04 ) following the first branching instruction ( 02 ) in said first instruction sequence (C 1 ), a first branch target address information ( 41 ) of the next branching instruction ( 04 ) is stored in the first branch target address information buffer (b- 1 ) without prefetching a branch target instruction sequence of the next branching instruction, when said branching instruction detection portion ( 14 ) detects a second branching instruction ( 12 ) in said branch target instruction sequence (C 2 ), a second branch target address information ( 21 ) of the second branching instruction ( 12 ) is stored in the second branch target address information buffer (b- 2 ) without prefetching a branch target instruction sequence of the second branching instruction, and when said first branching instruction is executed, depending on the execution result of the first branching instruction, said branch target address information in either the first or second branch target address information buffer (b- 1 , b- 2 ) is invalidated and another branch target instruction sequence starts to be fetched and stored in said instruction buffer, which is invalidated, based on the branch target address information which is not invalidated.