Patent ID: 8133809

Claim:
A method of fabricating thin metal via interconnects, comprising: (a) providing a substrate comprised of a copper layer formed in a first dielectric layer, said copper layer has a top surface that is coplanar with a top surface of the first dielectric layer; (b) depositing a thin single layer of interlayer dielectric (ILD) on the substrate; (c) sequentially forming a bottom anti-reflective coating (BARC) and a photoresist layer on the ILD; (d) forming a pattern in the photoresist layer comprised of a via opening that is aligned above a portion of the copper layer and exposes a portion of a top surface of the BARC; (e) performing a first reactive ion etch (RIE) process, comprising: (1) a BARC main etch step that removes a substantial thickness of BARC in regions exposed by the via opening; and (2) a BARC over etch step that completely uncovers a top surface of ILD aligned below the via opening (f) performing a second RIE etch process comprised of a low bias power, a fluorocarbon gas, and an initial end point detect signal thereby removing the ILD below the via opening and uncovering a portion of copper layer and first dielectric layer below the via opening; (g) stripping the BARC and any remaining portions of the photoresist layer with an oxygen plasma in an etch chamber with a wafer pedestal temperature, DC bias, and minimum time beyond an end point signal that avoid copper oxidation and damage to copper; and (h) performing a wet clean treatment.