Patent ID: 8468398

Claim:
A loopback testing method, comprising: receiving a test data signal and sampling the test data signal to generate a sampled test data signal; generating an error detection output signal when a bit error is detected in the sampled test data signal when compared to a known test data pattern; generating, based on one or more instances of the error detection output signal, a phase selection control signal, wherein a value of the phase selection control signal varies based on a number of instances of the error detection output signal that were generated within a test time; selecting, based on the value of the phase selection control signal, a particular one of a plurality of clock signals as a sampling clock signal, wherein the plurality of clock signals each have a different phase and are in quadrature with each other, and wherein one of the plurality of clock signals has a phase that is substantially aligned with respect to a phase of the test data signal; and sampling the test data signal based on the sampling clock signal to generate another sampled test data signal that is substantially phase-aligned with respect to the test data signal.