Patent ID: 8129814

Claim:
An integrated circuit including a Schottky diode, comprising: a cathode defined by an n-type semiconductor region of a substrate; an anode defined by a silicide region formed at a surface of the n-type semiconductor region; a p-type region formed in the n-type semiconductor region laterally annularly encircling the silicide region and unconnected by metal interconnect contacts; an n-type contact region formed in the n-type semiconductor region laterally separated by the p-type region from the silicide region and having a higher n-type doping than the n-type semiconductor region; a second silicide region formed at a surface of the n-type contact region; a patterned silicide blocking dielectric layer formed over the surface of the n-type semiconductor region and having first and second openings; the anode defining silicide region being formed at the first opening; the second silicide region being formed at the second opening; and dielectric material of the silicide blocking dielectric layer covering the p-type region; an n-well formed in the substrate, laterally spaced by an isolation structure from the n-type semiconductor region; a gate structure formed over the n-well; and p-type source/drain regions formed in the n-well on sides of the gate structure; a p-well formed in the substrate, laterally spaced by an isolation structure from the n-type semiconductor region and from the n-well; a second gate structure formed over the p-well; and n-type source/drain regions formed in the p-well on sides of the second gate structure; and a second anode defined by a third silicide region formed at the surface of the n-type semiconductor region; and wherein the p-type region formed in the n-type semiconductor region also laterally annularly encircles the third silicide region.