Patent ID: 8831241

Claim:
An earphone jack drive circuit comprising: a mute circuit; a micro-controller, comprising a detect pin and a control pin, wherein the detect pin is connected with an earphone jack, pulled up to a logic high when the earphone jack is not plugged in and pulled down to a logic low when the earphone jack is plugged in, the control pin is set to be logic low when the detect pin is pulled up to the logic high, thereby controlling the mute circuit to enter into the mute mode, and to the logic high when the detect pin is pulled down to the logic low, thereby controlling the mute circuit to enter into the normal mode; a delay switch circuit, further comprising a resistance, a capacitance, a npn transistor and a first current-limiting resistance, wherein a base of the npn transistor is connected with the detect pin via the first current-limiting resistance, a connector of the npn transistor is connected with a system voltage via the first current-limiting resistance, and connected with an input port of the mute circuit, an emitter of the npn transistor is grounded, and connected with the detect pin via the capacitance; wherein during plugging in and unplugging out of an earphone, a momentary logic high of the detect pin charges the capacitance, the capacitance discharges when the detect pin is set to logic low, the npn transistor is kept on for a period and the connector of the npn transistor is set to logic low for the period, the input port of the mute circuit is set to logic low for the period, thereby the mute circuit is controlled to perform the mute mode for the period to eliminate noise generated by plugging or unplugging out the earphone.