Patent ID: 6961746

Claim:
A current integration circuit, comprising: an operational amplifier having its inverting input connected to receive an input current to be integrated, an integration capacitor C 1 connected between said op amp's output and inverting input, said op amp and C 1 arranged such that said input current is integrated on C 1 , a charge dumping circuit arranged to dump a known charge (Q dump ) to the junction (J 1 ) of C 1 and said op amp's inverting input in response to a control signal, Q dump having the opposite polarity with respect to the charge stored on C 1 , a control circuit arranged to allow said input current to be integrated on C 1 for an integration period T int , said control circuit further arranged to provide said control signal to said charge dumping circuit such that Q dump is dumped to junction J 1 when said op amp's output exceeds a predetermined trip voltage but before it becomes saturated so that Q dump reduces the charge stored on C 1 and thereby prevents said op amp's output from saturating, and a counting means for counting the number of times Q dump is dumped to said junction J 1 during a given T int and thereby providing a coarse indication of the magnitude of said integrated input current.