Patent ID: 8488623

Claim:
An integrated circuit comprising: a high-speed serial interface including a plurality of data channels; a plurality of serial channel circuits, each serial channel circuit being associated with a data channel; a data aggregation module; a channel multiplexer circuit coupled to multiple serial channel circuits and to the data aggregation module, wherein the channel multiplexer circuit is programmed to provide data from a subset of the multiple serial channel circuits to inputs of the data aggregation module; and a channel demultiplexer circuit coupled to the data aggregation module and to the multiple serial channel circuits, wherein the channel demultiplexer circuit is programmed to provide data from outputs of the data aggregation module to said subset of the multiple serial channel circuits; bi-directional clock distribution circuitry configured to distribute a master clock signal to each of the multiple serial channel circuits which are coupled to the channel multiplexer and demultiplexer circuits; and wherein each serial channel circuit includes a clock signal generator which generates a clock signal that is programmed to be used as either a local clock signal for that serial channel circuit or as a master clock signal for other serial channel circuits.