Patent ID: 7802045

Claim:
A data processing system comprising: a processor bus operating in accordance with a first specification; a processor coupled to the processor bus; a memory bus operating in accordance with a second specification; a memory coupled to the memory bus; a system bus operating in accordance with a third specification; a device coupled to the system bus; and a controller coupled to the processor bus, the memory bus, and the system bus; wherein the controller has: a first mode in which data is bidirectionally transferred between the processor and the memory, using the processor bus and the memory bus, a second mode in which data is bidirectionally transferred between the memory and the device, using the memory bus and the system bus, a third mode in which data is bidirectionally transferred between the device and the processor, using the system bus and the processor bus; wherein in the first mode: if the controller transfers data from the processor to the memory, the controller outputs a signal in conformity with the second specification to the memory bus, the signal is converted from a signal received from the processor; wherein in the second mode: if the controller transfers data from the device to the memory, the controller outputs a signal in conformity with the second specification to the memory bus, the signal is converted from a signal received from the device; and wherein in the third mode: if the controller transfers data from the device to the processor, the controller outputs a signal in conformity with the first specification to the processor bus, the signal is converted from a signal received from the device, and if the controller transfers data from the processor to the device, the controller outputs a signal in conformity with the third specification to the system bus, the signal is converted from a signal received from the processor.