Patent ID: 7716520

Claim:
A multi-CPU computer system having a plurality of CPUs installed therein for operating on a common operating system, comprising: a nonvolatile storage device; a first CPU that incorporates a first error notification circuit for notifying another CPU of error information when a hardware error has occurred in said first CPU; and a second CPU that incorporates a second error notification circuit for obtaining the error information from said first CPU and notifying the operating system of the error information, said second CPU executing a process for storing fault information including the error information in said storage device, and a process for restarting the multi-CPU computer system, according to the operating system, when the operating system is notified of the error information from said second error notification circuit; wherein the first CPU further comprises a third error notification circuit to notify the operating system of the error information, and wherein the first CPU temporarily stops processing according to the operating system upon notification of the error information by said third error notification circuit and, when the multi-CPU computer system is not restarted during the temporary stoppage of the processing, stores data including the error information in said nonvolatile storage device, and restarts the multi-CPU computer system according to the operating system after a lapse of a predetermined time period from the stoppage of the processing.