Patent ID: 8867285

Claim:
A data write circuit of a semiconductor apparatus, comprising: a pre-patch unit configured to generate a plurality of data by latching data inputted serially; global input/output lines; a plurality of latches configured to be inputted the plurality of data, latch and output the plurality of data to the global input/output lines with a determined time difference in response to activation of a plurality of control signals; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data among the plurality of data is outputted at different timing with other data of the plurality of data by partial latches of the plurality of latches, wherein the control unit includes: a divider configured to divide a data clock signal by a predetermined division ratio and generate a data clock division signal; and a control signal generator configured to generate the plurality of control signals by selecting the data clock signal or a signal acquired by combining the data clock division signal and the data clock signal in accordance with a combination of an address signal and a data transmission mode signal.