Patent ID: 8145887

Claim:
A method, in a data processing system, for enhancing the execution of independent loads in a processing unit, the method comprising: detecting, by the processing unit, if a long-latency miss associated with a load instruction has been encountered, wherein the processing unit is operating in a single threaded mode; responsive to the encounter of the long-latency miss, entering, by the processing unit, a load lookahead mode in the processing unit; responsive to entering the load lookahead mode: dispatching, by the processing unit, each instruction from a first set of instructions from a first buffer with an associated vector, wherein the associated vector is within a set of vectors in a first vector array; fetching, by the processing unit, additional instructions into the first buffer in order until the first buffer is full; responsive to filling the first buffer, fetching, by the processing unit, the additional instructions into a second buffer in order until the second buffer is full; and responsive to filling the second buffer, stopping, by the processing unit, the fetch of the additional instructions; determining, by the processing unit, whether the first set of instructions from the first buffer have completed execution; and responsive to completed execution of the first set of instructions from the first buffer: copying, by the processing unit, the set of vectors from the first vector array to a second vector array; and dispatching, by the processing unit, a second set of instructions from the second buffer with an associated vector from the second vector array.