Patent ID: 8874885

Claim:
In a microprocessor with lookahead branch prediction, the microprocessor including a microprocessor pipeline having an instruction stream and a branch target buffer, a method for mitigating lookahead branch prediction latency, the method comprising: receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline; receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline; determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor; based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction; and based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline for execution.