Patent ID: 7324392

Claim:
An integrated circuit comprising: a plurality of operational circuits to be tested; a test read only memory storing at least one test set consisting of a test algorithm and test data; and a programmable built-in self test unit connected to said plurality of operational circuits to be tested and said test read only memory, said programmable built-in self test unit including a plurality of memory mapped readable/writable test data read/write registers, and a plurality memory mapped readable/writable test algorithm read/write registers; and said programmable built-in self test unit operable to: load from said test read only memory operable for each test set stored in said test read only memory one of (1) both said test algorithm and said test data, (2) only said test algorithm, and (3) only said test data, test at least one of said plurality of operational circuits to be tested according to said test algorithm and/or said test data loaded by storing selectively loaded test data in said test data read/write registers, storing selectively loaded test algorithms in said test algorithm read/write registers, loading said test algorithm from said test read only memory into said test algorithm read/write registers and loading said test data from said test read only memory into said test data read/write registers, loading said test algorithm from said test read only memory and loading said test data read/write registers via a memory mapped write operation, loading said test algorithm read/write registers via a memory mapped write operation and loading said test data from said test read only memory into said test data read/write registers, and testing said at least one of said plurality of operational circuits to be tested according to an algorithm stored in said test algorithm read/write registers and data stored in said test data read/write registers.