Patent ID: 8786538

Claim:
A display device comprising: a display panel assembly including data lines and gate lines intersecting each other; a data driving circuit configured to convert digital video data into data voltages which are supplied to the data lines; a gate driving circuit configured to sequentially supply gate pulses to the gate lines, wherein a voltage of each of the gate pulses increases from a gate low voltage to a precharging voltage during a first rising time all along the gate lines and thereafter increases from the precharging voltage to a gate high voltage during a second rising time all along the gate lines, and wherein the voltage of each of the gate pulses decreases from the gate high voltage to the precharging voltage during a first falling time all along the gate lines and thereafter decreases from the precharging voltage to the gate low voltage during a second falling time all along the gate lines, a timing controller which supplies the digital video data to the data driving circuit and controls operation timings of the data driving circuit and the gate driving circuit, wherein the timing controller generates gate shift clocks swinging in a TTL logic voltage level and a power sharing control signal for controlling the gate pulses, wherein the gate driving circuit comprises: a level shifter configured to convert the gate shift clocks into the gate pulses under the control of the timing controller; and a shift register configured to sequentially supply the gate pluses output from the level shifter to the gate lines, wherein the level shifter comprises: a first node configured to be applied with the precharging voltage; a second node configured to output the gate pulses; a power sharing switch circuit configured to be connected between the first node and the second node, applied with the precharging voltage via the first node, form a current path between first node and the second node during the first rising time and the first falling time, and block the current path between the first node and the second node during the second rising time and the second falling time; a first transistor configured to be connected to the power sharing switch circuit and the second node and applied with the gate high voltage; a second transistor configured to be connected to the power sharing switch circuit and the second node and applied with the gate low voltage; and a switch controller configured to control operation timings of the power sharing switch circuit, the first transistor, and the second transistor, in response to the gate shift clocks and the power sharing control signal.