Patent ID: 8108624

Claim:
A microprocessor, comprising: first and second functional units, each coupled to and configured to access a data cache; and the data cache, comprising: a data array, having a predetermined organization, comprising: a write port by which the first functional unit writes data to a cache line of the data array; a modified bit array, having the corresponding predetermined organization as the data array, comprising: a write port by which the first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array written to by the first functional unit has been modified; and a read port by which the second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified; and a tag array, having the corresponding predetermined organization as the data array, comprising: a read port by which the second functional unit reads a partial status of the corresponding cache line in the data array, wherein the partial status, when combined with the modified bit, determines whether the cache line has been modified; wherein the tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.