Patent ID: 8901663

Claim:
A semiconductor device, comprising: a substrate; a device isolation pattern located on the substrate and delimiting first and second active regions of the substrate, and the device isolation pattern including a recessed portion defining a recess in the device isolation pattern, the recessed portion having a bottom surface located below a plane coincident with a surface of the active regions, the bottom surface delimiting the bottom of the recess; first and second gate electrode structures disposed on the first and second active regions, respectively, and wherein the first and second gate electrode structures comprise first and second gate electrodes, respectively, first insulation spacers disposed on opposite sides of the first gate electrode, and second insulation spacers disposed on opposite sides of the second gate electrode, the first gate electrode includes a first etching barrier conductive pattern having a bottom extending horizontally on the first active region, and sides extending vertically over the first insulation spacers, respectively, and a first metal pattern disposed within the first etching barrier conductive pattern, the first etching barrier conductive pattern and the first metal pattern presenting an upper surface of the first gate electrode, the second gate electrode includes a second etching barrier conductive pattern having a bottom extending horizontally on the second gate dielectric pattern, and sides extending vertically over the first insulation spacers, respectively, and a second metal pattern disposed within the second etching barrier conductive pattern, the second etching barrier conductive pattern and the second metal pattern presenting an upper surface of the first gate electrode, the first and second gate electrodes have different work functions, and the first active region includes n-type impurities adjacent the sides of the first gate electrode, and the second active region includes p-type impurities adjacent sides of the second gate electrode, whereby the first and second regions respectively correspond to NMOS and PMOS regions of the device; a passive circuit element disposed on the bottom surface of the recessed portion of the device isolation pattern so as to be situated in the recess defined by the recessed portion; and an interlayer dielectric layer on the substrate, and wherein the passive circuit element is located in a passive circuit element region of the substrate, the respective upper surfaces of the first and second gate electrodes are coplanar, the interlayer dielectric layer extends within the recess of the device isolation layer so as to occupy the recess with the passive circuit element, and the interlayer dielectric layer has a planar upper surface that extends across the active and passive circuit element regions, and is substantially coplanar with the upper surfaces of the first and second gate electrodes.