Patent ID: 7895458

Claim:
A power control apparatus comprising: an active block in which power is maintained in a power-on state; and an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1, wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit, wherein each of the power management units comprises: an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and a state machine that controls the MTCMOS controller, wherein the state machine comprises a floating prevention circuit (FPC) temporarily storing information stored in the state machine when the state machine is even in a power-off state and outputting the stored information to the active block or a higher power management unit of the power management unit having the state machine.