Patent ID: 7079998

Claim:
A method for analyzing power noise, wherein the method for analyzing power noise is utilized in an IC design, and comprises: providing a power network model of the IC design; according to a predetermined method, defining the power network model as being constructed by a plurality of unit blocks; according to a position of each of the plurality of unit blocks and a covering range thereof, obtaining a plurality of data of a plurality of components that are electrically connected with each of the plurality of unit blocks, wherein the plurality of data are regarded as a reference data of each of the plurality of unit blocks; performing a sieving process onto the reference data of each of the plurality of unit blocks for obtaining a sieved data of each of the plurality of unit blocks, wherein the plurality of sieved data of the plurality of unit blocks are processed in an AC analysis step; and performing the AC analysis step according to the plurality of sieved data of the plurality of unit blocks for obtaining an AC analysis result of the power network model.