Patent ID: 7598784

Claim:
An electronic circuit comprising: an input node coupled to receive an input signal comprising a first transition and a second transition; a rising transition control circuit (RTCC) comprising an input configured to receive an enable signal, an input coupled to the input node and an output to produce a first output signal in response to the enable signal being asserted, the first output signal providing a first transition in response to the first transition and a first control signal; a falling transition control circuit (FTCC) comprising an input configured to receive the enable signal, an input coupled to the input node and an output to produce a second output signal in response to the enable signal being asserted, the second output signal providing a second transition in response to the second transition and a second control signal; and an output circuit having a first input coupled to the output of the RTCC, a second input coupled to the output of the FTCC, and a third input coupled to the input node, the output circuit configured to process the first output signal first transition with the second output signal second transition and the input signal to provide an output signal having delayed transitions with respect to the first and the second transitions of the input signal.