Patent ID: 8440530

Claim:
A method, comprising: forming gate structures for a PMOS transistor and for an NMOS transistor above a semiconducting substrate, said gates structures being adjacent to one another; forming a continuous first liner layer that extends continuously above said substrate and above said gate structures for both said PMOS transistor and said NMOS transistor; after forming said continuous first liner layer: performing a plurality of extension ion implant processes through said continuous first liner layer to form extension implant regions in said substrate for said PMOS transistor and said NMOS transistor; and performing a plurality of halo ion implant processes through said continuous first liner layer to form halo implant regions in said substrate for said PMOS transistor and said NMOS transistor; after forming said extension implant regions and said halo implant regions, performing an etching process to remove said continuous first liner layer; after removing said first liner layer, forming a second liner layer on said gate structures of said PMOS transistor and said NMOS transistor; after forming said second liner layer, forming a first spacer adjacent to said second liner layer and proximate said gate structures of both said PMOS transistor and said NMOS transistor; performing a plurality of source/drain ion implant processes with said first spacer in place to form deep source/drain implant regions in said substrate for said PMOS transistor and said NMOS transistor; removing said first spacer; and after removing said first spacer, forming a layer of material between said adjacent gate structures, wherein said layer of material occupies at least the space formerly occupied by said first spacer.