Patent ID: 7030020

Claim:
A method to form MOS gates in an integrated circuit device comprising: forming a dielectric layer overlying a substrate; forming a polysilicon layer overlying said dielectric layer; forming a silicon oxide layer overlying said polysilicon layer; forming a patterned masking layer overlying and selectively exposing said silicon oxide layer; thereafter oxidizing said polysilicon layer to increase thickness of said exposed silicon oxide layer wherein said thickened silicon oxide layer encroaches under the edges of said masking layer and wherein said silicon oxide layer does not thicken under other interior areas of said masking layer; thereafter removing said masking layer; thereafter etching said silicon oxide layer to selectively expose said polysilicon layer where said silicon oxide layer did not thicken; and thereafter etching through said exposed polysilicon layer to thereby form MOS gates in the manufacture of said integrated circuit device wherein before oxidizing said polysilicon layer, said silicon oxide layer is not etched through.