Patent ID: 8072819

Claim:
A memory device, comprising a first terminal; a second terminal; a third terminal; a control logic section connected to the first terminal; and a multiplexer configured convert the first terminal, the second terminal, and the third terminal; wherein the memory device is switchable between a serial interface mode and a parallel interface mode; wherein, when the memory device is in the serial interface mode, the first terminal is an address/data input terminal for inputting an address, data, and a command, the second terminal is a data output terminal, and the third terminal is a control terminal; wherein the control logic section is structured to control the multiplexer to convert the first terminal, second terminal, and third terminal such that the first terminal, the second terminal, and the third terminal become input/output terminals when the control logic section receives, by an input via the first terminal, a data readout command that is arranged as plural bits of serial data and instructs use of a parallel interface.