Patent ID: 7713853

Claim:
A method for manufacturing electronic devices on a semiconductor substrate with wide band gap comprising the steps of: forming a screening structure on said semiconductor substrate comprising at least a dielectric layer overlapped by an exposed conductive layer forming gate regions of a MOS device, said screening structure leaving a plurality of areas of said semiconductor substrate exposed; carrying out first ion implantation of a first type of dopant in said semiconductor substrate to form at least a first implanted region said first ion implantation with an inclination angle with respect to a normal to a surface of said semiconductor substrate which varies between 30° and 60°; and carrying out first a ion implantation of a second type of dopant with an inclination angle with respect to a normal to a surface of said semiconductor substrate which varies between 30° and 60° in said semiconductor substrate to form at least a second implanted region inside said at least a first implanted region; said method further comprising an activation thermal process of the first type of dopant and second type of dopant at temperatures lower than 1250° C. suitable to complete said formation of said at least first and second implanted regions and in order to obtain a doping profile of said channel region of the Gaussian type with a concentration peak next to a medium point of said channel region.