Patent ID: 7633498

Claim:
A display driver, comprising: a first signal generator that generates a first charge pumping signal (DCCLK 1 ) synchronized to a first system clock signal (DOTCLK 1 ), wherein the first charge pumping signal is used for charge pumping in a video interface mode; and a second signal generator that generates a second charge pumping signal (DCCLK 2 ) synchronized to a second system clock signal (DOTCLK 2 ), wherein the second charge pumping signal is used for charge pumping in a CPU interface mode, and wherein the first and second clock signals are from different sources; and wherein a common signal (VCOM) applied to a common node of the display panel is synchronized to the first charge pumping signal (DCCLK 1 ) during the video interface mode and synchronized to the second charge pumping signal (DCCLK 2 ) during the CPU interface mode, and wherein the video interface mode is for processing data based on the first system clock signal, and wherein the CPU interface mode is for processing data based on the second system clock signal.