Patent ID: 7297628

Claim:
A method for forming vias through an interlayer dielectric region of a monolithically integrated device where the interlayer dielectric region (ILD) is structured to separate a first conductive layer from a second conductive layer of the monolithically integrated device, the method comprising: (a) providing an organic Anti-Reflection Coating layer (ARC layer) above the material of the ILD; (b) providing a photoresist layer above the ARC layer, where the photoresist layer includes a plurality of first openings defined therethrough; (c) creating from the first openings, a plurality of second openings extending through the organic ARC layer, where the second openings have inwardly-tapered sidewalls such that bottom width dimensions of the second openings are smaller than corresponding width dimensions of the first openings; and (d) creating from the second openings, a plurality of third openings extending through the ILD material; wherein said first conductive layer is part of an active layers set and wherein said second conductive layer defines a first major interconnect layer above said active layers set.