Patent ID: 7893505

Claim:
A semiconductor integrated circuit device comprising: a memory cell of a static random access memory including a first transfer MISFET and a second transfer MISFET, a first drive MISFET and a second drive MISFET and a first load MISFET and a second load MISFET, the first and second drive MISFETs each having a source region and a drain region formed in a substrate, the first and second load MISFETs each having a source region and a drain region formed in a substrate, gate electrodes of the first and second drive MISFETs and the first and second load MISFETs formed over a main surface of the substrate; a first insulating film formed over the first and second transfer MISFETs, the first and second drive MISFETs and the first and second load MISFETs, wherein the first insulating film has a first opening and a second opening; a first capacitor element formed over the side wall and bottom of the first opening such that the first capacitor element has a lower electrode including a first conductive film formed along the side wall and bottom of the first opening, a capacitor insulator film including a second insulating film formed over the first conductive film, and an upper electrode including a second conductive film formed over the second insulating film; and a second capacitor element formed over the side wall and bottom of the second opening such that the second capacitor element has a lower electrode including a third conductive film formed along the side wall and bottom of the second opening, a capacitor insulator film including a third insulating film formed over the third conductive film, and an upper electrode including a fourth conductive film formed over the third insulating film, wherein the first opening is formed to extend over the drain region of the first drive MISFET and the drain region of the first load MISFET such that the first conductive film is electrically connected to the drain of the first drive MISFET, the drain of the first load MISFET, the gate electrode of the second drive MISFET and the gate electrode of the second load MISFET, and wherein the second opening is formed to extend over the drain region of the second drive MISFET and the drain region of the second load MISFET such that the third conductive film is electrically connected to the drain of the second drive MISFET, the drain of the second load MISFET, the gate electrode of the first drive MISFET and the gate electrode of the first load MISFET.