Patent ID: 7388790

Claim:
A semiconductor integrated circuit device comprising: dynamic latches whose output terminals are commonly connected to a first node; a switch circuit configured to selectively connect the dynamic latches to a second node; a capacitor to hold data of the second node; a first static latch whose input terminal is connected to the first node; and a first transfer gate which connects the first node and the second node on the basis of a first transfer control signal, wherein in refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and held in the capacitor, latch of the first static latch is released, data of a dynamic latch selected by the switch circuit as a refresh target is bootstrapped, the bootstrapped data is transferred to the first node to distribute charges, thereby setting a potential of the first node, the data amplified by the first static latch and held in the first node is written back to the dynamic latch as the refresh target to refresh the dynamic latch, the dynamic latches as the refresh target are sequentially selected by the switch circuit so that the dynamic latches are refreshed, and the data of the second node, which is held in the capacitor, is moved to the first node through the first transfer gate and written back to the first static latch.