Patent ID: 7281155

Claim:
A semiconductor memory device including a plurality of selecting lines for writing or reading data by selecting a specific memory cell from among a plurality of memory cells on the basis of the address signal supplied from external, comprising: at least one first redundancy selecting line positioned at one of the ends in a plurality of said selecting lines and at least one second redundancy selecting line positioned at the other end; and a switch circuit for changeably connecting a plurality of decode signal lines decoding said address signal to a plurality of said selecting lines and said redundancy selecting lines; wherein, when any fault occurs in a plurality of said selecting lines, a first switch operation for shifting at least one of said decode signal lines in the direction of said first redundancy selecting line is executed, or a second switch operation for shifting at least one of said decode signal lines in the direction of said second redundancy selecting line is executed, or both of said first and second switch operations are executed.