Patent ID: 7262647

Claim:
A delay locked loop circuit, comprising: a delay unit, receiving a reference signal and generating an output signal thereof, a delay time of the output signal of the delay unit being adjusted corresponding to the reference signal according to a phase control voltage, wherein the delay time having a lower limit; a phase detector, detecting a phase difference between the reference signal and the output signal of the delay unit, and outputting a voltage control signal; a charge pump, adjusting the phase control voltage according to the voltage control signal during a normal operation period; a start-up circuit, adjusting the phase control voltage to control the delay unit during an initial period, so as to adjust the delay time of the output signal of the delay unit to the lower limit; a correction circuit, adjusting the phase control voltage to control the delay unit during a correction period, so as to adjust the delay time of the output signal of the delay unit within a phase detection range of the phase detector; wherein, the initial period is before the correction period, the correction period is before the normal operation period.