Patent ID: 8462477

Claim:
An apparatus comprising: a protection circuit comprising an input, an output, and a junction field effect transistor (JFET), the JFET having a source electrically coupled to the input, and a drain electrically coupled to the output, wherein the JFET has a pinch-off voltage (Vp) of greater than 2 V in magnitude, wherein the JFET has a drain-source on resistance (R DSON ) when operating in the triode region of the JFET, wherein a relationship among W, L, Vp, and R DSON substantially satisfies R DSON =(L/W)/(2×B′×Vp), wherein W is a width of a channel of the JFET, wherein L is a length of the channel of the JFET, and wherein B′ is a transconductance parameter of the JFET; and an internal circuit having an input configured to receive a signal from the output of the protection circuit, wherein the internal circuit and the protection circuit are part of an integrated circuit, wherein the protection circuit is configured to protect the internal circuit from overvoltage and/or undervoltage conditions.