Patent ID: 8228731

Claim:
A method comprising: activating, by access circuitry of a digital memory device at a first time, a CMOS-compatible non-volatile storage element configured to hold a charge corresponding to a binary value, wherein: the CMOS-compatible non-volatile storage element is coupled to an access transistor in series; the CMOS-compatible non-volatile storage element is coupled to a storage capacitor via a storage node; and said activating causes a storage voltage to be applied to the storage node by the CMOS-compatible non-volatile storage element; fixing, by the access circuitry at a second time later than the first time, a row select voltage on a row line coupled to the access transistor, wherein the storage capacitor is configured to substantially hold the storage voltage driven to the storage node for a period of time greater than or equal to an elapsed time between the first and second times; and sensing, by the access circuitry at the second time, the storage voltage.