Patent ID: 7035956

Claim:
A transmission control circuit connected to a CPU and a communications bus, comprising: transmission data memory means for storing transmission data in segments in accordance with a command from the CPU; address information memory means for storing at least address information on the transmission data; transmission means for transmitting the transmission data to the communications bus; address setting means for sequentially storing address data for the transmission data in accordance with the address information; and communications control means for carrying out such a control that the transmission data is transmitted in groups of segments to the communications bus through the transmission means in accordance with the address data, wherein the address data stored in the address setting means is updated after each segment is transmitted, after each group of segments has been transmitted, if the transmission data has been successfully transmitted, the address information is updated by the address setting means according to the address data, and if the transmission data has not been successfully transmitted, the address information remains unchanged, and at least one group of segments includes two or more segments.