Patent ID: 8204166

Claim:
An apparatus comprising: a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock, wherein the transition clock is provided as the output clock during switching the output clock from the source clock to the destination clock; a phase difference calculation module configured to calculate a the phase difference between the source clock and the destination clock; a clock generation module configured to generate a plurality of clocks, wherein each clock of the plurality of clocks has a phase different from another one of the plurality of clocks; a clock selection module configured to select one of the plurality of clocks as the transition clock, wherein the clock of the plurality of clocks selected first has a phase least different from the source clock from among the plurality of clocks and the phase difference between the clock of the plurality of clocks selected last and the destination clock is within the predetermined range; and a control circuit configured to receive a clock switching signal and configured to provide: a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and a signal to the multiplexer to identify which one of the source clock, the destination clock, or the transition clock the multiplexer is to provide.