Patent ID: 6969646

Claim:
A method of fabricating a metal oxide semiconductor field effect transistor (MOSFET), on a semiconductor substrate, featuring the integration of an anneal procedure used to activate dopants in a polysilicon gate structure, and the formation of offset silicon oxide spacers on the sides of said polysilicon gate structure, comprising the steps of: forming a gate insulator layer on said semiconductor substrate; forming a polysilicon layer on said gate insulator layer; performing an ion implantation procedure to place dopants in said polysilicon layer; performing a first anisotropic RIE procedure to define said polysilicon gate structure; forming a first silicon oxide layer directly on said polysilicon gate structure via chemical vapor deposition procedures at a temperature between about 400 to 700Â°C.; immediately after forming said first silicon oxide layer performing said anneal procedure activating said dopants in said polysilicon gate structure; performing a second anisotropic RIE procedure to define said offset silicon oxide spacers on the sides of said polysilicon gate structure; forming a lightly doped source/drain region in an area of said semiconductor substrate not covered by said polysilicon gate structure or by said offset silicon oxide spacers; forming a second silicon oxide layer; forming a silicon nitride layer; forming a third silicon oxide layer; performing a third anisotropic RIE procedure to define first silicon oxide spacer components from said third silicon oxide layer, to define L shaped silicon nitride spacer components from said silicon nitride layer, and to define second silicon oxide spacer components from said second silicon oxide layer, resulting in a composite insulator spacers on the sides of said polysilicon gate structure, comprised of underlying, said offset silicon oxide spacers, said second silicon oxide spacer components, said L shaped silicon nitride spacer components, and overlying, said first silicon oxide spacer components; and forming a heavily doped source/drain region in an area of said semiconductor substrate not covered by said polysilicon gate structure or by said composite spacers.