Patent ID: 7163898

Claim:
A method for manufacturing circuit structures integrated in a semiconductor substrate that includes isolation regions, the method comprising the steps of: depositing a conductive layer onto said semiconductor substrate; forming a first mask of a first material on said conductive layer; forming a second mask made of a second material that is different from the first material and provided with first openings of a first width having spacers formed on sidewalls of the first openings to uncover portions of said first mask having a second width which is smaller than the first width; partly etching away said conductive layer through said first and second masks such to form grooves of said second width and leaving thin portions of said conductive layer covering said regions provided in said substrate; removing said second mask and said spacers; and after removing said second mask and said spacers, etching said thin portions of said conductive layer through the grooves to uncover said regions provided in said substrate and form conductive lines from the conductive layer.