Patent ID: 8791729

Claim:
An apparatus comprising: at least three serially connected latches comprising a first latch, a second latch, and at least one delay latch collectively forming a frequency divider chain and each latch comprising only a single clock input, only a single data input, a data output, and an inverting data output; wherein the data output of each latch is electrically connected to the data input of a next latch in the chain, and the inverting data output of a last latch in the chain is electrically connected to the data input of a first latch in the chain, and each latch receives an input clock having a first frequency and an individual input phase; wherein the first and second latches form a first flip-flip and each receive an input clock having a different phase and wherein the at least one delay latch is connected between the first and second latches and receives an input clock having a phase that is different from the phase of the input clocks received by the first and second latches forming the first flip flop, wherein a phase difference between the phase of the input clock of one latch with reference to the phase of the input clock of a next latch is larger than zero and does not exceed 180 degrees, and a phase difference between the phase of the input clock of the first latch in the chain with reference to the phase of the input clock of the last latch in the chain is larger than 180 degrees and less than 360 degrees.