Patent ID: 8830772

Claim:
A circuit for sensing a logic level of a bit stored in a bitcell, comprising: a sense amplifier including an imbalanced latch, the imbalanced latch comprising: a first inverter including a first transistor, the first inverter having an input terminal and an OUT_B output node; and a second inverter including a second transistor, the second inverter having an input terminal and an OUT output node, wherein the OUT_B output node of the first inverter is coupled to the input terminal of the second inverter, and the OUT node of the second inverter is coupled to the input terminal of the first inverter, wherein the first transistor has a first channel width (W) to channel length (L) ratio, and the second transistor has a second W/L, and the second W/L of the second transistor is greater than the first W/L of the first transistor, wherein the bitcell is operatively coupled to the sense amplifier, and wherein at least one of a signal at the OUT_B node and a signal at the OUT node is indicative of a logic level of a bit stored in the bitcell.