Patent ID: 7009892

Claim:
A semiconductor memory device comprising: N planes of a memory cell array in which memory cells are arranged in a matrix; and an address processing mechanism for providing simultaneous execution of reading and writing on the N planes, wherein in the simultaneous execution, in a period of the reading operation on one of the N planes, the writing operation can be performed on only arbitrary one of the other N- 1 planes, in a period of the writing operation on one of the N planes, the reading operation can be performed on only arbitrary one of the other N- 1 planes, the address processing mechanism has: a control logic circuit for generating N read selection signals each selecting one of the N planes for the reading operation and N write selection signals each selecting one of the N planes for the writing operation; an address selection circuit disposed in each of the N planes; and an address buffer circuit for simultaneously providing a write address and a read address in order to access the memory cell array, each of the address selection circuits is configured so as to be able to receive one of the N read selection signals and one of the N write selection signals from the control logic circuit, a first part of each of the read address and the write address is supplied to the control logic circuit in order to generate the N read selection signals and the N write selection signals, a second part of each of the read address and the write address is supplied to each of the address selection circuits, and the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.