Patent ID: 7245517

Claim:
A ferroelectric random access memory comprising; a memory cell array in which a plurality of memory cell blocks each obtained by series-connecting a plurality of memory cells each constituted by a cell transistor having source and drain terminals and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor are arranged in the form of a matrix, a block group being constituted by first to fourth memory cell blocks sequentially adjacently arranged in a row direction; a plurality of word lines arranged to extend in the row direction of the memory cell array; a plurality of bit lines arranged to extend in a column direction of the memory cell array and including first to fourth bit lines, the first bit line and the third bit line constituting a first bit line pair, and the second bit line and the fourth bit line constituting a second bit line pair; a plurality of plate lines arranged to extend in the row direction of the memory cell array and including first to fourth plate lines to which one ends of the first to fourth memory cell blocks are connected, respectively; a plurality of sense amplifier circuits arranged on a one-end side of the memory cell array in the column direction every block group constituted by the first to fourth memory cell blocks; first to fourth block selection transistors connected between the other ends of the first to fourth memory cell blocks and the first to fourth bit lines, respectively; a first block selection signal line arranged to extend in the row direction of the memory cell array and commonly connected to gate electrodes of the first and second block selection transistors; and a second block selection signal line arranged to extend in the row direction of the memory cell array and commonly connected to gate electrodes of the third and fourth block selection transistors.