Patent ID: 7990757

Claim:
A method of operating a memory circuit having: a plurality of bit line structures comprising true and complementary bit lines; a plurality of word line structures comprising READ and WRITE word lines; and a plurality of cells selectively coupled to a corresponding one of said bit line structures under control of a corresponding one of said word line structures, each of said cells in turn comprising: a first inverter having a first inverter double-gate pull-down device; a second inverter having a second inverter double-gate pull-down device, said second inverter being cross-coupled to said first inverter to form a storage flip-flop; and first and second access devices configured to selectively interconnect said cross-coupled inverters with said true and complementary bit lines of a corresponding one of said word line structures, said first and second access devices being double-gate devices, each having a first gate connected to said READ word line and a second gate connected to said WRITE word line; said method comprising the steps of: activating said READ word line but not said WRITE word line during a READ operation for a given one of said cells, so that said first and second access devices of said given one of said cells operate in a single-gate mode while said double-gate pull-down devices of said given one of said cells operate in a double gate mode; and activating both said READ word line and said WRITE word line during a WRITE operation for said given one of said cells, so that said first and second access devices of said given one of said cells operate in a double-gate mode.