Patent ID: 8120966

Claim:
A method of operating a dual charge retaining transistor NOR flash memory device for the correction of over-erasure comprising: erasing a block of pages of dual charge retaining transistor NOR flash cells, erasing comprising; selecting one block section of a plurality of block sections of the block of dual charge retaining transistor NOR flash cells; erasing a plurality of charge retaining transistors of the selected block section of the dual charge retaining transistor NOR flash cells; verifying that each page of the block section of the charge retaining transistors is erased to a threshold voltage level of an upper limit of a first program state; if any of the charge retaining transistors within a selected page of the block section have their threshold voltage level greater than the upper limit of the first program state, repetitively erasing the selected block section and verifying the selected page of charge retaining transistor until all the charge retaining transistors have their threshold voltage levels less than the upper limit of the first program state; verifying that each page of charge retaining transistors is not over-erased to the threshold voltage level that is less than a lower limit of the first program state; and if any of the charge retaining transistors one selected page has their threshold voltage levels less than a lower limit of the first program state, repetitively programming and verifying those charge retaining transistors of the one selected page to bring their threshold voltage levels to be greater than the lower limit of the first program state.