Patent ID: 8418159

Claim:
An apparatus, coupled with computer memory storage, for optimizing a transaction comprising an initial sequence of computer operations, comprising: a processing unit configured to identify one or more idempotent operations comprised within the initial sequence, wherein each of the computer operations of the initial sequence has a respective sequence number (sn), a function (k) and a variable (v) that receives the value of the function (k), the identifying comprising: constructing directed line segments representative of the computer operations of the initial sequence, the constructing comprising: defining a function vertex (sn,k) and its variable vertex (sn,v), wherein the function vertex (sn,k) corresponds to the function (k) and the variable vertex (sn,v) corresponds to the variable (v), a) constructing for sequence numbers i and j, where i<j, a directed line segment from the variable vertex (sn,v) of the sequence number i to the function vertex (sn,k) of the sequence number j, if variable (v) appears as an argument in the function (k), and there is no computer operation between the sequence i and the sequence j for which v is a variable, b) constructing for sequence numbers i and j, where i=j, a directed line segment from the variable vertex (sn,v) to the function vertex (sn,k) if variable (v) appears as an argument of function (k), and c) constructing, for each pair of computer operations sn, sp, sp>sn, a directed line segment from the variable vertex (sn,v) to the variable vertex (sp,v) if a same variable (v) is in both operations and the same variable (v) does not appear in a computer operation between computer operations sn, sp, and determining a line segment representative of a computer operation that is not contained in a loop including directed line segments based on a), b), and c) as an idempotent operation, and wherein the processing unit is further configured to reorder the initial sequence to form a reordered sequence comprising a first sub-sequence of the computer operations followed by a second sub-sequence of the computer operations, the second sub-sequence comprising only the one or more idempotent operations, wherein the reordered sequence is a computationally efficient representation of the initial sequence that improves efficiency of the transaction in the event of failure.