Patent ID: 8378495

Claim:
An integrated circuit (IC), comprising: a substrate having a semiconductor top surface having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level having inter-level dielectric (ILD) layers between respective ones of said plurality of metal interconnect levels, and a bottom surface; a plurality of through substrate vias (TSVs) extending from a TSV terminating metal interconnect level selected from said plurality of metal interconnect levels downward to said bottom surface, said plurality of TSVs comprising an electrically conductive filler material surrounded by a dielectric liner, said TSVs defining a projected volume, said projected volume comprising a projected area defined by an area of said electrically conductive filler material of said TSVs and a projected height extending upwards from said TSV terminating metal interconnect level to at least one of said plurality of metal interconnect levels above said TSV terminating metal interconnect level, and a projected sidewall surface along sidewalls of said projected volume:, and a crack suppression structure (CSS) for at least a protected portion of said plurality of TSVs, said CSS comprising a lateral CSS portion positioned lateral to said projected volume formed as vias in at least a first of said ILD layers which are filled with a crack suppression material different from a dielectric material for said first ILD layer, said lateral CSS portion enclosing at least 80% of said projected sidewall surface.