Patent ID: 8119484

Claim:
A method of forming a memory, comprising: forming a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions, the nanofin transistor including a nanofin structure with a sublithographic cross-sectional dimension and a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the nanofin structure and separated from the nanofin structure by the surrounding gate insulator, wherein forming the nanofin structure includes forming a sidewall spacer with a desired thickness to provide the nanofin structure with a sublithographic cross-sectional thickness that corresponds to the desired thickness of the sidewall spacer, wherein the nanofin structure is formed directly beneath the sidewall spacer; connecting a data-bit line to the first source/drain region; connecting at least one word line to the surrounding gate of the nanofin transistor; and forming a stacked capacitor positioned above the nanofin structure and connected between the second source/drain region and a reference potential.