Patent ID: 7519796

Claim:
A single chip multithreaded processor comprising: at least one processor core comprising a plurality of resources for forming an integer pipeline that generates store instructions, said processor core comprising: an instruction fetch unit for providing instructions to said integer pipeline, said instruction fetch unit comprising a first counter for counting only store instructions wherein the first counter is arranged to increment each time a store instruction is issued to the integer pipeline; and a store buffer for buffering only store instructions and issuing said store instructions in order, wherein the store buffer is arranged to issue a dequeue signal to the instruction fetch unit each time a store instruction is deallocated from the store buffer; wherein said instruction fetch unit is arranged to decrement the first counter each time a dequeue signal is received from the store buffer and halt issuance of instructions to the integer pipeline while the first counter is above a threshold value; wherein the instruction fetch unit further comprises a second counter which is arranged to increment each time a store instruction commits to the store buffer in the integer pipeline and decrement each time a store instruction is deallocated from the store buffer; and wherein the processor is arranged to copy the second counter to the first counter when a thread is flushed from the integer pipeline, and wherein the processor is arranged to flush the thread from the pipeline by removing only store instructions from the pipeline that are not committed to the store buffer.