Patent ID: 7385863

Claim:
A semiconductor memory device comprising: a first addressable memory array having a plurality of memory regions obtained by dividing the first memory array by one or more word lines; a second addressable memory array having a plurality of memory groups for storing defective memory address information, wherein each memory group corresponds to a memory region and stores information that designates a defective memory included in the corresponding memory region; a controlling unit for causing the second addressable memory array to output the defective memory address information stored in the memory group corresponding to one of said memory regions whenever a memory address for accessing a memory included in that memory region is input; at least one redundant memory; an access switching unit for specifying a defective memory according to the defective memory address information read out from said second memory array and switching an access operation so that said redundant memory is accessed instead of the specified defective memory; and a plurality of redundant memories, each of which corresponds to the each memory region on said first memory array and becomes accessible when a memory address for accessing a memory included in the corresponding memory region is input, and wherein said controlling unit executes processing for causing said first memory array, said second memory array, and said redundant memory to output the respective data stored therein in parallel when the memory address for accessing a memory on said first memory array is input.