Patent ID: 8222067

Claim:
A method of manufacturing a memory device, comprising: forming a bit line in a first direction on a substrate; forming a first interlayer insulating film on the bit line; forming a lower word line and a first sacrifice layer in a second direction intersecting the first direction of the bit line on the first interlayer insulating film; forming a spacer on a sidewall of the lower word line and the first sacrifice layer; removing the first interlayer insulating film exposed to the spacer on the bit line and thus forming a contact hole to which the bit line is selectively exposed; forming a pad electrode inside the contact hole; forming a cantilever electrode coupled between an upper part of the pad electrode and an upper part of the first sacrifice layer in the first direction; and forming a second sacrifice layer, trap site and upper word line in the second direction on the cantilever electrode formed on the lower word line, wherein the spacer includes one of silicon nitride and polysilicon and the first sacrifice layer and the second sacrifice layer include one of the same material and a different material as and from the spacer.