Patent ID: 7237000

Claim:
A method for increasing data processing efficiency of an apparatus when performing a conditional subtract instruction of a first number and a second number, said method comprising: loading said first number in a first register; left-shifting said second number by M-bits to generate a shifted second number, wherein M represents a number of bits in said first number; shifting said first number stored in said first register to the left by one bit to generate a shifted first number; subtracting said shifted second number from said shifted first number via an arithmetic logic unit to generate a temporary value; adding a 1 to said temporary value; determining if said temporary value is greater than or equal to zero; storing a result of adding 1 to said temporary value in said first register if said temporary value is greater than or equal to zero; and storing said shifted first number in said first register if said temporary value is less than zero, wherein said steps of loading, left-shifting, shifting, adding, determining, and storing cause the apparatus to more efficiently perform the conditional subtraction instruction.