Patent ID: 7149764

Claim:
An apparatus in a random number generator, comprising: first and second counters, configured to store a zero bit count and a one bit count, respectively, that indicate a current number of contiguous zero and one bits, respectively, detected in a series of random bytes generated by the random number generator; first and second adders, coupled to said first and second counters, for generating first and second sums, wherein said first sum is of said zero bit count and a number of leading zeros in a next random byte generated by the random number generator, wherein said second sum is of said one bit count and a number of leading ones in said next random byte; first and second comparators, coupled to respective said first and second adders, configured to compare respective said first and second sums with a counting number N, and to each generate a respective signal to indicate whether said respective sum is greater than said N; logic, coupled to receive said respective signals, configured to cause said first counter to retain said zero bit count if either of said respective signals indicates said respective sum is greater than said N, and to cause said second counter to retain said one bit count if either of said respective signals indicates said respective sum is greater than said N; and a buffer, coupled to said first and second comparators, for storing a plurality of random data bytes, wherein the apparatus writes said next random byte into said buffer if neither of said respective signals indicates said respective sum is treater than said N, wherein the apparatus discards said next random byte if either of said respective signals indicates said respective sum is greater than said N.