Patent ID: 8736318

Claim:
A multiphase clock divider, comprising: a reference clock generator, for generating a plurality of reference clocks, wherein frequencies of the plurality of reference clocks are the same and a specific phase difference exists between the reference clocks; and at least one output clock generator, comprising: a first multiplexer, coupled to the reference clock generator, for selecting to output one of the plurality of reference clocks as a selected reference clock; a second multiplexer, for selecting to output an input clock from among a first group of a plurality of input clocks as a first selected input clock; a third multiplexer, for selecting to output an input clock from among a second group of the plurality of input clocks as a second selected input clock; a first flip-flop, comprising: a data input terminal, coupled to the first multiplexer, for receiving the selected reference clock; a clock input terminal, coupled to the second multiplexer, for receiving the first selected input clock; and a data output terminal, for outputting a first sampling clock; a second flip-flop, comprising: a data input terminal, coupled to the data output terminal of the first flip-flop, for receiving the first sampling clock; a clock input terminal, coupled to the third multiplexer, for receiving the second selected input clock; and a data output terminal, for outputting a second sampling clock; and a fourth multiplexer, coupled to the data output terminal of the first flip-flop and the data output terminal of the second flip-flop, for selecting to output the first sampling clock or the second sampling clock to generate an output clock.