Patent ID: 7386710

Claim:
A hardware system comprising: a sequence processor (SP) configured to control at least one processing element (PE) which receives instructions and interrupt information from the SP; a PE compute register file (CRF); a plurality of PE functional units coupled to said PE compute register file (CRF); and a PE condition generation unit (CGU) configured to provide local PE condition information for controlling each local PE instruction sequence; wherein when an interrupt is detected in the SP and is acknowledged, all PE instructions in a decode phase are allowed to proceed through execute; one-cycle PE instructions are allowed to complete and update their target registers and flags; and any two-cycle PE instructions are allowed to complete, but based on the interrupt information their output which may include output data, output register address and flag information is saved in a set of special purpose interrupt forwarding registers and no update is made to the PE CRF or PE status registers.