Patent ID: 7406632

Claim:
In a computer system having a plurality of processor boards, each of the processor boards generating a plurality of error signals in response to different conditions on the processor boards, and a parallel transaction bus connected to each of the processor boards, an error reporting network comprising: a signal line, separate from the parallel transaction bus, and connected to each of the processor boards; and each of the processor boards containing: means for generating an error detection signal; control means responsive to the error detection signal for generating in sequence a plurality of control signals; means responsive to one of the control signals for collecting and storing the plurality of error signals; means responsive to one of the control signals for generating an error notification signal and for communicating the error notification signal to each of the processor boards over said signal line; means responsive to one of the control signals for communicating the plurality of error signals to each of the processor boards serially over said signal line; storage means; further control means responsive to the error notification signal for generating in sequence a plurality of further control signals; means responsive to one of the further control signals for converting to parallel form and storing in said storage means as error information the plurality of error signals communicated from each of the processor boards serially over said signal line; and means connected to said storage means for reading out the error information.