Patent ID: 7313715

Claim:
A memory system having a stub configuration comprising: a controller for generating a first clock signal, a control signal, an address signal and data signals on a data bus, the data bus, first clock signal, control signal, and address signal being arranged on a system bus in a stub configuration; a memory module including memory devices coupled to the controller via the system bus; a second clock signal generator independent of both the controller and the memory module for generating a second clock signal independently from the first clock signal that is sourced at a location that is beyond an outermost memory module on the system bus relative to the controller, the memory module receiving the first clock signal, the second clock signal and the control signal that includes a read or write command; the first clock signal propagating from the controller to the memory module in a first direction of propagation, and the second clock signal propagating from the memory module to the controller in a second direction of propagation; the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in synchronization with the first clock signal; and the memory module, in response to the read command, initiating a read operation for reading data from the memory to the data bus in response to the second clock signal, the controller receiving the data signals on the data bus in response to the second clock signal during the read operation.