Patent ID: 7473586

Claim:
A method of packaging a semiconductor integrated circuit, comprising: providing a sheet of metal foil; forming a plurality of cavities in a first surface of the sheet of metal foil; plating the cavities with a conductive metal; forming an insulating film over the metal foil first surface and the plated cavities; forming a plurality of vias in the insulating film, wherein the vias contact respective ones of the plated cavities; plating the vias with a conductive metal; forming a solder resist film over the insulating film and the plated vias; processing the solder resist film to form exposed areas above the vias; plating the exposed areas above the vias with a conductive metal; attaching a bumped semiconductor die to the first surface of the metal foil, wherein the die bumps contact respective ones of the plated, exposed areas thereby electrically connecting the die to the plated cavities; and removing the sheet of metal foil so that outer surfaces of the plated cavities are exposed, whereby said plated cavity outer surfaces form electrical interconnects to the semiconductor die.