Patent ID: 8841698

Claim:
A foundation element for JFET semiconductor devices that may be operated at temperatures of at least 500° C. for a duration of 10,000 hours, the foundation element comprising: A wide band gap material serving as a substrate; A first layer of p-type material on top of the substrate; A second layer of n-type material on top of the first layer; A third layer of p+ type material on top of the second layer; A first masking layer on top of the third layer wherein etching removes all of the third layer except for a portion laying under the first masking layer so as to form a first element (comprised of a portion of the third layer) and a second element (comprised of a portion of the second layer) of the p+ gate region; and A self-aligned ion implant of an n-type dopant, carried out at room temperate, and implanted into a self-aligned implant region provided at the union of both the first and second elements of the p+ gate region.