Patent ID: 7411820

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array comprising first even and odd strings of nonvolatile memory cells connected to a first even bit line and a first odd bit line, respectively, second even and odd strings of nonvolatile memory cells connected to a second even bit line and a second odd bit line, respectively, wherein the first even bit line and the first odd bit line are selectively connected to a first common bit line during programming and read operations, and wherein the second even bit line and the second odd bit line are selectively connected to a second common bit line during programming and read operations; a page buffer coupled to the memory array through the first and second common bit lines and configured to drive the first and second common bit lines to map first through third bits to levels of threshold voltage distributions of first and second memory cells forming a pair; and, a row decoder configured to control a word line of a selected memory cell of the memory array; wherein the first and second memory cells forming the pair are connected to the same word line and are arranged in the first and second even strings, respectively, or in the first and second odd strings, respectively.