Patent ID: 8266466

Claim:
A time synchronization system comprising: a plurality of cards residing in a chassis, the chassis running software that selects, from the plurality of cards, a card to be the master card, the plurality of cards each including a clock source and a counter, wherein the master card transmits on a first bus line, asynchronously and serially on a regular periodic basis, counter value information to the plurality of cards including to the master card, wherein one or more of the plurality of cards includes one of a packet accelerator card, a packet services card, a telephony services card, and a switch processing card, wherein one or more of the plurality of cards includes one of an access gateway, a packet data serving node, a foreign agent, a home agent, a base station, an access network, and a session control function, and wherein the master card further transmits counter value information to the plurality of cards on a second bus line.