Patent ID: 8792263

Claim:
An apparatus comprising: a first set of data lines; a second set of data lines; memory cells located in different levels of the apparatus and arranged in memory cell strings between the first and second sets of data lines, the first set of data lines used to retrieve information from a first memory cell set of the memory cells, and the second set of data lines used to retrieve information from a second memory cell set of the memory cells; a first transistor coupled between a first memory string of the memory cell strings and a first data line of the first set of data lines; a first select line to provide a signal to control the first transistor; a second transistor coupled between a second memory cell string of the memory cell strings and a second data line of the second set of data lines; a second select line to provide a signal to control the second transistor; and a module configured to select the first and second memory cell strings in an operation of the apparatus, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently store information into the first and second memory cells.