Patent ID: 6864506

Claim:
An SRAM cell having first and second access transistors, first and second drive transistors, and first and second load transistors on the same semiconductor substrate, comprising: a first local interconnection connected between first terminals of the first access transistor, the first load transistor, and the first drive transistor, and gates of the second load transistor, and the second drive transistor, electrically; a second local interconnection connected between first terminals of the second access transistor, the second load transistor, and the second drive transistor, and gates of the first load transistor, and the first drive transistor, electrically; a first interlayer insulating film formed on an entire surface having first contact holes exposing parts of second terminals of the first and second access transistors, the first and second load transistors, and first and second drive transistors; a first metal interconnection connected between second terminals of the first and second access transistors, first and second load transistors, and first and second drive transistors through the first contact holes, electrically; a second interlayer insulating film formed over an entire surface of the semiconductor substrate, the second interlayer insulating film having second contact holes exposing parts of second terminals of the first and second access transistors and first and second drive transistors; and a second metal interconnection connected to the second contact holes.