Patent ID: 8421489

Claim:
A semiconductor device, comprising: an internal power-supply circuit which produces an internal voltage potential; an external terminal; a test terminal which transfers a test mode signal; an inverter which receives the test mode signal and outputs an inverted test mode signal; a first transfer circuit which includes a first transistor of a first conductivity type coupled between the internal power-supply circuit and a first node and having a control gate supplied with the inverted test mode signal, and a second transistor of a second conductivity type coupled in parallel with the first transistor between the internal power-supply circuit and the first node and having a control gate supplied with the test mode signal; a resister coupled between the first node and a second node; a second transfer circuit which includes a third transistor of the first conductivity type coupled between the external terminal and the second node and having a control gate supplied with the inverted test mode signal, and a fourth transistor of the second conductivity type coupled in parallel with the third transistor between the external terminal and the second node and having a control gate supplied with the test mode signal; and a clamp element which clamps a potential on the second node.