Patent ID: 8563396

Claim:
A method of fabricating an enhanced 3D device stack comprising the steps of: fabricating silicon on insulator (SOI) circuits on a first SOI wafer with a buried oxide (BOX) layer; providing a first set of middle of the line (MOL) interconnects for said SOI circuits; patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer; filling and planarizing said vias and said alignment marks with a sacrificial fill material; completing a first set of BEOL interconnects to connect said SOI circuits; providing a first set of bonding pad level atop said first set of BEOL interconnects; fabricating a second device wafer with a set of circuits, second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads; flipping said first SOI wafer, positioning atop said second device wafer such that said first and said second set of bonding pads are aligned to each other; bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads; removing said silicon substrate from said first SOI wafer by grinding, polishing or etching or a combination thereof and stopping on said BOX layer and exposing said sacrificial material filled vias and alignment marks; etching out said sacrificial material, refilling and planarizing said vias and alignment marks with a conductive fill material; fabricating a third set of interconnects atop the BOX layer using said conducting material filled alignment marks as reference and connecting the structure so obtained to the exposed ends of said filled vias; and providing input out pads and solder connection means atop the top surface of said third set of interconnects to enable connections to a packaging substrate.