Patent ID: 8802465

Claim:
A method comprising: providing a wafer assembly comprising a plurality of semiconductor dies on a carrier substrate, each die comprising a multi-layer epitaxial structure; depositing a plurality of metal layers on the semiconductor dies configured as a metal substrate, the metal layers comprising: a first stress-reducing layer on the epitaxial structure comprising a first material having a first hardness and a first thickness, with the first material and the first thickness selected to minimize cracking of the epitaxial structure; a harder layer on the first stress-reducing layer comprising a second material having a second hardness greater than the first hardness and a second thickness, with the second material and the second thickness selected to allow handling of the wafer assembly without cracking of the epitaxial structure; and a second stress-reducing layer on the harder layer comprising a third material having a third thickness, with the third material and the third thickness selected to compensate for stress from depositing of the harder layer; removing the carrier substrate from the wafer assembly; and manipulating the wafer assembly via the metal substrate for further processing.