Patent ID: 7336539

Claim:
A method of operating a flash memory cell, wherein the flash memory cell comprises a substrate, a first conductive type deep well disposed in the substrate, a second conductive type well disposed within the first conductive type deep well, and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the substrate, wherein the flash memory cell further comprises a second conductive type source region and a second conductive type drain region disposed in the substrate on each side of the stacked gate structure respectively, a select gate disposed between the stacked gate structure and the second conductive type source region, a first gate dielectric layer disposed between the select gate and the stacked gate structure, a second gate dielectric layer disposed between the select gate and the substrate and a first conductive type shallow doped region disposed in the second conductive type well underneath the stacked gate structure and the select gate, wherein the second conductive type source region is disposed in the first conductive type shallow doped region, wherein the flash memory cell further comprises a first conductive type deep doped region disposed in the second conductive type well on one side of the stacked gate structure but adjacent to the first conductive type shallow doped region, wherein the second conductive type drain region is within the first conductive type deep doped region; and a conductive plug disposed in the substrate passing downward through the second conductive type drain region with a portion buried within the first conductive type deep doped region, wherein the operating method comprising: applying a first positive voltage to the second conductive type source region and the second conductive type drain region, applying a first negative voltage to the control gate and setting the select gate and the first conductive type deep well to 0V in programming the flash memory cell; applying a second positive voltage to the control gate, applying a second negative voltage to the second conductive type source region and the first conductive type deep well, setting the second conductive type drain region to a floating state and setting the select gate to 0V in erasing data from the flash memory cell; and applying a third positive voltage to the second conductive type source region, applying a fourth positive voltage to the control gate and the select gate, setting the first conductive type deep well and the second conductive type drain region to 0V in reading data from the flash memory cell.