Patent ID: 7470942

Claim:
A thin film transistor array, comprising: a substrate, having a display region and a peripheral circuit region; a plurality of data lines and scan lines, disposed in the display region for defining a plurality of pixel regions; a plurality of pixel structures, disposed in the pixel regions and driven by the data lines and the scan lines, wherein each pixel structure comprises: a top-gate thin film transistor, electrically connected to one of the data lines and one of the scan lines; a pixel electrode, disposed over and electrically connected to the top-gate thin film transistor; a first shorting bar, disposed in the peripheral circuit region; a second shorting bar, disposed in the peripheral circuit region; a plurality of first island structures, disposed on the substrate and between the scan lines and the first shorting bar; a plurality of second island structures, disposed on the substrate and between the data lines and the second shorting bar; a gate insulating layer, disposed on the substrate and covering the first island structures, the second island structures, and semiconductor layers of the top-gate thin film transistors; a dielectric interlayer, disposed on the gate insulating layer and covering the scan lines, the first shorting bar, and gates of the top-gate thin film transistors, wherein the gate insulating layer and the dielectric interlayer have a plurality of first contact windows over the scan lines, the first island structures, and the first shorting bar, and have a plurality of second contact windows over the second island structures, wherein the data lines and the second shorting bar are disposed on the dielectric interlayer and extends over the second island structures to be electrically connected to the second island structures via the second contact windows; a plurality of first connecting lines, disposed on the dielectric interlayer and electrically connected between the first island structures and the scan lines via the first contact windows; a plurality of second connecting lines, disposed on the dielectric interlayer and electrically connected between the first island structures and the shorting bar via the first contact windows; a passivation layer, covering the data lines, the second shorting bar, and source/drains of the top-gate thin film transistors, wherein the passivation layer has a plurality of third contact windows over the first connecting lines and the second connecting lines, and has a plurality of fourth contact windows over the data lines and the second shorting bar; a plurality of first resistance lines, disposed on the passivation layer and electrically connected between one of the first connecting lines and one of the second connecting lines via the third contact windows respectively; and a plurality of second resistance lines, disposed on the passivation layer and electrically connected between one of the data lines and the second shorting bar via the fourth contact windows respectively.