Patent ID: 7570523

Claim:
A method useful for a passive element memory cell array including a first plurality of array blocks, each array block comprising a respective plurality of memory cells, each memory cell coupled to an associated word line and bit line, each respective plurality of memory cells generally bounded by circuits, structures, or gaps which break the contiguous, repetitive pattern of word lines and bit lines and their associated memory cells, said method comprising: simultaneously selecting, in a first mode of operation, a word line in a first array block within a first group of said first plurality of array blocks, and a word line in a second array block within a second group of said first plurality of array blocks; and simultaneously coupling, in the first mode of operation, one or more selected bit lines in the first array block to corresponding lines of a first data bus that generally spans the first plurality of array blocks, and one or more selected bit lines in the second array block to corresponding lines of a second data bus that generally spans the first plurality of array blocks.