Patent ID: 8352752

Claim:
A device comprising: a plurality of standard logic cells; a first plurality of circuits that implements a function and that comprises a portion of the plurality of standard logic cells; a second plurality of circuits that comprises portions of the plurality of standard logic cells that are not included in the first plurality of circuits that implements the function, wherein each circuit in the second plurality of circuits is adapted to store either a first value or a second value and is configured to persistently store the first value; a detection circuit that determines whether a plurality of the circuits in the second plurality of circuits is concurrently storing the second value including a tuning circuit comprising a counter that counts how many of the second plurality of circuits are storing the second value and a tunable threshold register that indicates a threshold number of the second circuits that can store the second value concurrently without triggering a countermeasure; and a countermeasure circuit that initiates a first protective measure when the detection circuit determines that a first number of the second plurality of circuits is storing the second value where the first number is greater than the threshold number, and a second protective measure, which is different than the first protective measure, when the detection circuit determines that a second different number of circuits in the second plurality of circuits is also coincidentally storing the second value where both the first and the second protective measures include one or more measures to protect the first plurality of circuits.