Patent ID: 7073041

Claim:
A system for the translation of one or more virtual addresses into one or more accesses to one or more physical memories, comprising: an input interface to the one or more physical memories, wherein an address of an element of a memory of the one or more physical memories is represented as a point in a Cartesian coordinate system and consecutive points in the Cartesian coordinate system are operable to represent memory addresses corresponding to elements from different physical memories of the one or more physical memories; a virtual memory translator coupled to the input interface, wherein the virtual memory translator is operable to translate one or more points in the Cartesian coordinate system into one or more corresponding physical memory addresses, wherein the virtual memory translator further comprises: a split adjust block that determines the Cartesian coordinates of one or more selected points in the Cartesian coordinate system relative to the particular point; a Cartesian-to-linear address conversion mechanism; and a memory enable mechanism coupled to the Cartesian-to-linear address conversion mechanism that is operable to output the physical memory address of each of the selected points; a physical memory interface to the one or more physical memories, said physical memory interface coupled to the virtual memory translator and operable to perform one or more of: read one or more read data located in one or more physical memory addresses corresponding to one or more points in the Cartesian coordinate system; and write one or more write data to the one or more physical memory addresses corresponding to one or more points in the Cartesian coordinate system.