Patent ID: 8223535

Claim:
A phase change memory device, comprising: a memory array of memory cells arranged in a plurality of rows and columns, each memory cell including a phase change memory element and a selection element, the array comprising a plurality of wordlines and a plurality of bitlines, the memory cells of each row being coupled to a respective wordline and the memory cells of each column being coupled to a respective bitline, a bitline biasing unit; a bitline selection unit coupled to said bitlines and said bitline biasing unit and configured to connect a selected bitline to the bitline biasing unit and disconnect deselected bitlines from the bitline biasing unit in an operative condition of the memory device; and a bitline discharge unit coupled to said bitlines, the bitline discharge unit including: a voltage regulation unit, and a plurality of bitline discharge switches, each bitline discharge switch being coupled between the voltage regulation unit and a respective bitline and controlled in said operative condition to connect the deselected bitlines to the voltage regulation unit and disconnect the selected bitline from the voltage regulation unit, wherein the memory array comprises a plurality of tiles, the bitline discharge unit includes a regulated voltage bus coupled to the bitline discharge switches, and the memory device includes a periphery portion extending laterally to said tiles, the voltage regulation unit being arranged in the periphery portion, and the regulated voltage bus comprises a global voltage bus extending through the memory array from the voltage regulation unit and a plurality of local voltage buses extending between the global voltage bus and the tiles, respectively.