Patent ID: 8804401

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including one or more first wires, one or more memory cells stacked on the first wires, and one or more second wires intersecting the first wires on the memory cells, the memory cells brought into a low resistance state by application of voltage of a first polarity, and brought into a high resistance state by application of voltage of a second polarity different from the first polarity; and a control circuit configured to cause the memory cell to transition between the high resistance state and the low resistance state through the first wires and the second wires, wherein when performing a set operation for setting the memory cell to the low resistance state so that a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit is configured to repeat: applying a first voltage of the first polarity to the memory cell; a verify read to verify whether the resistance value of the memory cell has become lower than the predetermined resistance value; after the verify read, applying a second voltage of the second polarity to the memory cell; and if the verify read indicates the resistance value of the memory cell has not become lower than the predetermined resistance value, applying the first voltage again.