Patent ID: 7213108

Claim:
An information processing apparatus including processor means for executing an operation, the information processing apparatus comprising: a plurality of functional units for performing functional processes; storage means for storing said instruction and data for said processor means to execute said operation and including input/output registers for transferring said instruction and data between said processor means and said functional units; first and second transfer means for transferring said instruction or data between said processor means and said storage means; first address translation means for translating an instruction virtual address designated by said processor means into a physical address of said storage means; and second address translation means for translating a data virtual address including the virtual addresses of said data and said input/output registers designated by said processor means into a physical address of said storage means, wherein each of said first and second transfer means includes an independent respective first and second virtual address space each including virtual addresses, wherein the virtual addresses in the first virtual address space overlap with the virtual addresses in the second virtual address space; said first and second address translation means translate said virtual address space of said respective first and second transfer means into a single physical address space; the data virtual address space of said input/output registers and data are divided and disposed in a plurality of address areas so that the virtual addresses of an instruction and corresponding data and input/output registers are disposed at a near distance; wherein, said first and second transfer means include an instruction bus for transferring said instruction and a data bus for transferring said data; and a difference between a virtual address of an instruction accompanying an access to said first and second transfer means and a virtual address of data accessed by said instruction is equal to or shorter than a distance which can be directly designated as a relative address by an operand of the instruction; and further comprising: a cache, provided for each of said first and second transfer means, said cache using said virtual address as a tag, wherein said virtual address space includes virtual addresses in such a manner that a border between a virtual address of said instruction and a virtual address of said data becomes a line border of said cache.