Patent ID: 7084458

Claim:
A semiconductor device comprising: a gate structure including a first vertical surface, a second vertical surface, and a horizontal surface; a silicide formed on said horizontal surface, a first upper portion of said first vertical surface, and a second upper portion of said second vertical surface, wherein said silicide on said horizontal surface lowers a gate resistance of said semiconductor device, and wherein said silicide on said first upper portion and said second upper portion additionally lower said gate resistance; a drain having a triple LDD (lateral diffused dopants) structure; and a source having a triple LDD (lateral diffused dopants) structure, wherein said triple LDD structures of said source and said drain are formed by a single implant process that utilizes a first sacrificial spacer adjacent to said first vertical surface, wherein said first sacrificial spacer has a first thickness and a second thickness that is greater than said first thickness and that abuts said first vertical surface and a second sacrificial spacer adjacent to said second vertical surface, wherein said second sacrificial spacer comprises a third thickness and a fourth thickness that is greater than said third thickness and that abuts said second vertical surface.