Patent ID: 8415983

Claim:
A digital phase comparator comprising: a first circuit unit including a first delay element array delaying a first clock signal at regular intervals, and a first group of data holding circuits generating and producing first phase difference signals obtained by sampling a second clock signal with the use of the first clock signal and a first group of delayed signals obtained by delaying the first clock signal with the first delay element array; a second circuit unit generating a first signal by performing a logic operation on the first phase difference signals; and a third circuit unit including a second delay element array delaying the second clock signal at first regular intervals, and a third delay element array delaying the first signal at second regular intervals, and further including a second group of data holding circuits generating and producing second phase difference signals obtained by sampling a second group of delayed signals obtained by delaying the second clock signal with the second delay element array, with the uses of a third group of delayed signals obtained by delaying the first signal with the third delay element array, wherein the first phase difference signals and the second phase difference signals are digital phase difference information indicating a phase difference between the first clock signal and the second clock signal.