Patent ID: 8111233

Claim:
A display driver circuit configured to output a gradation voltage to a column selection line of a display panel, the circuit comprising: a shift register configured to sequentially shift a sampling start signal to generate a sampling signal for each pixel; a first register configured to sequentially perform sampling, with the sampling signal, on gradation data inputted through a gradation-data signal line, and store a first sampled data; a second register configured to perform sampling, with a load signal, on the first sampled data stored in the first register, and store a second sampled data which is converted and output as the gradation voltage; and a delay-time adjusting section configured to receive a data clock through a data-clock signal line, adjust a delay time of the data clock while receiving input of the load signal to set a phase difference between the data clock and the gradation data to a predetermined value, and hold and output the adjusted delay time as a shift clock for the shift register after the completion of the input of the load signal.