Patent ID: 6982456

Claim:
A nonvolatile semiconductor memory device comprising: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the first surface region; a control gate electrode formed on an area of the first surface region with the first insulating film interposed therebetween; a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween and opposed to the second surface region and the step side region with a third insulating film interposed therebetween; a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and an impurity region formed in the first surface region and step side region of the semiconductor substrate to have an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region, wherein the impurity region is in contact with the third insulating film formed on the step side region.