Patent ID: 8375347

Claim:
A method of designing an integrated circuit (“IC”), comprising: placing an IC design, wherein the IC design includes a first element, a second element, and a path coupling the first and second elements; routing the IC design; obtaining at least one of resistivity data and capacitance data related to the path; obtaining timing data related to the path; determining whether the path is a long path or a short path, wherein determining whether the path is the long path or the short path includes determining whether the path has only one path segment extending from only a first element to only a second element and determining that the path is the short path when the path has only one path segment extending from only the first element to only the second element, wherein the long path having more path segments than the short path; determining whether the path is a setup-critical path or hold-critical path; determining, by using a computer, a critical dimension (“CD”) bias to be applied to the path based upon at least one of the resistivity data, the capacitance data, and the timing data and based upon whether the path is determined the short path or the long path and whether the path is determined the setup-critical path or the hold-critical path; and modifying the IC design, wherein the modifying includes applying the CD bias to the path.