Patent ID: 8040728

Claim:
A semiconductor integrated circuit, comprising: a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity diffused region being coupled to one of a source and a drain of the selecting transistor; a first electrode formed above the semiconductor substrate with an insulating film therebetween, the first electrode receiving a control signal and part of the first electrode having an opening; a second electrode formed above the first electrode so as to oppose the first electrode with an insulating film therebetween, the second electrode having a protrusion which opposes the impurity diffused region with a tunnel film therebetween and projects toward the semiconductor substrate through the opening of the first electrode, and storing information based on an applied voltage; and a sensing transistor operating based on charges accumulated in the second electrode, so as to sense the information stored in the memory cell, wherein the entire first electrode is sandwiched between the second electrode and the semiconductor substrate in cross-section view.