Patent ID: 8611368

Claim:
A multiprocessor computer system comprising: a managed resource; a programmable hardware register; at least one of programs and other entities that need to access the managed resource; a control mechanism operational to check an identifier tagged to commands and/or informational packets destined to access the managed resource, the control mechanism operational to determine a value in the programmable hardware register based on the identifier and distribute the commands and/or informational packets to the managed resource based on the value in the programmable hardware register, the value indicating a distribution of the commands and/or informational packets substantially evenly over an operational time period from a source to the managed resource, wherein the control mechanism comprises a counter, and wherein the value in the programmable hardware register indicates a bit position of the counter wherein a transition of the bit position based on a corresponding number of clock cycles controls issuance of the commands and/or informational packets to the managed resource; and a zero count detection and decrementer receiving an output from the counter and providing a feedback to the counter such that a count value is decremented by one whenever it receives an indication that a command of a given class has been issued, and wherein when the count value reaches zero, an output signal is sent to the control mechanism issuing the given class command to prevent of any further access attempts of that class to the managed resource until a next operational window.