Patent ID: 8129788

Claim:
A trigger circuit comprising: a gated-diode/metal-oxide-semiconductor (MOS) capacitor trigger device formed in an N-type well region of a P-type substrate and connected to a PNPN silicon controlled rectifier SCR formed partly in the well region and partly in the substrate, wherein a first portion of a gate of the gated-diode/MOS capacitor is separated from the well region by a gate dielectric and a second portion of the gate of the gated-diode/MOS capacitor is separated from the well region by a field oxide region and not by the gate dielectric, the field oxide region also separating the gate of the gated diode/MOS capacitor from a first P+ type region of the SCR in the N-type well region, wherein the SCR includes the first P+ diffusion region and a first N+ tap in the N-type well both connected to a protected ESD node, and a second P+ diffusion region and a second N+ tap both in the P-type substrate and connected to a negative power supply, Vss; a resistor-capacitor R/C network including a capacitor, C, through which a gate node of the gated-diode/MOS capacitor is coupled to the negative power supply, Vss, and a resistance element, R. 1 through which the gate node is coupled to the protected ESD node; wherein the gated-diode/MOS capacitor is configured to inject electrons into the N-type well region when a voltage on the protected ESD node reaches a predetermined trigger voltage causing a well current to flow, charging the MOS capacitor to trigger the SCR to transfer charge from the protected node to Vss; and wherein an area A of the gated-diode/MOS capacitor, and a distance, L 1 , isolating the SCR device from the gated-diode/MOS capacitor in the substrate are selected to define the predetermined trigger voltage.