Patent ID: 7227784

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of nonvolatile memory cells constituting an entirety or part of a memory cell array; and a control circuit configured to perform a first block erase operation that erases the plurality of nonvolatile memory cells together in a lump such that threshold voltages of the memory cells are set lower than a first erase verify voltage, to perform a first erase-degree check as to whether a threshold voltage of each of the nonvolatile memory cells is lower than a first erase-degree-check voltage after the first block erase operation, to perform a first write-back operation in response to a check result indicating that the threshold voltage is lower than the first erase-degree-check voltage, the first write-back operation raising the threshold voltage above a first write-back-verify voltage that is higher than the first erase-degree-check voltage, and to perform a second block erase operation that erases the plurality of nonvolatile memory cells together in a lump after the first write-back operation such that the threshold voltages of the memory cells are set lower than a second erase verify voltage.