Patent ID: 8120024

Claim:
A semiconductor package, comprising: a substrate having top and bottom surfaces; a semiconductor chip mounted in a centrally located chip mounting area of the top surface; a first plurality of first test pads disposed in a peripheral area of the top surface surrounding the chip mounting area; a second plurality of first test pads disposed on the bottom surface, wherein each one of the first test pads has a first height above the respective top and bottom surfaces; and a plurality of second test pads disposed only on the bottom surface, wherein each one of the second test pads attaches a solder ball such that a combination of the second test pad and attached solder ball has a second height above the bottom surface greater than the first height, wherein the second plurality of first test pads is formed in a sub-group of first test pads under the chip mounting area, and wherein the plurality of second test pads is disposed on the bottom surface in an evenly spaced array, and at least one of the second test pads in the array is replaced by the sub-group of first test pads.