Patent ID: 6855597

Claim:
A method of manufacturing a DRAM cell comprising: forming an isolation layer on a region of a substrate to define an active region of the substrate, the active region having line shaped sub-regions; forming a word line pattern having pairs of line shaped portions on and crossing the active region; forming impurity regions in the active region by impurity implantation, the impurity regions including common drain regions respectively disposed between line shaped portions opposite of the pairs of line shaped portions of the word line pattern in the line shaped sub-regions of the active region, and source regions respectively disposed on both sides of the line shaped portions opposite the common drain regions in the line shaped sub-regions; forming word line spacers on side walls of the word line pattern; forming bit line pads and storage note pads respectively on the common drain regions and the source regions; forming a bit line pad protecting layer pattern, having line shaped portions disposed in parallel with the pairs of line shaped portions of the word line pattern, that covers the bit line pads; and forming storage nodes in direct contact on the storage node pads and electrically insulated from the bit line pads by the bit line pad protecting layer pattern.