Patent ID: 7919814

Claim:
A semiconductor device comprising: (a) an SOI substrate having a substrate layer, a buried insulating layer formed on the substrate layer, and a semiconductor layer formed on the buried insulating layer; (b) an integrated circuit formed on the semiconductor layer of the SOI substrate; and (c) a semiconductor element formed by processing the substrate layer of the SOI substrate, wherein the integrated circuit has: (b1) a plurality of MISFETs formed on the semiconductor layer; and (b2) a plurality of wirings in at least two wiring layers, which electrically connect the plurality of MISFETs, wherein the semiconductor element has: (c1) a fixing portion formed by processing the substrate layer; (c2) a structure mechanically connected to the fixing portion and movable; (c3) a cavity portion formed so as to surround the structure, and (c4) a cap hermetically sealing the structure, wherein the integrated circuit and the semiconductor element are electrically connected, and the electrical connection between the integrated circuit and the semiconductor element is achieved by a through-electrode formed inside the SOI substrate, wherein a first part of an uppermost wiring layer of the plurality of wirings is covered by an insulating film, wherein a second part of the uppermost wiring layer is exposed from the insulating film, and wherein the integrated circuit is arranged to be connected to an outside of the semiconductor device via the second part of the uppermost-layer wiring.