Patent ID: 6898106

Claim:
A memory device, comprising: at least one capacitor device for storing information on a basis of a hysteresis process and having a first electrode, a second electrode, first and second terminals connected to said first and second electrodes respectively, and an influence region with an influence medium disposed between said first and second electrodes; at least one transistor device connected to and accessing said capacitor device for reading and changing the information; a sense amplifier device for sensing an electromagnetic state of said capacitor device for accessing the information stored in said capacitor device; at least one plate line device electrically conductively connected to one of said first and second terminals of said capacitor device and to said sense amplifier device; a semiconductor substrate; and a bit line device, said bit line device and said second electrode of said capacitor device formed from a same material, and disposed in a same vertical layer region of said semiconductor substrate; said first electrode of said capacitor device being formed in a region of said plate line device.