Patent ID: 7777342

Claim:
A device comprising: a lower porous oxide layer formed over a semiconductor substrate having a conductive layer, the lower porous oxide layer including a via hole; a vacuum layer formed over the lower porous oxide layer, the vacuum layer including a bottom portion of a trench coupled with the via hole; an upper porous oxide layer formed over the lower porous oxide layer by interposing the vacuum layer between the lower porous oxide layer and the upper porous oxide layer, the upper porous oxide layer including a top portion of the trench coupled with the via hole, wherein the trench has a width larger than a width of the via hole such that the trench is connected with the via hole; and a metal interconnection formed in the via hole and the trench, respectively, wherein the vacuum layer directly physically contacting sidewall portions of the metal interconnection in the bottom portion of the trench, bottom surfaces of the upper porous oxide layer, and top surfaces of the lower porous oxide layer.