Patent ID: 8048735

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a first metal interconnect layer on a semiconductor substrate; forming an interlayer dielectric film on the first metal interconnected layer; forming an opening in a desired region of the interlayer dielectric film; forming a capacitance dielectric film in the opening so as to be in contact with the first metal interconnect layer; and forming a second metal interconnect layer in the opening and on the interlayer dielectric film, wherein the opening is formed in a region intended to form capacitance of the interlayer dielectric film placed on the first metal interconnect layer by performing a lithography process at least twice; and one of the two lithography processes is performed on the interlayer dielectric film remaining on the first metal interconnect layer with a thickness less than that of the interlayer dielectric film that is disposed between an upper surface of the first metal interconnect layer and a bottom of the second metal interconnect layer formed on the interlayer dielectric film at a periphery of the opening.