Patent ID: 8044516

Claim:
A semiconductor package comprising: a semiconductor chip having a bonding pad in a portion of a first surface thereof, and at least one of a data processing part and a data storage part formed at a vicinity of the first surface, wherein a receiving groove having a slit shape is formed in a second surface of the semiconductor chip, the second surface opposing the first surface; a through electrode passing through the semiconductor chip from the first surface to the second surface opposing the first surface, the through electrode being connected directly and electrically to the bonding pad; a redistribution pattern disposed at the second surface so as to minimize parasitic capacitance between the at least one of the data storage part and the data processing part and the redistribution pattern, the redistribution pattern being connected electrically to the through electrode and comprising a solder paste completely filling the slit shaped receiving groove formed in the second surface of the semiconductor chip; and a conductive ball electrically connected to the redistribution pattern; wherein the solder paste filled in the slit shaped receiving groove so as to form the redistribution pattern has a first melting point and the conductive ball includes a second solder having a second melting point that is lower than the first melting point.