Patent ID: 8683392

Claim:
A method of fabricating a semiconductor device, comprising: providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features; selecting, by using a computer, a subset of the features for decomposition as part of a double patterning process; designating a relationship between at least a first feature and a second feature of the subset of the features, the relationship dictating whether the first and second features are assigned to a same photomask or separate photomasks, wherein the designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask, wherein the pseudo feature includes a virtual assistant feature that is disposed between the first and second features in the layout plan; and assigning a color to the first feature and the second feature based on the pseudo feature, wherein the assigned color indicates a photomask to which the first feature and the second feature have been assigned.