Patent ID: 7158906

Claim:
A test system for conducting plural tests of a target with a computer in which the target transitions from an end state of one test to a start state of a subsequent test, the system comprising: a first storage device storing a plurality of test scenarios for testing the target sequentially; a second storage device storing a common intermediate state transition procedure in which the target is caused to transition from the end state of a first test to a common intermediate state and then the target is caused to transition from the common intermediate state to the start state of a second test that follows the first test, and in which the target is caused to transition from an end state of the second and subsequent tests to a start state of a following test by transitioning through the common intermediate state; and the computer having a central processing unit that executes the test scenarios from said first storage device and that executes the transitions through the common intermediate state from said second storage device, wherein tests are not conducted while the target is in the common intermediate state.