Patent ID: 7526688

Claim:
A device comprising: a memory cell array to store data; a register to store test data; and a decision circuit to invert the test data and to determine a failure of at least one memory cell within the memory cell array responsive to a comparison between the data and both of the test data and the inverted test data, where the decision circuit is operable to determine the failure responsive to a comparison of substantially all of the data stored in the memory cell array to the test data and responsive to a comparison of substantially all of the data stored in the memory cell array to the inverted test data, and the decision circuit includes: a first comparator to compare the data to the test data to generate a first result; a second comparator to compare the data to the inverted test data to generate a second result; and a combination circuit structured to combine the first result and the second result to generate a test signal indicating whether or not the memory cell array has at least one defective memory cell.