Patent ID: 7205820

Claim:
A circuit for voltage translation from a first voltage reference to a second voltage reference, the circuit comprising: an input coupled to a data input signal that is referenced to the first voltage reference; a switching circuit coupled to the second voltage reference for power, where the second voltage reference is independent of the first voltage reference, the switching circuit coupled to the input, the switching circuit configured to generate a data output signal referenced to the second voltage reference, where the data output signal changes with the data input signal when the switching circuit is enabled; and an enabling circuit coupled to the switching circuit for control of the switching circuit, the enabling circuit having an enable input referenced to the second voltage reference, where the enabling circuit is configured to be responsive to the enable input such that in an enabled state, the enabling circuit is configured to enable the switching circuit, and in a not enabled state, the enabling circuit is configured to set the data output signal to a predetermined level, wherein the enabling circuit further comprises: a PMOS transistor with a gate terminal, a drain terminal, and a source terminal, where the gate terminal is coupled to the enable input, where the drain terminal is coupled to a first portion of the switching circuit, and where the source terminal is coupled to the second voltage reference; and an NMOS transistor with a gate terminal, a drain terminal, and a source terminal, where the gate terminal of the NMOS transistor is coupled to the drain terminal of the PMOS transistor, where the drain terminal of the NMOS transistor is coupled to a second portion of the switching circuit different from the first portion, and where the source terminal of the NMOS transistor is coupled to a third voltage reference.