Patent ID: 8466645

Claim:
A motor control circuit comprising: a speed detecting section configured to detect a speed pulse having a frequency corresponding to a rotation speed of a motor; a generating section configured to generate torque command data based on the speed pulse detected by the speed detecting section; a motor driving control section configured to generate a PWM command signal based on the torque command data generated by the generating section to control driving of the motor; a first output section configured to output a first reference clock; and a second output section configured to output a second reference clock, wherein the generating section includes: a speed error detecting section configured to detect speed error data; a phase error detecting section configured to detect phase error data; and an addition section configured to add the speed error data and the phase error data to output torque command data, wherein the speed error detecting section includes: a first counter configured to count the first reference clock output from the first output section; a first latch circuit configured to latch a count value of the first counter with the speed pulse; and a first setting section configured to set a speed error detection range, wherein the speed error detecting section is configured to detect the speed error data based on the count value latched by the first latch circuit and set content by the first setting section, wherein the phase error detecting section includes: a second counter configured to count the second reference clock output from the second output section; a second latch circuit configured to latch a count value of the second counter with the speed pulse; and a second setting section configured to set a phase error detection range, and wherein the phase error detecting section is configured to detect the phase error data based on the count value latched by the second latch circuit and set content by the second setting section.