Patent ID: 7679144

Claim:
A semiconductor device comprising: a semiconductor substrate; a device isolation insulating film dividing an active region of the semiconductor substrate into plural pieces; a gate electrode formed on the active region with a gate insulating film interposed therebetween; a source/drain region which is formed in the active region on both sides of the gate electrode, and which constitutes a MOS transistor of a memory cell with the gate electrode; an interlayer insulating film formed over each of the active region and the device isolation insulating film; a hole which is formed in the interlayer insulating film, and which commonly overlaps with two adjacent active regions and the device isolation insulting film between the two active regions; and a conductive plug which is formed in the hole, and which electrically connects the two active regions wherein a plurality of the MOS transistors are formed, at least two of the plural MOS transistors are a driver transistor and a transfer transistor, and the active regions of the adjacent driver transistor and transfer transistor are electrically connected with each other by the conductive plug.