Patent ID: 8516428

Claim:
A method of improving manufacturability of an integrated circuit on a semiconductor substrate, the method comprising: a computer arranging an unmodified plurality of cells; the computer defining routes of interconnecting conductive paths between the unmodified plurality of cells based on operation of the integrated circuit; the computer evaluating the arrangement of the unmodified plurality of cells and the routes of the interconnecting conductive paths between the unmodified plurality of cells to identify a change, wherein the change comprises one of removing an uncontacted portion of a polysilicon element, removing an unused input or output connection portion of an element of an unmodified cell, increasing a separation between a conductive path element and a second conductive path of the unmodified cell by moving the conductive path element, removing unused routing targets of the unmodified cell, increasing coverage of metal of the contact element, adding dummy fill in sensitive locations of the unmodified cell, and adding via material to the metal element of the unmodified cell; and the computer modifying at least one element of at least one cell of the unmodified plurality of cells in response to identification of the change to create at least one modified cell based upon the change, wherein the at least one element comprises at least one of the polysilicon element, the metal element, the contact element, the diffusion material element, and the conductive path element, and wherein the at least one modified cell is to be used to create the integrated circuit on the semiconductor substrate.