Patent ID: 7793077

Claim:
A microcomputer system, comprising: a register file comprising a plurality of registers; a load/store unit coupled to the register file and configured to use a first part of a memory address to load a double-word into a first register and a second register of the register file; and a control unit configured to select either an alignment unit or a shuffle unit, wherein the alignment unit is configured to perform an alignment operation by determining a starting data byte of a vector based one of a value stored in a register and an immediate value of an instruction, such vector being stored partially in a first register and partially in a second register of the register file, and extracting the vector from the first register and the second register beginning from a first bit in a starting data byte in the first register continuing through bits in the second register and replicating the vector into a third register such that the third register contains a plurality of aligned data elements, and wherein the shuffle unit, coupled to the register file, selects one or more data elements from at least two registers of the register file, shuffles the order of the selected data elements and writes the reordered data elements into either a selected memory location or an additional register.