Patent ID: 7640397

Claim:
A memory for storing a plurality of stored values and for comparing an input value to said plurality of stored values to generate a hit signal indicative of said input value matching one of said plurality of stored values, each of said stored values and said input value has a shared portion and a non-shared portion, and said shared portion of each stored value matches said shared portion of each other stored value and not all of said non-shared portions of said stored values match, said shared portions and said non-shared portions having a variable length, said memory comprising: a plurality of memory rows for storing said plurality of stored values; an updateable base value register, separate from said plurality of memory rows, for storing a base value, said base value has a shared portion corresponding in value and bit position to the shared portion of said plurality of stored values and corresponding in bit position to said shared portion of said input value, said base value has a non-shared portion corresponding in bit position to the non-shared portion of said plurality of stored values and said input value; comparator circuitry coupled to said plurality of memory rows and to said updateable base value register and responsive to said input value, for identifying any memory row storing a stored value matching said input value and for generating a hit signal in response thereto, said comparator circuitry comprising: (i) first comparator circuitry for comparing said non shared portion of said input value with said non-shared portions of said plurality of stored values; and (ii) second comparator circuitry for comparing said shared portion of said input value with said shared portion of said base value; and comparator control circuitry, coupled to said comparator circuitry, for adjustably controlling a boundary between the shared portions and the non-shared portions of said stored values and said base value.