Patent ID: 7962717

Claim:
An array of processor nodes, each node having a respective local node address identifying it within the array, each local node address comprising a plurality of bits having an order of addressing significance from most to least significant, and each node comprising: a mapping device configure to map each of said bits of the local node address onto a respective routing direction; a switch arranged to receive a message having a destination node address identifying a destination node, the switch comprising: a comparing component configured to compare the local node address to the destination node address in order to identify the most significant non-matching bit; and a routing component configured to route the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching bit of the local node address by the mapping device, wherein the switch is configured to perform said comparison one bit at a time, and to halt the comparison upon encountering the most-significant non-matching bit.