Patent ID: 7871925

Claim:
A method for manufacturing a stack package, comprising the steps of: preparing a wafer having upper and lower surfaces and comprising a plurality of semiconductor chips, at least one of said chips having at least one through-via interconnection pattern forming region; forming a first groove that surrounds the through-via interconnection pattern forming region; filling an insulation layer into the first groove to substantially fill the first groove with electrically insulating material to thereby form a guard ring around the through-via interconnection pattern forming region; forming a hole through the through-via interconnection pattern forming region, said hole being inside the first groove; applying a metal to the hole in the through-via interconnection pattern forming region; forming a through-via interconnection plug by back-grinding a backside of the semiconductor chip to expose the insulation layer material in the first groove and to expose the metal layer in the hole; sawing the wafer to obtain first and second semiconductor chips, at least one of which is formed with the through-via interconnection plug and the guard ring surrounding the through-via interconnection plug; stacking at least two semiconductor chips, at least one of which is formed with the through-via interconnection plug and the guard ring, onto a substrate having upper and lower surfaces and a circuit pattern on at least one of the upper and lower surfaces, such that the semiconductor chips are electrically coupled to each other via the through-via interconnection plugs; overmolding a material over the upper surface of the substrate and the stacked semiconductor chips; and mounting solder balls to the lower surface of the substrate.