Patent ID: 7683665

Claim:
A method of implementing multiple programmable finite state machines using a shared transition table, said method comprising: forming a plurality of finite state machine cores such that an amount of said plurality of finite state machine cores is unchangeable; forming a state transition array, comprising: forming a plurality of state transition elements such that an amount of said plurality of state transition elements assigned to one of said plurality of finite state machine cores and to one of a plurality of states is adjustable, said forming said plurality of state transition elements comprising: forming a plurality of associated state transition elements such that said plurality of associated state transition elements is associated with said plurality of finite state machine cores, said forming said plurality of associated state transition elements comprising assigning said amount of said plurality of state transition elements to said one of said plurality of finite state machine cores and to said one of said plurality of states; and forming a plurality of free state transition elements not assigned to said plurality of finite state machine cores; and forming a routing network such that said forming said plurality of associated state transition elements is realized, said forming said routing network comprising: forming a plurality of compartmented multiplexors dedicated to a plurality of compartments, said plurality of compartments comprising said plurality of state transition elements; forming a current state register to control a usage of said plurality of compartmented multiplexors with respect to said plurality of compartments; connecting said plurality of said compartments to a plurality of corresponding mux-levels of said plurality of compartmented multiplexors; and providing a start base address to specify a starting one of said plurality of corresponding mux-levels for one of said plurality of compartments such that an overlapping of said plurality of corresponding mux-levels is prevented, wherein said amount of said plurality of finite state machine cores is equal to or greater than a number of said plurality of finite state machine cores associated with said plurality of associated state transition elements, wherein said one of said plurality of compartments has a number of state transition elements that is equal to a number of comparators in a finite state machine core associated with said one of said plurality of compartments, wherein an amount of said plurality of compartmented multiplexors equals said amount of said plurality of finite state machine cores, wherein a number of said plurality of corresponding mux-levels in an entirety of said plurality of compartmented multiplexors is not utilized, and wherein said plurality of corresponding mux-levels is utilized in at least one of said compartmented multiplexors.