Patent ID: 7671388

Claim:
A lateral junction field effect transistor comprising: a first semiconductor layer located on a semiconductor substrate, and doped with impurities (p) of a first conductivity type; a second semiconductor layer located on said first semiconductor layer, and doped with impurities (p) of the first conductivity type; a third semiconductor layer located on said first semiconductor layer, neighboring to said second semiconductor layer, and doped with impurities (n) of a second conductivity type; a fourth semiconductor layer located on said first semiconductor layer, neighboring to said third semiconductor layer, and doped with impurities (p) of the first conductivity type; source/drain region layers arranged in said second, third and fourth semiconductor layers, spaced from each other by a predetermined distance, and doped with impurities (n) of the second conductivity type more heavily than said third semiconductor layer; a first gate electrode layer arranged in said second semiconductor layer between said source/drain region layers, having a side surface on its one side extending on said third semiconductor layer, and doped with impurities (p) of the first conductivity type more heavily than said third semiconductor layer; and a second gate electrode layer of the first conductivity type arranged in said fourth semiconductor layer between said source/drain region layers, having a side surface on its one side extending on said third semiconductor layer, having substantially the same impurity concentration as said first gate electrode layer, and having the same potential as said first gate electrode layer.