Patent ID: 7199677

Claim:
A frequency modulation apparatus comprising: a synthesizer; an adder that adds together differential phase modulation data and a fractional part K of carrier frequency data and generates an addition fractional part K 1 ; an input data operation section that receives said addition fractional part K 1 and said carrier frequency data integer part M, generates integer part input data M 1 and fractional part input data K 2 , and provides said fractional part input data K 2 directly to said synthesizer; and an integer part data delay section that provides said integer part input data M 1 to said synthesizer delayed from first generation to second generation of a clock signal; wherein said synthesizer: receives a digital number of a plurality of bits and selects a controllable oscillator output signal frequency, divides said output signal frequency by means of a loop frequency divider, and, said loop frequency divider having a variable divisor controlled by a control input signal, generates a feedback signal that is to be compared with a reference signal; and includes a delta sigma modulation section that by integrating and delaying said fractional part input data K 2 from said input data operation section to generate a delayed signal and adding together a value of said delayed signal and a value of said integer part input data M 1 from said integer part data delay section performs delta sigma modulation of said fractional part input data K 2 , generates said control input signal, and provides said control input signal to said loop frequency divider.