Patent ID: 7949793

Claim:
A method of interfacing a programmable circuit and a processor, comprising: executing a blocking read instruction on the processor, where the processor remains in an idle state until the blocking read instruction returns; identifying a data output terminal of a plurality of data output terminals of the programmable circuit which is providing valid data in response to the blocking read instruction; receiving the valid data output from the identified data output terminal; packetizing the valid data output from the identified data output terminal of the programmable circuit to form at least one packet; providing the at least one packet to the processor via a streaming interface as a return to the blocking read instruction, the streaming interface comprising a non-arbitrated interface including a point-to-point streaming interface; extracting the valid data from the at least one packet; executing a function on the processor using the valid data as parametric input; packetizing return data produced by the function in response to the parametric input to produce at least one return packet; and sending the at least one return packet towards the programmable circuit via the streaming interface.