Patent ID: 8263468

Claim:
A method for fabricating an FET device, said method comprising: providing a body layer over, and in direct contact with, an insulator, wherein said body layer has a primary surface facing away from said insulator, which primary surface is adapted to host a device channel; selecting said body layer of the group consisting of Si, Ge, and their alloy mixtures; wherein said body layer has a thickness, selecting said thickness to be below a critical thickness, wherein below said critical thickness said body is susceptible to agglomeration upon being heated above an agglomeration temperature, wherein said thickness separates said primary surface from said insulator; forming a raised source/drain by a selective epitaxy, and using said primary surface for seeding said selective epitaxy; ahead of said selective epitaxy, clearing said primary surface of oxygen, wherein said clearing consists of heating said body layer under ultra high vacuum (UHV) conditions to a temperature not exceeding said agglomeration temperature; and wherein said FET device comprises said body layer, said device channel, and said raised source/drain, and wherein said FET device is characterized as being a planar semiconductor on insulator (SOI) device.