Patent ID: 8133773

Claim:
A method of forming a thin film transistor (TFT) array panel, comprising: (i) forming a patterned first conductive layer, including a gate line and a shielding portion, on a substrate, the shielding portion being electrically floated; (ii) forming a gate insulating layer on the patterned first conductive layer and the substrate; (iii) forming a patterned semiconductor layer, including a portion that overlaps the shielding portion, on the gate insulating layer; (iv) forming a patterned second conductive layer, including a source electrode and a drain electrode on the patterned semiconductor layer, and a data line electrically connected to the source electrode, wherein the shielding portion is not overlapped with the data line; (v) forming a patterned passivation layer on the patterned second conductive layer and the substrate; and (vi) forming a patterned transparent conductive layer on the patterned passivation layer.