Patent ID: 7069486

Claim:
A test circuit for a logical integrated circuit having an input terminal, a functional output terminal, and a scan output terminal, said test circuit comprising: a plurality of flip-flops, each flip-flop having an input terminal and an output terminal, said flip-flops being arranged in a matrix having n stages, each stage comprising m flip-flops, a like plurality of logic gates, each logic gate having an output terminal connected to an input terminal of a respective one of said plurality of flip-flops, and means forming a scan path serially connecting said plurality of flip-flops through the respective logic gates, to propagate a test pattern applied to the input terminal of one of said plurality of serially connected flip-flops, wherein: the test pattern is used to measure an alternating current characteristic of the input terminal of said logical integrated circuit, and said scan path connects the output terminal of the flip-flop located at an end of the first stage with the scan output terminal of said logical integrated circuit.