Patent ID: 7282974

Claim:
A delay locked loop (DLL) for reducing jitter, comprising: a multiplexing unit for receiving an external clock and an inverted external clock; a first delay line for generating a first internal clock by delaying an output clock of the multiplexing unit for a certain time, and generating a second internal clock by delaying the first internal clock for a determined time, in response to a first phase comparing signal and a second phase comparing signal; a delay line control unit for generating an enable signal; a second delay line for generating a first clock by delaying the first internal clock for a predetermined time, and generating a second clock by delaying the second internal clock for a preset time, under the control of the enable signal; a phase control unit for outputting a plurality of mix control signals and a first DLL clock and a second DLL clock by comparing a phase of the first clock with a phase of the second clock; and a phase comparing unit for generating the first phase comparing signal and the second phase comparing signal by comparing a phase of the first DLL clock and the second DLL clock with a phase of a rising clock.