Patent ID: 7466012

Claim:
A semiconductor package comprising: a semiconductor die that includes at least a first power electrode and a second power electrode, each power electrode including a plurality of spaced power fingers, said power fingers being arranged in an interdigitated pattern; a first conductive clip that includes a plurality of first fingers each electrically and mechanically coupled to a respective one of said fingers of said first power electrode; a first common connector integral with said first fingers; a second conductive clip that includes a plurality of second fingers each electrically and mechanically coupled to a respective one of said fingers of said second power electrode; a second common connector integral with said second fingers; and a passivation body encapsulating at least said semiconductor die, wherein said first fingers and said second fingers are arranged in an interdigitated pattern, wherein said first and second common connectors are disposed opposite one another, and wherein said passivation body is formed from a passivation material that is capable of protecting said semiconductor die without another housing element.