Patent ID: 7541275

Claim:
A method for manufacturing an interconnect for an integrated circuit, comprising: forming a surface conductive lead in an opening formed within a protective overcoat and over a barrier layer, the barrier layer providing additional adhesion between the protective overcoat and the surface conductive lead, a portion of the barrier layer extending beyond the surface conductive lead; providing a seed layer directly contacting the barrier layer and at least partially within the opening of the protective overcoat; subjecting the seed layer to a wet etch, wherein the wet etch is without substantially undercutting the etched seed layer or surface conductive lead and without substantially affecting the barrier layer; subjecting the portion of the barrier layer to a dry etch, subsequent to subjecting the seed layer to a wet etch, to remove the portion and form a skirt, the dry etch selective to the barrier layer without substantially undercutting the etched seed layer or surface conductive lead, without width reduction of the surface conductive lead, and without oxide formation on side walls of the surface conductive lead.