Patent ID: 7994626

Claim:
A semiconductor package comprising: a first substrate having first and second major planar surfaces defined by a first perimeter; a first semiconductor die electrically coupled to the second major planar surface of the first substrate; a second substrate having first and second major planar surfaces defined by a second perimeter; a first plurality of vertical connectors, the connectors having at least a partial internal core and being configured to electrically couple the first major planar surface of the second substrate to the second major planar surface of the first substrate; and a first encapsulating resin situated between the semiconductor die and the second major planar surface of the first substrate, the first encapsulating resin also encompassing at least a portion of at least some of the vertical connectors, wherein the vertical connectors are positioned substantially within the first perimeter and the second perimeter, and wherein the second major planar surface of the second substrate is substantially available for receiving one or more electronic components.