Patent ID: 7137030

Claim:
An apparatus for fault-tolerant control comprising: an active processor module and a stand-by processor module each including an A-port memory and a B-port memory which store memory data of their own processor module (the self processor module) or memory data of the other processor module; and a memory bus switch coupled to the processor module which performs switching-over to selectively store data of the self processor module or data transmitted from the other processor module in the A-port or B-port memory, depending on whether the self processor module or the other processor module has memory ownership, the memory bus switch comprises: a memory control matching unit which is connected to a memory controller and transmits data between the memories and the memory controller; a memory matching unit which matches with the memories; a data transmission channel matching unit which connects the processor modules so as to maintain the consistency of data in the processor modules; and a non-block crossbar switch which provides a path for receiving/transmitting a control signal, an address, and data from/to the memory matching unit and switches the corresponding signals to the memory matching unit, depending on an operation mode; wherein errors are fixed by transferring system functions from the active processor module performing the system functions to the standby processor module when the errors are detected in the active processor module.