Patent ID: 7538382

Claim:
An array of non-volatile memory cells including: a semiconductor body; at least one memory-transistor well disposed within the semiconductor body; at least one switch-transistor well disposed within the semiconductor body and electrically isolated from the at least one memory transistor well; a plurality of memory transistors formed within the at least one memory-transistor well, each including spaced-apart source and drain regions; a plurality of switch transistors formed within the at least one switch-transistor well region, each associated with one of the memory transistors and including spaced-apart source and drain regions; a floating gate associated with each memory transistor, each floating gate insulated from and self-aligned with the source and drain regions of the switch transistor with which it is associated; a control gate associated with each memory transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the at least one switch transistor with which it is associated.