Patent ID: 8650239

Claim:
A method of operating a Galois field multiplier in a processor, the method comprising the steps of: receiving a k bit multiplier operand and an n bit multiplicand operand, during a first group of one or more clock cycles wherein n is greater than k; calculating a (n+k−1) bit product based on the k bit multiplier operand and the n bit multiplicand operand during the first group of one or more clock cycles; storing the (n+k−1) bit product in a first memory element during the first group of one or more clock cycles; receiving an n bit polynomial value during a second group of one or more clock cycles, the second group following in time after the first group; dividing the (n+k−1) bit product by the n bit polynomial value during the second group of one or more clock cycles; storing an n bit result of dividing the (n+k−1) product by the n bit polynomial value in a second memory element during the second group of one or more clock cycles.