Patent ID: 7743289

Claim:
A calculation method of a soft error rate of a storage circuit or an information holding circuit, comprising: deriving a first mathematical expression indicating a dependence of a soft error rate on an information storage node diffusion layer area at the same information storage node voltage from a measurement result of a relationship between a soft error rate and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of a transistor with use of a plurality of information storage node voltages as a parameter; deriving a second mathematical expression indicating a soft error rate as a function of the information storage node diffusion layer area and the information storage node voltage by substituting a relationship indicating a dependence of a soft error rate on the information storage node voltage at the same information storage node diffusion layer area into the first mathematical expression; and calculating a soft error rate by substituting a desired information storage node diffusion layer area and a desired information storage node voltage into the second mathematical expression.