Patent ID: 7759733

Claim:
A power semiconductor device, comprising: a first semiconductor substrate of a first conductivity type; a second semiconductor layer of the first conductivity provided on the first semiconductor substrate; a plurality of third semiconductor pillar regions of the first conductivity type and a plurality of fourth semiconductor pillar regions of a second conductivity type that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode provided on a lower surface of the first semiconductor substrate and connected to the first semiconductor substrate; and a second main electrode provided on the fourth semiconductor pillar regions, a concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions being lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions, a position of the connective portion in a direction perpendicular to an upper surface of the first semiconductor substrate corresponding to a position of a border between the second semiconductor layer and the fourth semiconductor pillar regions in the perpendicular direction, a concentration profile of the first-conductivity-type impurity measured along a straight line passing through the first semiconductor substrate, the second semiconductor layer, and the third semiconductor pillar region in this order having a local minimum value in a position corresponding to the connective portion, and the local minimum value being greater than the concentration of the first-conductive-type impurity in the fourth semiconductor pillar region and smaller than concentration of the first-conductivity-type impurity in the second semiconductor layer.