Patent ID: 7214613

Claim:
A method comprising: forming a gate insulation layer on a substrate, the substrate including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate; forming on the gate insulation a doped polysilicon layer having a first gate portion of first conductivity type and a second gate portion of second conductivity type, wherein the doped polysilicon layer is formed such that the first and third doped regions are located on a first side of the doped polysilicon layer, and the second and fourth doped regions are located on a second side of the doped polysilicon layer, wherein the first and third doped regions are source and drain regions of a first transistor, wherein the second and fourth doped regions are source and drain regions of a second transistor, and wherein forming the doped polysilicon layer includes forming a doped polysilicon segment between the first and third doped regions for coupling to one of a source and a drain of a third transistor; performing a nitridization process to form a cross diffusion barrier layer below a top surface of the doped polysilicon layer for preventing cross diffusion between the first gate portion and the second gate portion, wherein the cross diffusion barrier layer is formed to a thickness of about 5 angstroms to about 10 angstroms, and wherein the cross diffusion barrier is formed to prevent the cross diffusion between the first gate portion and the second gate portion without substantially increasing a resistance of the gate layer; and forming an electrode layer on the diffusion barrier layer.