Patent ID: 8112264

Claim:
A computer-implemented method comprising: providing a system graph of an electronic circuit; using a computer processor, identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; partitioning the tree into at least a first subtree and a second subtree; identifying links of the system graph as at least one of a global link or a local link, wherein the system graph comprises both global and local links, a global link forms a path from a branch of the first subtree to a branch of the second subtree, and a loop with the global link and branches of the first and second subtrees has a voltage drop of 0; forming the first subtree by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a predefined count and there are branches in the tree which have not yet been assigned to a subtree; and forming the second subtree by repeatedly adding branches of the tree, not already assigned to the first subtree, to the second subtree when a number of branches in the second subtree is less than the predefined count and there are branches in the tree which have not yet been assigned to a subtree.