Patent ID: 7948272

Claim:
An input buffer comprising: an output node; a first buffer which receives an input signal and a reference voltage, compares the input signal and the reference voltage, and outputs a first control signal, where the first control signal controls a voltage level of an output node when the reference voltage is equal to or greater than a predetermined voltage, and does not control the voltage level of the output node when the reference voltage is less than the predetermined voltage; and a second buffer which receives the input signal, which controls the voltage level of the output node in response to the input signal when the reference voltage is lower than the predetermined voltage, and which does not control the voltage level of the output node when the reference voltage is equal to or greater than the predetermined voltage, wherein the second buffer comprises: an output control section which receives the input signal, and generates a level output signal at a second level; and a level control section which generates a second control signal which controls the output node at a first level in response to the level output signal when the reference voltage is lower than the predetermined voltage and overrides the second control signal when the reference voltage is equal to the predetermined voltage.