Patent ID: 8811052

Claim:
A system, comprising a semiconductor memory device and a controller, the semiconductor memory device comprising: a system clock terminal configured to receive a system clock; a first external terminal provided to receive a read command; a second external terminal provided to output a data strobe signal in response to the read command, the data strobe signal including a read preamble and a toggle transition following to the preamble; a third external terminal provided to output a read data in synchronization with the toggle transition of the data strobe signal; and a read preamble register that includes a bit area to store information specifying a length of the read preamble of the data strobe signal, the controller comprising: a fourth external terminal provided to output the read command; a fifth external terminal provided to receive the read data; a sixth external terminal provided to receive the data strobe signal related to the read data; and a seventh external terminal provided to be capable of outputting the information specifying the length of the read preamble, the length of the read preamble being set to a first length shorter than one period of the system clock when the information indicates a first value, and the length of the read preamble being set to a second length at least substantially longer than the first length when the information indicates a second value.