Patent ID: 7304878

Claim:
An autonomous antifuse cell, comprising: an antifuse device having a first terminal connected to a ground voltage and having a second sensed terminal, said antifuse device having a higher resistance unprogrammed intact state and a lower resistance programmed state; a programming voltage input terminal for receiving a programming voltage; a PMOS pass transistor for connecting the programming voltage to the second sensed terminal of the antifuse device, said PMOS pass transistor having a control gate terminal; a transmission gate having an input terminal connected to the second sensed terminal of the antifuse device and having an output terminal, said transmission gate having one or more control signal input terminals for controlling the conduction of said transmission gate; a sense circuit having an input terminal connected to the output terminal of the transmission gate and having an output terminal connected to an antifuse cell output terminal; a level shifter having an output terminals connected to the control gate terminal of the PMOS pass transistor and to one or more control signal input terminals of the transmission gate, said level shifter providing in a write mode for conduction of the PMOS pass transistor to program the antifuse device or for conduction of the transmission gate, or said level shifter alternatively providing in a read mode conduction of the transmission gate, said level shifter having a control input terminal for receiving a control signal; and a feedback latch logic circuit having a first input terminal connected to the output terminal of the sense circuit and having a second input terminal connected to the programming voltage input terminal, said feedback latch logic circuit having an output terminal that is coupled to the control input terminal of the level shifter, said output signal of the latch logic circuit having a first output state for controlling the level shifter to be in the write mode for conduction of the PMOS pass transistor to program the antifuse device, said feedback latch logic circuit having a second output state for controlling the level shifter to be in the read mode for conduction of the transmission gate.