Patent ID: 8003461

Claim:
A method of fabricating an efuse structure, a resistor structure and a transistor structure comprising: providing a substrate comprising a transistor region, a resistor region, and an efuse region; forming a work function layer, a polysilicon layer and a first hard mask covering the transistor region, the resistor region, and the efuse region; removing the work function layer on the resistor region and the efuse region by utilizing a first photo mask; patterning the work function layer, the polysilicon layer and the first hard mask to form a gate, a resistor, an efuse in the transistor region, the resistor region, and the efuse region, respectively; removing the first hard mask in the resistor region and the efuse region respectively by utilizing the first photo mask; forming a planarized dielectric layer on the substrate, and exposing the polysilicon layer in the gate, the resistor and the efuse; removing the polysilicon layer in the gate by utilizing a second hard mask as a mask to form a recess; and forming a metal layer to fill up the recess; and removing the second hard mask.