Patent ID: 7662684

Claim:
A method for reducing poly-depletion in a dual gate CMOS fabrication process, comprising the steps of: forming an STI oxide film at proper sites of a silicon substrate having an NMOS forming region and a PMOS forming region; forming a gate dielectric film on an upper surface of the silicon substrate including the STI oxide film; forming a polysilicon film on the gate dielectric film; selectively implanting an N-type impurity and a P-type impurity into portions of the polysilicon film, which correspond respectively to the NMOS forming region and PMOS forming region of the silicon substrate, by ion implantation; and patterning the polysilicon film having the selectively ion-implanted N-type and P-type impurities and the gate dielectric film to form an N+ polysilicon gate in the NMOS region of the silicon substrate and a P+ polysilicon gate in the PMOS region of the silicon substrate, wherein the polysilicon film has a thickness ranging from 1600 to 1800 Å and, wherein the ion implantation of the N-type impurity is performed by implanting phosphorous in a dose of at least 1×10 16 /cm 2 to inhibit the poly-depletion effect and reducing a threshold variation for a gate length or width less than or equal to 0.2 μm.