Patent ID: 7394694

Claim:
A flash memory device with NAND architecture, comprising: a matrix of memory cells each having a programmable threshold voltage, wherein the matrix includes at least one sector individually erasable and the matrix is arranged in a plurality of rows and columns with the cells of each row connected to a corresponding word line of a plurality of wordlines and the cells of each column arranged in a plurality of strings of cells connected in series, the strings of each column being connected to a corresponding bit line of a plurality of bit lines; means for erasing the cells of a selected sector of the at least one sector; and means for restoring the threshold voltages of the erased cells, wherein the means for restoring acts in succession on each of a plurality of blocks of the selected sector, for each one of a set of selected bit lines, each block includes a group of cells connected to a set of selected word lines, the means for restoring including: means for reading each group with respect to a first limit value exceeding a reading reference value; means for programming only each group in which the threshold voltage of at least one cell of the group does not reach said limit value; and means for stopping the restoring in response to reaching the limit value by at least one sub-set of the groups.