Patent ID: 8099703

Claim:
A method of verifying a power optimized design, comprising: analyzing a first design, comprising an original design, with a power optimization engine executing on a processor; generating with the power optimization engine a second design, which is functionally equivalent to the first design and is power optimized, determining with the power optimization engine, a required number of structural intermediate design transformations; generating a plurality of intermediate design transformations corresponding to the required number of design transformations; verifying with a combinational equivalency checker, functional equivalency between the first design and the second design by checking the first design and a first design transformation, by checking between each pair of the plurality of intermediate design transformations, and by checking a last design transformation and the second design, wherein a sequence of verification steps is specified by a user; and wherein the second design consumes less power than the first design, and the plurality of intermediate design transformations are generated using retiming to move structural locations of registers while maintaining the functional equivalency.