Patent ID: 8151060

Claim:
A semiconductor memory system, comprising: a flash memory including a plurality of memory chips each including a plurality of blocks that can be collectively deleted and a plurality of pages obtained by dividing each block into a plurality of areas to store data; and a memory controller configured to control one of writing to and reading from the memory chips on a page basis and control batch deletion on a block basis, said memory controller further configured to: perform one of reading from and writing to a memory chip based on a logical address included in a request received from a host apparatus; manage a table for at least two physical addresses related to each logical address on a page basis, a status of each page, and a snapshot flag; if a first physical address of a first page is related to a logical address in the table, and the memory controller receives a write request to the logical address from the host apparatus: store data into a second page; set the status of the first page as invalid, if the snapshot flag is off; set the status of the first page as non-latest and maintain the relationship between the first physical address and the logical address in the table, if the snapshot flag is on; relate a second physical address of the second page to the logical address in the table; and set the status of the second page as valid; provide data stored in a page having a valid status corresponding to a physical address related to a logical address included in a read request received from the host apparatus; and provide data stored in a page having a non-latest status corresponding to a physical address related to a logical address included in a recovery read request received from the host apparatus.