Patent ID: 8455877

Claim:
A thin film transistor (TFT) array substrate, comprising: a substrate; a first patterned conductive layer disposed on the substrate, wherein the first patterned conductive layer comprises a scan line, a gate electrode, and a float electrode, and the gate electrode is electrically connected to the scan line; a first insulation layer disposed on the first patterned conductive layer; a semiconductor layer disposed on the first insulation layer, wherein the semiconductor layer comprises a channel area and a first semiconductor area, wherein the channel area and the first semiconductor area are formed as separated pieces and are spaced apart from each other; a second patterned conductive layer disposed on the first insulation layer, the second patterned conductive layer comprising a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode, wherein the gate electrode, the source electrode, the drain electrode, and the channel area constructing a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the float electrode, and the extended electrode of the drain electrode and the drain electrode are integrally formed as one piece; a second insulation layer disposed on the second patterned conductive layer; a contact hole passing through the second insulation layer and exposing a portion of the extended electrode of the drain electrode; and a pixel electrode electrically connected to the extended electrode of the drain electrode through the contact hole; wherein the first semiconductor area and the channel area are separated.