Patent ID: 8396183

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: an input unit for outputting a driving control voltage according to at least one first input signal; a pull-up unit, electrically connected to the input unit and an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to the driving control voltage and a system clock, wherein the Nth gate line is employed to transmit the Nth gate signal; an energy-store unit, electrically connected to the pull-up unit and the input unit, for performing a charging/discharging process based on the driving control voltage; a carry unit, electrically connected to the input unit, for outputting an Nth start pulse signal according to the driving control voltage and the system clock; a first pull-down unit, electrically connected to the Nth gate line, for pulling down the Nth gate signal to a first power voltage according to a first control signal; a first control unit, electrically connected to the first pull-down unit and the Nth gate line, for generating the first control signal according to the Nth gate signal; a first auxiliary pull-down unit, electrically connected to the input unit, for pulling down the driving control voltage to a second power voltage according to a second input signal; a second auxiliary pull-down unit, electrically connected to the carry unit and the input unit, for pulling down the driving control voltage and the Nth start pulse signal to the second power voltage according to a third control signal; and a third control unit, electrically connected to the second auxiliary pull-down unit and the input unit, for generating the third control signal according to the driving control voltage.