Patent ID: 7872459

Claim:
A semiconductor integrated circuit device comprising: a semiconductor chip including: n power transistors each controlled by a control signal, n first pads each connected to a respective one of the n power transistors at one end thereof, n second pads each connected to a respective one of the n power transistors at another end thereof, wherein the semiconductor chip has the same number of first pads as there are power transistors controlled by the control signal and has the same number of second pads as there are power transistors controlled by the control signal; and a control signal generating circuit arranged to generate the control signal, wherein each of the power transistors is a PNP bipolar transistor comprising: a lightly doped n-type well region on a lightly doped p-type substrate, a heavily doped n-type buried region under the lightly doped n-type well region, a heavily doped n-type sinker region from a top to a bottom of the lightly doped n-type well region so as to make contact with the heavily doped n-type buried region, an extra heavily doped n-type base region in the heavily doped n-type sinker region and connected to an output terminal of the control signal generating circuit as a base of the power transistor, a heavily doped p-type emitter region in the lightly doped n-type well region and connected to the first pad as an emitter of the power transistor, and first and second heavily doped p-type collector regions in the lightly doped n-type well region so as to sandwich the heavily doped p-type emitter region and connected to the second pad as a collector of the power transistor.