Patent ID: 8553042

Claim:
A memory controller comprising: an agent interface unit coupled to receive a plurality of memory operations from one or more sources, and wherein each memory operation of the plurality of memory operations is accompanied by a quality of service (QoS) parameter specifying a requested quality of service for the memory operation, wherein the agent interface unit comprises at least one memory channel interface unit configured to schedule the memory operations to access the memory, wherein scheduling decisions in the memory channel interface unit are responsive to the QoS parameters associated with the memory operations; and at least one memory channel unit coupled to receive the memory operations scheduled by the memory channel interface unit, and wherein the memory channel unit is configured to schedule read operations responsive to the QoS parameters, and wherein, in a first case, the memory channel unit is configured to rank a low-latency QoS parameter equal to a best effort QoS parameter, and wherein, in a second case, the memory channel unit is configured to rank the low-latency QoS parameter higher than the best effort QoS parameter.