Patent ID: 8447917

Claim:
A flash memory device, comprising: a memory array, comprising a plurality of memory modules, wherein each memory module is located in a memory channel and comprises a predetermined number of memory cells; and a memory control circuit, coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin, wherein the ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array, and wherein the memory control circuit comprises: a memory controller, receiving access requests from a host and controlling access operations of the memory array, wherein the memory controller further determines a polling interval in accordance with an access operation of a corresponding memory cell, sets a counter according to the polling interval for checking whether the polling interval has expired, and transmits a polling command to retrieve a busy/ready status of the corresponding memory cell when the polling interval has expired.