Patent ID: 8352683

Claim:
An apparatus comprising: a data cache memory having a plurality of ways, wherein the data cache memory comprises a data array and a tag array; and logic coupled with the data cache memory to: facilitate access to only part of the plurality of ways of the data cache memory in response to a load instruction or a store instruction; determine whether a number of consecutive cache memory hits of the data array exceeds a threshold; facilitate access to only part of the plurality of ways of the tag array in response to a determination that the number of consecutive cache memory hits of the data array has exceeded the threshold; determine whether a virtual address associated with the load instruction or the store instruction is to index a physical address that is mapped to another virtual address; and facilitate access to all ways of the plurality of ways of the data cache memory in response to a determination that the virtual address associated with the load instruction or the store instruction is to index the physical address that is mapped to the another virtual address.