Patent ID: 8193058

Claim:
A method of forming a semiconductor device, including a semiconductor substrate having a first region, a second region and a third region located between the first and second regions, comprising: forming a gate insulating film on the semiconductor substrate in the first, second and third regions, respectively; removing the gate insulating film in the second region; forming a first polycrystalline silicon layer having a first thickness on the gate insulating film in the first and third regions, and directly on a diffusion layer of the semiconductor substrate in the second region, respectively; forming an inter-gate insulating film on the first polycrystalline silicon layer in the first, second and third regions, respectively, the inter-gate insulating film including an opening in the third region; forming a second polycrystalline silicon layer having a second thickness on the inter-gate insulating film in the first, second and third regions, respectively, the second polycrystalline silicon layer contacting the first polycrystalline silicon layer through the opening in the third region; removing the first and the second polycrystalline silicon layers and the inter-gate insulating film situated at a first border portion between the first and third regions and a second border portion between the second and third regions, to form a first gate electrode of a memory cell transistor in the first region, a second gate electrode of a select gate transistor in the third region and a contact plug in the second region; forming first silicon oxide in the first and second border portions where the first and the second polycrystalline silicon layers and the inter-gate insulating film have been removed; removing the second polycrystalline silicon layer in the second region to expose the inter-gate insulating film; forming a second silicon oxide film on the inter-gate insulating film in the second region; forming a third silicon oxide film above the first and second gate electrodes and the second oxide film; forming a contact hole penetrating the second and third silicon oxide films and the inter-gate insulating film to expose an upper surface of the first polycrystalline silicon layer in the second region; and forming a metal plug in the contact hole, the metal plug contacting the exposed upper surface of the first polycrystalline silicon layer in the second region.