Patent ID: 8063680

Claim:
A delay locked loop circuit comprising: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and configured to correct the duty cycle of the internal clock, the duty cycle correcting block including a first pumping output node and a second pumping output node; and an error detecting unit configured to compare voltages of the first and second pumping output nodes of the duty cycle correcting block and output the comparison result to indicate whether the duty cycle correcting block has an operation error, wherein the error detecting unit includes: a comparator configured to compare the voltages of the first and second pumping output nodes of the duty cycle correcting block in response to a first enable signal; a latch configured to latch the output of the comparator in response to a second enable signal; and an output buffer configured to buffer an output of the latch and apply the buffered output to an output pad, wherein the output pad is an external terminal.