Patent ID: 6949964

Claim:
An apparatus for providing an input output from an integrated circuit, the apparatus comprising: an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V DDO ) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said first bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V DDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said second bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said third bias circuit providing a third bias voltage, coupled to the gate of the second upper PMOS device; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said fourth bias circuit providing a fourth bias voltage to the gate of the first lower NMOS device, the fourth bias voltage being in a range, the range having a maximum value of V DDP +V T and a minimum value of (V DDO −V Tp ), where V DDP and V DDO are power supply voltages and V T and V Tp are offset voltages.