Patent ID: 7115921

Claim:
A semiconductor device, comprising: a substrate of a first conductivity type; a source region of a second conductivity type formed in the substrate proximate an upper surface of the substrate; a drain region of the second conductivity type formed in the substrate proximate the upper surface of the substrate and spaced apart from the source region; a gate dielectric layer formed on at least a portion of the upper surface of the substrate; a raised source feature and a raised drain feature formed on the upper surface of the substrate, the raised source and drain features being electrically connected to the source and drain regions, respectively; and a gate structure formed on the gate dielectric layer at least partially between the source and drain regions, the gate structure including a lower gate portion formed on the gate dielectric layer and an enlarged upper gate portion supported above the gate dielectric layer by the lower gate portion, the upper gate portion being wider than the lower gate portion; wherein the upper gate portion of the gate structure is formed such that at least a portion of the upper gate portion merges with at least one of the raised source and drain features, thereby forming an electrical connection between the gate structure and at least one of the source and drain regions, respectively.