Patent ID: 7248520

Claim:
A semiconductor memory comprising: a memory cell array in which a plurality of memory cells each holding data made up of first data and second data are arranged at least along a column direction; a plurality of word lines running along a row direction in said memory cell array, and connected to said memory cells; a first bit line which runs along the column direction in said memory cell array and is connected to said memory cells, and to which the first data is read out from said memory cell when the data is read out from said memory cell; a second bit line which runs along the column direction in said memory cell array and is connected to said memory cells, and to which the second data is read out from said memory cell when the data is read out from said memory cell; a bit line precharge unit which, when detecting that an electric potential of one of said first and second bit lines changes from a first potential to a second potential lower than the first potential after the data is read out from said memory cell, changes an electric potential of the other bit line from the second potential to the first potential; and a bit line selector which, if the electric potential of the selected one of said first and second bit lines changes from the first potential to the second potential when the data is read out, selects the other bit line when the data is to be read out next, and, if the electric potential of the selected one of said first and second bit lines maintains the first potential, keeps selecting the selected bit line even when the data is to be read out next.