Patent ID: 8633532

Claim:
A semiconductor memory device comprising: an SOI substrate with a base substrate on which a conducting surface, a buried insulating layer and a device-forming layer are stacked; a switching transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region; and a storage capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in an active area of the device-forming layer, a contact plug that penetrates the device-forming layer and the buried insulating layer and is in contact with the conducting surface of the base substrate, wherein the storage capacitor is electrically connected between a body of the switching transistor and a bias line, and charged or discharged in response to a driving of the switching transistor, and wherein the portion of the device layer is insulated from an isolation layer and the buried insulating layer, and the contact plug is formed outside the isolating layer and the portion of the device-forming layer.