Patent ID: 7151009

Claim:
A method for manufacturing a wafer level chip scale package (WLCSP) comprising: preparing a first wafer having a plurality of first semiconductor chips, wherein each first semiconductor chip includes a plurality of first conductive connectors formed in a peripheral region; preparing a second wafer having a plurality of second semiconductor chips, wherein each second semiconductor chip includes a plurality of second conductive connectors formed in a peripheral region; forming a solid adhesive region on the first semiconductor chips, the solid adhesive region covering at least a central portion of the first semiconductor chips; stacking the first wafer and the second wafer whereby the first semiconductor chips are aligned with corresponding second semiconductor chips and are attached by the solid adhesive regions, and whereby the first conductive connectors form electrical connections to corresponding second conductive connectors; separating the first and second stacked wafers into a plurality of chip stack packages having at least a first void formed between opposing surfaces of the first and second semiconductor chips, the first void being open to a lateral surface; and filling the first void with a flowable adhesive composition.