Patent ID: 7425764

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said first metallization structure, and exposes said contact point, wherein said first opening has a transverse dimension between 0.5 and 3 micrometers, and wherein said passivation layer comprises a nitride layer. a second metallization structure over said passivation layer and over said contact point wherein said second metallization structure comprises a metal pad and a metal interconnect, wherein said metal interconnect connects said metal pad to said contact point through said first opening and wherein said metal interconnect over said passivation layer has a thickness greater than that of said first metal layer and greater than that of said second metal layer; and a metal bump over said metal pad, wherein said metal bump is connected to said contact point through said second metallization structure, and wherein the position of said metal bump from a top perspective view is different from that of said contact point.