Patent ID: 7378333

Claim:
A semiconductor device manufacturing method comprising a first step of forming a plurality of semiconductor elements having an integrated circuit and an electrode pad on a circuit forming surface of a semiconductor wafer, a second step of forming a stress cushioning layer on a plurality of semiconductor elements, a third step of forming an opening in an electrode pad area of said stress cushioning layers, and forming a notch wider than a width of a scribe line in said stress cushioning layer on said cutting scribe line of said semiconductor wafer, a fourth step of forming a lead wire portion extending from said electrode pad and onto said stress cushioning layer via said opening, a fifth step of forming a conductor protective layer which covers said stress cushioning layer and said lead wire portion and has an external electrode connection window portion on said lead wire portion, and also has a notch wider than said width of said scribe line at a position corresponding to said notch of said stress cushioning layer, a sixth step of forming an external electrode in said external electrode connection window portion, and a seventh step of cutting said semiconductor wafer along said cutting scribe line and obtaining a plurality of semiconductor devices in minimum units, wherein an end face obtained by said notch of said conductor protective layer at said fifth step is distanced from a cutting plane of said semiconductor wafer cutting scribe line.