Patent ID: 8299494

Claim:
A semiconductor device comprising: a first semiconductor layer of a first conductivity type comprising a plurality of trenches formed in a top surface of the first semiconductor layer, the trenches forming mesas in the first semiconductor layer; a second semiconductor layer of a second conductivity type located at a bottom surface of the first semiconductor layer; a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches and covering at least sidewalls of the mesas of the first semiconductor layer; a second epitaxial layer of the second conductivity type formed on the first epitaxial layer, the second epitaxial layer being electrically connected to the second semiconductor layer; a first dielectric layer formed in the trenches, adjacent the second epitaxial layer, the first dielectric layer filling at least part of the trenches; a gate dielectric layer formed on the sidewalls of at least a first trench above the first dielectric layer; and a gate conductive layer formed in the first trench above the first dielectric layer and adjacent the gate dielectric layer, wherein the first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, the first epitaxial layer and the second epitaxial layer each having uniform doping concentration, the second epitaxial layer having a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration, the first and second thicknesses and the first doping concentration and second average doping concentrations being selected to achieve charge balance in operation.