Patent ID: 8035141

Claim:
A semiconductor structure comprising: at least one nFET gate stack located on an upper surface of a semiconductor substrate; a bi-layer nFET embedded stressor element located at a footprint of the at least one nFET gate stack substantially within a pair of recessed regions which are present on opposite sides of said at least one nFET gate stack, said bi-layer nFET embedded stressor element including a first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a tensile strain in a device channel that is located beneath the at least one nFET gate stack, and a second layer of a second epitaxy semiconductor material that has a lower resistance than the first epitaxy semiconductor material, wherein said first layer of said bi-layer nFET embedded stressor element fills a lower portion of each recessed region and entirely covers all wall portions of the semiconductor substrate; a spacer adjoining said nFET gate stack, wherein said spacer has a base that covers an upper surface of the first layer of the bi-layer nFET stressor element and extends onto an upper surface of said second layer of the bi-layer nFET stressor element; and a source/drain region located within said second layer of said bi-layer nFET embedded stressor element, but not said first layer of said bi-layer nFET embedded stressor element.