Patent ID: 6930900

Claim:
A memory module comprising: a printed circuit board having an edge, a first side, and a common signal trace connector area positioned along the edge, the printed circuit board having a line of bilateral symmetry substantially perpendicular to the edge and which bisects the printed circuit board into a first lateral half and a second lateral half, the printed circuit board having a plurality of interconnection levels; a first row of integrated circuits identical to one another, the first row mounted on the first side of the printed circuit board, the first row being substantially parallel to the edge and in proximity to the common signal trace connector area, the integrated circuits of the first row having a first orientation direction; a second row of integrated circuits identical to the integrated circuits of the first row, the second row mounted on the first side of the printed circuit board, the second row being substantially parallel to the edge and in proximity to the first row and located physically farther from the common signal trace connector than is the first row, the integrated circuits of the second row having a second orientation direction different from the first orientation direction; a first register connected to the integrated circuits of the first row and the second row on a first lateral portion of the printed circuit board by a first set of address signal paths; a second register connected to the integrated circuits of the first row and the second row on a second lateral portion of the printed circuit board by a second set of address signal paths; a first plurality of data lines electrically connecting data pins of the first row of integrated circuits to the common signal trace connector area, each data line of the first plurality of data lines comprising trace portions on different interconnection levels of the printed circuit board, each trace portion having a trace portion length; and a second plurality of data lines electrically connecting data pins of the second row of integrated circuits to the common signal trace connector area, each data line of the second plurality of data lines comprising trace portions on different interconnection levels of the printed circuit board, each trace portion having a trace portion length, each data line having a length substantially equal to a sum of the trace portion lengths of the data line, whereby lengths of corresponding data lines of the first plurality of data lines and the second plurality of data lines are substantially the same.