Patent ID: 8188469

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first region and a second region defined thereon; a pair of first active regions formed in the first region, wherein the first active regions extend in a first direction in the semiconductor substrate and are separated from each other; a pair of second active regions formed in the first region between the first active regions; a pair of first active regions formed in the second region, wherein the first active regions extend in the first direction in the semiconductor substrate to correspond to the pair of first active regions in the first region; a pair of second active regions formed in the second region to correspond to the pair of second active regions in the first region; a pair of first gate lines extending in a second direction different from the first direction and separated from each other, wherein the first gate lines are included in one or both of the first and second regions, and wherein each of the first gate lines has a first end adjacent to one of the first active regions in the region in which it is formed and a second end adjacent to an end of one of the second active regions in the region in which it is formed, respectively; a pair of first shared contacts formed in the first region, wherein each contact is partially formed over a respective one of the second ends of the first gate lines in the first region and a top surface of one of the second active regions in the first region; a pair of second shared contacts formed in the second region to correspond to the pair of first shared contacts; a pair of first nodes formed in the first region that apply voltages to the pair of first shared contacts, respectively; and a pair of second nodes formed in the second region to correspond to the pair of first nodes, wherein the second nodes apply voltages to the pair of the second shared contacts, respectively.