Patent ID: 7051434

Claim:
A method for designing a routing pattern for electrical contacts on a printed circuit board, comprising the steps of: arranging contacts in a contact array of rows and columns on a top layer of the printed circuit board, electrically connecting groups of n number of columns of the contacts to n−1 number of columns of vias disposed interstitially in a via array on the top layer of the printed circuit board, between the n number of columns of the contacts, thereby forming a major vertical routing channel between adjacent groups of n number of columns of the contacts and the n−1 number of columns of vias, where the major vertical routing channel does not extend completely through the contact array, electrically connecting a first number of the vias to first electrical traces, routing the first electrical traces to an outside edge of the via array, where the first electrical traces are routed out of the via array through the major vertical routing channel electrically connecting groups of n number of rows of the contacts to n−1 number of rows of vias disposed interstitially in the via array on the top layer of the printed circuit board, between the n number of rows of the contacts, thereby forming a major horizontal routing channel between adjacent groups of n number of rows of the contacts and the n−1 number of rows of vias, where the major horizontal routing channel does not extend completely through the contact array, the major vertical routing channel intersecting with the major horizontal routing channel, electrically connecting a second number of the vias to second electrical traces. and routing the second electrical traces to the outside edge of the via array, where the second electrical traces are routed out of the via array through the major horizontal routing channel.