Patent ID: 8665008

Claim:
A semiconductor device comprising: a bias line to which a bias current flows; a switch circuit controlling an amount of the bias current based on a control signal; a control line to which the control signal is supplied; a cancellation circuit substantially cancelling a fluctuation in voltage potential of the bias line caused by changing the control signal, the fluctuation in voltage potential propagating via a parasitic capacitance between the control line and the bias line; a current-to-voltage conversion circuit converting the bias current into a bias voltage; a bias transistor having a control electrode to which the bias voltage is supplied; and a clock transmission line transmitting a clock signal, wherein the cancellation circuit includes a balance capacitor having one end being coupled to the bias line and the other end to which an inversion signal of the control signal is supplied, and wherein the bias transistor is coupled to the clock transmission line so that transmission characteristics of the clock transmission line is controlled based on the bias voltage.