Patent ID: 7498863

Claim:
An integrated circuit comprising: at least one MOS-type transistor; a detector structured to detect a variation of an electrical quantity of said at least one transistor; and a biasing device structured to modify a bias voltage of a bulk of said at least one MOS-type transistor according to the variation measured by the detector, wherein the detector comprises: a MOS-type monitor transistor; a measurement device structured to measure a monitor value of the monitor transistor, wherein the measurement device is formed of a resistor placed between a drain of the monitor transistor and a first voltage reference, a source of the monitor transistor being connected to a second voltage reference, the monitor value being a voltage at a first intermediary node between the drain of the monitor transistor and the resistor of the measurement device; a reference device structured to generate a reference value corresponding to a value which would be measured on the monitor transistor if electric characteristics thereof remained unchanged, wherein the reference device is formed of two resistors placed in series between the first voltage reference and the second voltage reference, and the reference value being a voltage at a second intermediary node between the resistors of the reference device; a comparison device structured to compare the monitor and reference values and measure a value difference between the monitor and reference values, the biasing device being structured to apply to a bulk of the monitor transistor and the bulk of said at least one transistor the bias voltage which varies according to the value difference measured by the comparison device; and a control device structured to apply between a gate and the source of the monitor transistor a control voltage representative of a gate-source voltage applied to said at least one MOS-type transistor.