Patent ID: 7239193

Claim:
A semiconductor device comprising: a booster portion including a plurality of first switching elements connected in series from an output portion and a plurality of first capacitor elements whose one ends are connected between respective adjacent ones of the first switching elements, the booster portion being inputted with clock signals from the other ends of the first capacitor elements to output a boosted voltage from the output portion; and a voltage converter portion comprising n boosting stages each of which includes a second capacitor element whose one end is connected to a first voltage source via a second switching element and whose other end is connected to a reference voltage via a third switching element, said second capacitor element being charged on the basis of a voltage difference between the first voltage source and the reference voltage, and comprising a plurality of fourth switching elements each of which is provided at least between adjacent ones of the boosting stages to connect and disconnect the second capacitor elements in series between a second voltage source and the other ends of the first capacitor elements, the number of the second capacitor elements being controlled to each one of 0, m and n (0<m<n, m and n are counting numbers) according to the voltages of the first and second voltage sources when the fourth switching elements conduct the connecting and disconnecting operation, the voltage converter portion outputting clock signals with phases opposed to each other to adjacent ones of the first capacitor elements.