Patent ID: 8308966

Claim:
A method for performing a double patterning process of a semiconductor device, the method comprising: forming a hard mask layer having a stack structure of a first layer, a second layer formed over the first layer, and a third layer formed over the second layer in sequence; forming a first photoresist pattern over the hard mask layer; etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier; forming a second photoresist pattern over the third layer patterns, wherein the first photoresist pattern and the second photoresist pattern form lines that orthogonally cross each other; etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier; removing the second photoresist pattern; and etching the first layer to form first layer patterns by using only the second layer patterns as an etch barrier so that the first layer patterns have hole patterns, wherein the first layer and third layer are formed of the same material and the second layer is formed of a material having an etch selectivity with respect to the first and third layers.