Patent ID: 7360109

Claim:
A microcomputer comprising: a timer circuit built therein, which is operated in accordance with a timer clock signal asynchronous with a CPU clock signal for operating a CPU, said timer circuit including, a timer counter which counts a generation interval of an external signal in sync with the timer clock; a first timer register which fetches therein a counted value of the timer counter in sync with the timer clock; a second timer register which fetches therein the value of the first timer register in sync with the CPU clock; an edge detection circuit which detects a change in the level of the external signal to thereby generate an edge detection signal; and a reload control circuit which outputs a first reload control signal for reloading the count value of the timer counter into the first timer register in sync with the timer clock in accordance with the edge detection signal, and outputs a second reload control signal for reloading the value of the first timer register fetched therein by the first reload control signal into the second timer register in sync with the CPU clock, and which holds the output of the second reload control signal where a second edge detection signal is generated during the interval from after the generation of a first edge detection, the CPU reads the contents of the second timer register, and outputs the second reload control signal after the CPU has read the contents of the second timer register.