Patent ID: 7615435

Claim:
A method, comprising: embedding SiGe in source and drain regions of an NFET device; implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device; and heating the SiGeC to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe, wherein: the heating is a melt laser anneal; the heating is below a melting point of an underlying substrate; and the carbon is implanted before or after a rapid thermal anneal of the source and drain regions of the NFET device; the method further comprising: embedding SiGe in source and drain regions of a PFET device and blocking the source and drain regions of the PFET device during the implanting step; and masking the PFET device with a same mask during the implanting step and implantation of the source and drain regions of the NFET device, wherein the embedding SiGe in the source and drain regions of the NFET device is performed at a same time as the embedding SiGe in the source and drain regions of the PFET device.