Patent ID: 7493615

Claim:
A method for synchronizing multiple threads in an out of order microprocessor, comprising the steps of: identifying a synchronizing instruction in a sequence of instructions for a first thread executing on the microprocessor; in response to identifying the synchronizing instruction, halting execution of instructions in all other remaining threads that are executing on the microprocessor; executing the synchronizing instruction in said first thread; resuming execution of instructions in the remaining threads after executing the synchronizing instruction; marking a non-executed instruction that is slated for execution in each halted remaining thread with a trap; wherein instructions slated for execution prior to the instruction marked with a trap in each of the other remaining threads are retired before the synchronizing instruction is executed; wherein said synchronizing instruction is at least one that reads a system array directly, switches memory translation context, and employs a branch prediction scheme; and wherein the marking of a non-executed instruction with a trap in at least one of the other threads comprises adding an extra data bit to the non-executed instruction that identifies the trap as a hardware trap.