Patent ID: 7592844

Claim:
A comparator comprising: a pair of inputs; a first comparator cell coupled to the pair of inputs and responsive to a first range of input voltages for providing a first comparison signal; a second comparator cell coupled to the pair of inputs and responsive to a second range of input voltages, overlapping the first range, for providing a second comparison signal; and a logic arrangement responsive to the first and second comparison signals to provide a comparator output signal, the logic arrangement being responsive to a transition of the first comparison signal or a transition of the second comparison signal, whichever occurs first, representing a first change of comparison result to provide a first state of the comparator output signal, and being responsive to a transition of the first comparison signal or a transition of the second comparison signal, whichever occurs first, representing a second change of comparison result opposite to the first change to provide a second state of the comparator output signal opposite to said first state, wherein the logic arrangement comprises a latch providing an output of the comparator, at least one rising edge detector responsive to a transition of at least one of the first and second comparison signals representing said first change of comparison result to set a first state of the latch, and at least one falling edge detector responsive to a transition of at least one of the first and second comparison signals representing said second change of comparison result to produce a second state of the latch, wherein the logic arrangement further includes a logic function for setting the first state of the latch in response to a high level of both the first and second comparison signals, and a logic function for setting the second state of the latch in response to a low level of both the first and second comparison signals.