Patent ID: 7028111

Claim:
A bus system including a first station and a second station, coupled by a bus for transferring messages, said bus being designed to operate in accordance with a protocol in which said first station periodically sends messages in a predetermined order to the second station, characterized in that said first station includes an interruptible processor, a memory element comprising a buffer, and a bus interface, wherein said interruptible processor can be operated so as to generate a plurality of series of message properties where the message properties include timing information and further include a payload; wherein said processor can further be operated so as to issue a first series of message properties from among said plurality of series of message properties to said buffer, and upon receipt of an interrupt signal from said bus interface to issue a second series of message properties from among said plurality of series of message properties; wherein said buffer has a storage capacity that is adjustable by the processor such that it is matched to store said first series of said message properties and said second series of said message properties; wherein said bus interface can be operated so as to retrieve said first series of message properties from said buffer, to generate a first series of said messages properties from said message properties, to send said first series of said messages to said second station, and to send interrupt signal to said processor; said bus interface can be operated for periodically receiving messages with data items from the second station; said bus interface can be further operated so as to extract said data items from said received messages, to extract timing information from said received messages, to compare said timing information with said timing information of said message properties from said first series of message properties stored in said buffer, and if said extracted timing information matches the timing information of said message properties from said first series of message properties stored in said buffer, to add said extracted data items to said payload; and said processor can be operated so as to retrieve said payload from said message properties from said first series of message properties stored in said buffer upon receipt of a further interrupt signal from said bus interface.