Patent ID: 8463835

Claim:
A floating-point adder circuit, comprising: an input multiplexer coupled to receive a first input value and a second input value; a first adder-subtractor circuit implemented as a subtraction circuit for a near path calculation of the floating-point adder circuit, the first adder-subtractor circuit selectively coupled to receive one of the first input value and the second input value at each of a first input and a second input, wherein the value coupled to the second input is added to or subtracted from the value coupled to the first input; a right shift circuit for aligning the smaller of the first input value and the second input value which is coupled to the second input of the first adder-subtractor circuit; an additional shift circuit coupled to an output of the first adder-subtractor circuit, the additional shift circuit providing left shifting for a near path calculation and right shifting for a far path calculation; and a second adder-subtractor circuit coupled to an output of the additional shift circuit, wherein the additional shift circuit and the second adder-subtractor circuit are used in both near path calculations and far path calculations.