Patent ID: 7902878

Claim:
A clock gating circuit comprising: an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node, wherein the input logic circuit includes a pullup circuit serially coupled via the internal enable node to a pulldown circuit, and further comprising: a first isolation element configured to selectively prevent the pullup circuit from biasing the internal enable node at a logical high voltage level; and a second isolation element configured to selectively prevent the pulldown circuit from biasing the internal enable node at a logical low level, wherein at least one of the first isolation element and the second isolation element is responsive to a gated clock signal; a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to the gated clock signal; and a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.