Patent ID: 7246188

Claim:
A system-on-chip (SoC) integrated circuit (IC), comprising: a bus controller; a plurality of slaves interconnected with said bus controller via respective slave buses; a plurality of masters interconnected with said bus controller via respective master data buses, a first one of the plurality of masters configured to issue requests to a first one of the plurality of slaves and a second one of the plurality of slaves, a second one of the plurality of masters configured to issue a request to the first one of the plurality of slaves, wherein said first and second ones of the plurality of slaves receiving said requests for data and providing said requested data at the same time in response to the requests issued from the first one of the plurality of masters; and control signals issued by said bus controller and indicating to each slave a readiness of the first one of the plurality of masters to receive data it requested from that slave, the second one of the plurality of slaves sending the requested data to the first one of the plurality of masters causing the first one of the plurality of slaves to send the data requested from the second one of the plurality of masters to the second one of the plurality of masters without having to stall awaiting the first one of the plurality of masters to become ready.