Patent ID: 7139943

Claim:
An integrated circuit, comprising: a core memory array; a test mode compression circuit generating test mode data from data received from said core memory, array; a multiplexer receiving read data from said core memory array and receiving said test mode data from said test mode compression circuit, said multiplexer receiving a test mode compression signal, said multiplexer selectively transferring one of said read data and said test mode data dependent at least in part upon said test mode compression signals; a first in first out register, said first in first out register receiving from said multiplexer said test mode data when said test mode compression signal is active, said first in first out register receiving from said multiplexer said read data when said test mode compression signal is not active; and a latency control circuit, said latency control circuit receiving a clock signal and issuing a latency control signal, said latency control signal being dependent at least in part upon said clock signal and being issued after a predetermined number of cycles of the clock signal, the predetermined number of cycles being adjustable; wherein said first in first out register receives said latency control signal, said first in first out register shifting data dependent at least in part upon said latency control signal.