Patent ID: 8275945

Claim:
A memory system, comprising: a controller that regulates read and write timing access to one or more FLASH memory devices employed for random access memory applications and to a dynamic random access memory (DRAM) buffer component that operates as a data staging area for incoming system writes by receiving, during a data burst, incoming write data for the one or more FLASH memory devices, wherein the controller reads write data from the DRAM buffer component and application data from the one or more FLASH memory devices; a memory management unit that updates the one or more FLASH memory devices with the incoming system writes received by the DRAM buffer component at a frequency selected to sustain a frequently written sector in the DRAM buffer as a function of a capacity of the DRAM buffer component and provided at least one sector being cached in the DRAM buffer component before the one or more FLASH memory device are updated; and wherein the memory management unit maintains a sector-based write activity log and determines whether to move respective data of the incoming write data from the DRAM buffer component to the one or more FLASH memory devices during a background operation based at least in part on buffer write activity recorded in the sector-based write activity log at a time determined based on at least one of write times associated with the one or more FLASH memory devices, bandwidth of the one or more FLASH memory devices, or sector size associated with the one or more FLASH memory devices, wherein the memory management unit is bypassed for incoming system writes related to a low write demand application; and wherein during the data burst the incoming write data is written to the DRAM buffer component at a high rate over a short period of time and the write data is moved at a slower rate to the one or more FLASH memory devices during the background operation.