Patent ID: 7590819

Claim:
A memory, comprising: a RAM portion comprising a plurality of segments; a memory management unit embedded within the RAM portion; a bus internally coupled to the RAM portion through the memory management unit; a control portion in the memory management unit, wherein the control portion comprises a plurality of segment registers that maintain segment swap information and a control register that provides an enable bit to enable the plurality of segment registers, wherein each of the plurality of segment registers specifies a given one of the plurality of segments, and wherein the plurality of segment registers further each comprise a corresponding virtual segment number and a corresponding physical segment number, and wherein the control portion is configured to perform translation, the translation comprising steps of: monitoring the bus for an access to a memory address space in the RAM; detecting whether an address of an access to the RAM is within an address range that is predetermined to indicate that a translation is required; responsive to detecting an access address range indicating translation is required, comparing the access address to contents of the plurality of segment descriptor registers; checking whether a valid bit is set in each of the plurality of segment descriptor registers; responsive to a valid bit being set in a segment descriptor register that matches the access address, translating the access address, the translated address comprising bits of the access address; responsive to a valid bit not being set in a segment descriptor register, generating an error response; and vectoring to one of a prefetch or a data handler routine to manage the generated error response.