Patent ID: 7057270

Claim:
A chip stack comprising: a first chip having a first and a second side, wherein a first plurality of contacts are formed on the first side in a first pattern and a second plurality of contacts are formed on the first side in a second pattern; a second chip having a first and a second side and a selected thickness, wherein the second side of the second chip includes a first plurality of contacts arranged in the first pattern and wherein the second chip is positioned so that the first plurality of contacts on the second chip are aligned with the first plurality of contacts on the first chip; a third chip having a first and a second side wherein the third chip includes a first plurality of contacts arranged in the second pattern on the first side wherein the third chip is located proximate the first side of the second chip such that the second chip is interposed between the first and third chips and so that the first plurality of contacts on the third chip are aligned with the second plurality of contacts on the first chip; a first set of interconnecting structures having a first length that are interposed between the first plurality of contacts on the first chip and the first plurality of contacts on the second chip so as to interconnect the first plurality of contacts on the first chip and the first plurality of contacts on the second chip; and a second set of interconnecting structures having a second length that are interposed between the second plurality of contacts on the first chip and the first plurality of contacts on the third chip so as to interconnect the second plurality of contacts on the first chip and the first plurality of contacts on the third chip and wherein the second length of the second set of interconnecting structures is sized so that the second chip can be interposed between the first side of the third chip and the first side of the first chip, wherein the third chip comprises a second plurality of contacts arranged in the first pattern on the second side and further comprising a fourth chip having a first and a second side and a selected thickness, wherein the second side of the fourth chip includes a first plurality of contacts arranged in the first pattern and wherein the fourth chip is positioned so that the first plurality of contacts on the fourth chip are aligned with the first plurality of contacts on the first chip and further comprising a fourth set of interconnecting structures of the first length interposed between the third and fourth chips and aligned with the second and first contacts of the third and fourth chips respectively and interconnecting the third and fourth chips.