Patent ID: 8825948

Claim:
A memory controller comprising: a bus interface; scheduler circuitry communicably connected to the bus interface, the scheduler circuitry receiving a control signal from a processor via the bus interface; an external interface communicably connected to the scheduler circuitry, the external interface connecting an external device to the scheduler circuitry; and an internal memory buffer communicably connected only to the scheduler circuitry, wherein the processor emulates testing of the external device by transmitting the control signal to the scheduler circuitry and receiving a communication response from the scheduler circuitry, the scheduler circuitry is configured to receive test data via the bus interface and transmit the test data to the internal memory buffer, the test data simulating functionality and performance data of the external device, the internal memory buffer is configured to store the test data, the scheduler circuitry is further configured to transmit an operation signal to the internal memory buffer, in accordance with the control signal received from the processor, the operation signal to perform read/write operations on the test data stored within the internal memory buffer, the internal memory buffer is further configured to perform the read/write operations in accordance with the operation signal and transmit a result signal to the scheduler circuitry, and the scheduler circuitry is further configured to receive the result signal from the internal memory buffer and transmit the communication signal to the processor via the bus interface, in accordance with the result signal.