Patent ID: 7543120

Claim:
A processor, comprising: at least one instruction execution unit that executes store instructions to obtain store operations; a store queue coupled to said instruction execution unit, said store queue including: a queue entry in which said store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory, wherein a gather indication is generated when a store operation is gathered in the queue entry; and dispatch logic that varies a duration of said store gathering window, wherein said dispatch logic includes: a counter that increments during clock cycles in which the gather indication is not asserted; selection circuitry that selects a store gathering window duration for said queue entry; a policy control unit that controls selection by said selection circuitry; and a comparator that compares a count of said counter and said store gathering window duration, and responsive thereto, generates a dispatch signal to cause dispatch of a write transaction from said queue entry.