Patent ID: 7051061

Claim:
A circuit capable of performing a complex division and dual complex multiplication, the complex division involving dividing a first complex value by a second complex value and the dual complex multiplication involving multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value, the circuit comprising: a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication; a plurality of multipliers coupled to the first input for receiving real and imaginary components of the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplications; a second input configured for selecting the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication; a plurality of multiplexers coupled to the second input for selecting the real and imaginary components of the second complex value when the circuit is performing the complex division and real and imaginary components of the fifth and sixth complex values when circuit is performing the dual complex multiplication; circuitry coupled to the plurality of multiplexers the circuitry comprising: a first circuit comprising an adder/subtractor coupled to a MUX coupled to a multiplier coupled to a plurality of MUXes and a subtractor coupled to a MUX; a second circuit comprising an adder/subtractor coupled to a MUX coupled to a multiplier coupled to a plurality of MUXes and a subtractor; a divider coupled to said first and second circuits which is coupled to a MUX of said second circuit and an adder coupled to a plurality of multipliers; a first output for producing a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication; and a second output for producing a result of the complex division of the first complex value divided by the second complex value when the circuit is performing the complex division and complex multiplication of the fifth complex value by the sixth complex value when performing the dual complex multiplication.