Patent ID: 7915934

Claim:
A delay locked loop circuit, comprising: a clock buffering block configured to generate first and second internal clocks corresponding to first and second edges of a source clock in response to a clock buffering control signal, respectively, wherein the activation of the operation of generating the second internal clock is controlled in response to a duty correcting operation terminating signal and a delay locking signal; a delay locking block configured to compare phases of the first and second internal clocks with those of first and second feedback clocks, respectively, to enable the delay locking signal according to a delay locking, and delay the first and second internal clocks as much as times corresponding to the comparison results, respectively, thereby outputting first and second delay locking clocks; a duty correcting block configured to mix phases of the first and second delay locking clocks in an inactivation period of the duty correcting operation terminating signal; and a first signal generating block configured to generate the duty correcting operation terminating signal in response to a clock enable signal, a precharge control signal and the delay locking signal.