Patent ID: 6990037

Claim:
A semiconductor device comprising: a memory cell array including a word line, a plurality of first bit lines across the word line, a plurality of second bit lines across the word line, a first flag bit line across the word line, a second flag bit line across the word line, a plurality of first memory cells arranged at intersections of the word line and the plurality of first bit lines, a plurality of second memory cells arranged at intersections of the word line and the plurality of second bit lines, a first flag memory cell arranged at intersections of the word line and the first flag bit line, and a second flag memory cell arranged at intersections of the word line and the second flag bit line; a plurality of first sense amplifiers each coupled to corresponding one of the plurality of first bit lines; a plurality of second sense amplifiers each coupled to corresponding one of the plurality of second bit lines; a first flag sense amplifier coupled to the first flag bit line; and a second flag sense amplifier coupled to the second flag bit line, wherein the plurality of first bit lines and the plurality of second bit lines are alternately arranged, wherein the memory cell array is arranged between the plurality of first sense amplifiers and the plurality of second sense amplifiers, wherein data held in the plurality of first sense amplifiers and data held in the plurality of second amplifiers are independently encoded, wherein the first flag memory cell stores information that relates to encoding the data stored in the plurality of first memory cells, wherein the second flag memory cell stores information that relates to encoding the data stored in the plurality of second memory cells.