Patent ID: 7996642

Claim:
A method for performing memory optimization on a memory, the method comprising: receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests, such that a series of read/write requests having matching identifiers are associated and related with one another; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods during which none of the read/write requests will be received; and performing opportunistic functions in the memory during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.