Patent ID: 7271488

Claim:
A semiconductor integrated circuit comprising: a plurality of interconnect layers; and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer comprises a plurality of first interconnect groups and a plurality of second interconnect groups arranged in a matrix, each first interconnect group comprises a plurality of first interconnects extending in a row direction of the matrix and arranged side by side in a column direction of the matrix, each second interconnect group comprises a plurality of second interconnects extending in the column direction and arranged side by side in the row direction, the first interconnect groups and the second interconnect groups are alternately arranged in each row and in each column of the matrix, the first interconnect groups and the second interconnect groups are arranged facing each other between two adjacent interconnect layers, the first interconnect groups and the second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias, each first interconnect group and the first interconnect groups adjacent in the row direction to the second interconnect group facing that first interconnect group between layers comprise overlapping parts where they can be connected through vias, and each second interconnect group and the second interconnect groups adjacent in the column direction to the first interconnect group facing that second interconnect group between layers have overlapping parts where they can be connected through vias.