Patent ID: 8416011

Claim:
An adaptive body bias generation circuit, comprising: a PMOS body bias circuit, wherein the PMOS body bias circuit comprises: a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage; a PMOS charge pump coupled to the PMOS linear voltage regulator circuit for generating a positive supply voltage for the PMOS linear voltage regulator circuit using a core supply voltage; and a PMOS reference voltage generator coupled to the PMOS linear voltage regulator circuit for providing a PMOS reference voltage using the core supply voltage and wherein the PMOS linear voltage regulator circuit generates the PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage; a NMOS body bias circuit, wherein the NMOS body bias circuit comprises: a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage; a NMOS charge pump coupled to the NMOS linear voltage regulator circuit for generating a negative supply voltage for the NMOS linear voltage regulator circuit using the core supply voltage; and a NMOS reference voltage generator coupled to the NMOS linear voltage regulator circuit for providing a NMOS reference voltage using the core supply voltage and wherein the NMOS linear voltage regulator circuit generates the NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage, wherein the PMOS body bias voltage and the NMOS body bias voltage drive a substrate of PMOS and NMOS devices in an integrated circuit.