Patent ID: 7416929

Claim:
A method of making a SiC semiconductor device comprising a vertical junction field effect transistor (JFET) and a Schottky barrier diode (SBD) comprising: positioning a first mask on a source layer of SiC of a first conductivity type, wherein the source layer is adjacent a SiC drift layer of the first conductivity type and wherein the drift layer is adjacent a SiC substrate layer of the first conductivity type; selectively etching through the source layer and into the drift layer to form raised source regions separated by etched regions; implanting dopants of the second conductivity type into exposed portions of the drift layer such that the implanted regions are SiC of the second conductivity type; removing the first mask; annealing the device to activate the dopants; positioning a second mask on the source layer of the device; forming gate regions, a Schottky anode region, and, optionally, edge termination structures by selectively etching through the implanted layer of the device to expose material of the first conductivity type; removing the second mask; depositing dielectric material on exposed etched surfaces of the device such that the dielectric material is thinner on the raised source regions; etching the dielectric material to expose the source regions; selectively etching through the dielectric material over the gate region to expose implanted material; depositing metal on exposed source and gate regions to form source and gate ohmic contacts respectively; depositing metal on the substrate opposite the drift layer to form a drain ohmic contact; selectively etching through the dielectric material over the SBD anode region to expose material of the first conductivity type; depositing a Schottky metal layer in the Schottky anode region and in contact with the source ohmic contact; depositing metal layers on the Schottky metal layer and the gate ohmic contact to form electrical contact pads; and forming a metal layer on the drain ohmic contact to form a drain electrical contact pad; wherein the device comprises a JFET including a source, a gate and a drain and an SBD including a cathode and an anode and wherein the drain of the JFET also functions as the cathode of the SBD and wherein the source of the JFET also functions as the anode of the SBD.