Patent ID: 8450135

Claim:
A manufacturing method of pixel structure, comprising: sequentially forming a gate, a gate insulation layer, a semiconductor layer and a conductive layer on a substrate; forming a first patterned photoresist layer on the conductive layer, wherein the first patterned photoresist layer exposes a part of the gate insulation layer and comprises a plurality of first photoresist blocks and a plurality of second photoresist blocks, and a thickness of each of second photoresist block is less than the thickness of each the first photoresist block; reducing a thickness of the first patterned photoresist layer until the second photoresist blocks are completely removed to expose a part of the conductive layer; forming a pixel electrode layer on a remained first pattern photoresist layer, the remained first patterned photoresist layer and the part of the conductive layer; forming a second photoresist layer on a part of the pixel electrode layer, wherein the first patterned photoresist layer and the second photoresist layer are not overlapped with each other; taking the second photoresist layer as an etching mask to remove the part of the pixel electrode layer exposed by the second photoresist layer, the part of the conductive layer and a part of the semiconductor layer both under the removed pixel electrode layer, so that a first electrode block and a second electrode block are defined at the conductive layer and a channel region is defined at the semiconductor layer; removing the remained first patterned photoresist layer and the second photoresist layer to expose the first electrode block, the second electrode block and the pixel electrode layer; forming a protective layer to cover the first electrode block, the second electrode block, the channel region, the pixel electrode layer and the part of the gate insulation layer; and forming a common electrode layer on a part of the protective layer.