Patent ID: 7176574

Claim:
A semiconductor device structure, comprising: a semiconductor substrate having a top surface; a first dielectric layer over the top surface of the semiconductor substrate; a continuous opening in the first dielectric layer having a plurality of differing depths correlated to desired predetermined values of resistance and capacitance at predetermined points of the continuous opening, wherein the continuous opening has a first portion having a substantially planar horizontal lower surface, a second portion having a substantially planar horizontal lower surface, and a third portion having a substantially planar horizontal lower surface, wherein the first portion is shallower than the second portion and the second portion is shallower than the third portion; a first portion of a current carrying layer filling the first portion; a second portion of the current carrying layer filling the second portion and adjoining the first portion of the current carrying layer at an angle of not greater than about fifty degrees; and a third portion of the current carrying layer filling the third portion, wherein the first portion of the current carrying layer, the second portion of the current carrying layer and the third portion of the current carrying layer are electrically connected as a result of being physically continuous.