Patent ID: 6853231

Claim:
A method for synchronizing a programmable timing vernier with a reference signal, the timing vernier being programmable to one of a plurality of timing steps within a delay range, said delay range being controlled by a bias signal applied to a bias input of the timing vernier, said method comprising the steps of: (a) providing a first and a second control vernier; (b) programming said first control vernier to a first delay; (c) programming said second control vernier to a second delay; (d) triggering said first and second control verniers together to generate respective first and second delay signals; (e) generating a first difference signal corresponding to a difference between said generated first delay signal and second delay signal; and (f) comparing the first difference signal to a reference signal to generate a second difference signal, said second difference signal being coupled to the bias input of said vernier to adjust said delay range.