Patent ID: 7166498

Claim:
Method of manufacturing a thin film transistor array substrate, comprising: forming using a first mask process, a gate electrode of the thin film transistor on the substrate, a gate line connected to the gate electrode, a gate pattern including the gate pad connected to the gate line; forming a gate insulation film on the substrate where the gate pattern is formed; forming using a second mask process a source electrode and a drain electrode of the thin film transistor on the gate insulation film, a data line connected to the source electrode, a data pad connected to the data line, a source/drain pattern including a storage electrode in the region superimposed with the gate line, and a semiconductor pattern formed corresponding to the source/drain pattern; and forming using a third mask process a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode formed to cover the gate pad, a transparent electrode pattern including the data pad protection electrode formed to cover the data pad, and a gate insulation pattern and a protection film pattern stacked in the a region other than the region where the transparent electrode pattern is formed.