Patent ID: 8018416

Claim:
A driving circuit comprising: a plurality of gate lines that are parallel to each other and that each extend along a first direction; a plurality of first data lines that are parallel to each other and that each extend along a second direction substantially orthogonal to the first direction; a plurality of thin film transistors respectively provided in the vicinity of intersections of the gate lines and the first data lines; a gate driving circuit connected to the gate lines; a data driving circuit connected to the first data lines; a signal input terminal; an access circuit configured for accessing data signals outputted by the data driving circuit, the access circuit comprising a first signal line connected to the signal input terminal, a plurality of second data lines, a plurality of first field-effect transistors, a plurality of second field-effect transistors, a plurality of first capacitors, and a plurality of second capacitors, each first field-effect transistor comprising a gate electrode connected to the first signal line, a source electrode connected to a corresponding second data line, and a drain electrode connected to ground via a corresponding first capacitor, and each second field-effect transistor comprising a gate electrode connected to the first signal line, a source electrode connected to a corresponding second data line, and a drain electrode connected to ground via a corresponding second capacitor; and an output control circuit configured for receiving the data signals accessed by the access circuit and making the time period in which the data signals are applied to the first data lines accord with the time period during which the thin film transistors are switched on.