Patent ID: 7266004

Claim:
An apparatus for identifying matching values differing in less than a predetermined number of bit positions, the apparatus comprising: a content-addressable memory entry including n content-addressable memory entry cells, each particular content-addressable memory entry cell of said content-addressable memory entry cells being configured to identify whether or not a bit value of a lookup word in a bit position in the lookup word corresponding to said particular content-addressable memory entry cell matches the particular content-addressable memory entry cell's predetermined bit value; a match line, coupled to each of said content-addressable memory entry cells for providing a match reference voltage, after the match line is precharged during a precharge phase prior to a matching phase of a lookup operation on the lookup word, responsive to said identifications of not matching by said content-addressable memory cells, wherein said match reference voltage falls at rate corresponding to the number of said content-addressable memory entry cells said identifying not matching for the lookup word; and a comparator, coupled to the match line, configured to identify whether or not the match reference voltage is above or below a predetermined voltage level selected to reflect a matching of the lookup word by at least m said content-addressable memory cells at a predetermined time of the lookup operation, wherein the predetermined voltage level is selected such that said match reference voltage will be above the predetermined voltage level at the predetermined time if at least m said content-addressable memory cells did not said identify not matching and the match reference voltage will be below the predetermined voltage level at the predetermined time if at least n−m+1 said content-addressable memory cells did said identify not matching; wherein n>m>0.