Patent ID: 8487438

Claim:
An integrated circuit solder bumping system, comprising: a redistribution substrate; a first redistribution layer on the redistribution substrate; a first insulation layer on the first redistribution layer; a second redistribution layer on the first insulation layer; a second insulation layer on the second redistribution layer, the second insulation layer having a plurality of openings of at least two different sizes therethrough; a first UBM layer of titanium on at least portions of the second insulation layer and in the openings therethrough; a second UBM layer of chromium/copper alloy on the first UBM layer; a third UBM layer of copper on the second UBM layer; UBM pads formed over the openings and being formed from the UBM layers, the UBM pads being formed of at least two different sizes according to the sizes of the openings; smaller solder bumps on at least some of the UBM pads; and bigger solder bumps on at least some of the UBM pads, the bigger solder bumps having at least 100 μm of bump height difference greater than the smaller solder bumps.