Patent ID: 7788505

Claim:
A device comprising: a graphics processor that includes: a graphics rendering engine; and a frame buffer memory, operatively coupled to the graphics rendering engine, that is accessible to a user bus, wherein the frame buffer memory has a defined secure area and an unsecure area; and wherein the graphics processor is configurable as a secure or unsecure processor by use of at least one secure chip designation bit operative to provide a graphics processor level security designation configured by a non-reversible mechanism wherein the non-reversible mechanism is at least one of: a reading of at least one bit from a ROM residing on the graphics processor, a fusing to power, fusing to ground, an antifusing to power or an antifusing to ground, wherein access to the secure area is controlled by at least one access register defining at least one bound of the secure area; and further wherein the at least one access register may only be written if the at least one access register is uninitialized.