Patent ID: 8750497

Claim:
A cryptographic device comprising: arrays of first logic gates comprising I first logic gates which each receive 2 bits from among N bits of an input signal; 2 N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2 N bits output from the second logic gates, wherein the I bits, the 2 N bits, and L bits respectively output from the arrays of the first logic gates, the second logic gates, and the third logic gates each have only one active bit, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, wherein N, I, J, K, and L are positive integers, respectively, wherein each of the arrays of the first logic gates receives different 2 bits from among the N bits of the input signal, and wherein the first logic gates, the second logic gates, and the third logic gates are circuit logic gates.