Patent ID: 8598642

Claim:
A non-volatile memory bitcell comprising: a source region of a second conductivity type in a well of a first conductivity type; a drain region of the second conductivity type in the well, the drain region implanted with a halo region of the first conductivity type, a first boundary between the drain region and the halo region having a first doping gradient; a channel region in the well between the drain region and the source region; a capacitive region formed in the source region and comprising a dopant of the second conductivity type, a second boundary between the source region and the channel region having a second doping gradient that changes more gradually than the first doping gradient; and a floating gate above the well and covering the channel region, at least a portion of the drain region and the capacitive region, a gate-source capacitance between the floating gate and the source region increased relative to a gate-drain capacitance between the floating gate and the drain region by the capacitive region, an entire bottom surface of the floating gate being substantially flat.