Patent ID: 7705850

Claim:
A computer system employing PCI Express (PCIe) links, the computer system comprising: a chipset, the chipset comprising at least first and second controllers; and at least one processing unit coupled to the chipset, wherein the at least one processing unit includes: a first PCIe interface, a second PCIe interface that is physically distinct from the first PCIe interface, and a core logic unit, comprising: a first direct memory access (DMA) engine coupled to the first controller through the first PCIe interface and configured to transmit a first read request to the first controller through the first PCIe interface, and a second DMA engine coupled to the second controller through the second PCIe interface and configured to transmit a second read request to the second controller through the second PCIe interface following the transmission of the first read request, wherein the core logic unit is configured to cause the processing unit to process a first read completion packet associated with the first read request before processing a second read completion packet associated with the second read request independently of the order with which the first read completion packet and the second read completion packet are received by the processing unit.