Patent ID: 7973376

Claim:
A semiconductor device, comprising: a first interlayer insulation film formed above a semiconductor substrate; a lower layer wiring formed selectively to penetrate the first interlayer insulation film; a second interlayer insulation film formed over the first interlayer insulation film and the lower layer wiring and having a via hole exposing an upper surface of the lower layer wiring; a lower electrode formed at a bottom and a side surface of the via hole and over the second interlayer insulation film, the lower electrode being electrically connected with the lower layer wiring via the via hole; a TMR element, formed selectively over a portion of the lower electrode and including a laminated structure of a TMR film and an upper electrode; insulating film formed over the lower electrode, the TMR element and an inside of the via hole, wherein the semiconductor device has a first TMR formation area and a second TMR formation area, and the TMR element, the lower electrode, and the insulating film are formed in each of the first and the second TMR formation areas, wherein both the insulating film and the lower electrode have a side surface over the second interlayer insulation film in a uniform direction of an adjacent another lower electrode mutually, and wherein a side surface of the lower electrode corresponds in a uniform direction to a side surface of the insulating film, or a side surface of the lower electrode is depressed from the insulating film; and a third interlayer insulation film formed over the insulation film in the first and the second TMR formation areas, wherein the third interlayer insulation film is in contact with the second interlayer insulation film between the first and the second TMR formation areas to separate the lower electrodes and the insulating films in the first and the second TMR formation areas.