Patent ID: 7697343

Claim:
A circuit for performing a read operation in a NAND flash memory, the NAND flash memory comprising an array of bit lines, the array of bit lines grouped in a first group of bit lines and a second group of bit lines, the circuit comprising: a plurality of pre-charging and reading circuitries coupled to a first end of the array of bit lines, each of the plurality of pre-charging and reading circuitries comprising a select circuit connected between two adjacent bit lines of the array of bit lines, the select circuit configured to select one of a first bit line and a second bit line of the two adjacent bit lines, wherein the first bit line of the two adjacent bit lines is a part of the first group of bit lines and wherein the second bit line of the two adjacent bit lines is a part of the second group of bit lines, a first circuit connected to the first bit line of the two adjacent bit lines, the first circuit configured to pre-charge and read the first bit line, and a second circuit connected to the second bit line of the two adjacent bit lines, the second circuit configured to pre-charge and read the second bit line; and a plurality of pre-charging circuitries coupled to a second end of the array of bit lines, the plurality of pre-charging circuitries comprising a first select line connected to the first group of bit lines of the array of bit lines for selecting the first group of bit lines, a second select line connected to the second group of bit lines of the array of bit lines for selecting the second group of bit lines, and a plurality of pre-charging transistors, each of the plurality of pre-charging transistors coupled between a bit line and one of the first select line and the second select line, wherein the plurality of pre-charging circuitries is configured to simultaneously pre-charge the first group of bit lines and the second group of bit lines to different voltages.