Patent ID: 8378450

Claim:
A method of forming a device structure comprising: forming a semiconductor device on a substrate; forming at least one dielectric layer on said substrate; forming at least one metal interconnect structure including at least one interconnect-level metal line; forming a device structure including: a plurality of interdigitated structures embedded in said at least one dielectric layer, wherein said plurality of interdigitated structures vertically extends across multiple line levels, and each of said plurality of interdigitated structures vertically extends over, and not beyond, a single line level among said multiple line levels, is vertically spaced from one another, and includes at least one first metal line, at least one second metal line electrically isolated from said at least one first metal line, a third metal line laterally contacting said at least one first metal line and having a different lengthwise direction than a lengthwise direction of said at least one first metal line, wherein said at least one first metal line, said at least one second metal line, and said third metal line are vertically spaced from a topmost planar surface of said substrate by a same distance, wherein all of said at least one first metal line and said plurality of third metal lines are resistively connected to one another to constitute one electrode of a capacitor structure and are electrically isolated from said at least one second metal line, and all of said at least one second metal line are resistively connected to one another to constitute another electrode of said capacitor structure, and said one of said plurality of interdigitated structures includes a second metal line having a first sidewall and a second sidewall that is parallel to said first sidewall, and a first metal line among said one of said plurality of interdigitated structures is more proximal to said first sidewall than to said second sidewall, and another first metal line among said one of said plurality of interdigitated structures is more proximal to said second sidewall than to said first sidewall; at least one first vertical conductive via electrically connected to said at least one first metal line and said plurality of third metal lines; and at least one second vertical conductive via electrically connected to said at least one second metal line, wherein one of said at least one first metal line and said at least one interconnect-level metal line are formed concurrently by deposition and planarization of a metal layer in trenches located within said at least one dielectric layer.