Patent ID: 8433980

Claim:
A memory device comprising: (a) a memory including: (i) a plurality of cells at intersections of a plurality of word lines and a plurality of bit lines, with the cells that share a common bit line being connected in series, (ii) a word line selection mechanism for selecting one of the word lines, (iii) a programming mechanism for programming, substantially simultaneously, at least a portion of the cells of the selected word line, and (iv) a bit line selection mechanism for selecting only a portion of the bit lines that intersect the selected word line at the at least portion of the cells that was programmed substantially simultaneously, and for sensing only the cells, of the at least portion of the cells of the selected word line, that are at intersections of the selected word line with the selected portion of the bit lines; and (b) a controller, of the memory, for instructing the bit line selection mechanism to select the portion of the bit lines; wherein, to instruct the bit line selection mechanism to select the portion of the bit lines, the controller issues a command that specifies the portion of the bit lines for every command issued subsequently by the controller for sensing the cells, of the at least portion of the cells of the selected word line, that are at intersections of the selected word line with the selected portion of the bit lines, until the controller issues another command that specifies the portion of the bit lines.