Patent ID: 7403615

Claim:
A cryptographic accelerator for performing an RC4 stream cipher, comprising: a multi-ported memory having at least three read ports and at least two write ports; and a cryptographic core having a four-stage pipeline, wherein during a clock cycle in a key generation process the cryptographic core is configured to: in a first stage, increment the value of a first memory address location, in a second stage, read data stored at a previous first memory address location and calculate a value of a second memory address location, in a third stage, read data stored at a previous second memory address location, calculate a value of a third memory address location, and write data stored at a previous first memory address location to the previous second memory address location, and in a fourth stage, read data stored at a previous third memory address location and write data stored at the previous second memory address location to a previous first memory address location, wherein after three initialization clock cycles, a byte of a key stream is generated in the fourth stage by the cryptographic core in each subsequent clock cycle.