Patent ID: 8193064

Claim:
A method of manufacturing a semiconductor device, in which a substrate is prepared, where a gate electrode disposed over said substrate with a gate insulating film interposed therebetween, a sidewall spacer disposed in the side of said gate electrode, and a region, disposed in said substrate corresponding to both sides of said gate electrode, that includes a first conductivity-type source and drain region having an elevated structure above a level of an interface between said gate insulating film and said substrate are formed, the method comprising: firstly implanting a first impurity in said region including the source and drain region with a concentration equal to or less than 1E14 atoms/cm 2 , when a silicide region is formed over said source and drain region, on the conditions that a concentration peak of said first impurity of a first conductivity type is located more deeply than a bottom of said silicide region; secondly implanting a second impurity in said region including the source and drain region, on the conditions that a concentration peak of said second impurity of a first conductivity type, having a smaller mass than that of said first impurity, is located more shallowly than the concentration peak of said first impurity; and thirdly high-temperature millisecond annealing said substrate, subsequently to said firstly implanting the first impurity and said secondly implanting the second impurity, wherein implanting, in said step of firstly implanting the first impurity, said first impurity in said source and drain region so that the concentration peak of said first impurity is located more deeply than the level of the interface between said gate insulating film and said substrate, implanting, in said step of secondly implanting the second impurity, said second impurity in said source and drain region so that the concentration peak of said second impurity is located more shallowly than the level of the interface between said gate insulating film and said substrate, and said silicide region is formed so that the bottom of said silicide region is located more shallowly than the level of the interface between said gate insulating film and said substrate.