Patent ID: 7142015

Claim:
A buffer comprising: an input node for receiving a first input signal, wherein the input node comprises a voltage level, wherein the voltage level transitions between a logic one and a logic zero; first output means for providing enhanced current drive at an output node when the first output means is ON; a first control means for alternately turning the first output means ON and OFF, wherein the first control means is coupled to the input node, wherein the first control means turns the first output means ON in response to a voltage level transition at the input node, wherein the first control means turns the first output means OFF in response to a first feedback signal from the output node; a keeper means coupled to the input node and the output node for maintaining a logic one voltage level at the output node upon the turning OFF of the first output means, wherein the keeper means comprises one or more low-leakage inverters; a second output means for providing enhanced current drive at the output node when the second output means is ON; and a second control means for alternately turning the second output means ON and OFF, wherein the second control means is coupled to the input node, wherein the second control means turns the second output means ON in response to a voltage level transition at the input node, wherein the second control means turns the second output means OFF in response to a second feedback signal from the output node, wherein the first output means comprises a first PFET transistor that has higher leakage characteristics compared to the one or more low-leakage inverters of the keeper means.