Patent ID: 7110319

Claim:
A memory device comprising: a first plurality of wordline drivers, wherein each of the first plurality of wordline drivers is configured to receive an enable signal from a first row decoder and configured to drive a respective wordline; and a second plurality of wordline drivers, wherein each of the second plurality of wordline drivers is configured to receive an enable signal from a second row decoder and configured to drive a respective wordline, and wherein the first plurality of wordline drivers is interleaved with the second plurality of wordline drivers; and wherein each of the first plurality of wordline drivers and each of the second plurality of wordline drivers comprises: a first transistor, wherein a first terminal of the first transistor is coupled to a phase driver and wherein a second terminal of the first transistor is coupled to the respective wordline; a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor and a second terminal of the second transistor is coupled to ground, and wherein a gate of the first transistor is coupled to the gate of the second transistor and configured to receive a signal from one of the first and second row decoder; and a third transistor, wherein a first terminal of the third transistor is coupled to the first terminal of the second transistor and wherein a second terminal of the third transistor is coupled to ground; and wherein a current capability of the second transistor is greater than a current capability of the third transistor.