Patent ID: 8354870

Claim:
A clock-switching circuit comprising: a first switch, having as inputs a select line (SEL), a first relatively slower clock source (CK 0 _X 1 ), a second relatively slower clock source (CK 1 _X 1 ), and reset line (RESET), where the first switch ( 102 ) outputs first and second clock enable lines (ENCK 0 ) and (ENCK 1 ) and a first output clock line (MCK-X 1 ) through a delay ( 104 ), and a second switch having as inputs a first relatively faster clock source (CK 0 _X 2 ) that is a multiple of (CK 1 _X 1 ), a second relatively faster clock source (CK 1 _X2) that is a multiple of (CK 1 _X 1 ), where the two clock sources are each input through two separate delays and, the outputs of which are input to two separate AND gates, which also receive as inputs the two enable lines (ENCK 0 ) and (ENCK 1 ) respectively, where the outputs of the two AND gates are input to an OR gate, the output of which is a second output clock line (MCK-X 2 ).