Patent ID: 8890233

Claim:
A memory device, comprising: an integrated circuit substrate; a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions, different stacks of the plurality of stacks sharing a same staircase-shaped structure, the semiconductor material strips that share a same plane position of the plurality of plane positions being electrically coupled to a same bit line of a plurality of bit lines; the plurality of bit lines electrically coupled via a first plurality of conducting plugs to the plurality of stacks at the plurality of different plane positions, such that different bit lines distinguish different plane positions of the plurality of plane positions; a plurality of column select lines electrically coupled via a second plurality of conducting plugs to the plurality of stacks at the plurality of different plane positions, such that different column select lines of the plurality of column select lines distinguish different stacks of the plurality of stacks; wherein the first plurality of conducting plugs and the second plurality of conducting plugs electrically couple to the plurality of stacks at different locations along the plurality of stacks; a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the semiconductor material strips and the plurality of conductive lines, wherein the plurality of conductive lines arranged across the plurality of stacks; and memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of semiconductor material strips and the plurality of conductive lines.