Patent ID: 8274810

Claim:
A semiconductor memory device, comprising: a sub memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, each bit line pair including a bit line and an inverted bit line and each memory cell including at least one transistor having a vertical channel structure; a precharge unit comprising first MOS transistors having the vertical channel structure and providing a precharge voltage to a plurality of bit lines of the plurality of bit line pairs in response to a precharge control signal, and second MOS transistors having the vertical channel structure and providing the precharge voltage to a plurality of inverted bit lines of the plurality of bit line pairs in response to the precharge control signal; a sense amplifier unit comprising third MOS transistors having a horizontal channel structure and configured to sense and amplify a voltage difference between a bit line and an inverted bit line for each one of the plurality of bit line pairs; a column selecting gate unit comprising fourth MOS transistors having the vertical channel structure and configured to transmit data between the plurality of bit line pairs and a predetermined number of data input/output (I/O) line pairs; and an isolation gate unit connected in series between each on of the plurality of bit-line pairs and a corresponding sense bit line pair, and comprising fifth MOS transistors having the horizontal channel structure and configured to respectively connect each one of the plurality of bit line pairs to the corresponding sense bit line pair in response to an isolation control signal, wherein the precharge unit is disposed at both of opposite ends of each bit line pair and the column selecting gate unit is deposed at both of opposite ends of each bit line.