Patent ID: 8748253

Claim:
A method of forming an integrated circuit, comprising the steps of: forming a common n-channel source/drain (NSD) implant mask so as to expose an area for a logic n-channel metal oxide semiconductor (NMOS) transistor and an area for a memory NMOS transistor, and cover an area for a p-channel metal oxide semiconductor (PMOS) transistor; subsequently disposing said substrate on a first cryogenic substrate holder, which is cooled to a first cryogenic temperature no warmer than a first maximum effective cryogenic temperature T max1 ; subsequently implanting an amorphizing species at a first implant beam current density J beam1 so as to form amorphous layers in said substrate adjacent to gate sidewall spacers of said logic NMOS transistor and form amorphous layers in said substrate adjacent to gate sidewall spacers of said memory NMOS transistor, said first maximum effective cryogenic temperature T max1 being determined by said first implant beam current density J beam1 according to the relationship: log(J beam1 )=−(1020/(T max1 +273))+4.898; subsequently disposing said substrate on a second cryogenic substrate holder, which is cooled to a second cryogenic temperature no warmer than a second maximum effective cryogenic temperature T max2 ; subsequently implanting arsenic at a second implant beam current density J beam2 so as to form arsenic-doped layers in said substrate adjacent to said gate sidewall spacers of said logic NMOS transistor and form arsenic-doped layers in said substrate adjacent to said gate sidewall spacers of said memory NMOS transistor, said second maximum effective cryogenic temperature T max2 being determined by said second implant beam current density J beam2 according to the relationship: log(J beam2 )=−(1020/(T max2 +273))+4.898; implanting phosphorus while said common NSD implant mask is in place so as to form phosphorus-doped layers in said substrate adjacent to said gate sidewall spacers of said logic NMOS transistor and form phosphorus-doped layers in said substrate adjacent to said gate sidewall spacers of said memory NMOS transistor; forming a logic NSD implant mask over said substrate so as to expose said area for said logic NMOS transistor and cover said area for said memory NMOS transistor and said area for said PMOS transistor; subsequently disposing said substrate on a first non-cryogenic substrate holder, which is at a non-cryogenic temperature above −25° C. (248° K); implanting phosphorus while said logic NSD implant mask is in place so as to form phosphorus-doped layers in said substrate adjacent to said gate sidewall spacers of said logic NMOS transistor.