Patent ID: 7418692

Claim:
An ASIC device comprising: a wafer comprising a plurality of semiconductor components having a first metal level interconnecting the semiconductor components on the wafer, a first via level for interconnecting to the first metal level, a second metal level on said wafer connecting to said first metal through said first via level, a second via level through an insulator level over said second metal level, and a third metal level deposited on said wafer over said second via level, said first, second and third metal levels being insulated from one another by insulating levels through which said first and second via levels are formed; said first metal level, said first via level, said second metal level and said second via level having common masks for all ASIC devices; said third metal level masked on said wafer, said third metal level comprising a first unique mask; a third via level masked on said third metal level, said third via level comprising a second unique mask; a fourth metal level masked on said third via level, said fourth metal level comprising a third unique mask; and a fifth metal level masked on said fourth metal through a fourth via level mask, said fifth metal level mask and the fourth via level mask being common masks to all ASIC devices for completing the ASIC device; thereby completing the personalization of an ASIC device using only three unique masking levels.