Patent ID: 8042081

Claim:
A method of manufacturing a semiconductor device which has a plurality of wiring layers, comprising: determining, using a computing device, design criteria, and a manufacturing condition of said semiconductor device; carrying out layout design of said semiconductor device based on functional specification and said design criteria to produce a layout data; estimating process variations of width and thickness of each of interconnections for every wiring layer from said layout data based on said design criteria and said manufacturing condition; determining an interconnection delay affected by a specific condition of said process variations for every wiring layer; repeating correction of said layout data, the estimation and the determination until the determined interconnection delay meets said function specification, to produce a final layout data; and manufacturing said semiconductor device based on said final layout data and said manufacture condition, wherein said determining an interconnection delay comprises: determining a variation of said interconnection delay by using of parasitic resistance and parasitic capacitance for every wiring layer through statistical relaxation in which the process variations of width and thickness of each of interconnections are independent between said plurality of wiring layers.