Patent ID: 7733702

Claim:
A semiconductor memory device having a memory cell array configured by arranging a plurality of NAND cell units, said NAND cell unit comprises: a plurality of electrically erasable programmable nonvolatile memory cells connected serially; a first and a second selection transistor provided to connect both ends of said memory cells to a bit line and a source line, respectively; and dummy cells inserted in said NAND cell unit adjacent to said first and second selection transistors, respectively, wherein said dummy cells in said NAND cell unit are erased simultaneously with said memory cells under a weaker erase potential condition than that for said memory cells and set in a higher threshold distribution than an erased state of said memory cells, and wherein prior to erasing all NAND cell units in said erase unit, preprogramming is executed to selectively elevate the threshold of said dummy cells in said erase unit.