Patent ID: 7732284

Claim:
A method for fabricating a CMOS integrated circuit (IC), comprising: providing a substrate having a semiconductor surface; forming a gate stack comprising a metal gate electrode on a metal comprising high-k dielectric layer on said semiconductor surface; dry etching to pattern said gate stack to define a patterned gate electrode stack having exposed sidewalls of said metal gate electrode, said dry etching forming post etch residuals; and exposing said substrate including said patterned gate electrode stack to a solution cleaning sequence comprising: a first clean step comprising a first acid and a fluoride for removing at least a portion of said post etch residuals, said first clean step having a high selectivity to avoid etching said exposed sidewalls of said metal gate electrode, and a second clean after said first clean consisting essentially of a fluoride, wherein said second clean removes residuals from said high-k dielectric layer on said semiconductor surface.