Patent ID: 7363423

Claim:
A process of detecting multiple matches of words in a content addressable memory to an input word comprising steps of: a) receiving binary compare results, x 1 , x 2 , . . . , x N , from the memory representative of a match or not match condition of the input word to a respective word in the memory, and b) generating a representation of a relationship of x i and x j with static logic, where x i =x 1 , x 2 , . . . x N−1 and x j εx i+1 , x i+2 , . . . x N , and wherein if any pair of x i , x j are both true, the relationship is true, and wherein generating comprises: propagating a plurality of first-level general match representations though a plurality of first logic gates, each coupled to respective pairs of the binary compare results in response to a match condition on at least one of the binary compare results; propagating a plurality of first-level multiple-match representations though a plurality of second logic gates, each coupled to the respective pairs of the binary compare results in response to a match condition on at least two binary compare results; propagating at least two of the first-level general match representations through at least one third logic gate coupled to at least two of the first logic gates to generate at least one second-level general match representation; and propagating at least two of the first-level general match representations through at least one fourth logic gate coupled to at least two of the first logic gates to generate a first second-level multiple match representation.