Patent ID: 8921229

Claim:
A method of polishing surfaces of copper wiring of an ultra large scale integrated circuit, the method comprising: a) preparing a polishing solution consisting essentially of: between 35 and 80 w. % of a nano SiO 2 abrasive, between 12 and 60 w. % of deionized water, between 1 and 3 w. % of an oxidant, between 1 and 4 w. % of an active agent, and between 0.5 and 1.5 w. % of a chelating agent; and b) polishing using the polishing solution under following conditions: pressure: between 2 and 5 kPa; temperature: between 20 and 50° C.; flow rate: between 120 and 250 mL/min; and rotational speed: between 30 and 60 rpm/min; wherein the active agent is selected from the group consisting of an FA/O surfactant, O π -7((C 10 H 21 —C 6 H 4 —O—CH 2 CH 2 O) 7 —H), O π -10((C 10 —H 21 —C 6 H 4 —O—CH 2 CH 2 O) 10 —H), O−20(C 12-18 H 25-37 —C 6 H 4 —O—CH 2 CH 2 O) 70 —H), or JFC.