Patent ID: 6849489

Claim:
A method of forming semiconductor transistors, comprising: forming a gate electrode over but insulated from a semiconductor body region for each of first and second transistors; forming off-set spacers along side-walls of the gate electrode of each of the first and second transistors; after forming said off-set spacers, performing a DDD implant to form DDD source and DDD drain regions in the body region for the first transistor; after said DDD implant, forming main spacers adjacent the off-set spacers of at least the first transistor; performing a LDD implant to form LDD source and LDD drain regions for the second transistor; and after forming the main spacers, performing a source/drain (S/D) implant to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions, the highly doped regions being of the same conductivity type as and having a doping concentration greater than the DDD and LDD regions.