Patent ID: 7019361

Claim:
A semiconductor device, comprising: a semiconductor substrate having an upper surface and a lower surface; a semiconductor layer formed on said upper surface of said semiconductor substrate; a base layer of a first conduction type formed in said semiconductor layer; a gate electrode formed on said semiconductor layer with a gate insulator interposed therebetween; a source layer of a second conduction type formed in said base layer; a drain layer of said second conduction type formed in said semiconductor layer; a first interlayer insulator formed on said semiconductor layer to cover said gate electrode; a short electrode formed to short between said base layer and said source layer, a part of said short electrode overlapping said gate electrode with said first interlayer insulator interposed therebetween; a second interlayer insulator formed to cover said first interlayer insulator and said short electrode; a drain electrode formed on said second interlayer insulator and connected to said drain layer via a contact hole formed through said first and second interlayer insulators; and a source electrode formed on said lower surface of said semiconductor substrate.