Patent ID: 8809148

Claim:
A method for forming a FLOTOX-based nonvolatile memory cell comprising: forming at least one floating gate tunneling oxide transistor on a substrate diffused with an impurity of a first conductivity type, wherein forming the floating gate tunneling oxide transistor comprises: diffusing an impurity of a second conductivity type to form a drain region, diffusing an impurity of a second conductivity type to form a source region, forming a channel region by separating the drain region and the source region, forming a gate insulation layer on the substrate over the drain region, the source region and the channel region, thinning an area of the gate insulation layer to form a tunneling insulation window over the channel region overlapping a portion of the drain region and the source region, forming a floating gate as a first conductive layer formed over the tunneling insulation window to allow charges to tunnel between the floating gate and the channel region and the drain region during a programming procedure and an erasing procedure of the FLOTOX-based nonvolatile memory cell, such that a floating gate to drain capacitance is determined by the width of the channel region and an overlap length of the floating gate over the drain region and a thickness of the tunneling oxide, forming an interlayer dielectric layer on the floating gate for providing electrical insulation to the floating gate, and forming a control gate of a second conductive layer on the interlayer dielectric layer such that a control gate to floating gate capacitance is determined by an area of the floating gate with a wing extension and a thickness of the interlayer dielectric layer; wherein a coupling ratio of the control gate to the floating gate and a coupling ratio of the floating gate to the drain are maintained as a constant as a space occupied by the FLOTOX-based nonvolatile memory cell is decreased by adjusting the length and width of the channel region and a length of the wing extensions.