Patent ID: 7265697

Claim:
A decoder of a digital-to-analog converter for transforming a digital signal into a voltage signal, comprising: a first input stage for providing a plurality of input voltages Vr 0 ˜Vr 2 n −1 , wherein n is an integer larger than or equal to zero; a second input stage for providing the digital signal; an output stage for outputting the voltage signal; a N-type Metal-Oxide-Semiconductor (NMOS)-switch array comprising a plurality of NMOS transistors of k+1 columns, suitable for receiving the input voltages Vr 0 ˜Vr k of the first input stage and the digital signal of the second input stage wherein k is an integer larger than or equal to zero; and a P-type Metal-Oxide-Semiconductor (PMOS) switch array comprising a plurality of PMOS transistors of 2 n −(k−m+1) columns, suitable for receiving the input voltages Vr k−m+1 ˜Vr 2 n −1 of the first input stage and the digital signal of the second input stage, wherein m is an integer larger than or equal to zero; wherein the NMOS switch array and the PMOS switch array output one of Vr 0 ˜Vr 2 n −1 to the output stage in accordance to the digital signal.