Patent ID: 8402409

Claim:
A method of generating an implementation of a program language circuit description for a programmable logic integrated circuit (IC), comprising: on a computer processor, analyzing the program language circuit description, specified in a high-level programming language, to detect at least one function variable, each of the at least one function variable being assigned values corresponding to multiple function bodies, and each value references a different one of the multiple function bodies for dynamic function re-assignment; generating a hardware description of the program language circuit description, the hardware description being formatted in a hardware description language; wherein the step of generating the hardware description comprises: identifying a set of external variables that includes each external variable referenced by the multiple function bodies; generating, for each of the at least one function variable, a respective hardware template based on the set of external variables; and generating, for each of the multiple function bodies of the at least one function variable, a respective implementation based on the respective hardware template, each respective implementation having a respective port for each external variable referenced by the function body and a respective port for each external variable of the set of external variables not referenced by the function body; generating physical implementation data from the hardware description, the physical implementation data including a plurality of partial configurations for the programmable logic IC based on the respective implementations in the hardware description; and storing the physical implementation data in a memory; wherein the programmable logic IC, when loaded with the physical implementation data, is dynamically reconfigurable to implement selected partial configurations of the plurality of partial configurations responsive to a trigger within a static logic portion of the programmable logic IC.