Patent ID: 8799588

Claim:
A cache memory for a multiprocessor data processing system, the cache memory comprising: a data array; a directory of contents of the data array; and a Read-Claim (RC) machine that processes requests received from an associated processor core, wherein the RC machine: in response to a read-type request of the associated processor core, issues a read-type operation for a target cache line; while servicing the read-type request, monitors to detect receipt of a competing store-type operation for the target cache line; in response to receiving the target cache line of the read-type operation: installs the target cache line in the data array of the cache memory and, in the directory, sets a state field associated with the target cache line to a selected initial coherence state among multiple possible initial coherence states based on whether the competing store-type operation is detected while servicing the read-type request, wherein the RC machine selects, as the initial coherence state, a first coherence state that designates the cache memory as a source of copies of the target cache line in response to not detecting a competing store-type operation while servicing the read-type request, and wherein the RC machine selects, as the initial coherence state, a different second coherence state that does not designate the cache memory as a source of copies of the target cache line in response to detecting a competing store-type operation while servicing the read-type request.