Patent ID: 8901660

Claim:
A fault location detecting system, comprising: a semiconductor structure comprising at least one P-type substrate, at least one N-type doping area, at least one P-type well area, at least one NMOS structure, at least one P-type well contact area, and at least one charge guiding groove, wherein the N-type doping area is formed on the P-type substrate, the P-type well area is formed on the N-type doping area, the NMOS structure is formed on the P-type well area, the NMOS structure includes at least one exposed N-type source area, at least one exposed N-type drain area, and at least one exposed N-type gate area disposed between the N-type source area and the N-type drain area, the P-type well contact area is formed on the N-type doping area, and the charge guiding groove passes through the P-type well contact area and one part of the N-type doping area and is disposed between the P-type well area and the P-type well contact area; an ion beam generating device disposed above the semiconductor structure, wherein at least one ion beam generated by the ion beam generating device is projected onto the semiconductor structure to form an ion layer with positive charges and trigger off a plurality of reflected surface electronic signals, the positive charges of the ion layer are formed on the top surface of NMOS structure and the inner surface of the charge guiding groove, and the positive charges of the ion layer are transmitted to the N-type doping area through the charge guiding groove; and an image capturing device disposed above the semiconductor structure to receive the reflected surface electronic signals.