Patent ID: 7205788

Claim:
An integrated circuit comprising: a first pad; a second pad; a differential buffer coupled to the first pad and the second pad; and a differential termination impedance circuit coupled between the first pad and the second pad and comprising: a first resistance; a second resistance having a first terminal connected directly to a first terminal of the first resistance; a first active device having a first source/drain region connected directly to the first terminal of the first resistance and the first terminal of the second resistance; and a second active device having a first source/drain region coupled to a second terminal of the second resistance; a third resistance having a first terminal coupled to a second source/drain region of the second active device and a second terminal directly connected to a second source/drain region of the first active device; and a third active device having a first source/drain region coupled to the second terminal of the second resistance and a second source/drain region coupled to the first terminal of the third resistance.