Patent ID: 8907882

Claim:
A gate signal line drive circuit, comprising: a shift register basic circuit for applying a high voltage for a signal high period and a low voltage for a signal low period that is a period other than the signal high period, to a gate signal line at the time of a screen display, the shift register basic circuit comprising: a gate line high voltage applying circuit, on an input side thereof being connected to a clock voltage line to which a clock signal of a predetermined cycle set to a high voltage for the signal high period at the time of a screen display is input, a switch thereof an on-voltage being applied to in response to the signal high period and an off-voltage being applied to in response to the signal low period, and applying a voltage of the clock signal line to the gate signal line in on-state; and a gate line low voltage applying circuit, on an input side thereof being connected to a first reference voltage line set to a low voltage at the time of the screen display, a switch thereof an on-voltage being applied to in response to the signal low period and an off-voltage being applied to in response to the signal high period, and applying a voltage of the first reference voltage line to the gate signal line in on-state, wherein in the shift register basic circuit, the off-voltage is applied to the switch of the gate line low voltage applying circuit for a predetermined period at the time of a screen non-display, and wherein the shift register basic circuit further comprises a screen non-display period gate line high voltage applying circuit, entering on-state for the predetermined period at the time of the screen non-display and applying the high voltage to the gate signal line.