Patent ID: 7518412

Claim:
An output circuit comprising: a first circuit having first and second transistors connected in series between a first power supply potential node set at a first power supply potential level, and a first node, said first transistor having a control electrode directly connected to a second node that is an output node of the output circuit, so that a conduction state of said first transistor is controlled by a potential at said second node; and a second circuit having third and fourth transistors connected in series between said first power supply potential node, and said second node, said first and second circuits configured together as a current mirror circuit, said second transistor being so connected that a conduction state of said second transistor is controlled by a potential at said first node, said third transistor having a control electrode directly connected to said second node so that a conduction state of said third transistor is controlled by the potential at said second node, and said fourth transistor being so connected that a conduction state of said fourth transistor is controlled by the potential at said first node.