Patent ID: 8321751

Claim:
An apparatus for implementing a cyclic redundancy check (CRC) error detection methodology to compute a CRC error detection code for data according to the methodology, the apparatus comprising: computation means comprising a plurality of configurable elements, at least some of which comprise a data path circuit for receiving data and including an XOR gate providing an XOR function and a configurable device, the XOR gate receiving part of the data and using the received part of the data in the XOR function, at least one of the data path circuits configurable either to use the part of the data received by the circuit to compute a CRC error detection code by configuring the configurable device to output a signal resultant from the XOR function of the XOR gate or not to use the part of the data received by the circuit in the computation of the CRC error detection code by configuring the configurable device not to output a signal resultant from the XOR function of the XOR gate, the configurable elements operating in parallel to compute the CRC error detection code, and configurator means which uses the CRC error detection methodology to determine a configuration of the computation means required to compute the CRC error detection code, and configures the computation means accordingly, wherein the configurator means is able to use each of a plurality of CRC error detection methodologies to determine a configuration of the computation means required for parallel computation of a CRC error detection code according to each of the methodologies, and the computation means is configurable to allow configuration thereof for parallel computation of each CRC error detection code.