Patent ID: 8331184

Claim:
An SRAM compatible embedded DRAM device with hidden refresh and dual port capabilities, comprising: a memory cell array, having a plurality of single-port memory cells with dual-port capability; a first port access unit, connected to the memory cell array, for accessing the memory cells; a second port access unit, connected to the memory cell array, for accessing the memory cells; an access arbiter, connected to the first and the second port access units, for arbitrating a first port access request, a second port access request and a hidden refresh request; and a row decoding codeword driver, connected to the access arbiter and the memory cell array for generating a codeword line address in order to address the memory cell array, wherein the access arbiter comprises: a port control and address latch unit, for receiving control signals and addresses respectively from the first port access unit and the second port access unit to thus generate an access request signal, a refresh request signal, a first port state signal and a second port state signal; and an access control unit, connected to the port control and address latch unit, for generating a first port access control signal and a second port access control signal based on the access request signal, the refresh request signal, the first port state signal and the second port state signal, the port control and address latch unit comprising: a port controller, for receiving clock signals and enable signals respectively from the first port access unit and the second port access unit and a write signal from the second port access unit so as to generate the first port state signal, the second port state signal and a read/write mode signal; a first stage arbiter, connected to the port controller for receiving the first port state signal and the second port state signal to generate a first port request signal and a second port request signal and accordingly generate the access request signal; and a data and address latch unit, connected to the first stage arbiter for latching a first port address signal, a second port address signal and a first port write data signal based on the first port request signal and the second port request signal to further generate a first internal address signal, a second internal address signal and an input data signal.