Patent ID: 8099706

Claim:
A computer-readable software product comprising codes, executed by a computer, for a method of determining parasitic resistance and capacitance from a layout of an LSI, said method comprising: providing a plurality of patterns of a wiring structure which contains a target interconnection; and producing a library configured to store parameters indicating said parasitic resistance and said parasitic capacitance of said target interconnection for each of said plurality of patterns, wherein said producing comprises: calculating said parameters for a plurality of conditions corresponding to deviation in manufacture of said wiring structure for each of said plurality of patterns, wherein said plurality of conditions comprises a 0 th condition to a second condition, a desired width and desired film thickness of said target interconnection are W 0 and T 0 , respectively, standard deviations of a distribution of said width of said target interconnection and a distribution of said film thickness thereof are σ W and σ T , respectively, and said width W and said film thickness T in actual manufacture of said target interconnection are expressed, by using coefficients α W and α T , as W=W 0 +α W *σ W and T=T 0 +α T *σ T , said 0 th condition is a case where said width W and said film thickness T are W 0 and T0, respectively, said first condition is a case where a delay in said target interconnection is maximized under a condition that α W 2 +α T 2 is constant, and said second condition is when the delay in said target interconnection is minimized under the condition that α W 2 +α T 2 is constant.