Patent ID: 8766444

Claim:
An integrated circuit, comprising: an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings arranged along first and second lateral directions in a pattern; a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings arranged along first and second lateral directions in a pattern; first contacts extending through the lower contact openings to the upper interconnect area; and second contacts extending through the upper contact openings to the lower interconnect area; wherein the upper interconnect area is electrically coupled to a plurality of first conductive lines of an interconnect level arranged below the lower interconnect level and the lower interconnect area is electrically coupled to a plurality of second conductive lines of the interconnect level arranged below the lower interconnect level, the first and second conductive lines being alternately arranged to one another.