Patent ID: 8432190

Claim:
A semiconductor device comprising: a circuit comprising: first and second power lines extending in a first direction; a plurality of circuit cells aligned in the first direction, each of the plurality of circuit cells comprising a first region of a first conductivity type; a plurality of first transistors disposed in the first regions of parts of the plurality of circuit cells, each of the plurality of first transistors comprising first and second diffusion layers and a first gate electrode; a plurality of second transistors disposed in the first regions of the remaining parts of the plurality of circuit cells, each of the plurality of second transistors comprising third and fourth diffusion layers and a second gate electrode; a third transistor disposed in the first region of one of the plurality of circuit cells, the third transistor comprising fifth and sixth diffusion layers and a third gate electrode; a plurality of first interconnections connecting the first power line to the first diffusion layers of the plurality of first transistors; a plurality of second interconnections connecting the second power line to the third diffusion layers of the plurality of second transistors; a third interconnection connecting the first power line to the fifth diffusion layer of the third transistor; and a fourth interconnection connecting the second power line to the sixth diffusion layers of the third transistor, and wherein the circuit is configured to reduce a sub-threshold leakage current of the plurality of first transistors and the plurality of second transistors.