Patent ID: 7148759

Claim:
A phase-locked loop circuit comprising: a voltage controlled oscillator (VCO) generating oscillator signals (U vco ) with frequencies dependent on filtered signals (U cp ) applied to said voltage controlled oscillator (VCO); a phase detector circuit (PD) providing phase difference signals (U PD ) on the basis of the phase difference of said oscillator signals (U D ) and reference signals (U REF ); a loop filter circuit (LF) with at least a first and a second bandwidth filtering said phase difference signals and providing said filtered signals, said first bandwidth being determined by a first network of circuit components (C 1 , C 2 , C 3 , R 1 , R 2 ) being switched in when said phase-locked loop circuit is not locked, said second bandwidth being determined by a second network of circuit components (C 4 , C 5 , C 6 , R 3 , R 4 ) being switched in when said phase-locked loop circuit is locked; and a bias circuit (VF) applying a voltage value of a node ( 5 ) of said first network to a node ( 2 ) of said second network when said second network is switched off so that the circuit components (C 4 , C 5 , C 6 , R 3 , R 4 ) of said second network are being charged before the second network is switched in, wherein the node ( 5 ) of said first network (C 1 , C 2 , C 3 , R 1 , R 2 ) is situated at the interconnection of a capacitor (C 2 ) and a first end of a resistor (R 2 ) connected in series, the second end of said resistor (R 2 ) being connected to a signal path between the input and the output of said first network of circuit components (C 1 , C 2 , C 3 , R 1 , R 2 ).