Patent ID: 7881197

Claim:
A system for scheduling interfaces, the system comprising: a port having a line speed, the port being a physical port; a plurality of interfaces associated with the port, each interface having a bandwidth, each interface using the port to transmit data units according to a schedule; a first bit-mask associated with the port, the first bit-mask comprising a first bit-mask-level- 1 having a plurality of bits, each bit in the first bit-mask-level- 1 representing a unit of bandwidth with a total number of bits in the first bit-mask-level- 1 representing the port's line speed, each bit in the first bit-mask-level- 1 associated with an interface, each interface being associated with one or more bits in the first bit-mask-level- 1 , and the number of bits associated with each interface determining the bandwidth for that interface; a second bit-mask associated with the port, the second bit-mask comprising a second bit-mask-level- 1 having a plurality of bits separately addressable from those of the first bit mask, each bit in the second bit-mask-level- 1 representing a unit of bandwidth with the total number of bits in the second bit-mask-level- 1 representing the port's line speed, each bit in the second bit-mask-level- 1 associated with the interface, and the number of bits in the second bit-mask-level- 1 associated with each interface determining the bandwidth for that interface; and operable logic that uses the first bit-mask and the second bit-mask to identify an order in which the interfaces are scheduled for transmitting data units via the port.