Patent ID: 7692977

Claim:
A semiconductor memory device, comprising: a memory array comprising blocks of non-volatile memory cells, where each block of memory cells comprises a plurality of word lines each connected to a row of non-volatile memory cells in the block; and a high-voltage generator unit to generate different constant voltages that are applied to the memory array to perform erasing, programming and reading operations; wherein the high voltage generator unit comprises a first voltage generator circuit that selectively generates a programming pass voltage (Vpass) or a read voltage (Vread) in response to signals associated with an operation mode, and which commonly applies the selectively generated voltage to unselected word lines of a memory block, wherein the first voltage generator circuit comprises: an oscillator circuit to generate an oscillating signal; a charge pump unit to step-up a power supply voltage in response to the oscillating signal applied to an input to the charge pump unit; and a detection unit which is configured to maintain an output voltage level of the charge pump unit at Vpass during the programming operation, and which is configured to maintain the output voltage level at the output of the charge pump unit at Vread during the programming verification operation.