Patent ID: 8471839

Claim:
A signal control circuit, suitable for a liquid crystal display (LCD), the signal control circuit comprising: a bus, for transmitting a low voltage differential signal (LVDS) clock supplied to a timing controller of the LCD; and a control unit, comprising a transistor having a source, a drain and a gate, wherein the source is electrically connected to a reference level, the gate is used for receiving the LVDS clock, and the drain is electrically connected to a high level supply voltage, wherein the control unit is configured to detect a voltage level of a common-mode voltage of the LVDS clock, wherein when the control unit detects that the voltage level of the common-mode voltage of the LVDS clock drops to the reference level, a voltage level of a driving signal, which is output from the timing controller and required for driving a plurality of data drivers of the LCD by the timing controller, is maintained by the control unit to the high level supply voltage and then the driving signal with the high level supply voltage is supplied to the plurality of data drivers of the LCD, such that output from the data drivers is stopped outputting to an LCD panel of the LCD, wherein residual charges within pixel array of the LCD panel are quickly dissipated in response to the stopped output of the data drivers.