Patent ID: 7230475

Claim:
A semiconductor device, comprising: a memory; a level shifter comprising first and second level shifters that are configured to shift an internal power voltage level to an external power voltage level; an external power voltage controller comprising a first external power voltage controller configured to interrupt an external power voltage applied to the first level shifter responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of a memory and to shift an output of the first level shifter to a first level, and a second external power voltage controller configured to interrupt a connection to a ground terminal connected to the second level shifter responsive to the DPD command signal and to shift an output of the second level shifter to a second level; an inverter configured to invert the shifted outputs of the first and second level shifters; and a driver for outputting high-impedance data responsive to the inverted shifted output signals of the first and second level shifters.