Patent ID: 8513719

Claim:
A programmable power semiconductor device comprising: a substrate of a first conductivity type; a first well region of a second conductivity type disposed in the substrate, the second conductivity type being apposite to the first conductivity type; a second well region of the first conductivity type disposed in the substrate, the first well region laterally adjoining the first well region at a boundary; a first region of the second conductivity type disposed in the second well region, the first region being laterally separated from the boundary by a channel region, the first region comprising a source of a MOSFET; an insulated gate of the MOSFET disposed over the channel region, the insulated gate laterally extending at least just past the boundary to over a first area of the first well region; a conductive layer disposed aver and insulated from a second area of the first well region, the conductive layer comprising a capacitive plate, the second area of the first well region comprising a drain of the MOSFET.