Patent ID: 7535077

Claim:
A semiconductor device having a semiconductor substrate; comprising; an active region for forming transistors in which a gate is installed; an element isolation region for isolating each of transistors from others, that includes a shallow trench isolation structure; a stress region located at an interface with the element isolation region within the active region, in the stress region, a potential stress caused by a difference between a material for the element isolation region and a material of the semiconductor substrate is generated, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed and/or forming the element isolation region; a first ion impurity region at least including a first impurity for a source and/or a drain, which is formed in the active region except the stress region and the gate; and a second ion impurity region including a second impurity, each ion of which having a mass that is smaller than each ion of the first impurity, at least in a region having the stress region.