Patent ID: 8895389

Claim:
A method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a plurality of first doped regions and a plurality of second doped regions; forming a first dielectric layer having a plurality of first openings and a plurality of second openings on the semiconductor substrate; forming a first gate dielectric layer and a second gate dielectric layer in each of the first opening and each of second opening, respectively; forming a first metal gate and a second metal gate on the first gate dielectric layer and the second dielectric layer, respectively; forming a third dielectric layer on the second metal gate; forming a second dielectric layer on the first dielectric layer, the third dielectric layer, and the first metal gate; forming at least one fourth opening exposing at least one of the first metal gate and one of the first doped regions; and forming a first contact layer electrically contacting with the first metal gate and the first doped regions to be used as a share contact structure in the at least one fourth opening.