Patent ID: 8607177

Claim:
A computer implemented synthesis method for a programmable system-on-a-chip integrated circuit device, comprising: accessing a circuit netlist via the synthesis computer system, the circuit netlist representing a programmable system-on-a-chip integrated circuit design to be realized in physical form; and modifying a plurality of cells of the circuit netlist by using a netlist cell iterative sorting process, wherein the sorting process functions by: determining those cells of the circuit netlist that are coupled to a first power domain, wherein the first power domain is configured to remain powered in a standby mode; determining those cells of the circuit netlist that are coupled to a second power domain, wherein the second power domain is configured to shut down in the standby mode; and configuring those cells that are coupled to the second power domain to receive power from the second power domain to enable shut down when the integrated circuit device enters standby mode.