Patent ID: 7327597

Claim:
A memory for use in a router, comprising: a first data bus; a first plurality of banks of static random access memory (SRAM), each bank of said first plurality of banks having a driver associated therewith for selectively driving a first set of data signals from the first plurality of banks onto the first data bus; a first differential sense amplifier receiving the first set of data signals over the first data bus; a first output driver in communications with the first differential sense amp for selectively driving the first set of data signals; a second data bus coupled with the first output driver for receiving the first set of data signals; a second plurality of banks of SRAM, each bank of said second plurality of banks having a driver associated therewith for selectively driving a second set of data signals from the second plurality of banks onto the second data bus, and each bank of said second plurality of banks having one or more logic gates for temporarily storing the second set of data signals; and a second differential sense amplifier coupled with the second data bus; and a second output driver in communications with the second differential sense amp for selectively driving either the first set of data signals or the second set of data signals.