Patent ID: 8908345

Claim:
A semiconductor device, comprising: a plurality of chips of the same type; and an interposer, including a plurality of connection pads, on which the plurality of chips are homogeneously stacked in a number of layers, wherein the number of layers is between one and a scheduled number of layers N, wherein each chip has a plurality of IO terminals, a plurality of IO circuits, a plurality of ON/OFF controllable switch circuits, and a core circuit, wherein each chip has one or more IO groups connected to the core circuit, each IO group includes a plurality of IO channels equal to the scheduled number of layers N, and each IO channel is formed from an IO terminal, an IO circuit and a switch circuit, wherein each connection pad is connected to a corresponding IO terminal in a chip of an adjacent layer using a through via, wherein, when the number of layers is more than one, each IO terminal is connected to a corresponding IO terminal in a chip of an adjacent layer using a through via, and wherein the scheduled number of layers N is four or more.