Patent ID: 7280409

Claim:
An electrically erasable and programmable non-volatile memory device comprising: a plurality of erase unit areas each including a plurality of non-volatile memory cell transistors which are simultaneously selected in an erase operation; a plurality of output regulating value storing sections provided corresponding to the respective erase unit areas, of storing output regulating values of the respective erase unit areas in a non-volatile manner; a voltage generating circuit of generating a voltage having a level required in an erase operation and a write operation with respect to each of the erase unit areas; a voltage regulating circuit of regulating the level of the voltage generated in the voltage generating circuit based on a corresponding one of the output regulating values provided thereto; a read determination circuit of performing determination with respect to data after an erase operation and a write operation with respect to each of the erase unit areas; and a control circuit of operating in an erase operation and a write operation with respect to each of the erase unit areas.