Patent ID: 8051393

Claim:
A computer implemented method comprising: determining an object in a layout of a transistor design to be created with a manufacturing process, the object including a drawn width and a drawn length; determining a generated contour object of the object using a contour simulation to represent an effect of processing variation factors that occur during the manufacturing process; determining a first value for an adjusted width of the generated contour object by a computer processor; determining a plurality of segments in the generated contour object; determining a plurality of area values for the plurality of segments in the generated contour object; determining a plurality of edge lengths from the plurality of segments in the generated contour object; determining a second value for an adjusted length based on the plurality of edge lengths and the plurality of area values by the computer processor; and outputting the first value and the second value for the adjusted width and the adjusted length to a transistor simulator, the first value and the second value used by the transistor simulator instead of the drawn width and drawn length to simulate the generated contour object in a transistor simulation.