Patent ID: 7741190

Claim:
A method of fabricating isolation dielectric in an integrated circuit structure, the method comprising: forming a patterned mask over a p-type silicon substrate; using the patterned mask to implant oxygen in a selected region of the silicon substrate, the selected region having a lower layer that extends beneath an upper surface of the silicon substrate and sidewall layers that extend from the lower layer to the upper surface of the silicon substrate to define a volume region of the silicon substrate; using the patterned mask to introduce dopant into the defined volume of the silicon substrate; performing a thermal step that causes the lower layer and sidewalls of the selected region into which oxygen has been implanted to react to form silicon oxide that electrically isolates the defined volume region of the silicon substrate; forming a well of n-type conductivity in the defined volume of the silicon substrate; forming a PMOS device structure in the n-type well; and forming a NMOS device structure in a region of the silicon substrate that is not a part of the defined volume.