Patent ID: 8384216

Claim:
A manufacturing method of a package structure, comprising: providing a metal substrate, the metal substrate having a first surface, a first seed layer being formed on the first surface; forming a patterned insulating layer on the first seed layer, the patterned insulating layer exposing a portion of the first seed layer; forming a patterned circuit layer, comprising: forming a second seed layer on the patterned insulating layer, the second seed layer encapsulating the patterned insulating layer; forming a patterned photoresist layer on a portion of the first seed layer, a portion of the second seed layer, and a second surface of the metal substrate opposite to the first surface, wherein the patterned photoresist layer exposes a portion of the first seed layer and a portion of the second seed layer; plating the patterned circuit layer onto the portion of the first seed layer and the portion of the second seed layer exposed by the patterned photoresist layer, wherein the patterned circuit layer is plated with use of the patterned photoresist layer as a plating mask; and removing the patterned photoresist layer and the portion of the second seed layer underlying the patterned photoresist layer to expose a portion of the patterned insulating layer and the second surface of the metal substrate; performing a chip-bonding process to electrically connect a chip to the patterned circuit layer; forming an encapsulant, the encapsulant encapsulating the chip and the patterned circuit layer and covering a portion of the patterned insulating layer; removing the metal substrate and the first seed layer to expose a bottom surface of the patterned insulating layer and a lower surface of the patterned circuit layer; and forming a plurality of solder balls on the lower surface of the patterned circuit layer.