Patent ID: 7630229

Claim:
A semiconductor memory device including a first operation mode in which a logic circuit operates at a first power supply voltage, and a second operation mode in which the logic circuit operates at a second power supply voltage lower than the first power supply voltage, the first power supply voltage and the second power supply voltage being higher power than a ground voltage, the device comprising: a first inverter circuit and a second inverter circuit; a first memory node which is connected to an output of the first inverter circuit and an input of the second inverter circuit; and a second memory node which is connected to an input of the first inverter circuit and an output of the second inverter circuit; each of the first inverter circuit and the second inverter circuit comprising: a load transistor which includes a source connected to a first power supply terminal; and a driving transistor which includes a drain connected to a drain of the load transistor via a memory node, a gate connected to a gate of the load transistor, a source connected to a second power supply terminal, and a back gate connected to a third power supply terminal, wherein the first power supply voltage is applied to the first power supply terminal, a source voltage higher than the ground voltage is applied to the second power supply terminal, and the ground voltage is applied to the third power supply terminal; and wherein the source voltage is set to a value obtained by subtracting the second power supply voltage from the first power supply voltage.