Patent ID: 7745829

Claim:
An EL display device comprising: a plurality of pixels over a substrate, each of the plurality of pixels comprising: a switching TFT comprising a first channel formation region, a first source region, and a first drain region over the substrate, an insulating layer over the first channel formation region, the first source region, and the first drain region, and a first gate electrode over the insulating layer; a current controlling TFT comprising a second channel formation region, a second source region, and a second drain region over the substrate, the insulating layer over the second channel formation region, the second source region, and the second drain region, and a second gate electrode over the insulating layer; a first insulating film over the switching TFT and the current controlling TFT; a source wiring formed over the first insulating film and connected to one of the first source region and the first drain region of the switching TFT; a first drain wiring formed over the first insulating film and connected to the other of the first source region and the first drain region of the switching TFT and to the second gate electrode of the current controlling TFT; a second drain wiring formed over the first insulating film and connected to one of the second source region and the second drain region of the current controlling TFT; a current supply line formed over the first insulating film and connected to the other of the second source region and the second drain region of the current controlling TFT; a second insulating film over the source wiring, the first drain wiring, the second drain wiring, and the current supply line; a first electrode formed over the second insulating film and connected to the second drain wiring; an EL layer over the first electrode; a second electrode over the EL layer; and a holding capacitance comprising a semiconductor layer, a portion of the insulating layer, and a first portion of the second gate electrode of the current controlling TFT extended from a second portion of the second gate electrode of the current controlling TFT overlapping with the second channel formation region, wherein the current supply line overlaps with the holding capacitance.