Patent ID: 8200729

Claim:
A circuit comprising: an input multiplexer that interleaves samples from a plurality of input signals, and provides a multiplexed signal; a single composite finite impulse response filter configured to operate on a single signal, and to provide a filter output sequence, the single composite finite impulse response filter receiving the multiplexed signal as the single signal; and a decimator with a demultiplexer, configured to receive the filter output sequence and to perform decimation of the filter output sequence to extract a plurality of output signals, wherein each of the plurality of output signals comprises a sum of a plurality of filtered signals, wherein the plurality of filtered signals comprise the plurality of input signals with a corresponding plurality of filtering operations performed thereon such that each output signal is a function of the plurality of input signals, and wherein a first one of the filtering operations performed of a first one of the input signals for producing a first one of the output signals is independent of a second one of the filtering operations performed on the first one of the input signals for producing a second one of the output signals, and wherein the single composite finite impulse response filter comprises a shift register having a number of taps equal to the number of input signals multiplied by the number of output signals and further multiplied by a number of filter coefficients employed for one of the independent filtering operations.