Patent ID: 7663944

Claim:
A semiconductor memory device, comprising: an input data delay time adjustor for varying an input delay time, selecting one bit of n-bit input data, delaying a selected one bit of the n-bit input data by the input delay time and outputting the delayed bit, in response to a control signal during an input data delay test operation, where n is a predetermined integer; and an output data delay time adjustor for varying an output delay time, selecting one bit of m-bit output data, delaying a selected one bit of the m-bit output data by the output delay time and outputting the delayed bit, in response to the control signal during an output data delay test operation, where m is a predetermined integer, wherein the input data delay time adjustor is arranged for the n-bit input data, and wherein the output data delay time adjustor is arranged for the m-bit output data; wherein the semiconductor memory device generates a mode setting command in response to a command for a mode setting which is applied from an external portion, and receives a code applied from the external portion to generate the control signal in response to the mode setting command; and wherein the input data delay time adjustor includes: a first input switch for transmitting the n-bit input data to a normal input line or a test input line in response to the control signal; an input selector and delay for selecting the one bit of the n-bit input data outputted from the first input switch transmitted to the test input line, delaying the selected one bit of the n-bit input data by the input delay time and outputting the delay bit, in response to the control signal; and a second input switch for transmitting data outputted from the first input switch or transmitting data outputted from the input selector and delay in response to the control signal.