Patent ID: 7948284

Claim:
A power-on reset circuit that outputs a reset signal when a supply voltage reaches a first given voltage, comprising: a first output circuit comprising a first PMOS transistor and a first current source, the first output circuit controlling a first control circuit having a first output circuit reversal threshold voltage; a second output circuit comprising a second PMOS transistor and a second current source, the second output circuit having the first given voltage which is a second output circuit reversal threshold voltage lower than the first output circuit reversal threshold voltage and operating so that the reset signal is output when the supply voltage becomes higher than the first given voltage; a first source follower circuit that is applied with a reference voltage lower than the second output circuit reversal threshold voltage, and outputs a voltage based on the reference voltage to an input terminal of the first control circuit; a second source follower circuit that is applied with the reference voltage, and outputs the voltage based on the reference voltage to a gate of the first PMOS transistor and a gate of the second PMOS transistor; the first control circuit comprising a first capacitor, the first control circuit operating so that the first capacitor starts to be charged when the supply voltage becomes higher than the first output circuit reversal threshold voltage and the reset signal is not output after a given period of time has elapsed; and a second control circuit comprising a second capacitor, the second control circuit connecting the second capacitor to the gate of the first PMOS transistor and the gate of the second PMOS transistor when the supply voltage is lower than a second given voltage.