Patent ID: 8089299

Claim:
A method for coupling wiring of an integrated circuit device comprising: forming devices on a semiconductor substrate; forming a first plurality of metal layers that substantially comprise horizontal wiring tracks, the first plurality of metal layers electrically coupled to the devices; forming a second plurality of metal layers that substantially comprise vertical wiring tracks, the second plurality of metal layers electrically coupled to the devices; forming rows of through die vias that extend through the first plurality of metal layers and the second plurality of metal layers, the rows of through die vias including at least one row of through die vias that extends within an interface tile, the at least one row of through die vias interrupting a first wiring track on the first plurality of metal layers, the first wiring track including a first wiring segment that extends on one side of the at least one row of through die vias and including a second wiring segment that extends on the opposite side of the at least one row of through die vias; and forming horizontal wiring segments in the second plurality of metal layers, the horizontal wiring segments including a first horizontal wiring segment that is electrically coupled on one end to the first wiring segment and that is electrically coupled on the other end to the second wiring segment so as to electrically couple the first wiring segment to the second wiring segment.