Patent ID: 7344959

Claim:
A method of fabricating a vertical wafer-to-wafer interconnect structure comprising: providing a first wafer and a second wafer, said first wafer having at least one metal stud disposed on a surface thereof and said second wafer including at least one polyimide coated through via; inserting said at least one metal stud of said first wafer into said at least one polyimide coated through via of said second wafer to provide a combined structure; heating the combined structure to cause opposing polyimide surfaces to bond and initiate flow to fully encase each metal stud; thinning the second wafer to expose a surface of the at least one metal stud positioned within said at least one polyimide coated through via; and forming a patterned polyimide coating on a surface of the thinned second wafer and a metal pad on said exposed surface of said at least one metal stud.