Patent ID: 7288446

Claim:
A method for producing a test device for silicon-on-insulator (SOI) wafer including Si-containing material having an oxide layer buried therein, said method comprising: a) providing a gate insulator layer on a top Si surface of the SOI material; b) forming a plurality of electrode structures on said gate insulator layer, each electrode structure including a pair comprising a source electrode and a drain electrode, each of said source electrode and said drain electrode formed by depositing a first metal electrode layer from the group consisting of Al, Er, Gd, Nd, Ti and Y, followed by depositing a second metal layer from the group consisting of Ag, Al, Au, Cr, Cu, Mg, Ni and Pt; c) annealing said electrode structures at an elevated temperature in an inert atmosphere; d) for each of said electrode structures, depositing a gate electrode layer on the gate insulator between said formed source and gate electrodes; e) providing a protective mask layer over each of said electrode structures and said top Si surface of said SOI material, said protective mask being in a shape of an array of isolated mesas; f) removing Si material not protected by the protective mask layer to form an array of isolated Si mesas comprising portions of said top Si surface; and g) removing the protective mask layer from the array of isolated Si mesas comprising said portions of said top Si surface.