Patent ID: 8604835

Claim:
A device comprising: first and second power supply lines; a first circuit unit, comprising: first and second nodes; first and second transistors complementary in conductivity type to each other and coupled to each other at the first node; and third and fourth transistors complementary in conductivity type to each other and coupled to each other at the second node, the first and second transistors receiving a first clock signal at control electrodes thereof and the third and fourth transistors receiving a third clock signal at control electrodes thereof, the third clock signal being complementary to the first clock signal; a second circuit unit coupled between the first power supply line and the first circuit unit, receiving a second clock signal and connecting the first power supply line to the first circuit unit in response to the second clock signal; and a third circuit unit coupled between the second power supply line and the first circuit unit, receiving a fourth clock signal that is complementary to the second clock signal and connecting the second power supply line to the first circuit unit in response to the fourth clock signal, wherein the second circuit unit includes fifth and sixth transistors coupled in series between the first power supply line and the first circuit unit, and the third circuit unit includes seventh and eighth transistors coupled in series between the second power supply line and the first circuit unit.