Patent ID: 8829933

Claim:
A semiconductor apparatus comprising: a first chip having a first to mth memory banks, wherein m is a natural number equal or greater than 2; a second chip having a first to mth memory banks; a scribe lane disposed between the first and second chips; and a probe test logic circuit for probe testing both the first and second chips, wherein the probe test logic circuit is disposed on the scribe lane; a probe pad having a first to nth probe pads, wherein n is natural number equal or greater than 2; wherein the scribe lane and the probe test logic circuit disposed on the scribe lane are removed after the probe tests are completed; wherein the first to mth memory banks of the first chip are sequentially electrically connected with the first to nth probe pads, and the first to mth memory banks of the second chip are sequentially electrically connected with the nth to the first probe pads.