Patent ID: 7464241

Claim:
A method of operating a memory system, the method comprising: transmitting a data cycle burst such that error-protected data and error correction coding data pertaining to the error-protected data are temporally multiplexed onto the same data bus lines, wherein the transmitted data cycle burst is received by a memory device rank comprising at least one memory device, the memory device rank saving the error-protected data to an addressed segment of the memory device rank and saving the error correction coding data to an indirectly addressable segment of the memory device rank, the indirectly addressable segment of the memory device rank associated by the memory device rank with the addressed segment of the memory device rank; receiving the data cycle burst; and demultiplexing the data cycle burst to separate the error correction coding data from the error-protected data, wherein one data cycle of error correction coding is transmitted for a number of data cycles less than eight, the method further comprising masking a portion of the data transmitted during the one data cycle of error correction coding.