Patent ID: 7683664

Claim:
A selection circuit programmable in a first state to hold the output signal of the selection circuit at a constant logic level and programmable in a second state to select 1 of n input signals as the output signal, comprising: a first bank of transistors having sources receiving the n input signals, and having gates coupled to a first set of memory cells; a second bank of transistors including two or more transistors having gates coupled to a second set of memory cells, at least two transistors of the second bank having gates coupled to a complemented output of a respective one of the second set of memory cells, and each transistor in the second bank having a source coupled to drains of transistors in a respective subset of transistors of the first bank; an output stage coupled to drains of the second bank of transistors; a pair of serially coupled transistors coupled to a constant logic level signal and having gates coupled to two memory cells of the second set that control the at least at least two transistors of the second bank; and wherein the output stage outputs the constant logic level signal in response to the selection circuit being programmed in the first state and the serially coupled transistors conducting, and the output stage outputs the selected input signal in response to the selection circuit being programmed in the second state and the serially coupled transistors not conducting.