Patent ID: 7940088

Claim:
An apparatus comprising: a phase frequency detector configured to receive a first clock signal and a second clock signal, the phase frequency detector responsive to triggering edges of the first clock signal and the second clock signal, the phase frequency detector configured to generate an up signal and a down signal as control signals for a charge pump of a phase detector, wherein states of the up signal and a state of the down signal are based at least partially on the triggering edges of the first clock signal and the second clock signal, respectively; a missing clock edge detection circuit configured to determine when a particular triggering edge of the first clock signal or the second clock signal that should generate a response from the phase frequency detector has been missed by the phase frequency detector, and to correct the state of the up signal or the state of the down signal in response to a determination of a missed clock edge; and a bypass circuit configured to determine whether a missing clock edge determination by the missing clock edge detection circuit is accurate or not, wherein when the determination is accurate, the bypass circuit is configured to permit the missing clock edge detection circuit to correct the state of the up signal or the state of the down signal, and when the determination is inaccurate, the bypass circuit is configured to inhibit correction by the missing clock edge detection circuit.