Patent ID: 7546424

Claim:
A programmable logic integrated circuit comprising: a programmable logic portion comprising a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions; and an embedded processor portion coupled to the programmable logic portion and comprising: a plurality of memory cells; a first port coupled to the plurality of memory cells; a second port coupled to the plurality of memory cells; a multiplexer coupled to the first port; an arbiter coupled to the first port, the second port, and the multiplexer; and a lock register to store a user-defined variable lock size and coupled to the arbiter, wherein the user-defined variable lock size defines a lockable portion of the plurality of memory cells and a non-lockable portion of the plurality of memory cells, and wherein the arbiter arbitrates access by the second port to the lockable portion of the plurality of memory cells, and does not arbitrate access by the second port to the non-lockable portion of the plurality of memory cells.