Patent ID: 7974124

Claim:
A non-volatile memory circuit, comprising: an array of re-programmable non-volatile memory cells formed along columns along bit-lines; a plurality of column access circuits each having a corresponding set of one or more temporary data storage devices and each connectable to one or more bit-lines to transfer data between addressed memory cells formed thereupon and the corresponding set of temporary data storage devices; a plurality of N intermediate data buses, wherein the column access circuits are arranged into N subsets, each subset connected to a corresponding one of the intermediate data buses; a plurality of N shift registers, each including a plurality of series connected stages coupled with a corresponding one of the subsets of the column access circuits in order to enable connection of the temporary data storage devices of the corresponding subset with the corresponding intermediate data bus in successive instances of time as a change of state is propagated from stage-to-stage therealong; a first clock source and a plurality of N second clock sources having a frequency of 1/N of the first clock source, each of the N second clock sources connected with a corresponding one of the shift registers to cause the change of state to be propagated along the stages thereof in sequence; a unified data bus; and a bus combining circuit connected to the intermediate data buses and the unified data bus to transfer data between the intermediate data buses and the unified data bus, where the unified data bus is clocked by the first clock source and carries the combined data content of the intermediate data buses.