Patent ID: 8532122

Claim:
A network-on-chip architecture for dynamical adjusting channel direction comprising: a first channel having a first transmission direction; a first router coupled to the first channel for generating a first output request and outputting the first output request when receiving a first data, the first router comprising: a first input/output port coupled to the first channel and the first input/output port having a first operation mode; and a first channel control module coupled to the first input/output port, for outputting the first output request and generating a first output selection signal; and a second router coupled to the first router and the first channel for receiving the first data through the first channel when receiving the first output request, the second router comprising: a second input/output port coupled to the first channel and the second input/output port having a second operation mode; and a second channel control module coupled to the second input/output port and the first channel control module for receiving the first output request, and the second channel control module generating and outputting a first input selection signal according to the first output request; wherein, the first input/output port receives the first output selection signal and decides whether to change the first operation mode, the second input/output port receives the first input selection signal and decides whether to change the second operation mode, and the first transmission direction is formed by the first operation mode and the second operation mode; wherein the first router further comprises: a first register for receiving and storing the first data; a first routing module coupled to the first register for performing a bath computation with the first data to obtain and output a first channel request; the first channel control module further coupled to the first routing module for receiving the first channel request and outputting the first output request after being decoded, the first channel control module generating and outputting a first output arbitration signal; and a first arbitration module coupled to the first channel control module for receiving and deciding a timing of the first data when outputted according to the first output arbitration signal.