Patent ID: 8907380

Claim:
A dummy gate-assisted n-MOSFET having radiation tolerance characteristics, as a unit n-MOSFET that includes an N-active layer designating an active area of the transistor so that an isolation field oxide is not formed in the active area during a process, a poly gate layer designating a gate region of the transistor using poly silicon, and an n+ layer designating highly doped positions of n-type to form the source and the drain through self-alignment, the dummy gate-assisted n-MOSFET comprising: a dummy poly gate layer to block leakage current paths by use of a phenomenon that hole trapping is not generated when the thickness of the gate oxide becomes less than or equal to 10 nm; and a p-active layer and a p+ layer to block generation of leakage current by raising a threshold voltage so as to suppress channel inversion caused by trapped holes, wherein the source and the drain of the transistor are enclosed by the dummy poly gate layer, the p-active layer and the p+ layer so as to block radiation-induced leakage current paths.