Patent ID: 7099783

Claim:
A semiconductor integrated circuit having a self-testing circuit, said semiconductor integrated circuit comprising: the self-testing circuit including a test circuit which is incorporated in a logic circuit to test the logic circuit and which comprises a test pattern generator to generate a test pattern supplied to the logic circuit and a compressor to compress a test result output from the logic circuit and in which the logic circuit comprises a plurality of scan chains including a plurality of serial connected registers and the compressor comprises a through output portion to directly output the test result output from the logic circuit; a pattern counter which counts the test pattern at a test time of the logic circuit; a shift counter which counts the number of shifts in the scan chain in the logic circuit at the test time of the logic circuit; and a failure information output circuit which is connected to the test circuit and which outputs step information of the test pattern corresponding to a failure to an integrated circuit external terminal when the failure is detected at the test time of the logic circuit and which outputs count signals of the pattern counter and shift counter at the detection time of the failure to the outside of the semiconductor integrated circuit, wherein the failure information output circuit comprises, a comparison circuit which compares a signal passed through the compressor with an expected value for each test pattern and which outputs a failure flag at a mismatch time, a first external terminal which outputs the failure flag supplied from the comparison circuit to the outside of the semiconductor integrated circuit. a second external terminal which receives the failure flag and subsequently outputs the pattern count signal supplied from the pattern counter to the outside of the semiconductor integrated circuit, and a third external terminal which outputs the shift count signal supplied from the shift counter to the outside of the semiconductor integrated circuit.