Patent ID: 7721129

Claim:
A method comprising: when a processor is operating in a first state, monitoring the processor's operation for a first set of selected conditions, the processor having a plurality of functional units, the plurality of functional units receiving a clock signal with a first frequency when the processor is operating in the first state, the first set of selected conditions being indicative of a low workload period in the processor; selecting a grace period from a plurality of programmable grace periods based on detecting which one of the first set of selected conditions is satisfied, wherein each of the plurality of programmable grace periods stores a different grace period to allow completion or processing of a different event; waiting for the selected grace period to expire after detecting that the one of the first set of selected conditions is satisfied; and causing the processor to operate in a second state after expiration of the selected grace period, wherein in the second state the clock signal has a second frequency that is less than the first frequency, wherein one of the plurality of programmable grace periods is used to allow one or more pending store operations to be processed prior to the processor operating in the second state.