Patent ID: 8277668

Claim:
A method of manufacturing printed circuit boards and packaging substrates for integrated circuits, comprising: (1) forming a dielectric layer on a substrate, the dielectric layer having a surface; (2) creating blind vias in the dielectric layer so that the dielectric layer includes the blind vias and a remaining surface; (3) forming a seed layer on the dielectric layer to provide a first seed layer in each of the blind vias and a first seed layer on the remaining surface; (4) applying copper to the first seed layers to fill the blind vias to form solid conductive vias and to form a copper layer over the solid conductive vias and over the first seed layer on the remaining surface; (5) removing the copper layer and the first seed layer from the remaining surface to expose the remaining surface of the dielectric layer, and removing the copper layer from over the solid conductive vias to expose surfaces of the solid conductive vias; (6) forming a second seed layer on the remaining surface of the dielectric layer and on the exposed surfaces of the solid conductive vias; (7) applying a photo-sensitive thin film to the second seed layer, and creating a plating pattern in the photo-sensitive thin film using an image-transfer process, the plating pattern including regions of the photo-sensitive thin film that are plating resistant and regions in which the photo-sensitive thin film has been removed to expose a pattern of wires; (8) thickening the wires in the pattern of wires; (9) removing the regions of the photo-sensitive thin film that are plating resistant to expose portions of the second seed layer; (10) removing the exposed portions of the second seed layer and retaining the thickened wires, thus forming a first conductive pattern of wires; (11) repeating steps (1)-(10) to form a second conductive pattern of wires on the first conductive pattern of wires so as to provide inter-layer interconnections and fine wires.