Patent ID: 7698015

Claim:
An integrated semiconductor manufacturing system comprising: a first plurality of integrated sub-stations for operating on a first plurality of die-strips on an in-line basis to produce a second plurality of die-strips, wherein a next one of said first plurality of die-strips enters said first plurality of integrated sub-stations as soon as a previous one of said first plurality of die-strips clears said first plurality of integrated sub-stations; a second plurality of integrated sub-stations coupled to said first plurality of integrated sub-stations for operating on said second plurality of die-strips on an in-line basis to produce die-strip components; a third plurality of integrated sub-stations coupled to said second plurality of integrated sub-stations for testing said die-strip components; a fourth plurality of integrated sub-stations coupled to said third plurality of integrated sub-stations operating on tested die-strip components; a manufacturing execution system coupled to said first, second, third and fourth pluralities of integrated sub-stations for managing said die strips and said die-strip components; and a plurality of automated carriers configured to automatically provide said second plurality of die-strips from said first plurality of sub-stations to said second plurality of sub-stations in an in-line fashion, to automatically provide said die-strip components from said second plurality of sub-stations to said third plurality of sub-stations in an in-line fashion, and to automatically provide said tested die-strip components from said third plurality of sub-stations to said fourth plurality of sub-stations in an in-line fashion.