Patent ID: 8520679

Claim:
A system comprising: a memory to store a plurality of link identifiers at a respective plurality of memory addresses; and logic, at least partially implemented in hardware, to: receive a data unit, determine data associated with a plurality of fields of the data unit, the determined data including: first data associated with an Internet Protocol (IP) source address associated with the data unit, second data associated with an IP destination address associated with the data unit, and third data associated with at least one of a Transmission Control Protocol (TCP) port number associated with the data unit or a User Datagram Protocol (UDP) port number associated with the data unit, generate a particular memory address, of the respective plurality of memory addresses, based on hashing a sum of the first data, the second data, and the third data, the logic, when generating the particular memory address, being further to: determine a quantity of memory addresses included in the respective plurality of memory addresses, determine a first quantity of bits needed to express the quantity of memory addresses, determine a binary representation of the sum of the first data, the second data, and the third data, the binary representation of the sum including a second quantity of bits that is larger than the first quantity of bits, remove one or more bits from the binary representation of the sum of the first data, the second data, and the third data to form a modified binary representation, the modified binary representation including only the first quantity of bits, and use, as the particular memory address, the modified binary representation, identify a particular link identifier, of the plurality of link identifiers, stored at the particular memory address, and cause the data unit to be transmitted based on the particular link identifier.