Patent ID: 7189626

Claim:
A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device comprising, forming a layer of a first conductive material over a substrate, depositing an insulating layer over said first conductive material and said substrate, forming an opening in said insulating layer to expose at least a portion of said first conductive material, depositing a second conductive material over said insulating layer and within said opening, removing portions of said second conductive material to form a conductive area within said opening, recessing said conductive area within said opening to a level below an upper surface of said insulating layer, forming a cap of a third conductive material over the recessed conductive area within said opening, said third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.