Patent ID: 7715246

Claim:
A memory device, comprising: a memory segment including at least a memory cell and a local sense amp, wherein the memory cell includes a pass transistor and a capacitor as a storage element, wherein an insulation layer of the capacitor is etched or not by a contact mask during fabrication for realizing a mask ROM; the local sense amp is connected to the memory cell through a local bit line, wherein the local sense amp is composed of a write transistor connecting to the local bit line and a write bit line, a pre-charge transistor for pre-charging the local bit line, a local amplify transistor for reading the local bit line, an amplify enable transistor for enabling the local amplify transistor, and the amplify enable transistor is connected to a read bit line; and a buffered data path for writing and reading a stored data in the memory cell, wherein the buffered data path is divided into a forwarding write line and a returning read line by disabling a tri-state inverter in a global sense amp including a read circuit and a write circuit, wherein the read circuit is composed of the tri-state inverter for connecting to the returning read line, a common source amplifier for reading the read bit line, and a read inverter for generating a read output based on one of outputs from the tri-state inverter or the common source amplifier; the write circuit is composed of a receiving gate for receiving the forwarding write line, a pre-set transistor for pre-setting the write bit line, and a write buffer which is controlled by the receiving gate, wherein the write buffer includes a pull-up portion for inhibiting program and a pull-down portion for executing program through the write bit line, where the pull-down portion includes a feedback transistor for cutting off a current path after the capacitor is blown when programming, and the feedback transistor receives the read output from the read inverter; and an output latch circuit receiving the read output of the read inverter as well; and a latch control circuit generating a locking signal which is generated by a reference signal based on at least a reference memory cell, in order to lock the output latch circuit.