Patent ID: 7697542

Claim:
An apparatus comprising: a memory to store a scheduling data structure for a schedule for N resources, wherein: N>1; the scheduling data structure comprises M records; M>1; each of the M records represents a different one of M slots in the schedule; and each of the M slots is allocated to one of the N resources; and a scheduler comprising: a read circuit to read a record indicated by an index; a select circuit to select the resource allocated to the slot represented by the record read by the read circuit; and an index circuit to generate the index based on a previous record read by the read circuit, wherein: the index circuit comprises: an availability circuit to determine which of the N resources are available; a next available resource circuit to select the available resource that occurs next in the schedule based on the previous record; and a resource order circuit to identify the record representing the next slot allocated to the selected available resource based on the previous record, and to generate the index to indicate the identified record; each of the N resources occurs in the schedule WN times; and M = ∑ i = 0 N - 1 ⁢ ⁢ W i .