Patent ID: 7288792

Claim:
A semiconductor device, comprising: a substrate; a first semiconductor film positioned over the substrate; a first wiring positioned over the substrate; a first insulating layer positioned over the first semiconductor film and the first wiring; a gate electrode positioned over the first insulating layer, the gate electrode being overlapped with the first semiconductor film; a second wiring positioned over the first insulating layer, the first wiring being overlapped with the second wiring, the first and second wirings being electrically connected to each other via a first contact hole that is formed in the first insulating layer; a second insulating layer positioned over the gate electrode and the second wiring; and a third wiring positioned over the second insulating layer, the third wiring overlapped with the second wiring, the second and the third wirings being electrically connected to each other via a second contact hole that is formed in the second insulating layer; a source electrode positioned over the second insulating layer, the source electrode overlapped with the first semiconductor film, the source electrode and the first semiconductor film being electrically connected to each other via a third contact hole that is formed in the first and second insulating layers; and a drain electrode positioned over the second insulating layer, the drain electrode overlapped with the first semiconductor film, the drain electrode and the first semiconductor film being electrically connected to each other via a fourth contact hole that is formed in the first and the second insulating layers.