Patent ID: 8735972

Claim:
A static random access memory (SRAM) cell, comprising: a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D); a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D; a second pull-up FET having first and second S/Ds; a first gate electrode common to said first pull-down FET and said first pull-up FET and physically and electrically contacting said first S/D of said second pull-up FET, said first S/D of said second pull-up FET having a first end adjacent to said first gate electrode and a opposite second end adjacent to a third gate electrode, said first gate electrode extending over and electrically and physically contacting an end wall of said first end of said first S/D of said second pull-up FET and extending over an adjacent top surface of said first end of said first S/D of said second pull-up FET; a second gate electrode of said first pass gate FET; said third gate electrode common to said second pull-down FET and said second pull-up FET and physically and electrically contacting said first S/D of said first pull-up FET, said first S/D of said first pull-up FET having a first end adjacent to said third gate electrode and a opposite second end adjacent to said first gate electrode, said third gate electrode extending over and electrically and physically contacting an end wall of said first end of said first S/D of said first pull-up FET and extending over an adjacent top surface of said first end of said first S/D of said first pull-up FET; and a fourth gate electrode of said second pass gate FET.