Patent ID: 7072349

Claim:
A method of extending a FIFO buffer in a physical layer device of an Ethernet system having data terminal equipment (DTE) and a media access control (MAC) and connected by a media independent interface (MII) to the physical layer device comprising the steps of: determining an increased speed of a link partner within the Ethernet system in communication with data terminal equipment (DTE) using a first packet received within the FIFO buffer by initially filling the FIFO buffer substantially half-full with the first packet and if the link partner has been found to be faster, reconfiguring a half-full pointer used with the FIFO buffer; and optimizing subsequent reading of the FIFO buffer based on the increased speed of the link partner for enhancing an inter-packet gap space usage by using toggle bits as control bits to identify slots as valid or not such that a FIFO read/write control circuit can begin reading the FIFO buffer when a second or subsequent packet initially arrives.