Patent ID: 8175138

Claim:
A power efficient FHSS (Frequency Hopping Spreading Spectrum) base-band hardware architecture, comprising a digital wireless transceiver, a bi-directional data interface, a clock recovery circuit, a correlator, a MCU (Micro Control Unit), a timing_event controller, a series-parallel data converter, a DMA (Direct Memory Access) block, a coder, a transceiver controller and an oscillation circuit; wherein, the digital wireless transceiver enables receiving of signals; and the bi-directional data interface is connected to the digital wireless transceiver, the clock recovery circuit is connected to the bi-directional data interface to filter out noise on an external receiving signal and recover a sample clock for filtered receiving data, the correlator is connected to the clock recovery circuit, the MCU is connected to the correlator, the DMA block and the coder, the timing_event controller is connected to the correlator, the series-parallel data converter and the oscillation circuit, and the series-parallel data converter is connected to the correlator, the MCU, the timing_event controller and the DMA, thereby enabling the receiving of signals.