Patent ID: 7932129

Claim:
A method for manufacturing a memory cell, the method comprising: forming a bottom electrode having a top surface; forming an insulator over the bottom electrode, and a top electrode over the insulator, the insulator and the top electrode having a side intersecting the top surface of the bottom electrode; and forming a programmable resistive memory element on the side of the insulator and the top electrode and electrically coupled to the top surface of the bottom electrode; wherein forming the programmable resistive memory element comprises: depositing a layer of programmable resistive material on the side of the insulator and to electrode, and on the top surface of the bottom electrode; anisotropically etching the layer of programmable resistive material to leave a remaining portion of programmable resistive material on the side of the insulator and the top electrode, and so that a bottom surface of the remaining portion of programmable resistive material contacts the top surface of the bottom electrode; forming a mask over the remaining portion of programmable resistive material; and selectively etching the remaining portion of the programmable resistive material using the mask as an etch mask.