Patent ID: 8415796

Claim:
A semiconductor device, comprising: a semiconductor substrate including: a connection pad; a passivation layer having an opening portion exposing the connection pad; and a bump electrode formed on the connection pad; a first insulating layer formed on the passivation layer, and arranged to a lateral direction of the bump electrode; a second insulating layer formed on the first wiring layer; a via hole formed in the second insulating layer, and reaching the first wiring layer; a second wiring layer formed on the second insulating layer, and connected to the first wiring layer through a via conductor formed in the via hole, wherein the via conductor which connects the first wiring layer and the second wiring layer is formed of a conductive paste or a solder; a solder resist in which an opening portion is formed on a connection part of the second wiring layer; and an external connection terminal connected to the connection part of the second wiring layer; wherein an elastic modulus of the second insulating layer is set lower than an elastic modulus of the first insulating layer.