Patent ID: 8193846

Claim:
An apparatus comprising: a delay chain to generate a plurality of delayed signals from a clock signal that propagates through the delay chain, the delay chain having a plurality of taps for the delayed signals including a first tap closer to a clock signal input than a second tap, the clock signal being powered by a supply voltage of the apparatus; a multiplexer to sequentially couple selected delayed signals of the plurality of delayed signals to an output line with a pre-charge voltage that is lower than the supply voltage of the apparatus; and a pre-charge controller including: an input coupled to the output line; and an output responsive to each edge of the selected delayed signals; wherein the pre-charge controller is configured to vary a delay between edges of the selected delayed signals, and wherein the pre-charge voltage is selected to reduce a switch delay time from the taps of the delay chain to the output line compared to a supply voltage delay time based on the supply voltage, and the multiplexer is configured based on the reduced switch delay time to couple a clock edge at the second tap of the delay chain to the output line after coupling the clock edge at the first tap of the delay chain to the output line before the clock edge reaches the second tap of the delay chain.