Patent ID: 7132862

Claim:
An analog buffer comprising: a first comparing unit calibrating a voltage change of a first output terminal upon receiving an analog signal through a first switch and a first capacitor; a second switch connected between a first input terminal and the first output terminal of the first comparing unit; a second comparing unit calibrating a voltage change of a second output terminal upon receiving a first output signal of the first comparing unit through a second capacitor; a third switch connected between a second input terminal and the second output terminal of the second comparing unit; a third comparing unit calibrating a voltage change of a third output terminal upon receiving an output signal of the second comparing unit; a fourth switch connected to the third output terminal of the third comparing unit and between the first switch and the first capacitor; and fifth and sixth switches that respectively supply a source voltage and a ground potential to the third comparing unit or that respectively cuts off the source voltage and the ground potential from the third comparing unit.