Patent ID: 7408909

Claim:
An apparatus comprising a processor to enable a determined number of receivers of a multiple-inputs-multiple-outputs transmitters-receivers system according to a request to enable the determined number of receivers, wherein the processor is able to control a request-to send/clear-to-send network access mechanism, wherein the request-to send/clear-to-send network access mechanism comprises: a multiple-in-multiple-out-request-to send frame that includes the request to enable determined number of receivers; and a multiple-in-multiple-out-clear-to-send frame to acknowledge the multiple-in-multiple-out-request-request-to send frame, wherein the multiple-in-multiple-out-request-to-send message comprises: a first duration field to block transmission of a legacy station; a second duration field to block a high throughput station; and a multiple-in-multiple-out field that include a number of receivers to be enabled.