Patent ID: 7994957

Claim:
An apparatus comprising: a digital to analog converter (DAC) module to receive an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency, the DAC module comprising: an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal; wherein the first DAC cell comprises a first latch unit to latch the first digital signal, the second DAC cell comprises a second latch unit to latch the second digital signal, and timing of latching the first digital signal by the first latch unit and timing of latching the second digital signal by the second latch unit are controlled by a same control signal.