Patent ID: 7858468

Claim:
A method comprising: providing an integrated circuit having a metal-containing conductive interconnect; forming an electrical insulator material over the integrated circuit; providing a substrate containing a semiconductor material exhibiting a first conductivity type; placing a dopant in only a portion of the semiconductor material; activating the dopant to provide a doped region containing the activated dopant, the doped region exhibiting a second conductivity type opposite the first conductivity type and the doped region providing a junction with a portion of the semiconductor material still exhibiting the first conductivity type; after activating the dopant, bonding the substrate to the insulator material; removing at least some of the substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and after the removing, forming a memory cell having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction, the bit line and the word line overlapping at a cross-point, and the access diode and memory element extending between the word line and the bit line at the cross-point.