Patent ID: 7168020

Claim:
A device for testing an embedded phase-locked loop (PLL) circuit embedded in an IC chip, comprising: an external tester disposed outside said IC chip for providing an external clock signal for said PLL circuit to generate a test PLL clock signal of a first frequency, and additionally providing a test clock signal of a second frequency; a test circuit electrically connected to said embedded PLL circuit and said tester for, sampling said PLL clock signal with said test clock signal to generate a first sampled signal, sampling said first sampled signal with said test clock signal to generate a second sampled signal, and logically operating said first sampled signal and said second sampled signal, wherein said second clock frequency has a correlation with said first frequency, and a logic operational result of said first sampled signal and said second sampled signal is directly referred to by said external tester to determine whether said embedded PLL circuit is in a normal operation condition.