Patent ID: 8270236

Claim:
A semiconductor memory device, comprising: a plurality of memory banks that each comprise a plurality of memory cell arrays; a plurality of sense amplification units corresponding to the memory banks and configured to sense data corresponding to a selected memory cell and amplify the sensed data; and a common delay unit commonly coupled to the memory banks and configured to receive a plurality of bank active signals, delay a selected one of the plurality of bank active signals by a predetermined time using a common delay path, and generate the delayed bank active signal as an operation control signal for controlling one of the sense amplification units, wherein each of the plurality of bank active signals activates a corresponding one of the memory banks, wherein the common delay unit comprises: a common input unit configured to receive the bank active signals; and a delay configured to delay an output signal of the common input unit by the predetermined time to output a delayed signal as the operation control signal, wherein an output node of the delay is coupled to inputs of all of the sense amplification units to supply the operation control signal.