Patent ID: 7000078

Claim:
A computer system comprising: a memory system where at least some of the memory is designated as shared memory; a transaction-based bus coupled to the memory system wherein the transaction- based bus includes a cache coherency transaction defined within its transaction set; a processor having a cache memory, the processor coupled to the memory system through the transaction based bus; a plurality of system components other than the processor coupled to the transaction-based bus, wherein the system components access the memory system directly through the transaction based bus, but do not access the cache memory directly through the transaction based bus; a request issued by one of the plurality of system components and addressed to the processor, wherein the request indicates a request to perform a cache coherency operation; and wherein the processor is configured to respond to the request by treating the request as an explicit command to perform the cache coherency operation wherein the processor response to the request comprises executing the cache coherency operation without the assistance of instructions executed on the processor.