Patent ID: 8190808

Claim:
An integrated circuit, comprising: first, second, third and fourth storage arrays, arranged in respective quadrants of the integrated circuit, the first and fourth storage arrays in diagonally-opposite quadrants and the second and third storage arrays in diagonally-opposite quadrants, each storage array serviced by a row decoder and a column decoder; a controller to provide in response to a single activation request (a) row access signals to the row decoder for the first storage array and to the row decoder for the fourth storage array, and (b) subsequently, to provide row access signals to the row decoder for the second storage array and to the row decoder for the third storage array, and to, subsequent to providing the row access signals, to provide in response to a single read request, column access signals to the column decoder for the first storage array and to the column decoder for the fourth storage array, and subsequently, (d) column access signals to the column decoder for the second storage array and to the column decoder for the third storage array; and a serializer to receive, corresponding to the row activation request and read request, first parallel data from the first and fourth storage arrays, and second parallel data from the third and second storage arrays, and to combine the first and second parallel data into a series of data for serial transmission.