Patent ID: 6922443

Claim:
A signal transmission circuit for transmitting a digital signal from a first circuit block to a second circuit block via a signal line in synchronization with a clock signal that repeats a first logic level indicating a preparation period and a second logic level indicating a transmission period, the first circuit block comprising a transmitting circuit including: a transmitting capacitor; an input switch for supplying an input digital signal to the transmitting capacitor for each preparation period so as to set a voltage in accordance with a logic level of said input digital signal in the transmitting capacitor at each preparation period; and a transmitting switch for connecting the transmitting capacitor to the signal line for each transmission period so as to generate a small voltage change in the signal line at each transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor that is set during a preceding preparation period, the second circuit block comprising a receiving circuit including: an inverter connected to the signal line; an equalizing switch for short-circuiting an input terminal and an output terminal of the inverter so as to set a voltage of the signal line to a predetermined voltage at each preparation period; and a latch for supplying an output digital signal obtained by performing logic amplification of a voltage of the output terminal of the inverter at each transmission period.