Patent ID: 7678644

Claim:
A method for fabricating DRAM cells, the method comprising: providing a semiconductor substrate; forming a plurality of NMOS transistor gate structures, each of the NMOS gate structures including an NMOS source region and an NMOS drain region and a plurality of PMOS gate structures, each of the PMOS gate structures including a PMOS source region and a PMOS drain region, the NMOS gate structures being formed on P-type well regions and the PMOS gate structures being formed on N-type well regions; forming a blanket nitride layer overlying each of the NMOS gate structures, overlying each of the PMOS gate structures, overlying the PMOS source region and the PMOS drain region for each of the PMOS gate structures, and overlying the NMOS source region and the NMOS drain region for each of the NMOS gate structures, the nitride layer forming sidewall spacers on each of the NMOS gate structures and on each of the PMOS gate structures; forming a blanket oxide layer overlying the nitride layer, the blanket oxide layer covering an entirety of the nitride layer; removing portions of the oxide layer overlying the nitride layer on the PMOS source region and the PMOS gate region for each of the PMOS gate structures and overlying the nitride layer on the NMOS source region and the NMOS gate region for each of the NMOS gate structures to form oxide spacers on each of the NMOS and PMOS gate structures; forming a first protective layer using a first mask structure overlying the NMOS gate structures overlying the P-type well regions; implanting P type impurities into the PMOS source region and the PMOS drain region associated with each of the PMOS gate structures using at least the oxide spacers on each of the NMOS and PMOS gate structures as blocking structures; removing the first protective layer overlying the NMOS gate structures; forming a second protective layer using a second mask structure overlying the PMOS gate structures, the PMOS gate structures on the N-type well regions; implanting N-type impurities into the NMOS source region and the NMOS drain region into each of the NMOS transistors; selectively removing the oxide spacers while exposing the nitride layer to increase a spacing to a predetermined width between two or more of the NMOS gate structures; forming an interlayer dielectric layer overlying each of the gate structures while filling a gap between two or more of the NMOS gate structures; and steam annealing the interlayer dielectric layer to finish the interlayer dielectric layer, the interlayer dielectric layer being free from any gaps therein.