Patent ID: 8399336

Claim:
A method for fabricating a 3D integrated circuit, the method comprising the steps of: providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias; providing a first active circuitry layer wafer including active circuitry, a second wiring layer, and through-silicon vias; bonding the first active circuitry layer wafer face down to the interface wafer, the second wiring layer of the first active circuitry layer wafer being directly bonded to the first wiring layer of the interface wafer; after bonding the first active circuitry layer wafer face down to the interface wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer; after removing the first portion of the first active circuitry layer wafer, fabricating a third wiring layer on the second portion of the first active circuitry layer wafer; providing a second active circuitry layer wafer including active circuitry and a fourth wiring layer; bonding the second active circuitry layer wafer face down to the third wiring layer, the fourth wiring layer of the second active circuitry layer wafer being directly bonded to the third wiring layer of the first active circuitry layer wafer; after bonding the second active circuitry layer wafer face down to the third wiring layer, removing a first portion of the second active circuitry layer wafer such that a second portion of the second active circuitry layer wafer remains attached to the second wiring layer; after removing the first portion of the second active circuitry layer wafer, fabricating a fifth wiring layer on the second portion of the second active circuitry layer wafer; providing a base wafer, the base wafer including a sixth wiring layer; bonding the fifth wiring layer face down to the base wafer, the fifth wiring layer of the second active circuitry layer wafer being directly bonded to the sixth wiring layer of the base wafer; and after bonding the fifth wiring layer face down to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations comprising solder bumps on the interface layer, the solder bumps being coupled through the through-silicon vias in the interface layer to the first wiring layer, wherein the first active circuitry layer wafer is a memory layer comprising embedded memory and the second active circuitry layer wafer is a logic layer comprising control and/or logic circuitry.