Patent ID: 8549463

Claim:
A method for updating a processing system design on a first integrated circuit into a at least one updated processor design on respective second integrated circuits, comprising: arranging an original processing system design in a substrate in accordance with a substantially fixed layout, wherein the original processing system design includes original data resources for processing data and includes bus subsystems having first memory mapped control registers for controlling the data resources of the original processing system design and second memory mapped control registers for controlling data resources not of the original processing system design, the original processing system design further including a die expansion bus coupled to the bus subsystems and adapted to couple to supplemental bus systems of a supplemental processing system; constructing a first integrated circuit with the original processing system design; arranging at least one updated processing system design in a substrate including the original processing system design and a supplemental processing system design with a substantially fixed layout, wherein the supplemental processing system design includes supplemental data resources for processing data and includes supplemental bus subsystems having at least one of the second memory mapped control registers for controlling the data resources of the supplemental processing system, the supplemental bus subsystems arranged to couple to the die expansion bus wherein the original processing system design is operable to control the supplemental data resources of the supplemental processing system design by accessing a corresponding secondary memory mapped control registers associated with the supplemental bus subsystems of the supplemental processing system design, and wherein the layout of the supplemental processing system design is generated after the layout of the original processing system design has been substantially fixed; and constructing at least one second integrated circuit with a corresponding supplemental processing system design.