Patent ID: 7884872

Claim:
A method for driving a solid-state imaging apparatus that is provided with: a plurality of photoelectric conversion portions for accumulating signal charges in accordance with an amount of incident light, a transfer portion for reading out signal charges that have been accumulated in the photoelectric conversion portions, and an excess charge draining portion for draining, from the photoelectric conversion portions, excess charges in an amount exceeding a saturation charge amount that is set by a reference voltage, the method comprising: performing selectively one of a full pixel mode in which signal charges accumulated in the photoelectric conversion portions are detected individually for each pixel and a pixel mixing mode in which signal charges of a predetermined number of pixels are mixed to be detected; supplying the excess charge draining portion, in the full pixel mode, with the reference voltage having the same value during a charge accumulation period for accumulating charges in the photoelectric conversion portions and a read transfer period for read transferring charges by the transfer portion; and supplying the excess charge draining portion, in the pixel mixing mode, with the reference voltage having a low level during the charge accumulation period and with the reference voltage having a high level higher than the low level during the read transfer period, wherein the reference voltage in the full pixel mode and the reference voltage having the low level in the pixel mixing mode are supplied from a first reference voltage generating circuit, the reference voltage having the high level in the pixel mixing mode is supplied by a combination of the first reference voltage generating circuit and a second reference voltage generating circuit, so as to have a waveform obtained by superimposing a control pulse that is supplied from a timing generating circuit upon receipt of a signal output from the second reference voltage generating circuit on a voltage that is supplied from the first reference voltage generating circuit, the second reference voltage generating circuit is provided with a resistance dividing circuit in which a plurality of resistors are connected in series between an input terminal and the ground, with the input terminal being supplied with a power supply voltage, and the first and the second reference voltage generating circuits are provided on a common semiconductor substrate chip on which the photoelectric conversion portions, the transfer portion and the excess charge draining portion are provided, with the timing generating circuit being separated from the common semiconductor substrate chip.