Patent ID: 8607183

Claim:
A method of simplifying metal shapes in an integrated circuit, the method comprising: receiving, with a processor, an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto, the vias extending orthogonally to the at least one metal layer to connect to other metal layers above and below the at least one metal layer; grouping, with the processor, vias which are coupled to a same wire in the at least one metal layer and which are spaced from one another in the preferred direction by less than a desired separation distance to form via clusters; and defining in the at least one metal layer, with the processor, a metal via cluster shape about each via cluster and about each via which is not part of a via cluster, the via cluster shape of each via cluster connecting all vias of the via cluster to one another, and the via cluster shape of each via which is not part of a via cluster connecting to the via.