Patent ID: 8890330

Claim:
A semiconductor package comprising: a substrate; a first memory chip stacked on a first portion of the substrate; a controller chip stacked on a second portion of the substrate, the second portion being different from the first portion; at least one first bonding wire directly connecting the first memory chip with the controller chip; and at least one second bonding wire connecting the first memory chip with the substrate, the at least one second bonding wire being electrically connected with the at least one first bonding wire, wherein the first memory chip includes at least one first electrode pad, the controller chip includes at least one second electrode pad, and the at least one first bonding wire directly connects the at least one first electrode pad with the at least one second electrode pad, and wherein the controller chip further comprises at least one redistribution pad and at least one redistribution line configured to directly connect the at least one second electrode pad with the at least one redistribution pad, and wherein the substrate includes at least one bonding finger and the at least one second bonding wire directly connects the at least one bonding finger with the at least one redistribution pad.