Patent ID: 8566768

Claim:
A method of searching for desired clock frequency for integrated circuit-based design, comprising: (a) receiving timing result of a hardware synthesis job executed based on a code specifying hardware design; (b) automatically generating without modifying the code, one or more different timing constraints specifying respectively one or more different clock frequencies than used in the hardware synthesis job; (c) automatically spawning, by a processor, one or more instances of the hardware synthesis job to run with the respective one or more different timing constraints; (d) repeating the steps of automatically generating and automatically spawning until a termination criterion is met, or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether said one or more instances of the hardware synthesis job met their respective timing constraints, or combination of both the termination criterion is met and the desired successful timing constraint is identified, wherein if the received timing result indicates that a timing constraint is not satisfied, the generating at (b) includes generating a first new timing constraint specifying higher clock frequency than a previously specified clock frequency and a second new timing constraint specifying lower clock frequency than the previously specified clock frequency but higher than clock frequency of a last hardware synthesis job that satisfied its timing constraint, and the automatically spawning at (c) includes running a first instance of the hardware synthesis job with the first new timing constraint and a second instance of the hardware synthesis job with the second new timing constraint, without modifying the code, (c1) if both the first instance and the second instance do not meet the respective first new timing constraint and the second new timing constraint, selecting the clock frequency of the last hardware synthesis job that satisfied its timing constraint, and (c2) if either or both of the first instance and the second instance's timing criterion is satisfied, generating the different timing constraint specifying higher clock frequency than either or both of the first instance or the second instance that satisfied their respective timing criteria and repeating running of the hardware synthesis job with the newly specified clock frequency without modifying the code, and the repeating at (d) includes repeating (a), (b), (c), (c1) and (c2), until a termination criterion is met, wherein highest clock frequency among all hardware synthesis jobs run until the termination criterion is met is selected.