Patent ID: 8245015

Claim:
A processor comprising: a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads; an instruction issuing section configured to issue instructions to the plurality of executing sections, the instructions comprising an instruction-synchronizing instruction, wherein the instruction-synchronizing instruction instructs that instructions preceding the instruction-synchronizing instruction complete before issuance of instructions succeeding the instruction-synchronizing instruction; and an instruction sync monitoring section configured to, when the instruction-synchronizing instruction is issued to one or more executing sections of the plurality of executing sections, monitor completion of execution of the instruction-synchronizing instruction for each of the one or more executing sections to detect completion of execution of preceding instructions preceding the instruction-synchronizing instruction for a thread to which the instruction-synchronizing instruction belongs, wherein: the instruction-synchronizing instruction comprises a thread identifier of the thread that is a target of the instruction-synchronizing instruction and an identifier of each of the one or more executing sections to which the instruction-synchronizing instruction has been issued; and after issuing the instruction-synchronizing instruction, the instruction issuing section stops issuance of succeeding instructions succeeding the instruction-synchronizing instruction for the thread identified by the thread identifier in the instruction-synchronizing instruction, until the completion of execution of the preceding instructions for the thread identified by the thread identifier in the instruction-synchronizing instruction is detected by the instruction sync monitoring section.