Patent ID: 7631149

Claim:
A system comprising: a processor that is operable alternately in either a microprocessor mode or a DSP mode; a plurality of cache memories, including a first cache memory and a second cache memory, wherein a latency of data accesses to the first cache memory is less than a latency of data accesses to the second cache memory and wherein a data capacity of the first cache memory is less than a data capacity of the second cache memory; wherein in a first mode, for each data access, the system is configured to access the first cache memory prior to accessing the second cache memory, and in a second mode, for each data access, the system is configured to bypass the first cache memory and directly access the second cache memory; wherein in response to the processor operating in the microprocessor mode, each of a plurality of data accesses performed while the processor is operating in the microprocessor mode is performed in the first mode, and wherein in response to the processor operating in the DSP mode, each of a plurality of data accesses performed while the processor is operating in the DSP mode is performed in the second mode.