Patent ID: 7245553

Claim:
A memory device, comprising: a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device; a column address circuit operable to receive and decode column address signals applied to the external address terminals; a memory cell array operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals; a strobe generator circuit operable to generate a first periodic strobe signal and a second periodic strobe signal, the second strobe signal having signal transitions that are offset from signal transitions of the first strobe signal by 90 degrees, the second strobe signal being coupled to an external strobe signal output terminal of the memory device; a data path circuit operable to couple data signals corresponding to the data between the array and data bus terminals of the memory device, the data path circuit comprising: an output latch having an input terminal coupled to the array, an output terminal coupled to the data bus terminals, and a clock terminal coupled to receive the first strobe signal from the strobe generator circuit and to couple read data bits from the output latch to the data bus terminals responsive to a transition of the first strobe signal; and an input latch having an input terminal coupled to the data bus terminals, an output terminal coupled to the array, and a clock terminal coupled to receive the second strobe signal from a strobe signal input terminal; and a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.