Patent ID: 7330926

Claim:
An interruption control system for use with a computer system, the computer system comprising a CPU, a north bridge module including a north bridge chip, a south bridge chip and a first peripheral device, the interrupt control system comprising: a programmable interrupt controller (PIC) disposed in the south bridge chip, coupled to the first peripheral device, an interrupt status indicating pin of the north bridge module and the CPU, and optionally triggered with an interrupt status indicating signal received through the interrupt status indicating pin or by the first peripheral device to send an interrupt signal to the CPU via an interrupt request signal pin when the computer system is in a PIC mode; a first advanced programmable interrupt controller (APIC) disposed in the south bridge chip, coupled to the first peripheral device, disabled when the computer system is in the PIC mode, and enabled when the computer system is in an APIC mode to generate a first memory write cycle message to the CPU in response to the triggering of the first peripheral device; and a power management unit disposed in the south bridge chip, coupled to the CPU, the interrupt status indicating pin of the north bridge module and the PIC, and optionally triggered with the interrupt signal received from the PIC or the interrupt status indicating signal received from the interrupt status indicating pin of the north bridge module to change a state of a stop clock signal to awake the CPU from a power-saving state.