Patent ID: 7484199

Claim:
A method of reducing wirelength in a net of an integrated circuit design, comprising: identifying a plurality of sinks in the net to be interconnected with a source; forming two or more clusters of the sinks, wherein the forming of the clusters includes removing an overlap between two of the clusters by determining which of a plurality of horizontal cuts between sinks of the overlapping clusters and a plurality of vertical cuts between sinks of the overlapping clusters provides an optimum partition; inserting buffers at selected clusters; connecting buffers at selected clusters to sinks in respective clusters; connecting the source to at least a first buffer in a first one of the clusters; and connecting a first one of the sinks in the first cluster to at least a second one of the buffers in a second one of the clusters to create a buffer tree from the source to the sinks, wherein the connection between the first sink and the second buffer is the shortest distance from the second buffer to any sink outside of the second cluster.