Patent ID: 7596011

Claim:
An integrated circuit device comprising: a plurality of bit line pairs, wherein first and second bit lines within each of the plurality of bit line pairs are aligned with each other in an end-to-end arrangement, wherein the first bit lines are arranged consecutively adjacent to one another, and wherein the second bit lines are arranged consecutively adjacent to one another; a plurality of word lines associated with the first bit lines and the second bit lines, wherein a first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines; and a first plurality of multiplexers, each communicating with two adjacent bit lines within one of the first and second arrays, wherein each of the first plurality of multiplexers selectively outputs one of the two adjacent bit lines, wherein the first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.