Patent ID: 7102377

Claim:
A semiconductor test chip for thermal evaluation and reliability testing, said chip having alternate layers of metal and insulation with said layers of metal connected by conductive vias to an array of solder balls, comprising: a semiconductor chip arrangement having said array of solder balls subdivided into cells with each cell having a pattern of solder ball assignments to at least signal I/O, I/O voltage and power supply voltage functions; a plurality of individual resistive heaters formed in one of said alternate layers of metal at least one of which resistive heaters is arranged within each of said cells with each end of each said resistive heater having a conductive region for connection to respective ones of said conductive vias; and a first plurality of conductive vias respective ones of which act to connect one conductive region of each resistive heater of each cell to a first solder ball in the same cell with each said first solder ball of each cell having the same function assignment and a second plurality of conductive vias respective ones of which act to connect the other conductive region of each heater of each cell to a second solder ball in the same cell with each said second solder ball of each cell having the same function assignment other than the function assignment of said first solder ball.