Patent ID: 7763929

Claim:
A nonvolatile semiconductor memory device comprising: floating gates arranged on a semiconductor substrate in a matrix; source areas formed in a surface of the semiconductor substrate and each of which is shared by the floating gates adjacent to each other in a column direction; drain areas formed in the surface of the semiconductor substrate and each of which face the source area in the column direction with the floating gate interposed therebetween, the drain area being wider than the source area in the column direction; word lines each of which is continuously formed on the floating gates arranged in a row direction and within the same row; bit lines each of which is electrically connected to the drain area via a drain contact and provided above the word lines in the column direction with an interlayer insulating film interposed therebetween; diffusion layers each of which is formed on an inner wall portion of a trench made between the source areas adjacent to each other in the row direction within the same row and electrically connects the adjacent source areas together; source lines each of which is formed of the source areas and diffusion layers on the same row; an insulating layer which is formed on the diffusion layers and the source areas except for one of the source areas; and shield wires each of which is disposed on the insulating layer and along the source line, a top surface of the shield wire being lower than a top surface of the floating gate adjacent to the shield wire, the insulating layer being interposed between the source line and the shield wire, the shield wires being isolated from the source lines by the insulating layer except for one of the source areas.