Patent ID: 7791174

Claim:
A method of making a wafer translator having a silicon core, comprising: providing a silicon substrate having a first electrically conductive layer disposed on a first major surface thereof and a second electrically conductive layer disposed on a second major surface thereof; forming a plurality of through-holes in the silicon substrate having the first electrically conductive layer on the first major surface and the second electrically conductive layer on the second major surface; filling the plurality of through-holes with a dielectric material; disposing a first resin coated copper foil on the first electrically conductive layer of the first major surface of the silicon substrate and disposing a second resin coated copper foil on the second electrically conductive layer of the second major surface of the silicon substrate; forming at least one via opening through the dielectric filling in each of the dielectric filled through-holes; disposing a conductive filling in each of the via openings; planarizing the copper of the first resin coated copper foil to form a first planarized copper foil, and planarizing the copper of the second resin coated copper foil to form a second planarized copper foil; plating a third conductive layer on the first planarized copper foil, and plating a fourth conductive layer on the second planarized copper foil; etching a plurality of contact structure alignment marks in the fourth conductive layer in a predetermined pattern; plating a first nickel layer over the third conductive layer and a second nickel layer over the second conductive layer; plating a first gold layer over the first nickel layer and a second gold layer over the second nickel layer; disposing a plurality of contact structures on the second gold layer, the contact structures disposed in a predetermined spatial relationship to the contact structure alignment marks; removing portions of the first gold layer and the first nickel layer to form a first pattern, and removing portions of the second gold layer and second nickel layer form a second pattern, the first pattern exposing a portion of the first conductive layer and the second pattern exposing a portion of the second conductive layer; and chemically etching the exposed portions of the third and second conductive layers, and the copper and resin layers respectively underlying the first and fourth conductive layers.