Patent ID: 6965170

Claim:
A sub-assembly comprising a semiconductor chip and a chip carrier, said carrier comprising a) a core containing a voltage/ground plane, a first top signal plane forming the top of the core above the voltage/ground plane, the planes separated from one another by a layer of dielectric material; b) a second top signal plane above the first signal plane and separated from the first layer by a layer of dielectric material, and c) a conductive layer spaced from the second signal plane by a layer of dielectric material, the conductive layer forming the top surface of the carrier and being electrically coupled to the semiconductor chip positioned above the chip carrier, to deliver signals to and from the chip through the conductive layer to the top surface of the second signal plane; said chip having a planar surface, the edges of which create a footprint image on the carrier, the signals from the chip entering the carrier within the area of the footprint image, circuit lines on a surface of the second signal plane routing a first set of signals to a location outside the area of the footprint image and routing a second set of signals closer to an edge of the footprint area; the circuit lines coupled to microvias extending through the second signal plane down to the first signal plane, at least some of the second set of circuit lines being rerouted on the first signal plane to a location outside of the footprint area or to a location within the footprint area closer to an edge of the footprint area, the core having a plurality of conductive vias through which all of the signals are adapted to be transmitted between the chip and a printed wiring board.