Patent ID: 6927602

Claim:
A buffer circuit in a mixed-voltage circuit operating in a power supply voltage, comprising: a node; a driver circuit coupled to the node comprising at least a first PMOS transistor having a substrate, a drain, a source, and a parasitic diode between the drain and the substrate, the driver circuit having an on-state and an off-state and further comprising a pair of stacked transistors; a second PMOS transistor having a source and a drain, one of the source and drain of the second PMOS transistor being coupled to the substrate of the first PMOS transistor, wherein the second PMOS transistor is turned off when a first signal having a voltage level higher than the power supply voltage is provided on the node; and a gate-tracking circuit coupled to the node, and having a transistor whose gate is directly connected to each of the pair of stacked transistors.