Patent ID: 6995085

Claim:
A method for fabricating IC's comprising the following steps: (a) providing a substrate with a first insulating layer of silicon oxide over the substrate; (b) providing a first level of conducting material defined and embedded in a second insulating layer over the first insulating layer; (c) depositing a first intermetal dielectric layer over the second insulating layer; (d) patterning the first intermetal dielectric layer, forming via openings; (e) depositing and defining a metal barrier layer in the via openings; (f) coating with negative photoresist the top surface of first intermetal dielectric and filling the via openings; (g) exposing and developing the negative photoresist so that the negative photoresist remains in the via openings; (h) depositing a second intermetal dielectric layer; (i) patterning the second intermetal dielectric layer, forming trench openings; (j) stripping-off said negative photoresist, thus forming open trench and open via regions for subsequent conducting metal fill.