Patent ID: 8037383

Claim:
A semiconductor integrated circuit comprising; A. a substrate of semiconductor material; B. functional logic formed on the substrate, the functional logic including functional flip-flops; C. scan paths formed on the substrate, each scan path including a scan input bus for receiving test stimulus data to be applied to the functional logic, connections with the functional logic for applying stimulus data to the functional logic and receiving response data from the functional logic, a scan output bus for transmitting test response data obtained from the functional logic, and a control bus input for operating the parallel scan paths, each scan path including functional flip-flops of the functional logic that, in a test mode, are connected in series: and D. gating circuitry connected to the scan input bus, the scan paths, and the scan output bus, the gating circuitry having an enable input, and the gating circuitry in response to receiving one enable signal coupling the scan paths in series between the scan input bus and the scan output bus and in response to receiving another enable signal selectively coupling only one of the scan paths between the scan input bus and the scan output bus.