Patent ID: 8836036

Claim:
A method for fabricating a semiconductor device comprising: providing a substrate prepared with isolation regions; forming a gate stack having first and second sidewalls over a substrate; forming stressor diffusion extension regions within the substrate on opposed sides of the gate stack, wherein the stressor diffusion extension regions comprise a first concentration of stressor atoms incorporated into substitutional sites of diffusion extension regions; forming source/drain (S/D) stressor diffusion regions on opposed sides of the gate stack within the substrate, wherein the S/D stressor diffusion regions comprise a depth which is deeper than the diffusion extension regions and comprise the first concentration of stressor atoms incorporated into substitutional sites of S/D diffusion regions; forming a first stressor layer over the substrate after forming the stressor diffusion extension regions, the first stressor layer having a first stress value; performing a first anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the first anneal is conducted at a low temperature; and performing a second anneal with a laser based anneal to activate dopants in the S/D diffusion regions after the first anneal, wherein the first and second anneal prevent displacement of the stressor atoms having the first concentration from the substitutional sites and which are distributed throughout a width of diffusion extension and diffusion regions which extends from a sidewall of the gate to the isolation region.