Patent ID: 8643164

Claim:
An integrated circuit (IC) package structure, comprising: a fan-out wafer level integrated circuit package that includes an integrated circuit die having a plurality of terminals on a first surface of the integrated circuit die, a semiconductor material substrate having opposing first and second surfaces, the first surface of the semiconductor material substrate having a first electrically conductive feature, the second surface of the substrate having a second electrically conductive feature, the semiconductor material substrate having a first electrically conductive path through the semiconductor material substrate from the first electrically conductive feature to the second electrically conductive feature, a second surface of the integrated circuit die being attached to the first surface of the semiconductor material substrate, the semiconductor material substrate being a portion of a semiconductor wafer, a first layer of an insulating material that covers the first surface of the die and the first electrically conductive feature, and fills a space adjacent to at least one side of the die on first surface of the semiconductor material substrate, the first layer being a single layer of the insulating material, a second electrically conductive path through the insulating material coupled to the first electrically conductive feature, a wafer level redistribution interconnect on the first layer of the insulating material that has a first portion coupled to a terminal of the die through the first layer and a second portion that extends away from the first portion over the space adjacent to the die that is filled by the insulating material, the second portion being coupled to the second electrically conductive path, and a ball interconnect coupled to the second portion of the wafer level redistribution interconnect, wherein the ball interconnect is configured to be coupled to a printed circuit board such that the first surface of the integrated circuit die faces the printed circuit board; and an integrated circuit package mounted to the fan-out wafer level integrated circuit package.