Patent ID: 7069418

Claim:
A method for generation of instruction words in a digital processor having an instruction word memory wherein instruction words are arranged in rows, each instruction word having a plurality of instruction word parts, each driving a functional unit of said processor, comprising: deriving primary instruction words from a program code; combining said primary instruction words into a sequence of associated program words; reading an instruction word from a row of said instruction word memory determined by a reading row number; modifying said read instruction word by substituting an instruction word part with an information part of an associated program word; writing said modified instruction word part to a row of said instruction word memory determined by a writing row number; and outputting a completed instruction word to drive said functional units of said processor, wherein said reading row number and said writing row number are provided by respective reading row and writing row registers, and wherein a number of sequential reading row and writing row numbers are determined by contents of a block length register.