Patent ID: 6904572

Claim:
A computer-implemented method for designing a semiconductor integrated circuit, which optimizes the propagation delay oh path from a signal input terminal called a source, to a signal output terminal called a sink, on the same net, the method comprising: calculating the ratio of the total sum of a gate input load capacitance to the wiring capacitance of the path from the source to the sink as a process variation sensitivity relating to the capacitance component of the path to be designed from the source to the sink, based on a circuit design information of a gate level of the semiconductor integrated circuit to be designed; and optimizing the process variation sensitivity relating to the capacitance component of each path by enlarging a gap between neighboring wirings and adjusting a wiring capacitance load for a path in which the process variation sensitivity relating to the capacitance component is larger than the reference value in order to reduce the process variation sensitivity relating to the capacitance component of the path in order that the process variation sensitivities relating to the capacitance components of all the paths are smaller than a reference value.