Patent ID: 7308633

Claim:
In an integrated circuit of the type including an RRAM subsystem, the improvement comprising a master controller for the RRAM subsystem, the master controller including, an RRAM communication subsystem for communicating with a plurality of RRAM controllers, where each RRAM controller communicates with a given one of a plurality of RRAMs within the RRAM subsystem, a main control unit for selecting and implementing independently implemented test and repair operations on the plurality of RRAMs through the RRAM controllers, and a timer for determinig a maximum number of test and repair operations that can be implemented within a given time on a given one of the plurality of RRAMs, wherein the main control unit is further adapted to select and implement unique test vectors for different ones of the plurality of RRAM controllers, receive results from the plurality of RRAM controllers in response to the test vectors, and implement unique repair operations based on the results of the test vectors.