Patent ID: 7790525

Claim:
A method of forming an integrated circuit comprising the steps of: providing a substrate; forming an n-channel MOS transistor by: forming a first gate structure on a top surface of the substrate; and forming n-type source and drain regions adjacent to the first gate structure; forming a p-channel MOS transistor by: forming a second gate structure on a top surface of the substrate; and forming p-type source and drain regions adjacent to the second gate structure; and forming contacts on, and electrically connected to, the first gate structure, the n-type source and drain regions, the second gate structure and the p-type source and drain regions, wherein the contacts are formed on a pitch in the range 0.56·λ 1 /(n 1 ·NA 1 ) to 0.64·λ/(n·NA), wherein λ 1 is a wavelength of light used to generate a pattern for the contacts, and wherein n 1 is an index of refraction of a first medium between a first lens in a first photolithographic printer used to generate the pattern for the contacts and the integrated circuit and wherein NA 1 is a numerical aperture of the lens; forming a first set of metal lines, which contact and overlap the contacts, and which are formed on a pitch in the range 0.46·λ 2 /(n 2 ·NA 2 ) to 0.54·λ 2 /(n 2 ·NA 2 ), wherein λ 2 is a wavelength of light used to generate a pattern for the first set of metal lines, and wherein n 2 is an index of refraction of a second medium between a second lens in a second photolithographic printer used to generate the pattern for the first set of metal lines and the integrated circuit, and wherein NA 2 is a numerical aperture of the second lens.