Patent ID: 7581151

Claim:
A method for testing a first module and a second module on a same integrated circuit, the method comprising: assigning the first module to be tested, wherein the first module has a first state machine, wherein the first state machine is compatible with an IEEE 1149.1 standard, and wherein a transition of the first state machine from an UPDATE-DR state is solely dependent upon a first TMS signal; transferring first test data from the first module; assigning the second module to be tested, wherein the second module has a second state machine, wherein the second state machine is compatible with the IEEE 1149.1 standard, and wherein a transition of the second state machine from the UPDATE-DR state is solely dependent upon a second TMS signal; transferring second test data from the second module; using switching circuitry to control selection of the first and second modules; tracking state history of the first state machine using a first duplicate state machine; and tracking state history of the second state machine using a second duplicate state machine, wherein the switching circuitry uses the state history of the first and second state machines to determine when the first module is to be coupled to a plurality of integrated circuit terminals and to determine when the second module is to be coupled to the plurality of integrated circuit terminals.