Patent ID: 8254728

Claim:
A system for organizing data flow for two-dimensional image processing comprising: an address engine for generating addresses for reading image data from and writing image data to an external memory, the address engine comprising: a DMA unit for interfacing with the external memory, and a data flow organizer module for re-ordering the image data read from the external memory and generating data flows for the image data to be processed; and a data processing module for processing the image data read from the external memory, wherein the DMA unit comprises: a plurality of first read address generation units for generating read addresses for reading the image data from the external memory, and at least one first write address generation units for generating write addresses for writing the image data to the external memory, and wherein the data flow organizer module comprises: a cache memory divided into a plurality of virtual memories, a lookup table for storing function data, a plurality of second read address generation units for generating read addresses for reading data from the cache memory, each of the second read address generation units corresponding to a respective one of the plurality of virtual memories, a plurality of second write address generation units for generating write addresses for writing data to the cache memory, each of the second write address generation units corresponding to a respective one of the plurality of virtual memories, a control and synchronization circuit for ensuring that the data is in the cache memory and push the data to the data processing module, when need, and a plurality of pointer registers for ensuring that reading each memory cell in the cache memory is performed later than writing to said memory cell.