Patent ID: 7045422

Claim:
A method for fabricating a semiconductor gate structure, comprising: depositing a plurality of sacrificial layers on a semiconductor substrate, the plurality at least comprising a sacrificial oxide layer, a doped polysilicon layer and a silicon nitride layer; patterning the plurality of sacrificial layers to form at least one cutout in the plurality of sacrificial layers for uncovering the semiconductor substrate; forming a sidewall spacer over sidewalls of the plurality of sacrificial layers in the at least one cutout, a predetermined thickness of the sidewall spacer being set by the dopant concentration of the dopes polysilicon layer; forming a gate dielectric on the semiconductor substrate in the at least one cutout; providing a gate electrode in the at least one cutout in the plurality of sacrificial layers; and removing the plurality of sacrificial layers for uncovering the gate electrode surrounded by the sidewall spacer.