Patent ID: 7111176

Claim:
A system comprising: a processor that supports two or more operating modes with different levels of privilege, including a ring 0 operating mode and a higher ring operating mode; a chipset responsive to the processor, wherein the chipset supports communication between the processor and a memory; configuration storage within the processor to store configuration parameters comprising: a first configuration setting to define an isolated memory area within the memory; and a second configuration setting to switch the processor between an isolated execution mode within the ring 0 operating mode and a non-isolated execution mode within the ring 0 operating mode; an isolated execution circuit within the processor to generate isolated bus cycles when the processor executes in the isolated execution mode, wherein the isolated bus cycles enable a module to access a resource that is only accessible from the isolated execution mode of the ring 0 operating mode; and a logical processor counter in the chipset that is updated in a first direction in response to a logical processor entry to the isolated execution mode and is updated in a second direction in response to a logical processor withdrawal from the isolated execution mode.