Patent ID: 6885044

Claim:
An array of nonvolatile memory cells, each cell comprising a first conductive gate, two conductive floating gates, and two source/drain regions, the source/drain regions being regions of a first conductivity type in a semiconductor substrate; wherein in each row of the array, all the first conductive gates are connected together; wherein in each column of the array, for any two consecutive memory cells, one source/drain region of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the first conductivity type in the semiconductor substrate, each contiguous region providing source/drain regions to only two of the memory cells in said column of the memory cells; wherein the array also comprises a plurality of bitlines overlying the semiconductor substrate, each bitline being connected to the source/drain regions of a plurality of the memory cells of a column of the array.