Patent ID: 7592862

Claim:
A reference voltage generator, comprising: a first PMOS transistor having a source coupled to a power voltage and commonly coupled gate and drain; a second PMOS transistor having a source coupled to the power voltage and a gate coupled to the gate of the first PMOS transistor; a first NMOS transistor having a gate and a drain coupled to the drain of the second PMOS transistor and a source coupled to a ground voltage; and a second NMOS transistor having a drain coupled to the drain of the first PMOS transistor, a source coupled to the ground voltage and a gate coupled to the gate of the first NMOS transistor, wherein an output node is formed on a contact path between the drain of the first NMOS transistor and the drain of the second PMOS transistor and each of the MOS transistors has the adjusted number of source contacts to compensate for variation of a saturation current flowing through its source and drains, the number of the source contacts is adjusted to increase source contact resistance, and the number of the source contacts is fewer than the number of drain contacts.