Patent ID: 7439591

Claim:
An integrated circuit, comprising a patterned gate layer comprising; a diode region in which a gate layer diode is formed, the gate layer diode comprising: a first portion of the gate layer containing a P-type dopant to form a first doped portion of the diode and a second portion of the gate layer adjacent to the first portion containing an N-type dopant to form a second doped portion of the diode, wherein the first doped portion and the second doped portion define first and second terminals of the diode; and a first electrically conductive contact disposed on the first doped portion of the diode and a second electrically conductive contact disposed on the second doped portion of the diode, wherein the first electrically conductive contact and the second electrically conductive contact are configured to apply a voltage serially across the first and second terminals of the gate layer diode; and a CMOS region separate from the diode region in which a CMOS device is formed, the CMOS device comprising a PMOS region in which a PMOS transistor is formed and an NMOS region in which an NMOS transistor is formed, wherein a third doped portion of the gate layer forms a transistor gate of the PMOS transistor and a fourth doped portion of the gate layer forms a transistor gate of the NMOS transistor, and wherein a spacer material is formed along sidewall portions of the gate layer diode and the third and fourth doped portions.