Patent ID: 8274313

Claim:
A wake-up circuit, comprising: a control signal generation circuit, comprising, a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency of the digital signal; a first comparison circuit and a second comparison circuit both coupled to an output end of the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal based on the comparison; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal based on the comparison; and an indication generation circuit configured to use the first control signal and the second control signal to generate a wake-up indication when the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies; wherein, the first comparison circuit comprises a first p-type MOSFET, a first capacitor and a first load, wherein a gate of the first p-type MOSFET is connected to the output end of the pulse generator, a drain of the first p-type MOSFET is connected to a negative terminal of the first capacitor to form a first common terminal, a source of the first p-type MOSFET is connected to a positive terminal of the first capacitor to form a second common terminal, the first common terminal is connected to one end of the first load and the second common terminal is connected to a positive voltage power source, the other end of the first load is grounded; the second comparison circuit comprises a second p-type MOSFET, a second capacitor and a second load, wherein a gate of the second p-type MOSFET is connected to an output end of the pulse generator, a drain of the second p-type MOSFET is connected to a negative terminal of the second capacitor to form a third common terminal, a source of the second p-type MOSFET is connected to a positive terminal of the second capacitor to form a fourth common terminal, the third common terminal is connected to one end of the second load and the fourth common terminal is connected to the positive voltage power source, the other end of the second load is grounded.