Patent ID: 8143659

Claim:
An integrated circuit comprising: a substrate with a doped area, the doped area forming a first electrode of a capacitor; a plurality of trenches arranged in the doped area of the substrate, at least one of the trenches forming a second electrode of the capacitor; at least one dielectric layer arranged between each of the at least one of the trenches and the doped area for electrically insulating the trenches from the doped area; and at least one substrate contact structure for electrically connecting the doped area, wherein the doped area comprises first open areas arranged between neighboring trenches of the plurality of trenches and at least one second open area arranged between neighboring trenches, wherein the at least one second open area is arranged below the at least one substrate contact structure, wherein a shortest first distance between the neighboring trenches separated by the first open areas is shorter than a shortest second distance between the neighboring trenches separated by the at least one second open area, wherein no other trench is arranged in the substrate between the neighboring trenches separated by the first open areas, and wherein no other trench is arranged in the substrate between the neighboring trenches separated by the at least one second open area.