Patent ID: 6983011

Claim:
A filter circuit, comprising: a plurality of unit circuits including a first stage unit circuit, at least one second stage unit circuit, and a final stage unit circuit mutually connected in series, each of said first stage unit circuit, said at least one second stage unit circuit, and said final stage unit circuit are consecutively arranged, each of said unit circuits comprising a computing means; said computing means in each of said first stage unit circuit and said at least one second stage unit circuit successively transmitting to a respective unit circuit of an immediately following stage a computing result of a) an analog input signal sampled at a same sampling timing and b) a coefficient predetermined for each of said computing means, said computing result of said computing means of each of said first stage unit circuit and said at least one second stage unit circuit being computed by adding a value of a residual, respectively input to each of the first stage unit circuit and said at least one second stage unit circuit from a respective unit circuit of a previous stage, and an analog computing result based on said analog input signal and a coefficient for said computing means, to obtain an added value, low-bit quantizing said added value to obtain a quantization result, subtracting a D/A converted value of the quantization result from the added value to obtain a residual value, and successively transmitting said quantization result as said computing result and said residual value to a following circuit, said computing means of each said first stage unit circuit and said at least one second stage unit circuit mutually adding said computing result and a computing result of a unit circuit of an immediately preceding stage so as to compute in said final stage unit circuit a cumulative value of computing results of all the coefficients and time-series analog sampling signals whose number corresponds to that of the coefficients, and the cumulative value is outputted as digital data, wherein said previous stage residual and computing result values for said first stage unit circuit are default values.