Patent ID: 8912996

Claim:
A scan driver, comprising: a plurality of scan driving blocks arranged sequentially, each of the plurality of scan driving blocks including: a first node configured to receive a signal input into a driving signal input terminal in accordance with a clock signal input into a second clock signal input terminal; a second node configured to receive a clock signal input into a first clock signal input terminal; a first transistor including a gate electrode connected to the second node, a first electrode configured to receive an output control signal, and a second electrode connected to an output terminal; a second transistor including a gate electrode connected to the first node, a first electrode connected to a third clock signal input terminal, and a second electrode connected to the output terminal; and a third transistor including a gate electrode connected to the third clock signal input terminal, a first electrode connected to the first node, and a second electrode connected the output terminal, wherein the output control signal varies between at least two voltage levels.