Patent ID: 8237425

Claim:
A voltage regulator comprising: a first operational amplifier; a first native NMOS transistor having a first source, a first drain and a first gate, the gate being connected to an output of the first operational amplifier, an unregulated supply voltage being applied to the first drain and a first regulated voltage being provided at the first source, a first temperature dependent circuit connected to the source and having an output connected to an inverting input of the first operational amplifier; a second temperature dependent circuit connected to the source and having an output connected to a non-inverting input of the first operational amplifier; a second operational amplifier having a non-inverting input connected to the first source; a second native NMOS transistor having a second source, a second drain and a second gate, the second gate being connected to an output of the second operational amplifier, the voltage to be regulated being applied to the second drain and a second regulated voltage being provided at the second source, a feedback path between the second source and an inverting input of the second operational amplifier, a third operational amplifier having a non-inverting input connected to the second source; a third native NMOS transistor having a third source, a third drain and a third gate, the third gate being connected to an output of the third operational amplifier, the voltage to be regulated being applied to the third drain and a third regulated voltage being provided at the third source; and a feedback path between the third source and an inverting input of the third operational amplifier.