Patent ID: 8001285

Claim:
A system, comprising: first memory for storing data; a processing core for executing software instructions on the data that is received from the first memory; a peripheral device configured to communicate with the processing core through a peripheral control module; and the peripheral control module includes: second memory; an interface module configured to transmit command sequences to the peripheral device; and a comparator for governing data transfer transactions, without interrupting the processing core, based on a comparison of expected responses of the peripheral device to received responses from the peripheral device, wherein the received responses are generated based on the command sequences, wherein the expected responses are predetermined based on the command sequences, wherein the command sequences are associated with data packets to be exchanged between the first memory and the peripheral device, wherein each of the expected responses and each of the received responses is associated with a respective command of the command sequences, and wherein the processing core is in a sleep mode while the command sequences are transmitted to the peripheral device.