Patent ID: 7838395

Claim:
A method of making a wafer level chip scale package (WLCSP) semiconductor device, comprising: providing a semiconductor die having active circuits formed on an active surface of the semiconductor die; forming a plurality of contact pads on the active surface of the semiconductor die, the contact pads being coupled to the active circuits; forming a die extension region around a periphery of the semiconductor die; forming a plurality of conductive through hole vias (THV) in the die extension region around the periphery of the semiconductor die; forming a wafer level conductive plane over a center area on the active surface of the semiconductor die, the wafer level conductive plane being coupled to a first one of the plurality of contact pads for providing a first power supply potential to the active circuits, the wafer level conductive plane being electrically connected to a first one of the plurality of conductive THVs; forming a conductive ring partially around a perimeter of the wafer level conduction plane, the conductive ring being coupled to a second one of the plurality of contact pads for providing a second power supply potential to the active circuits, the conductive ring being electrically connected to a second one of the plurality of conductive THVs; and singulating the WLCSP semiconductor device through the die extension region to provide a direct path for the wafer level conductive plane and conductive ring through the conductive THVs in the die extension region around the periphery of the semiconductor die in the WLCSP semiconductor device.