Patent ID: 7821290

Claim:
A differential driver circuit having at least one driver stage comprising: an input coupled by a pre-driver to: a gate of a first PMOS transistor in parallel with a first NMOS transistor, where a source of the first PMOS transistor is coupled to a drain of the first NMOS transistor, and a drain of the first PMOS transistor is coupled to a source of the first NMOS transistor; a gate of a second NMOS transistor having a drain coupled to the drain of the first PMOS transistor and a source coupled to a ground; and a gate of a third NMOS transistor; a first differential output coupled to the drain of the second NMOS transistor; the input coupled by an inverting pre-driver to: a gate of a second PMOS transistor in parallel with the third NMOS transistor, where a source of the second PMOS transistor is coupled to a drain of the third NMOS transistor, and a drain of the second PMOS transistor is coupled to a source of the third NMOS transistor; a gate of the first NMOS transistor; and a gate of a fourth NMOS transistor having a drain coupled to the drain of the second PMOS transistor and a source coupled to the ground; and a second differential output coupled to the drain of the fourth NMOS transistor; wherein the source of the first PMOS transistor is coupled to a voltage source; wherein the source of the second PMOS transistor is coupled to the voltage source; and wherein the voltage source is configured to provide a voltage signal indicative of a predetermined peak to peak output voltage.