Patent ID: 7225439

Claim:
A computer comprising a processor for compiling source code that specifies operation of a mutator, which includes a loop including at least one reference-modifying instruction, into object code for execution by a computer system, which includes a memory of which at least a portion is logically partitioned into one or more cards, wherein the processor executes a set of instructions to perform: (A) determining whether execution of the loop included in the mutator results in modifications, by the at least one reference-modifying instruction included in the loop, of at least one reference within each card spanned by an array of references, wherein the at least one reference is stored in the array of references and the computer system includes a garbage collector that relies on the mutator's execution of write-barrier code to keep track of at least some reference modifications of the array of references; (B) deferring, in response to determining that execution of the loop results in the modifications of the at least one reference within each card spanned by the array of references, emission of write-barrier code corresponding to the modifications of the at least one reference within each card spanned by the array of references; (C) emitting write-barrier code that executes subsequent to the execution of the object code implementing the loop, wherein write-barrier code executes a write barrier corresponding to each card spanned by the array of references; and (D) providing, in response to determining that execution of the loop results in the modifications of the at least one reference within each card spanned by the array of references, a data structure containing an indication of a location that stores the memory address of the array of references, the data structure being accessible to the garbage collector.