Patent ID: 7630224

Claim:
A semiconductor integrated circuit device with a multilayer wiring structure including a first group of layers of wiring and a second group of layers of wiring provided over said first group, said semiconductor integrated circuit device comprising: a memory macro which comprises: an array of memory cells arranged in a matrix, a plurality of pairs of digit lines pairs coupled with said memory cells and extending in a column direction, and a column peripheral circuit having a sense amplifier circuit coupled with said digit line pairs, wherein said memory macro comprises said first group of layers of wiring; and one or more passage wirings arranged to extend in a row direction not parallel to said column direction, wherein said one or more passage wirings are provided in the lowermost one of the layers of said second group closest to said first group, and wherein the lowermost layer of said second group of layers is arranged to avoid any wiring section extending along said row direction over said column peripheral circuit.