Patent ID: 8138572

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a bit line and a bit line pad in a cell region and a peripheral region, respectively, over a substrate; forming a first metal layer on the bit line and the bit line pad; forming an interlayer insulating film over the first metal layer and the substrate; etching the interlayer insulating film in the cell region to form a storage node contact hole; filling the storage node contact hole with conductive material to form a storage node contact plug in the cell region; forming a second metal layer over the storage node contact plug; etching the interlayer insulating film in the peripheral region to form a contact hole exposing the first metal layer over the bit line pad; growing a nano tube using the second metal layer in the cell region and the exposed first metal layer in the peripheral region as a catalyst to form a lower electrode and a first contact, respectively; and forming a second contact connected to the first contact in the peripheral region to form a via contact.