Patent ID: 7110318

Claim:
A semiconductor memory device, comprising: a memory cell array in which a plurality of memory cells are arranged in columns and rows, each of said memory cells having a first access transistor receiving and transmitting data in correspondence with a first port having a first input/output group and a second access transistor receiving and transmitting data in correspondence with a second port having a second input/output group; a plurality of first word lines connected in respective rows to said first access transistors of said plurality of memory cells arranged in the row direction of said memory cell array; a plurality of second word lines connected in respective rows to said second access transistors of said plurality of memory cells arranged in the row direction of said memory cell array; a first port word driver arranged on one side of said memory cell array to drive said first word line and a second port word driver arranged on other side of said memory cell array to drive said second word line, said memory cell array being interposed between said first and second port word drivers in the row direction, wherein said first word line and said second word line are arranged alternately in the column direction of said memory cell array.