Patent ID: 7260793

Claim:
An apparatus performing compaction of a set of test stimuli for a digital circuit, comprising: a simulation device performing a simulation on the digital circuit with the set of test stimuli to trace faults which the set of test stimuli cover; a selection device selecting essential test stimuli from among subsets of the set of test stimuli after mapping between the test stimuli and the faults has been established by the simulation, an essential test stimulus being a test stimulus that detects at least one fault, which is detectable by no other test stimulus in one of the subsets of test stimuli; an elimination device eliminating redundant test stimuli from among subsets of test stimuli after selection of essential test stimuli from each subset, a redundant test stimulus being a test stimulus that detects a fault, which is detectable by another test stimulus in each subset after the selection of the essential test stimuli; and an output device outputting a compacted set comprising the selected essential test stimuli.