Patent ID: 8438517

Claim:
A computer-implemented method for identifying and managing the relationships between clock domains in an integrated circuit design, comprising: receiving at a computer system as inputs a description of the design, and definitions of clock waveforms and timing constraints used in the design; and in the computer system, automatically identifying pairs of clocks from the timing constraints and, for each identified pair of clocks: in the computer system, categorizing each clock in the pair as a source clock or a generated clock and, if the clock is a generated clock, its parent clock; in the computer system, identifying any points in the design at which the clocks in the pair of clocks are applied simultaneously; in the computer system, identifying any points in the design at which the clocks in the pair of clocks logically merge; in the computer system, if the clocks in the pair of clocks are both source clocks, determining the default relationship between the clocks; in the computer system, if either clock in the pair of clocks is a generated clock, determining the relationship between the generated clock and the source clock from which the generated clock is derived; in the computer system, if either clock in the pair of clocks is a generated clock, determining whether the generated clock inherits any relationship from its parent clock; and in the computer system, assigning the clock pair to one of a plurality of behavioral categories based upon one of the determined relationships.