Patent ID: 8624379

Claim:
A semiconductor device, comprising: a first chip mounting portion having electrical conductivity; a first semiconductor chip having a first main surface, and a first back surface opposite to the first main surface and bonded to the first chip mounting portion; a second chip mounting portion; a second semiconductor chip having a second main surface, and a second back surface opposite to the second main surface and bonded to the second chip mounting portion; a first lead portion; and a sealing portion sealing therein the first and second semiconductor chips, at least a part of each of the first and second chip mounting portions, and at least a part of the first lead portion, wherein the first semiconductor chip is formed with a first MOSFET and a second MOSFET which have respective drains thereof electrically coupled to each other, and respective gates thereof electrically coupled to each other, wherein the first MOSFET is formed in a first region of the first main surface of the first semiconductor chip, while the second MOSFET is an element for detecting a current flowing in the first MOSFET and is formed in a second region of the first main surface of the first semiconductor chip, wherein a first gate pad electrically coupled to the gates of the first and second MOSFETs, a first source pad electrically coupled to a source of the first MOSFET, and a second source pad electrically coupled to a source of the second MOSFET are formed over the first main surface of the first semiconductor chip, wherein a drain electrode electrically coupled to the drains of the first and second MOSFETs is formed over the first back surface of the first semiconductor chip, wherein the first source pad is electrically coupled to the first lead portion via a conductor plate, and wherein, in the first main surface of the first semiconductor chip, the second region has an area smaller than that of the first region, the conductor plate does not overlap the second region in a plan view, and the conductor plate is bonded to the first source pad of the first semiconductor chip so as to surround three sides of the second region in the plan view.