Patent ID: 7558948

Claim:
A method for reducing overhead on a loop of a plurality of instructions, the loop being performed a particular number of times, the method comprising: providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time; providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic; and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions by performing the operation A n XOR i n XOR (C n AND M n ), where A n is a n th bit of the current instruction address, i n is one for a least significant bit of the address of the current instuction and zero otherwise, C n is a carry bit for a n th digit of the carry mask and M n is a n th digit of the carry mask, the resultant of the addition logic corresponding to a next instruction of the plurality of instructions if the current instruction is not a last instruction, the resultant of the addition logic corresponding to an address of a first instruction if the current instruction is not a last instruction, the resultant of the addition logic corresponding to an address of a first instruction if the current instruction address is the last instruction and the loop being performed less than the particular number of times.