Patent ID: 8849885

Claim:
A hardware integer saturation detector, configured to detect whether packing a 32-bit integer value causes saturation and whether packing each of first and second 16-bit integer values causes saturation, wherein the first 16-bit integer value is the upper 16 bits of the 32-bit integer value and the second 16-bit integer value is the lower 16 bits of the 32-bit integer value, the hardware integer saturation module comprising: hardware signal logic, configured to generate: a 3-bit signal A that indicates whether a most significant bit of the 32-bit integer value and a most significant bit of each of the first and second 16-bit integer values is a 0 or a 1; a 3-bit signal B that indicates whether a most significant bit of a least significant word of the 32-bit integer value and whether a most significant bit of a least significant byte of each of the first and second 16-bit integer values is a 0 or a 1; a 3-bit signal C that indicates whether a most significant word of the 32-bit integer value is equal to 0xFFFF and whether a most significant byte of each of the first and second 16-bit integer values is equal to 0xFF; and a 3-bit signal D that indicates whether a most significant word of the 32-bit integer value is equal to 0x0000 and whether a most significant byte of each of the first and second 16-bit integer values is equal to 0x00; and hardware saturation logic, configured to: NAND the bits of signal B with the bits of signal C to form a signal E; NAND the bits of signal D with the inverted bits of signal B to form a signal F; MUX between the bits of signal E and signal F using the bits of signal A as control signals to form a signal J; MUX between signal J and an inverted signal D to form a 3-bit saturation signal, using a signal that indicates whether the packing operation is signed or unsigned as a control signal.