Patent ID: 7975200

Claim:
A method for designing an error correction code (ECC) decoding architecture using synthesis-time design parameters, the method comprising: receiving a plurality of predetermined architecture parameters; selecting a first plurality of semi-soft design constraints based on the plurality of predetermined architecture parameters; selecting a first parallel implementation of a plurality of processing modules employed within the ECC decoding architecture; generating a first version of the ECC decoding architecture based on the first plurality of semi-soft design constraints and the first parallel implementation of a plurality of processing modules; determining whether the first version of the ECC decoding architecture meets a time constraint; if the first version of the ECC decoding architecture does not meet the time constraint, then: selecting a second plurality of semi-soft design constraints based on the plurality of predetermined architecture parameters; selecting a second parallel implementation of the plurality of processing modules employed within the ECC decoding architecture; generating a second version of the ECC decoding architecture based on the second plurality of semi-soft design constraints and the second parallel implementation of the plurality of processing modules; and employing the second version of the ECC decoding architecture to design at least a portion of a communication device, that includes a hard disk drive (HDD), that is operable to decode a coded signal; and if the first version of the ECC decoding architecture meets the time constraint, then employing the first version of the ECC decoding architecture to design at least a portion of the communication device that is operable to decode the coded signal.