Patent ID: 8531222

Claim:
A method of operating a device, the method comprising: passing a clock signal provided by a phase locked loop (PLL) circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit during a low power operation mode of the device; detecting a lock between the first input signal and a reference signal during the low power operation mode, wherein the lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device; providing a first lock detection signal to indicate the lock between the first input signal and the reference signal; providing power to operate the PLL circuit during the normal operation mode; passing the clock signal through an external feedback path to provide a second input signal to the PLL circuit and through a signal path of the device to an output node of the device during the normal operation mode; switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal; providing a second lock detection signal to indicate the lock between the second input signal and the reference signal; receiving an operation mode signal to switch the device from the normal operation mode to the low power operation mode; disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode; and continuing providing power to the PLL circuit until after the signal path is disabled.