Patent ID: 7483304

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix, the memory cells arranged in each column being coupled in series to configure a NAND unit, the NAND unit being coupled to a bit line and a source line, and the memory cells arranged in each row being coupled to a word line; a control circuit which controls the potentials of the word line, the bit line, the source line and a well containing the memory cells; a first voltage generating circuit configured to generate a first voltage; and a second voltage generating circuit configured to generate a second voltage, wherein, when reading data from a memory cell, the control circuit supplies the first voltage generated by the first voltage generating circuit to the source line, supplies the second voltage generated by the second voltage generating circuit to the bit line, supplies a first predetermined voltage for reading data of memory cells to a selected word line, and supplies a second predetermined voltage for setting memory cells to off state to an unselected word line.