Patent ID: 7372737

Claim:
A nonvolatile memory comprising: a memory transistor, a reference memory transistor, a first circuit for reading the memory transistor, and a second circuit for writing each of the memory transistor and the reference memory transistor, wherein: each of the memory transistor and the reference memory transistor includes a semiconductor layer, a first gate over the semiconductor layer, and a second gale over the first gate, the first circuit includes a sense amplifier circuit, a data latch, a first resistor a second resistor, and a buffer, a first input terminal of the sense amplifier circuit is connected to one of a source and a drain of the memory transistor and a first terminal of the first resistor, a second input terminal of the sense amplifier circuit is connected to one of a source and a drain of the reference memory transistor and a first terminal of the second resistor the first input terminal of the sense amplifier circuit and the second input terminal of the sense amplifier circuit are commonly connected to a reference potential, an output terminal of the sense amplifier circuit is connected to the data latch, the other of the source and the drain of the memory transistor and the other of the source and the drain of the reference memory transistor are kept at a first potential, a second terminal of the first resistor and a second terminal of the second resistor are kept at a second potential, and the data latch is connected to the buffer.