Patent ID: 7260104

Claim:
A buffer control apparatus in a buffered switch for controlling transmission of data, comprising: a buffer memory for storing the data; a buffer write module for writing the data into the buffer memory; a buffer read module for reading the data from the buffer memory; a deferred header queue containing entries having destination and buffer address information for data to be deferred, with entries for data addressed to multiple destinations ports being intermingled within the deferred header queue; a header select device for controlling the buffer read module and having an initial and a deferred state, the initial state adding entries to the deferred queue so as to temporarily defer transmission to a destination port unavailable to receive the data, and the deferred state processing all entries in the deferred header queue in the order in which the entries were written in the deferred header queue, the deferred state submitting the buffer address information for an entry to the buffer read module when the destination port is available to receive data or the deferred state keeping the buffer address information on the deferred header queue when the destination port is unavailable to receive data.