Patent ID: 7272676

Claim:
A data transfer control device for data transfer through a bus, the data transfer control device comprising: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the allocated packet buffer, each of the pipe regions storing data which is transferred between each of the pipe regions and corresponding one of endpoints; and a transfer controller which controls data transfer between the pipe region and a corresponding endpoint, wherein: the data transfer control device performs pause processing in which data transfer between the pipe region and a corresponding endpoint is paused; the data transfer control device performs reconstruction processing of the pipe regions after the completion of the pause processing, the reconstruction processing including at least one of delete processing of the allocated pipe region, addition processing of a new pipe region, and size-change processing of the allocated pipe region; and the data transfer control device resumes the paused data transfer after the reconstruction processing of the pipe regions, wherein: when a first pipe region allocated in the packet buffer corresponding to a first endpoint before the reconstruction processing is allocated again after the reconstruction processing, the data transfer control device performs copy processing in which data is read from the first pipe region before the reconstruction processing and the read data is written into the first pipe region after the reconstruction processing, wherein: when a start address of the first pipe region after the reconstruction processing is greater than a start address of the first pipe region before the reconstruction processing, data is read from the first pipe region before the reconstruction processing while decrementing a source address which is a read address of the first pipe region before the reconstruction processing, and the read data is written into the first pipe region after the reconstruction processing while decrementing a destination address which is a write address of the first pipe region after the reconstruction processing; and when the start address of the first pipe region after the reconstruction processing is smaller than the start address of the first pipe region before the reconstruction processing, data is read from the first pipe region before the reconstruction processing while incrementing the source address, and the read data is written into the first pipe region after the reconstruction processing while incrementing the destination address.