Patent ID: 8461640

Claim:
A non-volatile memory cell comprising: a substrate layer; a fin shaped semiconductor member of a first conductivity type on said substrate layer having a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region; said fin shaped member having a top surface and two side surfaces between the first region and the second region; a word line adjacent to the first region and capacitively coupled to a first portion of the channel region; a floating gate adjacent to the word line and capacitively coupled to a second portion of the channel region; a coupling gate capacitively coupled to the floating gate; an erase gate insulated from the second region and adjacent to the floating gate and coupling gate; and wherein the floating gate has two sections with each section positioned adjacent to one of the side surfaces of the fin shaped member and is capacitively coupled thereto.