Patent ID: 7292490

Claim:
A system for refreshing a DRAM array, comprising: refresh control circuitry that selectively generates requests to perform refresh operations; a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to a request to perform a refresh operation, the refresh address corresponding to a word line of the DRAM array to be refreshed; and address control and switching circuitry coupled to the refresh control circuitry, the address control and switching circuitry being adapted to selectively transmit read/write addresses and refresh addresses to the DRAM array to facilitate refreshing of the DRAM array without inhibiting read and write operations; wherein the refresh control circuitry comprises: a refresh timer oscillator; and a pulse generator that is coupled to the refresh timer oscillator and that generates a refresh pulse, which starts a new refresh cycle during which a refresh is capable of being performed; wherein the address control and switching circuitry suspends the refresh operations in favor of read and write operations; wherein the width of the refresh pulse is longer than a time period required to complete a read or write operation; and wherein the width of the refresh pulse is at least as wide as the sum of the time required to complete the read or write operation plus twice the time required to perform a word line refresh.