Patent ID: 7936327

Claim:
A driving circuit comprising: a plurality of parallel gate lines; a plurality of parallel data lines orthogonal to the gate lines; a plurality of pixel electrodes; a plurality of thin film transistors, each of the thin film transistors positioned near a crossing of a corresponding gate line and a corresponding data line, each of the thin film transistors comprising a gate electrode coupled to the corresponding gate line, a source electrode coupled to the corresponding data line, and a drain electrode coupled to a corresponding one of the pixel electrodes; a plurality of gate driving circuits for driving the gate lines; a plurality of data driving circuits for driving the data lines; and a compensative unit having a first input terminal, a second input terminal, and a plurality of output terminals coupled to the data driving circuits, respectively; wherein the first and second input terminals are coupled to two nodes of one of the gate lines, the two nodes are coupled to two gate electrodes of two of the thin film transistors respectively connected to a selected two of the data driving circuits, and the compensative unit outputs a plurality of compensative voltages for compensating data voltage signals outputted by the data driving circuits, according to delays of two scanning signals received from the first and second input terminals, respectively, wherein the two nodes are a node “ 1 ” and a node “ 2 ”, and the compensative voltage is expressed by the following equation: V pi =( i −1) V s , ( i =1, 2, 3 . . . j ), where V pi represents a compensative voltage transmitted to an ith data driving circuit, j represents a number of data driving circuits, V s represents a unit compensative voltage, which is expressed by the equation: V s ″ = K ″ ⁡ ( ∫ t ⁢ ⁢ 0 ″ t ⁢ ⁢ 2 ″ ⁢ V 2 ⁢ ⅆ t - ∫ t ⁢ ⁢ 0 ″ t ⁢ ⁢ 1 ″ ⁢ V 1 ⁢ ⁢ ⅆ t ) K 2 - K 1 , ⁢ ( K 1 = 1 , 2 , 3 ⁢ ⁢ … ⁢ ⁢ j - 1 , K 2 = 2 , 3 ⁢ ⁢ … ⁢ ⁢ j , K 2 > K 1 ) , where t 0 represents a time of reversing of data voltage signals transmitted to the two thin film transistors with gate electrodes coupled to the nodes “ 1 ” and “ 2 ” respectively, t 1 represents a time of shutting off of the thin film transistor with the gate electrode coupled to the node “ 1 ”, t 2 represents a time of shutting off of the thin film transistor with the gate electrode coupled to the node “ 2 ”, V 1 represents an instant voltage of the node “ 1 ” during a time period from t 0 to t 1 , V 2 represents an instant voltage of the node “ 2 ” during a time period from t 0 to t 2 , K represents an adjusting constant, K 1 represents a number of data driving circuits corresponding to the node “ 1 ”, and K 2 represents a number of data driving circuit corresponding to the node “ 2 ”.