Patent ID: 6925030

Claim:
A nonvolatile ferroelectric memory device comprising: first and second cell array blocks which independently operate; an address path changing adjustor for decoding a plurality of row address predecoder input signals, outputting a plurality of row address predecoder output signals which are respectively corresponding to a plurality of split word lines, wherein the address path changing adjustor changes an input order of the row address predecoder input signals in response to a control signal to determine whether the first or second cell array block operates and produces order-changed row address predecoder output signals; a word line/plate line control signal path changing adjustor for receiving the row address predecoder output signals from the address path changing adjustor, a word line control signal and a plate line control signal and outputting a plurality of split word lines driving signals, wherein the word line/plate line control signal path changing adjustor changes operational features of the split word lines driving signals in response to the control signal so that each of split word lines driving signals drives word lines or a plate line in the first and second cell array blocks; a level shifter boosting the plurality of the split word lines driving signals; and a plurality of split word lines driving part for driving the split word lines in response to output signals from the level shifter.