Patent ID: 7535262

Claim:
A circuit arrangement comprising: an input circuit referenced to a first ground and providing complementary input signals; an output circuit for operating a power semiconductor device and referenced to a second ground; and at least one capacitor, said capacitor including an input plate electrically connected to said input circuit and receiving one of said complementary input signals and an output plate electrically connected to said output circuit; further comprising another capacitor, said another capacitor comprising an input plate electrically connected to said input circuit and receiving the other of said complementary input signals and an output plate electrically connected to said output circuit; wherein said output circuit includes a signal biasing portion, an edge triggered signal detection portion, and a signal reconstruction portion; wherein said edge triggered signal detection portion detects a beginning and an end of said input signal based on reference signals generated by said signal biasing portion and generates an edge identifier signal when it detects said beginning and an edge identifier signal when it detects said end of said input signal; wherein said signal reconstruction portion generates an output signal based on said edge identifier signals; and wherein said signal reconstruction portion determines whether a change of voltage of said output plates relates to common mode noise on the input plates of said two capacitors or whether said change of voltage of said output plates relates to said complementary input signals on the input plates and wherein said signal reconstruction portion determines that said change of voltage on said output plates is due to complementary input signals on said input plates when said voltage on said output plate of said one capacitor is higher than a first reference value while said voltage on said output plate at said another capacitor is below a second reference value, and said voltage on said output plate of said one capacitor is less than said second reference value and voltage on said output plate of said another capacitor is higher than said first reference value.