Patent ID: 8519506

Claim:
A galvanic isolation integrated circuit system comprising: a crystalline silicon substrate having an upper surface; a layer of dielectric material formed on the upper surface of the crystalline silicon substrate; a layer of diamond material formed on an upper surface of the layer of dielectric material, wherein the layer of diamond material is patterned to provide first, second and third portions that are spaced apart from one another; a first integrated circuit structure formed on an upper surface of the layer of diamond material; a second integrated circuit structure formed on the upper surface of the layer of diamond material and spaced apart from the first integrated circuit structure; and a transformer formed on the upper surface of the layer of diamond material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure; the first integrated circuit structure being formed on an upper surface of the first portion of diamond material, the second integrated circuit structure being formed on an upper surface of the second portion of diamond material, and at least a portion of the transformer being formed on an upper surface of the third portion of diamond material; wherein each of the first and second integrated circuit structures comprises an integrated circuit die mounted directly on the respective portion of the upper surface of layer of diamond material; a layer of epoxy formed in the gaps between the integrated circuit dies, the transformer and the spaces between the spaced apart portions of diamond material.