Patent ID: 7039881

Claim:
A process for modifying the design of an old integrated circuit that is suitable for manufacture at a first geometric size by a first manufacturing method to produce a new circuit that is suitable for manufacture at a second geometric size by a second manufacturing method while maintaining the functionality of the old circuit, wherein the first and second manufacturing processes are different and the geometry sizes are-different, said process including the steps of: a) comparing old gates stored in an electronic data model of the old integrated circuit against a target supplier library for supplying new gates suitable for the second manufacturing process, said supplier library being different from the electronic data model of the old integrated circuit and the new gates stored in the supplier library having been generated in accordance with the design rules of the second manufacturing process, said electronic data model including logical function, timing and geometric size information of the old gates and the supplier library containing logical function, timing and geometric size information for the new gates; b) analyzing the logical functions of the old and new gates using Boolean truth tables to determine a set of logical equivalent new gates for at least some of the old gates in the old integrated circuit; c) for each old gate having at least one logical equivalent new gate in the supplier library, analyzing the timings of the old gate and each logical equivalent new gate in the set using signal propagation delay information by comparing the signal propagation delay across each individual gate from a gate's input to a gate's output; d) for each old gate having at least one logical equivalent new gate in the supplier library, selecting a single logical equivalent new gate from the set of logical equivalents to replace the old gate on the basis of the timing analysis; e) scaling the old integrated circuit to the second geometric size; f) producing a data model of the new circuit by substituting at least some of the old gates in the old circuit with their logical equivalent new gates selected from the supplier library while maintaining the electrical connections between the gates; and g) subsequently adjusting the routing geometry of the electrical connections between the gates.