Patent ID: 7446035

Claim:
A method for fabricating a chip, comprising: providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said first internal circuit, and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming a third interconnecting structure over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said forming said third interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.