Patent ID: 8116149

Claim:
A memory circuit comprising: a plurality of memory banks arranged in an array, each memory bank comprising memory cells in rows and columns, and each having word lines configured to enable access transistors within the memory cells to couple data to and from a pair of complementary local bit lines, each memory bank further comprising a local sense amplifier for sensing small swing voltages on the local bit lines and for sensing small swing voltages on a pair of complementary global bit lines; a plurality of the global bit lines arranged in pairs of complementary bit line signals, the global bit lines extending across the memory array and coupled to the local sense amplifier in each of the memory banks; a write small signal driver circuit coupled to full swing input/output data lines and operable to output complementary small swing signals on the plurality of global bit lines; and a global sense amplifier coupled to the plurality of global bit lines and configured to sense small swing differential signals on the global bit lines, and having full swing output signals.