Patent ID: 7411419

Claim:
An integrated circuit comprising: a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, wherein the reference circuit is further adapted to provide default voltage levels for the second plurality of reference signals if a first control signal is asserted, wherein the default voltage levels are not based on the first reference signal; an output driver; and an input/output circuit, coupled to the reference circuit and the output driver, adapted to receive the second plurality of reference signals to control the output driver to provide an output signal, wherein the output driver is operated with the default voltage levels if the first control signal is asserted, wherein the reference circuit is further adapted to provide a third plurality of reference signals based on the first reference signal, wherein the third plurality of reference signals provides at least one of a slew rate control signal or differential input buffer reference signals, and wherein the first control signal prevents the first reference signal from being used to generate the third plurality of reference signals if the first control signal is asserted.