Patent ID: 7952317

Claim:
A motor driving inverter circuit module including a first output terminal, a second output terminal, and a third output terminal for respectively providing a first-phase motor driving output signal, a second-phase motor driving output signal, and a third-phase motor driving output signal, the inverter circuit module comprising: a first high voltage driver configured to generate a first-phase upper arm driving signal and a first-phase lower arm driving signal in response to input signals for driving a first-phase upper arm and a first-phase lower arm; a second high voltage driver configured to generate a second-phase upper arm driving signal and a second-phase lower arm driving signal in response to input signals for driving a second-phase upper arm and a second-phase lower arm; a third high voltage driver configured to generate a third-phase upper arm driving signal and a third-phase lower arm driving signal in response to input signals for driving a third-phase upper arm and a third-phase lower arm; a pair of a first upper arm transistor and a first lower arm transistor configured to generate the first-phase motor driving output signal in response to the first-phase upper arm and lower arm driving signals generated by the first high voltage driver; a pair of a second upper arm transistor and a second lower arm transistor configured to generate the second-phase motor driving output signal in response to the second-phase upper arm and lower arm driving signals generated by the second high voltage driver; and a pair of a third upper arm transistor and a third lower arm transistor configured to generate the third-phase motor driving output signal in response to the third-phase upper arm and lower arm driving signals generated by the third high voltage driver; wherein the first-phase, second-phase, and third-phase upper arm transistors comprise a gate insulation film whose thickness is selected in proportion to a ratio C gs /C gd satisfying R g ( off ) C gs /C gd >constant x BV ds /V th(min) , wherein BV ds is a break-down voltage of the first-phase, second-phase, and third-phase upper arm transistors, V th(min) is a minimum value of threshold voltage distribution of the first-phase, second-phase, and third-phase upper arm transistors, R g(off) is a gate turn-off resistance of the first-phase, second-phase, and third-phase upper arm transistors, C gs is a parasitic capacitance between a gate and a source of the first-phase, second-phase, and third-phase upper arm transistors, C gd is a parasitic capacitance between a gate and a drain of the first-phase, second-phase, and third-phase upper arm transistors, and the constant assumes a value in the range of 0.7 to 0.9.