Patent ID: 7783810

Claim:
An information processing apparatus comprising: a first processor configured to communicate with a first interrupt register, said first processor configured to execute a first operating system; a second processor configured to communicate with a second interrupt register, said second processor configured to execute a second operating system; and an interface device configured to communicate with said first processor and said second processor, said interface device including: (a) a receiver; (b) a memory device which stores a table including a plurality of predetermined fields, each of the predetermined fields indicating a correspondence between identification data and one of an identification of said first interrupt register and an identification of said second interrupt register; and (c) a third processor configured to operate with the receiver and the memory device to: (i) receive data from a network, said received data including the identification data, the identification data including destination information for said received data, wherein the received data corresponds to one of the first operating system and the second operating system based on the destination information of the identification data; (ii) analyze said identification data; (iii) determine whether the analyzed identification data corresponds to the identification of the first interrupt register or the identification of the second interrupt register based on one of the predetermined fields of said table; (iv) if the analyzed identification data is associated with the identification of the first interrupt register: (A) cause interrupt processing to occur by writing the received data into said first interrupt register; and (B) if the first operating system is available, notify said first processor of said interrupt processing; and (v) if the analyzed identification data is associated with the identification of the second interrupt register: (A) cause interrupt processing to occur by writing the received data into said second interrupt register; and (B) if the second operating system is available, notify said second processor of said interrupt processing.