Patent ID: 7590904

Claim:
A method of self-detecting an error in a field programmable gate array (FPGA) having an FPGA core configured to implement a user-defined function, a configuration memory having a portion designated as a signature memory, and an electrically-erasable programmable read-only memory (EEPROM) device configured for storing a copy of the user-defined function, the method comprising: writing a key value into the signature memory from a self-detecting error module within the FPGA in response to a timer-based event, wherein the key value is a string of bits different from the user-defined function; initiating a configuration refresh operation in response to writing the key value, wherein the configuration refresh operation loads the user-defined function from the EEPROM device to the configuration memory and flushes the signature memory; determining a conclusion of the configuration refresh operation; reading an outcome value from the signature memory in response to a conclusion of the configuration refresh operation; comparing the outcome value to an expected value; and setting an error flag when the outcome value is not equal to the expected value.