Patent ID: 6922083

Claim:
A sampling receiver comprising: a slave latch circuit; and first and second master latch circuits coupled to said slave latch circuit, said first and second master latch circuits performing a voltage level conversion of input signals and supplying level converted master latch signals to said slave latch circuit, wherein said first master latch circuit comprises: a first differential input transistor pair comprising a first pair of first conductivity type channel field effect transistors each having a respective output terminal coupled to said slave latch circuit, and a first bistable circuit comprising first and second CMOS inverters each having a respective output terminal connected to said output terminal of a corresponding one of said first pair of first conductivity type channel field effect transistors of said first differential input transistor pair for outputting a respective one of said level-converted master latch signals, wherein said second master latch circuit comprises: a second differential input transistor pair comprising a second pair of second conductivity type, different form said first conductivity type, channel field effect transistors each having a respective output terminal coupled to said slave latch circuit; and a second bistable circuit comprising a pair of third and fourth CMOS inverters each having a respective output terminal connected to said output terminal of a corresponding one of said second pair of second conductivity type channel field effect transistors of said, second differential input transistor pair for outputting another respective one of said level-converted master latch signals. wherein said first and second differential input transistor pairs receive said input signals.