Patent ID: 8614925

Claim:
A semiconductor memory device comprising: a main area including a plurality of first memory blocks sharing a first write bit line and sharing a first read bit line, the first write bit line being separate from the first read bit line; and a redundancy area configured to replace one or more defective components of the first memory blocks, the redundancy area including a plurality of second memory blocks sharing a second write bit line and sharing a second read bit line, the second write bit line being separate from the second read bit line, wherein the first memory blocks include first local bit line selectors, the first local bit line selectors configured to selectively connect a first local bit line in a corresponding one of the plurality of first memory blocks to both of the corresponding first write bit line and the corresponding first read bit line, and wherein each of the first local bit line selectors is coupled to an end of the corresponding first local bit line, wherein the first memory blocks are arranged in a direction along at least one of the first read bit line and the first write bit line, wherein each of the first local bit line selectors includes a first gate configured to selectively connect the first local bit line to the first write bit line and a second gate configured to selectively connect the first local bit line to the first read bit line, the first and second gates each being connected to the first local bit line through a common first node such that no intervening connection to memory cells of the memory device exist between the first gate and the first node or the second gate and the first node.