Patent ID: 7529912

Claim:
A microprocessor apparatus, for specifying a floating point format to be employed during execution of an associated legacy floating point operation, the microprocessor apparatus comprising: translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: instruction entities according to an existing instruction set, wherein said instruction entities comprise a first opcode within said existing instruction set that specifies the associated legacy floating point operation to be executed by a microprocessor, an extended prefix, for prescribing one of a plurality of floating point control words, wherein said one of a plurality of floating point control words specifies the floating point format; and an extended prefix tag, for indicating that said extended instruction prescribes architecture extensions which include specification of the floating point format, and for indicating that said extended prefix follows, wherein said extended prefix tag is a second opcode within said existing instruction set that specifies a different legacy operation to be executed by said microprocessor; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for executing the associated legacy floating point operation according to the floating point format prescribed by said extended prefix.