Patent ID: 8709930

Claim:
A semiconductor process, comprising: forming a first gate and a second gate on a substrate, wherein the first gate comprises a first gate layer located on the substrate and a first cap layer located on the first gate layer, and the second gate comprises a second gate layer located on the substrate and a second cap layer located on the second gate layer; forming a hard mask layer to cover the first gate and the second gate, wherein the material of the hard mask layer and the materials of the first cap layer and the second cap layer are different; performing a lithography process for patterning the hard mask layer located on the second gate to form a first spacer beside the second gate and forming a recess in the substrate beside the first spacer; forming an epitaxial layer in the recess; performing an etching process to remove the hard mask layer remaining and the first spacer entirely; and forming a second spacer beside the first gate and the second gate respectively.