Patent ID: 6987687

Claim:
A semiconductor memory comprising: a memory cell having ferroelectric capacitor which is selectively connected to a first bit line through a switching device; a sense amplifier for comparing an electric potential of said first bit line with a reference potential in order to read out data in said memory cell when said memory cell is connected to said first bit line through said switching device; first and second dummy memory cells having ferroelectric capacitors which are selectively connected to a second bit line and a third bit line through switching devices in order to apply said reference potential to said sense amplifier; and short-circuit means which short-circuits said second and third bit lines at the time of said data reading, wherein said ferroelectric capacitors of both of said dummy memory cells are polarized to opposite directions relative to one another, and wherein, when the data is read out, the operation to apply the electric potentials from both of said dummy memory cells to each bit line corresponding thereto is executed in a state where both of said second and third bit lines are mutually electrically shut off, and thereafter, an intermediate value of both electric potentials of both of said second and third bit lines which is obtained by said short-circuit of both of said second and third bit lines by said short-circuit means is supplied as the reference potential to said sense amplifier.