Patent ID: 7500065

Claim:
A cache coherent data processing system, comprising: a plurality of processing units each having at least an associated upper cache memory; a lower cache memory associated with the plurality of processing units, wherein the lower cache memory includes: a plurality of storage locations for storing a memory block of data, wherein each of the plurality of storage locations is sized to store a sub-block of data; metadata storage for storing metadata describing the memory block; and a memory controller that is coupled to and controls access to the lower cache memory, wherein the memory controller overwrites at least a portion of metadata in the metadata storage associated with a particular sub-block of data with a coherency state determined as a function of: (1) first coherency metadata related to the particular sub-block of data indicated in the metadata storage, and (2) second coherency metadata related to the particular sub-block of data indicated in the upper cache memory, wherein the memory controller determines a relative priority of the first coherency metadata and the second coherency metadata, wherein the relative priority between coherency metadata is defined as: (Mx|Tx)<<Ig<<Sl<<S<<In<<I, wherein all coherency metadata to the left of a coherency metadata has priority over that coherency metadata.