Patent ID: 7564264

Claim:
An integrated circuit, comprising: a switch having first and second output nodes, a power terminal coupled to a supply voltage, and a ground terminal; the switch having: a first p-type transistor having a first p-type source node coupled to the power terminal and having a first p-type drain node coupled to the first output node; a second p-type transistor having a second p-type source node coupled to the power terminal and having a second p-type drain node coupled to the second output node; a first n-type transistor having a first n-type drain node coupled to the ground terminal and having a first n-type source node coupled to ground potential; a third p-type transistor having a third p-type source node coupled to the power terminal, a third p-type drain node coupled to the first output node, and a fourth gate node coupled to the second output node; and a fourth p-type transistor having a fourth p-type source node coupled to the power terminal, a fourth p-type drain node coupled to the second output node, and a fifth gate node coupled to the first output node; a first gate of the first p-type transistor, a second gate of the second p-type transistor, and a third gate of the first n-type transistor being commonly coupled to receive a control signal for selectively activating an inactive mode and an active mode of the switch; wherein in the inactive mode, the control signal: decouples the switch from the ground potential via the first n-type transistor; and applies the supply voltage to the first output node and the second output node via the first p-type transistor and the second p-type transistor, respectively; wherein application of the supply voltage to the first output node and the second output node prevents Negative Bias Temperature Instability (“NBTI”) damage in the switch; a delay line including a plurality of switches coupled in series, the plurality of switches including the switch; the third p-type transistor and the fourth p-type transistor each being at least four times stronger with respect to a power-down cycle than the first p-type transistor and the second p-type transistor, respectively, for respective shunting of the first p-type transistor and the second p-type transistor to allow spreading out of power draw during the power-down cycle and to lessen peak current draw when transitioning to the inactive mode.