Patent ID: 7400525

Claim:
A memory cell for interconnection with true and complementary bit lines and READ and WRITE word lines, said cell comprising: a first inverter having a first inverter double-gate pull-down device; a second inverter having a second inverter double-gate pull-down device, said second inverter being cross-coupled to said first inverter to form a storage flip-flop; and first and second access devices configured to selectively interconnect said cross-coupled inverters with the true and complementary bit lines, said first and second access devices being double-gate devices, each having a first gate connected to the READ word line and a second gate connected to the WRITE word line, wherein: during a READ operation, said first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OFF” while said double-gate pull-down devices are configured to operate in a double gate mode; and during a WRITE operation, said first and second access devices are configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON”.