Patent ID: 7170167

Claim:
A wafer level chip scale package structure process, comprising: providing a glass substrate having a first surface and a second surface, wherein an interconnect pattern is disposed on the first surface of the glass substrate; providing a wafer comprising a plurality of chips and having an active surface and a back surface, wherein a plurality of bumps is disposed on the active surface of the wafer; flipping the wafer, so that the active surface of the wafer faces the first surface of the glass substrate; disposing the wafer on the glass substrate and connecting the active surface of the wafer to the first surface of the glass substrate through attachment of the bumps and the interconnect pattern; performing a first dicing step whereby the wafer is cut; drilling the glass substrate to form a plurality of through holes; subsequent to the first dicing step, forming a plurality of via plugs in the through plated holes in the glass substrate; and performing a second dicing step to dice the glass substrate and the interconnect pattern at the through hole to form a plurality of chip scale package structures with plated/or metal or metallic layers on the side edges of the substrate.