Patent ID: 7534653

Claim:
A chip packaging process, comprising: providing a wafer, said wafer having an active surface and a backside corresponding to said active surface, said wafer having a first chip area and a second chip area adjacent to said first chip area, said wafer having a plurality of first and second bond pads on said active surface in said first and second chip areas respectively; forming a plurality of through holes on said wafer, said plurality of through holes passing through said wafer and connecting said active surface and said backside, said through holes being arranged between said first chip area and said second chip area; forming a plurality of connecting lines on peripheral surfaces of said through holes, wherein each of said connecting lines has a first end portion extending on said active surface and electrically connecting to one of said first bond pads and one of said second bond pads; and disposing a first rigid cover and a second rigid cover on said active surface of said first chip area and said active surface of said second chip area respectively, wherein said first rigid cover and said second rigid cover respectively have a plurality of rows and columns of openings exposing the corresponding first bond pads and the corresponding; second bond pads.