Patent ID: 8619468

Claim:
A semiconductor memory device comprising: first and second bit lines; first and second word lines; first and second select transistors; a source line; a plurality of memory cells including first, second, third and fourth memory cells, each memory cell capable of storing n bits of data (n is a natural number equal to or larger than two), the first memory cell connected to the first word line, coupled to the first bit line and coupled to the source line via the first select transistor, the second memory cell being adjacent to the first memory cell along the first word line, connected to the first word line, coupled to the second bit line and coupled to the source line via the second select transistor, the third memory cell connected to the second word line, coupled to the first bit line and coupled to the source line via the first select transistor and the first memory cell, a source of the third memory cell connected to a drain of the first memory cell, the fourth memory cell being adjacent to the third memory cell along the second word line, connected to the second word line, coupled to the second bit line and coupled to the source line via the second select transistor and the second memory cell, a source of the fourth memory cell connected to a drain of the second memory cell; and a write circuit configured to write n bits of data into each of the memory cells, wherein: a first bit of data to be stored in the first memory cell is assigned to a first page address; a second bit of data to be stored in the second memory cell is assigned to a second page address which is consecutive to the first page address; a third bit of data to be stored in the third memory cell is assigned to a third page address which is consecutive to the second page address; a fourth bit of data to be stored in the fourth memory cell is assigned to a fourth page address which is consecutive to the third page address; a fifth bit of data to be stored in the first memory cell is assigned to a fifth page address which is consecutive to the fourth page address; the write circuit is configured to write the first bit of data into the first memory cell by altering a threshold voltage of the first memory cell from a first voltage to a second voltage according to a first logical state of the first bit of data; the write circuit is configured to write the fifth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the second voltage to a third voltage according to a first logical state of the fifth bit of data; and the write circuit is configured to write the fifth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the second voltage to a fourth voltage higher than the third voltage according to a second logical state of the fifth bit of data.