Patent ID: 8264896

Claim:
An integrated circuit comprising: a plurality of memory cells organized in rows and columns, wherein a row comprises a word line and all of the memory cells coupled to the word line and a column comprises a bit line pair and all of the memory cells coupled to the bit line pair; an array supply voltage control circuit coupled to the plurality of memory cells, the array supply voltage control circuit for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column, wherein the array supply voltage control circuit comprises: a logic gate having a first input for receiving a write select signal, a second input for receiving a column select signal, and an output; a first transistor having a first current electrode coupled to receive the power supply voltage, a control electrode coupled to the output of the logic gate, and a second current electrode coupled to power supply terminals of each memory cell of the selected column of memory cells; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the output of the logic gate, and a second current electrode; a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to a first bit line of the bit line pair, and a second current electrode; and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to a second bit line of the bit line pair, and a second current electrode coupled to ground.