Patent ID: 7042050

Claim:
A semiconductor device comprising: a gate insulating film which is formed on a major surface of a semiconductor substrate; a gate electrode which is formed on the gate insulating film; a first offset-spacer which is formed in contact with one side surface of the gate electrode; a first spacer which is formed in contact with the other side surface of the gate electrode; a second spacer which is formed in contact with the first offset-spacer; a first source region and a first drain region which are formed apart from each other in the major surface of the semiconductor substrate below the first and second spacers so as to sandwich the gate electrode and the first offset-spacer, the first source region being formed at a position deeper than the first drain region and a dopant concentration of the first source region being higher than a dopant concentration of the first drain region; a second source region which is formed adjacent to the first source region, the second source region being formed at a position deeper than the first source region and a dopant concentration of the second source region being higher than the dopant concentration of the first source region; and a second drain region which is formed adjacent to the first drain region, the second drain region being formed at a position deeper than the first drain region and a dopant concentration of the second drain region being higher than the dopant concentration of the first drain region.