Patent ID: 8830749

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of planes, each plane including a plurality of blocks; a bad block detector configured to determine whether each of input addresses for accessing corresponding blocks of the plurality of planes corresponds to any of bad block addresses and sequentially output a plurality of bad-block pulses showing the determination results according to an input sequence of the input addresses, a bad block address being an address for accessing a block determined as a bad block; and a block selector configured to receive the plurality of bad-block pulses and select the corresponding blocks of the plurality of planes in response to the plurality of bad-block pulses, respectively, wherein the bad block detector comprises: a latch unit configured to store the bad block addresses; a comparator configured to compare the bad block addresses with each of the input addresses to output a bad-block detection signal; and a bad block controller configured to sequentially output the plurality of bad-block pulses corresponding to the bad-block detection signal in response to a plurality of bad-block flag signals that are sequentially activated according to the input sequence of the input addresses, wherein the plurality of bad-block flag signals corresponds to the plurality of planes, respectively.