Patent ID: 7172940

Claim:
A method of fabricating a single-poly non-volatile memory, comprising: providing a semiconductor substrate having thereon a memory array region and a peripheral region; forming a device isolation structure on said semiconductor substrate, said device isolation structure isolating a first active area and a second active area within said peripheral region; forming a charge storage structure on said semiconductor substrate; removing said charge storage structure from said peripheral region; forming a first gate oxide layer on said first active area and a second gate oxide layer on said second active area within said peripheral region; forming a first gate on said first gate oxide layer and a second gate on said second oxide layer within said peripheral region, and a third gate on said charge storage structure within said memory array region, concurrently; forming a photoresist pattern masking said peripheral region but exposing entire said memory array region; etching away said charge storage structure not covered by said third gate within said memory array region, wherein said third gate and said photoresist pattern together act as an etching hard mask; implanting said memory array region by using said photoresist pattern and said third gate as an implant mask to form lightly doped drain regions in said semiconductor substrate adjacent to said third gate; and stripping said photoresist pattern.