Patent ID: 8432206

Claim:
A delay lock loop system with a self-tracking function, the delay lock loop system comprising: a timing controller for outputting an external enable signal periodically while a power saving signal is a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal; a pulse generator for generating a pulse according to a positive edge of the power saving signal; an OR gate having a first terminal for receiving the power saving signal, a second terminal coupled to the timing controller for receiving the external enable signal, a third terminal coupled to the pulse generator for receiving the pulse, and an output terminal for outputting an enable signal; an input buffer for receiving an external clock, and outputting an adjusted clock; and a delay lock loop (DLL) coupled to the OR gate and the input buffer for receiving the adjusted clock and the enable signal, the delay lock loop comprising a voltage control delay circuit for synchronizing a phase of the adjusted clock with a phase of an output clock of the delay lock loop, and the delay lock loop being enabled again according to the enable signal.