Patent ID: 6990623

Claim:
A method for error detection/correction of a multilevel cell memory having memory cells each for retaining two bits of data, the method comprising the steps of: assigning binary bit addresses, for error detection, said binary bit addresses designating individual bits of said memory cells such that each pair of said binary bit addresses corresponding to each of said memory cells is mutually exclusive in each digit; generating, for each digit of said binary bit addresses, first parity codes including a parity code of write data corresponding to all of said binary bit addresses having “0” in said digit and a parity code of said write data corresponding to all of said binary bit addresses having “1” in said digit; generating first parity codes of read data corresponding to said binary bit addresses whose combinations are the same as used in the generation of said first parity codes of said write data, when reading data from said memory cells; and detecting a presence of one memory cell storing erroneous data in both bits when said first parity codes generated in the read operation are all different from said first parity codes generated in the write operation.