Patent ID: 7230877

Claim:
A method for fabricating a semiconductor memory device, which comprises the steps of: providing a semiconductor substrate having a first conductivity type; providing an insulating layer on the semiconductor substrate; forming a matrix of contact holes down to the semiconductor substrate in the insulating layer in accordance with respective the semiconductor memory elements; providing a surface region of the semiconductor substrate situated underneath each of the contact holes with a contact resistance in accordance with a bit to be stored in a respective semiconductor memory element as a bit definition region of the respective semiconductor memory element, the contact resistance formed by the steps of: performing a first implantation with a dopant of the first conductivity type into a first group of the contact holes with remaining ones of the contact holes being masked; performing a second implantation with a dopant of a second conductivity type into a second group of the contact holes with remaining ones of the contact holes being masked; and leaving the surface region of the semiconductor substrate situated underneath the respective contact holes in a substrate doping in a third group of contact holes undoped; providing contact plugs in the contact holes, the contact plugs being in electrical contact with the bit definition region; and providing a further contact region located in the semiconductor substrate outside the bit definition region.