Patent ID: 8581299

Claim:
A semiconductor device comprising: a semiconductor substrate having a main surface; and first and second insulated gate bipolar transistors formed on the main surface, respectively, wherein each of the first and second insulated gate bipolar transistors includes: a first conductive collector region formed on the main surface; a first conductive base region formed on the main surface separately from the collector region; a second conductive emitter region formed on the main surface in the base region; an emitter conductive layer coupled to both the base region and the emitter region of each of the first and second insulated gate bipolar transistors; and a collector conductive layer coupled to the collector region of each of the first and second insulated gate bipolar transistors, and wherein the ratio (SB 11 /SA 11 ) of the area (SB 11 ) of the junction of the base region and the emitter conductive layer in the first insulated gate bipolar transistor, to the area (SA 11 ) in the main surface of the base region of the first insulated gate bipolar transistor, is greater than the ratio (SB 21 /SA 21 ) of the area (SB 21 ) of the junction of the base region and the emitter conductive layer of the second insulated gate bipolar transistor, to the area (SA 21 ) of the base region in the main surface of the second insulated gate bipolar transistor.