Patent ID: 6893911

Claim:
A method for forming an IC comprising: providing a substrate prepared with a first region, the first region comprising first and second trench isolations, wherein the trench isolation comprises dielectric material formed in a trench which extends above the surface of the substrate to form a gap between the trench isolations, an active area located between the trench isolations; depositing first and second etch stop layers lining the substrate surface and trench isolations without filling the gap, the first etch stop layer disposed beneath the second etch stop layer, the second etch stop layer includes horizontal and vertical components created by a topography of the substrate; removing the vertical portions of the second etch stop layer; isotropically etching the first etch stop layer selective to the second etch stop layer, the isotropic etch overetches the first etch stop layer to create an undercut under second etch stop layer, the undercut exposes edge portions of the active region; removing the second etch stop layer; and oxidizing the edge portions of the active area unprotected by the first etch stop layer.