Patent ID: 7566604

Claim:
A method of fabricating a semiconductor comprising: forming a first region and a second region in a substrate, the first region having p-type conductivity and the second region having n-type conductivity; forming a silicon oxide layer on the first and second regions; depositing a first polysilicon layer on an entirety of the silicon oxide layer; removing part of the first polysilicon layer so that the silicon oxide layer over the second region is exposed and so that a portion of the first polysilicon layer remains over the first region; forming a silicon nitride layer on the remaining first polysilicon layer; removing the silicon oxide layer from over the second region using the silicon nitride layer as a mask; forming a silicon nitride oxide layer on the substrate in the second region using the silicon nitride layer as a mask; depositing a second polysilicon layer over the first and second regions on the silicon nitride layer and on the silicon nitride oxide layer; removing part of the second polysilicon layer so that the silicon nitride layer is exposed above the first region and so that a portion of the second polysilicon layer remains over the second region; removing the silicon nitride layer; and patterning the silicon oxide layer, the remaining first polysilicon layer, the silicon nitride oxide layer and the remaining second polysilicon layer, to respectively form a first gate insulator and a first gate in the second region, and a second gate insulator and a second gate in the second region.