Patent ID: 8533423

Claim:
A system for performing parallel multi-level data computations in a storage system, comprising: a memory storing data; a plurality of caches, each cache including a memory capacity; and a processor coupled to the memory and the plurality of caches, wherein the processor comprises code that, when executed by the processor, cause the processor to: determine a total amount of data in the memory to be processed, divide the amount of data by a memory capacity of each cache to determine a plurality of computation nodes needed for processing the total amount of data, and automatically create the plurality of computation nodes, the plurality of computation nodes forming a tree structure comprising a plurality of levels, wherein: a lowest level of the tree structure comprises a first number of computation nodes equal to the total amount of data divided by the memory capacity of each cache, each computation node at the lowest level processes an amount of data equal to the memory capacity of each cache, and each level above the lowest level comprises one or more computation nodes that receive an input from a second number of computation nodes from a lower level, the second number of computation nodes is based on a predetermined constraint.