Patent ID: 7276746

Claim:
A metal-oxide-semiconductor integrated circuit varactor comprising: a p-substrate; a deep n-well formed in the p-substrate; an n-well formed in the deep n-well; an n+ region formed in the n-well; an oxide layer formed on the n-well; a first electrode formed on the oxide layer; and a second electrode formed on the n+ region, wherein at least a portion of the second electrode forms a strip having a longitudinal dimension and wherein semiconductor fabrication process design rules specify a maximum value indicating how many contact vias may be formed in the strip per unit length along the longitudinal dimension, the metal-oxide-semiconductor integrated circuit varactor further comprising: a plurality of contact vias in the second electrode, wherein the plurality of contact vias make electrical contact with the n+ region, and wherein there are fewer contact vias per unit length along the longitudinal dimension than specified by the maximum value.