Patent ID: 6972457

Claim:
A semiconductor circuit comprising: a MOS transistor having: spaced-apart source and drain regions of a first conductivity type that contact a semiconductor region of a second conductivity type, the semiconductor region having a top surface, one of the source and drain regions having a first bottom point that lies furthest away from the top surface, and a first depth measured from the top surface to the first bottom point along a line perpendicular to the top surface; a channel region located between the source and drain regions; and a gate formed over, and insulated from, the channel region; and an imaging cell having: spaced-apart source and drain regions of the first conductivity type that contact the semiconductor region, one of the source and drain regions of the imaging cell having a second bottom point that lies furthest away from the top surface, and a second depth measured from the top surface to the second bottom point along a line perpendicular to the top surface wherein the second depth is substantially larger than the first depth; a channel region located between the source and drain regions of the imaging cell; a floating gate formed over, and insulated from, the channel region of the imaging cell; and a control gate well of the first conductivity type, the floating gate being formed over and insulated from the control gate well.