Patent ID: 7510928

Claim:
A method for fabricating an integrated circuit, the method comprising: forming a first conductive layer having a first portion and one or more second portions; forming a first dielectric layer over at least the first portion; forming one or more first dielectric trenches in the first conductive layer, the first dielectric trenches completely laterally surrounding the second portions and insulating the second portions from the first portion, the first portion completely laterally surrounding the first dielectric trenches; forming a second conductive layer over the first conductive layer and the first dielectric layer, the second conductive layer having a third portion and one or more fourth portions, the third portion being in physical contact with each second portion, each fourth portion being in physical contact with the first portion, the third portion being separated from the first portion by the first dielectric layer; forming one or more second dielectric trenches in the second conductive layer, the second dielectric trenches completely laterally surrounding the fourth portions and separating the fourth portions from the third portion.