Patent ID: 7143331

Claim:
An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words, the apparatus comprising: a memory access circuit for controlling reading and writing of the code words to the buffer memory; a symbol counter for counting the number of symbols of the code words read from the buffer memory and generating a count value of a plurality of bits; a plurality of operational circuits for performing a syndrome calculation with each of the multiple code words read from the buffer memory; and an error correction circuit for performing an error correction process on the multiple code words read from the buffer memory based on the syndrome calculation performed by the plurality of operational circuits, wherein the memory access circuit consecutively reads the multiple code words from the buffer memory and distributes the read code words to the plurality of operational circuits based on the count value of the lower two bits of the plurality of bits; wherein the symbol counter includes: a register for holding the count value; a decoder for distributing the symbols read from the buffer memory to the plurality of the operational circuits in accordance with the count value of the lower two bits; and a count control circuit for altering the count value in accordance with a timing for reading the symbols.