Patent ID: 7084025

Claim:
A method of fabrication of a semiconductor device comprising steps of: a) forming a bottom pad dielectric layer and a silicon containing layer over a substrate; said bottom pad dielectric layer has a first thickness; b) patterning the silicon containing layer to form a sacrificial gate; c) performing a sacrificial gate amorphization implant by implanting ions into said sacrificial gate to form an amorphous layer; d) thermally oxidizing said sacrificial gate, and said amorphous layer to form sacrificial spacers on the sidewalls of said sacrificial gate; e) performing a LDD implant to form LDD regions adjacent to said sacrificial gate; f) in a bottom pad dielectric thinning step, removing the sacrificial spacers and removing a thickness of said bottom pad dielectric layer so that said bottom pad dielectric layer has a second thickness; g) forming spacers on said sacrificial gate; i) performing a S/D implant to form S/D regions adjacent to said sacrificial gate; j) forming a dielectric layer over said substrate; k) planarizing said dielectric layer to expose said sacrificial gate; l) removing said sacrificial gate to form a gate opening that expose an exposed portion of said bottom pad dielectric layer; m) removing the exposed portion of said bottom pad dielectric layer in said gate opening; n) forming a gate dielectric layer on said substrate that is exposed in said gate opening; o) forming a gate in said gate opening over said gate dielectric layer.