Patent ID: 7117406

Claim:
A semiconductor memory device comprising: a plurality of memory cells, each of which includes latch means for storing bit data which composes a word of a plurality of words; test target word selecting means for determining a memory cell as a test target memory cell which stores bit data of a test target word by selecting an arbitrary word of said plurality of words as said test target word; initializing means for initializing said plurality of memory cells by storing identical data to all of said plurality of memory cells in response to a simultaneous writing signal supplied; negative feedback means for storing inverted bit data into said test target memory cell, the inverted bit data being formed by inverting bit data outputted from said test target memory cell; reading means for reading all of said plurality of words; and comparator means for comparing expectation values and all of said read words, wherein said test target word selecting means includes a test target word changing means for changing said test target word to another word; wherein after said storing said inverted bit data, only said test target memory cell contains said inverted bit data and all of said plurality of memory cells other than said test target memory cell contain said identical data; and wherein said initializing said plurality of memory cells, said storing inverted bit data, said reading all of said plurality of words and said comparing said expectation values and said read words are repeated with each of said changing of said test target word to said another word, wherein said negative feedback means comprise data retaining means for retaining input bit data which is either bit data via a scan path or said inverted bit data, and for outputting said inputted bit data to said test target memory cell and said scan path, and further comprising input data selection means for selectively writing a plurality of pieces of input data supplied thereto to said memory cells.