Patent ID: 7883947

Claim:
A method of forming an integrated circuit, the method comprising: aligning at least one of a plurality of exposed terminals on a first semiconductor die with at least one of a plurality of exposed terminals on a second semiconductor die, the first semiconductor die comprising a first plurality of exposed terminals and a plurality of features having a first minimum feature size less than or equal to 0.13 μm, the second semiconductor die comprising a second plurality of exposed terminals, wherein at least one of the second plurality of exposed terminals is in electrical communication with one or more of the first plurality of exposed terminals, a plurality of input and/or output (I/O) circuits, wherein at least one of the I/O circuits is in electrical communication with the at least one of the second plurality of exposed terminals, and a plurality of I/O terminals, wherein at least one of the I/O terminals is in electrical communication with the at least one of the I/O circuits, wherein all features on the second die have a second minimum feature size greater than or equal to 0.18 μm; and forming at least one electrical junction between (i) the at least one of the second plurality of exposed terminals and (ii) the at least one of the first plurality of exposed terminals, such that the at least one of the first plurality of exposed terminals is in electrical communication with an I/O circuit in the second die and with an I/O terminal on the second die.