Patent ID: 7501871

Claim:
A latch circuit receiving an inverting input signal, a non-inverting clock signal, an inverting clock signal, and a common mode control signal; and producing a non-inverting output signal and an inverting output signal, the latch circuit comprising; a first transistor having its drain coupled to the non-inverting output signal and its gate coupled to the inverting output signal; a second transistor having its drain coupled to the non-inverting output signal, its gate coupled to the non-inverting clock signal, and its source coupled to the source of the first transistor; a third transistor having its gate coupled to the common mode control signal, and its source coupled to the source of the first transistor; a fourth transistor having its drain coupled to the drain of the third transistor, and its gate coupled to the common mode control signal; a fifth transistor having its drain coupled to the non-inverting output signal, its gate coupled to the inverting input signal, and its source coupled to the source of the fourth transistor; and a sixth transistor having its drain coupled to the non-inverting output signal, its gate coupled to the inverting clock signal and its source coupled to the source of the fourth transistor.