Patent ID: 7616034

Claim:
A data output control circuit comprising: a delay lock loop configured to output a first clock by delaying an external clock in response to a control signal; a phase detector configured to output a detection signal by detecting a frequency of the external clock in response to the control signal; a decoder configured to output a selection signal by decoding the detection signal; and a delay unit configured to output a second clock by delaying the first clock or inverting and delaying a phase of the first clock in response to the selection signal, wherein the phase detector includes an edge signal generator configured to generate a first edge signal synchronized with the first rising edge of the external clock, and a second edge signal synchronized with the second rising edge of the external clock; a delay component configured to generate at least one edge delay signal by delaying the first edge signal; an edge delay signal determiner for generating the detection signal according to level states of the edge delay signal in response to the second edge signal; and a clock transfer unit configured to selectively transfer the external clock to the edge signal generator in response to the control signal.