Patent ID: 7205801

Claim:
A power down circuit for controlling a current flow of a subsequent circuit having a N channel MOS transistor and a P channel MOS transistor arranged in series between the power source terminal and a ground terminal, the subsequent circuit also having a control terminal for receiving a bias voltage and an output of the power down circuit, the power down circuit comprising: a first N channel MOS transistor having a drain, a source connected to the ground terminal and a gate receiving a power down control signal; a load element connected between the power source terminal and the drain of the first N channel MOS transistor; and a second N channel MOS transistor having a first terminal for receiving a signal based on the power down control signal, a gate connected to the drain of the first N MOS transistor and a second terminal connected to the control terminal of the subsequent circuit; wherein a resistance value of the load element and an operation resistance value of the first N channel MOS transistor are set up so that the second N channel MOS transistor is being OFF state during the first N channel MOS transistor turns on, and the second N channel MOS transistor turns on during the first N channel MOS transistor is being OFF state.