Patent ID: 8214592

Claim:
A cache system, comprising: a plurality of cache lines; wherein a first cache line of the plurality of cache lines includes: a plurality of cache cells; a bus coupled to the plurality of cache cells, wherein the bus includes a switch that is operable to receive a first control signal and to split the bus into a first portion and a second portion without conductivity therebetween in response to a first state of the first control signal and to aggregate the bus into a whole in which the first portion and the second portion have conductivity therebetween in response to a second state of the first control signal; and a multiplexor coupled to the bus; wherein, when the bus is split, a first cache cell of the plurality of cache cells is coupled to the first portion of the bus and a second cache cell of the plurality of cache cells is coupled to the second portion of the bus; wherein a first input and a second input of the multiplexor are coupled to the bus such that, when the bus is split, the first input is coupled to the first portion of the bus and the second input is coupled to the second portion of the bus; and wherein the multiplexor is operable to receive a second control signal and to output first data from the first portion of the bus in response to a first state of the first control signal and to output second data from the second portion of the bus in response to a second state of the second control signal.