Patent ID: 7197626

Claim:
A computer system for use with a device, the system comprising: a central processing unit (CPU); a main memory; at least one device interface configured to be coupled to the device and to receive process requests from the device; a further unit comprising: a first microcontroller module; a first memory containing a first set of instructions configured to cause the first microcontroller module to manage CPU operations and to cause the first microcontroller to allocate CPU resources to each of the process requests received by the at least one device interface; a second microcontroller module in communication with the first microcontroller and configured to receive the process requests from the at least one device interface; a second memory containing a second set of instructions configured to cause the second microcontroller module to manage the device, and to identify the device and a means of connection used by the device; a third microcontroller module in communication with the first microcontroller; a third memory containing a third set of instructions configured to cause the third microcontroller module to manage memory operations; a fourth microcontroller module in communication with the first microcontroller; a fourth memory containing a fourth set of instructions configured to cause the fourth microcontroller module to manage data operations, wherein the CPU and the further unit both reside on a motherboard; and a plurality of trace links connecting the further unit to the CPU, the main memory, and the device interface to facilitate communication between the further unit, the CPU, the main memory, and the device.