Patent ID: 8693557

Claim:
A clock receiver for rejecting common-mode noise in a differential clock signal, the clock receiver comprising: a capacitive coupling circuit configured to receive an input differential clock signal and generate a filtered differential clock signal by high-pass filtering the input differential clock signal; a bias voltage generator configured to generate a bias voltage; a bias circuit coupled to the capacitive coupling circuit and the bias voltage generator, the bias circuit including a first resistor having a first end configured to receive a first component signal of the filtered differential clock signal and a second end configured to receive the bias voltage and a second resistor having a first end coupled to the second end of the first resistor and configured to receive the bias voltage and a second end configured to receive a second component signal of the filtered differential clock signal, the bias circuit configured to generate a biased differential clock signal based on the filtered differential clock signal, the bias voltage, and a feedback differential clock signal; and a differential amplifier coupled to the bias circuit, the differential amplifier configured to generate an output differential clock signal by amplifying the biased differential clock signal and to generate the feedback differential clock signal based on the output differential clock signal.