Patent ID: 6914945

Claim:
A clock recovery circuit provided to a receiving device which receives digital broadcasts using a vestigial sideband (VSB) modulation method, comprising: a first band pass filter which, when a symbol rate of a received signal is fs, extracts a signal of an fs/2 frequency component from an in-phase component of a VSB signal which has been converted to baseband; a second band pass filter which extracts a signal of an fs/2 frequency component from a quadrature-phase component of said VSB signal; a delay element which delays an output signal of said second band pass filter by Π/4; a first multiplier which squares an output signal of said first band pass filter; a second multiplier which squares an output signal of said delay element; an adder which adds together an output signal of said first multiplier and an output signal of said second multiplier; a third band pass filter which extracts a signal of an fs frequency component from an output signal of said adder, and outputs a symbol clock received signal; a phase error detector which detects a phase error between the symbol clock received signal of said third band pass filter and a reference clock of the receiving device; and a loop filter which smoothes a phase error signal which is outputted by said phase error detector.