Patent ID: 7602012

Claim:
A semiconductor memory device comprising: a control electrode disposed on a gate insulating film disposed on a major surface of a semiconductor substrate; a pair of diffusion regions formed in said major surface of the semiconductor substrate on mutually opposite sides of the control electrode; a pair of variable resistance regions formed in said major surface of the semiconductor substrate on mutually opposite sides of the control electrode, disposed between the pair of diffusion regions and the control electrode, and having a lower impurity concentration than the pair of diffusion regions; and a pair of charge traps disposed above the pair of variable resistance regions, each charge trap including a tunnel oxide film, a charge trapping film disposed on the tunnel oxide film, and a top oxide film disposed on the charge trapping film; wherein the charge trapping film has a dual-layer structure including a first layer formed on and over the tunnel oxide film and a second layer formed on and over the first layer, the first layer having a first band gap with a first upper boundary, the second layer having a second band gap with a second upper boundary, the first band gap including a first charge trapping level, the first upper boundary being lower than the second upper boundary.