Patent ID: 8732510

Claim:
A digital frequency generator that produces an output frequency relative to a reference clock, a device including: a reference clock signal having cycles, an accumulator stage coupled to the reference clock, that iteratively signals a terminal condition signal and a remainder signal after a number of cycles that it would take to reach an overflow (or underflow) condition by repeatedly accumulating a positive (or negative) numerator and overflowing (or underflowing) an accumulator that has a range from zero to a denominator minus one; a selector, coupled to the terminal condition signal and the remainder signal of the accumulator stage, including a state machine and an output section, wherein the state machine undergoes transitions, responsive to the terminal condition signal, through (a) a low value state, (b) a rising intermediate value state, (c) a high value state, (d) a falling intermediate value state, and circularly to (a) the low value state; wherein the output section outputs value signals responsive to the state machine, (a) outputting a low value responsive to the low value state, (b) outputting a rising intermediate value, during the rising intermediate value state and responsive to the remainder signal, (c) outputting a high value responsive to the high value state, and (d) outputting a falling intermediate value, during the falling intermediate value state and responsive to the remainder signal, a digital to analog converter (abbreviated DAC) coupled to the value signals, wherein the DAC outputs an analog signal responsive the value signal; a filter coupled to the analog signal, outputting a filtered analog signal; and a comparator coupled to the filtered analog signal and outputting a stream of pulses.