Patent ID: 7443222

Claim:
Circuitry to generate a dynamically controlled clock, the circuitry comprising: a clock input terminal to couple to a running clock; a first input terminal to couple to a first control signal from a programmed antifuse; a second input terminal to couple to a second control signal indicative of a switching fabric state; an output terminal to provide the dynamically controlled clock; a first gate comprising a first data input port coupled to the clock input terminal; a second data input port; and a data output port coupled to the output terminal; a clock generator comprising a clock generator input port coupled to the clock input terminal; and a clock generator output port to provide an internal clock out-of-phase from the running clock; a register comprising a register clock input port coupled to the clock generator output port; a register data input port coupled to the first input terminal; and a register data output port coupled to the second data input port of the first gate; wherein the second input terminal is coupled to switch a signal to one of the clock generator input port and the register data input port.