Patent ID: 7697320

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines provided with respect to the rows of the memory cells, including a first word line; a plurality of bit lines provided with respect to the columns of the memory cells, including a first and a second bit line; and a plurality of column lines provided with respect to the columns of the memory cells, including a first and a second column line, wherein each of the memory cells includes: a first access transistor provided between the corresponding first bit line of the bit lines and a first memory node, and controlled by the corresponding first word line of the word lines; a second access transistor provided between the corresponding second bit line of the bit lines and a second memory node, and controlled by the first word line; a latch circuit having the first and second memory nodes; a third access transistor connected in parallel to the first access transistor, and having a gate terminal connected to the first column line; and a fourth access transistor connected in parallel to the second access transistor, and having a gate terminal connected to the second column line.