Patent ID: 7058920

Claim:
A method of designing a programmable logic device (PLD), comprising: a) designing the PLD such that the PLD includes a plurality of logic elements (LE's) arranged in an array; b) designing the PLD such that the PLD includes a base signal routing architecture including a plurality of signal routing lines to route signals among the LE's, the base signal routing architecture characterized by a signal routing timing model; c) determining, if the base signal routing architecture is extended across an intellectual property IP-function lock portion incorporated within the array of LE's, an amount by which the resulting timing would differ from the signal routing timing model; and d) based on the determined difference amount, determining whether to design the PLD to extend the signal routing architecture of the PLD across the IP function block portion or to configure the design to include a hole within the base signal routing architecture to accommodate the IP function block portion.