Patent ID: 6850459

Claim:
A synchronous semiconductor memory device operating in synchronization with a clock signal, comprising: a memory cell array having a plurality of memory cells arranged; an output control circuit burst-reading a plurality of read data from said memory cell array, and sequentially generating a plurality of read instructions indicating levels of said plurality of read data respectively, in synchronization with said clock signal; a data output circuit outputting data in response to each of the sequentially generated said plurality of read instructions; a transmission control unit provided between said output control circuit and said data output circuit and transmitting each of said plurality of read instructions generated by said output control circuit to said data output circuit; and a signal propagation control circuit determining whether each of said plurality of read instructions sequentially generated by said output control circuit corresponds to a first one or a second or following one of said plurality of read data; wherein said transmission control unit transmits, in accordance with a result of determination by said signal propagation control circuit, said read instruction corresponding to said first one of said plurality of read data with a first transmission time to said data output circuit, and transmits said read instruction corresponding to said second or following one of said plurality of read data with a second transmission time being different from said first transmission time to said data output circuit.