Patent ID: 8429576

Claim:
A system for analyzing parametric yield of a semiconductor chip design comprising: threshold voltage adder calculation means for calculating a calculated threshold voltage adder for a device within a subset of a semiconductor chip design including an effect of at least one design parameter of said subset other than inherent geometric dimensions and inherent characteristics of said device; parametric yield estimation means for estimating a parametric yield estimation value of said subset of said semiconductor chip design, wherein said parametric yield estimation value is based on said calculated threshold voltage adder; a tester for generating at least one measured parametric yield value by testing at least one semiconductor chip that is manufactured according to said semiconductor chip design; parametric yield comparison means for comparing said parametric yield estimation value and said at least one measured parametric yield value; and incremental on-current deviation calculation means for calculating an incremental on-current deviation for said subset of said semiconductor chip design, wherein said incremental on-current deviation is an increment in statistical deviation of on-current of said subset of said semiconductor chip design from a scaling-estimated statistical deviation of on-current, which is obtained by scaling of statistical deviation of on-current of at least one nominal device, due to design parameters of said subset other than inherent geometric dimensions and inherent characteristics of at least one device of said subset.