Patent ID: 7068203

Claim:
A pipelined analog-to-digital converter, comprising: a sample-and-hold circuit, having an input receiving an analog input signal, and having an output; a plurality of pipeline stages, each having an input and an output, the input of the first of the plurality of pipeline stages connected to the output of the sample-and-hold circuit, and the input of each of the other pipeline stages connected to the output of a preceding one of the pipeline stages, each of the plurality of pipeline stages comprising: an analog-to-digital converter stage, having an input connected to the input of its pipeline stage and having an output; a digital-to-analog converter stage, having an input connected to the output of the analog-to-digital converter stage, and having an output; and a residual gain generator circuit, having a first input connected to the input of its pipeline stage, having a second input connected to the output of the digital-to-analog converter stage, and having an output coupled to the output of its pipeline stage; a clock generator circuit, for generating a first clock phase and a second clock phase; wherein the sample-and-hold circuit operates according to a sample phase responsive to the first clock phase, and a hold phase responsive to the second clock phase, the sample-and-hold circuit generating an approximate output voltage during its sample phase; wherein the analog-to-digital converter stage of the first pipeline stage operates according to a sample phase responsive to the first clock phase to sample the approximate output voltage of the sample-and-hold circuit, and an operate phase responsive to the second clock phase; and wherein the residual gain generator circuit of the first pipeline stage operates according to a sample phase responsive to the second clock phase, and an operate phase responsive to the first clock phase.