Patent ID: 8739101

Claim:
A method for configuring a hardware design for a pipelined parallel stream processor, the method comprising: obtaining a scheduled graph representing a processing operation in a time domain as a function of clock cycles, the graph comprising at least one data path to be implemented in hardware as part of said stream processor and comprising at least one input, at least one output and a plurality of parallel branches configured to enable data values to be streamed therethrough from the at least one input to the at least one output as a function of increasing clock cycle; partitioning, on a computing device, said at least one data path into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements; inserting phase transition registers into said data path at a boundary between regions having different clock phases, said phase transition registers being operable to align data separated by a boundary between regions having different clock phases; utilizing, on a computing device, said graph and control logic elements to define a hardware design for implementation in hardware as said pipelined parallel stream processor.