Patent ID: 7057538

Claim:
A reduced-rate differential phase shift keyed (DPSK) encoder, comprising: a set of N encoder stages, wherein each stage comprises an exclusive-OR gate having a first input terminal for receiving, as an input, one of N parallel data bits, and a second input terminal, for receiving as an input, an output signal from an encoder stage responsible for encoding an immediately prior data bit; wherein each encoder stage further includes a bit storage device into which the output of the exclusive-OR gate is coupled upon the occurrence of a clocking signal applied to the bit storage device; and wherein output from the N th -stage bit storage device is fed back as an input to a first-stage exclusive-OR gate, to be used in the encoding of a (N+1) th , (2N+1) th and subsequent data bits that are input to the first-stage exclusive-OR gate in second and subsequent cycles of parallel encoding operations.