Patent ID: 8293573

Claim:
A method of packaging integrated circuits comprising: providing a lead frame panel having a plurality of device areas, each device area including an array of contact posts suitable for forming contact pads; attaching a plurality of dice to the lead frame, wherein each die is mounted on an associated device area; encapsulating the dice with an encapsulant material; exposing a distal surface of the contact pads of the contact posts in an orientation substantially co-planar with a bottom surface of the microarray package such that the contact pads have a first stress concentration point; and after said encapsulating, lowering the first stress concentration point associated with one of the contact pads such that a lowered stress concentration point is formed for said contact pad outside the encapsulated package and below the first stress concentration point by forming a pedestal member over the distal surface of the respective contact pad such that said pedestal member protrudes downward below the bottom surface of the microarray package by a height sufficient to displace the lowered stress concentration point a specified distance below the first stress concentration point and below the bottom surface of the microarray package, wherein said forming of the pedestal is accomplished by plating the one or more pedestal member to a depth upon which the distal surface protrudes beyond the respective contact pad in the range of about 15 μm to about 35 μm.