Patent ID: 8908461

Claim:
A refresh circuit in a semiconductor memory device having a first memory group and a second memory group, comprising: a signal generation unit configured to receive a refresh command signal REF and to generate a plurality of refresh signals having different timings during a refresh operation period corresponding to the refresh command signal REF; a first refresh circuit configured to generate a first group row enable pulse based on a first subset of the plurality of refresh signals to enable first refresh target lines of the first memory group during a first enable time period and configured to generate a second group row enable pulse subsequent to the first group row enable pulse to enable second refresh target lines of the first memory group during a second enable time period, wherein the first and second enable time periods are within the refresh operation period; and a second refresh circuit configured to generate a third group row enable pulse based on a third subset of the plurality of refresh signals to enable third refresh target lines of the second memory group during a third enable time period and configured to generate a fourth group row enable pulse subsequent to the third group row enable pulse to enable fourth refresh target lines of the second memory group during a fourth enable time period, wherein the third and fourth enable time periods are within the refresh operation period, wherein first enable time period and the third enable time period are timewise-overlapping and do not begin at the same time.