Patent ID: 8660171

Claim:
An apparatus for measuring timing jitter in the digital domain, the apparatus comprising: an analog/digital (A/D) converter for converting a signal to a digital signal; a PLL (Phase-Locked Loop), coupled to the A/D converter and providing a clock signal according to the frequency of the signal; and an interpolator bank, coupled to the A/D converter and comprising m interpolators for over-sampling the digital signal, wherein m is an over-sampling rate and m is not smaller than 2, the interpolator bank configured to generate a sample α ⁡ ( t ) = ∑ j = - m N ⁢ X i + j · sin ⁢ ⁢ c ⁡ ( t - j ) where t is a time at which the sample α(t) is generated, j denotes j-th interpolator among interpolators from 1 to (m−1), and X i+j , denotes a sample received from an equalizer at time i by j-th interpolator.