Patent ID: 6875689

Claim:
A method of creating sub-micron lines and patterns in semiconductor devices, comprising: providing a base layer, providing a first layer over said base layer; providing a second material layer on the first layer; patterning and etching the second material layer to create an opening having a first dimension, the opening exposing a surface of the first layer; providing a mask comprising first and second mask layers over the second material layer and the first layer, the first mask layer having a first surface covering the entire exposed surface of the first layer, the first mask layer having an opposite second surface having an opening with a dimension that is smaller than the first dimension of the opening in the second material layer, the second mask layer covering at least the opening of the first mask layer; etching said first layer using said mask, thereby creating sub-micron lines and patterns; and removing the second mask layer and the portion of the first mask layer underlying the second mask layer from said sub-micron lines and patterns.