Patent ID: 7170132

Claim:
A twin MONOS memory comprising: a deep N-well in a substrate; polysilicon word gates having polysilicon control gates on sidewalls of said word gates having an oxide layer therebetween and not having an oxide-nitride-oxide (ONO) layer therebetween and having an ONO layer underlying said control gates wherein said nitride portion of said ONO layer underlying said control gates provides memory storage; raised polysilicon diffusions between each two of said control gates and separated from said control gates by an oxide layer; word lines overlying and crossing said word gates; source and drain regions in said substrate underlying and directly contacting said raised diffusions; diffusion contacts through a dielectric layer overlying said gates to said raised diffusions at an end of every other raised diffusion alternating in a memory block; control gate contacts through a dielectric layer overlying said gates on an extension of said diffusion contacts or between diffusion contacts; and word gate contacts at ends of said word lines alternately to complete said Twin MONOS memory device.