Patent ID: 7065028

Claim:
A method for generating a clock signal coupled to a reference signal, comprising the steps: a) supplying an operating clock signal (f 0 ); b) supplying a first clock signal (f T2 ); c) supplying a sequence of sampling values of the reference signal at the frequency of the first clock signal (f T2 ); d) supplying a second clock signal (f T1 ); e) determining the phase deviation between the first clock signal (f T2 ) and the second clock signal (f T1 ); and f) converting the sampling values of the reference signal with the frequency of the first clock signal (f T2 ) to corresponding sampling values with the frequency of the second clock signal (f T1 ), the conversion being based on the phase deviation determined in step e), where the resulting sampling values of the reference signal are used in step d) as the target specification to generate the second clock signal (f T1 ) coupled with the reference signal.