Patent ID: 7859319

Claim:
A setup/hold time control circuit, comprising: a reference signal output unit buffers a signal that is input from a reference port and outputs the signal as a reference signal; and a plurality of comparative signal output units, each of which receives a corresponding input signal through a corresponding comparative port and synchronizes the corresponding input signal with the reference signal to output an internal signal, wherein each of the comparative signal output units includes: a buffer unit receiving the input signal input from the corresponding comparative port and outputting the comparative signal; a comparison latch unit comparing the comparative signal with the reference signal in order to output selectively enabled control signals; and a control unit synchronizing an output time point of the comparative signal with an output time point of the reference signal using the control signals, wherein comparison latch unit includes a comparing unit and a latch unit, the comparing unit compares the comparative signal with the reference signal and outputs a first detect signal and a second detect signal, if a test mode signal is enabled, and the latch unit receives the first and second detect signals and selectively enables and outputs the first and the second control signals.