Patent ID: 7504301

Claim:
A method for fabricating a stressed field effect transistor including a monocrystalline silicon substrate, the method comprising the steps of: depositing and patterning a layer of polycrystalline silicon overlying the silicon substrate to form a gate electrode, the gate electrode defining a channel region in the silicon substrate underlying the gate electrode; depositing a first layer of spacer forming material overlying the gate electrode; anisotropically etching the first layer to form a first sidewall spacer on the gate electrode; etching a first recess into the silicon substrate using the gate electrode and the sidewall spacer as an etch mask; epitaxially growing an undoped embedded silicon germanium layer in the first recess; depositing a second layer of spacer forming material overlying the gate electrode and the first sidewall spacer; anisotropically etching the second layer to form a second sidewall spacer on the first sidewall spacer; etching a second recess into the silicon substrate using the gate electrode and the second sidewall spacer as an etch mask; epitaxially growing an impurity doped embedded silicon germanium layer in the second recess; removing the first sidewall spacer and the second sidewall spacer; implanting conductivity determining ions into the undoped embedded silicon germanium layer and the impurity doped embedded silicon germanium layer to form source and drain extensions; and forming electrical contacts to the gate electrode and to the impurity doped embedded silicon germanium layer.