Patent ID: 8044442

Claim:
An apparatus, comprising: (a) a cantilever beam configured as a gate electrode; (b) a gate stack coupled to said cantilever beam having layers comprising: (i) a first and second channel layer; and (ii) a dielectric configured for electrically isolating said first and second channel layers from said cantilever beam; (c) a first and second pair of output electrodes, each pair of output electrodes comprising a source electrode and drain electrode; (d) wherein said gate stack is configured for mechanical translation of said first channel layer, under electrostatic force responsive to the application of a first gate voltage, into contact with said first pair of output electrodes, while said second channel layer is held separated from said second pair of output electrodes; (e) wherein said gate stack is configured for mechanical translation of said second channel layer, under electrostatic force responsive to the application of a second gate voltage, into contact with said second pair of output electrodes, while said first channel is held separated from said first pair of output electrodes; and (f) wherein said apparatus is configured for complementary switching in which either said first pair or said second pair of output electrodes is bridged by said first or said second channel layer; (g) wherein a stiction force arises in response to establishing contacts with said first and second channel layers, said stiction force exceeding the mechanical biasing force supplied by said means for biasing; and (h) wherein disconnection of said contact requires application of an opposing electrostatic force which overcomes said stiction force; (i) a first transistor coupled between a bit-line and said gate electrode in common with said first and second channel layers, with a gate of said first transistor coupled to a write word-line; and (j) a second transistor coupled between a bit-line and the interconnection of drain electrodes within said first and second pair of output electrodes, with a gate of said second transistor coupled to a read word-line; (k) wherein said transistors are configured for storing data from the bit-line in response to activating the write word line, or reading back data onto the bit-line in response to activating the read word line.