Patent ID: 7119582

Claim:
A phase detector operable with a first clock signal and a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising: at least one first flip flop operable to sample said first clock signal with a rising edge of said second clock signal, said at least one first flip flop thereby operating to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals; and at least one second flip flop operable to sample said first clock signal with a falling edge of said second clock signal, said at least one second flip flop operating to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals, wherein said first and second sampled clock signals are operable to be forwarded to validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.