Patent ID: 8497708

Claim:
A circuit, comprising: phase detector circuitry coupled to receive (a) a serial data bit stream clocked by a full rate clock signal with a full rate frequency, and (b) at least two fractional clock signals with a fractional rate frequency that is a binary integer fraction of the full rate frequency: Clk-I and Clk-Q which lags in phase Clk-I by substantially 90°; the phase detector circuitry including: sampling circuitry configured to sample the at least Clk-I and Clk-Q fractional clock signals with the serial data bit stream to generate at least first and second phase differences between a sampling bit edge of the serial data bit stream and respective clock edges of the at least Clk-I and Clk-Q fractional clock signals closest in time to the sampling bit edge; and phase difference circuitry responsive to the at least first and second phase differences to provide a phase difference signal corresponding to the difference in phase between the edges of the serial data bit stream and at least the Clk-I fractional clock signal, and thereby corresponding to the difference in phase between the full rate clock signal and at least the Clk-I fractional clock signal.