Patent ID: 7293141

Claim:
A cache memory system comprising: a cache memory circuit comprising: a first region having a first latency with respect to an access by a cache control circuit, the first latency being based at least in part on a distance between the first region and the cache control circuit; and at least a second region, the second region having a second latency with respect to an access by a cache control circuit, the second latency being based at least in part on a distance between the second region and the cache control circuit, the second latency being greater than the first latency; wherein the cache memory circuit is addressable to load and store lines of data allocated to the cache memory circuit, the lines of data comprising multiple addressable units of data; and wherein the cache memory circuit is organized to store a first addressable unit of an individual data line in the first region and a second addressable unit of the individual data line in the second region.