Patent ID: 7830170

Claim:
A logic circuit comprising: a plurality of logic gates each having an enabling input connected to an enabling signal input and a data output, each logic gate comprising: a first p-channel transistor being connected between a logic node and a supply potential and having a control terminal connected to the enabling signal input; a second n-channel transistor being connected between the logic node and a reference potential via an electrical path and having a control terminal connected to the enabling signal input; a data network serially connected into the electrical path and adapted to disable and enable the electrical path responsive to data at a data input; an inverter; a third p-channel transistor being connected between the supply potential and the logic node and having a control terminal connected to, via the inverter, the logic node; and a fourth p-channel transistor being serially connected along with the third p-channel transistor between the logic node and the supply potential and having a control terminal separately controllable relative to the control terminal of the third p-channel transistor; and a plurality of WiredOr circuitries each comprising a WiredOr input and a WiredOr output, wherein the WiredOr input of each of the WiredOr circuitries is connected to the data output of an associated logic gate of the plurality of logic gates.