Patent ID: 7203920

Claim:
A method for performing performance analysis of a semiconductor chip design, said semiconductor chip design including a plurality of embedded semiconductor devices and a plurality of embedded interconnects connecting said plurality of semiconductor devices, the method comprising: computing a temperature for at least one of said plurality of embedded semiconductor devices and said plurality of embedded interconnects, said computed temperature being computed in accordance with a three-dimensional full-chip thermal model that is adaptively partitioned in response to volumes of steep thermal gradients over the semiconductor chip design and that depicts computed temperatures for all semiconductor devices and all interconnects in said semiconductor chip design; calculating a resistance of said at least one of said plurality of semiconductor devices and said plurality of interconnects, in accordance with the computed temperature; providing at least said resistance to at least one performance analysis tool for assessment of at least one performance parameter of said semiconductor chip design in accordance with said resistance; receiving a first input from said at least one performance analysis tool as a result of said assessment, said first input comprising at least one of: modified capacitive load data and modified signal waveform data, where said modified capacitive load data and said modified signal waveform data relate to at least one of said plurality of embedded semiconductor devices and said plurality of embedded interconnects; calculating a modified temperature for at least one of said plurality of embedded semiconductor devices and said plurality of embedded interconnects in accordance with the first input; and determining a delay that corresponds to the first input.