Patent ID: 8786310

Claim:
A circuit, comprising: a plurality of programmable resources; a plurality of frames of configuration memory cells coupled to the programmable resources, wherein each frame includes a plurality of subsets of configuration memory cells, and each subset of configuration memory cells of the frame is coupled to one of the programmable resources; a plurality of partial configuration control memory cells, wherein each partial configuration control memory cell is coupled to a respective one of the subsets of configuration memory cells; and wherein responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, responsive to the partial configuration control memory cell associated with one subset of the subsets of configuration memory cells of the first frame being in a second state, and responsive to the partial configuration control memory cells associated with other subsets of configuration memory cells of the first frame being in a first state, the one subset of configuration memory cells of the first frame is configurable with data from the first partial bitstream, and the other subsets of configuration memory cells of the first frame are not configurable with data from the first partial bitstream.