Patent ID: 8427204

Claim:
A mixed mode input buffer for providing an output signal that is switched between a high level and a low level according to a signal comparison, comprising: an input transistor having at least a first terminal, a second terminal, and a gate terminal, and connected to an externally generated input at the gate terminal, for providing a first signal according to at least the externally generated input; a first reference transistor having at least a first terminal, a second terminal, and a gate terminal, and connected to an externally generated reference voltage signal at the gate terminal, where the second terminal of the first reference transistor is coupled to the second terminal of the input transistor, and the first reference transistor is for providing a second signal according to at least the externally generated reference voltage signal; and a second reference transistor having at least a first terminal, a second terminal, and a gate terminal, and connected to an internally generated reference voltage signal at the gate terminal and coupled in parallel to the first reference transistor, the second reference transistor for providing a third signal according to at least the internally generated reference voltage signal; wherein the first signal is compared with a combination of the second signal and the third signal, and when the first signal is greater than the combination of the second signal and the third signal, the output signal of the mixed mode input buffer is switched between the high level and the low level; and wherein sum of the widths of the first reference transistor and the second reference transistor is substantially equal to width of the input transistor.