Patent ID: 7882409

Claim:
An apparatus, comprising: an integrated circuit including circuitry compacting test response data from scan chains in the integrated circuit under test, the circuitry comprising: a first set of logic gates coupled to the scan chains; a plurality of output registers receiving the test response data from the scan chains via the first set of logic gates, said plurality of output registers including sequential elements and a second set of logic gates that process the test response data with stored data in said output registers, (i) wherein a scan chain is coupled to at least one sequential element within each register of said plurality of output registers, and (ii) wherein clusters of the scan chains are coupled to output registers of said plurality of output registers, such that the clusters are a subset of the scan chains including at least two scan chains, and such that for output register triplets including three output registers from the plurality of output registers, the output register triplets include at least a first pair of output register pairs and a second pair of output register pairs, the first pair and the second pair have at least one different output register pair, and wherein a first common cluster of scan chains is shared between the output register pairs of the first pair, and a second common cluster of scan chains is shared between the output register pairs of the second pair.