Patent ID: 8338968

Claim:
A semiconductor device comprising: (a) a semiconductor substrate of a substantially rectangular shape; (b) semiconductor elements formed over a main surface of said semiconductor substrate; (c) a first wiring layer formed over said semiconductor elements; (d) a first insulating film formed over said main surface of said semiconductor substrate to cover said first wiring layer; (e) a plurality of first pad electrodes and a plurality of second pad electrodes formed over said first insulating film; (f) a second wiring layer formed over said first insulating film, said second wiring layer being formed at a same level as said first and second pad electrodes; (g) a second insulating film to cover said first and second pad electrodes and said second wiring layer, said second insulating film having openings at upper sides of said first and second pad electrodes, respectively; and (h) a plurality of first bump electrodes and a plurality of second bump electrodes of substantially rectangular shape formed over said second insulating film, said first and second bump electrodes being electrically connected to corresponding ones of said first and second pad electrodes via said openings of said second insulating film, respectively, wherein said first pad electrodes and said first bump electrodes are for outputting signals and arranged in a zigzag pattern in plan view in a vicinity of a first long side of said semiconductor substrate, said first pad electrodes and said first bump electrodes being respectively arranged at predetermined intervals in a first direction which is along said first long side of said semiconductor substrate, wherein said second pad electrodes and said second bump electrodes are for inputting signals and arranged linearly in a vicinity of a second long side of said semiconductor substrate, said second pad electrodes and said second bump electrodes being respectively arranged at predetermined intervals in said first direction, wherein each of said first bump electrodes and each of said second bump electrodes are configured such that long sides thereof extend in a second direction which is along a first short side of said semiconductor substrate, and wherein said second wiring layer is disposed directly under at least said first bump electrodes or said second bump electrodes and extends along said first direction.