Patent ID: 7589738

Claim:
A cache system in digital data processing, and in particular, two-dimensional image processing at a required throughput with simultaneous coordinate transformation for video processing applications, in an arrangement consisting of: (a) an external memory where data to be accessed and processed are stored, said external memory having a read format; (b) at least one processor unit (PU 1 ) issuing control commands and generating control parameters and memory addresses of data to be processed in said external memory; (c) at least one processor unit (PU 2 ) to process the data; said system comprising a primary cache memory (PCM), a secondary cache memory (SCM), and a control logic, wherein: (i) the SCM is deeper and has a higher storage capacity than the PCM to efficiently access data from said external memory, and further has a plurality of banks and each bank has a plurality of storage lines wherein the sizes and numbers of and storage lines are optimized based on an input block data structure, and the required thoughput, and the number of secondary cache banks is designed as a function of the data throughput such that, for an m×n structure of data and a required number of clock cycles N c to read the data, the secondary cache has n/N c banks; (ii) the PCM is faster and wider and has a lower storage capacity than the SCM for fast data access in said PU 2 , and further has a plurality of banks and each bank has a plurality of storage lines, wherein the sizes and numbers of the banks and storage lines are optimized based on an input block data structure, the read format from the external memory, and the required throughput; (iii) the control logic contains control stages and control queues, providing pre-fetching and cache coherency upon receiving address sequences and control parameters from said PU 1 ; wherein, said system is adapted to achieve cache coherency and hide memory read latency via identifying all data blocks in said external memory and issuing only the data reads required to fetch the data for processing based on the topology and structure of the processing operation and pre-fetching said data blocks for processing by said PU 2 .