Patent ID: 8533394

Claim:
A computer system comprising: one or more processors which process program instructions; a memory device connected to said one or more processors; and program instructions residing in said memory device for testing a design of an instruction fetch unit (IFU) of a microprocessor by supplying a sequence of instruction addresses to an IFU model which represents the IFU design wherein the instruction addresses correspond to program instructions provided by a memory hierarchy which is external to the IFU model, fetching one or more of the program instructions according to the instruction address sequence from the external memory hierarchy to the IFU model, detecting that a current state of the IFU model is a predetermined state of interest, automatically modifying the instruction address sequence responsive to said detecting to force a selected address to be fetched next by the IFU mode wherein the selected address is specifically based on the predetermined state of interest, and fetching a program instruction corresponding to the selected address from the external memory hierarchy to the IFU model.