Patent ID: 7257725

Claim:
A memory system comprising: a memory controller; a clock generator, connected to said memory controller through a first clock signal line, for propagating a clock signal along said first clock signal line toward said memory controller; a plurality of second clock signal lines extended to be parallel and adjacent respectively to said first clock signal line, one end of said plurality of second clock signal lines being connected to terminating resistance respectively so that, when the clock signal is propagated along said first clock signal line, a crosstalk signal is propagated along said plurality of second clock signal lines in a direction opposite to the propagation direction of said clock signal; a plurality of memory modules connected to the other ends of said plurality of second clock signal lines; a data wired line which is provided for each of said plurality of memory modules and on which a data signal is transmitted between the corresponding memory module to which said data wired line is connected and said memory controller, said data wired line having substantially the same length as that of a portion of said first and second clock signal lines formed between said corresponding memory module and said memory controller; and a signal line which is provided for each of said plurality of memory modules and by which said corresponding memory module is connected to said memory controller, said signal line having substantially the same length as that of said data wired line; wherein said memory controller comprises (i) a location detection circuit which transmits, prior to performing write access to said plurality of memory modules, a location detection signal to the memory module to which write access is performed through said signal line and receives a reflected signal from said memory module, thereby measuring a physical quantity corresponding to a signal propagation time between said memory module and said memory controller; and (ii) an adjustment circuit which controls timing, at which the data signal is transmitted from said memory controller to said memory module through said data wired line, according to the physical quantity so as to eliminate a phase difference in propagation delay times caused by the length of said data wired line.