Patent ID: 7170807

Claim:
A semiconductor memory array comprising: a plurality of memory cells, including a first memory cell and a second memory cell, wherein each memory cell of the plurality of memory cells includes an associated transistor having a source region, a drain region, an electrically floating body region disposed therebetween, and a gate disposed over the electrically floating body region, and wherein each memory cell further includes a charge in the body region of the associated transistor which varies with time and a first data state representative of a first charge provided in the body region of the associated transistor, and a second data state representative of a second charge in the body region of the associated transistor, wherein the first charge is greater than the second charge; and circuitry, coupled to the plurality of memory cells, to simultaneously apply first electrical signals to the first memory cell, which is in the first data state, and the second memory cell, which is in the second data state, wherein, in response to the first electrical signals, the first memory cell is refreshed and the second memory cell maintains the second data state.