Patent ID: 7703061

Claim:
A method of modeling for use with an integrated circuit (IC) design, the method comprising: partitioning an edge of a shape in the IC design into a plurality of intervals using a computer; wherein the partitioning includes; generating a core Voronoi diagram for the shape wherein the core Voronoi diagram is generated based on the L∞ metric, the L∞ metric defining a distance between two points in the shape as the maximum of a horizontal distance and a vertical distance between two points and the assigning is based on a Euclidean metric; and partitioning the edge based on the core Voronoi diagram; assigning at least one dimension to each interval; and using the at least one dimension to evaluate a check rule wherein the check rule involves at least one of: a single edge, a pair of neighboring edges, and edges within more than one layer of the IC design.