Patent ID: 8638584

Claim:
An integrated circuit comprising: a front-end-of-the-line (FEOL) logic layer including active circuitry fabricated FEOL on a substrate; and arrays of memory elements, each memory element coupled between back-end-of-the-line (BEOL) array lines that electrically couple the memory elements with the active circuitry; wherein the memory elements are fabricated in at least one BEOL layer directly above the FEOL logic layer within a memory element region having a boundary defined by a periphery of the memory elements and positioned in a plane parallel to the substrate and the BEOL array lines; wherein the active circuitry includes a plurality of FEOL array line decoders disposed in the FEOL logic layer within a decoder region defined by a periphery of the plurality of the FEOL array line decoders located between the substrate and the memory elements; wherein a quantity of the plurality of FEOL array line decoders corresponds to a quantity of memory elements in the memory arrays of the memory elements configured to provide a throughput value; wherein the memory element region and the decoder region substantially overlap; and wherein the decoder region is less than or equal to the memory element region.