Patent ID: 7844762

Claim:
A device comprising: a parallel bus having a plurality of lanes; a parallel source to provide parallel groups of signals including groups of video signals representing pixels and groups of control signals to the parallel bus, wherein the parallel bus has a number of lanes that is fewer than a number of signals used to represent a pixel, the parallel source including: a signal divider to divide a video signal into a two or more subsets of signals, each subset including a number of bits that is no more than the number of bus lanes, the signal divider including a clock edge synchronizer to configurable to synchronize a plurality of subsets of signals in a clock cycle, the bits of each subset being synchronized to an edge of a clock signal, and a controller to direct routing of video signals and control signals onto the parallel bus; and a parallel sink to receive the parallel subsets of signals from the parallel bus, wherein the parallel sink includes: a signal extractor to reconstruct the groups of signals from the received subsets of signals, the signal extractor to separate at least a portion of the groups of signals into multiple channels, encoder and serializer circuits to encode and serialize the separated signals, the signal extractor being operable to re-time each group of signals such that the bits of each group of signals pass to the encoder and serializer circuits in the same clock cycle, and a controller to control the receipt and extraction of signals.