Patent ID: 8768679

Claim:
A computer-implemented method that simulates NPskew effects on a combination semiconductor device using slew perturbations, said combination semiconductor device comprising an NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor), said method comprising: performing a timing test comprising one of a pulse width test and an inactive test, by a computing device, by: evaluating, by said computing device, perturbed slew times for a combination semiconductor device comprising a relatively strong NFET/relatively weak PFET, producing a first timing test result; evaluating, by said computing device, perturbed slew times for a combination semiconductor device comprising a relatively weak NFET/relatively strong PFET, producing a second timing test result; and evaluating, by said computing device, unperturbed slew times for a combination semiconductor device having a balanced NFET/PFET, producing a third timing test result; determining, by said computing device, which evaluation of said perturbed and unperturbed slew times produces a timing test result having the smallest value from said first timing test result, said second timing test result and said third timing test result, for said combination semiconductor device; and outputting a NPskew effect adjusted timing test result based on said determining said timing test result having the smallest value.