Patent ID: 7185133

Claim:
A data processor comprising: a first bus; a first bus master module connected to said first bus; a first bus slave module connected to said first bus; a second bus; a second bus master module connected to said second bus; a second bus slave module connected to said second bus; a bus bridge circuit connecting said first and second buses; a first bus right arbitrating circuit connected to said first bus; and a second bus right arbitrating circuit connected to said second bus, wherein said bus bridge circuit has: a first transfer controller for obtaining bus right of the second bus in response to an access request directed from the first bus to the second bus and performing transfer control on information of the request; and a second transfer controller for obtaining bus right of the first bus in response to an access request directed from the second bus to the first bus and performing transfer control on information of the request, and wherein said second bus has first and second paths which can be split, the first path connecting said second bus slave module and said first transfer controller, and the second path connecting said second bus master module and said second transfer controller.