Patent ID: 7859050

Claim:
A memory array for a memory device, comprising: a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising: a storage device; and an access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the array further comprising: a plurality of recesses each formed in the semiconductor substrate that includes a pair of opposing side walls and a floor extending there between, the side walls including active regions of the access device having a selected conductivities, wherein the active regions are confined to the side walls; a conductive film structure that includes non-contiguous portions partially disposed on opposing side walls of the recess; a dielectric layer interposed between the active regions and the conductive film structure; and a plurality of trenches formed between adjacent ones of the recesses, extending in a direction substantially perpendicular to the pairs of opposing side walls of the plurality of recesses, and having a depth greater than a depth of the recesses; with a plurality of other trenches formed between adjacent ones of the recesses, substantially in parallel with the recesses, and having a depth greater than a depth of the recesses.