Patent ID: 7936588

Claim:
A memory apparatus, comprising: a variable resistive memory cell electrically between a read bit line and a read source line, the variable resistive memory cell is configured to switch between a high resistance state and a low resistance state, and a read transistor electrically in series with the variable resistive memory cell and the read transistor electrically coupled to a word line; a low resistance state reference variable resistive memory cell electrically between a low resistance state reference bit line and a low resistance state reference source line, and a low resistance state reference transistor electrically in series with the low resistance state reference variable resistive memory cell and the low resistance state reference transistor electrically coupled to the word line; a high resistance state reference variable resistive memory cell electrically between a high resistance state reference bit line and a high resistance state reference source line, and a high resistance state reference transistor electrically in series with the high resistance state reference variable resistive memory cell and the high resistance state reference transistor electrically coupled to the word line; and wherein the low resistance state reference variable resistive memory cell and the high resistance state reference variable resistive memory cell provide an average voltage reference value when a read current is applied through the low resistance state reference variable resistive memory cell and the high resistance state reference variable resistive memory cell.