Patent ID: 7243278

Claim:
An apparatus for carrying out test activities at input/output (IO) pins of an IC device under test (DUT) during a succession of test cycles, wherein the test activities include changing a state of a tri-state test signal supplied to any DUT IO pin and sampling a DUT output signal appearing at any DUT IO pin, the apparatus comprising: a pattern generator programmed to generate data before each test cycle encoded to specify all test activities to be carried out during the test cycle and to specify for each test activity a time during the test cycle at which the test activity is to be carried out and a DUT IO pin at which the test activity is to be carried out; and N programmable channels, where N is an integer greater than 1, each comprising a plurality of DUT interface circuits, each of which can be connected to a separate DUT IO pin for carrying out test activities at that DUT IO pin when signaled to do so, and hardware resources programmed by decoding instructions to decode the data from the pattern generator for each test cycle and initiate each specified test activity during the test cycle by signaling the DUT interface circuit that is specified for the test activity at the time specified for the test activity.