Patent ID: 6909663

Claim:
A memory array, comprising: at least a first column of memory cells and a second column of memory cells, wherein the memory cells of the first column and the second column have a common logic and are associated with at least a first memory port and a second memory port; first column bitlines in communication with the memory cells of the first column, the first column bitlines including bitlines in communication with the first memory port and the second memory port, wherein the bitlines associated with the fist memory port include a bitline exchange associated with a first selected row of memory cells and the bitlines associated with the second memory port include a bitline exchange associated with a second selected row of memory cells, wherein the first selected row and the second selected row are different; and second column bitlines in communication with the memory cells of the second column, the second column bitlines including bitlines in communication with the first memory port and the second memory port, wherein the bitlines associated with the first memory port include a bitline exchange associated with the first selected row of memory cells and the bitlines associated with the second memory port include a bitline exchange associated with the second selected row of memory cells.