Patent ID: 8178921

Claim:
A semiconductor device comprising: a semiconductor substrate having an active region having a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate and having a first portion having a first height and a second portion adjacent to the active region and having a second height less than the first height so as to form an aperture interposed between the first portion and the active region, the aperture exposing side surface of a portion of the gate forming zone of the active region such that the portion of the gate forming zone of the active region constitutes a fin pattern; a silicon epitaxial layer formed on an upper surface of the fin pattern and formed on a side surface of the fin pattern within the aperture so as to be between the gate forming zone of the active region and the isolation layer; and a gate formed to cover the fin pattern on the silicon epitaxial layer and formed within the aperture on side surfaces of the isolation layer and the silicon epitaxial layer so as to be interposed between the silicon epitaxial layer and the isolation layer.