Patent ID: 8581314

Claim:
A semiconductor device comprising: a substrate including at least one active region having an elliptical shape and a field region confining the active region; a gate electrode having a top surface lower than that of the substrate, the gate electrode having a linear shape whose major axis is not parallel to a major axis of the active region; a gate insulating layer interposed between the substrate and the gate electrode; first and second doped regions formed in the active region adjacent to the gate electrode; a first interlayer dielectric provided with a first contact hole exposing a top surface of the first doped region; a spacer disposed on an inner sidewall of the first contact hole; a first contact plug disposed in the first contact hole; a bit line electrically connected to the first contact plug, the bit line extending perpendicular to the major axis of the gate electrode; a second interlayer dielectric covering the bit line; a second contact plug electrically connected to the second doped region through the first and second interlayer dielectrics; and a capacitor electrically connected to the second contact plug, wherein a space defined by the spacer increases in width from a bottom side thereof to a top side thereof.