Patent ID: 7702885

Claim:
A method of operation for a digital controller system that interfaces with a memory, the method comprising: decoding one or more of a first plurality of commands through a hardware command decoding state machine that is coupled to a microcontroller, and performing the one or more of the first plurality of commands on the memory, wherein the microcontroller remains asleep during performance of the one or more of the first plurality of commands on the memory; in response to the hardware command decoding state machine decoding an extended command, waking the microcontroller to process an additional command other than a command among the first plurality of commands, the extended command being a command that notifies the microcontroller of the additional command to be processed; receiving an indication that the digital controller system is operating in a test mode; and using a combination of the extended command and a testmode pin associated with the digital controller system to notify the microcontroller of a test mode command to be processed during the test mode, wherein the testmode pin is not bonded out in a packaged part comprising the digital controller system.