Patent ID: 7692990

Claim:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a circuit for accessing a memory cell, the circuit comprising: a local bitline; a local sense amplifier having a plurality of transistors, said local bitline connecting the memory cell to said sense amplifier; a first global bitline connected to a first one of said plurality of transistors; a second global bitline connected to a second one of said plurality of transistors; and a secondary sense amplifier connected to said first and second global bitlines; wherein said local sense amplifier includes: a first transistor having a gate connected to said local bitline, a source connected to said first global bitline, and a drain connected to said second global bitline; a second transistor having a gate connected to said first global bitline, and a drain connected to said local bitline, and a source connected to first power supply; a third transistor having a gate connected to said second global bit line, a source connected to a second power supply, a drain connected to said local bitline.