Patent ID: 7888773

Claim:
A semiconductor device, comprising: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern, wherein the upper electrode comprises a first upper electrode layer pattern on the dielectric layer pattern and a second upper electrode layer pattern on the first upper electrode layer pattern, and wherein a portion of the first upper electrode layer pattern is on the second upper electrode layer pattern.