Patent ID: 8447583

Claim:
A computer implemented method for emulating execution of Guest processor instructions on a Host processor, the method comprising: creating a cell association wherein each of n Guest cells of Guest addressable memory are associated with a corresponding Host cell of n Host cells of Host addressable memory, each of said n Guest cells corresponding to a beginning portion of a Guest instruction to be emulated, wherein each Guest cell is x bytes of memory, wherein each Host cell is y bytes of memory; initializing each Host cell associated with a first Guest cell of each Guest instruction with an initialization routine; responsive to an emulator determining that a Guest instruction is to be emulated, the emulator causing the corresponding Host cell to be executed comprising: responsive to the corresponding Host cell having the initialization routine, executing the initialization routine of the corresponding Host cell, the execution causing the Host processor to patch the initialized Host cell with a semantic routine for executing the corresponding Guest instruction of the first Guest cell; and responsive to the corresponding Host cell having the semantic routine, executing the semantic routine to perform the function of the Guest instruction.