Patent ID: 7818523

Claim:
A memory device, comprising: multiple layers of non-volatile memory in contact with and fabricated directly on top of a substrate including active circuitry electrically coupled with the multiple layers of non-volatile memory, the multiple layers of non-volatile memory are in contact with one another, the multiple layers of non-volatile memory including an obfuscation layer of memory configured to conceal a portion of data stored in the multiple layers of non-volatile memory; a first set of ports formed in association with the multiple layers of non-volatile memory, the flint set of ports being configured to provide access to data stored in the multiple layers of non-volatile memory; a logic layer Included in the active circuitry; and a second set of ports formed in association with the logic layer, the second set of ports being coupled with the first set of the ports, wherein the multiple layers of non-volatile memory are formed upon the logic layer and wherein the logic layer comprises a memory storage controller, the memory storage controller including a memory storage interface coupled with the second set of ports, the memory storage interface being configured to access the multiple layers of non-volatile memory, and a device access determinator including determination logic and a device communication interface configured to receive a signal.