Patent ID: 8331148

Claim:
A semiconductor memory device comprising: a plurality of memory cells whose source and drain are connected in series; a first select transistor connected to a gate of a selected memory cell in the memory cells; second select transistors each connected to respective gates of non-selected memory cells in the memory cells, the second select transistors having gates commonly connected to a gate of the first select transistor; and a control circuit configured to control the first and second select transistors, wherein when writing data to the selected memory cell in the memory cells, the control circuit supplies a first voltage to the gates of the selected memory cell through the first select transistor, and supplies a second voltage to the gates of non-selected memory cells through the second select transistors, wherein the control circuit supplies a third voltage, wherein the third voltage is greater than the first voltage, and the first voltage is greater than the second voltage, to the gates of the first and second select transistors in order to supply the first and second voltages to the gates of the memory cells, and then the control circuit causes a voltage of the gates of the non-selected memory cells to change from the second voltage to a fourth voltage greater than the second voltage while the first voltage is kept.