Patent ID: 7557811

Claim:
An apparatus comprising: a first storage device; a second storage device; and a control circuit configured to generate addresses to read and write data in said first and said second storage devices, said control circuit presenting a first address signal and a second address signal to said first storage device, presenting a third address signal and a fourth address signal to said second storage device and presenting a plurality of fifth address signals to both said first and said second storage devices, wherein (i) said first address signal is presented as said third address signal and said second address signal is presented as said fourth address signal in a first mode, (ii) a complement of said first address signal is presented as said third address signal and said second address is presented as said fourth address signal in a second mode and (iii) said first address signal is presented as said third address signal and a complement of said second address signal is presented as said fourth address signal in a third mode.