Patent ID: 8122179

Claim:
A memory apparatus, comprising: a flash memory including a data region having a plurality of data blocks arranged in a contiguous sequence and a spare region having a plurality of spare blocks arranged in a contiguous sequence, wherein each of the data blocks is filled with data, and each of the spare blocks is empty; and a controller being configured to receive data corresponding to a first logical address which is initially linked to a physical address of a first data block of the data blocks, to select one of the spare blocks, when an erased count corresponding to the spare block is less than a predetermined value, to program data directly into the selected spare block, and to link a physical address of the selected spare block to the first logical address, whereby the data blocks and spare blocks of the flash memory are used in an even manner, and wherein the controller is further configured to erase the first data block and to recycle the first data block at a tail sequence in the spare region.