Patent ID: 7804351

Claim:
A mixer circuit for mixing signals, comprising: (a) an input terminal section comprising positive and negative input terminals for respectively receiving positive and negative input signals that constitute a differential input signal; (b) a local signal terminal section comprising positive and negative local signal terminals for receiving a differential local signal; (c) an output terminal section comprising positive and negative output terminals for outputting a differential output signal representing results of mixing the differential input signal and the differential local signal; (d) a first input section comprising: a first transistor whose gate is coupled to the positive input terminal, a second transistor whose gate is coupled to the negative local signal terminal, and a first load resistor connected to a first node at which drains of the first and second transistors are connected together; (e) a second input section comprising: a third transistor whose gate is coupled to the negative input terminal, a fourth transistor whose gate is coupled to the positive local signal terminal, and a second load resistor connected to a second node at which drains of the third and fourth transistors are connected together; (f) a third input section comprising: a fifth transistor whose gate is coupled to the positive input terminal, a sixth transistor whose gate is coupled to the positive local signal terminal, and a third load resistor connected to a third node at which drains of the fifth and sixth transistors are connected together; (g) a fourth input section comprising: a seventh transistor whose gate is coupled to the negative input terminal, an eighth transistor whose gate is coupled to the negative local signal terminal, and a fourth load resistor connected to a fourth node at which drains of the seventh and eighth transistors are connected together; (h) a positive output section comprising: a ninth transistor whose drain is connected to the positive output terminal, a tenth transistor whose drain is connected to the positive output terminal, and a fifth load resistor connected to a fifth node at which the drains of the ninth and tenth transistors are connected together, wherein the ninth transistor is driven by a first signal supplied from the first input section via the first node, and wherein the tenth transistor is driven by a second signal supplied from the second input section via the second node; and (i) a negative output section comprising: an eleventh transistor whose drain is connected to the negative output terminal, a twelfth transistor whose drain is connected to the negative output terminal, and a sixth load resistor connected to a sixth node at which the drains of the eleventh and twelfth transistors are connected together, wherein the eleventh transistor is driven by a third signal supplied from the third input section via the third node, and wherein the twelfth transistor is driven by a fourth signal supplied from the fourth input section via the fourth node.