Patent ID: 8823096

Claim:
A device comprising: a semiconductor region in a semiconductor chip; a gate dielectric layer over the semiconductor region; a gate electrode over the gate dielectric; a drain region at a top surface of the semiconductor region and adjacent to the gate electrode; a gate spacer on a sidewall of the gate electrode, wherein the gate spacer is on a drain side of the gate electrode; a dielectric layer over the gate electrode and the gate spacer; a conductive field plate over the dielectric layer, wherein the conductive field plate comprises a first portion on the drain side of the gate electrode, with the first portion extending farther away from the gate electrode than the gate spacer, and a second portion extending further away from the semiconductor region than the gate electrode; a deep metal via in the semiconductor region; and a source electrode underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.