Patent ID: 8330205

Claim:
A memory device, comprising: a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers; a second floating gate electrode electrically connected to the first floating gate electrode, the second floating gate electrode being on a non-planar portion of an upper surface of at least one of the adjacent isolation layers, and a lower surface of the second floating gate electrode having a first non-planar contour corresponding to a second non-planar contour of the non-planar portion of the upper surface of the one of adjacent isolation layers; a dielectric layer over the first and second floating gate electrodes; a control gate over the dielectric layer and the first and second floating gate electrodes; and an insulation layer adjacent the second floating gate electrode and on an uppermost surface of the adjacent isolation layers, the insulation layer protruding above the second floating gate electrode.