Patent ID: 7834463

Claim:
A stack package comprising: an edge-pad-type first semiconductor chip having first bonding pads along edges of the first semiconductor chip; a pattern die smaller than the first semiconductor chip and mounted onto the first semiconductor chip wherein the pattern die has a plurality of linear redistribution parts formed thereon, each linear redistribution part is aligned laterally across the pattern die so that opposing end parts of each redistribution part are positioned along respective opposing edges of the pattern die; an edge-pad-type second semiconductor chip smaller in size than the pattern die and mounted onto the pattern die such that the pattern die is sandwiched between the first and second semiconductor chips in which portions of the linear redistribution parts of the pattern die are covered over by the second semiconductor chip, wherein the second semiconductor chip having second bonding pads along edges of the second semiconductor chip; a first bonding wire electrically connecting together one of the first bonding pads to one opposing end of one of the linear redistribution parts; and a second bonding wire electrically connecting together the other opposing end of the one of the linear redistribution parts to one of the second bonding pads.