Patent ID: 7620072

Claim:
A received data reproducing device comprising: a measuring circuit for measure a signal strength of a received signal; an optimum phase detecting circuit for dividing a phase of a frequency particular to the received signal into N, where N is 2 or greater integer, to sample the received signal with a sampling signal multiplied in accordance with N, storing a sampled value for each of divided phases, outpouring optimum clock phase information for the received data derived from error information of each field, which is set in accordance with a communication standard of the received signal, and output error presence/absence information obtained in the event of detection of the error information; a frequency determining circuit for determining an optimum frequency of the sampling signal on the basis of the signal strength measured, the error presence/absence information output field by field and link information indicative of a station communicating with said received data reproducing device, and feed the optimum frequency information to said optimum phase detecting circuit; a buffer circuit for taking in the received signal and then adjusting the phase of the received signal with individual clock phase information corrected to read out the received signal; a sync word detector for executing processing for detecting synchronizing data included in input data, which are fed via a phase sampling/storing circuit for sampling the baseband signal with the sampling signal in accordance with a phase of said baseband signal while sequentially storing resulting sampled data, to thereby output synchronization detection information, checking, during the processing, every packet produced by dividing the input data for errors, and outputting, as the error presence/absence information, number-of-error information relating to synchronization and reflecting a result of checking; an error confirming circuit arranged in parallel to said sync word detector for comparing data relating to errors and generated when the data are present with, among the input data, data relating to errors to thereby confirm accurate receipt to output optimum phase information derived from error detection, and checking every packet for errors to output number-of-error information reflecting a result of checking as the error presence/absence signal; a phase counter for cyclically outputting a count, which is output in synchronism with the sampling signal, as optimum clock phase information; a phase information latch for latching the optimum clock phase information in response to a confirmation signal representative of accurate receipt and fed to said optimum phase detecting circuit field by field, and then outputting the optimum clock phase information; and a sampling signal generator supplied with N-time information from an outside of said optimum phase detecting circuit as a clock control signal for generating, in accordance with N indicated by the clock control signal, a sampling signal N times as high as the baseband signal in frequency.