Patent ID: 7751519

Claim:
A clock data recovery (CDR) circuit comprising: a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other; a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals, wherein the adjusted first and second clock signals have reduced phase error with respect to detected edges of incoming data; an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal; and a control circuit coupled to output MUX select inputs, wherein the control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges.