Patent ID: 7170907

Claim:
A receiver for aligning n data signals received over a parallel bus, each of the n data signals comprising a System Packet Interface Level 4 Phase 2 System Interface for Physical and Link Layer Devices (SPI-4.2) training pattern, wherein n is at least two, the receiver comprising: n analog delay lines each connected to delay a respective one of the n data signals in accordance with a corresponding analog delay signal, thereby providing a corresponding delayed data signal; a controller to execute n bit state machines each configured to receive a respective one of the delayed data signals and to provide a corresponding one of the analog delay signals based on the SPI-4.2 training pattern in the delayed data signal; n digital delay units each connected to delay a respective one of the delayed data signals by m bit times in accordance with a corresponding digital delay signal, thereby providing a corresponding aligned data signal, wherein m is greater than, or equal to, zero; and wherein the controller executes a main state machine configured to provide each of the corresponding digital delay signals based on the training pattern in the corresponding delayed data signal.