Patent ID: 7423312

Claim:
A non-volatile memory comprising at least one array of memory cells, wherein each of the memory cells comprising a source, a control gate, and a drain, and capable of storing at least one bit, said array of memory cells further comprising: a plurality of word lines coupled to control gates of said memory cells, said plurality of word lines arranged in rows in said array; a plurality of bit lines individually coupled to both said source and said drain of each of said memory cells, wherein said source and said drain are separated by a channel region and wherein said plurality of bit lines are arranged in columns in said array; at least one row of bit line contacts for providing electrical conductivity to said plurality of bit lines; a plurality of shallow trench isolation (STI) regions separating each of said plurality of bit lines along said at least one row of bit line contacts; a plurality of side-wall spacers separating neighboring word lines from said plurality of STI regions and a cobalt silicide (COSI) layer formed between bit line contacts in said at least one row of contacts and said plurality of bit lines.