Patent ID: 7512845

Claim:
A semiconductor memory device comprising: a memory cell array unit serially receiving data bits of a data pattern, storing the data bits in memory cells, and serially outputting the data bits as output data; an output shift register serially receiving the output data, storing first data bits, outputting N of the first data bits, and updating the first data bits by shifting the first data bits and storing one bit of the output data as one of the first data bits; a reference shift register serially receiving the data bits of the data pattern, storing second data bits, outputting N of the second data bits, updating the second data bits using a first update operation when stack or shift information indicates a first logic state, and updating the second data bits using a second update operation when the stack or shift information indicates a second logic state; and a comparison unit comparing the N first data bits with the N second data bits and outputting the stack or shift information, wherein the logic state of the stack or shift information corresponds to the result of comparing the N first data bits with the N second data bits, wherein the first update operation comprises storing one of the data bits received by the reference shift register as one of the second data bits without shifting the second data bits, and wherein the second update operation comprises shifting the second data bits and subsequently storing the one of the data bits received by the reference shift register as one of the second data bits.