Patent ID: 7992112

Claim:
A hardware verification programming description generation apparatus, comprising: a behavior synthesis section, for a circuit of hardware that operates in accordance with a multi-phase clock, for dividing the hardware into blocks corresponding to clock systems and performing a behavior synthesis on each of the divided blocks to produce behavior-synthesized data, based on a behavioral description, the behavioral description only describing a process behavior of the hardware but does not describe information regarding a structure of the hardware; and a clock precision model generation section for generating clock precision models using the behavior-synthesized data, the clock precision model suited to verifying the hardware at a cycle precision level; wherein the clock precision model generation section includes: a scheduling/state allocation section for scheduling nodes in a control data flow graph as the behavior-synthesized data according to respective clock frequencies of the blocks and allocating the nodes for respective states; and a cycle precision model generation section for generating behavior models as the clock precision models for each of the states, the behavior models suited to verifying the hardware at a cycle precision level using a result obtained from the scheduling/state allocation section.