Patent ID: 7880230

Claim:
A zero capacitor RAM comprising: an SOI substrate comprising a stacked structure of a silicon substrate, an embedded insulation film, and a silicon layer, wherein the silicon layer is patterned into line types to constitute active patterns; a first insulation layer formed between the active patterns; a plurality of gates formed on the active patterns and the first insulation layer to extend in a direction perpendicular to the active patterns; a source formed in the active pattern on one side of each gate; a drain formed in the active pattern on the other side of each gate by filling a metal layer; doped silicon epitaxial layers formed as ohmic contact layers between the drain and the active patterns; a contact plug formed between the gates on the source; an interlayer dielectric formed on the contact plug and the gates; and a bit line formed on the interlayer dielectric to extend in a direction perpendicular to the gates and come into contact with the drain.