Patent ID: 7033883

Claim:
A placement method for decoupling capacitors in an integrated circuit, comprising: creating a floor plan of the integrated circuit, the floor plan comprising the relative locations of a plurality of functional units; overlaying a power mesh on the floor plan, wherein the power mesh comprises a plurality power lines and divides the floor plan into a plurality of windows; placing a plurality of semiconductor cells into a portion of the windows; detecting whether there is a residual area comprising two adjacent windows without functional units and semiconductor cells arranged therein and having three parallel power lines of the plurality of power lines; and placing a MOS capacitor in the detected residual area, serving as a decoupling capacitor, wherein the MOS capacitor has a gate connected to the middle of the three power lines in the detected residual area, and a drain and a source respectively connected to the remaining two power lines of three power lines in the detected residual area.