Patent ID: 7953911

Claim:
An application specific integrated circuit, comprising: (N) read channels; an SRAM memory device, wherein said SRAM memory device is capable of communicating with each of said (N) read channels; a microprocessor interface, wherein said microprocessor interface is capable of reading said SRAM memory device, and wherein said microprocessor interface is capable of communicating with each of said (N) read channels, wherein (N) is greater than or equal to 1 and less than or equal to 8, wherein said microprocessor interface is interconnected with a data storage device controller; wherein each of said (N) read channels comprises: an analog to digital converter; an equalizer; a first communication link interconnecting said equalizer and said analog to digital converter, wherein said first communication link comprising a first test port; a second communication link interconnecting said first testport and said data cache; a third communication link interconnecting said data cache and said microprocessor interface; a fourth communication link interconnecting said microprocessor interface and said equalizer.