Patent ID: 7966533

Claim:
An apparatus comprising: a multiplexer; and logic that is operable to receive an input signal and a test mode input signal and that includes a test enabled flip-flop, wherein the test enabled flip-flop includes: a data input terminal; a clock input terminal that is operable to receive a clock signal; a test mode input terminal that is operable to receive the test mode input signal, wherein, when the test mode input signal is de-asserted, the test enabled flip-flop is operable to register and output data from the data input terminal upon a transition of the clock signal; and a test circuit that is operable to output test data when the test mode input signal is asserted, wherein the test circuit includes: an inverter chain; a first gated inverter circuit that is gated with the clock signal; a second gated inverter circuit that is gated with an inverse of the clock signal, wherein an output of the first gated inverter is applied to the second gated inverter circuit and to an input of the inverter chain; a third gated inverter circuit that is gated with test mode signal; and a fourth gated inverter circuit that is electrically coupled to the multiplexer and that is gated with the an inverse of the test mode signal, and wherein an output of the third gated inverter is electrically coupled to the output of the second gated inverter circuit and to the input of the fourth gated inverter circuit, and wherein the output of the fourth gated inverter is applied to an output of the inverter chain.