Patent ID: 6879183

Claim:
An integrated circuit logic device comprising: a plurality of super-regions disposed on the logic device in a two-dimensional array of intersecting rows and columns of such super-regions, each of said super-regions including a plurality of regions of logic and a region of memory, each of said logic regions having a plurality of inputs and a plurality of outputs, and said memory region also having a plurality of inputs and a plurality of outputs; and interconnection circuitry for connecting said outputs of said logic regions and said memory regions to said inputs of said logic regions and said memory regions, wherein for each of the super-regions, the interconnection circuitry comprises: a plurality of first interconnection conductors uniquely associated with the super-region, each of the first interconnection conductors that is associated with a super-region extending substantially continuously adjacent to all of the logic and memory regions in that super-region and being connected only to the logic and memory regions in that super-region.