Patent ID: 7636813

Claim:
A computer memory system comprising: a memory controller for generating memory access requests to read data from two or more memory subsystems, receiving and responding to unsolicited data transfers from the two or more memory subsystems, the memory controller including pre-fetch data cache for storing pre-fetch data in anticipation of future data references, thereby eliminating sending one or more of the memory access requests to one or more of the memory subsystems when requested data is available in the pre-fetch data cache; one or more memory busses connected to the memory controller; and the two or more memory subsystems remote from the memory controller and in communication with the memory controller via the memory busses, each of the memory subsystems including one or more memory devices and pre-fetch logic to initiate an unsolicited data transfer to the memory controller based on access pattern analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem from the memory controller, wherein the unsolicited data transfer includes a tag identifying the unsolicited data transfer as unsolicited, and the two or more memory subsystems include logic to modify the tag as a response in response to determining that a read operation has received which matches an address range of the unsolicited data transfer.