Patent ID: 6877060

Claim:
An apparatus comprising: an input circuit coupled to a first bus to transfer a delayed transaction (DT) data having a transaction identifier to one of N buffers, the input circuit being dynamically configured according to a bus frequency, N being a positive integer, the one of the N buffers being associated with the transaction identifier, the input circuit comprising a 1-to-N de-multiplexing circuit to transfer the DT data from the first bus to the one of the N buffers based on the transaction identifier; and an output circuit coupled to the buffers to transfer the DT data from the one of the N buffers to a second bus operating at the bus frequency, the output circuit being dynamically configured according to the bus frequency, the output circuit comprising a N-to-1 multiplexing circuit to transfer the DT data from the one of the N buffers to the second bus based on the transaction identifier; wherein the 1-to-N de-multiplexing circuit comprises: a 1-to-P de-multiplexer to transfer the DT data to one of P signal paths, P being a positive integers; and P 1-to-Q de-multiplexers coupled to the P signal paths, Q being equal to N/P, each of the 1-to-Q de-multiplexers being coupled to Q of the N buffers to transfer the DT data to one of the Q buffers based on the transaction identifier.