Patent ID: 7552287

Claim:
A cache memory control unit that controls a cache memory comprising: a request receiving section that receives a prefetch request and a demand fetch request issued from a primary cache; and a swap processing section that performs swap processing when the request receiving section receives a demand fetch request designating a memory address as that designated by a prefetch request already received by the request receiving section, so that a move-in buffer (MIB), which is ensured due to a cache miss of the prefetch request received for replying to the prefetch request, is used for a reply to the demand fetch request received subsequent to the prefetch request; wherein the swap processing section comprises: an MIB ensuring section that ensures the move-in buffer; an MIB swap determination section that determines whether the swap processing is to be performed or not; and an MIB swap section that rewrites tag information of the move-in buffer when the MIB swap determination section makes a determination that the swap processing is to be performed; wherein when a correct reply to the prefetch request has arrived during a swap determination period in which it is determined by the MIB swap determination section whether the swap processing is to be performed or not, the swap processing section issues, to the primary cache, prior notice indicating an arrival of a reply to the demand fetch request and sends the correct reply to the primary cache; and the swap determination period is a time period from a time at which the demand fetch request has been received by the request receiving section to a time before the swap processing has been started by the MIB swap section.