Patent ID: 7994545

Claim:
A semiconductor device, comprising: a substrate portion; a plurality of diffusion regions formed in the substrate portion to define source and drain regions of transistor devices; and a gate electrode layer including a number of linear-shaped conductive structures each defined to extend lengthwise over the substrate portion in only a single common direction, wherein portions of some of the linear-shaped conductive structures that extend over the plurality of diffusion regions form a plurality of gate electrode segments of corresponding transistor devices, and wherein the gate electrode layer over the substrate portion includes a number of linear-shaped conductive structures that do not extend over any diffusion region; local interconnect metal disposed on the substrate portion between the linear-shaped conductive structures of the gate electrode layer, the local interconnect metal configured to form connections to, from, or between the source and drain regions, or between selected source or drain regions and one or more of the linear-shaped conductive structures that form one or more gate electrode segments; wherein the local interconnect metal is disposed beneath an inter-metal dielectric material.