Patent ID: 7398449

Claim:
An error-correcting memory controller comprising: an address linear block code generator, receiving a write address corresponding to write data, for generating address check bits from the write address using a linear block code function; wherein the address check bits comprise B+Y bits, and the write address comprises at least 4×(B+Y) bits, wherein the linear block code function compresses the write address by at least 75%; wherein B and Y are whole numbers and B is at least 4 and Y is less than B; a check word formed by combining the write data and the address check bits; an error-correction code (ECC) generator, receiving check word, for generating ECC bits of a correction code capable of correcting an error in a sequence of B data bits, and also capable of detecting another error bit separate from the B data bits, and capable of detecting an error in the address check bits; a write interface to a memory for writing the ECC bits to the memory that stores the write data at a location determined by the write address; a read interface to the memory for reading the ECC bits as read ECC bits and for reading read data from a location determined by a read address; a second address linear block code generator, receiving the read address corresponding to the read data, for generating read address check bits from the read address using the linear block code function; a second check word formed by combining the read data and the read address check bits; a second ECC generator, receiving the second check word, for generating second ECC bits of the correction code; a comparator, receiving the read ECC bits from the read interface and receiving the second ECC bits from the second ECC generator, for signaling an error when the read ECC bits and the second ECC bits mis-match; and a data corrector, coupled to the comparator, for correcting up to B bits in a sequence of B bits of the read data to generate corrected data using the second ECC bits to locate errors in the read data when the error is signaled by the comparator, wherein the write data comprises 64 data bits and the ECC bits comprise 12 ECC bits; wherein the correction code is a (84,72) code, whereby data is corrected and address errors are signaled using ECC bits stored in the memory.