Patent ID: 6925619

Claim:
A method for estimating capacitances of conductors residing alone parallel arid lines on each of LMAX vertically stacked layers of an integrated circuit (IC), where LMAX is an integer greater than 1, based on data contained in a layout file describing each layer and indicating each conductor's dimensions and position along one of the grid lines on one of layers, the method comprising the steps of: a. for each value of L from 1 to LMAX, processing the layout file to generate a separate database DB(L) comprising for each G th grid line on layer L a separate table TB(L,G) comprising for each conductor residing along that grid line a separate entry containing data indicating dimensions of that conductor and its position along that arid line; and, b. for each value of L from 1 to LMAX, processing tables TB(L,G) for all gridlines G of that layer L to generate a data structure M 1 (L,j) for each layer J=L+1 through L+N for which J<LMAX mapping layer J into an array of first rectangular areas and indicating an amount of surface area of conductors on layer L residing under each of the first rectangular areas, where N is an integer greater than 0.