Patent ID: 7340668

Claim:
A memory device, comprising: an array of memory cells arranged in rows and columns; a syndrome memory storing error checking and correcting syndromes corresponding to respective subsets of bits of data stored in the array of memory cells, the number of bits in each subset of data bits stored in the array of memory cells being less than the number of data bits stored in each row of memory cell in the array; an address decoder receiving row addresses and column addresses, the address decoder activating a row of memory cells corresponding to each received row address and to select a memory cell in a column of memory cells corresponding to each received column address; a read data path to couple read data from selected memory cells in an activated row to a predetermined number of data bus terminals, the predetermined number of data bus terminals being less than the number of bits in each subset of data bits stored in the array; a write data path to couple write data from the predetermined number of data bus terminals to selected memory cells in an activated row; a first set of column steering logic coupled to the array of memory cells, the first set of column steering logic selecting each of the subsets of data bits read from a corresponding subset of columns of the array of memory cells and outputting the selected subset of read data bits; error checking and correcting logic coupled to receive the selected subset of read data bits from the first set of column steering logic and the corresponding error checking and correcting syndromes from the syndrome memory, the error checking and correcting logic generating an error checking and correcting syndrome in the memory device from the selected subset of read data bits and comparing the generated error checking and correcting syndrome to the error checking and correcting syndrome received from the syndrome memory, the error checking and correcting logic further receiving the data written to the memory cells in the array and generating and storing in the syndrome memory error checking and correcting syndromes corresponding to respective subsets of bits of data written to the memory cells in the array; and control logic to cause the write data to be coupled from the data bus terminals to the array of memory cells and to cause the read data to be coupled from the array of memory cells to the data bus terminals.