Patent ID: 8766681

Claim:
A circuit comprising: a chain of one or more cascading units, wherein each cascading unit receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams; a chain of one or more dividers coupled to said chain of one or more cascading units for providing one or more divided clock signals to said chain of one or more cascading units, wherein said one or more divided clock signals is based on a gated common clock signal; an asynchronous reset signal delivered to said chain of one or more dividers, and when asserted sets said chain of one or more dividers to a reset state, wherein said asynchronous reset signal propagates through said chain or one or more dividers from a downstream side; a clock source providing an ungated common clock signal; a clock gating circuit configured for generating said gated common clock signal based on said ungated common clock signal, and configured to hold said gated common clock signal while said asynchronous reset signal is asserted, wherein said clock gating circuit is configured to provide said gated common clock signal to said chain of one or more dividers when said asynchronous reset signal is de-asserted; a retiming circuit configured to receive said ungated common clock signal and said reset asynchronous reset signal, wherein said retiming circuit generates a retimed reset signal that is de-asserted such that the gated common clock signal starts up undistorted after being released from reset.