Patent ID: 7873777

Claim:
A flash memory system comprising: a plurality of channel units, each comprising at least two flash memory chips, a control unit which controls the at least two flash memory chips, and a buffer unit which stores data; and a host interface unit which transmits data separated into a plurality of contiguous pieces according to the number of the channel units and transmitted by a host to the buffer units of the channel units, wherein the control unit of each channel unit records the data stored in the buffer unit into the at least two flash memory chips according to an interleaving process independently with respect to each channel, and separated data included in each contiguous piece of to-be-recorded data is stored in the same channel unit, and wherein the control unit of each channel unit controls a setup operation with respect to one flash memory chip selected from the at least two flash memory chips in the same channel unit, and a programming operation with respect to the selected flash memory chip in conjunction with a setup operation with respect to a flash memory chip of the at least two flash memory chips other than the selected flash memory chip.