Patent ID: 8402342

Claim:
A method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data, a shift register, and a comparator, for making a cyclic redundancy check in conjunction with decoding of received data corresponding to a convolutionally encoded data record of bit length L, in which at least A bits of the data record represent content data and at least B bits of the data record represent check data, the method comprising: while performing a trellis search of the received data, storing decision bits representing results of the trellis search and ordering a first portion of the stored decision bits according to the results of the trellis search; over A clock cycles following completion of the trellis search, providing stored decision bits corresponding to the A content bits to the CRC module, starting with the first portion of the stored decision bits ordered according to the results of the trellis search and followed by a second portion of the stored decision bits not ordered according to the results of the trellis search, to calculate a CRC remainder for the A content bits of the data record, and providing a third portion of the stored decision bits corresponding to the B check bits of the data record to the shift register; over B clock cycles following the A clock cycles, outputting the B bits of check data from the shift register in bitwise alignment with the CRC remainder calculated by the CRC module, and comparing the calculated CRC remainder to the B bits of check data in the comparator; determining, using the comparison of the calculated CRC remainder and the B bits of check data, whether the A bits of content data are corrupt; if the A bits of content data are determined to be corrupt, preparing a command signal to request resending of the data record.