Patent ID: 6977436

Claim:
A semiconductor packaging device comprising: a carrier having at least a cavity thereon, said cavity configured for fitting a chip; said chip having a back surface, an active surface, and a sidewall connecting said back surface and said active surface, wherein said active surface has a plurality of first bonding pads; an adhesive affixing said back surface and said sidewall to said cavity; a first insulating layer coated on said active surface and said carrier and having a plurality of first conductive holes therein, wherein said first conductive holes correspond to first bonding pads; a multi-layer structure on said first insulating layer, said multi-layer structure having a plurality of conductive layout lines, a plurality of second conductive holes therein, a second insulating layer thereon, and a plurality of exposed ball pads in said second insulating layer, wherein said first conductive holes are electrically connected with said conductive layout lines, said second conductive holes, and said exposed ball pads; and a plurality of solder balls affixed to said exposed ball pads.