Patent ID: 7487479

Claim:
A method for enforcing design for manufacturability rules on a circuit layout, comprising: receiving, at a tool, a first set of design rules, to be applied to the circuit layout, which must be followed; receiving, at the tool, a second set of design rules, to be applied to the circuit layout, which may be followed; storing priority data that associates a priority with each of the second set of design rules; and the tool applying the first set of design rules and the second set of design rules to the circuit layout to generate a revised circuit layout which conforms to each of the first set of design rules and to as many design rules in the second set of design rules as possible, wherein applying comprises: applying all of the first set of design rules to the circuit layout before applying any of the second set of design rules to the circuit layout; applying the second set of design rules to the circuit layout in order of priority; and in response to determining that a particular design rule, in the second set of design rules, to be applied to the circuit layout conflicts with another design rule that was previously applied to the circuit layout, determining that the particular design rule should not be applied to the circuit layout.