Patent ID: 7923321

Claim:
A method of fabricating a semiconductor device comprising: providing a semiconductor substrate having a first region and a second region; forming a high-k dielectric layer over the semiconductor substrate; forming a silicon layer over the high-k dielectric layer; forming a hard mask layer over the silicon layer; patterning the hard mask layer, the silicon layer, and the high-k dielectric layer to form a first gate structure over the first region and a second gate structure over the second region; forming a contact etch stop layer (CESL) over the first and second gate structures; modifying a profile of the CESL; forming an inter-layer dielectric (ILD) over the modified CESL; performing a chemical mechanical polishing (CMP) to expose the silicon layer of the first and second gate structures, respectively; and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.