Patent ID: 7122426

Claim:
A method for fabricating a cell of a nonvolatile memory device comprising: forming a plurality of trenches in a semiconductor substrate that define a plurality of active regions while simultaneously forming a plurality of stacked patterns including an oxide layer pattern, a floating gate pattern, a dielectric layer pattern, a control gate pattern, and a hard mask pattern that are sequentially stacked on each active region; forming a plurality of device isolation layers that fill the plurality of trenches on the semiconductor substrate and a space between the stacked patterns; removing the hard mask pattern; and patterning the conductive layer, the control gate pattern, the dielectric pattern, the floating gate pattern, and the oxide layer pattern to form gate structures and word lines, the gate structures including a tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode, the word lines parallel to each other, structured to cross over the device isolation layers, and disposed in contact with the gate structure.