Patent ID: 6867450

Claim:
A semiconductor memory device including memory cells each having a trench capacitor and a fin-gate-type MOSFET that selects the trench capacitor, comprising: a pillar formed on a major surface of a semiconductor substrate; a device isolation region formed on the semiconductor substrate in a vicinity of a proximal portion of the pillar; a gate electrode functioning as a word line, the gate electrode being formed on a side wall and an upper surface of the pillar; a gate insulation film interposed between the pillar and the gate electrode; a first activation region formed in the pillar and connected to a bit line; a second activation region formed in the pillar and spaced apart from the first activation region such that the gate electrode is interposed between the second activation region and the first activation region; a first oxide film formed on a side wall of the gate electrode, which corresponds to an upper surface of the pillar; a trench formed in a vicinity of the second activation region in the pillar; a capacitor formed on a side wall portion of the trench; a second oxide film formed on the device isolation region at an upper part of the side wall of the pillar such that the second oxide film is located lower than the upper surface of the pillar; and a surface strap formed on the second oxide film at a position above the second activation region in the pillar, the surface strap electrically connecting the second activation region and one of electrodes of the capacitor, wherein insulation of the side wall of the gate electrode is effected by the first oxide film alone, insulation between the gate electrode and the surface strap is effected by the second oxide film alone, and contact between the surface strap and the second activation region is made at the upper surface and the side wall of the pillar.