Patent ID: 7472212

Claim:
A multi CPU system in which a plurality of CPUs are connected to a same system bus, comprising: a plurality of semaphore circuits each corresponding one-to-one to one of said plurality of CPUs, wherein each of said plurality of semaphore circuits comprises: a bus unit that determines an accessing type of access from the corresponding CPU; a stack that holds information on a predetermined priority level of the corresponding CPU; a semaphore register in which a value indicating whether or not the corresponding CPU has a semaphore to be written; and a semaphore controlling unit that is communicably connected to at least another semaphore controlling unit of the plurality of semaphore circuits and controls the semaphore of the corresponding CPU; wherein said semaphore controlling unit outputs a semaphore acquisition request to the at least another semaphore controlling unit and controls the semaphore of the corresponding CPU based on the information held by said stack, the presence or absence of the semaphore acquisition request from the at least another semaphore controlling unit, and the value written in said semaphore register, when said bus unit determines the accessing type as a write access to a resource on said system bus.