Patent ID: 7990756

Claim:
A semiconductor memory device comprising a plurality of memory cells configured to be integrated in the semiconductor memory device, wherein: each memory device includes a first inverter, a second inverter, a first transfer transistor, and a second transfer transistor, the first inverter having a first driver transistor and a first load transistor formed over a semiconductor substrate, the first inverter including a first memory node, the second inverter having a second driver transistor and a second load transistor formed over the semiconductor substrate, the second inverter including a second memory node, the first transfer transistor being connected to the first memory node, the second transfer transistor being connected to the second memory node, the memory cell being connected to a bit line via the first transfer transistor and being connected to a complementary bit line via the second transfer transistor; a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to a source/drain region of the first load transistor on an opposite side to the first memory node and a source/drain region of the second load transistor on an opposite side to the second memory node; at least a memory-node-side end of a gate insulating film of the first driver transistor, a memory-node-side end of a gate insulating film of the second driver transistor, a memory-node-side end of a gate insulating film of the first load transistor, and a memory-node-side end of a gate insulating film of the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part; and the gate insulating film of the first driver transistor, the gate insulating film of the second driver transistor, the gate insulating film of the first load transistor, and the gate insulating film of the second load transistor have a thickness larger than a thickness of a gate insulating film of the first transfer transistor and a gate insulating film of the second transfer transistor.