Patent ID: 7392274

Claim:
A digital circuit configured as an arithmetic pipeline, said circuit comprising: a flat four-input single precision floating point adder module, said module being controllable to add first, second, third and fourth single precision floating point numbers and to output a resulting single precision floating point number, said module comprising: means for predicting a largest number from exponent and mantissa portions of said floating point numbers, said predicting means outputting a plurality of shifting data calculated based on said largest number and said exponent portions; means for partially sorting said floating point numbers based on sign-bit and the exponent portions of said floating point numbers, said sorting means outputting sorted mantissas, sorted exponents, and sorted sign-bits; carry-in generation means for outputting carry-in data based on said sorted sign-bits and mantissas: addition logic receiving the carry-in data and said sorted mantissas and said plurality of shifting data, said addition logic calculating and outputting a normalized mantissa output and exponent modifier; and output logic receiving the normalized mantissa output, exponent modifier, and a largest exponent, said output logic outputting the resulting floating point number based on the normalized mantissa output, the exponent modifier, and the largest exponent.