Patent ID: 7360064

Claim:
A processor, comprising: a selection unit, having a first input to receive a thread conditions signal indicative of one or more execution stalls, the selection unit selecting a thread from a plurality of threads based on the thread conditions signal, further comprising: a high priority unit, having a first input coupled to the first input of the selection unit, the high priority unit selecting a thread associated with a high priority instruction from the plurality of threads, a low priority unit, having a first input coupled to the first input of the selection unit, the low priority unit selecting a thread with a low priority instruction from the plurality of threads, and a control mux, having a first input coupled to an output of the high priority unit and having a second input coupled to an output of the low priority unit, the control mux selecting between the high priority selection and the low priority selection; and a selection mux, having a first input coupled to an output of the selection unit to receive the thread selection signal and a second input to receive a plurality of decoded instructions, the selection mux outputting a decoded instruction from the plurality of instructions in response to the thread selection signal.