Patent ID: 8458411

Claim:
A distributed shared memory multiprocessor, comprising: a first processing element; a first memory, the first memory being a local memory of the first processing element; a second processing element connected to the first processing element via a bus; a second memory, the second memory being a local memory of the second processing element; a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory including the first memory and the second memory; and an arbiter which arbitrates between a first write access request from the first processing element to the virtual shared memory region and a second write access request from the second processing element to the virtual shared memory region, wherein the arbiter comprises a first processing element control unit and a second processing element control unit, wherein the first processing element control unit comprises a first access permission control unit, a first address buffer control unit, a first suspension evaluation unit, a first address buffer, and a first comparator, wherein the second processing element control unit comprises a second access permission control unit, a second address buffer control unit, a second suspension evaluation unit, a second address buffer, and a second comparator, wherein a first address of the first write access request is registered in the first address buffer and a second address of the second write access request is registered in the second address buffer, wherein the first address is output from the first address buffer to the second comparator and the second address is output from the second address buffer to the first comparator, wherein the second comparator compares the first address with the second address, judges whether the first and second addresses are the same, and outputs a second judging result to the first suspension evaluation unit, wherein the first suspension evaluation unit outputs a first suspension evaluation signal to the first access permission control unit in a case that the second judging result is not the same according to the first write access request, wherein the first access permission control unit outputs a access permission signal to the first processing element according to the first suspension evaluation signal, and wherein the first address buffer control unit outputs a first release signal which releases the first address from the first address buffer when the first processing element completes write accesses to the physical addresses of the first and second memory associated with the first address.