Patent ID: 7466177

Claim:
A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range, comprising: an input control stage, for receiving an input clock and a feedback signal, and changing the pulse-width ratio of the input clock according to the feedback signal so as to generate a modulating signal; a buffer module, for buffering and reversing the modulating signal, thereby generating an output clock and a complementary signal, wherein the phases of the output clock and the complementary signal are opposite to each other; a programmable charge pump, comprising: a first differential charge pump; a second differential charge pump; and a current source module, for adjusting the ratio of charge to discharge of the pair of differential charge pumps; wherein, the first and the second differential charge pumps are used to adjust the potentials of a first comparative signal and a second comparative signal based on the output clock, the complementary signal, and the ratio of charge to discharge; at least one 2-stage LPF, for filtering the first and the second comparative signals; and a transconductor, for comparing the first and the second comparative signals, thereby adjusting the feedback signal to be fed back the input control stage.