Patent ID: 7428014

Claim:
A device for parallel data processing, wherein the device has at least one matrix of processors arranged in rows and columns, first additional data ports located outside the matrix and second additional data ports located outside the matrix, wherein the rows are arranged in a stepwise fashion relative to one another, the columns are arranged in a stepwise fashion relative to one another, processors have a first processor data port which is connected with one of the first external data ports by means of a first at least straight connection, processors have a second processor data port which is connected with one of the second external data ports by means of a second at least essentially straight connection, wherein the second at least essentially straight connection is oriented at least essentially orthogonal to the first at least essentially straight connection, and processors have a first primary processor data port and a first secondary processor data port, wherein the first primary processor data port is formed by the first processor data port and the first primary processor data port of at least one of the processors is also connected with the first secondary processor data port of another processor via the first connection.