Patent ID: 7447847

Claim:
A memory device comprising: a memory array; base trim circuitry adapted to store base control parameter values common to at least mutually exclusive first and second portions of the memory array; a first reference trim circuit corresponding to the first portion of the memory array, the first reference trim circuit adapted to store one or more first reference control parameter values; a second reference trim circuit corresponding to the second portion of the memory array, the second reference trim circuit adapted to store one or more second reference control parameter values; and a state machine adapted to receive the base control parameter values from the base trim circuitry and the one or more first reference control parameters from the first reference trim circuit and adapted to correct the base control parameter values, using the one or more first reference control parameters, for application to the first portion of the memory array, the state machine adapted to receive the one or more second reference control parameters from the second reference trim circuit and adapted to correct the base control parameter values, using the one or more second reference control parameters, for application to the second portion of the memory array; wherein the base control parameter values corrected using the one or more first reference control parameters for application to the first portion of the memory array are the same as the base control parameter values corrected using the one or more second reference control parameters for application to the second portion of the memory array.