Patent ID: 7233510

Claim:
A circuit configuration for actuating at least a first (TOP) and a second (BOT) respective power semiconductor switches in a bridge circuit, said circuit configuration comprising: a primary-side section and at least one respective secondary side section for respective power semiconductor switches in said bridge topology; said primary-side section circuitry further comprising: at least a first means for signal processing and at least one level shifter means for potential-free activation of said at least one secondary side section; said at least one secondary side further comprising: at least a second means for signal processing; at least one driver stage means for said respective power semiconductor switch; error acquisition means for conveying and determining an error status from said at least one secondary side section to said primary-side section; said means for conveying and determining an error status further comprising: at least one diode disposed between said primary side section and said at least one secondary side section; said diode having a cathode-side terminal joining said secondary-side section and connected to a secondary-side circuit means for implementing an error status; and said diode having an anode-side terminal joining at least one of a means for filtering and a means for current acquisition on said primary side section.