Patent ID: 6841481

Claim:
In a dual damascene patterning process, an etching method which comprises: providing a semiconductor structure with functional elements formed in a substrate, a dielectric disposed on the substrate, a photoresist etching mask above the dielectric, and a polymer intermediate layer between the etching mask and the dielectric layer; etching the dielectric layer and the polymer intermediate layer for the dual damascene patterning with a CF 4 ARC open process with high selectivity with respect to the photoresist of the etching mask, said CF 4 ARC open process including: adjusting RF power between 550 and 650 watts, adjusting pressure between 80 and 120 mtorr, adjusting CF 4 flow between 35 and 45 sccm, adjusting CHF 3 flow between 17 and 23 sccm, adjusting Ar flow between 80 and 120 sccm, and adjusting O 2 flow between 5 and 7 sccm.