Patent ID: 8896348

Claim:
A device comprising: first and second power lines; first and second sense nodes; a first circuit unit comprising: first and second transistors complementary in conductivity type to each other and coupled to each other at the first sense node, and third and fourth transistors complementary in conductivity type to each other and coupled to each other at the second sense node, the first and second transistors receiving a first clock signal at control electrodes thereof, the third and fourth transistors receiving a second clock signal at control electrodes thereof, and the second clock signal being complementary in phase to the first clock signal, a second circuit unit coupled between the first power line and the first circuit unit, and configured to respond to a third clock signal; a third circuit unit coupled between the second power line and the first circuit unit, and configured to respond to a fourth clock signal that is complementary in phase to the third clock signal; and a fifth transistor coupled between the first and second sense nodes.