Patent ID: 7447069

Claim:
In memory system that includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, a method of operating the memory system with a host computer, comprising: configuring use of the memory cells within the individual sectors to provide at least distinct portions in which user data and a sector address are stored, in response to receiving a memory address from the host computer, addressing a corresponding sector and reading the sector address from the sector address portion thereof, if the read sector address is that of the addressed corresponding sector, sending data to the host computer that is read from the user data portion of the addressed corresponding sector, and if the read sector address is that of a sector other than the addressed corresponding sector, addressing the other sector and sending data to the host computer that is read from the user data portion of the other sector.