Patent ID: 8624302

Claim:
A semiconductor device comprising: a trench region disposed within a silicon substrate, the trench region including: an outer trench having an outer trench sidewall defining an upper portion and a bottom portion of the outer trench, the upper portion of the outer trench having a first width that is substantially constant, the outer trench sidewall including a pattern in the bottom portion of the outer trench, the pattern including: a first portion that decreases in width from the first width to a second width; a second portion of substantially the second width; a third portion that increases in width from the second width to a third width; a fourth portion that decreases in width from the third width to a fourth width; and an outer trench bottom surface that is substantially flat; an oxide layer disposed on the sidewall of the outer trench and the bottom portion of the outer trench such that the oxide layer forms an inner trench within the outer trench, the inner trench having an inner trench sidewall that is substantially vertical and an inner trench bottom surface that is substantially flat; and a floating coupled capacitor including a conductive material disposed within the inner trench.