Patent ID: 7915657

Claim:
A semiconductor integrated circuit comprising: a memory circuit section used for storing data; and a non-memory circuit section which is provided to serve as a section other than said memory circuit section and used for storing no data, wherein the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in said non-memory circuit section is lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in said memory circuit section, wherein said non-memory circuit section includes: a combinational logic circuit having an output logic value determined by a combination of input logic values of said combinational logic circuit; and a sequential logic circuit having an output logic value determined by changes exhibited by an input logic value of said sequential logic circuit as changes along the time axis, and the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in said combinational logic circuit is lower than the second-conduction-type impurity concentration of said second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in said memory circuit section and lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in said sequential logic circuit.