Patent ID: 7085161

Claim:
A method of operating a non-volatile memory having an array of memory cells connected in a NAND arrangement and organized into blocks of cells with storage elements that are erasable together as a unit and which individually store a plurality of pages of user data in individual memory cells with at least first, second, third and fourth threshold ranges, comprising: (a) storing data of the number of times the blocks have been cycled, the cycle data being stored within memory cells of a single one of the plurality of pages of respective ones of said one or more blocks to which the cycle data pertain, (b) an erase operation, including, addressing one or more of the blocks for erase, reading the cycle data from each of said one or more blocks and temporarily storing the read cycle data, erasing the memory cells within said one or more blocks, updating the read cycle data, and programming the updated read cycle data back into memory cells of the single one of the plurality of pages of respective ones of said one or more blocks by utilizing only two of the threshold ranges, thereby to leave other memory cells of the pages within the one or more blocks available for programming user data therein, and (c) thereafter programming user data into the other memory cells of pages of said one or more blocks by using at least said first, second, third and fourth threshold ranges.