Patent ID: 7400548

Claim:
A method for accessing a register file array in a data processing system comprising: receiving a start read address for reading data from a register file array; generating a first read word line and a second read word line for reading the data from the register file array, wherein the register file array has a plurality of entries, each entry having only two read ports, and wherein a first read port of each entry is associated with the first read word line and a second read port of each entry is associated with the second read word line; and reading the data from the register file array based on the start read address, the first read word line, and the second read word line to thereby generate data outputs from the register file array, wherein the data outputs from the register file array are used to generate an input to one or more of a plurality of output multiplexers, wherein the plurality of output multiplexers provide the data from entries of the register file array to an instruction decode unit of the data processing system, wherein the plurality of entries in the register file array are partitioned into four sub-arrays, wherein the output from a first read port of entries in a sub-array are combined together to generate a first sub-array output, wherein the output from a second read port of entries in the sub-array are combined together to generate a second sub-array output, wherein a first sub-array of the register file array provides a zeroth sub-array output (Rd 0 ) and a fourth sub-array output (Rd 4 ), a second sub-array of the register file array provides the first sub-array output (Rd 1 ) and a fifth sub-array output (Rd 5 ), a third sub-array of the register file array provides the second sub-array output (Rd 2 ) and a sixth sub-array output (Rd 6 ), and a fourth sub-array of the register file array provides a third sub-array output (Rd 3 ) and a seventh sub-array output (Rd 7 ), wherein Rd 0 , Rd 1 , Rd 2 and Rd 3 are provided as inputs to a first output multiplexer, Rd 1 , Rd 2 , Rd 3 and Rd 4 are provided as inputs to a second output multiplexer, Rd 2 , Rd 3 , Rd 4 and Rd 5 are provided as inputs to a third output multiplexer, R 3 , Rd 4 , Rd 5 and Rd 6 are provided as inputs to a fourth output multiplexer, and Rd 4 , Rd 5 , Rd 6 and Rd 7 are provided as inputs to a fifth output multiplexer, wherein each of the first, second, third, fourth, and fifth output multiplexers receive a select signal indicating which of the inputs provided to the multiplexers is to be output, and wherein the select signals provided to the multiplexers are determined based on the start read address.