Patent ID: 8127081

Claim:
A system for prefetching data, comprising: a link interface configured to receive a memory request; a memory device interface operable to transmit memory requests and to receive read data responsive to at least some of the transmitted memory requests; a storage device configured to store data; and a prefetch circuit coupled to the link interface, the memory device interface and the storage device, the prefetch circuit being configured to receive memory requests from the link interface and to receive at least some of the read data received by the memory device interface, the prefetch circuit operable to: detect a pattern from which addresses to the memory requests that are likely to be accessed are predicted based on the memory requests previously received by the link interface, based on the pattern, generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests, couple read memory requests to the memory device interface according to the prefetch suggestions, and cause at least some of the read data received by the memory device interface to be stored in the storage device, wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the storage device, the data read control circuit operable to determine from read memory requests received by the link interface if the data corresponding to the read memory requests are stored in the storage device, the data read control circuit further operable to transfer the data corresponding to the read memory requests from the storage device if the data corresponding to the read memory requests are stored in the storage device, wherein the prefetch circuit is operable to transfer the read memory requests received by the link interface to the memory device interface if the data corresponding to the read memory requests are not stored in the storage device.