Patent ID: 7719525

Claim:
An electronic device comprising: a first semiconductor integrated circuit; and a plurality of cascade-connected second semiconductor integrated circuits comprising an initial-stage second semiconductor integrated circuit for receiving differential signals comprising data from the first semiconductor integrated circuit and sequentially transferring CMOS signals comprising the data, between each of the second semiconductor integrated circuits, wherein each second semiconductor integrated circuit comprises: a receiver that receives either the differential signals or the CMOS signals in accordance with an interface mode select signal; a data inversion signal generation circuit that detects a number of changed bits of the data comprised by the received signals and generates a data inversion signal corresponding with the number of changed bits of the inversion only when each second semiconductor integrated circuit is set to receive the differential signals; a first data inversion circuit that subjects the CMOS signals to a first inversion in accordance with the data inversion signal; and a second data inversion circuit that subjects the CMOS signals thus subjected to the first inversion to a second inversion in accordance with the data inversion signal.