Patent ID: 7312489

Claim:
A DRAM cell comprising: a first interlayer insulating layer disposed over a semiconductor substrate; a second interlayer insulating layer disposed over the first interlayer insulating layer; parallel bit line patterns disposed on the second interlayer insulating layer, each bit line pattern having a bit line and a bit line capping layer pattern stacked thereon, a lowermost surface of each bit line contiguous with an uppermost surface of the underlying second interlayer insulating layer; bit line spacers covering side walls of the bit line patterns; buried holes penetrating regions of the second interlayer insulating layer between the parallel bit line patterns; and storage node contact plugs placed between the parallel bit line patterns and surrounded by the bit line spacers, the storage node contact plugs filling the buried holes and being disposed directly on the uppermost surface of the second interlayer insulating layer.