Patent ID: 7884422

Claim:
A semiconductor memory comprising: a plurality of cell units arranged in a row direction, each of the cell units comprising: a semiconductor region; a first buried insulating film provided on the semiconductor region; a second buried insulating film provided on the first buried insulating film, which has higher dielectric constant than the first buried insulating film; a semiconductor layer provided on the second buried insulating film; and a plurality of memory cell transistors arranged in a column direction, each of the memory cell transistors having a source region, a drain region and a channel region defined in the semiconductor layer, wherein each of the cell units further comprises a select gate transistor comprising: a second drain region defined in the semiconductor layer so as to be shared with the source region of the memory cell transistor positioned at an end of a unit arrangement of the cell unit in the column direction; a second channel region defined in the semiconductor layer so as to contact the second drain region; and a second source region defined in the semiconductor layer so as to contact the second channel region; wherein the first and second buried insulating films are provided directly under the unit arrangement and the second source and drain regions of the select gate transistor, selectively.