Patent ID: 7342985

Claim:
A method for generating a fixed angle delayed clock signal as compared to a reference clock signal while compensating for skew introduced by system clock delay, the method comprising the following: an act of passing a reference clock signal through a reference clock delay line comprising a plurality of reference clock delay elements; an act of adjusting a number of reference clock delay elements through which the reference clock signal passes in the reference clock delay line until the reference clock signal at an output terminal of the reference clock delay line and received at a feedback clock input of a phase detector and the reference clock signal received at a reference input terminal of the phase detector are approximately in phase; an act of calculating an initial number of fixed angle clock delay elements in a fixed angle clock delay line needed to generate a fixed angle delayed clock signal with respect to the reference clock signal, the calculation being based on the number of reference clock delay elements used at the time the reference clock signal at the reference input of the phase detector and the reference clock signal at the feedback clock input of the phase detector are approximately in phase; an act of receiving a clock signal from the fixed angle clock delay line; an act of passing the clock signal through a system clock mechanism that introduces the system clock delay; an act of calculating an adjustment number of fixed angle clock delay elements needed to account for the system clock delay using the clock signal received from the fixed angle clock delay line and the clock signal after having passed through the system clock mechanism; an act of calculating a final number of fixed angle clock delay elements needed to generate a fixed angle delayed clock signal that accounts for the system clock delay by adjusting the initial number of fixed angle clock delay elements by the adjustment number of fixed angle clock delay elements; an act of receiving the reference clock signal at an input terminal of the fixed angle clock delay line; and an act of passing the reference clock signal through the final number of fixed angle clock delay elements before allowing the reference clock signal to be output from the fixed angle clock delay line in the form of the fixed angle delayed clock signal that accounts for system clock delay.