Patent ID: 8546862

Claim:
A memory cell comprising a transistor, the transistor comprising: a substrate; a first source/drain region; a second source/drain region; a gate; and a gate insulating layer positioned between the substrate and the gate, wherein the gate insulating layer is in a direct contact with the substrate and comprises charge traps distributed over an entire volume of the gate insulating layer, and wherein the gate insulating layer comprises a non-stoichiometric compound and the charge traps comprise bulk traps located in a bulk of the gate insulating layer and interface traps located in closed proximity of an interface between the substrate and the gate insulating layer, and wherein the interface traps are located within a first distance from the interface and the bulk traps are located within a second distance from the first distance, and wherein the second distance exceeds the first distance, and wherein a density of the bulk traps is higher than that of the interface traps by 8-10 orders of magnitude.