Patent ID: 8395923

Claim:
A memory device, comprising: an array of bitcells, each bitcell having two elements including a single antifuse element for storing a bitcell state and a single access element for providing access to the antifuse element for bitcell programming and readout, wherein the antifuse element is an NMOS transistor configured with an N Well surrounding +N source and drain regions and its source and drain tied together; power select circuitry for biasing a gate line of the array to a first voltage level for bitcell programming and a second voltage level for bitcell readout, the gate line connected to at least one of the antifuse elements; and sense circuitry for sensing bitcell state during readout, and including a voltage divider operatively coupled to a transmission gate serially coupled to a skewed inverter, wherein during readout a voltage divided signal from the voltage divider is passed through the transmission gate to the skewed inverter and a high or low value is provided at the inverter output.