Patent ID: 7027447

Claim:
An interface circuit for communicating received data from a receive clock domain into a transmit clock domain, comprising: a buffer, comprising a plurality of entries, having an input coupled to receive data from the receive clock domain and having an output for presenting data into the transmit clock domain; and a plurality of valid logic circuits, each associated with a corresponding one of the plurality of entries of the buffer, each valid logic circuit comprising: a write valid latch for controlling the state of a valid line in the receive clock domain, the write valid latch having a set input coupled to receive a write request signal; a read valid latch for controlling the state of a valid line in the transmit clock domain, the read valid latch having a reset input coupled to receive a read request signal; reset logic for resetting the write valid latch responsive to the read request signal; and set logic for setting the read valid latch responsive to the write request signal.