Patent ID: 7380189

Claim:
An apparatus comprising: a plurality of scannable flip-flops resident on an integrated circuit (IC); a clock source internal to the IC generate a system clock signal for the IC; and a clock generation circuit coupled to the clock source and to the scannable flip-flops to clock the scannable flip-flops, the clock generation circuit also coupled to receive from an external test source a regular scan signal to activate a regular scan mode, at-speed scan signal to activate an at-speed scan mode, shift enable signal to identify a shift phase and a capture phase and a scan clock signal which is lower in frequency than the system clock signal, in which the clock generation circuit is operable to: (a) couple the system clock signal to clock the scannable flip-flops for operation of the scannable flip-flops to transfer data during a normal mode of operation for the IC; (b) couple the scan clock signal to clock the scannable flip-flops for both the shift phase and capture phase of the shift enable signal when the regular scan signal indicates that the IC is placed in the regular scan mode, wherein the scan clock signal shifts in a test vector to the scannable flip-flops, captures a response and then shifts out a resultant vector from the scannable flip-flops; and (c) couple the scan clock signal to clock the scannable flip-flops for only the shift phase of the shift enable signal when the at-speed scan signal indicates that the IC is placed in the at-speed scan mode, and couple at least two pulses of the system clock signal to the scannable flip-flops for the capture phase of the shift enable signal, wherein the scan clock signal shifts in a test vector to the scannable flip-flops and shifts out a resultant vector from the scannable flip-flops, but at least two pulses of the system clock signal is used to capture a response from the scannable flip-flops.