Patent ID: 7965097

Claim:
A circuit under test, comprising: a plurality of transistors under measurement which are provided in electrically parallel; a plurality of gate voltage control sections which are provided correspondingly to the plurality of transistors under measurement, for applying a predetermined gate voltage to gate terminals of the corresponding transistors under measurement; a plurality of voltage applying sections which are provided correspondingly to the plurality of transistors under measurement to apply voltages to source terminals and drain terminals of the corresponding transistors under measurement such that a voltage applied to gate insulating films of the transistors under measurement is controlled to be generally constant; integral capacitors which are provided correspondingly to the plurality of transistors under measurement to integrate gate leak currents output from the source terminals and the drain terminals of the corresponding transistors under measurement; a selecting section which selects the respective transistors under measurement sequentially; and an output section which sequentially outputs voltages of the integral capacitors corresponding to the transistors under measurement sequentially selected by the selecting section.