Patent ID: 7757060

Claim:
A method for reducing wake latency time, the method comprising: copying contents of a main random access memory (RAM) to a non-volatile random access memory (NVRAM) in response to a refresh of the contents of the RAM, wherein sizes of the RAM and NVRAM are substantially equal; setting a checkpointing error bit to indicate a presence of errors in copying the contents of the main RAM to the NVRAM; transitioning from a higher activity state to a sleep state in response to a sleep event, wherein the sleep event removes power provided to the RAM; restoring from the sleep state to the higher activity state in response to a resume event, wherein the resume event restores the power provided to the RAM; copying contents of the NVRAM to the RAM in response to restoring the power to the RAM and in response to the checkpointing error bit not indicating the presence of errors in copying the contents of the main RAM to the NVRAM, thereby reducing the wake latency time; and verifying that the checkpointing error bit is checkpointed before removing power to the main RAM.