Patent ID: 8266413

Claim:
A method, comprising: switching operation of a processor from a general execution mode to an advance execution mode in response to a first cache miss of an instruction during performance in the general execution mode, the first cache miss resulting in a first stall lasting for a first amount of time; during the advance execution mode, performing multiple speculative execution passes through several instructions subsequent to the instruction causing the first cache miss with the processor, and storing results from one or more of the speculative execution passes; during performance of a first one of the speculative execution passes, executing a subsequent one of the instructions that causes a second cache miss resulting in a second stall that lasts a second amount of time; performing a second one of the speculative execution passes to process the subsequent one of the instructions after the second amount of time has lapsed; applying a subsequent one of the results from the subsequent one of the instructions to perform one or more other instructions during the speculative execution passes before the first amount of time has lapsed; and returning to the general execution mode and applying the results to reduce execution time for the several instructions subsequent to the instruction causing the first cache miss.