Patent ID: 7538772

Claim:
In a graphics system including a main processor and a graphics processing system for generating graphics images on a display in cooperation with said main processor, and a main memory, said system including a plurality of resources requesting access to said main memory, a memory controller comprising: a plurality of buffer memories, each of said buffer memories being operatively coupled to one of said plurality of resources requesting access to said main memory for storing information indicative of a request for main memory access; a multiple resource buffer memory coupled to said plurality of buffer memories for storing requests for main memory access from each of said plurality of resources; and a control circuit for controlling the transfer of information from said plurality of buffer memories to said multiple resource buffer memory, wherein said control circuit is operable to control the transfer of information from said plurality of buffer memories to said multiple resource buffer memory to reduce the frequency of switching from main memory write operations to main memory read operations, wherein said plurality of buffer memories and said multiple resource buffer memory are write request queues, wherein a resource that is writing to main memory generates a flush signal for initiating flushing of that resource's write request queue, and wherein said memory controller further includes a flush acknowledge handshake signal generating circuit that generates a flush acknowledge handshake signal to thereby indicate to competing resources that data written to main memory is actually stored in main memory rather than in an associated resource's buffer.