Patent ID: 8049295

Claim:
A semiconductor structure comprising: a substrate; a first well region of a first conductivity type overlying the substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the substrate; a first cushion region between the first and the second well regions, wherein the cushion region is an overlap region of the first and the second well regions; a third well region of the first conductivity type overlying the substrate; a second cushion region between the second and the third well regions, wherein the second cushion region is an overlap region of the second and the third well regions; an insulation region extending from a top surface of the first well region into the first well region, wherein the first and the second cushion regions are horizontally spaced apart from the insulation region; a gate dielectric extending from directly over the first well region to directly over the second and the third well regions; a gate electrode on the gate dielectric; a gate spacer on a sidewall of the gate electrode; a drain region in the first well region and adjoining the insulation region; and a source region in the third well region and underlying an edge of the gate spacer.