Patent ID: 8728886

Claim:
A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising: forming a first dielectric layer over a semiconductor layer in the NVM region and the logic region; forming a charge storage layer over the first dielectric layer in the NVM region and the logic region; patterning the charge storage layer to form a dummy gate in the logic region; patterning the charge storage layer to form a charge storage structure in the NVM region; forming a second dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the second dielectric layer surrounds the charge storage structure in the NVM region and the dummy gate in the logic region; removing the second dielectric layer from the NVM region while protecting the second dielectric layer in the logic region; removing the dummy gate in the logic region which results in an opening in the logic region; forming a third dielectric layer over the semiconductor layer, the charge storage structure in the NVM region, and the second dielectric layer, within the opening in the logic region, and along sidewalls of the charge storage structure; and forming a gate layer over the third dielectric layer in the NVM region and within the opening in the logic region, wherein the gate layer forms a control gate layer in the NVM region that is over and along the sidewalls of the charge storage structure and wherein the gate layer within the opening in the logic region forms a logic gate.