Patent ID: 7271059

Claim:
A method of fabricating a semiconductor device, comprising: preparing a substrate including a first area where a logic transistor is to be formed and a second area where a non-volatile memory cell is to be formed; forming a non-volatile memory cell at the second area of the substrate, comprising forming a floating gate on the second area of the substrate, forming an integrate dielectric on the floating gate, forming a control gate on the intergate dielectric and which has a smaller surface area than each of the floating gate and the intergate dielectric such that an upper part of the intergate dielectric is exposed, and forming an insulation layer as an uppermost portion of the non-volatile memory cell and in contact with the upper part of the intergate dielectric exposed by the control gate to thereby enhance the charge retention capability of the memory cell; and forming a logic transistor at the first area of the substrate, comprising selectively forming a silicide layer at the first area.