Patent ID: 8533441

Claim:
A method for managing branch instructions, the method comprising: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instructions during a single execution cycle; receiving, at a controller during a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage of the multiple pipeline stages that provides an instruction fetch request to the controller stores a variable length group of instructions that comprises a branch instruction; updating status information indicative of an order of branch instructions stored in the multiple pipeline stages based on an executed branch instruction of an immediately preceding execution cycle, wherein the status information for each of the multiple branch instructions includes a bit set for each branch instruction that precedes that branch instruction; determining a first in order branch instruction based on the status information wherein the first in order branch instruction has zero bits set in the status information; and sending, from the controller, to a fetch unit a certain instruction fetch command that is responsive to the first in order branch instruction of the multiple instruction fetch requests from the multiple pipeline stages, wherein the controller will always send an instruction fetch command responsive to the first in order branch instruction of the multiple instruction fetch requests for a cycle during which the controller receives the multiple instruction fetch requests.