Patent ID: 6934924

Claim:
A method of producing a clean layout from a floor plan for a VLSI chip, comprising the steps of: (a) defining metal rules for horizontal and vertical treatment of a plurality of metal layers; (b) defining block level rules for power strips, allocation of pins, signal and bus spacing and width, insertion of diodes, defining a buffer size for outputs, and setting a rise/fall time limit; (c) defining memory rules for power rings and power refresh; (d) defining top level rules for the power strips and a grid, said signal and bus spacing and width, buffer insertion rules for size, spacing, vias and amount, a rise/fall time limit, routing of the channels above logic, above memories and above analog, and bumping; (e) defining clock rules for clock tree structure, spacing and width, skew/delay limitation, and buffer parameters including; and (f) defining rules for the IO's, including rules governing power, metal width, ESD connection, bumping placement and connections, and bond pad placement and connections.