Patent ID: 6957244

Claim:
A reduced-width low-error multiplier method, for use in a communication system for making proper compensation in accordance with values of a multiplier and a multiplicand, comprising the steps of: Determining whether the multiplicand X has a bit length of m and is denoted by X m−1 . . . X i . . . X 0 , and whether a multiplier Y has a bit length of n and is denoted by Y n−1 . . . Y j . . . Y 0 then; When the multiplicand X has a bit length of m and is denoted by X m−1 . . . X i . . . X 0 , and when the multiplier Y has a bit length of n and is denoted by Y n−1 . . . Y j . . . Y 0 , establishing the product term PD, as having (m+n−p) bits and denoted by PD m+n−1 . . . PD n . . . PD p where p is a bit length of a product term to be removed, I is the ith bit of a multiplicand X, and j is the jth bit of the multiplicator Y; determining the compensation signal β, according to the equation: β = ∑ i + j = p - 1 ⁢ ⁢ x i ⁢ y j = x p - 1 ⁢ y 0 + x p - 2 ⁢ y 1 + … + x 1 ⁢ y p - 2 + x 0 ⁢ y p - 1 where i+j=p−1 and i varies from 0 to p−1.