Patent ID: 8686771

Claim:
A digital phase-locked loop (DPLL) for establishing and maintaining a phase relationship between an output signal and an input signal, the DPLL comprising: a synchronizer configured to synchronize the input signal with the output signal to provide a first comparison signal; an accumulator configured to accumulate a difference between a desired division factor and a number of edges of the output signal that occur during a cycle of the first comparison signal to provide a coarse phase error; a multi-modulus divider (MMD) configured to reduce a frequency of the output signal, on average, by the desired division factor to provide a second comparison signal; a time-to-digital converter (TDC) configured to detect a fine phase error based on a difference in phase between the input signal and the first comparison signal if the DPLL is in a non-locked state or detect the fine phase error between the input signal and the second comparison signal if the DPLL is in a locked state; and a digitally controlled oscillator (DCO) configured to adjust the frequency of the output signal based on the fine phase error and, if the DPLL is in the non-locked state, the coarse phase error.