Patent ID: 8225071

Claim:
A virtual computer system comprising: a computer running a virtual machine monitor having a first address space and a virtual machine having a second address space; a first page table for mapping addresses from the first address space and a second page table for mapping addresses from the second address space; and a first routine executing in the same context in which the TLB Miss fault occurred and a second routine executing in a different context from the first routine, wherein the virtual computer system performs a method for responding to a TLB Miss fault resulting from an attempted memory access, the method comprising: the first routine determining an operating state in which the virtual computer system was operating when the TLB Miss fault occurred; the first routine receiving an address space identifier which indicates if the attempted memory access was to the first address space or the second address space; the first routine using the operating state and the address space identifier to determine if the attempted memory access is permitted; and if the attempted memory access is permitted, the first routine using the address space identifier to determine if the attempted memory access was to the first address space or the second address space, and, if the attempted memory access was to the first address space, the first routine attempting to find a translation for the attempted memory access in the first page table, or, if the attempted memory access was to the second address space, the first routine attempting to find a translation for the attempted memory access in the second page table, or if the attempted memory access is not permitted, causing a context switch to be performed to switch execution to the second routine for responding to the impermissible attempted memory access.