Patent ID: 7475306

Claim:
A scan test method of an integrated circuit including a combinational circuit, there being a flip-flop coupled to an input of the combination circuit and a flip-flop coupled to an output of the combination circuit, said flip-flops forming a scan chain, comprising: setting initial test values to the flip-flops forming the scan chain; performing a first capture operation whereby a first output of the combination circuit is captured by said flip-flop coupled to the output of the combination circuit; performing a feedback shift operation feeding said first output of the scan chain back to an input side of the scan chain for re-input during a shift operation in the scan chain; performing a second capture operation, whereby a second output of the combination circuit based on inputting said first output to said combination circuit is captured by said flip-flop coupled to the output of the combination circuit; and comparing said second output of the scan chain, output after performing the second capture operation, with an expected value.