Patent ID: 6981009

Claim:
An apparatus for computing a logarithm to a base p of a floating-point number X wherein the floating-point number X is represented in the format of (−1) Sx ·2 Ex ·M x , where M x =(1+f x )=(1+A x ·2 −K )+(B x ·2 −N ), where S x is a sign, E x is an exponent, M x is a mantissa, 1≦M x <2, f x is a N-bit fraction, A x is a value of the most significant K bits of f x , B x is a value of the least significant (N−K) bits of f x , 0≦K<N, and p, K, N are natural numbers, the apparatus comprising: a first multiplier for multiplying a number whose value is log p 2 and the exponent E x and outputting a multiplying result; a logarithmic table for receiving the value A x and checking the logarithmic table to output a result; a first adder connected to the first multiplier and the logarithmic table for adding the multiplying result and the result to output an adding result; a divider for receiving the value B x and an adding number whose value is (2 K +A x ) and dividing the value B x by the adding number to output a dividing result R d ; a Taylor-Series approximation circuit connected to the divider for receiving the dividing result R d , finding a value of ln(1+R d ) and outputting the value of ln(1+R d ); a second multiplier for multiplying a number whose value is 1/ln(p) and the value of ln(1+R d ) to output a second multiplying result; and a second adder connected to the first adder and the second multiplier for adding the adding result and the second multiplying result to output the logarithm Y.