Patent ID: 8558278

Claim:
A semiconductor device formed in a substrate comprising: an active region; a gate electrode overlying the active region; a source region and a drain region formed on opposite sides of the gate electrode, the source region and the drain region being substantially aligned with the electrode; and a strain-induced layer substantially conformally over the gate electrode and the active region; wherein a first shortest distance between a first gate edge of the gate electrode and a first outermost edge of the strain-induced layer along a direction parallel to a current flow between the source region and the drain region in a plan view is greater than 0.4 um, wherein the strain-induced layer extends a shorter distance from the first gate edge than the active region in the direction parallel to the current flow; wherein a second shortest distance between a first edge of the active region and a second outermost edge of the strain-induced layer along a direction perpendicular to the current flow between the source region and the drain region in a plan view is between about 60 nm to about 400 nm.