Patent ID: 6980552

Claim:
An apparatus for switching packets, each packet having a header portion, an optional corresponding tail portion, and a class of service indicator, the apparatus comprising: a pipelined switch including: a plurality of packet header buffers (PHBs); a plurality of PHB pointers, each of the plurality of PHB pointers pointing to a PHB; and a plurality of pipeline stage circuits connected in a sequence and comprising at least a first stage circuit and a last stage circuit, wherein: each of the plurality of pipeline stage circuits begins an operation substantially simultaneously with each other of the plurality of pipeline stage circuits; each of the plurality of pipeline stage circuits passes data to a next stage circuit; at least one of the plurality of pipeline stage circuits is operable to access a content addressable memory; the first stage circuit reads the header portion and stores the header portion in at least one of the plurality of PHBs using at least one of the plurality of PHB pointers; and said last stage circuit outputs a modified header portion.