Patent ID: 7176125

Claim:
An integrated circuit comprising: a first p-channel pull-up transistor including a drain coupled to a high voltage supply node, a source coupled to a first storage node, and a gate coupled to a second storage node; a first n-channel pull-down transistor including a drain coupled to a low voltage supply node, a source coupled to the first storage node, and a gate coupled to the second storage node; a second p-channel pull-up transistor including a drain coupled to the high voltage supply node, a source coupled to the second storage node, and a gate coupled to the first storage node; a second n-channel pull-down transistor including a drain coupled to the low voltage supply node, a source coupled to the second storage node, and a gate coupled to the first storage node; a first dielectric layer formed over the first pull-up transistor, the first pull-down transistor, the second pull-up transistor and the second pull-down transistor; a first local interconnect electrically coupling the source of the first pull-up transistor, the source of the first pull-down transistor, the gate of the second pull-up transistor and the gate of the second pull-down transistor, the first local interconnect formed within and substantially co-planar with the first dielectric layer; a second local interconnect electrically coupling the source of the second pull-up transistor, the source of the second pull-down transistor, the gate of the first pull-up transistor and the gate of the first pull-down transistor, the second local interconnect formed within and substantially co-planar with the first dielectric layer; a second dielectric layer formed over the first dielectric layer, the first local interconnect and the second local interconnect; a first metal region formed over the second dielectric layer, the first metal region being held a voltage level of the high voltage supply node; a first contact plug extending through the first dielectric layer and the second dielectric layer and coupled between the drain of the first pull-up transistor and the first metal region; a second metal region formed over the second dielectric layer, the second metal region being held the voltage level of the high voltage supply node; and a second contact plug extending through the first dielectric layer and the second dielectric layer and coupled between the drain of the second pull-up transistor and the second metal region.