Patent ID: 7551488

Claim:
A semiconductor nonvolatile memory comprising: a memory array in which a plurality of first nonvolatile memory cells are arranged; a plurality of memory areas which are arranged in the memory array and have a plurality of second nonvolatile memory cells in which the same predetermined information is stored; a sequence circuit which generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on; a write-read unit which writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal; a latch circuit which latches the predetermined information which is read by the write-read unit, based on the latch selection signal; and a selection-drive unit which selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells, wherein the plurality of second nonvolatile memory cells respectively store logical information values of both 0 and 1 as the predetermined information, and the sequence circuit comprises a determination unit, wherein the determination unit carries out repeated cycles of reading the plurality of second nonvolatile memory cells through the write-read unit in a read operation when the power is turned on, determines whether or not all of the read logical values are matched with the logical information values, and causes the write-read unit to read the predetermined information when all of the read logical values are matched with the logical information values.