Patent ID: 7816271

Claim:
A method for fabricating a semiconductor device, comprising: forming a DSL (dual stress liner) structure on an active surface of a semiconductor substrate having first and second device regions, wherein the DSL structure comprises first and second stress liner layers formed over the first and second device regions, respectively, the DSL structure comprising an overlapped region in which a portion of the second stress liner layer overlaps a portion of the first stress liner layer at an interface between the first and second stress liner layers, and wherein the DSL structure comprise a non-overlapped region in which portions of the first and second stress liner layers are not overlapped; forming an insulating layer over the DSL structure; forming a pattern of partial via holes in the insulating layer down to the DSL structure, the pattern of partial via holes including partial via holes that extend to the first or second stress liner layers in the non-overlapped region of the DSL structure and partial via holes that extend to the second stress liner layer in the overlapped region of the DSL structure; selectively etching portions of the second stress liner layer exposed through the partial via holes in the overlapped region of the DSL structure to extend the partial via holes in the overlapped region down to the underlying first stress liner; and concurrently etching portions of the first and second stress liner layers exposed through the partial via holes in the overlapped and non-overlapped regions of the DSL structure to form via contact holes that extend to underlying via contact regions; wherein selectively etching portions of the second stress liner layer exposed through the partial via holes in the overlapped region of the DSL structure comprises: depositing sacrificial material to cover portions of the first or second stress liner layers exposed at the bottom of the partial via holes in the non-overlapped region of the DSL structure; and anisotropically etching the portions of the second stress liner layer exposed through the partial via holes in the overlapped region of the DSL structure using an etch chemistry in which the exposed portions of the second stress liner layer at the bottom of the partial via holes in the overlapped region is etched selective to the sacrificial material in the partial via holes in the non-overlapped region.