Patent ID: 8089124

Claim:
A method comprising: providing a first conductivity-type semiconductor substrate having an active area and a field area; and then forming a second conductivity-type deep well on the first conductivity-type semiconductor substrate; and then forming a second conductivity-type adjusting layer located in the second conductivity-type deep well on the first conductivity-type semiconductor substrate; and then forming a first conductivity-type body in the second conductivity-type deep well; and then forming an insulating layer on the first conductivity-type semiconductor substrate in the active area and the field area; and then forming a gate area on the first conductivity-type semiconductor substrate in the active area; and then forming a second conductivity-type source area in the first conductivity-type body; and then forming a second conductivity-type drain area in the second conductivity-type deep well, wherein forming the second conductivity-type deep well comprises: simultaneously forming a deep well cutout area by coating the first conductivity-type semiconductor substrate with a mask when performing the ion implantation for forming the second conductivity-type deep well, wherein the second conductivity-type adjusting layer is formed on both the deep well cutout area and the second conductivity-type deep well, wherein a thickness of a second conductivity-type epitaxial layer is increased to have a thickness of between approximately 7.5 to 8.0 μm and a width of the deep well cutout area is widened to have a width of between approximately 3 to 5 μm so as to raise a breakdown voltage and the second conductivity-type adjusting layer is added so as to lower an on-resistance of an LDMOS device.