Patent ID: 8265219

Claim:
A method comprising: receiving a phase locked loop (PLL) input signal; receiving a PLL feedback signal, wherein said PLL feedback signal is selected from the group consisting of substantially a voltage controlled oscillator (VCO) output, and substantially said VCO output divided by N wherein N is an integer; generating a comparison signal based on said received PLL input signal and said received PLL feedback signal; generating a first control signal based on said comparison signal; generating a second control signal based upon a prespecified value programmed into a register, wherein said prespecified value is selected from the group consisting of a substantially static value, a value determined at time of manufacture, a value loaded at power up, a value loaded at reset, a value loaded at a frequency change, a value loaded from a nonvolatile memory, a value loaded by a serial control chain, and a value loaded by a parallel control chain; receiving a selection signal; selecting either said first control signal or said second control signal based upon said received selection signal; controlling said VCO (voltage controlled oscillator) by controlling three or more multiplexers based upon said selected control signal, wherein said VCO generates a VCO output, and wherein said three or more multiplexers control how many delay elements are in said VCO.