Patent ID: 8901537

Claim:
A transistor device, comprising: a substrate having a channel region; a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode; source and drain regions formed in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm −3 ; and a buffer between the substrate and the boron doped germanium layer; wherein the buffer has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .