Patent ID: 7143379

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; an integrated circuit design residing in the memory, the integrated circuit design including a plurality of logic blocks; a static timing tool residing in the memory and executed by the at least one processor, the static timing tool performing analysis that results in a plurality of slack computations; a timing analysis mechanism residing in the memory and executed by the at least one processor, the timing analysis mechanism including a dummy edge mechanism that creates a dummy clock test edge for a selected logic block that has a clock test signal and a data launch signal that are on opposite edges in a manner that results in the dummy clock test edge and the data launch signal being on the same edge, the static timing tool automatically identifying in the integrated circuit design at least one common logic block through which the clock test signal and the data launch signal both pass before arriving at the selected logic block, the timing analysis mechanism automatically improving at least one of the plurality of slack computations due to the at least one common logic block.