Patent ID: 7047507

Claim:
A method for determining wire capacitance for a VLSI circuit design, comprising the steps of: determining hierarchical blocks of a portion of the design; storing, for a plurality of the blocks, indicia of a most accurate one of a plurality of wire capacitance data sources; generating a wire capacitance database with an entry for each net, in at least a plurality of the blocks, using information stored in at least one of the wire capacitance data sources; generating a hierarchical connectivity model for the design using a single type of connectivity data for each of the blocks; wherein said single type of data is selected from either a layout or a schematic diagram; and using the hierarchical connectivity model and said wire capacitance database to determine a cumulative wire capacitance value for each high level signal name (HLSN) in each of the blocks in a portion of the design to be analyzed.