Patent ID: 8183105

Claim:
A method for forming an integrated circuit device comprising: generating an integrated circuit device design that includes a dual stress liner NMOS cell, a dual stress liner PMOS cell, a reduced-stress dual stress liner NMOS cell and a reduced-stress dual stress liner PMOS cell; and fabricating an integrated circuit device using the integrated circuit device design so as to form an integrated circuit device having a dual stress liner NMOS device that includes a tensile stress layer that overlies a first NMOS gate film stack, a dual stress liner PMOS device that includes a compressive stress layer that overlies a first PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a first stress reduction layer that extends between the tensile stress layer and a second NMOS gate film stack, and a reduced-stress dual stress liner PMOS device that includes a second PMOS gate film stack, the first stress reduction layer extending between the compressive stress layer and the second PMOS gate film stack.