Patent ID: 7733725

Claim:
A method of driving a 1-transistor DRAM including an NMOS being on top of a SOI layer, the NMOS having a parasitic bipolar transistor component, the method including: precharging, during a first hold period, a source line and a bit line of the NMOS of the 1-transistor DRAM at a precharge voltage while deactivating a word line of the NMOS transistor at a ground voltage to maintain an accumulation of charge carriers within a floating channel region underneath a gate of the NMOS transistor, wherein the accumulation of charge carriers corresponding to data in a binary logic state; shifting, during a composite operation period, the source line voltage and the bit line voltage to the ground voltage while shifting the word line of the NMOS transistor to a VDD voltage, the shifting step operates on the NMOS transistor and the parasitic bipolar transistor component of the NMOS transistor to activate the word line of the NMOS transistor, wherein the composite operation period being after the first hold period; deactivating, during a bipolar transistor operation period, the word line of the NMOS transistor to the ground voltage while maintaining the source line and the bit line at the ground voltage, the deactivating step operates only on the parasitic bipolar transistor component, wherein the bipolar transistor operation period being after the composite operation period; and precharging, during a second hold period, the source line and the bit line of the NMOS transistor to the precharge voltage while maintaining the word line to the ground voltage, wherein the second hold period performed after the bipolar transistor operation period to hold data at a “0” binary logic state.