Patent ID: 7501689

Claim:
A standard cell which is used for providing a desired logical function with a semiconductor integrated circuit chip, the standard cell being placement information of a layout pattern in which an optimum arrangement of a basic logical circuit is designed within a predetermined area by an arrangement of transistor elements and an arrangement of inner metal wires, and has a power layer disposed at an upper-layer in the inner metal wires, and in which an upper-layer metal power standard cell comprises a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer, wherein the basic power metal layer, the transistor element layer and the inner wire layer constitute the standard cell, wherein the transistor element layer and the inner wire layer form an underlayer in which the transistor element layer and the inner wire layer are formed as an optimized standard cell being placement information of a layout pattern which is designed by repeating several times a predetermined processing of a compaction or resizing, and wherein the underlayer includes a plurality of compacted or resized transistor elements are formed on the circuit substrate.