Patent ID: 8539294

Claim:
An integrated circuit comprising: A. logic circuitry having a certain order of logic stimulus inputs and a certain order of logic response outputs; B. a scan in lead and a scan out lead; and C. a scan path of serially connected scan cells, the scan path having an input connected to the scan in lead, an output connected to the scan out lead, a certain order of scan stimulus parallel outputs connected from the scan cells to the certain order of logic stimulus inputs, and a certain order of scan response parallel inputs connected to the scan cells from the certain order of logic response outputs, the scan path being divided into segments of scan cells, each segment having a scan input connected to the scan in lead, a separate scan enable input, a separate scan clock input, a separate scan output, stimulus parallel outputs, response parallel inputs, and a tristate output buffer selectively coupling the separate scan output with the scan out lead, and each segment maintaining the certain order of stimulus parallel outputs and response parallel inputs; and D. decode logic circuitry having a scan clock input, a scan enable input, at least one binary control input, and, for each segment, a separate scan clock output and a separate scan enable output.