Patent ID: 7770140

Claim:
A method of integrated circuit (IC) design model testing, comprising: receiving a workload, by a simulator test information handling system (IHS) that includes the IC design model, the workload including test application software exhibiting a first predetermined number of instructions; grouping, by the simulator test IHS, the workload into a plurality of instruction intervals, each instruction interval including a second predetermined number of instructions of the workload; generating, by the simulator test IHS, a plurality of basic block vectors (BBVs), each BBV being generated for a respective instruction interval; generating, by the simulator test IHS, a respective fly-by vector (FBV) for each BBV generated by the simulator test system, each FBV being generated independently of its respective BBV, but having in common a same instruction interval, each FBV including microarchitecture dependent information; clustering, by the simulator test IHS, the BBVs to form BBV cluster groups that represent code profile phases of the workload; clustering, by the simulator test IHS, the FBVs to form FBV cluster groups that represent microarchitecture dependent phases of the workload, the FBV clustering being independent of the BBV clustering; and generating, by the simulator test IHS, a reduced representative workload as specified by a total instruction budget that includes a BBV instruction budget and an FBV instruction budget.