Patent ID: 7323915

Claim:
A Delay Locked Loop (DLL), comprising: a control module coupled to receive a phase detect signal, the control module deriving a feedback select signal and an output select signal based on the phase detect signal; a Multi-Tap Delay Line (MTDL) coupled to receive a reference clock signal, the MTDL comprising a plurality of delay taps, each delay tap outputting a delayed reference clock signal, the MTDL, thereby, providing a plurality of delayed reference clock signals; a first multiplexer coupled to receive the feedback select signal and the plurality of delayed reference clock signals, the first multiplexer selecting, via the feedback select signal, a first delayed reference clock signal from the plurality of delayed reference clock signals as a feedback clock signal; a second multiplexer coupled to receive the output select signal and the plurality of delayed reference clock signals, the second multiplexer selecting, via the output select signal, a second delayed reference clock signal from the plurality of delayed reference clock signals as a first output signal; and; a phase detector coupled to receive the reference clock signal and the feedback clock signal, the phase detector deriving the phase detect signal by measuring a phase difference between the reference clock and feedback clock signals; wherein the phase detector comprises latches coupled together in a voting scheme so as to prevent Single Event Upset (SEU) events.