Patent ID: 6885609

Claim:
A dual-port semiconductor memory device comprising: a semiconductor substrate, which includes a memory cell having one N-well area where a p+-type active region is formed and one contiguous P-well area where an n+-type active region is formed; a first word line; a second word line (scan address line); a first bit line; a first complementary bit line; a second bit line (scan data out line); a first CMOS inverter, which includes a first NMOS transistor, a first PMOS transistor, an input terminal, and an output terminal; a second CMOS inverter, which includes a second NMOS transistor, a second PMOS transistor, an input terminal, and an output terminal, wherein the input terminal of the second CMOS inverter is connected to the output terminal of the first CMOS inverter to form a first memory node and the output terminal of the second CMOS inverter is connected to the input terminal of the first CMOS inverter to form a second memory node; a third NMOS transistor, which has a gate connected to the first word line, a drain connected to the first bit line, and a source connected to the first memory node; a fourth NMOS transistor, which has a gate connected to the first word line, a drain connected to the first complementary bit line, and a source connected to the second memory node; a fifth NMOS transistor, which has a gate connected to the first memory node and a source connected to a ground line; and a sixth NMOS transistor, which has a gate connected to the second word line, a source connected to the drain of the fifth NMOS transistor, and a drain connected to the second bit line, wherein the first PMOS transistor and the second PMOS transistor are disposed in the p+-type active region of the N-well area; and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are formed in the n+-type active region of the contiguous P-well area.