Patent ID: 8652891

Claim:
A method of manufacturing a semiconductor device, comprising: forming a plurality of fins extending along a first direction on a substrate and a hard mask layer over the fins; forming a plurality of dummy gate stack structures extending along a second direction and across each of the fins; forming stress layers in the fins on both sides of the dummy gate stack structures and source and drain regions in the stress layers; depositing an interlayer dielectric layer to overlap the fins, the stress layers, and the dummy gate stack structures; removing the dummy gate stack structures, thereby forming first gate trenches in the interlayer dielectric layer to expose the hard mask layer; etching the fins below the hard mask layer to form second gate trenches, wherein the fins between the second gate trenches and the hard mask layer form a plurality of channel regions; and performing a deposition in the first and second gate trenches to form a plurality of gate stack structures that enclose the plurality of channel regions.