Patent ID: 6861318

Claim:
A method of forming a transistor comprising: forming a gate dielectric layer on a layer of semiconductor material having a first lattice with a first structure and a first spacing; forming a gate electrode on the gate dielectric layer; implanting dopants into the layer of semiconductor material to form doped tip regions in the layer with a channel between the tip regions; etching the layer to form source and drain recesses in the layer with the tip regions between the recesses; and filling the source and drain recesses with a source and a drain respectively, wherein at least one of the source and drain regions is made of a film material which: (a) is formed epitaxially on the semiconductor material; and (b) has a second lattice with a second structure which is the same as the first structure; and (c) includes a dopant selected from one of a p-dopant and an n-dopant, wherein (i) if the dopant is a p-dopant, the second spacing is larger than the first spacing, and (ii) if the dopant is an n-dopant, the second spacing is smaller than the first spacing.