Patent ID: 8518792

Claim:
A method for forming an integrated circuit device in conjunction with a 3-D transistor structure formed in a planar surface of a semiconductor substrate, the method comprising: forming an insulating layer overlying said planar surface; selectively removing a portion of said insulating layer and a selected region of said planar surface beneath said portion to form an opening over said transistor structure and expose first and second contacts to said transistor structure; forming conductive spacers to each of said first and second contacts laterally of said opening; forming bottom electrode spacers medially of said conductive spacers within said opening; forming an insulating cap in a lower portion of said opening between said conductive and bottom electrode spacers; forming ferroelectric spacers in said opening over said insulating cap and medially of said bottom electrode spacers; forming top electrode spacers in said opening over said insulating cap and medially of said ferroelectric spacers; forming an additional insulating layer in said opening over said insulating cap and between said top electrode spacers; and forming a first contact stud to a first one of said top electrode spacers and a second contact stud to a second one of said top electrode spacers.