Patent ID: 7821059

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a stacking structure formed on the semiconductor substrate, the stacking structure including in order: a tunnel insulating film, an electric charge storage layer, a top insulating film made of an oxide including Al, Si, and La, and a control electrode; a side wall formed on a side of the stacking structure, the side wall being made of at least one selected from the group consisting of SiO 2 , SiN and SiON; and an impurity doped layer formed at a surface of the semiconductor substrate adjacent to the tunnel insulating film, wherein the top insulating film has: a number ratio Si/La of Si element to La element that is no less than 0.93 and no more than 2.78; a number ratio Al/La of Al element to La element that is no less than 0.0625 and no more than 96; and a number ratio Si/(La+Al) of Si element to La element and Al element that is no less than 0.6.