Patent ID: 8184635

Claim:
A switch comprising: an ingress port configured to receive data packets; a segment buffer memory in communication with the ingress port and being configured to store the data packets received from the ingress port; a plurality of egress ports, each egress port being in communication with the segment buffer memory and being configured to forward the data packets; and a plurality of egress port queues, each egress port queue being configured to store pointers to the locations of respective ones of the stored data packets to be forwarded to at least one associated egress port of the plurality of egress ports, each egress port queue comprising: a first queue memory having a first memory access time, the first queue memory being configured to store the pointers; and a second queue memory having a second memory access time that is significantly slower than the first memory access time, the second queue memory being in communication with the first queue memory for receiving a plurality of pointers from the first queue memory in a single transfer cycle.