Patent ID: 7797497

Claim:
For a configurable integrated circuit (IC) that implements a user design having an associated user design clock cycle, said IC operating on a sub-cycle clock that has multiple sub-cycle periods within a user period of said user design clock cycle, a method of mapping the user design to the configurable IC, the method comprising: a) identifying accesses to multiple ports of a multi-port memory defined in the user design, said accesses being in a single user design clock cycle; and b) mapping said accesses to the multiple ports of the multi-port memory to multiple accesses of a particular port of a physical memory in the configurable IC during multiple sub-cycles associated with the single user design clock cycle, wherein the particular port of the physical memory is for accessing the physical memory at least once per sub-cycle period, and the particular port comprises a clock input for receiving clock signals at a first frequency that is a frequency of the sub-cycle clock.