Patent ID: 7010452

Claim:
An event pipeline and summing apparatus for processing event data stored in an event memory of an event based test system, comprising: an event count delay logic which produces a gross delay of event count data, which is an integral part of the event data, by counting a clock by a number of times defined by the event count data; a vernier data decompression logic which reproduces event vernier data which is a fractional part of the event data; an event vernier summing logic which produces event vernier sum data by summing the vernier data from the vernier data decompression logic; and an event scaling logic which changes the event count data from the event count delay logic and the event vernier data from the event vernier summing logic in proportion to a scale factor; wherein a plurality of parallel pipelines are incorporated at least in the event vernier summing logic for processing the event vernier data in parallel where each pipeline is configured by a plurality of series connected registers.