Patent ID: 7936789

Claim:
An integrated circuit comprising: a core circuit and an input/output (I/O) circuit operating in different clock domains, the core circuit including circuitry to conditionally steer parallel test data to the I/O circuit at a first frequency, the I/O circuit including a parallel-to-serial converter circuit to convert the parallel test data to serial test data at a second frequency, where the second frequency is higher than the first frequency, the I/O circuit further including a serial-to-parallel converter circuit to convert the serial test data to parallel feedback test data; control circuitry to steer the parallel test data from the core circuit to the I/O circuit, and to influence operation of the parallel-to-serial converter to allow synchronization between the different clock domains when the I/O circuit awakes from a reduced power non-operational state; and a data path from the I/O circuit to the core circuit to return to the core circuit the parallel feedback test data, wherein the core circuit includes a comparator to compare the parallel test data against the parallel feedback test data to determine a timing offset between the different clock domains, and to compare the timing offset between the different clock domains with a stored timing offset determined during a link training between the circuits of the different clock domains, the link training occurring prior to the reduced power state, and wherein synchronization between the different clock domains includes adjusting the timing offset between the different clock domains to match the stored timing offset.