Patent ID: 7420284

Claim:
A semiconductor device comprising: a semiconductor chip having a plurality of semiconductor elements and a plurality of external terminals formed in a main surface thereof; an elastic layer provided on the main surface of the semiconductor chip in a manner to expose the plurality of external terminals, the elastic layer having a first edge and a second edge opposing to the first edge, the first edge being closer to the plurality of external terminals than the second edge, the elastic layer containing a volatile ingredient thereof; an insulating tape provided on the elastic layer and having an opening to expose the plurality of external terminals, the opening being defined by an edge of the insulating tape; a plurality of leads provided on a surface of the insulating tape, wherein each of the plurality of leads has a first portion disposed on the insulating tape and a second portion which extends across the edge of the insulating tape and is in the opening of the insulating tape, each of the second portions being electrically connected with a corresponding one of the external terminals, a bump land being comprise of a part of the first portion of each of the plurality of leads; and a plurality of bump electrodes formed on the bump land of each of the plurality of leads and being electrically connected to the plurality of leads, respectively, wherein each of the plurality of leads includes a copper lead as core material thereof, wherein the copper lead of each of the plurality of leads has gold-plating applied on its surface, wherein a length of the second portion of each of the plurality of leads is longer than a straight line distance from the edge of the insulating tape to the corresponding one of the external terminals, and wherein the elastic layer is recessed from the edge of the insulating tape in a plane view such that the first edge of the elastic layer is arranged between the edge of the insulating tape and the bump land in a plane view.