Patent ID: 7861064

Claim:
A method for selectively accelerating early instruction processing, comprising: receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage; determining if dispatching the instruction data to the address generation stage for processing results in a delay due to an unavailability of a resource needed for the processing of the instruction data in the address generation stage, the determining responsive to an address generation interlock scheme; dispatching the instruction data for processing in the address generation stage if it is determined that dispatching the instruction data to the address generation stage for processing does not result in a delay due to the unavailability of the resource; and dispatching the instruction data for processing in the execution stage if it is determined that dispatching the instruction data to the address generation stage for processing results in a delay due to the unavailability of the resource, the dispatching the instruction data for processing in the execution stage comprising overriding a delaying of the instruction data by the address generation interlock scheme in response to the unavailability of the resource and allowing the instruction data to dispatch to the execution stage via the address generation stage.