Patent ID: 8178905

Claim:
A layout structure of a semiconductor device, the layout structure comprising: a cell line including a plurality of cells arranged in series; and a reinforcing power supply cell arranged in any one of positions between the cells in the cell line, wherein each said cell includes: a first impurity doped region arranged on a first well region for supplying a substrate or well potential which is different from a positive power supply potential to a p-type transistor arranging region; and a second impurity doped region arranged on a second well region for supplying a substrate or well potential which is different from a ground potential to an n-type transistor arranging region, the first and second impurity doped regions of the cells adjacent to each other are electrically and physically connected, respectively, said reinforcing power supply cell includes: first and second power supply impurity doped regions to which the first and second impurity doped regions in one of the cells located adjacent thereto are electrically connected, respectively; first and second power supply wires provided in a first wiring layer formed above the first and second power supply doped regions and electrically connected to the first and second power supply impurity doped regions, respectively; and first and second pins provided in a second wiring layer formed above the first and second power supply wires and electrically connected to the first and second power supply wires, respectively, and the first and second pins are arranged in the same straight line extending in parallel to a direction of alignment of the cells, and in the second wiring layer, a first cell wire electrically connected to an adjacent cell adjacent to the reinforcing power supply cell is provided between the first pin and a region above the first power supply impurity doped region.