Patent ID: 8652898

Claim:
A method for fabricating an integrated circuit, the method comprising: isolating a transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer; forming a dummy gate structure on the first semiconductor layer in the transistor region; after forming the dummy gate structure, forming a gate spacer on vertical sidewalls of the dummy gate structure; after forming the gate spacer, forming a second semiconductor layer on the first semiconductor layer, first and second portions of the second semiconductor layer being in contact with first and second portions, respectively, of the first semiconductor layer located in the transistor region, and a third portion of the second semiconductor layer being in contact with a third portion of the first semiconductor layer located in the capacitor region; forming a first silicide region on the first portion of the second semiconductor layer, a second silicide region on the second portion of the second semiconductor layer, and a third silicide region on the third portion of the second semiconductor layer; forming a dielectric layer that covers the first, second, and third silicide regions; after forming the dielectric layer, removing the dummy gate structure so as to form a first cavity, and removing at least a portion of the dielectric layer located above the third silicide region so as to form a second cavity; forming a gate dielectric in the first cavity and a capacitor dielectric in the second cavity; and forming a gate conductor in the first cavity and a metal electrode in the second cavity.