Patent ID: 7106649

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in rows and columns and which comprises a plurality of memory sub-array blocks divided in a direction of the rows; a plurality of sub-word lines which are provided in each of the plurality of memory sub-array blocks, and extend in the direction of the rows to connect with corresponding ones of the plurality of memory cells; a plurality of sub-word-line drivers each of which is provided in each of the plurality of memory sub-array blocks and which drive the plurality of sub-word lines; a plurality of sub-word-line level shifters each of which is provided in each of the plurality of memory sub-array blocks and which supply a boosted signal to the plurality of sub-word-line drivers; a first pre-decoded line group which extends across the plurality of memory sub-array blocks in the direction of the rows, and is connected with the plurality of sub-word-line drivers; a second pre-decoded line group which extends across the plurality of memory sub-array blocks in the direction of the rows, and is connected with the plurality of sub-word-line level shifters; and a pre-row-decoder which pre-decodes an address of a selected cell in the plurality of memory cells, and supplies information of a sub-word-line corresponding to a row address of the selected cell in the plurality of sub-word lines to the first pre-decoded line group and the second pre-decoded line group, wherein signal voltages of the plurality of sub-word-lines are selectively made higher than signal voltages of the first pre-decoded line group by the plurality of sub-word-line level shifters and the plurality of sub-word-line drivers.