Patent ID: 7180126

Claim:
A non-volatile memory transistor array having word lines over the surface of a substrate and bit lines under the surface comprising: (a) a plurality of non-volatile memory transistors, each transistor storing two binary bits and having (i) an active region in the substrate defined by a stripe running in a first direction with spaced apart source and drain subsurface regions in the active region electrically connected across the array as subsurface stripes running in a second direction, the second direction being perpendicular to the first direction; (ii) a first insulative layer disposed over the substrate between the source and drain regions; (iii) a polysilicon gate disposed over the insulative layer, the polysilicon gate having sidewalls; (iv) a pair of conductive polysilicon upright spacers acting as charge storage regions spaced apart above the substrate on opposite sides of the polysilicon gate adjacent to the sidewalls but separated therefrom and from the substrate by tunnel oxide, the spacers and the polysilicon gate lying in the same plane; (v) a second insulative layer covering the upright spacers and the polysilicon gate, thereby allowing the spacers to be electrically floating structures; (vi) a polysilicon word line over the second insulative layer electrically connected across the array as a single stripe over the surface running in the second direction and having means for electrically communicating with the polysilicon gate through an opening in the insulative layer at voltage levels effective for writing charge on the upright spacers by tunneling action with respect to the subsurface source and drain regions and reading charge on the upright spacers through the polysilicon gate; and (b) first and second low voltage transistors conducting in opposed phases associated with the source and drain regions respectively of multiple memory transistors, applying a signal of one polarity first to the source region of the memory region and then to the drain region.