Patent ID: 8188549

Claim:
A semiconductor memory device comprising: a memory array having a plurality of memory cells arranged in a matrix of rows and columns; a plurality of bit line pairs arranged corresponding to the respective memory cell columns; a plurality of word lines arranged corresponding to the respective memory cell rows; a plurality of first power supply lines supplying a first power supply voltage to the corresponding memory cells; a plurality of second power supply lines supplying a second power supply voltage to the corresponding memory cells; and a plurality of power feed cells provided corresponding to the respective memory cell columns, feeding a first P well region, a second P well region and a N well region extended in a column direction respectively, wherein said memory cell including a first and a second P-channel MOS load transistors arranged on said N well region, having source nodes supplied said first power supply voltage, a first N-channel MOS driver transistor arranged on said first P well region, connected to said first P-channel MOS load transistor to configure a first inverter, having a source node supplied said second power supply voltage, a second N-channel MOS driver transistor arranged on said second P well region, connected to said second P-channel MOS load transistor to configure a second inverter, having a source node supplied said second power supply voltage, a first N-channel MOS access transistor arranged on said first P well region, connected to said first inverter, and a second N-channel MOS access transistor arranged on said second P well region, connected to said second inverter, wherein said power feed cell including a third power supply line supplying a third power supply voltage to said N well region, and two fourth power supply lines arranged in parallel, supplying a fourth power supply voltage to said first and second P well regions, wherein said third power supply line is structured on a first metal interconnection layer, said first power supply line is structured on a second metal interconnection layer above said first connection layer, and said fourth power supply lines are structured on a third metal interconnection layer above said second connection layer.