Patent ID: 8035434

Claim:
A delay locked loop comprising: a delay line comprising a plurality of differential delay elements having V nbias inputs and V pbias inputs; a biasing circuit comprising: an input for receiving a control voltage, and a V nbias output for outputting a V nbias voltage for input to the V nbias inputs of the differential delay elements, and a V pbias output for outputting a V pbias voltage for input to the V pbias inputs of the differential delay elements; a direct connection between the input and the V pbias output such that the V pbias output tracks the control voltage; circuitry that produces the V nbias voltage from the control voltage, the circuitry comprising: a pull-up network for pulling up the V nbias voltage when the control voltage is low; a pull-down network for pulling down the V nbias voltage when the control voltage is high; and a variable resistive element for impeding the pull-down network from pulling down the V nbias ; wherein the pull-up network comprises a p-type transistor having a gate connected to receive the control voltage; wherein the pull-down network comprises an n-type transistor having a gate connected to receive the control voltage.