Patent ID: 7660364

Claim:
An apparatus comprising: a buffer memory having a plurality of stages, wherein the buffer memory receives serial data; decision logic that detects whether at least one of a plurality of predetermined bit sequences is present in the serial data, and wherein each of the plurality of predetermined bit sequences is susceptible to inter-symbol-interference (ISI), and wherein the decision logic includes: a plurality of XNOR gates, wherein each XNOR gate is coupled to at least two successive stages of the buffer memory; a first set of D-flip-flops, wherein each D-flip-flop from the first set of D-flip-flops is coupled to at least one of the XNOR gates; a first set of logic gates, wherein each logic gate from the first set of logic gates is coupled to a plurality of D-flip-flops from the first set of D-flip-flops; a second set of D-flip-flops, wherein each D-flip-flop from the second set of D-flip-flops is coupled at least one of the logic gates from the first set of logic gates; and a second set of logic gates, wherein each logic gate from the second set of logic gates is coupled to a plurality of D-flip-flops from the second set of D-flip-flops; a transmitter that is coupled to the buffer memory so as to receive the serial data from the buffer memory; a clock generate having a plurality of output terminals, wherein each output terminal outputs at least one phase of a clock signal; a phase multiplexer having a plurality of selection terminals, a plurality of input terminals, and an output terminal, wherein each selection terminal is coupled to the decision logic, and wherein each input terminal of the phase multiplexer is coupled to at least one of the output terminals of the clock generator, and wherein the output terminal of the phase multiplexer is coupled to each of the buffer memory and the transmitter, and wherein each D-flip-flop from the first set of D-flip-flops is coupled to the output terminal of the phase multiplexer.