Patent ID: 7791193

Claim:
A system, comprising: a bus; a display in communication with the bus; a memory in communication with the bus; and an integrated circuit in communication with the display and the memory via the bus, the integrated circuit including an active circuit; a metal layer disposed, at least partially, above the active circuit; and a bond pad disposed, at least partially, above the metal layer; wherein the metal layer is meshed; wherein the bond pad is only disposed above an outer periphery of an input/output (I/O) bus of the active circuit; wherein an interconnect metal layer of the metal layer is electrically coupled to a plurality of underlying metal layers by way of vias, the plurality of underlying metal layers disposed at least in part below the active circuit; wherein the interconnect metal layer interconnects the bond pad with the plurality of underlying metal layers; wherein the interconnect metal layer of the metal layer defines an island, the island including a plurality of openings, the openings defining a plurality of substantially linear first portions and a plurality of substantially linear second portions which intersect, where interconnect vias formed in rows along a length of at least the first portions provide communication between the interconnect metal layer and the bond pad; wherein the openings are adapted for facilitating an interlock between the interconnect metal layer of the metal layer and an inter-metal dielectric layer disposed between the metal layer and the bond pad.