Patent ID: 7596483

Claim:
A method of determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths, the method comprising: 1) Forming predictions for timing delays in said signal paths in the integrated circuit; 2) Selecting a first such path, tracing wires in the integrated circuit forming the path, hereinafter referred to as victim wires, and determining adjacent and crossing wires thereto, hereinafter referred to as aggressor wires; 3) For each aggressor wire, determining the amount of electromagnetic coupling to the victim wires of the first path; 4) Dividing the aggressor wires into a plurality of categories depending on the clocked timing of the aggressor wires in relation to the clocked timing of the victim wires; 5) Allowing a user to select a mode of operation; and 6) For each victim wire, modifying the predictions formed in step (1) based on the effects of the aggressor wires only in those categories corresponding to the mode of operation selected by the user.