Patent ID: 8359448

Claim:
A system for controlling a memory arrangement, comprising: an array of programmable resources and interconnect resources, the programmable resources and interconnect resources in the array initially configured with a reference configuration data-set, wherein the reference configuration data-set configures the programmable resources and interconnect resources to implement a general memory controller; a port coupled to the array, the port for reconfiguring the programmable resources and interconnect resources in the array; and a processor coupled to the port, the processor configured to obtain a characteristic of the memory arrangement and to select one of a plurality of partial reconfiguration data-sets in response to the characteristic of the memory arrangement, the processor further configured to partially reconfigure the programmable resources and interconnect resources in the array via the port with the selected partial reconfiguration data-set, wherein the selected partial reconfiguration data-set partially reconfigures the programmable resources and interconnect resources to implement a portion of a specific memory controller that differs from the general memory controller.