Patent ID: 6931509

Claim:
A method of interfacing a data storage device comprising an array of a plurality of memory elements, with a logical address bus on which a plurality of logical address data is carried for identifying data stored in said memory device, said method comprising the steps of: storing a data translation table comprising a plurality of data entries, each said data entry comprising a look up logical address value being a logical address stored in said data translation table and a look up physical address value, said look up physical address value corresponding to a physical location of one or more said memory elements; upon receipt of a requested logical address, parsing said data entries in said data table, to read a look up logical address of each of a plurality of said data entries; comparing said look up logical address with said requested logical address; if a said look up logical address is less than said requested logical address, continuing to parse said data translation table; and if a said look up logical address is less than said requested logical address, determining a corresponding respective physical address to said requested logical address as being said requested logical address, minus a look up logical address of a preceding data entry in said data translation table, plus a look up physical address corresponding to said preceding data entry in said data translation table.