Patent ID: 8461867

Claim:
A semiconductor device comprising: a bonding pad including a first portion and a second portion arranged separately from the first portion in physical layout; first and second transistors configured to receive a control signal in common and output first and second output data in response to the control signal, respectively; first and second terminals configured to be supplied with the first and second output data, respectively, the first terminal being arranged separately from the second terminal in physical layout; a first wiring coupled between the first terminal and the first portion of the bonding pad in physical layout; a second wiring coupled between the second terminal and the second portion of the bonding pad, the second wiring being arranged separately from the first wiring in physical layout; and a third wiring conveying the control signal, the first transistor including a gate electrode that is directly connected to the third wiring and the second transistor including a gate electrode that is directly connected to the third wiring.