Patent ID: 8241979

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an insulation layer structure pattern having an opening therethrough on a substrate having a lower structure, the opening exposing a contact region of the lower structure; forming a metal layer on a sidewall of the opening; forming an amorphous silicon layer doped with first impurities, the amorphous silicon layer partially filling the opening; reacting a portion of the metal layer with the amorphous silicon layer to form a metal silicide layer; crystallizing the amorphous silicon layer, using the metal silicide layer, to form a polysilicon layer in the opening; implanting second impurities into the polysilicon layer to form a doped polysilicon layer in the opening, the second impurities having a type of conductivity different from that of the first impurities; and forming a lower electrode on the doped polysilicon layer.