Patent ID: 7571204

Claim:
An M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit comprising: M adder cells arranged in R rows, wherein a least significant adder cell in a first one of said rows of adder cells is operable to: receive a first data bit, A X , from said first M-bit argument and a first data bit, B X , from said second M-bit argument, generate both a first conditional carry-out bit, C X ( 1 ), and a second conditional carry-out bit, C X ( 0 ), provide the first and second conditional carry-out bits C X ( 1 ) and C X ( 0 ) to a second one of said adder cells, and wherein said C X ( 1 ) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding said first row is a 1 and said C X ( 0 ) bit is calculated assuming said row carry-out bit from said second row is a 0; and wherein said second one of said adder cells within said first one of said rows is operable to: receive a first data bit, A X+1 , from said first M-bit argument and a first data bit, B X+1 , from said second M-bit argument, receive both said first conditional carry-out bit, C X ( 1 ) and said second conditional carry-out bit C X ( 0 ), generate both a first conditional carry-out bit, C X+1 ( 1 ), and a second conditional carry-out bit, C X+1 ( 0 ), by propagating said first conditional carry-out bit C X ( 1 ) and said second conditional carry-out bit C X ( 0 ) through a first pass gate and a second pass gate, respectively, when said first data bit A X+1 and said second data bit B X+1 are not equal, and output said first and second conditional carry-out bits C X+1 ( 1 ) and C X+1 ( 0 ) to other circuitry, and wherein said second adder cell further comprises: a first inverter operable for inverting said first conditional carry-out bit C X ( 1 ) transmitted through said first pass gate prior to outputting said first conditional carry-out bit C X ( 1 ); and a second inverter operable for inverting said second conditional carry-out bit C X ( 0 ) transmitted through said second pass gate prior to outputting said second conditional carry-out bit C X ( 0 ).