Patent ID: 8154077

Claim:
A semiconductor device, comprising: a gate electrode formed on a semiconductor substrate via an insulating layer; a source region formed in the semiconductor substrate and including an extension region in a side closer to the gate electrode and a conductive impurity, the extension region including a side surface facing a horizontal direction and a bottom surface facing a vertical direction; a drain region formed in the semiconductor substrate and including an extension region in a side closer to the gate electrode and the conductive impurity, the extension region including a side surface facing the horizontal direction and a bottom surface facing a vertical direction; a first diffusion restraining layer formed in the semiconductor substrate, configured to prevent a diffusion of the conductive impurity in the source region, and including an impurity other than the conductive impurity, the first diffusion restraining layer being in contact with the side surface of the extension region of the source region and not in contact with the bottom surface of the extension region of the source region; and a second diffusion restraining layer formed in the semiconductor substrate and configured to prevent a diffusion of the impurity in the drain region, and including the impurity other than the conductive impurity, the second diffusion restraining layer being in contact with the side surface of the extension region of the drain region and not in contact with the bottom surface of the extension region of the drain region.