Patent ID: 8357991

Claim:
A semiconductor device, comprising: an upper interconnect formed of a material; a lower interconnect that is placed below said upper interconnect; an insulating layer that is placed between said upper interconnect and said lower interconnect; a connecting portion that is formed in said insulating layer over said lower interconnect and connects said upper interconnect and said lower interconnect, wherein said connecting portion is formed with the material of the upper interconnect; a fuse element that is placed in said insulating layer and has a conductive layer connected to said connecting portion, said fuse element having an outermost perimeter, and said connecting portion located adjacent to an end portion of said conductive layer on said outermost perimeter, said connecting portion being in contact with less than an entirety of an upper face of said lower interconnect, and also in contact with an upper face and a side face of said end portion on said outermost perimeter of said conductive layer of said element; a hole formed in said insulating layer exposing said upper face of said lower interconnect, and said side face and upper face of said conductive layer of said fuse element; and another insulating layer that covers said upper interconnect, wherein said connecting portion is formed along an inner surface of said hole, and said another insulating layer fills the region inside the connecting portion.