Patent ID: 6917248

Claim:
A variable capacitance circuit comprising: a first variable capacitive element having a varying capacitance within a first capacitance range; a second variable capacitive element having a varying capacitance within a second capacitance range disposed within a parallel circuit path with the first variable capacitive element for in conjunction with the first variable capacitive element providing a summed capacitance, which is a sum of the first capacitance of the first variable capacitive element and the second capacitance of the second variable capacitive element; a biasing circuit comprising: at least a diode disposed in series between the first and second variable capacitive elements; and, at least a coupling capacitor disposed in parallel with the diode, said coupling capacitor and said diode being in series between the first and second variable capacitive elements, for providing a first bias voltage to the first variable capacitive element and for providing a second bias voltage to the second variable capacitive element; a tuning voltage circuit for providing a tuning voltage to each of the first and second variable capacitive elements; an output port for providing an output signal; and, at least a reactive component disposed in parallel with the first and second variable capacitive elements and disposed in series with the coupling capacitors and the diodes for, with the summed capacitance arising therefrom, forming a stable oscillator when in use, wherein a first potential difference between the tuning voltage applied to the first variable capacitive element and the first bias voltage is different from a second potential difference between the tuning voltage applied to the second variable capacitive element and the second bias voltage, wherein a slope of the variation of the summed capacitance for the first and second variable capacitive elements is less than a slope of the variation of capacitance for a single variable capacitive element formed using a same semiconductor process, wherein the summed capacitance is dependent upon a magnitude and polarity of the tuning voltage applied to the first variable capacitive element and the first bias voltage and a magnitude and polarity of the tuning voltage applied to the second variable capacitive element and the second bias voltage, wherein an oscillating frequency of the output signal is dependent upon a reactance of the at least a reactive component and the summed capacitance, wherein said diode provides the difference between the first potential difference and the second potential difference.