Patent ID: 8866751

Claim:
A display device comprising: a display panel including an array substrate on which source lines and gate lines are disposed and an opposite substrate on which a common electrode is disposed, the opposite substrate facing the array substrate; a source driving part configured to output a data signal to respective source lines during a display period of a frame period; a gate driving part configured to output a gate signal to respective gate lines during the display period; a readout part configured to read out a detection signal during an elimination period of the frame period, the readout part being electrically connected with at least one of the lines of the array substrate, wherein the elimination period is separate from the display period; a pulse generating part configured to output a control pulse for operating the readout part during the elimination period; and a voltage generating part configured to electrically float the entire common electrode during the elimination period, wherein the opposite substrate is adapted to be touched by an object wherein the readout part comprises: a first readout part configured to read out first detection signals from the source lines, the first readout part, the first readout part comprising: a first switching part having a plurality of first transistors electrically connected to respective terminals of the source lines; and a first current detecting part having a plurality of first op-amps electrically connected to respective one or more of the first transistors of the first switching part, the first current detecting part being configured to output first detection currents flowing through the source lines as the first detection signals; and a second readout part configured to read out second detection signals from the gate lines, the second readout part comprising: a second switching part having a plurality of second transistors electrically connected to respective terminals of the gate lines; and a second current detecting part having a plurality of second op-amps electrically connected to respective one or more of the second transistors of the second switching part, the second current detecting part being configured to output second detection currents flowing through the gate lines as the second detection signals, wherein the pulse generating part is configured to output a first control pulse and a second control pulse at the same time for controlling an operation of the first readout part and an operation of the second readout part, respectively, wherein the first detection signals from the source lines are configured to be read out at the same start time as the second detection signals from the gate lines are read out, wherein gate electrodes of the plurality of first transistors are configured to simultaneously receive the first control pulse, and wherein gate electrodes of the plurality of second transistors are configured to simultaneously receive the second control pulse.