Patent ID: 7928427

Claim:
A method for manufacturing a semiconductor device with group III-V channel and group IV source-drain, comprising: preparing a substrate, the substrate being a group III-V substrate or a Si substrate with GaN grown thereon; forming a recess in the substrate by etching, the recess having a depth required for forming a channel-containing stacked element by subsequent epitaxy; forming the channel-containing stacked element in the recess by epitaxy; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; forming a source-drain recess on the substrate by using the dummy gate as a mask; filling the source-drain recess with a group IV material by selective heteroepitaxy using the dummy gate as a mask; doping the group IV material by self-aligned ion implantation and activating the group IV material at high temperature, so as to form source-drain; removing the dummy gate; and forming a gate on the channel-containing stacked element.