Patent ID: 6876084

Claim:
A chip package structure, comprising: a carrier having at least one signal contact, a pair of first non-signal contacts and a pair of second non-signal contacts, wherein the signal contact, the pair of first non-signal contacts and the pair of second non-signal contacts are positioned on the surface of the carrier, and the second non-signal contacts are electrically connected to each other; a die having an active surface and a corresponding back surface, wherein the back surface of the die is attached to one surface of the carrier, the die further includes a signal pad, a pair of first non-signal pads and a pair of second non-signal pads, the signal pad, the pair of first non-signal pads and the pair of second non-signal pads are positioned on the active surface of the die, and furthermore, the pair of second non-signal contacts is closer to the die than the signal contact or the pair of first non-signal contacts; a signal wire whose ends are connected to the signal pad and the signal contact respectively; a pair of first non-signal wires, wherein the two ends of each first non-signal wire are connected to one of the first non-signal pads and one of the first non-signal contacts respectively, and the first non-signal wires of the first non-signal wire pair are on each side of the signal wire; and a pair of second non-signal wires, wherein the two ends of the each second non-signal wire are connected to one of the second non-signal pads and one of the second non-signal contacts respectively, and the second non-signal wires of the second non-signal wire pair are on each side of the signal wire and first non-signal wire pair assembly.