Patent ID: 6998652

Claim:
A memory cell comprising: a substrate; a thyristor having anode and cathode emitters, at least one base region in the substrate and a control port; a trench region in the substrate laterally adjacent to said at least one base region in the substrate, the trench region including an insulative liner material and a conductive material in a portion of the trench region that is lined, the insulative liner material being arranged to electrically insulate the conductive material from said at least one base region in the substrate, wherein the thyristor control port is in the trench and configured and arranged for capacitively coupling to the at least one base region in the substrate for causing an outflow of minority carriers from the thyristor body for controlling current therein; a pass device coupled to a first emitter region of the thyristor and adapted to pass current between the emitter region and a bit line; a reference voltage interconnect coupled to a second emitter region of the thyristor; and wherein, in response to pulses applied to the control port and the pass device, the memory cell is adapted for storing data as a state of the thyristor, for reading the stored data from the memory cell via the bit line and for writing data to the memory cell via the reference voltage interconnect.