Patent ID: 7804327

Claim:
An I/O buffer, comprising: a plurality of the level shifters, each comprising: a first logic unit powered by an input/output (I/O) power voltage, the first logic unit receiving input signals with a core power voltage, the first logic unit comprising first and second output terminals; and a first driver coupled to the first output terminal, matching a voltage level on the first output terminal with the I/O power voltage by AC coupling when the core power voltage is not ready during power-up; and a plurality of driving units coupled between the level shifters and a pad, the driving units selectively setting a logic state of the pad to one of N predetermined logic states according to the voltages on the first or second output terminal of the level shifters during power-up, wherein N predetermined logic states comprise a strong “1” state, a strong “0” state, a weak “1” state, a weak “0” state and a high impedance state, and the driving units comprise: a pull-up driver coupled between the I/O power voltage and the pad, the pull-up driver setting the logic state of the pad to the strong “1” state when turning on; a pull-down driver coupled between the pad and a ground voltage, the pull-down driver setting the logic state of the pad to the strong “0” state when turning on; a weak pull-up resistor coupled between the pad and the I/O power voltage, the weak pull-up resistor setting the logic state of the pad to the weak “1” state when turning on; and a weak pull-down resistor coupled between the pad and the ground voltage, the weak pull-down resistor setting the logic state of the pad to the weak “0” state when turning on, wherein when the pull-up driver, the pull-down driver, the weak pull-up resistor and the weak pull-down resistor are turned off, the logic state of the pad is set at the high impedance state.