Patent ID: 8088668

Claim:
A method for manufacturing capacitor lower electrodes of a semiconductor memory, comprising the steps of: forming a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs, the first stacked structure includes two first insulating oxide layers, a first dielectric layer and a first insulating nitride layer, the first dielectric layer and the first insulating nitride layer are interposed there between the two first insulating oxide layers, the first insulating nitride layer is deposited onto the first dielectric layer; etching the first stacked structure to form a plurality of first trenches in which the conductive plugs are exposed; disposing a conductive metal material within each of the first trenches to cover the conductive plugs; disposing a solid first conducting cylindrical structure within each of the first trenches, the first conducting cylindrical structures are deposited over the conductive metal materials; forming a second stacked structure on the first stacked structure, the second stacked structure includes a second dielectric layer and a second insulating nitride layer from bottom to top; etching the second stacked structure to form a plurality of second trenches in which the first conducting cylindrical structures are exposed; and disposing a solid second conducting cylindrical structure within each of the second trenches, the second conducting cylindrical structures are deposited over the first conducting cylindrical structures.