Patent ID: 6912673

Claim:
A semiconductor chip having a Bus Analyzer Unit (“BAU”) for trace analysis on both a global bus and an I/O bus of the semiconductor chip, said BAU comprising: a) a global bus trace unit including: i) a global bus trace memory configured to store trace data from the global bus; ii) a global bus trace control logic in electrical communication with the global bus trace memory and configured to transfer trace data from the global bus trace memory to a first circular buffer; iii) a global bus address register in electrical communication withe the global trace memory and configured to identify an available block of memory where trace data may be written to the first circular buffer; and iv) a first pair of registers in electrical communication with the global bus address register and configured to identify start and end addresses of the first circular buffer, wherein the first pair of registers may be programmed to provide a variably-sized first circular buffer; and b) an I/O bus trace unit including: i) an I/O bus trace memory configured to store trace data from the I/O bus; ii) an I/O bus trace control logic in electrical communication with the I/O bus trace memory and configured to transfer trace data from the I/O bus trace memory to a second circular buffer; iii) an I/O bus address register in electrical communication with the I/O bus trace memory and configured to identify an available block of memory where trace data may be written to the second circular buffer; and iv) a second pair of registers in electrical communication with the I/O bus address register and configured to identify start and end addresses of the second circular buffer, wherein the second pair of registers may be programmed to provide a variably-sized second circular buffer.