Patent ID: 7863671

Claim:
A NAND type flash memory device comprising: a source select transistor, a plurality of memory cells, and a drain select transistor over a semiconductor substrate; a first conductive layer for floating gate formed over the semiconductor substrate of the source and the drain select transistors, and the plurality memory cells; a dielectric layer formed over the floating gate of the source and the drain select transistors, and the plurality memory cells; an opening formed by etching the dielectric layer to partially expose an upper surface of the first conductive layer for floating gate of the source and the drain select transistors; a low resistance layer formed over inner sidewalls and a bottom of the opening; a second conductive layer filling openings over the low resistance layer; and a third conductive layer for control gate is formed over the dielectric layer, the low resistance layer and the second conductive layer of the source and drain select transistors, and over the dielectric layer of the plurality of memory cells, wherein the first conductive layer for floating gate is electrically connected to the third conductive layer for control gate by the second conductive layer and the low resistance layer, and wherein a top surface of the floating gate is in contact with a bottom surface of the second conductive layer, and a bottom surface of the control gate is in contact with a top surface of the second conductive layer.