Patent ID: 8872256

Claim:
A three-dimensional (3D) semiconductor memory device comprising: a stack structure including a plurality of gate patterns and a plurality of insulating patterns which are stacked alternately and vertically on a substrate, the stack structure having a sidewall including a plurality of enlarged regions recessed laterally; a channel structure having a first sidewall adjacent to the sidewall of the stack structure and connected to the substrate; and a data storage layer disposed between the stack structure and the channel structure and covering the sidewall of the stack structure, wherein the plurality of enlarged regions are each defined by two insulating patterns of the plurality of insulating patterns and a gate pattern of the plurality of gate patterns, the two insulating patterns being vertically adjacent to each other and the gate pattern being disposed between the two insulating layers, and wherein the channel structure has a second sidewall adjacent to the plurality of enlarged regions, wherein the second sidewall is vertically in parallel to the first sidewall, wherein the second sidewall is vertically flat with no protrusions toward the stack structure.