Patent ID: 8110916

Claim:
A chip package structure, comprising: a chip module comprising a chip, wherein the chip includes an upper surface, a side surface, and an active surface opposite the upper surface of the chip; a plurality of pre-patterned structures disposed around the chip, wherein each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface; a filling material layer that encapsulates the chip and the plurality of pre-patterned structures, wherein: the filling material layer encapsulates the upper surface of the chip, the side surface of the chip, the upper surface of each of the plurality of pre-patterned structures, and the side surface of each of the plurality of pre-patterned structures; the filling material layer includes a second surface; and the active surface, the first surface of each of the plurality of pre-patterned structures, and the second surface are substantially co-planar; and a redistribution layer disposed on the active surface, the first surface of each of the plurality of pre-patterned structures, and the second surface, wherein the redistribution layer electrically connects the chip and the circuit in each of the plurality of pre-patterned structures.