Patent ID: 8589747

Claim:
An integrated circuit comprising: A. an input pad; B. first core circuitry having: i. a first data input lead coupled to the input pad; ii. a first data output lead; iii. first functional circuitry having a functional input formed of an input buffer circuit having an input coupled to the first data input lead, a functional output formed of an output buffer circuit having an output coupled to the first data output lead, and first parallel scan paths, each scan path having a serial input; iv. first scan distributor circuitry having a serial input coupled to the first data input lead, a serial output, and parallel outputs connected to the serial inputs of the first parallel scan paths; and v. a first distributor output buffer having an input connected to the serial output of the first scan distributor circuitry, an output coupled to the first data output lead, and a control input that selectively disconnects the buffer input from the buffer output; C. second core circuitry having: i. a second data input lead; ii. second functional circuitry having a functional input formed of an input buffer circuit having an input coupled to the second data input lead, and second parallel scan paths, each scan path having a serial input; iii. second scan distributor circuitry having a serial input coupled to the second data input lead, a serial output, and parallel outputs connected to the serial inputs of the second parallel scan paths; and D. multiplexer circuitry having a first input coupled to the first data output lead, a second input, and an output coupled to the second data input lead.