Patent ID: 7925013

Claim:
A system of digital data encryption in a digital device, comprising: generating an inaccurate clock signal that oscillates at different frequencies; an integrated encryption key generator generating a plurality of encryption keys based upon the input received from an inaccurate timing source; and based on the generated clock signal and a pseudorandom bit pattern generated in a linear feedback shift register each time the digital device is reset; a data buffer; an input/output register that interfaces with memory of the digital device; a control pad coupled to the input/output register; and a memory controller that directs digital data from the memory to the data buffer with the digital data passing through the encryption key generator prior to entering the input/output register, wherein the integrated encryption key generator is coupled between the data buffer and the input/output register, and the integrated encryption key generator, the data buffer, the input/output register, the control pad and the memory controller are formed on a single substrate and are accessed through the control pad.