Patent ID: 8107570

Claim:
A phase correction circuit comprising: A. a first input lead carrying a first signal R j 1 ; B. a second input lead carrying a second signal R j 2 ; C. first multiplier circuitry having one input connected to the first lead, a second input receiving a complex conjugate of a first Rayleigh fading parameter estimate signal a j 1 *, and an output; D. second multiplier circuitry having one input connected to the second lead, a second input receiving the complex conjugate of the first Rayleigh fading parameter estimate signal a j 1 *, and an output; E. first complex conjugate circuitry having an input connected to the first lead and an output; F. second complex conjugate circuitry having an input connected to the second lead and an output; G. third multiplier circuitry having one input connected to the output of the first complex conjugate circuitry, a second input receiving a second Rayleigh fading parameter estimate signal a j 2 , and an output; H. fourth multiplier circuitry having one input connected to the output of the second complex conjugate circuitry, a second input receiving the second Rayleigh fading parameter estimate signal a j 2 , and an output; I. first summing circuitry having a first positive input connected to the output of the first multiplier circuitry, a second positive input connected to the output of the fourth multiplier circuitry, and an output providing a first symbol estimate signal; and J. second summing circuitry having a first negative input connected to the output of the third multiplier circuitry, a second positive input connected to the output of the second multiplier circuitry, and an output providing a second symbol estimate signal.