Patent ID: 7913049

Claim:
A secure non-volatile memory device, comprising: a silicon semiconductor substrate including active circuitry fabricated on a logic plane of the silicon semiconductor substrate; a memory layer in contact with and fabricated directly above the silicon semiconductor substrate; at least one two-terminal cross-point memory array embedded in the memory layer, each array including a plurality of first conductive array lines that are oriented orthogonally to a plurality of second conductive array lines, the plurality of first and second conductive array lines are electrically coupled with at least a portion of the active circuitry; a plurality of two-terminal memory elements operative to retain stored data, each memory element positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and including first and second terminals electrically coupled with the first and second conductive array lines respectively, each memory element including an electrolytic tunnel barrier and a conductive metal oxide including mobile oxygen ions, the conductive metal oxide and the electrolytic tunnel barrier are in contact with each other and are electrically in series with the first and second terminals; a memory storage controller in electrical communication with the at least one two-terminal cross-point memory array and configured to control data operations access to the at least one two-terminal cross-point memory array; and a device access determinator in electrical communication with the memory storage controller and a validation signal, the device access determinator configured to determine a geographical location of the memory layer, to detect a validation signal, and to grant access to the memory storage controller as a function of the validation signal.