Patent ID: 7449378

Claim:
A method of forming a semiconductor structure comprising: providing a structure including at least one trench isolation region located within a semiconductor substrate, said at least one trench isolation region including an oxide liner in contact with said semiconductor substrate and lining walls of a trench located within said semiconductor substrate, a nitride liner on said oxide liner and a dielectric material on said nitride liner; forming at least one gate region on said semiconductor substrate, said at least one gate region including at least an inner oxide spacer in contact with a gate conductor and a gate dielectric of said gate region; recessing the semiconductor substrate adjacent to said at least one trench isolation and said at least one gate region, wherein said recessing forms a cavity in said semiconductor substrate that exposes a portion of the oxide liner of said at least one trench isolation region and a portion of said inner oxide spacer; removing said exposed portion of the oxide liner, while forming a recess in said exposed portion of said inner oxide spacer; and filling said cavity with a stress inducing material, said stress inducing material is faceted at said inner oxide spacer, but not at an edge of the at least one trench isolation region.