Patent ID: 7948466

Claim:
A dual resolution circuit for supporting dual resolution display modes in a display apparatus, comprising: a shift register stage, receiving a start pulse and at least four clock signals, generating a plurality of intermediate scan signals; a dual resolution switch, controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals; and a logic circuit stage, including a plurality of NAND gates, wherein each of the NAND gates directly receives an enablement signal and receives one of the intermediate scan signals from the shift register stage and one of the switched intermediate scan signals from the dual resolution switch, and performing logic operations on the enablement signal, the intermediate signals and the switched intermediate scan signals to generate a plurality of output scan signals for performing dual resolution display modes, wherein: the dual resolution display modes includes a normal resolution display mode and a half resolution display mode, each NAND gate corresponding to a separate one of the plurality of intermediate scan signals, the plurality of intermediate scan signals include first, second and third intermediate scan signals, and the NAND gate corresponding to the first intermediate scan signal performs logic operations on the enablement signal, the first intermediate signal, and either the second intermediate scan signal or the third intermediate scan signal that is switched from the dual resolution switch to generate the output scan signals depending on which of the normal resolution display mode or the half resolution display mode.