Patent ID: 8076753

Claim:
A semiconductor device comprising: a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities for controlling a threshold voltage wherein the first MOS device has a characteristic that is similar to that of a depletion mode MOS device; a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of added impurities in addition to the impurities formed on the surface of the p-type substrate for controlling a threshold voltage wherein the second MOS device has a characteristic that is similar to that of a depletion mode MOS device; and a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device, wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers, wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively.