Patent ID: 6851044

Claim:
An instruction execution device for use in a processor with an exception routine, the instruction execution device comprising: an instruction pipeline for producing a first result for a first instruction, wherein the exception routine interrupts the instruction pipeline at random intervals; a register file connected to the instruction pipeline, the register file including at least a first write port for storing the first result; a bypass circuit connected to the instruction pipeline, the bypass circuit for allowing access to the first result; means for indicating whether the first result is used by only a second instruction that includes determining whether an instruction subsequent to the second instruction in the pipeline designates a same destination address for storage in the resister file as that of the first result; a register file control connected to the instruction pipeline and the register file, the register file control for preventing the first result from being stored in the write port when the first result has been accessed via the bypass circuit and is used by only the second instruction; a buffer that is not a part of the register file, said buffer only for storing the first result from the pipeline after being accessed by the second instruction via the bypass circuit; and a buffer control for writing the first result from the buffer to the register file when an exception occurs.