Patent ID: 7630244

Claim:
A method of operating a memory device including a memory cell array having a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor, wherein the string selection transistor is coupled between the string and a bit line, wherein the ground selection transistor is coupled between the string and a common source line, and wherein each memory cell transistor includes a floating gate between a control gate electrode and a semiconductor substrate and source/drain regions of the semiconductor substrate on opposite sides of the control gate electrode, the method comprising: responsive to an erase command, erasing the memory cell transistors of the string; and responsive to the erase command and after erasing the memory cell transistors of the string, discharging electrical charge from the source/drain regions of the memory cell transistors through the ground selection transistor to the common source line and/or through the string selection transistor to the bit line.