Patent ID: 7259048

Claim:
A process for fabricating a vertical silicon-on-insulator MOSFET comprising: forming a first contact region selected from the group consisting of a source contact region and a drain contact region of a semiconductor device in a semiconductor substrate; forming a multilayer stack comprising at least three layers of material over the first contact region, wherein the second layer is interposed between the first and the third layers, and wherein the first layer is proximate the first contact region; forming a window in the at least three layers of material, wherein the window does not extend into the first contact region; forming a semiconductor material along at least one vertical wall region of the window, wherein the semiconductor material comprises a first, a second and a third doped region, and wherein the first doped region is adjacent the first layer and is doped a first conductivity type and further is in electrical contact with the first contact region, and wherein the second doped region is adjacent the second layer and is doped a second conductivity type, and wherein the third doped region is adjacent the third layer and is doped the first conductivity type; forming a first insulating surface adjacent the first doped region and extending toward the center of the window; forming a second insulating surface adjacent the third doped region and extending toward the center of the window; forming a conductive plug in the remaining open volume of the window, wherein a portion of the plug is in electrical contact with the second doped region on the surface of the second doped region facing the center of the window; removing the second layer, thereby exposing at least a portion of the second doped region; forming a gate dielectric layer in contact with the second doped region; and forming a gate in contact with the gate dielectric layer.