Patent ID: 7233178

Claim:
An integrate circuit comprising: a first node having a first supply voltage level; a first level shift circuit coupled between the first node and a first path, the first level shift circuit configured to output a signal at a second supply voltage level, and the first path including an even number of inverter stages; a second level shift circuit coupled between the first node and a second path, the second level shift circuit configured to output a signal at the second supply voltage level, and the second path including an odd number of inverter stages; a PMOS transistor and an NMOS transistor coupled in series between a second node having the second supply voltage level and a reference voltage; a gate of the PMOS transistor coupled to the first path; a gate of the NMOS transistor coupled to the second path; an I/O pad coupled between the PMOS transistor and the NMOS transistor, the I/O pad being in a high impedance state during a power-on period when the first supply voltage level is powered up before the second supply voltage level.