Patent ID: 6877103

Claim:
A timing adjustment device for adjusting the timing at a bus interface and preventing any read/write error due to timing deviation, the adjustment device comprising: a cycle protocol device for generating a special read/write cycle signal that links up with devices having connection with the bus interface; a phase lock loop device coupled to the bus interface for receiving an internal clocking signal, increasing/decreasing the amount of phase shift in the internal clocking signal to become a clocking signal for the bus interface to drive a special read/write test sample to a bus and trigger the reception of data on the bus; a special pattern device coupled to the cycle protocol device, wherein the special pattern device generates the special read/write test samples according to the special read/write cycle signal to provide read/write tests of the bus interface and check the bus interface for the correctness of data read/write operation; and an add/subtract device coupled to the phase lock loop device for setting the amount of phase shift in the phase lock loop device.