Patent ID: 7461199

Claim:
A memory system, comprising: a memory, including a plurality of independently controllable non-volatile data storage sections each having a plurality of memory cells; a corresponding plurality of data registers associated with a respective data storage section; and write circuitry whereby data content held in a given data register can be programmed into the corresponding data storage section; and a controller for controlling the transfer of data between a host to which the memory system is connected and the data storage sections, including: a plurality of data buffers, and a data bus whereby data content can be transferred from the data buffers to the data registers, wherein the memory system can perform a plurality of overlapping data write operations, a write operation for a data set including the sequential sub-operations of: a) transferring the data set from the host to one of the data buffers; b) transferring said data set from said one of the data buffers though the data bus to one of the data registers; and c) programming the data set from said one of the data registers into the corresponding one of the data storage sections, wherein sub-operations a) and b) of one write operation are performed concurrently with sub-operations b) and c), respectively, of a preceding overlapping write operation.