Patent ID: 7124338

Claim:
A method of testing a programmable logic device (PLD), the PLD comprising an interconnect line and programmable first, second, and third buffers each programmably driving the interconnect line, the PLD further comprising first, second, and third memory elements associated with the first, second, and third buffers, respectively, the method comprising: configuring the PLD with a first configuration wherein a signal path is provided from an input terminal to the first memory element, the first buffer, the interconnect line, the second memory element, the third memory element, and an output terminal, in the stated order, and wherein the first buffer is enabled and the second and third buffers are disabled; running a first test pattern on the PLD by applying a first test input signal to the input terminal and monitoring a resulting first test output signal on the output terminal; partially reconfiguring the PLD with a second configuration wherein the signal path is severed between the interconnect line and the second memory element, wherein new segments are added to the signal path between the first memory element and the second memory element and between the interconnect line and the third memory element, and wherein the first buffer is disabled and the second buffer is enabled; and running a second test pattern on the PLD by applying a second test input signal to the input terminal and monitoring a resulting second test output signal on the output terminal.