Patent ID: 7968917

Claim:
A semiconductor memory device comprising: a first wiring layer for carrying out wiring in at least a first direction; a second wiring layer that is layered on the first wiring layer and is for carrying out wiring in a second direction intersecting the first direction; a third wiring layer that is layered on the second wiring layer and is for carrying out wiring in the first direction; a memory array region at which a plurality of memory cells are formed so as to be arrayed at the first wiring layer, the memory array region being formed at a region at which the first wiring layer, the second wiring layer and the third wiring layer can be used in wiring of the plurality of memory cells; a first gate array region at which a plurality of unit cells are formed so as to be arrayed at the first wiring layer, the first gate array region being formed at a region at which the first wiring layer, the second wiring layer and the third wiring layer can be used in wiring of the plurality of unit cells; and a second gate array region at which a plurality of unit cells are formed so as to be arrayed at the first wiring layer, the second gate array region being formed at a region at which two wiring layers that are the first wiring layer and the second wiring layer can be used in wiring of the plurality of memory cells, and the plurality of unit cells are arrayed so as to be separated at an interval needed for placement, by using the first wiring layer, of wiring that should be placed by using the third wiring layer.