Patent ID: 8173541

Claim:
A method for manufacturing a semiconductor structure comprising: forming a chip carrier substrate by: forming a first trench having a first width and a first depth and a second trench having a second width and a second depth in a substrate, wherein said second width is greater than said first width and said second depth is greater than said first depth, and said first and second trenches extend from a front surface of said substrate into said substrate, depositing a stack of a first capacitor plate layer, a capacitor dielectric layer, and a second capacitor plate layer in that order within said first trench and said second trench, and planarizing a back surface of said substrate, wherein said first trench is spaced from a planarized back surface of said substrate and a portion of said second capacitor plate layer within said second trench is physically exposed at said planarized back surface of said substrate; forming at least one solder layer on a surface of said portion of said second capacitor plate layer; and affixing at least one semiconductor chip to said chip carrier substrate by connecting said at least one semiconductor chip at least to said portion of said second capacitor plate layer through said at least one solder layer.