Patent ID: 7071100

Claim:
A method for forming a copper dual damascene with improved barrier layer thickness uniformity and improved electrical resistivity comprising the steps of: providing a substrate comprising upper and lower dielectric insulating layers separated by a middle etch stop layer comprising multiple layers; forming a dual damascene opening by first forming a via extending through a thickness of the upper and lower dielectric insulating layers; then forming an upper trench line portion extending through the upper dielectric insulating layer thickness and partially through the middle etch stop layer thickness including an uppermost layer comprising the middle etch stop layer; then blanket depositing a barrier layer comprising at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; then removing a bottom portion of the barrier layer to reveal an underlying conductive area according to a plasma etching process, said plasma etching process further improving said barrier layer thickness uniformity along trench and via sidewalls; and, then filling the dual damascene opening with copper to provide a substantially planar surface.