Patent ID: 7381621

Claim:
A method of fabricating a high voltage MOSFET, comprising: epitaxially growing an impurity region on a semiconductor substrate; ion-implanting first impurities of a second conductivity type into the impurity region using a first photo resist pattern as a first implant mask; then ion-implanting first impurities of a first conductivity type into the impurity region using a second photo resist pattern as a second implant mask; then performing a first heat treatment to form third and fourth diffusion regions from the first impurities of the second conductivity type, a well region from the first impurities of the first conductivity type, and regions where the well region overlaps with the third and fourth diffusion regions by diffusion; then forming a gate oxide layer on the well region; then forming a gate electrode on the gate oxide layer; then ion-implanting second impurities of the second conductivity type into the impurity region using the gate electrode as an implant mask; and then performing a second heat treatment to form first and second diffusion regions from diffusion of the second impurities of the second conductivity type.