Patent ID: 7033709

Claim:
A method for manufacturing a mask for integrated circuit devices, the method comprising: providing a mask including a surface region, the surface region including a plurality of spaced regions forming an array configuration, each of the spaced regions being separated from each other by an opaque region to form the array configuration and being characterized by a dimension no greater than 0.25 microns; selectively coding one or more of the spaced regions to define a masked read only memory (ROM) structure, each of the coded spaced regions including a structure, the structure causing an interference with light from a light source; illuminating the surface region of the mask with the light source to allow the light to traverse through each of the spaced regions, whereupon the selectively coded one or more spaced regions transmits a lower light intensity to a photoresist material than a light intensity on the photoresist material from light illuminated on the photoresist material through the spaced regions free from the one or more codings; and developing the photoresist material to selectively remove portions of the photoresist material only in the portions where light transmitted through the spaced regions free from coding while the portions of the photoresist material corresponding to the one or more coded regions remain intact.