Patent ID: 7473102

Claim:
An electronic apparatus, comprising: a first level package structure comprising a package substrate, one or more IC (integrated circuit) chips mounted on a first surface of the package substrate, and a first pattern of I/O contacts with pitch P 1 formed on a second surface of the package substrate opposite the first surface; a second level package structure comprising a second pattern of I/O contacts with pitch P 2 , wherein P 2 is not equal to P 1 ; and an LGA (land grid array) interposer disposed between the first and second level package structures, wherein the LGA interposer provides space transform electrical interconnections between the first pattern and second pattern of I/O contacts, and further comprising a dummy contact formed on at least a first or second surface of the LGA interposer and aligned to an LGA contact on an opposing surface of the LGA interposer.