Patent ID: 8097531

Claim:
A method of manufacturing a charge trap type memory device, the method comprising: forming a tunnel insulating layer on a substrate that has an isolation layer and a stepped active region; forming a charge-trapping layer on the tunnel insulating layer; forming an oxidation mask on the charge-trapping layer, the oxidation mask being configured to allow oxygen plasma ions to pass through to a portion of the charge-trapping layer over the isolation layer, wherein the oxidation mask is formed to have a portion over the isolation layer that is less thick than other portions of the oxidation mask to allow the oxygen plasma ions to pass therethrough and be implanted in the portion of the charge-trapping layer over the isolation layer; converting the portion of the charge-trapping layer over the isolation layer into a charge-blocking pattern having a vertical side profile using an anisotropic oxidation process; forming a blocking layer on the charge-trapping layer; and forming gate electrodes on the blocking layer, the gate electrodes being electrically isolated from each other by a trench.