Patent ID: 7948328

Claim:
An oscillator comprising: a reference voltage generator generating a reference voltage; a first output voltage generator generating a first output voltage going high or low in response to the reference voltage and a second internal clock signal, wherein the first voltage output generator comprises: a first voltage generator generating a first applied voltage in response to the second internal clock signal; a first comparator comparing the first applied voltage with the reference voltage to generate the first output voltage; a first pull-up circuit pulling up an output of the first comparator in response to the second internal clock signal to generate the first output voltage: and a first initializing circuit initializing the output of the first comparator; a second output voltage generator generating a second output voltage complementary to the first input signal in response to the reference voltage and a first internal clock signal complementary to the second internal clock signal, wherein the second voltage output generator comprises: a second voltage generator generating a second applied voltage in response to the first internal clock signal; a second comparator comparing the second applied voltage with the reference voltage to generate the second output voltage; a second pull-up circuit pulling up an output of the second comparator in response to the first internal clock signal to generate the second output voltage, wherein one of the first and second output voltages going high is pulled up by a corresponding one of the first and second pull-up circuits before being applied to the logic combination circuit before the other one of the first and second output voltages going low; and a second initializing circuit initializing the output of the second comparator; and a logic combination circuit logically combining the first and second output voltages to generate the first and second internal clock signals, wherein one of the first and second output voltages going high is provided to the logic combination circuit before the other one of the first and second output voltages going low, the respective outputs of the first and second comparators are initialized at complementary logic levels by the first and second initializing circuits, and the first and second pull-up circuits are configured to operate without an applied power supply voltage following initialization of the first and second comparators by the first and second initializing circuits.