Patent ID: 7089404

Claim:
A method of scheduling and executing instructions comprising: a) accessing a sequence of instructions comprising: a first memory operation that involves a first address range; a second memory operation that involves at least a portion of said first address range; and a third memory operation intervening said first and second memory operations, wherein it is not known whether said third memory operation involves an address within said first address range, wherein at least one of said first through third memory operations comprises a store operation; b) eliminating said second memory operation from said sequence of instructions; c) adding information to said third memory operation to allow determination of said first address range, wherein said information comprises a mask allowing determination of which of a plurality of registers hold protected addresses; d) executing said sequence of instructions with said second memory operation eliminated; and e) determining, during said executing, if said third memory operation involves an address within said first address range, and if so, raising an exception and re-executing the sequence of instructions including said second memory operation.