Patent ID: 7992052

Claim:
A data processing system comprising: a data processor for executing a plurality of data processing instructions; a memory coupled to the data processor for storing and providing information to the data processor; debug circuitry coupled to the data processor for generating debug messages including address translation trace messages; a memory management unit coupled to the debug circuitry, data processor and the memory, the memory management unit comprising a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms, wherein: the debug circuitry comprises: message generation circuitry coupled to the memory management unit for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information, the branch history information comprising a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken, and the instruction count information being a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.