Patent ID: 8242802

Claim:
An apparatus for enabling a multi-core environment on a bus, the bus requiring active termination impedance control, the apparatus comprising: a plurality of processor cores, coupled to a single substrate via a plurality of signals, wherein transmission line location of each of said signals is a function of physical length of traces that route said signals through said single substrate to each of said plurality of processor cores, said each of said plurality of processor cores comprising: a location array, configured to generate a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, wherein said locations comprise either an internal location or a bus end location; and a plurality of drivers, coupled to said plurality of location signals, each comprising one of said corresponding plurality of nodes, and each configured to control how said one of said corresponding plurality of nodes is driven responsive to a state of a corresponding one of said plurality of location signals, each of said plurality of drivers comprising: location-based multi-core logic, configured to enable pull-up logic and first pull-down logic if said state indicates said bus end location, and configured to disable said pull-up logic and enable said first pull-down logic and second pull-down logic if said state indicates said internal location.