Patent ID: 8487652

Claim:
A method of manufacturing an integrated circuit, the method comprising: selecting a programmable logic device to be formed on a chip; selecting a dedicated device to be formed on the chip; selecting an interface circuit to be formed on the chip to provide the interface connections between the programmable logic device and the dedicated device; the interface circuit comprising a plurality of interface buffer circuits; determining a number of input interface connections to the dedicated device from the programmable logic device and a number of output interface connections from the dedicated device to the programmable logic device; adjusting the routing of the conductors to be formed in a layer of the integrated circuit for a subset of the plurality of interface buffer circuits based on the determined number of at least one of the input interface connections and the output interface interconnects, wherein the subset of the plurality of interface buffer circuits is the same as the remainder of the plurality of interface buffer circuits except for the routing of the conductors.