Patent ID: 7782674

Claim:
A NAND architecture non-volatile memory device, comprising: a NAND memory array having a plurality of non-volatile memory cells arranged in a plurality of NAND strings; and circuitry for control and/or access of the plurality of non-volatile memory cells of the NAND memory array; wherein the NAND architecture non-volatile memory device is adapted to sense a threshold voltage of a selected memory cell of a NAND memory cell string of the NAND memory array by, coupling the NAND string to a bit line and a source line, applying an elevated source voltage (Vsource) to the source line, applying a pass voltage (Vpass) to one or more word lines coupled to control gates on one or more unselected memory cells of the NAND string, applying a read gate voltage (Vg) to a word line coupled to a control gate of the selected memory cell, and sensing a voltage expressed on the coupled bit line indicative of the read gate voltage (Vg) minus the threshold voltage (Vt) of the selected memory cell of the NAND memory cell string.