Patent ID: 7064616

Claim:
A numeric counter oscillator comprising: a quotient accumulator, the quotient accumulator having a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output, the output adapted for transmitting an output value OUT representing an accumulated quotient sum, the multi-bit output incrementing in response to each reference clock period; a remainder accumulator, the remainder accumulator having programmable inputs for receiving respective REMAINDER and DIVISOR values, a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer, the remainder accumulator further comprising: a) an arithmetic circuit having an output representing accumulated remainder values; and b) circuitry having a first input for receiving a programmed divisor value, and a second input for receiving the output of the arithmetic circuit, the circuitry operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output of the arithmetic circuit exceeds a value dependent on the programmed divisor value.