Patent ID: 7020037

Claim:
A nonvolatile semiconductor memory device comprising: a main memory array comprising a plurality of arranged memory cells each having a nonvolatile memory element; at least one reference memory cell having the nonvolatile memory element; an address selection circuit which selects a particular memory cell from the main memory array; a readout circuit which reads data stored in the memory cell selected by the address selection circuit, by applying a predetermined electric stress to the selected memory cell and the reference memory cell so that currents corresponding to the respective storage states may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference memory cell; and a program circuit which programs data in the memory cell selected by the address selection circuit, wherein the readout circuit commonly uses the reference memory cell set in the same storage states at the time of normal readout and at the time of readout for program verification, and when the predetermined electric stress is applied to the programmed memory cell and the reference memory cell at the time of the readout for the program verification, the readout circuit sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.