Patent ID: 7636356

Claim:
An apparatus comprising: a plurality of network interfaces to exchange packets of data with a network; a processor interface to exchange at least some of the packets of data with a processor; a forwarding engine to transfer the packets of data among the interfaces; a memory to store first associations between the interfaces and at least one flooding domain; a control circuit to remove the processor interface from all of the first associations; a classifier to assign one of a plurality of processor codes to each of the packets of data received by one of the network interfaces and addressed to the processor interface, wherein the processor code assigned to each of the packets of data represents a protocol of the packet of data and comprises an allowance flag; wherein the memory stores second associations between the network interfaces and the protocols; an allowance circuit to set the allowance flag in the processor code assigned to each of the packets of data when the packet of data comprises the protocol associated with the network interface that is the source of the packet of data, and to clear the allowance flag otherwise; and a processor interface egress circuit to receive packets of data addressed to the processor interface, to drop the received packets of data having a first of the processor codes comprising the allowance flag that is clear, and to transfer the received packets of data having a second of the processor codes comprising the allowance flag that is set to the processor interface.