Patent ID: 7928572

Claim:
A composite semiconductor device, comprising: a substrate; a plurality of circuits formed on said substrate; one or more wiring layers, each including a plurality of wiring patterns connected to circuits of the plurality of circuits, a plurality of dummy patterns electrically isolated from the plurality of circuits, and an interlayer dielectric film that is spin-coated directly onto the wiring patterns and onto the dummy patterns, and that is a spin-coated layer, the dummy patterns being formed in areas where the plurality of wiring patterns are absent and lying substantially in a plane in which the wiring patterns lie; and a semiconductor thin film layer that includes semiconductor device elements and that is disposed on an upper most surface of the one or more wiring layers wherein the plurality of the wiring patterns, the interlayer dielectric thin film, and the plurality of dummy patterns have respective thicknesses, wherein a thickness is the thickness of the plurality of wiring patterns plus the thickness of the interlayer dielectric thin film on the plurality of wiring patterns in each wiring layer of the one or more wiring layers, a second thickness is the thickness of the interlayer dielectric thin film at the areas where the plurality of wiring patterns are not formed in each wiring layer of the one or more wiring layers; and wherein the thickness of the plurality of dummy patterns is substantially equal to a difference between the first thickness and the second thickness.