Patent ID: 7111216

Claim:
A scan controller for controlling scan path testing of a logic block within a target device having a serial programmable interface providing serial data in, serial clock and mode control pins, wherein the scan controller uses said serial data in, serial clock and mode control pins of the serial programmable interface, and when the serial programmable interface is active, the controller uses the mode control pin in a first state to instruct the serial programmable interface to shift data and in a second state to instruct the serial programmable interface to latch data, and the serial programmable interface is responsive to an instruction to make the scan controller active and to disable the programmable interface itself and, when the scan controller is active, the mode control pin is used to control transitions to a shift state when scan registers are to shift data and a capture state when scan registers are to latch data, and the scan controller is arranged to detect a predetermined signal indicative of the end of the test and to place the scan controller in a state where the scan controller re-enables operation of the serial programmable interface.