Patent ID: 7725689

Claim:
A multiprocessing system, comprising: a hardware multithreading microprocessor, comprising: a first plurality of thread contexts (TCs), each having a program counter and a general purpose register set; and a translation lookaside buffer (TLB), shared by said first plurality of TCs rather than being replicated for each of said first plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads; and a multiprocessor operating system (OS), said OS comprising a data structure having an entry for each of said first plurality of TCs, each said entry configured to store a first item of information describing capabilities of at least one hardware resource shared by said first plurality of TCs and a second item of information associated with a corresponding one of said first plurality of TCs such that a value of said first item of said data structure corresponding to one of said first plurality of TCs is the same as a value of said first item of said data structure corresponding to each other of said first plurality of TCs while a value of said second item of said data structure corresponding to said one of said first plurality of TCs is different from a value of said second item of said data structure corresponding to said each other of said first plurality of TCs, said OS configured to manage said TLB, and to schedule execution of both said operating system-privileged threads and said user-privileged threads on said first plurality of TCs, wherein TLB entries loaded as a result of a thread executing on one of said first plurality of TCs are valid and usable on any other of said first plurality of TCs to which said thread subsequently migrates.