Patent ID: 6852592

Claim:
A method for fabricating a semiconductor device comprising: forming a plurality of first plugs that extend through a first inter-layer insulation layer disposed on a substrate with the first plugs contacting the substrate; forming an attack barrier layer on the first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs and the attack barrier layer; forming a conductive pattern on a first portion of the first plugs by selectively etching the second inter-layer insulation layer and the attack barrier layer leaving a second portion of the first plugs not in contact with the conductive pattern; and forming a contact holes that individually expose surfaces of second portion of the first plugs that are not in contact with the conductive pattern by etching selectively the second insulation layer with use of dry-type and wet-type etch processes, wherein the attack barrier layer prevents an attack or erosion of the first interlayer insulation layer in contact with the first plug during the wet-type etch process for forming the contact holes.