Patent ID: 7829430

Claim:
A method for fabricating a semiconductor device, comprising: forming shallow trench isolation structures to define electrically isolated active regions and dummy moats on a substrate; including: selectively removing portions of the substrate to form trenches; forming a layer of insulating material over the substrate including in the trenches; and removing portions of the insulating material outside of the trenches; forming a layer of silicide-blocking material to selectively cover at least some portions of at least some of the dummy moats, leaving at least some portions of at least some of the active regions uncovered; forming a layer of siliciding material at least over the covered portions of the dummy moats and over the uncovered portions of the active regions; reacting the layer of siliciding material with the uncovered portions of the active regions, with the layer of silicide-blocking material serving to prevent reaction with the covered portions of the dummy moats; and removing unreacted portions of the layer of siliciding material.