Patent ID: 7525151

Claim:
An integrated circuit comprising: a semiconductor wafer that includes a plurality of semiconductor devices, said plurality of semiconductor devices including a CMOS and a first vertical conduction DMOS and a second vertical conduction DMOS, each vertical conduction DMOS including a gate, one power electrode on one side thereof, and another power electrode on an opposing side thereof, a first insulation wall adjacent said CMOS and said first DMOS and a second insulation wall adjacent said CMOS and said second DMOS and an insulation layer under said CMOS and extending between said first insulation wall and said second insulation wall, wherein said CMOS is disposed between said first DMOS and said second DMOS and insulated from said first DMOS and said second DMOS by an insulation tub comprised of said first insulation wall, said second insulation wall and said insulation layer.