Patent ID: 7446568

Claim:
A receiver start-up compensation circuit comprising: a bias voltage source; a current mirror circuit for providing a current at an output end, the current mirror comprising: a reference current source; a first PMOS transistor including: a source coupled to the bias voltage source; a drain coupled to the reference current source; and a gate coupled to a bias end of the current mirror circuit and the drain of the first PMOS transistor; and a second PMOS transistor including: a source coupled to the bias voltage source; a drain coupled to the output end of the current mirror circuit; and a gate coupled to the bias end of the current mirror circuit; a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on a first control signal received at a control end of the power-down switch; and a compensating unit coupled to the bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit by providing charges at the bias end of the current mirror circuit based on signals received at control ends of the compensating unit, the compensating unit comprising: a fourth PMOS transistor having a source and a drain directly coupled to each other regardless of the status of the first control signal, and a gate coupled to the bias end of the current mirror circuit; a first control switch coupled between the source of the fourth PMOS transistor and the bias voltage source, and including a control end coupled to receive the first control signal for controlling passages between the fourth PMOS transistor and the bias voltage source; and a second control switch coupled between the source of the fourth PMOS transistor and the power-down switch, and including a control end coupled to receive a second control signal for controlling passages between the fourth PMOS transistor and the power-down switch.