Patent ID: 7569803

Claim:
An apparatus comprising: a first input to provide a biasing voltage; a plurality of pixels providing a corresponding plurality of pixel outputs; and a plurality of biasing circuits, each of said plurality of biasing circuits connected to one of said plurality of pixels, wherein each of said biasing circuits comprises: a biasing transistor having a source, a drain, and a gate, the source to receive a pixel output included in the plurality of pixel outputs; a first switch having a first end connected to a first end of a capacitor, and a second end of the first switch connected to a first ground; a second switch having a first end connected to the first input, and having a second end connected to a gate of a biasing transistor and a second end of the capacitor; and a third switch having a first end connected to the first end of the capacitor, and a second end of the third switch connected to the drain of the biasing transistor and a second ground, wherein the first and the second switch are to close and the third switch is to open to set a bias voltage on the capacitor, and wherein said first and said second switches are to open and said third switch is to close when the bias voltage is set on the capacitor.