Patent ID: 8237980

Claim:
A serial interface device comprising: a FIFO portion to which 8 or 12 bit parallel data is written based on a first clock signal; a FIFO reader that reads the parallel data written to the FIFO portion 8 bits at a time based on a second clock signal; a parallel/serial converter that converts the 8-bit parallel data read by the FIFO reader into 1-bit serial data based on a third clock signal; a PLL circuit that produces the third clock signal by multiplying the first clock signal by a factor of 8 or 12; and a frequency divider circuit that produces the second clock signal by dividing a frequency of the third clock signal by 8, wherein a multiplication factor of the PLL circuit is so controlled as to be changed according to a number of bits of the parallel data written to the FIFO portion such that, when the number of bits is 8, the multiplication factor is 8 and, when the number of bits is 12, the multiplication factor is 12, and wherein the FIFO reader operates according to the number of bits of the parallel data written to the FIFO portion, such that when the number of bits is 8, operation is at a frequency equal to a frequency of the first clock signal, and when the number of bits is 12, operation is at a frequency 1.5 times the frequency of the first clock signal, and wherein when a number of bits of the parallel data written to the FIFO portion is 12, the FIFO reader reads 8 bits of a first parallel data at a first pulse of the second clock signal, reads 8 bits of a second parallel data at a second pulse of the second clock signal, and reads 4 residual bits of the first parallel data and 4 residual bits of the second parallel data at a third pulse of the second clock signal.