Patent ID: 7323924

Claim:
A level shifter circuit comprising a first power source; a second power source imparting a potential lower than that of the first power source; a first p-channel transistor, a second p-channel transistor; a third p-channel transistor; a fourth p-channel transistor; a first n-channel transistor; a second n-channel transistor; a first inputting unit for inputting a signal to a gate of the second p-channel transistor; and a second inputting unit for inputting a signal to a gate of the fourth p-channel transistor; wherein each of the first inputting unit and the second inputting unit outputs a signal which is different from that inputted to a gate of the first n-channel transistor or the second n-channel transistor, wherein a source and a drain of the first p-channel transistor are connected to the first power source and a source of the second p-channel transistor respectively, wherein a drain of the second p-channel transistor is connected to a gate of the third p-channel transistor and a drain of the first n-channel transistor, wherein a source of the first n-channel transistor is connected to the second power source, wherein a source and a drain of the third p-channel transistor are connected to the first power source and a source of the fourth p-channel transistor respectively, wherein a drain of the fourth p-channel transistor is connected to a gate of the first p-channel transistor and a drain of the second n-channel transistor, wherein a source of the second n-channel transistor is connected to the second power source, wherein a signal is inputted to the first inputting unit and a gate of the first n-channel transistor, and the first inputting unit outputs the signal after changing a phase and raising an amplitude voltage thereof, and wherein a signal is inputted to the second inputting unit and a gate of the second n-channel transistor, and the second inputting unit outputs the signal after changing a phase and raising an amplitude voltage thereof.