Patent ID: 7642650

Claim:
A semiconductor device, comprising: a substrate; a first multilayer interconnection structure formed over said substrate; and a second multilayer interconnection structure formed over said first multilayer interconnection structure, wherein said first multilayer interconnection structure includes a first interlayer insulation film and a first interconnection layer included in said first interlayer insulation film; said second multilayer interconnection structure includes a second interlayer insulation film and a second interconnection layer included in said second interlayer insulation film, said first multilayer interconnection structure including a pillar vertically extending straight from a surface of said substrate and reaching at least said second multilayer interconnection structure, said pillar being formed in a region of said substrate right underneath an electrode pad so as to support stress during wire bonding, said first interconnection layer being formed so as to avoid said pillar, and said pillar being provided on a device isolation structure on said substrate, wherein said first interlayer insulation film has a first Young modulus and said second interlayer insulation film has a second, larger Young modulus than said first Young modulus.