Patent ID: 8473878

Claim:
A computer-implemented method for determining a modified target pattern associated with an integrated-circuit design, comprising: receiving at least a portion of a target pattern associated with the integrated-circuit design, wherein the target pattern includes polygons that represent features in the integrated-circuit design; determining a set of polygon parameters in the modified target pattern, wherein the set of polygon parameters include polygon positions in the modified target pattern and areas of the polygons; calculating, using a computer, a mask pattern that can be used in a photolithographic process to fabricate the modified target pattern on a semiconductor die, wherein the mask pattern is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path, and the inverse optical calculation is applied to the modified target pattern to calculate the mask pattern; evaluating a cost function to determine when the termination criterion is met, wherein the cost function corresponds to a difference between the modified target pattern and an estimated target pattern produced during the photolithographic process at the image plane using the mask pattern at the object plane; and when the termination criterion is not met, revising the set of polygon parameters, repeating the calculation of the mask pattern and the evaluating of the cost function until the termination criterion is met.