Patent ID: 8247875

Claim:
A P-channel type MIS transistor comprising: a semiconductor substrate including an N type well surrounded by an isolation region; a gate electrode formed on the N type well, a gate insulating film disposed between said N type well and said gate electrode; first source/drain regions formed in regions of the N type well, one of the first source/drain regions formed on a first side of said gate electrode and another of the first source/drain regions formed on a second side of said gate electrode, said first source/drain regions including a first element, said first element being larger than silicon and exhibiting P type conductivity; second source/drain regions formed in regions of the N type well, one of the second source/drain regions formed on said first side of said gate electrode and another one of the second source/drain regions formed on said second side of said gate electrode, said second source/drain regions including a second element, said second element being smaller than silicon and exhibiting P type conductivity; and a metal silicide layer formed on source/drain regions, said source/drain regions including the first source/drain regions and the second source/drain regions, wherein the first element is adjacent the metal silicide layer.