Patent ID: 8030106

Claim:
A method of manufacturing a display device, comprising: forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon, wherein forming the gate electrode, the gate insulating layer and the active layer includes: forming an extrinsic amorphous silicon layer on the substrate, an insulating layer on the extrinsic amorphous silicon layer, and an intrinsic amorphous silicon layer on the insulating layer; crystallizing the extrinsic amorphous silicon layer and the intrinsic amorphous silicon layer using a SPC (Solid Phase Crystallization); forming a photoresist pattern including first to third portions, wherein the second and third portions are at both sides of the first portion and have a thickness less than a thickness of the first portion; patterning the crystallized intrinsic silicon layer, the insulating layer, and the crystallized extrinsic silicon layer using the photoresist pattern, wherein the patterned crystallized extrinsic silicon layer is the gate electrode and the patterned insulating layer is the gate insulating layer; ashing the photoresist pattern to remove the second and third portions; and pattering the patterned crystallized intrinsic silicon layer using the ashed photoresist pattern to form the active layer; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.