Patent ID: 8689068

Claim:
An integrated circuit, comprising: a plurality of modules for performing a plurality of applications, each of said plurality of modules having a plurality of cells and a plurality of scan test elements that form a scan chain, wherein when at least one of said plurality of applications is being performed at least one of said modules is operating in a functional mode and at least one of said modules is inactive; and a controller for configuring the at least one inactive module of said plurality of modules to operate in a low leakage current mode while the at least one module of said plurality of modules is operating in the functional mode, wherein configuring the inactive module to operate in said low leakage current mode comprises applying a low leakage vector of input signals from said controller to said plurality of cells of said inactive module by way of said scan chain of the inactive module, and wherein said controller further comprises a clock generator that provides a low leakage scan clock signal to the inactive module to load the low leakage vector into said scan test elements of said inactive module.