Patent ID: 7100032

Claim:
An apparatus comprising: a revision identification (ID) register readable by a processor; a stepping revision ID register to maintain a value indicating the actual stepping revision level of a first hardware component; one or more compatible revision ID registers to maintain a value indicating a stepping revision level of a second hardware component that may be used with a same piece of software as the first hardware component, wherein one of the at least one compatible revision ID registers comprises at least one pin of a package enclosing the integrated circuit being tied to at least one voltage level to provide the stepping revision level of the second hardware component; and selection logic to enable the selection of a value from either the stepping revision ID register or one of the one or more compatible revision ID registers, the selected value to be readable by the processor, wherein the selection logic comprises a multiplexer within an integrated circuit and the stepping revision ID register comprises at least one hardwired connection within the integrated circuit that ties at least one input of the multiplexer to at least one voltage level to provide the value indicating the actual stepping revision level of the first hardware component.