Patent ID: 7244977

Claim:
A vertical MISFET comprising: a lower semiconductor layer of a first conductivity type formed over a main surface of a semiconductor substrate; an intermediate semiconductor layer formed over said lower semiconductor layer, an impurity of a conductivity type opposite to said first conductivity type having been introduced into the intermediate semiconductor layer; and an upper semiconductor layer of the first conductivity type, the upper semiconductor layer being formed over said intermediate semiconductor layer, wherein at least said upper semiconductor layer and said intermediate semiconductor layer each have a columnar laminated structure, said lower semiconductor layer constitutes one of a source and drain of said vertical MISFET, said upper semiconductor layer constitutes the other of the source and drain of said vertical MISFET, a gate electrode of said vertical MISFET is formed on a sidewall of said intermediate semiconductor layer via a gate insulating film, and a concentration of said impurity introduced into said intermediate semiconductor layer is lower in regions of said intermediate semiconductor layer closer to said lower and upper semiconductor layers and is higher in a region of said intermediate semiconductor layer further from said lower and upper semiconductor layers.