Patent ID: 8332700

Claim:
An integrated circuit comprising: A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; B. an IC TAP domain including: i. a TAP controller having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input coupled to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input coupled to the test data in lead, a test data output, and control inputs connected to the control outputs; and iv. multiplexer circuitry having an input connected to the test data output of the instruction register, an input connected to the test data output of the data register, and an output coupled to the test data out lead; C. a core TAP domain including: i. a TAP controller having a test clock input connected to the test clock lead, a test mode select input, and control outputs; ii. an instruction register having a test data input coupled to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs; iii. a data register having a test data input coupled to the test data in lead, a test data output, and control inputs connected to the control outputs; and iv. multiplexer circuitry having an input connected to the test data output of the instruction register, an input connected to the test data output of the data register, and an output coupled to the test data out lead; and D. input linking circuitry including: i. first multiplexer circuitry having an input connected to the test data in lead, an input connected to the multiplexer output of the core TAP domain, a control input, and an output connected to the test data input of the instruction register and the data register of the IC TAP domain; and ii. second multiplexer circuitry having an input connected to the test data in lead, an input connected to the multiplexer output of the IC TAP domain, a control input, and an output connected to the test data input of the instruction register and the data register of the core TAP domain.