Patent ID: 7671460

Claim:
A three dimensional integrated circuit comprising: a first active circuit layer deposited on a substrate wafer; a second active circuit layer coupled to the first active circuit layer, the second active circuit layer having a via and a first metal layer, the first metal layer is embedded in a first dielectric material in the second active circuit layer, the via is etched through the first dielectric material to expose the first metal layer, the via contains metal in contact with the first metal layer of the second active circuit layer; and a third active circuit layer having a second metal layer, the second metal layer is embedded in a second dielectric material in the third active circuit layer, the second dielectric material has an opening that exposes the second metal layer of the third active circuit layer, the opening is aligned above the via of the second active circuit layer, the opening contains a metal bond that mechanically couples the third active circuit layer to the second active circuit layer, and the metal of the via electrically couples the first metal layer of the second active circuit layer to the second metal layer of the third active circuit layer, the third active circuit layer having a third metal layer located above the second metal layer, wherein the via does not contact and interrupt routing of the third metal layer.