Patent ID: 8598004

Claim:
A method for fabricating a semiconductor integrated circuit, the method comprising: providing a semiconductor substrate; forming a dielectric layer overlying the semiconductor substrate; forming a polysilicon gate layer overlying the dielectric layer; forming a capping layer overlying the polysilicon gate layer; patterning the polysilicon gate layer and the capping layer to form a gate structure, a local interconnect structure, and a contact region, the contact region being defined between the gate structure and the local interconnect structure, the gate structure and the local interconnect structure including the polysilicon gate layer and the overlying capping layer; forming sidewall spacers on the gate structure and the local interconnect structure; covering the gate structure including the sidewalls and a portion of the contact region with a photoresist layer while leaving the local interconnect structure totally uncovered; removing the sidewall spacer on the local interconnect structure; forming a contact polysilicon on the contact region; implanting a dopant impurity into the contact polysilicon; diffusing the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region; selectively removing the capping layer overlying the gate structure; and forming a silicide layer overlying the gate structure and a surface of the contact polysilicon, whereupon the sidewall spacers isolate the silicide layer on the gate structure from the silicide layer on the contact polysilicon.