Patent ID: 7119399

Claim:
A Semiconductor device comprising: a semiconductor substrate, an insulating layer on top of said substrate, a lateral field effect transistor comprising a drain region and a source region arranged in said substrate and a gate arranged above said substrate within said insulating layer, a drain runner arranged on top of the insulator layer above said drain region, a source runner arranged on top of the insulator layer above said source region, a gate runner arranged on top of the insulator layer outside an area defined by said drain runner and said source runner, a first coupling structure comprising a via for coupling said drain runner with said drain region, and a second coupling structure comprising a via for coupling said source runner with said source region and a barrier metal layer arranged at the bottom of said via and within said insulating layer, wherein the barrier metal layer comprises a first horizontal bottom layer adjacent said via and a side wall being rectangular to and surrounding said first horizontal bottom layer and said side wall is spaced apart from said via.