Patent ID: 7098111

Claim:
A manufacturing method of a semiconductor integrated circuit device including the following steps of: (a) forming a gate insulator on a main surface of a semiconductor substrate, and forming a dummy gate electrode on the gate insulator; (b) ion-implanting a first impurity on the main surface of the semiconductor substrate subsequent to the step (a); (c) forming a sidewall spacer in the sidewall of the gate electrode subsequent to the step (b); (d) ion-implanting a second impurity of the same conductive type as the first impurity on the main surface of the semiconductor substrate subsequent to the step (c); (e) forming an energy absorber layer comprising a thin layer on the main surface of the semiconductor substrate subsequent to the step (d); (f) activating the first impurity and the second impurity by transmitting a heat of the energy absorber layer heated by the irradiation of a laser beam to the semiconductor substrate and annealing its main surface, and forming a source and drain of a MOSFET including an extension region on the main surface; (g) removing the energy absorber layer subsequent to the step (f); (h) depositing a thick insulator higher in height than the dummy gate on the main surface of the semiconductor substrate, and subsequently, exposing the upper surface of the dummy gate electrode by polishing the insulator by chemical mechanical polishing subsequent to the step (g); (i) removing the dummy gate electrode subsequent to the step (h); and (j) forming the gate electrode of a MOSFET comprising the conductive layer by filling the conductive layer mainly comprising a metal in a region removed from the dummy gate electrode subsequent to the step (i).