Patent ID: 8327301

Claim:
A method of designing a double patterning mask set for a chip, the method comprising: designating a first pattern set; designating a second pattern set; dividing a metal layer of the chip into a grid; laying out metal line patterns for the metal layer of the chip, wherein all left-boundary metal line patterns in a first grid cell of the grid are in a same one of the first pattern set and the second pattern set, and all right-boundary metal line patterns in the first grid cell are in an additional same one of the first pattern set and the second pattern set; switching by a computer the left-boundary metal line patterns to a different pattern set in the first pattern set and the second pattern set; switching by a computer the right-boundary metal line patterns to an additional different pattern set in the first pattern set and the second pattern set; forming a first mask of the double patterning mask set, wherein patterns in the first pattern set are formed on the first mask; and forming a second mask of the double patterning mask set, wherein patterns in the second pattern set are formed on the second mask.