Patent ID: 7555591

Claim:
A computational system comprising: a processor configured to access a virtual memory space to perform a first task of a plurality of tasks and configured to access the virtual memory space to perform a second task of the plurality of tasks, the virtual memory space referencing a first set of task instructions associated with the first task and referencing a second set of task instructions associated with the second task, the virtual memory space referencing non-instruction data associated with the first task; cache memory accessible to the processor, the cache memory configured to store the first set of task instructions and the non-instruction data; and a memory management unit accessible to the processor, the memory management unit configured to determine a physical memory location of the second set of task instructions, wherein the second set of task instructions is copied to volatile storage or to the cache memory directly from non-volatile storage when the second set of task instructions is accessed such that at least a portion of the first set of task instructions in the cache memory or in the volatile storage are overwritten by the second set of task instructions.