Patent ID: 8786111

Claim:
A semiconductor package comprising: a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip, wherein the first major surface includes a first contact region and the second major surface includes a second contact region, and wherein the vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction; a front side conductor disposed over the first contact region; a back side conductor disposed at the second contact region of the second major surface and covering the second major surface; and a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed, the first encapsulant disposed along a sidewall of the semiconductor chip in a direction of current flow, wherein the first encapsulant covers a first portion of sidewalls of the back side conductor; and a second encapsulant covering outer sidewalls of the first encapsulant, the front side conductor, and remaining portions of the sidewalls of the back side conductor.