Patent ID: 8129750

Claim:
An integrated circuit, comprising: a substrate region; and a gate electrode level region formed above the substrate region, the gate electrode level region including at least six linear-shaped conductive structures each fowled to extend lengthwise in a first direction, the at least six linear-shaped conductive structures including— a first linear-shaped conductive structure including a first gate portion that forms a gate electrode of a first transistor of a first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, a second linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the first transistor type, a third linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the second transistor type, a fourth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the first transistor type, a fifth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the second transistor type, a sixth linear-shaped conductive structure including a first gate portion that forms a gate electrode of a fourth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fourth transistor of the second transistor type, wherein at least two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.