Patent ID: 7547595

Claim:
A method for forming a semiconductor integrated circuit device comprising: providing a semiconductor substrate including a first well region and a second well region; forming a dielectric layer overlying the semiconductor substrate including the first well region and the second well region; forming a polysilicon gate layer overlying the dielectric layer, the polysilicon gate layer being overlying a first channel region in the first well region and a second channel region in the second well region in the semiconductor substrate; forming a hard mask overlying the polysilicon gate layer; patterning the polysilicon gate layer, including the hard mask layer, to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region; forming a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region; forming a spacer dielectric layer overlying the liner layer; patterning the spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges; etching a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer; depositing a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region; forming a blanket layer of silicon dioxide overlying an entirety of the surface region of the first well region and the second well region, the blanket layer of silicon dioxide overlying the hard mask on the first gate structure and the second gate structure, the blanket layer of silicon dioxide overlying a region to be protected; protecting the region to be protected using a masking layer, while the surface region of the first well region and the second well region being exposed; selectively removing exposed portions of the blanket layer of silicon dioxide, including the hard mask on the first gate structure and the second gate structure, while exposing a first polysilicon material on the first gate structure and exposing a second polysilicon material on the second gate structure; stripping the masking layer; and forming a silicided layer overlying the first polysilicon material on the first gate structure and the second polysilicon material on the second gate structure, while the region to be protected remains free from the silicided layer.