Patent ID: 8040747

Claim:
A circuit for controlling precharge in a semiconductor memory apparatus, comprising: a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal wherein the read write mode signal has different potential levels in a read operation mode and a write operation mode; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read auto precharge signal and the write auto precharge signal and generate an auto precharge signal in response to a bank active signal, a command pulse signal, and a precharge delay signal, wherein the write clock driver is configured to toggle the write burst clock signal when the read write mode signal indicates the write operation mode and the data input off signal is disabled.