Patent ID: 7707324

Claim:
A direct memory access controller comprising: a system bus interface adapted for connection to a system memory over a system bus, where the system memory includes first, second, and third color data for each pixel of a plurality of pixels of an image, wherein the 0 first, second, and third color data for each pixel of the plurality of pixels is stored respectively at first, second, and third color planes of the system memory, where the first color plane includes first color data for the plurality of pixels of the image, the second color plane includes second color data for the plurality of pixels of the image, and the third color plane includes third color data for the plurality of pixels of the image, and wherein the first, second, and third color data for a given pixel are disposed at non-contiguous memory locations within the system memory; an image processor interface adapted for connection to an image processing engine over an image processor bus, where the image processor bus is separate from the system bus; a plurality of registers defining parameters for multiple direct memory access transactions, the plurality of registers including a first set of transaction registers defining parameters for transferring the first color data for each pixel of the plurality of pixels from the first color plane over the system bus for provision to the image processing engine over the image processor bus, a second set of transaction registers defining parameters for transferring the second color data for each pixel of the plurality of pixels from the second color plane over the system bus for provision to the image processing engine over the image processor bus, and a third set of transaction registers defining transfer of the third color data for each pixel of the plurality of pixels from the third color plane over the system bus for provision to the image processing engine over the image process or bus; and transfer control circuitry adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers, where each data transaction includes transfer of the first, second, and third color data for at least one respective pixel of the plurality of pixels from the first, second, and third color planes to the processing engine for generally concurrent processing of the first, second, and third color data for the respective pixel to generate a corresponding color processed pixel.