Patent ID: 7437617

Claim:
A method in a processor for concurrently sharing a memory controller between a tracing process and non-tracing processes, said processor including a plurality of processing units coupled together utilizing a system bus, said plurality of processing units including said memory controller that controls a system memory, said method comprising: capturing hardware trace data in said processor utilizing a hardware trace facility included within said processor; transmitting, utilizing said system bus, said hardware trace data to said system memory that is controlled by said memory controller, said system bus capable of being utilized by said plurality of processing units while hardware trace data is being transmitted to said system bus; utilizing said memory controller to store said trace data in said system memory; said memory controller being accessed by processing units in said processor other than said hardware trace facility while said memory controller is being utilized to store said trace data; temporarily storing all data that is to be stored in said system memory first in one of a plurality of write buffers controlled by said memory controller; determining a number of said plurality of write buffers that are needed to optimize said transmission of said hardware trace data; requesting, by said hardware trace facility, said number of said plurality of write buffers; temporarily allocating, by said memory controller, said number of said plurality of write buffers to said hardware trace facility; and requesting said number of said plurality of write buffers by repeatedly generating a separate cast out request until said number has been requested, said separate cast out request requesting an allocation of one of said plurality of write buffers.