Patent ID: 6948050

Claim:
A single integrated circuit comprising: a first data processor including a first program counter ( 2903 ) storing an address of a next instruction, a first opcode register ( 2911 ) storing a current instruction, first data processing units ( 2902 , 2905 , 2906 , 2907 , 2908 , 2909 , 2910 ) capable of data processing, a first control logic ( 2904 ) connected to said opcode register for control of said first data processing units corresponding to said current instruction stored in said first opcode register according to a first instruction set; a second data processor including a second program counter ( 3100 ) storing an address of a next instruction, a second opcode register ( 3105 ) storing a current instruction, second data processing units ( 3301 , 3302 , 3303 , 3304 ) capable of data processing, a second control logic ( 3002 ) connected to said opcode register for control of said second data processing units corresponding said current instruction stored in said second opcode register according to a second instruction set, said second data processing units having a different mapping of instructions to controlled operations than that of said first instruction set; and an external interface ( 11 ) connected to said first and second data processors and adapted for connection to memory ( 15 ) external to said single integrated circuit, said external interface forming the only connection between said first and second data processors and memory external to said single integrated circuit; where said first and second data processors are capable of independent operations on disjoint instructions and data sets.