Patent ID: 7619939

Claim:
A semiconductor storage apparatus comprising: a memory cell array formed by arranging a plurality of memory cells in rows and columns; a cell array bit line pair which is provided for each column of the memory cell array, and connected to a plurality of memory cells of the column; a bit line sense amplifier which senses a potential of the cell array bit line pair; a sense amplifier bit line pair connected to the bit line sense amplifier; a cell array selection circuit which has a pair of transistors each having a gate electrode receiving a first control signal, the cell array selection circuit being connected between the cell array bit line pair and the sense amplifier bit line pair, and selectively connecting the cell array bit line pair and the sense amplifier bit line pair; a first precharge circuit which includes at least one transistor having the same conductivity type as that of the pair of transistors in the cell array selection circuit, and precharges and equalizes the cell array bit line pair, said at least one transistor having a gate electrode receiving a second control signal; a second precharge circuit which includes at least one transistor having the same conductivity type as that of the pair of transistors in the cell array selection circuit, and precharges and equalizes the sense amplifier bit line pair, said at least one transistor having a gate electrode receiving a third control signal; and a control signal generating circuit which generates the first, the second, and the third control signals, supplies the first, the second, and the third control signals to the cell array selection circuit, the first precharge circuit and the second precharge circuit, respectively, controls the cell array selection circuit to an inactive state and controls the first and the second precharge circuits to an active state in a standby state of read/write operation for the memory cell array, and controls the cell array selection circuit to an active state and controls the first and the second precharge circuits to an inactive state in an active state of read/write operation for the memory cell array.