Patent ID: 8418357

Claim:
A printed circuit board layout method comprising: providing a printed circuit board with a first layout layer, and a second layout layer; disposing a pair of first conducting portions on the first layout layer to electrically couple to a control chip; sequentially disposing a pair of second conducting portions, a pair of third conducting portions and a pair of fourth conducting portions on the second layout layer; providing a pair of connecting portions to respectively connect the first conducting portions of the first layout layer and the third conducting portions of the second layout layer; electrically coupling an electronic device to the second conducting portions, and providing a first component to electrically connect one of the second conducting portions and a corresponding one of the third conducting portions, and a second component to electrically connect the other one of the second conducting portions and the other one of the third conducting portions to form a first route; or electrically coupling the electronic device to the fourth conducting portions, and providing the first component to electrically connect one of the fourth conducting portions to a corresponding one of the third conducting portions, and the second component to electrically connect the other one of the fourth conducting portions to the other one of the third conducting portions to form a second route; and transmitting a pair of high-speed differential signals generated by the control chip to the electronic device, via the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the second conducting portions in turn in response to the first route being formed, or via the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the fourth conducting portions in turn in response to the second route being formed.