Patent ID: 7893477

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a first memory cell, a second memory cell, a first select gate transistor and a second select gate transistor; a first select gate line which is provided along a first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line; a first word line which is provided between the first and second select gate lines and along the first direction, a gate electrode of the first memory cell being connected to the first word line; and a second word line which is provided between the first word line and the second select gate line and along the first direction, a gate electrode of the second memory cell being connected to the second word line, wherein all of the first select gate line, the second select gate line, the first word line and the second word line are connected to the same memory cell unit, and the second select gate line is located closer to the second word line than the first select gate line, and wherein a voltage of the first select gate line is increased after a voltage of the second select gate line is increased, when data in the memory cell connected to the second word line is read.