Patent ID: 8841768

Claim:
A chip package, comprising: a first encapsulation structure; a first passivation layer formed over the first encapsulation structure and a first electrically conductive layer formed over the first passivation layer; at least one chip arranged over the first electrically conductive layer and the first passivation layer wherein at least one chip contact pad contacts the first electrically conductive layer; at least one cavity formed in the first encapsulation structure, wherein the at least one cavity exposes a portion of the first passivation layer covering the at least one chip contact pad; a second encapsulation structure disposed over the first encapsulation structure and covering the at least one cavity, wherein a chamber region over the at least one chip contact pad is defined by the at least one cavity and the second encapsulation structure; wherein the second encapsulation structure comprises an inlet and outlet connected to the chamber region, wherein the inlet and the outlet control an inflow and outflow of heat dissipating material to and from the chamber region.