Patent ID: 7456481

Claim:
A semiconductor device, comprising: a first device region including a plurality of source regions and a plurality of drain regions of first conductivity type transistors; a plurality of loop-shaped gate electrode regions of the first conductivity type transistors, each of the gate electrode regions formed on the first device region; a second device region including a plurality of source regions and a plurality of drain regions of a second conductivity type transistors; a plurality of loop-shaped gate electrode regions of the second conductivity type transistors, each of the gate electrode regions formed on the second device region and electrically coupled to each of the gate electrode regions of the first conductivity type transistors; a first wiring configured to supply a first voltage to at least one of the source regions of the first device region; a second wiring configured to supply a second voltage to at least one of the source regions of the second device region; and a third wiring electrically coupled to the drain regions of the first and second device regions and to the gate electrode regions of the first and the second conductivity type transistors; wherein the plurality of the loop-shaped gate electrode regions of the first conductivity type transistors are arranged to surround a part of the first device region and at least one device isolation region, and wherein the plurality of the loop-shaped gate electrode regions of the second conductivity type transistors are arranged to surround a part of the second device region and at least one device isolation region.