Patent ID: 7684311

Claim:
An equalizer comprising: a first extracting circuit extracting a plurality of pilot symbols from an inputted signal; an inverse Fourier transform circuit inversely Fourier transforming the extracted plurality of pilot symbols, and computing a complex gain per path; a second extracting circuit extracting a plurality of paths by using the complex gains; a Fourier transform circuit Fourier transforming the extracted paths; an equalization computing circuit extracting phase components of the Fourier-transformed paths, and equalizing the inputted signal by using the extracted phase components; a one-symbol delay circuit delaying the inputted signal by one symbol; a storing circuit temporarily storing the Fourier-transformed paths; a first switching circuit outputting the Fourier-transformed paths or the stored paths, in accordance with a control signal; and a second switching circuit determining, in accordance with the control signal, whether or not a clock signal is to be supplied to the Fourier transform circuit.