Patent ID: 8154071

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell including a cell transistor and a first insulation isolation layer in a first region of a semiconductor substrate, the cell transistor including a first gate insulator, a first gate electrode formed on the first gate insulator, an upper portion of the first gate electrode having a first concave portion, a second gate insulator covering the upper portion of the first gate electrode, a second gate electrode being embedded into the first concave portion and being formed on the second gate insulator, and the first insulation isolation layer being extended to a side-wall of the first gate electrode from the semiconductor substrate to be embedded in the semiconductor substrate to electrically separate the cell transistor; and a periphery circuit including a transistor and a second insulation isolation layer in a second region of the semiconductor substrate, the transistor including a third gate insulator being the same material as the first gate insulator, a gate electrode having a first conductive layer and a second conductive layer, the first conductive layer being formed on the third gate insulator, the second conductive layer having the same material as the first gate electrode and being formed to contact with the upper surface of the first conductive layer, and the second insulation isolation layer being extended to a side-wall of the second gate electrode from the semiconductor substrate to be embedded in the semiconductor substrate to electrically separate the transistor, wherein a third insulator is formed only between the second gate insulator and top portions of the first gate electrode on opposite sides of the first concave portion, and the second gate insulator is conformally formed covering the upper portion of the third insulator.