Patent ID: 8621142

Claim:
A storage system comprising: a communication interface through which to communicate with a host; a storage interface through which to access a plurality of solid-state memory devices arranged as an NÃ—M array of solid-state memory elements, where M is at least three (3); and a processor which, in operation, performs a set of operations including performing memory access operations on the solid-state memory elements in response to requests from the host, while not permitting all of the memory elements at a time in each row of the array to perform an erase or write; in response to a request from the host to read a set of data, determining whether a solid-state memory element in which at least a portion of the set of data is stored is busy; and when the solid-state memory element in which at least a portion of the set of data is stored is busy, reading information from other solid-state memory elements in the array, and reconstructing the set of data from said information.