Patent ID: 7033893

Claim:
A method of manufacturing a semiconductor device having a PMOS transistor and an NMOS transistor, the method comprising: forming a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (SiGe); forming isolation regions defining a PMOS region and an NMOS region; forming a thermal oxide layer on the strained Si layer in the PMOS and NMOS regions; selectively removing the thermal oxide layer and strained Si layer from the SiGe layer in the PMOS region; depositing a layer of dielectric material on the layer of SiGe in the PMOS region; and forming transistors in the PMOS and NMOS regions, wherein: a portion of the thermal oxide layer serves as the gate dielectric layer of the NMOS transistor; and a portion of the deposited layer of dielectric material serves as the gate dielectric layer of the PMOS transistor.