Patent ID: 6967371

Claim:
A semiconductor memory device comprising: a first area surrounded by a first side, a second side, a third side which is an opposite side of the first side, and a fourth side which is an opposite side of the second side; a second area arranged along the first side; a third area arranged along the second side; a fourth area arranged along the third side; a fifth area arranged along the fourth side; a first voltage supply line extending a first direction and crossing the first, second, and fourth areas; and a second voltage supply line extending a second direction and crossing the first, third, and fifth areas, wherein the second, third, fourth, and fifth areas are quadrilateral areas, wherein the first area includes a memory array, wherein the memory array has a plurality of dynamic memory cells which is provided at intersections of a plurality of word lines and a plurality of data lines, wherein the second and fourth areas include a plurality of word drivers each which is connected to corresponding one of the plurality of word lines, wherein the third and fifth areas include a plurality of sense amplifiers, and each of the plurality of data lines is connected to corresponding one of the plurality of sense amplifiers, wherein the first and second power supply lines are formed in a different layer, and wherein a first contact of the first and second power supply line is provided in the first area.