Patent ID: 7949855

Claim:
A multi-threaded processor, comprising: a plurality of different types of execution units, at least one of each type of execution unit servicing a different class of operations; an instruction buffer that is configured to buffer a set of instructions for a plurality of asynchronous threads, each instruction requiring an operation performed by one of each of the plurality of different types of execution units; a monitor unit coupled to the plurality of different types of execution units and configured to monitor status of the plurality of different types of execution units; and an instruction scheduler coupled to the instruction buffer and the monitor unit, configured to receive input from the instruction buffer and the monitor unit, and also configured to: qualify at least a portion of the set of instructions for execution based on a qualification rule stored in memory and the status of the plurality of different types of execution units to produce a set of qualified instructions; wherein a remaining portion of the set of instructions are unqualified for execution based on the qualification rule and the status of the plurality of different types of execution units; prioritize the set of qualified instructions, and not the unqualified instructions, based on a prioritization rule to produce prioritized instructions for issue from said instruction buffer to the plurality of different types of execution units; and provide an output representing at least a portion of the prioritized instructions to be issued to at least a portion of the plurality of different types of execution units.