Patent ID: 8395189

Claim:
A semiconductor integrated circuit device comprising: a group of wirings routed at first to Nth (N being an integer not less than two) wiring positions sequentially disposed in parallel, each of the wirings being divided into two portions comprising a starting end side and a terminating end side; and an Mth buffer circuit that connects the starting end side of the wiring at the Mth wiring position (M being an integer that satisfies 1≦M≦K, wherein K is an integer that satisfies K≦N/2) as an input and the terminating end side of the wiring at the (M+N−K)th wiring position as an output; wherein said group of the wirings has a structure in which connection is switched so that the starting end side of the wiring at a Jth (J being an integer. that satisfies K<J≦N) wiring position is routed to the terminating end side of the wiring at a (J−K)th wiring position on a wiring layer above a placement region of the buffer circuit(s).