Patent ID: 7436474

Claim:
A thin film transistor array panel comprising: an insulating substrate; a gate wire formed on the substrate and including a gate line and a gate electrode connected to the gate line; a gate insulating layer formed on the gate wire; a data wire including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode with reference to the gate electrode; a semiconductor pattern formed on the gate insulating layer and including a first portion located under the data line between two neighboring gate wires and a second portion located under the source electrode and the drian electrode; a light blocking member overlapping the first portion of the semiconductor pattern, wherein the light blocking member is formed of the same layer as the gate wire and separate from the gate wire; and a pixel electrode electrically connected to the drain electrode, wherein a width of the light blocking member is smaller than a width of the data wire and a width of the light blocking member overlapping the first portion of the semiconductor pattern is equal to or larger than a width of the first portion of the semiconductor pattern.