Patent ID: 8766410

Claim:
An integrated circuit comprising: a substrate comprising a silicon layer over a buried oxide (BOX) layer, wherein a select region of the silicon layer, an extremely-thin silicon-on-insulator (ETSOI) region, has a thickness of between about three nanometers and about 20 nanometers; at least one embedded dynamic random access memory (eDRAM) cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer and a pass transistor gate region over the pass transistor channel region, wherein the pass transistor channel region is undoped and is defined by extension implants in the silicon layer at opposite ends of the pass transistor channel region, and wherein a threshold voltage of the pass transistor is set by a work function of the pass transistor gate region as opposed to the channel region which is undoped; a capacitor electrically connected to the pass transistor; and a doped silicon layer surrounding the capacitor configured to serve as a ground to the capacitor.