Patent ID: 8050130

Claim:
A semiconductor memory device comprising: a memory controller configured to, during an internal data transmission operation, externally receive and store a source address and a target address and output an internal control signal and an internal address signal using the source address and the target address in response to an externally applied command, the internal control signal including an internal write signal and an internal read signal; a pair of data lines on which transmission data is transmitted during the internal data transmission operation; and a plurality of memory banks configured to read the transmission data stored in a region corresponding to the source address and transmit the transmission data on the pair of data lines in response to the internal read signal, and to write the transmission data transmitted on the pair of data lines in response to the internal write signal, wherein, during the internal data transmission operation, the transmission data is transmitted from the region corresponding to the source address to a region corresponding to the target address, and is not output external to the semiconductor memory device.