Patent ID: 7073102

Claim:
A method for repairing faults in a memory with W base units and k redundant units, each base unit comprising at most S=2 s identical portions, selected by s address bits, z among said k redundant units (z≧0, k−z>0) each comprising the same number of portions, of same size, as the base units, selected by s address bits, the k−z other redundant units each comprising at most T=2 t portions of same size as the base units, selected by t address bits which form a subset of the s address bits, and comprising: storage means for storing the fault locations, connection/disconnection means for disconnecting from a rest of the memory faulty units and connecting in their place fault-free units, and means for generating control signals of the connection/disconnection means, responding to the content of the storage means, the value of the control signals determining the units to disconnect and the units to be connected instead, wherein: in a test phase, fault tests are carried out for the different units, and the results of the fault tests of each portion of the k−z redundant units are stored in at most P=2 p distinct sets of storage means, selected by p address bits which form a subset or superset of the t address bits, with p=t+c, c being a negative, positive or zero integer, such that p≧0, and the results of the fault tests of each portion of the base units and of the z redundant units are stored in at most R=2 r distinct sets of storage means, selected during the test phase by r address bits which form a superset or subset of the s address bits, with r=s+c, and in a use phase aiming at the use of given unit portions, said control signals are determined by the content of the storage means corresponding to these unit portions, said control signals being a function of the p address bits and of at most P=2 p groups of intermediary control signals, each group of the intermediary control signals being a function of: the content of all the storage means affecting the k−z redundant units, selected in the test phase by a value of the p address bits, at most U=2 r−p sets or means for storing the locations of the faults affecting the base units and the z redundant units, selected during the test phase by the same value of the p address bits, and u from among the r address bits other than the p address bits (u=r−p).