Patent ID: 6925583

Claim:
A JTAG-compliant chip for communicating with a non-JTAG-compliant chip comprising: a JTAG-compliant test access port (TAP) controller integrated on a programmable logic device (PLD); a TAP input pin coupled to the TAP controller on the PLD; a boundary scan shift resister coupled to the TAP input in and to the TAP controller; a plurality of pins of the PLD coupled to the first shift resister and coupled to the non-JTAG-compliant chip; and a controller implemented on programmable logic resources of the PLD coupled to: receive signals from a second shift register that is coupled to the TAP input pin and implemented on programmable logic resources of the PLD, and in response to the signals from the shift register and the TAP controller, send and receive signals on the plurality of PLD pins coupled to the non-JTAG-compliant chip.