Patent ID: 7646191

Claim:
A method for detecting a leading edge blanking parameter of a power management chip, comprising: generating a pulse signal, wherein a voltage amplitude of the pulse signal is larger than a reference voltage level necessary to cause a pulse width modulation (PWM) signal of the power management chip to change its duty cycle, and wherein a pulse width of the pulse signal may cause the PWM signal of the power management chin to change its duty cycle; inputting the pulse signal to the power management chip, and detecting the duty cycle of the PWM signal of the power management chip to generate a detected result; when the detected result indicates that the duty cycle of the PWM signal has not changed, adjusting a pulse width of the pulse signal to generate an adjusted pulse signal, inputting the adjusted pulse signal to the power management chip and detecting the duty cycle of the PWM signal; and when the detected result indicates that the duty cycle of the PWM signal has changed, determining the leading edge blanking parameter of the power management chip, the leading edge blanking parameter being substantially the pulse width of the inputted pulse signal that causes the pulse width modulation signal of the rower management chip to change its duty cycle.