Patent ID: 8358015

Claim:
A layered chip package comprising a main body and wiring, wherein: the main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part; the wiring includes a plurality of lines that are electrically connected to the plurality of first terminals and the plurality of second terminals and that pass through all the three or more layer portions; each of the three or more layer portions includes: a semiconductor chip having a first surface, and a second surface opposite to the first surface; and a plurality of electrodes that are electrically connected to the wiring; in at least one of the three or more layer portions, the plurality of electrodes are electrically connected to the semiconductor chip; the plurality of electrodes are disposed on a side of the first surface of the semiconductor chip; the three or more layer portions include a first layer portion that is located closest to the top surface of the main part, and a second layer portion that is located closest to the bottom surface of the main part; the first layer portion and the second layer portion are arranged so that the second surfaces of their respective semiconductor chips face toward each other; the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion; and the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.