Patent ID: 6855608

Claim:
A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates, the method comprising: fabricating a tunnel dielectric layer on a surface of a substrate; fabricating a charge trapping dielectric over the tunnel dielectric; depositing a polysilicon layer over the charge trapping dielectric; applying a word line mask over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between; etching the polysilicon layer to expose the charge trapping dielectric in the trench regions; applying a bit line mask over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between; etching the polysilicon layer and the charge trapping dielectric layer to expose the tunnel dielectric layer in the bit line regions; fabricating insulating spacers on exposed sidewalls of the polysilicon layer and the charge trapping layer; removing the tunnel dielectric layer to expose the substrate between insulating spacers in the bit line regions; fabricating a conductor on the exposed substrate in the bit line regions; and fabricating word line conductors that electrically couple remaining portions of the polysilicon layer along word lines in the first direction.