Patent ID: 8687406

Claim:
A semiconductor memory device, comprising: a memory cell array configured having a plurality of memory cell mats stacked therein, each of the memory cell mats including a plurality of first lines, a plurality of second lines intersecting the first lines, and a plurality of memory cells connected to the first lines and the second lines, and the memory cell mats being stacked such that the first lines and the second lines are shared alternately by each of the memory cell mats; and a peripheral circuit for applying a voltage to the memory cell array, each of the memory cells having a variable resistance characteristic and a current rectifying characteristic, and adopting one end as an anode and the other end as a cathode according to the current rectifying characteristic, an orientation from the anode toward the cathode of all the memory cells in the memory cell array being identical, and the peripheral circuit, during setting, resetting, and read operations of a selected memory cell, adopting one of the first line and the second line connected to an anode side of the selected memory cell as a selected bit line, and applying to the selected bit line a selected bit line voltage which is a voltage on the anode side required in the setting, resetting, and read operations, and adopting the other of the first line and the second line connected to a cathode side of the selected memory cell as a selected word line, and applying to the selected word line a selected word line voltage which is a voltage on the cathode side required in the setting, resetting, and read operations.