Patent ID: 7979763

Claim:
A scan test system for testing a design implemented in an integrated circuit (IC), the design including a plurality of scan chains, the system comprising: a first pseudo-random pattern generator (PRPG) processing chain for receiving a first seed to generate patterns for identifying faults of the design, the patterns being applied to the plurality of scan chains; a second PRPG processing chain for receiving a second seed to generate X-tolerant (XTOL) control bits, the XTOL control bits determining a level of observability of the scan chains; an unload block for receiving scan outputs from the plurality of scan chains and the XTOL control bits, providing a per-shift X-control, and generating test outputs for analyzing the design; and an addressable PRPG shadow configured to receive inputs from a tester and to selectively provide one of the first seed to the first PRPG processing chain and the second seed to the second PRPG processing chain.