Patent ID: 8607241

Claim:
A processor comprising: an execution unit; and a decoder coupled with the execution unit, the decoder to decode instructions including a first instruction, wherein the first instruction comprises a compare and exchange instruction: (1) the execution unit, in response to the first instruction, operable to cause a second source operand of the first instruction to be stored in a destination operand of the first instruction if a first source operand of the first instruction equals a third source operand of the first instruction; and (2) the processor comprising a sleep-wakeup mechanism implemented in hardware that is responsive to the compare and exchange instruction, if the first source operand does not equal the third source operand, to: (a) put one or more instructions decoded from the first instruction to sleep, and to allow other instructions of a same thread as the first instruction to execute while the one or more instructions decoded from the first instruction sleep, if the first source operand does not equal the third source operand; and (b) wake the one or more instructions decoded from the first instruction if an event occurs, where the processor is to detect that the event occurs without repeatedly executing a software-based spin-loop, and where the event is at least one of: an attempt to change a value of a cache line associated with the first instruction; an invalidation of the cache line associated with the first instruction; and a change of the value of the cache line associated with the first instruction.