Patent ID: 8357582

Claim:
A method of forming a plurality of memory cells, comprising: forming a semiconductor substrate to have a first series of electrically conductive lines spaced from one another by dielectric regions; the electrically conductive lines of the first series extending primarily along a first direction; the substrate having an upper surface comprising surfaces of the electrically conductive lines; forming alternating first and second surface configurations along the surfaces of individual electrically conductive lines; forming memory cell material across the semiconductor substrate; the memory cell material comprising two or more domains; a first of the domains being induced by the first surface configuration, and a second of the domains being induced by the second surface configuration; forming a second series of electrically conductive lines over the memory cell material; the first domains of the memory cell material being in regions of the memory cell material that are directly between electrically conductive lines of the first series and the electrically conductive lines of the second series, and the second domains of the memory cell material being in regions of the memory cell material that are not directly between electrically conductive lines of the first series and the electrically conductive lines of the second series.