Patent ID: 8315226

Claim:
An apparatus comprising: at least one processor configured to receive signaling indicating power control (PC) modes selected from among multiple PC modes, wherein the multiple PC modes comprise an up-down PC mode and an erasure-based PC mode, wherein the signaling are received from at least one serving sector and one neighboring sector, and wherein the signaling from at least two different sectors indicate different PC modes, and to adjust transmit power in accordance with a determined PC mode, wherein the determined PC mode is based upon the received PC modes and their corresponding erasure indications, wherein to adjust transmit power further comprises to adjust the transmit power by an up power step size computed by a product of a down power step size and a first function of a target erasure rate in response to an erased decision based on the erasure indications, and to adjust the transmit power by a down power step size computed by a product of an up power step size and a second function of the target erasure rate in response to a non-erased decision based on the erasure indications; and a memory coupled to the at least one processor, wherein the memory is configured to store the multiple PC modes.