Patent ID: 7531420

Claim:
A method that produces a semiconductor memory cell having a contact hole capacitor and at least one selection transistor connected thereto, the method comprising: preparing a semiconductor substrate; forming the at least one selection transistor with a source region and a drain region to establish a channel in the semiconductor substrate, a gate stack having a gate dielectric and a control electrode formed on a surface of the channel; forming an inter-dielectric on a surface of the semiconductor substrate and of the gate stack; forming contact holes for the contact hole capacitor and a remaining source or drain region in the inter-dielectric to at least partially expose the source region and the drain region of the selection transistor; forming a liner layer as a capacitor counter electrode on the surface of the semiconductor substrate and of the at least one contact hole for the contact hole capacitor, the liner layer not reaching to the surface of the inter-dielectric; forming a further dielectric layer, which extends to the surface of the inter-dielectric, as a capacitor dielectric on the surface of the capacitor counter-electrode; forming an electrically conductive filler layer as a capacitor electrode on a surface of the capacitor dielectric inside the at least one contact hole for the contact hole capacitor; and forming a capacitor connection line on the surface of the inter-dielectric and of the filler layer to connect the capacitor electrode.