Patent ID: 7146722

Claim:
A method of forming a bond pad structure in a semiconductor die, the die having a test mode function circuitry configured to initiate a test sequence in the die and an operational mode function circuitry configured to initiate an operational mode in the die, and the bond pad structure comprising a first and second bond pad, the method comprising the steps of: depositing a first metal layer onto a substrate of the semiconductor die; etching the first metal layer to form first and second lower metal layers having a space thereinbetween; depositing a dielectric layer over the first and second lower metal layers and into the space thereinbetween; etching the dielectric layer to form openings to each of the first and second lower metal layers; depositing a second metal layer over the dielectric layer and into the openings of the dielectric layer; and etching the second metal layer to form first and second upper metal layers having a space thereinbetween to form the upper metal layer of one of the bond pads as an extension over the lower metal layer of the other of the bond pads; the first upper metal layer overlying the first lower metal layer to form a first bond pad, and the second upper metal layer overlying the second lower metal layer to form a second bond pad; wherein the first and second bond pads are electrically separate, and the first bond pad but not the second bond pad is connected to the test mode function circuitry of the die, and the second bond pad but not the first bond pad is connected to the operational mode function circuitry of the die.