Patent ID: 8503213

Claim:
A memory device, comprising: an integrated circuit substrate; a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks being ridge-shaped and including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions; a plurality of word lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the plurality of stacks and the plurality of word lines; memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of semiconductor material strips and the plurality of word lines, the memory cells arranged in strings between bit line structures and source line structures; and a plurality of string select gate structures, different ones of the plurality of string select gate structures coupling different ones of the stacks of semiconductor material strips to different ones of a plurality of string select lines, the plurality of string select gate structures coupled to alternating ends of the stacks of semiconductor material strips, such that string select gate structures of the plurality of string select gate structures are coupled to every other one of a first end of the stacks of semiconductor material strips and to every other one of a second end of the stacks of semiconductor material strips.