Patent ID: 6977197

Claim:
A method of manufacturing a semiconductor device, comprising: forming bit line and storage node landing pads over a semiconductor substrate; forming a bit line interlayer insulating layer overlying the bit line and storage node landing pads; forming a plurality of bit line patterns on the bit line interlayer insulating layer; forming line insulating layer patterns filling gap regions between the bit line patterns; forming a plurality of hard mask patterns traversing the bit line patterns over the line insulating layer patterns and the bit line patterns; partially etching the line insulating layer patterns by using the hard mask patterns and the bit line patterns as an etching mask to form upper contact holes which expose side walls of the bit line patterns; forming contact hole spacers on the side walls of the upper contact holes; sequentially etching the line insulating patterns and the bit line interlayer insulating layer, using the contact hole spacers, the hard mask patterns and the bit line patterns as an etching mask to form lower contact holes which expose the storage node landing pads; and forming storage node contact plugs filling the upper and lower contact holes.