Patent ID: 7371631

Claim:
A method of manufacturing a non-volatile semiconductor memory device having a memory cell comprising: a control gate formed over a first gate insulative film formed over a first p-type well of a main surface of a semiconductor substrate; a charge accumulation layer having a first portion formed on one of side walls of said control gate and a second portion formed over said first p-type well; a memory gate formed on said one of side walls of said control gate, electrically separated by said first portion of said charge accumulation layer from said control gate and electrically separated by said second portion of said charge accumulation layer from said first p-type well; a drain region of a second conductive type formed in said first p-type well with one end thereof being disposed near said control gate; and a source region of said second conductive type formed in said first p-type well with one end thereof being disposed near said memory gate, said method comprising steps of: (a) forming said first gate insulative film over said surface of said first p-type well and forming an undoped silicon film over said first gate insulative film; (b) ion implanting impurities into said undoped silicon film to convert said undoped silicon film into an n-type first silicon film; (c) patterning said n-type silicon film and said first gate insulative film to form said control gate comprising said n-type first silicon film while leaving said first gate insulative film below said control gate; (d) forming a first insulative film so as to cover said surface of said first p-type well and said side walls and said upper surface of said control gate; (e) forming an n-type second silicon film over said first insulative film and patterning said n-type second silicon film to form said memory gate comprising said n-type second silicon film on one of said side walls of said control gate; (f) removing said first insulative film in a region not in contact with said memory gate thereby forming said charge accumulation layer comprising said first insulative film with a first portion being disposed to one of said side walls of said control gate and a second portion thereof being disposed over said first p-type well; and (g) ion implanting impurities in said first p-type well to form said drain region of said second conduction type with one end thereof being disposed near said control gate and said source region of said second conductive type with one end thereof being disposed near said memory gate.