Patent ID: 8386828

Claim:
A circuit for estimating a latency through a FIFO buffer, comprising: a first detector for detecting a first plurality of instances of a pattern in first data values serially written to a write port of the FIFO buffer; a second detector for detecting a second plurality of instances of the pattern in second data values serially read from a read port of the FIFO buffer, wherein the second data values are the first data values delayed by the latency through the FIFO buffer; a counter coupled to the first and second detectors and counting a count of active transitions of a sample clock signal, the counter started in response to each detected instance of the first plurality of instances and stopped in response to each detected instance of the second plurality of instances, wherein the count provides an estimate of the latency of the FIFO buffer; and a data generator coupled to the first detector and the write port of the FIFO buffer: wherein: the data generator generates the first data values and serially writes the first data values to the write port of the FIFO buffer; the first data values repeat the first plurality of instances of the pattern; the pattern includes a first block of zero values followed by a second block of one values; the first block of zero values has a first duration and the second block of one values has a second duration; and a sum of the first and second durations is greater than an upper limit on the latency.