Patent ID: 7342279

Claim:
A non-volatile memory cell array of a type including a plurality of strings of series connected memory cells formed on a semiconductor substrate surface that are connectable at their ends to global bit lines, wherein the strings extend in a first direction across the substrate and the array includes eight or more word lines elongated in a second direction across the strings and positioned immediately adjacent each other in the first direction with a layer of dielectric therebetween, the first and second directions being perpendicular with each other, and wherein a charge storage dielectric layer is sandwiched in the strings between the word lines and the substrate surface, wherein the individual strings have a series of eight or more dielectric charge storage regions formed along the memory cell strings without source and drain regions therebetween, wherein the word lines individually comprise a metal material and the charge storage dielectric layer includes a first oxide layer on the substrate, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer, the second oxide layer also being contacted by the word line.