Patent ID: 8853703

Claim:
A thin film transistor array panel, comprising: a substrate; a plurality of gate lines disposed on the substrate, wherein each gate line comprises a gate pad; a gate insulating layer disposed on the plurality of gate lines; a plurality of data lines disposed on the gate insulating layer, wherein each data line comprises a data pad connected to a source electrode and a drain electrode; a first passivation layer disposed on the plurality of data lines and the drain electrode; a first electric field generating electrode disposed on the first passivation layer; a second passivation layer disposed on the first electric field generating electrode; and a second electric field generating electrode disposed on the second passivation layer, wherein the first passivation layer and the second passivation layer are inorganic materials, and the gate insulating layer, the first passivation layer, and the second passivation layer comprise a first contact hole exposing a part of the gate pad, the first passivation layer and the second passivation layer comprise a second contact hole exposing a part of the data pad, and at least one of the first contact hole and the second contact hole have a positive taper structure having a wider area at an upper side than at a lower side.