Patent ID: 7737775

Claim:
A DC offset calibration circuit comprising: two R-2R resistor arrays, a first end of one R-2R resistor array coupled to a first supply voltage, a first end of the other R-2R resistor array coupled to a second supply voltage, each R-2R resistor array comprising: a plurality of first resistors in series, a first end of the plurality of first resistors forming the first end of the R-2R array, each of the first resistors having a first resistance, each consecutive pair of the first resistors forming a node; a plurality of second resistors, a first end of one of the second resistors coupled to a second end of the plurality of first resistors, first ends of the second resistors other than the one coupled to each of the nodes respectively, each of the second resistors having a second resistance substantially twice the first resistance; and a third resistor having the second resistance, a first end of the third resistor coupled to the second end of the plurality of first resistors; a plurality of first switches, first ends of each of the first switches coupled to second ends of the second resistors respectively, second ends of each of the first switches coupled to a first input of an amplifier; and a plurality of second switches, first ends of each of the second switches coupled to the second ends of the second resistors respectively, second ends of each of the second switches coupled to a second input of the amplifier; wherein the third resistor of the one R-2R resistor array has a second end coupled to the first input of the amplifier, and the third resistor of the other R-2R resistor array has a second end coupled to the second input of the amplifier.