Patent ID: 6870189

Claim:
A junction field effect transistor, comprising: a gate region of a second conductivity type provided on one main surface of a semiconductor thin body consisting of an SiC substrate; a source region of a first conductivity type provided on said one main surface; a channel region of the first conductivity type that adjoins said source region; a confining region of the second conductivity type that adjoins said gate region and encloses and confines a range of said channel region; a drain region of the first conductivity type provided on an other main surface of said semiconductor thin body; and a drift region of the first conductivity type that continuously lies in a direction of thickness of said semiconductor thin body from said channel region to said drain region; wherein: a concentration of an impurity of the first conductivity type in said drift region and said channel region is lower than a concentration of an impurity of the first conductivity type in said source region and said drain region and lower than a concentration of an impurity of the second conductivity type in said confining region, said source region, said channel region, said drain region and said drift region are formed of at least one first SiC film having the first conductivity type, said gate region and said confining region are formed of at least one second SiC film having the second conductivity type, a first conductivity type impurity concentration of said drift region is higher than a first conductivity type impurity concentration of said channel region, and there is no contact plane surface between said confining region and said source region.