Patent ID: 7688123

Claim:
A delay locked loop circuit comprising: a register controlled delay part adapted to receive initial state setting signals and a phase detecting signal, receive and delay a plurality of clocks input during an initial operation by delay amounts among varied initial delay amounts set according to the initial state setting signals, and increase or decrease the set delay amounts according to the phase detecting signal after the initial operation, wherein the register controlled delay part comprises a plurality of delay lines configured to receive the initial state setting signals or register values and receive and delay the plurality of clocks by the delay amounts set according to the initial state setting signals or register values, a shift register configured to receive shift control signals and output register values corresponding to the shift control signals and a shift controller configured to receive the phase detecting signal and output the shift control signals to the shift register in accordance with the phase detecting signal; a phase comparator adapted to receive the plurality of clocks and the plurality of clocks delayed by the register controlled delay part, compare a phase of any one of the plurality of clocks and a phase of any one of a plurality of clocks delayed by the register controlled delay part, and output the phase detecting signal; and an initial state setting unit adapted to generate the initial state setting signals, wherein the initial state setting unit comprises: a fuse having a first end coupled to a power supply terminal and a second end; a first switching element coupled between the second end of the fuse and a ground terminal and is adapted to be turned on according to the reset signal; an inverting element coupled to the second end of the fuse and providing an output; and a second switching element coupled to the ground terminal and a connecting node between the fuse and the inverting element and is adapted to be turned on according to the output of the inverting element.