Patent ID: 8130012

Claim:
A buffer circuit of a semiconductor integrated apparatus, comprising: a control block configured to compare an input voltage level and an output voltage level and output the result as a control signal; and a buffering block including: a signal generation section configured to receive a first bias voltage and a second bias voltage and to generate a pull-up signal and a pull-down signal in response to the input voltage level, and a voltage output section configured to the generate the output voltage in response to the pull-up signal, the pull-down signal, and the control signal, wherein the voltage output section includes: a pull-up unit configured to perform a pull-up operation in response to the control signal and the pull-up signal, and a pull-down unit configured to perform a pull-down operation in response to the control signal and the pull-down signal, wherein the pull-up unit includes: a pull-up driver configured to receive the pull-up signal and to connect with a supply voltage terminal, and a first switching part configured to receive the control signal, to connect with the pull-up driver, and to provide an output voltage of the pull-up driver as the output voltage of the buffering block when the control signal is enabled, wherein the pull-down unit comprises: a second switching part configured to connect with the first switching part and to transmit the output voltage of the pull-up driver when the control signal is disabled, and a pull-down driver configured to connect with the second switching part and to provide an output of the second switching part to a ground terminal depending upon a potential level of the pull-down signal, and wherein the control block has a single output node that is directly connected to both the first and the second switching parts.