Patent ID: 7652935

Claim:
A semiconductor memory device, comprising: a memory array having a plurality of memory cells and divided into first and second memory mats; a selection circuit designating prescribed areas having an identical address, of respective said first and second memory mats of said memory array, that are data write targets, based on external address input; first and second data latch portions holding first and second write data groups defining application of program pulses to memory cells in the prescribed areas of said first and second memory mats designated by said selection circuit, respectively; first and second write drivers provided corresponding to said first and second data latch portions respectively, for applying the program pulses to the memory cells included in selected said prescribed areas in accordance with said first and second write data groups; a write/verify control portion for controlling at least one of said first and second write drivers to perform data write and verify write in which the program pulse is applied to the memory cell included in said selected prescribed area; and a sense amplifier portion for performing data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target; said write/verify control portion giving an instruction to perform data write into the prescribed area of one of said first and second memory mats based on said write data group held in one of said first and second data latch portions, and repeatedly giving an instruction to perform said verify write into the memory cell included in said selected prescribed area until verify is completed, based on a result of verify obtained based on comparison between a data group read by said sense amplifier portion from the memory cell included in said selected prescribed area and said write data group, and in a write sequence, said write/verify control portion giving an instruction to perform data write into the memory cell included in the prescribed area of said second memory mat after verify of the memory cell included in the prescribed area of said first memory mat is completed.