Patent ID: 7327590

Claim:
A memory module comprising: an IO chip; a plurality of DRAMs stacked on the IO chip; and an interposer substrate having BGA terminals of all system data signals, system address signals, system control signals, and system clock signals required to constitute a function of a memory sub-system of one channel, and including a constitution in which a plurality of DRAM chips connected to a pad for input/output and a pad for input of each input/output circuit on the IO chip and stacked on the IO chip are bonded to a data signal terminal, an address signal terminal, and a control signal terminal of the IO chip by the through electrodes, a data signal, an address signal, and a control signal between the chips are received/transmitted via the through electrodes, and a power supply and GND are supplied to the pads on the IO chip from the BGA terminals, and supplied to a power supply of each DRAM chip and a GND terminal via the through electrode, and wherein the DRAM chip has the number, which is 2n (n denotes a natural number of 1 or more) times that of system data buses, of through electrode data signal terminals for write and read, or bidirectional terminals, and the IO chip further has the number, which is 2n times that of system data buses, of through electrode data signal terminals for write and read, or bidirectional terminals.