Patent ID: 8338859

Claim:
A semiconductor electronic device comprising: a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising a nitride based compound semiconductor having a smaller lattice constant and a greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising a nitride based compound semiconductor having a smaller lattice constant and a smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising a nitride based compound semiconductor formed on said buffer layer; and a dislocation reducing layer comprising a nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and an inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein the lower layer area and the upper layer area are made of semiconductor materials that have the same composition and a threading dislocation extending from the lower layer area to the upper layer area is bent at said boundary surface.