Patent ID: 6839859

Claim:
A semiconductor integrated circuit comprising: a clock non-synchronous type circuit for performing data read operation on the basis of a read control signal and outputting read data from a data output node asynchronously with a clock signal; a clock synchronous type circuit for receiving the read data through a data input node in synchronism with the clock signal; data storage circuits connected in parallel between the data output node and the data input node; a first transfer timing determining circuit for selecting one of said data storage circuits and transferring the read data output from said clock non-synchronous type circuit to said selected one data storage circuit, said first transfer timing determining circuit transferring the read data on the basis of a first control signal representing that the read data is output from said clock non-synchronous type circuit; and a second transfer timing determining circuit for selecting one of said data storage circuits and transferring the read data stored in said selected one data storage circuit to said clock synchronous type circuit, said second transfer timing determining circuit transferring the read data on the basis of a second control signal synchronous with the clock signal.