Patent ID: 8587052

Claim:
A semiconductor device, comprising: a memory cell array formed on a substrate, the memory cell array including, a gate stack including alternating conductive and insulating layers, a first lower conductive layer in the gate stack having a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer disposed substantially higher than a second contact area of the first upper conductive layer; and first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively, wherein the gate stack includes a second lower conductive layer and a second upper conductive layer, the second lower conductive layer has a portion disposed below the second upper conductive layer, and a third contact area of the second lower conductive layer is disposed higher than a fourth contact area of the second upper conductive layer, the first lower conductive layer is disposed below the second lower conductive layer, and the first upper conductive layer is disposed below the second upper conductive layer, and the first contact area and the fourth contact area are at a substantially same level.