Patent ID: 6903409

Claim:
A semiconductor device comprising: a semiconductor substrate; a first isolation layer on the semiconductor substrate; a second isolation layer on the semiconductor substrate, wherein the second isolation layer is spaced apart from the first isolation layer to define a first active region therebetween; a third isolation layer on the semiconductor substrate, wherein the third isolation layer is spaced apart from the second isolation layer to define a second active region therebetween, and wherein the first, second and third isolation layers define a row; a first cell gate on the first active region, the first cell gate comprising a first gate dielectric layer, a first storage node, a first multiple tunnel junction barrier and a first source layer that are sequentially stacked; a second cell gate on the second active region, the second cell gate comprising a second gate dielectric layer, a second storage node, a second multiple tunnel junction barrier and a second source layer that are sequentially stacked; a first control line surrounding at least a portion of each sidewall of the first cell gate; a second control line surrounding at least a portion of each sidewall of the second cell gate, the second control line disposed parallel to the first control line; a first dielectric layer interposed between the first control line and the sidewalls of the first cell gate; a second dielectric layer interposed between the second control line and the sidewalls of the second cell gate; and a data line connecting to the first and second cell gates.