Patent ID: 7016344

Claim:
A SONET multiplexed communications system, comprising: at least one SONET input signal path configured to receive at least one input signal, the SONET input signal path including a pointer interpreter configured to interpret at least one input signal pointer; at least one SONET output signal path configured to transmit at least one output signal corresponding to the input signal, the SONET output signal path including a pointer generator configured to generate at least one output signal pointer; and a time slot interchange circuit operatively coupled between the pointer interpreter and the pointer generator included in the SONET input and output signal paths, respectively, the time slot interchange circuit being configured to provide time division multiplexed connections for the input and output signals, wherein the SONET input signal path further includes a synchronization buffer serially coupled to the pointer interpreter, the synchronization buffer being configured to transfer the input signal from a respective clock rate of the SONET input signal path to a respective clock rate of the time slot interchange circuit, and wherein the SONET output signal path further includes a first-in first-out buffer serially coupled to the pointer generator, the first-in first-out buffer being configured to transfer the output signal from the respective clock rate of the time slot interchange circuit to a respective clock rate of the SONET output signal path.