Patent ID: 7471277

Claim:
A display apparatus, comprising: a liquid-crystal cell array having pixels arranged in a matrix and active elements for driving the pixels; a data-line drive circuit that scans data lines, connected to the corresponding active elements in a column direction, to supply video signals; and a row drive circuit that scans gate lines, connected to the corresponding active elements in a row direction, to supply drive signals, thereby writing the video signals to the pixels, wherein, in a horizontal blanking period in a predetermined horizontal period, the row drive circuit drives the active elements in a predetermined row that is different from a row to which the video signals are written in the horizontal period, and the data-line drive circuit supplies a first predetermined fixed-level signal to all the data lines in the horizontal blanking period to write the fixed-level signal to pixels in a corresponding row, and wherein the data-line drive circuit supplies video signals containing the first predetermined fixed-level signal and a second predetermined fixed-level signal to the data lines, in the horizontal blanking period, wherein the data-line drive circuit comprises: a data-line selection circuit for sequentially selecting the data lines; and switching elements that are driven, in accordance with a fixed-level write signal generated in the horizontal blanking period and outputs from the data-line selection circuit, to supply the first predetermined fixed-level signal, the second predetermined fixed-level signal, and video signals to the data lines; the row drive circuit comprises a first row selection circuit and a second row selection circuit that scan the gate lines to drive the active elements; the first row selection circuit sequentially scans the gate lines to drive the active elements, thereby writing the second predetermined fixed-level signal and video signals to the pixels; and the second row selection circuit starts the vertical-direction scanning with delay of a predetermined amount of time relative to the first row selection circuit, to scan the gate lines to drive the active elements at timing when the switching elements are driven in accordance with the fixed-level write signal to cause the first predetermined fixed-level signal to be supplied to the data lines, thereby writing the first predetermined fixed-level signal to the pixels.