Patent ID: 8352893

Claim:
A method of circuit topology recognition, executed by at least one processor of a computer, comprising: receiving transistor-level netlist data for a circuit; identifying one or more current mirrors in the circuit by analyzing the transistor-level netlist data by using the at least one processor of the computer; partitioning the circuit into a plurality of subcircuits; identifying a differential pair in the circuit based on the one or more current mirrors; determining one or more outputs of a differential pair subcircuit, the differential pair subcircuit being the subcircuit in which the differential pair is located; identifying one or more strongly connected subcircuits in the plurality of subcircuits that form a feedback loop with the differential pair subcircuit based on the one or more outputs; and grouping the one or more strongly connected subcircuit and the differential pair subcircuit into one subcircuit for circuit analysis, circuit simulation or both.