Patent ID: 7571260

Claim:
A microcomputer comprising: a central processing unit (CPU) that outputs an address signal; a plurality of resources is configured to be writable by the central processing unit each resource having a unique address identified by the CPU; and an output circuit including an address decoder configured to decode the an address signal output by the CPU into a decoded address signal the output circuit being configured to output a plurality of select signals based on the decoded address signal, each of the resources being configured to receive a corresponding one of the plurality of select signals from the output circuit, and each of the resources being made writable upon receiving corresponding select signal, the number of the plurality of select signals simultaneously outputted by the output circuit being configured to vary depending on the decoded address signal, and when the address signal output by the CPU indicates a predetermined address, the output circuit simultaneously outputs at least two of the plurality of select signals based on the decoded address signal to write to at least two of the resources corresponding to the at least two select signals.