Patent ID: 8384578

Claim:
An analog-to-digital converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal, said analog-to-digital converter circuit comprising: a first converter stage configured for receiving said analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing a difference between said analog input signal and a signal represented by said first set of conversion bits; a second converter stage comprising: (i) a clock generation circuit arranged for receiving said first completion signal and for generating a clock signal; (ii) a plurality of comparators each being configured for receiving said residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by said clock signal and for outputting a plurality of comparator decisions; (iii) a digital processing stage configured for receiving said plurality of comparator decisions and for generating a second set of conversion bits; and means for generating said digital representation of said analog input signal by combining said first set of conversion bits and said second set of conversion bits.