Patent ID: 6915366

Claim:
A computer system comprising: a communication bus with a local section ( 10 a,b ) and a shared section for connection of addressable bus units; an arbiter circuit ( 16 ) for issuing an arbited grant ( 25 ) to access the shared section ( 11 a,b ) in response to a request ( 22 ) to perform a bus access transaction; a bus station ( 12 ) coupled to the local section; a bridge circuit ( 16 ) with a coupling between the local section ( 10 a,b ) and shared section ( 11 a,b ) and coupled to the arbiter ( 15 ) for receiving the arbited grant ( 25 ), the bridge ( 16 ) enabling the coupling to pass the address to the shared section ( 11 a,b ) in said bus cycle conditional on the arbited grant ( 25 ), characterized in that the bus station ( 12 ) has a request output ( 17 a ) for issuing the request to the arbiter ( 16 ), the bus station having a grant input ( 19 c ) arranged to receive a local grant ( 24 ) in response to the request ( 22 ) independent of the arbited grant ( 25 ), the bus station ( 12 ) being arranged to start the transaction, applying an address to the local section ( 10 a,b ) in response to the local grant ( 24 ) in a bus cycle following the local grant ( 24 ), the bridge circuit ( 16 ) signaling the station ( 12 ) to disable progress of the transaction when it detects that the address addresses a bus unit ( 14 b,c ) on the shared bus ( 11 a,b ) and no arbited grant ( 25 ) is received in response to the request ( 22 ) before said bus cycle.