Patent ID: 7068566

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells; an address input section used for input of an address for selecting a set of memory cells among the plurality of memory cells; a data I/O section used for input or output of data corresponding to the set of memory cells selected by the address, the data I/O section including a holding section that holds data input externally and externally outputs the held data; and a controller that, in response to a write or read request given externally and a specification request that is given externally and specifies input or output of a data group including at least part of the data corresponding to the set of memory cells, controls a write or read operation for a group of memory cells corresponding to the specified data group, wherein the controller, (i) in a first situation in which the write or read request is issued and the specification request for a first data group is issued, executes the write or read operation of the first data group for a first group of memory cells among the set of memory cells selected by the current address, executes the read operation of a second data group for a second group of memory cells among the set of memory cells on a preliminary basis, and holds the second data group in the holding section, the second group of memory cells being different from the first group of memory cells, and (ii) in a second situation in which the read request is issued while the current address is being maintained and the specification request for the second data group is issued, externally outputs the second data group held in the holding section without executing the read operation for the second group of memory cells.