Patent ID: 8234602

Claim:
A semiconductor-device manufacturing method comprising: forming a first layer including a line portion and a space portion with a first pitch above a lower layer to be processed; forming a second layer on each of side walls of the line portion of the first layer; removing the first layer thereby making the second layer into a layer including line portions and space portions with a second pitch smaller than the first pitch; patterning the lower layer by using the second layer as a mask thereby forming a first pattern structure on the lower layer including line portions and space portions with the second pitch; measuring an amount of displacement of the line portions of the first pattern structure based on a width of each of a first space portion and a second space portion among the space portions of the first pattern structure, the first space portion being derived from the space portion of the first layer, and the second space portion being derived from the line portion of the first layer; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure formed to be overlaid above the first pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets a corrected overlay specification, wherein the amount of displacement is an absolute value of a difference between the width of the first space portion and the width of the second space portion.