Patent ID: 8108730

Claim:
Apparatus for processing data comprising: a plurality of processors, each processor including debug circuitry having debug state data and configured to perform debug operations upon said processor; comparison circuitry configured to compare processing results of different processors of said plurality of processors; and debug control circuitry configured to control said debug circuitry of each of said plurality of processors, wherein said plurality of processors and said debug control circuitry are configured to provide: (i) a locked mode of operation in which each of said plurality of processors separately and during a corresponding processing cycle executes a common processing operation to generate respective processing results, said processing results of different processors compared by said comparison circuitry to identify incorrect operation; (ii) a split mode of operation in which each of said plurality of processors separately and during said corresponding processing cycle executes a different processing operation to generate respective different processing results; and (iii) an emulation-locked mode of operation in which at least one processor of said plurality of processors is an active processor and said debug circuitry of said active processor is configured to perform debug operations upon said active processor including changing said debug state data of said debug circuitry of said active processor and at least one processor of said plurality of processors is an inactive processor and maintains said debug state data of said inactive processor unaltered, wherein said inactive processor is configured to resume processing upon switching from said emulation-locked mode of operation to said split mode of operation without loss of the debug data from before entry into the emulation-locked mode of operation.