Patent ID: 7808272

Claim:
An integrated circuit to evaluate a signal, wherein said integrated circuit receives first and second input signals and said first input signal transitions between first and second states during a signal period, said integrated circuit comprising: a first storage unit to store a state for said second input signal in response to said first input signal attaining said first state during said signal period; a second storage unit to store a state for said second input signal in response to said first input signal attaining said second state during said signal period; and an evaluation unit to receive and compare said states of said second input signal stored in said first and second storage units to produce an evaluation signal, wherein said evaluation signal includes a first evaluation state in response to said state of said second input signal stored in said first storage unit differing from said state of said second input signal stored in said second storage unit, and wherein said evaluation signal includes a second evaluation state in response to said state of said second input signal stored in said first storage unit matching said state of said second input signal stored in said second storage unit; wherein: said first storage unit comprises a plurality of first storage devices coupled together in a serial fashion with each to store a respective state for said second input signal, wherein an initial first storage device receives said second input signal and remaining ones of said first storage devices receive said state of said second input signal stored within a preceding first storage device, and wherein said plurality of first storage devices produces said stored state as an output in response to said first input signal attaining said first state during said signal period; and said second storage unit comprises a plurality of second storage devices coupled together in a serial fashion with each to store a respective state for said second input signal, wherein an initial second storage device receives said second input signal and remaining ones of said second storage devices receive said state of said second input signal stored within a preceding second storage device, and wherein said plurality of second storage devices produces said stored state as an output in response to said first input signal attaining said second state during said signal period.