Patent ID: 7692833

Claim:
A multi-dimensional interpolation device for outputting scalar signals from input N-dimensional vector signals where N is an integer of not smaller than 4, the multi-dimensional interpolation device comprising: a dividing unit adapted to divide each component of the input N-dimensional vector signals into higher-order bits and lower-order bits; a memory unit adapted to store reference values corresponding to combinations of data of the higher-order bits divided by the dividing unit, the memory unit divisionally storing the reference values in 2 N−1 sub-memories; a reading unit adapted to read the reference values; an interpolation processing unit adapted to execute interpolation processing for the input N-dimensional vector signals based on the reference values read by the reading unit and data of the lower-order bits divided by the dividing unit; and a higher-order address generating unit adapted to repeatedly execute operation for collecting and coupling N bits at the same bit positions from N signals of the higher-order bits divided by the dividing unit to create an N-bit signal, from the least significant bit to the most significant bit of each signal of the higher-order bits in sequence, to further couple a plurality of created N-bit signals with each other, and to generate, as a higher-order address signal, signals obtained by excepting (N+3) bits from the coupled signals.