Patent ID: 7203818

Claim:
A microcontroller comprising: a central processing unit; a data memory having a linearized address space coupled with the central processing unit being divided into n banks; the central processing unit comprising: a bank select unit which either accesses one of the banks or accesses a virtual bank, whereby the virtual bank combines partial memory space of two banks of the data memory and wherein the selected bank forms a register file; an arithmetic logic unit coupled with the register file; a plurality of special function registers being mapped to one of the banks in the data memory, wherein one of the special function registers is a working register being coupled with the arithmetic logic unit; a program counter register within the central processing unit, the program counter mapped in the data memory; and a working register within the central processing unit being coupled with the arithmetic logic unit, the working register mapped in the data memory; wherein the microcontroller having an instruction set for controlling the arithmetic logic unit; wherein at least one instruction comprises a bit indicating whether the bank select unit accesses one of the banks or the virtual bank; and wherein the instruction set includes an instruction with an encoding of 1110 1010 kkkk kkkk, wherein upon invocation of the instruction, an 8 bit literal is copied to the location pointed to by a file select register, and the file select register is then decremented, the literal ‘k’ is designated in the kkkk kkkk portion of the instruction.