Patent ID: 8492208

Claim:
A method of fabricating a field-effect transistor (FET) device, comprising the steps of: forming nanowires and pads in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, wherein the nanowires are connected to the pads in a ladder-like configuration, and wherein the nanowires are suspended over the BOX; depositing a hydrogen silsesquioxane (HSQ) layer that surrounds the nanowires; cross-linking one or more portions of the HSQ layer that surround the nanowires, wherein the cross-linking causes the one or more portions of the HSQ layer to shrink thereby inducing strain in the nanowires, wherein the strain induced in the nanowires comprises a) tensile strain being induced in one or more portions of the nanowires and b) compressive strain being introduced in one or more other portions of the nanowires; and forming one or more gates surrounding portions of each of the nanowires, wherein the gates retain the strain induced in the nanowires by the cross-linking step, and wherein the portions of the nanowires surrounded by the gates comprise channel regions of the device and portions of the nanowires extending out from the gates and the pads comprise source and drain regions of the device.