Patent ID: 6901472

Claim:
A data processing device comprising: a first circuit configuration ( 1 ), which connects a first communication bus ( 2 ) with a second communication bus ( 3 ) and is the bus master of the first communication bus ( 2 ); a second circuit configuration ( 4 ), which is connected with the first communication bus ( 2 ), wherein the second circuit configuration is equipped with a first output port ( 5 ), which is connected with the input port ( 6 ) of the first circuit configuration ( 1 ); and a third circuit configuration ( 7 ), which is equipped with a second output port ( 8 ) that is connected with the first output port ( 5 ) through a logical OR function ( 9 ), wherein output port ( 10 ) of the OR function ( 9 ) is connected with the input port ( 6 ) of the first circuit configuration ( 1 ).