Patent ID: 8921920

Claim:
A semiconductor device, comprising: a semiconductor substrate; and a semiconductor element configured to comprise an FET which is formed on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state, wherein the semiconductor element comprises: an insulating film disposed above a part where a channel of the semiconductor substrate is formed; a gate electrode disposed above the insulating film; and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel, wherein when the semiconductor element is an n-type FET, the charge trap film sets the threshold voltage to a first voltage level when the semiconductor element is in the OFF state by capturing electrons from the gate electrode and becoming a neutral state, and sets the threshold voltage to a second voltage level lower than the first voltage level when the semiconductor element is in the ON state by transferring electrons to the gate electrode, and when the semiconductor element is a p-type FET, the charge trap film sets an absolute value of the threshold voltage to a third voltage level when the semiconductor element is in the OFF state by transferring extra electrons to the gate electrode and becoming the neutral state, and sets the absolute value of the threshold voltage to a fourth voltage level lower than the third voltage level when the semiconductor element is in the ON state by capturing electrons from the gate electrode.