Patent ID: 8503966

Claim:
A semiconductor integrated circuit comprising: a transconductance circuit comprising: a first current generator configured to generate a first current depending on an input voltage; and a second current generator configured to generate a second current depending on the input voltage; a first load circuit comprising a first load configured to output a first output voltage depending on the first current from a first output terminal; and a second load circuit comprising a second load configured to output a second output voltage depending on the second current from a second output terminal, wherein at least one of the transconductance circuit, the first load circuit and the second load circuit comprises an impedance adjusting module configured to adjust impedance in such a manner that a parameter “P” shown in a following equation decreases, P=Z 01 *Z 04 −Z 02 *Z 03 where, the Z 01 is impedance of the transconductance circuit seen from the first output terminal, the Z 02 is impedance of the transconductance circuit seen from the second output terminal, the Z 03 is impedance of the first load circuit, and the Z 04 is impedance of the second load circuit.