Patent ID: 8546239

Claim:
A method of fabricating non-volatile storage, comprising: etching a layer stack into a first layer stack column for a first column of non-volatile storage elements over a first active area of a substrate and a second layer stack column for a second column of non-volatile storage elements over a second active area of the substrate, wherein the first layer stack column includes a first tunnel dielectric strip, a first charge storage strip, and a first intermediate dielectric strip, wherein the second layer stack column includes a second tunnel dielectric strip, a second charge storage strip, and a second intermediate dielectric strip; forming an isolation region in the substrate between the first active area and the second active area; at least partially filling the isolation region with a sacrificial material; forming a control gate layer after at least partially filling the isolation region; etching the control gate layer, the first layer stack column and the second layer stack column, wherein etching forms a plurality of control gates from the control gate layer, a first plurality of charge storage regions from the first charge storage strip, and a second plurality of charge storage regions from the second charge storage strip; and removing at least a portion of the sacrificial material after etching the control gate layer, the first layer stack column and the second layer stack column, wherein removing at least a portion of the sacrificial material forms a bit line air gap in at least a portion of the isolation region.