Patent ID: 7188286

Claim:
An integrated circuit (IC), comprising: a multiplicity of mode-control signals, each adapted to assume one of at least two states; a multiplicity of scan-chains, each comprising at least one flip-flop; a multiplicity of blocking circuits, each of said blocking circuits receiving at least one data-in signal and adapted to be responsive to at least one mode-control signal, each of said multiplicity of blocking circuits providing serial scan data to at least one flip-flop of said multiplicity of scan-chains; wherein each of said blocking circuits outputs a value that is representative of a combination of a value on said at least one data-in signal of said blocking circuit and at least one value of at least one scan bit position previous to said at least one flip-flop, in at least a first state of said multiplicity of mode control inputs; and each of said blocking circuits outputs a constant value, in at least a second state of said multiplicity of mode control inputs.