Patent ID: 8089641

Claim:
An image processing apparatus comprising: a controller for generating expanded image data; a local bus connected with the controller; a first generic bus and a second generic bus which are independent from each other and each of which has a data transmission speed lower than that of the local bus and which are provided outside of any image processing section; a first image processing section being directly connected to the first generic bus and not connected to the second generic bus, and a second image processing section being directly connected to the second generic bus and not connected to the first generic bus, for executing image processing of the expanded image data to generate processed image data, wherein the first and second image processing sections are configured with independent hardware from each other; a first bridge which connects the local bus with the first generic bus, and a second bridge which connects the local bus with the second generic bus; and a memory section, being connected to the local bus, for storing at least one of the expanded image data and the processed image data, wherein the first and second image processing sections share execution of image processing of the expanded image data generated by the controller, and the memory section memorizes the processed image data; wherein the controller controls to make a time-sharing between an access of the first image processing section to the memory section through the first generic bus, the first bridge and the local bus, and an access of the second image processing section to the memory section through the second generic bus, the second bridge and the local bus.