Patent ID: 7310010

Claim:
A duty cycle corrector comprising: a first controllable delay configured to delay a first signal to provide a second signal; a second controllable delay configured to delay the second signal to provide a third signal; a phase detector configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal; and a compensation circuit configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal; wherein the compensation circuit comprises a first delay circuit configured to delay the first signal to provide the fourth signal and a second delay circuit configured to delay the second signal to provide the fifth signal, and wherein a delay of the first delay circuit and a delay of the second delay circuit are set based on a phase difference between a test mode signal delayed by the first controllable delay and the second delay circuit and the test mode signal delayed by the second controllable delay and the first delay circuit.