Patent ID: 8493900

Claim:
An apparatus, comprising: a radio frequency (RF) module to perform parallel processing of a plurality of paging broadcasts corresponding to a plurality of servicing cells to generate a plurality of demodulated signals; a hardware accelerator module, coupled to the RF module, to process the plurality of demodulated signals to generate a corresponding plurality of soft symbol groups such that each soft symbol group corresponds to one of the plurality of servicing cells, wherein the hardware accelerator module includes a memory module to store each of the plurality of soft symbol groups; a host processor module, coupled to the hardware accelerator module, to: perform serial Viterbi decoding of each of the plurality of soft symbol groups to generate a plurality of broadcast channel transport blocks such that each broadcast channel transport block corresponds to one of the plurality of servicing cells; and perform serial processing of the plurality of broadcast channel transport blocks to generate a plurality of system frame numbers, for use in timing synchronization with respect to the plurality of servicing cells, such that each frame number corresponds to one of the plurality of servicing cells; and a control module, coupled to the RF module, the hardware accelerator module, and the host processor module, to: turn on each of the RF module, the hardware accelerator module, and the host processor module at a beginning of a wakeup period; turn off the RF module after each of the plurality of soft symbol groups is stored in the memory module; turn off the hardware accelerator module after the host processor module has generated the plurality of broadcast channel transport blocks; and turn off the memory module and the host processor module after the plurality of system frame numbers is generated and output to a higher protocol layer module.