Patent ID: 7506079

Claim:
A data processor comprising: a bus; a central processing unit coupled to the bus; a memory coupled to the bus; a serial I/O device connected to the bus and connectable to an external device for simultaneously transmitting and receiving data to and from the external device, the serial I/O device generating a first activation request signal and a second activation request signal; a transmission direct memory access controller coupled to the bus for transferring transmission data, which is to be transmitted to the external device, from the memory to the serial I/O device; and a reception direct memory access controller coupled to the bus for transferring received data, which is received from the external device, from the serial I/O device to the memory; wherein the serial I/O device includes: a transmission buffer in which the transmission data transmitted from the memory can be stored; a reception buffer in which the received data, received from the external device, can be stored; and a control circuit, coupled to the transmission buffer and the reception buffer, for transmitting the transmission data in the transmission buffer to the external device when there is a space to store data to be received from the external device in the reception buffer of the serial I/O device of the data processor.