Patent ID: 6965139

Claim:
A semiconductor device having co-loaded semiconductor memory composed of a memory cell portion and a peripheral circuit portion and a logic circuit on the same semiconductor substrate, the semiconductor device comprising: (a) a capacitive element in the memory cell portion and covered by a flattening insulating layer; (b) a first metal layer that consists of a buried metal layer embedded within a connecting hole passing through first and second insulating films, wherein the logic circuit is connected to a diffusion layer formed in the semiconductor substrate or connected to a lower layer wiring on the semiconductor substrate; (c) a first metal wiring layer connected to the first metal layer; (d) first and second insulating layers sandwiching the first metal wiring layer from above and below, wherein the first metal wiring layer is formed on and in contact with the first insulating layer and the second insulating layer covers the first metal wiring layer; (e) a second metal layer that consists of a buried metal layer embedded within a connecting hole passing through a portion of the second insulating layer and connected to the first metal wiring layer; (f) a second metal wiring layer that is formed on the flattening insulating layer located above the capacitive element and connected to the second metal layer; (g) a groove that passes through the first and second insulating layers and that is formed in the memory cell portion; (h) the capacitive element being formed through the first and second insulating layers and in the groove, wherein the capacitive element includes a memory node electrode and a plate electrode, the capacitive element having a comb configuration and the plate electrode does not extend beyond the capacitive element, wherein the plate electrode is formed on the second insulating layer; and wherein the plate electrode includes a wire taking-out portion; (i) a dielectric layer in the interior of the groove and on a layer-insulating layer and a comb-like upper electrode covering the dielectric layer; and (j) a concavity portion formed in such a way as to surround the memory cell portion, wherein the wire taking-out portion is formed along the concavity portion, and wherein a contact layer, extended from the second metal wiring layer, is connected to a midway position of the wire taking-out portion, and wherein the height of the portion at which the contact layer and the wire taking-out portion are connected to each other is approximately equal to the height of the first metal wiring layer.