Patent ID: 6891775

Claim:
A semiconductor integrated circuit device comprising: a memory cell array; a chip enable transition detection circuit which detects transition of a chip enable signal that indicates a start of an operation of the memory cell array; a first address transition detection circuit which detects transition of a row address signal that indicates a row address of the memory cell array and transition of a column address signal that indicates a column address; a write enable transition detection circuit which detects transition of a write enable signal that indicates a write operation of the memory cell array; a first control circuit comprising a timeout circuit which generates a control signal that controls row access of the memory cell array on the basis of detection results of the chip enable transition detection circuit, the first address transition detection circuit, and the write enable transition detection circuit; a second address transition detection circuit which detects only the transition of the column address signal; a second control circuit which controls column access of the memory cell array on the basis of a detection result of the second address transition detection circuit; and a mode determination circuit which determines a start of a mode in which column access is executed and generates a mode determination signal when a condition that allows a start of a column access operation of the memory cell array is satisfied, and the second address transition detection circuit detects the transition of the column address, or determines an end of column access and sets a standby state when column access starts, and transition of a predetermined address or a row address is detected, wherein when the mode determination circuit determines row access, the access operation of the memory cell array is controlled by the timeout circuit in the first control circuit in read and write operations for the memory cell array, and when the mode determination circuit determines column access, an active operation is continued while stopping control by the timeout circuit until column access is ended in the read and write operations for the memory cell array.