Patent ID: 8916467

Claim:
A method of forming a semiconductor structure comprising: forming a shallow trench isolation structure in a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate including a bottom semiconductor layer having a doping of a first conductivity type; forming a via cavity through said shallow trench isolation structure and a buried insulator layer, wherein sidewalls of said via cavity includes sidewalls of said shallow trench isolation structure and sidewalls of said buried insulator layer, and a top surface of said bottom semiconductor layer is physically exposed at a bottom of said via cavity; forming, after formation of said via cavity, a doped semiconductor region in a bottom semiconductor layer, wherein said doped semiconductor region abuts said buried insulator layer and has a doping of a second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type, and wherein at least a portion of said doped semiconductor region underlies said top semiconductor layer, wherein a bottom surface of said doped semiconductor region and sidewalls of said doped semiconductor region form a set of contiguous interfaces between a semiconductor material of said first conductivity type and a semiconductor material of said second conductivity type; depositing a conductive material directly on said sidewalls of said shallow trench isolation structure and said sidewalls of said buried insulator layer and said doped semiconductor region having said doping conductivity type and over said top semiconductor layer; removing all portions of said conductive material above a top surface of said top semiconductor layer by a planarization process, wherein a remaining portion of said conductive material below a horizontal plane including said top surface of said top semiconductor layer constitutes a conductive via in contact with said doped semiconductor region having said doping of said second conductivity type; forming, after formation of said conductive via, at least one field effect transistor on a semiconductor material portion in said top semiconductor layer; forming a middle-of-line (MOL) dielectric layer over said at least one field effect transistor and said shallow trench isolation structure and said contact via.