Patent ID: 6898126

Claim:
A method of programming a non-volatile memory, the non-volatile memory comprising: n cell transistors cascaded in series, each cell transistor having a control gate, a floating gate, a source, and a drain; a local bit line positioned above the n cell transistors, the local bit line being electrically connected to a drain of a 1 st cell transistor; a buried local bit line positioned under the n cell transistors, the buried local bit line being electrically connected to the drain of the 1 st cell transistor; and a source line positioned under the buried local bit line, the source line capable of being electrically connected to a source of a n th cell transistor; the method comprising: (a) inputting a word line voltage to a control gate of a k th cell transistor; and (b) floating the local bit line, and inputting a first source line voltage to the source line for increasing a voltage difference between the control gate of the k th cell transistor and the buried local bit line through capacitance coupling between the buried local bit line and the source line; wherein the voltage difference is used to adjust an amount of electrons stored on the floating gate of the k th cell transistor for programming the k th cell transistor.