Patent ID: 8365142

Claim:
A method, comprising: under control of a processor configured with specific executable instructions to perform acts comprising: a hypergraph template library comprising: a plurality of bulk data areas forming at least a portion of an application configured for execution on a multi-core computing device, and a plurality of hypergraphs that include: a plurality of pointers such that the multi-core computing device that runs the application accesses a second processor, the second processor including cache memory and main memory, wherein the application captures the plurality of pointers in the cache memory and captures a plurality of data structures in the main memory; and a basic hypergraph that comprises a hyperedge table, a tentacle table, a vertex table and a backpointer table, wherein the tentacle table and the backpointer table are ghosted to form one of the plurality of data structures such that when the tentacle table and the backpointer table are statically known, the tentacle table and the backpointer table are not stored in memory at runtime and only the known value is stored in memory at runtime.