Patent ID: 8885773

Claim:
A receiver that decodes data from an analog signal, the receiver comprising: a matching network component that is connected to a mixer/phase detector component, the mixer/phase detector component being connected to a first amplifier component, wherein the first amplifier is a low noise amplifier, the first amplifier being connected to a first filter/amplifier component, the first filter/amplifier component being connected to a filter component, an oscillator that is connected to the filter component, a second amplifier that is connected to the oscillator, and an analog-to-digital converter, wherein the converter digitizes the signal and wherein the mixer/phase detector component, first amplifier component, first filter/amplifier component, filter component, and oscillator are arranged in a loop, wherein the oscillator generates a single phase, wherein the receiver is a single path ultra low power receiver comprising a limiter, wherein the receiver provides phase and frequency of received signals, wherein the receiver is used for FSK, GMSK or PSK signal detection without the need for an analog-to-digital converted, and wherein the arrangement of the components forms a phase locked loop architecture which provides frequency offset tracking capability and mitigates the requirement of frequency reference stability.