Patent ID: 8039946

Claim:
A chip package structure, comprising: a single lead frame, comprising: a die pad; a plurality of inner leads disposed around the die pad; at least one bus bar located between the die pad and the inner leads, wherein the die pad is connected to the bus bar and is supported by the bus bar; an insulating layer disposed on the bus bar, wherein the bus bar is arranged without intersecting with the inner leads that are not connected to the bus bar; a plurality of transfer bonding pads disposed on the insulating layer; a chip disposed on the leadframe, wherein the chip has an active surface and a plurality of chip bonding pads, the chip bonding pads are disposed on the active surface; a plurality of first bonding wires respectively connecting the chip bonding pads and the transfer bonding pads; and a plurality of second bonding wires respectively connecting the transfer bonding pads and the inner leads.