Patent ID: 7475230

Claim:
A method for performing register file checkpointing to support speculative execution within a processor, comprising: commencing speculative execution of a program from a point of speculation, at which the outcome of a long latency instruction is speculatively predicted; wherein updating a register with a new value during the speculative execution involves, checkpointing an old value of the register when the register has not already been checkpointed, wherein checkpointing the old value of the register involves: determining if the register has already been checkpointed by examining a checkpoint table, wherein the checkpoint table contains an entry for each architectural register, wherein each entry comprises a single bit specifying if the corresponding register has been checkpointed during the speculative execution, and if the register has not already been checkpointed, checkpointing the old value for the register, and updating the checkpoint table to indicate that the register has been checkpointed, and updating the architectural state of the register with the new value; whereby only registers that are updated during the speculative execution are checkpointed, instead of checkpointing all of the architectural registers prior to commencing speculative execution.