Patent ID: 7961832

Claim:
An apparatus for recovering a symbol clock associated with a symbol stream in a communication receiver, comprising: a digital delay line having an input for receiving a symbol clock signal, said digital delay line having an output for providing the symbol clock; a digital control circuit coupled to said digital delay line for providing thereto a digital control signal, said digital delay line for phase-adjusting said symbol clock signal based on said digital control signal to produce said symbol clock, said digital control signal indicative of a timing relationship between said symbol clock and symbol transitions in said symbol stream; wherein said digital control circuit includes a digital transition detection circuit having an input for receiving said symbol stream, said digital transition detection circuit responsive to said symbol stream for outputting a transition detection signal indicative of symbol transitions in said symbol stream; wherein said digital control circuit includes a digital phase detection circuit coupled to said digital transition detection circuit for receiving said transition detection signal, said digital phase detection circuit having an input for receiving said symbol clock, said digital phase detection circuit operable for determining a phase difference between said symbol clock and said transition detection signal, said digital phase detection circuit having an output coupled to said digital delay line input for providing said control signal to said digital delay line, said control signal indicative of said phase difference between said symbol clock and said transition detection signal; and wherein said digital phase detection circuit includes a transition timer coupled to said transition detector and responsive to said transition detection signal for producing a compare signal, said compare signal active for a predetermined period of time after each symbol transition indication of said transition detection signal.