Patent ID: 7493599

Claim:
A method comprising: during translation of a code block in a system comprising a hardware processor from a first format suitable for a first computing platform to a second format suitable for a second computing platform, inserting one or more instructions in said code block to detect whether execution of said code block results in a misaligned data access prior to execution of said code block; storing a location of a first memory address in a tracking list for storing the location of memory addresses for which misaligned data access is detected if accessing the first memory address by a first instruction results in the misaligned data access; adding one or more instructions to the first instruction; checking the tracking list to determine if a location of a second memory address is identical to the location of the first memory address when a second instruction requires access to the second memory address; and obviating the need to add instructions to the second instruction if the location of the second memory address accessed by the second instruction is identical to the location of the first memory address.