Patent ID: 7728565

Claim:
An LDO voltage regulator comprising: an output terminal for providing a regulated voltage output to a load, a plurality of PFETs connected in parallel, wherein each PFET drains a level of current and the sum of the levels of current are provided as a current output at the output terminal, and all drains of the plurality of PFETs are directly tied together to provide the regulated voltage output to the load, a sensing network, including a sensing PFET, connected to the plurality of PFETs for sensing the level of current drained by each of the plurality of PFETs, wherein the sensing PFET includes a drain, which is not tied to the drains of the plurality of PFETs, and an error amplifier coupled between the output terminal and the sensing network for providing a voltage to the sensing network, wherein a summation of the drains of current from each PFET is provided as the current output to regulate the voltage output at the output terminal, and the sensing network senses the level of current drained by each PFET of the plurality of PFETs, and provides the sensed level of current as an output control signal.