Patent ID: 7539590

Claim:
A method of testing a memory device having a plurality of memory instances and a built-in self test and repair (BISTR) processor integrated therein, the method comprising: sending test information from said BISTR processor to a respective test and repair wrapper integrated with each of said memory instances; providing a strobe control signal to each said respective test and repair wrapper for signaling commencement of testing operations with respect to a respective memory instance of said plurality of memory instances; generating, by each said respective test and repair wrapper, at least one of an address signal, a data signal and a command signal based on said test information; executing at least one test by each said respective test and repair wrapper with respect to said respective memory instance based on said address, data and command signals, wherein said at least one test comprises at least one of a back-to-back memory operation and a simultaneous read/write operation; and responsive to executing said at least one test, providing error signals to said BISTR processor for effectuating appropriate repair control logic.