Patent ID: 8139702

Claim:
An apparatus for recovering a clock signal, the apparatus comprising: a phase detector configured to receive an input data signal and to receive a recovered clock signal, the phase detector further configured to generate a signal with an indication of a phase difference between the input data signal and the recovered clock signal; a feedback circuit operatively coupled to the phase detector, the feedback circuit configured to receive the generated signal from the phase detector and to receive a reference signal, the feedback circuit configured to generate the recovered clock signal, wherein the feedback circuit is configured to select a first locking range when phase lock has not been detected, wherein the first locking range is less than a frequency modulation associated with the input data signal, and being configured to select a second locking range broader than the first locking range when phase lock between the recovered clock signal and the input data signal has at least momentarily been detected, wherein the second locking range is sufficient to sustain lock to the input data signal over a full cycle of the frequency modulation associated with the input data signal, wherein the feedback circuit generates the recovered clock signal in a phase-locked manner while operating with the second locking range; a phase tracking path; and a frequency tracking path with an accumulator, the accumulator having at least one range limit that is dynamically selectable for dynamic selection of the limit of the locking range of the feedback circuit.