Patent ID: 7639550

Claim:
A semiconductor memory device comprising: a pair of local input/output (IO) lines; a global IO line; a local driver configured to pull up/down voltage levels of the local IO lines in response to input data; a global driver configured to pull up/down a voltage level of the global IO line according to input data; and a data IO control block configured to transport output data from the local IO lines to the global driver and input data from the global IO line to the local driver, wherein the data IO control block includes an amplification unit configured to amplify the input data selectively provided through first and second sense nodes and the output data selectively provided through the first and second sense nodes in response to read and write operation signals, wherein the data IO control block further includes: a first input unit used to receive the output data in response to the read operation signal; a second input unit used to receive the input data in response to the write operation signal; the amplification unit used to amplify the output data provided by the first input unit through the first and second sense nodes and the input data provided by the second input unit through the first and second sense nodes; and data output units used to output the output data and the input data amplified at the amplification unit, wherein the local driver pulls up/down the voltage levels of the local IO lines according to the input data provided by the data output units in response to the write operation signal, wherein the global driver pulls up/down the voltage level of the global IO line according to the output data provided by the data output units in response to the read operation signal, wherein the data IO control block further includes a precharge unit used to precharge the first and second sense nodes in response to the read operation signal and the write operation signal, wherein the first input unit includes: a first metal oxide semiconductor (MOS) transistor receiving the read operation signal through a gate of the first MOS transistor and including one terminal coupled to a terminal of a ground voltage; a second MOS transistor receiving a signal from a first local IO line through a gate of the second MOS transistor and coupled between a first input node and the first MOS transistor; and a third MOS transistor receiving a signal from a second local IO line through a gate of the third MOS transistor and coupled between a second input node and the first MOS transistor.