Patent ID: 8680685

Claim:
A semiconductor package comprising: a semiconductor chip having a first bump group including a plurality of first bumps and a second bump group including a plurality of second bumps; and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the plurality of first bumps are commonly disposed on the first pattern and are commonly connected to the first pattern, and the plurality of second bumps are commonly disposed on the second pattern and are commonly connected to the second pattern, wherein the first pattern comprises a first land and a first extension portion extending from the first land, and the second pattern comprises a second land and a second extension portion extending from the second land, the first extension portion having a width smaller than a width of the first land, and the second extension portion having, a width greater than a width of the second land and wherein the plurality of first bumps comprise a first real bump disposed on the first land and a plurality of first dummy bumps disposed on the first extension portion, and the plurality of second bumps comprise a second real bump disposed on the second land and a plurality of second dummy bumps disposed on the second extension portion.