Patent ID: 7374971

Claim:
A method of making an integrated circuit, comprising: providing a semiconductor wafer having a major surface; forming active circuitry on the major surface of the semiconductor wafer; forming a dielectric layer over the active circuitry; forming an interconnect layer over the dielectric layer; forming a plurality of bond sites over the interconnect layer; performing a cutting operation to form a plurality of grooves through the interconnect layer, the dielctric layer and partially through the semiconductor wafer; applying a sealing material to coat the inside of each of the plurality of grooves, wherein the sealing material is not applied over a substatial portion of the major surface of the semiconductor wafer; and performing a separating operation to separate the semiconductor wafer into a plurality of singulated integrated circuit die, wherein the separtaing operation begfins in the plurality of grooves after the sealing material is applied, and wherein the sealing material remains on a side of the groove after the separating operation.