Patent ID: 8753931

Claim:
A method of fabricating a semiconductor device, comprising: forming a first gate structure and a second gate structure over a substrate, the first gate structure and the second gate structure each including a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer; forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure; polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure; replacing portions of the second gate structure with a metal gate; and after replacing portions of the second gate structure with the metal gate, performing a silicidation process to the semiconductor device, wherein performing the silicidation process to the semiconductor device includes performing the silicidation process to the polysilicon layer of the first gate structure to form a silicide feature.