Patent ID: 7439138

Claim:
A method of forming integrated circuitry comprising: providing a substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent conductive structures received over the substrate in at least a first cross-section, the second circuitry area comprising a second pair of spaced adjacent conductive structures received over the substrate in at least a second cross-section, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section, first anisotropically etched insulative sidewall spacers being received over sidewalls of the conductive structures of the first and second pair; depositing a masking material between the conductive structures of each of the first and second pairs; and anisotropically etching the masking material effective to form sidewall spacers over the first anisotropically etched sidewall spacers of each of the conductive structures of the second pair and leave at least some of the masking material spanning between the first anisotropically etched sidewall spacers of each of the conductive structures of the first pair at the conclusion of said anisotropically etching.