Patent ID: 8578242

Claim:
A data storage device comprising: a non-volatile memory comprising a plurality of memory segments; and control circuitry operable to: receive a read command identifying a plurality of logical block addresses (LBAs); map the LBAs to physical block addresses (PBAs) addressing the memory segments; generate at least two seed values corresponding to two of the LBAs; store the seed values in an array; after storing the seed values in the array: index the array with an index value to access a first one of the seed values corresponding to a first LBA; seed an error code generator with the first seed value; read data from a first memory segment corresponding to the first LBA; generate a first error code using the error code generator; increment the index value; index the array with the incremented index value to access a second one of the seed values corresponding to a second LBA; seed the error code generator with the second seed value; read data from a second memory segment corresponding to the second LBA; and generate a second error code using the error code generator.