Patent ID: 7501878

Claim:
An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal, comprising: an inverter that has a first conductivity-type transistor (M 1 ) and a second conductivity-type transistor (M 2 ) connected in series in between a source power line and a sink power line which complementarily become conductive and outputs the output signal into which the input signal has been inverted in logic level; a first drive transistor (Q 1 ) that is provided between the source power line and the first conductivity-type transistor (M 1 ) and drives the first conductivity-type transistor (M 1 ); a second drive transistor (Q 4 ) that is provided between the second conductivity-type transistor (M 2 ) and the sink power line and drives the second conductivity-type transistor (M 2 ); a voltage divider that has a first resistor (R 1 ), a first diode-connected transistor (Q 5 ), a second resistor (R 3 ), a third resistor (R 4 ), a second diode-connected transistor (Q 6 ), and a fourth resistor (R 6 ) connected in series between the source power line and the sink power line and applies potential of a control electrode of the first diode-connected transistor (Q 5 ) to a control electrode of the first drive transistor (Q 1 ) and applies potential of a control electrode of the second diode-connected transistor (Q 6 ) to a control electrode of the second drive transistor (Q 4 ); a fifth resistor (R 5 ) that is provided between a first connection point of the first drive transistor (Q 1 ) and the first conductivity-type transistor (M 1 ), and the sink power line and adjusts a current flowing through the first drive transistor (Q 1 ); and a sixth resistor (R 2 ) that is provided between the source power line and a second connection point of the second conductivity-type transistor (M 2 ) and the second drive transistor (Q 4 ) and adjusts a current flowing through the second drive transistor (Q 4 ), wherein by setting a current flowing through the first diode-connected transistor (Q 5 ) and the current flowing through the first drive transistor (Q 1 ) to be in a predetermined relationship, variation with temperature in potential at the first connection point is removed, and by setting a current flowing through the second diode-connected transistor (Q 6 ) and the current flowing through the second drive transistor (Q 4 ) to be in a predetermined relationship, variation with temperature in potential at the second connection point is removed.