Patent ID: 8154126

Claim:
A semiconductor workpiece for fabricating a plurality of semiconductor devices, comprising: a wafer having a substrate composed of a semiconductor material, the substrate having an active side and a backside; a plurality of dies having integrated circuitry on the active side of the substrate and a plurality of bond-pads electrically coupled to the integrated circuitry; a protective layer formed on the backside of the substrate, wherein the protective layer is a flowable material; a redistribution layer having a dielectric layer formed over the dies, ball-pads arranged in ball-pad arrays corresponding to the dies and traces coupling the bond-pads of a die to the ball-pads of a corresponding ball-pad array wherein the traces are embedded in the dielectric layer and the bond-pads embedded in but not covered by the dielectric layer; a plurality of solder balls on the ball-pads; and a protective film over the dielectric layer and surrounding a portion of the solder balls and covering the ball-pads.