Patent ID: 8751999

Claim:
A method comprising: by one or more computing devices, creating a layout for a Printed Circuit Board (PCB), comprising: creating n boundary lines at n locations, respectively, on the PCB; and randomly placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied, and wherein for iteratively evaluating the layout of the PCB, each iteration comprises: computing a cost of the layout of the PCB based on the set of layout requirements; generating, by a random value generating function, a random value; computing a value to evaluate a currently best layout of the PCB, the value computed based on at least a cost of the currently best layout of the PCB and a current temperature controlling the iterative process; and if the random value is less than the value, then: setting the currently best layout of the PCB as the layout of the PCB; and setting the cost of the currently best layout of the PCB as cost of the layout of the PCB.