Patent ID: 7954006

Claim:
A method for preventing loss of data in a computer interface board during power failure, comprising: providing a secondary data path to a non-volatile storage element from a cache memory on the computer interface board, the cache memory of the computer interface board being a volatile memory, the secondary data path and the non-volatile storage element enabling reliable memory operation during both normal and power fail modes; providing a secondary power supply to the non-volatile memory and the cache memory in the secondary data path, wherein the secondary power supply is a non-chemical cell power source; detecting an unexpected power failure at the computer interface board, the unexpected power failure resulting in incomplete transactional data within the cache memory; verifying, in response to the unexpected power failure, if any incomplete transactional data is left behind in the cache memory, wherein when incomplete transactional data is left behind in the cache memory, the verifying further includes, (a) verifying status of the incomplete transactional data in the cache memory; (b) activating the secondary power supply to supply power to the secondary data path; and (c) transmitting the incomplete transactional data from the cache memory to the non-volatile storage element through the secondary data path, the non-volatile storage element preserving the transactional data of the cache memory during power failure, wherein the secondary power supply provides sufficient power to supplement power lost due to power failure so as to transfer the incomplete transactional data to the non-volatile memory.