Patent ID: 8032690

Claim:
A non-volatile memory device connected to a host via a bus, the non-volatile memory device comprising: a bus controller, being configured to communicate with the host via the bus; a non-volatile memory; a memory controller, being configured to access the non-volatile memory, and to predict a busy time in which the non-volatile memory can't transfer data; and an auxiliary circuit, for controlling accessing modes of the non-volatile memory device, the auxiliary circuit comprising: a first terminal coupled to the bus controller, a second terminal coupled to the memory controller; a third terminal coupled to the non-volatile memory; a parsing module coupled to the first terminal and the second terminal, being configured to receive and compile an accessing command from the bus controller, and generate a parsing signal in response to the accessing command; an executing module coupled to the parsing module, the second terminal, and the third terminal, being configured to execute a pre-determined accessing mode to read or write the non-volatile memory in response to the parsing signal, wherein the bus controller sets the bus into power saving mode when the non-volatile memory can't transmit data with bus controller during the busy time, the bus controller resumes the bus according to the busy time, and the pre-determined accessing mode can only be executed by the auxiliary circuit.