Patent ID: 8135878

Claim:
A method for bus accessing, comprising: receiving a first bus request for first data from a first direct memory access (“DMA”) engine to a first target module (“TM”); allocating a single data bus to the first DMA engine; setting a first busy signal from the first TM to an active state base on time required to retrieve the first data is greater than one of a plurality of equally partitioned time slots; detecting the first busy signal from the first TM requesting additional time for retrieving the first data; setting a first read pending indicator in a read pending memory in response to the first busy signal; releasing the single data bus in response to the first busy signal and setting of the first read pending indicator; continuing retrieving the first data from a memory device to the first TM while the single data bus is allocated to another DMA engine after the single data bus was released; and reallocating the single data bus back to the first DMA engine for transferring the first data from the first TM to the first DMA engine when the first busy signal is deactivated.