Patent ID: 8082530

Claim:
A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design, the method comprising: generating a low-level circuit design comprising a plurality of low-level circuit elements from the HLMS circuit design; simulating the low-level circuit design and storing power usage data, from the simulating, for each of the plurality of low-level circuit elements; automatically correlating, by a computer, the plurality of low-level circuit elements with the high-level blocks of the HLMS circuit design; providing a power usage application programming interface (API) configured to receive an identifier of a high-level block as an argument; receiving a user-specified query for power usage of a selected high-level block of the HLMS circuit design via the power usage API, wherein the query specifies an identifier of the selected high-level block; wherein the HLMS circuit design is displayed in the form of a plurality of graphical blocks comprising the selected high-level block, wherein each graphical block represents a circuit function; determining a measure of power usage for the selected high-level block according to the power usage data for selected ones of the plurality of low-level circuit elements correlated with the selected high-level block; and outputting the measure of power usage for the selected high-level block.