Patent ID: 7554360

Claim:
A CMOS level shifter circuit comprising: an input transistor; an output transistor; an inverter arranged between said input and output transistors and in communication with a first level voltage supply; a first pull-up transistor in communication with said input transistor and a second level voltage supply; a second pull-up transistor in communication with said output transistor and said second level voltage supply; and a boost circuit, in communication with at least one of said first and second pull-up transistors, wherein the boost circuit includes: first and second boost pull-up transistors with a source or a drain of said first boost pull-up transistor coupled to a source or drain of either said first or second pull-up transistors and a source or drain of said second boost pull-up transistor coupled to the other of said source or said drain of either said first or second pull-up transistors; and at least one boost biasing transistor with a source or drain coupled to a gate of one of said first and second boost pull-up transistors and the other of said source or drain of said at least one boost biasing transistor coupled to said second level voltage supply.