Patent ID: 8510588

Claim:
A semiconductor device comprising: a power supply circuit comprising a regulator; a first circuit configured to receive a first clock signal and a first signal and output a second signal; and a second circuit configured to receive the second signal and output a second clock signal, wherein the power supply circuit is configured to supply a power supply voltage regulated by the regulator to the first circuit and the second circuit, wherein the first circuit is configured to increment a value of the second signal in accordance with the first clock signal, wherein the first circuit is configured to reset the value of the second signal in accordance with the first signal, wherein the second circuit is configured to generate the second clock signal, wherein a cycle of the second clock signal corresponds to a period while the value of the second signal grows by a value, and wherein a first cycle of the second clock signal in a first period is longer than a second cycle of the second clock signal in a second period.