Patent ID: 8687709

Claim:
In a computing device that implements a video decoder, the computing device including a processor and memory, a method comprising: receiving, at the computing device that implements the video decoder, encoded data for video in a bit stream, wherein bit stream syntax for the bit stream includes frame level, macroblock level and block level; with the computing device that implements the video decoder, decoding an interlaced frame coded picture of the video using the received encoded data, including: using one or more transform level syntax elements to select the frame level, the macroblock level, or the block level of bit stream syntax as including frequency transform block/sub-block size information, wherein the video decoder is configurable, depending on the one or more transform level syntax elements, to set frequency transform block/sub-block size for the interlaced frame coded picture, to switch the frequency transform block/sub-block size between macroblocks in the interlaced frame coded picture, and to switch the frequency transform block/sub-block size between blocks in the interlaced frame coded picture; obtaining field/frame type information for a current macroblock in the interlaced frame coded picture; obtaining the frequency transform block/sub-block size information for plural blocks in the current macroblock, the frequency transform block/sub-block size information indicating the frequency transform block/sub-block size from among plural possible frequency transform block/sub-block sizes; selecting one or more block boundaries for in-loop deblocking, wherein the selecting is based at least in part on the frequency transform block/sub-block size information and the field/frame type information; and performing in-loop deblocking on the selected block boundaries.