Patent ID: 7893979

Claim:
An XY address type solid-state imager apparatus comprising a solid-state imager having a plurality of pixels two-dimensionally arranged and horizontal and vertical scanning circuits to read signals of the pixels, wherein the scanning circuits each have a progressive scanning circuit to progressively read out pixel signals by a first scanning control signal and an interlace scanning circuit to read pixel signals with an interlaced manner by a second scanning control signal different from the first scanning control signal, the XY address type solid-state imager apparatus arbitrarily carries out combining of progressive reading and interlace reading in one frame in accordance with a combination of the respective scanning control signals, and reads pixel signals, and the scanning circuits each are configured such that shift register circuits which are unit stages are connected in multiple stages, each register circuit further has a plurality of information transmitting units which transmit information by separate clocks and a storage unit which stores an output of each shift register circuit, and an arbitrary area in one frame is read by starting scanning based on the information stored in the storage unit.