Patent ID: 8283237

Claim:
A through-silicon via fabrication method comprising: (a) forming a silicon plate having a front surface, one or more features therein, and a back surface; (b) providing a carrier for supporting the silicon plate; (c) forming a substrate by bonding the front surface of the silicon plate to the carrier using an adhesive layer therebetween to expose the back surface of the silicon plate; (d) depositing a silicon nitride passivation layer on the exposed back surface of the silicon plate of the substrate; (e) etching a plurality of through holes in the silicon plate, the through holes comprising sidewalls and a bottom wall; (f) depositing in each of the through holes: (i) an oxide liner on the sidewalls and bottom wall of the through holes; (ii) a sealing layer over the oxide liner, the sealing layer comprising silicon nitride; and (iii) a metallic conductor over the sealing layer to form a plurality of through-silicon vias; (g) after (f), chemical mechanical polishing the back surface of the silicon plate to expose the to portions of the metallic conductor deposited into the through holes of the silicon plate; (h) removing a native oxide film formed on the exposed portions of the metallic conductor in the through holes by (1) maintaining the substrate at a first temperature of from about 100° C. to about 220° C. in a process zone comprising a pair of process electrodes, (2) introducing into the process zone, a reducing gas comprising ammonia or hydrogen, and (3) applying a first power to the process electrodes; and (i) after (h), performing a silane soaking step comprising (1) maintaining the substrate at a second temperature of from about 100° C. to about 220° C. in the process zone comprising the pair of process electrodes, (2) introducing into the process zone, a soaking gas comprising silane, and (3) applying a second power to the process electrodes.