Patent ID: 7772638

Claim:
A non-volatile memory device comprising: a semiconductor substrate; a device isolation region isolating a first active region and a second active region formed on the semiconductor substrate; a well region having a first type dopant formed in both the first active region and the second active region; a junction region having a second type dopant formed on the well region, wherein the second type of dopant is opposite to the first type dopant; a sense transistor for read operation formed in the first active region comprising a first insulating layer, a polysilicon gate, a drain region and a source region, a first capacitor electrode for electric charge or discharge during write/erase operation formed in the first active region sharing the drain region of the sense transistor, and a tunneling insulating layer formed between the tunneling gate and the junction region; a second capacitor electrode for voltage coupling formed in the second active region, and a second insulating layer formed between the second capacitor electrode and the junction region; a first metal line which connects the sense transistor to the second capacitor electrode and a second metal line which connects the first capacitor electrode to the second capacitor electrode, the first metal line and the second metal line being physically separated, wherein the second capacitor electrode is disposed not to overlap the device isolation region in order to reduce parasitic capacitance, wherein the drain region is spaced apart from the polysilicon gate by a predetermined distance and is enclosed by the junction region to mitigate the electric field, and the drain region and the source region have the second type dopant; wherein the polysilicon gate of the sense transistor, the first capacitor electrode and second capacitor electrode are configured to be physically separated from one another and isolated by the device isolation region.