Patent ID: 7558987

Claim:
A testing system, comprising: a target system comprising: a first processor core configured to generate first trace data wherein the first trace data describes actions of the first processor core as the first processor core executes, a first data select logic unit coupled to the first processor core to receive the first trace data, a second processor core configured to generate second trace data, wherein the second trace data describes actions of the second processor core as the second processor core executes, and a second data select logic unit coupled to the second processor core to receive the second trace data and coupled to the first data select logic unit to receive the first trace data; and a host computer coupled to the target system by way of a connection and adapted to debug an application executing on the first processor core and the second processor core using the first trace data and the second trace data received via the connection; wherein the target system is configured to send trace data via the connection to the host computer by a method comprising: determining by the second data select logic whether the second processor core has a token, wherein the token assigns priority to valid trace data from a processor core having the token and wherein only one processor core has the token at a time, and when the second processor core has the token and the second trace data is valid, transmitting the second trace data, and sending a stall signal to the first processor core to indicate that the first trace data was not transmitted.