Patent ID: 8169850

Claim:
An apparatus comprising: a first multi-chip package (MCP) including a first dual processor formed on a first semiconductor die and a second dual processor formed on a second semiconductor die, each of the first and second dual processors including: a plurality of cores; a caching agent logic coupled to the plurality of cores; a home agent logic coupled to the caching agent logic and to a memory controller of the corresponding dual processor; and a link logic coupled to the home agent logic and the caching agent logic via a switch of the corresponding dual processor, wherein the link logic is to interface with a first point-to-point (PtP) link coupled between the first MCP and a first off-package agent, a second PtP link coupled between the first MCP and a second off-package agent, and a third PtP link coupled between the first and second dual processors of the first MCP, wherein the third PtP link is to operate at an independent bandwidth from the first and second PtP links to balance traffic.