Patent ID: 8108596

Claim:
Apparatus for processing data comprising: a memory having one or more banks, each bank having an array of memory cells including a plurality of rows of memory cells and a plurality of columns of memory cells; and a memory controller responsive to a memory access request specifying a memory address to generate at least a row selecting signal, a column selecting signal output to said memory and a chip select signal; wherein said memory controller includes mapping logic responsive to mapping specifying data to apply a programmable mapping between at least some bits of said memory address and respective bits of at least said row selecting signal and said column selecting signal, such that row selecting bits of said memory address that form said row selecting signal and column selecting bits of said memory address that form part of said column selecting signal are selected from said memory address in dependence upon said mapping specifying data, said memory controller using different mappings for at least two portions of said memory having a common chip select signal.