Patent ID: 7589387

Claim:
A memory cell capable of storing 2 bits, the memory cell comprising: a semiconductor fin on a top surface of a substrate, the semiconductor fin having two sidewalls and a top surface, wherein the semiconductor fin comprises a middle channel section, two source/drain regions, and two extension sections, and wherein each of the extension sections is between the middle channel section and the respective source/drain region; a gate insulation film on a top surface and sidewalls of the middle channel section of the semiconductor fin; a gate electrode on the gate insulation film, the gate electrode having two sidewalls on planes substantially perpendicular to a major axis of the semiconductor fin; two tunneling layers, each of the tunneling layers being along one of the sidewalls of the gate electrode and on at least a portion of the semiconductor fin close to the gate electrode; and two charge-trapping regions substantially along opposite sides of the gate electrode, each of the charge-trapping regions being separated from the gate electrode and the semiconductor fin by the respective tunneling layer.