Patent ID: 8247864

Claim:
A semiconductor device having amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structures with one-time programmable (OTP) function, the device comprising: a substrate; a first dielectric layer on the substrate, the first dielectric layer being associated with a first surface; one or more source or drain regions being embedded in the first dielectric layer, each of the one or more source or drain regions including an n-type a-Si layer, a diffusion barrier layer, and a conductive layer, the diffusion barrier layer overlying the conductive layer, the n-type a-Si layer being located on the diffusion barrier layer and associated with a second surface, the second surface being substantially co-planar with the first surface; an intrinsic (i-type) a-Si layer overlying the first surface and the second surface; a p-type a-Si layer overlying the i-type a-Si layer; a second dielectric layer overlying the p-type a-Si layer; at least one control gate overlying the second dielectric layer, the at least one control gate being associated with a drain region of the one or more source or drain regions; and a conductive path formed between the at least one control gate and the associated drain region by applying a certain voltage.