Patent ID: 6885093

Claim:
A stacked multichip package, comprising: a base carrier having a top side and a bottom side; a bottom integrated circuit die having a bottom surface attached to the base carrier top side, and an opposing, top surface, the top surface having a peripheral area including a plurality of first bonding pads and a central area; a bead formed on the top surface of the bottom die between the peripheral area and the central area, wherein the bead does not extend to the first bonding pads; an adhesive material formed in the central area on the top surface of the bottom die, the adhesive material being surrounded by the bead; and a top integrated circuit die having a bottom surface, wherein the top die is positioned over the bottom die and the bottom surface of the top die is attached to the top surf ace of the bottom die via the adhesive material, wherein the bead maintains a predetermined spacing between the bottom die and the top die and wherein the top die and the bottom die are of similar size and shape as the bottom die.