Patent ID: 7089412

Claim:
In a module that contains a set of data-storing devices on a printed circuit board, and that receives control signals from an external controller over a bus for accessing the set of data-storing devices, an adaptive buffering mechanism comprising: buffers to produce control drive signals from the received control signal and to electrically isolate the control drive signals from the received control signals; control-synchronization logic to synchronize the received control signals to a clock to produce clocked control drive signals; and a mode selection mechanism to selectively output either the control drive signals or the clocked control drive signals to access the set of data-storing devices on the module; wherein the module is compatible with host devices requiring modules having a first mode of operation and host devices requiring modules having a second mode of operation that is incompatible with the first mode, the first mode requiring the module to use the control drive signals to access the set of data-storing devices on the module and the second mode requiring the module to use the clocked control drive signal to access the set of data-stored devices on the module.