Patent ID: 8724414

Claim:
A method comprising: receiving an address corresponding to a bit cell within a first bank of a memory, wherein the first bank comprises the bit cell, a first plurality of word lines, and a first reference cell, wherein the bit cell stores a first value, and wherein the address includes a first row address and a first bank address; accessing a second reference cell of a second bank of the memory during a read operation of the bit cell within the first bank of the memory in response to the first reference cell in the first bank being indicated as bypassed, wherein the second bank comprises a second plurality of word lines that is distinct from the first plurality of word lines, wherein the second bank does not include the first plurality of word lines, wherein the second reference cell has a second row address and a second bank address, and wherein the second row address is determined based on the first row address; and determining an output of the bit cell during the read operation based on the first value and a second value of the second reference cell when the first reference cell is indicated as bypassed.