Patent ID: 8003516

Claim:
A method for fabricating a back-end-of-line (BEOL) interconnect structure, the method comprising: forming a first temporary feature on a top surface of a first dielectric layer; depositing a second dielectric layer comprised of a first dielectric material on the top surface of the first dielectric layer; planarizing the second dielectric layer and the first temporary feature such that a layer thickness of the second dielectric layer is approximately equal to a height of the first temporary feature; forming a first conductive feature that extends from a top surface of the second dielectric layer to a conductive element in the first dielectric layer and that is located in the second dielectric layer laterally adjacent to the first temporary feature; removing the first temporary feature from the second dielectric layer to define a first void in the second dielectric layer laterally adjacent to the first conductive feature; and filling the first void formed in the second dielectric layer with a second dielectric material that has a lower dielectric constant than the first dielectric material of the second dielectric layer.