Patent ID: 7436208

Claim:
An integrated circuit, comprising: a carry chain including an initialization stage, a carry stage, and an output stage; the carry chain being part of a Configurable Logic Element of a programmable logic device; mode select circuitry coupled to the carry chain and configurable to put the carry chain in a power-save mode; the mode select circuitry including: mode circuitry coupled to the initialization stage, the mode circuitry configurable for selecting of a voltage level input and for coupling the voltage level input as an initial carry input of the carry chain for the power-save mode; and select circuitry coupled to the mode circuitry to receive a power-save input therefrom and coupled to the carry stage for providing control select signaling thereto; for the power-save input being for the power-save mode, the control select signaling for causing propagation of the initial carry input through the carry stage to provide the initial carry input as interim carry outputs of the carry stage; the output stage coupled to the carry stage for receiving the initial carry input and the interim carry outputs as first value inputs; and the output stage coupled to the select circuitry for receiving the control select signaling therefrom as second value inputs; wherein the output stage is put in a first non-switching steady state mode responsive to processing the first value inputs and the second value inputs for the power-save mode; wherein the carry stage is put in a second non-switching steady state mode responsive to propagation of the initialization input through the carry stage; and wherein the initialization stage in combination with the carry stage forms a series of multiplexers wherein, in the power-save mode, each multiplexer in the series of multiplexers receives the logic low voltage level as an input and provides the logic low voltage level as an output; and wherein the logic low voltage level is a ground voltage level.