Patent ID: 7172959

Claim:
A method for forming a dual damascene interconnection in a semiconductor device, comprising the steps of: forming an etch stop film and an intermetal insulating film sequentially on a lower metal film; forming a via hole to expose a portion of a surface of the etch stop film through the intermetal insulating film; forming a sacrificial film with which the via hole is filled; removing portions of the intermetal insulating film and the sacrificial film to form a trench; removing the sacrificial film to expose the portion of the surface of the etch stop film; performing a plasma etching process at a temperature of 0â€“40Â° C. using a CF 4 /CHF 3 /CH 3 gas and an Ar gas to remove the exposed portion of the etch stop film; forming a diffusion barrier film within the trench and the via hole such that the diffusion barrier contacts the lower metal film; and forming an upper metal film on the diffusion barrier.