Patent ID: 7129556

Claim:
An array substrate comprising: a plurality of gate lines on a substrate, each gate line having at least one gate electrode and a gate-protruded portion; a first insulation layer over the gate lines, over the gate electrodes, over the gate protruded portions, and over the substrate; a plurality of gate line contact holes, each passing through said first insulation to said gate-protruded portions; a conductive shorting element having a plurality of stopper-protruded portions that electrically connect to the gate lines via the gate-protruded portions, wherein said conductive shorting element electrically connects said plurality of gate lines together, and wherein said conductive shorting element is comprised of a conductive material; a plurality of thin film transistors on said first insulation layer, each thin film transistor located over a gate electrode and having a source electrode, a drain electrode, an ohmic contact layer, and a channel region in an active layer; a plurality of drain electrodes, each contacting an ohmic contact layer of an associated thin film transistor; a plurality of data lines on said first insulation layer, each data line having a plurality of source electrodes that electrically contact to a plurality of ohmic contact layers, wherein said plurality of data lines cross said plurality of gate lines to define a plurality of pixel regions; a ground line under each pixel region, said ground line being on said first insulation layer; a first capacitor electrode over said ground line and over a portion of said first insulation layer, said first capacitor electrode electrically connecting to said ground line, wherein said first capacitor electrode is comprised of said conductive material; a protection layer over said thin film transistor, over said data lines, over said source electrodes, over said drain electrodes, over said conductive shorting element, and over said first capacitor electrode; a plurality of second capacitor electrodes on said protection layer and over said first capacitor electrodes; a second insulating layer over said protection layer and over said second capacitor electrodes; and a cutting furrow through said second insulating layer and through said protection layer to said conductive shorting element.