Patent ID: 7883945

Claim:
A method of manufacturing an array substrate comprising: forming one or more silicon patterns on a base substrate comprising a display region and a peripheral region, the peripheral region being formed in an outer area of the display region, the silicon patterns comprising a pixel pattern part formed in the display region, a storage pattern part in the display region, and a driving pattern part formed in the peripheral region; implanting a first impurity at a high concentration simultaneously into a first portion of the pixel pattern part, a first portion of the storage pattern part, and a first portion of the driving pattern part; forming one or more gate metal patterns on the silicon patterns using one or more photosensitive patterns having a first sub-sensitive layer and a second sub-sensitive layer; implanting a second impurity at a high concentration into the first portion of the driving pattern part; implanting the first impurity at a low concentration into a second portion of the pixel pattern part; and forming a pixel electrode that is electrically connected to the first portion of the pixel pattern part implanted with the first impurity at the high concentration, wherein the second impurity is implanted into a second portion of the driving pattern part at a high concentration though the first sub-sensitive layer of the one or more photosensitive patterns.