Patent ID: 8766721

Claim:
A circuit for time gain compensation comprising: a first op-amp comprising an output terminal, the first op-amp configured to conduct a comparison between first and second input voltage signals and output a first op-amp output signal based on the comparison; a first input circuit coupled with the first op-amp and configured to provide the first input voltage signal to the first op-amp, the first input signal being generated based on signal levels of an input control voltage signal and a first reference voltage signal; a second input circuit comprising a first semiconductor element, the second input circuit coupled with the output terminal, the second input circuit configured to provide the second input voltage signal to the first op-amp, the second input voltage signal being generated based on signal levels of the first op-amp output signal and a relatively high voltage signal; and a control circuit coupled with the first semiconductor element and configured to vary a first resistance value of the first semiconductor element to thereby control the first op-amp output signal, the first op-amp output signal comprising the relatively high voltage signal when the input control voltage signal corresponds to the first reference voltage, and the first op-amp output signal comprising a relatively low voltage signal when the input control voltage signal corresponds to a second reference voltage signal, the relatively high voltage signal being higher than the relatively low voltage signal, the first op-amp output signal being input to a gate terminal of a load semiconductor element so as to vary an impedance of the load semiconductor element.