Patent ID: 6931088

Claim:
A signal processing circuit, comprising: a decision feedback equalizer for waveform-equalizing a digital signal in accordance with a clock signal and generating the waveform-equalized digital signal; and a timing recover PLL, connected to the decision feedback equalizer, for generating the clock signal, the clock signal having a phase which is substantially coincident with the phase of the digital signal, based on the phase difference between the digital signal and the clock signal, and supplying the clock signal to the decision feedback equalizer, wherein the decision feedback equalizer includes, a prefilter for filtering the digital signal and generating a filtered digital signal, a decision circuit, connected to the prefilter, for performing a calculation with a feedback signal and the filtered digital signal and generating a calculation signal, and for analyzing the calculation signal in accordance with predetermined criteria to generate a decision signal, a shift register, connected to the decision circuit, for sampling the decision signal in accordance with the clock signal and storing sampling data, wherein the sampling data stored in the shift register is output from the shift register as the waveform-equalized digital signal, a feedback filter, connected to the shift register, for receiving the sampling data and generating the feedback signal using the sampling data, and a loop control circuit for calculating a phase difference between the filtered digital signal and the feedback signal and controlling a feedback loop formed by the decision circuit, the shift register, and the feedback filter based on the phase difference.