Patent ID: 7807525

Claim:
A method for processing a circuit structure, comprising: in an NFET device, implementing an NFET gate stack, an NFET gate insulator, and an n-channel, wherein said n-channel is hosted in a Si based material and underlies said NFET gate insulator, wherein said NFET gate insulator comprises a layer of a first high-k material; in a PFET device, implementing a PFET gate stack, a PFET gate insulator, and a p-channel, wherein said p-channel is hosted in said Si based material and underlies said PFET gate insulator, wherein said PFET gate insulator comprises a layer of a second high-k material; overlaying said first high-k material and said second high-k material with a layer of a cap material, wherein said first and second high-k materials are in direct physical contact with said layer of said cap material; overlaying said cap material with a layer of a gate metal, wherein said layer of said cap material and said layer of said gate metal are in direct physical contact; in said implementing of said NFET gate stack and said PFET gate stack, producing a portion in said NFET gate stack and in said PFET gate stack by patterning said layers of said cap material and of said gate metal, wherein said portion is identical in said NFET device and in said PFET device; overlaying said NFET gate stack and a vicinity of said NFET gate stack with a first dielectric layer; and exposing said NFET device and said PFET device to oxygen, wherein oxygen reaches said second high-k material, and causes a predetermined shift in the threshold voltage of said PFET device, while due to said first dielectric layer oxygen is prevented from reaching said first high-k material.