Patent ID: 8828814

Claim:
A method for fabricating an integrated semiconductor structure, comprising: providing a semiconductor substrate; forming a first active region, a second active region and a plurality of isolation region in the semiconductor substrate; forming a first gate dielectric layer on one surface of the semiconductor substrate; forming an interlayer dielectric layer leveling with a substituted gate electrode layer on the semiconductor substrate; removing the substituted gate electrode layer to form a first trench on the first active region and a second trench on the second active region using the interlayer dielectric layer as a mask; removing the first gate dielectric layer in the second trench and reserving the first gate dielectric layer in the first trench using a first barrier layer on the first trench as a mask; forming a second gate dielectric layer having a thickness smaller than the thickness of the first gate dielectric layer on the bottom of the second trench; and forming metal gates in the first trench and the second trench.