Patent ID: 8318556

Claim:
A method for making a semiconductor integrated circuit memory device, the method comprising: providing a semiconductor substrate; forming an isolation region in the semiconductor substrate; forming a first and a second active regions in the semiconductor substrate, the active regions being separated by the isolation region; forming a plurality of word lines, one or more of the plurality of word lines overlying the first active region, one or more of the plurality of word lines overlying the second active region, at least one of the plurality of word lines overlying the isolation region; depositing a silicon nitride cap layer; forming an interlayer dielectric layer overlying the nitride cap layer; depositing a photoresist layer overlying the interlayer dielectric layer; using a mask pattern to selectively remove a portion of the photoresist layer to form a line type opening, the line type opening exposing a portion of the interlayer dielectric layer overlying at least the first and second active regions and the isolation region; removing a thickness of the interlayer dielectric layer that is exposed in the line type opening of the photoresist; selectively removing a first portion of the silicon nitride cap layer to expose a semiconductor substrate region between the word lines while maintaining a second portion of the silicon nitride cap layer overlying the plurality of word lines; removing a predetermined thickness of the exposed semiconductor substrate; depositing a polysilicon fill material overlying the exposed semiconductor region, the nitride layer overlying the word lines, and the interlayer dielectric layer; and forming a plurality of polysilicon landing contact pads by performing a chemical mechanical planarization process on the polysilicon fill material and the interlayer dielectric layer using the second portion of silicon nitride cap layer as a polish stop layer.