Patent ID: 8181149

Claim:
A method of assembling an electronic circuit design, comprising: performing operations by one or more processors in a computing arrangement, the operations including: instantiating and coupling a plurality of instances of functional blocks in the design in response to designer input, wherein the plurality of instances of functional blocks includes at least one meta block instance and at least one instance that is not a meta block instance; wherein each meta block instance has two or more alternative implementations, each instance that is not a meta block instance has a single implementation, and each implementation is synthesizable; displaying the plurality of instances of functional blocks as respective graphical objects; displaying for designer selection, identifiers of the two or more implementations for the meta block instance from a meta block library; in response to designer selection of one implementation of the two or more instances, storing a specification of the selected one implementation for the meta block instance in association with the design; in response to designer selection of a graphical object corresponding to the at least one meta block instance, displaying a designer-editable version of the one implementation; and storing an updated specification of the one implementation associated with design in response to designer modification of the designer-editable version of the one implementation.