Patent ID: 8225156

Claim:
A method, comprising: performing an external input voltage test on Input-Output (I-O) circuits in a plurality of I-O circuits, wherein the plurality of I-O circuits are segmented together into at least a first I-O segment of two or more I-O circuits, wherein performing an external input voltage test comprises applying an input voltage to a first I-O circuit, capturing I-O input receiver logic, and determining whether the first I-O circuit transfers logic accurately; and providing a first on-chip analog bus to provide external access for an external tester to two or more input-output pins that provide Parametric Test Unit (PMU) functionality to the first I-O segment through at least a first and a second I-O within the first I-O segment, which are directly connected to the external tester, wherein the first on-chip analog bus indirectly connects to the external tester through the first and second I-O circuits, one or more of the remaining I-O circuits in the first segment connect to the external tester via the first on-chip analog bus and connection of the first on-chip analog bus to the first I-O circuit and a second I-O circuit, which are directly connected to the external tester, and the external tester provides the PMU functionality.