Patent ID: 8779754

Claim:
A signal delay measurement circuit, comprising: an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein the test clock signal is a clock input to the input register; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal, wherein the delayed version of the test clock signal is a clock input to the output register; an emulation module connected between an output of the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the output of the input register to arrive at the output register as the delayed version of the test data signal; and a delay chain defined to introduce a selectable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal.