Patent ID: 6937520

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array that has a plurality of memory cells arranged in a row direction and a column direction, respectively, each memory cell having a transistor formed with a floating gate between a channel area and a control gate via an insulation film, the control gates of the memory cells in the same row being mutually connected to form common word lines, and drains of the memory cells in the same column being mutually connected to form common bit lines; word line voltage supply means for selecting the word line connected to the memory cell which is to be programmed with data, and applying a programming gate voltage to the selected word line; and bit line voltage supply means for selecting the bit line connected to the memory cell which is to be programmed with data, and applying a programming drain voltage to the selected bit line; wherein the word line voltage supply means is configured to be able to apply gate voltages to the same memory cell such that the gate voltage applied at and after the second time is different from the gate voltage applied at the first time; and at least one of the word line voltage supply means and the bit line voltage supply means is set to be able to apply a voltage to the same memory cell for a longer application period at the first time than at the second time.