Patent ID: 7577038

Claim:
A semiconductor memory device, comprising: a first data pad group for receiving data according to a first data input/output operation mode, a second data input/output operation mode and a third data input/output operation mode; a second data pad group for receiving data according to the second data input/output operation mode and the third data input/output operation mode; a third data pad group for receiving data according to the third data input/output operation mode; a fourth data pad group for receiving data according to the third data input/output operation mode; a first to a fourth data transferring line wherein each of the data transferring lines corresponds to a plurality of memory cells; a first multiplexing unit for receiving a first input data from the first data pad group to transfer the first input data into one of the first data transferring line and the third data transferring line; a second multiplexing unit for receiving a second input data from the second data pad group to transfer the second input data into one of the second data transferring line and the fourth data transferring line; a first data transferring unit for receiving a third input data from the third data pad group to transfer the received third input data to the third data transferring line; a second data transferring unit for receiving a fourth input data from the fourth data pad group to transfer the received fourth input data to the fourth data transferring line; a third multiplexing unit for transferring data on one of the first data transferring line and the second data transferring line; and a fourth multiplexing unit for transferring data on one of the third data transferring line and the fourth data transferring line.