Patent ID: 8860098

Claim:
A shielded superjunction junction gate field-effect transistor (JFET) comprising: a superjunction charge balanced area comprising a first implanted region of n-type conductivity and a second implanted region of p-type conductivity; a buried shield area disposed above the superjunction charge balanced area at a first direction comprising a first plurality of regions of n-type conductivity and a second plurality of regions of p-type conductivity; a link area disposed above the superjunction charge balanced area and the buried shield area at the first direction comprising a third plurality of regions of n-type conductivity and a fourth plurality of regions of p-type conductivity; a JFET area disposed above the superjunction charge balanced area and the buried shield area at the first direction comprising a fifth plurality of regions of n-type conductivity and a sixth plurality of regions of p-type conductivity; a source electrode disposed above the superjunction charge balanced area, the buried shield area, and the JFET area at the first direction; and an electrical link comprising: a first region of p-type conductivity of the link area electrically connected to, and at least partially aligned with, a first region of p-type conductivity of the buried shield area at the first direction, and a second region of p-type conductivity of the JFET area electrically connected to the first region of p-type conductivity of the link area and the source electrode, wherein the second region of p-type conductivity of the JFET area is at least partially aligned with the first region of p-type conductivity of the link area at the first direction, and wherein the electrical link electrically connects the source electrode to the buried shield area holding the buried shield area at source electrode potential.