Patent ID: 7859937

Claim:
Apparatus comprising: a group of storage elements, each storage element within said group being identified by an n-bit address, and the total number of storage elements in said group being less than 2 to the power of n; write enable circuitry, responsive to an access request specifying an n-bit address, to issue a write control signal to the storage element addressed by the access request in the event that the access request is a write access request, the write control signal causing a write to that addressed storage element to occur; the write enable circuitry comprising: selective address modification circuitry for outputting as an internal address the n-bit address specified by the access request if the access request is said write access request, and for outputting as the internal address an n-bit unused address if the access request is not said write access request, the n-bit unused address not identifying any of the storage elements in said group; and comparison circuitry for comparing the internal address with the addresses of the storage elements in the group, and in the event of a match between the internal address and the address of one of said storage elements, for issuing the write control signal to said one of said storage elements.