Patent ID: 8446186

Claim:
A device comprising: a buffer circuit including first and second buffer outputs; and a latency locked loop (LLL) circuit comprising: first and second LLL inputs configured to receive first and second input signals, respectively; at least one reference delay circuit including an input configured to couple to one of the first and second LLL inputs and to generate a reference signal having a pre-determined delay in response to a corresponding one of the first and second input signals; and at least one shared component that is that is shared between the first and second buffer outputs and configured to measure edge timing errors in output signals on the first and second buffer outputs based on a difference between the reference signal and the corresponding one of the first and second inputs signals, the at least one shared component configured to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.