Patent ID: 7765449

Claim:
A test apparatus that tests a plurality of devices under test, comprising: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of devices under test; a plurality of logical comparison sections, each arranged corresponding to one of the devices under test and judging whether a comparison result of comparing a result signal outputted from the corresponding device under test in response to the test signal based on the common pattern with a reference voltage corresponds to an expected value; an additional pattern storage section that preliminarily stores a plurality of additional patterns to be added to the common pattern, the plurality of additional patterns comprising patterns to be added when the comparison result corresponds to the expected value and patterns to be added when the comparison result does not correspond to the expected value; and a plurality of pattern adding sections, each arranged corresponding to one of the plurality of devices under test and selectively reading one of the plurality of additional patterns for the corresponding device under test based on whether the comparison result corresponds to the expected value and providing the additional pattern added with the common pattern to the corresponding device under test, wherein each of the devices under test has a plurality of memory cells connected in series on a data signal line and writes data to one of the plurality of memory cells by applying one of a plurality of writing voltages to the one of the plurality of memory cells and applying one of a plurality of passing voltages that passes a data signal indicative of the data to the other memory cells, and at least one of the plurality of additional patterns stored in the additional pattern storage section is for setting one of the plurality of writing voltages and one of the plurality of passing voltages.