Patent ID: 8362546

Claim:
A memory device comprising: a plurality of pillars arranged in an array of rows and columns, wherein individual pillars have a semiconductor post with a proximal region, a distal region, and an intermediate section between the proximal and distal regions; source regions between the pillars proximate the proximal regions of the semiconductor posts; a plurality of gate lines, wherein individual gate lines surround the intermediate sections of semiconductor posts along a corresponding column of pillars, wherein the rows of pillars are spaced apart by a row spacing and the columns of pillars are spaced apart by a column spacing greater than the row spacing such that the gate lines span across the row spacing but do not span across the column spacing; self-aligned openings over the distal regions of corresponding semiconductor posts; drains implanted in the distal regions of the semiconductor posts; and drain contacts in the self-aligned openings that are electrically connected to corresponding drains at the distal regions of the semiconductor posts.