Patent ID: 7971117

Claim:
A test circuit for performing a test on a plurality of semiconductor memory chips in cooperation with a tester having a plurality of input/output pins connected to a plurality of input/output lines of the test circuit, the test circuit comprising: a plurality of first comparing units adapted to compare, on a bit-by-bit basis, read data that is read from memory cells corresponding to an address in each of the plurality of semiconductor memory chips with expected data applied via each of the plurality of input/output lines of the test circuit, and to output the comparison results as first comparison signals; a plurality of second comparing units, each second comparing unit of the plurality of second comparing units being connected to a corresponding first comparing unit of the plurality of first comparing units, being adapted to receive corresponding first comparison signals from the corresponding first comparing unit of the plurality of first comparing units and to perform a logic operation on the corresponding first comparison signals, and being adapted to generate a flag signal when determining a memory cell failure based on the logic operation result; and a plurality of storage units, each storage unit of the plurality of storage units being connected to a corresponding second comparing unit of the plurality of second comparing units, being adapted to store the corresponding first comparison signals in response to the flag signal and to serially output the stored corresponding first comparison signals via one of plurality of input/output lines of the test circuit in response to at least one control signal applied via another one of the plurality of input/output lines.