Patent ID: 8880860

Claim:
A method for saving pre-reset information in a processor, the method comprising: updating pre-reset information in a first storage element on the processor during processor operations and prior to the occurrence of a processor reset, wherein the pre-reset information changes in response to the processor operations; generating a processor reset by a reset control circuit after a history of the pre-reset information has been saved from the first storage element on the processor to a second storage element on the processor in response to detection of a reset condition, wherein the second storage element is separate from processor operating registers, wherein the history of the pre-reset information is saved from the first storage element to the second storage element over a period of processor operations in response to capture signals operating at a clock rate of the processor according to the reset control circuit prior to the processor reset, wherein the second storage element holds the history of pre-reset information after the processor has been reset and the first storage element has been overwritten during processor operations occurring after the processor reset, wherein the history of pre-reset information is accessible from the second storage element for evaluation by the processor after the processor reset has occurred; saving the pre-reset information in the second storage element in response to the capture signals according to an adjustable counter configured to sample state values every clock cycle of the processor to create a running list of N previous state values; and resetting the first storage element after saving the processor pre-reset information to the second storage element upon detection of the reset condition.