Patent ID: 8023611

Claim:
A shift register, comprising a first shift register circuit and second shift register circuit that in use, are formed on the left and right sides, respectively, of a display panel such that a pixel matrix of the display panel is located between the first and second shift register circuits, each of the first and second shift register circuits comprising: (a) a first control line for providing a first control signal, Bi 1 _L/Bi 1 _R, and a second control line for providing a second control signal, Bi 2 _L/Bi 2 _R, wherein each of the first control signal Bi 1 _L/Bi 1 _R and the second control signal Bi 2 _L/Bi 2 _R is characterized with a period and a phase, the periods of the first and second control signals Bi 1 _L/Bi 1 _R and Bi 2 _L/Bi 2 _R being identical and the phases of the first and second control signals Bi 1 _L/Bi 1 _R and Bi 2 _L/Bi 2 _R being opposite to each other; and (b) a plurality of stages, {S j }, j=1, 2, . . . , N, N being a positive integer, electrically coupled to each other in series, wherein each stage S j comprises: (i) a first transistor M 1 having a gate electrically coupled to the immediately prior stage S j−1 , a drain electrically coupled to a node BP, and a source electrically coupled to the first control signal line or the second control signal line for receiving a corresponding control signal therefrom, respectively; and (ii) a second transistor M 2 having a gate electrically coupled to the immediately next stage S j+1 , a drain electrically coupled to the drain of the first transistor M 1 , and a source electrically coupled to the source of the first transistor M 1 , respectively.