Patent ID: 7895556

Claim:
A method of determining in an unrouted integrated circuit (IC) design, timing effects and coupling effects, said unrouted IC design being described as a netlist including at least one net having a source and at least one sink, the method comprising: a. by using a computer, determining a delay change (TotalDeltaDelay) for at least one sink of said at least one net, said delay change comprising propagated effects of slew degradation; b. determining whether a difference between said TotalDeltaDelay and a slack of said at least one sink is smaller than a threshold; and c. if said slack is smaller than said threshold, then modifying said unrouted IC design by at least of one of: i) decreasing the TotalDeltaDelay of said at least one sink, and ii) increasing said slack of said at least one sink, wherein said propagation effects of slew degradation comprises estimating delay changes in downstream gates, wherein said estimation of downstream gate delay increases when excluding propagating timing values from said at least one sink.