Patent ID: 7400540

Claim:
A programmable memory, comprising: N number of one-time programmable (OTP) memory rows, each OTP memory row having multiple OTP memory cells, wherein N is a positive integer; an output module for receiving all data of the N number of OTP memory rows to generate N-bit output data, wherein each bit datum of the output data is generated by means of a calculation performed on all data of each OTP memory row corresponding to the bit datum; a judge module for receiving the output data and N-bit input data and generating N-bit write-in control data according to the output data and the input data, wherein, when the M th bit datum of the output data is different to the M th bit datum of the input data, the M th bit datum of the write-in control data is enabled, and otherwise the M th bit datum of the write-in control data is disabled, where M is a positive integer from 1 to N; and a write-in module for receiving the write-in control data and recording a preset bit datum in an unprogrammed OTP memory cell of the corresponding M th OTP memory row when the M th bit datum of the write-in control data is enabled.