Patent ID: 8043918

Claim:
A method of manufacturing a semiconductor device that includes an element isolation trench, the method comprising: forming a first layer on a substrate; etching the first layer and the substrate to form a trench in the substrate; thermally oxidizing an inner wall of the trench; depositing a first conductive film having a thickness equal to or larger than one half of width of the trench on the substrate including inside the trench; removing the first conductive film on the first layer by chemical mechanical polishing such that the first conductive film remains in only the trench; adjusting height of the first conductive film in the trench to be lower than a surface of the substrate by anisotropically etching the first conductive film; depositing an insulating film on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench; flattening the insulating film by chemical mechanical polishing; and removing the first layer; oxidizing the substrate to form an oxide-semiconductor insulating film; forming a second conductive film on the oxide-semiconductor insulating film; patterning the second conductive film and the oxide-semiconductor insulating film; forming a first impurity diffusion layer with a first concentration that is self-aligned with the second conductive film in a region from the surface of the substrate to a first depth; forming sidewalls on sides of the second conductive film; and forming a second impurity diffusion layer with a second concentration higher than the first concentration that is self-aligned with the second conductive film and the sidewalls in a region to a second depth deeper than the first depth from the surface of the substrate, a lower edge of the second impurity diffusion layer being lower than an upper edge of the first conductive film at a side of the trench.