Patent ID: 7847330

Claim:
A multi-layer non-volatile re-writeable memory, comprising: a substrate including front end of line (FEOL) active circuitry fabricated on the substrate; and four layers of non-volatile re-writeable memory in contact with the substrate and integrally fabricated on top of the substrate such that the four layers of non-volatile re-writeable memory are vertically stacked upon one another and over the substrate, each layer of non-volatile re-writeable memory including a plurality of memory cells arranged in a cross point array, each memory cell is electrically in series with and is positioned at an intersection of only one of a plurality of first conductive array lines and only one of a plurality of second conductive array lines, each memory cell is configured to store data as a plurality of conductivity profiles that are retained in the absence of power and can be non-destructively determined by applying a read voltage across its respective first and second conductive array lines, and the data can be reversibly switched between the plurality of conductivity profiles by applying a write voltage having a predetermined magnitude and polarity across its respective first and second conductive array lines, and wherein the active circuitry is electrically coupled with the plurality of first and second conductive array lines in each layer and is configured to apply to at least one memory cell in at feast one of the four layers in response to at least one signal, the read voltage during a read operation and the write voltage during a write operation.