Patent ID: 8164164

Claim:
A semiconductor device comprising: a substrate having an integrated circuit therein; an electrode disposed on the substrate and electrically connected to the integrated circuit; a blocking member disposed on a periphery of the substrate; a first wiring layer disposed on the substrate and between the electrode and the blocking member, the first wiring layer being adapted to receive a power supply voltage; a passivation layer on the substrate that covers the integrated circuit, the blocking member and the first wiring layer, the passivation layer having a groove between the blocking member and the first wiring layer and also having a first via hole therein, wherein a surface of the electrode is exposed in the first via hole, and the blocking member prevents cracking generated in an end of the passivation layer from progressing toward the integrated circuit; a protective layer on the passivation layer to fill the groove of the passivation layer and on a side of the passivation layer in the first via hole, the protective layer having a second via hole therein, wherein a portion of the surface of the electrode is exposed in the second via hole; and a second wiring layer disposed on the protective layer and electrically connected to the integrated circuit through the first and second via holes.