Patent ID: 8093127

Claim:
A method for forming a vertical transistor, comprising the steps of: forming a first junction region within a surface of a semiconductor substrate; forming a first tensile layer comprising a Si 1-x C x layer over the first junction region; forming a conductive layer over the first tensile layer; etching the conductive layer and the first tensile layer to form a hole exposing the first junction region; forming a pillar-shaped active pattern in the hole such that the pillar-shaped active pattern protrudes from the conductive layer; forming a second tensile layer comprising a Si 1-x C x layer over the protruding upper portion of the pillar-shaped active pattern; etching the conductive layer to form a gate surrounding at least a portion of the pillar-shaped active pattern; and forming a second junction region in the second tensile layer and the protruded upper portion of the pillar-shaped active pattern, wherein the first tensile layer is formed only over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern and the second tensile layer is formed only at an upper end portion of the pillar-shaped active pattern, the first and second tensile layers applying a tensile stress to a channel region of the pillar-shaped active pattern in a vertical direction.