Patent ID: 8107304

Claim:
A method of storing data in a system, comprising: requesting the system to enter read mode; providing a first column address from a microprocessor to a burst access memory; providing a first plurality of data bits to the memory; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first plurality of data bits in a portion of the memory dependent on the first column address; automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address; providing a second plurality of data bits to the memory; generating an equilibration signal synchronously with an access cycle strobe signal; asserting the equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.