Patent ID: 7084499

Claim:
A semiconductor package comprising: a semiconductor die having a pad-mounting surface, and a plurality of spaced apart bonding pads formed on said pad-mounting surface; a plurality of conductive bodies, each of which has a trace part that is formed on said pad-mounting surface and that is offset from a respective one of said bonding pads in a lateral direction relative to said pad-mounting surface, and a pad-connecting part that extends from said trace part to connect electrically with the respective one of said bonding pads; a dielectric protective layer formed on said pad-mounting surface and said conductive bodies and formed with a plurality of bump-through-holes, each of which exposes a portion of said trace part of a respective one of said conductive bodies; a plurality of solder bumps, each of which fills a respective one of said bump-through-holes to connect electrically with said portion of said trace part of a respective one of said conductive bodies and each of which protrudes outwardly from said protective layer; and a pair of opposite dielectric partition walls that are formed on said pad-mounting surface at two opposite sides of each of said bonding pads, said trace part of each of said conductive bodies extending through a respective one of said partition walls in a transverse direction relative to said partition walls in such a manner that said pad-connecting part of each of said conductive bodies is disposed between said partition walls.