Patent ID: 8243491

Claim:
A semiconductor integrated circuit comprising: a memory cell array comprising a plurality of memory cells arranged at crossing points of a plurality of bit lines and a plurality of word lines in a form of a matrix, the bit lines including first, second, third, and fourth bit lines sequentially arranged adjacent to one another; a first sense circuit which is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines, and reads data from the memory cell; a second sense circuit which is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines, and reads data from the memory cell; a first hookup region arranged between the memory cell array and the first sense circuit, the first hookup region comprising a first transfer transistor including a first current path, one end of the first current path being connected to the first bit line, the other end of the first current path being electrically connected to the first sense circuit; and a second hookup region arranged between the first hookup region and the first sense circuit, the second hookup region comprising a second transfer transistor including a second current path, one end of the second current path being connected to the third bit line, the other end of the second current path being electrically connected to the first sense circuit, wherein the first bit line formed in the first hookup region and the second hookup region includes an electrode interconnection layer configured by the same layers as gate electrode layers of the first and second transfer transistors and made of the same material as that of the gate electrode layers.