Patent ID: 7290190

Claim:
A semiconductor integrated circuit having an operational mode for processing operation input data and a test mode for processing test input data, comprising: a plurality of scan registers that are operable in response to a clock signal and a mode signal, each scan register having an output terminal, an operation input data terminal, and a test input data terminal; a plurality of logic circuits, each having an input terminal and having an output terminal that is connected to the operation input data terminal of one of the scan registers, the logic circuits and the scan registers being connected alternately in series to form m scan chains (wherein m is an integer greater than 1), the scan chains being connected to one another in a sequence, each of the scan chains including a first logic circuit, a first scan register connected to the first logic circuit, and a last scan register; a serial/parallel conversion circuit connected to the test input terminals of the first scan registers of the scan chains, the serial/parallel conversion circuit converting serial test input data supplied during the test mode into parallel test input data in response to a multiplied clock signal having a frequency that is m times that of the clock signal, the parallel test input data being fed in parallel to the scan chains; and a parallel/serial conversion circuit connected to the output terminals of the last scan registers of the scan chains, the parallel/serial conversion circuit converting parallel data received from the scan chains into serial data in response to the multiplied clock signal, wherein the parallel/serial conversion circuit comprises a selector that receives the clock signal and selectively outputs processed test input data from the last scan registers of the scan chains in response to the clock signal during the test mode, and a flip-flop that receives the multiplied clock signal and latches output data from the selector in response to the multiplied clock signal, wherein operation input data is supplied to the sequence of scan chains via the input terminal of the first logic circuit in a first one of the scan chains in the operational mode, and wherein the flip-flop outputs processed operation input data from the sequence of scan chains during the operational mode.