Patent ID: 7786760

Claim:
An output buffer circuit ( 101 ) receives a control signal (OE) and a data signal (Dout) from a first core circuit ( 10 ), operates in a transmitting mode according to the control signal and converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO), wherein the supply voltage is adjusted to pull up or pull down the first voltage level of the output signal, and the output buffer circuit comprises: a pre-driver circuit ( 103 ) receiving the control signal and the data signal and generating an up signal (UP) and a down signal (DN) according to the control signal and the data signal; a dynamic gate bias generator circuit ( 107 ) receiving the up signal and the down signal and generating first, second and third gate bias signals (Vg 1 , Vg 2 and Vg 5 ) according to the up signal and the down signal; an output stage circuit ( 104 ) comprising a first transistor (PM 201 ), a second transistor (PM 202 ) and a third transistor (NM 203 ), receiving the first, second and third gate bias signals from the dynamic gate bias generator circuit, respectively, for the first transistor, the second transistor and the third transistor, and converting the data signal into the output signal on a pad at the first voltage level or the ground voltage level according to the first, second and third gate bias signals and the supply voltage level; a gate-tracking circuit ( 106 ) detecting a voltage level of the pad for providing a gate bias signal at first specific voltages to at least one transistor of the output stage circuit for avoiding leakage currents of the transistor of the output stage circuit; and a floating N-well circuit ( 105 ) providing second specific voltages to N-wells of transistors of the output stage circuit and the gate-tracking circuit for avoiding leakage currents.