Patent ID: 7539810

Claim:
A buffer device for providing multiple operating modes, the buffer device comprising: a first memory interface adapted to connect the buffer device to a cascaded interconnect system through an upstream memory bus and a downstream memory bus, wherein the buffer device receives one or more clock inputs; and a second memory interface which includes one or more second clock lines for driving one or more second clocks derived from the one or more clock inputs, the second memory interface having two or more selectable modes of operation including: a first mode of operation for connecting the buffer device to one or more synchronous memory devices located on a first memory assembly which includes the buffer device; and a second mode of operation for connecting the buffer device to one or more second memory assemblies, the second memory assemblies including one or more of unbuffered and registered memory assemblies, wherein at least one of the second memory assemblies requires that the buffer device communicate with the second memory assembly using drive strength and timing characteristics that differ from those used to communicate with the synchronous memory devices connected to the first memory assembly in the first mode of operation, the timing characteristics including one or more of read data, write data, address and command timing relationships relative to the one or more second clocks.