Patent ID: 8710898

Claim:
Apparatus comprising a reference voltage generator (e.g., 100 , for generating a reference voltage signal (e.g., V BG ), the reference voltage generator comprising: an operational amplifier (op amp) (e.g., 110 ) having first and second input nodes (e.g., 112 , 114 ) and an output node (e.g., 116 ), wherein the reference voltage signal appears at the output node of the op amp; a first resistance (e.g., R 1 +ΔR 1 ) connected between the output node and one of first and second input nodes (e.g., 112 ); a second resistance (e.g., R 2 +ΔR 2 ) connected to the first input node; a first transistor device (e.g., Q 1 ) having an emitter connected to the second resistance and a collector connected to a voltage reference node (e.g., ground); a third resistance (e.g., R 3 ) connected between the output node and the other of the first and second input nodes (e.g., 114 ) of the op amp; a second transistor device (e.g., Q 2 ) having an emitter connected to the second input node of the op amp and a collector connected to the voltage reference node: a curvature compensation adjustment circuitry selectively connected to control nodes of the first and second transistor devices, wherein the first and second resistances and curvature compensation adjustment circuitry are trimmable; logic circuits and programmable switches (e.g., 120 ) configured to enable an external programmable tester (e.g., 150 ) to set: (a) a first resistance level (e.g., AR 1 ) for the first resistance; (b) a second resistance level (e.g., ΔR 2 ) for the second resistance; and (c) a transistor control voltage (e.g., VCU) applied by the curvature compensation adjustment circuitry to the control nodes of the first and second transistor devices; wherein the programmable tester and the logic circuits and programmable switches support a characterization phase and a production phase, such that: during the characterization phase, a design-specific trim value is determined for the second resistance level (e.g., ΔR 2 ) and a design-specific trim value is determined for the transistor control voltage (e.g., VCU); and during the production phase, with the second resistance level (e.g., ΔR 2 ) and the transistor control voltage (e.g., VCU) fixed to their design-specific trim values, an instance-specific trim value is determined for the first resistance level (e.g., ΔR 1 ).