Patent ID: 7067869

Claim:
An adjustable capacitor, comprising: a silicon wafer having a topmost layer on which are contact pads connected to a circuit contained in said wafer; a base dielectric layer on said topmost layer and said contact pads; an etch stop layer on said base dielectric layer; a support dielectric layer on said etch stop layer; a tungsten via, extending through said support dielectric layer, said etch stop layer, and said base dielectric layer, and contacting said contact pad; three trenches that extend through said support dielectric layer as far as said etch stop layer; a common capacitor electrode on said support dielectric layer, including inside said trenches, that contacts said tungsten via; on said common capacitor electrode, a layer of high dielectric constant material that fully overlaps said common capacitor electrode; on said high dielectric constant layer, four unconnected top electrodes, all of whom are overlapped by said common electrode, said top electrodes having, relative to one another, areas in the ratio 5:2:1:1; a top dielectric layer on said top electrodes and said high dielectric constant layer; four tungsten vias, extending through said top dielectric layer, that contact each top electrode, one such via per electrode; and on said top dielectric layer, permanent electrical connections between said top electrodes, whereby said adjustable capacitor has a specific capacitance value.