Patent ID: 7687407

Claim:
A method for forming an interconnect structure having reduced line edge roughness, comprising: providing a substrate having a major surface; patterning a photoresist layer over the substrate to form a first opening that exposes an area of the major surface, the first opening having a first width dimension parallel to the major surface; subjecting a first portion of the substrate adjacent to the first opening to a first etch process having a first angle, wherein the first angle is constant and greater than about 10 degrees, relative to a line perpendicular to the major surface, throughout the entire first etch process, the angle of the first etch process forming a hole with tapered sidewalls in the substrate, the hole having a second width dimension that is both parallel to, and smaller than, the first width dimension; and after the first etch process, subjecting a second portion of the substrate to a second different etch process to extend the depth of the hole to a conductive feature in the substrate, the second different etch process designed to etch at a second angle from the line perpendicular to the major surface, forming a second opening, the second angle being less than the first angle and constant throughout the entire second different etch process, the second portion being adjacent to the first portion, wherein a second degree of line edge roughness of the opening of the hole in the second portion of the substrate is reduced as compared to a first degree of line edge roughness of the opening of the hole in the first portion.