Patent ID: 8631365

Claim:
A method comprising: converting, by using a computer, a first memory element to a second memory element, the first memory element having an analog output interface, and the second memory element having a digital interface, and functionality of the first memory element and the second memory element are compatible, wherein the analog output interface of the first memory element comprises analog devices and is configured to set an output port of the first memory element at either a first logic state or a high-impedance state; and the digital interface of the second memory element comprises digital devices and is configured to set an output port of the second memory element at either the first logic state or a second logic state; generating a layout cell for the second memory element, the layout cell having a layout pitch recognizable by a synthesis tool and a place and route tool; generating timing arcs for the second memory element, the timing arcs being recognizable by the place and route tool and a timing analysis tool; and using the second memory element in conjunction with a register level transfer tool, the synthesis tool, the place and route tool, and the timing analysis tool to automatically generate a memory, by using a computer.