Patent ID: 7120617

Claim:
A product-sum operation circuit comprising: a pulse with/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal; a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit; a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value; and an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit, wherein said pulse width/digital conversion circuit comprises a counter which counts a clock and outputs a count value as a digital signal, and a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal, and wherein said pulse with/digital conversion circuit further comprises, in correspondence with each of said plurality of trailing edge latch circuits, a leading edge latch circuit which latches the count value output from said counter at a leading edge of the pulse signal, and a subtraction circuit which operates and outputs a difference between a digital output value from said trailing edge latch circuit and a digital output value from said leading edge latch circuit.