Patent ID: 7960223

Claim:
A method of forming a semiconductor device comprising: providing a substrate including a semiconducting surface; forming first conductivity type devices including first gate structures in a first device region of the substrate and second conductivity type devices including second gate structures in a second device region of the substrate, wherein the first conductivity type device is an n-type device, and the second conductivity type device is a p-type device; forming a protective dielectric mask overlying the second device region; forming a first work function metal semiconductor alloy adjacent the first gate structures in the first device region, wherein the first work function metal semiconductor alloy is composed of material that provides a work function substantially aligned with the conduction band of the n-type conductivity device, wherein the protective dielectric mask is overlying the second device region; forming a first strain inducing layer overlying the first device region of the substrate including the first work function metal semiconductor alloy, and atop the protective dielectric mask that is present in the second device region of the substrate; removing the first strain inducing layer that is overlying the protective dielectric mask and the protective dielectric mask to expose the second conductivity type devices; forming a second work function metal semiconductor alloy after removing the first strain inducing layer that is overlying the protective dielectric mask and the dielectric mask to expose the second conductivity type devices, in which the second work function metal semiconductor alloy is adjacent the second gate structures in the second device region, wherein the first work function metal semiconductor alloy is composed of a different material than the second work function metal semiconductor alloy, and the second work function metal semiconductor alloy is substantially aligned with the valence band of the p-type conductivity device; and forming a second strain inducing layer overlying the second device region of the substrate including the second work function metal semiconductor alloy.