Patent ID: 8766701

Claim:
An apparatus, comprising: an analog multiplexer having first select circuits and at least one second select circuit; wherein the first select circuits have respective input nodes and output nodes; wherein the output nodes are all coupled to one another to provide an output node of the analog multiplexer; wherein the first select circuits are coupled to a first supply voltage of a first supply domain; wherein the at least one second select circuit is coupled to a second supply voltage of a second supply domain different from the first supply domain; wherein the at least one second select circuit has an input port and an output port; wherein the output port is coupled to an input node of the input nodes; and a voltage monitoring circuit coupled to receive the first supply voltage and the second supply voltage and configured to generate a power-on-reset signal and a complement of the power-on-reset signal for pass gate operation of the at least one second select circuit; wherein the voltage monitoring circuit comprises: a power-on-reset circuit coupled to receive the first supply voltage and configured to provide a first ramp-up signal of the first supply domain for the first supply voltage; and a level shifter coupled to receive the first ramp-up signal, the first supply voltage and the second supply voltage to provide the power-on-reset signal of the second supply domain.