Patent ID: 8080471

Claim:
A method of manufacturing a memory cell structure, the method comprising: forming an under-metal layer electrically coupled to a switching device for reading a memory state of a memory stack; forming a via structure on and electrically connected to the under-metal layer; forming a data control line for controlling the memory state of the memory stack directly and laterally adjacent to the via structure, and at least partially directly vertically over the under-metal layer; forming a conductive extender having a main portion located directly vertically over, but not in electrical contract with, the data control line, and having an extending portion at least partially laterally extending directly vertically over the under-metal layer; forming a memory stack having a bottom electrode and a top electrode on the main portion of the extender and directly vertically over, but not in electrical contract with, the data control line; wherein the via structure directly connects the extending portion to the under-metal layer.