Patent ID: 8143929

Claim:
A method of operating a circuit during a normal mode of operation using a clock signal, comprising: receiving a first data signal at a first node; coupling the first node to a second node in response to assertion of a first pair of complementary clocks to couple the first data signal to the second node; after coupling the first node to the second node, coupling the second node to a third node in response to assertion of a second pair of complementary clocks to couple the first data signal to the third node, wherein both the first pair of complementary clocks and the second pair of complementary clocks are generated from the clock signal and the second pair of complementary clocks is delayed with respect to the first pair of complementary clocks; decoupling the first node from the second node in response to deassertion of the first pair of complementary clocks and performing a first step of latching the first data signal at the third node, wherein the first step of latching is through the second node while the second node is coupled to the third node; and decoupling the second node from the third node in response to deassertion of the second pair of complementary clocks and performing a second step of latching the first data signal to the third node, wherein the second step of latching is while the second node is decoupled from the third node.