Patent ID: 7084666

Claim:
A programmable interconnect structure in an integrated circuit comprising: a first wire and a second wire; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a user configurable configuration circuit comprising one or more memory elements; and a first programmable multiplexer comprising: two inputs and an output wherein the inputs are coupled to said first and second wires, and the output is coupled to said input of the buffer; and wherein, the data stored in the memory elements select one of said two wires to couple to said buffer input; and a second programmable multiplexer comprising: an input and two outputs, wherein the input is coupled to said output of the buffer and the outputs are coupled to said first and second wires; and wherein, the data stored in the memory elements select said buffer output to couple to one of said two wires; wherein, a signal received by the buffer on any one of the two wires is buffered and transmitted on the other wire; and wherein, said one or more memory elements in the configuration circuit are located substantially above the programmable multiplexers and the buffer.