Patent ID: 8365121

Claim:
A design supporting method of designing a semiconductor integrated circuit that includes a plurality of data holding elements and a clock path that propagates a clock signal from a clock source to the data holding elements, wherein a computer executes: detecting, from layout data of the semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers; selecting sequentially the data holding elements connected to the clock path detected at the detecting; identifying an input clock buffer of the data holding element, each time a data holding element is selected at the selecting; determining whether the clock buffer identified at the identifying outputs the clock signal from the clock source according to non-inverting logic or inverting logic, based on a number of gates from the clock source to the clock buffer; replacing, based on a result obtained at the determining, the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal; and outputting a result obtained at the replacing.