Patent ID: 8581316

Claim:
A method of manufacturing a semiconductor device, comprising: (a) forming an active region and an element isolation region on a semiconductor substrate, the element isolation region having a surface higher in height than a surface of the active region; (b) forming a gate oxide film of a transistor element on a well region of a first conductivity type formed along a main surface of the semiconductor substrate on the active region; (c) forming a first polysilicon film on the semiconductor substrate; (d) patterning the first polysilicon film, to thereby form, in the active region, a gate electrode of the transistor element and a lower electrode of a capacitor; (e) implanting impurities of a second conductivity type into the gate electrode and the lower electrode; (f) implanting impurities of the second conductivity type into a surface of the well region of the first conductivity type with use of the gate electrode as a mask, to thereby form a source region and a drain region of the transistor element; (g) forming a capacitor insulator on the lower electrode of the capacitor; (h) forming a second polysilicon film on the semiconductor substrate; (i) patterning the second polysilicon film, to thereby form an upper electrode of the capacitor in the active region, and a resistor in the element isolation region; (j) implanting impurities of the second conductivity type into the upper electrode; (k) implanting impurities of the first conductivity type into the resistor; (l) forming a first interlayer insulator on the semiconductor substrate; (m) grinding down at least the first interlayer insulator and the resistor until the resistor has a thickness different from the thickness of the upper electrode of the capacitor and the thickness difference therebetween is determined depending on the difference between the surface heights of the active region and the element isolation region and on a thickness of the first polysilicon film; (n) forming a second interlayer insulator on the semiconductor substrate; and (o) forming a contact hole on the second interlayer insulator.