Patent ID: 6888773

Claim:
A semiconductor memory device comprising: a single or a plurality of memory cell arrays; and erase means, wherein: the memory cell array is configured such that a plurality of nonvolatile memory cells each comprising a variable resistor element for storing information through variations in electric resistance are arranged in each of a row direction and a column direction, and a plurality of word lines and a plurality of bit lines are arranged along the row direction and the column direction, respectively, to select a predetermined memory cell or memory cells from the plurality of memory cells; the memory cells are arranged such that one end sides of the variable resistor elements are individually connected to drains of selection transistors, the other end sides of the variable resistor elements or sources of the selection transistors are commonly connected to the bit lines along the column direction, the others thereof are commonly connected to the source line, and gates of the selection transistors are commonly connected to the word lines along the row direction; and the erase means is configured to apply voltage individually to each of the word lines, the bit cells, and the source line that are connected to the memory cell array under predetermined application conditions, to set the electric resistances of the variable resistor elements in individual erase-target memory cells in the memory cell array to a predetermined erased state, and to thereby render the information in the memory cells to be erasable; and concurrently, the erase means executes the erase by switching between a batch-erase mode and an individual-erase mode depending on the voltage application conditions in at least one of the memory cell arrays, wherein in the batch-erase mode the erase means performs batch erase of all the memory cells in the memory cell array, and in the individual-erase mode the erase means performs individual erase of a part of the memory cells in the memory cell array.