Patent ID: 8397183

Claim:
A method of generating block level shapes to manufacture asymmetric field effect transistors (FETs) comprising: obtaining an integrated circuit design having a multitude of levels including an active region level and a gate region level, each of the active region and gate levels having a multitude of shapes representing semiconductor regions; defining a new source-drain level having a multitude of source-drain level shapes from the level active region shapes and the gate level shapes, and whereby two new source-drain level shapes result from each of the active region level shapes, and one of said two new source-drain level shapes is a source region and the other of said two new source-drain level shapes is a drain region; wherein in some of said two new source-drain level shapes, the source region of said two new shapes is in a defined up position relative to the drain region of said two new shapes; and in others of said two new source-drain level shapes, the source region of said two new shapes is in a defined down position relative to the drain region of said two new shapes; identifying which ones of the new shapes are source regions, and which ones of the new shapes are drain regions; determining which ones of the identified source regions are in the defined up position and which ones of the identified source regions are in the defined down position, according to given rules; defining a plurality of additional levels; and copying the shapes of the source regions that are position up and the shapes of the source regions that are in the defined down position onto said additional levels.