Patent ID: 6873650

Claim:
A circuit for providing transmission rate compensation, comprising: (a) a transmit path configured to receive downstream coefficients in a frequency domain at a first data rate and to generate a block of upstream digital samples at a second data rate; and (b) a receive path configured i) to receive a block of downstream digital samples in a time domain at the second data rate and ii) to generate downstream coefficients in the frequency domain at a third data rate, wherein: the first data rate is different from the second data rate; and the transmit path comprises: (1) a zero-padding module configured to append one or more zeros to each set of received downstream coefficients; (2) an inverse transform module configured to convert each set of zero-padded downstream coefficients into a corresponding block of downstream digital samples at the second data rate; (3) an intermediate inverse transform module applying an intermediate inverse transform to the received downstream coefficients to generate intermediate digital samples, (4) an interpolator interpolating the intermediate digital samples, and (5) an intermediate transform module applying an intermediate transform to the upstream coefficients to generate the upstream coefficients for the inverse transform module.