Patent ID: 8222677

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a cell array block formed on said semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing said plurality of first lines, and memory cells connected at intersections of said first and second lines between both lines; and a plurality of contact plugs which are substantially pillar-shaped bodies having the stack direction of said cell array layers as a height direction, and which are configured to connect between said first lines, between said second lines, between said first or second line and said semiconductor substrate, or between said first or second line and another metal line, in said cell array layers, wherein said first or second line in a certain one of said cell array layers has a contact connector making contact with said contact plug in at least two places facing each other in a direction orthogonal to said stack direction on sides of said contact plug.