Patent ID: 7585719

Claim:
A method of manufacturing a power integrated circuit (IC) comprising: fabricating a control circuit in a first area of a semiconductor die having a substantially rectangular shape, the first area having first and second sides, the semiconductor die having an overall length and an overall width; fabricating first and second output field-effect transistors (FETs) transistors, each having interdigitated segments, in an L-shaped second area of the semiconductor die, the L-shaped area having first and second inner sides that are respectively disposed adjacent the first and second sides of the first area, the first inner side having a length substantially equal to a length of the first side of the first area, the second inner side having a length substantially equal to a length of the second side of the first area, the L-shaped second area including first and second outer sides, the first outer side having a length substantially equal to the overall length of the semiconductor die, the second outer side having a length substantially equal to the overall width of the semiconductor die; and coupling the control circuit to at least one of the first or second output FETs.