Patent ID: 8799587

Claim:
A method of controlling region coherence in a shared-memory multiprocessor system, the method comprising: a processor in the shared-memory multiprocessor system generating a request for a line of data storable in a first subregion of a region of system memory, wherein a subregion is a smaller division of the region of system memory that is at least as large as the line of data; determining, from a first entry in a region coherence array (RCA), a current region coherence state of the first subregion which indicates whether at least one other processor in the shared-memory multiprocessor system has cached at least one line of data of the first subregion, wherein the RCA is a meta-data array located in a cache hierarchy and is accessed in parallel with a lowest-level cache in the cache hierarchy; in response to determining the current region coherence state of the first subregion, updating the RCA associated with the requesting processor; and creating a combined snoop response based on a snoop response of the processor and a snoop response for each of the at least one other processor, wherein the snoop response of the processor comprises a status of the line of data and a status of the first subregion in the processor, and wherein the snoop response for each of the at least one other processor comprises a status of the line of data and a status of the first subregion in the at least one other processor.