Patent ID: 8125255

Claim:
A PLL circuit including a voltage controlled oscillator and phase comparison means that frequency-divides an output of the voltage controlled oscillator, compares phase between the output and a reference signal and outputs a signal based on a phase difference as a control voltage for the voltage controlled oscillator, comprising: a reference oscillator that makes a reference frequency variable in accordance with a reference frequency selection signal and outputs the reference frequency; a DDS circuit that outputs an output signal based on a reference frequency input and in response to an external output instruction signal, while outputting a folding signal of an output signal for the reference frequency and an integral multiple of the reference frequency; a first amplifier that amplifies an output signal from the DDS circuit with a first amplification setting value externally input; a variable filter that makes a frequency pass band thereof variable in accordance with a variable frequency setting value externally input and lets an output signal from the first amplifier pass therethrough; a second amplifier that amplifies an output signal from the variable filter with a second amplification setting value externally input and outputs the amplified signal to the phase comparison means as a reference signal; and a control circuit that, when an instruction signal is input to instruct to make the reference signal at a desired frequency, outputs a reference frequency selection signal corresponding to the instruction signal to the reference oscillator, outputs an output instruction signal corresponding to the instruction signal to the DDS circuit, outputs a first amplification setting value corresponding to the instruction signal to the first amplifier, outputs a variable frequency setting value corresponding to the instruction signal to the variable filter, outputs a second amplification setting value corresponding to the instruction signal to the second amplifier, and outputs a division ratio to the phase comparison means.