Patent ID: 8026131

Claim:
A method of forming a semiconductor structure comprising: forming at least one field effect transistor on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate including a buried insulator layer and a bottom semiconductor layer having a doping of a first conductivity type; forming a shallow trench isolation structure in said top semiconductor layer, wherein said shallow trench isolation structure laterally abuts and surrounds said at least one field effect transistor; forming a first doped semiconductor region in said bottom semiconductor layer, wherein said first doped semiconductor region abuts said buried insulator layer and has a doping of said first conductivity type; and forming a second doped semiconductor region in said bottom semiconductor layer, wherein said second doped semiconductor region abuts said buried insulator layer and has a doping of a second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type, and wherein said first and second doped semiconductor regions are electrically connected through at least one metal interconnect structure located above said SOI substrate and configured to apply a same voltage to said first and second doped semiconductor regions.