Patent ID: 7710759

Claim:
A nonvolatile ferroelectric memory device comprising: a plurality of memory cells connected serially between a bit line and a sensing line; a first switching unit configured to selectively connect the plurality of memory cells to the bit line in response to a first selecting signal; and a second switching unit configured to selectively connect the plurality of memory cells to the sensing line in response to a second selecting signal, wherein each of the plurality of memory cells, the first switching unit, and the second switching unit comprises: a bottom word line; an insulating layer formed on the bottom word line; a floating channel layer formed on the insulating layer; a ferroelectric layer formed on the floating channel layer; and a top word line formed on the ferroelectric layer in parallel with the bottom word line, wherein, when a bit of “1” is written in a selected one of the memory cells, the first switching unit and the second switching unit are turned on and a negative polarization transition threshold voltage is applied to the top word line of the selected memory cell.