Patent ID: 7075839

Claim:
A semiconductor memory device comprising: a plurality of first memory cells arranged in matrix; a control line connecting a subset of the plurality of first memory cells which are aligned in a row direction or a column direction; and a second memory cell connected to the control line, wherein the second memory cell in configured to retain information on a stress applied from the control line to each of the first memory cells, wherein the first memory cells and the second memory cells each have a floating gate electrode which in formed, as the charge storage portion, above a semiconductor substrate with a tunnel insulating film interposed therebetween, a control gate electrode formed above the floating gate electrode with a capacitor insulating film interposed therebetween, and a source electrode and a drain electrode provided to interpose a portion of the semiconductor substrate located below the floating gate electrode, and wherein the first memory cells differ from the second memory cells in the composition or the shape of at least one of the tunnel insulating film, the floating gate electrode, the capacitor insulating film, and the control gate electrode.