Patent ID: 7978554

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of pairs of bit lines and complementary bit lines; a plurality of memory cells, each memory cell being at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other; a voltage control unit that controls a power voltage to obtain a controlled voltage appliable to the memory cells in response to a control signal that controls an operation of the memory cells; and at least one dummy cell disposed between the voltage control unit and the memory cells and configured to reduce the controlled voltage to a predetermined level, wherein the at least one dummy cell and a memory cell are connected in parallel both to the voltage control unit and to a word line common to the memory cell and the at least one dummy cell, and wherein widths of channels of a first access transistor and a second access transistor in the at least one dummy cell are greater than widths of channels of the first access transistor and the second access transistor in each of the plurality of memory cells.