Patent ID: 7340643

Claim:
A processor comprising: an execution unit including a first parity-protected storage structure having a first parity bit and a second parity-protected storage structure having a second parity bit; a check unit coupled to the first parity-protected storage structure and the second parity-protected storage structure, the check unit to monitor the first parity-protected storage structure and the second parity-protected storage structure, to detect a parity error in data accessed from the first parity-protected storage structure or in data accessed from the second parity-protected storage structure, and to signal a parity error; and a replay queue coupled to the check unit and the execution unit, the at least one replay queue to issue a plurality of instructions to the protected execution unit for processing, to track the plurality of instructions issued to the protected execution unit, and to selectively reissue one or more of the plurality of instructions to the protected execution unit in response to the check unit detecting and signaling a parity error.