Patent ID: 8120108

Claim:
An integrated circuit, comprising: a semiconductor substrate, said substrate having a first conductivity type; and an SCRMOS transistor formed in and on said substrate, said SCRMOS transistor having: a deep well formed in said substrate, said deep well having an opposite conductivity type from said substrate, in which said deep well has a drift region; a RESURF region formed in said deep well so that said RESURF region laterally abuts said drift region, said RESURF region having a same conductivity type as said deep well, in which a doping density of said RESURF region is at least two times a doping density of said drift region; a body region formed in said deep well so that said body region laterally abuts said drift region opposite from said RESURF region, said body region having an opposite conductivity type from said deep well; an MOS gate formed over said substrate such that said MOS gate overlaps a portion of said body region; a drain structure formed in said drain RESURF region, said drain structure having: a drain diffused region, said drain diffused region having a same conductivity type as said RESURF region, such that a doping density of said drain diffused region is at least three times greater than said doping density of said RESURF region; and an SCR terminal, said SCR terminal having an opposite conductivity type from said RESURF region; and a source structure formed in said body region, said source structure having: a source diffused region adjacent to said MOS gate, said source diffused region having a same conductivity type as said deep well; and a body contact diffused region, said body contact diffused region having a same conductivity type as said body region.