Patent ID: 7729173

Claim:
A voltage output circuit for a nonvolatile semiconductor memory device, the circuit comprising: a high voltage generator generating an internal high voltage; a sampling signal generator generating a sampling signal in response to a selection signal generated according to a mode of the voltage output circuit; and a sample and hold circuit sampling the internal high voltage output in response to the sampling signal to produce a sample of the internal high voltage output, and holding the sample for a predetermined time interval, wherein an output of the high voltage generator is electrically connected to an input of the sample and hold circuit; and the sampling signal generator comprises: a mode selection switch outputting first through third selection mode decision signals in response to external selection input data derived from the selection signal to perform a sampling of the minimum value of the internal high voltage, the maximum value of the internal high voltage, or of overall waveforms, respectively; a first pulse generator generating a first sampling pulse as the sampling signal in response to a rising edge of a high voltage pump enable signal and an activation of the first selection mode decision signal; a second pulse generator generating a second sampling pulse as the sampling signal in response to a falling edge of the high voltage pump enable signal and an activation of the second selection mode decision signal; and a clock generator generating a periodic clock signal as the sampling signal in response to activation of the third selection mode decision signal.