Patent ID: 8753970

Claim:
A method, comprising: forming a sacrificial gate structure and a sacrificial gate cap layer above a semiconducting substrate, said sacrificial gate structure comprising at least a sacrificial gate electrode that has a plurality of sidewalls; forming at least one first sacrificial sidewall spacer adjacent said sacrificial gate electrode; performing at least one etching process to remove a portion of said first sacrificial sidewall spacer and thereby expose at least a portion of said sidewalls of said sacrificial gate electrode; after performing said etching process, forming a liner layer on said exposed sidewalls of said sacrificial gate electrode and above a residual portion of said first sacrificial sidewall spacer; forming a first layer of insulating material above said liner layer; forming at least one second sacrificial sidewall spacer above said first layer of insulating material and adjacent said liner layer; forming a second layer of insulating material adjacent said second sacrificial sidewall spacer; performing at least one etching process to remove at least said second sacrificial sidewall spacer and said sacrificial gate cap layer to thereby define an opening in said second layer of insulating material that exposes an upper surface of said sacrificial gate electrode; after exposing said upper surface of said sacrificial gate electrode, removing at least said sacrificial gate electrode to thereby define a gate cavity that is at least partially defined laterally by said liner layer; and forming a replacement gate structure in said gate cavity.