Patent ID: 8392772

Claim:
An integrated circuit, comprising: a substrate; a memory array with dedicated support hardware formed on the substrate; an access wrapper circuit coupled to address and data lines of the memory array and to control lines of the dedicated support hardware, the wrapper circuit configured to provide an access port to the memory array; and a test controller formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array; another logic module coupled to the access port; isolation logic coupled between the memory array and the access wrapper circuit, wherein the isolation logic is operable to allow the test controller to autonomously test the entire memory array using the test program while a function controller coupled to the access port simultaneously accesses the other logic module.