Patent ID: 8318549

Claim:
A method of packaging an integrated circuit on a package substrate, comprising: attaching the integrated circuit to the package substrate; forming electrical connections between the integrated circuit and the package substrate using a first plurality of bond wires connected to a first plurality of bond posts on the package substrate and a first plurality of bond pads along a first side of the integrated circuit and a second plurality of bond wires connected to a second plurality of bond posts on the package substrate and a second plurality of bond pads along a second side of the integrated circuit; and injecting mold compound through a plurality of openings in the package substrate, wherein a first opening of the plurality of openings is between the first plurality of bond posts and the first side and a second opening of the plurality of openings is between the second plurality of bond posts and the second side, wherein the injecting results in applying the mold compound over the integrated circuit and the package substrate, and wherein the plurality of wire bonds function to screen out a portion of filler from the mold compound during the injecting so that a first region of the mold compound has a first concentration of filler that is evenly distributed throughout an entirety of the first region, and a second region of the mold compound has a second concentration of filler that is evenly distributed throughout an entirety of the second region, the first concentration of filler being greater than the second concentration of filler, and wherein the first region includes all of the mold compound between the first and second plurality of wire bonds and the first and second sides to which the first and second plurality of wire bonds are adjacent, and the second region of the mold compound includes all of the mold compound between the first and second plurality of wire bonds and a mold cap boundary.