Patent ID: 7206894

Claim:
A microcomputer application system comprising: a microcomputer including an MPU, an internal RAM, and a bus for connecting the MPU and the internal RAM; an external ROM connected to the bus; first means for transferring a high-speed processing part which is part of a program stored in the external ROM and is required to be operated at high speed from the external ROM to the internal RAM; and second means for translating, when a fetch address AZ 1 which the MPU specifies to fetch program data indicates a region of the external ROM in which the high-speed processing part is stored, the fetch address AZ 1 to an address AF of a region of the internal RAM corresponding to the high-speed processing part, and for not translating the fetch address AZ 1 , when the fetch address AZ 1 does not indicate the region of the external ROM in which the high-speed processing part is stored; and a register referred to by the second means, wherein the register is operable to set a top address AO 1 of the high-speed processing part stored in the external ROM and a top address AA 1 of the high-speed processing part transferred to the internal RAM, wherein the second means translates the fetch address AZ 1 to a value obtained by subtracting the top address AO 1 from a sum of the top address AA 1 and the fetch address AZ 1 as the address AF with referring to the register, when the fetch address AZ 1 indicates the region of the external ROM in which the high-speed processing part is stored.