Patent ID: 7401333

Claim:
An apparatus comprising: an array of parallel programmable processing engines; a switching network interconnecting the array of parallel programmable processing engines, wherein at least some of the processing engines execute a thread, at least some threads communicating with each other through communication objects either internally within one processing engine or through the network, the array of parallel programmable processing engines include means for scheduling a scheduling step of the parallel programmable processing engines, the scheduling step being initiated by one or more events, an event being defined by a change of a state variable of a communication object, a scheduling step comprising a delta cycle convergence step, wherein the array of parallel programmable processing engines executes a system level model, the system level model comprising a plurality of concurrent processes at least some of which communicate with each other, at least one of the processes being a further system model and each of the other processes being a primitive process, and wherein executing a thread on one of the processing engines of the array of parallel programmable processing engines executes a primitive process.