Patent ID: 8212311

Claim:
A semiconductor device comprising a first MOS transistor and a second MOS transistor each formed on a substrate, wherein: each of the first and second MOS transistors is a vertical transistor in which a source diffusion layer, a drain diffusion layer and a pillar-shaped semiconductor layer are hierarchically arranged in a vertical direction with respect to the substrate while the pillar-shaped semiconductor layer is arranged between the source diffusion layer and the drain diffusion layer, and a gate electrode is formed along a sidewall of the pillar-shaped semiconductor layer, and wherein: the first and second MOS transistors have a common gate electrode, and a common first planar diffusion layer formed on the substrate; the first MOS transistor has a first diffusion layer formed on a top of the pillar-shaped semiconductor layer thereof to serve as the source diffusion layer; and the second MOS transistor has a second diffusion layer formed on a top of the pillar-shaped semiconductor layer thereof to serve as the drain diffusion layer, and wherein the first and second MOS transistors are connected in series to allow a total gate electrode length to become two times greater than a gate electrode length of each of the first and second MOS transistors, and wherein each of the first and second MOS transistors includes a plurality of the pillar-shaped semiconductor layers, in such a manner that the plurality of pillar-shaped semiconductor layers belonging to a respective one of the first and second MOS transistors are arranged to form a line-array, wherein the two line-arrays of the first and second MOS transistors are arranged in parallel to each other, and wherein: the first MOS transistor has a first gate electrode common to the line-array of pillar-shaped semiconductor layers thereof; and the second MOS transistor has a second gate electrode common to the line-array of pillar-shaped semiconductor layers thereof, and wherein each of the first and second gate electrodes is connected to a same interconnection layer via a contact at an end of the line-array of pillar-shaped semiconductor layers of a corresponding one of the first and second MOS transistors.