Patent ID: 8904189

Claim:
A processor comprising: an instruction processing pipeline, configured to receive a sequence of instructions for execution, said sequence comprising at least one instruction including a flow control instruction which terminates the sequence; a hash generator, configured to generate a hash associated with execution of the sequence of instructions; a memory configured to securely receive a reference signature corresponding to a hash of a verified corresponding sequence of instructions; verification logic configured to determine a correspondence between the hash and the reference signature, to validate at run-time instructions within the sequence of instructions; and authorization logic configured to: selectively produce a signal, after at least partial execution of the sequence of instructions within the instruction processing pipeline, in dependence on a correspondence of the hash with the reference signature, to authorize commitment of the control flow instruction that terminates the sequence of instructions, and generate an interrupt, if the correspondence of the hash with the reference signature is insufficient, the generated interrupt being adapted to invoke an appropriate handler that suspends further execution of the sequence of instructions and restore the processor to a known stable state or a previous checkpoint.