Patent ID: 7079172

Claim:
A circuit for generating dot clock pulses utilized for an imageforming apparatus having an image-writing section, comprising: a digital-delay dot clock adjusting section to generate first dot clock pulses having a predetermined number of pulses within a predetermined time interval at a constant exposing range of said image-writing section for making a correction against a deviation expanded or contracted, wherein each period of said first dot clock pulses is slightly increased or reduced by changing a successive selection for a plurality of delayed clock pulses, which are generated successively in slightly different delay times by delaying clock-pulses, outputted from a reference oscillator, in slightly different delay times; and a jitter suppressing section to suppress a jitter component included in said first dot clock pulses, wherein said jitter suppressing section divides said first dot clock pulses to generate second dot clock pulses, and then, multiplies said second dot clock pulses to generate said dot clock pulses.