Patent ID: 7479423

Claim:
A manufacturing method of a semiconductor device, comprising: forming a first and a second dummy gate pattern on a silicon layer formed over a semiconductor substrate via an insulation film; forming impurity diffusion layers at positions of source regions and drain regions by introducing impurities into said silicon layer, using said first and said second dummy gate pattern as masks; forming an insulation film over said silicon layer so as to bury said first and said second dummy gate pattern; removing said first dummy gate pattern to form a first groove in said insulation film; forming a silicon oxide film at a position of a channel region of said silicon layer in said first groove; removing said silicon oxide film to reduce a thickness of a portion corresponding to the channel region of said silicon layer; removing said second dummy gate pattern to form a second groove in said insulation film; forming gate insulation films over the channel regions of said silicon layer; and forming gate electrodes over said gate insulation films.