Patent ID: 8687736

Claim:
A demodulating and digitizing circuit, comprising: a wideband low-noise amplifier configured to generate N low-noise radio frequency (RF) signals based on N received RF signals, the N received RF signals having N different RF signal frequencies, respectively; N filters configured to filter the N low-noise RF signals, respectively, to generate N filtered RF signals; a clock generator configured to generate N first mixing clock signals having N different first mixing frequencies, respectively; N mixers configured to mix the N filtered RF signals with the N mixing clock signals, respectfully, to generate N first frequency-shifted RF signals; a summer circuit configured to combine the N first frequency-shifted RF signals to generate an aggregate first-intermediate-frequency (first-IF) signal having a first-IF bandwidth; a sampling clock generator configured to generate a first sampling clock having a first sampling clock frequency, an in-phase sampling clock having an in-phase sampling clock frequency, and a quadrature sampling clock having a quadrature sampling clock frequency, the quadrature sampling clock frequency being ninety degree out of phase with the in-phase sampling clock frequency; a quadrature bandpass-sampling analog-to-digital demodulator configured to digitize and frequency-shift the aggregate first-IF signal to generate an in-phase aggregate second-IF signal based on the in-phase sampling clock, and generate a quadrature aggregate second-IF signal based on the quadrature sampling clock; a decimation low-pass filter configured to filter the in-phase second-IF signal based on the first sampling clock to generate an in-phase K-bit second-IF signal, and filter the quadrature second-IF signal based on the first sampling clock to generate a quadrature K-bit second-IF signal; and N digital down converters configured to generate N second mixing clock signals responsive to the first sampling clock, the N second mixing clock signals having N different second mixing frequencies, respectively, and generate N demodulated RF signals based on the N second frequency-shifted RF signals embedded in both the in-phase K-bit second-IF signal and the quadrature K-bit second IF signal, responsive to the N second mixing clock signals, respectively, wherein the in-phase second-IF signal and the quadrature second-IF signal are both digital bi-level signals, and the in-phase K-bit second-IF signal and the quadrature K-bit second-IF signal each have K bits of resolution, N is an integer greater than 1, and K is an integer greater than 0.