Patent ID: 8053317

Claim:
A method of forming a semiconductor device comprising the steps of: obtaining a semiconductor substrate having a logic region and a shallow trench isolation (STI) region; sequentially depositing layers of a high dielectric constant (high K) material, a metal gate, a first silicon and a hardmask on the semiconductor substrate to form a semiconductor substrate having layers of high dielectric constant (high K) material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region of the semiconductor substrate to result in a semiconductor substrate having a logic region having layers of high K material and metal gate and an STI region having layers of high K material, metal gate, first silicon and a hardmask; and applying a second layer of silicon on the semiconductor substrate such that the logic region comprises layers of high K material, metal gate and second silicon and the STI region comprises layers of high K material, metal gate, first silicon, hardmask and second silicon.