Patent ID: 7590007

Claim:
A nonvolatile semiconductor memory device comprising; a memory cell array including a plurality of electrically reprogrammable nonvolatile memory cells each having a plurality of threshold levels corresponding to a plurality of programming data respectively; a voltage generator circuit which generates a plurality of programming voltage pulses and a plurality of verify voltage pulses which are applied to said nonvolatile memory cells; a counter circuit which counts the number of times said programming voltage pulse is applied to corresponding said nonvolatile memory cell; a storage circuit which stores data corresponding to said plurality of verify voltage pulses which are set for each of corresponding said threshold levels and the number of times said programming voltage pulse is applied, the number of times said programming voltage pulse is applied being standards for switching a plurality of said verify voltage pulses; a comparison circuit which compares the number of times said programming voltage pulse is applied with said standards and generates a comparison result; a control circuit which controls said plurality of verify voltage pulses step by step based on said comparison result.