Patent ID: 6903367

Claim:
A decoder for a memory device, comprising: a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer; a number of vertical floating gate transistors, each floating gate transistor being formed in a single crystalline layer that is selectively disposed on a side of one of the vertical pillars, the single crystalline layer having a thickness of less than 10 nanometers from the side of the vertical pillar and extending in a direction normal to the side of the vertical pillar, wherein each transistor includes: a first source/drain region in contact with the first contact layer; a second source/drain region in contact with the second contact layer; a body region which opposes the oxide layer and contacts the first and the second source/drain regions; and a floating gate opposing the body region; a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array; and wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the vertical floating gate transistors and serves as a control gate.