Patent ID: 7787317

Claim:
A memory circuit, comprising: a control circuit, enabling a word-line pulse signal to initiate reading of a memory cell array; a word-line driver, enabling a word line according to the word-line pulse signal to trigger the memory cell array; the memory cell array, reading a data bit from a memory cell directed by the enabled word line and outputting the data bit onto a bit line; a tracking circuit, delaying the word-line pulse signal by a delay period to generate a sense amplifier enable signal; and a sense amplifier, detecting the data bit on the bit line to generate an output signal when the sense amplifier enable signal is enabled, wherein the tracking circuit comprises a plurality of dummy cells, a dummy bit line, and an inverter, at least one of the dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for pulling down the voltage of the dummy bit line when the word-line pulse signal is enabled, and the inverter inverts the voltage of the dummy bit line to generate the sense amplifier enable signal.