Patent ID: 8131981

Claim:
A method comprising: decoding a fractional multiply operation that specifies a first operand and a second operand both stored in a first source register, and a third operand and a fourth operand both stored in a second source register; executing a first multiply operation on the first and third operands pursuant to the fractional multiply operation to generate a first intermediate product; executing a second multiply operation on the second and fourth operands pursuant to the fractional multiply operation to generate a second intermediate product; shifting the first intermediate product and the second intermediate by a predetermined number of bit positions; saturating the shifted first and second intermediate products to n-bit width specified by the fractional multiply operation; storing the saturated first and second intermediate products in a destination register and a saturation history according to whether saturation has occurred at a particular byte, half-word, or word position in a saturation history field of a saturation flag register; processing the saturation history and storing a result of the processing in a condition code flags set indicating negative, zero, carry out, overflow, and optional saturation; and executing subsequent operations conditioned upon the condition code flags set.