Patent ID: 6847556

Claim:
A method for operating a flash memory device that is constituted by arraying silicon-oxide-nitride-oxide-semiconductor (SONOS) memory cells including a drain and a source formed in a substrate, a channel formed between the drain and the source, a gate formed over the channel, and a multi-layered dielectric layer of an oxide layer, a nitride layer, and an oxide layer formed between the gate and the substrate in the NOR form, the method comprising: applying voltages to one selected from the SONOS memory cells and programming the selected SONOS memory cell so that hot electrons are injected into at least one of either the interface between the oxide layer and the nitride layer or into the nitride layer from the channel and trapped in at least one of either the interface between the oxide layer and the nitride layer or in the nitride layer to increase a threshold voltage; and applying a positive voltage to the substrate, at least one of either a ground voltage or a negative voltage to the gate and floating at least one of either the source or the drain to reduce the threshold voltage to perform at least one of either removing trapped electrons using Fowler-Nordheim tunneling or erasing the trapped electrons by injecting hot holes created between one of either the source and the substrate or between the drain and the substrate under a voltage condition into the multi-layered dielectric layer.