Patent ID: 8853042

Claim:
A method of forming an integrated circuit (IC) including a core PMOS transistor and a non-core PMOS transistor, comprising: forming over a semiconductor surface of a substrate a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric, wherein said gate dielectric for said non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to said gate dielectric for said core gate structure, wherein said gate electrode comprises polysilicon and said gate dielectric for said non-core gate structure comprises a low % nitrogen silicon oxynitride having a nitrogen concentration of at least 1×10 19 /cm 3 at an interface between said polysilicon with said low % nitrogen silicon oxynitride; performing p-type lightly doped drain (PLDD) implantation including a boron comprising specie to establish source/drain extension regions in said substrate on either side of said non-core and said core gate structure, wherein said PLDD implantation further comprises selective co-implanting carbon, nitrogen and indium into said source/drain extension region of said non-core gate structure, wherein said core gate structure is masked from at least one of said carbon, said nitrogen and said indium implant during said selective co-implanting; performing source and drain implantation to establish source/drain regions for said non-core and said core gate structure, wherein said source/drain regions are distanced from said non-core and said core gate structures further than their respective source/drain extension regions, and source/drain annealing after said performing source and drain implantation, wherein at least one ultra high temperature (UHT) anneal is included after said selective co-implanting, said UHT anneal providing a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at said peak temperature ≦10 seconds.