Patent ID: 7829926

Claim:
A semiconductor structure, comprising: (a) a substrate; (b) 2 N semiconductor regions on the substrate, wherein N is a positive integer, and wherein the 2 N semiconductor regions are parallel to one another and run in a first direction; (c) first N gate electrode lines on the 2 N semiconductor regions, such that an intersection transistor exists at each of intersections between the first N gate electrode lines and the 2 N semiconductor regions, wherein the first N gate electrode lines run in a second direction which is perpendicular to the first direction, and wherein the first N gate electrode lines are electrically insulated from the 2 N semiconductor regions; (d) a contact region electrically coupled to the 2 N semiconductor regions; and (e) a first plurality of memory cells on the 2 N semiconductor regions, wherein the first N gate electrode lines are disposed between the first plurality of memory cells and the contact region, wherein in response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells on only one of the 2 N semiconductor regions are selected, and wherein intersection transistors on each semiconductor region of the 2 N semiconductor regions form a unique combination in terms of channel types.