Patent ID: 8214172

Claim:
A system for identifying the location of defective field reparable units comprised of scan cells in a circuit under diagnosis (CUD) comprising: a test pattern generator configured to generate a set of test patterns for scanning through scan cells of the CUD which are arranged in tiles such that at least one tile includes scan cells from a plurality of field repairable units, wherein the CUD is comprised of field repairable units composed of different numbers of scan cells; a compressor block configured to generate compressed signatures of CUD responses to the set of test patterns, the compressor block including separate signature register blocks, each signature register block configured to receive CUD responses to the set of test patterns from tiles in a row of the CUD that is different from rows of tiles received and processed by other signature register blocks; a concealment circuit configured to conceal CUD responses from a set of rows of scan cells in a first tile by setting a response to the set of test patterns from the first set of rows of scan cells to a pre-determined value, wherein the first set of rows of scan cells include all scan cells contributed to the first tile by at least one field repairable unit; and error location finder block configured to analyze the compressed signatures and to determine that a second field repairable unit different from the at least one field repairable unit is defective if a response to the set of test patterns from rows of non-concealed scan cells in the first tile indicates a defect; wherein the at least one field repairable unit is a single first field repairable unit and wherein the error location finder block is further configured to determine that the first field repairable unit is defective if the response from the rows of non-concealed scan cells indicates that there is no defect in the response from the rows of non-concealed scan cells.