Patent ID: 8024551

Claim:
A pipelined processor containing an apparatus for reducing pipeline stalls between a compute unit and an address unit, comprising: plurality of compute units each having a pipeline with stages for computing results in response to instructions of an algorithm; said plurality of compute units each including a first compute unit block in a first stage of the pipeline, a second compute unit block in a second stage of the pipeline, and a local random access memory array within the second stage of the pipeline, the array for storing predetermined sets of function values related to the computed results for predetermined sets of instructions of said algorithm, to provide within the pipeline of the compute unit direct mapping of computed results to one or more related functions; and a register file shared by said plurality of compute units, wherein the first compute unit block, the second compute unit block, and the local random access memory array of each compute unit are configurable so as to provide a local data path between (i) the first compute unit block of each compute unit and (ii) one of the second compute unit block and the local random access memory array of each compute unit without utilizing a system bus, and wherein local random access memory arrays are filled with different values in parallel from said register file.