Patent ID: 7236397

Claim:
A redundancy circuit for a NAND flash memory device, comprising: a plurality of main cell blocks in which a plurality of memory cells are connected, to store data; a redundancy cell block to repair the memory cells of the main cell blocks; a main page buffer unit to sense the data of the memory cells of the main cell blocks, or to buffer external data and apply the buffered data to the main cell blocks; a redundancy page buffer unit to sense the data of the memory cells of the redundancy cell block, or buffer the external data and apply the buffered data to the redundancy cell block; a content addressable memory(CAM) cell unit to store information on a repaired address, and output a redundancy control signal; and a repair select unit to apply the external data to the main page buffer unit or the redundancy page buffer unit according to the redundancy control signal, the repair select unit comprising: a latch to latch a predetermined signal; a first NMOS transistor connected to a first input terminal of the latch, to control the signal of the latch according to the redundancy control signal; a second NMOS transistor connected to a second input terminal of the latch, to reset the latch according to an external content addressable memory(CAM) reset signal; a third NMOS transistor to transmit the external data to the main page buffer unit according to the first input terminal of the latch; and a fourth NMOS transistor to transmit the external data to the redundancy page buffer unit according to the second input terminal of the latch.