Patent ID: 7936604

Claim:
A twin MONOS memory array comprising: a plurality of memory cells two dimensionally disposed in a first direction and in a second direction wherein each pair of said memory cells comprises a control gate pair having an ONO memory element thereunder, wherein each control gate is shared by two word gates, wherein a first control gate in said control gate pair is accessed by a first of said two word gates adjacent to said first control gate and wherein a second control gate in said control gate pair is accessed by a second of said two word gates adjacent to said second control gate; a plurality of bit lines extending in said first direction; a plurality of said word gates extending in said second direction; a plurality of said control gates extending in said second direction; and structures for applying a select voltage to some of said control gate pairs, for applying an override voltage to others of said control gate pairs, for applying word gate voltages, and for applying bit line voltages wherein said memory array is divided into two or more virtual banks of pairs of memory cells wherein control gates sharing a word line are in different virtual banks, wherein at a given time, one of said virtual banks is selected and all other of said virtual banks are unselected, wherein control gate pairs in said selected one of said virtual banks are preset to a select voltage prior to reading any memory cell and wherein control gate pairs in all other unselected said virtual banks are preset to an override voltage prior to reading any memory cell and wherein reading a memory element in said selected virtual bank requires setting only word gate voltages and bit line voltages.