Patent ID: 7202528

Claim:
A monolithic integrated circuit comprising: a substrate having opposed first and second major surfaces; and first and second junction field-effect transistors on discrete locations on the first major surface of the substrate, each of the first and second junction field-effect transistors comprising: a drain layer of an n-type semiconductor material on and non-coextensive with the first major surface of the substrate such that portions of the substrate surrounding the drain layer are exposed; a drift layer of an n-type semiconductor material on and non-coextensive with the drain layer such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer; one or more raised regions on discrete locations on the drift layer, each raised region comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the semiconductor material of the source region having a higher conductivity than that of the channel region; a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with n-type material of the drift layer and the channel region(s); ohmic contacts on the gate and source regions and on exposed portions of the drain layer; a first electrical connection between the source ohmic contact of the first junction field-effect transistor and the gate ohmic contact of the second junction field-effect transistor; and a second electrical connection between the drain ohmic contact of the first junction field-effect transistor and the source ohmic contact of the second junction field-effect transistor.