Patent ID: 7049658

Claim:
A power semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer; a first main electrode electrically in contact with the first semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively formed in surface regions of the second and third semiconductor layers; a fifth semiconductor layer of the first conductivity type selectively formed in a surface region of the fourth semiconductor layer; a second main electrode formed in contact with surfaces of the fourth and fifth semiconductor layers; and a control electrode formed on surfaces of the second, fourth and fifth semiconductor layers, wherein an impurity concentration of the first semiconductor layer is lower than that of the second semiconductor layer; and a layer thickness ratio A is given by an expression: 0< A=t/ ( t+d )≦0.72 where t is a thickness of the first semiconductor layer, and d is a thickness of the second semiconductor layer; and wherein a void is present in a border region between the second semiconductor layer and the third semiconductor layer.