Patent ID: 7024606

Claim:
A method of generating a test pattern for an integrated circuit set in m scan flip-flops (m indicates any natural number) when m outputs from a logical circuit are applied to m output terminals through m scan flip-flops and m output buffers, comprising: a first process of counting the total number of output buffers, whose output values change, when said m scan flip-flops output an input pattern to said m output buffers; a second process of checking a total noise value generated from all output buffers counted in said first process based on a noise value defined for each of said m output buffers; a third process of selecting output buffers from the total output buffers counted in said first process such that said total noise value is at most equal to an allowable noise value; and a fourth process of outputting the test pattern obtained by amending the input pattern output to the m output buffers such that only the output buffers selected in said third process can change output values, thereby insuring that said total noise value is at most equal to said allowable noise value upon performing said fourth process.