Patent ID: 8736327

Claim:
A time-to-digital converter (TDC) circuit, comprising: a first delay circuit configured to include an even number of first inverting delay devices connected in series to form a loop, each of the first inverting delay devices outputting a signal having a logical value inverted from the logical value of an input signal after a first signal delay period; a second delay circuit configured to include the same even number of second inverting delay devices connected in series to form a loop as that of the first inverting delay devices, each of the second inverting delay devices outputting a signal having a logical value inverted from the logical value of an input signal after a second signal delay period different from the first signal delay period; a first pulse signal drive circuit configured to receive a first input signal and cause any of the first inverting delay devices to produce a first pulse signal; a second pulse signal drive circuit configured to receive a second input signal and cause any of the second inverting delay devices to produce a second pulse signal; a plurality of first flip-flop circuits configured to latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices corresponding to the second inverting delay devices or pulse signals produced by the first inverting delay devices in response to the first pulse signal based on fourth pulse signals including the second pulse signal or pulse signals produced by the second inverting delay devices in response to the second pulse signal; a first counter configured to count the third pulse signal produced by any one of the first inverting delay devices; a second counter configured to count the fourth pulse signal produced by any one of the second inverting delay devices; and a detection result output circuit configured to store a first count from the first counter and a second count from the second counter when the plurality of first flip-flop circuits latch the third pulse signals based on the fourth pulse signals and the logical value of the signal latched by any of the plurality of first flip-flop circuits undergoes a first change.