Patent ID: 7203919

Claim:
A method for retiming an integrated circuit in an electronic design automation (EDA) environment, comprising: performing a timing analysis for one or more paths in the integrated circuit to obtain delay times for a signal propagating along the paths; selecting a path based on the delay times obtained, the path selected having a delay time that fails a timing constraint, the path selected originating at a source sequential element and ending at a destination sequential element, the path selected further comprising two or more logic instances; determining a retiming location along the path selected where one of the source sequential element or the destination sequential element can be repositioned in order to satisfy the timing constraint, the retiming location being at least two logic instances from the one of the source sequential element or the destination sequential element; updating a design database of the integrated circuit to reposition the one of the source sequential element or the destination sequential element to the retiming location; and storing the updated design database.