Patent ID: 7242599

Claim:
A content addressable memory comprising: a plurality of cells arranged in rows and columns, the cells in each row constituting a self-analyzing memory word capable of storing a plurality of data bits; a plurality of local word buses, each connectable to a self-analyzing memory word; a first control bus configured to select a first set of cells comprising cells from each self-analyzing memory word; a second control bus configured to select a second disjoint set of cells comprising cells from each self-analyzing memory word; a third control bus connectable to each cell and configured to enable toggles of the second set cells; wherein each self-analyzing memory word comprises circuitry that is logically reversible, approximately adiabatic and configured to perform a micro-operation on the cells that constitute the self-analyzing memory word such that the bit values of cells from the second set are toggled if and only if all bit values of cells found in the first set are true; and wherein the logically reversible circuitry comprises a toggle circuit comprising a capacitor configured to sample the current state of each cell and allow a complement of the sampled state to become established within the cell; and wherein all of the circuitry in each cell is asymptotically adiabatic except for the capacitor circuit that is configured to sample the current state of each cell.