Patent ID: 7727885

Claim:
A method of fabricating a semiconductor device, comprising: forming a first conductive via in a first dielectric layer; forming a second dielectric layer over the first dielectric layer; forming a conductive trench comprised of a conductive material in the second dielectric layer; forming an etch stop layer over the trench, wherein the etch stop layer has a predetermined thickness; mitigating diffusion of the conductive material through the etch stop layer according to the predetermined thickness of the etch stop layer; forming a third dielectric layer over the etch stop layer; forming via openings in the third dielectric layer; and preventing void formation within the conductive trench; wherein forming the conductive trench comprises: forming a resist mask over the second dielectric layer; patterning trench openings within the second dielectric layer; removing the resist mask; filling the trench openings with a copper material via an electrochemical deposition process; and removing excess copper material by a planarization process; and further comprising performing the electrochemical deposition process at a temperature greater than 50° C., and increasing grain size and mitigating hillock formation in the deposited copper material in response to performing the electrochemical deposition process at a temperature greater than 50° C.