Patent ID: 8705268

Claim:
A circuit, comprising: at least one bit cell having a first input/output (I/O) terminal coupled to a first bit line, a coupling of the first I/O terminal to the first bit line controlled by a state of a word-line, and a second input/output (I/O) terminal coupled to a second bit line, a coupling of the second I/O terminal to the second bit line controlled by the state of the word-line; a word-line driver having an output terminal coupled to the word-line; a selector having a first input terminal coupled to a first power supply node, a second input terminal coupled to a second power supply node, a third input terminal coupled to a first control signal source, and an output terminal coupled to a supply rail of the word-line driver; and a voltage regulator having a first input terminal coupled to a third power supply node, a second input terminal coupled to a second control signal source, and an output terminal coupled to the second power supply node.