Patent ID: 8880967

Claim:
An integrated circuit comprising: A. input pads; B. output pads; C. core circuitry coupled between the input pads and the output pads; D. output circuitry coupled between the core circuitry and an output, the output circuitry including: i. a tri-state buffer having a core input lead coupled to a core output lead of the core circuitry, a data output lead connected to an output pad, and a tristate enable input lead; ii. comparator circuitry having a core input coupled to the core output lead, a response input connected to the output pad, and an enable input lead connected to the tristate enable input of the tri-state buffer; and iii. multiplex circuitry having inputs connected to core output leads of the core circuitry, a core select input, and a selected core output connected to the core input of the compare circuitry.