Patent ID: 6972200

Claim:
A method for in situ electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising: providing one or more integrated circuit (IC) dice, each with a surface having interconnection bumps thereon; providing a substrate with conductive pads deposited on a surface thereof for flip-chip attachment to the interconnection bumps of the one or more IC dice; providing a plurality of probes for contacting the substrate; positioning the one or more IC dice on the surface of the substrate with the interconnection bumps of the one or more IC dice in conductive contact with the conductive pads of the substrate to form the flip-chip semiconductor assembly; contacting the substrate with the plurality of probes; while the substrate is in contact with the plurality of probes and the one or more IC dice are positioned on the surface of the substrate, and before sealing of the one or more IC dice, electrically testing the flip-chip semiconductor assembly using the plurality of probes; repairing the flip-chip semiconductor assembly if it fails the electrical testing, repairing comprising at least one of: removing and replacing at least one of the one or more IC dice of the assembly; repairing the interconnection bumps of the at least one of the IC dice of the assembly; and repairing at least one of the conductive pads of the substrate; speed grading the flip-chip semiconductor assembly; and sealing the one or more IC dice of the flip-chip semiconductor assembly.