Patent ID: 7174486

Claim:
A method for enabling a repair of defective memory in an integrated circuit design, said design having memory locations, redundant memory, and a central location for ordered fuses adapted to identify in compressed format defective sections of each of the memory locations, said defective sections adapted to be replaced by sections of the redundant memory, said ordered fuses having a fuse bit pattern, said fuse bit pattern sequentially representing said defective sections in said compressed format, said method comprising: determining the order in which the memory locations are wired together; designing a shift register of latches through the memory locations in accordance with said order; and associating each of the latches with a corresponding bit of an uncompressed bit pattern from which said fuse bit pattern is derived, said uncompressed bit pattern sequentially representing said defective sections in uncompressed format, wherein said associating comprises generating a logical-to-physical cross reference (LPXREF) dataset encoded within a first computer readable medium, said generating the LPXREF dataset comprising generating a fuse portion of the LPXREF dataset and generating a memory portion of the LPXREF dataset; wherein the fuse portion of the LPXREF dataset comprises an array of fuse elements, the fuse elements respectively corresponding to the ordered fuses and ordered in correspondence to the ordered fuses, each fuse element comprising a fuse identifier and associated spatial coordinates of the corresponding fuse; wherein the memory portion of the LPXREF dataset comprises a sequence of memory data blocks ordered in accordance with the order in which the memory locations are wired together; and wherein the memory data blocks facilitate forming a sequence of address bits of the failed memory addresses of said defective sections, said sequence of address bits corresponding to said uncompressed bit pattern, said address bits derived from built-in self test (BIST) latches that comprise said address bits, said sequence of address bits ordered in accordance with the sequence of latches in the shift register and adapted to be compressed into said fuse bit pattern.