Patent ID: 7410829

Claim:
A fabrication method for a semiconductor chip package, comprising: preparing a first semiconductor chip, said first semiconductor chip including a frame section having a top face and a bottom face, a movable structure having a movable section formed in said frame section, a plurality of first electrode pads arranged on said top face of said frame section, a first sealing section provided on said top face of said frame section and having a closed loop shape to surround said movable structure, and a thin plate member provided on said first sealing section for sealing said movable structure; preparing a second semiconductor chip, said second semiconductor chip including a first surface having a plurality of sides, a second surface in parallel to the first surface, and a plurality of second electrode pads arranged on said first surface side; preparing a substrate, said substrate including a first main surface having a semiconductor chip mounting area, a second main surface in parallel to the first main surface, and a plurality of third electrode pads formed along an edge of said first main surface outside said semiconductor chip mounting area; mounting said first and second semiconductor chips on said chip mounting area of said substrate; forming first bonding wires for connecting said plurality of first electrode pads to said plurality of second electrode pads respectively; and forming second bonding wires for connecting said plurality of second electrode pads to said plurality of third electrode pads respectively.