Patent ID: 7721074

Claim:
A load/store architecture processing system, comprising: a hardware processor that includes an execution unit, a plurality of software accessible registers coupled to the execution unit, and a data moving engine coupled to the execution unit; and a buffer coupled to the hardware processor, the processor system being configured such that: following execution of a read-tie instruction that associates a memory address of the buffer with a register address of a first software accessible register, the data moving engine causes the execution unit to operate upon data read from the buffer in response to instructions that specify operating upon data from the first software accessible register, following execution of an untie instruction that disassociates the memory address of the buffer from the register address of the first software accessible register, the execution unit operates upon data read from the first software accessible register in response to instructions that specify operating upon data from the first software accessible register, and prior to execution of the read-tie instruction a first value corresponding to a number of elements to be accessed from the buffer is stored in a location, and a conditional branch instruction following the read-tie instruction accesses the location based on the memory address of the buffer, wherein the location is not part of the buffer.