Patent ID: 7376923

Claim:
A layout designing apparatus comprising: storage means for storing circuit data on a circuit constituted by a plurality of transistors; search means of searching for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network represented by the circuit data; extraction means of extracting a set of routes having the smallest number of routes in sets of routes found as search results by said search means; layout width determination means of determining a layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between the source or drain electrodes of some of the adjacent pairs of the transistors not combined into a common electrode, the number of the transistors, and the number of routes contained in the set of routes extracted by said extraction means; layout determination means of forming information on a layout in which the source, drain, and gate electrodes of the transistors included in said circuit are placed in a small-width region having the width determined by said layout width determination means; and output means of outputting the layout information determined by said layout determination means.