Patent ID: 6897708

Claim:
A step-up power supply device comprising a semiconductor booster circuit, comprising: a power supply input terminal being supplied with a power-supply voltage; a clock input terminal being supplied with a reference clock signal of a predetermined duty cycle that alternates between said power-supply voltage and a ground voltage; a clock inverting circuit connected to said clock input terminal providing a clock signal generated by inverting said reference clock signal; a first capacitor having its one end connected to said clock input terminal; a second capacitor having its one end connected to the output of said clock inverting circuit; a first FET transistor of a first conduction type having its drain electrode connected to the other end of said first capacitor and its gate electrode connected to the other end of said second capacitor; a second FET transistor of the first conduction type having its drain electrode connected to the other end of said second capacitor and its gate electrode connected to the other end of said first capacitor; a third FET transistor of a second conduction type having its source electrode connected to said power supply input terminal, its gate electrode connected to the output of said clock inverting circuit, and its drain electrode connected to the other end of said first capacitor, the drain electrode of said first FET transistor, and the gate electrode of said second FET transistor; a fourth FET transistor of the second conduction type having its source electrode connected to said power supply input terminal, its gate electrode connected to said clock input terminal, and its drain electrode connected to the other end of said second capacitor, the drain electrode of said second FET transistor, and the gate electrode of said first FET transistor; and an external output terminal connected to the source electrodes of said first and second FET transistors, the gate electrode of the first FET transistor not being directly connected to the gate electrode of the third FET transistor and the gate electrode of the second FET transistor not being directly connected to the gate electrode of the fourth FET transistor.