Patent ID: 8143117

Claim:
An active device array substrate, comprising: a substrate; a first patterned semiconductor layer disposed on the substrate; a gate insulator disposed on the substrate and covering the first patterned semiconductor layer; a first patterned conductive layer disposed on the gate insulator; a first dielectric layer disposed on the gate insulator and covering the first patterned conductive layer, wherein the first dielectric layer and the gate insulator comprise a plurality of first contact holes exposing the first patterned semiconductor layer; a second patterned conductive layer, disposed on the first dielectric layer, wherein the second patterned conductive layer comprises a plurality of contact conductors and a bottom electrode, and the active layer being substantially located within an area of the bottom electrode; a second patterned semiconductor layer, disposed on the second patterned conductive layer, wherein the second patterned semiconductor layer comprises an active layer disposed on the bottom electrode; a second dielectric layer, disposed on the first dielectric layer, wherein the second dielectric layer comprises a plurality of second contact holes to expose the active layer; and a third patterned conductive layer, disposed on the second dielectric layer, wherein a portion of the third patterned conductive layer is electrically connected to the active layer through a portion of the second contact holes.