Patent ID: 8115522

Claim:
A prescaler circuit that divides a frequency of a clock signal by an integer 3 or 4 comprising: a first flip-flop circuit that detects second output data in synchronization with the clock signal and outputs the detected data as first output data; and a second flip-flop circuit that detects the first output data in synchronization with the clock signal and outputs the detected data as the second output data to the first flip-flop circuit; wherein the first flip-flop circuit comprises: a master-side latch circuit that generates intermediate data in synchronization with the clock signal; a slave-side latch circuit that detects the intermediate data in synchronization with the clock signal and outputs the detected intermediate data as the first output data; and the control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4; and wherein the master-side latch circuit generates the intermediate data based on the second output data and the control signal.