Patent ID: 7355891

Claim:
A device including an array of memory transistors, wherein each memory transistor comprises: a first source/drain region, a second source/drain region, and a channel in a substrate, the channel regions extending from the first source/drain region to the second source/drain region; a first charge storage region overlying and insulated from a first portion of the channel adjacent the first source/drain region, wherein a first charge stored on the first charge storage region represents a first multi-bit value; a second charge storage region overlying and insulated from a second portion of the channel adjacent the second source/drain region, a gap being between the second charge storage region and the first charge storage region and overlying a central portion of the channel between the first and second portions of the channel, wherein a second charge stored on the second charge storage region represents a second multi-bit value; and a control gate overlying and insulated from the first and second charge storage regions, the control gate extending into the gap between the first and second charge storage regions and modulating the central portion of the channel.