Patent ID: 7476813

Claim:
A substrate comprising: a core layer; at least two buildup layers on one side of the core layer, and at least one buildup layer on an opposing side of the core layer; a core via positioned within the core layer along an axis; a plurality of distinct and separated micro-vias each positioned within a different one of the buildup layers, where each micro-via has a diameter substantially smaller than a diameter of the core via; a plurality of traces electrically interconnecting each of the micro-vias and the core via to form an electrically conductive path having an impedance substantially matching a target impedance, wherein the plurality of traces include: at least two traces on the first side of the core layer and positioned along a first plane that intersects with the axis; and at least one trace on the second side of the core layer and positioned along a second plane that intersects with the axis, wherein the second plane is distinct from the first plane.