Patent ID: 6946377

Claim:
A method of fabricating a MOS transistor, comprising the steps of: creating a form structure above a starting structure, the form structure having an opening exposing a surface portion of the starting structure; forming a spacer in the opening of the form structure, the spacer extending over part of the starting structure surface and along a sidewall of the form structure opening; disposing a semiconductor material in the opening of the form structure to create a formed semiconductor body on the exposed surface of the starting structure; removing the form structure and the spacer; forming a gate structure disposed along a central portion of the formed semiconductor body, the gate structure comprising a conductive gate electrode and a gate dielectric disposed between the gate electrode and the formed semiconductor body; and doping portions of the formed semiconductor body at opposing ends of said semiconductor body to form source/drains, a portion of said semiconductor body beneath said gate structure disposed between said source/drains.