Patent ID: 6992390

Claim:
An interconnection structure for semiconductor integrated circuits which comprises a substrate comprising at least one dielectric layer comprising at least one trench in said dielectric layer, an adhesion/diffusion barrier layer in said trench, a redundant layer on said adhesion/diffusion barrier layer, an overlayer on said redundant layer, and an interconnect material on said overlayer sufficient to fill said at least one trench; wherein: said adhesion/diffusion barrier layer comprises a metal, a metal alloy, or metal nitride, wherein the metal is selected from the group consisting of Ta, Ti, and W; said overlayer comprises: (i) a metal, a metal alloy, or metal nitride, wherein the metal is selected from the group consisting of Ta, Ti, and W; or (ii) a metal or metal alloy, wherein the metal is selected from the group consisting of Mo, Be, Cr, Co, Ir, Ni, Nb, Os, Pd, Pt, Rb, Rh, Ru, and Th; said redundant layer comprises α-Ta; and said interconnect material comprises Cu or Cu alloy and when said overlayer comprises a material selected from (i), said structure further comprises an additional layer comprising α-Ta, wherein said additional layer is between said overlayer and said interconnect material.