Patent ID: 7821340

Claim:
An output stage circuit, comprising: a first PMOS transistor, the bulk of the first PMOS transistor being connected to a first operating voltage, the drain of the first PMOS transistor being connected to a first mid level voltage, and the gate of the first PMOS transistor being connected to a first control signal; a second PMOS transistor, the bulk and the source of the second PMOS transistor being connected to the first operating voltage, and the gate of the second PMOS transistor being connected to a second control signal; a first NMOS transistor, the drain of the first NMOS transistor being connected to a second mid level voltage, the bulk of the first NMOS transistor being connected to a second operating voltage, and the gate of the first NMOS transistor being connected to a third control signal, wherein the second operating voltage is less than the first operating voltage; and a second NMOS transistor, the source and the bulk of the second NMOS transistor being connected to the second operating voltage, and the gate of the second NMOS transistor being connected to a fourth control signal; wherein the transistors are fabricated using twin-well CMOS process and the drains of the transistors are connected to each other at an output terminal, and wherein at least one of the control signals is enabled to turn on at least one of the transistors correspondingly for each time interval.