Patent ID: 7996632

Claim:
A device for executing atomics, comprising: a crossbar that includes a processor-to-cache interface (PCX) and a cache-to-processor interface (CPX); a processor coupled to the crossbar, the processor including a control unit and a datapath, wherein the processor: controls execution of an atomic instruction in accordance with an instruction set architecture that includes one or more atomic operations within the instruction set, in which for each of the one or more atomic operations a load, an arithmetic or logical operation, and a store are each capable of being performed within the atomic operation, wherein the instruction set is such that source data for a memory address can be divided among more than one bank of a plurality of banks of a banked memory cache, wherein the banked memory cache is coupled to the crossbar, wherein each of the plurality of banks of the banked memory cache includes a plurality of separate lines, and wherein controlling execution of the atomic instruction is accomplished such that controlling execution of the atomic instruction includes, for the one or more atomic operations: generating an atomic memory address; determining whether the atomic memory address source data is included in its entirety in one bank of the plurality of banks of the banked memory cache; and if it is determined that the atomic memory address source data is included in its entirety in one bank of the plurality of banks of the banked memory cache: enabling the bank that includes the atomic memory address source data to perform the arithmetic or logical operation of the one or more atomic operations within the bank that includes the atomic memory address source data; otherwise if it is determined that the atomic memory address source data is divided among two or more particular banks of the banked memory cache: generating requests to fetch each part of the atomic memory address source data to the processor via a corresponding one of the plurality of separate lines for the two or more particular banks of the banked memory cache; and asserting a lock condition on each corresponding one of the plurality of separate lines; and performing the arithmetic or logical operation of the at least one of the atomic operations within the processor; and wherein the processor in conjunction with the crossbar performs multiple atomic operations concurrently in parallel via the separate lines of the banked memory cache.