Patent ID: 7391072

Claim:
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a vertical p-type non-volatile memory cell including: a first source/drain region formed on an n-type substrate; a body region including a p-type channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the p-type channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by an intergate insulator formed of at least two metal oxide materials with different barrier heights with the lower barrier height material being in contact with the control gate and having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate to promote easier erase operations using electron tunneling from the floating gate to the control gate and to promote longer retention.