Patent ID: 7640420

Claim:
A processor comprising: one or more processing cores, cache memory coupled to the one or more processing cores, and a processing logic coupled to the one or more processing cores and the cache memory, wherein the processing logic further comprises, a first unit to store data corresponding to executed load instructions, wherein the data to be stored in the first unit is to be indexed according to the instruction pointer (IP) values associated with the executed load instructions; a second unit to produce a predicted address for a next load instruction, wherein the predicted address is to be based, at least in part, on a constant stride value that depends, at least in part of, on target address differences between executed load instructions; and a third unit to generate an instruction pointer pre-fetch (IPP) request based, at least in part, on the predicted address wherein the first unit is to store the data corresponding to the executed load instructions in an IP history array, wherein an entry in the IP history array comprises: a first field to store data corresponding to a last demand address; a second field to store data corresponding to a last stride value; a third field to store data corresponding to a linear address that facilitates avoiding pre-fetching across memory pages; a fourth field to store data to identify a state in a state machine; and a fifth field to store data corresponding to a last pre-fetched address that facilitates avoiding redundant pre-fetch requests.