Patent ID: 7783206

Claim:
A system for multi-rate, high-sensitivity clock and data recovery, comprising: a connector for an optical input; a clock and data recovery circuit, wherein the clock and data recovery circuit performs clock and data recovery at a plurality of data rates that are digitally selectable and defined by a control switch configuration; a decision threshold circuit; an internal power supply comprising a plurality of voltage supply sources; an optical-to-electrical converter; an external electrical output; a plurality of clock outputs; and a connector for an external electrical input, wherein the system utilizes an RF electrical input, wherein RF signal evaluation is performed without the need for an optical input reference, and wherein an RF signal is split between the clock and data recovery circuit and a digital communications analyzer, lock is achieved, and a trigger is provided; wherein the system provides clock and data recovery, optical-to-electrical conversion, and the plurality of clock outputs; and wherein the system for multi-rate, high-sensitivity clock and data recovery is comprised in a single, stand-alone hardware unit.