Patent ID: 8878714

Claim:
A method for clockless conversion of voltage value to digital word consisting in a detection of a trigger signal by the use of a control module and in mapping the converted voltage value to a portion of electric charge proportional to this converted voltage value delivered by use of a current source while a portion of electric charge is accumulated in a sampling capacitor or in the sampling capacitor and in a capacitor having a highest capacitance value in an array of redistribution, which is connected in parallel to the sampling capacitor, until a voltage increasing on the sampling capacitor observed at the same time by the use of a comparator is equal to the converted voltage value, and then consisting in a realization of a process of accumulated electric charge redistribution in the array of redistribution in a known way by means of the control module by changes of states of signals from relevant control outputs, while the array of redistribution comprises an array of on-off switches, of change-over switches and of capacitors such that a capacitance value of each capacitor of a given index is twice as high as a capacitance value of a capacitor of a previous index, and also consisting in an assignment of relevant values to bits of the digital word by means of the control module characterized in that after termination of accumulation of electric charge in the sampling capacitor (C n ) or in the sampling capacitor (C n ) and in the capacitor (C n-1 ) having the highest capacitance value in the array of redistribution which is connected to the sampling capacitor (C n ) in parallel and after detection of the trigger signal by means of the control module (CM), electric charge is accumulated in the additional sampling capacitor (C nA ), and next the process of redistribution of electric charge accumulated in the additional sampling capacitor (C nA ) is realized and relevant values are assigned to bits (b n-1 , b n-2 , . . . , b 1 , b 0 ) in the digital word by means of the control module (CM) while accumulation of electric charge in the additional sampling capacitor (C nA ) and the process of redistribution of electric charge accumulated in the additional sampling capacitor (C nA ) and assignment of relevant values to bits (b n-1 , b n-2 , . . . , b 1 , b 0 ) in the digital word are realized such as for the sampling capacitor (C n ).