Patent ID: 8713410

Claim:
A data storage apparatus comprising: a channel controller configured to control writing to and reading from each of nonvolatile memories of a plurality of channels, detect errors in data read from the nonvolatile memory of each channel and correct the errors; an error correction controller configured to perform an inter-channel error correction process on first data designated by the channel controller, the designated data indicating that the errors cannot be corrected by the channel controller, wherein the inter-channel error correction process uses inter-channel error correction codes and the inter-channel error correction codes are generated by using the data of the channels written in the writing by the channel controller; and an additional correction module configured to designate second data to be subjected to an additional correction process and notify the error correction controller of the second data, if errors are detected in the second data by the channel controller while the channel controller is performing a corrective read process of reading data necessary to perform the inter-channel error correction process.