Patent ID: 7596053

Claim:
A circuit for reading data from a buffer memory, the buffer memory being a Synchronous Dynamic Random access Memory (“SDRAM”) or a Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”), the circuit comprising: logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal, wherein the DDR receives an SDRAM clock signal and the DQS signal is generated from the DDR based on the SDRAM clock signal; at least one delay element that delays the data; and at least one logic element that receives a buffer clock signal and that selectively adjusts an alignment of the DQS signal based on the buffer clock signal, the SDRAM clock signal, and a selected one of a plurality of latencies, wherein the DQS signal is aligned with at least one of a positive edge and a negative edge of the SDRAM clock signal.