Patent ID: 7625805

Claim:
A method of forming a wafer for integrated circuits comprising low voltage elements and high voltage elements, wherein chip regions of different potentials are separated by dielectrically insulating regions formed as isolation trenches extending downward from a first planar surface, at least one of said isolation trenches receiving a material that is oxidizable in an oxygen containing atmosphere at an elevated temperature, said method comprising a sequence of process steps after forming at least two vertical insulating layers in said at least one of said isolation trenches and a horizontal insulating layer on said first planar surface to provide a second planar surface of an insulating layer above said first planar surface, said sequence comprising: filling said at least one isolation trench with a fill material until a deepest point of an indentation in a resulting fill material layer formed on said first planar surface has a first level that is above a second level defined by said second planar surface; performing a first planarization of said resulting fill material layer; removing a first portion of fill material in said at least one of said isolation trenches by a first over-removal down to a defined depth not deeper than down to half of a trench depth; removing a portion of at least the vertical insulating layers and over-removing a further portion of the fill material so as to reach a height level substantially equal with said vertical insulating layers within said at least one of said isolation trenches; depositing at least one cap layer having a thickness extending above said first planar surface and extending downward to said vertical insulating layers and said fill material within said at least one of said isolation trenches; and performing a further planarization of said cap layer by one of a chemical mechanical polishing process and a resist planarization process to form a cover.