Patent ID: 8854079

Claim:
A system on chip (SoC) comprising: one or more core logic blocks; a memory array coupled to the one or more of the core logic blocks, wherein the memory array comprises: n rows by m columns of data bit cells and one column of parity bit cells, wherein m is odd; parity logic coupled to data outputs of the m columns of data bits and to a data output of the column of parity bit cells, wherein for each row of data bit cells and associated parity bit cell, the parity logic is configured to generate a parity bit responsive to data stored in the data bit cells and to store an inverted representation of the parity bit in the parity bit cell; and control logic coupled to the parity logic and to the one or more core logic blocks, wherein the control logic is configured to cause the one or more core logic blocks to perform a restart operation when a parity error is detected.