Patent ID: 7067367

Claim:
A method for reducing poly-depletion in a dual gate CMOS fabrication process, comprising the steps of: forming an STI oxide film adjacent an active region having an NMOS forming region and a PMOS forming region in a silicon substrate, wherein the area above the boundary between the active region and the STI oxide film is referred to as the fringing portion, wherein the height of the STI oxide film not at or near the fringing portion (referred to as a non-fringing portion) is higher than the height of the STI oxide film at or near the fringing portion and the height of the active region; sequentially forming a gate dielectric film and a polysilicon film on the STI oxide film and the active region formed on the silicon substrate wherein the polysilicon film formed at or near the fringing portion is thicker than the non-fringing portion of the polysilicon film; selectively implanting an N-type impurity and a P-type impurity into the portions of the polysilicon film, which correspond respectively to the NMOS forming region and PMOS forming region of the silicon substrate, by ion implantation; and patterning the polysilicon film having the selectively ion-implanted N-type and P-type impurities and the gate dielectric film to form an N+ polysilicon gate in the NMOS region of the silicon substrate and a P+ polysilicon gate in the PMOS region of the silicon substrate, wherein the ion implantation of the N-type impurity is performed by implanting phosphorus in a dose of 1 to 2×10 16 /cm 2 , after the step of patterning the polysilicon film, heating at a temperature higher than 800 degree Celsius allowing thermal diffusion of the ion-implanted impurities into the bottom portion of the polysilicon film formed at the boundary between the active region and the STI oxide film.