Patent ID: RE40486

Claim:
A non-volatile memory cell comprising: a semiconductor substrate, with a drain and a source in the substrate; a conductive floating gate formed on the substrate between the source and drain with a first insulating layer separating said floating gate from said substrate, said floating gate including a main floating gate region and a small sidewall spacer, said first insulating layer including a first insulating portion separating said small sidewall spacer from the substrate and from the main floating gate region, said a second insulating portion separating said main floating gate region from said substrate, wherein the first insulating portion is thin tunnel oxide that is thinner than said second insulating portion, said small sidewall spacer having a first side contacting the thin tunnel oxide insulation and an opposite side that is electrically couple to the main floating gate region by a conductive connecting layer extending over said opposite side of the sidewall spacer and extending past the thin tunnel oxide to contact the main floating gate region; a control gate formed over the floating gate; and a second insulating layer separating said control gate and said floating gate.