Patent ID: 7493523

Claim:
A computer implemented method for preventing soft error accumulation, the computer implemented method comprising: monitoring a plurality of instructions to be executed by a processor, wherein each of the plurality of instructions reference one of a plurality of registers in the processor; counting a number of cycles between successive references to each of the plurality of registers in the processor; determining whether the number of cycles between successive references to a register within the plurality of registers is greater than a threshold, wherein the threshold is selected dynamically to maximize performance of the processor; responsive to a determination that the number of cycles between successive references to the is greater than the threshold, injecting data refresh instructions that reference the register to prevent soft error accumulation, wherein the data refresh instructions access the register so that data elements in the register are refreshed without slowing down the processor; responsive to a determination that the number of cycles between successive references to the register is not greater than the threshold, determining whether empty issue slots are available for the data refresh instructions; responsive to determining that empty issue slots are available for the data refresh instructions, injecting the data refresh instructions into the empty issue slots; responsive to determining that empty issue slots are unavailable for the data refresh instructions, performing normal instruction issue; updating a register reference counter for the register to indicate when the register was last accessed; and responsive to the register being accessed, passing a reset value to the register reference counter to reset the number of cycles to zero.