Patent ID: 6965267

Claim:
A bipolar differential input stage which includes an input bias current cancellation circuit, comprising: first and second bipolar input transistors having their bases connected to first and second input terminals, respectively, and their emitters connected together at a common emitter node; a first current source connected to said common emitter node and arranged to provide a first bias current I bias1 to said first and second input transistors; a bipolar tracking transistor; a second current source which provides a second bias current I bias2 to said tracking transistor; said input stage arranged such that the collector currents in and the collector-emitter voltages of said first and second input transistors and said tracking transistor are substantially equal when the voltages at said first and second input terminals are equal; and a base current copy circuit arranged to provide a base current I trk to said tracking transistor required to achieve said substantially equal collector current in said tracking transistor, said copy circuit further arranged to provide first and second bias current cancellation currents I cncl1 , I cncl2 to the bases of said first and second input transistors, respectively, such that I cncl1 ≈I cncl2 ≈I trk , thereby reducing the input stages' input bias currents.