Patent ID: 7253480

Claim:
A method for fabricating an electrostatic discharge protection circuit, comprising: providing a substrate; forming a well in the substrate, wherein the well is doped with a first conductive type; forming a buried layer at a lateral junction between the well and the substrate, wherein the buried layer is doped with a second conductive type; forming a sinker layer doped with the second conductive type in the well, wherein the sinker layer is electrically connected to the buried layer; forming a gate on the well; forming a source and a drain in the well at two sides of the gate, wherein the gate and the source/drain constitute an electrostatic discharge (ESD) transistor, and the drain is directly connected to the sinker layer, such that the sinker layer electrically connects the buried layer with the drain of the transistor and an ESD current flows from the source through the well, the buried layer and the sinker layer to the drain; and forming a substrate-connecting region in the well.