Patent ID: 8023356

Claim:
A voltage adjustment circuit of a semiconductor memory apparatus, comprising: a control voltage generating unit configured to selectively output a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each having a different voltage level; a comparing unit configured to receive the control voltage, and external voltage and a reference voltage, and to output a detection voltage; and a voltage generating unit configured to generate an output voltage based on the detection signal, wherein the comparing unit includes: a first node and a second node; a voltage supply unit configured to supply the external voltage the first and second nodes if a level of the output voltage is higher than a level of the reference voltage in response to the control voltage; and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as the detection signal.