Patent ID: 8263462

Claim:
A semiconductor structure comprising: a semiconductor substrate comprising a first portion and a second portion; a first shallow trench isolation (STI) region and a second STI region, wherein the first STI region has a first top surface substantially level with a second top surface of the second STI region; a first Fin field-effect transistor (FinFET) over the first portion of the semiconductor substrate, wherein the first FinFET comprises a first fin having a first fin height, wherein the first fin is adjacent to and above the first STI region; a second FinFET over the second portion of the semiconductor substrate, wherein the second FinFET comprises a second fin having a second fin height different from the first fin height, wherein the second fin is adjacent to and above the second STI region, and wherein a first top surface of the first fin is substantially level with a second top surface of the second fin; a punch-through stopper underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate, and wherein the punch-through stopper is formed of a dielectric material that is an oxidized portion of the first fin; and an additional fin underlying and at least partially vertically overlapping the first fin, wherein the punch-through stopper electrically disconnects the additional fin from the first fin.