Patent ID: 7112835

Claim:
A semiconductor device having a junction capacitance formed in an SOI layer of an SOI substrate constituted by a substrate, at least a surface of which is insulative, and said SOI layer of a first conductivity type provided on said surface of said substrate, said junction capacitance including: a first junction semiconductor region of a second conductivity type formed on said SOI layer; a second junction semiconductor region of a first conductivity type formed on said SOI layer, said first and second junction semiconductor regions having a PN junction portion; a first semiconductor region of the second conductivity type formed on said SOI layer; a second semiconductor region of the first conductivity type formed on said SOI layer independently of said first semiconductor region; and an isolating region provided in an upper layer portion of said SOI layer and serving to isolate said first and second semiconductor regions from each other, wherein said isolating region includes a partial isolating region constituted by a partial insulating region provided in an upper layer portion of said SOI layer and an isolating semiconductor region of the first conductivity type which is a part of said SOI layer present in a lower layer portion, said first junction semiconductor region includes said first semiconductor region, said second junction semiconductor region includes said second semiconductor region and said isolating semiconductor region, and said isolating semiconductor region has a PN junction portion together with said first semiconductor region.