Patent ID: 8447955

Claim:
In a multiprocessor data processing system having at least one weakly-ordered processor and a memory subsystem, a method comprising: performing on-the-fly translation of one or more store instructions of a well-behaved application executing on the at least one weakly-ordered processor; identifying a lock instruction in the one or more store instructions; in response to identifying the lock instruction, entering a lock phase, wherein during the lock phase store instructions of the at least one weakly-ordered processor are not visible to the other processors in the multiprocessor data processing system, and wherein during the lock phase the at least one weakly-ordered processor performs the functions of: issuing one or more intermediate store instructions, wherein the one or more intermediate store instructions are issued without individual sync instructions following each intermediate store operation; tracking a lock operation of the well-behaved application executing on the at least one weakly-ordered processor; detecting when an unlock operation corresponding to the lock operation is scheduled to release a lock operation; in response to detecting the unlock operation is about to be performed to release the lock operation: generating a sync instruction to be issued before the unlock operation is executed; and issuing the generated sync instruction before the unlock operation is executed, wherein the sync instruction guarantees visibility of all of the one or more intermediate store instructions to a point of coherency within the memory subsystem; determining the value of the lock flag from among one of two values the lock flag can be set to, wherein a first value indicates that sync instructions are to be issued following each store operation, and wherein the second value indicates that sync instructions are not be issued following each store operation during a lock phase; detecting when a well-behaved application is loaded for execution on the at least one weakly-ordered processor; in response to detecting loading of the well-behaved application on the at least one weakly-ordered processor, setting the lock flag to the second value; and in response to the lock flag being set to the first value, issuing sync instructions following each store operation of the well-behaved application.