Patent ID: 7338888

Claim:
A method for manufacturing a semiconductor device, comprising: forming a gate structure over a substrate, said gate structure including a gate dielectric, a polysilicon gate electrode located over said gate dielectric, and a protective layer located over said polysilicon gate electrode; forming source/drain regions in said substrate proximate said gate structure; forming a first silicidation metal in contact with said source/drain regions, said protective layer separating said polysilicon gate electrode from said first silicidation metal; forming a blocking layer over said source/drain regions from said first silicidation metal, said blocking layer comprising a metal silicide; removing said protective layer from over said polysilicon gate electrode after forming said blocking layer; forming a second silicidation metal in contact with said polysilicon gate electrode and in contact with said blocking layer; and siliciding said polysilicon gate electrode using said second silicidation metal to form a silicided gate electrode, said blocking layer protecting said source/drain regions from said siliciding.