Patent ID: 8473668

Claim:
A memory device comprising: a memory cell array including at least a first memory cell; a controller configured to determine whether to select the first memory cell based on a number of times that the first memory cell has been erased, and an elapsed time after the first memory cell is erased; and a programming unit, the programming unit being configured to program data in the first memory cell if the first memory cell is selected by the controller; wherein the memory cell array further includes a second memory cell; wherein the controller is configured to select one of the first memory cell and the second memory cell based on a number of times that the second memory cell has been erased, and an elapsed time after the second memory cell is erased, in addition to the number of times that the first memory cell has been erased, and the elapsed time after the first memory cell is erased; and wherein the programming unit is further configured to program data in the second memory cell if the second memory cell is selected by the controller.