Patent ID: 7219317

Claim:
A method of verifying an incremental change to an integrated circuit design comprising steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking polygons in a generic data stream file in the integrated circuit design database to indicate a current state of the integrated circuit design database; (d) applying the engineering change order to the integrated circuit design database; (e) analyzing the integrated circuit design database to generate a list of incremental changes to the integrated circuit design database, the list of incremental changes including all new polygons added to the integrated circuit design and all polygons deleted from the integrated circuit design by the engineering change order; (f) adding all cells that have been relocated in the integrated circuit design or that have changed in cell type to the list of incremental changes; (g) adding all nets that include the cells that were added to the list of incremental changes in step (f) to the list of incremental changes; (h) identifying and marking polygons in the generic data stream file in the integrated circuit design database included in the list of incremental changes to generate a marked integrated circuit design database that distinguishes polygons in the generic data stream file that were changed from the current state; and (i) generating as output the marked integrated circuit design database.