Patent ID: 7470613

Claim:
A method of fabricating an interconnect structure, comprising: providing a substrate; forming, on said substrate, a lower level wire having a side and a bottom, said lower level wire comprising a lower core conductor and an lower conductive liner, said lower conductive liner formed on the side and the bottom of said lower level wire; forming one or more first dielectric pillars in a first portion of said lower level wire, said lower conductive liner formed on sides of said first dielectric pillars; forming an upper level wire in an upper level dielectric layer, said upper level wire having a side and a bottom and one or more vias integrally formed in the bottom of said upper level wire, each via having a side and a bottom, said upper level wire and each via comprising an upper core conductor and an upper conductive liner, said upper conductive liner formed on the side and the bottom of said upper level wire and on the side and bottom of each via; and aligning said upper level wire to said lower level wire such that said upper conductive liner on the bottom of at least a portion of said one or more vias contacts said lower core conductor and at least a portion of said one or more vias contacts said lower conductive liner on said side of at least a portion of said one or more first dielectric pillars to form liner-to-liner contact regions, wherein a first portion of a continuously distributed dielectric material of the upper level dielectric layer is in direct mechanical contact with a first surface of the upper conductive liner, wherein the first portion of the continuously distributed dielectric material of the upper level dielectric layer is on and in direct mechanical contact with a first surface portion of a top surface of one dielectric pillar of the one or more first dielectric pillars at a bottom bounding surface of the first portion of the continuously distributed dielectric material, wherein a second surface of the upper conductive liner is on and in direct mechanical contact with a second surface portion of the top surface of the one dielectric pillar, and wherein the first surface portion of the top surface of the one dielectric pillar and the second surface portion of the top surface of the one dielectric pillar are parallel to each other.