Patent ID: 7230462

Claim:
A clock signal synchronizing device for synchronizing clock signals comprising: a delay module with a variable delay time into which a clock signal is input, is charged with the variably controllable delay time, and is output as a delayed clock signal; a phase comparator for comparing the phase of the clock signal, with the phase of the delayed clock signal, or of a signal obtained therefrom, and outputting a first signal when the phase of the clock signal hurries ahead the phase of the delayed clock signal or of the signal obtained therefrom, and a second signal when the phase of the clock signal runs after the phase of the delayed clock signal or of the signal obtained therefrom; and a filter for receiving the first and second signals, and for transmitting a control signal to the delay module for varying the delay time of the delay module when for a predetermined number of successive clocks the filter receives the first signal or when for a predetermined number of successive clocks the filter receives the second signal, the predetermined number of successive clocks being greater than one.