Patent ID: 6956768

Claim:
A method of programming and subsequently reading a charge trapping dielectric memory device having a first charge storing cell adjacent a first conductive region and a second charge storing cell adjacent a second conductive region, comprising: programming the memory device, including: programming the first charge storing cell to store a first amount of charge, the first amount of charge corresponding to a first cell data state selected from a blank program level or one of a plurality of charged program levels; and programming the second charge storing cell to store a second amount of charge, the second amount of charge corresponding to a second cell data state selected from the blank program level or one of the plurality of charged program levels; and reading one of the charge storing cells, including: comparing a first conductive region to second conductive region current against a plurality of reference currents to determine the data state to which the read charge storing cell is programmed, and wherein the reference currents include a first reference current derived from a maximum complimentary bit disturb threshold voltage condition of a first associated dynamic reference and a minimum lowest program level threshold voltage condition of a second associated dynamic reference.