Patent ID: 6964891

Claim:
A thin film transistor substrate comprising: a substrate; a first transistor structure having a first semiconductor layer formed on said substrate, a first gate insulating film and a first gate electrode, wherein a channel region of said first semiconductor layer under said first gate electrode is intentionally doped with only p-type impurities, said first semiconductor layer includes n-type LDD regions outside the channel region and high impurity concentration n-type source/drain regions outside the n-type LDD regions, and said first gate electrode is made of a lamination of a first metal layer and a second metal layer; a second transistor structure having a second semiconductor layer formed on said substrate, a second gate insulating film and a second gate electrode, wherein a channel region of said second semiconductor layer under said second gate electrode is intentionally doped with only p-type impurities, said second semiconductor layer includes high impurity concentration n-type source/drain regions outside the channel region, and said second gate electrode is made of a lamination of said first metal layer and said second metal layer; and a third transistor structure having a third semiconductor layer formed on said substrate, a third gate insulating film and a third gate electrode, wherein a channel region of said third semiconductor layer under said third gate electrode is intentionally doped with p-type impurities and n-type impurities, said third semiconductor layer includes high impurity concentration p-type source/drain regions outside the channel region, and said third gate electrode is made of said second metal layer.