Patent ID: 8843799

Claim:
A parallel processing method of bit rate matching, comprising: receiving a system bit data stream, a check 1 data stream and a check 2 data stream, performing interleaving processing on N system bit data in the received system bit data stream, and caching the N system bit data in a storage used for storing the system bit data in parallel; respectively constituting corresponding data with data in the check 1 data stream and data in the check 2 data stream; wherein the corresponding data refers to: a first data to a last but one data in the check 1 data stream respectively corresponding with a second data to a last data in the check 2 data stream; a last data in the check 1 data stream corresponding with a NULL padded in the check 2 data stream, and a first data in the check 2 data stream corresponding with a NULL padded in the check 1 data stream; performing interleaving processing on the corresponding data and caching the corresponding data in a storage used for storing the check bit data in parallel with a parallelism degree of N, until all of the corresponding data are processed, wherein each corresponding data is regarded as one data for interleaving processing by a same interleaving address generation; reading valid data from the storage used for storing the system bit data and the storage used for storing the check bit data, and implementing the rate matching.