Patent ID: 8878298

Claim:
A field-effect transistor (FET) device comprising: a source region; a drain region; at least one channel interconnecting the source region and the drain region along a first plane of the device that is parallel to a length of the channel between the source and drain regions; and a gate that surrounds at least a portion of the channel, wherein the gate comprises a gate electrode that is configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate electrode, wherein the gate electrode comprises at least one metal layer, disposed on the channel, comprising the at least one band edge metal, and wherein the selective placement of the at least one band edge metal results in, when viewed in cross-section through the gate electrode and the channel along a second plane of the device that is perpendicular to the length of the channel, the at least one metal layer comprising the at least one band edge metal being either 1) present in the gate electrode adjacent to both sides of the channel but excluded from the gate electrode adjacent to a top of the channel and covered with a metal top electrode layer that is present in the gate electrode adjacent to both of the sides and to the top of the channel or 2) present in the gate electrode overlying a first metal layer and adjacent to a first side of the channel but excluded from the gate electrode adjacent to a second side of the channel that is opposite to the first side of the channel and covered with a metal top electrode layer that is present in the gate electrode adjacent to both of the sides and to the top of the channel, wherein the first plane of the device and the second plane of the device are perpendicular to one another.