Patent ID: 7682902

Claim:
A method of fabricating a flash structure comprising: providing a substrate with a pad; forming a first recessed trench in the substrate and the pad; forming a first gate dielectric layer on the surface of the first recessed trench; forming a spacer on a sidewall of the first recessed trench; forming a second recessed trench in a bottom of the first recessed trench by taking the pad and the spacer as a mask; forming an inter-gate dielectric layer on the surface of the spacer, the sidewall and the bottom of the second recessed trench; forming a first conductive layer on the inter-gate dielectric layer, wherein the first conductive layer fills the first and the second recessed trench; polishing the first conductive layer, and making the top surface of the first conductive layer aligned with the top surface of the pad; etching back the first conductive layer to form a recessed region; forming a first dielectric layer, wherein the first dielectric layer fills up the recessed region; polishing the first dielectric layer, and making the top surface of the first dielectric layer aligned with the top surface of the pad; forming a plurality of STI trenches in the substrate; forming a second dielectric layer, wherein the second dielectric layer covers the surface of the pad and the first dielectric layer, and fills up the STI trenches; polishing the second dielectric layer and making the top surface of the second dielectric layer aligned with the top surface of the pad; removing the first dielectric layer; etching back the first conductive layer; removing the pad; and forming a source/drain doping region in the substrate adjacent the spacer.