Patent ID: 7821296

Claim:
A circuit, comprising: a first buffer having a first input coupled to a first signal source and a first output coupled to a first load, the first buffer configured to provide an output signal substantially tracking an output signal of the first signal source, the first buffer comprising at least one first transistor comprising a first terminal, a second terminal, and a third terminal; a second buffer having a second input coupled to a second signal source and a second output coupled to a second load that is distinct from the first load, the second buffer configured to provide an output signal substantially tracking an output signal of the second signal source, the second buffer comprising at least one second transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first and second buffers are stacked buffers, and are configured such that a quiescent current that flows from the second terminal of the at least one first transistor to the third terminal of the at least one first transistor also flows from the second terminal of the at least one second transistor to the third terminal of the at least one second transistor; and an active current source connected between the first output and the second output as a biasing element that determines a value of the quiescent current, and wherein a current through the active current source is independent of an output voltage of the first buffer and an output voltage of the second buffer.