Patent ID: 7981792

Claim:
A method of manufacturing a semiconductor device, comprising: (a) forming a passivation layer directly on a surface of a substrate having an electrode, the passivation layer having an opening that exposes a part of the electrode; (b) forming a resin layer on the passivation layer; (c) forming a conductive layer which is electrically connected to the electrode and formed to extend over the resin layer; (d) forming an interconnect layer which includes a linear section and a land section connected with the linear section so that the conductive layer is disposed under at least the land section, the land section is disposed above the resin layer; (e) forming an underlayer by over-etching the conductive layer to be included inward a region of the land section so that the land section includes a first section which is in contact with the underlayer and a second section which is not in contact with the underlayer; (f) forming an insulating layer covering a part of the interconnect layer so that the insulating layer has an opening positioned on a part of the land section; (g) forming an external electrode in the opening so that the external electrode is electrically connected to the interconnect layer; and (h) mounting a semiconductor chip on the substrate, an integrated circuit being formed in the semiconductor chip.