Patent ID: 7633127

Claim:
A semiconductor chip, comprising: a substrate that includes a semiconductor layer overlying an insulator layer formed on a substrate substructure, said semiconductor layer having a first active region and an adjacent second active region; a gate dielectric layer overlying the first active region and a fully silicided first gate electrode comprised of a first metal formed thereon; a first pair of spacers formed adjacent to said gate dielectric layer and the overlying first gate electrode such that the first gate electrode is recessed below the top of the first pair of spacers; a first raised source region between one of the first pair of spacers and an adjacent isolation region and a first raised drain region between the other of the first pair of spacers and an adjacent isolation region wherein the first raised source/drain regions are comprised of the first metal and are fully silicided; a gate dielectric layer overlying the second active region and a fully silicided second gate electrode comprised of a second metal formed thereon; a second pair of spacers formed adjacent to the gate dielectric layer and the overlying second gate electrode such that the second gate electrode is recessed below the top of the second pair of spacers; and a second raised source region between one of the second pair of spacers and an adjacent isolation region and a second raised drain region between the other of the second pair of spacers and an adjacent isolation region wherein the second raised source/drain regions are comprised of the second metal and are fully silicided and wherein the second metal includes a different composition than the first metal.