Patent ID: 8530121

Claim:
A method comprising: receiving an integrated circuit (IC) layout design including a target pattern on a grid; receiving a multiple-grid structure, the multiple-grid structure including first and second exposure grid segments offset one from the other by an offset amount in a first direction; and performing a multiple-grid exposure to expose the target pattern onto a substrate and thereby form a circuit feature pattern on the substrate, wherein performing the multiple-grid exposure includes: scanning the first exposure grid segment across a surface of the substrate in a second direction and exposing the target pattern on the substrate during the scanning of the first exposure grid segment, the first direction and the second direction being orthogonal one to the other; and scanning the second exposure grid segment across the surface of the substrate in the second direction and exposing the target pattern on the substrate during the scanning of the second exposure grid segment, wherein exposing the target pattern on the substrate during the scanning of the second exposure grid segment is performed such that a sub-pixel shift of the exposed target pattern occurs in the first direction, wherein exposing the target pattern on the substrate during the scanning of the second exposure grid segment includes delaying the exposure for a delta time (Δt) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.