Patent ID: 8135991

Claim:
An apparatus, said apparatus comprising: a semiconductor device including a central processing unit (CPU) and a read control circuit (RCC); a data-rewritable nonvolatile memory communicatively coupled to the CPU that includes a plurality of data blocks with each data block including a plurality of data pages, wherein, at least two boot program instructions are stored in a predetermined number of data blocks in parallel in the data-rewritable nonvolatile memory, the predetermined number being less than the total number of data blocks, block state information indicating that a data block is faulty or not faulty is stored in a leading data page of each of the data blocks storing boot program instructions, the CPU is configured, in part, to specify to the RCC a read position for reading out the boot program instruction from a data block in the data-rewritable nonvolatile memory at a starting time; and the RCC is configured to (a) determine whether a first respective data block is faulty or not according to the block state information, (b) output first data to the CPU when the first respective data block is determined as not faulty, and (c) read, when the first respective data block is determined as faulty, second data from a second respective data block and output the second data to the CPU when the second respective data block is determined as not faulty, and the RCC prevents the CPU from accessing the data-rewritable nonvolatile memory while the RCC determines which of the respective data blocks to output to the CPU.