Patent ID: 8466569

Claim:
An integrated circuit, comprising: a photolithographic topographical alignment mark formed in a substrate; a low reflectivity layer formed on a top surface of said topographical alignment mark; said low reflectivity layer being a layer stack that includes a layer of titanium aluminum nitride (TiAlN), a layer of titanium aluminum oxynitride (TiAlON), a first sub-layer of iridium containing material, a layer of lead zirconium titanate (PZT), a second layer of iridium containing material, and a layer of TiAlN; a reflective layer that includes titanium aluminum (TiAl) formed on a top surface of said low reflectivity layer, in which: a top surface of said reflective layer duplicates a height difference across said topographical alignment mark; and a reflectivity of said reflective layer is greater than 25 percent at a wavelength used for positional measurement; and a photoresist layer formed in contact with a top surface of said reflective layer.