Patent ID: 6990669

Claim:
A computer-readable medium having computer-executable instructions for performing real-time execution-thread switching comprising: issuing a first non-maskable interrupt from a counter to an interrupt controller when the counter turns over; in response to receiving the first non-maskable interrupt, issuing a second non-maskable interrupt from the interrupt controller to a central processing unit; in an interrupt service routine that services the second non-maskable interrupt, saving a first execution thread's current state information, wherein the first execution thread is an application-level-code execution thread that does not execute in a most-privileged CPU mode, and wherein the first execution thread's current state information includes stack data, processor data, and floating point-unit data; setting the counter to specify when the counter will turn over again; restoring previously stored state information pertaining to a second execution thread, wherein the second execution thread is an application-level-code execution thread that does not execute in a most-privileged CPU mode, and wherein the previously stored state information pertaining to the second execution thread includes stack data, processor data, and floating-point-unit data; and after execution of the interrupt service routine has finished, executing the second execution thread such that the interrupt service routine that services the second non-maskable interrupt minimizes overhead associated with switching thread execution from the first thread to the second thread.