Patent ID: 8225005

Claim:
A computer-implemented method for creating a high speed peripheral component interconnect input/output virtualization configuration, the computer-implemented method comprising: creating, by a trusted entity being executed by a processor, a set of virtual function path authorization tables in a peripheral component interconnect adapter, wherein each entry permits a virtual function to access a set of address ranges in one of a plurality of logical partitions; receiving a request including a virtual function, from a requester, to provide requested data from a source logical partition of the plurality of logical partitions to a target set of logical partitions of the plurality of logical partitions; identifying a source address of the requested data that is located in the source logical partition of the plurality of logical partitions and a target address in each one of the target set of logical partitions of the plurality of logical partitions to which the requested data will attempt to be written; creating a virtual function work queue entry for the source logical partition of the plurality of logical partitions containing the source address of the requested data in the source logical partition of the plurality of logical partitions and the target address in each one of the target set of logical partitions of the plurality of logical partitions; determining, in the set of virtual function path authorization tables, whether the virtual function is authorized; responsive to a determination that the virtual function is authorized, writing the requested data from the source address of the source logical partition of the plurality of logical partitions through a firewall in the peripheral component interconnect adapter into the target address of each one of the target set of logical partitions of the plurality of logical partitions; responsive to a determination that the virtual function is not authorized, preventing, by the firewall, writing the requested data from the source address of the source logical partition of the plurality of logical partitions into the target address of each one of the target set of logical partitions of the plurality of logical partitions; and responsive to writing the requested data, issuing a notice of completion to the requester.