Patent ID: 8606976

Claim:
A data stream flow-controller for controlling a transfer of data between a data processing device and a network on chip (NoC) supporting a plurality of interconnection paths to destinations at other data processing devices, comprising: interfaces configured to interface the flow-controller on the network on chip side and on the data processing device side, a configurable memory configured to buffer data in a plurality of first-in-first-out (FIFO) queues including a plurality of individual receive data queues and a plurality of individual transmit data queues; an additional memory configurable to provide for a software queue extension beyond the configurable memory when one or more of the FIFO queues is full and backlogged buffer data is rep sent; a plurality of queue registers each associated with a corresponding one of the plurality of FIFO queues and configured to store identification data for the interconnection paths and addressing data for identifying where backlogged buffer data for the FIFO queues is being stored in said additional memory.