Patent ID: 7713804

Claim:
A manufacturing process, comprising: in a semiconductor substrate, forming an active area in a semiconductor portion of a well region doped with a predetermined type of conductivity enhancing impurities, said active area defined by insulating material formed in said semiconductor portion, said active area having a first region where a junction field-effect transistor is to be formed and a second region in electrical contact with said first region where a surface contact to said well region is to be formed; performing an ion implantation to form a channel region in said first region of said active area; forming a dielectric layer on top of the channel region and at least a portion of the insulating material; masking and etching the dielectric layer to open source, drain, and gate openings; masking and forming a gate region through said gate opening; masking and forming source and drain regions through said source and drain openings; forming metal silicide ohmic contacts in said source, drain, and gate openings; depositing a metal layer to fill said source, drain, and gate openings; and polishing said metal layer back to be approximately flush with a top of said dielectric layer.