Patent ID: 8178287

Claim:
A method of forming a integrated circuit pattern, comprising: forming an under layer on a substrate wherein the under layer includes a first material capable of diffusing to a top surface of the under layer and providing etch resistance tuning for the under layer, and wherein the under layer includes a second material capable of diffusing to the top surface of the under layer and controlling top surface properties of the under layer; performing a first diffusion process, aggregation process or separation process to redistribute the first material of the under layer, resulting in a top portion and main portion of the under layer, the top portion and the main portion having different etching resistance; performing a second diffusion process, aggregation process or separation process to redistribute the second material of the under layer to the top surface of the under layer, thereby adjusting surface properties of the top surface of the under layer; forming a patterned photoresist layer on the under layer; etching the top portion of the under layer through the patterned photoresist layer; stopping the etching after patterning the top portion; thereafter removing the patterned photoresist layer from the substrate; and after removing the photoresist, etching the main portion of the under layer using the etched top portion as a masking element.