Patent ID: 7682911

Claim:
A method for fabricating a semiconductor device, the method comprising: forming an isolation layer in a substrate having first, second and third regions, to define active regions in the first through third regions, respectively; selectively etching a portion of the isolation layer in the first region where a gate electrode passes, to form a fin active region forming a gate insulation layer over the fin active region of the first region and the active regions of the second and third regions, thereby forming a first resultant structure; and forming first, second and third gate electrodes over the substrate of the first through third regions, wherein work functions of the first through third gate electrodes are different from one another, and the first gate electrode has the work function between those of the second and third gate electrodes, and wherein the forming of the first through third gate electrodes, comprises: forming a SiGe layer over the first resultant structure where the gate insulation layer is formed; removing the SiGe layer of the second and third regions through masking and etching processes, thereby forming a second resultant structure; forming an undoped polysilicon layer along a surface profile of the second resultant structure of the first through third regions; performing a planarization until the surface of the SiGe layer of the first region is exposed; and selectively implanting n-type impurities into the second region, and p-type impurities into the third region.