Patent ID: 7738617

Claim:
An apparatus for recovering a clock signal, the apparatus comprising: a phase detector configured to receive an input data signal and to receive a recovered clock signal, the phase detector further configured to generate a signal with an indication of a phase difference between the input data signal and the recovered clock signal; and a feedback circuit operatively coupled to the phase detector, the feedback circuit configured to receive the generated signal from the phase detector and to receive a reference signal, the feedback circuit configured to generate the recovered clock signal, wherein the feedback circuit takes into consideration whether the recovered clock signal is at least momentarily phase locked to the input data signal in selecting a frequency range, wherein the feedback circuit further comprises: a phase tracking path; and a frequency tracking path with an accumulator, the accumulator having at least one range limit that is dynamically selectable for dynamic selection of the limit of the frequency range of the feedback circuit, wherein the accumulator for the frequency tracking path is configured to have at least a first predetermined value range for a full range, a second predetermined value range for a first subrange, and a third predetermined value range for a second subrange, the second predetermined value range having a range different than the third predetermined value range, the second predetermined value range and the third predetermined value range having ranges smaller than the first predetermined value range, wherein the accumulator is initially configured to select the second predetermined value range, wherein the accumulator is configured to select the third predetermined value range after a predetermined time has elapsed after which phase lock has been determined to have not occurred, wherein the accumulator is further configured to select the first predetermined value range after phase lock has occurred.