Patent ID: 7435638

Claim:
A method of forming one or more MOS transistors comprising: forming a layer of gate dielectric material over a semiconductor substrate; forming a first layer of gate electrode material over the layer of gate dielectric material; performing a first implantation of one or more dopants of a first electrical conductivity type through the first layer of gate electrode material and the layer of gate dielectric material, and into a first region of the substrate to establish a first well having the first electrical conductivity type; performing a second implantation of one or more dopants of the first electrical conductivity type into a first region of the first layer of gate electrode material, where the first region of the first layer of gate electrode material is located above the first region of the substrate; performing a third implantation of one or more dopants of a second electrical conductivity type through the first layer of gate electrode material and the layer of gate dielectric material, and into a second region of the substrate to establish a second well having the second electrical conductivity type; performing a fourth implantation of one or more dopants of the second electrical conductivity type into a second region of the first layer of gate electrode material, where the second region of the first layer of gate electrode material is located above the second region of the substrate; forming a second layer of gate electrode material over the first layer of gate electrode material; patterning the second layer of gate electrode material, the first layer of gate electrode material and the layer of gate dielectric material to form a gate structure over at least one of the first region of the substrate and the second region of the substrate; and forming source and drain regions in at least one of the first region of the substrate and the second region of the substrate.