Patent ID: 6949424

Claim:
A method of forming a vertical PNP bipolar transistor in a BiCMOS process, where the transistor is formed upon a wafer having a silicon substrate, the method comprising: forming a double diffused DWELL in a DNWELL formed within a P-epi layer formed across the substrate; forming a SPWELL in the DNWELL region adjacent the DWELL region; forming a layer of oxide material over the wafer, at least portions of the oxide layer forming gate oxide regions for MOS transistor devices on the wafer; patterning the layer of oxide material to form an opening overlying and exposing silicon in a portion of the double diffused DWELL; forming a layer of poly-silicon across the wafer; patterning the layer of poly-silicon forming gate electrodes over the gate oxide regions for the MOS transistor devices and forming an emitter contact that fills the opening overlying the double diffused DWELL for the vertical PNP transistor; and performing PSD/NSD implants to establish a collector contact and a base contact, respectively, for the vertical PNP transistor.