Patent ID: 8836369

Claim:
A latch circuit comprising: a first logic circuit configured to receive an input signal from a first input terminal and output a first output signal; a second logic circuit configured to receive an inverted input signal, which is obtained by logically inverting the input signal, from a second input terminal and output a second output signal; a third logic circuit configured to input in the first output signal and a fourth output signal and output a third output signal; and a fourth logic circuit configured to input in the second output signal and the third output signal and output the fourth output signal, wherein the latch circuit switches a differential operation performed by a differential operation circuit including the first logic circuit, the second logic circuit, the third logic circuit, and the fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal, and according to logic levels of an inputted clock signal and an inverted clock signal which is obtained by logically inverting the clock signal, the latch circuit performs an operation to output the input signal and the inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation.