Patent ID: 8716119

Claim:
A method of forming a plurality of charge storage transistor gates and field effect transistor (FET) gates, comprising: forming a stack over a semiconductor substrate; the stack comprising a gate dielectric material, a gate material over the gate dielectric material, an electrically insulative material over the gate material, a sacrificial material over the electrically insulative material, and a protective material over the sacrificial material; patterning the stack into a plurality of pillars; some of the pillars being at charge storage transistor gate locations, and some of the pillars being at FET gate locations; forming electrically insulative spacers along sidewalls of the pillars; after forming the electrically insulative spacers, removing the protective material from over the sacrificial material; removing the sacrificial material from all of the pillars to form cavities at the tops of all of the pillars; individual cavities being bounded by the electrically insulative material along the bottom, and by the spacers along the sides; after removing the sacrificial material, removing at least some of the electrically insulative material of the pillars at the FET locations to extend the cavities through the electrically insulative material and expose the gate material, while not etching through the electrically insulative material of the pillars at the charge storage transistor locations; forming a first electrically conductive material conformally within all of the cavities to partially fill the cavities and thereby narrow the cavities, the first electrically conductive material physically contacting the gate material within the extended cavities of the pillars at the FET gate locations, and being separated from the gate material of the pillars at the charge storage transistor gate locations by the electrically insulative material; and forming second electrically conductive material within the narrowed cavities to entirely fill the cavities.