Patent ID: 8054934

Claim:
A shift register, comprising a plurality of shift register units, each shift register unit comprising: a first switch circuit controlled by a first input terminal of the shift register unit and a second common node of the shift register unit and configured for providing a high level signal to a first common node of the shift register unit; a second switch circuit controlled by the first input terminal and a second input terminal of the shift register unit and configured for providing a high level signal to the first common node; a third switch circuit controlled by the first input terminal and configured for providing a low level signal to the first common node; a fourth switch circuit controlled by the second input terminal and the second common node and configured for providing a low level signal to the first common node; a fifth switch circuit controlled by the first common node and the second common node and configured for providing a clock signal to an output terminal of the shift register unit; a sixth switch circuit controlled by the first common node and configured for providing a low level signal to the output terminal; a first inverter connected between the first common node and the second common node; and a second inverter connected between the output terminal and a reverse output terminal of the shift register unit.