Patent ID: 7843012

Claim:
A CMOS transistor, comprising: a substrate comprising a first conductive type MOS device region and a second conductive type MOS device region, the substrate further comprising a second conductive type well disposed in the first conductive type MOS device region, and a first conductive type well disposed in the second conductive type MOS device region; a plurality isolation structures disposed on the surface of the substrate; a gate structure disposed in the first conductive type MOS device region, and spacers disposed alongside the gate structure; two source/drain doped regions disposed in the second conductive type well by both sides of the spacers of the gate structure in the first conductive type MOS device region; two lightly doped drains disposed in the second conductive type well by both sides of the gate structure in the first conductive type MOS device region, the two lightly doped drains being corresponding to the spacers; and two second conductive type deep halo doped regions disposed in the second conductive type well by both sides of the gate structure in the first conductive type MOS device region, wherein each of the deep halo doped regions is disposed corresponding to and directly under one of the source/drain regions and one of the lightly doped drains, wherein no deep halo regions are disposed in the first conductive type well of the second conductive type MOS device region.