Patent ID: 6867630

Claim:
A clock processing logic for determining an edge of a clock signal indicated in a sample vector by a bit location corresponding to a transition from one or more bits of a first value on one side of said bit location to one or more bits of a second value on another side of said bit location, wherein said bit location varies from cycle to cycle according to reference voltage and temperature variations affecting said clock signal, comprising: edge detection logic configured to compare adjacent pairs of bits of said sample vector starting from one end of said sample vector to another end of said sample vector until a bit location corresponding to a transition from one or more bits of a first value on one side of said bit location to one or more bits of a second value on another side of said bit location is detected; and sensitivity adjustment logic configured to adjust said bit location according to information of at least one other bit location corresponding to a previous cycle of said clock signal that was previously detected by said edge detection logic.