Patent ID: 7814381

Claim:
A semiconductor memory device comprising: a memory array; and a first input node, a second input node and a third input node each electrically connected to the memory array, wherein said first input node is configured to receive a first input signal, a read or write operation of the memory array in a normal mode is performed in accordance with the first input signal, wherein said second input node is configured to receive a second input signal, a read or write operation of the memory array in a test mode is performed in accordance with the second input signal, wherein a test of a plurality of output data from the memory array is conducted in the test mode to determine whether an access time is within a fixed period and results of the test are output at an output node, and wherein said device is so configured that said test is conducted in the test mode based upon a third input signal input to said third input node, said third input signal is unrelated to the first input signal and the second input signal.