Patent ID: 7157927

Claim:
A test pattern used for testing a resistance of a subject pattern of a semiconductor substrate, comprising: a lower wiring pattern as the subject pattern, formed on a lower surface of the substrate, said lower wiring pattern including a longitudinally extending center portion terminating at opposite first and second ends, first and second terminal portions on said lower surface, laterally spaced from each other adjacent said first end of said center portion, both of said first and second terminal portions being spaced from said center portion, and third and fourth terminal portions on said lower surface laterally spaced from each other adjacent said second end of said center portion, both of said third and fourth terminal portions being spaced from said center portion, a first end portion branching from said first end of said center portion in different first and second directions along said lower surface respectively to connect said first and second terminal portions to said first end of said center portion, and a second end portion branching from said second end of said center portion in different third and fourth directions along said lower surface respectively to connect said third and fourth terminal portions to said second end of said center portion; first, second, third and fourth upper patterns formed on an upper surface of the substrate; first, second, third and fourth electrodes formed respectively on the first, second, third and fourth upper patterns, the first and second electrodes for connection to first and second test probes; and first and second via-holes formed through the substrate respectively to connect the first and second upper patterns electrically respectively to said first and second terminal portions; and third and fourth via-holes formed through the substrate respectively to connect the third and fourth upper patterns electrically respectively to said third and fourth terminal portions.