Patent ID: 7876893

Claim:
A logic circuit for calculating an encrypted result operand from a first encrypted input operand and a second encrypted input operand according to a combination rule, comprising: a first input for receiving the first encrypted input operand; a second input for receiving the second encrypted input operand; an output for outputting the encrypted result operand; wherein each operand comprises a first logic state or a second logic state; and at least one first logic stage and at least one second logic stage, wherein the at least one first logic stage is connected between the inputs and an intermediate node, and the at least one second logic stage is connected between the intermediate node and the output, and wherein the logic stages are arranged such that a logic path from one of the inputs of the logic circuit to the output of the logic circuit comprises an even number of logic stages, wherein the logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to impress the same at the output, and wherein the logic circuit is formed so that the logic state of the encrypted result operand is maintained or changed exactly once, independently of an order of arrival of the encrypted input operands, depending on the combination rule.