Patent ID: 7096376

Claim:
A semiconductor integrated circuit device in which variation in a minimum propagation time of a transmission signal from a source node to a destination node is sufficiently large, relative to a clock period at an intended clock frequency of the device, to cause variation in a clock cycle in which the transmission signal reaches the destination node, the device comprising: a plurality of clocked elements connected in series between the source and destination nodes for causing a shift signal, representing said transmission signal present at said source node in a first clock cycle, to be shifted from said source node to said destination node through said series of clocked elements one clocked element per predetermined number of clock cycles, said series of clocked elements being connected and arranged such that variation in a propagation time of said shift signal from each clocked element to the next clocked element is sufficiently small, relative to said clock period, that a clock cycle in which the shift signal reaches the next clocked element does not vary, whereby said shift signal always reaches said destination node a fixed number of clock cycles after said first clock cycle.