Patent ID: 7733136

Claim:
A frequency synthesizer, comprising: a fractional-N synthesizer configured to provide, in a locked condition, an output signal with an output frequency based on an input signal with a reference frequency, the fractional-N synthesizer including a first charge pump outputting a current to be calibrated; a lock detector coupled to the fractional-N synthesizer to detect the locked condition, the lock detector being configured to send a first signal indicating the detection; a calibration component coupled to the lock detector and the fractional-N synthesizer, the calibration component being configured to provide a second signal to calibrate the current after receiving the first signal, based on a voltage sampled from the fractional-N synthesizer; and a first current source array coupled to the calibration component and the fractional-N synthesizer, the first current source array being configured to calibrate the current based on the second signal; wherein the calibration component includes: a timing generator configured to receive the first signal indicating the detection of the locked condition and to provide first and second switch signals; a second charge pump coupled to the timing generator and including first and second current sources, the first current source providing a first current in response to the first switch signal, the second current source providing a second current in response to the second switch signal, the second charge pump being substantially the same as the first charge pump; a second current source array coupled to the second charge pump and including a plurality of current sources coupled in parallel, the second current source array being substantially the same as the first current source array; an integrator circuit coupled to the second charge pump and the second current source array, the integrator circuit being configured to provide a voltage based on the voltage sampled from the fractional-N synthesizer and a total current provided by the second charge pump and the second current source array; a comparator coupled to the integrator circuit, the comparator being configured to determine whether further calibration is needed based on the voltage provided by the integrator circuit; a counter coupled to the comparator, the counter being configured to increase a count value by one if the comparator determines further calibration is needed, and to output a count signal corresponding to the count value; and an adder coupled to the counter, the adder being configured to add the count signal to an initial signal to provide a calibration signal to the second current source array, and to output the calibration signal as the second signal to the first current source array if the comparator determines no further calibration is needed.