Patent ID: 7436698

Claim:
An MRAM array circuit, comprising: a data line, a word line, and a bit line across the word line; a switch comprising a control gate coupled to the data line, a first terminal coupled to the bit line, and a second terminal, wherein the switch is turned on via a selection signal from the data line; a plurality of MTJ memory devices each having first electrodes coupled to the second terminal and second electrodes coupled to the word line, and each memory device comprising a free ferromagnetic layer, a pinned ferromagnetic layer, and an insulating tunneling barrier located in between; a plurality of program lines respectively corresponding to the MTJ memory devices, wherein a combination of a first writing magnetic field via the word line and a second writing magnetic field via one of the program lines exceeds a threshold magnetic field and switches the resistance of a corresponding MTJ memory device during a data writing procedure; and a sensing circuit for determining data stored in a selected MTJ device by comparing a first signal from the selected MTJ memory device with a wiggle magnetic field applied via a program line corresponding to the selected MTJ device with a second signal from the selected MTJ device without the wiggle magnetic field applied, the wiggle magnetic field inducing a tilt of a magnetic moment of the free ferromagnetic layer of the selected MTJ device by an angle not exceeding 90 degree during a data reading procedure.