Patent ID: 8274830

Claim:
A non-volatile semiconductor memory circuit, comprising: a non-volatile memory cell having an erase state in which a threshold voltage is low and a write state in which the threshold voltage is high to thereby store data; a constant current circuit connected in series with the non-volatile memory cell; and a connection point between the non-volatile memory cell and the constant current circuit being set to be an output; wherein, in a reading mode or a retention mode, in which a voltage is applied to the non-volatile memory cell, the following relationship is satisfied: I WRITE <I CONST <I ERASE , where a saturation current flowing through the non-volatile memory cell in the erase state is represented by I ERASE , a saturation current flowing through the non-volatile memory cell in the write state is represented by I WRITE , and a constant current provided from the constant current circuit is represented by I CONST .