Patent ID: 8667232

Claim:
A flash memory, comprising: a memory core comprising an array of memory cells; a command user interface; and a controller having a code storage device, the controller coupled to and interposed between the memory core and the command user interface; wherein the code storage device is configured to run algorithms that cause the controller to perform operations on the memory cells; wherein the command user interface is configured to decode signals, generate control signals based on the decoded signals, and send the control signals to the controller; wherein the code storage device contains an instruction that causes a value contained in the instruction to be stored in a register of a register bank of the flash memory having an address contained in the instruction; and wherein the instruction includes a flag, wherein when the flag has a first value, only a first portion of the value contained in the instruction is stored in the register, and wherein when the flag has a second value, only a second portion of the value contained in the instruction is stored in the register.