Patent ID: 8203217

Claim:
A stacked wafer level package, comprising: a base substrate having a chip region and a peripheral region disposed at the periphery of the chip region; a first semiconductor chip disposed over the chip region and having a first bonding pad; a first insulation layer pattern for covering the chip region and the peripheral region and exposing the first bonding pad; a first redistribution pattern connected with the first bonding pad and extended from the first bonding pad to the peripheral region; a second insulation layer disposed over the first insulation layer pattern and opening some portion of the first redistribution pattern disposed in the peripheral region; a second semiconductor chip disposed in the chip region of the second insulation layer pattern and having a second bonding pad; a third insulation layer pattern for covering the second semiconductor chip and the peripheral region and exposing the second bonding pad, the third insulation layer pattern having a through hole exposing some portion of the first redistribution pattern disposed in the peripheral region; a second redistribution pattern connected with the second bonding pad and having a connection pattern electrically connected to the first redistribution pattern through the through hole, wherein the second redistribution pattern and the connection pattern are formed integrally with each other; and a fourth insulation layer pattern covering the second redistribution pattern, the fourth insulation layer pattern having an opening for exposing some portion of the second redistribution pattern.