Patent ID: 7656322

Claim:
A semiconductor memory device which stores predetermined code words each composed of information bits and parity check bits, comprising: a memory cell array having a plurality of word lines and a plurality of bit lines and having a plurality of memory cells respectively formed at places at which said word lines and said bit lines cross over, said memory cells being arranged in a matrix; a row decoder to select one of said word lines based on a row address signal; a column decoder to select some of said bit lines based on a column address signal; an error correction circuit to perform error correction on a code word read through the bit lines selected by said column decoder from ones of said memory cells located at places at which the word line selected by said row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating said error position, and to correct the information bit in said detected error position to generate error corrected data; and an output circuit to receive said error detection data and said error corrected data from said error correction circuit, wherein said output circuit relays said error corrected data to outside when a normal operation mode has been designated and relays said error detection data to outside when a test operation mode has been designated.