Patent ID: 8209473

Claim:
A flash storage device, coupled to a host, comprising: at least one flash memory, divided into a plurality of management units, wherein each of the management units comprises a plurality of blocks for data storage, and each of the management units has a link table for storing a corresponding relationship between logical addresses and physical addresses of the blocks thereof; a random access memory, divided into a plurality of slots, wherein each of the slots stores one of the link tables corresponding to the management units; and a controller, recording access frequencies by which the host accesses data of the management units, receiving an access logical address from the host, retrieving a target link table storing the access logical address from the link tables stored in the random access memory, determining an access physical address corresponding to the access logical address according to the target link table, and accessing data from the flash memory according to the access physical address; wherein when the controller cannot find the target link table storing the access logical address from the link tables stored in the random access memory, the controller selects the link table corresponding to a lowest access frequency as a replaced link table, clears the replaced link table from the random access memory, and then loads the target link table to the random access memory.