Patent ID: 7254806

Claim:
A computer, comprising; a binary translator programmed to translate at least a segment of a first binary representation of a program from a first binary representation in a first instruction set to a second binary representation in a second instruction set, a sequence of side-effects in the second binary representation differing from a sequence of side-effects in the translated segment of the first binary representation, the second binary representation distinguishing individual memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s); instruction execution circuitry designed, while executing the second binary representation, to identify an individual memory-reference instruction, or an individual memory reference of an instruction, a side-effect arising from the memory reference having been reordered by the translator, the memory reference having been believed at translation time to be directed to well-behaved memory but that at execution time is found to reference a device with a valid memory address that cannot be guaranteed to be well-behaved, based at least in part on an annotation encoded in a segment descriptor, and based in the distinguishing, to identify whether the difference in sequence of side-effects may have a material effect on the execution of the program; and circuitry and/or software designed to establish program state to a state equivalent to a state that would have occurred in the execution of the first binary representation, and to resume execution of the translated segment of the program in the first instruction set.