Patent ID: 7839181

Claim:
A buffer circuit that suppresses glitches on an input clock signal, the buffer circuit comprising: a latch having a set terminal, a reset terminal, and an output terminal; a delay element coupled between the output terminal of the latch, the delay element providing a delay signal that is a version of the output clock signal delayed by a delay period; a frequency sensor having an input terminal for receiving the input clock signal and an output terminal coupled to the delay element, wherein the frequency sensor measures a frequency of the input clock signal and varies the delay period in response to the frequency of the input clock signal; a first logic gate having a first input terminal coupled to receive an inversion of the delay signal from the delay element, a second input terminal coupled to receive the input clock signal, and an output terminal coupled to the set terminal of the latch; and a second logic gate having a first input terminal coupled to receive the delay signal, a second input terminal coupled to receive an inversion of the input clock signal, and an output terminal coupled to the reset terminal of the latch.