Patent ID: 8036052

Claim:
A semiconductor memory device, comprising: a memory cell array outputting at least one of a first and a second data group at a first data rate; an output circuit, wherein the output circuit in a normal mode of operation serially outputs at least one of the first and the second data group at the first data rate to an external terminal, and in at least one test mode of operation, outputs the first data group or the second data group at a second data rate in response to at least one control signal without switching the test mode of operation; and a mode set circuit that outputs, in response to a plurality of input signals, at least one test mode signal for determining a test mode of operation of the output circuit, wherein the output circuit includes, a selecting section configured to output at least one selection signal that selects the first data group or the second data group in response to the control signal, the at least one test mode signal, and an internal read signal, wherein the selecting section includes, a first sub-selecting section configured to output a first selection signal in response to a first logic operation of an inverted signal of the control signal, the at least one test mode signal, and the internal read signal, and a second sub-selecting section configured to output a second selection signal in response to a second logic operation of the control signal, the at least one test mode signal, and the internal read signal, and a buffering section configured to output the first data group in response to the first selection signal and output the second data signal in response to the second selection signal.