Patent ID: 7417456

Claim:
A dedicated logic cell in a sequential logic function (LS) structure, comprising: a first multiplexer having one or more inputs, one or more control signals and an output, the one or more control signals being driven by dedicated lines, the one or more inputs in the first multiplexer including a first input coupled to a data input, a second input coupled to a load data, a third input coupled to a power signal and a fourth input coupled to ground; a second multiplexer having a first input coupled to the output of the first multiplexer, a second input, a control signal and an output, the control signal of the second multiplexer being driven by a dedicated line; and a configurable register having an input coupled to the output of the second multiplexer and an output, the output of the configurable register coupled to the second input of the second multiplexer; where in the combination of the first multiplexer, the second multiplexer and the configurable register forms a sequential logic function circuit.