Patent ID: 8307190

Claim:
A memory control device connected to a master and to a first memory device and a second memory device, and which receives a memory access request from the master and accesses the first memory device and the second memory device, said memory control device comprising: a command controller connected to the first memory device and the second memory device via a first command bus, the first memory device being connected through a first select signal line, and the second memory device being connected through a second select signal line, wherein said command controller is configured to switch, according to a logical address output by the master, between a first operation and a second operation, the first operation accesses the first memory device and the second memory device by simultaneously outputting a first select signal and a second select signal to the first select signal line and the second select signal line, respectively, and outputting a first physical address to the first command bus, the second operation accesses the first memory device and the second memory device by outputting the second select signal to the second select signal line and outputting a third physical address, different from a second physical address, to the first command bus, after outputting the first select signal to the first select signal line and outputting the second physical address to the first command bus, the memory control device is connected to m memory devices including the first memory device and the second memory device, each of the m memory units has a minimum access unit of N bytes, a logical address space has logical addresses which are consecutive along unit areas that are repeatedly arranged, and in each of the unit areas, m (N×integer)-byte areas each corresponding to one of the m memory devices are sequentially arranged.