Patent ID: 7814386

Claim:
A test system in an integrated circuit, the test system comprising: at least one boundary scan cell, the at least one boundary scan cell comprising: a first storage element; a second storage element connected in series with the first storage element; and test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to a test value signal (TVALUE), the test logic further configured to provide the output of the first storage element to the input of the second storage element unchanged during a first operating state and, depending at least in part on the test completion signal, to provide an inverted version of the output of the first storage element to the input of the second storage element during a second operating state; and a bi-directional element connected to receive the output of the second storage element, the bi-directional element feeding the output of the second storage element to an input of the first storage element.