Patent ID: 8468286

Claim:
A variable-frequency bus adapting method, comprising: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication, wherein blocking the current bus transfer comprises: detecting a bus control signal between the bus side and a peripheral component side, as for a read address bus, setting a detected bus control signal of the bus side representing that a slave device is configured for receiving read address and control information to be a preset low level, and setting a detected bus control signal of the peripheral component side representing a read address and control information valid flag to be a preset low level, as for a read data bus, after the current bus transfer completes the last read data, setting a detected bus control signal of the peripheral component side representing that a master device is configured for receiving read data to be a preset low level, and setting a detected bus control signal of the bus side representing that read data is valid to be a preset low level, as for a write address bus, setting a detected bus control signal of the bus side representing that a slave device is configured for receiving write address and control information to be a preset low level, and setting a detected bus control signal of the peripheral component side representing a write address and control information valid flag to be a preset low level, as for a write data bus, after the current bus transfer completes the last write data, setting a detected bus control signal of the bus side representing that a slave device is configured for receiving write data to be a preset low level, and setting a detected bus control signal of the peripheral component side representing that write data is valid to be a preset low level, and as for a write response bus, setting a detected bus control signal of the peripheral component side representing that a master device is configured for receiving feedback information to be a preset low level, and setting a detected bus control signal of the bus side representing completion of a write operation fed back by a slave device to be a preset low level; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, wherein the DFS response signal is adapted to enable the bus side to perform a DFS operation.