Patent ID: 7545693

Claim:
A semiconductor memory device comprising: a memory cell array with electrically rewritable memory cells arranged therein, the memory cells being defined as information cells and reference cells in which a data level and a reference level are set, respectively; and a sense amplifier configured to sense data stored in the memory cell array, wherein the sense amplifier comprises: a latch-type of differential amplifier configured to detect a current difference between a selected information cell and a selected reference cell in the memory cell array; a pair of transistors attached to the differential amplifier, the pair of transistors being on-driven to keep the differential amplifier inactive in a stationary state and off-driven to make the differential amplifier active at a sensing time, whereby the current difference is amplified as a drain voltage difference of the pair of transistors; and a pair of capacitors coupled to the pair of transistors to hold voltages corresponding to the respective currents of two current paths of the differential amplifier prior to inputting the current difference, and apply a certain offset voltage to the pair of transistors at the sensing time.