Patent ID: 8431982

Claim:
A semiconductor device comprising: a discharge active portion and a plurality of electrode active portions, each of the discharge active portions and electrode active portions being defined by a device isolation pattern on a semiconductor substrate that is doped with a first-type dopant, the electrode active portions being electrically connected to each other; a plurality of capping electrodes disposed respectively on the electrode active portions; a capacitor-dielectric layer disposed between each of the capping electrodes and each of the electrode active portions; a counter doped region disposed in the discharge active portion and doped with a second-type dopant; a lower interlayer dielectric disposed on the surface of the semiconductor substrate; a plurality of electrode contact plugs respectively contacting the capping electrodes; a discharge contact plug contacting the counter doped region; and a lower interconnection disposed on the lower interlayer dielectric and contacting top surfaces of the electrode contact plugs and a top surface of the discharge contact plug.