Patent ID: 7595532

Claim:
A semiconductor memory device comprising: a semiconductor substrate including an insulating layer; a charge storage region of a first conductivity type on the insulating layer; an insulating film on the insulating layer and surrounding the charge storage region while exposing at least part of an upper surface of the charge storage region; a body region of the first conductivity type contacting the at least part of the upper surface of the charge storage region; a gate stack including a gate electrode and a gate insulating film on the body region; and a source region and a drain region of a second conductivity type on opposite sides of the body region, wherein the charge storage region extends further towards the semiconductor substrate than the source region and/or the drain region; wherein the body region, the source region and the drain region are formed in a single semiconductor layer and the single semiconductor layer is on the charge storage region and extends over the insulating film so that the source region and the drain region are disposed over the insulating film.