Patent ID: 7737017

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a trench by selectively etching an isolation region of a semiconductor substrate to define an active region; forming a first Spin On Dielectric (SOD) partially filling the trench; forming a stress shielding layer over the first SOD, the stress shielding layer being denser than the first SOD; forming a second SOD that fills the trench over the first SOD including the stress shielding layer, forming a recess groove by selectively etching a portion of the active region of a semiconductor substrate, wherein the upper surface of the first SOD is spaced downwardly from the bottom of the recess groove, and the upper surface of the stress shielding layer inside the trench is spaced upwardly from the bottom of the recess groove; and forming a gate of a transistor that fills the recess groove.