Patent ID: 8675387

Claim:
A variable resistance nonvolatile memory device comprising: memory cells each of which includes a variable resistance element and a current steering element having two terminals connected in series, the variable resistance element changing, by application of a first voltage having a predetermined first polarity, to a low resistance state with a resistance value in a first range, and changing, by application of a second voltage having a second polarity opposite to the first polarity, to a high resistance state with a resistance value in a second range higher than the first range; first signal lines and second signal lines crossing the first signal lines; a memory cell array in which the memory cells are arranged at cross-points of the first signal lines and the second signal lines and each of the memory cells has ends connected to a set of one of the first signal lines and one of the second signal lines which crosses one of the first signal lines; a programming circuit which generates a bipolar voltage to be applied to the memory cells through the first signal lines and the second signal lines; a current limit circuit placed in a path of a current flowing from the programming circuit to the memory cells, the current limit circuit limiting only a first current among the first current and a second current, the first current flowing in a direction for changing the memory cells to the low resistance state, and the second current flowing in a direction for changing the memory cells to the high resistance state; and a boost circuit that is connected in parallel to the current limit circuit and increases, when one of the memory cells changes to the low resistance state, the first current by short-circuiting the path of the current and a voltage supply during a first period before the memory cell changes to the low resistance state.