Patent ID: 8420521

Claim:
A method for fabricating a stack structure of semiconductor packages, the method comprising the steps of: providing a substrate having a first surface and a second surface opposite to the first surface, wherein a plurality of electrical connection pads and dummy pads are formed on the second surface of the substrate; mounting and electrically connecting at least one semiconductor chip to the first surface of the substrate; implanting a plurality of solder balls to the electrical connection pads and the dummy pads of the second surface of the substrate, so as to form an upper semiconductor package; and providing a fabricated lower semiconductor package comprising a substrate, a semiconductor chip disposed on and electrically connected to the substrate, and an encapsulant formed on the substrate and encapsulating the semiconductor chip, and mounting the upper semiconductor package on the lower semiconductor package, wherein the upper semiconductor package is electrically connected to the substrate of the lower semiconductor package by the solder balls implanted to the electrical connection pads of the upper semiconductor package, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads of the upper semiconductor package, so as to form the stack structure of semiconductor packages.