Patent ID: 8187923

Claim:
A process of fabricating an integrated circuit module on a glass handle wafer comprising; obtaining a semiconductor substrate having CMOS BEOL wiring defined thereon; obtaining a glass handler wafer; applying a layer of a synthetic adhesive on the substrate or on the glass handler wafer or both, and curing the synthetic adhesive, wherein the synthetic adhesive upon curing can withstand temperatures of at least 400° C.; laminating the glass handler wafer to the semiconductor substrate with the synthetic adhesive located between the semiconductor substrate and the glass handler wafer; thinning the semiconductor-carrier wafer to the thickness of the CMOS BEOL wiring or greater than the thickness of the CMOS BEOL wiring but less than about 150 μ; carrying out processing on the backside of the semiconductor-carrier wafer after the thinning; depositing C4 balls on the semiconductor-carrier wafer; then dicing the carrier wafer with the glass-handler wafer to a pre-determined carrier size; and joining the diced semiconductor carrier-laminated glass handler wafer to a substrate using the C4 balls; subjecting the supported module to an excimer laser release process to degrade the release adhesive and separating the glass handler wafer from the module; placing the module onto a vacuum chuck of a X-Y translation stage to minimize module jitter during ablation/release; wherein the edges of the carrier/adhesive/glass handler module are exposed first on tilt stage to the laser radiation; and wherein the bulk carrier/adhesive/glass handler module is exposed to laser radiation at 0degree tilt, whereby cracking of the carrier edge is avoided.