Patent ID: 8239051

Claim:
An information processing apparatus comprising: a node; and a system controlling apparatus connected to the node, wherein the node comprising: a first detecting unit that detects first error information indicating a level or message of a fault state of hardware; a second detecting unit that detects second error information indicating the level or message of the fault state of hardware and different from the first error information; a retaining unit that retains the first error information and the second error information at corresponding bit positions; and a temporary retaining unit that retains new first error information that is different from the first error information stored in the retaining unit and is newly detected by the first detecting unit and new second error information that is different from the second error information stored in the retaining unit and is newly detected by the second detecting unit, in corresponding bit positions, and when the first or second error information retained in the retaining unit is initialized by the system controlling apparatus, causes the retaining unit to store error information corresponding to the initialized first or second error information from among the retained new first and second error information, and wherein the system controlling apparatus comprising: a controlling unit connected to the retaining unit; and a firmware that causes the controlling unit to read into the first and second error information retained in the retaining unit and causes the controlling unit to initialize the new first or second error information.