Patent ID: 8089809

Claim:
A logic interconnect circuit, comprising: a) a first and a second split gate storage device, each split gate storage device comprising a word gate and a control gate, wherein a first insulator to store charge located under said control gate of the first split gate storage device and a second insulator to store charge located under said control gate of the second split gate storage device; b) said word gates of the first and second split gate storage devices connected together; c) said first and second split gate storage devices connected in series between a high voltage and a low voltage wherein said first split gate storage device connected to said high voltage and said second split gate storage device connected to said low voltage, and wherein the connection between the first and second split gate storage devices coupled to a logic interconnect transistor through a pass gate transistor; and d) stored charge in said first and second insulators determines an “on” or “off” state of said logic interconnect transistor.