Patent ID: 7078758

Claim:
A semiconductor device comprising: a semiconductor substrate having a memory formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in said memory formation region; a second impurity region formed in the upper surface of said semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of said first impurity region and having a conductivity type different from that of said first impurity region; a fourth impurity region formed in an upper surface of said second impurity region and having a conductivity type different from that of said second impurity region; a first silicide film formed in an upper surface of said third impurity region; a capacitor formed above said first silicide film and electrically connected to said first silicide film; and a second silicide film formed in an upper surface of said fourth impurity region and having a larger thickness than said first silicide film.