Patent ID: 8080861

Claim:
A semiconductor device comprising: a substrate; an electric fuse formed over said substrate; a first large area wiring which is formed in at least a first layer over said substrate for applying a first voltage to said electric fuse; a second large area wiring which is formed in at least a second layer, which is different from said first layer, over said substrate for applying a second voltage to said electric fuse; and a guard portion formed on at least one side of the electric fuse and entirely parallel to the first large area wiring and the second large area wiring when seen in a plan view and entirely parallel to the first large area wiring and the second large area wiring when seen from a top view, wherein said electric fuse includes: a fuse unit which includes a first fuse wiring formed in said first layer, a second fuse wiring formed in said second layer, and a via connecting said first fuse wiring and said second fuse wiring, and in which a flowing-out portion of a conductive material constituting said electric fuse and a cutting-off portion are formed when said fuse is cut off; a first lead-out wiring which is formed in said first layer, connects said first fuse wiring and said first large area wiring, and has a bent pattern; and a second lead-out wiring which is formed in said second layer, connects said second fuse wiring and said second large area wiring, and has a bent pattern.