Patent ID: 8319767

Claim:
A driver, comprising: a plurality of amplifier circuits which outputs a plurality of gradation voltages to a display portion according to a control signal; a control circuit which outputs the control signal; and a delay portion which sequentially supplies the control signal to amplifier circuits in a first amplifier circuit group including half of the plurality of amplifier circuits, and which sequentially supplies a delayed control signal to amplifier circuits in a second amplifier circuit group other than the first amplifier circuit group, the delayed control signal being obtained by delaying the control signal by a certain delay time, wherein, when the plurality of amplifier circuits are N amplifier circuits provided in order from a first amplifier circuit to an Nth amplifier circuit (where N is an integer of 4 or more and is a multiple of 2), the first amplifier circuit group includes the first amplifier circuit to an (N/2)th amplifier circuit, the second amplifier circuit group includes the Nth amplifier circuit to an ((N/2)+1)th amplifier circuit, the control circuit outputs the control signal to the first amplifier circuit, and the delay portion includes: a first delay portion which delays the control signal by a first delay time in order from a second amplifier circuit to the (N/2)th amplifier circuit, to supply the control signal to the second amplifier circuit to the (N/2)th amplifier circuit; a second delay portion which delays the control signal by a second delay time to produce the delayed control signal to supply the delayed control signal to the Nth amplifier circuit; and a third delay portion which delays the delayed control signal by the first delay time in order from an (N−1)th amplifier circuit to the ((N/2)+1)th amplifier circuit, to supply the delayed control signal to the (N−1)th amplifier circuit to the ((N/2)+1)th amplifier circuit, and wherein the second delay time is shorter than the first delay time.