Patent ID: 8440512

Claim:
A method for reducing the impact of inter-transistor variance, the method comprising: providing a first transistor including a first drain having a first side and a second side, and a first source having a third side and a fourth side; wherein the first side is closer to the third side than to the fourth side; wherein the first side is closer to the third side than the second side is to the third side; wherein the first transistor includes a first channel extending from the first drain to the first source, and wherein the first channel varies in cross-sectional width from the third side of the first source to the first side of the first drain; and providing a second transistor including a second drain and a second source, wherein the second transistor includes a second channel extending from the second drain to the second source, and wherein the second channel varies in cross-sectional width from the second source to the second drain, and wherein the second drain is the closest drain to the third side.