Patent ID: 8648450

Claim:
A semiconductor device, comprising: a generally planar die pad defining multiple peripheral edge segments, a die pad top surface and a die pad bottom surface; a tie bar comprising an inner portion and an outer portion separated from the inner portion by a gap, the inner portion attached to and extending from the die pad, the tie bar having a tie bar top surface and a tie bar bottom surface, wherein the tie bar top surface of the outer portion is co-planar with the die pad top surface, and wherein a first portion of the tie bar bottom surface of the outer portion comprises a recessed surface that is half-etched; a plurality of first lands which are segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto; a plurality of second lands which are segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto; a plurality of leads which are segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, each of the leads defining at least one land portion; a semiconductor die attached to the die pad and electrically connected to the first and second lands and the leads; and a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the tie bar, the first and second lands, the leads, and the semiconductor die such that at least portions of the first and second lands, and the land portions of the leads are exposed in and substantially flush with the bottom surface of the package body, and are positioned between the die pad and the side surface of the package body, and wherein the first portion of the tie bar bottom surface is encapsulated by the package body.