Patent ID: 8274412

Claim:
An integrated circuit having a serializer (e.g., 100 ) adapted to serialize N-bit parallel data, where N is an odd integer, the serializer comprising: a transfer stage (e.g., 102 ) connected to transfer the N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain; an update stage (e.g., 104 , 106 ) connected to receive parallel data from the transfer stage; and a serializing stage (e.g., 108 , 110 ) connected to convert parallel data received from the update stage into serial data having N-bit data words, wherein the update stage is selectively configurable to cause the serializer to operate in either (i) an N−1 operating mode in which (N−1) bits of parallel data are serialized or (ii) an N+1 operating mode in which (N+1) bits of parallel data are serialized.