Patent ID: 7006527

Claim:
A system that converts words of pipelined data from a first data width to a smaller second data width over a series of cycles, comprising: a pipeline control that generates a word output from the pipeline control that is at least twice as wide as the first data width entering the pipeline control, and shifts the pipelined data within the generated word such that the pipelined data word is, depending on the cycle, either prefixed by zeros, suffixed by zeros, or both, and that outputs a residual portion that is at least as wide as the word output having a second data width and a current portion that is at least as wide as the second data width; a delay register that receives at least a portion of the residual portion of the data from the pipeline control and delays the received residual portion one cycle from the current portion of the data from the pipeline control; a combiner circuit that compares the delayed residual portion of data from the delay register with the current portion of data from the pipeline control, and outputs data having a width equal to the second data width; and output conduits that, for every complete series, transport; the current portion of the data during the initial cycle; the combiner circuit output during the non-initial cycles; and the residual portion of the data during the final cycle.