Patent ID: 8766663

Claim:
A circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, said circuit comprising: a P-channel field effect transistor (PFET) calibration impedance matching function determining calibration bits PVTP for output stage PFETs, an N-channel field effect transistor (NFET) calibration impedance matching function coupled to said PFET calibration impedance matching function, determining calibration bits PVTN for output stage NFETs, responsive to PFET calibration completed, and an output latch function coupled to said PFET calibration impedance matching function and said NFET calibration impedance matching function, providing PVTP and PVTN calibration outputs, responsive to NFET calibration completed, to the linearly weighted, thermal coded I/O driver output stage within a single predefined calibration cycle.