Patent ID: 7232749

Claim:
A method for manufacturing an integrated circuit inductance, comprising: providing a first dielectric layer and a first photo-resist layer thereon; forming a first pattern in said first photo-resist layer through exposing a portion of said first dielectric layer, said first pattern defining a plurality of first conductive wires substantially in parallel with one another; filling a first conductive material into said first pattern to form said first conductive wires; removing said first photo-resist layer; forming a second dielectric layer over said first conductive wires; forming a second photo-resist layer on said second dielectric layer; forming a plug pattern in said second photo-resist layer through exposing a portion of said second dielectric layer, wherein said plug pattern has a plurality of plugs located on a plurality of terminals of said first conductive wires; etching said second dielectric layer with said plug pattern as a mask to expose said two terminals of each said first conductive wire; filling a second conductive material into said plug pattern to form said plugs in parallel with one another and substantially perpendicular to said first conductive wires; removing said second photo-resist layer; forming a third photo-resist layer on said second dielectric layer and said plugs; forming a second pattern in said third photo-resist layer through exposing a portion of said second dielectric layer and said plugs, said second pattern defining a plurality of second conductive wires substantially in parallel with one another, wherein said second pattern connects two said plugs which are located at two said respective terminals of two said adjacent first conductive wires and in diagonal relation; filling a third conductive material into said second pattern to form said second conductive wires in parallel with one another and substantially perpendicular to said plugs; removing said third photo-resist layer; and forming a third dielectric layer over said second conductive wires and said second dielectric layer.