Patent ID: 7678627

Claim:
A process for producing a thin film transistor display comprising steps of: providing a substrate; forming a polysilicon layer on said substrate; patterning said polysilicon layer to define a first and a second TFT regions; providing a first and a second doping masks on said polysilicon layer in said first and said second TFT regions to result in a first exposed portion in said first TFT region and a second exposed portion in said second TFT region; implanting a first doping material into said first and said second exposed portions, thereby defining a first doped region and a first channel region adjacent to said first doped region in said first TFT region, and a second doped region and a second channel region adjacent to said second doped region in said second TFT region; removing said first doping mask without removing said second doping mask; providing a third doping mask on said first channel region, which partially overlies said first doped region, so as to result in a third exposed portion in said first TFT region smaller than said first exposed portion; implanting a second doping material into said third exposed portions and said second exposed portion to form first source/drain regions and second source/drain regions and simultaneously define a first LDD region; removing said second doping mask along with said third doping mask; forming an insulator layer and a gate metal layer on the resulting structure; and patterning said gate metal layer to form a first and a second gate structures over said first and said second channel regions, respectively, wherein in a certain direction, said first gate structure is longer than said first channel, and said second gate structure has length no greater than the length of said second channel region.