Patent ID: 8271841

Claim:
A method for testing an integrated circuit to detect delay faults resulting from a signal path from a first block of the integrated circuit to a second block of the integrated circuit, the method comprising: shifting first data into scan memory cells of the integrated circuit at a first frequency; determining a second frequency according to a speed of the signal path from the first block to the second block; applying a launch test clock pulse to a clock input of the first block; applying a capture test clock pulse to a clock input of the second block, wherein the first edges of the launch and capture pulses are delayed with respect to each other by a period that is a reciprocal of the second frequency, wherein the first and second blocks run at different application speeds; shifting second data from the scan memory cells to an output at the first frequency; and comparing the second data at the output with expected values, wherein determining the second frequency comprises determining the second frequency to be in a range of 5-20% larger than the reciprocal of a time that a signal propagates from a latch in the first block to a latch in the second block.