Patent ID: 7406113

Claim:
A semiconductor integrated circuit for processing a plurality of received broadcast signals, the broadcast signals being of a type each having a different respective digital code, the semiconductor integrated circuit comprising: a digital sampler; a sample reducer; and a plurality of correlators being arranged to be operable in two modes wherein: in an acquisition mode: the digital sampler is adapted to sample the received broadcast signals to produce a digital bit stream at a first bit rate; the sample reducer is adapted to reduce bits of the digital bit stream by combining groups of N bits together to produce a reduced digital bit stream; the plurality of correlators is adapted to receive the reduced digital bit stream at a second bit rate, being higher than the first bit rate, and each of the plurality of correlators is adapted to correlate the reduced digital bit stream with a same locally generated version of one of the different digital codes; and in a track mode: the digital sampler is adapted to sample the received broadcast signals to produce a digital bit stream at the first bit rate and to provide the digital bit stream direct to each of the plurality of correlators, each correlator is adapted to correlate the digital bit stream with a different locally generated version of one of the digital codes, wherein for the acquisition mode, the sample reducer includes an adder to add the groups of N bits, wherein in the acquisition mode, the adder is adapted to provide a digital output representative of a value of a sum of the N bits, and wherein in the acquisition mode, the adder is adapted to provide an output having a first logic state if the sum of the N bits is greater than a given value and an output having a second logic state opposite to said first logic state if the sum of N bits is less than the given value.