Patent ID: 8732225

Claim:
Digital signal processing (“DSP”) block circuitry comprising: first multiplier circuitry for producing a first output signal indicative of a first multiplication product of a multiplicand signal and a multiplier signal; first systolic delay circuitry for delaying at least one of (1) the multiplicand signal and (2) the multiplier signal by at least one systolic delay time interval; second multiplier circuitry for producing a second output signal indicative of a second multiplication product; adder circuitry for adding the first and second output signals and a third signal indicative of a data value received from a first other instance of said DSP block circuitry; output register circuitry for registering an output signal of the adder circuitry; and second systolic delay circuitry for delaying output of the output register circuitry by at least one of the systolic delay time interval.