Patent ID: 8200908

Claim:
A data processing system comprising: a system interconnect; a first interconnect master coupled to the system interconnect, the first interconnect master having a cache; a second interconnect master coupled to the system interconnect; and a cache coherency manager coupled to the first and second interconnect masters and an external debugger, wherein the cache coherency manager provides debug cache coherency operations and non-debug cache coherency operations to the first interconnect master, the cache coherency manager generates the debug cache coherency operations in response to debug cache coherency commands from the external debugger and generates the non-debug cache coherency operations in response to transactions performed by the second interconnect master on the system interconnect, the cache coherency manager provides second debug cache coherency operations and second non-debug cache coherency operations to the second interconnect master, and the cache coherency manager generates the second debug cache coherency operations in response to second debug cache coherency commands from the external debugger and generates the non-debug cache coherency operations in response to transactions performed by the first interconnect master on the system interconnect.