Patent ID: 8610210

Claim:
A power semiconductor device comprising: a first semiconductor layer of a first conductivity type; first semiconductor regions of a second conductivity type filling trench grooves formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type, which is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface of the first semiconductor layer and in a terminal portion provided around the device portion; a second semiconductor region of the first conductivity type, which is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions; and third semiconductor regions of the second conductivity type provided below the first semiconductor regions in communication with the first semiconductor regions in the terminal portion, wherein the third semiconductor regions have a width that is greater than a width of a base of the first semiconductor regions provided in the device portion, and a concentration of impurities of the second conductivity type doped in the third semiconductor regions decreases more gradually from each of the third semiconductor regions toward the second semiconductor layer at a boundary therebetween than a concentration of impurities of the second conductivity type doped in the first semiconductor regions which decrease from each of the first semiconductor regions toward the second semiconductor region at a boundary therebetween.