Patent ID: 8027828

Claim:
An apparatus for performing hardware emulation using synchronized processors comprising: a plurality of processors, the plurality of processors part of an emulation chip, defining a plurality of processor groups for evaluating data regarding a hardware design that has been divided into an unconditional submodel and a conditional submodel; a data memory coupled to the plurality of processors; a plurality of submodel matching blocks coupled to the data memory and configured to control whether a processor of the plurality of processors can write to the data memory based on whether the processor is evaluating a submodel currently selected for evaluation; a synchronizer for synchronizing the operation of the plurality of processor groups while emulating at least a portion of the hardware design such that the plurality of processor groups first select the unconditional submodel for evaluation, then select the conditional submodel for evaluation after instructions of the unconditional submodel have been evaluated, wherein each of the plurality of processor groups enters a wait state until the unconditional submodel has been completely evaluated.