Patent ID: 7126511

Claim:
A circuit arrangement for delay adjustment of analog-to-digital converters operating in a temporally offset manner, having: (a) at least two analog-to-digital converters each having a signal path, which receive an analog signal present at an input of the circuit arrangement and convert it into a digital intermediate signal, each of the analog-to-digital converters being clocked by a respective clock signal, the clock signals having a predetermined time offset with respect to one another; (b) a logic circuit, which interconnects the digital intermediate signals for the purpose of generating a digital output signal of the circuit arrangement; (c) means for bandwidth setting having an input and an output for changing the bandwidth of the signal paths of the analog-to-digital converters; and (d) an adjustment device, which has an output connected to the input of the circuit arrangement, and an input connected to the output of the circuit arrangement, and supplies control signals to the means for changing the bandwidth in such a way that by changing the bandwidth of at least one signal path a deviation of the clock signal from the predetermined time offset for the respective analog-to-digital converter is compensated for.