Patent ID: 7757188

Claim:
A method for designing an integrated circuit that designs an integrated circuit by dividing the integrated circuit into a plurality of blocks in an integrated circuit designing apparatus, the method comprising: creating at a block level net list creating unit a block level net list by grouping circuit elements belonging to the same block for the circuit elements to be designed at the block level and assigning an input pin to the grouped circuit elements; creating at a chip level net list creating unit a chip level net list for the circuit elements to be designed at the chip level and the input pin, while clarifying a circuit element whose destination block can be determined among the circuit elements to be designed at the chip level; determining at a destination block determining unit a destination block for a circuit element whose destination block cannot be determined among the circuit elements to be designed at the chip level; and creating at a final net list creating unit a final block level net list by reflecting the chip level net list on the block level net list based on information on the determined destination block, while adding a keyword indicating that a component name owned by the net list part to be reflected is generated from the chip level net list to the component name in reflecting the chip level net list on the block level net list.