Patent ID: 7164302

Claim:
A structure comprising: a dynamic data input terminal; a storage node; a not storage node; an output terminal; a data clock line; a staticizer connected to the input terminal, the output terminal, and the data clock line; a mirror staticizer connected to the input terminal in parallel with the staticizer, to the storage node, and to the data clock line; a weak keeper having an input terminal connected to the storage node and an output terminal connected to the not storage node; and a strong enabled tri-state keeper connected to the not storage node, to the data clock line, and to the output terminal, wherein the strong enabled tri-state keeper comprises: a transistor of a first type comprising: a first lead couplable to and de-couplable from a first power supply voltage; a second lead connected to the output terminal; and a third lead connected to the data clock line; a transistor of second type comprising a first lead connected to the output terminal; a second lead couplable to and de-couplable from a second power supply voltage; and a third lead connected to the not storage node; another transistor of the first type comprising a first lead connected to the first power supply voltage; a second lead connected to the first lead of the transistor of the first lead; and a third lead connected to the not storage node; wherein the another transistor is shared with the weak keeper.