Patent ID: 7939445

Claim:
A method of forming an interconnect structure, the method comprising: defining a first metal pattern having a minimum feature size in a layout view; removing, from the first metal pattern, metal features having the minimum feature size in more than one dimension; forming a first pattern of metal lines according to the first metal pattern with the metal features having the minimum feature size in more than one dimension removed, each of the metal lines having the minimum feature size in no more than one dimension; forming a first dielectric layer on or over the first pattern of metal lines, the dielectric layer having a substantially planar horizontal upper surface; etching a plurality of via holes in the first dielectric layer using a via mask, the plurality of via holes exposing a top surface of the metal lines; changing an etchant chemistry after exposing the top surface of the metal lines, and continuing to etch the plurality of via holes using the changed etchant chemistry to expose a top surface of contacts, vias, or silicon structures below the metal lines in one or more areas where the metal features having the minimum feature size in more than one dimension have been removed; and depositing metal in the via holes.