Patent ID: 7396775

Claim:
A method for manufacturing semiconductor device, the method comprising the steps of: (a) providing a semiconductor substrate including a cell region when Fin cell transistors are formed, a V PP peripheral circuit region where transistors used for generation and transfer of V PP voltage are formed, and a V DD peripheral circuit region where V DD transistors are formed; (b) forming a device isolation film on the semiconductor substrate to define an active region; (c) etching the device isolation film in the cell region to at least expose a sidewall of a predetermined portion of the active region where a channel region is to be formed; (d) forming a first gate oxide film pattern on a surface of the active region including the exposed sidewall in the cell region; (e) forming a second gate oxide film pattern on the first gate oxide film pattern and a surface of the semiconductor substrate in the V PP peripheral circuit region; (f) forming a third gate oxide film pattern on the second gate oxide film pattern and a surface of the semiconductor substrate in the V DD peripheral circuit region; (g) forming a planarized conductive layer for a lower gate electrode on an entire surface of the semiconductor substrate; (h) sequentially forming a conductive layer for an upper gate electrode and a hard mask layer on the conductive layer for the lower gate electrode; (i) patterning the hard mask layer, the conductive layer for the upper gate electrode and the conductive layer for the lower gate electrode to form a gate structure including Fin cell gates in the cell region, wherein the gate structure comprises a stacked structure of the lower gate electrode, the upper gate electrode and a hard mask layer pattern; and (j) forming a source/drain region on the semiconductor substrate at both sides of the gate structure; wherein the thickness of the gate oxide film of the Fin cell transistor in the cell region is larger than that of the transistor used for the V PP peripheral circuit region, and the thickness of the gate oxide film of the transistor used for the V PP peripheral circuit region is larger than that of the transistor used for the V DD peripheral circuit region and wherein the gate oxide film of the Fin cell transistor includes the first, the second and the third gate oxide film patterns, the gate oxide film of the V DD peripheral circuit region includes the second and the third gate oxide film patterns, and the gate oxide film of the V PP peripheral circuit region includes the third gate oxide film patterns.