Patent ID: 7392499

Claim:
A processor-implemented method for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit, comprising: assigning each IOB to one of a plurality of sets, wherein the electronic design includes at least one input/output bus associated with a plurality of the IOBs, and the plurality of IOBs for each input/output bus are assigned to a respective one of the sets; for each combination of pairs of the sets, each pair having a first set and a second set, generating a respective weight factor that indicates a degree of coupling between the first and second sets in the electronic design; generating an order of the sets; placing the sets, according to the order of the sets, in an ordered series of input/output sites in the integrated circuit; evaluating a cost function, including summing respective terms for each of the pairs of the sets, each respective term being a product of the respective weight factor for the pair and a distance between a center of the input/output sites of the first set of the pair and a center of the input/output sites of the second set of the pair; and conditionally repeating the generating of the order of the sets and the placing of the sets responsive to the evaluating of the cost function.