Patent ID: 8780658

Claim:
A memory device comprising: a core array comprising a plurality of memory cells and a core array headswitch, the core array headswitch coupled to a positive supply voltage, the core array headswitch reducing leakage current from the core array; a write driver coupled to the core array, the write driver comprising: a plurality of write driver headswitch transistors coupled to data lines; and control logic coupled to the write driver headswitch transistors and configured to disconnect the data lines from a supply voltage to reduce leakage current from the data lines in response to the data lines and a control signal; a bit line precharge circuit coupled to bit lines; and a logic gate coupled to the bit line precharge circuit and an equalization circuit, wherein the logic gate is selected from the group consisting of a NAND gate, a NOR gate, a XOR gate and a NXOR gate, wherein a first input of the logic gate is coupled to the control signal, a second input of the logic gate is coupled to a precharge signal, and wherein the logic gate is configured to: generate an output based on the first input of the logic gate and the second input of the logic gate; and if the output is high, the bit line precharge circuit disconnects the bit lines from the supply voltage.