Patent ID: 7808812

Claim:
A static random access memory (SRAM) cell comprising: a pair of cross-coupled inverters having a first storage node; a first NMOS transistor having a source and a drain connected between the first storage node and a first signal line; a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a second signal line, the second NMOS transistor having a gate connected to a third signal line; a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, the third NMOS transistor having a gate connected to a fourth signal line, the fourth signal line being complementary to the third signal line; and a fourth NMOS transistor having a source and a drain connected between a second storage node of the pair of cross-coupled inverters and a fifth signal line, the second storage node being complimentary to the first storage node.