Patent ID: 7485535

Claim:
A method of fabricating a semiconductor device, comprising: forming a mask pattern on a substrate; patterning the substrate using the mask pattern as an etch mask to form a trench for defining an active region; forming an insulation layer in the trench to provide a device isolation layer, wherein the device isolation layer has an upper sidewall contacting the mask pattern; removing the mask pattern to expose the upper sidewall of the device isolation layer; laterally recessing the upper sidewall of the device isolation layer and vertically recessing a portion of the device isolation layer to expose an upper sidewall of the trench that protrudes vertically relative to the device isolation layer; forming an epitaxial layer on the active region, wherein the epitaxial layer is formed to extend on and contact a portion of the device isolation layer that is recessed vertically relative to an upper surface of the active region and contact the upper sidewall of the trench that protrudes vertically relative to the device isolation layer; forming a gate pattern crossing over the epitaxial layer; and implanting impurity ions in the epitaxial layer at both sides of the gate pattern to form source and drain regions.