Patent ID: 7236421

Claim:
A circuit arrangement for providing read-modify-write memory for a system having row address lines and bank address lines, the circuit arrangement comprising: a memory having at least one read-or-write bank electrically coupled to a read-modify-write bank having a tag that indicates a read-or-write bank to which data in the read-modify-write bank belongs; a modify logic for modify data during a read-modify-write operation; a comparator; and a multiplexer; wherein: the tag accepts inputs from the row and bank address lines and delivers output to the comparator; the read-modify-write bank accepts inputs from the row address lines and modify logic and delivers output to the multiplexer; the at least one read-or-write bank accepts inputs from the row address lines, the bank address line, the tag and the read-modify-write bank and delivers output to the multiplexer; and the comparator accepts inputs from the bank address lines and the tag and delivers an output for controlling the multiplexer.