Patent ID: 7998812

Claim:
An exposure method comprising: performing a first exposure using a first mask, the first mask comprising a first transparent substrate, a pattern of a memory cell array provided on the first transparent substrate, wherein the memory cell array corresponds to a memory cell array area provided on a semiconductor substrate, and a first light shielding portion provided on the first transparent substrate, wherein the first light shielding portion corresponds to a peripheral circuit area provided on the semiconductor substrate; and performing a second exposure using a second mask, the second mask comprising a second transparent substrate, a pattern of a peripheral circuit provided on the second transparent substrate, wherein the peripheral circuit area provided on the second transparent corresponds to the peripheral circuit area provided on the semiconductor substrate, and a second shielding portion provided on the second transparent substrate, wherein the second light shielding portion corresponds to the memory cell array area, wherein the first mask further comprises a first area corresponding to a boundary area having a specific width provided between the memory cell array area and the peripheral circuit area, and the first area is provided with no pattern thereon, and the second mask further comprises a second area corresponding to the boundary area, and the second area is provided with no pattern thereon.