Patent ID: 7843717

Claim:
A semiconductor storage device including a memory array compartmentalized into a plurality of first regions and second regions alternately arranged, the second regions being formed by odd and even columns alternately arranged, the semiconductor storage device comprising: a memory mat array arranged in each of the first regions; a sense amp array arranged in each of the second regions; local IO lines arranged in each of the second regions and connected to the sense amp array; main IO lines crossing all of the first regions and the second regions; and a read/write amplifier arranged in each of the second regions and at one of intersection regions where the local IO lines cross the main IO lines, wherein the read/write amplifier in one of the odd columns is connected to a first local IO line in said one of the odd columns and to a second local IO line in next one of the odd columns, and the read/write amplifier in one of the even columns is connected to a third local IO line in said one of the even columns and to a fourth local IO line in next one of the even columns.