Patent ID: 7544576

Claim:
A semiconductor fabrication method, comprising: forming a gate module, including a gate electrode overlying a gate dielectric, overlying a substrate of a semiconductor wafer; etching recesses in the semiconductor substrate using the gate module as an etch mask wherein the recesses are self aligned to the gate module; non-selectively depositing a barrier layer over the wafer, wherein the barrier layer is selected from the group consisting of TiN, TaN, ZrN, MoN, WN, TaSiN, TiSiN, and TiAIN; etching the barrier layer selectively to form barrier structures adjacent to sidewalls of the recesses by removing horizontally oriented portions of the barrier layer; and depositing a metal layer, wherein the metal layer contacts an underlying semiconductor within the recesses and the metal layer comprises a nickel layer; annealing the wafer to react portions of the metal layer with the underlying semiconductor to form a silicide selectively and, after said annealing, removing unreacted portions of the metal layer.