Patent ID: 7636837

Claim:
An apparatus for controlling instructions, comprising: an instruction fetch control unit configured to exercise such control as to fetch instructions from a memory unit storing the instructions therein that are to be executed according to an out-of-order method, the memory unit including a cache control unit and a cache memory having cache lines holding a fetched instruction respectively; an instruction buffer configured to store temporarily the instructions supplied from the memory unit; an instruction decoder configured to decode the instructions supplied from the instruction buffer; a branch instruction prediction unit configured to make branch prediction with respect to an instruction; and a branch prediction control unit configured to control the instruction fetch control unit, the instruction buffer, the instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch prediction by the branch instruction prediction unit is erroneous, the branch prediction control unit outputs to the instruction fetch control unit a cancellation signal suppressing an instruction fetch request already supplied to the memory unit thereby to cause the instruction fetch control unit to supply to the cache control unit a signal informing of nullification of the instruction fetch request and outputs to the instruction buffer the cancellation signal nullifying the instruction buffer during a time period between a point in time at which the ascertainment is made by the branch prediction control unit that the branch prediction by the branch instruction prediction unit is erroneous and a point in time at which the instruction buffer fetches a correct instruction from the memory unit, the cancellation signal starting to be output in response to said ascertainment and being continuously output for said time period until the fetching of the correct instruction; wherein the signal informing of nullification of the instruction fetch request having already been supplied to the cache control unit causes the cache control unit of the memory unit to nullify the instruction fetch request having already been supplied to the cache control unit and avoids replacement of the cache line in the cache memory caused by an instruction fetch operation corresponding to the instruction fetch request.