Patent ID: 8736332

Claim:
A device comprising a sequential circuit having an active mode and a standby mode, the sequential circuit comprising: a first combinational logic circuit; a first set of one or more reset flip-flops, each reset flip-flop having (i) a data input port, (ii) a reset port, and (iii) a data output port coupled to a corresponding data input port of the first combinational logic circuit; a first set of one or more set-reset flip-flops, each set-reset flip-flop having (i) a data input port, (ii) a set port, (iii) a reset port, and (iv) a data output port coupled to a corresponding data input port of the first combinational logic circuit, wherein the first combinational logic circuit provides reduced leakage current when (i) each reset flip-flop provides a data value of 0 and (ii) each set-reset flip-flop provides a data value of 1 to the corresponding data input ports of the first combinational logic circuit; and a control module coupled to the one or more reset flip-flops and to the one or more set-reset flip-flops, wherein the control module is configured to: apply active-mode data values presented at the data input ports of (i) the one or more reset flip-flops and (ii) the one or more set-reset flip-flops to the corresponding data input ports of the first combinational logic circuit during the active mode of the sequential circuit; and (i) reset the one or more reset flip-flops such that the data output port of each reset flip-flop applies a data value of 0 to the corresponding data input port of the first combinational logic circuit and (ii) set the one or more set-reset flip-flops such that the data output port of each set-reset flip-flop applies a data value of 1 to the corresponding data input port of the first combinational logic circuit during the standby mode of the sequential circuit to configure the first combinational logic circuit to provide the reduced leakage current.