Patent ID: 7883966

Claim:
A method for manufacturing a memory device comprising: depositing an insulating layer on a semiconductor substrate; forming a first trench by etching the insulating layer and the semiconductor substrate to a predetermined depth; forming a tunneling oxide layer in the first trench; forming a floating gate layer on the tunneling oxide layer; forming an indentation by etching a central portion of the floating gate layer to a predetermined depth; forming a dielectric layer on the floating gate layer; forming a control gate layer in the first trench on the dielectric layer, each of the floating gate, the dielectric layer and the control gate having an outermost sidewall contacting the tunneling oxide layer; forming an oxide layer on the control gate layer; forming a second trench by removing central portions of the oxide layer, the control gate layer, the dielectric layer, the floating gate layer, and the tunneling oxide layer in the first trench; forming a buffer dielectric layer on a sidewall of the second trench, wherein each of the floating gate, the dielectric layer, and the control gate have an innermost sidewall in contact with the buffer dielectric layer; forming a source junction by implanting impurity ions into the semiconductor substrate below the second trench; forming a source electrode in the second trench, electrically connected to the source junction; and forming a drain junction by implanting impurity ions into exposed areas of the semiconductor substrate.