Patent ID: 7127588

Claim:
A processor comprising: i. A first thread and a second thread, said first thread comprising a first processing unit and said second thread comprising a second processing unit; ii. A first instruction packet and a second instruction packet, said first instruction packet comprising at most two issue groups and said second instruction packet comprising at most two issue groups, each of said at most two issue groups of said first instruction packet and each of said at most two issue groups of said second instruction packet comprising at most 64 bits and an internal instruction bus no greater than 64 bits wide for transport to one of said first and second processing units; iii. Each of said first and second threads receiving a respective one of said at most two issue groups of a respective one of said first and second instruction packets; iv. Said first processing unit executing one of said at least two issue groups of said first instruction packet and said second processing unit executing one of said at most two issue groups of said second instruction packet in a single clock cycle; v. Each of said at most two issue groups of each of said first and second instruction packets performing an operation on data fetched from an exclusive thread memory communicating with only one of said first and second threads, a result of said operation being stored back in said exclusive thread memory communicating with said only one of said first and second threads.