Patent ID: 7073107

Claim:
A method of testing integrated circuits, the method comprising the steps of: performing on each of the integrated circuits a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits, recording the first test results with associated integrated circuit identification information, logically subdividing the integrated circuits into bins based at least in part on the associated integrated circuit identification information and not on the first test results, calculating a defectivity value for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information, performing on the integrated circuits within each of the bins a second test at a second level of testing at a succeeding testing step in the fabrication cycle of the integrated circuits to produce second test results associated with a second characteristic of the integrated circuits, where the second characteristic is related to the first characteristic and the second level of testing is varied from bin to bin based at least in part on the defectivity value for the bin being tested, where the second level of testing is a normal level of testing, based on the defectivity being substantially equal to a predetermined value, the second level of testing is a reduced level of testing, based on the defectivity being less than the predetermined value, and the second level of testing is an elevated level of testing, based on the defectivity being more than the predetermined value, calculating a second running defectivity for the bin during the second test, and dynamically adjusting the second level of testing for the bin based at least in part on the second running defectivity.