Patent ID: 8021937

Claim:
A method of fabricating an array substrate, comprising: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrodes to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.