Patent ID: 8812997

Claim:
In a lithographic process, a method of forming a plurality of masks used to manufacture an integrated circuit including a stage of forming a lithographic layer from a plurality of separately printed pattern layers formed with different masks, said integrated circuit including a circuit having a plurality of devices each including one or more structural features formed using said lithographic layer, at least two of said plurality of devices being matched devices such that performance of said circuit is degraded as said matched devices deviate from having matched performance characteristics, said method comprising the steps of: forming data defining one or more dummy structural features; allocating each contact to be formed to a pattern layer; said step of allocating being responsive to a location of said one or more dummy structural features relative to one or more structural features of each of said matched devices so as to force said one or more structural features of each of said matched devices to be formed in a common one of said pattern layers; forming data for controlling formation of said plurality of masks used to print said plurality of pattern layers, each pattern layer including those structural features allocated to said pattern layer; and forming said plurality of masks using said data for controlling formation.