Patent ID: 8607031

Claim:
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, the device comprising: a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units; a task interconnection logic means interconnecting the task units for communicating actions from a source task unit to a destination task unit; and each of the task units including: a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action; a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units; and two configuration registers CONFIG.L and CONFIG.R which are respectively selected by a binary value of a bit L/R of a control/data register of an instance of the algorithm being considered, contents of the configuration registers being loaded at a beginning of the algorithm processing for defining a task to be activated, an action to be performed and an instance to be considered, wherein the control/data register comprises a control field and a data field.