Patent ID: 7932157

Claim:
A method of forming test structures in semiconductor processing, comprising: forming a first test structure comprising a first instance of a first feature formed from a first layer and a first instance of a second feature formed from a second layer over the first layer, the first instance of the first feature aligned in a layer thickness direction with the first instance of the second feature; and forming a second test structure comprising: a second instance of the first feature formed from the first layer, the second instance of the first feature not aligned in a layer thickness direction with an instance of the second feature, and a second instance of the second feature formed from the second layer, the second instance of the second feature not aligned in a layer thickness direction with an instance of the first feature, the second instance of the first feature resulting from a first exposure through a mask comprising a plurality of die columns where the mask is in a first position above the first layer; the first instance of the first feature resulting from a second exposure through the mask where the mask is in a second position above the first layer where the mask is shifted by a distance of all die columns of the mask relative to the first position; the first instance of the second feature resulting from a third exposure through the mask where the mask is in a third position above the first layer where the mask is shifted by a distance of fewer than all die columns of the mask relative to the first position; and the second instance of the second feature is resulting from a fourth exposure through the mask where the mask is in a fourth position above the first layer where the mask is shifted by a distance of more than all die columns of the mask relative to the first position.