Patent ID: 7728566

Claim:
A voltage regulator having a voltage input terminal and a voltage output terminal comprising: a first p-channel MOS transistor and a second p-channel MOS transistor connected in series between the voltage input terminal and the voltage output terminal, the first p-channel MOS transistor having a drain connected to the voltage input terminal and a gate to which a voltage less than or equal to a threshold voltage is applied, the second p-channel MOS transistor having a drain connected to the voltage output terminal; a voltage regulator circuit comprising an operational amplifier, a reference voltage circuit, and a resistance voltage divider, a third p-channel MOS transistor connected to the gate of the first p-channel MOS transistor, and a comparator connected to a gate of the third p-channel MOS transistor, the comparator configured to compare an input voltage from the input voltage terminal with an output voltage from the output voltage terminal, and output a cut-off signal to the gate of the third p-channel MOS transistor when the input voltage is lower than the output voltage, wherein the voltage regulator circuit and the second p-channel MOS transistor are driven by a current flowing through the first p-channel MOS transistor, and wherein the third p-channel MOS transistor is configured to send a signal to the gate of the first p-channel MOS transistor to cut off current flowing between the voltage output terminal and the voltage input terminal upon receiving the cut-off signal from the comparator.