Patent ID: 8645796

Claim:
A computer program product for implementing dynamic pipeline cache error correction, comprising: a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: receiving a request to perform an operation by a read-modify-write pipeline that requires a cache slot, the cache slot residing in a cache, the cache associated with a cache directory; simultaneously accessing, by a read part of the read-modify-write pipeline, a cache slot of the cache and a directory entry associated with the cache, the directory entry located in the cache directory; determining a cache hit for the cache slot based on the simultaneous accessing of the cache and the directory entry associated with the cache, and, based on determining the cache hit: correcting any correctable soft errors associated with the cache slot and the directory entry to produce corrected cache data or corrected directory data; updating, by a write part of the read-modify-write pipeline, the directory entry with the corrected directory data; and based on the corrected cache data being associated with the cache slot, updating, by the write part of the read-modify-write pipeline, the cache slot with the corrected cache data; and based on determining a cache miss for the cache slot based on the simultaneous accessing of the cache and the directory entry associated with the cache: determining whether an error has occurred in the cache directory in a same index as the directory entry and in a second cache slot; and based on determining that an error has occurred in the cache directory in the same index, issuing a read-correct-write operation to the second cache slot corresponding to the same index in which the error occurred.