Patent ID: 6905923

Claim:
A method of manufacturing an integrated circuit, the method comprising: providing a first gate structure and a second gate structure on a semiconductor substrate including a strained semiconductor layer, the first gate structure and the second gate structure each including a first spacer, wherein the first gate structure is provided above a first area of the strained semiconductor layer and the second gate structure is provided above a second area of the strained semiconductor layer; providing a first masking layer above the first area; forming first deep source and drain regions in the strained semiconductor layer in the second area; removing the first masking layer; masking the second area with a second masking layer; selectively providing a second spacer to the first gate structure; and forming second deep source and drain regions in the strained semiconductor layer in the first area after the step of selectively providing a second spacer to the first gate structure; wherein the first gate structure is part of an NMOS transistor and the second gate structure is part of a PMOS transistor.