Patent ID: 7773591

Claim:
An integrated egress/replay memory structure disposed within a network device where the network device has one or more egress pipes with respective reconfigurable egress data bandwidths, said integrated egress/replay memory structure comprising: (a) a first packet data storage area for storing first-time playout data (PdUx) of a first packet that is subject to being played out for a first time from the memory structure for corresponding first time transmission toward a link partner through a corresponding first egress pipe of the network device where the first egress pipe has a configurably defined first egress data bandwidth and where upon being played out from the first storage area for the corresponding first time transmission toward the link partner, the first-time playout data (PdUx) is played out from the first storage area at an average first rate corresponding to the configurably defined first egress data bandwidth; (b) a second packet data storage area for storing second packet data (PdAx) that has been at least once transmitted via the first egress pipe as said first-time playout data (PdUx) but is subject to possibly being replayed through the first egress pipe at least one more time and at said average first rate corresponding to said predefined first egress data bandwidth; and (c) a third packet data storage area for storing third data (PdBx) of one or more packets that have not yet been transmitted wholly as said first-time playout data (PdUx), where the third data (PdBx) can be written and added to the third storage area at an average second rate corresponding to a raceway bandwidth that is no less than a predefined largest configurable value usable in the device for said first egress data bandwidth.