Patent ID: 7268036

Claim:
A method for fabricating a semiconductor device, comprising the steps of: a) forming a first interlevel dielectric film on a semiconductor region; b) forming, in the first interlevel dielectric film, a conductive plug connected to the semiconductor region; c) after the step b, forming, on the first interlevel dielectric film, a second interlevel dielectric film having a first opening in which the conductive plug is exposed; d) forming a conductive oxygen barrier film in the first opening such that the conductive oxygen barrier film fills in the first opening and then planarizing a surface of the second interlevel dielectric film and a surface of the buried conductive oxygen barrier film so that the surfaces will be at substantially the same level; e) forming, on the second interlevel dielectric film, a third interlevel dielectric film having a second opening in which the oxygen barrier film is exposed; f) forming a lower electrode on bottom and wall surfaces of the second opening formed in the third interlevel dielectric film such that the lower electrode is connected to the oxygen barrier film; g) forming a capacitive insulating film on the lower electrode such that the capacitive insulating film follows the lower electrode; and h) forming an upper electrode on the capacitive insulating film such that the upper electrode follows the capacitive insulating film.