Patent ID: 8691644

Claim:
A method of forming a semiconductor device comprising: implanting spaced-apart portions of an n-type single-crystal-silicon substrate region with a p-type dopant; annealing the n-type single-crystal-silicon substrate region implanted with the p-type dopant to form a p-type source region and a p-type drain region that lie spaced apart in the n-type single-crystal-silicon substrate region; after implanting and annealing the n-type single-crystal-silicon substrate region, forming a non-conductive layer that touches an n-channel transistor gate structure and a p-channel transistor gate structure, the n-channel transistor gate structure touching a p-type single-crystal-silicon substrate region, the p-channel transistor gate structure touching the n-type single-crystal-silicon substrate region; implanting spaced-apart portions of the p-type single-crystal-silicon substrate region through the non-conductive layer with an n-type dopant; and forming a stress layer that touches and covers the non-conductive layer after the n-type dopant has been implanted, the stress layer being substantially etch selective to the non-conductive layer.