Patent ID: 7688102

Claim:
A semiconductor circuit comprising: a majority voter circuit configured to generate a selecting signal being indicative of which of a first type and a second type of bits in input data are in a majority, wherein the majority voter circuit includes, an input circuit connected between a first node, a second node and a common node, the input circuit being configured to generate a voltage difference between the first node and the second node based on the input data, and inverted input data, an input weight and an inverted input weight, a switching circuit comprising a first switch that includes a plurality of first switch transistors and a first dummy transistor connected in parallel between the first node and a third node, a second switch connected between the second node and a fourth node, and the switching circuit being configured to receive an amplification weight, the input data, an inverted amplification weight and the inverted input data, and a data amplifying circuit configured to amplify a voltage of the first node in proportion to the received amplification weight and a number of bits of the first type in the input data, and a voltage of the second node in proportion to the inverted amplification weight and a number of bits of the first type in the inverted input data, wherein the data amplifying circuit comprises, a first data amplifier including a plurality of first amplifying transistors and a first amplifying dummy transistor connected in parallel between a first power supply voltage and the third node, gates of the plurality of first amplifying transistors and the first amplifying dummy transistor being connected to a common gate line and connected to a corresponding drain of one of the plurality of first amplifying transistors and the first amplifying dummy transistor, the plurality of first amplifying transistors being activated in response to an activation state of the plurality of first switch transistors, the first amplifying dummy transistor being turned on in response to an activation state of the first dummy transistor.