Patent ID: 8680648

Claim:
A semiconductor device, comprising: a clock tree comprising at least a first functional element and a second functional element formed above a substrate, wherein nodes within the first functional element and the second functional element are electrically connected through a plurality of metal layers; and at least one interconnect structure formed between at least two nodes in the plurality of metal layers, wherein the interconnect structure includes metal lines formed in each of the plurality of metal layers, and wherein the clock tree is fine-tuned by adding or removing parallel functional elements by modifying one of said metal lines in any one of the plurality of metal layers in said at least one interconnect structure, and wherein said metal lines are connected by a plurality of vias, and wherein modifying one of said metal lines in any one of the plurality of metal layers changes an electrical connection between said at least two nodes, and wherein changing the electrical connection modifies operation of the first functional element and the second functional element by connecting or disconnecting the first functional element and the second functional element.