Patent ID: 8451040

Claim:
A logic circuit comprising: a first flip-flop circuit, comprising: a first flip-flop circuit input portion configured to receive a first flip-flop circuit first signal; a first flip-flop circuit storage portion configured to receive a first flip-flop circuit second signal outputted from the first flip-flop circuit input portion; and a first flip-flop circuit output portion configured to receive a first flip-flop circuit third signal outputted from the first flip-flop circuit storage portion; a second flip-flop circuit, comprising: a second flip-flop circuit input portion configured to receive a second flip-flop circuit first signal; a second flip-flop circuit storage portion configured to receive a second flip-flop circuit second signal outputted from the second flip-flop circuit input portion; and a second flip-flop circuit output portion configured to receive a second flip-flop circuit third signal outputted from the second flip-flop circuit storage portion, and a load unit, comprising: a first logical gate configured to receive a first flip-flop circuit fourth signal outputted from the first flip-flop circuit output portion; and a second logical gate configured to receive a second flip-flop circuit fourth signal outputted from the second flip-flop circuit output portion, wherein the load unit performs a first NOT operation with respect to the first flip-flop circuit fourth signal, wherein an OR operation is performed on a result of the first NOT operation and the second flip-flop circuit fourth signal, wherein a second NOT operation is performed on a result of the OR operation, wherein a NAND operation is performed on a result of the second NOT operation and first flip-flop circuit fourth signal, and wherein a result of the NAND operation provides an output signal of the load circuit.