Patent ID: 7067375

Claim:
A method for fabricating a non-volatile memory, the method comprising: providing a substrate, and sequentially forming a dielectric layer, a conductive layer, and a mask layer on the substrate; pattering the mask layer, the conductive layer, and the dielectric layer to form a plurality of first openings exposing the substrate; forming a buried bit line in the substrate at the bottom of each first opening; forming an isolation layer in the first openings on the substrate; removing part of the isolation layer, and forming a plurality of second openings by using the remained isolation layers as a mask; removing the isolation layers covered on the mask layer and the mask layer; forming a tunneling dielectric layer, a charge trapping layer, and a barrier dielectric layer sequentially on the substrate, so as to jointly cover the second openings, the isolation layer and the conductive layer; filling a material layer into the second openings; removing parts of the tunneling dielectric layer, the charge trapping layer, and the barrier dielectric layer not covered by the material layer; removing the material layer; and forming a word line on the substrate.