Patent ID: 8497789

Claim:
A system for error correction of a pipeline analog to digital converter (“ADC”), wherein the pipeline ADC converts a voltage signal to a digital version of the voltage signal, comprising: a coarse ADC wherein an input terminal of the coarse ADC receives the voltage signal and a reference signal and provides a digital version of the voltage signal value relative to the reference signal to a digital to analog converter (“DAC”) input terminal; a first adder for combining the voltage signal and an output signal from the DAC, wherein the first adder result is provided to a residue amplifier; a backend ADC, wherein the backend ADC provides a digital version of an output voltage signal received from the residue amplifier; a second adder for summing digital values received from the coarse ADC, a digital to analog converter noise cancellation (“DNC”) circuit, and a harmonic distortion correction (“HDC”) circuit, thereby providing a pipelined ADC output; a circuit for estimating distortion parameters from the residue amplifier and digital to analog converter comprising: the HDC, wherein the HDC, responsive to the pipelined ADC output, corrects distortion components due to the residue amplifier present in the digital signal from the backend ADC; and the DNC circuit, wherein the DNC circuit, responsive to the pipelined ADC output, corrects the distortion components due to the DAC present in the digital signal from the backend ADC; and a circuit for modifying the reference signal to the coarse analog to digital converter.