Patent ID: 7440348

Claim:
A memory array ( 14 ) for an integrated circuit ( 10 ) comprising: A) a plurality of memory elements ( 18 , 20 ) including at least one redundant memory element ( 20 ) for exchanging with a failed memory element in the plurality of memory elements; and B) a failing address repair register ( 16 ) including: 1) a register ( 26 ) for controlling enablement of a corresponding redundant memory element ( 20 ), wherein each register includes: a) a set of address bits (A 0 -An) for containing an address location of a failing memory element to be replaced by a redundant memory element; b) an enable bit (EN) for controlling whether the memory element whose address location is contained in the address bits is to be exchanged with a corresponding redundant memory element; c) a bad-redundancy bit (BR) for disabling the enable bit; d) a temporary enable bit (TE) for holding a value to be loaded into the enable bit in response to a timing-controlled load-enable signal; and e) a temporary bad-redundancy bit (TB) for holding a value to be loaded into the bad-redundancy bit in response to the timing-controlled load-enable signal; and 2) compare logic ( 30 ) for determining whether an address of a failing memory element is stored in the register.