Patent ID: 6934895

Claim:
An I/O compression circuit for a semiconductor memory device, comprising: a command decoder adapted to combine external control signals and output a test mode command; a test mode control unit adapted to generate a compress signal for controlling a compress operation and a compress mode signal for distinguishing a first compress mode in which identical data are transmitted to data transmission lines from second compress mode in which different data are transmitted to adjacent data transmission lines according to the test mode command and addresses; a mode decoder adapted to decode the compress signal and the compress mode signal and to output a same compress signal for controlling the compress operation in a first compress mode and a different compress signal for controlling the compress operation in the second data compress mode; an input unit adapted to decode input data input inputted via I/O data pins, transmit the input data to data transmission lines in a normal mode, transmit the same data inputted via the I/O data pins to the data transmission lines in the first compress mode and alternately invert the input data to transmit different data to the adjacent data transmission lines in the second compress mode based on the compress signal, the same compress signal and the different compress signal; and an output unit adapted to drive the data transmitted through the data transmission lines and output the data to the I/O data pins in the normal mode, test the data transmitted through the data transmission lines in the first compress mode according to the compress signal and the compress mode signal, and re-invert the inverted data among the data transmitted through the data transmission lines, and test the data in the second compress mode.