Patent ID: 8924828

Claim:
A memory controller controlling a memory, comprising: an encoding unit which encodes user data into code word which have the ability to correct t erroneous bits, wherein t is an integer equal to or greater than 2; a syndrome calculation unit which computes syndrome based on the code word read from the memory; an error locator polynomial calculation unit which derives an error locator polynomial from the syndrome; and a Chien search unit which identifies all roots of the error locator polynomial, wherein the Chien search unit includes: a root shift block which shifts all roots of the error locator polynomial; a division block which divides the output polynomial from the root shift block by a predetermined polynomial, of which the order is smaller than t; and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements.