Patent ID: 7904842

Claim:
A processor-implemented method for modifying a first implementation of a logic description that has first and second signals respectively coupled to first and second inputs of a plurality of inputs of a fanout-free cone that converges at an output, the first implementation of the logic description having a plurality of primary inputs and a plurality of primary outputs, the processor-implemented method comprising: in at least one programmed processor, performing steps including: for the fanout-free cone, determining a swap function of the inputs of the fanout-free cone, the swap function indicating whether there is a difference at the output of the fanout-free cone between the fanout-free cone with the first and second signals respectively coupled to the first and second inputs and the fanout-free cone with the first and second signals respectively coupled to the second and first inputs; for the logic description, determining a do-not-care function of the inputs of the fanout-free cone, the do-not-care function indicating that a modification of the output of the fanout-free cone is not observable at the primary outputs of the logic description, wherein the do-not-care function is a complete do-not-care function; and outputting, in response to the do-not-care function covering the swap function, a second implementation of the logic description that has the first and second signals respectively coupled to the second and first inputs of the fanout-free cone.