Patent ID: 7426006

Claim:
A thin film transistor array substrate, comprising: a substrate; a plurality of scan lines disposed over the substrate; a plurality of data lines disposed over the substrate, wherein the scan lines and the data lines together define a plurality of pixel areas; a plurality of thin film transistors with each thin film transistor disposed inside one of the pixel areas, wherein each thin film transistor is driven by one of the scan lines; a plurality of pixel electrodes with each pixel electrode disposed inside one of the pixel areas and electrically connected to one of the thin film transistors wherein each pixel electrode has at least a first slit and at least a second slit with the second slit extending in a direction different from the first slit but connected with the first slit; a plurality of common lines disposed over the substrate, wherein the portion area of each pixel electrode is disposed above one of the common lines and the connecting area between the first and the second slit of each pixel electrode disposed above the corresponding common line; and an upper electrode disposed between each pixel electrode and one of the common lines, wherein the portion area of the upper electrode is electrically connected to one of the pixel electrodes.