Patent ID: 7829357

Claim:
A method, comprising: forming a first metallization layer of a test area for a semiconductor device on the basis of a first set of design rules for a device region of said semiconductor device; forming a metal region in said first metallization layer on the basis of design rules that violate said first set of design rules; generating a recessed surface area in said first metallization layer by performing a first chemical mechanical polishing process on said first metallization layer to remove excess metal of said metal region; forming a first metal region and a second metal region in a first leakage area of a second metallization layer formed on said first metallization layer by filling openings in said leakage area with a metal and removing excess metal by performing a second chemical mechanical polishing process, said leakage area being aligned to said recessed surface area; and evaluating said second chemical mechanical polishing process by determining a leakage current between said first and second metal regions.