Patent ID: 8743930

Claim:
A system having a feedback loop, the feedback loop comprising: an interference suppression module comprising an inter-cell interference suppression module to suppress inter-cell interference, the interference suppression module further comprising an intra-cell interference suppression module to suppress intra-cell interference; a pre-equalization (pre-EQ) module coupled to an output of the interference suppression module; a chip equalization (chip-EQ) weight calculation module coupled to an output of the pre-EQ module; a delay match module coupled to the output of the pre-EQ module; a chip-level equalization (chip-EQ) module coupled to an output of the chip-EQ weight calculation module, the chip-EQ module further being coupled to an output of the delay match module; a downlink shared channel (DSCH) despreader coupled to an output of the chip-EQ module; a shared control channel (SCCH) despreader coupled to an output of the chip-EQ weight calculation module; and a high-speed (HS) shared control channel (SCCH) decoding module coupled to an output of the SCCH module, wherein an output of the HS-SCCH decoding module is coupled to the DSCH module, wherein the output of the HS-SCCH is further coupled to the interference suppression module.