Patent ID: 6895548

Claim:
A semiconductor testing apparatus for supplying a test input signal to a semiconductor device as a testing target and receiving an output signal from the semiconductor device, comprising: a test program memory section configured to store a test program including at least a wait time for testing the semiconductor device; a measuring/deciding section, connected to the test program memory section, for receiving the test program stored in the test program memory section, for supplying the test signal to the semiconductor device in accordance with the test program having the wait time set to a predetermined value, and for detecting an optimal value of the wait time through a series of processes comprising measuring, after elapse of the wait time, the electrical characteristics of the semiconductor device on the basis of the response signal outputted from the semiconductor device; making an OK/NG decision on the electrical characteristics of the semiconductor device on the basis of the measurement results; if the decision is “NG”, remeasuring the electrical characteristics of the semiconductor device under a newly set wait time; for each newly set wait time, performing the remeasuring operation on the electrical characteristics of the semiconductor device until the result of a decision is “OK”; and initiating the next measuring operation when the result of that decision is “OK”; and a wait time initializing/changing control section, connected to the measuring/deciding section; for receiving the result of the OK/NG decision from the measuring/deciding section after an initialization of the wait time included in the test program; and for controlling the measuring/deciding section to, if the result of the OK/NG decision is “NG”, repeat the setting of the wait time to sequentially increment the wait time toward an initially determined maxima/value until the result of the decision is “OK” and, if the result of the decision is “OK”, terminate the setting of the wait time.