Patent ID: 7655503

Claim:
A method for fabricating a semiconductor package with stacked chips, comprising the steps of: preparing a lead frame having a plurality of leads and supporting extensions; preparing at least one preformed package having an active surface and a non-active surface, including the steps of: mounting at least a first chip on a substrate, electrically connecting the first chip to the substrate, and packaging the first chip and the substrate to form the preformed package; attaching the non-active surface of the preformed package to the plurality of supporting extensions of the lead frame; mounting at least a second chip on the active surface of the preformed package, wherein the active surface of the preformed package is a surface of the substrate free of being mounted with the first chip; electrically interconnecting the lead frame, the preformed package and the second chip via a plurality of bonding wires; and forming an encapsulant for encapsulating the preformed package, the second chip, the bonding wires and a portion of the lead frame.