Patent ID: 8787086

Claim:
A system comprising: solid state memory circuitry comprising a plurality of memory banks, which are associated with a plurality of memory accesses, and adapted to receive a plurality of sets of gated address signals, such that each set of gated address signals is associated with a corresponding one of the plurality of memory banks; and bank selection and address gating circuitry adapted to: during each memory access, receive a first clock signal having: a first phase; a second phase following the first phase; and a first transition at the end of the first phase and at the beginning of the second phase; receive a first plurality of address signals, which are stable during the first transition; and provide the plurality of sets of gated address signals, such that: each gated address signal of the plurality of sets of gated address signals does not transition during the first phase; one of the plurality of sets of gated address signals is associated with a selected one of the plurality of memory banks and is based on the first plurality of address signals during the first transition; and a balance of the plurality of sets of gated address signals is associated with unselected memory banks, such that each gated address signal of the balance of the plurality of sets of gated address signals is prevented from transitioning; wherein the one of the plurality of sets of gated address signals provides an address associated with the each memory access.