Patent ID: 8456223

Claim:
An integrated circuit comprising: a main power rail; a virtual main power rail connected to said main power rail by one or more first operational mode transistors and one or more first retention mode transistors; a ground power rail; a virtual ground power rail connected to said ground power rail by one or more second operational mode transistors and one or more second retention mode transistors; combinatorial logic circuitry connected between said virtual main power rail and said virtual ground power rail; signal value storage circuitry connected between one of: (a) said main power rail and said virtual ground power rail; and (b) said virtual main power rail and said ground power rail; and power control circuitry coupled to and configured to control said one or more first operational mode transistors, said one or more first retention mode transistors, said one or more second operational mode transistors and said one or more second retention mode transistors such that: (i) in an operational mode said one or more first operational mode transistors and said one or more second operational mode transistors are in a low impedance state to provide an operating voltage difference sufficient to support data processing operations and signal value retention across said combinatorial logic circuitry and said signal value storage circuitry; (ii) in a retention mode said one or more first operational mode transistors and said one or more second operational mode transistors are in a high impedance state and said one or more first retention mode transistors and said one or more second retention mode transistors are in a low impedance state to provide a low power voltage difference insufficient to support data processing operations across said combinatorial logic circuitry and a retention voltage difference greater than said low power voltage difference and sufficient to support signal value retention across said signal value storage circuitry; and (iii) in a power off mode said one or more first operational mode transistors, said one or more second operational mode transistors, said one or more first retention mode transistors and said one or more second retention mode transistors are in a high impedance state to provide a power off voltage difference insufficient to support data processing operations and signal value retention across said combinatorial logic circuitry and said signal value storage circuitry.