Patent ID: 8516491

Claim:
A processing load distribution method in a multi-core processor having a plurality of cores, comprising: forming a plurality of basic modules, including processing contents required for the overall processor being divided into minimum configuration units each having a unified input/output format interface; as initial allocation, allocating in distribution the plurality of basic modules to the plurality of cores; and subsequently, based on functional information of the each core, relocating by respective cores, the plurality of initially allocated basic modules either periodically or at appropriate timing, wherein the functional information of each core is information obtained from the functions of: i) counting the number of signals requested to the self-core and the number of signals being output from the self-core to other cores; ii) measuring a reception buffer storage capacity and a transmission buffer storage capacity incorporated in the self-core; and iii) measuring the number of queues requested to the self-core and the number of queues requested to other cores.