Patent ID: 8772880

Claim:
A semiconductor integrated circuit device comprising: a common source region; N (N≧1) first gate layers and M (M≧1) third gate layers arranged so as to extend in a first direction and align sequentially starting from the common source region toward a second direction which is orthogonal to the first direction; N second gate layers and M fourth gate layers arranged so as to extend in the first direction and align sequentially starting from the common source region toward a third direction which is parallel, and opposite, to the second direction; a first diffusion layer which is arranged between the N first gate layers and the M third gate layers and which serves as a shared diffusion layer between the N first gate layers and the M third gate layers; a third diffusion layer which faces the first diffusion layer such that the M third gate layers are interposed therebetween; a second diffusion layer which is arranged between the N second gate layers and the M fourth gate layers and which serves as a shared diffusion layer between the N second gate layers and the M fourth gate layers; and a fourth diffusion layer which faces the second diffusion layer such that the M fourth gate layers are interposed therebetween, wherein the N first gate layers are gate fingers of a first MIS transistor and take a first differential input signal as an input, the N second gate layers are gate fingers of a second MIS transistor and take a second differential input signal as an input, the first diffusion layer is a drain of the first MIS transistor, the second diffusion layer is a drain of the second MIS transistor, and both of the third and the fourth diffusion layers are unconnected.