Patent ID: 8184227

Claim:
A flat display panel, comprising: a substrate, a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region arranged as an array being defined on the substrate, the first pixel region and the second pixel region being arranged along a horizontal direction, the third pixel region and the fourth pixel region are respectively disposed on an underside of the first pixel region and the second pixel region and adjacent to the first pixel region and the second pixel region; a first downside sub-pixel, a second downside sub-pixel, a third upside sub-pixel, and a fourth upside sub-pixel respectively positioned in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region; a first data line and a second data line, arranged on the substrate along a vertical direction, positioned on two sides of the first pixel region and the third pixel region respectively; a third data line and a fourth data line disposed on the substrate along the vertical direction, positioned at two sides of the second pixel region and the fourth pixel region respectively, the second data line and the third data line being disposed between the first pixel region and the second pixel region; a first scan line and a second scan line disposed on the substrate and extending along the horizontal direction, the first scan line passing through the first pixel region and the second pixel region, and the second scan line passing through the third pixel region and the fourth pixel region; a first common electrode line, extending along the horizontal direction and passing through the first pixel region and the second pixel region; a second common electrode line, extending along the horizontal direction and passing through the third pixel region and the fourth pixel region; a first bridge line, disposed between the first common electrode line and the second common electrode line in the first pixel region and the third pixel region and electrically connected to the first common electrode line and the second common electrode line; and a second bridge line, disposed between the first common electrode line and the second common electrode line in the second pixel region and the fourth pixel region and electrically connected to the first common electrode line and the second common electrode line.