Patent ID: 8461890

Claim:
A phase and/or frequency detector, comprising: a first flip-flop having a first data-input terminal, a first data-output terminal, a first clock-input terminal and a first reset terminal, the first data-input terminal being electrically coupled to a power source, and the first clock-input terminal being configured for receiving a reference signal with a reference frequency; a second flip-flop having a second data-input terminal, a second data-output terminal, a second clock-input terminal and a second reset terminal, the second data-input terminal being electrically coupled to the power source, the second clock-input terminal being configured for receiving a frequency-divided signal, and the frequency-divided signal being generated by performing a frequency-divided operation on an oscillating signal with an oscillating frequency; a logic gate configured for receiving signals outputted from the first data-output terminal and the second data-output terminal; a control circuit configured for generating a delay control signal according to the oscillating frequency of the oscillating signal; and a delay circuit configured for altering a prolonged period according to the delay control signal to generate a reset signal to be outputted to the first reset terminal and the second reset terminal.