Patent ID: 7197682

Claim:
A semiconductor test equipment for testing DUT, comprising: a timing generator (TG); a waveform formatting unit (FC); a pattern generator (PG); n level comparison circuits, n being more than one and corresponding to a number of comparator channels included in said semiconductor test equipment; n timing comparison circuits; n primary logical comparison circuits; and n secondary logical comparison circuits, wherein for a DUT output signal containing jitter output from said device under test, two defined times are measured and determined to be good or not simultaneously without being affected by said jitter component, and wherein said secondary logical comparison circuit comprises a data shifting flip-flop for shifting input data with a reference clock of said semiconductor test equipment by a period of one clock, said semiconductor test equipment comprises a first logical comparison and selection circuit for determining whether timings of a first defined time that is a period between two pre-selected edges are good or not, and outputting a determination result, and a second logical comparison and selection circuit for determining whether timings of a second defined time that is a period between two pre-selected edges are good or not, and outputting a determination result, and said first and second defined times are determined to be good or not, without being affected by said jitter component contained in said DUT output signal.