Patent ID: 7202163

Claim:
A method of forming a local interconnection wire, comprising: forming, on an insulation film, a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with the insulation film, and that simultaneously has a length equal to or shorter than a length between outer ends of the adjacent gate electrodes; etching the insulation film exposed in the first etching mask pattern so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern; removing the first etching mask pattern; forming a second etching mask pattern so as to partially expose the insulation film provided within the recess pattern; performing an etching to form apertures for exposing a partial surface of the gate electrodes; removing the second etching mask pattern; and filling the recess pattern and the apertures with conductive material to form a local interconnection layer for connecting between the gate electrodes.