Patent ID: 7446277

Claim:
A testing method for an integrated circuit of an integrated circuit device of a plurality of integrated circuit devices comprising: establishing an enhanced reliability testing flag for an integrated circuit device resulting from fabrication errors and manufacturing deviations from a manufacturing process for an integrated circuit device of a plurality of integrated circuit devices; storing an enhanced reliability testing flag in the integrated circuit device associated with a unique identification code of each integrated circuit device of the plurality of integrated circuit devices for indicating whether each integrated circuit device requires enhanced reliability testing; automatically reading the unique identification code of each integrated circuit device of the plurality of integrated circuit devices when each integrated circuit device of the plurality of integrated circuit devices forms a portion of a wafer; accessing the enhanced reliability testing flag stored for the unique identification code of each integrated circuit device of the plurality of integrated circuit devices; sorting the plurality of integrated circuit devices in accordance with whether their enhanced reliability testing flag indicates they are in need of the enhanced reliability testing; and performing the enhanced reliability testing for each integrated circuit device of the plurality of integrated circuit devices requiring the enhanced reliability testing.