Patent ID: 8023314

Claim:
An apparatus for selecting a word line and writing to memory cells in a dynamic random access memory (DRAM), the apparatus comprising: a level shifter circuit including at least first and second transistors having their respective sources directly connected to a controlled high supply voltage level Vpp supplied from a high voltage supply, the level shifter circuit being configured to: respond to a decoded address input signal selectively having logic voltage levels that are less than the controlled voltage level Vpp, the drain of the first transistor being configured to apply current to a first node, the drain of the second transistor being configured to apply current to a second node, the first and second transistors being gated from the second and first nodes, respectively, and produce a control signal selectively having the controlled high supply voltage level Vpp or a Vss voltage level; and a driving circuit to drive a selected word line to the controlled high supply voltage level Vpp in response to the control signal to write a logic voltage level in a DRAM cell storage capacitor associated with the selected word line.