Patent ID: 6982912

Claim:
A semiconductor memory device comprising: a plurality of word lines including one or more redundant word lines; a plurality of pairs of bit lines; a plurality of memory cells connected to said plurality of word lines and said plurality of pairs of bit lines; a plurality of word-line drivers, each of which is connected to one end of each of said plurality of word lines and controlled by a plurality of word-line control signals; and a plurality of first word-line control circuits respectively located at the other ends of said plurality of word lines, each of said plurality of first word-line control circuits receiving a signal level of a corresponding one of said plurality of word lines, wherein in the case where the signal level of said corresponding word line is a first level at which corresponding ones of said plurality of memory cells connected to said corresponding word line go into a high impedance state, each of said plurality of first word-line control circuits switches to a conducting state and outputs a signal of said first level to said corresponding word line, and in the case where the signal level of said corresponding word line is a second level at which said corresponding memory cells go into a state wherein data input/output is performed, each of said plurality of first word-line control circuits switches to a non-conducting state.