Patent ID: 8584073

Claim:
A method for developing a scan-based test design for an integrated circuit design, comprising the steps of: developing a plurality of candidate test designs for the circuit design, including using a computer system, generating a plurality of test vectors in dependence upon the circuit design; using a computer system, generating a test protocol figure of merit for each of the candidate test designs; and selecting, in dependence upon a comparison among the test protocol figures of merit generated for each of the candidate test designs, one of the candidate test designs for implementation in an integrated circuit device, wherein the step of generating a plurality of test vectors employs a predetermined automatic test pattern generation algorithm, and wherein the step of generating a test protocol figure of merit for each of the candidate test designs comprises the step of determining the test protocol figure of merit for each particular candidate test design using at least one but not all of the test vectors that would be generated if the predetermined automatic test pattern generation algorithm were run to completion.