Patent ID: 7930672

Claim:
A system for incrementally reducing a circuit design, said system comprising: means, responsive to receiving a circuit design and a property for logical verification with respect to said circuit design, for reducing said circuit design to create a reduced circuit design, said means for reducing includes means for re-encoding a portion of said circuit design by replacing the fan-in side of a cut with equivalent logic of reduced size and means for overapproximating said circuit design by injecting cutpoints in parallel; means for determining whether a valid solution for said property on said reduced circuit design can be generated, wherein said valid solution is a valid result of combinational logic irrespective of any physical layout of said circuit design; means for replacing said circuit design with said reduced circuit design; means, until said valid solution can be generated, for repeating said reducing, determining and replacing; and means, responsive to generating said valid solution, outputting said valid solution from said data processing system.