Patent ID: 8438521

Claim:
A system comprising: a processor configured on a programmable chip, the processor including: a plurality of functional units arranged to perform a plurality of different operations; a processor functional unit operable to calculate a first set of states for all of the functional units based on a first program, wherein the processor functional unit is arranged to output specific one or more states from the first set of states to specific one or more functional units from the functional units to thereby control specific one or more operations from the different operations; a program memory that is programmed with the first program, wherein the program memory is further programmable with a second program to replace the first program for execution to cause the processor functional unit to calculate a second plurality of states differing from the first set of states, wherein the processor functional unit is arranged to output specific one or more states from the second set of states to specific one or more functional units from the functional units to thereby control specific one or more operations from the different operations; and a plurality of registers operable to store the first or second set of states, wherein the plurality of functional units are located outside said processor functional unit.