Patent ID: 7361596

Claim:
A semiconductor processing method, comprising: providing a substrate having a patterned second composition over a silicon-containing first composition; the second composition having one or more openings extending therethrough to substantially expose one or more silicon-containing surfaces of the first composition: forming titanium silicide along the first composition within the one or more openings; the formation of the titanium silicide occurring in a reaction chamber and comprising at least two iterations of the following sequence in the following order: providing at least one titanium halide in the reaction chamber in the substantial absence of one or more hydrogen-containing reductants to selectively form a titanium-containing layer on the one or more silicon-containing surfaces first composition relative to the second composition; purging substantially all of any unreacted titanium halide from the reaction chamber; and providing the one or more hydrogen-containing reductants in the reaction chamber and utilizing such reductants to form titanium silicide from titanium of the titanium-containing layer and silicon of the one or more silicon-containing surfaces; and wherein an earlier of the at least two iterations has a shorter exposure of the substrate to the titanium halide and longer exposure of the substrate to the one or more hydrogen-containing reductants than a later of the at least two iterations; the earlier of the at least two iterations forming a first portion of the titanium silicide, said first portion being substantially entirely in the C-54 phase and thus being a C-54 phase template; the later of the at least two iterations forming a second portion of the titanium silicide, and comprising conditions less conducive to forming the C-54 phase than the earlier of the at least two iterations; the second portion being substantially entirely in the C-54 phase due, at least in part, to the C-54 phase being induced from the C-54 phase template.