Patent ID: 7208323

Claim:
A method for fabricating a magneto-resistive memory cell in an integrated circuit, comprising: forming a free magnetic layer having a first widened end-portion at a first end of the free magnetic layer and a second widened end-portion at a second end of the free magnetic layer opposite to the first end of the free magnetic layer; forming a pinned magnetic layer having a third widened end-portion at a first end of the pinned magnetic layer and a fourth widened end-portion at a second end of the pinned magnetic layer opposite to the first end of the pinned magnetic layer; setting magnetization orientions of the first and third widened end-portions antiparallel; magnetically coupling the first and third widened end-portions; setting magnetization orientions of the second and fourth widened end-portions antiparallel; and magnetically coupling the second and fourth widened end-portions, wherein a first minimum magnitude of an applied magnetic field for switching the magneto-resistive memory cell from a low resistance state to a high resistance state is about 80–120 percent of a second minimum magnitude of an applied magnetic field for switching the magneto-resistive memory cell from the high resistance state to the low resistance state.