Patent ID: 7614022

Claim:
An apparatus for testing for bridge faults in nets of a programmable integrated circuit, the apparatus comprising: a plurality of nets organized in groups; function generators configured as clocked shift registers such that each of the plurality of nets is sourced by a function generator, wherein for each net group: shift registers coupled to nets in the net group are initialized identically to one value; shift registers coupled to nets in the net group are initialized to a different unique value than shift registers coupled to nets in other net groups; and each shift register in the net group stores one bit with a value of one and with zeros in all other bits so that when clocked, each shift register provides a single one on one clock cycle and provides zeros in all other clock cycles; and a test device to couple to net groups to test the net groups after each clock cycle, such that the test device provides an indication when a short is detected between net groups.