Patent ID: 7486688

Claim:
A method of accessing Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) memory storage employed in a packet switch, the DDR SDRAM memory having a plurality of memory banks for storing packet data of a plurality of packets, the method comprising steps of: a. segmenting packet data into variable size burst units; b. sequencing a plurality of burst unit memory write operations ensuring that each burst unit memory write operation writes packet data to a memory bank different from the previous burst unit memory write operation; c. sequencing a plurality of burst unit memory read operations ensuring that each bust unit memory read operation reads packet data from a memory bank different from the previous burst unit memory read operation; d. arranging the plurality of sequenced burst unit memory write operations in a plurality of write windows; e. arranging the plurality of sequenced bust unit memory read operations in a plurality of read windows; and f. performing memory access operations interleaving the write windows with the read windows.