Patent ID: 7209384

Claim:
A random access memory, comprising: memory cell, wherein a capacitor stores data and a diode controls to store data “1” (on) or “0” (off); and the diode, wherein includes four terminals, the first terminal is p-type and serves as a word line, the second terminal is n-type and serves as a storage node, the third terminal is p-type and floating, and the fourth terminal is n-type and serves as a bit line; and plate of capacitor couples to the second terminal, which plate has no coupling region to first, third and fourth terminal; and the diode is planar type which is horizontally formed on the surface of the wafer; capacitor is formed on the second terminal of the diode by adding insulator between the second terminal and the plate, thus the height of the memory cell is almost same as that of MOS transistor in the chip; and pull-down transistor, wherein is connected to the fourth terminal of the diode through the bit line, and the pull-down transistor sustains the current path from the word line through the diode when the storage node voltage is lower than the word line voltage minus built-in voltage of the diode, which establishes the forward bias from the word line (first terminal) to the storage node (second terminal) by asserting the word line, thus the forward bias turns on the diode and sets up the current path from the word line to the pull-down transistor, as a result the diode generates a current flow, which is data “1” as a current output, and when the storage node voltage is higher than the word line voltage, the forward bias is not established from the word line to the storage node, as a result the diode does not generate a current flow through the pull-down transistor, which is data “0” with no current output.