Patent ID: 7096470

Claim:
Apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure comprising: a first tier thread state storage for storing a limited number of runnable thread register states; a second tier thread storage facility for storing a second number of thread states; said second number of thread states being greater than the limited number of runnable thread register states; each stored thread state including predefined selection data; said predefined selection data including predefined historical thread usage data; said predefined selection data includes processor cycle usage efficiency data for each specific thread; said processor cycle usage efficiency data including a ratio of latency events per processor cycle, where a higher ratio indicates more inefficiency of historical thread use of a processor; and a runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility using said stored predefined selection data.