Patent ID: 7162705

Claim:
A method comprising: designing a clock distribution tree for a plurality of circuit components on an integrated circuit to achieve a predetermined clock skew across combinable circuit components of the plurality of circuit components and component blocks of the combinable circuit components; determining if the integrated circuit is functional in view of the clock skew, for at least one of the combinable circuit components, generating a master clock signal and at least one other clock signal transmitted through the clock distribution tree to the circuit component, the circuit component receiving the master clock signal at a first component block of the circuit component; defining two signal paths including a default path and a bypass path, wherein defining the bypass path includes allowing a second component block of the circuit component to receive the master clock signal and defining the default path includes allowing the second component block of the circuit component to receive the circuit component clock signal; and wherein during functionality testing, the integrated circuit is tested to determine if the integrated circuit functions utilizing the bypass path, and, if so, the bypass path is selectable such that the first and second component blocks of the circuit component are controlled by a common clock domain in response to the master clock signal so that signals can be passed between the first and second component blocks.