Patent ID: 8255618

Claim:
A memory controller for controlling operation of a data storage device, the memory controller comprising: a queue arbiter configured to obtain, from a host device, memory operation commands for execution by the data storage device; a command dispatcher operationally coupled with the queue arbiter, the command dispatcher being configured to: receive the memory operation commands from the queue arbiter in a same order as obtained by the queue arbiter from the host device; separately and respectively queue the memory operation commands for each of a plurality of memory devices; and dispatch the memory operation commands for execution by the plurality of memory devices; a plurality of command queues operationally coupled with the command dispatcher, each command queue being associated with a respective one of the plurality of memory devices and configured to: receive the dispatched memory operation commands corresponding with its respective memory device from the command dispatcher in a same order as received by the command dispatcher; and provide the received memory operation commands to its respective memory device in a first-in-first-out order.