Patent ID: 7986001

Claim:
A semiconductor memory device, comprising: a plurality of transistors having a stacked-gate structure, each transistor including: a semiconductor substrate, a gate insulator formed on said semiconductor substrate, a lower gate formed on said semiconductor substrate with said gate insulator interposed, an intergate insulator formed on said lower gate, and an upper gate formed and silicided on said lower gate with said intergate insulator interposed, wherein at least one of said transistors further includes: an aperture formed through said intergate insulator to connect said lower gate with said upper gate, a silicide suppression region between said aperture and said gate insulator to suppress diffusion of metal atoms from said silicided upper gate, and a silicide formation region provided in a first portion of said lower gate below said aperture, a side surface of said silicide formation region in said lower gate being in direct contact with a second portion of said lower gate and being electrically connected to said second portion of said lower gate, and said silicide suppression region being formed in a base of said silicide formation region.