Patent ID: 8722443

Claim:
A method for fabricating an integrated circuit (IC), the method comprising: forming an IC body comprising at least one base layer, at least a first upper layer disposed on said base layer, and at least a second upper layer disposed on said first upper layer, wherein said at least a portion of said second upper layer comprises at least one planar inductive element formed of a conductive material so as to be substantially parallel to said base layer and having a first contacting end and a second contacting end; and forming at least one cavity region in said IC body to expose said planar inductive element, said cavity region extending through at least said base layer, said first upper layer, and at least a portion of said second upper layer; wherein said forming offset at least one cavity region defines at least one support member formed of a dielectric material so as to be horizontally elongate and so as to extend horizontally across at least a portion of said cavity region from said IC body in at least a first direction parallel to said base layer; and wherein at least a portion of said support member is in direct contact with adjacent intermediary portions of at least first and second windings defining said planar inductive element which reside between the first and second contacting ends, whereby the planar inductive element is suspended within the cavity region.