Patent ID: 8072721

Claim:
A capacitivly-coupled electro-static-discharge (ESD) protection circuit comprising: core circuitry having transistors that use a minimum transistor gate length and drive an internal node; an output transistor having a gate driven by the internal node from the core circuitry; an output pad on a pad node connected to a source/drain of the output transistor; an ESD coupling capacitor coupled between the pad node and a coupled-gate node; a gate-grounding transistor having a gate connected to the coupled-gate node and a source/drain connected to the internal node; and a disabling transistor having a source/drain connected to the coupled-gate node, for driving a disabling voltage onto the coupled-gate node when power is applied; wherein the disabling voltage disables the gate-grounding transistor from conducting current from the internal node; wherein the gate-grounding transistor turns on to shunt charge coupled across a parasitic Miller capacitance of the output transistor when an ESD is applied to the pad node, whereby ESD protection of the core circuitry is provided.