Patent ID: 7953992

Claim:
A system in package (SIP) semiconductor device comprising a plurality of chips including a first chip and a second chip, wherein each of the chips includes: an alive block continuously supplied with power in order to continuously be in an on-state; a local interface transmitting data to the other chips or receiving data from the other chips; and an intellectual property (IP) block individually storing or processing data, wherein the alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips, and the alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or a signal transmitted through the first signal line unit, wherein the local interfaces of the chips are connected to each other through a second signal line unit; wherein the alive block of the first chip comprises a real time clock (RTC) outputting an RTC signal for providing state information by counting a period of the RTC signals; and wherein when an external instruction signal is transmitted to the alive block of the first chip for waking up the chips, the alive block of the first chip transmits a power-on signal to the alive block of the second chip through a second signal line of the first signal line unit.