Patent ID: 7488691

Claim:
A method of fabricating a semiconductor device including forming, in an insulating film formed on a semiconductor substrate, an interconnect pattern with a predetermined geometry, using a multi-layered resist film containing at least a lower resist film and a silicon-containing film, comprising: judging whether an interconnect pitch of an interconnect pattern having the smallest interconnect pitch out of all interconnect patterns to be formed in said insulating film is not larger than a predetermined value or not; if said smallest interconnect pitch is judged as being not larger than a predetermined pitch, in said judging whether said interconnect pitch is not smaller than a predetermined value or not, determining the thickness of said lower resist film corresponding to said smallest interconnect pitch; forming said lower resist film having said thickness on said insulating film; forming said silicon-containing film on said lower resist film; patterning said silicon-containing film according to said predetermined geometry; patterning said lower resist film through said silicon-containing film used as a mask; and patterning said insulating film through said lower resist film used as a mask.