Patent ID: 7605461

Claim:
A chip package structure, comprising: a circuit pattern; a frame, surrounding the circuit pattern; a first adhesive layer, formed on the circuit pattern and the frame to fasten the circuit pattern and the frame together and exposing a part of the circuit pattern; a plurality of leads, disposed around the circuit pattern; an insulating adhesive layer, disposed between the leads and the frame to attach the leads to the frame; a chip, mounted upon the circuit pattern with the first adhesive layer, the chip having a plurality of bonding pads; a plurality of first bonding wires, electrically connecting the bonding pads individually to the circuit pattern; a plurality of second bonding wires, electrically connecting the leads individually to the circuit pattern, the bonding pads being electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires; and a molding compound, covering the circuit pattern, the frame, the first adhesive layer, parts of the leads, the insulating adhesive layer, the chip, the first bonding wires, and the second bonding wires.