Patent ID: 6934815

Claim:
An interprocessor data communication apparatus, comprising: a shared memory having a queue having a plurality of elements including a first empty element, each of the plurality of elements having a first area and a second area; a first processor configured to add a second empty element to the queue, write into the first area of the first empty element communication information related to communication data, and write into the second area of the first empty element connection information indicating a connective relationship between the first and second empty elements, and write completion information indicating whether the communication information has been written in the first area of the first empty element; and a second processor configured to access the second area of the first empty element and read the write completion information, determine whether the communication information is written in the first empty element, based on the write completion information read, and read the communication information from the first empty element if the second processor determines that the communication information has been written in the first empty element, wherein a memory area of each of the plurality of elements has a size such that all of the information written by the first processor and all of the information read by the second processor are written by the first processor or read by the second processor in an uninterruptible single access without requiring an exclusive lock on the queue.