Patent ID: 7340708

Claim:
A method for generating a layout pattern of a basic cell forming a semiconductor integrated circuit, the method comprising: obtaining process technology definition data related to a process technology of each layer forming the basic cell as an object in which the layout pattern is generated, from a process technology definition file defining process technology definition data related to a process technology for use in fabricating a semiconductor integrated circuit, thereby holding a process technology definition table containing the obtained process technology definition data; obtaining device structure data including data related to a device template which defines a structure of each layer of the basic cell as an object in which the layout pattern is generated and data related to the structure of each layer defined in accordance with the device template, from a device structure definition file defining the device structure data determined for each type of the basic cell forming the semiconductor integrated circuit, thereby holding the obtained device structure data as a device structure definition table; and determining the structure of each layer defined in accordance with the device template held as the obtained device structure data, in accordance with the process technology definition data of a corresponding layer in the process technology definition table, thereby generating the layout pattern of the basic cell forming the semiconductor integrated circuit.