Patent ID: 8796127

Claim:
A method of fabricating a semiconductor device, comprising: forming first and second dummy gate patterns spaced apart from each other on a substrate; forming an etch stop layer to cover sidewall and top surfaces of the first and second dummy gate patterns; forming an interlayer insulating layer on the substrate and the etch stop layer; planarizing the interlayer insulating layer to expose the etch stop layer on the first and second dummy gate patterns; etching the etch stop layer to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns; forming a gap-filling insulating pattern to fill the groove; removing the first and second dummy gate patterns to form first and second trenches exposing the substrate; forming a gate insulating layer on bottom surfaces of the first and second trenches; and forming first and second gate electrodes on the gate insulating layer.