Patent ID: 6854049

Claim:
A method for handling instructions within a processor with a decoupled architecture, the processor comprising a first processing unit including at least one register, first and second FIFO-type memories for storing instructions for the second processing unit, the method comprising: providing to the third FIFO-type memory an operative instruction for deriving an address of memory stored data; providing to the first FIFO-type memory a loading instruction for loading the memory stored data into the at least one register, the loading instruction being executed only when the memory stored data has been delivered by the second processing unit, each loading instruction being provided to the first FIFO-type memory for storage therein and other operative instructions for the first processing unit being provided to the second FIFO-type memory for storage therein; and removing from the second FIFO-type memory the operative instruction involving the at least one register after having reached an output of the second FIFO-type memory if no earlier loading instruction for modifying a value of the at least one register associated with this operative instruction is present in the first FIFO-type memory, and in the presence of such an earlier loading instruction, then removing the operative instruction from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.