Patent ID: 8209489

Claim:
A processing unit for a multiprocessor data processing system, said processing unit comprising: a processor core; and a cache hierarchy coupled to the processor core to provide low latency data access, the cache hierarchy including an upper level cache coupled to the processor core and a lower level victim cache coupled to and populated by data evicted from the upper level cache, each of the upper level cache and the lower level victim cache including a respective cache directory and a respective data array, wherein responsive to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system; wherein: the prefetch request is a leading prefetch request; the processor core includes a streaming prefetcher that generates the leading prefetch request and a trailing prefetch request both targeting the target memory block; the lower level victim cache, responsive to receipt of the trailing prefetch request, provides the target memory block to the upper level cache, preserves the target memory block in the lower level victim cache in a shared coherence state, and updates a replacement order of the target memory block to a position other than most recently used.