Patent ID: 7818651

Claim:
A semiconductor memory device comprising: memory cells which dynamically hold data; ECC circuits which perform error correction on codes read out from the memory cells; and a control circuit which controls operations of the memory cells and operations of the ECC circuits, the control circuit performing control such that when the memory cells enter a data holding mode, a plurality of data are read out from the memory cells to generate and store a check bit for error detection and correction, and a refresh operation is performed in a period within an error occurrence allowable range of the error correcting operation performed by the ECC circuit by using the check bit, and, before a normal operation mode is restored from the data holding mode, an error bit of the data is corrected by using the check bit, wherein in an entry/exit period, read and write are performed by a page operation, and, when n cycles are necessary from a read command to data output determination, one cycle is necessary for a write operation, and m cycles are necessary for an ECC operation, a page length k is a multiple of (n+m), and the page operation repeats (n+m)-time consecutive read and (n+m)-time consecutive write k/(n+m) times.