Patent ID: 7573753

Claim:
A semiconductor device including a semiconductor memory, wherein the semiconductor memory comprises: a data input-output buffer to send input data from an external data bus to an internal input data bus, and to send output data from an internal output data bus to the external data bus, a first data bus and a second data bus, a first select circuit to select one of the first data bus or the second data bus, and to output data to the internal data bus, an address bus including a row address bit and a memory bank address bit, a first memory device including a number of memory banks indicated by the memory bank address bit, and including a plurality of rows indicated by the row address bit and a first number of the row data for each of the plurality of rows, and adapted to store data input from the first data bus, and to provide the stored data as output to the second data bus, a third memory device including a number of cache data banks indicated by a second number including the plurality of rows and number of row data indicated by the first number, and adapted to output stored data to the first data bus, and to store data input from the second data bus, a fourth memory device including a number of cache tag banks indicated by the second number including the plurality of rows, and adapted to store data input from the memory bank address bit of the address bus, and a control circuit including a function for determining a cache hit or a cache miss by comparing data read from the fourth memory device with the memory bank address bit of the address bus, when the data write instruction or the data read instruction is issued to the semiconductor memory, to control the first, the third, and the fourth memory devices, wherein, if a write cycle time of the first device is N (N ≧2) times as long as that of a read cycle time, the second number is equal to or larger than N.