Patent ID: 7120059

Claim:
An integrated circuit memory device, comprising: an array of multiple-gate memory cells, the array including a plurality of columns and at least one row of multiple-gate memory cells, where multiple-gate memory cells in the array respectively comprise a semiconductor body, a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, a charge storage structure including charge trapping locations beneath more than one of the plurality of gates in the series, and a continuous, multiple-gate channel region in the semiconductor body beneath the plurality of gates in the series; a plurality of word lines coupled to the plurality of gates of multiple-gate memory cells in the at least one row; a plurality of bit lines, arranged orthogonally to the plurality of word lines, bit lines in the plurality of bit lines arranged for connection to multiple-gate memory cells in one or more columns of the plurality of columns; a plurality of select gates, the select gates in the plurality of select gates arranged to connect respective multiple-gate memory cells in the at least one row to a corresponding bit line in the plurality of bit lines in response to a select gate control signal; a select line coupled to the plurality of select gates in the at least one row to provide the select gate control signal; and a controller which controls the plurality of bit lines, plurality of word lines and the select line to conduct source and drain bias voltages to the multiple-gate memory cells in the array, and to conduct gate bias voltages to the plurality of gates in the multiple-gate memory cells in the at least one row, and to provide the select gate control signal.