Patent ID: 7075817

Claim:
A memory comprising: address lines operable to carry addresses; control lines operable to carry control signals; data lines operable to carry data; a memory array that is accessed by array lines; an address decoder that decodes the address on the address lines and activates certain array lines; drivers that, as a function of the control signals, are operative to cause some array lines to be placed at a first write voltage, a second write voltage, or a read voltage; a plurality of two-terminal memory plugs within the memory array, each two-terminal memory plug electrically connected to at least one array line, the two-terminal memory plug being able to be reversibly written to a first resistive state when the some array lines are at the first write voltage, reversibly written to a second resistive state when the some array lines are at the second write voltage, and have its resistive state undisturbed when the some array lines are at the read voltage, wherein a read output is produced when the some array lines are at the read voltage; a reference cell within the memory array that contributes to a reference level; and sensing circuitry that compares the read output to the reference level and produces data.