Patent ID: 7159092

Claim:
A timing skew compensation circuit for generating a plurality of skew compensated latch clock signals that are applied to a corresponding plurality of latch circuits to compensate for timing skew of a corresponding plurality of digital signals relative to a common clock signal, the timing skew compensation circuit comprising: a clock generator having an input node at which the common clock signal is applied and further having a plurality of output nodes at which a plurality of phase adjusted clock signals are provided, each phase adjusted clock signal having a different phase relationship relative to a common clock signal applied to the clock generator; a plurality of selection circuits, each selection circuit having a plurality of input nodes coupled to the plurality of output nodes of the clock generator to receive the plurality of phase adjusted clock signals, each selection circuit further having a control node at which control signals are applied and having an output node at which one of the plurality of phase adjusted clock signals is provided as a skew compensated latch clock signal based on the control signals applied to the control node; a plurality of registers, each register coupled to the control node of a corresponding one of the plurality of the selection circuits to provide a respective stored value as the control signals to the respective selection circuit; and a control circuit coupled to each of the plurality of registers, the control circuit generating for each of the registers a compensation value for storage that when provided to the respective selection circuit as the control signal compensates for the timing skew associated with the respective digital signal.