Patent ID: 8793633

Claim:
A method of modifying a hierarchical circuit design, comprising: accessing hierarchical circuit data in the hierarchical circuit design, the hierarchical circuit data comprising top-level data and lower-level block data; performing, using one or more computer processors, timing analysis on a subset of the hierarchical circuit data to determine whether inter-block timing closure is achieved; and in the event that inter-block timing closure is not achieved, performing a set of one or more fixes on the subset of the hierarchical circuit data to achieve inter-block timing closure; wherein: the subset of the hierarchical circuit data includes a selected portion of the top-level data and a selected portion of the lower-level block data; and accessing the hierarchical circuit data in the hierarchical circuit design, performing the timing analysis on the subset of the hierarchical circuit data to determine whether inter-block timing closure is achieved, and in the event that inter-block timing closure is not achieved, performing the set of one or more fixes on the subset of the hierarchical circuit data to achieve inter-block timing closure are performed while maintaining block boundaries of the hierarchical circuit data within a top-level place and route (P&R) process.