Patent ID: 7353363

Claim:
A processor comprising: an instruction decode block including both a fixed decode path and a configurable decode path that includes a programmable multi-entry store from which, for a first subset, less that all, of instructions executed by the processor, programmable sequences of one or more decoded operations are generated; a predecode path that is configurable to select, for respective instruction patterns, one of the fixed decode path and the configurable decode path wherein said predecode path includes a fixed predecode path and a programmable predecode path wherein each of said fixed predecode path and said programmable predecode path receive a same input; and an instruction store coupled between the configurable predecode path and the instruction decode block, the instruction store including storage for instructions and for predecode information associated with said instructions, wherein said predecode information is received from said predecode path; and at least some of the predecode information is selective for one of the fixed instruction decode path and the configurable instruction decode path.