Patent ID: 7120779

Claim:
Apparatus for processing data, said apparatus comprising: an instruction decoder responsive to program instructions to control data processing operations; and an address offset generating circuit controlled by said instruction decoder and operable to generate an N-bit address offset having a value specified by an address offset generating instruction including an offset value sign specifying bit S; wherein said N-bit address offset has bit values B i when expressed as a two's complement number, where (N−1)≧i≧Z and (N−1)>Z≧0, said address offset generating instruction includes L high order field bits P k , where (N−Z)>L≧1 and L>k≧0, and said address offset generating circuit is operable such that: (i) if all of said high order field bits P k have respective predetermined values D k , then bits B j of said N-bit address offset are given by B j =S for all values of j such that (N−1)≧j≧(N−L−1); and (ii) if any of said high order field bits P k does not have said predetermined value D k , then bits B j of said N-bit address offset, where (N−1)≧j≧(N−L−1), are given by a predetermined one-to-one mapping from combinations of values of said high order field bits P k and said offset value sign specifying bit S to combinations of values of B j other than the combination B j =1 for all values of j such that (N−1)≧j≧(N−L−1) and the combination B j =0 for all values of j such that (N−1)≧j≧(N−L−1).