Patent ID: 8880777

Claim:
A complex memory device, comprising: a storage unit comprising a non-volatile random access memory (RAM) and a flash memory; and a controller to process an input/output (I/O) request from a host, to determine whether the I/O request is in units of bytes or blocks, and to automatically execute one of a first or second interface protocol between the host and the storage unit according to whether the I/O request is in the units of bytes or blocks, wherein, each time the I/O request is in the units of bytes the controller automatically executes the first interface protocol in which the I/O request is hierarchically processed such that the controller determines whether data requested by the I/O request is present in the non-volatile RAM, and if the data is not present in the non-volatile RAM, the data is loaded from the flash memory to the non-volatile RAM, and each time the I/O request is in units of blocks the controller automatically executes the second interface protocol by issuing a command using a register interface to directly access a register corresponding to a flash memory such that the I/O request is processed directly by the flash memory without passing the I/O request through the non-volatile RAM, wherein the second interface protocol is devoid of any determination as to whether the data requested by the I/O request is present in the non-volatile RAM.