Patent ID: 7685369

Claim:
A method of tuning memory allocated to caches resident in the memory, said method comprising: determining a size of a first resident cache and a size of a second resident cache; determining a rate at which pages in the first resident cache and the second resident cache are evicted; determining a rate at which pages in the first and second resident caches are scanned; estimating first inter-reference distances for least recently accessed resident hot pages in the first and second resident caches based on the respective rates at which pages in the first and second resident caches are evicted and rates at which pages in the first and second resident caches are scanned; determining second inter-reference distances for non-resident pages that were evicted from the first and second resident caches; and allocating memory to the first and second resident caches based on size of the first and second resident caches and the first and second inter-reference distances.