Patent ID: 7635891

Claim:
A semiconductor device comprising: a semiconductor substrate; and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells comprising: a first insulating film provided on the semiconductor substrate; a charge storage layer provided on the first insulating film; a second insulating film provided on the charge storage layer; and a control electrode provided on the charge storage layer via the second insulating film, the control electrode comprising first and second portions and both the first and second portions directly contacting the second insulating film, wherein the first portion is a corner of a lower part of the control electrode and comprises semiconductor and fails to contain metal or metal silicide in a channel width direction of the memory cell, and the second portion forms directly next to the first portion and is a part of the lower part of the control electrode except the first portion and comprises metal or metal silicide and fails to contain semiconductor.