Patent ID: 7240186

Claim:
A multi-threaded processor, comprising; a plurality of thread processing units capable of concurrently processing one or more instructions from different programs; a fetching unit that fetches instructions for each of said plurality of thread processing units; a non-speculative exception handler that receives an indication of any of a first group of excepting speculative instructions, and identifies the program associated with said excepted instruction, and wherein said exception handler generates a signal to said fetching unit to disable fetching for the program associated with the excepted instruction until the processor determines that the excepted instruction is associated with an actual program path, and permitting the fetching unit to continue fetching instructions for at least one other thread processing unit so that processor resources can continue to be used to execute instructions such at least one other program running on another thread processing unit; and a speculative exception handler that receives an indication of any of a second group of excepting speculative instructions and, without the processor determining whether a second group instruction is from the actual program path, the speculative exception handler resolves said second group excepted instruction.