Patent ID: 7424561

Claim:
An apparatus comprising: a first system forming a first node of a multiple-node coherent system, in which the first system includes a first plurality of interface circuits that couple to interface circuits of one or more other nodes of the multiple-node coherent system, the first system also includes a first direct memory access (DMA) circuit to handle packet traffic and a first memory bridge to handle coherent and noncoherent non-packet traffic separate from the packet traffic, the first DMA circuit and the first memory bridge coupled to the first plurality of interface circuits and to a first interconnect internal to the first node to respectively transfer packet traffic and non-packet traffic between the first plurality of interface circuits and the first interconnect; and a second system forming a second node of the multiple-node coherent system, in which the second system includes a second plurality of interface circuits that couple to interface circuits of one or more other nodes of the multiple-node coherent system, including the first node; wherein the first interface circuits and the second interface circuits are separately programmable to receive and send packet traffic, coherent and noncoherent traffic that are not packet traffic, between the first and second nodes.