Patent ID: 8055957

Claim:
A semiconductor integrated circuit device, comprising: a flash memory; a processor which instructs a write operation, an erase operation, and an erase verify operation following the erase operation to the flash memory; and a flash control unit which executes, in a normal mode, a writing to the flash memory based on a write command from the processor, and executes, in a fail-safe mode, the writing to the flash memory and correcting of an error of a written data based on the write command from the processor, wherein the normal mode is shifted to the fail-safe mode when the erase verify operation in the normal mode indicates a defect, wherein the flash control unit includes: an error correction code (ECC) encoder which generates an error correction code for data written in the flash memory, write data being written into the flash memory along with the error correction code; and an ECC decoder which corrects an error based on a read data read from the flash memory, wherein, in the normal mode, when retries of a rewrite operation exceed a specified count, the flash memory is prohibited from being used, as a write detect, and wherein, in the fail-safe mode, when retries of the rewrite operation exceed the specified count, the ECC decoder is activated to perform the erase verify operation.