Patent ID: 7813459

Claim:
A system that facilitates data transfer between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another, comprising: a transfer ok component configured to determine when to transfer data from the first domain to the second domain based upon at least one of a clock signal from the first domain and a clock signal from the second domain, a first multiplexer operatively coupled to the transfer ok component to receive a transfer ok signal from the transfer ok component indicative of when to effect a data transfer from the first domain to the second domain, the first multiplexer also operatively coupled to a first combinational logic component of the first domain to receive one or more first combinational signals from the first combinational logic component, the first multiplexer also operatively coupled to a first output flip flop in the first domain, where output from the first output flip flop is transferred to a second combinational logic component in the second domain when the transfer ok signal is high, and where output from the first output flip flop is fed back into the first multiplexer when the transfer ok signal is low.