Patent ID: 8704591

Claim:
A high-voltage tolerant reference circuit, comprising: a first NMOS transistor including a first source/drain adapted for connection with a first voltage supply and a gate adapted to receive a first bias signal; a first PMOS transistor including a first source/drain adapted for connection with a second voltage supply that is lower in magnitude than the first voltage supply, a gate adapted to receive a second bias signal, and a second source/drain connected with a second source/drain of the first NMOS transistor at an output of the reference circuit; and a bias circuit operative to generate the first and second bias signals, a magnitude of each of the first and second bias signals being configured to control a magnitude of a reference signal generated at the output of the reference circuit such that when the reference signal is within prescribed limits of a quiescent value of the reference signal, a magnitude of a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the magnitude of the current in the reference circuit increases nonlinearly to thereby restore the magnitude of the reference signal to within the prescribed limits of its quiescent value.