Patent ID: 8683100

Claim:
A method performed by a processing system that comprises at least one interchip interface module, the method comprising: assigning a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of the multiple time slices comprising the first time slice and additional time slices; storing a first data item from the first-type communication channel in a memory element in the interchip interface module in response to at least the first priority that is assigned to the first-type communication channel; arbitrating among one or more communication channels of one or more types other than the first-type in each of the additional time slices; in response to the arbitrating, storing a second data item from one of the one or more communication channels of one or more types other than the first-type in the memory element in the interchip interface module; and repeating the assigning, the storing, and the arbitrating for one or more additional sets of multiple time slices.