Patent ID: 7525147

Claim:
A volatile memory structure comprising: a semiconductor substrate; an insulator layer formed on the semiconductor substrate; and a gate layer formed on the insulator layer; the insulator layer comprising: a first nanocrystal implanted region proximate to the gate layer; and a second nanocrystal implanted region proximate to the semiconductor substrate; wherein the first nanocrystal implanted region has an average nanocrystal concentration which is higher than an average nanocrystal concentration of the second nanocrystal implanted region, wherein the nanocrystal concentration of the first nanocrystal implanted region varies with depth below the gate layer with one concentration peak and further wherein the first nanocrystal implanted region has its nanocrystal concentration peak positioned at least substanstially half depth of said first nanocyrstal implanted region below the gate layer, and wherein the depth of the first nanocrystal implanted region below the gate layer is between aboout 8 nm to about 16 nm.