Patent ID: 8245074

Claim:
An apparatus, comprising: a clock integrated circuit, comprising: a first reference signal including a varying noise signal; a timing circuit having an output alternating between the first reference signal and a second reference signal at a rate determined by a time constant determining timing of a clock signal output of the clock integrated circuit, wherein an output of the timing circuit stores the value of the varying noise signal included in the first reference signal, when the timing circuit output changes between (i) falling from the second reference signal to the first reference signal and (ii) rising from the first reference signal to the second reference signal; a reference circuit having an output selectably coupled to the varying noise signal, such that the output of the reference circuit stores the value of the varying noise signal, when the timing circuit output changes between (i) falling from the second reference signal to the first reference signal and (ii) rising from the first reference signal to the second reference signal; and a level switching circuit comparing the output of the reference circuit with the output of the timing circuit, such that an output of the level switching circuit determines the clock signal output of the clock integrated circuit.