Patent ID: 7737752

Claim:
A clock generator, comprising: a first circuit having a first clock input configured to receive a first clock signal having a first frequency, a second clock input configured to receive a second clock signal having the first frequency, and an output, wherein the second clock signal is out-of-phase with the first clock signal, the first circuit comprising a multiplexer having a first input, a second input, a third input, a fourth input, a first select input, a second select input, and an output; and a second circuit coupled to the first circuit, the second circuit having a mode signal input configured to receive a mode signal, wherein the output of the first circuit is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal, a first edge of the generated clock signal based on an edge of the first clock signal and a second edge of the generated clock signal based on an edge of the second clock signal.