Patent ID: 7910443

Claim:
A method for fabricating a semiconductor device, comprising: forming a conductive material layer over a substrate including a cell region and a peripheral region; forming hard mask patterns over the conductive material layer in the cell region and the peripheral region; forming a mask pattern over the substrate including the hard mask patterns only in the cell region, exposing the peripheral region; trimming the hard mask patterns in the peripheral region without using a mask formed over the hard mask patterns in the peripheral region so that the critical dimension of the hard mask patterns in the peripheral region is reduced; removing the mask pattern; and etching the conductive material layer to form gate patterns using the hard mask patterns in the cell region and the trimmed hard mask patterns in the peripheral region, wherein the hard mask patterns comprise a stack structure including a carbon (C)-based material and a silicon (Si)-based material including a polymer, wherein the polymer includes one selected from a group consisting of silicon oxide (SiO2) and Si.