Patent ID: 8504974

Claim:
A method of analyzing a circuit design, comprising performing operations on a programmed processor, the operations including for each sub-circuit of a plurality of sub-circuits specified in the circuit design: determining a respective logic level probability that indicates a probability that an output of the sub-circuit will have a first value in response to possible values of inputs to the sub-circuit; wherein the determining of the respective logic level probability includes: retrieving the logic level probability from a database describing a plurality of compound circuits and associated logic level probabilities for respective outputs of the compound circuits; for each input of the circuit design coupled to an input of one of the plurality of sub-circuits that is not described in the database of compound circuits, setting a logic level probability of the input to 0.5, wherein the logic level probability indicates a probability that the input will have the first value; and determining the logic level probability of each output of a sub-circuit as a function of logic level probabilities of inputs of the sub-circuit; converting, by the programmed processor, each logic level probability to a switching probability that indicates a probability that a switching event will occur at the respective output of the sub-circuit within a time period; and storing the switching probability.