Patent ID: 7524719

Claim:
A method for forming a split gate memory cell using a semiconductor substrate, comprising: forming a first gate structure and a sacrificial structure over the semiconductor substrate, each of the first gate structure and the sacrificial structure including a nitride layer overlying the semiconductor substrate, wherein forming the first gate structure and the sacrificial structure includes forming an opening between the first gate structure and the sacrificial structure, wherein forming the first gate structure, the sacrificial structure, and the opening further includes using a single masking step which lithographically defines both (i) a gate length of the first gate structure and (ii) a gate length of a second gate structure yet to be formed, wherein the gate length of the second gate structure is lithographically defined by the opening; lining the opening with a layer; and filling the lined opening with a gate material of the second gate structure, wherein the first and second gate structures comprise one of (i) a select gate structure and a control gate structure, respectively, further wherein the layer comprises a storage layer and (ii) a control gate structure and a select gate structure, respectively, further wherein the layer comprises a dielectric layer; planarizing the gate material down to the nitride layer; thermally oxidizing an exposed top surface of the planarized gate material; and removing the sacrificial structure via a wet etch, wherein the thermally oxidized top surface of the planarized gate material protects underlying gate material during the wet etch removal of the sacrificial structure.