Patent ID: 7397272

Claim:
A system for configuring a plurality of programmable devices comprising: a parallel memory for storing a configuration bitstream having a parallel data output; a master programmable device having a parallel data input, a parallel data output, and a chip select output, the parallel data output of the parallel memory coupled to the parallel data input of the master programmable device; and a first slave programmable device having a parallel data input and a chip select input, the parallel data output of the master programmable device coupled to the parallel data input of the first slave programmable device, and the chip select output of the master programmable device coupled to the chip select input of the first slave programmable device; wherein the master programmable device provides addresses to the parallel memory; wherein the parallel memory provides the configuration bitstream in parallel to the master programmable device in response to the addresses; wherein the master programmable device provides at least a portion of the configuration bitstream in parallel to the first slave programmable device; and wherein the master programmable device comprises configuration control circuitry for controlling configuration of the master programmable device.