Patent ID: 8918594

Claim:
A memory device comprising: a memory array; a first register; a second register; a first interface configured to provide access to said memory array and write access to the second register for a first privilege level, but not for a second privilege level, configured to provide access to the first register regardless of privilege level, and configured to provide read access to the second register regardless of privilege level; a second interface configured to provide access to said memory array and write access to the second register for the first privilege level, but not for the second privilege level, configured to provide access to the first register regardless of privilege level, and configured to provide read access to the second register regardless of privilege level; and a controller configured to concurrently maintain said first interface and said second interface in enabled states, wherein a privilege level assigned to said first interface and said second interface to access said memory array is based, at least in part, on contents of the first register and contents of the second register, wherein an interface of the first interface or the second interface with the first privilege level is configured to indicate a busy state in the second register while using the memory array, wherein a requesting interface of the first interface or the second interface with a second privilege level is configured to read the contents of the second register before requesting a change in privilege level, and wherein the requesting interface is configured to request the change in privilege level by writing to the first register.