Patent ID: 7925862

Claim:
A method for implementing a plurality of operations by a coprocessor for a processor, comprising: transferring a program counter value of the processor to the coprocessor; the coprocessor generating a plurality of load instructions for loading a plurality of input samples, wherein each of the plurality of load instructions includes at least an opcode field, and wherein the coprocessor generates the plurality of load instructions in response to the program counter value of the processor being within a predetermined range, and wherein the coprocessor generating the plurality of load instructions comprises calculating an address displacement field for each of the plurality of load instructions; the coprocessor transferring the generated plurality of load instructions to the processor; the processor decoding and executing the generated plurality of load instructions; in response to the processor decoding and executing the generated plurality of load instructions, the coprocessor receiving the plurality of input samples; and the coprocessor performing the plurality of operations using the plurality of input samples.