Patent ID: 7793179

Claim:
A test clock control structure for generating a test clock to implement scan-based testing of electronic circuits, said test clock control structure comprising: a programmable test clock controller for testing a circuit, said programmable test clock controller including: a clock pulse controller to receive a portion of clock command information in a control chain; and a test clock generator configured to generate a configurable test clock as a function of the received portion of clock command information, the test clock to drive a scan chain portion of a scan chain; a scan layer interface configured to drive a portion of the scan chain with said configurable test clock; and a control layer interface configured to access the clock command information in the control chain; wherein the clock pulse controller receives a scan enable data (SeD) signal to control a shifting of the portion of clock command information into the clock pulse controller, wherein the test clock generator provides to the clock pulse controller a clock rate control signal generated based on the SeD signal and a scan enable clock (SeC) signal indicating a clock signal to apply to the scan chain, wherein the clock pulse controller, in response to the clock rate control signal, selects a clock rate for generating a test clock enable signal, the clock pulse controller to provide the test clock enable signal to the test clock generator, and wherein the test clock generator generates the test clock by multiplexing between a scan clock and a functional clock based on the test clock enable signal.