Patent ID: 8716831

Claim:
A semiconductor device having an eFuse structure for a one time programmable memory (OTP), comprising: a base substrate having a shallow trench isolation (STI) formation; a first metal layer formed on the STI formation, having a shape that defines an anode, a cathode, and a fuse neck connected between the cathode and the anode; an undoped polysilicon (poly) region formed on the fuse neck; and a second metal layer having a first portion and a second portion that are formed on the first metal layer on opposite sides of the poly region, the first portion of the second metal layer formed on the anode and on a first portion of the fuse neck, and the second portion of the second metal layer formed on the cathode and on a second portion of the fuse neck, wherein the poly region is formed on a third portion of the fuse neck disposed between the first and the second portions of the fuse neck.