Patent ID: 7405445

Claim:
A semiconductor integrated circuit structure comprising: a semiconductor region of a first conductivity type; a first well region formed in the semiconductor region, the first well region being lightly doped to a second conductivity type opposite the first conductivity type; a first highly doped n-region formed in the first well region; a first highly doped p-region formed in the first well region and spaced apart from the first n-region; a second well region formed in the semiconductor region, the second well region being lightly doped to the second conductivity type; a second highly doped n-region formed in the second well region; a second highly doped p-region formed in the second well region and spaced apart from the second n-region; a first insertion region disposed in the semiconductor region between the first well region and the second well region, the first insertion region being heavily doped to the first conductivity type; a third well region formed in the semiconductor region, the third well region being lightly doped to the second conductivity type; a third highly doped n-region formed in the third well region; a third highly doped p-region formed in the third well region and spaced apart from the third n-region, wherein the first n-region, the first p-region, the second n-region, the second p-region, the third n-region and the third p-region are connected in series to form diodes; a second insertion region disposed in the semiconductor region between the second well region and the third well region, the second insertion region being heavily doped to the first conductivity type; and a guard ring region disposed in the semiconductor region and encircling the first well region, the second well region, and the third well region, the guard ring region being heavily doped to the first conductivity type, wherein the first and the second insertion regions are physically connected to the guard ring region, and wherein depths of the first and the second insertion regions and the guard ring region are less than depths of the first, the second and the third well regions, and wherein no well region is between any of the first and the second insertion regions and the semiconductor region.