Patent ID: 7402494

Claim:
A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on the semiconductor substrate; forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode; selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask; forming the gate insulating layer and the gate electrode using the gate formation mask; removing the gate-formation mask after the gate electrode is formed; and forming a second low-density impurity implanted region on the semiconductor substrate so that the second low-density impurity implanted region is located outside the first low-density impurity implanted region.