Patent ID: 7827473

Claim:
A turbo decoder for performing parallel decoding of a turbo coded signal that has been generated using almost regular permutation (ARP) interleaving, the turbo decoder comprising: a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal; and a plurality of memories; and wherein: during a first decoding cycle: each turbo decoder of the plurality of turbo decoders retrieving information from a first respective, corresponding memory of the plurality of memories as directed by a first decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its first respective, corresponding memory thereby generating respective updated information; during a second decoding cycle: each turbo decoder of a first subset of the plurality of turbo decoders retrieving information from a second respective, corresponding memory of the plurality of memories as directed by a second decoding cycle contention-free mapping between the plurality of turbo decoders and the plurality of memories; and each turbo decoder of a second subset of the plurality of turbo decoders performing a dummy decoding cycle; and the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal.