Patent ID: 8621323

Claim:
A memory system, comprising: a controller; and a memory, including a non-volatile data storage section; a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller, wherein a second data set transferred from the second data register can be operated upon in the controller concurrently with transferring a first data set between said first data register and the non-volatile data storage section, and wherein the controller includes error correction circuitry and the controller can perform error correction operations upon the second data set concurrently with transferring the first data set between the first data register and the non-volatile data storage section.