Patent ID: 7629669

Claim:
A semiconductor apparatus comprising: a first transistor having a first emitter region as an impurity region of a first conductivity type, a first base region as an impurity region of a second conductivity type different from said first conductivity type, and a first collector region as an impurity region of said first conductivity type; a second transistor having a second emitter region as an impurity region of said first conductivity type, a second base region as an impurity region of said second conductivity type, and a second collector region as an impurity region of said first conductivity type; a first emitter electrode connected to said first emitter region; a first base electrode connected to said first base region; a first collector electrode connected to said first collector region; a second base electrode connected to said second base region, and a second collector electrode connected to said second collector region; wherein said first emitter region, said first base region, and said first collector region are located in a first region surrounded by a first element separating region, wherein a second emitter region, a second base region, and a second collector region are located in a third region surrounded by a second element separating region, wherein said first emitter electrode, said first base electrode, and said first collector electrode are located in a region over said first region, wherein said second emitter electrode, said second base electrode, and said second collector electrode are located in a region over said third region, wherein a first wiring connecting said first base electrode and said first base region passes over a second region provided out of said first region, wherein said first emitter electrode and said second collector electrode are connected by a wiring layer of an upper layer over said first wiring, wherein said first collector electrode and said first base electrode are connected by the wiring layer of the upper layer over said first wiring, and wherein said second emitter electrode and said second base electrode are connected by the wiring layer of the upper layer over said first wiring.