Patent ID: 7981803

Claim:
A method of forming a micro pattern of a semiconductor device, the method comprising: forming an etch target layer and a first hard mask layer over a semiconductor substrate; forming a plurality of insulating patterns having a lozenge shape over the first hard mask layer in a longitudinal direction and a cross direction; forming a first auxiliary pattern on the first hard mask layer including the insulating patterns, wherein the first auxiliary pattern is formed on sidewalls of the insulating patterns to a thickness to the extent that gap regions between adjacent insulating patterns in at least one of the longitudinal direction or the cross direction are buried, and a contact hole having substantially the same shape as that of the insulating pattern is formed at the middle of four adjacent insulating patterns, which form a quadrilateral; forming a second auxiliary pattern by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed; removing the exposed insulating patterns; forming a first hard mask pattern by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask; and etching the etch target layer using the first hard mask pattern.