Patent ID: 8445297

Claim:
A method of fabricating an integrated circuit device, the method comprising the steps of: forming a shell with a first side portion and a second side portion, wherein a cavity is formed within the second side portion, wherein a first electrical part is embedded within the first side portion and electrically coupled via a first set of pads of a lead frame, the lead frame having integral and continuous distal end exposed portions that extend into the second side portion; testing the first electrical part by communicating at least one test signal from a tester to the first electrical part, wherein at least one response signal is generated by the first electrical part and is processed by the tester by comparing the at least one response signal to known response signals in a database to determine whether the first electrical part is functional; and wherein in response to the first electrical part being functional, embedding a second electrical part within the cavity and electrically coupling the second electrical part to the lead frame via a second set of pads of the lead frame, wherein the cavity is filled with a filler material to at least partially embed the second electrical part within the filler material if the second electrical part is functional.