Patent ID: 7181720

Claim:
A process for circuit design by means of high-level synthesis in which a register-transfer description is determined from a system description of a circuit to be designed, the process comprising the steps of: a) generation of a data structure representing the system description, b) determination of a schedule for operations for accomplishment of an objective by means of a scheduling operation, c) determination of an initial register-transfer description by means of an allocation and binding operation, d) determination of an initial floorplan for a needed circuit area, e) determination of an initial power consumption occurring in the initial register-transfer description and the initial floorplan, f) determination of a modified register-transfer description by a single change of the initial register-transfer description by means of an allocation and binding operation, g) modification of the initial floorplan to obtain a modified floorplan reflecting the modified register-transfer description, h) determination of a modified power consumption occurring in the modified register-transfer description and the modified floorplan, i) use of the modified register-transfer description, the modified floorplan, and the modified power consumption as a new initial register-transfer description, a new initial floorplan and a new initial power consumption if the modified power consumption is less than the initial power consumption, and j) iteration of the steps f) to i) until a termination criterion is met.