Patent ID: 7323392

Claim:
A method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate; forming a first semiconductor plate over the semiconductor substrate; forming a second semiconductor plate on the first semiconductor plate, wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate; forming a gate stack over the first and the second semiconductor plates, wherein the first and the second semiconductor plates have extensions extending substantially beyond side edges of the gate stack, and wherein the gate stack comprises: a gate dielectric over the second semiconductor plate; and a gate electrode over the gate dielectric; forming an additional semiconductor layer containing silicon on the semiconductor substrate and spaced apart from the first and the second semiconductor plates; forming a lightly doped drain/source (LDD) region in at least the first and the second semiconductor plates and the semiconductor substrate, the LDD region being substantially aligned with an edge of the gate stack; forming a gate spacer along sidewalls of the gate stack and the first and the second semiconductor plates; and forming a source/drain region substantially aligned with an edge of the gate spacer.