Patent ID: 7989853

Claim:
A dual channel junction field effect transistor (JFET), comprising: a p-type semiconductor substrate; a deep n-well formed in said p-type semiconductor substrate; a plurality of p-wells formed in said deep n-well, such that a first channel is formed between a first p-well of said plurality of p-wells and a bottom surface of said deep n-well and a second channel is formed between said first p-well and a second p-well of said plurality of p-wells, wherein said second p-well is adjacent to said first p-well; a plurality of n-well regions formed in said deep n-well in exterior regions to said plurality of p-wells; a plurality of n-type drain contact regions formed in said plurality of n-well regions, such that each n-well region of said plurality of n-well regions contains at least one n-type drain contact region of said plurality of n-type drain contact regions; and an n-type source contact region formed in said deep n-well between said first p-well and said second p-well.