Patent ID: 7468913

Claim:
A semiconductor device comprising: a first source region, a second source region, and a first drain region which exhibit a second conductivity type and are formed in a semiconductor well of a first conductivity type; a first memory node which is formed on the semiconductor well between the first source region and the first drain region via a first insulator and is insulated from its periphery; a second memory node which is formed on the semiconductor well between the first drain region or a second drain region electrically connected to the first drain region and the second source region via a second insulator and is insulated from its periphery; a first electrode formed on the first memory node via a third insulator; and a second electrode formed on the second memory node via a fourth insulator, wherein, in a programming operation to the first memory node, (a) a first voltage is applied to the first electrode, thereby putting a channel at lower portion of the first memory node into a low resistance state, (b) a second voltage is applied to the second electrode, thereby putting a channel at lower portion of the second memory node into a high resistance state, and (c) a current is allowed to flow between the first source region and the first drain region below the first memory node, thereby injecting generated hot carries into the first memory node, and wherein the semiconductor well is put into an electrically floating state in the programming operation.