Patent ID: 8343833

Claim:
A method of manufacturing a semiconductor device including a plurality of units having identical structures using a semiconductor substrate that includes a drain layer including an impurity of a first conductive type at a given concentration, and a low concentration layer on the drain layer and including an impurity of the first conductive type at a concentration lower than the given concentration, the method comprising: injecting an impurity of the first conductive type at a first concentration higher than that of the low concentration layer into the low concentration layer; performing a thermal treatment to make a reference concentration layer, the reference concentration layer and the low concentration layer forming a drift layer; injecting an impurity of a second conductive type into regions spaced at a given interval in the reference concentration layer to form a pair of depletion-layer extension regions; performing a thermal treatment for activating the impurity injected into the depletion-layer extension regions; forming an oxide film on the semiconductor substrate; layering a polysilicon layer on the semiconductor substrate to form a gate pattern between the depletion-layer extension regions; injecting an impurity of the second conductive type at a second concentration higher than those of the depletion-layer extension regions with the gate pattern serving as a mask for forming a pair of base regions; performing a thermal treatment to form the base regions; injecting an impurity of the first conductive type at a concentration higher than the first concentration with the gate pattern serving as a mask for forming a pair of source regions; and performing a thermal treatment to form the source regions, wherein boundaries between the depletion-layer extension regions and the low concentration layer are positioned lower than a boundary between the reference concentration layer and the low concentration layer.