Patent ID: 8431471

Claim:
A method for integrating a non-volatile memory (NVM), the method comprising: forming a first conductive layer over a substrate, the substrate having an NVM region, a logic region, and an isolation region, wherein the isolation region is adjacent the NVM region and the logic region; patterning the first conductive layer to expose at least a portion of the substrate to leave exposed substrate in the NVM region and at least a portion of the isolation region to leave exposed isolation region; forming an NVM dielectric stack over the first conductive layer, the exposed substrate, and the exposed isolation region; forming a second conductive layer over the NVM dielectric stack; and patterning the first conductive layer, the NVM dielectric stack, and the second conductive layer to form: a first gate and a second gate of an NVM cell over the substrate in the NVM region, wherein the first gate is formed from the first conductive layer and the second gate is formed from the second conductive layer, and a feature over the isolation region, wherein the feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack; and after the step of patterning the first conductive layer, the NVM dielectric stack, and the second conductive layer to form the first and second gates of the NVM cell and the feature, the method further comprises: patterning the first conductive layer in the logic region to form at least one gate of a logic device.