Patent ID: 7774687

Claim:
A method for Low Density Parity Check (LDPC) code erasure decoding, comprising: generating, by a LDPC code erasure decoding system, a first code word through setting a value as a value in Galois field having two elements GF(2) at each of erasure locations in a received LDPC code word; generating, by the LDPC code erasure decoding system, a second code word through setting the value as an inverse value of the value in GF(2) at each of the erasure locations in the received LDPC code word; conducting, by the LDPC code erasure decoding system, a Majority Logic Decoding, MLD, error correcting operation for the generated first code word to get a first result of hard decoding which includes a first error pattern; conducting, by the LDPC code erasure decoding system, the MLD error correcting operation for the generated second code word to get a second result of hard decoding which includes a second error pattern; and determining, by the LDPC code erasure decoding system, a result of erasure decoding according to the first result of hard decoding and the second result of hard decoding; wherein the conducting the MLD error correcting operation for the generated first and second code word comprises: multiplying the generated first or second code word by an LDPC code check matrix H T to get an adjoint series {s 1 , s 2 , . . . s J }; selecting, from the adjoint series {s 1 , s 2 , . . . s J }, an adjoint series corresponding to each error bit of the first error pattern or the second error pattern; and if the number of adjoint elements with a value of 1 in the selected adjoint series corresponding to an error bit is larger than half of the total number of adjoint elements in the selected adjoint series corresponding to the error bit, setting the value of the error bit as 1; otherwise, setting the value of the error bit as 0.