Patent ID: 7885031

Claim:
An integrated circuit device comprising: an input configured to couple with an output of a signal equalizer configured to receive an input signal responsive to an output of an asymmetry correction circuit and to generate an equalized signal, where the asymmetry correction circuit is configured to receive an analog signal and to compensate for asymmetry in the received analog signal; an input configured to couple with an output of a discrete time sequence detector operable to examine the equalized signal; an output configured to provide a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation; and circuitry configured to generate the output to provide the coefficient adjustment to the asymmetry correction circuit based on a correlation between an estimated ideal channel output and an error signal, the estimated ideal channel output derived from the output of the discrete time sequence detector, and the error signal derived from the equalized signal and an estimated real equalized channel output with asymmetry taken into account.