Patent ID: 8737107

Claim:
A memory circuit, comprising: at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line; and a first conductive layer, a second conductive layer, and a third conductive layer arranged at different levels and being routed to define the word line, the bit line, the bit line bar, the first voltage line, and the second voltage line; wherein the second conductive layer is electrically coupled with the first conductive layer; the third conductive layer is electrically coupled with the second conductive layer; the third conductive layer is routed for the word line and is free from including the bit line, the bit line bar, the first voltage line, and the second voltage line within the memory cell; within the memory cell, the memory circuit is free from including a conductive part co-elevational with the third conductive layer; and a width of the third conductive layer for the word line within the memory cell is 50% or more of a width of a short side of the memory cell.