Patent ID: 8209446

Claim:
An apparatus comprising: a Direct Memory Access (DMA) controller; and a host coupled to the DMA controller, wherein the host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host; wherein the DMA controller is configured to perform DMA transfers between a first memory region in the plurality of memory locations and a second memory region in the plurality of memory locations; and wherein the DMA controller comprises a transmit control circuit, a receive control circuit, and a loopback circuit coupled to the transmit control circuit and the receive control circuit, wherein the transmit control circuit is configured to read data from the first memory region and to provide the data to the loopback circuit, and wherein the loopback circuit is configured to provide the data to the receive control circuit, and wherein the receive control circuit is configured to write the data to the second memory region; and wherein the transmit control circuit is configured to read the data from the first memory region in response to a DMA descriptor, and wherein the DMA descriptor further includes an address of the second memory region, and wherein the loopback circuit is coupled to receive the address and to provide the address to the receive control circuit to write the data to the second memory region.