Patent ID: 7439569

Claim:
A semiconductor device comprising: a semiconductor substrate having a memory region where a memory device is formed and a logic region where a logic device is formed; a first insulating film provided on said semiconductor substrate; first and second contact plugs provided in said first insulating film with their respective top surfaces exposed from said first insulating film, and electrically connected to said semiconductor substrate in said memory region; a third contact plug provided in said first insulating film with its top surface exposed from said first insulating film, and electrically connected to said semiconductor substrate in said logic region; an MIM capacitor having a lower electrode, an upper electrode, and a dielectric film interposed therebetween, said lower electrode being in contact with the top surface of said first contact plug; a second insulating film provided on said first insulating film and covering said MIM capacitor; a fourth contact plug provided in said second insulating film and being in contact with said second contact plug; and a fifth contact plug provided in said second insulating film and being in contact with said third contact plug; said first contact plug having a first conductive barrier layer in its top portion and a first conductive film in a remaining portion; said second contact plug having a second conductive barrier layer in its top portion and having, in a remaining portion, a second conductive film having a higher conductivity than said second conductive barrier layer; said forth contact plug extending into said first insulating film and being in contact with said second conductive barrier layer and a side surface of said second conductive film; said third contact plug having a third conductive barrier layer in its top portion and having, in a remaining portion, a third conductive film having a higher conductivity than said third conductive barrier layer; said fifth contact plug extending into said first insulating film and being in contact with said third conductive barrier layer and a side surface of said third conductive film.