Patent ID: 8373479

Claim:
A delay locked loop (DLL) circuit for improving jitters, comprising: a detecting unit, detecting a phase difference between a reference clock and a delay clock, and generating a detecting signal in response to the phase difference; a master controller, generating a first control signal in response to the detecting signal; a slave controller, generating a second control signal in response to the detecting signal; a first variable delay line, delaying the reference clock in response to the first control signal so as to generate the delay clock; a second variable delay line; a first dummy load, coupled to the master controller; a second dummy load, coupled to the slave controller; and a processor, selectively generating a slave input signal in response to a input control signal, wherein: if the processor does not generate the slave input signal, the processor makes the second dummy load draw a load current from the slave controller; and if the process generates the slave input signal, the second variable delay line delays the slave input signal in response to the second control signal so as to generate a slave output signal.