Patent ID: 8683400

Claim:
A computer implemented method for conducting fault sensitivity analysis of a mixed signal circuit design having analog portions and digital portions, the method comprising: receiving a fault free mixed signal circuit design for a mixed signal integrated circuit, a fault, and a fault interval time period; during a single fault sensitivity analysis simulation run: using a computer, simulating the fault free mixed signal circuit design with a mixed signal circuit simulator from an initial circuit simulation time point until the end of the fault interval time period; inserting the fault into an analog portion of the fault free mixed signal circuit design; and using a computer, simulating the fault free mixed signal circuit design with the fault, using the mixed signal circuit simulator, only from the beginning of the fault interval time period until the end of the fault interval time period; and determining whether the fault is detectable, wherein simulating the fault free mixed signal circuit design with the fault from the beginning of the fault interval time period until the end of the fault interval time period comprises creating a child process during simulation of the fault free mixed signal circuit design for simulating the fault free circuit with the fault, and ensuring that child process is initialized with the fault free simulation state at the beginning of the fault interval time period.