Patent ID: 8793634

Claim:
An LSI design method of designing a clock tree that supplies a clock signal from a clock supply point in an LSI chip to a plurality of leaves, the method comprising using a computer to perform the steps of: a first step for dividing the leaves into a plurality of groups and forming a local tree in each of the divided groups to generate a plurality of local trees; a second step for forming a high level clock tree by repeating a step of uniformly dividing a clock-supplied region and a step of placing a low level clock buffer with an equal load through an approximately equal-length routing from a high level clock buffer, with the clock supply point as a start point, and placing one clock buffer for each of the divided regions; a third step for calculating, for each of the divided regions, a skew of a path for supplying a clock signal from an end of the high level clock tree to each of start points of the two or more local trees included in the divided region; and a fourth step for determining whether or not the skew calculated for each of the divided regions satisfies a predetermined skew constraint, and the LSI design method further comprising: a loop, in which the divided region is further uniformly-divided until the skew constraint is satisfied in all the divided regions, where a number of stages of the high level clock tree is increased by further placing one clock buffer for each further divided region, and subsequently the third step and the fourth step are carried out.