Patent ID: 7826279

Claim:
A bias circuit for a receiver architecture of a computer processor, the bias circuit comprising: a comparator having a positive input node, a negative input node, and an output node for a current control voltage; a variable current source coupled to the output node of the comparator, the variable current source being configured to generate a current that is dependent on the current control voltage, and to generate an internal bias voltage at a bias voltage node; a receiver replica stage having an output node coupled to the negative input node of the comparator and having a bias input node coupled to the bias voltage node of the variable current source, the receiver replica stage being configured to mimic operation of a counterpart stage in the receiver architecture by generating a replica output at its output node; and a programmable reference voltage generator coupled to the positive input node of the comparator, the programmable reference voltage generator being configured to generate a reference voltage that causes the receiver replica stage to be properly biased, wherein the comparator receives the reference voltage and the replica output and generates the current control voltage based on a comparison of the reference voltage to the replica output.