Patent ID: 8742388

Claim:
A variable resistance memory device, comprising: a semiconductor layer including a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one third doped region of the first conductivity type, the first doped region being spaced apart from the third doped region, the second doped region being between the first and third doped regions; a variable resistance pattern on the semiconductor layer; at least one lower electrode between the semiconductor layer and the variable resistance pattern; and a first metal silicide pattern in contact with the semiconductor layer, the first metal silicide pattern being spaced apart from the third doped region, the second doped region being in contact with the first metal silicide pattern, wherein the first metal silicide pattern is spaced apart from the lower electrode and the first doped region, and the lower electrode is spaced apart from the second doped region.