Patent ID: 8898653

Claim:
A method for updating code of a single processor in a multi-processor system having resources that are coupled through a bridge to all of the processors in the system, each resource usable exclusively by anyone of the processors and each resource sharable by more than one of the processors, comprising: halting transactions processed by a first processor in the system and maintaining processing of transactions by a second processor in the system; receiving new code in the first processor; terminating an operating system running on the first processor whereby all processes and threads being executed by the first processor are terminated; after terminating the operating system, checking the state of a bit settable in memory after receiving the new code in the first processor to determine if a self-reset is to be performed by the first processor; performing a hardware reset of the multi-processor system if the bit is not set; and if the bit is set: commencing execution of a self-reset of the first processor; disabling interrupts associated with the first processor; resetting only those system resources being exclusively used by the first processor without resetting those system resources being used exclusively by the second processor and without resetting those system resources, including the bridge, being shared with the second processor; disabling memory transactions associated with the first processor; copying an image of the new code into memory associated with the first processor, after the steps of commencing execution of the self-reset, disabling interrupts, resetting, and disabling the memory transactions; resetting registers over which the first processor has control as if a hardware reset had occurred; and executing the new code by the first processor as if a hardware reset had occurred.