Patent ID: 7786525

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate having an upper surface in which a plurality of first trenches are formed such that an element forming region is defined, the first trenches having respective sidewalls; an element isolation insulating film buried in the first trenches; a floating gate electrode formed on the element forming region with a first gate insulating film being interposed therebetween, the floating gate electrode being formed so as to have a sidewall which extends from a bottom thereof to an upper portion thereof and is substantially an extension of a sidewall of each first trench; a second gate insulating film formed on upper portions of the floating gate electrode and the element isolation insulating film; and a control gate electrode formed on the second gate insulating film, wherein the element isolation insulating film has an upper end located lower than an upper surface of the floating gate electrode and the upper end of the element isolation insulating film includes a sidewall having such a height as to be in contact with the floating gate electrode; the element isolation insulating film includes a central portion in which a second trench is formed, the second trench having a bottom located lower than the upper surface of the semiconductor substrate; the sidewall of the floating gate electrode includes an upper portion opposed to the control gate electrode with the second gate insulating film being interposed therebetween, the sidewall of the floating gate electrode including a lower portion opposed to the control gate electrode with the element isolation insulating film and the second gate insulating film being interposed therebetween in turn; the control gate electrode is buried in the second trench with the second gate insulating film being interposed therebetween, the control gate electrode having a lower end including a sidewall opposed to the sidewall of each first trench with the second gate insulating film and the element isolation insulating film being interposed therebetween; and the element isolation insulating film includes a portion located between the sidewall of each first trench and a sidewall of the second trench, said upper end and said portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate, said film thickness being equal to a film thickness of the second gate insulating film.