Patent ID: 7477068

Claim:
A data processing system comprising: a central processing unit (CPU); a random access memory (RAM) coupled to the CPU; and a bus for coupling a first and second IC in the CPU using bus circuitry to reduce the cross-talk induced edge jitter within a plurality of propagating data signals transmitted over data transmission lines and a synchronous propagating clock signal transmitted over a clock transmission line, the bus circuitry having a first circuit for coupling states of each of a plurality of data signals to an input of a data off-chip driver (OCD) in response to a first logic state transition of a first clock signal of frequency F thereby generating the propagating data signal as the output of the data OCD coupled to one of the data transmission lines, circuitry for generating a second clock signal with a frequency F/ 2 from the first clock signal, a second circuit for shifting the second clock signal a time substantially equal to one-half cycle of the first clock signal thereby generating a shifted second clock signal by, and circuitry for coupling the shifted second clock signal to the input of a clock OCD that generates the propagating clock signal as an output of the clock OCD coupled to the clock transmission line, wherein transition generated noise coupled from the data transmission lines to the clock transmission line occurs between positive going and negative going logic state transitions of the propagating clock signal.