Patent ID: 7592218

Claim:
A method of forming a vertical transistor comprising: forming a first semiconductor pillar elevationally above a first transistor source/drain in a semiconductor substrate and laterally between a second semiconductor pillar and a third semiconductor pillar, the first pillar being closer to the second pillar than to the third pillar, thus, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars; forming a gate insulator over sidewalls of the first pillar within the first and second recesses; forming a transistor front gate and a transistor back gate over the gate insulator and over respective sidewalls of the first pillar by forming a gate conductor material within the first and second recesses, the gate conductor material forming the back gate in the first recess and forming the front gate in the second recess; forming element isolation material within the second recess between the front gate and the third pillar; and forming a second transistor source/drain elevationally above the first source/drain and providing a transistor channel in the first pillar, the channel being operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.