Patent ID: 7027307

Claim:
An apparatus comprising: a memory interface circuit; a clock signal generating circuit; a plurality of memory modules, each having memory circuitry thereon, the memory modules being operatively coupled and arranged in an order, wherein the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit, and the memory module positioned at the end of the order includes a clock signal terminating circuit, and wherein a clock loop is formed by initially directly routing a clock signal from the output of the clock signal generating circuit through each of the memory modules in the order to the memory module positioned at the end of the order without asserting the clock signal on the memory circuitry, then routing and asserting the clock signal back through the memory modules and the memory circuitry thereon in reverse order to the memory module positioned at the beginning of the order and from there to the memory interface circuit, then routing and asserting the clock signal from the memory interface circuit back through the memory modules and memory circuitry thereon in order to the memory module positioned at the end of the order, and then terminating the clock signal at the clock signal terminating circuit.