Patent ID: 8753961

Claim:
A method of manufacturing an integrated circuit, comprising: providing a lightly doped p-type substrate having a resistivity in the range of 1.5-15 ohm-cm; loading said lightly doped p-type substrate into an oxidation furnace; performing an oxygen precipitate nucleation step prior to an oxygen precipitate growth step with a temperature in the range of 550° C. to 750° C. for a time in the range of 30 minutes to 180 minutes on said lightly doped p-type substrate while said lightly doped p-type substrate is in said oxidation furnace; growing a layer of pad oxide for a shallow trench isolation (STI) process on said lightly doped p-type substrate while said lightly doped p-type substrate is in said oxidation furnace; performing said oxygen precipitate growth step on said lightly doped p-type substrate while said lightly doped p-type substrate is in said oxidation furnace with a temperature in the range of 850° C. to 1000° C. for a time in the range of 30 minutes to 120 minutes, at least a portion of said oxygen precipitate growth step being concurrent with said step of growing said layer of pad oxide; and forming a layer of pad nitride for said STI process on said layer of pad oxide, prior to a core transistor extension implant step.