Patent ID: 7263011

Claim:
A memory circuit having a data input and a data out-put, comprising: a main memory block having a data input and a data output and comprising at least one complete memory array of memory cells being connected to wordlines and bitlines, with the memory cells being addressable via an address signal; a substitution memory block for the substitution of memory cells within the main memory block, having at least one data input and at least one data output and comprising a plurality of substitution memory cells; wherein the substitution memory block is external to the main memory block and arranged to substitute at least one bitline-related set of memory cells being connected to the same bitline in one memory array of the main memory block; and a redirection circuit for redirecting access to a memory cell of the at least one respective substituted bitline-related set of memory cells in the main memory block to the substitution memory block, wherein the redirection circuit comprises: a first multiplexer having (i) an input electrically connected to receive a signal from the data input of the memory circuit and (ii) an output electrically connected to the data input of the substitution memory block; whereby the first multiplexer is configured to support writing to the substitution memory block; and a second multiplexer having (iii) an input electrically connected to receive a signal from the at least one data output of the substitution memory block and a signal from the data output of the main memory block and (iv) an output electrically connected to the data output of the memory circuit; whereby the second multiplexer is configured to support reading from the substitution memory block.