Patent ID: 8093621

Claim:
A power transistor device fabricated on a semiconductor die comprising: a substrate of a first conductivity type disposed at a bottom of the semiconductor die; a buffer layer of a second conductivity type opposite to the first conductivity type, the buffer layer adjoining a top surface of the substrate to form a PN junction therebetween; a first region of the second conductivity type disposed at or near a top surface of the semiconductor die, the first region comprising a source region of a field-effect transistor (FET) that controls forward conduction in a vertical direction between the substrate and the first region when the power transistor device is in an on-state, the substrate comprising an emitter of a bipolar transistor that conducts current in the vertical direction when operation in the on-state; a second region of the first conductivity type disposed adjacent to the first region at or near the top surface, the second region comprising a collector of the bipolar transistor; a body region of the first conductivity type, the body region adjoining a bottom surface of the first and second region; a drift region of the second conductivity type extending in the vertical direction from a top surface of the buffer layer to a bottom surface of the body region; first and second dielectric regions that respectively adjoin opposing lateral sidewall portions of the drift region, the dielectric regions extending in the vertical direction from at least just beneath the body region down at least into the buffer layer; a gate disposed adjacent to and insulated from the body region the gate extending in the vertical direction from the bottom surface of the first region to a least the bottom surface of the body region; and first and second field plates disposed within the first and second dielectric regions, respectively, the first and second field plates each extending in the vertical direction from just above a lowermost portion of the gate down to near the top surface of the buffer layer, the first and second field plates being fully insulated from the drift region and the buffer layer.