Patent ID: 8310896

Claim:
A memory system comprising: a nonvolatile semiconductor memory comprising a first physical block and a second physical block, each of the first and second physical blocks comprising write unit areas, each of the write unit areas comprising memory cells, each of the memory cells configured to store i-bits data, i being equal to or larger than 2; and a controller configured to receive first data and a request for writing the first data from outside of the memory system, the controller configured to write the first data in the first physical block such that each of the memory cells in the first physical block stores only j-bits data, j being smaller than i, the controller configured to manage a correspondence between a physical address of the first physical block and a logical address of the first data stored in the first physical block, the controller configured to receive second data and a request for writing the second data, the controller configured to write the second data in the first physical block such that each of the memory cells in the first physical block stores only j-bits data, the second data having a logical address identical to the logical address of the first data, the controller configured to manage a correspondence between the physical address of the first physical block and the logical address of the second data stored in the first physical block, the controller configured to perform a copy operation, the copy operation comprising reading the second data stored in the first physical block and writing the second data read from the first physical block in the second physical block such that each of the memory cells in the second physical block stores only k-bits data, k being larger than j and equal to or smaller than i, the controller configured to manage a correspondence between a physical address of the second physical block and the logical address of the second data stored in the second physical block.