Patent ID: 7146595

Claim:
A computer readable medium having stored thereon a data structure defining a physical block (pblock) in a hierarchy of pblocks (both parent and child) which defines the same integrated circuit structure by reference to data in a netlist which defines a logical hierarchy, the data defining said pblock comprising: A) a set of pointers to data defining boundary pins of said pblock, said boundary pins for connecting to nets external to the pblock and for connecting to nets internal to the pblock; B) a field containing a pointer to a first parent physical block cellview (pcellview) which contains said pblock; C) a field containing a pointer to a second pcellview data structure owned by said pblock, said second pcellview containing pointers to data which define lists of pins internal to the pblock, nets that connect to the internal pins and boundary pins of the pblock, child pblocks and child instances which have been assigned to said pblock and which define the functionality of said pblock; and D) a field containing coordinates on a floorplan representing a surface of an integrated circuit on which circuits assigned to said pblocks are to be formed, said coordinates to define a geometric shape representing said pblock and the size thereof, said geometric shape being displayed on a computer display of a computer executing a floor planning process.