Patent ID: 7185175

Claim:
A method for providing a bi-directional communication bus between a first processing unit (PU) and a second and third PU each adjacent to the first PU and within M processing units (PUs), wherein the first PU is physically coupled to the second PU with a first Link input and a first Link output and to the third PU with a second Link input and a second Link output, the method comprising the steps of: sending a first output signal from an output of the first PU to the third PU on the second Link output or selectively sending a second output signal received on the first Link input from the second PU to the third PU on the second Link output in response to the first logic state of a first enable signal; selectively sending a third output signal received on the second Link input from the third PU or the first output signal from the first PU to the second PU on the first Link output in response to the first logic state of a second enable signal; and receiving, in an input of the first PU, the third output signal received on the second Link input from the third PU or selectively receiving the second output signal on the first Link input from the second PU when the first enable signal has the first logic state.