Patent ID: 8482972

Claim:
A memory, comprising: a plurality of memory cells, at least one of the memory cells comprising: a memory element having a first end and a second end, the first end being coupled to a first supply voltage line; a first diode having a first end doped with a first type of dopant and a second end doped with a second type of dopant, the first end having a first terminal, the second end having a second terminal, the first terminal being coupled to the second end of the memory element; and a second diode having a first end doped with the first type of dopant and a second end doped with the second type of dopant, the first end having a first terminal, the second end having a second terminal, the second terminal being coupled to the second end of the memory element, wherein the second terminal of the first diode coupled to a second supply voltage line, wherein the first terminal of the second diode is coupled to the second supply voltage line or a third supply voltage line, and wherein the memory element is configured to be programmable into one state by applying voltages to the first, second, and/or third supply voltage lines to conduct the first diode while cutting off the second diode, or into another state by applying voltages to the first, second, and/or third supply voltage lines to conduct the second diode while cutting off the first diode.