Patent ID: 7602026

Claim:
A memory cell in a semiconductor memory device comprising: a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element; wherein the variable resistor element is configured so that the variable resistor body is arranged on the second electrode and the first electrode is arranged on the variable resistor body, and the first electrode contains at least one type of material from precious metals in the platinum group metals, single metals selected from Ag, Al, Cu, Ni, Ti, and Ta or alloys of these, oxide conductors selected from Ir, Ru, Re, and Os, and oxide conductors selected from SRO(SrRuO 3 ), LSCO((LaSr)CoO 3 ), and YBCO(YbBa 2 Cu 3 O 7 ).