Patent ID: 8570061

Claim:
A circuit comprising: a plurality of inputs; an output; a high voltage source; a low voltage source; a first plurality of logic paths connecting the output to the high voltage, wherein each logic path of the first plurality of logic paths comprises two transistors, wherein in response to a majority but not all of the plurality of inputs having a same value, two or more logic paths of the first plurality of logic paths enable current flow between the high voltage source and the output; a second plurality of logic paths connecting the output to the low voltage, wherein each logic path of the second plurality of logic paths comprises two transistors, wherein a first logic path of the second plurality of logic paths comprises a first re-channel MOSFET and a second n-channel MOSFET, and wherein a second logic path of the second plurality of logic paths comprises the second n-channel MOSFET and a third n-channel MOSFET, and wherein a source of the first n-channel MOSFET is connected to the low voltage source and a source of the third n-channel is connected to the low voltage source; a drain of the first n-channel MOSFET is connected to a source of the second n-channel MOSFET and a drain of the third n-channel MOSFET is connected to the source of the second n-channel MOSFET; and, a drain of the second n-channel MOSFET is connected to the output.