Patent ID: 7907442

Claim:
A semiconductor integrated circuit comprising: a readout circuit which detects a difference between a change that appears on a first signal line and another change that appears on a second signal line, according to stored information of a memory cell selected from a plurality of memory cells, thereby to determine the stored information, wherein the readout circuit includes: a first initialization circuit which initializes the first signal line and the second signal line to a first level before the start of a read operation thereof, a preamplifier which amplifies changes in initialization levels of the first and second signal lines respectively upon the read operation and outputs the same therefrom, a data latch circuit which receives a pair of outputs of the preamplifier at input nodes to perform a latch operation, and a second initialization circuit which initializes input nodes of the data latch circuit to a second level before the start of the read operation, and wherein the preamplifier includes: a pair of first MOS transistors one of which receives the first signal line at a gate thereof and couples the first signal line to the corresponding input node of the data latch circuit through an input gate capacitance and the other of which receives the second signal line at a gate thereof and couples the second signal line to the corresponding input node of the data latch circuit through an input gate capacitance, and a pair of second MOS transistors which couples the one first MOS transistor to the first signal line and couples the other first MOS transistor to the second signal line and which is on-operated after the initialization.