Patent ID: 6917366

Claim:
A system to align digital image data, comprising: a plurality of serial data channels, each channel transmitting corresponding serial data, the serial data on one serial channel having skew relative to the serial data on other serial channels; a serial to parallel converter to convert the serial data on each of the plurality of serial data channels into parallel data on corresponding parallel data channels responsive to a serial reference clock; and an alignment circuit adapted to align the parallel data such that no skew is present between the parallel data on one parallel channel and the parallel data on other parallel channels responsive to a pixel clock; wherein the serial to parallel converter generates a pixel clock for each parallel data channel and a parallel reference clock; wherein the alignment circuit comprises: a queue circuit to store the parallel data on each of the parallel data channels responsive to the corresponding pixel clock; and an alignment detection circuit to detect alignment of the parallel data stored in the queue circuit responsive to the parallel reference clock; and wherein the queue circuit for each of the parallel data channels comprises: a plurality of FIFO latches, each FIFO latch to store parallel data responsive to the corresponding pixel clock; a compare circuit to generate a match bit for each word of parallel data by monitoring the parallel data for a code; a register circuit to generate a leading edge signal responsive to the corresponding pixel clock; a counter circuit to generate a write pointer responsive to the corresponding pixel clock; a latch circuit to generate a leading edge pointer by latching the write pointer responsive to the leading edge signal and the corresponding pixel clock; and a multiplexer circuit to receive parallel data stored in the plurality of FIFO latches and output aligned parallel data to a corresponding parallel data channel responsive to a corresponding read pointer.