Patent ID: 7647445

Claim:
A processor bus arrangement in a single chip vector processor, comprising: at least a first and a second data processing units internal to the single chip vector processor, each of which is connected to a system of lines combined as a bus internal to the vector processor, wherein the bus has connection units and bus segments, wherein the bus segments provide line connections to and between the connection units of the vector processor, wherein the bus segments are connected to the bus in a separable manner by means of the connection units so that each bus segment operates as a bus between interconnected data processing units of the vector processor even when isolated from the remaining bus and bus segments, wherein the bus has multiple paths, which unidirectional or bidirectionally perform data transmission, are arranged in the connection unit, wherein a second and a third connection unit are arranged in a chain with a first connection unit as a repeater structure, wherein the connection units of the repeater structure are arranged chained together in one of a star and a ring, and wherein the connection units are arranged to bridge across adjacent connection units.