Patent ID: 7777340

Claim:
A semiconductor device comprising: a semiconductor substrate; a first insulating layer having a first wire-forming region and laminated on the semiconductor substrate; a first metal wiring pattern embedded in the first wire-forming region; a second insulating layer having a second wire-forming region and laminated on the first insulating layer; a second metal wiring pattern embedded in the second wire-forming region; a non-wire-forming region distinct from the second wire-forming region; a wire-opposed region distinct from the first wire-forming region and opposing the second wire-forming region; a non-wire-opposed region distinct from the first wire-forming region and opposing the non-wire-forming region; and first dummy metal patterns embedded both in the wire-opposed region and in the non-wire-opposed region, wherein the first dummy metal patterns are electrically connected with neither the first metal wiring pattern nor the second metal wiring pattern.