Patent ID: 8116126

Claim:
A memory system comprising: a memory cell configured to represent at least two binary values; a bit line coupled to the memory cell; a first comparator coupled to the bit line that compares a first reference value to a value of a parameter of the bit-line; a second comparator coupled to the bit line that compares a second reference value to the value of a parameter of the bit-line; a first timer coupled to the first comparator that measures a time for the parameter of the bit line to decay from a first value to the first reference value; a second timer coupled to the second comparator that measures a time for the parameter of the bit line to decay from the first value to the second reference value; and a logic unit coupled to the first timer and the second timer that selects the time for the parameter of the bit line to decay from the first value to the first reference value in the event it is greater than a minimum time and otherwise selects the time for the parameter of the bit line to decay from the first value to the second reference value.