Patent ID: 7816958

Claim:
A circuit comprising: a phase/frequency detector; a control circuit responsive to the phase/frequency detector and adapted to supply first, second and third control signals, wherein said second control signal is generated after the first control signal is terminated and during a same cycle of a feedback clock signal, and said third control signal is generated after the second control signal is terminated and during the same cycle of a feedback clock signal, wherein a current generated during the second control signal is equal to a sum of currents generated during the first and third control signals, wherein said control circuit comprises: a first pulse-width limiting circuit adapted to limit a width of a first signal received from the phase/frequency detector so as to generate a first pulse-width limited signal; a second pulse-width limiting circuit adapted to limit a width of a second signal received from the phase/frequency detector so as to generate a second pulse-width limited signal; a first slew detector adapted to generate a first slew signal after detecting the first pulse-width limited signal; a second slew detector adapted to generate a second slew signal after detecting the first slew signal; a third pulse-width limiting circuit adapted to limit a width of the first slew signal so as to generate a third pulse-width limited signal; and a fourth pulse-width limiting circuit adapted to limit a width of the second slew signal so as to generate a fourth pulse-width limited signal; and a charge pump responsive to said first, second and third control signals.