Patent ID: 7873687

Claim:
Method for calculating a result of a division with a Floating Point Unit with fused multiply add with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, comprising the following steps: normalization of the dividend and the divisor of the division calculation, loading the C-register with the bit-normalized dividend and divisor while calculating in parallel a shift correction for alignment of the dividend by a control logic, the method characterized in the following steps: loading the fraction of the dividend through the divisor register into the partial remainder register of the divide while applying the calculated shifting for alignment by using the multiplier associated to the subtractor, loading the fraction of the divisor into the divisor register, performing a division calculation by the divide processor by the required number of iterations, loading the redundant parts of remainder and quotient into the main adder of the Floating Point Unit and build the explicit raw quotient result, which is already hexadecimal normalized.