Patent ID: 7974135

Claim:
A non-volatile semiconductor memory device comprising a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit, and wherein the two verify-read operations in the erase-verify mode are as follows: a first verify-read operation is for verifying the erase state of all memory cells in such a way as to detect whether the bit line is charged up or not under the condition that (a) all word lines coupled to control gates of the memory cells in the NAND cell unit are applied with verify-read voltage, (b) the source line is applied with bit line charging voltage, (c) the second select gate transistor is turned on, and (d) the first select gate transistor is turned on later than the second select gate transistor; and a second verify-read operation is for verifying the erase state of the memory cell disposed adjacent to the first select gate transistor after the first verify-read operation in such a way as to temporally turn off the second select gate transistor, and make the bit line discharged, and then turn on again the second select gate transistor, thereby detecting whether the bit line is charged up or not under the condition that (e) the bit line charging voltage applied to the source line and the verify-read voltage applied to the word lines are kept as it is, and (f) the first select gate transistor is kept on.