Patent ID: 7015090

Claim:
A method of manufacturing a semiconductor device comprising: semiconductor elements; element isolation trenches each for isolation between the semiconductor elements formed in a MISFET formation region arranged in a first well; capacitor formation trenches formed in capacitor formation regions arranged in a second well separated from the first well; and capacitor electrodes each formed inside the capacitor formation trenches via a dielectric film, the method comprising steps of: (a) forming the capacitor formation trenches in capacitor formation regions arranged in said second well separated from said first well by a step of forming the element isolation trenches in a semiconductor substrate; (b) embedding insulating films in the element isolation trenches formed in the MISFET formation region arranged in the first well and in the capacitor formation trenches; (c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the element isolation trenches; and (d) forming gate electrodes in the MISFET formation region by a step of forming capacitor electrodes in the capacitor formation regions.