Patent ID: 7286430

Claim:
A semiconductor device comprising: a data line; a plurality of memory cells coupled to the data line and storing a first information or a second information according to write data; a dummy data line; a plurality of first dummy cells and second dummy cells coupled to the dummy data line, the plurality of first dummy cells storing the first information and the plurality of second dummy cells storing the second information; a first load circuit coupled between the data line and a first voltage; a second load circuit coupled between the dummy data line and the first voltage; and a third load circuit coupled between the dummy data line and the first voltage, wherein a signal read out from a selected one of the plurality of memory cells is inputted to the first load circuit, and wherein a signal read out from a selected one of the plurality of first dummy cells and a selected one of the plurality of second dummy cells is inputted to the second load circuit and the third load circuit.