Patent ID: 7118973

Claim:
A method of forming a MOS transistor on a semiconductor material of a first conductivity type, the method comprising: forming a layer of composite material of the first conductivity type on the semiconductor material, the layer of composite material including a first layer, a second layer that contacts a top surface of the first layer, a third layer that contacts a top surface of the second layer, and a fourth layer that contacts a top surface of the third layer, the first layer including silicon and carbon, the second layer including silicon and being substantially free of carbon, the third layer including silicon and carbon, the fourth layer including silicon and being substantially free of carbon; forming an insulation layer on the layer of composite material; forming a layer of conductive material on the insulation layer; etching the layer of conductive material to form a gate; and forming spaced-apart source and drain regions of a second conductivity type in the layer of composite material on opposite sides of the gate, an isolation region adjoining the semiconductor material, the isolation region having a top surface, the semiconductor material having a top surface that is substantially coplanar with the top surface of the isolation region.