Patent ID: 6996598

Claim:
A calculation circuit for the division of a fixed-point input signal, which comprises a sequence of digital data values having a width of n bits, by an adjustable division factor 2 a for generating a divided fixed-point output signal, the circuit comprising: a signal input for receiving a data value sequence of the fixed-point input signal; a first addition circuit for adding the digital data value input at the signal input to a data value stored in a register to form a digital first summation data value comprising a width of max (n, a+1)+1 bits; a shift circuit for shifting the first summation data value by a data bits towards the right to output the max (n, a+1)−a+1 more significant data bits of the first summation data value; a logic circuit having an AND gate configured to logically AND the a less significant data bits of the first summation data value with a logic combination data value to generate a first logically combined data value (d v1 ) and having an OR gate configured to logically OR the a less significant data bits of the first summation data value with an inverted logical combination data value to generate a second logically combined data value (d v2 ) wherein depending on a sign of the first summation data value the first logically combined data value (d v1 ) or the second logically combined data value (d v2 ) is output for storage in the register; a second addition circuit configured to provide as an output the data value output by the shift circuit added to a value one for eliminating the DC signal component to form a second summation data value, depending on a sign of the first summation data value; and a signal output for outputting the sequence of the second addition circuit output as a divided fixed-point output signal.