Patent ID: 7962881

Claim:
A method for placing wiring channels and via connections between wiring channels within multiple layers of an integrated circuit, comprising: creating a model of the integrated circuit on a computing device; placing, in the model on the computing device, a plurality of via connections between wiring channels on a first layer of the integrated circuit and wiring channels on a second layer of the integrated circuit, wherein each of the via connections connect together one wiring channel on the first layer and one wiring channel on the second layer, wherein one of the wiring channels on the first and second layers is blocked if the channel has one of the via connections located along its length and wherein one of the wiring channels is available if the channel does not have one of the via connections located along its length; and relocating in the model on the computing device certain one or more of the via connections by no more than some amount of wiring channels to thereby maximize the number of available wiring channels in both the first and second layers; and defining one or more areas within the integrated circuit where there exists a global routing congestion condition; wherein for each of the one or more areas with a horizontal global routing congestion condition, increasing a spacing between the via connections in a vertical direction when viewing the wiring channels from a top view; and wherein for the one or more areas with a vertical global routing congestion condition, increasing a spacing between the via connections in a horizontal direction when viewing the wiring channels from a top view.