Patent ID: 8542525

Claim:
A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction, wherein either a word write bias voltage and a source write bias voltage, is applied respectively to the word line and source line connected to a selected MRAM cell, and the bit line connected to the selected MRAM cells is grounded, and a bit bias voltage is applied to bit lines connected to other MRAM cells in the same row as the selected MRAM cell, the bit bias voltage having a value corresponding substantially to the word write bias voltage, and the word lines connected to remaining MRAM cells are grounded, or a word read bias voltage is applied via the word line to the gate of the select transistor connected to the selected MRAM cell, and a bit read bias voltage and a source read bias voltage is applied to the bit line and source line connected to the selected MRAM cell, and a bit bias voltage having a value corresponding to the source read bias voltage is applied to bit lines connected to other MRAM cells in the same row as the selected MRAM cell, and the word lines connected to remaining MRAM are grounded.