Patent ID: 7155694

Claim:
A method for generating a layout for an integrated circuit (IC) based on an IC design describing the IC as comprising cell instances forming a plurality of modules, including a master module and at least one clone module identical to the master module, the cell instances being linked to one another by nets, the method comprising the steps of: a. generating a floor plan for the IC, defining positions and dimensions of a plurality of separate areas of the IC, each area corresponding to a separate module of the IC, including a master module area corresponding to the master module, and a separate clone module area corresponding to each clone module, the master module area and each clone module area being identical in size and shape; b. generating a trial placement plan for an entire IC describing each cell instance as residing at a separate position within the IC, wherein selection of cell instance positions within the master module is sequentially executed a predefined portion at a time to be biased toward minimizing lengths of nets linking those cell instances to other cell instances, and wherein cell instance placement within each clone module area is collectively established by periodically copying cell placement within each predefined portion of the master module area as it is sequentially executed; and c. generating a trial routing plan for the entire IC, defining approximate routes for nets linking cell instances forming the plurality of modules including the master module and the at least one clone module.