Patent ID: 7206891

Claim:
A memory controller system comprising: a plurality of system buses; a multi-port memory controller comprising a plurality of system bus ports and a memory port; a plurality of error correcting code (ECC) encoders, wherein each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller, wherein each ECC encoder is adapted to receive write data on an ECC input, which has an ECC block width, generate a set of ECC bits based on the write data, and apply the set of ECC bits with the write data on an ECC output; and for each ECC encoder, a respective line buffer coupled between the respective system bus and the ECC input, which gathers write data from the system bus into groups of write data, corresponding to respective memory addresses, and applies each group of write data to the ECC input as an ECC block if the group has a width that is equal to the ECC block width, and if the group of write data has a width that is less the ECC block width, then the line buffer receives read data from the memory address through the memory controller, merges the read data with the group of write data to form the ECC block and then applies the ECC block to the ECC input.