Patent ID: 7404166

Claim:
A method for mapping a netlist of an integrated circuit to a design, said method comprising steps of: using chaos algorithm to obtain most favorable places in said design for cells from said netlist, said using step comprising: assuming that a coordinate of said each cell of said netlist is a center of said template; and calculating, on each cycle, a pseudo coordinate of each wire w as a center of coordinates of all pins of said netlist connected to said wire w and cells that have pins connected to said wire w, and a coordinate of each cell c as a center of pseudo coordinates of all wires connected to pins of said cell c, utilizing Kuhn's algorithm to assign each cell of said netlist a cell in a template having a set of predefined cells so that, for said each cell of said netlist, its place in said template is as close as possible to its place obtained by said chaos algorithm; and applying simulating annealing optimization technique to reduce a sum of wire length of said design.