Patent ID: 8332610

Claim:
A system on chip comprising: N components, wherein N is an integer greater than one; and a storage module comprising: a first memory including M blocks of static random access memory, wherein M is an integer greater than one, and wherein one of the M blocks is dual-ported; a control module configured to (i) generate a first assignment of the M blocks to the N components during a first period and (ii) generate a second assignment of the M blocks to the N components during a second period, wherein the first assignment is different from the second assignment, and wherein the second period is subsequent to the first period; and a connection module configured to dynamically connect the M blocks to the N components according to each of the first assignment and the second assignment, wherein the connection module is configured to selectively connect the one of the M blocks to two of the N components, wherein the first period corresponds to a development phase of the system on chip, wherein the second period corresponds to an operational phase of the system on chip, wherein the first assignment assigns first ones of the M blocks to first ones of the N components to emulate read-only memory, and wherein the second assignment reassigns the first ones of the M blocks to second ones of the N components as one of cache or temporary storage.