Patent ID: 7886238

Claim:
A method for an integrated circuit layout, the method comprising: generating the integrated circuit layout including at least two layers of wire interconnect to form net segments and at least one via contact layer to couple net segments in the wire interconnect together; with a processor, performing a yield analysis of the net segments in the integrated circuit layout to form yield scores for the net segments in the integrated circuit layout, including checking a wire width of each net segment and checking a wire spacing of each net segment from other net segments; and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect the yield scores of the net segments in the integrated circuit layout, including determining a first wire opacity for each net segment in response to the wire width check and a second wire opacity for each net segment in response to the wire spacing check, weighting the first wire opacity and the second wire opacity, and summing the weighted first wire opacity and the weighted second wire opacity together to generate a level of opacity for each net segment.