Patent ID: 7154293

Claim:
A high-speed transmitter circuit comprising: an input separator circuit for inputting a signal for a single-wire circuit and separating the signal into two signals; a two-wire transmitter circuit including at least one pair of logic gates in which a P-channel CMOS transistor and an N-channel CMOS transistor whose size is different from that of the P-channel CMOS transistor are complementarily connected, outputting a first signal speeded up a rising transition time thereof from one of the logic gates and outputting a second signal speeded up a falling transition time thereof from the other of the logic gates; and an output converter circuit receiving in parallel the first signal and the second signal outputted from the two-wire transmitter circuit and converting the signals into a signal for the single-wire circuit, the output converter circuit picking up an edge of the rising output signal with speeded-up rising transition time at the first logic gate and an edge of the falling output signal with speeded up falling transition time at the second logic gate, respectively and converting them into a signal for the single-wire circuit, the output converter circuit comprising: a first transfer gate for passing the rising edge of the output signal with speeded-up rising transition time at the first logic gate to supply it to a single-wire output terminal, a second transfer gate for passing the falling edge of the output signal with speeded-up falling transition time at the second logic gate to supply it to the single-wire output terminal, and a control circuit for repeatedly performing the following: opening the first transfer gate in the state that the output signals of both of the first logic gate and the second logic gate are logic level 0 and latching the opening state; supplying the rising edge to a logic level 1 of the output signal of the first logic gate from the opening first transfer gate to the signal-wire output terminal and closing the first transfer gate after a predetermined period; alternatively opening the second transfer gate to supply a signal at a logic level 1 outputted from the subsequent second logic gate to the signal-wire output terminal; opening the second transfer gate in the state that the output signals of both of the first logic gate and the second logic gate are logic level 1 and latching the opening state; supplying the falling edge to a logic level 0 of the output signal of the second logic gate from the opening second transfer gate to the single-wire output terminal and closing the second transfer gate after a predetermined period; alternatively opening the first transfer gate to supply a signal at a logic level 0 outputted from the subsequent first logic gate to the single-wire output terminal.