Patent ID: 8354697

Claim:
A semiconductor integrated circuit device comprising an element isolation region and a first active region defined by the element isolation region in a semiconductor substrate, wherein the first active region is formed in the semiconductor substrate and includes a first well of a first conductivity type; wherein the first active region further includes a first region which extends in a first direction and in which a plurality of MISFETs is formed, and a second region which extends in the first direction and feeds power to the MISFETs; wherein each gate electrode of the MISFETs extends in a second direction intersecting the first direction; wherein a plurality of first plugs is formed in each of the gate electrodes of the MISFETs, respectively; and wherein in the second region, a plurality of second plugs is placed along the first direction, and the second plug is not formed within a range less than 2.5 times a diameter of the first plug from a center of the first plug.