Patent ID: 8073825

Claim:
A data correction method, the method comprising: receiving, by a processor, a first packet, wherein the first packet comprises a plurality of first data bits and cyclic redundancy check (CRC) information; determining that the first packet is an erroneous packet according to the CRC information; receiving, by the processor, a second packet, wherein the second packet comprises a plurality of second data bits and the CRC information; determining that the second packet is an erroneous packet according to the CRC information; receiving, by the processor, a third packet, wherein the third packet comprises a plurality of third data bits and the CRC information; determining that the third packet is an erroneous packet according to the CRC information; retrieving each of the first data bits and each of the second data bits to perform an exclusive-OR (XOR) logical operation thereon to generate a first error pattern; retrieving two of each of the first data bits, each of the second data bits and each of the third data bits to perform the XOR logical operation thereon to generate a second error pattern; performing an OR logical operation on the first error pattern and the second error pattern to generate a third error pattern; and calculating a correct packet according to the third error pattern and one or more of the first packet, the second packet and the third packet.