Patent ID: 7236205

Claim:
A scan line conversion circuit for converting the number of scan lines of an input interlace video signal constituted by a plurality of fields each having scan lines, said scan line conversion circuit comprising: a first memory for memorizing said interlace video signal, a first sequential scan line conversion circuit for generating a scan line of (i+½) lying between a scan line i and a scan line of (i+1) in a single field of the memorized interlace video signal, a second sequential scan line conversion circuit for generating a scan line of (i+1+½) lying in between said scan line of (i+1) and a scan line of (i+2) in said single field, and an adding circuit for adding the respective ones of said scan line i, said scan line of (i+½), said scan line of (i+1), said scan line of (i+1+½) and said scan line of (i+2) so as to generate a single video signal.