Patent ID: 8671232

Claim:
A system for migrating at least one stash transaction between a plurality of processor cores of a multicore processor system, wherein each of the plurality of cores includes a cache register, the system comprising: a main memory for storing an input/output memory management unit (IOMMU) mapping table that includes a mapping between a logical input/output (I/O) device number (LIODN) corresponding to an I/O device and a corresponding stash transaction destination identification (ID), wherein the stash transaction destination ID includes a cache register ID associated with a cache register of one of the cores of the plurality of cores; a stash transaction migration management unit (STMMU), coupled to the main memory, for determining a first core ID of a first core that executes a first thread associated with a first I/O device when the first thread is scheduled-out from the first core, wherein the first I/O device has a corresponding first stash transaction destination ID stored in the IOMMU mapping table, determining a second core ID of a second core that executes the first thread after the first thread is scheduled-in, comparing the first and second core IDs, updating a stash transaction destination ID field of the IOMMU mapping table corresponding to the first I/O device when the first and second core IDs are different to replace the first stash transaction destination ID with a second stash transaction destination ID, wherein the stash transaction destination ID field for the first I/O device stores the first stash transaction destination ID, and updating a second cache register ID associated with a cache register of the second core when the first and second core IDs are different to replace the second cache register ID with a first cache register ID associated with a cache register of the first core; a frame manager for generating a first data frame, initiating a direct memory access (DMA) transaction for storing the first data frame in an external buffer of the main memory, and initiating the at least one stash transaction; and an IOMMU, coupled to the main memory, the frame manager, and the plurality of cores, for validating the DMA transaction initiated by the frame manager using a LIODN of the frame manager and determining a stash destination for the at least one stash transaction by accessing the IOMMU mapping table.