Patent ID: 7115950

Claim:
A semiconductor device comprising: a multi-layer SOI substrate comprising a first insulating layer, a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked in this order on a support substrate; a first MOS transistor formed on and in the second semiconductor layer of the SOI substrate; a contact portion for applying to the first semiconductor layer of the multi-layer SOI substrate different bias voltages in an operating state and a standby state of a semiconductor circuit including the first MOS transistor, the first MOS transistor including source and drain regions of a second conductivity type, a channel of the first conductivity type, and wherein an impurity diffusion layer of the first conductivity type is formed in the first semiconductor layer of the multi-layer SOI substrate under at least the entire source, drain and channel regions, so that the impurity diffusion layer is of the same conductivity type as the first semiconductor layer of the multi-layer SOI substrate, wherein said source and drain regions as well as said channel are all formed in the second semiconductor layer of the multi-layer SOI substrate; wherein the contact portion for applying the different bias voltages is formed in a device isolation region and comprises a contact hole in the second semiconductor layer and the buried insulating film, said contact hole reaching the impurity diffusion layer so that the different bias voltages are applied to the SOI substrate via the impurity diffusion layer, and wherein a conductor of the contact portion in the contact hole is electrically insulated from the second semiconductor layer by at least said device isolation region which includes at least one insulator; a second MOS transistor, wherein the first and second MOS transistors are of different conductivity types on the SOI substrate and are adjacent each other, and wherein bias voltages applied via said contact portion for the first transistor and a contact portion for the second transistor are changed between the active and standby states so that active regions of the first and second transistors are substantially completely depleted in the standby state; and wherein the first MOS transistor comprises a P-type well and the second MOS transistor comprises an N-type well formed in the first semiconductor layer of the multi-layer SOI substrate, and wherein the P-type well of the first MOS transistor and the N-type well of the second MOS transistor are substantially electrically isolated from each other, and wherein the impurity diffusion layer makes up at least part of the P-type well of the first MOS transistor.