Patent ID: 8115321

Claim:
An integrated circuit comprising: a plurality of probe pads arranged in a staggered manner in a core region of the integrated circuit, the core region including logic circuitry therein; a plurality of bond pads in an Input/Output (I/O) region surrounding the core region, the I/O region being configured to enable the core region to communicate with at least one external circuit through the plurality of bond pads; and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area in the core region, wherein at least one of a dimension of the die metal interconnect and a position of the die metal interconnect between the probe pad area and the bond pad area is variable, and wherein the die metal interconnect separating the bond pad area and the probe pad area is of a variable length based on the staggered positions of the plurality of bond pads in the I/O region and the staggered positions of the plurality of probe pads in the core region.