Patent ID: 6909187

Claim:
A conductive wiring layer structure, applied to a chip comprising a substrate, on which a core circuit and a bonding pad area are formed, whereon an insulation layer with a plurality of openings is formed to cover the core circuit and the bonding pad area, the conductive wiring layer structure comprising: a plurality of first conductive wiring regions, located in the bonding pad area, wherein each of the first conductive wiring regions comprises a plurality of first dielectric layers and a plurality of patterned first conductive wiring layers alternately overlaying each other, and the first conductive wiring layers are gradually wider approaching the substrate, and gradually narrower away from the substrate; and a plurality of second conductive wiring regions, alternately arranged in the bonding pad area with the first conductive wiring regions, wherein each of the second conductive wiring regions comprises a plurality of second dielectric layers and a plurality of patterned second conductive wiring layers alternately overlaying each other, and the second conductive wiring layers are gradually narrower approaching the substrate, and gradually wider away from the substrate.