Patent ID: 7098717

Claim:
A clamp circuit comprising: a first low voltage, thin oxide NMOS transistor having a source, a drain and a gate, said source and drain being connected between a first node and a second node, a trigger circuit comprising a timing element and an even number of series-connected inverters connected to the gate of the first NMOS transistor, the timing element comprising a capacitive element and a resistive element connected in series between the first node and the second node, an input to the inverters being connected to a third node to which the capacitive element and the resistive element are connected, the capacitive element being connected between the first node and the third node, and an additional MOS transistor having a source, a drain and a gate in which the source and drain are connected across the capacitive element, and the gate is connected to an output from an odd number of series-connected inverters.