Patent ID: 6979611

Claim:
A method for fabricating a contact plug in a semiconductor device having a silicon substrate for minimal resistance between the contact plug and the silicon substrate, which comprises the steps of: forming a device isolation film defining a device region in a silicon substrate; depositing a gate electrode material film on the silicon substrate and pattering the deposited gate electrode material film so as to form a gate electrode on the silicon substrate; implanting impurity ions into the silicon substrate so as to form junction regions in the silicon substrate; forming an interlayer insulating film on the silicon substrate and selectively patterning the interlayer insulating film so as to partially expose the surface of the silicon substrate; and forming a two-layered contact plug consisting of a first contact layer of monocrystalline silicon grown on the interlayer insulating film including the exposed surface of the silicon substrate at a temperature less than 700 degrees Celsius and a second contact layer of polycrystalline silicon on the first contact layer.