Patent ID: 8153492

Claim:
A method for manufacturing an integrated circuit, comprising: forming a field effect transistor gate structure between a source region and a drain region in a semiconductor substrate, the gate structure including a sacrificial material between a pair of sidewall spacers; forming an insulation layer over the gate structure; polishing the insulation layer until the sacrificial material is exposed; removing the sacrificial material, thereby forming a cavity having sidewalls defined by the sidewall spacers and exposing the semiconductor substrate between the sidewall spacers; forming a recess in the semiconductor substrate within the cavity, whereby the recess forms a self-aligned curved channel region; conformally depositing a gate dielectric layer overlying the insulation layer and all surfaces within the cavity including the sidewalls and the curved channel region; and forming a gate electrode overlying the gate dielectric layer within the cavity, whereby the gate dielectric layer conformally lines the interface between the sidewall spacers and the gate electrode.