Patent ID: 8049827

Claim:
A thin film transistor array substrate, comprising: an insulating substrate; a plurality of scan lines formed on the insulating substrate; an insulating layer formed on the scan lines and the insulating substrate; a plurality of data lines formed on the insulating layer; and a plurality of pixels arranged in an array of rows and columns, wherein the pixels in each row are aligned in a row direction, the pixels in each column are aligned in a column direction, and the pixels are separated from each other by the scan lines and the data lines, and each pixel comprising: a thin film transistor electrically connected to at least one of the scan lines and at least one of the data lines; and a pixel electrode having at least one opening that extends from the periphery to the inside of the pixel electrode and having at least one extension part that extends in the row direction into an opening of a neighboring pixel electrode in the same row, wherein each of the scan lines alternately controls one of the pixel electrodes in a first row and one of the pixel electrodes in a second row immediately adjacent to the first row, and the opening is formed in the middle of the pixel electrode and the thin film transistor is formed near one side of the pixel electrode.