Patent ID: 7069574

Claim:
A method for synchronizing a system including a host computer having a microprocessor, a receiver circuit and a decoder circuit, the method comprising: (a) coupling the receiver circuit with the decoder circuit and the microprocessor, wherein the receiver circuit, decoder circuit, and microprocessor each comprise separate nodes of a bus in the host computer; (b) maintaining synchronization between the receiver circuit and a transmitter external to the host computer by receiving a first transport packet from the transmitter with the receiver circuit; capturing a first system time clock (STC) timestamp at a start of receiving the first transport packet, the first STC timestamp being captured into a latch in the receiver circuit; obtaining a program clock reference (PCR) timestamp from the transport packet; comparing the first STC timestamp to the PCR timestamp to generate a comparison result; and adjusting a STC frequency based on the comparison result by using firmware within the receiver circuit; (c) capturing, with the decoder circuit, a second STC timestamp; and (d) adjusting a system timestamp with an offset based on a message delay time between the second STC timestamp and a last PCR timestamp received maintain synchronization between the decoder circuit and the receiver circuit.