Patent ID: 8362615

Claim:
A memory comprising: a first dielectric layer; a first polysilicon layer disposed on the first dielectric layer; a first buried diffusion and a second buried diffusion separately disposed in the first polysilicon layer; a first charge storage structure disposed on the first polysilicon layer and positioned between the first buried diffusion and the second buried diffusion; a first gate disposed on the first charge storage structure; a control device, wherein in one cross-section of the control device and the first poly silicon layer, the control device is disposed directly under the first polysilicon layer; a second dielectric layer covering the first gate, the first charge storage structure and the first polysilicon layer; a plug disposed on the first polysilicon layer and electrically connected to the first polysilicon layer; a voltage source; and wherein the plug penetrates the second dielectric layer, is exposed at a surface of the second dielectric layer and is connected to the voltage source.