Patent ID: 8803782

Claim:
A bidirectional shift register, comprising: a shift register portion including unit register circuits cascaded in m stages, where m is an integer which is equal to or larger than 3, for outputting an output pulse P k in a k-th stage, where k is an integer which satisfies 1≦k≦m, in a shift order which is one of a forward direction and a reverse direction; a clock signal generating portion for supplying n-phase clock pulses to the respective stages of the shift register portion, where n is an integer which is equal to or larger than 3, in sequence in the forward direction in forward shift operation of the shift register portion and in the reverse direction in backward shift operation; and a trigger signal generating portion for generating a forward direction trigger signal at the start of the forward shift operation and generating a reverse direction trigger signal at the start of the backward shift operation, the unit register circuit in a k-th stage including forward and reverse direction set terminals, forward and reverse direction reset terminals, a set circuit for setting a reference point of the unit register circuit to a first potential when a set signal is input to one of the set terminals, a reset circuit for setting the reference point to a second potential when a reset signal is input to one of the reset terminals, and an output circuit for bootstrapping the reference point and outputting the output pulse P k from an output terminal in synchronization with the n-phase clock pulse which is input to the unit register circuit with the reference point of the unit register circuit being at the first potential, where variables given as αf, αb, βf, and βb are natural numbers which satisfy both αf<βb<n and αb<βf<n, the set circuit in the k-th stage being input the output pulse P k−αf when k>αf and the forward direction trigger signal when k≦αf to the forward direction set terminal as the set signal and being input the output pulse P k+αb when k≦m−αb and the reverse direction trigger signal when k>m−αb to the reverse direction set terminal as the set signal, and the reset circuit in the k-th stage being input the output pulse P k+βf , where k≦m−βf, to the forward direction reset terminal as the reset signal after the output pulse P k ends and being input the output pulse P k−βb , where k>βb, to the reversed direction reset terminal as the reset signal after the output pulse P k ends, the forward direction trigger singnal being input to the forward direction reset terminal in each of (m−βf +1)th to m-th stages as the reset signal, and the reverse direction trigger signal being input to the reverse direction reset terminal in each of first to βb-th stages as the reset signal.