Patent ID: 7338875

Claim:
A method of fabricating a p-n junction in an electronic device comprising: forming a slot region for a doped polycrystalline semiconductor plug material within an outer periphery of an etched window region, said window region formed by etching a film stack residing on a topmost surface of a semiconductor substrate, said substrate having a first conductivity type; filling said slot region with said polycrystalline semiconductor plug material; depositing a dielectric separation layer over said polycrystalline semiconductor plug material and on an uppermost surface of said film stack; forming a dopant region in an area of said substrate located within a region circumscribed by said slot region; depositing a spacer over said dielectric separation layer; etching said spacer and said dielectric separation layer anisotropically to form a dielectric boot shape extending radially inward on a lower edge of said dielectric separation layer, said lower edge being a portion of said dielectric separation layer proximal to said substrate; redistributing a dopant from said polycrystalline semiconductor plug into said substrate; etching through any remaining film layers within a region substantially circumscribed by said dielectric boot to said topmost surface of said substrate; and depositing an emitter polycrystalline semiconductor layer over said topmost surface of said substrate.