Patent ID: 7218546

Claim:
An integrated circuit device comprising: a memory cell block comprising memory cells connected in series, the memory cell comprising a cell transistor and a ferroelectric capacitor, the cell transistor including a current path and a gate which is connected to a word line, and the ferroelectric capacitor including a first electrode and a second electrode, one end of the current path of the cell transistor being connected to the first electrode, and the other end of the current path of the cell transistor being connected to the second electrode; a word line selecting circuit which selects the word lines connected to the cell transistors in sequence from a memory cell at one end of the memory cell block to a memory cell at the other end of the memory cell block, in response to address signals during an active cycle; and a driving circuit which applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period for which the word lines connected to the cell transistors are selected in sequence by the word line selecting circuit.