Patent ID: 7548080

Claim:
A method for optimizing a burn-in process of an integrated circuit, comprising: performing a plurality of different portions of the burn-in process at a predetermined maximum burn-in voltage; selecting specific input conditions for each of the plurality of different portions of the burn-in process to drive changes in the integrated circuit that enhance the burn-in process, wherein the changes include an increase in a threshold voltage of NFETs and PFETs in the integrated circuit and a corresponding decrease in a power dissipation of the integrated circuit; and adjusting a burn-in temperature and the input conditions applied to the integrated circuit during the plurality of different portions of the burn-in process of the integrated circuit, while maintaining the power dissipation of the integrated circuit below a predetermined maximum power dissipation; wherein adjusting a burn-in temperature and the input conditions comprises: performing an initial burn-in of the integrated circuit at an initial burn-in temperature and a set of input conditions, wherein the initial burn-in temperature is approximately within the range of 18 to 28 degrees Celsius; determining if the power dissipation of the integrated circuit is below the predetermined maximum power dissipation; and in the case that the power dissipation of the integrated circuit is below the predetermined maximum power dissipation, incrementally increasing the burn-in temperature from the initial burn-in temperature until the predetermined maximum power dissipation is reached to optimize the burn-in process.