Patent ID: 7795953

Claim:
A voltage step-down circuit comprising: an input terminal to which an external power-supply voltage is input; an output terminal from which an internal power-supply voltage that is lower than the external power-supply voltage is output; a first PMOS that is connected to the input terminal and is turned ON during an active state and turned OFF during a standby state; a first NMOS having: a drain that is connected to the input terminal through the first PMOS, a gate to which a control voltage is input, and a source that is connected to the output terminal; a second NMOS having: a drain that is connected to the input terminal, a gate to which the control voltage is input, and a source that is connected to the output terminal; and a current control circuit that sinks a control current from the output terminal to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.