Patent ID: 7921400

Claim:
A method for generating an integrated circuit design comprising: selecting, on a computer, logic cells from a cell library so as to define a first integrated circuit design, the cell library including a first set of logic cells and a second set of logic cells, each cell in the second set of logic cells having a higher soft error resistance than a corresponding cell in the first set of logic cells, each cell in the second set of logic cells performing the same function as the corresponding cell in the first set of logic cells and each cell in the second set of logic cells having the same cell size as the corresponding cell in the first set of logic cells, the first integrated circuit design including logic cells from the first set of logic cells and not including logic cells from the second set of logic cells; and generating, on the computer, a soft error resistant design by replacing some of the logic cells in the first integrated circuit design with corresponding logic cells in the second set of logic cells, the soft error resistant design having higher soft error resistance than the first integrated circuit design, having the same number of logic cells as the first integrated circuit design and each replaced logic cell in the first integrated circuit design replaced by a corresponding cell in the second set of logic cells that has the same function and the same cell size.