Patent ID: 7366869

Claim:
A processing system, comprising: a translation lookaside buffer (TLB) configured to map a contiguous block of virtual memory to physical memory, and provide a size attribute indicating the size of the contiguous block of virtual memory; and a processor configured to vary the size of the contiguous block of virtual memory and the corresponding physical memory, and vary the size attribute accordingly, wherein the processor is further configured to vary the size of the contiguous block of virtual memory by consolidating a first block of virtual memory with a second block of virtual memory in response to a determination that both the first and second blocks of virtual memory are contiguous, and the corresponding of physical memory is also contiguous, wherein the processor is further configured to map the first and second blocks of virtual memory to their corresponding blocks of physical memory by mapping the page address for the first block of virtual memory to the page address for its corresponding block of physical memory, the page address for the first block of virtual memory being lower than the page address for the second block of virtual memory.