Patent ID: 8134152

Claim:
A CMOS thin film transistor arrangement, comprising: a substrate; a poly-silicon layer arranged on the substrate, the poly-silicon layer having source and drain regions separated by a channel region at a center portion of the poly-silicon layer, the poly-silicon layer being P-type; a gate insulating layer arranged on the poly-silicon layer; a gate electrode arranged on a portion of the gate insulating layer that corresponds to the channel region of the poly-silicon layer; an intermediate insulating layer arranged on the gate electrode and on the gate insulating layer; an oxide semiconductor layer arranged on a portion of the intermediate insulating layer that corresponds to the gate electrode; a passivation layer arranged on the oxide semiconductor layer to entirely cover the oxide semiconductor layer, the passivation layer being perforated by a plurality of apertures; first source and drain electrodes arranged on the passivation layer and contacting the source and drain regions respectively of the poly-silicon layer via ones of the apertures; and second source and drain electrodes arranged on the passivation layer and contacting portions of the oxide semiconductor layer via ones of said apertures.