Patent ID: 7436703

Claim:
A flash memory device formed from a substrate, the device comprising: strings of transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate; a plurality of wordlines perpendicular to the axes of the strings, each wordline of the plurality situated above floating gates of the strings; and a booster plate comprising a plurality of fingers and a portion linking the fingers, the fingers running parallel to the wordlines and located between adjacent wordlines, the plurality of wordlines having a top surface approximately a distance from a reference plane that is parallel to the top surfaces of the wordlines, the plurality of fingers having a top surface also approximately the distance from the reference plane, a floating gate associated with a selected word line of the plurality of word lines is read by applying a first voltage to the selected word line while applying a read voltage to unselected word lines of the plurality of word lines while applying a voltage higher than the read voltage to the booster plate.