Patent ID: 8368176

Claim:
A semiconductor device comprising: a substrate; a transistor formed in said substrate; a multilayer interconnect layer formed over said substrate and said transistor; and a capacitive element formed in said multilayer interconnect layer, wherein said capacitive element includes a lower electrode including a metal, a dielectric film, formed over said lower electrode, which is made of a metal oxide film, and an upper electrode formed over said dielectric film, said lower electrode includes an oxide layer having a thickness of 2 nm or less over the surface layer, said dielectric film includes at least a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in said first phase in the bulk state, wherein said first phase is a monoclinic phase, and said second phase is a tetragonal phase, and said second phase has a higher relative permittivity than that of said first phase.