Patent ID: 8145965

Claim:
A test apparatus for testing a device under test, comprising: a performance board on which the device under test is placed; an additional board configured to be added to the performance board, a capture memory, provided on the additional board, that stores thereon an output pattern received from the device under test in accordance with a first reference clock signal input to the additional board and; a header detecting section, provided on the additional board, that reads the output pattern from the capture memory in accordance with a second reference clock signal input to the additional board, detects a portion matching a predetermined header pattern in the output pattern, and outputs the output pattern, the first reference clock signal being a higher speed clock signal than the second reference clock signal; and a judging section provided outside the additional board that receives the output pattern that is output from the header detecting section, judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.