Patent ID: 8638589

Claim:
An operating method for a memory unit, the memory unit comprising a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region, the well region comprising an active region, the select gate formed fully on the active region, the first gate and the second gate formed partially on the active region at a first side of the select gate, the oxide nitride spacer filled between the first gate and the second gate, the first diffusion region formed at a second side of the select gate, and the second diffusion region formed at the first side of the select gate, the operating method for the memory unit comprising: during a programming operation, coupling a breakdown voltage to the second diffusion region through a first channel region formed under the select gate, and applying a programming voltage to the first gate and the second gate sequentially or simultaneously to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.