Patent ID: 7933142

Claim:
An integrated circuit device comprising: a memory cell including at least one transistor, wherein the transistor, in operation, operates in a punch-through, the transistor includes: a first region having impurities to provide a first conductivity type and a first junction; a second region having impurities to provide a first conductivity type and a second junction, wherein in operation, the first and second junctions of the transistor abut or overlap; a body region, disposed between the first region and the second region, having impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and a gate disposed over the body region; and a gate insulator disposed between the gate and the body region wherein the body region includes a storage node which is: (i) located, at least in part, immediately beneath the gate insulator and (ii) separated from portions of the body region by the abutting or overlapping first and second junctions of the transistor; and wherein the memory cell includes at least two data states including (i) a first data state which is representative of a first charge in the body region, and (ii) a second data state which is representative of a second charge in the body region; first circuitry, coupled to the transistor of the memory cell, to: (1) generate first and second sets of write control signals and (2a) apply the first set of write control signals to the transistor to write the first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write the second data state in the memory cell; and wherein, in response to the first set of write control signals, the transistor provides at least the first charge in the body region via impact ionization.