Patent ID: 7638822

Claim:
A memory cell comprising: a long dimension; a short dimension, an aspect ratio of the long dimension to the short dimension being at least 5:1; a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value, the plurality of transistors including at least a first storage transistor of a first type in a first diffusion in a first well of a first type; a second storage transistor of the first type in a second diffusion in the first well of the first type; a third storage transistor of the first type in a third diffusion in a second well of the first type; a fourth storage transistor of the first type in a fourth diffusion in the second well of the first type; and first, second, third, and fourth transistors of a second type formed in at least a first well of a second type, the first well of the second type being disposed between the first well of the first type and the second well of the first type along the long dimension of the memory cell.