Patent ID: 8031504

Claim:
A memory device comprising: a plurality of memory chips divided into the memory chips of a first group and the memory chips of a second group; a first command or address line having a first branch point and a plurality of first bifurcation points, wherein the first branch point is located at the center of the first command or address line, each of the first bifurcation points is correspondingly connected to one of the memory chips of the first group, and the length of a plurality of first line segments between the first bifurcation points are equal; a second command or address line having a second branch point and a plurality of second bifurcation points, wherein the second branch point is located at the center of the second command or address line, each of the second bifurcation points is correspondingly connected to one of the memory chips of the second group, and the length of a plurality of second line segments between the second bifurcation points equal to the length of the first line segment; a third command or address line having a third branch point and two third bifurcation points, wherein the third branch point is located at the center of the third command or address line, the length of a plurality of third line segments between each of the third bifurcation points and the third branch point are equal, one of the third bifurcation points is connected to the first branch point, and the other third birfurcation point is connected to the second branch point; a first terminator connected to the first branch point; and a second terminator connected to the second branch point.