Patent ID: 8904161

Claim:
A memory system including at least one nonvolatile memory device, the memory system comprising: a plurality of power lines to receive a power source voltage; a plurality of power domains respectively connected to the power lines; a plurality of voltage detectors to respectively detect the power lines; a plurality of power boosters respectively to boost an output voltage of a charge cell array and to apply the boosted voltage to a corresponding power line among the power lines such that each of the plurality of power boosters respectively powers a separate power domain of the plurality of power domains; and a reset signal generator to detect voltages from the plurality of power lines and to generate a power-off reset signal to at least a first power domain of a plurality of power domains when at least one of the detected voltages is lower than a first predetermined voltage and supplemental power provided to the plurality of the power lines is not able to maintain a second predetermined voltage and the first predetermined voltage, wherein the at least first power domain of the plurality of power domains comprises a Central Processing Unit (CPU) to perform a power-off reset operation in response to the power-off reset signal so as to turn off write and read operations of the plurality of power domains, other than the at least first power domain, that are in a process of accessing memory devices, the power-off reset signal being generated by the reset signal generator by connecting detected result values outputted from the plurality of voltage detectors by wired-OR circuitry, wherein the charge cell array comprises at least one charge cell which charges electric charges.