Patent ID: 7509561

Claim:
A parity checking system for continuous parity checking of memory cells of a memory cell array configured to store an original payload data word of M bits, comprising: a plurality of parity checking circuits, where each parity checking circuit is connected to a corresponding memory cell of the memory cell array and configured to continuously check a parity of the corresponding memory cell, each parity checking circuit comprising: a first parity input and a second parity input; a first parity output and a second parity output; a first transistor connected between the first parity input and the second parity input; a second transistor connected between the second parity input and the first parity output; a third transistor connected between the second parity input and the second parity output; a fourth transistor connected between the first parity input and the first parity output; where each of the first, second, third, and fourth transistors comprise a gate connected to a memory cell of the memory cell array; and where each of the first, second, third, and fourth transistors comprise the same conductance type; and where the number N of parity checking circuits in the plurality of parity checking circuits equals the number M of bits in the original payload data word.