Patent ID: 8853766

Claim:
A nonvolatile semiconductor memory device comprising: a substrate; a semiconductor region formed in an upper portion of the substrate; a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a plurality of through holes extending in the stacking direction and formed in a matrix configuration as viewed along the stacking direction; conductor pillars buried inside a subset of the plurality of through holes, piercing at least one of the dielectric films and at least one of the electrode films, the through holes in the subset being arranged in a first direction; semiconductor pillars buried inside the remaining through holes, piercing the dielectric films and the electrode films, and connected to the semiconductor region; a shunt interconnect provided above the plurality of dielectric films and electrode films and connected to the conductor pillars; a bit interconnect provided above the plurality of dielectric films and electrode films and connected to the semiconductor pillars; a charge storage layer provided at least between one of the semiconductor pillars and some of the electrode films, the conductor pillars having a lower resistivity than the semiconductor pillars, and the conductor pillars being connected to one of the electrode films, and not connected to the other electrode films and the semiconductor region.