Patent ID: 7058945

Claim:
A computer-implemented parallel processing method for causing a computing device having a plurality of processors to carry out predetermined information processing, the method comprising: dividing a program to be executed into a plurality of parallel processing blocks; dividing said parallel processing blocks into threads which are basic units to be assigned respectively to said plurality of processors for being processed thereby; providing a parallel processing control information region indicating a first parallel processing block number; providing, for each of the plurality of threads, a thread information region indicating a second parallel processing block number; providing a parallel processing block control information region containing an executed thread number; causing each processor to increment the second parallel processing block number of the thread information region corresponding thereto when said each processor has finished a currently parallel processing block and, when the incremented second parallel processing block number exceeds the first parallel processing block number, causing each processor to update the first parallel processing block number accordingly and creating a new parallel processing block control information region corresponding to the updated first parallel processing block number; and causing each processor to increment the executed thread number in the corresponding parallel processing block control information region when said each processor has finished a current parallel processing block thereof, and causing said each processor to delete the parallel processing block control information region when the incremented executed thread number equals a total number of threads.