Patent ID: 8411014

Claim:
A signal processing circuit configured to process a picture signal to output to a display unit made up of a collective entity of pixels, comprising: more than two digital signal processing means which operate in parallel each including selecting means configured to select one of a plurality of systems of picture signals which are input based on a mirror reversed setting, a master/slave setting associated with the plurality of digital signal processing means, and a display position setting, and output the selected picture signals to double-speed converting means, the display position setting indicating a number of dots shifted from a default position, wherein the mirror reversed setting, master/slave setting and display position setting are stored in a register located in each of the digital signal processing means, and wherein the display position setting includes a default setting, a default +1 setting in which each of the data is shifted and written onto a subsequent dot in relation to the default setting, and a default +2 setting in which the data is shifted and written onto a subsequent dot in relation to the default +1 setting, the double-speed converting means configured to write the data equivalent to one field of the picture signal selected by said selecting means in field memory, and simultaneously read said data equivalent to one field from said field memory twice at double speed, thereby converting the frequency of said picture signal into double speed, wherein the double-speed converting means further implements a serial-to-parallel conversion of the read data; reading means configured to read out the picture signal converted into double speed by said double-speed converting means, and temporarily stored in line memory, and correction processing means configured to subject the picture signal read out by said reading means to predetermined correction processing; and switch means configured to output one data of two data that are subjected to the correction processing means to an external driver, wherein each digital signal processing means receives both odd data and even data of a picture; and control means configured to perform a selection control of said plurality of systems of picture signals using said selecting means, and to perform a read position control of a picture signal from said line memory using said reading means.