Patent ID: 8329507

Claim:
A method of forming a semiconductor package, the method comprising: providing a substrate comprising an upper surface and a lower surface opposite the upper surface; forming a first through-hole within the substrate, the first through-hole extending from the upper surface to the lower surface; forming a first conductive pattern on the upper surface of the substrate, wherein the first conductive pattern extends over the first through-hole; providing at least a portion of a first semiconductor chip within the first through-hole; inserting an insulating material having a pre-formed shape in the first through-hole between the first semiconductor chip and the conductive pattern; connecting the first conductive pattern to the first semiconductor chip through the insulating material; and electrically connecting the first conductive pattern to the first semiconductor chip with a first external contact terminal located within the first through-hole, wherein inserting the insulating material comprises: providing an insulator frame body, wherein the insulator frame body comprises at least a first insulator frame body through-hole defined therethrough; and disposing the insulator frame body within the first through-hole to be adjacent to the first conductive pattern, wherein electrically connecting the first conductive pattern to the first semiconductor chip comprises inserting the first external contact terminal through the first insulator frame body through hole.