Patent ID: 8759899

Claim:
An integrated circuit device, comprising: a substrate including a first region and a second region; a pit formed in the first region, the pit having a depth; a stack of active layers alternating with insulating layers deposited in the pit, wherein the stack includes: a particular insulating layer having a first thickness, wherein a sum of the first thickness of the particular insulating layer, thicknesses of active layers, and thicknesses of other insulating layers in the stack is essentially equal to the depth, the first thickness being different than the thicknesses of the other insulating layers in the stack by an amount within a range of process variations for the depth of the pit, for the thicknesses of active layers, and for the thicknesses of other insulating layers; and a planarized surface over the first region and the second region, wherein an uppermost one of the active layers has a top surface below the planarized surface; the integrated circuit device further comprising: an isolation region in the pit separating the stack from the second region including a peripheral region; and a stopping layer between the stack and the isolation region and between the isolation region and the peripheral region.