Patent ID: 7194049

Claim:
A digital automatic level control (DALC) system comprising: a level detector module including: a first digital delay element having an input for receiving a sequence of inputted digital time samples of a signal to be leveled and an output for sequentially outputting a first sequence of outputted time samples after a pre-selected delay; a first accumulator for receiving said sequence of inputted time samples and adding each of said inputted samples to a first running sum, and for receiving said sequence of outputted time samples on said output of said delay element and subtracting each of said outputted time samples from said first running sum, whereby said first running sum is representative of the average value of all time samples presently contained in said first delay element; a second digital delay element having an input for receiving said sequence of outputted digital time samples from said output of said first digital delay element and an output for sequentially outputting a second sequence of outputted time samples after a predetermined delay; and a second accumulator for receiving said first sequence of outputted time samples and adding each of said first sequence of outputted time samples to a second running sum, and for receiving said second sequence of outputted time samples on said output of said second delay element and subtracting each of said outputted time samples in said second sequence from said second running sum, whereby said second running sum is representative of the average value of all time samples presently contained in said second delay element; and a level adjustment module for employing the greater of said first and second running sums to form a level adjusted output sequence of digital time samples.