Patent ID: 8909687

Claim:
An apparatus comprising: a processor to calculate a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence, the processor comprising: multipliers, each multiplying two numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real, in which when each of the first sequence of numbers is a complex number and each of the second sequence of numbers is a real number, the control circuitry controls the multiplexers to direct the first and second input sequences of numbers to the multipliers to enable a first multiplication and a second multiplication to be performed in parallel, the first multiplication comprising a first complex number in the first input sequence multiplied by a real number in the second input sequence, and the second multiplication comprising a second complex number in the first input sequence multiplied by the real number in the second input sequence; and an accumulator to add partial products from the multiplications to calculate the convolution.