Patent ID: 8669179

Claim:
A method of forming a microelectronic assembly, the method comprising: exposing at least a portion of a first surface of a bond-site covered by a passivation layer, wherein the bond-site has a second surface opposite the first surface that faces a front side of a substrate; disposing a first conductive layer on at least a portion of the first surface of the bond-site; exposing at least a portion of the front side of the substrate through the bond-site; forming a via in the substrate extending to an intermediate depth from the front side of the substrate; disposing a dielectric on a sidewall of the via and on the first conductive layer; removing the dielectric from an uppermost surface of the assembly; applying a second conductive material on the dielectric; filling the via with a third conductive material; and exposing the third conductive material from a back side of the substrate.