Patent ID: 8421227

Claim:
A semiconductor chip comprising: a semiconductor substrate; a copper interconnect over said semiconductor substrate; a first metal layer at a bottom of said copper interconnect and at a sidewall of said copper interconnect; an insulating layer over said semiconductor substrate and on a top surface of said copper interconnect, wherein a first opening in said insulating layer is over a first contact point of said copper interconnect, wherein said insulating layer comprises a nitride; a second metal layer on said first contact point and on a top surface of said insulating layer; a third metal layer on said second metal layer, wherein said third metal layer is connected to said first contact point through said first opening; a passivation layer on a top surface of said third metal layer and on said insulating layer, wherein a second opening in said passivation layer is over a second contact point of an aluminum-containing layer of said third metal layer, wherein said passivation layer comprises a nitride; a fourth metal layer on said second contact point and on a top surface of said passivation layer; a gold seed layer on said fourth metal layer; and an electroplated gold layer on said gold seed layer, wherein said electroplated gold layer is configured for connecting with an external circuit in a chip-on-film (COF) package, wherein said electroplated gold layer has a thickness between 5 and 25 micrometers.