Patent ID: 7200769

Claim:
An integrated circuit comprising: a series of circuits; a phase detector having a first input coupled to an input of the series of circuits and a second input coupled to an output of the series of circuits; an up/down counter having an input coupled to an output of the phase detector; a first variable-delay block having a control input coupled to an output of the up/down counter; an input buffer; a first register having an input coupled to an output of the input buffer and a clock input coupled to an output of the first variable-delay block; a second register having an input coupled to the output of the input buffer and a complementary clock input coupled to the output of the first variable-delay block; and a third register coupled between the phase detector and the up/down counter, wherein the series of circuits comprises: a second variable-delay block having a control input coupled to the output of the up/down counter; and a frequency divider.