Patent ID: 7667219

Claim:
A phase-change memory device comprising: a semiconductor substrate formed with a lower pattern; a first insulating layer covering the lower pattern; a first electrode formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first electrode, and formed with a first contact hole for exposing a predetermined portion of the first electrode; a first phase-change layer including both a plug portion formed in the first contact hole and a layer portion formed on a predetermined portion of the second insulating layer adjacent to the first contact hole, such that the first phase-change layer including both the plug portion and the layer portion has a shape of a ‘T’; a third insulating layer formed on the second insulating layer so as to cover the layer portion of the first phase-change layer, and formed with a second contact hole for exposing a portion of the layer portion of the first phase-change layer formed over the first contact hole; a second phase-change layer having a plug shape formed in the second contact hole so as to directly contact the exposed portion of the layer portion of the first phase-change layer formed over the first contact hole; and a second electrode formed on the second phase-change layer having the plug shape and on a predetermined portion of the third insulating layer adjacent to the second phase-change layer, wherein a width of the second contact hole having the second phase-change layer formed therein is greater than a width of the first contact hole having the plug portion of the first phase-change layer formed therein, so that a phase-change is generated in the first phase-change layer at an interfacial portion between the plug portion of the first phase-change layer formed in the first contact hole and the layer portion of the first phase-change layer formed over the first contact hole.