Patent ID: 7487334

Claim:
A method, in a data processing system, for determining a target of a branch instruction, comprising: receiving a branch instruction from a Level 2 cache; performing combinatorial decoding on the branch instruction; directing the branch instruction on which the combinatorial decoding has been performed to a pre-decode logic unit; determining, using combinatorial logic of the pre-decode logic unit, a class of the branch instruction from a plurality of classes of branch instructions, wherein the plurality of classes of branch instructions include branch instructions that get their target from an architected register, relative branch instructions and absolute branch instructions; in response to determining that the class of the branch instruction is a relative branch instruction, performing pre-calculations by the pre-decode logic unit to create a pre-decoded branch, wherein the pre-calculations comprise re-encoding pre-calculations for re-encoding a relative address of the relative branch instruction into an absolute address, branch prediction decode pre-calculations and parity pre-calculations, and wherein the re-encoding the relative address into the absolute address includes calculating an effective address of the target; marking the pre-decoded branch with a pre-decode bit to indicate that the pre-decoded branch is a branch unit instruction; and writing the pre-decoded branch with the pre-decode bit into a Level 1 cache.