Patent ID: 7120215

Claim:
A circuit for jitter measurement, comprising: a plurality of delay elements arranged in a series-connected chain having a total delay equal to a sum of each delay of the delay elements, each delay element having an input and output, wherein the input of the first element in the chain receives an input clock signal, the chain propagating the input clock signal through each of its delay elements, and each delay element output producing a delayed version of the propagated input clock signal on its input; a first set of circuitry operative to produce at an output a pulse corresponding to each delay element in response to the propagation of a significant instant of the input clock signal through the delay element, each pulse having a width that is approximately equal to the delay of the corresponding delay element; a second set of circuitry having one storage element corresponding to each output of the first set of circuitry, and an input that receives a trigger signal that is timed to correspond to a delay that is approximately half of the total delay of the chain, and the second set of circuitry being operative to record in the corresponding storage elements one or more pulses that may be active at the time of occurrence of the trigger signal; and a single one detector operative to select one from the recorded pulses in the storage elements at the time of occurrence of the trigger signal, wherein a jitter measurement is made based on the selected pulses after a plurality of trigger signals has occurred.