Patent ID: 8080454

Claim:
A method of forming a CMOS transistor, wherein the CMOS transistor is formed on a substrate, and the substrate comprising a first transistor region comprising a first gate and a first source/drain region, a second transistor region comprising a second gate and a second source/drain region, and an insulator positioned between the first transistor region and the second transistor region, wherein the first transistor region is used for forming a first-type conductivity transistor and the second transistor region is used for forming a second-type conductivity transistor, the method comprising: performing a first amorphizing process in the first source/drain region; forming a first stressor covering the first gate and the first source/drain region; performing a first annealing process to form a first strained silicon channel in the substrate under the first gate; removing the first stressor; performing a second amorphizing process in the second source/drain region; forming a second stressor covering the second gate and the second source/drain region; performing a second annealing process to form a second strained silicon channel in the substrate under the second gate; and removing the second stressor to form the CMOS transistor.