Patent ID: 7707237

Claim:
A macrocell, comprising: an adder block comprising a plurality of bit-slice adders corresponding to a sequence of consecutive significance bit positions of input values; a bypass path; and a control unit adapted to receive a carry of a first neighboring macrocell associated with lower-significance bit positions in dual-rail coded form on two carry input lines, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path, to a second neighboring macrocell associated with higher-significance bit positions in dual-rail coded form on two carry output lines, wherein the control unit is adapted to determine from data depending on the input values of the adder block whether the carry of the first neighboring macrocell may enable the bypass path to the second neighboring macrocell; wherein the control unit is adapted to signal a validity of the carry output of the macrocell after a generation thereof within the macrocell or a passage thereof through the macrocell to the second neighboring macrocell depending on a logical combination of states of the two carry output lines; and wherein the control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry of the first neighboring macrocell, to prevent forwarding the carry of the first neighboring macrocell to the bypass path and the adder block, respectively.