Patent ID: 8335108

Claim:
A nonvolatile memory structure comprising: a plurality of nonvolatile memory cells connected in a NAND series string; and a pair of serially connected threshold voltage adjustable top select transistors comprising, a first threshold voltage adjustable top select transistor comprising a first source/drain connected to a first bit line associated with the NAND series string within an array of the nonvolatile memory structures, and a second threshold voltage adjustable top select transistor comprising a first source/drain connected to a second source/drain of the first threshold adjustable top select transistor and a second source/drain connected to a first nonvolatile memory cell of the plurality of nonvolatile memory cells, wherein the first threshold voltage adjustable top select transistor has its threshold voltage modified to a first threshold voltage level and the second threshold voltage adjustable top select transistor has its threshold voltage modified to a second threshold voltage level or the first threshold voltage adjustable top select transistor has its threshold voltage modified to the second threshold voltage level and the second threshold voltage adjustable top select transistor has its threshold voltage modified to the first threshold voltage level, wherein the second threshold voltage level has a greater absolute magnitude than the first threshold voltage level, wherein a first gate select voltage has a voltage level between the first threshold voltage level and the second threshold voltage level such that when the first select gate voltage level is applied to a gate of the first or second threshold voltage adjustable top select transistor, the first or second threshold voltage adjustable top select transistor with the first threshold voltage level is activated and the first or second threshold voltage adjustable top select transistor with the second threshold voltage level is not activated.