Patent ID: 7241696

Claim:
A method for depositing a metal layer on an interconnect structure for a semiconductor wafer, the method comprising the steps of: (a) providing an interconnect structure comprising a metal conductor covered by a capping layer and a dielectric layer; (b) patterning the dielectric layer to form an opening that exposes the capping layer over the metal conductor; (c) depositing a liner layer on a wall and bottom of the opening; (d) sputter-etching the liner layer and capping layer to expose the metal conductor and at least partially redepositing the liner layer and capping layer on a sidewall of the opening; (e) depositing at least one layer on the wall and bottom of the opening and covering the redeposited liner layer and capping layer, wherein the at least one layer is selected from the group consisting of TaN, Ta, Ti, Ti(Si)N and W; (f) depositing a copper seed layer on the at least one layer; and (g) filling the opening with copper.