Patent ID: 7945803

Claim:
An integrated system comprising: a master clock signal; in a first clock domain: a first divided clock signal generated from the master clock signal, the first divided clock signal having rising clock edges, and a first clock suppression circuit structured to generate a first suppressed clock signal from the first divided clock signal, each of the rising clock edges of the first suppressed clock signal aligned with one of the rising edges of the first divided clock signal; in a second clock domain: a second divided clock signal generated from the master clock signal, the second divided clock signal having rising clock edges, and a second clock suppression circuit structured to generate a second suppressed clock signal independent of information about the first clock suppression circuit, each of the rising clock edges of the second suppressed clock signal aligned with one of the rising edges of the second divided clock signal; and a clock crossing domain between the first clock domain and the second clock domain, the clock crossing domain accepting a clock crossing signal that is as fast or faster than the fastest of the first divided clock signal and the second divided clock signal, and the clock crossing domain requiring no buffering of data.