Patent ID: 8111565

Claim:
A memory interface comprising: a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data to a memory through said first delaying circuit; a data read circuit configured to read said write data written in said memory, as said read data through said second delaying circuit; an edge detecting circuit configured to detect edges of said read data; and a control circuit configured to detect positions of a start edge and an end edge of an eye opening which is formed based on fluctuation of said write data or said read data, to specify an intermediate position of the start edge and the end edge, and to determine a phase of a data strobe signal based on a difference between the intermediate position and one of the start edge and the end edge, wherein said data write circuit writes first test data in which at least two bits with a same sign succeed, in said memory in a normal mode, said data read circuit reads the written first test data from said memory, said edge detecting circuit detects a transition timing at which the level of the read first test data transits and notifies the transition timing to said control circuit, and said control circuit specifies a timing of the start edge of said eye opening based on the transition timing, wherein said data write circuit writes a second test data which contains only a single 1-bit lone pulse, in said memory in the normal mode, said data read circuit reads the written second test data from said memory, and said control circuit detects whether or not the read second test data is coincident with an expectation of read data which is formed based on the position of the start edge of said eye opening, and detects the position of an end edge based on said expectation.