Patent ID: 8621406

Claim:
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, the method performed by a layout generating machine having a processor component executing instructions prior to manufacturing, said method comprising: receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas; generating a plurality of FinFET active areas, wherein each FinFET active area corresponds to one planar active area of the plurality of planar active areas; defining a plurality of FinFET cells, wherein each FinFET cell includes one or more of the FinFET active areas; determining whether each of the plurality of FinFET cells is symmetrical; and for each symmetrical FinFET cells, generating mandrels in the FinFET cell to create an internally symmetrical FinFET active area or more than one symmetrical FinFET active areas each of the more than one symmetrical FinFET active areas having a same number and location of mandrels.