Patent ID: 7538385

Claim:
A memory device comprising: a plurality of selection lines on a semiconductor substrate; a plurality of word lines on the semiconductor substrate and coupled to the plurality of selection lines; a cell gate insulating layer between the semiconductor substrate and the word lines, the cell gate insulating layer comprising a plurality of layers including a charge storage layer; and a selection gate insulating layer between the semiconductor substrate and the selection lines, the selection gate insulating layer thinner than the cell gate insulating layer, wherein the selection gate insulating layer comprises at least one layer and not all layers of the cell gate insulating layer, the cell gate insulating layer comprises a tunnel insulating layer and a blocking insulating layer sandwiching the charge storage layer therebetween, the selection gate insulating layer comprises a single layer of the blocking insulating layer or a double layer of the tunnel insulating layer and the blocking insulating layer, the selection gate insulating layer comprises a single layer of the blocking insulating layer or a double layer of the tunnel insulating layer and the blocking insulating layer, and the blocking insulating layer comprises a metal oxide.