Patent ID: 7417460

Claim:
A multi-standard transmitter, comprising: a differential stage configured to be connected to a first voltage reference and to a second voltage reference, the differential stage including: a first input terminal and a second input terminal; a first output terminal and a second output terminal; a current generator transistor; a first transistor and a second transistor connected between a first inner circuit node and said current generator transistor and having respective control terminals connected together and to said first input terminal, said first and second transistors being interconnected at said first output terminal; a third transistor and a fourth transistor connected between said first inner circuit node and said current generator transistor and having respective control terminals connected together and to said second input terminal, said third and fourth transistors being interconnected at said second output terminal; and a first resistive end element and a second resistive end element connected between said first and second output terminals and interconnected at a second inner circuit node; and a selective enabling circuit connected to said first and second inner circuit nodes, as well as to a third inner circuit node corresponding to a control terminal of said current generator transistor, said selective enabling circuit being configured to supply said inner circuit nodes with regulation signals to modify an operating mode of said multi-standard transmitter, wherein said selective enabling circuit comprises: a first enabling transistor configured to be connected between said first voltage reference and said second inner circuit node and having a control terminal configured to receive a first enabling signal; a differential amplifier, having a first input terminal connected to said second inner circuit node, a second input terminal being configured to receive a reference voltage, a control terminal configured to receive a second enabling signal and an output terminal connected to said third inner circuit node; and a second enabling transistor, having a first conducting terminal connected to said third inner circuit node and a control terminal configured to receive a third enabling signal.