Patent ID: 6996794

Claim:
A semiconductor device including a logic cell and auxiliary cells and having a device layout determined by a method for laying out the auxiliary cells in a vacant area that is not occupied by the logic cell in the semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the semiconductor device being produced by a method comprising: determining a device layout comprising temporarily arranging each representative auxiliary cell in the vacant area, calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells, selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device, and arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells; and producing the semiconductor device using the determined device layout, wherein all of the arranged representative auxiliary cells are replaced with the auxiliary cells and no representative auxiliary cells remain in the semiconductor device.