Patent ID: 7592847

Claim:
A phase-locked loop device, comprising: a phase frequency detector, the phase frequency detector comprising: a first D flip-flop receiving a reference signal to output an up signal; a second D flip-flop receiving a clock signal to output a down signal; a first delay unit with a first delay; and a second delay unit with a second delay; a charge pump circuit receiving and transforming the up signal and the down signal into a current; a loop filter receiving and transforming the current into a voltage; and a voltage-controlled oscillator receiving the voltage and outputting the clock signal, wherein when the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on a first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on a second delay.