Patent ID: 8296608

Claim:
A memory device comprising: a first module configured to calculate a failure occurrence risk index of each data storage area address; a second module configured to calculate a power saving index of each data storage area address; a third module configured to calculate an access speed index per unit data volume necessary to access each data storage area address; a fourth module configured to generate a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed; and a fifth module configured to select a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distribute the data to the candidate address, wherein the failure occurrence risk index is calculated by using: a table representing a failure occurrence probability of a failure portion address; a first model that associates the failure occurrence probability of each data storage area address with the failure portion address; and a second model that associates a degree of influence on a user with the failure occurrence probability of each data storage area address.