Patent ID: 7463548

Claim:
The DRR DRAM having a low frequency and a high frequency operating mode, comprising: a multiplicity of storage cells arranged in an array, each storage cell accessible by a wordline and a bitline; wherein peripheral logic circuits of said DDR DRAM are adapted to execute a write burst enable and a column address command one clock cycle earlier in low frequency operating mode than in high frequency operating mode, adapted to execute an auto-precharge enable one-half clock cycle earlier in low frequency operating mode than in high frequency operating mode, and having a column address latency of one clock cycle in test mode and two or three clock cycles in operational mode; wherein said DDR DRAM is adapted to initiate, in a timed auto-precharge mode of low frequency operational mode, a precharge immediately after a falling edge of a clock cycle; and wherein said DDR DRAM is adapted to, in a non-timed auto-precharge mode of said test mode, to start an auto-precharge asynchronously after the falling edge of a clock cycle and after a timer allows enough time for a write-back to said DDR DRAM.