Patent ID: 7180784

Claim:
A page buffer, comprising: a bit line selection unit to selectively connect an even bit line or an odd bit line, which is connected to a memory cell array and to a sensing node according to a bit line selection signal; a first switch to precharge the even bit line or the odd bit line by supplying a predetermined voltage to the sensing node according to a precharge signal; a main register to store state data of the selected cell according to a voltage level of the sensing node and a main latch signal; a second switch to output an erase-verify signal according to a voltage level of a first terminal of the main register; a third switch to output a program-verify signal according to a voltage level of a second terminal of the main register; a cache register to store program data according to a control signal in a program operation; a fourth switch to transfer data stored in the cache register to the main register; and a fifth switch to program the program data stored in the main register into the selected memory cell according to a program signal.