Patent ID: 7088142

Claim:
A semiconductor integrated circuit, comprising: a level conversion circuit having a pair of transistors including a first MOS transistor and a second MOS transistor, connected in series between a first power supply and a second power supply, and a further pair of transistors including a third MOS transistor and a fourth MOS transistor, connected in series between the first power supply and the second power supply, the level conversion circuit generating a first output signal from a node connecting the first and second MOS transistors and a second output signal from a node connecting the third and fourth transistors; and a differential amplification circuit, connected to the level conversion circuit, for functioning in accordance with the first and second output signals of the level conversion circuit and generating a differential amplification output siginal, wherein the first and fourth MOS transistors each have a gate for receiving a first input signal, and the second and third MOS transistors each have a gate for receiving a second input signal having a phase inverted from the phase of the first input signal, and wherein the gate of each transistor has a gate length and a gate width, the ratio between the gate length and the gate width of one of the transistors in each pair of the series-connected MOS transistors is about three times or less than the ratio between the gate length and the gate width of the other one of the transistors in the pair of the series-connected MOS transistors such that fluctuation of a voltage level of the differential amplification output signal is suppressed and fluctuation of delay time of the differential amplification output signal is in a predetermined time period regardless of a change in voltage levels of the first and second input signals.