Patent ID: 7867840

Claim:
A method of fabricating a semiconductor device including a first MIS transistor of a first conductive type and a second MIS transistor of the first conductive type whose impurity concentration profiles in channel regions being different from each other, the method comprising the steps of: (a) implanting ions of a first impurity into a semiconductor substrate in a first MIS transistor formation section to form a first channel region of a second conductive type which has an impurity concentration peak in an interior apart from a surface of the semiconductor substrate in the first MIS transistor formation section; (b) implanting ions of a second impurity into the semiconductor substrate in a second MIS transistor formation section to form a second channel region of the second conductive type which has the impurity concentration peak at a position close to a surface of the semiconductor substrate in the second MIS transistor formation section; (c) forming a first gate electrode over the semiconductor substrate in the first MIS transistor formation section through a first gate insulation film, and forming a second gate electrode over the semiconductor substrate in the second MIS transistor formation section through a second gate insulation film; (d) implanting ions of a third impurity using the first gate electrode and the second gate electrode as a mask to form a first extension region of the first conductive type and a second extension region of the first conductive type in the first MIS transistor formation section and in the second MIS transistor formation section; and (e) after step (d), thermally treating the semiconductor substrate to eliminate defects produced in the first extension region and the second extension region due to implanting the ions of the third impurity.