Patent ID: 7827323

Claim:
A host device, comprising: a peripheral control module that includes a first memory register that receives first data from a first memory; and a direct memory access (DMA) module that communicates with the first memory; a host control module that receives second data from the first memory; a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array, and wherein the DMA control module compares contents of the first memory array to contents of the first memory register, controls transfers of the first data from the first memory to the peripheral control module based on the comparison made by the DMA control module, and processes a secure digital input/output header to run an interrupt header sequence without interrupting the host control module until the interrupt header sequence is complete; and an interrupt control module that communicates with the DMA control module, and that selectively passes interrupts to the host control module when the contents of the first memory do not match contents of the first register.