Patent ID: 8169948

Claim:
A code synchronization circuit, comprising: reception means for receiving an external carrier signal; variable oscillation means for generating a clock signal with a variable frequency for generation of component code signals other than a minimum cycle component code signal having a minimum cycle, all the component code signals, including the minimum cycle component code signal, being used to generate a multi-component code signal and having cycles which, given as integral multiples of one bit length, are relatively prime; a plurality of component code signal generation means for generating the component code signals other than the minimum cycle component code signal when the clock signal is input; first correlation value output means for outputting a first correlation value indicating similarity between the carrier signal and each of the component code signals; code phase control means for controlling, according to the first correlation value, phases of the component code signals, other than the minimum cycle component code signal, which are out of sync with the carrier signal so that each of the component code signals, other than the minimum cycle component code signal, which are out of sync with the carrier signal is in sync with the carrier signal; code synchronization determining means for deter lining whether each of the component code signals is in sync with the carrier signal based on the first correlation value; frequency dividing means for dividing the clock signal by 2 to generate the minimum cycle component code signal; delay means for outputting a delayed minimum cycle component code signal lagging in phase behind the minimum cycle component code signal by half a bit; and second correlation value output means for outputting a second correlation value indicating similarity between the delayed minimum cycle component code signal and the carrier signal, wherein the variable oscillation means controls the frequency of the clock signal according to the second correlation value so that the carrier signal and the clock signal are in sync.