Patent ID: 7085917

Claim:
A method for use in a superscalar processor in which instructions of the same or different types are dispatched and executed in parallel in multiple execution units, comprising the steps of: decoding complex multifunctional or multi-cycle execution instructions in a decode unit that decodes said complex multifunction and multi-cycle execution instructions and loads them into an instruction queue buffer, and examining the loaded complex multifunctional or multi-cycle instructions in said instruction queue buffer and grouping them for execution, and dispatching said grouped complex multifunction and multi-cycle instructions to a fixed point execution unit (FXU) for execution of the dispatched instructions in parallel in multiple execution pipelines of said superscalar processor, and wherein the step of decoding of the complex multifunctional or multi-cycle instructions is performed and the instructions are loaded without cracking into a single instruction queue buffer, and wherein the steps of decoding includes marking each complex multifunctional or multi-cycle instruction with two bits identifying the manner by which it should be dispatched and executed, and wherein the steps of grouping and dispatching the instructions includes looking at instructions in the single instruction buffer queue and upon encountering a multifunctional or multi-cycle execution instruction dispatches said multifunctional or multi-cycle execution instruction alone to a single port of the FXU but duplicates the instruction's text including its opcode to other ports, and wherein the identifying bits allow the execution of the multifunctional or multi-cycle execution instruction to be distributed across the multiple execution pipelines.