Patent ID: 7685483

Claim:
An integrated circuit comprising: a wordline driver having an address input terminal, an enable input terminal, and a driver output terminal, the wordline driver configured to drive wordlines in a memory; an address decoder coupled to the address input terminal of the wordline driver; a multiplexer having an output terminal, input terminals, and a select terminal, the output terminal of the multiplexer coupled to the enable input terminal of the wordline driver; an enable signal source coupled to a first input terminal of the multiplexer for asserting a wordline enable signal, the wordline enable signal possibly causing a failure of the integrated circuit if asserted before new address signals from the address decoder to the wordline driver have settled; a test signal source coupled to a second input terminal of the multiplexer for asserting a wordline enable test signal, the timing of the wordline enable test signal controllable to test whether a failure of the integrated circuit is due to the wordline enable signal being asserted before new address signals from the address decoder to the wordline driver have settled; and a control signal source coupled to the select terminal of the multiplexer, wherein the multiplexer is responsive to the control signal source in coupling either the enable signal source or the test signal source to the enable input terminal of the wordline driver.