Patent ID: 6891225

Claim:
A semiconductor memory device comprising: a source diffusion layer of said semiconductor memory device formed on a semiconductor substrate and connected to a fixed potential line, said source diffusion layer being formed as a sheet-form layer covering the surface of the substrate; a plurality of columnar semiconductor layers arranged in a matrix form and formed on said source diffusion layer and each having one end connected to said source diffusion layer commonly, said columnar semiconductor layer being arranged to accumulate, to take a first data state with a first threshold voltage, excessive majority carriers in said columnar semiconductor layer, and being arranged to discharge, to take a second data state with a second threshold voltage, excessive majority carriers from said columnar semiconductor layer, said columnar semiconductor layers being electrically insulated from the semiconductor substrate so as to be in an electrical floating state; a plurality of drain diffusion layers of said semiconductor memory device, each of said plurality of said drain diffusion layers formed at the other end of said columnar semiconductor layer; a plurality of gate electrodes of said semiconductor memory device, each of said plurality of gate electrodes opposed to said columnar semiconductor layer via a gate insulating film; a plurality of word lines of said semiconductor memory device, each of said plurality of word lines connected to corresponding said gate electrodes; and a plurality of bit lines of said semiconductor memory device, each of said plurality of bit lines connected to corresponding said drain diffusion layers, said bit lines being perpendicular to said word lines.