Patent ID: 8055847

Claim:
A data processing system comprising: a processor; a cache group having multiple cache elements, including: at least one lower level cache; a region coherence array; a region cache for storing state information obtained from the region coherence array in one or more entries, wherein the one or more entries correspond to regions recently used by the processor; and wherein the at least one lower level cache, the region cache, and the region coherence array are interconnected to each other and to the processor in accordance with one of multiple access configurations, wherein an access configuration of the multiple access configurations is pre-selected based on request latency and power consumption considerations for resolving a data request within the cache group, and wherein the multiple access configurations are ordered by increasing power consumption and reduced latency; and logic executing on the processor that, in response to the data request, initiates an access to one or more of the multiple cache elements within the cache group in an order corresponding to a pre-selected access permission of the one or more of the multiple cache elements.