Patent ID: 8828819

Claim:
A method, comprising: forming a gate layer stack above a first semiconductor region and a second semiconductor region; patterning said gate layer stack to form a first gate electrode structure above said first semiconductor region and a second gate electrode structure above said second semiconductor region, an upper portion of said first gate electrode structure having a first target gate length, a lower portion of said first gate electrode structure adjacent to said first semiconductor region having a first effective gate length that is less than said first target gate length, and a lower portion of said second gate electrode structure having a second effective gate length adjacent to said second semiconductor region that is greater than said first effective gate length; forming a spacer layer above said first and second gate electrode structures, said spacer layer having a thickness of approximately 10 nm or less; forming a spacer element on sidewalls of said first gate electrode structure from said spacer layer; and forming a strain-inducing semiconductor alloy in said first semiconductor region by using said spacer element as a mask.