Patent ID: 7453725

Claim:
A high-voltage latch system for a non-volatile memory, comprising: a HV terminal that is coupled to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a HIGH-VOLTAGE supply voltage during a high-voltage write mode of operation; a cross-coupled high-voltage CMOS latch that is coupled between the HV terminal and a ground terminal and that has a latch input node B and a latch output node A; an input buffer that is coupled between the HV terminal and the ground terminal, that has an input terminal coupled to a DATA INPUT terminal that is adapted to be coupled to a bit line of the non-volatile memory, that has an output terminal coupled to the latch input node B, and that has data loading means for enabling the input buffer to load data from the DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch during a load-data mode of operation; wherein the input buffer isolates the DATA INPUT terminal from the high-voltage CMOS latch.