Patent ID: 8019958

Claim:
A method of controlling a memory device, the method comprising: over a first set of interconnect resources: conveying a first command that specifies activation of a row of memory cells; conveying a second command that specifies a write operation, wherein write data associated with the write operation is written to the row of memory cells; conveying a bit that specifies whether precharging occurs after the write data is written; conveying a code that specifies whether data mask information will be issued in connection with the write operation; and if the code specifies that the data mask information will be issued, then conveying the data mask information after conveying the code, wherein the data mask information specifies whether to selectively write portions of the write data; and over a second set of interconnect resources that is separate from the first set of interconnect resources, conveying the write data to be written in connection with the write operation.