Patent ID: 7099179

Claim:
A re-writable memory, comprising: a substrate; a two-terminal cross point memory array formed above the substrate and including: a first conductive array line; second conductive array lines, each of the second conductive array lines oriented generally substantially perpendicular to the first conductive array line; two-terminal memory plugs, each memory plug having a first terminal in electrical communication with the first conductive array line and a second terminal in electrical communication with one of the second conductive array lines, and each memory plug configured to assume a first electrical resistance that corresponds to a first data state in response to a first voltage and a second electrical resistance that corresponds to a second data state in response to a second voltage; driver circuits, each driver circuit in electrical communication with the cross point array and operable to deliver the first voltage during a first cycle to a first group of memory plugs, and the second voltage during a second cycle following the first cycle, the second voltage delivered to a second group of memory plugs, the second group of memory plugs not including any memory plugs from the first group of memory plugs; and address circuits in electrical communication with the driver circuits and configured to receive binary information and an address signal, the address circuits further configured to distribute the binary information to decoder circuits according to the address signal, so as to facilitate writing of the received binary information to the two-terminal memory plugs in page mode.