Patent ID: 8237477

Claim:
A programmable clock generator suitable to be used in dynamic-voltage-and-frequency-scaling (DVFS) operated in Sub- and Near-Threshold region, comprising: a first pulse generating unit means for receiving an input signal having an input frequency in order to generate a first pulse signal with a first phase and a first frequency; and a pulse multiplier means for connecting the first pulse generating unit, the pulse multiplier comprising: a phase detector connecting the first pulse generating unit and receiving the first pulse signal in order to generate a phase difference signal; a control unit connecting the phase detector in order to generate a first control signal and a selection signal; a multiplexer connecting the control unit, the first pulse generating unit, and a second pulse generating unit in order to receive the selection signal, the first pulse signal, and a second pulse signal, wherein the control unit controlling the multiplexer in accordance with the selection signal in order to transmit the first pulse signal or the second pulse signal; a lock-in delay unit connecting the control unit and the multiplexer, the lock-in delay unit being to delay the signals receiving by the multiplexer so that a first predetermined phase being generated between the first pulse signal and the second pulse signal; a compensation unit connecting the lock-in delay unit in order to compensate a second predetermined phase generated between the first pulse signal and the second pulse signal; the second pulse generating unit connecting the compensation unit and the phase detector in order to generate the second pulse signal having a second phase and a second frequency; and a first counting unit connecting the second pulse generating unit, the control unit and the phase detector, the first counting unit being calculate a first counting value, and transmitting a first counting signal to the phase detector and the control unit; wherein, when the first counting value calculated by the first counting unit being 8, the first counting unit generating the first counting signal to control the phase detector comparing a phase difference between the first pulse signal and the second pulse signal in order to transmit the phase difference signal to the control unit, the control unit transmitting the first control signal to the lock-in delay unit in accordance with the phase difference signal, and controlling the lock-in delay unit to adjust the phase of the second pulse signal, so that a predetermined phase being generated between the first pulse signal and the second pulse signal.