Patent ID: 6861907

Claim:
A power amplifier comprising: a first amplifier including a first transistor for signal amplification, a first two-terminal network for giving an open-circuit condition or a sufficiently large load to an even-numbered harmonic frequency of a signal frequency and giving a short-circuiting condition or a sufficiently small load to an odd-numbered harmonic frequency of the signal frequency, and which is provided at an output side of the first transistor, a first input matching circuit for impedance matching the signal frequency, and which is provided at an input side of the first transistor, and a first output matching circuit for impedance matching the signal frequency, and which is provided at the output side of the first transistor; a second amplifier including a second transistor for signal amplification, a second two-terminal network for giving the short-circuiting condition or the sufficiently small load to the even-numbered harmonic frequency of the signal frequency and giving the open-circuit condition or the sufficiently large load to the odd-numbered harmonic frequency of the signal frequency, and which is provided at an output side of the second transistor, a second input matching circuit for impedance matching the signal frequency, and which is provided at an input side of the second transistors and a second output matching circuit for impedance matching the signal frequency, and which is provided at the output side of the second transistor; a power distribution circuit for distributing an input signal to the first transistor and the second transistor such that a phase difference between signals supplied to the first transistor and the second transistor reaches about 90 degrees, and which is connected between an input of the first amplifier and an input of the second amplifier; a distributed line for controlling an output load of the first transistor through an impedance transformation based on an operating state of the second transistor, and which is connected between an output of the first amplifier and an output of the second amplifier; and a bias circuit for biasing the first transistor and the second transistor.