Patent ID: 7969446

Claim:
A method of performing a graphics processing operation on a graphics processor using programmable arithmetic logic units in place of a dedicated deep graphics pipeline stage, comprising: for a graphics function identifying a sequence of scalar arithmetic operations that may be performed on subsets of pixel attributes to implement said graphics function; rasterizing a primitive; for a pixel of the rasterized primitive, partitioning pixel attributes of the pixel into at least two pixel packets with each pixel packet having a subset of the total pixel attributes, the partitioning further including partitioning the pixel attributes into a plurality of different types of pixel packets with each of the different types of pixel packets having fields corresponding to a different subset of the attributes of the pixel and each pixel packet having at least one field for associated sideband information including a sequence of at least one instruction to be executed on said pixel packet to perform said sequence of scalar arithmetic operations for implementing said graphics function; an arithmetic logic unit (ALU) stage of said graphics processor having at least one ALU receiving said plurality of different types of pixel packets and reading operands from selected ones of said plurality of different types of pixel packets; in said at least one ALU, performing scalar arithmetic operations according to said sequence of at least one instruction and updating one or more pixel packets or a temporary result to perform said sequence of scalar arithmetic operations for implementing said graphics function.