Patent ID: 7750444

Claim:
A LOC semiconductor package primarily comprising: a plurality of leadframe's leads, each having a bonding finger; at least a tie bar having a dummy finger, wherein the dummy finger is disposed at one side of the disposition area of the bonding fingers, wherein the bonding fingers and the dummy finger are linearly arranged in parallel; a die-attaching layer connecting the bonding fingers and of the dummy finger; a chip having an active surface and a plurality of bonding pads disposed on the active surface, wherein the die-attaching layer is attached to the active surface so that the bonding fingers and the dummy finger are located above the active surface, and the dummy finger is adjacent to a first edge of the active surface; a plurality of bonding wires electrically connecting the bonding pads to the bonding fingers; and an encapsulant encapsulating parts of the leads including the bonding fingers, the tie bar, the die-attaching layer, the chip, and the bonding wires.