Patent ID: 8638630

Claim:
A device comprising: a plurality of local bit lines; at least one word line; a plurality of memory cells each connected to an associated one of the local bit lines and the word line; at least one global bit line; a plurality of switch transistors, a selected one of the switch transistors being turned ON to form an electrical path between the global bit line and a selected one of the local bit lines; a global sense amplifier coupled to the global bit line, the global sense amplifier being configured to receive, through the global bit line, data that is read out from the memory cell connected to the selected one of the local bit lines, and restore, through the global bit line, the data into the memory cell connected to the selected one of the local bit lines; and a plurality of restoring circuits each provided for an associated one of the local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from the memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.