Patent ID: 7673295

Claim:
A method for compile-time detection of non-concurrency in a parallel program having a base language and a parallel programming language, the method comprising: modeling a program control flow of a subroutine of the parallel program, utilizing at least one processing unit, in a control flow graph having plural phases, wherein each phase having plural nodes; modeling a program hierarchical loop structure of the subroutine of the base language and a parallel programming language constructs in a region tree of the subroutine, utilizing the at least one processing unit, wherein the region tree comprises at least one construct edge defining a cycle between at least one end construct directive node and at least one begin construct directive node, wherein the at least one construct edge does not reflect control transfer of a the subroutine; analyzing the control flow graph and the region tree, utilizing the at least one processing unit, to identify plural parallel regions; analyzing a parallel region, utilizing the at least one processing unit, to identify plural static phases, each static phases having one or more nodes; and comparing nodes of the control flow graph and nodes of the static phases, utilizing the at least one processing unit, to determine non-concurrency at compile time for nodes in the same phase.