Patent ID: 7750384

Claim:
A non-volatile memory device, comprising: first and second consecutively arranged cell gates formed in a cell region of a semiconductor substrate, wherein the first and second cell gates each comprise a floating gate and a control gate; first and second consecutively arranged peripheral gates formed in a peripheral region of the semiconductor substrate; an ion implantation region provided in the semiconductor substrate between the first and second cell gates; an inter-gate plug provided on the ion implantation region between the first and second cell gates, the inter-gate plug including a first insulating layer, a second conductive layer formed over the first insulating layer, and a third insulating layer formed over the second conductive layer; a first inter-gate spacer formed between the first and second peripheral gates; and a second inter-gate inter-gate spacer formed between the first and second peripheral gates, wherein the first insulating layer isolates the second conductive layer from the ion implantation region, wherein the first and second inter-gate spacers each includes a first insulating film, a second conductive film, and a third insulating film, and wherein the first insulating film, the second conductive film, and the third insulating film of the first inter-gate spacer correspond to the first insulating layer, the second conductive layer, and third insulating layer of the inter-gate plug, respectively.