Patent ID: 7585716

Claim:
A method of forming a semiconductor structure comprising: providing a structure including a sacrificial gate and a gate dielectric located on a semiconductor substrate, said structure further including an interlevel dielectric located on said semiconductor substrate and separated from said sacrificial gate by a sacrificial spacer; removing the sacrificial gate and a portion of the gate dielectric that is not protected by the sacrificial spacer to form an opening that exposes a surface of the semiconductor substrate; forming a U-shaped high-k gate dielectric and a metal-containing gate conductor inside the opening; removing the sacrificial spacer to expose a portion of the U-shaped high-k gate dielectric that laterally abuts sidewalls of the metal-containing gate conductor; removing substantially all of the exposed portion of the high-k gate dielectric that laterally abuts the sidewalls of the metal-containing gate conductor from the gate sidewalls; and forming a gate spacer in an area that previously included the sacrificial spacer and a portion of the U-shaped high-k gate dielectric to provide at least one MOSFET comprising a gate stack including, from bottom to top, the high-k gate dielectric and the metal-containing gate conductor, said metal-containing gate conductor having gate corners located at a base segment of the metal-containing gate conductor, wherein said metal-containing gate conductor has vertical sidewalls devoid of said high-k gate dielectric except at said gate corners, and wherein the gate dielectric is laterally abutting said high-k gate dielectric which is present at said gate corners and said gate spacer is laterally abutting said metal-containing gate conductor and is located upon an upper surface of both the gate dielectric and the high-k gate dielectric that is present at the gate corners.