Patent ID: 6944295

Claim:
A method of generating a random number sequence, particularly in a chip card or smart card, characterized by the steps of (a) scanning the outputs of Nosz independent frequency oscillators and buffering corresponding Nosz output signals of the Nosz frequency oscillators at each clock of a clock signal from an external clock signal source, (b) applying the buffered signals of step (a) to a logic operation assigning a predetermined output value to the Nosz buffered signals as input values, (c) generating the parity of a predetermined number Nlog of output values of step (b) at each Nlog th clock of the external clock signal, (d) storing a predetermined number Nz of parity numbers in a random-number register, and (e) reading all of the Nz*Nlog clocks of the clock signal as a random number from the random-number register.