Patent ID: 8536009

Claim:
A method, comprising: selectively forming a threshold voltage adjusting semiconductor alloy on a first semiconductor region while preventing said threshold adjusting semiconductor alloy from being formed on a second semiconductor region and a third semiconductor region; forming a first gate electrode structure of a first transistor above said first semiconductor region including said threshold voltage adjusting semiconductor alloy, said first gate electrode structure having a first gate length; forming a second gate electrode structure of a second transistor on said second semiconductor region, said second gate electrode structure having a second gate length that is less than said first gate length, the first and second gate electrode structures comprising a high-k dielectric material; forming first drain and source regions in said first semiconductor region; forming second drain and source regions in said second semiconductor region, said first and second drain and source regions having the same conductivity type; and forming third drain and source regions in said third semiconductor region, said third drain and source regions having an inverse conductivity type relative to said same conductivity type of said first and second transistors.