Patent ID: 7120855

Claim:
A survivor path memory circuit, which is used in a Viterbi decoder to receive decision bit signals and output decoded data according to the decision bit signals, the survivor path memory circuit comprising: a plurality of survivor paths, each having a plurality of multiplexers connected in series; each of the multiplexers having at least two input terminals, selection terminal and an output terminal, the output terminal of each multiplexer being connected to one of the input terminals of another multiplexer in a survivor path, and being connected to the input terminals of other multiplexers in other survivor paths; and a plurality of decision bit paths, each having a plurality of register nodes connected in series for receiving the decision bit signal, delaying the decision bit signals, and outputting the output signal of each register node to the corresponding multiplexer in the survivor paths; wherein the data flow direction of the survivor paths is opposite to the data flow direction of the decision bit paths.