Patent ID: 7190667

Claim:
A Link Packet Scheduler for each virtual lane (VL) at a given port, comprising: a N—bit counter arranged to accumulate free credits relinquished, when a data packet is removed from a receive buffer and buffer space is reclaimed as available for data packet storage, or when a link packet is received whose Flow Control Total Bytes Sent (FCTBS) field differs from actual blocks received (ABR) at the given port; a first comparator arranged to make comparison between accumulated free credits from the N—bit counter and a programmable credit threshold; a second comparator arranged to make comparison between a current buffer receive utilization indicating a data storage level of the receive buffer and a programmable utilization threshold; and a logic device arranged to track a current link state of a corresponding port, to monitor amount of receive buffer resources from the first and second comparators and to schedule a link packet transmission, via a physical link.