Patent ID: 7281178

Claim:
An integrated circuit, comprising: a critical path that traverses a block of input logic, a memory block and a block of output logic, the memory block having a memory, at least one input and at least one output, the at least one input coupled to the block of input logic and the at least one output coupled to the block of output logic, the memory block also having a write-enable input; and a bypass circuit coupled to the write-enable input of the memory block and a control output of the block of input logic, the bypass circuit operable to verify the block of input logic and the block of output logic, such that when the bypass circuit is enabled responsive to a scan mode, a logic signal propagates along the critical path of the integrated circuit in a specified number of clock cycles and when the bypass circuit is disabled, the logic signal propagates along the critical path of the integrated circuit in the same specified number of clock cycles wherein the bypass circuit is exclusive of the critical path.