Patent ID: 8018751

Claim:
A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns, comprising: a first storage circuit that stores a first data value and has a first data path coupled to a first storage node and a second data path coupled to a second storage node; a second storage circuit that stores a second data value and has a third data path coupled to a third storage node and a fourth data path coupled to a fourth storage node; a compare circuit that generates a match result at a match node based on the first data value, second data value, and a compare data value; and no more than four conductive lines in the column wise direction having a direct electrical connection to the TCAM cell for providing non-power supply signals, including a first bit line coupled to the first data path, a second bit line coupled to the third data path, a first shared bit line coupled to the second data path and the compare circuit, and a second shared bit line coupled to the fourth data path and the compare circuit; wherein the first data path and second data path are commonly coupled to a first word line; and the third data path and fourth data path are commonly coupled to a second word line.