Patent ID: 8760909

Claim:
A manufacturing method of a memory, comprising: forming a plurality of stacked structures on a substrate, the stacked structures extending along a first direction, each of the stacked structures comprising a plurality of first insulation layers and a plurality of second insulation layers, the first insulation layers being stacked on the substrate, each of the second insulation layers being respectively located between two adjacent first insulation layers of the first insulation layers; removing a first portion of each of the second insulation layers and retaining a second portion of the each of the second insulation layers to form a plurality of trenches in each of the stacked structures, the trenches extending along the first direction and being located at two opposite sides of the second portion of the each of the second insulation layers; filling the trenches with a first conductive layer; and forming a plurality of charge storage structures on the stacked structures and forming a second conductive layer on each of the charge storage structures, the charge storage structures extending along a second direction.