Patent ID: 6927474

Claim:
A method of operating an integrated circuit, the integrated circuit including: an antifuse having: a first metal antifuse plate; a layer of dielectric material connected to the first metal antifuse plate; and a second metal antifuse plate connected to the layer of dielectric material and vertically aligned with the first metal antifuse plate, the second metal antifuse plate having a thickness, a length, and a width; a layer of isolation material connected to the second metal antifuse plate; a via formed through the layer of isolation material to make an electrical connection with the second metal antifuse plate, the via having a length, a width, and a substantially uniform thickness, the length and width of the via being substantially less than the length and width, respectively, of the second antifuse plate; a first metal trace positioned horizontally-adjacent and connected to the first metal antifuse plate, the first metal antifuse plate being a wider extension of the first metal trace; and a second metal trace formed on the layer of isolation material to contact the via, the second metal trace being vertically spaced apart from the first metal trace and the second metal antifuse plate; the method comprising the steps of: forming a voltage difference across the first and second metal antifuse plates; and removing the voltage difference from the first and second metal antifuse plates when a predetermined condition occurs, a conductive path being formed from the second metal antifuse plate to the first metal antifuse plate when the predetermined condition occurs.