Patent ID: 8504855

Claim:
A method for conserving power in a computing device having a plurality of resources and at least one processor, comprising: defining a plurality of low power resource modes in a compilable expression, the low power resource modes identifying a set of resource dependencies, power savings and latency time characteristics associated with a resource as well as a low power state into which each of the plurality of resources can be placed when not in use; compiling, by the processor, the defined plurality of low power resource modes to generate one or more synthetic low power resources each having one or more synthetic low power resource modes that represent functionality, power savings, latency and resource dependencies characteristics of one or more of the low power resource modes; defining for each of the synthetic low power resource modes an associated backoff time indicating an amount of time to be allowed for the synthetic low power resource mode to exit before a next scheduled wakeup event occurs; selecting at most one synthetic low power resource mode for each synthetic low power resource based on the synthetic low power resource mode's power savings, latency time, and dependency requirements; and entering and exiting the selected synthetic low power resource modes in the appropriate order when the processor becomes and leaves idle.