Patent ID: 7915940

Claim:
A differential latch comprising a first inputting transistor, a second inputting transistor, a first data holding transistor, and a second data holding transistor, said differential latch comprising: a first switching transistor that is connected to a gate electrode of said first data holding transistor and said second inputting transistor, and is controlled by a switch signal, being an inverted version of a reset signal; a first resetting transistor that is connected to the gate electrode of said first data holding transistor and a ground, and is controlled by said reset signal; a second switching transistor that is connected to the gate electrode of said second data holding transistor and said first inputting transistor, and is controlled by said switch signal; and a second resetting transistor that is connected to the gate electrode of said second data holding transistor and a power source, and is controlled by an inverted reset signal, being an inverted version of said reset signal.