Patent ID: 7979552

Claim:
A system comprising: a hardware compute element enabled to execute a system management process operable to access a networked computing system template, the system management process further operable to instantiate a networked computing system according to the template; a pool of free primitives comprising a pool of free hardware primitives, the pool of free hardware primitives comprising one or more partitionable symmetric multiprocessors having at least two portions, each portion operable as a symmetric multiprocessor, and each portion being coupled by one or more links, the links being configurable in a first mode to isolate two or more of the portions from each other and in a second mode to enable two or more of the portions to communicate memory coherency transactions with each other; and wherein the hardware compute element, on behalf of the system management process, is enabled to perform shared memory coherency transactions that are isolated by hardware from the pool of free hardware primitives, the template comprises a hardware manifest of required hardware primitives, and the hardware manifest comprises a description of a required number of partitions of the partitionable symmetric multiprocessors, each of the required number of the partitions comprising at least one of the portions operable as a symmetric multiprocessor.