Patent ID: 8484409

Claim:
A nonvolatile memory controller for controlling a nonvolatile memory configured from a plurality of physical blocks, the nonvolatile memory controller comprising: a control unit for controlling writing and/or reading of data to and from a physical block, selected out of the plurality of physical blocks, based on a logical address received from an external device, within an effective logical address range from a minimum logical address to a maximum logical address; a logical defective cluster table for storing, while the minimum logical address and the maximum logical address remain unchanged, a logical address of a logical defective cluster which is one or more partial areas within the effective logical address range and in which reflection of the writing of data to the logical address of the logical defective cluster is disabled; and an address conversion table for storing logical addresses within the effective logical address range in correspondence with physical addresses of the plurality of physical blocks, wherein, upon receiving a data write command from the external device for writing data to the logical address of the logical defective cluster stored in the logical defective cluster table, the control unit disables the reflection of writing of data for the logical address of the logical defective cluster stored in the logical defective cluster table.