Patent ID: 8227315

Claim:
A method for manufacturing an iT-FET semiconductor device on a semiconductor substrate having a doped bottom layer functioning as a bottom source region, the method further comprising: opening a trench in the semiconductor substrate followed by doping a body region surrounding a lower portion of the sidewalls of the trench and below a bottom surface of the trench and doping a source region below the bottom surface of the trench encompassed in the body region; depositing a polysilicon layer into the trench followed by etching a central hole in the polysilicon layer in the trench for forming a trenched gate as the polysilicon layer attached to the trench sidewalls followed by doping a body contact region below the source region through the central hole wherein the trenched gate on the sidewalls controlling a vertical channel formed along said trenched gate in said body region for conducting a current vertically between a top drain electrode to the bottom source region.