Patent ID: 8164604

Claim:
A flat panel display device, comprising: a display panel having a non-defect area and a panel defect area; a memory to store first compensation data for compensating the panel defect area and, a second compensation data for compensating a boundary between the panel defect area and the non-defect area; a first compensation part to change a first data that are to be displayed in the panel defect area to the first compensation data by dispersing the first compensation data to the panel defect area; a second compensation part to change a second data that are to be displayed in a fixed area inclusive of the boundary to the second compensation data by dispersing the second compensation data to the fixed area inclusive of the boundary; and a driver for driving the display panel using the first and second data which are changed by the first and second compensation parts, wherein the first compensation part comprises: a location judging part judging and outputting a first location information of the first data; a gray level judging part analyzing and outputting a first gray level information of the first data; an address generating part generating a read address for reading the first compensation data of the memory using the first location information and the first gray level information, wherein the memory outputs the first compensation data in accordance with the first read address; and a FRC (Frame Rate Control) controller compensating the first data with the first compensation data by dispersing the first compensation data for a plurality of frame periods in the panel defect area, wherein the second compensation part comprises: a location judging part judging and outputting a second location information of the second data; a gray level judging part analyzing and outputting a second gray level information of the second data; an address generating part generating a second read address for reading the second compensation data of the memory using the second location information and the second gray level information, wherein the memory outputs the second compensation data in accordance with the second read address; and a FRC controller compensating the second data with the second compensation data by dispersing the second compensation data for a plurality of frame periods in the boundary.