Patent ID: 7488635

Claim:
A method for forming a semiconductor structure comprising: providing a substrate having a memory region and a logic region; and forming a first p-type device in the memory region and a second p-type device in the logic region, wherein at least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device, the semiconductor gates of the first and second p-type devices each having a non-zero p-type dopant concentration, wherein forming further comprises: performing a diffusion-reducing implant in a semiconductor gate layer corresponding to the first p-type device and the second p-type device, and wherein the memory region further comprises a first device region having p-type devices and a second device region having n-type devices, and wherein the diffusion-reducing implant is performed in the semiconductor gate layer in only the first device region of the memory region, prior to forming the semiconductor gates of the first and second p-type devices.