Patent ID: 7482231

Claim:
A method of manufacturing a semiconductor device, comprising: forming a first gate stack on an array region of a substrate and a second gate stack on a periphery region of the substrate, wherein the first gate stack has a first sidewall and the second gate stack has a second sidewall; forming a first dielectric material over the substrate to cover the first gate stack and the second gate stack; forming a lightly doped drain region in the periphery region; forming a charge-storing material over the first dielectric material; forming a second dielectric material over the charge-storing material; removing portions of the first, dielectric material, the charge-storing material, and the second dielectric material, such that a first storage structure is formed adjacent to the first sidewall of the first gate stack, and a second storage structure is formed adjacent to the second sidewall of the second gate stack; forming a first source/drain region in the array region; depositing a third dielectric material over the substrate.