Patent ID: 8405142

Claim:
A semiconductor memory device comprising: a substrate; a multilayer body provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, including a valley made of a pair of staircases opposed to each other and including a terrace for each of the electrode films, and being not full divided by the valley; a first contact connected to a portion of the each of the electrode films constituting the terrace of one of the staircases; a second contact connected to a portion of the each of the electrode films constituting the terrace of another of the staircases; an interconnection connected to the first contact and the second contact; a semiconductor member provided in a portion of the multilayer body on a side of the first contact as viewed from the valley, the semiconductor member extending in a stacking direction of the insulating films and the electrode films; and a charge storage layer provided between the each of the electrode films and the semiconductor member.