Patent ID: 7450455

Claim:
A semiconductor memory device, comprising: a bit line sense amplifier for sensing and amplifying data supplied on a bit line; a supply line driver for supplying pull-up and pull-down supply lines coupled to the bit line sense amplifier with a pull-up voltage and a pull-down voltage, wherein the pull-down voltage is adjusted according to an operation period, wherein the pull-down voltage is adjusted to a first pull-down voltage in a first driving period and is adjusted to a second pull-down voltage in a second driving period, and wherein the first driving period is an initial sensing and amplifying period of the bit line sense amplifier and the second driving period is a stable period after the initial sensing and amplifying period, wherein the first driving period extends from an enable time of the bit line sense amplifier to an input time of a precharge command and the second driving period extends from the input time of the precharge command to a disable time of the bit line sense amplifier.