Patent ID: 8854062

Claim:
A readout circuit for processing a transducer signal from a capacitive transducer and producing a circuit output signal, the readout circuit comprising: a high gain circuit element receiving the transducer signal and generating an amplified transducer signal; a first summing amplifier implemented by active circuitry, the first summing amplifier summing the amplified transducer signal with a positive reference voltage and generating a first summation signal; a second summing amplifier implemented by active circuitry, the second summing amplifier summing the amplified transducer signal with a negative reference voltage and generating a second summation signal, the negative reference voltage having substantially the same magnitude but opposite polarity of the positive reference voltage; a first feedback path feeding back the first summation signal to the capacitive transducer; a second feedback path feeding back the second summation signal to the capacitive transducer; and output circuitry generating the circuit output signal based on the first summation signal and the second summation signal.