Patent ID: 7446685

Claim:
A read signal processing circuit, comprising: an AD converter that converts an analog read signal into a digital read signal; a DFB slicer that processes the digital read signal; a DC component detector that detects a DC component remaining in an output from the DFB slicer; a subtracter that subtracts an output from the DC component detector from the output from the DFB slicer; a phase comparator that performs a comparison between a phase of an output from the subtracter and a phase of a channel clock signal; a loop filter to which an output from the phase comparator is inputted; a DA converter that converts an output from the loop filter into an analog voltage signal; a VCO that oscillates at a frequency specified by the analog voltage signal supplied from the DA converter and thereby generates the channel clock signal; and a Viterbi decoder to which an output from the subtracter is inputted.