Patent ID: 8216932

Claim:
A method of manufacturing semiconductor devices having metal lines, the method comprising: forming a first pre-metal dielectric layer having a trench on a semiconductor substrate; forming a diffusion barrier layer on an entire surface of the first pre-metal dielectric layer including the trench; forming a metal layer on the diffusion barrier layer to fill the trench; performing a polish etching process on the metal layer to expose a top surface of the first pre-metal dielectric layer, wherein portions of the metal layer and the diffusion layer are exposed between the exposed first pre-metal dielectric layer; performing an etching process to lower a height of the metal layer to increase a distance between metal lines so that a portion of side walls of the first pre-metal dielectric layer is exposed; forming a capping layer along an entire surface after performing the etching process; forming a second pre-metal dielectric layer over the capping layer; performing a polish etching process on the second pre-metal dielectric layer, the capping layer, and a portion of the first pre-metal dielectric layer; and forming a third pre-metal dielectric layer over the first pre-metal dielectric layer, the capping layer, and the second pre-metal dielectric layer.