Patent ID: 8901725

Claim:
A semiconductor device comprising: a laminated structure in which a plurality of wiring layers is stacked in a state that a plurality of insulating layers is interposed therebetween and a first outermost insulating layer is arranged on one side of the laminated structure, and a second outermost insulating layer is arranged on another side of the laminated structure, and the plurality of wiring layers is connected through a plurality of vias formed in the insulating layers, wherein the plurality of wiring layers includes at least an inner wiring layer, an outer wiring layer, and a third wiring layer, wherein the plurality of vias includes at least a first via, a second via and a third via; a semiconductor element buried in the first outermost insulating layer, wherein an end face of an electrode terminal, an electrode terminal formation face and a side face of the semiconductor element are coated with the first outermost insulating layer, and a face opposite to the electrode terminal formation face of the semiconductor element is exposed from a surface of the first outermost insulating layer, and the second via formed in the first outermost insulating layer is directly connected to the end face of the electrode terminal of the semiconductor element; and a sheet-shaped member buried in the second outermost insulating layer, wherein one face of the sheet-shaped member is covered with the second outermost insulating layer, other face of the sheet-shaped member contacts an inner insulating layer, of the plurality of insulating layers, located at an inside of the second outermost insulating layer, the sheet-shaped member having a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element, wherein the sheet-shaped member has an opening portion in a part that the first via is arranged, and an outer wiring layer, of the plurality of wiring layers, located at a surface of the second outermost insulating layer is connected to an inner wiring layer, of the plurality of wiring layers, located at an inside of the outer wiring layer by the first via which penetrates the second outermost insulating layer located in the opening portion and the inner insulating layer, and the second outermost insulating layer is formed between a side wall of the opening portion and the first via, and all of the plurality of vias has a taper shape such that diameter of the vias decreases gradually from the second outermost insulating layer side toward the semiconductor element side, and a thickness of the first outermost insulating layer is thicker than a thickness of the other insulating layers, wherein the sheet-shaped member is formed of a member of the group consisting of alloy 42, alloy 36, or kovar, a carbon fiber cloth, and ceramic material.