Patent ID: 8302066

Claim:
A clock jitter suppression method for suppressing clock jitter in a semiconductor integrated circuit having a clock buffer configured to receive a clock, comprising: setting an arbitrary logic value to storage elements that are coupled to the clock buffer; variably setting a threshold voltage of the storage elements; reading a value held in the storage elements in a state where an analyzing target circuit within the semiconductor integrated circuit operates; performing an analyzing process to specify an extent of an effect of noise in a power supply voltage or a ground voltage of the clock buffer and to specify a location where the effect of the noise is greater than or equal to a predetermined amount within the semiconductor integrated circuit, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set arbitrary logic value and each storage element that is a read target; performing a constraint condition creating process to create a constraint condition for placement of constituent elements of the semiconductor integrated circuit and routing within the semiconductor integrated circuit based on results of the analyzing process; and performing one of a re-placement process to modify and re-place the placement of the constraint condition and a re-routing process to modify and re-route the routing of the constraint condition, in order to reduce the noise.