Patent ID: 8248834

Claim:
A semiconductor device comprising: a first global bit line and a second global bit line; a first memory mat that includes a plurality of first hierarchy switches each connected to the first global bit line, and a plurality of first local bit lines each connected to the first global bit line via an associated one of the first hierarchy switches; a second memory mat that includes a plurality of second hierarchy switches each connected to the second global bit line, and a plurality of second local bit lines each connected to the second global bit line via an associated one of the second hierarchy switches; a sense amplifier that is arranged between the first and second memory mats and amplifies a potential difference between the first and second global bit lines; and a control circuit that activates one of the first hierarchy switches and one of the second hierarchy switches, wherein the control circuit activates one of the first hierarchy switches and one of the second hierarchy switches having a substantially equal distance from the sense amplifier along the first global bit line and the second global bit line, respectively.