Patent ID: 7642653

Claim:
A semiconductor device comprising: a semiconductor substrate; a semiconductor element formed in the semiconductor substrate; an interlayer dielectric film disposed on the semiconductor substrate; a plurality of wiring layers that are separated from one another through the interlayer dielectric film and electrically coupled to the semiconductor element through the interlayer dielectric film; a bonding pad electrically coupled to a top wiring layer of the plurality of wiring layers, the bonding pad being configured to be bonded to a metal bonding wire for electrically coupling the semiconductor element to an external device; and a contact member disposed in a through hole in the interlayer dielectric film, wherein the top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad, wherein the top wiring-electrode layer is formed with a first material having a first Young's Modulus value, wherein the bonding pad is formed with a second material having a second Young's Modulus value less than the first Young's Modulus value, wherein the electrode layer of the top wiring-electrode layer is disposed directly above the semiconductor element, wherein the bonding pad and the electrode layer are multilayered to form a pad structure, wherein the interlayer dielectric film includes an insulation film that surrounds the top wiring-electrode layer to cover sidewalls of the top wiring-electrode layer, wherein a thickness of the bonding pad is set, so that the bonding pad remains interposed between the bonding wire and the top wiring-electrode layer after the bonding wire is wire-bonded to the bonding pad, wherein an outer edge of the top wiring-electrode layer is separated from an outer edge of a contact surface between the bonding wire and the bonding pad by at least 1 μm in a direction parallel to the contact surface, and the contact member is positioned directly below the contact surface and couples the top wiring-electrode layer to a bottom wiring layer of the plurality of wiring layers.