Patent ID: 7211864

Claim:
An improved fully-depleted castellated-gate MOSFET device having robust I/O applications, said device comprising: a silicon semiconductor substrate having an upper portion with a top surface and a lower portion with a bottom surface; a source region, a drain region, and a channel-forming region disposed between said source and drain regions, all of which are formed in said semiconductor substrate body; trench isolation insulator islands having upper and lower surfaces and surrounding said source and drain regions and said channel-forming region; said channel-forming region comprising a plurality of thin, spaced, vertically-oriented conductive channel elements that span longitudinally along said device between said source and drain regions; a gate structure in the form of a plurality of spaced, castellated conductive gate elements interposed longitudinally between and outside of said channel elements, and a top gate member interconnecting said gate elements at their upper vertical ends to cover said channel elements, said gate elements having a depth less than the lower surface of said shallow trench isolation islands; a dielectric layer separating said conductive channel elements from said gate structure; and a buried insulator layer formed in said semiconductor body lower portion beneath said source and drain regions.