Patent ID: 8051340

Claim:
A system for balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit, comprising: a plurality of communication paths between the analog domain and the digital domain, each of said plurality of communication paths including a tunable delay element therein, with a selected one of said communication paths configured for the application of a test signal therethrough; means for equalizing a rising edge delay and a falling edge delay of said test signal by adjustment of a body bias voltage of a corresponding one of said tunable delay elements within said selected communication path; means for comparing a rising edge delay and a falling edge delay for each of the remaining of said plurality of communication paths with the equalized rising edge delay and falling edge delay of said selected communication path; and means for adjusting a body bias voltage for one or more of said tunable delay elements within each of the remaining of said plurality of communication paths until corresponding rising and falling edge delays thereof match said equalized rising edge delay and falling edge delay of said selected communication path.