Patent ID: 8283962

Claim:
A semiconductor device comprising: a reset signal generating unit configured to generate a plurality of reset signals in response to a control signal, wherein the plurality of the reset signals have different activation timings according to a constant phase difference; and a multi-phase clock signal generating unit configured to divide a frequency of a source clock signal in response to the plurality of the reset signals in order to generate a plurality of phase clock signals having the constant phase difference, wherein each reset signal of the plurality of reset signals is generated by shifting a previous reset signal, wherein the source clock signal has twice the frequency of the phase clock signals, wherein the plurality of the phase clock signals include first to fourth phase clock signals having the constant phase difference, wherein the plurality of the reset signals include first positive and negative reset signals corresponding to the first phase clock signal, second positive and negative reset signals corresponding to the second phase clock signal, third positive and negative reset signals corresponding to the third phase clock signal and fourth positive and negative reset signals corresponding to the fourth phase clock signal.