Patent ID: 7944963

Claim:
A system for compensating jitter in receiver circuits using a nonlinear dynamic phase shifting technique based upon bit history pattern between a decoder and receiver, the system comprising a phase shifter for receiving an original bit stream having bit transitions from the decoder, the phase shifter comprising a bit history detector, a phase delay look-up table, a delay element and a multiplexor, the delay element for receiving an undelayed bit stream and delaying the undelayed bit stream and passing the delayed bit stream to the multiplexor, the bit history detector for inspecting the undelayed bit stream, for detecting a bit transition in the undelayed bit stream after at least two consecutive bit non-transitions, for passing bit transition information of the undelayed bit stream to the phase delay look-up table, the phase delay look-up table for selecting a phase delay value based upon the bit transition information and passing the phase delay value to the multiplexor, the multiplexor for delaying the delayed bit stream based upon the phase delay value and passing the delayed bit stream to the receiver; wherein the phase delay decision for a given bit stream is based upon the phase delay decisions for at least one previous bit stream having the same bit pattern of consecutive non-transitions and based upon the history of bits prior to the bit pattern of consecutive non-transitions of the at least one previous bit stream.