Patent ID: 8169760

Claim:
A design structure that is tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit that when processed on a data processing system generates a functional representation of the integrated circuit, the design structure comprising: a signal pad electrostatic discharge (ESD) device coupled to an I/O signal pad; and a power supply ESD device coupled to a source VDD, wherein the signal pad ESD device and the power supply ESD device are integrated in a single ESD structure comprising: a FET coupled to a parasitic transistor; a collector of the parasitic transistor and a source of the FET coupled to the I/O signal pad; an emitter of the parasitic transistor and a drain and gate of the FET coupled to ground; a base of the parasitic transistor coupled to the ground through a resistor; and a second emitter of the parasitic transistor coupled to the source VDD.