Patent ID: 8018271

Claim:
A semiconductor integrated circuit, comprising: a first flip-flop, a combined circuit and a second flip-flop that are connected in series; a first delay circuit and a third flip-flop connected in series that are provided in parallel with the second flip-flop in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop connected in series that are provided in parallel with the second flip-flop in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop; and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the output of the first comparison circuit and the output of the second comparison circuit, wherein the first delay circuit outputs a signal inputted from the combined circuit after a first delay time and the second delay circuit outputs a signal inputted from the combined circuit after a second delay time different from the first delay time.