Patent ID: 7151418

Claim:
An apparatus, comprising: a phase locked loop (PLL) comprising a charge pump, the charge pump comprising an input and an output; and a bias circuit coupled to the input of the charge pump, the bias circuit comprising: a sensor circuit to sense a temperature and at least one of a voltage and a process variation, the sensor circuit comprising: at least one buffer gate coupled to each other in series to delay a reference clock signal, and an exclusive-OR (XOR) gate comprising a first input, a second input, and an output, the first input to receive the delayed reference clock signal, the second input to receive the reference clock signal; a current reference circuit coupled to the sensor circuit; a pull-up transistor driven by the current reference circuit to provide a reference current substantially insensitive to the temperature, the voltage, and the process variation; and a pull-down transistor coupled to the pull-up transistor, the pull-down transistor being driven by the output of the XOR gate of the sensor circuit.