Patent ID: 8471597

Claim:
A circuit, comprising: a clock input for at least one clock signal; a clock buffer connected to the clock input configured to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal; a plurality of flip-flops connected to the clock buffer, each of which is configured to receive the first modified clock signal and the second modified clock signal; a plurality of data inputs, each being connected to at least one of the plurality of flip-flops, to provide input data to the plurality of flip-flops; and a plurality of data outputs, each being connected to at least one of the plurality of flip-flops, configured to provide output data from the plurality of flip-flops, wherein each of the plurality of flip-flops is configured to transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal generated from the clock buffer; wherein the clock buffer comprises: at least a first clock inverter and a second clock inverter, connected to one another in series, wherein the first clock inverter is configured to receive the at least one clock signal and generate the first modified clock signal from the at least one clock signal, and wherein the second clock inverter is configured to receive the first modified clock signal and generate the second modified clock signal from the first modified clock signal.