Patent ID: 8338894

Claim:
A method, comprising: masking a first semiconductor region of a first transistor having formed thereon a first gate electrode structure comprising a first sidewall spacer structure, while exposing a second semiconductor region of a second transistor having formed thereon a second gate electrode structure comprising a second sidewall spacer structure; forming deep drain and source regions in said second semiconductor region by using said second gate electrode structure as an implantation mask; removing at least a portion of said second sidewall spacer structure; forming first cavities in said first semiconductor region on the basis of said first sidewall spacer structure; forming second cavities in said second semiconductor region after removing at least said portion of said second sidewall spacer structure, wherein forming said second cavities is performed by the same process as forming said first cavities; forming deep drain and source regions in said first cavities; forming drain and source extension regions in said second semiconductor region; and forming a strain-inducing semiconductor material in said first and second cavities.