Patent ID: 7598592

Claim:
A capacitor structure for an integrated circuit, comprising: an insulating layer disposed on a substrate; a first conductive line embedded in a first level of the insulating layer; a second conductive line embedded in a second level of the insulating layer lower than the first level and having a projection onto the substrate completely covered by the first conductive line; and a third conductive line embedded in the second level of the insulating layer, separated from the second conductive line by a predetermined space and having a projection onto the substrate partially covered by the first conductive line; wherein the second conductive line is coupled to the first conductive line by at least one first conductive plug and has a polarity opposite to the third conductive line; wherein the first, second and third conductive lines have first, second and third line widths, respectively, and the first line width is substantially equal to the sum of the second and third line widths.