Patent ID: 6968027

Claim:
A digital PLL device comprising: a first selector for selecting and outputting one of a first synchronous timing signal and a second synchronous timing signal; a comparator for detecting a phase difference between the synchronous timing signal selected by said first selector and an internal synchronous timing signal, and outputting phase correction data corresponding to the phase difference; a hold over unit for outputting hold over data used for performing phase correction; a second selector for selecting and outputting one of the phase correction data supplied from said comparator and the hold over data supplied from said hold over unit, said second selector selecting the output from said hold over unit when a hold over mode is set; a digital VCO for creating a clock signal with a frequency corresponding to data supplied from the second selector; a filter for creating an internal synchronous timing signal from the clock signal created by said digital VCO; and a controller for controlling said selectors and changing over the first synchronous timing signal to the second synchronous timing signal at switching of synchronous timing over a digital synchronous network, said controller setting the hold over mode during the changeover of the synchronous timing over the digital synchronous network, wherein the hold over unit comprises: an up/down counter, the addition/subtraction of said up/down counter being controlled by the phase correction data supplied from said phase comparator, a memory for storing, as the hold over data, a count value of said up/down counter every K (integer) frames, a memory controller for performing read control, write control, and address control of said memory, and a decoder for decoding the hold over data read from said memory to frequency of corrections and a correction value, and outputting the number of corrections and the correction value, and wherein said memory controller performs the read control of said memory in the hold over mode, and performs the write control of said memory when the synchronous timing signal supplied from said first selector is synchronizing with the internal timing signal.