Patent ID: 7803680

Claim:
A method for manufacturing a memory device, comprising: performing a shallow trench isolation (STI) process on a semiconductor material to form a plurality of active regions and a plurality of isolation regions, the plurality of active regions being formed to comprise a plurality of exposed corners; forming a plurality of charge trapping structures over the plurality of active, regions, wherein the plurality of charge trapping structures are self-aligned; separating the plurality of charge trapping structures at their respective bottom portions such that the respective bottom portions of the plurality of charge trapping structures are separated by a distance that is greater than the distance separating respective top portions of the plurality of charge trapping structures; forming a first layer of semiconductor or conductive material over the plurality of charge trapping structures, wherein the shallow trench isolation process is performed before the plurality of charge trapping structures is formed; and further wherein, a rounding process is performed on the plurality of exposed corners of the active region after the shallow trench isolation process is performed.