Patent ID: 7649957

Claim:
A multi-stage clock generator architecture that generates multiple non-overlapping clock phases, the clock generator architecture comprising: a back end clock generator having an input for a main clock signal, the back end clock generator being configured to generate, based on the main clock signal, a first primary clock signal and a second primary clock signal that is non-overlapping with the first primary clock signal, wherein the first primary clock signal and the second primary clock signal are periodic signals generated at a same frequency so that each pulse of the second primary clock signal has a rising edge and a falling edge that occur between and at different times from a falling edge of a pulse of the first primary clock signal and a rising edge of a next pulse of the first primary clock signal; and a second stage clock generator coupled to the back end clock generator, the second stage clock generator having a first input for a first signal that is based upon the first primary clock signal and a second input for a second signal that is based upon the second primary clock signal, the second stage clock generator being configured to generate, in response to the first signal and the second signal, a first clock phase signal based upon the first primary clock signal, a second clock phase signal based upon the first primary clock signal, a third clock phase signal based upon the second primary clock signal, and a fourth clock phase signal based upon the second primary clock signal, the first, second, third, and fourth clock phase signals being mutually non-overlapping.