Patent ID: 8036228

Claim:
A system, comprising: a plurality of peripheral devices, each of the plurality of peripheral devices configured to specify its minimum quality of service (QOS) level; and a physical layer device coupled to the plurality of peripheral devices, the physical layer device configured to assign the minimum QOS level for each of the plurality of peripheral devices and schedule services to meet the assigned QOS level for each of the plurality of peripheral devices, wherein at least one of the plurality of peripheral devices is a Time Division Multiplexing (TDM) peripheral device, wherein in hardware, the TDM peripheral device utilizes a physical (PHY) level interface for frame timing logic and serialization, and in software, the TDM peripheral device is configured to treat a TDM interface as a constant bit rate (CBR) stream of data, and wherein at least one of the plurality of peripheral devices is an HDLC peripheral device, wherein in hardware, the high-level data link control (HDLC) peripheral device uses the PHY level interface as a bus to simulate timing logic, serialization logic and cell buffers, and in software, the HDLC peripheral device is configured to treat the HDLC interface as a variable bit rate (VBR) stream of data with peak cell rate (PCR) equal to the HDLC controller's line rate and with burst size equal to packet length.