Patent ID: 8924655

Claim:
A method for implementing SRCU with reduced OS jitter in a system having plural CPUs capable of executing concurrent readers and updaters of shared data, comprising: providing a pair of critical section counters for each CPU, one critical section counter of each critical section counter pair being associated with a first grace period and the other critical section counter of each critical section counter pair being associated with a second grace period; when entering an SRCU read-side critical section involving reading said shared data, incrementing one of said critical section counters associated with said first grace period; when exiting an SRCU read-side critical section involving reading said shared data, decrementing one of said critical section counters associated with said first grace period; when updating said shared data, initiating said second grace period and performing a counter summation operation that sums said critical section counters associated with said first grace period to generate a critical section counter sum; storing a snapshot value for each of said critical section counters during said summing; and if said critical section counter sum reaches a value indicating there are no SRCU read-side critical sections in progress for said first grace period, performing a recheck operation that compares said snapshot values to current values of said critical section counters associated with said first grace period to verify that said critical section counter sum is correct.