Patent ID: 7382593

Claim:
A method for linearizing the capacitance of an ESD protection circuit with respect to voltage, the method comprising the steps of: providing a first discharge path to ground via a drain of an NMOS transistor disposed between the pad and ground; transferring at least part of a positive ESD pulse at the pad to the gate of the NMOS thereby turning on the NMOS; providing a second discharge path via a drain of a PMOS transistor disposed between the pad and a positive power rail, wherein the PMOS gate is connected to its source to form a diode connected PMOS with its anode at the pad and its cathode at the power rail, and wherein a positive ESD pulse at the pad turns on the diode connected PMOS, so that a positive ESD pulse is discharged simultaneously through both the first and the second discharge paths, the NMOS and the diode connected PMOS, respectively, and wherein the drain of the NMOS and the drain of the PMOS have capacitance sensitivities with respect to voltage that compensate for each other; and functionally connecting the drain and the substrate of the second PMOS to the substrate of the PMOS; wherein the operation of the second PMOS prevents parasitic transistors in the PMOS from turning on when the positive power rail experiences a rising voltage, and further comprising the step of sizing the NMOS and PMOS transistors so that the voltage sensitivities of the PMOS and the NMOS drain capacitances compensate for each other.