Patent ID: 6989306

Claim:
A fabrication method of forming a trenched DMOS device and a termination structure thereof, the method comprising; forming an N− epitaxial layer on an N+ silicon substrate; forming an oxide layer on the N− epitaxial layer; patterning the oxide layer to form a termination oxide layer therein to define an exposed active area of the DMOS device; implanting P-type ions into the active area by using the termination oxide layer as a mask to form a P body in the N− epitaxial layer. recessing the N− epitaxial layer to form a plurality of DMOS trenches in the P body by patterning and etching, the DMOS trenches having bottoms which extend beneath a bottom of the P body; forming a gate oxide layer over exposed surfaces of the P body; depositing a polysilicon layer over exposed surfaces and also filling the DMOS trenches; recessing the polysilicon layer to form a plurality of polysilicon gates and a polysilicon plate by patterning and etching, wherein the polysilicon gates are positioned in the DMOS trenches and the polysilicon plate is positioned over the termination oxide layer and a portion of the gate oxide layer disposed adjacent the termination oxide layer; implanting N-type ions into the P body by using the polysilicon plate and the termination oxide layer as a mask to form a plurality of N+ diffused regions; forming an isolation layer over exposed surfaces after implanting the N-type ions; patterning and anisotropically etching using a two-step etching process, the isolation layer and the gate oxide layer to form a plurality of body contact windows over the N+ diffused regions, and a first contact window over the polysilicon plate; implanting P-type ions through the body contact windows to form a plurality of P+ diffused regions; and forming a source metal contact layer disposed over the isolation layer, and filling the body contact windows and the first contact window.