Patent ID: RE43417

Claim:
A multi-state flash memory device formed from a substrate in which individual memory cells can store multiple bits represented as charges of more than two possible levels , the device comprising: a plurality of strings of transistors of a NAND architecture, each string of the plurality of strings comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above channel regions in the substrate and separated from the channel regions, wherein a controller circuit is adapted to cause adjacent first and second strings of the plurality of strings to undergo programming operations at the same time , the programming operations including setting different voltages levels in floating gates of the adjacent first and second strings , and wherein when the plurality of strings of transistors is arranged such that, during programming of a selected floating gate of the first string, a change in a potential of a portion of the second adjacent string is shielded from the selected floating gate of the first string by a wordline extending across adjacent strings and extending between floating gates of the first and second strings into a shallow trench isolation trench between the channel regions of the first and second strings.