Patent ID: 8510482

Claim:
In a data processing system having a processor, a direct memory access (DMA) controller, a peripheral that is distinct from the DMA controller, and a memory, a method comprising: asserting a request enable signal, by the DMA controller, which initiates a data transfer between the peripheral and the memory, wherein the data transfer comprises N subsets of data to be transferred between the peripheral and the memory, N having a value of two or more; while the request enable signal is asserted, the peripheral asserting a data request signal to request transfer of a next subset of data within the N subsets of data; in response to the asserting of the data request signal, the DMA controller initiating the transfer of the next subset of data between the memory and the peripheral; after completion of the transfer of the next subset of data between the memory and the peripheral, the peripheral again asserting the data request signal to request transfer of a last subset of data within the N subsets of data; in response to the again asserting the data request signal, the DMA controller initiating the transfer of the last subset of data between the memory and the peripheral, wherein the transfer of the last subset of data between the memory and the peripheral completes the data transfer; deasserting the request enable signal, by the DMA controller, which provides an indication to the peripheral of the completion of the transfer of the last subset of data between the memory and the peripheral; and after the peripheral receives the indication of the completion of the transfer of the last subset of data between the memory and the peripheral, the peripheral asserting an interrupt request that is provided to the processor to indicate the completion of the data transfer, whereas the interrupt request is not asserted by the peripheral prior to completion of the transfer.