Patent ID: 8132145

Claim:
A method for supporting design of a printed circuit board including, at least one processor, memory coupled to the at least one processor via a bus, and a plurality of conductive layers including conductive areas to which a constant potential is applied, comprising: specifying the conductive areas for each of the plurality of conductive layers; extracting, using the at least one processor, areas which overlap on the plurality of conductive layers, from the specified conductive areas which include a non-overlapped area on the plurality of conductive layers; specifying an interlayer connection member that electrically connects at least two of the plurality of conductive layers in the extracted areas; specifying signal lines for each of the plurality of conductive layers; specifying a second interlayer connection member configured to electrically connect at least two signal lines among the specified signal lines; and specifying second areas in the extracted areas and within a predetermined distance from the specified second interlayer connection member, as the areas where the interlayer connection member is to exist, wherein the second areas are away from the first interlayer connection member.