Patent ID: 7351611

Claim:
A method of encapsulating an integrated circuit package, the method comprising: attaching an integrated circuit die having a plurality of bonding pads formed thereon to a lead frame having a plurality of leads; electrically connecting at least some of the leads to at least some of the bond pads; encasing the integrated circuit die and at least a portion of the lead frame within a cavity of a mould comprising a mould top portion having a relief and a mould bottom portion, the mould top and bottom portions shaped such that when joined together to encase the integrated circuit die, the mould substantially closes spaces between adjacent leads of the lead frame while allowing the leads to extend out of the cavity, and the relief produces a narrow peripheral moulded flange when filled with a resin that supports the integrated circuit die, wherein the formed peripheral moulded flange includes a narrow flat surface which supports the integrated circuit die along the peripheral edge of the integrated circuit die and wherein the peripheral moulded flange includes an opening that is surrounded by the peripheral moulded flange and wherein the opening does not provide support to some portion of the integrated circuit die; introducing the resin into the cavity to encapsulate the integrated circuit die; clamping down the lead frame; and separating the encapsulated integrated circuit die from the lead frame by severing the leads with a punch that is cleared from cutting into a moulded flange by a guide so that the entire punching action is used to sever the lead only and avoids stressing the edges of the integrated circuit die.