Patent ID: 8626807

Claim:
A method for converting a signed fixed point number into a floating point number in a floating-point unit of a processor, the floating-point unit comprising a preparation circuit, a normalizer, and a rounder, the method comprising: reading, by the preparation circuit, an input number that is a signed fixed point number to be converted into a floating point number, wherein the signed fixed point number is an estimate of a logarithm of an input floating point number; determining, by the preparation circuit, whether the input number is less than zero; setting, by the preparation circuit, a sign bit based upon whether the input number is less than zero or greater than or equal to zero; computing, by the preparation circuit, a first intermediate result by exclusive-ORing the input number with the sign bit; computing, by the preparation circuit, a number of leading zeros of the first intermediate result; padding, by the normalizer, the first intermediate result on a least significant bit side with ones or zeros based upon the sign bit; computing, by the normalizer, a second intermediate result by shifting the padded first intermediate result to the left by a number based on the number of leading zeros, wherein the computing of the second intermediate result based on the first intermediate result, the sign bit, and the number of leading zeros is performed within a normalization step of a floating-point fused multiply-add computation, wherein the normalization step is configured to perform a desired function by setting the normalization step to a default normalization function as used in a computation of a fused multiply-add instruction; computing, by the rounder, an exponent portion using the number of leading zeros; computing, by the rounder, a fraction portion using the second intermediate result; conditionally incrementing, by the rounder, the fraction portion based on the sign bit; correcting, by the rounder, the exponent portion and the fraction portion if the incremented fraction portion overflows; and returning the floating point number including the sign bit, and the exponent portion and fraction portion, wherein a computation of the floating point number based on the sign bit, the second intermediate result and the number of leading zeros is performed within a rounding step of the floating-point fused multiply-add computation, wherein the rounding step is configured to perform a desired function by setting the rounder to a default rounding function as used in the computation of a fused multiply-add instruction and applying an appropriate rounding mode, wherein the rounding mode is set based on the input number, and further wherein the setting of the sign bit, the exclusive-ORing of the input number, and the computing of the number of leading zeros are performed as part of a table lookup for the estimate of a logarithm of an input floating point number.