Patent ID: 7724008

Claim:
A method of providing electrical access to one or more pads of one or more integrated circuits on a wafer, comprising: providing an edge-extended wafer translator having a wafer-side and an inquiry-side, a first plurality of contact terminals disposed on a first portion of the wafer-side, a second plurality of contact terminals disposed on a second portion of the wafer-side, a third plurality of contact terminals disposed on a first portion of the inquiry-side, and a fourth plurality of contact terminals disposed on a second portion the inquiry-side; aligning the wafer and the edge-extended wafer translator to each other; and removably attaching the aligned wafer and edge-extended wafer translator such that the first plurality of contact terminals are in electrical contact with the one or more pads of the one or more integrated circuits; wherein the second portion of the wafer-side is an area outside the region where the wafer is removably attached to the edge-extended wafer translator, and wherein the first plurality of contact terminals and the second plurality of contact terminals have different contact areas and different spacing therebetween; wherein removably attaching the wafer to the wafer-side of the edge-extended wafer translator comprises creating a pressure differential between a volume defined by the space between the wafer and edge-extended wafer translator, and the atmosphere outside the defined volume.