Patent ID: 8904327

Claim:
A wiring method executable by a device, wherein the method assists in designing a logic circuit having a plurality of levels and able to minimize a sum total of wire lengths, the method comprising: placing, by a computer, cells of all levels of the logic circuit in placement areas within a grid, wherein the placement areas comprise blocks of the grid; placing, by the computer, a port at a first of the levels that enables a connection to an already placed cell in another of the levels, wherein the port is placed in a boundary portion between one of the placement areas of the grid having the already placed cell, and another one of the placement areas of the grid enabling new cells to be placed; wiring, by the computer, cells in a same one of the levels between cells; and wiring, by the computer, cells in the first of the levels to the already placed cell in the another level between the cells in the first level and the port.