Patent ID: 7010766

Claim:
A parallel design process for integrated circuits, comprising: a) while designing an integrated circuit, laying out plural circuit features to be evaluated; b) fabricating and packaging a plurality of the integrated circuits; c) for a first of the packaged integrated circuits, i) identifying a circuit feature that is interior to the packaged integrated circuit, wherein the interior circuit feature is coupled to at least one of the plural circuit features to be evaluated; ii) identifying a trimming point on the interior circuit feature using an x-ray inspection system; iii) relating coordinates of the trimming point to coordinates of a visible reference marker; iv) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and v) utilizing the cutting tool to make one or more cuts into the first of the packaged integrated circuits, until the interior circuit feature has been acceptably modified at the trimming point; and d) comparing operation of the first of the packaged integrated circuits to operation of a second of the packaged integrated circuits.