Patent ID: 7336735

Claim:
Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction, and are transmitted via a transmission channel, having: (a) a branch metric calculation circuit for calculation of branch metrics for the received sequence of coded data symbols; (b) a path metric calculation circuit for calculation of path metrics and decision values as a function of the branch metrics and the coding instruction, with the calculated path metrics in each case being compared with an adjustable decision threshold value in order to produce an associated logic validity value, in which case the decision threshold value for the path metric normalization can be set such that it is variable; (c) a selection circuit which temporarily stores only those path metrics whose validity value is logic high in a memory, and selects from the temporarily stored path metrics that path with the optimum path metric, with an increasing number of decision values being stored in the selection circuit as the signal-to-noise ratio of the transmission channel decreases; (d) wherein two or more logic validity values which are produced by the path metric calculation circuit are logically OR-linked by a logic circuit, and all the associated decision values are temporarily stored in the memory of the selection circuit when the result of the logical OR linking is logic high.