Patent ID: 8370607

Claim:
A system for recovering an architecture register mapping table (ARMT), comprising: a first number of collection circuits, wherein the ARMT includes a second number of architecture table fields each configured to enable mapping a physical register to its associated architecture register, wherein a physical register mapping table (PRMT) includes a third number of paired physical table fields and valid mapping fields, wherein each physical table field is configured to enable mapping one of the architecture registers to its associated physical register if the associated valid mapping field value permits such mapping, and wherein each paired physical table field and valid mapping field is coupled to one and only one collection circuit during only one of a fourth number of instruction cycles; a first number of decode circuits each having its input coupled to the output of one different collection circuit and capable of converting its input into a third number bit wide binary string selection code at its output, wherein each selection code specifies whether or not and to which architecture table field one of the physical table fields is to be mapped; a second number of selection circuits, wherein each of the selection circuits is configured to receive from each selection code a bit from the bit position associated with that selection circuit; and an enable circuit configured to choose the appropriate architecture table fields to recover, wherein the output of each selection circuit is coupled to one different architecture table field and is written into that architecture table field when permitted by the enable circuit.