Patent ID: 8138798

Claim:
A circuit comprising: a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output, the first mixer cell, when operating, producing a first delay between the first mixer cell input and the first mixer cell output and a second delay between the second mixer cell input and the first mixer cell output, there being a first difference between the first delay and the second delay; a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output, the second mixer cell, when operating, producing a third delay between the third mixer cell input and the second mixer cell output, and a fourth delay between the fourth mixer cell input and the second mixer cell output, there being a second difference between the third delay and the fourth delay; and a current mirror configured to mirror a current of a first-mixer-cell output signal and a current of a second-mixer-cell output signal; wherein: the first circuit input is connected to the first mixer cell input and the third mixer cell input; the second circuit input is connected to the second mixer cell input and the fourth mixer cell input; the first mixer cell output and the second mixer cell output are combined with each other to provide the circuit output by adding the mirrored current of the first-mixer-cell output signal and the mirrored current of the second-mixer-cell output signal to produce the circuit output signal; and when present, a current of the circuit output signal is proportional to a phase offset between the first phase and the second phase.