Patent ID: 8416013

Claim:
An integrated circuit configured for core circuit leakage control, the integrated circuit comprising: a core circuit configured to operate in a standby mode, the core circuit comprising a power terminal and a ground terminal; a first switch and a second switch, the first switch coupled between the power terminal and a power supply, the second switch coupled between the ground terminal and a ground supply, the first switch and the second switch configured to power ON and power OFF the core circuit to thereby control leakage associated with the core circuit; a first feedback circuit coupled with the first switch and the core circuit, configured to control an ON state and an OFF state of the first switch based on voltage at the power terminal during the standby mode to thereby maintain a logic state of the core circuit; and a second feedback circuit coupled with the second switch and the core circuit, configured to control an ON state and an OFF state of the second switch based on voltage at the ground terminal of the core circuit during the standby mode to thereby maintain the logic state of the core circuit; wherein the first feedback circuit comprises: a first trigger circuit configured to generate a trigger signal for controlling the ON state and the OFF state of the first switch in response to a control signal and a standby mode signal; a first voltage sense circuit coupled with the power terminal and the first trigger circuit, configured to generate the control signal at an output in response to the voltage at the power terminal, wherein the control signal is asserted when the voltage at the power terminal is less than a first threshold voltage; and a first reset circuit coupled to the output of first voltage sense circuit, configured to reset the control signal upon a threshold delay from a time of assertion of the control signal.