Patent ID: 7877587

Claim:
Apparatus for processing data, said apparatus comprising: a multithreaded processor having a hardware scheduling mechanism for interleaving execution of program instructions from a plurality of program threads; and a branch prediction mechanism having: (i) a plurality of branch history registers each storing a prediction index that is a representation of taken or not taken preceding branch behaviour for a respective program thread of said plurality of program threads; (ii) a global history table shared between said plurality of program threads and having a plurality of storage locations storing predictions of branch behaviour, said plurality of storage locations being indexed in dependence upon a prediction index for a currently active program thread such that different program threads use the same storage locations; and (iii) mapping logic configured to provide different one-to-one mappings for different program threads between storage locations of predictions within said plurality of storage locations and preceding branch behaviour represented by respective prediction indices, wherein the same value of prediction index maps to different preceding branch behavior for each different program thread.