Patent ID: 8448173

Claim:
A method for executing a transaction by a processor apparatus that includes a plurality of hardware threads, the method comprising the steps of: creating a main software thread by the processor apparatus for executing the transaction; creating a helper software thread by the processor apparatus for executing a barrier function; executing the main software thread and the helper software thread by the processor apparatus using the plurality of hardware threads; deciding, by the processor apparatus, whether or not the barrier function is required to be executed when the main software thread encounters a transactional load or store operation that requires the main software thread to read or write data; executing the barrier function by the helper software thread, wherein the step of executing the barrier function includes: stalling the main software thread; activating the helper software thread to execute the barrier function; and exiting the helper software thread in response to the completion of the execution; and returning to the main software thread, thereby executing the transaction by the processor apparatus.