Patent ID: 8225157

Claim:
An addressable test interface comprising: A. substrate; B. a test data input lead having an input and an output on the substrate; C. a test clock lead having an input and an output on the substrate; D. a test mode select lead having an input on the substrate; E. a mode gate on the substrate, the mode gate having one input connected to the test mode select lead, another input, and an output connected to a gated test mode select lead on the substrate; F. a test data output lead having an input on the substrate; G. a tri-state gate on the substrate, the tri-state gate having an input connected to the test data output lead, an enable input, and an output connected to a gated test data output lead on the substrate; and H. a shadow protocol circuit on the substrate, the circuit having inputs connected to the test data lead, the test clock lead, and the test mode select lead, and having a first interface select output, and a second interface select output.