Patent ID: 6951015

Claim:
A computer-implemented method for inserting prefetch instructions in an executable computer program, comprising; generating profile data of executed load instructions and store instructions, including instruction addresses, target addresses, data loaded and stored, and execution counts; identifying from the profile data recurring patterns of instructions resulting in cache-miss conditions, wherein the patterns of instructions include, a first pattern having a target address of an instruction resulting in a cache-miss condition that is equal to a target address of a previous load instruction plus an offset value; a second pattern having a target address of an instruction resulting in a cache-miss condition that is equal to a target address of a previous load instruction minus an offset value; a third pattern having a target address of an instruction resulting in a cache-miss condition that is equal to a target address of a previous store instruction plus an offset value; and a fourth pattern having a target address of an instruction resulting in a cache-miss condition that is equal to a target address of a previous store instruction minus an offset value; and inserting prefetch instructions prior to the instructions that result in cache-miss conditions for patterns of instructions recurring more than a selected frequency.