Patent ID: 8347035

Claim:
A processor comprising: a core area, wherein the core area comprises a plurality of processing cores including a first processing core and a set of processing cores, a plurality of per core caches including a first per core cache and a set of per core caches, and a plurality of line-fill buffers including a first line-fill buffer and a set of line-fill buffers, and an uncore area coupled to the core area, wherein the uncore area comprises an extended buffer space coupled between the first line fill buffer and a last level cache (LLC) coupled to the extended buffer space, wherein the first processing core is to offload a first weakly ordered transaction to write data stored in the first line-fill buffer to a memory coupled to the processor, to the extended buffer space after receiving a request for the data of the first weakly ordered transaction from the uncore area, wherein the request for the data is generated before the first weakly ordered transaction is posted to the memory, and wherein the first processing core is to de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space.