Patent ID: 8174126

Claim:
A stacked multi-chip comprising a base layer comprising a mounting panel being non-conductive and having an outer surface being mounted in an electrical device; and an inner surface; and a redistributed layer being mounted on the inner surface of the mounting panel and having a top surface; a first chip comprising an electrically non-conductive layer having a top surface and a bottom surface and comprising a Through Silicon Via (TSV) channel being a good thermal conductor and having multiple vias formed through the channel with metal as conductors to form a decoupling capacitor that filters harmonic waves and reduces noise; and a connective layer being mounted against the bottom surface of the electrically non-conductive layer and the TSV channel and abutting the redistributed layer; and a first stacked chip being mounted on the first chip and comprising an electrically non-conductive layer having a top surface and a bottom surface and comprising a TSV channel being a good thermal conductor, corresponding and being connected to the TSV channel of the first chip and having multiple vias and metal in the vias as conductors to form a decoupling capacitor that filters harmonic waves and reduces noise; and a connective layer being mounted against the top surface of the electrically non-conductive layer and the TSV channel of the first stacked chip; and at least one second stacked chip being mounted on the first stacked chip and comprising an electrically non-conductive layer having a top surface and a bottom surface and comprising a TSV channel being formed by TSV technology with multiple vias and metal in the vias as conductors to form a decoupling capacitor and being a good thermal conductor; and a connective layer being mounted against the bottom surface of the electrically non-conductive layer and the TSV channel of the second stacked chip and being connected to the connective layer of the first stacked chip.