Patent ID: 7375567

Claim:
A digital storage element, comprising: a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled thereto, said first transistor also coupled to electrical ground; and a slave transparent latch coupled to the master transparent latch, said slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop, said second transistor coupled to electrical ground; wherein, when a clock signal is in a first state, the first single transistor is activated to preset the digital storage element; wherein, when the clock signal is in a second state, the second single transistor is activated to preset the digital storage element; an input circuit located in the master transparent latch and directly coupled to the data input port; a third transistor fixed between the input circuit and a voltage source, wherein one end of the third transistor is coupled to the input circuit and another end of the third transistor is coupled to said voltage source; wherein the first and second transistors are activated by a preset signal having a particular state, and wherein the third transistor is activated by the preset signal having a different state.