Patent ID: 7417897

Claim:
An operation method for reading a single-poly, single-transistor non-volatile memory (NVM) cell unit, the single-poly, single-transistor NVM cell unit comprising a conductive gate disposed on a P well of a substrate, a gate dielectric layer between the conductive gate and the P well, an N type drain region, an N type source region, and an N channel between the N type drain region and the N type source region, the operation method comprising: electrically connecting the P well to a P well voltage V B ; coupling the N type source region with the P well or providing a source voltage V S to the N type source region, wherein the source voltage V S is larger than the P well voltage V B ; electrically connecting the N type drain region to a drain voltage V D that is relatively positive with respect to the P well voltage V B or the source voltage V S ; and electrically connecting the conductive gate to a gate voltage VG that is relatively positive with respect to the P well voltage V B to create strong inversion of the N channel; wherein when the single-poly, single-transistor NVM cell unit is not programmed, the N channel is completely turned on; wherein when the single-poly, single-transistor NVM cell unit is programmed to breakdown the gate dielectric layer, the gate voltage V G will discharge through a leakage path formed in the gate dielectric layer whereby the gate voltage V G and the P well voltage V B will converge, and wherein when the difference between the gate voltage V G and the P well voltage V B is less than one threshold voltage, the N channel will begin to turn off.