Patent ID: 6940762

Claim:
A semiconductor memory device comprising: a memory cell array which has memory cells arranged in a matrix, each memory cell having a first MOS transistor with a stacked gate including a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer with an inter-gate insulating film interposed therebetween; bit lines each of which connects one end of the current path of each of the first MOS transistors in the same column in common electrically; first word lines each of which connects the second semiconductor layers of the first MOS transistors in the same row in common; a column selector which selects any one of the bit lines; a column decoder which controls the column selector; and a first row decoder which selects any one of the first word lines, at least one of the column decoder and the first row decoder including a level shift circuit which includes: a second and a third MOS transistor each of which has one end of its current path connected electrically to a power supply potential; a fourth MOS transistor which has a gate receiving an input signal related to an address signal, one end of its current path connected to the other end of the current path of the second MOS transistor and to the gate of the third MOS transistor, and the other end of its current path connected electrically to the ground potential; a fifth MOS transistor which has a gate receiving the inverted signal of the input signal, one end of its current path connected to the other end of the current path of the third MOS transistor, to the gate of the second MOS transistor and to the bit line or the first word line electrically, and the other end of its current path connected electrically to the ground potential; and a first switch element which controls the supply of the power supply potential to the second and third MOS transistors in response to the input signal.