Patent ID: 7271627

Claim:
An input buffer for buffering an input signal sent to a core circuitry from outside of an integrated circuit, comprising: a signal passing module for generating a first output signal in response to the input signal based on a comparison between the input signal and a first supply voltage thereof; a regulating module having a first input terminal receiving the input signal and a second input terminal receiving the first output signal for generating a second output signal within a voltage range no greater than the first supply voltage; and a level down module for generating a third output signal within a voltage range no greater than a second supply voltage, which is lower than the first supply voltage, for the core circuitry in response to the second output signal, wherein the signal passing module comprises a first NMOS transistor coupled between the second input terminal of the regulating module and the input signal, having its gate connected to the first supply voltage, a first PMOS transistor having its source and drain connected to a drain and source of the first NMOS transistor, respectively, and a control module for generating a control signal to a gate of the first PMOS transistor, the control signal turning on the first PMOS transistor when a voltage level of the input signal is equal to or less than the first supply voltage, while turning off the same when the voltage level of the input signal is greater than the first supply voltage.