Patent ID: 8385117

Claim:
A semiconductor memory device comprising: a word line controlling section configured to, when N (N is a natural number not less than 2) bits of data stored in one memory cell and belonging to different pages, each page being a unit of reading, are decoded by iterative calculation using probability based on 2 N threshold voltage distributions, select a voltage set required to read 1-bit data belonging to a page to be read from among (2 N −1) voltage sets, each set being composed of a reference voltage for hard bit reading and a plurality of intermediate voltages including a voltage lower than the reference voltage and a voltage higher than the reference voltage for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell; a log likelihood ratio table storing section configured to store a log likelihood ratio based on each of the read voltages; and a decoder configured to decode the data read by the read voltages which are applied by the word line controlling section using the log likelihood ratios stored in the log likelihood ratio table storing section and corresponding to the read voltages.