Patent ID: 7808273

Claim:
Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input; said sequential circuitry, arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, to output a data signal from said sequential circuitry at said data output in response to said clock signal; and said sequential circuitry responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal, wherein said sequential circuitry comprises: a retention circuit; and a functional path latch circuit, said retention circuit arranged to receive and retain a data signal from said functional path latch circuit in response to a changing edge of a retention signal, and to output said data signal to said functional path latch circuit in response to a different changing edge of said retention signal, said retention signal being received at said clamp signal input.