Patent ID: 6965248

Claim:
A method for concurrently transmitting a test signal to a plurality of integrated circuit (IC) terminals of ICs during a test of the ICs, wherein a voltage of the test signal repeatedly transitions between first and second test signal voltage levels representing first and second logic levels when a control signal repeatedly transitions between first and second states, wherein at least one fault linking at least one of the plurality of IC terminals to a source of potential has no substantial effect on the first and second logic levels represented by the test signal at others of the IC terminals, the method comprising the steps of: a. driving an output signal between first and second output signal voltage levels when the control signal transitions between the first and second states, b. resistively coupling the output signal to a circuit node to produce the test signal at the circuit node, c. concurrently distributing the test signal from the circuit node to the plurality of IC terminals though paths resistively isolating the IC terminals from one another, and d. adjusting the first and second output signal voltage levels such that the test signal transitions between the first and second test signal voltage levels when the control signal transitions between said first and second states.