Patent ID: 8379454

Claim:
A method of operating a non-volatile memory circuit having an array including a plurality of erase blocks each including a plurality of memory cells formed along word-lines, comprising: determining whether a word-line is defective by a process including: performing first write operation on a first plurality of memory cells along a first word-line from a first erase block, the first write operation including a series of alternating programming pulses and verify operations, the first plurality of memory cells along the first word-line individually locking out from further programming pulses as verified; determining the number of programming pulses in the first write operation for the memory cells of the first plurality of memory cells along the first word-line to verify as written; subsequently performing a second write operation on a first plurality of memory cells along a second word-line from the first erase block, the second write operation including a series of alternating programming pulses and verify operations, the first plurality of memory cells along the second word-line individually locking out from further programming pulses as verified; determining the number of programming pulses in the second write operation for the memory cells of the first plurality of memory cells along the second word-line to verify as written; determining whether the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeds a threshold value; and in response to the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeding the threshold, determining that the second word-line is defective.