Patent ID: 7586936

Claim:
An Ethernet adapter providing direct data and control paths between using partitions and the adapter, the adapter comprising: an architecture for allowing the adapter to receive and transmit packets from and to a processor; the architecture including: a demultiplexing mechanism to allow for partitioning of the processor and a plurality of layers including: a media access controller and serialization / deserialization (MAC and Serdes) layer having same chip input/outputs (I/Os) providing a plurality of interfaces from and to one or more devices on a network; a packet acceleration and virtualization layer, for receiving packets from and providing packets to the MAC and Serdes layer, including demultiplexing packets for enabling virtualization or partitioning an operating system (OS) in relation to the packets, and for providing packet header separation by separating as appropriate the packet header from a data payload by removing the header from the body of the packet and directing the header to a protocol stack for processing without polluting received buffers thereby reducing into a latency period for certain transactions; and, a host interface layer providing for context management, for communicating with the packet accelerator and virtualization layer and for interfacing and directly interacting with a private bus of the processor; wherein one logical switch is utilized for each physical port of the adapter and wherein each logical port has a separate port on a logic switch, wherein one logical switch provides a plurality of logical ports wherein each of the plurality of logical ports supports a partition of the processor, and wherein partition to partition communication is enabled.