Patent ID: 8751850

Claim:
An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a resistor network, configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group; a composite delay element, configured to equalize delay paths within a receiving device, wherein said delay paths correspond to a data strobe signal that is received from a transmitting device, wherein said receiving device is coupled to a motherboard, and wherein said resistor network is coupled to said motherboard, and wherein said ratio signal enters said receiving device through an external pin; and delay-locked loops (DLLs), coupled to said ratio signal and disposed within said receiving device, configured to generate delayed data bit signals, wherein said DLLs add said amount of delay to said data bit signals to generate said delayed data bit signals, and wherein said data bit signals are delayed in phase by said amount, and wherein said amount ranges from no phase delay up to an advance of one half cycle of said data strobe signal, and wherein said delayed data bit signals and said data strobe signals are provided to synchronous receivers that are configured to detect states of said delayed data bit signals, and wherein said composite delay element comprises a plurality of delay elements, each of which is associated with a corresponding one of said synchronous receivers, wherein said each introduces a delay into a corresponding propagation path such that said corresponding propagation path is equal to a longest propagation path.