Patent ID: 8019971

Claim:
A VLIW (Very Long Instruction Word) processor that decodes and executes an instruction that has at least two operation fields, of which a first operation field only includes one operation code without any operand codes and a second operation field includes a combination of one operation code and at least one operand code, the VLIW processor comprising: first decoding unit configured to decode the operation code in the first operation field; first execution unit configured to execute an operation indicated by the operation code in the first operation field in accordance with a decoding result of the first decoding unit; second decoding unit configured to decode the operation code in the second operation field; and second execution unit configured to execute an operation indicated by the operation code in the second operation field on data which is indicated by the at least one operand code in the second operation field, in accordance with a decoding result of the second decoding unit.