Patent ID: 7130955

Claim:
A microprocessor comprising: a processor core including an instruction executing unit configured to execute instructions for input and output controlling and processing for data and a cache memory configured to store the data; a memory management unit coupled to the processor core, the memory management unit configured to manage memory system including the cache memory, the memory management unit comprising a pre-routing storing unit configured to store pre-routing information that indicates the connection state of signals of a switching circuit, and an address translation buffer configured to store virtual tag information for translating virtual addresses generated inside the processor into physical addresses, each of the virtual tag information is stored by an entry and corresponds to bus switch control information for controlling a connection relationship of a bus switch; and a bus interface coupled to the processor core and the memory management unit, the bus interface configured to rearrange an order of bits of the data transferred from the processor core, the bus interface comprising a data input/output unit coupled to the processor core and memory management unit, the data input/output unit configured to receive and send the data, the switching circuit coupled to the data input/output unit, the switching circuit configured to receive the data to change the order of the bits of the data according to the pre-routing information, and the bus switch coupled to the switching circuit and configured to receive the data and change the order of the bits per a predetermined number of the bits according to the bus switch control information corresponding to an entry in the address translation buffer.