Patent ID: 6862332

Claim:
A clock reproducing circuit comprising: a master clock signal source for generating a master clock signal pulses having a period equal to 1/N-th times as large as one bit period of normal received data, where N is a positive integer; a first counter for iterating operation of counting said master clock signal pulses from an initial state and returning to said initial state when counting N master signal pulses; edge detecting means for detecting transitions of received data from a first level to a second level and from the second level to the first level, and generating an edge representative signal each time the transition is detected; a second counter for counting said master clock signal, and resetting said first counter when a count in said second counter becomes a number determined based on said number N and a predetermined number equal to or large than two (2) during a time interval during which said predetermined number of edge representative signals occur; and clock generating means for generating a clock signal for said received data, said clock signal assuming a first state when said firm counter counts N/2 of said master clock signal pulses from said initial state and assuming a second state when said first counter counts N of said master clock signal pulses from said initial state.