Patent ID: 7466623

Claim:
A pseudo SRAM comprising: a memory cell array including a plurality of DRAM cells; a burst mode controller which receives external address signals in response to an external clock signal and external control signals, continuously generates burst row address signals and burst column address signals based on the external address signals, and generates a burst operation control signal and a word line control signal in response to the external control signals, a precharge control signal and latency control signals; a read and write controller that generates a driver control signal in response to the word line control signal and the precharge control signal; a row decoder that decodes the burst row address signals; a word line driver that enables one of a plurality of word lines of the memory cell array, which corresponds to a result decoded by the row decoder or disables the plurality word lines of the memory cell array, in response to the driver control signal; and a column decoder that receives the burst column address signals in response to the burst operation control signal and enables bit lines of the memory cell array, which correspond to the burst column address signals.