Patent ID: 8705293

Claim:
A method of operating a non-volatile memory circuit, the memory circuit having a plurality of non-volatile memory cells formed along word lines and bit lines, the bit lines connectable to a corresponding sense amp circuit, where each of the sense amp circuits including a latch connectable to a bus and to intermediate circuitry whereby the corresponding bit line can be connected to the latch, the method comprising: receiving at the latch a first data programming value from the bus; connecting the latch by the intermediate circuitry to the bit line through a first node of the sense amp circuit, thereby biasing the bit line according to the first data programming value; while the bit line is biased according to the first data programming value, isolating the latch from the first node by a first switch connected therebetween; while the bit line is biased according to the first data programming value and subsequent to isolating the latch, receiving at the latch a second data programming value from the bus; and subsequent to receiving the first data programming value and prior connecting the latch to the bit line, transferring the first data programming value through the first node to an internal node of the intermediate circuitry, wherein the internal node is connected to a first plate of a capacitance whose second plate is connected to a second node, and wherein the second node is connectable to the first node through a first transistor whose control gate is connected to the internal node; and while connecting the latch to the bit line: biasing a second transistor whereby the first node is connected to the internal node to be weakly on; raising the voltage level on the second node to a high voltage supply level; and subsequently connecting the second node to the first node through the first transistor.