Patent ID: 8467215

Claim:
A solid state memory device, comprising: at least one first array of wires in a first layer that lies in a first plane; at least one second array of wires extending transverse to the first array of wires in a second layer that lies in a second plane, wherein the first plane is generally parallel to the second plane; and at least one data layer disposed between the first layer and the second layer such that a voltage applied to a first wire in the first array and to a second wire in the second array heats the data layer at a location between the first wire and the second wire and forms a data point comprising a void when data is written to the solid state memory device; wherein the first layer comprises a first substrate and the first wire array supported on the first substrate; wherein the second layer comprises a second substrate and the second wire array supported on the second substrate; and wherein the first substrate is bonded to the second substrate with the data layer disposed between the first substrate and the second substrate.