Patent ID: 8236661

Claim:
A method of forming a self-aligned well implant for a transistor device, the method comprising: forming a patterned gate structure over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers, and the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; and with the patterned gate structure in place, removing, by etching, portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant, and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor device.