Patent ID: 7330061

Claim:
A method of correcting the duty cycle of a digital signal, the method comprising: operating in a calibration mode, by a duty cycle measurement (DCM) circuit, to store in a data store a plurality of voltage values and corresponding duty cycle values, each voltage value being dependent on a respective duty cycle value; operating in a test mode, by the duty cycle measurement (DCM) circuit, to determine the duty cycle of a test clock signal exhibiting an unknown duty cycle, the DCM circuit operating in a test mode including: receiving, by charger circuitry in the DCM circuit, the test clock signal exhibiting an unknown duty cycle; charging, by the charger circuitry, a capacitor in the DCM circuit to a test voltage value that depends on the duty cycle of the test clock signal; accessing, by a control mechanism, the data store to determine a duty cycle which corresponds to the test voltage value, thus defining a measured duty cycle value of the test clock signal; and operating in a correction mode, by a programmable duty cycle clock circuit that generates the test clock signal, to change the duty cycle of the test clock signal from the measured duty cycle value to a predetermined duty cycle value.