Patent ID: 7760572

Claim:
A semiconductor memory device comprising: a command decoder that recognizes a refresh command received from outside the semiconductor memory device and outputs a refresh instruction signal; a refresh number control circuit that controls a number of times that internal refresh signals for refreshing memory cells are output; and a refresh command generating circuit that outputs the internal refresh signals in accordance with the refresh number control circuit, wherein the refresh number control circuit controls the number of times that the internal refresh signals are output so that each of a plurality of banks is refreshed and, after a count value for designating a word line of a refresh address counter has been changed, at least one of the banks is further refreshed, wherein the refresh number control circuit comprises a refresh number counter circuit that measures the number of transitions of an internal signal for generating the internal refresh signals, and wherein the refresh number control circuit comprises a comparison unit that compares the number of the transitions of the internal signal with number-of-times information that has been determined in advance.