Patent ID: 8295090

Claim:
A semiconductor memory device comprising: a plurality of memory cells of a first conductivity type; a plurality of bit lines connected to the plurality of memory cells; a plurality of first bit line select transistors of the first conductivity type which select a bit line from the plurality of bit lines and connect the selected bit line to a sense amplifier; a plurality of second bit line select transistors of the first conductivity type which select an unselected bit line of the plurality of bit lines and supply a potential to the unselected bit line; a first well of the first conductivity type which is formed in a substrate; and a second well of a second conductivity type which is formed in the first well, wherein the plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.