Patent ID: 7153734

Claim:
A method for making a semiconductor device comprising: forming an n-type polysilicon layer, which is bracketed by a pair of sidewall spacers, on a first gate dielectric layer, and a p-type polysilicon layer on a second gate dielectric layer; applying a wet etch process tat is selective for the n-type polysilicon layer over the p-type polysiicon layer to remove the n-type polysilicon layer without removing significant portions of the p-type polysilicon layer, generating a trench that is positioned between the pair of sidewall spacers, and exposing the first gate diclectjic layer; removing the exposed first gate dielectric layer; forming a high-k gate dielectric layer on the substrate at the bottom of the trench; forming an n-type metal layer on the high-k gate dielectric layer to generate a metal NMOS gate electrode; and converting the p-type polysilicon layer to a silicide to generate a silicide PMOS gate electrode.