Patent ID: 7765387

Claim:
A program counter control method for controlling instructions using a branch prediction mechanism and controlling an architecture having a delay instruction that follows a branch instruction, comprising: simultaneously committing a plurality of instructions including the branch instruction and the delay instruction, when a branch prediction is successful and a branch is taken; holding values of a program counter and a next program counter from a time when an instruction is committed until a next instruction is committed; when the delay instruction is annulled by the branch instruction, treating the delay instruction as a non-operation (NOP) instruction during a program counter update cycle, based upon simultaneous updating of the program counter and the next program counter that replaces the delay instruction by the NOP instruction and setting an address of a branch target instruction into the next program counter which is to be actually executed next to the branch instruction, when the plurality of instructions are committed, the program counter update cycle being a time interval from a time when the values of the program counter and the next program counter are updated when the branch instruction is committed until the values of the program counter and the next program counter are updated when the delay instruction is annulled by the branch instruction; setting a signal when annulling the delay instruction; and upon an interrupt of an interrupt process when the signal is set, according to the set signal updating once the program counter and the next program counter and updating again the program counter and the next program counter during the interrupt process.