Patent ID: 7608850

Claim:
A phase change memory device comprising: a semiconductor substrate having a plurality of bar type active regions and an isolation structure between active regions delimiting the active regions; a plurality of gate lines formed on the semiconductor substrate to extend in a direction perpendicular to the active regions; a plurality of source regions formed in the active regions, the source regions being on a first side of each gate line; a plurality of drain regions formed in the active regions, the drain regions being formed on a second side of each gate line, the second side being opposite the first side a dot type lower electrode including a first contact plug formed in the drain region; second contact plugs formed in the source region and the isolation structure in the shape of a line parallel to the gate line; a lower electrode contact formed on the lower electrode; a phase change layer and an upper electrode formed on the lower electrode contact; an upper electrode contact formed on the upper electrode; a plurality of contacts for ground lines, formed between the active regions, wherein each of the plurality of contacts for ground lines come into contact with a top side the second contact plugs, and wherein a bottom side of the same second contact plugs come in contact with the isolation structure between the active regions delimiting the active regions; a bit line formed in each active region to be connected with the upper electrode contact; and a plurality of ground lines formed between the active regions to be connected with the contacts for ground lines.