Patent ID: 7955964

Claim:
A method of forming an integrated circuit structure, the method comprising: providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; performing a first planarization to lower the first top surface of the first filling material, until the top surfaces of the patterned features are exposed; depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features, wherein a height of the first top surface of the first filling material above the patterned features is greater than a height of the second top surface of the second filling material; and performing a second planarization to lower the second top surface of the second filling material, until the top surfaces of the patterned features are exposed.