Patent ID: 7073012

Claim:
A system for interleaving data in a communications device, wherein the data is comprised of a plurality of data blocks, each block having a plurality of symbols, the system comprising: a memory segmented into a plurality of addressable memory blocks, each memory block having a unique address; a write module coupled to the memory, the write module configured to write symbols to the addressable memory blocks; a read module coupled to the memory, the read module configured to read symbols from the addressable memory blocks in an interleaved fashion; means for determining an interleaving sequence for transmitting symbols of a stored data block wherein the interleaving sequence includes a sequence of memory addresses; and means for sequentially communicating each memory address in the interleaving sequence to the read module first and then to the write module; wherein said read module is further configured to receive the memory address and to read the symbol stored in the memory address; and wherein said write module is further configured to receive the memory address and to write a symbol from a next block of data to the memory address.