Patent ID: 7379363

Claim:
A method of operating an integrated circuit array of memory cells receiving a gate voltage from at least a first word line and a second word line to read 1) copied data stored at least as a first copy on memory cells coupled to the first word line and as a second copy on memory cells coupled to the second word line, 2) other data stored on memory cells coupled to the first word line, and 3) other data stored on memory cells coupled to the second word line, comprising: in response to a Serial Peripheral Interface-compliant command to read data: reading the other data stored on memory cells coupled to the first word line; prior to a voltage of the second word line reaching a precharged state, reading the first copy of the copied data from memory cells coupled to the first word line, wherein the second copy of the copied data is stored on memory cells coupled to the second word line; and after the voltage of the second word line reaches the precharged state, reading the other data stored on memory cells coupled to the second word line.