Patent ID: 7633113

Claim:
A semiconductor device comprising: a semiconductor substrate; a device isolation separating active region of the semiconductor substrate, wherein at least a portion of the device isolation is provided in the semiconductor substrate; and a memory cell including a memory cell transistor and a select transistor provided on the active region, wherein the memory cell transistor comprises a channel region separated by a slit and constituted of a flat active region surface alone, wherein the slit is provided so as to include at least end portion of the active region to reduce a width of the active region to a width less than a distance between the device isolations, a charge storage layer provided on a gate dielectric on the channel region, and a first gate electrode provided on an inter-electrode dielectric so as to cover the charge storage layer, and wherein the select transistor comprises a second gate electrode provided on the gate dielectric on the active region and electrically connected to a wiring.