Patent ID: 7176864

Claim:
A display memory for storing pixel data to be supplied to pixels of a display, comprising: at least one pair of bit lines; at least one column of memory cells each having a first storage node and a second storage node able to hold states of a complementary first level and second level; a first read circuit for reading the stored data of said first storage node output to one bit line of said pair of bit lines; a second read circuit for reading the stored data of said second storage node output to the other bit line of said pair of bit lines; a write circuit for outputting the data of said first level and second level to said first and second storage nodes of said memory cells to each the pair of bit lines and writing the data into said memory cells; a controlling means for controlling the operation of said display memory; a write port including at least one said write circuit; a first read port including at least one said first read circuit; and a second read port including at least one said second read circuit, wherein, said first read port supplies the data stored in said memory cell to said display, said second read port reads the data from said memory cell and outputs the same to said controlling means, said write port writes the data from said controlling means into said memory cell, said second read circuit inverts and outputs the level of the stored data of said second storage node output to said other bit line, in a first level period of a clock signal of said display memory, said first read port performs a first access for outputting the data read via said first read circuit to said display, and in a second level period of the clock signal of said display memory, said second read port and said write port perform a second access for outputting the data read via said second read circuit to said controlling means and inputting the write data to be written into said memory cell from said controlling means.