Patent ID: 7555577

Claim:
A data transfer control apparatus comprising: a channel controller including an event input receiving each of a plurality of event signals indicative of occurrence of corresponding events, an event priority encoder connected to said event input selecting one of said event signals indicating occurrence of an event, a bus write address input carrying the address of a bus write, a write priority encoder connected to said bus write address input selecting one of a set of memory writes to predetermined memory addresses; and an event queue connected to said event priority encoder and said write priority encoder storing a queue of data transfer requests corresponding to event signals and memory writes to said predetermined memory addresses; and a transfer controller connected to said event queue for controlling data transfers corresponding to data transfer requests recalled from said event queue as selected by said transfer controller number, said transfer controller including an active source register storing data transfer parameters for controlling selection of data source in a data transfer corresponding to said data transfer requests, and an active destination register storing data transfer parameters for controlling selection of data destination in a data transfer corresponding to said data transfer requests.