Patent ID: 8656102

Claim:
A method for preloading, into a hierarchy of memories, bitstreams representing configuration information for a reconfigurable information processing system comprising a plurality of processing units of different types, the configuration describing a possible logical organization of the processing units which is suited to the execution of a given task, the method comprising: determining off-execution tasks that can be executed on a processing unit of a given type subsequently to execution of the task; during execution of the given task, computing, for each of the tasks that can be executed, a priority dependent on information relating to the current execution of the given task; during execution of the given task, sorting the tasks that can be executed in the order of their priorities; and during execution of the given task, preloading, into the hierarchy of memories, bitstreams representing the information of the configurations useful for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest, the method further comprising, for each type of processing unit, constructing a dependency graph (Tile-dependent Configuration Dependency Graph (TCDG)) indicating the tasks that can be executed on the processing unit of the given type subsequently to execution of the given task, wherein the dependency graph (TCDG) is constructed by using, for each task that can be executed on the processing unit of the given type subsequently to the execution of the given task, an algorithm description graph (Configuration Dependency Graph (CDG) or Control-Data Flow Graph (CDFG)).