Patent ID: 8839175

Claim:
A method for defining an integrated circuit, comprising: generating a digital data file that includes both electrical connection information for a number of transistors having gate electrodes formed from a number of linear-shaped gate-level conductive structures and physical topology information for the number of linear-shaped gate-level conductive structures, wherein each of the number of linear-shaped gate-level conductive structures is defined to extend lengthwise in a parallel manner in a first direction; operating a computer to execute a layout generation program, whereby the layout generation program reads the electrical connection information for the number of transistors and physical topology information for the number of linear-shaped gate-level conductive structures from the digital data file and automatically creates one or more layout structures necessary to form each of the number of linear-shaped gate-level conductive structures in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file, and such that the one or more layout structures that form the number of linear-shaped gate-level conductive structures are positioned in accordance with a fixed gate electrode pitch measured in a second direction perpendicular to the first direction; and operating the computer to store the one or more layout structures necessary to form each of the number of linear-shaped gate-level conductive structures in a digital format on a computer readable medium.