Patent ID: 7724568

Claim:
A memory device comprising: a non-volatile electrically alterable memory which is selected from floating gate based non-volatile memory, SONOS based non-volatile memory, MONOS based non-volatile memory, or phase change based non-volatile memory and is susceptible to read disturbance; a control circuit for controlling the operation of the non-volatile memory; a first volatile cache memory, said first volatile cache memory connected to the control circuit and for storing data to be written to or read from said non-volatile memory, as cache for the memory device; a second volatile cache memory, said second volatile cache memory connected to the control circuit and for storing only data read from said non-volatile memory as read cache for the memory device; wherein the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memory.