Patent ID: 7313768

Claim:
A register file comprising: a plurality of input ports each for receiving therethrough a write data and having a priority order specified among said input ports; and a plurality of registers each for storing therein said write data based on a write address, each of said registers including an input port selector and a data storage for storing an output from said input port selector, said input port selector including a combinational circuit including a plurality of first AND gates each corresponding to one of said input ports and a first OR gate for generating a logical sum of outputs from said first AND gates, wherein: each of said first AND gates in one of said input port selector receives a write instruction signal for specifying whether or not write data input through a corresponding one of said input ports is to be stored in a corresponding one of said registers, and generates a logical product of said write data and said write instruction signal and an inverted signal of each of said write instruction signals received through said input ports each having a higher priority order compared to said input port corresponding to said one of said input port selector.