Patent ID: 8576643

Claim:
A semiconductor integrated circuit comprising: a processing unit; a volatile memory; a first bus which is coupled to the processing unit and the volatile memory; a second bus which is different from the first bus; a bus controller which is coupled between the first bus and the second bus; an electrically rewritable nonvolatile memory which is coupled to the first bus and which stores information based on difference of threshold voltages; and wherein the electrically rewritable nonvolatile memory has a first electrically rewritable nonvolatile memory area and a second electrically rewritable nonvolatile memory area, wherein the first electrically rewritable nonvolatile memory area is used to store a program that the processing unit executes and the second electrically rewritable nonvolatile memory area is used to store data used when the processing unit executes the program, wherein a maximum variation width of a memory threshold voltage of the first electrically rewritable nonvolatile memory area is larger than a maximum variation width of a memory threshold voltage of the second electrically rewritable nonvolatile memory area between an erase determination level and a write determination level, and wherein the first electrically rewritable nonvolatile memory area and the second electrically rewritable nonvolatile memory area each include a number of nonvolatile memory cells, each of the nonvolatile memory cells having: a memory transistor of which threshold voltage is differentiated based on a charge retention state of a charge storage area and a select transistor which selectively connects the memory transistor to a bit line, wherein a gate insulating film of the select transistor is formed thinner than a gate insulating film of the memory transistor, and wherein hot electrons formed based on a potential difference between a channel formed in a semiconductor area immediately below a gate electrode of the select transistor and a channel formed in a semiconductor area immediately below a charge storage area of the memory transistor are injected in the charge storage area to set a threshold voltage higher to reduce electrons held in the charge storage area to initialize a threshold voltage in a lower direction.