Patent ID: 7799619

Claim:
A fabricating method of a thin film transistor (TFT) array substrate, the fabricating method comprising: providing a substrate; forming a plurality of first transparent conductive patterns and a plurality of second transparent conductive patterns on the substrate; forming a plurality of scan lines, a plurality of gates and a plurality of connecting patterns, wherein one of the scan lines electrically connects one of the gates, each of the gates is disposed on one of the first transparent conductive patterns and each of the connecting patterns is electrically connected to two adjacent second transparent conductive patterns; forming a gate insulation layer on the plurality of scan lines, the plurality of gates and the connecting patterns; forming a plurality of channel layers each above each of the gates and a plurality of semiconductor patterns each above each of the second transparent conductive patterns; forming a plurality of data lines on the gate insulation layer and a plurality of sources and drains on the channel layers; forming a dielectric layer on plurality of data lines and the plurality of sources and drains, wherein the dielectric layer has a plurality of contact openings for respectively exposing the drains; and forming a plurality of pixel electrodes on the dielectric layer, wherein each pixel electrode is electrically connected to the corresponding drain via the corresponding contact opening.