Patent ID: 8725929

Claim:
An apparatus, comprising: multi-level memory cells including (i) pilot cells having predetermined data and (ii) multi-level data memory cells to store user data, the multi-level memory cells having M-levels, where M is an integer greater than 1; and an estimation block configured to compute, for each of M level distributions of the multi-level memory cells, (i) estimated mean and (ii) estimated variance, based at least in part on signal samples associated with the predetermined data of the pilot cells, wherein each of the M level distributions is associated with a corresponding level of the M-levels, and wherein the estimation block is configured to refrain from using signal samples associated with the user data of the multi-level data memory cells to compute (i) the estimated mean and (ii) the estimated variance; wherein the estimation block is further configured to recompute, for each of the M level distributions of the multi-level memory cells, (i) the estimated mean and (ii) the estimated variance, based at least in part on the signal samples associated with the user data of the multi-level data memory cells, and wherein the estimation block is configured to refrain from using the signal samples associated with the predetermined data of the pilot cells to recompute (i) the estimated mean and (ii) the estimated variance.