Patent ID: 7049651

Claim:
Charge-trapping memory device comprising: a semiconductor body or substrate with at least one memory cell arranged in said semiconductor body or substrate; source and drain regions formed by doped regions in said semiconductor body or substrate and limited by junctions; a gate dielectric on a surface of said semiconductor body or substrate between said source and drain regions and having a layer thickness; a gate electrode on said gate dielectric; and a charge-trapping layer formed within said gate dielectric, the charge-trapping layer comprising two strips which are each located between an upper boundary of said junctions and said gate-electrode and which are enclosed by said gate dielectric, said strips being formed of a material with higher relative permittivity than the gate dielectric, and said strips having a layer thickness which is provided relative to said layer thickness of said gate dielectric in an area between said strips and a total layer thickness of said gate dielectric in an area of said strips in such a manner that a positive voltage applied to said gate electrode and provided for inducing a Fowler-Nordheim-tunnelling of electrons into said charge-trapping layer generates an electric field strength in said area of said strips, which is larger or equal to an electric field strength in said area between said strips during a process of erasure of said memory cell.