Patent ID: 8908435

Claim:
A 3 D stacked non-volatile memory device, comprising: a substrate; a stacked non-volatile memory cell array carried by the substrate, the stacked non- volatile memory cell array comprising a memory string, the memory string comprising a plurality of memory cells between a first select transistor at a first end of the memory string and a second select transistor at a second end of the memory string, the first end of the memory string connected to a first control line, and the second end of the memory string connected to a second control line; and a control circuit in communication with the stacked non-volatile memory cell array, the first control line and the second control line, the control circuit, to perform each erase iteration of a plurality of erase iterations of an erase operation for one or more memory cells of the memory string, is configured to perform: a preparation phase in which a voltage of the first control line and a voltage of the first select transistor are driven higher, such that the voltage of the first control line does not exceed the voltage of the first select transistor by a sufficient margin to charge up a channel of the memory string by gate-induced drain leakage at the first select transistor, a charge up phase in which a voltage of a control gate of each of the one or more memory cells floats, and the voltage of the first control line is driven higher to a level which exceeds the voltage of the first select transistor by the sufficient margin to charge up the channel of the memory string by gate-induced drain leakage at the first select transistor, wherein the voltage to which the first control line is driven in the charge up phase increases in an erase iteration of the plurality of erase iterations according to a first respective step size, and the voltage to which the first select transistor is driven in the preparation phase increases in the erase iteration of the plurality of erase iterations according to a second respective step size, and an erase phase in which the voltage of the control gate of each of the one or more memory cells is driven lower.