Patent ID: 7404032

Claim:
A memory subsystem, comprising: a first memory module including, a first integrated circuit having memory including a first storage cell and a second storage cell, a first buffer device coupled to the first integrated circuit; a second memory module including, a second integrated circuit having memory including a third storage cell and a fourth storage cell, a second buffer device coupled to the second integrated circuit; an interconnect including a first signal line and a second signal line; and a first switch element coupling the second signal line to the first memory module, the first switch element having an input to receive a control signal, wherein the first switch element determines which of the first and second buffer devices is accessed via the second signal line based on the control signal, wherein the memory subsystem is operable in a first mode of operation and a second mode of operation, wherein: during the first mode of operation, the first storage cell is accessible from the first signal line through the first buffer device and the second storage cell is accessible from the second signal line through the first switch element and the first buffer device, and during the second mode of operation, the first storage cell is accessible from the first signal line through the first buffer device and the third storage cell is accessible from the second signal line through the first switch element and the second buffer device.