Patent ID: 8273618

Claim:
A method for forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device, the method comprising: forming a first layer of high-K metallic oxide on a semiconductor substrate, the first layer having a barrier layer sandwiched between portions of the high-K metallic oxide of the first layer; forming at least one composite layer directly on said first layer, said composite layer including a second layer of high-K metallic oxide formed directly on a dipole induction layer, the dipole induction layer comprising a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than said first and second layers; and forming a metallic gate electrode on said at least one composite layer; wherein formation of said layers is such as to position the dipole induction layer of said at least one composite layer between the gate electrode and substrate to shift said threshold voltage to a desired level.