Patent ID: 7167887

Claim:
Circuitry for performing a square root or division operation, said circuitry comprising: a plurality of sets of iteration circuitry, at least a current one of the sets of iteration circuitry being connected to the output of a previous one of said sets of iteration circuitry, the current one of said sets of iteration circuitry comprising: a quotient selection logic part which is arranged to make a decision as to what is to be done by the current one of the sets of iteration circuitry to a remainder of a previous one of the sets of iteration circuitry, a determination part arranged to receive an output from the quotient selection logic part and based on the received output to determine a value to be added by the current one of the sets of iteration circuitry to said remainder of the previous ones of the sets of iteration circuitry, a carry save adder part which adds the determined value to said remainder, and a remainder part that is arranged to perform similar functions to the determination part and said carry save adder part.