Patent ID: 7979218

Claim:
A test apparatus configured to test a device under test, the test apparatus comprising: a pattern generating section that inputs a test pattern to the device under test; a judging section that judges whether the device under test is defective or not, based on an output signal outputted from the device under test; a power supply apparatus that supplies a source power to the device under test; a setting section that detects a fluctuation amount of the source voltage resulting when the test pattern is inputted to the device under test, and sets, based on the detected fluctuation amount, a current range within which a compensation current that is in accordance with a fluctuation of a consumption current consumed by the device under test can be generated so as to compensate a fluctuation of a source voltage to be applied to the device under test attributable to the fluctuation of the consumption current, the current range having a predetermined number of levels that the compensation current can take; and a load fluctuation compensation circuit that, so as to compensate a fluctuation of a source voltage to be applied to the device under test attributable to a fluctuation of a consumption current consumed by the device under test, generates a compensation current that is in accordance with the fluctuation of the consumption current within the set current range and at a predetermined number of levels, wherein the load fluctuation compensation circuit includes: a first delay circuitry section that delays a supplied clock signal by a delay amount fluctuated by a predetermined first fluctuation amount with respect to a unit fluctuation amount of a source voltage supplied to the device under test; a second delay circuitry section that delays a supplied clock signal by a delay amount fluctuated by a second fluctuation amount that is larger than the first fluctuation amount, with respect to the unit fluctuation amount of the source voltage supplied to the device under test, the second delay circuitry section being provided to be parallel with the first delay circuitry section; a load circuit provided to be parallel with the device under test and sharing at least part of power supply wiring with the device under test; and a phase detecting section that detects a phase difference between the clock signal outputted from the first delay circuitry section and the clock signal outputted from the second delay circuitry section, and adjusts a consumption current amount consumed by the load circuit, within the current range set by the setting section and at the number of levels based on the phase difference.