Patent ID: 7764550

Claim:
A memory system, comprising: a plurality of non-volatile memory cells, each memory cell of the plurality is programmable and erasable; program circuitry for programming memory cells of the plurality of non-volatile memory cells, the program circuitry programs memory cells of the plurality to above a first program threshold voltage in response to a first mode and to above a second program threshold voltage in response to a second mode, wherein the first program threshold voltage is different than the second program threshold voltage; erase circuitry for erasing cells of the plurality of non-volatile memory cells; a count circuit, the count circuit including an erase count value; and count increment circuitry for incrementing the erase count value in response to an erase operation of the plurality of memory cells when in the first mode, wherein the first mode transitions to the second mode in response to the erase count value reaching a specific value.