Patent ID: 7729182

Claim:
A method for issuing write data and address signals to a memory array, the method comprising: storing received address signals in respective selected address registers selected from a plurality of address registers in accordance with the system clock signal; routing write data signals and a write clock signal through a local clock tree; storing the write data signals responsive, at least in part, to the write clock signal from the local clock tree; delaying the system clock signal an amount such that the delayed system clock signal will be synchronized with the write clock signal after routing through a global clock tree; retrieving an address signal from a selected address register from the plurality of address registers in accordance with the delayed system clock signal; capturing the write data signals from the stored write data signals responsive to the delayed system clock signal; generating an enable signal based, at least in part, on the delayed system clock signal and synchronized with the address signals retrieved from the selected address register; routing the enable signal and the address signal retrieved from the selected address register through the global clock tree and the local clock tree; issuing the data signal responsive, at least in part, to the enable signal; and issuing the address signal from the local clock tree.