Patent ID: 6969645

Claim:
A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells including a select transistor with a select gate and including a memory transistor with a floating gate and a control gate, the method comprising: forming active semiconductor regions in a semiconductor body, the active semiconductor regions bordering on a surface of the semiconductor body, and the active semiconductor regions being mutually insulated by field oxide; providing a layer of gate oxide on the surface of the semiconductor body and a first layer of conductive material on the layer of gate oxide and the semiconductor body, wherein: the first layer of conductive material being etched to form the select gate on the layer of gate oxide, the select gate being provided with side walls of insulating material wherein the side walls of insulating material extending transversely to the surface of the semiconductor body, the gate oxide next to the select gates being removed and substituted with a layer of tunnel oxide, the first layer of conductive material further forming the first conductive strips serving as selective lines extending transversely to the active semiconductor regions, the first conductive strips deposited over the layer of gate oxide, the first conductive strips spanning a width between the side walls of insulating material, the first conductive strips forming select gates of the select transistors; thereafter, depositing a second layer of conductive material over the select gates and the semiconductor body characterized in that the second layer of conductive material is deposited in a thickness that exceeds thickness of the select gates; thereafter, planarizing the second layer of conductive material; after planarizing the second layer of conductive material, etching grooves in the second layer of conductive material, the grooves extending transversely to the select lines and exposing the field oxide and the select lines having the side walls of insulating material; thereafter, depositing a layer of an intermediate dielectric over the second layer of conductive material and in the grooves; depositing a third layer of conductive material over the layer of intermediate dielectric and in the grooves wherein the grooves being filled with the layer of interlayer dielectric and the third layer of conductive material; forming the control gate in the third layer of conductive material, wherein the control gate extending above and next to the select gate, the third layer of conductive material further forming second conductive strips serving as word lines in the third layer of conductive material wherein the word lines parallel to the select lines and at least partly overlapping the select lines, the second conductive strips forming the control gates of the memory transistors at location of the floating gates; etching the floating gate in the second layer of conductive material by using the control gate as a mask.