Patent ID: 7609556

Claim:
A non-volatile memory, comprising: an array of memory cells to be programmed relative to a demarcation threshold voltage; a programming circuit for applying a programming pulse to the group of memory cells; a sensing circuit with a first configuration to verify the cells of the group relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage; a memory controller alternately controlling applying a programming pulse and verifying the programmed result for the group of memory cells in parallel; said verifying further comprises: a first verifying relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage; reducing the rate of subsequent programming of the cell that has been verified relative to the first reference threshold voltage; a second verifying relative to the demarcation threshold voltage; and inhibiting the memory cell that has been verified relative to the demarcation threshold voltage from further programming; and wherein: said second verifying is skipped until at least one of the memory cells of the group has been verified relative to the first threshold voltage.