Patent ID: 6898740

Claim:
A computer system, comprising: a host bus; an input/output (I/O) fault-tolerant interconnect system; and a core logic chipset comprising a bridge interface configurable to implement either one of an accelerated graphics bus bridge and a peripheral component interconnect bridge, wherein the configurable bridge interface is connectable between the host bus and the I/O fault-tolerant interconnect system, the I/O fault-tolerant interconnect system comprising: an I/O bus selectively comprising one of a first type bus and a second type bus, the I/O bus comprising a first bus portion and a second bus portion, wherein the first type bus comprises an accelerated graphics port bus, and the second type bus comprises a peripheral component interconnect bus; and a device interface connectable to the I/O bus, wherein the device interface is configured to detect errors in a transaction received by the device interface, wherein, if a first error is detected on the first bus portion, then the transaction is performed over the second bus portion; and if a second error is detected on the second bus portion, then the transaction is performed over the first bus portion.