Patent ID: 7923315

Claim:
A method for fabricating a planar independent-double-gate FET on a bulk semiconductor substrate, the method comprising: a) providing a substrate with an active semiconductor region laterally defined by an isolation region and with a sacrificial layer buried under a semiconductor layer; b) depositing a first gate-dielectric layer and a first gate layer, and depositing a hard mask layer on the first gate layer; c) laterally trimming the first gate-dielectric layer and the first gate layer in a stripe shape so as to cause them to extend, in a channel direction pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region but also on portions of the isolation region; d) fabricating source and drain regions; e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to cause the recess to undercut portions of the first gate stack in the channel direction; f) selectively removing the buried sacrificial layer with the etching agent, thus forming a tunnel with semiconductor tunnel walls in place of the buried sacrificial layer; g) depositing a second dielectric layer and a second gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate-stack; h) laterally trimming the gate stack so as to separate top and bottom gate layers.