Patent ID: 7808288

Claim:
A circuit for an automatic coarse tuning in a phase locked loop (PLL) by observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range, said circuit comprising: a bandgap module operatively coupled to said circuit for generating one or more signals; a loop filter connected between the bandgap module and a first intermediate node for providing the control voltage; a coarse loop module operatively coupled to the bandgap module and a second intermediate node for providing a coarse loop signal to said circuit for switching on a coarse loop tuning, said coarse loop module receiving the one or more signals from the bandgap module and receiving the control voltage from the first intermediate node; a phase frequency detector connected to a first node and a second node for comparing phases of a first input signal and a second input signal, said phase frequency detector receiving said coarse loop signal; a charge pump operatively coupled to the phase frequency detector for providing the control voltage at the first intermediate node, said charge pump receiving the coarse loop signal; a frequency detector connected to the first node, a third node and a fourth node for generating one of an up signal and a down signal, said frequency detector receiving the coarse loop signal; an up counter connected to the frequency detector for incrementing a count number, said up counter receiving the coarse loop signal; a down counter connected to the frequency detector for decrementing a count number, said down counter receiving the coarse loop signal; a voltage controlled oscillator (VCO) module operatively coupled to the up counter, the down counter, the charge pump, the loop filter, and said coarse loop module for generating an output signal at a third intermediate node for ensuring that variations in the output signal and a gain of said VCO being within said specified range; and a divider connected between the third node, the fourth node and the third intermediate node for dividing said output signal, said divider being coupled to the second node for providing the second input signal.