Patent ID: 7797591

Claim:
A design support software system configured to support a test circuit design of a semiconductor integrated circuit comprising a memory circuit having memory cells and a redundant cell for avoiding a faulty cell among the memory cells, in which fault has occurred, to achieve repair; a fuse circuit in which a logic for repairing said memory circuit is determined based on a repair code for avoiding said faulty cell detected as a result of testing said memory circuit and for using the redundant cell; a first register which is controlled by output signals from said fuse circuit; a second register having a scan design and having a test input and test output; a register selection circuit having an input to which an output of said first register and an output of said second register are connected, and performing switching between output signals of said first register and output signals of said second register to output signals; a first switching circuit which is connected between a first user circuit and inputs of said memory circuit, and switches the inputs of said memory circuit from a first signal path including a path to which said faulty cell is connected to a second signal path including a path to which said redundant cell is connect for avoiding the path to which said faulty cell is connected; a second switching circuit which is connected between a second user circuit and outputs of said memory circuit, and switches the output of said memory circuit from said first signal path to said second signal path; a memory bypass circuit which is located between said first switching circuit and said second switching circuit, and connected to the inputs and the outputs of said memory circuit; and a decoding circuit configured to output signals for controlling said first switching circuit and said second switching circuit based on an output from said register selection circuit comprising: a redundancy circuit producing portion configured to produce a redundancy circuit file based on an input from a redundant memory information filed including information on cell names and on address width/bit width repair processes of said memory circuit; and a circuit incorporation porting configured to produce a second net list in which redundancy circuits are incorporated, based on imputer from said redundancy circuit file a first net list of said semiconductor integrated circuit which is subjected to incorporation of said redundancy circuits, a fault test register specifying file for specifying a second register, and a redundant memory instance specifying fir of specifying a logical location of said memory circuit, wherein said register selection circuit is switched to the output signals of said first register when performing testing by way of said memory circuit, and switched to output signals of said second register when performing testing by way of said memory bypass circuit.