Patent ID: 7119587

Claim:
A frequency divider state circuit, comprising: a first flip flop coupled to receive a feedback signal and a clock signal, and configured to produce a first output signal dependent upon the feedback signal and the clock signal; a second flip flop coupled to receive the first output signal, the clock signal, and an error signal indicative of an error state, wherein the second flip flop comprises logic coupled to receive the clock signal and the error signal and configured to produce an internal clock signal dependent upon the clock signal and the error signal, and wherein the second flip flop is configured to produce a second output signal dependent upon the first output signal, the clock signal, and the internal clock signal; a third flip flop coupled to receive the second output signal and the clock signal, and configured to produce a third output signal dependent upon the second output signal and the clock signal; and wherein the frequency divider state circuit is configured to produce an output signal having a frequency that is less than a frequency of the clock signal.