Patent ID: RE38956

Claim:
A test circuit for detecting defective memory cells in a plurality of memory cells in a memory device, the test circuit comprising: a test mode terminal adapted to receive a test mode signal; an error detection circuit including a plurality of inputs and an output, each input coupled to some of the plurality of memory cells, the error detection circuit developing an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data, the error detection circuit comprising: a first data compression circuit including first and second pairs of complementary inputs adapted to receive first and second complementary data signals, respectively, and having a pair of outputs; a second data compression circuit including first and second pairs of complementary inputs adapted to receive third and fourth complementary data signals, respectively, and having a pair of outputs; a third data compression circuit including a first pair of complementary inputs coupled respectively to the outputs of the first data compression circuit, and a second pair of complementary inputs coupled respectively to the outputs of the second data compression circuit and having a pair of outputs; a logic gate having an output and having inputs coupled respectively to the outputs of the third data compression circuit, and a latch having a set input coupled to the output of the logic gate and an output coupled to a data terminal of the memory device; and a control circuit coupled to the test mode terminal, the error detection circuit, and the memory-cells, the control circuit operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.