Patent ID: 7473635

Claim:
A method for manufacturing a semiconductor device having the step of forming a wiring by a damascene method, comprising the steps of: forming an etching stopper film and an interlayer insulating film in sequence over a conductive layer; forming a silicon carbide film, a silicon nitride film, or a silicon oxynitride film as a first hard mask over the interlayer insulating film; forming a silicon oxide film as a second hard mask over the first hard mask; forming a silicon carbide film or a silicon nitride film as a third hard mask over the second hard mask; forming a silicon oxide film as a fourth hard mask over the third hard mask; forming a pattern over the fourth hard mask; etching the fourth hard mask by using the pattern; etching the third hard mask by using the fourth hard mask; etching the second hard mask by using the third hard mask; etching the first hard mask by using the third hard mask; forming an opening which reaches the etching stopper film in the interlayer insulating film by etching the interlayer insulating film by using the third hard mask; etching a portion of the etching stopper film which is exposed from the opening formed in the interlayer insulating film; and embedding a wiring material in the opening, wherein a thickness of the third hard mask is more than twice that of the first hard mask, and wherein said step of forming the pattern over the fourth hard mask comprises the steps of: forming a first pattern over the fourth hard mask with a first resist mask; removing the first resist mask; forming a resin film over an entire surface; forming a pattern over the resin film with a second resist mask; forming a second pattern over the fourth hard mask with the resin film as a mask; and removing the resin film.