Patent ID: 7991820

Claim:
A One Step Binary Summarizer circuit comprising: An Operation Control Unit for selecting one of an addition operation and a subtraction operation that is applied to two input operands, said Operation Control Unit including: a Decoder Module having a combinational circuit that converts information from N input lines to M separate, distinct, and mutually exclusive combination output lines, wherein N and M are digit numbers, with N<M, and wherein (numeric base) N =M; and wherein the numeric base is binary, with N=3, and M=8; an operation control module coupled to the decoder module for generating signal indicating the selected one of addition operation and a subtraction operation; a resultant operand Sign Bit Generator Module coupled with the decoder module for determining a sign of a resultant operand; and a Magnitude and Sign Module, which determines and displays if the input operands are identical, and if they are identical in both value and sign; and if they are not identical, which input operand has higher absolute value and which input operand has higher relative value; and one or more One Step Binary Summarizer Units coupled to the Operation Control Unit for performing said selected one operation.