Patent ID: 7585726

Claim:
The fabrication process of a nonvolatile semiconductor memory device, comprising: a step of forming a first conductivity type well in a silicon substrate; a step of forming in the first conductivity type well a second conductivity type semiconductor region which will be formed into a source/drain; a step of forming a first gate in the silicon substrate via a first gate oxide film; a step of forming a second gate in such a manner as to insulate the second gate from the first gate with a second insulating layer which covers the first gate; a step of forming a third gate in such a manner as to insulate the third gate from the first gate and the second gate with a third insulating layer and a fourth insulating layer; and a step of forming a fifth insulating layer adjacent to the first gate, wherein the first gate is formed in such a manner that one of surfaces of the first gate, which contacts with the second gate via the second insulating layer, has a dented shape as viewed in sections which are perpendicular to the silicon substrate, one of the sections being taken in a direction extending from the first gate to the third gate and the other section being taken in a direction extending from the first gate to the fifth insulating layer, a step of covering the third gate and the fourth insulating layer with the fifth insulating layer which is formed from a material different from that used for forming the fourth insulating layer after forming the third gate and a multilayer of the fourth insulating layer; a step of processing the fifth insulating layer to form a space for forming therein the first gate; a step of forming the first gate oxide film; a step of forming the third insulating layer; a step of depositing a first gate material in such a manner as to avoid filling up the space perfectly; a step of filling with a resist material the space remaining after the deposition of the first gate material; a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate becomes greater than at least one of those of the fourth insulating layer and the fifth insulating layer; a step of depositing the second insulating layer; a step of depositing a second gate material; and a step of processing the second gate in such a manner that a portion of the second insulating layer covering a dented surface of the first gate is not exposed.