Patent ID: 7718497

Claim:
A method for manufacturing a semiconductor device, comprising: forming a gate electrode on an active region of a semiconductor layer having a device isolation region in addition to the active region; forming a sidewall spacer on a sidewall surface of the gate electrode by using a material different from those of the semiconductor layer, the device isolation region and the gate electrode; forming a pair of source and drain regions in the active region by introducing impurities into the active region while using the device isolation region, the gate electrode and the sidewall spacer as a mask; covering top surfaces of the semiconductor layer, the device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which has a higher etching selectivity of the unreacted portion of the metal film and the sidewall spacers than that of the device isolation regions, resistance-reduced portions of the gate electrodes and resistance-reduced portions of the source and drain regions, wherein the semiconductor layer and the gate electrodes include silicon, the metal film includes one of Ni, Co and Ti, the sidewall spacers are formed of either one of GeCOH and SiBN, and the etchant which has a higher etching selectivity of the unreacted portion of the metal film and the sidewall spacers than that of the device isolation regions, resistance-reduced portions of the gate electrodes and resistance-reduced portions of the source and drain regions is a SPM (sulfuric-acid and hydrogen-peroxide mixture) or APM (ammonia and hydrogen-peroxide mixture).