Patent ID: 8211801

Claim:
A method of fabricating a CMOS device, comprising: forming an isolation structure in a substrate to define a first-type metal-oxide-semiconductor (MOS) region and a second-type MOS region; sequentially forming an interfacial layer and a high-k dielectric layer over the substrate; forming a first cover layer and a second cover layer respectively over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; forming a first gate stacked structure and a second gate stacked structure respectively over a part of the first cover layer and a part of the second cover layer, wherein the first gate stacked structure and the second gate stacked structure each comprise a first conductive layer, a second conductive layer and a hard mask layer; and performing an in-situ wet etching step by sequentially using a first etching solution to etch both the first cover layer and the second cover layer, and a second etching solution to etch both the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.