Patent ID: 8324709

Claim:
A semiconductor device, comprising: a substrate; an electrical fuse formed over said substrate, having a first interconnect and a second interconnect, respectively formed in different layers, and a via provided in a layer between said first interconnect and said second interconnect, the via being connected to one end of said second interconnect and connected also to said first interconnect; and a first guard interconnect, a second guard interconnect, and a third guard interconnect formed in the same layer with said second interconnect so as to surround said one end of said second interconnect, wherein, in a plan view, said second interconnect is formed so as to extend from an other end towards said one end, and said first guard interconnect, said second guard interconnect, and said third guard interconnect are formed so as to surround the one end of the second interconnect in three directions, and wherein a site of disconnection is formed in said via when the electrical fuse is blown.