Patent ID: 8238154

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array which includes a plurality of memory cells, each including a charge storage layer and a control gate, being capable of holding not less than two levels of data, and having its current paths connected in series; bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells; a first voltage generator unit which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage externally supplied and which is as high as the first voltage, the second voltage being higher than the first voltage; and a second voltage generator unit which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator unit steps down the second voltage to generate the third voltage.