Patent ID: 7890682

Claim:
A semiconductor storage device comprising: an external input/output port to which a system bus of a server, which is extended to outside of the server without protocol conversion, is connected directly as a serial interface; a device controller that connects to the server using predetermined number of links among serial transmission links of the serial interface, which are successful in connection on initialization; wherein: the device controller comprises: an external link detection section that detects the serial transmission links, which are successful in connection; and a first register that stores a detection result of the external link detection section, the first register that can be accessed from outside of the device; a memory controller connected to the device controller through a control bus and a memory bus, wherein: the memory controller comprises: a downstream bus-error detection section that detects an error in downstream transmission in the memory bus; a memory error detection section that detects an error relating to access to a memory; and a third register that stores a detection result of the downstream bus-error detection section and a detection result of the memory error detection section, the third register that can be accessed from the outside of the device, through the control bus, the device controller further comprises: an upstream bus-error detection section that detects an error in upstream transmission in the memory bus; and a second register that stores a detection result of the upstream bus-error detection section, the second register that can be accessed from the outside of the device, and when information read from registers includes a fatal error, the device controller terminates data transmission forcedly at once, and transmits an error interrupt signal to the server as an external input/output signal.