Patent ID: 7068253

Claim:
A device for controlling a display on a display panel on which a plurality of data lines and a plurality of scanning lines are arranged in a matrix, the device comprising: a first generator for generating an original clock signal; a memory for storing display data received from an external device; a register for setting a division ratio of the original clock signal and the number of clocks of a reference clock signal per a scanning period and a number of active lines of the display panel, all of which being received from the external device; a second generator for dividing the original clock signal by the division ratio to generate the reference clock, to thereby generate a line pulse synchronized with the scanning period and a frame pulse synchronized with a frame period; and a data line driver for reading out display data from the memory according to the line pulse and the frame pulse, for converting the display data into a driving voltage to be provided to the display panel, wherein the data line driver reads out the display data line by line from an address on the memory according to the line pulse, the address corresponding to a top line of the display panel, and repeats the readout of the display data by using the address corresponding to the top line of the display panel according to the frame pulse.