Patent ID: 6847539

Claim:
A ferroelectric memory comprising a ROM area and a RAM area both including memory cells each having a ferroelectric capacitor, wherein said ROM area comprises: at least one real memory cell for storing data to be written in manufacturing process of said ferroelectric memory; a dummy memory cell; a reference memory cell having a ferroelectric capacitor therein whose residual dielectric polarization value is set to a predetermined value in the manufacturing process; a first bit line connected to said real memory cell and said dummy memory cell, and transferring therethrough an electric charge corresponding to a residual dielectric polarization value of the ferroelectric capacitor which is included in a selected one of said real memory cell and dummy memory cell; a second bit line connected to said reference memory cell, and transferring therethrough an electric charge corresponding to a residual dielectric polarization value of the ferroelectric capacitor which is included in said reference memory cell being selected in synchronization with a selection of said real memory cell or said dummy memory cell; and a sense amplifier connected to said first and second bit lines, for amplifying a difference in voltage between said first and second bit lines, the difference occurring due to the transferred electric charges.