Patent ID: 7515501

Claim:
An array of memory cells, comprising: a plurality of sections of memory, each section of memory having first and second sub-sections of memory, each sub-section of memory having a plurality of memory cells arranged in rows and columns of memory; a plurality of regions disposed between the plurality of sections of memory, each region having a first portion adjacent the first sub-sections of memory and a second portion adjacent the second sub-sections of memory; a plurality of sense amplifiers located in each of the plurality of regions, each sense amplifier coupled to a respective column of memory; a plurality of column select switches coupled to the plurality of sense amplifiers and configured to conduct current when activated; a plurality of column select lines located in the first or second portions of each of the plurality of regions, each column select line located in the first portion of a region associated with the first sub-sections of memory and each column select line located in the second portion of a region associated with the second sub-sections of memory, each column select line coupled to a group of column select switches to activate the respective column select switches; a first column select line decoder coupled to the column select lines associated with the first sub-sections of memory and configured to selectively activate the column select switches coupled to column select lines located in the first portion of at least one of the regions; and a second column select line decoder coupled to the column select lines associated with the second sub-sections of memory and configured to selectively activate the column select switches coupled to column select lines located in the second portion of at least one of the regions.