Patent ID: 7968870

Claim:
A thin film transistor, comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode and the substrate; a semiconductor layer, disposed on the gate insulating layer, including at least the following: a channel area corresponding to the gate electrode, first source and drain areas doped with an impurity outside the channel area, and second source and drain areas, including a metal, outside the first source and drain areas; source and drain electrodes overlapping substantially an entire length of the second source and drain areas and exposing the first source and drain areas, end parts of the source and drain electrodes being vertically aligned with end parts of the semiconductor layer; a planarization layer disposed on the gate insulating layer, the source and drain electrodes, and the channel area, and the planarization layer having openings exposing parts of the first source and drain areas and the source and drain electrodes; and a pixel electrode disposed on the planarization layer and electrically connected to at least one of the source and drain electrodes through one of the openings, the pixel electrode being in direct contact with the parts of the first source and drain areas exposed through one of the openings in the planarization layer.