Patent ID: 8259741

Claim:
An adaptive digital data processing system, comprising: a preliminary primary input; a preliminary secondary input; a primary input; a secondary input; an output; a logic processor for producing the output based at least in part on the primary input and the secondary input; a primary input processor, taking as its input the preliminary primary input, and producing as its output the primary input for the logic processor; and a secondary input processor, taking as its input the preliminary secondary input, and producing as its output the secondary input for the logic processor; wherein the producing the secondary input by the secondary input processor is controlled at least in part by the preliminary primary input, to cause the primary input and the secondary input to arrive at the processing logic in same digital signal frame phase, and wherein the primary input either: i) has certain overhead bit fields processed to appropriate values needed for the output, whereas the preliminary primary input has said certain overhead bit fields in their un-processed values, or ii) except for being delayed in its phase compared with the preliminary primary input by a given number of logic processor clock cycles, is identical with the primary input.