Patent ID: 8395217

Claim:
A method for formation of an isolation region in a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate comprising a semiconductor substrate, a buried dielectric layer overlying the semiconductor substrate and an upper semiconductor layer overlying the buried dielectric layer; forming a plurality of gates on the SOI substrate, the plurality of gates comprising a first dielectric layer overlying the SOI substrate and a conductive material layer overlying the first dielectric layer; forming one or more trenches between each of the plurality of gates, the one or more trenches extending through the conductive material layer and the first dielectric layer to expose the upper semiconductor layer; forming one or more sidewall spacers covering opposing sidewalls of the one or more trenches; extending the one or more trenches through the upper semiconductor layer of the SOI substrate to expose the buried dielectric layer; and forming, in the one or more trenches, an epitaxial lateral growth layer, wherein the epitaxial growth layer grows laterally from the opposing sidewalls of the one or more trenches to enclose a portion of the one or more trenches extending into the upper semiconductor layer, so that the epitaxial lateral growth layer includes an air gap region overlying the buried dielectric layer.