Patent ID: 8748969

Claim:
A non-volatile memory device comprising: a substrate; a plurality of semiconductor pillars on the substrate; a plurality of control gate electrodes stacked on the substrate and intersecting the plurality of semiconductor pillars; a plurality of dummy electrodes stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes; a plurality of via plugs connected to the plurality of control gate electrodes; and a plurality of wordlines on the plurality of via plugs, wherein each of the plurality of via plugs penetrates a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes, and wherein the plurality of control gate electrodes each includes a protrusion connected to the plurality of via plugs, and each of the plurality of dummy electrodes is adjacent to and spaced apart from the corresponding protrusion.