Patent ID: 8432385

Claim:
A display device comprising: a substrate; a pixel portion over the substrate; a driver circuit over the substrate, and comprising: first to ninth transistors; and first to second inverters, wherein one of a source and a drain of the first transistor is directly connected to a first power source, wherein the other of the source and the drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is directly connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the third transistor is directly connected to a second power source, wherein one of a source and a drain of the fourth transistor is directly connected to the first power source, wherein the other of the source and the drain of the fourth transistor is directly connected to one of a source and a drain of the fifth transistor, wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, wherein one of a source and a drain of the sixth transistor is directly connected to the second power source, wherein the other of the source and the drain of the sixth transistor is directly connected to one of a source and a drain of the seventh transistor, wherein the one of the source and the drain of the seventh transistor is directly connected to a gate of the third transistor, wherein a gate of the sixth transistor is directly connected to a gate of the seventh transistor, wherein an output terminal of the first inverter is directly connected to the gate of the fourth transistor, wherein an input terminal of the second inverter is directly connected to the other of the source and the drain of the second transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the first power source, wherein the other of the source and the drain of the eighth transistor is directly connected to one of a source and a drain of the ninth transistor, wherein the one of the source and the drain of the ninth transistor is directly connected to the input terminal of the second inverter, wherein the other of the source and the drain of the ninth transistor is directly connected to the second power source, and wherein an output terminal of the second inverter is directly connected to a gate of the eighth transistor.