Patent ID: 8760914

Claim:
A magnetic memory write circuitry comprising: a magnetic memory element coupled to a bit line on one end, a reference magnetic memory element used to read and write to the magnetic memory element, the reference magnetic memory element including a first magnetic tunnel junction (MTJ), a second MTJ, a third MTJ, and a fourth MTJ, the first MTJ coupled in parallel to the second MTJ, the third MTJ coupled in parallel to the fourth MTJ, the first MTJ being coupled in series with the third MTJ, the second MTJ being coupled in series with the fourth MTJ, each of the first, second, third, and fourth MTJs having associated therewith a resistance value; an access transistor coupled to an opposite end of the magnetic memory element and operative to select the magnetic memory element to be read or written thereto, the access transistor further coupled to a word line, the magnetic memory element being selected to be read from or written to when the bit line and word line are activated; a formatting circuit coupled to the second MTJ and the fourth MTJ and operable to apply programming current to the magnetic memory element through the first and second MTJs thereby causing changing of the respective resistance values of the first and second MTJs; a first inverter having an output coupled to the bit line and an input coupled to an input of the magnetic memory write circuit; a second inverter having an input coupled to the input of the magnetic memory write circuit and further having an output; and a third inverter having an input coupled to the output of the second inverter and an output coupled to the source of the access transistor and to virtual ground.