Patent ID: 8373260

Claim:
A chip package comprising: a circuit board comprising a substrate and a circuit layer positioned on the substrate; a pad comprising an electrical connection area in a center portion thereof and an extending area extending outward from the electrical connection area, the electrical connection area covering the circuit layer and electrically connected to the circuit layer, the extending area surrounding the electrical connection area and the circuit layer; a chip comprising two chip areas and an enlarging area having a top surface and a bottom surface at opposite major sides thereof, the enlarging area defining two through holes apart from each other, each chip area having an upper surface and a lower surface at opposite major sides thereof, the chip areas received in the respective through holes and electrically connected to the electrical connection area, the upper surface of each of the chip areas being coplanar with the top surface, and the lower surface of each of the chip areas being coplanar with the bottom surface; and a glue layer adhering the chip to the pad, the chip and the pad positioned on opposite sides of the glue layer.