Patent ID: 7613856

Claim:
A method of arbitrating access for a plurality of data channel inputs with different characteristics, the method comprising: providing a plurality of data channel inputs based on a priority ordering; setting a channel fair done bit in a channel fair done register for data channel inputs from the plurality of data channel inputs having a higher priority value than a winning data channel input, wherein the channel fair done register includes a channel fair done bit for each of the plurality of data channel inputs, and wherein a set channel fair done bit in the channel fair done register blocks an associated data channel input having a higher priority value than the winning data channel input from winning arbitration; determining the winning data channel input from the plurality of data channel inputs using a round robin ordering based on the priority ordering in response to a fairness enable signal being asserted, wherein the winning data channel input is a highest priority channel input with a pending request having a cleared channel fair done bit in the channel fair done register so that the winning data channel input is serviced prior to data channel inputs with higher priority values having associated channel fair done bits set in the channel fair done register; setting a minimum time counter and a maximum slice counter for the winning data channel input in response to a slot enable signal being asserted; allowing the winning data channel input to burst data for a minimum time based on the minimum time counter and a maximum time based on the maximum slice counter, wherein the winning data channel input is allowed to continue to burst the data until its request for access deasserts even when the maximum slice counter reaches zero in response to the maximum slice counter being assigned a maximum value; bumping an active data channel input that won arbitration to form a bumped data channel input in response to a requesting data channel input asserting an override priority signal for immediate access even when the requesting data channel input asserting the override priority signal has its associated channel fair done bit set in the channel fair done register, wherein the channel fair done bit associated with the bumped data channel input that lost a time slice in a current round robin ordering is cleared in the channel fair done register so that the bumped data channel input gets another time slice in the current round robin ordering; and causing the minimum time counter to expire in response to a done indication from the winning data channel input.