Patent ID: 8310879

Claim:
A method of programming an electrically programmable and erasable non-volatile memory having at least one floating-gate transistor coupled to a bit line and to a voltage reference line, and configured to be programmed with a programming voltage, the method comprising: in a phase of erasure of the electrically programmable and erasable non-volatile memory, applying a first negative voltage having an absolute value smaller than a threshold value of a PN diode to the bit line and to the voltage reference line, while applying a second positive voltage smaller than the programming voltage to a control gate of the at least one floating-gate transistor, a difference between the second positive voltage and the first negative voltage being equal to the programming voltage; and in a phase of writing to the electrically programmable and erasable non-volatile memory, applying the first negative voltage to the control gate of the at least one floating-gate transistor, and applying the second positive voltage to the bit line.