Patent ID: 7226838

Claim:
A method for fabricating a semiconductor device comprising: providing a semiconductor substrate; forming a first gate electrode including a dielectric layer pattern, a first conducting layer pattern, and an insulating nitride layer pattern, the first gate electrode functioning as a flash memory, wherein the first conductive layer pattern consists of conductive material and the insulating nitride layer pattern is formed in contact with the first conducting layer pattern; growing a thermal oxide layer on the semiconductor substrate, on sidewalls of the dielectric layer pattern and on sidewalls of the first conducting layer pattern up to a height of the first conducting layer such that the thermal oxide layer is not grown above the first conducting layer and is not grown on the sidewalls of the insulating nitride layer pattern; forming a nitride layer on the thermal oxide layer and on the insulating nitride layer pattern; partially removing the nitride layer and the thermal oxide layer to form spacers on sidewalls of the first gate electrode, the spacers comprising the nitride layer pattern and the thermal oxide layer pattern; forming a second oxide layer on the semiconductor substrate but not on the first gate electrode or the spacers; and forming a second conducting layer over the second oxide layer, the first gate electrode, and the spacers.