Patent ID: 7906375

Claim:
A method for efficiently connecting multiple, separate and three dimensionally formed interconnection plates, each with a pre-determined geometry, onto a matching circuit substrate having a pair of bonded semiconductor dies atop, the method comprises: a) making a multi-plate carrier frame having the multiple interconnection plates integrally held thereon with a plurality of integrated interim holding members; b) separating the individual interconnection plates from the multi-plate carrier frame by breaking the interim holding members; c) attaching each interconnection plate onto the matching circuit substrate; wherein attaching each interconnection plate further comprises connecting one of the interconnection plates from the top of one semiconductor die to an exposed intermediate contact area, wherein the intermediate contact area comprises an L-shaped circuit route, being part of and coplanar with the circuit substrate, that extends from below the other semiconductor die and terminating with the exposed intermediate contact area atop the circuit substrate for electrically routing the bottom surface of die one to the exposed intermediate contact area whereby the presence of said L-shaped circuit route and exposed intermediate contact area allow reduction of the inter-die distance from an otherwise straight transverse circuit routing between the pair of bonded semiconductor dies.