Patent ID: 8072446

Claim:
A display, comprising: a display panel configured to display a plurality of frames; a driving control module, coupled to the display panel, the driving control module being configured to provide a driving signal of each of the frames to the display panel; a power-saving control module, coupled to the driving control module; and a timing controller, coupled to the driving control module and the power-saving control module, the timing controller being configured to provide a timing control signal and a power-saving switch signal, wherein a displaying period of each of the frames comprises a first period and a second period, during the first period, the display enters a displaying mode to display a first frame, and during the second period, the power-saving control module adjusts operating parameters of the driving control module such that the display enters a power-saving mode, and wherein the driving control module comprises a common electrode buffer, coupled to the display panel, the timing controller and the power-saving control module; a gate buffer, coupled to the display panel, the timing controller and the power-saving control module; a source buffer, coupled to the display panel, the timing controller and the power-saving control module; a digital to analog converter, coupled to the source buffer, the timing controller and the power-saving control module; and a display data memory, coupled to the digital to analog converter, the timing controller, and the power-saving control module.