Patent ID: 7592668

Claim:
A charge balance semiconductor power device, comprising: an active area comprising a plurality of cells capable of conducting current when biased in a conducting state; a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars formed in a silicon region of the second conductivity type, the strips of first conductivity type pillars having a depth, a width and a length, the alternately arranged strips of first and second conductivity type extending along their length through both the active area and the non-active perimeter region, wherein each of the strips of first conductivity type pillars includes a discontinuity along its length forming a portion of a strip of second conductivity type region extending in the non-active perimeter region perpendicular to the strips of first conductivity type pillars.