Patent ID: 7506237

Claim:
A programmable data combiner comprising: a plurality of registers configured to receive a 16-bit or less input from a first source and a 5-bit or less input from a second source and to generate a first 20-bit or less output based on the 16-bit or less input from the first source and the 5-bit or less input from the second source; and a selector configured to receive a mode signal, a first set of one or more control signals capable of modifying an output word length, and the first 20-bit or less output and to select 4 bits or less from the first 20-bit or less output to generate a first selection of 4 bits or less based on the mode signal and the first set of one or more control signals; and a filler configured to receive and combine the 16-bit or less input from the first source, a 16-bit or less input from a third source, and the 4 bits or less selection output by the selector to generate a 32-bit or less output based on a second set of control signals capable of modifying an output word length.