Patent ID: 8729689

Claim:
A stacked semiconductor package, comprising: a substrate unit, comprising a first substrate having a contact pad, a second substrate having a contact pad, and a connection substrate which connects the first substrate and the second substrate; a first chip laminate comprising a plurality of first semiconductor chips stacked on the first substrate; a second chip laminate comprising a plurality of second semiconductor chips stacked on the second substrate; a first conductive wire which electrically connects a bonding pad of each of the first semiconductor chips and the contact pad of the first substrate; a second conductive wire which electrically connects a bonding pad of each of the second semiconductor chips and the contact pad of the second substrate; and a bonding unit having a contact adhesive layer having a predetermined thickness disposed between an uppermost first semiconductor chip of the first chip laminate and an uppermost second semiconductor chip of the second chip laminate so that the first chip laminate and the second chip laminate are vertically stacked and bonded.