Patent ID: 7817385

Claim:
A semiconductor device comprising: a first circuit block powered by voltages at first and second power supply terminals; a second circuit block powered by voltages at third and fourth power supply terminals, the voltages at said first and third power supply terminals having a same voltage level as each other, the voltages at said second and fourth power supply terminals having a same voltage level as each other; a first ESD (electrostatic discharge) protection circuit including a first field effect transistor having a source, a drain, and a gate, where the gate and one of the source and the drain are connected to said first power supply terminal, the other of the source and the drain is connected to said third power supply terminal; and a first back gate potential adjusting circuit adapted to adjust a potential at a back gate of said first field effect transistor, wherein said first back gate potential adjusting circuit is adapted to make an absolute value of a threshold voltage of said first field effect transistor larger in a usual operation mode than in an ESD protection mode.