Patent ID: 7835899

Claim:
A method of simulation processing in a data processing system, said method comprising: receiving a collection of files including one or more HDL source files, wherein: the one or more HDL source files describe a plurality of hierarchically arranged design entities collectively representing a digital design to be simulated; the one or more HDL source files include a statement specifying inclusion, within one of the plurality of design entities, of an instrumentation entity described in the collection of files, wherein said instrumentation entity does not form a portion of the digital design but enables observation of its operation during simulation, said instrumentation entity including sequential logic containing at least one storage element, the instrumentation entity having an output signal capable of indicating occurrence of an event during simulation; processing the collection of files to obtain an instrumented simulation executable model, wherein the processing includes: instantiating, within said instrumented simulation executable model, at least one instance of each of the plurality of design entities; instantiating said instrumentation entity within each instance of said one of said plurality of design entities; instantiating, within said instrumented simulation executable model, external instrumentation logic to record occurrences of the event, wherein said external instrumentation logic is logically coupled to each instance of said instrumentation entity; and recording the instrumented simulation executable model in data storage; and wherein said collection of files describes at least a portion of said instrumentation entity utilizing a non-HDL instrumentation language and includes: a first instrumentation language statement in the non-HDL instrumentation language that defines a default clock qualifier specifying at least one latch clock applicable to one or more second instrumentation language statements; and the one or more second instrumentation language statements describing said sequential instrumentation logic to which said default clock qualifier applies, wherein the one or more second instrumentation language statements describe the sequential instrumentation logic without reference to the at least one latch clock.