Patent ID: 8847641

Claim:
A phase comparison device, which compares a phase of a first clock with a phase of a second clock having the same frequency as the first clock and delayed from the first clock just by a delay amount D1, the phase comparison device comprising: a divider that generates a division clock obtained by receiving said first clock and dividing the first clock by N, N being a positive integer not smaller than two; an inverter that inverts a phase of said division clock to generate a division inverted clock; a first synchronizing section to synchronize said division inverted clock sequentially with delay clocks in the number of m, m being a positive integer not smaller than N−1, to generate a synchronized clock, the delay clocks having the same frequencies as said first clock and whose delay amounts from said first clock increase by 2π each at the maximum within a range smaller than said delay amount D1 when one cycle of said first clock is regarded as 2π; a second synchronizing section to synchronize said synchronized clock with said second clock to generate a final synchronized clock; and a phase comparator that receives said division clock and said final synchronized clock to compare phases of the division clock and the final synchronized clock.