Patent ID: 7884364

Claim:
An array substrate, comprising: a substrate; a plurality of gate lines on the substrate; a plurality of data lines crossing the gate lines to define a plurality of pixel regions; a plurality of thin film transistors connected to the gate and data lines; a plurality of pixel electrodes in each of the plurality of pixel regions; and a plurality of common electrodes associated with each pixel region, each common electrode including first, second, third, fourth and fifth portions, wherein the first and second portions are respectively disposed at opposite sides of each of the plurality of data lines, each of the third and fourth portions is connected to the first and second portions, and the fifth portion is connected to the second portion and extends from one pixel region into a next pixel region adjacent to the one pixel region, wherein the fifth portion is spaced apart from the first portion in the one pixel region, and from the first portion in the next adjacent pixel region.