Patent ID: 7732906

Claim:
A semiconductor device comprising: a wiring substrate having a plurality of first electrodes and a plurality of second electrodes; a memory chip having a plurality of first bonding pads, and mounted over an upper surface of the wiring substrate; a microcomputer chip having a plurality of second bonding pads, and mounted over an upper surface of the memory chip; a plurality of first wires electrically connecting the plurality of first electrodes with the plurality of first bonding pads; a plurality of second wires electrically connecting the plurality of second electrodes with the plurality of second bonding pads; and a mold resin sealing the plurality of first electrodes, the plurality of second electrodes, the memory chip, the microcomputer chip, the plurality of first wires, and the plurality of second wires; wherein a number of the plurality of second electrodes is more than a number of the plurality of first electrodes; wherein the plurality of second electrodes are arranged more toward a periphery of the wiring substrate than the plurality of first electrodes; and wherein a number of the plurality of second bonding pads is more than a number of the plurality of first bonding pads.