Patent ID: 8176387

Claim:
An error detection control system comprising: a nonvolatile memory having data areas for a plurality of addresses, the data areas each including a main data area for storing predetermined data and a redundant data area for storing redundant data to be used in an error detecting process on the data; memory control means for controlling on the nonvolatile memory a batch erasing process on a data area group basis, the data area group including the data areas of a predetermined number of addresses, a reading process on the data area basis, a programming process on the data area basis, and an overwriting process on the main data area after the programming process on a bit basis, the bit constituting the main data area; error detecting means for executing the error detecting process on read-out data in the reading process, based upon the corresponding redundant data; and error detecting control means for controlling availability of execution of the error detecting process on the read-out data by the error detecting means, based upon data types to be classified depending on whether or not the read-out data is subjected to the overwriting process or a storage state indicating whether or not the overwriting process has been executed.