Patent ID: 6992511

Claim:
An output buffer circuit comprising: an output section for driving an output terminal which outputs a binary signal to a plurality of predetermined voltages; and a bias control section for variably controlling driving capability of the output section by variably controlling a bias to drive the output section in a transition period where the output terminal reaches one of the predetermined voltages, wherein the bias control section comprises: a plurality of bias control MOS transistors for varying the bias to drive the output section; and a timer section for providing a predetermined time where the plurality of the bias control MOS transistors are to be turned ON within the transition period, wherein the predetermined time includes a first predetermined time from a start of the transition period during which a first predetermined number of transistors among the plurality of the bias control MOS transistors are conductive and a second predetermined time after the first predetermined time during which a second predetermined number of transistors among the plurality of the bias control MOS transistors are conductive, wherein conducting capability of the first predetermined number of transistors is higher than that of the second predetermined number of transistors.