Patent ID: 8149017

Claim:
A voltage level translator circuit, comprising: a digital logic circuit having a digital logic signal; first and second high-voltage capacitors, each having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal; a cross-coupled inverter pair having the output of at least one inverter of the pair electrically coupled to the other connection of at least one of the first and second high-voltage capacitors; a sensing circuit configured to sense the state of the cross-coupled inverter pair and to produce an output signal having a voltage level higher than the digital logic signal; wherein the second capacitor has the first connection electrically coupled to the digital logic signal and the second connection electrically coupled to an output of the other of the at least one inverter of the pair; wherein the electrical coupling of the digital logic signal to the first connection of the second capacitor includes logic inversion.