Patent ID: 8273617

Claim:
A method for forming a field effect transistor (FET) in a doped well, the FET having a source, a drain, and a gate stack having a gate length, comprising the steps of: forming a screening region contacting the doped well, the screening region being doped with a first type of dopant to have a dopant concentration between 5×10 18 to 1×10 20 atoms/cm 3 , the screening region being electrically coupled to the doped well, the screening region being positioned below the gate stack to set a depletion depth; forming a substantially undoped semiconductive layer above the screening region, the substantially undoped semiconductive layer being adjacent to the screening region; forming a threshold voltage setting region in the substantially undoped semiconductive layer, the threshold voltage setting region being doped with the first type of dopant, the threshold voltage setting region dopant concentration modifying the threshold voltage of the FET; maintaining at least a portion of the substantially undoped semiconductive layer as a substantially undoped channel region having a first dopant concentration less than 1/10 of the screening region dopant concentration; forming the gate stack having a length Lg positioned above the doped well to control conduction between a drain and a source; and forming the source and the drain doped with a second type of dopant, wherein the substantially undoped channel region is laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region, and the threshold voltage setting region is vertically positioned between the substantially undoped channel region and the screening region.