Patent ID: 8375174

Claim:
A method for partitioning memory comprising: providing a plurality of boards, each of said plurality of boards including a physical memory portion and a set of one or more processors; and partitioning the physical memory portion in each of said plurality of boards into a plurality of logical partitions including a global memory partition accessible by any processor on any of the plurality of boards and one or more other memory partitions configured for use by one or more processors of said each board, each of said one or more other memory partitions not being accessible to a processor on a board other than said each board, wherein said one or more other memory partitions of said each board include a shared memory partition accessible to all processors on said each board and a private memory partition including a section for each processor on said each board wherein each section of the private memory partition used by an associated processor of said each board is used exclusively by said associated processor, and wherein each processor on said each board uses a memory map having a logical address range including a first logical address range portion that maps to a first section in the private memory partition used exclusively by said each processor, a second logical address range portion that maps to said shared memory partition of said each board, and a third portion mapping to global memory of the global memory partition whereby said global memory is used by said each processor and located on said each board.