Patent ID: 8181074

Claim:
A storage element configured to recover from a soft error, comprising: a plurality of inverting elements configured in a loop, each inverting element having an input node and an output node, an output node of a first of the plurality of inverting elements operably coupled to an input node of a second inverting element in the loop, wherein each inverting element comprises: a first switching element operably coupled between a first voltage potential and the output node, the first switching element configured to drive the output node to a logic zero when the input node is a logic one; and a second switching element operably coupled between a second voltage potential and the output node and directly to the first switching element, the second switching element configured to drive the output node to a logic one when the input node is a logic zero; and a plurality of first gating elements, each first gating element of the plurality of first gating elements comprising a third switching operably coupled to one of the plurality of inverting elements, the third switching element operably coupled in series between the first switching element and the first voltage potential, and wherein the third switching element of each first gating element further includes a first control node directly coupled to the output node of the second inverting element in the loop such that when the first control node is at a logic zero value, the first gating element prevents the corresponding inverting element from being able to drive its output node to a logic zero state.