Patent ID: 8884401

Claim:
A stacked resistive random access memory (RRAM), comprising: a first metal electrode layer; a first insulator above the first metal electrode layer wherein the first insulator is patterned to expose one or more first metal portions of the first metal electrode layer; a first Pr 1-x Ca x MnO 3 (PCMO) layer above the first insulator and the first metal portions, wherein x is between approximately 0.3 and approximately 0.5; a second metal electrode layer; a second insulator located above the second metal electrode layer, wherein the second insulator is patterned to expose one or more second metal portions of the second metal electrode layer; a second Pr 1-x Ca x MnO 3 (PCMO) layer above the second insulator and the second metal portions; and a last metal electrode layer, thus comprising a two-layer, resistive random access memory.