Patent ID: 7639695

Claim:
A system for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, comprising: a translation circuit translating a GMII reception signal received from a GMII interface device into an SPI-3 reception signal synchronized with an SPI3 reference clock, and translating an SPI-3 transmission signal received from an SPI-3 interface device into a GMII transmission signal synchronized with a GMII reference clock, said translation circuit comprising: first translation means for translating the GMII reception signal received from the GMII interface device into the SPI-3 reception signal synchronized with the SPI3 reference clock based on starting frame delimiter (SFD) pattern information in the GMII reception signal; and second translation means for translating the SPI-3 transmission signal received from the SPI-3 interface device into the GMII transmission signal synchronized with the GMII reference clock by adding the SFD pattern information to the SPI-3 transmission signal; said first translation means comprising: an SFD pattern detector for detecting the SFD pattern information from the GMII reception signal received from the GMII interface device; a first clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the GMII reception signal into the SPI-3 reception signal; and a first controller for translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock from the first clock synchronizer when the SFD pattern information received from the SFD pattern detector matches pre-stored SFD pattern information.