Patent ID: 7485567

Claim:
A method of manufacturing a microelectronic circuit, comprising the steps of: providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificing material over said first wiring level; forming a plurality of interconnect openings and a plurality of gap openings in said alternating layers of layer dielectric material and sacrificial material, said interconnect openings being formed over said first wiring level conductors; forming: metallic conductors comprising second wiring level conductors, and interconnects at said interconnect openings; removing said layers of said sacrificial material through said gap openings; replacing said layers of said sacrificial material with substantially horizontally extending relatively low dielectric constant (low-k) volumes; forming substantially vertically extending relatively low-k volumes in said gap openings; completely sealing said substantially vertically extending relatively low-k volumes and said substantially horizontally extending relatively low-k volumes such that said substantially vertically extending relatively low-k volumes and said substantially horizontally extending relatively low-k volumes remain low-k volumes in a finished form of said microelectronic circuit; wherein said first wiring level conductors, said second wiring level conductors, and said interconnects form a series of conductor structures, and said substantially vertically extending relatively low-k volumes and said substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between adjacent ones of said conductor structures as compared to an otherwise comparable microelectronic circuit not including said substantially vertically extending relatively low-k volumes and said substantially horizontally extending relatively low-k volumes.