Patent ID: 7350092

Claim:
A data synchronization arrangement for exchanging clocked data between different clock domains running in a digital processing equipment at substantially the same clock frequency but at an arbitrary relative phase shift, comprising: a buffer memory with a predetermined number of memory locations each of which has a data write port and a data read port, a write select multiplexer having a data input for receiving an input data stream synchronized with the clock from a first clock domain, one data output for each of said memory locations and connected to a respective data write port, and one write select input for each data output; a read select multiplexer having one data input for each of said memory locations and connected to a respective data read port, one read select input for each data input, and a data output supplying an output data stream synchronized with the clock from a second clock domain; a write select shift register with a number of stages corresponding to the predetermined number of memory locations and an output stage looped back to an input stage, each stage having an output connected to a respective one of the write select inputs of the write select multiplexer, the write select shift register being clocked with the clock from the first clock domain; a read select shift register with a number of stages corresponding to the predetermined number of memory locations, each stage having an output connected to a respective one of the read select inputs of the read select multiplexer, the read select shift register being clocked with the clock from the second clock domain; and a bit synchronization circuit for shifting bits from the write select shift register to the read select shift register to provide a relative offset between the bit patterns in the respective shift registers in response to clocking with the clocks in the first and second clock domains.