Patent ID: 8364904

Claim:
A method of horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer, the computer comprising a plurality of compute nodes, each compute node comprising at least one processor operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the compute nodes, each cache controller coupled for data communications to cache controllers on other compute nodes, the method comprising: responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by the first compute node to other compute nodes an eviction notice for the cache line; responsive to receiving the eviction notice, transmitting from each of the compute nodes receiving the eviction notice to all other compute nodes the state of the cache line on that compute node, including, if the cache line is missing from that compute node, an indication whether that compute node has cache storage space available for the cache line; evicting the cache line by the first compute node, including determining by the first compute node, in dependence upon the states of the cache line in other compute nodes and space available in other compute nodes, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.