Patent ID: 8819099

Claim:
A digital signal processor in a wireless communication device, the processor comprising: a vector unit, the vector unit including multiple instances of a CORDIC functional unit as execution stages of a processing pipeline, each CORDIC functional unit configured to perform one iteration of a CORDIC algorithm; first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform singular value decomposition of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers, the instruction set including: a first instruction that reads x and y coordinate values from the first register, reads angle z and iteration count n values from the second register, performs M iterations of the CORDIC algorithm using the multiple instances of the CORDIC functional unit, and writes updated x and y values from the M iterations to the first register without writing updated z and n values from the M iterations to the second register; a second instruction that reads x and y coordinate values from the first register, reads angle z and iteration count n values from the second register, performs M iterations of the CORDIC algorithm using the multiple instances of the CORDIC functional unit, and writes updated z and n values to the second register without writing updated x and y values to the first register.