Patent ID: 7211474

Claim:
A method of forming at least one CMOS transistor in a semiconductor wafer comprising the steps of: providing a bulk semiconductor wafer with at least one pad layer; patterning and etching an SOI region of said wafer in a first etch step with a set of trenches adapted to isolate a set of individual transistors in individual active areas; extending said set of trenches vertically in a second etch step; oxidizing said wafer transversely through sides of said set of trenches to a transverse dimension such that a layer of buried oxide is formed, containing a pillar of un-reacted semiconductor material in said individual active areas connecting vertically a set of transistor body areas with said bulk semiconductor wafer; forming a set of MOS transistors in said individual active areas such that the gate of said set of MOS transistors are self-aligned to said pillar.