Patent ID: 8233578

Claim:
A frequency synthesizer, comprising: a phase lock loop (PLL) having a plurality of output taps configured to generate an oscillator output signal having a plurality of output phases responsive to a feedback input, wherein said phase lock loop includes a feedback path coupled between an output of said PLL and said feedback input, wherein said feedback path includes a means for rotating a phase of said oscillator output signal in said feedback path to tune a frequency of said oscillator output signal, wherein said means for rotating includes, a plurality of differential amplifiers configured to receive said plurality of output phases; a differential output configured to combine respective outputs of said differential amplifiers; and means for weighting said plurality of output phases over time responsive to an input clock, wherein said means for weighting includes a plurality of digital-to-analog converters (DACs) arranged in groups, each group of DACs configured to supply bias current to a corresponding differential amplifier; and a shift register configured to receive said input clock and having a plurality of outputs configured to switch said plurality of digital-to-analog converters (DACs) responsive to said input clock.