Patent ID: 7018895

Claim:
A method for fabricating a nonvolatile memory, the method comprising: (1) forming a first conductive gate for a nonvolatile memory cell; (2) after the operation (1), forming conductive floating gates FG 1 and FG 2 for the memory cell; wherein the nonvolatile memory cell is part of an array of nonvolatile memory cells, each memory cell of the array having conductive floating gates FG 1 and FG 2 and a first conductive gate; wherein the method comprises, before the operation (1), performing the following operation: (a) forming one or more substrate isolation regions in a semiconductor substrate between active areas of the semiconductor substrate, each substrate isolation region being a dielectric region protruding above the semiconductor substrate; wherein the operation (1) comprises: (b) forming one or more conductive lines G 1 , each conductive line G 1 overlying at least one active area, wherein each first conductive gate comprises a portion of a line G 1 ; wherein the operation (2) comprises: (c) forming a layer (“FG layer”) over the first conductive lines and the substrate isolation regions, wherein each of the floating gates FG 1 , FG 2 of each memory cell comprises a portion of the FG layer; (d) partially removing the FG layer to expose the substrate isolation regions and to remove the FG layer from over at least a portion of each conductive line G 1 .