Patent ID: 7671422

Claim:
A semiconductor device comprising: a substrate having a first active area, a second active area, a third active area, and a fourth active area; a first pull-up transistor in the second active area, the first pull-up transistor having a source electrically coupled to a voltage source and having a drain; a first pull-down transistor in the first active area, the first pull-down transistor having a source electrically coupled to a ground, having a drain electrically coupled to the drain of the first pull-up transistor, and having a gate; a second pull-up transistor in the third active area, the second pull-up transistor having a source electrically coupled to a voltage source, having a drain, and having a gate; a second pull-down transistor in the fourth active area, the second pull-down transistor having a source electrically coupled to a ground, having a drain electrically coupled to the drain of the second pull-up transistor, and having a gate; wherein the drain of the first pull-up transistor and the drain of the first pull-down transistor are electrically coupled to the gate of the second pull-up transistor and the gate of the second pull-down transistor, and the drain of the second pull-up transistor and the drain of the second pull-down transistor are electrically coupled to the gate of the first pull-up transistor and the gate of the first pull-down transistor; a first bit line and a first complementary bit line; a second bit line and a second complementary bit line; a first pass-gate transistor in the first active area, the first pass-gate transistor having a first beta ratio, having a source connected to the first bit line, having a drain connected through the first active area to the drain of the first pull-down transistor, and having a gate; a second pass-gate transistor in the fourth active area, the second pass-gate transistor having a second beta ratio, having a source connected to the first complementary bit line, having a drain electrically coupled through the fourth active area to the drain of the second pull-down transistor, and having a gate; a third pass-gate transistor in the first active area, the third pass-gate transistor having a third beta ratio that is different from the first beta ratio, having a source connected to the second bit line, having a drain electrically coupled through the first active area to the drain of the first pull-down transistor, and having a gate; and a fourth pass-gate transistor in the fourth active area having a fourth beta ratio that is different from the second beta ratio, having a source connected to the second complementary bit line, having a drain electrically coupled through the fourth active area to the drain of the second pull-down device, and having a gate.