Patent ID: 8334551

Claim:
A non-volatile semiconductor storage device comprising: a plurality of memory blocks, each of the memory blocks having a plurality of memory strings with a plurality of memory cells connected in series, and each of the memory blocks being provided for each first area parallel to a substrate; and a plurality of wiring layers formed in a same plane and extending in a first direction parallel to the substrate, each of the memory blocks comprising: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer formed to extend in a lamination direction and penetrate the first conductive layers, the first semiconductor layer provided for each of the memory strings; an electric charge accumulation layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to accumulate electric charges; a second conductive layer provided below the first conductive layers and expanding in parallel to the substrate over the first area; a second semiconductor layer formed to extend in a lamination direction from the bottom surface of the first semiconductor layer and penetrate the second conductive layer; a first gate insulation layer formed between the second conductive layer and the second semiconductor layer; a third conductive layer provided above the first conductive layers, and formed to be aligned in the second direction and extend in the first direction at the first area; a third semiconductor layer formed to extend in a lamination direction from the top surface of the first semiconductor layer and penetrate the third conductive layer; and a second gate insulation layer formed between the third conductive layer and the third semiconductor layer, the second semiconductor layer, a part of the second conductive layer, and the first gate insulation layer being included in a plurality of first selection transistors connected in series to one ends of the memory strings, the third semiconductor layer, a part of the third conductive layer, and the second gate insulation layer being included in a plurality of second selection transistors connected in series to the other ends of the memory strings, the memory strings including the first semiconductor layer, parts of the first conductive layers, and the electric charge accumulation layer, and being arranged with m columns in a second direction orthogonal to the lamination direction and the first direction, for each of the memory blocks; the wiring layers being arranged in the second direction, being formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and being connected via contact plugs to the first conductive layers; and a relation represented by (Formula 1) being satisfied: m≧n (Formula 1).