Patent ID: 8659464

Claim:
An analog-digital converter which converts an analog signal into an N-bit digital signal (N being a positive integer), comprising: a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal (K being a positive integer of more than 1 and less than N) according to a control signal, the first clock signal being delayed by a first delay time from the clock signal and the Kth clock signal being delayed by a Kth delay time from the clock signal; a capacitive digital-analog converting unit receiving the analog signal and a reference signal and outputting a difference between the analog signal and the reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal, wherein the N-bit digital signal is divided into K groups from a most significant bit, each of the K groups includes at least one bit, and the clock delay adjusting unit sequentially transfers one of the first to Kth clock signals according to the control signal to the comparison unit and the SAR logic unit to correspond to the K groups according to the control signal.