Patent ID: 7477044

Claim:
A circuit of an output stage of an LDO voltage regulator implemented with low-voltage devices and still allowing higher voltage levels is comprising: a low-voltage PMOS pass device having its source connected to VDD voltage and to its bulk, its gate is controlled by said LDO voltage regulator, its drain is connected to a means of controllable resistance; said means of controllable resistance protecting actively a voltage level at the drain of said PMOS pass device is implemented between the drain of said PMOS pass device and an output port of the LDO voltage regulator; a first voltage limiting means implemented in parallel to said PMOS pass device; and a second voltage limiting means implemented in parallel to said means of controllable resistance, wherein said second voltage limiting means is a Zener diode having a maximal threshold voltage corresponding to a maximal tolerable voltage level of said pass device.