Patent ID: 7154312

Claim:
An apparatus for generating an internal clock signal synchronized with an external clock signal, the apparatus comprising: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal by a predetermined time to output a delayed first reference clock signal; a forward delay array comprising a plurality of first delay units for sequentially delaying the delayed first reference clock signal output from the delay compensation circuit in a forward direction to output first delayed clock signals; a mirror control circuit including a plurality of phase detectors; a plurality of local clock drivers, less in number than the plurality of phase detectors, receiving the first reference clock signal and each producing therefrom a second reference clock signal, wherein the plurality of phase detectors respectively receive the first delayed clock signals from the plurality of first delay units, wherein the plurality of phase detectors are arranged in groups and the phase detectors in each group each receive the second reference clock signal from one of the plurality of local clock drivers, and wherein the mirror control circuit determines second delayed clock signals comprising the first delayed clock signals that are in phase with the second reference clock signal; a backward delay array comprising a plurality of second delay units for sequentially delaying the second delayed clock signals output from the mirror control circuit in a backward direction to output third delayed clock signals; and an output buffer for buffering the third delayed clock signals of the backward delay array to generate the internal clock signal.