Patent ID: 8667254

Claim:
A device, comprising: a processor; a core memory having a receive buffer and a transmit buffer; a bus coupled to the processor and the core memory; at least one co-processor separate from the core memory and coupled to the core memory via a direct link that is accessible only by the at least one co-processor and by the core memory, wherein the at least one co-processor accesses at least one of: the receive buffer of the core memory, or the transmit buffer of the core memory, without assistance from the processor; and at least one network interface providing a direct path between the core memory and a network; wherein: the receive buffer has a plurality of portions and the transmit buffer has a plurality of portions; a first one of the portions of the receive buffer and a first one of the portions of the transmit buffer are dedicated to network and bus access; a second one of the portions of the receive buffer and a second one of the portions of the transmit buffer are dedicated to co-processor and bus access; and a third one of the portions of the receive buffer and a third one of the portions of the transmit buffer are dedicated to network and co-processor access.