Patent ID: 7778073

Claim:
An integrated circuit comprising: a first bit line; a second bit line; a third bit line; a first memory cell string comprising a plurality of serially source-to-drain coupled memory cells; a second memory cell string comprising a plurality of serially source-to-drain coupled memory cells; the first bit line being coupled to a source/drain region of a first memory cell of the plurality of serially source-to-drain coupled memory cells of the first string; the second bit line being coupled to a source/drain region of a first memory cell of the plurality of serially source-to-drain coupled memory cells of the second string; and the third bit line being coupled to a source/drain region of a last memory cell of the plurality of serially source-to-drain coupled memory cells of the first string and to a source/drain region of a last memory cell of the plurality of serially source-to-drain coupled memory cells of the second string; and wherein at least one memory cell of the first and/or second memory cell strings comprises: a trench in a carrier, wherein the source/drain regions of the at least one memory cell is next to the trench; a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions and; electrically conductive material at least partially filled in the trench.