Patent ID: 7080115

Claim:
A fixed-width multiplier, comprising: a plurality of adder cells; and a digital circuit coupled to said plurality of adder cells that generates a compensation bias, said digital circuit being formed by selecting a canonic signed digit value (Y), multiplying a W-bit variable (X) by the canonic signed digit value (Y) to produce sign-extended partial products each having an associated weight (2 n ), associating each partial product with a most significant bit group (MP) or a least significant bit group (LP), associating the partial products of the least significant bit group (LP) with a major least significant bit group (LP major ) or a minor least significant bit group (LP minor ), computing an error compensation bias for each possible input bit combination of the partial products having the greatest weight of the least significant bit group (LP), and forming a circuit to generate the error compensation biases computed in said computing step from the partial products having the greatest weight of the least significant bit group (LP).