Patent ID: 7327610

Claim:
A semiconductor memory device comprising; a plurality of memory cells arranged in a two dimensional matrix of memory cells, said matrix of memory cells being divided into a plurality of two dimensional arrays of memory cells, a plurality of word lines, said word lines traversing said matrix of cells in a first direction, a plurality of bit line pairs, said bit lines traversing said matrix in a second direction, each pair of bit lines having a first and second bit line, one of said memory cells being located at the intersection of a word line and either one of said first or said second bit lines, alternate pairs of said bit lines being twisted between adjacent arrays of memory cells, each pair of bit lines having an associated sense amplifier to detect voltage differences between said pair of bit lines, a plurality of pre-charge circuits, each pre-charge circuit charging one bit line of two adjacent bit line pairs, the two bit lines in each bit line pair being charged to different voltages, and a sense stress test circuit for simultaneously activating all word lines, whereby when said pre-charge circuits charge the two bit lines in each bit line pair to different voltages, and all word lines are simultaneously activated, each bit line only senses cells charged to one particular voltage.