Patent ID: 8135768

Claim:
An electronic circuit comprising: a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an input for receiving the at least two binary inputs; an output for outputting a carry out signal and a sum signal; a carry signal propagator coupled between said input and said output for determining said carry-out signal and said carry signal propagator including a first inverter for inverting a carry in signal; a logic circuit coupled to said carry signal propagator and having an input capacitance, said logic circuit including a summing circuit to calculate said sum signal; a capacitance decoupler coupled between said logic circuit and said carry signal propagator for decoupling said input capacitance of said logic circuit from said carry signal propagator, and for reducing said input capacitance of said carry signal propagator and providing carry signals using said carry in signal to said logic circuit to calculate said sum signal, wherein said capacitance decoupler comprises a second inverter having a first and second field effect transistor (FET) having a gate, a source, and a drain and a third inverter having a third and fourth FET having a gate, a source, and a drain; wherein an input of said first inverter is connected to said gate of said first FET, an output of said first inverter is connected to said gate of said third FET, an output of said second inverter is connected to said gate of said fourth FET, and an output of said third inverter is connected to said gate of said second FET, and said outputs of said second and third inverters also connected to said logic circuit to calculate said sum signal; and wherein said capacitance decoupler causes a capacitive loading of said carry signal propagator to be shared evenly between said second and third inverters, and an overall capacitance on said carry signal propagator is reduced.