Patent ID: 8370410

Claim:
A floating point adder, comprising: an addition circuit configured to perform a selected operation from a plurality of addition operations on a first floating point value and a second floating point value, said plurality of addition operations comprising an addition operation and a half-addition operation; a small exponent difference datapath within the addition circuit configured to generate an SED result mantissa; an exponent datapath within the addition circuit configured to generate a result exponent and an LED/SED select signal responsive to said first floating point value and said second floating point value; a large exponent difference datapath within the addition circuit comprising an LED selection logic configured to select, responsive to a half-adder operation signal, an ‘A’ mantissa variant and one of a ‘B’ mantissa or a ‘B’/2 mantissa, said selected ‘B’ mantissa and said ‘A’ mantissa variant used to generate an LED result mantissa, said half-adder operation signal responsive to said selected operation; and a construct result logic within the addition circuit configured to select a result mantissa from said LED result mantissa or said SED result mantissa, the construct result logic further configured to construct a floating point result value from said result mantissa and said result exponent.