Patent ID: 7978503

Claim:
A static semiconductor memory, comprising: a memory cell including a pair of P-channel MOS load transistors, a pair of N-channel MOS transfer transistors, and a pair of N-channel MOS drive transistors; a dummy memory cell including a pair of P-channel MOS load transistors, a pair of N-channel MOS transfer transistors, and a pair of N-channel MOS drive transistors; and voltage control circuits selected from the group of the following voltage control circuits consisting of: a voltage control circuit for decreasing a voltage of a source power supply allocated to the P-channel MOS load transistors of both the memory cell and the dummy memory cell, a voltage control circuit for increasing a voltage of a source power supply allocated to the N-channel MOS drive transistors of both the memory cell and the dummy memory cell, a voltage control circuit for increasing a substrate potential of the P-channel MOS load transistors of both the memory cell and the dummy memory cell, a voltage control circuit for increasing a substrate potential of the N-channel MOS transfer transistors of both the memory cell and the dummy memory cell, and a voltage control circuit for decreasing a substrate potential of the N-channel MOS drive transistors of both the memory cell and the dummy memory cell, wherein: in a data write operation for the memory cell, the voltage increasing or decreasing operation starts as a write assist operation, a data write operation for the dummy memory cell starts by supplying a dummy selection signal to gates of the pair of N-channel MOS transfer transistors of the dummy memory cell before supplying a selection signal to gates of the pair of N-channel MOS transfer transistors of the memory cell, and the voltage increasing or decreasing operation as a write assist operation ends after completion of the data write operation for the dummy memory cell is detected.