Patent ID: 7015525

Claim:
A folded bit line DRAM device, comprising: an array of memory cells formed in rows and columns, wherein each memory cell in the array of memory cells includes: a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer; a single crystalline vertical transistor formed along a side of the pillar, wherein the single crystalline vertical transistor includes: a single crystalline vertical first source/drain region coupled to the first contact layer; a single crystalline vertical second source/drain region coupled to the second contact layer; and a single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array of memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.