Patent ID: 8026507

Claim:
A gated quantum well device, comprising: a well of a first conductivity type formed in a semiconductor substrate; a gated quantum well device gate dielectric layer formed on a top surface of said well; a gated quantum well device gate formed on a top surface of said gated quantum well device gate dielectric layer; gated quantum well device gate sidewall spacers formed on lateral surfaces of said gated quantum well device gate; gated quantum well device source/drain regions of said first conductivity type formed in said well adjacent to said gated quantum well device gate sidewall spacers such that said gated quantum well device source/drain regions are less than 20 nanometers apart across a quantum well region under said gated quantum well device gate; gated quantum well device lightly doped drain (LDD) regions of said first conductivity type formed in said well adjacent to said gated quantum well device gate such that said gated quantum well device LDD regions are less than 15 nanometers apart across said quantum well region under said gated quantum well device gate; and gated quantum well device halo regions of a second conductivity type formed in said well under said gated quantum well device gate between said gated quantum well device LDD regions.