Patent ID: 7195975

Claim:
A method of forming a bit line contact via, comprising: providing a substrate with a transistor thereon, the transistor having a gate electrode, drain region, and source region; forming a conductive layer overlying the drain region, wherein the top surface of the conductive layer is lower than that of the gate electrode, wherein forming the conductive layer further comprises: blanketly forming a layer of conductive material overlying the substrate; removing a portion of the conductive material layer, leaving the conductive layer overlying the drain region and source region, wherein the top surface of the conductive layer is lower than that of the gate electrode; forming a patterned resist layer exposing the conductive layer overlying the source region; removing the exposed conductive layer using the patterned resist layer as a mask; and removing the Patterned resist layer; conformally forming an insulating barrier layer overlying the substrate; blanketly forming a dielectric layer overlying the insulating barrier layer; and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.