Patent ID: 8078840

Claim:
An apparatus for selecting one of N threads for fetching instructions into N respective instruction buffers from an instruction cache in a multithreading microprocessor that concurrently executes the N threads, the apparatus comprising: a first round-robin generator, having a circuit configured to receive a first N-bit value specifying which of the N threads was last selected to fetch instructions and a second N-bit value specifying if a corresponding one of the N threads is enabled for fetching and has an empty instruction buffer; and generate a first round-robin indicator indicating a next one of the N threads in round-robin order which is enabled for fetching and has an empty instruction buffer; a second round-robin generator, having a circuit configured to receive a first N-bit value specifying which of the N threads was last selected to fetch instructions and a second N-bit value specifying if a corresponding one of the N threads is enabled for fetching; and generate a second round-robin indicator indicating a next one of the N threads in round-robin order which is enabled for fetching; and a multiplexer, coupled to receive said first and second indicators and a selection control fetch priority signal generated by control logic, and configured: to output said first indicator if at least one of the N threads is enabled for fetching and has an empty instruction buffer; and to output said second indicator otherwise; wherein said output indicates which of the N threads is selected for fetching instructions.