Patent ID: 7319061

Claim:
A method for fabricating an electronic device including an n-transistor with a drain extension structure and a p-transistor with a drain extension structure, the method comprising: previously obtaining a first correspondence between a size of a gate electrode of the n-transistor and ion implantation conditions for forming the drain extension structure of the n-transistor, the first correspondence satisfying that the n-transistor has a given threshold voltage; previously obtaining a second correspondence between a size of a gate electrode of the p-transistor and heat treatment conditions for forming the drain extension structure of the p-transistor, the second correspondence satisfying that the p-transistor has the given threshold voltage; forming the gate electrodes of the respective n-transistor and p-transistor; measuring the sizes of the gate electrodes of the respective n-transistor and p-transistor; setting ion implantation conditions for forming the drain extension structure of the n-transistor, based on the previously-obtained first correspondence and the measured size of the gate electrode of the n-transistor; performing first ion implantation for forming the drain extension structure of the n-transistor under the ion implantation conditions that have been set; performing second ion implantation for forming the drain extension structure of the p-transistor; setting heat treatment conditions for forming the drain extension structure of the p-transistor, based on the previously-obtained second correspondence and the measured size of the gate electrode of the p-transistor; and performing heat treatment for forming the drain extension structures of the n-transistor and the p-transistor under the heat treatment conditions that have been set, after the steps of performing the first ion implantation and the second ion implantation.