Patent ID: 8456921

Claim:
A nonvolatile memory comprising: a first bit line coupled to a first cell string; a second bit line coupled to a second cell string; and a bit line precharge unit configured to precharge the first bit line and the second bit line before a program operation, wherein a bit line selected from among the first bit line and the second bit line is precharged to a lower voltage level than a target voltage level, and an unselected bit line is precharged to the target voltage level, wherein the bit line precharge unit comprises: a first transistor configured to transfer a precharge voltage to the first bit line in response to a first precharge signal; and a second transistor configured to transfer the precharge voltage to the second bit line in response to a second precharge signal, and wherein, during a precharge operation, a precharge signal corresponding to the selected bit line from among the first precharge signal and the second precharge signal has a lower voltage level than a precharge signal corresponding to the unselected bit line.