Patent ID: 8142961

Claim:
A pattern correcting method for correcting design patterns to form a desired pattern on a wafer, the method comprising: preparing a circuit model; defining an allowable dimensional change quantity for the circuit model; assigning the allowable dimensional change quantity to each of a plurality of design patterns included in a design layout; calculating a dimension of a finished pattern of said each design pattern on a wafer; acquiring a difference between the dimension of the finished pattern and a dimension of a desired pattern of said each design pattern on the wafer; checking whether or not the difference of the dimensions satisfies the allowable dimensional change quantity for said each design pattern; and correcting said each design pattern so that the difference of the dimensions satisfies the allowable dimensional change quantity, wherein correcting said each design pattern comprises: defining a pattern correction condition for said each design pattern based on the allowable dimensional change quantity; carrying out, via a computer, a simulation of an operation using the circuit model; and determining, based on the simulation, whether or not a predetermined operation margin is attained for the circuit model, and performing correction for said each design pattern based on the pattern correction condition until it is determined that the predetermined operation margin is attained.