Patent ID: 8584053

Claim:
A method for designing a mask set for patterning a mask layer for a semiconductor device, the semiconductor device comprising a plurality of active regions and a transistor gate array comprising a plurality of transistor gate lines, wherein the method comprises: designing a first mask set for etching the transistor gate array during a first etch; and using a computer, designing a second mask set for etching the transistor gate array during a second etch using a method comprising: specifying that a lateral distance between an edge of an opening defined by the second mask set which transects the transistor gate array and an edge of an active area of the plurality of active regions is at least a value “B”, where “B” is determined by the formula: ( MA ( POLY ⁢ _ ⁢ SUB ⁢ ⁢ to ⁢ ⁢ ACTIVE ) ) 2 + ( CD ( POLY ⁢ _ ⁢ SUB ) / 2 ) 2 + ( CD ( ACTIVE ) / 2 ) 2 where “MA (POLY — SUB to ACTIVE) ” is a misalignment of the second mask set to a mask which defines the plurality of active regions, “CD (POLY — SUB) ” is a critical dimension of the second mask, and “CD (ACTIVE) ” is the critical dimension of the mask which defines the plurality of active regions.