Patent ID: 8050099

Claim:
A non-volatile memory device comprising: a memory cell array including memory cells; a page buffer circuit including page buffers, wherein each page buffer is coupled to a bit line corresponding to the memory cells and is configured to temporarily store data to be programmed to a specific memory cell or store data read from a given memory cell; a voltage generating circuit configured to generate an operation voltage for reading or verifying data from the given memory cell, wherein the voltage generating circuit includes: a first voltage outputting circuit configured to receive an input voltage, adjust the input voltage and output a first voltage in accordance with the temperature; a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit; and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage as the operation voltage by dividing a driving voltage which is a high voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal; and a controller configured to output a first control signal for storing data in the memory cell array or reading data from the memory cell array.