Patent ID: 7301369

Claim:
A programmable gate array apparatus comprising: a plurality of macrocells connected in series; a first input unit configured to input a load signal to the macrocells; a second input unit configured to input a swap signal to the macrocells; a third input unit configured to input one of a plurality of context data items to the macrocells; and a fourth input unit configured to input a clock signal to the macrocells; and each of the macrocells including: a first group of storage elements in which another of the context data items is stored as an active context data item; a second group of storage elements corresponding to the storage elements of the first group respectively, in which another of the context data items is stored as an idle context data item; a loading control unit configured to connect the storage elements of the second group in series when the load signal is input, to connect the macrocells in series via the second group in the each of the macrocells, and load, by using the clock signal, the one of the context data items into the second group whose storage elements are connected in series, to store the one of the context data items in the second group as the idle context data item; and a swapping control unit configured to connect the first group and the second group by connecting the storage elements of the first group to corresponding storage elements of the second group respectively when the swap signal is input, and swap the another of the context data items and the one of the context data items between the first group and the second group, to store the one of the context data items in the first group as the active context data item and to store the another of the context data items in the second group as the idle context data item.