Patent ID: 6868030

Claim:
A semiconductor memory apparatus, comprising: a first I/O port and a second I/O port; a cell array circuit divided into a plurality of column blocks and a plurality of row blocks; a first column line and a second column line corresponding to said first I/O port and said second I/O port, respectively; a first global data bus and a second global data bus corresponding to said first I/O port and said second I/O port, respectively, said first global data bus and said second global data bus being provided to each one of the plurality of column blocks; a first bus connection gate circuit that connects a sense amp of one of the plurality of row blocks selected in response to an access through said first I/O port, said sense amp being selected by said first column line, to said first global data bus; and a second bus connection gate circuit that connects a sense amp of one of the plurality of row blocks selected in response to an access through said second I/O port, said sense amp being selected by said second column line, to said second global data bus.