Patent ID: 6939789

Claim:
A method of wafer level chip scale packaging comprising: providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end spaced a distance from the contact pad; forming an encapsulation layer over the semiconductor device including the redistribution trace; forming an opening in the encapsulation layer down to the redistribution trace; thereafter forming a contact post in the opening in the encapsulation layer comprising electroplating a metal over the semiconductor device and down into the opening in the encapsulation layer and planarizing the semiconductor device to remove portions of the electroplated metal over the semiconductor device to expose the encapsulation layer and leaving a contact post formed in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end; forming an electrically conductive bump on the semiconductor device and in electrical contact with the contact post.