Patent ID: 8513791

Claim:
A Content Addressable Memory-based (CAM-based) cache comprising an array of multi-ported Content Addressable Memory (CAM) cells, wherein each multi-ported CAM cell in said array includes: a storage element located on a first semiconductor layer and comprising a first set of complementary metal oxide semiconductor (CMOS) transistors having a 6T configuration including two inverters each having a first conductivity transistor and a second conductivity transistor, wherein the two inverters provide a first storage node and a second storage node, wherein access to each of the first storage node and the second storage node is provided by a pass gate transistor that is in contact with a write word line; a compare element located on a second semiconductor layer and comprising a second set of CMOS transistors having a 9T configuration with first conductivity compare element transistors and second conductivity compare element transistors; at least one first dielectric material located on and above said first semiconductor layer, wherein the at least one first dielectric material contains a portion of the write word line and a read word line; a match line embedded in at least one second dielectric material located on and above said second semiconductor layer, wherein the match line is in contact with at least one of the second set of CMOS transistors having the 9T configuration; and at least one vertical interconnect structure interconnecting said storage element and said compare element through said at least one first dielectric material and said at least one second dielectric material and through one of said first and second semiconductor layers, wherein one of the at least one vertical interconnect structures extends from a first of the first conductivity compare element transistors to the first conductivity transistor of the first storage node, a second of the at least one vertical interconnect structures extends from a first of the second conductivity compare elements transistor to the second conductivity transistor of the first storage node, a third of the at least one vertical interconnect structures extends from a second of the first conductivity compare elements transistor to the first conductivity transistor of the second storage node, and a fourth of the at least one vertical interconnect structures extends from a second of the second conductivity compare elements transistor to the second conductivity transistor of the second storage node, wherein the CMOS transistors having the 6T configuration are within an area footprint defined by the CMOS transistors having the 9T configuration.