Patent ID: 7188281

Claim:
An error correction coding apparatus comprising: a parity check matrix generation unit that generates a parity check matrix having elements arranged in rows and columns, with a number of the elements in each of the rows having a value of 1 and all of the other elements in the rows having a value of 0, and a number of the elements in each of the columns having a value of 1 and all of the other elements in the columns having a value of 0; a parity check matrix adjustment unit that receives the parity check matrix from the parity check matrix generation unit, searches the parity check matrix for a cycle forming group of four elements having a value of 1 respectively positioned at vertexes of a rectangle, and when a cycle forming group is found in the parity cheek matrix, generates an adjusted parity matrix without a cycle forming group therein by replacing the value of 1 of at least one element of the four elements of the cycle forming group with a value of 0, and replacing the value 0 of another element in the same row or the same column as the one element of the four elements with a value of 1; and a low-density parity-check (LDPC) coding unit that receives the adjusted parity check matrix from the parity check matrix adjustment unit, receives an m-bit message word, and performs LDPC coding of the m-bit message word based on the adjusted parity check matrix.