Patent ID: 7576806

Claim:
A thin film transistor array substrate, comprising: a substrate; a plurality of scan lines disposed over the substrate; a plurality of data lines disposed over the substrate, wherein the data lines and the scan lines form a plurality of pixel areas on the substrate; a plurality of common lines disposed over the substrate, wherein a portion of each common line is disposed in one of the pixel areas; and a plurality of pixel units disposed over the substrate, wherein each of the pixel units is disposed in one of the pixel areas and driven by one of the scan lines and one of the data lines corresponding thereto, and each of the pixel units comprises: a thin film transistor coupled to the scan line and the data line corresponding thereto; a patterned pixel electrode disposed over the common line corresponding thereto and coupled to the thin film transistor, wherein the pixel electrode has at least one slit; and a plurality of upper electrodes disposed between the pixel electrode and the common line corresponding thereto, a portion of at least one slit is across the common line corresponding thereto and across an area located between the upper electrodes, wherein the portion of the at least one slit is across two opposite sides of the area aligned with two opposite sides of each of the upper electrodes respectively, and is substantially not overlapped with the upper electrodes, each of the upper electrodes is coupled to the pixel electrode and forms a plurality of capacitors with the common line corresponding thereto to, and if at least one of the capacitors is defective, a portion of the pixel electrode corresponding to the defective capacitor is electrically isolated from the other portion of the pixel electrode.