Patent ID: 7847335

Claim:
A method of manufacturing a non-volatile semiconductor memory device, the method comprising: forming a gate stack on a substrate, the gate stack comprising a gate electrode having a top surface and a gate dielectric; forming an oxide-nitride-oxide stack over the gate stack, wherein the oxide-nitride-oxide stack comprises a first oxide layer, a nitride layer, and a second oxide layer; depositing a semiconductor layer over the oxide-nitride-oxide stack; removing portions of the semiconductor layer and the oxide-nitride-oxide stack to define semiconductor spacers adjacent the gate stack and over the substrate, the oxide-nitride-oxide stack being located between the semiconductor spacers and the gate stack, and being located between the semiconductor spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack; forming dielectric spacers, each dielectric spacer being immediately adjacent to a surface of one of the semiconductor spacers extending away from the substrate, and being immediately adjacent to a surface of the first oxide layer, the nitride layer, and the second oxide layer; etching back a portion of the oxide-nitride-oxide stack to form a recess between the gate electrode and the semiconductor spacers, wherein the recess is formed such that the first oxide layer, the nitride layer, and the second oxide layer each have a top surface that is below the top surface of the gate electrode; and forming a contact pad comprising forming a silicon layer having a metal silicide formed thereon, the contact pad being over and in electrical contact with the gate electrode and the semiconductor spacers, wherein the contact pad is adjacent to the dielectric spacers and substantially fills the recess.