Patent ID: 8103925

Claim:
A built-in self-test system in an integrated circuit device, comprising: a plurality of scan chains configured to capture test responses generated by testing an integrated circuit device; read-only memory circuitry configured to store a plurality of masking data sets and control information, the plurality of masking data sets comprising masking information; a first memory circuit configured to receive one of the plurality of masking data sets from the read-only memory circuitry based on the control information; a second memory circuit configured to receive the one of the plurality of masking data sets from the first memory circuit and to keep the one of the plurality of masking data sets for one or more clock cycles based on the control information; and masking circuitry configured outputs from one or more of the plurality of scan chains for the one or more clock cycles based on the one of the plurality of masking data sets stored in the second memory circuit.