Patent ID: 7590518

Claim:
A method for implementing a circuit design of a circuit using a reduced model of the circuit, comprising: selecting a parameter of the circuit; selecting a plurality of values for the selected parameter without reference to a nominal value of the selected parameter to model variation of a characteristic of a circuit feature in the circuit; solving an equation for the circuit with each of the selected plurality of values, thereby generating a corresponding result, in which the each of the selected plurality of values is used in forming a coefficient of the equation for the circuit; repeating the action of selecting and the action of solving for remainder of the selected plurality of values and, for each iteration of the action of selecting and the action of solving, determining whether a sufficient number of the corresponding result has been generated to form the reduced model; generating the reduced model from the corresponding result by using a processor and displaying the reduced model or storing the reduced model in a computer storage device, wherein the reduced model provides an accurately sized model which accounts for the variation of the characteristic of the circuit feature, and the variation comprises electrical or geometrical deviation of the characteristic from a target electrical or geometrical value due to fabrication or processing; and implementing the circuit design which is used for the fabrication or processing of the characteristic of the circuit feature by running a simulation on the reduced model.