Patent ID: 8385106

Claim:
A magnetic memory comprising: a plurality of memory array tiles (MATs), each of the plurality of MATs including a plurality of magnetic storage cells, a plurality of bit lines, and a plurality of word lines, each of the plurality of magnetic storage cells including at least one magnetic element and at least one selection device, the at least one magnetic element being programmable using at least one write current driven through the at least one magnetic element, the plurality of bit lines and the plurality of word lines corresponding to the plurality of magnetic storage cells; intermediate circuitry for controlling read operations and write operations within the plurality of MATs; a plurality of global bit lines, each of the global bit lines corresponding to a first portion of the plurality of MATs; a plurality of global write lines, each of the global write lines corresponding to a second portion of the plurality of MATs; and global circuitry for selecting and driving a portion of the plurality of global bit lines and a portion of the plurality of global write lines for the read operations and the write operations; wherein the intermediate circuitry further includes a plurality of intermediate drive/sense circuitry and local decoding circuitry, the plurality of intermediate driver/sense circuitry for driving at least one of read operations and write operations in the plurality of MATs, each of the plurality of intermediate drive/sense circuitry corresponding to a third portion of the plurality of MATs, the local decoding circuitry for selecting at least one selected MAT of the plurality of MATs and at least one of the storage cells in the at least one selected MAT.