Patent ID: 8633492

Claim:
A semiconductor device comprising: a gate electrode; a gate insulating film over the gate electrode; a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having an electrical conductivity lower than the first non-single crystalline oxide semiconductor layer; a source electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer; a drain electrode over and in electrical contact with the second non-single crystalline oxide semiconductor layer; and an insulating film comprising silicon over the second non-single crystalline oxide semiconductor layer, the source electrode and the drain electrode, wherein an upper surface of the second non-single crystalline oxide semiconductor layer includes a depression between the source electrode and the drain electrode so that a thickness of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second non-single crystalline oxide semiconductor layer below the source electrode and the drain electrode, and wherein the insulating film is in contact with the upper surface of the second non-single crystalline oxide semiconductor layer between the source electrode and the drain electrode.