Patent ID: 7424692

Claim:
A method for determining a worst-case single cycle setup time between a first and second clock domain comprising method operations of: normalizing an offset time of the second clock domain with respect to the first clock domain by subtracting a source clock offset time from a destination clock offset time; factoring a first greatest common denominator (FGCD) shared by the first and second clock domains and the normalized second clock domain offset time; substituting a reduced offset time and a reduced offset time size factor into an expression representing a relationship between the first and second clock domains, the reduced offset time size factor representing a number of times the reduced offset time is greater than a destination clock period; factoring a second greatest common denominator (SGCD) shared by the first and second clock domains from the expression, the factoring including computing a modulus value of the reduced offset time and the SGCD; and computing the worst-case single cycle setup time from the modulus value.