Patent ID: 7449363

Claim:
A fabrication method of a semiconductor package substrate with embedded chip, comprising the steps of: applying a first insulating layer on a surface of a metallic board, wherein the first insulating layer is formed with at least one opening for exposing a portion of the metallic board; providing at least one semiconductor chip having a plurality of electrode pads, and mounting the semiconductor chip on the portion of the metallic board exposed via the opening of the first insulating layer, wherein the semiconductor chip is mounted on the metallic board by a thermally conductive adhesive layer and the semiconductor chip is thicker than the first insulating layer; mounting a support plate on the first insulating layer, wherein the support plate is formed with a through cavity at a position corresponding to the opening of the first insulating layer, for receiving the semiconductor chip in the through cavity; applying a second insulating layer on the semiconductor chip and the support plate, and allowing insulating materials of the first and second insulating layers by heating pressing to bond together, and to fill a gap between the semiconductor chip and the support plate, wherein the second insulating layer and the first insulating layer are comprised of the same material; and performing a circuit patterning process to form a circuit layer on the second insulating layer applied on the semiconductor chip and the support plate so as to form conductive structures in the second insulating layer, such that the circuit layer is electrically connected to the electrode pads of the semiconductor chip by the conductive structures.