Patent ID: 7552286

Claim:
A system, comprising: a processor, wherein said processor has a cache associated with it; a system memory for storing data of said processor; a bus system coupling said processor to said system memory; wherein said cache comprises: a data array comprising a plurality of congruence classes, wherein each of said congruence classes groups a plurality of cache lines; a tag array comprising a plurality of tags, wherein each of said plurality of tags is associated with one of said plurality of cache lines, wherein each of said plurality tags comprises a bit used to indicate whether its associated cache line has been reused; logic for receiving a request of an address of data; logic determining if said requested data is located in said cache; logic for setting said bit in said tag associated with a cache line in a congruence class to a second state if said requested data is located within said cache line of said cache; and logic for resetting said bit for one of said plurality of cache lines in said congruence class if a number of cache lines in said congruence class identified as being reused exceeds a threshold.