Patent ID: 7560966

Claim:
A method of testing connectivity, comprising: (a) operating a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series with at least one multiplexer within the series receiving at least one clock signal as a selection input thereto for multiplexing parallel data into serial data, each of the CML latch circuits being operable to output a latched signal at a timing in accordance with the at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive; (b) activating the mode control devices of each of the CML latch circuits to operate each of the CML latches as a buffer amplifier; (c) applying a selection signal instead of the at least one clock signal to the selection input of the at least one multiplexer to select a first signal input to a first CML latch circuit in the series for propagation through a plurality of the CML latch circuits in the series operating as buffer amplifiers including a second CML latch circuit connected at a point in the series downstream from the first CML latch circuit; (d) latching a signal output by the second CML latch; and (e) determining whether the latched signal output by the second CML latch changes in accordance with a change in the first signal to determine whether there is a connection between the first and second CML latch circuits.