Patent ID: 7366024

Claim:
A method of operating a plurality of memory cells arranged in series, the series having a first end coupled to a first pass transistor and a bit line and a second end coupled to a second pass transistor and the bit line, each memory cell comprising a gate, source and drain regions in a substrate region, and including a top dielectric, a charge trapping structure having parts corresponding to the source and drain regions, and a bottom dielectric between the gate and the substrate region, the method comprising: selecting a memory cell in the plurality of memory cells; turning on one of the first pass transistor and the second pass transistor to permit electrical coupling of the bit line to the source region or the drain region of the selected memory cell, thereby selecting part of the charge trapping structure corresponding to the source region or the drain region; applying a first bias arrangement to determine a charge storage state of the selected part of the charge trapping structure, wherein the first bias arrangement applies a voltage difference between the substrate region and one of the source region or the drain region, and floats the other of the source region or the drain region; applying a second bias arrangement to adjust the charge storage state by increasing a net positive charge in the charge trapping structure; and applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure.