Patent ID: 7531906

Claim:
A semiconductor device assembly comprising: a wafer having an active surface and a back surface and including a plurality of unsingulated semiconductor dice, each of the semiconductor dice having a plurality of spaced conductive bumps on the active surface; and a wafer scale interposer superimposed on the wafer, having a first surface and a second, opposing surface and comprising a dielectric member, the wafer scale interposer including a plurality of unsingulated interposer substrates each of the plurality of unsingulated interposer substrates sized and aligned with one of the plurality of unsingulated semiconductor dice of the wafer, each of the plurality of unsingulated interposer substrates having a plurality of recesses opening onto the first surface and extending through the dielectric member to conductive terminals at recess bottoms proximate the second, opposing surface of the wafer scale interposer; wherein at least one of the plurality of spaced conductive bumps is substantially completely received in each recess of the plurality in conductive contact with a conductive terminal at a recess bottom.