Patent ID: 7547603

Claim:
A method of forming a semiconductor memory cell, comprising: forming a trench into a surface of a semiconductor substrate, wherein the substrate has a first conductivity type; forming first and second spaced-apart regions of a second conductivity type in the substrate with the first region formed underneath the trench, wherein a channel region is defined in the substrate between the first and second regions such that the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate; forming an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; forming an electrically conductive erase gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate; and forming an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion.