Patent ID: 8803332

Claim:
An integrated circuit structure comprising: a first die comprising at least one through-substrate via (TSV), the first die further comprising a first surface and a second surface opposite the first surface, the second surface having at least one redistribution line disposed thereon, the at least one TSV extending from the at least one redistribution line through the first die and above the first surface; a second die over and bonded to the first die, the first surface of the first die spaced apart from and facing the second die, the second die in electrical contact with the at least one TSV; a molding compound comprising a portion over the first die and the second die, wherein the molding compound contacts the first surface of the first die, and wherein the molding compound comprises a first portion extending below the first surface of the first die and further comprises a bottom surface that is about level with the second surface of the first die; at least one connector different from the at least one TSV and disposed on the second surface of the first die; and a package substrate underlying and bonded to the first die by the at least one connector, wherein the molding compound is spaced apart from the package substrate.