Patent ID: 7965708

Claim:
A packet processing system, comprising: a first storage buffer configured to store data packets containing headers with address or control fields used for directing transport of the data packets over a packet switched network; a second storage buffer configured to store packet fragments, wherein two or more of the packet fragments are combinable as a reassembled data packet that is capable of being transported over the packet switched network; a first packet queue configured to store the data packets or packet handles that identify where the data packets are located in the first storage buffer; a second packet queue configured to store meta-packets containing embedded sequences of meta-commands that are executable independently of the address and control fields contained in the packet headers and that comprise instructions for reassembling the packet fragments; a packet scheduler configured to output the data packets stored in the first packet queue together with the meta-packets stored in the second packet queue in a first sequential order corresponding with a same order that the data packets and the meta-packets are each separately stored in the first and second packet queues; a queuing system configured to process the data packets or packet handles and the meta-packets in the first sequential order received from the packet scheduler, wherein the queuing system is further configured, during processing of the meta-packets, to process the packet fragments stored in the second storage buffer to create the reassembled data packet, wherein the packet fragments are reassembled in a second sequential order identified by the embedded sequences of meta-commands contained in the meta-packets, and wherein the reassembled data packet replaces the meta-packets in the first sequential order; and an output port configured to output the data packets and the reassembled data packet in the first sequential order.