Patent ID: 8558334

Claim:
A semiconductor device having a multilayered wiring layer formed over a substrate, wherein a first layer contained in the multilayered wiring layer has: a first interlayer insulating film; and a plurality of first via holes buried in the first interlayer insulating film, and a plurality of first wirings buried in the first interlayer insulating film, connected with the first via holes, and exposed at the surface from the first interlayer insulating film, and wherein a second layer contained in the multilayered wiring layer and situated just over has, in a first region, an MRAM (magnetoresistive random access memory) having at least two first magnetization pinning layers in contact with the first wiring and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layer in a plan view and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layers situated over the non-magnetic layer; a second interlayer insulating film covering the MRAM; a second via hole buried in the second interlayer insulating film and connected with the second magnetization pinning layers; and a second wiring buried in the second interlayer insulating film, connected with the second via hole, and exposed at the surface from the second interlayer insulating film.