Patent ID: 7655535

Claim:
A method for fabricating a device isolation structure of a semiconductor device comprising: forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a dummy region, wherein a pattern in the dummy region is larger than a pattern in the cell region; etching a portion of the pad nitride layer, the pad oxide layer, and the semiconductor substrate to form a trench; forming a sidewall oxide layer over the pad nitride layer and the sidewalls of the trench; removing the sidewall oxide layer in the dummy region; forming a silicon nitride layer over the pad nitride layer and the sidewalls of the trench in the dummy region, and over the sidewalls of the sidewall oxide layer in the cell region; filling the trench with an insulating layer; polishing the insulating layer and the sidewall oxide layer on the pad nitride layer in the cell region, to expose the pad nitride layer, wherein the polishing is performed based on the pattern in the cell region; and removing the pad nitride layer.