Patent ID: 8575963

Claim:
An input buffer system, comprising: first inverter stage circuitry configured to invert an input digital signal that switches between states; and first current source circuitry comprising a first current source coupled between a first voltage rail and the first inverter stage circuitry, the first current source is configured to generate a first reference current to supply power to the first inverter stage circuitry, the first current source circuitry is further configured to limit a threshold current of the first inverter stage circuitry, wherein the first reference current limits a switching speed of the first inverter stage circuitry to a first switching speed; first enable/disable circuitry configured to provide a bypass path from the first voltage rail to the first inverter stage circuitry, wherein the bypass path bypasses the first current source circuitry; and wherein the first voltage rail provides a second reference current to supply power to the first inverter stage circuitry; wherein the first inverter stage circuitry switches at a second switching speed when powered by the second reference current; and wherein the second reference current is greater than the first reference current and wherein the second switching speed is greater than the first switching speed; second inverter stage circuitry coupled together in series with the first inverter stage circuitry, the second inverter stage circuitry is configured to invert an output of the first inverter stage circuitry; second current source circuitry coupled between the first voltage rail and the second inverter stage circuitry and configured to generate a third reference current to supply power to the second inverter stage circuitry, the second current source is further configured to limit a threshold current of the second inverter stage circuitry; wherein the third reference current limits a switching speed of the second inverter stage circuitry to a third switching speed; and second enable/disable circuitry configured to provide a bypass path from the first voltage rail to the second inverter stage circuitry, wherein the bypass path bypasses the second current source circuitry; and wherein the first voltage rail provides a fourth reference current to supply power to the second inverter stage circuitry; wherein the second inverter stage circuitry switches at a fourth switching speed when powered by the fourth reference current; and wherein the fourth reference current is greater than the third reference current and wherein the fourth switching speed is greater than the third switching speed.