Patent ID: 7091128

Claim:
A method for forming a CMOS device comprising the steps of: (a) providing a patterned gate stack on a surface of a semiconductor substrate, said patterned gate stack including gate dielectric below a gate conductor with exposed vertical sidewalls; (b) forming a dielectric layer over said gate region, exposed vertical sidewalls and substrate surfaces; (c) forming a vertical spacer element overlying said dielectric layer formed at each vertical sidewall, said vertical spacer element comprising a nitride layer; (d) removing said dielectric layer using an etch process such that a portion of said dielectric layer underlying each said vertical spacer element remains, an edge of said remaining portion of said dielectric layer underlying said vertical nitride spacer being aligned with an outer edge of said vertical nitride spacer element; (e) forming a thin nitride layer over said gate region, said vertical spacer elements, said edge of said portion of said dielectric layer underlying said vertical nitride spacer and said substrate surfaces; (f) etching said thin nitride layer to create a nitride plug layer that encapsulates and seals said vertical nitride spacers and said edge of said portion of said dielectric layer underlying said vertical nitride spacers; (g) performing a pre-silicide clean process for removing material remaining on said substrate and gate surfaces, wherein dielectric undercut during this clean process is prevented by the provision of said nitride plug layer encapsulating and sealing said edge of said portion of said dielectric layer underlying said vertical nitride spacers.