Patent ID: 8290734

Claim:
A semiconductor integrated circuit comprising: a data input circuit to receive a data input signal from outside and to output an output signal; a comparison value register to memorize an expectation value of the number of rising edges, the number of falling edges, or the number of rising edges and falling edges of the output signal of the data input circuit varying in accordance with the data input signal of the data input circuit; a clock input circuit to receive a first clock signal from outside to output a second clock signal; a first selector to selectively output the output signal of the data input circuit or the second clock signal; a holding circuit to hold the number of rising edges, the number of falling edges, or the number of rising edges and falling edges of an output signal of the first selector; a comparing circuit to compare the expectation value and the number held by the holding circuit; a second selector to selectively output the output signal of the data input circuit or an output signal of the holding circuit; and a logic circuit to receive the output signal of the second selector.