Patent ID: 8847638

Claim:
A divider comprising: a first differential latch disposed in a first integrated circuit, wherein the first differential latch comprises: a first output node; a second output node; a first N-channel transistor having a source, a drain, and a gate, wherein the drain of the first N-channel transistor is coupled to the first output node; a second N-channel transistor having a source, a drain, and a gate, wherein the source of the second N-channel transistor is coupled to the source of the first N-channel transistor, wherein the drain of the second N-channel transistor is coupled to the second output node; a first P-channel transistor having a source, a drain, and a gate, wherein the drain of the first P-channel transistor is coupled to the first output node, wherein the gate of the first P-channel transistor is coupled to the second output node; and a second P-channel transistor cross-coupled with the first P-channel transistor, the second P-channel transistor having a drain coupled to the second output node, a source coupled to the source of the first P-channel transistor, and a gate coupled to the first output node; and a first variable resistance element coupled between the first output node and the second output node, wherein the first variable resistance element has a first lead and a second lead and does not have any inductors, wherein the first lead is directly connected to the first output node and to the drain of the first N-channel transistor, wherein the second lead is directly connected to the second output node and to the drain of the second N-channel transistor, wherein the first variable resistance element receives a first multi-bit digital control signal supplied from a processor disposed in a second integrated circuit, wherein the first multi-bit digital control signal controls the first variable resistance element to at least in part determine an output resistance of the first differential latch, and wherein the output resistance of the first differential latch is changed based at least in part on digital control information sent across a serial bus from the second integrated circuit to the first integrated circuit.