Patent ID: 6960527

Claim:
A method for fabricating a non-volatile memory device, the method comprising: forming first and second vertical structures on first and second surface regions of a silicon substrate, each of the first and second vertical structures including a tunneling layer pattern, a charge trapping layer pattern, and blocking layer pattern sequentially stacked on the silicon substrate; forming a gate insulating layer on a third surface region of the silicon substrate which is interposed between the first and second surface regions of the silicon substrate; forming first and second gate spacers on respective surface portions of the gate insulating layer, the first gate spacer contacting an upper portion of a sidewall of the first vertical structure and protruding above an upper surface of the first vertical structure, and the second gate spacer contacting an upper portion of a sidewall of the second vertical structure and protruding above an upper surface of the second vertical structure; forming a gate forming conductive layer on exposed surfaces of the first and second vertical structures, the first and second gate spacers, and the gate insulating layer; etching the gate forming conductive layer to form first and second gate electrodes, wherein the first and second gate electrodes expose portions of the first and second vertical structures and the gate insulating layer; removing the portions of the first and second vertical structures and the gate insulating layer exposed by the first and second gate electrodes by performing an etching process using the first and second gate electrodes as an etch mask; and forming a source region and a drain region by implanting impurity ions in portions of the silicon substrate exposed by the first and second gate electrodes.