Patent ID: 7414907

Claim:
A semiconductor memory device comprising: a memory cell array which has a plurality of memory cells arranged in a matrix form; a plurality of bit line pairs which transfer data among the memory cells; a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs; a plurality of word lines connected to the memory cells; a plurality of wirings disposed respectively corresponding to the plurality of word lines and above the plurality of word lines; and a plurality of stitch portions which connect the plurality of word lines to the plurality of wirings every predetermined intervals, wherein two active areas in which the sense amplifier circuit is formed respectively in both sides of a stitch area corresponding to each of the stitch portions in the sense amplifier bank are connected to each other, and a dummy transistor is disposed on the connected active areas.