Patent ID: 8365000

Claim:
A computer system comprising: a main memory comprising a plurality of memory units; a power supply to supply power to the plurality of memory units; a controller to control the supply of power to the plurality of memory units so as to intercept power supplied from the power supply to at least one, but not all, of the plurality of memory units, according to a user selection input setting a low-power mode; a setting storage unit to store user setting information on the selection of the low-power mode by the user selection input; a switching unit to intercept the supply of the power to the at least one memory unit based on the control of the controller; and a plurality of termination units corresponding to the plurality of memory units to receive power from the power supply and in which power is intercepted from the power supply according to intercepted power of the corresponding at least one memory unit, and to perform impedance matching during data transmission, wherein the controller comprises a Central Processing Unit (CPU) to execute programs and perform operations and intercepts power supplied from the power supply to a least one termination unit corresponding to the at least one memory unit, and the plurality of memory units loads control programs comprising a Basic Input/Output System (BIOS) and an Operating System (OS) executed by the CPU, wherein the main memory comprises a Random Access Memory (RAM) and the plurality of memory units of the main memory are arranged in a dual channel architecture, wherein the setting information comprises setting values of the BIOS and the OS, and wherein the controller determines whether the low-power mode is selected in accordance with the setting information stored in the setting storage unit when the computer system is booted and controls the switching unit by setting a status of a GPO port provided in a south bridge to a predetermined status corresponding to the low-power mode, and the switching unit performs a switching operation to intercept the supply of power to the at least one memory unit according to the control signal output from the south bridge.