Patent ID: 7632711

Claim:
A semiconductor device fabrication method, comprising: providing a semiconductor wafer having a plurality of integrated circuit formation regions, each integrated circuit formation region including a circuit region in a central part thereof and a wiring region surrounding the circuit region; forming an integrated circuit, having a plurality of electrode pads, only in the circuit region of each of the plurality of integrated circuit formation regions, and forming a groove disposed between the circuit region and the wiring region; and selecting a type of package structure for the integrated circuits and performing a first fabrication process if the type of package structure selected is chip size packages, and performing a second fabrication process if the type of package structure selected is not chip size packages; wherein the wiring region is of sufficient width to receive therein external terminals and redistribution wiring extending to a corresponding circuit region to connect the external terminals to the electrode pads, wherein said first fabrication process includes for each integrated circuit formation region (a) forming first redistribution wiring, one end of which is connected to the electrode pads, in the circuit region, and forming second redistribution wiring, one end of which is connected to the electrode pads, at least a portion of the second redistribution wiring being disposed in the wiring region, (b) forming first external terminals, which are connected to the other end of the first redistribution wiring, in the circuit region, and forming second external terminals. which are connected to the other end of the second redistribution wiring, in the wiring region, (c) forming a sealing film which covers the circuit region and the wiring region such that the first external terminals and the second external terminals are exposed, and (d) completing the semiconductor device by dicing the semiconductor wafer along the outer edges of the wiring regions; wherein said second fabrication process includes for each integrated circuit formation region fabrication of semiconductor devices other than chip size packages, including (e) creating semiconductor chips by dicing the semiconductor wafer along the groove, and (f) completing the semiconductor devices by subjecting the semiconductor chips to predetermined packaging for the type of package structure selected, wherein the first fabrication process further includes forming passive elements for regulating the electrical characteristics of the second redistribution wiring in the wiring region. and wherein the passive elements include a capacitor.