Patent ID: 7285377

Claim:
A fabrication method for a damascene bit line contact plug, comprising the steps of: providing a semiconductor substrate having a first gate conductive structure, a second gate conductive structure and a source/drain region, in which the source/drain region is formed in the substrate between the first gate conductive structure and the second gate conductive structure; forming a first liner on the substrate; forming a first conductive layer in a space between the first gate conductive structure and the second gate conductive structure, in which the first conductive layer is electrically connected to the source/drain region; forming a second liner on the substrate to cover a top of the first conductive layer; forming an inter-layer dielectric with a planarized surface overlying the substrate to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure; forming a bit line contact hole in the inter-layer dielectric to expose the top of the first conductive layer; and forming a second conductive layer in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.