Patent ID: 7603488

Claim:
A system comprising: a plurality of memory units; a memory management subsystem configured to access the plurality of memory units in parallel and configured to dynamically allocate and deallocate storage space in each of the plurality of the memory units, wherein the memory management subsystem is configured to allocate memory randomly across the memory units and comprises a plurality of ports, the plurality of ports configured to be assessed in parallel and each port comprising: an instruction decoder configured to receive instructions and determine if the instruction is an allocate, deallocate or read/write instruction; an access state machine configured to implement a read or write access to the plurality of memory units; an allocate state machine configured to randomly pre-allocate a plurality of memory blocks across the plurality of memory units and to return a pointer to at least one of the randomly pre-allocated memory blocks memory in response to an allocate instruction; and a deallocate state machine configured to deallocate memory in response to a deallocate instruction; and a plurality of direct memory access (DMA) engines, each DMA engine associated with a port of the plurality of ports and configured to send instructions to its associated port, wherein the plurality of DMA engines are configured to write to the memory units in parallel utilizing the associated port of the plurality of ports, wherein the plurality of ports including at least a first port corresponding to a time division multiple access (TDMA) micro engine and a second port corresponding to a first-in-first-out (FIFO) micro engine, wherein, during a transmit operation, the FIFO micro engine reads data to be sent and writes the data to a first FIFO in the memory using the second port and the TDMA micro engine reads the data from the first FIFO in the memory using the first port, wherein at least a portion of the writing of data to the first FIFO and the reading of data from the first FIFO takes place in parallel, and during a receive operation, the TDMA micro engine reads received data and writes the data to a second FIFO in the memory using the first port and the FIFO micro engine reads the data from the second FIFO in the memory using the second port wherein at least a portion of the writing of data to the second FIFO and the reading of data from the second FIFO takes place in parallel.