Patent ID: 7572689

Claim:
A method of relieving stresses in stressed semiconductor liners comprising: providing a semiconductor structure having a first FET and a second FET; providing a single stress liner, wherein when said second FET comprises an NFET and said first FET comprises a PFET on an (001) oriented silicon surface said single stress liner comprises a single compressive stress liner for enhancement of said PFET and when said first FET comprises an NFET and said second FET comprises a PFET on an (011) oriented silicon surface said single stress liner comprises a single tensile stress liner for enhancement of said NFET; depositing said single stress liner over an entire surface of said semiconductor structure to cover said first and second FETs; depositing a disposable layer over said single stress liner, said disposable layer comprises a material selected from the group consisting of an antireflective coating, spin-on glass, photoresist, reflowable oxides, reflow-able acrylic, and the like; recessing said disposable layer, while protecting said first FET, to expose only the upper portion of said single stress liner over at least said second FET; removing said exposed single stress liner from over at least said second FET, while protecting said first FET, to expose a top surface of a gate of said second FET; removing any remaining portions of said disposable layer; and depositing a neutral stress liner over said surface of said semiconductor structure, thereby enhancing performance of said first FET while avoiding degradation of said second FET.