Patent ID: 8189729

Claim:
Wide range clock data recovery (CDR) circuitry comprising: means for receiving a CDR data signal; means for receiving a reference clock signal; means for dividing the reference clock signal by a first user-programmable value to produce a divided reference clock signal; means for dividing a first feedback clock signal to phase detector circuitry by a second user-programmable value; means for further dividing the first feedback clock signal by a third user-programmable value to produce a second feedback clock signal to phase frequency detector circuitry, wherein the means for further dividing is coupled to the means for dividing the first feedback clock signal; means for applying the divided reference clock signal to the phase frequency detector circuitry for comparison to the second feedback clock signal; means for outputting a clock signal recovered from the CDR data signal; and means for reconfiguring the CDR circuitry by changing at least one of the first, second, and third user-programmable values without powering down the CDR circuitry, but with resetting the phase detector circuitry and the phase frequency detector circuitry, wherein the phase detector circuitry and the phase frequency detector circuitry are distinct and coupled to a reset signal that is asserted when reconfiguring the CDR circuitry, without resetting circuitry within the CDR circuitry other than the phase detector circuitry and the phase frequency detector circuitry.