Patent ID: 8442096

Claim:
A system for identifying a scrambling code in received signals comprising: a first plurality of heterogeneous computational elements, each of the computational elements performing an arithmetic operation; a switchable interconnection network coupled to the first plurality of heterogeneous computational elements to configure the first plurality of heterogeneous computational elements as a scrambling code generator generating a plurality of segments forming a plurality of sequential chips of a master scrambling code, the configuration performed by switching the interconnections between the first plurality of heterogeneous computational elements; a second plurality of heterogeneous computational elements, each of the computational elements performing an arithmetic operation and each coupled to the interconnection network, the second plurality of heterogeneous computational elements configured as a plurality of correlators configured to correlate in parallel the received signals with corresponding segments, a first correlator of the plurality of correlators configured to receive a next corresponding segment generated by the scrambling code generator, each remaining correlator of the plurality of correlators configured to receive its next corresponding segment from another correlator of the plurality of correlators, the configuration performed by switching the interconnections between the second plurality of heterogeneous computational elements.