Patent ID: 7173466

Claim:
A timing signal generating circuit which receives multi-phase input signals via a plurality of input buffers and generates a signal having a phase intermediate therebetween, wherein weighting is applied to said multi-phase input signals by using a variable impedance circuit, each of said input buffers comprising a plurality of stages of electronic elements between a high potential power supply line and a low potential power supply line, said variable impedance circuit comprising a plurality of variable impedance units one for each of said multi-phase input signals, each of said variable impedance units including at least one transistor without providing vertically stacked transistors between the high potential power supply line and the low potential power supply line, and without increasing a number of stages of electronic elements between the high potential power supply line and the low potential power supply line of said input buffers, wherein the at least one transistor of each of said variable impedance units includes a first, a second, and a control electrode, said each input signal is received at said first electrode and output at said second electrode, and impedance is controlled by controlling a voltage applied to said control electrode, wherein each of said variable impedance units comprises a plurality of variable impedance parts that include said at least one transistor, and wherein said variable impedance parts are arranged to form a plurality of variable impedance groups.