Patent ID: 8238175

Claim:
A semiconductor device comprising: a clock terminal to which a clock signal is supplied; a data strobe terminal to which a data strobe signal that indicates an input timing of write data is supplied; a mode register which can be set as a normal operation mode of receiving the write data synchronously with the data strobe signal and as a write leveling mode of measuring a skew between the clock signal and the data strobe signal; a terminating resistance circuit connected to the data strobe terminal; a command terminal to which an ODT (On-Die Termination) signal that designates whether to activate the terminating resistance circuit is supplied; a skew detecting circuit that is activated in the write leveling mode, measures a skew between the clock signal and the data strobe signal, and outputs a result of measuring; and an ODT control circuit that includes a counter circuit that delays the ODT signal by counting the clock signal or an internal clock signal synchronous with the clock signal for a predetermined number of times, activates the terminating resistance circuit by using the ODT signal having passed the counter circuit in the normal operation mode, and activates the terminating resistance circuit by using the ODT signal having bypassed the counter circuit in the write leveling mode.