Patent ID: 7629210

Claim:
A method of fabricating a semiconductor integrated circuit device comprising the steps of: (a) within a substrate layer, simultaneously forming a first conductivity type well of a second conductivity type MOS transistor for an inner circuit and a first conductivity type collector connection well to be connected with a collector of a vertical bipolar transistor on a second conductivity type semiconductor substrate; (b) using ion implantation into the substrate layer, forming a first conductivity type collector well to be a collector of said vertical bipolar transistor; (c) using ion implantation into the substrate layer, forming a second conductivity type layer to be a base in the first conductivity type collector well of said vertical bipolar transistor; (d) using ion implantation into the substrate layer, simultaneously forming a first conductivity type layer to be a collector connection in the first conductivity type collector connection well of said vertical bipolar transistor, and a first conductivity type layer to be an emitter in the second conductivity type layer of said vertical bipolar transistor; (e) using ion implantation into the substrate layer, simultaneously forming a second conductivity type source/drain layer on the first conductivity type well of said second conductivity type MOS transistor, and a second conductivity type base contact layer on the second conductivity type layer of said vertical bipolar transistor; and (f) using ion implantation into the substrate layer, forming a first conductivity type layer between said first conductivity type collector connection well and said first conductivity type layer to be a collector connection so as to alleviate a high intensity of electric field between said first conductivity type collector connection well and said first conductivity layer collector connection.