Patent ID: 8488731

Claim:
A slicing level and sampling phase adaptation circuitry for data recovery systems, comprising: a slicing level adjustment element, receiving a processed data and frequency division signals and comparing the processed data and the frequency division signals for generating a phase difference, wherein the phase difference being fed back to an input of the slicing level adjustment element to rectify the processed data; a sampling period adjustment element, receiving the processed data and time division signals and comparing the processed data and the time division signals for a timing margin, wherein the timing margin is fed back to the input of the sampling period adjustment element to adjust the frequency division signals and then becoming the time division signals; and a clock and data recovery loop, receiving the processed data and recovering system clock signals from the processed data, wherein the system clock signals are transferred to next stage circuitry and wherein the clock and data recovery loop receives the timing margin for the adjustment of system clock signals, and the system clock signals are transferred to the slicing level adjustment element and the sampling period adjustment element.