Patent ID: 8653866

Claim:
A semiconductor device, comprising: a control voltage generating block configured to generate a control voltage, at a control voltage node, corresponding to a phase difference between a reference clock signal and an internal clock signal; a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to the control voltage node when exiting from the low power mode; and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage, wherein the control voltage restoring block comprises: a control signal generating sector configured to generate first and second control signals that are enabled based on timing points of entering into and exiting from the low power mode, respectively; and a voltage restoring sector configured to store the control voltage as the restoring voltage in response to the first control signal and to supply the restoring voltage directly to the control voltage node in response to the second control signal.