Patent ID: 7217978

Claim:
An SRAM array comprising a plurality of SRAM cells, each of said SRAM cells comprising: a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET; a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and where at least two adjacent NFETs of the SRAM cell share a leakage path between body regions, and where at least two adjacent NFETs have a source/drain diffusion region and a leakage path diffusion region under the source drain diffusion region positioned between their respective body regions, wherein the source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions.