Patent ID: 8116306

Claim:
A shared memory system comprising: a shared memory including a plurality of memory banks for storing data, each of the memory banks including a plurality of divided portions of memory blocks, the memory blocks including a set of divided portions across the memory banks; a plurality of input ports for transferring a plurality of streams of data from an exterior of the shared memory system, respectively; a plurality of input buffers for receiving the plurality of the streams of data transferred from the plurality of the input ports, respectively; and a controller for controlling writing-into and reading out of the shared memory and for transferring data from each of the input buffers to the shared memory, said controller writing a series of data received from each of the input buffers into the memory banks around word by word sequentially and cyclically in one of the memory blocks from one of the memory banks designated as a starting memory bank toward the end of the series of data, wherein when selected one of the memory banks for writing one of the words in the series of data is cycled back next to the starting memory bank, another memory block is to be selected next for writing the remainder of the series of data, said controller controlling each of the input buffers to transfer a plurality of series of data to the shared memory successively with a time gap while switching to said another memory block, said controller offsetting a start memory bank in said another block for start writing the remainder of the series of data by an amount of memory banks corresponding to the time gap.