Patent ID: 8658474

Claim:
A process of forming an integrated circuit, comprising the steps of: forming a lower conductive structure; forming a vertical interconnect by a process further including the steps of: forming at least one dielectric pillar on a top surface of said lower conductive structure; forming a region of interconnect metal, such that said interconnect metal continuously surrounds each said at least one dielectric pillar, every location in said interconnect metal region is within a desired maximum horizontal distance from a boundary of said interconnect metal, and said interconnect metal electrically contacts said lower conductive structure, wherein said boundary includes edges of said interconnect metal region and perimeters of said pillars. wherein a top surface of said interconnect metal and a top surface of each said at least one dielectric pillar are substantially coplanar; and forming an upper conductive structure, said upper conductive structure contacts a top surface of said vertical interconnect.