Patent ID: 8260955

Claim:
A system, comprising: a first interface circuit including: first transmitting means, including amplification means, for transmitting a first signal as a first differential signal to a second interface circuit through a transmission line; and second transmitting means, including first addition means, for transmitting a second signal, being multiplexed to the transmission line, as a common-mode signal to the second interface circuit, the first addition means for receiving the first differential signal from the amplification means and outputting the second signal for transmission; a first communication circuit that communicates with the second interface circuit via a pair of differential transmission lines included in the transmission line, wherein the first communication circuit includes a circuit for biasing the transmission line to a first voltage level to indicate a connection to the transmission line, thereby notifying the second interface circuit of a connection status of its own device by at least one of direct current bias potentials of the pair of differential transmission lines; the second interface circuit including: first receiving means for extracting the first signal from the first differential signal received from the first interface circuit through the transmission line, the first receiving means comprising second addition means for adding the extracted first signal to an inverted signal; second receiving means for extracting the second signal from the common-mode signal received from the first interface circuit through the transmission line, the second receiving means comprising third addition means for extracting the common-mode signal by adding a second differential signal and a third differential signal; and a second communication circuit that communicates with the first interface circuit via the pair of differential transmission lines included in the transmission line, wherein the second communication circuit receives a notification of the connection status from the first interface circuit by at least one of the direct current bias potentials of the pair of differential transmission lines.