Patent ID: 8604954

Claim:
A timing calibration circuit for a time-interleaved analog-to-digital converter (ADC), comprising: a correlation unit, coupled to a first ADC, a second ADC and a third ADC, the first ADC, the second ADC and the third ADC respectively outputting a first digital data, a second digital data and a third digital data; the correlation unit generating a first correlation coefficient according to a first zero-crossing possibility distribution between the first digital data and the second digital data, and generating a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and the third digital data; an adaptive filter, coupled to the correlation unit, for generating a predicted time skew according to a coefficient variance between the first correlation coefficient and the second correlation coefficient; and a delay cell, coupled to the adaptive filter, for calibrating a clock signal of the second ADC according to the predicted time skew.