Patent ID: 8706964

Claim:
A non-transitory computer-readable memory device that stores instructions, the instructions comprising: one or more instructions that, when executed by a processor, cause the processor to: receive cache conditions and data of a software application; determine related sections of code of the software application; receive an input, the input specifying: one or more particular related sections of code of the software application, and specific cache conditions; determine a cache management scheme based on the cache conditions; align the determined related sections of the code and the particular related sections of the code based on the cache management scheme to create aligned code; group that aligned code into one or more first sections; distribute the grouped code into one or more second sections in a memory; receive information regarding a section of the one or more second sections, the information being based on: a size of the section, and a frequency of access of the section; and lock, based on the received information, the section in a cache for a particular period of time.