Patent ID: 8120026

Claim:
A testing wiring structure of a thin film transistor (TFT) array motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard, comprising a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring, the gate layer metallic testing wiring being connected to a portion of the plurality of signal lines, and the drain layer metallic testing wiring being connected to remaining portion of the plurality of signal lines, wherein a pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring, and the pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring.