Patent ID: 8030150

Claim:
A non-volatile memory integrated circuit device comprising: a substrate in which a cell array region and a peripheral circuit region are defined by a device isolation region; a plurality of first and second stacked gate structures formed in the cell array region, the first and second stacked gate structures each having a structure in which a lower structure, a conductive pattern and a damascene metal layer pattern are stacked, the first and second stacked gate structures being formed so that a first pitch between neighboring first stacked gate structures, and a second pitch between neighboring first and second stacked gate structures are narrower than a third pitch between neighboring second stacked gate structures; a plurality of junction regions formed in the cell array region exposed by the first and second stacked gate structures; a plurality of spacers formed on side walls of the first and second stacked gate structures, the spacers being formed so that spacers between the first stacked gate structures are connected to each other and spacers between the first and second stacked gate structures are connected to each other, but spacers between the second stacked gate structures are separated from each other; and a stop layer formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.