Patent ID: 8549458

Claim:
A computer implemented method for routing an electronic circuit design manufactured with sidewall image transfer processes that is correct by construction, the method implemented with at least one processor, the method comprising: using the at least one processor of a computing system to perform a process, the process comprising: identifying an object which is to be physically implemented in a layout of the electronic circuit design; and generating a physical implementation including placement or routing for the object that is correct by construction based at least in part upon a number of regions adjacent to a sidewall and whether the number of regions intersects a core polygon or a non-core polygon by at least identifying a possible placement for the object in the layout and determining whether the possible placement for the object in the layout creates a manufacturing conflict with sidewall image transfer manufacturing techniques for the object when the object is to be manufactured with the sidewall image transfer manufacturing techniques, wherein the layout is modified to resolve the manufacturing conflict with the sidewall image transfer manufacturing techniques if the manufacturing conflict is determined to exist during the physical implementation for the object, and the physical implementation for the object is correct by construction in that the process disallows physical implementations that lead to unsuccessful manufacturing of the object with a sidewall image transfer technique upon completion of the physical implementation for the object.