Patent ID: 7528446

Claim:
A semiconductor substrate comprising: a singlecrystalline Si substrate which includes an active layer having a substance implanted into the singlecrystalline Si substrate for adjustment of a threshold voltage in an N-type or P-type channel region, said active layer having a channel region, a source region, and a drain region, wherein the source region and the drain region have the impurity implanted selectively due to an arbitrary type of MOS transistor; the semiconductor substrate not including a well-structure or a channel stop region for the active layer irrespective of the type of MOS transistor so that the active layer is directly adjacent to an intact part of the singlecrystalline Si substrate; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film, wherein: an ion implantation layer is formed in the singlecrystalline Si substrate with a predetermined depth, the ion implantation layer including one or plural kinds of implanted ion selected from a hydrogen ion group or an inactive element ion group.