Patent ID: 8236628

Claim:
A method of manufacturing an array substrate, comprising: forming a data line and a gate line which are crossed with each other and a gate electrode on a base substrate, and the data line is discontinuously disposed so as to be separated from the gate line or the gate line is discontinuously disposed so as to be separated from the data line; forming an active layer and a gate insulating layer including bridge via holes and a source electrode via hole on the base substrate, and the bridge via holes are located at positions respectively corresponding to adjacent discontinuous sections of the data line or adjacent discontinuous sections of the gate line, and the source electrode via hole is located at a position corresponding to the data line; and forming a pixel electrode, a source electrode, a drain electrode and a bridge line on the base substrate, and the pixel electrode and the drain electrode are formed integrally, and the source electrode is connected to the data line through the source electrode via hole, and the bridge line connects the adjacent discontinuous sections of the data line or the adjacent discontinuous sections of the gate line through the bridge via holes.