Patent ID: 8537625

Claim:
A circuit comprising: a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising: a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; a regulating transistor having a first current terminal coupled to the regulated node and a second current terminal coupled to a power supply node; an operational amplifier circuit including an inverting input coupled to the reference node, a non-inverting input coupled to the regulated node, and an output coupled to a control terminal of the regulating transistor.