Patent ID: 6916675

Claim:
A method of fabricating an array substrate for use in an IPS-LCD device, comprising: depositing a first metallic material on a substrate; patterning the first metallic material to form a first gate electrode, a first gate line, a first common line, and a plurality of protrusions, wherein each protrusion has a hole in a central portion thereof and extends from the first common line, and wherein the first gate electrode extends from the first gate line; depositing a second metallic material on the substrate and on the patterned first metallic material; patterning the second metallic material to form a second gate electrode, second gate line, second common line, a common-connecting line, and a plurality of common electrodes, wherein the first and second gate electrodes overlap each other to form a double-layered gate electrode, wherein the first and second common lines overlap each other to form a double-layered common line, and wherein the first and second gate lines overlap each other to form a double-layered gate line; forming a gate insulation layer on the substrate and on the patterned second metallic material; forming an active layer and an ohmic contact layer sequentially on the gate insulation layer and over the double-layered gate electrodes; depositing a third metallic material on the ohmic contact layer and on the gate insulation layer; forming a data line, a source electrode, and a drain electrode by patterning the third metallic material, wherein the source and drain electrodes are over the double-layered gate electrodes, and wherein the data line is perpendicular to both the double-layered gate lines and double-layered common lines; forming a passivation layer on the patterned third metallic layer and on the gate insulation layer, wherein the passivation layer has a drain contact hole to the drain electrode, and an etching hole over each protrusion; depositing a transparent conductive material on the passivation layer having the drain contact hole and the etching hole; and forming a plurality of pixel electrodes and first and second connecting lines.