Patent ID: 8741723

Claim:
A method, comprising: forming gate structures for first and second spaced-apart transistors above a semiconducting substrate; forming an etch stop layer above said substrate and said gate structures for said transistors; performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of said etch stop layer, wherein performing said at least one angled ion implant process to implant said at least one etch-inhibiting species comprises performing a first ion implant process using one of carbon or fluorine and performing a second ion implant process using the other of said carbon or fluorine; after performing said at least one angled ion implant process, forming a layer of insulating material above said etch stop layer; performing at least one first etching process to define an opening in said layer of insulating material and thereby expose a portion of said etch stop layer; performing a second etching process on said exposed portion of said etch stop layer to define a contact opening therethrough that exposes a doped region formed in said substrate; and forming a conductive contact in said opening that is conductively coupled to said doped region.