Patent ID: 6882558

Claim:
A method of operating a ferroelectric-type nonvolatile semiconductor memory comprising a memory unit having; (A) a bit line, (B) a transistor for selection, (C) a sub-memory unit composed of memory cells that are M (M≧2) in number, (D) plate lines that are M in number, and (E) a sense amplifier connected to the bit line, wherein each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, the first electrodes of the memory cells constituting the sub-memory unit are in common with the sub-memory unit, said common first electrode is connected to the bit line through the transistor for selection, and each second electrode is connected to each plate line, said method comprising reading out data stored in the memory cell at a designated address externally designated, latching said data in the sense amplifier, and then outputting said data latched in the sense amplifier, wherein after said data latched in the sense amplifier is outputted, said data latched in the sense amplifier is re-written into said memory cell at said designated address, and then data stored in other memory cell constituting the sub-memory unit is read out without external addressing and is latched in the sense amplifier.