Patent ID: 7269714

Claim:
An apparatus comprising: an integer pipeline to process integer instructions; a floating point pipeline to process short latency and long latency floating point instructions in which both short and long latency floating point instructions generate exceptions, wherein the floating point pipeline has a greater number of pipeline stages to process floating point instructions than a number of pipeline stages to process integer instructions in the integer pipeline; and a control circuit coupled to the integer and floating point pipelines to inhibit co-issuance of an integer instruction to the integer pipeline when the integer instruction is subsequent to a first floating-point instruction in program order, until the first floating point-instruction reaches a stage in the floating-point pipeline where exceptions are to be generated to ensure that the integer instruction does not graduate from the integer pipeline prior to exception determination for the first floating point instruction in the floating-point pipeline, the control circuit to also inhibit co-issuance of a second floating-point instruction that follows the first floating-point instruction in program order, if the first floating-point instruction is a long latency floating-point instruction, to ensure that the second floating-point instruction does not graduate prior to the exception determination for the first floating point instruction, but not to inhibit the second floating-point instruction from co-issuance if the first floating-point instruction is a short latency floating-point instruction, since the second floating-point instruction will not graduate prior to the exception determination for the first floating-point instruction.