Patent ID: 7325123

Claim:
An integrated circuit, comprising: a first plurality of computational elements, at least one computational element of the first plurality of computational elements having a fixed architecture; a first interconnection network coupled to the first plurality of computational elements and adapted to configure the first plurality of computational elements for a first data operation of a plurality of data operations, in response to first configuration information; a first memory element coupled to the first interconnection network and adapted to store the first configuration information; a second plurality of computational elements, at least one computational element of the second plurality of computational elements having a fixed architecture; a second interconnection network coupled to the second plurality of computational elements arid adapted to configure the second plurality of computational elements for a second data operation of the plurality of data operations, in response to second configuration information; a second memory element coupled to the second interconnection network and adapted to store the second configuration information; a processor element; and a third interconnection network adapted to selectively transfer data or control between or among the first and second pluralities of computational elements and the processor element.