Patent ID: 8086870

Claim:
A method for improving the efficiency of a hardware-based cryptographic accelerator, comprising: receiving in the hardware-based cryptographic accelerator an unnormalized data block containing unnormalized data, wherein the unnormalized data block has a first number of sub-blocks, wherein the most significant bit in the unnormalized data is a zero; mapping the bits in the unnormalized data block to a normalized data block having a second number of sub-blocks such that a leading one in the unnormalized data is located at a most significant bit position in the normalized data block, wherein the mapping includes: writing data in the unnormalized data block into the normalized data block in an unnormalized sub-block by unnormalized sub-block basis, starting with a least significant sub-block, wherein a least significant bit in the least significant sub-block of the unnormalized data block is written to an Xth position within an Nth sub-block of the normalized data block, wherein the Xth position is determined based on a number of bits following the leading one in a sub-block of the unnormalized data containing the leading one; storing data identifying a bit position of the leading one in the unnormalized data; and performing cryptographic processing on the normalized data block to generate a normalized processed block.