Patent ID: 6960792

Claim:
A silicon controlled rectifier structure comprising: a semiconductor material of a first conductivity type having a top surface and a dopant concentration; a first well of a second conductivity type formed in the semiconductor material, the first well contacting the top surface of the semiconductor material and having a dopant concentration; a first semiconductor region of the first conductivity type formed in the first well, the first semiconductor region having a greater dopant concentration than the dopant concentration of the semiconductor material; a second semiconductor region of the second conductivity type formed in the first well, the second semiconductor region having a greater dopant concentration than the dopant concentration of the first well; a third semiconductor region of the first conductivity type formed in the semiconductor material, the third semiconductor region contacting the first well and the semiconductor material, being spaced apart from the first and second semiconductor regions, and having a greater dopant concentration than the dopant concentration of the semiconductor material; a second well of the second conductivity type formed in the semiconductor material, the second well contacting the top surface of the semiconductor material, and being spaced apart from the first well; a fourth semiconductor region of the first conductivity type formed in the semiconductor material, the fourth semiconductor region contacting the top surface of the semiconductor material, the second well, and the semiconductor material, and having a greater dopant concentration than the dopant concentration of the semiconductor material; and a fifth semiconductor region of the first conductivity type formed in the second well, the fifth semiconductor region contacting the top surface of the semiconductor material, being spaced apart from the fourth semiconductor region, and having a greater dopant concentration than the dopant concentration of the semiconductor material, a shortest distance between the second and third semiconductor regions being less than a shortest distance between the fourth and fifth semiconductor regions.