Patent ID: 8352534

Claim:
An integer division circuit with an allowable error, comprising: a pointer, for searching for a most significant non-zero bit of a divisor and outputting a most significant byte value; a first left shifter, electrically connected to the pointer, for performing a shift operation according to the most significant byte value, so as to generate a first exponential coefficient; a second left shifter, electrically connected to the pointer, for performing a shift operation according to the most significant byte value, so as to generate a second exponential coefficient; a subtractor, electrically connected to the first left shifter and the second left shifter, for performing a weight adjustment procedure according to the divisor, the first exponential coefficient, and the second exponential coefficient, so as to output a multiplier factor; a multiplier that receives a dividend value; and a right shifter, for performing an exponent right shift operation on an output result of the multiplier by using the most significant byte value, so as to output a quotient value with the allowable error, wherein the multiplier is connected between the subtractor and the right shifter, the multiplier multiplying the multiplier factor with the dividend value and outputting a multiplication result to the right shifter for the exponent right shift operation.