Patent ID: 8258806

Claim:
A method of testing functional circuit blocks of an integrated circuit, the functional circuit blocks having circuit components fabricated in surface layers of a semiconductor substrate and metal interconnects fabricated in layers above the substrate; the method comprising: providing IC functional circuit blocks in modified form with respective continuity paths of conductive elements having first elements and last elements, such that passing electrical current from the first element to the last element will result in current flowing through every element in the continuity path; and also including respective isolation features which separate the conductive elements of the interconnects; and providing a test structure having: test circuit blocks comprising sets of multiple duplicate instances of the modified functional circuit blocks including duplications of the continuity paths and isolation features; continuity interconnect links and serpentine interconnect links connecting the duplicated continuity paths of the respective duplicated blocks in a serial manner with the last element of the continuity path of one duplicated block being connected to a first element of the continuity path of a next duplicated block, thereby forming a continuity chain of the individual continuity paths of the duplicated blocks; a first parallel isolation bus conductor electrically connected to first conductive elements on first sides of the duplicated isolation features; and a second parallel isolation bus conductor electrically connected to second conductive elements on second sides of the duplicated isolation features, electrically isolated from the first conductive elements; the first and second parallel isolation buses defining a parallel isolation test circuit for the isolation features; measuring electrical resistance between ends of the continuity chain to provide an assessment of a level of open circuit defects that can be expected to occur in the functional circuit blocks in the integrated circuit; and measuring electrical isolation between terminals of the first parallel isolation bus conductor and the second parallel isolation bus conductor to provide an assessment of a level of short circuit defects that can be expected to occur in the functional circuit blocks in the integrated circuit.