Patent ID: 8088681

Claim:
A method for fabricating an integrated circuit, comprising: fabricating a substrate region that forms part of a substrate of the integrated circuit; fabricating a first active region within the substrate region; fabricating a second active region within the substrate region; fabricating a gate electrode level region over the substrate region, wherein the gate electrode level region is part of a gate electrode level of the integrated circuit, wherein fabricating the gate electrode level region includes: fabricating first, second, third, and fourth gate electrodes to extend lengthwise in a first direction over the first active region to respectively foam first, second, third, and fourth transistors of a first transistor type that are electrically connected in a serial manner, wherein the first, second, third, and fourth gate electrodes are the only gate electrodes fabricated to extend over the first active region, and fabricating fifth, sixth, seventh, and eighth gate electrodes to extend lengthwise in the first direction over the second active region to respectively form first, second, third, and fourth transistors of a second transistor type that are electrically connected in a serial manner, wherein the fifth, sixth, seventh, and eighth gate electrodes are the only gate electrodes fabricated to extend over the second active region, and wherein the first active region is separated by a non-active portion of the substrate from any other active region of the substrate that forms another transistor of the first transistor type, and wherein the second active region is separated by a non-active portion of the substrate from any other active region of the substrate that forms another transistor of the second transistor type, and wherein the first gate electrode and the fifth gate electrode are fabricated as respective portions of a first linear conductive segment within the gate electrode level region, and wherein the fourth gate electrode and the eighth gate electrode are fabricated as respective portions of a second linear conductive segment within the gate electrode level region.