Patent ID: 6920519

Claim:
An input/output system comprising: a host bridge connected by a bus to I/O adapters; a plurality of input/output hub nodes; means for subdividing address space for said bus among said plurality of input/output hub nodes; a translation table containing a plurality of translation table entries at each of a plurality of said hub nodes; a translation table entry in said translation table containing a hub ID field for determining which of said hub nodes is to receive a data transfer from said host bridge; means for routing of data from an I/O device to one hub node using said hub ID field from said translation table entry while accessing said translation table entry at another hub node using said means for subdividing address space; a plurality of registers containing a hub ID field and a system memory address field; an address associated with said bus originating from said I/O adapter; means responsive to said means for subdividing address space for selecting one of said plurality of registers; means responsive to said hub ID field from said selected register for determining which hub node to use for accessing said translation table entry; and means for combining said system memory address field from said selected register with a portion of said address for determining a system memory address of said translation table entry in said hub node.