Patent ID: 6998302

Claim:
A method for fabricating a transistor in a semiconductor device, comprising: forming an isolation region in a semiconductor substrate and sequentially depositing a pad oxide layer, a pad nitride layer and a first oxide layer on the substrate and the isolation region; pattering the first oxide layer and pad nitride layer to form a gate electrode opening; depositing a doped poly silicon layer over the whole semiconductor substrate including the opening; etching back the doped poly silicon layer until the pad oxide layer is exposed to form a doped polysilicon sidewall in contact with a sidewall of the pad nitride layer and the first oxide layer, wherein the doped polysilicon sidewall is used to serve as the lightly doped drain (LDD) implantation; etching the pad oxide layer exposed by the doped polysilicon sidewall to expose the semiconductor substrate; forming a gate isolation layer thinner than the thickness of the pad oxide layer and in contact with the pad oxide layer on the exposed semiconductor substrate; sequentially depositing and planarizing a gate nitride layer covering the gate isolation layer and the doped polysilicon sidewall, and a metal layer on the whole substrate to form the gate electrode; and forming a source, a drain, a gate plug, a source plug and a drain plug, respectively.