Patent ID: 8765599

Claim:
A method of fabricating a semiconductor device structure including a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate, the method comprising: forming a first layer of a first dielectric material overlying the doped region; forming a third layer of a third dielectric material overlying the first layer; forming a voided region in the first layer and the third layer, wherein the voided region is bounded and contacted by edges of the first layer and third layer; forming a first conductive contact in the voided region within the first layer and in contact with the edges of the first layer and third layer, the first conductive contact being electrically connected to the doped region; forming a dielectric cap in the voided region within the third layer, on the first conductive contact, and in contact with the edges of the third layer; forming a second layer of a second dielectric material overlying the gate structure and the dielectric cap; and forming a second conductive contact within the second layer, the second conductive contact being electrically connected to the gate structure.