Patent ID: 8129226

Claim:
A method for making a package assembly comprising: providing a carrier substrate having a plurality of reference voltage terminal package landing pads and a plurality of signal line package landing pads formed on a first surface of the carrier substrate; attaching an integrated circuit die to the first surface of the carrier substrate where the integrated circuit die comprises an active surface having a plurality of die level reference voltage supply terminals and a plurality of die level signal terminals; affixing a conductive structure of a first leadframe power conductor to at least two of the reference voltage terminal package landing pads so that the conductive structure of the first leadframe power conductor is electrically connected to the reference voltage terminal package landing pads and disposed over an interior region of the integrated circuit die; electrically connecting the conductive structure of the first leadframe power conductor to the plurality of die level reference voltage supply terminals in the interior region of the integrated circuit die; encapsulating the integrated circuit die and first leadframe power conductor to completely enclose the first leadframe power conductor; wherein electrically connecting the conductive structure of the first leadframe power conductor to the plurality of die level reference voltage supply terminals comprises wirebonding the plurality of die level reference voltage supply terminals to the conductive structure of the first leadframe power conductor with a plurality of wirebond conductors prior to encapsulating the integrated circuit die.