Patent ID: 8569764

Claim:
A thin film transistor, comprising: a substrate; a semiconductor layer disposed on the substrate, and comprising a crystallization inducing metal, a channel region, source and drain regions respectively disposed on opposing first and second sides of the channel region, and edge regions that are doped with a first impurity and that extend continuously from the source region to the drain region, along opposing third and fourth sides of the channel region, and excluding center portions of the channel region, source region and drain region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer, wherein a first interconnection is formed through a first contact hole exposing the source region and a portion of the edge regions at edges of the source region, wherein a second interconnection is formed through a second contact hole exposing the drain region and a portion of the edge regions at edges of the drain region, and wherein the first impurity is doped at a dose of 1*e 11 /cm 3 to 3*e 15 /cm 3 to getter the crystallization inducing metal into the edge regions of the semiconductor layer.