Patent ID: 7626462

Claim:
A system comprising: a reference oscillator adapted to provide a first reference signal; a first fractional-N phase-locked loop (FN-PLL) adapted to provide a first baseband local oscillator signal based on the first reference signal and comprising first fractional-N divider circuitry controlling a frequency of the first baseband local oscillator signal based on a first nominal fractional divide value corresponding to a desired frequency of the first baseband local oscillator signal and a first automatic frequency control (AFC) value computed to compensate for a frequency error of the reference oscillator; a second fractional-N phase-locked loop (FN-PLL) adapted to provide a first receive local oscillator signal based on the first reference signal and comprising second fractional-N divider circuitry controlling a frequency of the first receive local oscillator signal based on a second nominal fractional divide value corresponding to a desired frequency of the first receive local oscillator signal and a second AFC value computed to compensate for the frequency error of the reference oscillator; third fractional-N divider circuitry adapted to receive the first receive local oscillator signal and provide a second reference signal based on the first receive local oscillator signal; and a translational loop adapted to provide a first transmit local oscillator signal based on the second reference signal.