Patent ID: 8576636

Claim:
A semiconductor device comprising: a common bit line; a plurality of divided bit lines electrically connected to the common bit line; a source line; a word line; a signal line; a selection line; a selection transistor whose gate is electrically connected to the selection line; a plurality of memory cell arrays divided into a plurality of blocks every plural rows; and a plurality of memory cells included in each of the plurality of memory cell arrays, one of the plurality of memory cells in one of the plurality of memory cell arrays comprising: a first transistor including a first gate, a first source, a first drain, and a first channel formation region; a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and a capacitor, wherein the common bit line is electrically connected to a first divided bit line of the plurality of divided bit lines through the selection transistor, wherein the source line is electrically connected to the first source, wherein the first divided bit line is electrically connected to the first drain and the second source, wherein the word line is electrically connected to one electrode of the capacitor, wherein the signal line is electrically connected to the second gate, wherein the first gate, the second drain, and the other electrode of the capacitor are electrically connected to each other, wherein the first channel formation region includes single crystal silicon, and wherein the second channel formation region includes an oxide semiconductor.