Patent ID: 8298920

Claim:
A chip forming position specifying method for applying chip identifications indicative of position of semiconductor chips on a wafer, the semiconductor chips having a plurality of wiring layers, the method comprising: forming different first linear marks for every semiconductor chip in a first transfer mask used to form a first wiring layer and normal functional wirings of the plurality of wiring layers; forming different second linear marks for every semiconductor chip in a second transfer mask used to form a second wiring layer and normal functional wirings of the plurality of wiring layers, the second wiring layer above the first wiring layer; constructing each of the first and second transfer masks so that a plurality of chip areas are arranged in matrix form and so that the first and second linear marks are formed in the respective chip areas one by one, the first and second linear marks extend in directions to intersect one another at right angles when transferred onto the wafer from the first and second transfer masks, so that the intersecting positions differ depending on chip forming positions on the wafer; bringing the intersecting first and second linear marks into conduction at the intersecting positions; and specifying positions of the chips on the wafer based on conducting states of the first and second linear marks.