Patent ID: 7254657

Claim:
A computing system, comprising: a system bus that implements a bus protocol; an interface unit coupled to the system bus, wherein the interface unit is compatible with a first system bus protocol in a first selectable mode and a second system bus protocol in a second selectable mode, and the first system bus protocol is different from the second system bus protocol; at least one processor arrangement coupled to the system bus via the interface unit; a controller coupled to the system bus via an interface function compatible with one of the system bus protocols, the controller adapted to provide access to memory and input/output resources; a mode register coupled to the interface unit, wherein the interface unit selects the first selectable mode responsive to data in the mode register being equal to a first value and selects the second selectable mode responsive to the data in the mode register being equal to a second value; and a scan controller coupled to the mode register, the scan controller adapted to scan data into the mode register, whereby the interface unit provides access to the system bus for the at least one processor according to one of the first and second selectable modes.