Patent ID: 7395305

Claim:
A method for incrementing, decrementing or two's complementing a first string of N bits, the method comprising: generating a signal representing an auxiliary string of N bits as a function of the first string, the auxiliary string having a first least significant bit that is independent from the first string and any other bit of the auxiliary string, the generating based on starting from a second least significant bit up to a most significant bit of the auxiliary string, and performing a first logic combination with a corresponding bit of the first string or a negated replica thereof, starting from a least significant bit up to a second most significant bit of the first string, and performing the first logic combination with a corresponding bit of the first string or the negated replica thereof less significant than the corresponding bit, and selection of the first string or the negated replica thereof for the first logic combination is based on the incrementing, decrementing or two's complementing operation to be performed; generating an output signal containing a string as a second logic combination of the auxiliary string and of the first string the second logic combination and the selection of the first string or the negated replica thereof with the first logic combination determines whether the incrementing, decrementing or two's complementing operation is being performed on the first string.