Patent ID: 8284885

Claim:
A clock and data recovery (CDR) circuit for receiving a data signal and generating a clock signal, comprising: an oscillator for generating the clock signal according to an oscillation voltage; a phase detector for receiving the data signal, wherein the phase detector comprises a mixer, the mixer configured for detecting a phase difference between the data signal and the clock signal and generating a phase detection signal which represents the phase difference between the data signal and the clock signal, wherein the phase detector delays the data signal to generate a first delayed data signal and a third delayed data signal; a first voltage-to-current (V-to-I) converter for receiving the phase detection signal and generating a first current signal according to a voltage level of the phase detection signal to vary the oscillation voltage; a frequency detector, coupled to the phase detector, for detecting a frequency difference between the data signal and the clock signal according to the clock signal, the first delayed data signal, and the third delayed data signal and generating a frequency detection signal which represents the frequency difference; and a second V-to-I converter for receiving the frequency detection signal and generating a second current signal according to a voltage of the frequency detection signal to vary the oscillation voltage.