Patent ID: 8384158

Claim:
An electrostatic discharge (ESD) protection device, comprising: a P-type doped region; an N-type doped region, located in the P-type doped region; a first P+ doped region, located in the N-type doped region and electrically connected to a pad; a first N+ doped region, located between the P-type doped region and the N-type doped region, wherein a portion of the first N+ doped region is located in the N-type doped region and a residue portion is located in the P-type doped region; a second N+ doped region, located in the P-type doped region and outside the N-type doped region, wherein the second N+ doped region is electrically connected to a first power rail; a third N+ doped region, located in the P-type doped region and outside the N-type doped region, wherein the third N+ doped region is electrically connected to a second power rail and the second N+ doped region is located between the first N+ doped region and the third N+ doped region; a first gate structure located on the P-type doped region and between the first N+ doped region and the second N+ doped region, wherein the first gate structure is electrically connected to the second power rail, and the first gate structure, the first N+ doped region, the second N+ doped region and the P-type doped region together form an N-type metal-oxide-semiconductor (NMOS) field-effect transistor; and a second gate structure located on the P-type doped region and between the second N+ doped region and the third N+ doped region, wherein the second gate structure is electrically connected to the second power rail, and the second gate structure, the second N+ doped region, the third N+ doped region and the P-type doped region together form an NMOS field-effect transistor.