Patent ID: 7650579

Claim:
A method comprising: associating at a processor a first label to a first vertex associated with a first circuit design model, wherein the first vertex is representative of a first circuit element of the first circuit design model; associating at the processor a first set of labels to a plurality of input and output nodes associated with the first circuit design model, wherein the plurality of input and output nodes is representative of a first set of inputs and outputs of the first circuit design model; associating at the processor a second set of labels to a plurality of vertices associated with the first circuit design model, wherein the plurality of vertices is associated with a plurality of circuit elements coupled to the first circuit element of the first circuit design model; determining at the processor a second label for the first vertex based on the first set of labels and the second set of labels; and determining at the processor a first correspondence between the first circuit design model and a second circuit design model based on the second label for the first vertex; associating at the processor a third label to a second vertex associated with the second circuit design model, wherein the second vertex is representative of a first circuit element of the second circuit design model; associating at the processor the first set of labels to a plurality of input and output nodes associated with the second circuit design model, wherein the plurality of input and output nodes is representative of a set of inputs and outputs of the second circuit design model; associating at the processor a third set of labels to a plurality of vertices associated with the second circuit design model, wherein the plurality of vertices is associated with a plurality of circuit elements coupled to the first circuit element of the second circuit design model; determining at the processor a fourth label for the second vertex based on the first set of labels and the third set of labels; wherein the first correspondence between the first circuit design model and the second circuit design model is further based on the fourth label.