Patent ID: 7391716

Claim:
A data transmitting and receiving apparatus comprising: a main data transmitting circuit for converting main data into serial data and transmitting the serial data via at least one transmission path in synchronization with a clock signal; a main data receiving circuit for receiving the serial data and converting the received serial data into parallel data to obtain main data; an ancillary data transmitting circuit for pulse-width-modulating the clock signal by using ancillary data to generate a modulated clock signal having at least three kinds of pulse widths in a predetermined order and transmitting the modulated clock signal via another transmission path, said ancillary data transmitting circuit including a one-bit signal generating circuit for generating a one-bit signal which is inverted at a cycle of the clock signal when the second value is inputted as the ancillary data and a pulse width generating and modulating circuit for generating a pulse having a pulse width of 50% of the cycle of the clock signal when the first value is inputted as the ancillary data and alternately and selectively generating (i) a pulse having a pulse width of (50−a)% of the cycle of the clock signal when the second value is inputted as the ancillary data and the first value is inputted as the one-bit signal and (ii) a pulse having a pulse width of (50+a)% of the cycle of the clock signal when the second value is inputted as the ancillary data and the second value is inputted as the one-bit signal, where “a” satisfies 0<a<50; and an ancillary data receiving circuit for receiving the pulse-width-modulated clock signal and demodulating the received clock signal to obtain ancillary data, said ancillary data receiving circuit including a pulse width detecting circuit for receiving the pulse-width-modulated clock signal and detecting whether or not the pulse width of the received clock signal is within a range from (50−b)% to (50+b)% of one cycle on the basis of a rising edge of the received clock signal, where “b” satisfies 0<b<50.