Patent ID: 7567101

Claim:
A digital PLL circuit comprising: a frequency comparator that compares a frequency of a reference clock and a frequency of an output clock generated according to the reference clock, to output a frequency comparison signal indicating a result of the comparison; a frequency variable circuit comprising: a delay circuit having a plurality of inverting circuits connected in series; and a first selection circuit that adjusts the frequency of the output clock by selecting one of odd output signals outputted from odd-numbered inverting circuits out of said inverting circuits, according to the frequency comparison signal to supply a selected odd output signal to an input of said delay circuit as a feedback signal; a phase comparator comparing phases of the reference clock and the output clock to output a phase comparison signal indicating a result of the comparison; a second selection circuit adjusting the phase of the output clock by selecting one of the odd output signals according to the phase comparison signal to output a selected odd output signal as the output clock; and a first reference divider frequency-dividing the reference clock at a predetermined division ratio to output the divided reference clock as a first divided reference clock, wherein said frequency comparator comprises: a first counter that counts the reference clock to output a counted value as a first counter value signal and that is reset in response to the first divided reference clock; a second counter that counts the output clock to output a counted value as a second counter value signal and that is reset in response to the first divided reference clock; and a magnitude comparator that compares a first counter value indicated by the first counter value signal of said first counter and a second counter value indicated by the second counter value signal of said second counter to output a result of the comparison as the freguency comparison signal.