Patent ID: 7361559

Claim:
A method of forming a semiconductor construction, comprising: providing a first electrically insulative material; forming a first crystalline Si/Ge layer over the first electrically insulative material; the first crystalline Si/Ge layer having a relaxed crystalline lattice; forming a second crystalline Si/Ge layer over the first crystalline Si/Ge layer; the second crystalline Si/Ge layer having a strained crystalline lattice; forming an electrically floating element over the second crystalline Si/Ge layer; forming an active region extending into the first and second crystalline Si/Ge layers proximate the floating element, the active region including a pair of source/drain regions gatedly connected with one another by the floating element; the active region within the first crystalline Si/Ge layer being within a single crystal of the first crystalline Si/Ge layer; and forming a control gate proximate the floating element and spaced from the floating element by one or more second insulative materials.