Patent ID: 8694595

Claim:
A system for low latency, high bandwidth data transfers between compute nodes in a parallel computer, the system comprising an origin compute node and a target compute node, each compute node comprising one or more computer processors, a DMA controller, a DMA engine installed upon the DMA controller, and computer memory operatively coupled to the computer processors, the DMA controller, and the DMA engine, the computer memory for the origin compute node having disposed within it computer program instructions that when executed by one of the computer processors cause the system to carry out the steps of: transferring, by the origin DMA engine, a portion of the data to the target compute node using a memory FIFO operation, the memory FIFO operation specifying one end of the buffer from which to begin transferring the portion of the data; receiving, by an origin direct memory access (‘DMA’) engine, an acknowledgement of an request to send (‘RTS’) message from a target compute node; and transferring, concurrently with the transfer of the portion of the data to the target compute node using the memory FIFO operation, by the origin DMA engine in response to receiving the acknowledgement of the RTS message, any remaining portion of data in a buffer for transfer to the target compute node, to the target compute node using a direct put operation, including initiating the direct put operation without invoking an origin processing core on the origin compute node, the direct put operation specifying the other end of the buffer from which to begin transferring the remaining portion of the data.