Patent ID: 8094497

Claim:
An integrated circuit memory device, comprising: a semiconductor body; a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, with insulating members isolating gates in the series from adjacent gates in the series; and a charge storage structure on the semiconductor body, the charge storage structure including dielectric charge trapping locations beneath more than one of the plurality of gates in the series, the charge storage structure including a multilayer tunnel dielectric structure disposed above the semiconductor body, the tunnel dielectric structure, including a bottom dielectric layer adjacent the channel having a thickness of less than 2 nanometers and having a hole tunneling barrier height, a middle dielectric layer having a hole-tunneling-barrier height smaller than that of the bottom dielectric layer and having a thickness less than 3 nanometers, and a top dielectric layer having a hole tunneling barrier height greater than that of the middle dielectric layer; a charge storage layer disposed above the tunnel dielectric structure, and a blocking insulating layer disposed above the charge storage layer; wherein the semiconductor body includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, the multiple-gate channel region having one of n-type and p-type conductivity.