Patent ID: 7710162

Claim:
A differential amplifier, comprising: an input unit configured to control voltage levels of a first output node and a second output node according to a voltage difference between a first input signal and a second input signal; a feedback input unit configured to control the voltage levels of the first output node and the second output node according to a voltage difference between first and second feedback signals respectively fed back from the first output node and the second output node; a load unit having at least two transistors coupled with each other at their gates to provide the input unit and the feedback unit with current determined by the input unit and the feedback unit, wherein one of the two transistors is diode-connected, the other transistor is coupled to a corresponding one of the first and second output nodes, and voltages loaded at the first and the second output nodes are respectively output as a first output signal and a second output signal; an initialization unit configured to initialize the first and the second output nodes in response to an enable signal; and a bias provider configured to control the activation of the differential amplifier by providing the input unit, the load unit, and the feedback unit with a bias current in response to the enable signal, wherein the input unit includes: a first input unit provided with first and second NMOS transistors, connected between the load unit and the bias provider, for respectively receiving the first input signal and the second input signal through their gates; and a second input unit provided with third and fourth NMOS transistors, connected between a load unit and the bias provider, for respectively receiving the first input signal and the second input signal through their gates, wherein a first terminal of the first NMOS transistor is connected to the second output node and a first terminal of the fourth NMOS transistor is connected to the first output node, wherein the feedback unit includes: a fifth NMOS transistor receiving the first feedback signal from the first output node at its gate, wherein the gate of the fifth NMOS transistor is not connected to a source of a sixth NMOS transistor; the sixth NMOS transistor receiving the second feedback signal from the second output node at its gate, wherein the gate of the sixth NMOS transistor is connected to a source of the fifth NMOS transistor; a seventh NMOS transistor receiving the first feedback signal from the first output node at its gate, wherein the gate of the seventh NMOS transistor is not connected to a source of an eighth NMOS transistor; and the eighth NMOS transistor receiving the second feedback signal from the second output node at its gate, wherein the gate of the eighth NMOS transistor is connected to a source of the seventh NMOS transistor.