Patent ID: 7940559

Claim:
An integrated circuit device comprising: a memory cell array including: a plurality of word lines; a plurality of source lines; a plurality of bit lines; and a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes a transistor having a source, drain, gate and body region, wherein the body region is electrically floating; and wherein each memory cell is programmable to store one of a plurality of data states which are representative of an amount of charge in the body region of the electrically floating body transistor; write circuitry, coupled to each memory cell of a first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by: (i) applying write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and (ii) applying write de-select control signals to each memory cell of a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation.