Patent ID: 7969006

Claim:
An integrated circuit chip comprising: a silicon substrate; a voltage regulator in or over said silicon substrate, wherein said voltage regulator has a first node at a first voltage level of Vcc output from said voltage regulator and a second node at a second voltage level of Vdd supplied from an external circuit, wherein a ratio of a difference of said second voltage level minus said first voltage level to said second voltage level is less than 10%; an internal circuit in or over said silicon substrate, wherein said internal circuit comprises an NMOS transistor, wherein a ratio of a physical channel width of said NMOS transistor to a physical channel length of said NMOS transistor ranges from 0.1 to 20; a dielectric structure over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric structure, wherein said first interconnecting structure is connected to said first node of said voltage regulator; a first metal interconnect over said silicon substrate, wherein said first metal interconnect is connected to said first node of said voltage regulator through said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric structure, wherein said second interconnecting structure is connected to a first node of said internal circuit; a second metal interconnect over said silicon substrate, wherein said second metal interconnect is connected to said first node of said internal circuit through said second interconnecting structure; a passivation layer over said dielectric structure, said voltage regulator and said internal circuit, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said second opening has a width between 0.1 and 30 micrometers; and a third interconnecting structure over said passivation layer and on said first and second contact points, wherein said first node of said voltage regulator is connected to said first node of said internal circuit through, in sequence, said first interconnecting structure, said first contact point, said third interconnecting structure, said second contact point and said second interconnecting structure, wherein said third interconnecting structure comprises a seed layer and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a thickness between 2 and 30 micrometers.