Patent ID: 7093148

Claim:
A microcontroller comprising: a clock control circuit provided with a clock mode designation register for storing clock frequency information corresponding to an extremely low speed mode for an operation by a clock of an extremely low frequency, or a normal operation mode for operation by a clock of a normal frequency, which outputs a first control signal in accordance with a value set in the clock mode designation register when the extremely low speed mode is designated during an operation in the normal operation mode; a dynamic random access memory (DRAM)for holding, in the extremely low speed mode, data by being operated in a self-refresh mode, and outputting a confirmation signal indicating switching to the self-refresh mode; a DRAM control circuit for switching the DRAM to the self-refresh mode based on the first control signal; a read-only memory (ROM)operated in the extremely low speed mode; an address changing circuit; and a remap control circuit for controlling the address changing circuit based on the confirmation signal, and outputting a second control signal for switching a program execution address from the DRAM to an address of the ROM to control an address space in which a program is executed, the address changing circuit switching the address space based on the second control signal, wherein when the extremely low speed mode is designated, the address changing circuit is controlled in a manner that the first and second control signals and the confirmation signal are outputted while one command in the DRAM is executed to set a value in the clock mode designation register, and a command next to the one command is executed in the ROM based on the second control signal.