Patent ID: 7071028

Claim:
A method for manufacturing a layered semiconductor device, comprising the steps of: forming inter-substrate connecting bumps on one of a front surface or both of front and back surfaces of inter-substrate connecting electrodes formed on both front and back surfaces of a substrate, connected by through holes and connected to a wiring pattern, so as to be higher than a required height; connecting electrodes of a semiconductor chip to the wiring pattern formed on the substrate and mounting the electrodes of the semiconductor chip on the front surface or both the front and back surfaces of the substrate; applying an encapsulating resin to the substrate so as to cover the semiconductor chip and the inter-substrate connecting bumps therewith so as to form an encapsulated unit having a top surface and a plurality of side surfaces; and cutting flat the top surface of the encapsulated unit so as to have a prescribed distance between the substrate and the cut flat surfaces of the encapsulating resin, the semiconductor chip and the inter-substrate connecting bumps and cutting a number of the side surfaces where a number of through holes and the inter-substrate connecting bumps are located to expose the number of through holes and the inter-substrate connecting bumps on the number of side surfaces so that each semiconductor device is formed; layering a plurality of semiconductor devices; and connecting the inter-substrate connecting bumps of the respective semiconductor devices together or the inter-substrate connecting bumps and the inter-substrate connecting electrodes together.