Patent ID: 8036318

Claim:
A clock and data recovery circuit comprising: a clock generator to generate a synchronous clock signal; a phase detector to compare a phase of the synchronous clock signal obtained by the clock generator with a phase of serial data and obtain a phase error signal corresponding to a comparison result of the comparing; a phase tracking loop to acquire a phase correction control signal for tracking phase shift of the serial data based on the phase error signal; and a frequency tracking loop to acquire a frequency correction control signal for tracking frequency shift of the serial data based on the phase error signal, wherein the clock generator corrects the phase of the synchronous clock signal based on the frequency correction control signal and the phase correction control signal, the frequency tracking loop includes: a first smoothing unit to receive the phase error signal obtained by the phase detector as an input signal, smooth the input signal in each smoothing period with a predetermined length and output a smoothed error signal; and a pattern generator to generate a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a second predetermined length and output the pattern as the frequency correction control signal, and the first smoothing unit changes the length of the smoothing period according to a direction of a change in the frequency of the frequency correction control signal.