Patent ID: 8874872

Claim:
A memory channel comprising: a plurality of memory units, with each memory unit comprising a plurality of garbage collection units; and a controller communicatively coupled to the plurality of memory units, the controller configured to select a memory unit of the plurality of memory units for garbage collection based on a calculated number of memory units, of the plurality of memory units, to garbage collect, wherein the calculated number of memory units, of the plurality of memory units, to garbage collect is dynamically obtained as a function of a time-variable parameter of the plurality of memory units and as a function of a ratio of erasing memory units of the plurality of memory units to writing memory units of the plurality of memory units, and wherein the ratio of erasing memory units to of the plurality of memory units to writing memory units of the plurality of memory units is: R =( T erase+ Tgc _read)/( T prog* P ) where Tprog is a time required for a memory unit to program a page, Terase is a time required for a memory unit to erase an erasure block, Tgc_read is a time required to perform a read operation required to garbage collect an erasure block in a memory channel selected for garbage collection, wherein Tgc_read is a run-time parameter, and P is pages per erasure block.