Patent ID: 7355877

Claim:
A semiconductor device comprising: a die pad having a first surface and a second surface opposed to the first surface; leads including a first lead, a second lead, a third lead and a fourth lead, the leads being spaced from the die pad; a first semiconductor memory chip mounted over the first surface of the die pad; a second semiconductor memory chip mounted over the second surface of the die pad; each said semiconductor memory chip having a first external electrode and a second external electrode, the first and second external electrodes of the semiconductor chips each being connected to a different one of the first to fourth leads by a corresponding wire; and a sealing resin sealing the die pad, a part of each said lead, the first semiconductor memory chip, the second semiconductor memory chip, and each said wire; wherein the first semiconductor memory chip is of the same design as the second semiconductor memory chip; and wherein each said semiconductor memory chip includes a switching circuit that can perform switching between interface functions of the second external electrode of the chip based on a potential applied to the first external electrode of the chip.