Patent ID: 7417483

Claim:
A circuit apparatus comprising: a current source circuit; and a level shifter circuit coupled to the current source circuit wherein the level shifter circuit has a circuit for independently controlling a voltage on a cascode node; wherein the current source comprises: a first transistor having a first, second and third terminal, a second terminal of the first transistor coupled to the level shifter current, and a third terminal coupled to the cascode node; and a second transistor having a first, second and third terminal, a first terminal of the second transistor coupled to the cascode node, a second terminal of the second transistor coupled to a voltage source, and a third terminal of the second transistor coupled to ground; wherein the level shifter circuit comprises: a third transistor having a first, second and third terminal, the first terminal of the third transistor coupled to a voltage supply, and the third terminal of the third transistor coupled to the current source circuit; a fourth transistor having a first, second and third terminal, the first terminal of the fourth transistor coupled to the voltage supply, the second terminal of the fourth transistor coupled to the second terminal of the third transistor, and the third terminal of the fourth transistor coupled to a circuit for independently controlling a voltage on a cascode node; a fifth transistor having a first, second and third terminal, the first terminal of the fifth transistor coupled to the third terminal of the third transistor, the second terminal of the fifth transistor coupled to the circuit for independently controlling the voltage on a cascode node, and the third terminal of the fifth transistor coupled to ground; and the circuit for independently controlling the voltage on a cascode node coupled to the third terminal of the fourth transistor and to the cascode node, the circuit for independently controlling the voltage on a cascode node comprising: a resistive element for independently controlling the voltage on a cascode node; and a capacitive element coupled in parallel to the resistive element, the resistive element and the capacitive element coupled to the second terminal of the fifth transistor and the cascode node.