Patent ID: 8385142

Claim:
A first integrated circuit contained in a semiconductor package, the first integrated circuit comprising: a plurality of input/output (I/O) modules, each I/O module including a plurality of data pins to receive and transmit data, a subset of the I/O modules having a data strobe pin; a plurality of fixed data strobe signal buses coupled to the plurality of I/O modules, each fixed DQS bus having a fixed configuration that correlates a number of data pins with a corresponding data strobe pin, wherein the data strobe pin spans multiple I/O modules; and a flexible data strobe signal (DQS bus coupled to the plurality of I/O modules, the flexible DQS bus enabling selection of a subset of the number of data pins of the first integrated circuit which map to a plurality of data pins of corresponding I/O modules of a second integrated circuit contained in the semiconductor package, wherein the second integrated circuit has a different number of I/O modules than a number of the plurality of I/O modules of the first integrated circuit.