Patent ID: 8394689

Claim:
A semiconductor memory device manufacturing method comprising: forming a first gate insulating film and a second gate insulating film on a first region in which a memory cell transistor is to be formed and on a second region in which a peripheral transistor for controlling the memory cell transistor is to be formed on a semiconductor substrate, respectively; forming a first conductive layer on each of the first gate insulating film and second gate insulating film; forming a mask material on the first conductive layer; making a first trench which passes through the mask material, first conductive layer, and first gate insulating film in the first region and reaches the inside of the semiconductor substrate and a second trench which passes through the mask material, first conductive layer, and second gate insulating film in the second region and has a bottom face that reaches the inside of the semiconductor substrate and a side face in contact with the bottom face and which has a greater width than that of the first trench; implanting impurities into the side face of the second region by implanting ions into the first trench and second trench in a direction deviating from a normal line to the bottom face by an acute angle to the side face; forming a first element isolating region by burying a first insulating film in the first trench; forming a second element isolating region by burying a second insulating film in the second trench; removing the mask material after forming the first element isolating region and second element isolating region; forming a third insulating film on the first conductive layer; forming a second conductive layer on the third insulating film; and forming the memory cell transistor and peripheral transistor by patterning the second conductive layer, first insulating film, first conductive layer, first gate insulating film, and second gate insulating film.