Patent ID: 8032810

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array comprising a plurality of memory cells enabled to store multi-value data by differences of threshold voltages, the memory cells being arranged along a plurality of bit-lines and a plurality of word-lines; a sense amplifier circuit connected to the bit-lines; a word-line control circuit controlling applying a read voltage as a word line voltage to the word line, the read voltage being larger than an upper limit of one of plural threshold voltage distributions representing the data and smaller than a lower limit of another threshold voltage distribution with higher threshold voltages than the one of the plural threshold voltage distributions, and applying a soft-value read voltage as a word line voltage to the word line, the soft-value read voltage being smaller than an upper limit of each of the plurality of the threshold voltage distributions and larger than a lower limit thereof to generate a plurality of soft-values; a likelihood calculation circuit calculating a likelihood value of data stored in the memory cell based on the soft-value; an error correction circuit executing data error correction for the data read from the memory cell based on the likelihood value; and a refresh control circuit controlling a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.