Patent ID: 7145805

Claim:
A nonvolatile memory comprising: a plurality of nonvolatile memory cells, each of which has an arbitrary one of a program state and an erase state, being divided into a plurality of blocks; a plurality of input/output terminals; a command decode circuit which is capable of decoding an arbitrary one of plural commands received via said plurality of input/output terminals; a plurality of word lines; and a control circuit, wherein a capacity of each of said plurality of blocks is more than 512 bytes, wherein said control circuit is capable of performing a consecutive write operation within the same block without an intervening erase to said nonvolatile memory cells, wherein said intervening erase is that said control circuit controls selection of an arbitrary one of said blocks and a moving state of said nonvolatile memory cells belonging in the selected one block to said erase state in response to an erase command, wherein said consecutive write operation is that said control circuit controls selection of a first word line and a moving state of first ones of said nonvolatile memory cells coupled to said first word line to said program state in accordance with data in response to a write command accompanied with first address information, and then, said control circuit controls selection of said first word line and a moving state of second ones of said nonvolatile memory cells coupled to said first word line to said program state in accordance with data in response to said write command accompanied with second address information, and wherein said write command is capable of being accompanied with 512-byte data.