Patent ID: 8891308

Claim:
A method for erasing in a 3D stacked non-volatile memory device, comprising: accessing data indicating an amount of program-erase cycles in the 3D stacked non-volatile memory device, the 3D stacked non-volatile memory device comprising alternating word line layers and dielectric layers and a plurality of NAND strings of memory cells formed in memory holes which extend through the layers, each memory cell has a control gate formed by one of the word line layers, and each NAND string comprises a drain end and a source end; and in connection with an erase operation of selected memory cells of one or more selected word line layers, applying a plurality of erase voltages, in turn, to at least one of the drain ends or the source ends of the NAND strings, each erase voltage charges up respective bodies of the NAND strings to a charged state, after which a voltage of the one or more selected word line layers is driven lower, so that threshold voltages of the selected memory cells are driven lower, wherein the plurality of erase voltages include an initial erase voltage and a subsequent erase voltage which is stepped up from the initial erase voltage by a step size which is based on the data, and the step size is relatively higher when the amount of program-erase cycles is relatively higher.