Patent ID: 7987385

Claim:
A method of providing high integrity checking for an N-lane computer processing module (Module), N being an integer greater than equal to two, the method comprising the steps of: detecting, by a data Output Management unit (OM), when any of the N processing lanes sends different output data; and configuring each Hosted Application as either normal or high integrity; and determining whether the respective processing lane receives exactly the same set of high-integrity data as all other of the N processing lanes, and outputting an error condition otherwise; and determining, whether the respective processing lane output exactly the same set of high-integrity data as all other of the N processing lanes, and outputting an error condition otherwise; and for the Hosted Applications configured as high integrity, running an identical version of the software source code targeted for similar or dissimilar microprocessors on all N processing lanes, and activating a Time Management Unit, Critical Regions Management Unit, data input Management Unit and data Output Management Unit for each of the N processing lanes; and for the Hosted Applications configured as normal integrity, running a copy of the software on one of the N processing lanes, and not activating the Time Management Unit, Critical Regions Management Unit, input Management Unit and Output Management Unit for the one activated processing lane while that Hosted Application is running.