Patent ID: 8331050

Claim:
A write clock synchronization system comprising: a channel module configured to read a servo section of a bit-patterned magnetic medium to generate a preamble signal; an initial phase estimating system configured to (i) estimate an initial phase of the preamble signal based on servo clock samples of the preamble signal, and (ii) estimate the initial phase of the preamble signal based on write clock samples of the preamble signal; a phase determination module configured to estimate a phase of a write clock signal based on (i) the initial phase of the preamble signal estimated using the servo clock samples, and (ii) the initial phase of the preamble signal estimated using the write clock samples; and a phase error module configured to estimate a phase error based on the phase of the write clock signal, wherein the channel module is configured to write data to discontinuous bit islands of the bit-patterned magnetic medium based on the phase error.