Patent ID: 7035128

Claim:
A semiconductor memory device comprising: a word line; a first bit line intersecting with the word line; a second bit line forming a bit line pair with the first bit line; a memory cell including an access transistor of an MISFET in which a gate electrode is connected to the word line and a first doped layer is connected to the first bit line, and a cell capacitor connected to a second doped layer of the access transistor, being capable of storing electric charge, and located at the intersection between the word line and the first bit line; and a sense amplifier for amplifying a potential difference between the first bit line and the second bit line during a read-out operation wherein a positive power supply voltage is applied to the first bit line in a high level state and a ground voltage is applied to the first bit line in a low level state, wherein the access transistor is a depletion type p-channel MISFET, and wherein the ground voltage is applied to a gate electrode of the access transistor through the word line when the memory cell is in an activated state.