Patent ID: 8103897

Claim:
A clock generation circuit comprising: an edge detection circuit; a reference clock generation circuit; a reference clock counter circuit; and a frequency-divider circuit, wherein the edge detection circuit comprises a first latch circuit, a second latch circuit, an inverter circuit, and an AND circuit, wherein the first latch circuit is electrically connected to the second latch circuit and the inverter circuit, wherein the AND circuit is electrically connected to the second latch circuit and the inverter circuit, wherein the AND circuit outputs a reset signal when the first latch circuit receives a first signal, wherein the reference clock generation circuit outputs a reference clock signal, wherein the reference clock counter circuit outputs a counter value obtained by counting a number of waves of the reference clock signal, and resets the counter value when the reference clock counter circuit receives the reset signal, wherein the frequency-divider circuit generates a clock signal from the counter value, and wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period.