Patent ID: 7948699

Claim:
A data processing circuit, the circuit comprising: a multiplexer, wherein a first input of the multiplexer is operable to receive an input data set and a second input of the multiplexer is operable to receive a buffered data set, and wherein the multiplexer is operable to provide either the input data set or the buffered data set as a multiplexer output based upon a select signal; a memory buffer coupled to an output of the multiplexer, and operable to receive the multiplexer output and to provide the buffered data set; a data processing circuit, wherein operation of the data processing circuit is at least in part governed by channel settings, wherein the data processing circuit is operable to receive the multiplexer output and to perform a data detection process, wherein the select signal is assertable to select the buffered data set when the data detection process fails, and wherein the select signal is assertable to select the input data set when the data detection process succeeds; and a channel setting modification circuit operable to modify the channel settings when the data detection process fails.