Patent ID: 8482336

Claim:
A single pole double throw (SPDT) switch circuit comprising: a serial connection of a first transmission-side transistor and a first reception-side transistor between a transmission node and a reception node; an antenna connected to a node between said first transmission-side transistor and said first reception-side transistor; a first variable impedance circuit connected to a gate of said first transmission-side transistor and configured to provide a first high impedance state or a first low impedance state depending on a first impedance control voltage; a second variable impedance circuit connected to a gate of said first reception-side transistor and configured to provide a second high impedance state or a second low impedance state depending on a second impedance control voltage; a third variable impedance circuit connected to a body of said first transmission-side transistor and configured to provide a third high impedance state or a third low impedance state depending on said first impedance control voltage, wherein said first impedance control voltage is applied to said third variable impedance circuit; and a fourth variable impedance circuit connected to a body of said first reception-side transistor and configured to provide a fourth high impedance state or a fourth low impedance state depending on said second impedance control voltage, wherein said second impedance control voltage is applied to said fourth variable impedance circuit, wherein said third variable impedance circuit is located between a first body bias control node and said body of said first transmission-side transistor, and said fourth variable impedance circuit is located between a second body bias control node and said body of said first reception-side transistor, and said first and second body bias control nodes are configured to be provided with a complementary pair of body bias control signals.