Patent ID: 7460113

Claim:
A digital pixel clock generation circuit operative to receive timing information associated with image data from at least one external image source from which image presentation time information can be derived comprising: an image presentation timing error determination circuit operative to produce desired pixel clock frequency control information based on a difference between expected presentation time, which is based on at least the received image presentation time information from the external image source, and presentation time information provided by a display controller that is operatively coupled to the digital display clock generation circuit; a programmable digital waveform generation circuit that is programmed based on the produced desired pixel clock frequency control information, having an input responsive to an independent clock source and an output operative to provide a digital representation of an independently generated desired pixel clock; and a digital to analog converter (DAC) having an input, operatively coupled to receive the digital representation of the independently generated desired pixel clock, and an output operative to provide an analog representation of the digital representation of the independently generated desired pixel clock for the digital display based on the independent clock source.