Patent ID: 7496822

Claim:
A data processing system, comprising: a non-volatile memory unit having an address input, a data input and a corrected data output, the non-volatile memory unit comprising: a main memory coupled to the data input and the address input for storing signal groups; an error checking and correction (ECC) memory coupled to the data input and the address input for storing error correction bits, wherein the main memory and the ECC memory determine a first logic state by means of a stored charge and determine a second logic state by means of a lack of stored charge; an error checking and correction (ECC) circuitry coupled to the main memory and to the FCC memory being operable to detect an error in a signal group retrieved from the main memory in response to an address provided on the address input, and being operable to correct the error in the signal group and to output the corrected signal group on the corrected data output, the ECC circuitry comprising: an interrupt circuitry operable to selectively signal an interrupt, such that an interrupt is signaled when the ECC circuitry determines the error in the signal group resulted from a bit signal that should be in the first state but was instead in the second state, and such that an interrupt is not signaled when the ECC circuitry determines the error in the signal group resulted from a bit signal that should be in the second state but was instead in the first state.