Patent ID: 8601047

Claim:
A system comprising: a minimum circuit configured to receive a first count value and a second count value, wherein the first count value represents a leading zero count of a significand of a first decimal floating point (DFP) operand, wherein the second count value represents a leading zero count of a significand of a second DFP operand, wherein the minimum circuit is configured to generate a preliminary leading zero count (PLZC) equal to the minimum of the first count value and the second count value; a decrementer configured to decrement the PLZC to obtain a decremented value; a multiplexer configured to select one of the PLZC and the decremented value based on a selection control signal, wherein the output of the multiplexer represents a leading zero count of a significand of a sum of the first DFP operand and the second DFP operand; and a logic unit configured to generate the selection control signal based on a carry operand and a sum operand.