Patent ID: 7123063

Claim:
A clock multiplier circuit disposed on an integrated circuit device having at least one other circuit comprising a plurality of logic gates operating using a supply voltage, the clock multiplier circuit comprising: a delay line circuit functioning to produce at each of a plurality of outputs a delayed version of a first clock signal, the delay of the delay line circuit being dependent upon at least one control signal and variations in the supply voltage; a control circuit accepting as inputs at least two of the plurality of outputs of the delay line circuit, the control circuit producing the at least one control signal, the control circuit adapted to adjust the at least one control signal in order to maintain a predetermined phase relationship of the at least two of the plurality of outputs of the delay line circuit; a mixer circuit adapted to combine a subset of the plurality of outputs of the delay line circuit in order to produce a second clock signal having a number of cycles for each cycle of the first clock signal; and wherein the clock multiplier circuit functions to adjust a duration of one or more portions of the second clock signal in response to variations in the supply voltage while producing the number of cycles of the second clock signal during each cycle of the first clock signal and maintaining a predetermined timing relationship of the first and second clock signals.