Patent ID: 6960801

Claim:
A ferroelectric memory cell, comprising: a semiconductor substrate having: a source that serves both as the source for the ferroelectric memory cell and the source for an adjacent memory cell; a drain in a spaced apart configuration with respect to the source and drains and sources of adjacent ferroelectric memory cells, wherein the drain is not included as a component of the adjacent ferroelectric memory cell; and a channel; a gate oxide substantially covering the drain, source, and channel; a ferroelectric gate unit positioned on said gate oxide layer, the ferroelectric gate unit asymmetrically overlying the drain with respect to the source, the ferroelectric gate unit comprising: a bottom electrode in electrical communication with said drain; a top electrode; a ferroelectric layer disposed between said bottom and said top electrode; and a sealing layer disposed on each side of said ferroelectric gate unit; and an upper conductive layer disposed on said ferroelectric gate unit and a portion of said gate oxide layer such that said upper conductive layer and said top electrode of said ferroelectric gate unit are in electrical communication.