Patent ID: 7485925

Claim:
A high voltage metal-oxide-semiconductor (MOS) transistor, comprising: a substrate; a well disposed in the substrate; a gate insulation layer disposed on the substrate; a gate disposed on the gate insulation layer; two drift regions disposed in the well at two sides of the gate, respectively, wherein the width of the gate is smaller than or at most equal to that of the drift regions; a channel region disposed between the drift regions, wherein the width of the channel region is greater than that of the drift regions; a source/drain region disposed inside the drift regions, respectively; and an isolation structure disposed inside the drift regions, respectively, wherein the isolation structure is located between the source/drain region and the channel region, the two drift regions enclose the source/drain region and the isolation structure, and the width of the source/drain region is smaller than or at least equal to that of the gate.