Patent ID: 8259495

Claim:
A method for driving a semiconductor memory device including a plurality of memory cell transistors arranged in a matrix; a plurality of word lines coupling the control gates of the plural memory cell transistors present in the identical one direction; a plurality of source lines coupling the sources of the plural memory cell transistors present in the identical one direction; a plurality of bit lines coupling the drains of the plural memory cell transistors present in the identical other direction intersecting said one direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and control lines coupling the gates of the plural first transistors, said method comprising: turning the plural first transistors on-states via the control line; applying a first voltage to one of the bit lines coupled to the drain of one of the memory cell transistors and applying a second voltage selectively to one of the word lines coupled to the gate of said one memory cell transistor; and reading information stored in said one memory cell transistor, based on a current flowing in said one of the bit lines.