Patent ID: 8431435

Claim:
A method comprising the steps of: stacking a first subassembly including a plurality of microelectronic elements onto a first adhesive layer of a substrate, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and then forming initial notches in said first subassembly so as to expose at least some of said traces of said first subassembly and coating a second adhesive layer on said first subassembly so as to fill said initial notches in said first subassembly with said second adhesive layer and cover said at least some traces; and then stacking a second subassembly including a plurality of microelectronic elements onto said second adhesive layer of said first subassembly, at least some of the plurality of microelectronic elements of said second subassembly having traces that extend to respective edges of the microelectronic elements; and then forming initial notches in said second subassembly so as to expose at least some of said traces of said second subassembly and coating a third adhesive layer on said second subassembly so as to fill said initial notches in said second subassembly with said third adhesive layer and cover said at least some traces of said second subassembly; and then forming notches in said first, second, and third adhesive layers so as to expose at least some of said traces of at least some of the plurality of microelectronic elements; and forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.