Patent ID: 7955970

Claim:
A semiconductor device manufacturing method comprising: forming an inter-layer insulating film over a semiconductor substrate; forming a first wiring trench of which a depth-to-width ratio is larger than 1 and a second wiring trench of which the depth-to-width ratio is equal to or smaller than 1 in the inter-layer insulating film; forming a seed layer over the inter-layer insulating film, an internal wall of the first wiring trench and an internal wall of the second wiring trench; depositing a first copper layer over the seed layer up to a state where the first wiring trench is embedded but the second wiring trench is not completely embedded by use of an electroplating method employing a current having a first current density; forming a second copper layer over the first copper layer till the second wiring trench is embedded by use of the electroplating method of the current with a transition of the current density, which is conducted a plural number of times between the first current density and a second current density higher than the first current density; and polishing said seed layer, the first copper layer and the second copper layer formed over the inter-layer insulating film.