Patent ID: 7692991

Claim:
A semiconductor memory device comprising: a plurality of memory cell plates; a plurality of sense amplifier regions, the memory cell plates and the sense amplifier regions being alternately arranged in a first direction, a plurality of sense amplifier groups arranged on the sense amplifier regions, respectively, each of the sense amplifier groups consisting of a plurality of sense amplifiers arranged in a second direction perpendicular to the first direction; a plurality of bit lines, each of which is connected to one of the sense amplifiers and extending over one of the memory cell plates; and column selection signal lines, each of which is connected to at least one of the sense amplifiers on every sense amplifier region so that a first bit line is positioned between a second bit line and a third bit line on one of the memory cell plates, wherein the first bit line is at least one of the bit lines extending from a first one of the sense amplifiers connected to a first one of the column selection signal lines, the second bit line is one of the bit lines extending from a second one of the sense amplifiers connected to a second one of the column selection signal lines, the third bit line is one of the bit lines extending from a third one of the sense amplifiers connected to the second column selection signal line, the first to the third sense amplifiers are different from each other, and the first and the second column selection signal lines are different from each other.