Patent ID: 7233349

Claim:
An apparatus for displaying time offset information between a reference signal and a test signal having a repetitive signal format with successive data values appearing as successive segments of at least one of analog and digital data values, the apparatus comprising: a timing extraction circuit coupled to the test signal, the timing extraction circuit being operable to derive a first signal from a rate of said successive data values and a second signal from a rate of said successive segments; a timing generator coupled to the timing extraction circuit, the timing generator accumulating a first measure of elapsed time associated with said successive data values and a second measure of elapsed time associated with said successive segments; wherein the reference signal is coupled for at least one of loading to a register and resetting said first and second measures of elapsed time; and, a display processor operable to generate a graphic display from said first and second measures of elapsed time, the display processor providing at least partly coextensive scales wherein said first and second measures are displayed graphically for as coarse and fine measures of a time offset between the test signal and the reference signal.