Patent ID: 8344492

Claim:
A semiconductor device comprising: a first multilayer wiring structure having a first surface and a second surface which is positioned on an opposite side to the first surface, the first multilayer wiring structure having a first wiring pattern formed on the second surface side and a housing portion penetrating through the first multilayer wiring structure from the first surface to the second surface; an electronic component having an electrode pad, the electronic component being accommodated in the housing portion in a state that an electrode pad formation surface at the side where the electrode pad is formed is positioned on the second surface side of the first multilayer wiring structure; and a second multilayer wiring structure having an insulating layer and a second wiring pattern which are stacked on the second surface of the first multilayer wiring structure and the electrode pad formation surface of the electronic component, wherein the second wiring pattern is electrically connected to the first wiring pattern and the electrode pad, wherein the second multilayer wiring structure has a plurality of external connecting pads formed on a surface which is positioned on an opposite side to a surface which is in contact with the first multilayer wiring structure, and wherein the plurality of external connecting pads are electrically connected to the second wiring pattern.