Patent ID: 7313730

Claim:
An integrated circuit (IC), comprising: one or more configurable elements; one or more configuration memory cells to store configuration data for the configurable elements; an embedded processor having one or more resources, a test port to receive a test bitstream, and a debug unit capable of accessing the one or more resources in response to the test bitstream; wherein the test port comprises a JTAG port, and the test bitstream comprises a JTAG-compatible bitstream; a configuration circuit having an input to receive the configuration data from an external storage device, and having an output connected to the configuration memory cells; a formatting circuit having an input to receive soft data from the external storage device and having outputs connected to the processor's test port; a plurality of JTAG input/output (I/O) pins; a JTAG-compliant test circuit having a plurality of inputs coupled to corresponding JTAG I/O pins, and having a plurality of outputs; and a select circuit having first inputs coupled to corresponding outputs of the JTAG-compliant test circuit, second inputs coupled to corresponding outputs of the formatting circuit, outputs coupled to the processor's JTAG port, and a control terminal to receive a mode signal.