Patent ID: 7772112

Claim:
A method of manufacturing a semiconductor device comprising: forming an insulating layer over an electrically conductive layer; forming a first mask layer over said insulating layer; forming a second mask layer over said first mask layer; forming a via which passes through said second mask layer, said first mask layer, and said insulating layer; forming a first resist layer in such a manner as to fill said via; forming a second resist layer over said second mask layer and said first resist layer; patterning said second resist layer into an interconnect pattern; etching said second mask layer by using said patterned second resist layer as a mask; etching said first mask layer halfway through a thickness thereof by using said second resist layer and said second mask layer as a mask; removing said first resist layer and said second resist layer; etching away a remaining portion of said first mask layer by using said second mask layer as a mask; forming an interconnect groove by etching said insulating layer using said first mask layer as a mask; and forming an electrically conductive material into said via and said interconnect groove, thereby forming an interconnect layer connected to said electrically conductive layer.