Patent ID: 7826612

Claim:
A method for a computer having a processor and a memory, the method comprising: determining with the processor a first product for a portion of a first operand and a portion of a second operand located in the memory; prefixing the first product with selected bits; determining a second product from the prefixed first product; performing a bit slicing procedure to produce a product P from eight word values w s and eight lookup tables T i , as follows: P = [ p c : P v ] ← ∑ i = 1 8 ⁢ T i ⁡ ( w s ( i ) ) + [ c : r ] wherein the value p c represents accumulated carry values resulting from the additions of the lookup tables and the tail R=[c:r] where c is 1 bit long and r is k words long; performing modular reduction of the second product; and providing the reduced second product to a multiplication portion of an encryption process.