Patent ID: 8854346

Claim:
A pixel circuit comprising: a display element unit including a unit display element; an internal node that is a part of the display element unit and holds a voltage of pixel data applied to the display element unit; first to fourth transistor elements, each of the first to fourth transistor elements having a first terminal, a second terminal, and a control terminal that controls conduction between the first and second terminals; a first switch circuit that transfers the voltage of the pixel data supplied from a data signal line to the internal node through at least the fourth transistor element; a second switch circuit that transfers a voltage supplied to a predetermined voltage supply line to the internal node without passing through the fourth transistor element; and a control circuit that holds a predetermined voltage depending on the voltage of the pixel data held by the internal node at one end of a first capacitor element and controls on/off of the second switch circuit, wherein the second switch circuit includes the first transistor element and the third transistor element, the control circuit includes the second transistor element, the second switch circuit is configured by a series circuit of the first transistor element and the third transistor element, the control circuit is configured by a series circuit of the second transistor element and the first capacitor element, one end of the first switch circuit is connected to the data signal line, one end of the second switch circuit is connected to the voltage supply line, the other ends of the first and second switch circuits and the first terminal of the second transistor element are connected to the internal node, the control terminal of the first transistor element, the second terminal of the second transistor element, and one end of the first capacitor element are connected to each other, the control terminal of the second transistor element is connected to a first control line, the control terminal of the fourth transistor element is connected to a scanning signal line, the control terminal of the third transistor element is connected to a second control line through a delay circuit, and the other terminal of the first capacitor element is connected to the second control line without passing through the delay circuit.