Patent ID: 7098133

Claim:
A method of forming a copper wiring in a semiconductor devices, the method comprising: forming damascene patterns in an interlayer insulating film which is formed on a substrate; sequentially forming a copper barrier metal layer and a copper seed layer on the surface of the interlayer insulating film including the damascene patterns; performing a copper electroplating process in an electroplating apparatus to fill the damascene patterns with a copper layer by applying a negative (−) power supply to the substrate; performing a copper electro-polishing process to remove the copper layer and the copper seed layer on the interlayer insulating film in the same electroplating apparatus that the copper electroplating process is performed by applying a positive (+) power supply to the copper layer and the copper barrier layer on the interlayer insulating film without the use of a pad so that the copper electro-polishing process is automatically stopped and the copper layer and the copper seed layer is remained in the damascene patterns when the copper barrier metal layer is exposed; and polishing the copper barrier metal layer on the interlayer insulating film by means of a chemical mechanical polishing process until the surface of the interlayer insulating film is exposed.