Patent ID: 7884479

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect; and a second metallization structure over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises nickel and electroplated copper.