Patent ID: 6965537

Claim:
A method of refreshing an array of memory cells arranged in rows and columns in a dynamic random access memory (“DRAM”) device, the method comprising: alternately refreshing the memory cells in the array in either a normal operating mode or a reduced power refresh mode; refreshing the memory cells in a first plurality of the rows at a first rate in the normal operating mode; refreshing the memory cells in a second plurality of the rows at a second rate in the reduced power refresh mode, the second rate being significantly slower than the first rate; prior to transitioning from the normal operating mode to the reduced power refresh mode: reading data from the memory cells in a third plurality of the rows; generating syndromes for the data read from the memory cells in the third plurality of the rows; and storing the syndromes; and after transitioning from the reduced power refresh mode to the normal operating mode: reading data from the memory cells in a fourth plurality of the rows; obtaining the stored syndromes; using the obtained syndromes to check for errors in the data read from the memory cells; using the obtained syndromes to correct any data read from the memory cells that have been found to be in error thereby providing corrected data; and writing the corrected data to the memory cells in the array.