Patent ID: 8912093

Claim:
A method of forming a semiconductor device having a via disposed in an active area and a first trench disposed in a die seal area, the method comprising: filling the via and the first trench with an underlayer resist; performing an underlayer etch of the underlayer resist in the via and the first trench to remove a portion of the underlayer resist from the via and the first trench; resist patterning a metal material in the active area to define a second trench overlapping with the via, and in the die seal area to cover the first trench; performing a tetraethylorthosilicate (TEOS) etch of the active area and the die seal area; and performing an ash and SiN etch of the active area and the die seal area, wherein the metal material in the first trench protects the first trench during the TEOS etch.