Patent ID: 7572684

Claim:
A nonvolatile memory device comprising: a substrate comprising a cell region, a low voltage region, and a high voltage region; a ground selection transistor, a string selection transistor, and a cell transistor in the cell region, a low voltage transistor in the low voltage region, and a high voltage transistor in the high voltage region; a common source contact on an impurity region of the ground selection transistor, and a first low voltage contact on an impurity region of the low voltage transistor; a bit line contact on an impurity region of the string selection transistor, and a first high voltage contact on an impurity region of the high voltage transistor; a bit line on the bit line contact; a first interlayer insulating layer on the substrate; and a second interlayer insulating layer on the first interlayer insulating layer; wherein the common source contact and the first low voltage contact penetrate the first interlayer insulating layer, and wherein the bit line contact and the first high voltage contact penetrate the first interlayer insulating layer and the second interlayer insulating layer, and wherein heights of the common source contact and the low voltage contact are lower than heights of the bit line contact and the first high voltage contact.