Patent ID: 8810282

Claim:
A comparator, comprising: a first comparator stage configured to receive a first input voltage and a second input voltage, the first comparator stage comprising: a first input transistor, wherein a gate of the first input transistor is configured to receive the first input voltage; a second input transistor, wherein a gate of the second input transistor is configured to receive the second input voltage, and wherein a source of the first input transistor is electrically connected to a source of the second input transistor; a first inverting gain circuit including an input and an output, wherein the input of the first inverting gain circuit is electrically connected to a drain of the first input transistor; a first capacitor having a first end electrically connected to the drain of the first input transistor and a second end electrically connected to the output of the first inverting gain circuit; a second inverting gain circuit including an input and an output, wherein the input of the second inverting gain circuit is electrically connected to a drain of the second input transistor; a second capacitor having a first end electrically connected to the drain of the second input transistor and a second end electrically connected to the output of the second inverting gain circuit; a first cascode transistor electrically connected in a signal path between the drain of the first input transistor and the first end of the first capacitor; and a second cascode transistor electrically connected in a signal path between the drain of the second input transistor and the first end of the second capacitor.