Patent ID: 8587270

Claim:
A PWM limiter circuit comprising: a first terminal to which highest duty ratio reference voltage is input; a second terminal to which lowest duty ratio reference voltage is input; a comparator for comparing a voltage input to a third terminal with the highest duty ratio reference voltage or the lowest duty ratio reference voltage; a controller circuit electrically connected to the comparator; a first switch which is turned on when the voltage input to the third terminal is higher than the highest duty ratio reference voltage; a second switch which is turned on when the voltage input to the third terminal is lower than the lowest duty ratio reference voltage; a third switch which is turned on when the voltage input to the third terminal is higher than the lowest duty ratio reference voltage and lower than the highest duty ratio reference voltage; and an output terminal electrically connected to the first switch, the second switch, and the third switch, wherein the first switch comprises a first transistor and a second transistor whose source and drain are short-circuited, wherein the second switch is a transmission gate comprising a third transistor and a fourth transistor, wherein the third switch comprises a fifth transistor and a sixth transistor whose source and drain are short-circuited, wherein gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are electrically connected to the controller circuit, and wherein one of a source or a drain of the first transistor is electrically connected to the first terminal, one of a source or a drain of the third transistor and one of a source or a drain of the fourth transistor are electrically connected to the second terminal, and one of a source or a drain of the fifth transistor is electrically connected to the third terminal.