Patent ID: 8867573

Claim:
A device, the device comprising an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module, wherein the first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchroniser, the first control signal indicating a presence of a packet of data in a first storage location of the buffer, wherein one of the first and second clock boundary modules comprises a multiplexer having inputs connected to outputs of the buffer and an output connected to circuitry forming part of the second domain; and wherein the second clock boundary module comprises: a second controller, operable in response to receiving the first control signal to control said multiplexer to transfer said data from an output of the buffer, and to send a second control signal to the first controller via a second synchroniser, the second control signal indicating transfer of said data, wherein the buffer has a default storage location, said default storage location being a value of the first control signal when the first domain is reset, and wherein the first controller is operable, in response to determining that data transfer from said first controller is complete, to reset the first control signal and the second control signal such that the first control signal and the second control signal identify the default storage location of the buffer and to enter an idle state, wherein resetting the first and second control signals comprises controlling a transfer of dummy packets, said dummy packets containing null information, wherein the number of said dummy packets is sufficient to drive the first control signal and the second control signal to identify the default storage location of the buffer.