Patent ID: 7412670

Claim:
A method of optimizing area on a chip while satisfying timing constraints between nodes of a distributed multiplexed bus interconnect, comprising: searching all possible paths from an output port of a first node to reach an end node of the distributed multiplexed bus interconnect; adding up timing components along each path to reach the end node; maintaining a list of each unique path and an associated delay time with each path; scaling an associated delay time with each path of the distributed multiplexed bus interconnect to select components that occupy a least amount of area on a chip and meet a required timing constraint for that path of the distributed multiplexed bus interconnect, where one or more paths in the distributed multiplexed bus interconnect have both components that have a fixed delay value as well as components that have a scalable delay value; optimizing an amount of signaling wiring present within the distributed multiplexed bus interconnect by eliminating individual signaling wires based upon whether an Intellectual Property core connected to the distributed multiplexed bus interconnect transmits or receives signals from the multiplexed bus interconnect, wherein the multiplexed bus interconnect contains one or more multiplexers to route signals through the multiplexed bus interconnect; and supplying the scaled associated delay time with each path and associated timing constraints of the selected components to a logic synthesis tool.