Patent ID: 8725439

Claim:
A memory controller for controlling a memory device, the memory controller comprising: a transceiving unit configured to receive first interface information regarding an operation of the memory device via a system bus and first state information from the memory device; a calculation unit configured to calculate first performance information based on first detailed information including the first interface information and the first state information and second performance information based on second detailed information including second interface information and second state information; a tuning unit configured to generate the second detailed information based on the first detailed information and select one of the first detailed information and the second detailed information based on the first performance information and the second performance information; and a storage unit configured to store the first detailed information, the second detailed information, the first performance information and the second performance information, wherein the transceiving unit transmits the selected one of the first detailed information and the second detailed information to the memory device, and wherein the first state information and the second state information respectively include state information corresponding to an internal state of a memory cell array of the memory device.