Patent ID: 7596046

Claim:
A data conversion circuit for a semiconductor memory apparatus comprising: a data conversion unit that includes a plurality of latches for storing input data and outputting stored data as output data in response to a clock; and an operation mode selection unit that selects either a first operation mode to convert serial data to parallel data during a write operation or a second operation mode to convert parallel data to serial data during a read operation, to control the data conversion unit, wherein at least one of the plurality of latches selectively receives the serial data as the input data in the first operation mode and receives the parallel data as the input in the second operation mode, wherein, during the first operation mode, the data conversion unit sequentially decreases a delay value according to an order in which the serial data is input, and outputs the parallel data, and during the second operation mode, the data conversion unit receives the parallel data, sequentially increases the delay value according to the order, and sequentially outputs the serial data.