Patent ID: 8868992

Claim:
An apparatus, comprising: a pattern generator including a data generation portion to generate a pseudo-random data pattern to create a worst case effect for a memory test, the data generation portion to include: a linear feedback shift register (LFSR); a pattern buffer; and hardware coupled to the LSFR and to the pattern buffer, wherein the hardware is to be implemented to combine an input from the LSFR and an input from the pattern buffer to generate the data pattern, wherein the data pattern is to be generated by a combination of a first pattern including multiple bits from the LSFR with a second pattern including multiple bits from the pattern buffer via the hardware, wherein the data pattern is to be generated by a selection of a part of the second pattern from the pattern buffer based on a bit from the LSFR, and wherein the data pattern is output from the hardware and is to include a third pattern that is different than the first and second patterns and that is not longer than the second pattern.