Patent ID: 8200911

Claim:
A digital processing device, comprising: n processors, n being a natural number and the same as or larger than 2, wherein the n processors include a main processor and n-1 application processors coupled to the main processor through each separate bus and perform an operation according to a control signal inputted through a control bus; and a shared memory including a storage area having at least one common section coupled to the main processor and the n-1 application processors through each separate bus, and outputting access information related to whether at least one of the n processors is accessing the at least one common section, n access ports corresponding to the n processors, respectively, and an internal controller configured to generate and output to the corresponding processor the access information related to whether the at least one of the n processors is accessing or attempts to access the at least one common section, wherein the storage area further comprises c dedicated sections, respectively, allotted to be permitted to be accessed by a predetermined processor of the n processors, c being a natural number, wherein the at least one common section is an area of the storage area that is accessible individually by k processors, k being a natural number and 2=k=n, during a non-overlapping period of time, and is an area of the storage area for writing or reading operation result values to be communicated between the n processors, wherein the main processor performs a processing operation by accessing a first dedicated section of the c dedicated sections until an operation result value is computed per a processing unit for all operation result values, and writes each computed operation result value in the at least one common section once each operation result value is computed, whereby, during access of the at least one common section by the main processor, the internal controller provides to the n-1 application processors through one interrupt pin, the access information indicating access of the at least one common section by the main processor while the main processor is accessing the at least one common section, and wherein subsequently the n-1 application processors access the at least one common section, read the written operation result values of the at least one common section, maintain the access to the at least one common section until all operation result values written in the at least one common section are read, write the read operation result values in a second dedicated section of the c dedicated sections, and perform an operation corresponding to the processing command received from the main processor, whereby, during access of the at least one common section by the n-1 processors, the internal controller provides to the main processor through another interrupt pin, the access information indicating the access of the at least one common section by the n-1 application processors while the n-1 application processors are accessing the at least one common section.