Patent ID: 7285807

Claim:
A semiconductor device, comprising: a substrate having a source contact covering a substantial portion of a bottom surface thereof; a first buffer layer formed over said substrate; an isolation layer formed over said first buffer layer; a first spacer layer formed over said isolation layer; a second buffer layer formed over said first spacer layer; a first barrier layer formed over said second buffer layer; a second spacer layer formed over said first barrier layer; a first lateral channel formed over said second spacer layer; a third spacer layer formed over said first lateral channel; a fourth spacer layer formed over said third spacer layer; a second lateral channel formed over said fourth spacer layer; a fifth spacer layer formed over said second lateral channel; a sixth spacer layer formed over said fifth spacer layer; a third lateral channel formed over said sixth spacer layer; a seventh spacer layer formed over said third lateral channel; a second barrier layer formed over said seventh spacer layer; a recess layer formed over said second barrier layer; an etch-stop layer formed over said recess layer; first and second source/drain contact layers formed over said etch-stop layer; a source interconnect that connects said first, second and third lateral channels to said substrate operable to provide a low resistance coupling between said source contact and said first, second and third lateral channels; a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer; a dielectric layer formed over said gate, and said first and second source/drain contact layers; a drain post located in a drain via formed through said dielectric layer and over said first and second source/drain contact layers; a drain contact coupled to said drain post; and; a Schottky diode having a first terminal coupled to said source contact and a second terminal coupled to said drain contact.