Patent ID: 8726088

Claim:
A method for processing booting errors for a computer having multiple voltage regulator downs (VRDs), comprising: reading a boot sequence which comprises multiple power-on stages, and each power-on stage corresponding to a boot voltage and one of the VRDs; performing the power-on stages according to the boot sequence, and determining whether an output voltage of the VRD corresponding to each power-on stage is equal to the corresponding boot voltage; and when the output voltage of any one of the VRDs is not equal to the corresponding boot voltage, performing a debugging procedure, wherein the debugging procedure comprises: reading a processing mode parameter; when the processing mode parameter is a first parameter value, performing the following steps: maintaining the computer in a debugging state that the output voltage is not equal to the boot voltage; and outputting a first light driving signal; and when the processing mode parameter is a second parameter value, performing the following steps: setting the debugging state as the previous successfully performed power-on stage and maintaining the computer in such stage; and outputting a second light driving signal.