Patent ID: 8519764

Claim:
A shift register comprising a plurality of bistable circuits each having a first state and a second state and connected in series with each other, in which the plurality of bistable circuits sequentially become in the first state based on at least four-phase clock signals including two-phase clock signals which are provided as a first clock signal and a second clock signal to odd-order stage bistable circuits out of the plurality of bistable circuits, and two-phase clock signals which are provided as the first clock signal and the second clock signal to even-order stage bistable circuits out of the plurality of bistable circuits, wherein each bistable circuit includes: an output node that outputs a state signal indicating either one of the first state and the second state; an output-control switching element in which the first clock signal is provided to a second electrode, and a third electrode is connected to the output node; a first first-node charge unit for charging a first node connected to a first electrode of the output-control switching element based on a state signal outputted from a pre-stage bistable circuit of each bistable circuit concerned; a second first-node charge unit for charging the first node based on a state signal outputted from a next-stage bistable circuit of each bistable circuit concerned; a first first-node discharge unit for discharging the first node based on a state signal outputted from a bistable circuit of a third stage after each bistable circuit concerned, and a second first-node discharge unit for discharging the first node based on a state signal outputted from a bistable circuit of a third stage before each bistable circuit concerned.