Patent ID: 7451363

Claim:
A semiconductor integrated circuit comprising: a plurality of memory macros and a redundant memory macro for repairing the plurality of memory macros, each of the plurality of memory macros comprising: a memory cell array connected to word lines and bit lines; a row decoder coupled to the memory cell array through the word lines; and a redundant circuit that has means for replacing a defective bit line of the memory cell array by an adjacent normal bit line or a redundant bit line and outputs defect information to a redundant signal line; the redundant memory macro comprising: a redundant memory cell array connected to redundant word lines, provided internally to the redundant memory macro, and the redundant bit line; a first word line connection circuit that connects the word lines in a first memory macro of the plurality of memory macros to the redundant word lines in response to the defect information on the redundant signal line of the fist memory macro; and a second word line connection circuit that connects the word lines in a second memory macro of the plurality of memory macros to the redundant word lines in response to the defect information on the redundant signal line of the second memory macro, wherein the redundant memory macro is connected to the first and the second memory macro via a first and a second set of signal lines, each set of signal lines including the corresponding memory macro word lines, redundant bit line, and redundant signal line, and at least one of the plurality of memory macros has a different number of word lines from the number of word lines of the other memory macros, and a word line that is not used in the redundant memory macro is connected to a ground potential.