Patent ID: 7185338

Claim:
In a computer system having a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, comprising: a set of K global registers, wherein a register is a global register if it is visible to each of the plurality of N threads of instructions, K being an integer; a plurality of K by N busy bit memory elements, each N elements corresponding to one of the set of K global registers; processor logic to set busy bit memory elements for global registers that are used in more than one of the plurality of N threads of instructions; processor logic to stall a read from global register if a thread of the plurality of N threads of instructions reading that global register is a speculative thread and at least one busy bit for a prior thread and for that global register is set; and processor logic to clear a busy bit for a thread of the plurality of N threads of instructions and a global register of the set of K global registers when the thread writes the corresponding global register.