Patent ID: 7984204

Claim:
A programmable multi-stage pipelined Direct Memory Access controller, comprising: a data load unit configured for performing a load operation; a data computation unit configured for performing a data conversion and the data computation unit being pipeline connected in sequence to the data load unit; a data store unit configured for performing a store operation with data from the data computation unit, and the data store unit being pipeline connected in sequence to the data computation unit, wherein at least a portion of the load operation and at least a portion of the store operation are performed concurrently with the data conversion within the programmable multi-stage pipelined Direct Memory Access controller; a double buffering connection between the data load unit and the data computation unit, and between the data computation unit and the data store unit, and configured for performing burst load and burst store operations on the data, wherein each double buffering connection comprises a dual port circular First In, First Out (FIFO) memory with a user-selectable fullness threshold to adjust an amount of the data buffered between multiple stages of the Direct Memory Access controller.