Patent ID: 7747936

Claim:
A logic circuit, comprising: a logic module that includes: a functional asynchronous logic block executing a first determined logic function and comprising at least one data input of a number of bits and one output supplying a functional result comprising a number of bits in parallel; and a functional synchronous flip-flop receiving the functional result and supplying a synchronous result that copies the functional result; and a first module for checking an integrity of the functional asynchronous logic block, the first module including: a reduced asynchronous logic block supplying a checking result and comprising an input having a number of bits which is less than the number of bits of the at least one data input of the functional asynchronous logic block and an output having a number of bits which is less than the number of bits of the functional result of the functional asynchronous logic block, the reduced asynchronous logic block performing, relative to its inputs, a corresponding logic function as the functional asynchronous logic block; checking synchronous flip-flops for applying data present at the input of the functional asynchronous logic block to the input of the reduced asynchronous logic block; and a comparison circuit receiving the functional result and the checking result and supplying a first error signal having an active value when the functional result does not correspond to the checking result.