Patent ID: 8724389

Claim:
A non-volatile solid state mass storage device comprising: a substrate; an array of NAND flash memory integrated circuits mounted on the substrate, wherein the NAND flash memory integrated circuits are organized into blocks comprising pages that contain cells and are adapted for storing more than one bit per cell including at least a first bit logically assigned to a first page and at least a second bit logically assigned to a second page, the second page being characterized by slower write times that the first page, wherein each of the NAND flash memory integrated circuits has at any given time a block that is a write target block wherein the write target blocks of the NAND flash memory integrated circuits are simultaneously accessible by a write command; a NAND flash controller adapted to have several I/O channels each functionally coupled to at least one of the NAND flash memory integrated circuits for parallel and simultaneous access of a group of the NAND flash memory integrated circuits in a single write cycle; means for determining a lowest unused page number for each of the write target blocks in the group of NAND flash memory integrated circuits; means for programming a dummy write to at least a first of the write target blocks in a first of the NAND flash memory integrated circuits within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second of the write target blocks in a second of the NAND flash memory integrated circuits in the group of NAND flash memory integrated circuits.