Patent ID: 7020831

Claim:
An add-compare-select circuit, comprising: an adder having an input port, a sum output port, and a carry output port; a first code converter having an input port and an output port, said input port of said first code converter coupled to said sum output port of said adder; a second code converter having an input port and an output port, said input port of said second code converter coupled to said carry output port of said adder; a maximum select circuit having a first input port, a second input port, and an output port, said first input port of said maximum select circuit coupled to said output port of said first code converter and said output port of said maximum select circuit coupled to said input port of said adder; a first decision logic circuit having an input port and an output port, said input port of said first decision logic circuit coupled to said output port of said second code converter; a delay circuit having an input port and an output port, said input port of said delay circuit coupled to said output port of said first decision logic circuit; and a second decision logic circuit having an input port and an output port, said input port of said second decision logic circuit coupled to said output port of said delay circuit and said output port of said second decision logic circuit coupled to said second input port of said maximum select circuit, wherein said first decision logic circuit and said second decision logic circuit are used to compute a preliminary decision value and a final decision value.