Patent ID: 7064982

Claim:
A semiconductor memory device, comprising: a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode, each memory function unit having a retaining region for retaining charges, at least a part of the retaining region existing over one of the diffusion regions; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the first voltage source and the control terminal of the switching transistor, wherein the pull-up circuit is configured in such a manner as to connect the second voltage source to the control terminal of the switching transistor when the pull-up circuit is connected to the second voltage source and the switching transistor does not connect the first voltage source to the output of the negative voltage switching circuit, and the pull-down circuit is configured in such a manner as to connect the first voltage source to the control terminal of the switching transistor when the pull-up circuit is not connected to the second voltage source and the switching transistor connects the first voltage source to the output of the negative voltage switching circuit.