Patent ID: 6901494

Claim:
A memory control translator comprising: a first bus interface for a first memory interface, the first bus interface to couple to a memory control unit; a second bus interface for a second memory interface, the second bus interface to couple to a system memory, the second memory interface differing from the first memory interface; a command decoder and generator coupled between the first bus interface and the second bus interface, the command decoder and generator to decode and translate commands for the first memory interface from the memory control unit into commands for the second memory interface; at least one data buffer coupled between the first bus interface and the second bus interface, the at least one data buffer to store data; at least one address buffer coupled between the first bus interface and the second bus interface, the at least one address buffer to store one or more addresses corresponding to memory locations associated with the data stored in the at least one data buffer; and wherein the memory control translator to synchronize commands, data and addresses between the memory control unit and the system memory to send a buffered write command and its corresponding write data to the system memory for execution upon receipt of another write command from the memory control unit, without waiting for write data associated with the another write command to arrive from the memory control unit.