Patent ID: 7237212

Claim:
A method for identifying realistic-case violating paths in a computationally efficient manner, the method comprising: receiving parametric variation data which describes the variation of timing-related parameters over a chip, wherein using path-specific derating factors to directly identify realistic-case violating paths in the set of all paths in the chip is computationally infeasible; computing region-specific derating factors using the parametric variation data; identifying a set of worst-case violating paths using the region-specific derating factors, thereby automatically identifying paths that are of interest for reducing timing pessimism; computing path-specific derating factors for the set of worst-case violating paths using the parametric variation data, wherein the path-specific derating factors include distance-dependent components; and identifying realistic-case violating paths in the set of worst-case violating paths using the path-specific derating factors, wherein using the path-specific derating factors to identify realistic-case violating paths in the set of worst-case violating paths is computationally feasible; wherein the method reduces the timing pessimism because the method identifies realistic-case violating paths using the fine-grained path-specific derating factors instead of only identifying worst-case violating paths using the coarse-grained region-specific derating factors.