Patent ID: 7625790

Claim:
A method for fabricating a semiconductor structure comprising: forming an insulator layer on a semiconductor layer comprising a semiconductor material; forming a recessed region having two parallel edges within said insulator layer; applying self-assembling block copolymers within said recessed region; forming a set of parallel polymer block lines having a first sublithographic width and containing a first polymeric block component within said recessed region; etching said semiconductor layer employing said set of parallel polymer block lines as an etch mask to form a set of semiconductor fins having a second sublithographic width; forming a plurality of parallel semiconductor fins on said substrate, wherein each of said plurality of parallel semiconductor fins has substantially vertical walls, wherein said substantially vertical sidewalls have a surface orientation at which a carrier mobility is optimized or maximized for said semiconductor material; forming a plurality of gate dielectric portions directly on said substantially vertical walls; and forming a gate electrode abutting said plurality of gate dielectric portions.