Patent ID: 7872297

Claim:
A flash memory device comprising a structure, comprising: a wall-type semiconductor body region formed on a semiconductor substrate; a first dielectric film formed on a surface of said semiconductor substrate and a surface of said wall-type semiconductor body region; a device isolation field dielectric film, said device isolation field dielectric film being formed on said first dielectric film up to a vicinity of a surface of said wall-type semiconductor body region; a body recess region with a predetermined width and a predetermined depth from the surface of said wall-type semiconductor body region, disposed such that recessed channels are formed on the surface and a part of sides of said wall-type semiconductor body region in said body recess region; a tunneling dielectric film formed on the surface and the part of the sides of said wall-type semiconductor body region; a charge storage node formed on an upper region of said body recess region; an inter-electrode dielectric film and a control electrode formed successively; a source/drain formed on an upper region of said wall-type semiconductor body region; a second dielectric film, a contact, and a metal layer, each formed with a predetermined width on a structure formed by said wall-type semiconductor body region, the first dielectric film, the device isolation field dielectric film, said body recess region, the tunneling dielectric film, the charge storage node, the inter-electrode dielectric film and the source/drain, wherein the device isolation field dielectric film of the flash memory device is patterned together with a mask pattern preformed for said body recess region and the first dielectric film.