Patent ID: 8756559

Claim:
A method, comprising: in a computer system, executing logic instructions for: generating a circuit design; simulating operation of the circuit design at a plurality of time slices; determining type 1 damage and type 2 damage for each time slice; providing a total type 1 damage as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage; providing a total type 2 damage as a sum of the type 2 damage for all of the slices in which type 2 damage is greater than type 1 damage; determining a type 1 aging effect based on the total type 1 damage; determining a type 2 aging effect based on the total type 2 damage; adding the type 1 aging effect to the type 2 aging effect to obtain a total aging effect; executing the simulation of the circuit design using the total aging effect to determine if the circuit design provides adequate lifetime performance, wherein the providing the total type 1 damage includes including one half of the type 1 damage in the total type 1 damage for each slice in which the type 1 damage equals the type 2 damage; and the providing the total type 2 damage includes including one half of the type 2 damage in the total type 2 damage for each slice in which the type 2 damage equals the type 1 damage.