Patent ID: 8274157

Claim:
A semiconductor device comprising: a plurality of multi-layer interconnects formed over a semiconductor substrate; a passivation film formed over the semiconductor substrate to cover the multi-layer interconnects; a plurality of redistribution interconnects formed over the passivation film; and a first insulating film formed over the passivation film so as to cover the redistribution interconnects, wherein the plurality of redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, wherein each of the first patterns is electrically coupled to a corresponding multi-layer interconnect in a first opening portion formed in the passivation film over a part of the uppermost-level interconnect of the corresponding multi-layer interconnect, wherein the second patterns are electrically separated from the multi-layer interconnects, wherein a part of each of the first patterns is exposed in a second opening portion formed in the first insulating film over the part of the first pattern, and wherein the first patterns and the second patterns are coexistent within the plane of the semiconductor substrate.