Patent ID: 7570081

Claim:
A multiple-output static logic gate computing a NAND of a plurality of inputs and subfunctions thereof, the logic gate comprising: a plurality of NMOS transistors connected serially between ground and a first output, the gate of each of the plurality of NMOS transistors connected to one of the plurality of inputs; a corresponding plurality of PMOS transistors, the gate of each PMOS transistor from the corresponding plurality being connected to one of the inputs, each PMOS transistor from the corresponding plurality connecting a positive voltage to the first output, each input being connected to a transistor from the corresponding plurality; and a subfunction plurality of PMOS transistors, the gate of each PMOS transistor from the subfunction plurality being connected to one of the inputs, each PMOS transistor from the subfunction plurality having terminals connected between a positive voltage and a subfunction output; wherein the first output is a NAND computation of all the inputs; wherein the subfunction output is a NAND computation of a subset of the inputs.