Patent ID: 8359527

Claim:
A signal processing apparatus comprising: an analog-to-digital converter (ADC) to convert an analog signal to a digital signal; a filter that is communicatively coupled with the ADC to produce a filtered digital signal based on the digital signal; a buffer that is communicatively coupled with the filter to store a group of signals, the group of signals comprising the filtered digital signal and one or more previous signals; a detector to interpret the filtered digital signal as first discrete values; a controller configured to determine whether the first discrete values are adequately indicated based on an output of the detector, and initiate a retry mode when the first discrete values are not adequately indicated; and an averager that is communicatively coupled with the buffer to produce a new signal in the retry mode, the new signal being determined based on an average of at least a portion of the group of signals, wherein the detector is configured to interpret the new signal as second discrete values in the retry mode, wherein the controller is configured to determine whether the second discrete values are adequately indicated based on a measurement of differences between hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal, and wherein the controller is configured to selectively exclude a signal of the group of signals from the average.