Patent ID: 6906372

Claim:
A semiconductor device comprising: an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate; said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer; an impurity diffusion source buried in said laterally receded portion of said groove to be contacted with said portion of the bottom surface of said semiconductor layer; a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode; and a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove, for constitution of a DRAM cell together with said transistor, wherein said groove is formed deep enough to reach the inside of said semiconductor substrate after penetration through said dielectric film, wherein a buried strap for use as said impurity diffusion source is formed and buried in said laterally receded portion overlying said storage electrode to be contacted with said semiconductor layer only at the bottom surface thereof, wherein said buried strap is covered with a cap insulation film with the gate electrode of said transistor embedded to overlie said cap insulation film, and wherein said buried strap comprises a first strap buried on said storage electrode and a second strap stacked on the first strap and buried in said laterally receded portion being in contact with said semiconductor layer only at the bottom surface thereof.