Patent ID: 7243250

Claim:
An electronic apparatus having a semiconductor integrated circuit having a first circuit and a second circuit, the second circuit having a normal operation state and a standby state, the electronic apparatus comprising: power controlling means for supplying power to the first circuit and the second circuit in the normal operation state and for supplying power to only the first circuit in the standby state; first and second clock generators disposed in the first circuit and configured to generate first and second clock signals; a third clock generator disposed in the second circuit and configured to generate a third clock signal; clock controlling means for controlling a generation of first, second and third clock signals so as to generate the first clock signal, the second clock signal, and the third clock signal in the normal operation state and only the first clock signal in the standby state; a first register that is disposed in the first circuit and operated with the first clock signal; a second register that is disposed in the first circuit and operated with the second clock signal; and controlling means for copying contents that are set to the first register to the second register when the state of the second circuit changes from the standby state to the normal operation state, wherein the second clock signal is provided to the first circuit and the second circuit, and the third clock generator generates the third clock signal only when the third clock generator receives the second clock signal.