Patent ID: 7745868

Claim:
A semiconductor device comprising: a semiconductor substrate; a MOS transistor having source and drain regions that are provided in the semiconductor substrate; a first inter-layer insulator over the MOS transistor, the first inter-layer insulator having first contact holes that reach the source and drain regions; cell contact plugs in the first contact holes, the cell contact plugs contact with the source and drain regions; a second inter-layer insulator over the first inter-layer insulator and the cell contact plugs, the second inter-layer insulator having second contact holes that reach the cell contact plugs; contact plugs each having first and second portions, the first portion being in the second contact hole, the second portion extending over the second inter-layer insulator; metal barrier layers that cover the upper surfaces of the second portions of the contact plugs; and capacitors each having a bottom electrode layer, a capacitive insulating layer and a top electrode layer, the bottom electrode layers each having a contact portion that contacts with the metal barrier layer.