Patent ID: 8212539

Claim:
An interleaved converter comprising: a parallel converter including a plurality of converters connected in parallel, each of the plurality of converters including a reactor, a switching unit, and a rectifier; an input power source configured to supply power to the parallel converter; a smoothing capacitor configured to smooth an output of the parallel converter; an input voltage detector configured to detect an input voltage of the parallel converter, and thereby to output an input voltage signal; an output voltage detector configured to detect an output voltage of the parallel converter, and thereby to output an output voltage signal; and a controller configured to control the parallel converter, wherein the controller includes: an error amplifier configured to compare the output voltage signal with a reference voltage, and thereby to output an error amplification signal; an arithmetic operator configured to perform arithmetic processing based on the input voltage signal, the output voltage signal, and the error amplification signal, and thereby to generate an ON time signal and an OFF time signal; a phase signal generator configured to generate a plurality of phase signals having mutually different phases, based on the ON time signal, the OFF time signal, and the error amplification signal; a pulse generator configured to generate a plurality of pulse-train signals synchronized respectively with the plurality of phase signals, based on the ON time signal, the error amplification signal, and the plurality of phase signals; and a driver configured to drive the switching units in accordance with the plurality of pulse-train signals.