Patent ID: 7375599

Claim:
A signal generating circuit comprising: (a) a relaxation oscillator including switching circuitry operative to alternately generate a first ramp signal that is periodic at a frequency of the relaxation oscillator and a second ramp signal that is periodic at the frequency of the relaxation oscillator and is out of phase with respect to the first ramp signal; and (b) an analog multiplier circuit including i. a first comparator having a first input coupled to receive the first ramp signal and a second input coupled to receive a first reference voltage, ii. a second comparator having a first input coupled to receive the second ramp signal and a second input coupled to receive the first reference voltage, iii. a first flip-flop having a clock input coupled to an output of the first comparator, iv. a second flip-flop having a clock input coupled to an output of the second comparator, v. first reset circuitry for resetting the first flip-flop in response to a first level of the first ramp signal and second reset circuitry for resetting the second flip-flop in response to a second level of the second ramp signal, and vi. a gate circuit for performing a logical ORing function on an output of the first flip-flop and an output of the second flip-flop to produce an output signal that is periodic at a frequency that is a multiple of the frequency of the relaxation oscillator.