Patent ID: 7395476

Claim:
A method for creating test data for testing a packetized cascade memory subsystem, the method comprising: receiving test data at a bus converter, the test data in a parallel bus data format and received via a slow speed bus; converting the test data into a serial packetized data format at the bus converter, the converting the test data resulting in converted test data; and transmitting the converted test data from the bus converter to the memory subsystem via a high speed bus, wherein the high speed bus operates at a faster speed than the slow speed bus, wherein the bus converter includes a standard operating mode for converting serial packetized input data received via the high speed bus into parallel bus output data for output to the slow speed bus and an alternate operating mode for the converting the test data into the serial packetized data format, and wherein the serial packetized input data is consistant in function and timing to the converted test data.