Patent ID: 7541649

Claim:
A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a plurality of first semiconductor layers of a first conductivity type separately formed on the first insulating film; a plurality of second semiconductor layers of a second conductivity type which is opposite to the first conductivity type, formed on the first insulating film, each disposed between adjacent ones of the first semiconductor layers and formed in contact with the first semiconductor layers; a third semiconductor layer of the second conductivity type formed on the first insulating film and formed in contact with the plurality of second semiconductor layers; a plurality of gate electrodes formed on the second semiconductor layers with gate insulating films interposed therebetween; a first wiring layer formed on the third semiconductor layer with a second insulating film interposed therebetween and commonly connecting the plurality of gate electrodes; a fourth semiconductor layer of the second conductivity type formed on the first insulating film, the fourth semiconductor layer being in contact with at least the third semiconductor layer, a length of the fourth semiconductor layer in a lengthwise direction being smaller than a length of the third semiconductor layer in a lengthwise direction; a fifth semiconductor layer of the second conductivity type formed on the first insulating film and isolated from the first semiconductor layers by the fourth semiconductor layer, the fifth semiconductor layer being in contact with the fourth semiconductor layer, the first to fifth semiconductor layers being electrically isolated from the semiconductor substrate by the first insulating film; a second wiring layer formed on the fourth semiconductor layer with a third insulating film interposed therebetween; and a first contact plug formed on the fifth semiconductor layer.