Patent ID: 7941722

Claim:
A method of testing an integrated circuits circuit that includes a processor and an integrated test module, the method comprising: receiving, from an external testing unit, at the integrated test module (ITM), a test case for the processor; in response to receiving the test case from the external testing unit at the integrated test module, loading the test case into random access memory, with the integrated test module operating at an ITM clock rate when loading the test case into the random access memory; receiving, from the external testing unit, at the integrated test module, an initialization signature for the random access memory; in response to receiving the initialization signature from the external testing unit at the integrated test module, loading the initialization signature into a signature section of the random access memory, with the integrated test module operating at the ITM clock rate when loading the initialization signature into the random access memory; executing the test case on the processor, at a processor clock rate, wherein the processor clock rate is independent of the ITM clock rate, and wherein the processor, in response to executing the test case, writes a result signature to the signature section of the random access memory; with the integrated test module, reading the result signature from the signature section of the random access memory; and sending the result signature from the integrated test module to the external testing unit.