Patent ID: 6963244

Claim:
A common mode linearized input stage, comprising: a differential input terminal V in+ ; a differential input terminal V in− , said differential input terminals connected to receive a differential input signal; first and second NPN transistors arranged as a differential transistor pair, the bases of said first and second NPN transistors connected to V in+ and V in− , respectively, the emitters of said first and second NPN transistors connected together at a first node, and the collectors of said first and second NPN transistors conducting respective currents I D1+ and I D1− in response to said differential input signal; first and second PNP transistors arranged as a differential transistor pair, the bases of said first and second PNP transistors connected to V in− and V in+ , respectively, the emitters of said first and second PNP transistors connected together at a second node, and the collectors of said first and second PNP transistors conducting respective currents I D2+ and I D2− in response to said differential input signal; a first tail current source connected to said first node to provide a first tail current I tail1 to said NPN differential transistor pair; a second tail current source connected to said second node to provide a second tail current I tail2 to said PNP differential transistor pair; and a tail current modulation circuit which generates complementary output currents I in1 , I in2 as a function of the difference between the voltages at said first and second nodes; said first tail current source arranged to generate said first tail current I tail1 as a function of I in1 , and said second tail current source arranged to generate said second tail current I tail2 as a function of I in2 , said tail current modulation circuit and said first and second tail current sources arranged such that the magnitudes of tail currents I tail1 and I tail2 increase with an increasing differential input signal.