Patent ID: 7804714

Claim:
A memory cell of an electrically programmable read only memory (EPROM), the memory cell comprising at most two transistors, including: a select transistor that comprises an n-channel metal oxide semiconductor (NMOS) transistor having a gate oxide layer that has a thickness of approximately sixty Angstroms; and a breakdown transistor connected to the select transistor, wherein the breakdown transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor having a gate oxide layer that has a thickness of approximately twenty Angstroms, wherein the gate oxide layer of the PMOS transistor is broken down when exposed to a programming current in a range of ten microamperes to one hundred microamperes, wherein the select transistor sources said programming current on to at least one of a drain, a source and an N well of the breakdown transistor, and a gate of the breakdown transistor is connected to ground.