Patent ID: 7248499

Claim:
A memory array for a non-volatile memory device, the memory array comprising: a first region in which a first memory sub-array is located, the first memory sub-array having NAND flash memory cells coupled to word lines and bit lines corresponding to rows and columns of memory cells; a second region separated from the first region in which a second memory sub-array is located, the second memory sub-array having NAND flash memory cells coupled to word lines and bit lines corresponding to rows and columns of memory cells; a driver region in which word line driver circuits and first row decoder sub-circuits are located, the driver region separating the first and second regions, the word line drivers coupled to the word lines from the first memory sub-array and the word lines from the second memory sub-array and configured to drive the respective word lines responsive to a drive signal and each first row decoder sub-circuit configured to generate a drive signal for a respective word line driver circuits responsive to an enable signal; and a row decoder region in which row decoder circuits are located, the row decoder region adjacent the first region and separated from the driver region by the first region, each row decoder circuit including a second row decoder sub-circuit coupled to a respective first row decoder sub-circuit and configured to generate the enable signal in response to decoding address signals selecting the particular row decoder circuit.