Patent ID: 7288971

Claim:
An integrated circuit comprising: a voltage bias source having at least a first voltage bias and a second voltage bias, wherein the first voltage bias is of higher voltage than the second voltage bias; a first logic cell of current mode logic (CML) having at least a first differential input, a second differential input, and a first differential output, wherein the first logic cell further comprises: a first differential pair of transistors operatively coupled to the first differential input and operatively coupled to the first differential output; a second differential pair of transistors operatively coupled to the second differential input, wherein at least a portion of the second differential pair is operatively coupled to the first differential pair of transistors; and a first active load having an inductive characteristic coupled to the first differential pair of transistors such that the first differential pair of transistors is electrically disposed between the first active load and the second differential pair of transistors, wherein the first active load is operatively coupled to the first voltage bias; and a second logic cell having at least a third differential input and a second differential output: a third differential pair of transistors operatively coupled to the third differential input and to the second differential output, wherein the second differential output of the third differential pair of transistors is operatively coupled to the second differential input of the second differential pair of transistors; and a second active load of current mode logic (CML) having an inductive characteristic coupled to the third differential pair of transistors, wherein the second active load is operatively coupled to the second voltage bias.