Patent ID: 7659567

Claim:
A semiconductor device comprising: a semiconductor substrate which is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed and a memory formation section in which a plurality of memory cells are formed; and a multi-layered insulating layer formed on said semiconductor substrate, said multi-layered insulating layer comprising: a conductive structure formed in said multi-layered insulating layer at said logic-circuit formation section; a plurality of capacitors formed in said multi-layered insulating layer at said memory formation section, said plurality of capacitors comprising: a lower capacitor electrode; a capacitor dielectric layer formed on said lower capacitor electrode; and an upper capacitor electrode formed on said capacitor dielectric layer, said upper capacitor electrode having an uppermost portion that is coplanar with an uppermost portion of said capacitor dielectric layer; a plurality of lower-side connection layers formed below the lower capacitor electrode of said plurality of capacitors at said memory formation section; a logic-circuit-side connection layer formed on or above said conductive structure at said logic-circuit formation section such that the logic-circuit-side connection layer is electrically connected to said conductive structure; a common capacitor electrode layer formed at the memory formation section on or above said plurality of capacitors such that said common capacitor electrode layer is electrically connected to the upper capacitor electrode of said plurality of capacitors; and a capacitor conductive plug covering said uppermost portion of said upper capacitor electrode and said uppermost portion of said capacitor dielectric layer and disposed between said common capacitor electrode and said plurality of capacitors.