Patent ID: 7378888

Claim:
A delay-locked loop circuit comprising: a delay circuit, providing plural different delays corresponding to an input control signal for an input first clock signal, and outputting one of said plural delay signals as a second clock signal; a phase detector detecting the advance or delay in the phase of said second clock signal with respect to said first clock signal, a delay controller, which generating said control signal setting the delay of said delay circuit in a predetermined range in a first mode, and generating said control signal to control the delay of said delay circuit so that the advance or delay in the phase detected by said phase detector is reduced in a second mode, a phase-detection controller setting the advance or delay in the phase of said second clock signal detected by said phase detector in the predetermined range when transition from said first mode to said second mode occurs; a phase-judgment circuit judging the phase state for two signals among plural signals input/output to/from said delay circuit; and a transition-judgment circuit judging whether the transition of the phase state judged with said phase-judgment circuit is a predetermined transition, and, if it is not the predetermined transition, changes the operation mode to said first mode.