Patent ID: 7149857

Claim:
A memory controller comprising: an input queue for receiving a plurality of memory access requests in an originally received order from at least one requestor; a sequence matrix into which the plurality of memory access requests can be arranged, wherein the sequence matrix stores the plurality of memory access requests in a sequenced order; a sequencing unit for arranging a timing sequence of a plurality of memory access requests in the sequence matrix; a conflict detector for detecting whether a conflict or delay would occur among a sequence of memory access requests arranged in the sequence matrix by the sequencing unit, said conflict detector reporting a detected conflict or delay to said sequencing unit such that said sequencing unit rearranges the stored sequenced order of the requests within the sequence matrix when a conflict or delay is detected, the conflict or delay arising from a comparison of one of the memory access requests in the sequence matrix with a second memory access request in the sequence of memory access requests arranged in the sequence matrix or with one of a plurality of non-executed memory access requests that have previously been sequenced in the sequence matrix; an execution queue in which a plurality of commands are extracted from the memory access requests, each memory access request comprising either a read or write command and data control commands, the plurality of commands being arranged in an execution order determined by the sequence matrix, the execution order further arranged such that a data control command from a memory access request is executed before a read or write command from a previous memory access request is executed; a read return queue for keeping track of the original received order of the memory access requests after execution of the memory access requests from the execution queue in the execution order, and for returning requested data to the at least one requestor in the originally received order of the memory access requests; and a returned data buffer for holding requested data read from a memory until the data is to be returned to the requestor of the associated access request, wherein the controller is configured to interface with memory having multiple memory clock speeds.