Patent ID: 7657713

Claim:
A memory system comprising: a synchronous memory; and a packet controller receiving a plurality of data packets via a plurality of packet pins, respectively, when a packet enable signal is activated, and comprising: a decoding and detecting circuit outputting decoding signals and generating a latch enable signal having a first or a second logic level; a delay circuit receiving the decoding signals and outputting delayed decoding signals; a selector circuit receiving the decoding signals and the delayed decoding signals and providing either the decoding signals or the delayed decoding signals to the synchronous memory as control signals in response to the latch enable signal; and an address latch circuit latching bits of the data packets in response to the latch enable signal when the latch enable signal has the first logic level, and providing at least some of the latched bits to the synchronous memory as address signals when the latch enable signal has the first logic level, wherein the decoding and detecting circuit receives first bits of the data packets through the packet pins respectively, generates the latch enable signal having the first logic level when the first bits indicate an operation requiring address information, and generates the latch enable signal having the second logic level when the first bits indicate an operation not requiring address information.