Patent ID: 7760845

Claim:
A shift register comprising: at least two clock transmission lines configured for transmitting a first clock pulse and a second clock pulse, wherein the first clock pulse and the second clock pulse have an amplitude, a duty ratio, and a frequency, and wherein the first clock pulse has an inverse phase relative to a phase of the second clock pulse; a plurality of stages receiving the clock pulses from the at least two clock transmission lines, and outputting a plurality of output-signals in sequence, wherein a first alternating stage of the plurality of stages receives the first clock pulse, and wherein a second alternating stage of the plurality of stages receives the second clock pulse; wherein each of the plurality of stages comprises: a voltage high input, a voltage low input, a first output, a second output, and an input, wherein the voltage high input receives a high-level voltage signal, wherein the voltage low input receives a low-level voltage signal, and wherein a first output of the first alternating stage inputs a signal into the input of the second alternating stage; an input circuit configured receiving one of the first clock pulse and the second clock pulse for generating a pulse signal to the second output, wherein the pulse signal is configured according to said one of the first clock pulse and the second clock pulse, and an input from one of the first alternating stage and the second alternating stage; a first inverter comprising an input terminal connected to the second output; a voltage circuit configured for providing a high-level signal and a low-level signal under control of the input, an output of the first inverter, the first output, and the second output to a common node of the voltage circuit; and a second inverter comprising an output connected to the first output, and an input connected to the common node.