Patent ID: 8367553

Claim:
A method for manufacturing a through-silicon via (TSV), the method comprising: providing a stack structure having a substrate, an internal layer dielectric (ILD) layer and a dielectric planarization stopping layer, wherein an opening is formed in the stack structure penetrating through the ILD layer, the dielectric planarization stopping layer and further extending into the substrate; providing an insulator layer and a metal barrier sequentially on the stack structure and the sidewalls of the opening; providing a top metal layer formed on the stack structure to fill the opening; conducting a first planarization process stopping on the metal barrier to remove a portion of the top metal layer, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer; conducting a second planarization process stopping on the dielectric planarization stopping layer to remove portions of the top metal layer, the metal barrier and the insulator layer, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric planarization stopping layer; and conducting a third planarization process stopping on the ILD layer to remove the dielectric planarization stopping layer and portions of the top metal layer, the metal barrier and the insulator layer, wherein the third planarization process has a polishing rate for removing the dielectric planarization stopping layer greater than that for removing the ILD layer.