Patent ID: 8032669

Claim:
A universal DMA (Direct Memory Access) engine architecture for processing either receive or transmit communications, wherein a DMA engine configured according to the architecture comprises: a software interface for enabling software operating on a host to manage the DMA engine; a client interface for interacting with either a receive client or a transmit client; a data plane configured to perform direct memory access for either receive or transmit communications; and a separate software-posted descriptor ring that is statically and uniquely bound to the DMA engine and, if the DMA engine is configured as a receiver, a hardware-posted descriptor ring bound to the DMA engine, wherein the hardware-posted descriptor ring is shared between the DMA engine and any other DMA engines that are configured as receivers, and wherein the hardware-posted descriptor ring is not bound to the DMA engine if the DMA engine is configured as a transmitter; a control plane configured to fetch to a memory for the DMA engine software-posted descriptors from the software-posted descriptor ring in a memory for the host and to post hardware-posted descriptors to the hardware-posted descriptor ring; wherein the software-posted descriptors include transmit packet and receive buffer information and the hardware-posted descriptors include receive packet information.