Patent ID: 8723322

Claim:
An integrated circuit comprising: a semiconductor substrate; an active device having a portion in said semiconductor substrate; a passivation layer on said semiconductor substrate, wherein said passivation layer comprises a nitride; a first conductive interconnect on said passivation layer; a second conductive interconnect on said passivation layer; a dielectric layer on said passivation layer, on a first surface and at least one sidewall of said first conductive interconnect, and on a first surface and at least one sidewall of said second conductive interconnect; a re-deposited seasoning layer on at least one sidewall of said dielectric layer; a titanium-containing layer on said dielectric layer and aligned with said first surfaces of said first and second conductive interconnects, said titanium-containing layer on the re-deposited seasoning layer, in which the re-deposited seasoning layer is surrounded by portions of the dielectric layer and said titanium-containing layer; a conductive seed layer on said titanium containing layer and aligned with said first surfaces of said first and second conductive interconnects; and a third conductive interconnect on said conductive seed layer and aligned with said first surfaces of said first and second conductive interconnects.