Patent ID: 8120972

Claim:
A test circuit for a semiconductor memory apparatus of an open bit-line structure, the test circuit comprising: a compression part configured to, in response to test data read from a plurality of memory cells included in a pair of adjacent cell mats and a compression control signal outputted from a compression control signal generating part, compress the test data that are read from the memory cells that share a sense amplifier block and sequentially output compression test signals, wherein the sense amplifier block is disposed between the pair of adjacent cell mats, bit-lines of the adjacent cell mats are configured to be connected in common to the sense amplifier block, and the compression part includes: a first compression unit confiured to receive test data outputted from memory cells connected to even numbered bit-lines for the plurality of memory cells included in the pair of adjacent cell mats and output a first compression data: and a second compression unit configured to receive test data outputted from memory cells connected to odd numbered bit-lines for the plurality of memory cells included in the pair of adjacent cell mats and output a second compression data.