Patent ID: 7838355

Claim:
A method of forming an integrated circuit structure, said method comprising: patterning a first insulator layer semiconductor layer stack to form, on a substrate, a first semiconductor body, having a first sidewall and a first cap layer, and a second semiconductor body, having a second sidewall and a second cap layer; selectively removing portions of said first cap layer to expose upper edges of said first semiconductor body and leaving said second cap layer intact; depositing a second insulator layer different from said first insulator layer to form a first isolation region adjacent to said first sidewall and a second isolation region adjacent to said second sidewall; performing a wet etch process to selectively remove said first cap layer and said second cap layer so as to expose top surfaces of said first semiconductor body and said second semiconductor body; and performing additional processing steps such that any one of the following occurs: a divot is formed only in said second isolation region and not in said first isolation region; and a first divot is formed in said first isolation region and a second divot, having a greater depth than said first divot, is formed in said second isolation region.