Patent ID: 7333371

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit for reading said memory cell array, wherein said sense amplifier circuit includes: a first transistor disposed between a bit line of said memory cell array and a sense node, said first transistor being driven by a voltage generating circuit including a boost circuit on reading data to transfer a bit line voltage determined in response to data of a selected memory cell to said sense node; a second transistor coupled to said sense node for precharging said sense node up to a power supply voltage prior to bit line data sensing; a data latch connected to said sense node and configured to judge a level of a bit line voltage transferred to said sense node using a threshold value determined by said power source voltage and store a sensed data therein; a capacitor with a capacitance coupling ratio to said sense node, a first end thereof being connected to said sense node, a second end thereof being alternatively given a first voltage or a second voltage higher than the first voltage, wherein prior to the bit line data sensing, said first voltage is changed to said second voltage at said second end to boost said sense node to a boosted voltage determined by said capacitance coupling ratio, and wherein after finishing said bit line data sensing, said second voltage applied to said second end is changed to said first voltage to step down the sense node.