Patent ID: 8279787

Claim:
A packet processing apparatus comprising: a packet buffer unit that temporarily holds packet data, the packet buffer unit outputting an accumulation amount signal indicating an amount of packet data accumulated in the packet buffer unit; a packet processing unit that processes packet data output from the packet buffer unit; a clock supply unit that supplies a clock signal to the packet processing unit; a buffer vacant measurement unit that receives the accumulation amount signal supplied from the packet buffer unit, and measures a buffer vacant time indicating a duration in which the accumulated amount is zero based on the accumulation amount signal supplied from the packet buffer unit; and, a comparison unit that compares the buffer vacant time with a predetermined comparison reference time and controls an operational state of the clock supply unit based on the comparison results, such that the supply operation of the clock signal is suspended or the clock signal having a frequency less than a threshold frequency being supplied to the packet processing unit during a period in which the buffer vacant time exceeds the predetermined comparison reference time, wherein the predetermined comparison reference time is a time required to process the packet data in the packet processing unit, and wherein the comparison unit controls the operational state of the clock supply unit such that the supply of the clock signal is suspended when the buffer vacant time is longer than the comparison reference time.