Patent ID: 7216277

Claim:
A method of configuring a programmable logic device (PLD) comprising a first random access memory (RAM) circuit that includes a first array of rows and columns of RAM cells and a first redundant column of the RAM cells, the method comprising: initiating a configuration sequence for the PLD; initiating a built in self test (BIST) procedure on the first array; setting, when an error associated with the first array is reported by the BIST procedure, a first error flag in a first volatile memory circuit associated with a first defective column of the RAM cells in the first array; wherein a respective error flag is associated with each column of RAM cells in the first array; loading first PLD configuration data into the first RAM circuit, wherein when the first error flag is set the first PLD configuration data bypasses the first defective column of the RAM cells and a first portion of the first PLD configuration data is loaded into the first redundant column of the RAM cells; and wherein the loading comprises generating for each column of RAM cells a respective selection signal as a function of the error flag associated with each column and a selection signal carried in from an adjacent column of RAM cells, and selecting for input to each column of RAM cells in response to the respective selection signal, one of a first set of bits of configuration data addressed to the column of RAM cells and a second set of bits of configuration data addressed to the adjacent column.