Patent ID: 8421083

Claim:
A semiconductor device comprising: a gate electrode layer provided over an insulating surface; a gate insulating layer provided over the gate electrode layer; a first oxide semiconductor layer provided over the gate insulating layer; a second oxide semiconductor layer provided over and in contact with the first oxide semiconductor layer; an oxide insulating layer provided over the second oxide semiconductor layer; a source electrode layer and a drain electrode layer which are provided over the oxide insulating layer, and are in contact with the second oxide semiconductor layer; a planarizing insulating layer provided over the source electrode layer and the drain electrode layer; and a conductive layer provided over the planarizing insulating layer and connected with the gate electrode layer, wherein the oxide insulating layer includes a first region and a second region, wherein the first region is in contact with the second oxide semiconductor layer so as to overlap with the gate electrode layer, and wherein the second region is in contact with the second oxide semiconductor layer so as to cover end portions of the second oxide semiconductor layer.