Patent ID: 6972492

Claim:
A method of forming a metal on metal capacitor structure for an integrated circuit device, the method comprising: forming a dual damascene structure, where the structure has a first conductive portion comprising copper material that is separated by a dielectric material from a second conductive portion, the second conductive portion is coupled to the first conductive portion underlying the dielectric material through a third conductive portion, the first conductive portion, the dielectric material, and the second conductive portion forming a substantially planar surface region opposing the third conductive portion, the first conductive portion and the second conductive portion coupled through the third conductive portion define a first electrode; selectively removing the dielectric material between the first conductive portion and the second conductive portion to form an opening defined by the first conductive portion and the second conductive portion; forming an insulting layer within with opening to define a capacitor dielectric layer therefrom; forming a copper layer overlying the insulating layer to a height above the substantially planar surface to form a second electrode; and planarizing the copper layer to define the second electrode.