Patent ID: 8829966

Claim:
A current reuse frequency divider, comprising: a first latch circuit, comprising a first transistor pair and a second transistor pair, wherein the first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides a frequency of the first differential oscillation signal to generate a second differential oscillation signal; and a second latch circuit, coupled to the first latch circuit, and comprising a third transistor pair and a fourth transistor pair, wherein the second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal, wherein the first latch circuit further comprises: a first transistor, having a first source/drain; a second transistor, having a first source/drain, wherein the first transistor and the second transistor form the first transistor pair; a third transistor, having a gate coupled to the first source/drain of the first transistor, a first source/drain coupled to the first source/drain of the second transistor, and a second source/drain coupled to a second source/drain of the second transistor; and a fourth transistor, having a gate coupled to the first source/drain of the second transistor, a first source/drain coupled to the first source/drain of the first transistor, and a second source/drain coupled to a second source/drain of the first transistor, wherein the third transistor and the fourth transistor form the second transistor pair.