Patent ID: 8097884

Claim:
A semiconductor device comprising: a driver circuit including a first thin film transistor and a pixel portion including a second thin film transistor; the first thin film transistor including a first semiconductor layer, a gate insulating film over the first semiconductor layer, and a first gate electrode having a tapered side surface over the gate insulating film, wherein the first semiconductor layer contains a first channel forming region, a pair of first impurity regions, a pair of second impurity regions, and a pair of third impurity regions; and the second thin film transistor including a second semiconductor layer, the gate insulating film over the second semiconductor layer, and a second gate electrode having a tapered side surface over the gate insulating film, wherein the second semiconductor layer contains a second channel forming region, a pair of fourth impurity regions, and a pair of fifth impurity regions, wherein the pair of first impurity regions through the pair of fifth impurity regions contain an impurity element that imparts a conductivity, wherein the pair of first impurity regions are provided so as to interpose the first channel forming region, wherein the pair of second impurity regions are provided so as to interpose the first channel forming region and the pair of first impurity regions, wherein the pair of third impurity regions are provided so as to interpose the first channel forming region, the pair of first impurity regions and the pair of second impurity regions, wherein the pair of fourth impurity regions are provided so as to interpose the second channel forming region, wherein the pair of fifth impurity regions are provided so as to interpose the second channel forming region and the pair of fourth impurity regions, wherein the first gate electrode overlaps the pair of the first impurity regions, and does not overlap the pair of second impurity regions, wherein the impurity element contained in the pair of third impurity regions is at a higher concentration than the impurity element contained in the pair of first impurity regions and the pair of second impurity regions, wherein the second gate electrode does not overlap the pair of fourth impurity regions, and wherein the impurity element contained in the pair of fifth impurity regions is at a higher concentration than the impurity element contained in the pair of fourth impurity regions.