Patent ID: 7691694

Claim:
A method for manufacturing a silicon carbide semiconductor device, the method comprising the steps of: preparing a substrate having a first conductive type and made of silicon carbide; forming a first semiconductor layer on the substrate, wherein the first semiconductor layer has the first conductive type and is made of silicon carbide with a low impurity concentration lower than the substrate; forming a first gate layer on a surface of the first semiconductor layer, wherein the first gate layer has a second conductive type and is made of silicon carbide; forming a first channel layer on the substrate to be adjacent to the first gate layer in a planar direction, wherein the first channel layer has the first conductive type; forming a first source layer to connect to the first channel layer electrically, wherein the first source layer has the first conductive type and has a high impurity concentration higher than the first channel layer; forming a second gate layer to be adjacent to the first channel layer, wherein the second gate layer has the second conductive type and is disposed opposite to the first gate layer to sandwich the first channel layer; forming a second channel layer to be adjacent to the second gate layer, wherein the second channel layer has the first conductive type and is disposed opposite to the first channel layer to sandwich the second gate layer; forming a third gate layer to be adjacent to the second channel layer, wherein the third gate layer is disposed opposite to the second gate layer to sandwich the second channel layer; and forming a second source layer to connect to the second channel layer electrically, wherein the second source layer has the first conductive type and has a high impurity concentration higher than the second channel layer, wherein an impurity concentration of the first channel layer is equal to an impurity concentration of the second channel layer, and wherein the impurity concentration of the first channel layer is higher than an impurity concentration of the first semiconductor layer, and lower than an impurity concentration of the second gate layer.