Patent ID: 7957118

Claim:
A method for processing a semiconductor wafer, comprising: providing test data from a plurality of test wafers, the test data including number of wafer cracks observed with a plurality of chucking voltages applied to respective portions of the test wafers by an electrostatic chuck for holding the test wafers, and warpage amounts for each of the plurality of test wafers; for each warpage amount, selecting a plurality of chucking voltages for which the number of cracks observed at that warpage amount in the test data is fewest; measuring data indicating an amount of warpage of an additional wafer; determining at least two different voltages to be applied to respective portions of the additional wafer by an electrostatic chuck that is to hold the additional wafer, based on the amount of warpage and the selected chucking voltages corresponding to the measured amount of warpage; applying the at least two different voltages to hold the respective portions of the additional wafer while performing a fabrication process on the additional wafer.