Patent ID: 7194496

Claim:
A system for producing functions for generating pseudo-random bit sequences, comprising: a memory that stores the steps of a computer program to: extend a length of a shift register to form an extended shift register, wherein the extended shift register is comprised of a plurality of bits of information; copy each bit in the extended shift register to a next higher bit; replace a lowest-order bit of the extended shift register with an EXCLUSIVE-OR operation of at least two other bits in the extended shift register; generate a plurality of bit equations, wherein each of the plurality of bit equations is associated with a bit in the extended shift register, wherein each of the plurality of bit equations comprises an EXCLUSIVE-OR operation of at least two other bits of the extended shift register from an iteration of a predetermined number of iterations of the plurality of bit equations; for each of the plurality of bit equations, replace a bit in the extended shift register with an AND operation between a shift of the contents of the extended shift register, to move the bit to a predetermined position within the extended shift register, and one of a plurality of first bit masks applied to the shifted contents of the extended shift register to isolate the bit; combine each of the plurality of bit equations using an EXCLUSIVE-OR operation; merge shifts of a same shift distance in the combined plurality of bit equations, wherein a plurality of second bit masks is applied to the merged shifts, and wherein each of the plurality of second bit masks comprises an OR operation between the first bit masks associated with the shifts of the same shift distance; remove redundant first and second bit masks from the merged and combined plurality of bit equations, wherein the redundant first and second bit masks zero the same bits as those zeroed by a shift associated with the first and second bit masks; transform at least one of the plurality of first and second bit masks in the merged and combined plurality of bit equations into an associated one of a plurality of third bit masks comprising a sequence of zero bits and a sequence of one bits, when the at least one of the plurality of first and second bit masks is comprised of an absence of the sequence of zero bits and the sequence of one bits; replace the plurality of first, second and third bit masks with bit shift operations in the merged and combined plurality of bit equations, to form a function for generating the pseudo-random bit sequences; generate the pseudo-random bit sequences from the function for generating the pseudo-random bit sequences; a processor for accessing the memory to execute the computer program; and utilizing at least one of the pseudo-random bit sequences in communications equipment for transmitting or receiving communications data.