Patent ID: 7193329

Claim:
A semiconductor device comprising: a tabular base substrate having a planar surface portion; a wiring pattern formed directly on the planar surface portion of said base substrate and including first and second portions; a semiconductor chip disposed on the planar surface portion of said base substrate; an electrode provided on said semiconductor chip; a conductive wire extending between said electrode on said semiconductor chip and the first portion of said wiring pattern on the planar surface portion of said base substrate, the conductive wire directly connected to the first portion of said wiring pattern; an interposer substrate defined by an insulating body having opposite top and bottom surfaces, wherein the bottom surface of said interposer substrate confronts the planar surface portion of said base substrate over said wiring pattern, wherein said interposer substrate includes an opening in which said semiconductor chip is positioned, wherein said interposer substrate includes a conductor extending therethrough from the top surface to the bottom surface, and wherein said conductor at the bottom surface of said interposer substrate contacts the second portion of said wiring pattern; and an external electrode electrically connected to said conductor at the top surface of said interposer substrate.