Patent ID: 7593276

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells, each memory cell being of a static type and configured by MIS transistors; a plurality of word lines which select the memory cells; a plurality of bit lines which transfer data of the memory cells; a sense amplifier circuit which amplifies data transferred to the bit lines; a dummy cell group which includes a plurality of dummy cells, each dummy cell being configured by MIS transistors and having data fixed therein; a dummy word line which selects the dummy cell group; a dummy bit line to which data of the dummy cell group is transferred; and a detection circuit which detects that a potential amplitude of the dummy bit line is changed to a constant level independent of a variation of a power supply potential, and generates an activation signal to activate the sense amplifier circuit, wherein: the detection circuit includes a first N-type MIS transistor having a threshold voltage and a first inverter circuit; the first MIS transistor has a source terminal connected to the dummy bit line; the first MIS transistor has a drain terminal connected to an input terminal of the first inverter circuit; the first MIS transistor has a gate terminal to which a desired potential is applied; and the activation signal is output from an output terminal of the first inverter circuit.