Patent ID: 8010764

Claim:
A method of managing a memory array within a processing system, said method comprising: counting accesses to each page of data locations of said memory array from a memory controller managing said accesses, wherein said memory array is a common level of system memory comprising multiple memory device ranks; determining whether or not pages stored in a first portion of said memory array are accessed less frequently than pages stored in a second portion of said memory array, wherein said first portion and said second portion of said memory array correspond to separate sets of physical dynamic memory devices that are independently power-managed; responsive to said determining, relocating data stored in less frequently accessed locations of a first portion of said memory array to a second portion of said memory array; further responsive to said determining, relocating data stored in more frequently accessed locations of a second portion of said memory array to a first portion of said memory array; and setting power management states of said first portion of said memory array and said second portion of said memory array in conformity with a frequency of accesses to said corresponding portion of said memory array, wherein said setting selects a first power management state for said first portion of said memory array from among a set of at least two power management states, and wherein said setting selects a second power management state for said second portion of said memory array from among said set of at least two power management states, wherein said at least two power management states are states in which said physical dynamic memory devices are refreshed to retain volatile storage contents, wherein said first portion of said memory array comprises multiple sets of physical dynamic memory devices, and wherein said method further comprises selectively only interleaving storage of consecutive memory chunks across said multiple sets of said physical dynamic memory devices within said first portion of said memory array, whereby an average access time to said first portion of said memory array is reduced, while reducing memory power consumption by not interleaving consecutive memory chunks of said second portion of said memory array.