Patent ID: 6982921

Claim:
A method of using a memory integrated circuit having an internal row address bus for receiving M row address bits and an internal column address bus for receiving N column address bits, comprising: in a first use for the memory integrated circuit: packaging one of the memory integrated circuits in an integrated circuit package; coupling M externally applied row address bits to the integrated circuit package; coupling N externally applied column address bits to the integrated circuit package; coupling the M externally applied row address bits to the internal row address bus of the memory integrated circuit; and coupling the N externally applied column address bits to the internal column address bus of the memory integrated circuit; and in a second use for the memory integrated circuit: packaging at least two of the memory integrated circuits in a single integrated circuit package; coupling M+P externally applied row address bits to the integrated circuit package; coupling N externally applied column address bits to the integrated circuit package; coupling M of the M+P externally applied row address bits to the internal row address bus of each of the memory integrated circuits; and coupling the N externally applied column address bits and P of the M+P externally applied row address bits to the internal column address bus of each of the memory integrated circuits.