Patent ID: 7949856

Claim:
A computer processor, the processor comprising: (a) a decode unit for decoding a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions; (b) a first processing channel comprising a plurality of functional units and operable to perform control processing operations responsive to control instructions dedicated to program flow and branch and address generation; (c) a second processing channel comprising a plurality of functional units and operable to perform data processing operations; wherein the decode unit is operable to receive instruction packets sequentially and to detect if each instruction packet is of a first class which defines (i) at least two said control instructions or a second class which defines (ii) a plurality of instructions one or more of which is a data processing instruction, the decode unit using at least one identification bit at a predetermined bit location in the packet for detecting if the instruction packet is of the first or second class, and wherein when the decode unit detects that the instruction packet comprises at least two said control instructions, said control instructions are supplied to the first processing channel for execution in program order, and when the decode unit detects that the instruction packet is of the second class, said plurality of instructions are executed simultaneously, and wherein said control instructions have a bit length less than said data processing instructions.