Patent ID: 7544569

Claim:
A method of erasing a plurality of floating gates arranged in a first row direction in an array of NAND flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of NAND structure with each structure having a first region of a second conductivity type in the substrate; a second region of the second conductivity type in the substrate, spaced apart from the first region in a column direction, forming a channel region therebetween; with the column direction substantially perpendicular to the first row direction; a plurality of floating gates, spaced apart from one another, each insulated from the substrate; each NAND structure further having a control gate insulated from the substrate, the control gate being between a pair of floating gates and being capacitively coupled to the pair of floating gates; with a select gate insulated from the substrate, the select gate being between a pair of floating gates; whereby a floating gate is between a select gate and a control gate, and wherein the NAND structures adjacent to one another in the row direction, have the select gate connected to one another in the row direction, and the control gate connected to one another in the row direction; said method of erasing comprising applying a negative voltage to a selected row of control gates immediately adjacent to one side of the select plurality of floating gates in the select row; and applying a positive voltage to a selected row of select gates immediately adjacent to another side of the select plurality of floating gates in the select row; wherein the first row of floating gates between the selected row of control gate and the selected row of select gates are erased by charges from the first row of floating gates tunneling to the selected row of select gates.