Patent ID: 8559230

Claim:
A non-volatile memory device comprising: a memory cell array comprising a plurality of memory cells, each memory cell of the plurality of memory cells including a first cell transistor and a second cell transistor; a voltage generator for generating a plurality of voltages in response to an operation mode with respect to the plurality of memory cells; and a row decoder comprising a first driver and a second driver configured to generate a first control signal and a second control signal, respectively, wherein the first cell transistor is connected to the row decoder to receive the first control signal and the second cell transistor is connected to the row decoder to receive the second control signal, wherein the first driver includes a first NMOS transistor and a first PMOS transistor formed adjacent to the first NMOS transistor, wherein the second driver includes a second NMOS transistor and a second PMOS transistor formed adjacent to the second NMOS transistor, and wherein the first and second NMOS transistors are disposed between the first PMOS transistor and second PMOS transistor.