Patent ID: 7692101

Claim:
A method for arranging planes in a printed circuit board (PCB) to which is attached a semiconductor device, the PCB having stacked metal layers extending from a top surface for receiving the semiconductor device to a bottom surface, the method comprising: placing one or more core voltage supply planes in one or more metal layers of the stacked metal layers of the PCB proximate to the semiconductor device, each core voltage supply plane of the one or more core voltage supply planes coupling a single core voltage supply to the semiconductor device, comprising: placing a primary core voltage supply plane of the one or more core voltage supply planes in a first predetermined metal layer of the stacked metal layers nearest to the semiconductor device; and placing others of the one or more core voltage supply planes below the primary core voltage supply plane in descending order based on the amount of supply noise the circuitry of the semiconductor device can accept that is driven by each of the one or more core voltage supply planes; and placing one or more input/output (I/O) voltage supply planes below the one or more core voltage supply planes in one or more metal layers of the stacked metal layers below the first predetermined metal layer, each I/O voltage supply plane of the one or more I/O voltage supply planes coupling a single I/O voltage supply to the semiconductor device, comprising: placing a lowest I/O voltage supply plane nearest to the one or more core voltage supply planes; and placing others of the one or more I/O voltage supply planes below the lowest I/O voltage supply plane in order of increasing voltage.