Patent ID: 6925537

Claim:
A computer system, comprising: an interconnect; a plurality of processor nodes, coupled to the interconnect, each processor node comprising at least one processor core, each processor core having an associated memory cache for caching memory lines of information; a plurality of input/output nodes coupled to the interconnect; and wherein the processor nodes and the input/output nodes collectively comprise a plurality of system nodes, each of which comprises input logic that receives a first invalidation request, the invalidation request identifying a memory line of information and a patten of bits that identify a subset of the plurality of system nodes that potentially store cached copies of the identified memory line; and processing circuitry that, responsive to receipt of the first invalidation request, determines a next node identified by the pattern of bits in the invalidation request and sends to the next node, if any, a second invalidation request corresponding to the first invalidation request, and that invalidates a cached copy of the identified memory line, if any, in the particular node of the computer system.