Patent ID: 8576655

Claim:
A semiconductor memory, comprising: a memory bit cell including: a first storage node coupled to an input of a first inverter and to an output of a second inverter; a second storage node coupled to an output of the first inverter and to an input of the second inverter; a first transistor coupled to the first storage node and to a first write bit line; a second transistor coupled to the second storage node and to a second write bit line; a third transistor having a source coupled to a first voltage supply and to the first inverter; a fourth transistor having a drain coupled to a second voltage source, a gate coupled to a first control line, and a source coupled to a first node; a third inverter having an input coupled to a first control line and an output coupled to the gates of the first, second, and third transistors; and a read port coupled to a first read bit line and to the second storage node.