Patent ID: 7137013

Claim:
A microprocessor configured for executing at least one instruction, the microprocessor having a main processor clock, the microprocessor comprising: a first stage having one or more storage components configured for storing operand data of the at least one instruction, the first stage being clocked by at least a first clock derived from the main processor clock; a first combinatorial logic connected to the first stage for receiving the operand data from the first stage and configured for processing the operand data and generating first output data, wherein the first clock is operational only during a first period of time when the operand data is processed by the first combinatorial logic; a second stage of one or more storage components configured for storing the first output data, the second stage being clocked by at least a second clock derived from the main processor clock; control logic that is at least configured to: generate at least two instruction-valid control bits, wherein the at least two instruction-valid control bits are configured to: disable the first clock derived from the main processor clock by a first instruction-valid control bit if a first stage is unused or disable the second clock derived from the main processor clock by a second instruction-valid control bit if a second stage is unused; enable the first clock and the second clock in response to a scan mode signal; disable the first clock by the first instruction-valid control bit in response to a first stop control signal and disable the second clock by the second instruction-valid control bit in response to a second stop control signal; and a second combinatorial logic connected to the second stage for receiving the first output data from the second stage and configured for processing the first output data and generating second output data, wherein the second clock is operational only during a second period of time when the first output data is processed by the second combinatorial logic.