Patent ID: 6939751

Claim:
A method of forming an FET device with a raised silicon source/drain and a gate electrode structure on an SOI structure comprising an silicon layer formed on a substrate wherein the substrate comprises an insulator by the following steps: forming a SiGe layer over the silicon layer, forming a raised source/drain layer over the SiGe layer, etching through the raised source/drain layer and the SiGe layer to form a gate electrode space with wails reaching down through the raised source/drain layer and the SiGe layer to the surface of the silicon layer thereby forming a pair of raised source/drain regions separated by the gate electrode space in the source/drain layer, lining the walls of the gate electrode space with an internal etch stop layer and inner sidewall spacers, forming a gate electrode inside the inner sidewall spacers on a cleaned surface of the silicon layer, forming external sidewall spacers adjacent to the gate electrode between the raised source/drain regions adjacent to the inner sidewall spacers, and doping the source/drain regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.