Patent ID: 8819309

Claim:
Apparatus for buffering received data transaction requests, said apparatus comprising: shared buffer circuitry configured to store, in order of reception time at said shared buffer circuitry, data transaction requests received from one or more data transaction sources; low latency identifying circuitry configured to identify low latency data transaction requests associated with low latency handling from among said data transaction requests received from said one or more data transaction sources and stored in said shared buffer circuitry; output selection circuitry configured to select a data transaction request for output from said shared buffer circuitry and to operate in a selectable one of: a bypass mode in which said data transaction request selected for output is one of: (a) if any low latency data transaction requests are stored in said shared buffer circuitry, an earliest received low latency data transaction stored in said shared buffer circuitry; and (b) if no low latency data transaction requests are stored in said shared buffer circuitry, an earliest received data transaction request among any data transaction requests stored in said shared buffer memory; and a non-bypass mode in which said data transaction request selected for output is an earliest received data transaction request among any data transaction requests stored in said shared buffer memory; rate detection circuitry configured to detect a rate of output of low latency data transaction requests from said shared buffer circuitry; and bypass control circuitry configured to compare said rate with a threshold value and to control said output selection circuitry to operate in one of: said bypass mode when said rate is less than said threshold value; and said non-bypass mode when said rate is greater than said threshold value.