Patent ID: 7026220

Claim:
A method for production of charge-trapping memory devices comprising the steps of: providing a semiconductor substrate with a main surface; depositing a memory layer sequence comprising a bottom confinement layer, a memory layer, and a top confinement layer; providing openings in said memory layer sequence in locations of intended bitlines; implanting a dopant to form buried bitlines and source/drain regions that are electrically connected by the bitlines; etching said memory layer back selectively with respect to the confinement layers, starting from the openings, to form recesses in the memory layer; depositing a layer of semiconductor material that at least fills said recesses; selectively removing portions of said semiconductor layers so as to leave said semiconductor material filing said recesses; and performing an oxidizing step to form oxide regions above the bitlines and to convert semiconductor material in said recesses to an oxide so as to confine said memory layer sequence with oxide.