Patent ID: 8044453

Claim:
A non-volatile memory device, comprising: adjacent field insulating layer patterns on a substrate to define an active region of the substrate therebetween, upper portions of the adjacent field insulating layer patterns protruding above an upper surface of the substrate; a tunnel insulating layer on the active region; a charge trapping layer on the tunnel insulating layer, the charge trapping layer contacting the upper portions of the adjacent field insulating layer patterns protruding above the upper surface of the substrate; a blocking layer on the charge trapping layer; first insulating layers on upper surfaces of the field insulating layer patterns; a word line structure on the blocking layer and first insulating layers, and second insulating layers on the first insulating layers, the second insulating layers being between the word line structure and the first insulating layers, and the second insulating layers being connected to the blocking layer via extensions, the extensions being positioned along side surfaces of the field insulating layer patterns and being thinner than the blocking layer.