Patent ID: 7979732

Claim:
A computer implemented method, in a data processing system, for achieving timing closure in a clocked logic circuit, the method comprising: for a local clock buffer, determining a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint is met, thereby forming a determined clock control signal input; responsive to determining the determined clock control signal input, coupling the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit; for each latch in a set of latches, determining whether a second timing constraint is met such that a clock signal is driven from the local clock buffer to the latch at the target frequency; responsive to a failure to drive the latch with the clock signal at the target frequency, determining a number of times the local clock buffer would need to be cloned in order to drive the latch with the clock signal at the target frequency such that the second timing constraint is met; and automatically cloning the local clock buffer the determined number of times, thereby forming a set of local clock buffers.