Patent ID: 7830964

Claim:
An apparatus comprising: a parsing circuit having a first input receiving a serial bitstream, a second input receiving a control signal and an output presenting a plurality of decoded syntax elements, said parsing circuit configured to generate said plurality of decoded syntax elements in response to (i) said serial bitstream and (ii) said control signal, wherein said parsing circuit comprises (a) an input circuit configured to generate a parallel bitstream in response to said serial bitstream and a first intermediate signal and (b) a first decoder configured to generate said first intermediate signal, a second intermediate signal and a third intermediate signal in response to said parallel bitstream and said control signal, wherein said first decoder includes a run before decoder configured to process run before syntax elements of said serial bitstream, said first intermediate signal comprises a length signal, said second intermediate signal comprises a run before signal and said third intermediate signal comprises a number of zero run befores signal; and a control circuit configured to generate said control signal in response to said plurality of decoded syntax elements, wherein (a) said parsing circuit generates said plurality of decoded syntax elements by grouping said run before syntax elements into one or more groups for atomic decoding such that one or more consecutive zero-valued run before syntax elements are grouped with a non-zero run before syntax element, (b) said run before decoder generates (i) said length signal, (ii) said number of zero run befores signal indicating the number of consecutive zero-valued run before syntax elements in a respective group, and (iii) said run before signal indicating a value of the non-zero run before syntax element for the respective group, and (c) said plurality of decoded syntax elements are generated based upon said length signal, said number of zero run befores signal, and said run before signal.