Patent ID: 8319542

Claim:
An integrated circuit comprising: an internal logic circuit processing data input from one of a plurality of input terminals and outputs processed data to one of a plurality of output terminals; a plurality of bypass paths bypassing the internal logic circuit; a first switch, provided between a first input terminal included in the plurality of input terminals and the internal logic circuit, switching pathways of a first path used for inputting the data to the internal logic circuit from the first input terminal and a bypass path used for bypassing the internal logic circuit; a second switch, provided between a first output terminal included in the plurality of output terminals and the internal logic circuit, switching a pathway of the second path used for outputting the processed data to the first output terminal from the internal logic circuit and the bypass path used for outputting the data bypassing to the first output terminal; and a timing correction circuit correcting a timing mismatch between signals output from each of the first switch and the second switch, when an input signal synchronized with a clock signal is transmitted from a signal source having a clock source, wherein the internal logic circuit includes a switch changeover controller performing the functions of selecting at least one of paths within the logic circuit and the bypass path, generating a switch control signal for the changeover of the first switch and the second switch, issuing the switch control signal to the first switch and the second switch, entering a waiting state until the switching of the first switch and the second switch is completed, and issuing a completion signal when the switching of the first switch and the second switch completes, and wherein, when the input signal is input from the first switch or the second switch to the timing correction circuit, the timing correction circuit generates a first output signal having a doubled length of the input signal, and a second output signal is shifted from the first output signal by one cycle of the clock signal, selects the first output signal and the second output signal alternately by using a divided clock of the clock signal, and performs correction of timing by punching out the selected first or second output signal by the clock.