Patent ID: 8194186

Claim:
A receiver for use in a system with a transmitter transmitting a sampling frequency, a first natural number, and a second natural number to a receiver, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock, the receiver comprising: a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1; and a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder, wherein, the cycle control portion calculates a sum of remainders as necessary, and controls the cycles of the second signal when the sum exceeds a threshold.