Patent ID: 6914836

Claim:
A semiconductor memory device comprising: at least a pair of bit lines; a selection circuit for selecting one of the bit lines; a precharge circuit for precharging the selected bit line; a direct current (DC) voltage generating circuit for generating a predetermined bias voltage using a power supply voltage; a reference voltage generating circuit for receiving the bias voltage to generate a reference voltage in response to first and second control signals, wherein die reference voltage is lower than the bias voltage; and a sense amplifier circuit for performing a sense and amplification operation according to a voltage on the selected bit line and the reference voltage, wherein the sense amplifier circuit comprises: first and second signal lines; a sense amplifier coupled between the first and second signal lines for amplifying a voltage difference between first and second terminals; an equalizer coupled between the first and second terminals for equalizing voltages of the first and second terminals in response to a third control signal; a first active load element coupled between the first signal line and the first terminal and having a resistance value varied according to a voltage of the selected bit line; and a second active load element coupled between the first signal line and the second terminal and having a resistance value varied according to the reference voltage; and wherein the first signal line receives a ground voltage or a power supply voltage according to an operation of the sense amplifier, and the second signal line is fixed to a ground voltage.