Patent ID: 8281199

Claim:
A hybrid self-test circuit structure, having a plurality of input terminals and a plurality of output terminals, for testing a plurality of memory units, and the structure comprising: a first level functional unit, electrically coupled to at least one of the input terminals and at least one of the output terminals, and the first level functional unit having a plurality of first output terminals, and provided for outputting an output signal from the first output terminals according to an external control signal transmitted from the input terminals; a plurality of second level functional units, having a plurality of second input terminals, for receiving the output signal, and the second level functional units generating test signals according to the output signals respectively, and the test signals being outputted to the memory units through at least one of the output terminals electrically coupled to the second level functional units; a parallel interface, parallelly installed between the first level functional unit and at least one of the second level functional units, and provided for parallelly transmitting the output signal to the second level functional units; and a serial interface, serially installed between the first level functional unit and at least one of the second level functional units, and provided for serially transmitting the output signal to the second level functional units; wherein the first level functional unit simultaneously cooperating with the parallel interface and the serial interface; wherein the hybrid self-test circuit structure simultaneously having the parallel interface and the serial interface electrically coupled between the first and second level functional units to reduce a wiring area for a circuit layout of a chip and to provide a high-speed testing and diagnostic.