Patent ID: 7741220

Claim:
A manufacturing method of a semiconductor device, comprising: forming a first semiconductor region and a second semiconductor region in a semiconductor substrate; forming a first gate electrode on the first semiconductor region through a first insulator, and forming a second gate electrode on the second semiconductor region through a second insulator; forming a pair of first diffusion layers in the semiconductor substrate with the first gate electrode interposed therebetween, and forming a pair of second diffusion layers in the semiconductor substrate with the second gate electrode interposed therebetween; depositing a metal film on the first and second diffusion layers; forming a first conductor layer and a second conductor layer, each being with a first phase and having an internal stress in a first direction in the first and second diffusion layers, respectively, caused by partially reacting the metal film with the semiconductor substrate in a first annealing; forming a stress control film having an internal stress in a second direction opposite to the first direction over the second semiconductor region including the second diffusion layers; and forming a first conductor layer with a second phase having an internal stress in the first direction on the first diffusion layers by a second annealing to manufacture a first semiconductor element device, and forming a second conductor layer with a second phase having an internal stress in the second direction on the second diffusion layers by the second annealing to manufacture a second semiconductor element device, such that the internal stress in the second conductor layer with a second phase is a stress caused by the second annealing, frozen in the second conductor layer, and has the same direction as the internal stress of the stress control film and an opposite direction to an original internal stress of the second conductor layer.