Patent ID: 8378930

Claim:
A display device, comprising: a scan driver connected to a plurality of scan lines; a data drive connected to a plurality of signal lines; a plurality of pixel circuits arranged in a matrix, connected to the signal lines which are supplied with data signals containing luminance information, wherein pairs of pixel circuits, comprising odd column pixel circuits, positioned in odd number columns of the matrix, and even column pixel circuits, positioned in adjacent even number columns of the matrix, sandwich an axis in a column direction and have a mirror type circuit arrangement symmetric with respect to the axis of the column direction; the signal lines are arranged in a direction parallel to the column direction; a plurality of power supply lines arranged in columns, each pair of pixel circuits sharing a power supply line from the plurality of power supply lines; and a plurality of potential lines, wherein a first end of each of the plurality of potential lines is directly connected to a first common line, a second end of each of the plurality of potential lines is directly connected to a second common line, and the first common line and second common line are conductively connected to a common voltage source, thereby making the potential lines common, the plurality of potential lines being arranged between pairs of adjacent signal lines with the potential lines and signal lines being adjacent to each other without any circuit elements in between them, the potential lines and signal lines being formed in a same plane such that crosstalk between the pixels is prevented without requiring three-dimensional shielding, a first signal line in a pair of adjacent signal lines being associated with an odd pixel column and a second signal line in a pair of adjacent signal lines being associated with an even pixel column, wherein each pixel circuit includes an electro-optic element, a drive transistor with a first source or drain electrode connected to the electro-optic element and a second source or drain electrode connected to one of the power supply lines, a capacitor with a first terminal connected to a gate of the drive transistor, the capacitor retaining the data signal provided from a write transistor with a first source or drain electrode connected to one of the signal lines and a second source or drain electrode connected to a second terminal of the capacitor, and a third transistor with a first source or drain electrode connected to one of the potential lines and a second source or drain area connected to the second terminal of the capacitor, and wherein the potential lines supply an initialization voltage to the pixel circuits for threshold initialization of the drive transistors, and wherein the scan driver and data driver are configured such that, during a one field period, the third transistor is put into a conducting state before the data signal is supplied to the capacitor.