Patent ID: 6966047

Claim:
A circuit design for use with electronic design automation (EDA) tools in designing integrated circuits, the circuit design being stored on a computer readable medium and containing an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit, the layout pattern comprising: a first layout region having a first flag associated therewith, the first layout region corresponding to a first procedure region on a reticle or an integrated circuit; and a second layout region having a second flag or no flag associated therewith, the second layout region corresponding to a second procedure region on the reticle or the integrated circuit; wherein the first flag of the first layout region is readable by an inspection or a fabrication system, and indicates that the first procedure region of the reticle or the integrated circuit has a first circuit characterization type and is thereby subject to a first inspection or fabrication procedure that is to be performed on the first procedure region on the reticle or the integrated circuit; the second flag or absence of a flag of the second layout region is readable by the inspection or the fabrication system, and indicates that the second procedure region of the reticle or integrated circuit has a second circuit characterization type and is thereby subject to a second inspection or fabrication procedure that is to be performed on the second procedure region on the reticle or the integrated circuit; the second inspection or fabrication procedure differs from the first inspection or fabrication procedure; and the first circuit characterization type and the second circuit characterization type identify types of structures of the first and second layout regions, wherein the first circuit characterization type is an active transistor, and the second circuit characterization type is a decoupling transistor.