Patent ID: 8710580

Claim:
A semiconductor device comprising: a semiconductor substrate; an insulating layer on the semiconductor substrate; first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of the insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other; a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof; and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers, wherein the layer select transistor comprises first to m-th gate electrodes (m=n+k, k is an even number) which are arranged in order from the first end of the second direction of the first to n-th semiconductor layers toward a second end of the second direction of the first to n-th semiconductor layers, and which extend in the first direction along side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and an i-th normally-on region (i is one of 1 to n) which sets channels adjacent to the i-th to (i+k)-th gate electrodes in the i-th semiconductor layer to normally-on channels, the normally-on channels which are not dependent on potentials of the i-th to (i+k)-th gate electrodes.