Patent ID: 7915658

Claim:
A semiconductor on insulator (SOI) device, comprising: a semiconductor substrate including a pn junction diode formed in a first portion of the semiconductor substrate; a buried insulator layer overlying the semiconductor substrate; a monocrystalline semiconductor layer overlying the buried insulator layer; an MOS capacitor comprising: a first plate that comprises gate electrode forming material having a first conductivity type; a second plate that comprises an impurity doped region having the first conductivity type in the monocrystalline semiconductor layer beneath the gate electrode forming material; a dielectric layer disposed between the first plate and the second plate, a first contact region electrically in series with the impurity doped region, and a second contact region electrically in series with the impurity doped region, wherein the first contact region and the second contact region each have the first conductivity type; a first voltage bus coupled to the pn junction diode and the first plate; and a second voltage bus coupled to the second plate, the first contact region and the second contact region such that the MOS capacitor is coupled between the first voltage bus and the second voltage bus.