Patent ID: 8161271

Claim:
A method for storing data to memory, comprising: by operation of a computer processor and based on at least two predefined instructions supported by the computer processor, storing aligned vector data in a vector register of a register file to memory in a misaligned manner and without requiring any data permutation in the register file, wherein the at least two predefined instructions are each identifiable based on a respective opcode and include: (i) a first instruction for setting a permute control stored in a store-permute-control (SPC) register and (ii) a second instruction for storing aligned vector data from the register file to memory in a misaligned manner based on the permute control stored in the SPC register, and wherein storing aligned vector data based on the at least two predefined instructions comprises; in response to receiving the first instruction, setting the permute control in the SPC register to configure at least one multiplexer in a store-permute unit (SPU) on the basis of the first instruction, wherein the SPU is communicably connected to the register file, the memory, and the SPC register via a data path, wherein the SPU comprises at least one multiplexer; receiving the second instruction, wherein the second instruction specifies: (i) the vector register and (ii) a target memory address along a memory array boundary of the memory; and in response to receiving the second instruction: misaligning the vector data as it passes from the vector register to the memory through the at least one multiplexer in the SPU; and storing the misaligned vector data in the memory at a memory location specified by the target memory address.