Patent ID: 7804711

Claim:
A method of operating a memory device, the method comprising: erasing a plurality of two-bit memory cells, each two-bit memory cell comprising a first bit and a second bit, by: applying a reference voltage to a first bit line and a second bit line, the first bit line associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell; applying a control activation voltage to a first bit line select and a second bit line select, the first bit line select associated with the first bits of each memory cell and the second bit line select associated with the second bits of each memory cell; and applying an erase voltage to a plurality of word lines associated with each two-bit memory cell, wherein the erase voltage is between 14 and 20 volts, wherein applying the erase voltage includes creating a threshold voltage associated with each two-bit memory cell less than or equal to 0 volts.