Patent ID: 7271891

Claim:
A method of providing selective defect sensitivity in inspection of semiconductor reticles, the method comprising: a) providing a target portion of a reticle, wherein the target portion comprises a plurality of pattern portions; b) analyzing the pattern portions of the reticle to thereby determine a characteristic of defect susceptibility for each pattern portion, wherein each characteristic of defect susceptibility is a quantification of the predicted impact of a defect in the corresponding pattern portion of the reticle on a corresponding portion of a wafer that is to be fabricated with such each pattern portion of the reticle; c) determining and storing a sensitivity level for inspection of each pattern portion of the reticle that corresponds to the determined defect susceptibility characteristic of such each pattern portion; and d) inspecting each portion of the reticle using the determined sensitivity level for such reticle portion, wherein the operation of analyzing the pattern portions of the reticle comprises: simulating an approximation of a lithography image which would be produced by a lithography tool which is to be used to expose a semiconductor device with the reticle; simulating resist development results using the approximation of the lithography image; and generating the sensitivity levels in the form of a defect susceptibility map for the reticle based on the simulated resist development results, wherein the approximation of the lithography image is simulated by convoluting a low pass filter function with an image of the target portion of the reticle and wherein the low pass filter function also incorporates at least some of the differences between the lithography tool and an inspection tool which is to be used to inspect the reticle or a semiconductor device fabricated from such reticle.