Patent ID: 7046553

Claim:
A minimum conversion time means between program and program verify operations for a dual storage site MONOS memory cell, comprising: a) a means for minimizing a charging and discharging of wiring capacitance of connections to a selected twin MONOS memory cell during and between program and program verify operations; b) a means for said program operations, comprising: i) a first control gate coupled to a first high voltage and a second control gate coupled to a second high voltage, ii) a first bit diffusion coupled to a first low voltage near circuit ground voltage, and iii) a second bit diffusion coupled to a third high voltage and a word gate voltage raised to a second low voltage; c) a means for said program verify operations, comprising: i) said first control gate voltage maintained at said first high voltage, ii) said second control gate voltage reduced from said second high voltage to a fourth high voltage lower than said second high voltage by a first low differential amount, iii) said second low voltage maintained on said word gate, said first low voltage and said third high voltage coupled to said first and second bit diffusions equalized to an equalization voltage, and then said equalization voltage on said first and second bit diffusions floated, iv) whereupon said floated voltage on the second bit diffusion is reduced by a second low differential amount and said word gate voltage is raised to a fifth high voltage to allow current flow between the first and second bit diffusions allowing said equalized voltage of said first bit diffusion to drop depending upon a threshold voltage of a nonvolatile storage site under said second control gate and providing a reverse read operation; and d) a means for using a forward read operation during the program verify operation, comprising: i) said floated voltage on said first bit diffusion reduced by a third low differential amount, and ii) said word gate voltage raised to said fifth high voltage to allow current flow between the first and second bit diffusions which allows said equalized voltage of said second diffusion to drop depending upon a threshold voltage of said nonvolatile storage site under said second control gate and providing said forward read operation.