Patent ID: 8258628

Claim:
An integrated circuit arrangement, comprising: a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate, the wiring interconnects each comprise a planar bottom area and a planar top area which are in contact with a dielectric, the bottom area of the wiring interconnect remote from the substrate extends entirely and is defined by a plane in which the top area of the middle wiring interconnect also extends, or the bottom area of the wiring interconnect remote from the substrate extends in a plane which lies nearer to the substrate than a plane in which the top area of the middle wiring interconnect extends; the bottom area of the middle wiring interconnect extends entirely and is defined by a plane in which the top area of the wiring interconnect near to the substrate extends, or the bottom area of the middle wiring interconnect extends in a plane which lies nearer to the substrate than a plane in which the top area of the wiring interconnect near to the substrate extends; and wherein the wiring interconnects each have a middle section that is not adjoined by any conductive structure of another conductive structure level, the middle section in each case being at least a third of the length of the interconnect away from each end of the interconnect.