Patent ID: 8321649

Claim:
A system for configuring a memory controller, the memory controller suitable for communicating with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the system comprising: a programmable logic block connected to the set of pins of the memory controller, the programmable logic block selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, wherein the selection of the subset is performed by re-organizing one or more address bits among the set of pins of the memory controller in accordance with the size of the memory device; a multiplexer connected to the programmable logic block for multiplexing address and data bits; and a latch connected between the multiplexer and the memory device, the latch latching the multiplexed address and data bits on a plurality of pins from the subset of pins to transfer address and data bits between the memory device and the memory controller, wherein each of the latch and the multiplexer includes a control pin for receiving a control signal indicating multiplexing of address and data bits, wherein the control signal indicates a transfer of one of the address bits and the data bits, wherein multiplexing address and data bits on a plurality of pins comprises multiplexing one or more most significant bits (HSBs) of the address bits with data bits.