Patent ID: 6865240

Claim:
A frame synchronizing circuit comprising: a synchronization pattern detecting unit that detects a first pattern and a second pattern each similar to a predetermined synchronization pattern in input data within a predetermined period of time; a first frame synchronizing unit synchronizing with the first pattern at a first position of the input data; a second frame synchronizing unit synchronizing with the second pattern at a second position of the input data; a first error detecting unit that detects that the first position is different from a position of the predetermined synchronization pattern, and controls the first frame synchronizing unit to operate in accordance with the second position; and a second error detecting unit that detects that the second position is different from a position of the predetermined synchronization pattern, wherein the synchronization pattern detecting unit detects a third pattern similar to the predetermined synchronization pattern in the input frame, and controls the second frame synchronizing unit to operate in accordance with a third position.