Patent ID: 7421559

Claim:
An apparatus comprising: a memory array; a plurality of ports coupled with the memory array, each of the plurality of ports comprising: a delay stage to delay access to the memory array while a memory access arbitration is performed, wherein the delay stage comprises a control delay element, an address delay element and a data delay element; an input stage coupled with the delay stage to receive memory access requests, wherein the input stage comprises an address input element, a control input element and a data input element; an address multiplexer coupled with the address input element, the address delay element and the memory array; a data multiplexer coupled with an output element, the memory array, the data delay element of the port, the data input element of an other port, and the data delay element of the other port; and a data latch; and selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request from a prevailing port and to implement memory access controls, wherein the control delay element in a non-prevailing port is cleared to assert a disable signal at the memory array.