Patent ID: 7075149

Claim:
A semiconductor device comprising: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar layer of a second conductivity type provided on the major surface of the semiconductor layer and adjoining the first semiconductor pillar layer; a third semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer and adjoining the second semiconductor pillar layer; a forth semiconductor pillar layer of the second conductivity type provided on the major surface of the semiconductor layer and adjoining the third semiconductor pillar layer; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer and adjoining the forth semiconductor pillar layer; a semiconductor intermediate layer of the first conductivity type whose concentration of impurities is lower than the first, third, and fifth semiconductor pillar layers, provided on the major surface of the semiconductor layer in a surrounding of the first through fifth semiconductor pillar layers; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; a first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; a second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; a gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and a gate electrode provided on the gate insulating film, each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively being 10 microns or less.