Patent ID: 8806093

Claim:
A method for facilitating deterministic data at an interface comprising: starting a link clock after a predetermined time after a common clock; initiating a counter based on the link clock; restarting the counter on every rising edge of the common clock for clock ratios with respect to the link clock to common clock; and adjusting an output point of a latency buffer in response to detecting a skip ordered set to match an entry that corresponds to the counter being equal to a value in a register and wherein the latency buffer is to be integrated into a physical data path of the interface, wherein the register is to be programmed to vary based on at least one of: routing, protocol, semiconductor processing, and a particular design implementation, wherein adjusting the latency buffer output point is performed based on an output of a multiplexer, wherein an output selector of the multiplexer is incremented in response to the detection of the skip ordered set and a determination that a value stored in the counter is not equal to a value stored in the register.