Patent ID: 7208374

Claim:
A method for manufacturing a nonvolatile memory device, comprising the steps of: forming a gate oxide film of a select transistor and a tunnel oxide film of an Electrically Erasable and Programmable Read Only Memory (“EEPROM”) cell on a semiconductor substrate where a cell region and a logic region are isolated and a predetermined substructure is formed; depositing a first polysilicon on the resultant material where the gate oxide film of the select transistor and the tunnel oxide film of the EEPROM cell are formed; forming a gate electrode of the select transistor and a floating gate electrode of the EEPROM cell by selectively etching the first polysilicon, wherein the floating gate electrode formed by the selective etching has a channel length that is the same as a channel length of a first polysilicon in a stack cell formed by a combined selective etching and Self-Aligned Etch process; forming an Oxide-Nitride-Oxide (“ONO”) film so as to cover the floating gate electrode; carrying out a threshold voltage control ion implantation to the logic region and forming a logic gate oxide film; and forming a logic gate electrode and a control gate electrode of the EEPROM cell at the same time by depositing a second polysilicon on the entire surface of the resultant material and etching the second polysilicon.