Patent ID: 7917707

Claim:
A semiconductor device, comprising: a first storage that stores a program code including unit codes defining a state transition; a second storage that stores base address information in association with each unit code of the unit codes; a third storage that stores data; a fourth storage that stores circuit information that specifies an operation process; a controller configured to sequentially read the program code stored in the first storage to obtain the unit codes; read and output the data stored in the third storage; read and output the circuit information stored in the fourth storage; and transition a state by executing each unit code of the unit codes; a first operating unit that performs a first operation process that is specified by the circuit information received from the controller for data received from the controller; a second operating unit that performs a second operation process that is specified by the circuit information received from the controller on a result of the first operation process performed by the first operating unit; and a fifth storage that stores offset information for generating an address specifying the data read from the third storage and a pointer specifying the circuit information stored in the fourth storage in association with each state to be transitioned by the controller, wherein the controller is further configured to read, from the second storage, the base address information associated with a unit code, of the unit codes, that is being executed; read the offset information and the pointer associated with a current state from the fifth storage; calculate an address from the read base address information and the read offset information; transmit the data stored in the third storage that is specified by the calculated address, to the first operating unit; and transmit the circuit information stored in the fourth storage and specified by the read pointer to the first and second operating units.