Patent ID: 6839301

Claim:
A delay-locked loop, comprising: a delay line having first and second inputs and an output, said first input configured to receive an external clock signal via a clock input path and said output configured to couple with an output driver of a memory device; an I/O model having an output and an input, said input of said I/O model configured to couple with said output of said delay line via a clock distribution network of said memory device, said I/O model including an output driver delay model configured to model delay of said output driver; a phase detector having forward and feedback path inputs and an output operably coupled to said second input of said delay line, said forward path input coupled to said first input of said delay line and said feedback path input coupled to said output of said I/O model; and a timer circuit having an output and an input, said output of said timer circuit switchably coupled to said first input of said delay line and said input of said timer circuit operably coupled to said feedback path input of said phase detector, said timer circuit configured to generate a test signal on said output thereof and calculate a loop delay from receipt of said test signal on said input thereof.