Patent ID: 7029925

Claim:
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising: forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate; patterning the hard mask layer; patterning the top electrode layer in accordance with the patterned hard mask; patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees; and patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 degrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch; wherein patterning the PZT ferroelectric layer comprises etching using a fluorine gas+Cl 2 +an oxidizer at a relatively low temperature; and wherein the temperature of the PZT ferroelectric layer etch is about 60° C.