Patent ID: 7095262

Claim:
A triple redundant latch for reducing soft errors comprising: a) a first settable memory element; b) a second settable memory element; c) a third settable memory element; d) a first voting structure; e) a first buffer; f) wherein an identical logic value is set in each settable memory element; g) wherein inputs to the voting structure are provided by the second settable memory element and the third settable memory element; h) wherein an output of the first voting structure determines a logical value held on the first settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set; i) wherein the second settable memory element is capable of being set by scan data; j) wherein the second settable memory element into the buffer is capable of propagating data to a scan output; k) wherein data is capable of being scanned from the buffer into third settable memory element; l) wherein data is capable of being scanned out of the third settable memory element; m) wherein a propagation delay through the first settable memory element is the only propagation delay of the triple redundant latch.