Patent ID: 7286422

Claim:
A memory device comprising: a main memory block having an arrangement of regular memory cells; a test circuit which performs a self-test of the regular memory cells in memory blocks; an external memory block provided external to the main memory block, the external memory block including alternative cells, one of which replaces one of the regular memory cells which has been found to be erroneous as a result of the self-test; a bypass circuit which switches access to the main memory block to access to the external memory block when one of the regular memory cells has been found to be erroneous; and an enable register which permits the operation of the test circuit: the bypass circuit comprises: an error address storage circuit which stores the address of the erroneous memory cell; a comparator circuit which compares a currently accessed address with an address stored in the error address storage circuit; and a switching circuit which changes an access destination to the alternative cell when there is a match between both the addresses to be compared in the comparator circuit; wherein the most significant bit in the error address storage circuit is utilized as an error presence flag and the most significant bit and an output from the enable register are supplied to a gate, so as to enable the comparator by the output of the gate.