Patent ID: 8514002

Claim:
A clock signal adjustment circuit for a semiconductor integrated circuit comprising: a plurality of circuit blocks each including specific functional blocks to be subject to a delay test; a clock tree buffer which distributes clock signals to the circuit blocks; a plurality of clock delay circuits which perform the delay process by delaying the clock signal input from the clock tree buffer by a delay value based on the delay control signal, then by supplying the delayed clock signal to its corresponding circuit blocks; a control circuit which performs the delay test of the circuit blocks by performing the delay process on the circuit blocks based on the delay control signal which is set by an external setting signal; a recovery group memory circuit which stores the information about the circuit blocks requiring the delay process among the circuit blocks, in response to the result of the delay test; a predetermined number of delay setting circuits which are less than the number of the circuit blocks, and which store the information about the delay value of the circuit blocks requiring the delay process among the circuit blocks, in response to the result of the delay test; and a delay setting dispatch control circuit which dispatches the delay control signal in correspondence with the information about the delay value stored in the delay setting circuit to the clock delay circuit corresponding to the information about the circuit blocks stored in the recovery group memory circuit.