Patent ID: 6982908

Claim:
A memory device comprising: a first memory array having a plurality of first memory cells, wherein each one of the plurality of first memory cells is arranged at an intersection of at least one of a plurality of wordlines, at least one of a plurality of bitlines, and at least one of a plurality of digit lines; a second memory array having a plurality of second memory cells, wherein each one of the plurality of second memory cells is arranged at an intersection of at least one of the plurality of wordlines, at least one of a first reference bitline and a second reference bitline of the plurality of bitlines, and at least one of the plurality of digit lines; a current providing unit for providing a second current to the first and second reference bitlines in response to a reference voltage; and a sense amplifier for comparing a first current flowing through one of the plurality of bitlines with the second current, wherein each one of the plurality of second memory cells set to a first logic state is coupled to the first reference bitline and each one of the plurality of second memory cells set to a second logic state is coupled to the second reference bitline.