Patent ID: 7046549

Claim:
A layout of nonvolatile memory, comprising: a word line; a bit line; a plurality of metal-oxide semiconductor (MOS) transistor memory cells, each having a gate electrode, a first doped electrode, and a second doped electrode, wherein each of the first doped electrode is coupled to the bit line, and each of the gate electrode is coupled to a corresponding one of the word line; and a shared coupled capacitor structure, coupled between the transistor memory cells of the adjacent bit line from the second doped electrodes, wherein the shared coupled capacitor structure comprises at least two floating-gate MOS capacitors, wherein each of the floating-gate MOS capacitors comprises: a floating-gate transistor having a floating gate, a first source/drain (S/D) region and a second S/D region; and a MOS capacitor, coupled to the floating gate, wherein the first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of tile floating-gate transistor.