Patent ID: 7620677

Claim:
A digital multiplication circuit for adding partial products received by the digital multiplication circuit, the digital multiplication circuit having a 4:2 carry save adder cell comprising: an odd detector generating an XOR signal of first through fourth input signals, outputting the XOR signal of the first through fourth input signals as an odd signal, generating an XOR signal of the first and second input signals, and outputting the XOR signal of the first and second input signals as a first XOR signal; a first switch outputting the third input signal as a carry output signal in response to the first XOR signal of a logic ‘1’ state; a second switch outputting the first input signal as the carry output signal in response to a first XOR signal of a logic ‘0’ state; a third switch outputting the carry input signal as a carry signal in response to the odd signal; a fourth switch outputting the fourth input signal as the carry signal in response to an inverted version of the odd signal; a fifth switch outputting an inverted carry input signal as a sum signal in response to the odd signal; and a sixth switch outputting the carry input signal as the sum signal in response to the inverted version of the odd signal.