Patent ID: 7148731

Claim:
A duty cycle correction system comprising: a first circuit configured to receive a clock signal and output a corrected clock signal having a first duty cycle closer to 50% than the clock signal; a second circuit configured to receive an inverted clock signal and output a corrected inverted clock signal having a second duty cycle closer to 50% than the inverted clock signal; and a third circuit configured to receive the corrected clock signal and the corrected inverted clock signal and provide a first signal having a third duty cycle closer to 50% than the corrected clock signal and the corrected inverted clock signal; wherein the first circuit comprises: an averaging circuit configured to receive the clock signal and a second signal and provide a third signal; a duty restoration circuit configured to receive the third signal and the inverted clock signal and provide the corrected clock signal; and a synchronous mirror delay circuit configured to receive the corrected clock signal and provide the second signal.