Patent ID: 7180963

Claim:
A digital receiver configured to process modulated signals at various data rates, comprising: a sampling circuit operating at a fixed sampling rate for receiving transmitted signals and outputting a plurality of digitalized sampled signals; a channel matched filter for expelling noise from the plurality of digitalized sampled signal at a first data rate and at a second data rate and generating in-phase and quadrature-phase signals; a first correlator unit coupled to the channel matched filter for depreading the in-phase and quadrature-phase signals at the first data rate; a channel equalizer which counteracts co-channel interferences, coupling to the sampling circuit, by using equalizer coefficients obtained from a plurality of noise whitening coefficients so as to generate a sequence of symbol decisions therefrom; a second correlator unit coupled to the channel equalizer for decoding signals at the second data rate or at a third data rate; a first quantization filter coupling to the first correlator for recovering transmitted signals at the first data rate; and a second quantization filter coupling to the second correlator for recovering transmitted signals at the second data rate and at the third data rate.