Patent ID: 8440533

Claim:
A method comprising: forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on a shallow trench isolation (STI) region, and a first inter layer dielectric (ILD) between the first and second metal gate stacks; forming an etch stop layer on the first and second metal gate stacks; forming a second ILD on the etch stop layer, with openings over the first and second gate stacks; forming first and second spacers on the edges of the openings; forming a third ILD over the second ILD and the first and second spacers; removing the first ILD over the source/drain regions and the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the first spacers, and over a portion of the first spacers, forming first trenches; removing the third ILD over the second high-k metal gate stack and over a portion of the second spacers, forming second trenches; and forming contacts in the first and second trenches.