Patent ID: 6946321

Claim:
A method of forming an integrated circuit, the method comprising the steps of: forming a first die from a first wafer, the first die having: a substrate with an electrical circuit; an interconnect formed on the substrate and electrically connected to the electrical circuit; a passivation layer formed on the interconnect; a plurality of first bonding pads formed on the passivation layer, the first bonding pads being electrically connected to the interconnect; and a plurality of second bonding pads formed on the passivation layer, the second bonding pads being electrically connected to the interconnect; forming a second die from a second wafer, the second die having: a micro-electromechanical structure having an inductance; and a plurality of third bonding pads, the micro-electromechanical structure being connected to a third bonding pad; and attaching the third bonding pads of the second die to the second bonding pads of the first die.