Patent ID: 7432565

Claim:
A III-V based, implant free MOS heterostructure field-effect transistor device comprising: a gate insulator layer overlying a compound semiconductor substrate, wherein the gate insulator layer/compound semiconductor interface comprises an annealed interface, the gate insulator layer/compound semiconductor interface having been annealed with a water vapor anneal to reduce a density of interface states (D it ) therein to a desired level; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate, the ohmic contacts having portions thereof that overlap with portions of the gate insulator layer within the active device region, the overlapping portions ensuring avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer; and a gate metal contact electrode formed on the gate insulator layer in a region between the ohmic contacts, further comprising: a protective layer overlying the gate insulator layer, wherein the ohmic contacts further include the ohmic contacts having a portion thereof that overlaps with the protective layer and the gate insulator layer, further wherein the gate metal contact electrode is formed through an opening in the protective layer at a desired location of the gate metal contact electrode, wherein the protective layer comprises an aluminum nitride (AlN) layer.