Patent ID: 7622353

Claim:
A method for forming a recess-gate structure comprising: dividing a silicon substrate into an active region and a device isolation region; forming a gate recess having a stepped profile, in which a plurality of gates will be formed, by etching part of the active region of the silicon substrate to a predetermined depth; implanting primary ions for adjusting a threshold voltage into the silicon substrate; forming the plurality of gates on the silicon substrate so that a specific number of the gates on the active region is positioned to correspond to a boundary of the stepped gate recess; applying an ion implantation mask over the silicon substrate, where the plurality of gates are formed, to cover storage nodes while exposing a bit line node; implanting secondary ions for adjusting the threshold voltage by means of the ion implantation mask; removing the ion implantation mask; and implanting ions, as impurities, into the substrate after the removal of the ion implantation mask, forming asymmetrical junctions.