Patent ID: 7454575

Claim:
A cache memory, comprising: a flag holding unit which holds, in a correspondence with a cache entry that holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into; a command holding unit which is configured of a register that allows access from a processor by a data transfer instruction, and holds a command issued by the processor by a data transfer instruction; and an altering unit operable to alter, based on a command held by said command holding unit, at least one of the valid flag and the dirty flag, contrary to the state of the cache entry, wherein the command to said command holding unit is issued by a data transfer instruction, the command being data transferred by the data transfer instruction, said altering unit operating independently of an operation of the processor, and performs the altering while the cache memory is not accessed by the processor.