Patent ID: 6984559

Claim:
A method of fabricating a flash memory, comprising the steps of: providing a substrate having a tunneling dielectric layer, a first conductive layer, a pad oxide layer and a patterned mask layer formed thereon; removing portions of the pad oxide layer, the first conductive layer, the tunneling dielectric layer and the substrate using the patterned mask layer as an etching mask to form a plurality of first trenches in the substrate; depositing an insulating material into the first trenches to form a plurality of device isolation structures; removing a portion of each device isolation structure to form a plurality of second trenches such that the top section of each retained device isolation structure lies between the tunneling dielectric layer and the patterned mask layer; forming a dielectric layer over the substrate to cover the patterned mask layer and the surface of the second trenches; filling the second trenches with sacrificial material so as to form sacrificial layers; removing a portion of the dielectric layer using the sacrificial layers as self-aligned masks; removing the patterned mask layer to expose the pad oxide layer; removing the pad oxide layer to expose the first conductive layer; forming a second conductive layer over the substrate; removing a portion of the second conductive layer to expose a top section of the sacrificial layers, wherein the second conductive layer and the first conductive layer together form a plurality of floating gates; removing the sacrificial layer; forming an inter-gate dielectric layer over the substrate to cover the floating gate; forming a third conductive layer over the inter-gate dielectric layer to form a plurality of control gates; and forming a plurality of source/drain regions in the substrate on each side of the control gates.