Patent ID: 7397281

Claim:
An input/output circuit for a semiconductor memory device, comprising: a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line; a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device; a capacitor coupled to the input/output signal line; and a load controller configured to couple the capacitor to a power supply in response to the input/output enable signal, the load controller including: a pad coupled to the input/output signal line; and a MOS transistor coupled between the pad and the power supply and responsive to the input/output enable signal; wherein the pad includes: a first layer coupled to the input/output signal line; and a second layer coupled to a drain of the MOS transistor.