Patent ID: 7371632

Claim:
A method of fabricating a semiconductor device, comprising: defining a high-voltage transistor area and a polysilicon-insulator-polysilicon (PIP) capacitor area on a substrate; forming an extended drain region in the high-voltage transistor area; forming a pad insulating layer on the substrate including the extended drain region; stacking a polysilicon layer and a mask layer on the pad insulating layer; patterning the mask layer to expose a PIP capacitor portion of the polysilicon layer; patterning the mask layer and the polysilicon layer to expose a drain region portion of the pad insulating layer in the high-voltage transistor area; and implanting impurity ions into the exposed portions of the pad insulating layer and the polysilicon layer to form an impurity region within the extended drain region and a first electrode layer on an ion-implanted portion of the polysilicon layer.