Patent ID: 7152152

Claim:
An apparatus for performing commands, comprising: performance logic, wherein the performance logic is configured to perform a plurality of commands issued by a processor, and wherein the performance logic further comprises a command queue having a queue depth equal to a predefined number of slots for storing the plurality of commands issued by the processor; a command pipeline, wherein the command pipeline communicates the plurality of commands issued by the processor to the performance logic; a plurality of counters, wherein a known counter within the plurality of counters represents a count of a number of commands in the command pipeline and in the command queue, and wherein an unknown counter within the plurality of counters represents a predicted count of future commands that can be directed toward the command queue and are past a point where the future commands can be stalled; and stall logic, wherein the stall logic stalls performance of the plurality of commands issued by the processor responsive to a sum of the known counter and the unknown counter being greater than the queue depth.