Patent ID: 8759874

Claim:
A transistor comprising: a silicon substrate; an epitaxial source and drain in contact with a surface of the silicon substrate and formed within an active region located between a pair of insulating trenches extending at least partially into the silicon substrate; a substrate insulating layer in contact with the silicon substrate within an area located between the source and the drain; an array of semiconducting fins positioned between the source and the drain, the array aligned substantially parallel to the trenches, the semiconducting fins selectively electrically coupling the source and the drain while remaining isolated from the silicon substrate by the substrate insulating layer; an array of insulating columns at least partially interdigitated with the array of semiconducting fins, the insulating columns providing localized inter-fin isolation; and a conformal gate overlying, and at least partially contiguous to, three sides of each semiconducting fin, the gate operable to control current flow within the semiconducting fin in response to an applied voltage.