Patent ID: 7647438

Claim:
A base address sorting device in a switching device, comprising: an array of base address registers sorted into a pre-existing order, each base address register in said array of base address registers containing a base address, wherein each of the base addresses contained in said base address registers designates an identifying address of a specific external device; a hardware implemented control logic element electrically coupled to said array of base address registers and operable upon receiving a configuration command comprising a new base address to reconfigure the contents of said array of base address registers by determining an insertion point base address register in said array of base address registers into which to write said new base address of said configuration command which will preserve the pre-existing sorted order of the contents of the array of base address registers, wherein the insertion point base address register is determined by: dividing the array of base address registers into a plurality of base address intervals; identifying the base address interval in which the new base address belongs by using a first plurality of comparators to simultaneously compare the new base address to one of the base address registers in each of the plurality of base address intervals; and after the base address interval has been identified in which the new base address belongs, determining the insertion point base address register by using a second plurality of comparators to simultaneously compare the new base address to each of the base address registers in the identified base address interval; generating a shift vector to direct the shifting of the base addresses of one or more base address registers in said array of base address registers to preserve the pre-existing sorted order of the contents of the array of base address registers, wherein the shift vector is a multi-bit digital word comprising directions for each base address register in said array of base address registers to either; make no change to its content, replace its content with the content from the configuration command, replace its content with the content of a next lower base address register or replace its content with the content of the next higher register, inserting said new base address into said insertion point base address register and shifting the contents of the one or more base address registers in said array of base address registers in accordance with the shift vector, wherein said inserting and said shifting of the contents of the one or more base address registers to preserve the pre-existing sorted order is accomplished in a single clock cycle.