Patent ID: 8163614

Claim:
A method for fabricating a NAND type flash memory device comprising: defining a select transistor region and a memory cell region in a semiconductor substrate; forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over the semiconductor substrate; etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer in the select transistor region; forming a low resistance layer over inner sidewalls and a bottom of the opening; forming a barrier metal layer in a remaining region of the opening after forming the low resistance layer, wherein a top surface of the floating gate is in contact with a bottom surface of the barrier metal layer; forming a control gate conductive layer over the semiconductor substrate, wherein a bottom surface of the control gate is in contact with a top surface of the barrier metal layer, thereby electrically connecting the floating gate to the control gate by the barrier metal layer and the low resistance layer; and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer, thereby forming gate stacks of memory cells and source/drain select transistors.