Patent ID: 7797596

Claim:
A method for testing an integrated circuit implemented in an electronic system, the method comprising: placing one or more functional blocks of the integrated circuit into an offline status; setting an electrical parameter of the one or more functional blocks of the integrated circuit to a first of a plurality of predetermined values; conducting a built-in self-test (BIST) of the one or more functional blocks of the integrated circuit; recording any failures that occur while performing the BIST; repeating said setting, said conducting, and said recording for each remaining one of the plurality of predetermined values of the electrical parameter; determining a failure rate and a passing range for the BIST for each of the predetermined values; predicting, for each of the plurality of predetermined values of the electrical parameter, a point in time at which the one or more functional blocks of the integrated circuit will fail based on the failure rates of the BIST; and determining a new value of the electrical parameter at which the one or more functional blocks of the integrated circuit is to operate based on at least one of the failure rate and the passing range for the BIST.