Patent ID: 7539927

Claim:
A decoder suitable for use in a digital communications system utilizing an RS(n′, k′) code modified from an RS(n, k) code, wherein the decoder receives n′-symbol vectors each including k′ message symbols and r′=n′−k′ parity symbols and decodes the n′-symbol vectors to correct errors therein, wherein n, k, n′, and k′ are integers, and k′<n′<n, k′<k <n, and wherein the decoder stores one erasure locator polynomial σ 0 (x), the decoder comprising: a syndrome calculator for receiving the n′-symbol vectors and for calculating syndromes of each n′-symbol vector, wherein the i-th syndrome S i of one n′-symbol vector R′, (r n′−1 , r n′−2 , . . . , r 0 ), is S i =R s (α i+1 ) for i=0, 1, . . . , n−k−1, wherein R s (x)=r n′−1 x n′−1 +r n′−2 x n′−2 + . . . +r 0 ; an index adjustment circuit for generating an adjusted error/erasure locator polynomial {tilde over (σ)}(x) and an adjusted error/erasure evaluator polynomial {tilde over (ω)}(x) based on the syndromes calculated by the syndrome calculator; a memory device for storing the one erasure locator polynomial σ 0 (x) and a look-up table; and means for finding the locations and values of the errors in each n′-symbol vector based on the adjusted error/erasure locator polynomial {tilde over (σ)}(x) and the adjusted error/erasure evaluator polynomial {tilde over (ω)}(x), using the look-up table.