Patent ID: 8659097

Claim:
A device comprising: a semiconductor substrate; a Shallow Trench Isolation (STI) region adjacent to a surface of the semiconductor substrate; a first and a second semiconductor strip comprising sidewalls and ends contacting edges of the STI region, wherein the first and the second semiconductor strips have lengthwise directions aligned to a straight line; a first and a second semiconductor fin over and joining the first and the second semiconductor strips, respectively, wherein fin heights of the first and the second semiconductor fins are smaller than about 400 Å, and wherein the semiconductor fin is comprised in a Fin Field-Effect Transistor (FinFET); and a gate stack overlapping the STI region, wherein the gate stack is between the first and the second semiconductor fins, with no additional gate stack and no additional semiconductor fins between the gate stack and the first and the second semiconductor fins, and wherein the gate stack has a lengthwise direction perpendicular to the straight line.