Patent ID: 8488358

Claim:
A semiconductor storage device, comprising: a plurality of sub memory arrays each including a plurality of memory cells and sub bit lines, the memory cells including cell transistors; main bit lines; and bit-line connecting transistors for selectively connecting the sub bit lines to one of the main bit lines, wherein the semiconductor storage device has a folded-bit-line architecture, the sub memory arrays are arranged such that the sub bit lines are aligned along the main bit lines in a first direction, a pattern formed of given numbers of the cell transistors and the bit-line connecting transistors is repeated, the main bit lines and the sub bit lines connected to one another via the bit-line connecting transistors overlap with one another in plane view along the length of the sub bit lines, and the main bit lines and the sub bit lines arranged abreast in a second direction which is perpendicular to the first direction are arranged at same intervals as one another.