Patent ID: 7719363

Claim:
An amplifier circuit, comprising: a first PMOS transistor, a source of the PMOS transistor coupled to a voltage supply, a drain of the PMOS transistor coupled to an output node of the amplifier circuit; an NMOS transistor, a drain of the NMOS transistor coupled to the output node the amplifier circuit and the drain of the first PMOS transistor, a source of the NMOS transistor coupled to a ground potential; a plurality of serially connected diode devices including a first, a second, a third, a fourth, and a fifth diode devices, the first diode device being coupled to the power supply and the fifth diode device being coupled to the gate of the first PMOS transistor; and a second PMOS transistor having a source connected between the first and the second diode devices, a drain connected between the third and the fourth diode devices, and a gate connected to the output node of the amplifier circuit, whereby the second PMOS transistor is configured to turn on and to maintain a gate-to-source bias of the first PMOS transistor within a predetermined voltage range, when the output node of the amplifier circuit is below a reference voltage.