Patent ID: 7326614

Claim:
A method of forming a semiconductor memory cell, comprising: forming first and second spaced-apart regions in a semiconductor substrate, with a channel region defined in the substrate therebetween having a first portion and a second portion, wherein the substrate has a first conductivity type and a surface, and the first and second regions have a second conductivity type; forming an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion is formed to extend along and be insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region; forming an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and forming a block of conductive material disposed over and electrically connected to the first region, wherein the floating gate second portion extends along and is insulated from a surface of the conductive material block.