Patent ID: 8847395

Claim:
A method for producing a microelectronic device, comprising: forming, on a first metal line of a first metal interconnection level, at least one semiconductor connection element arranged in a cavity formed through a dielectric layer resting on the first metal line, the at least one semiconductor connection element being configured to connect the first metal line to a second metal line of another metal interconnection line located above the first metal interconnection line, wherein the at least one semiconductor connection element extends in a length direction forming a nonzero angle with the first metal line and second metal line; forming a dielectric layer around an outer surface of the at least one semiconductor element along the length direction; and forming, in the cavity, a gate electrode configured to control conduction of the at least one semiconductor connection element, wherein the gate electrode surrounds substantially all of an outer surface of the dielectric layer along the length direction of the at least one semiconductor element.