Patent ID: 7824999

Claim:
A process for fabricating a metal oxide integrated circuit comprising the steps of: providing a substrate of monocrystalline silicon; depositing a layer of silicon nitride over the substrate; forming openings in the silicon nitride layer to expose surface regions for local oxidation; locally oxidizing the exposed surface regions of the silicon substrate to form regions of local oxide (LOCOS); removing the rest of the silicon nitride layer to expose surface regions of the silicon substrate between the LOCOS regions; oxidizing the exposed surface regions of the silicon substrate to form a gate oxide layer on the silicon substrate; depositing a polysilicon layer over the surface of the substrate; patterning the polysilicon layer to simultaneously form polysilicon gates and LOCOS protection tiles; implanting the substrate to form active regions in the semiconductor substrate; and forming metal interconnects and contact plugs to connect together at least some of the active regions; wherein the LOCOS protection tiles electrically float.