Patent ID: 8278685

Claim:
A semiconductor device comprising: a semi-insulating substrate; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the semi-insulating substrate, and have a plurality of fingers, respectively; a ground conductor placed on a second surface of an opposite side with the first surface of the semi-insulating substrate; a gate terminal electrode, a source terminal electrode, and a drain terminal electrode which are placed on the first surface of the semi-insulating substrate, connecting a plurality of fingers, respectively, and formed for every the gate electrode, the source electrode, and the drain electrode; an active layer formed on the semi-insulating substrate under the gate electrode, the source electrode, and the drain electrode; a multi stage VIA hole composed of a small caliber VIA hole near the first surface, and a large caliber VIA hole near the second surface; and a ground electrode which is formed in an internal wall surface of the multi stage VIA hole and the second surface of the semi-insulating substrate, and is connected from the ground conductor placed at the second surface side of the semi-insulating substrate for the source terminal electrode near the first surface, wherein a central axis of the large caliber VIA hole is eccentric from a central axis of the small caliber VIA hole.