Patent ID: 8856719

Claim:
A circuit simulation method for checking a circuit error using a circuit simulation tool and a schematic tool implemented by a circuit design apparatus, the method comprising: obtaining a netlist with respect to a designed circuit using the schematic tool; simulating an operation of the designed circuit using the netlist using the circuit simulation tool for displaying results of the simulation; and checking the designed circuit using the netlist using the circuit simulation tool, wherein checking the designed circuit includes: determining one or more waveforms of discrete values of elements in the designed circuit, and identifying at least one predetermined condition in the designed circuit based on the discrete values of the one or more waveforms, the discrete values determining one or more of a circuit path or a value of a node in the designed circuit corresponding to the at least one predetermined condition, and wherein the at least one predetermined condition includes a circuit path which consumes a power in an abnormal operation of the designed circuit, the circuit path formed by at least one transistor turned on based on one or more of the discrete values of the one or more waveforms.