Patent ID: 7898017

Claim:
A floating-gate memory cell, comprising: a tunnel dielectric layer overlying a silicon-containing semiconductor substrate and adjacent a trench formed in the semiconductor substrate; a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer comprises at least one silicon-containing layer; an intergate dielectric layer overlying the floating-gate layer; a control gate layer overlying the intergate dielectric layer; a first silicon oxide layer formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extending across a first portion of an edge of the tunnel dielectric layer; and a second silicon oxide layer formed on a sidewall of the trench and extending across a second portion of the edge of the tunnel dielectric layer; wherein the first and second silicon oxide layers are two distinct layers; and wherein the first and second silicon oxide layers are in contact with the tunnel dielectric layer.