Patent ID: 7964941

Claim:
A semiconductor device comprising: a chip mounting portion; a plurality of suspension leads supporting the chip mounting portion; a semiconductor chip having a front surface including a first side, and a plurality of electrode pads arranged along the first side in a plan view, and mounted over the chip mounting portion; a plurality of leads arranged along the first side of the semiconductor chip in the plan view and arranged between the suspension leads adjacent to each other in the plan view; a plurality of wires electrically connecting the electrode pads with the leads, respectively; and a molded body sealing the semiconductor chip and the wires; wherein a pitch of the leads adjacent to each other is larger than that of the electrode pads adjacent to each other; wherein the suspension leads include a first suspension lead, and a second suspension lead arranged next to the first suspension lead; wherein the leads include a first lead arranged between the first suspension lead and the second suspension lead, a second lead arranged between the first lead and the first suspension lead, a third lead arranged between the second lead and the first suspension lead, a fourth lead arranged between the first lead and the second suspension lead, a fifth lead arranged between the fourth lead and the second suspension lead; wherein a front end portion of each of the second and fourth leads is located far from the semiconductor chip than a front end portion of the first lead in the plan view; wherein a front end portion of each of the third and fifth leads is located far from the semiconductor chip than the front end portion of each of the second and fourth leads in the plan view; wherein the wires include a first wire electrically connected with the first lead, a second wire electrically connected with the second lead, a third wire electrically connected with the third lead, a fourth wire electrically connected with the fourth lead, a fifth wire electrically connected with the fifth lead; wherein a wide angle formed between the first side of the semiconductor chip and the second wire in the plan view is larger than a wide angle formed between the first side of the semiconductor chip and the first wire in the plan view; wherein a wide angle formed between the first side of the semiconductor chip and the third wire in the plan view is larger than the wide angle formed between the first side of the semiconductor chip and the second wire in the plan view; wherein a wide angle formed between the first side of the semiconductor chip and the fourth wire in the plan view is larger than the wide angle formed between the first side of the semiconductor chip and the first wire in the plan view; and wherein a wide angle formed between the first side of the semiconductor chip and the fifth wire in the plan view is larger than the wide angle formed between the first side of the semiconductor chip and the fourth wire in the plan view.