Patent ID: 7782593

Claim:
A carrier wafer, with a flat substrate with a top side and a bottom side, a first layer sequence, at least on the top side of the substrate, arranged with area parallel to the substrate and with at least one isolating layer, and at least one flat, conductive electrode arranged on the first layer sequence with area parallel to the substrate, whereby, everywhere that it is not in contact with the first layer sequence, the at least one electrode is surrounded by a second layer sequence having at least one layer made of an isolating material, wherein in at least one region, which forms at least one tunnel window and on which the at least one electrode is arranged, the first layer sequence is thinner than on the rest of its area, and wherein an electrical voltage can be applied to the substrate in such a way that the electrical field lines caused by the applied voltage pass through the at least one tunnel window, and wherein the electrode can be charged, by means of a potential difference between the electrode and the substrate caused by the applied voltage, in that electrons tunnel through the at least one tunnel window.