Patent ID: 7734675

Claim:
An apparatus for processing data, comprising: a plurality of logic elements, each of the logic elements operable to generate one or more binary results based on one or more of inputs, each logic element comprising: a NAND gate configured to generate a generate-bar output from the inputs; and a NOR gate configured to generate a kill output from the inputs; a propagate cell coupled to one or more of the logic elements that are non-complementary and operable to generate one or more conditional carryout signals, without using inverters, in a single stage based on one or more of the binary results and a carry-in signal, the propagate cell configured to: yield a carryout output of zero if the generate-bar output is one and the kill output is one; yield a carryout output of one if the generate-bar output is one, the kill output is zero, and the carry-in signal is one without inverting the carry-in signal input to the propagate cell; yield a carryout output of zero if the generate-bar output is one and the kill output is zero, and the carry-in signal is zero without inverting the carry-in signal input to the propagate cell; and yield a carryout output of one if the generate-bar output is zero and the kill output is zero; and a multiplexer operable to generate a sum that is based on a carryout signal that is based on one or more of the conditional carryout signals, and to communicate the sum to an adders circuit, a plurality of additional propagate cells are provided in parallel processing sections that receive the conditional carryout signals.