Patent ID: 8090067

Claim:
A clock-data recovery circuit, comprising: a phase rotator configured to generate a modified clock signal responsive to a first reference clock signal, a second reference clock signal and first and second control signals; a phase detector configured to receive the modified clock signal and a data signal, the phase detector further configured to generate a modified data signal and a phase adjustment signal responsive to the modified clock signal and the data signal; and a charge pump configured to receive the phase adjustment signal and generate the first and second control signals, wherein the charge pump comprises a first tuning channel and a second tuning channel, the first tuning channel using a first window comparator configured to generate a first window comparator output and a second window comparator output, the first window comparator output responsive to a first condition when the phase adjustment signal is above a first threshold value, the second window comparator output responsive to a second condition when the phase adjustment signal is below a second threshold value.