Patent ID: 7808032

Claim:
An integrated circuit comprising: a semiconductor substrate comprising a plurality of upward protrusions; a plurality of nonvolatile memory cells, each memory cell being associated with a respective one of said protrusions, different protrusions being associated with respective different memory cells of said plurality of memory cells; wherein each memory cell comprises: a first dielectric feature present at least on a top of the associated protrusion between the associated protrusion's sidewalls lying on opposite sides from said top of the associated protrusion on at least two sides of the associated protrusion, and present on said sidewalls of the associated protrusion on the at least two sides of the associated protrusion, the top of the associated protrusion being located between the associated protrusion's sidewalls; a floating gate present at least over the top of the associated protrusion between said sidewalls of the associated protrusion and present over said sidewalls of the associated protrusion over at least the two sides of the associated protrusion, the floating gate being separated from the associated protrusion by the respective first dielectric feature, the floating gate having a top surface coming down from a location over the top of the associated protrusion and between the at least two sidewalls of the associated protrusion along the at least two sides of the associated protrusion to a level below the top of the associated protrusion; a second dielectric feature over the floating gate; a conductive gate over the second dielectric feature, the conductive gate having a bottom surface coming down a location over the top of the associated protrusion and between the at least two sidewalls of the associated protrusion along at least the two sides of the associated protrusion to a level below the top of the associated protrusion; wherein the integrated circuit further comprises: a conductive line interconnecting the conductive gates and overlying the tops of the protrusions; between each two adjacent memory cells and their associated adjacent protrusions, an isolation region which is a dielectric region having a top and a bottom, wherein the isolation region's bottom is lower than the entire floating gates of the adjacent memory cells, wherein the isolation region's top is higher than bottoms of the conductive gates of the adjacent memory cells.