Patent ID: 8036283

Claim:
A data/strobe encoding scheme circuit in which data and a strobe signal are transmitted through mutually different lines, a change in the data and a change in the strobe signal are employed as clock signals for a latching operation, and the data is transmitted to a circuit operating on a second clock signal in a succeeding stage, comprising: a clock generator circuit for generating and outputting a clock signal according to predetermined data and a predetermined strobe signal and changing the clock signal when the data or the strobe signal varies; a clock enable generator circuit for generating and outputting an enable signal to enable latching of the data; a flip-flop enable flag generator circuit for creating and outputting, synchronized with the clock enable generator circuit, if the clock signal produced from the clock generator circuit is changed, a flip-flop enable flag indicating a flip-flop circuit having latched data to be received; a data latch flip-flop array including a plurality of flip-flop circuits for latching the data by a flip-flop circuit selected by an enable signal produced from the clock enable generator circuit and producing the data as flip-flop output data; a meta-stable countermeasure circuit for flip-flop data enable flag for taking meta-stable countermeasures for the flip-flop data enable flag produced from the flip-flop enable flag generator circuit; a command decoder circuit for receiving the flip-flop output data produced from the data latch flip-flop array and the flip-flop data enable flag processed through meta-stable countermeasures by the meta-stable countermeasure circuit for flip-flop data enable flag; and a meta-stable countermeasure circuit for flip-flop data acknowledge signal for taking meta-stable countermeasures for the flip-flop data acknowledge signal produced from the command decoder circuit, wherein: the command decoder circuit refers to the flip-flop data enable flag and latches, for bits thus asserted, the flip-flop output data received from the data latch flip-flop array, according to the clock signal of the succeeding-stage circuit, and asserts, each time data is received from the flip-flop circuit, the flip-flop data acknowledge signal for the flip-flop enable flag generator circuit; the flip-flop enable flag generator circuit receives the flip-flop data acknowledge signal which is produced from the command decoder circuit and for which the meta-stable countermeasure circuit for flip-flop data acknowledge signal has taken meta-stable countermeasures and then sends to the clock enable generator circuit an empty flip-flop indication signal indicating a flip-flop circuit not having held unread data; and the clock enable generator circuit receives the empty flip-flop indication signal from the flip-flop enable flag generator circuit, sequentially generates enable signals, and sets the flip-flop circuit of the data latch flip-flop array in a state not receiving new data, again to an input enable state.