Patent ID: 7016216

Claim:
A ferroelectric memory device comprising: memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor in between said two terminals; a memory cell block including the memory cells that are series connected between a first terminal and a second terminal, the first terminal being connected to a bit line via a block select transistor, the second terminal being connected to a plate line, and the cell transistor having a gate connected to a word line; a sense amplifier which amplifies data read out from the memory cell to the bit line, and generates one of a first potential and a second potential higher than the first potential in accordance with the read-out data; a precharge circuit which precharges the bit line at a third potential that is higher than the first potential and lower than the second potential; a bit line drive circuit which sets the bit line precharged by the precharge circuit at a fourth potential; and a plate line drive circuit which supplies a potential to the plate line.