Patent ID: 7335939

Claim:
A semiconductor memory device comprising: a semiconductor substrate with a main surface; an array of memory cells that are arranged in rows and columns at said main surface; wordlines that are arranged parallel and at a distance from one another along said rows; bitlines that are arranged parallel and at a distance from one another along said columns transversely to said wordlines; each of said memory cells comprising source/drain regions that are located at said main surface, a gate electrode that is arranged in a recess of said main surface between said source/drain regions, a gate dielectric that is arranged between said gate electrode and said substrate, and a memory layer that is present at least between said gate electrode and said source/drain regions; and gate interconnects being provided to electrically connect each of said gate electrodes to one of two adjacent ones of said wordlines, wherein electrical connection of said gate electrodes and said wordlines by said gate interconnects is arranged in a fashion that, along each of said rows, said gate electrodes are subsequently coupled alternatingly to one of said two adjacent wordlines.