Patent ID: 7548089

Claim:
A method of avoiding hold time violations in a programmable logic device (PLD), comprising: assigning a source logic element to drive a signal onto a programmable interconnect structure of the PLD; assigning a destination logic element to receive the signal from the programmable interconnect structure, wherein the destination logic element comprises a clock skew relative to the source logic element; implementing a signal path between the source and destination logic elements utilizing the programmable interconnect structure, wherein implementing the signal path comprises configuring an optional delay element to bypass an optional delay; wherein the delay element includes a memory cell, a logic circuit having a first input terminal coupled to receive a logic value from the memory cell, a second input terminal coupled to receive the signal, and an output terminal coupled to a plurality of serially coupled inverters, the delay element further including a transistor controlled by an inverse of the logic value from the memory cell; wherein the configuring the delay element to bypass the delay includes configuring the memory cell with a first logic value, and in response to the first logic value from the memory cell, output of the logic circuit to the inverters remains in a steady state independent of a state of the signal at the second input terminal and the transistor passes the signal to output of the delay element; checking the implemented signal path for a hold time violation; and configuring, when a hold time violation is found, the optional delay element to insert the optional delay, wherein the insertion of the optional delay overcomes the hold time violation; wherein the configuring the delay element to insert the delay includes configuring the memory cell with a second logic value that is an inverse of the first logic value.