Patent ID: 8315085

Claim:
A memory apparatus comprising: a plurality of bit cells in an array, a plurality of word lines and bit lines meeting at the bit cells and operated for selecting a given bit cell in the array by concurrently activating a word line and a bit line coupled to said given cell, for one of reading and writing to one or more selected bit cells, a pulse generator configured to generate a test signal for operating a test bit cell at a predetermined location in the array, said test bit cell including at least one switching transistor; a conductor coupling said pulse generator to said test bit cell, said conductor configured to conduct the test signal to the test bit cell, said conductor comprising an electrical path including at least a part of one of said bit lines and word lines that is enlisted for timing tracking purposes, wherein the enlisted one of said bit lines and word lines carries the test signal for changing a state of the switching transistor at the selected one or more of the bit cells; and a timing measurement circuit configured to detect operation of the switching transistor and to determine a time delay between generation of the test signal by the pulse generator and detection of a current switched by the switching transistor, said delay being a function of the location of the test bit cell in the array.