Patent ID: 7453128

Claim:
A semiconductor device comprising: an element formed on a substrate in a chip region; a multilayer structure including a plurality of dielectric films formed on the substrate; an interconnect formed in at least one of the dielectric films in the chip region; a plug formed in at least one of the dielectric films in the chip region and connecting either the element and the interconnect or the interconnect and another interconnect; a seal ring structure formed through the multilayer structure in a peripheral part of the chip region and surrounding the chip region; and a protection film formed on the multilayer structure in which the interconnect, the plug and the seal ring are provided, wherein a dual damascene interconnect in which the interconnect and the plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region, a part of the seal ring structure located in the dielectric film in which the dual damascene interconnect is formed is continuous, the seal ring structure includes at least two seal rings surrounding the chip region, the protection film has a first opening only on a top of an outermost seal ring out of the seal rings, and a cap layer is formed in the first opening to be connected to the outermost seal ring.