Patent ID: 6963511

Claim:
A semiconductor integrated circuit comprising: a plurality of chip areas each having a semiconductor chip formed therein; and a peripheral area connecting the chip areas with each other, wherein: each of said chip areas includes a plurality of electric fuse circuits each for programming control information on an internal circuit of the semiconductor chip; and said peripheral area includes: a shift register composed of a plurality of latch circuits corresponding to said electric fuse circuits, respectively; a clock pad connected via a clock supply line to a clock terminal of each of the latch circuits in said shift register; a data pad connected via a data supply line to a data terminal of one of the latch circuits on an initial stage in said shift register; a voltage pad connected to a voltage supply line; and a connecting switch circuit composed of a plurality of switches corresponding to said electric fuse circuits, respectively, and connecting the voltage supply line to a corresponding one of the electric fuse circuits according to outputs of said latch circuits in said shift register.