Patent ID: 7352631

Claim:
A method of programming a non-volatile memory (NVM) cell having a floating body, comprising during a first programming phase: applying a voltage at a first level to a drain of the NVM cell; applying a voltage at a second level to a source of the NVM cell, wherein the second level is lower than the first level; and applying a voltage at a third level to a gate of the NVM cell, wherein the third level is greater than the second level; and during a second programming phase after the first programming phase, performing one of the following steps to remove holes in the floating body: reducing the voltage on the drain to a fourth level, wherein current flows between the source and drain and wherein the fourth level is sufficiently low so as to result in minimal impact ionization; reducing the voltage on the gate to a fifth level, wherein the fifth level is lower than the second level; or reducing the voltage on the drain to a sixth level and reducing the voltage on the gate, wherein the sixth level is below the second level.