Patent ID: 7906842

Claim:
A system-in-package (SiP) comprising: a substrate obtained by cutting a wafer for each unit system; a heat radiation plate formed on the substrate; a first electronic device mounted on the heat radiation plate; a first dielectric layer on the substrate and the first electronic device; a first conductive pattern electrically connected to the first electronic device; a second dielectric layer on the first conductive pattern; one or more second electronic devices and passive devices buried between or in the second dielectric layer, said second electronic devices and said passive devices being placed above the first electronic devices; a third dielectric layer on the second electronic devices and passive devices; a second conductive pattern on the third dielectric layer and electrically connected to the second electronic device; a fourth dielectric layer on the second conductive pattern; solder bumps on the fourth dielectric layer; a first vertical conductive layer passing through the dielectric layers and electrically connected between the first and second conductive patterns; a second vertical conductive layer passing through the dielectric layers and electrically connected between the first electronic device and one of the solder bumps; a heat sink attached beneath the substrate; heat pipes formed to pass through the substrate and connecting the heat radiation plate on the substrate and the heat sink to each other; and a die attach film being placed between the first electronic device and the heat radiation plate.