Patent ID: 8379471

Claim:
A semiconductor memory device comprising: a bank including a first cell region and a second cell region; an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in response to a refresh command; and an address counting unit configured to count the refresh command and generate a row address, wherein a word line of the first cell region designated by the row address is activated when the first row active signal is activated, and a word line of the second cell region designated by the row address is activated when the second row active signal is activated, wherein the active signal generation unit comprises: a pre-active signal generation unit configured to activate a pre-active signal in response to the refresh command and a precharge signal; and an enable unit configured to transfer the pre-active signal, during a first activation period, as the first row active signal, and transfer the pre-active signal, during a second activation period, as the second row active signal when a refresh signal representing a refresh period is activated.