Patent ID: 7265599

Claim:
A flipflop comprising: a first complex gate having an output, a first input connected to a data node, and a second input connected to a clock node, the first complex gate including an OR-AND-INVERT (OAI) gate; a second complex gate having an output, a first input connected to the output of the first complex gate, and a second input connected to the clock node, the second complex gate including an AND-OR-INVERT (AOI) gate; a third complex gate having an output, a first input connected to an inverse data node, and a second input connected to the clock node, the output of the third complex gate being connected to the first complex gate, the output of the first complex gate being connected to the third complex gate, the third complex gate including an OR-AND-INVERT (OAI) gate; a fourth complex gate having an output, a first input connected to the output of the third complex gate, and a second input connected to the clock node, the output of the fourth complex gate being connected to the second complex gate, the output of the second complex gate being connected to the fourth complex gate, the fourth complex gate including an AND-OR-INVERT (AOI) gate; and an inverter connected between the data node and the inverse data node.