Patent ID: 7739560

Claim:
A nonvolatile semiconductor memory device comprising: a first nonvolatile memory cell which stores information; a test interface which receives a test command designating execution of a test for the first nonvolatile memory cell; a test storage circuit which stores test information necessary to execute the test designated by the test command, the test storage circuit comprising an erasable programmable second nonvolatile memory cell, the second nonvolatile memory cell having the same structure as the first nonvolatile memory cell; a decoder which decodes the test command input to the test interface, and selects the test information stored in the test storage circuit based on the decoded test command input; a sense amplifier which is common to the test storage circuit and first nonvolatile memory cell, reads out, from the test storage circuit, the test information selected by the decoder and reads out the information stored in the first nonvolatile memory cell; a holding circuit which holds the test information read out by the sense amplifier; a control circuit which controls a test operation of checking whether the first nonvolatile memory cell normally operates, on the basis of the test information held in the holding circuit; and a defect storage circuit associated with the first nonvolatile memory cell, the defect storage circuit storing fail information indicating that the first nonvolatile memory cell is defective if the first nonvolatile memory cell does not normally operate in the test operation performed by the control circuit.