Patent ID: 7691663

Claim:
A method for manufacturing a complementary metal-oxide semiconductor (CMOS) image sensor, the method comprising: preparing a semiconductor substrate having a p-type epitaxial layer, wherein the semiconductor substrate includes a pixel array area and a logic circuit area; forming a plurality of doped regions in the p-type epitaxial layer of the pixel array area to fabricate a plurality of pixel sensors grouped with one another in the pixel array area, wherein doped regions for each pixel sensor are provided to fabricate a photodiode, a MOSFET transfer transistor, a MOSFET reset transistor, a MOSFET drive transistor, and a MOSFET select transistor; forming a plurality of doped regions in the p-type epitaxial layer of the logic circuit area to fabricate a plurality of MOSFET transistors in the logic circuit area, wherein the plurality of MOSFET transistors in the logic circuit area include one or more n-channel MOSFETs and one or more p-channel MOSFETs; forming a field oxide in a region around the pixel array area to physically separate and isolate the plurality of pixel sensors in the pixel array area from the plurality of MOSFET transistors in the logic circuit area; depositing a first gate insulating layer concurrently over both the pixel array area and the logic circuit area; forming a mask over the first gate insulating layer on the pixel array area, wherein the mask leaves the first gate insulating layer over the logic circuit area exposed; removing the first gate insulating layer from the logic circuit area while leaving the first gate insulating layer over the pixel array area intact; removing the mask from the pixel array area; depositing a second gate insulating layer over both the pixel array area and the logic circuit area; removing the second gate insulating layer from selected areas of the logic circuit area to leave gate areas available for use in completing fabrication of the plurality of MOSFET transistors in the logic circuit area, wherein the gate area for each of the plurality of MOSFET transistors in the logic circuit area has a thickness from approximately 5 Å to approximately 40 Å; and removing both the first and second gate insulating layers from selected areas of the pixel array area to leave gate areas formed by the first and second gate insulating layers available for use in completing fabrication of the MOSFET transfer transistor, the MOSFET reset transistor, the MOSFET drive transistor, and the MOSFET select transistor for each of the pixel sensors, wherein the gate area for each MOSFET transistor in the pixel array area has a gate insulating layer thickness from approximately 40 Å to approximately 90 Å, and wherein the thickness of the gate insulating layer of the MOSFETs in the pixel array area is greater than the thickness of the gate insulating layer of the MOSFETs in the logic circuit area.