Patent ID: 7081383

Claim:
A method for fabricating memory cells, comprising: providing an electrically conductive substrate; etching a trench structure, which has side walls and a base, into the substrate; depositing a first insulation layer at the side walls of the trench structure that does not cover the base; depositing a catalyst material on the base of the trench structure, in such a manner that an electrical connection is provided between the electrically conductive substrate and the catalyst material; growing at least one nanostructure within the trench structure, starting from and electrically connected to the catalyst material deposited on the base of the trench structure; depositing a second insulation layer on the nanostructure which has grown in the trench structure and on the base of the trench structure; and depositing an electrically conductive layer on the first insulation layer and second insulation layer, the electrically conductive layer extending into the trench to form an electrode.