Patent ID: 7423486

Claim:
A differential amplifier circuit formed on an SOI substrate, comprising: a bias section activated and deactivated by an enable signal, outputting a predetermined bias potential when activated, and outputting a first power-supply potential when deactivated; a first MOS transistor of a first channel type, having a source receiving the first power-supply potential, a gate receiving the potential output by the bias section, and a drain connected to a first node; a second MOS transistor of the first channel type, having a body, a source connected to the first node, a gate receiving a first differential input signal, and a drain connected to a second node; a third MOS transistor of the first channel type, having a body, a source connected to the first node, a gate receiving a second differential input signal, and a drain connected to a third node; a fourth MOS transistor of the first channel type, having a source connected to the first node, a gate receiving the enable signal, and a drain connected to the body of the second MOS transistor of the first channel type; a fifth MOS transistor of the first channel type, having a source connected to the first node, a gate receiving the enable signal, and a drain connected to the body of the third MOS transistor of the first channel type; a source-tied first MOS transistor of a second channel type, having a source receiving a second power-supply potential, a gate connected to the second node, and a drain connected to the second node; a source-tied second MOS transistor of the second channel type, having a source receiving the second power-supply potential, a gate connected to the second node, and a drain connected to the third node; and an output section connected to the third node, generating an output signal from the potential of the third node.