Patent ID: 8653645

Claim:
A semiconductor device comprising: a plurality of stacked LSIs connected by through vias, the plurality of LSIs including a first LSI and a second LSI, wherein the first LSI includes a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction, wherein the second LSI includes a second circuit block, which is different from the first circuit block, formed on a second semiconductor substrate having first and second sides extending in the first direction and third and fourth sides extending in the second direction, the first circuit block including a processing unit, and the second circuit block including a memory; signal-line through vias for transmitting signals from the first circuit block to the second circuit block; and power-supply through vias for supplying power to the first circuit block, wherein a respective plurality of rows of the power-supply through vias is disposed along each of the four sides of the first and second substrates at outermost peripheries of the first and second LSIs, wherein a respective plurality of rows of the signal-line through vias is disposed along each of the four sides of the first and second substrates, wherein along each side of the four sides of the first and second substrates the respective plurality of rows of the signal-line through vias is disposed between the respective plurality of rows of the power-supply through vias and the corresponding circuit block.