Patent ID: 8243058

Claim:
A gate driving circuit including a plurality of stages cascade-connected to each other, each of the plurality of stages outputting a plurality of gate signals, an m-th stage of the stages comprising: a pull-up part for outputting a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage received from a first output control part; a pull-down part for pulling down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal; a first holding part for holding a voltage received from the first output control part as a second low voltage having a level lower than the first low voltage in response to the high voltage of the clock signal; and a second holding part for holding a low voltage of the m-th gate signal to the first low voltage in response to the high voltage of the clock signal.