Patent ID: 7577020

Claim:
A memory device manufactured in semiconductor processes comprising: a plurality of random access memory (RAM) cells and a select transistor connected in series to form a memory string, each of the plurality of RAM cells toggles among at least two stable resistive levels to represent at least two logic states, respectively; a resistance sensing circuit coupled to the memory string for measuring a resistance level thereof; an address decoder coupled to a gate of the select transistor for selectively engaging the memory string to the resistance sensing circuit; a toggle control circuit configured to selectively toggle at least one of the plurality of RAM cells after a first measurement of the resistance level of the memory string and toggle back the at least one of the plurality of memory cells after a second measurement of the resistance level of the memory string; and a logic control circuit coupled to the resistance sensing circuit and the toggle control circuit, and being configured to compare both the first and second measurement results with a plurality of predetermined values and to use the comparison result to determine the data stored in the memory string.