Patent ID: 7777855

Claim:
A thin film transistor substrate having gate shorting line and gate shorting bar connection, comprising: a gate lines formed on a substrate; a data lines intersect the gate lines with a gate insulating film there-between; a thin film transistor formed at the intersection of the gate lines and the data lines; a protective film that covers a thin film transistor formed on the gate insulating film; a pixel electrode that is connected, via a first contact hole that passes through the protective film, to the thin film transistor; a gate shorting bar connected to an odd and an even gate shorting line that extends from a gate pad connected to the gate line; a data shorting bar connected to a data shorting line extended from a data pad connected to the data line; and an open hole that separates at least one of the odd and the even gate shorting lines from the gate shorting bar, wherein the gate shorting bar includes a first gate shorting bar connected to the odd gate shorting line that extends from the gate pad and a second gate shorting bar connected via a second contact hole and a transparent conductive layer formed on the second contact hole to the even gate shorting line; wherein the even gate shorting line is separated from the first gate shorting bar by the open hole, wherein the data shorting line includes an odd and even data shorting line, wherein the first gate shorting bar is formed simultaneously on the substrate along with the odd and even gate shorting lines by a mask process using the same metal as the gate lines, wherein the second gate shorting bar is simultaneously formed along with the data lines and is formed to cross with the gate shorting lines with having the gate insulating film therebetween, wherein the data lines is formed in a crossed manner with the odd and even gate shorting line on a gate insulating film of the substrate by a mask process using the same metal as the data line, wherein the gate insulating film is located between the first gate shorting bar and the second gate shorting bar, wherein the second gate shorting bar is insulated from the odd gate shorting line by the gate insulating film and is connected to the even gate shorting line via the second contact hole passing through the protective film and the gate insulating film, wherein the thin film transistor includes a channel protective film to protect an active layer of the thin film transistor, wherein the open hole formed on the protective film passes through the protective film and the gate insulating film to expose the substrate and separates the even gate shorting line and the first gate shorting bar on the protective film.