Patent ID: 7757192

Claim:
An integrated circuit designing device for performing wiring design of shielded clock wiring used in an integrated circuit, comprising: a storage unit configured to store a table of identifiers of shielded clock wiring usable in the integrated circuit and, dividing rule information in correspondence with each identifier, describing a way of dividing the shielded clock wiring indicated by the each identifier; an input unit configured to input a wiring layer of a shielded clock wiring of a wiring request, an identifier of the shielded clock wiring of the wiring request, and a starting point and an end point of the shielded clock wiring of the wiring request, and thereby input the wiring request for the shielded clock wiring; a specifying unit configured to refer to the storage unit to specify a dividing rule of the shielded clock wiring indicated by the identifier inputted by the input unit; and a judging unit configured to judge whether to permit the shielded clock wiring of the wiring request, by judging whether shielded clock wiring resulting from division based on the dividing rule specified by the specifying unit is spatially permissible.