Patent ID: 7719330

Claim:
A phase locked loop device comprising: a phase/frequency detector generating a compared signal corresponding to a phase difference between a reference clock signal and a feedback clock signal; a charge pump, generating a pump current according to the compared signal; a low pass filter coupled to the charge pump to generate an operating voltage corresponding to the pump current; a voltage-controlled oscillator coupled to the low pass filter to generate an output clock signal in response to the operating voltage; and a control unit coupled to the low pass filter and the voltage-controlled oscillator, wherein when the frequency of the output clock signal is out of a predetermined frequency range, the control unit constrains the operating voltage to a predetermined voltage level, and the control unit comprising: a voltage comparator providing a first output signal corresponding to the voltage level difference between the operating voltage and an inner-reference voltage; a clock detector, coupled to the voltage comparator and the output clock, generating a second output signal in response to the first output signal and the output clock signal; and a voltage converter coupled to the clock detector to constrain the operating voltage to the predetermined voltage level corresponding to the second output signal.