Patent ID: 7670866

Claim:
A method, comprising: joining a plurality of separate, generally coplanar dies using a molding material to form a molded substrate having said plurality of dies joined together with molding material between adjacent dies, each die having an integrated circuit and a plurality of terminals electrically coupled to the integrated circuit of the die; and forming interconnects on said die terminals and the molded substrate to electrically connect selected terminals of said integrated circuits of at least two generally coplanar dies of said dies together; wherein said joining includes molding said molding material in the shape of a semiconductor wafer around the separate dies wherein the molding material fills spaces between the dies, and curing the molding material until it hardens sufficiently to support the dies, and wherein said interconnect forming includes forming said interconnects on said molding material between the dies after the molding material is cured and hardened to electrically connect at least two generally coplanar dies together.