Patent ID: 7469389

Claim:
A standard cell library comprising: a plurality of types of standard cells, each standard cell including patterns in a plurality of layers arranged within a cell frame, the cell frame having a fixed height and a width of an integer times a unit width Wu, for forming a semiconductor integrated circuit by placing selected ones of the plurality of types of standard cells such that left, right, upper, and lower boundaries of the cell frame being in contact with boundaries of other cell frames, the plurality of types of standard cells including a first plurality of types of standard cells, the patterns of each of the first plurality of types of standard cells including: first transistor patterns for forming a first conduction-type transistor arranged within an upper side of the cell frame and second transistor patterns for forming a second conduction-type transistor arranged within a lower side of the cell frame; a first threshold voltage adjusting pattern for doping a first impurity to adjust an threshold voltage of the first conduction-type transistor, the first threshold voltage adjusting pattern having an upper boundary that contacts the upper boundary of the cell frame, and having a left and a right boundary, and a second threshold voltage adjusting pattern for doping a second impurity to adjust an threshold voltage of the second conduction-type transistor, the second threshold voltage adjusting pattern having a lower boundary that contacts the lower boundary of the cell frame, and having a left and a right boundary, wherein: each of a distance D 1 between the left boundary of the first threshold voltage adjusting pattern and the left boundary of the cell frame, a distance D 2 between the right boundary of the first threshold voltage adjusting pattern and the right boundary of the cell frame, a distance D 3 between the left boundary of the second threshold voltage adjusting pattern and the left boundary of the cell frame, and a distance D 4 between the right boundary of the second threshold voltage adjusting pattern and the right boundary of the cell frame is expressed as Di=Wu×ni/2 (i=1, 2, 3, 4, ni is an integer equal to or larger than 0); and Wu≧Wmin and Wu≧Smin where Wmin is a minimum allowable width and Smin is a minimum allowable space set by a design rule of the semiconductor integrated circuit for each of the first and the second threshold voltage adjusting patterns, both n 1 and n 2 are even numbers or odd numbers and both n 3 and n 4 are even numbers or odd numbers for all of the first plurality of types of standard cells.