Patent ID: 8380149

Claim:
A DC offset canceller comprising: a first DA converter configured to DA-convert first correction data into a first correction voltage; a first adder configured to add an input signal and the first correction voltage to output a first added signal; an amplifier configured to amplify the first added signal to output an amplified signal; a comparator configured to compare the amplified signal and a reference voltage to output a comparison result; an averaging circuit configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period; and a successive approximation register configured to sequentially set each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases, wherein the averaging circuit comprises a first counter configured to count one logical value of the comparison results based on a clock, a second counter configured to count the number of clocks of the clock, and a magnitude comparator configured to, at a timing when the number of clocks reaches a predetermined number of clocks, if the number of counts of the one logical value is greater than or equal to a half of the predetermined number of clocks, output the one logical value of the comparison results as the majority decision result, and if the number of counts of the one logical value is less than a half of the predetermined number of clocks, output the other logical value of the comparison results as the majority decision result.