Patent ID: 7173876

Claim:
A semiconductor integrated circuit comprising: a memory cell having a port through which data is input to and output from a set of bit lines when a word line is driven; a write/read circuit connected with the port via the set of bit lines for writing data to the memory cell and for reading data from the memory cell; a read circuit connected with the port via the set of bit lines for reading data from the memory cell; a CPU-system control circuit that controls the write/read circuit so that a data write or read operation based on at least one of a write request and a read request from a CPU is performed for a first period; and a display-system control circuit that controls the read circuit so that data to be supplied to a display panel is read for a second period which does not overlap the first period, wherein the CPU-system control circuit includes: a first circuit that activates a write control signal based on a write request signal sent from the CPU; and a second circuit that activates a read control signal based on a read request signal sent from the CPU, and the display-system control circuit includes a third circuit that activates a display-data read control signal based on at least the write request signal and read request signal sent from the CPU and a display-data read request signal sent from a timing generator circuit.