Patent ID: 8537886

Claim:
A programmable integrated circuit device comprising: a decision feedback equalizer configured to equalize an input signal, wherein the decision feedback equalizer comprises: a summer circuit configured to sum the input signal with a plurality of signals, wherein the summer circuit includes a first transistor and second transistor arranged as a differential pair; the first transistor configured to receive the input signal and the second transistor configured to receive a complement of the input signal; a resistor disposed between the first transistor and the second transistor configured to provide resistor degeneration; a first current source disposed at a first node connecting the first transistor and the resistor, the first current source configured to provide offset cancellation; and a second current source disposed at a second node connecting the second transistor and the resistor, the second current source configured to provide offset cancellation; and logic circuitry configured to control the first current source and the second current source based on stored calibration data.