Patent ID: 7005354

Claim:
A method of fabricating a depletion drain-extended MOS transistor, comprising: forming a first well of a first conductivity type in a substrate; forming a second well of a second conductivity type in the substrate, the first and second conductivity types being opposite, wherein portions of the first and second wells overlap in a compensated channel region of the substrate; forming a drain of the first conductivity type in a portion of the first well; forming a source of the first conductivity type in a portion of the second well; forming a thick dielectric extending laterally from a first end adjacent the drain to a second opposite end in the first well, the thick dielectric extending into the first well of the substrate; forming a thin dielectric over the substrate, the thin dielectric extending from the second end of the thick dielectric in the first well to the source in the second well, a portion of the thin dielectric extending over the compensated channel region of the substrate; and forming a conductive gate contact structure extending over the thin dielectric and over a portion of the thick dielectric, wherein said compensated channel region is located directly adjacent said source and spaced apart from said thick dielectric.