Patent ID: 7679952

Claim:
An electronic circuit, comprising a memory matrix comprising rows and columns of memory cells, the matrix comprising: first row conductors for each of the rows, each first row conductor corresponding to a respective row of cells; second row conductors corresponding to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair and; column conductors for each of the columns, wherein each of said memory cells comprises an access transistor, a node and a first and second resistive memory element, wherein the access transistor has a control electrode electrically coupled to the first row conductor of the row of the memory cell, a main current channel electrically coupled between the column conductor for the column of the memory cell and the node, the first and the second resistive memory element are electrically coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.