Patent ID: 7994835

Claim:
A duty control circuit configured to control duty of a clock signal, the duty control circuit comprising: a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal; a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied; and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies in accordance with the slew rate of the signal at the second node, wherein the slew controller includes: an “n” (where “n” is a positive integer) number of first switches that include first electrodes receiving a same one of the first voltage level or the second voltage level, the first switches being controlled by the input clock signal; and an “n” number of second switches that are connected between second electrodes of the “n” number of first switches and the second node, and which selectively connect the second electrodes of the “n” number of first switches to the second node, each of the “n” number of second switches being switched on in response to a corresponding control signal so as to provide the same one of the first voltage level or the second voltage level to the second node.