Patent ID: 6943118

Claim:
A method of fabricating a flash memory, comprising: sequentially forming a tunneling dielectric layer, a first conductive layer and a mask layer on a substrate; patterning the tunneling dielectric layer, the first conductive layer and the mask layer to form at least a strip structure; performing an ion implantation to form a buried drain region in the substrate at one side of the strip structure; patterning the strip structure to form a gate structure, wherein the gate structure includes the tunneling dielectric layer, the mask layer, and the first conductive layer; forming an insulation layer adjacent to a sidewall of the gate structure, the insulation layer having a top surface lower than a top surface of the first conductive layer in a manner to expose a part of a sidewall of the first conductive layer; forming a material layer on the insulation layer sideways adjacent to the gate structure; removing the mask layer; forming a second conductive layer on the top surface of the first conductive layer of the gate structure, wherein the second conductive layer covers the top surface of the first conductive layer and further extends over the adjacent material layer and the first conductive layer and the second conductive layer together form a floating gate; removing the material layer to expose a part of the sidewall of the first conductive layer of the gate structure; forming a gate dielectric layer over the floating gate; and forming a control gate on the gate dielectric layer.