Patent ID: 7808035

Claim:
A semiconductor memory having a semiconductor substrate with a surface layer covered by an interlayer dielectric film of silicon oxide and a plurality of memory cells formed on the surface layer within the interlayer dielectric film, each memory cell including a gate electrode with a pair of side surfaces, a gate insulation film interposed between the gate electrode and the surface layer of the semiconductor substrate, a pair of highly doped diffusion regions formed in the surface layer of the semiconductor substrate on both sides of the gate electrode, and a pair of multilayer memory elements formed on the side surfaces of the gate electrode, the multilayer memory elements extending onto the highly doped diffusion regions of the semiconductor substrate, each multilayer memory element comprising: a first silicon oxide layer formed on one of the side surfaces of the gate electrode, extending to a bottom of said one of the side surfaces and onto one of the highly doped diffusion regions; a charge trapping nitride layer formed on the first silicon oxide layer; a second silicon oxide layer formed on the charge storage nitride layer; a protective silicon nitride layer formed directly on the second silicon oxide layer, so as to touch the second silicon oxide layer; a hard mask silicon nitride layer disposed on the gate electrode; and a silicon nitride stopper film disposed between the hard mask silicon nitride layer and the interlayer dielectric film so as to touch the hard mask silicon nitride layer, and being disposed between the multilayer memory elements and the interlayer dielectric film.