Patent ID: 8161337

Claim:
Test circuitry comprising: A. plural circuit blocks, each circuit block being a separate test domain and each circuit block including: i. an instruction register, a data register connected to the instruction register, gating circuitry connected to the instruction register, an instruction register multiplexer connected to the instruction register, and a data register multiplexer connected to the gating circuitry and coupled to the data register, the circuit blocks being connected together serially via serial data input leads and serial data output leads coupled with the data register; ii. a wrapper serial port circuitry connected to a capture lead, an update lead, a transfer lead, a shift lead a select lead, a reset lead, and a clock lead, the capture lead, the update lead, the transfer lead, and the shift lead also being connected to the gating circuitry, the wrapper serial port circuitry having a first output connected to the instruction register multiplexer and a second output connected to the data register multiplexer; and iii. a test access port controller connected to a test mode select lead, a test clock lead and having an instruction control bus output and a data control bus output, the instruction control bus is connected to the instruction register multiplexer, and the data control bus is connected to the data register multiplexer and gating circuitry; and B. a wrapper enable lead coupled to a control input of the data register multiplexer of each circuit block.