Patent ID: 8347312

Claim:
A device comprising one or more processors, each of the one or more processors comprising: an execution unit for executing a plurality of threads, each of the plurality of threads comprising a sequence of instructions; sets of thread registers, each of the sets of thread registers being arranged to store information relating to a respective one of the plurality of threads; and circuitry comprising a plurality of channel terminals and being operable to establish a channel between one of the sets of thread registers of the one or more processors and another one of the sets of thread registers of the one or more processors via one of the plurality of channel terminals of the one or more processors and any other one of the plurality of channel terminals of the one or more processors; wherein each of the channel terminals comprises at least one buffer operable to buffer data transferred over the channel, and a channel terminal identifier register operable to store a channel terminal identifier of the other of the channel terminals via which the channel is established, the channel terminal identifier register of the one of the plurality of channel terminals being operable to store the channel terminal identifier of the other one of the plurality of channel terminals and the channel terminal identifier register of the other one of the plurality of channel terminals being operable to store the channel terminal identifier of the one of the plurality of channel terminals; wherein the execution unit is operable to execute at least one transfer instruction of one of said plurality of threads for transferring information over the channel; and wherein the circuitry is operable to disconnect the channel, so that said one of the plurality of channel terminals is available for connecting with a further one of the plurality of channel terminals of the one or more processors by storing a channel terminal identifier of the further one of the plurality of channel terminals in the channel terminal identifier register of said one of the plurality of channel terminals.