Patent ID: 8653646

Claim:
A microelectronic package, comprising: a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function, the microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face, the microelectronic element including a plurality of stacked electrically interconnected semiconductor chips; a plurality of terminals on the second surface of the substrate configured for connecting the microelectronic package with at least one component external to the microelectronic package, the terminals electrically connected with the substrate contacts and including first terminals disposed at locations within first and second parallel grids each grid disposed on a respective side of an axis, the first terminals in each grid being configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, the terminals including second terminals arranged at positions within third and fourth parallel grids, the second terminals configured to carry second information, the second information being other than the information carried by the first terminals, the second information including data signals, wherein the first and second grids separate the third and fourth grids from one another, the first terminals having signal assignments, wherein the signal assignments of the first terminals in the first grid are symmetric about the axis with the signal assignments of the first terminals in the second grid, such that of the first terminals of the first grid that are configured to carry address information, each of such first terminals is configured to carry the same address information as a corresponding one of the first terminals of the second grid at a position symmetric about the axis with respect to such first terminal.