Patent ID: 6880021

Claim:
An apparatus comprising: a processor handling an I/O request in an I/O operation; main storage controlled by the processor for storing data; one or more I/O devices for sending data to or receiving data from said main storage; a vector mechanism operable to register I/O requests by said devices to send or receive data from said main storage; a dispatcher operable to poll said vector mechanism to determine if there is an outstanding I/O request; and an override bit having a first condition when an immediate interrupt is to be sent to said processor for handling an I/O request from said I/O device(s), and a second condition when said dispatcher is to poll said vector mechanism to determine if there is an outstanding I/O request, said override bit being set to its first condition or reset to its second condition by said processor, and further comprising a Target Delay Interval (TDI) register containing a TDI value for determining when the vector mechanism should not be polled by said dispatcher and an interrupt given to said processor, and wherein said override bit, when in its first condition, overrides said TDI value and drives an immediate interrup to said processor.