Patent ID: 7414435

Claim:
A circuit arrangement for converting logic signal levels, said circuit arrangement comprising: a level converter comprising: a first signal path and a second signal path each having a series circuit comprising a transistor of a first conductivity type and a transistor of a second conductivity type; a first signal input and a second signal input for supplying a push-pull signal; a first output coupled to a tap between the transistors of the series circuit of the first signal path; a second output coupled between the transistors of the series circuit of the second signal path; wherein the transistors of the first conductivity type can be controlled by means of the push-pull signal; and wherein the transistors of the second conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path; a third signal path that is coupled between the output of the first signal path and a second supply potential connection and comprises a first resistor and a further transistor that is coupled in series with the first resistor and has a control input that is coupled to an activation input; a fourth signal path that is coupled between the output of the second signal path and the second supply potential connection and comprises a second resistor and a further transistor that is coupled in series with the second resistor and has a control input that is coupled to the activation input; and a mixing arrangement for influencing comprising: a first input that is coupled to the first output of the level converter; a second input that is coupled to the second output of the level converter; and a first signal output and a second signal output for tapping off output signals; wherein the first input is coupled to the first signal output and the second input is coupled to the second signal output; wherein the first input is coupled to the second signal output via at least one inverter; and wherein the second input is coupled to the first signal output via at least one inverter.