Patent ID: 7319712

Claim:
A scrambling code generation apparatus generating a scrambling code used in a scrambling operation of transmission data, comprising: a shift register formed of a plurality of stages of registers connected so as to execute a feedback operation and a spreading operation to generate a sequence of scrambling codes by a predetermined generating polynomial; an arithmetic circuit computing values of said registers involved with said feedback operation and said spreading operation that would have been obtained if said shift register carries out a shift operation for an increasing predetermined number of times based on predetermined initial values; an input circuit applying said computed values of registers into corresponding said registers; and a control circuit controlling said arithmetic circuit and said input circuit so that said arithmetic circuit computes values of said registers and said input circuit applies said computed values into said registers until all said plurality of stages of registers store valid values based on said computed values; wherein said shift register continues a shift operation based on valid values stored in all of said plurality of stages of registers to generate said sequence of scrambling codes.