Patent ID: 6870569

Claim:
An apparatus including an integrated circuit with a signal demultiplexor, comprising: signal separating circuitry that receives a multiplexed signal with first, second and third input signal state levels transcending a lower signal threshold, transcending an upper signal threshold and having a value between said lower and upper signal thresholds, respectively, separates first and second input signals from said multiplexed signal, and provides corresponding first and second separated signals, wherein said first separated signal includes first and second separated signal state levels corresponding to said first and second input signal state levels, and said second separated signal includes a third separated signal state level corresponding to said first input signal state level and a fourth separated signal state level corresponding to said second and third input signal state levels; signal processing circuitry, coupled to said signal separated circuitry, that receives and processes said first and second separated signals to provide a processed signal with first and second processed signal state levels corresponding to and time delayed from said first, second and third input signal state levels, wherein said first processed signal state level corresponds to said first and second input signal state levels, and said second processed signal state level corresponds to said third input signal state level; and signal gating circuitry, coupled to said signal separating and processing circuitry, that receives said processed and first separated signals and gates said processed signal in response to said first and second separated signal state levels to provide a gated signal with a plurality of asserted signal states defining a time interval substantially equal in duration to another time interval during which said third multiplexed signal state level is between said lower and upper signal thresholds.