Patent ID: 6856542

Claim:
An integrated circuit, comprising: a programmable logic device (PLD), comprising: an array of PLD cells, each of a plurality of PLD cells comprising a nonvolatile transistor and a select transistor connected in series between a bit line and a source line, a control terminal of the nonvolatile transistor being connected to a predetermined voltage level and a control terminal of the select transistor being coupled to an input of the PLD, the nonvolatile transistors being disposed in at least one first area within the array and the select transistors being disposed in at least one second area within the array, the at least one second area being disposed adjacent the at least one first area; a plurality of sense amplifiers, each sense amplifier being coupled to a distinct source line; and an array of combinational logic having inputs coupled to the sense amplifiers and at least one output coupled to an output of the PLD.