Patent ID: 6903418

Claim:
A semiconductor device comprising: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first electrode layer on the first major surface having a first peripheral portion; a second electrode layer on the second major surface; an active region in a vicinity of the first major surface, the active region being in electrical contact with the first electrode layer; a layer with low electrical resistance of a first conductivity type in a vicinity of the second major surface, the layer with low electrical resistance being in electrical contact with the second electrode layer; a drain drift region between the first major surface and the layer with low electrical resistance, the drain drift region providing a vertical drift current path in the ON-state of the semiconductor device, the drain drift region being depleted in the OFF-state of the semiconductor device, wherein the drain drift region comprises a first alternating conductivity type layer comprising vertically extending first semiconductor regions of the first conductivity type and vertically extending second semiconductor regions of a second conductivity type arranged alternately at a first pitch of repeating; a breakdown withstanding region around the drain drift region, the breakdown withstanding region being between the first major surface and the layer with low electrical resistance, the breakdown withstanding region providing substantially no current path in the ON-state of the semiconductor device, the breakdown withstanding region being depleted in the OFF-state of the semiconductor device, the breakdown withstanding region comprising a second alternating conductivity type layer comprising vertically extending third semiconductor regions of the first conductivity type and vertically extending fourth semiconductor regions of the second conductivity type arranged alternately at a second pitch of repeating; an under region below the first peripheral portion of the first electrode layer, the under region comprising a third alternating conductivity type layer comprising vertically extending fifth semiconductor regions of the first conductivity type and vertically extending sixth semiconductor regions of the second conductivity type arranged alternately at a third pitch of repeating; and wherein the third pitch of repeating is narrower than the first pitch of repeating.