Patent ID: 8324109

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a gate insulation layer over a substrate; sequentially forming a silicon layer and a metal layer over the gate insulation layer; performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern; performing a second gate etching process to partially etch the silicon layer beneath the metal layer while not exposing the gate insulation layer, thereby forming an undercut beneath the metal layer; forming a capping layer on both sidewalls of the first pattern including the undercut; performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern; and performing a gate re-oxidation process.