Patent ID: 8283779

Claim:
A semiconductor device, comprising: a substrate having a first surface and a second surface opposing the first surface, the second surface being compartmentalized into a bump-free area provided along four sides of the substrate and a bump area which is surrounded by the bump-free area; a plurality of connection pads provided on the first surface of the substrate; a semiconductor chip mounted on the first surface of the substrate, the semiconductor chip being electrically coupled to the plurality of connection pads; and a plurality of bumps provided on the bump area of the second surface, the plurality of bumps being electrically coupled to the plurality of connection pads, respectively, wherein the plurality of bumps includes a first group of bumps aligned along the four sides and a second group of bumps surrounded by the first group, and a first subgroup of bumps included in the first group and aligned along one side of the four sides is shifted with respect to a second subgroup of bumps included in the first group and aligned along an opposing side of the four sides in a direction parallel to the one side.