Patent ID: 8473541

Claim:
An M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit, the M-bit adder comprising: M adder cells arranged in R rows including a first row and R−1 subsequent rows, each row subsequent to the first row having more adder cells than a preceding row, wherein each row of adder cells includes a least significant adder cell and at least one subsequent adder cell, wherein each adder cell is configured to receive a data bit A X , from the first M-bit argument, and a data bit, B X , from the second M-bit argument, wherein each adder cell subsequent to the least significant adder cell within each row subsequent to the first row is configured to receive a first conditional carry-in bit, C X−1 ( 1 ), from a preceding adder cell within the row, and a second conditional carry C X−1 ( 0 ), from the preceding adder cell within the row, and wherein each adder cell within a row subsequent to the first row is configured to generate a first conditional carry-out bit C X ( 1 ), and a second conditional carry-out bit, C X ( 0 ), wherein the C X ( 1 ) bit is calculated assuming a carry-out bit from a most significant adder cell within the preceding row is a 1 and C X ( 0 ) bit is calculated assuming the carry-out it from the most significant adder cell within the preceding row is a 0, wherein each adder cell subsequent to the least significant adder cell within each row further comprises: first and second passgates receiving the first and second conditional carry-in bits C X−1 ( 1 ) and C X−1 ( 0 ), respectively; and first and second inverters coupled to the first and second passgates, wherein the respective adder cell is configured to generate the first conditional carry-out bit C X ( 1 ) and the second conditional carry-out bit C X ( 0 ) by inverting and propagating the first conditional carry-in bit C X−1 ( 1 ) and the second conditional carry-in bit C X−1 ( 0 ), respectively, and wherein alternate adder cells subsequent to the least significant adder cell within each row are configured to invert and propagate the first and second conditional carry-in bits C X−1 ( 1 ) and C X−1 ( 0 ) as the first and second conditional carry-out bits C X ( 1 ) and C X ( 0 ) when the data bit A X and the data bit B X are equal, and wherein intervening adder cells subsequent to the least significant adder cell within each row are configured to invert and propagate the first and second conditional carry-in bits C X−11 ( 1 ) and C X−1 ( 0 ) as the first and second conditional carry-out bits C X ( 1 ) and C X ( 0 ) when the data bit A X and the data bit B X are not equal.