Patent ID: 7448009

Claim:
A method of reducing leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells for particular circuit functions, the library including a plurality of cells for each circuit function, comprising the steps of: considering design cells in a predetermined order; for each considered design cell determining if said design cell had a timing slack greater than a predetermined slack limit; for each design cell determined to have said timing slack, determining if said design cell has an output slew rate less than a slew limit; for each design cell determined to have said output slew rate, determining all candidate cells in said library having the function of said design cell; for all candidate cells for each design cell determining eligible candidate cells which have a size no greater than said design cell, timing slack less than a predetermined slack limit, output slew less than a predetermined output slew limit and leakage current less than said design cell; for each design cell selecting a candidate cell having the least leakage current; and substituting said candidate cell having the least leakage current for said design cell.