Patent ID: 6891438

Claim:
A power amplifier circuit comprising: an FET amplifier including a gate terminal, a drain terminal and a source terminal; a current sensing element coupled to the drain terminal of the FET amplifier, said current sensing element providing a measured voltage signal indicative of a quiescent drain current of the FET amplifier; a switch coupled across the sensing element and being responsive to a switch signal, said switch signal closing the switch to bypass the sensing element when data is being amplified by the FET amplifier and opening the switch to sense the quiescent drain current when data is not being amplified by the FET amplifier; and a sample and hold circuit responsive to the measured voltage signal across the sensing element and a reference voltage signal, said sample and hold circuit forcing the measured voltage signal as close as possible to the reference voltage signal by a negative feedback through the amplifier circuit to regulate the current through the sensing element and set the quiescent drain current of the FET amplifier, said sample and hold circuit generating a DC bias voltage that is applied to the gate terminal of the FET amplifier.