Patent ID: 8738888

Claim:
A memory device packaged into one package, comprising: a first memory device and a second memory device; a command interface which receives access commands from an outside source, and supplies the access commands to a corresponding one of the first memory device and the second memory device; a data bus divided into at least two partial buses, the at least two partial buses corresponding to the first memory device and the second memory device; and a data interface which independently inputs and outputs data between the outside source and each of the first memory device and the second memory device via said data bus according to a synchronization signal supplied from the outside source, wherein said command interface receives time-division multiplexed access commands in one cycle period of the synchronization signal, and said memory device further comprises a demultiplexer configured to demultiplex the time-division multiplexed access commands received by said command interface, and to allocate each of the access commands to a corresponding one of the first memory device and the second memory device.