Patent ID: 7173308

Claim:
A lateral short-channel DMOS, comprising: an epitaxial layer formed on a surface of a semiconductor substrate; a first conductivity-type well formed in a surface of the epitaxial layer; a second conductivity-type well that is formed in a surface of the first conductivity-type well and includes a channel forming region, the second conductivity type being an inverse of the first conductivity type; a first conductivity-type source region that is formed in a surface of the second conductivity-type well; a first conductivity-type ON resistance lowering well that is formed in a surface of the epitaxial layer so as to contact the first conductivity-type well and to not contact the second conductivity-type well, and includes a higher concentration of a first conductivity-type dopant than the first conductivity-type well; a first conductivity-type drain region formed in a surface of the first conductivity-type ON resistance lowering well; a gate electrode formed, via a gate insulating film, in an upper part of at least the channel forming region, out of a region from the first conductivity-type source region to the first conductivity-type drain region; and a gate resistance lowering metal layer connected to the gate electrode; wherein a second conductivity-type diffused region is formed in a floating state in a surface of the first conductivity-type well in a region between the second conductivity-type well and the first conductivity-type drain region so as to not contact the second conductivity-type well; and the second conductivity-type diffused region is formed so as to not contact the first conductivity-type ON resistance lowering well.