Patent ID: 7430578

Claim:
A method for processing digital video, image or audio signal data elements, the method comprising: decoding a plurality of instructions including a multiply-add instruction of a variable length instruction format comprising a first and a second opcode field, an addressing mode field, a first source field to indicate a first operand, the first operand having a first plurality of byte data elements including at least A 1 , A 2 , A 3 , and A 4 byte data elements, and second source field to indicate second operand having a second plurality of byte data elements including at least B 1 , B 2 , B 3 , and B 4 byte data elements; determining a length of the multiply-add instruction from said first opcode field, said addressing mode field, and optionally from said first source field, said second source field and an optional base field; and responsive to said second opcode field, enabling an execution unit with the decoded multiply-add instruction to perform the operation (A 1 ×B 1 )+(A 2 ×B 2 ) to generate a first 16-bit data element of a packed result data, and to perform the operation (A 3 ×B 3 )+(A 4 ×B 4 ) to generate a second 16-bit data element of the packed result data.