Patent ID: 7821284

Claim:
A semiconductor test head apparatus using a field programmable gate array (FPGA), comprising: an algorithm pattern generator (ALPG) chip for generating a predetermined memory test pattern; a field programmable gate array (FPGA) chip comprising a first transceiver which performs a driver function capable of recording a memory test pattern generated from the ALPG chip in a device under test (DUT), and performs a first comparator function capable of comparing a level of a signal read by the DUT with a predetermined high-level reference value, and a second transceiver which performs the driver function, and performs a second comparator function capable of comparing a level of a signal read by the DUT with a predetermined low-level reference value; a connection circuit for electrically connecting the first transceiver in parallel to the second transceiver, and connecting the first transceiver and the second transceiver to the DUT; and a test controller for controlling the ALPG chip such that the FPGA chip selectively performs the driver and comparator functions.