Patent ID: 8536643

Claim:
A semiconductor device comprising: a MISFET formed in a chip region of a semiconductor substrate and having a gate comprised of a first conductor, a source, and a drain; a gate electrode formed over said gate and electrically connected with said gate, said gate electrode being comprised of a second conductor having a resistivity lower than said first conductor; a source electrode formed over said source and electrically connected with said source, said source electrode being comprised of said second conductor; a drain electrode formed over said drain and electrically connected with said drain; a gate bump electrode formed over said gate electrode; a plurality of source bump electrodes formed over said source electrode; a gate lead formed over said gate bump electrode and electrically connected with said gate bump electrode; a plurality of source leads formed over said plurality of source bump electrodes and electrically connected with said source bump electrodes; a drain lead formed over said drain electrode and electrically connected with said drain electrode; and a resin body sealing said semiconductor substrate, wherein said gate electrode and said source electrode are formed in a same layer, wherein said source electrode has a plurality of regions, and wherein said gate electrode has a gate finger portion which is located between two of said plurality of regions of said source electrode.