Patent ID: 7505359

Claim:
A memory device that is operable in a first operating state and a second operating state, with read access to memory cells of the memory device being facilitated in the first operating state, the memory device comprising: an activatable clock generator circuit configured to generate a clock signal in an activated state and to suppress generation of the clock signal in a deactivated state; an activation circuit to switch the activatable clock generator circuit between the activated and deactivated states; an output unit configured to output data stored in the memory cells of the memory device, wherein stored data are output by the output unit in sync with the clock signal; and a control connection configured to apply a first state or a second state of a control signal, wherein the memory device is operable in the first operating state when the control connection applies the control signal in the first state, and the memory device is operable in the second operating state when the control connection applies the control signal in the second state; wherein the activation circuit is configured to switch the activatable clock generator circuit between activated and deactivated states such that the activatable clock generator circuit operates in the activated state during a time period that is after the memory device has changed from the first operating state to the second operating state, and such that the activatable clock generator circuit is changed from the activated state to the deactivated state after the time period has elapsed, and the activation circuit comprises a counter circuit with a counter reading, the activation circuit being configured to alter the counter reading from a first counter reading until the counter reading has reached a second counter reading after the control connection applies the control signal in the second state, and the activation circuit further being configured to switch the activatable clock generator circuit to the deactivated state when the counter reading of the counter circuit has reached the second counter reading.