Patent ID: 7974114

Claim:
A memory cell arrangement, comprising: a first memory cell and a second memory cell; a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell; a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line, wherein the first source/drain line is a first bit line; wherein the second source/drain line is a first source line; wherein the third source/drain line is a second bit line; and wherein the fourth source/drain line is a second source line.