Patent ID: 8736308

Claim:
An apparatus comprising: a plurality of source storage elements; a plurality of destination storage elements; a plurality of power-gated gates coupled between the source storage elements and supplying the destination storage elements; one or more power gates coupled in series between a power supply node and the power-gated gates, the power gates to reduce current flow through the power-gated gates in response to a control signal being deasserted indicating a sleep state and to allow current flow through the power-gated gates in response to the control signal being asserted to indicate a wake state; and control logic coupled to receive one or more source clock enable signals that enable clocking one or more of the source storage elements, and to receive at least one destination clock enable signal, the control logic configured to cause the control signal to indicate the wake state in response to assertion of any of the source clock enable signals, and wherein the control logic is further configured to cause the control signal to indicate the sleep state only after all of the one or more source clock enable signals are deasserted and the destination clock enable signal has been asserted thereby allowing the destination storage elements to be clocked to consume values supplied by the power-gated gates.