Patent ID: 7953916

Claim:
A computing platform comprising: a central processing hub (CPH) with one or more processors, wherein each processor includes a local advanced programmable interrupt controller (APIC) and a local interrupt descriptor table; an input output hub (IOH) communicatively coupled to the CPH, the IOH including a plurality general purpose input/output (GPIO) pins and an emulated input/output APIC, wherein the GPIO pins are to be coupled to at least one peripheral device, each peripheral device to communicate with the IOH via a serial peripheral interface (SPI) bus; and a kernel to execute on at least one of the one or more processors, the kernel configured to include a common GPIO driver serving as interrupt request routing agent, wherein the kernel is further configured to dynamically define interrupt routing information and interrupt descriptor tables for each of the one or more processors based on results of a call back function of discovered GPIO device drivers, and wherein the common GPIO driver is configured to retrigger interrupts received from a requesting device, at run time, as inter-processor interrupts, based on the interrupt descriptor table and identifier of the requesting device, wherein the computing platform is a mobile Internet device having an architecture without PCI pins for interrupt request signals.