Patent ID: 7631165

Claim:
An array processor, comprising: processing elements (PEs) PE i,j , where i and j refer to the respective row and column PE positions within a conventional torus-connected array, and where i=0,1,2, . . . N−1 and j=0,1,2, . . . N−1, said PEs arranged in clusters, wherein PE ij is arranged in a cluster with PE (i+a)(Mod N), (j+N−a)(Mod N) , for any i,j and for all a ∈{0,1, . . . ,N−1}, wherein each cluster contains a PE i,j and a PE j,i (K)and cluster switches connected to multiplex inter-PE communication paths between said clusters thereby providing inter-PE connectivity between clusters equivalent to that of a torus connected array, wherein the cluster switches are controlled by PEs within the PE clusters to enable selected inter-PE communication paths.