Patent ID: 7821110

Claim:
A circuit structure comprising: at least one substrate comprising at least one integrated circuit; a plurality of back end of line (BEOL) layers disposed over the at least one substrate, a first BEOL layer of the plurality of BEOL layers comprising a first conductive pattern defined therein by a first plurality of separate conductive elements arrayed in a first direction and a second direction throughout at least a portion thereof, the conductive elements of the first plurality of separate conductive elements being electrically isolated from each other within the first BEOL layer, and a second BEOL layer of the plurality of BEOL layers comprises a second conductive pattern defined therein by a second plurality of separate conductive elements arrayed in the first direction and the second direction throughout at least a portion thereof, the conductive elements of the second plurality of separate conductive elements being electrically isolated from each other within the second BEOL layer, and the second BEOL layer being disposed between the first BEOL layer and the at least one substrate, and wherein the first conductive pattern is configured to polarize electromagnetic interference in one of the first direction or the second direction, and the second conductive pattern is configured to block polarized electromagnetic interference in the other of the first direction or second direction from passing therethrough, and wherein the first BEOL layer and second BEOL layer cooperate to block external electromagnetic interference of a particular wavelength in any direction from passing therethrough to the at least one substrate; and wherein the first BEOL layer is a first BEOL dielectric laver, the first conductive pattern being a first conductive chemical-mechanical polishing (CMP) fill pattern configured in part relative to the size of the first BEOL dielectric layer to satisfy a predefined chemical-mechanical polishing ratio for the first BEOL dielectric layer, the predefined chemical-mechanical polishing ratio for the first BEOL dielectric layer being a predefined area-occupation ratio of dielectric material of the first BEOL dielectric layer to conductive material of the first conductive CMP fill pattern, and the second BEOL layer is a second BEOL dielectric layer, the second conductive pattern being a second conductive CMP fill pattern configured in part relative to the size of the second BEOL dielectric layer to satisfy a predefined chemical-mechanical polishing ratio for the second BEOL dielectric layer, the predefined chemical-mechanical polishing ratio for the second BEOL dielectric layer being a predefined area-occupation ratio of dielectric material of the second BEOL dielectric layer to conductive material of the second conductive CMP fill pattern.