Patent ID: 7372932

Claim:
A locking-status judging circuit for a digital PLL circuit, judging whether or not the digital PLL circuit locks on an input signal, comprising: a comparator for comparing a phase error signal outputted from the digital PLL circuit with a reference signal to be utilized for judging whether or not the digital PLL circuit locks on an input signal, and for outputting a signal “0 (zero)” in case the reference signal is larger than the phase error signal or a signal “1 (one)” in case the reference signal is smaller than the phase error signal; a selector section for outputting a positive number in case the signal “0” is inputted or a negative number in case the signal “1” is inputted; a limiter section for limiting an accumulated positive or negative number to be within a range of a prescribed upper limit and a prescribed lower limit; a feedback section for returning the accumulated positive or negative number within the range of the prescribed upper limit and the prescribed lower limit; an accumulator for adding the accumulated positive or negative number, returned from the feedback section, and either the positive number or the negative number, outputted from the selector section, and for outputting a newly accumulated number obtained by adding the accumulated positive or negative number and either the positive number or the negative number; and a lock-state judging section for judging the digital PLL circuit as a lock-state in case an accumulated value of the newly accumulated number is positive, or as an unlock-state in case the accumulated value of the newly accumulated number is negative.