Patent ID: 7068567

Claim:
A data output controller of a semiconductor device, the data output controller comprising: a delay unit for delaying an external clock signal; a delay line for delaying an output signal of the delay unit; a phase detector for detecting a differential phase between the external clock signal and an output signal of the delay line; a clock counter/delay line control unit for outputting a counter signal capable of controlling a time delay of the delay line in response to an output signal of the phase detector; a timing decoder/register for checking frequency of the external clock signal in response to an output signal of the clock counter/delay line control unit and storing information related to the frequency; and a multiplexer for receiving a plurality of output enable control signals, wherein the multiplexer selects one of output enable control signals according to the frequency information of the external clock signal which is checked by the timing decoder/register, and the output enable control signals include CAS latency of the semiconductor memory device and control an operation of an output driver of the semiconductor memory device.