Patent ID: 7478300

Claim:
A method for testing logic associated with an asynchronous clock boundary in an integrated circuit device, comprising: inputting test pattern data into a first set of latches associated with a first clock domain of the asynchronous clock boundary of the integrated circuit device; running functional boundary logic, associated with the asynchronous clock boundary of the integrated circuit device, in a functional mode of operation to move the test pattern data to a second set of latches associated with a second clock domain of the asynchronous clock boundary of the integrated circuit device; obtaining results data from the second set of latches; verifying an operation of the functional boundary logic based on the results data obtained from the second set of latches; and performing at least one of a logic built-in-self-test (LBIST) or an On-Product Multiple Input Signature Register (OPMISR) test to test the logic of the integrated circuit device for inputting the test pattern data into the first set of latches, wherein: running functional boundary logic of the integrated circuit device in a functional mode of operation comprises running functional boundary logic present in the first clock domain using a first clock native to the first clock domain, and running functional boundary logic present in the second clock domain using a second clock, different from the first clock, and which is native to the second clock domain, inputting the test pattern data into the first set of latches comprises scanning-in the test pattern data into the first set of latches, and wherein scanning-in of data across the asynchronous clock boundary is prohibited during the inputting, running, obtaining, and verifying operations, logic of the integrated circuit device that is not part of the functional boundary logic is held during the running of the functional boundary logic, obtaining of the results data, and verifying the operation of the functional boundary logic, and verifying the operation of the functional boundary logic comprises: comparing the results data obtained from the second set of latches with expected results data; and indicating that the functional boundary logic is operating properly if the results data matches the expected results data.