Patent ID: 8223579

Claim:
A semiconductor storage device comprising a memory cell, wherein the memory cell comprises: a first drive transistor; a second drive transistor; a first load transistor connected to the first drive transistor in series; a second load transistor connected to the second drive transistor in series; a first write-only transfer transistor whose drain is connected to a gate of the second drive transistor, a gate of the second load transistor, a drain of the first drive transistor, and a drain of the first load transistor; a second write-only transfer transistor whose drain is connected to a drain of the second drive transistor, a drain of the second load transistor, a gate of the first drive transistor, and a gate of the first load transistor; a first read-only drive transistor whose gate is connected to the gate of the first drive transistor, the gate of the first load transistor, the drain of the second drive transistor, and the drain of the second load transistor; a first read-only transfer transistor whose drain is connected to a drain of the first read-only drive transistor; a first column selection transistor whose drain is connected to a source of the first write-only transfer transistor; a second column selection transistor whose drain is connected to a source of the second write-only transfer transistor; a word line connected to a gate of the first write-only transfer transistor, a gate of the second write-only transfer transistor, and a gate of the first read-only transfer transistor; a first write bit line connected to a source of the first column selection transistor; a second write bit line connected to a source of the second column selection transistor; a first read bit line connected to a source of the first read-only transfer transistor; and a column selection line connected to a gate of the first column selection transistor and a gate of the second column selection transistor.