Patent ID: 7414431

Claim:
A dedicated logic cell in a dedicated logic function (LD) structure, comprising: a first multiplexer having a first input for receiving a first operation, a second input for receiving a second operation, a select input line and an output, the select input line driven by a dedicated line; and a second multiplexer having one or more inputs for receiving one or more operations, a first select input line, a second select input line, and an output coupled to the first input of the first multiplexer, the first and second select input lines of the second multiplexer driven by the one or more dedicated lines; a third multiplexer having one or more inputs for receiving one or more operations, a first select input line, a second select input line, and an output coupled to the second input of the first multiplexer, the first and second select input lines of the third multiplexer driven by one or more dedicated lines; and a first select signal generated to the select input line in the first multiplexer, a second select signal generated to the first select input line in the second multiplexer and the first select input line in the third multiplexer, and a third select signal generated to the second input line in the second multiplexer and the second select input line in the third multiplexer, wherein the first, second, third select signals are set during configuration.