Patent ID: 7042763

Claim:
A method of selectively programming first and second memory cells each of which includes a plurality of P-channel insulated gate field effect transistors (P-IGFETs), each having a gate, a drain, a source and an N-well, wherein each one of the first and second memory cells includes a control P-IGFET with a control electrode connecting its drain, source and N-well, a write P-IGFET with a write electrode connecting its source and N-well, a read P-IGFET with a read electrode connecting its source and N-well, an erase P-IGFET with an erase electrode connecting its drain, source and N-well, and a shared electrode connecting the control, write, read and erase P-IGFET gates, the method comprising: applying a substantially fixed reference voltage to said control electrodes, said write P-IGFET drains, said write electrodes, said read P-IGFET drains, said read electrodes and said erase electrodes of said first and second memory cells; applying to at least said write P-IGFET drains, said write electrodes, said read P-IGFET drains, said read electrodes and said erase electrodes of said first and second memory cells a first substantially fixed programming voltage which is more positive than said reference voltage; applying to said control electrodes of said first and second memory cells a second substantially fixed programming voltage which is more positive than said first substantially fixed programming voltage; re-applying said substantially fixed reference voltage to said write P-IGFET drain of said first memory cell while continuing said applying of said first substantially fixed programming voltage to said write P-IGFET drain of said second memory cell; re-applying said first substantially fixed programming voltage to said write P-IGFET drain of said first memory cell; re-applying said substantially fixed reference voltage to said control electrodes of said first and second memory cells; and re-applying said substantially fixed reference voltage to said write P-IGFET drains, said write electrodes, said read P-IGFET drains, said read electrodes and said erase electrodes of said first and second memory cells.