Patent ID: 8518821

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming a first interconnect over a main surface of a semiconductor substrate; (b) forming a first interlayer insulating film over the first interconnect; (c) forming a first via hole in the first interlayer insulating film for connecting to the first interconnect; (d) forming a first interconnect trench in the first interlayer insulating film in a region including a region in which the first via hole has been formed; (e) filling a metal film in the first interconnect trench and the first via hole so as to form a second interconnect; (f) forming a third interconnect over the second interconnect and the first interlayer insulating film; (g) forming a second interlayer insulating film over the third interconnect; (h) forming a second via hole in the second interlayer insulating film for connecting to the third interconnect; (i) forming a second interconnect trench in the second interlayer insulating film in a region including a region in which the second via hole has been formed; and (j) filling a metal film in the second interconnect trench and the second via hole so as to form a fourth interconnect, wherein the second interlayer insulating film is thicker than the first interlayer insulating film, step (g) includes forming a first etching stopper film in the second interlayer insulating film, a bottom of the second interconnect trench is arranged near the first etching stopper film, in the step (i), the second interconnect trench is formed by using the first etching stopper film as an etching stopper, in the step (d), the first interconnect trench is formed without using an etching stopper, a depth of the second interconnect trench is greater than a depth of the first interconnect trench, a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film, a diameter of the second via hole is greater than a diameter of the first via hole, in step (b), the first interlayer insulating film is formed so as to include a first barrier insulating film in contact with a surface of the first interconnect so as to prevent diffusion of copper, in step (g), the second interlayer insulating film is formed so as to include a second barrier insulating film in contact with a surface of the third interconnect so as to prevent diffusion of copper, the first and second barrier insulating films are made of a first material including silicon, carbon, and nitrogen, the first etching stopper film is made of a second material including silicon and nitrogen, the first material is different from the second material, and the first, second, third, and fourth interconnects have copper as a main component.