Patent ID: 8649428

Claim:
Decoding logic comprising: a convolutional decoder arranged to receive an encoded data signal and perform convolutional decoding on the encoded data signal to produce a decoded data signal; a descrambler for descrambling decoded data packets according to a descrambling sequence; and header bit prediction logic arranged to determine whether the decoded digital signal comprises an inverted synchronization byte, and in response thereto: predict a value for at least one header bit within the decoded data signal based on statistical analysis of header bit information of previously received encoded data signals; provide the predicted value for the at least one header bit to the convolutional decoder to be applied during initial convolutional decoding of the encoded data signal; predict a value for a second header bit based on statistical analysis of header bit information of previously received encoded data signals; and provide the predicted value for the second header bit to the convolutional decoder to be applied during convolutional decoding, the statistical analysis restricted to statistical analysis of values for headers bits within the header bit information for which no errors are detected.