Patent ID: 7890831

Claim:
A system for testing a processor, the system comprising: a gold processor socket configured to receive a gold processor; a test processor socket configured to receive a test processor, wherein the test processor is a device under test (DUT); a first memory coupled to the gold processor socket via a first memory bus; a second memory coupled to the test processor socket, via a second memory bus, wherein the first and second memories are independent of one another; a memory bus comparator coupled to the first memory bus and the second memory bus, wherein the memory bus comparator is configured to, when the gold and test processors are present and operating in their respective sockets, compare memory signals generated by the gold processor to memory signals generated by the test processor and to provide a first indication if a memory bus comparison results in a mismatch; a peripheral bus comparator coupled to the gold processor and the test processor socket, wherein the peripheral bus comparator is configured to, when the gold and test processors are present in their respective sockets, compare downstream transactions generated by the gold processor to downstream transactions generated by the test processor and to provide a second indication if a peripheral bus comparison results in a mismatch.