Patent ID: 8707234

Claim:
A method comprising: selecting a cell from one or more cells in a given collection of standardized cells, wherein each of the one or more cells represents one or more functional circuit design blocks usable as part of a design of an integrated circuit; one of generating and selecting a noise signal; applying the noise signal to an input node of the selected cell; identifying noise threshold data using a noise analysis module, for a given set of process, voltage and temperature variations, for an output node of the selected cell based on the noise signal applied to the input node of the selected cell, wherein the noise analysis module performs the noise threshold data identification at an analysis level higher than that of a transistor-level and device-level circuit simulation; and storing the noise threshold data with the selected cell as part of the given collection of standardized cells such that the noise threshold data is subsequently usable during a post layout noise analysis operation of an integrated circuit design that includes the selected cell; wherein one or more of the above steps are performed via a processing device.