Patent ID: 7185184

Claim:
Processor system, with a processor unit for executing instructions filed in a program memory, whereby the processor unit comprises instruction read out means for reading out an instruction from the program memory, instruction decoding means for decoding the instruction, and instruction executing means for executing the instruction, whereby the instruction executing means comprise a plurality of executing units for parallel execution of various instructions, and the instruction read out means and the instruction decoding means are jointly provided for all executing units, whereby a first executing unit of the plurality of executing units is connected to a first databus, the first executing unit being configured to execute all instructions of a set of instructions of the processor system, while a second executing unit of the plurality of executing units is connected to a second databus, the second executing unit being configured to execute only a few special instructions of the instruction set of the processor system, the first databus having a lower transmission rate than the second databus, and whereby the processor unit includes a path leading to the first executing unit that is temporarily deactivated by the instruction read out means via the instructions decoding means, if momentarily no instruction has to be executed by the first executing unit.