Patent ID: 8447920

Claim:
A storage system comprising: a non-volatile solid-state memory array, the memory array comprising units of memory accessible via one or more data channels; and a controller in communication with the memory array via the one or more data channels, the controller configured to: maintain an assignment table comprising information related to a memory access configuration that: groups a plurality of physical addresses in the memory array into a plurality of logical groups with the physical addresses for each logical group organized in a sequence, and associates a physical address number to each physical address, the physical address number corresponding to the position of the physical address in the sequence, wherein the physical addresses in each logical group are distributed across the units of memory accessible via the one or more data channels to maximize concurrent access to the memory array; receive a memory command from a host system for execution in the memory array, the memory command associated with one or more logical addresses; determine one or more physical addresses for the memory command by using the assignment table; and execute the memory command in accordance with the one or more determined physical addresses, wherein physical address numbers for each of the plurality of logical groups are assigned to physical addresses that are accessible via different data channels on a rotating basis.