Patent ID: 8175215

Claim:
A shift register comprising: a plurality of cascade-connected stages, each stage for generating an output signal at an output end based on a clock signal, a first control signal, each stage comprising: a pull-up module coupled to a first node, for providing the output signal at the output end based on the clock signal; a pull-up driving module coupled to the first node, for turning on the pull-up module in response to the first control signal; a first pull-down module coupled to the first node and a first supply voltage, for adjusting voltage level on the first node to the first supply voltage in response to a second control signal; a second pull-down module coupled to the output end and a second supply voltage, for adjusting voltage level on the output end to the second supply voltage in response to the second control signal, the voltage level of the first supply voltage being less than that of the second supply voltage; and a third pull-down module coupled to a second node and a third supply voltage, for adjusting voltage level on the second node to the third supply voltage in response to a third control signal, the voltage level of the third supply voltage being less than that of the first supply voltage.