Patent ID: 7462532

Claim:
A method of fabricating a high voltage metal oxide semiconductor (MOS) device, comprising the steps of: providing a substrate; forming a buried N-doped region in the substrate; forming an N-type epitaxial layer on the substrate; forming an isolation structure in the N-type epitaxial layer; forming a first well of N-type in the N-type epitaxial layer on that side close to the isolation structure such that the first N-type well is connected to the buried N-doped region, forming a gate dielectric layer on the N-type epitaxial layer; forming a gate on the gate dielectric layer and a portion of the isolation structure on that side of the isolation structure away from the first well of N-type; forming a P-type well under a portion of the gate and in the N-type epitaxial layer on that side of the gate away from the isolation structure; and forming an N-type drain region in the N-type epitaxial layer on that side of the gate close to the isolation structure and forming an N-type source region in the P-type well, and the first well of N-type and the N-type drain region have some overlapping area.