Patent ID: 8140832

Claim:
A computer-implemented method of selectively forcing a hardware pipeline to single step execution of software instructions in a process packet, the method comprising: a host central processing unit (CPU) appending a “single step” packet to a process packet to form a merged packet, wherein the host CPU is coupled to a Network On A Chip (NOC), wherein the NOC comprises multiple processing hardware nodes that communicate via routers, and wherein the merged packet comprises data, instructions, and a header that contains routing information for the merged packet; the host CPU dispatching the process packet to a first processor core on the NOC, wherein the process packet is executed in a preselected hardware thread that is located within the first processor core, wherein the “single step” packet causes the preselected hardware thread to single step an execution of software instructions in the process packet, and wherein the preselected hardware thread comprises a register, an execution unit, and an output buffer; the host CPU freezing other hardware threads within the NOC until the merged packet finishes single-stepping execution; and in response to the “single-step” packet being unappended from the merged packet and returned to the host CPU, unfreezing the other hardware threads within the NOC.