Patent ID: 8615688

Claim:
A memory system comprising: an array of memory cells, wherein a plurality of memory cells in the array of memory cells are redundant to other memory cells in the array of memory cells; and a repair module configured to iteratively test the array of memory cells, wherein during the iterative testing of the array of memory cells, the repair module is configured to, during each test of the array of memory cells, (i) identify one or more defective memory cells in the array of memory cells, if any, and (ii) in response to one or more defective memory cells being identified during the test, respectively replace the one or more defective memory cells with one or more of the plurality of memory cells that are redundant to other memory cells in the array of memory cells, wherein the repair module is configured to during a first iteration of the iterative testing of the array of memory cells and as a first attempt to repair a first defective memory cell, replace the first defective memory cell with a first redundant memory cell in the array of memory cells, and during a second iteration of the iterative testing of the array of memory cells, replace the first redundant memory cell with a second redundant memory cell as a second attempt to repair the first defective memory cell.