Patent ID: 7504336

Claim:
A method for forming a semiconductor device comprising: forming at least one field effect transistor (FET) comprising a source region and a drain region; forming a metal layer over the source and drain regions of the at least one FET, wherein the metal layer comprises a silicide metal M capable of reacting with silicon to form an intrinsically stressed metal silicide; conducting a first annealing step to form source and drain metal silicide layers respectively in the source and drain regions of the at least one FET, wherein the source and drain metal silicide layers comprise a metal silicide of a first phase (MSi x ); forming a silicon nitride layer over the at least one FET; conducting a second annealing step to convert the metal silicide from the first phase (MSi x ) into a second phase (MSi y ), wherein x<y, and wherein the metal suicide phase conversion generates intrinsic tensile or compressive stress in the source and drain metal silicide layers of the at least one FET; and removing the deposited silicon nitride layer from the at least one FET, followed by deposition of an interlevel dielectric layer and formation of source, drain, and gate contacts.