Patent ID: 8099638

Claim:
An integrated circuit comprising: memory test logic comprising: at least one programmable virtual memory client that includes: programmable control logic configured to generate a plurality of bursts, each burst including at least one data pattern sequence generated from a plurality of stored data patterns; virtual memory client control logic configured to: use the generated bursts to at least one of read from and write to at least one memory device; based on mismatch information generated based on the bursts, generate controlled programming information that causes changing of parameters of a memory interface that comprises a plurality of pads on the integrated circuit; issue the controlled programming information to the memory interface; based on the controlled programming information, automatically tune the memory interface by automatically adjusting a write and/or read delay of at least one of the pads and by automatically updating a signal strength level of at least one of the plurality of pads; wherein the virtual memory client control logic tunes write data and accompanying strobe delays by adjusting the write delay of at least one of the pads and updating a signal strength level having at least one of a plurality of pads used to write the data; and wherein the virtual memory client control logic is further operative to: cycle through a plurality of write and/or read data and strobe delay settings to determine a desired setting for the tuning process; and repeat the tuning process until no data mismatches are determined.