Patent ID: 8773163

Claim:
An integrated circuit comprising an I/O portion, the I/O portion comprising: a plurality of I/O buffers forming a first bank of I/O buffers; a plurality of I/O buffers forming a second bank of I/O buffers; a plurality of I/O pads forming a first bank of I/O pads coupled to I/O buffers of the first bank of I/O buffers such that each I/O pad of the first bank of I/O pads is coupled to at least one I/O buffer of the first bank of I/O buffers; a plurality of I/O pads forming a bank of I/O pads coupled to I/O buffers of the second bank of I/O buffers such that each I/O pad of the second bank of I/O pads is coupled to at least one I/O buffer of the second bank of I/O buffers; and customization circuitry configured in accordance with one of a plurality of different configurations for customizing the I/O pads of the first bank of I/O pads and I/O pads of the second bank of I/O pads such that: each I/O pad of the first and second bank of I/O pads is defined as either a signal pad or a fixed voltage pad; each signal pad in the first bank of I/O pads is supplied power in accordance with power supply requirements of one or more I/O standards of the first bank of I/O pads; each signal pad in the second bank of I/O pads is supplied power in accordance with different power supply requirements of one or more different I/O standards different than the one or more I/O standards of the first bank of I/O pads; wherein, in accordance with different configurations of the customization circuitry, different numbers of I/O pads are defined as belonging to the first bank of I/O pads and the second bank of I/O pads.