Patent ID: 7530062

Claim:
In a computer, a method of optimizing shader code compiled from a high level shader language, the method comprising: for at least a subset of instructions of the shader, calculating a metric indicative of whether an instruction reduces a count of active vector registers utilized by the shader; and re-ordering the instructions by moving ahead instructions whose calculated metric indicates would reduce the active vector register count of the shader subject to the instructions'interdependencies; whereby the vector register load of the shader is lessened; and wherein calculating the metric indicative of whether an instruction reduces a count of active vector registers comprises: identifying a subgraph of instructions in the shader encompassing the instruction and any ancestor instructions on which the instruction depends; determining a number of reads made from within the subgraph; determining a number of values produced within the subgraph and read from outside the subgraph; determining a number of instructions in the subgraph; and calculating the metric as a function of the number of reads from within the sub graph, the number of reads from outside the sub graph and number of instructions in the subgraph.