Patent ID: 8848447

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having electrically rewritable nonvolatile memory cells arranged therein; and a control unit configured to perform control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected one of the memory cells for data write, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage by an amount of a step-up voltage if data write is not completed, the control unit being configured to, during the write operation, raise a first write pulse voltage with a first gradient, and then raise a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient, wherein the control unit is configured to perform voltage control such that a relation of Wp/3≦t is satisfied, where Wp is a pulse width of the first write pulse voltage, and t is a width of a portion of a rise curve of the first write pulse voltage until the first write pulse voltage reaches a value.