Patent ID: 7633103

Claim:
A method of fabricating a semiconductor device, comprising: providing a substrate comprising a layer of semiconductor material; forming an inactive region in the substrate to define an active region in a first portion of the substrate; forming a gate electrode structure having a portion overlying the active region, the gate electrode structure comprising: a common portion; a plurality of gate electrode finger portions integral with the common portion; and a plurality of fillet portions integral with the common portion and the gate electrode finger portions, wherein the fillet portions do not overlie the active region; depositing a compressive stress layer overlying the active region; and removing a portion of the compressive stress layer overlying the inactive region to leave a remaining portion of the compressive stress layer overlaying the active region; depositing a tensile stress layer overlying a remaining portions of the compressive stress layer and overlying an exposed portion of the inactive region; and removing a portion of the tensile stress layer overlying at least a portion of the remaining portion of the compressive stress layer, wherein a remaining portion of the tensile stress layer is disposed outside the active region and is spaced apart from the active region and overlies a portion of the compressive stress layer that does not overlap with the active region.