Patent ID: 7187616

Claim:
A MOS semiconductor integrated circuit device comprising: a prebuffer circuit connected to receive a signal produced within the semiconductor integrated circuit device and including a first transistor of P-channel type and a second transistor of N-channel type each having a gate and a current path, the first and second transistors being connected at their gates to receive the signal, one end of the current paths of the first and second transistors being connected together to the output node of the prebuffer circuit, and the other end of the current path of the first transistor being connected to a first power supply node; a third transistor of N-channel type having a gate and a current path connected at its one end to the other end of the current path of the second transistor and at its other end to a second power supply node; a fourth transistor of P-channel type having a gate and a current path connected at its one end to the output node of the prebuffer circuit; a fifth transistor of N-channel type having a gate connected to receive the signal and a current path connected between the other end of the current path of the fourth transistor and one end of the current path of the third transistor; a last-stage buffer circuit connected to the output node of the prebuffer circuit and including a sixth transistor of P-channel type having a gate and a current path one end of which is connected to the output node of the last-stage buffer circuit and a seventh transistor of N-channel type having a gate and a current path connected between the output node of the last-stage buffer circuit and the second power supply node, the gate of the sixth transistor being connected to the output node of the prebuffer circuit and the gate of the seventh transistor being connected to the other end of the current path of the fourth transistor; an eighth transistor of P-channel type having a gate and a current path connected between the other end of the current path of the sixth transistor and the first power supply node; a ninth transistor of P-channel type having a gate and a current path connected between the first power supply node and the output node of the prebuffer circuit; and a control circuit which produces a plurality of control signals applied to the gates of the third, fourth, eighth and ninth transistors, in a standby state, the third, fourth and eighth transistors are turned off and the ninth transistor is turned on and, in an active state, the third, fourth and eighth transistors are turned on and the ninth transistor is turned off.