Patent ID: 8829922

Claim:
An apparatus for determining alternating current (AC) delay variation of a transistor device under test, comprising: a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test such that a gate-to-drain propagation delay, t gd , represents the time for a drain voltage on the drain terminal to transition between logic states after a gate voltage on the gate terminal transitions between logic states, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test such that a source-to-drain propagation delay, t sd , represents the time for the drain voltage to transition between logic stages after a source voltage on the source terminal transitions between logic states.