Patent ID: 8064206

Claim:
A semiconductor memory device, comprising: a wiring board including a first main surface having an element mounting portion, connection pads and a wiring layer, and a second main surface opposing the first main surface; a first semiconductor memory element mounted on the element mounting portion of the wiring board and having first electrode pads; a second semiconductor memory element stacked on the first semiconductor memory element and having second electrode pads; metal wires which electrically connect the connection pads of the wiring board and the first and second electrode pads of the first and second semiconductor memory elements; and a sealing resin layer formed on the first main surface of the wiring board to seal the first and second semiconductor memory elements together with the metal wires, wherein the first main surface of the wiring board has a convex portion on the wiring layer, and the first semiconductor memory element is adhered to the first main surface of the wiring board via an adhesive layer, and the first semiconductor memory element is disposed on the convex portion only via the adhesive layer, and wherein the first semiconductor memory element has a thickness greater than that of the second semiconductor memory element.