Patent ID: 7005670

Claim:
A thin film transistor array panel for a liquid crystal display, comprising: an insulating substrate; a gate line assembly of an aluminum-based conductive layer formed on the insulating substrate, the gate line assembly comprising gate lines, gate pads, and gate electrodes coupled with the gate lines; a gate insulating layer over the insulating substrate and the gate line assembly; a semiconductor layer on the gate insulating layer; ohmic contact layers formed on the semiconductor layer; data lines crossing over the gate lines, source electrodes coupled with the data lines, and drain electrodes separated from the source electrodes while interposing the gate electrodes; a protective layer having first contact holes over the drain electrodes; and pixel electrodes on the protective layer such that the pixel electrodes are coupled with the drain electrodes through the first contact holes, wherein boundaries of the source electrodes and the drain electrodes in a channel region between the source electrodes and the drain electrodes is on a line with boundaries of the ohmic contact layers in the channel region.