Patent ID: 8645580

Claim:
An integrated circuit comprising: a first configuration terminal; a second configuration terminal; and an auto addressing circuit coupled to the first and second configuration terminals, and responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal, the auto addressing circuit comprising: a comparator including a first input coupled to the first configuration terminal, a second input for receiving a reference voltage, and an output; a repeater including an input coupled to the first configuration terminal, a control input, and an output coupled to the second configuration terminal; and an address assignment circuit including an input coupled to the output of the comparator and a control output coupled to the control input of the repeater, the address assignment circuit configured to disable the repeater in response to receiving the data pattern and to activate the repeater after assigning the node address, wherein the integrated circuit is subsequently responsive to the node address when the node address is received.