Patent ID: 7309894

Claim:
A high voltage gate driver integrated circuit comprising: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift LDMOS transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region; wherein the LDMOS transistor comprises: second conductive type epitaxial layer formed on a first conductive type substrate; a first conductive type well region formed over the epitaxial layer; a second conductive type highly doped source region formed over the well region; a second conductive type highly doped drain region formed over the epitaxial layer to be separated in a certain distance in a lateral direction from the well region; a gate electrode formed on a channel formation region over the well region through a gate insulating layer; a source electrode electrically connected to the highly doped source region; and a drain electrode electrically connected to the highly doped drain region.