Patent ID: 7370262

Claim:
An apparatus generating error flags for a data frame including a plurality of ECC (Error-Correction Coding) data blocks, wherein each ECC data block is located between frame-sync data and BIS (Burst Indicator Subcode) data or between two of the BIS data, the BIS data comprising information that is inserted in order to indicate a generation of a burst error, the apparatus comprising: a frame-sync error memory which stores frame-sync error information for at least one of the ECC data blocks; a BIS error flag memory which stores a BIS error flag for the at least one ECC data block; and an error flag generator, which generates one of the error flaps indicating an error existence/absence for a corresponding one of the ECC data blocks with reference to the frame-sync error information stored in the frame-sync error memory and the BlS error flag stored in the BIS error flag memory, wherein the at least one ECC data block has an error correction format in which the frame-sync data is recorded in a heading of the at least one ECC data block and BIS data columns are recorded between sets of ECC data columns, and the error flag generator generates an error flag indicating an error existence for an entire ECC data constructing a set of ECC data columns with reference to error information stored in the frame-sync error memory and the BIS error flag memory, if both the frame-sync error information of the frame-sync data and the BIS error flag of one of the BIS data columns neighboring the set of the ECC data columns, or the BIS error flag of the BIS data columns neighboring the set of the ECC data columns, indicate the error existence.