Patent ID: 7993967

Claim:
A semiconductor package fabrication method, comprising the steps of: applying a sacrificial layer on a surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming a plurality of through holes at a plurality of predetermined areas of the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in the through holes; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on a predetermined position of the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and the conductive metallic layer, to allow the conductive metallic layer to protrude from the insulation layer.