Patent ID: 7525856

Claim:
A serial-interface flash memory device including: a data/address I/O pin; a clock input pin; a bidirectional buffer coupled to the a data/address I/O pin; a clock buffer coupled to the clock input pin; internal control logic; a serial interface logic coupled to the clock buffer, the bidirectional buffer, and the internal control logic, the serial interface logic including a data-direction control coupled to the bidirectional buffer; a read-voltage generator coupled to the internal control logic; a modify-voltage generator coupled to the internal control logic; a first switch coupled to the read-voltage generator and the clock buffer, the first switch having a control input; a second switch coupled to the modify-voltage generator and the clock buffer, the second switch having a control input; memory drivers coupled to the read-voltage generator through the first switch and to the modify-voltage generator through the second switch; a first register coupled between the serial interface logic and the control input of the first switch; a second register coupled between the serial interface logic and the control input of the second switch; a memory array coupled to the memory drivers; and read amplifiers and program buffers coupled between the serial interface logic and the memory drivers.