Patent ID: 8743628

Claim:
A line driver comprising: a voltage selection circuit configured to provide a line voltage from one of a first power control circuit and a second power control circuit to a line of a memory array according to a received gate voltage, said voltage selection circuit comprising: a first voltage selection transistor with a first source/drain coupled to said first power control circuit and a second source/drain coupled to said line; and a second voltage selection transistor with a first source/drain coupled to said line and a second source/drain coupled to said second power control circuit; and a gate voltage selection circuit configured to provide said gate voltage to a node of said voltage selection circuit, said gate voltage selection circuit comprising: a first gate voltage selection transistor with a first source/drain coupled to said first power control circuit and a second source/drain coupled to said node of said voltage selection circuit; and a second gate voltage selection transistor with a first source/drain coupled to said node of said voltage selection circuit and a second source/drain commonly coupled with said second source/drain of said second voltage selection transistor, wherein said first power control circuit provides different first and second pull-up voltages and said second power control circuit provides different first and second pull-down voltages, depending upon a state of the memory array.