Patent ID: 7259460

Claim:
A substrate panel assembly for use in the packaging of integrated circuits, comprising: a lead-frame panel including an array of micro-array device areas and a matrix of tie bars that support the device areas, each device area having a plurality of leads, each lead including elongated lead trace segments and a lead contact post, the lead contact posts being arranged in a micro-array, the lead contact posts being exposed at a bottom surface of the lead-frame panel, and the lead trace segments not being exposed at the bottom surface of the lead-frame, wherein the lead trace segments of at least some of the leads have portions extending between lead contact posts associated with adjacent leads and wherein at least some of the tie bars include lateral support ribs formed on the tie bars, each lateral support rib being positioned under an associated tie bar adjacent a lead trace segment, the lateral support ribs being exposed on the bottom surface of the lead frame panel and arranged and sized such that the lateral support ribs may be removed along with the tie bars during singulation processes; an adhesive tape adhered to the lower surface of the contact posts, wherein the adhesive tape does not contact the lead trace segments; a plurality of dice, each die being mounted on an associated device area; and a plurality of bonding wires that electrically connect the dice to at least some of the leads in an associated device area, wherein at least some of the bonding wires are bonded to lead trace segments that are associated with contacts posts that underlie an associated die; and wherein at least some of the leads are configured such that the bonding wires are securely wire bonded to portions of the lead trace segments that are not in contact with the adhesive tape or otherwise directly supported during a wire bonding operation.