Patent ID: 8014453

Claim:
An apparatus, comprising: at least one processor, configured to precode data using a codeword from a codebook consisting of exactly twelve code words, each codeword being based on a Binary Phase Shift Keying (BPSK) character set, the codewords being: 1 2 ⁡ [ 0 1 0 1 0 0 0 0 1 1 0 0 ] , 1 2 ⁡ [ 0 1 0 1 0 0 0 0 1 - 1 0 0 ] , 1 2 ⁡ [ 1 0 0 0 1 0 1 0 0 0 0 1 ] , 1 2 ⁡ [ 1 0 0 0 1 0 - 1 0 0 0 0 1 ] , 1 2 ⁡ [ 1 0 0 1 0 0 0 1 0 0 0 1 ] , ⁢ 1 2 ⁡ [ 1 0 0 - 1 0 0 0 1 0 0 0 1 ] , 1 2 ⁡ [ 0 1 0 0 0 1 1 0 0 1 0 0 ] , 1 2 ⁡ [ 0 1 0 0 0 1 1 0 0 - 1 0 0 ] , ⁢ 1 2 ⁡ [ 1 0 0 0 0 1 0 1 0 1 0 0 ] , 1 2 ⁡ [ 1 0 0 0 0 1 0 1 0 - 1 0 0 ] , 1 2 ⁡ [ 0 1 0 1 0 0 1 0 0 0 0 1 ] , and ⁢ ⁢ 1 2 ⁡ [ 0 1 0 1 0 0 - 1 0 0 0 0 1 ] . ⁢