Patent ID: 8307191

Claim:
A computer implemented method for handling page faults in a virtualized computer system in which at least one guest page table maps virtual addresses to guest physical addresses, some of which are backed by machine addresses, and wherein at least one shadow page table and at least one translation look-aside buffer map virtual addresses to corresponding machine addresses, the method comprising the steps of: maintaining indicators in entries of at least one shadow page table, wherein each indicator denotes a state of its associated entry from a group of states consisting of: a first state indicating that a mapping of a virtual address corresponding to the associated entry to a guest physical address is not present in the guest page table and a second state indicating that said mapping is present in the guest page table; processing hardware page faults by an enhanced virtualization layer; determining states of shadow page table entries corresponding to hardware page faults; responsive to a shadow page table entry corresponding to a hardware page fault being in the first state, delivering that page fault to a guest operating system for processing without activating a virtualization software component; responsive to a shadow page table entry corresponding to a hardware page fault being in the second state, delivering that page fault to the virtualization software component for processing; determining from an indicator of a shadow page table entry corresponding to a hardware page fault that a corresponding guest page table entry can be used to translate a guest virtual address to a guest physical address; and determining that the page fault is a hidden page fault.