Patent ID: 7986584

Claim:
A memory device having a memory core, the memory device comprising: a clock receiver circuit to receive an external clock signal; a first interface to receive a command that specifies a read operation to the memory device; a data interface, separate from the first interface, to transfer data between the memory device and an external set of signal lines; and a second interface, separate from the first interface and the data interface, the second interface to receive power mode information; the memory device having a plurality of power modes comprising: a first mode in which the clock receiver circuit is turned off, the first interface is turned off, and the data interface is turned off; a second mode in which the clock receiver is turned on, the first interface is turned off, and the data interface is turned off; and a third mode in which the clock receiver is turned on and the first interface is turned on, wherein in the third mode the data interface is turned on, when the first interface receives the command, to output data in response to the command.