Patent ID: 7039144

Claim:
A circuit for receiving input data with a delay variation, the input data including multiple units of data input to the circuit in a predetermined sequence, comprising: a write-enable pulse sequencer, in response to a reset signal and a clock signal, for sequentially generating a plurality of write-enable signals; an N-stage register including N stages of register, the N-stage register, in response to the plurality of write-enable signals, for sequentially storing each of multiple units of data within one corresponding stage of register, each of N stages of register having an output terminal outputting one corresponding unit of data; an output stage selector for generating a control signal, wherein the output stage comprises: an initial stage unit, responsive to the reset signal, for outputting a set signal and an initial stage number signal; and an output stage selector sequencer, responsive to the set signal, the clock signal and the initial stage number signal; and a multiplexer inputting each one corresponding unit of data from the N-stage register, the multiplexer, responsive to the control signal, for outputting each one corresponding unit of data according to said predetermined sequence.