Patent ID: 7716541

Claim:
A test apparatus that tests a device under test, comprising: a main memory that stores pattern data including at least one pattern bit defining a test signal provided to each of a plurality of terminals of the device under test; a pattern cache memory that caches the pattern data read from the main memory; a pattern generation control section that reads pattern data from the main memory and writes the same to the pattern cache memory; a pattern generating section that causes the pattern cache memory to sequentially read the pattern data stored in each cache entry of the pattern cache memory and to output the same; and a channel circuit that generates a test signal corresponding to each of the plurality of terminals based on the pattern data outputted from the pattern generating section and provides the test signal to the device under test, the pattern generation control section including: a replicating section that at least one pattern bit as pattern bits corresponding to two or more terminals to generate pattern data including pattern bits for the plurality of terminals; and a writing section that writes the pattern data including the pattern bits for the plurality of terminals to the pattern cache memory, wherein the writing section writes the pattern data read from the main memory to the pattern cache memory in a first operation mode in which the pattern data including the pattern bits for the plurality of terminals is stored in the main memory, and writes the pattern data generated by the replicating section to the pattern cache memory in a second operation mode in which the pattern data including the number of pattern bits less than the plurality of terminals is stored in the main memory.