Patent ID: 8694962

Claim:
A method for using one or more aspect-oriented parallelism primitives to implement one or more aspects of a program in parallel, comprising: partitioning the program into two or more threads corresponding to two or more aspects of the program; implementing each of the two or more threads on a separate processor core of a multi-core processor in parallel; and invoking one or more parallel aspect-oriented programming features for each of the two or more threads during implementation of each thread to leverage hardware support provided for implementation of the one or more parallel aspect-oriented programming features to facilitate interaction amongst the two or more threads implementing on the multi-core processor in parallel, wherein said hardware support comprises a set of hardware queues implemented between each thread-pair of a core and between each thread-pair of neighboring cores of the multi-core processor to support one or more logical streams that carry data corresponding to one or more viewpoints, wherein each hardware queue is accessible to a machine instruction set via at least one of a register identifier and a special memory address, and each hardware queue is specialized to be at least one of non-blocking and asynchronous, and wherein said parallel aspect-oriented programming features comprise: a language extension that enables a first thread to set a break-point on a second thread of a same program, wherein the second thread stops implementation when its break-point is reached in its control flow; a language extension that enables a first thread to set a watch-point on at least one of a register and a memory location of a second thread of a same program, wherein the second thread stops implementation at any point in time corresponding to when the value of the at least one of register or memory location of the second thread changes; and a language extension that inserts a viewpoint instruction in a thread of interest so as to send multiple sibling threads a stream over a logical queue containing all of one or more values taken on by at least one of a register and a memory location of the thread of interest, as specified in the view-point instruction without stopping the multiple sibling threads.