Patent ID: 8102960

Claim:
An apparatus comprising: an equalizer to receive an incoming digital signal based on an incoming analog signal from a transmission channel and to output an equalized digital signal, the equalizer to initiate adaptation to the transmission channel responsive to a first control signal; a slicer coupled to the equalizer to generate symbol decisions based at least in part on the equalized digital signal; a first logic coupled to receive the symbol decisions from the slicer, the first logic to generate a lock signal when the first logic has locked onto a training sequence of the symbol decisions; a second logic coupled to the first logic to receive the lock signal and to generate a first selection signal responsive thereto, wherein the second logic is to generate the first control signal after receipt of the lock signal and a phase settling delay, and generate a second selection signal to select an output of the slicer or an output of the first logic as a symbol source; a first phase detector to detect a first phase error of the equalized digital signal; a second phase detector to detect a second phase error of the incoming digital signal; and a clock generator to generate a clock signal responsive to the first phase error or the second phase error, wherein the clock generator is to receive the first or second phase error responsive to the first selection signal.