Patent ID: 8010927

Claim:
A machine-readable storage medium except for transitory propagated signals containing a design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event, wherein said design structure is readable in a machine in a design flow for designing an integrated circuit that contains said ESD protection circuit, said ESD protection circuit comprising: a BigFET stack electrically connected between a high-voltage pin and a low-voltage pin of the integrated circuit chip, said BigFET stack including a first BigFET and a second BigFET connected in series with, and downstream of, said first BigFET without being electrically connected to a diffusion contact between said first BigFET and said second BigFET, said first BigFET including a first gate and said second BigFET including a second gate; a driver electrically connected to each of said first and second gates and configured to drive said first and second gates during the ESD event; and a trigger for detecting the ESD event and triggering said driver to drive said first and second gates in response to the ESD event; wherein said second gate of said second BigFET is driven by a voltage and said driver includes gate pull-up feedback circuitry for controlling the magnitude of said voltage.