Patent ID: 7295100

Claim:
An apparatus comprising: a non-volatile memory containing a stored access code; a circuit comprising two processors wherein at least one of the processors is shielded from external access; a portion of the circuitry generating a wake-up signal in response to pressing a key on a keypad; at least one of the processors being woke-up in response to the wake-up signal and receiving an input code; at least one of the processors being woke-up and comparing the input code with the stored access code; at least one of the processor generating a signal to activate a lock actuator if the input code matches the stored access code; at least a portion of the circuitry comprising a low battery detection circuit that is enabled by one of the processors in an operation mode and disabled in a sleep mode, the low battery detection circuit measuring a voltage of a battery in the operation mode; and, wherein at least one of the processors enters a sleep mode wherein the processor operates at a lower power consumption rate than when the processor is awake.