Patent ID: 7453268

Claim:
An input power protected ratiometric output sensor circuit comprising: first and second power terminals; a ratiometric output sensor having a load impedance between a pair of sensor input terminals and an output terminal providing an output voltage ratiometric with an input voltage applied across the load impedance; a p-channel MOSFET having a source and a drain connected in series between the first power terminal and one of the pair of sensor input terminals of the ratiometric output sensor and further having a gate coupled to the second power terminal; an n-channel MOSFET having a source and a drain connected in series between the second power terminal and the other of the pair of sensor input terminals of the ratiometric output sensor and further having a gate coupled to the first power terminal, whereby connection of a DC voltage power supply across the first and second power terminals with a predetermined positive polarity of the first power terminal relative to the second power terminal renders both the p-channel MOSFET and the n-channel MOSFET conducting to power the ratiometric output sensor but connection of a DC voltage power supply with a polarity reversed relative to the predetermined polarity across the first and second power terminals renders one of the p-channel MOSFET and the n-channel MOSFET non-conducting, the one of the p-channel MOSFET and the n-channel MOSFET having its source and drain oriented with respect to the load impedance so that any internal source-drain bypass diode therein is not effective to conduct bypass current flow with connection of a DC voltage power supply with a polarity reversed relative to the predetermined polarity across the first and second power terminals; a third MOSFET having a source and a drain connected between the gate and source of the other of the p-channel MOSFET and the n-channel MOSFET and further having a gate; and a voltage sensing circuit having an output connected to the gate of the third MOSFET and being responsive to the voltage across the first and second power terminals to render the third MOSFET non-conducting and thus render the other of the p-channel MOSFET and the n-channel MOSFET conducting when the voltage across the first and second power terminals in the predetermined polarity is not greater than a predetermined value and alternatively to render the third MOSFET conducting and thus render the other of the p-channel MOSFET and the n-channel MOSFET non-conducting when the voltage across the first and second terminals in the predetermined polarity is greater than the predetermined value.