Patent ID: 7031198

Claim:
A non-volatile semiconductor memory device, comprising: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an access control circuit that regulates operations of the word line, the multiple bit lines, and the multiple control gate lines to control a writing operation of information; a buffer circuit that stores in advance multiple pieces of information; and a bit line actuation circuit that is driven to write the information stored in the buffer circuit via the multiple bit lines, the memory cell array being divided into m memory blocks in the row direction, where m is an integer of not less than 1, each of the memory blocks being divided into n column blocks in the row direction, where n is an integer of not less than 2, in the nonvolatile semiconductor memory device, in the case of collectively writing the information into the second non-volatile memory element of an (i)-th twin memory cell in the row direction in each of the column blocks, where i is an integer of not less than 1, the access control circuit, collectively setting a programming word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell in each of the column blocks, collectively setting a programming control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate in each of the column blocks, and collectively setting a programming bit line voltage, which is supplied from the bit line actuation circuit, to an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell in each of the column blocks.