Patent ID: 7859930

Claim:
An application specific integrated circuit (ASIC) device comprising: a DRAM that includes a plurality of cache registers, said DRAM embedded within the ASIC device and further including: a plurality of memory arrays including: word lines extending in a first direction, bit lines extending in a second direction orthogonal to the first direction, and charge storage cells formed at intersections of said word lines and said bit lines; a plurality of strips of bit line sense amplifiers electrically connected to said bit lines; a plurality of data bus lines extending in the second direction, said plurality of cache registers being electrically connected to receive data from said plurality of data bus lines; array select circuitry for applying first data from a selected one of said strips of sense amplifiers to said data bus lines; and a plurality of data bus read amplifiers electrically connected to said data bus lines and configured to facilitate transmission of said first data to outputs of said DRAM.