Patent ID: 8670284

Claim:
A semiconductor device comprising: a global bit line; a first local bit line to which normal memory cells are connected, the first local bit line corresponding to the global bit line; a first hierarchical switch controlling an electrical connection between the global bit line and the first local bit line; a second local bit line to which redundant memory cells replacing at least the normal memory cells are connected, the second local bit line corresponding to the global bit line; a second hierarchical switch controlling an electrical connection between the global bit line and the second local bit line; a precharge circuit precharging the global bit line to a predetermined voltage; a redundancy determination circuit determining whether or not an address specifying a memory cell to be accessed matches a defective address; and a control circuit controlling operations of the normal memory cells, the redundant memory cells, the precharge circuit and the redundancy determination circuit, wherein the control circuit performs an operation in a standby state, in which the precharge circuit and the second hierarchical switch are activated so that the global bit line and the second local bit line are precharged to the predetermined voltage, and the first hierarchical switch is inactivated so that the first local bit line is brought into a floating state, and the control circuit performs an active operation to access the normal memory cells, in which the first hierarchical switch is activated before receiving a determination result of the redundancy determination circuit so that the first local bit line is precharged to the predetermined voltage, subsequently when the determination result indicates that the addresses do not match each other, the first hierarchical switch is maintained active while the second hierarchical switch that has been active is inactivated and the precharge circuit is inactivated so as to access the normal memory cells, and when the determination result indicates that the addresses match each other, the first hierarchical switch that has been active is inactivated and the precharge circuit is inactivated so as to access the redundant memory cells.