Patent ID: 7433230

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array portion, wherein said memory array portion is formed of a plurality of sub-blocks, each sub block is formed of a plurality of word lines, a plurality of local bit lines which extend in the direction crossing the word lines, and a plurality of memory cells each storing information based on a level change of its threshold voltage and each placed so as to correspond to each intersection of a word line and a local bit line, said memory array portion further has a plurality of main bit lines which are provided for each sub-block, and a plurality of global bit lines which are provided so as to be shared by said plurality of sub-blocks, each main bit line can be selectively connected to one local bit line within a corresponding sub-block, each global bit line can be selectively connected to one main bit line from among a plurality of corresponding main bit lines, and a voltage controlling circuit for controlling the voltage of each main bit line independently of the voltage of the global bit line is further provided.