Patent ID: 7727834

Claim:
A method for manufacturing a semiconductor device, comprising: forming a conductive layer on a substrate; removing at least one portion of the conductive layer to form a plurality of separate conductive lines; forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate; removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines; forming a second stress-inducing layer of a second stress type opposite the first stress type on the conductive lines, the substrate, and the first stress-inducing layer; forming a mask layer that covers a first portion of the second stress-inducing layer over the second subset of conductive lines and exposes a second portion of the second stress-inducing layer over the first subset of conductive lines; and etching the second portion of the second stress-inducing layer using the mask layer as an etching mask, wherein the second portion of the second stress-inducing layer extends over a different third subset of the conductive lines, wherein the remaining portion of the first stress-inducing layer is not disposed on the third subset, and wherein the third subset includes a plurality of conductive lines each disposed between one of the conductive lines of the first subset and one of the conductive lines of the second subset, and wherein the first and second subsets of the conductive lines are field-effect transistor (FET) gates and the third subset of the conductive lines are not FET gates.