Patent ID: 7504850

Claim:
A single-event-effect tolerant SOI-based inverter comprising a first p-channel MOS transistor and a first n-channel MOS transistor, which are formed on a substrate having an SOI structure to provide a floating body structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, wherein: each of said first p-channel MOS transistor and said first n-channel MOS transistor is combined with a second MOS transistor having a channel of a same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that they are connected in series with respect to the source or drain line, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistors are connected together via a short line, so as to formed a double structure.