Patent ID: 8604844

Claim:
An output circuit comprising: a first output MOS transistor disposed between a first power supply terminal and an external output terminal, a current flowing from the source of the first output MOS transistor to the drain thereof being controlled on the basis of an external input signal; a second output MOS transistor disposed between a second power supply terminal and the external output terminal, a current flowing from the source of the second output MOS transistor to the drain thereof being controlled on the basis of an external input signal; and a first clamping MOS transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output MOS transistor, and a second terminal coupled to the drain of the first output MOS transistor, wherein the first output MOS transistor and the first clamping MOS transistor are p-channel MOS transistors, wherein the second output MOS transistor is an n-channel MOS transistor, a higher-potential power supply voltage is applied to the first power supply terminal, and wherein an intermediate voltage between the higher-potential power supply voltage and a lower-potential power supply voltage is applied to the second power supply terminal.