Patent ID: 7814280

Claim:
A shared memory, comprising: a plurality of receive ports characterized by a maximum port data rate; a plurality of transmit ports characterized by the maximum port data rate; a memory array comprising a plurality of memory banks, operation of the memory array being characterized by a second data rate; non-blocking receive crossbar circuitry configured to connect any of the receive ports with any of the memory banks; non-blocking transmit crossbar circuitry configured to connect any of the memory banks with any of the transmit ports; buffering configured to decouple operation of the receive and transmit ports at the maximum port data rate from operation of the memory array at the second data rate; and scheduling circuitry configured to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of frames of data in the shared memory, each of the frames of data comprising one or more data segments, each of the data segments comprising a plurality of data bytes, wherein the scheduling circuitry is configured in a store-and-forward mode to sequentially query the plurality of ports for the frames of data, arbitrate among a subset of the ports having the frames of data to assign a first starting location in a first one of the memory banks during a first cycle to a first data segment of a first frame received on a first one of the ports, facilitate storage of equal portions of the data bytes of the first data segment at the first starting location during the first cycle and corresponding locations in successive memory banks following the first memory bank on successive cycles, and facilitate storage of equal portions of the data bytes of each subsequent data segment of the first frame at corresponding locations in the first and successive memory banks until storage of the first frame is complete, such that the shared memory is fully provisioned for all of the ports simultaneously operating at the maximum port data rate.