Patent ID: 6875641

Claim:
A process for fabricating two memory levels in a memory array comprising: forming a first conductive layer; depositing a first semiconductor layer over the first conductive layer, the first semiconductive layer being doped with a first conductivity type dopant; forming a first antifuse layer over the first semiconductor layer; depositing a second semiconductor layer doped with a second conductivity type dopant over the first antifuse layer; in a first etch step, etching the first conductive layer, the first semiconductor layer, the first antifuse layer, and the second semiconductor layer into a plurality of first parallel, spaced-apart rail-stacks; filling the space between the first rail-stacks with a first insulator; planarizing the first upper surface of the first rail-stacks and the first insulator; forming a second conductive layer over the second semiconductor layer; depositing a third semiconductor layer doped with a second conductivity type dopant over the second conductive layer; in a second etch step, etching the second conductive layer and the third semiconductor layer into a plurality of second parallel, spaced-apart rail-stacks; filling the space between the second rail-stacks with a second insulator; planarizing the second upper surface of the second insulator and the second rail-stacks; forming a second antifuse layer on the planarized second upper surface; depositing a fourth semiconductor layer doped with a first conductivity type dopant over the second antifuse layer; forming a third conductive layer; in a third etch step, etching the third semiconductor layer and third conductive layer to form third parallel, spaced-apart rail-stacks; filling the space between the third rail-stacks with a third insulator.