Patent ID: 7447054

Claim:
A memory cell, comprising: a plurality of NAND gates comprising at least two inputs, each NAND gate further comprising: a first p-type transistor and a second p-type transistor; a first n-type transistor and a second n-type transistor; a first input; a second input; and an output; wherein the output of a first NAND gate of the plurality of NAND gates is coupled to one of the at least two inputs of each of the other NAND gates of the plurality of NAND gates; a plurality of access transistors, one for each of the other NAND gates, wherein the output of each other NAND gate is coupled to a source or drain of the associated access transistor; and a plurality of bitlines, one for each of the other NAND gates, wherein the plurality of access transistors couple the output of each other NAND gate to one of the plurality of bitlines.