Patent ID: 7133944

Claim:
A media access controller comprising: a local bus for connecting blocks of the media access controller with each other; a CPU connected with the local bus to drive the media access controller; a register unit connected with the local bus to store information used for software control of the CPU with respect to internal units of the media access controller; a host interface unit connected with the local bus to manage an interface between the media access controller and a host; a physical layer interface unit connected with the local bus to manage an interface between the media access controller and a physical layer; a power-save master for generating a signal for requesting an occupation/occupation expiration of the local bus in response to a signal inputted via the local bus and a value of the register; a bus arbiter for generating a signal controlling a use of the local bus in response to the signal generated from the power-save master; a power control unit for generating signals determining whether to supply clocks and power to the respective blocks of the media access controller, in response to the control signal of the bus arbiter, the register values inputted via the local bus, and a power-save mode exiting signal provided from other blocks of the media access controller; a phase-locked loop for generating clocks in response to the signal determining whether to supply the power, the signal being generated from the power control unit; a clock generator receiving the phase-locked clock from the phase-locked loop to generate clocks required to the media access controller, and supplying or disabling the clocks generated according to the signal determining whether to supply the clock, the signal being generated from the power control unit; and a wake-up timer for applying a power-save mode exiting signal to the power control unit in response to the signals inputted from the local bus and the clock generator.