Patent ID: 7898237

Claim:
A power factor correction apparatus, the apparatus comprising: a timing component being configured to receive a first input signal at a first time from a flip-flop component and generate a first output signal at a second time based on at least information associated with the first input signal; an AND gate being configured to receive the first output signal and a second input signal and generate a second output signal based on at least information associated with the first output signal and the second input signal; a zero current detector being configured to receive a third input signal and generate a third output signal based on at least information associated with the third input signal; the flip-flop component being configured to receive the third output signal at a first terminal and the second output signal at a second terminal and output a fourth output signal at a third terminal; and a driver component being configured to receive the fourth output signal and output a fifth output signal, the fifth output signal being at least capable of causing a switch to be turned off; wherein: a time difference between the first time and the second time is predetermined based on at least a characteristic of the apparatus; the first terminal is different from the second terminal; the third output signal is capable of setting the flip-flop component; and the second output signal is capable of resetting the flip-flop component.