Patent ID: 7023235

Claim:
A system comprising: transistors adapted to operate as an SR flip-flop wherein each one of the transistors has an insulated gate and wherein the SR flip-flop is a SEUSSNor comprising: a power node and four p type transistors named P 2 , P 4 , P 6 , and P 8 wherein the sources of P 2 , P 4 , P 6 , and P 8 are connected to the power node; a ground node and eight n type transistors named N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 , and N 8 wherein the sources of N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 , and N 8 are connected to the ground node; a p type transistor called P 1 wherein the source of P 1 is connected to the drain of P 2 ; a p type transistor called P 3 wherein the source of P 3 is connected to the drain of P 4 ; a p type transistor called P 5 wherein the source of P 5 is connected to the drain of P 6 ; a p type transistor called P 7 wherein the source of P 7 is connected to the drain of P 8 ; an S input connected to the gate of P 1 , the gate of N 1 , the gate of N 5 and the gate of P 5 ; an R input connected to the gate of P 3 , the gate of N 3 , the gate of N 7 and the gate of P 7 ; a Q 2 node connected to the gate of P 2 , the gate of N 6 , the drain of N 7 , the drain of P 7 , and the drain of N 8 ; a Qbar node connected to the gate of P 4 , the gate of N 8 , the drain of N 1 , the drain of P 1 , and the drain of N 2 ; a Q node connected to the gate of P 6 , the gate of N 2 , the drain of N 3 , the drain of P 3 , and the drain of N 4 ; and a Qbar 2 node connected to the gate of P 8 , the gate of N 4 , the drain of N 5 , the drain of P 5 , and the drain of N 6 .