Patent ID: 7725865

Claim:
A terminal layer setting method, in the method for a computer setting up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprising: obtaining by the computer various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing between a driver resistance of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with a cell or macro at a connecting destination by the computer; setting up a terminal layer based on a result of the comparing by the computer; and outputting a processing result of the setting up the terminal layer by the computer, wherein the terminal layer is a wiring layer to which a wiring terminal is extended from the subject cell or macro for connecting the subject cell or macro with the cell or macro at the connecting destination.