Patent ID: 7934178

Claim:
A method of laying out a semiconductor circuit, comprising: obtaining at least one of transistor characteristic information and variations in the transistor characteristic information on the basis of layout information about regions formed with transistors; obtaining at least one of a polynomial expression representing a relationship between characteristic values of a circuit including the transistors and the transistor characteristic information, and a polynomial expression representing a relationship between variations of characteristic values of the circuit and variations in the transistor characteristic information; calculating, by using a computer, a plurality of characteristic values corresponding to plural sets of transistor characteristic information or a plurality of variations of characteristic values corresponding to plural sets of variations in the transistor characteristic information by using the polynomial expression; selecting part of the plurality of the characteristic values which are values of a function of the polynomial expression or part of the plurality of the variations of the characteristic values, the variations being values of a function of the polynomial expression, on the basis of a restriction about the characteristic values; and obtaining the transistor characteristic information or the layout information used as a value of the variable in the function, corresponding to the selected part of the plurality of the characteristic values being the values of the function or the selected part of the plurality of the variations being the values of the function.