Patent ID: 8443174

Claim:
A method of performing speculative load instructions of a processor, the method comprising: performing a branch instruction; receiving a speculative load instruction; determining whether the speculative load instruction is related to a physical memory area; if the speculative load instruction is related to the physical memory area according to the determining, performing the speculative load instruction during an occurrence of a delay while the branch instruction is being performed; and if the speculative load instruction is related to a memory area that is not the physical memory area according to the determining, not performing the speculative load instruction during the occurrence of the delay, wherein the physical memory area corresponds to a first hierarchy memory area which is a highest order hierarchy from among multiple hierarchies, wherein the determining comprises determining whether the speculative load instruction includes an identifier, distinct from a memory address, for identifying that the speculative load instruction accesses the physical memory area, and wherein the determining further comprises determining whether the speculative load instruction is related to the physical memory area based on the identifier and whether the speculative load instruction is related to a performance improvement of the processor.