Patent ID: 8861275

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a first block, the first block including a first memory string, the first memory string including a memory cell, a first transistor, a second transistor, and a third transistor, the first transistor being electrically connected to the second transistor, the second transistor being electrically connected to the memory cell; a row decoder including a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the row decoder being configured to apply a first voltage to gates of the fourth transistor and the fifth transistor when the first block is selected, a first end of the fourth transistor and a first end of the fifth transistor being electrically connected to a first node, both a second end of the fourth transistor and a first end of the sixth transistor being electrically connected to a gate of the first transistor, a second end of the sixth transistor being electrically connected to a second node, the second node being different from the first node, both a second end of the fifth transistor and a first end of the seventh transistor electrically connected to a gate of the second transistor, a second end of the seventh transistor being electrically connected to a third node, the third node being different from both the first node and the second node, gates of the six transistor and the seventh transistor being electrically connected to a gate of the eighth transistor.