Patent ID: 8218347

Claim:
A memory device comprising: a semiconductor die having a substrate including: a first surface and a second surface; a first plurality of contact pads arranged in rows across the first surface; a second plurality of contact pads arranged in rows of consecutive adjacent contact pads across the second surface, wherein each contact pad of the second plurality of contact pads is physically arranged in a vertical alignment with a corresponding contact pad of the first plurality of contact pads and is electrically coupled to the corresponding contact pad using a via; a metallization layer formed on the second surface and including a plurality of external data contact pads arranged in rows of consecutive adjacent contact pads, wherein each of the external data contact pads is arranged in vertical alignment with a respective contact pad on the second surface, wherein the plurality of external data contact pads correspond to data signals of a memory bus of the memory device; wherein each row the plurality of external data contact pads is grouped to include n contact pads, numbered consecutively from A 0 to An−1, and each row of the second plurality of contact pads is grouped to include n contact pads, numbered consecutively from B 0 zero to Bn−1, where n is a positive integer; wherein for each group, a given external data contact pad Bk is electrically coupled to the contact pad Ak+1 on the second surface, where k is from zero to n−1, and wherein the Bn−1 external contact pad is electrically coupled to the A 0 contact pad on the second surface.