Patent ID: 7638869

Claim:
An integrated circuit comprising: a substrate; a first chip, a lower surface of the first chip being disposed adjacent to an upper face of the substrate; a second chip, a lower surface of the second chip being disposed adjacent to an upper surface of the first chip; a connecting layer comprising a connecting line, the connecting layer being arranged between the first and the second chips; a first chip wire contact pad that is arranged on an uncovered portion of the upper surface of the first chip; a first bonding wire that is connected with a first substrate wire contact pad and the first chip wire contact pad; a first substrate contact pad that is arranged on the upper surface of the substrate and is connected with a first via connecting element of the first chip; wherein the first via connecting element extends from the lower surface to the upper surface of the first chip; the first via connecting element is connected with a second via connecting element of the second chip, the second via connecting element extending from the lower surface to the upper surface of the second chip; and the connecting line is adapted to connect the second via connecting element with the first via connecting element.