Patent ID: 7532873

Claim:
A single chip integrated transceiver suitable for IEEE 802.11 applications, said transceiver comprising: a single-ended input low noise amplifier (LNA) having an LNA input and an LNA output; a quadrature mixer coupled to said LNA output, said quadrature mixer generating signals I and Q at first and second quadrature mixer outputs; a first controllable AC coupler having a first controllable AC coupler input coupled to said first quadrature mixer output, and a first controllable AC coupler output; a first channel filter having a first channel filter input coupled to said first controllable AC coupler output, and a first channel filter output; a second controllable AC coupler having a second controllable AC coupler input coupled to said second quadrature mixer output, and a second controllable AC coupler output; a second channel filter having a second channel filter input coupled to said second controllable AC coupler output, and a second channel filter output; an automatic gain control (AGC) having first and second AGC inputs, and first and second AGC outputs, wherein said first AGC input is coupled to said first channel filter output, and said second AGC input is coupled to said second channel filter output; a baseband processor coupled to said AGC; wherein during a first step of receiver signal processing, said baseband processor provides cut-off frequency control signals for said first and second controllable AC couplers such that said first and second AC couplers apply AC coupling at a first frequency for a first period of time, and said first and second AC couplers apply AC coupling at a second frequency for a second period of time, and further wherein said baseband processor provides signals for controlling said AGC; wherein during a second step of receiver signal processing, said baseband processor employs digital to analog converters coupled to said first and second controllable AC coupler inputs to cancel at least some DC offset present in said I and Q signals; wherein during a third step of receiver signal processing, said baseband process digitally filters said I and Q signals to reduce DC offset present in said I and Q signals, wherein the DC offset is estimated during a DC coupling.