Patent ID: 7791950

Claim:
A non-volatile memory (NVM) system, comprising: an array of NVM cells configured in rows and columns, each NVM cell comprising a storage element and a programming element, such that each NVM cell is arranged to be programmed, erased, and read based on a plurality of row selection, column selection, and programming signals, wherein a supply voltage for the storage elements is turned off during a programming mode and an erase mode; and an inverter circuit for each row of cells that is configured to provide an inverted row selection signal to each row, wherein the storage element of each NVM cell comprises a four field effect transistor (FET) logic circuit in one of a NAND and NOR configuration capable of storing two bits, wherein each of the FET pairs are arranged to share a common floating gate, and wherein each FET pair includes a first type FET and a second type FET, and wherein the programming element comprises two p-FETs coupled together at their gate terminals such that electrons are injected to the common floating gate when a high programming voltage is provided to a source, a drain, and an n-well terminal of a first p-FET of the two p-FETs and a low programming voltage is provided to a source, a drain, and an n-well terminal of a second p-FET of the two p-FETs, wherein the gate terminals of the first and second p-FETs are coupled to the common floating gate of the storage element.