Patent ID: 8706923

Claim:
A system, comprising: a processing entity configured to run multiple threads; and a direct memory access (DMA) engine coupled to the processing entity, the DMA engine is configured to track a DMA in flight status bit and a completion bit for each of a plurality of DMA channels, a DMA channel having an in-flight status when it cannot be stopped and has not been completed; wherein the processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status bit and said completion bit for said plurality of DMA channels; and wherein a DMA request received by the DMA engine comprises an instruction to allocate memory for storage of said DMA in flight status bit in a predetermined memory location, the memory allocated for storage of the DMA in-flight status bit readable by the processing entity via a load instruction and writable by the processing entity via a store instruction.