Patent ID: 7119396

Claim:
A memory device comprising: pairs of memory cells formed on a substrate of a first conductivity type, each of the memory cell pairs including: a pair of electron trapping dielectric material segments disposed over the substrate, a pair of first conductive material segments disposed over the dielectric material segments, a pair of spacers of material disposed over the first conductive material segments, and a first region formed in the substrate under the memory cell pair and having a second conductivity type different from the first conductivity type; a plurality of channel regions defined in the substrate each extending between adjacent pairs of the first regions, wherein each of the channel regions have first and second portions, and wherein each of the segments of the dielectric and first conductive materials are disposed over one of the channel region first portions for controlling a conductivity thereof; a layer of second conductive material that extends over the pairs of memory cells and that includes portions each of which extend over and are insulated from one of the channel region second portions for controlling a conductivity thereof.