Patent ID: 7426607

Claim:
A system comprising: a plurality of memory devices including a first memory device and a second memory device; a memory bus; and a memory controller configured to alternatively couple the memory bus between the memory controller and the first memory device and between the memory controller and the second memory device; wherein the memory bus comprises a single address and data bus that the memory controller shares for both the first and second memory devices and a separate data bus for the second memory device; wherein the memory controller is configured to multiplex at least I/O pins for the first memory device and address control pins for the second memory device comprised in the single address and data bus; and wherein the memory controller is configured to read data via the separate data bus from the second memory device during reading data from the first memory device or wherein the memory controller is configured to provide an address to a flash memory device via the single address and data bus during data being read from a random access memory device via the separate data bus.