Patent ID: 8248079

Claim:
A sensing circuit for sensing an electric fuse, the sensing circuit comprising: a capacitor coupled to the electric fuse; a detection circuit coupled to the electric fuse and the capacitor, the detection circuit controlling the capacitor to discharge according to a pulse width signal and a present resistance value of the electric fuse, so as to generate a detection voltage; an output circuit coupled to the detection circuit, the output circuit outputting a state of the electric fuse according to the detection voltage; a pulse width signal generator coupled to the detection circuit, the pulse width signal generator comprising a reference resistance and a reference capacitor and generating the pulse width signal according to a low to high signal, wherein a pulse width of the pulse width signal is affected by a discharging speed of the reference capacitor, and the discharging speed of the reference capacitor is affected by the reference resistance, the pulse width signal generator comprises: a first transistor, wherein a first terminal of the first transistor is coupled to a first voltage, a second terminal of the first transistor is coupled to the reference capacitor, and a gate terminal of the first transistor receives the low to high signal; a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, a second terminal of the second transistor is coupled to the reference resistance, and a gate terminal of the second transistor receives a second pulse width signal; a first inverter, wherein an input terminal of the first inverter is coupled to the second terminal of the first transistor; a second inverter, wherein an input terminal of the second inverter is coupled to an output terminal of the first inverter; a NAND gate, wherein a first input terminal of the NAND gate receives the low to high signal and a second input terminal of the NAND gate is coupled to the output terminal of the second inverter; and a third inverter, wherein an input terminal of the third inverter is coupled to an output terminal of the NAND gate and an output terminal of the third inverter provides the pulse width signal.