Patent ID: 7335966

Claim:
A semiconductor device comprising: a capacitor array comprising a plurality of capacitor tiles, each capacitor tile comprising at least one capacitor; a first plurality of first metal routing tracks overlaying the at least one capacitor of each capacitor tile; a second plurality of second metal routing tracks also overlaying the at least one capacitor of each capacitor tile, with the second metal routing tracks crossing over the first metal routing tracks; an orientation of the first metal routing tracks being alternated from one capacitor tile to the next; and an orientation of the second metal routing tracks being alternated from one capacitor tile to the next; each capacitor within a capacitor tile having: a first electrical connection to a first of said first metal routing tracks and a second electrical connection to a second of said first metal routing tracks; and a plurality of vias all belonging to a single layer within the semiconductor device, said plurality of vias connecting some of the second metal routing tracks to some of the first metal routing tracks, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor.