Patent ID: 7636811

Claim:
A cache memory that employs a set associative method including a plurality of ways and lines, and passes data to a processor according to a request from the processor, the cache memory comprising: a holding unit that holds the ways divided into a plurality of blocks in each of the ways, each of the blocks including a plurality of tag information, wherein a first entry address of the tag information is formed as the entry address when an entire cache capacity of a way is used, and a second entry address of the tag information is formed as the entry address using a different bit from the first entry address without changing a region of the entry address that is used when one block of the way is disabled, the tag information including the entry address and a status bit, the entry address being compared with a tag comparison address that determines whether the data specified by the line address is valid, and the status bit unit including information indicating whether the tag information is valid; an access-address acquiring unit that acquires an access address that includes a line address of a position of the data requested by the processor and the tag comparison address; a cache hit detector that determines which one block of the way is exclusively enabled; and a determination processing unit that determines whether the data requested by the processor has been hit, based on statuses of the access address and a result of a determination by the cache hit detector.