Patent ID: 8843690

Claim:
An apparatus comprising: a memory configured to (i) assert a first signal in response to detecting a conflict between at least two addresses requesting access to a first block of said memory at a first time, (ii) generate a second signal in response to a cache miss caused by a first address of said at least two addresses requesting access to said first block at a second time and (iii) store a first line of data fetched from external memory in response to said cache miss in a second block of said memory instead of said first block by adjusting said first address by a first address offset value, wherein said second time is after said first time; and a circuit configured to (i) generate said first address offset value in response to said assertion of said first signal and (ii) present said first address offset value in a third signal to said memory in response to said assertion of said second signal corresponding to reception of said first address at said second time, wherein said first address offset value is associated with said first address.