Patent ID: 8433944

Claim:
An apparatus comprising: a first input to receive an initial first ramp control value and an initial second ramp control value; a second input to receive a target first ramp control value and a target second ramp control value, the initial first ramp control value, the initial second ramp control value, the target first ramp control value, and the target second ramp control value collectively defining a desired ramp control adjustment of a system clock signal; a memory comprising a temporary first ramp control value register and a temporary second ramp control value register; and a single step increment calculation module responsive to the first ramp control values and the second ramp control values and comprising an output to generate a single step frequency adjustment, wherein in response to a frequency adjustment calculation, a calculated first ramp control value is stored in the temporary first ramp control value register and a calculated second ramp control value is stored in the temporary second ramp control value register, and wherein the generated single step frequency adjustment is applied to the system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency, wherein the first frequency is different from the second frequency and wherein the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.