Patent ID: 7110306

Claim:
An dual access DRAM comprising: a plurality of DRAM subarrays; a plurality of sense amplifier columns for sensing data in the DRAM subarrays; a first set of data lines; a plurality of selection circuits respectively coupled between each sense amplifier column and the first set of data lines for selectively coupling the first set of data lines to the sense amplifier columns; a second set of data lines; and means for selectively coupling the second set of data lines to the sense amplifier columns, wherein the first set of data lines is used for writing external data to a first DRAM subarray, or for providing external data read from a first DRAM subarray, and the second set of data lines is used to simultaneously transfer data between the first DRAM subarray and a second DRAM subarray; and further comprising a data transfer register coupled between a first portion of the second set of data lines and a second portion of the second set of data lines to provide sufficient drive capability to correctly write the transferred data between the first DRAM subarray and the second DRAM.