Patent ID: 7607113

Claim:
A processor-implemented method for determining optimal wiring patterns of plated leads in the vicinity of an edge of a semiconductor package having a multi-layered structure by computation, comprising: a determination step of moving, by a processor, positions of tentatively designed plated leads on said edge to the positions that can be accommodated in positionable windows nearest to the positions of the respective tentatively designed plated leads in a template in which said positionable windows are arranged so that said positionable windows have a predetermined pitch in a row direction corresponding to an identical layer of said multi-layered structure and so that said positionable windows are positioned at least in every other row in a column direction corresponding to a lamination direction of said multi-layered structure; a detection step of, among said tentatively designed plated leads, detecting by the processor, a plated lead that has the shortest straight line section orthogonal to the edge of said semiconductor package as a minimum straight line segment; and a reference setting step of setting, by the processor, a position that acts as a reference of said template when the positions of said tentatively designed plated leads are moved in said determination step, as the position of said minimum straight line segment, so that said minimum straight line segment can be surely positioned in any one of said positionable windows in said template, wherein said determination step moves the positions of said tentatively designed plated leads based on said template, the reference point of which is set in said reference setting step; and determining, by the processor, the moved positions as the optimal positions of said plated leads.