Patent ID: 7240144

Claim:
A data processing apparatus comprising: arbitration logic; and a data processor core, said data processor core comprising: a memory access interface portion for performing data transfer operations between an external data source and at least one memory associated with said data processor core; a data processing portion for performing data processing operations; a read/write port for transferring data from said processor core to first and second buses, said first and second buses providing data communication between said processor core and said at least one memory, said at least one memory comprising first and second memory portions, said first bus providing exclusive access to said first memory portion and said second bus providing exclusive access to said second memory portion, wherein said arbitration logic is associated with said read/write port and said arbitration logic is configured to route a data access request requesting access of data in said first memory portion received from said memory access interface to said first bus and to route a further data access request requesting access of data in said second memory portion received from said data processing portion to said second bus, said routing of said data access requests being performable during the same clock cycle, wherein said first and second portions of said memory include an instruction portion for storing instructions and at least one data portion for storing data items, respectively, said arbitration logic configured to route said data access request to said first bus for providing access to said instruction portion when data to be transferred is an instruction and to route said data access request to said second bus for providing access to said at least one data portion when data to be transferred is a data item, and wherein said at least one data portion includes an even data portion for storing data having an even address and an odd data portion for storing data having an odd address, said read/write port configured to transfer data between said processor core and said at least one memory via three buses including said first bus for providing access to said instruction portion, said second bus for providing access to said odd data portion, and a third bus for providing access to said even data portion, and said arbitration logic is configured to route a data access request to said first bus when data to be transferred is an instruction, to said second bus when data to be transferred is a data item associated with an odd address, and to said third bus when data to be transferred is a data item associated with an even address.