Patent ID: 6963077

Claim:
A memory array comprising: a first set of nanoscale wires; a second set of nanoscale wires intersecting the first set of nanoscale wires, intersections between the first set and the second set defining memory locations; wherein the memory locations are addressed by selecting one nanoscale wire of the first set of nanoscale wires and one wire of the second set of nanoscale wires; wherein nanoscale wires of the first set and nanoscale wires of the second set comprise controllable regions axially distributed along the nanoscale wires, a first set of the controllable regions exhibiting a first physical property, and a second set of the controllable regions exhibiting a second physical property, different from the first physical property; the memory array further comprising: a first plurality of addressing wires, each addressing wire of the first plurality associated with a series of regions of the first set of nanoscale wires; and a second plurality of addressing wires, each addressing wire of the second plurality associated with a series of regions of the second set of nanoscale wires.