Patent ID: 7220667

Claim:
A method of fabricating a semiconductor device comprising: a step of forming via-holes having a predetermined depth in an interposer comprising one of a silicon substrate, metal substrate and glass substrate; a step of forming a layer of a conductive material on the surface of said interposer, and at the same time filling said conductive material in said via-holes; a step of etching said layer of the conductive material to thereby form a wiring pattern; a step of grinding said interposer from the surface opposite to the surface on which said wiring pattern is formed, to thereby allow said via-holes to expose; a step of mounting a plurality of IC chips or chips being passive elements formed on one of a silicon substrate, metal substrate and glass substrate, on the surface of said interposer opposite to the surface on which said wiring pattern is formed, in a face-up manner; a step of forming an insulating film on said mounted chips; a step of forming a re-wiring pattern for mutually connecting said mounted chips on said insulating film; a step of forming openings in portions of said insulating film which falls on electrodes of said mounted chips, and at the same time forming via-holes having a predetermined diameter by opening portions of said insulating film which falls on gaps between the adjacent mounted chips; a step of filling openings including said via-holes with a conductive metal; and a step of planarizing the surface of said insulating film together with said filled conductive metal, wherein said conductive metal is copper.