Patent ID: 7892888

Claim:
A method of stacking semiconductor chips, comprising: providing a lead-frame having a plurality of leads disposed at a periphery thereof, the plurality of leads having lead inner portions and lead outer portions, the inner portions having first surfaces, second surfaces, and lead vias extending through the lead inner portions; providing a first chip stack comprising at least one chip having an active surface, a back surface, a plurality of bonding pads embedded in the active surface, and a plurality of chip vias extending from the plurality of bonding pads through the chip to the back surface without passing through the bonding pads, wherein the first chip stack is positioned on the first surfaces with the first active surface paralleling the first surfaces; positioning the first chip stack with a first active surface facing the first surfaces and with a first plurality of bonding pads aligned with and contacting the lead inner portions, and coaxially aligning the plurality of chip vias of said chip with the lead vias; providing a second chip stack comprising at least one chip having an active surface, a back surface, a plurality of bonding pads embedded in the active surface, and a plurality of chip vias extending from the plurality of bonding pads through the chip to the back surface without passing through the bonding pads; and positioning the second chip stack with a second active surface facing the second surfaces and with a second plurality of bonding pads aligned with and contacting the lead inner portions, wherein the second chip stack is positioned on the second surfaces with the second active surface paralleling the second surfaces, and coaxially aligning the plurality of chip vias of said chip with the lead vias.