Patent ID: 7419898

Claim:
A method for forming a gate structure for MOS devices, comprising: depositing a gate dielectric layer on a substrate; depositing a gate metal layer directly on the gate dielectric layer; depositing a cap layer directly on the gate metal layer, the bottom of the cap layer above the uppermost portion of the gate metal layer; patterning the cap layer, the gate metal layer and the gate dielectric layer to form a capped gate conductor; forming one or more spacers covering sidewalls of the capped gate conductor, including a stack of the patterned cap layer and gate metal layer; forming an inter-level dielectric layer over the capped gate conductor, the spacers and the substrate; forming a contact opening in the inter-level dielectric layer, exposing a portion of a top surface of the substrate adjacent to the spacers; and forming a contact structure within the contact opening, wherein the spacers and the cap layer separate the contact structure from the patterned gate metal layer enclosed therein.