Patent ID: 7198967

Claim:
A method of manufacturing a circuit comprising: forming first and second semiconductor layers over a substrate; forming a gate insulating film over the first and the second semiconductor layers; forming gate electrodes over the first and the second semiconductor layers with the gate insulating film interposed therebetween; introducing a first impurity element into portions of the first and the second semiconductor layers so as to form a pair of first impurity regions with a channel formation region interposed therebetween; introducing a second impurity element into portions of the first and the second semiconductor layers so as to form a pair of second impurity regions with the pair of first impurity regions interposed therebetween; and introducing a third impurity element into portions of the first semiconductor layer so as to form a pair of third impurity regions with the pair of second impurity regions interposed therebetween, wherein an edge of the gate insulating film is aligned with a boundary between the pair of second impurity regions and the pair of third impurity regions.