Patent ID: 7221198

Claim:
An interface circuit comprising: an address register that serially reads in an address code synchronously with a clock signal; an address decoder configured to output a decode output indicative of whether said address code inputted in said address register matches a predetermined address code; a hold circuit that holds decode output of said address decoder due to a control signal changing from one level to the other level; a data output circuit, in response to decode output indicating that said address code inputted in said address register matches the predetermined address code and being held in said hold circuit, outputting data, subsequent to said address code, to a data register that serially reads in said data synchronously with said clock signal; and a clock output circuit, in response to the decode output indicating that said address code inputted in said address register matches the predetermined address code and being held in said hold circuit and to said control signal being at the other level, outputting said clock signal to said data register, said clock output circuit further comprising: a latch circuit configured to output latch data for allowing said clock signal to be output, at a timing different in response to the decode output, and also at a timing different in response to whether said clock signal is held at the one level or the other level when said control signal changes from the one level to the other level, and a gate circuit configured to output said clock signal based on the latch data.