Patent ID: 7071487

Claim:
A wafer-level package comprising: a semiconductor wafer having at least one semiconductor chip circuit forming region that includes a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal; at least one external connection terminal electrically connected to said at least one non-test chip terminal; at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being electrically connected to said at least one test chip terminal and a second end of said redistribution trace being extended out to a position offset from one of said chip terminals; at least one test terminal, exclusively for testing, provided in an outer region outside said semiconductor chip circuit forming region, said second end of said redistribution trace being electrically connected to said at least one test-terminal; and an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one test terminal being exposed from said insulating material, wherein said at least one test terminal is provided in said outer region and corresponds to said at least one semiconductor chip circuit forming region.