Patent ID: 8289302

Claim:
An output buffer circuit with enhanced, slew rate, comprising: an output stage including a source transistor and a sink transistor for driving a, load; a first slew-rate enhancing transistor configured to enhance slew rate of one of the source transistor and the sink transistor; a second slew-rate enhancing transistor configured to enhance slew rate of the other of the source transistor and the sink transistor; a first control circuit configured to control the first slew-rate enhancing transistor; and a second control circuit configured to control the second slew-rate enhancing transistor; wherein the first control circuit and the second control circuit turn off the first slew-rate enhancing transistor and the second slew-rate enhancing transistor respectively during static state, and turn on the first slew-rate enhancing transistor and the second slew-rate enhancing transistor respectively during transition.