Patent ID: 7827387

Claim:
A system-on-chip (SOC) comprising: a processor; a controller module for a hard disk drive; and a communication bus that provides a communication link between the processor and the controller module, wherein the communication bus comprises: a first multiplexer that: includes a first output and a first input, receives data from a selected one of N registers associated with the controller module, and propagates the data to the first output; M address registers that store addresses of up to M ones of the N registers; M data registers that periodically receive pre-fetch data that corresponds to the data from the first output from the M ones, respectively, of the N registers; and a second multiplexer that: includes a second output connected to the processor, selectively propagates the data from the N registers to the second output for reading by the processor, and selectively propagates the pre-fetch data from the M data registers to the second output for reading by the processor, wherein M and N are positive integers greater than two and N is greater than M, and wherein the M data registers disable receiving the pre-fetch data when the processor is reading the data from the N registers.