Patent ID: 8180978

Claim:
An address locked loop (ALL) apparatus for address recycling comprising: a block of memory comprising a plurality of buffers; each said buffer has the same byte size; said block of memory is configured to store a plurality of incoming packets; wherein said incoming packet is stored in at least one said buffer if a byte size of said incoming packet is less than said byte size of said buffer; and wherein said incoming packet is stored in a plurality of buffers if said byte size of said incoming packet is greater than said byte size of one said buffer; an address stack configured for storing of a plurality of free addresses; wherein each said free address corresponds to one said free buffer; an address locked loop (ALL) control block coupled to said address stack; said address locked loop control block configured to provide an arbitrated interface with said address stack for filling address requests by a local process and for returning free addresses from said local process to said address stack; wherein said address locked loop (ALL) control block further comprises: an address locked loop (ALL) control feedback interface configured to send a feedback signal to a previous local process; and configured to receive a feedback signal from a following local process; wherein said ALL control feedback interface is configured to provide a data flow control between said previous local process and said following local process; and wherein said ALL control feedback interface further comprises: a plurality of flags; a first said flag is configured to indicate said local process status; a second said flag is configured to indicate said previous process status; a third said flag is configured to indicate said following process status; and a stack address counter coupled to said ALL; said stack address counter configured to maintain count of said available free addresses remaining on said address stack.