Patent ID: 7902904

Claim:
A bias circuit, comprising: a supply voltage and a reference supply voltage; a first resistor connected between said supply voltage and a feedback node; a plurality of resistors connected in series between said feedback node and said reference supply voltage, said connections between said plurality of resistors defining at least one bias voltage; a second resistor connected between said feedback node and a first drain node; a first field-effect transistor having a first gate node, said first drain node, and a first source node, said first gate node connected to said supply voltage; a second field-effect transistor having a second gate node, a second drain node, and a second source node, said second drain node being connected to said first source node, said second gate node connected to said bias voltage, and said second source node connected to an output signal node, said output signal node capable of experiencing an overshoot voltage, said first field-effect transistor and said second field-effect transistor are of a first type.