Patent ID: 8106444

Claim:
A semiconductor device comprising: a plurality of gate electrodes formed via an insulating film on a base, at least a surface of the base being formed of a semiconductor layer; a first diffusion layer and a second diffusion layer formed in the semiconductor layer with the plurality of gate electrodes sandwiched therebetween; and a channel layer formed between the first diffusion layer and the second diffusion layer in the semiconductor layer, wherein: the insulating film comprises a structure in which a plurality of insulating regions are disposed in due order from the first diffusion layer along the channel layer in the semiconductor layer toward the second diffusion layer; at least one insulating region of the plurality of insulating regions includes a charge trap and at least one insulating region of the plurality of insulating regions does not include a charge trap; the plurality of gate electrodes are formed on the base via the plurality of insulating regions, respectively; the plurality of gate electrodes are insulated from adjacent ones of the gate electrodes, respectively; levels of the channel layer formed below bottoms of the adjacent gate electrodes are different from each other, and the insulating film is formed also on part of the first diffusion layer and part of the second diffusion layer.