Patent ID: 8421191

Claim:
A semiconductor structure comprising: at least one FET gate stack located on an upper surface of a semiconductor substrate, the at least one FET gate stack including a source extension region and a drain extension region located within the semiconductor substrate at a footprint of the at least one FET gate stack, and a device channel located between the source extension region and the drain extension region and beneath the at least one gate stack; embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate, wherein each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer, wherein the lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material; and at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements, the at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.