Patent ID: 7900100

Claim:
A method for utilizing error correction code (ECC) logic that detects and corrects correctable errors to detect multi-bit errors, said method comprising: applying a first test pattern and a second test pattern to a set of hardware bit positions, wherein the second test pattern is the logical complement of the first test pattern, wherein the first and second test patterns are utilized by said ECC logic to detect correctable errors having n or fewer bits; determining one or more bit positions of a first correctable error occurring responsive to applying the first test pattern; determining one or more bit positions of a second correctable error occurring responsive to applying the second test pattern, wherein one or more of the bit positions of the second correctable error are different than the bit positions of the first correctable error; processing the determined bit positions of the first and second correctable errors to identify a multiple-bit error within the set of hardware bit positions; and in response to detecting a multiple-bit error within the set of hardware bit positions resulting from the processing of the determined bit positions of the first and second correctable errors, recording an uncorrectable error record entry, wherein said uncorrectable error record entry includes: the bit positions of the first and second correctable errors; and the count and frequency of occurrence of each of the first and second correctable errors.