Patent ID: 7720089

Claim:
A serial communication device comprising a first transmission/reception circuit and at least one second transmission/reception circuit connected to the first transmission/reception circuit by a transmission path for performing serial communication by half-duplex communication between the first transmission/reception circuit and the second transmission/reception circuit, wherein: the first transmission/reception circuit outputs a serial data signal DATA to the transmission path, said serial data signal DATA being generated by superposing a first superposition pulse having a second level on a portion of a clock signal input from outside having a first level according to binary first transmission data to be output to the second transmission/reception circuit, said clock signal being a binary signal, said second level being reciprocal to said first level; the second transmission/reception circuit superposes a second superposition pulse having the first level on a portion of the serial data signal DATA input from the transmission path according to binary second transmission data to be output to the first transmission/reception circuit, said portion corresponding to a duration of the clock signal having the second level, the first transmission/reception circuit comprises: a first transmission circuit that superposes the first superposition pulse on the portion of the clock signal having the first level, and outputs the serial data signal DATA to the transmission path, and a first reception circuit that extracts the second superposition pulse from the serial data signal DATA to extract the second transmission data; the first transmission circuit comprises: a first T 2 delay circuit that delays the clock signal by a time period T 2 and outputs said delayed signal, a first T 1 delay circuit that delays the output signal from the first T 2 delay circuit by a time period T 1 and outputs said delayed signal, a first superposition pulse generation circuit that generates the first superposition pulse having a pulse width T 1 from the output signal from the first T 2 delay circuit and the output signal from the first T 1 delay circuit, and a first output signal generation circuit that superposes the first superposition pulse from the first superposition pulse generation circuit to the clock signal according to the first transmission data, and generates data equaling to one bit sequentially to generate the serial data signal DATA and to transmit the serial data signal DATA to the transmission path; and the first output signal generation circuit sets an output terminal to be in a high impedance state when the serial data signal DATA is at the second level.