Patent ID: 8451660

Claim:
A semiconductor memory device comprising: a first conductive type well and a second conductive type well disposed on a semiconductor substrate; a first gate and a second gate disposed on the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at a first side of the first gate; a second conductive type second ion implantation region disposed in the first conductive type well at a second side of the first gate opposite to the first side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at a first side of the second gate; a first conductive type second ion implantation region disposed in the second conductive type well at a second side of the second gate opposite to the first side of the second gate; and a line electrically connecting the second conductive type second ion implantation region to the first conductive type first ion implantation region, wherein the first conductive type well, the first gate, the second conductive type first ion implantation region, and the second conductive type second ion implantation region collectively form a second conductive type select transistor and the second conductive type well, the second gate, the first conductive type first ion implantation region, and the first conductive type second ion implantation region collectively form a first conductive type floating transistor, wherein: the second conductive type first ion implantation region is connected to a common source line; the second conductive type second ion implantation region is connected to the first conductive type first ion implantation region; the first gate is connected to a word line; the first conductive type second ion implantation region is connected to a bit line; the second gate floats; a first voltage serving as a positive program voltage of positive potential is applied to the hit line and the second conductive well; a second voltage serving as a word line program voltage of positive potential is applied to the word line; and the common source line and the first conductive type well are connected to a reference voltage and programmed.