Patent ID: 6861306

Claim:
A method of forming a memory cell on a semiconductor material of a first conductivity type, the method comprising the steps of: forming a layer of first insulation material on the semiconductor material; forming a layer of first conductive material on the layer of first insulation material; defining a first region on the layer of first conductive material, and a second region on the layer of first conductive material, the first region being spaced apart from the second region; etching the first region of the layer of first conductive material to form a first surface of the layer of first conductive material, and the second region of the layer of first conductive material to form a second surface of the layer of first conductive material; etching the layer of first conductive material to form a floating gate, the floating gate having side wall surfaces and the first and second surfaces; forming a layer of second insulation material on the layer of first insulation material, on the side wall surfaces of the floating gate, and over the first and second surfaces of the floating gate; and forming a merged gate on the layer of second insulation material over the floating gate.