Patent ID: 7679983

Claim:
An address path circuit with a row redundant scheme, comprising: a pre-latch unit for pre-latching an internal address synchronously with a specific command to output a pre-latched internal address; a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection; and a global address generator for receiving the detection signals from the detector and a latched internal address and generating a global row address, the global address generator outputting the latched internal address from the address latch unit as the global row address when the detection result of the detector indicates that the pre-latched internal address from the pre-latch unit is the normal address, and an encoded address obtained by encoding the detection signals as the global row address when the detection result of the detector indicates that the pre-latched internal address is the repaired address.