Patent ID: 8575764

Claim:
A semiconductor device comprising; a semiconductor chip having a passivation film on a front surface thereof which is a functional surface; a sealing resin layer provided over the passivation film for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the passivation film such that the sealing layer covers the side surface of the passivation film; and a stress relieving layer having an upper surface and a side surface provided between the passivation film and the sealing resin layer for absorbing and relieving an externally applied stress; and a rewiring provided on the upper surface of the stress relieving layer, the rewiring having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed; wherein both the sealing resin layer and the stress relieving layer are in direct contact with an upper surface of the passivation film, and the sealing resin layer entirely covers the stress relieving layer, the passivation film and the rewiring.