Patent ID: 8193835

Claim:
A circuit for switching voltage at an first and second output terminals of the circuit, the circuit comprising: an n-type cascode stage coupled between the first and second output terminals and a pair of terminals through which a pair of voltage signals is applied to the n-type cascode stage, the n-type cascode stage enabling propagation of a first voltage signal to the first and second output terminals in a preset mode in response to a third voltage signal, the pair of voltage signals comprising the first voltage signal and a second voltage signal; a p-type cascode stage coupled to the first and second output terminals to enable propagation of the first voltage signal to an input voltage supply terminal of the circuit; a first pair of cross-coupled p-type metal oxide semiconductor (PMOS) transistors coupled to the input voltage supply terminal and responsive to voltage switching at the input voltage supply terminal to switch voltage at the first and second output terminals in a latched mode; and a pair of PMOS transistors, coupled between the first pair of cross-coupled PMOS transistors and the p-type cascode stage, that is responsive to the first voltage signal to inactivate a first one of the first pair of cross-coupled PMOS transistors and activate a second one of the first pair of cross-coupled PMOS transistors in the preset mode to enable propagation of the first voltage signal to the input voltage supply terminal and is responsive to the voltage switching at the input voltage supply terminal and a fourth voltage signal to enable propagation of the voltage switching at the input voltage supply terminal to the first and second output terminals in the latched mode in conjunction with the p-type cascode stage.