Patent ID: 8431962

Claim:
A field effect transistor device comprising: a substrate; a plurality of semiconductor device layers deposited on the substrate; a plurality of dielectric passivation layers deposited on the semiconductor device layers; a source terminal deposited directly on and in contact with the semiconductor device layers; a drain terminal deposited directly on and in contact with the semiconductor device layers; and a gate terminal deposited on at least one of the passivation layers so that all of the gate terminal is positioned on the at least one of the passivation layers and none of the gate terminal is positioned directly on any of the plurality of semiconductor device layers, wherein at least two of the passivation layers are made of a different dielectric material and wherein the thickness of the passivation layers between the source terminal and the gate terminal and the drain terminal and the gate terminal is greater than the thickness of the one or more passivation layers between the gate terminal and the semiconductor device layers so that at least one passivation layer is provided at sides of the gate terminal, wherein the plurality of passivation layers is three passivation layers where the thickness of the combination of two of the passivation layers closest to the device layers is thinner than a top passivation layer on the two passivation layers.