Patent ID: 6998911

Claim:
A switching amplifier comprising: two output transistors having respective current paths and control terminals, the current paths being connected in series between positive and negative power supply terminals with a common output node between the transistors being connectable to drive a load; a driver circuit for the control terminals; signal source providing a pulse width modulated (PWM) signal, the duty cycle of which is representative of an information signal; a control terminal driver circuit for each of the output transistors; the control terminal driver circuits being responsive to the PWM signal to generate pulse width modulated control terminal drive pulses to drive the output transistors between substantially fully on and fully off states with one transistor being on while the other is off; the control terminal driver circuits being further responsive to an operating state signal indicating a start up interval for the amplifier to vary the amplitude of the control terminal drive pulses between a zero value to a maximum value for normal operation of the amplifier over the start up interval; a feedback circuit including a detector which is responsive to a DC offset at the output node; and an error circuit responsive to an output of the detector to control the relative amplitude of the control terminal drive pulses during at least a portion of the start up interval to substantially eliminate DC offset.