Patent ID: 7577560

Claim:
A microcomputer logic development device comprising: a first block including a first Central Processing Unit (CPU) and a Random Access Memory (RAM) and providing functions corresponding to a microcomputer core; a second block including a second CPU and providing functions corresponding to microcomputer resources; a bus connecting said first and second blocks; and a RAM measurement block including a common memory, and being connected to said first block and a RAM measurement device; wherein a process for monitoring the RAM of said first block by the RAM measurement device is divided into a first process for writing content said RAM in said common memory and a second process for sending content of said common memory to said RAM measurement device, and said process for writing content of said RAM in said common memory and said process for sending content of said common memory to said RAM measurement device are performed in different timing; and wherein said first CPU performs an application processing, which is a process in a microcomputer core, upon receipt of an event from said second block, performs a data communication of I/O information with said second block while said application processing is being performed, and performs said first process at a last timing of said application processing.