Patent ID: 8832346

Claim:
An apparatus to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments, the apparatus comprising: a packing unit positioned between the first and second buses, the packing unit comprising: a flip-flop driving an effected first bus segment, and a multiplexer coupled to the flip-flop, the multiplexer receiving data from a plurality of second bus segments and adapted to enable the effected first bus data segment in sequence; and an unpacking unit positioned between the first and second buses, the unpacking unit comprising: a multiplexer, the multiplexer receiving data from a plurality of first bus segments and adapted to enable an effected first bus data segment in sequence; and a flip-flop coupled to the multiplexer to drive the effected second bus segment; wherein the packing and unpacking units utilize gated clocks for packing and unpacking of data, wherein the gated clock is enabled based on a target peripheral device's width, location, and the least significant bits of the address for the target peripheral device.