Patent ID: 7450462

Claim:
A method for performing memory operations in a multi-plane flash memory having a plurality of memory planes, the method comprising: providing commands and addresses for a memory operation in a first memory plane of the plurality of memory planes; simultaneously applying common program pulse signals to respective driver circuits associated with each of the memory planes of the plurality of memory planes; enabling the driver circuits associated with the first memory plane of the plurality of memory planes; beginning the memory operation in the first memory plane of the plurality of memory planes responsive to the common program pulse signals; during the memory operation in the first plane of memory, providing commands and addresses for the memory operation in a second memory plane of the plurality of memory planes; and during the memory operation in the first plane of memory, enabling the driver circuits associated with the second memory plane of the plurality of memory planes and beginning the memory operation in the second memory plane of plurality of memory planes responsive to the common program pulse signals.