Patent ID: 8445991

Claim:
A semiconductor device, comprising: a lower electrode on a substrate; a dielectric layer on the lower electrode, the dielectric layer comprising a first dielectric region and a second dielectric region; an upper electrode on the second dielectric region; a hardmask on the upper electrode, the hardmask comprising one or more substances selected from the group consisting of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), silicon-on-glass (SOG), field oxide (FOX), tetraethyl orthosilicate (TEOS), plasma TEOS (PE-TEOS), high density plasma oxide, silicon nitride (SiN), and silicon oxynitride (SiON); a spacer at a side surface of the hardmask and the upper electrode and over the first dielectric region; and a buffer insulation layer on the hardmask and the spacer.