Patent ID: 8423736

Claim:
A method of maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer comprising a plurality of compute nodes, each compute node comprising at least one processor operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the compute nodes, each cache controller coupled for data communications to cache controllers on other compute nodes, the method comprising: responsive to a cache miss of a cache line on a first one of the compute nodes, broadcasting by the first compute node to other compute nodes a request for the cache line; responsive to receiving the broadcast request, transmitting from each of the compute nodes receiving the broadcast request to all other nodes the state of the cache line on that node, including, if at least one of the compute nodes has a correct copy of the cache line, transmitting from the at least one compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.