Patent ID: 7482218

Claim:
A method for forming a transistor comprising: forming an n-well in a p-type substrate, the n-well including a selected central region having an effective net concentration of n-type dopant less than the concentration of n-type dopant in the remainder of the n-well; forming a p-type drain region in the selected central region of the n-well, the p-type drain region being more heavily doped at a center portion thereof and more lightly doped at a peripheral region thereof; forming first and second p-type source regions spaced apart from opposite edges of the p-type drain region at distances sufficient to form a first channel between the p-type drain region and the first p-type source region and a second channel between the p-type drain region and the second p-type source region, each of the first and second p-type source regions being more heavily doped at a center portion thereof and more lightly doped at a peripheral region thereof, and further being electrically connected to one another; and forming a first gate disposed above and insulated from the first channel and a second gate disposed above and insulated from the second channel, the first and second gates electrically coupled to one another.