Patent ID: 7737717

Claim:
A method for evaluating gate dielectrics, comprising: providing a test structure comprising a gate stack comprising a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in said substrate including a portion below said gate stack and a portion beyond said gate stack; pre-stress off-state I-V testing on said test structure to obtain pre-stress I-V test data, said pre-stress off-state I-V testing comprising a first measurement involving said gate electrode, said substrate and said diffusion region, a second measurement involving said gate electrode and said substrate with said diffusion region floating, and a third measurement involving said gate electrode and said diffusion region with said substrate floating, stressing comprising electrically stressing said test structure for a time (t); following said stressing, post-stress I-V testing comprising repeating said first, second and third measurements to obtain post-stress I-V test data, and evaluating said gate dielectric from said pre-stress and said post-stress I-V test data.