Patent ID: 8151176

Claim:
A parity checking circuit comprising: a microprocessor; instruction memory; a parity checker; an address capture device; a data bus connected to the microprocessor, the instruction memory and the parity checker; an address bus connected to the microprocessor, the instruction memory and the address capture device, wherein the instruction memory is configured to send a parity bit to the parity checker, wherein the address bus is configured to send an address to the parity checker, wherein the parity checker is configured to compare the address which the parity checker receives from the address bus to the parity bit which the parity checker receives from the instruction memory, and determine whether or not there is a parity error, wherein the parity checker is configured to send an error signal to the address capture device if a parity error is detected, wherein the address capture device is configured to capture an address that the address capture device receives from the address bus, whenever the address capture device receives the error signal from the parity checker.