Patent ID: 8913706

Claim:
A transceiver system comprising: a plurality of transmitters; a plurality of receivers; and a plurality of phase lock loop systems, wherein each of the plurality of phase lock loop systems comprises: a plurality of reference clock systems configured to receive a constant reference clock frequency, wherein each of the plurality of reference clock systems comprises: a bypass path, a divider path, the divider path including an adjustable divider configured to change a value of a divisor of the adjustable divider that divides the constant reference clock frequency, wherein the value is adjusted and set each time based on a selected communications protocol of a plurality of possible communications protocols, and a multiplexer configured to route the bypass path or the divider path based on the selected communications protocol, wherein, at any given time, the divisor value of each adjustable divider of the plurality of reference clock systems is different from a divisor value of each other adjustable divider of the plurality of reference clock systems; and a plurality of phase lock loops, wherein each of the plurality of phase lock loops comprises: a feedback path, the feedback path including an integer divider, wherein a divisor of the integer divider is set based on the selected communications protocol, and a voltage controlled oscillator configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol, wherein the one of the plurality of output clock frequencies is produced based on at least one of the routings of the multiplexer, the divisor of the adjustable divider, and the divisor of the integer divider, wherein the divisor of each integer divider of the plurality of phase lock loops is different from a divisor of each other integer divider of the plurality of phase lock loops.