Patent ID: 8055695

Claim:
A shift register having multiple serially connected shift register units, wherein an n th shift register unit of the shift register units outputs an output signal, which is an input signal of an (n+1) th shift register unit of the shift register units, and n is a natural number, the n th shift register unit comprising: a first level control unit for providing a first clock signal to an output terminal; a first driving unit, wherein the first driving unit and an input terminal of the first level control unit are coupled to a first node, a voltage on the first node is a first control signal, the first driving unit turns on the first level control unit in response to a front edge of the input signal, and turns off the first level control unit when a level of a second control signal is higher than a level of a third control signal; a second level control unit for providing a first voltage to the output terminal; a second driving unit for turning off the second level control unit in response to a front edge of the first control signal, and turning on the second level control unit in response to a rear edge of the first control signal; and a third level control unit for providing the first voltage to the output terminal in response to the front edge of the first control signal of an (n+2) th shift register unit of the shift register units.