Patent ID: 8122216

Claim:
A computer system, comprising: a processor having a cache; a main memory comprising first and second memory regions having different access characteristics; a memory controller to manage the main memory and to allow access to stored data blocks in the main memory, wherein the memory controller implements a memory reorganization process comprising an execution flow of process steps for accessing a data block that is stored in one of the first or second memory region, and storing the accessed data block in the other one of the first or second memory region; and a local buffer memory operated under control of the memory controller to temporarily buffer the accessed data block during the memory reorganization process, wherein the memory controller temporarily suspends the execution flow of the memory reorganization process in an incomplete and pending state with the accessed data block temporarily buffered in the local buffer memory and during the suspension of the execution flow, fetches another data block of the main memory to serve one of a new access request having priority over the execution flow masking a data access latency associated with the memory reorganization process, wherein the memory controller fetches a requested cache line corresponding to the new access request from main memory and places the requested cache line in the cache of the processor.