Patent ID: 7115929

Claim:
A semiconductor construction comprising: a substrate; a pair of wordlines supported by the substrate; the wordlines each comprising a gate dielectric, an electrically conductive material and an electrically insulating cap; the electrically insulative caps of the wordlines having uppermost surfaces; a source/drain region within the substrate between the wordlines, the source/drain region being electrically isolated from one of the wordlines and being part of a transistor comprising a gate contained by the other of the wordlines; an electrically conductive pedestal between the wordlines, over the source/drain region, and electrically connected with the source/drain region; the electrically conductive pedestal having an uppermost surface; the uppermost surface of the conductive pedestal and the uppermost surfaces of the electrically insulative caps of the wordlines together forming a planar platform extending across the wordlines and the electrically conductive pedestal; a first capacitor electrode over the planar platform and having a planar surface of conductively-doped silicon; a planar second capacitor electrode over the first capacitor electrode planar surface and comprising one or more materials selected from the group consisting of metals and metal compounds; a planar first dielectric layer between the first and second capacitor electrodes, the first dielectric layer comprising aluminum oxide; a planar second dielectric layer between the first and second capacitor electrodes, the second dielectric layer comprising a metal oxide other than aluminum oxide; wherein the first dielectric layer is between the second dielectric layer and the conductively-doped silicon; and wherein the metal oxide of the second dielectric layer is in physical contact with the second capacitor electrode.