Patent ID: 8639960

Claim:
Apparatus for processing data comprising: data processing circuitry configured to perform data processing operations; a plurality of state retention circuits forming part of said data processing circuitry, said plurality of state retention circuits configured to hold respective state values at respective nodes of said data processing circuitry when said data processing circuitry enters a low power mode; a scan path connecting said plurality of state retention circuits together in series, such that when said data processing circuitry is in a scan mode said state values may be scanned into and out of said respective nodes; and a plurality of parity information generation elements coupled to said scan path and configured to generate parity information indicative of said respective state values held at said respective nodes by said state retention circuits, wherein said plurality of parity information generation elements are arranged to provide a parity path, such that an output parity value generated at an output of said parity path will invert if one of said respective state values changes, wherein said plurality of parity information generation elements are provided with a parity element voltage supply which is configured to keep said parity information generation elements active with a full or reduced supply voltage when said data processing circuitry enters said low power mode and when said data processing circuitry is in said scan mode, and wherein said parity element voltage supply is configured to reduce or switch off the power supplied to said parity information generation elements when said data processing circuitry performs data processing operations not in said scan mode.