Patent ID: 8772903

Claim:
A semiconductor device comprising: a plurality of floating regions arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween and include a first floating region and a second floating region located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate; an insulating layer interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate; and a capacitance forming portion forming a capacitance in parallel with, and in addition to, either the capacitance of the insulating region between the first floating region and the island region of the predetermined potential, or the capacitance of the insulating region between each adjacent pair of floating regions of the plurality of floating regions, or both, the adjacent pair of floating regions including the first floating region, wherein the capacitance forming portion includes a plurality of capacitive elements, the capacitive elements on the side of the capacitance forming portion adjacent the first floating region have a greater capacitance than the capacitive elements on the side of the capacitance forming portion adjacent the second floating region, and the capacitance forming portion includes a capacitive element of the capacitive elements connected at a first end to a one floating region of an adjacent pair of floating regions and at a second end to another floating region of the adjacent pair of floating regions.