Patent ID: 8786319

Claim:
A latch isolation circuit comprising: a first node (CP) to supply a first analog signal; a latch having a first input (LP) to receive the first analog signal, an output to supply a digital signal responsive to the first analog signal, and a reset port, wherein the latch resets in response to a first edge of a periodic first clock (PH 1 ) and captures the first analog signal on a second edge of PH 1 ; a reset switch configured to selectively connect the latch first input to a first reference voltage in response to a periodic reset pulse (RST); a first series switch configured to selectively connect the first node (CP) to the latch first input (LP) in response to a periodic second clock (PH 2 ); wherein the first edge of the PH 1 occurs subsequent to a first edge of RST, but prior to a second edge of RST; and a first edge of PH 2 occurs subsequent to the first edge of PH 1 and a second edge of PH 2 occurs subsequent to the second edge of PH 1 .