Patent ID: 7196561

Claim:
A power-up reset (PUR) circuit for generating a reset signal, the PUR circuit comprising: a first node for receiving a reference voltage and a second node for receiving a supply voltage; a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith; a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage; and a programmable delay circuit having an input for receiving a third control signal and an output for generating the reset signal, the delay circuit being configurable for selectively adjusting a delay between a change of logical state of the second control signal and a change of logical state of the reset signal in response to the third control signal; wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.