Patent ID: 7763920

Claim:
A semiconductor memory comprising: a lower electrode; a first insulating region that is formed in the same layer as the lower electrode and that partitions the lower electrode; a ferroelectric film that is formed on the lower electrode and on the first insulating region; an upper electrode formed on the ferroelectric film; a second insulating region that is formed in the same layer as the upper electrode and that partitions the upper electrode; and a transistor comprising: a first impurity region connected to the lower electrode, a second impurity region connected to the upper electrode, and a channel region disposed between the first impurity region and the second impurity region; wherein at least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode, wherein the lower electrode includes at least one material selected from a group consisting of Pt, Ir, IrO 2 , SrRuO 3 , Ru, RuO 2 , and La 1-x Sr x VO 3 (X<0.2), and wherein the first insulating region comprises the material of the lower electrode and an insulating species.