Patent ID: 6976098

Claim:
A computing system comprising: a first processing module disposed to process first data and to provide first requests over a first data channel; a second processing module disposed to process data and to provide second requests over a second data channel; and a direct memory access (DMA) engine that is external to and shared by the first processing module and the second processing module for receiving the first and second requests over the first and second data channels, the DMA engine comprising: a centralized data reservoir divided into a plurality of device memory buffers, with one or more device memory buffers being allocated to the first processing module and one or more device memory buffers being allocated to the second processing module, in order to consolidate buffer requirements for the first processing module and the second processing module within the centralized data reservoir and an arbitration mechanism disposed to arbitrate the first and second data requests, wherein the arbitration mechanism arbitrates the data requests from the first processing module and the second processing module on a per module basis regardless of the number of requests made by the first processing module or by said second processing module.