Patent ID: 8106701

Claim:
A level shifter circuit connected to receive an input voltage at a first node, to receive a first enable signal, and to supply an output voltage at a second node, where the output voltage is provided from the input voltage in response to the first enable signal being asserted and to a low voltage value when the first enable signal is de-asserted, the level shifting circuit comprising: a depletion type NMOS transistor, having a gate connected to the second node; a PMOS transistor, having a gate connected to the first enable signal; a first resistive element distinct from the NMOS and PMOS transistors, where the NMOS transistor, the PMOS transistor and the first resistive elements are connected in series between the first and second nodes, the NMOS transistor being connected to the first node; and a discharge circuit connected to the second node and to receive a second enable signal, where the second enable signal is asserted when the first enable signal is de-asserted and is asserted when the first enable signal is de-asserted, and where the discharge circuit comprises one or more series connected transistors having control gates connected to receive the second control signal and connects the second node to the low voltage value when the second enable signal is asserted and isolates the second node from ground when the second enable signal is de-asserted.