Patent ID: 8719479

Claim:
A system for network adaptor optimization and interrupt reduction, the method comprising: a host platform comprising: a host device driver comprising: a build module configured to build an outbound Queued Direct I/O (QDIO) Storage Address Buffer List (SBAL) based on outgoing data; a queue addition module configured to add the outgoing data to an outbound QDIO buffer queue; a state update module configured to set a Storage-List-State Block (SLSB) buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting; a signal module configured to signal an Open Systems Adaptor (OSA) with a Signal Adapter-write (SIGA-w) signal; a network configured to communicate data between a plurality of devices; an OSA operationally coupled to the host platform, the OSA in communication with the network, the OSA comprising: a receiving module configured to receive the SIGA-w signal; a transmission module configured to process the outbound QDIO buffer queue and transmit the outgoing data to the network in response to the SIGA-w signal; a polling update module configured to set the SLSB buffer state to a polling state indicating that the OSA is polling for additional outgoing data; and an OSA polling module configured to poll for additional outgoing data for a predetermined time interval.