Patent ID: 7366947

Claim:
A method of operating a server for detecting the status of a DIMM inserted therein to assure the DIMM can monitor the address and control bus integrity, and can correct errors on the address and control bus and report errors and log and count errors consisting of the steps of; accessing said DIMM using an industry standard IIC protocol and address input range sources (SA 0 , SA 1 , SA 2 ), activating said DIMM to produce a byte of data which includes the contents of Byte 0 , i.e., Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RFU DIMM DIMM DIMM Mode Parity ECC ECC 0 Address Address Address 1=ECC Error error error SA2 SA1 SA0 0=Pty 1= 1=UE 1=CE PERR stimulating the DIMM to ensure that the DIMM echoes back the same SA 0 , SA 1 , and SA 2 address as that sent to the DIMM: and verifying that a high signal level (a “1”) is present on bit 3 .