Patent ID: 8386690

Claim:
An apparatus, comprising: a first integrated circuit layer comprising one or more first functional units; an interconnect layer coupled to the first integrated circuit layer; and power control logic for independently controlling a powering on/off of the first independent on-chip network and the second independent on-chip network, wherein: the first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit, the interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points, the one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer, and the power control logic operates to power off either the first independent on-chip network or the second independent on-chip network when the on-chip network is not being used.