Patent ID: 8450155

Claim:
A method for fabricating a field effect transistor, comprising the following steps: 1) etching source/drain region grooves by using a silicon oxide sacrificial gate as a mask; 2) depositing a strained dielectric layer that directly contacts the source/drain region grooves, and selectively etching the strained dielectric layer by using polysilicon sacrificial source/drain as a protection layer; 3) performing epitaxial growth by using exposed channel windows as seed crystal layers to obtain source/drain regions; 4) performing a light doped LDD implantation, depositing a silicon nitride layer, and performing a source/drain implantation by using the silicon nitride layer as a protection layer; 5) depositing a thick silicon nitride layer, and performing a chemical mechanical polish until the silicon oxide sacrificial gate; and 6) etching and removing the silicon oxide sacrificial gate, obtaining a gate dielectric layer, and depositing a polysilicon layer and performing a chemical mechanical polish to obtain a polysilicon gate.