Patent ID: 7205674

Claim:
A semiconductor package with build-up layers formed on a chip, comprising: a chip having an active surface and a non-active surface and formed with a plurality of bond pads on the active surface; a conductive bump formed on each of the bond pads of the chip; a carrier having a cavity for receiving the chip therein, wherein the non-active surface of the chip is attached to a bottom surface of the cavity, and a depth of the cavity is between a thickness of the chip and a sum of the thickness of the chip and a height of the conductive bump; a first dielectric layer which is applied over the active surface of the chip and the carrier, and which fills in the cavity and encapsulates the conductive bumps with ends of the conductive bumps being exposed; a plurality of first conductive traces formed on the first dielectric layer and electrically connected to the exposed ends of the conductive bumps; a second dielectric layer applied over the first conductive traces and formed with a plurality of vias by which predetermined portions of the first conductive traces are exposed; and a plurality of second conductive traces formed on the second dielectric layer and electrically connected to the exposed portions of the first conductive traces.