Patent ID: 7484188

Claim:
An on-chip test circuit for testing a system-on-chip integrated circuit, the on-chip test circuit comprising: a programming control unit having an input/output port adapted to receive an operation command, the programming control unit operable in a test-input mode to apply a plurality of command signals on a first control port in response to the operation command, and the programming control unit operable in a test-output mode to receive status data through the first control port and to provide the received status data on the input/output port; an execution and reporting unit coupled to the programming control unit through the first control port, the execution and reporting unit operable responsive to the command signals to apply a plurality of control signals on a second control port during the test-input mode and further operable during the test-output mode to capture result data received through the second control port and to process the result data to generate the status data, and to provide the status data on the first control port; and an interface unit coupled to the execution and reporting unit through the second control port and having an interface port adapted to be coupled to an IP core, the interface unit operable responsive to the control signals to apply interface control signals on the interface port to control the IP core during the test-input mode and operable during the test-output mode to receive core data through the interface port and to process the core data to generate the result data, and to provide the result data through the second control port to the execution and reporting unit; wherein the operation command comprises a command packet having, an operation code field that defines the operation to be performed by the on-chip test circuit; a data field containing data to be supplied to the IP core during the test-input mode; an expected time field containing an expected time to completion of the operation code; and an expected data field containing expected core data corresponding to the expected values of core data to be received from the IP core.