Patent ID: 7741192

Claim:
A method of manufacturing a semiconductor device having: a second conductivity type base region selectively provided in a surface region on a first principal surface of a first conductivity type semiconductor substrate; a first conductivity type emitter region selectively provided in a surface region on the base region; a MOS gate structure including: a gate insulator film provided on a surface of a section of the base region, the section being positioned between the semiconductor substrate and the emitter region; and a gate electrode provided on the gate insulator film; an emitter electrode in contact with the emitter region and the base region; a second conductivity type collector layer provided on a surface layer of a second principal surface of the semiconductor substrate; a collector electrode in contact with the collector layer; and a second conductivity type isolation layer surrounding the MOS gate structure, reaching from the first principal surface to the second principal surface while being inclined to the second principal surface, and being coupled to the collector layer, each of the first principal surface and the second principal surface being a {100} plane, and a surface of an isolation layer being a {111} plane, the method including the steps of: covering the first principal surface of the first conductivity type semiconductor substrate with a mask having openings of a desired pattern; forming a trench whose cross sectional shape is a trapezoid-shape on the semiconductor substrate by etching sections of the first principal surface of the semiconductor substrate without using a mask in areas of the openings, said etching being wet anisotropic etching with an alkaline solution; and forming the second conductivity type isolation layer by introducing a second conductivity type impurity into a side wall of the trench.