Patent ID: 7620138

Claim:
A data reception apparatus for receiving a first parallel data of a plurality of bits, comprising: a plurality of clock adjustment devices, the number of clock adjustment devices being equal to a number of bits of the first parallel data, each of the clock adjustment devices adjusting a first clock signal using a data signal of each bit of the first parallel data, the data signal being different from the first clock signal, and generating an adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit of the first parallel data; a plurality of data buffer devices, the number of data buffer devices being equal to a number of bits of the first parallel data, each of the data buffer devices fetching the data signal of each bit and retaining a fixed number of data for each bit in chronological order, in accordance with the adjustment clock signal; a read device selecting data of a plurality of bits in the data buffer devices in chronological order and reading out the selected data as a second parallel data, in accordance with a second clock signal, each bit of the selected data being selected from each of the data buffer devices; and a storage device storing the second parallel data.