Patent ID: 7624157

Claim:
A single chip network controller for interfacing between a physical network and a processing system on a media side of the network controller external thereto, comprising: a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data; a media layer for interfacing with the external processing system for receiving data from the external processing system for interface with said physical layer for encoding and transmission thereof, and for receiving decoded data from said physical layer and providing access thereto by the external processing system; on-chip non-volatile memory having a first portion associated with configuration information for configuring operation of said physical layer and said media layer and a second portion thereof that is accessible by the external processing system on the media side of the network controller; and a memory interface interfacing the external processing system with the second portion of said memory, the external processing system having an expanded memory capability, with the memory space of the external processing system being mapped with the memory space of the on-chip non-volatile memory, the mapped portion of the on-chip non-volatile memory extending the memory for the external processing system, wherein an address that is generated by the external processing system addresses a memory location in the internal memory space of the external processing system can be received by said memory interface to access a mapped location in said non-volatile memory.