Patent ID: 7092475

Claim:
An apparatus including a phase-frequency detector (PFD) having substantially linear phase error gain within a predetermined phase error range centered about zero phase error when used in a delta sigma phase-locked loop (PLL), comprising: first logic circuitry that receives reference, feedback and output control signals and in response thereto provides frequency increase and decrease control signals, wherein said reference signal has an associated frequency, phase and assertion state, said feedback signal has an associated frequency, phase and assertion state, said frequency increase control signal is indicative of when said feedback signal frequency is lower than said reference signal frequency, has an assertion state corresponding to said reference signal assertion state and has a de-assertion state responsive to said output control signal, and said frequency decrease control signal is indicative of when said feedback signal frequency is higher than said reference signal frequency, has an assertion state corresponding to said feedback signal assertion state and has a de-assertion state responsive to said output control signal; and second logic circuitry, coupled to said first logic circuitry, that receives and combines said frequency increase and decrease control signals and in response thereto provides said output control signal, wherein one of said frequency increase and decrease control signal assertion states is of a substantially constant time duration at least during when a difference between said reference and feedback signal phases is within a predetermined phase difference range centered about zero phase difference.