Patent ID: 7916822

Claim:
A clock and data recovery (CDR) circuit for recovery of an input analog signal, comprising: at least two data detectors to receive in parallel said input analog signal, each of said detectors to detect samples of said analog signal and to produce a data detector output; at least two phase detectors, wherein each of said at least two phase detectors corresponds to one of said at least two data detectors, said phase detectors to receive as inputs the data detector outputs and to produce phase detector outputs; a phase selection circuit (PSC) for generating a sampling signal used to obtain said samples, said sampling signal comprising frequency and phase, wherein said sampling signal for each of said at least two data detectors have a phase offset relative to one another; a voltage controlled oscillator (VCO) connected to said PSC for generating a clock signal, said clock signal controlling said frequency of said sampling signal; and a phase adjustment signal generator connected to said PSC for generating a phase adjustment signal, said phase adjustment signal controlling said phase of said sampling signal.