Patent ID: 7449752

Claim:
A chip comprising: a silicon substrate; an ESD circuit in or on said silicon substrate; a first internal circuit in or on said silicon substrate; a driver, receiver or I/O circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure; a third via over said silicon substrate and in said dielectric layer, wherein said third via is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit; and a fourth via in said passivation layer and directly over said third via, wherein said fourth via is connected to said third via.