Patent ID: 8163646

Claim:
A method for manufacturing an interconnection wiring structure of a semiconductor device, the method comprising: forming an isolation region, wherein the isolation region arranges an active region in a diagonal direction with respect to a semiconductor substrate; forming a first interlayer insulation layer on the active region; forming a plurality of bit line contacts, wherein the bit line contacts penetrate the first interlayer insulation layer, and wherein the bit line contacts are coupled to the active region; forming a second interlayer insulation layer, wherein the second interlayer insulation layer covers the bit line contacts; forming a plurality of first damascene trenches by selectively etching the second interlayer insulation layer, wherein the first damascene trenches expose a plurality of upper portions of the bit line contacts; forming a plurality of bit lines, wherein the bit lines fill the first damascene trenches; forming a second damascene trench by selectively etching a portion of the second interlayer insulation layer between the bit lines and selectively etching a portion of the first interlayer insulation layer, wherein the second damascene trench exposes a portion of the active region; attaching a trench spacer on side walls of the second damascene trench; forming a storage node contact line, wherein the storage node contact line fills the second damascene trench; forming a mask having a linear shape, wherein the mask intersects with the storage node contact; forming node separation grooves by selectively etching the portion of the storage node contact line exposed by the mask, wherein the node separation grooves separate the storage node contact line into storage node contacts; and forming a third interlayer insulation layer, wherein the third interlayer insulation layer fills and insulates the node separation grooves.