Patent ID: 7772877

Claim:
An output buffer circuit comprising: an input terminal for receiving an input signal; a delay circuit for delaying the input signal input from the input terminal for a certain period of time; an inverter for inverting the input signal delayed for the certain period of time by the delay circuit; an output buffer for receiving the input signal inverted by the inverter; and an output terminal for outputting a signal from the output buffer which has received the input signal; wherein the output buffer includes an output resistance, the output resistance including a variable resistance portion, wherein a pre-emphasis amount is changed by changing the variable resistance value, wherein the output buffer circuit transmits a logical signal from the output buffer to a transmission line and generates a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line, and wherein the output buffer has a selector on a forward stage and the variable resistance portion of the output resistance and the inverter is configured to operate in cooperation with the selector to select a signal input into the output buffer by a selector logic, invert a data signal, adjust a top pre-emphasis amount by a select signal of the selector logic and change a pre-emphasis amount by changing a variable resistance value.