Patent ID: 8659963

Claim:
A memory array, comprising: a plurality of global bit lines, wherein each bit line is coupled to a plurality of memory cells; a plurality of precharge logic, wherein each precharge logic is coupled to an associated global bit line in the plurality of global bit lines; identification logic coupled to the plurality of precharge logic, wherein the identification logic provides a precharge enable signal that enables a subset of the plurality of precharge logic to precharge its associated subset of the plurality of global bit lines to a voltage level of a voltage source and wherein the identification logic sends the precharge enable signal to the subset of the plurality of precharge logic on each clock cycle, thereby reducing the power consumption of the memory array; a NAND gate between the identification logic and each of the plurality of precharge logic, wherein a first input to the NAND gate is coupled to the identification logic via a first latching mechanism, wherein a second input to the NAND gate is coupled to a local clock signal, wherein an output of the NAND gate is coupled to each precharge logic, wherein the first latching mechanism, when activated by the identification logic, provides the precharge enable signal to the NAND gate, and wherein the first latching mechanism provides a scanable boundary in front of the plurality of memory cells; and a NOR gate coupled between each global bit line and an output device, wherein a first input to the NOR gate is coupled to the global bit line, wherein a second input to the NOR gate is coupled to the identification logic via a second latching mechanism, wherein an output of the NOR gate is coupled to the output device, and wherein the second latching mechanism, when activated by the identification logic, provides the precharge enable signal to the NOR gate.