Patent ID: 7142466

Claim:
A memory unit comprising: a memory array containing a plurality of memory cells organized as a plurality of rows and a plurality of columns, each of said plurality of memory cells storing a corresponding bit value; a plurality of column lines, with each column line providing a common path for the outputs of cells in a corresponding one of said plurality of columns; a plurality of row enable signals, with each row enable signal enabling the cells in a corresponding one of said plurality of rows causing the cells to provide the corresponding bit values on said plurality of column lines; a decoder receiving a row address and enabling one of said plurality of row enable signals according to said row address; a plurality of sense amplifier units, with each of said plurality of sense amplifier units being connected to receive a corresponding bit value on a corresponding one of said plurality of columns, said plurality of sense amplifier units sensing said plurality of columns according to a sense enable signal; and a tracking circuit generating said sense enable signal at optimal time instances, said tracking circuit comprising: a scalable drivers block containing a plurality of dummy cells connected by a dummy column, each of said dummy cells having a drive strength identical to that of said plurality of cells, said scalable drivers block receiving a first pulse and generating a first transition with a delay substantially equaling the delay with which said bit values would be propagated on corresponding columns; and a control block receiving said first transition and generating said sense enable signal in response.