Patent ID: 6917549

Claim:
An integrated memory, comprising: a memory cell array, the memory cell array having word lines for the selection of memory cells and bit lines for reading out or writing data signals of the memory cells, the bit lines being organized in bit line pairs, the bit lines of one of the bit line pair crossing one another at a crossing location and running parallel to one another; a sense amplifier, which is connected to one of the bit line pairs at one end of the bit line pair; two precharge circuits, the precharge circuits being connected to one of the bit line pairs in order to precharge the bit lines of the bit line pair to a precharge voltage, one of the precharge circuits being arranged on a side of the crossing location which faces the sense amplifier, the other of the precharge circuits being arranged on a side of the crossing location which is remote from the sense amplifier, the first precharge circuit facing the sense amplifier being arranged at a first distance from the crossing location and at a second distance from the sense amplifier, the first distance being less than the second distance.