Patent ID: 7137093

Claim:
A method for generating an integrated circuit (IC) layout for an IC that is to include cells interconnected by nets to form signal paths, wherein some of the signal paths are time-constrained signal paths, wherein each time-constrained signal path is subject to a timing constraint limiting a delay through that signal path to not exceed a specified maximum allowable delay, the method comprising: a. generating a placement plan specifying initial positions of the cells within the layout prior to generating a routing plan, b. processing the placement plan to estimate a length of each net to be included in the time-constrained signal paths based on the specified initial positions of cells that the net is to interconnect, c. estimating a path delay through each time-constrained signal path based at least in part on the length of each net included in the time-constrained signal path estimated at step b, d. identifying each time-constrained signal path as a critical path when a difference between its maximum allowable path delay and its path delay estimated at step c is less than a predetermined slack margin λ, and e. determining how to modify the placement plan so that it specifies new positions within the layout for cells included in each identified critical path, with the new positions being selected to reduce the path delays through the critical paths.