Patent ID: 8484437

Claim:
A data processing apparatus comprising: a pre-fetch unit configured to divide and store data; a validation setting unit configured to store information regarding whether or not the data stored in the pre-fetch unit are valid; an address generation unit configured to generate an address for reading/storing the data from/in the pre-fetch unit; and a pre-fetch control unit configured to control a storage position of the data in the pre-fetch unit by using the address and information of the address generation unit and the validation setting unit, wherein the pre-fetch unit comprises: a first register and a second register each configured to store a respective N-bit output of the data, where the data is 2×N bit data and N is any positive integer; a first multiplexer configured to selectively output an output of the first register or an N-bit output of the data currently inputted; a second multiplexer configured to selectively output an output of the second register or another N-bit output of the data currently inputted; a third register and a fourth register configured to store an output of the first multiplexer and an output of the second multiplexer, respectively; and a third multiplexer configured to selectively output an output of the third register or an output of the fourth register, wherein, when all of the first to fourth registers are invalid, the first multiplexer outputs the N-bit output of the data currently inputted, and the second multiplexer outputs another N-bit output of the data currently inputted.