Patent ID: 8560814

Claim:
A microprocessor comprising: an instruction pipeline configured to concurrently process instructions corresponding to a plurality of threads, wherein the instruction pipeline comprises one or more hardware (HW) resource groups each configured to execute instructions; and control circuitry; wherein for a given HW resource group of the one or more HW resource groups, the control circuitry is configured to: identify at least two active threads configured to utilize the given HW resource group and execute an instruction of a first type, the given HW resource group being configured to support only one of the at least two active threads at a given time; set a thread mode for a first thread of the at least two active threads to a first mode which causes an issued instruction of the first type to execute with one or more added stalls within the given HW resource group, in response to a condition being met, said condition comprising determining the first thread is associated with an instruction of the first type and a second thread of the at least two active threads is not associated with an instruction of the first type; and set the thread mode for the first thread to a second mode which causes the issued instruction of the first type to execute without said one or more added stalls within the given HW resource group, in response to said condition not being met.