Patent ID: 7106292

Claim:
A shift register comprising: a plurality of stages including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock and a first control signal, the first clock being prevented from being outputted from each of the odd numbered stages in response to the first control signal, the even numbered stages respectively receiving a second clock and a second control signal, the second clock being prevented from being outputted from each of the even numbered stages in response to the second control signal, the second clock having a first phase 180° different from a second phase of the first clock, the stages respectively delaying the first clock or the second clock by a first period to sequentially output the first clock end the second clock as a scan line driving signal; a dummy stage for generating a dummy output signal, the scan line driving signal of a last stage falling below a first predetermined voltage level in response to the dummy output signal of the dummy stage, the dummy output signal being delayed by a second period and falling below a second predetermined voltage level in response to the dummy output signal.