Patent ID: 7464350

Claim:
A method of verifying a layout of an integrated circuit device, said method comprising the steps of: establishing designations comprising positive and negative relationships between layers and device types of said integrated circuit device, wherein said positive relationship indicates the presence of a layer with respect to a device type and said negative relationship indicates the absence of a layer with respect to a device type; receiving a physical layout for a schematic of a circuit to be implemented in said integrated circuit device; generating an implant table file associated with a process for implementing said integrated circuit device, said implant table file having one of said designations for each combination of a layer of said physical layout and said device type of said integrated circuit device to show a relationship between each layer of said physical layout and each device type of said integrated circuit device; and generating a layout-versus-schematic rules file using said implant table file to ensure that each said layer of said physical layout is located where it is supposed to be located; and performing a layout-versus-schematic verification of said physical layout using said layout-versus-schematic rules file.