Patent ID: 8677049

Claim:
A method, comprising: in response to a cache miss based on a first address: selecting a first plurality of memory locations of a first memory based on a cache line associated with the first address; selecting a subset of the plurality of memory locations based on first region information delineating a cache region associated with the first address, the cache region comprising a plurality of cache lines, wherein selecting the subset selects fewer than all of the plurality of memory locations; storing values at the selected subset of the plurality of memory locations; and fetching an instruction based on the values stored at the subset of the plurality of memory locations, wherein fetching an instruction comprises modifying a plurality of confidence values stored a second memory, each of the plurality of confidence values associated with an address of a third memory, wherein modifying the confidence values comprises selecting the plurality of confidence values based on the values stored at subset of the plurality of memory locations by rotating based on second region information indicating a location of the cache line in the cache region the values stored at the first memory to determine a rotated value and selecting the plurality of confidence values based on the rotated; and clearing the first memory of the values stored at the subset of the plurality of memory locations in response to rotating the values.