Patent ID: 7012463

Claim:
A circuit with a common-mode dual output comprising: a common-mode circuit with an output portion; a common-mode corrector circuit connected to alternate the states of said output portion between an average output level and a desired common-mode level, the difference between the average and desired levels being proportional to a signal offset level; and an error correcting circuit connected to said common-mode corrector circuit to adjust the signal offset level; wherein said common-mode corrector circuit further includes: a common-mode voltage terminal connected to said output portion through a first pair of switches, said first pair of switches being responsive to alternating clock cycles which alternate the states of said output portion; a bias terminal providing a bias level, said bias terminal being connected to a first control terminal in said common-mode circuit through a second pair of switches, said second pair of switches being responsive to the alternating clock cycles; a precharging capacitor which stores the difference between the desired common-mode level and the bias level during a first clock cycle in the alternating clock cycles; and a common-mode capacitor which stores the average output level during the first clock cycle, said common-mode capacitor and said precharging capacitor being connected in parallel during a second clock cycle in the alternating clock cycles.