Patent ID: 6993108

Claim:
A digital filter of a DPLL (Digital Phase locked loop) comprising: a first reloadable register portion for storing a TBW (total bandwidth) value, wherein said first reloadable register portion is capable of being coupled to a first port for inputting said TBW value that is programmed into said first reloadable register portion through said first port; a second reloadable register portion for storing a DBW (differential bandwidth) value, wherein said second reloadable register portion is capable of being coupled to a second port for inputting said DBW value that is programmed into said second reloadable register portion through said second port; an up — counter for generating an UP — CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal generated by a phase selector; a down — counter for generating a DOWN — CNT value by counting up each DOWN signal pulse generated by said phase transition detector when said first phase of said SDIN (serial data input) signal lags said second phase of said current ACLK (recovered clock) signal; an adder for adding said UP — CNT value and said DOWN — CNT value to generate a SUM value; a subtractor for generating a DELTA value that is the difference between said UP — CNT value and said DOWN — CNT value; a delta comparator for asserting a LTP (larger than positive) signal if the magnitude of said DELTA value is greater than said DBW value and if said DOWN — CNT value is greater than said UP — CNT value, and for asserting a STN (small than negative) signal if the magnitude of said DELTA value is greater than said DBW value and if said UP — CNT value is greater than said DOWN — CNT value; a sum comparator for asserting a WE (write enable) signal when said SUM value is greater than said TBW value; and a phase select controller for asserting a FWD (forward) signal if said LTP signal is asserted when said WE signal is asserted or for asserting a BWD (backward) signal if said STN signal is asserted when said WE signal is asserted; wherein said phase selector selects another clock signal having a leading phase from said current ACLK signal as a new ACLK (recovered clock) signal when said FWD signal is asserted; and wherein said phase selector selects another clock signal having a lagging phase from said current ACLK signal as said new ACLK (recovered clock) signal when said BWD signal is asserted; and wherein said phase selector selects said current ACLK signal to remain as said new ACLK (recovered clock) signal if said FWD signal and said BWD signal are not asserted when said WE signal is asserted.