Patent ID: 7525180

Claim:
A semiconductor mount substrate provided as a wiring substrate having a plurality of segments arranged at equal intervals in straight rows to form segment groups, a pair of the segment groups being arranged in parallel with each other, and an outer connecting portion placed along substrate peripheral edges to surround the segment group in the front row and the segment group in the rear row, a semiconductor mount area, internal terminals and external terminals being provided on each segment, the semiconductor mount substrate comprising: a staggered array of the segments formed by half-pitch shifting the arrangement intervals of the segment group in the front row and the arrangement intervals of the segment group in the rear row from each other; rear-row tie bars provided between the segments in the front row to connect the segments in the rear row and the outer connecting portion; and front-row tie bars provided between the segments in the rear row to connect the segments in the front row and the outer connecting portion.