Patent ID: 7524757

Claim:
A method for manufacturing a multi-level transistor on a substrate having a cell region and a peripheral region, the method comprising: forming a recessed region in the cell region of the substrate to define a first active region; forming a first transistor on the first active region; forming a first insulating layer on the substrate to cover the recessed region and the first transistor; forming a first contact hole through the first insulating layer to expose a portion of the first active region; growing a preliminary first selective epitaxial growth (SEG) layer on the exposed portion of the first active region to fill the first contact hole and at least partially cover an upper surface of the first insulating layer; planarizing the preliminary first SEG layer using a Chemical Mechanical Polishing (CMP) process to expose the upper surface of the first insulating layer to form a first SEG layer on the substrate; forming a preliminary second SEG layer on the first SEG layer and the first insulating layer, wherein the preliminary second SEG layer is formed only in the cell region; forming a dummy layer on the substrate and only in the peripheral region; planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer; forming a second active region from the second SEG layer formed on the first insulating layer; and, forming a second transistor on the second active region.