Patent ID: 8014485

Claim:
A clock generator system, comprising: a phase locked loop (PLL) including a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency, wherein the second clock signal is out-of-phase with the first clock signal; a first clock generator having a first clock input configured to receive the first clock signal, a second clock input configured to receive the second clock signal, a mode signal input configured to receive a first mode signal, and an output, wherein the output of the first clock generator is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and the first mode signal; and a second clock generator having a first clock input configured to receive the first clock signal, a second clock input configured to receive the second clock signal, a mode signal input configured to receive a second mode signal, and an output, wherein the output of the second clock generator is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and the second mode signal.