Patent ID: 8304864

Claim:
A package ( 138 ) for encasing at least one semiconductor device ( 28 ), comprising: a lead frame including an electrically conductive substrate and having opposing first and second sides, said first side of said lead frame having a planar first side surface ( 121 ) and an array of lands ( 14 ), a surface of each of said lands comprising a portion of said first side surface, said lands adapted to be bonded to external circuitry and being arranged in a first pattern, and said second side of said lead frame having a planar second side surface ( 122 ) and an array of chip attach sites ( 124 ), each of said chip attach sites comprising a portion of said second side surface, said chip attach sites being arranged in a second pattern and being directly electrically interconnected by interconnections ( 30 ) to input/output pads on said at least one semiconductor device ( 28 ), said chip attach sites disposed opposite said input/output pads, and a plurality of electrically isolated routing circuits ( 26 ) each having a surface comprising a portion of said second side surface and coplanar with the chip attach sites ( 124 ), electrically interconnecting individual combinations of said array of lands ( 14 ) and said array of chip attach sites ( 124 ); a first molding compound ( 18 ), disposed at said first side of said lead frame and between individual lands of said array of lands ( 14 ), having a surface comprising a portion of said first side surface ( 121 ); and a second molding compound ( 36 ) encapsulating said at least one semiconductor device ( 28 ), said array of chip attach sites ( 124 ) and said routing circuits ( 26 ), wherein the lands and chip attach sites are formed from a monolithic electrically conductive structure, the array of lands ( 14 ) has a lateral extent greater than or equal to that of the array of chip attach sites ( 124 ), and the second molding compound does not extend to the first side of the lead frame.