Patent ID: 7213196

Claim:
A data driven clock recovery system comprising: a Viterbi detector for detecting data and tentatively deciding the closest approximation; and a timing loop for performing a timing recovery procedure; a circuit for retrieving the tentative decision in stages; and a combination series and parallel comparison circuit for selecting one value of a set of values for input to the Viterbi detector and for applying said one value to the Viterbi detector, said combination series and parallel comparison circuit comprising: (i) a first portion for processing said set of values in parallel to select a group of said values; and (ii) a second circuit portion, in series with said first circuit portion, for receiving said group of values from said first circuit portion, for selecting said one value from said group, and for applying said one value to the Viterbi detector; and a means for applying said selected one value from the Viterbi decoder to the timing loop for timing recovery.