Patent ID: 8466511

Claim:
A FinFET device, comprising: a semiconductor bulk substrate having a device isolation layer thereon; a fin-shaped active region vertically protruding from the semiconductor bulk substrate between portions of the device isolation layer, the fin-shaped active region having first and second source/drain regions therein and a channel region therebetween; a gate electrode on an upper surface and sidewalls of the channel region; and first and second source/drain contacts on respective upper surfaces of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode, wherein the device isolation layer is recessed to expose sidewalls of the first and second source/drain regions above an upper surface of the semiconductor bulk substrate such that the first and second source/drain contacts are also in contact with the sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode.