Patent ID: 7805581

Claim:
A method of operating a processing device comprising: in response to determining mode information indicates a first mode of operation, performing memory accesses at the processing device by translating N-bit address values stored at a first register to corresponding physical addresses associated with a memory device and performing arithmetic operations at the processing device using N-bit values; in response to determining the mode information indicates a second mode of operation, performing memory accesses at the processing device by translating M-bit address values stored at the first register to corresponding physical addresses associated with the memory device and performing arithmetic operations at the processing device using N-bit values, wherein M is less than N; and in response to determining the mode information indicates a third mode of operation, performing memory accesses at the processing device by translating M-bit address values stored at the first register to corresponding physical addresses associated with the memory device and performing arithmetic operations at the processing device using M-bit values.