Patent ID: 8629012

Claim:
A method of forming an integrated circuit structure, the method comprising: forming a first plurality of III-V semiconductor layers over a substrate, wherein the step of forming the first plurality of III-V semiconductor layers comprises: epitaxially growing a first bottom barrier over the substrate; epitaxially growing a first channel layer over the first bottom barrier; and epitaxially growing a first top barrier over the first channel layer; forming a first field-effect transistor (FET) with a portion of the first channel layer acting as a channel region of the first FET; forming a second plurality of III-V semiconductor layers comprising: epitaxially growing a second bottom barrier over the first plurality of III-V semiconductor layers; epitaxially growing a second channel layer over the second bottom barrier; and epitaxially growing a second top barrier over the second channel layer; and forming a second FET comprising a portion of the second channel layer acting as a channel region of the second FET.