Patent ID: 8614921

Claim:
A nonvolatile semiconductor memory device comprising: a sense amplifier; a bit line coupled to the sense amplifier; a memory cell transistor; a dummy cell transistor; a current generating circuit supplying a test current to a first node, wherein either of the source and the drain of the dummy cell transistor is coupled to the bit line and the other is coupled to the first node, wherein either of the source and the drain of the memory cell transistor is coupled to the bit line and the other is coupled to another node, wherein a gate of said memory cell transistor is coupled to one of control signal lines and a gate of said dummy cell transistor is coupled to another one of control signal lines, and wherein either of the source and the drain of said memory cell transistor and the either of the source and the drain of the dummy cell transistor are electrically connected to each other regardless of the value of both said control signal lines; a first block; and a second block, wherein each of the first block and the second block includes the bit line, the memory cell transistor, the dummy cell transistor, the first node, and the current generating circuit, and wherein in a read operation test, the sense amplifier uses the test current in either of the first block and the second block as a reference current and compares the test current in the other of the first block and the second block with the reference current.