Patent ID: 7287320

Claim:
A method for fabricating a routing layout design, the method comprising: (a) forming a plurality of metal traces on a first routing layer and a second routing layer, comprising: positioning a plurality of first conducting wires and a plurality of second conducting wires on a plurality of horizontal tracks and a plurality of vertical tracks of the first routing layer respectively; and positioning a plurality of third conducting wires and a plurality of fourth conducting wires on a plurality of horizontal tracks and a plurality of vertical tracks of the second routing layer respectively, the third conducting wire on a k th horizontal track of the second routing layer vertically overlapping the first conducting wire on the k th horizontal track of the first routing layer; and (b) positioning a plurality of vias within a via layer disposed between the first and second routing layers for connecting the metal traces on the first and second routing layers according to a first current route defined by a predetermined circuit layout design used for connecting a first node and a second node so as to establish a second current route equivalent to the first current route.