Patent ID: 7214586

Claim:
A method of fabricating nonvolatile memories comprising the steps of: forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on a surface of a semiconductor substrate; patterning the semiconductor substrate vertically to form a control gate and a first device isolation region; implanting ions into the first device isolation region to form common source and drain regions; filling a gap of the first device isolation region to form a first device isolation structure; removing a portion of the buffer nitride layer and a portion of the buffer oxide layer; depositing polysilicon for a word line on the semiconductor substrate, and patterning the semiconductor substrate vertically to form the word line and a second device isolation region; forming sidewall spacers on sidewalls of the control gate and the word line; and forming silicide on the word line.