Patent ID: 8853701

Claim:
A semiconductor device, comprising: a first P-type TFT; a second P-type TFT; a first N-type TFT; and a second N-type TFT, each of which has a channel region that is made of polycrystalline silicon, wherein at least three values out of impurity concentrations d1, d2, d3, and d4 differ from each other, and d1, d2, d3, and d4 satisfy relations of d1<d2 and d3<d4, where d1, d2, d3, and d4 respectively represent p-type impurity concentrations in the respective channel regions in the first P-type TFT, the second P-type TFT, the first N-type TFT, and the second N-type TFT, wherein the first P-type TFT and the second N-type TFT are high-voltage driven TFTs, and the second P-type TFT and the first N-type TFT are low-voltage driven TFTs that control a source-drain voltage lower than a source-drain voltage controlled by the high-voltage driven TFTs, and wherein three values out of d1, d2, d3, and d4 differ from each other, and two values out of d1, d2, d3, and d4 are equal to each other.