Patent ID: 7948024

Claim:
A multi-layered, vertically stacked, nonvolatile memory device, comprising: a plurality of single layers vertically stacked on top of one another, wherein each single layer is formed in a common lateral plane by an alternating arrangement of first semiconductor layers and second semiconductor layers; wherein each first semiconductor layer extends in parallel with a corresponding second semiconductor layer and is separated from the second semiconductor layer by an isolation layer; a first control gate electrode is disposed between the first semiconductor layer and the isolation layer, wherein the first control gate electrode comprises a plurality of first control gate electrodes spaced apart and extending in the first direction, and a second control gate electrode is disposed between the second semiconductor layer and the isolation layer, wherein the second control gate electrode comprises a plurality of second control gate electrodes spaced apart and extending in the first direction, such that the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer; a first charge storing layer is disposed between the first control gate electrode and the first semiconductor layer, and a second charge storing layer is disposed between the second control gate electrode and the second semiconductor layer; a first tunneling insulating layer disposed between the first charge storing layer and the first semiconductor layer; a second tunneling insulating layer disposed between the second charge storing layer and the second semiconductor layer; a first blocking insulating layer disposed between the first charge storing layer and the first control gate electrode; a second blocking insulating layer disposed between the second charge storing layer and the second control gate electrode, wherein the isolation layer comprises a continuous isolation layer extending upward through the multi-layered vertically stacked nonvolatile memory device and separating the plurality of first control gate electrodes and the opposing plurality of second gate electrodes.