Patent ID: 7569495

Claim:
A method for manufacturing a semiconductor device comprising: forming a gate electrode on a semiconductor substrate, the gate electrode comprising a patterned polysilicon layer and having a side wall spacer on a sidewall thereof; forming source and drain regions in the semiconductor substrate using the gate electrode and the side wall spacer as a mask; forming a PMD liner layer on the gate electrode by sequentially forming a first SiO 2 :H layer, a SiON:H layer having a thickness of 50 Å to 200 Å using a plasma of SiH 4 , N 2 O, NH 3 , and He, and a SiN:H layer using a same deposition apparatus as the first SiO 2 :H layer and the SiON:H layer, wherein the PMD liner layer directly contacts the gate electrode and the source and drain regions; forming an interlayer insulating layer above the PMD liner layer by an HDP method employing a plasma of SiH 4 , H 2 , and at least one of N, P, As, and a hydride of Sb or Bi; and removing dangling bonds in the source and drain regions by diffusing hydrogen in the PMD liner layer and the insulating layer to the source and drain regions by N 2 annealing or Ar annealing.