Patent ID: 8169065

Claim:
A circuit structure comprising: at least one chips-first layer, each chips-first layer including: at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface, and a pad mask over the upper surface with at least one opening therein exposing the at least one contact pad at the upper surface; at least one electrically conductive structure comprising at least one side surface, an upper surface and a lower surface; a structural material surrounding the at least one side surface of each chip of the at least one chip of the chips-first layer and surrounding the at least one side surface of each electrically conductive structure of the at least one electrically conductive structure, the structural material having an upper surface substantially coplanar with or parallel to at least one of the upper surface of the at least one chip or the upper surface of the at least one electrically conductive structure, and defining at least a portion of a front surface of the chips-first layer, and a lower surface substantially coplanar with or parallel to at least one of a lower surface of the at least one chip or a lower surface of the at least one electrically conductive structure, and defining at least a portion of a back surface of the chips-first layer, and wherein the structural material comprises a dielectric material, and a majority of the pad mask of the at least one chip of the chips-first layer is uncovered by the structural material; a metallization layer at the front surface of the chips-first layer, the metallization layer residing at least partially on the upper surface of the structural material and at least partially on the pad mask of the at least one chip, and extending over at least one edge of the at least one chip, and wherein the metallization layer electrically connects the at least one contact pad on the upper surface of the at least one chip to the at least one electrically conductive structure, and the structural material and the pad mask over the upper surface of the at least one chip electrically isolate the metallization layer from the at least one edge of the at least one chip; and at least one input/output interconnect structure disposed over the back surface of the at least one chips-first layer, the at least one input/output interconnect structure physically and electrically contacting the lower surface of at least one electrically conductive structure and facilitating electrical connection from the back surface of the at least one chips-first layer to the metallization layer at the front surface of the at least one chips-first layer.