Patent ID: 8510631

Claim:
A multi-channel memory apparatus, comprising: a host interface, arranged to receive and transmit data from and to a host device; a plurality of storage channels, each coupled to a memory device for storing the data; an error correcting module, shared by the storage channels, comprising an error correction code (ECC) engine and a data buffer, and arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices; a multiple memory access module, coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module; and a scrambler module, coupled to the error correcting module, wherein the scrambler module comprises a plurality of scramblers, each of the scramblers is coupled to the storage channel correspondingly and arranged to perform intra-channel disarrangement for the data to be stored into the corresponding memory device and rearrange the scrambled data read out from the corresponding memory device.