Patent ID: 6903594

Claim:
A leaky integrator, comprising: a capacitor-free non-linear delay resistor having a parasitic capacitance; and a capacitor-free amplifier operable to utilize the parasitic capacitance of the delay resistor to provide differing time constants for the rising and falling edges of an output signal produced in response to a pulsed input signal; wherein the delay resistor includes a first transistor and a plurality of second transistors, the first transistor having a source that defines an input for the leaky integrator, a gate tied to a voltage source, and a drain tied to the amplifier; wherein the second transistors include a starting transistor, a terminating transistor, and a plurality of intermediate transistors, each of the second transistors having a source, a drain, and a gate, and wherein: the gates of each of the second transistors are tied to the voltage source; the source of the starting transistor is tied to the drain of the first transistor; the drain of the terminating transistor defines an output of the delay resistor; the source of the terminating transistor is tied to the drain of one intermediate transistors; and the source of all but one intermediate transistor is tied to either the drain of another intermediate transistor while the source of the remaining intermediate transistor is tied to the drain of the starting transistor.