Patent ID: 8199592

Claim:
A semiconductor memory device, comprising: a first memory cell array including, a plurality of first memory cells respectively connected between a plurality of bit lines and a plurality of first word lines, and a plurality of first mismatch cells connected between the plurality of bit lines and at least one first mismatch enable line, at least one of the plurality of first mismatch cells being configured to be selected together with a corresponding first memory cell; a second memory cell array including, a plurality of second memory cells respectively connected between a plurality of inverted bit lines and a plurality of second word lines, and a plurality of second mismatch cells connected between the plurality of inverted bit lines and at least one second mismatch enable line, at least one of the plurality of second mismatch cells being configured to be selected together with a corresponding second memory cell; and a sense amplifier configured to detect a voltage difference between the bit lines and the inverted bit lines in response to a sense enable signal, the sense amplifier being further configured to amplify the voltage difference between the bit lines and the inverted bit lines to one of a source voltage level and a ground voltage level.