Patent ID: 8253457

Claim:
A delay locked loop (DLL) comprising: a first delay block comprising a first plurality of delay elements, but configurable to couple only a first subset of delay elements in the first plurality of delay elements between a first input node and a first output node of the first delay block, wherein the first input node and the first output node respectively represent an input terminal and an output terminal of the DLL, wherein the DLL is coupled to receive an input signal on the input terminal, the DLL to generate a first delayed signal with a first delay with respect to the input signal on the output terminal; a second delay block comprising a second plurality of delay elements, but configurable to couple only a second subset of delay elements in the second plurality of delay elements between a second input node and a second output node of the second delay block, wherein the second input node is coupled to the first output node to couple the first subset of delay elements and the second subset of delay elements in series, wherein the second delay block provides a second delayed signal on the second output node; and a phase discriminator coupled to receive the input signal and the second delayed signal as inputs, and to generate an error signal representing a phase difference between a phase of the input signal and a phase of the second delayed signal, wherein a control signal derived from the error signal is coupled to each delay element in the first subset of delay elements and the second subset of delay elements to control a delay provided by the corresponding delay element; wherein the first delay block receives a first configuration value from a component external to the DLL, wherein the number of delay elements in the first subset of delay elements equals the first configuration value, wherein the second delay block receives a second configuration value from the component external to the DLL, wherein the number of delay elements in the second subset of delay elements equals the second configuration value, wherein the first configuration value and the second configuration value are selected to provide the first delayed signal with the first delay on the first output node.