Patent ID: 8566668

Claim:
A communication terminal comprising: a decoding circuit configured to decode data that has been encoded according to a coding scheme defining a parity check matrix, wherein the parity check matrix defines parity equations and edges between bit nodes and check nodes, the decoding circuit comprising: an input buffer configured to store channel soft information; a bit node processing (BNP) accumulation module configured to read the channel soft information, to access extrinsic information for edges, and to generate accumulated values for edges by summing the channel soft information and the extrinsic information for edges; a controller module configured to reformat the accumulated values into an index and a respective set of candidate values for each edge, each index identifying which one of the candidate values in the respective set to apply to the edge for that index; an edge memory configured to store the index and the respective set of candidate values for each edge; a BNP calculation module configured to access extrinsic information for edges of a previous check node processing (CNP) iteration and to generate extrinsic information inputs for edges for a new CNP iteration by subtracting the extrinsic information for edges of the previous CNP iteration from the reformatted accumulated values for edges; a CNP processor module configured to generate output extrinsic information for edges using the extrinsic information inputs for edges generated by the BNP calculation module; and an output buffer configured to store output data from the BNP accumulation module when a determination is made that all parity equations defined by the parity check matrix are satisfied.