Patent ID: 6956921

Claim:
A clock and data recovery circuit comprising: a first data input receiving a data signal of a first frequency; a clock defining a timing signal of a second frequency; a phase generator dividing a cycle of the timing signal into a number of N clock phases; a data sampling component sampling a portion of said data signal causing a logic output statement based on a truth table, said data sampling component comprising a buffer component for buffering said data signal, said buffer component triggered by a first clock phase i, a second clock phase j and a third clock phase k, resulting in a buffering of the state of said data signal at said clock phases i, j, and k and wherein the clock phases i, j, and k are interdependent by at least one of the equations: j=i+N/ 2 −M and k=i+N/ 2 if i≦N/ 2 and j=i−N/ 2 −M and k=i−N/ 2+ M if i>N/ 2 with a parameter M selectable within 0<M<N/2, and a phase detector coupled to said buffer component; and a phase selector coupled to said data sampling component.