Patent ID: 7356111

Claim:
A processing system comprising: a reference clock generator configured to generate an F(in) reference signal having an F(in) frequency; a phase-locked loop (PLL) frequency synthesizer configured to be tuned in small step sizes comprising: a PLL circuit comprising; i) a PLL core configured to receive said F(in) reference signal and generate a plurality of multiphase output signals having an F2 frequency, where F2=F(in) (P+Î”p), and ii) a feedback frequency divider configured to receive said plurality of multiphase output signals and generate a feedback signal having a frequency F2/(P+Î”p) wherein P is an integer and Î”p is a fractional value less than 1, and wherein said feedback frequency divider comprises a first counter circuit and a first switching circuit configured to receive said plurality of multiphase output signals and selectively apply selected ones of said plurality of multiphase output signals to an input of said first counter circuit; an output divider configured to receive said plurality of multiphase output signals and generate an output signal, wherein said output divider comprises a second counter circuit and a second switching circuit configured to receive said plurality of multiphase output signals and selectively apply selected ones of said plurality of multiphase output signals to an input of said second counter circuit; and a clock controller configured to control said reference clock generator and to monitor one of said multiphase output signals, wherein said clock controller is configured to tune said F2 frequency by modifying P and Î”p.