Patent ID: 7126370

Claim:
A power gated semiconductor integrated circuit comprising: logic circuit to be power gated, said logic circuit having a virtual ground rail; footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, wherein said virtual rail voltage clamp comprises: N max-VC NFETs, where N max-VC is a maximum number of footer devices needed for said virtual ground rail to be substantially at a voltage value V clamp , where V clamp is a desired steady state voltage at the virtual ground rail in a power saving state; and N max-VC latches, each latch coupled to and controlling a respective one of said N max-VC NFETs; and wherein said footer device comprises: (N f −N max-VC ) NFETS, where (N f −N max-VC ) is a number of footers required to produce a certain amount of leakage reduction in said logic circuit.