Patent ID: 8154941

Claim:
A non-volatile semiconductor memory device comprising a memory cell array and a control circuit for controlling the memory cell array, the memory cell array comprising a plurality of word-lines, a plurality of bit-lines, and a plurality of memory cells arranged at the intersections of the word-lines and the bit-lines, each memory cell comprising an electrically programmable antifuse element, the control circuit being adapted to be able to perform: as a first step, applying a programming voltage to one of the word-lines while applying a ground voltage to bit-lines each connected to respective selected memory cells to be programmed, thereby concurrently applying the programming voltage to a plurality of the selected memory cells; and as a second step after the first step, keeping one of the word-lines at the programming voltage while concurrently reading the electrical states of a plurality of the selected memory cells, and according to the electrical states of a plurality of the memory cells, applying the ground voltage again to a bit-line connected to an unprogrammed selected memory cell after the first step, and applying a voltage higher than the ground voltage to a bit-line connected to a programmed selected memory cell after the first step.