Patent ID: 6977930

Claim:
An apparatus for switching packets, each packet having a header portion, a corresponding tail portion, and a class of service indicator, said apparatus comprising: a pipelined switch comprising: a plurality of packet header buffers (PHBs); an equal plurality of PHB pointers, each said PHB pointer pointing to a corresponding PHB; and an equal plurality of pipeline stage circuits connected in a sequence, comprising at least a first stage circuit and a last stage circuit, wherein: each said stage circuit begins an operation substantially simultaneously with each other; each said stage circuit passes data to a next stage circuit in said sequence when every said operation performed by all said stage circuits is completed; said first stage circuit reads said header portion and stores said header portion in said corresponding PHB using said corresponding PHB pointer; and said last stage circuit outputs a modified header portion; and a receive buffer manager (RBM) comprising: a joining circuit connected to said pipelined switch wherein said modified header portion and said corresponding tail portion are joined to form a modified packet; a receive queue manager connected to said joining circuit that buffers said modified packet in a receive packet buffer and enqueues said modified packet using said class of service indicator and a plurality of receive queues; and a dequeue circuit connected to said receive queue manager and said receive packet buffer, wherein said dequeue circuit uses said class of service indicator to dequeue said modified packet to a switch fabric.