Patent ID: 7705391

Claim:
A semiconductor device including a plurality of memory cells, comprising: a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a top surface of a semiconductor substrate and having an upper portion which is narrower in a channel width direction than a lower portion, the lower portion including a largest-width portion which is largest in width with respect to the channel width direction; an element isolation insulating film which is formed between adjacent ones of the floating gate electrodes aligned in the channel width direction, the element isolation insulating film having a bottom surface below the top surface of the semiconductor substrate; an interelectrode insulating film formed on the floating gate electrodes and the element isolation insulating film; and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and the element isolation insulating film and partially buried between the floating gate electrodes opposing each other, wherein at least a part of a sidewall of said largest-width portion of each of the floating gate electrodes is in direct contact with a left or right sidewall of the element isolation insulating film, and a width, in the channel width direction, of the upper portion of the floating gate electrode is smaller than a width, in the channel width direction, of a portion of the floating gate electrode where the floating gate electrode is in contact with the tunnel insulating film.