Patent ID: 7622757

Claim:
A semiconductor device, comprising; a plurality of semiconductor elements; and a first wire and a second wire provided to connect said semiconductor elements in parallel, wherein said first wire and said second wire include respective wires in multiple wiring layers, wherein each wiring layer includes said first wire and said second wire arranged alternately and in parallel, wherein said wires intersect each other in adjacent wiring layers, and said first wires are connected with each other through a via-connection at an intersection of said first wires and said second wires are connected with each other through a via-connection at an intersection of said second wires, and wherein when L total denotes a total length in a wire stretching direction of an effective portion of the elements, the total length L total of the elements is set to have a value of: L total <j EM (max)·t·i( μm )/2, where t denotes a thickness of the wires in a highest wiring layer, i ( μm ) denotes a current flowing in the elements per unit length (1 μm) and j EM (max) denotes an Electro-Migration tolerance of a material of the wires in the highest wiring layer.