Patent ID: 7193922

Claim:
A semiconductor integrated circuit comprising: a first memory block, further comprising: first memory cells; first bit lines connected to the first memory cells; and first word lines connected to the first memory cells; and a second memory block, further comprising: second memory cells, a type of which are different from that of the first memory cells and operating independently of the first memory block; second bit lines connected to the second memory cells; and second word lines connected to the second memory cells, wherein said second memory cells each have an area 2 a times an area of each of said first memory cells, wherein a is a positive integer; and further wherein said first and second bit lines are wired in a same direction; said first and second word lines are wired in a same direction; said first memory cells are memory cells of a dynamic RAM; said second memory cells are memory cells of a static RAM; said first memory block includes a sense amplifier row which amplifies data signals on said first bit lines; and said second memory block includes a redundancy memory cell row land a connection area which connects a well region with a power supply line, the well region being formed on a semiconductor substrate.