Patent ID: 7462910

Claim:
A power MOSFET having reduced on resistance comprising: a P+ conductivity substrate; an epitaxially deposited N+ conductivity layer deposited atop said P+ substrate to form an epitaxial layer having a substantially uniform concentration of N type dopants throughout its volume; a plurality of spaced stripe trenches having vertical walls extending through said epitaxial layer into said P+ conductivity substrate; a thin gate oxide on said vertical walls and conductive polysilicon with a P type conductivity deposited into said trenches to define a polysilicon gate; P+ concentration source region stripes formed adjacent the walls of each of said trenches and diffused into the top of said epitaxial layer; a plurality of spaced notches extending through said source regions and exposing said epitaxially deposited layer; an N++ region formed in said N+ epitaxially deposited layer at bottom of each notch; a source contact connected to at least said source regions; and a drain contact made of metal and connected to a bottom surface of said substrate, wherein the doping of said N+ epitaxially deposited layer allows reverse voltage to be blocked therein and wherein said source contact extends through said plurality of notches and is connected to each said N++ region.