Patent ID: 8836396

Claim:
A PWM (pulse width modulation) circuit for generating a PWM output signal having an output frequency in response to a PWM input signal having an input frequency such that a duty cycle of the PWM output signal is precisely equal to a duty cycle of the PWM input signal, comprising: (a) an algebraic summing circuit for producing an increment signal if a value of the PWM input signal exceeds a corresponding value of the PWM output signal and for producing a decrement signal if the value of the PWM input signal is less than the corresponding value of the PWM output signal; (b) an integrating circuit for generating a first duty cycle signal representative of the duty cycle of the PWM input signal, the integrating circuit producing an increase in value of the first duty cycle signal in response to each increment signal produced by the algebraic summing circuit and producing a decrease in value of the first duty cycle signal in response to each decrement signal produced by the algebraic summing circuit; (c) a PWM generator circuit for generating the PWM output signal in response to the first duty cycle signal; and (d) wherein the PWM circuit operates to cause the duty cycle of the PWM output signal to approach and become substantially equal to the duty cycle of the first PWM signal, an interpolation circuitry for generating a second duty cycle signal which is an interpolated representation of the first duty cycle signal, wherein the PWM generator circuit includes a ramp generator circuit for generating a ramp signal in response to the PWM output signal and a comparator for comparing the ramp signal to the first duty cycle signal and causing the PWM output signal to have a duty cycle determined by the first duty cycle signal, wherein the ramp generator circuit generates a digital representation of the ramp signal and the comparator is a digital comparator.