Patent ID: 7266735

Claim:
A semiconductor device comprising: a memory which stores data configured with data bits; an ECC circuit which corrects a bit error of the data read out from the memory and generates correction data bits; a memory test circuit which receives all data bits read out from the memory including the correction data bits and tests whether a read operation of all the data bits with respect to the memory is performed correctly; a mode setting circuit for setting the ECC circuit and the memory test circuit to a test mode; a pseudo error generator circuit which generates a pseudo error for at least one bit configuring the data bits read out from the memory in a test mode; and a supplying circuit for supplying the data bits including the pseudo error bit generated in the pseudo error generator circuit to the ECC circuit for obtaining error-corrected data bits including a corrected bit corresponding to the pseudo error bit, whereby testing whether the read operation of all the data bits with respect to the memory is performed correctly by supplying the error-corrected data bits including the corrected bit corresponding to the pseudo error bit to the memory test circuit, and testing whether data correction in the ECC circuit is performed correctly by supplying the data bits including the pseudo error bit to the ECC circuit in the test mode.