Patent ID: 7248538

Claim:
A semiconductor memory device comprising: an interface unit that executes transmission/reception of data with an external circuit; a data memory unit including a write data line, a read-out data line, a data control unit connected to the interface unit via the write data line, and a memory block connected to the data control unit; and a read-out latch block that is connected between the read-out data line and the interface unit, wherein the data control unit outputs data, which is read out of the memory block, to the read-out data line with a trailing edge of a clock being used as a trigger, the read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger, and the interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.