Patent ID: 7895557

Claim:
A method in a data processing system for assigning buffer and layer positions within a multi-level integrated circuit design layout, said method comprising: for every driver and all receivers having an interconnection therewith: the data processing system inserting sufficient buffers within said interconnection to obtain a required signal arrival time; where sufficient buffers can not be inserted, the data processing system promoting at least a portion of said interconnection to a higher level within said multi-level integrated circuit design; the data processing system additionally promoting each portion of said interconnection to a higher level within said multi-level integrated circuit design so long as each promotion results in a signal arrival time savings which exceeds 5 picoseconds; and thereafter, for every driver and all receivers having an interconnection there between: the data processing system selectively demoting each interconnection between a driver and a receiver to a lower level only if said required signal arrival time can still be satisfied.