Patent ID: 8354671

Claim:
An integrated circuit wafer comprising: a gate dielectric thickness test structure configured to determine a gate dielectric thickness; and an integrated circuit (IC) having a Vgg supply circuit configured to establish a gate bias voltage based on a specified reliability lifetime and the gate dielectric thickness determined by the gate dielectric thickness test structure; wherein the gate dielectric thickness test structure includes: a test pad, an NMOS gate leakage current device connected to the test pad through a first switch, and a PMOS gate leakage current device connected to the test pad through a second switch; wherein the gate dielectric thickness test structure is configured to determine the gate dielectric thickness based at least on a leakage current of the NMOS gate leakage current device, or a leakage current of the PMOS gate leakage current device, measured at the test pad; and wherein the integrated circuit wafer or the IC includes the gate dielectric thickness test structure.