Patent ID: 8239806

Claim:
A routing method comprising steps of: (a) receiving in a processor an identification of a plurality of circuit components to be included in an integrated circuit (IC) layout; (b) generating data within the processor representing a first pattern to connect two of the plurality of circuit components, the first pattern having a plurality of segments, such that at least two segments of the plurality of segments have lengthwise directions perpendicular to each other; (c) reserving at least one pattern-free region, wider than a minimum spacing between parallel lines, adjacent to at least one segment of the at least two of the plurality of segments to prevent the processor from generating another pattern occupying or overlapping the at least one pattern-free region without increasing the minimum spacing throughout the entire IC layout; (d) generating data within the processor representing one or more additional patterns near the first pattern, such that none of the one or more additional patterns is formed in the at least one pattern-free region, and the first pattern and the one or more additional patterns form a double-patterning compliant set of patterns; and (e) outputting the double-patterning compliant set of patterns from the processor to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.