Patent ID: 6928535

Claim:
A signal processing device comprising: a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal; a controller for giving the control signal to the processors; and a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other; and wherein each of the plurality of processing elements comprises: a memory circuit for storing data; an arithmetic unit for receiving at least data read out from the memory circuit and performs an arithmetic operation; and a data input/output unit, connected among the memory circuit, the arithmetic unit and one of the plurality of data transfer lines, for transmitting and receiving data among the memory circuit, the arithmetic unit and the one of the data transfer lines, the data input/output unit including a data input/output circuit, an output circuit having an input node connected to the data input/output circuit and an output node connected to the one data transfer line, and a switch circuit for taking in data, the switch circuit having one end connected to the data input/output circuit and the other end connected to the one data transfer line, wherein the output circuit within the processing element connected to the one data transfer line outputs data output from the associated data input/output circuit to the one data transfer line, and the switch circuit within at least one of the processing elements connected to the one data transfer line simultaneously inputs data on the one data transfer line to the associated data input/output circuit; wherein the output circuit is a three-value output circuit, an output from which takes one of a logic 0 state, a logic 1 state and a high-impedance state, each of the plurality of data transfer lines comprises a single wiring for transferring one-bit data, and the output circuit within one of the processing elements connected to each of the plurality of data transfer lines outputs one of logic 0 data and logic 1 data to the data transfer line, the output circuits within the remaining ones of the processing elements connected to the same data transfer line takes the high-impedance state, and the switch circuit within at least one of the remaining ones of the processing elements connected to the same data transfer line simultaneously takes in data on the data transfer line.