Patent ID: 8893070

Claim:
A method for pin placement for repeated blocks associated with an integrated circuit, the method comprising: receiving, at one or more computer systems, information specifying an integrated circuit that includes a plurality of instances of a repeated block, at least some of the plurality of instances of the repeated block having different I/O pin placements; superimposing, with one or more processors associated with the one or more computer systems, a set of nodes associated with the plurality of instances of a repeated block that an I/O of the repeated block contacts, each node representing a first placement for a corresponding instance of a repeated block for an I/O pin for the I/O of the repeated block; determining, with the one or more processors associated with the one or more computer systems, connections between the superimposed nodes and the I/O of the repeated block using a minimum spanning tree analysis; and generating, with the one or more processors associated with the one or more computer systems, information placing the I/O pin for the I/O of the repeated block similarly at each of the plurality of instances of a repeated block based on the connections.