Patent ID: 8106505

Claim:
An assembly, comprising: a chip stack comprising plural chips including plural integrated circuits, a chip of said plural chips including an integrated circuit and a silicon die formed on said integrated circuit of said chip; a casing including an integrated circuit, the integrated circuit comprising plural active elements, an upper portion formed on a side of said chip, and a lower portion formed on another side of said chip, said upper and lower portions of said casing forming a coolant inlet for transporting coolant into said chip stack, and a coolant outlet for transporting said coolant out of said chip stack; a first plurality of through-wafer vias for interconnecting the chips in the chip-stack; a second plurality of through-wafer vias for electrically connecting said integrated circuit of said chip and said integrated circuit of said casing, said second plurality of through-wafer vias being formed in silicon pillars of said silicon die and comprising: first vias that electrically connect said integrated circuit of said chip to said upper casing; and second vias that electrically connect said integrated circuit of said chip to said lower casing, said first and second vias being alternately formed such that an interleaving input/output (I/O) is formed above and below said chip; plural cards connected to said casing for electrically connecting said casing to a system board, said plural cards comprising: an upper card connected to said upper portion of said casing by plural solder balls which are aligned with said plural through-wafer vias such that said plural through-wafer vias are electrically connected to said upper card; and a lower card connected to said lower portion of said casing by plural solder balls which are aligned with said plural through-wafer vias such that said plural through-wafer vias are electrically connected to said lower card; and a fluid channel formed between an upper surface of a silicon die formed on a first chip in said chip stack, and a lower surface of a second chip formed above said first chip in said chip stack.