Patent ID: 7507637

Claim:
A method of manufacturing a wafer level stack package, comprising the steps of: preparing a first wafer with first via patterns projecting from a front side thereof and a second wafer with second via patterns projecting from a front side thereof; attaching the second wafer to the first wafer such that the front sides of the first and second wafers face each other and the first and second via patterns are connected to each other; grinding a back side of the second wafer such that lower ends of the second via patterns are exposed; projecting the lower ends of the second via patterns by etching the back side of the ground second wafer; adding a protective layer to the backside of the second wafer if the second wafer is a last layer added; grinding a back side of the first wafer such that lower ends of the first via patterns are exposed; projecting the lower ends of the first via patterns by etching the back side of the ground first wafer to form a wafer level stack structure; removing the protective layer from the last layer after grinding the backside of the first wafer and after protecting the lower ends of the first via patterns from the back side of the ground first wafer; forming a chip level stack structure by sawing the wafer level stack structure when the lower ends of the first via patterns project from the back side of the first wafer of the wafer level stack structure and when the lower ends of the second via patterns project from the back side of the second wafer of the wafer level stack structure; attaching the chip level stack structure to a substrate with electrode terminals such that the first via patterns are connected to the electrode terminals; molding an upper surface of the substrate including the chip level stack structure using a molding material; and attaching solder balls to the lower surface of the substrate.