Patent ID: 7649248

Claim:
A stack package comprising: a plurality of unit packages, each of the unit packages including a first substrate having a top surface and a bottom surface; a first chip mounted on the top surface of the first substrate, the first chip having an active surface and a back surface; a plurality of conductive supports provided on the top surface of the first substrate and electrically connected to the first chip; a second substrate provided on and electrically connected to the conductive supports, the second substrate having a top surface and a bottom surface; an encapsulant sealing the first chip and the conductive supports and exposing the top surface of the second substrate; and a plurality of conductive bumps provided on the bottom surface of the first substrate; wherein the conductive bumps of an upper unit package is connected to the second substrate of a lower unit package, and wherein the second substrate has a window, the width of the window is larger than the width of the first chip.