Patent ID: 7605609

Claim:
An integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain, wherein: switching speed of the level shifter is higher in the high-speed mode than in the low-power mode; power consumption of the level shifter is lower in the low-power mode than in the high-speed mode; and the programmable level shifter comprises: first and second devices that are configured as a current-mirror amplifier in the high-speed mode and as a cross-coupled latch in the low-power mode; first, second, third, and fourth n-type devices, wherein: the first and third n-type devices are connected in parallel; the second and fourth n-type devices are connected in parallel; in the high-speed mode, the third and fourth n-type devices are disabled; and in the low-power mode, the third and fourth n-type devices are enabled, such that (1) the first and third n-type devices form a first relatively large effective n-type device and (2) the second and fourth n-type devices form a second relatively large effective n-type device.