Patent ID: 8543963

Claim:
A computer-executed method for optimizing a circuit design's leakage power, the method comprising: determining leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on a difference between the logic gate's leakage power and a leakage power of another logic gate in a library; determining a processing order for processing the logic gates based at least on the leakage potentials; and optimizing, by computer, the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves: selecting a leakage-power-reducing transformation to apply to one or more logic gates, and in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.