Patent ID: 8592295

Claim:
A method of forming a non-planar semiconductor device comprising: forming at least one semiconductor wire region within a bulk semiconductor substrate; providing a sacrificial spacer to vertical sidewalls of said at least one semiconductor wire region; removing portions of the bulk semiconductor substrate to provide an undercut beneath the sacrificial spacer and a vertical semiconductor pillar portion directly beneath the at least one semiconductor wire region; performing an oxidation process converting a recessed surface of the bulk semiconductor substrate into a horizontal semiconductor oxide portion, and converting the vertical semiconductor pillar portion into a vertical semiconductor oxide pillar portion; removing at least said vertical semiconductor oxide pillar portion and said sacrificial spacer forming at least one suspended semiconductor nanowire, while retaining at least a portion of said horizontal semiconductor oxide portion on said recessed surface of said semiconductor substrate, wherein said at least one suspended semiconductor nanowire has an end segment attached to a first semiconductor pad region and another end segment attached to a second semiconductor pad region, said first and second semiconductor pad regions are located above and are in direct contact with a non-recessed portion of the bulk semiconductor substrate; performing a hydrogen anneal on said at least one suspended semiconductor nanowire; providing a gate surrounding a central portion of said at least one suspended semiconductor nanowire; and forming a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite said first side of the gate.