Patent ID: 8184219

Claim:
A stacked storage capacitor structure for a thin film transistor liquid crystal display having a plurality of pixels, each pixel having a pixel area, wherein at least some of the pixels have a storage capacitor formed substantially within the pixel area and associated with the stacked storage capacitor structure, the stacked storage capacitor structure comprising: a first storage capacitor having a first plate formed by a first electrically conductive layer, a second plate formed by a second electrically conductive layer and a dielectric formed by a first insulator layer positioned between the first electrically conductive layer and the second electrically conductive layer; and a second storage capacitor having a first plate formed by a third electrically conductive layer, a second plate formed by the second electrically conductive layer and a dielectric formed by a second insulator layer positioned between the first and second plates, wherein the first electrically conductive layer and the third electrically conductive layer are electrically connected to each other so that the first and second storage capacitors are electrically connected in parallel, and wherein the second electrically conductive layer is positioned between the first electrically conductive layer and the third electrically conductive layer, wherein each of said at least some of the pixels has a gate line disposed at one edge section of the pixel area for controlling electric charges in the first storage capacitor and the second storage capacitor, and wherein the stacked storage capacitor structure is formed substantially in said one edge section, and wherein each of said at least some of the pixels comprises a pixel electrode located within the pixel area adjacent to said one edge section in a non-overlapping manner, and the second electrically conductive layer comprises a first section having a first width and an extended section extending from the first section in a direction different from that of the gate line, the extended section having second width smaller than the first width, the extended section of the second electrically conductive layer arranged to provide electrical contact with the pixel electrode at a connection point within the pixel electrode.