Patent ID: 7312737

Claim:
A digital-to-analog converting system clocked by a clock signal having a clock period, said system comprising: a first digital-to-analog converter connected to receive a first digital data stream and operable to convert said first digital data stream to a first analog signal; first timing circuitry connected to receive said first analog signal and operable to output said first analog signal for a first half of said clock period; a second digital-to-analog converter connected to receive a second digital data stream and operable to convert said second digital data stream to a second analog signal; second timing circuitry connected to receive said second analog signal and operable to output said second analog signal for a second half of said clock period; and a combiner operable to combine said first analog signal and second analog signal to produce an interleaved analog signal; wherein said first and second digital data streams are vary as a function of time and said second digital data stream is independent of said first digital data stream.