Patent ID: 7141482

Claim:
A method of making a memory cell for a non-volatile semiconductor device, comprising: providing a dielectric layer having a planar surface and at least one opening formed therein; forming a first electrode layer over the dielectric layer planar surface and in the opening; forming a controllably conductive media comprising an active layer and a passive layer over the first electrode and in the opening, the active layer having at least two relatively stable oxidation states and comprising at least one of a chalcogenide, transition metal oxide, and an organic semiconductor material, the passive layer comprising at least one conductivity-facilitating compound having at least two relatively stable oxidation states, wherein the passive layer and the active layer are selected so that energy bands of the two relatively stable oxidation states of the passive layer match with energy bands of the two relatively stable oxidation states of the active layer; forming a second electrode layer over the controllably conductive media and in the opening; and removing the first and second electrode layers and controllably conductive media on the dielectric layer planar surface so that the remaining second electrode surface in the opening is co-planar with the dielectric layer planar surface.