Patent ID: 7085866

Claim:
A hierarchically arranged multi-processor system, comprising: a leaf bus having a plurality of leaf level processors thereon, the leaf bus connected to a first bus cycle assignment unit that provides an interface to a first shared memory, wherein the first bus cycle assignment unit allocates slots to each of the leaf level processors to control a timing with which the leaf level processors use the leaf bus to access the first shared memory; and a root bus having a plurality of root level processors thereon, the root bus connected to the first bus cycle assignment unit to allow the root level processors to access the first shared memory without use of the leaf bus, and connected to a second bus cycle assignment unit that allocates slots to each of the root level processors to control a timing with which the root level processors use the root bus to access at least the first shared memory; wherein each root level processor has a single CPU, and the root level processors operate at a higher level in a control hierarchy than the leaf level processors.