Patent ID: 8155236

Claim:
A data receiver circuit comprising: a transmission line comprising a plurality of segments of predetermined lengths, said transmission line to receive a reference signal and to propagate said reference signal for the predetermined lengths, said transmission line further comprising: a first tab to extract, from a first segment of said transmission line, a first delayed signal and; a second tab to extract, from a second segment of said transmission line, a second delayed signal, wherein each tab is situated at the end of each segment of said transmission line; a sampling circuit, coupled to said transmission line, to receive a serial bit stream and to generate samples of said serial bit stream at times specified by said first delayed signal and at times specified by said second delayed signal, wherein a sampling rate is based on said predetermined lengths of the first and second segments of said transmission line; a phase detector to detect a phase difference between said reference signal at an input to said transmission line and said reference signal at an output of said transmission line; a filter, coupled to said phase detector, to receive said phase difference and to generate a value in accordance with a loop filter parameter; and a capacitance control device, coupled to said transmission line and coupled to receive said value, to adjust the capacitance of said transmission line.