Patent ID: 8198659

Claim:
An apparatus comprising: a gate electrode of a transistor over a semiconductor substrate; a first conductive type second ion implantation region forming two separate wells at sides of said gate electrode; a first conductive type first ion implantation region forming a source or a drain of the transistor and surrounding one of the wells of said first conductive type second ion implantation region, wherein said first conductive type second ion implantation region comprises a lower concentration than said first conductive type first ion implantation region; a gate spacer at sidewalls of said gate electrode, said gate spacer and said first conductive type second ion implantation region spaced from each other, wherein a portion of said first conductive type first ion implantation region is interposed between said gate spacer and said first conductive type second ion implantation region; a first device isolation layer that is gap-filled in a trench formed over said semiconductor substrate, said first device isolation layer and said first conductive type second ion implantation region spaced from each other, wherein said first conductive type first ion implantation region contacts said gate spacer and each edge of said device first isolation layer; and a salicide layer over at least one of an upper surface of said gate electrode, over said first ion implantation region and said second ion implantation region.