Patent ID: 7155685

Claim:
An optimizing designing apparatus of an integrated circuit for designing a circuit, comprising: operation region judging means which carries out analysis of operation of said circuit, which extracts node voltage of the circuit and transistor current Ids of the circuit obtained as a result of the analysis, which converts the extracted node voltage into voltages Vds and Vgs between nodes of a transistor using a circuit topology information, and which judges an operation region including a linear region and a saturation region using threshold voltage, the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor; operation region analysis means which carries out DC analysis or TRAN analysis of the circuit, which extracts node voltage of the circuit and the transistor current Ids of the circuit obtained as a result of the analysis by the operation region analysis means, which converts the extracted node voltage into the voltages Vds and Vgs between the nodes of the transistor using the circuit topology information, and which displays linear characteristics including Ids-Vgs characteristics and saturation characteristics including Ids-Vds characteristics using the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor; and SWEEP sensitivity analysis means which displays variation in output characteristics of said circuit when the circuit parameter including gate width W and gate length L is varied by ±α(%).