Patent ID: 7482850

Claim:
A delay locked loop circuit comprising: a delay locked loop element; and a control circuit which outputs a control signal to control an operation of the delay locked loop element, wherein the delay locked loop element is configured to receive a reference signal and the control signal, and is configured to output an output signal, wherein the control circuit is configured to receive the reference signal and the output signal, and is configured to output the control signal, wherein the control circuit includes an exclusive OR circuit and a counter, wherein the exclusive OR circuit is configured to receive the reference signal and the output signal, and is configured to provide an output to the counter, and wherein the control circuit is configured to count the output of the exclusive OR circuit using the counter, to output a first set signal by which the delay locked loop element is not operated by the control signal until the number of counts of the counter reaches a set value, and to output a second set signal by which the delay locked loop element is operated by the control signal after the number of counts of the counter reaches the set value.