Patent ID: 8242607

Claim:
An integrated circuit package system comprising: a first integrated circuit die having an interconnect proximal side; a second integrated circuit die over the first integrated circuit die, the second integrated circuit die having an interconnect distal side and an interconnect proximal side offset in a first direction from the interconnect proximal side of the first integrated circuit die; an interdie layer over the second integrated circuit die; a third integrated circuit die over the interdie layer, the third integrated circuit die having an interconnect proximal side aligned with the interconnect distal side of the second integrated circuit die, and the interdie layer is recessed from the interconnect proximal side of the second integrated circuit die and the interconnect proximal side of the third integrated circuit die; a fourth integrated circuit die over the third integrated circuit die, the fourth integrated circuit die having an interconnect proximal side offset in a second direction from the interconnect proximal side of the third integrated circuit die with the second direction opposite to the first direction, wherein the first, second, third, and fourth integrated circuit dies are a same size; a lower interconnect connected to an upper surface near the interconnect proximal side of the first integrated circuit die and an upper surface near the interconnect proximal side of the second integrated circuit die; an upper interconnect connected to an upper surface near the interconnect proximal side of the third integrated circuit die and an upper surface near the interconnect proximal side of the fourth integrated circuit die; and a single package encapsulant in direct contact with the first integrated circuit die, the second integrated circuit die, the third integrated circuit die, the fourth integrated circuit die, and the interdie layer.