Patent ID: 7888255

Claim:
A method of forming an antifuse and a conductive interconnect, comprising: forming a first via opening to a first node location and a second via opening to a second node location, the first and second node locations being spaced apart from one another on a substrate; after forming the first and second via openings, masking the first node location from being exposed through the first via opening and to leave the second node location outwardly exposed through the second via opening; while masking the first node location, forming an antifuse dielectric within the second via opening over the exposed second node location and not within the first via opening over the first node location; after forming the antifuse dielectric, unmasking the first node location to expose the first node location through the first via opening; and after said unmasking of the first node location, depositing conductive material to within the first via opening in conductive connection with the first node location and forming a conductive interconnect within the first via opening to the first node location and to within the second via opening over the antifuse dielectric and forming an antifuse comprising the second node location, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening.