Patent ID: 7851136

Claim:
An integrated circuit fabrication method comprising: patterning a first photoresist layer from a photoresist material disposed over a target material by exposing the first photoresist layer to radiation having a deep ultraviolet wavelength, resulting in an exposed first photoresist layer; developing the exposed first photoresist layer into a patterned first photoresist layer; stabilizing the patterned first photoresist layer by exposing the patterned first photoresist layer to radiation having a wavelength for which the patterned first photoresist layer is highly absorptive, resulting in stabilized photoresist features; thereafter, forming a second photoresist layer over the target material and over the stabilized photoresist features, the second photoresist layer being formed from the same photoresist material used for the first photoresist layer; patterning the second photoresist layer, while the stabilized photoresist features remain intact, by exposing the second photoresist layer to radiation, resulting in an exposed second photoresist layer; developing the exposed second photoresist layer into a patterned second photoresist layer, while the stabilized photoresist features remain intact, wherein the patterned second photoresist layer has second photoresist features defined therein, wherein the stabilized photoresist features and the second photoresist features together define a combined mask for the target material, and wherein the stabilized photoresist features and the second photoresist features are separated such that they define unprotected areas of the target material therebetween; thereafter, utilizing the combined mask during a subsequent process step for the unprotected areas of the target material; and thereafter, removing the stabilized photoresist features and the second photoresist features from the target material.