Patent ID: 7057236

Claim:
A semiconductor device, comprising on a same semiconductor substrate, a first MIS type transistor and a second MIS type transistor having a same conductivity type as the first MIS type transistor, wherein: the first MIS type transistor comprises: a first gate insulating film formed on a first transistor-forming region in the semiconductor substrate; a first gate electrode formed on the first gate insulating film; first sidewall insulating films formed on side surfaces of the first gate electrode; first low concentration impurity regions formed underneath the first sidewall insulating films in the first transistor-forming region; first high concentration impurity regions formed outside the first gate electrode in the first transistor-forming region so as to adjoin to the first low concentration impurity regions; and first metal silicide layers formed on each surface of the first high concentration impurity regions using the first sidewall insulating films as a mask, and the second MIS type transistor comprises: a second gate insulating film formed on a second transistor-forming region in the semiconductor substrate and having a thickness thinner than the first gate insulating film; a second gate electrode formed on the second gate insulating film; second sidewall insulating films formed on side surfaces of the second gate electrode; second low concentration impurity regions formed underneath the second sidewall insulating films in the second transistor-forming region; second high concentration impurity regions formed outside the second gate electrode in the second transistor-forming region so as to adjoin to the second low concentration impurity regions; third sidewall insulating films formed on the portions of the second high concentration impurity regions located in proximity of the second low concentration impurity regions and on the side surfaces of the second sidewall insulating films; and second metal silicide layers formed on each surface of the second high concentration impurity regions using the second sidewall insulating films and the third sidewall insulating films as a mask.