Patent ID: 7777353

Claim:
A semiconductor device in which a plurality of leads are each connected to a plurality of electrode pads formed in a periphery of a semiconductor chip via a plurality of wires, said semiconductor device comprising: a first set of electrode pads that are aligned adjacent to each other in a first line, which is defined opposite to and at a first distance from a first lead, wherein a plurality of first electrode bonds corresponding to the first set of the electrode pads are connected to a plurality of first lead bonds aligned in the first lead in its longitudinal direction via a first set of wires each having a respective first loop height; and a second set of electrode pads that are aligned adjacent to each other in a second line, which is defined opposite to and at a second distance from a second lead, wherein the second distance is greater than the first distance and the second lead is arranged adjacent to and in parallel with the first lead, wherein a plurality of second electrode bonds corresponding to the second set of electrode pads are connected to a plurality of second lead bonds aligned in the second lead in its longitudinal direction via a second set of wires each having a respective second loop height that is greater than each of the first loop heights, wherein a first lead bond that is farthest from the first line among the plurality of first lead bonds is connected to one of the first electrode bonds except for a first electrode bond positioned closest to the second line, and/or wherein a second lead bond that is closest to the second line among the plurality of second lead bonds is connected to one of the second electrodes bonds except for a second electrode bond positioned closest to the first line.