Patent ID: 7231478

Claim:
A computer memory arrangement, comprising a first plurality of input port facilities that are collectively coupled through a first router facility to selectively feed a second plurality of memory modules, and furthermore comprising an output port facility that is collectively fed by said second plurality of memory modules, said computer memory arrangement comprising a detection facility for detecting simultaneous and conflicting accesses through more than one of said first plurality of input port facilities, and for thereupon allowing only a single one among said simultaneous and conflicting accesses whilst generating a stall signal for signalling a mandatory stall cycle to a request source that implies an access latency thereto, and said computer memory arrangement further comprising a programming facility for having said access latency be selectably programmable according to an actual processing application; and request queues, each coupling an associated corresponding input port facility to said first router for thereby providing an additional and programmable slack interval, and each memory module comprising a respective memory bank, and a respective arbiter for upon finding plural concurrent access requests for access to an associated memory bank, generating an arbitrage signal that singles out a particular one among said concurrent access requests for exclusive handling thereof in preference to further access requests, and queueing such further access requests in the request queue in question that has a programmable length for thereby selecting a programmable access latency, whilst signalling said stall signal exclusively under control of an ORED full signalization of any such request queue.