Patent ID: 7700432

Claim:
A process for fabricating an integrated circuit structure comprising: forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate; forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate wherein the second layer is interposed between the first and the third layers, and wherein the first layer is adjacent the first device region forming a first and a second window in the at least three layers of material, wherein said first and second windows terminate at the first device region; forming doped semiconductor material in the first window, thereby forming a doped semiconductor plug in the at least three layers of material, wherein the doped semiconductor plug has a first end and a second end, and wherein the first end is in contact with the first device region; forming a second device region selected from the group consisting of a source region and a drain region in the second end of the doped semiconductor plug, wherein one of the first and second device regions is a source region and the other is a drain region; removing the second layer, thereby exposing a portion of the doped semiconductor plug; forming gate dielectric material on the exposed portion of the first semiconductor plug; forming a gate in contact with the gate dielectric material; forming a first conductive layer in the second window; forming a first dielectric layer overlying the first conductive layer in the second window; and forming a second conductive layer over the first dielectric layer in the second window, such that the first conductive layer, the first dielectric layer and the second conductive layer form a capacitor.