Patent ID: 7987342

Claim:
An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor, where the instruction processing circuit comprises: a cache circuit configured to: store a sequence of operations of a first type and a sequence of operations of second type, wherein the sequence of operations of the second type represents at least a portion of the sequence of operations of the first type, wherein the sequence of operations of the second type is generated by a basic block builder circuit for optimizing the sequence of operations of the first type using a first optimization technique, and store a plurality of sequences of operations of a third type that represent sets of at least two sequences of operations stored in the cache circuit, wherein a sequence of operations of the third type is generated by a multi-block builder circuit, separate from the basic block builder circuit, from the sequence of operations of the second type and another sequence of operations of the third type using a second optimization technique, wherein the another sequence of operations of the third type is generated by the multi-block builder circuit and stored in the cache circuit; and the multi-block builder circuit configured to retrieve the sequence of operations of the second type and the another sequence of operations of the third type from the cache circuit for generating the sequence of operations of the third type, wherein the first optimization technique and the second optimization technique comprise reordering of operations, removal of dependencies between operations, and grouping of operations.