Patent ID: 8677182

Claim:
A computer system, comprising: a first processor, outputting a first catastrophic error signal; an error detecting circuit, coupled to the first processor to receive the first catastrophic error signal, wherein the error detecting circuit further comprises a first internal error detecting unit and a first machine error detecting unit, the first internal error detecting unit outputting an internal error reset signal when the first catastrophic error signal changes to a first level and is maintained for a period exceeding a first predetermined time, and the first machine error detecting unit outputting a machine error reset signal when the first catastrophic error signal changes to the first level and passes a second predetermined time, wherein the second predetermined time is greater than the first predetermined time; and a south bridge chip, coupled to the error detecting circuit, and rebooting the computer system according the internal error reset signal or the machine error reset signal, wherein the first internal error detecting unit comprises: a first inverter, wherein an input terminal of the firs inverter is coupled to the first processor to receive the first catastrophic error signal; a first filter, wherein an input terminal of the first filter coupled to an output terminal of the first inverter, and when a voltage level of the input terminal of the first filter is a second level and is maintained for a period exceeding the first predetermined time, a voltage level of an output terminal of the firs filter changes to the second level; a second inverter, wherein an input terminal of the second inverter is coupled to the output terminal of the first filter, and an output terminal of the second inventor outputs the internal error reset signal.