Patent ID: 7378316

Claim:
A method for fabricating a memory array comprising a plurality of vertical NROM memory cells, the method comprising: forming a first plurality of doped regions in a substrate such that a gap exists between each doped region, the doped regions having a different conductivity type than the substrate; forming an oxide pillar over the gap between the doped regions; forming an ultra-thin silicon body region extending from each doped region along opposing sidewalls of the oxide pillar; forming a second plurality of doped regions in a polysilicon material over the oxide pillar and body regions such that the doped regions over the pillar are electrically coupled and have the same conductivity type as the first plurality of doped regions; forming a gate insulator layer over the first plurality of doped regions, the body regions, and the second plurality of doped regions; and forming a polysilicon gate area over the gate insulator adjacent to each of the body regions.