Patent ID: 7778790

Claim:
A semiconductor integrated circuit device comprising: a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register; wherein a first flip-flop of said plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes a signal level of the first output signal regardless of changing a signal level of a first signal flowing in a first signal route from an output of a third flip-flop of said plurality of flip-flops to an input of said first flip-flop based on a first selection control signal; wherein a second flip-flop of said plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes a signal level of the second output signal regardless of changing a signal level of a second signal flowing in a second signal route from an output of a fourth flip-flop of said plurality of flip-flops to an input of said second flip-flop, based on a second selection control signal; and a control circuit configured to generate the first and second selection control signals such that a period during which said first flip-flop fixes the signal level of the first output signal is different from a period during which said second flip-flop fixes the signal level of the second output signal.