Patent ID: 8656337

Claim:
A computer executable method for assisting in the design of a logic circuit, the method comprising the steps of: acquiring a logic circuit description data; generating, based on the acquired logic circuit description data, a first netlist that is logically integrated with a first frequency; generating, based on the acquired logic circuit description data, a second netlist that is logically integrated with a second frequency that is higher than the first frequency; arranging logical operation elements and wiring the logical operation elements based on the first netlist; outputting a timing report related to execution timing for each of a plurality of blocks associated with the logical operational elements; extracting any block of the plurality of blocks, based on the outputted timing report, not satisfying a desired operational speed; replacing the first netlist with the second netlist for any extracted block when performing the arranging step for logical operation elements associated with any extracted block and wiring associated with any extracted block; and outputting another timing report after the arranging for the extracted blocks is performed, wherein at least one step is carried out on a computer device.