Patent ID: 8781051

Claim:
A symbol clock recovery circuit for a data communication system using coherent demodulation, the symbol clock recovery circuit comprising an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols, a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit, wherein the timing detector is adapted for detecting at least one zero crossing between the at least two symbols of the preamble of the frame of the digital signal, for determining a phase being associated with the at least one zero crossing, and for calculating an optimum phase for sampling the coherent-detected baseband analog signal based on the calculated phase being associated with the at least one zero crossing, wherein the phase shifting unit comprises a second input for receiving from the timing detector the optimum phase for sampling the coherent-detected baseband analog signal, and wherein the phase shifting unit is adapted for shifting the phase of the symbol clock signal according to the received optimum phase to generate an adapted symbol clock signal and for providing the adapted symbol clock signal to the analog-to-digital converter.