Patent ID: 8461638

Claim:
A non-volatile semiconductor memory device comprising: a charge accumulation layer formed on a substrate; a memory gate formed onto said substrate through said charge accumulation layer; a first side gate formed on a first insulating film, a first portion of the first insulating film extending between the first side gate and a first side of said memory gate, and a second portion of the first insulating film extending between the first side gate and the substrate; a second side gate formed on a second insulating film, a first portion of the second insulating film extending between the second side gate and a second side of the memory gate opposite to said first side of the memory gate, and a second portion of the second insulating film extending between the second side gate and the substrate; a first impurity implantation region formed in said substrate on a side of said first side gate; a second impurity implantation region formed in said substrate on a side of said second side gate; and a channel region formed between said first impurity implantation region and said second impurity implantation region, wherein said channel region comprises: a first region that extends for an entire length of a boundary between said charge accumulation layer and said substrate; a select side region that extends from a first end of said first region to an end of said first impurity implantation region; and an assist side region that extends from a second end of said first region to an end of said second impurity implantation region, and wherein a length of said select side region is longer than a length of said assist side region.