Patent ID: 7830203

Claim:
A power gating circuit, comprising: a first transistor, having a gate terminal controlled by a first input signal, a first source/drain terminal coupled to a system voltage, and a second source/drain terminal outputting an output voltage for powering a logic circuit in accordance with the first input signal; a charge pump circuit, directly coupled to a bulk terminal of the first transistor for pulling high a bulk voltage of the first transistor when the first input signal is pulled low, and pulling low the bulk voltage of the first transistor when the first input signal is pulled high; and a hold circuit, coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor, wherein the charge pump circuit comprises a capacitor having a first terminal coupled to a second input signal, and a second terminal coupled to the bulk terminal of the first transistor, wherein the first input signal and the second input signal are always inverted with each other.