Patent ID: 8399934

Claim:
A complementary metal oxide semiconductor (CMOS) device, comprising: a positive channel metal oxide semiconductor (PMOS) transistor formed in a first region of a semiconductor substrate, the PMOS transistor comprising a first portion of a single layer of a high-k dielectric material having a top surface and defining a first high-k gate dielectric, the first portion of the single layer of the high-k dielectric material disposed over and in contact with the semiconductor substrate, wherein the single layer of the high-k dielectric material has no physical interface layer between the top surface of the single layer of the high-k dielectric material and a bottom surface of the single layer of the high-k dielectric material contacting the semiconductor substrate, and a first gate disposed over and in contact with the top surface of the single layer of the high-k dielectric material; and a negative channel metal oxide semiconductor (NMOS) transistor formed in a second region of the semiconductor substrate, the NMOS transistor comprising a second portion of the single layer of the high-k dielectric material defining a second high-k gate dielectric, the second portion of the single layer of the high-k dielectric material disposed over and in contact with the semiconductor substrate in the second region, and a second gate disposed over and in contact with the second portion of the single layer of the high-k dielectric material, wherein the first portion of the single layer of the high-k dielectric material comprises an additional material that is higher concentrated at the top surface than at the bottom surface, and wherein the second portion of the single layer of the high-k dielectric material does not comprise the additional material.