Patent ID: 7953941

Claim:
A data processor comprising: a central processing unit; and a memory controller capable of controlling an external memory via an external bus, wherein the memory controller is adapted to be coupled to the external memory which has a buffer to store predetermined size data, and the predetermined size data includes data of an address range corresponding to low order side a plurality of bits of an address signal, the memory controller being further adapted to perform a burst operation between the buffer and the data processor according to an access request in which an access address is changed within the address range, wherein the memory controller outputs a chip enable signal, an output enable signal, and the address signal to the external memory via the external bus to control the external memory, wherein the memory controller performs an access control for executing the burst operation of the external memory continuously, if it detects a burst access of a boundary of the buffer by exceeding the address range from a change in a higher order bit than a predetermined bit number on the low order side, during control of the burst operation, wherein the access control performed by the memory controller includes control to output the chip enable signal, to negate temporarily the output enable signal, to stop the burst operation, and to assert again the output enable signal, wherein the memory controller includes a register having: a field to specify a burst frequency, a field to specify a bus width of the external bus, a field to specify an access time after a first burst, a field to specify a memory type of the external memory, a field to specify a first number of wait cycles to be inserted between assertion of the chip enable signal and assertion of the output enable signal, and a field to specify a second number of wait cycles to be inserted between assertion of the output enable signal and a read of data, wherein the memory controller includes a burst counter to count the burst frequency specified by the register, a circuit to generate an address signal for the burst operation corresponding to a start address received from the central processing unit, and a burst stop detect circuit to detect a burst access exceeding the address range of data stored in the buffer, wherein the burst counter counts continuously until reaching the burst frequency value of the register after stopping the burst operation when the access of exceeding the address range is detected, and wherein the burst stop detect circuit includes the burst counter, and a burst stop deciding circuit generating a burst stop signal after receiving the access request exceeding the address range of data stored in the buffer, based on the burst frequency, the bus width, the memory type specified by the register, the access address, an information of the access size and the counter value of the burst counter.