Patent ID: 8198917

Claim:
A current segmentation circuit for optimizing output waveform from high speed data transmission interface, comprising: four current sources I 1 , I 2 , I 3 and I 4 ; four current control switches K 1 , K 2 , K 3 and K 4 ; a first resistor; and a second resistor, wherein a first end of said current source I 1 , a first end of said current source I 2 , a first end of said current source I 3 and a first end of said current source I 4 are connected with a power supply, a second end of said current source I 1 and a second end of said current source I 3 are connected with a first end of said current control switch K 1 and a first end of said current control switch K 3 , a second end of said current source I 2 and a second end of said current source I 4 are connected with a first end of said current control switch K 2 and a first end of said current control switch K 4 , a second end of said current control switch K 1 and a second end of said current control switch K 2 are connected with a first differential data line and a first end of said first resistor, a second end of said current control switch K 3 and a second end of said current control switch K 4 are connected with a second differential data line and a first end of said second resistor, and a second end of said first resistor and a second end of said second resistor are connected with ground, whereby a high speed emission current is segmented by said current segmentation circuit for controlling a rising and falling time of a high speed transmission datum to match a delay of a segmented current control signal and a delay of a datum.