Patent ID: 7259968

Claim:
A method, comprising: placing at least first and second conductive traces of different widths and same impedance on a first layer, wherein said first layer is one layer in a multi-layer circuit board; and providing a power plane and a ground plane, wherein one of the power plane and ground plane has a first void region such that the first conductive trace is spaced apart from the power plane by a first thickness, and the second conductive trace is spaced apart from the ground plane by a second, different thickness, wherein the power plane is placed on a second layer of the multi-layer circuit board, and wherein the ground plane is placed on a third layer of the multi-layer circuit board; removing a portion of one of the power and ground planes to form the first void region, said first void region resulting in the traces having the same impedance; placing another power plane on a fourth layer; placing another ground plane on a fifth layer; and removing a portion of the fourth layer power plane to form a second void region in the fourth layer power plane, said second void region resulting in the traces having the same impedance.