Patent ID: 8520416

Claim:
A current reference generating circuit, comprising: a first multiplier module, configured to receive a rectified voltage waveform signal (Iac) generated by a rectifier bridge in a main circuit of a switch mode power supply and an amplified error signal (Vcomp) generated by an average current loop, and to generate a sinusoidal half-wave signal (Iref), wherein the sinusoidal half-wave signal (Iref) has a same frequency and phase with the rectified voltage waveform signal (Iac), the amplitude of the sinusoidal half-wave signal (Iref) varies with the amplified error signal (Vcomp) generated by the average current loop and the sinusoidal half-wave signal (Iref) serves as a reference signal that is followed by a primary-side current signal in the main circuit of the switch mode power supply; a second multiplier module, configured to receive the sinusoidal half-wave signal (Iref) and a control signal (Vcontrol) and generate a pulse signal (iemu), wherein the control signal (Vcontrol) is a pulse signal indicative of a conduct time of an output diode in the main circuit of the switch mode power supply, an amplitude envelope of the pulse signal (iemu) is a sinusoidal half-wave having the same frequency and phase with the sinusoidal half-wave signal (Iref) and having an amplitude in direct proportion with that of the sinusoidal half-wave signal (Iref), and a pulse width of the pulse signal (iemu) equals a pulse width of the control signal (Vcontrol); an average current loop, configured to receive the pulse signal (iemu) and an average current loop reference signal (Vref), wherein the average of the pulse signal (iemu) is compared to the predetermined average current loop reference signal (Vref) and the difference between the average of the pulse signal (iemu) and the predetermined average current loop reference signal (Vref) is amplified by a compensation network in the average current loop and the amplified difference is output as an amplified error signal (Vcomp).