Patent ID: 7816201

Claim:
A method of manufacturing a semiconductor device comprising: forming a first insulating layer on a first semiconductor region of a first conductivity type; forming a second insulating layer thinner than the first insulating layer on a second semiconductor region of a second conductivity type; implanting first impurities simultaneously in the first and second semiconductor regions with a condition that a peak of a profile of the first impurities of a first conductivity type is formed in the first and second semiconductor regions; implanting second impurities simultaneously in the first and second semiconductor regions with a condition that a peak of a profile of the second impurities of a first conductivity type is formed in the first insulating layer; forming a first MIS transistor of a second conductivity type with the first insulating layer as a gate insulating layer in the first semiconductor region; and forming a second MIS transistor of a first conductivity type in the second semiconductor region.