Patent ID: 7772898

Claim:
A phase interpolator comprising: a first adjustable delay unit to delay a first reference clock signal to generate an interpolated clock signal with a variable delay amount; a second adjustable delay unit to delay a second reference clock signal which has different phase from the first reference clock signal to generate a signal for comparison with a variable delay amount; a phase comparator to compare a phase of the interpolated clock signal and the signal for comparison, and to output a comparison result signal; an integrator to integrate the comparison result signal and output a phase difference voltage depending on the comparison result signal; a first multiplier to multiply the phase difference voltage by a first constant number and output a first control voltage for the delay amount of the first adjustable delay; and a second multiplier to multiply the phase difference voltage by a second constant number and output a second control voltage for the delay amount of the second adjustable delay, wherein the delay amount of the second adjustable delay is a sum of one period of the second reference clock signal and a negative value.