Patent ID: 7541236

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor on a surface of a semiconductor substrate; forming an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor; forming, in the interlayer insulation film, a plurality of contact holes exposing respectively a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or drain of the pMOS transistor; and forming a single-layer first wiring connecting the control gate to the sources or the drains of the nMOS transistor and the pMOS transistor, and a single-layer second wiring connecting the sources or the drains of the nMOS transistor and the pMOS transistor to each other which sources or the drains are not connected to said first wiring, via the plurality of the contact holes in a same layer, wherein the semiconductor device has an embedded structure.