Patent ID: 7971034

Claim:
A recycling microprocessor supporting more than one instruction-and-operand addressing mode, the recycling microprocessor comprising: an instruction fetch unit (IFU) for computation of address adds in selected address modes and for reporting non-equal comparison of the computation to logic executing on the recycling microprocessor; and a fixed point unit for determining whether an address mode has changed and for reporting any address mode changes to the logic; the recycling microprocessor for performing a method comprising: computing address adds in selected address modes; comparing the computed address adds to the logic; triggering a recycling event to ensure subsequent ofetches are relaunched in a correct address mode and that no execution writebacks occur from work performed in an incorrect address mode, in response to determining that the comparison yields an equal result but the address mode has changed; and clearing bits respectively set in response to the determinations, and resetting, via a serialization event, a corresponding pipeline for operation in the correct address mode, in response to determining that the comparison yields an non-equal result but the address mode has changed.