Patent ID: 6970316

Claim:
A driver circuit for driving a head of a memory disk device, comprising: switching circuitry connected between a first voltage supply, a second voltage supply and first and second terminals of the head, the switching circuitry including first and second steady state switch-connected resistances each connected at one end to a corresponding one of the first and second terminals and connected at another end to a voltage reference; and timing circuitry connected to the switching circuitry for connecting the first terminal to a first voltage level during a first time period and to a second voltage level during a second time period following the first time period while disconnecting the first and second steady state switch connected resistances, and connecting the second terminal to a third voltage level during the first time period and to a fourth voltage level during the second time period while disconnecting the first and second steady state switch connected resistances, the first and second time periods occurring when current through the head transitions between steady state current levels, and the first, second, third and fourth voltage levels forming drive signals applied to the head having substantially no common mode voltage.