Patent ID: 8584065

Claim:
A method, carried out by one or more devices, for designing an integrated circuit to operate at a desired clock frequency range comprising: determining a value of pessimism in a static timing analysis of at least two adjacent timing critical paths of the integrated circuit based on timing correlation between the at least two adjacent timing critical paths, wherein determining the value of pessimism comprises: performing a first static timing analysis at a critical corner with variation information to provide a variation incorporated clock delay for each of the at least two adjacent timing critical paths; performing a second static timing analysis at the critical corner without the variation information to provide a non-variation incorporated clock delay for each of the at least two adjacent timing critical paths; determining a value of clock pessimism based on the variation incorporated clock delay and the non-variation incorporated clock delay for each of the at least two adjacent timing critical paths comprising: in the first static timing analysis, determining a first variation incorporated clock delay for a first timing critical path of the at least two adjacent timing critical paths from a common flip-flop between the at least two adjacent timing critical paths to a clock divergence point of the first timing critical path; in the first static timing analysis, determining a second variation incorporated clock delay for a second timing critical path of the at least two adjacent timing critical paths from the common flip-flop to a clock divergence point of the second timing critical path; in the second static timing analysis, determining the non-variation incorporated clock delay from the common flip-flop to a common clock divergence point of the first and second timing critical paths; and determining the value of clock pessimism based on a difference between the non-variation incorporated clock delay and a larger one of the first and second variation incorporated clock delays; and reducing the value of pessimism in the static timing analysis of the at least two adjacent timing critical paths in response to the determination.