Patent ID: 7685332

Claim:
A method of managing data flow in a programmable element for data processing that includes a crosspoint switch, a register array, and a control register, the programmable element being part of an integrated circuit, the integrated circuit being in communication with a host circuit that is external to the integrated circuit, the method comprising: writing data to the register array at a first data rate and reading the data from the register array at a second data rate if the control register is in a first state; establishing a first data path from a host input to a first bank of registers in the register array that excludes the crosspoint switch, wherein data traveling along the first data path passes from the host input to the first bank of registers through a host register, a first set of multiplexers coupled to receive the output of the host register, and a second set of multiplexers coupled to receive a first and a second the output of the first set of multiplexers and configured to distribute data to the inputs of the first bank of registers; simultaneously writing data to the first bank of registers in the register array from the host along the first data path and reading data from a second bank of registers in the register array to the crosspoint switch through a third set of multiplexers coupled directly therebetween if the control register is in a second state; and storing data input values at a first data rate and reading the stored data values at a second, faster rate each time a data input value is stored if the control register is in a third state.