Patent ID: 8151255

Claim:
A method for performing speculative parallelization, comprising: executing, by a first computer processor, a first co-thread of an application; executing, by a second computer processor, a second co-thread of the application in parallel with the first co-thread; assigning a first memory log to the first co-thread; assigning a second memory log to the second co-thread; assigning a first police thread to the first memory log and the second memory log; while executing the second co-thread in parallel with the first co-thread: logging, in the first memory log, a first plurality of memory transactions requested by the first co-thread; logging, in the second memory log, a second plurality of memory transactions requested by the second co-thread; maintaining a plurality of temporary results for the first co-thread and the second co-thread; performing, by the first police thread, a first comparison of the first memory log with the second memory log; and identifying, based on the first comparison, a first dependence violation between the first co-thread and the second co-thread, wherein the first dependence violation is caused by a write to a memory location performed by the first co-thread before a read to the same memory location performed by the second co-thread; and in response to identifying the first dependence violation: determining a location of the read within the second co-thread where the first dependence violation occurs; committing a first portion of the plurality of temporary results occurring prior to the location; rolling back a second portion of the plurality of temporary results occurring after the location; and generating a notification of the first dependence violation.