Patent ID: 7061272

Claim:
A finite state machine, comprising: a memory device for providing outputs which depend on inputs to the memory device; a device configured to receive input values; a multiplexer for selecting a subset of the input values based on an output of the memory device; a latch, connected to the output of the memory device, the latch being configured to allow the outputs of the memory device to be read only after a predetermined delay following any change in the inputs to the memory device; and a control circuit, the control circuit being adapted to trigger a change in the outputs of the memory device following a change in the inputs to the memory device, and to enable the latch after said predetermined delay; wherein the outputs of the memory device form the outputs of the finite state machine and a present state of the finite state machine, and wherein the present state of the finite state machine and the selected subset of the received input values define the inputs to the memory device.