Patent ID: 8173993

Claim:
A method for forming a nanowire tunnel field effect transistor (FET) device, the method comprising: forming a nanowire suspended by a first pad region and a second pad region over a semiconductor substrate, the nanowire including a core portion and a dielectric layer around the core portion; forming a gate structure around a portion of the dielectric layer; forming a first protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure; implanting a first type of ions in a first portion of the exposed nanowire; implanting a second type of ions in the dielectric layer of a second portion of the exposed nanowire; removing the dielectric layer from the second portion of the exposed nanowire to reveal the core portion of the second portion of the exposed nanowire; removing the core portion of the second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer; and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.