Patent ID: 8904099

Claim:
A memory module comprising: a volatile memory subsystem having a first storage capacity; a nonvolatile memory subsystem having a second storage capacity, the second storage capacity being at least 400 percent more than the first storage capacity, wherein the memory module is configured to provide non-volatile storage via the non-volatile memory subsystem; a standard DIMM interface configured to electrically couple the memory module to a host system, the standard DIMM interface including an edge connector which fits into a memory socket of the host system, the edge connector including a plurality of edge connections to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and the host system, the first plurality of DDR SDRAM signals including at least address/control and data signals, wherein data is communicated between the volatile memory subsystem and the host system using the first signals path; and a controller in communication with the volatile memory subsystem via a second signals path for transmitting a second plurality of DDR SDRAM signals between the controller and the volatile memory subsystem, the second plurality of DDR SDRAM signals including at least address/control and data signals, the controller being coupled to the nonvolatile memory subsystem via a third signals path for transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem, wherein the controller includes: a logic element operable to generate address and control signals for the nonvolatile memory subsystem, wherein the logic element performs address-to-address translation between the volatile memory subsystem and the nonvolatile memory subsystem, and a microcontroller operable to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem, wherein the controller is configured (i) to communicate data with the volatile memory subsystem using the second plurality of DDR SDRAM signals via the second signals path, and (ii) to communicate data with the nonvolatile memory subsystem using the at least data, address and control signals via the third signals path.