Patent ID: 8027421

Claim:
A method for serial communication of binary signals between a data transmitter and a data receiver, the binary signals varying between a first logic level representing a first binary value and a second logic level representing a second binary value, comprising: transmitting a clock signal from the data receiver to the data transmitter over a clock channel, the clock signal having a predetermined clock cycle; transmitting a synchronization signal from the data receiver to the data transmitter over a synchronization channel; and receiving the binary data signals at the data receiver over a data channel, the binary data signals being received in a frame that includes a header code and followed by a plurality of data bits, each bit of the header code and the data bits having a width of multiple predetermined clock cycles, the receiving including: sampling the data channel periodically based on the predetermined clock cycle, including sampling a first header bit at a plurality of times, determining data bit sampling times for other data bits in the frame, the determined data bit sampling times being chosen from a pattern of the sampled first header bit signals, wherein determining data bit sampling times for other data bits in the frame includes: counting a total number of samples indicative of detection of the first header bit; and in response to said count, establishing sampling times for remaining data bits in the frame based on one of two rules: sampling at the times corresponding to a second detection of the first header bit, and sampling at the times corresponding to a second to last detection of the first header bit; and detecting at the data receiver at said data bit sampling times the logic value of each said data bit.