Patent ID: 7709349

Claim:
A method of manufacturing a semiconductor device, comprising: placing a blocking layer over an oxide cap layer located over a gate electrode and sidewall spacers and source/drains located adjacent thereto; forming a chemical/mechanical polishing (CMP) stop layer over the blocking layer; forming a bulk oxide layer over the CMP stop layer; removing the bulk oxide layer with a CMP process to expose at least the CMP stop layer located over the gate electrode, wherein a removal rate of the bulk oxide layer is at least about 3 times greater than a removal rate of the CMP stop layer; removing portions of the CMP stop layer, the blocking layer, and the oxide cap layer to expose a top portion of the gate electrode; and removing the bulk oxide and the CMP stop layer located over the source/drains with a wet etch, wherein a wet etch removal rate of the CMP stop layer is at least about 10 times greater than a removal rate of the blocking layer.