Patent ID: 7956453

Claim:
A semiconductor package, comprising: a substrate including an insulative layer defining opposed first and second surfaces and having a first conductive pattern disposed on the first surface and a second conductive pattern disposed on the second surface and electrically connected to the first conductive pattern; at least one semiconductor die mounted to the insulative layer and electrically connected to the first conductive pattern thereof; a patterning layer defining a first surface, the patterning layer at least partially encapsulating the semiconductor die and at least partially covering the first conductive pattern and the first surface of the insulative layer, the second conductive pattern not being covered by the patterning layer; and a wiring pattern embedded in the patterning layer and electrically connecting the semiconductor die to the first conductive pattern of the substrate, a portion of the wiring pattern being exposed in and substantially flush with the first surface of the patterning layer.