Patent ID: 8786328

Claim:
An apparatus comprising: a plurality of latches coupled in series with one another in a ring configuration, wherein each latch includes: a tri-state inverter with a first clock terminal and a second clock terminal; a first resistor-capacitor (RC) network that is coupled to the first clock terminal; and a second RC network that is coupled to the second clock terminal; and a biasing network having: a first bias voltage generator that is coupled to the first RC network for each latch; and a second bias voltage generator that is coupled to the second RC network for each latch, wherein the first RC network further comprises: a capacitor that is coupled to the first clock terminal and that is configured to receive a clock signal; and a resistor that is coupled to the first clock terminal and the first bias voltage generator, wherein the capacitor, resistor, and clock signal further comprise a first capacitor, a first resistor, and a first clock signal, and wherein the second RC network further comprises: a capacitor that is coupled to the first clock terminal and that is configured to receive a second clock signal; and a resistor that is coupled to the first clock terminal and the first bias voltage generator, wherein each of the resistors allow inner transistors of a first latch of the plurality of latches and the second latch of the plurality of latches to be biased through coupled each of the resistors such that the gate voltages of these transistors are near or above their respective threshold voltages during operation.