Patent ID: 7786459

Claim:
A memory element comprising: one or more layers comprising an ion path layer and an ion source layer in contact with said ion path layer, said ion path layer being positioned between a first electrode and a second electrode, wherein an element selected from Cu and Ag is contained in said ion path layer or in another of the one or more layers in contact with said ion path layer and an element selected from Te, S and Se is contained in said ion source layer; wherein said memory element is constructed and arranged to provide, upon application of a voltage, a changed resistance to perform recording of information, a state of low resistance value defining a recorded state of said memory element and a state of high resistance value defining an erased state of said memory element; and wherein the one or more layers have a thickness such that, upon a change in voltage, said memory element converts from said recorded state to said erased state, a resistance value of said memory element after the change being within ten times a resistance value of said memory element prior to said change.