Patent ID: 7700419

Claim:
A method of forming an insulated gate silicon nanowire transistor amplifier structure, comprising: (a) disposing a silicon layer on a dielectric substrate; (b) patterning the silicon layer for forming at least first, second and third electrodes separated by first and second trenches; (c) growing laterally at least a first nanowire in the first trench for electrically coupling the first and second electrodes; (d) growing laterally at least a second nanowire in the second trench for electrically coupling the second and third electrodes; (e) encapsulating the first and second nanowires in a first dielectric material; (f) disposing first drain and first source contacts on respective first and second electrodes; (g) disposing second drain and second source contacts on respective second and third electrodes; (h) disposing a first gate contact on the first dielectric material in close proximity to the first nanowire; and (i) disposing a second gate contact on the first dielectric material in close proximity to the second nanowire, wherein the first drain, source and gate contacts serve as an interface to a first transistor stage of the transistor amplifier structure and the second drain, source and gate contacts serve as an interface to a second transistor stage of the transistor amplifier structure.