Patent ID: 7582520

Claim:
A method of fabricating a metal-oxide-semiconductor (MOS) transistor, comprising: forming a first gate structure and a second gate structure on a substrate, wherein the first gate structure has a dimension greater than the second gate structure; forming first N-type lightly doped drain regions in the substrate on two sides of the first gate structure; after forming the N-type first lightly doped drain regions, performing a lightly doped drain annealing process; after performing the lightly doped drain annealing process, forming a second N-type lightly doped drain region in the substrate on two sides of the second gate structure; forming first spacers on the sidewalls of the first gate structure and simultaneously forming second spacers on the sidewalls of the second gate structure; forming first N-type source/drain regions in the substrate on two sides of the first spacers and forming second N-type source/drain regions in the substrate on two sides of the second spacers; and performing a source/drain annealing process.