Patent ID: 7169660

Claim:
A method of fabricating a small opening for forming a vertical MOS transistor comprising: doping a subsurface area of a semiconducting substrate to form a source region; forming a first dielectric layer over the doped area of the semiconducting substrate; depositing a first polysilicon layer over the first dielectric layer; forming a second dielectric layer over the first polysilicon layer; forming a third dielectric layer over the second dielectric layer; etching a dielectric window through the third dielectric layer; forming a fourth dielectric layer into the dielectric window and over the third dielectric layer, the fourth dielectric layer being of a material dissimilar to the second dielectric layer; etching the fourth dielectric layer anisotropically using an etchant with a high selectivity ratio between the fourth dielectric layer and the second dielectric layer thereby forming a spacer; etching portions of the first and second dielectric layers and the first polysilicon layer anisotropically, the portions underlying an area bounded by a periphery of the spacer thereby forming the opening; filling the opening with epitaxial silicon, thereby forming an epitaxial channel; forming a second polysilicon layer over the epitaxial channel thereby forming a drain layer; forming a second spacer circumscribing the second polysilicon layer thereby defining a drain; etching portions of the first polysilicon layer using the second spacer as a mask to expose polysilicon proximate to the channel thereby defining a gate; forming a third spacer circumscribing the first polysilicon layer; and etching portions of the first and second dielectric layers using the third spacer as a mask thereby exposing the source region.