Patent ID: 7694244

Claim:
A computer-implemented method for predicting criticalities for optimization of integrated circuit (IC) manufacturing with modeling and cross correlation comprising: using a processor for: identifying a first set of critical areas, wherein the first set of critical areas is determined at least in part by analyzing a first IC design layout for simulated hotspots; identifying a second set of critical areas, wherein the second set of critical areas is based at least in part upon manufactured data of a second IC design layout; tuning a set of weighting parameters of the first set of critical areas so that one or more critical areas of the first set of critical areas substantially match one or more corresponding critical areas of the second set of critical areas; and providing a prioritized list of a third set of critical areas from a third IC design layout, wherein the third set of critical areas is prioritized by applying the set of weighting parameters to the third set of critical areas; and storing the prioritized list of the third set of critical area in a volatile or non-volatile computer-usable medium or displaying the prioritized list of the third set of critical area on a display device.