Patent ID: 7184310

Claim:
A sequential program-verify method for use in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments, the method comprising: writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common one of the alignments; verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value; buffering the fault values; and in response to the verification of all the blocks of cells, providing an indication of the alignments being defective according to the fault values, wherein the memory device further includes a plurality of read/write units each one having a first latch and a second latch, and means for selectively coupling each read/write unit with the cells belonging to a corresponding one of the alignments, and wherein: the verifying step includes reading the block of cells into the corresponding second latches, and the buffering step includes latching the fault values into the corresponding first latches.