Patent ID: 8232607

Claim:
A method of forming a semiconductor structure comprising: forming a gate electrode and a planarization dielectric layer on a semiconductor substrate, wherein a top metallic surface of said gate electrode is coplanar with a top surface of said planarization dielectric layer; selectively forming a gate cap dielectric on said top metallic surface of said gate electrode, while said gate cap dielectric is not formed on or above said planarization dielectric layer; forming a contact-level dielectric layer over said gate cap dielectric and said planarization dielectric layer; and forming a via hole through said contact-level dielectric layer over a periphery of said gate cap dielectric, wherein a first portion of said via hole does not extend below said gate cap dielectric where said gate cap dielectric is present, and a second portion of said via hole extends into said planarization dielectric layer where said gate cap dielectric is not present.