Patent ID: 8625355

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory strings, each memory string including memory cells series-connected between a string select transistor and a ground select transistor, wherein the ground select transistor is connected to a common source line (CSL); a plurality of word lines including a selected word line, wherein the selected word line is commonly connected to gates of a row of memory cells extending across the plurality of memory strings; a plurality of bit lines including a selected bit line, wherein each one of the plurality of bit lines is connected to a corresponding one of the plurality of memory strings; a page buffer that programs data in selected memory cells associated with at least one of the selected word line and the selected bit line during a program operation, and that reads the programmed data from the selected memory cells during a verify read operation of a program verification operation; a fail bit counter that determines a number of fail cells among the selected memory cells based on the read data; a voltage controller that generates a read voltage applied to the selected word line during the verify read operation and a pre-charge voltage applied to selected bit line during the read verify operation; and a control circuit that controls the voltage controller to correct at least one of the read voltage and the pre-charge voltage to be applied during a subsequent verify read operation of the program verification operation in response to the number of fail cells.