Patent ID: 7486123

Claim:
A latch circuit for implementing enhanced noise immunity performance comprising: an L 1 latch; an L 2 latch coupled to said L 1 latch; said L 1 latch latching data during a first half clock cycle and providing a latched data state at an L 1 latch output node; said L 2 latch latching data during a second half clock cycle and providing a latched data state at an L 2 latch output node; said L 1 latch including a plurality of gated transistors connected between said L 1 latch output node and ground, and between said L 1 latch output node and a voltage supply for gating off a path from said L 1 latch output node to ground with a high latched data state at said L 1 latch output node; said L 2 latch including a plurality of gated transistors connected between said L 2 latch output node and ground, and between said L 2 latch output node and said voltage supply for gating off a path from said L 2 latch output node to ground with a high latched data state at said L 2 latch output node; and said L 1 latch including predefined L 2 nodes connected to selected gates of said plurality of gated transistors in the L 1 latch.