Patent ID: 7157768

Claim:
A semiconductor memory having a row and column arrangement of bit lines and word lines with a memory cell arranged at each crossing point of a bit line and a word line, comprising: conductively doped source/drain regions formed in fins of semiconductor material which are arranged parallel to one another, wherein the bit lines are connected to the source-drain regions; channel regions arranged between the respective source/drain regions and located a distance from one another in a direction of the word lines; gate electrodes, which are arranged on top and side walls of the respective fins, electrically insulated from and drive the respective channel regions, connected to the word lines, and electrically conductively connected to one another; and storage layers, which are located between the gate electrodes and the semiconductor material on top sides of the respective fins, and are used to program the respective memory cells, wherein the word lines are formed by parts applied to the side walls of the fins of the gate electrodes.