Patent ID: 8856494

Claim:
A data processing circuit, comprising: a set of registers that comprises instruction selectable registers, each register containing a plurality of N parts suitable for storing respective SIMD instruction operands and/or results; an instruction execution circuit having an instruction set that comprises a SIMD instruction, the instruction execution circuit comprising a plurality of arithmetic circuits, arranged to perform N respective identical operations in parallel in response to the SIMD instruction, the SIMD instruction defining a first and a second series of N respective SIMD instruction operands of the SIMD instruction from a first register and a second register from the set of registers that are selected by the SIMD instruction, each arithmetic circuit being arranged to receive a respective first operand and a respective second operand from the first and second series respectively, when executing the SIMD instruction, wherein the instruction execution circuit is arranged for selecting the first and second series so that the first and second series partially overlap, wherein at least a first and a second arithmetic circuit of the plurality of arithmetic circuits commonly use an operand from the first and/or the second series, and wherein at least two different operands from the operand registers of the plurality of arithmetic units overlap in the first and second series of operands.