Patent ID: 7426130

Claim:
A ferroelectric random access memory device, comprising: a first memory cell, comprising: a single ferroelectric capacitor; and a first access transistor connected between the ferroelectric capacitor and an independent plate line and operated by a word line enable signal on a word line, the ferroelectric capacitor connected between a bit line and the first access transistor; a second memory cell immediately adjacent to the first memory cell, having a second access transistor, the second access transistor connected to the independent plate line; and a word line driver coupled to the word line and a word line decoder, the word line driver including: a transistor coupled between the word line and the word line decoder, the transistor responsive to a word line enable signal; the transistor configured to transfer a main word line signal having a level less than or equal to a level of a first power supply from the word line decoder to the word line in response to the word line enable signal having a level substantially equal to a level of a second power supply, the level of the first power supply being less than the level of the second power supply; wherein the word line driver is configured to maintain the main word line signal having the level less than or equal to the level of the first power supply on the word line without boosting a signal on the word line.