Patent ID: 8909998

Claim:
An electronic device, comprising: a memory controller; and a memory storage device comprising: a first data signal receiver configured to receive a first data signal comprising a plurality of data bits from the memory controller connected to the first data signal receiver via at least one first data signal line; second data signal receivers each configured to receive at least one of a plurality of second data signals each comprising a plurality of data bits from the memory controller via at least one second data signal line; a redundancy check calculating circuit configured to calculate an error detection code based on the first and second data signals; and a masking device controllably masking the plurality of second data signals, the masking device comprising: a plurality of AND gates, wherein one input of each of the plurality of AND gates is connected to a first output of one of the first and second data signal receivers, and wherein an output of each of the plurality of AND gates is connected to the redundancy check calculating circuit; and a controller with a plurality of control outputs, wherein each of the plurality of control outputs is connected to a second input of one of the plurality of AND gates.