Patent ID: 8520429

Claim:
A semiconductor chip comprising: an SRAM (static random access memory), the SRAM further comprising: an SRAM cell comprising a first inverter and a second inverter, an output of the first inverter connected to an input of the second inverter, an output of the second inverter connected to an input of the first inverter; and a data dependent write assist circuit configured to reduce a supply voltage to the first inverter if the first inverter must be overcome during a write, and to reduce a supply voltage of the second inverter if the second inverter must be overcome during a write; and the data dependent write assist circuit further comprising logic to couple a Vdd supply to the first inverter when a write enable is low or when a data true signal is low, and to couple a Vwr supply that is lower than the Vdd supply, to the first inverter when both the write enable and the data true signal are high.