Patent ID: 7669152

Claim:
A method for semiconductor chip design comprising: identifying a leaf cell in a hierarchical description of a chip layout; applying a three-dimensional Monte Carlo random-walk process from the leaf cell; generating information from the three-dimensional Monte Carlo random-walk process, the generation of information including calculating one or more coupling parameters, the one or more coupling parameters including coupling resistance, coupling capacitance, coupling inductance, or combinations thereof; filtering the information to determine one or more conductors that contribute at or above a threshold level to the coupling parameters and neglecting conductors that contribute below the threshold level to the coupling parameters, the threshold level being a numeric threshold level; building a neighborhood of the leaf cell, the neighborhood including the conductors that contribute at or above the threshold level to the coupling parameters and neglecting the conductors that contribute below the threshold level to the coupling parameters; and storing data corresponding to the neighborhood of the leaf cell on a computer-readable medium.