Patent ID: 8325524

Claim:
A semiconductor device comprising: a semiconductor substrate having a principal surface; and a plurality of nonvolatile memory cells arranged at positions where word lines and bit lines which are arranged in a matrix intersect each other, each of the nonvolatile memory cells comprising a data write/erase element, a data read element, and a capacitor element, wherein the nonvolatile memory cells include a first nonvolatile memory cell, and a second nonvolatile memory cell which are arranged adjacent to each other, wherein a first active region, a second active region, a third active region, and a fourth active region which are electrically isolated from each other are arranged in the principal surface, wherein the capacitor element of the first nonvolatile memory cell is formed in the first active region, the respective write/erase elements of the first and second nonvolatile memory cells are both formed in the second active region, the respective read elements of the first and second nonvolatile memory cells are both formed in the third active region, and the capacitor element of the second nonvolatile memory cell is formed in the fourth active region, wherein the second active region and the third active region are arranged, in a first direction, between the first active region and the fourth active region, and wherein a capacitor element of a third nonvolatile memory cell which follows, in the first direction, the second nonvolatile memory cell is formed in the fourth active region.