Patent ID: 7984214

Claim:
A data bus interface with a bus clock line and a bus data line, in which beginning and end of a data transmission, respectively, is indicated by unique state combinations of the bus clock line and the bus data line, wherein an interface circuit is provided, which, in a receiving mode during active communication, ascertains states of the bus clock line and the bus data line by sampling the states of the bus clock line and the bus data line with a multiple of a clock rate of the bus clock line and outputs received data, wherein a control circuit is provided for detecting the beginning and the end of the data transmission, wherein the control circuit applies—after detecting the beginning of a data transmission—to the interface circuit a first clock signal, having a multiple of the clock rate of the bus clock line, which first clock signal is required for the operation of the interface circuit, and wherein the control circuit interrupts—after detecting the end of the data transmission—the first clock signal, wherein the control circuit is adapted to switch the first clock signal at an opposite slope of a decisive slope of a sampling stage of the interface circuit, whereby a fixed time is available before and after the data transmission for setting up and completing the transmission, and wherein applying and/or interrupting of the first clock signal takes place synchronously with a second clock signal, with the first clock signal being derived from the second clock signal.