Patent ID: 7376855

Claim:
A computer system, comprising: a transmitting integrated circuit arranged to generate a data signal, the data signal being aligned with a first clock signal; and a receiving integrated circuit arranged to receive the data signal and the first clock signal, the receiving integrated circuit having a clock domain synchronizer that comprises: a first circuit path arranged to input the data signal dependent on the first clock signal, synchronize the data signal with a second clock signal, and pass the synchronized data signal to an output of the clock domain synchronizer, and a second circuit path arranged to input the data signal and pass the data signal to the output dependent on the second clock signal, wherein the second circuit path comprises: circuitry arranged to generate an internal clock signal, wherein the internal clock signal is equivalent to the second clock signal less clock edges occurring during times of transitions of the data signal; and circuitry arranged to output the data signal dependent on the internal clock signal, and wherein the circuitry arranged to generate the internal clock signal comprises: an XOR gate having a first input operatively connected to the data signal and a second input operatively connected to the second clock signal; and a pulse suppression circuit having an input connected to an output of the XOR gate, wherein the pulse suppression circuit is arranged to suppress glitches that are narrower than a pre-determined pulse width, and wherein the pulse suppression circuit is further arranged to output the internal clock signal.