Patent ID: 7932172

Claim:
A semiconductor chip comprising: a semiconductor substrate; a first MOS device in and over said semiconductor substrate; a second MOS device in and over said semiconductor substrate; a first interconnecting structure over said semiconductor substrate, wherein said first interconnecting structure is connected to a diffusion layer of said first MOS device, wherein said first interconnecting structure comprises a first portion and a second portion over said first portion, wherein said first portion is connected to said second portion; a second interconnecting structure over said semiconductor substrate, wherein said second interconnecting structure is connected to a gate of said second MOS device, wherein said second interconnecting structure comprises a third portion and a fourth portion over said third portion, wherein said third portion is connected to said fourth portion, wherein said first and third portions are provided by a first metal layer, and said second and fourth portions are provided by a second metal layer over said first metal layer, wherein said first metal layer comprises a copper line and a first adhesion layer at a bottom of said copper line and at a sidewall of said copper line; an insulating layer between said first and second metal layers; a passivation layer over said first and second interconnecting structures and over said insulating layer, wherein said passivation layer comprises a nitride; a third interconnecting structure over said passivation layer, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated copper layer having a thickness between 1 and 100 micrometers on said seed layer, wherein said second adhesion layer is under said electroplated copper layer but not at a sidewall of said electroplated copper layer, wherein said third interconnecting structure is connected to said first interconnecting structure through a first opening in said passivation layer, and wherein said third interconnecting structure is connected to said second interconnecting structure through a second opening in said passivation layer, wherein said first opening has a greatest transverse dimension between 0.5 and 20 micrometers, wherein a signal path is between said diffusion layer and said gate, wherein said diffusion layer is connected to said gate through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure; and a first polymer layer over said third interconnecting structure.