Patent ID: 6842848

Claim:
A method for controlling an instruction issuance sequence for a plurality of threads of a multithreaded processor, the method comprising the steps of: associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions; and utilizing the stored value to control the instruction issuance sequence; wherein the multithreaded processor comprises a plurality of concurrently-executing hardware thread units, each of the hardware thread units being configurable to issue one or more instructions per processor clock cycle for a corresponding one of the threads, the stored value for the corresponding thread indicating, for a given one of the hardware thread units, another of the hardware thread units that will be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions, the stored values for the plurality of threads thereby permitting the concurrently-executing hardware thread units to issue instructions in an arbitrary order over consecutive processor clock cycles.