Patent ID: 7969199

Claim:
A logic circuit implemented in a region of an integrated circuit using a reduced pattern complexity design style, said logic circuit comprising: uniform width, elongated, parallel positive and negative supply rails extending in a first direction in a first metal layer; at least six identically shaped, elongated, unbroken, parallel, uniformly spaced and uniform width polysilicon stripes, each polysilicon stripe extending longitudinally in a second direction, perpendicular to the first direction, and spanning substantially the entire distance between opposing positive and negative supply rails; only two elongated diffusion stripes, of different types, both located between said opposing positive and negative supply rails, a first of said diffusion stripes extending in the first direction in a first region proximate to the positive supply rail, and a second of said diffusion stripes extending in the first direction in a second region proximate the negative supply rail; between each pair of adjacent polysilicon stripes, at least first and second elongated segments extending longitudinally in the second direction in the first metal layer, the first elongated segment located within the first region, and the second elongated segment located within the second region; located in a third region between said first and second regions, a plurality of third elongated segments extending longitudinally in the second direction in the first metal layer, each of said third elongated segments overlying a respective one of said polysilicon stripes; multiple connecting segments, including plural elongated connecting segments extending longitudinally in the first direction in the first metal layer and plural elongated connecting segments extending longitudinally in the first direction in a second metal layer; wherein (i) the connecting segments provide connections that implement logic function(s); and (ii) a region bounded by the opposing supply rails and outermost polysilicon stripes is substantially fully populated with connecting segment(s) and/or dummy feature(s) in the first metal layer, but not substantially fully populated with connecting segment(s) and/or dummy feature(s) in the second metal layer.