Patent ID: 7501341

Claim:
A method for providing an interconnect array pattern, comprising: obtaining an interconnect pattern, the interconnect pattern having at least ten interconnect locations, one of the at least ten interconnect locations being for a power interconnect, another one of the at least ten interconnect locations being for a ground interconnect, and at least eight remaining interconnect locations of the at least ten interconnect locations being for additional interconnects to provide at least eight additional interconnect locations for signals and not being for either power or ground, one of either the ground interconnect or the power interconnect being located in a medial region of the interconnect pattern; a first two of the at least eight additional interconnect locations located horizontally adjacent to the medial region, one of the first two being located on a right side of the medial region, another one of the first two being located on a left side of the medial region; a second two of the at least eight additional interconnect locations located vertically adjacent to the medial region, one of the second two being located on a top side of the medial region, another one of the second two being located on a bottom side of the medial region; an offset region of the at least ten interconnect locations located diagonally adjacent to one of either the first two or the second two of the at least eight additional interconnect locations, the offset region being external to a perimeter defined by the at least eight additional interconnect locations; the one of either the power interconnect or the ground interconnect that is not located in the medial region being located in the offset region; and repeatedly applying the interconnect pattern to provide at least a portion of the interconnect array pattern.