Patent ID: 7924070

Claim:
A power-on reset circuit, connected to an external direct current (DC) power source, to receive DC power signals and generate a reset signal for at least one functional chip, the power-on reset circuit comprising: a delay circuit comprising a plurality of delay units, structured and arrange to delay the received DC power signals and output a plurality of delayed DC power signals, the plurality of delay units each comprising: a first delay unit to delay the received DC power signal and output a first delayed signal, the first delay unit comprising a first capacitor and a first resistor connected in series between the external DC power source and ground; and a second delay unit to delay the received DC power signal and output a second delayed signal, the second delay unit comprising a second resistor and a second capacitor connected in series between the external DC power source and ground; a combination circuit connected to the delay circuit, to combine the plurality of delayed DC power signals together to generate a combination signal; and a shaping circuit connected to the combination circuit, the shaping circuit operable to be turned on and off according to the combination signal, and operable to output the reset signal.