Patent ID: 7943499

Claim:
A method, comprising: forming a transistor having source/drain regions, sidewalls, and a polysilicon gate electrode; forming a layer of Spin-On-Glass in contact with said source/drain regions, said sidewalls, and said polysilicon gate electrode; removing a portion of said Spin-On-Glass layer, wherein said removed portion is the portion of said Spin-On-Glass layer that extends above a top surface of said polysilicon gate electrode; performing a pre-clean of said Spin-On-Glass and said top surface; forming a layer of silicidation metal over said Spin-On-Glass, said sidewalls, and said polysilicon gate electrode; performing a first silicide anneal; removing unreacted portions of said silicidation metal layer; performing a second silicide anneal to fully silicide said polysilicon gate electrode; and removing all remaining portions of said Spin-On-Glass layer.