Patent ID: 7579878

Claim:
A comparator comprising a differential pair of transistors for (a) providing a first stage of amplification and (b) receiving inverting and non-inverting input signals, a current-tail transistor coupled to the differential pair of transistors and configured to have a current flow that is substantially equal to the sum of the currents flowing in each of the differential pair of transistors, an output transistor having a grounded node, the output transistor coupled to the differential pair of transistors for (a) providing a second stage of amplification and (b) transitioning an output signal from a low level state to a high level state, when the non-inverting input signal is higher than the inverting input signal, and a feedback transistor coupled to the current-tail transistor for establishing the currents flowing in each of the differential pair of transistors, wherein an output node comprising either a drain or a collector of one of the differential pair of transistors is directly connected to an input node of the current-tail transistor, and an output node of the other one of the differential pair of transistors is connected to an input node of the output transistor.