Patent ID: 8531001

Claim:
A complementary transistor inverter circuit comprising: a semiconductor-on-insulator (SOI) substrate; a lateral PNP bipolar transistor fabricated on the SOI substrate, the lateral PNP bipolar transistor including a PNP base, a PNP emitter, and a PNP collector; a lateral NPN bipolar transistor fabricated on the SOI substrate, the lateral NPN bipolar transistor including a NPN base, a NPN emitter, and a NPN collector; and a NPN extrinsic base region abutting the NPN base, the NPN extrinsic base region being a heavily-doped p-type semiconductor region; and wherein the NPN base is a p-type semiconductor region; wherein the NPN emitter and the NPN collector are heavily-doped n-type semiconductor regions separated by the NPN base; and wherein the NPN base, the NPN emitter, and the NPN collector abut a buried insulator of the SOI substrate.