Patent ID: 7893980

Claim:
A Complementary Metal-Oxide-Silicon (CMOS) image sensor comprising: a two-dimensional array of a plurality of unit pixels, each unit pixel having a photo diode and transistors; a row decoder, the row decoder assigning row addresses, the row decoder having a plurality of row decoder cells, each of the row decoder cells including an address signal input line, a transfer signal input line, a selection signal input line, a reset signal input line, a reset gate signal output unit, a selection gate signal output unit, and a transfer signal output line; a column decoder, the column decoder assigning column addresses to corresponding pixels in a row selected by the row decoder; and a reduction rate measurement unit, the reduction rate measurement unit measuring a rate of reduction between outputs from first to n-th row data that are sequentially output from the CMOS image sensor according to an operation of the row decoder, wherein n is a natural number, wherein the reset gate signal output unit outputs a reset gate signal that is generated in response to a reset signal, which is entered through the reset signal input line, and an address signal, which is entered through the address signal input line, the selection gate signal output unit outputs a selection gate signal that is generated in response to a selection signal, which is entered through the selection signal input line, and the address signal, which is entered through the address signal input line, and the transfer signal output line outputs a transfer signal which is entered through the transfer signal input line, wherein the transfer signal is directly output from the transfer signal input line to the transfer signal output line.