Patent ID: 8097500

Claim:
A method for fabricating a complementary metal-oxide-semiconductor device comprising an n-type metal-oxide-semiconductor device and a p-type metal-oxide-semiconductor device, the method comprising: fabricating the n-type metal-oxide-semiconductor device using a gate first process, the n-type metal-oxide-semiconductor device comprising a first polysilicon layer and a first silicide layer deposited on the first polysilicon layer; and fabricating the p-type metal-oxide-semiconductor device using a gate last process without exposing the first polysilicon layer of the n-type metal-oxide-semiconductor device, the p-type metal-oxide-semiconductor device comprising a second polysilicon layer and a second silicide layer deposited on the second polysilicon layer, wherein the fabricating the p-type metal-oxide-semiconductor device comprises: creating a trench in a region of the p-type metal-oxide-semiconductor device; lining the trench with a layer of p-type metal; depositing a tungsten layer over the layer of p-type metal; depositing a silicon nitride layer over the n-type metal-oxide-semiconductor and the p-type metal-oxide-semiconductor device, prior to creating the trench; and depositing an oxide layer over the silicon nitride layer, wherein creating the trench comprises: etching the oxide layer down to the silicon nitride layer above the n-type metal-oxide-semiconductor device and the p-type metal-oxide-semiconductor device; etching the silicon nitride layer above the p-type metal-oxide-semiconductor device only; and etching the second silicide layer without etching the first silicide layer; etching the second polysilicon layer without etching the first polysilicon layer; and etching a titanium nitride layer in the region of the p-type metal-oxide-semiconductor device only.