Patent ID: 7394300

Claim:
A delay line, comprising: an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal; and a plurality of set delay cells coupled in series with the adjustable delay cell that delay transmission through the set delay cells of an input signal to the respective set delay cells an amount that does not vary responsive to the control signal; wherein the adjustable delay cell comprises: a buffer that adjusts the speed at which the input signal to the adjustable delay cell is transmitted responsive to the control signal; and a multiplexer that selects and outputs an output of the buffer or a second input signal, responsive to a select signal; and wherein the buffer comprises: a first inverter that inverts the input signal to the adjustable delay cell; a driver that directly receives the input signal to the adjustable delay cell and outputs a signal having the same value as a value of the inverted signal output from the first inverter when activated by the control signal; and a second inverter that has an input coupled to the output signal of the driver and the signal output from the first inverter that inverts the input signal of the second inverter and wherein the output signal of the second inverter is generated at a rate that is greater when the driver is activated by the control signal.