Patent ID: 7463266

Claim:
A graphics controller, comprising: a memory; a serial interface for receiving coded serial data, the serial interface including, coded data detection logic configured to detect a transition of a command signal subsequent to receipt of a command code selecting the graphics controller; and decode circuitry configured to decode the coded serial data in response to the transition of the command signal; a bus enabling communication between the memory and the serial interface; a first register; and a second register, wherein the first register acts as a data port for a memory address programmed into the second register; wherein the decode circuitry includes, a first multiplexer configured to select one of a plurality of inputs, the plurality of inputs including the coded serial data; a second multiplexer having two inputs, a first input being an output of the first multiplexer, a second input being an inverted output of the first multiplexer; wherein the first multiplexer is configured to select the one of the plurality of inputs according to a number of times a most significant bit of the coded serial data is repeated.