Patent ID: 7278072

Claim:
A test auxiliary device for testing a RAM memory circuit containing a multiplicity of memory cells, an input/output device for receiving and outputting memory data, having an address input for applying address information items, and having a selection device for selecting groups of n ≧1 memory cells depending on the address information being applied and for one of writing in and reading out a group of n data at the respectively selected memory cell group, the test auxiliary device comprising: a test control device for applying control, data, and address information items to the selection device; in a test write operation, said test control device applying subsequentially test data for j subsequent write cycles at a first clock speed; in each write cycle, the selection device selecting m memory cell groups, where j and m are in each case integers ≧2, and writing subsequentially, on a group by group basis, one of said test data as an identical datum to all of the memory cells of the m selected memory cell groups at a second clock speed faster than said first clock speed; in a test read operation, said test control device carrying out j subsequent read cycles at a third clock speed; in each read cycle, the selection device reading data subsequentially, on a group by group basis, from the m selected memory cell groups as a read data block including m*n data at a fourth clock speed faster than said third clock speed; an evaluation device determining and providing a compressed test result indicating if all of the m*n data of the read data block correspond to the identical datum written therein; and said evaluation device outputting subsequentially said compressed test result.