Patent ID: 8390487

Claim:
An analog-to-digital converter (ADC) system for converting an input, comprising: a pipeline including successively-cascaded signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of the input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration, wherein for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage, the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage, and the amplified error is one of (a) amplified in a second configuration of following signal converter stages and (b) digitized in a first configuration by the ADC starting from one of the following signal converter stages, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.