Patent ID: 8665634

Claim:
A semiconductor memory device, comprising: a memory cell array including memory cells that are disposed at intersections of a plurality of first lines and a plurality of second lines, the plurality of first lines and second lines being formed so as to intersect one another, and each of the memory cells having a rectifying element and a variable resistance element connected in series; and a control circuit configured to selectively drive the first lines and the second lines, the control circuit being configured to, when performing an operation to change retained data of a selected memory cell selected from among a plurality of the memory cells, apply a first voltage to a selected first line which is a first line connected to the selected memory cell and apply a second voltage to a selected second line which is a second line connected to the selected memory cell, apply a third voltage to a non-selected first line which is a first line other than the selected first line, and apply a fourth voltage which is larger than the third voltage to a non-selected second line which is a second line other than the selected second line, an absolute value of a difference between the third voltage and the fourth voltage being set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage, and the control circuit being configured to increase a value of the offset voltage as the absolute value of the difference between the first voltage and the second voltage increases.