Patent ID: 8212296

Claim:
A semiconductor device having a vertical MOS transistor having a channel of a first conductivity type and formed by burying a gate electrode in a semiconductor substrate, a planar MOS transistor having a channel of the first conductivity and having a gate electrode formed on said semiconductor substrate, and a planar MOS transistor having a channel of a second conductivity and having a gate electrode formed on said semiconductor substrate, said semiconductor device, comprising: said vertical MOS transistor having said channel of the first conductivity type, and having said gate electrode having a lamination structure in which an electrode layer containing an impurity of the first conductivity type introduced thereto, and an electrode layer containing no impurity introduced thereto are formed in this order; said planar MOS transistor having said channel of the first conductivity type, and having said gate electrode having a lamination structure in which an electrode layer containing an impurity of the first conductivity type introduced thereto, and an electrode layer containing no impurity introduced thereto are formed in this order; said planar MOS transistor having said channel of the second conductivity type, and having said gate electrode, as an electrode of the second conductivity type, and having a lamination structure in which an electrode layer containing an impurity of the first conductivity type introduced thereto, and an electrode layer containing an impurity of the second conductivity type introduced thereto are formed in this order; and other circuit element(s), other than a transistor, formed either below or above said vertical MOS transistor having said channel of the first conductivity type.