Patent ID: 7471113

Claim:
A driver circuit, comprising: a first driver comprising: a first inverter with a first inverter input lead and a first inverter output lead; a first p-type transistor, one of a source and a drain of the first p-type transistor connected to a HIGH voltage source, the other of the source and the drain of the first p-type transistor connected to a driver output node, the gate of the first p-type transistor connected to the first inverter output lead; a pull-down circuit comprising: a second inverter with a second inverter input lead and a second inverter output lead, the second inverter input lead connected to the first inverter output lead; a first n-type transistor, one of a source and a drain of the first n-type transistor connected to the first inverter output lead, the other of the source and the drain of the first n-type transistor connected to a LOW voltage source, the gate of the first n-type transistor connected to the second inverter output lead; a third inverter with a third inverter input lead and a third inverter output lead; a second n-type transistor, one of a source and a drain of the second n-type transistor connected to the driver output node, the other of the source and the drain of the second n-type transistor connected to the LOW voltage source, the gate of the second n-type transistor connected to the third inverter output lead; and a delayed pull-up circuit comprising: a fourth inverter with a fourth inverter input lead and a fourth inverter output lead, the fourth inverter input lead connected to the third inverter output lead; and a second p-type transistor, one of a source and a drain of the second p-type transistor connected to the third inverter output lead, the other of the source and the drain of the second p-type transistor connected to the HIGH voltage source, the gate of the second p-type transistor connected to the fourth inverter output lead.