Patent ID: 7696629

Claim:
A chip-stacked package structure, comprising: a substrate with a first surface and a second surface opposite to the first surface; a first chip set on the first surface of the substrate, wherein the first chip comprises: a first active area and a first rear surface opposite to the first active area, wherein the first active area faces the substrate and is electrically connected to the substrate; and a first patterned circuit layer formed on and directly contacted with the first rear surface and electrically connected to the substrate via at least one bonding wire; a second chip set on the first patterned circuit layer, where the second chip has: a second active area that faces the first rear area; and at least one second bonding pad set on the second active area, wherein the second bonding pad is electrically connected to the first patterned circuit layer and is electrically connected to the substrate via the bonding wire; and a molding compound fills a space between the first chip, the substrate, the first patterned circuit layer and the second chip.