Patent ID: 7247906

Claim:
A semiconductor device, comprising: bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a semiconductor substrate; a bit line interlayer insulating layer overlying the bit line and storage landing pads; a plurality of bit line patterns disposed on the bit line interlayer insulating layer, the bit line patterns each including a bit line and a bit line capping layer pattern; line insulating layer patterns placed on a top surface of the bit line interlayer insulating layer; upper contact holes placed in a region between the bit line patterns and higher than upper surfaces of the bit lines; contact hole spacers covering the side walls of the upper contact holes; lower contact holes self-aligned with the upper contact holes, the lower contact holes extending through the line insulating layer patterns and the bit line interlayer insulating layer, the lower contact holes exposing the storage node landing pads; and storage node contact plugs filling the upper and lower contact holes.