Patent ID: 7652368

Claim:
A semiconductor device comprising: a wiring substrate having a main surface, a back surface opposing to the main surface, a plurality of first electrodes formed on the main surface, a plurality of second electrodes formed on the main surface, a plurality of first external terminals formed on the back surface, and a plurality of second external terminals formed on the back surface, wherein the plurality of second electrodes are arranged closer to a periphery of the main surface of the wiring substrate than the plurality of first electrodes are, and wherein the plurality of second external terminals are arranged closer to a periphery of the back surface of the wiring substrate than the plurality of first external terminals are; a first semiconductor chip having a first upper surface, a first rear surface opposing to the first upper surface, and a plurality of bump electrodes formed on the first upper surface, wherein the plurality of bump electrodes are connected with the plurality of first electrodes, respectively, and wherein the first semiconductor chip is mounted over the wiring substrate through the plurality of bump electrodes in such a manner that the first upper surface of the first semiconductor chip is opposed to the main surface of the wiring substrate; a second semiconductor chip having a second upper surface, a second rear surface opposing to the second upper surface, and a plurality of electrode pads formed on the second upper surface, wherein the second semiconductor chip is mounted over the first semiconductor chip through an adhesive in such a manner that the second rear surface of the semiconductor chip is opposed to the first rear surface of the first semiconductor chip; a plurality of wires electrically connected to the plurality of electrode pads of the second semiconductor chip with the plurality of second electrodes, respectively; a sealing body sealing the main surface of the wiring substrate, the first semiconductor chip, the second semiconductor chip and the plurality of wires; and a plurality of solder bumps formed on the plurality of second external terminals of the wiring substrate, respectively, wherein the plurality of solder bumps are not formed on the plurality of first external terminals of the wiring substrate.