Patent ID: 8762921

Claim:
An apparatus for providing a semiconductor device, comprising: an analysis module configured to receive information pertaining to the semiconductor device, wherein the information includes an optimization parameter specification corresponding to an optimization parameter and at least one target parameter corresponding to the optimization parameter, and wherein the at least one target parameter also corresponds to a physical dimension of the semiconductor device and the physical dimension corresponds to a geometric layout parameter; a G-function processor coupled to the analysis module, wherein the G-function processor is configured to receive at least one of the optimization parameter specification, the at least one target parameter, or the geometric layout parameter, and wherein the G-function processor formulates an ordered relationship representation between two or more of the optimization parameter specification, the at least one target parameter, or the geometric layout parameter and the ordered relationship representation describes a characteristic of the semiconductor device; and a power cell optimizer coupled to receive the ordered relationship representation from the G-function processor, wherein the power cell optimizer includes an optimizer module and the optimizer module transforms the ordered relationship representation to correspond to the optimization parameter and wherein the optimizer module is a multivariate optimizer, the ordered relationship representation is formed so at to be non-monotonic, and wherein the optimization parameter corresponds to a global error minimum in a solution space defined by the ordered relationship representation, and wherein the optimization parameter corresponds to an improved characteristic of the semiconductor device.