Patent ID: 7432736

Claim:
A logic basic cell for forming an output signal from at least three input signals in accordance with a predeterminable logic function, comprising: a first logic function block having two data signal inputs, to which a first input signal and a second input signal can be applied, and having a data signal output for providing a logic combination of the first input signal and the second input signal in accordance with a predeterminable first logic subfunction; a second logic function block having two data signal inputs, to which the first input signal and the second input signal can be applied, and having a data signal output for providing a logic combination of the first input signal and the second input signal in accordance with a predeterminable second logic subfunction; a first logic transistor having a first source/drain terminal, which is coupled to the data signal output of the first logic function block, having a gate terminal, at which a third input signal can be provided, and having a second source/drain terminal, at which the output signal can be provided; and a second logic transistor having a first source/drain terminal, which is coupled to the data signal output of the second logic function block, having a gate terminal, at which a complementary signal with respect to the third input signal can be provided, and having a second source/drain terminal, which is coupled to the second source/drain terminal of the first logic transistor.