Patent ID: 7423459

Claim:
A data bus switching device comprising: first signal synchronization generation means for generating a first mask signal and a first synchronized switching signal based on a switching signal used in selecting either a first clock signal inputted via a first data bus or a second clock signal inputted via a second data bus and based on the first clock signal, the first mask signal and the first synchronized switching signal being synchronous with the first clock signal; second signal synchronization generation means for generating, based on the switching signal and the second clock signal, a second mask signal and a second synchronized switching signal each synchronous with the second clock signal; first clock signal mask means for masking the first clock signal with the first mask signal, thereby generating a first masked clock signal; second clock signal mask means for masking the second clock signal with the second mask signal, thereby generating a second masked clock signal; synchronized switching signal selection means for selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal; masked clock signal selection means for selecting either the first masked clock signal or the second masked clock signal as a selected clock signal based on the selected switching signal; and data signal selection means for selecting either a first data signal or a second data signal based on the selected switching signal and outputting the selected data signal as a selected data signal synchronously with the selected clock signal, the first data signal being inputted via the first data bus and synchronous with the first clock signal, the second data signal being inputted via the second data bus and synchronous with the second clock signal.