Patent ID: 8898050

Claim:
A static voltage drop analyzing apparatus, for measuring a static IR (voltage) drop of a multi-threshold complementary-metal-oxide-semiconductor (MTCMOS) transistor, having a gate terminal and a drain terminal, the apparatus comprising: an estimation module, for estimating a voltage drop tolerance according to voltage drop characteristics of said MTCMOS transistor; a processor, coupled to the estimation module, for selecting a simulation metal layer from a plurality of candidate simulation metal layers according to the voltage drop tolerance, and adding the selected simulation metal layer to said MTCMOS transistor, coupling said gate terminal to said drain terminal; and a measuring module, for measuring a voltage drop of said simulation layer added into said MTCMOS transistor; wherein, the voltage drop measured by the measuring module is a static voltage drop of said MTCMOS transistor, said MTCMOS transistor is disposed in a power gating circuit comprising a switched supply voltage (VDD) for said drain terminal of said MTCMOS transistor and a constant VDD for said gate terminal of said MTCMOS transistor, and the estimation module executes a Simulation Program with Integrated Circuit Emphasis (SPICE) tool to simulate voltage drop characteristics of the MTCMOS transistor to estimate the voltage drop tolerance.