Patent ID: 7526049

Claim:
A data sampling circuit, comprising: a receiver which receives an embedded clock obtained by multiplexing a clock signal and data; a phase comparator which outputs a phase difference signal indicating phase comparison result by performing a phase comparison between the embedded clock and a first reference clock signal; a phase interpolator which adjusts a phase of the first reference clock signal and generates a second reference clock signal having a phase different from the phase of the first reference clock signal by 90°, based on the phase difference signal; a feedback controller which conforms the phase of the first reference clock signal with the phase of the embedded clock by feedback control using the phase comparator and the phase interpolator; a sampling controller which performs phase control of the second reference clock signal at higher speed than the feedback control of the first feedback loop based on the phase difference signal; and a sampling circuit which samples the embedded clock received by the receiver in synchronization with the second reference clock signal after performing phase control of the sampling controller.