Patent ID: 7137092

Claim:
A method of forming, on a computer system, a layout structure of a semiconductor integrated circuit, comprising: preparing a first plurality of types of standard cells having respective logical functions, a first proximity dummy cell, and a second proximity dummy cell in a library; each of the first plurality of types of standard cells including standard cell patterns in a plurality of layers arranged in a standard cell frame having an upper, a lower, a left, and a right side, the first plurality of types of standard cells having a common height defined by distances between the upper and the lower sides of the standard cell frames; the first proximity dummy cell including a first proximity dummy pattern, which does not contribute to a logical function of the semiconductor integrated circuit, in at least one of the plurality of layers arranged in a first proximity dummy cell frame having an upper, a lower, a left, and a right side, the first proximity dummy cell having a height defined by a distance between the upper and the lower sides of the first proximity dummy cell frame of k 1 times the common height of the standard cells, where k 1 is an integer not less than one; the second proximity dummy cell including a second proximity dummy pattern, which does not contribute to the logical function of the semiconductor integrated circuit, in the at least one of the plurality of layers arranged in a second proximity dummy cell frame having an upper, a lower, a left, and right side; selecting a second plurality of types of standard cells required for realizing the logical function of the semiconductor integrated circuit from the first plurality of types of standard cells; forming a channel-less type standard cell array by arranging one or more of each of the second plurality of types of standard cells in rows and columns, an outer perimeter of the standard cell array having vertical and horizontal sides each formed with the sides of the frames of the standard cells arranged in an outer-most portion of the standard cell array; forming first proximity dummy bands by arranging a plurality of the first proximity dummy cells along each of at least some of the vertical sides of the standard cell array such that the upper and the lower sides of the frames of the plurality of first proximity dummy cells are in contact with each other and such that one of the left and the right sides of the frame of each of the plurality of first proximity dummy cells is in contact with a corresponding portion of the vertical sides of the standard cell array; and forming second proximity dummy bands along each of at least some of the horizontal sides of the standard cell array by arranging a plurality of the second proximity dummy cells such that one of the upper and the lower sides of the frame of each of the plurality of second proximity dummy cells is in contact with a corresponding portion of the horizontal sides of the standard cell array.