Patent ID: 8194484

Claim:
A bit line pre-charge circuit providing a pre-charge voltage equal to one half a power voltage to a bit line pair of a dynamic random access memory (DRAM), the pre-charge circuit comprising: a first switching element disposed between a power voltage node at which the power voltage is apparent and a first node, the first switching element being controlled by a first control signal; a first capacitor connected between the first node and ground; a second capacitor connected between a second node and the ground; a second switching element connected between the ground and a node between the first node and the second node, the second switching element also being controlled by the first control signal; a third switching element disposed between the first node and the second node, the third switching element being controlled by a second control signal; and a fourth switching element disposed between the second node and an output node at which the pre-charge voltage is apparent, the fourth switching element being controlled by a third control signal.