Patent ID: 7642551

Claim:
A wafer-level package comprising: a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal; at least one external connection terminal electrically connected to said at least one non-test chip terminal; at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals; at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member; an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; a test history recording part provided in said outer region and connected to said second end of a plurality of said redistribution traces; and input/output terminals for writing into/reading out from said test history recording part, said input/output terminals being exposed from said insulating material.