Patent ID: 7596732

Claim:
A digital storage element comprising: a data input port that provides functional data during a functional mode; a scan input port that provides scan data during a scan mode; a first clock input port that provides a first clock signal during the functional mode and a second clock signal during the scan mode, wherein the first and second clock signals are non-overlapping; a second clock input port that provides a third clock signal; an enable port that indicates the scan mode and the functional mode; a data output port; a scan output port; a master latch including: a first inverter that is coupled to the data input port; a second inverter that is coupled to the scan input port; a first logic gate that is coupled to the first clock port and the enable port; a first pass gate that is coupled to the first inverter and the first logic gate, wherein the first logic gate is adapted to activate and deactivate the first pass gate, and wherein, in the scan mode, the first logic gate deactivates the first pass gate; a second pass gate that is coupled to the second inverter and the second clock input port; and a third inverter that is coupled to the first and second pass gates; a slave latch including: a third pass gate that is coupled to the third inverter and the first clock input port; a fourth inverter coupled between the third pass gate and the data output port; a fifth inverter that is coupled to the third pass gate; and a Second logic gate that is coupled to fifth inverter, the enable port, and the scan output port.