Patent ID: 8649234

Claim:
A semiconductor memory device comprising: a memory cell; and an interface which comprises: a first input circuit which outputs an active first internal signal in response to an active first control signal received by the semiconductor memory device; a second input circuit which outputs an active second internal signal in response to an active second control signal received by the semiconductor memory device while the semiconductor memory device is receiving the active first control signal; a delay circuit which outputs a selection signal in a first state or a second state after the elapse of a first period from when the first control signal becomes inactive or active, respectively; a selection circuit which outputs the first internal signal as an enable signal while receiving the selection signal of the first state, and outputs the second internal signal as the enable signal while receiving the selection signal of the second state; and a third input circuit which outputs an input signal received from the outside of the semiconductor memory device from the interface to the inside of the semiconductor memory device while receiving the active enable signal.