Patent ID: 8497543

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a plurality of element isolations formed in an upper portion of the semiconductor substrate and partitioning the upper portion into a plurality of active areas extending in a first direction; a plurality of first stacked bodies provided on the semiconductor substrate and extending in a second direction crossing the first direction; a second stacked body provided on the semiconductor substrate, located outside a region populated with the plurality of first stacked bodies, and extending in the second direction; and an interlayer insulating film covering the first stacked bodies and the second stacked body, each of the first stacked bodies including: a first electrode provided above each of the active areas; an insulating film provided on the first electrode; and a second electrode provided on the insulating film and extending in the second direction, distance between each of the first stacked bodies and the second stacked body being longer than distance between adjacent ones of the first stacked bodies, a first void being formed in the interlayer insulating film between the first stacked bodies, a second void being formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body, and a lower end of the second void being located above a lower end of the first void, wherein the lower end of the first void is located below an upper surface of the first electrode.