Patent ID: 6993736

Claim:
A method of monitoring pending bugs in circuit under design, said method comprising the steps of: supplying a plurality of test cases to a simulation of a circuit design; supplying the plurality of test cases to a reference model; comparing results from the simulation of the circuit design with results obtained from a reference model for each test case; detecting each test case where results from the simulation of the circuit design differs from the results obtained from the reference model and designating each such test case as a bug; comparing each bug with a pending bug list; updating the pending bug list with non-repetitive new bugs corresponding to test cases directed to implemented behavior of simulation of the circuit design; analyzing for correction bugs in the pending bug list; modifying the simulation of the circuit design attempting to correct bugs in the pending bug list; and repeating said steps of supplying, comparing, detecting, comparing, updating, analyzing and modifying in plurality of iterations until the circuit design is complete and there are no bugs in the pending bug list.