Patent ID: 7071664

Claim:
A low drop out linear voltage regulator, a first and a second power supply, comprising: an error amplifier having a first input coupled to receive a reference voltage, a second input and an output terminal; a first NMOS pass transistor having a source connected to an output terminal of the voltage regulator, a drain coupled to an auxiliary voltage input node, and a gate coupled to the output terminal of the error amplifier; a second NMOS pass transistor having a source connected to the first power supply, a drain coupled to an auxiliary voltage input node, and a gate; an control circuit having a mode select input, a first control signal input, a second control signal input, and an output coupled to the gate of the second NMOS pass transistor, wherein, in a first mode of operation, the first control signal input operable to receive an independent control signal for controlling the second NMOS pass transistor during reverse battery condition, and in a second mode of operation, the second control signal input operable to couple to the output terminal of the error amplifier and the first power supply rail operable to couple to the output terminal of the voltage regulator; a feedback network coupled between the source of the first NMOS pass transistor and the second input of the error amplifier; a voltage supervisor circuit having a reset delay coupled to the output terminal of the voltage regulator, wherein the voltage supervisor circuit being effective to render the voltage regulator non-operational in the event of the voltage supplied by the first NMOS pass transistor falling below a predetermined level; and a third NMOS pass transistor coupled between a reset node and the second power supply rail, the third NMOS pass transistor biased by the voltage supervisor circuit.