Patent ID: 8730745

Claim:
A semiconductor memory device comprising: a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the first direction; a plurality of second interconnects which extend in the second direction and are arranged in the first direction; a plurality of first storage modules which are formed in regions where the first interconnects and the second interconnects cross; a first interconnect control module which supplies a voltage to the first interconnects, detects a first current flowing in the first interconnects, and outputs a first voltage corresponding to the first current; a reference voltage generator module which generates a second voltage based on a second current; and a regulator which generates a third voltage based on the first voltage and the second voltage, wherein the regulator comprises a computing unit which includes a first input terminal to which the first interconnect control module inputs the first voltage, a second input terminal to which the reference voltage generator module inputs the second voltage, and an output terminal that outputs a result of doing calculations based on the first voltage and the second voltage, a transistor which includes one end to a current path to which a fourth voltage is applied, a gate to which the output of the computing unit is input, and the other end of the current path which outputs a fifth voltage, a converter which creates voltage information based on the fifth voltage supplied from the transistor, and a voltage generator module which generates the third voltage based on the voltage information.