Patent ID: 8305007

Claim:
A circuit comprising: an analog-to-digital converter (ADC) core comprising an input to receive an input signal and an output to provide a first digital value having a first number of bits, the ADC core to generate the first digital value based on the input signal and an accuracy configuration of the ADC core; an encoder to generate a second digital value having a second number of bits based on the first digital value and the accuracy configuration of the ADC core, the second number of bits being greater than the first number of bits; and an accuracy controller to adjust the accuracy configuration of the ADC core based on a relationship between the first digital value and at least one threshold; wherein: the ADC core comprises an input adjuster module to at least one of scale and offset the input signal to generate a modified input signal, wherein the ADC core generates the first digital value based on the modified input signal; and the accuracy controller adjusts the accuracy configuration of the ADC core by adjusting a scaling and an offset applied to the input signal by the input adjuster module based on the first digital value.