Patent ID: 7526583

Claim:
A method of checkpointing registers in a microprocessor, comprising: storing register values in a register array of a recovery unit queue, the register array having N number of entries with N corresponding outputs connected to respective inputs of a first N-to-1 multiplexer and connected to respective inputs of a second N-to-1 multiplexer which is separate from the first N-to-1 multiplexer; providing a current read value from a current read entry of the register array to a first input of a 2-to-1 multiplexer which is separate from the first and second N-to-1 multiplexers, wherein the current read entry is output from the first N-to-1 multiplexer responsive to a first select signal pointing to a current read position; in parallel with said providing of the current read value, providing a next read value from a next read entry of the register array to a second input of the 2-to-1 multiplexer, wherein the next read entry is output from the second N-to-1 multiplexer responsive to a second select signal pointing to a next read position; and selectively passing one of the current read value and next read value from the 2-to-1 multiplexer to a capture latch based on an instruction completion signal.