Patent ID: 8310898

Claim:
A semiconductor storage device comprising: a memory cell array comprising a plurality of memory cells in a matrix arrangement, wherein the plurality of memory cells operate at an operating frequency (T cyc ); a plurality of word lines which extend in a row direction of the matrix and which are connected to at least one of the plurality of memory cells; a plurality of bit lines which extend in a column direction of the matrix and which are connected to at least one of the plurality of memory cells, wherein each bit line of the plurality of bit lines conducts a read-out current (I cell ) and has a bit-line capacitance (C); and a row selector configured to multiply-select a number of word lines (N WL ), such that the number of memory cells connected to each of the bit lines (N cell ), divided by the number of word lines multiply-selected by the row selector (N WL ), is less than or equal to four (4) times a power supply voltage (V DD ), times the bit-line capacitance (C), divided by the product of the operating frequency (T cyc ) of the plurality of memory cells, the read-out current (I cell ) of each bit line of the plurality of bit lines, and the number of memory cells connected to each of the bit lines (N cell ), wherein the row selector is further configured to: receive a preset redundant address signal; determine whether the redundant address signal matches an address signal among a plurality of address signals of multiply-selected word lines; and deselect a word line corresponding to the matched address signal when the redundant address signal matches an address signal.