Patent ID: 7787305

Claim:
A flash memory device comprising: a flash memory cell array having flash memory cells arranged with word and bit lines; a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation; a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array; a writing circuit configured to drive the bit lines selected by conditions in a programming operation; and a control logic block configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation, wherein the control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage in response to the selected step increment, wherein the selected step increment of the programming voltage includes a first step increment adopted in a programming period of a convergence programming mode and a second step increment adopted in an incremental step pulse programming (ISPP) mode, wherein the first step increment is larger than the second step increment.