Patent ID: 8063416

Claim:
A semiconductor device having an upper-layer power supply wiring formed in an upper layer within the semiconductor device, a first power supply cell, and a second power supply cell, wherein the first and second power supply cells each have a power supply wiring and a power supply connection portion, the power supply connection portion is provided in a boundary portion of each of the first and second power supply cells, the power supply wiring is formed in an upper layer higher than the power supply connection portion in the semiconductor device, the power supply wiring and the power supply connection portion partially overlap as the semiconductor device is viewed from the top, the power supply connection portion is electrically connected via a contact to the upper-layer power supply wiring provided in the upper layer higher than the power supply wiring, the power supply wiring of the first power supply cell has a width larger than or equal to a width of an intra-cell power supply wiring in another logic cell in the semiconductor device, and the power supply wiring of the second power supply cell has a width larger than a width of the power supply wiring of the first power supply cell.