Patent ID: 7316935

Claim:
A semiconductor wafer, wherein the wafer is manufactured using a process comprising: forming on a wafer surface, at a first process step, a first die area having a first die, a first test structure, and a second test structure, wherein the first test structure is spaced from the first die by a first gap, and the second test structure is spaced from the first die by a second gap; and forming on the wafer surface, at a second process step, a second die area having a second die, a third test structure, and a fourth test structure, wherein the third test structure is spaced from the second die by a third gap, the third test structure is disposed in the second gap, and the fourth test structure is spaced from the first die by a fourth gap, wherein each of the first, second, third, and fourth test structures are formed on sacrificial regions of the wafer and are part of a plurality of test structures used to test aspects of the wafer prior to separating the wafer into individual dies.