Patent ID: 7375564

Claim:
A delay-locked loop for receiving an external clock signal and synchronizing a phase of a feedback clock signal with a phase of the external clock signal, the delay-locked loop comprising: a phase detector for comparing the phase of the external clock signal with the phase of the feedback clock signal and outputting a phase difference as an error control signal; a delay line, comprising a plurality of delay blocks, each delay block comprising a plurality of delay cells having the same unit time delay, wherein the unit time delay of delay cells from different delay blocks are different, the delay line for receiving the external clock signal, controlling the phase of the external clock signal to obtain an output clock signal and outputting the output clock signal, wherein the number of delay cells in operation is adjusted in response to a shift signal, wherein each delay cell is a differential amplifier having a resistor connected to a power supply voltage, wherein the resistors of the delay cells from different delay blocks have different resistances and the resistors of the delay cells from the same delay block have the same resistance, to vary the unit time delay; and a filter unit for generating the shift signal for selecting the number of delay cells in operation in the delay line, in response to the error control signal.