Patent ID: 7144744

Claim:
A method for fabricating a magnetoelectronic memory element structure, the method comprising: fabricating an interconnect stack in electrical communication with at least one transistor; forming a digit line disposed at least partially within a first dielectric material layer, said first dielectric material layer overlying said interconnect stack; etching a void space in said first dielectric material layer to expose said interconnect stack; depositing a conductive barrier layer having a first portion and a second portion, said first portion of said conductive barrier layer overlying said digit line and said second portion of said conductive barrier layer disposed within said void space and in electrical communication with said interconnect stack; forming a magnetic memory element layer overlying said first portion of said conductive barrier layer; depositing an electrode layer overlying said magnetic memory element layer; patterning and etching said electrode layer to form an electrode overlying said digit line; and patterning and etching said magnetic memory element layer wherein the step of patterning and etching said electrode layer to form an electrode overlying said digit line is performed before the step of and etching said magnetic memory element layer.