Patent ID: 7063975

Claim:
A method for fabricating a power semiconductor device, comprising: forming a shallow trench on a substrate having a first surface and a second surface, the shallow trench having a first depth and a width, the width of the shallow trench being greater than the first depth of the shallow trench; forming a doped region provided proximate the first surface of the substrate and having a second depth; forming a source region provided within the doped region and proximate the first surface; and forming a gate structure provided adjacent the source region, the gate structure including a first portion provided within the shallow trench and a second portion provide outside of the trench, wherein the first portion includes a lateral extension and that is parallel to the first and second surface of the substrate, wherein the lateral extension of the first portion is at least 2.5 times greater than the first depth of the shallow trench, wherein forming the shallow trench includes: etching the substrate to form an intermediate trench having a third depth that is less than the first depth; forming a first oxide layer within the intermediate layer; and removing the oxide layer formed within the intermediate trench, wherein a resulting trench from the removal of the oxide layer has a fourth depth that is greater than the third depth.