Patent ID: 7142442

Claim:
A memory including at least one row, the at least one row comprising: a first row segment having a first plurality of memory cells coupled to a first dataline segment; a second row segment having a second plurality of memory cells coupled to second dataline segment; a control circuit providing read and write control signals to enable driving of the first row segment and the second row segment, the control circuit connected to the first row segment to enable data propagation in compliance with the read and write control signals; and a dataline driver connected between the first and second dataline segments and having inputs connected to the control circuit to receive the read and write control signals, the dataline driver configurable to propagate data only in a first direction from the second row segment to the first row segment toward the control circuit during a read operation and to propagate data only in a second direction from the first row segment to the second row segment from the control circuit during a write operation.