Patent ID: 7411834

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells disposed in rows and columns; a plurality of word lines, arranged corresponding to the memory cell rows, each having the memory cells on a corresponding row connected; a sub-decoding circuit including a plurality of sub-decoding elements arranged corresponding to the word lines, for setting voltages of the word lines in accordance with a set of source signals and a set of gate signals; a block decoding circuit for generating the source signals in accordance with an address signal; and a gate decoding circuit for generating the gate signals in accordance with an address signal, each sub-decoding element comprising first and second transistors of a same conductivity type each having a gate, a source and a drain, the first and second transistors receiving first and second gate signals from said gate decoding circuit at the respective gates, receiving first and second source signals from said block decoding circuit at the respective sources, and coupled to a corresponding word line at the drains in common; and a substrate potential setting circuit for setting a voltage of a substrate region in which the sub-decoding elements are formed separately from a source potential of the transistors of the sub-decoding elements.