Patent ID: 7454693

Claim:
An LDPC decoder that receives input words and provides output words to an output memory, the output words representing a decoding of the input words, the decoder comprising: a determined number of processing units operating in parallel, capable of receiving first messages and of providing second messages based on a processing of the first received messages; first and second single-port memories; first means for: reading first words both from the first single-port memory and from the second single-port memory, each first word comprising a juxtaposition of first messages in a number equal to said determined number; providing first messages to the processing units, each first message being based on at least one of the first words and/or at least one of the input words; forming second words, each second word comprising a juxtaposition of second messages provided by the processing units in a number equal to said determined number; and writing at least some of the second words into the first and second single-port memories, said first means being capable, for at least some of the first words and second words, of reading the at least some of the first words from the first single-port memory and of simultaneously writing the at least some of the second words into the second single-port memory or of reading the at least some of the first words from the second single-port memory and of simultaneously writing the at least some of the second words into the first single-port memory; and second means for providing the output words based, at least in part, on the second messages provided by the processing units.