Patent ID: 8614143

Claim:
A method for forming a metal level and a via level within a single inter-level dielectric layer, comprising: providing a semiconductor substrate comprising a conductive layer positioned on the substrate; forming an inter-level dielectric layer of a dual damascene structure on the semiconductor substrate; performing a lithography process that forms a photoresist layer above the inter-level dielectric to define a pattern of a via hole having a width of a first critical dimension and a plurality of metal line trenches with widths of a second critical dimension abutting the via hole, wherein the first critical dimension is larger than the second critical dimension, and wherein the metal line trenches extend in parallel, laterally spaced positions from the via hole; and performing a first etching process according to the pattern of the photoresist layer to remove the inter-level dielectric layer not covered by the pattern of the photoresist layer, the removal proceeding at different vertical etch rates for the via hole and the plurality of metal line trenches determined by differences in the first and second critical dimensions, so as to form the via hole by etching vertically at a first etch rate from a top of the inter-level dielectric layer down to the conductive layer and to simultaneously form the plurality of metal line trenches by etching vertically at a second etch rate from the top of the inter-level dielectric layer down to a depth only within an upper part of the inter-level dielectric layer.