Patent ID: 7570651

Claim:
An on-chip interconnection apparatus, comprising: a plurality of programmable routing elements; a plurality of communication segments coupled between said routing elements and a plurality of system units; wherein the plurality of programmable routing elements and the plurality of communication segments are adapted for integration into very large scale integrated (VLSI) circuit designs; wherein a first traffic stream is transferred between two of said plurality of said system units through at least one of said plurality of programmable routing elements and at least one of said plurality of segments; wherein a second traffic stream is transferred between two of said plurality of said system units through at least one of said plurality of programmable routing elements and at least one of said plurality of segments; and wherein said plurality of programmable routing elements implement a fabric schedule based on a global classification of said first traffic stream and said second traffic stream said fabric schedule being determined using optimization criterion based on two or more factors from a set consisting of bandwidth, quality of service, traffic priority class, cost, scalability for future enhancement, power consumption, physical size, development time, process technology, resource utilization and efficiency.