Patent ID: 7340667

Claim:
An apparatus comprising: a logic circuit configured to generate a check signal in response to a data signal decoded from a series of frames, each of said frames comprising a plurality of logical transmission units (LTUs), each of said LTUs comprising (a) a payload and (b) a field; a compare circuit configured to generate a compare signal in response to said check signal and said field corresponding to each of said LTUs in said data signal; a control circuit configured to generate a control signal indicating either a valid status or an invalid status of each of said payloads in response to a data valid signal and said compare signal, wherein said control signal indicates said invalid status when said data valid signal indicates a frame error and said compare signal indicates said invalid status; and a memory interface configured to generate an output data signal in response to said control signal, wherein said memory interface (i) stores each of said payloads when received and (ii) overwrites at least one of said payloads having said invalid status such that said payloads have a different sequence as stored than as in said frame.