Patent ID: 8344769

Claim:
A jitter suppression circuit using a digital phase locked loop, wherein shortening of a pull-in time and suppression of a jitter is achieved by determining whether the loop is in a synchronous state from a phase difference between an input clock and an output clock, and changing characteristics of a loop filter according to a determination result, wherein a bandwidth of the loop filter is expanded when judgment has been made that the loop is in an asynchronous state, wherein the bandwidth of the loop filter is narrowed when judgment has been made that the loop is in the synchronous state, wherein the jitter suppression circuit comprises: a clock transferring part by which retiming of an input data is performed; and the digital phase locked loop which suppresses a jitter of an output data of said clock transferring part and the output clock by changing characteristics of the loop filter according to a determination result of whether the loop is in the synchronous state or not, wherein said clock transferring part comprises: a serial/parallel converting circuit which performs serial-to-parallel conversion of input data; a flip-flop circuit which changes timing of parallel data from said serial/parallel converting circuit; and a parallel/serial converting circuit which performs parallel-to-serial conversion of data from said flip-flop circuit, wherein said digital phase locked loop comprises: a phase comparator which compares a phase difference between an input clock of said clock transferring part and the output clock; a numerical control oscillator which supplies a clock signal to said flip-flop circuit and said parallel/serial converting circuit; the loop filter inserted between said phase comparator and said numerical control oscillator; and a parameter selection circuit which selects and changes a parameter of said loop filter according to output of said phase comparator, and wherein said phase comparator comprises: an input-side rising edge detection circuit which detects a rising edge of an input-side phase comparison signal which is generated by dividing said input clock; an output-side rising edge detection circuit which detects a rising edge of an output-side phase comparison signal which is generated by dividing said output signal; a counter which detects a phase difference by counting a period from a rising edge of said input-side phase comparison signal to a rising edge of said output-side phase comparison signal by using a sampling clock.