Patent ID: 7830703

Claim:
A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein: each of the transistors comprises: a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; the semiconductor layers under the respective gate electrodes, the semiconductor layers constituting the transistors in the SRAM cell units, have an equal width in a direction parallel to a substrate plane and perpendicular to a channel length direction; and at least one of a number or a height of the semiconductor layer of each of the first and second driving transistors is larger than that of at least one of each of the load transistors or each of the access transistors, such that the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.