Patent ID: 6906653

Claim:
D/A converter including n+1 (n is a natural number) capacitors in total consisting of one terminating capacitor (C 0 ) serving as a unit capacitor and n binary-weighted capacitors (C 1 - 4 ) that are subjected to binary weighting to the unit capacitor in the ratio of 1:2:4: . . . :2 (n−1) , and, an inverting amplifier (INV 1 ) for obtaining amplified output, the input terminal of the inverting amplifier being connected to first terminal side of the n+1 capacitors in common, further comprising: a feedback switching means (SWR 5 ) provided between the input and output of the inverting amplifier (INV 1 ) and being in a closed state on reset operation period (T 1 ) and in an open state on output operation period (T 2 ); a switching means for terminating operation (SWR 0 ) supplies one of two main reference voltages (VB,VT) to second terminal side of the terminating capacitor (C 0 ) on the reset operation period (T 1 ), and then, makes connection of the second terminal side of the terminating capacitor (C 0 ) to the output of the inverting amplifier (INV 1 ) on the output operation period (T 2 ); a plurality of switching means for input operation (SWD 1 - 4 ,SWR 1 - 4 ) makes selection of one of the two main reference voltages (VB,VT) to be provided for the second terminal side of the n binary-weighted capacitors (C 1 - 4 ) depending on digital data (D 1 - 4 ) on the reset operation period (T 1 ), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C 1 - 4 ) to the output of the inverting amplifier (INV 1 ) on the output operation period (T 2 ).