Patent ID: 8704553

Claim:
A comparator comprising: a differential pair of transistors, wherein each transistor has a body coupled to an input signal, a gate coupled to a clock signal, a source coupled to a first reference voltage, and a drain; an active load coupled to the drain of each transistor of the differential pair of transistors; a first cross-coupled pair of transistors, wherein each transistor has a source coupled to the first reference voltage, a gate coupled to an inverse of the clock signal, and a drain, and wherein the body of one of the transistors of the first cross-coupled pair of transistors is coupled to the drain of the other of the transistors of the first cross-coupled pair of transistors, and the body of the other of the transistors of the first cross-coupled pair of transistors is coupled to the drain of the one of the transistors of the first cross-coupled pair of transistors; and a second cross-coupled pair of transistors, wherein each transistor has a source coupled to a second reference voltage, a gate coupled to the clock signal, and a drain coupled to the drains of the first cross-coupled pair of transistors, and wherein the body of one of the transistors of the second cross-coupled pair of transistors is coupled to the drain of the other of the transistors of the second cross-coupled pair of transistors, and the body of the other of the transistors of the second cross-coupled pair of transistors is coupled to the drain of the one of the transistors of the second cross-coupled pair of transistors.