Patent ID: 7902677

Claim:
A composite layered chip package comprising a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other, wherein: each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body; the main body has a main part, the main part including at least one first-type layer portion and having a top surface and a bottom surface; for any two vertically adjacent subpackages, the main body of a lower subpackage further has a plurality of first terminals that are arranged on the top surface of the main part and electrically connected to the wiring, while the main body of an upper subpackage further has a plurality of second terminals that are arranged on the bottom surface of the main part and electrically connected to the wiring, and the plurality of second terminals of the main body of the upper subpackage are electrically connected to the plurality of first terminals of the main body of the lower subpackage; the main part of the main body of at least one of the plurality of subpackages further includes at least one second-type layer portion; each of the first-type layer portion and the second-type layer portion includes a semiconductor chip; and the first-type layer portion further includes a plurality of electrodes, each of the electrodes being electrically connected to the semiconductor chip and having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, whereas the second-type layer portion does not include the plurality of electrodes, and the wiring is electrically connected to the end faces of the plurality of electrodes.