Patent ID: 8358539

Claim:
A semiconductor storage device comprising: a memory cell array having a plurality of memory strings arranged therein, each of the memory strings including a plurality of electrically rewritable memory transistors, selection transistors operative to select a memory transistor, and a back-gate transistor, each of the plurality of memory strings comprising: a body semiconductor layer having a columnar portion extending in a vertical direction to a substrate; an electric charge storage layer formed to surround a side surface of the columnar portion; a first conductive layer formed to surround a side surface of the columnar portion as well as the electric charge storage layer, and functioning as a word line connected to a control electrode of the memory transistor; a second conductive layer formed on a side surface of the columnar portion via an insulation film, and functioning as a selection gate line connected to a control electrode of a respective one of the selection transistors; a third conductive layer arranged with a first direction taken as its longitudinal direction, connected to one end of a respective one of the memory strings, and functioning as a bit line; a fourth conductive layer arranged with the first direction taken as its longitudinal direction, connected to the other end of a respective one of the memory strings, and functioning as a source line; and a fifth conductive layer arranged with the first direction taken as its longitudinal direction, connected to a control gate of the back-gate transistor and functioning as a control electrode of the back-gate transistor; wherein the memory transistors included in a first memory string as one of the memory strings connected to a pair of the third conductive layer and the fourth conductive layer are commonly connected to the first conductive layers connected to the memory transistors included in a second memory string as one of the memory strings, the second memory string being connected to the same pair of the third conductive layer and the fourth conductive layer as that of the first memory string, and adjacent to the first memory string, and the back-gate transistor in the first memory string and the back-gate transistor in the second memory string are each connected to independent of the fifth conductive layers.