Patent ID: 8664071

Claim:
A method of manufacturing a castellated-gate MOSFET tetrode device comprising the steps of: pre-conditioning a starting semiconductor substrate; applying active layer pad nitride masks to form trench isolation islands in said substrate; forming a plurality of channel elements by etching a plurality of spaced gate slots to a first predetermined depth into said substrate; filling said slots with a dielectric material; clearing out a predetermined area of said dielectric material within said gate slots to form a primary channel, a gate slot spacer and a bottom gate; depositing a first gate dielectric; filling said slot regions with a first conductive gate material and connecting them together at their upper end surfaces with a first top gate layer; implanting source and drain regions at opposite end portions of said spaced, channel elements, and having a predetermined separating distance along said elements from said primary channel to form one or two secondary channels; deposing a planarized interlevel dielectric layer having a top surface; clearing out one or two predetermined regions adjacent to said first top gate, including a portion of said gate slot spacer; depositing a second gate dielectric; filling in said adjacent regions with a second conductive gate material to form a second gate structure; and planarizing said second conductive material to be coincident with said top surface of said interlevel dielectric layer.