Patent ID: 8203199

Claim:
An integrated circuit package, comprising: a first leadframe generally defining a first plane and having a first plurality of electrical leads adapted to couple to one or more contacts on an associated primary die, said first plurality of electrical leads having a first set of one or more gaps therebetween, a die attach pad adapted to couple to the associated primary die and having a first pair and a second pair of substantially parallel edges that extend along substantially the full length and full width of the die attach pad, and a plurality of tie bars coupled to said die attach pad, wherein both of said first pair and exactly one of said second pair of substantially parallel edges include at least one tie bar, while the other of said second pair of substantially parallel edges includes zero tie bars; a second leadframe generally defining a second plane substantially parallel to and separated from said first plane, said second leadframe being generally positioned above or below said first leadframe, said second leadframe having a second plurality of electrical leads coupled to one or more contacts on said associated primary die, one or more contacts on said first leadframe, or both, said second plurality of electrical leads having a second set of one or more gaps therebetween; and an encapsulant that binds and protects various portions of said first leadframe and said second leadframe within an encapsulated region such that at least some of said first plurality of electrical leads and first set of gaps and at least some of said second set of electrical leads and second set of gaps protrude from said encapsulated region, wherein no encapsulant flash remains in any of said first set of gaps or second set of gaps that protrude from said encapsulated region.