Patent ID: 6885055

Claim:
A double-gate FinFET device, comprising: a bulk silicon substrate; a Fin active region which is a wall-shape single crystalline silicon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate; a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate; a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer; a first oxide layer which is formed on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide; a gate which is formed on said first and second oxide layer; a source/drain region which is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the thickness of said gate oxide layer is between 0.5 nm and 10 nm, and the thickness of said first oxidation layer is between 0.5 nm and 200 nm.