Patent ID: 8923315

Claim:
An apparatus comprising a packet router that includes: an input buffer module configured to receive packets from a set of input ports; a set of output buffer modules, each configured to direct packets stored therein to a respective set of output ports; and one or more interconnect fabrics configured to transport packets from the input buffer module to the set of the output buffer modules, wherein: each of said one or more interconnect fabrics is disposed to couple a respective first buffer module, a respective second buffer module, and a respective third buffer module and is configured to transport packets from said respective first buffer module to at least one of said respective second and third buffer modules; and said respective first buffer module is configured to: enqueue packets at an end of a queue therein in an order of their arrival to said respective first buffer module; dequeue packets from a head of the queue; advance packets toward the head of the queue when the first buffer module dequeues one or more packets from the head of the queue and transmits the one or more dequeued packets, via the interconnect fabric, to at least one of said respective second buffer module and said respective third buffer module; wherein each enqueued packet has a destination address, transmit the enqueued packet to said respective second buffer module if a most significant bit in the enqueued packet's destination address has a first binary value; transmit the enqueued packet to said respective third buffer module if the most significant bit in the enqueued packet's destination address has a second binary value different from the first binary value, wherein each of said respective second buffer module and said respective third buffer module is configured to: enqueue received packets at an end of a respective queue therein in an order of their arrival to the buffer module; and shorten each enqueued received packet's destination address by removing the most significant bit.