Patent ID: 7652374

Claim:
A semiconductor electronic package, comprising: a circuit chip having an active surface; a plurality of solder bumps disposed on the active surface; a solder paste; and a substrate, including: a first patterned conductive circuit layer comprising a plurality of solder bump pads; and a first insulating layer covering the first patterned conductive circuit layer and defining a plurality of holes exposing the solder bump pads, wherein inside walls of the holes are conductive; wherein: the solder paste is disposed inside the holes; the circuit chip is positioned with the active surface facing the holes in the first insulating layer so that each of the solder bumps is substantially aligned with a corresponding solder bump pad through a corresponding hole; each solder bump penetrates into the solder paste inside the corresponding hole and electrically connects to the corresponding solder bump pad; and the solder paste fills in a space between each of the solder bumps and the conductive inside walls of the corresponding holes thereby increasing contact area between the solder paste and the inside walls.