Patent ID: 7208344

Claim:
A method of making a semiconductor package comprising; providing a semiconductor chip carrier substrate, having a first surface and a plurality of cavities formed in the first surface and wherein each cavity is defined, at least in part, by a bottom surface and at least one sidewall; placing an integrated circuit chip, having bond pads on an upper surface thereof, in each of the cavities formed in the chip carrier substrate, and wherein each semiconductor chip overlies the bottom surface; forming a first dielectric layer over the first surface of the chip carrier substrate and over the integrated circuit chip in each of the cavities wherein the first dielectric layer comprises at least one of a polyimide and BCB; forming a first set of vias in the first dielectric layer and so that each of the first set of vias is aligned with a respective bond pad of the integrated circuit chip; forming electrically conductive traces over the first dielectric layer and so that each one of the electrically conductive traces is electrically connected to at least one of the bond pads of the integrated circuit chip; and, forming a second dielectric layer comprising at least one of a polyimide and BCB over the redistribution traces, and forming a second set of vias in the second dielectric layer so that each of the second set of vias communicates with one of the redistribution traces; and, forming electrically conductive bumps by reflow wherein each electrically conductive bump overlies the second dielectric layer and comprises an unrounded portion extending into one of the vias formed in the second dielectric layer and so that the electrically conductive bump is electrically connected to one of the redistribution traces.