Patent ID: 8554529

Claim:
A method of simulating an integrated circuit device under test (“DUT”), wherein the DUT includes at least first and second terminals, the method comprising: applying first and second probe pulses to the first and second terminals, respectively, and recording time-dependent reactions of the first and second terminals in response thereto, wherein the time-dependent reactions have decay times and are recorded in table entries that store information about the first and second probe pulses; using the table entries to calculate, by a device, first reactions of the first and second terminals in response to values of the first and second terminals at a first time step; and using the table entries to calculate, by the device, second reactions of the first and second terminals in response to values of the first and second terminals at a second time step; wherein at least one of the first reactions has a respective decay that is longer than the first time step and continues during the second time step and contributes to at least one of the second reactions; wherein the first and second reactions include steady-state components and time-dependent components; wherein using the table entries to calculate the steady-state components of the second reactions includes performing interpolation from the table entries in response to the values of the first and second terminals at the second time step; and wherein using the table entries to calculate the time-dependent components of the second reactions includes performing summation from the table entries in response to the values of the first and second terminals at the second time step and in response to the first reactions.