Patent ID: 7170780

Claim:
A semiconductor memory device comprising: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, each memory cell storing one of first, second, third and fourth data defined as being arranged in order of threshold voltage height; a read/write circuit configured to read data of and write data in said memory cell array; and a controller configured to control said read/write circuit so as to execute first and second write sequences, the first write sequence being defined as to write the second data into a first selected memory cell or cells within a selected page of said memory cell array which has been initialized in the first data state, the second write sequence being defined as to write the fourth data into a second selected memory cell or cells within memory cells storing the second or first data in the selected page, and successively write the third data into a third selected memory cell or cells within memory cells storing the first or second data in the selected page, wherein said memory cell array comprises: a plurality of word lines, to each of which control gates of memory cells arranged in a first direction are coupled; and a plurality of bit lines each disposed to be selectively coupled to a drain of memory cells arranged in a second direction, and wherein said read/write circuit comprises: a row decoder configured to selectively drive the word lines of said memory cell array; a sense amplifier circuit coupled to the bit lines of said memory cell array to be able to hold one page data; and a data cache configured to transfer data in parallel between itself and the sense amplifier and to be able to hold one page data.