Patent ID: 7961453

Claim:
A multilayer chip capacitor comprising: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer therebetween in the capacitor body and having a single lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction, the external electrodes having different polarities are alternately disposed on the bottom surface, and all of the leads extended to the bottom surface are disposed in a single zigzag line passing the three or more external electrodes along the lamination direction, wherein the capacitor is a 4-terminal capacitor, six internal electrodes sequentially disposed in the lamination direction form one block, and the block is repeatedly laminated.