Patent ID: 8171047

Claim:
A computer apparatus comprising: a plurality of nodes each having a memory and at least one processor with a processor arithmetic logic unit (ALU), wherein the plurality of compute nodes further comprise a combining network adapter (CNA) that is a hardware network adapter for performing collective operations, wherein the CNA comprises an arithmetic logic unit (ALU) that operates on data in registers in the CNA and stores the results in a results buffer, and wherein the CNA contributes to a collective operation by operating on data in the registers received from the child nodes with local data and passing the results in the results buffer to a parent node; wherein the collective operation is an all reduce operation that combines data provided from the child nodes in registers of each CNA using a common operation and then returns a combined value in the results buffer on the plurality of compute nodes; a combining network comprising a plurality of networks connecting the plurality of nodes through the CNA on the plurality of nodes, and wherein the collective operation is a logical operation that includes a contribution from the CNA of connected nodes on the combining network; a database residing in the memory of the plurality of nodes; and a query optimizer that optimizes a query to the database to utilize the combining network and the CNA on the plurality of nodes to perform the collective operation to process a portion of the query.