Patent ID: 7277350

Claim:
A memory device comprising: an internal voltage generator configured to generate a plurality of internal voltages; a trim circuit configured to trim each internally generated voltage based on a trim setting; trim control circuitry configured to, for each of the plurality of internally generated voltages: (a) receive a target digital value for the internally generated voltage; (b) compare the target digital value to a current digital value for the internally generated voltage; (c) if the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, adjusting the trim setting based on the difference; (d) repeat steps (b) and (c) until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold; and (e) store the adjusted trim setting in non-volatile storage located on the memory device; whereby the plurality of internally generated voltages are each trimmed independently of each other according to steps (a) through (e).