Patent ID: 7171526

Claim:
A data processing system, comprising: a system bus; a system bus master, coupled to the system bus; a first memory controller for controlling a first memory; a second memory controller for controlling a second memory; and a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller, wherein: the second memory controller comprises arbitration logic for arbitrating between the system bus master and the first memory controller for access to the second memory; when the data is transferred from the first memory controller to the second memory controller, the data is received by the first memory controller from the storage locations within the first memory prior to transferring the data to the second memory controller, and when the data is transferred from the second memory controller to the first memory controller, the data is received by the second memory controller from storage locations within the second memory prior to transferring the data to the first memory controller.