Patent ID: 7342425

Claim:
For use in an electronic circuit, a method of dividing the frequency of an input clock signal having a period P C by an odd positive integer N, comprising the steps of: producing a first signal by clocking a first plurality of D-type flip-flops with the input clock signal, wherein the first signal is true for a time substantially equal to P C *M P and false for time a time substantially equal to P C *(N−M P ), where M P is a positive integer less than (N−1)/2; producing a second signal by clocking a second plurality of D-type flip-flops with the input clock signal, wherein the second signal is true for a time substantially equal to P C *M N and false for a time substantially equal to P C *(N−M N ), where M N is a positive integer less than (N+1)/2 and greater than ((N+1)/2)−(M P +1); and combining the first signal and second signal to produce a divided clock signal having period P C *N.