Patent ID: 7479683

Claim:
A semiconductor structure comprising: a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of said source and drain diffusion regions is separated by a device channel; and a first gate stack of a pFET device located on top of some of said device channels, said first gate stack of said pFET device comprising a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, said insulating interlayer comprises an insulating metal nitride that stabilizes threshold voltage and flatband voltage of said p-FET device to a targeted value and is one of aluminum oxynitride (AlO x N y ), boron nitride (BN), boron oxynitride (BO x N y ), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN) and indium oxynitride (InON); and a second gate stack of an nFET device located on top remaining device channels, said second gate stack of said n-FET device comprising a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.