Patent ID: 7449872

Claim:
A low-drop-out voltage regulator (LDO), comprising: a local reference generator circuit that receives a voltage input signal (V IN ) and outputs a reference voltage signal (V REF ); a buffer circuit that receives the reference voltage signal (V REF ) and outputs an output voltage signal (V OUT ) at an LDO output, the buffer circuit having an operational amplifier with a positive input terminal, a negative input terminal, and an output, the operational amplifier output coupled to the LDO output and the operational amplifier having an input stage that receives the reference voltage signal (V REF ) and the voltage input signal (V IN ), the input stage comprising a voltage input transistor pair, including a first voltage input transistor and a second voltage input transistor, the voltage input transistor pair having sources coupled to each other and to an accurate reference voltage signal input and having gates coupled to each other and to a drain of the first voltage input transistor; an input terminal transistor pair, including a first input terminal transistor and a second input terminal transistor, the first input terminal transistor having a gate and a drain coupled together at the negative input terminal and also coupled to the first voltage input transistor drain, and the second input terminal transistor having a gate coupled to the positive input terminal and a drain coupled to a drain of the second voltage input transistor; and a current source, having a first end coupled to sources of the first and second input terminal transistors and having a second end coupled to ground; an attenuator circuit located between the local reference generator circuit and the buffer circuit; and a comparison device that receives the output voltage signal (V OUT ) and an accurate reference voltage signal (REF), compares the output voltage signal (V OUT ) to the accurate reference voltage signal (REF), and outputs an adjustment signal that signifies tuning necessary in the LDO to adjust output voltage signal (V OUT ) in the direction of a value of the accurate reference voltage signal (REF), wherein a gain of the buffer circuit is adjusted if the output voltage signal (V OUT ) has a value lower than the accurate reference voltage signal (REF); and wherein at least one of a gain of the attenuator circuit and a gain of the buffer circuit is adjusted if the output voltage signal (V OUT ) has a value higher than the accurate reference voltage signal (REF).