Patent ID: 7035145

Claim:
A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising: generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; and generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage being ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the gate voltage ramped with a ramping rate, whereby the selected threshold voltage for each programming state is generated by applying a gate voltage with a different final magnitude, wherein the ramping rate is between approximately 5.5 V/ms and approximately 10.5 V/ms.