Patent ID: 7923756

Claim:
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a well of the first conductivity type formed in a surface of the semiconductor substrate of the first conductivity type; a first MOS transistor of the a second conductivity type formed on the well of the first conductivity type; a second MOS transistor of the second conductivity type formed on the well of the first conductivity type, the second MOS transistor of the second conductivity type being adjacent to the second MOS transistor of the first conductivity type, the first and second MOS transistors of the second conductivity type having sources connected to each other and connected to a first power supply; a well of a second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type, the well of the second conductivity type being adjacent to the well of the first conductivity type with an element isolation region interposed therebetween; a first MOS transistor of the first conductivity type formed on the well of the second conductivity type, the first MOS transistors of the first and second conductivity types having gates connected to each other; a second MOS transistor of the first conductivity type formed on the well of the second conductivity type, the second MOS transistors of the first and second conductivity types having gates connected to each other, the first and second MOS transistors of the first conductivity type having sources connected to each other and connected to a second power supply; and a buried region of the second conductivity type not provided under other areas except for under drain regions of the first and second MOS transistors of the first and second conductivity types and the element isolation region.