Patent ID: 7105434

Claim:
A method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method comprises steps of: depositing by a CVD technique a substantially conformal seed layer over the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.13 μm; depositing by a PVD technique a second seed layer over the substantially conformal seed layer, wherein the substantially conformal and the second seed layers do not seal the at least one opening; and electroplating a metallic layer over the second seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.