Patent ID: 7286412

Claim:
A nonvolatile memory integrated circuit, comprising: nonvolatile memory cells, including: a plurality of data cells storing at least data values associated with a low threshold voltage and a high threshold voltage; reference current circuitry generating reference currents each with a high sensing window to sense the high threshold voltage and a low sensing window to sense the low threshold voltage, the reference currents including: a normal reference current associated with a first operating window having a first high sensing window and a first low sensing window; a first monitor reference current associated with a second operating window having a second high sensing window narrower than the first high sensing window, and a second low sensing window wider than the first low sensing window; and a second monitor reference current associated with a third operating window having a third high sensing window wider than the first high sensing window and a third low sensing window narrower than the first low sensing window; one or more sets of sense amplifier circuitry sensing a memory current from the plurality of data cells with the normal reference current to generate a first result and with at least one of: the first monitor reference current to generate a second result, and the second monitor reference current to generate a third result; and comparison logic comparing the first result with at least one of the second result and the third result from the sense amplifier circuitry.