Patent ID: 7977725

Claim:
An integrated circuit device, comprising: a first semiconductor substrate having at least one of a first vertical-channel transistor and a first planar-channel transistor therein, said first substrate comprising a fin-shaped active pattern extending in a first direction therein and a first plurality of spaced-apart pillar active regions on the fin-shaped active pattern that are surrounded by a first insulated gate electrode, said first plurality of spaced-apart pillar active regions comprising respective source/drain regions adjacent tops thereof; a bonding insulation layer on said first semiconductor substrate; a second semiconductor substrate having at least one of a second vertical-channel transistor and a second planar-channel transistor therein, on said bonding insulation layer; and an electrical interconnect electrically connected to a terminal of the at least one of a first vertical-channel transistor and a first planar-channel transistor, extending through said bonding insulation layer.