Patent ID: 8050066

Claim:
A semiconductor device comprising: a semiconductor substrate; and a first capacitive element, a second capacitive element, a third capacitive element, and a fourth capacitive element which are disposed over the semiconductor substrate, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed by first and second electrodes opposite to each other via an insulating film interposed therebetween, wherein the first electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are formed by respective portions of a first conductor layer, the portions being located in a first plane, wherein the second electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are formed by respective portions of a second conductor layer, the portions being located in a second plane, wherein the first electrodes of the first capacitive element and the third capacitive element are electrically coupled to each other through a conductor and coupled to a first potential, wherein the first electrodes of the second capacitive element and the fourth capacitive element are electrically coupled to each other through a conductor and coupled to a second potential different from the first potential, wherein the second electrodes of the first capacitive element and the second capacitive element are electrically coupled to each other through a conductor and brought to a floating potential, wherein the second electrodes of the third capacitive element and the fourth capacitive element are electrically coupled to each other through a conductor and brought to a floating potential, wherein the second electrodes of the first capacitive element and the second capacitive element, and the second electrodes of the third capacitive element and the fourth capacitive element are not coupled by a conductor, wherein the first capacitive element is connected in series with the second capacitive element to form a first series circuit, and the third capacitive element is connected in series with the fourth capacitive element to form a second series circuit, and wherein the first series circuit is connected in parallel with the second series circuit.