Patent ID: 7512827

Claim:
A CAN communication module ( 10 ), comprising: a protocol kernel ( 14 ) and a CAN logic block ( 12 ); the protocol kernel ( 14 ) including a CAN bus interface; and the CAN logic block ( 12 ) including a module interface for connection to an external peripheral bus ( 22 ), a message RAM ( 28 ) and a CAN message handler ( 26 ), wherein the protocol kernel ( 14 ) and the CAN logic block ( 12 ) have separate clock inputs ( 32 , 36 ); a clock generator ( 42 ) with a fixed frequency oscillator that supplies a low jitter clock output ( 54 ); and a frequency modulation phase locked loop circuit ( 50 ) with a reference input ( 56 ) receiving the low jitter clock output ( 54 ) and with a logic clock output ( 58 ); wherein the clock input ( 36 ) of the protocol kernel ( 14 ) is connected to the low jitter clock output ( 54 ) and the clock input ( 32 ) of the CAN logic block ( 12 ) is connected to the logic clock output ( 58 ).