Patent ID: 8510941

Claim:
A method of manufacturing a printed circuit board or a sub-component of the printed circuit board having a plurality of circuit layers with at least one hole for interconnecting copper patterns on the different circuit layers of the circuit board or the sub-component of the circuit board, the method comprising: laminating the plurality of circuit layers with each other to form the circuit board or the sub-component of the circuit board with a first solid copper layer and a second solid copper layer respectively as both outermost layers of the circuit board or the sub-component of the circuit board; selectively removing a portion of at least one of the first solid copper layer or the second solid copper layer to form a clearance for drilling the hole; drilling the hole into the laminated circuit layers at the clearance; metalizing the circuit layers with the drilled hole to metalize the hole; coating a photo resist on both the outermost layers; patterning the photo resist on the circuit layers with a photo dot to expose the clearance and the metalized hole; electrolytic copper plating the metalized hole with an electrolytic plating solution to plate the metalized hole to a desired copper thickness in the metalized hole and with copper wrap continuously wrapping from the hole wall onto an outer surface into the clearance around the metalized hole; stripping the photo resist; filling the copper plated hole with a via fill material; curing the via fill material in the via filled hole; planarizing the via fill material and the plated copper wrap in the clearance around the plated hole to a level substantially the same as the level of the at least one of the first solid copper layer or the second solid copper layer; and forming a conductive image to cover the planarized hole along with the planarized copper wrap.