Patent ID: 7071059

Claim:
A method for forming a recess gate of a semiconductor device, comprising the steps of: (a) forming a polysilicon layer pattern on a semiconductor substrate having an active region, the polysilicon layer pattern covering a contact region; (b) forming an insulating film covering the polysilicon layer pattern; (c) etching a predetermined thickness of the semiconductor substrate using the polysilicon layer pattern as an etching mask to form a recess gate region in the active region; (d) forming a planarized gate polysilicon layer at least filling up the recess gate region; (e) depositing a gate conductive layer and a gate hard mask layer on the gate polysilicon layer to form a stacked structure of the gate polysilicon layer, the gate conductive layer and the gate hard mask layer; (f) etching the stacked structure to form a gate structure, whereby the insulating film is exposed; (g) forming a spacer on a top surface and a sidewall of the gate structure; (h) removing the exposed insulating film to expose the polysilicon layer pattern; and (i) depositing a polysilicon film on the exposed polysilicon layer pattern in the contact region to form a landing plug.