Patent ID: 7560338

Claim:
A manufacturing method of a non-volatile memory, comprising: providing a substrate; forming a plurality of dummy bit lines on the substrate; forming an electron trapping layer covering the substrate and the dummy bit lines; forming a plurality of conductive spacers on the sidewalls of the dummy bit lines; forming a protection layer on the surface of the conductive spacers; removing the electron trapping layer which is not covered by the conductive spacers; forming a plurality of conductive layers between the dummy bit lines; removing the dummy bit lines to form a plurality of strip structures; performing a BL ion implantation process upon the substrate, so as to form a plurality of buried bit lines in the substrate; covering a dielectric layer on the buried bit lines and exposing the top of the strip structures; forming a plurality of word lines over the substrate, and the word lines are interlaced with the buried bit lines; and etching the conductive layer in the strip structures by using the word lines as a mask to form a plurality of word gates.