Patent ID: 7023497

Claim:
A clamping circuit having an input node, an output node, and a power supply, comprising: a clamping capacitor coupled to the input node, the input node coupled to receive a video input signal; an automatic clamping circuit portion coupled to the clamping capacitor to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage of a first clamping pulse signal; a customizable clamping circuit portion coupled to the automatic clamping portion to clamp any portion of the video input signal to a second predetermined reference voltage of a second clamping pulse signal; and a buffer coupled between to the customizable clamping circuit portion and the output node, wherein the automatic clamping circuit portion comprises: a comparator having a first and second input, and an output; a first level shift circuit coupled between the first input of the comparator and a reference voltage input; a second level shift circuit coupled between the second input of the comparator and the clamping capacitor; a first transistor, having a gate, a drain, and a source, the gate coupled to the output of the comparator, the source coupled to the power supply, the drain coupled to the clamping capacitor; and a current source coupled between the clamping capacitor and ground.