Patent ID: 8539250

Claim:
An apparatus, comprising: a memory; a processor coupled to the memory; an address translator configured in accordance with a predetermined translation function to translate respective original data storage addresses arranged in an original order to respective translated data storage addresses arranged in a translated order, wherein respective data blocks are associated with the respective translated data storage addresses, and wherein the address translator is configured to exchange the respective data blocks with a platform having data storage locations configured to store the respective data blocks, wherein the data storage locations correspond to respective data storage addresses; a cryptographic engine coupled to the address translator and configured to reversibly encrypt the respective data blocks in accordance with a predetermined cryptographic function, wherein the cryptographic engine is configured to exchange encrypted data blocks with the storage component; the processor arranged to implement at least one of the address translator or the cryptographic engine; wherein the translation function comprises a globally unique function with respect to one or more predetermined characteristics of the platform and the globally unique function is used to facilitate generation of the translated data storage addresses; and a manageability engine coupled to the cryptographic engine and the address translator, wherein the manageability engine configures at least one of the cryptographic engine in accordance with the predetermined cryptographic function or the address translator in accordance with the predetermined translation function.