Patent ID: 8131985

Claim:
A semiconductor memory device for use in a multiprocessor system, the device comprising: a shared memory area accessible by a plurality of processors of the multiprocessor system through different ports, the shared memory area being assigned to a portion of a memory cell array; and a reset signal generator configured to provide a reset enable signal to a processor, predetermined as a slave processor among the plurality of processors, for a predetermined time after an initial booting of the multiprocessor system, and to provide a reset disable signal to the slave processor after the predetermined time lapses, wherein the reset signal generator comprises: a mode register set circuit configured to output a register setting signal in response to an external signal; a latch configured to latch the register setting signal applied through an input node; a switching transistor configured to discharge the input node in response to a power-up reset related signal; and a driver configured to drive an output signal of the latch and to output the output signal as one of the reset enable signal or the reset disable signal.