Patent ID: 8667451

Claim:
A broadcaster that accepts virtual scan patterns via its scan inputs for generating broadcast scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said broadcaster comprising: a) a virtual scan controller for controlling the operation of said broadcaster during each shift cycle or between test sessions, said virtual scan controller further including one or more shift registers for accepting said virtual scan patterns via said scan inputs of said broadcaster; and b) a solely combinational logic network directly connected to selected outputs of said virtual scan controller and selected scan inputs of said broadcaster for generating said broadcast scan patterns at the outputs of said combinational logic network in said broadcaster, said combinational logic network further comprising a plurality of broadcast scan outputs and logic gates, said plurality of logic gates comprising one or more AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, or inverters, or any combination of said plurality of logic gates.