Patent ID: 7996821

Claim:
A data processor formed on a semiconductor chip comprising: a first central processing unit; a second central processing unit; a debugging module including a selection circuit and a buffer circuit; a first bus to be coupled to the first central processing unit; and a second bus to be coupled to the second central processing unit, wherein the debugging module monitors the first bus and the second bus, wherein the debugging module monitors a command on the first bus and/or the second bus, traces address information and data information on the first bus and/or the second bus according to a trace condition, and outputs CPU identification information, wherein the CPU identification information indicates the data information that either the first central processing unit or the second central processing unit performs an operation corresponding to the trace information, and wherein said selection circuit comprises: a first selector for selecting a bus for obtaining trace information from the first and/or second buses, holding information of the selected bus on a bus cycle unit basis, and generating a first output; a second selector for selecting a bus for obtaining trace information from the first and/or second buses, holding information of the selected bus on the bus cycle unit basis, and generating a second output; and a third selector for selecting from a selected output from the first output and the second output and supplying the selected output to the buffer circuit.