Patent ID: 8125263

Claim:
A charge pump for amplifying an input voltage received at an input end and outputting the amplified voltage from an output end as an output voltage, comprising: a first clock input for providing a first clock signal; a second clock input for providing a second clock signal; a first cascode section including a first transistor and a second transistor cascode-connected to between the input end and a first point, and a gate of the first transistor and a gate of the second transistor being connected to each other at a first node; a second cascode section including a third transistor and a fourth transistor cascode-connected to between the input end and a second point, and a gate of the third transistor and a gate of the fourth transistor being connected to each other at a second node; a third cascode section including a fifth transistor and a sixth transistor cascode-connected to between the first point and the output end, and a gate of the fifth transistor and a gate of the sixth transistor being connected to each other at a third node; a fourth cascode section including a seventh transistor and an eighth transistor cascode-connected to between the second point and the output end, and a gate of the seventh transistor and a gate of the eighth transistor being connected to each other at a fourth node; a first source/drain coupling transistor having a source and a drain separately coupled to the first clock input, and a gate coupled to the second node; a second source/drain coupling transistor having a source and a drain separately coupled to the second clock input, and a gate coupled to the first node; a third source/drain coupling transistor having a source and a drain separately coupled to the first node, and a gate coupled to the fourth node; a fourth source/drain coupling transistor having a source and a drain separately coupled to the second node, and a gate coupled to the third node; a first diode-connected transistor being connected to between the second node and the third node; a second diode-connected transistor being connected to between the first node and the fourth node; a first output transistor being connected to between the fourth node and the output end by way of diode; and a second output transistor being connected to between the third node and the output end by way of diode; wherein the first clock signal has a polarity reverse to that of the second clock signal; and wherein the first node is a connecting point of the cascode-connected third transistor and fourth transistor; the second node is a connecting point of the cascode-connected first transistor and second transistor; the third node is a connecting point of the cascode-connected fifth transistor and sixth transistor; and the fourth node is a connecting point of the cascode-connected seventh transistor and eighth transistor.