Patent ID: 7179664

Claim:
A method for generating a work in progress (WIP) schedule in a semiconductor manufacturing facility, the method comprising: determining starting and ending dates of a predetermined schedule period for generating the WIP schedule; determining remaining days for completing at least one wafer lot associated with a predetermined product from the starting date; determining a starting process stage for the wafer lot at the beginning of the starting date based on the remaining days; determining an ending process stage for the wafer lot at the end of the ending date; identifying all stages between the starting and the ending process stages; assigning wafer numbers to each process stage of the schedule time in proportion to a process time of each stage in view of a total process time for the schedule period; and repeating the above steps for one or more other wafer lots under production to determine a total wafer number assigned to each stage, thereby constructing the WIP schedule for the schedule period, wherein at least one of the above steps is performed through a computing device.