Patent ID: 7466610

Claim:
A non-volatile semiconductor memory device, comprising: a memory cell array including electrically rewritable non-volatile memory cells arrayed; a redundant memory cell having threshold voltages differing in accordance with data to be stored and storing address data of a defect cell in said memory cell array; a first decoder circuit given a first drive voltage to provide a control signal to said redundant memory cell; a latch circuit storing said address data of said defect cell read out of said redundant memory cell; a dummy memory cell having a threshold voltage corresponding to said redundant memory cell; a second decoder circuit given a second drive voltage corresponding to said first drive voltage to provide a control signal to said dummy memory cell; a comparator circuit operative to compare data to be read out of said dummy memory cell with data actually read out of said dummy memory cell and, based on a result of the comparison, permit said redundancy replacement control to be started a power-on reset circuit providing a power-on reset signal when the power-on reset circuit detects that said external supply voltage rises and reaches a certain value; a reference voltage generator circuit generating a certain reference voltage from said external supply voltage; a delay circuit providing a delayed signal at a certain delayed timing after receipt of said power-on reset signal; a booster circuit that starts boosting said external supply voltage on receipt of said delayed signal to generate a boosted voltage; and a boost detector circuit comparing said boosted voltage with said reference voltage and, based on a result of the comparison, halting operation of said booster circuit, wherein said first row decoder is driven by said boosted voltage as said first drive voltage.