Patent ID: 8793435

Claim:
A load miss result buffer for a load/store unit with a load pipeline and configured to access a memory system having a level one cache and a level two memory sub-system, the load miss result buffer comprising: a first plurality of dependent data lines; a first plurality of dependent data selection circuits, wherein each dependent data line of the first plurality of dependent data lines is coupled to an associated dependent data selection circuit of the first plurality of dependent data selection circuits and configured to receive data from the memory system; a second plurality of dependent data lines; a second plurality of dependent data selection circuits, wherein each dependent data line of the second plurality of dependent data lines is coupled to an associated dependent data selection circuit of the second plurality of dependent data selection circuits and configured to receive data from the memory system; a plurality of shared data lines; and a plurality of shared data selection circuits, wherein each shared data line of the plurality of shared data lines is coupled to an associated shared data selection circuit of the plurality of shared data selection circuits and configured to receive data from the memory system.