Patent ID: 7864600

Claim:
A memory array system having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell, the memory cell comprising: a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one of a read operation and a write operation; a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell; and a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array, the read access circuit being enabled and configured to read the logic state of the storage element in response to a read signal on the read word line wherein the reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.