Patent ID: 8524557

Claim:
A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising: forming a control gate overlying a charge storage layer over the substrate in the NVM region; forming a thermally-grown oxygen-containing dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region; forming a polysilicon layer over the thermally-grown oxygen-containing dielectric layer in the NVM region and the logic region; planarizing the polysilicon layer; forming a first masking layer in the NVM region wherein the first masking layer defines a select gate location laterally adjacent the control gate in the NVM region; forming a second masking layer in the logic region wherein the second masking layer defines a logic gate location in the logic region; using the first masking layer to remove exposed portions of the polysilicon layer from the NVM region, wherein a first portion of the polysilicon layer remains at the select gate location to form a select gate; using the second masking layer to remove exposed portions of the polysilicon layer from the logic region, wherein a second portion of the polysilicon layer remains at the logic gate location; forming a dielectric layer in the NVM region and the logic region, wherein the dielectric layer is formed over the select gate, the control gate, and the second portion of the polysilicon layer; planarizing the dielectric layer to expose the second portion of the polysilicon layer; removing the second portion of the polysilicon layer and a portion of the thermally-grown oxygen-containing dielectric layer to result in an opening at the logic gate location which exposes the substrate; and forming a high-k gate dielectric layer and a logic gate within the opening in the logic region.