Patent ID: 8743626

Claim:
A device comprising: a plurality of non-volatile memory cells; a high-voltage node coupled to the plurality of memory cells; an intermediate-voltage node coupled to the plurality of memory cells; and a metal-oxide-semiconductor field-effect transistor (MOSFET) coupled between the high-voltage node and the intermediate-voltage node and configured to provide a voltage drop between the high-voltage node and the intermediate-voltage node, wherein: the MOSFET comprises a gate, source, and drain; the gate is fabricated by a counter-doping process, wherein the gate is doped with a first type of dopant and then doped with a second type of dopant, the second type of dopant being an opposite type of dopant compared to the first type of dopant; the source and drain are doped with a dopant having a same type as the first type of dopant; a proximate region located next to the source on a side opposite to the gate is doped with a dopant having a same type as the second type of dopant; and the MOSFET is configured as a device comprising a first terminal and a second terminal, wherein the first terminal comprises the gate electrically coupled to the drain, and wherein the second terminal comprises the source electrically coupled to the proximate region.