Patent ID: 8793558

Claim:
A memory system, comprising: an array of memory cells; sense amplifier circuitry configured to provide data output signals associated with sensed voltage levels for a plurality of memory cells within the array of memory cells, the sense amplifier circuitry having read detection windows for the sensed voltage levels; and memory control circuitry configured to receive the data output signals and to identify and correct bit errors within the data output signals by applying at least one error correction control (ECC) routine, the memory control circuitry being further configured to vary the read detection windows by adjusting at least one operating parameter when an identified bit error is not correctable by the at least one ECC routine and to cause the sense amplifier circuitry to re-sense voltage levels for the plurality of memory cells using the adjusted at least one operating parameter; and data storage circuitry; wherein the memory control circuitry is further configured to vary the read detection windows until detected but uncorrectable bit errors are corrected and to output corrected data, to store the corrected data and an address for the not correctable error in the data storage circuitry, and to access the stored corrected data if a subsequent read operation addresses data from the address.