Patent ID: 8145869

Claim:
A method for controlling multiple data buses including a first data bus to a first memory device and a second data bus to a second memory device, the method comprising: splitting the first data bus to the first memory device into multiple sets of first data bus signals; for each of multiple controller chips, assigning a respective controller chip to control a corresponding set of the multiple sets of the first data bus signals associated with the first data bus between the respective controller chip and the first memory device; splitting the second data bus to the second memory device into multiple sets of second data bus signals; for each of the multiple controller chips, assigning a respective controller chip to control a corresponding set of the multiple sets of the second data bus signals associated with the second data bus between the respective controller chip and the second memory device; via the first data bus, enabling each of the multiple chip controllers to simultaneously access a different respective portion of data stored in the first memory device; via the second data bus, enabling each of the multiple chip controllers to simultaneously access a different respective portion of data stored in the second memory device; and synchronizing the multiple chip controllers for purposes of enabling simultaneous access of different portions of data from the first memory device at the same time and enabling simultaneous access of different portions of data from the second memory device at the same time; wherein enabling each of the multiple chip controllers to simultaneously access the different respective portions of data stored in the first memory device includes: assigning a first controller chip of the multiple controller chips to control a first address bus and first control bus associated with the first memory device; and wherein enabling each of the multiple chip controllers to simultaneously access the different respective portions of data stored in the second memory device includes: assigning a second controller chip of the multiple controller chips to control a second address bus and second control bus associated with the second memory device, enabling the first and second controller chips to simultaneously access a respective portion of data from the first memory device while the first controller chip controls the first address bus and first control bus associated with the first memory device; and enabling the first and second controller chips to simultaneously access a respective portion of data from the second memory device while the second controller chip controls the second address bus and second control bus associated with the second memory device.