Patent ID: 8441506

Claim:
A liquid crystal display device comprising: a liquid crystal display panel including a plurality of data lines and a plurality of gate lines crossing each other; a backlight unit configured to radiate backlight to the liquid crystal display panel; a backlight driving circuit configured to turn on and off light sources of the backlight unit according to a backlight dimming data; a data driving circuit configured to convert digital video data into positive and negative data voltages and to supply the positive and the negative data voltages to the plurality of data line; a gate driving circuit configured to supply a gate pulse to the plurality of gate line sequentially; a field programmable gate array (FPGA) configured to set circuit configurations of a built-in gate array logic part according to a gate array connection data downloaded from a non-volatile memory in order to modulate an input video data and to generate the backlight dimming data; and a timing controller configured to control operating timings of the data driving circuit and the gate driving circuit, wherein the FPGA includes: a built-in phase-locked loop (PLL) configured to generate an internal clock and lock a frequency and a phase of the internal clock output by responding to a PLL lock reset signal; a PLL lock reset clock generator configured to supply the PLL lock reset signal to the built-in PLL by responding to a FPGA reset signal; a data receiver configured to sample the input video data according to the internal clock from the built-in PLL and supply the received input video data to the gate array logic part; and a data transmitter configured to send a modulated data by the gate array logic part to the timing controller, wherein the field programmable gate array downloads the gate array connection data from the non-volatile memory during a time interval which is defined from when a logic power voltage generated after a power of the liquid crystal display device is turn on is converted into a high logic voltage to when a configuration signal is reversed to the high logic voltage, and wherein the gate array logic part configures an internal reset circuit to output the FPGA reset signal according to the gate array connection data.