Patent ID: 7973399

Claim:
An embedded chip package, comprising: a first substrate, comprising at least a first dielectric layer and at least a first patterned circuit layer disposed on a bottom surface of the first dielectric layer; a semiconductor chip, having a first surface and a second surface opposite the first surface, wherein the semiconductor chip disposes on the first substrate; a plurality of first electrical bonding pads, on the first surface of the semiconductor chip, wherein the first electrical bonding pads contact an upper surface of the first dielectric layer; an encapsulating material layer, disposed on the first substrate and around the semiconductor chip; a plurality of first conductive vias, disposed in the first substrate to electrically connect the first patterned circuit layer to the first electrical bonding pads; a second substrate, comprising at least a second dielectric layer and at least a second patterned circuit layer directly disposed on the second dielectric layer, wherein the second substrate is disposed on the second surface of the semiconductor chip and the encapsulating material layer; and the second dielectric layer contacts the second surface of the semiconductor chip; and a plurality of second conductive vias, disposed in the first substrate, the encapsulating material layer and the second substrate to electrically connect the first patterned circuit layer to the second patterned circuit layer.