Patent ID: 7177196

Claim:
A nonvolatile semiconductor memory comprising: a first string including a first memory cell and a first select transitor connected in series; a second string line including a second memory cell and a second select transistor connected in series; a first bit line connected to said first string line; a second bit line connected to said second string line, being different from said first bit line; a common node connected to one ends of said first and second bit lines, and a common latch circuit connected to said common node, wherein said first and second memory cells are programmed substantially simultaneously; and while a program voltage is supplied to said second memory cell, a verify read operation to verify whether said first memory cell has been programmed sufficiently, is carried out by said common latch circuit, and while said program voltage is supplied to said first memory cell, a verify read operation to verify whether said second memory cell has been programmed sufficiently, is carried out by said latch circuit.