Patent ID: 8065456

Claim:
A system, comprising a multiple-core processor including a plurality of processor cores configured to support a plurality of software generated read or write instructions for interfacing with a star topology serial bus interface; a messaging network coupled to said plurality of processor cores and configured to link the processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory; a star topology serial bus interface operably coupled to said messaging network, said star topology serial bus interface comprising a direct memory access (DMA) device configured to translate memory read or write instructions from said messaging network into star topology serial bus transaction layer packets (TLP) in response to said read or write instructions, a message box circuit for storing incoming read or write instructions from said plurality of processor cores and assigned to at least one of a plurality of message types; and wherein said plurality of processor cores communicate with said star topology serial bus interface via short messages sent over said messaging network and assigned to at least one of the plurality of message types.