Patent ID: 7432749

Claim:
A circuit for providing a periodic clock signal, comprising: a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having an input voltage, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop, the logic circuit having a counter output coupled with the input voltage of the voltage controlled oscillator, the logic circuit including, a comparator having a first and a second input and a comparator output, the first input coupled with a single reference voltage and the second input coupled with the input voltage input of the voltage controlled oscillator, the comparator comparing the input voltage only against the single reference voltage, and an up/down counter having at least one input and the counter output, the at least one input coupled with the comparator output, so that if the input voltage is different than the reference voltage, the counter output adjusts the operating frequency of the phase locked loop circuit, and so that if the input voltage is substantially equal to the reference voltage, the counter output counts up one cycle and counts down one cycle and repeats until the input voltage is no longer substantially equal to the reference voltage.