Patent ID: 7966486

Claim:
A computer system, comprising: a central processing unit (CPU); a chipset, coupled to the CPU; a first bus, coupled to the chipset; a second bus, coupled to the chipset; a first memory, coupled to the chipset through the first bus for storing a first basic input output system (BIOS); a second memory, coupled to the chipset through the second bus for storing a second BIOS; and a logic control circuit, for detecting a state of the first bus and controlling the chipset to select to access the first memory through the first bus or select to access the second memory through the second bus according to the state of the first bus, wherein the logic control circuit comprises: a first detection unit, for detecting a state of the first bus and a state of the first BIOS, and outputting a first detecting result; a second detection unit, for detecting a state of the second bus and a state of the second BIOS, and outputting a second detecting result; a logic unit, coupled to the first detection unit and the second detection unit, for generating a control signal according to the first detecting result and the second detecting result; and a gate unit, coupled between the logic unit and the chipset, for determining whether to transmit the control signal to the chipset or not.