Patent ID: 7144799

Claim:
A method for pre-retaining bit line CB opening, comprising the following steps: providing a substrate; forming a plurality of gate conductors (GCs) on said substrate, with a gap between each pair of adjacent GCs; forming a photo-resist layer on said GCs and said gaps; removing a part of said photo-resist layer to expose a part of said substrate and a part of said GCs, said photo-resist layer still partially covering two adjacent GCs and filling the gap between said two partially covered GCs; forming a sacrifice layer at the locations of said removed photo-resist layer; removing said photo-resist layer on said filled gap and said partially covered GCs to form a bit line CB opening; forming a polysilicon layer in said bit line CB opening and on said sacrifice layer; removing said polysilicon layer to expose said sacrifice layer; removing said sacrifice layer to expose a part of said substrate and a part of said GCs; uniformly forming a nitrogen compound layer on said polysilicon layer, said exposed substrate and said exposed GCs; forming a BPSG layer on said nitrogen compound layer; and removing said BPSG layer to expose said nitrogen compound layer on top of said polysilicon layer.