Patent ID: 8826099

Claim:
A memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell in which each of a plurality of 3-bit values is allocated to each of a plurality of threshold voltage distributions, a first bit represents a first page bit, a second bit represents a second page bit, and a third bit represents a third page bit, the memory controller comprising: upon writing data for three pages of the first page, the second page, and the third page to a first memory area of the non-volatile semiconductor memory, a control unit that selects one bit, from the first page bit and the second page bit, which becomes an error bit when a threshold voltage distribution moved to an adjacent threshold voltage distribution owing to charge leakage or flow, and generates a virtual page using the selected bits from the first page and the second page; an encoding unit that generates a first error correcting code for the virtual page; and an interface unit that writes the data for the three pages and the first error correcting code in the non-volatile semiconductor memory.