Patent ID: 7611933

Claim:
A process for manufacturing a thin-film transistor device comprising: forming a dielectric insulation layer on a substrate; forming an amorphous silicon layer on said dielectric insulation layer; crystallizing said amorphous silicon layer so as to obtain polycrystalline silicon; forming gate structures on said polycrystalline silicon; and forming first doped regions within said polycrystalline silicon laterally with respect to said gate structures; wherein crystallizing comprises: forming first capping dielectric regions on said amorphous silicon layer; and after forming first capping dielectric regions, irradiating said amorphous silicon layer using a laser, so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying said first capping dielectric regions, wherein the horizontal dimension of at least one of said active areas differs from the horizontal dimension of another of said active areas, and wherein the horizontal dimension of each active area is selected to obtain desired electrical properties for that active area.