Patent ID: 7045863

Claim:
A semiconductor device, comprising: a semiconductor substrate which includes an active region; an element isolation region provided in a region surrounding sides of said active region of said semiconductor substrate; a gate insulating film provided on said active region; a gate electrode provided on said gate insulating film; a source region and a drain region which are provided in regions located below sides of said gate electrode in said active region, respectively; an on-source silicide film provided on said source region; an on-drain silicide film provided on said drain region; a plurality of source contacts which are provided over said source region with said on-source silicide film interposed therebetween, and which are aligned in a gate width direction; and a plurality of drain contacts which are provided over said drain region with said on-drain silicide film interposed therebetween, and which are aligned in the gate width direction, wherein a first dummy gate insulating film and a first dummy gate electrode located on said first dummy gate insulating film are provided on the at least one region out of the regions located between the respective adjacent pairs of the drain contacts among said plurality of drain contacts in said active region located below sides of said gate electrode, and said on-drain silicide film includes a narrow-width silicide region in a region located between said first dummy gate electrode and said gate electrode, the narrow-width suicide region being smaller in a width in a gate length direction than respective regions where said drain contacts are formed.