Patent ID: 7129159

Claim:
A method of forming a dual damascene conductor structure comprising: providing a substrate having a top surface with an electrical conductor exposed on said top surface; forming a cap layer having a bottom surface located above said top surface of said substrate; forming a dielectric layer having a bottom surface located above said cap layer; forming an organic (OL) layer over said dielectric layer; forming a lower, via hard mask layer and a tap, trench hard mask layer over said OL layer; forming a trench patterning hole through said top, trench hard mask layer; forming a via patterning hole through said lower, via hard mask layer inside said trench patterning hole through said top, trench hard mask layer; etching said via patterning hole through said organic layer and then etching said via patterning hole into said dielectric layer; etching away said via hard mask layer below said trench patterning hole and then etching away said OL layer below said trench patterning hole; etching said via hole through said bottom of said dielectric layer to said cap layer while partially etching a trench into said dielectric layer below said trench patterning hole with said trench having a bottom and sidewalls in said dielectric layer with said bottom being spaced above said cap layer; and etching through said cap layer below said via hole to expose said conductor.