Patent ID: 7491611

Claim:
A method of fabricating a voltage sense device, comprising: forming a first doped region in a well included in a substrate; forming a second doped region in the substrate outside of the well; forming a third doped region in the well; coupling a first terminal to the well via the first doped region; coupling a second terminal to the substrate via the second doped region; and coupling a third terminal to the well via the third doped region, wherein a voltage output by the voltage sense device at the third terminal is substantially proportional to a voltage between the first and second terminals when the voltage between the first and second terminals is less than a pinch-off voltage of the voltage sense device, wherein the voltage output by the voltage sense device at the third terminal is substantially constant and less than the voltage between the first and second terminals when the voltage between the first and second terminals is greater than the pinch-off voltage of the voltage sense device.