Patent ID: 7254070

Claim:
A semiconductor device comprising: a memory cell array having a plurality of word lines, a plurality of bit lines and a plurality of memory cells each of which is located at an intersection between one of the word lines and one of the bit lines, wherein the word lines includes a redundant word line; a row decoder connected to the word lines, the row decoder selecting one of the word lines in response to a row address, the row address decoder selecting the redundant word line when a replacement signal is received thereto; a column decoder connected to the bit- lines, the column decoder selecting one of the bit lines in response to a column address; a row address redundancy circuit including a fuse circuit and storing a redundant row address, the row address redundancy circuit providing a redundancy signal when the redundant row address corresponds to an address received thereto; and a mode setting circuit connected to the row address redundancy circuit and the row decoder for receiving a mode signal having a normal mode and a test mode, the mode setting circuit outputting the replacement signal to the row decoder when the mode signal is in the normal mode and the redundancy signal is provided by the row address redundancy circuit, and prohibiting said output of the replacement signal when the mode signal is in the test mode, wherein the fuse circuit includes: a main fuse circuit having a first fuse for indicating whether the redundant word line is used, and a sub fuse circuit having a plurality of second fuses for storing the redundant row address.