Patent ID: 8428061

Claim:
A packet processor for a network device, the packet processor comprising: an incoming port configured to receive a packet, wherein the first packet includes a data portion and a control portion; a first outgoing port; a control data processing device configured to i) receive the control portion of the packet from the incoming port while the data portion of the packet is stored in memory, and ii) transmit the control portion of the packet to the first outgoing port, wherein prior to any attempt to transmit the data portion of the packet from the first outgoing port, the first outgoing port is configured to transmit a first request for the data portion of the packet based on the control portion of the packet; and a header altering device configured to i) retrieve the data portion of the packet from the memory, and ii) strip, modify, and encapsulate the data portion of the packet based on requirements specified in the first request.