Patent ID: 6999358

Claim:
A semiconductor memory device, comprising: a plurality of subblocks, each comprising a memory array and a drive circuit located along a side of the memory array and, driving lines of memory cells therein, the lines including a redundant line for repair; an address input circuit for receiving an address signal input; a defective line information store circuit for storing defective line information showing defective lines in the plurality of subblocks, the defective line information store circuit being shared by at least a portion of the plurality of subblocks and being located proximate to a side of one of the plurality of subblocks parallel to the defective line, wherein the plurality of subblocks which share the defective line information store circuit are located in the direction perpendicular to the lines of memory cells; a redundant circuit, located proximate to the drive circuit of each of the plurality of subblocks and comprising a volatile storage circuit, for substituting one of the lines including the redundant line of the corresponding subblock for a defective line in that subblock according to the state of the volatile storage circuit; common signal lines for connecting the defective line information store circuit and the redundant circuit corresponding to each subblock and for connecting the address input circuit and the drive circuit of each subblock to deliver the address signal input, the common signal lines running parallel to the drive circuit; and a supply circuit for transferring the defective line information from the defective line information store circuit to the volatile storage circuit in the redundant circuit corresponding to each subblock via the common signal lines.