Patent ID: 7260682

Claim:
A processor adapted to couple to external memory, comprising: a controller; data storage operated by said controller, said data storage usable to store local variables and temporary data and said data storage configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory; wherein said data storage comprises a first portion and a second portion, and wherein only one of said portions is active at a time for storing said local variables, the non-active portion being unusable for storing the local variables; wherein, when the active portion does not have sufficient capacity for additional local variables to be stored therein, the other portion becomes the active portion for storing local variables; and wherein, when one portion is the active portion, the other portion is used to store the temporary data, such other portion being sufficiently large to contain all desired such temporary data.