Patent ID: 8119457

Claim:
A method of making a semiconductor package assembly comprising: providing, on a tape, a half-etched lead frame having a die attach pad, a gate lead, one or more source leads, and one or more no connection leads; flip chip attaching a power MOSFET to said die attach pad of said lead frame; molding said lead frame and attached power MOSFET flip chip on said tape, such that the drain of said power MOSFET is exposed; producing a molded leadless package (MLP) by sawing said molded lead frame and power MOSFET on said tape; providing a folded heat sink having an exposed planar top surface and one or more leads extending generally perpendicularly from said planar top surface; and picking up said sawn MLP from said tape and soft-solder-attaching said MLP to said folded heat sink such that the heat sink is in contact with said exposed drain and said folded heat sink leads end in the vicinity of said no connection leads and are separated from the no connection leads by an empty gap.