Patent ID: 8067992

Claim:
A relaxation oscillator circuit, comprising: a relaxation oscillator having an input, the relaxation oscillator being configured to provide an output signal having a frequency; a field effect transistor (FET); a current mirror circuit configured to provide a charging current to the input of the relaxation oscillator and a biasing current to a drain of the FET; an operational amplifier having an output operably connected to a gate of the FET; a band-gap circuit operably connected to a first input of the operational amplifier, and a resistor array circuit having an output operably connected to a source of the FET and a second input of the operational amplifier; wherein the resistor array circuit further comprises an array of positive temperature coefficient resistors arranged in parallel respecting one another and in parallel with respect to an array of negative temperature coefficient resistors arranged in parallel respecting one another, values of resistances provided by the positive temperature coefficient resistor array and the negative temperature coefficient resistor array being selectively controllable and selectable using switches operably connected to each of the resistors in the positive and negative arrays such that the frequency of the output signal remains substantially constant despite changes in the ambient temperature to which the relaxation oscillator circuit is subjected, the relaxation oscillator circuit having a temperature coefficient less than or equal to about 10 ppm/° C., the relaxation oscillator circuit further being one of a CMOS circuit and a BiCMOS circuit disposed on a single chip or integrated circuit.