Patent ID: 6861738

Claim:
A laminated-chip semiconductor device comprising: a semiconductor chip having a plurality of terminals for signals; a plurality of chip-mounting substrates on each of which at least one said semiconductor chip is mounted, and a plurality of chip connecting wirings electrically connected to said terminals for signals of said semi-conductor chips which are mounted on said chip-mounting substrates are formed, and which are laminated in two or more layers in a thickness direction; and a plurality of intermediate substrates which are alternately arranged with respect to said plurality of chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to said chip connecting wirings of an adjacent said chip-mounting substrate are formed, wherein each of said plurality of chip connecting wirings are formed in a same pattern with respect to each of said plurality of chip-mounting substrates, and each of said plurality of interlayer connecting wirings are formed in patterns such that a first electric connection state of said plurality of terminals for signals each other between said semiconductor chips each mounted on said chip-mounting substrates, or a second electric connection state between a plurality of external terminal connecting wirings electrically connected to a plurality of predetermined external terminals and each of said plurality of terminals for signals can be switched.