Patent ID: 7389316

Claim:
A digital logic circuit for generating random numbers, comprising: N logic gates, N being an integer greater than two, where one of said N logic gates comprises an exclusive-NOR (XNOR) logic gate and each remaining one of said N logic gates comprises an exclusive-OR (XOR) logic gate; each of said N logic gates including an output terminal, a first input terminal, a second input terminal, and a third input terminal; each of said N logic gates having a right neighbor in said N logic gates and left neighbor in said N logic gates; where, for each logic gate of said N logic gates: said first input terminal thereof is coupled to said output terminal thereof; said second input terminal thereof is coupled to said output terminal of said left neighbor thereof; and said third input terminal thereof is coupled to said output terminal of said right neighbor thereof; a sampling logic circuit for sampling first output data on said output terminal of each of said N logic gates.