Patent ID: 8294279

Claim:
A chip package comprising: a circuit component having a top surface with a first region and a second region, wherein said circuit component comprises multiple first metal pads at said second region, wherein said multiple first metal pads are arranged substantially in a direction from a top perspective view, and wherein a ditch in said circuit component extends substantially in said direction from said top perspective view; a chip vertically over said first region, wherein said second region has no area vertically under said chip; multiple metal bumps between said chip and said first region, wherein one of said multiple metal bumps has a top end joining said chip and a bottom end joining said first region, wherein said multiple metal bumps connect said chip to said circuit component; an underfill between said chip and said first region and between said multiple metal bumps; and a dam bar on and in contact with said second region, wherein said dam bar comprises a metal, wherein from said top perspective view, said dam bar extends substantially in said direction and is located between an outer edge of said chip and an outer edge of said multiple first metal pads, wherein said dam bar contacts said underfill, and wherein said ditch is between said dam bar and said multiple metal bumps and there is no metal bump located between said ditch and said multiple first metal pads.