Patent ID: 7244650

Claim:
A method for manufacturing a transistor, comprising the steps of: forming a device isolation film on a semiconductor substrate to define an active region and a device isolation region in the semiconductor substrate; forming a step gate mask on the active region of the semiconductor substrate; etching the semiconductor substrate to a predetermined depth, using the step gate mask as an etch mask, thereby forming a stepped profile; implanting first threshold voltage control ions into the semiconductor substrate formed with the stepped profile; forming a gate on the semiconductor substrate implanted with the first threshold voltage control ions; forming a mask on the semiconductor substrate formed with the gate to shield a storage node region and to expose a bit line node region; implanting second threshold voltage control ions into the exposed bit line node region, using the mask as an ion implantation mask; and removing the mask, and then implanting source/drain formation ions into the semiconductor substrate, thereby forming source/drain junctions.