Patent ID: 8745119

Claim:
A processor comprising: a cache to store one or more instructions including an instruction to perform a multiplication of a first complex number and a second complex number; a decoder to decode the one or more instructions; a register file including a plurality of registers to store packed data including the first complex number and the second complex number; and one or more execution units to perform the one or more instructions, wherein the one or more execution units to generate a final result to include one or more dot-products in response to processing the instruction, wherein a first dot product is generated by multiplying lower portions of the first and second complex number and a second dot product is generated by multiplying upper portions of the first and second complex number, wherein a first result is generated by subtracting the second dot product from the first dot product, wherein a third dot product is generated by multiplying an upper portion of the first complex number with a lower portion of the second complex number and a fourth dot product is generated by multiplying a lower portion of the first complex number and an upper portion of the second complex number, wherein a second result is generated by adding the third and fourth dot product, wherein the final result is generated based on the first result and the second result.