Patent ID: 7009910

Claim:
A semiconductor memory comprising: a plurality of memory arrays each having a plurality of memory cells arranged along rows and columns, the plurality of memory arrays being partitioned into first and second memory banks in correspondence with one of a plurality of mask options such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays; and a row selection circuitry comprising: a first horizontal global row decoder configured to receive a first subset of addresses for the first memory bank and in response provide a first plurality of predecoded row address signals on a first plurality of lines extending only across the at least one but less than all of the plurality of memory arrays; and a second horizontal global row decoder configured to receive a first subset of addresses for the second memory bank and in response provide a second plurality of predecoded row address signals on a second plurality of lines extending only across the corresponding remainder of the plurality of memory arrays.