Patent ID: 7333367

Claim:
An integrated circuit memory device comprising: an integrated circuit substrate having a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array regions on a second side of the main cell array region; a plurality of main cells in the main cell array region, ones of the main cells including a main gate pattern having a main tunnel insulating layer on the integrated circuit substrate, a main charge storage layer on the main tunnel insulating layer, an inter-gate insulating layer on the main charge storage layer and a main control gate electrode on the inter-gate insulating layer; and a plurality of dummy cells in the first and second dummy cell array regions, ones of the dummy cells including a dummy gate pattern having a dummy tunnel insulating layer on the integrated circuit substrate, a dummy charge storage layer on the dummy tunnel insulating layer, a dummy inter-gate insulating layer on the dummy charge storage layer and a dummy control gate electrode on the dummy inter-gate insulating layer, the dummy tunnel insulating layer having a thickness that is greater than a thickness of the main tunnel insulating layer.