Patent ID: 8417961

Claim:
A processor, comprising: a control unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and a cryptographic unit configured to receive instructions issued by the control unit, wherein the received instructions include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, wherein the cryptographic unit is configured to perform a first CRC operation on a set of data in response to receiving the first instance of the CRC instruction, wherein the first CRC operation uses a generator polynomial to produce a checksum value from the set of data; wherein the cryptographic unit includes a first exclusive-or (XOR) unit and a second XOR unit, wherein the first XOR unit is configured to perform a first set of XOR operations between an initialization vector and a first portion of the set of data, and wherein the second XOR unit is configured to perform a second set of XOR operations between an output of the first XOR unit and a second portion of the set of data.