Patent ID: 7408220

Claim:
A non-volatile memory, comprising: a substrate; a plurality of columns of isolation structures located on the substrate; a plurality of rows of stacked gate structures located on the substrate and cross over the isolation structures, wherein each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate; a plurality of stripes of spacers located on the sidewalls of the stacked gate structures; a plurality of first dielectric layers located on a portion of the isolation structures adjacent to two rows of stacked gate structures, wherein one isolation structure is between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interfacing manner; a plurality of first conductive layers located between two neighboring first dielectric layers in the same row, and between two spacers in opposite direction; and a plurality of doping regions located in the substrate beneath the first conductive layers.