Patent ID: 7879718

Claim:
A method for forming an interconnect in a semiconductor memory device, the method comprising: forming a pair of source select transistors on a substrate, where forming each of the pair of source select transistors comprises: forming a first dielectric layer on the substrate, forming a charge storage layer on the first dielectric layer, forming a second dielectric layer on the charge storage layer, and forming a control gate layer on the second dielectric layer; forming a source region in the substrate between the pair of source select transistors; forming a first inter-layer dielectric between the pair of source select transistors; depositing a mask layer over the pair of source select transistors and the first inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors; etching the semiconductor memory device to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region; and forming a metal contact in the local interconnect area.