Patent ID: 7977983

Claim:
A device having synchronism capabilities, the device comprises: a first circuit that is adapted to receive a first clock signal; a second circuit that is adapted to receive a second clock signal; and a synchronizer that is coupled between the first and second circuit and is adapted to receive the second clock signal, to receive an input signal from the first circuit and to output an output signal of definite values to the second circuit; wherein the synchronizer comprises: a master latch, coupled to the first circuit and to a feedback circuit, the master latch comprising an input to receive the input signal, the input coupled to a first node of the master latch wherein the input signal is synchronized with the first clock signal: a master inverter, coupled to the master latch and to a feedback circuit, adapted to invert the signal latched by the master latch to provide a master inverter output signal; a slave latch, coupled to the master inverter, adapted to latch the master inverter output signal; a slave inverter, coupled between the slave latch and the second circuit, wherein the slave inverter inverts a master inverter output signal latched by the slave latch to provide an output signal of a definite level, wherein the output signal is synchronized with the second clock signal: wherein the first and second clock signals are mutually asynchronous: and a feedback circuit comprising an output coupled to the first node of the master latch, wherein the feedback circuit receives the master inverter output signal and the output signal to determine when a previous output value of the slave latch equals a current output value of the master latch and write to the master latch the feedback signal, wherein the feedback signal has a value that equals a previous output value of the slave latch when the previous output value of the slave latch equals the current output value of the master latch.