Patent ID: 8040735

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in row and column directions; a plurality of sense amplifier units configured to detect write completion of the selected memory cells; and a plurality of detection units arranged correspondingly to the sense amplifier units, each of the detection units forming a transfer path for transferring potential in accordance with detection signals output from the sense amplifier units, and detecting a sense amplifier unit corresponding to a portion where the transfer path breaks off as a sense amplifier unit including a write incompletion bit, wherein each of the detection units includes: a first conductivity type transfer gate having first and second gates, and having a current path inserted in the transfer path, a detection signal output from the sense amplifier unit being supplied to the first gate; a second conductivity type first transistor having a gate connected to one terminal of the current path of the transfer gate, one terminal of a current path of the first transistor receiving a control signal; a first conductivity type second transistor having a gate connected to the other terminal of the current path of the transfer gate, the second transistor having one terminal of a current path connected to the other terminal of the current path of the first transistor, a select signal being output from the other terminal of the current path; and a first circuit having an input terminal connected to the other terminal of the current path of the second transistor and having an output terminal connected to the second gate of the transfer gate, the first circuit conducting the transfer gate when the select signal is output from the other terminal of the current path of the second transistor.