Patent ID: 7505315

Claim:
A nonvolatile semiconductor storage apparatus comprising: a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2 x threshold voltages, the x-bit information being able to be read from each memory cell by applying a read voltage to the corresponding word line; a row decoder connected to the word lines to supply voltages to the word lines to operate the memory cells; and a sense amplifier device connected to the bit lines to read data stored in the memory cells and to hold the read data and data written to the memory cells, wherein the x-bit information corresponding to a certain threshold voltage differs from that corresponding to the adjacent threshold voltage by only 1 bit, 2 x −1 of the read voltages are each set for a pair of adjacent threshold voltages, and applying any of the read voltages to the word line determines the x-bit information stored in the memory cell, and at least two read voltages are set in order to determine information for each of the x bits.