Patent ID: 7672180

Claim:
A semiconductor memory device comprising: a first line of memory cells including a plurality of memory cells; a second line of memory cells electrically replaceable for said first line of memory cells; an address comparator for comparing an input address with a first address specifying said first line of memory cells as a failed address; a first converter for receiving a first signal from said first line of memory cells for converting the first signal into a first corresponding logic signal; a second converter for receiving a second signal from said second line of memory cells for converting the second signal into a second corresponding logic signal; a selector for selecting the second logic signal output when said address comparator has determined that the input address coincides with the failed address; and a controller for controlling test operation to cause said first converter to output a high level signal or a low level signal, said controller causing said second converter to output the low level signal when said first converter outputs the high level signal, and causing said second converter to output the high level signal when said first converter outputs the low level signal.