Patent ID: 7350032

Claim:
A cache comprising: a cache memory configured to store a plurality of cache blocks and a plurality of cache states, wherein each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks; and a cache control circuit coupled to the cache memory, wherein, responsive to a request from a local consumer that accesses a first cache block of the plurality of cache blocks, wherein a first cache state of the plurality of cache states corresponds to the first cache block, the cache control circuit is configured to change the first cache state to a transient state if a change from a current state to a new state is to be performed responsive to the request and performing the change from the current state to the new state includes performing at least a first communication on an interconnect to maintain coherency of the first cache block, and wherein a same transient state is used in response to any request from a local consumer for changing from any current state to any new state if the change includes at least one communication on the interconnect, and wherein the same transient state is used for changing to at least two different new states.