Patent ID: 7236404

Claim:
A non-volatile memory structure, comprising: a NROM memory array having a plurality of NROM cells organized by rows and columns, a first column of NROM cells having a first NROM cell and a second NROM cell, the first NROM cell having a first node, a second node and a third node, the second NROM cell having a first node, a second node and a third node; a first metal bit line connecting to the second node of the first NROM cell and the second node of the second NROM cell; and a second metal bit line connecting to a third node of the first NROM cell and the third node of the second NROM cell; wherein during an erase operation of the second node, the second node of the first NROM cell and the second node of the second NROM are connected a positive voltage, the third node of the first NROM cell and the third node of the second NROM cell are connected to a common node; and wherein during an erase operation of the third node, the second node of the first NROM cell and the second node of the second NROM are connected the common node, the third node of the first NROM cell and the third node of the second NROM cell are connected to the positive voltage.