Patent ID: 7826460

Claim:
A network-on-chip apparatus comprising: a plurality of network interfaces being independently connected to a plurality of processing elements; a network including a plurality of switches for controlling data transmission/reception among the network interfaces; and a plurality of bidirectional links for connecting between the network interfaces and the switches, and among the switches; wherein at least one of the plurality of network interfaces includes: an output packet buffer for outputting sequentially stored packets to a corresponding switch via a link connected to an output packet port; an input packet buffer for sequentially storing a packet received from the switch via an input packet port; a packet composer and decomposer for composing a packet using an address signal, a control signal and a data signal received from a corresponding processing element, storing the composed packet in the output packet buffer, decomposing a packet provided from the input packet buffer, decrypting the decomposed packet, and delivering the decrypted packet to the plurality of the corresponding processing element; and an autonomic clock control unit for controlling a clock frequency being output to the corresponding processing element according to a backlog of the output packet buffer, wherein the autonomic clock control unit comprises: a frequency controller for detecting a processing element's frequency according to the backlog of the output packet buffer; and a frequency generator for adjusting a clock frequency of the processing element according to a control signal received from the frequency controller.