Patent ID: 8230199

Claim:
A computer program product for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a machine architecture, the computer system configured to translate a virtual address into a translated address of a block of main storage in the computer system having a hierarchy of translation tables used for translation of said virtual address to obtain any one of an absolute address of a large block of main storage or a real address of a small block of main storage, wherein a real address is subject to prefixing to form an absolute address, wherein each block of main storage has an associated storage key separate and distinct from any of said translation tables, said PFMF machine instruction defined for said machine architecture, the computer program product comprising: a storage medium readable by said computer system, said computer readable medium storing instructions for performing a method comprising: fetching for execution said PFMF machine instruction, the PFMF machine instruction comprising an opcode field, a first register field for identifying a first general register and a second register field for identifying a second general register; and executing the PFMF machine instruction, the executing comprising: obtaining frame management information from said first general register wherein said frame management information comprises a set key control (SK) bit, a key field for specifying a plurality of access-protection bits, a clear frame control (CF) bit, and an indicator field (FSC) specifying the size of a frame of main storage, the frame of main storage being one of a large block of main storage and a small block of main storage, the access-protection bits comprising access-control bits (ACC); obtaining an operand address of a frame of main storage from said second general register; in response to the setting of said set key control bit being 1, setting storage access protection bits of a storage key associated with the frame of main storage to a value of said access-protection bits, the storage access protection bits comprising storage ACC bits for matching with a program access key to determine accessibility of a main storage location; and in response to the setting of said clear frame control bit being 1, clearing main storage of the frame of main storage by setting all bytes of the frame of main storage to zero.