Patent ID: 8898215

Claim:
A high-radix multiplier-divider for performing simultaneous multiplication and division in radix r of a multiplicand A=0·a −1 a −2 . . . a −n , a multiplier B=0·b −1 b −2 . . . b −n , and a divisor D=0·d −1 d −2 . . . d −n so that ( AB D ) where AB<D, comprising: a plurality of registers for storing the multiplicand, the multiplier, the divisor, a quotient, and a remainder, wherein the multiplicand is an input value; a first data switch having a first input receiving the multiplicand right-shifted by one digit (m-bits), a second input for sequentially receiving bits from the multiplier register corresponding to digits of the multiplier from the most significant digit to the least significant digit, and an output for outputting b −j−1 A r −1 where j is a counter of the multiplier digits; a digital lookup table having a first input for receiving a truncated shifted partial remainder, a second input for receiving a truncated divisor, and an output for outputting a quotient digit corresponding to the truncated shifted partial remainder and truncated partial divisor, the output being stored in the quotient register and left-shifted by the radix; a second data switch having a first input connected to the output of the digital lookup table, a second input receiving the divisor, and an output for outputting the product of the quotient digit and the divisor; and an addition module having inputs for receiving the output of the first data switch and the 2's complement output of the second data switch, the addition module being configured for recursively adding the inputs for each digit of the multiplier and outputting the truncated partial remainder at each iteration for input to the digital lookup table.