Patent ID: 8339873

Claim:
A device comprising: a memory array including a first bitline to communicate first information during a read operation, the first information including first storage state information from one of a first plurality of memory cells, a second bitline to communicate second information during the read operation, the second information including second storage state information from one of a second plurality of memory cells, a third bitline to communicate third information during the read operation, the third information including third storage state information from one of a third plurality of memory cells during the read operation, a fourth bitline to communicate fourth information during the read operation, the fourth information including fourth storage state information from one of a fourth plurality of memory cells, a fifth bitline to communicate fifth information during the read operation, the fifth information including fifth storage state information from one of a fifth plurality of memory cells; a first sense amplifier including a first input coupled to the first bitline to receive the first information, a second input coupled to the second bitline to receive the second information, a third input coupled to the third bitline to receive the third information, and an output to provide an indicator of the first storage state information based upon the first information, the second information and the third information; a second sense amplifier including a first input coupled to the second bitline to receive the second information, a second input coupled to the fourth bitline to receive the fourth information, a third input coupled to the first bitline to receive the first information, and an output to provide an indicator of the second storage state information based upon the second information, the fourth information and the first information; and a third sense amplifier including a first input coupled to the third bitline to receive the third information, a second input coupled to the first bitline to receive the first information, a third input coupled to the fifth bitline to receive the fifth information, and an output to provide an indicator of the third storage state information based upon the third information, the first information and the fifth information.