Patent ID: 6952791

Claim:
An apparatus comprising: a buffer for storing data; a write pointer coupled to the buffer, wherein the write pointer is configured to point to an entry in the buffer into which data is to be written, the write pointer to be clocked by a first clock; a read pointer coupled to the buffer, wherein the read pointer is configured to point to an entry in the buffer from which data is to be read, the read pointer to be clocked by a second clock that has a same clock frequency as the first clock; and a circuit configured to transfer a pointer value of the write pointer as the read pointer in response to an indication that a predetermined pattern of data is transmitted to the buffer for storage; and a synchronizing circuit coupled to the circuit to receive the indication of the predetermined pattern and, in response, to compensate for a skewing of the second clock from the first clock by synchronizing commencement of the read pointer to read from the buffer after data that is written into the buffer is stable.