Patent ID: 7629689

Claim:
A semiconductor integrated circuit having a logical function formed on a surface of a semiconductor substrate, comprising: an active element forming area for forming a plurality of active elements on the surface of the semiconductor substrate; a plurality of wiring layers over the surface of the semiconductor substrate; a connection pad formed over the plurality of wiring layers, the connection pad being divided into a probing area for probing and a bonding area for wire bonding, each of the probing area and the bonding area are arranged over the active element forming area; a first reinforcing structure between the probing area and the active element forming area formed by using at least one of the plurality of wiring layers such that remaining one or more of the plurality of wiring layers including one wiring layer which is directly over the active element forming area is configured to form circuit wires for realizing the logical function of the semiconductor integrated circuit under the first reinforcing structure; and a second reinforcing structure between the bonding area and the active element forming area formed by using the at least one of the plurality of wiring layers and an additional one of the plurality of wiring layers under the at least one of the plurality of wiring layers, wherein the number of the wiring layers containing, between the probing area and the active element area, part of any reinforcing structure is less than the number of the wiring layers containing, between the bonding area and the active element area, part of any reinforcing structure, and reinforcing structures are defined as including dummy patterns, which do not contribute to the logical function of the semiconductor integrated circuit.