Patent ID: 7392351

Claim:
A snoop filtering method for supporting cache coherency in a computing environment having multiple processing units, each processing unit having one or more cache memories associated therewith and an associated snoop filter device, a snoop filter device provided in 1:1 correspondence with an associated processing unit, said method comprising: at each snoop filter device associated with a processing unit: tracking cache line addresses of data that have been loaded into a cache memory level of its associated processing unit and storing cache line addresses in a first memory storage means, said first memory storage means comprising a first plurality of stream register sets, each stream register set comprising one or more stream registers, each stream register including a base register and a corresponding mask register, said base register tracking address bits common to all cache line addresses represented by the stream register; and, said mask register tracking bits representing differences between a base register address and subsequent load/store addresses to the cache memories of said processing unit included in its corresponding base register, wherein differing bit positions are indicated in said mask register to indicate corresponding bits of said base register as insignificant; receiving snoop requests from a plurality of memory writing sources; and comparing an address of a received snoop request against addresses stored in said first memory storage means; and, forwarding said received snoop request to said processing unit in response to matching an address stored in said first memory storage means, or otherwise discarding said snoop request, whereby a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of said computing environment.