Patent ID: 7692483

Claim:
A method including: coupling a circuit node including at least one source/drain node of at least one MOS transistor to a bias-voltage circuit; and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node, the potential having a magnitude selected to prevent a parasitic bipolar transistor of the at least one MOS transistor from turning on, wherein the bias-voltage circuit includes: an enable input node; a bias-voltage output node; a first P-channel MOS transistor connected in series with a second P-channel MOS transistor between a first supply potential and the bias-voltage output node; a first N-channel MOS transistor connected in series with a second N-channel MOS transistor between a second supply potential and the bias-voltage output node; a gate of the first N-channel MOS transistor coupled to the enable input node and a gate of the first P-channel MOS transistor coupled to the input node through an inverter; and gates of the second N-channel MOS transistor and the second P-channel MOS transistor coupled to the bias-voltage output node.