Patent ID: 8549235

Claim:
A method of performing an address match check in a processor, comprising: requesting, by an instruction executing on a processor, an address; performing a partial match check by comparing a first set of bits included in the requested address to a second set of bits contained in a registry address that is stored in an address registry, wherein the first set of bits corresponds to less than all of a plurality of bits included in the requested address and the second set of bits corresponds to less than all of a plurality of bits included in the registry address; in response to determining the first set of bits matches the second set of bits, suspending execution of the instruction; in response to determining the first set of bits matches the second set of bits and the instruction is a demand instruction, performing a full match check by comparing at least remaining bits in the requested address to at least remaining bits in the address registry; and in response to determining the first set of bits does not match the second set of bits, continuing execution of the instruction.