Patent ID: 7779393

Claim:
A system, comprising: a computer; a computer accessible storage medium storing program instructions executable to implement a test module and an analysis module; wherein the instructions executable to implement the test module include instructions executable to coordinate an execution of a multithreaded test program on a test platform including a plurality of processing elements; and wherein the instructions executable to implement the analysis module include instructions executable to: automatically represent memory operations performed during execution of the multithreaded test program using a directed graph, wherein each node of the directed graph represents a memory operation performed by one of the plurality of processing elements, wherein representing memory operations performed during execution of the multithreaded test program includes adding edges to the directed graph, wherein a given node of the directed graph includes a vector clock data structure, wherein the vector clock data structure for the given node is configured to store information specifying an edge for each of the other ones of the plurality of processing elements, wherein each specified edge for the given node indicates the earliest node in the directed graph that follows the given node in a global memory order, but does not indicate other nodes; and automatically determine whether results of the execution of the multithreaded test program violate a memory consistency model by determining whether a cycle is found in the directed graph, wherein said determining whether the cycle is found includes traversing edges in the directed graph, wherein said traversing includes using one or more vector clock data structures for one or more corresponding nodes, wherein use of the one or more vector clock data structures reduces a number of edges to be traversed.