Patent ID: 8159880

Claim:
A NAND flash memory using a programming scheme programming a memory cell transistor from a source line side, the NAND flash memory comprising: a first selection gate transistor comprising a first end connected to a source line; a second selection gate transistor comprising a first end connected to a bit line; and a plurality of memory cell transistors connected in series between a second end of the first selection gate transistor and a second end of the second selection gate transistor, data being able to be programmed into each of the plurality of the memory cell transistors by applying a voltage to a control gate thereof, controlling a charge quantity of a floating gate thereof, and changing a threshold voltage, and in an erase state each of the memory cell transistors being set equal to a first threshold voltage being the lowest threshold voltage, wherein the data are assigned to threshold voltages which are higher than the first threshold voltage corresponding to the erase state, N+1 threshold voltages are set for the memory cell transistors, N data are assigned to N threshold voltages other than the first threshold voltage corresponding to the erase state, and a first programming is conducted, as regards a threshold voltage of one memory cell transistor included in the plurality of the memory cell transistors, by setting one data of two-valued data to a second threshold voltage which is lower next to the first threshold voltage and setting the other data of the two-valued data to a third threshold voltage which is higher than the second threshold voltage.