Patent ID: 7843065

Claim:
A flash memory device comprising: a first insulating layer on a base insulating layer on a substrate; a lower wire layer that fills a trench in the first insulating layer; a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer; a middle wire layer that fills a trench in the second insulating layer; and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer, the middle wire layer and the upper wire layer are electrically connected to each other, wherein the first insulating layer includes a low-k layer in contact with the base insulating layer, wherein each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer includes an FSG layer; and wherein a first FSG layer included in the first insulating interlayer and a second FSG layer included in the second insulating layer are formed in an interface between the middle wire layer and the first insulating interlayer.