Patent ID: 7259996

Claim:
A flash memory, comprising: at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate; a memory control circuit for controlling operations on the at least one floating-gate memory cell; a wordline coupled to the control gate of the at least one memory cell; and a wordline drive transistor coupled to the wordline; wherein the memory control circuit is adapted to apply a positive voltage relative to a common voltage to the source while simultaneously applying a first negative voltage relative to the common voltage to the control gate during an erase period; wherein the memory control circuit is further adapted to discharge the positive voltage while continuing to apply the first negative voltage, the discharging to occur at a rate sufficient to couple a second negative voltage to the control gate; and wherein the memory control circuit is further adapted to leave the positive voltage in a discharged state for a remainder of the erase period.