Patent ID: 7141476

Claim:
A method of forming a transistor, comprising: providing a wafer comprising a semiconductor layer, a gate dielectric, and a layer of gate material, wherein the gate dielectric is located between the semiconductor layer and the layer of gate material; patterning the semiconductor layer to leave a first portion of the semiconductor layer; after the patterning the semiconductor layer, patterning the layer of gate material, wherein the patterning the layer of gate material leaves a second portion of the layer of gate material not covered by a remaining portion of the semiconductor layer, wherein after the patterning the layer of gate material, a third portion of the layer of gate material remains and is covered by the first portion of the semiconductor layer; forming a bottom gate of a transistor wherein at least a portion of the bottom gate is formed from the third portion, forming a second layer of gate material after the patteming the layer of gate material; forming a layer of mask material over the second layer of gate material; patterning the layer of mask material to form a mask; forming a top gate of the transistor, wherein the forming a top gate includes patterning the second layer of gate material as per the mask to form a gate structure.