Patent ID: 8233335

Claim:
A semiconductor storage device comprising: a memory cell array; a first selection circuit to which data read out from the memory cell array is input via a first internal bus; a second selection circuit to which the data output from the first selection circuit is input via a second internal bus; and a data output circuit to which the data output from the second selection circuit is input via a third internal bus, the semiconductor storage device outputting the data from the data output circuit to an external bus, wherein the first internal bus, the second internal bus, and the third internal bus have bus widths decreasing stepwise from the memory cell array side to the data output circuit side, and the first selection circuit and the second selection circuit divide the data, which is input via the first or second internal bus, according to a rate of a decrease in bus width in the input and the output, time-divide the divided data, and output the divided data to the second or third internal bus.