Patent ID: 7288980

Claim:
A multiple mode clock receiver, comprising: first and second input AC-coupled capacitors, wherein said first and second input AC-couple capacitors comprise first and second N-channel devices, respectively, each having a source and a drain coupled together at respective input and a gate coupled to a corresponding one of a first junction and a second junction; a first voltage divider coupled between DC source voltages and having said first junction coupled to said first input AC-coupled capacitor; a second voltage divider coupled between DC source voltages and having said second junction coupled to said second AC-coupled capacitor; a differential amplifier, having a differential input including a first input coupled to said first junction and a second input coupled to said second junction, and having an output; a third N-channel device having a source coupled to said source of said first N-channel device and a drain and a gate coupled to said first junction; and a fourth N-channel device having a source coupled to said source of said second N-channel device and a drain and a gate coupled to said second junction; wherein said output of said differential amplifier provides an output clock signal that is aligned with an input clock signal provided through at least one of said first and second input AC-coupled capacitors.