Patent ID: 8653635

Claim:
A power overlay (POL) structure comprising: a POL sub-module, the POL sub-module comprising: a dielectric layer having a plurality of vias formed therethrough, the dielectric layer comprising a dielectric lamination or dielectric film; at least one semiconductor device attached to the dielectric layer, with each of the at least one semiconductor device including a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate; and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, the metal interconnect structure extending through the vias formed through the dielectric layer so as to be connected to the plurality of connection pads; a leadframe electrically coupled to the POL sub-module, the leadframe comprising a plurality of leads configured to make an interconnection to an external circuit structure; and a multi-layer substrate having a first surface and a second surface, wherein the POL sub-module and each of the plurality of the leads of the leadframe is directly attached to the first surface of the multi-layer substrate, such that electrical coupling of the POL sub-module to the external circuit structure is achieved at a multi-layer substrate plane.