Patent ID: 7834390

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in said semiconductor substrate; an erase gate facing an upper surface of said floating gate; a first device isolation structure having a first projecting portion that projects from said semiconductor substrate; and a second device isolation structure having a second projecting portion that projects from said semiconductor substrate, wherein said first projecting portion has a first sloping surface connecting between an upper surface and a side surface of said first device isolation structure, said second projecting portion has a second sloping surface connecting between an upper surface and a side surface of said second device isolation structure, said first sloping surface and said second sloping surface face each other, an interval between said first sloping surface and said second sloping surface becomes larger away from said semiconductor substrate, said floating gate is sandwiched between said first projecting portion and said second projecting portion, and at least has a portion located on said semiconductor substrate side of said first sloping surface and said second sloping surface.