Patent ID: 7853747

Claim:
An embedded disk controller, comprising: a first processor in communication with a first bus; a second processor in communication with a second bus; and an external bus controller (“EBC”) that is located on the embedded disk controller, the EBC being coupled to an external bus and to at least one of the first bus and the second bus, wherein the EBC manages a plurality of memory devices external to the embedded disk controller via the external bus, wherein a first memory device of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second memory device of the plurality of memory devices, wherein the EBC is coupled to the first memory device and the second memory device via the same external bus, wherein the at least one of the different timing characteristics and the different data width are associated with the external bus, and wherein the EBC includes memory to store, for each of the plurality of memory devices, a device range and a segment descriptor to respectively indicate address space sizes and timing characteristics.