Patent ID: 7669109

Claim:
A spread spectrum processor coupled to a program memory for storing a sequence of operating instructions, said spread spectrum processor comprising: a macro matrix defining a Low Density Parity Check (LDPC) code said macro matrix having zero-valued and non-zero-valued entries arranged in block rows and block columns and in which each zero-valued entry corresponds to a p×p zero-valued matrix and each non-zero-valued entry corresponds to a p×p permutation matrix that has at most a single “1” entry in each row and each column and “0” entries elsewhere to define a parity check matrix, wherein the block columns of the macro matrix are grouped into groups of block columns so that at most one column in any group has a “1” entry in any row, at least one of the groups including more than one block column, and wherein the columns of the parity check matrix correspond to input nodes and the rows of the parity check matrix correspond to parity check sums; local memory for code execution and data buffering; an embedded central processing unit (CPU) for executing said sequence of operating instructions to perform a plurality of operations comprising: receiving a set of input values corresponding to input nodes of the macro parity check matrix; estimating, for each of the input nodes, over each of a plurality of parity check sums of the LDPC code, a check node value using values of other input nodes contributing to the parity check sum; estimating, for each of the input nodes, a probability value using the estimates of the check node values for that input node; and repeating the estimating operations to a termination criterion.