Patent ID: 7916718

Claim:
A shared memory switch, comprising: a plurality of ports configured to receive and transmit frames of data; frame classification circuitry configured to classify the frames into a plurality of traffic classes; frame memory configured to store the frames, the frame memory including a plurality of shared memory partitions, each of the shared memory partitions corresponding to one or more of the traffic classes, each of the shared memory partitions having a plurality of counters associated therewith, the plurality of counters including at least one per port memory usage counter for each of the plurality of ports and at least one aggregate memory usage counter, the counters associated with each of the shared memory partitions being independent of the counters associated with others of the shared memory partitions; and congestion management circuitry configured to implement congestion management policies for each of the partitions independently with reference to the counters associated with each of the partitions; wherein the at least one per port memory usage counter for each of the ports comprises a private ingress counter which tracks memory usage for frames received on the corresponding port, and wherein the at least one aggregate memory usage counter comprises a global ingress counter which tracks memory usage for frames received on all ports and stored in the corresponding shared memory partition excluding the frames tracked by the private ingress counters.