Patent ID: 7738049

Claim:
An active device array substrate, comprising: a substrate; a plurality of semiconductor patterns disposed on the substrate; a gate insulator layer disposed on the substrate to cover the semiconductor patterns; a first patterned conductive layer disposed on the gate insulator layer, the first patterned conductive layer comprising a plurality of scan lines, a plurality of gate electrodes disposed on each of the semiconductor patterns and connected with the scan lines, and a plurality of common electrodes disposed between the scan lines; a dielectric layer disposed on the gate insulator layer to cover the first patterned conductive layer; a plurality of transparent electrodes disposed on the dielectric layer; a passivation layer disposed on a portion of the dielectric layer so as to expose the transparent electrodes, wherein the gate insulator layer, the dielectric layer, and the passivation layer comprise a plurality of contact windows to expose the semiconductor patterns; a second patterned conductive layer disposed on the passivation layer, wherein the second patterned conductive layer comprises a plurality of contact conductors disposed in the contact windows, a plurality of data lines electrically connected with a portion of the contact conductors, and a plurality of reflective electrodes electrically connected with corresponding transparent electrodes respectively, and a portion of the common electrodes is disposed under the second patterned conductive layer; and a plurality of material pattern layers disposed on the second patterned conductive layer, wherein the material pattern layers and the second patterned conductive layer are different.