Patent ID: 7592225

Claim:
A method of forming an integrated semiconductor device including a non-volatile memory array, comprising: providing a first dielectric layer above a substrate; providing a first conductive layer above said first dielectric layer; providing an intervening layer above said first conductive layer, said intervening layer including an upper surface; providing a set of strips of sacrificial material having sidewalls elongated in a first direction above said intervening layer; forming spacers along said sidewalls of said strips of sacrificial material, said spacers contacting said upper surface of said intervening layer and having a material composition substantially similar to said intervening layer; and etching said strips, said intervening layer, and said first conductive layer to form a plurality of conductive gate regions, said plurality of conductive gate regions are floating gates of said non-volatile memory array, said floating gates having substantially vertical sidewalls elongated in said first direction and being separated from adjacent floating gates in a second direction with spaces therebetween; providing a second dielectric layer along said sidewalls of said floating gates, and providing control gates at least partially occupying said spaces between adjacent floating gates, said control gates separated from said sidewalls of said floating gates by said second dielectric layer.