Patent ID: 8176282

Claim:
A computer system for managing a cache memory, the system comprising: a processor having an address interface for sending a memory access message including an address in physical memory and a domain identification (ID); a cache memory portioned into a plurality of partitions, where each partition includes a plurality of physical cache addresses; a cache controller having an interface to accept the memory access message from the processor, the cache controller determining if the address in physical memory is cacheable, and if cacheable, cross-referencing the domain ID to a cache partition identified by partition bits, deriving an index from the physical memory address, creating a partition index by combining the partition bits with the index, and granting the processor access to an address in cache defined by partition index; and, wherein the cache controller sequentially accepts a first memory access message with a first address in physical memory and a first domain ID, and a second memory access message with a second address in physical memory and a second domain ID, the cache controller cross-referencing the first and second domain IDs to a shared first cache partition, and granting access to the first and second cache addresses in the first cache partition.