Patent ID: 7535748

Claim:
A semiconductor memory device comprising: a single or plurality of memory cell arrays each having a plurality of memory cells arranged in rows and columns, a plurality of row select lines arranged to correspond to the respective rows of the plurality of memory cells and connected to the memory cells in the corresponding rows, and a plurality of column select lines arranged to correspond to the respective columns of the plurality of memory cells and connected to the memory cells in the corresponding columns; a row control circuit for controlling potentials on the respective row select lines; and a column control circuit for controlling potentials on the respective column select lines, wherein each of the memory cells has a pair of a variable-resistance element and a diode, the pair being connected in series between a first node and a second node, the first node is connected to the corresponding column select line, the second node is connected to the corresponding row select line, the column control circuit has column-select-line driver circuits each for controlling the potential on one of the column select line in one-to-one correspondence to the column select lines, and each of the column-select-line driver circuits is constructed such that corresponding potentials are applied thereto from at least four predetermined potential supply sources.