Patent ID: 8438308

Claim:
A non-transitory memory device storing instructions, the instructions comprising: one or more instructions which, when executed by one or more processors, cause the one or more processors to: determine that an occurrence of a particular event may cause a failure of at least two links or at least two nodes; determine a relationship between the at least two links or the at least two nodes based on determining that the occurrence of the particular event will cause the failure of the at least two links or the at least two nodes; determine a first value associated with the at least two links or the at least two nodes, the first value indicating a likelihood that a failure of a first link of the at least two links, or a failure of a first node of the at least two nodes, resulting from the occurrence of the particular event, will result in a failure of other links of the at least two links or other nodes of the at least two nodes; assign, based on the relationship, the first value to: each link of the at least two links, or each node of the at least two nodes; determine a first cost for each link, of the at least two links, or each node, of the at least nodes, based on the first value, the first cost being associated with transmitting data via the link or the node; and determine, based on the first cost, a primary path and a secondary path through a network.