Patent ID: 7225047

Claim:
A method of processing a plurality of wafers for manufacturing semiconductor devices, the method sequentially comprising: (a) measuring at least one critical dimension of at least one device fabricated on at least one of the plurality of wafers by a metrology tool of an implant-annealing process module before the at least one of the plurality of wafers has been processed in at least one implant or annealing processing tool of the implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device; (b) determining at least one control parameter value of the at least one implant or annealing processing tool based on the measured at least one critical dimension, wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an energy and tilt level, a pocket implant dose level, and a channel and channel V T adjust implant dose level; (c) controlling the at least one implant or annealing processing tool of the implant-annealing process module to process the at least one of the plurality of wafers based on the at least one control parameter value; (d) measuring at least one post process dimension of the at least one of the plurality of wafers after step (c), wherein the measured at least one post process dimension is different than the measured at least one critical dimension; (e) determining whether the measured at least one post process dimension is within a first predetermined range; and (f) adjusting the at least one implant or annealing processing tool of the implant-annealing process module upon determining that the measured at least one post process dimension is not within the first predetermined range.