Patent ID: 8872251

Claim:
A semiconductor device comprising: a first semiconductor layer comprising impurity regions; a second semiconductor layer comprising a first region, a second region, a third region, a fourth region and a fifth region; a first insulating film over the first semiconductor layer and the second semiconductor layer; a floating gate over the first insulating film, the floating gate overlapping with the first semiconductor layer and the second semiconductor layer; a second insulating film over the floating gate; a control gate over the second insulating film, the control gate overlapping with the first semiconductor layer, the second semiconductor layer, and the floating gate, a first conductive film over the control gate, the first conductive film being electrically connected to the impurity regions; a second conductive film over the control gate, the second conductive film being electrically connected to the fourth region; and a third conductive film over the control gate, the third conductive film being electrically connected to the fifth region, wherein the floating gate overlaps with the first region, wherein the first region is interposed between the second region and the third region, wherein the second region is interposed between the first region and the fourth region, wherein the third region is interposed between the first region and the fifth region, wherein each of the second region, the third region, the fourth region, and the fifth region comprises an impurity element, wherein an impurity concentration of the second region and the third region is lower than that of the fourth region and the fifth region, wherein the first conductive film entirely overlaps with the first semiconductor layer, and wherein the second conductive film and the third conductive film partially overlap with the second semiconductor layer.