Patent ID: 8679902

Claim:
A method for fabricating a nanowire field effect transistor device, the method comprising: depositing a first sacrificial layer on a substrate; depositing a first layer of a semiconductor material on the first sacrificial layer; depositing a second sacrificial layer on the first layer of semiconductor material; depositing a second layer of the semiconductor material on the second sacrificial layer; pattering and removing portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer; patterning a dummy gate stack over a portion of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer; forming source and drain regions over exposed portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer; forming spacers along sidewalls of the dummy gate stack prior to forming the source and drain regions, the spacers being retained in the nanowire field effect transistor device; removing the dummy gate stack to define a cavity; removing exposed portions of the first sacrificial layer and the second sacrificial layer to define a first nanowire including an exposed portion of the first semiconductor layer and a second nanowire including an exposed portion of the second semiconductor layer; forming dielectric layers along sidewalls of the spacers; and forming gate metal layers about the first nanowire and the second nanowire.