Patent ID: 7227382

Claim:
A driver circuit comprising: a plurality of pull-up circuits in parallel with each other between a voltage node and a signal node, wherein each pull-up circuit includes a pull-up transistor, wherein each of the plurality of pull-up circuits includes a resistance which is binary weighted with respect to the resistances of other ones of the plurality of pull-up circuits; a plurality of pull-down circuits in parallel with each other between the signal node and a reference node, wherein each pull-down circuit includes a pull-down transistor, wherein each of the plurality of pull-down circuits includes a resistance which is binary weighted with respect to the resistances of other ones of the plurality of pull-down circuits; control logic coupled to a gate terminal of each pull-up transistor of the plurality of pull-up circuits and a gate terminal of each pull-down transistor of the plurality of pull-down circuits, wherein the control logic is configured to, in an emphasized mode, to cause the driver circuit to transmit logic signals having a voltage swing of a first magnitude, and in a de-emphasized mode, to cause the driver circuit to transmit logic signals having a voltage swing of a second magnitude, wherein the second magnitude is less than the first magnitude, and wherein an output impedance of the driver circuit for transmissions in the emphasized mode and transmissions in the de-emphasized mode is substantially equal.