Patent ID: 8110462

Claim:
A method of forming an integrated circuit including an ESD protection device, comprising: forming a plurality of source regions, drain regions and gates in or on generally elongate parallel finger regions of a semiconductor substrate defined within a moat region surrounded by an insulating barrier on the substrate; the gates comprising dielectric material overlying channel regions within the substrate between respective ones of the source and drain regions, and conductive material overlying the dielectric material; wherein the semiconductor substrate is doped to have a net one of an N or P conductivity type; the source and drain regions are doped to have a net other of the N or P conductivity type; and at least a portion of a respective end region of one or more of the substrate finger regions is doped to provide a higher net doping of the one of the N or P conductivity type than a corresponding net doping of a corresponding respective middle region of the same one or more finger regions, so that the end region with the higher net doping is provided with an initial trigger voltage that is lower than a trigger voltage at the corresponding middle region; wherein the semiconductor substrate is provided with an initial doping of the one of the N or P conductivity type; and forming the plurality of source regions, drain regions and gates includes providing a supplemental doping of the one of the N or P conductivity type at the portion of the end region; and wherein the supplemental doping is provided prior to formation of the gates.