Patent ID: 7148522

Claim:
An integrated circuit structure, comprising: a silicon semiconductor substrate; N− and P− implanted regions in the silicon semiconductor substrate; a vertical P-type silicon pillar; gate oxide around the sides of the P− Si pillar and over the P− implantation region; a polysilicon gate over the gate oxide in the P− implantation region; an implanted polysilicon gate adjacent the P− Si pillar; implanted N− source/drain areas adjacent the polysilicon gate over the P− implantation region; nitride spacers around at least one of the polysilicon gates and the P− Si pillar; N+ implantations in the N− source/drain areas, in the top of the P− Si pillar, and in the top of the polysilicon gate over the P− implantation region; a self-aligned P+ implantation in the N− implantation adjacent the P− Si pillar; respective salicide layers over the N+ and P+ implantations; and an interconnect between the salicide layer over the top of the P− Si pillar and one of the salicide layers over the N− source/drain areas.