Patent ID: 7110485

Claim:
A clock control circuit for use in a multi-channel baud-rate timing recovery loop, comprising: a plurality of first amplifiers each generating proportional outputs responsive to input from a corresponding one of a plurality of phase detectors; a plurality of first resettable phase error integrators each connected to one of the plurality of first amplifiers for accumulating proportional outputs until a programmable threshold is reached, said resettable phase error integrators outputting a pulse and resetting responsive to reaching said programmable threshold; at least one second amplifier for generating a second output responsive to input from at least one of the plurality of phase detectors; an integrator for integrating the second output to generate an integrating output proportional to a frequency offset; a second resettable phase error integrator for accumulating integrating outputs until a second programmable threshold is reached, said second resettable phase integrators outputting a pulse and resetting responsive to reaching said second programmable threshold; and a plurality of Mod-N integrators for generating a frequency and phase corrected clock control signal to select an N sampling phase of N-tap digitally controlled oscillators responsive to outputs of the plurality of first resettable phase error integrator and the second resettable phase error integrator.