Patent ID: 7581202

Claim:
A method of generating and placing of test structures in test chips comprising: creating a control data set for one or more device types, wherein the control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords, and wherein the keywords each define (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, and (c) placement information of the test structures relative to one or more pad allocations of at least one pad array; generating a test structure layout in response to the control data set; placing the test structure layout within a given pad array layout of the at least one pad array as a function of the set of keywords, wherein the pad array layout is configured for enabling a fabrication of corresponding test structures in test chips; and establishing, for one or more device types of a given semiconductor technology, a predefined set of keywords in which each keyword defines (i) the one or more pad allocations for each test structure of a given device type, (ii) the number quantity of test structures for the given device type, and (iii) the placement information of the test structures relative to one or more pad allocations of the at least one pad array, and wherein the set of predefined keywords comprise definitions stored on a computer readable medium, the predefined set of keywords further defining one or more classifications which are used in driving the generating and placing of test structures.