Patent ID: 7372305

Claim:
A scannable latch circuit comprising: a first dynamic logic gate having a first clock input coupled to a data clock signal, a second clock input coupled to a scan clock signal, and an output coupled to a first dynamic node, wherein the first dynamic node is pre-charged to a first logic state when both the data clock signal and the scan clock signal have the first logic state and the first dynamic node is evaluated by a logic tree to a first Boolean combination of a plurality of first logic signals when the data clock signal is has a second logic state and the scan clock signal has the first logic state; a scan latch circuit having an input coupled to a scan input signal and a scan output, wherein a logic state of the scan input signal is coupled to the scan output when the scan clock signal has the first logic state and a logic state of the scan output is latched when the scan clock has the second logic state; a scan pull-down tree having a first input coupled to the scan output a second input coupled to the scan clock, and an output node coupled to the first dynamic node, wherein the scan pull-down tree evaluates the first dynamic node to a logic state in response to a logic state of the scan output when the scan clock has the second logic state; and a static latch having a first input coupled to the first dynamic node, a second input coupled to the scan clock signal, a third input coupled to the data clock signal, a latch output coupled to a scan path and a data path, wherein a logic state is set to the latch output in response to a logic state of the first dynamic node when either the scan clock or the data clock transition to the second logic state and the logic state of latch output is held when both the scan clock and the data clock have the first logic state.