Patent ID: 7478225

Claim:
A processor, comprising: instruction fetch logic configured to issue a first instruction from one of a plurality of threads during one execution cycle and to issue a second instruction from another one of said plurality of threads during a successive execution cycle, wherein each of said plurality of threads is assigned to a corresponding one of a plurality of thread groups, and wherein each of said plurality of thread groups includes at least two of said plurality of threads; a first execution unit configured to execute a shorter-latency instruction and to write a result of said shorter-latency instruction to a result write port during a first writeback stage that occurs a first number of execution cycles after issue of said shorter-latency instruction; and a second execution unit configured to execute a longer-latency instruction and to write a result of said longer-latency instruction to said result write port during a second writeback stage that occurs a second number of execution cycles after issue of said longer-latency instruction, wherein said second number is greater than said first number, and wherein said longer-latency instruction corresponds to a particular one of said plurality of thread groups; wherein said instruction fetch logic is further configured to guarantee access by said second execution unit to write said result of said longer-latency instruction to said result write port during said second writeback stage by preventing issue of any other instruction corresponding to said particular thread group during an execution cycle for which said first writeback stage collides with said second writeback stage; and wherein said instruction fetch logic is further configured to issue an instruction corresponding to a thread group other than said particular thread group during an execution cycle for which said first writeback stage collides with said second writeback stage.