Patent ID: 7912886

Claim:
An apparatus, comprising: an integrated circuit (IC) configured to load a first word of an exponent vector having a plurality of words from memory into a first register, wherein the first register is configured to hold a number of bits corresponding to one word; the IC further configured to load the first word from the first register to a second register, wherein the second register is configured to hold the number of bits corresponding to one word; the IC further configured to load a second word of the exponent vector into the first register, wherein the second word is sequential in position to the first word in the exponent vector; the IC further configured to load at least one bit from the second register into an arithmetic logic unit (ALU); the IC further configured to perform modular exponentiation on the at least one bit from the second register to generate a first result; the IC further configured to generate a public key based upon, at least in part, the first result; the IC further configured to perform double exponentiation, wherein the IC is configured to: load a third word of the exponent vector into a third register wherein the third register is configured to hold the number of bits corresponding to one word, load the third word from the third register to a fourth register wherein the fourth register is configured to hold the number of bits corresponding to one word, load a fourth word of the exponent vector into the third register, wherein the fourth word is sequential in position to the third word in the exponent vector, load at least one bit from the fourth register to the ALU, perform modular exponentiation on the at least one bit from the fourth register to generate a second result, and generate a public key based upon, at least in part, the second result, wherein the IC is further configured to alternate loading the at least one bit from the second register and the at least one bit from the fourth register into the ALU.