Patent ID: 7082057

Claim:
A semiconductor memory device, comprising: a field-effect transistor provided on a surface of at least one of (i) a P-type semiconductor substrate, (ii) a P-well region provided in a semiconductor substrate, and (iii) a P-type semiconductor film provided on an insulator, the field-effect transistor including two N-type diffusion layer regions, a gate electrode, and a charge storage section, holes being injected into the charge storage section by applying a reference voltage to one of the N-type diffusion layer regions, a voltage higher than the reference voltage to the other of the N-type diffusion layer regions, a voltage lower than the reference voltage to the gate electrode, and a voltage higher than the reference voltage to the at least one of (i) the P-type semiconductor substrate, (ii) the P-well region, and (iii) the P-type semiconductor film.