Patent ID: 7805590

Claim:
A method for interfacing a processor to a coprocessor, wherein the processor is coupled to the coprocessor via a processor/coprocessor interface, the coprocessor capable of performing a plurality of coprocessor operations, comprising: the processor performing an instruction fetch from a target address, wherein the processor has a standard instruction set, and wherein the standard instruction set of the processor comprises a plurality of opcodes; in response to the processor performing the instruction fetch from the target address, the coprocessor initiating one of the plurality of coprocessor operations, wherein the one of the plurality of coprocessor operations is selected based on at least a portion of the target address; the coprocessor using the target address to determine an opcode of a first instruction, wherein the opcode of the first instruction is one of the plurality of opcodes of the standard instruction set of the processor; the coprocessor transferring the first instruction to the processor; the processor decoding and executing the first instruction to produce a result; and the coprocessor receiving at least a portion of the result from the first instruction, wherein the first instruction is within the standard instruction set of the processor and is not a special instruction related to the processor/coprocessor interface.