Patent ID: 7502273

Claim:
A static random access memory (SRAM) macro comprising: a cell array having one or more two-port SRAM cells addressed by a plurality of bit lines and word lines including write bit lines, complementary write bit lines, and write word lines for write operation and read bit lines and read word lines for read operation; a plurality of reference cells coupled to a read reference bit line separate from the plurality of the bit lines addressing the SRAM cells and a plurality of read word lines for read operation of the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.