Patent ID: 7902024

Claim:
A method for forming a memory device, comprising: forming a stacked structure including a first floating gate electrode and a mask pattern on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above the adjacent isolation layers; forming a gate spacer overlapping a sidewall of the stacked structure protruding above the isolation layer, the sidewall of the stacked structure including portions of the first floating gate electrode and the mask pattern; forming a second floating gate electrode by partially removing a portion of the gate spacer, the second floating gate electrode being electrically connected to the first floating gate electrode and on at least one of the adjacent isolation layers; providing an insulation layer on the isolation layer, a first insulation pattern being formed by etching the insulation layer before forming the second floating gate electrode, and a second insulation pattern being formed by the etching the first insulation pattern after forming the second floating gate electrode; removing the mask pattern on the first floating gate electrode; forming a dielectric layer over the first and second floating gate electrodes; and forming a control gate over the dielectric layer and the first and second floating gate electrodes.