Patent ID: 8598666

Claim:
A semiconductor structure, comprising: a semiconductor substrate; a first insulating material layer on the semiconductor substrate; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; a semiconductor layer on the insulating buried layer; transistors formed on the semiconductor layer, the transistors at least comprising a first group of transistors and a second group of transistors, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer, the conductive contact being isolated from the transistors by means of at least one of the isolation structures, and the first conductive material layer being electrically connected to outside by the conductive contact to realize control of the back-gate voltages of the first group of transistors.