Patent ID: 8906805

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a stacked structure of alternatingly deposited sacrificial layers and insulating layers on an upper surface of a substrate, the upper surface extending in a first direction and a second direction that is substantially perpendicular to the first direction, the stacked structure extending in a third direction that is substantially perpendicular to the first direction and the second direction; forming a recess group that includes a plurality of first recesses that penetrate the sacrificial layers except a first one of the deposited sacrificial layer; forming a buried insulating layer group that includes buried insulating layers that are configured to substantially fill the plurality of first recesses; forming a contact plug group that includes contact plugs that are configured to penetrate an uppermost one of the insulating layers and the buried insulating layers; wherein forming the stacked structure includes forming 2 n deposited sacrificial layers and 2 n deposited insulating layers, wherein n is an integer that is greater than or equal to two, and wherein forming the recess group is performed by n quantity etch processes, each of the etch processes removing a portion of the stacked structure.