Patent ID: 7886132

Claim:
A method of processing program instructions within a processor, the method comprising: fetching an instruction stream containing a region of predicated instructions associated with multiple conditional execution paths within the instruction stream, wherein the region contains a predicated region identifying operation code specifying the beginning of the region and wherein the region contains multiple instructions for at least one of the multiple conditional execution paths; decoding the predicated instructions within the region, wherein each target register specified in the region that is targeted to receive a result of one of the predicated instructions included in one of the multiple conditional execution paths also receives a result of another of the predicated instructions for each of the other multiple execution paths; assigning associated storage resources within the processor to represent said each specified target register, whereby an instruction within each of the multiple execution paths targets each associated storage resource; dispatching the predicated instructions to one or more execution units within the processor; resolving conditions within the processor to determine which one of the multiple conditional execution paths is to-be-taken, wherein the conditions are resolved by an operation outside the region of predicated instructions; and executing the predicated instructions with the one or more execution units, wherein only one of the predicated instructions targeting each target register is selectively executed, and wherein the selectively executed predicated instruction is the predicated instruction that is a member of the conditional execution path specified by the resolving conditions.