Patent ID: 8488398

Claim:
A system comprising: a calibration module configured to apply a first voltage to a first word line, wherein a first transistor is arranged along (i) the first word line and (i) a first bit line, and wherein the first voltage is generated based on a first set of counts output by a counter at a first rate, latch a first count from the first set of counts in response to the first transistor turning on, wherein the first count represents a first threshold voltage of the first transistor, apply a second voltage to the first word line, wherein the second voltage is generated based on a second set of counts output by the counter at a second rate, wherein the second rate is different than the first rate, latch a second count from the second set of counts in response to the first transistor turning on, and generate a difference between the first count and the second count; and a read module configured to apply the second voltage generated based on the second set of counts to a second word line, wherein a second transistor is arranged along (i) the second word line and (ii) the first bit line, latch a third count from the second set of counts in response to the second transistor turning on, and adjust the third count based on the difference between the first count and the second count, wherein the adjusted third count represents a second threshold voltage of the second transistor, and determine a state of the second transistor based on the second threshold voltage.