Patent ID: 8324090

Claim:
A method of fabricating a semiconductor device comprising: providing a semiconductor substrate having a first region and a second region; forming a high-k dielectric layer over the semiconductor substrate; forming a first capping layer over the high-k dielectric layer, the first capping layer overlying the first region; forming a second capping layer over the high-k dielectric layer after forming the first capping layer, the second capping layer overlying the second region; forming a layer containing silicon (Si) over the first and second capping layers; forming a metal layer over the layer containing Si; and forming a first gate stack over the first region and a second gate stack over the second active region; wherein the first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer, wherein the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer, and wherein the forming the first capping layer includes: forming the first capping layer over the first and second regions; removing the first capping layer overlying the second region by a patterning and etching process; wherein the forming the second capping layer includes: forming the second capping layer over the first and second regions; and removing the second capping layer overlying the first region by a patterning and etching process.