Patent ID: 7098500

Claim:
A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise: a substrate having one surface with a first layer highly doped with a first conductivity dopant and forming a drain; a second layer over the first layer and lightly doped with a first conductivity dopant; a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component, and forming a PN junction with the second layer; a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant; a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions, said trench having spaced apart sidewalls and a floor with an insulating layer on the sidewalls and floor, upper and lower conductive layers separated by a dielectric layer, said upper and lower conducting layers having approximately the same width in their respective regions adjacent the dielectric layer separating them.