Patent ID: 8135935

Claim:
A method comprising: receiving a logical address, wherein the logical address maps to a first physical address of a memory and a second physical address of the memory, wherein the first physical address is configured to store data and the second physical address configured to store an error correction code (ECC) corresponding to the data stored at the first physical address; translating the logical address into the first and second physical addresses, wherein translating the logical address into first and second physical addresses comprises permuting bits of the logical address such that the ECC's are stored in physical memory locations adjacent to physical locations in the memory in which data protected by the ECC's is stored, wherein said permuting is performed based on a page boundary, wherein the ECC's are stored adjacent to the page boundary such that a single row address and two column addresses are provided to access a block of data and its corresponding ECC; accessing the data from the first physical address over a data path; separately accessing the ECC over the data path; and checking integrity of the data using the ECC.