Patent ID: 6938194

Claim:
A system for testing an integrated circuit, the integrated circuit including flip-flops connected to a logic block and the test system including: test means operable for connecting the flip-flops as a register, and a plurality of types of inhibition means, each type of inhibition means being operable for inhibiting one specific type of element of the logic block having a configuration that can disturb the sequencing of the register or the propagation of signals into the logic block, and control means having: a first operating mode for operating the test means in synchronism with a command signal while operating continuously the inhibition means; and a second operating mode for operating inhibition means of a first of the plurality of types of inhibition means in synchronism with the command signal while operating continuously inhibition means of a type different than the first type and the test means, or for operating simultaneously the test means and inhibition means of a first of the plurality of types of inhibition means in synchronism with the command signal while operating continuously inhibition means of a type different than the first type.