Patent ID: 7539022

Claim:
A chip embedded packaging structure comprising: a first metal board; a second metal board disposed on the upper surface of the first metal board, wherein the second metal board further comprises at least a through cavity and forms a heat dissipating substrate with the first metal board; at least a semiconductor chip and at least a capacitor chip embedded in the surface of the first metal board and embraced in the through cavity of the second metal board; a passive component layer disposed on part of the upper surface of the second metal board; and at least a build-up circuit layer disposed on the heat dissipating substrate and covering the semiconductor chip, the capacitor chip, and the passive component layer, wherein the build-up circuit layer further comprises: a dielectric layer; at least a circuit layer formed on the dielectric layer, wherein the circuit layer, the passive component layer, and the second metal board comprise a metal-insulator-metal (MIM) capacitor; and a plurality of conductive vias penetrating the dielectric layer for connecting the circuit layer and electrically connecting the build-up circuit layer and the capacitor chip, semiconductor chip, and the passive component layer.