Patent ID: 8723612

Claim:
A trimming circuit for a clock source, comprising: a plurality of switches, wherein each switch is controlled by a bit of a trimming signal; a plurality of trimming capacitors respectively connected in series with the plurality of switches, wherein the plurality of switches comprises, a first switch including a PMOS device connected in parallel with an NMOS device, wherein a least significant bit of the trimming signal is connected to the gates of the PMOS and NMOS devices, a second switch including two PMOS devices connected in parallel with each other, and two NMOS devices connected in parallel with each other, wherein the two PMOS devices are connected in parallel with the two NMOS devices, and wherein a second bit of the trimming signal is connected to the gates of the two PMOS devices and the two NMOS devices; and a third switch including two NMOS devices connected in parallel with each other, and four PMOS devices connected in parallel with each, wherein the two NMOS devices are connected in parallel with the four PMOS devices, wherein a third bit of the trimming signal is connected to the gates of the two NMOS devices and the four PMOS devices.