Patent ID: 7414555

Claim:
A sample/hold circuit for an analog to digital converter (ADC), the sample/hold circuit comprising: an amplifier having positive and negative input terminals; first, second, third, and fourth capacitors, each capacitor having first and second terminals; a first switch set for selectively connecting the first terminals of the first, second, third, and fourth capacitors to I p , I n , Q p , and Q n input terminals, respectively, of the ADC; a second switch set, the second terminal of the first capacitor being selectively connected to the positive input terminal of the amplifier using a first switch of the second switch set, and the second terminal of the second capacitor being selectively connected to the negative input terminal of the amplifier using a second switch of the second switch set; a third switch set, the second terminal of the third capacitor being selectively connected to the positive input terminal of the amplifier using a first switch of the third switch set, and the second terminal of the fourth capacitor being selectively connected to the positive input terminal of the amplifier using a second switch of the third switch set; first and second feedback lines, the first feedback line being connected to a positive output line of the amplifier, the second feedback line being connected to a negative output line of the amplifier, the first terminal of the first capacitor being selectively connected to the first feedback line using a third switch of the second switch set, the first terminal of the second capacitor being selectively connected to the second feedback line by a fourth switch of the second switch set, the first terminal of the third capacitor being selectively connected to the first feedback line using a third switch of the third switch set, the first terminal of the fourth capacitor being selectively connected to the first feedback line by a fourth switch of the third switch set; and a fourth switch set for selectively connecting the second terminals of the first, second, third, and fourth capacitors to a predetermined voltage.