Patent ID: 7732864

Claim:
A semiconductor device comprising: a first circuit block including a plurality of first transistors, each of the plurality of first transistors having a first semiconductor layer formed on a semiconductor substrate via a first embedded oxide film; a first source region and a first drain region formed in the first semiconductor layer and having the same thickness as that of the first semiconductor layer; a first channel region formed between the first source region and the first drain region and formed in the first semiconductor region, the first channel region being a full depletion region; a first gate formed on a first main surface of the first channel region via a first gate insulating film; a second gate formed of a conductive layer formed in contact with a bottom surface of the first embedded oxide film and electrically connected with the first gate; and a first insulating separating layer formed on the semiconductor substrate so as to surround the first semiconductor layer; and a second circuit block including a plurality of second transistors, each of the plurality of second transistors having a second semiconductor layer formed on the semiconductor substrate via a second embedded oxide film; a second source region and a second drain region formed in the second semiconductor layer and having the same thickness as that of the second semiconductor layer; a second channel region formed between the second source region and the second drain region and formed in the second semiconductor region, the second channel region being a full depletion region; a third gate formed on a first main surface of the second channel region via a second gate insulating film; a fourth gate formed of a conductive layer formed in contact with a bottom surface of the second embedded oxide film; and a second insulating separating layer formed on the semiconductor substrate so as to surround the second semiconductor layer, wherein an output signal of the first circuit block is input to the fourth gates of the plurality of the second transistors, and wherein an input signal to the third gate of each second transistor is independent of the input signal into the fourth gate of that same second transistor.