Patent ID: 7831878

Claim:
An integrated circuit, comprising: A. a substrate; B. a first die carried on the substrate, the first die including: i. a first test access port interface having first leads that include a test data in input, a test clock input, a test mode select input, a test reset input, and a test data out output, ii. an off chip tap port interface having second leads that include a test data in output, a test clock output, a test mode select output, a test reset output, and a test data out input, and iii. linking module circuitry including controller circuitry connected with the first leads and having control output leads, and multiplexer circuitry having control inputs connected with the control output leads, interface inputs coupled with the first leads and interface outputs coupled with the second leads, the multiplexer circuitry selectively coupling the second leads with the first leads; and C. a second die carried on the substrate, the second die including a second test access port interface having leads that include a test data in input, a test clock input, a test mode select input, a test reset input, and a test data out output that are connected with the second leads.