Patent ID: 7994580

Claim:
A high voltage semiconductor device comprising: an active region in a semiconductor substrate having a planar top surface, wherein the active region is bounded by an isolation region; a gate electrode over the active region having opposing sidewalls; a first dielectric layer over the sidewalls of the gate electrode, the first dielectric layer having upper portions overlying the sidewalls of the gate electrode and lower portions adjacent a bottom of the gate electrode, the lower portions of the first dielectric layer extending away from the bottom of the gate electrode and extending parallel to the planar top surface of the substrate; an etch stop layer formed over the first dielectric layer over the sidewalls of the gate electrode, the etch stop layer having upper portions overlying the upper portions of the first dielectric layer and having lower portions adjacent the bottom of the gate electrode and the lower portions of the etch stop layer extending away from the bottom of the gate electrode and extending parallel to the planar top surface of the substrate; a pair of spacers formed over the etch stop layer; a first doped region within the active region and having a first depth, wherein the first doped region comprises a portion underlying one of the spacers and a portion adjacent the one of the spacers; and a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and having a second depth less than the first depth, wherein the second doped region is spaced apart from the one of the spacers by a distance; wherein the lower portions of the first dielectric and the lower portions of the etch stop layer extending away from the bottom of the gate electrode and extending parallel to the planar top surface of the substrate are further extending over an entire region corresponding to the distance wherein the second doped region is spaced apart from the one of the spacers.