Patent ID: 7870306

Claim:
An apparatus comprising: a message switch module to pass message headers, the message switch module further to receive a memory read request from a requesting agent coupled to the message switch module, identify if there is a pointer in the pointer memory corresponding to an address associated with the memory read request, and based on a determination there is a corresponding pointer, send a memory read response to the requesting agent; a cache controller module coupled to and associated with the message switch module; an arbitration logic module coupled to and associated with the message switch module and the cache controller module; and a single integrated shared switch memory and cache memory integrated with the message switch module to provide shared memory to both the message switch module and to the cache controller module, the single integrated shared switch memory and cache memory being accessible to the cache controller module through the arbitration logic module, the single integrated shared switch memory and cache memory configured to send requested data to the requesting agent without requiring the cache controller module to write the requested data to the message switch module, the cache controller module further comprising the pointer memory to store a plurality of pointers, at least one of the plurality of pointers being configured to point to a location in the shared switch memory and cache memory.