Patent ID: 7330522

Claim:
A process of sequentially decoding complementary code keying (CCK) codes, applicable in CCK code correlation in a wireless network, the process comprising: receiving and saving a first input signal in a first signal register (Xo) and then the first signal multiplying with one selected from 1, −1, j or −j according to the first set of CCK codes of No. 0 chip (C 0 — 1 ), this product being saved in the first operation register (R 0 ); receiving and saving a second input signal in a second signal register (X 1 ) and then the second signal multiplying with one selected from 1, −1, j or −j according to a first set of CCK codes of No. 1 chip (C 1 — 1 ), this product and the value of the first operation register (R 0 ) adding up to save in a second operation register (R 1 ); receiving and saving a third input signal in a third signal register (X 2 ), and then the third signal multiplying with 1, −1, j or j according to a first set of CCK codes of No. 2 chip (C 2 — 1 ), this product and the value of the second operation register (R 1 ) adding up to save in a third operation register (R 2 ); receiving and saving a fourth input signal in a fourth signal register (X 3 ), and then the fourth signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 3 chip (C 3 — 1 ), this product and the value of the third operation register (R 2 ) adding up to save in a fourth operation register (R 3 ); receiving and saving a fifth input signal in a fifth signal register (X 4 ), and then the fifth input signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 4 chip (C 4 — 1 ), this product and the value of the fourth operation register (R 3 ) adding up to save in a fifth operation register (R 4 ) receiving and saving a sixth input signal in a sixth signal register (X 5 ), and then the sixth input signal multiplying with 1, −1, j or j according to a first set of CCK codes of No. 5 chip (C 5 — 1 ), this product and the value of the fifth operation register (R 4 ) adding up to save in a sixth operation register (R 5 ); receiving and saving a seventh input signal in a seventh signal register (X 6 ), and then the seventh input signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 6 chip (C 6 — 1 ), this product and the value of the sixth operation register (R 5 ) adding up to save in a seventh operation register (R 6 ); and receiving and saving an eighth input signal in an eighth signal register(X 7 ), and then the eighth input signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 7 chip(C 7 — 1 ), this product and the value saved in the seventh operation register(R 6 ) adding up to save in an eighth operation register (R 7 ).