Patent ID: 8004050

Claim:
A semiconductor device comprising: a gate electrode having a laminated structure of a polycrystalline silicon film containing arsenic and phosphorous or a polycrystalline germanium film containing arsenic and phosphorous and a first silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film; a sidewall insulating film formed on a side surface of the gate electrode; source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode; and second silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is lower than a peak concentration of arsenic contained in the source/drain layers, the peak concentration of arsenic contained in the gate electrode is more than 1E19 cm−3, and the peak concentration of arsenic contained in the source/drain layers is more than 1E20 cm−3.