Patent ID: 8205180

Claim:
A method of placing a circuit design in circuit blocks of an integrated circuit, the method comprising: receiving a circuit design to be implemented in the circuit blocks and memory elements of the integrated circuit, the circuit design receiving data and a clock signal; determining clock skew for a clock tree providing the clock signal to the memory elements of the integrated circuit by determining a first delay of the clock signal to a first memory element and a second delay of the clock signal to a second memory element; evaluating delay associated with data routed between the memory elements of the circuit design; and transforming, by using a computer, the circuit design to a placement configuration by selecting portions of the circuit design to be placed between the first memory element and the second memory element, wherein the placement configuration places the circuit design in the circuit blocks of the integrated circuit according to the delay associated with data routed in a selected combinational path of one or more combinational paths between the memory elements of the circuit design and the first delay of the clock signal to the first memory element and the second delay of the clock signal to the second memory element.