Patent ID: 7538023

Claim:
A method of manufacturing a semiconductor wafer device, comprising the steps of: (a) forming first lower wiring patterns over a semiconductor wafer having semiconductor elements formed in a circuit area and forming second lower wiring patterns in a wafer peripheral area, the first lower wiring patterns being connected to the semiconductor elements; (b) forming an interlevel insulating film over the semiconductor wafer, the interlevel insulating film covering the first lower wiring patterns and the second lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the first lower wiring patterns, wiring patterns disposed on the via conductors in the circuit area and conductor patterns made of a same material as the wiring patterns in the wafer peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the intertevel insulating film, the conductive patterns being electrically isolated from the second wiring patterns.