Patent ID: 6979593

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor wafer having a plurality of areas respectively formed with integrated circuits, spaced from each other by dicing areas, and arranged orderly in a matrix on a main surface thereof, and a wiring substrate with a plurality of mounting areas arranged orderly on a main surface thereof, having wiring lines formed on the main surface and on a backside surface of the wiring substrate at each of the mounting areas, the wiring lines on the main surface and on the back side surface of the wiring substrate being interconnected by conductors penetrating the wiring substrate; affixing a protective tape so as to cover an entire area of the main surface of the semiconductor wafer; removing the back side of the semiconductor wafer by a predetermined thickness while the entire area of the main surface of the semiconductor wafer is covered with the protective tape; affixing a dicing tape to the back side of the semiconductor wafer exposed by the removing step; while the main surface of the semiconductor wafer is covered with the protective tape, cutting the semiconductor wafer along said dicing areas from the main surface of the semiconductor wafer to a halfway depth of the dicing tape by means of a dicing blade to divide the semiconductor wafer into a plurality of individual semiconductor chips; picking up the semiconductor chips on the dicing tape one by one and fixing the semiconductor chips to the mounting areas of said wiring substrate, respectively; removing the protective tape from each of the semiconductor chips affixed to the wiring substrate; connecting electrodes formed on the semiconductor chip at each of the mounting areas of said wiring substrate with the associated wiring lines formed on the main surface of the wiring substrate, by electrically conductive wires; forming an insulating encapsulation material layer on the main surface of the wiring substrate so as to cover the semiconductor chips and the wires; affixing a support member to the combination of the semiconductor chips and the wiring substrate through a main surface of the insulating encapsulation material layer; forming salient or bump electrodes on wiring lines formed on the back side surface of the wiring substrate while said combination is supported by the support member; dicing the combination along boundaries between the mounting areas of said wiring substrate from the wiring substrate to a halfway depth of the support member through the insulating encapsulation material layer by means of a dicing blade; and separating each of semiconductor devices having said individual semiconductor chips and said wiring substrate from the support member.