Patent ID: 7173862

Claim:
A sub-block erase method of a non-volatile semiconductor memory device including a matrix of rows and columns of memory cells organized into more than one cell array block, each said memory cell has a charge storage layer, said method being for erasing more than one partial memory cell of said cell array block, said method comprising: performing sub-block erase by giving a voltage to said partial memory cell; performing sub-block erase verify read to check whether said memory cell is set in the erase state; performing over-program verify read to check whether an memory cell having its threshold voltage higher than a read voltage; determining the erase is inexecutable to thereby terminate the processing when an over-programmed memory cell is found to be present by said over-program verify read; counting a number of cell units, each comprising a plurality of said memory cells queued in a column direction, each being determined by said over-program verify read to include therein an over-programmed memory cell; and continuing the processing without rendering the erase inexecutable when the number as counted at this step is less than or equal to an error correctable number.