Patent ID: 7960230

Claim:
A method of manufacturing a semiconductor device, comprising: forming a plurality of floating gate electrodes, which have an upper portion which is narrower in a channel width direction than a lower portion, on a tunnel insulating film formed on a semiconductor substrate; filling a gap between side surfaces of the floating gate electrodes opposing each other with an element isolation insulating film; removing part of the element isolation insulating film to partially expose the side surfaces of the floating gate electrodes; forming an interelectrode insulating film on the floating gate electrodes and forming part of the interelectrode insulating film on the exposed side surfaces of the floating gate electrodes; and forming a control gate electrode on the floating gate electrodes, the control gate electrode being partially buried between the floating gate electrodes opposing each other, wherein at least a part of a sidewall of the lower portion of each of the floating gate electrodes is in direct contact with a left or right sidewall of the element isolation insulating film, and a width, in the channel width direction, of the upper portion of the floating gate electrode is smaller than a width, in the channel width direction, of a portion of the floating gate electrode where the floating gate electrode is in contact with the tunnel insulating film.