Patent ID: 8412902

Claim:
A signal processor comprising: a plurality of storage sections; a start address input section to which a start address is input from an external controller, the start address indicating an address for starting output of data from an external memory that stores a set of data to be downloaded to the plurality of storage sections; a signal output section adapted to output a start signal based on a download start instruction input from the external controller, and to output an end signal when download has been completed of data to be downloaded to at least one storage section designated by the external controller; an output instruction section that: (A) when the start signal is input thereto, is adapted to output to the external memory a data output instruction to output data corresponding to bytes of the data to be downloaded to the at least one designated storage section, starting from the start address, and (B) when the end signal is input thereto, is adapted to stop output of the data output instruction; and a write instruction section that is adapted to receive input of the at least one designated storage section from the external controller, and, based upon the input, output a write instruction to the plurality of storage sections which prohibits writing of data to the plurality of storage sections other than the at least one designated storage section, and causes the data to be downloaded to be written only to the at least one designated storage section when the start signal is input to the output instruction section.