Patent ID: 8223529

Claim:
A resistive memory device comprising: a resistive memory cell array including a plurality of resistive memory cells, respective ones of which are coupled to a corresponding bitline; an output circuit configured to generate a sensing output signal during a write operation by sensing a bitline voltage, and configured to generate output data during a read operation by sensing the bitline voltage; and an input circuit configured to control the bitline voltage based on input data for the write operation, and configured to receive the sensing output signal directly from the output circuit to limit the bitline voltage in response to the sensing output signal during the write operation, wherein the input circuit is configured to limit a maximum voltage and/or a maximum time of a particular set pulse and/or reset pulse of the bitline voltage in response to the sensing output signal during the write operation; the resistive memory device further comprising a sensing reference voltage generator configured to generate a sensing reference voltage that is compared with the bitline voltage by the output circuit to generate the sensing output signal, wherein the sensing reference voltage generator is configured to adjust the sensing reference voltage in response to a location compensation control signal for compensating deviations due to respective locations of the resistive memory cells.