Patent ID: 8301821

Claim:
A system, comprising: an adapter circuit including a customer interface having a first buffer memory, a gateway interface having a second buffer memory, a first generic interface, and an arbiter finite state machine prioritizing and arbitrating data transmission over the customer and gateway interfaces; and a communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module, including: a second generic interface coupled to the first generic interface of the adapter circuit; a communication protocol unit connected to the serial bus for converting between data packets and messages, which are respectively made up of a plurality of data words; and a message relaying unit coupled to the second generic interface for signaling a master unit of at least one system bus through the second generic interface and the adapter circuit that a message has been received at the communication protocol unit and routing the received message to the second generic interface and the adapter circuit connected to a system bus transmitting a request for the received message; wherein data words are transmitted simultaneously from and to the buffer memories of the customer and gateway interfaces and each interface includes an associated device-independent system bus master.