Patent ID: 7095266

Claim:
A symmetric DC switch comprising: a first field effect transistor (FET) having gate, source, drain and well contacts, wherein the source or the drain contact receives an input signal, an output signal substantially equal to the input signal is presented to the respective drain or source contact when the FET is on, a second FET arranged, when on, to connect the source to the well of the first FET, a third FET arranged, when on, to connect the drain to the well of the first FET, wherein the first second and third FET's are all on and off together, wherein the input signal appears at the source, drain and well of the first FET when the FET's are on, and a switch arranged between the well of the first FET and a potential, wherein the well is connected to the potential when the first FET is off, and a resistor arranged between an enable signal and the gate of the first FET, the enable signal, when true, turning on the first, second and third FET's and, when false, turning them off, wherein the bandwidth of the first FET, when on, is increased and the insertion loss reduced.