Patent ID: 7962906

Claim:
A computer implemented method for a compiler to compile a single source program to employ multiple ancillary SIMD accelerators, the computer implemented method comprising: receiving, by the compiler, the single source program; identifying vectorizable loop code in the single source program; extracting the vectorizable loop code from the single source program to form extracted vectorizable loop code; compiling the extracted vectorizable loop code using an SIMD instruction set to form executable vectorized instruction sequences to be executed by the multiple ancillary SIMD accelerators; replacing the extracted vectorizable loop code in the single source program with calls to runtime library code to form a main program, wherein the runtime library code is configured to cause the executable vectorized instruction sequences to be executed at runtime, and wherein the runtime library code is inserted at a location that included the extracted vectorizable loop; compiling the main program for a principal processor using an instruction set of a processor using an instruction set of a processor that executes code sequentially to form an executable main program that includes only sequential code that is to be executed by the processor, wherein the executable main program controls operation of the executable vectorized instruction sequences on the multiple ancillary SIMD accelerators; inserting data management code in the executable vectorized instruction sequences, wherein the data management code accesses vector data for a given one of the multiple ancillary SIMD accelerators; the data management code is configured to allow each one of the multiple ancillary SIMD accelerators to perform computation on vector data with non-stride-1 array accesses; and forming a completed program by placing the executable vectorized instruction sequences into the executable main program.