Patent ID: 7356551

Claim:
An apparatus for retaining maximum speed of a flip-flop metastability based random number generator, comprising: a fixed delay unit having an input for receiving a common signal from a digital signal generator, said fixed delay unit providing a fixed period of delay to the signal as an output; a variable delay unit having an input for receiving the common signal from the digital signal generator, said variable delay unit being tunable to provide a variable delay to the common signal as an output; a pair of NAND gates each of which has a first input that receives a respective output of one of fixed delay unit and variable delay unit; an output of a first NAND gate is input to a second NAND gate of the pair of NAND gates, and an output of the second NAND gate is input to the first NAND gate of the pair of gates; a frequency measurement and delay tuning module that receives an output of a first NAND gate of the pair of NAND gates, said module checks the frequency of random number bit generation and updates the variable delay unit according to predetermined criteria to tune the variable delay unit so as to maximize the speed of the random bit generation.