Patent ID: 7293211

Claim:
A semiconductor integrated circuit comprising: a first and a second input/output (I/O) terminal; a first scan-path comprising a plurality of flip-flops with scan function connected in a cascading manner for testing a combination circuit; a second scan-path which is independent from the first scan-path comprising a plurality of flip-flops with scan function connected in a cascading manner for testing a combination circuit; a first switching circuit connecting the first I/O terminal to the combination circuit when a normal operation mode is set, for connecting the first I/O terminal to an input of the first scan-path when test-data is applied to the combination circuit, for connecting the first I/O terminal to an output of the second scan-path when reading out test data from the combination circuit; and a second switching circuit connecting the second I/O terminal to the combination circuit when the normal operation mode is set, for connecting the second I/O terminal to the input of the second scan-path when test-data is applied to the combination circuit, for connecting the second I/O terminal to the output of the first scan-path when reading out test data from the combination circuit.