Patent ID: 6881629

Claim:
A method to form MOS gates in an integrated circuit device comprising: providing a substrate; forming a dielectric layer overlying said substrate; forming a conductor layer overlying said dielectric layer; depositing a first masking layer overlying said conductor layer; patterning said first masking layer to selectively expose said conductor layer; depositing a second masking layer overlying said first masking layer and said conductor layer; etching back said second masking layer to form spacers on sidewalls of said first masking layer; etching through said conductor layer where exposed by said first masking layer and said spacers to thereby form MOS gates in the manufacture of said integrated circuit device; removing said first masking layer and said spacers; etching said MOS gates to selectively expose said substrate; forming a second dielectric layer overlying said MOS gates and said substrate; deposing a second conductor layer overlying said second dielectric layer; and etching back said second conductor layer to form second MOS gates on sidewalls of said MOS gates.