Patent ID: 7445999

Claim:
A method of fabricating a flash memory cell, comprising the steps of: providing a first conductive type substrate having a second conductive type well and a plurality of device isolation structures formed thereon, wherein the device isolation structures are disposed within the second conductive type well to define an active region on the first conductive type substrate; forming a first conductive type doped region on the second conductive type well within the active region; forming a patterned film layer over the first conductive type substrate, wherein the patterned film layer has a plurality of openings that exposes a portion of the first conductive type doped region within the active region; forming a second conductive type doped region in the first conductive type substrate using the patterned film layer as a mask so that the second conductive doped region cuts off the first conductive type doped region; forming a tunneling dielectric layer over the second conductive type doped region within the openings; forming a plurality of floating gates inside the openings; removing a portion of the patterned film layer so that the patterned film layer has a thickness smaller than that of the floating gate; forming an inter-gate dielectric layer over the first conductive type substrate to cover the floating gates and the patterned film layer; and forming a plurality of control gates over the inter-gate dielectric layer with each control gate stacked on top of each of the floating gates respectively.