Patent ID: 8018541

Claim:
An array substrate for an in-plane switching mode liquid crystal display device, comprising: first and second gate lines on a substrate including first and second pixel regions; a first common connection pattern in an upper side of each of the first and second pixel regions; first and second outmost common electrodes extending from ends of the first common connection pattern; a gate insulating layer on the first and second gate lines, the first common connection pattern and the first and second outmost common electrodes; first and second data lines on the gate insulating layer and crossing the first and second gate lines to define the first and second pixel regions, the first and second pixel regions being adjacent to each other along a direction of the first and second data lines; a thin film transistor in the first pixel region and connected to the first gate line and the first data line, the thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode, the drain electrode extending to overlap the first outmost common electrode; a passivation layer on the first and second data lines and the thin film transistor and including a drain contact hole exposing a portion of the drain electrode and a first common contact hole exposing a portion of the second outmost common electrode; a plurality of pixel electrodes on the passivation layer and spaced apart from each other; a pixel connection pattern on the passivation layer and connecting one end of the pixel electrodes, the pixel connection pattern connected to the drain electrode through the drain contact hole, the pixel connection pattern overlapping the first and second outmost common electrodes and first and second portions of the first common connection pattern; a plurality of common electrodes on the passivation layer and alternately arranged with the pixel electrodes; and a second common connection pattern at a lower side of the pixel regions and on the passivation layer, the second common connection pattern connected to the second outmost common electrode through the first common contact hole and connecting one end of the common electrodes.