Patent ID: 7234123

Claim:
A process for designing an integrated circuit having desired functionality, the process comprising: defining a plurality of sub-circuits, each subcircuit comprising fewer than 5000 gates, including at least one of data path sub-circuits, control path sub-circuits, memory sub-circuits, and input/output sub-circuits, each sub-circuit performing at least one electronic function, each sub-circuit having a defined physical arrangement of transistors and interconnections among the transistors on a set of layers of the sub-circuit, as well as defined interconnection points for interconnection to other sub-circuits, the resulting sub-circuit having fixed dimensions and being characterized by an implementation file; partitioning the desired functionality of the integrated circuit being designed into sub-circuits, selecting appropriate ones of the sub-circuits, including at least one of data path sub-circuits, control path sub-circuits, memory sub-circuits, and input/output sub-circuits, to thereby provide a set of sub-circuits to implement the desired functionality for the integrated circuit being designed; testing a functional model of the set of sub-circuits to verify correctness of the set of sub-circuits to implement the desired functionality for the integrated circuit being designed; performing timing, area, and power estimation on the integrated circuit being designed using physical models of the sub-circuits; importing the implementation files for the set of sub-circuits into a design for the integrated circuit without changing the fixed dimensions of the sub-circuits; and interconnecting the sub-circuits to each other using layers of the integrated circuit being designed other than the set of layers used for the interconnections within individual sub-circuits.