Patent ID: 8141098

Claim:
An apparatus, comprising: a hardware prefetcher; and processor logic coupled to the hardware prefetcher and configured to perform a context switch operation in a multithreaded computer by initiating a prefetch of data likely to be used by a thread prior to resuming execution of the thread, wherein the data for which the prefetch is initiated is determined using state information stored during a prior context switch from the thread, wherein the processor logic is configured to initiate the prefetch further by retrieving the state information stored during the prior context switch from the thread, wherein the state information includes hardware prefetcher state information, wherein the processor logic is configured to initiate the prefetch further by initializing the hardware prefetcher using the hardware prefetcher state information, wherein the hardware prefetcher state information includes a base address value, wherein the hardware prefetcher state information further includes a stride value, and wherein the processor logic is configured to initialize the hardware prefetcher by initializing the hardware prefetcher to prefetch starting at an address calculated by subtracting at least one of the stride value and a multiple of the stride value from the base address, wherein the processor logic is configured to initialize the hardware prefetcher further by initializing the hardware prefetcher to repeat at least one prefetch operation performed prior to the prior context switch from the thread, wherein the state information identifies at least one cache line accessed prior to the prior context switch from the thread, and wherein the processor logic is configured to initiate the prefetch further by initiating prefetching of the cache line identified by the state information.