Patent ID: 8143932

Claim:
A clock distribution network, comprising: a plurality of clock drivers for outputting clock signals, at least two of the plurality of clock drivers having unequal driving capacities; and a grid distribution network functionally coupled to a chip region for distributing the clock signals output from the plurality of clock drivers, the chip region defined by n sides, where n≧3, the sides intersecting at n vertices, wherein the plurality of clock drivers are arranged along one side of the chip region such that a first clock driver having a first driving capacity C 1 is located a first minimum distance D 1 from the n vertices and a second clock driver having a second driving capacity C 2 is located a second minimum distance D 2 from the n vertices, and wherein the expressions D 2 >D 1 and C 2 >C 1 are both satisfied, further wherein the driving capacity of each clock driver is proportional to a separation distance D by which each clock driver is separated from the closest one of the n vertices.