Patent ID: 7064453

Claim:
A semiconductor memory device, comprising: a first driver transistor having a gate and a drain; a second driver transistor including: a drain connected to the gate of the first driver transistor; and a gate connected to the drain of the first driver transistor; a first load transistor connected in series to the first driver transistor, the gate of the first load transistor being an extension of the gate of the first driver transistor; a second load transistor connected in series to the second driver transistor, the gate of the second load transistor being an extension of the gate of the second driver transistor; a first transfer gate including: a source connected to the drain of the first driver transistor, a drain connected to a first bit line; and a gate connected to a word line; a second transfer gate including: a source connected to the drain of the second driver transistor; a drain connected to a second bit line; and a gate connected to the word line; a read-out transistor connected in series to the second load transistor, the gate of the read-out transistor being a bended extension of the gate of the second load transistor, the gate of the second load transistor being L-shaped; and a recess provided in an inner corner of the gate of the second driver transistor, the second load transistor and the read-out transistor.