Patent ID: 7705649

Claim:
A duty cycle correction circuit ( 10 ) for receiving an input clock signal ( 11 ) and generating an output clock signal ( 13 ) having a predetermined duty cycle, comprising: a clock trigger circuit ( 12 ) receiving the input clock signal and a delayed clock signal ( 22 ), the clock trigger circuit generating the output clock signal ( 13 ) having a first clock edge triggered from a first clock edge of the input clock signal and a second clock edge triggered from a first clock edge of the delayed clock signal; a charge pump circuit ( 14 ) receiving the output clock signal as input signal and generating a charging current and a discharging current at an output node ( 15 ) for charging and discharging a capacitor (C 1 ), a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit ( 18 ) receiving the control voltage and generating first and second bias voltages ( 23 , 24 ) in response to the control voltage; and a delay-locked loop circuit ( 20 ) receiving the output clock signal and the first and second bias voltages, the delay-locked loop circuit generating the delayed clock signal having a first delay from the output clock signal, the first delay being corresponding to the first and second bias voltages, the delay-locked loop circuit comprising a plurality of delay cells connected in series, each of the delay cells ( 32 ) being biased by the first and second bias voltages to generate a second delay, wherein the self-track bias circuit generates the first and second bias voltages using circuitry matching that of the delay cell of the delay-locked loop, the first and second bias voltages providing compensation for temperature and process variations of the delay cell.