Patent ID: 7558934

Claim:
A data storage apparatus comprising: a memory including a plurality of addressable memory banks; a data storage control unit sequentially storing input data among the memory banks; an input for an access pattern representing a pattern of stored data to be read simultaneously from said memory; a judging means judging whether the input data are to be stored at memory locations corresponding to the access pattern; and a memory controlling means storing said input data in different memory banks at the locations corresponding to the access pattern, said memory controlling means incrementing the memory bank address to skip a memory bank for said input data when it is judged that said input data are to be stored at the locations corresponding to the access pattern and will be read simultaneously, said memory controlling means storing said input data at the locations in the memory bank whose bank address is incremented and that correspond to said access pattern, said memory controlling means including relocating means that (a) reads the data from said memory simultaneously from a plurality of first addresses represented by the access pattern, (b) restores, by incrementing the bank address, said read data at second addresses where the read data have not been stored, and (c) re-stores said read data at said second addresses, wherein the data is pixel data and wherein the memory controlling means includes relocating means relocating data stored in a previous storage location to a destination storage location, a storage location has an address B,I,J represented by a bank address b, a word line address i, and a bit line address j in which B=(d+b−1) mod n I=i J=j where d is a pixel interval from a previous storage location to a destination storage location for given pixel data and n is the number of memory banks; and the memory controlling means re-stores the data at each storage location in each memory bank to a respective destination storage location represented by a destination address B,I,J, where B is the destination bank address, I is the destination word line address, and J is the destination bit line address, in which the destination bit line address J is J=j−1 when B−b>0 and the destination word line I is I=i−1 when the bit line address sequences to a final bit line address and the destination word line address I is I=i when the bit line address is not the final bit line address.