Patent ID: 7877542

Claim:
A single-chip non-volatile memory device (NVMD) comprising: a high-speed internal bus with a plurality of components coupled thereupon; the components includes: an advanced input/output interface logic configured to facilitate data and control signals, to and from a host computer system via a host bus; a central processing unit (CPU) configured to manage one or more data transfer operations between the host computer system and the single-chip NVMD; at least one non-volatile memory (NVM), each including a page register configured to conduct one or more data exchanges with a plurality of parallel data buffers, and a reserved area of the at least non-volatile memory is configured to store N sets of partial logical-to-physical address and page usage information (PLTPPUI), where N is a positive integer, wherein each of the data changes is managed by the CPU through a scheme based on source synchronous interface, data interleaving and block abstracted addressing; a block address manager configured to ensure a physical address of the at least one NVM is converted to a transformed address accessible by the CPU; and an address correlation and page usage memory (ACPUM) configured to hold one set of the N sets of PLTPPUI such that said one set is pertinent to a particular one of the data transfer operations between the CPU and the at least one NVM.