Patent ID: 7205802

Claim:
A delay circuit comprising: a first inverter comprising a first PMOS transistor and a first NMOS transistor; a plurality of second PMOS transistors connected in parallel to each other and to the first PMOS transistor; a plurality of second NMOS transistors connected in parallel to each other and to the first NMOS transistor; a decoder for controlling a plurality of transistor pairs, each transistor pair in the plurality of transistor pairs comprising one of the plurality of second PMOS transistors, each transistor pair in the plurality of transistor pairs comprising one of the plurality of second NMOS transistors wherein each of the plurality of transistor pairs provides a delay to the first inverter, wherein the decoder comprises an input for receiving control signals, wherein when a signal is passing through the delay circuit the decoder ignores any changes to the input, when the signal is not passing through the delay circuit, the decoder passes though any changes to at least one transistor pair of the plurality of transistor pairs.