Patent ID: 6990646

Claim:
A hold time error correction method for integrated circuits, comprising: generating, for an integrated circuit layout, a hold time error list that includes hold time error paths causing hold time errors which exist under a plurality of timing constraints, and a hold time error value for each hold time error path which satisfies said plurality of timing constraints as a result of correction; detecting a setup time margin for said plurality of timing constraints, and generating a setup time margin list having setup time errors paths with the possibility of causing setup time errors as a result of correction of said hold time errors, and a setup time margin for each setup time error path which is common for said plurality of timing constraints; generating a setup time margin map, in which the setup time margin of said setup time margin list is allocated to each path of said integrated circuit; and inserting a delay buffer, which, while referencing said setup time margin map, corrects the hold time error values of said hold time error list, within the range of a delay amount and position which satisfy said allocated setup time margin.