Patent ID: 8705297

Claim:
A semiconductor memory device comprising: a plurality of memory cell blocks, each of the plurality of memory cell blocks having a first region including first memory cells connected to a first bit line, and a second region including second memory cells connected to a second bit line; a plurality of bit line sense amplifiers, each of the plurality of bit line sense amplifiers being connected to the first or second memory cells of a corresponding memory cell block from among the plurality of memory cell blocks; and a plurality of connection units, each of the plurality of connection units being configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal, wherein the first region and the second region of each of the plurality of memory cell blocks cross each other in a first direction, and the first region and second region of each of the plurality of memory cell blocks are arranged adjacent to each other in a second direction.