Patent ID: 7456098

Claim:
A method of designing an integrated circuit (IC) chip comprising: designing the chip with a base substrate, a plurality of stacked layers of conductive metallurgy and low-k dielectric material fabricated over the substrate, with the conductive metallurgy including active electrical lines, and the conductive metallurgy in different layers being connected by conductive metallurgy vias, and being capped by a top oxide cap; incorporating in the design of the chip a plurality of stacked via pillars positioned at spaced locations in the chip, wherein the plurality of stacked via pillars extend completely from the base substrate of the chip to the top oxide cap of the chip, and at least a portion of the plurality of stacked via pillars are not electrically connected to any of the active electrical lines or vias, wherein the plurality of stacked via pillars support the chip structure to accommodate radial deformations during any thermal and/or mechanical stresses, and said stacked via pillars are fabricated of a high modulus, low coefficient of thermal expansion material selected from SiO 2 and SiN, which is different from the conductive material forming the conductive metallurgy vias in the chip.