Patent ID: 8289802

Claim:
A processor-based system, comprising: a volatile memory operable to store data; a processor coupled to the memory through address, data and control busses and operable to process data; at least one input device coupled to the processor; and a data storage coupled to the processor and operable to store data, the data storage including a flash memory receiving control signals, and command and address signals, the flash memory comprising: an array of flash memory cells having a plurality of memory planes, each memory plane being controlled by a control circuit; a plurality of array drivers, wherein each of the array drivers is associated with a respective one of the plurality of memory planes, and is operable to receive a respective one of a plurality of enable signals and a common control signal, each of the array drivers further operable to initiate a memory operation in at least one memory plane responsive to receipt of the common control signal and the respective enable signal; control logic coupled to the plurality of arrays drivers, the control logic comprising control circuit enable logic operable to generate the respective enable signals for the plurality of memory plane control circuits to initiate the memory operation in at least one memory plane in synchronicity with the periodically repeating control signals; and array driver logic coupled to the control logic, wherein the array drive logic is configured to couple at least one of the respective enable signals to a corresponding array driver to initiate the memory operation in at least one memory plane during a memory operation in another one of the memory planes.