Patent ID: 7643355

Claim:
A semiconductor memory device, comprising: a memory core; an input circuit configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods, and configured to provide the second data to the memory core, the second data having 2N times a number of bits of the first data, where N is a positive integer; and an output circuit configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods, and configured to provide the fourth data to data output pins, the fourth data having ½N times a number of bits of the third data, wherein the input circuit includes: an input buffer configured to generate the first data by sampling serial input data in response to a write DQS signal and converting the sampled serial data to parallel data; a data converter configured to generate the second data based on the first data using the latch circuits operating in response to the input control signals; and an input drive circuit configured to drive the memory core in response to the second data.