Patent ID: 7576677

Claim:
A pipeline A/D converter converting an analog signal to a digital signal, comprising: first to Nth stages that are cascaded, where N is an integer not smaller than 2; and an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, said first sub DAC being configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, said first stage further including an overflow detection circuit outputting an overflow detection signal in response to the level of said analog signal exceeding said predetermined input voltage range, said overflow detection circuit including a voltage-division circuit dividing a first voltage to generate a plurality of second voltages, and a comparator comparing a first level corresponding to said analog signal with a second level corresponding to a sum of said first voltage and said second voltage and outputting said overflow detection signal in response to said first level exceeding said second level, and said first sub DAC outputs the sub analog signal at a prescribed level within said predetermined output voltage range, in response to said overflow detection signal.