Patent ID: 7039852

Claim:
A coding circuit, comprising: a sequence of delay stages, for storing successive states of a datastream; a first code register, for storing a plurality of bits having states corresponding to a first set of code generator polynomial coefficients; at least one additional code register, for storing a plurality of bits having states corresponding to at least one additional set of code generator polynomial coefficients; and a code register multiplexer, for selecting one of the code registers; a parallel multiplier, comprising a plurality of adder units arranged in rows, each row associated with one of the plurality of bits of the first code register, and each adder unit comprising: a first logic gate for selectively applying a corresponding one of the successive states of the datastream responsive to a corresponding bit of the selected code register; and an adder for adding a sum bit from an adder unit in a previous row with an output of the first logic gate; wherein selected outputs of the adder units in a last row of the parallel multiplier provide an encoded output of the coding circuit.