Patent ID: 8214770

Claim:
A method of designing a mask layout for an integrated circuit, the method comprising the steps of: providing a plurality of mask shapes corresponding to a plurality of layers; providing lithographic models for said plurality of layers, said models describing processes according to which wafer images are transferred from said mask shapes to a wafer; determining, by using a computer, simulated wafer images resulting from transferring said plurality of mask shapes in accordance with said models; providing functional constraints comprising at least one functional inter-layer constraint that ensures proper functional interaction among said simulated wafer images from at least two of said plurality of layers; evaluating said simulated wafer images relative to other of said simulated wafer images from another one of said at least two of said plurality of layers; and if said at least one functional inter-layer constraint is violated, modifying said mask layout to correct said violation wherein modifying said mask layout comprises modifying said simulated wafer images from said at least two of said plurality of layers.