Patent ID: 8239439

Claim:
A computer-implemented method, comprising: providing a computer processor, comprising: a vector arithmetic unit comprising a plurality of processing lanes, each processing lane configured to, in parallel, perform one or more arithmetic operations on a predefined count of operands; a dot product support unit comprising at least one aligner per processing lane, a compressor, and an adder; and an operand reordering device comprising a plurality of multiplexors configured to order unorganized operands and transfer an ordered operand and one or more predetermined values to at least one processing lane of the vector arithmetic unit; wherein the computer processor is configured to perform a dot product operation by the dot product support unit by aligning and then summing the products generated by the plurality of processing lanes of the vector arithmetic unit; receiving, by the computer processor, a single, predefined scalar instruction for adding more than two floating point addends, wherein the predefined instruction is identifiable by an associated opcode; and responsive to the predefined scalar instruction for adding more than two floating point addends, performing, by the operand reordering device, the vector arithmetic unit, and the dot product support unit of the computer processor, a predefined operation to add the more than two floating point addends using a single pass through the processing lanes of the computer processor.