Patent ID: 7424565

Claim:
An interconnect apparatus comprising a transaction packet buffer and control logic operable sequentially to write transaction packets for transmission to the transaction packet buffer and operable to transmit the buffered transaction packets in sequence to a destination, the control logic farther being operable to: on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet; in response to the absence of a control packet indicative of non-receipt by the destination of a transmitted transaction packet within a predetermined period to retransmit the transaction packets transmitted from the transaction packet buffer subsequent to a transaction packet for which an acknowledgment of receipt from the packet destination was last received; wherein the control logic comprises an address buffer, each entry in the address buffer identifying a location in the transaction packet buffer at which a corresponding transaction packet is stored; and wherein the control logic comprises a read pointer indicating an address buffer entry for a next transaction packet to be transmitted, a write pointer indicating an address buffer entry for a next transaction packet to be added to the buffer, and a last acknowledged sequence number pointer indicating an address buffer entry for the transaction packet having a sequence number for which an acknowledgment of receipt from the packet destination was last received.