Patent ID: 6922368

Claim:
A computer comprising: a microprocessor; and a dynamic random access memory (DRAM), coupled to the microprocessor, which includes: a clock controller; an address decoder operatively coupled to the clock controller; an I/O circuit operatively coupled to the clock controller and address decoder; and a memory array, operatively coupled to the I/O circuit and the address decoder, comprising: digit line pair; an internal row address signal (RAS) generator operable to produce an internal RAS in response to an initial power on condition; a sense amplifier that upon an occurrence of the internal RAS pulse during the initial power on condition drives the digit line pair to opposite rails; and an equilibration circuit that upon the occurrence of the internal RAS pulse during the initial power on condition equilibrates voltages on the digit line pair to Vcc/2 and permits a common capacitor plate to charge to Vcc/2.