Patent ID: 7112500

Claim:
A method of fabricating a thin film transistor comprising the steps of: providing a gate over a substrate; providing a gate insulating layer over said gate and said substrate; providing an amorphous silicon layer having a first resistance over said gate insulating layer; providing an impurity on the surface of said amorphous silicon layer; forming a drain electrode and a source electrode separated by a channel region over a contact portion with said amorphous silicon layer; subsequently, removing said impurity from said channel region by exposing said channel region to hydrogen plasma and diffusing said impurity into said contact portion to form a contact layer within said amorphous silicon layer, wherein said contact layer has a second resistance lower than said first resistance; and removing the impurity formed over the amorphous silicon layer in the channel region between the drain and source electrodes while retaining the impurity over the amorphous silicon layer surface contacted with drain and source region, so that the drain and source regions become a contact layer.