Patent ID: 7751995

Claim:
A capacitance measurement method employing a floating gate of a semiconductor device in a circuit having a MOSFET in which a drain is connected to a ground, and a source and a gate are connected to each other, and a capacitor having a capacitance C r connected to the gate, the method comprising the steps of: measuring a voltage V s of the source by applying a voltage V f to the capacitor in a state where a static current I s is applied to the source of the MOSFET; setting the voltage V s when the voltage V f is zero to V o (I s ), and obtaining a slope S from a relationship between the voltage V s and the voltage V f ; setting a standard slope S 0 as a y-intercept of a first-order linear equation obtained from a relationship between the slope S depending on the source current I s and the V o (I s ); and calculating a gate-to-drain overlap capacitance C dgo of the MOSFET based on a capacitance C r of the capacitor and the standard slope S 0 , wherein the gate-to-drain overlap capacitance C dgo of the MOSFET is calculated from an equation: C dgo =[(1 −S 0 )/ S 0 ]*C r .