Patent ID: 8499187

Claim:
An apparatus, comprising: a first pulse generator coupled to a succeeding memory unit input and coupled to a preceding memory unit output, the first pulse generator configured to generate a pulse and further configured to provide the generated pulse and pulses provided to the succeeding memory unit to the preceding memory unit output; a first pulse counter coupled to the succeeding memory unit input and configured to count pulses provided to the succeeding memory unit input to provide a first count; a second pulse generator configured to generate pulses when enabled; a second pulse counter coupled to a preceding memory unit input and the second pulse generator, the second pulse counter configured to count pulses provided by the second pulse generator or count pulses provided to the preceding memory unit input to provide a second count; and a comparator unit coupled to the first and second pulse counters and configured to compare the first and second counts and provide a location count signal based at least in part on the comparison, the location count signal indicative of a location to the memory unit in a memory group.