Patent ID: 7336731

Claim:
A demodulator with a phase-adjusting function comprising: a detecting section including; a delay detection circuit which delays an input modulated signal in a plurality of delaying stages using a first frequency-divided clock obtained by frequency-dividing a sampling clock at a first frequency division ratio to output the delayed modulated wave signal, said sampling clock having a predetermined frequency and a predetermined clock number, and a phase-adjusting circuit which, when a quotient which is obtained by dividing the predetermined clock number at the first frequency division ratio does not become an integer, delays the input modulated wave signal using a second frequency-divided clock, said second frequency-divided clock being obtained by frequency-dividing the sampling clock at a second frequency division ratio, a ratio between said second frequency division ratio and said first frequency division ratio corresponding to the remainder of the quotient to produce a phase-adjusted modulated wave signal which has been adjusted to cause the phase of the input modulated wave signal to coincide with the phase of the delayed modulated wave signal; and a demodulating section which performs predetermined arithmetic operation of the delayed modulated wave signal and the phase-adjusted modulated wave signal to output a digital demodulated signal.