Patent ID: 8786018

Claim:
A transistor device, comprising: an insulating layer; gate electrode embedded in the insulating layer; a dielectric deposition-prohibiting layer formed on a surface of the insulating layer surrounding the gate electrode; a gate dielectric layer selectively formed on the gate electrode, wherein the gate dielectric layer comprises a first dielectric material; a channel structure comprising a carbon nanostructure disposed on the gate dielectric layer; a passivation layer selectively formed on the gate dielectric layer, covering a portion of the channel structure that is disposed on the gate dielectric layer, wherein the passivation layer comprises a second dielectric material; and source and drain contacts formed on opposing sides of the passivation layer in contact with the channel structure, wherein the dielectric deposition-prohibiting layer comprises a material that prevents chemical reactive deposition of the first and second dielectric materials on top of exposed portions of the dielectric deposition-prohibiting layer surrounding the gate electrode when the gate dielectric layer and passivation layer are selectively formed by the chemical reactive deposition of the first and second dielectric materials.