Patent ID: 7947592

Claim:
A process for providing a power metal interconnection ( 115 ) with a metal cap ( 117 / 118 ) on a substrate ( 100 ) having at least one exposed interconnect metal feature ( 107 ), said process comprising the steps of: (a) depositing at least one dielectric layer ( 112 ) over said at least one exposed interconnect metal feature ( 107 ) and said substrate ( 100 ); (b) defining a photolithographic pattern for at least one power metal interconnect ( 115 ) over said substrate ( 100 ), and etching said at least one dielectric layer ( 112 ) to expose said interconnect metal feature ( 107 ) on said substrate ( 100 ); (c) sputter depositing a seed layer ( 114 / 113 ), wherein said seed layer ( 114 / 113 ) comprises a first barrier layer ( 114 ) and a low resistivity power metal layer ( 113 ); (d) defining a photoresist pattern for at least one power metal interconnect ( 115 ), and selectively removing photoresist from said at least one power metal interconnect locations ( 114 / 113 ) such that at least a portion of said low resistivity power metal layer ( 113 ) is exposed; (e) electroplating a low resistivity power metal layer ( 115 ) using said seed layer ( 114 / 113 ) as an electrode; (f) removing said photoresist, and wet-etching said seed layer ( 114 / 113 ) using said electroplated metal ( 115 ) as a mask, and forming said power metal interconnect ( 115 ); (g) depositing at least one layer of at least one flowable dielectric ( 116 ); (h) photolithographically defining a pattern for at least one pad-via layout ( 135 ) in said flowable dielectric layer ( 116 ); (i) opening said at least one pad-via ( 135 ) to expose a portion of said power metal ( 115 ); (j) sputter cleaning and sequentially sputter depositing a second barrier layer ( 117 ) and a wire bondable metal ( 118 ) over said at least one pad-via ( 135 ); and (k) photolithographically defining a pattern for a pad layout and etch removing said wire bondable metal ( 118 ) and said second barrier layer ( 117 ).