Patent ID: 7498263

Claim:
A method of forming a planarized inter-metal insulation film, comprising: forming a metal wiring pattern exposing portions of a semiconductor substrate; forming a polish-stop layer pattern on the metal wiring pattern; forming a first insulation film on the polish-stop layer pattern and the exposed portions of the semiconductor substrate; polishing the first insulation film using a chemical mechanical polishing (CMP) process until the polish-stop layer pattern is exposed to form a first inter-metal insulation film; selectively removing the polish-stop layer pattern from between portion of the first inter-metal insulation film to expose upper surface portions of the metal wiring pattern, such that the exposed upper portions of the metal wiring pattern are stepped down from upper surface portions of the first inter-metal insulation film; and thereafter, forming a second inter-metal insulation film from a second insulation film formed on the upper surface portions of the first inter-metal insulation film and the upper surface portions of the metal wiring pattern.