Patent ID: 8245010

Claim:
A method for memory address arrangement, for a memory to store a serial data representing addresses of pixels in a display panel, wherein the pixels is arranged in the display panel in a manner of array, the memory is coupled to a data converter and is laterally divided into N blocks, each of the N blocks comprises M longitudinal units, and N and M are natural numbers, the method for the memory address arrangement comprising: laterally writing a serial part of the serial data into the memory from an I th longitudinal unit of a P th block of the memory in sequence by the data converter, wherein the number of the serial data is greater than N, wherein the serial part of the serial data corresponds to addresses of first pixels in the display panel, and the first pixels are located on a first row in the array; and laterally writing another serial part of the serial data following the part of the serial data into the memory from a J th longitudinal unit of a Q th block of the memory in sequence by the data converter, wherein the I th longitudinal unit of the P th block and the J th longitudinal unit of the Q th block are located in different rows, and P, Q, I, and J are natural numbers; the another serial part of the serial data corresponds to addresses of second pixels in the display panel, the second pixels are located on a second row in the array, and the second row is a next row after the first row; and P, Q, I, and J satisfy one of following two conditions: (1) Q=P+1 and J=I+1, wherein P is smaller than N, Q is smaller than or equal to N, I is smaller than M, and J is smaller than or equal to M; and (2) P=N, Q=1, I=M, and J=1.