Patent ID: 8039350

Claim:
A method of forming a MOS transistor, the method comprising: forming a gate pattern on a semiconductor substrate; implanting impurity ions in the semiconductor substrate to form a first impurity doped region on a first side of the gate pattern and a second impurity doped region on a second side of the gate pattern; removing a first portion of each of the first and second impurity doped regions to form respective first and second recesses; forming an epitaxial layer on the first and second impurity doped regions that at least partially fills the first and second recesses, and wherein the epitaxial layer comprises doped impurity ions to form a first high concentration impurity doped region adjacent the first side of the gate pattern and a second high concentration impurity doped region adjacent the second side of the gate pattern, and wherein depths of the first and second recesses are shallower than depths of the first and second impurity doped regions, and wherein the impurity concentration of the first high concentration impurity doped region exceeds the impurity concentration of the first portion of the first impurity doped region, and the impurity concentration of the second high concentration impurity doped region exceeds the impurity concentration of the first portion of the second impurity doped region.