Patent ID: 7953938

Claim:
A processor comprising: an operation unit having plural processing elements each for operating a plurality of pieces of data in a parallel manner; a storing unit separated into a plurality of banks; a switching unit switching a path for a data transfer between a device and said plurality of banks, and a path for data reading and data writing between said plurality of banks and said operation unit; and a controller controlling the switching by said switching unit based on free bank information representing that a bank among said plurality of banks is free by said operation unit, wherein one of said banks is used for read data storing for said operation unit, another of said banks is used for write data storing of said operation unit, and said free bank information identifies in addition to said first and second banks, a free bank of said plurality of banks, wherein said controller generates used bank information, which determines one of said banks to be used for data transfer using said operation unit, wherein said controller enables the data transfer with said outside, and other executable requests including the data reading and data writing by said operation unit, when said free bank information is matched with said used bank information representing that a bank among said plurality of banks is used for the data transfer with said outside, and wherein said controller performs the data transfer with said outside based on a predetermined priority of operations when said free bank information is mismatched with said used bank information.