Patent ID: 8024638

Claim:
An information-processing apparatus comprising: a first memory controller comprising: a memory-chip interface that outputs memory addresses in a plurality of portions, including a first-address portion that is sufficient to refresh a set of addresses for a portion of a memory and a second-address portion that specifies one or more locations within the set of addresses; and a refresh controller, coupled to the memory-chip interface, and configured to send read-refresh requests, wherein the read-refresh requests use refresh addresses that cycle through address-bit combinations for the first-address portion and also cycle through address-bit combinations for the second-address portion, and wherein read-refresh result data is fetched to the memory-chip interface as a result of each of the read-refresh requests, wherein the refresh controller further includes a priority controller that sends a first read-refresh request at an initial priority value, and later if the first read-refresh request has not been initiated, increases the priority value.