Patent ID: 7184290

Claim:
A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising: a plurality of bit line pairs, wherein each bit line pair includes a first bit line and a second bit line, wherein the first bit line and the second bit line within each bit line pair are aligned with each other in an end-to-end arrangement, wherein the first bit lines are arranged substantially parallel and consecutively adjacent to one another, wherein the second bit lines are arranged substantially parallel and consecutively adjacent to one another; a plurality of word lines, wherein each word line is associated with one of the first bit lines and the second bit lines such that a first array is formed by the first bit lines and the associated word lines and a second array is formed by the second bit lines and the associated word lines; a plurality of memory cells, wherein each of the plurality of memory cells is associated with every other bit line along each word line; and a first plurality of multiplexers, wherein each of the first plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays, wherein said first array acts as a sense array and said second array acts as a reference array for said first array when at least one of said plurality of word lines is active in said first array.