Patent ID: 7880263

Claim:
A method for a shallow trench isolation structure for integrated circuits, the method comprising: providing a semiconductor substrate; forming a buffered oxide layer overlying the semiconductor substrate; forming a pad nitride layer overlying the buffered oxide layer; patterning the pad nitride layer to expose a portion of the semiconductor substrate corresponding to a trench region; implanting P-type material into a portion of the semiconductor substrate using the patterned pad nitride layer as a protective mask layer while using an angle of implanting of less than 45 degrees to form an implanted region around a perimeter of the trench region within the portion of the semiconductor substrate; forming a blanket layer of oxide material overlying the patterned nitride layer and implanted region of the semiconductor substrate; selectively removing the blanket layer of the oxide material to leave side wall spacers on edges of the pad nitride layer facing the exposed portion of the semiconductor substrate; using the patterned pad nitride and the side wall spacers as a protective layer; etching the exposed portion of the semiconductor substrate to form a trench region within the semiconductor substrate while using the patterned pad nitride and the side wall spacers as the protective layer, the trench region including sharp edge regions defining the trench region on a surface of the semiconductor substrate; selectively removing the side wall spacers on edges of the pad nitride; performing a soft etch on the sharp edge regions of the trench region to reduce a radius of curvature on the sharp edge regions to round the sharp edge regions; performing a high density plasma chemical vapor deposition process to fill the trench region while a dielectric material; planarizing the high density plasma chemical vapor deposition process dielectric material until a portion of the patterned pad nitride layer has been exposed; stripping the patterned pad nitride layer; forming P-well regions within the semiconductor substrate within a vicinity of the trench region; and forming channel regions using boron bearing species within the P-well regions in the semiconductor substrate, the channel regions being providing with 1.5×10 13 atoms/cm 2 at an energy of ranging from about 30 keV to about 40 keV.