Patent ID: 8635575

Claim:
A method, comprising: building a network on a layer of a semiconductor chip; determining one or more rules that govern placement of devices on the network by a computing device; creating, in conformance with the one or more rules, an electrical path on a same layer between two adjacent metal traces that are both on the network to create a metal short on the network which decreases resistance and improves chip yield and reliability; identifying two adjacent metal traces on the same layer of the semiconductor chip and that are on the network; forming an electrical path completely on the same layer of the two adjacent metal traces, the electrical path connecting the two adjacent metal traces; and bypassing one or more vias that connect the two adjacent metal traces to a metal trace formed on another layer of the semiconductor chip, and wherein the electrical path on the same layer is shorter and has less path resistance than a multi-layer electrical path which connects the two adjacent metal traces.