Patent ID: 7012846

Claim:
A memory system comprising: a memory array containing a first plurality of cells, each of first plurality of cells storing a corresponding one of a plurality of data values; a decoding circuit selectively coupling a first cell to a bit line according to an access address, wherein said first cell is comprised in said plurality of cells; a sense amplifier determining whether a current path is present on said bit line, said sense amplifier generating a first logical value as an output if said current path is present on said bit line and another logical value as said output otherwise, wherein said output represents a data value stored in said first cell; and wherein said sense amplifier comprises: a first transistor having a crate terminal connected to a sense enable signal; a second transistor and a third transistor forming a current mirror, a drain terminal of each of said second transistor and said third transistor being connected to a source terminal of said first transistor, a gate terminal of said second transistor being connected to a crate terminal of said third transistor, said crate terminal of said second transistor also being connected to a source terminal of said second transistor at a first node, said bit line also being connected to said first node: a fourth transistor having a gate terminal connected to said sense enable signal, a drain terminal of said fourth transistor being connected to said first node; a resistor being connected to a source terminal of said third transistor at a second node; and an inverter having an input coupled to said second node, wherein an output of said inverter represents said output of said sense amplifier.