Patent ID: 7338815

Claim:
A semiconductor device manufacturing method, comprising; a step of forming a source/drain region of a MOS transistor in a partial area of a semiconductor substrate; a step of forming a refractory metal silicide layer on the source/drain region in the partial area of the semiconductor substrate; a step of forming an insulating film on the refractory metal silicide layer; a step of forming a first conductive film, a ferroelectric film, and a second conductive film in sequence on the insulating film; a step of forming a capacitor consisting of a lower electrode, a capacitor dielectric film, and an upper electrode by patterning the first conductive film, the ferroelectric film, and the second conductive film; and a step of performing an annealing with such a annealing time that an agglomeration area of the refractory metal silicide layer becomes equal to or less than an upper limit area; wherein the upper limit area is defined as an area in which a total resistance value of the refractory metal silicide layer and the source/drain region is equal to or lower than an upper limit resistance value.