Patent ID: 8315109

Claim:
A memory interface circuit comprising: a data output buffer that outputs write data received from outside during writing to a memory device; a write delay-locked loop that outputs a write strobe signal to the memory device through a strobe signal output buffer, wherein the write strobe signal is generated by delaying a phase of a clock signal received from outside during writing; a first latch that latches the write data from the outside in synchronization with the clock signal; a data input buffer that outputs read data received from the memory device during reading; a read delay-locked loop that outputs a delayed read strobe signal generated by delaying a phase of a read strobe signal received from the memory device through a strobe signal input buffer during reading and outputs a delayed write strobe signal generated by delaying a write strobe signal looped back from the strobe signal output buffer through the strobe signal input buffer during writing; a second latch that latches the read data from the data input buffer during reading in synchronization with the delayed read strobe signal and latches the write data looped back from the data output buffer through the data input buffer during writing in synchronization with the delayed write strobe signal; a comparator that compares output from the first latch with output from the second latch during writing and outputs a comparison result as a comparison result signal; a register portion that stores a delay value to be supplied to the read delay-locked loop in order to delay one of the write strobe signal and the read strobe signal; a register control portion that updates the delay value stored in the register portion in accordance with the comparison result signal; and a delay selection portion that is controlled by the register control portion and supplies the read delay-locked loop with the delay value stored in the register portion.