Patent ID: 8124481

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate having an active region having a plurality of channel forming areas extending across the active region and a plurality of junction forming areas also extending across the active region, wherein any two channel forming areas or any two junction forming areas in the active region are not contiguous; forming a device isolation structure in a semiconductor substrate to delimit the active region; recessing the channel forming areas in the active region, thereby forming recessed channel areas; forming gates in and over the recessed channel areas of the active region; forming junction areas in the junction forming areas of the active region; forming an interlayer dielectric over the semiconductor substrate formed with the junction areas; etching the interlayer dielectric to expose the junction areas and parts of the device isolation structure in front of and behind each of the junction areas; forming a first conductive material on each of the exposed junction areas, wherein each first conductive material extends over portions of the exposed parts of the device isolation structure in front of and behind the respective junction area; etching the exposed parts of the device isolation structure in front of and behind each of the junction areas to form a recessed portion in front of and behind each junction area such that portions of the device isolation structure adjacent to the junction areas remain unetched; and forming a second conductive material on each of the first conductive materials and in and over the recessed portions of the device isolation structure in front of and behind each respective junction area, thereby forming landing plugs including a stack of the first and the second conductive materials.