Patent ID: 8806405

Claim:
A method to produce in a computer readable storage device constraint information for use by a computer configured to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing, by using the computer, a net topology pattern structure stored in the storage device that corresponds to a logical net that is associated in the storage device with at least two instance item structures of at least one functional design structure stored in the storage device, wherein the net topology pattern structure is associated in the storage device with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure; wherein the multiple constituent structures include a trunk structure that is associated in the device with attribute information that includes a net the trunk structure applies to, a constraint group specifying rules for the trunk structure, and a constraint group specifying default rules for twigs attached to the trunk structure wherein the trunk structure is an interconnect structure that is oriented in a design to run parallel to a channel in which it is disposed, the twig structure is an interconnect structure that connects a trunk structure to instance item and the twig structure is oriented in a design to run perpendicular to the channel in which it is disposed; and wherein the channel is a region where the connections between trunk structures and twig structures are made.