Patent ID: 7368392

Claim:
A method for fabricating a gate structure of a field effect transistor, comprising: (a) providing a substrate having a metal-containing gate electrode layer formed upon a gate dielectric layer, a contact layer formed upon the metal-containing gate electrode layer, and a patterned mask formed upon the contact layer, the patterned mask defining location and topographic dimensions of the gate structure; (b) etching the contact layer through the patterned mask, the step of etching causing a residue to be deposited upon sidewalls of the contact layer and a lower surface of the feature being etched; (c) etching the metal-containing gate electrode layer using a plasma comprising a bromine-containing gas, wherein the residue on the sidewalls is used to protect the sidewalls of the contact layer from undercutting, wherein said etching further comprises a soft landing period and an overetch period following the soft landing period, where each of the periods uses different process time and substrate bias power; and (d) etching the gate dielectric layer.