Patent ID: 7348671

Claim:
A method for use in fabrication of a semiconductor device, the method comprising: providing a semiconductor wafer having at least one first opening and at least one second opening therein, wherein the at least one first opening has a narrower width than a width of the at least one second opening; forming a first conductive layer of copper over the semiconductor wafer and within the at least one first opening and the at least one second opening in the semiconductor wafer to completely fill the at least one first opening in the semiconductor wafer and only partially fill the at least one second opening in the semiconductor wafer; subsequent to forming the first conductive layer, forming a second conductive layer of a solder comprising at least one of tin and lead over the semiconductor wafer and within the second opening in the semiconductor wafer; and forming, prior to forming the first conductive layer, a dielectric layer within the at least one first opening and within the at least one second opening to substantially electrically isolate the semiconductor wafer from the first conductive layer.