Patent ID: 7885134

Claim:
A refresh controller for embedded DRAM, configured to receive an external access signal, generate a refresh enabling signal REFN, a refresh address signal CRA and a confliction signal, and transmit the refresh enabling signal REFN and the refresh address signal CRA to said embedded DRAM which contains a plurality of memory bank groups, said refresh controller comprising: a status controlling module, configured to generate said refresh enabling signal REFN and a last refresh signal last_ccr according to the refresh interval and clock cycles; a refresh searching module, configured to search in said plurality of memory bank groups for at least one memory bank group that is to be refreshed in the refresh interval, and to generate said refresh address signal CRA according to said external access signal and the searched memory bank group; a scoreboard module, configured to record the status of each of said plurality of memory bank groups according to said refresh address signal CRA and the external access signal; and a confliction detecting module, configured to generate the confliction signal according to said external access signal, last refresh signal last_ccr and the status of each of said memory banks.