Patent ID: 8253248

Claim:
A fabrication method for a semiconductor device having conductive bumps, comprising: providing a semiconductor substrate having a plurality of solder pads and a passivation layer formed thereon, the passivation layer being formed with a plurality of first openings for exposing a desired part of each of the solder pads; forming a first covering layer on the solder pads and the passivation layer of the semiconductor substrate and exposed parts of the solder pads; forming a first metallic layer over the first covering layer, allowing the first metallic layer to electrically connect the solder pads; applying a second covering layer over the first metallic layer and the first covering layer, with a plurality of second openings formed to expose predetermined parts of the first metallic layer; forming a second metallic layer over the exposed parts of the first metallic layer via the second openings and the second covering layer, allowing the second metallic layer to electrically connect to the first metallic layer; applying a third covering layer over the second metallic layer and the second covering layer, with a plurality of third openings formed for exposing predetermined parts of the second metallic layer, wherein each of centers of the third openings corresponds in position to each of centers of the solder pads, respectively; forming a metallic standoff over each of the exposed parts of the second metallic layer via the third openings of the third covering layer; and applying a solder material over the metallic standoff, so as to form the conductive bump together with the metallic standoff.