Patent ID: 8261124

Claim:
A system, comprising: a memory controller component that transmits data; a memory array that includes Y memory components associated with the memory controller component, wherein at least one of the Y memory components is employed to store redundancy information associated with the data, wherein Y is an integer number higher than two; an optimized correction component that is associated with the memory array and facilitates error correction of the data when the data meets a predetermined error correction criteria; and at least one error correction code (ECC) component that corrects data errors associated with the data when the data is read from the Y memory components and the data does not meet the predetermined error correction criteria, wherein the Y is an integer number higher than three, wherein the optimized correction component partitions the data into Y minus 2 (two) data blocks, facilitates the generation of a Q block and a parity block, assembles the Y minus 2 (two) data blocks, the parity block, and the Q block into a data stripe, and utilizes the parity block and the Q block to correct data errors associated with one of the data blocks when the data stripe is read from the Y memory components based in part on the predetermined error correction criteria, wherein the predetermined error correction criteria includes at least one of the Y minus 2 (two) data blocks containing data that has a number of errors that is at or more than a predetermined threshold number of errors, wherein the errors include a positive number of data errors of at least two different data blocks.