Patent ID: 8879640

Claim:
A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, and determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream; wherein said combined de-reordering and de-mapping process on the decoded LLR input bitstream, comprising: retrieving each of the decoded LDPC codewords in the decoded LLR input bitstream; deriving from an original de-mapping index table a new de-mapping index table with each of its index value determined by combining de-reordering with each index of the original index de-mapping table such that the value of each index in the new de-mapping index table is pointing to the bit position of the decoded LDPC codeword; and reorganizing bits in each of the decoded LDPC codewords according to the new de-mapping index table.