Patent ID: 7982704

Claim:
A data driving circuit, comprising: a shift register unit including a plurality of first stages connected in series and receiving data signals and outputting the data signals, wherein each first stage receives the data signals output from a preceding first stage; and a latch unit including a plurality of second stages, wherein each second stage is connected to a different predetermined first stage and receives the data signals output from the predetermined first stage, wherein each of the first stages is connected to a first clock and a second clock and is adapted to receives first clock signals and second clock signals as input, and each of the first stages includes: a first transistor connected between an input port and a first node and being turned on based on the second clock; a second transistor connected between the first clock and a second node and being turned on based on a voltage of the first node; a third transistor connected between a third node and a first power supply and being turned on based on the second clock; a fourth transistor connected between the second clock and the third node and being turned on based on the voltage of the first node; and a fifth transistor connected between a second power supply and an output port and being turned on based on the voltage of the third node.