Patent ID: 7904870

Claim:
A method of integrated circuit (IC) design model testing, comprising: providing an original workload program to a simulator test system, the original workload program exhibiting a first executable instruction length, the simulator test system including an IC design model and workload reduction software (WRS); apportioning, by the WRS of the simulator test system, the original workload program into a plurality of instruction intervals; generating, by the WRS of the simulator test system, a respective basic block vector (BBV) per instruction interval, the resultant BBVs including basic block execution count information; generating, by the WRS of the simulator test system, a respective fly-by vector (FBV) per instruction interval independent of the BBV for that same instruction interval, the resultant FBVs including microarchitecture dependent information; clustering, by the WRS of the simulator test system, the resultant BBVs into a plurality of BBV clusters, each BBV cluster representing a program phase of the original workload program; clustering, by the WRS of the simulator test system, the resultant FBVs into a plurality of FBV clusters, each FBV cluster representing a program phase of the original workload program, the clustering of FBVs being independent of the clustering of the BBVs; generating, by the WRS of the simulator test system, a reduced workload program representative of the original workload program, by using microarchitecture dependent information related to the BBV clusters and FBV clusters, the reduced workload program exhibiting a second executable instruction length less than the first executable instruction length; and executing the reduced workload program on the IC design model of the simulator test system.