Patent ID: 8127108

Claim:
An apparatus for prefetching data in a bus system, coupled to a Master and a Slave, comprising: a first select circuit, receiving a plurality of input signals from the Master and a prefetching address generator, and selecting one signal from the plurality of input signals to output to the Slave, wherein the plurality of input signals comprise an address signal from the Master; the prefetching address generator, generating a prefetching address signal according to the address signal from the Master and transferring the prefetching address signal to the first select circuit; and a prefetching controller controlling the first select circuit, wherein the prefetching controller directs the first select circuit to transfer the prefetching address signal generated from the prefetching address generator to the Slave in response to a prefetching condition is present, wherein the prefetching condition is present if a signal from the Master indicates that the address signal is related to a last address signal and a control signal is identical to a last control signal, or if the signal indicates that the address signal and the control signal are unrelated to the last address and control signals but is matched to a hit logic.