Patent ID: 7655994

Claim:
A semiconductor structure comprising: a semiconductor substrate having n-type semiconducting device regions and p-type semiconducting device regions, each of the n-type semiconducting device regions and the p-type semiconducting device regions having source and drain diffusion regions located therein; a gate stack located on top of the semiconductor substrate of each of the n-type semiconducting device regions and the p-type semiconducting device regions, said gate stack comprising a high k gate dielectric having a Si or Ge content of greater than 50% and a silicon (Si)- or germanium (Ge)-containing gate conductor, wherein the high-k gate dielectric is present on a surface of the semiconducting substrate of the n-type semiconducting device regions and the p-type semiconducting device regions; an insulating interlayer present in the p-type semiconducting device regions located between said high k gate dielectric and said gate conductor, the insulating interlayer comprising at least one of aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), boron nitride (BN), boron oxynitride (BO x N y ), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN), indium oxynitride (InON) or a combination thereof, wherein the insulating interlayer is not present in the n-type semiconducting device regions; and an engineered device channel comprising a counterdoped region located between the source and drain diffusion regions and having a dopant concentration ranging from about 10 17 atoms/cm 3 to about 10 19 atoms/cm 3 , the counterdoped region having a dopant of opposite type than an underlying portion of the semiconductor substrate between the source and drain diffusion regions, wherein said high k gate dielectric and said insulating interlayer and said engineered device channel stabilize the gate stack's threshold/flatband voltage to a targeted value.