Patent ID: 7122432

Claim:
A method of manufacturing a non-volatile semiconductor memory device, comprising: depositing a first gate material layer via a first gate insulating film on a semiconductor substrate; forming a masking material for isolation in pattern on the first gate material layer; forming an isolation trench so as to define device forming regions continuous in a first direction at a predetermined interval in a second direction orthogonal to the first direction by etching the first gate material layer and the semiconductor substrate by use of the masking material; embedding an isolation insulating film into the isolation trench so as to be substantially flush with the masking material; forming in pattern, on the isolation insulating film, a stacked layer of a protective insulating film for protecting the isolation insulating film and a gate embedding-oriented insulating film so as to be continuous in the first direction; removing the masking material by etching with the stacked layer serving as a mask; forming a charge-storage layer having a stacked layer structure of the first gate material layer and a second gate material layer by depositing the second gate material layer and polishing the surface thereof, the charge-storage layer being isolated on the isolation insulating film by the stacked layer; depositing, after removing the gate embedding-oriented insulating film on the isolation insulating film, a third gate material layer via the second gate insulating film on the charge-storage layer and the protective insulating film; and forming in pattern the control gate continuous in the second direction and the charge-storage layer self-aligned with the control gate and isolated in the first direction by sequentially etching the third gate material layer, the second gate insulating film and the charge-storage layer.