Patent ID: 7510937

Claim:
A fabrication method for a nonvolatile semiconductor memory device comprising a memory cell area including memory cells and a peripheral circuit area adjacent to the memory cell area and including peripheral transistors, the method comprising the steps of: (1) forming a first active region in the memory cell area and a second active region in the peripheral circuit area in a substrate by forming isolation insulating films in the memory cell area and the peripheral circuit area so as to be away from a boundary between the memory cell area and the peripheral circuit area; (2) forming a bottom insulating film and an intermediate charge trap film sequentially over the entire surface of the substrate; (3) removing a portion of the intermediate charge trap film formed in the peripheral circuit area using a first mask film; (4) forming a gate insulating film in the peripheral circuit area and also at least part of a top insulating film in the memory cell area; (5) forming a gate electrode film on the top insulating film and the gate insulating film; and (6) forming gate electrodes of memory cells and gate electrodes of peripheral transistors by patterning the gate electrode film, wherein the step (3) comprises a step of aligning an end of the first mask film with the boundary in the substrate.