Patent ID: 6999466

Claim:
An m×m switch having m input ports and m output ports to route m incoming signals, the switch arranged as an m-to-n concentrator, n<m/2, wherein m−n of the m output ports are grouped into a 0-output group while the remaining n output ports are grouped into a 1-output group, and the m incoming signals are compared according to a predetermined order among all possible values of a signal and thus the largest n among the m incoming signals are routed to the 1-output group while the remaining m−n of the m incoming signals are routed to the 0-output group, the concentrator comprising an └m/2┘-to-n first concentrator/sorter to process └m/2┘ of the incoming signals wherein n of the └m/2┘ output ports are grouped into a first 1-output group of the first concentrator/sorter and the largest n among the └m/2┘ incoming signals are routed to the first 1-output group, an ┌m/2┐-to-n second concentrator/sorter to process the remaining ┌m/2┐ of the incoming signals wherein n of the ┌m/2┐ output ports are grouped into a second 1-output group of the second concentrator/sorter and the largest n among the ┌m/2┐ incoming signals are routed to the second 1-output group, and n sorting cells wherein the k-th one of the sorting cells, k=1, 2, . . . , n, has a first input port connected to a specific one of the output ports of the 1-output group of the first concentrator/sorter to receive one signal from the specific output port of the first concentrator/sorter as the first one of the two input signals to the k-th sorting cell and a second input port connected to a specific one of the output ports of the 1-output group of the second concentrator/sorter to receive one signal from the specific output port of the second concentrator/sorter as the second one of the two input signals to the k-th sorting cell and the sorting cell compares the values of its two input signals and routes the one with the larger value to the lower one of its two output ports, and wherein the 1-output group for the m-to-n concentrator comprises the lower output port of all n sorting cells.