Patent ID: 7689958

Claim:
A method for partitioning a logic design for a cycle-based system, comprising: building, using a processor of a computer, an intermediate form data flow graph (IFgraph) from an intermediate form data flow tree (IFtree) associated with the logic design; partitioning the IFgraph for each of at least three levels of hardware granularity of the cycle-based system to obtain a partitioned IFgraph, wherein the partitioning, using the processor of the computer, of the IFgraph comprises: coarsening the IFgraph to obtain a coarsened IFgraph for a first level of the at least three levels of hardware granularity; balancing a set of nodes of the coarsened IFgraph for the first level into a first subset and a second subset to obtain a balanced IFgraph for the first level; uncoarsening the balanced IFgraph for the first level to obtain an uncoarsened balanced IFgraph for the first level; coarsening the uncoarsened balanced IFgraph for the first level to obtain a coarsened IFgraph for a second level of the at least three levels of hardware granularity; balancing a set of nodes of the coarsened IFgraph for the second level into a third subset and a fourth subset to obtain a balanced IFgraph for the second level; uncoarsening the balanced IFgraph for the second level to obtain an uncoarsened balanced IFgraph for the second level; coarsening the uncoarsened balanced IFgraph for the second level to obtain a coarsened IFgraph for a third level of the at least three levels of hardware granularity; balancing a set of nodes of the coarsened IFgraph for the third level into a fifth subset and a sixth subset to obtain a balanced IFgraph for the third level; and uncoarsening the balanced IFgraph for the third level to obtain the partitioned IFgraph, wherein the first subset and the second subset are each within a predefined constraint of the cycle-based system, and wherein the predefined constraint comprises at least one selected from the group consisting of memory capacity, register capacity, bit-register capacity, static random access memory (SRAM) capacity, and number of processor instructions; and rewriting the IFtree based on the partitioned IFgraph.