Patent ID: 6977856

Claim:
A semiconductor integrated circuit device comprising: first and second bit lines; a first memory cell connected to the first bit line; a first line coupled to the first bit line via a first switch MOSFET; a second line coupled to the second bit line via a second switch MOSFET; a sense amplifier connected between the first and second lines and including a CMOS latch circuit, a first precharge circuit connected to the first and second lines and including a first MOSFET, the first MOSFET being connected between the first line and a precharge potential; and a second precharge circuit connected between the first and second bit lines and including a second precharge MOSFET, the second precharge MOSFET being connected between the first and second bit lines, wherein a gate electrode of the first switch MOSFET is inputted a first signal and an upper level of the first signal is a first potential, and wherein a gate electrode of the second precharge MOSFET is inputted a second signal and an upper level of the second signal is a second potential lower than the first potential.