Patent ID: 8892918

Claim:
A system for power management comprising: A plurality of input/output pads; A plurality of input/output cells, each input/output cell coupled to one of the input/output pads; and a plurality of interrupt observe circuits, each interrupt observe circuit coupled to one of the input/output cells, where the interrupt observe circuits are configured to generate an interrupt flag during a low power mode, and wherein each of the interrupt observe circuits comprises: a high detect circuit configured to change a state of the interrupt observe circuit if a signal received at the input/output pad associated with the interrupt observe circuit changes from a low state to a high state; a low detect circuit configured to change a state of the interrupt observe circuit if a signal received at the input/output pad associated with the interrupt observe circuit changes from a high state to a low state; a first OR gate coupled to the high detect circuit and the low detect circuit; and a second OR gate configured to receive a signal from an adjacent interrupt observe circuit and an output from the interrupt observe circuit and to generate an output; and wherein each of the plurality of interrupt observe circuits is coupled to core logic, wherein the core logic is configured to set a state of the plurality of interrupt observe circuits based on an input to the input/output pad associated with each of the interrupt observe circuits when the core logic circuit transitions from a full power mode to a low power mode.