Patent ID: 7851858

Claim:
A semiconductor device comprising: an SOI semiconductor substrate including a semiconductor supporting substrate, a buried insulating film formed on the semiconductor supporting substrate, and a silicon active layer formed on the buried insulating film; and a MOS transistor of a first conductivity disposed on the silicon active layer, the MOS transistor comprising a gate electrode on a gate insulating film; and an element isolation insulating film surrounding the MOS transistor; the gate electrode of the MOS transistor comprising a first polysilicon region of a first conductivity disposed above a channel region of the silicon active layer having a constant thickness; and second polysilicon regions of a second conductivity disposed above edge regions of the silicon active layer at which a thickness of the silicon active layer decreases along a width direction of the MOS transistor; and wherein the element isolation insulating film is disposed between the second polysilicon regions and the edge regions of the silicon active layer.