Patent ID: 7177996

Claim:
A semiconductor apparatus comprising a processor core for performing computation, an external bus interface unit for connecting to an external bus, a memory interface unit for controlling access to a local memory, and an internal bus that interconnects the processor core, the external bus interface unit, and the memory interface unit, the external bus interface unit comprising: an access control unit for receiving an access request conveyed through the external bus, a TLB connected to the access control unit for judging whether the access request is to be honored or rejected, and a TLB control unit for updating the contents of the TLB as requested by the processor core, wherein upon receiving the access request conveyed through the external bus, the access control unit sends to the TLB a TLB check request signal asking whether the requested address falls within one of the access-permitted areas registered in the TLB, the TLB checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit a TLB check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the TLB check result signal indicates that the access request is to be honored, or rejects the access request otherwise.