Patent ID: 7234095

Claim:
A turbo encoded hybrid Automatic Repeat reQuest (ARQ) system comprising: a transmitter that, by equivalently Cyclic Redundancy Check (CRC) encoding inputted data bits using an equivalent CRC generator polynomial, performs CRC encoding and pre-termination simultaneously, multiplexes turbo encoded bits according to equivalent CRC encoded output bits, maps the multiplexed output bits to the channel symbol by bit interleaving, and transmits a channel symbol in packet form to a receiver; and the receiver receives the channel symbol transmitted in the packet form from the transmitter, computes a bit metric for bits that constitute an equivalent CRC encoded and turbo encoded new message symbol, de-multiplexes the received channel symbol by bit de-interleaving, turbo decodes the de-multiplexed new message symbol iteratively by using a computed bit metric, detects whether there are any errors included in the packet by CRC decoding a forward error correction processed frame, which has passed through the iterative turbo decoding, and transmits a signal related to a request for retransmission of a packet in accordance with an existence of errors, wherein the transmitter comprises: (i) an equivalent CRC encoder that performs both CRC encoding and pre-termination simultaneously by performing the equivalent CRC encoding of data bits to be transmitted using an equivalent CRC generator polynomial; (ii) a turbo encoder that turbo encodes equivalent CRC encoded output bits; (iii) a multiplexer that multiplexes the turbo encoded output bits; (iv) a bit interleaver that performs bit interleaving to rearrange an order of the multiplexed output bits; and (v) a modulator that maps the bit interleaved output bits to a channel symbol and transmits the channel symbol in the packet form to the receiver, wherein the turbo encoder comprises: (i) a first component Recursive Systematic Convolution (RSC) encoder that turbo encodes the equivalent CRC encoded output bits according to an original input order and outputs first output additional bits; (ii) a first turbo interleaver that turbo interleaves the equivalent CRC encoded output bits to rearrange an input order of the equivalent CRC encoded output bits; and (iii) a second component RSC encoder that performs the turbo encoding according to the order of the equivalent CRC encoded output bits which were turbo interleaved by the first turbo interleaver and outputs second output additional bits, and wherein the equivalent CRC encoder comprises: (i) a CRC encoder that CRC encodes data bits to be transmitted using a CRC generator polynomial and outputs encoded data bits; and (ii) a pre-termination encoder that performs pre-termination of the CRC encoded output bits by multiplying the CRC encoded output bits by a feedback polynomial of the first component RSC encoder or the second component RSC encoder, and outputs the output bits which were pre-terminated.