Patent ID: 8242810

Claim:
An improved fast settling bit slicing comparator circuit comprising: a comparator having a non-inverting and inverting input; said non-inverting input receiving an input signal; a filter circuit for receiving said input signal and being connected with the inverting input of said comparator; a source resistance configured to be coupled between an input source and the filter circuit; a feedback circuit interconnected between the output of said comparator and the non-inverting input of said comparator for providing a feedback signal that introduces a predetermined hysteresis offset, said feedback circuit additionally interconnected with the inverting input of said comparator through said filter circuit for reducing the effect of the hysteresis offset by providing the feedback signal to both the non-inverting and inverting inputs to reduce the differential voltage between said inverting and non-inverting inputs; said filter circuit including a filter resistance and filter capacitance having a reduced time constant sufficient to compensate for at least a portion of said hysteresis offset.