Patent ID: 8877583

Claim:
A method of manufacturing a semiconductor device, comprising: forming an insulation interlayer on a substrate such that conductive structures on the substrate are covered with the insulation interlayer and a buried contact makes contact with the conductive structures through the insulation interlayer; forming a mold pattern on the insulation interlayer, the mold pattern having a node hole through which the buried contact covered with a metal silicide layer is exposed and the metal silicide layer being formed by a first heat treatment under a first temperature and a second heat treatment under a second temperature higher than the first temperature; forming a cylindrical node-separated lower electrode on a sidewall of the node hole and on the metal silicide layer in the node hole of the mold pattern; removing the mold pattern from the insulation interlayer, thereby exposing the cylindrical lower electrode; forming a dielectric layer such that the cylindrical lower electrode is covered with the dielectric layer; and forming an upper electrode on the dielectric layer; wherein forming the mold pattern through which the metal silicide layer is exposed comprises: forming a metal layer on the insulation interlayer and the buried contact; performing the first heat treatment on the metal layer, thereby forming a preliminary metal silicide layer on the buried contact by a silicidation process between silicon of the buried contact and metal of the metal layer; removing residuals of the metal layer that did not participate in the silicidation process; instantaneously performing the second heat treatment on the preliminary metal silicide layer, thereby forming a metal silicide layer on the buried contact; sequentially forming an etch stop layer and a mold layer on the insulation interlayer and the metal silicide layer; and sequentially and partially removing the mold layer and the etch stop layer, thereby forming the node hole penetrating through the mold layer and the etch stop layer such that the metal silicide layer is exposed through the node hole.