Patent ID: 8368453

Claim:
A switch circuit, comprising: a pair of NMOS transistors connected in series as pass-through transistors to transmit an input signal at an input terminal to produce an output signal at output terminal in response to an active state of a switching signal; a pair of PMOS transistors connected in series as pass-through transistors to transmit the input signal at the input terminal to produce the output signal at output terminal in response to the active state of the switching signal; and a switch network connecting, in response to the active state of the switching signal, sources to bodies of the pairs of NMOS and PMOS transistors, and connecting, in response to an inactive state of the switching signal, the bodies of the pair of NMOS transistors to a first reference voltage, the bodies of the pair of PMOS transistors to a second reference voltage, and the sources of the pairs of NMOS and PMOS transistors to a third reference voltage.