Patent ID: 7727894

Claim:
A method of fabricating an integrated circuit structure, comprising: defining a damascene structure in dielectric material; forming a layer of etch stop material on an upper surface of the dielectric material; forming a layer of conductive material in the damascene structure and over a least a portion of an upper surface of the layer of etch stop material; removing at least a portion of the layer of conductive material until an upper surface of the layer of conductive material is substantially coplanar with the upper surface of the layer of etch stop material, wherein one or more dished regions are formed in the upper surface of the layer of conductive material, a lowest portion of the one or more dished regions being spaced above the upper surface of the layer of etch stop material; forming a layer of planarizing material in at least a portion of the one or more dished regions such that an upper surface of the layer of planarizing material is substantially coplanar with the upper surface of the layer etch stop material; removing at least a portion of the layer of etch stop material until at least a portion of sidewalls of the one or more dished regions are expose above a newly exposed upper surface of the layer of etch stop material; removing at least a portion of the upper surface of the layer of conductive material until the upper surface of the layer of conductive material is substantially coplanar with the newly exposed upper surface of the layer of etch stop material.