Patent ID: 8546913

Claim:
A semiconductor integrated circuit device comprising: a substrate structure layer at least including a pair of diffusion regions arranged at a preset spacing from each other; an interconnect layer at least including a pair of power supply lines arranged at a preset spacing from each other so that said power supply lines will be superposed with said pair of diffusion regions; a capacitance including a first electrode, a dielectric member and a second electrode stacked in this order looking from a side of said substrate structure layer; said capacitance being arranged within a space delimited between said substrate structure layer and said interconnect layer and being formed in a shape of a frame of a preset width; said capacitance of the frame shape being disposed inside an outer rim of a standard cell region so as to extend along the outer rim of the standard cell region; said standard cell region being a region in which a standard cell is arranged between the pair of power supply lines; a first substrate contact that electrically connects one of the power supply lines that is superposed with one of said pair diffusion regions to said one diffusion region, externally of said standard cell region; a second substrate contact that electrically connects the other of the power supply lines that is superposed with the other of said pair of diffusion regions to said other diffusion region, externally of said standard cell region; a first capacitance contact that electrically connects said first electrode and said other diffusion region, internally of said standard cell region; and a second capacitance contact that electrically connects said second electrode to said one power supply line, internally of said standard cell region.