Patent ID: 8433950

Claim:
A system to determine fault tolerance in an integrated circuit comprising: a programmable logic device carried by the integrated circuit; configurable memory carried by the programmable logic device to control at least one of function and connection of a portion of said programmable device; user logic carried by said programmable logic device and in communication with at least one of a user and said configurable memory, said user logic to identify corrupted data in said configurable memory based upon changing user requirements, the user logic being part of a user application function programmed by the user; and data access registers that correspond to the configurable memory and arranged as a shift register having each stage read and write a plurality of configuration memory array column cells via an associated array row data bus, the array row data bus coupled to a multiplexer first input and a multiplexer output, the multiplexer output coupled to a next stage register input, the multiplexer to provide correct data in place of any corrupted data.