Patent ID: 7254599

Claim:
A method comprising: first and second circuits generating in-bit binary codes a m-1:0 and b m-1:0 , respectively; an asynchronous circuit generating in-bit binary code c m-1:0 in response to the asynchronous circuit receiving binary codes a m-1:0 and b m-1:0 ; wherein if binary codes a m-1:0 and b m-1:0 are identical to each other or if binary codes a m-1:0 and b m-1:0 differ from each other by only one bit, the asynchronous circuit generates binary code c m-1:0 identical to one of the binary codes a m-1:0 and b m-1:0 ; wherein if binary codes a m-1:0 and b m-1:0 differ from each other by only two bits, the asynchronous circuit generates binary code c m-1:0 which is identical to a result of left shifting one of the binary codes a m-1:0 and b m-1:0 by one bit with logical zero fill at the least significant bit thereof; wherein if binary codes a m-1:0 and b m-1:0 differ from each other by at least three bits, the asynchronous circuit generates binary code c m-1:0 which is identical to a result of left shifting one of the binary codes a m-1:0 and b m-1:0 by two bits with logical zero fill at the least significant bit thereof; wherein m is at least three.