Patent ID: 8436426

Claim:
A device, comprising: an integrated circuit die, the integrated circuit die including: a semiconductor substrate; a first interconnect having a first conductor layer on the substrate and a second conductor layer on the first conductor, the first interconnect having a first sidewall transverse to the substrate; a second interconnect spaced from the first interconnect, the second interconnect having the first conductor layer on the substrate and the second conductor layer on the first conductor layer, the second interconnect having a second sidewall transverse to the substrate; and a resistive element having a plurality of resistive layers formed on the substrate between the first and second interconnects and on the first and second sidewalls of the first and second interconnects, the plurality of resistive layers comprising: a first resistor layer of chromium boride having a first temperature coefficient of resistance and electrically connecting the first conductor layers of the first and second interconnects; and a second resistor layer of chromium boride on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance.