Patent ID: 8619554

Claim:
An interconnect block for a data processing apparatus, said interconnect block providing data routes via which at least one initiator device may access at least three recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said at least one initiator device and at least one recipient port for communicating with one of at least three recipient devices; said second portion comprising at least two recipient ports for communicating with at least two of said at least three recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein, said first portion comprises: at least two connecting routers associated with said respective at least two parallel connecting routes, and at least one initiator port router associated with said initiator port, said at least one initiator port router configured to perform a transaction in response to a request received from one of said initiator devices at said first portion, said transaction accessing one of said at least three recipient devices and said initiator port router, in response to an address associated with said request, is configured to; provide data routes from said at least one initiator port router to said at least one recipient in response to an address associated with said request indicating said at least one recipient, and provide data routes from said at least one initiator port router to all of said at least two connecting routers in response to said address indicating one of said at least two recipients communicating with said second portion, and to maintain at least one of said data routes for the duration of said transaction.