Patent ID: 7409493

Claim:
A non-volatile memory device comprising: a memory array comprising a plurality of non-adjacent boot areas; a data register, independent from the memory array and comprising a non-volatile portion and a volatile portion of the data register, wherein the data register stores a plurality of protect status bits, each bit corresponding to a protect status of each boot area; and a state machine adapted to perform an erase operation on the plurality of non-adjacent boot areas, wherein the state machine transfers a first protect status bit of the plurality of protect status bits from a non-volatile portion of the data register to a volatile portion of the data register, initiates the erase operation of a first boot area, reads the first protect status bit from the volatile data register, reads a security voltage, and authorizes the erase operation to the first boot area if the first protect status bit is in a first state or the security voltage is greater than a predetermined voltage.