Patent ID: 7276799

Claim:
A chip stack package comprising: a substrate, the substrate including a first surface, the first surface including a plurality of substrate terminals, and a second surface, the second surface including a plurality of connection terminals, the connection terminals being in electrical contact with the substrate terminals; a first chip, the first chip including a backside surface, an active surface, the active surface having a device periphery, a residual portion of a scribe lane extending outwardly from the device periphery of the active surface, a plurality of first connection vias formed through the residual portion of the scribe lane, the first connection vias having an upper surface and a lower surface, the first chip being disposed on and electrically connected to the first surface of the substrate, the electrical connection being established between the lower surfaces of the first connection vias and the substrate terminals; a second chip, the second chip including a backside surface, an active surface, the active surface having a device periphery, a residual portion of a scribe lane extending outwardly from the device periphery of the active surface, a plurality of second connection vias formed through the residual portion of the scribe lane, the second connection vias having an upper surface and a lower surface, the second chip being disposed on and electrically connected to the active surface of the first chip, the electrical connection being established between the lower surfaces of the second connection vias and the upper surfaces of the first connection vias.