Patent ID: 7964931

Claim:
A semiconductor device comprising: a square substrate having a first side and a second side which face each other in a first direction and a third side and a fourth side which face each other in a second direction, the first and second directions intersecting with each other; a plurality of reduced surface field (RESURF) regions having long sides which extend from the first side to the second side of the substrate in an element area on a main surface of the substrate, and including a plurality of flat stripes arranged from the third side to the fourth side of the substrate; semiconductor elements provided between the RESURF regions on the element area of the main surface of the substrate, and having a plurality of flat stripes arranged in the second direction; a first high withstand voltage section having long sides which extend in the second direction along the third and fourth sides in a peripheral area of the main surface of the substrate, and including first trenches with a plurality of flat stripes arranged in the first direction; and a second high withstand voltage section including a plurality of second trenches which are symmetrically arranged with a diagonal line passing through corners of the main surface of the substrate, wherein the first high withstand voltage section has the first trenches in the main surface of the substrate, an insulant filled in the first trenches, and first semiconductor regions provided on the main surface of the substrate and having electric conductivity opposite to electric conductivity of the substrate; the RESURF regions each have a third trench, an insulant filled in the third trench, and a second semiconductor region provided on the main surface of the substrate and having electric conductivity opposite to the electric conductivity of the substrate; and one end of each of the first semiconductor regions is physically connected to an adjacent second semiconductor region.