Patent ID: 7577054

Claim:
A semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, the semiconductor memory comprising: a word driver circuit that drives the word line and has a drive PMOS transistor and drive NMOS transistor which are connected in series between a first node and a second node and each of which has a gate connected to a third node, said word line being connected to a connection node of the two transistors; a first voltage generating circuit that generates a first voltage; and a second voltage generating circuit that generates a second voltage lower than said first voltage, wherein said first voltage or said second voltage is applied to said third node, and said first voltage or second voltage is applied to said first node; and between said third node and the gate of the drive PMOS transistor, there is provided a leakage prevention NMOS transistor having a gate applied with a prescribed voltage.