Patent ID: 7500139

Claim:
A fault-tolerant computer comprising: a pair of duplex systems having respective CPU subsystems operable identically in lock-step synchronism; each of said duplex system comprising: a CPU of the duplex system included in one of said CPU subsystems; a main storage unit included in said one of the CPU subsystems; a CPU bus controller for continuously operating the CPU of the duplex system without shutdown if an asynchronous operation is detected while said CPU subsystems are operating in synchronism with each other; a trace memory for storing information of a writing area for storing data in the main storage unit of the duplex system each time data is stored in the main storage unit of the duplex system after the asynchronous operation is detected by said CPU bus controller; a DMA controller for, if the asynchronous operation is detected by said CPU bus controller, holding a DMA transfer process to transfer the data having the writing area stored in said trace memory, the data being stored in the main storage unit of the duplex system or the other duplex system, the DMA transfer process to transfer the data to the main storage unit of the other duplex system or the duplex system, after the asynchronous operation is detected until a predetermined time is reached; a buffer for temporarily storing input data and thereafter outputting the input data; and an access comparator for sending an interrupt signal to said CPU of the duplex system if details of an access from the CPU of the duplex system through said buffer and details of an access from the CPU of the other duplex system are compared with each other and detected as being not in conformity with each other and also if the storage capacity of said buffer exceeds a predetermined value; wherein said predetermined time to be reached in said DMA controller is a time when the interrupt signal is sent from said access comparator to said CPU of the duplex system.