Patent ID: 8212298

Claim:
A semiconductor storage device having a memory cell section and a peripheral circuit section each comprising at least one MOS transistors, the device comprising: a substrate; a dielectric film on the substrate; and a planar semiconductor layer on the dielectric film, wherein: the at least one MOS transistor in the memory cell section comprises a selection transistor, the at least one MOS transistor in the peripheral circuit section comprises a first MOS transistor and a second MOS transistor which are different in conductivity type from each other, the first MOS transistor includes a first lower drain or source region in the planar semiconductor layer, a first pillar-shaped semiconductor layer on the planar semiconductor layer, a first upper source or drain region in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode, such that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer and is separated therefrom by a first dielectric film, the second MOS transistor includes a second lower drain or source region in the planar semiconductor layer, a second pillar-shaped semiconductor layer on the planar semiconductor layer, a second upper source or drain region in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode, such that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer and is separated therefrom by a second dielectric film; and the selection transistor includes a third lower drain or source region in the planar semiconductor layer, a third pillar-shaped semiconductor layer on the planar semiconductor layer, a third upper source or drain region in an upper portion of the third pillar-shaped semiconductor layer, and a third gate electrode, such that the third gate electrode surrounds a sidewall of the third pillar-shaped semiconductor layer and is separated therefrom by a third dielectric film, and wherein the semiconductor storage device has a first silicide layer in the planar semiconductor layer and connecting at least a part of a surface of the first lower drain or source region of the first MOS transistor and at least a part of a surface of the second lower drain or source region of the second MOS transistor, a voltage output line coupled to the first silicide layer by a pillar-shaped contact , and a second silicide layer on at least a part of a surface of the third lower drain or source region of the selection transistor.