Patent ID: 6924529

Claim:
A MOS transistor comprising: an isolation layer formed at a predetermined region of a semiconductor substrate to define an active region; an upper trench region formed in the active region, the upper trench region crossing the active region to divide the active region into two sub-active regions; a spacer covering at least a pair of sidewalls of the upper trench region that are adjacent to the active region; a lower trench region formed under the upper trench region surrounded by the spacer; a pair of low concentration source/drain regions formed under the spacer, the low concentration source/drain regions being shallower than the lower trench region; a pair of high concentration source/drain regions formed at top surfaces of the sub-active regions that are located at both sides of the upper trench region respectively; a gate insulating layer covering the sidewalls and a bottom surface of the lower trench regions; and a gate electrode filling the lower trench region, surrounded by the gate insulating layer, and filling the upper trench region, surrounded by the spacer.