Patent ID: 7294920

Claim:
A wafer-leveled chip package structure, comprising: a wafer having a first surface, on which an integrated circuit pattern and a plurality of pads are formed, and a plurality of through holes penetrating said wafer; a plurality of first chips each having at least one pad on said first surface of said wafer, wherein said pads being mounted on the surface of said first chip which is opposed to said wafer; a first insulating layer formed on said first surface of said wafer, having a plurality of first conductive vias penetrating said first insulating layer, wherein said first insulating layer covers said first chips and said integrated circuit pattern of said wafer; and a conductive pattern layer formed on a surface opposed to said wafer of said first insulating layer, and said conductive pattern layer is electrically connected with said first conductive vias; wherein a second insulating layer is filled in said through holes and at least one second conducting via passes through said second insulating layer, parts of said first conductive vias are connected with said pads of said wafer, parts of said first conductive vias are connected with said pads of said first chips and part of said first conductive vias are connected with said second conductive vias in said through holes.