Patent ID: 7176113

Claim:
A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising: forming a portion of a charge trapping dielectric layer over the substrate; forming a hardmask over the portion of the charge trapping dielectric layer; patterning the hardmask to form hardmask features having respective first spacings there-between, the first spacings having respective first widths; performing a lightly doped channel (LDC) implant through the portion of the charge trapping dielectric layer to establish LDC regions within the substrate having respective LDC widths corresponding substantially to the first widths; forming a spacer material over the hardmask features and exposed areas of the portion of the charge trapping dielectric layer; patterning the spacer material to form sidewall spacers adjacent to the hardmask features and defining respective second spacings there-between, the second spacings having respective second widths that are less than the first widths; performing a bitline implant through the portion of the charge trapping dielectric layer to establish buried bitlines within the substrate having respective bitline widths corresponding substantially to the second widths; removing the patterned hardmask features and sidewall spacers; forming the remainder of the charge trapping dielectric layer over the portion of the charge trapping dielectric layer; forming a wordline material over the charge trapping dielectric layer; and patterning the wordline material to form wordlines that overlie the LDC regions and buried bitlines.