Patent ID: 8521994

Claim:
A processor comprising: a register file to store a first packed data and a second packed data, the first packed data to include a first data element, a second data element, and at least one other data element, and the second packed data to include a third data element, a fourth data element, and at least one other data element, wherein each data element in the first packed data corresponds to a different data element in the second packed data in a respective position, wherein each of the first, second, third, and fourth data elements comprise at least 16-bits; a decoder to decode a packed data instruction; and an execution unit coupled to the register file and the decoder, wherein the execution unit is to store the first data element from the first packed data and a corresponding data element from the second packed data in the register file as a third packed data in response to the packed data instruction, wherein the first data element in the third packed data comprises at least 16-bits, wherein the corresponding data element is the third data element, and is to store the second data element from the first packed data and a corresponding data element from the second packed data in the third packed data in response to the packed data instruction, wherein the data element corresponding to the second data element is the fourth data element, and wherein the third packed data does not include either the at least one other data element of the first packed data or the at least one other data element of the second packed data, wherein the processor is operable to perform saturation.