Patent ID: 6941444

Claim:
In a computer system, including memory for storing instructions and operands, a central processor able to fetch and decode instructions, a method of performing branch prediction for an instruction comprising: specifying in data associated with said instruction whether static branch prediction or dynamic branch prediction should be used; for static branch prediction, specifying in data associated with said operand whether said branch is predicted taken or not taken; operand descriptor indexes operand descriptors, and memory for storing operand descriptors, and further wherein in the operand descriptor memory, storing an indication of loop count value for a loop count instruction; at execution of a static prediction loop counting instruction, modifying data stored at an location indicated by a a first operand descriptor; if a result of said modifying indicates an end of loop, storing a current program address in a fully-associative loop-exit look-up table; and thereafter, predicting a branch result opposite of a specified static branch prediction if an instruction address matches one stored in said loop-exit look-up table.