Patent ID: 8892972

Claim:
A method for testing an integrated circuit, comprising the steps of: shifting a test vector into a scan chain of the integrated circuit; outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values being generated by combinational logic cells electrically connected with the scan chain; sequentially determining the scan cell value for each scan cell; identifying as a reference scan cell a scan cell last determined to be at an expected logical state for that scan cell; determining whether there is a candidate reference cell that is closer to an input end of the scan chain than the identified reference scan cell; and in the case that there is a candidate reference cell that is closer to an input end of the scan chain than the identified reference scan cell, replacing the identified reference cell with the candidate reference cell as a new identified reference cell for assessing a defect in the integrated circuit.