Patent ID: 8730731

Claim:
A semiconductor memory device comprising: a memory cell array including a matrix of memory cells; a plurality of local bit lines divided into a plurality of local bit line groups in which the plurality of local bit line groups are alternatively connected with at least two global bit lines and coupled with the memory cells; a plurality of bit line selection drivers respectively connected to the local bit lines; an internal boosted voltage generator which generates at least two internal boosted voltages having different levels; and a power transmitter which respectively transmits the at least two internal boosted voltages to a plurality of bit line selection driver groups, into which the plurality of bit line selection drivers are classified according to an arrangement of the local bit lines, wherein at least one of the at least two internal boosted voltages is transmitted according to positions of the memory cells to at least two bit line selection driver groups which correspond to at least two local bit line groups, wherein the at least two local bit line groups include at least one bit line group including at least two bit lines sequentially arranged with another of the at least one bit line group, such that the at least one bit line group including at least two bit lines is connected to a first global bit line of the at least two global bit lines and the another at least one bit line group is connected to a second global bit line of the at least two global bit lines, and the first global bit line is a different line from the second global bit line.