Patent ID: 7884783

Claim:
A data driver, comprising: a first digital-to-analog converter configured to select first and second reference voltages from a plurality of reference voltages depending on upper bits of data and supply the selected first and second reference voltages to a first line and a second line, respectively; a second digital-to-analog converter having: the first line and the second line configured to receive the first and the second reference voltages, respectively; a first group of voltage dividing resistors, the first group of voltage dividing resistors having resistors connected in series between the first line and the second line, the first group of voltage dividing resistors dividing the first reference voltage and the second reference voltage to generate a plurality of gray scale voltages; a voltage dividing resistor unit, the voltage dividing resistor unit including a second group of voltage dividing resistors, the second group of voltage dividing resistors having resistors connected in series between the first line and the second line; and at least one switch between the voltage dividing resistor unit and one of the first line and the second line, the at least one switch including a second switch that corresponds to the second group of voltage dividing resistors, the second switch being configured to connect the second group of voltage dividing resistors in parallel with the first group of voltage dividing resistors between the first line and the second line; and a first group of switches, switches of the first group of switches being respectively connected between nodes of the first voltage dividing resistors and an output terminal, the first group of switches being controlled by the decoder unit and configured to supply a divided voltage to the output terminal; a second group of switches, switches of the second group of switches being respectively connected between the nodes of the first voltage dividing resistors and corresponding nodes of the second voltage dividing resistors, the second group of switches being configured to be turned on simultaneously with the second switch; and a decoder unit configured to control on and off states of the at least one switch depending on lower bits of data.