Patent ID: 6934733

Claim:
An adder based circuit embodied in an integrated circuit comprising an input module responsive to inputs A[i] and B[i] to generate a first input function U[i]=A[i]&B[i] and a second input function V[i]=A[i] B[i] or V[i]=A[i]⊕B[i]; a carry module responsive to the first and second input functions to generate carry functions; and an output module responsive to the first and second input functions and the carry function to provide an output function S = ∑ i = 0 n ⁢ 2 i ⁢ S ⁡ [ i ] = ∑ i = 0 n - 1 ⁢ 2 i ⁢ A ⁡ [ i ] + ∑ i - 0 n - 1 ⁢ 2 i ⁢ B ⁡ [ i ] , wherein the carry module has a minimal depth defined by a recursive expansion of at least one function associated with the carry module based at least in part on a parameter k, where k≧F_l and n−k≦F_{l−1} and where l satisfies F_l<n≦F_{l+1}, F_{l−1}, F_l and F_{l+1} are members of a Fibonacci series and n is the number of bits of at least one of the inputs.