Patent ID: 8476946

Claim:
A delay lock loop, comprising: a phase frequency detector having a first input terminal for receiving a reference clock, a second input terminal for receiving a feedback clock, a first output terminal for outputting an upper switch signal, and a second output terminal for outputting a lower switch signal; a loop filter having a first input terminal for receiving the upper switch signal, a second input terminal for receiving the lower switch signal, and an output terminal for outputting a control voltage, wherein the loop filter includes a first capacitor, a second capacitor, and a first switch, and the first switch is coupled between a first terminal of the first capacitor and a first terminal of the second capacitor, wherein the first capacitor is charged/discharged and the first switch is turned off when the loop filter is in phase tracking, and the first switch is turned on when the loop filter is in phase locking; and a voltage control delay line having a first input terminal for receiving the reference clock, a second terminal coupled to the output terminal of the loop filter for receiving the control voltage, and an output terminal for outputting the feedback clock.