Patent ID: 7615434

Claim:
A fabricating method of a CMOS device, comprising: providing a substrate having a first active area and a second active area separated by an isolation structure; forming a first-type MOS transistor and a second-type MOS transistor respectively on the first active area and the second active area of the substrate; forming a first stress layer on the substrate, compliantly covering the first-type MOS transistor, the second-type MOS transistor, and the isolation structure; compliantly forming a first liner layer on the first stress layer, wherein the first liner layer and the first stress layer have a high etching selection ratio; forming a first photoresist layer on the first liner layer of the first active area; patterning the first liner layer with the first photoresist layer to remove the first liner layer in the second active area; removing the first photoresist layer; patterning the first stress layer by using the patterned first liner layer as a first mask to remove the first stress layer in the second active area, after the first photoresist layer is removed, wherein the first stress layer is directly in contact with the first-type MOS transistor; forming a second stress layer on the substrate, compliantly covering the second-type MOS transistor and the first liner layer; compliantly forming a second liner layer on the second stress layer, wherein the second liner layer and the second stress layer have a high etching selection ratio; forming a second photoresist layer on the second liner layer of the second active area; patterning the second liner layer with the second photoresist layer to remove the second liner layer in the first active area; removing the second photoresist layer; and patterning the second stress layer by using the patterned second liner layer as a second mask to remove the second stress layer in the first active area after the second photoresist layer is removed, wherein the second stress layer is directly in contact with the second-type MOS transistor, the patterned second liner layer remains on the second active area, and the patterned first liner layer remains on the first active area.