Patent ID: 7871902

Claim:
A method of making a semiconductor component, the method comprising: forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels; forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels, the BEOL layers comprising metal lines and vias embedded in an inter level dielectric layer; forming crack stop trenches encircling the cell regions by etching the BEOL layers surrounding the cell regions, wherein a portion of the BEOL layers surrounding the cell regions comprises an inner continuous metallic wall on an edge of each cell region and an outer continuous metallic wall on an edge of the dicing channel, wherein the portion of the BEOL layers between the inner continuous metallic wall and the outer continuous metallic wall comprises no metal, and wherein forming the crack stop trenches encircling the cell regions comprises etching the BEOL layers between the inner continuous metallic wall and the outer continuous metallic wall; and dicing the substrate by dicing along the dicing channels.