Patent ID: 7030494

Claim:
A semiconductor package comprising: a semiconductor structure comprising: (a) a semiconductor substrate including an integrated circuit provided thereon and a plurality of connection pads that are each electrically connected to the integrated circuit, and (b) a plurality of electrodes for external connection which are provided on the semiconductor substrate; an insulation layer provided around the semiconductor structure; a first upper insulation film provided on the semiconductor structure and the insulation layer; an upper wiring which includes connection pad portions and is provided on the first upper insulation film such that at least a part of the upper wiring is connected to the electrodes for external connection of the semiconductor structure; a micro electric mechanical system electrically connected to at least one of the connection pad portions of the upper wiring; a protection cover arranged to cover the micro electric mechanical system; pole electrodes electrically connected to others of the connection pad potions of the upper wiring; and a second upper insulation film covering vicinities of the pole electrodes, and at least a vicinity of the micro electric mechanical system.