Patent ID: 8898429

Claim:
An application processor, comprising: a system memory unit including one page table; a plurality of peripheral devices configured to share the page table and to perform a write operation and a read operation on the system memory unit using the page table, each of the plurality of peripheral devices including a memory management unit (MMU) having a translation lookaside buffer (TLB) configured to store a virtual address and a physical address corresponding to the virtual address; a control unit configured to divide a total virtual address space corresponding to the page table into a plurality of sub virtual address spaces, to assign the plurality of sub virtual address spaces to the plurality of peripheral devices, respectively, to allocate a DMA (Direct Memory Access) buffer in the system memory unit, to release the DMA buffer from the system memory unit, and to update the page table, at least two of the plurality of sub virtual address spaces having different sizes from each other; and a central processing unit configured to control the plurality of peripheral devices and the control unit.