Patent ID: 7254729

Claim:
Apparatus comprising: a system clock generator which produces a system clock; and a memory module which is coupled to said system clock generator and which produces an internal operation clock for use within the memory module, the internal operation clock being synchronized with an external clock present at an external clock input of the memory module, wherein the system clock is supplied to the external clock input of the memory module and wherein the memory module includes: a first DLL circuit which generates a first internal clock from an external clock in a first frequency band; a second DLL circuit which generates a second internal clock from an external clock in a second frequency band different from the first frequency band; and a selector which selects any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputs the selected clock as the internal operation clock for the memory module; and wherein a graphic controller which is coupled to said memory module and which controls draw processing of an image displayed on a display device through use of said memory module as a graphic memory; and wherein an operation state detector which detects an operation state of said graphic controller, and allows the selector to select the second internal clock generated by the second DLL circuit operated based on the external clock in the second frequency band lower than the first frequency band when the graphic controller is in an idle state; and wherein the operation state detector stops an operation of the first DLL circuit when the graphic controller is in the idle state.