Patent ID: 7879627

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising: in a plurality of semiconductor manufacturing processes, forming a plurality of layers on a substrate so as to fabricate a semiconductor device; using a multidirectional overlay mark to determine an overlay between at least two separately generated patterns on a single or successive layers of the semiconductor device, the multidirectional overlay mark comprising (i) a first region having at least two separately generated working zones, that are juxtaposed relative to one another, and are configured to provide overlay information in a first direction, and each include a periodic structure comprised of a plurality of coarsely segmented elements positioned therein, (ii) a second region having at least two separately generated working zones, that are juxtaposed relative to one another, and are configured to provide overlay information in the first direction, and each include a periodic structure comprised of a plurality of coarsely segmented elements positioned therein, (iii), a third region having at least two separately generated working zones, that are juxtaposed relative to one another, and are configured to provide overlay information in a second direction that differs from the first direction, and each include a periodic structure comprised of a plurality of coarsely segmented elements positioned therein, and (iv) a fourth region having at least two separately generated working zones, that are juxtaposed relative to one another, and are configured to provide overlay information in the second direction, and each include a periodic structure comprised of a plurality of coarsely segmented elements positioned therein, wherein the working zones of the first and second regions that were generated together are diagonally opposed and spatially offset relative to one another, wherein the working zones of the third and fourth regions that were generated together are diagonally opposed and spatially offset relative to one another, wherein the determined overlay is used to control a process for forming the at least two separately generated patterns on a single or successive layers of the semiconductor device.