Patent ID: 7105402

Claim:
A method of forming a semiconductor construction, comprising: forming a pair of transistor constructions and an isolation region, wherein: the transistor constructions are electrically separated from one another by the isolation region; each of the transistor constructions comprises a transistor gate between a pair of source/drain regions, the transistor gates comprising a first semiconductive material conductively doped to a first dopant type, and the source/drain regions comprising a second semiconductive material conductively doped to the first dopant type; the isolation region comprises a mass between two of the source/drain regions, the isolation region mass comprising the first semiconductive material conductively doped to a second dopant type; one of the first and second dopant types is n-type and the other is p-type; the method further comprising: initially doping the first semiconductive material of the isolation region mass with first type dopant; and subsequently counter-doping the first semiconductive material of the isolation region mass with sufficient second type dopant to form the second type doped first semiconductive material of the isolation region mass.