Patent ID: 7684242

Claim:
A flash memory device comprising: a memory cell array having a plurality of memory cells for storing data, wherein a portion of the memory cells is configured to store initial data; a page buffer circuit having a plurality of page buffers configured to store data to be programmed in the memory cell or data to be read from the memory cell; a controller comprising a data evaluating circuit, wherein the controller is configured to: control the page buffer circuit so that the initial data stored in the memory cell array is read by the page buffer circuit when the flash memory device is powered up, determine, by the data evaluating circuit, whether the initial data read from the memory cell array by the page buffer circuit has an error, in the event that the data evaluating circuit determines that the initial data has an error, control the page buffer circuit so that the initial data is read again, and in the event that the data evaluating circuit determines that the initial data does not have an error, transmit the initial data; and an initial data latching circuit configured to receive and latch the initial data transmitted by the controller.