Patent ID: 6888739

Claim:
A write once read only memory cell, comprising: a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET including: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles; and a gate formed on the gate insulator; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; a transmission line coupled to the second source/drain region; and wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ) and such that the programmed MOSFET operates at reduced drain source current.