Patent ID: 7746695

Claim:
A bi-stable latch circuit having a pair of cross-coupled branches, each branch including a driver and a load, the branch connected between a drain line and a source line, and each branch providing a non-volatile memory cell having a program transistor and a read transistor, wherein: at least one of the driver and load of a branch includes the corresponding read transistor; said driver and load of each branch are connected in series and provide a respective output node; said read transistor and said program transistor of each branch have a common floating gate ( 13 , 14 ) and separate control gates; each control gate of each program transistor is connectable to a program voltage; a drain of each program transistor is connected to a respective input node; said control gate of said read transistor in each branch is connected to the output node of the other branch; and wherein said drain and source line are connectable across a common supply voltage in static mode and at least one of said drain and source lines is disconnectable from said common supply voltage in a program mode.