Patent ID: 7608887

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell section provided with a plurality of memory cell transistors each having a first gate electrode on the semiconductor substrate, a first insulating film formed at a side wall of the first gate electrode and at the lower periphery to the side wall, and a first sidewall made of an insulating film formed at a side of the first insulating film; and a periphery circuitry section formed in the vicinity of the memory cell section and provided with a plurality of periphery circuitry transistors each having a second gate electrode, a second insulating film formed on a side wall of the second gate electrode and at the lower periphery to the side wall, and a second sidewall made of an insulating film formed at a side of the second insulating film; the periphery circuitry section controlling memory operations with respect to the memory cell section, wherein, in the memory cell section of the memory cell section and the periphery circuitry section, an electric charge accumulation layer made of an insulating film is formed on top of the first insulating film lower periphery and between the side face of the first insulating film and the first sidewall.