Patent ID: 8629435

Claim:
A method comprising: providing a first test structure comprising: a first isolation region; a first gate electrode over the first isolation region; a first and a second semiconductor fin parallel to each other and on a side of the first gate electrode; and a first contact plug over and electrically connected to the first and the second semiconductor fins; providing a second test structure comprising: a second isolation region; a second gate electrode over the second isolation region; a third semiconductor fin and a first dielectric fin parallel to each other and on a side of the second gate electrode, wherein the first, the second, and the third semiconductor fins and the first dielectric fin have substantially a same fin height; and a second contact plug over and electrically connected to the third semiconductor fin; measuring a first capacitance between the first gate electrode and the first contact plug; measuring a second capacitance between the second gate electrode and the second contact plug; and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance.