Patent ID: 6849949

Claim:
A stacked package formed by stacking a plurality of semiconductor device packages, each semiconductor device package comprising: a plurality of leads each including inner leads having a thickness and connection terminals having a thickness less than said thickness of the inner leads, said inner leads arranged along sides of a chip receiving area, said connection terminals lying adjacent to the chip receiving area; a semiconductor chip having first and second surfaces located in the chip receiving area, the first surface of the semiconductor chip being electrically connected to the connection terminals, the second surface of the semiconductor chip being exposed, wherein said inner leads and said connection terminals do not overlay or underlay said semiconductor chip; and a package body encapsulating the semiconductor chip and the connection terminals of the inner leads, said package body having a thickness such that an upper and a lower surface of the inner leads is exposed, wherein each of the packages is stacked on another package by electrically connecting the exposed upper and lower surfaces of the inner leads with each other and wherein the exposed second surface of the semiconductor chip in an upper package body contacts an upper surface of a lower package body.