Patent ID: 8385401

Claim:
An equalizer for performing equalization on an input electrical signal to produce an equalized output electrical signal, the equalizer comprising: at least a first finite impulse response (FIR) filter comprising N tunable delay cells cascaded between an input of the first FIR filter and an output of the first FIR filter, the first FIR filter processing a first input signal received at the input of the first FIR filter to produce a first output signal at the output of the first FIR filter, each tunable delay cell providing a respective time delay period during which a respective input signal to the respective delay cell is delayed before being output from the respective delay cell, and wherein the time delay periods provided by the respective tunable delay cells of the FIR filter are tunable to allow the respective time delay periods to be adjusted; and a delay control component configured to perform a calibration algorithm, the delay control component comprising at least one replica tunable delay cell that provides a time delay period that is tunable to allow the tunable time delay period of the replica delay cell to be varied by a selected amount, and wherein the replica delay cell receives an input clock signal, CLK, at an input to the replica delay cell and delays CLK by the tunable time delay period provided by the replica delay cell before outputting a delayed CLK at an output of the replica delay cell, the delay control component including circuitry that measures a phase difference value, Phase_Diff, between the input CLK and the delayed CLK, the calibration algorithm determining an amount by which the respective tunable time delay periods of the N tunable delay cells of the first FIR filter are to be adjusted based on the Phase_Diff value and adjusting the respective tunable time delay periods by the determined amount such that the respective tunable delay cells provide the adjusted respective time delay periods.