Patent ID: 6960507

Claim:
A method of manufacturing a vertical double channel silicon-on-insulator (SOI) field effect transistor (FET), comprising: a. forming a pair of shallow trench isolation (STI) regions in an active region of a substrate so that an upper surface of the shallow trench isolation regions protrudes above an upper surface of the substrate; b. performing a first ion implantation process on the active region of the substrate to form a pair of vertical transistor channels and a bottom channel, wherein the pair of vertical transistor channels and the bottom channel extend in a longitudinal direction; c. forming sidewall spacers on the active region of the substrate above the pair of vertical transistor channels and adjacent to the protruding portion of the pair of shallow trench isolation regions; d. etching the active region of the substrate, using the sidewall spacers as a mask, to expose the pair of vertical transistor channels and the bottom channel, wherein the pair of vertical transistor channels and the bottom channel define a trench; e. performing a second ion implantation process on the exposed bottom channel; f. forming a gate oxide layer between the pair of vertical transistor channels on the bottom channel in a lateral direction at a midsection of the substrate; g. forming a gate electrode on the gate oxide layer, the sidewall spacers, and an upper surface of the pair of vertical shallow trench isolation regions; h. performing a third ion implantation process on the exposed pair of vertical transistor channels to form a pair of vertical source/drain regions; i. depositing an oxide layer on the bottom channel, the sidewall spacers, and an upper surface of the shallow trench isolation regions so that the oxide layer is adjacent to the gate oxide layer and the gate electrode, the oxide layer filling the trench; j. etching the oxide layer to expose an upper portion of the pair of vertical source/drain regions; and k. forming a source/drain contact electrode on the bottom channel and between the pair of vertical source/drain regions so that an upper surface of the source/drain contact electrode is even with an upper surface of the gate mask.