Patent ID: 7098711

Claim:
A semiconductor device comprising: a delay circuit including 2n (n is a natural number) unit delay circuits for delaying an input clock signal (with the period of T) in accordance with a delay amount setting signal for controlling the delay amount and generating and outputting 2n phases of delayed clock signals; a phase locked circuit for locking phases of two of the outputs from the delay circuit to be in phase with each other and for outputting the delay amount setting signal for causing each of the first to the last stages of the unit delay circuits to delay the phase of an output clock signal by T/2n; a correction circuit to which the input clock signal and the delay amount setting signal are input for generating a corrected clock signal by delaying the input clock signal, and outputting the corrected clock signal to the delay circuit; and a bias circuit for generating first and second delay amount setting signals in accordance with the delay amount control signal and supplying the first and the second delay amount setting signals to the delay circuit, wherein the first and the second delay amount setting signals control an amount of current flowing through at least one of the unit delay circuits.