Patent ID: 7358131

Claim:
A method of forming an SRAM construction comprising: providing a substrate; forming an electrically insulative layer over the substrate; forming a first silicon/germanium layer over the electrically insulative layer, the first silicon/germanium layer being background n-type doped and having a relaxed crystalline lattice; forming a second silicon/germanium layer over and directly against the first silicon/germanium layer, the second silicon/germanium layer being background n-type doped and comprising a strained crystalline lattice; forming three p-type doped diffusion regions extending through the second silicon/germanium layer and into the first silicon/germanium layer; the three p-type doped diffusion regions being laterally spaced from one another, and being a first p-type diffusion region, a second p-type diffusion region and a third p-type diffusion region, respectively; forming a first gate electrode above the p-type diffusion regions, the first gate electrode gatedly coupling the first and second p-type diffusion regions to one another, the first gate electrode comprising n-type doped silicon; forming a second gate electrode above the p-type diffusion regions, the second gate electrode gatedly coupling the second and third p-type diffusion regions to one another, the second gate electrode comprising n-type doped silicon; forming a background p-type doped semiconductor layer over the first and second gate electrodes; forming three n-type doped diffusion regions over the first and second gate electrodes and extending upwardly into the background p-type doped semiconductor layer; the three n-type doped diffusion regions being laterally spaced from one another, and being a first n-type diffusion region, a second n-type diffusion region and a third n-type diffusion region, respectively; the first and second n-type diffusion regions being electrically gatedly coupled to one another by the first gate electrode, and the second and third n-type diffusion regions being electrically gatedly coupled to one another by the second gate electrode; the first, second and third n-type diffusion regions being directly over the first, second and third p-type diffusion regions, respectively; forming a first p-type doped electrical interconnect electrically connecting the first p-type diffusion region and first n-type diffusion region to one another; and forming a second p-type doped electrical interconnect electrically connecting the second p-type diffusion region and second n-type diffusion region to one another.