Patent ID: 6927115

Claim:
A method of fabricating a semiconductor integrated circuit comprising: selectively forming a first diffusion region of the second conductivity type on a semiconductor substrate of a first conductivity type; growing an epitaxial layer of the second conductivity type on said first diffusion region so as to make said first diffusion region a first buried region; selectively diffusing impurity atoms of the second conductivity type so as to form a first plug region of the second conductivity type, from a top surface of said epitaxial layer such that a bottom of said first plug region reaches to said first buried region; selectively diffusing impurity atoms of the second conductivity type so as to form a graded base region of the second conductivity type, from the top surface of said epitaxial layer, a lateral position of the graded base region is separated from the lateral position of said first plug region and a vertical position of the graded base region is separated from the vertical position of said first buried region, the graded base region has a doping profile such that impurity concentration decreases towards peripheral region from central region of the graded base region; forming a first main electrode region of the first conductivity type in and at the top surface of said graded base region; and forming a said second main electrode region of the first conductivity type, so as to sandwich said graded base region between said first and second main electrode regions, in and at the top surface of said epitaxial layer.