Patent ID: 7003652

Claim:
An apparatus for processing data, said apparatus comprising: (i) a processor core operable to execute operations as specified by instructions of a first instruction set; (ii) an instruction translator operable to translate instructions of a second instruction set into translator output signals corresponding to instructions of said first instruction set, at least one instruction of said second instruction set specifying an operation to be executed using one or more input variables; (iii) an interrupt handler responsive to an interrupt signal to interrupt execution of operations corresponding to instructions of said first instruction set after completion of execution of any currently executing operation; and (iv) restart logic for restarting execution after said interrupt; wherein (v) said instruction translator is operable to generate a sequence of one or more sets of translator output signals corresponding to instructions of said first instruction set to represent said at least one instruction of said second instruction set, each sequence being such that no change is made to said one or more input variables until a final operation within said sequence is executed; and (vi) after occurrence of an interrupt during execution of a sequence of operations representing said at least one instruction of said second instruction set: (a) if said interrupt occurred prior to starting execution of a final operation in said sequence, then said restart logic restarts execution at a first operation in said sequence; and (b) if said interrupt occurred after starting execution of a final operation in said sequence, then said restart logic restarts execution at a next instruction following said sequence.