Patent ID: 7508368

Claim:
A drive voltage generator circuit comprising: a breeder developing a set of first to N-th different voltages on first to N-th nodes, respectively, N being any integer equal to or more than 2, and said first to N-th voltages being associated with grayscale levels, respectively; a buffer amplifier; a set of first to N-th output terminals through which drive voltages are provided for an LCD panel; and a switch circuitry that switches connections among an input and an output of said buffer amplifier, said first to N-th nodes, and said first to N-th output terminals, wherein each horizontal period is divided into first to N-th time periods, wherein said first to N-th voltages satisfy the following relation: V 1 <V 2 < . . . <V N , where V i is a level of said i-th voltage, wherein, during a first time period within a first horizontal period during which a common electrode within said LCD panel is pulled down to ground, said switch circuitry connects said first node to said input of said buffer amplifier, and connects said output of said buffer amplifier to all of said first to N-th output terminals, wherein, during an i-th time period within said first horizontal period with i being any integer ranging from 2 to N, said switch circuitry connects said i-th node to said input of said buffer amplifier, connects said output of said buffer amplifier to said i-th to N-th output terminals, disconnecting said first to (i−1)-th output terminals from said output of said buffer amplifier, and connects said first to (i−1)-th nodes to said first to (i−1)-th output terminals, respectively, wherein, during a first time period within a second horizontal period during which a common electrode within said LCD panel is pulled up to a voltage, said switch circuitry connects said N-th node to said input of said buffer amplifier, and connects said output of said buffer amplifier to all of said first to N-th output terminals, and wherein, during an i-th time period within said second horizontal period, said switch circuitry connects said (N−i+1)-th node to said input of the buffer amplifier, connects the output of the buffer amplifier to said first to (N−i+1)-th output terminals, disconnecting said (N−i+2)-th to N-th output terminals from said output of the buffer amplifier, and connects said (N−i+2)-th to N-th nodes to said (N−i+2)-th to N-th terminals.