Patent ID: 7406581

Claim:
A computer system having: a physical processor operable to issue memory access requests to a memory address space; a memory map for addressing a plurality of selectively available memory mapped devices, using a page for each memory map device; translation circuitry for translating virtual memory addresses into physical memory addresses, wherein the memory map is divided into virtual pages mapped to corresponding physical addresses, the pages having a page size greater than the memory space occupied by at least one of said memory mapped devices; and a memory access system for accessing said memory mapped devices when available, the memory access system having: an input for receiving a physical memory address from said physical processor; means for defining a plurality of valid memory regions covering a memory space within which there exists at least one of said available memory mapped devices; means for checking whether the received physical memory address lies in at least one of the defined memory regions, whereby if it does, the address is validated for access, and if it does not, an error is returned; a prefetching unit for identifying received physical memory addresses corresponding to speculative load operations directed to the at least one memory mapped device occupying memory space smaller than the page size; and means for checking whether the received physical memory address of one of said speculative load operations lies in at least one of the defined memory regions, whereby if it does, the address is validated for access, and if it does not, an error is returned.