Patent ID: 8386867

Claim:
A method of testing a memory board, the method comprising: testing a memory of the memory board, the memory being a serial port dynamic random access memory (SPDRAM) including a plurality of serial ports, testing of the memory including: providing, by a first built-in self-test structure of the memory a first test pattern for the testing of the memory, wherein the first test pattern complies with a protocol for the memory; performing error checking for the testing of the memory by enabling detection of legal commands for the memory; and testing an IO (input output) interface of the memory, the IO interface to be coupled to a host, testing of the IO interface including: providing, by the first built-in self-test structure of the memory, a second test pattern for the testing of the IO interface; wherein testing of the memory is separate from the testing of the IO interface, and wherein the first built-in self-test structure includes a set of memory interface test structures and a set of IO interface structures; wherein the second test pattern for the testing of the IO interface does not comply with the protocol for the memory.