Patent ID: 7539968

Claim:
A method for performing an iterative synthesis of an integrated circuit design to attain power closure while maintaining other design criteria, comprising: performing an initial synthesis of the integrated circuit design to generate a netlist containing a listing of circuits and interconnections that form the integrated circuit design; generating a tag list that specifies a tag for each node in the netlist; identifying a predetermined number of nodes from the netlist that are representative of worst case power consuming nodes; performing a power reduction algorithm on each of the predetermined number of nodes; calculating power of the netlist after each instance that a power reduction algorithm is run on a node selected from the predetermined number of nodes; determining after each instance that a power reduction algorithm is run on a node selected from the predetermined number of nodes whether the netlist satisfies design constraints specified for the integrated circuit design; using the tag list to iterate through the performing of a power reduction algorithm, calculating of power and determining of whether the netlist satisfies specified design constraints for each of the predetermined number of nodes; and generating a final netlist after all of the predetermined number of nodes have been iterated through the performing of a power reduction algorithm, calculating of power and determining of whether the netlist satisfies specified constraints.