Patent ID: 7349513

Claim:
A circuit for modeling a coarse delay element with a plurality of fine delay elements for a delay locked loop, the circuit comprising: first and second parallel delay paths receiving a clock signal, the first path including a first plurality of delay elements and the second path including a second plurality of delay elements; a phase detector for receiving the first and second clock delay signals from the first and second delay paths respectively, for detecting a phase difference between said first and second clock delay signals, the phase detector providing the phase difference to a counter; and a decoder for receiving a signal from the counter, the decoder being connected to the first plurality of delay elements within the first delay path for adjusting the delay provided by the first delay path until the first and second clock delay signals are in a locked state, the delay lock loop including a coarse delay line for receiving a system clock, a fine delay line coupled to an output of the coarse delay line for providing a delay clock signal, and a main phase detector for receiving the system clock and the delay clock signal, the main phase detector coupled to a main fine counter, the main fine counter being adjusted by the signal from the counter for adjusting the fine delay line.