Patent ID: 7525162

Claim:
A semiconductor structure comprising: a substrate containing a first silicon layer having a (110) surface orientation; a p-type field effect transistor (PFET) located on said first silicon layer and containing a PFET channel between a PFET source region and a PFET drain region, wherein an azimuthal angle between a direction of current flow in said PFET channel and an in-plane [1 1 0] crystallographic direction in said first silicon layer is from about 25° to about 55°; a PFET gate line located over said PFET channel; a compressive stress liner located on said PFET gate line, a PFET source region, and a PFET drain region, wherein said compressive stress liner produces a compressive longitudinal strain in said PFET channel; a second silicon layer having a (001) surface orientation; an n-type field effect transistor (NFET) located on said second silicon layer and containing an NFET channel, an NFET source region, and an NFET drain region; an NFET gate line located over said NFET channel; and a tensile stress liner located on said NFET gate line, said NFET source region, and said NFET drain region, wherein said tensile stress liner produces a tensile longitudinal strain in said NFET channel and a secondary tensile transverse stress in said PFET channel.