Patent ID: 8817146

Claim:
An imaging device, comprising: a pixel unit including a plurality of pixels, each of which outputs a pixel signal corresponding to a quantity of incident light, the pixels being arranged in a two-dimensional matrix form; m digital signal output circuits (m is a natural number larger than 1), each of which is arranged for a column of the pixel unit or for every two or more columns, receives the pixel signal output from the pixel of the corresponding column, and outputs an n-bit digital signal (n is a natural number equal to or more than 1) corresponding to a level of the input pixel signal; m latch circuits, each of which is arranged to correspond to the digital signal output circuit, and includes n latch unit, the latch units receiving bit signals of the n-bit digital signal output from the corresponding digital signal output circuit at input terminals of the latch units, holding the bit signals of the n-bit digital signal, and outputting the bit signals of the n-bit digital signal to output terminals of the latch units; n horizontal signal lines through which the bit signals of the n-bit signal held in the n latch units are output; and n×(m−1) switches, each of which is arranged between the every two neighboring latch units among the n×m latch units that hold the bit signals being output through the n horizontal signal lines, each of the every two neighboring latch units holding the bit signals corresponding to the pixel signals output from the pixels that are arranged in a same line of the pixel unit, wherein each of the n×(m−1) switches is capable of switching the bit signal that is input at the input terminal of a first neighboring latch unit, from a first bit signal that is output from the digital signal output circuit corresponding to the latch circuit including the first neighboring latch unit, to a second bit signal that is output from the output terminal of a second neighboring latch unit, and then transferring the second bit signal that is output from the output terminal of the second neighboring latch unit, n×(m−2) latch units are arranged as that the input terminal and the output terminal of each of the n×(m−2) latch units are connected with the output terminal and the input terminal of the other latch units via each of the n×(m−1) switches, among the n×m latch units included in the m latch circuits, both of the bit signals being output from the corresponding digital signal output circuits and the bit signals corresponding to the pixel signals output from the pixels that are arranged in the same line of the pixel unit are capable of being held by the n×(m−2) latch units, and each of the n×(m−2) latch units is capable of inputting the bit signals being held by the latch units that are arranged at a side of the input terminals of each of the n×(m−2) latch units, at the input terminals subsequently, and outputting the bit signals to the latch units that are arranged at a side of the output terminals of each of the n×(m−2) latch units subsequently.