Patent ID: 7285829

Claim:
An NMOS transistor comprising: a dielectric layer above a substrate; a trench in said dielectric layer, wherein the bottom of said trench is directly above said substrate; a gate dielectric layer in said trench, wherein a first portion of said gate dielectric layer is adjacent to a first sidewall of said trench, wherein a second portion of said gate dielectric layer is adjacent to a second sidewall of said trench, and wherein a third portion of said gate dielectric layer is on the bottom of said trench; a gate electrode in said trench, wherein said gate electrode is directly between said first and said second portions of said gate dielectric layer, wherein said gate electrode is comprised of a central portion and a pair of outer portions, wherein said outer portions are each comprised of a sidewall region and an extension region, wherein said central portion is directly adjacent to said sidewall region and directly above said extension region of each of said outer portions, wherein the bottom surfaces of said central portion and said pair of outer portions are directly on said third portion of said gate dielectric layer, and wherein the workfunction of said pair of outer portions is lower than the workfunction of said central portion; and a pair of n type source/drain regions in said substrate on opposite sides of said pair of outer portions of said gate electrode.