Patent ID: 7094649

Claim:
A method for forming a mask read only memory structure, comprising: providing a substrate having a memory region and a periphery region; performing a threshold voltage implantation to adjust a threshold voltage of the memory region; forming a plurality of gate structures on the substrate, wherein the gate structure includes a gate oxide layer on the substrate and a gate conductive layer on the gate oxide layer; forming spacers on sidewalls of the gate structures; forming a plurality of source/drain regions in the substrate along both sides of the spacers; applying a first patterned photoresist layer with a first code pattern to the substrate and then performing a first code implantation to the memory region using the first patterned photoresist layer with the first code pattern as a mask; applying a second patterned photoresist layer with a second code pattern to the substrate and then performing a second code implantation to the memory region using the second patterned photoresist layer with the second code pattern as a mask; forming an interlayer over the substrate; and forming at least a contact plug in the interlayer.