Patent ID: 6990294

Claim:
An optical network system with quality control function in the optical network system wherein a signal to be transmitted is converted to an optical signal of a prescribed wavelength and transmitted over an optical transmission path by a transmit-end wavelength convener; and said optical signal from said optical transmission path is received and wavelength-converted by a receive-end wavelength converter, for regenerating the signal to be transmitted, the optical network system comprising: said transmit-end wavelength converter for a transmit end with a first transponder further comprising: an optical signal input unit for inputting an optical signal to be transmitted; a test signal generator circuit ultimately connected to said optical signal input unit for generating a test signal for testing optical transmission quality, said test signal generator circuit further comprising: a clock generator for generating a clock signal indicative of a bit rate to be added to the test signal; an ‘all 1s and all 0s’ generator circuit for generating ‘all 1s and all 0s’ signals; and a scrambler circuit connected to said ‘all 1s and all 0s’ generator circuit for scrambling the ‘all 1s and all 0s’ signals to generate a scrambled test signal; an insertion circuit connected to said optical signal input unit and said test signal generator circuit for outputting an output signal by selectively inserting the test signal from said test signal generator circuit into the transmission path formed between the transmit end and a receive end; and a converter connected to said insertion circuit for converting the output signal of said insertion circuit to a predetermined optical wavelength; and said receive-end wavelength converter at the receive end with a second transponder further comprising: an extraction circuit for selectively extracting the test signal in the optical signal from said transmission path; a test comparison circuit connected to said extraction circuit for determining the optical transmission quality based on the test signal extracted by said extraction circuit, said test comparison circuit further comprising: a clock extraction circuit for extracting the clock signal from the test signal that is received at the receive end in order to synchronize with the bit rate of the selected test signal; a descrambler circuit connected to said clock extraction circuit for using the clock component for descrambling the scrambled test signal to generate descrambled signals; a selector circuit connected to said descrambler unit for selecting one of the descrambled signals from said descrambler circuit; and a comparison test circuit connected to said selector circuit for performing a test signal comparison and a bit error count/computation of the selected descrambled signal.