Patent ID: 8237283

Claim:
A structure for reducing electromigration cracking and extrusion effects in semiconductor devices, comprising: a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer, the second dielectric layer comprising a porous, low-K material; a void formed in the second dielectric layer, with a bottom of the void stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer; a pore-sealing liner material formed on sidewall surfaces of the second dielectric layer that define the void; and a sealing dielectric material formed over the second dielectric layer, the sealing dielectric material configured to pinch off upper portions of the void while maintaining lower portions of the void; wherein the void is localized around an anode end of the first metal line so as to prevent extrusions from the anode end from shorting to an adjacent second metal line formed in the first dielectric layer.