Patent ID: 7728331

Claim:
A thin film transistor array panel, comprising: a substrate; a gate line and a gate-layer signal transmitting line of a gate driving circuit portion formed on the substrate; a gate insulating layer formed on the gate line and the gate-layer signal transmitting line and having a first contact hole exposing a portion of the gate-layer signal transmitting line; a semiconductor layer formed on the gate insulating layer; a data line including a source electrode, and a drain electrode formed on the gate insulating layer and the semiconductor layer; a data-layer signal transmitting line of the gate driving circuit portion formed on the gate insulating layer and connected to the gate-layer signal transmitting line through the first contact hole; a pixel electrode connected to the drain electrode; and a passivation layer formed on the data line, the drain electrode, and the data-layer signal transmitting line of the driving circuit portion, wherein the data line, the drain electrode, and the data-layer signal transmitting line have a triple-layered structure including a lower layer, an intermediate layer, and an upper layer, and the lower layer is made of a same layer as the pixel electrode.