Patent ID: 8373273

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a first interlayer insulating film on a semiconductor substrate by using p-SiCOH; forming a trench in the first interlayer insulating film; forming a conductive film to fill the trench; forming a damascene interconnect by removing a portion of the conductive film such that a top surface of the first interlayer insulating film is exposed; forming a second interlayer insulating film by removing a portion of the exposed top surface of the first interlayer insulating film such that a top surface of the second interlayer insulating film is lower than a top surface of the damascene interconnect; forming a first capping film along the top surface of the second interlayer insulating film and a side surface and a top surface of a protruding region of the damascene interconnect; forming a planarization film on the first capping film; forming a planarization pattern and a first capping pattern by removing a portion of the planarization film and a portion of the first capping film, which is formed on the top surface of the protruding region of the damascene interconnect, such that the top surface of the damascene interconnect is exposed; forming a CoWP film on the exposed top surface of the damascene interconnect; removing the planarization pattern; and forming a second capping film on the first capping pattern and the CoWP film.