Patent ID: 7579265

Claim:
A method for manufacturing a recess gate in a semiconductor device, the method comprising: forming a device isolation structure on a substrate to define an active region; forming a first hard mask pattern and a second hard mask pattern over the substrate; forming an island-shaped mask pattern over the second hard mask pattern to cover facing ends of neighboring active regions and the device isolation structure between the neighboring active regions: etching the first hard mask using the island-shaped mask pattern and the second hard mask pattern as an etch barrier; forming a recess pattern in the active region through an etching process using the first and second hard mask patterns as an etch barrier to selectively expose at least a portion of the active region; removing the first and second hard mask patterns; forming a gate insulating layer over the substrate; and forming a gate electrode over the gate insulating layer to cover at least the recess pattern, wherein the second hard mask has a straight line pattern with spacing therebetween over the first hard mask.