Patent ID: 8918786

Claim:
A multiprocessing system, comprising: a process execution circuit configured to execute a plurality of processes concurrently and to issue requests to access a shared resource of the multiprocessing system from the plurality of processes; a shared access circuit coupled to the shared resource and configured to arbitrate conflicts arising from handling concurrent requests to access the shared resource by sequencing conflicting requests; a simulating access circuit coupled between the process execution circuit and the shared access circuit for receiving requests from the plurality of processes and comprising at least a first buffer for buffering the requests, wherein the simulating access circuit is configured to: send the requests to the shared access circuit for handling; generate stall signals to the process execution circuit to stall at least one of the plurality of processes at respective simulated stall time points selected as a predetermined function based on an access speed model or a history of requests from the at least one process, wherein the stall signals are generated independent of the actual handling of the requests from the at least one process by the shared access circuit and irrespective of whether the stalling is made necessary by sequencing conflicting requests between the requests from the at least one process and other requests, and wherein the stall signals are further generated when the first buffer is full and additional requests are received by the simulating access circuit or when a response to a request from the at least one process is not yet available.