Patent ID: 6977421

Claim:
A semiconductor construction, comprising: a semiconductor substrate; a first transistor structure supported by the semiconductor substrate; the first transistor structure comprising a first gate stack over the semiconductor substrate, and comprising a pair of first source/drain regions on opposing sides of the first gate stack and within the substrate; the first source/drain regions being majority-doped to a first type which is either p-type or n-type, and the first gate stack comprising a semiconductor layer which is majority doped to the first type; a second transistor structure supported by the semiconductor substrate; the second transistor structure comprising a second gate stack over the semiconductor substrate, and comprising a pair of second source/drain regions on opposing sides of the second gate stack and within the substrate; the second source/drain regions being majority-doped to the first type, and the second gate stack comprising a semiconductor layer which is majority doped to the first type; and a third gate stack over the semiconductor substrate; the third gate stack extending over a portion of one of the first source/drain regions and over a portion of one of the second source/drain regions; the third gate stack comprising a semiconductor layer which is majority doped to a second type which is the other of p-type or n-type relative to the first type.