Patent ID: 8373216

Claim:
A semiconductor device comprising, on a semiconductor substrate: a first memory cell forming region in which a plurality of memory cells are formed in an array; and a first feeding region, wherein the memory cell formed in the first memory cell forming region includes: a first gate insulating film formed of a first insulating film formed on the semiconductor substrate; a select gate electrode formed of a first conductive film formed on the first gate insulating film; a sixth insulating film formed on the select gate electrode; a cap insulating film formed of a second insulating film formed on the sixth insulating film; a memory gate electrode formed of a second conductive film formed in a sidewall shape on one side surface of a stacked film of the select gate electrode, the sixth insulating film, and the cap insulating film; and a second gate insulating film formed between the stacked film of the select gate electrode, the sixth insulating film, and the cap insulating film and the memory gate electrode, and formed between the memory gate electrode and the semiconductor substrate, wherein, in the first feeding region, the select gate electrode, from which the sixth insulating film and the cap insulating film are removed, is provided, and wherein a pad electrode formed of the second conductive film is formed by running on a partial region of the select gate electrode, from which the sixth insulating film and the cap insulating film are removed, via the second gate insulating film, the pad electrode being continuous with the memory gate electrode formed in the first memory cell forming region.