Patent ID: 8743882

Claim:
A packet processor for a network device, the packet processor comprising: a plurality of ports including at least one incoming port and at least one outgoing port, the at least one incoming port configured to receive a data packet including a header portion and a data portion; and a header altering device, the header altering device comprising: a plurality of packet processing pipeline stages configured to process the data packet by modifying a data structure of the header portion while the data portion is stored in memory, each of the plurality of packet processing pipeline stages in the header altering device being assigned one or more tasks associated with modifying the data structure, the plurality of packet processing pipeline stages further configured to: determine whether to extract first header information from the data structure and selectively extract the first header information, selectively generate a modified header portion of the data packet using the extracted first header information, and retrieve the data portion from the memory and combine the data portion with the modified header portion.