Patent ID: 7669101

Claim:
A method of generating distributable algorithms related to testing of an electronic circuit, the method comprising: accessing a circuit testing algorithm having a sequence of (N+1) or more tasks that are performed sequentially when the algorithm is performed by a single processor, wherein N is a positive integer and a task M is the starting point in the sequence of tasks; starting at task M in the sequence of tasks, creating a rolling window of independent tasks comprising N tasks from task M to task (M+N−1) by not using the results of the N tasks in the performance of any of the other of the N tasks; delaying the performance of task (M+N) and any subsequent tasks until the reporting of the results for at least task M and any earlier tasks are available; and creating a next rolling window of independent tasks comprising N tasks from task (M+1) to task (M+N) after completion of the Mth task.