Patent ID: 7801261

Claim:
An apparatus for clock recovery from incoming data streams containing embedded reference clock values, comprising: clock reference storage circuit for storing clock reference values received from the incoming data stream connected to, an output of said digital comparator, a second input of which is connected to, a local clock storage circuit for storing locally generated clock values provided by a, a counter which receives a clock signal from a controlled clock source circuit controlled by the output of said digital comparator, wherein said controlled clock source circuit consists of a controllable digital fractional divider receiving a control value from said digital comparator and a clock input from a digital clock synthesizer driven by a fixed oscillator, and wherein said digital fractional divider is a digitally implemented fractional divider for providing an output signal having a frequency that is a fraction of a frequency of an input clock signal, the divider comprising: a programmable counter to count to a value K equal to an integer part of the fraction denominator when a count-control signal has a first state, and count to a value K+1 when the count-control signal has a second state, and to generate the output signal and a terminal count signal that is a function of the count value; and a fractional accumulator to receive the terminal count signal, a feedback of the accumulator output, and a fractional part of the fraction denominator, and produce the count-control signal having the second state upon occurrence of an addition overflow.