Patent ID: 7532498

Claim:
A device comprising: a bitline; a memory cell coupled to the bitline; a reference bitline coupled in a reference cell; an integrator to integrate a signal of the bitline, wherein the integrator is operable to integrate a signal of the memory cell propagated by the bitline and operable to integrate a difference signal representative of the level of a signal of the bitline defined relative to that of the reference bitline; a sampler to obtain a sample of a signal of an output of the integrator following a first duration; a reference sampler operable to obtain a sample of the signal of the reference bitline at the end of the first duration; a comparator operable to compare the sample of the sampler to the signal of the integrator's output and operable to signal an end for a second duration when the level of the signal of the reference bitline reaches the level of the sample of the sampler; a self-timer circuit to influence a duration of an integration of the integrator dependent upon a reference signal; the self-timer circuit further comprising: a threshold source; and a threshold comparator operable to signal the end of at least one of the first and second durations dependent upon the level of the signal of the reference bitline and a level of a signal of the threshold source; a latch operable to establish a data value dependent upon the output of the comparator, wherein the self-timer circuit is operable to establish the end for the second duration dependent upon the level of the signal of the reference bitline and enable the latch at the end of the second duration.