Patent ID: 7960798

Claim:
A semiconductor structure having a stressed device channel comprising: at least one field effect transistor located on a surface of a semiconductor substrate, said semiconductor substrate including a mesa portion and a recessed portion, wherein each of said at least one field effect transistor includes a gate structure on a mesa portion of the semiconductor substrate; and a multilayer embedded stressor having a graded dopant profile present in the recessed portion of the semiconductor substrate that is adjacent to the mesa portion of the semiconductor substrate, said multilayer embedded stressor comprising a first semiconductor layer that is conformal and is located in direct contact with a base surface of the recessed portion of the semiconductor substrate, and a sidewall surface of the mesa portion of the semiconductor substrate, and a second semiconductor layer present on the first semiconductor layer having an upper surface that is coplanar with the upper surface of the mesa portion of the semiconductor substrate, said second semiconductor layer having a greater dopant concentration than the first semiconductor layer, wherein said multilayer embedded stressor induces a strain upon a channel region of said at least one field effect transistor.