Patent ID: 6841832

Claim:
A wafer comprising: a base layer; an active layer formed on the base layer; a gate dielectric layer formed on the active layer; a conductive layer formed on the gate dielectric layer; and a plurality of isolation regions formed in said wafer, said wafer being divided into a plurality of first portions, second portions, and third portions; said first portions comprise gate dielectric capacitors, said gate dielectric capacitors comprise a first electrode layer, an insulating layer, and a second electrode layer; wherein the first electrode layer is formed from said active layer, the insulating layer is formed from said gate dielectric layer, and the second electrode layer is formed from said conductive layer; said second portions comprise first dummy structures, said first dummy structures comprise a first electrode layer and an insulating layer; wherein the first electrode layer of the first dummy structures is formed from said active layer and the insulating layer of the first dummy structures is formed from said gate dielectric layer, wherein said second portion does not contain said conductive layer; and said third portions comprise second dummy structures, said second dummy structures comprise an insulating layer and a second electrode layer, wherein the insulating layer of the second dummy structures is formed from an isolation region and the second electrode layer of the second dummy structures is formed from said conductive layer, wherein said third portion does not contain said active layer.