Patent ID: 7251764

Claim:
A serializer/deserializer (SERDES) circuit having built-in self-test (BIST) capabilities that is configured to perform jitter sensitivity characterization, comprising: a clock and data recovery (CDR) circuit coupled to said SERDES circuit that generates recovered clock and data from an incoming serial data stream; a deserializer (DES) circuit connected to said CDR circuit to output corresponding data (Parallel Data Out) and clock (DES clock) in a parallel format; a programmable pattern generator generating BIST patterns; a serializer (SER) circuit that receives either the BIST patterns or input data (Parallel Data In) in a parallel format on a data input of the serializer circuit and a serializer clock (SER clock) on a clock input of the serializer circuit to generate a serial data stream; a delay perturbation circuit for adding a perturbation delay to said serial data stream to produce a perturbed serial data stream; a multiplexor circuit to output either the serial data stream or the perturbed serial data stream in a loop back to the CDR circuit; a control logic circuit block coupled to said deserializer circuit to detect a start-of-frame pattern using a dedicated signal (FD) and coupled to the programmable pattern generator and the perturbation circuit.