Patent ID: 7820480

Claim:
A process for the manufacture of a package ( 38 ) to encase encasing at least one semiconductor device ( 28 ) comprising the steps of: by patterning a first side ( 12 ) of an electrically conductive metal substrate ( 10 ), forming an array of lands ( 14 ) separated by channels ( 16 ); disposing a first molding compound ( 18 ) within said channels ( 16 ); subsequently, by patterning a second side of said electrically conductive metal substrate, forming second patterning a second side ( 22 ) of said electrically conductive substrate ( 10 ) to form at least a first conductive portion and a second conductive portion recessed with respect to the first conductive portion, the first conductive portion including an array of chip attach sites ( 24 ), and the second conductive portion including routing circuits ( 26 ) the routing circuits electrically interconnecting said array of lands ( 14 ) and said array of chip attach sites ( 24 ); removing metal between the routing circuits, thereby exposing a portion of a surface of the molding compound; directly electrically interconnecting ( 30 ) input/output pads on said at least one semiconductor devices ( 28 ) to chip attach site members ( 24 ) of said array of chip attach sites ( 24 ); and encapsulating said at least one semiconductor device ( 28 ), said array of chip attach sites ( 24 ) and said routing circuits ( 26 ) with a second molding compound ( 36 ).