Patent ID: 7990173

Claim:
A circuit for handling single event upsets in a circuit arrangement, comprising: first, second, and third digital clock manager circuits; a plurality of counters having inputs coupled to outputs of the first, second, and third digital clock managers, respectively, each counter outputting a respective counter value indicating a number of transitions of a signal output from the respective digital clock manager circuit; and a reset controller coupled to the outputs of the counters, wherein the reset controller is configured to: determine an expected value of the counters after a pre-determined number of clock cycles, the expected value being equal to the pre-determined number of clock cycles; in response to the counter value of one of the counters being less than the expected value, trigger a reset of the digital clock manager circuit coupled to the input of the one of the counters; and in response to the counter value of one of the counters being greater than the expected value, continue operation without triggering a reset of the digital clock manager circuit coupled to the input of the one of the counters.