Patent ID: 7386433

Claim:
A method for speeding up an iterative process that simulates and corrects a layout of a target cell within an integrated circuit, the method comprising: determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution, wherein the target cell is similar to a preceding cell if (1) a layout of a target cell matches a layout of a preceding cell, but an environment surrounding the target cell differs from an environment surrounding the preceding cell; (2) the layout of the target cell matches the layout of the preceding cell, and the environment surrounding the target cell matches the environment surrounding the preceding cell; or (3) if the layout of the target cell differs from the layout of the preceding cell by less than a pre-specified amount; and if the target cell is similar to the preceding cell, using the previously calculated solution for the preceding cell as an initial input to the iterative process for the target cell, wherein the iterative process involves one or more repetitions of simulating a current solution for the target cell to produce a current simulated layout, wherein if the current simulated layout differs from the desired layout by less than a pre-specified amount, accepting the current solution as a final solution for the target cell, otherwise, correcting the current solution to compensate for differences between the current simulated layout and the desired layout; otherwise using the layout of the target cell as the initial input to the iterative process for the target cell; wherein the difference between the final solution and a desired layout for the target cell is less than a pre-specified tolerance.