Patent ID: 8176255

Claim:
A system, comprising: a processor core; a first cache coupled to the core and comprising at least one cache way dedicated to the core, said cache way comprising multiple, cache lines; a second cache coupled to the core, said second cache comprises a different level than said first cache; and a cache controller coupled to the first cache and the second cache; wherein, upon receiving a data request from the core, the cache controller determines whether said first cache has a predetermined amount of invalid cache lines; wherein, if the first cache has said predetermined amount of invalid cache lines not located in said at least one cache way dedicated to the core, the cache controller evicts an invalid cache line not located in said at least one cache way dedicated to the core and replaces the evicted, invalid cache line with data corresponding to said data request; wherein, if the first cache does not have said predetermined amount of invalid cache lines, the cache controller is adapted to allocates space in the first cache for new data, the space allocable in said at least one cache way dedicated to the core; wherein, if the first cache does not have the predetermined amount of invalid cache lines, the cache controller is configured to searches the at least one way in the first cache for a line associated with a hint bit that indicates that the line is not associated with another line stored in the second cache; and wherein, if a valid line is evicted from the second cache, the cache controller provides the first cache with a hint transaction signal that causes a line in the first cache corresponding to the valid, evicted line to indicate that the valid, evicted line is not stored in the second cache.