Patent ID: 8116114

Claim:
A semiconductor memory, comprising: a plurality of data terminals; a plurality of complementary bit line pairs extending along a first direction, arranged toward a second direction orthogonal to the first direction, and corresponding to the respective data terminals; a plurality of memory cells coupled to respective bit lines of the bit line pairs; a plurality of access control circuits each having the bit line pairs wired therein and operating when the memory cells are accessed; a contact arranged between the access control circuits adjacent to each other and supplying a voltage to nodes in the access control circuits; a plurality of data lines provided corresponding respectively to the respective data terminals and coupled in common to the access control circuits corresponding to the data terminals; and a data swap circuit which is arranged between the data lines and the data terminals and swapping connections between a pair of the data terminals and a pair of the data lines corresponding to the pair of the data terminals, wherein: at least a pair of the access control circuits adjacent to each other is assigned a same number of a data terminal, and is assigned different addresses; and during a test mode, the data swap circuit prohibits swapping of the connections when the memory cells corresponding to one of the access control circuits of a pair are accessed, and swaps the connections when the memory cells corresponding to the other one of the access control circuits of the pair are accessed.