Patent ID: 8536007

Claim:
A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising: forming a charge storage layer over the substrate in the NVM region and the logic region; forming a first conductive layer over the charge storage layer in the NVM region and the logic region; patterning the first conductive layer and the charge storage layer to form a control gate in the NVM region and to remove the first conductive layer and the charge storage layer from the logic region; forming a first dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region; forming a sacrificial layer over the first dielectric layer in the NVM region and the logic region; planarizing the sacrificial layer, wherein the first dielectric layer comprises a sidewall portion located along a sidewall of the control gate, between the control gate and the sacrificial layer; forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the first sacrificial layer and the control gate in the NVM region and a second masking portion over the first sacrificial layer in the logic region, wherein: the first masking portion defines a select gate location laterally adjacent the control gate in the NVM region; and the second masking portion defines a logic gate location in the logic region; using the patterned masking layer to remove exposed portions of the sacrificial layer, wherein a first portion of the sacrificial layer remains at the select gate location and a second portion of the sacrificial layer remains at the logic gate location; forming a second dielectric layer in the NVM region and the logic region, wherein the second dielectric layer is formed over the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer; planarizing the second dielectric layer to expose the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer; removing the first portion of the sacrificial layer to result in a first opening at the select gate location and the second portion of the sacrificial layer to result in a second opening at the logic gate location; forming a gate dielectric layer over the second dielectric layer and within the first and second openings; and forming a select gate within the first opening and a logic gate within the second opening.