Patent ID: 8624328

Claim:
A semiconductor device, comprising: a semiconductor substrate; a multi-layered wiring structure which is formed over said semiconductor substrate and in which a plurality of wiring layers, each of which comprises a wiring and an insulating layer, are laminated; and a capacitive element comprising: a lower electrode; a capacitor insulating layer; and an upper electrode, the capacitive element being embedded in said multi-layered wiring structure, wherein at least two or more wiring layers of said plurality of wiring layers are provided between a lower capacitor wiring connected to said lower electrode and an upper capacitor wiring connected to said upper electrode, and wherein each of said at least two or more wiring layers comprises a via, said via being connected to said wiring formed in each of said at least two or more wiring layers and being connected to another wiring formed in another wiring layer located below each of said at least two or more wiring layers; another wiring, said another wiring being provided in a same wiring layer as the lower capacitor wiring, wherein the another wiring has a thickness equal to that of the lower capacitor wiring, in a normal direction of the semiconductor substrate, and wherein the lower capacitor wiring and the another wiring have a same layer structure; a first lower wiring formed under the lower capacitor wiring and a second lower wiring formed under the another wiring; and a first barrier metal layer covering a bottom surface of the first lower wiring and a second barrier metal layer covering a bottom surface of the second lower wiring, wherein the first lower wiring is connected to the first barrier metal layer and the second lower wiring is connected to the second barrier metal layer.