Patent ID: 7651935

Claim:
A process of forming an electronic device comprising: providing a workpiece including a first active region and a second active region; forming a gate dielectric layer over the first active region and the second active region; forming a first layer over the first and second active regions, wherein the first layer has a first work function; forming a second layer over the first layer and the first and second active regions, wherein the second layer has a second work function; patterning the first and second layers, wherein after patterning the first and second layers: within the first active region, the first and second layers remain over the first active region; and within the second active region, the first and second layers are removed and the gate dielectric layer is exposed; forming a third layer over the first and second active regions after patterning the first and second layers; and patterning the third layer, wherein after pattering the third layer: a first gate electrode overlies the first active region, includes portions of the first and second layers, and has an effective work function closer in value to the second work function than the first work function; and a second gate electrode overlies the second active region and includes a remaining portion of the third layer.