Patent ID: 8530954

Claim:
A non-volatile memory device comprising: a channel region of a substrate and source/drain regions at surface portions of the substrate adjacent to the channel region; a tunnel insulating layer on the channel region and extending over the source/drain regions; a charge-trapping layer pattern on the tunnel insulating layer over the channel region; a first blocking layer pattern on the charge-trapping layer pattern; second blocking layer patterns on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern and extending over the tunnel insulating layer over the source/drain regions and configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern, wherein the charge-trapping layer pattern comprises a charge-trapping material and wherein the second blocking layer patterns comprise an oxide of the charge-trapping material such that a thin layer of the charge-trapping material extends over the source/drain regions and underlies the second blocking layer patterns; and a gate electrode on the first blocking layer pattern.