Patent ID: 8738976

Claim:
A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus comprising: a memory bus coupled to the subject memory; a mirror memory coupled to the memory bus so as to receive the same data as data to be written into the subject memory, the received data being written into the mirror memory; an address analyzer configured to analyze an address related to the data written into and read from the subject memory and acquire the address analyzed; a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address; a comparator configured to compare data read from the subject memory and data read from the mirror memory; an error detector configured to detect a data error on the basis of a result of the comparison; an address converter configured to convert a logical address acquired by the address analyzer to a physical address in the subject memory; and a command analyzer configured to analyze a command instructed to the subject memory on the basis of a command table of the memory bus and acquire a type of the command, wherein the mirror memory controller controls to write the received data into the mirror memory and to read the data from the mirror memory on the basis of the physical address and the acquired command type, and the error detector detects a physical address related to the detected data error on the basis of a result acquired by the comparison.