Patent ID: 7171445

Claim:
A multiprocessor system comprising: a first microprocessor having one or more interfacing logics including a first interfacing logic, the first microprocessor being clocked by a first system clock; a memory controller connected to the first interfacing logic through at least a first bus for transmitting at least a first signal from the memory controller to the first interfacing logic, the memory controller being clocked by a second system clock; and a second microprocessor connected to the memory controller through at least a second bus for transmitting at least a second signal from the memory controller to the second processor, the second bus requiring a first period of time more to transmit the second signal than what the first bus requires to transmit the first signal, the first interfacing logic delaying the first signal by the first period of time so that the first and the second signals are respectively received by the first and the second microprocessors substantially at the same time.