Patent ID: 7875495

Claim:
A method of making a semiconductor device, comprising: providing a substrate having a conductive layer; disposing a solder resist film laminate layer over the substrate and conductive layer; forming an opening in the solder resist film laminate layer to expose the conductive layer; curing the solder resist film laminate layer after the opening is formed; forming an under bump metallization (UBM) layer over the conductive layer; forming a plurality of first solder bumps over the UBM layer to promote reflow of the first solder bumps at a eutectic temperature; forming a plurality of standoff solder bumps on the solder resist film laminate layer around a perimeter of the substrate, the solder resist film laminate layer preventing reflow of the standoff solder bumps at the eutectic temperature; providing a semiconductor die; disposing a plurality of second solder bumps between the semiconductor die and the first solder bumps of the substrate; and reflowing the second solder bumps to electrically connect the semiconductor die to the first solder bumps of the substrate, wherein after reflow of the second solder bumps the standoff solder bumps have a height 70-90% of a height of the second solder bumps prior to reflow to maintain a predetermined separation between the semiconductor die and substrate.