Patent ID: 7493537

Claim:
A test circuit comprising: A. a tap controller having a test clock input lead, a test mode select input lead, and state output leads; B. An instruction register having a test data input lead, a test data output lead, a mode output lead and control bus output leads; C. boundary scan register circuitry having a test data input lead, a test data output lead, and a mode input lead connected to the respective instruction register test data input, test data output, and mode output leads, having state input leads connected to the state output leads of the tap controller, and having a state clock input lead; and D. capture test strobe circuitry having a test clock input lead connected to the test clock input lead of the tap controller, state input leads connected to the state output leads of the tap controller, an enable input lead connected to the control bus output leads of the instruction register, and a state clock output lead connected to the state clock input lead of the boundary scan register circuitry.