Patent ID: 7569894

Claim:
A semiconductor device comprising: a plurality of PMOS transistors formed on a semiconductor substrate; a plurality of NMOS transistors formed on said semiconductor substrate; and a gate structure formed on said semiconductor substrate between an adjacent of said plurality of NMOS transistors to extend in a second direction perpendicular to a first direction over an N-type diffusion layer, wherein said plurality of PMOS transistors are surrounded and electrically isolated from each other by a device isolation structure formed in said semiconductor substrate, wherein said plurality of NMOS transistors are adjacent to each other and surrounded by said device isolation structure in said first direction such that said N-type diffusion layer of said plurality of NMOS transistors extends continuously with respect to said plurality of NMOS transistors in said first direction, and wherein one of said plurality of PMOS transistors and one of said plurality of NMOS transistors share a gate electrode.