Patent ID: 7810005

Claim:
An automated test equipment system comprising: a first test component for generating a first test signal for testing an integrated circuit, said first test signal generated in response to receiving a first portion of functional data for testing said integrated circuit, wherein said first test component is operable to correct timing errors in said first test signal using data from said first portion of said functional data: a second test component for generating a second test signal for testing said integrated circuit, said second test signal generated in response to receiving a second portion of said functional data for testing said integrated circuit, wherein said second test component is operable to correct timing errors in said second test signal using data from said second portion of said functional data; and an interface coupled to said second test component and for enabling said second test component to access a select sub-portion of said first portion of said functional data; and wherein said second test component is further operable to correct timing errors in said second test signal using said select sub-portion supplied to said second test component via said interface, said select sub-portion processed before said second portion of said functional data.