Patent ID: 7176825

Claim:
A data-converting circuit comprising: a data combining circuit for outputting 1 st through (2 n −1) th intermediate data bits by combining binary data bits corresponding to “1”s in n-bit binary data corresponding to a decimal number; a thermometer code generating circuit for generating 1 st through (2 n −1) th bits of thermometer code data each activated as “1” when a corresponding intermediate data bit among the 1 st through (2 n −1) th intermediate data bits is activated, wherein each of the 1 st through (2 n −1) th bits of thermometer code data is also activated as “1” by the 1 st through (2 n −1) th intermediate data bits that are activated by binary data having a value greater than binary data activating the corresponding intermediate data bit among the 1 st through (2 n −1) th intermediate data bits; and a reset circuit for periodically resetting the 1 st through (2 n −1) th bits of thermometer code data to “0” in response to an external clock signal.