Patent ID: 7858461

Claim:
A method of fabricating a semiconductor device, the method comprising the steps of: forming a plurality of trenches in parallel in an active region of a semiconductor substrate in a direction; forming a recessed gate to cross the trenches in the semiconductor substrate, wherein regions of the trenches overlapping with the recessed gate are filled with a recessed gate material; forming source/drain regions on an upper surface of the semiconductor substrate and in bottoms of the trenches on both sides of the recessed gate; forming an interlayer insulating layer over the semiconductor substrate and the recessed gate; etching the interlayer insulating layer to form contact holes through which the source/drain regions in the trench bottoms and the source/drain regions on the upper surface of the semiconductor substrate are exposed on both sides of the recessed gate; forming contact plugs by filling the contact holes; and forming a metal line, connected to the contact plugs, in parallel to the recessed gate.