Patent ID: 7774662

Claim:
An electronic circuit, comprising: at least one scan chain of latches, for providing a test stimuli pattern to an associated combinatorial logic circuit; and a mechanism to allow a data flow in said scan chain to be reversed in direction so that a critical stimuli pattern can selectively be restored and thereby repeated by at least a portion of said at least one scan chain, wherein each said latch comprises a master flipflop and a slave flipflop and said mechanism to reverse data flow comprises a multiplexer interconnected between said master flipflop and said slave flipflop, and wherein said multiplexer between said master flipflop and said slave flipflop is interconnected such that said slave flipflop receives, as based on a control signal to said multiplexer, an input signal from a selected one of: an output from said master flipflop, thereby permitting said test stimuli pattern to progress; and an output from a second master flipflop from a next subsequent stage in said scan chain, thereby restoring said critical stimuli pattern for a repeat execution through said slave flipflop.