Patent ID: 8772183

Claim:
A method of forming an integrated circuit, the method comprising: providing a first material layer; forming a second material layer on the first material layer; forming a patterned mask layer having a plurality of first features with a first pitch P 1 on the second material layer; patterning the second material layer by using the patterned mask layer as a mask to form the first features in the second material layer and expose a portion of a top surface of the first material layer; trimming the patterned mask layer after patterning the second material layer to form a trimmed patterned mask layer; introducing a plurality of dopants into the second material layer not covered by the trimmed patterned mask layer to form doped regions with a second pitch P 2 , wherein the second pitch P 2 is smaller than the first pitch P 1 ; removing the trimmed patterned mask layer to expose un-doped regions in the second material layer; selectively removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions in the second material layer.