Patent ID: 8105890

Claim:
A method of forming a semiconductor structure, the method comprising the steps of: disposing a first layer of semiconductor material; disposing a second layer of semiconductor material adjacent the first layer of semiconductor material; disposing a third layer of semiconductor material adjacent the second layer of semiconductor material; disposing a gate insulator layer over the third layer; disposing a gate electrode layer over the gate insulator layer; forming a pair of trenches through at least the third layer to expose the second layer of semiconductor material for access by an etchant thereto, the pair of trenches disposed on opposite sides of the gate insulator layer and the gate electrode layer; exposing the second layer of semiconductor material to a thermal gaseous chemical etchant, the thermal gaseous etchant laterally and isotropically etching the second layer of semiconductor material so as to form a cavity between the first and third layers of semiconductor material, wherein the second layer of semiconductor material is formed from a different material to the first and third layers of semiconductor material; and depositing a sidewall spacer material to form a sidewall on the gate insulator and the gate electrode, the sidewall spacer material depositing into the cavity.