Patent ID: 7114035

Claim:
A computing system, comprising: a plurality of memory regions each having a different address range and a corresponding class identifier; a range register coupled to receive an address and configured to produce: (i) the class identifier corresponding to the memory region having an address range that includes the received address, or (ii) a default class identifier in the event that none of the memory regions has an address range that includes the received address; a cache comprising a plurality of sets; a replacement management table (RMT) having a plurality of entries, wherein each of the entries corresponds to one of the class identifiers and to one of the sets of the cache, and wherein the entries of the RMT are configured to store data that define the sets of the cache that may be used to store data retrieved from each of the memory regions, and wherein the RMT is coupled to receive the class identifier produced by the range register and configured to produce a tag replacement control indicia dependent on the received class identifier, and wherein the tag replacement control indicia is indicative of the sets of the cache that may be used to store data retrieved from one of the memory regions having the received class identifier; and wherein the cache is coupled to receive data retrieved from one of the memory regions and the tag replacement control indicia, and configured to store the received data in one of the sets of the cache dependent upon the tag replacement control indicia.