Patent ID: 8232655

Claim:
A packaging substrate for mounting a semiconductor chip, said packaging substrate comprising: a core; a front metal interconnect layer containing front metal interconnect components and an insulator material including a topmost front insulator layer and located on and above a top surface of said core; a backside metal interconnect layer containing backside metal interconnect components and said insulator material and located on and below a bottom surface of said core; and a C4 pad filling said opening and comprising, from bottom to top, an insulator-contacting Cu portion including atomic scale voids therein and having a first density that is lower than density of copper in an elemental form that does not have atomic scale voids and contacting one of said front metal interconnect components, a first Cu portion having a second density that is greater than said first density and lower than said density of copper in said elemental form that does not have atomic scale voids and contacting said insulator-contacting Cu portion, a Ni portion contacting said first Cu portion, and a second Cu portion having said second density and contacting said Ni portion, wherein a bottom surface of said insulator-contacting Cu portion contacts an insulator surface.