Patent ID: 7795088

Claim:
A method for manufacturing a memory cell comprising the steps of: providing a substrate having a liner layer and a material layer sequentially formed thereon; forming a patterned mask layer on the substrate; trimming the patterned mask layer; removing a portion of the material layer, a portion of the liner layer and a portion of the substrate to define a plurality of fin structures in the substrate by using the patterned mask layer as a mask; removing the patterned mask layer; forming a plurality of isolation structures among the fin structures and a surface of the isolation structures is lower than a surface of the fin structures; forming a charge trapping structure on the substrate, covering the fin structures; removing a portion of the charge trapping structure to expose the material layer; performing a treatment process to turn the material layer into a protection layer; forming a gate on the substrate and over the protection layer, the charge trapping structure, and the fin structure; and forming a source/drain region in the fin structure exposed by both sides of the gate.