Patent ID: 6930885

Claim:
A densely packed electronic assemblage, comprising: a substrate medium for supporting at least one heat generating component thereon, said at least one heat generating component having a junction temperature T j ; means for reducing said junction temperature T j of said at least one heat generating component, said means for reducing defining a heat removing element thermally associated with said at least one heat generating component and spaced apart therefrom so as to produce an open space nearest to said at least one heat generating component for accommodating high density electrical layouts, said heat removing element comprising a plurality of regularly spaced thermal vias, said plurality of regularly spaced thermal vias being generally round and optimally having a diameter of about 0.022 inches, each one of said plurality of spaced thermal vias being optimally spaced about 0.040 inches apart in a pattern; a thermal conduction path associating said heat removing element with said at least one heat generating component; and a heat sink for absorbing heat from said at least one heat generating component and thereby reducing said junction temperature T j of said at least one heat generating component to a temperature T 1 , wherein T 1 is less than T j , said heat sink being in fluid communication with said means for reducing said junction temperature T j .