Patent ID: 8635578

Claim:
A method implemented in a programmable system for incorporating power reduction into a design for an integrated circuit, the method comprising: receiving a description of a design of at least a portion of the integrated circuit from a storage accessible to the system; identifying from the received description a first flip-flop (FF) in the design, the first FF having an enable condition of a clock signal of the first FF; determining for the first FF at least one of: a stability condition (STC) and an observability don't care condition (ODC); adding to the design description, responsive to the determining for the first FF, at least one of: an ODC controller to strengthen an enable condition of the first FF based on respective ODC and causing the ODC controller to generate an enable signal to the first FF; and, an STC controller to strengthen an enable condition of the first FF based on respective STC and causing the STC controller to generate an enable signal to the first FF; and storing in a memory the updated description of the integrated circuit; wherein strengthening an enable condition ensures that a second FF at a fan-out of the first FF is enabled only when the first FF drives a signal to the second FF.