Patent ID: 7404133

Claim:
A method for error detection and correction using an error detection and correction process comprising: grouping a plurality of data bits into a plurality of error control coding (ECC) symbols; modulating said ECC symbols into a plurality of modulation symbols such that a first predetermined criteria is satisfied for each modulation symbol, the first predetermined criteria specifying that each modulation symbol includes between x and y binary (1) bits in total and between x and y binary (1) bits in total, wherein modulating said ECC symbols into the modulation symbols comprises: ordering the ECC symbols in numerical order from a lowest ECC symbol to a highest ECC symbol; ordering the modulation symbols in numerical order from a lowest modulation symbol to a highest modulation symbol, each modulation symbol satisfying the first predetermined criteria; setting a current ECC symbol to the lowest ECC symbol and setting a current modulation symbol to the lowest modulation symbol; as a predefined entry point of the method, assigning the current ECC symbol to the current modulation symbol; where the current ECC symbol is not the highest ECC symbol, advancing the current ECC symbol to a next ECC symbol within the numerical order in which the ECC symbols have been ordered; advancing the current modulation symbol to a next modulation symbol within the numerical order in which the modulation symbols have been ordered; repeating the method at the predefined entry point; combining a sub-plurality of modulation symbols with at least one parity symbol to form a codeword; performing a first modulation error scan of each of said modulation symbols in said codeword; marking said modulation symbols that fail to comply with the first predetermined criteria; demodulating each of said modulation symbols in said codeword; computing a first error syndrome using each of said demodulated symbols; and, correcting errors using said first error syndrome computed.