Patent ID: 7431795

Claim:
A cluster tool facilitating process integration in manufacture of a gate structure of a field effect transistor having a high-k dielectric, comprising: at least one first etch reactor configured to etch a high-k dielectric material comprising at least one of hafnium dioxide (HfO 2 ), hafnium silicate (HfSiO 2 ), or hafnium silicon oxynitride (HfSiON); at least one second etch reactor configured to etch polysilicon or a metal; at least one ashing reactor; at least one load-lock chamber; a vacuum-tight substrate transfer chamber coupled to the at least one first etch reactor, the at least one second etch reactor, the at least one ashing reactor, and the at least one load-lock chamber; an input/output module, coupled to the at least one load-lock chamber, comprising at least one substrate robot and a metrology tool employing a non-destructive optical measuring technique; a controller; and computer readable media, containing instruction, that when executed by the controller, cause the tool to perform a method in-situ the tool including the steps of: (a) measuring pre-trim dimensions of a patterned photoresist mask of the gate structure to define a trimming process; (b) trimming the patterned photoresist mask to a pre-determined width; (c) forming beneath the patterned photoresist mask a hard mask comprising an anti-reflective coating disposed upon a film comprising α-carbon; (d) fabricating the gate structure using a plasma etch process to form the high-k gate dielectric; and (e) measuring dimensions of the gate structure to adjust the trimming process.