Patent ID: 7617367

Claim:
A memory system comprising: a first memory subsystem comprising: a buffer device having a first port, a second port, and a third port; one or more memory devices coupled to the buffer device via the second port; a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller, the first two-on- one link coupled to the first port of the buffer device, the first memory subsystem configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device and the first two-on-one link, wherein the first two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single; a second buffer device having a first port and a second port; a second two-on-one link having a first connection to the third port of the buffer device and a second connection to the first port of the second buffer device; and one or more second memory devices connected to the second port of the second buffer device, wherein the memory subsystem is further configured to transfer data between at least one memory device of the one or more second memory devices and the memory controller via a path comprising the buffer device, the first two-on-one link, the second buffer device and the second two-on-one link.