Patent ID: 7755956

Claim:
A non-volatile semiconductor memory comprising: a memory cell array including a plurality of banks, redundant blocks, and special blocks, each bank including a plurality of normal blocks, each normal block including a plurality of electrically rewritable memory cells and being a minimum unit which is independently erased, the special block storing management data, the redundant block configured to replace the normal block and being incapable of replacing the special block; a plurality of first defective block memory circuits configured to store data which indicates whether respective normal blocks include a defective memory cell; a plurality of second defective block memory circuits configured to store data which indicates whether respective special blocks include a defective memory cell; a plurality of first logic circuits configured to indicate whether respective banks include a defective memory cell based on the data stored in the plurality of first defective block memory circuits; a second logic circuit configured to indicate whether respective special blocks include a defective memory cell based on the data stored in the second defective block memory circuit; and a third logic circuit configured to indicate whether the memory cell array includes a defective memory cell based on signals outputted from the plurality of first logic circuits and the second logic circuit.