Patent ID: 7977988

Claim:
A delay adjusting method comprising; inputting a reference clock into a first multistage delay circuit constructed by connecting a plurality of delay elements in series; at decision timing synchronized to said reference clock, making a decision on a logic state of each delayed signal sequentially selected from among a plurality of delayed signals obtained by introducing different amounts of delay by passing said reference clock through one or more of said delay elements; detecting from among said delay elements at least two delay elements where a change has occurred in the logic state of said reference clock at said decision timing; determining the number of delay elements that provides a desired delay time, by taking a difference between the numbers of delay elements through which said clock signal has passes until reaching respective ones of said two detected delay elements; inputting an input signal into a second multistage delay circuit constructed from a plurality of delay elements connected in series; multiplying a set value with said determined number of delay elements so as to determine the number of delay elements to be used to pass said input signal therethrough in said second multistage delay circuit; and extracting from said second multistage delay circuit said input signal that has been delayed through said number of delay elements determined to be used.