Patent ID: 7072204

Claim:
A semiconductor memory device, comprising: a memory cell array having first to sixth memory cells arranged in rows and columns, each of said memory cells including a transistor and a capacitor formed with a storage node connected to the transistor and a cell plate provided opposite to the storage node; a first word line formed with a first conductive layer, connected to the transistors of said first and second memory cells neighboring to each other in a row direction, and extending in said row direction; a second word line formed with said first conductive layer, connected to the transistors of said third and fourth memory cells neighboring to each other in said row direction, and extending in said row direction; a third word line formed with said first conductive layer, connected to the transistors of said fifth and sixth memory cells neighboring to each other in said row direction, and extending in said row direction; a first bit line formed with a second conductive layer, connected to the transistors of said first, third and fifth memory cells respectively arranged neighboring to one another in a column direction, and extending in said column direction; a second bit line formed with said second conductive layer, connected to the transistors of said second, fourth and sixth memory cells respectively arranged neighboring to one another in said column direction, and extending in said column direction; and a dummy word line formed with said first conductive layer, arranged between said first word line and said second word line without being connected to the transistors of said first to sixth memory cells, and extending in said row direction, wherein an interval between said first word line and said second word line is larger than an interval between said second word line and said third word line.