Patent ID: 8120987

Claim:
A random access memory circuit comprising: an array of memory cells; an array of global bit lines; a first decoder coupled to the array of memory cells, the first decoder being configurable for receiving an input address and for accessing at least one memory cell in the array of memory cells in response thereto, wherein the first decoder is capable of executing column steering redundancy within the array of memory cells; an output bus which is selectively driven by a subset of global bit lines in the array of global bit lines based on the input address; a master redundancy signal which is activated if column steering redundancy is executed; a plurality of sense amplifiers, wherein, each sense amplifier in the plurality of sense amplifiers is coupled to at least one memory cell in the array of memory cells; each sense amplifier drives one of the global bit lines in the array of global bit lines; and each sense amplifier is configurable for determining a logical state of the memory cells to which it is coupled; a second decoder coupled to the plurality of sense amplifiers, wherein, the second decoder receives the input address; the second decoder selectively activates a first set of sense amplifiers of the plurality of sense amplifiers; and the second decoder selectively activates a second set of sense amplifiers in the plurality of amplifier only when the master redundancy signal is activated.