Patent ID: 8670275

Claim:
A method comprising: performing a first operation on at least one memory cell of a first sub-block of a memory array, the memory array formed on a semiconductor substrate and comprising a plurality of cells associated with a plurality of word lines, the memory array including a plurality of sub-blocks including the first sub-block and a second sub-block, the first sub-block comprising a first memory cell portion of the plurality of memory cells associated with a first word line portion of the plurality of word lines and the second sub-block including a second memory cell portion of the plurality of memory cells associated with a second word line portion of the plurality of word lines, the first and second memory cell portions being independently addressable with respect to each other; suspending the first operation responsive to identifying a second operation directed to at least one memory cell of the second sub-block; and performing the second operation on the at least one memory cell of the second sub-block while the first operation is suspended, wherein the first operation comprises an erase operation and the second operation comprises at least one of a read operation or a program operation.