Patent ID: 7338896

Claim:
A method for fabricating a vertical stack of at least two wafers to create a three dimensional stacked semiconductor device using a through wafer via, the method comprising the steps of: patterning at least one via having sidewalls in a first wafer; forming a partially filled-in portion of the via, wherein the partially filled-in portion comprises a sacrificial material, whereby a portion of the sidewalls is exposed and a portion of the sidewalls is covered by the sacrificial material; forming spacers on the exposed portion of the sidewalls, whereby an opening to the via is narrowed; removing the sacrificial material through the narrowed opening; sealing the opening by depositing a sealing layer above the spacers, whereby an airgap with an airgap plug is formed; creating at least one contact hole in the airgap plug; filling the contact hole with a conductive material such that at least one contact plug is created; depositing a conductive structure onto the contact plug; making a contact to the contact plug by performing a conventional back end of line processing step; thinning a backside of the first wafer such that the airgap is opened, thereby forming a through wafer via or a deep via; depositing a conductive material in the through wafer via or the deep via to create in the first wafer either a through wafer via filled with conductive material or a deep via filled with conductive material, respectively; and contacting the backside of the first wafer through the through wafer via filled with conductive material or through the deep via filled with conductive material to an interconnect structure situated in a frontside of the second wafer.