Patent ID: 7882476

Claim:
A semiconductor integrated circuit device comprising: a circuit section which is formed by arranging a set of cell columns, each cell column having a plurality of standard cells arranged in a first direction, each of the set of cell columns including: a first set of the plurality of standard cells, each of the first set of the plurality of standard cells including: a first terminal and a second terminal to which a power supply voltage and a ground potential are applied, and a first circuit which includes a first transistor that operates on a voltage applied between the first terminal and the second terminal wherein the first circuit has no well potential fixing active region, and a second set of the plurality of standard cells arranged in a region in which a set of transistors in the first set of the plurality of standard cells that are to be switched according to the same timing are concentrated, or near a large transistor, wherein each of the second set of the plurality of standard cells includes: a third terminal and a fourth terminal to which the power supply voltage and the ground potential are applied, and a second circuit which includes a first active region and a second active region for fixing a well potential formed in an empty region inside the cell, wherein the first active region is electronically connected to the third terminal and the second active region is electrically connected to the fourth terminal and a second transistor to which power is supplied from the third terminal and fourth terminal and a back gate bias is applied from the first active region and second active region, wherein a well potential of the first set of the plurality of standard cells in the cell columns is configured to be fixed by the second set of the plurality of standard cells.