Patent ID: 8853761

Claim:
A non-volatile memory bitcell comprising: a first active region in a substrate, the first active region comprising a source, a drain, and a well, the source having a first implant of a first conductivity type, the drain having a second implant of a second conductivity type of opposite polarity to the first conductivity type, the well having the second conductivity type; a second active region in the substrate separated from the first active region by a nonconductive region; a floating gate extending above the substrate from a portion of the first active region between the source and the drain to a portion of the second active region over the nonconductive region, the floating gate not extending over to active regions other than the first and second active regions; and a capacitor comprising a first plate and a second plate, the first plate comprising a portion of the floating gate above the second active region, and the second plate comprising a portion of the second active region underneath the floating gate.