Patent ID: 8042078

Claim:
A method comprising: developing a first electrical circuit design; creating a netlist data structure as a representation of the first electrical circuit design; generating a first set of target signatures of the netlist data structure or first electrical circuit design for a first verification run, according to a first set of input vectors; executing the first functional verification run for the first electrical circuit design; obtaining a status of one or more first targets from the first functional verification run; wherein said status of the one or more first targets represents a first set of outputs from the first verification run of the first electrical circuit design; modifying the first electrical circuit design; providing a modified netlist data structure for the modified first electrical circuit design; initiating a second functional verification run for the first electrical circuit design; generating a second set of target signatures of the first netlist data structure or first electrical circuit design, according to a second set of input vectors; determining whether a first set of target signatures are substantially identical to a second set of target signatures, respectively; when a first target signature is substantially identical to a second target signature, determining that a first target and a second target have a substantially identical functionality; and when a first target and a second target have the substantially identical functionality, re-using verification results associated with a corresponding first target to eliminate a formal verification re-run associated with the second target; performing an initial functional verification run for the modified first electrical circuit design; obtaining a second set of outputs from the initial functional verification run for the modified first electrical circuit design; and comparing a first set of outputs with a second set of outputs, respectively.