Patent ID: 7047341

Claim:
An apparatus comprising: a first processor module; a second processor module; a bus coupled to the first processor module and the second processor module, wherein the bus is configured to transmit both processor related communication and memory related communication and wherein: the first processor module comprises a first processing unit, a first memory controller/host bridge, a first PCI-to-PCI bridge, a first memory replication engine and a first memory unit; and the second processor module comprises a second processing unit, a second memory controller/host bridge, a second PCI-to-PCI bridge, a second memory replication engine and a second memory unit, wherein the first PCI-to-PCI bridge, the second PCI-to-PCI bridge, the first memory replication engine, and the second memory replication engine are mutually coupled by the bus, the first memory controller/host bridge coupled to the first memory replication engine and the first memory unit, the second memory controller/host bridge coupled to the second memory replication engine and the second memory unit, the first memory controller/host bridge coupled to the first PCI-to-PCI bridge, the second memory controller/host bridge coupled to the second PCI-to-PCI bridge, the first memory controller/host bridge coupled to the first processing unit, and the second memory controller/host bridge coupled to the second processing unit.