Patent ID: 7994582

Claim:
A stacked load-less static random access memory (SRAM) device comprising: a semiconductor substrate having first and second active regions which are spaced apart from each other; a first transistor having a first gate arranged on the first active region of the semiconductor substrate, and a first source region and a first drain region arranged in the first active region on both sides of the first gate; a second transistor having a second gate arranged on the second active region of the semiconductor substrate, and a second source region and a second drain region arranged in the second active region on both sides of the second gate; a first semiconductor layer arranged to overlap the first active region; a third transistor having a third gate arranged on the first semiconductor layer and a third source region and a third drain region arranged in the first semiconductor layer on both sides of the third gate; a second semiconductor layer arranged on the same layer as the first semiconductor layer to overlap the second active region; and a fourth transistor having a fourth gate arranged on the second semiconductor layer and a fourth source region and a fourth drain region arranged in the second semiconductor layer on both sides of the fourth gate, wherein the first drain region of the first transistor, the third drain region of the third transistor, and the second gate of the second transistor are electrically connected through a first contact node, and wherein the second drain region of the second transistor, the fourth drain region of the fourth transistor, and the first gate of the first transistor are electrically connected through a second contact node.