Patent ID: 8239611

Claim:
A system, comprising: at least one memory component configured to include a plurality of memory locations contained in a memory array, the plurality of memory locations comprising at least one memory location and at least one other memory location; a first processor component configured to perform at least one lower level memory operation on the at least one memory location, the at least one lower level memory operation comprising at least one of a read operation, a write operation, an erase operation, or a refresh operation; and a second processor component configured to be local to the at least one memory component and further configured to determine whether at least one higher level memory operation is to be performed on the at least one other memory location and, in response to determining the at least one higher level memory operation is to be performed, perform the at least one higher level memory operation on the at least one other memory location independent of the first processor component and without using any processing resources from the first processor component, the at least one higher level memory operation comprising at least one of data compaction, error code correction, or wear leveling, wherein the first processor component and the second processor component are further respectively configured to operate independent of each other for at least a portion of time including during respective performance of the at least one lower level memory operation and the at least one higher level memory operation, which are performed simultaneously, and wherein the second processor component is further configured to obtain code relating to the at least one higher level memory operation from a storage component and execute the code to facilitate performance of the at least one higher level memory operation.