Patent ID: 7073047

Claim:
A control chip for accelerating memory access, wherein said control chip is coupled to a system bus at least having a clocking line, said control chip comprising: a memory write command queue for holding a plurality of memory write commands, wherein each said memory write command has a write address; a bus interface unit coupled to the system bus, wherein said bus interface unit receives a first section read address and a second section read address of a memory read command sequentially from said system bus according to a clock signal and concurrently outputs said first section read address and said second section read address; and a memory request organizer coupled to the bus interface unit and said memory write command queue for comparing said first section read address with an identical bit portion of each said write address of said memory-write commands inside said memory-write command queue; wherein if the comparison indicates a difference, execution of said memory read command would be permitted; if the comparison indicates the presence of identical bits, said second section read address would be compared with an identical bit portion of each said write address of said memory-write commands inside said memory-write command queue; wherein if the comparison indicates a difference, execution of said memory read command would be permitted; if said comparison still indicating said presence of identical bits, permission to execute said memory read command would be delayed until the memory-write command with identical address bits inside said memory-write command queue executes; wherein said first section read address and said second section read address are compared respectively before they are combined.