Patent ID: 8612651

Claim:
A FIFO memory circuit for interfacing between circuits with different clock domains, comprising: a FIFO memory; a write pointer circuit clocked by a clock of a first clock domain and controlling a memory location to which data is written; and a read pointer circuit clocked by a clock of a second clock domain and controlling a memory location from which data is read, wherein the read and write pointer circuits use gray coding, and wherein the memory circuit further comprises a duplicate write pointer circuit which has its write pointer address incremented synchronously with the write pointer circuit, and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to a size of the FIFO memory, and wherein the memory circuit further comprises a comparator for comparing the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.