Patent ID: 8688914

Claim:
A system for promoting partial data segments in a computing storage environment having lower and higher speed levels of cache, comprising: a processor, operable in the computing storage environment, wherein the processor is adapted for: configuring a data moving mechanism adapted for performing at least one of: allowing the partial data segments to remain in the higher speed cache level for a time period longer that at least one whole data segment, and implementing a preference for movement of the partial data segments to the lower speed cache level based on at least one of an amount of holes and a data heat metric, wherein: a first of the partial data segments having at least one of a lower amount of holes and a hotter data heat is moved to the lower speed cache level ahead of a second of the partial data segments having at least one of a higher amount of holes and a cooler data heat, and if the first of the partial data segments has a hotter data heat and greater than a predetermined number of holes, the first of the partial data segments is discarded.