Patent ID: 7724044

Claim:
An apparatus including a digital multiplexer for selecting among a plurality of input clock signals to provide an output clock signal substantially free of spurious signals related to said selecting among said plurality of input clock signals, comprising: signal loss detection circuitry responsive to a plurality of input clock signals by providing a plurality of signal loss status signals and a plurality of system control signals, wherein each one of said plurality of input clock signals includes respective active and inactive signal states, and respective pulse durations during said active signal states; decoding circuitry coupled to said signal loss detection circuitry and responsive to said plurality of system control signals and a plurality of clock mode control signals by providing a plurality of clock state signals and an output reset signal; and synchronized multiplexer circuitry coupled to said decoding circuitry and responsive to said plurality of input clock signals, said plurality of clock state signals and said output reset signal by selecting one of said plurality of input clock signals as an output clock signal having a minimum pulse duration at least as long as one of said respective pulse durations of said plurality of input clock signals, wherein a first one of said plurality of input clock signals is initially selected as said output clock signal, following a transition by said first one of said plurality of input clock signals from said active state to said inactive state, said first one of said plurality of input clock signals is deselected as said output clock signal, following said deselection of said first one of said plurality of input clock signals as said output clock signal, said output clock signal is reset to a predetermined state, and following said resetting of said output clock signal to said predetermined state, a second one of said plurality of input clock signals is selected as said output clock signal.