Patent ID: 8159262

Claim:
A compensation circuit for controlling a variation in output impedance of at least one buffer circuit, the compensation circuit comprising: a monitor circuit including a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor, the monitor circuit being configured to track an operation of an output stage of the buffer circuit and being operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in at least one of process, voltage and temperature (PVT) conditions to which the buffer circuit may be subjected; and a control circuit generating a first set of digital control bits and a second set of digital control bits for compensating the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions, the second set of digital control bits being generated based at least on the first set of digital control bits and the first control signal.