Patent ID: 7564936

Claim:
Decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit, wherein said decoding process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that L min <L<L max =(L min +k), where k is a predetermined whole number greater than or equal to one, wherein the step for automatically detecting the length L comprises itself the followings steps: a) detection of a possible transition in a portion of the signal carrying the row bit (L min +p) where p is a variable of a whole number type that is initialized at 1; b) if a transition is detected, the row bit (L min +p) is considered as an information bit and: b-1) if (L min +p)=L max , the frame is treated as an information bit frame (L min +p); b-2) if (L min +p)<L max , return to step a) after first incrementing p by one to treat a portion of the signal carrying the following bit, and in that the step for automatically detecting the length of the frame comprises moreover a first step for verifying the decision, made during step c-1), to treat the frame as an information bit frame (L min +p), the said second verification step consisting of verifying that the row bit (L min +(p+1)) is a stop bit.