Patent ID: 8270230

Claim:
A semiconductor device, comprising: a first array composed of memory cells with a select terminal connected with a word line and a data terminal connected with a bit line; a first word-line-timing generator operable to generate a first word-line timing signal for determining a word-line activation time for the first array; a first comparator operable to make a comparison between the first word-line timing signal and a reference signal; a first back-gate-bias control circuit which applies a back-gate bias for enlarging a read margin to the first array when a result of the comparison by the first comparator represents a low condition of the read margin, and which applies a back-gate bias for enlarging a write margin to the first array when the comparison result represents a low condition of the write margin; a second array composed of memory cells with a select terminal connected with a word line and a data terminal connected with a bit line; a second word-line-timing generator operable to generate a second word-line timing signal for determining a word-line activation time for the second array; a second comparator operable to make a comparison between the second word-line timing signal and a reference signal; and a second back-gate-bias control circuit which applies a back-gate bias for enlarging a read margin to the second array when a result of the comparison by the second comparator represents a low condition of the read margin, and which applies a back-gate bias for enlarging a write margin to the second array when the comparison result represents a low condition of the write margin.