Patent ID: 7683428

Claim:
A vertical Fin-FET semiconductor device characterized by: At least one vertical semiconductor fin ( 12 A) disposed on an insulator layer ( 4 ); Doped source ( 26 A) and drain regions ( 28 A) in bottom and top portions of the at least one semiconductor fin ( 12 A); and Gate conductors ( 24 A, 24 B) disposed along vertical sidewalls of the at least one semiconductor fin ( 12 A) and separated therefrom by thin gate insulators ( 22 ); Source conductors ( 18 A, 18 B) contacting the source region ( 26 A) on opposite sides of the at least one semiconductor fin ( 12 A); At least one source contract ( 38 A) connecting to at least one source conductor ( 18 A, 18 B); At least one drain contact ( 40 A) connecting to the drain region ( 28 A) of the at least one semiconductor fin ( 12 A); A vertical channel region in the fin ( 12 A) between the source region ( 26 A) and the drain region ( 28 A); and At least one gate contact ( 42 A) connection to at least one gate conductor ( 24 A, 24 B).