Patent ID: 7423319

Claim:
A semiconductor structure comprising: a substrate; a first well region of a first conductivity type overlying the substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region; a third well region of the second conductivity type adjacent the first well region, wherein the second and the third well regions are spaced apart from each other; a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions; a second deep well region of the second conductivity type underlying the third well region, wherein the second deep well region encloses at least portions of sidewalls and bottom of the third well region, and wherein the first and the second deep well regions are spaced apart by a spacing; an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region; a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region; and a gate electrode on the gate dielectric.