Patent ID: 8536712

Claim:
A memory device comprising: a laminated chip package laminated from a plurality of memory chips each having a plurality of memory cells, an interposed chip equal in outside dimension to a memory chip from the plurality of memory chips and having no semiconductor element, and a controller plate having a control circuit controlling read/write from/to the plurality of memory cells, the laminated chip package, the interposed chip and the controller plate being laminated together, the interposed chip being between the laminated chip package and the controller plate, wherein each of the memory chips comprising: a device region in which the plurality of memory cells are formed; a resin insulating layer made of an insulating resin formed outside the device region; and a plurality of wiring electrodes for memory connected to the plurality of memory cells and extending from a connection pad in contact with the device region to the top of the resin insulating layer; wherein the controller plate comprises: a plurality of opposing wiring electrodes formed on an opposing surface opposing the interposed chip; a plurality of outside wiring electrodes formed on an outer surface arranged on a rear side of the opposing surface; and a plurality of connection electrodes for plate formed on a side surface crossing the opposing surface and the outer surface and each connecting each of the opposing wiring electrodes to each of the outside wiring electrodes, wherein the interposed chip has a plurality of interposed wiring electrodes formed in a common arrangement pattern in common with an arrangement pattern of the plurality of opposing wiring electrodes, and wherein the controller plate is mounted on the interposed chip and each of the opposing wiring electrodes is connected to each of the interposed wiring electrodes.