Patent ID: 8458538

Claim:
A semiconductor device, comprising: a memory portion; a memory built-in self-test (MBIST) circuitry connected to said memory portion, said MBIST circuitry configured to perform a memory self-test by reading out said memory portion and comparing read results with a reference data to provide compare results to identify a plurality of memory failures; and a latency detection circuit provided in said MBIST circuitry, wherein said latency detection circuit comprises a ping signal generator configured to generate a ping signal and a ping signal receiver configured to receive said ping signal to determine a round trip latency from the said latency detection circuit to said memory portion and back to said latency detection circuit and said latency detection circuit is configured to determine a time interval from an execution of a test algorithm at said memory portion to a detection of a predefined numbered failure of said memory failures based on said round trip latency.