Patent ID: 7277909

Claim:
A high speed adder in which provisional carries composed of a pair of signals that indicate a case where carry is produced from a low order bit and a case where no carry is produced therefrom are generated in advance and an actual carry is selected from the provisional carries in accordance with selection information from the low order bit, the high speed added comprising: a carry transfer path; and a plurality of converters, each of which converts the provisional carries into provisional sums composed of a pair of signals that indicate the case where the carry is produced from the low order bit and the case where no carry is produced therefrom, the converters being provided on a predetermined portion of the carry transfer path, wherein, when the adder is a 2 N (N is an integer of 3 or more)-bit adder, the carry transfer path comprises (N+1) or less circuit stages, wherein a first circuit stage receives two input data for each corresponding bit and an input carry signal from an outside, generates a bit sum of a least significant bit, outputs the bit sum to the outside, generates provisional carries corresponding to each of bits other than the least significant bit, and outputs the generated provisional carries to a following circuit stage, wherein second to N-th circuit stages convert the provisional carries corresponding to higher (2 (N−1) −1) bits other than a most significant bit, of the provisional carries into the provisional sums by at least one of the converters in course of transfer, and generate actual carries from the provisional carries corresponding to lower (2 (N−1) −1) bits other than the least significant bit, and wherein a (N+1)-th circuit stage outputs data other than a bit sum of the least significant bit, of sum data of the two input data and an output carry signal to the outside.