Patent ID: 7111112

Claim:
A semiconductor memory device having an operation state capable of performing a read operation and a write operation of data and a standby state to hold said data, comprising: a memory cell array including a plurality of memory cells arranged in columns and rows; and a complete hidden refresh circuit refreshing said data held by said plurality of memory cells in a predetermined timing; wherein said complete hidden refresh circuit includes: a refresh circuit outputting a refresh command signal that commands to perform a refresh operation, and a control circuit outputting an internal operation designation signal that commands to perform a read or write operation of data in said operation state; and said control circuit includes: a first circuit activating and outputting said internal operation designation signal to start said operation state based on an external signal that commands to start said operation state, and terminating said operation state based on an external signal that commands to terminate said operation state, and a second circuit outputting a control signal via a signal path different from a signal path of said first circuit based on the external signal that commands to terminate said operation state to allow said first circuit to inactivate and output said internal operation designation signal.