Patent ID: 8063492

Claim:
A multi-chip stacked package primarily comprising: a chip carrier; a first chip disposed on the chip carrier, wherein the first chip has a first active surface and a plurality of first bonding pads disposed on a central region of the first active surface; a plurality of first die-attaching bars formed on the first active surface of the first chip in a pattern to dispose at two opposing sides adjacent to the first bonding pads and also to form a central gap between the first die-attaching bars without covering the first bonding pads, wherein the first die-attaching bars have an adhesive surface away from the first active surface, the adhesive surface having a width not less than the width of the central gap between the first die-attaching bars; a plurality of first bonding wires electrically connecting the first bonding pads of the first chip to the chip carrier, wherein the first bonding wires have a loop height lower than the adhesive surface in a manner that specific sections of the first bonding wires are embedded in the corresponding first die-attaching bar from the adhesive surface; a second chip having a second active surface and a second back surface, wherein the second back surface is attached to the adhesive surface of the first die-attaching bars; and an encapsulant formed on the chip carrier to encapsulate the first chip and the second chip and also to completely fill in the central gap between the first die-attaching bars.