Patent ID: 7834387

Claim:
A semiconductor structure comprising: a first gate stack located in a first device region and a second gate stack located in a second device region, wherein said first and second gate stacks include different material stacks, said first gate stack comprises: a semiconductor oxide containing gate dielectric portion contacting a top surface of a semiconductor substrate; a semiconductor gate electrode contacting said semiconductor oxide containing gate dielectric; a first high-k gate dielectric portion comprising a dielectric metal oxide, having a dielectric constant greater than 4.0, and located above said semiconductor gate electrode; an interfacial dielectric portion comprising an oxide of a material comprising said semiconductor gate electrode and vertically contacting a top surface of said semiconductor gate electrode and a bottom surface of said first high-k gate dielectric portion; and a first metal-semiconductor-stack gate electrode contacting a top surface of said first high-k gate dielectric portion and comprising a first metal gate portion and a first doped semiconductor portion, wherein a top surface of said first metal gate portion contacts a bottom surface of said first doped semiconductor portion, and wherein said second gate stack comprises: a second high-k gate dielectric portion comprising said dielectric metal oxide; and a second metal-semiconductor-stack gate electrode contacting a top surface of said second high- k gate dielectric portion and comprising a second metal gate portion and a second doped semiconductor portion, wherein a top surface of said second metal gate portion contacts a bottom surface of said second doped semiconductor portion.