Patent ID: 8178971

Claim:
A semiconductor device comprising: a wiring substrate including an upper surface, a lower surface opposed to the upper surface, a plurality of connection pads formed on the upper surface so that the connection pads are positioned adjacent to a first side of the wiring substrate; a first semiconductor chip mounted over the upper surface of the wiring substrate the first semiconductor chip electrically connected to an associated one of the connection pads; a second semiconductor chip stacked over the first semiconductor chip so that a center of the second semiconductor chip is deviated from a center of the wiring substrate toward a second side opposed to the first side of the wiring substrate, the second semiconductor chip electrically connected to an associated one of the connection pads; a sealing resin formed on the upper surface of the wiring substrate to cover the first semiconductor chip and the second semiconductor chip; and a plurality of external terminals formed on the lower surface of the wiring substrate, the plurality of external terminals including a first external terminal that is electrically connected to the associated one of the connection pads, and a second external terminal that is not electrically connected to the associated one of the connection pads, the second external terminal being positioned adjacent to the second side of the wiring substrate and under the sealing resin, wherein the second external terminal is arranged adjacent to the second side of the wiring substrate without arranging adjacent to the first side.