Patent ID: 7475304

Claim:
A field programmable bit error testing device comprising: means for sending a signal to a unit-under-test comprising a debouncer circuit, said means including: 25-bit binary counter comprising: a load input; a clock; a first preselected threshold; a second preselected threshold; up and down inputs combined using an AND gate and input into said 25-bit binary counter; an OR gate connected to said two preselected thresholds and wherein said first threshold is connected to said load input; and wherein once the counter reaches the first threshold, the OR gate outputs logic 1 and when the counter reaches the second threshold, the OR gate again goes to logic 1 switching back and forth between said load input and said second preselected threshold; means for receiving a signal from said unit-under-test means for introducing a time-delay into the signal from said means for receiving step; the comparator circuit for comparing a signal from said means for sending step to the signal from said means for receiving step; and an end-circuit for outputting a time differential from said comparator circuit to an oscilloscope, thereby allowing an operator to determine degree of error and operating capability of said unit-under-test.