Patent ID: 8645116

Claim:
A hybrid simulation system, comprising: a processor; a hybrid simulation model, which comprises: a real model for simulating execution of a group of instructions on a hardware design; a bus interface for providing the real model a function of accessing other slave models of the hardware design; and an acceleration model, which comprises: a trace generation unit for recording behavior of the real model for accessing the other slave models as at least one trace file and storing the at least one trace file to a computer usable medium when the real model is executing a first simulation; a trace replay unit for reading the at least one trace file and accordingly performing an access operation in a plurality of repeated simulations after the first simulation; a selection unit for dynamically switching to the real model to perform a real simulation or switching to the trace replay unit to perform a trace simulation in the plurality of repeated simulations; a snapshot generation and load unit for generating at least one status snapshot file corresponding to at least one specific time point and storing the at least one status snapshot file to the computer usable medium when the real model is executing the first simulation, and loading the corresponding at least one status snapshot file to the real model when switching to the real model in the plurality of repeated simulations; and a virtual breakpoint control unit for controlling the selection unit to switch between the trace simulation and the real simulation in the plurality of repeated simulations according to a virtual breakpoint set by a debugger in the at least one trace file.