Patent ID: 8178947

Claim:
A semiconductor device, comprising: a semiconductor substrate having first and second main surfaces; a first impurity region of a first conductivity type between said first main surface and said second main surface; a second impurity region of a second conductivity type at said second main surface; a first groove portion at said first main surface and reaching said first impurity region; a first electrode in said first groove portion with a first insulating film interposed therebetween; a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface; a second electrode in said second groove portion with a second insulating film interposed therebetween; a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode; a third impurity region of said first conductivity typed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode; a fourth impurity region of the second conductivity type at said first main surface between said first electrode and said second electrode and surrounding said third impurity region; a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region; an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other; a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region and having an impurity concentration higher than an impurity concentration of said first impurity region; and a sixth impurity region of said second conductivity type at said first main surface adjacent to said second electrode on a side opposite to said fourth impurity region with respect to said second electrode, wherein said main electrode extends in the direction along which said first and second electrodes are aligned, and is connected to said second electrode, and said interlayer insulating film is on said sixth impurity region to insulate said sixth impurity region and said main electrode from each other.