Patent ID: 7966440

Claim:
An image processing controller that performs transmission and processing of image data by connecting an engine, including a scanner and a plotter, and a central processing unit that is connected via a chipset, the image processing controller comprising: a first controller to control communication with the chipset via a first PCI-Express interface; a second controller, operatively connected to the first controller, to control in cooperation with the first controller, communication with the engine when the engine is connected via a second PCI-Express interface, the second controller including a first image input/output resource; and a third controller, operatively connected to the first controller to control, in cooperation with the first controller, communication with at least one of the engine and an external device when the at least one of the engine and the external device is connected via a PCI interface, the third controller including a second input/output resource; wherein the first controller is configured to receive, on behalf of the engine and the external device, an access from the central processing unit to the engine and the external device, and is configured to inhibit a reference from the central processing unit to a resource operatively connected to the image processing controller, the image processing controller configured to detect whether the engine is connected to the second or third controller, to reject an access request from the second PCI-Express interface to the first input/output resource of the second controller when the second controller is not connected to the engine, and to reject an access request from the PCI interface unit to the second input/output resource of the third controller when the third controller is not connected to the engine, wherein when the second controller receives an access request from the engine to a memory connected to the chipset, the second controller converts a memory access from the engine into an access to the memory and inhibits a reference by the engine to the first image input/output resource, and when the third controller receives an access request from at least one of the engine and the external device to the memory connected to the chipset, the third controller converts a memory access from the at least one of the engine and the external device into an access to the memory and inhibits a reference by the at least one of the engine and the external device to the second image input/output resource.