Patent ID: 7812650

Claim:
A bias voltage generation circuit for generating a bias voltage for a clock synchronizing circuit, the bias voltage generation circuit comprising: a bias unit configured to control a current in response to a plurality of first bandwidth control signals; an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit; and an output unit configured to receive an output signal of the amplification unit to variably control the bias voltage in response to a plurality of second bandwidth control signals and output the bias voltage, wherein the bias unit, comprising a plurality of first transistors configured to operate in response to the first bandwidth control signals from a mode register set; and a plurality of second transistors coupled to the first transistors in series and configured to operate in response to a bias control voltage, wherein the output unit comprises a feedback path configured to detect an output of the amplification unit to control a feedback voltage depending on the detected output of the amplification unit, wherein the output unit is configured to control a capacitance of a capacitor connected to an output node to variably control the bias voltage.