Patent ID: 8604827

Claim:
A logic circuit comprising: at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value, the selected value being selected from among a voltage and a current of an input signal, the at least one variable resistance device being configured to memorize the resistance value, the logic circuit being configured to store multi-level data by setting the memorized resistance value; and a write unit including the at least one variable resistance device, a first write switch and a second write switch, the write unit being configured to write the multi-level data to the variable resistance device by setting the resistance value of the at least one variable resistance device based on the at least one selected value and a write enable signal, the variable resistance device including at least a first terminal and a second terminal, the first and second terminals being separate terminals, wherein the first write switch is connected to the variable resistance device via the first terminal, the first switch is configured such that a conductivity of the first write switch is controlled based on the write enable signal, the second write switch is connected to the variable resistance device via the second terminal, and the second switch is configured such that a conductivity of the second write switch is controlled based on the write enable signal.