Patent ID: 7459978

Claim:
An output stage, comprising: a first diode connected transistor (Q 1 ) including a control terminal and a current path including a first terminal and a second terminal, the first current path terminal of the first transistor (Q 1 ) connected to a first voltage rail, and the control terminal of the first transistor (Q 1 ) connected to one of the first and second current path terminals of the first transistor (Q 1 ); a second diode connected transistor (Q 2 ) including a control terminal and a current path including a first terminal and a second terminal, the first current path terminal of the second transistor (Q 2 ) connected to the first voltage rail, and the control terminal of the second transistor (Q 2 ) connected to one of the first and second current path terminals of the second transistor (Q 2 ); a third diode connected transistor (Q 3 ) including a control terminal and a current path including a first terminal and a second terminal, the second current path terminal of the third transistor (Q 3 ) connected the second current path terminal of the first transistor (Q 1 ), and the control terminal of the third transistor (Q 3 ) connected one of the first and second current path terminals of the third transistor (Q 3 ); a fourth transistor (Q 4 ) including a control terminal and a current path including a first terminal and a second terminal, the second current path terminal of the fourth transistor (Q 4 ) connected the second current path terminal of the second transistor (Q 2 ), and the control terminal of the fourth transistor (Q 4 ) connected to the first current path terminal of the third transistor (Q 3 ); a bias current source (Ibias) connected between the first current path terminal of the third transistor (Q 3 ) and a second voltage rail; a fifth transistor (Q 5 ) including a control terminal and a current path including a first terminal and a second terminal, the control terminal of the fifth transistor (Q 5 ) forming an input of the output stage, the first current path terminal of the fifth transistor (Q 5 ) connected to the second current path terminals of the second and fourth transistors (Q 2 and Q 4 ), and the second current path terminal of the fifth transistor (Q 5 ) forming an output of the output stage; and a current mirror ( 120 ) including an input and an output, the input of the current mirror ( 120 ) connected to the first current path terminal of the fourth transistor (Q 4 ), the output of the current mirror connected to the second current path terminal of the fifth transistor (Q 5 ), and wherein the current mirror ( 120 ) is connected to the second voltage rail.