Patent ID: 8129259

Claim:
A manufacturing method of a semiconductor device comprising: preparing a semiconductor substrate including plural regions for forming semiconductor chips, plural scribing regions surrounding the plural regions for forming the semiconductor chips, and plural cutting regions which are formed in the plural scribing regions and have widths less than those of the scribing regions; forming check patterns and semiconductor chips, the check patterns being arranged on a first surface of the semiconductor substrate at portions corresponding to the plural scribing regions having checking terminal connecting faces, and provided for testing electrical characteristics of the semiconductor substrate, the semiconductor chips including semiconductor elements arranged on the first surface of the semiconductor substrate at portions corresponding to the plural regions for forming the semiconductor chips, electrode pads having connecting faces which are electrically connected to the semiconductor elements, and a protection film covering the semiconductor elements while enabling exposing the connecting faces and the checking terminal connecting faces to an outside; forming a resist film over the checking terminal connecting faces of checking terminals, the connecting faces of the electrode pads and the protection film; forming through grooves having widths less than those of the scribing regions and greater than those of the check patterns and the cutting regions; removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of the protection film facing the through grooves and at portions of the semiconductor substrate facing the through grooves; removing the resist film; forming internal connection terminals on the contacting faces of the electrode pads; forming an insulating resin layer including a sheet-like insulating resin as a base material by pressing the sheet-like insulating resin onto the protection film and the grooves to form a flat connecting face over the internal connection terminals and fill a space under the flat connecting face with the sheet-like insulating resin; forming a wiring forming face on the insulating resin layer by removing the insulating resin layer until connecting faces of the internal connection terminals are exposed to the outside; forming wiring patterns connected to the connecting faces of the internal connection terminals on the wiring forming face; and cutting the semiconductor substrate and the insulating resin layer to separate the plural semiconductor elements into individual semiconductor devices.