Patent ID: 7498651

Claim:
A method of making a high voltage power semiconductor device with a junction termination structure, comprising: forming a high voltage power semiconductor device on a region of a substrate, the device having a peripheral edge; forming at least first and second conductive rings around the device, the first ring spaced from the peripheral edge and the second ring spaced from the first ring; and forming a resistive interconnection between the peripheral edge of the device and at least the first ring, the resistive interconnection being formed so as to provide an electrical path which stabilizes the voltages at each of the conductive rings and to provide a doped region that can be partially or completely depleted so that the electric field lines can be terminated on the charge in the depleted doped region; the foregoing forming steps including: depositing a doped semiconductive layer of a first thickness on the substrate; forming the device in or on the doped semiconductor layer within the region of the substrate; and etching a pattern in the doped semiconductor layer to define the peripheral edge of the device, and at least first and second rings spaced therefrom; wherein the etching step etches entirely through the doped semiconductor layer in at least one gap between the device, the first ring and the second ring.