Patent ID: 8156251

Claim:
A hardware based controller useful for at least partially controlling a system comprising: a) a complex logic device which includes: i) a fixed bus communication circuit, ii) a plurality of input memory locations, iii) a core logic circuit, iv) a plurality of output memory locations, v) an integrity monitor circuit, and vi) a scheduler circuit, b) wherein said complex logic device i) requests digital input information from said system through said fixed bus communication circuit, ii) stores said digital input information into said input memory locations, iii) uses said input memory locations to create digital output information according to a predetermined system criterion, iv) stores said digital output information into said output memory locations, and v) transmits said digital output information through said fixed bus communication circuit to said system, c) wherein said complex logic device contains no executable software component, d) wherein said fixed bus communication circuit provides a communication interface between said system and said complex logic device based on a communication schedule from said scheduler circuit, e) wherein said complex logic device operates in a pre-determined, fixed, uninterruptible, and non-modifiable manner during normal operation, f) wherein said scheduler circuit provides an access pattern and control signals for communication with said system in a predetermined and non-modifiable manner, and g) wherein said integrity monitor circuit monitors the operation of said complex logic device for failure, whereby said complex logic device provides at least one control function for said system.