Patent ID: 7256501

Claim:
A semiconductor device comprising: a semiconductor chip having first and second principal surfaces which are positioned on opposite sides, a first electrode formed on said first principal surface, and second and third electrodes formed on said second principal surface; a resin sealing body which seals said semiconductor chip and has first and second principal surfaces positioned on opposite sides, in which the first principal surface of said resin sealing body is positioned on the first principal surface side of said semiconductor chip and the second principal surface of said resin sealing body is positioned on the second principal surface side of said semiconductor chip; a first conductive member having one end, which is positioned on the first electrode of said semiconductor chip and connected to the first electrode of said semiconductor chip via first connection means, and the other end on the opposite side of the one end, which is positioned on the second principal surface side of the resin sealing body in comparison with the one end and exposed from said resin sealing body; a second conductive member connected to the second electrode of said semiconductor chip via second connection means; and a third conductive member connected to the third electrode of said semiconductor chip via third connection means, wherein the one end of said first conductive member is exposed from the first principal surface of said resin sealing body, said second and third conductive members are exposed from the second principal surface and side surfaces of said resin sealing body, and each of said first, second, and third connection means includes: a stress buffer layer having a function to buffer thermal stress generated by a difference in thermal expansion coefficients between said first, second, and third conductive members and said semiconductor chip; a first connection layer formed on the semiconductor chip side of said stress buffer layer and having a function to connect said stress buffer layer to the first, second, and third electrodes of said semiconductor chip; and a second connection layer formed on the first, second, and third conductive member side of said stress buffer layer and having a function to connect said stress buffer layer to said first, second, and third conductive members.