Patent ID: 8816951

Claim:
A shift register unit, comprising: an input module which inputs a first clock signal, a second clock signal, a frame start signal, a high voltage signal, and a low voltage signal, wherein the first clock signal is identical with the phase-inverted signal of the second clock signal within time interval of one frame; a processing module comprising a plurality of thin film transistors and connected to the input module, which generates a gate drive signal according to the first clock signal, the second clock signal, and the frame start signal, controls the voltage of a first node formed by the thin film transistors lower than the low level of a power supply signal during an evaluation period of the shift register unit, and controls to reset a second node formed by the thin film transistors, so as to cut off a transient direct current path formed by the input terminal of the high voltage signal, the input terminal of the low voltage signal, and at least one thin film transistor in time; and an output module connected with the processing module, which sends the gate drive signal generated by the processing module, wherein the processing module comprises: a gate drive signal generation unit connected with the input module and comprising at least an evaluation thin film transistor and a reset thin film transistor, which generates the gate drive signal according to the first clock signal, the second clock signal, and the frame start signal, wherein the ON and OFF of the evaluation thin film transistor is driven by the first node, and the ON and OFF of the reset thin film transistor is driven by the second node; a feedback control unit connected with the gate drive signal generation unit, which controls to make the voltage of a first node formed by the thin film transistors lower than the low level of the power supply signal during the evaluation period of the shift register unit, and controlling to reset the second node formed by the thin film transistors, so as to cut off the transient direct current path formed by the input terminal of the high voltage signal, at least one thin film transistor, and the input terminal of the low voltage signal in time.