Patent ID: 7327204

Claim:
A tapped delay chain comprising a plurality of analog delay cells where at least a first delay cell in the chain has associated therewith a follow-on processing unit having an input capacitance and the first delay cell has: at least two output taps for respectively outputting first and second delayed signals derived from and delayed relative to a received analog input signal of the first delay cell, where the delays of the first and second delayed signals differ from one another, where a first of the at least two output taps is operatively coupled for feeding forward the corresponding first delayed signal to a next delay cell in the chain, and where a second of the at least two output taps is operatively coupled for feeding the corresponding second delayed signal to the respective follow-on processing unit of the first delay cell so that the second delayed signal can be processed by the respective follow-on processing unit without loading the first output tap of the first delay cell with the input capacitance of the respective follow-on processing unit.