Patent ID: 7095895

Claim:
A semiconductor integrated circuit for coding input data of 8 bits into output data of 10 bits, said semiconductor integrated circuit comprising: a number-of-levels comparison circuit for comparing a number of bits having a first level and a number of bits having a second level in predetermined bits of the input data to output first data which changes in accordance with whether or not at least 4 bits within predetermined 7 bits of the input data have the first level and which constitutes a portion of the output data; a number-of-transitions decrease circuit for decreasing a number of transitions between adjacent two bits of the input data in accordance with the first data to output second data of 8 bits; a DC balance circuit for keeping balance between a number of bits having the first level and a number of bits having the second level in the output data of 10 bits in accordance with the first and second data to output third data which constitutes another portion of the output data; and an output inversion circuit for inverting the second data in accordance with the third data to output fourth data which constitutes the other portion of the output data.