Patent ID: 7276761

Claim:
A semiconductor memory device comprising: a plurality of bit lines formed by implanting a second conductive-type impurity in a first conductive-type semiconductor substrate; a thick insulating film on the bit lines; a thin insulating film between the neighboring bit lines; and a plurality of word lines formed on the thick and thin insulating films so as to cross the bit lines, wherein each of the word lines includes a plurality of first conductors and a second conductor which electrically connects the first conductors in series, the respective first conductors are formed on the thin insulating film, wherein the thick insulating film comprises first and second opposing and substantially vertically oriented sidewalls and a top face which interconnects the sidewalls, wherein the top face of the thickest portion of the thick insulating film is higher than the top face of the first conductors, and the uppermost portions of the respective substantially vertically oriented sidewalls of the thick insulating film are located at an elevation above a top surface of the thin insulating film; and the film thickness of the thick insulating film is made thinner toward edges of the top face where the top face angles downwardly and meets the substantially vertically oriented sidewalls.