Patent ID: 6898562

Claim:
A method in a logic simulator machine for overriding a value of a net during execution of a test routine, said method comprising the steps of: building a model of a logic design to be simulated utilizing said logic simulator machine, said logic design including a plurality of nets; selecting one of said plurality of nets whose actual value may be overridden; inserting a multiplexer into said model during said step of building, said multiplexer receiving as its inputs said actual value of said one of said plurality of nets, a control bit, and an override value, and outputting a current value of said one of said plurality of nets, wherein said current value is propagated to other ones of said plurality of nets; and propagating said override value as said current value of said one of said plurality of nets instead of said actual value throughout execution of said test routine utilizing said multiplexer when said control bit is set.