Patent ID: 7259595

Claim:
A frequency detection circuit to detect a frequency of a clock signal, the circuit comprising: a frequency detector to divide the clock signal by a predetermined division ratio, to detect the frequency of the clock signal based on a divided signal obtained by the division of the clock signal, an inverted signal of the divided signal, and the clock signal, and to generate a first detection signal; and an output controller to generate a second detection signal in response to the first detection signal, the second detection signal indicating whether or not the frequency of the clock signal is higher than a predetermined value, wherein the frequency detector comprises: a divider to divide the clock signal by the predetermined division ratio in response to a first detection control signal and to generate the divided signal, and a logic circuit to generate the first detection signal based on the divided signal, the inverted signal of the divided signal, and the clock signal, and wherein the logic circuit comprises: a first logic circuit to generate a first delay pulse signal in response to the divided signal and the clock signal, a second logic circuit to generate a second delay pulse signal in response to the inverted signal of the divided signal and the clock signal, and a third logic circuit to generate the first detection signal in response to the first delay pulse signal and the second delay pulse signal.