Patent ID: 8232594

Claim:
A semiconductor device comprising: an isolation layer formed over a semiconductor substrate; a drift area formed in an active area separated by the isolation layer; a pad nitride layer pattern formed in a form of a plate on the drift area; a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern such that only one side of the gate electrode is formed over the pad nitride layer pattern; and a first conductive type deep well formed in the semiconductor substrate, wherein the isolation layer contacts the first conductive type deep well and the drift area, wherein the pad nitride layer pattern has one end interposed between the gate electrode and the semiconductor substrate, wherein the pad nitride layer pattern has an opposite end exposed to an outside of the gate electrode, wherein the opposite end of the pad nitride layer pattern exposed to the outside of the gate electrode is provided on the drift area, wherein the drift area is formed in the first conductive type deep well.