Patent ID: 8058123

Claim:
A method of forming an integrated circuit structure comprising: providing a substrate; forming a first and second device region on a surface of the substrate; forming first spacers of a first width on sidewalls of a first gate stack in said first device region; forming second spacers of a second width on sidewalls of a second gate stack in said second device region; forming first source/drain stressor elements in a first source/drain stressor region in the substrate adjacent to the first gate stack with the first spacers, wherein the first source/drain stressor elements have a first proximity to a first channel in the substrate below the first gate stack determined by the first spacers; and forming second source/drain stressor elements in a second source/drain stressor region in the substrate adjacent to the second gate stack with the second spacers, wherein the second source/drain stressor elements have a second proximity to a second channel in the substrate below the second gate stack determined by the second spacers.