Patent ID: 7843218

Claim:
A data storage circuit, comprising: a multiplexer for receiving functional data and scan data inputs and generating a multiplexer output signal under control of a scan enable signal; a master latch for generating a master latch output signal from said multiplexer output signal at a hold time under control of a master clock signal; a slave latch for generating a flip flop output signal from said master latch output signal at a launch time under control of a slave clock signal; clock generation circuitry for receiving a first clock signal and generating therefrom a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode; and data propagation logic circuitry operable to use said first and second clock signals to generate the master and slave clock signals during a scan mode to delay data launch at the slave latch with respect to data capture at the master latch, and to generate the master and slave clock signals during a functional mode so that data launch at the slave latch coincides with data capture at the master latch.