Patent ID: 7177215

Claim:
A semiconductor integrated circuit device comprising: a first memory cell array including a first bit line and a first precharge circuit; a second memory cell array including a second bit line and a second prechrage circuit; a third memory cell array including a third bit line and a third precharge circuit; a fourth memory cell array including a forth bit line and a fourth precharge circuit; a first MOS transistor coupled to the first bit line; a second MOS transistor coupled to the second bit line; a third MOS transistor coupled to the third bit line; a fourth MOS transistor coupled to the fourth bit line; and a sense amplifier coupled to the first, second, third, and fourth MOS transistors; wherein when the first memory cell array is selected, the second, third, and fourth MOS transistors are turned off, wherein the sense amplifier is arranged between the second and third memory cell arrays, and wherein the second and third memory cell arrays are arranged between the first and fourth memory cell arrays.