Patent ID: 8362573

Claim:
An integrated circuit comprising: a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area; a second diffusion area for a second type transistor, the second diffusion area being spaced from the first diffusion area, the second type transistor including a second drain region and a second source region in the second diffusion area; a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction; a first metallic layer electrically coupled with the first source region, the first metallic layer and the first diffusion area overlapping with a first distance in the routing direction; a second metallic layer electrically coupled with the first drain region and the second drain region, the second metallic layer and the first diffusion area overlapping with a second distance in the routing direction, wherein the first distance is larger than the second distance; and a third metallic layer electrically coupled with the second source region, the third metallic layer and the second diffusion area overlapping with a third distance in the routing direction, wherein the second metallic layer and the second diffusion area are overlapped by a fourth distance in the routing direction, and the third distance is larger than the fourth distance.