Patent ID: 8732647

Claim:
An electronic design automation method implemented in a computing system for creating a physical connection netlist for a pre-floorplan partitioned design file of a 3D integrated circuit containing stacked tiers of dies, the method comprising receiving, using a computer in the system, a hardware description of a pre-floorplan integrated circuit design, the design having been partitioned so as to assign logic to respective ones of multiple dies, the design further including a 3D stack model defining locations and orientations of the multiple dies within a stack of tiers of such dies, each tier containing one or more dies at a same level in the stack; selecting and processing, using the computer, in successive iterations different pairs of dies, wherein for each selected pair of dies the processing comprises successive iterations of creating physical connections data for selected die paths connecting the pair of dies, the physical connections data defining through-silicon vias, bump pins and both intra-die and inter-die connecting nets for the selected die paths of the pair of dies; and storing in a memory of the computing system all created physical connections data for all selected die paths for all selected pairs of dies as a netlist for the received design.