Patent ID: 7308663

Claim:
A design verification method, comprising: providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, L being an integer greater than 4, wherein the stimulus tree diagram further comprises M checkpointed splits, M being an integer greater than 1, and wherein the stimulus tree diagram further comprises N non-checkpointed splits, N being an non-negative integer; and executing the stimulus tree diagram, wherein said executing the stimulus tree diagram comprises, for i=1, . . . , M, executing an i th checkpointed split of the M checkpointed splits, wherein said executing the i th checkpointed split comprises: saving an i th context of an i th simulation environment in which said executing the stimulus tree diagram is performed; and after said saving the i th context is performed, executing from the i th context along Pi paths of the stimulus tree diagram branching from the i th checkpointed split, wherein the i th checkpointed split is a Pi-way split, Pi being an integer greater than 1.