Patent ID: 8140771

Claim:
A method of data processing in a data processing system including a memory hierarchy, said method comprising: a processor core executing a storage-modifying memory access instruction to determine a memory address and to detect whether a partial cache line hint is present in the storage-modifying memory access instruction; in response to execution of the storage-modifying memory access instruction, the processor core transmitting to a cache memory within the memory hierarchy a storage-modifying memory access request including the memory address, an indication of an memory access type, and, only if a partial cache line hint is detected in the storage-modifying memory access instruction executed by the processor core, a partial cache line hint signaling access to less than all of multiple granules of a target cache line of data associated with the memory address; in response to the storage-modifying memory access request: the cache memory performing a storage-modifying access to all granules of the target cache line of data if the partial cache line hint is not present in the storage-modifying memory access request; and the cache memory performing a storage-modifying access to less than all granules of the target cache line of data if the partial cache line hint is present in the storage-modifying memory access request; and prior to execution of the storage-modifying memory access instruction, marking the storage-modifying memory access instruction with the partial cache line hint if only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying memory access instruction with the partial cache line hint.