Patent ID: 7411805

Claim:
A dynamic type semiconductor memory device, comprising: a semiconductor chip having a clock generating circuit that generates clock signals, and an internal circuit whose operation is controlled by the clock signals, wherein the semiconductor chip includes: a first power source pad which is coupled to the clock generating circuit for supplying a first power source voltage to the clock generating circuit; a second power source pad which is coupled to the clock generating circuit for supplying a second power source voltage which is lower than the first power source voltage to the clock generating circuit; a third power source pad which is coupled to the internal circuit for supplying a third power source voltage to the internal circuit; and a fourth power source pad which is coupled to the internal circuit for supplying a fourth power source voltage which is lower than the third power source voltage to the internal circuit, wherein the dynamic type semiconductor memory device includes: a first terminal which is coupled to the first power source pad; a second terminal which is coupled to the second power source pad; a third terminal which is coupled to the third power source pad and which is different from the first terminal; and a fourth terminal which is coupled to the fourth power source pad and which is different from the second terminal.