Patent ID: 7478190

Claim:
A method for routing traffic, said method comprising: providing a processor having an operating portion and a cache with a data block associated with an address, said address being comprised of a plurality of bits; providing at least a first conductor configured to extend from said operating portion to said cache to supply a first address packet comprised of first selected bits of said plurality of bits of said address from said operating portion to said cache; providing at least a second conductor configured to extend from said operating portion to said cache to supply a second address packet comprised of second selected bits of said plurality of bits of said address from said operating portion to said cache, wherein said at least a second conductor has a higher latency than said at least a first conductor; operating said processor to generate said address at said operating portion and directing said first address packet over said at least a first conductor to said cache, and directing said second address packet over said at least a second conductor to said cache; fetching a plurality of data blocks associated with said first address packet from said cache, and identifying said data block associated with said address from said plurality of data blocks using said second selected bits.