Patent ID: 8093578

Claim:
A nonvolatile memory element array, comprising: a plurality of nonvolatile memory elements; a plurality of lower electrodes formed on a first flat plane parallel to a main surface of a substrate so as to extend in parallel with one another; and a plurality of upper electrodes formed on a second flat plane parallel to the first flat plane so as to extend in parallel with one another and to three-dimensionally cross the plurality of lower electrodes, wherein: each of the plurality of nonvolatile memory elements is provided at a corresponding one of three-dimensional cross-points where the plurality of lower electrodes and the plurality of upper electrodes cross each other, and each of the plurality of nonvolatile memory elements comprises: a resistance variable layer interposed between a corresponding one of the plurality of upper electrodes and a corresponding one of the plurality of lower electrodes at the corresponding one of the three-dimensional cross-points, the resistance variable layer containing a metal oxide material; and a rectifying element including a first electrode layer, a second electrode layer, and a blocking layer sandwiched between the first electrode layer and the second electrode layer, wherein: the resistance variable element and the rectifying element are connected to each other in series in a thickness direction of the resistance variable layer, and the blocking layer has a hydrogen barrier property.