Patent ID: 8563341

Claim:
A method for manufacturing a thin film transistor array substrate, the method comprising the steps of: providing a substrate; depositing sequentially a transparent conductive layer and a first metal layer on the substrate by a sputtering process, and patterning the transparent conductive layer and the first metal layer by a multi-tone mask forming a gate electrode and a common electrode, the gate electrode having the transparent conductive layer and the first metal layer, and the common electrode being formed by the transparent conductive layer; depositing sequentially a gate insulative layer and a semi-conductive layer on the substrate with the gate electrode and the common electrode, and patterning the semi-conductive layer by a second mask for retaining a region of the semi-conductive layer being there-above the gate electrode; depositing a second metal layer on the substrate with the gate insulative layer along with the retained semi-conductive layer, and patterning the second metal layer by a third mask for forming a source electrode and a drain electrode on the retained semi-conductive layer, wherein a pixel electrode is formed by the second metal layer on the gate insulative layer corresponding to the common electrode; and depositing a planarization layer on the pixel electrode and on the source electrode, the drain electrode and the retained semi-conductor layer of the thin film transistor, wherein the planarization layer is formed of a transparent insulating material.