Patent ID: 7393720

Claim:
A method for fabricating an electrical interconnect structure, adapted for a circuit board manufacturing process, the circuit board comprising a conductive substrate, the conductive substrate comprising a first conductive layer and a bump conductive layer, the bump conductive layer being disposed over the first conductive layer, the method comprising: patterning the bump conductive layer to form at least one bump over the first conductive layer; forming a dielectric layer over the first conductive layer and the bump, the dielectric layer covering a top surface of the bump; forming a second conductive layer over the dielectric layer; forming at least one blind hole in the second conductive layer and the dielectric layer, the blind hole passing through the second conductive layer and dielectric layer to expose the top surface of the bump; and filling a conductive material in the blind hole, the conductive material in the blind hole and the bump constituting a solid conductive post.