Patent ID: 7924062

Claim:
A sampling circuit operating in a sampling phase and a holding phase, comprising: an amplifier having a first input terminal and an output terminal for outputting an output signal; a first capacitor, coupled to the first input terminal, for sampling an input signal during the sampling phase; a second capacitor, having a first terminal coupled to the first input terminal and a second terminal coupled to the output terminal during the holding phase and decoupled from the output terminal during the sampling phase, for sampling a reference signal during the sampling phase and receiving charges from the first capacitor during the holding phase; and a voltage source, coupled between the first input terminal and the output terminal, for providing a predetermined voltage level during the sampling phase to eliminate difference between an input common mode voltage and an output common mode voltage of the amplifier; wherein the input common mode voltage of the amplifier is different from the reference signal; and wherein the output common mode voltage of the amplifier is different from the reference signal.