Patent ID: 8691655

Claim:
A method for fabricating a semiconductor integrated circuit (IC), the method comprising: receiving a semiconductor device, the semiconductor device including: a semiconductor substrate having a field-effect transistor (FET) region and a high resistor (Hi-R) region; a dummy gate stack with a first hard mask in the FET region, and a Hi-R stack including the first hard mask disposed over a dummy gate in the Hi-R region; recessing the first hard mask to form a first recess in an upper portion of the first hard mask, a bottom of the first recess being lower than an upper surface of the first hard mask; removing the first hard mask; forming a second recess in an upper portion of the dummy gate of the Hi-R stack; forming a second hard mask in the second recess in the Hi-R stack; and performing a gate trench etch on either side of the second hard mask, thereby forming a Hi-R.