Patent ID: 8269712

Claim:
A gate driving circuit for providing a plurality of gate signals to a plurality of gate lines, the gate driving circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals to a high voltage level according to a driving control voltage and a first clock; a buffer unit for receiving an input signal; an energy-store unit, electrically connected to the pull-up unit and the buffer unit, for providing the driving control voltage to the pull-up unit through performing a charging process based on the input signal; a first discharging unit, electrically connected to the energy-store unit, for pulling down the driving control voltage according to the first clock and the Nth gate signal; a second discharging unit, electrically connected to the energy-store unit, for pulling down the driving control voltage to a low power voltage according to an (N+1)th gate signal of the gate signals; a first pull-down unit, electrically connected to the Nth gate line, for pulling down the Nth gate signal to the low power voltage according to a second clock having a phase opposite to the first clock; a second pull-down unit, electrically connected to the Nth gate line, for pulling down the Nth gate signal to the low power voltage according to the (N+1)th gate signal; and an auxiliary unit, electrically connected between the Nth gate line and the first discharging unit, for controlling an auxiliary electrical connection between the Nth gate line and the first discharging unit according to the first clock; wherein an end of the first discharging unit electrically connected to the auxiliary unit is not electrically connected to the lower power voltage when the auxiliary unit is turned on.