Patent ID: 7672181

Claim:
A semiconductor memory, comprising: a plurality of memory cells each having a storage part of data and a transfer transistor; a plurality of sub word lines each coupled to a gate of the transfer transistor; a bit line coupled to the storage part via the transfer transistor; a plurality of sub word decoders provided with corresponding to the sub word lines, and having a first switch turning on when a main word line is in an activation level to couple any of the sub word lines to a high level voltage line, a second switch turning on when the main word line is in an inactivation level to couple the sub word line to a low level voltage line, and a third switch turning on when a word reset signal line is in an activation level to couple the sub word line to the low level voltage line; and a reset control circuit disabling one of the inactivation of the main word line and the activation of the word reset signal line to disable that one of the second switch and the third switch turns on during a test mode.