Patent ID: 7888967

Claim:
A voltage-level translator circuit comprising: a first MOS transistor of a first type, having a gate configured to receive input data varying between a first voltage level and a second voltage level smaller than the first voltage level, the first MOS transistor having a source coupled to a first node and a drain coupled to a second node; a second MOS transistor of the first type, having a gate configured to receive an inverse of the input data, a source coupled to the first node, and a drain coupled to a third node; a third MOS transistor of a second type, having a gate coupled to the third node, a source coupled to a fourth node, and a drain coupled to the second node; a fourth MOS transistor of the second type, having a gate coupled to the second node, a source coupled to the fourth node, and a drain coupled to the third node the third node being configured to issue output data corresponding to the input data and the second node being configured to issue an inverse of the output data, the output data varying between a third voltage level and the second voltage level, the third voltage level being greater than the first voltage level; first and second branches between the second node and the fourth node, the second branch having a smaller impedance than the first branch; third and fourth branches between the third node and the fourth node, the fourth branch having a smaller impedance than the third branch; and a selection unit configured to activate the second branch and deactivate the fourth branch before the second node switches from the second voltage level to the third voltage level and configured to deactivate the second branch and activate the fourth branch before the second node switches from the third voltage level to the second voltage level.