Patent ID: 8654575

Claim:
A solid-state memory cell, comprising: a storage element, having first and second complementary latched storage nodes, the storage element including two load transistors plus two driver transistors, each of the load and driver transistors having a high threshold voltage; a first read buffer coupled to the first storage node and to a first read bit line, the first read buffer selectively driving a data level at the first read bit line responsive to a read word line signal, the first read buffer including a first read driver transistor having a conduction path connected to a read reference voltage and having a control terminal coupled to the first storage node plus a first read pass transistor having a conduction path connected between the conduction path of the first driver transistor and the first read bit line, the first read pass transistor having a control terminal for receiving the read word line signal, the first read driver transistor and the first read pass transistor having a low threshold voltage, the first read driver transistor and the first read pass transistor also having a larger channel width than a channel width of the load and driver transistors; and a write element, comprising: at least one write select transistor, having a conduction path connected to a write reference voltage, and having a control electrode for receiving a write word line signal; a first write pass transistor having a conduction path connected between the first storage node and the conduction path of a write select transistor, and having a control electrode for coupling to a first write bit line; and a second write pass transistor having a conduction path connected between the second storage node and the conduction path of a write select transistor, and having a control electrode for coupling to a second write bit line.