Patent ID: 7507633

Claim:
A method for implementing alignment of a semiconductor device structure, the method comprising: forming first and second sets of alignment marks within a lower level of the structure, said second set of alignment marks adjacent said first set of alignment marks, wherein said first set of alignment marks includes both alignment marks and overlay boxes, and said second set of alignment marks includes both alignment marks and overlay boxes; forming an opaque layer over said lower level, including said first and second sets of alignment marks; opening a portion of said opaque layer corresponding to the location of said first set of alignment marks so as to render said first set of alignment marks optically visible while said second set of alignment marks initially remains covered by said opaque layer; lithographically patterning said opaque layer, using said optically visible first set of alignment marks; and measuring overlay errors with respect to said overlay boxes included within said second set of alignment marks; and adjusting said measured overlay errors by a constant offset, said constant offset representing an offset between said overlay boxes included within said first set of alignment marks and said overlay boxes included within said second set of alignment marks, thereby effectively measuring overlay errors with respect to said overlay boxes included within said first set of alignment marks.