Patent ID: 7948035

Claim:
A memory array comprising: a first insulating/dielectric layer formed on a semiconducting body; a charge trapping dielectric layer formed over the first insulating/dielectric layer; a second insulating/dielectric layer formed over the charge trapping dielectric layer; at least one bit line formed in the semiconducting body that respectively operates as an acting source and acting drain; a discharging circuit, wherein the discharging circuit is electrically connected to a first discharge terminal; a first word line formed over the second insulating/dielectric layer and orthogonal to the at least one bit line; a second word line formed over the second insulating/dielectric layer and orthogonal to the at least one bit line and parallel to the first word line, wherein the second word line is directly coupled to the discharging circuit exclusively by a contact level and a first metal level; and a shorting path electrically connecting the first word line to the second word line, wherein the shorting path comprises a resistance higher than the first word line or the second word line.