Patent ID: 8751853

Claim:
A Quad-Data Rate (QDR) controller, comprising: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module; the arbiter is configured to arbitrate commands and data according to a state of the control state machine; the control state machine is configured to manage a state of a controller and provide state basis for the arbiter to arbitrate the commands and the data; the read data sampling clock generating module is configured to generate read data sampling clocks with a same source, a same frequency and different phases; the read data path calibrating module is configured to determine, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data respectively when the read data path module reads data by reading training words when the control state machine is in “read data path calibrating state”; the read data path module is configured to synchronize positive edge read data and negative edge read data that are in a non-system clock domain to a system clock domain according to the sampling clocks determined by the read data path calibrating module.