Patent ID: 7894026

Claim:
A thin film transistor array panel comprising: a gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a passivation layer formed on the data line; a pixel electrode formed on the passivation layer and connected to the thin film transistor; and a shielding electrode formed on the passivation layer, wherein the shielding electrode is formed on the same layer as the pixel electrode, wherein the shielding electrode extends along the data line and substantially fully covers the data line, and an edge of the pixel electrode parallel to the data line is disposed adjacent to an edge of the shielding electrode with an entire gap between the adjacent edges of the pixel electrode and the shielding electrode narrower than a width of the pixel electrode, and wherein the entire gap between the adjacent edges of the pixel electrode and the shielding electrode is substantially uniform.