Patent ID: 8319531

Claim:
A divider circuit comprising: M first dividers configured to receive M first signals, where M is an integer of 2 or more; and N second dividers configured to receive N second signals, where N is an integer more than or equal to M, wherein an I-th one of the first dividers outputs a third signal obtained by dividing a frequency of one of the first signals input to the I-th first divider according to an output of a J-th first driver, where I is an integer of 1 to M, J is I−1, and J is 1 or M when I is 1 and a K-th one of the second dividers inputs the third signal and outputs a fourth signal having a frequency similar to that of the third signal input to the K-th second divider based on one of the second signals input to the K-th second divider, where K is an integer of 1 to N.