Patent ID: 7916133

Claim:
A buffer circuit comprising: a first comparator in which a comparing portion is constituted by one of P channel and N channel MOS transistors provided between an input terminal and an output terminal of a buffer amplifier for comparing an input voltage and an output voltage of the buffer amplifier and a predetermined offset voltage is set for the comparing operation in the comparing portion, and which performs the comparing operation when the predetermined offset voltage is exceeded, and a first switch circuit which turns ON/OFF in response to an output signal from the first comparator, wherein a leading up of an output voltage or a trailing down of an output voltage from the buffer amplifier is accelerated by flowing current from a power source line to the output terminal or from the output terminal to a reference potential line in response to ON or OFF of the first switch circuit, the buffer circuit further comprising a second comparator of which a comparing portion is constituted by the other of P channel and N channel MOS transistors for comparing the input voltage and the output voltage, and an operation restricting circuit for restricting the comparing operation of the second comparator in a range of a dead band of the one of P channel and N channel MOS transistors, wherein the first switch circuit is turned ON or OFF in response to the output signal of the first comparator and an output signal of the second comparator.