Patent ID: 7709336

Claim:
A method for forming a semiconductor integrated circuit device comprising: providing a semiconductor substrate; forming a gate dielectric layer overlying the semiconductor substrate; forming a gate layer overlying the gate dielectric layer, the gate layer being overlying a channel region in the semiconductor substrate; forming a metal hard mask overlying the gate layer; patterning the gate layer, including the metal hard mask layer, to form a gate structure including edges; forming only a single dielectric layer overlying the gate structure and the metal hard mask layer to protect the gate structure including the edges; patterning the dielectric layer to form single-layer sidewall spacer structures on the gate structure, including the edges, while exposing a portion of the metal hard mask layer; etching a source region and a drain region adjacent to the gate structure using the dielectric layer and portion of the metal hard mask layer as a protective layer; depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region; maintaining the gate structure free from any silicon germanium residues; causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region; and forming a contact structure on the metal hard mask, the metal hard mask being in physical and electrical contact with the gate structure.