Patent ID: 7139211

Claim:
A semiconductor memory device comprising: a cell area including a first and a second cell areas, wherein each cell area is provided with a plurality of cell blocks and a plurality of bit line sense amplifying units; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first cell area and the second cell area; an IO sense amplifying means including a plurality of first IO sense amplifiers and a plurality of second IO sense amplifiers, wherein the first IO sense amplifiers are disposed at one side of the cell area and the second IO sense amplifiers are disposed at the other side of the cell area; a plurality of first data lines for transferring a first data sensed and amplified at the bit line sense amplifier of the first cell area throughout the first I/O sense amplifiers; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area throughout the second I/O sense amplifiers.