Patent ID: 8688952

Claim:
A processor connected to a main memory unit, the processor comprising: a plurality of translation lookaside buffers (TLBs) holding as entries a portion of a conversion table for conversion between virtual addresses and physical addresses that has been stored in a main memory unit, a TLB of the plurality of TLBs including, for each of the entries registered therein, a valid bit that indicates whether a corresponding entry is valid and a relocation bit that indicates that the corresponding entry is not directly output from the main memory unit but is output from another TLB of the plurality of TLBs; a determining unit that determines whether an entry output from the main memory unit has already been registered in an entry of a registering destination of a TLB of the plurality of TLBs; and a control unit that evicts the entry that has already been registered and registers the evicted entry in another TLB of the plurality of TLBs, the evicted entry being registered, with a corresponding relocation bit validated, in an entry having a smallest entry number from among entries that are already registered in the another TLB and that have a respective valid bit set to indicate the corresponding entry is invalid when the determining unit determines that an entry has already been registered in the registering destination of the TLB.