Patent ID: 7936766

Claim:
A device, including: a processor; a memory storing a set of protocols for controlling the execution of the processor, the set of protocols comprising: a first protocol including a first protocol stack configured to process data packets of a first type, wherein the first protocol is initialized independently of other software in an operating system and includes a first variable; a second protocol including a second protocol stack configured to process data packets of a second type, wherein the second protocol is initialized independently of the other protocols in the operating system and includes a second variable; a third protocol configured to receive data packets of the first type and the second type and direct the data packets of the first type to the first protocol and the data packets of the second type to the second protocol, wherein, when the first variable and a third variable are set to an up state, the first protocol is attached to the third protocol for processing the first data packets, and when, the second variable and a fourth variable are set to an up state, the second protocol is attached to the third protocol for processing the second data packets; and a multiplexer command interposed between the third protocol and the first and second protocol, wherein each of the first, second and third protocols attach to the multiplexer command and data packets directed from the third protocol travel through the multiplexer command to the first and second protocols.