Patent ID: 8433880

Claim:
A method of handling memory access requests in a digital memory system, said method comprising: receiving a first memory access request, said first memory access request identifying a first virtualized memory address in a virtualized memory address space; translating said first virtualized memory address into a first physical memory address wherein said physical memory address space is larger than said virtualized memory address space, said translating comprising accessing a set of entries from a virtualized translation table using a first subset of said first virtualized memory address as an index, identifying a first memory bank from a set of N memory banks that currently represents said first virtualized memory address, and generating said first physical memory address using said first memory bank and a second subset of said first virtualized memory address; handling said first memory access request with a physical memory system using said first physical memory address; storing said set of entries from said virtualized translation table into a temporary register when said first memory access request is a read request; receiving a subsequent memory write request to said first virtualized memory address at least one clock cycle after receiving said first memory access request; and accessing said set of entries from said temporary register to identify a physical memory write location to handle said memory write request.