Patent ID: 7682907

Claim:
A method of making a nonvolatile memory including a plurality of non-volatile memory cells in rows and columns, the method comprising: providing a first region of a first conductivity type in a semiconductor substrate; forming a plurality of parallel pairs of implant regions in the first region in the form of parallel lines; forming dielectric isolation region lines in the first region, said isolation region lines being parallel to the implant region lines, wherein one of the isolation region lines is between adjacent pairs of the implant region lines, wherein respective subportions of one of the implant region lines of each pair will be a source region for each of a plurality of memory cells in a column of the memory cells, an adjacent respective subportion of the other of the implant region lines of the pair will be a drain region for each of the memory cells of the column, and a respective intervening portion of the first region between the diffusion region lines of the pair will be a channel region of the respective memory cell; forming a plurality of tunnel dielectric layers on a top surface of the first region, with each of the memory cells including one of the tunnel dielectric layers in contact with the source of the memory cell; depositing and patterning a first polysilicon layer to obtain polysilicon stripes, wherein the tunnel oxide layer at each of the memory cells is in contact with one of the first polysilicon layer stripes; forming a first dielectric layer over a top surface of each of the first polysilicon layer stripes; depositing a second polysilicon layer over the first dielectric layer, and patterning the second polysilicon layer to obtain stripes perpendicular to the pairs of implant region lines, with each said second polysilicon layer stripe overlying a plurality of memory cells of a row of the memory cells, the second polysilicon layer stripe being entirely separated from a surface of the first region by a dielectric layer; and etching the first polysilicon layer using the second polysilicon layer stripes as a mask, in order to produce a rectangle of the first polysilicon layer at each of the memory cells.