Patent ID: 7521767

Claim:
A MOS transistor, comprising: a semiconductor substrate of a first conductivity type; an insulated gate pattern including a gate electrode on the substrate and a capping layer on the gate electrode, the insulated gate pattern having sidewalls formed on a predetermined region of the semiconductor substrate of the first conductivity type so that portions of the semiconductor substrate of the first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern; impurity regions of a second conductivity type formed in a surface of the semiconductor substrate of the first conductivity type at at least one side of the insulated gate pattern; and a conformal polycrystalline pad of the second conductivity type formed on the impurity regions to directly contact and cover at least the impurity regions, wherein: the conformal polycrystalline pad covers a portion of each of the sidewalls of the insulated gate pattern and exposes a portion of each of the sidewalls of the insulated gate pattern, the gate electrode has sidewalls that form a section of the sidewalls of the insulated gate pattern, the conformal polycrystalline pad extends above a bottom of the gate electrode so as to cover a portion of each of the sidewalls of the gate electrode and exposes a portion of each of the sidewalls of the gate electrode, and the capping layer is an insulator.