Patent ID: 8539427

Claim:
A method of providing a device mismatch corner model for semiconductor device simulation, comprising: selecting a type of electric performance target F for a type of device; determining a number N of semiconductor devices for which mismatches among electric performance targets of the semiconductor devices are simulated; determining a desired k-sigma mismatch corner value among N(N−1)/2 pairs of the electric performance targets; identifying at least one electric parameter P of the semiconductor devices that has a mismatch component and contributes to the mismatches among the electric performance targets of the semiconductor devices; determining a plurality of corner values for the at least one electrical parameter P; running at most N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations; and post-processing results of the N circuit simulations to achieve simultaneous mismatch among N(N−1)/2 pairs of the electric performance targets, wherein at least the step of the running at most N circuit simulations is implemented on a processor.