Patent ID: 8045395

Claim:
A bit line driver system coupled to a plurality of bit lines, the bit lines being coupled to respective columns of non-volatile memory cells, the bit line driver system comprising: a plurality of bit line drivers, each bit line driver being coupled to a respective one of the bit lines, each of the bit line drivers including a bias transistor through which an input data signal is coupled to the respective bit line, each of the bias transistors having a respective gate; a current generator generating a reference current; a current mirror circuit coupled to receive the reference current from the current generator, the current mirror including a diode-coupled reference transistor through which a mirrored current is conducted so that the reference transistor generates a reference voltage between a source and a drain of the reference transistor; and a bias voltage generator coupled to receive the reference voltage from the current mirror circuit, the bias voltage generator being operable to generate a bias voltage corresponding to the reference voltage, the bias voltage generator being coupled to supply the bias voltage to the respective gates of the bias transistors.