Patent ID: 8482319

Claim:
A circuit comprising: a bias generation circuit electrically connected to a high voltage power supply to generate a biasing current during a startup period of a driver circuit in which an internal power supply fails to supply an internal voltage; a current mirror electrically connected to said bias generation circuit and a ground, the current mirror comprising a first plurality of transistors electrically connected to each other to receive the bias current and to output a mirrored bias current; and a second plurality of transistors electrically connected to said current mirror and each other to receive the mirrored bias current, wherein: a first one of said second plurality of transistors receives and amplifies the mirrored bias current, a second one of said second plurality of transistors receives the amplified mirrored bias current and puts an internal reference voltage node in a first logic state, and a third one of said second plurality of transistors receives the amplified mirrored bias current and puts a high voltage transistor gate node in the first logic state, and wherein putting the internal reference voltage node and the high voltage transistor gate node in the first logic state turns off the high voltage transistor.