Patent ID: 7374972

Claim:
A micro package manufacturing method comprising: (a) bonding at least one device substrate and at least one protection cap by patterning at least one bonding substance on a first predetermined area of the device substrate; (b) etching away a second predetermined area comprising a portion of the device substrate, a portion of the bonding substance and a portion of the protection cap in a first predetermined shape to form at least one layer; (c) etching away a third predetermined area comprising another portion of the protection cap in a second predetermined shape to form at least one via, whereby the via is electrically connected to an upper surface of the device substrate through the bonding substance; (d) depositing the layer and the via on the etched second predetermined area and in the etched third predetermined area, respectively; (e) forming at least one under-barrier metal (UBM) on the via; (f) forming at least one solder mask on a fourth predetermined area on an upper surface of the protection cap; (g) forming at least one solder bumper, being a connection terminal for an external signal, on the UBM; and (h) cutting the layer and separating out the micro package.