Patent ID: 7723174

Claim:
A method, comprising: forming a gate electrode structure above a silicon-containing semiconductor region, said gate electrode structure comprising a cap layer, a first etch stop layer located below said cap layer, a first polycrystalline silicon layer located below said first etch stop layer, and a second etch stop layer located below said first polycrystalline silicon layer; forming a strain-inducing semiconductor alloy in recesses in said silicon-containing semiconductor region laterally offset from said gate electrode structure; forming drain and source regions in said semiconductor region and said semiconductor alloy; removing said cap layer and said first etch stop layer; removing material of said strain-inducing semiconductor alloy so as to recess said drain and source regions and removing material of said gate electrode structure including at least said first polycrystalline silicon layer to reduce a height of said gate electrode structure using said second etch stop layer as an etch stop; and forming a strain-inducing layer above said drain and source regions.