Patent ID: 8427884

Claim:
A method of determining in an N-bit string a number of bits, M, having a first binary value relative to a number of bits N−M having a second binary value, comprising: providing N latch circuits in a daisy chain, wherein each latch circuit has a tag bit and acts as either a no-pass or a pass gate, depending on the tag bit having a “no-pass” or “pass” value respectively; loading into the N latch circuits respective ones of the N bits of the N-bit string as respective loaded bits; initially setting the tag bit at each latch circuit according to the respective loaded bit, such that when the respective loaded bit is of the first binary value the tag bit is set to the “no-pass” value and when the respective loaded bit is of the second binary value the tag bit is set to the “pass” value; providing a clock signal having a pulse train, each pulse having a fixed width; passing the pulse train through the daisy chain, wherein for a latch circuit acting as a pass gate the pulse train passes straight through and for a latch circuit acting as a no-pass gate, a leading pulse of the pulse train resets the tag bit from the “no-pass” to the “pass” value so that the no-pass gate of the latch circuit is reset to a pass gate in a period of the pulse width and the pulse train drops the leading pulse at the latch circuit before the rest of the pulse train moves to the next latch circuit down the daisy chain; gating the clock signal with a gating signal that is asserted whenever any one of the N latch circuits is generating a tag bit of the “no-pass” value; and obtaining M by determining the number of pulses missing from the pulse train of the gated clock signal after all the N latch circuits are generating a tag bit of the “pass” value.