Patent ID: 8230408

Claim:
A method comprising: compiling a hardware description language (HDL) description of an electronic system into a plurality of programs, each of the plurality of programs comprising a plurality of instructions that are processor-executable to realize at least a portion of the operation of the electronic system, wherein said compiling comprises: separating dataflow elements described in the HDL description from control logic described in the HDL description; generating at least a first set of arithmetic/logic instructions based on the dataflow elements and a second set of control flow instructions based on the control logic, wherein the first set of instructions does not comprise control flow instructions, and wherein the second set of instructions does not comprise arithmetic/logic instructions; and arranging the first set of arithmetic/logic instructions and the second set of control flow instructions into a corresponding plurality of program partitions, wherein each program partition comprises dataflow operations corresponding to respective dataflow elements that are connected together, and control operations corresponding to control logic that controls the respective dataflow elements; and downloading each of the plurality of program partitions to an instruction memory of one of a plurality of processors; wherein the plurality of program partitions are executable on the plurality of processors.