Patent ID: 8650379

Claim:
A data processing method for a nonvolatile memory system including a host central processing unit (CPU) and a memory link architecture (MLA) including a multiple access memory, an Application Specific Integrated Circuit (ASIC), and a nonvolatile memory, the data processing method comprising: by operation of the host CPU, calling N data file segments indicated by a write request, and generating N payload data segments and logical addresses for the N payload data segments based on data file segments; transferring the N payload data segments and the logical addresses to the ASIC; using the ASIC, mapping the logical addresses onto physical addresses of the nonvolatile memory; using the ASIC, collectively generating corresponding metadata for all of the N payload data segments; and then, performing a single multi-segment transfer operation that includes; sequentially writing the N payload data segments to a data block in the nonvolatile memory, and thereafter, writing the corresponding metadata to a metadata block associated with the data block.