Patent ID: 7281091

Claim:
A storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and that is to be written to a cache memory or a memory as a result of the store request, comprising: a data storing unit receiving the store data from the store port, temporarily storing the store data, and comprised between the store port and the cache memory or the memory; and a data write controlling unit controlling a write of the store data from the store port to said data storing unit; and wherein: the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; said data storing unit receives the store data from the store port after the instruction processing device commits execution of the store request; said data storing unit comprises a plurality of write buffers which respectively store the store data received from the store port; and said data write controlling unit limits write buffers to a range from a write buffer in which data is stored most recently among the plurality of write buffers to a write buffer ahead by n buffers in an order where data is to be stored, when the instruction processing device simultaneously commits execution of a plurality of (n) store requests, and controls a data write to limited write buffers; and a unit resetting a flag which instructs the store port to write data to said data storing unit upon receipt of a cancellation signal of the store request transmitted from the instruction processing device is further comprised on a side of the store port.