Patent ID: 7471570

Claim:
An array of single-level polysilicon EEPROM memory cells arranged in a plurality of rows and columns, the array comprising: row and column driver circuits operable to select one or more rows and columns of memory cells, respectively, to apply a programming voltage comprising first and second half-write voltages associated with the row and column driver circuits, respectively, to the selected memory cells associated with the selected rows and columns, and to apply a stabilizing voltages comprising about half of the programming voltage to the remaining unselected memory cells of the array during a program or erase operation, wherein a maximum voltage between any two rows or any two columns is about half of the programming voltage; the EEPROM memory cells comprising: a MOS floating-gate transistor having a drain region connected to a column-source select line, for selecting and programming or erasing a first one of a column of selected memory cells; a gate capacitor or tunneling region; a coupling capacitor connected to a row control line for controlling program and erase operations of a first one of a row of selected memory cells; and a floating gate of the transistor coupled to the gate capacitor and the coupling capacitor at a common node therebetween, the floating gate used for storing a charge representing a data state of the memory cell.