Patent ID: 8438306

Claim:
A method of layer concurrency connecting two or more master Intellectual Property cores to a Network on the Chip (NoC) for an integrated circuit comprising: connecting two or more masters using a common tightly coupled protocol to a first interface of the NoC which is a communication-bus module that includes transaction flow control logic, registers, and volatile memory components including buffers to route requests and responses from masters to one or more target IP cores and back, even when the masters and targets connected to that NoC have different interface protocols, data width, or clock speed; wherein the NoC has internal flow control logic to support protocols, including OCP multithread protocol and AXI protocol, that support sending one or more responses back to the master, in which the requests were serviced out-of-order from the order in which the requests were issued from the master; converting a protocol, where a protocol conversion unit coupled between the two or more masters and the NoC, where the protocol conversion unit converts a request in the tightly coupled protocol that couples request phasing with response phasing over to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC; and configuring for arbitration amongst the two or more masters while any requests from the masters are still in the common tightly coupled protocol of the masters' first, and only then translating the requests in the tightly coupled protocol for the winning request by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.