Patent ID: 8237510

Claim:
A phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock comprising: a Voltage Controlled Oscillator (VCO) receiving a differential filter VCO control voltage; a plurality of filter comparators comparing the differential filter VCO control voltage values, said plurality of filter comparators generating a respective gate enable signal responsive to the compared differential filter VCO control voltage values; an up/down counter receiving a clock signal responsive to said respective gate enable signal and the wide range dynamic reference clock; and said up/down counter providing counter values to said VCO for selecting a respective frequency range for the VCO; a first latch coupled to a first pair of said filter comparators and a second latch coupled to a second pair of said filter comparators; a first AND gate coupled to said first latch receiving said respective gate enable signal, and a second AND gate coupled to said second latch receiving said respective gate enable signal; and a frequency divider for dividing a received wide range dynamic reference clock frequency signal and generating a divided reference clock frequency signal, each said first AND gate and said second AND gate receiving divided reference clock frequency signal, and said first AND gate providing an increment clock, and said second AND gate providing a decrement clock.