Patent ID: 6853212

Claim:
A digital system, comprising: a plurality of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit, with each of the storage circuits having a scan input and having a scan output with the scan input of each storage circuit connected to the scan output of another storage circuit to form a scan chain, each of the storage circuits comprising: a scan enable input for controlling a mode of operation of the storage circuit; a storage element with a node connected to a data output buffer for driving a data output terminal, the storage element selectively coupled to a data input terminal and the scan input in accordance with the scan enable input; a scan output buffer for driving the scan output and coupled to the storage element in a parallel manner with the data output buffer, the scan output buffer being responsively coupled to the scan enable input; wherein the scan output buffer is operable to provide a representation of the storage element when the scan enable input is in a first state, and to provide a steady signal when the scan enable input is in a second state; and wherein the scan output buffer comprises a third MOS transistor with a source/drain connected to a source/drain of a fourth MOS transistor in a series manner, another source/drain of the third MOS transistor connected to drive the scan output with no other devices in electrical connection path between the other source/drain of the third MOS transistor and the scan output and another source/drain of the fourth MOS transistor connected to a voltage source with no other devices in electrical connection path between the other source/drain of the fourth MOS transistor and the voltage source.