Patent ID: 8195849

Claim:
A device comprising: a first-in first-out memory (FIFO); a first access device comprising an input and an output, the output coupled to the FIFO to access the FIFO in response to asserted access cycles received at the input of the first access device; a first access cycle generator comprising an input to receive a first access signal comprising a first plurality of asserted access cycles at a first frequency and an output coupled to the input of the first access device to provide a second access signal based on the first access signal, in response to a desired fullness of the FIFO being met, the second access signal comprising a second plurality of asserted access cycles at the first frequency during time periods corresponding to time periods of the first access signal having asserted access cycles, and in response to the desired fullness of the FIFO not being met, the second access signal comprising a third plurality of asserted access cycles at the first frequency during time periods corresponding to time periods of the first access signal having asserted access cycles, the third plurality of asserted access signals including more asserted access signals than the second plurality of asserted access signals; and a second access cycle generator to receive a third access signal comprising a second plurality of asserted access cycles and an output coupled to the second access device to provide a fourth access signal based on the third access signal, the fourth access signal having a variable frequency based on the fullness of the FIFO.