Patent ID: 7999793

Claim:
Conversion circuitry comprising: circuitry for generating a first number of digital data numbers each having a second number of bits; and sorting circuitry for sorting the digital data numbers in order of their respective values, including a plurality of compare and swap state machines including a number of rows of the state machines and a number of columns of the state machines, each state machine having first and second inputs, first and second outputs, and a reset input, each state machine having an equal state to which the state machine can be reset wherein the first and second inputs and the first and second outputs all are equal, a swap state into which the state machine can be switched if it is in its equal state wherein the first and second inputs are swapped so as to be presented at the second and first outputs, respectively, if the first input is less than the second input, and a pass state into which the state machine can be switched if it is in its equal state wherein the first and second inputs are presented unchanged at the first and second outputs, respectively, if the first input is greater than the second input, wherein if the state machine is switched into either the swap state or the pass state, that state is locked into the state machine until a future reset signal occurs, wherein the first output of each odd-numbered state machine is connected to the second input of a state machine in a next column of the same row as that odd-numbered state machine, and the second output is connected to the first input of a state machine in a next lower row of a next column, wherein the second output of each even-numbered state machine is connected to the first input of a state machine in a next column of the same row as that even-numbered state machine, and the first output is connected to the second input of a state machine in a next higher row of a next column, and wherein the digital data numbers are shifted bit by bit, with most significant bits first, into the various first and second inputs of the state machines in a first column.