Patent ID: 8724391

Claim:
A semiconductor memory device comprising: a first select transistor and a second select transistor; a plurality of memory cells stacked above a semiconductor substrate and electrically connected in series between the first select transistor and the second select transistor; word lines electrically connected to the control gates of the memory cells; select gate lines electrically connected to gates of the first select transistor and the second select transistor; a driver circuit configured to output a first voltage; first transfer transistors electrically connected to the word lines and the select gate lines, the first transfer transistors being electrically connected to the driver circuit; bit lines electrically connected to the memory cells; a source line electrically connected to the memory cells; and a detection circuit configured to detect a second voltage applied to the bit lines and/or the source line and output a flag, wherein the driver circuit changes a value of the first voltage in response to the flag.