Patent ID: 8159627

Claim:
A pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects, comprising: a transparent substrate; a first metal layer disposed on said transparent substrate to form a pattern of a gate line, a gate electrode of a transistor and at least a shadow layer; a first insulation layer disposed on said first metal layer; an a-Si layer deposited on said first insulation layer to form a channel of said transistor, wherein said a-Si layer further includes at least a dummy layer disposed above said shadow layer; a second metal layer sputtered on said a-Si layer, so that a data line as well as a source electrode and a drain electrode of said transistor are formed and said dummy layer is located on one or both sides of the data line; said dummy layer further includes two strips, each of said strips is respectively disposed on said first insulation layer which is located at a lateral side of said data line, and under each of said dummy layers is correspondingly provided with said shadow layer; a second insulation layer disposed on said second metal layer that includes a plurality of through holes; and a transparent conductive layer located on said second insulation layer whereby said drain electrode of said transistor is electronically connected with said transparent conductive layer by means of said through holes.