Patent ID: 8397034

Claim:
A multi-port arbitration system, comprising: a write detection circuit configured to detect one or more write operations and generate a signal based on the detected operations, the write detection circuit coupled to each of a plurality of ports, wherein the plurality of ports is greater than two; an address coincidence detector coupled to the write detection circuit and each of the plurality of ports and configured to detect when two or more of the plurality of ports is addressing the same cell during a write operation; a plurality of clocks for the plurality of ports, wherein each of the plurality of ports is coupled with a different clock; and a deactivation pulse generator circuit coupled to the address coincidence detector and configured to generate a deactivation pulse synchronous with a first clock of the plurality of clocks and asynchronous with at least a second clock of the plurality of clocks, and to deactivate all but one of the two or more of the plurality of ports attempting to address the same cell during a write operation.