Patent ID: 7941651

Claim:
An apparatus comprising: a decoder to receive a first instruction of a first instruction format, the first instruction format including an opcode and a plurality of bytes of immediate data, the decoder to decode the first instruction to provide a first micro-operation to process a first portion of the plurality of bytes of immediate data and a second micro-operation to process a second portion of the plurality of bytes of immediate data; a storage medium coupled with the decoder to receive and to store the first and second micro-operations for execution; an execution unit having a first input coupled with the storage medium to receive the first and second micro-operations, and further having a first output coupled to a group of registers and a second output coupled to a logic unit, the execution unit responsive to the first micro-operation to store the first portion of the plurality of bytes of immediate data in a first portion of a first register of the group of registers, and responsive to the second micro-operation to provide the second portion of the plurality of bytes to the logic unit via the second output to initiate an operation in the logic unit to recombine the first and second portions of the plurality of bytes of immediate data; and the logic unit separate from and coupled to the execution unit and having a first input coupled to the group of registers to receive the first portion of the plurality of bytes of immediate data from the first portion of the first register and having a second input coupled to the execution unit to receive the second portion of the plurality of bytes of immediate data directly from the execution unit and to recombine the first and second portions of the plurality of bytes of immediate data responsive to the initiation of the recombination by the execution unit.