Patent ID: 8222712

Claim:
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a first principal surface and a second principal surface; (b) a CMOS integrated circuit portion provided in a first region of the first principal surface of the semiconductor substrate; and (c) a Schottky barrier diode portion provided in a second region of the first principal surface of the semiconductor substrate, wherein the Schottky barrier diode portion comprises: (c1) a first N-type semiconductor region provided in the first principal surface in the second region; (c2) a first field insulating film region having an opening and provided in the first principal surface in the first N-type semiconductor region; (c3) a P-type guard ring region provided in the first principal surface in the opening of the first field insulating film region so as to be in contact with and along an inner periphery of the first field insulating film region; (c4) a Schottky junction cathode portion in which the first N-type semiconductor region is exposed at the first principal surface within the P-type guard ring region; (c5) a silicide film provided over the first principal surface over the opening of the first field insulating film region; and (c6) an anode contact electrode provided over the silicide film over the opening of the first field insulating film region, wherein the anode contact electrode is provided primarily over the P-type guard ring region, and wherein the first principal surface of an outer peripheral portion of the first field insulating film region is such that the first N-type semiconductor region of the Schottky barrier diode portion is electrically isolated from the CMOS integrated circuit portion by a ring-shaped P-type isolation region.