Patent ID: 8043925

Claim:
A method of forming a semiconductor memory device, the method comprising: forming an interlayer dielectric layer on a semiconductor substrate; forming storage node contacts that extend through the interlayer dielectric layer; sequentially forming an etch stop layer and then a mold layer on the interlayer dielectric layer; forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, the support structures extending in a first direction; sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, the first mask patterns extending in a second direction crossing the first direction, the second sacrificial layer covering the first mask patterns to a uniform thickness, and the second mask patterns being formed in trenches in the second sacrificial layer between adjacent ones of the first mask patterns; removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks to form storage node electrode holes that expose surfaces of the storage node contacts; removing the first mask patterns and second mask patterns to expose the support structures; filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures; and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.