Patent ID: 7241684

Claim:
A method for forming a metal wiring of a semiconductor device, comprising steps of: forming an etch stop layer on a semiconductor substrate; forming a first inter metal dielectric on the etch stop layer, the first inter metal dielectric being formed of an inorganic material; forming a second inter metal dielectric on the first inter metal dielectric, the second inter metal dielectric being formed of an organic polymer material having a low permittivity; forming a first photoresist pattern defining a via hole on the second inter metal dielectric, wherein the etching selectivity of the second inter metal dielectric to the first inter metal dielectric is high; forming a via hole exposing the etch stop layer using the first photoresist pattern; forming a second photoresist pattern defining a trench by exposing and developing the first photoresist pattern; forming a trench by wet-etching the second inter metal dielectric so as to be undercut using the second photoresist pattern as a mask; removing the etch stop layer exposed through the via hole; and forming a metal wiring by filling the via hole and the trench.