Patent ID: 7439759

Claim:
A bus system for an integrated circuit device, the bus comprising a plurality of bus lines each of which connects a driver circuit and a receiver circuit; and a glitch sensor circuit which is operable to detect glitches on at least one of the bus lines, characterized in that each receiver circuit comprises: a first detector operably connected to receive a data signal from an associated bus line, and operable to detect a rising transition of the data signal with respect to a first threshold level, and to produce a first output signal upon detection of such a rising transition; a second detector operably connected to receive the data signal, and operable to detect a falling transition of the data signal with respect to a second threshold level, and to produce a second output signal upon detection of such a transition; output means operable to output the first or second output signal as a receiver output signal; and wherein the first and second threshold levels are variable.