Patent ID: 7631235

Claim:
Circuit testing equipment for testing a circuit that has at least one first integrated circuit (IC) that is operatively connected to a boundary-scan bus and at least one second IC that is not operatively connected to the boundary-scan bus, and for testing interconnections between the first IC and the second IC, the equipment comprising: a computer having stored thereon a boundary scan description language (BSDL) file for the first IC, and a netlist and a connections list for the circuit to be tested, and having loaded therein a test script specific to the second IC and independent of the first IC, the netlist and the connections list, for testing the second IC; and a connector for connecting the computer to the boundary scan bus of the circuit to be tested; the computer being arranged to parse the BSDL file, the netlist and the connections list, to find points from which selected pins of the second IC can be driven and read via the first IC, and to generate a data structure therefrom which defines pins of the first IC for driving pins of the second IC and pins of the first IC for reading pins of the second IC and which permits automated execution of the test script from the computer through the boundary scan bus to perform tests through the boundary scan bus by driving pins of the first IC to test that interconnections between the first IC and the second IC are properly connected and have no short-circuits.