Patent ID: 7713863

Claim:
A method for manufacturing a semiconductor device with a dual damascene structure, comprising: preparing a semiconductor substrate; forming a first interconnection layer over the semiconductor substrate; forming an organic insulating film over the first interconnection layer; forming a via hole in the organic insulating film; forming an inorganic insulating film so that the inorganic insulating film covers an upper surface of the organic insulating film and an interior of the via hole; forming a hard mask pattern on the inorganic insulating film; forming an interconnection groove by etching the inorganic insulating film with the hard mask pattern as an etching mask until the inorganic insulating film inside said via hole is removed; filling the via hole and the interconnection groove with a conductive substance, wherein forming said hard mask pattern on said inorganic insulating film includes forming a hard mask on said inorganic insulating film, forming a second resist pattern with an opening on the hard mask, and etching the hard mask with the second resist pattern as an etching mask; and removing the second resist pattern, before said forming an interconnection groove.