Patent ID: 7308665

Claim:
An apparatus for analyzing a clock delay of a target circuit, comprising: an input unit receiving circuit information on the target circuit; a first calculating unit calculating a first parameter and a second parameter based on the received circuit information wherein the first parameter determines a first probability density function of a delay of a data path of the target circuit, and the second parameter determines a second probability density function of a delay of a clock path of the target circuit; a second calculating unit calculating a third parameter that determines a third probability density function of a difference between the delay of the data path and the delay of the clock path, based on the first parameter and the second parameter; and a third calculating unit calculating a clock-delay value of the target circuit, based on the third probability density function; a storage unit storing information on a delay of each circuit element of the target circuit; and an extracting unit extracting, from the storage unit based on the circuit information, first information on delays of circuit elements on the data path and second information on delays of circuit elements on the clock path; and the first calculating unit calculating the first parameter and the second parameter based on the first information and the second information, respectively.