Patent ID: 7058754

Claim:
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in a plurality of blocks; each block having a plurality of non-volatile memory cells arranged in a plurality of rows and columns; a plurality of local bit lines in each block not extending to an adjacent block with each local bit line connecting cells in the same column; a plurality of row lines in each block with each row line connecting cells in the same row; a plurality of global column lines, each global column line associated with a plurality of local bit lines with each local bit line from a different block; a plurality of switches in each block, each switch for connecting a local bit line to its associated global column line; each switch being activatable by a switch signal supplied on a select line connected to the switch; a row decoder connected to the plurality of row lines and the select line of each block; a column decoder connected to the plurality of global column lines; and a controller circuit for determining when memory cells of a first block are to be erased and when memory cells of a second block are to be programmed and to activate the row decoder associated with said second block to cause the switches of said second block to connect the local bit lines of said second block to the global column lines causing simultaneous erasure of memory cells of said first block and programming of memory cells of said second block.