Patent ID: 7792656

Claim:
A test apparatus that tests a device under test, comprising: a plurality of testing units that are mapped to a control bus address space and that test the device under test; a control processor that executes a plurality of test control programs to control each testing unit corresponding to each test control program; a plurality of address registers that are mapped to a control processor address space and store an address in the control bus address space of one of the testing units when written thereon by the control processor; and a plurality of data registers that are mapped onto the control processor address space, that are disposed to correspond one-to-one with the plurality of address registers, and that store data that is written thereto and read therefrom by the testing unit designated by the address stored in the corresponding address register, wherein the control processor allocates at least one address register and one data register to each test control program and writes test data and address data generated according to each test control program onto the corresponding address register and data register.