Patent ID: 8384200

Claim:
A semiconductor device assembly comprising: a substrate including a plurality of conductive terminals disposed on or in a surface thereof; a first semiconductor die including an active surface and a plurality of bond pads disposed in a first selected connection pattern on or in the active surface; a second semiconductor die including an active surface and a plurality of bond pads disposed in a second selected connection pattern on or in the active surface of the second semiconductor die, the active surface of the first semiconductor die facing the active surface of the second semiconductor die; a plurality of conductive structures, each conductive structure of the plurality being electrically and structurally coupled to a bond pad of the first semiconductor die and a bond pad of the second semiconductor die; a plurality of laterally extending conductive elements, a first end of each laterally extending conductive element being structurally and electrically coupled to a conductive terminal of the substrate, a second end of each laterally extending conductive element being structurally and electrically coupled to at least one of a bond pad of the first semiconductor die, a bond pad of the second semiconductor die, and a conductive structure of the plurality of conductive structures; and a plurality of discrete dielectric structures disposed between and in contact with each of the active surface of the first semiconductor die and the active surface of the second semiconductor die; wherein an intermediate portion of at least one laterally extending conductive element of the plurality of laterally extending conductive elements, between the first end and the second end of the at least one laterally extending conductive element of the plurality, passes through at least one discrete dielectric structure of the plurality of discrete dielectric structures; wherein each discrete dielectric structure is in physical contact with both the active surface of the first semiconductor die and the active surface of the second semiconductor die.