Patent ID: 7401107

Claim:
A data processing apparatus for converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, where n is less than m, the data processing apparatus comprising: determination logic operable to determine the bit location of the most significant bit of the value expressed within the m-bit fixed point number; low order bit analysis logic operable to determine from a selected number of least significant bits of the m-bit fixed point number a rounding signal indicating whether a rounding increment is required in order to generate the n-bit significand; generation logic operable in response to the rounding signal to generate a rounding bit sequence appropriate having regard to the bit location determined by the determination logic; adder logic operable to add the rounding bit sequence to the m-bit fixed point number to generate an intermediate result; and normalization logic operable to shift the intermediate result to generate the n-bit significand.