Patent ID: 7480202

Claim:
A memory device, comprising: a memory array having a plurality of memory cells; a plurality of digitlines each connected to certain of said plurality of memory cells; and a plurality of peripheral devices for reading data out of and writing data into said memory array through said digitlines, said peripheral devices comprising: a plurality of first write drivers and a plurality of second write drivers, one of said plurality of first write drivers and one of said plurality of second write drivers each connected to a same one of said plurality of digitlines through one of a plurality of first input/output lines and one of a plurality of second input/output lines, respectively; and a plurality of first input/output devices and a plurality of second input/output devices responsive to one of a plurality of first column select signals and a plurality of second column select signals for controlling the connection of said plurality of first write drivers and said plurality of second write drivers, respectively, to said plurality of digitlines.