Patent ID: 7465664

Claim:
A method for fabricating a semiconductor device to lower source/drain sheet resistance, comprising: providing a semiconductor device with at least one gate region and two junction regions; forming a dielectric layer on the semiconductor device, wherein the dielectric layer is provided with a plurality of contact windows corresponding to the gate region and the two junction regions to expose a part of the gate region and the junction regions; depositing a silicon layer or SiGe epitaxial layer in the plurality of contact windows to cover the exposed gate region and the exposed junction regions; depositing a metal layer to cover the silicon layer or the SiGe epitaxial layer in the contact windows and the rest of the dielectric layer; and conducting a heat treatment of the semiconductor device in a nitrogen-containing environment, such that the silicon layer or the SiGe epitaxial layer and the metal layer are reacted, so as to convert the silicon layer or the SiGe epitaxial layer into a silicide.