Patent ID: 8116156

Claim:
A semiconductor memory device comprising: a memory cell array including a normal memory cell and a redundant memory cell that replaces the normal memory cell when it is defective; a first sub-word driver that selects the normal memory cell; a second sub-word driver that selects the redundant memory cell; a predecoder that predocodes an address to which access is requested irrespective of whether the address is a defective address; a main decoder that controls the first and second sub-word drivers based on a predecode signal generated by the predecoder; and a repair determining circuit that determines whether the address to which access is requested is the defective address, wherein a physical layout of the semiconductor memory device includes: the predecoder and the repair determining circuit having a shape in which a first direction is set to be a longitudinal direction, and the predecoder and the repair determining circuit are arranged adjacent to each other in the first direction, and are arranged in parallel with the main decoder, wherein the main decoder includes a plurality of first and second main word drivers that control the first and second sub-word drivers, respectively, the repair determining circuit includes a plurality of fuse sets each corresponding to an associated one of the second main word drivers, positions of the corresponding second main word driver and fuse set in the first direction are substantially matched, the memory cell array is divided into a plurality of memory mats, and wiring that connects the second main word driver and the fuse set is arranged on the corresponding memory mat.