Patent ID: 7539075

Claim:
A method for adjusting a trim setting used to trim a plurality of internally generated voltages of an integrated circuit, comprising: (a) receiving a target digital value for each of the plurality of internally generated voltages; (b) comparing the target digital value to a current digital value for each of the plurality of internally generated voltages; (c) adjusting the trim setting, for each of the plurality of internally generated voltages, based on a difference if the comparison indicates that the difference between the target digital value and the current digital value is greater than an allowable threshold; and (d) repeating steps (b) and (c) for each of the plurality of internally generated voltages until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold; whereby the plurality of internally generated voltages are each trimmed independently of each other according to steps (a) through (d).