Patent ID: 7006385

Claim:
A nonvolatile memory device comprising: a memory cell array having a plurality of nonvolatile memory cells capable of erasing data by applying high voltage; a control circuit generating an erase execution signal in response to an erase command signal received thereto, the control circuit stopping the erase execution signal and generating a discharge control signal in response to an erase termination signal received thereto, the control circuit stopping the discharge control signal in response to a discharge termination signal received thereto, the control circuit stopping the erase execution signal and the discharge control signal in response to a reset signal received thereto; a voltage boost circuit providing high voltage to the memory cell for erasing data in response to the erase execution signal; a timer circuit generating the erase termination signal when a predetermined time elapses after receiving the erase execution signal; a discharge circuit discharging the high voltage supplied from the voltage boost circuit in response to either one of the discharge control signal and the reset signal received thereto; and a sensor circuit being enabled in response to either one of the discharge control signal and the reset signal received thereto, the sensor circuit generating the discharge termination signal when the high voltage drops down to a predetermined voltage.