Patent ID: 8637995

Claim:
A semiconductor structure, comprising: a substrate comprising a layer of semiconductor material; a first metallization layer on the substrate over a first side of the layer of semiconductor material; a second metallization layer on the substrate over a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material; a plurality of through wafer interconnects extending at least partially through each of the first metallization layer and the layer of semiconductor material of the substrate; a first processed semiconductor structure carried by the substrate over the first side of the layer of semiconductor material; and a second processed semiconductor structure carried by the substrate over the first side of the layer of semiconductor material; wherein an electrical pathway extends from the first processed semiconductor structure, through a conductive feature of the first metallization layer, through a first through wafer interconnect of the plurality of through wafer interconnects, through a conductive feature of the second metallization layer, and through a second through wafer interconnect of the plurality of through wafer interconnects to the second processed semiconductor structure.