Patent ID: 8536048

Claim:
A method of manufacturing an electronic component, comprising: forming a lower wiring layer using a first sidewall transfer process, the first sidewall transfer process including: forming a first sidewall film having a closed loop along a first sidewall of a first sacrificed pattern formed on a first base material, removing the first sacrificed pattern to leave the first sidewall film, and selectively removing the first base material using the first sidewall film as a mask to form the lower wiring layer; forming one or more upper wiring layers located in a higher position than the lower wiring layer via another layer which is on the lower wiring layer using a second sidewall transfer process, the second sidewall transfer process including: forming a second sidewall film having a closed loop along a second sidewall of a second sacrificed pattern formed on a second base material, removing the second sacrificed pattern to leave the second sidewall film, and selectively removing the second base material using the second sidewall film as a mask to form the one or more upper wiring layers; and collectively performing etching for cutting each of the lower wiring layer and the one or more upper wiring layers to thereby apply a closed-loop cut to the lower wiring layer and the one or more upper wiring layers.