Patent ID: 6853035

Claim:
A memory device comprising: a first negative differential resistance (NDR) field effect transistor (FET) coupled to a storage node and a first voltage potential, wherein said first NDR FET is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential; and said first NDR FET having a first gate terminal coupled to a first voltage bias that is adapted to switch said first NDR FET; a second NDR FET coupled to said first NDR FET, said storage node and a second voltage potential wherein said second NDR FET is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential; said second NDR FET having a second gate terminal coupled to a second voltage bias that is adapted to switch said second NDR FET; a transfer field effect transistor (FET), coupled to said first NDR FET and second NDR FET, and adapted for transferring data to and from said storage node; said first NDR FET and said second NDR FET both including a trap layer in which charge traps are used to effectuate said first NDR characteristic and said second NDR characteristics; wherein said charge traps are distributed so as to cause the memory device to achieve a soft error rate (SER) of approximately 1,000 failures-in-time (FITs)/Mbit or less.