Patent ID: 8707115

Claim:
A micro controller comprising: an input and output unit having a reset terminal, a plurality of input terminals, and a test enable terminal; a test mode setting unit configured to allocate a first input terminal which is one of the plurality of input terminals to a test clock terminal and allocate the remaining N, where N is an integer equal to or more than 1, input terminals of the plurality of input terminals to L, where L is an integer equal to or more than 1, test terminals, in response to a signal output from the input and output unit; and a processor configured to control the input and output unit and the test mode setting unit, wherein the test mode setting unit includes: M, where M is an integer equal to or more than 2, flip-flops configured to receive a test clock signal from the first input terminal, receive a test signal from the N input terminals, and receive a test enable signal from the test enable terminal; and a decoder configured to decode a signal output from the M flip-flops and to allocate the N input terminals to the L test terminals.