Patent ID: 8193575

Claim:
A flash memory structure comprising: an isolation region embedded within a semiconductor substrate, the semiconductor substrate having a recessed surface adjacent to the isolation region, wherein sidewalls of the isolation region and the recessed surface of the semiconductor substrate define a first aperture, the first aperture having sidewalls provided by the isolation region that are perpendicular to a base surface of the first aperture, wherein the base surface of the first aperture is provided by the recessed surface of the semiconductor substrate, the recessed surface of the semiconductor substrate being below an upper surface of the semiconductor substrate; an active region at the base surface of the first aperture the semiconductor substrate; a tunneling dielectric located upon the active region at the base surface of the first aperture; a floating gate located upon the tunneling dielectric, the floating gate not rising above the isolation region and present on the sidewalls of the isolation region that provides the first aperture, wherein the floating gate has a U-shaped geometry with floating gate sidewalls that are perpendicular to a base of the floating gate at an intersection between the floating gate sidewalls and the base of the floating gate; a conformal intergate dielectric located upon the floating gate, wherein a sidewall of each end of the conformal integrate dielectric is aligned to a sidewall of each end of the floating gate; a control gate located upon the conformal intergate dielectric; and a plurality of source and drain regions located within the active region at locations not covered by the floating gate, wherein an upper surface of the source and drain regions are recessed relative to the upper surface of the semiconductor substrate and an upper surface of the isolation region.