Patent ID: 8479205

Claim:
A computer-readable, non-transitory medium storing a schedule control program for allocating threads to a plurality of groups of processor devices to execute the threads, the schedule control program causing a computer to perform a procedure comprising: storing an execution start time and identification information of a processor device when the processor device starts to execute a thread; calculating an elapsed time counted from the execution start time when the thread is re-allocated after being interrupted; setting a plurality of time parameters to first to n-th level cache memories in such a way that the higher a level of a cache memory, the larger time parameter is set, wherein n is a natural number equal to or greater than 3, and each of the groups of processor devices share 2 nd level cache memory and different groups of processor devices share n-th level cache memories whose levels are equal to or greater than 3, and the plurality of the groups of processor devices are connected to each other; determining an m-th level cache memory, which is among the first to n-th level cache memories, whose level is lowest of the first to n-th level cache memories expected to contain data used in the interrupted thread and shared by the different groups of processor devices, by comparing the elapsed time with the plurality of time parameters, successively from the time parameter of the first level cache memory to the time parameter of the n-th level cache memories, until the elapsed time is found to be smaller than the time parameter of the n-th level cache memories; and allocating the interrupted thread to a processor device with a lowest load which is selected from among the processor device that last executed the thread and other processor devices sharing the m-th level cache memory with the processor device that last executed the thread.