Patent ID: 7496732

Claim:
A processor, comprising: an instruction buffer to hold a plurality of instructions, the instruction buffer to support run-ahead execution of the plurality of instructions; an advance data table, indexed by said instruction buffer, to store a set of data for said plurality of instructions during the run-ahead execution, and to supply said set of data to at least one of said plurality of instructions during re-execution, each of said set of data intended for a target register of one of said plurality of instructions, and wherein said advance data table includes a valid bit for each of said set of data derived from poisoned status of source registers of the corresponding instruction, and wherein the advance data table is populated responsive to a cache miss; and a pipeline to issue more than one instruction in a single clock cycle during the re-execution when data required by said more than one instruction is either in said advance data table with valid bit being set valid or otherwise available.