Patent ID: 8493308

Claim:
A source driver, comprising: a plurality of first data channel pairs, each of the first data channel pairs comprising a first odd channel and a first even channel, and the first odd channel and the first even channel respectively used to output driving voltages having a first polarity or a second polarity during a first period; a plurality of second data channel pairs, each of the second data channel pairs comprising a second odd channel and a second even channel, and the second odd channel and the second even channel respectively used to output driving voltages having the first polarity or the second polarity during the first period; a first switch group coupled to the first data channel pairs and conducting the first odd channels to each other according to a horizontal synchronous signal during a second period, wherein when first switch group is turned on, the first odd channels are not conducted with the first even channels, the second odd channels, and the second even channels during the second period; a second switch group coupled to the first data channel pairs and conducting the first even channels to each other according to the horizontal synchronous signal during the second period; a third switch group coupled to the second data channel pairs and conducting the second odd channels to each other according to the horizontal synchronous signal during the second period; and a fourth switch group coupled to the second data channel pairs and conducting the second even channels to each other according to the horizontal synchronous signal during the second period, wherein the first data channel pairs and the second data channel pairs are alternatively arranged and respectively receive a first polarity control signal and a second polarity control signal to determine the polarities of driving voltages corresponding to the first odd channel, the first even channel, the second odd channel, and the second even channel; and wherein the first odd channels, the first even channels, the second odd channels, and the second even channels are repeatedly arranged in a cycle of four channels, in each cycle, the first odd channel, the first even channel, the second odd channel, and the second even channel are sequentially arranged, and the first even channel is directly adjacent to the first odd channel, the second odd channel is directly adjacent to the first even channel, and the second even channel is directly adjacent to the second odd channel, and the first odd channels, the first even channels, the second odd channels, and the second even channels each comprise a plurality of directly connected switches.