Patent ID: 6920594

Claim:
A method for laying out a scan test circuit for scan testing a combination logic circuit having at least a first logic macro using at least a first scan flip-flop circuit and a second scan flip-flop circuit, the method comprising: forming a wiring line for propagating scan test data in a polysilicon layer or a diffusion layer of the first logic macro in advance, the wiring line connecting a scan test data output terminal included in the first scan flip-flop circuit and a scan test data input terminal included in the second scan flip-flop circuit; and thereafter, connecting the data input terminal and the data output terminal included in the first scan flip-flop circuit and the second scan flip-flop circuit with the wiring line for propagating the scan test data that has been formed in the first logic macro by disposing the first logic macro between the first and the second flip flop circuits so as to be adjacent to both the first flip flop circuit and the second flip flop circuit by automatic placing and routing, wherein: in the first and the second scan flip-flop circuits each having the same vertical length as the first logic macro, the scan test data input terminal and the scan test data output terminal each extending to an end along the horizontal direction are formed in advance in a position spaced at a predetermined distance from a side portion with respect to the vertical direction; and in the first logic macro, both ends of the wiring line for propagating the scan test data that is formed in the polysilicon layer or a diffusion layer are placed in advance in a position spaced at the predetermined distance from a side portion with respect to the vertical direction so as to extend to ends along the horizontal direction.