Patent ID: 8756605

Claim:
A multithreaded processor comprising: an instruction buffer for storing instructions for a plurality of threads; at least one processor core for executing instructions stored in the instruction buffer; and a scheduler for selecting which of the plurality of threads will have an instruction scheduled for execution by monitoring a current thread state for each of the plurality of threads to determine whether each thread is ready to be scheduled for execution, whether each thread is currently executing and what condition is preventing each thread from executing, where the scheduler selects a first thread having a current thread state indicating that the first thread was least recently scheduled, wherein the scheduler selects which of the plurality of threads will have an instruction scheduled for execution by applying a priority rule that gives a higher priority to a thread that is in a ready state, a lower priority to a thread that is in a speculative ready state, and a lowest priority to a thread that is in a run state, wherein the scheduler selects which of the plurality of threads will have an instruction scheduled for execution by applying a priority rule that gives a highest priority to a thread that is in an idle state with an interrupt pending.