Patent ID: 8487398

Claim:
A semiconductor device comprising: an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric over the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode, and functions as a contact while being p-type; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, and functions as a contact while being p-type, wherein a portion of the isolated p-type well between the first p-type contact region and the second p-type contact region is under the p-type polysilicon electrode and the capacitor dielectric; an n-type isolation region surrounding the isolated p-type well on sides and a bottom of the isolated p-type well; a p-type semiconductor substrate, wherein the isolated p-type well is over the semiconductor substrate, and a horizontal portion of the n-type isolation region between the isolated p-type well and the p-type semiconductor substrate to isolate the isolated P-type well from the P-type semiconductor substrate; a semiconductor layer over the p-type substrate layer, wherein the isolated p-type well is in the semiconductor layer, and wherein a vertical portion of the n-type isolation region is between the isolated p-type well and the semiconductor layer; and a trench isolation region in the semiconductor layer comprised of an insulating material having an opening therethrough filled with conductive material, wherein the trench isolation region is over and in physical contact with the vertical portion of the n-type isolation region and the conductive material is in physical and electrical contact with a portion of the vertical portion of the n-type isolation region, and wherein the first p-type contact region extends laterally from the first sidewall of the p-type polysilicon electrode to the trench isolation region and the second p-type contact region extends laterally from the second sidewall of the p-type polysilicon electrode to the trench isolation region.