Patent ID: 8409461

Claim:
A printed wiring board manufacturing method, comprising: forming a multilayer printed wiring board having a conductive layer, an outermost conductive layer formed in an outer portion of the multilayer printed wiring board with respect to the conductive layer and electrically connected to the conductive layer, and a solder resist layer formed over the outermost conductive layer and having an opening exposing a portion of the outermost conductive layer; forming a sacrificial layer on a portion of a surface of the solder resist layer; forming a plurality of plating layers on the portion of said outermost conductive layer, said sacrificial layer and the solder resist layer such that the plurality of plating layers includes a first plating layer formed on the portion of the outermost conductive layer, the sacrificial layer and the solder resist layer and a second plating layer formed over the first plating layer and such that the first plating layer has a coefficient of thermal expansion which is higher than a coefficient of thermal expansion of the second plating layer; patterning the plurality of plating layers so as to shape a component mounting pin comprising a patterned portion of the plating layers; removing said sacrificial layer under the patterned portion of said plurality of plating layers; and erecting said component mounting pin such that the component mounting pin protrudes from the opening of the solder resist layer.