Patent ID: 7808408

Claim:
An analog-to-digital converter (ADC) system, comprising: a first ADC comprising a first ADC element, the first ADC element producing a first digital output signal in response to a first analog signal representing an analog input signal to be converted and a first clock signal representing a master clock signal; a second ADC comprising a second ADC element, the second ADC element producing a second digital output signal in response to a second analog signal representing the analog input signal to be converted and a second clock signal representing the master clock signal; a correction estimator, the correction estimator comprising gain logic, offset logic, and a slope detector, the slope detector producing a slope factor representing a slope of the analog input signal, the gain logic producing a gain signal in response to the first digital output signal and the second digital output signal, the offset logic producing an offset signal in response to the first digital output signal and the second digital output signal, wherein the correction estimator applies the gain signal to at least one of the first digital output signal and the second digital output signal and applies the offset signal to at least one of the first digital output signal and the second digital output signal, and wherein the correction estimator produces a correction signal in response to the first digital output signal, the second digital output signal and the slope factor; and a timing adjuster, the timing adjuster adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.