Patent ID: 7322000

Claim:
A semiconductor device providing access to system logic via a plurality of interface pins, the device comprising: an on-chip test module contained within the semiconductor device that is configured to generate an internal testing signal; a test access port configured to receive an external testing signal from a source outside the semiconductor device; a plurality of boundary shift registers each coupling one of the plurality of interface pins to the system logic, wherein each of the plurality of boundary shift registers is coupled to the other boundary shift registers by a common serial chain; and control logic configured to receive the internal testing signal from the built-in self test module and to serially scan the internal testing signal into the plurality of boundary shift registers via the common serial chain in an internal testing mode, and to provide the external testing signal to the plurality of boundary shift registers via the common serial chain in an external test mode to thereby facilitate both internal testing of the system logic and external testing of the interface pins with the common serial chain.