Patent ID: 7029932

Claim:
A method of testing an integrated circuit chip including a first terminal, a second terminal, and a third terminal, the method comprising: (a) providing first, second, and third ESD diodes on the integrated circuit chip, anodes of the first and second ESD diodes being coupled to the second terminal, cathodes of the first and third ESD diodes being coupled to the first terminal, an anode of the third ESD diode and a cathode of the second ESD diode being coupled to the third terminal, the first, second, and third ESD diodes having known first, second and third forward resistances, respectively; (b) pressing first, second, and third contact elements against the first, second and third terminals, respectively; (c) forcing a first reference current through a first circuit path including the second contact element, the second ESD diode, the third contact resistance, and the third contact element and measuring a first voltage across the first circuit path, forcing a second reference current through a second circuit path including the second contact element, the first ESD diode, and the first contact element and measuring a second voltage across the second circuit path, and forcing a third reference current through a third circuit path including the third contact element, the third ESD diode, and the first contact element and measuring a third voltage across the third circuit path; (d) solving three equations representative of the first, second, and third voltages to determine first, second, and third contact resistances between the first contact element and the first terminal, the second contact element and the second terminal, and the third contact element and the third terminal, respectively; and (e) performing a parametric test operation on the integrated circuit chip to determine a parameter dependent on a voltage of the third terminal by determining a first test current through the third contact resistance and using the first test current to determine a voltage drop across the third contact resistance, and computing a value equal to a measurement voltage of the third contact element offset by the amount of the voltage drop across the third contact resistance to obtain a more accurate measurement value representative of the voltage of the third terminal.