Patent ID: 8212318

Claim:
A high voltage NMOS transistor, comprising: a substrate having a surface; a deep n-well arranged near the surface of the substrate; a body which is isolated from the substrate via the deep n well; an n-doped source and drain arranged in the deep n well; a field oxide or a shallow trench region situated on the surface of the deep n-well between said n-doped source and drain; a p-doped channel region situated between the field oxide or shallow trench region and the n-doped source; and a gate partly covering said field oxide or shallow trench region and the p-doped channel region; wherein the deep n-well comprises a pinch-off region located under a middle of the field oxide or shallow trench region; wherein a depth of the deep n-well varies in the pinch off region; wherein a height of the substrate is greatest at the middle of the field oxide or shallow trench region and is greater than near the n-doped source and drain; and wherein the gate extends over the pinch-off region.