Patent ID: 7366971

Claim:
A semiconductor memory, comprising: a parity cell array to which parity data are written; a plurality of first regular cell arrays disposed on one side of said parity cell array and to which a plurality of bits of write data are written; a plurality of second regular cell arrays disposed on the other side of said parity cell array and to which a plurality of bits of write data are written; a plurality of first external data terminals disposed on said one side so as to input and output data to and from said first regular cell arrays; a plurality of second external data terminals disposed on said other side so as to input and output data to and from said second regular cell arrays; an address terminal which receives an address to select a memory cell from which and to which data are read and written; a plurality of sub parity generation circuits disposed corresponding to said first and second regular cell arrays and generating sub parity data according to read data which are read simultaneously from said first and second regular cell arrays; a main parity generation circuit disposed corresponding to said parity cell array and generating said parity data according to said sub parity data, the parity data being common to said first and second regular cell arrays; a syndrome generation circuit which generates a syndrome according to parity data read from said parity cell array and to parity data generated by said main parity generation circuit; and a read error correction circuit which corrects, according to said syndrome, read data read from said first and second regular cell arrays, wherein: a bit width of data in said first and second regular cell arrays is equal to a bit width of said first and second external data terminals; data supplied to said first external data terminals are written to any one of said first regular cell arrays in accordance with said address; and data supplied to said second external data terminals are written to any one of said second regular cell arrays in accordance with said address.