Patent ID: 7516444

Claim:
An integrated circuit (IC) card comprising: a memory device having stored therein a plurality of executable instructions; an input/output (I/O) interface; a smart card development interface (SCDI), coupled to the I/O interface, to receive and identify one or more debug frames interlaced within a normal communication flow between the IC card and a host system; and a controller, coupled to the memory device and the SCDI, to execute at least a subset of the plurality of executable instructions to selectively implement at least one IC card application and a debug application which selectively controls the IC card application executing on the IC card, wherein the SCDI is configured to route the received debug frames to the debug application executing on the IC card, while promoting the application frames to the IC card application executing on the IC card, subject to conditions imposed by the debug frames, wherein the SCDI is configured to implement one or more debug features on the IC card according to debug instructions embedded within the received debug frames, wherein the debug features include one or more of read/write IC card memory, get/set breakpoints in a IC card application, sequentially step an IC card application, run an IC card application, or release a IC card application frame, wherein the SCDI is configured to generate one or more response debug frames in response to one or more received debug frames, interlace the one or more response debug frames with response application frames, and send the one or more response debug frames and response application frames to the host system.