Patent ID: 8742961

Claim:
A pipeline analog-to-digital converter comprising: a plurality of calibrated stages, each of the plurality of calibrated stages comprising: an amplifier generating an output representing an amplified difference between a first voltage at an input of the amplifier and a second voltage at another input of the amplifier; and a sampling capacitor comprising a plurality of sub-capacitors, each of the plurality of sub-capacitors having a first terminal coupled to the input of the amplifier and a second terminal selectively coupled to a first reference voltage or a second reference voltage higher than the first reference voltage in a calibration mode or an input voltage of each of the plurality of stages in an operational mode subsequent to the calibration mode; and a correction circuit coupled to the plurality of calibrated stages and configured, for each of the plurality of calibrated stages, to: receive a plurality of measurements of the output of the amplifier performed in calibration mode, during each of the plurality of measurements, the second terminal of at least one of the plurality of sub-capacitors coupled to the first reference voltage; determine a calibration coefficient for the calibrated stage based on the received plurality of measurements; and compensate, in operation mode, for a gain error of the calibrated stage based on the determined calibration coefficient.