Patent ID: 6977607

Claim:
An analog-to-digital converter with reduced parasitic capacitance on the input during a sampling operation, comprising: a charge-redistribution, binary-weighted switched-capacitor array having a plurality of array capacitors that each have a commonly connected plate interfaced to a first common node and a switched plate, said switched plate operable to be switched between first and second reference voltages during a redistribution phase and selected ones of said capacitors additionally operable to be switched to the input during a sampling phase; each of said array capacitors having a parasitic capacitance associated therewith; a compensation capacitor having a common plate connected to said first common node and a switched plate operable to be switched to the input during the sampling phase and to said first reference voltage during the redistribution phase, the parasitic capacitance thereof less than the parasitic capacitance of the combination of all of said non-selected ones of said array capacitors; a comparator for comparing the voltage on said first common node to a compare reference voltage during the redistribution phase; and a successive approximation controller for switching the switched plate of said array capacitors between said first and second reference voltages in accordance with a successive approximation algorithm during the redistribution phase.