Patent ID: 6900701

Claim:
A method of generating a clock signal for an electronic device, comprising: monitoring an output of a first oscillator to detect the presence of a first oscillator signal, the first oscillator signal being generated by the first oscillator when the electronic device has a first configuration; if the first oscillator signal is present, selecting the first oscillator signal as the source of the clock signal; and if the first oscillator signal is determined not to be present, selecting a second oscillator signal as the source of the clock signal, the second oscillator signal being generated by a second oscillator when the electronic device has a second configuration, wherein monitoring comprises: counting cycles of the first oscillator signal; and determining whether a predetermined count of cycles has been reached by a predetermined time, wherein the predetermined time is established by counting cycles of a separate clock signal, and wherein the separate clock signal comprises a phase-lock-loop (PLL) clock signal of a phase lock loop (PLL).