Patent ID: 7161521

Claim:
An analog to digital converter (ADC) generating a digital code from an analog sample, said ADC comprising: a first stage generating a first sub-code using a first reference signal, wherein said first sub-code comprises m-bits, wherein said first stage comprises: a sub-ADC generating said first sub-code from said analog sample, said first sub-code being generated according to said first reference voltage (Vref); a digital to analog converter (DAC) converting said first sub-code to an intermediate voltage (Vint), wherein Vint equals ((Vref/2 m )*V 1 ), wherein * represents a multiplication operation and V 1 equals said first sub-code; a subtractor generating a residue signal having a voltage level Vres equaling (Voltage level of said analog sample—Vint); and a gain amplifier amplifying said residue signal by a factor F, wherein F equals (2 m /2 k ); and a second stage generating a second sub-code using a second reference signal, wherein a voltage level of said first reference signal is not equal to the voltage level of said second reference signal, wherein the voltage level of said second reference signal is less than the voltage level of said first reference signal, wherein the voltage level of said second reference signal equals (the voltage level of said first reference signal/2 k ) wherein k is an integer, wherein said first sub-code and said second sub-code are used in generating said digital code.