Patent ID: 7533251

Claim:
A semiconductor integrated circuit, comprising: a CPU which operates such that when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction, when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction; a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein when the fourth signal is asserted, the memory content of the stack memory is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first and second signals are negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address.