Patent ID: 8169243

Claim:
A device comprising: a delay lock loop (DLL) circuit to extend at least one of an active high and an active low time of a control voltage derived from a duty cycle of an input clock signal; and a clock generator circuit, responsive to the control voltage, to generate a first set of clock signals and a second set of clock signals separated from the first set of clock signals by a non-overlapping time (t nlp ), where the DLL circuit includes a duty cycle control (DCC) circuit having a number (n_dll) of voltage-controlled delay cells, and where the clock generator circuit includes a first number (n_td) of voltage-controlled delay cells to delay a first clock signal (C 1 ) of the first set of clock signals by a first predetermined amount of time (t d ) from a delayed clock signal (C 1 d ) and a second number (n_nlp) of voltage-controlled delay cells to delay a second clock signal (C 2 ) of the second set of clock signals by the t nlp from the C 1 d , and device wherein a ratio between the n_dll and n_td is defined as n_dll n_td = Ts t d · ( duty out - duty in ) where duty in is the duty cycle of the input clock signal Ck_in to the DCC circuit; duty out is an output clock duty cycle of the DCC circuit; and Ts is a duration of time from a rising edge of a C 1 clock to the next rising edge of the same C 1 clock.