Patent ID: 7558133

Claim:
A memory system, comprising: a memory controller having a first group of terminals, a second group of terminals, and a data strobe terminal, the memory controller being operable to output memory command signals and address signals from the terminals in the first group, write data signals from the terminals in the second group, and a write data strobe from the data strobe terminal having transitions that are synchronized to the write data signals, the memory controller being operable to generate at least one transition of the write data strobe immediately prior to generating the transitions that are synchronized to the write data signals, the memory controller further being operable to receive and process read data signals received from the terminals in the second group in synchronism with transitions of a read data strobe received from the data strobe terminal; a memory device having a first group of terminals, a second group of terminals, and a data strobe terminal, the memory device being operable to process memory command signals and address signals received from the terminals in the first group, to store write data corresponding to write data signals received from the terminals in the second group, and to process a write data strobe received from the data strobe terminal, the memory device being operable to output the read data signals from the terminals in the second group in synchronism with the read data strobe received from the data strobe terminal, the memory device further comprising: a decoder coupled to the terminals in the first group to receive the memory command signals, the decoder being operable to decode the command signals and to determine if the command signals correspond to a write command, the decoder being operable to generate a data start signal after a delay period from receiving the memory command signals corresponding to a write command; a data latch circuit having data input terminals coupled to the terminals in the second group to receive the write data signals and a clock input terminal coupled to the data strobe terminal of the memory device to receive the write data strobe signal, the data latch circuit being operable to capture the received write data signals responsive to respective transitions of the write data strobe signal; a control circuit coupled to the data latch circuit to receive the write data signals captured by the data latch circuit, the control circuit outputting the write data signals captured by the data latch circuit responsive to receiving the data start signal; and a bus system coupling the first group of terminals of the memory controller to the first group of terminals of the memory device, the bus system further coupling the second group of terminals of the memory controller to the second group of terminals of the memory device.