Patent ID: 8479076

Claim:
An apparatus, comprising: at least one processor to: scramble a plurality of header bits to generate a scrambled plurality of header bits; pad a predetermined number of zero-valued bits to the scrambled plurality of header bits to generate a padded bit block; employ a rate 3/4 low density parity check (LDPC) code to encode the padded bit block to generate a plurality of LDPC parity bits; generate a first sequence based on the scrambled plurality of header bits and a first subset of the plurality of LDPC parity bits; generate a second sequence by XOR processing a third sequence, being a concatenation of the scrambled plurality of header bits followed by a second subset of the plurality of LDPC parity bits, with a first pad sequence; generate a fourth sequence by XOR processing a fifth sequence, being a concatenation of the scrambled plurality of header bits followed by a third subset of the plurality of LDPC parity bits, with a second pad sequence; concatenate the first sequence followed by the second sequence followed by the third sequence to form a sixth sequence; map the sixth sequence as quadrature phase shift keying (QPSK) and insert a plurality of pilot symbols to generate a seventh sequence; and modulate the seventh sequence as an orthogonal frequency division multiplexing (OFDM) symbol; and a transmit driver to transmit a physical layer (PHY) frame, that includes the OFDM symbol and data, to at least one additional apparatus in accordance with OFDM signaling.