Patent ID: 7285435

Claim:
A method for manufacturing an active matrix organic electroluminescence display device, the method comprising: depositing an amorphous silicon on a substrate; crystallizing the amorphous silicon to a polysilicon by an SLS method; forming first and second semiconductor layers in portions where switching and driving transistors will be formed by selectively removing the crystallized poly silicon; forming a gate insulating film on an entire surface of the substrate including the semiconductor layers; forming a scan line to cross the first semiconductor layer on the gate insulating layer and a gate electrode of the driving transistor to cross the second semiconductor layer; forming source and drain regions of switching and driving transistors on the first and second semiconductor layers at both sides of the scan line and the gate electrode of the driving transistor, wherein the first semiconductor layer includes a plurality of longitudinal grains that are substantially parallel with a first channel direction between the source and drain regions of the switching transistor, and wherein the second semiconductor layer includes a plurality of longitudinal grains that are substantially parallel with a second channel direction between the source and drain regions of the driving transistor; depositing an insulating interlayer on the entire surface of the substrate; forming contact holes to expose the source and drain regions of the first semiconductor layer, the gate electrode of the driving transistor and the source region of the second semiconductor layer, respectively; forming a data line connected to the source region of the first semiconductor layer substantially perpendicular to the scan line on the insulating interlayer; a power line connected to the source region of the second semiconductor layer substantially perpendicular to the scan line, the scan line overlapped with the gate electrode of the driving transistor; and an electrode pattern to connect the drain region of the first semiconductor layer to the gate electrode of the driving transistor; forming an insulating layer for planarization having a contact hole to the drain region of the second semiconductor layer; and forming an electroluminescence device connected to the drain region on the insulating layer.