Patent ID: 8617957

Claim:
A method for fabricating a bipolar transistor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate having a silicon layer thereon; patterning lithographically a fin hardmask on said silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask, wherein said step of placing exposes a collector region and an emitter region; doping said collector region and said emitter region; depositing a filler layer over said collector region and said emitter region; removing said dummy contact line to reveal a trench and said central portion of said patterned fin hardmask; forming a plurality of fin-shaped base regions in said silicon layer by removing, within said trench, a portion of said silicon layer not covered by said central portion of said patterned fin hardmask after said step of removing said dummy contact line; doping said fin-shaped base region; and forming a contact line by filling said trench with a contact line material over said fin-shaped base regions, wherein said collector and emitter regions are self-aligned with said contact line.