Patent ID: 8748965

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell transistor obtained by sequentially stacking a gate insulation film, a floating gate electrode, an interelectrode insulation film, and a control gate electrode above a semiconductor substrate; and a peripheral circuit transistor, obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode above the semiconductor substrate, the peripheral circuit transistor being disposed in a position other than a position where the memory cell transistor is formed, wherein in the memory transistor, the control gate electrode has a structure in which a first semiconductor film, a silicide phase-change suppressing layer, and a silicide film are sequentially stacked above the interelectrode insulation film, in the peripheral circuit transistor, the control gate electrode of the peripheral circuit transistor has a structure in which the first semiconductor film, the silicide phase-change suppressing layer, a second semiconductor film, and in the peripheral circuit transistor, the second semiconductor film of the peripheral circuit transistor is connected to the floating gate electrode through an opening formed in the silicide phase-change suppressing layer, the first semiconductor film, and the interelectrode insulation film, and the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×10 20 to 5×10 21 [atom/cm 3 ].