Patent ID: 8284610

Claim:
A data sensing module of a flash memory, comprising: a memory core circuit, wherein the memory core circuit comprises: a first memory cell; a second memory cell; a second transistor, having a gate receiving a first bit line signal, a source coupled to the first memory cell, and a drain coupled to a source of a first transistor; a third transistor, having a gate receiving a second bit line signal, a source coupled to the second memory cell, and a drain coupled to the source of the second transistor; and a fourth transistor, having a gate receiving a word line signal, a source coupled to a common voltage, and a drain coupled to the source of the third transistor; a first transistor, having a drain coupled to a bias, a gate receiving an inverted signal, and the source coupled to the memory core circuit for receiving data stored in the memory core circuit; a detector, coupled to the drain of the first transistor for detecting a voltage of the drain, wherein a control signal is directly enabled by the detector when the voltage of the drain is lower than a threshold voltage and the control signal is directly disabled by the detector when the voltage of the drain reaches the threshold voltage; and a charge circuit, coupled to the detector and the source of the first transistor, wherein the charge circuit charges the source of the first transistor when the control signal is enabled, and stops charging the source of the first transistor when the control signal is disabled and the voltage of the drain reaches the threshold voltage, the source of the first transistor being charged to a settling voltage that is higher than the threshold voltage.