Patent ID: 7427542

Claim:
A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate in which a p-type well and an n-type well are formed; removing the gate oxide layer on the p-type well; forming bases made of polysilicon on the p-type well; forming a first photosensitive layer pattern that exposes the bases on the substrate; implanting p-type impurity ions into the bases through the first photosensitive layer pattern; removing the first photosensitive layer pattern; forming a second photosensitive layer pattern that exposes the p-type well and the n-type well on the bases and the substrate; and implanting n-type impurity ions into the p-type well and the n-type well through the second photosensitive layer pattern to form an emitter and a collector of the BJT.