Patent ID: 8615064

Claim:
A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying a frequency of a reference signal by a ratio represented by a sum of a first fraction and a second fraction, the circuit comprising: a controlled oscillator including a number of annularly connected amplifiers determined by dividing a least common multiple value by an integer value, a number of multiphase signals being equal to the least common multiple, and the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal, wherein the least common multiple value is a least common multiple of a denominator of the first fraction, a denominator of the second fraction, and the integer value; a converter which converts a frequency difference and a phase difference between the output signal and the reference signal to a first digital signal; a digital phase frequency detector which subtracts the first digital signal from a second digital signal representing the ratio and obtains a third digital signal representing a frequency difference and a phase difference between the output signal and the target signal; a digital filter which performs filter processing of smoothing the third digital signal to generate the digital control signal; a signal selector which sequentially selects, from the multiphase signals at every period of the reference signal in accordance with the first digital signal, a signal in phase with the reference signal in a next period as a selected signal; an analog phase detector which obtains an analog phase difference signal representing a phase difference between the selected signal and the reference signal; an analog filter which performs filter processing of smoothing the analog phase difference signal to generate the analog control signal; and a lock detector which switches signal paths for the analog control signal so that the analog control signal is provided to the controlled oscillator when the lock detector detects in accordance with the third digital signal that the output signal and the target signal are coincident in frequency and phase.