Patent ID: 8738889

Claim:
A method comprising: setting, by a control program running on a processor, a first portion of a first of a plurality of virtual partition identifiers; generating, by the processor, a second portion of the first of the plurality of virtual partition identifiers based on a first address; generating, by the processor, a second portion of a second of the plurality of virtual partition identifiers based on a second address, the first and the second of the plurality of virtual partition identifiers associated with a first of a plurality of virtual machines; storing, in a page table pointer storage location, the first address; receiving an instruction requiring translation from an untranslated address to a translated memory address; initiating, in response to receiving the instruction, a page walk from a first page table pointed to by the contents of the page table pointer storage location, the page walk through a plurality of translation stages starting with a first translation stage, each translation stage having translation logic to find an entry in a corresponding data structure based on a corresponding portion of the untranslated address, each entry to store one of a transition address of a second page table for the first translation stage, an address of a third page table for a successive translation stage, and the translated memory address; finding, during the page walk, the transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on the first of the plurality of virtual partition identifiers, each of the plurality of address source identifiers to identify a unique micro-context in a plurality of micro-contexts, each of the plurality of address source identifiers based on one of the plurality of virtual partition identifiers; and re-initiating the page walk.