Patent ID: 7566963

Claim:
A stacked assembly of semiconductor packages comprising: a first semiconductor package including a first encapsulant, at least a first chip inside the first encapsulant, and a plurality of first external leads of a leadframe, wherein the first external leads are exposed and extended from a plurality of sides of the first encapsulant; at least a second semiconductor package mounted onto the first semiconductor package, the second semiconductor package including a second encapsulant, at least a second chip inside the second encapsulant, and a plurality of second external leads of a leadframe, wherein the second external leads are exposed and extended from a plurality of sides of the second encapsulant; wherein each second external lead has a U-shaped cut end locking to a soldered section of the corresponding first external lead; and soldering materials electrically connecting and mechanically bonding the lead-cut ends of the second external leads to the soldered sections of the first external leads.