Patent ID: 7392493

Claim:
A computer system comprising: one or more processors which process program instructions; a memory device connected to said one or more processors; and program instructions residing in said memory device for determining buffer insertion locations in a net of an integrated circuit design by defining at least one signal slew constraint for the net, establishing a plurality of candidate locations for inserting one or more buffers into the net, and selecting buffer insertion locations from among the candidate locations by pruning any candidate location whose buffer output slew is greater than the signal slew constraint, the buffer output slew SL(v) of a given candidate location having a buffer b inserted at a node v being computed as SL ( v )= RS ( b )· C ( v )+ KS ( b ) wherein C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b.