Patent ID: 7005361

Claim:
A method for constructing a thin film resistor for an integrated circuit, comprising: forming a stencil structure on a substrate surface, the stencil structure comprising one or more layers and defining a channel separating first and second opposing portions of the stencil structure; depositing a thin film resistor material, some of the thin film resistor material being deposited on the substrate surface within the channel to define the thin film resistor, some of the thin film resistor material being deposited outside the channel on the first and second opposing portions of the stencil structure, the thin film resistor having an initial width determined by a width of the channel; depositing a planarizing material within the channel so as to substantially surround the thin film resistor within the channel and protect against reduction of the initial width of the thin film resistor during subsequent process steps for removing the stencil structure from the substrate surface; removing at least some of the planarizing material sufficient to expose the thin film resistor material deposited outside the channel on the first and second opposing portions of the stencil structure, the thin film resistor within the channel remaining covered by the planarizing material; removing the thin film resistor material deposited outside the channel on the first and second opposing portions of the stencil structure; removing the first and second opposing portions of the stencil structure; and removing the remaining planarizing material deposited on the thin film resistor within the channel; wherein forming the stencil structure on the substrate surface further comprises: depositing a first stencil structure layer on the substrate surface; and depositing a second stencil structure layer on the first stencil structure layer, the second stencil structure layer comprising a different material than the first stencil structure layer, the second stencil structure layer extending further into the channel than the first stencil structure layer due to preferential etching of the first stencil structure layer relative to the second stencil structure layer, the width of the channel between opposing second stencil structure layers determining the initial width of the thin film resistor.