Patent ID: 7685553

Claim:
A method for determining a circuit layout, the method comprising: defining, by a processor, a grid of tiles on a circuit layout area, each tile of the grid having a respective associated critical area estimate metric; performing, by the processor, a global circuit routing for a circuit to be placed within a plurality of tiles of the grid; estimating, by the processor, for at least one tile of the grid, prior to determining a detailed circuit routing for the circuit, a respective critical area estimate metric that is based upon at least one linear measurement of conductive traces within each of the at least one tile; adjusting, by the processor, the global circuit routing, after estimating the critical area estimate metrics and prior to determining the detailed circuit routing for the circuit, to improve a selected respective critical area estimate metric assigned to at least one tile of the grid to create an adjusted global circuit routing; and producing, by the processor, an adjusted global circuit routing.