Patent ID: 7429767

Claim:
A non-volatile memory cell, comprising: a first and second source/drain regions formed in a substrate coupled by a channel region; a band-engineered tunnel insulator layer containing two or more sub-layers formed over the channel region; a composite trapping layer formed over the tunnel insulator layer, wherein the composite trapping layer contains a plurality of band engineered sub-layers providing a plurality of charge trapping layers and where the band-engineered tunnel layer is adapted to allow low voltage Fowler-Nordheim or direct tunneling injection of electrons from the channel region to the composite charge trapping layer; a band-engineered charge blocking insulator layer containing two or more sub-layers formed over the trapping layer; and a control gate formed over the crested barrier charge blocking layer, wherein the band-engineered charge blocking layer is adapted to allow low voltage Fowler-Nordheim or direct tunneling injection of holes from the control gate to the composite trapping layer.