Patent ID: 7598525

Claim:
A thin film transistor array substrate with multiple chamfers, a plurality of thin film transistor arrays are configured on a mother substrate, each of the thin film transistor arrays comprises: signal lines and scan lines, configured to be at the longitudinal and transverse directions on an insulated substrate; display elements formed in the position adjacent to the intersection points of said signal lines and said scan lines; and a plurality of outer lead bonding pads (Hereinafter, referred to as “OLB Pads”) and the wiring for connecting are formed at the peripheral of said insulated substrate in order to connect to the outside after cutting off from said mother substrate, wherein: outside said OLB pad, branch wiring (Hereinafter, referred to as “branch wiring for scale and OLB protection”) is provided based on the predetermined interval at two sides of the wiring (Hereinafter, referred to as “terminal face wiring”) which intersects with the line (Hereinafter, referred to as “cut off line”) used for representing the position where said thin film transistor array is cut off from said thin film transistor array substrate, thereby said thin film transistor array substrate with multiple chamfers is cut off.