Patent ID: 7038515

Claim:
A circuit comprising: a memory unit including a plurality of storage nodes; a transfer unit including a plurality of pass elements, each of the pass elements being located in a path coupled between a data input node and one of the plurality of storage nodes; an inversion unit coupled between the data input node and at least one of the plurality of pass elements; and an output unit coupled between the memory unit and a latch output node, wherein the memory unit further includes: a first inverter having an input node coupled to a first storage node of the plurality of storage nodes and an output coupled to a second storage node of the plurality of storage nodes; a second inverter having an input node coupled to the second storage node and an output coupled to the first storage node; a third inverter having an input node coupled to a third storage node of the plurality of storage nodes and an output coupled to a fourth storage node of the plurality of storage nodes; and a fourth inverter having an input node coupled to the fourth storage node and an output node coupled to the third storage node, wherein the output unit includes a first pair of transistors having gates coupled to the second and fourth storage nodes and a drain of a transistor of the first pair of transistors coupled to the latch output node, and a second pair of transistors having gates coupled to the second and fourth storage nodes and a drain of a transistor of the second pair of transistors coupled to the latch output node.