Patent ID: 8386735

Claim:
A system comprising: a first integrated circuit comprising a direct memory access (DMA) circuit, a first random access memory (RAM) configured to be accessed by the DMA circuit, wherein the DMA circuit is configured to access the first RAM using DMA, a data/command terminal in communication with the DMA circuit, wherein the data/command terminal is configured to receive a selection signal at the first RAM, and an M-bit data terminal in communication with the DMA circuit, wherein the M-bit data terminal is configured to receive, at the first RAM, i) a write command during a first period in response to a first clock signal when the selection signal has a first state, ii) a write address during a second period in response to the first clock signal when the selection signal has a second state that is different than the first state, and iii) write data during T third periods in response to the first clock signal when the selection signal has the second state, wherein the write command, the write address, and the write data are received on a plurality of the same bit lines of the M-bit data terminal, wherein M is an integer greater than one, and T is an integer greater than zero, and wherein the first period, the second period, and the T third periods are non-overlapping.