Patent ID: 7598540

Claim:
A method for forming a semiconductor device comprising: forming at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET) that are spaced apart from each other by an isolation region; forming a compressively stressed dielectric layer over both the n-FET and the p-FET; selectively removing a portion of the compressively stressed dielectric layer from the n-FET, wherein a remaining portion of the compressively stressed dielectric layer overlays the p-FET; forming a tensilely stressed dielectric layer over both the n-FET and the p-FET; selectively removing a portion of the tensilely stressed dielectric layer from the p-FET, wherein a remaining portion of the tensilely stressed dielectric layer overlays the n-FET, and wherein a gap is located atop the isolation region and between the remaining portion of the tensilely stressed dielectric layer and the remaining portion of the compressively stressed dielectric layer; filling the gap with a dielectric filler material, said dielectric filler material is located above the isolation region and is confined within the gap; and forming an interconnect structure including an interlayer dielectric material having conductive features embedded therein.