Patent ID: 7844807

Claim:
A processor, comprising: at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including a branch target address cache (BTAC) having: at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address; and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address; wherein: the branch logic, responsive to the instruction sequencing logic using the third instruction fetch address to initiate an instruction fetch from the memory system, outputs the fourth instruction fetch address; and the instruction sequencing logic, following initiation of access to the memory system using the third instruction fetch address, thereafter initiates an instruction fetch from the memory system using the fifth instruction fetch address followed by an instruction fetch from the memory system using the fourth instruction fetch address indicated by the BTAC.