Patent ID: 7590960

Claim:
A computer-implemented method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD), the method comprising: executing a program by a computer system to perform functions including: mapping circuit elements of the circuit design to corresponding partitions of the circuit design; defining a plurality of logic boundaries on the target PLD, wherein each logic boundary is defined by a plurality of logic cells directly connected to a routing matrix that is programmable to connect the logic cells; selecting a circuit element of the circuit design; selecting a candidate location within a logic boundary on the target PLD; wherein the candidate location is one the logic cells connected the routing matrix of the logic boundary; validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary; selectively placing the selected circuit element at the candidate location according to the validation; repeating the steps of selecting a circuit element, selecting a candidate location, validating, and selectively placing for each unplaced circuit element, wherein a placed circuit design is generated once all circuit elements have been placed; and outputting the placed circuit design.