Patent ID: 7268719

Claim:
An analogue-to-digital (A/D) conversion device comprising: a pulse delay circuit comprising a plurality of delay units connected in series, each delay unit configured to input an analogue input signal and to delay the analogue input signal by a delay time corresponding to a voltage level of the analogue input signal, and each delay unit comprising inverting circuits of m×n (m, n are positive integers) stage; a clock generator configured to generate m-sampling clocks of a different phase by Td/m with one another, where Td is a delay time of each delay unit and m is a positive integer of not less than two, and the clock generator comprising m-delay lines comprising inverting circuits of i×n stages (i=1, 2, . . . , and m) configured to output the m-sampling clocks; m-pulse position numerizing means each configured to detect a position of a pulse signal output from the pulse delay circuit at a timing of one of a rising edge and a falling edge of a corresponding one of the m-sampling clocks generated by the clock generator, and the m-pulse position numerizing means configured to numerically express the detected position of the pulse signal and to output numerical data expressing the detected position of the pulse signal; an adder configured to add the numerical data output from the m-pulse position numerizing means and to output the added data as numerical data expressing the analogue input signal, wherein each of the m-pulse position numerizing means comprises at least a hold circuit configured to hold an output from a corresponding one of the plurality of delay units forming the pulse delay circuit, in synchronization with the corresponding one of the m-sampling clocks, and the parameter “n” determining a number of the inverting circuits in each of the plurality of delay units is an odd number, and the hold circuit forming each of the m-pulse position numerizing means is composed of both an inverter operating at the rising edge of the corresponding sampling clock and an inverter operating at the falling edge of the corresponding sampling clock.