Patent ID: 7746969

Claim:
A receiver system for receiving signals, the receiver system comprising: a) a timing circuit for frequency locking to the received signals; b) a digital clock and data recovery (DCDR) circuit receiving a data stream within the received signals and coupled to the timing circuit to receive timing signals, the DCDR circuit comprising: i) an analog equalizer; ii) a dc-offset and base-line wander block, coupled to the analog equalizer; iii) an analog to digital converter, coupled to the dc-offset and base-line wander block; iv) a phase block coupled to the timing circuit, the phase block outputting sampling clock signals for receiving data to the analog to digital converter, the phase block picking the correct phase at which to sample the signal input to the analog to digital converter once the timing circuit has been frequency locked to the received signals; v) a control block, coupled to the analog to digital converter and to the timing circuit, the control block digitally controlling each of the analog to digital converter, the dc-offset and base-line wander block and the analog equalizer and the phase block, the control block comprising: A) an analog equalizer loop; and B) an adder having a first and second input and an output, being coupled to the analog to digital converter and the output providing an error signal coupled to the analog equalizer loop; and vi) a slicer, coupled to the control block and providing an a decision output signal from the DCDR and also coupled to the second input of the adder and to the analog equalizer loop; wherein the analog equalizer loop uses the error signal output from the adder and the decision output signal from the slicer to generate a control signal to adjust the analog equalizer.