Patent ID: 8390328

Claim:
Clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit, said integrated circuit comprising said plurality of synchronous elements and combination circuitry, said clock gating circuitry unit being configured to receive an input clock signal and to output an output signal comprising either said clock signal or said predetermined gated value, said clock gating circuitry unit comprising: a clock input for receiving said input clock signal; a clock enable signal input for receiving a clock enable signal having either an enable value indicating said plurality of synchronous elements are currently functional and are to be clocked, or a disable value indicating said plurality of synchronous elements are currently not required and are not to be clocked; a power mode signal input for receiving a low power mode signal having either a low power value indicating entry to a low power mode in which at least a portion of said plurality of synchronous elements are powered to retain data and are not clocked and at least one of: a further portion of said plurality of synchronous elements and at least a portion of said combinational circuitry are powered down, or a functional mode value indicating said plurality of synchronous elements and said combinational circuitry are to be powered; logic circuitry configured in response to said clock enable signal having said enable value and to said low power mode signal having said functional mode value to output said clock signal and in response to at least one of said clock enable signal having said disable value and said low power mode signal having said low power value to output said predetermined gated value.