Patent ID: 7638402

Claim:
A method for implementing a sidewall spacer pullback scheme in forming a transistor, comprising: forming a first layer of oxide based material over exposed portions of a semiconductor substrate and over a gate stack formed over the semiconductor substrate; performing a first implantation of dopants to form a source extension and halo/pocket region in the semiconductor substrate adjacent to a first side of the gate stack and a drain extension and halo/pocket region in the semiconductor substrate adjacent to a second side of the gate stack; performing a first anneal; forming a first layer of nitride based material over the first layer of oxide based material; forming a second layer of oxide based material over the first layer of nitride based material; patterning the second layer of oxide based material to form a first sidewall spacer on the first side of the gate stack and a second sidewall spacer on the second side of the gate stack; removing at least some of the first layer of nitride based material when patterning the second layer of oxide based material; pulling back the first layer of nitride based material under the sidewall spacers; performing a second implantation of dopants to form a source region in the semiconductor substrate adjacent to the first sidewall spacer and a drain region in the semiconductor substrate adjacent to the second sidewall spacer; performing a second anneal; removing the sidewall spacers; pulling back the first layer of oxide based material such that a lateral extent of the pulled back first layer of oxide based material is substantially flush or undercut with a lateral extent of the pulled back first layer of nitride based material; forming silicide regions in the substrate above the source and drain regions that abut the lateral extents of the pulled back first layer of nitride based material; and forming a pre metal dielectric (PMD) liner over the silicide regions and gate stack.