Patent ID: 7119575

Claim:
A logic circuit comprising: a plurality of logic blocks, each of the plurality of logic blocks including: a first logic element (LE) including a first plurality of LE input terminals and a first LE output terminal of the first LE; a second LE including a first LE output terminal of the second LE; a first multiplexer including a first plurality of multiplexer input terminals and a first select terminal, wherein a first multiplexer input terminal of the first plurality of multiplexer input terminals is coupled to the first LE output terminal of the first LE, a second multiplexer input terminal of the first plurality of multiplexer input terminals is coupled to the first LE output terminal of the second LE, and the first select terminal is coupled to an LE input terminal of the first plurality of LE input terminals; a third logic element (LE) including a third plurality of LE input terminals and a first LE output terminal of the third LE; a fourth LE including a first LE output terminal of the fourth LE; and a second multiplexer including a second plurality of multiplexer input terminals and a second select terminal, wherein a first multiplexer input terminal of the second plurality of multiplexer input terminals is coupled to the first LE output terminal of the third LE, a second multiplexer input terminal of the second plurality of multiplexer input terminals is coupled to the first LE output terminal of the fourth LE, and the second select terminal is coupled to an LE input terminal of the third plurality of LE input terminals.