Patent ID: 8878709

Claim:
A semiconductor integrated circuit comprising: line buffers respectively configured to convert serial data into alpha and beta channel parallel digital signals; an alpha channel first selector configured to selectively switch one of the alpha and beta channel digital signals and output the selected signal; an alpha channel digital-to-analog converter configured to convert the digital signal fed from the alpha channel first selector into an analog signal; a beta channel digital-to-analog converter configured to convert the beta channel digital signal into an analog signal; a redundant digital-to-analog converter configured to convert the alpha channel digital signal into an analog signal; an alpha channel second selector configured to selectively switch one of two analog signals, one from the redundant digital to analog converter and another from the alpha channel digital-to-analog converter and output the selected signal; a beta channel second selector configured to selectively switch one of two analog signals, one from the alpha channel digital-to-analog converter and another from the beta channel digital-to-analog converter and output the selected signal; an alpha channel amplifier configured to amplify the analog signal fed from the alpha channel second selector; and a beta channel amplifier configured to amplify the analog signal fed from the beta channel second selector, wherein the alpha channel includes first to nth channels with the first channel being higher in order and the nth channel being lower in order where n is an integer equal to or greater than 2, the line buffers are respectively configured to generate digital signals of corresponding ones of the first to nth channels, each of the first to nth channels includes a first selector, digital-to-analog converter, second selector and amplifier, assuming that the redundant digital-to-analog converter is the highest-order zeroth digital-to-analog converter, the digital-to-analog converters in the first to nth channels are respectively the first to nth digital-to-analog converters with the first digital-to-analog converter being higher in order and the nth digital-to-analog converter being lower in order, and the digital-to-analog converter in the beta channel is the lowest-order digital-to-analog converter, the first selector in each of the first to nth channels selectively switches one of two digital signals, one of the own channel and another of the channel lower in order than the own channel, and outputs the selected signal to the digital-to-analog converter in the own channel, and the second selector in each of the first to nth channels selectively switches one of two analog signals, one from the digital-to-analog converter in the own channel and another from the higher-order digital-to-analog converter, and outputs the selected signal to the amplifier in the own channel.