Patent ID: 7376014

Claim:
A non-Volatile NAND Memory cell that is programmed and erased by FN Tunneling comprising: a. a drain diffusion; b. a drain select device adjacent the drain diffusion; c. a first memory element; d. a first connect diffusion acting as a source of the drain select device and a drain for the first memory element; e. a source diffusion; f. a source select device adjacent the source diffusion; g. a last memory element; h. a last connect diffusion acting as a drain of the source select device and a source for the last memory element; and i. a number of memory elements in series with the first and the last memory elements, separated from and interconnected to its neighbor by connect diffusions where each memory element between the connect diffusions comprise: i. a channel region between the connect diffusions; ii. a tunnel oxide region over the channel region; iii. two high voltage oxide regions on either side of the tunnel oxide region; iv. a floating gate poly-silicon deposed over the tunnel oxide region; iv. an inter-poly dielectric layer covering the floating gate poly-silicon; and v. a poly-silicon control gate deposed over and on the sides of the floating gate, covering five sides of the floating gate, but separated from it by the inter-poly dielectric layer; such that covering of the floating gate on five sides by the control gate provide high coupling between the control gate and floating gate of the same memory element while reducing the impact of coupling to the floating gate from neighboring memory elements.