Patent ID: 8618542

Claim:
An integrated circuit comprising: A. logic circuitry; B. parallel scan paths coupled to the logic circuitry, each scan path having a scan input and a scan output; C. response data circuitry having a serial input, control inputs, a serial output, and parallel inputs coupled with the scan outputs of the parallel scan paths, the response data circuitry including shift elements connected in series between the serial input and the serial output, each shift element including a multiplexer having a serial data input, an input from a parallel scan path, and an output, and a flip-flop having an input connected to the output of the multiplexer and an output; and D. header return circuitry having a header serial output connected with the serial input of the response data circuitry, control inputs, a command input and a frame marker input, the header data circuitry including two shift elements connected in series with the header serial output, the first shift element including a first multiplexer having an input connected to the frame maker input and an output, and a first flip-flop having an input connected to the output of the multiplexer and an output, the second shift element including a second multiplexer having an input connected to the command input, a serial data input connected to the output of the first flip-flop, and an output, and a second flip-flop having an input connected to the output of the second multiplexer and an output connected to the header serial output.