Patent ID: 8563369

Claim:
A method for fabricating an integrated circuit having at least one p-FinFET device and at least one n-FinFET device, the method comprising: forming a substrate comprising a first layer and a second layer, wherein the forming comprises bonding the first layer having a first crystalline orientation to the second layer having a second crystalline orientation that is different from the first crystalline orientation, where the first layer is situated above a top surface of the second layer; forming, in a region of a surface of the first layer, a volume of material extending through the first layer from the second layer up to the surface of first layer, wherein the material has a crystalline orientation that substantially matches the crystalline orientation of the second layer; selectively etching areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins, wherein the first and second plurality of fins are parallel to each other, and wherein the etching stops at the top surface of the second layer of the substrate; forming a spacer around each fin in the first plurality of fins and second plurality of fins, wherein a bottom portion of the spacer contacts a top surface of the second layer; recessing a set of regions of the second layer between each fin in the first plurality of fins and the second plurality of fins to form a base with exposed sidewalls under each fin in the first plurality of fins and the second plurality of fins; and oxidizing the base under each fin and a set of exposed regions between each fin, the oxidizing forming an isolation layer between and under each fin in the first plurality of fins and the second plurality of fins.