Patent ID: 8644088

Claim:
A semiconductor memory device, comprising: a memory block configured to store a data transferred through a data transfer line; a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal; a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time; and a data input block configured to load the data on the data transfer line in response to the write operation signal, wherein the data output block comprises: a data output enable pulse generator configured to generate a data output enable pulse that is activated for a predetermined time whenever the source clock pulses; a data sense amplifier configured to sense-amplify the data loaded on the data transfer line for a period that the data output enable pulse is activated, latch a sense-amplified data, and output a latched data; and an access controller configured to control the data sense amplifier to be coupled with the data transfer line in response to the write operation signal.