Patent ID: 7542363

Claim:
A semiconductor memory device comprising: a plurality of memory cells; sense amplifier circuitry for sensing data of a memory cell selected in said plurality of memory cells, said sense amplifier circuitry including (i) a boosted power supply node receiving a voltage higher than an internal power supply voltage, (ii) a read section coupled to said boosted power supply node when in operation, and reading storage data of said selected memory cell according to a current flowing through said selected memory cell, said current being supplied from said boosted power supply node to said selected memory cell, and (iii) a precharge stage coupled to an internal power supply node receiving said internal power supply voltage, supplying a current received from said internal power supply node to said selected memory cell in response to a precharge instructing signal, and precharging a data line connected to said selected memory cell to a predetermined potential; a first power supply being enabled when an externally suppliable external power supply voltage is higher than said boosted voltage, for producing said boosted voltage by down-converting the external power supply voltage to supply said boosted voltage to said boosted power supply node when made active; and a second power supply being enabled when the external power supply voltage is lower than said boosted voltage, for producing said boosted voltage by boosting said external power supply voltage and to supply said boosted voltage to said boosted power supply node when made active.