Patent ID: 7692287

Claim:
A semiconductor device characterized by comprising: a wiring board comprising a plurality of connecting terminals arranged on one surface in a direction of thickness and a plurality of external connecting bumps arranged on the other surface in the direction of thickness; and a semiconductor chip connected to said connecting terminals on said wiring board by flip chip bonding, wherein said wiring board comprises: a first wiring portion comprising a plurality of wiring layers and said external connecting bumps; and at least one second wiring portion integrated with said first wiring portion on said first wiring portion, said connecting terminals are entirely made of contact plugs formed in through holes extending through said second wiring portion in the direction of thickness, one end of each of said contact plugs is in direct contact with respective land portion of one of said wiring layers, a planar size of a surface of said second wiring portion on a side of said first wiring portion is smaller than a planar size of a surface of said first wiring portion on a side of said second wiring portion, and each connecting terminal of the second wiring portion has a smaller area than an area of each respective connecting land portion of the first wiring portion, and a thermal expansion coefficient of said second wiring portion is smaller than a thermal expansion coefficient of said first wiring portion and substantially equal to a thermal expansion coefficient of said semiconductor chip.