Patent ID: 8924629

Claim:
A method for reducing write amplification in a data storage system, the method comprising: maintaining a mapping table for a non-volatile solid-state storage array comprising a plurality of memory pages, the mapping table comprising a plurality of entries, each entry in the mapping table providing a one-to-one mapping between one of a plurality of logical addresses and one of a plurality of physical addresses corresponding to one of a plurality of partial memory pages of the plurality of memory pages; receiving a first write command from a host system, the first write command designating a first logical address of the plurality of logical addresses and first write data; when a size of the first write data is smaller than a memory page size of the plurality of memory pages, waiting for a period of time to receive a second write command from the host system, the second write command designating a second logical address of the plurality of logical addresses and second write data; when the second write command is received from the host system within the period of time and the combined size of the first write data and the second write data is smaller than or equal to the memory page size, issuing a write command to a destination memory page of the plurality of memory pages for the first and the second write commands, the destination memory page comprising a first partial memory page of the plurality of partial memory pages and a second partial memory page of the plurality of partial memory pages; updating entries of the mapping table to reflect writing of the first and second write data by: updating a first mapping entry for the first logical address with a first physical address of the plurality of physical addresses corresponding to the first partial memory page thereby invalidating data stored in a third partial memory page of the plurality of partial memory pages, and updating a second mapping entry for the second logical address with a second physical address of the plurality of physical addresses corresponding to the second partial memory page thereby invalidating data stored in a fourth partial memory page of the plurality of partial memory pages; and executing the issued write command on the storage array; wherein the method is performed under control of a controller of the data storage system, and wherein updating the entries of the mapping table is performed so that at least some memory pages of the plurality of memory pages each store partially-valid data and partially-invalid data.