Patent ID: 8144282

Claim:
A liquid crystal display device, comprising: a plurality of drain signal lines, a plurality of gate signal lines, and a plurality of reference signal lines, the drain signal lines, the gate signal lines, and the reference signal lines being formed on a surface of a substrate that faces liquid crystal; a plurality of pixel regions defined by the drain signal lines and the gate signal lines; and corresponding first and second pixel electrodes and a corresponding counter electrode in each pixel region, wherein, in each pixel region: a contact bridge line is arranged in the pixel region to cross one of the gate signal lines that defines the pixel region, the contact bridge line being connected to a reference signal line corresponding to the pixel region and the corresponding counter electrode in another pixel region that is adjacent to the pixel region, the corresponding counter electrode in the pixel region is formed between the substrate and an insulation film, and the pixel electrodes are formed between the liquid crystal and the insulation film, the first and second pixel electrodes are constituted of separate pixel electrodes to which a video signal which is supplied to the pixel region is inputted through two thin film transistors at the same timing, each of the separate first and second pixel electrodes is formed of a respective plurality of electrodes such that the electrodes of the first pixel electrode are alternately arranged with the electrodes of the second pixel electrode, the corresponding counter electrode in the pixel region is formed in a plane shape, is connected to the reference signal line corresponding to the pixel region, and overlaps the first and second pixel electrodes; the two thin film transistors have respective semiconductor layers, respective drain electrodes, and respective source electrodes, the respective source electrodes are connected to the separate first and second pixel electrodes through respective contact holes that are arranged on the reference signal line corresponding to the pixel region, the semiconductor layers are formed on one of the gate signal lines defining the pixel region and do not protrude from the gate signal line, the respective drain electrodes of the two thin film transistors are electrically connected to a same one of the drain signal lines that defines the pixel region and are each formed in a semicircular shape, respective end portions of the respective source electrodes are respectively arranged in respective inner portions of the semicircular shapes of the respective drain electrodes, and the respective drain electrode of one of the thin film transistors is physically and commonly connected with the respective drain electrode of the other thin film transistor at a position where the drain electrodes are arranged close to each other, and a width of a commonly connected portion of the respective drain electrodes is equal to a width of portions of the respective drain electrodes other than the commonly connected portion.