Patent ID: 7936329

Claim:
An active matrix type display device comprising: a display unit including: a plurality of data lines extending parallel to one another in one direction; a plurality of scan lines extending parallel to one another in a direction orthogonal to said one direction; a plurality of pixel electrodes arranged in a matrix pattern at points of intersection of said data lines and said scan lines; and a plurality of thin film transistors (TFTs) provided in a one-to-one relationship with respect to said plurality of pixel electrodes, each transistor having one of a drain and a source connected to a corresponding one of said pixel electrodes, the other one of the drain and the source connected to a corresponding one of said data lines, and a gate connected to a corresponding one of said scan lines; a scan driver for supplying a scan signal to each of said scan lines in a preset scan cycle; a column driver including: digital-to-analog converter units for converting video data to gray scale signals; a plurality of buffer amplifiers for sequentially amplifying and outputting the gray scale signals in a preset output cycle; and an output switch circuit comprising a plurality of switches for controlling connection between output terminals of said buffer amplifiers and a first end of said data lines; a delay control circuit for controlling said scan driver so that a scan selection period of the preset scan cycle is delayed by a preset delay time for a corresponding output period of the preset output cycle; an output switch control circuit for controlling said output switch circuit to be kept off during the preset delay time; and a display controller for controlling the video data, said scan driver, said column driver, said delay control circuit, and said output switch control circuit, wherein the scan selection period delayed by the delay control circuit extends beyond the corresponding output period of the preset output cycle and the scan selection period overlaps with an output period succeeding the corresponding output period of the preset output cycle.