Patent ID: 8134198

Claim:
A nonvolatile semiconductor memory, comprising: a plurality of active regions extending along a column direction formed in a semiconductor substrate; a plurality of word lines extending along a row direction; a plurality of memory cell transistors, each of the memory cell transistors including a floating gate electrode provided on the semiconductor substrate via a tunneling insulating film, an inter-gate insulating film disposed on the floating gate electrode, and a control gate electrode disposed on the inter-gate insulating film, and the plurality of memory cell transistors are disposed on intersections of the plurality of word lines and the plurality of active regions; a plurality of select gate lines extending along the row direction in parallel to the word lines; a plurality of bit line contacts disposed on the active regions; and a plurality of bit lines extending along the column direction and connected to the plurality of active regions via the bit line contacts; wherein the bit line contacts include a first conductive layer having the same material as the floating gate electrode formed in contact with the semiconductor substrate and a second conductive layer having the same material as the control gate electrode disposed on the floating gate electrode, a height of the upper surface of the first conductive layer from the surface of the active regions is substantially equal to a height of the upper surface of the floating gate electrodes from the surface of the active regions, and a bottom surface of the first conductive layer is positioned lower than a bottom surface of the floating gate electrodes.