Patent ID: 8005130

Claim:
A transceiver, comprising: a clock signal line; data signal lines; a transmitter that transmits a clock signal to the clock signal line and respectively transmits data signals to the data signal lines; and a receiver that receives the clock signal and the data signals which are transmitted through the clock signal line and the data signal lines, wherein the transmitter includes an encoder circuit that transmits a bit sequence obtained by encoding link information including byte alignment information to the clock signal line, and wherein the receiver includes a clock and data recovery circuit that extracts a clock component from the signal that is received from the clock signal line and recovers the bit sequence from the signal that is received from the clock signal line by using the extracted clock component, a decoder circuit that decodes the recovered bit sequence to reproduce the link information, a first deskew circuit that adjusts a skew among the signals received from the respective data signal lines in a time range lower than one bit on the basis of the clock component, a plurality of demultiplexers respectively converting the recovered bit sequence and outputs of the first deskew circuit into parallel data based on byte alignment information extracted from the reproduced link information, and a second deskew circuit that eliminates misalignments in the parallel data due to a bitwise skew remaining among the outputs of the first deskew circuit.