Patent ID: 8112563

Claim:
An arrangement comprising: a first semiconductor chip; and a plurality of second semiconductor chips which are connected to and drives electrical loads based on a timing defined by load control data; a first data line via which the second semiconductor chip transmits diagnostic data, which represent at least one of states prevailing in and events occurring in the second semiconductor chip, to the first semiconductor chip; a chip select line associated with each of the second semiconductor chips; and a single, second data line via which the first semiconductor chip transmits the load control data and pilot data which control the second semiconductor chips; wherein the load control data and the pilot data are transmitted in units of frames, and wherein the load control data frames and the pilot data frames are transmitted using time-division multiplexing; and wherein a first portion of data transmitted in a frame is intended for a first, second semiconductor chip, and a second portion of the data transmitted in this frame is intended for a second, second semiconductor chip as designated by data on the chip select line.