Patent ID: 7144807

Claim:
A method for forming a semiconductor structure, said method comprising: (a) forming a first semiconductor region characterized by a dopant concentration greater than 1×10 19 /cm 3 ; (b) forming a second semiconductor region overlying the first semiconductor region, said second semiconductor region comprising silicon and characterized by a dopant concentration less than 1×10 19 /cm 3 and a thickness t 1 ; (c) forming a layer comprising titanium directly overlying the second semiconductor region, said layer characterized by a line width no greater than 0.3 μm and a thickness t 2 , wherein t 1 >1.2t 2 ; t 1 /t 2 being sufficiently small that, when the layer is reacted with the second semiconductor region to form titanium disilicide, the titanium disilicide is in ohmic contact with the first semiconductor region; t 1 /t 2 being sufficiently large that, when the layer is reacted with the second semiconductor region to form titanium disilicide, the titanium disilicide anneals to a phase with a sheet resistance less than 3 ohms/square.