Patent ID: 7203876

Claim:
A method for implementing AC power dissipation control during scan operations in scannable latch designs comprising the steps of: providing a scannable latch having a functional data output and a scan data output; providing a logical NAND gate coupled to said functional data output, said logical NAND gate a first P-channel field effect transistor (PFET) connected to a voltage supply and connected in series with a first N-channel field effect transistor (NFET) defining a functional data output inverter and a second NFET coupled between said functional data output inverter and ground; and a second PFET connected between the supply voltage and said functional data output of said inverter; providing a switching control with said functional data output applied to said logical NAND gate; driving said switching control to prevent switching of said functional data output during at least part of the scan operations; and disabling said switching control to enable switching of the functional data output during functional data operations.