Patent ID: 7127015

Claim:
A digital filter suitable for receiving a digital input signal (INPUT(G)), comprising a rising edge detector (PD), a falling edge detector (ND), a delay line (T) adapted to delay said digital input signal (INPUT(G)) and to produce a delayed digital input signal (INPUT(G)+Δt), said digital input signal (INPUT(G)) comprising a voltage peak also known as glitch, wherein: the rising edge detector (PD) is adapted to produce a rising edge indicator signal (P) from the delayed digital input signal (INPUT(G)+Δt), the falling edge detector (ND) is adapted to produce a falling edge indicator signal (N) from the delayed digital input signal (INPUT(G)+Δt), first mixing means (M 1 ) adapted to produce a rising edge filter indicator signal (P′) from said digital input signal (INPUT(G)) and said rising edge indicator signal (P), second mixing means (M 2 ) adapted to produce a falling edge filter indicator signal (N′) from said digital input signal (INPUT(G)) and said falling edge indicator signal (N), and third mixing means (M 3 ) adapted to produce a digital output signal (OUTPUT) without a glitch, having a duration no greater than delay Δt, from the rising edge filter indicator signal (P′) and the falling edge filter indicator signal (N′).