Patent ID: 8211767

Claim:
A method of manufacturing a nonvolatile semiconductor memory, the method comprising: forming a first and a second gate insulating film on a semiconductor substrate, respectively; forming a floating gate electrode material on the first gate insulating film and forming at the same time a first gate electrode material on the second gate insulating film; defining first and second element areas of the semiconductor substrate by forming first and second isolation insulating layers in the semiconductor substrate, respectively; forming a first intergate insulating film having a multilayer structure on the first isolation insulating layer and the floating gate electrode material and forming at the same time a second intergate insulating film having a multilayer structure on the second isolation insulating layer and the first gate electrode material; forming a control gate electrode material on the first intergate insulating film and forming at the same time a second electrode material on the second intergate insulating film; sequentially etching the control gate electrode material, the first intergate insulating film and the floating gate electrode material to form a stacked gate electrode of a memory cell, and sequentially etching at the same time the second gate electrode material, the second intergate insulating film and the first gate electrode material to form a stacked gate electrode of a peripheral transistor; after forming the stacked gate electrodes, by oxidizing process, reducing a thickness of an insulating film serving as lowermost layer of the first intergate insulating film on the first isolation insulating layer to be thinner than a thickness of an insulating film serving as a lowermost layer of the second intergate insulating film on the second isolation insulating layer.