Patent ID: 7580275

Claim:
A circuit comprising: a memory matrix with rows and columns of cells, each cell containing a series arrangement of a resistance hysteresis element and a threshold element coupled between a row terminal and column terminal of the cell; row conductors, each coupled to the row terminals of the cells in a respective row; column conductors, each coupled to column terminals of the cells in a respective column; driver circuits coupled to the row conductors and the column conductors; a control circuit having control outputs coupled to the driver circuits, the control circuit being arranged to switch between respective discrete circuit states in response to commands, the circuit states including: a first idle state, wherein the control circuit controls the driver circuits to drive all row and column conductors to one or more idle voltages; an all-column update state, if wherein the control circuit controls the driver circuits to drive voltages at selected row conductors and all column conductors to a first and second voltage on mutually opposite sides of the one or more idle voltages respectively, and the voltages at the remaining row conductors to the one or more idle voltages; a column selective update state, wherein the control circuit controls the driver circuits to drive voltages at selected row and column conductors in mutually opposite directions from the one or more idle voltages, and the voltages at the remaining column and row conductors to the one or more idle voltages; a second idle state wherein the control circuit controls the driver circuits to drive the column conductors to the second voltage and to drive the voltages at the row conductors to the one or more idle voltages, the control circuit being arranged to switch back and forth to the column selective update state from the first idle state during execution of a column selective update command and back and forth to the all-column update state from the second idle state during execution of an all column update command, and to remain in the first and second idle state between execution of successive column selective update commands and all column update commands respectively.