Patent ID: 8154065

Claim:
A semiconductor memory device of comprising: a semiconductor substrate including a plurality of pillars separated from each other by a predetermined distance; a device isolation film between the pillars; respective surrounding gate electrodes electrically insulated from the pillars and surrounding an upper outside of each pillar; first source/drain regions formed in an upper portion of respective ones of the pillar; a second source/drain region formed in the semiconductor substrate between adjacent ones of the pillars; a buried bit line, interposed between the second source/drain region and the device isolation film, electrically contacting the second source/drain region; a word line formed in a cross-wise pattern with the bit line and electrically connected to ones of the surrounding gate electrodes; contact pads, formed on respective ones of the first source/drain regions and contacting the respective ones of the first source/drain regions; storage node electrodes formed on the contact pads; and conductive spacers between an upper outside of the surrounding gate electrodes and the word line.