Patent ID: 7388394

Claim:
A method of manufacturing a multiple layer printed circuit board configured to facilitate testing of layer-to-layer misregistration, the method comprising the steps of: forming a plurality of electrical test traces extending from near a through-hole site on a first layer, a first end of each of the plurality of electrical test traces located adjacent the through-hole site and a second end of each of the plurality of electrical test traces located away from the through-hole site, wherein at least two of the plurality of electrical test traces are electrically isolated from each other; forming an electrically conductive connecting pathway between the first layer and a second layer at the through-hole site; forming a plurality of electrical test references on the second layer corresponding to the plurality of electrical test traces; connecting the plurality of electrical test traces with the plurality of electrical test references such that each of the plurality of electrical test references is singly conductively connected to a corresponding one of the plurality of electrical test traces; testing for an electrical continuity between the electrically conductive connecting pathway and each of the plurality of electrical test references; and determining layer-to-layer misregistration of the first layer with respect to the second layer based on the electrical continuity.