Patent ID: 8488404

Claim:
A counter control signal generator, comprising: a first pulse signal generator configured to generate a first pulse signal, a pulse of the first pulse signal generated when a self-refresh period is terminated; a second pulse signal generator configured to generate a second pulse signal, a pulse of the second pulse signal generated in sync with a cyclic signal generated during a refresh period; and a signal generator configured to generate a counter control signal counting an address of a memory cell, corresponding to a memory cell on which a refresh operation is conducted, in response to the first and second pulse signals, wherein the pulse of the second pulse signal is activated upon inactivation of the cyclic signal for a delay period, wherein the second pulse signal generator comprises a second inversion delay circuit configured to inversely delay the cyclic signal for the delay period; and a second logic circuit configured to logically combine the cyclic signal and an output signal of the second inversion delay circuit to generate the second pulse signal.