Patent ID: 8392156

Claim:
A power supply noise analysis model creation method, comprising the steps of: reading data indicating the shapes of power supply conductors or grounding conductors of a multi-layer circuit board from a memory, and generating the data of a power island structure indicating the power supply conductors or grounding conductors provided on the circuit board on the basis of the data; reading data indicating the shapes of power supply conductors or grounding conductors provided on different layers of the multi-layer circuit board from the memory, and generating the data of a power supply pair indicating a shape where the power supply conductors or the grounding conductors provided on the different layers of the multi-layer circuit board face with each other on the basis of the data; reading the data of the positions of connection pads of a semiconductor device mounted on the circuit board from the memory, and determining a processing target area including the positions of the connection pads of the semiconductor device on the basis of the data, reading the data of the positions of vias included in the processing target area from the memory, and storing the data of the positions of the vias into the memory; reading the data of the positions of the vias from the memory, calculating the distances among the vias on the basis of the data, and judging, for each of the vias, the nearest via; obtaining a distance which appears most frequently, from among the distances from the vias judged to be the nearest to the vias, respectively, as a reference via pitch; obtaining each of the positions of the vias from the data stored in the memory, as a processing target via, and generating four nodes for the processing target via in a manner that the position relation between the processing target via and the four nodes corresponds to the position relation between one via and four nodes in the case where, when vias are two-dimensionally arrayed with the reference via pitch, a total of the four nodes are generated for the one via, each of the four nodes being generated at almost the middle point of each of line segments connecting the one via and adjacent four vias in directions oblique to the direction of the reference via pitch; obtaining meshes which include the nodes, respectively, by dividing the power island structure by dividing lines which pass between the generated nodes; obtaining meshes which include the nodes, respectively, by dividing the power supply pair by dividing lines which pass between the generated nodes; and converting each of the meshes obtained in each of the power island structure mesh dividing step and power supply pair mesh dividing step to a circuit element equivalent to the mesh and generating an analysis model for analyzing power supply noise caused on the circuit board.