Patent ID: 7206879

Claim:
An apparatus comprising: a first system forming a first node of a multiple-node coherent system, in which the first system includes a first plurality of interface circuits that couple to interface circuits of one or more other nodes of the multiple-node coherent system, the first system also includes a first packet direct memory access (DMA) circuit to handle packet traffic, a first memory bridge to handle coherent and noncoherent traffic separate from the packet traffic, and a first internal interconnect to which the first packet DMA circuit and the first memory bridge are coupled to transfer packet, coherent and noncoherent traffic received by the first plurality of interface circuits to a device resident within the first node, and wherein each interface circuit of the first plurality of interface circuits is separately programmable to allow one or more of receiving packet traffic destined for the first node, receiving coherent and noncoherent traffic destined for the first node and to transfer the packet traffic and coherent and noncoherent traffic to another node in the multiple-node system if the received traffic is not destined for the first node; and a second system forming a second node of the multiple-node coherent system, in which the second system includes a second plurality of interface circuits that couple to interface circuits of one or more other nodes of the multiple-node coherent system, including the first node, the second system also includes a second packet direct memory access (DMA) circuit to handle packet traffic, a second memory bridge to handle coherent and noncoherent traffic separate from the packet traffic, and a second internal interconnect to which the second packet DMA circuit and the second memory bridge are coupled to transfer packet, coherent and noncoherent traffic for transmission from a device resident within the second node to other node or nodes, and wherein each interface circuit of the second plurality of interface circuits is separately programmable to allow one or more of transmitting packet traffic and, coherent and noncoherent traffic to other node or nodes, wherein one or more of packet communication and coherent and noncoherent communication from the second system to the first system is achieved through respective pair of interface circuits of first and second plurality of interface circuits.