Patent ID: 8572538

Claim:
A device comprising: a logic block, wherein the logic block includes a plurality of logic elements; configuration logic associated with the logic block, wherein the configuration logic is operable to identify values stored in the plurality of logic elements; a first memory cell storing a mode flag value, wherein the mode flag value is operable to identify whether the configuration logic stores a user defined state or a design state, wherein the configuration logic is excluded from a data verification and correction process in response to the configuration logic storing a user defined state, and wherein the configuration logic is included in the data verification and correction process in response to the configuration logic storing a design state; and a second memory cell storing an enable read flag value, wherein the enable read flag value is operable to identify whether values stored in the configuration logic are to be read out or whether a known state is to be read out during the data verification and correction process, wherein the mode flag value or enable read flag value is implemented using at least one of triple modular redundancy, larger gate area, protective capacitors, or the use of increased voltage.