Patent ID: 7257046

Claim:
A bitline selection network, the network comprising: a plurality of bitlines, said plurality of bitlines coupled to provide access in reading and writing to a plurality of memory cells; a plurality of bitline select switches, each of said plurality of bitline select switches is coupled to one of said plurality of bitlines, said plurality of bitline select switches configured to provide at most only a single coupling to a single one of said plurality of bitlines at a time; a plurality of bitline select lines, each of said plurality of bitline select lines being coupled to one of said plurality of bitline select switches and is configured to provide independent control of each of said plurality of bitline select switches; a plurality of global bitlines, each of said global bitlines being coupled to a subset of said plurality of bitline select switches and configured to provide a common point of coupling to each of said subsets of said plurality of bitline select switches; a plurality of bit select switches, each of said bit select switches is coupled to one of said plurality of global bitlines; and a plurality of bit select lines, each of said plurality of bit select lines coupled to one of said plurality of bit select switches and electrically coupled to said plurality of memory cells in read and write operations.