Patent ID: 8510713

Claim:
A computer-implemented method for analyzing a disassembler, comprising: generating a set of processor instructions; and validating the disassembler using each processor instruction from the set of processor instructions by: obtaining an assembly representation for the processor instruction using the disassembler; monitoring an execution of the processor instruction on a processor operating in single-step mode to produce an execution result for the processor instruction; determining a correctness of the disassembler by comparing the assembly representation for the processor instruction with the execution result for the processor instruction, the comparison comprising: verifying an instruction length of the processor instruction by: receiving a program counter from the execution result after execution of the corresponding processor instruction; and comparing a number of bytes advanced by the program counter with an instruction length predicted by the disassembler; verifying a branch target of the processor instruction by: receiving a value of a branch target from the execution result after execution of the corresponding processor instruction; and comparing the received branch target value with a branch target of the assembly representation for the processor instruction; and verifying memory access associated with the processor instruction by: using anonymous or copy-on-write memory during execution of the processor instruction; and receiving a hardware exception for an illegal memory access; and generating an error if an inconsistency is found between the assembly representation and the execution result, the error including a value of the processor instruction, the assembly representation of the processor instruction as determined by the disassembler, and/or state information associated with the error.