Patent ID: 7123178

Claim:
A digital encoder comprising: a master processing means that encodes a multibit digital input signal into prescribed parallel codes; and a plurality of slave processing means, each of which has 3 or more output nodes, encodes the codes output in parallel from said master processing means into parallel codes corresponding to the configuration of said 3 or more output nodes and with the same weighting for all of the codes on the basis of a prescribed dynamic element matching algorithm, and outputs said parallel codes in parallel from 3 or more output nodes, wherein the encoding of the multibit digital input signal in said master processing means into the aforementioned parallel codes is performed corresponding to the configuration of the plurality of output nodes on the basis of a prescribed dynamic element matching algorithm; and, wherein said master processing means comprises: an input conversion means, which computes a remainder code that shows the remainder value indicating the remainder obtained when the value of said input signal is divided by N, the number of the slave processing means, and the multiple code that is commonly given to a plurality of slave processing means so as to enable representation of the multiple value of N, and which converts said input signal into said remainder code and said multiple code, and a master DEM means, which takes said remainder code output from said input conversion means as input, and which encodes said remainder code into parallel codes corresponding to the configuration of the plurality of output nodes on the basis of a prescribed dynamic element matching algorithm; and said slave processing means has a slave DEM means, which takes said multiple code output from said input conversion means and the parallel codes output from said master DEM means as input, and which performs encoding on the basis of a prescribed dynamic element matching algorithm.