Patent ID: 8463986

Claim:
A memory system comprising: a nonvolatile semiconductor memory having a plurality of channel parallel operation elements including a plurality of memory chips, in which each memory chip is divided into a plurality of planes capable of operating in parallel, each plane includes a plurality of physical blocks as a unit of data erasing, and the memory chips in the respective channel parallel operation elements operated in parallel are divided into a plurality of banks, which respectively shares a ready/busy signal, over the channel parallel operation elements; and a controller that manages a free block based on a logical block associated with physical blocks selected from the channel parallel operation elements operated in parallel and controls a parallel operation by the planes, banks, or channel parallel operation elements, wherein the controller includes: a plurality of free-block management lists in which logical blocks with a same bank number, a same chip number, and a same plane number are respectively managed as free blocks; and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from selected free-block management lists.