Patent ID: 7495975

Claim:
A memory chip comprising: a first power supply line connected to a plurality of first power supply pads; a second power supply line connected to a plurality of second power supply pads; at least one data input/output pad; a driver connected to the first power supply line, the driver outputting data to the at least one data input/output pad; an on-die termination unit connected to the second power supply line, the on-die termination unit having output characteristics matching impedance in a transmission line connected to the at least one data input/output pad; a package board including a plurality of third power supply pads which are wire-bonded to the first power supply pads and the second power supply pads; wherein the first power supply line is connected to the first power supply pads; the second power supply line is connected to the second power supply pads; the at least one data input/output pad is connected to the transmission line; the driver is connected to the first power supply line and the at least one data input/output pad, the driver outputting data to the at least one data input/output pad; and the on-die termination unit connected between the second power supply line and the data input/output pad.