Patent ID: 8385108

Claim:
A magnetic memory array comprising: a magnetic memory cell including a pair of magnetic tunnel junctions (MTJs); an access transistor coupled between a first MTJ of the pair of MTJs and a second MTJ of the pair of MTJs; a word line coupled to the access transistor; magnetic memory cells arranged in a column alternately coupled to a first and second pair of bit lines, each bit line of the pair coupled to a MTJ of the pair of MTJs; a read access transistor coupling adjacent magnetic memory cells; a read word line coupled to the read access transistor; a first and a second pair of current sources, each current sources of the pair coupled to a bit line (BL) of the first and second pair of bit lines respectively; a first and a second sense amplifier coupled to the first and second pair of bit lines respectively; the magnetic memory array operable to, select the magnetic memory cell; and set a bit line (BL) coupled to the magnetic memory cell to a voltage level, indicative of a certain state, that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the MTJs of the pair of MTJs to be in a direction opposite to that of the other MTJ of the pair of MTJs to write to the magnetic memory cell.