Patent ID: 8179719

Claim:
A memory system comprising: a state set module configured to provide a first state set having a first plurality of states, wherein each of the first plurality of states includes a first bit and a second bit, wherein a first error rate is associated with a first page including the first bit of each of the first plurality of states, and wherein a second error rate is associated with a second page including the second bit of each of the first plurality of states; and a second state set having a second plurality of states, wherein each of the second plurality of states includes a first bit and a second bit, wherein the second error rate is associated with a third page including the first bit of each of the second plurality of states, and wherein the first error rate is associated with a fourth page including the second bit of each of the second plurality of states; and a write module configured to write a third plurality of states to a plurality of multi-level memory cells on a wordline, wherein each of the third plurality of states includes a first bit and a second bit, wherein a first set of the plurality of multi-level memory cells is written using states selected from the first plurality of states, wherein a second set of the plurality of multi-level memory cells is written using states selected from the second plurality of states, and wherein a fifth page including the first bit of each of the third plurality of states has a same error rate as a sixth page including the second bit of each of the third plurality of states.