Patent ID: 7996710

Claim:
A method for managing defects in a semiconductor memory system having a plurality of addressable locations, the method comprising: allocating a first plurality of the addressable locations as in-use locations and a second plurality of the addressable locations as spare locations; determining, among the in-use locations, a number of sets of the in-use locations, wherein the sets of the in-use locations are associated with a memory defect, and wherein at least one of the sets of the in-use locations comprises a different number of the in-use locations than another one of the sets of the in-use locations; associating each of the sets of the in-use locations with at least one corresponding set of the spare locations; and directing each of a plurality of data requests that is associated with one of the sets of the in-use locations to the at least one corresponding set of the spare locations, in which determining a number of sets of the in-use locations comprises: monitoring the in-use locations for data errors; logging each of the in-use locations associated with at least one of the data errors; and processing the logged in-use locations to identify the sets of the in-use locations.