Patent ID: 8513064

Claim:
A method of forming a memory array, comprising: forming a stack comprising vertically-spaced semiconductor material plates; etching through the plates to subdivide the plates into planar pieces; forming horizontally-extending electrically conductive tiers along and in electrical connection with sidewall edges of the planar pieces; patterning the planar pieces into an array of wires; the array comprising vertical columns and horizontal rows; the electrically conductive tiers interconnecting wires of individual rows of the array; individual wires having first ends joining to the electrically conductive tiers, having second ends in opposing relation to the first ends, and having intermediate regions between the first and second ends; forming at least one gate material along the intermediate regions of the wires; forming memory cell structures at the second ends of the wires; and forming a plurality of vertically-extending electrical interconnects connected to the wires through the memory cell structures; individual vertically-extending electrical interconnects being along individual columns of the array.