Patent ID: 8554821

Claim:
An incrementor circuit for computing an output data word by increasing an input data word magnitude by one of a plurality of positive integer values, said incrementor circuit comprising: a mode increment signal circuit providing mode data designating one of the plurality of positive integer values for increasing the input data word magnitude; a first multiplexer connected to receive input data word bits and said mode data and providing a first multiplexed output data word; a single positive integer incrementor connected to receive the first multiplexed output data word and providing an intermediate sum by adding a single bit positive integer value to the first multiplexed output data word; and a second multiplexer connected to receive the intermediate sum from the single integer incrementor, the input data word bits, and the mode data and including logic circuitry connected to the input data word bits and mode data for selectively altering lower bit position data provided to the second multiplexer, the second multiplexer providing the output data word being the input data word magnitude incremented by the designated one of the plurality of positive integer values.