Patent ID: 7871846

Claim:
A method of fabricating a thin-film transistor, said transistor including a gate layer, a gate insulating layer, a semiconductor layer, a drain layer, and a passivation layer, each of which is formed on or over an insulating substrate, said transistor further including a conductive layer formed on the passivation layer, the conductive layer being connected to the gate layer or the drain layer by way of a contact hole penetrating at least the passivation layer, said method comprising: forming a first sublayer of the passivation layer over the substrate; forming a second sublayer of the passivation layer on the first sublayer, the second sublayer having an etch rate higher than that of the first sublayer; selectively etching the second sublayer and the first sublayer using a mask, thereby forming the contact hole penetrating at least the passivation layer; and forming the conductive layer to cover the contact hole, thereby contacting the conductive layer with the gate layer or drain layer by way of the contact hole, wherein the second sublayer has a thickness equal to or less than that of the conductive layer, wherein the passivation layer is formed by silicon nitride (SiN), and wherein the etch rate of the second sublayer of the passivation layer made of SiN is 1.1 times as much as that of the first sublayer, or greater in the selectively etching the second sublayer and the first sublayer.