Patent ID: 7818525

Claim:
A memory system comprising: a FLASH memory space organized into a plurality of blocks, each block comprising a plurality of pages, and each page defining an individually addressable physical memory location; and a controller operatively coupled to the FLASH memory space and configured to: access a logical-to-physical translation table that associates a logical address provided in a WRITE request with a physical address corresponding to a page within the FLASH memory space; associate a plurality of blocks together to form a first block group; associate pages within each of the blocks within the first block group together to form page stripes; accumulate, for the first block group, a Block Group READ count corresponding to the number of READ requests for a page within any of the blocks within the first block group; and after the Block Group READ Count for the first block group has reached a predetermined number, respond to the receipt of a first READ request for a first page within the first block group by moving data associated with the page stripe including the first page to a page stripe in a second block group that is different from the first block group without moving the data from the other page stripes in the first block group to the second block group in response to the receipt of the first READ request; and respond to the receipt of a second READ request for a second page within the block group by moving data associated with the page stripe including the second page to a block group different from the first block group, without moving the data from the other page stripes in the first block group in response to the receipt of the second READ request.