Patent ID: 7321162

Claim:
A semiconductor package, comprising: a leadframe comprising: a chip paddle defining opposed, generally planar top and bottom surfaces and a half-etched section which at least partially circumvents the bottom surface, the chip paddle having a paddle thickness between the top and bottom surfaces thereof; and a plurality of leads extending at least partially about the chip paddle, each of the leads having: opposed, generally planar upper and lower lead surfaces and a lead thickness between the upper and lower lead surfaces thereof; an inner lead end; and a half-etched portion formed within the lower lead surface and extending to the inner lead end, the half-etched portion defining an etched lead surface which is disposed in opposed relation to the upper lead surface; a semiconductor chip attached to the top surface of the chip paddle and electrically connected to at least one of the leads; and an encapsulation material at least partially encapsulating the leadframe and the semiconductor chip such that at least portions of the lower surfaces of the leads are exposed within the encapsulation material; wherein the lead thickness of each of the leads exceeds the paddle thickness such that the top surface of the chip paddle extends in generally co-planar relation to the etched lead surface of each of the leads.