Patent ID: 8643139

Claim:
A semiconductor device, comprising: a substrate; a first insulating layer formed over the substrate; an electrical fuse formed over the substrate, having a first interconnect formed in the first insulating layer and a via connected to one end region of the first interconnect; a first guard interconnect formed in the first insulating layer and, facing a first side of the first interconnect in a plan view; a second guard interconnect formed in the first insulating layer and, facing the one end region of the first interconnect in a plan view; and a third guard interconnect formed in the first insulating layer and, facing a second side of the first interconnect in a plan view, wherein the first side is an opposite side of the second side in a plan view, wherein the first side and the second side are formed to sandwich the one end region in the plan view, wherein the first guard interconnect, the second guard interconnect and the third guard interconnect are not connected each other, wherein only the first insulating layer is formed between the first guard interconnect and the first interconnect in the plan view, wherein only the first insulating layer is formed between the second guard interconnect and the first interconnect in the plan view, and wherein only the first insulating layer is formed between the third guard interconnect and the first interconnect in the plan view.