Patent ID: 7221576

Claim:
A dynamic RAM, comprising: a plurality of memory mats comprising a plurality of bit lines; a plurality of word lines; and a plurality of memory cells coupled to said plurality of bit lines and said plurality of word lines, said plurality of memory mats being placed along a line in a direction of said bit line, each of said plurality of memory cells comprising a MOSFET comprising a capacitor having first and second electrodes; a gate coupled to a corresponding one of said plurality of word lines; and a source and a drain connected to provide a source-drain path, one of which source and drain is coupled to a corresponding one of said plurality of bit lines and the other of which source and drain is coupled to said first electrode of said capacitor; and a sense amplifier array comprising a plurality of latch circuits being provided in areas between said memory mats placed in said bit line direction, respectively, and a pair of input/output nodes connected to a pair of bit lines placed separately in said memory mats on both sides of said area, wherein, for a general memory mat other than a pair of end memory mats respectively arranged at both end portions of said plurality of memory mats placed in said bit line direction, word lines in any one of said memory mats are activated while, for said end memory mats provided on said both end portions in said bit line direction, word lines said both memory mats are activated together, and said end memory mats include a plurality of dummy bit lines placed in said bit line direction.