Patent ID: 8004316

Claim:
A complementary logic cell, comprising: a first logic input; a second logic input; a first dedicated logic terminal; a second dedicated logic terminal; a high-voltage terminal configured for connection to a high constant voltage, wherein said high-voltage terminal is separate from said first dedicated logic terminal and from said second dedicated logic terminal; a low-voltage terminal configured for connection to a low constant voltage, wherein said low-voltage terminal is separate from said first dedicated logic terminal and from said second dedicated logic terminal; a p-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection; and an n-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection; said first dedicated logic terminal being connected to said outer diffusion connection of said p-type transistor, said second dedicated logic terminal being connected to said outer diffusion connection of said n-type transistor, said inner diffusion connection of said p-type transistor and said inner diffusion connection of said n-type transistor being connected to form a common diffusion logic terminal, said high-voltage terminal being connected to said bulk connection of said p-type transistor, and said low-voltage terminal being connected to said bulk connection of said n-type transistor.