Patent ID: 8330494

Claim:
A semiconductor device comprising: a first transistor included in a latch circuit; a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor; and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well, wherein: the latch circuit has a first node and a second node; the first node and the second node have a relationship such that a logic of data retained in the latch circuit is inverted in a case where logics at the first node and the second node are inverted concurrently; and the first transistor is coupled to the first node, and the second transistor is coupled to the second node, wherein the well contact is provided only in a central part of the well, the central part being situated between the first node and the second node.