Patent ID: 8122204

Claim:
A memory system comprising: a memory controller for outputting a command signal and an address signal and for inputting and outputting a data signal, a first memory device for inputting the command signal and the address signal from the memory controller, wherein the first memory device comprises a deep power down command control circuit for stopping the first memory device, and a first command judging circuit for inputting and outputting the data signal and for decoding the command signal, and a second memory device for inputting the command signal and the address signal from the memory controller, wherein the second memory device comprises a second command judging circuit for inputting and outputting the data signal and for decoding the command signal, wherein the command signal, the address signal and the data signal are commonly connected to the first memory device and the second memory device; and wherein a first action of the first memory device and a second action of the second memory device commonly operate simultaneously in the same data latency and in the same cycle, wherein the second memory device adds, in the case of a determined data transfer mode, a specified number to an address latency of the first memory device to obtain an address latency for the second memory device.