Patent ID: 8476633

Claim:
A thin film transistor array substrate for a display panel comprising: a base substrate; a plurality of gate lines including a gate electrode disposed on the base substrate; a plurality of storage electrode lines disposed on the base substrate; a gate insulating layer disposed on the gate electrode, the plurality of gate lines and the plurality of storage electrode lines; a semiconductor layer including a channel portion disposed on the gate insulating layer; a plurality of data lines including a source electrode, and a drain electrode opposite to the source electrode disposed on the semiconductor layer; a first passivation layer disposed on the plurality of gate lines and the plurality of data lines including a opening exposing a portion of drain electrode, wherein the first passivation layer comprises one of silicon nitride (SiNx) and silicon oxide (SiOx), and an organic insulating material having a small dielectric constant; a second passivation layer disposed on the first passivation layer, wherein the second passivation layer includes a material having a lower etch selectivity than the first passivation layer; and a third passivation layer disposed on the second passivation layer and over the gate electrode, the source electrode, and the drain electrode; and a pixel electrode disposed on the second passivation layer and connected with the drain electrode, wherein the third passivation layer includes a material having a higher etch selectivity than the first passivation layer.