Patent ID: 7385251

Claim:
A gated diode structure, comprising: a semiconductor layer of a first conductivity type; an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer; at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer, the at least one trench electrode comprising a trench extending substantially vertically through the active region and at least partially into the semiconductor layer, the trench being substantially filled with an electrically conductive material, the electrically conductive material being isolated from the active region and the semiconductor layer by an insulating layer formed on sidewalls and a bottom of the trench; a first terminal electrically connected to the trench electrode; at least a second terminal, the second terminal comprising a plurality of terminals electrically connected to the active region at different points throughout the active region; and a gate formed proximate the upper surface of the semiconductor layer, the gate extending above and substantially parallel to the upper surface of the semiconductor layer, the gate being electrically connected to the trench electrode, the insulating layer formed on sidewalls and a bottom of the trench extending laterally above an upper surface of the substrate, beyond an upper perimeter opening of the trench, so as to electrically isolate the gate from the active region, the electrically conductive material in the trench being formed substantially concurrently with the gate so that the gate is integrated with the trench electrode; wherein the gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals, the first mode being characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode, the gated diode having a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being substantially greater than the second capacitance.