Patent ID: 7664810

Claim:
An apparatus in a microprocessor, for accomplishing modular multiplication operations, comprising: translation logic, configured to receive an atomic Montgomery multiplication instruction from a source therefrom, wherein said atomic Montgomery multiplication instruction prescribes generation of a Montgomery product, and configured to translate said atomic Montgomery multiplication instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of said Montgomery product, wherein said atomic Montgomery multiplication instruction implicitly references a plurality of registers within the microprocessor, and wherein said plurality of registers comprises: a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory, wherein said first location comprises: a first operand pointer, said first operand pointer pointing to a second memory address, said second memory address specifying a second location in said memory comprising a first operand for generation of said Montgomery product; and execution logic, operatively coupled to said translation logic, configured to receive said sequence of micro instructions, and configured to perform said sub-operations to generate said Montgomery product.