Patent ID: 7956659

Claim:
A semiconductor memory device comprising: an input circuit configured to receive a system clock signal to generate a duty cycle-corrected clock signal by correcting a duty cycle ratio of the system clock signal; a delay locked loop (DLL) circuit configured to receive the duty cycle-corrected clock signal, and output first and second delay-locked clock signals, respectively produced by delay locking operations based on a rising edge and a falling edge of the duty cycle-corrected clock signal, by comparing a phase of the duty cycle-corrected clock signal with phases of first and second feedback clock signals; a replica model configured to receive the first and second delay-locked clock signals, and output the first and second feedback clock signals, respectively, by delaying the first and second delay-locked clock signals by a modeling delay value of the semiconductor memory device; and a duty cycle correction circuit configured to receive first and second delay-locked clock signals, and control the duty cycle ratio of the first and second delay-locked feedback clock signals, wherein the first and second delay-locked clock signals are received by the replica model prior to being duty cycle-corrected by the duty cycle correction circuit.