Patent ID: 7968408

Claim:
A method comprising: forming a capacitor lower metal layer over a semiconductor substrate including a plurality of layers; forming a SiN layer over the capacitor lower metal layer; reacting a surface of the SiN layer with a mixture of Ar gas and at least one of NF 3 and NH 3 gas via a remote plasma process to form a capacitor dielectric layer having a thickness of approximately 30 nm or less; forming a capacitor upper metal layer over the capacitor dielectric layer, forming a second insulating layer to cover a metal-insulator-metal capacitor region including the capacitor lower metal layer, the capacitor dielectric layer, and the capacitor upper metal layer; forming an fluorine doped silicate glass layer, a third D-TEOS insulating layer, a SiN layer, and a fourth D-TEOS insulating layer sequentially over the entire surface of the semiconductor substrate; forming a first contact layer by a conductive material and penetrating through the second and third insulating layers, to electrically connect the first bonding metal layer and the capacitor upper metal layer to each other; forming a second contact layer by a conductive material and penetrating through the second and third insulating layers and the capacitor dielectric layer, to electrically connect the second bonding metal layer and the capacitor lower metal layer to each other, wherein first and second bonding metal layers formed of conductive metals and penetrating through the fourth insulating layer and the SiN layer.