Patent ID: 7164606

Claim:
A method of programming a non-volatile memory (NVM) cell, the memory cell including a first P-IGFET programming transistor having a source region, a bulk region, a drain region and a gate electrode connected to a common storage node, a second P-IGFET read transistor having interconnected source and bulk regions, a drain region and a gate electrode connected to the common storage node, a third P-IGFET erase transistor having interconnected drain, source and bulk regions and a gate electrode connected to the common storage node, and a fourth P-IGFET control transistor having interconnected drain, source and bulk regions and a gate electrode connected to the common storage node, the NVM cell programming method comprising: grounding the source region, the drain and the gate electrode of each of the first, second, third and fourth P-IGFET transistors; applying an inhibiting voltage to the interconnected source and bulk regions of the P-IGFET read transistor, the interconnected drain, source and bulk regions of the P-IGFET erase transistor and the drain region of the P-IGFET read transistor, while grounding the source region and the drain region of the P-IGFET programming transistor and maintaining the bulk region of the P-IGFET programming transistor at either ground or the inhibiting voltage; sweeping the interconnected drain, source and bulk regions of the P-IGFET control transistor from 0V to a predefined maximum programming voltage in a preselected programming time; and at the end of the preselected programming time, ramping the interconnected drain, source and bulk regions of the P-IGFET control transistor from the predefined maximum programming voltage to 0V and returning all electrodes having the inhibiting voltage applied thereto to ground.