Patent ID: 8824201

Claim:
A semiconductor memory apparatus comprising: a read current supply unit configured to supply a read current; a resistive memory cell having a resistance value and configured to pass a current having a magnitude corresponding to the resistance value thereof in a data read mode; a voltage transfer unit coupled to the read current supply unit and the resistive memory cell and configured to transfer the read current to the resistive memory cell, wherein a voltage due to the current flowing through the resistive memory cell is formed at a sensing node; and a feedback unit configured to drive in response to the voltage formed at the sensing node, and to detect a voltage level of the sensing node and output a detection voltage, and to pull-down drive a connection node, which is coupled between the voltage transfer unit and the resistive memory cell, when the detection voltage reaches a predetermined level, wherein the feedback unit comprises: a voltage detection section configured to detect the voltage level of the sensing node and output the detection voltage, which corresponds to a detection result, to a detection voltage terminal; and a pull-down driving section configured to pull-down drive the connection node according to a voltage level of the detection voltage terminal, and wherein the voltage detection section comprises a first transistor having a gate coupled to the sensing node, a source coupled to an internal voltage terminal, and a drain coupled to the detection voltage terminal.