Patent ID: 7006148

Claim:
A scan line conversion circuit for converting the number of scan lines of an input video signal, said scan line conversion circuit comprising: a FIFO (first in first out) memory into which the video signal is input; a sequential scan conversion circuit section for converting an interlace signal sent from the FIFO memo to non-interlace signal, the sequential scan conversion circuit section including a field memory; an address generator into which a vertical enlargement ratio and a synchronous signal are input to generate an address as a spatial position after scan line conversion; a memory control unit for generating a memory control signal based on the address sent from the address generator; a coefficient generator for generating a coefficient for performing scan line conversion; a plurality of first multipliers for multiplying sequentially scan converted signals, sent from the sequential scan conversion circuit section, by respective coefficients; and an adder for adding signals output from the multipliers together, wherein the memory control unit controls memories including the FIFO memory and the field memory in the sequential scan conversion circuit section and inputs line data necessary for resolution conversion into the multipliers.