Patent ID: 8324662

Claim:
A semiconductor device, comprising: a substrate; and an electric fuse formed on the substrate, the electric fuse including: a first interconnect formed on one end side of the electric fuse; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via portion provided in contact with the first interconnect and the second interconnect to connect the first interconnect and the second interconnect; a third interconnect formed on another end side of the electric fuse, the third interconnect being formed in the same layer in which the first interconnect is formed, as being separated from the first interconnect; and a second via portion provided in contact with the third interconnect and the second interconnect to connect the third interconnect and the second interconnect, the second via portion being lower in resistance than the first via portion, wherein the electric fuse is disconnected by a flowing-out portion at the first interconnect that comprises a conductive material forming the electric fuse which flows outwardly during disconnection, wherein each of the first interconnect, the second interconnect, the third interconnect, the first via portion, and the second via portion comprises a copper-containing metal, and wherein the electric fuse is disconnected without cutting the second interconnect, wherein the second via portion has a contact area with the second interconnect, which is larger than a contact area of the first via portion with the second interconnect, wherein the second via portion comprises a single via, and wherein, in a plan view, a length of the second interconnect in a first direction is substantially a same as a length of the first interconnect in the first direction at an overlap portion between the first and second interconnects, wherein a width of the overlap portion between the first and second interconnects in a second direction perpendicular to the first direction is smaller than a width of an overlap portion between the second and third interconnects in the second direction, wherein an entire non-overlap portion of the second interconnect which is not overlapped by the first and third interconnects is in a rectangular shape, wherein each of the first and second via portions is a single via, and a width of the second via portion is greater than a width of the first via portion.