Patent ID: 8125837

Claim:
A semiconductor device comprising: an array including memory cells each having a select terminal connected with a word line and a data terminal connected with a bit line; a word-line-timing generator operable to generate a word-line timing signal or deciding a word-line activation time; a comparator operable to make a comparison between the word-line timing signal and a reference signal for detecting whether the word-line timing signal after activation transitions to a non-activated state later than a timing of a level change of the reference signal; and a back-gate-bias control which controls a back-gate bias of a transistor in each of the memory cells in response to a comparison result of the comparator, wherein the memory cells are each a static type memory cell having a pair of CMOS inverters with an input of one inverter and an output of the other connected with each other, wherein the word-line-timing generator has a replica cell equivalent to each memory cell in electrical characteristic during a read action, and changes the word-line timing signal in response to an output of the replica cell, and wherein the transistor is a p-channel MOS transistor and the back-gate-bias control circuit applies a reverse back-gate bias to the transistor when a period between a selection of a word line and a change of the word-line timing signal is shorter than the reference signal.