Patent ID: 7557627

Claim:
A semiconductor memory apparatus, comprising: a first delay locked loop configured to compare a system clock with a delayed signal of the system clock to thereby generate a first delay locked clock synchronizing a data output timing with the system clock; a second delay locked loop configured to compare the system clock with a delayed and inversed signal of the system clock to thereby generate a second delay locked clock synchronizing the data output timing with the system clock; and a clock selection block configured to select one of the first and second delay locked clocks to thereby output a reference clock for data output, wherein the first delay locked loop includes: a first delay line configured to delay the system clock; a first delay model configured to delay an output of the first delay line by a modeled delay time to generate a first feedback clock; a first phase comparator configured to compare a phase of the first feedback clock with that of the system clock; a first shift register configured to control a delay amount of the first delay line according to a comparison result of the first phase comparator; and a first locked detector configured to output a first locking signal to the clock selection block when the phase of the first feedback clock is the same as that of the system clock.