Patent ID: 7307873

Claim:
A memory circuit, comprising: a plurality of bit lines; a plurality of select lines; a plurality of bit cells, each bit cell formed using five transistors, with two of the five transistors forming a first inverter, another two of the five transistors forming a second inverter, the two inverters forming a bi-stable loop, and the fifth transistor serving as an access transistor, with the drain, the source and the gate of the access transistor coupled to inputs of the inverters, one of the bit lines, and one of the select lines respectively; and a controller coupled to the bit lines and the select lines, and adapted to clear all bit cells by activating all the select lines, driving all bit lines to a logic one, and causing a power cycle to be initiated on the bit cells, and to selectively set the bit cells by selectively activating the select lines and selectively driving the bit lines to logic zero.