Patent ID: 7990861

Claim:
A device, comprising: a processor to implement logic to: receive a data unit intended for a destination device, obtain information from the data unit, where the obtained information includes a source side acknowledgement number, a source side window size, a maximum window size, a data unit sequence number, a data unit acknowledgement number, a data unit length value, a destination side acknowledgement number, and a destination side window size, determine whether the data unit sequence number is greater than the source side acknowledgement number minus the maximum window size, determine whether a sum of the data unit sequence number and the data unit length value is less than a sum of the source side acknowledgement number and the source side window size, determine whether the data unit acknowledgement number is less than a sum of the destination side acknowledgement number and the destination side window size, and forward the data unit to the destination device when the data unit acknowledgement number is less than the sum of the destination side acknowledgement number and the destination side window size, the sum of the data unit sequence number and the data unit length value is less than the sum of the source side acknowledgement number and the source side window size, and the data unit acknowledgement number is less than the sum of the destination side acknowledgement number and the destination side window size.