Patent ID: 7550378

Claim:
A method of manufacturing a semiconductor device comprising: providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area; depositing a first insulating layer over the semiconductor substrate and then patterning the first insulating layer to form a first trench in the scribe line area and second trenches in the cell area; forming metal plugs in the second trenches such that the uppermost surface of the metal plug is coplanar with the uppermost surface of the patterned first insulating layer; forming metal interconnections over the patterned first insulating layer and electrically connected to a respective one of the metal plugs; depositing a second insulating layer over the semiconductor substrate including the first insulating layer, the metal interconnections and the metal plugs such that a step height difference exists between the cell area and the scribe line area; and then planarizing the second insulating layer through a chemical mechanical polishing (CMP) process after forming the metal interconnections, the CMP process including a first polishing step and a second polishing step having different removal rates with respect to the second insulating layer formed over the cell area and the scribe area.