Patent ID: 8495286

Claim:
A method for operating a DRAM main memory having a DRAM main memory access time, characterized by the steps of: a) operating a memory page concentration buffer ( 30 ) operatively connected to said DRAM main memory, said buffer ( 30 ) having a faster access time compared to said DRAM main memory access time, and comprising a plurality (N) of buffer lines ( 34 ), wherein each buffer line ( 34 ) may store a plurality of (M) data entries together with a main memory address, consisting of memory page ( 32 ) ID and internal page offset; b) in response to a write access request to said DRAM main memory, selecting a buffer line ( 34 ) corresponding to the memory page ID for buffering said data of said write access request; c) storing ( 420 ) said data of said write access request in an entry of said selected buffer line, if ( 415 ) the fill level of said selected buffer line ( 34 ) is not beyond a certain predefined fill level, otherwise generating a FULL signal representing that at least a plurality of P data need to be written to said DRAM main memory; in case said selected buffer line ( 34 ) comprises data entries of more than one memory page ( 32 ), sorting ( 425 ), in response to said FULL signal, said data entries in said selected buffer line ( 34 ) with respect to the main memory addresses, selecting ( 430 ) said plurality of P data entries from said selected buffer line, writing ( 435 ) said plurality of P selected data entries to said DRAM main memory, wherein a single memory page ( 32 ) remains open for writing access of said plurality of P data entries, and deleting ( 440 ) said selected plurality of P data entries from said selected buffer line ( 34 ).