Patent ID: 7352049

Claim:
A semiconductor device comprising: an SOI substrate including a substrate serving as a base, a buried oxide film provided on said substrate, and an SOI layer provided on said buried oxide film; plural first isolation films provided in a main surface of said SOI layer in a first region defined on said SOI substrate, with a portion of said SOI layer interposed therebetween; and plural resistive elements provided on said plural first isolation films in said first region, respectively, wherein at least a portion of each of said plural first isolation films passes through said SOI layer and reaches said buried oxide film to include a full-trench isolation structure, and wherein said SOI layer is an impurity layer of the first conductivity type, further comprising: a MOS transistor provided in an element forming region of said SOI layer; and a partial isolation region provided in said SOI layer, wherein said partial isolation region includes partial isolation films formed in an upper layer of said SOI layer and semiconductor region located under partial isolation films of the first conductivity type which is a part of said SOI layer in a lower layer, said MOS transistor includes the second conductivity type source/drain layers each selectively formed in said SOI layer, a gate electrode provided over a region of said SOI layer positioned between said source/drain layers, with a gate oxide film lying between said electrode and said region, and a channel region of the first conductivity type provided on an upper layer of said SOI layer between said source/drain layers, said channel region is electrically connected to a body-potential fixing region of the first conductivity type, with said semiconductor region located under partial isolation films lying between said channel region and said body-potential fixing region.