Patent ID: 8028210

Claim:
A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein each of said judging circuits comprises: a first clock control unit for controlling a transmission of a clock signal based on an enable signal; a first register for capturing the data from said logic circuits in a predetermined timing of said clock signal controlled by said first clock control unit; a first delay unit for delaying said clock signal; a second clock control unit for controlling a transmission of said clock signal, which has passed through said first delay unit, based on said enable signal; a second register logically equivalent to said first register for capturing the data from said logic circuits in a predetermined timing of said clock signal controlled by said second clock control unit; and a comparator for comparing an output from said first register and an output from said second register to output an error signal, and wherein said semiconductor device further comprises a detection circuit for detecting a setup violation of said enable signal, with respect to a plurality of said judging circuits for controlling said clock signal by said same enable signal.