Patent ID: 8762792

Claim:
An error monitor comprising: a) a clock lead; b) event monitor control leads; c) switch matrix circuitry having event inputs, event monitor control inputs connected to the event monitor control leads, and separate event signal outputs; d) first event counter circuitry having an input connected to a first event signal output, event monitor control inputs connected to the event monitor control leads, a clock input connected to the clock lead, and a first event count output; e) first event compare circuitry having an input connected to the first event count output, event monitor control inputs connected to the event monitor control leads, and a first error output; f) second event counter circuitry having an input connected to a second event signal output, event monitor control inputs connected to the event monitor control leads, a clock input connected to the clock lead, and a second event count output; and g) second event compare circuitry having an input connected to the second event count output, event monitor control inputs connected to the event monitor control leads, and a second error output.