Patent ID: 7779226

Claim:
A memory controller for controlling access to a flash memory having a plurality of physical blocks each of which is a minimum erasing unit, based on an address provided from a computer, the memory controller comprising: an initial setting module which initially assigns each of a plurality of virtual block addresses to each of a plurality of physical block addresses, said plurality of physical block addresses respectively indicating the plurality of physical blocks in the flash memory; a logical zone forming module which forms a plurality of logical zones each of which includes a plurality of logical blocks, each of said plurality of logical blocks having each of a plurality of logical block addresses defined based on a plurality of addresses within an address space of the computer; a virtual zone forming module which forms a plurality of virtual zones each of which includes a plurality of virtual blocks, each of said plurality of virtual blocks having each of a series of virtual block addresses; a zone assigning module which assigns each of the plurality of logical zones to each of the plurality of virtual zones; an address management module which manages a correspondence between the plurality of logical block addresses of one of the logical zones and the plurality of virtual block addresses of one of the virtual zones, said one of the logical zones being assigned to said one of the virtual zones, said correspondence being alterable in data re-writing in the flash memory; a first address converting module which converts a logical block address to a virtual block address based on the correspondence managed by said address management module; and a second address converting module which converts the virtual block address converted by said first address converting module to a physical address based on the assignment by said initial setting module, wherein said initial setting module determines a number of times of operations with a cyclic function for generating one-to-one mapping between one of the plurality of virtual block addresses and one of the plurality of physical addresses, said cyclic function having a predetermined recurring cycle, wherein said second address converting module converts the virtual block address to the physical address, based on the one-to-one mapping generated by executing the operations for the number of times, wherein the cyclic function is a tent function, wherein when the recurring cycle of the tent function is T and a total number of physical blocks in the flash memory to be assigned the plurality of virtual block addresses is N, then T and N satisfy a following relationship N=2 (T−1) .