Patent ID: 7843712

Claim:
An apparatus comprising: a first voltage input/output terminal and a second voltage input/output terminal; a voltage booster that receives a voltage from one of said first voltage input/output terminal and said second input/output terminal and outputs a boosted voltage from the other one of said first voltage input/output terminal and said second input/output terminal; an output selector that receives the boosted voltage from the voltage booster and selects any one of a positive or negative voltage to output; and an voltage regulator that receives the boosted voltage from the voltage booster and regulates the output voltage, wherein the output selector comprises a pump switch that selects output of a positive high voltage or a negative high voltage, wherein the pump switch comprises a first NMOS transistor, wherein a gate of the first NMOS transistor is connected to said first voltage input/output terminal and VSS is connected to a source/drain of the first NMOS transistor, wherein the pump switch comprises a first PMOS transistor, wherein a gate of the first PMOS transistor is connected to said first voltage input/output terminal and VDD is connected to a source/drain of the first PMOS transistor.