Patent ID: 8432925

Claim:
An apparatus, comprising: a memory configured to temporarily store one or more packets to be transmitted, each of the one or more packets being added with an arrival time at which the each of the one or more packets arrived at the apparatus; and a processor configured to: calculate a packet residence time indicating magnitude of an elapsed time during which at least one packet included in the one or more packets has been staying in the memory, using a current time and at least one arrival time added to the at least one packet, the at least one packet including a longest-staying packet that has been staying in the memory for the longest time period among the one or more packets, determine whether an arrival packet that has newly arrived at the apparatus, is to be discarded or to be stored in the memory, based on the calculated packet residence time, add, to the arrival packet that has been determined to be stored in the memory, the arrival time at which the arrival packet arrived at the apparatus, and store the arrival packet added with the arrival time in the memory as one of the one or more packets to be transmitted.