Patent ID: 6853596

Claim:
A semiconductor memory comprising: a core array including a plurality of memory cells; a redundant array to be substituted for a substitution object area including a defective cell in the core array; a substitution address memory storing an address of a first substitution object area including both sides of the defective cell as a substitution object address; and a redundancy controller controlling to substitute the redundant array for the core array, wherein, when the first substitution object area is entirely located on the inside of the core array, said redundancy controller controls to substitute the redundant array for said first substitution object area corresponding to the substitution object address, and when a portion of the first substitution object area is located on the outside of the core array, the redundancy controller controls to substitute the redundant array for a second substitution object area which includes the defective cell and is located on the inside of the core array, irrespective of the substitution object address.