Patent ID: 7793008

Claim:
A system comprising: a plurality of first controller circuits each configured to generate a plurality of control signals that control storage of data in a corresponding one of a plurality of peripheral devices; a plurality of line buffer circuits each (i) connected to a different one of a plurality of first busses in a one-to-one relationship as a bus slave having a write data bus interface and a read data bus interface and (ii) configured to transfer said data bi-directionally between an accessed one of said first controller circuits and said respective first bus while access is granted; a first arbiter circuit configured to arbitrate access to said first controller circuits by said line buffer circuits in response to a plurality of requests initiated by said line buffer circuits; and a configuration circuit configured to receive configuration data from a second bus and send said configuration data directly to (i) said line buffer circuits, (ii) said first arbiter circuit and (iii) said first controller circuits.