Patent ID: 7378289

Claim:
A method for forming test structures comprising: patterning a resist layer on a first semiconductor substrate to form a resist structure within production die regions of the first semiconductor substrate, the resist layer patterned by exposing portions of a photomask that includes a plurality of identical die regions configured to a design layer of a semiconductor design and a test pattern configured to a different design layer of a semiconductor design, the identical die regions disposed in a rectangular shape that covers most of the focus region and the test pattern disposed in a blading area of the photomask, wherein all of the identical die regions are exposed and the test pattern is not exposed; and patterning a resist layer on a second semiconductor substrate by exposing only the test pattern of the photomask to transfer the test pattern to a test die region of the second semiconductor substrate and exposing die regions from a different photomask to pattern production die regions of the second semiconductor substrate.