Patent ID: 6853698

Claim:
A ripple counter circuit, comprising: a clock input terminal; a control circuit having a test enable input terminal, a clock input terminal coupled to the clock input terminal of the ripple counter circuit, and a control output terminal, wherein the control circuit controls a signal on the control output terminal to alternate between a first value and a! second value; a first stage, comprising a first storage element having a data input terminal, a true data output terminal, a complement data output terminal, an initialization terminal, and a clock terminal, wherein the clock terminal is coupled to the clock input terminal of the ripple counter circuit, and wherein the complement data output terminal is coupled to the data input terminal; and a plurality of additional stages, each additional stage comprising an additional storage element having a data input terminal, a true data output terminal, a complement data output terminal, an initialization terminal, and a clock terminal, wherein the initialization terminal is coupled to the initialization terminal of the first storage element, and wherein the complement data output terminal is coupled to the data input terminal, and an additional multiplexer having an output terminal coupled to the clock terminal of the additional storage element, a first input terminal coupled to the true data output terminal of the storage element in a preceding stage, a second input terminal coupled to the complement data output terminal of the additional storage element in the preceding stage, and a select input terminal coupled to the control output terminal of the control circuit.