Patent ID: 7068089

Claim:
A frequency synthesizer circuit comprising: a phase locked loop having a voltage controlled oscillator producing an output frequency; a frequency divider receiving the output frequency of the voltage controlled oscillator and producing differential in-phase and quadrature signals; and a phase offset compensation circuit for compensating a phase offset between the in-phase and quadrature signals, the phase offset compensation circuit comprising: first pairs of series connected MOS varactors, each pair coupled between transmission lines of said in-phase differential signals; a first group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said first pairs of MOS varactors; second pairs of series connected MOS varactors, each pair coupled between transmission lines of said quadrature differential signals; a second group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said second pairs of MOS varactors; and a phase offset compensation logic circuit controlling the bias voltage controllers of the first and second groups in response to a phase offset compensation value received by the logic circuit to adjust the relative phases of the in-phase and quadrature signals.