Patent ID: 8217453

Claim:
A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising: a first uni-directional LDMOS transistor, further including: a first backgate region which is electrically isolated from a semiconductor substrate; and a first low resistance shunt which is electrically connected to said first backgate region and a source node of said first uni-directional LDMOS transistor; a second uni-directional LDMOS transistor, further including: a second backgate region which is electrically isolated from said semiconductor substrate and from said first backgate region; and a second low resistance shunt which is electrically connected to said second backgate region and a source node of said second uni-directional LDMOS transistor; a common n-type drain node, of which a portion of said common n-type drain node forms a drain node of said first uni-directional LDMOS transistor and a portion of said common n-type drain node forms a drain node of said second uni-directional LDMOS transistor; a first source/drain terminal of said three terminal bi-directional LDMOS transistor which is electrically connected to said source node of said first uni-directional LDMOS transistor; a second source/drain terminal of said three terminal bi-directional LDMOS transistor which is electrically connected to said source node of said second uni-directional LDMOS transistor; a first gate clamp circuit which is electrically connected to said first source/drain terminal and to a gate node of said first uni-directional LDMOS transistor; a second gate clamp circuit which is electrically connected to said second source/drain terminal and to a gate node of said second uni-directional LDMOS transistor; a first gate blocking diode which is electrically connected to a gate terminal of said three terminal bi-directional LDMOS transistor and to said gate node of said first uni-directional LDMOS transistor, wherein an anode of said first gate blocking diode is electrically connected to said gate terminal of said three terminal bi-directional LDMOS transistor and a cathode of said first gate blocking diode is electrically connected to said gate node of said first uni-directional LDMOS transistor; and a second gate blocking diode which is electrically connected to said gate terminal of said three terminal bi-directional LDMOS transistor and to said gate node of said first uni-directional LDMOS transistor, wherein an anode of said second gate blocking diode is electrically connected to said gate terminal of said three terminal bi-directional LDMOS transistor and a cathode of said second gate blocking diode is electrically connected to said gate node of said second uni-directional LDMOS transistor.