Patent ID: 8837213

Claim:
A semiconductor memory device comprising: a memory cell; a flag memory cell configured to store a flag, the flag memory cell being configured to be selected at the same time as the memory cell; a dummy cell configured to be selected at the same time as the memory cell and the flag memory cell; and a controller configured to control write and read of the memory cell, the flag memory cell and the dummy cell, wherein the controller is configured to set, by a first write operation, a threshold voltage of the memory cell from a first threshold voltage to the first threshold voltage or a second threshold voltage (first threshold voltage<second threshold voltage), the controller is configured to set, by a second write operation, the threshold voltage of the memory cell to the first threshold voltage or a third threshold voltage (first threshold voltage<third threshold voltage) when the threshold voltage of the memory cell is the first threshold voltage, and to set the threshold voltage of the memory cell to a fourth threshold voltage or a fifth threshold voltage (second threshold voltage<=fourth threshold voltage<fifth threshold voltage) when the threshold voltage of the memory cell is the second threshold voltage, and the controller is configured to set, at a time of the second write operation, a threshold voltage of the flag memory cell, which is selected at the same time as the memory cell, from the first threshold voltage to the fourth threshold voltage, and to set a threshold voltage of the dummy cell, which neighbors the flag memory cell, from the first threshold voltage to the third threshold voltage.