Patent ID: 7269716

Claim:
A processor comprising: an instruction issuing unit which issues fetched and decoded instructions to a reservation station in-order; an instruction executing unit which executes out-of-order the instructions issued to said reservation station; a committing unit which discriminates a commitment of the instructions executed by said instruction executing unit and completes them in-order; an instruction fetching unit which simultaneously fetches a plurality of instructions including a condition code update instruction and a condition code read instruction into said instruction issuing unit; a renaming map update processing unit which, at a decoding stage of said condition code update instruction, when a renaming register which holds condition code update data until the commitment of the condition code update instruction is allocated, registers condition code information including a register number of said renaming register into a renaming map for a condition code; a renaming map reference processing unit which develops said condition code read instruction into a multiflow instruction, transfers and holds the multiflow instruction into a multiflow instruction word register at a decoding stage of the condition code read instruction after no-operation has been performed by the condition code read instruction during the decoding stage of the condition code update instruction, and stores the condition code information of the condition code update instruction registered in said renaming map for the condition code into a source register area of a previous instruction allocation entry stored in said reservation station; a forward control discriminating unit which, at a priority stage of said condition code update instruction, compares a renaming register number of an execution result with a renaming register number in the previous instruction allocation entry in said reservation station and, when they coincide, notifies said instruction executing unit of completion of preparation for forward control of condition data for the condition code read instruction and allows said instruction executing unit to execute the condition code read instruction thereby avoiding simultaneous renaming of said condition code by both said condition code update instruction and said condition code read instruction; and a condition data write processing unit which, at an updating stage of said condition code update instruction, stores condition code data obtained as an execution result of the condition code update instruction into the source register area of the previous instruction allocation entry stored in said reservation station.