Patent ID: 8558362

Claim:
A semiconductor device, comprising: (a) a plurality of leads each having a first upper surface, a first step part formed at an end part of the first upper surface, and a first lower surface opposite to the first upper surface, where the first step part has a second upper surface arranged on the same side of the leads as the first upper surface, and a second lower surface opposite to the second upper surface; (b) a chip mounting part arranged between the leads adjacent to one another in a cross-section view, where the chip mounting part has a third upper surface arranged on the same side as the first upper surface, a second step part formed at a peripheral part of the third upper surface in a plan view, and a third lower surface opposite to the third upper surface, and where the second step part has a fourth upper surface arranged on the same side as the third upper surface, and a fourth lower surface opposite to the fourth upper surface; (c) a semiconductor chip having a front surface, a plurality of electrodes formed on the front surface, and a rear surface opposite to the front surface, and mounted over the third upper surface of the chip mounting part via a paste material such that both the second upper surface of the first step part located between the first upper surface and the first lower surface in the cross-section view and the fourth upper surface of the second step part located between the third upper surface and the third lower surface in the cross-section view are overlapped by the rear surface of the semiconductor chip in a plan view; (d) a plurality of wires electrically connecting the electrodes with the leads, respectively, wherein each of the wires is connected to the first upper surface of respective ones of the leads; and (e) a sealing body sealing the semiconductor chip and the wires such that the first lower surface of each of the leads and the third lower surface of the chip mounting part are exposed from the sealing body, wherein the first step part of each of the leads faces the chip mounting part and the second step part is formed at a peripheral part of the third upper surface such that the first step part and the second step part face each other, wherein the second upper surface of the first step part and the fourth upper surface of the second step part are disposed at the same height, wherein a width of the first upper surface is larger than a width of the first lower surface, the width of the first upper surface and the width of the first lower surface being defined in a direction parallel to an edge of the sealing body in the plan view, and wherein a size of the chip mounting part is smaller than that of the semiconductor chip in the plan view.