Patent ID: 6915476

Claim:
A semiconductor integrated circuit device including a memory array having first to Nth banks, where N being an integer greater than or equal to 2, the memory array further including a redundancy block comprising: first to Nth column recovery circuit blocks corresponding to the first to Nth banks; first to Nth row recovery circuit blocks corresponding to the first to Nth banks; first to Nth ECC fuse blocks corresponding to the first to Nth banks; and first to Nth ECC circuits corresponding to the first to Nth banks; wherein, during initial cycles started by an input of an initial-cycle start command to the semiconductor integrated circuit device, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.