Patent ID: 7418541

Claim:
A method in a data processing system for indirect access from a support processor to memory-mapped resources on multiple support chips, the method comprising: receiving an input to the data processing system from the support processor into one or more input registers using a first field replaceable unit support interface, wherein the input is across multiple separate transfers on the first field replaceable unit support interface, and wherein the support processor performs other unrelated processing between the multiple separate transfers on the first field replaceable unit support interface; responsive to receiving the input, generating a command packet, wherein the command packet includes a command based on the input received, wherein the command is comprised of an address specifying a target for the command and one of a read command and a write command, wherein the write command includes data, and wherein generating the command packet is performed by coherency fabric generation logic; initiating the command packet on a bus, wherein the bus is a coherency fabric bus structure; updating first bits in a status register in the data processing system to indicate that the command packet has been sent but a response packet has not yet been received; forwarding the command packet to a support chip using one or more transfers on a second field replaceable unit support interface; processing the command on the support chip; responding to the command from the support chip using the second field replaceable unit support interface; generating the response packet with the response from the support chip, wherein the command packet and the response packet are both coherency fabric packets, and wherein multiple command and response packets may be active on the bus at the same time from different sources to the same or different targets; monitoring the bus for a response packet by a coherency fabric snoop logic; receiving the response packet; writing response data from the response packet to a data register; updating second bits in the status register in the data processing system to indicate that the response packet has been received and the response data is available for the read command, wherein updating the second bits in the status register includes reporting any error indicated in the response packet; monitoring the second bits in the status register by the support processor using the multiple separate transfers on the first field replaceable unit support interface; and accessing register values for the response data by the support processor using the multiple separate transfers on the first field replaceable unit support interface.