Patent ID: 6998676

Claim:
A semiconductor memory device with a fin-type transistor comprising: a projecting semiconductor region formed on a major surface of a semiconductor substrate of a first conductivity type; a gate electrode formed on at least opposed side surfaces of the projecting semiconductor region, with a gate insulating film interposed; source and drain regions of a second conductivity type formed in the projecting semiconductor region such that the source and drain regions sandwich the gate electrode; a channel region of the first conductivity type formed in the projecting semiconductor region between the source and drain regions; a device isolation insulating film formed on the semiconductor substrate such that the device isolation insulating film is interposed between the projecting semiconductor region and the semiconductor substrate, wherein the following relationship is established: T FIN ≧(∈/4 qN CH ) 1/2 where T FIN is a width of the projecting semiconductor region, N CH is an impurity concentration in the channel region, ∈ is a dielectric constant of a semiconductor material of the projecting semiconductor region, and q is an elementary charge; and wherein when a gate length L G is 0.15 μm or less, and a thickness T OX of the gate insulating film thickness is 0.008 μm or less, a width of the projecting semiconductor in a direction perpendicular to the channel region just under the gate electrode satisfies the following relationship: T FIN ≦a ′( T OX )×exp( b ′( T OX )×L G ) where a ′( T OX )=0.0149×(1−88.4 ×T OX ),and b ′( T OX )=26.3×(1−36.2 ×T OX ).