Patent ID: 8300444

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in a matrix, each memory cell using a variable resistor; a pulse generator operative to generate plural types of write pulses for varying the resistance of said variable resistor based on write data; a selection circuit operative to apply write pulses generated by said pulse generator to one of said memory cells; a sense amplifier operative to execute verify read to said memory cell; a status decision circuit operative to decide a verify result based on an output from said sense amplifier; and a control circuit operative to execute additional write to said memory cell based on said verify result from said status decision circuit, wherein said sense amplifier executes verify read to plural memory cells in batch, and wherein said control circuit makes the verify result pass if a number of bits with the verify result indicative of fail is not more than a number of pre-determined allowable failed bits.