Patent ID: 7605070

Claim:
A method for fabricating a semiconductor device comprising the steps of: forming a plurality of gate patterns directly on a substrate; filling the space between the gate patterns by forming an inter-layer insulation layer on the substrate; forming a contact hole, which exposes a predetermined surface of the substrate between the gate patterns, by selectively etching the inter-layer insulation layer; performing a first pre-cleaning process to recover a defect on a bottom portion of the contact hole and remove a first natural oxide layer; forming a sacrificial layer at a temperature, where an amorphous structure is formed, to remove a fine oxide layer remaining on a surface of the substrate of the bottom portion of the contact hole after performing the first pre-cleaning process; removing the sacrificial layer; forming an epitaxial stack including at least a SEG-silicon germanium layer through the SEG process on the contact hole; performing a second pre-cleaning process to remove a second natural oxide layer on a surface of the epitaxial stack; and forming a metal layer filling the contact hole on the epitaxial stack, wherein a surface of the metal layer is formed on a same plane as a surface of the gate patterns.