Patent ID: 7900022

Claim:
A processing unit, comprising: an input buffer to store data received by the processing unit wherein the data received by the processing unit is received from a multiplier or shared memory logic; a memory, coupled to the input buffer via a first path; an arithmetic logic unit coupled to the input buffer and to the memory, the arithmetic logic unit to perform operations on operands provided by the input buffer and the memory, wherein the first path does not include the arithmetic logic unit; a shifter coupled to an output of the arithmetic logic unit; at least one output buffer coupled to the shifter and the memory to store data to transfer from the processing unit to the multiplier or to the shared memory logic; and control logic having access to a control store of program instructions, the control logic to process instructions including: a first instruction to transfer data from the input buffer to the memory; a second instruction to cause the arithmetic logic unit to perform an operation on operands provided by both the memory and the input buffer, the second instruction to output results of the operation to at least one of the memory and the output buffer; and a mode instruction configured to change a mode of operation of the processing unit from a run mode to an I/O mode and from the I/O mode to the run mode, wherein the input buffer and the output buffer are configured to exclusively exchange data with the shared memory logic in the I/O mode and to exclusively exchange data with the multiplier in the run mode.