Patent ID: 7067872

Claim:
A semiconductor memory device provided with a memory cell region, having first gate electrodes and a selecting transistor region having second gate electrodes, comprising: the first gate electrodes arranged a first distance apart from each other on a semiconductor substrate; the second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate; first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes; second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes; a first insulating film formed on the first diffusion layers and covering the first diffusion layers; second insulating films formed on the side surfaces of the second gate electrodes; third insulating films formed on the second diffusion layers and covering the second diffusion layers; first silicide films formed on the first gate electrodes; and second silicide films formed on the first gate electrodes; wherein the respective thicknesses A 1 and A 2 of the first and second insulating films as formed satisfy the relationships X/2≦A 1 ≦Y/2 and X/2≦A 2 ≦Y/2, where X represents the first distance, and Y represents the second distance.