Patent ID: 7880457

Claim:
A method for converting a DC input voltage (V IN ) to a DC output voltage (V OUT ), the method comprising the steps of: generating a first pulse width modulated (PWM) clock signal having a first duty cycle associated therewith and a second PWM clock signal having a second duty cycle associated therewith; continuously determining which one of the first duty cycle of the first PWM clock signal and the second duty cycle of the second PWM clock signal has a lower duty cycle value; generating a PWM output signal having a modulated duty cycle equal to the one of the first duty cycle and the second duty cycle that is determined to have the lower duty cycle value; and concurrently maintaining, based on the PWM output signal, the output voltage (V OUT ) at less than or equal to a desired maximum value of the output voltage (V OUT ) and the input voltage (V IN ) at greater than or equal to a desired minimum value of the DC input voltage (V IN ).