Patent ID: 7476590

Claim:
A method of manufacturing a semiconductor device which comprises: a semiconductor substrate body; a hetero semiconductor region which is in contact with a major surface of the semiconductor substrate body, and whose bandgap is different from that of the semiconductor substrate body; a gate electrode arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with a gate insulating film interposed between the gate electrode and the junction part; a source electrode connected to the hetero semiconductor region; and a drain electrode ohmically connected with the semiconductor substrate body, the method comprising: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings such that a predetermined thickness of the hetero semiconductor layer remains at the openings; oxidizing a portion of the hetero semiconductor layer to form an oxidized film thereon; forming the hetero semiconductor region by etching the oxidized film; and forming the gate insulating film such that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body.