Patent ID: 7965541

Claim:
A field programmable gate array (FPGA) system comprising: a first and second inverters connected to each other in a cross-coupled manner, wherein gates of transistors within said first inverter are connected to drains of transistors within said second inverter via a first feedback resistor, and gates of transistors within said second inverter are connected to drains of transistors within said first inverter via a second feedback resistor; a first FPGA unit connected to said drains of transistors within said first inverter; a second FPGA unit connected to said drains of transistors within said second inverter; a first chalcogenide memory element, connected to said first inverter, for receiving and storing device configuration information from said first FPGA unit; and a second chalcogenide memory elements, connected to said second inverters, for receiving and storing device configuration information from said second FPGA unit.