Patent ID: 7898030

Claim:
A high-voltage NMOS transistor comprising: a deep n-conductively doped well (DN) and therein a deep p-conductively doped well formed in a semiconductor body or substrate at a top side; an n-conductively doped source region arranged in the deep p-conductively doped well; a channel region adjoining the source region; a gate electrode above the channel region, said gate electrode being electrically insulated from the channel region; an n-conductively doped drain region arranged on a side of the channel region opposite to the source region; and a drift path between the channel region and the drain region; wherein a portion of the deep p-conductively doped well is present along the drift path; a drain-side interface of the deep p-conductively doped well is arranged in a region of the drift path; a counterdoping region having an n-type conductivity implanted with donors overlaps a region of the deep p-conductively doped well that is present at the top side of the semiconductor body or substrate, and forms at least one portion of the drift path; and wherein the drain-side interface of the counterdoping region having the n-type conductivity is arranged in the region of the drift path, and the drain region is situated in a shallow n-conductively doped well arranged in the deep n-conductively doped well at a distance from the counterdoping region.