Patent ID: 7257041

Claim:
A memory circuit comprising: a plurality of memory cells for respectively storing data; a plurality of column lines for respectively connecting at least one memory cell; a plurality of pre-charge units, each pre-charge unit corresponds to one of the column lines, when one of the pre-charge unit is enabled, the pre-charge unit charges the corresponding column line; when the pre-charge unit is disabled, the pre-charge unit stops charging the corresponding column line; a column pre-decoder, providing a corresponding selection signal for each column line to indicate whether the column line is connected to a objective memory cell when the objective memory cell is to be accessed; a sense amplifier, electrically connected to the objective memory cell for receiving and sensing the stored data; a plurality of control units, respectively corresponding to one of the column lines, for respectively receiving the corresponding selection signal and enabling or disabling the corresponding pre-charge unit according to the corresponding selection signal, so that the pre-charge units are independently and respectively enabled or disabled according to whether the column line is connected to the objective memory cell; and a plurality of accessing units disposed between the column lines and the sense amplifier, wherein each accessing unit is enabled to be conducted or is disabled to be not conducted, and one of the column lines is electrically connected to the sense amplifier only when all the accessing units corresponding to the column line are conducted; wherein the column pre-decoder records the corresponding decision signal to determine whether the accessing units corresponding to the column lines should be enabled or disabled.