Patent ID: 7218155

Claim:
An integrated circuit comprising a calibration circuit that controls a termination resistance in a buffer coupled to a first pin, the calibration circuit comprising: first transistors; and a control circuit coupled to the first transistors that monitors an effective resistance of the first transistors and that selectively enables a set of the first transistors using control signals generated by a counter circuit, the control circuit selecting values of the control signals corresponding to the effective resistance of the first transistors that is nearest to a resistance value, wherein the selected control signals are used to control a termination resistance of second transistors in the buffer, wherein the control circuit comprises: a first comparator coupled to monitor a voltage across the first transistors, wherein the counter circuit is coupled to monitor an output signal of the first comparator; a first storage circuit coupled to receive the control signals generated by the counter circuit; second and third comparators coupled to monitor the voltage across the first transistors; and a logic gate coupled to receive output signals of the second and the third comparators, an output signal of the logic gate indicating when the voltage across the first transistors is within a selected voltage range.