Patent ID: 8258813

Claim:
A circuit having a controlled output impedance during all operating phases, including the positive and negative full-signal operation phases as well as the switching phases between said positive and negative full-signal operation phases, comprising: a) the circuit being configured for being supplied by a voltage source for driving at least one differential line which can be connected to at least one first output connection and to at least one second output connection for the purpose of digital data transmission; b) the circuit having at least two paths which are arranged in a mirror-image fashion relative to one another and which connect the voltage source to at least one reference potential; c) the first path including: i) at least one first transistor including at least one first n-channel MOSFET, whose gate connection is assigned to at least one first input connection which can be acted upon by at least one first control voltage; and ii) at least one second transistor including at least one second n-channel MOSFET, whose gate connection is assigned to at least one second input connection which can be acted upon by at least one second control voltage, and the first output connection is connected between the first transistor and the second transistor; d) the second path including: i) at least one third transistor including at least one third n-channel MOSFET, whose gate connection is assigned to at least one third input connection which can be acted upon by at least one third control voltage; and ii) at least one fourth transistor including at least one fourth n-channel MOSFET, whose gate connection is assigned to at least one fourth input connection which can be acted upon by at least one fourth control voltage, and the second output connection is connected between the third transistor and the fourth transistor; e) in the first path there is provided: i) at least one first drain degradation resistance which is connected between the voltage source and the drain connection of the first transistor; f) in the second path there is provided: i) at least one second drain degradation resistance which is connected between the voltage source and the drain connection of the third transistor; g) at least one first separating resistance is connected between the source connection of the first transistor and the first output connection, and at least one second separating resistance is connected between the drain connection of the second transistor and the first output connection; and h) at least one third separating resistance is connected between the source connection of the third transistor and the second output connection, and at least one fourth separating resistance is connected between the drain connection of the fourth transistor and the second output connection.