Patent ID: 7436650

Claim:
A laminated ceramic capacitor comprising: at least two capacitance forming layers in which at least one ceramic dielectric layer and capacitance-forming inner electrode layers that contribute to the formation of electrostatic capacitance are laminated; at least one stress relieving layer in which ceramic dielectric layers and at least one dummy inner electrode layer that does not contribute to the formation of electrostatic capacitance are laminated, the stress relieving layer being disposed between two adjacent capacitance forming layers so as to relieve stress caused by electrostriction in the capacitance forming layers; and capacitance-formation-preventing inner electrode layers that prevent capacitance from being formed between the capacitance-forming inner electrode layers and the dummy inner electrode layer, each of the capacitance-formation-preventing inner electrode layers being disposed between each of the capacitance forming layers and the stress relieving layer; wherein a thickness of the stress relieving layer is in the range of about 100 μm to about 300 μm inclusive; a plane area of the dummy inner electrode layer in a single layer is about 60% or more of a plane area of the capacitance-forming inner electrode layer in a single layer; and the dummy inner electrode layer is undivided or is divided into at least two parts in a single layer.