Patent ID: 7535250

Claim:
A method for calibrating the impedance at a plurality of nodes in an integrated circuit, comprising: prior to useful operation of the integrated circuit: defining a plurality of groups of node circuitry, each group comprising a plurality of node circuitry, each node circuitry associated with one node; evaluating for each group an impedance of a model representative of an impedance of the node circuitry in each group, wherein each evaluated impedance is unique to its associated group, wherein each model is proximate to its associated node circuitry group, and wherein the model is distinct from the plurality of node circuitry and is not associated with any particular one of the plurality of nodes; and in response to each evaluated impedance, generating a plurality of sets of control signals for each node circuitry group to calibrate the impedance of the node circuitry in each group, wherein each set of control signals comprises a plurality of control signals sent to one model and to that model's associated node circuitry, and wherein the plurality of control signals are unique to its associated group.