Patent ID: 7061306

Claim:
A method of boosting a programming voltage, comprising: applying a first voltage to a first source/drain region of a first transistor and a first source/drain region of a second transistor while the first and second transistors are activated; applying a voltage from a second source/drain region of the first transistor to a gate of a third transistor and a first source/drain region of a fourth transistor, wherein the voltage from the second source/drain region of the first transistor is sufficient to activate the third transistor; applying a voltage from a second source/drain region of the second transistor to a first source/drain region of the third transistor, to a gate of the fourth transistor and to a gate and a first source/drain region of a fifth transistor, wherein the voltage from the second source/drain region of the second transistor is sufficient to activate the fourth and fifth transistors; applying the programming voltage to a second source/drain region of the third transistor and a second source/drain region of the fourth transistor; applying a first clock signal to a first terminal of a first capacitor, wherein the gates of the fourth and fifth transistors are coupled to a second terminal of the first capacitor; applying a second clock signal to a first terminal of a second capacitor, wherein the gate of the third transistor is coupled to a second terminal of the second capacitor and wherein the second clock signal is a complement of the first clock signal; generating a boosted voltage at a second source/drain region of the fifth transistor that is higher than the programming voltage.