Patent ID: 7638412

Claim:
A method for reducing charge damage in a silicon-on-insulator device during fabrication, comprising: providing an oxide layer over a substrate; providing a field effect transistor structure over the oxide layer; the transistor structure including source and drain regions of a first conductivity type separated by a body region of a second conductivity type, a gate oxide over the body region, and a gate over the gate oxide; providing a diode over the oxide layer, spaced by an oxide region from the source region of the transistor structure; the diode comprising a material of the first conductivity type and a material of the second conductivity type disposed in a p-n junction configuration; providing a metallization layer to form a conductive contact to the gate; and conductively coupling the metallization layer through the diode to the source region to enable charge built up on the metallization layer to discharge to the source region and to the body region under the gate oxide, thereby reducing potential difference across the gate oxide during fabrication of the device wherein an electrical interconnection layer is formed above and in contact with the oxide region and at least a portion of each of the source region and the diode.