Patent ID: 8819359

Claim:
A memory system, comprising: a set of N memory modules, wherein each memory module in the set of N memory modules includes a plurality of ranks, wherein each rank is an independent memory that provides the full data width of the memory module, and wherein the plurality of ranks in each memory module share a common data path for the memory module; and a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that, physical addresses for a given page all map to a given subset of M memory modules, wherein M<N, and physical addresses for the given page are interleaved across a plurality of ranks which comprise the given subset of M memory modules, wherein the hybrid interleaving mechanism is configured to: for a given physical address in the physical addresses, use a first set of bits in the physical address to select a given memory module in the M memory modules and a second set of bits in the physical address to select a rank within the given memory module; and at least one of use the first set of bits to specify a granularity for an inter-memory-module interleaving of the given page between the M memory modules and use the second set of bits to specify a granularity for an intra-memory-module interleaving for at least a portion of the given page that is interleaved across ranks of a memory module corresponding to the first set of bits.