Patent ID: 8426294

Claim:
A method for manufacturing a memory device, comprising: providing a substrate including an array of access devices and a first set of bit lines, the substrate having a surface with an array of contacts, including contacts coupled to access devices in the array of access devices and contacts coupled to bit lines in the set of bit lines; forming a stack of alternating layers of word line material and insulating material over the array of contacts; forming trenches in the stack, the trenches exposing respective rows of contacts on the surface of the substrate coupled to access devices and exposing contacts on the surface of the substrate coupled to bit lines in the first set of bit lines, and having sidewalls exposing word line material in the layers of word line material in the stack; forming a charge trapping structure, lining the sidewalls of the trenches at least on word line material exposed on sidewalls of the trenches; forming semiconductor body pillars within the trenches over the charge trapping structure, the semiconductor body pillars contacting respective contacts in the rows of contacts in the trenches; forming bit line pillars within the trenches on first and second opposing sides of the semiconductor body pillars and within the trenches, where bit line pillars on the first side of the semiconductor body pillars contact respective contacts coupled to a bit line in the first set of bit lines; and forming a second set of bit lines coupled to the bit line pillars on the second opposing side of the semiconductor body pillars.