Patent ID: 7505589

Claim:
A method of scrambling a first ternary signal with a scrambler, each ternary signal being able to assume on of three states and the scrambler having a first scrambling ternary logic device that implements a ternary logic function, sc, the first scrambling ternary logic device having a first input enabled to receive the first ternary signal and a second input enabled to receive a second ternary signal and an output enabled to provide a third ternary signal and a scrambling logic circuit having an input and an output enabled to provide the second ternary signal, comprising: inputting the ternary signal on the first input of the first scrambling ternary logic device and providing the second ternary signal from the output of the scrambling logic circuit to the second input of the first scrambling ternary logic device; inputting the third ternary signal provided on the output of the first scrambling ternary logic device to the input of the scrambling logic circuit; wherein a state of the first ternary signal on the first input of the first scrambling ternary device may be represented by A, a state of the second ternary signal on the second input of the first scrambling ternary device may be represented by B and a state of the third ternary signal provided on the output of the first scrambling ternary device may be represented by C, and the ternary logic function, sc, satisfies the following equations for all possible combinations of A and B: A sc B=C; C sc B=A; and A sc C=B; and whereby the output of the first scrambling ternary logic device provides a scrambled version of the ternary signal.