Patent ID: 7329954

Claim:
A semiconductor chip comprising: a silicon substrate; multiple semiconductor devices in or over said silicon substrate; an interconnecting metallization structure over said silicon substrate, wherein said interconnecting metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a separating, passivation layer over said interconnecting metallization structure and over said dielectric layer, wherein said separating, passivation layer comprises multiple inorganic layers and an organic layer, said organic layer being over said multiple inorganic layers, wherein said organic layer has a thickness greater than that of said dielectric layer, and wherein a first opening in said separating, passivation layer exposes a first contact point of said interconnecting metallization structure, and a second opening in said separating, passivation layer exposes a second contact point of said interconnecting metallization structure, wherein said first contact point is separate from said second contact point; and an upper metallization structure over said separating, passivation layer and over said first and second contact points, wherein said upper metallization structure comprises an electroplated metal, and wherein a connecting portion of said upper metallization structure connects at least one portion of said interconnecting metallization structure with at least one other portion of said interconnecting metallization structure through said first and second openings and through said first and second contact points, wherein said connecting portion of said upper metallization structure comprises a signal distribution interconnect.