Patent ID: 8921901

Claim:
A stacked wafer structure, comprising: a CIS wafer comprising: a CIS substrate having a front side and a back side opposing to the front side; a first dielectric layer disposed on the front side of the CIS substrate; and at least one set of first conductive stack disposed within the first dielectric layer; an ISP wafer comprising: an ISP substrate; a second dielectric layer disposed on the ISP substrate; at least one set of second conductive stack disposed within the second dielectric layer; and at least one active device disposed on the ISP substrate; a lamination layer disposed between the first dielectric layer and the second dielectric layer so as to bond the CIS wafer to the ISP wafer; a through silicon via penetrating the CIS wafer and the lamination layer so as to electrically connects the first conductive stack to the second conductive stack; and a pixel device disposed on the back side of the CIS substrate.