Patent ID: 7287171

Claim:
A method for reducing power consumption in a programmable logic device, the programmable logic device comprising a plurality of transistors, the method comprising: evaluating, during a synthesis period relating to a first transistor or group of transistors, whether the first transistor or group of transistors is used for a design implemented in the programmable logic device; if the first transistor or group of transistors is not used for the design, evaluating a second transistor or group of transistors; if the first transistor or group of transistors is used for the design, determining whether the first transistor or group of transistors can be reverse biased to operate in a low power mode; and if the first transistor or group of transistors can be reverse biased to operate in a low power mode and a programmable logic device speed specification and a programmable logic device routability specification permit, reverse biasing the first transistor or group of transistors to operate in low power mode.