Patent ID: 7843724

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when performing 4-value data programming, read or erasure with respect to at least one of the plurality of memory cells, selecting and applying a voltage to a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines; wherein the memory cell array stores a plurality of flags related to a data programming state in each of the plurality of memory cells; the data reading and programming control section includes: an adjacent memory cell data reading section which confirms whether or not data is programmed in a lower page of a second memory cell adjacent to a first memory cell in the memory cell array using the flag corresponding to the second memory cell, and which generates adjacent memory cell state data which represents a data state of the second memory cell; an adjacent memory cell data memory section for storing the adjacent memory cell state data generated by the adjacent memory cell data reading section; a reading voltage level control section which controls each of a plurality of predetermined reading voltage verify levels to a reading voltage verify level added with a predetermined level when the 4-value data is read from the first memory cell when confirmed using the adjacent memory cell state data that data is programmed to the lower page of the second memory cell, and the reading voltage level control section which controls each of the predetermined plurality of reading voltage verify levels to a predetermined level when confirmed using the adjacent memory cell state data that data is not programmed to the lower page of the second memory cell; a data reading section for reading the data from the first memory cell at a plurality of reading voltages corresponding to the plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.