Patent ID: 7139877

Claim:
A cache memory, comprising: a plurality of storage elements, arranged as a last-in-first-out (LIFO) memory, for storing data exclusively specified by push instructions, wherein each of said push instructions implicitly specifies a data memory address based on a value stored in a microprocessor stack pointer register rather than explicitly specified by the push instruction, said LIFO memory having a top one of said plurality of storage elements for storing a cache line of data specified by a plurality of most-recent said push instructions, and for storing a virtual address and a physical address of said cache line; a comparator, coupled to said top storage element, for comparing said cache line virtual address with a source virtual address of data requested by a load instruction; and an output, coupled to said comparator, for speculatively indicating said data requested by said load instruction is present in the cache memory if said comparator indicates said source virtual address matches said cache line virtual address stored in said top storage element, prior to determining whether a source physical address of said data requested by said load instruction matches said physical cache line address.