Patent ID: 7663203

Claim:
A high-voltage PMOS transistor comprising: an insulated gate electrode; a p-conductive source region in an n-conductive well which is arranged on a p-conductive substrate; a p-conductive drain region in a p-conductive well which is arranged in said n-conductive well, said drain region having a portion facing away from said n-conductive well and forming part of a plane corresponding to an upper surface of the transistor; and an insulation area between said gate electrode and said drain region; wherein a lower boundary of the n-conductive well extends a shorter distance into the p-conductive substrate away from the upper surface underneath said drain region than the lower boundary of the n-conductive well extends into the p-conductive substrate away from the upper surface underneath said source region, and a lower boundary of the p-conductive well extends a farther distance into the n-conductive well away from the upper surface underneath said drain region than the lower boundary of the p-conductive well extends into the n-conductive well away from the upper surface underneath a region lateral to said drain region.