Patent ID: 7190023

Claim:
A semiconductor device comprising: a plurality of memory cells each of which includes: a first diffusion region formed in a semiconductor substrate; a second diffusion region formed in the semiconductor substrate; a first gate electrode formed over a region of semiconductor substrate between the first and second diffusion regions; a second gate electrode formed over the region of semiconductor substrate between the first and second diffusion regions; a charge storage film formed over the region of semiconductor substrate between the first and second diffusion regions, having discrete traps, and located between the first and second gate electrodes; and a third gate electrode formed over the charge storage film; a word line coupled to the third gate electrodes of the plurality of memory cells which are arranged in a first direction; and a bit/source line coupled to first diffusion regions of the plurality of memory cells which are arranged in a second direction intersecting the first direction, wherein the first gate electrodes of the plurality of memory cells arranged in the second direction are coupled to each other, and wherein the second gate electrodes of the plurality of memory cells arranged in the second direction are coupled to each other.