Patent ID: 7316971

Claim:
A method, comprising: forming an interlevel dielectric layer on a substrate; forming a plurality of electrically conductive wires in said interlevel dielectric layer, top surfaces of said wires coplanar with a top surface of said interlevel dielectric layer; forming a passivation layer on said top surfaces of said wires and said interlevel dielectric layer; removing regions of said passivation layer to form via opening in said passivation layer over said plurality of wires, there being a respective via opening for each wire of said plurality of wires, said via openings extending from a top surface of said passivation layer to said top surfaces of said wires; forming an electrically conductive layer on a top surface of said passivation layer; patterning said conductive layer into a plurality of wire bond pads spaced apart, each wire bond having first and second opposite ends, said top surface of said passivation layer exposed between said wire bond pads, top surfaces of said wire bond pads being top surfaces of said patterned conductive layer and being parallel to said top surface of said substrate, said first ends of each wire bond pad of said plurality of wire bond pads extending over a respective via opening, filling said via opening and electrically contacting a respective wire of said plurality of wires; after said patterning, forming a first dielectric layer directly on said top surface of said passivation layer in spaces between said wire bond pads, on all sidewalls of said wire bond pads, and directly on said top surfaces of said wire bond pads, said first dielectric layer not filling said spaces between adjacent sides of said wire bond pads; after said forming said first dielectric layer, forming a second dielectric layer on a top surface of said first dielectric layer, said second dielectric layer filling remaining spaces between adjacent sidewalls of said wire bond pads; and after said forming said second dielectric layer, completely removing said first and second dielectric layers from said top surfaces of said wire bond pads, newly formed top surfaces of said first and second dielectric layers coplanar with said top surfaces of said wire bond pads.