Patent ID: 7673117

Claim:
A physical operation apparatus comprising: i. a processor; ii. a memory associated with the processor and including a plurality of registers; iii. a first generator running in the memory and corresponding to at least one of the plurality of registers which is configured to generate first source data storable in respective registers; iv. a second generator running in the memory and corresponding to at least one of the plurality of registers which is configured to generate second source data storable in respective registers; and v. a spatially arranged operation element running in the memory which is configured to perform a predetermined data flow operation, wherein, vi. each generator temporarily stores the predetermined operation results in the respective registers, vii. the predetermined operation is performed independent of the respective registers of the first and second generators and in association with the first source data and the second source data by switching operations in response to a control signal, viii. the first generator or the second generator provides the control signal together with the generated first source data or the generated second source data to the operation element, and ix. the control signal controls reading and writing of data held by the plurality of registers.