Patent ID: 8570266

Claim:
A display device comprising: gate signal lines arranged in a plurality of rows; source signal lines arranged in a plurality of columns; a pixel portion including a plurality of pixels, each of the pixels being surrounded by two adjacent ones of the gate signal lines and two adjacent ones of the source signal lines; a source signal line driver circuit electrically connected to the source signal lines; and a gate signal line driver circuit electrically connected to the gate signal lines, wherein the gate signal line driver circuit includes a shift register and a latch circuit, the latch circuit comprising a plurality of stages, wherein each stage of the latch circuit comprises an RS latch circuit, wherein a given stage is configured to be inputted with a signal in accordance with an output of an RS latch circuit of a previous stage, wherein a first stage of the shift register is configured to be inputted with a clock signal, a first start pulse signal and a second start pulse signal, and to output a row selection pulse in accordance with the first start pulse signal and the second start pulse signal, wherein the latch circuit is configured to be inputted with the second start pulse signal, the row selection pulse, a first pulse width control signal, and a second pulse width control signal, and wherein the gate signal line driver circuit is configured to output one of a writing signal and an erasing signal to the gate signal lines, in accordance with the second start pulse signal, the row selection pulse, the first pulse width control signal, and the second pulse width control signal.