Patent ID: 7687306

Claim:
A method for manufacturing a CMOS image sensor, comprising the steps of: forming a first mask over a semiconductor substrate including a gate electrode to expose a transistor region on a first side of the gate electrode and cover a photodiode region on a second side of the gate electrode; forming a first lightly doped drain in the transistor region with the first mask over the photodiode region, including a first dopant having a first conductivity type; removing the first mask; forming a second mask to expose the photodiode region and cover the transistor region; forming a first photodiode diffusion region substantially aligned with a gate sidewall on the second side of the gate electrode with the second mask over the transistor region, the first photodiode diffusion region including a second dopant having the first conductivity type; forming a second photodiode diffusion region substantially aligned with the gate sidewall on the second side of the gate electrode over or in the first photodiode diffusion region with the second mask over the transistor region, the second photodiode diffusion region including a third dopant having a second conductivity type; removing the second mask and forming insulating sidewalls on the first and second sides of the gate electrode; forming a third mask to cover the photodiode region and expose the transistor region; forming a source/drain diffusion region in the transistor region with the third mask over the photodiode region and the insulating sidewall on the second side of the gate electrode covering a portion of the first lightly doped drain, the source/drain diffusion region partially overlapping with the lightly doped drain and including a fourth dopant having the first conductivity type; removing the third mask; forming a fourth mask to expose the photodiode region and cover the transistor region; and forming a third photodiode diffusion region substantially aligned with an outer sidewall of the insulating sidewall on the second side of the gate electrode over or in the photodiode region, the insulating sidewall in the photodiode region covering a portion of the first and second photodiode diffusion regions, the third photodiode diffusion region partially overlapping the first photodiode diffusion region, and including a fifth dopant having the second conductivity type, wherein the third photodiode diffusion region has a higher dopant concentration than that of the second photodiode diffusion region.