Patent ID: 7250789

Claim:
A CMOS logic circuit, comprising: a plurality of logic gates, including: at least on NOR logic gate including p-channel and n-channel transistors; and at least on NAND logic gate including p-channel and n-channel transistors; wherein each individual one of the plurality of logic gates has at least two logic inputs, a logic output, an n-channel transistor enable clock input, and a p-channel transistor pre-charge clock input; wherein a pre-charge clock signal activates the p-channel transistor in each individual one of the plurality of logic gates to provide a high logic potential at the logic output in preparation for an enable clock signal; and wherein every p-channel transistor in the plurality of logic gates has a drain connected to the logic output in a pre-charged high logic state prior to the enable clock signal; wherein each of the at least two logic inputs has at least one transistor with a gate for receiving logic signals, and a drain connected to the logic output; wherein the n-channel transistor enable clock input for the at least one NOR logic gate includes a delayed enable clock signal coupled to a source region of transistors at the at least two logic inputs.