Patent ID: 7133942

Claim:
A communication parallel processing system comprising: an input bus; N task orientated processing devices, wherein N is greater than 1 and each of the task-oriented devices provides a particular function; M buffers connected to said input bus, wherein M is greater than 1, each one adaptable to operate in a plurality of different phases operatively coupled to the N task orientated processing devices; said phases including a Fast Write Phase, a Slow Read Phase, a Slow Write Phase, and a Fast Read Phase; and a Time Division Multiplex Control mechanism operatively connected to the M buffers and imposing respective ones of the different phases on said M buffers to deliver outputs from said buffers to an output bus in the order that inputs were outputted on the said input bus; wherein said each one of the M buffers further includes a slow write port receiving data if said each one of the M buffers is in the Slow Read Phase, a slow read port providing data if said each one of the M buffers is in the Slow Read Phase, a fast write port receiving data if said each one of the M buffers is in a Fast Write Phase and a Fast Read Phase providing data if said each one of the M buffers is in a Fast Read Phase.