Patent ID: 7542340

Claim:
An integrated circuit device comprising: a memory cell array including: a plurality of bit lines; a plurality of bit line segments, wherein at least two bit line segments are associated with each bit line and wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line; a plurality of word lines; a plurality of memory cells, wherein each memory cell stores at least two data states and includes a transistor, wherein the transistor includes: a first region connected to an associated bit line segment; a second region; a body region disposed between the first region and the second region; and a gate disposed over the body region and coupled to an associated word line; wherein: a first group of memory cells is coupled to a first bit line via a first bit line segment; a second group of memory cells is coupled to the first bit line via a second bit line segment; a third group of memory cells is coupled to a second bit line via a third bit line segment; and a fourth group of memory cells is coupled to the second bit line via a fourth bit line segment; first circuitry, coupled to the first and second bit lines, to sense the data state stored in the memory cells of the first, second, third and fourth groups of memory cells; and a plurality of isolation circuits, wherein each isolation circuit is associated with a bit line segment and wherein each isolation circuit is disposed between the associated bit line segment and the associated bit line thereof, wherein the isolation circuit responsively connects to or disconnects the associated bit line segment from the associated bit line, and wherein each isolation circuit includes: a first transistor comprising: (i) a first region connected to the associated bit line, (ii) a second region connected to the associated bit line segment, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal, and a second transistor comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.