Patent ID: 7618866

Claim:
A method of forming a semiconductor structure having a stressed device channel comprising: providing at least one field effect transistor having an extension spacer on a surface of a mesa portion of a semiconductor substrate, said semiconductor substrate having a recessed region at a footprint of the at least one field effect transistor; conformally growing a first epitaxial semiconductor layer on exposed surfaces of said semiconductor substrate in said recessed region and on an entirety of sidewalls of said mesa portion of the semiconductor substrate, said first epitaxial semiconductor layer having a lattice constant that is different from a lattice constant of said semiconductor substrate; forming a second epitaxial semiconductor layer on said first epitaxial semiconductor layer, wherein said second epitaxial semiconductor has the same lattice constant as the first epitaxial semiconductor layer and a higher dopant concentration than the first epitaxial semiconductor layer, in which the first epitaxial layer and the second epitaxial layer provide deep source and drain regions, wherein the deep source and drain regions are formed via in-situ doping during the forming of the first epitaxial layer and the second epitaxial layer, in which the second epitaxial semiconductor layer is directly present on the first epitaxial layer, and the second epitaxial layer has an upper surface that is coplanar with an upper surface of the mesa portion of the semiconductor substrate; and forming an extension region within upper portions of said the first and second epitaxial semiconductor layers.