Patent ID: 8427128

Claim:
A control circuit for reducing output ripple in a constant on-time switching regulator, the control circuit controlling a power stage to convert an input voltage to an output voltage and to provide an output current to a load, the control circuit comprising: a zero current detector (ZCD) detecting a zero current period wherein the output current is about zero, and generating a zero current period signal representing the zero current period; an on-time (TON) adjustment circuit receiving the zero current period signal to determine whether the zero current period is longer than a first threshold period, and generating a TON control signal accordingly; and a constant on-time (COT) generation circuit determining a TON of a square wave signal according to the TON control signal, the power stage being controlled according to the TON of the square wave signal, wherein when the zero current period is shorter than the first threshold period, the COT generation circuit generates the square wave signal with a longer TON, and when the zero current period is longer than the first threshold period, the COT generation circuit generates the square wave signal with a shorter TON whereby the power stage operates in a discontinuous conduction mode (DCM) according to the shorter TON.