Patent ID: 8760924

Claim:
A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a memory cell array including a plurality of memory cells stacked on the semiconductor substrate; and a control circuit configured to control a voltage supplied to the plurality of memory cells, each of the memory cells comprising: a first semiconductor layer extending in a perpendicular direction with respect to the semiconductor substrate and functioning as a body of the memory cell; a charge storage layer provided on a side surface of the first semiconductor layer; and a first conductive layer provided so as to sandwich the charge storage layer with the first semiconductor layer and functioning as a gate of the memory cell, the control circuit executing a first program operation that supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell, and then executing a second program operation that renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.