Patent ID: 6992354

Claim:
A device, comprising: an integrated circuit formed on a substrate and comprising a plurality of FETs wherein at least some of said plurality of FETs are finFETs each comprising: a) a fin having a source portion, a drain portion and a channel portion extending between said source portion and said drain portion, said fin having a base portion disposed on said substrate, each of said source portion and said drain portion having an upper surface, said fin having a length extending from, and including, said source portion and said drain portion and each of said source portion and said drain portion including an upper surface having a width; b) a first spacer formed adjacent said base portion; c) a gate located at said channel portion; d) a first reentrant corner between said upper surface of said source portion and said gate; e) a second reentrant corner between said upper surface of said drain portion and said gate; f) a second spacer proximate said first reentrant corner and having a length extending alone said gate substantially equal to said width of said source portion immediately adjacent said gate; and g) a third spacer proximate said second reentrant corner and having a length extending along said gate substantially equal to said width of said drain portion immediately adjacent said gate.