Patent ID: 7300811

Claim:
A manufacturing method of a TFT (thin film transistor) array, the method comprising: forming a first conductive material layer on a substrate; patterning the first conductive material layer for defining a scan line on the first layer and a plurality of discontinuous data lines on the first layer; deposing a gate insulating layer, an active layer and a doping layer on the first conductive material layer and the substrate; patterning the gate insulating layer, the active layer and the doping layer for defining an active region and a region of cross-interconnection; forming a second conductive material layer on the substrate; and patterning the second conductive material layer for defining a data line on the second layer and a plurality of discontinuous scan lines on the second layer, wherein the patterned doping layer is divided into a first doping region and a second doping region, the plurality of discontinuous scan lines on the second layer and the scan line on the first layer are fitting-contacted to each other to form a scan line structure, the plurality of discontinuous data lines on the first layer and the data line on the second layer are fitting-contacted to each other to form a data line structure, and the gate insulating layer, the active layer, the first doping region and the second doping region form a TFT structure.