Patent ID: 8476703

Claim:
A method for forming a three-dimensional semiconductor device, comprising: forming a first semiconductor device, the first semiconductor device having a first terminal on a terminal side of the first semiconductor device and a first metal substrate on a metal side of the first semiconductor device, the first terminal being electrically coupled with the first metal substrate, and the forming of the first semiconductor device including: forming a metal oxide semiconductor (MOS) device in and over a semiconductor substrate, the MOS device including the first terminal on a terminal side of the semiconductor substrate, forming a first recess in the terminal side of the semiconductor substrate; forming a first metal layer overlying, at least in part, the MOS device and the first recess, patterning the first metal layer to form at least a first electrode, a portion of the first electrode overlying the first recess, attaching a first carrier substrate to the terminal side of the MOS device, forming a second recess in a metal side of the semiconductor substrate, the second recess being substantially aligned with the first recess, and forming a second metal layer overlying, at least in part, the metal side of the semiconductor substrate, the second metal layer filling the second recess and forming the first metal substrate; forming a second semiconductor device, the second semiconductor device having a second terminal on a terminal side of the second semiconductor device; forming a patterned conductive layer, the patterned conductive layer including an interconnected conductive region; and bonding the patterned conductive layer with the first semiconductor device and the second semiconductor device, such that the patterned conductive layer is at least partially between the first semiconductor device and the second semiconductor device, and the conductive region is electrically coupled with the first terminal and coupled with the second terminal.