Patent ID: 6842052

Claim:
An asynchronous clock switching system comprising: two or-more asynchronous clock-signals; a detector for detecting a selected one of the two or more asynchronous clock signals, the detector including a detector first input, a detector second input, a detector third input, a detector first output, and a detector second output; the detector first input coupled to the two or more asynchronous clock signals; the detector second input coupled to the detector first output; a requestor, for sending request signals that request the selected one of the two or more asynchronous clock signals, the requestor including a requestor first input, a requestor second input, and requestor first output; the requestor first output, for sending selection signals, including a delay, coupled to the detector third input; control signals, coupled to the requestor second input, for indicating a requested asynchronous clock signal; a signal output, for outputting the selected asynchronous clock signal, the signal output including a signal output first input, and a signal output first output; the signal output first input coupled to the detector second output; and the signal output first output coupled to the requestor first input.