Patent ID: 7375025

Claim:
A method for forming a metal silicide layer in a semiconductor device comprising: forming a first gate structure including a first gate electrode and a first spacer on a first region of a substrate; forming a second gate structure including a second gate electrode and a second spacer on a second region of the substrate; partially removing the first and second spacers to different depths such that side portions of the first and second gate electrodes are exposed by different amounts in thickness; and forming a metal suicide layer on the first and second electrodes having the different exposed thicknesses, wherein the metal silicide layer formed on the second gate electrode has a second thickness that is different from a first thickness of the metal silicide layer formed on the first gate electrode, and wherein partially removing the first and second spacers comprises: removing partially and simultaneously the first and second spacers to expose upper side portions of the first and second electrodes; removing the exposed upper portion of the first gate electrode; and removing partially and simultaneously the first and second spacers to provide the first and second gate electrodes having the different exposed thicknesses, wherein the second thickness of the metal silicide layer formed on the second gate electrode is greater than the first thickness of the metal silicide layer formed on the first gate electrode.