Patent ID: 8097522

Claim:
A method of forming an isolation structure in a semiconductor substrate of a first conductivity type, the substrate having a top surface, the method comprising: implanting a dopant of a second conductivity type opposite to the first conductivity type to form a floor isolation region, the dopant being implanted with sufficient energy such that immediately following the implanting an upper junction of the floor isolation region is located below the top surface of the substrate; forming a mask layer over the top surface of the substrate; forming an opening in the mask layer; etching the substrate through the opening in the mask layer to form an annular trench in the substrate, a bottom of the annular trench being located in or below the floor isolation region; filling the annular trench with a dielectric material so as to form an isolated pocket of the substrate; implanting a dopant of a second conductivity type opposite to the first conductivity type to form a second floor isolation region, the dopant being implanted with sufficient energy such that an upper junction of the second floor isolation region is located below the top surface of the substrate; forming a second opening in the mask layer; etching the substrate through the second opening in the mask layer to form a second annular trench in the substrate, a bottom of the second annular trench being located in or below the second floor isolation region; filling the second annular trench with a dielectric material so as to form a second isolated pocket of the substrate; and implanting a dopant of the first conductivity type into the substrate with sufficient energy to form a submerged region of the first conductivity type between the first and second floor isolation regions, an upper boundary of the submerged region being located below the top surface of the substrate.