Patent ID: 8866521

Claim:
A voltage generation circuit of a semiconductor memory apparatus, comprising: a sensing unit configured to sense a voltage level of an output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; a first standby pumping unit configured to perform a pumping operation in response to the oscillator signal, and output a voltage generated by the pumping operation, to the output node; a second standby pumping unit configured to perform a pumping operation in response to the oscillator signal when a mode register set signal is enabled, and output a voltage generated by the pumping operation, to the output node; and an active pumping unit configured to perform a pumping operation in response to the oscillator signal when an active signal is enabled, and output a voltage generated by the pumping operation, to the output node, wherein the second standby pumping unit interrupts the pumping operation from a time when a power-up signal is enabled to a time when the mode register set signal is enabled, and performs the pumping operation in response to the oscillator signal when the mode register set signal is enabled.