Patent ID: 7298407

Claim:
A method for reducing shutter latency in an imager operating in accumulation mode, wherein the imager comprises an array of pixels arranged in rows and columns with two or more phases per pixel while maintaining low dark current in the imager and minimizing energy consumption, the method comprising the steps of: (a) transferring excess charge from a row of pixels by setting one vertical clocking voltage operatively connected to one phase of the pixels in a row to a high level when another vertical clocking voltage operatively connected to another phase of the pixels in a row is at a low level and shifting the high level to a low level while shifting the low level to a high level; (b) setting the vertical clocking voltages to a low level for a time duration selected to be between a minimum time duration that is greater than a time between row transfers during image readout and a maximum time duration of twice the time between row transfers during image readout; and (c) repeating steps (a) and (b) for a time necessary to readout all rows of pixels such that an exposure may be captured with substantially zero latency.