Patent ID: 6898770

Claim:
A method for improving a turnaround time for design verification of a process database representing a semiconductor design, comprising: (a) deriving a timing database and a physical verification database from the process database, each containing a power mesh description for the semiconductor device, a custom routing description for the semiconductor device and standard cell power routine description for the semiconductor device; (b) performing, using the timing database, one or more design changes and one or more timing verifications and corrections to generate a modified timing database by (b1) deleting the custom routing description, (b2) fixing the vower mesh description to pass verification, and (b3) adding a new custom routing description to pass verification; (c) initiating, using the process database, physical validation of the semiconductor design prior to completion of step (b) to generate a modified physical verification database; (d) merging the modified timing database with the modified physical verification database to form a modified process database; and (e) performing, using the modified process database, one or more design verification checks of the semiconductor design.