Patent ID: 7425852

Claim:
A phase-locked loop for frequency synthesis having a phase or phase frequency detector, a controllable oscillator, a loop filter, and a frequency divider, a. the phase-locked loop comprising a reference oscillator or being connectable to a reference oscillator, the reference oscillator being implemented to generate a reference clock signal and output it to a reference input of the phase or phase frequency detector, b. the controllable oscillator: (1) having a control input for a control signal and being implemented to generate a clock signal, (2) having a synthesis frequency adjustable by the control signal applied to the control input in operation, and output it to the frequency divider, c. the frequency divider being implemented: (1) to divide the clock signal output by the controllable oscillator by a divider value and thus generate a divider clock signal which has a frequency reduced by the divider value in relation to the synthesis frequency, and (2) to output the divider clock signal to a feedback input of the phase or phase frequency detector, d. the phase or phase frequency detector being implemented: (1) to compare the reference clock signal and the divider clock signal to one another and (2) to generate a comparison signal which contains information about the phase relation or the frequency relation or about the phase relation and the frequency relation of reference and divider clock signals, and (3) to output the comparison signal to the loop filter, e. the loop filter being implemented to generate a control signal, by filtering the comparison signal output by the phase or phase frequency detector, and output it to the controllable oscillator, characterized in that: A. the phase-locked loop has a memory for a control value, which is connectable to the control input of the controllable oscillator via a first switch, which is switchable as a function of a first switching signal, and is implemented to output a stored control value, and B. the frequency divider is connectable at its output via a second switch, which is switchable as a function of a second switching signal, to the reference oscillator.