Patent ID: 7084683

Claim:
A flip-flop comprising: an input stage having complementary data inputs and complementary output terminals coupled to a first and a second input terminal of an output stage, the output stage including a first transistor having a first current-handling terminal connected to a first output terminal of the flip-flop, a second current-handling terminal connected to a second output terminal of the flip-flop, and a first control terminal connected to a clock signal; a second transistor having a third current-handling terminal connected to the first output terminal of the flip-flop, a fourth current-handling terminal continuously connected to a first voltage supply terminal, and a second control terminal connected to the first input terminal; a third transistor having a fifth current-handling terminal connected to the first output terminal of the flip-flop, a sixth current-handling terminal connected to the first voltage supply terminal, and a third control terminal continuously connected to the second output terminal of the flip-flop; and a cross coupled circuit having a cross coupled transistor continuously connected to a second voltage supply terminal, wherein a gate of the cross coupled transistor is connected to the second output terminal of the flip-flop; and wherein the second transistor has a first threshold and the third transistor has a second threshold, the second threshold being lower than the first threshold.