Patent ID: 7045434

Claim:
A method for manufacturing a semiconductor device, the method comprising: forming a silicon oxide film on an upper surface of a semiconductor substrate; forming a silicon nitride film on the silicon oxide film; forming an element partitioning trench and a mask aligning trench in the semiconductor substrate; simultaneously depositing a silicon oxide insulation in the element partitioning trench and the mask aligning trench by a chemical vapor deposition process consisting of high density plasma chemical vapor deposition, wherein no other insulation layer has been deposited by a plasma process in the trenches prior to the silicon oxide insulation being deposited; applying a protective mask on the silicon oxide insulation deposited in the element partitioning trench to fully cover the element partitioning trench; etching the silicon oxide insulation deposited in the mask aligning trench to remove some of the silicon oxide insulation while the silicon oxide insulation deposited in the element partitioning trench is covered by the protective mask so that the silicon oxide insulation deposited in the mask aligning trench has an upper surface located lower than the upper surface of the semiconductor substrate; removing the protective mask; flattening an upper surface of the semiconductor device; and selectively removing the silicon nitride film by etching, wherein after said etching, an upper portion of the silicon oxide insulation deposited in the element partitioning trench projects above the upper surface of the silicon oxide film by a controlled height; removing the silicon oxide film by etching to define a mask aligning step between the upper surface of the silicon oxide insulation deposited in the mask aligning trench and the upper surface of the semiconductor substrate; aligning a mask for patterning a conductive film with the semiconductor substrate using the mask aligning step; and then patterning the conductive film, wherein a predetermined etched amount of said upper portion of the silicon oxide insulation is removed during a period from when the silicon oxide film is etched to when the conductive film is patterned, and wherein said controlled height of said upper portion of the silicon oxide insulation is predetermined so that said controlled height is equal to said predetermined etched amount.