Patent ID: 8381139

Claim:
A method of via patterning mask assignment for a via layer using double patterning technology, wherein vias of the via layer land on respective underlying metal structures, said method comprising: generating via mask-split-rule violation marks for vias of the via layer, wherein the via mask-split-rule violation marks connect vias that violate at least a via mask-split rule; determining, by a processor, if a via touches one of the via mask-split-rule violation marks, if the via does not touch one of the via mask-split-rule violation marks, assigning the via to one of two via masks which aligns with the underlying metal structure on which the via lands, if the via touches one of the via mask-split-rule violation marks, proceeding to determine if the via is an end via, if the via is an end via, assigning a first weight to the via, if the via is not an end via, assigning a second weight to the via, and assigning each via that touches one of the via mask-split-rule violation marks to one of the two via masks such that vias with the first weight are given higher priority in being assigned to the via masks aligning with the underlying metal structures that the vias land on.