Patent ID: 7045450

Claim:
A method of manufacturing a semiconductor device, the method comprising the steps of: i) forming gates having nitride hard mask on an upper surface of a semiconductor substrate; ii) forming junction areas on a surface of the semiconductor substrate between gates; iii) forming a first BPSG layer on a resultant structure of the semiconductor substrate such that the gates are covered with the first BPSG layer; iv) performing a first chemical mechanical polishing process with respect to the first BPSG layer by using acid slurry having a high polishing selectivity between an oxide layer and a nitride layer in such a manner that the nitride hard mask of each gate is exposed; v) forming a second BPSG layer on the first BPSG layer, which is polished through the chemical mechanical polishing process; vi) forming a landing plug contact, which simultaneously exposes surfaces of the junction areas formed between gates, by etching the second and first BPSG layers; vii) depositing a polysilicon layer on a resultant structure of the semiconductor substrate such that the landing plug contact is filled up with the polysilicon layer; and viii) performing a second chemical mechanical polishing process with respect to the polysilicon layer, the second BPSG layer and the nitride hard mask by using acid slurry in such a manner that landing plug polys make contact with gates while being spaced from the junction areas formed between the gates.