Patent ID: 7446012

Claim:
A manufacturing method of a lateral PNP (LPNP) transistor, wherein a N-type buried layer (buried N) is formed on a P-type substrate and is to be surrounded by a P-type buried layer (buried P); and forming a N-type epi layer and a N-type field implant layer sequentially on the surfaces of P-type substrate, N-type buried layer and P-type buried layer; and doping downward a deep N + -type sinker from the surface of N-type field implant layer on the up edge of buried layer, then opening the doping windows for LPNP areas and isolation area at shielding oxide layer grown on N-type field implant layer; and forming P − -type collector downward from the surface of the N-type epi layer and P − -type isolation area which surrounds N-type buried layer and downward extended to connect with P-type buried layer by P − implantation and drive-in process, at this time, the deep N + -type sinker will extend downward to connect with the edge of N-type buried layer by drive-in process; and the N-type base, which is surrounded by P − -type collector, is formed downward from the surface of the N-type epi layer by N implantation process, and the P + implantation into the needed area and drive-in to form P + collector and P + isolated area and P + emitter downward from N-type field implant layer, while do not surpass the P − -type collector, P − -type isolated area, and N-type base respectively; and the N + -type base area is formed on the deep N + -type sinker via N + implantation process; and the contact holes are formed at P + collector area, N + -type base area, and P + emitter area by photolithography and etching process; and finally forming metal electrodes of collector, base and emitter on said contact; wherein the doping windows of isolation/P − /N-type base/P + layers are defined on shielding oxide layer at the same time by a composite mask, and wherein the N-type base is formed to be sandwiched by the P + emitter and the N-type epi layer.