Patent ID: 8161450

Claim:
An integrated circuit (IC) comprising: an interconnect bus that includes a signal conductor; a plurality of non-volatile memory cells capable of storing first configuration information and second configuration information; a first general purpose input/output (GPIO) terminal that is couplable to the interconnect bus; a second general purpose input/output (GPIO) terminal that is couplable to the interconnect bus; a switching power converter that is couplable to the interconnect bus, wherein the IC is configurable such that control information can be supplied from a selected one of the first terminal and the second terminal, across the signal conductor of the interconnect bus, and to the switching power converter, wherein which one of the first and second terminals is coupled to supply the control information to the signal conductor of the interconnect bus is determined by the first configuration information stored in the plurality of non-volatile memory cells, and wherein whether the signal conductor of the interconnect bus is coupled to supply the control information to the switching power converter is determined by the second configuration information stored in the plurality of non-volatile memory cells; and a master tile comprising a bus portion, wherein the bus portion is part of the interconnect bus, and wherein the master tile is adapted to receive the first and second configuration information onto the IC such that the first and second configuration information is transferred across the interconnect bus and is then loaded into said non-volatile memory cells.