Patent ID: 8310612

Claim:
A thin film transistor liquid crystal display panel, comprising: a buffer layer formed on a substrate; a gate line formed on the buffer layer; a data line separated by the gate line; a first thin film transistor having a first semiconductor layer, a first gate electrode overlapping a channel area of the first semiconductor layer with a first insulating pattern therebetween, a first source electrode separated from the first gate electrode and directly connected with a source area of the first semiconductor layer, and a first drain electrode separated from the first gate electrode and directly connected with a drain area of the first semiconductor layer, wherein the source and drain areas are doped with the first impurity; a second thin film transistor having a second semiconductor layer doped with a second impurity, a second gate electrode overlapping the second semiconductor layer with a second insulating pattern therebetween, and a second source electrode and a second drain electrode separated from the second gate electrode and connected with the second semiconductor layer; a passivation film protecting the first and second thin film transistors; a first contact hole penetrating the passivation film and exposing the first drain electrode; a pixel electrode connected with the first drain electrode through the first contact hole; a storage line overlapping the pixel electrode with the passivation film therebetween to form a storage capacitor, wherein the storage line is parallel to the gate line and the data line is separated by the storage line; a plurality of second contact holes penetrating the passivation film such that parts of the data line separated by the gate line are exposed; a first contact electrode connecting the parts of the data line separated by the gate line through the second contact holes, wherein the gate line, the storage line, the first source electrode and the first drain electrode are formed of the same material on the buffer layer and are coplanar to each other; wherein the pixel electrode and the first contact electrode comprise a transparent conductive layer on the passivation film; wherein the first insulating pattern is formed only between the first gate electrode and the channel area of the first semiconductor layer; and wherein the second insulating pattern is formed only between the second gate electrode and a channel area of the second semiconductor layer and has same width as the second gate electrode.