Patent ID: 8035365

Claim:
A direct current (DC) converter, comprising: a PWM (Pulse Width Modulation) pulse generation unit which outputs a PWM pulse signal having a duty ratio controlled in accordance with an output voltage; a PFM (Pulse Frequency Modulation) pulse generation unit which outputs a PFM pulse signal including a pulse output interval controlled in accordance with the output voltage; a selection circuit which selects and outputs any one of the PWM pulse signal and the PFM pulse signal in accordance with a selection signal; a drive circuit unit which drives a load, and generates an output voltage on a basis of a signal outputted from the selection circuit; and a switching control unit which outputs the selection signal, wherein when the selection signal is in a second state which instructs to select the PFM pulse signal, the switching control unit detects a number of pulses of the PFM pulse signal within one measurement period that increases to equal or greater than a set value of a maximum number of pulses, and switches the selection signal to a first state which instructs to select the PWM pulse signal, wherein the switching control unit includes a counter counting a number of pulses of the PWM pulse signal within the one measurement period, and the counter switches the selection signal to the first state when the pulses of the PFM pulse signal, the number of which is equal to or greater than the set value of the maximum number of pulses, are inputted within the one measurement period, wherein the PFM pulse generation unit includes: a PFM reference clock generation unit which outputs a PFM reference clock signal; and a gating circuit which thins out the PFM reference clock signal in accordance with a value of the output voltage, and generates the PFM pulse signal, wherein the switching control unit includes a frequency-divided PFM reference clock signal, wherein the counter is reset in accordance with a logic level of the frequency-divided PFM reference clock signal; and wherein the one measurement period is set as a period from cancellation of the counter reset to a start of a next reset state of the counter.