Patent ID: 8817514

Claim:
A method of forming a memory having memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, comprising: providing a semi-conductor substrate; forming predetermined active elements and metal lines on the semi-conductor substrate; forming a multi-layer structure on top of the substrate, the multi-layer structure being repeated subsets of layers, each subset of layers comprising a layer for forming a sheet electrode, a dielectric layer and a sacrificial material; forming a 2-D array in the x-y plane of conductive pillars as bit line pillars elongated in the z-direction through the plurality of planes, each said conductive pillars being formed with a cladding layer of R/W material for of the memory elements, said layer of R/W material for the memory elements being in electrical contact with the layer of sheet electrode when said conductive pillars in the x-z plane and the layer of sheet electrode in the x-y plane intersect at each subset of layers; exposing a cross section of the multi-layer structure by opening a plurality of trenches in the x-z plane in the multi-layer structure; etching recesses in the sacrificial layer of the multi-layers to within a predetermined offset from the conductive pillars from each of the trenches, thereby exposing a portion of the layer for forming the sheet electrode; and forming the word lines on the multiple planes in a lateral direction in the recesses, said word lines being formed over the exposed portion of the layer for forming the sheet electrode and making electrical contact therewith.