Patent ID: 7572727

Claim:
A contact formation process comprising; preparing a silicon wafer substrate; forming a gate region; creating source and drain regions; depositing a multiple etch stop insulation layer, wherein depositing said multiple etch stop insulation layer comprises: depositing a first etch stop layer directly on said silicon wafer substrate in a contact region; depositing a first sub interlevel dielectric layer over said first etch stop layer; depositing a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer; and depositing a second sub interlevel dielectric layer over said second etch stop layer; forming said contact region in said multiple etch stop insulation layer by selectively removing some of said multiple etch stop insulation layer and forming a sub spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and depositing electrical conducting material in said contact region.