Patent ID: 7877721

Claim:
A method of implementing a user's logic design in a programmed FPGA and a functionally equivalent structured ASIC comprising: synthesizing the user's logic design for implementation in the FPGA; performing a first place and route operation on a synthesis that results from the synthesizing to produce a first further synthesis adapted for determining how the FPGA should be programmed; converting a synthesis that results from synthesizing the user's logic design for implementation in the FPGA to a modified synthesis that is suitable for structured ASIC implementation; performing a second place and route operation on the modified synthesis to produce a second further synthesis adapted for placement on a structured ASIC; and converting the second further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC, wherein the performing a first place and route operation includes changing an aspect of what is specified by the user's logic design, and wherein the method further comprises: modifying data for the user's logic design with information about a change that results from the changing.