Patent ID: 7649774

Claim:
A memory system comprising: a memory unit which includes a plurality of first blocks each having a first block size, each of the first blocks storing data of a plurality of second blocks each having a second block size which is smaller than the first block size; and a control unit which writes the data of the second block in the first block, the control unit being configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block, wherein when the control unit writes the second block in the first block, if an address of the second block is not an address that is to be written in the same first block as the second block that is already written in the first block, the control unit writes data of the second block in another said first block.