Patent ID: 8168489

Claim:
A method of manufacturing a semiconductor structure, comprising the steps of: forming a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate; forming a pFET stack in the pFET channel and an nFET stack in the nFET channel; after the pFET stack is formed, providing a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel; and after the nFET stack is formed, providing a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel, wherein the first layer of material is formed by placing a mask over the nFET stack, etching the regions of the pFET, and selectively growing the first layer of material within the source/drain regions of the pFET; and wherein the second layer of material is formed by placing a mask over the pFET stack, etching regions of the nFET, and selectively growing the second layer of material within the source/drain regions of the nFET.