Patent ID: 8023363

Claim:
A time-to-digital converter apparatus, comprising: a delay phase-locked loop, having an input terminal and an output terminal, wherein the input terminal receives an input clock signal and the output terminal transmits a first counting signal; a subtracter, having an output terminal, a first input terminal and a second input terminal, wherein the first input terminal receives the first counting signal, the second input terminal receives a second counting signal, the output terminal produces a third counting signal and the third counting signal is equal to the difference between the first counting signal and the second counting signal; a multi-phase detector, coupled to the delay phase-locked loop to receive the first counting signal; and a Vernier detector, coupled to the delay phase-locked loop, the subtracter and the multi-phase detector, the Vernier detector receives the first and the third counting signals and a plurality of outputs of the multi-phase detector, the Vernier detector generates a digital output signal according to the first and the third counting signals and the outputs of the multi-phase detector.