Patent ID: 8557635

Claim:
A method of manufacturing a stacked semiconductor device, comprising: preparing a first semiconductor wafer including plural first chip areas sectioned by first dicing grooves and each having first electrode pads formed at a circuit surface, and first photosensitive surface protection and adhesive layers provided at each of the circuit surfaces of the plural first chip areas to expose the first electrode pads; and stacking a second semiconductor wafer including plural second chip areas sectioned by second dicing grooves and each having second electrode pads formed at a circuit surface, and second photosensitive surface protection and adhesive layers provided at each of the circuit surfaces of the plural second chip areas to expose the second electrode pads, with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers while facing a non-circuit surface of the first semiconductor wafer and the circuit surface of the second semiconductor wafer to form plural chip stacked bodies of the first chip areas and the second chip areas, wherein the first chip area and the second chip area are stacked in a staircase pattern to expose the second electrode pads.