Patent ID: 8741773

Claim:
A method comprising: depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein said FET is a 45 nm-node FET and the first metal layer is deposited using a first nickel target material comprising nickel and platinum with the content of platinum at 10 percent measured in atom, and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering said FET to form a platinum-containing nickel-silicide layer, at a top surface of said at least one of said gate, source, and drain regions, having a platinum concentration level that is higher near a bottom surface than near a top surface of said nickel-silicide layer and is lower in a middle portion of said nickel-silicide layer than near said top surface of said nickel-silicide layer.