Patent ID: 7660967

Claim:
A computer system comprising: a memory having a plurality of addressable storage locations for storing data-elements, and a processor responsive to vector defining instructions to issue successive scalar processing instructions in an issue order to execute functions on input data-elements inputted from memory in a vector order to be operands to generate result data-elements arranged in the vector order for storage into memory according to the issue order, the processor comprising: a plurality of architectural registers, at least two of the architectural registers having input-vector capability to receive input data-elements arranged in vector order from the memory and at least one architectural register having output-vector capability to write result data-elements to the memory, each of the architectural registers being operable to receive result data-elements for use as data-elements as operands by a subsequent processing instruction; a plurality of functional units coupled to the architectural registers and responsive to processing instructions for concurrent pipelined execution of selected functions on data-elements as operands to generate result data-elements, at least some of the functional units requiring different periods of execution; a plurality of result registers, each result register being coupled to a respective architectural register and to the plurality of functional units to receive result data-elements from a selected functional unit and to send data-elements as operands to selected functional units; and issue-order logic responsive to the issuance of successive processing instructions to identify whether a result data-element in a result register is a result of a processing instruction issued earlier or later than a processing instruction that resulted in a result data-element in the respective architectural register, the result register being responsive to the identification from the issue-order logic to selectively transfer a result data-element to a respective architectural register or the memory, the respective architectural register being responsive to the identification from the issue-order logic to selectively transfer a result data-element to memory, and the result registers and respective architectural register being responsive to the identification from the issue-order logic to transfer a result data element required by a respective functional unit from the one of the result register and respective architectural register containing the required result data-element.