Patent ID: 8065575

Claim:
A method for implementing isolation of very-large-scale integration (VLSI) AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns comprising the steps of: using a voltage and frequency timing control and determining a passing operating region and a failing operating region for the device under test; applying an ABIST test pattern to the device under test and applying multiple ABIST array algorithms and varying voltage and frequency timing parameters in the passing operating region for the device under test and unloading scan chain data; applying the ABIST test pattern to the device under test and applying multiple ABIST array algorithms and varying voltage and frequency timing parameters in the failing operating region for the device under test and unloading scan chain data; comparing the unload data from the passing operating region and the failing operating region; identifying each latch having different results as a potential AC defective latch; and sending the identified potential AC defective latches to a Physical Failure Analysis system.