Patent ID: 8022520

Claim:
A system for hermetically sealing devices, the system comprising: a substrate, the substrate comprising a plurality of individual chips and CMOS circuitry, wherein each of the chips includes a plurality of devices; wherein each of the chips are arranged in a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration; a transparent member of a predetermined thickness, the transparent member configured to include a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array, and wherein each of the recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness; wherein the substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips, whereupon the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions; and wherein each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions; and wherein each of the chips comprises an interconnect region, the interconnect region being outside of the recessed region.