Patent ID: 7734860

Claim:
A signal processor which includes a first operation processor and a second operation processor sharing an external memory via a bus, the signal processor comprising: an access time period setting section which requests a bus release to the second operation processor and sets an access time period by occupying the bus released from the second operation processor according to the request for every sampling period of the first operation processor; wherein the first operation processor executes read/write processing in relation to the external memory during the access time period set by the access time period setting section for every sampling period; and wherein the access time period setting section comprises: an access time period start direction section which generates a request signal requesting bus release and outputs the request signal to the second operation processor every time that a given time elapses from a start of the sampling period of the first operation processor, and which generates a start signal representing a start of the access time period and outputs the start signal to the first operation processor after waiting a given time from when the request signal was generated; and an access time period end direction section which ends the access time period by directing the access time period start direction section to stop the request signal and the start signal, in accordance with a completion signal generated when the first operation processor completes accessing the external memory.