Patent ID: 8742490

Claim:
A semiconductor device, comprising: a lead frame, comprising a first plate and a second plate, wherein the first and the second plates are electrically isolated from each other; a first vertical power transistor die comprising a first vertical power transistor having a first source electrode, a first drain electrode, and a first gate electrode, the first vertical power transistor die being attached to the lead frame with the first source electrode being coupled to the first plate of the lead frame via flip-chip bumps and the first gate electrode being coupled to the second plate of the lead frame via flip-chip bumps; and a second vertical power transistor die comprising a second vertical power transistor having a second source electrode, a second drain electrode and a second gate electrode, the second vertical power transistor die being stacked on the first vertical power transistor die with the second source electrode coupled to the first drain electrode via flip-chip bumps; wherein the first vertical power transistor comprises a first substrate having a top surface and a bottom surface opposite to the top surface, and a first epitaxial layer having a top surface in contact with the bottom surface of the first substrate and a bottom surface opposite to the top surface of the first epitaxial layer, wherein the first substrate functions as a drain of the first vertical power transistor, and wherein the first drain electrode is on the top surface of the first substrate, and the first source electrode and the first gate electrode are on the bottom surface of the first epitaxial layer; and wherein the second vertical power transistor comprises a second substrate having a top surface and a bottom surface opposite to the top surface, and a second epitaxial layer having a top surface in contact with the bottom surface of the second substrate and a bottom surface opposite to the top surface of the second epitaxial layer, wherein the second substrate functions as a drain of the second vertical power transistor, and wherein the second drain electrode is on the top surface of the second substrate, and the second source electrode and the second gate electrode are on the bottom surface of the second epitaxial layer; and wherein the first vertical power transistor die further comprises a contact plate on the top surface of the first substrate, wherein the contact plate is electrically isolated from the first drain electrode and from the first substrate, and the contact plate extends laterally outboard the perimeter of the second vertical power transistor and is coupled to a lead of a plurality of leads by a bond wire, and wherein the second gate electrode of the second vertical power transistor is coupled to the contact plate of the first vertical power transistor die via flip-chip bumps.