Patent ID: 8626814

Claim:
A computer system comprising: a processor including: an instruction cache to store instructions; an instruction pointer register to store an address of an instruction to be executed; a register file including a plurality of registers operable to store floating point data and packed data in a single register, the packed data including a first packed data having a first plurality of data elements and a second packed data including a second plurality of data elements, each of the first and second plurality of data elements including two 32-bit data elements, four 16-bit data elements, and eight 8-bit data elements; a decoder coupled to the instruction pointer register and the instruction cache, the decoder to decode: a packed multiply-add instruction to perform: a multiply operation to multiply each of the first plurality of data elements with a corresponding one of the second plurality of data elements to generate respective products therefrom; an add operation to sum products of corresponding data elements of the first and second packed data to generate packed results therefrom; and the packed multiply-add instruction further specifying a size of the plurality of data elements; and a packed load instruction to perform a load operation to load packed data from a data cache into a packed register; a packed add instruction to perform an add operation; and a packed subtract instruction to perform a subtract operation; and a packed shift instruction to perform a shift operation; and an execution unit coupled to the register file and the decoder, the execution unit to: execute the multiply-add operation on the data elements independently responsive to the packed multiply-add instruction; execute the load operation responsive to the load instruction; execute the add operation responsive to the add instruction; execute the subtract operation responsive to the subtract instruction; and execute the shift operation responsive to the shift instruction; and a bus coupled to the processor and adapted to be coupled to a device for sound recording and/or playback; a ROM coupled to the bus to store instructions for the processor; a RAM coupled to the bus; and a video digitizing device coupled to the bus; the computer system to be coupled to a user input device and a display device, and further to be a terminal is a network and to support 2D/3D graphics.