Patent ID: 8724371

Claim:
A semiconductor memory device, comprising: a plurality of parallel word lines; a plurality of parallel bit lines formed crossing said plurality of word lines; a plurality of memory cells arranged at intersections of said word lines and said bit lines, each memory cell having one end connected to one of said plurality of word lines and the other end connected to one of said plurality of bit lines; and a control circuit operative to perform a read operation and a write operation, wherein said control circuit is configured to read out data from one memory cell of said memory cells, if said data read out is a first level, said control circuit applies a first voltage to one bit line of said plurality of parallel bit lines, if said data read out is a second level, said control circuit applies a second voltage generated based on a physical address of said memory cell to said bit line, said control circuit has a column control circuit and a word line drive circuit, said word line drive circuit is configured to apply a third voltage to one word line of said plurality of parallel word lines, and said second voltage is lower than said third voltage.