Patent ID: 7272059

Claim:
A sensing circuit for a semiconductor memory, comprising: a circuit branch intended to be electrically coupled to a memory bit line, said memory bit line having connected thereto a memory cell to be sensed; a bit line precharge circuit, for precharging the memory bit line coupled to the circuit branch to a predetermined bit line potential in a precharge phase of a memory cell sensing operation, and an evaluation circuit for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation, said electric quantity being indicative of an information content of the memory cell, wherein the bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential; at least said bit line precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase, and a same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.