Patent ID: 7650255

Claim:
A method of multi-site testing a batch of semiconductor units using a multi-site automated tester, said tester comprising a handler coupled to a contactor comprising a first plurality of contact sites, comprising the steps of: (a) loading a first plurality of said units into said first plurality of contact sites; (b) simultaneously testing said first plurality of units using a test program to determine bin information for each of said first plurality of units, said bin information defining each of said first plurality units being a passed unit or a reject unit; (c) offloading said passed units from respective contact sites of said first plurality of contact sites to create vacant contact sites while keeping said reject units at respective contact sites of said first plurality of contact sites; (d) loading untested units from said batch to fill said vacant contact sites, and (e) simultaneously retesting said reject units and testing said untested units using said test program.