Patent ID: 7613903

Claim:
A data processing device with an instruction translator comprising: a processor core; and a memory interface portion arranged between said processor core and an external memory mapped into a predetermined external memory space, said memory interface portion including a fetch circuit for receiving an address value for access to said external memory space from said processor core, and fetching information at said address in said external memory, said information being an instruction nonnative to said processor, an instruction native to said processor or data to be processed; a translator for translating the instruction nonnative to said processor core fetched by said fetch circuit from said external memory into the native instruction; and a select circuit for selectively applying the information read from said external memory space and the instruction prepared by translating the instruction read from said external memory space by said translator to said processor core depending on whether the address value for the access from said processor core to said external memory space is in a predetermined region or not, wherein a bus width of an instruction bus in said processor core is different from a bus width of a data bus of said external memory; and said select circuit includes: a bus width changing circuit having an input connected to said external memory and an output of a same width as the bus width of the instruction bus of said processor for performing conversion between the bus width of the data bus of said external memory and the bus width of the instruction bus in said processor, and outputting a result, and a multiplexer having inputs connected to the outputs of said bus width changing circuit and said translator, respectively, and an output connected to said instruction bus of said processor core for selectively applying to said processor core an instruction output from said bus width changing circuit and an instruction output from said translator, depending on whether the address value for the access from said processor core to said external memory space is within a predetermined region or not.