Patent ID: 8217703

Claim:
A level shifter, comprising: an input for receiving an input signal in a first voltage domain and an output for providing an output signal in a second voltage domain; a first NFET, wherein a gate of the first NFET receives the input signal and a source of the first NFET is coupled to Vss voltage; a second NFET, wherein a gate of the second NFET receives a secondary control signal and a source of the second NFET is coupled to Vss voltage; a third NFET, wherein a gate of the third NFET is coupled to a drain of the first NFET, a source of the third NFET is coupled to Vss voltage, and a drain of the third NFET is coupled to the output; a fourth NFET, wherein a source of the fourth NFET is coupled to a drain of the second NFET; a first PFET, wherein a source of the first PFET is coupled to Vdd voltage and a drain of the first PFET is coupled to a drain of the first NFET and the gate of the third NFET; a second PFET, wherein a source of the second PFET is coupled to Vdd voltage, a gate of the second PFET is coupled to at least one of (a) the output and (b) the gate of the fourth NFET, and a drain of the second PFET is coupled to a gate of the first PFET; and a third PFET, wherein a source of the third PFET is coupled to Vdd voltage, a gate of the third PFET is coupled to a drain of the first NFET and the gate of the third NFET, and a drain of the third PFET is coupled to the output.