Patent ID: 8633589

Claim:
A structure comprising an integrated circuit comprising: a semiconductor substrate; a first conductive feature overlying the semiconductor substrate; one or more second conductive features overlying the semiconductor substrate; one or more first dielectric trenches completely laterally surrounding the second conductive features and separating the second conductive features from the first conductive feature; wherein the first conductive feature completely laterally surrounds the first dielectric trenches; wherein the integrated circuit further comprises: a third conductive feature overlying the first and second conductive features and physically contacting each second conductive feature; one or more fourth conductive features overlying and physically contacting the first conductive feature; one or more second dielectric trenches completely laterally surrounding the fourth conductive features and separating the fourth conductive features from the third conductive feature, wherein the third conductive feature completely laterally surrounds the second dielectric trenches; third dielectric overlying the first conductive feature and separating the first conductive feature from the third conductive feature, wherein the third dielectric is less than 1 μm thick, and the third dielectric comprises a dielectric material not present in the one or more first dielectric trenches; wherein the integrated circuit comprises a plurality of conductive paths each of which passes through the first and third conductive features down into the semiconductor substrate; wherein each conductive path is associated with one or more insulating features, and is insulated from one or both of the first and third conductive features by the associated one or more insulating features; wherein the conductive paths comprise the second and fourth conductive features, and wherein the insulating features associated with the conductive paths comprise the first and second dielectric trenches; wherein both of conditions (A) and (B) are true, wherein the conditions (A) and (B) are as follows: (A) the first conductive feature covers a whole area of the semiconductor substrate except for intersection with each conductive path insulated from the first conductive feature and with the one or more insulating features insulating, from the first conductive feature, each conductive path insulated from the first conductive feature; (B) the third conductive feature covers the whole area of the semiconductor substrate except for intersection with each conductive path insulated from the third conductive feature and with the one or more insulating features insulating, from the third conductive feature, each conductive path insulated from the third conductive feature.