Patent ID: 8028190

Claim:
A computer system comprising: a processor which performs data processing; an input and output bus to which at least one input and output device is connected; and a bus control device which is intervened between said processor and said input and output bus, and performs control of the operation of said input and output bus; wherein said bus control device includes: a reset control unit which resets said input and output bus in response to receipt of reset instruction; a reset inhibition unit which inhibits a reset of said input and output bus triggered by a fault occurrence in said input and output bus; a log collection unit which collects log information of an input and output device connected to a fault occurrence section in said input and output bus triggered by the fault occurrence in said input and output bus, the log information including internal register information of said bus control device and a hold value of the input and output device; and an input and output interface which transfers the log information collected by said log collection unit to said processor; wherein said reset inhibition unit cancels inhibition of the reset after the collection of the log information by said log collection unit has been completed.