Patent ID: 8173524

Claim:
A method comprising: forming at least two gate stacks on a silicon substrate; forming sidewall spacers on sides of said gate stacks; patterning a recess in said silicon substrate between adjacent ones of said gate stacks; providing an insulating liner in a bottom of said recess; and epitaxially growing material from sidewalls of said recess to fill said recess with an epitaxial material, said providing of said insulating liner comprising any one of the following: patterning said recess through said silicon substrate into an underlying insulator layer such that said bottom of said recess comprises said insulator layer; and lining said sidewalls and said bottom of said recess with said insulating liner such that a horizontal portion of said insulating liner on said bottom surface is relatively thin compared to vertical portions on said sidewalls; and isotropically etching said insulating liner until said vertical portions are removed such that said horizontal portion remains.