Patent ID: 7768070

Claim:
A semiconductor device comprising: a channel pattern protruded from a substrate and having a pair of first sidewalls facing each other and a pair of second sidewalls facing each other; a separated channel pattern vertically separated from the protruded channel pattern and having a pair of third sidewalls and a pair of fourth sidewalls, which are aligned with the first sidewalls and the second sidewalls, respectively; a pair of in-situ doped epitaxial patterns respectively formed on the first sidewalls, the in-situ epitaxial pattern extended to be formed on the third sidewall; a pair of conductive patterns, each of the pair respectively formed on each sidewall of the pair of the in-situ doped epitaxial patterns opposite the protruded and separated channel patterns; a gate electrode crossing the protruded and separated channel patterns; and a gate insulating layer interposed between the gate electrode and the protruded channel pattern, and between the gate electrode and the separated channel pattern.