Patent ID: 7652647

Claim:
An image display device in which a plurality of pixel circuits each comprising a capacitor, a first transistor, a second transistor, a third transistor and an EL element are arranged in a matrix form over a substrate, further comprising: a scanning circuit for controlling the operation of said plurality of pixel circuits; a plurality of scanning wirings for conveying signals of said scanning circuit to said plurality of pixel circuits; a plurality of first wirings and a plurality of second wirings for supplying image signal voltages and power voltages to said plurality of pixel circuits, arranged in parallel to each other and crossing said scanning wirings; a drive circuit for supplying image signal voltages to said first wirings and said second wirings, and selection switch circuits, wherein: a gate of the first transistor in the pixel circuit on an odd row of the matrix is connected to one of the first wirings, one end of the EL element in the pixel circuit on the odd row of the matrix is connected to one of the second wirings through source-drain paths of the first transistor and the second transistor, the other end of the EL element in the pixel circuit on the odd row of the matrix is connected to a common electrode, one end of EL element in the pixel circuit on an even row of the matrix is connected to one of the first wirings through source-drain paths of the first transistor and the second transistor, the other end of the EL element in the pixel circuit on the even row of the matrix is connected to the common electrode, a source-drain path of the third transistor is connected between the gate of the first transistor and the drain of the first transistor, the image signal voltage is supplied to the first wiring and held in the capacitor of the pixel circuit on the odd row of the matrix, and the power voltage is supplied to the second wiring through one of the selection switch circuits during a first write time, the image signal voltage is supplied to the second wiring and held in the capacitor of the pixel circuit on the even row of the matrix, and the power voltage is supplied to the first wiring though one of the selection switch circuits during a second write time, and the power voltages are supplied to the first wiring and the second wiring and the second transistors are on in the lit mode.