Patent ID: 7885138

Claim:
A design structure embodied in a machine-readable medium used in a design process, the design structure comprising: an array of dual-port memory cells arranged in rows and columns, each cell being connected to a read word line and at least one read bit line and a write word line and at least one write bit line; a read circuit connected to said at least one read bit line and a driver circuit connected to said at least one write bit line; in which said at least one read bit line comprises two read bit lines disposed along columns in at least two sections of said memory array, said read lines in said at least two sections having opposite senses of reception of electromagnetic radiation, whereby said read circuit receives common mode noise from said at least one write bit line; and said at least one write bit line comprises two write bit lines disposed in at least two sections of said memory array, said at least two sections having opposite senses of transmission of electric current, whereby said read circuit receives a reduced differential mode noise from said write bit line.