Patent ID: 7288826

Claim:
A semiconductor integrated circuit device comprising: a first conductivity type semiconductor substrate having a top surface and a bottom surface, said first conductivity type semiconductor substrate being connected to a first power supply; a second conductivity type semiconductor layer having a top surface and a bottom surface, said second conductivity type semiconductor layer being provided on said top surface of said first conductivity type semiconductor substrate, said second conductivity type semiconductor layer being connected to a second power supply, said bottom surface of said second conductivity type semiconductor layer contacting with said top surface of said first conductivity type semiconductor substrate; a device forming portion including a first conductivity type well region and a second conductivity type well region, said device forming portion having a top surface and a bottom surface, said bottom surface of said device forming portion contacting with said top surface of said second conductivity type semiconductor layer, said top surface of said second conductivity type semiconductor layer being a substantially flat surface, said first conductivity type well region and said second conductivity type well region being provided on said top surface of said second conductivity type semiconductor layer; and a decoupling capacitor formed at an interface between said top surface of said first conductivity type semiconductor substrate and said bottom surface of said second conductivity type semiconductor layer.