Patent ID: 7120076

Claim:
A semiconductor memory device comprising: a plurality of bit line pairs each having first and second bit lines arranged in a first direction; a cell array having a plurality of SRAM cells each of which is connected between the first and second bit lines of a corresponding bit line pair via first and second storage nodes, respectively; a plurality of word lines arranged in a second direction crossing the first direction; and a data write circuit which, in the write mode, writes data into an SRAM cell selected by a word line via the first and second bit lines and, in the read mode, rewrites data read onto the first bit line from an SRAM cell selected by a word line onto a first writing bit line; wherein the write circuit includes a rewrite circuit which, when data corresponding to a precharge potential is read from the first bit line in the read mode, recharges the first bit line to the precharge potential on the basis of the read data.