Patent ID: 8753944

Claim:
A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor, comprising: providing a substrate having a substrate surface doped with a second dopant type, a gate stack over said substrate surface, and a masking pattern on said substrate surface which together with said gate stack exposes a portion of said substrate surface for ion implantation; implanting a first pocket implant using said second dopant type with said masking pattern on said substrate surface, implanting at least one retrograde gate edge diode leakage (GDL) reduction pocket implant using a first dopant type with said masking pattern on said substrate surface, and annealing said first pocket implant and said retrograde GDL reduction pocket implant, wherein after said annealing said first pocket implant provides first pocket regions and said retrograde GDL reduction pocket implant provides an overlap with said first pocket regions to form a first counterdoped pocket portion within said first pocket regions.