Patent ID: 7517763

Claim:
A method of fabricating a semiconductor device comprising: providing a semiconductor substrate having a fuse area and a capacitor area; forming a fuse and a lower plate on the fuse area and the capacitor area respectively, the fuse and the lower plate being separated by an interlayer insulating layer; sequentially forming a capping layer and a passivation layer on the semiconductor substrate, the fuse and the lower plate; patterning the passivation layer to form a fuse window that exposes the capping layer and a capacitor hole that exposes the capping layer, on the fuse area and the capacitor area respectively, the fuse window crossing over the fuse, and the capacitor hole being located above the lower plate; forming an upper conductive layer on the passivation layer and in the fuse window and the capacitor hole; and patterning the upper conductive layer to concurrently form an upper plate located above the lower plate and remove the upper conductive layer formed in the fuse window.