Patent ID: 6967516

Claim:
A semiconductor testing apparatus for testing a semiconductor device, comprising: a pattern generator for generating a test pattern input to a semiconductor device; a formatted test pattern generator that has: a plurality of referential delay units having different numbers of first variable delay elements, the delay amount of which changes based on a control signal; a delay compensation unit which generates each of a plurality of said control signals provided to said first variable delay elements according to a number of said first variable delay elements; and a delay unit which generates a delay clock having a delay amount according to an operation characteristic of said semiconductor device by controlling a plurality of second variable delay elements having a same characteristic with that of said first variable delay elements by said plurality of control signals; and the formatted test pattern generator formats said test pattern based on said delay clock and generates a formatted test pattern; a device contact unit, on which said semiconductor device is installed, for inputting said formatted test pattern to said semiconductor device; and a comparator which judges the quality of said semiconductor device based on an output signal output from said semiconductor device, to which said formatted test pattern is input.