Patent ID: 8228115

Claim:
A biasing circuit of an integrated circuit, comprising: a well of the integrated circuit; and a plurality of transistors disposed in the well and coupling the well to three signals providing corresponding voltages, the plurality of transistors including, for each of the three signals: a respective field-effect transistor coupled between the well and the signal through source and drain electrodes of the respective transistor, a gate electrode and a base electrode of the respective field-effect transistor coupled to the well; and a respective pair of field-effect transistors coupled in series between the well and the signal through source and drain electrodes of the respective pair of field-effect transistors, the two of the three signals other than the signal being coupled to a gate electrode of respective ones of the field-effect transistors in the respective pair; and wherein the transistors bias the well to an extreme one of the corresponding voltages of the three signals.