Patent ID: 7262462

Claim:
A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET), comprising: first and second vertical semiconductor layers disposed between a pair of parallel shallow trench isolation layers on a substrate, wherein: a first source region, a first drain region and a first channel region are formed in the first vertical semiconductor layer, and a second source region, a second drain region and a second channel region are formed in the second vertical semiconductor layer, the second source region facing the first source region, the second drain region facing the first drain region and the second channel region facing the first channel region; a gate oxide on the first and second channel regions; a first gate electrode on the gate oxide between the first channel region and the second channel region so as to enable conduction between the first source region and the first drain region and between the second source region and the second drain region concurrently; and a bottom channel region between the first and second vertical semiconductor layers, wherein the bottom channel region, the first channel region and the second channel region are each doped with an impurity of a first type, the bottom channel region being more heavily doped than the first and second channel regions.