Patent ID: 8680901

Claim:
An integrated circuit comprising: a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level; a pulse generation circuit coupled with the power supply sense circuit, the pulse generation circuit configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal; and a reset generation circuit coupled with the pulse generation circuit so as to be positioned to receive the POR pulse, the reset generation circuit configured to generate a reset pulse based on the POR pulse and at least one control signal, wherein the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit; wherein the pulse generation circuit comprises: one or more delay blocks connected in a serial configuration for generating the POR pulse of the threshold duration, each delay block comprising: an inverter configured by a NMOS transistor and a PMOS transistor, the inverter configured to receive an input signal and provide an inverted input signal at an output terminal of the inverter; a MOS based resistor having a first node and a second node, the first node coupled with the output terminal of the inverter to receive the inverted input signal, and pass the inverted input signal at the second node; an amplifier circuit comprising an inverting voltage amplifier and a miller capacitor coupled between an input node and an output node of the inverting voltage amplifier, wherein discharging and charging of an equivalent capacitor at the input node of the inverting voltage amplifier is configured to generate a pulse of a pre-determined width at the output node of the inverting voltage amplifier; and a Schmitt trigger buffer coupled with the output node of the inverting voltage amplifier, configured to receive the pulse of pre-determined width and provide a portion of the POR pulse at an output node of the Schmitt trigger buffer, wherein the input signal received by the inverter is the sense signal for the first delay block of the serial configuration of pulse generation circuit and the input signal is an output of the Schmitt trigger buffer of a preceding delay block in the serial configuration for each of the remaining delay blocks of the serial configuration, and wherein the one or more delay blocks are configured to generate the POR pulse of the threshold duration.