Patent ID: 8436468

Claim:
A semiconductor device having a semiconductor chip, comprising: a silicon substrate provided with first and second through electrodes; a top first interlayer insulating film on a first surface of said substrate; a first connection terminal connected to said first through electrode and disposed on within a top surface of the first interlayer insulating film on said first surface, said first connection terminal extending into said first interlayer insulating film with a lower surface located below the top surface of the first interlayer insulating film and an upper surface extending above an uppermost surface of said first interlayer insulating film; and a second connection terminal connected to said second through electrode and disposed on a top surface of the first interlayer insulating film on said first surface, the second through electrode and the second connection terminal being connected to each other by a wiring, a length of one side of the second connection terminal being longer than a width of the wiring, said second connection terminal extending into said first interlayer insulating film with a lower surface located below the top surface of the first interlayer insulating film and an upper surface extending above an uppermost surface of said first interlayer insulating film, a first interconnect in said first interlayer insulating film connecting said first connection terminal to said first through electrode; and a second interconnect in said first interlayer insulating film connecting said second connection terminal to said second through electrode, wherein, said first connection terminal is disposed at a position overlapping said first through electrode in a plan view, said second connection terminal is disposed at a position not overlapping said second through electrode in the plan view, and said semiconductor chip includes no transistor circuit.