Patent ID: 7110476

Claim:
A demodulation circuit for demodulating a digital transmission signal having improved power consumption levels and sampling frequency for an analog-to digital (A/D) converting means wherein a known signal is inserted in said digital transmission signal at transmission, said demodulation circuit comprising: said A/D converting means for performing A/D conversion of a base band signal obtained by demodulation of said digital transmission signal; and phase shifting means for repeatedly varying a phase shift of one of said digital transmission signal and said base band signal before digital conversion by said A/D converting means on the basis of a comparison between said known signal after digital conversion by said A/D converting means and prior to a parallel-to-serial (P/S) conversion with said known signal that was inserted at transmission, wherein said phase shifting means modifies shifting amounts of a plurality of phase shifting elements for N times (in which N is an integer greater than or equal to one) where the phase shift equals Δθ n (in which n is in the range of 1 to N) and a comparison means compares said known signal after digital conversion by said A/D converting means and said known signal inserted at transmission for each of said N times and a result from said comparison means is stored in a memory means for each of said N times and a second comparison means for comparing each of the N results from said comparison means.