Patent ID: 6941445

Claim:
A resampling address generator for generating a write address and a read address in a buffer memory for a sampling frequency converter, said resampling address generator comprising: a resampling period address generator for generating period data representing a period of the read address in accordance with a sampling frequency ratio between an input clock and an output clock; a resampling period address register for retaining the period data generated by said resampling period address generator; a selector for selectively extracting the period data generated by said resampling period address generator and retained by said resampling period address register; an accumulative adder for generating the read address by accumulatively adding the extracted period data; and a frequency change detector for determining whether or not periods of the input clock and the output clock are stable; wherein, when said frequency change detector determines that the periods of the input clock and the output clock are stable, said selector is controlled to extract the period data retained by said resampling period address register.