Patent ID: 8148750

Claim:
A semiconductor transistor device comprising: a layer of semiconductor material having a channel region defined therein; a gate structure overlying the channel region, the gate structure including a source sidewall and a drain sidewall; a first spacer formed on the source sidewall; a second spacer formed on the drain sidewall; recesses formed in the layer of semiconductor material and adjacent to the channel region, the recesses extending asymmetrically toward the channel region; and stress-inducing semiconductor material formed in the recesses; wherein: the recesses include a source recess and a drain recess; the source recess is a stepped recess having an upper portion that extends to form a pocket under the first spacer, and having a lower portion that is self-aligned with the first spacer; and the drain recess is a stepped recess having an upper portion that is self-aligned with the second spacer.