Patent ID: 7742266

Claim:
An ESD/EOS protection circuit, comprising: a first protection circuit, coupled between an I/O pad and a power pad, the first protection circuit comprising: a first P-type transistor having a control node, a first connection node, and a second connection node, wherein the control node of the first P-type transistor is coupled to a bias voltage, the first connection node of the first P-type transistor is coupled to the power pad, and the second connection node of the first P-type transistor is coupled to the I/O pad; and a third P-type transistor, having a control node, a first connection node and a second connection node, where the control node of the third P-type transistor is coupled to the ground pad, the second connection node of the third P-type transistor is coupled to the control node of the first P-type transistor, and the first connection node of the third P-type transistor is floating, the third P-type transistor is used for providing the bias voltage to the first P-type transistor; and a second protection circuit, coupled between the I/O pad and a ground pad.