Patent ID: 8536701

Claim:
An electronic device packaging structure, comprising: a semiconductor device, comprising: a semiconductor base, comprising a first surface and a second surface, wherein the first surface is opposite to the second surface; a collector, disposed on the second surface of the semiconductor base; a first conductivity type body region, disposed in the first surface of the semiconductor base; a second conductivity type doped region, disposed in the first conductivity type base region; a gate, disposed on the first surface of the semiconductor base, covering a portion of the first conductivity type body region, and a portion of the second conductivity type doped region, the gate being isolated from the first surface of the semiconductor base, the first conductivity type body region, and the second conductivity type doped region by a first dielectric layer; a second dielectric layer, covering the gate and having an opening, wherein the opening penetrates the second conductivity type doped region and extends to a bottom of the opening to expose the first conductivity type body region; and an emitter, disposed on the second dielectric layer over the semiconductor base and filling the opening, the emitter being electrically connected to the second conductivity type doped region and the first conductivity type body region; a first passivation layer, disposed on the first surface of the semiconductor base surrounding the gate and connected to the first dielectric layer; a first conductive pad, disposed on the first passivation layer; a second conductive pad, disposed on the collector on the second surface of the semiconductor base; and at least one conductive through via structure, penetrating the first passivation layer, the first surface and the second surface of the semiconductor base, and the collector, and electrically comected to the first conductive pad and the second conductive pad, wherein the conductive through via structure comprises: a conductive pillar, disposed in the semiconductor base and the collector; and a second passivation layer, disposed between the conductive pillar and the semiconductor base and the collector.