Patent ID: 6947338

Claim:
A memory device, comprising: a data receive gate to buffer, in a first buffer, data to be inputted, by gate control; a data transfer gate to input the data of said first buffer and buffer the same data in a second buffer by gate control; a data write gate to output the data of said second buffer to a data bus by gate control; a memory cell to write and store the data in said data bus; a selector not to connect said data bus to said memory cell when masked by a data mask signal, and to connect the data bus to the memory cell when the masking is released by the data mask signal; and a control circuit to input data to the first buffer by controlling said data receive gate according to a write enable signal and the data mask signal in a present cycle, and input the data of the first buffer to the second buffer by controlling said data transfer gate and then output the data in the second buffer to said data bus by controlling said data write gate in a subsequent cycle, wherein, in said cycle of said control circuit, data is not inputted to the first buffer by controlling the data receive gate, and at the same time data is inputted to the second buffer by controlling the data transfer gate, in a certain cycle depending on a time period from activation of the write enable signal to changing of the data mask signal.