Patent ID: 8433740

Claim:
An M-sequence generator comprising a plurality of series-connected registers and a plurality of EXCLUSIVE-OR gates which feed back pieces of bit data stored in the registers to the registers in each time a clock is fed into said plurality of registers, the pieces of bit data being supplied in parallel from said each register, wherein a period of a cyclic group {(α 1k ), (α 2k ), (α 3k ), . . . } falls within a maximum length period (2 m -1), the cyclic group {(α 1k ), (α 2k ), (α 3k ), . . . } being produced as an element (α k ) that is of a generating element (α k ), the element (α k ) being obtained by raising a root α of a polynomial to a specified power value k of at least 2 (k≧2), the polynomial having the large number of terms in a plurality of polynomials of a Galois field GF(2 m ) in which the number m (m is a positive integer which is 2 or more) of plurality of registers is set to an order m, and the M-sequence generator comprises a Galois field multiplying unit comprising said plurality of EXCLUSIVE-OR gates, pieces of bit data supplied in parallel from the registers is fed into one end of the Galois field multiplying unit in each time the clock is fed while the generating element (α k ) is fed into the other end, the Galois field multiplying unit performing Galois field multiplication between said each piece of bit data and the generating element (α k ), the EXCLUSIVE-OR gate supplying the Galois field multiplication result as feedback bit data to each register in parallel.