Patent ID: 8659092

Claim:
A fabricating method of a complementary metal oxide semiconductor transistor, comprising: forming a first gate and a second gate on a substrate; forming a gate insulator on the substrate to cover the first gate and the second gate; forming a first source, a first drain, a second source, and a second drain on the gate insulator, wherein the first source and the first drain are located above the first gate, and the second source and the second drain are located above the second gate; forming a first channel layer and a mask layer on the gate insulator, wherein the mask layer is located on the first channel layer, and the first channel layer is located above the first gate and is in contact with the first source and the first drain; and forming a second channel layer on the gate insulator, wherein the second channel layer is located above the second gate and is in contact with the second source and the second drain, and the method of forming the second channel layer comprises forming a second channel material layer on the mask layer, the first channel layer, the gate insulator, the first source, the first drain, the second source, and the second drain, and patterning the second channel material layer.