Patent ID: 7184362

Claim:
A page access control circuit of a semiconductor memory device, comprising: an address transition detecting unit adapted and configured to generate a page address transition detecting signal; a column control unit controlled by a page address control signal, and adapted and configured to generate a active operation strobe signal in response to the page address transition detecting signal; a column selecting unit adapted and configured to generate a column selecting signal in response to the active operation strobe signal; a page control unit controlled by a sense detecting signal which represents completion of an operation of a bit line sense amplifier, and adapted and configured to generates the page address control signal in response to a refresh signal and a read command signal; a pre-active unit adapted and configured to generate a normal mode control signal which represents that there is a new external access, and to generate a mode identification signal in response to the page address control signal and the page address transition detecting signal; and a precharge unit controlled by the mode identification signal, and adapted and configured to perform a selective precharge operation.