Patent ID: 8219785

Claim:
A programmable device comprising: a processor core including a processor core master data port; a memory including a memory slave data port; and an unaligned access adapter operable to receive unaligned memory access requests from a plurality of master components, wherein the unaligned access adapter is a component available from a library of components, wherein the plurality of master components includes the processor core and a peripheral implemented on the programmable device, wherein the unaligned access adapter receives unaligned memory access requests from the processor core via the processor core master data port, wherein the unaligned access adapter is operative to stall the processor core responsive to receiving an unaligned memory access request, wherein the unaligned access adapter is further operable to send a memory access request to the memory, wherein the memory access request corresponds to an unaligned access address range that is obtained from a plurality of responses to a plurality of aligned memory accesses, and wherein the unaligned access adapter is further operable to combine and truncate the plurality of responses corresponding to the plurality of aligned memory access requests to form a combined response.