Patent ID: 7378299

Claim:
A process for making a plurality of semiconductor packages, comprising the following steps: providing a lead frame having a thickness between about 10 and about 20 mils, the lead frame including a plurality of units in an array arrangement, each unit having first and second die pads, and an output bar and a plurality of leads arranged at the periphery of the die pads, each lead having an half-etched indentation formed corresponding to a predetermined dicing line; attaching a first semiconductor device onto the first die pad of each unit of the lead frame by solder paste; attaching a second semiconductor device onto the second die pad of each unit of the lead frame by silver epoxy; electrically coupling the first semiconductor device to the output bar; electrically coupling the second semiconductor device to the leads and the first semiconductor device; forming a molded product by encapsulating the semiconductor devices against the lead frame to form a plurality of package bodies each encapsulating the first semiconductor device and the second semiconductor device; and cutting the molded product along the half-etched indentations of the leads into individual semiconductor packages.