Patent ID: 7034479

Claim:
A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references, the digital interface comprising: a first input terminal for receiving a PWM input signal; a first counter stage connected to the first input terminal; a second counter stage connected to an output of the first counter stage; a toggle stage connected to the first input terminal and to an output of the second counter stage; a first output terminal connected to an output of the toggle stage, and to be connected to a control terminal of the first power element; and a second output terminal connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and to be connected to a control terminal of the second power element; the toggle stage generating a second PWM output signal for the first output terminal, the second PWM output signal being kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.