Patent ID: 7939384

Claim:
A method of forming an integrated circuit structure, the method comprising: providing a substrate comprising a first active region, and a second active region adjacent to the first active region; forming a gate electrode layer over the substrate; etching the gate electrode layer, wherein remaining portions of the gate electrode layer comprise: a first gate strip; a second gate strip substantially parallel to the first gate strip, wherein a first lengthwise direction of the first gate strip is substantially parallel, and misaligned to, a second lengthwise direction of the second gate strip; and a sacrificial strip having a lengthwise direction unparallel to the first lengthwise direction and the second lengthwise direction, wherein the sacrificial strip is between the first active region and the second active region, and wherein the sacrificial strip interconnects the first gate strip and the second gate strip; forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip connected to the sacrificial strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip exposed through the opening.