Patent ID: 8502223

Claim:
A silicon wafer having testing pad(s), comprising: a silicon substrate, having a first surface and a second surface; an insulation layer, disposed on the first surface of the silicon substrate; at least one testing pad, disposed on the insulation layer and having a surface, wherein the testing pad comprises: a first metal layer, disposed on the insulation layer, wherein the first metal layer has a first area and a second area, the first area and the second area are separated from each other; a second metal layer, disposed above the first metal layer; and at least one first interconnection metal, connecting the second area of the first metal layer and the second metal layer; a dielectric layer, disposed on the insulation layer and exposing the surface of the testing pad; at least one through hole, penetrating through the silicon substrate and the insulation layer, and exposing part of the first metal layer; and at least one seed layer, disposed on a wall of the through hole and the second surface of the silicon substrate, wherein the at least one seed layer contacts the first area and the second area of the first metal layer, and is electrically connected to the surface of the testing pad through the second area.