Patent ID: 7153707

Claim:
A method for fabricating an integrated circuit structure on a substrate, comprising: forming an insulative layer on the substrate; forming a first opening in the insulative layer; forming digit lines in the first opening; forming a second opening in the insulative layer; and forming an electrode, wherein forming the electrode includes: forming a first portion of the electrode in a lower region of the second opening; forming a second portion of the electrode in the second opening and overlying the first portion, said insulative layer encompassing a sidewall of said second portion; forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein said first portion and said second portion are different materials; and forming a dielectric layer on the third portion, with the dielectric layer including a material from a group of materials consisting of Bax Sr(1−x) TiO 3 , BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 , (Pb,La)(Zr,Ti)O 3 , (Pb,La)TiO 3 , KNO 3 , and LiNbO 3 .