Patent ID: 7940099

Claim:
A method of reducing noise of an all-digital phase locked loop (ADPLL) generating a feedback word representing a continuous-time oscillating signal, the ADPLL including a time-to-digital converter (TDC) input with the continuous-time oscillating signal and a reference signal, the reference signal being a function of a reference clock signal, the TDC generating a digital word, the feedback word being based upon a function of the digital word, the method comprising: adding a pseudo-random sequence to at least one of the reference clock signal, the digital word, and the continuous-time oscillating signal; generating the reference signal by performing at least one of delaying the reference clock signal and delaying a replica of the continuous-time oscillating signal by a time value, the time value based upon a function of a level of the pseudo-random sequence; and generating the feedback word by adding the digital word to a dither signal, the dither signal being generated as an inverted and amplified replica of the pseudo-random sequence.