Patent ID: 8802495

Claim:
A method of manufacturing a semiconductor package comprising: preparing a parent substrate including a plurality of package board parts laterally spaced apart from each other; mounting first chips on the package board parts such that each of the first chips is mounted on a different one of the package board parts, each of the first chips including at least one through-via electrode, back sides of the first chips covering the through-via electrodes; forming a first mold layer on the parent substrate having the first chips; planarizing the first mold layer to expose the back sides of the first chips; etching the exposed back sides of the first chips to thin the first chips and to expose back sides of the through-via electrodes; forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes; and selectively removing the passivation layer disposed on the back sides of the through-via electrodes to expose the back sides of the through-via electrodes.