Patent ID: 7479425

Claim:
A method of fabrication of a non-volatile memory device comprising the steps of: a) forming a bottom tunnel layer over a substrate; the bottom tunnel layer comprised of a lower oxide tunnel layer and an upper hafnium oxide tunnel layer; b) forming a charge storage layer over the bottom tunnel layer; said charge storage layer is comprised of tantalum oxide; b1) in a storage anneal step, annealing the charge storage layer in a nitrogen containing atmosphere; c) forming a lower hafnium oxide blocking layer over the charge storage layer; d) forming an upper cap oxide layer over the lower hafnium oxide blocking layer; the lower hafnium oxide blocking layer and the upper cap oxide layer form a top blocking layer; e) forming a gate electrode over the top blocking layer; f) patterning the bottom tunnel layer, the charge storage layer, the upper cap oxide layer, the lower hafnium oxide blocking layer, and the gate electrode to form a gate structure; and g) forming source/drain regions in the substrate adjacent to the gate structure.