Patent ID: 8866136

Claim:
A transistor comprising: a channel layer including an oxide; a source electrode and a drain electrode configured to separately contact both ends of the channel layer, the source electrode covering a first region of the channel layer and the drain electrode covering a second region of the channel layer; a gate corresponding to the channel layer; a gate insulating layer between the channel layer and the gate, the gate insulating layer including a silicon nitride layer and a silicon oxide layer which are sequentially stacked from the gate; and a passivation layer on the channel layer, the source and drain electrodes, the gate insulating layer, and the gate, the passivation layer including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked, wherein the silicon oxynitride layer includes oxygen through an entire thickness, wherein a portion of the channel layer between the first region and the second region, which is not covered by the source electrode and the drain electrode, is a plasma-treated region that is treated with plasma including oxygen, and the portion of the channel layer includes oxygen provided by the plasma, and wherein the portion of the channel layer between the first region and the second region has an oxygen concentration that is different from the oxygen concentration of a portion of the channel layer that is covered by the source electrode and the drain electrode.