Patent ID: 7749848

Claim:
A method of forming a multi-gate non-volatile memory cell, comprising: forming a first and second source/drain regions on a substrate, the first and second source/drain regions defining an intervening channel region; forming a fixed threshold voltage access field effect transistor (FET) over a first portion of the channel region; and forming a non-volatile memory cell field effect transistor (FET) over a second portion of the channel region by, forming a tunnel insulator layer over the second portion of the channel region, wherein forming the tunnel insulator layer comprises, forming a first layer of oxygen-rich silicon oxy-nitride (SiON) and forming a second layer of alumina (Al 2 O 3 ) over the first layer, forming a trapping layer of silicon-rich silicon oxy-nitride (SiON) over the tunnel insulator layer, forming a charge blocking layer of hafnium oxide (HfO 2 ) over the trapping layer, and forming a control gate over the charge blocking layer.