Patent ID: 7271625

Claim:
A sample-and-hold device, comprising: an amplifier having at least first and a second positive input terminals, first and second negative input terminals, and an output terminal, the amplifier comprising: a first input stage coupled to the first positive input terminal and the first negative input terminal; a second input stage coupled to the second positive input terminal and the second negative input terminal; a switchable bias current source used to provide a first bias current to bias the first and second input stages, wherein the switchable bias current source switches the first bias current to the first input stage during a second period, and switches the first bias current to the second input stage during a first period; and an output stage coupled to the first and second input stages to provide an output signal to the output terminal according to outputs of the first and second input stages; a feedback network used to provide a feedback signal to the first and second negative input terminals according to the output signal; a first capacitor; a second capacitor; a first switch which is coupled in series with the first capacitor between an input signal and a first voltage, and a common node of the first switch and the first capacitor is coupled to the first positive input terminal, wherein the first switch is turned on during the first period to transmit the input signal to the first capacitor to store a first sampling result of the input signal in the first capacitor, and the first switch is turned off during the second period; and a second switch which is coupled in series with the second capacitor between the input signal and a second voltage, and a common node of the second switch and the second capacitor is coupled to the second positive input terminal, wherein the second switch is turned on during the second period to transmit the input signal to the second capacitor to store a second sampling result of the input signal in the second capacitor, and the second switch is turned off during the first period; wherein the feedback network comprises a first and second resistors coupled in series between the output terminal and a third voltage, and a common node of the first and second resistors is coupled to the first and second negative input terminals.