Patent ID: 7271452

Claim:
An analog switch comprising: an input terminal; an output terminal; a first P-channel MOS transistor having a first drain and a first gate, the first drain being connected to the input terminal and the first gate being supplied with a first on/off control signal; a first N-channel MOS transistor having a second drain, a second source, a second bulk and a second gate, the second drain being connected to the input terminal, and the second gate being supplied with a second control signal rendered by inverting the on/off control signal; a second N-channel MOS transistor having a third drain, a third source, a third bulk and a third gate, the third drain being connected to the first source of the first P-channel MOS transistor, the third source being connected to the output terminal, the third bulk being connected to ground potential, and the third gate being supplied with the first on/off control signal; and a second P-channel MOS transistor having a fourth drain, a fourth source, a fourth bulk and a fourth gate, the fourth drain being connected to the second source of the first N-channel MOS transistor, the fourth source being connected to the output terminal, the fourth bulk being connected to the supply potential, and the fourth gate being supplied with the second control signal, wherein the analog switch is turned off when the first off control signal is supplied to the first and third gates and the second off control signal is supplied to the second and fourth gates, whereby an off state of the analog switch is maintained even if the input terminal is supplied with a voltage greater than a power source voltage or lower than a ground voltage.