Patent ID: 7332641

Claim:
A method for producing an interlaced device, the device comprising a first and a second interlaced element, each interlaced element comprising a mated first and second part, the first part having two termini and the second part having two termini, and a defined central void through which the other interlaced element passes, the method comprising: a) providing a first and a second substrate layer, the first and second substrate layers each comprising a top surface, a bottom surface and a mating zone, the first substrate layer to having a portion corresponding to a first part of a first interlaced element and a first part of a second interlaced element and the second substrate layer having a portion corresponding to a second part of a first interlaced element and a second part of a second interlaced element; b) introducing terminal end cuts in the first substrate layer for the first part of the first interlaced element and the first part of the second interlaced element; c) introducing cross-over point cuts in the first substrate layer for the first part of the first interlaced element first part of the second interlaced element; d) introducing terminal end cuts in the second substrate layer for the second part of the first interlaced element and the second part of the second interlaced element; e) introducing cross-over point cuts in the second substrate layer to define a cross-over point of the second part of the first interlaced element and a cross-over point of the second part of the second interlaced element; f) mating the top surface of the first substrate layer to the bottom surface of the second substrate layers by aligning the mating zones and interlaced element parts; g) bonding the top and bottom substrate layers along the mating zones; and h) completing, any cuts necessary to fully define the first and second interlaced elements.