Patent ID: 7952201

Claim:
A semiconductor device comprising: three or more semiconductor chips, each of the three or more semiconductor chips including: a substrate having upper and lower surfaces; first to Nth upper terminals on the upper surface, where N is an integer equal to or greater than three, the first to Nth upper terminals being arranged at vertices of a polygon; first to Nth lower terminals on the lower surface, the first to Nth lower terminals being vertically aligned with the first to Nth upper terminals, respectively; and first to Nth electrodes each of which penetrates the substrate to reach the upper and lower surfaces, (1) the first to N-1th electrodes being electrically coupled to the second to Nth upper terminals, respectively, (2) the Nth electrode being electrically coupled to the first upper terminal, and (3) the first to Nth electrodes being electrically coupled to the first to Nth lower terminals, respectively, wherein the three or more semiconductor chips are stacked with each other such that the first to Nth upper terminals of a lower one of the semiconductor chips are electrically coupled respectively to the first to Nth lower terminals of an upper one of the semiconductor chips, and the first to Nth lower terminals of the lowermost semiconductor chip are electrically coupled through the first to Nth electrodes to, and vertically aligned with, the first to Nth upper terminals of the uppermost semiconductor chip, respectively.