Patent ID: 6952034

Claim:
An electrically programmable and erasable memory device comprising: a substrate of semiconductor material having a first conductivity type and a horizontal surface; a trench formed into the surface of the substrate; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region formed in the substrate therebetween, wherein the first region is formed underneath the trench, and the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate; an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion, wherein there is at most only a partial vertical overlap between the control gate and the floating gate.