Patent ID: 8649202

Claim:
A resistance change memory comprising: a memory cell array area and a resistive element area on a substrate; a first memory cell array in the memory cell array area, the first memory cell array including a first control line which is placed on a first interconnect level and parallel to a first direction, a second control line which is placed on a second interconnect level above first interconnect level and parallel to a second direction crossing the first direction, and a first cell unit provided between the first control line and the second control line; a second memory cell array stacked on the first memory cell array, the second memory cell array including the second control line shared by the first memory cell array and the second memory cell array, a third control line which is placed on a third interconnect level above the second interconnect level and parallel to the first direction, and a second cell unit provided between the second control line and the third control line; a first contact plug in contact with the first control line and a fourth control line placed on the third interconnect level; and a resistive element in the resistive element area, the resistive element including at least two resistance lines provided on at least two interconnect levels in the first to third interconnect levels, and at least one resistor which is connected to the resistance lines and includes the same constituent member as a constituent member of the first contact plug.