Patent ID: 7145227

Claim:
A stacked memory comprising: an upper carrier substrate having a ground layer formed on a lower face of said upper carrier substrate, and leads connected to pads that are formed on said lower face; a semiconductor device having leads; and a lower carrier substrate having pads formed on an upper face of said lower carrier substrate, wherein said semiconductor device is sandwiched between said ground layer of said upper carrier substrate and said upper face of said lower carrier substrate, wherein said leads of said upper carrier substrate are connected to said pads of said lower carrier substrate and said leads of said semiconductor device are connected to said pads formed on said lower face of said upper carrier substrate wherein a thermosetting conductive resin joins at least one of said leads of said semiconductor device and said pads of said upper carrier substrate, said semiconductor device and said ground layer, said leads of said upper carrier substrate and said pads of said lower carrier substrate, and said semiconductor device and said lower carrier substrate.