Patent ID: 8537832

Claim:
A packet classifier for a network processor having a plurality of processing modules and at least one shared memory coupled to an external memory, wherein the network processor generates one or more tasks corresponding to each of a plurality of received packets, the packet classifier comprising: a scheduler configured to generate one or more contexts corresponding to tasks received by the packet classifier from one of the plurality of processing modules; a multi-thread instruction engine configured to process one or more threads of instructions, each thread of instructions corresponding to a context received from the scheduler; a function bus interface configured to inspect instructions received from the multi-thread instruction engine for one or more exception conditions before providing the instructions to a corresponding destination processing module of the network processor, wherein the function bus interface is configured to detect exceptions from the group of: invalid function length, invalid memory offsets, invalid command codes, invalid thread identifiers, invalid destination processing module identifiers, invalid function parameters, and invalid function sequences, wherein if the function bus interface detects an exception condition: the function bus interface is further configured to report the exception condition to the scheduler and the multi-thread instruction engine, wherein the report comprises a unique code corresponding to the exception condition type and a thread identifier of the thread corresponding to the instruction having the exception condition; and the scheduler is further configured to reschedule the thread corresponding to the instruction having the exception condition for processing in the multi-thread instruction engine; otherwise: the function bus interface is configured to provide the instruction to a corresponding destination processing module of the network processor.