Patent ID: 7515475

Claim:
A memory, comprising: a plurality of memory cells; a wordline coupled to each of the plurality of memory cells; a wordline driver having an output coupled to the wordline, the wordline driver capable of driving the wordline to a first logic level to enable access to the plurality of memory cells, and capable of driving the wordline to a second logic level to disable access to the plurality of memory cells, wherein the first logic level corresponds to a first range of voltages including a first desired voltage which is a desired voltage for the first logic level, and the second logic level corresponds to a second range of voltages including a second desired voltage which is a desired voltage for the second logic level; and a logic level reinforcement circuit (LLRC) having an input coupled to the wordline and an output also coupled to the wordline, the LLRC sensing a present logic level on the wordline, which may be either the first logic level or the second logic level, and if the present logic level is the first logic level, the LLRC outputting a first logic level reinforcement signal onto the wordline to push a voltage on the wordline towards the first desired voltage, and if the present logic level is the second logic level, the LLRC outputting a second logic level reinforcement signal onto the wordline to push the voltage on the wordline towards the second desired voltage.