Patent ID: 8207614

Claim:
A partially fabricated integrated circuit comprising: a multilevel mask structure overlying a substrate, the mask structure comprising: rows of substantially periodically spaced elongate features formed from spacer material having a width of less than or approximately 60 nm; columns of substantially periodically spaced elongate features formed from spacer material having a width of less than or approximately 60 nm, the elongate features in the columns crossing substantially perpendicularly the elongate features in the rows such that each elongate feature in the columns crosses substantially perpendicularly multiple elongate features in the rows; an upper hard mask layer underlying the rows of elongate features and the columns of elongate features; and a lower hard mask layer underlying the upper hard mask layer and overlying the substrate, wherein the rows of elongate features and the columns of elongate features define a plurality of voids there between, wherein the voids extend through the upper hard mask layer and the lower hard mask layer.