Patent ID: 7861059

Claim:
A method for programming first and second memory devices arranged in parallel and each including at least one memory bank with a plurality of storage locations and being configured to at least one of receive and store data and retrieve and transmit data associated with the plurality of storage locations, the method comprising: providing successively a first address to the first memory device and a second address that is different than the first address to the second memory device, the first address referring to a first group of the plurality of storage locations in the first memory device and the second address referring to a second group of the plurality of storage locations in the second memory device; determining if the first address matches a stored first bad address in the first memory device so as to constitute an inoperable storage unit; determining if the second address matches a stored second bad address in the second memory device so as to constitute an inoperable storage unit; generating a first modified memory address and a second modified memory address in response to the determination that the first and second addresses respectively match first and second bad addresses by adding a first accumulated offset that includes a first sum of memory address offsets to the first address and a second accumulated offset that includes a second sum of memory address offsets to the second address; providing the first and second accumulated offsets in a feedback loop to respective first and second registers; providing the first and second modified memory addresses to the memory devices; and loading in parallel a string of data to the first and second memory devices whereby the string of data is written simultaneously to each of the first and second groups of the plurality of storage locations.