Patent ID: 7723181

Claim:
A method for fabricating a microelectronic device, comprising: providing a semiconductor substrate comprising thereon a device region and an alignment-mark forming region; forming a trench in the semiconductor substrate within the device region, and simultaneously, forming a previous-layer alignment pattern in the semiconductor substrate within the alignment-mark forming region, wherein the previous-layer alignment pattern comprises a plurality of trench lines; forming a capacitor structure within the trench comprising at least a conductive layer in the trench, wherein the trench lines also comprises the conductive layer; forming a first photo resist layer over the semiconductor substrate and performing an exposure process to form an opening in the first photo resist layer, wherein the opening only exposes the previous-layer alignment pattern in the alignment-mark forming region; using the first photo resist layer as a mask, performing an removing process to remove the conductive layer inside the trench lines; removing the first photo resist layer; forming a second photo resist layer over the semiconductor substrate; patterning the second photo resist layer in both the device region and the alignment-mark forming region, and simultaneously, forming an existing-layer photo resist pattern within the alignment-mark forming region, wherein the existing-layer photo resist pattern and the previous-layer alignment pattern together form an overlay mark; and using the overlay mark to assess AA-DT (active area-deep trench) overlay accuracy.