Patent ID: 8165191

Claim:
A configurable transceiver comprising: a plurality of data processing circuitry blocks including at least some circuitry blocks corresponding to Physical Coding Sublayer (“PCS”) circuitry; and configurable selection circuitry coupled between at least some of the data processing circuitry blocks, the selection circuitry being configurable to either bypass or enable one or more link-wide data processing circuitry blocks and one or more lane-wide data processing circuitry blocks in a data path of the transceiver such that the transceiver is configurable to accommodate data communication using a select one of a plurality of high speed communication protocols, wherein a lane-wide data processing circuitry block of the one or more lane-wide data processing circuitry blocks is adapted to process a subset of data processed by a link-wide data processing circuitry block of the one or more link-wide data processing circuitry blocks.