Patent ID: 8421656

Claim:
Time-interleaved analog-to-digital (AD) conversion circuit, comprising: a first and a second AD converter that generate a first and a second digital signal sequence by converting an analog input signal into first and second digital signals with a first frequency at first and second timings mutually different with each other; a FIFO that receives the first and second digital signal sequences and outputs the first and second digital signal sequences at same timings as a first and a second synchronized digital signal sequence; and a correction filter that corrects errors in the second digital signal sequence caused by an error in the second timings from reference timings, the correction filter including a first and a second portion that are supplied with a common clock signal having the first frequency and operate in synchronous with the common clock signal, each of the first and second portions of the correction filters including a plurality of delay elements each having a delay time equal to a cycle period of the common clock signal; wherein the correction filter generates: a first corrected digital signal sequence by passing the second synchronized digital signal sequence through the first portion of the correction filter and adding the first synchronized digital signal sequence and the second synchronized digital signal sequence passed through the first portion of the correction filter; and a second corrected digital signal sequence by passing the second synchronized digital signal sequence through the second portion of the correction filter.