Patent ID: 8577946

Claim:
A signal receiving apparatus of an orthogonal frequency division multiplex scheme using 2 N subcarriers including 2 (N−(M+L)) *2k data subcarriers and 2 N −{2 (N−(M+L)) *2k} null subcarriers where “N” is an integer equal to or greater than 2, “M” is an integer equal to or greater than 1 where 2 N /2 M is an integer, “L” is an integer equal to or greater than 1 and equal to or smaller than (N−M−1) when “M” is 1 and is an integer equal to or greater than 0 and equal to or smaller than (N−M−1) when “M” is greater than 1, and “k” is an integer satisfying 1≦k≦2 (M+L−1) −1, comprising: 0th to p−1th stage computers configured to apply, in a step by step manner, butterfly operations to 2 N input values corresponding to 2 N FFT (Fast Fourier Transform) points where “p” is a value equal to (log 2 M 2 N )−1; 2 N registers arranged corresponding to the 2 N FFT points and to store values obtained by the butterfly operation by the p−1th stage computer; a pth stage computer comprising (a) 2 L butterfly operation circuits, each including 2 M input ports and 2 M output ports, performing the butterfly operation based on values provided to the input ports, and transmitting values obtained by the butterfly operation from the corresponding output ports and (b) 2 L selecting circuits arranged corresponding to the butterfly operation circuits, each selecting circuit reading a value of a register corresponding to different one of 2 L BFInOrder_i(j,t) and providing the value to a j (0≦j≦2 M −1)th input port of the corresponding butterfly operation circuit where the BFInOrder_i(j,t) denotes values obtained by converting BFOutOrder_i(j,t) expressed by base H to base 2 M of log 2 M 2 N words, word-reversing the converted values, and converting the word-reversed values to the base H, wherein “H” is an integer greater than 1, and the BFOutOrder_i(j,t) denotes t+j*2 (N−M) +i*2 N−(M+L) or (2 (N−(M+L)) −1−t)+j*2 (N−M) +i*2 (N−(M+L) , wherein “t” is an integer expressing a computation time being 0 or greater and 2 (N−(M+L) −1 or smaller, and i is an integer 0 or greater and 2 L −1 or smaller; and an output controller configured to selectively output values corresponding to the data subcarriers among the values transmitted from the output ports of the butterfly operation circuits.