Patent ID: 8551874

Claim:
A method for forming a field effect transistor comprising: selecting a Si containing substrate having a source, drain and channel regions, said channel region having a sacrificial gate dielectric, sacrificial Si gate electrode and sidewall spacers thereover, then forming a metal silicide only in said source and drain regions, forming a first dielectric layer thicker than and over said sacrificial Si gate electrode, planarizing said first dielectric layer down to said sacrificial Si gate electrode, removing said sacrificial gate dielectric and said sacrificial Si gate electrode, then forming a second dielectric layer on said channel region, then forming a metal gate layer over said second dielectric layer, then forming openings in said first and second dielectric layers to said source and drain regions, forming a first metal liner layer over said metal silicide in said source and drain regions and over said metal gate layer, and over sidewalls of said openings in said first and second dielectric layers, forming a second metal layer over said first metal liner layer having a thickness to fill said openings, and planarizing said first metal layer and said second metal layer down to said first dielectric layer.