Patent ID: 6856567

Claim:
A semiconductor memory comprising: a memory array; a self refresh timer for outputting one or more self refresh timing signals during a self refresh test mode of the semiconductor memory; a self refresh counter coupled to the self refresh timer for outputting row addresses in response to the one or more self refresh timing signals during the self refresh test mode; a row address buffer for connecting to the self refresh counter for buffering the row addresses during the self refresh test mode; a row decoder for connecting to the row address buffer and the memory array for refreshing rows in the memory array selected in accordance with the row addresses during the self refresh test mode; and a self refresh test mode controller implemented using one of dedicated hardware and a microprocessor for connecting to at least one of the self refresh timer, the row address buffer, and the row decoder for controlling operation of at least one of the self refresh timer, the row address buffer, and the row decoder for outputting the one or more self refresh timing signals, for holding the row addresses, and for refreshing the selected rows in the memory array in response to self refresh test mode control signals received from an external testing device.