Patent ID: 7428175

Claim:
A dynamic random access memory (DRAM) ( 5 ) comprising memory cells (T 1,1 , T 1,2 , T 2,1 , T 2,2 ) distributed in rows and in columns, each memory cell comprising a MOS transistor ( 10 ) with a floating body ( 11 ), the memory comprising circuitry (DL 1 , DL 2 , SL 1 , SL 2 ) for writing a datum into a determined memory cell belonging to a determined row and to a determined column, wherein the write circuitry comprises: circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V 1 ; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V 2 ; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V 3 , voltages V 1 , V 2 , and V 3 being such that |V 1 −V 2 |>|V 3 −V 2 | and (V 1 −V 2 )×(V 3 −V 2 )>0, and characterized in that it comprises circuitry (DL 1 , DL 2 , SL 1 , SL 2 ) for holding the data stored in the memory cells of the memory, the hold circuitry being capable of bringing the drains and the sources of all the memory cells in the memory to voltage V 3 .