Patent ID: 7461307

Claim:
A method for delay fault testing in a circuit, comprising steps of: providing a scan chain; selecting a subset of scan flip-flops from said scan chain; and replacing said subset of scan flip-flops with a plurality of Enhanced Scan flip-flops, each of said plurality of Enhanced Scan flip-flops comprising a first flip-flop including a first multiplexer, a second flip-flop communicatively coupled to said first flip-flop including a second multiplexer, a functional data input coupled to said first multiplexer and said second multiplexer, a scan input coupled to said first multiplexer, said scan input for receiving signals from an adjacent flip-flop in a scan chain wherein an output of said adjacent scan flip-flop is coupled to said first flip-flop, a SEN (scan enable) control input for providing a SEN signal to said first flip-flop, said SEN control input selecting said first multiplexer of said first flip-flop to provide an input of said first flip-flop with one selected from said functional data input and said scan input, and a ESM control input for providing a ESM signal to said second flip-flop, said ESM control input selecting said second multiplexer of said second flip-flop to provide an input of said second flip-flop with one selected from said functional data input and an output of said first flip-flop, wherein each of said plurality of Enhanced Scan flip-flops is configurable for operating at least one Enhanced Scan flip-flop mode.