Patent ID: 7055075

Claim:
An electronic circuit for self-test of a random access memory array having a plurality of memory storage cells in a circuit, wherein the storage cells are organized into a plurality of slice arrays, comprising: a control circuit, wherein the control circuit is embedded in a control and address block of the RAM circuit; an address selection circuit, wherein the control circuit directs the address selection circuit to index through memory addresses; one input/output circuit each associated with each slice array, wherein the control circuit directs each input/output circuit to write data into its associated slice array at an indexed memory address, to read data from the associated slice array at the indexed memory address, and to compare the data read from the associated slice array with that written into the associated slice array at the indexed memory address; and an error detection circuit, wherein the error detection circuit collects results of self-test data comparisons from each input/output circuit and notifies the control circuit of the results of the data comparisons, wherein: when a defect is present in one of the slice arrays, the input/output circuit associated with the defective slice array redirects data intended for storage in the defective slice array to an adjacent slice array, and wherein: when a defect is present in one of the slice arrays, the input/output circuit associated with the defective slice array redirects data read from the adjacent slice array of the defective slice array to the output of the defective slice array.