Patent ID: 7227398

Claim:
A digital delay circuit comprising: a first delay element; a second delay element having a first input and a second input, wherein said first input is in communication with an output of said first delay element and wherein said second input is operative to receive a digital control signal for adjusting a time delay that said second delay element provides; a multiplexer having a first input, a second input, a third input and an output, wherein said first input of said multiplexer is in communication with said output of said first delay element, said second input of said multiplexer is in communication with an output of said second delay element and said output of said multiplexer is in communication with an input of said first delay element, and wherein said third input of said multiplexer is operative to receive a control signal that selects which of said first and second inputs of said multiplexer is selected as said output of said multiplexer; and a control circuit operative to: receive a signal from one of said outputs of said first and second delay elements; determine a cycle count of said signal received from one of said outputs of said first and second delay elements; and output said control signal whenever said cycle count is equal to a predetermined value.