Patent ID: 8473248

Claim:
A test apparatus configured to receive, from a device under test, a clock signal and a data sequence which is transmitted in synchronization with the clock signal and which contains n (n represents an integer of 2 or more) phases of data for each cycle of the clock signal, and to test the device under test, the test apparatus comprising: a first time to digital converter configured to receive the clock signal, and to generate clock change point information which represents a change timing of the clock signal; a second time to digital converter configured to receive the data sequence in increments of cycles of the clock signal, and to generate data change point information which represents a change timing of the data sequence in increments of phases of the data; a first transform unit configured to transform the clock change point information into information with respect to the frequency domain so as to generate first clock change point frequency information; a filter having predetermined frequency characteristics, and configured to perform filtering of the first clock change point frequency information so as to generate second clock change point frequency information; a second transform unit configured to inverse-transform the second clock change point frequency information into information with respect to the time domain so as to generate second clock change point information; a calculation unit configured to calculate difference data between the change timing represented by the data change point information and the change point timing represented by the second clock change point information in increments of phases; and a judgment unit configured to evaluate the device under test based upon the difference data received from the calculation unit.