Patent ID: 7333365

Claim:
A non-volatile memory device, comprising: a memory cell array having a plurality of Multi-Level Cells (MLCs), each MLC being configured to store at least first and second bits of data; a page buffer coupled to the memory cell array via at least first and second bit lines, the page buffer including: a bit line select unit configured to select one of the first and second bit lines, and connect the selected bit line to a sense node in response to bit line select signals and discharge signals; an upper bit register configured to store upper bit sensing data and output first upper bit output data in response to an upper bit read signal and a voltage level of the sense node, or store first or second input data received through a data I/O terminal or output second upper bit output data in response to data input signals; a data input circuit configured to transmit the first or second input data to the upper bit register in response to the data input signals; and a lower bit register configured to store lower bit sensing data and output first lower bit output data in response to a lower bit read signal and the voltage level of the sense node, or store first or second initial data received through a latch initialization circuit, the latch initialization circuit being configured to generate the first or second initial data in response to the data input signals or output second lower bit output data in response to the data input signals, wherein while the first or second input data is stored on the upper bit register, the first or second initial data having the same value as that of the first or second input data is stored in the lower bit register at substantially the same time in response to data input signals.