Patent ID: 7002369

Claim:
A field programmable device (FPD) implementing a circuit logic containing a first base sequential element to be clocked by a first circuit clock and a second base sequential element to be clocked by a second circuit clock, said FPD comprises: a first modified sequential element to receive a global clock and said first circuit clock, said first modified sequential element containing said first base sequential element, said global clock being connected to a clock input of said first base sequential element, said first base sequential element transitioning to a next state only after occurrence of a transition on said first circuit clock and transition to said next state being timed according to said global clock; and a second modified sequential element to receive said global clock and said second circuit clock, said second modified sequential element containing said second base sequential element, said global clock being connected to a clock input of said second base sequential element, said second base sequential element transitioning to a next state only after occurrence of a transition on said second circuit clock and transition to said next state being timed according to said global clock.