Patent ID: 7483013

Claim:
A semiconductor circuit comprising: m (m is an arbitrary positive integer, m≧3) stages, each of the m stages comprising a circuit group and an inverter circuit, wherein the circuit group includes: a p-channel transistor having a first terminal connected to a first potential power source; a first n-channel transistor having a gate connected to a gate of the p-channel transistor and a first terminal connected to a second terminal of the p-channel transistor; a second n-channel transistor having a first terminal connected to a second terminal of the first n-channel transistor and a second terminal connected to a second potential power source; and an NAND circuit connected to the gate of the p-channel transistor, the gate of the first n-channel transistor, the second terminal of the p-channel transistor, and the first terminal of the first n-channel transistor, wherein an input terminal of the inverter circuit is connected to the second terminal of the p-channel transistor and the first terminal of the first n-channel transistor, wherein a clock signal is input to a gate of the second n-channel transistor in a (2n−1)th (n. is an arbitrary integer, m≧2n≧2) stage, and wherein an inverted clock signal is input to a gate of the second n-channel transistor in a 2n-th stage.