Patent ID: 7490202

Claim:
A cache memory for a cache coherent data processing system including a hierarchy of cache memory devices, the cache memory comprising: a cache controller; a data array including a data storage location for caching a memory block; a cache directory including: a tag field for storing an address tag in association with the memory block; a coherency state field associated with the tag field and said data storage location, wherein said coherency state field has a plurality of possible coherency states; wherein the cache controller sets a coherency state of the coherency state field as a function of a received coherency state for the memory block and a current coherency state for the memory block in the coherency state field, wherein the cache controller determines a relative priority of the received coherency state and the current coherency state, wherein the relative priority between coherency states is defined as: (Mx|Tx)*Ig*Sl*S*In*I, wherein all coherency states to the left of a coherency state has priority over that coherency state.