Patent ID: 8803567

Claim:
A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N>=2, comprising: a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency, wherein the interpolator comprises a plurality of interpolation units INTP and corresponding buffers BUF of the same number, each input end of the interpolation units INTP is connected with an output end of the buffers BUF in the frequency divider, each output end of the interpolation units INTP is respectively connected with an input end of the corresponding buffer BUF in the interpolator, wherein the phase equalizer comprises a plurality of mixers MIXER and a plurality of buffers BUF correspondingly connected with each output end of the mixers MIXER, each input end of the mixers MIXER is connected with the output end of the corresponding buffer BUF in the interpolator, each output end of the mixers MIXER is connected with the input end of another mixer MIXER, so as to form a feedback, wherein supposing a single phase clock of N multiplied frequency is to be obtained by the frequency multiplier system, the number of the interpolation units INTP and the buffers BUF in the interpolator is respectively 2N, the number of the mixers MIXER and the buffers BUF in the phase equalizer is respectively 2N.