Patent ID: 8830365

Claim:
A circuit for processing an analog signal having a time sequence of discrete signal levels, each discrete signal level lying in a time interval and representing an information-bearing segment of the interval, the rest of the interval being a non-information-bearing segment, comprising: a transistor with a first; a second and a third terminal, where the transistor is so arranged that the current flow between the second and the third terminal is adapted to be controlled by a signal at the first terminal, that the time-discrete analog signal is adapted to be applied to the first terminal and that the third terminal is adapted to be coupled to an output node of the circuit; a device for applying a voltage between a first node with a first potential and a second node with a second potential, where the first node is adapted to be coupled to the second terminal of the transistor; a device for supplying a dc current between two terminals, where one terminal is connected to the output node and the other terminal is connected to the second node; a first switch, which is normally open and which is adapted to be controlled so that, in the closed state, it connects the output node to a reference node during at least part of the non-information-bearing segment of the interval so as to create a reference potential at the output node of the circuit; and a second switch, which is located between the second terminal of the transistor and the first node and which is adapted to be controlled so as to interrupt an electrically conductive connection between the first node and the second terminal of the transistor for at least as long as the first switch connects the third terminal of the transistor with the reference node, wherein the transistor is an npn transistor, where the first terminal is a base terminal, the second terminal is a collector terminal, and the third terminal is an emitter terminal, wherein the device for applying a voltage is arranged so as to provide a positive potential at the first node and a ground potential at the second node, wherein the first switch is arranged to remain closed at least until the potential at the output node is smaller than or equal to the smallest expected discrete signal level of the analog signal, or wherein the potential at the reference node is smaller than or equal to the lowest expected discrete signal level of the analog signal, and wherein the switch is arranged to remain closed until the potential at the output node has the potential of the reference node as reference potential.