Patent ID: 7864611

Claim:
A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line, the DRAM comprising: a plurality of source lines and word lines arranged in a row direction; a plurality of bit lines arranged in a column direction; a pair of reference bit lines arranged in a column direction; a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed; a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the pair of reference bit line are crossed so as to output a different reference current; a reference voltage generating unit connected to the pair of reference bit lines and configured to generate a reference voltage corresponding to the different reference current; a sense amplifier and a write driving unit connected to the bit line and configured to receive the reference voltage.