Patent ID: 7428682

Claim:
A semiconductor memory device comprising: a plurality of RAM macros; a plurality of CAM macros; a test pattern generating circuit configured to generate a first test pattern to test said plurality of RAM macros and said plurality of CAM macros, and connected in common to said plurality of RAM macros and said plurality of CAM macros; and a plurality of data generators, wherein each of said data generators is configured to generate a second test pattern to test at least one corresponding CAM macro among said plurality of CAM macros in accordance with said first test pattern input from said test pattern generating circuit and connected to said at least one corresponding CAM macro, wherein said plurality of RAM macros, said plurality of CAM macros, said test pattern generating circuit, and said data generators are formed on a single chip of semiconductor integrated circuit, wherein the length of wiring channels connecting said data generators with said at least one corresponding CAM macro is shorter than the length of the wiring channels connecting said test pattern generating circuit with said data generators, and wherein the number of wiring channels connecting said data generators with said at least one corresponding CAM macro is more than the number of the wiring channels connecting said test pattern generating circuit with said data generators.