Patent ID: 6943061

Claim:
A method of fabricating a semiconductor chip package comprising: providing a semiconductor wafer, said semiconductor wafer having a top surface and a bottom surface, a plurality of bonding pads being located on said top surface; applying at least one nonconductive epoxy sublayer to a said bottom surface of said semiconductor wafer using a screen printing process; completely curing said at least one nonconductive epoxy sublayer; applying a final nonconductive epoxy sublayer on top of said at least one epoxy sublayer, said at least one nonconductive epoxy sublayer and said final nonconductive epoxy sublayer together forming a nonconductive epoxy layer; partially curing said final nonconductive epoxy sublayer such that said final epoxy sublayer is in a soft but solid form; while said final nonconductive epoxy sublayer is still only partially cured, sawing said wafer to create a plurality of semiconductor dice, said nonconductive epoxy layer completely covering a bottom surface of each of said semiconductor dice; and attaching at least one of said semiconductor dice to a die-attach member by means of said nonconductive epoxy layer.