Patent ID: 8085585

Claim:
A semiconductor memory device comprising: a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, each of the memory cell arrays including: a plurality of first lines which are parallel to one another; a plurality of second lines which are formed so as to intersect with the first lines, the second lines being parallel to one another; a memory cell including a non-ohmic element and a variable resistor connected in series and disposed in each intersection portion of the first lines and the second lines, the non-ohmic element having a first conductivity type semiconductor and a second conductivity type semiconductor, the variable resister being connected to one of the first lines, the first conductivity type semiconductor of the non-ohmic element being connected to one of the second lines; a first drive sense line connected to the first lines via first transistors, respectively; and a second drive sense line connected to the second lines via second transistors, respectively, wherein in a data write or data erase, the first drive sense line is driven to an “H” level and the second drive sense line is driven to an “L” level.