Patent ID: 6906562

Claim:
A system comprising a clock multiplier circuit, the clock multiplier circuit comprising: an input clock terminal; an output clock terminal; a first counter circuit having a clock terminal coupled to the input clock terminal and further having N+1 output terminals, where N is an integer; a divide-by-two register having a plurality of data input terminals coupled to N most significant output terminals of the first counter circuit, a clock terminal coupled to receive a clock update signal from the first counter circuit, and a plurality of output terminals; an adder circuit having a first plurality of data input terminals coupled to the N most significant output terminals of the first counter circuit, a second plurality of data input terminals coupled to N−1 most significant output terminals of the first counter circuit, and a plurality of output terminals; a three-quarter register having a plurality of input terminals coupled to the output terminals of the adder circuit, and further having a plurality of output terminals; a second counter circuit having a clock terminal coupled to the input clock terminal, a plurality of data input terminals coupled to the output terminals of the divide-by-two register and the three-quarter register, and a plurality of output terminals; and an output clock generator having a plurality of input terminals coupled to the output terminals of the second counter circuit, and further having an output terminal coupled to the output clock terminal.