Patent ID: 8569144

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a silicon-nitride-based film over a first main surface of a wafer; (b) forming a silicon-oxide-based film over the silicon-nitride-based film; (c) processing the silicon-oxide-based film and a resist film disposed over the silicon-oxide-based film using a lithography process to form a group of first linear films extending in a column direction and openings such that the silicon-nitride-based film remains under the group of first linear films and the openings; (d) after the step (c), forming a resist film over the first main surface, and exposing the resist film to light; (e) subjecting the resist film to a development process to form a group of second linear films extending in a row direction; (f) after the step (e), in a state where there are the group of first linear films and the group of second linear films, performing an etching process to the first main surface to form, in a portion of the first main surface serving as a memory cell array, a plurality of STI unit trench regions each having a rectangular shape longer in the row direction than in the column direction into a matrix arranged in the column direction and the row direction; (g) forming a STI buried insulating film over the first main surface so as to be buried in the STI unit trench regions; (h) subjecting the STI buried insulating film located outside the STI unit trench regions to a planarization process to form a group of STI regions arranged in a matrix; and (i) after the step (h), forming first and second word lines longitudinally traversing, at predetermined space intervals, each row of the group of STI regions arranged in the matrix by a lithography process, wherein alignment in an exposure step in the lithography process in the step (i) is performed using positions in the column direction of the group of STI regions arranged in the matrix as a reference.