Patent ID: 7711974

Claim:
SCLK auto-detection and generation circuitry for use in a digital-to-analog converter audio system in which the number of input pins is reduced, said auto-detection and generation circuitry comprising: a multiplier circuit including a Phase Lock Loop (“PLL”) circuit responsive to a LRCK signal for generating an internal PLL signal which is a predetermined multiple of said LRCK signal; SCLK detection circuit responsive to said LRCK signal and adapted to be coupled to an external serial clock signal input pin for detecting whether an external serial clock signal is present and for generating a selection signal; internal SCLK generator circuit responsive to said internal PLL signal for generating a first internal serial clock signal and a second internal serial clock signal; and multiplexer circuit responsive to said selection signal for selecting said external serial clock signal when said external serial clock signal is detected and for selecting one of said first and second internal serial clock signals when said external serial clock signal is not detected.