Patent ID: 8737134

Claim:
A nonvolatile semiconductor storage device comprising: a cell array including a cell unit, a selection wire and a dummy wire, the cell unit including a memory string in which a plurality of memory cells for storing data are connected in series and one or more dummy cells being provided at one end of the memory string, the selection wire connecting to each of the memory cells, and the dummy wire connecting to each of the dummy cells; and a drive circuit applying voltages to the selection wire and the dummy wire during erase operation for erasing data in the memory cells, the dummy cell adjacent to the memory string being defined as a first dummy cell, the memory cell adjacent to the first dummy cell being defined as a first memory cell, the memory cell adjacent to the first memory cell being defined as a second memory cell, a voltage applied to the dummy wire connected to the first dummy cell being defined as a first dummy wire voltage, a voltage applied to the selection wire connected to the first memory cell being defined as a first selection wire voltage, and a voltage applied to the selection wire connected to the second memory cell being defined as a second selection wire voltage, and when the second selection wire voltage is lower than the first dummy wire voltage in the erase operation, the drive circuit controlling the voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.