Patent ID: 7528475

Claim:
A stacked package, comprising: at least two semiconductor packages including a first semiconductor chip package and a second semiconductor chip package stacked on the first semiconductor chip package, wherein: the first semiconductor chip package includes: a first substrate having an upper surface and a lower surface, the first substrate is formed with a plurality of first land pads and a plurality of first interconnection pads formed outside the plurality of first land pads, the plurality of first interconnection pads having top surfaces exposed by a plurality of upper grooves formed on the upper surface of the first substrate and bottom surfaces exposed by a plurality of lower grooves formed on the lower surface of the first substrate, the plurality of first land pads exposed on the lower surface of the first substrate by a plurality of through holes formed on the lower surface of the first substrate, a first semiconductor chip mounted on the upper surface of the first substrate via a first adhesive, the first semiconductor chip having an active surface with a circuit formed thereon and a surface opposing the active surface, wherein the active surface faces the upper surface of the first substrate, a plurality of inner solder balls formed on the upper surface of the first substrate and electrically connected to the first substrate, and a plurality of outer solder balls formed on the lower surface of the first substrate, wherein the first semiconductor chip and the plurality of inner solder balls are molded by a first epoxy and the surface opposing the active surface of the first semiconductor chip and the plurality of inner solder balls are ground, whereby the plurality of inner solder balls and the first semiconductor chip have same height and the plurality of inner solder balls have exposed contact portions; and the second package includes: a second substrate having an upper surface and a lower surface, a second semiconductor chip mounted on the upper surface of the first substrate via a second adhesive, the second semiconductor chip having an active surface with a circuit formed thereon and a surface opposing the active surface, wherein the active surface faces the upper surface of the second substrate, a plurality of outer solder balls formed on the lower surface of the second substrate and electrically connected to the plurality of inner solder balls formed on the first substrate, and a second epoxy molding the second semiconductor chip, wherein the plurality of inner solder balls of the first semiconductor chip package are formed on the upper grooves of the first substrate, the plurality of outer solder balls of the first semiconductor chip are formed on the plurality of lower grooves and the plurality of through holes of the first substrate.