Patent ID: 8031511

Claim:
A semiconductor device comprising: a memory-cell array including: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction crossing the plurality of word lines; and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines; a plurality of word driver circuits connected to the plurality of word lines; and a plurality of read circuits and a plurality of write circuits connected to the plurality of bit lines, wherein each of the plurality of memory cells includes: a first node connected to a corresponding one of the plurality of word lines; a second node connected to a corresponding one of the plurality of bit lines; a third node provided correspondingly to the second node; a memory element in which a crystalline state having a low resistance is formed by a set operation and an amorphous state having a high resistance is formed by a reset operation; and a switch element in which a current path from the second node to the third node via the memory element is formed upon reception of control of the first node, and wherein, after the reset operation, the read circuit supplied with a determination reference level compares a level generated from the memory element and the determination reference level, thereby performing a verify operation for determining a resistance value of the memory element, and the determination reference level is changed according to an ambient temperature.