Patent ID: 8307168

Claim:
An integrated memory control method, for an interface controller coupled to a control chip through a first interface comprising a first clock, coupled to a micro-processor unit through a transmission interface, and coupled to a memory through a second interface comprising a second clock to control transmitted signals between the memory and the control chip, and between the memory and the micro-processor unit, the integrated memory control method comprising: receiving a first request sent from the micro-processor unit and a second request sent from the control chip respectively for reading data from the memory, wherein the second request is being transmitted for a period comprising a plurality of ticks of the first clock; bridging the second request sent from the control chip to the memory for one portion of the plurality of ticks of the first clock; sending a wait signal to the micro-processor unit to suspend the first request; and varying the frequency of the second clock sent from in the second interface while the first interface is transmitting the second request for the other portion of the plurality of ticks of the first clock to set time points of addresses in the second interface fall behind time points of corresponding addresses in the first interface respectively.