Patent ID: 8464134

Claim:
A method for handling error correction, the method comprising a) maintaining an erase count for at least one block of a solid state memory; b) reading data from one of the memory blocks having an associated erase count; c) establishing and enforcing a policy based on the erase count, wherein the policy identifies transition conditions and error correction parameters used for correcting errors in the read data; d) in accordance with the associated erase count of the memory block, effecting at least one of: i) choosing one of a first decoder and a second decoder; and ii) choosing one of a first decoder mode and a second decoder mode, wherein effecting at least one of the decoder and the decoder mode is based on transition conditions and error correction parameters of the policy; and e) correcting errors in the read data using only the chosen decoder or the chosen decoder mode, wherein the error correction parameters are selected from a group consisting of, (i) selection parameter for selecting the first decoder or the second decoder; and (ii) a decoder mode parameter for selecting the first decoder mode or the second decoder mode of the selected decoder.