Patent ID: 7240184

Claim:
A multipurpose functional unit for a processor, the functional unit compnsing: an input section configured to receive first, second, and third operands and an opcode designating one of a plurality of supported operations to be performed and further configured to generate a plurality of control signals in response to the opcode; a multiplication pipeline coupled to the input section and configurable, in response to the control signals, to compute a product of the first and second operands and to select the computed product as a first intermediate result; a test pipeline coupled to the input section and configurable, in response to the control signals, to perform a comparison on one or more of the first, second, and third operands and to select a result of the comparison as a second intermediate result; an addition pipeline coupled to the multiplication section and the test pipeline and configurable, in response to the control signals, to compute a sum of the first and second intermediate results and to select the computed sum as an operation result; and an output section coupled to receive the operation result and configurable, in response to the control signals, to generate a final result for the one of the supported operations designated by the opcode, wherein the plurality of supported operations includes an integer multiply-add (IMAD) operation that operates on the first, second, and third operands and a logical test operation that operates on at least one of the first, second, and third operands.