Patent ID: 7426675

Claim:
A dynamic random access memory circuit comprising: a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of said memory plane corresponding to a page of words; at least first and second buffer registers coupled with the memory plane allowing reading of words of a memory page and writing of new words to a page of the memory plane, said first and second buffer registers being used alternatively to access said memory; circuits associated with said first and second buffer registers in order to allow a simultaneous submission of a read column address and a write column address; an error correcting mechanism applied to word groups in order to reduce a silicon surface allocated to the error correcting mechanism; an error correcting circuit connected to an output of said at least first and second buffer registers and based on a correcting code applied to a group of n words constituting a sub-assembly of said page; a register connected to an output of said error correcting circuit to store said group of n words, after correction; an array of multiplexers for modifying a word within said group; and an encoder circuit for recomputing a new correcting code based on said modified group before storage thereof in one of said buffer registers.