Patent ID: 8004321

Claim:
A power switch circuit comprising: a power switch including a P-channel Metal Oxide Semiconductor (PMOS) which receives an input voltage, a buffer, and a level-shifter circuit; a power-on reset (POR) circuit configured for a peaking current technique to generate a current and for generating a power-on reset (POR) signal, wherein the POR circuit comprises two NMOS transistors, four PMOS transistors and three resistors, wherein the two NMOS transistors and the three resistors are configured to generate a small current and utilizing the small current to generate a power-on reset signal when the input voltage reaches two times the threshold voltage of the PMOS; a delay circuit coupled to the POR circuit, the delay circuit comprising a plurality of the buffer stages, the delay circuit providing an active POR signal; and an active low reset (PORB) signal for enabling a control loop of the power switch wherein the active POR signal provides for activating the switch by the PORB signal at a predetermined voltage being at least of a minimum lower input voltage.