Patent ID: 7847393

Claim:
A package substrate comprising: an inner interlayer resin insulating layer; a conductor layer formed over the inner interlayer resin insulating layer; an outermost interlayer resin insulating layer formed over the conductor layer; a pad structure having an outermost conductor portion formed on the outermost interlayer resin insulating layer and a plurality of via holes formed through the outermost interlayer resin insulating layer, each of the plurality of via holes being formed directly on the conductor layer and electrically connecting the outermost conductor portion to the conductor layer and; a solder resist formed on the outermost interlayer resin insulating layer and the pad structure, the solder resist having an opening exposing a partially exposed portion of the pad structure; and a conductive connecting pin configured to establish an electrical connection with another substrate, the conductive connecting pin being secured to the partially exposed portion of the pad structure via a solder, the solder being disposed over the partially exposed portion of the pad structure, wherein the outermost conductor portion and the plurality of via holes comprise a first film having an electroless plated film structure, and a second film having an electrolytic plated film structure and formed on the electroless plated film structure.