Patent ID: 8516231

Claim:
An interrupt support determining apparatus for an equal-model processor, comprising: a remaining latency update unit configured to compare a current latency of a current instruction received at a current operation cycle, with a remaining latency of a previous instruction that is set by the remaining latency update unit at a previous operation cycle, and update the remaining latency to the current latency if the current latency is greater than the remaining latency; and an interrupt support determining unit configured to output a flag indicating that processing of an interrupt is not allowed if the updated remaining latency is greater than ‘1’, output the flag indicating that processing of an interrupt is allowed if the updated remaining latency is less than or equal to ‘1’, and continue to output the flag indicating that processing of an interrupt is not allowed until the updated remaining latency is decremented to be equal to ‘1’, wherein the interrupt support determining apparatus is implemented as a hardware logic.