Patent ID: 7413981

Claim:
A method for connecting a plurality of bit lines to sense circuitry, the method comprising: providing a plurality of bit lines extending from a memory array in a first metal layer, wherein the plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer; elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer, wherein the elevated bit lines are separated from each other by an average spacing y in the second metal layer, and wherein y>x; extending a portion of the plurality of bit lines into a second region of the first metal layer, wherein the extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, and wherein z>x; connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry, wherein the sense circuitry includes a multiplexer having contacts that are positioned between two bit lines in the first metal layer.