Patent ID: 7949989

Claim:
A method for layout device matching driven by a schematic editor, the method consisting of: implementing a processor to: identify a master device in a circuit layout having at least transistors, the master device having property values including at least one of topology, name and device-type; identify a cloned device linked to the master device; automatically propagat the property values to the cloned device; make changes to a design layout of the master device, including a change to the property values; automatically propagate the changes to the design layout and the change to the property values of the master device to the cloned device; identify one or more additional cloned devices to which the property values and the changes to the design layout of the master device are propagated; check for changes in the cloned device and the one or more additional cloned devices that are to be matched among the cloned device and the one or more additional cloned devices; and in response to an attempt to make changes to the cloned device and the one or more additional cloned devices, prevent the changes being made to the cloned device and the one or more additional cloned devices, wherein the property values are stored in schematic libraries having one or more schematic pages.