Patent ID: 8361821

Claim:
A method for fabricating a pixel structure, comprising the steps of: (a) providing a substrate; (b) forming a scan line and a gate electrode on the substrate, wherein the gate electrode is electrically connected to the scan line; (c) forming a first insulation layer on the substrate, overlying the scan line and the gate electrode; (d) forming a semiconductor layer on the first insulation layer, wherein the semiconductor layer is overlapped with the gate electrode; (e) forming a source electrode and a drain electrode on the semiconductor layer and a data line on the first insulation layer, respectively, wherein the source electrode is electrically connected to the data line, and wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode define a switch; (f) forming a second insulation layer on the first insulation layer, overlying the data line and the switch; (g) forming a shielding electrode on the second insulation layer, wherein the shielding electrode has a first portion overlapped with the switch, and a second portion extending from the first portion and overlapped with the data line; (h) forming a third insulation layer on the second insulation layer, overlying the shielding electrode; and (i) forming a pixel electrode on the third insulation layer, wherein the pixel electrode has a first portion overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween, and a second portion extending from the first portion having no overlapping with the second portion of the shielding electrode, wherein the source electrode and the drain electrode of the switch are electrically connected to the data line and the pixel electrode respectively.