Patent ID: 8284628

Claim:
A voltage regulator for memory, comprising: a first transistor, having a first end electrically connected to an input node, a second end electrically connected to an output node, and a control end; a feedback unit, electrically connected to the output node; a comparison unit, having a first input end electrically connected to the feedback unit, a second input end for receiving a reference voltage, and an output end electrically connected to the control end of the first transistor; a second transistor, having a first end electrically connected to the input node, a second end electrically connected to the output node, and a control end; a first control unit, electrically connected to the control end of the second transistor, for generating a first control signal to control the second transistor according to an input signal; a third transistor, having a first end electrically connected to the control end of the first transistor, a second end electrically connected to a ground end, and a control end; and a second control unit, electrically connected to the control end of the third transistor, for generating a second control signal to control the third transistor according to the first control signal.