Patent ID: 7701301

Claim:
A system for generating a clock signal comprising: a self-starting oscillator comprising two delay stages in a ring configuration; and a compensation module configured to sense temperature and process variations and adjust a supply voltage for the two-stage ring oscillator to compensate for both temperature and process variations in order to maintain a constant frequency clock signal, wherein the two-stage ring oscillator is configured to generate the clock signal, and wherein the delay stages are configured such that the two-stage ring oscillator has a single right-half plane (RHP) pole in each of the two delay stages where feedback is always positive, and wherein the compensation module further comprises: a replica circuit configured to mirror operation of the n-channel devices within the two-stage ring oscillator; a constant g m circuit configured to provide a biasing current to the replica circuit, the replica circuit receiving the biasing current to generate a reference voltage; and a voltage regulator configured to receive the reference voltage from the replica circuit, the voltage regulator further configured to provide a supply voltage to the two-stage ring oscillator.