Patent ID: 7410860

Claim:
A method of forming a pn junction diode in an integrated circuit, the method comprising: forming a first region of relatively thick material on the surface of a substrate of a first conductivity type, wherein the first region of relatively thick material is thick enough to mask a selected implant; forming a second region of relatively thick material on the surface of a substrate a predetermined distance from the first region, wherein the second region of relatively thick material is thick enough to mask a selected implant; implanting high density of dopants of a second conductivity type in the substrate to form a diode contact using first edges of the first and second regions as masks to define edges of the diode contact, wherein the diode contact is positioned between the first and second regions; and implanting dopants of a first conductivity type in the substrate to form first and second top gate regions using second edges of the first and second regions as masks to define first edges of the first and second top gate regions, wherein the distance between the diode contact and the first top gate region is defined by the lateral length of the first region and the distance between the diode contact and the second top gate region is defined by the lateral length of the second region.