Patent ID: 7669005

Claim:
A content addressable memory (CAM) device, comprising: a plurality of CAM array blocks each including a plurality of rows of CAM cells, wherein each CAM array block has a unique hard priority indicative of the CAM array block's physical location relative to the other CAM array blocks, and has an arbitrarily assigned soft priority that is independent of the CAM array block's physical location relative to the other CAM array blocks; and a priority resolution circuit configured to hierarchically resolve competing soft priorities between a plurality of active hit signals according to numeric significance so that a first of the plurality of active hit signals having a first soft priority will block resolution of a second of the plurality of active hit signals having a second soft priority when the first soft priority is higher than the second soft priority and vice versa when the second soft priority is higher than the first soft priority, and configured to resolve competing hard priorities between two or more of the plurality of active hit signals having equivalent highest soft priorities by identifying which of the two or more of the plurality of active hits signals has the highest hard priority.