Patent ID: 8330471

Claim:
A test apparatus for testing a device under test, comprising: a signal generating apparatus that inputs a pattern signal into the device under test; a signal detecting apparatus that detects an output signal output from the device under test; and a judging section that judges whether the device under test is acceptable based on the output signal detected by the signal detecting apparatus, wherein the signal detecting apparatus comprises: a first comparing section that detects a logic value of the output signal in accordance with a first timing signal having a predetermined cycle time; a second comparing section that detects a logic value of the output signal in accordance with a second timing signal having a different phase from the first timing signal; a selection control section that detects a waveform pattern of the output signal based on one of (i) the logic value of the output signal detected by the first comparing section and (ii) the logic value of the output signal detected by the second comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the output signal; a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the output signal, and outputs the selected logic value; a timing generating section that generates the second timing signal; and a delay circuit that generates the first timing signal by delaying the second timing signal, wherein an output terminal of the device under test for outputting the output signal is connected to a first input terminal of the first comparing section and a first input terminal of the second comparing section, an output terminal of the timing generating section for outputting the second timing signal is connected to a second input terminal of the second comparing section and an input terminal of the delay circuit, an output terminal of the delay circuit for outputting the first timing signal is connected to a second input terminal of the first comparing section, an output terminal of the first comparing section is connected to a first input terminal of the selecting section, and an output terminal of the second comparing section is connected to a second input terminal of the selecting section.