Patent ID: 7496712

Claim:
A system, comprising: a first processor; a first cache overlapping a first corner of the first processor; a second cache overlapping a second corner of the first processor; a third cache overlapping a third corner of the first processor; a fourth cache overlapping a fourth corner of the first processor, wherein the first cache, the second cache, the third cache, and the fourth cache belong to a plurality of off-chip cache memories and are operatively connected to the first processor by proximity communication; and a physical memory comprising a physical address space, wherein the first cache is configured to cache data for the first processor only from a first portion of the physical address space, wherein the second cache is configured to cache data for the first processor only from a second portion of the physical address space, wherein the third cache is configured to cache data for the first processor only from a third portion of the physical address space, and wherein the fourth cache is configured to cache data for the first processor only from a fourth portion of the physical address space.