Patent ID: 8902662

Claim:
A memory system comprising: a first nonvolatile semiconductor memory comprising a first memory cell array and a first control circuit, the first memory cell array having memory cells, the first control circuit executing a first operation that is at least one of write, read, and erase operations with respect to the first memory cell array; a second nonvolatile semiconductor memory comprising a second memory cell array and a second control circuit, the second memory cell array having memory cells, the second control circuit executing a second operation that is at least one of write, read, and erase operations with respect to the second memory cell array; and a detection circuit which is provided to each of the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory and detects whether both the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory are in a ready state, wherein, when the detection circuit detects that both the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory are in the ready state, the first control circuit starts the first operation after elapse of a first standby time, and the second control circuit starts the second operation after elapse of a second standby time different from the first standby time, and wherein the first operation includes a first high-current operation that consumes a current equal to or higher than a predetermined current and a first low-current operation that consumes a current smaller than that of the first high-current operation, the second operation includes a second high-current operation that consumes a current equal to or higher than the predetermined current and a second low-current operation that consumes a current smaller than that of the second high-current operation, and the second standby time is set to a time at which the first high-current operation included in the first operation is terminated, and the first low-current operation and the second high-current operation are concurrently executed.