Patent ID: 7018907

Claim:
A method for forming a shallow trench isolation structure in a semiconductor device comprising: forming a trench in a substrate; forming an oxide layer on sidewalls and a bottom of the trench; forming a metal or poly-silicon layer on the oxide layer; etching a portion of the metal or poly-silicon layer to expose the oxide layer on the bottom of the trench while leaving the metal or poly-silicon layer on the sidewalls of the trench; and depositing a dielectric material layer to fill the trench, wherein forming the trench in the substrate comprises: forming a LP-TEOS (Low Pressure Tetra Ethyl Ortho Silicate) oxide layer on a surface of the substrate; forming a nitride layer on the LP-TEOS oxide layer; forming a PR pattern on the nitride layer; forming a LP-TEOS oxide pattern and a nitride pattern by etching the LP-TEOS oxide layer and the nitride layer using the PR pattern as a mask; removing the PR pattern; and etching the substrate to a predetermined depth using the nitride pattern as a mask.