Patent ID: 7459926

Claim:
An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate; C. bond pads formed on the substrate, a first bond pad inputting test input data and a second bond pad outputting test output data; D. plural scan path circuits formed on the substrate, each of the scan path circuits having a serial input for loading test stimulus data, a serial output for unloading test response data, parallel outputs coupled to the functional circuits to apply the test stimulus data to the functional circuits, and parallel inputs receiving the test response data from the functional circuits; E. scan distributor circuitry having a serial input coupled to the first bond pad and plural parallel outputs, each of the parallel outputs being coupled to the serial input of an associated one of the scan path circuits, the scan distributor circuitry loading the test stimulus data to the serial inputs of the scan path circuits simultaneously with loading the test input data from the first bond pad; and F. scan collector circuitry having a serial output coupled to the second bond pad and having plural parallel inputs, each of the parallel inputs being coupled to a serial output of an associated one of the scan path circuits.