Patent ID: 7159216

Claim:
A method for dispatching threads to central processing units (CPUs) in a computer system, said computer system having a plurality of CPUs and a memory divisible into a plurality of discrete subsets, said method comprising the steps of: (a) identifying a target CPU of said plurality of CPUs; (b) identifying a set of threads which are eligible to execute on said target CPU, said set of threads waiting on a common ready queue wherein no CPU or group of CPUs receives preferential dispatching of tasks from said common ready queue; (c) identifying at least one target subset of said plurality of discrete subsets of memory for each respective thread of said set of threads, each target subset having a respective latency period for memory access by said target CPU to a location within the target subset, wherein said respective latency periods for memory access are not all identical, wherein each CPU of said plurality of CPUs is associated with a respective subset of said plurality of discrete subsets of memory, and wherein said step of identifying at least one target subset of said plurality of discrete subsets of memory comprises designating a respective preferred CPU for executing each thread of said set of threads, said target subset of said plurality of discrete subsets of memory being the subset of memory associated with said preferred CPU; and (d) selecting a thread from said set of threads for execution on said target CPU, said selecting step being based at least in part on said respective latency period of each target subset, wherein said step of selecting a thread from said set of threads for execution comprises allocating a first relative priority to a thread for which the designated preferred CPU is the target CPU, allocating a second relative priority to a thread for which the designated preferred CPU is associated with the same subset of memory as the target CPU, and allocating a third relative priority to a thread for which the designated preferred CPU is not associated with the same subset of memory as the target CPU, said first relative priority being greater than said second relative priority, and said second relative priority being greater than said third relative priority.