Patent ID: 7958338

Claim:
An instruction execution control device, comprising: a reservation station which controls a computing processing and a main storage operand address generation for processing out-of-order execution; a register update buffer which stores data acquired by execution of a function; a register file comprising an architecture register for each thread, and a read thread selection circuit for limiting a number of threads that can be read simultaneously, to a number of threads less than a number of threads of the architecture registers, so that a plurality of threads operate in a simultaneous multi-thread system; and a thread selection circuit which, when reading an operand data from the register file by executing an entry in the reservation station, selects a read thread of the entry before the entry is executed and controls the read thread selection circuit, wherein the operand data is read from an architecture register of the read thread selected by the thread selection circuit when the entry is computed or the operand generation is executed, and the operand data in the register update buffer is stored in the architecture register when data acquired by executing an instruction by the entry in the reservation station is stored in the register update buffer and an instruction executed by the reservation station is completed.