Patent ID: 7229928

Claim:
A method for structuring a layered stack in the production of a semiconductor device, the method comprising: depositing a resist layer on a first layer of the layered stack, the stack further comprising a second layer below the first layer; processing the resist layer with a lithographic method to achieve a first structured resist layer; trimming at least a part of the first structured resist layer to achieve a second structured resist layer, the second structured resist layer having at least in parts a critical dimension smaller than a critical dimension of the first structured resist layer; removing the first layer selectively from the second layer in the areas not covered by the second structured resist layer, modifying an exposed portion of the second layer by implantation in order to change the etchability of the modified portion of the second layer relative to unmodified portions of the second layer; removing remaining portions of the first layer; removing the unmodified portions of the second layer utilizing the etch rate difference between the modified and the unmodified portions of the second layer, thereby creating a hardmask layer from modified portions of the second layer; and further structuring at least one lower layer of the layered stack, the further structuring using the hardmask layer.