Patent ID: 7728751

Claim:
An apparatus, comprising: a pipelined converter comprising a first set of stages and a second set of stages; and a clocking circuit configured to generate a plurality of clocking signals; wherein the plurality of clocking signals comprise a first clocking signal including first and second phases at a first amplitude that are provided to the first set of stages, and a second clocking signal including first and second phases at a second amplitude different than the first amplitude that are provided to the second set of stages; wherein the first and second phases of the first clocking signal are non-overlapping; wherein the first and second phases of the second clocking signal are non-overlapping; wherein the first amplitude is greater than the second amplitude; wherein the greater first amplitude corresponds to a higher voltage level so as to reduce sampling distortion; and wherein a larger clocking voltage is employed at an input of the stages so as to accommodate larger voltage swings at the input stages.