Patent ID: 7812652

Claim:
A locked loop, comprising: a phase detector having a first input coupled to receive a reference signal and a second input coupled to receive a feedback signal, the phase detector being operable to output at least one phase error signal responsive to a comparison of the phase of the reference signal and the phase of the feedback signal; a charge pump coupled to receive the at least one phase error signal from the phase detector, the phase detector having an output and being configured to either apply charge to or receive charge from the output responsive to the at least one phase error signal; a capacitance coupled to the output of the charge pump to provide a control voltage that changes responsive to receiving charge from and applying charge to the output of the charge pump; a bias generator coupled to receive the control voltage from the capacitance, the bias generator being configured to output at least one bias voltage corresponding to the control voltage, a portion of the bias generator having a topography that is substantially to the same as at least a portion of a topography of the charge pump; the portion of the topography of the bias generator that is substantially the same as at least a portion of the topography of the charge pump comprising: a first transistor of a first type and a first transistor of a second type coupled to each other in a first parallel combination; a second transistor of the first type and a second transistor of the second type coupled to each other in a second parallel combination and in series with the first parallel combination; a third transistor of the first type coupled between a first power supply voltage and the first parallel combination; and a third transistor of the second type coupled between a second power supply voltage and the second parallel combination; and an output signal generator coupled to receive the at least one bias voltage from the bias generator, the output signal generator being configured to output an output signal with a phase corresponding to the at least one bias voltage, the output signal corresponding to the feedback signal.