Patent ID: 7667525

Claim:
A bus switch circuit comprising: a first terminal; a second terminal; a first NMOS transistor that is coupled to the first terminal at its source and the second terminal at its drain; a second NMOS transistor that is coupled to the first terminal at its drain; a third NMOS transistor that is coupled to the second terminal at its drain; a first PMOS transistor that is coupled to the first terminal at its drain; a second PMOS transistor that is coupled to the second terminal at its drain; a third PMOS transistor that is coupled to the sources of the first and second PMOS transistors at its source; a fourth NMOS transistor that is coupled to the gate of the third PMOS transistor at its gate; and a fifth NMOS transistor that is coupled to the drains of the third PMOS transistor and the fourth NMOS transistor at its gate and the sources of the second and third NMOS transistors at its drain.