Patent ID: 7237072

Claim:
A memory-built-in data processor connected to an external unit, comprising: a plurality of first data processing parts comprising, a memory configured to store data internal to the data processor, a first bus, a second bus and a third bus, a controller connected to the external unit and the memory via the first bus and the second bus, respectively, and a data processing unit connected to the controller via the third bus, the data processing unit configured to perform readout/write-in of data with respect to the memory via the third bus, the controller and the second bus, and configured to subject the data to desired processing; at least one second data processing part which accesses the whole of memories of the plurality of first data processing parts as one memory space, the second data processing part configured to perform readout/write-in of data with respect to the memories and subjecting the data to desired data processing; and an interface configured to connect the external unit to the second data processing part, wherein the controller is configured to perform arbitration between a first access requirement input from the external unit via the first bus to perform readout/write-in with respect to the memory and a second access requirement input from the data processing unit via the third bus, to access the memory internally; and wherein when memory access destinations of a first access requirement and a second access requirement are on the same area in the memory, the controller checks an access priority for local memory access internal to the data processor, and if the access priority is set, the controller accesses the memory of the second access requirement; and wherein when memory access destinations of the first access requirement and the second access requirement are on different areas in the memory, the controller accesses the different areas simultaneously; and wherein the plurality of first data processing parts, the at least one second data processing part, and the interface are integrated in an integrated circuit; wherein the second data processing part is configured to determine a polygon size of polygon data input from the external unit over the interface, to make the first data processing part according to a position of a polygon represented by the polygon data depicting the polygon, when the polygon data has a polygon size capable of being depicted by means of the first data processing part, and configured to depict the polygon indicated by the polygon data, when the polygon data has a polygon size not capable of being depicted by means of the first data processing unit.