Patent ID: 7855969

Claim:
A method for providing visibility of intermediate signals of a high speed SERDES core, comprising: providing a plurality of test points of the high speed SERDES core; selecting desirable test points from the plurality of test points further including selecting a first test point for having a raw receive signal to appear at a first pin on a chip and a second test point for having Dynamic Feedback Equalization (DFE) processed signal to appear at a second pin on the chip, the first and second test points located on the high speed SERDES core; tapping signals at the plurality of test points further including probing a first signal at the first pin and simultaneously detecting at least a second signal and a third signal at the second pin; and exposing the first signal at the first test point; exposing the second signal and the third signal at the second test point, the second signal being a raw signal as seen on a die, the third signal being a Dynamic Feedback Equalization-processed version of the second signal; and comparing the first signal, the second signal, and the third signal to determine the impact of at least one of an equalization setting or an emphasis setting, and comparing a simulated data expectations to near actual data detected on the chip; buffering the tapped signals in the high speed SERDES core; running the buffered signals at the desirable test points through a programmable analog MUX to dynamically select a desirable signal which gates out through a corresponding pin; and directing the multiplexed signals to a restricted number of debug port pins to control required pin count.