Patent ID: 7761759

Claim:
A semiconductor integrated circuit operable in a normal operation mode for operating an internal logic circuit using a scan circuit, and a scan test mode for testing the internal logic circuit using the scan circuit, comprising: a test mode decision circuit configured to: receive a scan enable signal for controlling which one of (1) data for the normal operation mode and (2) data for the scan test mode should be inputted into the scan circuit, and generate, based at least in part on the scan enable signal, a decision signal having a logic level corresponding to one of (1) the normal operation mode and (2) the scan test mode; and a mask circuit configured to control a masked scan enable signal into the scan circuit by carrying out a logical operation of the scan enable signal and the decision signal, wherein, once the decision signal has been generated, the logic level of the decision signal remains unchanged irrespective of a logic level of the scan enable signal.