Patent ID: 8108859

Claim:
A processor, executing a plurality of threads, each of the plurality threads having a plurality of instructions, comprising: an instruction cache unit that stores instructions of a thread of the plurality of threads; an instruction fetch unit that fetches an instruction of the thread from the instruction cache unit; a cache control unit that detects a cache miss occurring due to an instruction to be fetched by the instruction fetch unit is not stored in the instruction cache unit; an instruction decode unit that decodes the fetched instruction; an instruction execution unit that executes the decoded instruction of the thread; an instruction completion management unit that includes a plurality of entries, each of the entries is created and stores data related to the decoded instruction in order of decoding, and deletes the created entry corresponding to the executed instruction in order of executing when the executed instruction is completed by the instruction execution unit; an uncompleted instruction number report unit that reports a number of uncompleted instructions in response to a number of the entries in the instruction completion management unit; and a thread switching control unit that controls the instruction fetch unit to switch from the thread to another thread of the plurality of threads when the reported number of uncompleted instructions indicates 0 and the cache control units detects the cache miss.