Patent ID: 7072996

Claim:
An input/output (I/O) system that transfers control and data between a core-processing engine and a plurality of bus types including a direct memory access (DMA) data bus and a streaming data bus, the system comprising: a streaming interface to transfer streamed data between the streaming data bus and the core-processing engine; a DMA interface to transfer DMA data between the DMA data bus and the core-processing engine; and an arbiter for coordinating data transfer between the core-processing engine and both the streaming interface and the DMA interface, the arbiter configured to receive a data processing request from the core-processing engine, the data processing request indicating when the core-processing engine is ready to process data, the arbiter operable, in response to the data processing request, to (i) select either the streaming interface or the DMA interface, (ii) enter into an address phase with the core-processing engine, and (iii) enter into a data phase with the core-processing engine to transfer data from the selected interface to the core-processing engine, wherein, when the streaming interface is selected, during the address phase, a dummy address is used for a host source address for reading data, and a dummy address is used as a host destination address when writing data.