Patent ID: 7193447

Claim:
A sense amplifier latch, comprising: a latch module operable to generate first and second rail signals; a precharge and equalization module; an impedance divider network comprising a plurality of MOS devices connected in a push-pull configuration, said impedance divider network having a plurality of input ports operable to receive first and second input signals; first and second pass gates operable to control operation of said impedance divider network to receive one of said first and second input signals; the impedance divider network comprising first and second MOS devices in a first push pull configuration, the first push pull configuration operable to receive the other of the first and second input signals and a reference signal, and third and fourth MOS devices in a second push pull configuration, the second push pull configuration operable to receive the other of the first and second input signals and said reference signal; a first output of the first push pull configuration coupled with the first pass gate, the first pass gate coupled with the first rail signal; a second output of the second push pull configuration coupled with the second pass gate, the second pass gate coupled with the second rail signal; wherein said first and second rail signals are initially precharged to Vdd and thereafter are pulled down to a predetermined voltage level in response to said first and second input signals; and wherein, said MOS devices in said impedance divider network have substantially identical feature sizes and are operable to maintain a difference between said first and second input signals, while maintaining a common mode output voltage at a predetermined level.