Patent ID: 8614479

Claim:
A vertical transistor structure comprising: a substrate; a source configured on the substrate; a first gate configured on the source and having at least one first through hole, the at least one first through hole penetrating the first gate; a first insulating layer configured between the first gate and the source; a second gate configured on the first gate and having at least one second through hole, the at least one second through hole penetrating the second gate; a gate insulating layer configured between the first gate and the second gate and having at least one third through hole, the at least one third through hole penetrating the gate insulating layer, wherein the at least one first through hole, the at least one second through hole, and the at least one third through hole are communicated with one another, the gate insulating layer further has at least one contact window, and the first gate and the second gate are directly physically connected through the at least one contact window; a drain configured on the second gate; a second insulating layer configured between the second gate and the drain; and a semiconductor channel layer filling the at least one first through hole, the at least one second through hole, and the at least one third through hole.