Patent ID: 8923405

Claim:
An apparatus comprising: a plurality of memories configured to store a plurality of first data points, wherein (i) said first data points form a two-dimensional block in either a spatial domain or a frequency domain, (ii) said first data points are arranged among said memories such that a load cycle from said memories accesses a rectangular region of said two-dimensional block and (iii) said load cycle comprises a plurality of read cycles, a different one of said read cycles corresponding to each one of said memories; a first circuit configured to (i) generate said read cycles in response to a command to perform said load cycle and (ii) receive said first data points from said memories, wherein said command defines a shape of said rectangular region being accessed in said load cycle; and a second circuit configured to (i) generate said command, (ii) receive said first data points from said first circuit and (iii) generate a plurality of second data points by a video codec transformation of said first data points between said spatial domain and said frequency domain.