Patent ID: 7285458

Claim:
A method for forming an ESD protection circuit formed at an input/output interface of an integrated circuit formed on a substrate to protect said integrated circuit from damage caused by an ESD event, said ESD protection circuit comprising: forming a polycrystalline silicon bounded SCR on a surface of said substrate by the steps of: forming a first well region lightly doped with impurities of a first conductivity type on a surface of said substrate, forming a second well region within said first well region by lightly doping said second well region with impurities of a second conductivity type, said impurities of the second conductivity type having a polarity opposite from the impurities of the first conductivity type, forming a first diffusion region within said second well by heavily doping said first diffusion region with the impurities of the first conductivity type, forming a second diffusion region within said first well region at a second distance from the first diffusion region by heavily doping said second diffusion region with impurities of the second conductivity type, and forming a heavily doped polycrystalline layer at the surface of said substrate and between the first and second diffusion regions and astride a junction of the first well region and the second well region to form a bounding component to prevent suicide formation at junctions of the first diffusion region and the second well region, the first well region and the second region, and the second diffusion region and the first well region during fabrication of said silicon controlled rectifier; connecting said polycrystalline silicon bounded SCR between a signal input/output interface of said integrated circuit and a power supply connection of said integrated circuit; forming a biasing circuit; and connecting said biasing circuit to said polycrystalline silicon bounded SCR to bias said polycrystalline silicon bounded SCR to turn on more rapidly during said ESD event.