Patent ID: 8902641

Claim:
A digital memory, comprising: an array of magnetoresistive memory bit cells, each of the bit cells comprising at least one magnetic tunnel junction element having at least two magnetic layers in a stack including a pinned layer with a permanent magnetic field establishing a reference direction, and a free layer with a magnetic field component that is selectively alignable parallel to the reference direction, thereby providing a first state of electrical resistance through the stack, and anti-parallel to the reference direction, thereby providing a second state of electrical resistance through the stack; a current bias source for supplying a current to at least a selected one of the bit cells coupled to a comparison circuit for comparing a resistance related parameter of the at least one magnetic tunnel junction element of the selected bit cell to a reference for distinguishing between the first and the second resistance states; at least one current summing transistor coupled to the magnetic tunnel junction elements of the bit cells through their respective addressing conductors and to the current bias source, wherein the reference is based at least partly on a current summed and conducted through the summing transistor, and wherein the reference is based on at least one of a resistance of plural associated magnetic tunnel junction elements, and a resistance determined by a location of the selected bit cell in the array.