Patent ID: 8156495

Claim:
A system for managing a plurality of threads in a processor having a plurality of processing units (PUs), comprising: a) a processor configuration manager configured to: retrieve information descriptive of components of the processors; and create a graph structure including a plurality of nodes, wherein the graph structure is representative of at least a portion of the information; and b) a thread scheduler configured to: identify a first thread of the plurality of threads to be assigned; identify an affinity PU, wherein the first thread has an affinity with the affinity PU, and wherein the affinity PU is one of the plurality of nodes; set the identified affinity PU as a current node; make a first determination, using the information, that the first thread may not be assigned to the affinity PU; set a parent node of the affinity PU as the current node, wherein the parent node comprises a plurality of child nodes, wherein a first child node of the plurality of child nodes is the affinity PU; make a second determination, using the information, that the first thread may be assigned to at least one of the plurality of child nodes; set a second child node of the plurality of child nodes as the current node in response to the second determination, wherein the second child node is a non-affinity PU; and assign the first thread to the non-affinity PU in response to a third determination that the first thread may be assigned to the non-affinity PU.