Patent ID: 8106396

Claim:
A thin film transistor array substrate, comprising: a substrate having a display area and a peripheral area connected with the display area; a plurality of pixel units disposed in the display area; a plurality of signal lines electrically connected with the pixel units, and an end of each of the signal lines having a terminal located in the peripheral area; and a testing circuit disposed on the peripheral area and electrically connected with the terminals of a portion of the signal lines, and the testing circuit comprising: a common gate line having a plurality of notches formed on an edge thereof, a plurality of channel layers disposed above the common gate line; a plurality of drain electrodes disposed on the corresponding channel layers, wherein each of the drain electrodes respectively extends from the top of the common gate line toward the top of one of the notches and further extends along an extension direction to the top of the terminal of one of the signal lines so as to electrically connect thereto, and two extension lines extending from two opposite sides of the terminals that are parallel to the extension direction define a range and a portion of each of the drain electrodes extending along the extension direction is configured outside the range; and a plurality of source electrodes disposed on the corresponding channel layers.