Patent ID: 8176372

Claim:
A semiconductor integrated circuit that includes a built-in self-test circuit for testing a memory, the semiconductor integrated circuit comprising: a data generating unit that generates a data pattern to be input to a data input of the memory; a control-signal generating unit that generates a control signal for controlling read and write of data with respect to the memory; and a one-hot data generating unit that generates one-hot data for a predetermined bit width in which a state of one bit is exclusively inverted with respect to states of other bits, and inputs the one-hot data to the data input or a bit write enable input of the memory, while sequentially shifting a bit position to be inverted; an address generating unit that generates an address of the memory to which the data pattern or the one-hot data is to be input; wherein the built-in self-test circuit has a first test mode and a second test mode, in the first test mode, the one-hot data generated by the one-hot data unit are input to a bit write enable input of the memory, while the data pattern generated by the data generating unit are input to the data input of the memory so as to write the data pattern in an area designated by the address, the data pattern written to the memory is compared with the data pattern read from the memory each time one bit of the one-hot data is exclusively inverted while the address is fixed, and in the second test mode, the one-hot data generated by the one-hot data unit are input to the data input of the memory so as to write the one-hot data in an area designated by the address, while the data pattern generated by the data generating unit are inhibited from inputting to the data input of the memory, the one-hot data written to the memory is compared with the one-hot data read from the memory each time one bit of the one-hot data is exclusively inverted while the address is fixed.