Patent ID: 7206897

Claim:
A memory module comprising: a connector interface; a plurality of memory devices including a first memory device and a second memory device; an integrated circuit buffer device, coupled to the connector interface, to receive control information via the connector interface; a first plurality of signal lines coupled to the first memory device and the integrated circuit buffer device, the first plurality of signal lines to carry a first address from the integrated circuit buffer device to the first memory device; a second plurality of signal lines coupled to the first memory device and the integrated circuit buffer device, the second plurality of signal lines to carry at least a first control signal from the integrated circuit buffer device to the first memory device, the at least a first control signal to specify a read operation by the first memory device such that the first memory device provides first data, accessed from a memory location in the first memory device based on the first address, to the integrated circuit buffer device, the at least a first control signal corresponding to the control information; a first signal line coupled to the first memory device and the integrated circuit buffer device, the first signal line to carry a first signal from the integrated circuit buffer device to the first memory device, the first signal to synchronize communication of the first control signal from the integrated circuit buffer device to the first memory device; a third plurality of signal lines coupled to the second memory device and the integrated circuit buffer device, the third plurality of signal lines to carry a second address from the integrated circuit device to the second memory device; a fourth plurality of signal lines coupled to the second memory device and the integrated circuit buffer device, the fourth plurality of signal lines to carry at least a second control signal from the integrated circuit buffer device to the second memory device, the at least a second control signal to specify a read operation by the second memory device such that the second memory device provides second data, accessed from a memory location in the second memory device based on the second address, to the integrated circuit buffer device, the at least a second control signal corresponding to the control information; a second signal line coupled to the second memory device and the integrated circuit buffer device, the second signal line to carry a second signal from the integrated circuit buffer device to the second memory device, the second signal to synchronize communication of the second control signal from the integrated circuit buffer device to the second memory device; and a transmitter circuit, disposed on the integrated circuit buffer device, the transmitter circuit coupled to the connector interface to transmit the first data and the second data.