Patent ID: 8264026

Claim:
A nonvolatile memory device comprising: a tunneling layer on a substrate; a floating gate on the tunneling layer; an inter-gate dielectric layer structure on the floating gate, the inter-gate dielectric layer structure comprising a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer; and a control gate on the inter-gate dielectric layer structure; wherein the high dielectric layer comprises first and second high dielectric layers laminated on each other, and the first high dielectric layer comprises a material having a lower density of electron trap sites and a larger energy band gap or conduction band-offset than the second high dielectric layer; wherein the first high dielectric layer is directly on the first silicon oxide layer and the second silicon oxide layer is directly on the second high dielectric layer.