Patent ID: 8145877

Claim:
A method for address generation, comprising: obtaining a block size and a skip value; initializing at least one address, at least one increment value, and a step value; wherein the initializing of the at least one address follows from: Π(x)=(f 1 x+f 2 x 2 )mod K, where K is the block size, where f 1 , and f 2 are respective coefficients associated with a quadratic formula, and wherein the initializing of the at least one increment follows from: Π′(x)=[f 2 (2nx+n 2 )+f 1 n)]mod K, where the increment value Π′(x) is a derivation of the address Π(x), and where n is the skip value and x is a first count index for incrementally counting from a first initial value to a first terminal value; setting, by a processor, a second count index for incrementally counting from a second initial value to a second terminal value, the second terminal value being bounded by the block size; for the second count index not in excess of the second terminal value, iteratively performing: selecting an output address for output from at least one phase responsive to at least the at least one address; first updating the at least one address as being equal to summation of the at least one increment value and the at least one address modulo the block size; second updating the at least one increment as being equal to summation of the at least one increment value and the step value modulo the block size; incrementing the second count index; and repeating the selecting, the first updating, the second updating, and the incrementing to output a sequence of addresses; and outputting the sequence of addresses responsive to iterative generation of the output address.