Patent ID: 8072031

Claim:
A p-channel MOS transistor comprising: a silicon substrate; a gate electrode formed on the silicon substrate via a gate insulating film; a channel region formed below the gate electrode within the silicon substrate; a p-type source region and a p-type drain region that are formed at opposite sides of the channel region within the silicon substrate; a first sidewall insulating film and a second sidewall insulating film that are formed on opposing sidewall faces of the gate electrode; a first p-type epitaxial region and a second p-type epitaxial region that are respectively formed at outer sides of the first sidewall insulating film and the second sidewall insulating film on the silicon substrate the first p-type epitaxial region and the second p-type epitaxial region being arranged to have heights larger than a height of the gate electrode; and a tensile stress film that stores tensile stress and is arranged to cover the gate electrode via the first sidewall insulating film and the second sidewall insulating film, said tensile stress film being arranged to continuously cover the gate electrode, the first and second sidewall insulating films, the first and second p-type epitaxial regions, and depression regions between the first sidewall insulating film and the first p-type epitaxial region and between the second sidewall insulating film and the second p-type epitaxial region, wherein a bottom of said tensile stress film on the gate electrode is lower than bottoms of said tensile stress film on the first and the second p-type epitaxial regions.