Patent ID: 7224611

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix form of rows and columns, each memory cell having a first electrode and a pair of second electrodes arranged from which memory data can be read out by a conducting state between the two second electrodes according to the first electrode potential, each row of the memory cells connected at their first electrode with a common word line, any two adjacent memory cells connected at one of the two second electrodes to each other along the row, each column of the memory cells connected at one of their two second electrodes with a common first bit line and at the other with a common second bit line, the first bit lines and the second bit lines arranged alternately; a readout circuit for selecting a pair of the first and second bit lines both connected to the memory cell to be read, applying a predetermined voltage to between the first selected bit line and the second selected bit line, and sensing a memory cell current flowing through the memory cell to be read in order to conduct a readout action; and a counter potential generation circuit for, during the readout action, generating from an intermediate node potential, which is higher than any voltage level of the potential on the first and second selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as that of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied, during the readout action, to one of the first unselected bit lines other than the first selected bit line and second unselected bit lines other than the second selected bit line, which is allocated next to one at a higher voltage level of the first and second selected bit lines or is separated from one at a higher voltage level of the first and second selected bit lines by the or both the bit lines, at least another one of the first unselected bit lines and the second unselected bit lines which is held at the floating state.