Patent ID: 7084027

Claim:
A method for fabricating an integrated circuit, the method comprising: (a) providing an insulation layer on the surface of a semiconductor substrate with a circuit region to be contact-connected; (b) providing a contact hole in the insulation layer for the purpose of contact-connecting the circuit region, the contact hole having an upper region and a lower region; (c) providing a contact plug made of a conductive material in the lower region of the contact hole; (d) providing an insulating spacer region on the sidewalls in the upper region of the contact hole; (e) providing at least three line trenches, of which a first line trench on the one hand runs adjacent to and spaced apart from the contact hole in the insulation layer, a second line trench runs through the contact hole and a third line trench on the other hand runs adjacent to and spaced apart from the contact hole in the insulation layer, the spacer region being left on the sidewalls of the contact hole between the first and the second line trench and the second and the third line trench; (f) filling of the three line trenches with a line material; (g) chemical mechanical polishing of the line material for the purpose of producing three separate lines; and (h) after providing the spacer region, depositing an antireflection coating on the entire structure, which essentially fills the contact hole.