Patent ID: 8754828

Claim:
A display apparatus comprising: a first physical layer circuit (PHY) coupled to receive a first stream of pixel values, wherein the first PHY is configured to drive a first set of control signals to a first display responsive to the first stream of pixel values, wherein the first PHY is in a first clock domain; and a second physical layer circuit (PHY) coupled to receive a second stream of pixel values, wherein the second PHY is configured to drive a second set of control signals to a second display responsive to the second stream of pixel values, wherein the second PHY is in a second clock domain that is independent of the first clock domain; wherein, in a first mode of operation in which the first display and the second display are to show a same one or more frames concurrently, the first stream of pixel values and the second stream of pixel values both represent the one or more frames, and wherein the first PHY is configured to transmit one or more synchronization signals indicating at least a start of each frame, and wherein the second PHY is configured to initiate independent processing of a first frame in the second stream of pixel values responsive to the one or more synchronization signals indicating a start of the first frame.