Patent ID: 8862835

Claim:
A dual port register file comprising: a clock signal; a memory array comprising: a group of rows of memory array registers; synchronous write address decode logic having inputs and outputs, wherein the synchronous write address decode logic outputs select which row from the group of rows of memory array registers data is written; a write port, the write port comprising: pipelined synchronous data registers; pipelined synchronous bit-write registers wherein the pipelined synchronous bit-write registers select which data from the pipelined synchronous data registers is written into the memory array; pipelined synchronous write address registers having inputs and outputs wherein the outputs are electrically connected to the inputs of the write address decode logic, wherein the pipelined synchronous write address registers store a write address; a pipelined synchronous write-enable register, wherein the pipelined synchronous write-enable register selects when the data from the pipelined synchronous data registers is written to the memory array; a read port, the read port comprising an asynchronous read address; asynchronous read address decode logic having inputs and outputs wherein the outputs from the asynchronous read address decode logic select which row of memory array registers is read from the memory array, wherein an asynchronous read address is electrically connected to the inputs of the asynchronous read address decode logic; wherein when the write address stored in the pipelined synchronous write address registers is identical to the asynchronous read address, a result of a bit-wise ANDing of the output from the pipelined synchronous data registers and the output from the pipelined synchronous bit-write registers is output from the dual port register file.