Patent ID: 7764069

Claim:
A process for measuring the bond-line thickness of a semiconductor package, the process comprising: providing the semiconductor package which includes a dielectric material disposed between a semiconductor chip and a heat spreader; providing a device used to measure capacitance, wherein at least one lead of the capacitance measuring device is in electrical communication with the heat spreader and at least one other lead of the capacitance measuring device is in electrical communication with the semiconductor chip; measuring the capacitance of the dielectric material to provide the bond-line thickness B of the dielectric material according to the formula, B=∈ r ∈ o A/C, where C is the capacitance, A is the area of the semiconductor chip, ∈ o is the permittivity of free space and ∈ r is the relative dielectric constant of the dielectric material, wherein the at least one lead in electrical communication with the semiconductor chip is electrically connected to a conductive plate, and providing a chip carrier disposed between the conductive plate and the semiconductor chip, wherein the chip carrier includes a plurality of electrical leads that electrically connect the conductive plate to the semiconductor chip, wherein one or more conducting electrodes extend through one surface to the opposite surface of the heat spreader, and wherein the one or more conducting electrodes are electronically insulated from the heat spreader.