Patent ID: 8327229

Claim:
A data memory system comprising: a nonvolatile memory cell array including a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in said each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit, the nonvolatile memory cell array erasing memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells; an error correction code generation circuit which generates a correction code from first bit information; an error correction code decoding circuit which corrects an error based on the correction code to restore the first bit information; and a first circuit which detects a series of a writing bit, an erasing bit and a writing bit on a second page physically adjacent to a first page to which data is to be written, and outputs a certain bit on the first page that is adjacent to the erasing bit included in the series of the writing bit, the erasing bit and the writing bit, wherein: when the first circuit detects the series of the writing bit, the erasing bit and the writing bit, the certain bit on the first page adjacent to the erasing bit included in the series of the writing bit, the erasing bit and a writing bit on the second page is replaced with the erasing bit, thereby generating an encoded information bit; and a first page output of the first circuit is set as a second code, and the second code is added to the encoded information bit to generate the first bit information.