Patent ID: 8194432

Claim:
A ferroelectric memory device comprising: a plurality of bit lines disposed in a column direction; a plurality of word lines intersecting perpendicularly with the bit lines and disposed in a row direction; a plurality of plate lines intersecting perpendicularly with the bit lines and disposed in a row direction; a bit line control line intersecting perpendicularly with the bit line and disposed in a row direction; a ferroelectric memory cell disposed adjacent an intersection of one of the bit lines and one of the word lines, and adjacent an intersection of the bit line and one of the plate lines, the ferroelectric memory cell including a ferroelectric capacitor and a memory cell transistor, an electrode of one side of the ferroelectric capacitor being connected to the plate line, the memory cell transistor connecting a source to an electrode of another side of the ferroelectric capacitor, connecting a drain to the bit line, and connecting a gate to the word line; and a load capacitor adjustment cell disposed adjacent an intersection of one of the bit lines and the bit line control line, the load capacitor adjustment cell including a load capacitor and a load capacitor adjustment transistor, an electrode of one side of the load capacitor being connected to ground potential, the load capacitor adjustment transistor connecting a source to an electrode of another side of the load capacitor, connecting a drain to the bit line, and connecting a gate to the bit line control line, wherein both of the ferroelectric memory cell and the load capacitor adjustment cell are commonly connected to a same one of the bit lines.