Patent ID: 7602779

Claim:
A microprocessor having a communication module that conducts transmission/reception using packets through a network, and a CPU that processes data included in the packets received by the communication module, the communication module comprising: a register that stores first information that is managed by the microprocessor; and a comparator that compares second information at a given bit position within the received packet with the first information stored in the register to conduct a first determination of whether the CPU processes the data, or not, according to a comparison result, wherein the communication module generates an interrupt request signal with respect to the CPU when the comparator conducts the first determination that the CPU processes the data, and wherein the communication module comprises a process determination unit that inputs a first result that conducts the first determination, a second result that conducts a second determination of whether the packet is addressed to a subject microprocessor, or not, with reference to address information included in the packet, and a third result that conducts a third determination of whether the interrupt request signal is generated with reference to the message identification information included within the packet not depending on the first determination result, or the process is selected on the basis of the first determination result, and conducts a packet reply when both of the first result and the second result are affirmative, and the third result is that the process is selected on the basis of the first determination result.