Patent ID: 7514735

Claim:
A semiconductor device comprising: a semiconductor substrate; a transistor formed on the semiconductor substrate, the transistor including a gate, a source and a drain; a first insulating layer formed above the semiconductor substrate and the transistor; a first hydrogen barrier layer formed on the first insulating layer; a first plug formed in the first insulating layer and the first hydrogen barrier layer, the first plug being connected to the source or the drain electrically; a first lower electrode formed on the first plug; a first ferroelectric layer formed on the first lower electrode; a first upper electrode formed on the first ferroelectric layer; a second hydrogen barrier layer formed on side of each of the first lower electrode, the first ferroelectric layer and the first upper electrode; a second insulating layer formed on the second hydrogen barrier layer; a contact hole formed in the second hydrogen barrier layer and the second insulating layer; an upper wiring layer formed on the second insulating layer and the first upper electrode through the contact hole; a third hydrogen barrier layer formed above the upper wiring layer; a third insulating layer formed on the third hydrogen barrier layer; and a plate line formed on the third insulating layer, the plate line being connected to the upper wiring layer electrically, an element isolation region formed in the semiconductor substrate, the element isolation region being located at both sides of the source or the drain; a fourth insulating layer formed between the semiconductor substrate and the first insulating layer; a second plug formed in the fourth insulating layer; and a lower wiring layer formed between the first plug and the second plug.