Patent ID: 7402854

Claim:
An integrated circuit structure, comprising: a plurality of active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer; a plurality of voltage supply planes, each of the voltage supply planes residing in a respective one of the active layers, each of a given one of the voltage supply planes including at least one capacitor connected between the given voltage supply plane and at least one of the other voltage supply planes, the voltage supply planes being configured such that for a given one of the active layers, a corresponding voltage supply plane serves as a virtual ground for another one of the active layers formed above and adjacent to the given active layer, the voltage supply planes being further configured such that leakage current associated with the given one of the active layers is added to current supplied to another of the active layers formed below and adjacent to the given active layer; and a plurality of circuits, each of the active semiconductor regions including at least one of the plurality of circuits, the plurality of circuits including at least two timing circuits residing in at least two respective active semiconductor regions, the timing circuits being configured such that a prescribed timing relationship is maintained between the at least two respective active semiconductor layers, at least one of the plurality of circuits including clock distribution circuitry for distributing a reference clock signal supplied to the integrated circuit structure throughout the integrated circuit structure, wherein each of the plurality of circuits is connected to a corresponding voltage supply plane in such a manner as to achieve substantially uniform power consumption across each of the plurality of active semiconductor regions; wherein a voltage supplied to the integrated circuit structure is substantially equal to a sum of voltage requirements corresponding to the respective supply voltage planes, and wherein loads on voltage supplies from one active layer to another active layer are substantially balanced so as to facilitate prescribed voltage differentials on each of the voltage supply planes.