Patent ID: 7496771

Claim:
A processor, comprising: a controller; an execution unit, coupled to the controller; an instruction cache, coupled to the controller; a scratch pad, coupled to the controller; a comparator coupled to the controller; and a memory management unit (MMU) coupled to the comparator, wherein the controller initiates an instruction fetch associated with a virtual address, the MMU translates the virtual address to a physical address, and the comparator determines whether the physical address is associated with the scratch pad, and when the scratch pad is enabled, the scratch pad is accessed to retrieve an instruction based on the virtual address in parallel with the MMU translation and if the physical address is associated with the scratch pad, the controller provides the instruction to the execution unit, otherwise, the controller disables the scratch pad to reduce power consumption and re-initiates the instruction fetch for the virtual address, and when the scratch pad is disabled, if the physical address is associated with the scratch pad, the controller enables the scratch pad and re-initiates the instruction fetch for the virtual address.