Patent ID: 7805593

Claim:
A system in an integrated circuit for real-time performance monitoring, comprising: performance monitors instantiated in programmably configurable resources of the integrated circuit; the programmably configurable resources including configuration memory; the configuration memory programmed for instantiation of the performance monitors; an embedded processor comprising a pipeline; an auxiliary processing unit coupled to the performance monitors, the auxiliary processing unit being in the integrated circuit, the auxiliary processing unit being a controller for interfacing to the pipeline of the embedded processor and observing instruction sequences to facilitate real-time performance monitoring by decoding predetermined instructions flowing through the pipeline; the embedded processor located in the integrated circuit and coupled to the auxiliary processing unit, the auxiliary processing unit coupled to obtain real-time execution status of an instruction as the instruction is being processed in the pipeline of the embedded processor including prior to exit from a final stage thereof, the auxiliary processing unit configured to provide the execution status of the instruction to the performance monitors for the real-time performance monitoring; the performance monitors coupled via dedicated wiring to a decode stage and an execution stage of the pipeline of the embedded processor via the auxiliary processing unit for dynamic instruction stream analysis; the dynamic instruction stream analysis including data gathering for statistical analysis including for Real-Time Operating System statistics; and the performance monitors being partitioned for per-clock cycle or per-instruction monitoring for the dynamic instruction stream analysis.