Patent ID: 7917822

Claim:
An integrated circuit comprising: A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; B. test access port circuitry having a TDI input connected to the TDI lead, a TDO output connected to the TDO lead, a TMS input coupled to the TMS lead, and a TCK input coupled to the TCK lead, the test access port circuitry providing an enable serial input signal, and an input/output sync signal; C. sync circuitry having a first input coupled to the enable serial input signal, a second input connected to the input/output sync signal, a sync clock input, and an input enable output, the sync circuitry including: i. flip-flop circuitry having a data input and a reset input connected with the first input, a clock input connected with the sync clock input, and a non-inverting output, and ii. multiplexer circuitry having an input connected with the first input, another input connected with the non-inverting output, a control input connected with the input/output sync signal, and the input enable output; and D. serial communication circuitry having an input enable input connected to the input enable output.