Patent ID: 7943958

Claim:
A method of increasing the holding voltage of an LVTSCR structure, comprising forming an n-well and a p-well in a substrate, forming a first n+ region and a first p+ region in the n-well wherein the first n+ region defines a drain, forming a second n+ region and a second p+ region in the p-well wherein the second n+ region defines a source, providing a gate above a channel region, the channel region is located between the drain and the source, and forming an additional n+ region inside the p-well LVTSCR of the structure to define a p-n junction of a diode between the additional n+ region and the p-well, with the second p+ region forming an anode contact to the diode, and the p-n junction of the diode being forward biased during normal operation by having said additional n+ region located at a first distance from the drain and the second p+ region located at a second distance from the drain, wherein the first distance is greater than the second distance.