Patent ID: 7458045

Claim:
A computer-implemented method of generating information related to manufacturing an integrated circuit (IC) in silicon, the method comprising: automatically selecting at least a group of names of circuit elements from among a plurality of names of circuit elements in a circuit model of an IC design of the integrated circuit, based on each circuit element named in the group having a circuit attribute of a value in conformance with a predetermined condition; wherein the predetermined condition is based on at least one of: a predetermined range for said value, a predetermined limit on said value, said value being highest, and said value being smallest; wherein the plurality of names comprises at least names of instances of cells in a library used in the IC design, and names of nets interconnecting the instances; automatically using the group of names of circuit elements, obtained from automatically selecting, to select a plurality of shapes existing in a layout of the IC design; automatically storing in a memory at least geometric data related to the plurality of shapes, and associated therewith the circuit attribute used in said automatically selecting; automatically identifying a silicon tolerance for the plurality of shapes, from the circuit attribute associated therewith, by use of a predetermined correspondence between the silicon tolerance and the circuit attribute; and performing resolution enhancement by using said silicon tolerance on said plurality of shapes, and using a default tolerance on another plurality of shapes.