Patent ID: 6960821

Claim:
A semiconductor device, comprising: an array of lateral transistors formed on a trench wall of a trench in a silicon wafer, wherein the silicon wafer has a top surface in a (100) crystal plane orientation an the trench wall has a (110) crystal plane orientation, and wherein each lateral transistor includes: a first conductive region in a first portion of the trench wall; a second conductive region in a second portion of the trench wall; and a third conductive region in a third portion of the trench wall, such that the third conductive region is between the first and second conductive regions and wherein each lateral transistor is configured to conduct an electrical current between the first conductive regions and the second conductive region in a <110> direction; and a wordline coupled to a gate of each lateral transistor formed on the trench wall of the trench of the silicon wafer.