Patent ID: 7348841

Claim:
An integrated circuit comprising: a first transistor coupled between an input node and a first node; a first impedance matching circuit coupled between the first node and a second node; a second impedance matching circuit coupled between the second node and a third node; a second transistor coupled between the third node and a fourth node; a third impedance matching circuit coupled between the fourth node and a fifth node; and an impedance transforming circuit coupled between the second node and the fifth node, wherein in a first mode of operation, a signal provided at the input node passes through the first transistor, first impedance matching circuit, and impedance transforming circuit, in a second mode of operation, the signal provided at the input node passes through the first transistor, first impedance matching circuit, second impedance matching circuit, second transistor, and third impedance matching circuit; and a voltage control circuit coupled to the first transistor, wherein the voltage control circuit, in response to the mode control voltage, provides a signal to the first transistor to adjust a bias of the first transistor so during the first mode of operation the bias of the first transistor is reduced compared to the bias of the first transistor during the second mode of operation.