Patent ID: 7882458

Claim:
A power consumption analyzing method, comprising: extracting a signal judged as to whether the signal is transformed into a gated clock in a logic synthesis stage; storing the signal in a memory part; measuring a valid time of the signal stored in the memory part by a logic simulation; storing the valid time in the memory part; and computing a power consumption analysis result of a circuit from the valid time stored in the memory part, a number of registers for each of modules that are function units forming the circuit, and a memory capacity coefficient indicating an extent to which a memory capacity within the circuit affects the power consumption of the circuit, wherein the extracting of the signal includes: extracting the signal judged whether the signal is transformed into an enable signal of the gated clock after a logic synthesis, from RTL design information stored in the memory part, and storing in the memory part a signal name of the signal and path information from a highest hierarchical level of the module in which the signal exists, together with the number of registers for each module, and generating a test bench that is provided with a counter for measuring a valid time of the signal, from the signal name and the path information read from the memory part, and storing the test bench in the memory part.