Patent ID: 8013399

Claim:
A static random access memory cell which, on a substrate surmounted by a stack of layers, comprising: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region, the second plurality of transistors is formed: from a first load transistor and a second load transistor, a first conduction transistor and a second conduction transistor, and the first load transistor, the second load transistor and the first conduction transistor and the second conduction transistor being formed in a single level of said stack.