Patent ID: 8667040

Claim:
An apparatus for performing a carryless multiplication, comprising: first and second operand registers, configured to respectively receive first and second operands for the carryless multiplication; an opcode detector, configured to receive a carryless multiplication instruction, and configured to assert a carryless signal responsive to receipt of said carryless multiplication instruction; a carryless preformat unit, configured to partition said first operand into a plurality of parts responsive to assertion of said carryless signal, wherein said plurality of parts are configured such that a Booth encoder is precluded from selection of second partial products of said second operand, and wherein said second partial products reflect implicit carry operations; a compressor, configured to sum first partial products of said second operand via a configuration of carry save adders that generate sum bits and carry bits, wherein said carry save adders are arranged in a Wallace tree configuration, and wherein generation of said carry bits is disabled responsive to assertion of said carryless signal; a left shifter, coupled to said compressor, configured to shift bits of one or more outputs of said compressor; and exclusive-OR logic, coupled to said compressor and said left shifter, configured to execute an exclusive-OR function on said outputs to yield a carryless multiplication result.