Patent ID: 7714378

Claim:
A semiconductor device comprising: a semiconductor substrate; multiple floating gate structures, each comprising: a tunnel oxide layer pattern on the substrate; a floating gate polysilicon layer pattern on the tunnel oxide layer pattern; an inter-gate dielectric layer pattern on the floating gate polysilicon layer pattern; a control gate polysilicon layer pattern on the inter-gate dielectric layer pattern; a control gate metal layer pattern on the control gate polysilicon layer pattern, wherein a width of the control gate metal layer pattern is greater than a width of the control gate polysilicon layer pattern; and a hard mask pattern on the control gate metal layer pattern, wherein a lower side of the hard mask pattern contacts the control gate metal layer pattern and a width of the lower side of the hard mask pattern is greater than a width of the control gate metal layer pattern; an insulating layer on the substrate and on the multiple floating gate structures; and an inter-layer contact in the insulating layer between a pair of the multiple floating gate structures, wherein the inter-layer contact has an upper portion that is wider than a lower portion thereof, and wherein the upper portion of the inter-layer contact overlaps a portion of the control gate metal layer pattern.