Patent ID: 7243252

Claim:
A semiconductor device which outputs internal data to an external data bus of a width narrower than the width of an internal data bus, the device comprising: a data selection circuit for selecting data from n divided data blocks on an internal data bus of a width of m bits; a data output section for outputting the data in the data block selected by the data selection circuit to an external data bus of a width of m/n bits; an output control circuit for generating n selection signals in order in response to an output start signal, for controlling so that the data selection circuit will select data according to the data blocks, and for outputting two complementary synchronous signals the states of which change reversely each time the selection signal is generated and a synchronous signal synchronized with the first selection signal; and a synchronous signal output section for outputting the complementary synchronous signals and the synchronous signal to synchronous signal lines as strobe signals and a start signal respectively, wherein the data selection circuit, the data output section, the output control circuit, and the synchronous signal output section operate in synchronization with an output clock at a frequency higher than the frequency of a system clock, and wherein the output control circuit includes: n latch circuits for outputting the selection signals in order in synchronization with the output clock by the method under which the output start signal is latched and a first selection signal is output in response to the output clock and under which the first selection signal is latched and a second selection signal is output in response to the next output clock; a first OR gate for inputting output from odd latch circuits of the latch circuits; and a second OR gate for inputting output from even latch circuits of the latch circuits, and wherein the output control circuit outputs the first selection signal as the synchronous signal.