Patent ID: 7840744

Claim:
A method of interfacing a processor and memory of a system, comprising: generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; determining whether the memory includes a plurality of ranks; if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; wherein employing the processor to update the address associated with the first command includes adapting the processor to update a value stored in a predetermined bit position to indicate a memory rank targeted by the first command; if the memory does not include a plurality of ranks, employing a memory interface controller (mic) to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and converting the first command and associated updated address to a second command and associated address that are employed to access the memory.