Patent ID: 7724594

Claim:
A leakage current control device of a semiconductor memory device, comprising: a refresh block detecting unit configured to detect a block where a refresh operation is performed in response to a driving control signal generated by combination of a block selecting signal; a control signal input unit configured to latch and output a signal from the refresh block detecting unit for a predetermined time at a standby mode; a voltage control unit configured to supply a bit line precharge voltage to a bit line in response to an output signal from the control signal input unit at a refresh mode and to supply a ground voltage to the bit line at the standby mode, wherein the bit line precharge voltage is supplied to the bit line in the block where the refresh operation is performed and in a block where a subsequent refresh operation is performed; a refresh counter configured to count a refresh operation and output the driving control signal in a predetermined refresh period; a latch unit configured to latch an output signal from the control signal input unit and output N control signals, wherein N is an integer greater than zero; and a logic unit configured to perform a logic operation on the N control signals and a predetermined logic signal and to output (N+1) control signals to the voltage control unit.