Patent ID: 8885403

Claim:
In a split gate memory having a first sector of split gate memory cells arranged in rows and columns, wherein each split gate memory cell has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to a bit line along one of the columns, and a source terminal, a method of selective programming, comprising: for a split gate memory cell selected for programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage; and for split gate memory cells split gate cells not being programmed by being coupled to a deselected row, coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected.