Patent ID: 7622799

Claim:
A semiconductor device with which a first chip and a second chip are stacked over a front surface of a wiring substrate, wherein an interposer chip is formed over a front surface of the first chip, adjoining the second chip; a plurality of first electrodes are arranged along one side of a front surface of the wiring substrate; a plurality of second electrodes are arranged along one side of a front surface of the interposer chip, at a side of the first electrodes; a plurality of third electrodes are arranged along one side of a front surface of the second chip, at the interposer chip side; a plurality of fourth electrodes are arranged along another side of the front surface of the second chip, a projection of which intersects perpendicularly with another side of the interposer chip; a plurality of fifth electrodes corresponding to the third electrodes and a plurality of sixth electrodes corresponding to the fourth electrodes are arranged along the front surface of the interposer chip; a distance between at least one fifth electrode among the fifth electrodes and the another side of the interposer chip is longer than a distance between the each sixth electrode, and the another side of the interposer chip; each third electrode is connected to a corresponding fifth electrode via a bonding wire; each fourth electrode is connected to a corresponding sixth electrode via a bonding wire; each fifth electrode is connected to a corresponding second electrode via a wiring of the interposer chip; each sixth electrode is connected to a corresponding second electrode via a wiring of the interposer chip; and each second electrode is connected to a corresponding first electrode via a bonding wire.