Patent ID: 8058163

Claim:
A method for a semiconductor device using dielectric encasement, the semiconductor device comprising a substrate layer, a passivation layer overlying the substrate layer, and a plurality of under bump metallurgies (UBMs), each UBM extending onto a top surface of the passivation layer, the method comprising: forming a photoimageable permanent dielectric layer overlying the passivation layer; patterning the dielectric layer to form a plurality of openings in the dielectric layer, each opening positioned over a respective one of the UBMs, and each opening having a sidewall; adding fluxing material into each of the plurality of openings; applying solder to a respective top surface of the fluxing material in each of the openings; and heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to and fully cover the respective sidewall of each opening.