Patent ID: 7122431

Claim:
A method of forming a unit cell of a metal oxide semiconductor (MOS) transistor, comprising: forming an integrated circuit substrate; forming a MOS transistor on the integrated circuit substrate, the MOS transistor having a source region, a drain region and a gate, the gate being between the source region and the drain region; forming first and second spaced apart buffer regions beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate; and forming a channel region beneath the gate and between the source and drain regions, wherein the first and second buffer regions are defined by the channel region and respective ones of the source and drain regions and wherein a portion of an upper surface of the channel region is lower than upper surfaces of the first and second buffer regions, wherein forming the gate comprises forming a gate electrode on the channel region and forming a capping layer on the gate electrode, wherein a bottom surface of the gate electrode is lower than bottom surfaces of the first and second buffer regions and wherein a bottom surface of the channel region is lower than the bottom surfaces of the first and second buffer regions.