Patent ID: 8269563

Claim:
A method for generating a digitally controlled oscillator (DCO) signal output at a frequency that changes at dithered intervals, comprising: generating a dithered clock signal comprising: receiving an undithered reference clock signal in a first buffer; and applying a pseudo-random number generator to a first set of switches to vary the amount of analog capacitive loading on an output of the first buffer over time, wherein the dithered clock signal has a center frequency that is significantly lower frequency than the DCO signal output; receiving the dithered clock signal at the DCO; receiving an undithered stream of digital tuning words at the DCO; dithering the undithered stream of digital tuning words by decoding the undithered stream of digital tuning words into switch control signals and latching the decoded switch control signals coincidentally with a rising edge of the dithered clock signal; and outputting the decoded switch control signals to selectively open and close a second set of switches which determine the resonant frequency of the DCO signal output.