Patent ID: 7406567

Claim:
A method comprising: mapping a shared memory into first and second virtual address spaces, with the shared memory holding buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between Input/Output (I/O) devices which send and receive packets and a Central Processing Unit (CPU); setting a cache attribute for the first virtual address space and utilizing the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses in the first virtual address space to access only buffer data structures; reporting addresses in the first virtual address space to code executed by the CPU which implements switching; returning pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory; setting a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second address space; converting a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an I/O device; at the I/O device, using the converted pointer to access packet data stored in a buffer data structure in the shared memory; and at the CPU, invalidating the cache lines corresponding to the addresses of a received packet before accessing data in the received packet.