Patent ID: 6982494

Claim:
A semiconductor device, comprising: a semiconductor chip having a main surface, wherein the main surface has a first area, a second area located outside and adjacently to the first area and a third area located outside and adjacently to the second area; first, second and third electrode pads formed on the main surface in the third area, wherein the first, second and third electrode pads are aligned with each other and wherein the second electrode pad is located between the first and third electrode pads; an insulating layer formed on the main surface in the first, second and third areas, wherein the first, second and third electrode pads are exposed from the insulating layer; a first exterior terminal formed above the insulating layer in the first area; a second exterior terminal formed above the insulating layer in the second area; a third exterior terminal formed above the insulating layer in the first area; a first conductive pattern formed above the insulating layer, so that the first conductive pattern electrically connects the first electrode pad and the first exterior terminal; a second conductive pattern formed above the insulating layer, so that the second conductive pattern electrically connects the second electrode pad and the second exterior terminal; and a third conductive pattern formed above the insulating layer, so that the third conductive pattern electrically connects the third electrode pad and the third exterior terminal, wherein the first and third conductive patterns are longer than the second conductive pattern, the second exterior terminal is sandwiched between the first and third conductive patterns, and a same predetermined potential is applied to the first and third electrode pads.