Patent ID: 8234594

Claim:
An integrated circuit comprising: a first wire in a first level of wiring tracks; a second wire in a second level of wiring tracks, said second level being adjacent said first level; a first via connecting said first and second wires at a first location of said second wire; a third wire in a third level of wiring tracks, said third level being adjacent said second level; a second via connecting said second and third wires at said first location, said second via being approximately axially aligned with said first via; a fourth wire located a first distance from said second wire in said second level; a third via connecting said third and fourth wires at a second location of said fourth wire; and a fourth via connecting said first and fourth wires at said second location, said fourth via being approximately axially aligned with said third via; wherein said second, third, and fourth vias, and said third and fourth wires form a path between said first and second wires redundant to said first via.