Patent ID: 7145789

Claim:
A content addressable memory (CAM) block array, comprising: a multiple CAM blocks, wherein the multiple CAM blocks are organized into at least one rectangular array having rows, wherein each row has a plurality of CAM blocks and an associated GMAT line, wherein each column in the rectangular array has a compare data line and a compare complement data line, wherein each CAM block is associated with a row and a column of the CAM block array, and wherein each CAM block comprising: one or more CAM cells; an associated LMAT line connected to the one or more CAM cells and the associated GMAT line; and a conversion circuit having at least one LMAT precharge transistor connected between an input voltage terminal and the LMAT line, at least one GMAT evaluation transistor connected between the input voltage terminal and the GMAT line, and a GMAT predischarge transistor connected between the GMAT line and a ground terminal.