Patent ID: 8423686

Claim:
A method for detecting inopportune or erroneous transactions by way of a direct memory access unit or of an external master peripheral, for implementation on a microcontroller, said microcontroller exhibiting a direct memory access unit and at least one interface linked to the direct memory access and the microcontroller being able to implement transactions by way of the direct memory access unit or of the external master peripheral connected to the microcontroller, from and to a target area of a target interface of the microcontroller, said target interface being a private area of an application package on a memory external to the microcontroller, said microcontroller comprising at least one non-target interface, to which no transaction can be performed, said method comprising a step of verifying by way of logic pseudo-analysers the number of transactions on the said non-target interface, said number of transactions on the said non-target interface having to be zero.