Patent ID: 8023309

Claim:
A semiconductor memory device comprising: a stacked-layer film formed of a ferroelectric layer and a semiconductor layer; a first electrode formed on the ferroelectric layer of the stacked-layer film; and a plurality of second electrodes formed on the semiconductor layer of the stacked-layer film, wherein each of parts (A) of the semiconductor layer located in regions in which the second electrodes are formed, respectively, holds one of a first state in which majority carriers in the semiconductor layer are coupled with polarization charges in the ferroelectric layer and thereby a low resistance state is achieved and a second state in which minority carriers in the semiconductor layer are coupled with polarization charges in the ferroelectric layer and thereby a high resistance state is achieved, and part (B) of the semiconductor layer located in a region other than the regions in which the second electrodes are formed, respectively, holds a low resistance state in which majority carriers in the semiconductor layer are coupled with polarization charges in the ferroelectric layer.