Patent ID: 7996800

Claim:
A computer program product comprising computer executable instructions, stored on a computer readable medium, for a process of verifying whether a model of an integrated circuit satisfies its specification, the computer executable instructions comprising: computer executable instructions for performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit; computer executable instructions for unfolding the simplified sequential model for N time steps to produce a combinational model of the integrated circuit; computer executable instructions for performing a sequence of at least one combinational transformation on the combinational model to produce a simplified combinational model; and computer executable instructions for performing an exhaustive search of states of the simplified combinational model, wherein the computer executable instructions for performing the exhaustive search comprises computer executable instructions for performing an exhaustive satisfiability search, and wherein the computer executable instructions for performing an exhaustive satisfiability search includes computer executable instructions for propagating a binary decision diagram (BDD) through a netlist; and computer executable instructions for storing a result of the verifying process in response to i) performing a predetermined number of iterations of the verifying process, or else ii) the verifying process encountering a checkstop or no new states.