Patent ID: 7120912

Claim:
A method in a system comprising a computer having a plurality of host bus adapters (HBAs), a storage system having a first channel adapter (CHA) and a second CHA coupled to a first logical unit in the storage system, and a network coupled to the plurality of HBAs, the first CHA and the second CHA, the method comprising: identifying a first HBA of the plurality of HBAs used in a first access path, which is an active path from the computer to the first logical unit via the first CHA; selecting a second HBA of the plurality of HBAs which has a second load smaller than a first load of the first HBA; changing the active path into a second access path which is from the second HBA to the first logical unit via the first CHA after the second HBA is selected; and accessing the first logical unit via the second access path as the active path, wherein the first CHA has a cache memory for temporarily storing data to be stored into the logical unit of the storage system or to be sent from the storage system, and whereby the computer can continue to use the cache memory in the first CHA after changing the active path from the first access path to the second access path.