Patent ID: 6989659

Claim:
A liner voltage regulator comprising: an input terminal means for receiving power; an output terminal means for supplying current to a load; a common terminal means for receiving power and supplying power to said load; a depletion MOS first transistor having a drain, a source, and a gate, said source being coupled to said output terminal means and said gate being coupled to a first controlling signal; an enhancement MOS second transistor with a source, a drain and a gate, said source of said second transistor coupled to said input terminal means, said drain of said second transistor coupled to said drain of said first transistor and said gate of said second transistor coupled to a second controlling signal; wherein said depletion MOS first transistor constitutes the main element for regulating the voltage at said output terminal means; wherein said enhancement MOS second transistor constitutes the main element for limiting the current supplied to said output terminal means; and whereby said linear voltage regulator achieves a low dropout voltage.