Patent ID: 8394699

Claim:
A method of fabricating a memory array, comprising: forming alternating lines of active area regions and trench isolation regions within semiconductive material; etching a series of racetrack-shaped trenches into the active area regions and the trench isolation regions generally orthogonal to the alternating lines of active area regions and trench isolation regions; forming conductive material within the racetrack-shaped trenches to form a pair of electrically connected word lines in each of the racetrack-shaped trenches; forming source/drain regions within the active area regions laterally internal of the racetrack-shaped trenches and laterally external of the racetrack-shaped trenches; forming conductive data lines in electrical connection with the source/drain regions formed laterally external of the racetrack-shaped trenches; and forming charge storage devices in electrical connection with the source/drain regions formed laterally internal of the racetrack-shaped trenches.