Patent ID: 7277977

Claim:
A dynamic random access memory (DRAM) comprising: a plurality of normal banks, wherein a selected normal bank outputs at least two data continuously without restoring each data back to an original cell of the selected normal bank when continuous read commands are accessed to the selected normal bank; at least one cache bank, which has same data access scheme with the normal banks, for selectively storing the data outputted from a normal bank selected in response to a read command and a fast read command; and a controlling means for controlling an access to one of the cache banks and the plurality of normal banks and restoring the data that is outputted from the selected normal bank in response to the fast read command and stored in the cache bank into the original bank after a data access to the original bank is terminated, wherein the controlling means includes: an address comparing means for comparing if data corresponding to an address signal is in the cache bank or not; an access controlling means for controlling the data access of the cache bank and the normal banks according to the result from the address comparing means; a command decoding means for controlling the access controlling means; and a latching means for setting an output timing between a data control signal for controlling the normal bank or the cache bank in the access controlling means, and addresses outputted from the address comparing means.