Patent ID: 8321490

Claim:
A processor with instruction-based parallel median filtering comprising: a filtering core unit for receiving a plurality of inputs, the core including: a core-resident comparing circuit for sorting in parallel each combination of pairs of inputs into greater and lesser members; a core-resident decision circuit responsive to the sorting of the pairs of inputs to determine the minimum, maximum and median filter values of the inputs; and a core-resident processing circuit for processing one of the minimum, maximum and median filter values and providing the processed value as a core unit input; and a program sequencer for providing a first instruction for causing the core-resident decision circuit to provide one of the minimum, maximum and median filter values to the core-resident processing circuit, a second instruction for causing the core-resident decision circuit to indicate at least one of those values at a core unit output, and a third instruction for causing the core-resident decision circuit to indicate the others of those values at the output; wherein the program sequencer causes the core-resident decision circuit to execute the second and third instructions after the processed value has been provided to the filtering core unit.