Patent ID: 8495264

Claim:
A receiver (e.g., 100 ) comprising: serial-to-parallel (S-to-P) conversion circuitry (e.g., 110 , 130 ) configured to convert a serial input data stream (e.g., 105 ) having M-bit serial-data words into an N-bit parallel data stream (e.g., 137 ), wherein M and N are positive integers; and continuous alignment circuitry (e.g., 150 ) configured to correct for misalignment of the M-bit serial-data words within the N-bit parallel data stream to generate an N-bit aligned parallel output data stream (e.g., 175 ), wherein the continuous alignment circuitry is based on a mapping (e.g., Table I) from each of a finite number of possible previous alignment conditions (e.g., A, B, C, D) to a corresponding finite number of possible subsequent alignment conditions (e.g., B, C, D, E, F, G).