Patent ID: 8580650

Claim:
A process of forming an integrated circuit, comprising steps: providing a semiconductor substrate; forming an extended drain MOS transistor in and on said substrate, by a process including steps: forming a drift region in said substrate, said drift region having a first conductivity type; forming a plurality of deep SC RESURF trenches in said drift region, by a process including steps: forming an undersized trench in said drift region for each said deep SC RESURF trench; forming a semiconductor RESURF layer at a sidewall of said undersized trench contacting said drift region, by forming a counterdoped semiconductor RESURF layer of semiconductor RESURF material at a sidewall and a bottom of said undersized trench, so that said semiconductor RESURF layer has an opposite conductivity type from said drift region, so that a depth:width ratio of said deep SC RESURF trench is at least 5:1, and so that said deep SC RESURF trenches do not extend through said bottom surface of said drift region.