Patent ID: 8187939

Claim:
A method for making a shield gate trench semiconductor device, comprising: a) applying a trench mask as a first mask to a semiconductor substrate; b) etching the semiconductor substrate to form trenches TR 1 , TR 2 and TR 3 with three widths W 1 , W 2 and W 3 , respectively, wherein the trench TR 3 is widest and deepest and the width W 3 of the trench TR 3 depends on a depth D 2 of the trench TR 2 ; c) forming first conductive material at the bottom of the trenches TR 1 , TR 2 and TR 3 to form a source electrode; d) forming a second conductive material over the first conductive material in the trenches TR 1 and TR 2 to form a gate electrode, wherein the first and second conductive materials are separated from each other and from the semiconductor substrate by an insulator material; forming a dielectric layer on top of the source electrode in the trenches TR 1 , TR 2 and TR 3 ; chemical mechanical polishing and/or etching back the dielectric layer to a pre-determined thickness to form the inter-poly-dielectric layer; growing gate oxide on sidewalls of exposed portions of the trenches TR 1 , TR 2 and TR 3 ; and depositing the second conductive material into the trenches TR 1 , TR 2 and TR 3 to a pre-determined thickness to fill up the trenches TR 1 and TR 2 but does not fill completely the trench TR 3 ; e) depositing a first insulator layer on top of the trenches TR 1 , TR 2 and TR 3 , wherein a top portion of the trench TR 3 is filled up with the insulator; f) forming a body layer in a top portion of the substrate; g) forming a source layer in a top portion of the body layer; h) applying a second insulator layer on top of the trenches TR 1 , TR 2 and TR 3 and the source; i) applying a contact mask as a second mask on top of the second insulator laver; j) forming a source electrode contact in trench TR 3 , a gate electrode contact in trench TR 2 , and a source/body contact to the semiconductor substrate; and k) applying a metal mask as a third mask and forming source metal and gate metal on top of the second insulator layer.