Patent ID: 7392354

Claim:
An integrated circuit device, comprising: a multi-queue first-in first-out (FIFO) memory chip configured to support a plurality of independently addressable FIFO queues and a corresponding pair of read and write counter values associated with each of the plurality of FIFO queues, said FIFO memory chip further configured to support a backed-off standard mode of operation in at least one of the plurality of FIFO queues, said backed-off standard mode of operation configured to: enable automatic re-reading of at least one data word previously read from a first one of the plurality of FIFO queues in said FIFO memory chip during a first FIFO read operation, in response to a read queue-switch from a second one of the plurality of FIFO queues back to the first one of the plurality of FIFO queues; and generate a backed-off read counter value associated with the first one of the plurality of FIFO queues when performing a read queue-switch from the first one of the plurality of FIFO queues to another one of the plurality of FIFO queues.