Patent ID: 7689782

Claim:
A method comprising: fetching an instruction that comprises: a first set of one or more bits identifying the instruction; and a second set of one or more bits associated with a first address value; executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test; wherein: the second set of one or more bits is used in the determination of whether to perform the trap; the determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access; the selection of the at least one test is based at least in part on a configuration option; and the plurality of tests includes: a marking test based at least in part on a group of one or more marker bits included in the first address value; and a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein: the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits; and the plurality of managed memory types include garbage collection generation, heap, and stack.