Patent ID: 7295474

Claim:
An integrated circuit, comprising: a plurality of write word lines; a plurality of read word lines; a write bit line; a read bit line; a plurality of information storage cells, each cell having a first transistor and a second transistor, an input electrode of the first transistor in one of the cells being coupled to a respective one of the write word lines, and an output electrode of the first transistor being coupled to the write bit line, an input electrode of the second transistor being coupled to another output electrode of the first transistor, an output electrode of the second transistor being coupled to a respective one of the read word lines, and another output electrode of the second transistor being coupled to the read bit line; and conditioning circuitry to force one of the read word lines towards a power supply or power return voltage of the array, in response to a read command, but stop substantially short of said voltage, wherein the first and second transistors are p-channel field effect transistors, and the conditioning circuitry is to force the read word line towards the power supply voltage and stop more than two transistor source-drain drops below the power supply voltage.