Patent ID: 7576431

Claim:
A semiconductor chip package, comprising: a semiconductor chip having a rectangular main surface, wherein the rectangular main surface has a first side and a second side opposite to the first side; a plurality of first electrode pads which is provided on the main surface along the first side; a plurality of second electrode pads which is provided on the main surface along the second side; a plurality of central bonding pads which is provided between the first electrode pads and the second electrode pads on the main surface, wherein the central bonding pads are located near the first electrode pads; a plurality of first bonding pads which is provided between the first side and the first electrode pads on the main surface, wherein the first bonding pads are provided along the first side; a plurality of second bonding pads which is provided between the second side and the second electrode pads on the main surface, wherein the second bonding pads are provided along the second side; a plurality of first redistribution wiring layers which electrically connects the first electrode pads, first central bonding pads which are included in the plurality of central bonding pads, and the first bonding pads in a one-to-one correspondence relationship, respectively; a plurality of second redistribution wiring layers which electrically connects the second electrode pads, second central bonding pads which are included in the plurality of central bonding pads, and the second bonding pads in a one-to-one correspondence relationship, respectively; and an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second central bonding pads and top faces of the first and second bonding pads to be exposed.