Patent ID: 8359173

Claim:
A process for dynamic timing-dependent power estimation for a digital circuit having coupled interconnects and at least two gates, comprising the steps of: (a) capturing information on relative switching activities and timing dependence for the coupled interconnects in the digital circuit; (b) storing the captured information in a memory; (c) estimating the probabilities associated with switching activities and timing dependence for each gate in the digital circuit from the captured information; (d) obtaining dynamic power estimation of the digital circuit from the estimations of the probabilities, wherein the step of estimating the probabilities associated with switching activities and timing dependence comprises calculating the probability that a particular switching activity occurs at a specific time, for each gate in the digital circuit, and, wherein the step of calculating the probability that a particular switching activity occurs at a specific time comprises calculating the relative switching probability for rise, fall, stay low, and stay high, for each gate of the digital circuit.