Patent ID: 7880297

Claim:
A semiconductor chip, comprising: a packaging substrate; and an integrated circuit die mounted on a first side of the packaging substrate, the integrated circuit die comprising: a semiconductor substrate; a plurality of inter-metal dielectric (IMD) layers on the semiconductor substrate; a plurality of levels of metal interconnection in the respective IMD layers, wherein at least two potential equivalent metal traces are formed in one level of the metal interconnection; a passivation layer covering the at least two potential equivalent metal traces, wherein two openings are formed in the passivation layer to expose portions of the at least two potential equivalent metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer (RDL) formed over the conductive member, wherein the RDL fills into the two openings such that the potential equivalent metal traces are electrically connected to each other through the RDL and the conductive member.