Patent ID: 7085162

Claim:
A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix and which includes a plurality of blocks, each of said blocks having memory cells connected to one word line or a plurality of word lines; and a row decoder circuit configured to select a word line in said memory cell array, said row decoder circuit including: a first transistor of a first conductivity type, a source or a drain of said first transistor being connected to a corresponding one of said word lines; and a second transistor of a second conductivity type, opposite to the first conductivity type, wherein said first transistor applies voltage to said word line, and a source or a drain of said second transistor is connected to a gate of said first transistor, and when a word line in a selected block is biased to a first voltage which is higher than a power supply voltage, said second transistor applies a second voltage to said gate of said first transistor, and said second voltage is higher than the first voltage.