Patent ID: 7977736

Claim:
A semiconductor memory device comprising: a substrate including a memory core area and a peripheral circuit area; and a first NMOS vertical channel transistor, a second NMOS vertical channel transistor, and a PMOS vertical channel transistor located in the memory core area of the substrate; wherein the first NMOS vertical channel transistors includes a p+ poly-silicon gate electrode surrounding a vertical p-channel region, the second NMOS vertical channel transistor includes an n+ poly-silicon gate electrode surrounding a vertical p-channel region, and the PMOS vertical channel transistor includes an n+ poly-silicon gate electrode surrounding a vertical n-channel region, wherein a threshold voltage of the first NMOS vertical channel transistor is positive, and threshold voltages of the second NMOS vertical channel transistor and the PMOS vertical channel transistor are negative, and wherein the first NMOS and PMOS vertical channel transistors are operable in a CMOS operational mode.