Patent ID: 7961837

Claim:
A counter circuit comprising: a first flip-flop that is inactive when any one of a counter enable signal by the numerical value of 2, a counter enable signal by the numerical value of 4, and a counter enable signal by the numerical value of 8 is enabled; a second flip-flop that is inactive when the counter enable signal by the numerical value of 4 or the counter enable signal by the numerical value of 8 is enabled; a third flip-flop that is inactive when the counter enable signal by the numerical value of 8 is enabled; and a control unit that generates first to third control signals that activate the first to third flip-flops in response to the counter enable signal by the numerical value of 2, the counter enable signal by the numerical value of 4, and the counter enable signal by the numerical value of 8 and carries transmitted from the first and second flop-flops, wherein the control unit includes: a first multiplexer that includes a first input terminal to which the counter enable signal by the numerical value of 1 is input, a second input terminal connected to a ground terminal, and a control terminal to which the counter enable signal by the numerical value of 2 is input and that outputs the first control signal in response to the counter enable signal by the numerical value of 2, a second multiplexer that includes a first input terminal to which the counter enable signal by the numerical value of 1 is input, a second input terminal connected to the ground terminal, and a control terminal to which the counter enable signal by the numerical value of 4 is input, and that outputs a signal in response to the counter enable signal by the numerical value of 4, a third multiplexer that includes a first input terminal to which a carry of a last digit is input, a second input terminal to which the signal output of the second multiplexer is input, and a control terminal to which the counter enable signal by the numerical value of 2 is input, and that outputs the second control signal in response to the counter enable signal by the numerical value of 2, a fourth multiplexer that includes a first input terminal to which the counter enable signal by the numerical value of 1 is input, a second input terminal connected to the ground terminal, and a control terminal to which the counter enable signal by the numerical value of 8 is input, and that outputs a signal in response to the counter enable signal by the numerical value of 8, and a fifth multiplexer that includes a first input terminal to which a carry of a digit before the last digit is input, a second input terminal to which the signal output of the fourth multiplexer is input, and a control terminal to which the counter enable signal by the numerical value of 4 is input, and that outputs the third control signal in response to the counter enable signal by the numerical value of 4.