Patent ID: 7179714

Claim:
A method of fabricating a MOS transistor comprising: forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked; forming source/drain regions by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks; forming a protecting layer on the semiconductor substrate having the gate pattern; planarizing the protecting layer, the gate pattern, and the gate spacers until the insulating layer pattern is exposed, wherein the planarized protecting layer, the planarized gate pattern, and the planarized gate spacers are at substantially the same height relative to the substrate; removing the insulating layer pattern, thereby exposing the lower gate pattern; selectively removing the protecting layer, thereby exposing the source/drain regions; and fully converting the exposed lower gate pattern to a gate silicide layer and concurrently forming a silicide layer on the surfaces of the source/drain regions.