Patent ID: 8099448

Claim:
A system, comprising: a first data path comprising an arithmetic logic unit, a data cache, a multiplexer, and a programmable shifter device; a second data path comprising the arithmetic logic unit, the multiplexer, and the programmable shifter device; wherein in an address generation mode, data flows from the arithmetic logic unit through the data cache, the multiplexer, and the programmable shifter device to a register file via the first data path; wherein in an arithmetic mode, data flows from the arithmetic logic unit through the multiplexer and the programmable shifter device to the register file via the second data path in response to a common control signal provided from an instruction cache to the arithmetic logic unit, the multiplexer, and the programmable shifter device; wherein the multiplexer has a first multiplexer input to receive an arithmetic output from the arithmetic logic unit, a second multiplexer input to receive data from the data cache, and a control multiplexer input to receive the common control signal; and wherein the arithmetic output received in the arithmetic mode includes data resulting from an arithmetic operation performed by the arithmetic logic unit and bits that indicate an amount the resulting arithmetic operation data is to be shifted by the programmable shifter device.