Patent ID: 8830097

Claim:
An A/D converter comprising: a modulator configured to perform delta-sigma modulation of a differential analog signal; and a decimation filter configured to generate digital data on the basis of an output of the modulator, wherein the modulator comprises at least one arithmetic operation circuit configured to alternately repeat a sampling state and an arithmetic operation state including: a first capacitor and a second capacitor each of which samples an input signal; a third capacitor and a fourth capacitor each of which has a first electrode connected to a first electrode of the first capacitor and configured to perform sampling of a first reference voltage or a second reference voltage different from the first reference voltage; a fifth capacitor and a sixth capacitor each of which has a first electrode connected to a first electrode of the second capacitor and configured to perform sampling of the first reference voltage or the second reference voltage; and the arithmetic operator configured to obtain a first addition or subtraction result by performing addition or subtraction between charge sampled by the first capacitor and charge sampled by the third capacitor and the fourth capacitor, and configured to obtain a second addition or subtraction result by performing addition or subtraction between charge sampled by the second capacitor and charge sampled by the fifth capacitor and the sixth capacitor, and thereby integrates the first addition or subtraction result to output a first integration result, and integrates the second addition or subtraction result to output a second integration result, wherein in an addition state of the arithmetic operation state, a second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and a second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, wherein in a subtraction state of the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and wherein in the sampling state, the second electrode of each of the third capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of each of the fourth capacitor and the fifth capacitor is connected to the second reference voltage.