Patent ID: 8889513

Claim:
A method of manufacturing a semiconductor power device comprising: (a) forming a plurality of trenches in an epitaxial layer of first conductivity type; (b) depositing a HDP oxide on trench sidewall, and bottom, and top surface of said mesa area wherein said trench sidewall has thinner oxide than said trench bottom and said mesa area; (d) removing, using wet etching, the oxide on trench sidewall completely, and the oxide on trench bottom and said mesa area partially wherein a remaining oxide and said pad oxide on trench bottom defined as bottom oxide layer; (e) depositing a photo resist filled into said trenches and top surface of said mesa area; (f) removing a portion of said photo resist from top surface of said mesa area to expose said portion of surface area of said oxide on said mesa area where said oxide layer can be removed; (g) removing said oxide on said top surface of said mesa area completely; (h) forming a gate oxide on trench sidewall; and (i) forming trenched gates, trenched floating gates, body regions, source regions and trenched source-body contact in said epitaxial layer.