Patent ID: 7123068

Claim:
A flip-flop, comprising: a master latch that has a signal terminal for receiving an input signal, a control input for receiving a clock signal, and an output; an output circuit having an input coupled to the output of the master latch and having an output that provides an output of the flip-flop; a slave latch coupled to the output of the master latch, the slave latch comprising: a first switch having a first signal terminal coupled to the output of the master latch, a second signal terminal, and a control input that receives a power down signal; a first inverting circuit having an input coupled to the second signal terminal of the first switch and an output; a second inverting circuit having an input coupled to the output of the first inverting circuit and an output; a second switch having a first signal terminal coupled to the input of the first inverting circuit, a second signal terminal coupled to the output of the second inverting circuit, and a control input for receiving the clock signal; and a third switch having a first signal terminal coupled to the input of the first inverting circuit, a second signal terminal coupled to the output of the second inverting circuit, and a control input for receiving the power down signal.