Patent ID: 7015535

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of memory cells, each of which includes: a first conductive type of semiconductor substrate; first and second diffusion layers formed on the semiconductor substrate, the diffusion layers being of a second conductive type; a channel region formed between the first and second diffusion layers; a gate insulating layer formed on the channel region; a gate electrode formed on the gate insulating layer; a first variable resistance region, which is formed outside the first diffusion layer and is of the second conductive type; a second variable resistance region, which is formed outside the second diffusion layer and is of the second conductive type; wherein a couple of bits of data are stored in the memory cell, the stored data being controlled according to resistance values of the first and second variable resistance regions, wherein one of the memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell, wherein the first diffusion layers of the plurality of memory cells are coupled to each other with a first conductive line extending in a first direction, wherein the second diffusion layers of the plurality of memory cells are coupled to each other with a second conductive line extending in the first direction, and wherein the gate electrodes of the plurality of memory cells are coupled to each other with a third conductive line extending in a second direction, which is orthogonal to the first direction.