Patent ID: 8441589

Claim:
A pixel array structure, comprising: a plurality of scan lines; a plurality of data lines, wherein the scan lines and the data lines intersect with each other so as to define a plurality of pixel regions; a plurality of first active devices, electrically connected to the data lines and the scan lines; a plurality of second active devices, electrically connected to the data lines and the scan lines; a plurality of first pixel electrodes, disposed in the pixel regions, electrically connected to the first active devices, wherein each of the first pixel electrode comprises a first electrode block and a second electrode block electrically connected to each other; a plurality of second pixel electrodes, disposed in the pixel regions, electrically connected to the second active devices, the second pixel electrodes being electrically insulated from the first pixel electrodes, and the second pixel electrodes separating the first electrode blocks and the second electrode blocks; a plurality of first capacitance electrodes, wherein each of the first capacitance electrodes has different patterns in the adjacent pixel regions; and a plurality of second capacitance electrodes, disposed between the first capacitance electrodes and the scan lines, wherein each of the second capacitance electrodes has different patterns in the adjacent pixel regions, wherein a first overlapping region between each of the first pixel electrodes and the corresponding first capacitance electrode forms a first capacitor, a second overlapping region between each of the first pixel electrodes and the corresponding second capacitance electrode forms a second capacitor, a third overlapping region between each of the second pixel electrodes and the corresponding first capacitance electrode forms a third capacitor, a fourth overlapping region between each of the second pixel electrodes and the corresponding second capacitance electrode forms a fourth capacitor, and an overlapping area of the first overlapping region is different from that of the second overlapping region such that the first capacitor and the second capacitor have different capacitances, and an overlapping area of the third overlapping region is different from that of the fourth overlapping region such that the third capacitor and the fourth capacitor have different capacitances.