Patent ID: 7590831

Claim:
A data processing system comprising a loop accelerator which processes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a storage which transmits data between the processor core and the loop accelerator, wherein the loop accelerator comprises: a plurality of processing elements (PEs), each of which performs an operation on each word to process the program; a configuration memory which stores configuration bits indicating configuration information of the PEs; and a plurality of context memories installed in one of column and row directions of the PEs, wherein the plurality of context memories transmits the configuration bits provided from the configuration memory along a direction toward which the PEs are arrayed, wherein each of the context memories comprises: a shift register which temporarily stores the configuration bits provided from the configuration memory; a counter which counts a number of configuration bits provided to the shift register; and a comparator which compares the number of configuration bits with a number of the PEs.