Patent ID: 8415738

Claim:
A semiconductor memory device comprising: a first bit line and a first word line orthogonal to each other; first to fourth semiconductor pillars each having a sidewall, a top end and a bottom end; first to fourth memory elements connected to the top end of the first to fourth semiconductor pillars, respectively; first to fourth gate electrodes covering the sidewall of the first to fourth semiconductor pillars, respectively via a gate insulating film interposed therebetween, wherein the first and second semiconductor pillars are adjacent to each other with the first bit line interposed therebetween, the third and fourth semiconductor pillars are adjacent to each other with the first bit line interposed therebetween, the first and third semiconductor pillars are adjacent to each other with the first word line interposed therebetween, the second and fourth semiconductor pillars are adjacent to each other with the first word line interposed therebetween, the first bit line is electrically connected to the bottom ends of the third and fourth semiconductor pillars, and the first word line is electrically connected to the first and third gate electrodes; and the first bit line is free from being electrically connected to the bottom ends of the first and second semiconductor pillars, and the first word line is free from being electrically connected to the second and fourth gate electrodes.