Patent ID: 8739089

Claim:
A method to debug a register transfer level (RTL) design in a FPGA-based emulation or co-emulation system, the method comprising steps of: instrumenting the RTL design by inserting at least one dummy module for correlating a set of signals of the RTL design to a corresponding set of gate-level signals; synthesizing the instrumented RTL design to generate a gate-level netlist targeting for the FPGA-based emulation or co-emulation system, wherein the set of signals of the RTL design is correlated to the corresponding set of gate-level signals through the at least one dummy module; fitting the gate-level netlist into at least one field programmable gate array (FPGA) device in the FPGA-based emulation or co-emulation system and generating location information of instances of the-gate-level netlist in the at least one FPGA device, wherein each of the at least one dummy module has no corresponding instance implemented in the at least one fitted FPGA device; and extracting values of gate-level signals corresponding to the set of signals of the RTL design in an emulation or co-emulation run, wherein said values of the gate-level signals are obtained according to the location information of the instances that output the corresponding set of gate-level signals in the FPGA-based emulation or co-emulation system.