Patent ID: 8675427

Claim:
A circuit for implementing delay improvement in static random access memory (SRAM) including a precharge signal and respective wordline signals extending from a source near end to a distal far end of the SRAM, said circuit comprising: a precharge enable signal; said precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals at proximal and distal ends of the SRAM; a precharge pull down device coupled between said precharge far signal and ground; said precharge pull down device being controlled responsive to said precharge enable signal to decrease a time delay of a falling transition of said precharge far signal; and a respective word line pull up device coupled between a respective wordline far signal and a voltage supply rail; said respective word line pull up device being controlled responsive to said precharge enable signal to increase wordline voltage level upon a rising transition of said respective wordline far signal.