Patent ID: 8311077

Claim:
A modulator comprising: a code modulating unit to receive transmitted data to perform code modulation on the data and to output a code-modulated data signal; a gain control signal generating unit to generate a gain control signal; and a filter unit to receive said code-modulated data signal from said code modulating unit to perform bandwidth limitation on the received code-modulated data signal and to output a bandwidth-limited signal, wherein said filter unit comprises: a time-series data generating unit to output time-series data having a plurality of signals containing past inputted signals, and to perform shifting processing; a coefficient setting unit to set a plurality of filter weighting coefficients in accordance with the value of the gain control signal received from the gain control signal generating unit, setting of the filter weighting coefficients associated with the shifting processing of each of the plurality of signals of the time-series data outputted by said time-series data generating unit; and a gain control unit to control a gain according to the plurality of filter weighting coefficients set by said coefficient setting unit, wherein said filter unit further comprises: a shift register section to perform shifting processing on an inputted signal and to output the time-series data made up of the plurality of signals containing past inputted signals; a shift register to receive the gain control signal from said gain control signal generating unit to perform shifting processing on the received gain control signal and to output a time-series gain control data consisting of a plurality of signals containing past gain control signals; a plurality of multipliers to multiply each of the plurality of signals outputted from said shift register by each of a plurality of specified first and second coefficients and to output a plurality of first and second weighting coefficients; a plurality of register sections to receive the first and second weighting coefficients outputted from said plurality of multipliers to store the first and second weighting coefficients to switch one of the first and second weighting coefficients in accordance with the plurality of signals outputted from said shift register section and to output the filter weighting coefficients; and an adder to add outputs from said plurality of register sections.