Patent ID: 8158520

Claim:
A method for processing integrated circuit devices, the method comprising: providing a substrate; forming a dielectric layer directly overlying the substrate; forming a metal interconnect in direct contact with the dielectric layer; forming a first interlayer dielectric layer surrounding the metal interconnect; forming a capping layer overlying the metal interconnect and the first interlayer dielectric layer; forming a second interlayer dielectric layer of a predetermined thickness overlying the first interlayer dielectric layer, the second interlayer dielectric layer being made of a single dielectric layer; forming a trench opening of a first width within an upper portion of the second interlayer dielectric layer, the upper portion being a portion of the predetermined thickness of the second interlayer dielectric layer and not through the predetermined thickness; forming a first barrier layer lining a sidewall surface and a bottom portion of the trench opening of the first width, the first barrier layer comprising tantalum overlying tantalum nitride; forming a contact opening of a second width within a lower portion of the second interlayer dielectric layer and through the trench opening, the second width being less than the first width, the lower portion of the second interlayer dielectric layer being coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric layer, the contact opening exposing a portion of a surface of the metal interconnect; forming a second barrier layer within and overlying the opening of the contact opening and overlying the first barrier layer lining the sidewall surface of the trench opening, the first barrier layer and the second barrier layer substantially overlying an interior portion of the trench, the second barrier layer overlying the contact opening including the exposed portion of the top surface of the metal interconnect and the exposed portion of the lower portion of the second interlayer dielectric layer; thinning away a contact portion of the second barrier layer along the top surface of the metal interconnect using a blanket etching process; and forming a copper material overlying the first barrier layer and the second barrier layer including the thinned contact portion of the second barrier layer along the top surface of the metal interconnect to substantially fill the contact opening and the trench within the second interlayer dielectric layer.