Patent ID: 7565638

Claim:
A computer implemented method, comprising: using a computer processor to perform: accessing a configuration file, wherein the configuration file comprises: a minimum density design rule for a design layer of an integrated circuit design layout, wherein the design layer comprises an encoded representation to be used in fabrication of the integrated circuit; and an identifier specifying an area of the design layout on which to operate; generating a run deck dependent on the configuration file, wherein the run deck comprises program instructions executable to perform a density-based layer filling operation on the area of the design layout specified by the identifier; executing the program instructions comprised in the run deck to perform the density-based layer filling operation; wherein the density-based layer filling operation comprises: identifying a portion of the specified area of the design layout in which the minimum density design rule for the design layer is not met; constructing one or more dummy shapes to be added on the design layer; and inserting the one or more dummy shapes into the design layout only in the identified portion of the specified area; wherein inserting the one or more dummy shapes results in the minimum density design rule for the design layer being met in the identified portion of the specified area.