Patent ID: 7334152

Claim:
A clock switching circuit comprising: a composite clock generation circuit, which is to receive a first clock, a second clock whose frequency is different from that of the first clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the second clock fixed to be a second level and to output the second clock as a composite clock for clock switching, for a specified period including one of a leading edge and a trailing edge of the first clock as well as additional time before and after the edge, when the clock switching execution signal becomes active while the second clock is at a first level; a switching demand signal generation circuit that receives the composite clock for clock switching and the clock switching execution signal, and outputs a clock switching demand signal; a clock selection signal generation circuit that changes a level of a first clock selection signal when the switching demand signal becomes active; and a first selector that selects one of the first clock and the composite clock for clock switching, according to the level of the first clock selection signal which comes from the clock selection signal generation circuit, and outputs the selected clock.