Patent ID: 7028168

Claim:
A system for executing matrix operation instructions, comprising: a processor having a memory cache, the processor configured to execute a matrix operation instruction; memory external to the processor, the memory storing first and second matrices; and a matrix operation manager configured to perform a matrix operation by mathematically combining the first matrix with the second matrix utilizing a hoisted matrix algorithm for hoisting values of the first matrix, the hoisted matrix algorithm having an outer loop and an inner loop that is performed to completion for each iteration of the outer loop, the matrix operation manager, for each iteration of the outer loop, configured to load to the cache and to write to a contiguous portion of the memory, before performing the inner loop, values from the first matrix that are to be combined, via performance of the inner loop, with values from the second matrix, wherein the matrix operation manager is configured to load, from the contiguous portion of the memory that is external to the processor, at least one of said values from the first matrix in response to at least one cache miss resulting from performance of the inner loop, and wherein the processor, in executing the matrix operation instruction, is configured to cause the matrix operation manager to perform the matrix operation.