Patent ID: 7906398

Claim:
A method of fabricating a semiconductor device on a substrate, the method comprising: forming at least one pillar pattern having a pillar head and a pillar neck on the substrate; forming a gate insulation layer that surrounds the pillar neck; forming a conductive layer over the substrate having the gate insulation layer on the pillar neck; and forming a gate electrode that surrounds the gate insulation layer on the pillar neck by performing multiple etching processes on the conductive layer, wherein the multiple etching processes performed on the conductive layer comprise: an isotropic etching process performed on a portion of the conductive layer exposed from a sacrificial layer pattern partially filling a gap between adjacent pillar patterns; a first anisotropic etching process performed on both the isotropically-etched conductive layer and the sacrificial layer pattern; and a second anisotropic etching process performed, after the sacrificial layer pattern has been removed, on the once-anisotropically-etched conductive layer to obtain the gate electrode.