Patent ID: 8675385

Claim:
A semiconductor device comprising: a substrate; a first semiconductor device including a first insulation film formed over the substrate, a first electrode formed over the first insulation film, and a first diffusion layer that is formed over the substrate and is adjacent to at least the first electrode in a planar view; a second semiconductor device including a second insulation film formed over the substrate, a second electrode that is formed over the second insulation film and is adjacent to the first electrode, and a second diffusion layer that is formed over the substrate and is adjacent to at least the second electrode in a planar view; a bit line; a word line; a control transistor having one of a source and a drain coupled to the first electrode and the second electrode, the other one of a source and a drain coupled to the bit line, and a gate electrode coupled to the word line; a first potential control section that controls a potential of the first diffusion layer; and a second potential control section that controls a potential of the second diffusion layer, wherein a contact is coupled to the first diffusion layer and is not provided for at least one of a plurality of first regions included in the first diffusion layer divided by the first electrode.