Patent ID: 8159884

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell transistor configured to electrically rewrite data; a word line connected to a gate of the memory cell transistor; a row decoder which applies a read voltage to the word line; a bit line connected to a drain of the memory cell transistor; a sense amplifier which determines the data in the memory cell transistor via the bit line; a first bit line clamp transistor connected in series between the bit line and the sense amplifier; a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor; and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.