Patent ID: 7205225

Claim:
Method of manufacturing a semiconductor device with a semiconductor body and a substrate comprising at least one semiconductor element and provided with at least one connection region and an overlying stripe-shaped connection conductor connected to the connection region which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer, a hard mask layer, and a second dielectric layer are deposited on the semiconductor body, where at the location of the connection region to be formed, a via is formed in the first dielectric layer by plasma etching using a plasma containing a compound of carbon and fluorine, and in the presence of a patterned photoresist layer deposited on top of the connection region and at the location of the connection conductor to be formed, a trench is formed in the second dielectric layer by plasma etching, which via and trench are filled with an electrically conducting material in order to form, respectively, the connection region and the connection conductor, and where before the trench is formed, the already formed via is filled with an organic material, characterized in that the material of the first dielectric layer and the etch conditions during formation of the via in the first dielectric layer by plasma etching are chosen such that during etching the via, said via is at the same time substantially completely filled with the organic material, the organic material being formed from organic material already present within the already formed via and within the plasma, wherein the organic material in the via acts as a sacrificial material thereby protecting the via during plasma etching and during trench formation, resulting in enhanced dimensional integrity of the via and trench structure.