Patent ID: 8913432

Claim:
A method for programming transistors, comprising: performing each program-verify iteration of a plurality of program-verify iterations for a set of transistors which are to be programmed in a programming operation, the set of transistors is in a memory device, the memory device comprises a plurality of memory cells formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the plurality of memory cells comprise columnar active areas, each transistor initially has a program status which indicates that the transistor is to be programmed, and the performing each program-verify iteration comprises applying a program pulse to the set of transistors, determining whether a threshold voltage of at least some of the transistors with the program status exceeds a lockout verify voltage and changing the program status to a lockout status for a remainder of the programming operation for each of the transistors for which the threshold voltage is determined to exceed the lockout verify voltage, the lockout verify voltage is stepped up in multiple program-verify iterations of the program-verify iterations for the set of transistors.