Patent ID: 8338891

Claim:
A MOSFET arrangement, comprising: at least two MOSFETs provided on a chip, wherein the chip includes a first terminal, a second terminal and a third terminal, wherein at least one first MOSFET is used as a control cell and at least one second MOSFET is used as a power cell, and wherein the at least one first MOSFET and the at least one second MOSFET each have a gate terminal, a source terminal and a drain terminal; wherein the source terminals of the at least one first MOSFET and the at least one second MOSFET are connected to one another and contact the first terminal of the chip; wherein the drain terminal of the at least one second MOSFET contacts the second terminal of the chip; wherein the gate terminals of the at least one first MOSFET and the at least one second MOSFET are connected to one another and directly contact the third terminal of the chip; and wherein the gate terminal and the drain terminal of the at least one first MOSFET are connected to each other.