Patent ID: 7148567

Claim:
A semiconductor integrated circuit device, comprising: a first semiconductor integrated circuit chip having a first electrode pad and a second electrode pad thereon; a second semiconductor integrated circuit chip having a third electrode pad, a fourth electrode pad, a fifth electrode pad, a sixth electrode pad, a first wire electrically connecting the third electrode pad with the fourth electrode pad and a second wire electrically connecting the fifth electrode pad with the sixth electrode pad; first and second leads; a first bonding wire electrically connecting the first electrode pad with the third electrode pad; a second bonding wire electrically connecting the second electrode pad with the fifth electrode pad; a third bonding wire electrically connecting the fourth electrode pad with the first lead; and a fourth bonding wire electrically connecting the sixth electrode pad with the second lead, wherein the second semiconductor integrated circuit chip is arranged between the first semiconductor integrated circuit chip and the two leads, wherein the first, second, third and fourth bonding wires do not straddle the second semiconductor integrated circuit chip, and wherein the first wire crosses over the second wire.