Patent ID: 8729565

Claim:
A semiconductor device, comprising: a heterostructure that includes a channel layer extending in a longitudinal direction, a first portion of the channel layer being located on a mesa and a second portion of the channel layer being located off the mesa; a series of interdigitated gate, source and drain electrodes extending in the longitudinal direction and being disposed over the first portion of the channel layer located on the mesa, the source and drain electrodes extending in the longitudinal direction beyond an edge of the mesa and extending over the second portion of the channel layer, the gate electrodes extending along a sidewall of the mesa; a source pad located off the mesa; a conductive source interconnect having a first portion electrically connected to one of the source electrodes and a second portion electrically connected to the source pad; a gate pad located off the mesa and overlapping the source pad at least in part; and a conductive gate interconnect having a first portion electrically connected to a portion of the gate electrode extending along the mesa sidewall, the conductive gate interconnect having a second portion electrically communicating with the gate pad.