Patent ID: 8525229

Claim:
A semiconductor device, comprising: a channel layer; an electron-supplying layer provided on said channel layer; a cap layer, provided on said electron-supplying layer and creating lattice match with said channel layer; and an ohmic electrode provided on said cap layer, wherein said cap layer has a composition of (In y Al 1-y ) z Ga 1-z N where (0≦y≦1, 0≦z≦1), wherein a boundary surface between said electron-supplying layer and said cap layer contains at least In, and in said cap layer a ratio of InAlN in the (In y Al 1-y ) z Ga 1-z N decreases from said boundary surface to a side of said cap layer opposite said boundary surface, wherein said electron-supplying layer has a composition of (In u Al 1-u ) x Ga 1-x N (0≦u≦1, 0<x≦1), wherein said cap layer creates lattice match with both said channel layer and said electron-supplying layer, wherein said semiconductor device further comprises a gate electrode coupled to said electron-supplying layer, said gate electrode constituting a hetero junction field effect transistor, and wherein said ohmic electrode functions as a source electrode or a drain electrode of said hetero junction field effect transistor.