Patent ID: 8841725

Claim:
A semiconductor device comprising: a semiconductor substrate having a first transistor region in which a first transistor of a first conductivity type having a source region and a drain region is formed; a first gate electrode formed in the first transistor region; an insulating offset mask that extends from and in contact with a side wall and an upper surface of a drain-side of the first gate electrode to the drain region to cover a first part of the drain region, the insulating offset mask being made of a first insulating film; a first side wall spacer formed at a side wall of a source-side of the first gate electrode, the first side wall spacer being made of the first insulating film; a channel dose region of a second conductivity type that is a conductivity type opposite to the first conductivity type, the channel dose region extends from the source region to a position under the first gate electrode, and the channel dose region having a first depth under the source region and having a second depth under the first gate electrode, and the second depth being shallower than the first depth; and a first source extension region of the first conductivity type, the first source extension region being shallower than the channel dose region of the second conductivity type and being formed in overlapping the source region.