Patent ID: 7518241

Claim:
A wafer structure, comprising: a semiconductor substrate having an active surface, wherein the semiconductor substrate has a plurality of bonding pads positioned on the active surface and a passivation layer, which covers the active surface exposes the bonding pads; a plurality of UBM layers disposed on the bonding pads, wherein each of the UBM layers comprises: an adhesive layer disposed on the bonding pads; a super-lattice barrier layer disposed on the adhesive layer, wherein the super-lattice barrier layer comprises a plurality of alternately stacked sub-barrier layers and sub-wetting layers; a welling layer disposed on the super-lattice barrier layer; and a plurality of bumps disposed on the wetting layer, wherein the thickness of the welling layer is Y 1 , the overall thickness of the sub-wetting layers adds up to Y 2 , and the quotient of Y 1 /Y 2 ranges between 1 and 2.