Patent ID: 7573077

Claim:
A thyristor-based semiconductor memory device, comprising: a supporting substrate comprising at least one of semiconductor material and conductor material; dielectric layered on the supporting substrate; a layer of silicon disposed on the dielectric; the layer of silicon comprising doped regions of opposite sequential polarity that define a thyristor; a wordline electrode disposed in insulated relationship over a base region of the thyristor; a MOSFET with source, body and drain regions formed in at least a further portion of the layer of silicon over the dielectric, the drain region of the MOSFET physically shared in common, contiguous relationship with a cathode-emitter region of the thyristor; and a bias circuit electrically coupled to the supporting substrate to enable application of a given voltage to the supporting substrate when the memory device is operating; wherein at least a portion of the supporting substrate is conductively and operatively configured to enable receipt and delivery of the given applied voltage to a location beneath the thyristor to impart a back-side bias electric field effect to the thyristor when the bias circuit applies the given voltage to the supporting substrate.