Patent ID: 7639529

Claim:
A non-volatile memory device, comprising: a memory array having at least one row of three-state memory cells therein that are grouped in pairs to provide 3-bit data storage per pair, said at least one row comprising a first pair of first and second non-volatile memory cells extending immediately adjacent a second pair of first and second non-volatile memory cells; and a program control circuit electrically coupled to said memory array, said program control circuit configured to support mirror-image programming of the first and second pairs of non-volatile memory cells so that the threshold voltages in the first and second non-volatile memory cells of the first pair are mirror images of the threshold voltages in the first and second non-volatile memory cells of the second pair whenever the first and second pairs of non-volatile memory cells are storing the same 3-bit data containing at least one programmed bit and the threshold voltages of the first and second non-volatile memory cells in each of the first and second pairs of non-volatile memory cells are unequal; said program control circuit further configured to concurrently drive two pairs of bit lines associated with the first and second pairs of non-volatile memory cells in said memory array with bit line voltages during said mirror-image programming and readout data from the first and second pairs of non-volatile memory cells by concurrently transferring data from the first and second pairs of non-volatile memory cells to the two pairs of bit lines.