Patent ID: 7109812

Claim:
An apparatus for presenting a capacitive output at at least one output locus in response to receiving a voltage input at an input locus; said voltage input varying over a voltage range; the apparatus comprising: (a) a plurality of switching units coupled with said input locus; and (b) a plurality of capacitive units coupled with selected switch units of said plurality of switch units and with a respective output locus of said at least one output locus; each respective switch unit of said plurality of switch units being configured to conduct in response to said voltage input over a respective range-portion of said voltage range; said capacitive output being substantially linearly variable with respect to said voltage input over a segment of said voltage range spanning a plurality of said range-portions, wherein said plurality of switching units is a plurality of MOS transistor; each respective MOS transistor having a respective gate coupled with said input locus, and wherein each respective MOS transistor has a respective source and a respective drain; each respective capacitive unit of said plurality of capacitive units being coupled between a respective said drain and a respective output locus of said at least one output locus.