Patent ID: 8644035

Claim:
A DC-to-DC full bridge converter circuit comprising: a leading leg comprising: a first transistor; a second transistor; a lagging leg comprising: a third transistor; a fourth transistor; a first auxiliary circuit comprising: a first capacitor coupled between a first node and a second node; a second capacitor coupled between said second node and a third node; a first auxiliary inductor coupled between said second node and a fourth node; a second auxiliary circuit comprising: a third capacitor coupled between said first node and a fifth node; a fourth capacitor coupled between said third node and said fifth node; a second auxiliary inductor coupled between said fifth node and a sixth node; wherein said first node is coupled to a drain of said first transistor and a drain of said third transistor; said third node is coupled to a source of said second transistor and a source of said fourth transistor; said fourth node is coupled to a source of said first transistor and a drain of said second transistor; said sixth node is coupled to a source of said third transistor and a drain of said fourth transistor; wherein said first auxiliary inductor has an inductance according to the formula: L AUX ⁢ ⁢ 1 = V dc · t d 16 ⁢ ⁢ f s · C s ⁢ ⁢ 1 · ( V dc + V Z ) where f s is a switching frequency for said converter; C s1 is a snubber capacitance for said first transistor; t d is a transition time between said first transistor being switched off and said second transistor being switched on; V Z is a voltage across said first transistor at an end of said transition time; and V dc is an input voltage of the converter.