Patent ID: 7254761

Claim:
A method for monitoring a fabrication of a circuit, comprising the steps of: (A) fabricating a chip only up to and including a first metal layer such that (i) a core region of said chip has an array of cells, (ii) each of said cells having a plurality of transistors and (iii) said chip includes a plurality of flip-flops; (B) after said fabricating of step (A) has started, designing a plurality of upper metal layers above said first metal layer, said upper metal layers (i) interconnecting a plurality of said cells to form said circuit, (ii) forming a plurality of scan chains from a number of said flip-flops not used in said circuit and (iii) forming a plurality of paths in said upper metal layers, wherein each of said paths connects a respective output of a first of said scan chains to a respective input of a second of said scan chains; (C) fabricating said chip to add said upper metal layers; and (D) measuring a transition delay along each of said paths to characterize said fabrication of said circuit.