Patent ID: 7739092

Claim:
A method of resetting programmable logic in an integrated circuit device for use with hardware co-simulation comprising: using a tool to identify components that do not have a reset mechanism; grouping the components that do not have a reset mechanism into at least one selected portion of the programmable logic of the integrated circuit device; generating a full bitstream comprising the at least one selected portion of the programmable logic of the integrated circuit device; loading the full bitstream into the programmable logic, wherein the full bitstream programs the programmable logic with a circuit design to be used with a first hardware co-simulation; and responsive to determining that the circuit design for the first hardware co-simulation will be used within a subsequent hardware co-simulation, initializing the circuit design for use in the subsequent hardware co-simulation by: loading, into the programmable logic, a partial bitstream of the circuit design, in lieu of the full bitstream, that reprograms the at least one selected portion of the programmable logic, thereby resetting each component in the at least one selected portion of the programmable logic that does not have a reset mechanism; identifying components that do have a reset mechanism that are located outside of the at least one selected portion of the programmable logic; and resetting each identified component of the circuit design that does have a reset mechanism using the reset mechanism of the component in lieu of the partial bitstream.