Patent ID: 8653629

Claim:
A semiconductor device, comprising: a semiconductor substrate; a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire; a first power supply terminal formed on the semiconductor substrate; a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region; and a second power supply terminal formed on the semiconductor substrate, wherein a first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire, wherein the first power supply wiring layer further includes a third power supply wire, the second power supply wiring layer further includes a fourth power supply wire that is formed below the second power supply wire and electrically connects the third power supply wire and the second power supply terminal, wherein a second barrier metal film is formed at least in the LSI regions at a boundary between the third power supply wire and the fourth power supply wire.