Patent ID: 8581642

Claim:
A data transfer circuit comprising: primary data holding circuits that hold input data according to a first clock pulse signal and output data being held; and secondary data holding circuits that hold the output data of said primary data holding circuits according to a second clock pulse signal having a pulse width different from a pulse width of said first clock pulse signal and output data being held, said data transfer circuit further includes: pulse signal generator that compares timings of pulse edges of said first clock pulse signal and said second clock pulse signal, generates a pulse signal corresponding to said second clock pulse signal when a pulse edge of said first clock pulse signal and a pulse edge of said second clock pulse signal occur at different timings and generates a pulse signal having the pulse edge of said second clock pulse signal removed therefrom when the pulse edge of said first clock pulse signal and the pulse edge of said second clock pulse signal occur at the same timing, wherein said secondary data holding circuits hold the output data of said primary data holding circuits synchronously with the pulse signal generated by said pulse signal generator.