Patent ID: 8659935

Claim:
A semiconductor device comprising: a first line; a second line; a third line; a first memory cell and a second memory cell connected in series between the first line and the second line; a first circuit configured to select and output any of a plurality of writing potentials to the third line; and a second circuit configured to compare a potential of the second line with a plurality of reference potentials to read data out, wherein each of the first memory cell and the second memory cell comprises: a first transistor including a first gate, a first source, and a first drain; a second transistor including a second gate, a second source, and a second drain; and a third transistor including a third gate, a third source, and a third drain, wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and wherein the first gate and one of the second source and the second drain are electrically connected to each other, wherein the first line, the first source, and the third source are electrically connected to one another, wherein the second line, the first drain, and the third drain are electrically connected to one another, and wherein the third line and the other of the second source and the second drain are electrically connected to each other.