Patent ID: 8114756

Claim:
A method for memory device fabrication, comprising: fabricating a periphery region of a flash memory, wherein the fabricating includes: growing an oxide layer on top of a semiconductor layer, such that the oxide layer has a substantially uniform height; depositing a nitride layer on top of the oxide layer; anisotropically etching a plurality of shallow trenches, such that each shallow trench etching occurs through the oxide layer, the nitride layer, and a portion of the semiconductor layer, such that the shallow trenches separate a plurality of gate oxide regions, wherein the plurality of gate oxide regions include a plurality of high voltage gate oxide regions and a plurality of low voltage gate oxide regions; depositing an oxide layer over each of the shallow trenches such that the height of the oxide above each of the shallow trenches is substantially the same as the height of the nitride layer; anisotropically etching the nitride above each of the high voltage gate oxide regions; and after anisotropically etching the nitride above each of the high voltage gate oxide regions, growing an oxide on each of the high voltage gate oxide regions to increase the height of the oxide layer at each of the high voltage gate oxide regions.