Patent ID: 7447292

Claim:
A shift register comprising: a first rectifying element, a first terminal thereof directly coupled to a first input node; a second rectifying element, a first terminal thereof directly coupled to a second input node; a first transistor, a first source/drain thereof directly coupled to a common voltage, a gate thereof directly coupled to a second terminal of the second rectifying element, a second source/drain thereof directly coupled to a second terminal of the first rectifying element; a second transistor, a first source/drain thereof directly coupled to the common voltage, a gate thereof directly coupled to the second terminal of the first rectifying element, a second source/drain thereof directly coupled to the second terminal of the second rectifying element; a third transistor, a first source/drain thereof directly coupled to the common voltage, a gate thereof directly coupled to the second terminal of the second rectifying element, a second source/drain thereof directly coupled to a first output node; and a fourth transistor, a first source/drain thereof directly coupled to the first output node, a gate thereof directly coupled to the second terminal of the first rectifying element, a second source/drain directly thereof coupled to a third input node.