Patent ID: 7417898

Claim:
A non-volatile semiconductor memory device comprising: a memory cell composed of a transistor having a charge trapping layer in a gate dielectric layer, in which charge is trapped in a first charge trapping region and a second charge trapping region, which are different from each other, in the charge trapping layer, and information is stored in each charge trapping region, depending on a trapped charge level; a plurality of read reference cells having the same structure as that of the memory cell and including a first read reference cell and a second read reference cell; a read reference cell setting section of setting a first charge trapping region of the first read reference cell into a first state in which a first charge amount is trapped, setting a second charge trapping region of the first read reference cell into a second state in which a second charge amount is trapped, setting a first charge trapping region of the second read reference cell into a third state in which a third charge amount larger than the first charge amount is trapped, and setting a second charge trapping region of the second read reference cell into a fourth state in which a fourth charge amount smaller than the second charge amount is trapped; and a reference information output section of outputting combination information of first information which is accumulation information about the first charge trapping region of the first read reference cell and second information which is accumulation information about the first charge trapping region of the second read reference cell, as a read reference which is used as a reference when information is read from the memory cell, wherein an absolute value of a difference between the first charge amount and the third charge amount is different from that of a difference between the second charge amount and the fourth charge amount.