Patent ID: 6928012

Claim:
A bitline equalization system for pre charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising: a first equalization circuit connected between a first position along the bitline and a corresponding first position along the complementary bitline, including a first transistor having a first gate connected to a first equalization line, a first source connected to the first position along the bitline, and a first drain connected to the corresponding first position along the complementary bitline, a second transistor having a second gate connected to the first equalization line, a second source connected to the first position along the bitline, and a second drain connected to the equalization potential, a third transistor having a third gate connected to the first equalization line, a third source connected to the corresponding first position along the complementary bitline, and a third drain connected to the equalization potential; and a second equalization circuit connected between a second position along the bitline and a corresponding second position along the complementary bitline, the second equalization circuit including a fourth transistor having a fourth gate connected to a second equalization line, a fourth source connected to the second position alone the bitline, and a fourth drain connected to the corresponding second position on the complementary bitline, a fifth transistor having a fifth gate connected to the second equalization line, a fifth source connected to the second position along the bitline, and a fifth drain connected to the equalization potential; and a sixth transistor having a sixth gate connected to the second equalization line, a sixth source connected to the corresponding second position along the complementary bitline, and a sixth drain connected to the equalization potential, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position.