Patent ID: 7999386

Claim:
A semiconductor device, comprising: a semiconductor substrate; a plurality of insulating interlayers formed over said semiconductor substrate, and comprising a plurality of interconnect layers; an inductor formed over said semiconductor substrate while placing at least one of said insulating interlayers in between; a guard ring surrounding said inductor in a plan view, so as to isolate said inductor from other regions, said guard ring being connected to a first external substrate through a first pad that is applied with a reference potential; and at least one transistor formed in said semiconductor substrate, said transistor being connected to a second external substrate through a second pad that is applied with the reference potential, wherein an interconnect drawn out from the first pad and connected to the guard ring is electrically isolated from the second pad, and wherein said guard ring comprises: an annular impurity diffused layer provided in a surficial portion of said semiconductor substrate; and an annular electro-conductor connected to said impurity diffused layer, and extended across said plurality of interconnect layers in said plurality of insulating interlayers, up to a layer having at least a height of the layer having said inductor provided therein.