Patent ID: 7443713

Claim:
An integrated semiconductor memory device comprising at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, and each memory cell includes a selection transistor and a storage capacitor; wherein: the storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode; the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell; the second capacitor electrode of the storage capacitor of each memory cell is directly connected to and permanently short-circuited with the other bit line of the pair of bit lines corresponding with the memory cell; and the two bit lines of the pair of bit lines that are connected to each sense amplifier are configured to be biased by the respective sense amplifier such that an existing potential difference between a potential of one bit line and a potential of the other bit line of the pair is increased, with one of the bit lines of the pair being biased with a first potential that is output at a first connection of the respective sense amplifier and the other bit line of the pair being biased with a second potential that is output at a second connection of the respective sense amplifier.