Patent ID: 7303992

Claim:
A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate with electrical interconnect features including submicron-sized features having bottoms, sidewalls, and top openings, the method comprising: immersing the semiconductor integrated circuit device substrate including submicron-sized features having bottoms, sidewalls, and top openings wherein said submicron-sized features include high aspect ratio features having dimensions such that the high aspect ratio features have aspect ratios of at least about 3:1 into an electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features and a polyether suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species, wherein the molecular weight of the suppressor compound is between about 1000 and about 30,000; and supplying electrical current to the electrolytic composition to deposit Cu onto the substrate and superfill the submicron-sized features by rapid bottom-up deposition at a rate of growth in the vertical direction which is greater than a rate of growth in the horizontal direction.