Patent ID: 8380934

Claim:
A cache device interposed between a processor and a memory device, comprising: a cache memory to store data from the memory device; a plurality of buffers to hold output data output from the processor; and a control circuit to determine, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in one of the plurality of buffers in response to the request to access the memory device, outputting a read request for reading the data in a line containing data requested by the request to access the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the one of the plurality of buffers into the cache memory, wherein the plurality of buffers, each including the data in a different line, wherein: if an address of the output data is not within the address range of the data in the line included in the one of the plurality of buffers, another one of the plurality of buffers is alternately selected, the address of the output data being within the address range of the data in the line included in another one of the plurality of buffers.