Patent ID: 8285896

Claim:
A video signal conversion system comprising: a first node and a second node in which one of the first node and the second node on an IEEE1394 bus serves as a cycle master, the first node having a DV data processing unit configured to transmit first a DV video signal to the second node via the IEEE1394 bus at a transfer rate synchronized with a cycle start packet output from the cycle master, the second node having a data conversion unit configured to receive the first DV video signal from the DV data processing unit of the first node via the IEEE1394 bus, convert the first DV video signal to a second video signal, and output the second video signal generated by conversion of the first DV video signal in the second node in synchronism with an external reference signal from the second node, an external synchronizing signal receiver for receiving the external reference signal provided on at least one of the first and second nodes, and a synchronization adjustment unit for synchronizing a frequency of the cycle start packet output from the cycle master with a frequency of the external reference signal received by the external synchronizing signal receiver, by carrying out feedback control of a clock source frequency of the cycle master using the external reference signal, such that the transfer of the first DV video signal to the second node is synchronized with the output of the second video signal from the second node.