Patent ID: 8551825

Claim:
A method for fabricating a thin film transistor (TFT) array, the method comprising: forming a gate line and a gate electrode overlying a substrate; forming a semiconductor layer to be insulated from the gate electrode, and to be overlapped with a portion of the gate electrode; forming a source electrode and a drain electrode on one side of the semiconductor layer and on the opposing side of the semiconductor layer, while forming a data line intersecting with the gate line; forming a passivation layer overlying an entire upper surface of the substrate including the source electrode and the drain electrode using a sol compound; forming a contact hole, with a photolithography process, in the passivation layer, through which the drain electrode is exposed; and forming a pixel electrode to be in contact with the drain electrode through the contact hole, wherein the sol compound includes metal alkoxide having a photosensitive group X and silicon alkoxide having a photosensitive group Y, and wherein each of the photosensitive groups X and Y is selected from at least one of groups consisting of an acrylate group, an epoxy group and an oxetane group.