Patent ID: 7851283

Claim:
A method of forming a field effect transistor, said method comprising: forming a gate that covers a channel region of each of a plurality of parallel semiconductor fins, said gate and said fins being formed on an isolation layer; forming a first dielectric layer on said fins and said gate; forming trenches in said first dielectric layer such that a first trench traverses said fins at a first end of said fins and a second trench traverses said fins at a second end of said fins and such that a first distance between said isolation layer and a top surface of said gate is less than a second distance between said isolation layer and bottom surfaces of said trenches; forming a plurality of via holes in said first dielectric layer through said bottom surfaces of said trenches such that each of said fins is contacted by a via hole at both said first end and said second end; and filling said via holes and said trenches with a conductor.