Patent ID: 7321329

Claim:
An analog-to-digital converter comprising: a timing controller which generates a clock signal; a reference signal generator which receives said clock signal and generates a sloped reference signal in synchronization therewith; a plurality of image elements arrayed in columns and rows, each of which generates an image signal; a plurality of comparators each of which is arranged to receive as inputs said reference signal, an image signal and said clock signal; a reference signal interface unit operative to receive said reference signal and to redistribute same to said comparators; and a plurality of counters, each of which is associated with a respective one of said comparators, wherein, each comparator is operative to compare an image signal against said reference signal in synchronization with said clock signal, the reference signal supply interface unit supplies the reference signal to said comparators via separate signal lines, the reference signal generator receives control data from said timing controller containing information indicating the slope of the reference signal, the reference signal generator provides the reference signal with color-dependant variation characteristics and initial values to at least one comparator via the reference signal supply interface unit, each counter is operable to measure a comparison time of its respective comparator and to hold a count value at the time of completion of comparison performed by the comparator, and each counter receives at least one data signal from the timing controller indicating up-counting or down-counting.