Patent ID: 8667325

Claim:
An apparatus comprising: a memory controller to couple to a memory including a plurality of ranks comprising a first rank including multiple memory lines each addressable by a different respective address, the multiple memory lines comprising a memory line A addressable by a first address, the memory controller including: detection logic to receive a signal indicating a failure of the memory line A, wherein, of the multiple memory lines, the signal indicates failure of only the memory line A; and memory sparing logic coupled to the detection logic, the memory sparing logic to store, in response to the received signal, first memory sparing information identifying an association of a second address with the first address, wherein the first memory sparing information is stored in the memory controller as a reference for the memory controller to redirect a memory access request, wherein, of the multiple memory lines, only memory sparing information for memory sparing of the memory line A is stored in response to the received signal; the memory controller further to receive a request to access the memory line A, the request identifying the first address, the memory controller further comprising: access redirection logic to access the first memory sparing information in response to the received request, and based on the first memory sparing information, the access redirection logic further to redirect the received request for an access of a memory line addressable by the second address.