Patent ID: 8352894

Claim:
A method of verification of an integrated circuit logic design embodied in a netlist using a liveness-to-safety conversion as set forth by instructions executed by a computer system, comprising: assigning, by one or more instructions executed in the computer system, liveness gates for liveness properties of the netlist; assigning, by one or more instructions executed in the computer system, a single loop gate to provide a loop signal for the liveness gates; preventing, by one or more instructions executed in the computer system, assertion of the single loop gate when none of the liveness gates are asserted; sampling, by one or more instructions executed in the computer system, a first state of the netlist, the sampled first state providing an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate; comparing, by one or more instructions executed in the computer system, the sampled first state of the first behavioral loop with a later state of the first behavioral loop to determine if the sampled first state is repeated; and returning a liveness violation as an output of the computer system when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.