Patent ID: 8295110

Claim:
A processor comprising: a cache memory comprising an array of memory cells; a decoder configured to (i) generate a first word line signal to access first instructions stored in a first word line of the array of memory cells, and (ii) generate a second word line signal to access second instructions stored in the first word line or a second word line of the array of memory cells; a precharge circuit configured to (i) precharge first bit lines connected to the first word line during a first precharge event and prior to accessing the first instructions, and (ii) precharge the first bit lines during a second precharge event and prior to accessing the second instructions, wherein the second precharge event is subsequent to the first precharge event; a control module configured to, during the first precharge event, adjust a rate of a clock signal from a first rate to a second rate; and an amplifier module configured to access the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and access the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.