Patent ID: 8023337

Claim:
A semiconductor memory device, comprising: at least one memory cell array having a plurality of memory cells between a plurality of word lines and a first number of n bit lines, the first number of being equal to 2 k (k is a natural number); a column decoder configured to output a k-bit bit-line indication signal in response to a column address; at least one bit-line selector configured to select, activate and output one of the first number bit-line selection signals in response to the bit-line indication signal; at least one switch unit having the first number switches, having one end connected with the first number bit lines and the other end circularly connected with a second number of sensing lines, the second number being 1 and smaller than the first number in sequence and activated in response to the n bit-line selection signals; and at least one shared sense amplifier unit having the second number of sense amplifiers sensing and amplifying data applied through the i sensing lines.