Patent ID: 7977986

Claim:
A delay locked loop, comprising: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by delaying the external clock with different delays, respectively, in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal, wherein the skew information signal corresponds to at least one of process, voltage and temperature (PVT) characteristics, wherein the skew information signal generator includes: a delay unit configured to delay a first input signal to output a second input signal; a pulse generating unit configured to generate a pulse signal enabled during a period defined by the first input signal and the second input signal in response to the first and second input signals; a clock sampling unit configured to output a sampling clock by sampling a reference clock in response to the pulse signal; a clock counting unit configured to count pulses of the sampling clock; and a skew information signal output unit configured to output the skew information signal in response to an output signal of the clock counting unit.