Patent ID: 8559576

Claim:
A synchronization circuit, comprising: multiple selectively coupled synchronization stages configurable to synchronize data and control signals between a first time domain and a second time domain, wherein the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain; multiple FIFO stages, wherein at least one of the FIFO stages includes an instance of the multiple selectively coupled synchronization stages, and wherein the multiple FIFO stages are configured to exchange a put token that determines which of the multiple FIFO stages services a request from a transmitter of at least some of the data and control signals; and control logic, coupled to the synchronization stages, configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during synchronization.