Patent ID: 8299526

Claim:
An integrated circuit comprising: at least one power MOS transistor, comprising: a drain region having a doping region of a first conductivity type connected to a drain electrode; a trench gate extending into the drain region, wherein the trench gate includes an insulating layer and a poly gate; a source region having a doping region of the first conductivity type connected to a source electrode; a well region with a second conductivity type formed under the source region and connected to the source electrode; a deep well region with the first conductivity type formed under the drain region and the well region; and a substrate region with the second conductivity type formed under the deep well region; wherein the drain electrode and source electrode are formed on the top surface of the power MOS transistor; and a controller circuit; wherein the power MOS transistor provides power input and output for the controller circuit, and the drain region has a double diffused drain structure.