Patent ID: 8872184

Claim:
An array structure, comprising: a thin film transistor, comprising a gate, a source and a drain; a passivation layer, overlaying the thin film transistor and having a first contacting opening exposing the drain; a pixel electrode, located on the passivation layer; a first connecting layer, located on the pixel electrode and electrically connected to the pixel electrode and the drain, wherein a portion of the first connecting layer is filled inside the first contacting opening so as to electrically connect the drain; and a first spacer, located on the first connecting layer, wherein at least a portion of the first connecting layer is located between the pixel electrode and the first spacer, the first spacer covers the first connecting layer, and the first connecting layer is not exposed by the first spacer, wherein the pixel electrode has a second contacting opening communicating with the first contacting opening of the passivation layer, and the portion of the first connecting layer is filled inside the first contacting opening through the second contacting opening.