Patent ID: 8433853

Claim:
A microprocessor, comprising: a translation lookaside buffer; a request to load a page table entry into the microprocessor generated in response to a miss of a first virtual address in the translation lookaside buffer; a prefetch unit, configured to receive a physical address of a first cache line that includes the requested page table entry, wherein the prefetch unit is further configured to responsively generate a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line; and a tablewalk engine configured to perform a tablewalk in response to an indication that a second virtual address is missing in the translation lookaside buffer, wherein the second virtual address implicates a page table entry contained in the prefetched second cache line, wherein to perform the tablewalk, the tablewalk engine loads into the translation lookaside buffer from within the microprocessor, rather than from system memory, a physical page address stored in the page table entry implicated by the missing second virtual address.