Patent ID: 7047432

Claim:
A method for synchronizing output from a plurality of timed circuits, comprising: receiving a first clock signal at a first timed circuit, the first clock signal associated with a first frequency; retrieving a first sequence of first circuit values from the first timed circuit; inserting a plurality of first count values periodically into the first sequence of first circuit values using a first counter, the first count values associated with the first frequency; receiving a second clock signal at a second timed circuit, the second clock signal associated with a second frequency, the first frequency corresponding to a multiple of the second frequency, the second frequency different from the first frequency; retrieving a second sequence of second circuit values from the second timed circuit; inserting a plurality of second count values periodically into the second sequence of second circuit values using a second counter, the second count values associated with the second frequency, the first sequence of first circuit values operable to be synchronized with the second sequence of second circuit values according to the first count values, the second count values, and the multiple.