Patent ID: 8274319

Claim:
A semiconductor device comprising: a flip-flop circuit formed in a CMOS semiconductor integrated circuit, wherein the flip-flop circuit comprises at least a first clock generating inverter that generates a first clock signal, and a second clock generating inverter that generates a second clock signal obtained by inverting the first clock signal, the first clock generating inverter and the second clock generating inverter are arranged so as to sandwich a latch unit in a layout pattern of the flip-flop circuit, the latch unit comprising a master latch unit and a slave latch unit in the flip-flop circuit, the first clock generating inverter and a first other circuit in the flip-flop circuit are configured to share a source region, the first other circuit being adjacent to the first clock generating inverter in the layout pattern, and the second clock generating inverter and a second other circuit in the flip-flop circuit are configured to share a source region, the second other circuit being adjacent to the second clock generating inverter in the layout pattern.