Patent ID: 8580645

Claim:
A method of forming a memory device, comprising: forming a plurality of word line structures above a semiconducting substrate within a cell array area, the word line structures individually comprising gate insulation over the semiconducting substrate, a floating gate over the gate insulation, inter-gate insulation over the floating gate, and a control gate over the inter-gate insulation; performing an ion implant process to form doped implant regions in said semiconducting substrate between said word line structures within the cell array area; performing a halogen ion implantation process to implant halogen atoms into said semiconducting substrate between said word line structures within the cell array area, the halogen ion implantation process and the ion implant process being conducted in separate ion implanting steps; and performing at least one anneal process to cause at least some of said halogen atoms to diffuse from the semiconducting substrate into the gate insulation and the floating gate of adjacent word line structures.