Patent ID: 7981761

Claim:
A manufacturing method of a semiconductor device which includes a capacitive element comprising the steps of: forming a first metallic film over a first interpoly dielectric film; forming a first upper barrier film over said first metallic film; forming a plurality of first metallic interconnects and a lower electrode of said capacitive element by processing a stacked film of said first metallic film and said first upper barrier film; forming a second interpoly dielectric film which covers said plurality of first metallic interconnects and said lower electrode; partially removing said second interpoly dielectric film and exposing a part of the upper face of said first upper barrier film of said lower electrode; forming a capacitive dielectric film of said capacitive element over exposed said first barrier film of said lower electrode; forming a second metallic film over said second interpoly dielectric film and said capacitive dielectric film; forming a second upper barrier film over said second metallic film; and forming a plurality of second metallic interconnects and an upper electrode of said capacitive element by processing a stacked film of said second metallic film and said second upper barrier film, wherein the film thickness of said first upper barrier film is made thicker than the film thickness of said second upper barrier film by more than 25 nm.