Patent ID: 7508016

Claim:
An imaging system comprising: an integrated circuit comprising: an array including a plurality of pixels; and a programmable non-volatile memory located on the integrated circuit for storing information relating to said array, said memory including: a plurality of rows and columns of addressable fuses connected between a respective pair of row and column lines; a plurality of row access transistors wherein a single row access transistor is coupled by a source/drain connection to a respective row line of the array; a plurality of column access transistors each coupled by a source/drain connection to a respective column line of the array; a second plurality of column access transistors each having one source/drain terminal connected to a respective column line and another source/drain terminal connected to an output line for read out of data from said fuses; and a control circuit arranged and configured to selectively operate said row and column access transistors to provide a voltage at a first level through a respective row access transistor, a respective column access transistor, and access a selected fuse sufficient to break the selected fuse during a programming operation.