Patent ID: 7985693

Claim:
A method of producing a semiconductor device with a variable resistance layer in contact with a lower electrode, comprising: (1) forming a lower electrode material serving as the lower electrode; (2) forming a mask on the lower electrode material; (3) subjecting the lower electrode material to an anisotropic etching process using the mask to form a lower electrode precursor-form; and (4) subjecting the lower electrode precursor-form to an isotropic etching process using the mask to form the lower electrode, wherein in said forming a lower electrode material, a first opening is formed in an insulating layer formed on a substrate in which a selective active element or a lower wire is formed so that a through hole connected to the lower wire or to the selective active element is exposed and the lower electrode material is fowled in the first opening, in said forming a mask, a part of the lower electrode material is selectively etched on the flat surface made up of the lower electrode material and the insulating layer to form a second opening and a first insulating material is deposited on the main surface of the substrate including the second opening and subjected to the anisotropic etching process to form a sidewall made up of the first insulating material as the mask on a sidewall of the second opening, in said subjecting the lower electrode material to an anisotropic etching process, the lower electrode material is subjected to the anisotropic etching process using the sidewall as the mask to form the lower electrode precursor-form, and in said subjecting the lower electrode precursor-form to an isotropic etching process, the lower electrode precursor-form is subjected to the isotropic etching process using the sidewall as the mask to form the lower electrode.