Patent ID: 6891916

Claim:
A shift register incorporating a built-in level shifter, comprising: n number of stages connected in cascade to an input terminal of a start pulse, wherein each state receives an input pulse, shifts the received input pulse and outputs an output pulse, wherein the output pulse includes the shifted input pulse, wherein the input pulse of a first one of the n number of stages includes the start pulse, and wherein the input pulse of the second to n th stages includes the output pulse of a preceding one of the first to n-1 th stages, respectively; and a plurality of level shifters for level-shifting voltage levels of the output pulses of each of the stages and for outputting the output pulses having the level-shifted voltage levels, wherein each of the stages comprises: a buffer for outputting an output pulse using a first clock signal and a first supply voltage in accordance with voltages at a first node and a second node; a first controller for controlling the voltage of the first node in accordance with an input pulse and the second node; and a second controller for controlling the voltage of the second node using the first supply voltage and a second supply voltage in accordance with the input pulse and a second clock signal, and wherein each of the level shifters comprises: a third controller for forming a current path between an input line of a third supply voltage and an input line of the first supply voltage and for controlling a third node using the first supply voltage and the third supply voltage in accordance with the voltage of the second node and two clock signals selected from the group consisting of second to fourth clock signals; and an output part for outputting an output pulse having a level-shifted voltage level using the first and third supply voltages in accordance with a state of the voltage at the third node.