Patent ID: 6938150

Claim:
A managing method for a re-order buffer in an out-of-order execution processor for predicting the flow of a program by branch prediction, determining a next executable instruction from an instruction string in the program and speculatively executing the instruction based on a dependence relationship between the prediction and the instruction, in which said re-order buffer rewrites an execution result according to a program order and the end of the instruction is notified from each of a plurality of function units containing a branching unit and a load unit to said re-order buffer by using a WRB number corresponding to an entry number of said re-order buffer, which comprises the steps of: managing a latest speculation state of a load instruction issued to said load unit by said load unit based on a branch prediction success/failure signal output from said branching unit and suppressing notification to said re-order buffer by said load unit, as to a subsequent load instruction of a branch instruction for which the branch prediction has failed, based on the WRB number of the subsequent load instruction even if the processing of the load instruction issued to said load unit is finished, and re-using an entry stored with the subsequent load instruction of the branching instruction for which the branch-prediction has failed, by the re-order buffer, to store a new instruction before the end notification based on the WRB number of the entry concerned is received, wherein a control signal for discriminating non-speculative execution/speculative execution for every instruction under consideration, which corresponds to a branching level, is generated in an instruction fetch/decode unit, the branching level being set to zero when an instruction under consideration is an instruction for non-speculative execution, and the branching level being set at a value of 1 or more which is determined by the number of branching instructions interposed between an instruction for the non-speculative execution and an instruction for the speculative execution when an instruction under consideration is an instruction for speculative execution, the control signal thus generated is held in said re-order buffer and said load unit, and the branching level is decremented by 1 in said re-order buffer and said load unit when a branch-prediction failure signal is output from said branching unit, thereby managing the latest instruction speculation state.