Patent ID: 8288821

Claim:
A fabrication method, comprising: providing a structure which includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, a plurality of active semiconductor regions on the buried dielectric layer, a plurality of active devices on the plurality of active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, and a protection layer on the plurality of active devices and the plurality of active semiconductor regions, but not on the plurality of dummy regions, wherein the plurality of active semiconductor regions comprise a first material, wherein the plurality of dummy regions comprise first dummy regions which comprise the first material, and wherein a first pattern density of the plurality of active semiconductor regions and the first dummy regions is essentially uniform across the structure; after said providing is performed, etching the buried dielectric layer with the protection layer and the plurality of dummy regions as blocking masks, resulting in a trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions, and such that some areas of the top substrate surface are exposed to a surrounding ambient through the trench; and after said etching is performed, bombarding the exposed areas of the top substrate surface with bombardment ions such that said bombarding does not bombard the plurality of active devices with any ion.