Patent ID: 7652927

Claim:
A semiconductor memory device comprising: a plurality of memory cells arranged in rows and columns, a bit line provided corresponding to each column of memory cells, a sense amplifier circuit provided corresponding to each bit line pair formed of said bit lines, and a control circuit, wherein each of said memory cells includes a storage transistor having a storage node to accumulate an amount of charge according to data, and an access transistor connected in series with said storage node, and each of said memory cells is connected between a corresponding bit line and source line, and configured to change current flowing through said corresponding bit line according to the amount of charge accumulated in said storage node, said sense amplifier circuit reads out data of a relevant memory cell based on current flowing from said relevant memory cell to a corresponding bit line, and then supplies voltage according to the read data to a relevant bit line pair, said control circuit effects control such that a read operation is conducted by said sense amplifier circuit corresponding to a target memory cell in a state of said storage transistor of said target memory cell being active, and then effects control such that the read data is rewritten to said target memory cell.