Patent ID: 8443330

Claim:
A computer chip comprising: a core clock; a core clock distribution network (CCDN), wherein the CCDN is configured to distribute signals from the core clock to a first leaf node and a second leaf node of the CCDN; a sampling clock distribution network (SCDN), wherein the SCDN is configured to distribute signals from a sampling clock to a first sampler configured to sample the core clock signal at the first leaf node, and to a second sampler configured to sample the core clock signal at the second leaf node; and a digital processor configured to receive an output from the first sampler and an output from the second sampler, measure at least one sample at the first sampler, calculate a first average rising edge time of the at least one sample measured at the first sampler, measure at least one sample at the second sampler, calculate a second average rising edge time of the at least one sample measured at the second sampler, and determine the clock skew based on calculating a difference between the first average rising edge time and the second average rising edge time.