Patent ID: 7649779

Claim:
An integrated circuit comprising: a plurality of first memory cells arranged along a first line; a first contact coupled to the plurality of first memory cells; a plurality of second memory cells arranged along a second line; a second contact coupled to the plurality of second memory cells; a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first contact and a second switching element of the two adjacent switching elements is coupled to the second contact, wherein the two adjacent switching elements are of the same type of switching element; a first select line to select the plurality of first memory cells, the first select line crossing the first line and the second line, wherein the first select line is coupled to the first switching element and to the second switching element; and a second select line to select the plurality of second memory cells, the second select line crossing the first line and the second line; wherein the plurality of switching elements further comprise a third switching element that is serially coupled to the first switching element, and a fourth switching element, that is serially coupled to the second switching element, and wherein the second select line is coupled to the third switching element and to the fourth switching element.