Patent ID: 6853222

Claim:
A PLL circuit comprising: a first fixed frequency divider ( 103 ) dividing an output signal of a reference oscillator ( 102 ) by a frequency-division ratio of N1 (N1 being an integer); a second fixed frequency divider ( 105 ) dividing an intermediate signal (FR) output from a first voltage-controlled oscillator ( 104 ) by a frequency-division ratio of N2 (N2 being an integer); a first phase comparator comparing phases between an output of the first fixed frequency divider ( 103 ) with an output of the second fixed frequency divider ( 105 ) to output a phase comparison signal to the first voltage-controlled oscillator ( 104 ); and a converter ( 110 ) dividing the intermediate signal (FR) by a frequency-division ratio of N3 (N3 being an integer) to output a plurality of reference signals (FR 1 to FR 4 ) having different phases; further comprising a variable frequency dividing unit ( 119 , 121 , 123 , 125 ) dividing an output of a second voltage-controlled oscillator ( 118 ) and a second phase comparing unit ( 114 to 117 ) comparing phases between the plurality of the reference signals (FR 1 to FR 4 ) with outputs (FV 1 to FV 4 ) of the variable frequency dividing unit to output a plurality of phase comparison signals to the second voltage-controlled oscillator ( 118 ).