Patent ID: 7719345

Claim:
A reference buffer circuit for providing a reference voltage at an output node, comprising: a closed-loop branch comprising: an amplifier having a positive input terminal for receiving an input voltage, a negative input terminal, and an output terminal; a first metal oxide semiconductor (MOS) transistor having a gate coupled to the output terminal of the amplifier, a source coupled to the negative input terminal of the amplifier, and a drain; a second MOS transistor coupled to the source of the first MOS transistor; and an open-loop branch comprising: a third MOS transistor having a gate coupled to the output terminal of the amplifier, a source coupled to the output node, and a drain; a fourth MOS transistor having a drain coupled to the source of the third MOS transistor, a source, and a gate; and a first tracking circuit arranged to make a voltage of the gate of the fourth MOS transistor track a voltage of the drain of the third MOS transistor; wherein the closed-loop branch further comprises: a second tracking circuit arranged to make a voltage of the gate of the second MOS transistor track a voltage of the drain of the first MOS transistor, wherein the second tracking circuit comprises: a current source coupled between a voltage source and the gate of the second MOS transistor; and a fifth MOS transistor having a gate for receiving a bias voltage, a source coupled to the drain of the first MOS transistor, and a drain coupled to the gate of the second MOS transistor.