Patent ID: 8847623

Claim:
A circuit comprising: a first plurality of transistors connected in parallel between a first power supply and a data output terminal; a first plurality of Off-Chip Drive (OCD) configuration bits; a first plurality of On-Die Termination (ODT) configuration bits; and logic for driving a gate of each of the first plurality of transistors based on the OCD and ODT configuration bits, the logic being configurable in an OCD mode to drive the gate of each of the first plurality of transistors based on a state of a respective one of the first plurality of OCD configuration bits to generate a first OCD impedance; the logic being configurable in an ODT mode to drive the gate of each of the first plurality of transistors based on a state of a respective one of the first plurality of ODT configuration bits to generate a first ODT impedance; wherein the first plurality of transistors dynamically switches between the first OCD impedance and the first ODT impedance based on an enable signal.