Patent ID: 7254718

Claim:
A tamper-resistant processing method comprising the steps of: (a) deciding whether to first transfer one operation unit in the bit pattern of data A in a memory to a first register R 1 and then to transfer one operation unit in the bit pattern of data B in the memory to a second register R 2 , or to first transfer one operation unit in the bit pattern of said data B to said second register R 2 and then to transfer one operation unit in the bit pattern in said data A to said first register R 1 ; (b) transferring each operation unit to said registers R 1 and R 2 , respectively, in accordance with the order of transfer decided in step (a); (c) executing a predetermined arithmetic operation on the contents of said first register R 1 and the contents of said second register R 2 ; (d) storing the result of said arithmetic operation in the memory, (e) repeating the steps from (a) through (d) until said arithmetic operation for said data A and said data B is finished.