Patent ID: 7370176

Claim:
A computer-implemented method comprising: transferring, on a first instruction cycle, an instruction from a first instruction stage to a second instruction stage, wherein the first instruction stage and the second instruction stage are both included within an issue unit, the instruction corresponding to instruction attributes that comprise a dependency stall signal that signifies whether the instruction is dependent upon a different instruction, a complete before issue signal that signifies whether to wait until other instructions that are currently executing on an execution unit are complete before issuing the instruction, a complete after issue signal that signifies whether to issue the instruction and wait until the instruction completes before issuing a different instruction, a resource collision signal that signifies whether a resource collision results from the instruction and another instruction, and an instruction valid signal that signifies whether the instruction and other transferred instructions are valid; determining, before commencing a second instruction cycle immediately following the first instruction cycle, whether to issue the instruction based upon the dependency stall signal, the complete before issue signal, the complete after issue signal, the resource collision signal, and the instruction valid signal, the determining performed by issue control logic included within the issue unit; issuing, during the second instruction cycle, the instruction in response to the determining to issue the instruction, the issuing performed by the issue control logic; and stalling, during the second instruction cycle, the instruction in response to the determining to not issue the instruction, the stalling performed by the issue control logic.