Patent ID: 7499320

Claim:
A non-volatile memory, comprising: an array of memory cells, wherein individual memory cells are each programmable to one of multiple memory states; a multi-bit code having multiple code bits for encoding each of the multiple memory states; a predetermined bit order of the code bits such that as more of the higher order code bits are available, more of the higher programmed states are decodable; a set of latches for latching the multi-bit data of each memory cell of a memory cell group, the set of latches having capacity just for the multiple code bits plus an additional bit; a controller in response to a request for copying a group of data from a first memory cell group to a second memory cell group, wherein said controller performing operations that comprise: reading from memory cells of the first memory cell group to determine the memory states programmed therein; encoding each read memory state as multi-bit data with the multi-bit code; latching the multi-bit data of every memory cell of the first memory cell group; grouping the latched data into as many data groups as the number of code bits, each data group collecting a same code bit from every memory cell of the first memory cell group; processing the data groups, data group by data group according to the predetermined code bit order, by outputting the bits of each data group to a controller for data-processing and returning any modified bits to update each data group; if any data group has been processed, simultaneously with any additional data group processing, programming individual memory cells of the second memory cell group up to a highest memory state decodable by available code bits from the processed data groups; and repeating the processing and the programming until all code bits of the multi-bit code are available to complete said programming.