Patent ID: 6996692

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of main memory cells arranged in rows and columns to form a matrix; a plurality of word lines each connected to the main memory cells arranged in the associated row in the memory cell array; a plurality of bit lines each connected to the main memory cells arranged in the associated column in the memory cell array; a column latch circuit, connected to associated one or more of the bit lines, for performing a latching operation for latching therein data to be written in the main memory cells, and for performing a verifying operation for determining whether the latched data is identical to the data written in the main memory cells; a plurality of deactivation code storing memory cells for storing a security function deactivation code for permitting access to the memory cell array from outside; and a control section for allowing, when a password for deactivating a security function has been inputted, the column latch circuit to latch the password, and for performing a verifying operation for determining whether the latched password is identical to the security function deactivation code stored in the deactivation code storing memory cells.