Patent ID: 8154086

Claim:
A semiconductor storage device comprising a static type memory cell in which four MOS transistors and two load resistor elements are arrayed on a dielectric film formed on a substrate, characterized in that: each of the four MOS transistors comprises functions as respective ones of first and second NMOS access transistors each operable to hold data in the memory cell, and allow access to the memory cell, and first and second NMOS driver transistors each operable to drive a storage node so as to write and read data in the memory cell, and wherein: the first and second NMOS access transistors comprise a first diffusion layer of N-type conduction, a first pillar-shaped semiconductor layer and a second diffusion layer of N-type conduction arranged on a dielectric film formed on the substrate, hierarchically in a vertical direction; the first pillar-shaped semiconductor layer is arranged between the first diffusion layer formed on a bottom of the first pillar-shaped semiconductor layer and the second diffusion layer formed on a top of the first pillar-shaped semiconductor layer; and a gate is formed along a sidewall of the first pillar-shaped semiconductor layer; and wherein: the first and second NMOS driver transistors comprise a third diffusion layer of N-type condition, a second pillar-shaped semiconductor layer and a fourth diffusion layer of N-type conduction arranged on the dielectric film formed on the substrate, hierarchically in a vertical direction, the second pillar-shaped semiconductor layer is arranged between the third diffusion layer formed on a bottom of the second pillar-shaped semiconductor layer and the fourth diffusion layer formed on a top of the second pillar-shaped semiconductor layer; and a gate is formed along a sidewall of the second pillar-shaped semiconductor layer; and wherein: the first NMOS access transistor and the first NMOS driver transistor are arrayed in adjacent relation to each other; the second NMOS access transistor and the second NMOS driver transistor are arrayed in adjacent relation to each other; the first diffusion layer formed on a bottom of the first NMOS access transistor and the third diffusion layer formed on a bottom of the first NMOS driver transistor are directly connected, and the directly connected first and third diffusion layers serve as a first storage node for holding data; the first diffusion layer formed on a bottom of the second NMOS access transistor and the third diffusion layer formed on a bottom of the second NMOS driver transistor are directly connected, and the directly connected first and third diffusion layers serve as a second storage node for holding data; and the two load resistor elements are arranged on the first and third diffusion layers serving as the first storage node and the first and third diffusion layers serving as the second storage node.