Patent ID: 8232599

Claim:
A method of manufacturing an integrated circuit, the method comprising the steps of: providing an semiconductor on insulator (SOI) wafer including a semiconductor substrate, a first semiconductor layer over the semiconductor substrate, and a buried insulating layer formed between the semiconductor substrate and the first semiconductor layer, said SOI wafer including a predefined bulk device region and a predefined SOI device region; forming shallow trench isolation (STI) regions and at least one bulk active region in said first semiconductor layer in said bulk device region and at least one SOI active region in said SOI device region; forming an SOI gate stack atop said at least one SOI active region; forming bulk contact trenches through said first semiconductor layer and said buried insulating layer adjacent said at least one bulk active region, so that said semiconductor substrate is exposed at the bottom of said bulk contact, wherein a portion of said at least one active region between said adjacent bulk contact trenches comprises a bulk gate conductor of a bulk gate stack and a portion of said buried insulating layer under said bulk gate conductor comprises a bulk gate dielectric of said bulk gate stack; forming bulk source/drain regions in said exposed semiconductor substrate by dopant implant through said bulk contact trenches adjacent said bulk gate stack; and forming SOI source/drain regions in said first semiconductor layer adjacent said SOI gate stack.