Patent ID: 6941421

Claim:
A cache line selector comprising: a register file containing decoded displacement data for identifying a cache line, said decoded displacement data being from a modified register file address image obtained during a first cache access operation, and wherein said decoded displacement data includes a base register offset and a rotation data, and wherein said decoded displacement data includes a decoded Row Address Select (RAS) component and a Column Address Select (CAS) component; a plurality of output lines from said register file; a cache memory coupled to said register file via said plurality of output lines, wherein said displacement data selectively causes an access of said cache line by transmitting said decoded displacement data to said cache memory via said plurality of output lines; a first rotator coupled to said register file, wherein said first rotator rotates said base register offset according to said rotation data to select a cache line in said cache memory; a second rotator, wherein said second rotator rotates said CAS component; a third rotator for speculatively rotating said CAS component one extra position if said CAS component has a carry-in when logically AND combined with said RAS component; and a 2-way select buffer for selecting said first and second rotators' output or said first and third rotator's output according to whether a carry-in has occurred.