Patent ID: 8125030

Claim:
An integrated circuit, comprising; a semiconductor substrate; and an SCRMOS transistor formed in and on said substrate, said SCRMOS transistor having: a deep well formed in said substrate, said deep well having a first conductivity type; a first drain structure formed in said deep well, said first drain structure having: a centralized drain diffused region, said centralized drain diffused region having a same conductivity type as said deep well, such that said centralized drain diffused region is centrally located in said first drain structure and extends less than half a length of said first drain structure; and first distributed SCR terminals, said first distributed SCR terminals having an opposite conductivity type from said deep well, such that said first distributed SCR terminals extend to each end of said first drain structure; a body region formed in said deep well adjacent to said first drain structure, said body region having an opposite conductivity type from said deep well; a source structure formed in said body region, said source structure having: a source diffused region, said source diffused region having a same conductivity type as said deep well; and a body contact diffused region, said body contact diffused region having an opposite conductivity type from said deep well; a second drain structure formed in said deep well adjacent to said body region opposite from said first drain structure, said second drain structure having: distributed drain diffused regions formed in said deep well, said distributed drain diffused regions having a same conductivity type as said deep well; and second distributed SCR terminals formed in said deep well, said second distributed SCR terminals having an opposite conductivity type from said deep well, such that a combination of said distributed drain diffused regions and said second distributed SCR terminals extend substantially to each end of said second drain structure; a first MOS gate formed over said substrate, such that said first MOS gate overlaps said body region between said first drain structure and said source structure, and such that said first MOS gate is electrically coupled to said source diffused region; and a second MOS gate formed over said substrate, such that said second MOS gate overlaps said body region between said second drain structure and said source structure.