Patent ID: 7634745

Claim:
A method of calculating critical area of a compound fault mechanism in an integrated circuit design, said method comprising: generating, by a computer system, maps, wherein each map comprises a three-dimensional diagram that represents a single one of multiple simple fault mechanisms within said compound fault mechanism and wherein said map is divided into regions; overlaying, by said computer system, said maps in order to identify sub-regions that represent intersections between said regions of said maps; identifying, by said computer system, a dominant fault mechanism from amongst any of said multiple simple fault mechanisms in each of said sub-regions based on the relative locations of said multiple simple fault mechanism along a z-axis representing critical defect size, wherein identification of said dominant fault mechanism is dependent upon a type of relational operator predetermined to be applied between said multiple simple fault mechanism so as to compose said compound fault mechanism, wherein if said predetermined relational operator comprises OR: then said dominant fault mechanism for said sub-region comprises that fault mechanism which corresponds to a lowest of said multiple simple fault mechanisms along said z-axis within said sub-region and wherein if said predetermined relational operator comprises AND, then said dominant fault mechanism for said sub-region comprises that fault mechanism which corresponds to a highest of said multiple simple fault mechanisms along said z-axis within said sub-region; and computing, by said computer system, said critical area of said compound fault mechanism based on an accumulation of critical areas calculated, for each of said sub-regions, using said dominant fault mechanism in each of said sub-regions.