Patent ID: 7142623

Claim:
An integrated circuit including an on-chip clock and data recovery circuit operable to measure tolerance to jitter in a data stream signal, comprising: a multiplexer operable to select a data stream signal for output, said data stream signal having a repeatable known sequence of data values; a clock and data recovery circuit (“CDR”) coupled to receive the data stream signal output by the multiplexer, said CDR being operable to recover a phase of a clock for sampling said data stream signal by examining transitions of said data stream signal, and to sample said data stream signal with said recovered clock phase to obtain data stream sample data; an error rate determination circuit operable to locally generate a replica of said repeatable known sequence of data values and to compare said data values of said locally generated replica with said data stream sample data to determine an error rate associated with obtaining said data stream sample data wherein said CDR includes a control circuit operable to delay said recovered clock phase by a predetermined amount a plurality of times, and said error rate determination circuit is operable to monitor said error rate each time after said control circuit delays said recovered clock phase, such that a maximum delayed clock phase is determined for sampling said data stream signal, said maximum delayed clock phase representing a right timing signal margin.