Patent ID: 7294567

Claim:
A method of fabricating a memory cell array on a substrate, wherein in the array includes memory cells arranged in rows/columns, and wherein each of the memory cells includes a stacked gate, a source and a drain, wherein each source and drain in the array includes corresponding source and drain junctions, comprising: forming discrete and substantially similarly sized self-aligned contacts in a first layer disposed over the array to form a plurality of source and drain contacts to each individual one of the source and drain junctions, respectively, in the array; forming self-aligned local area horizontal slotted vias in a second layer disposed over the first layer to form interconnections between each of the plurality of source contacts to each of the source junctions, and local area interconnects between at least two memory cells, wherein each of the formed local area interconnects electrically shunt all of the source junctions through the formed source contacts in each row in the array, and further forming discrete self aligned drain extensions over each formed self-aligned drain contact to electrically connect the drain junctions to the extensions; and plugging and filling in a single step each of the formed self-aligned contacts, drain extensions, and slotted vias with a conductive material to form the array including self-aligned drain contacts and the slotted local area interconnects that electrically shunt all of the source junctions.