Patent ID: 7007053

Claim:
A filter device, comprising: a plurality of delay blocks; a plurality of coefficient lines coupled respectively to the delay blocks; a logic architecture that includes: serial input bit lines S 1 , S 2 , . . . Sn coupled to the plurality of coefficient lines, n representing a number of coefficients of a filter transfer function; and m combinational logic blocks having full adder elements and providing addition terms of the filter transfer function [(a 0 *S 1 +b 0 *S 2 + . . . +k 0 *Sn), (A 1 *S 1 +b 1 *S 2 + . . . +k 1 *Sn) . . . (am*S 1 +bm*S 2 + . . . +km*Sn)], where a 0 , b 0 . . . k 0 , a 1 , b 1 . . . k 1 , am, bm, . . . km are coefficients having values of +/−1 or 0; wherein the full adder elements have respective first inputs, second inputs, and third input, the first inputs of the full adder elements being connected to the serial input bit lines S 1 , S 2 . . . Sn and to each other depending on the coefficients a 0 . . . km; wherein each full adder element includes a carry-out pin coupled to the third input of one of the full adder elements of a previous one of the combinational logic blocks; wherein the combinational logic blocks include respective output lines b_ 1 , b_ 2 , . . . b_m, and the output line b_m provides a final output of the architecture; and a sequential logic cluster having a plural number of delay elements depending on a size of a maximum coefficient value of the filter transfer function, each delay element having an input coupled to a respective one of the output lines of the combinational logic blocks and an output coupled to the second input of one of the full adder elements of a respective combinational logic block corresponding to a next bit position, wherein the delay elements are respectively positioned adjacent to respective end positions of respective combinational logic blocks.