Patent ID: 8063425

Claim:
A semiconductor device, comprising: a semiconductor substrate having a first circuit region and a second circuit region, the semiconductor substrate including an isolation region to define a first active region and a second active region in the first circuit region and the second circuit region, respectively; a first transistor in the first active region of the semiconductor substrate, the first transistor including first impurity regions and a first gate pattern; an insulating pattern on the first transistor and the isolation region of the first circuit region; a second transistor in the second active region of the second circuit region, the second transistor including second impurity regions and a second gate pattern; and a first conductive pattern formed on the insulating pattern, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern, wherein a bottom surface of the second gate pattern is disposed at a lower level than an interface between the first conductive pattern and the insulating pattern.