Patent ID: 8680653

Claim:
A method of dicing a semiconductor wafer, the method comprising: providing the semiconductor wafer so that the semiconductor wafer comprises a substrate with a main surface, a layer stack disposed on the main surface, the layer stack comprising at least one interconnection layer embedded into insulating material, and a plurality of circuits laterally distributed within the wafer, the circuits being separated from each other by kerf-line regions, the layer stack comprising interconnecting vias made of a conductive material within the kerf-line regions so that the conductive material is formed as a continuous physical path-connected closed loop within a layer of the layer stack around each of the plurality of circuits as well as continuously along a wafer normal direction from a surface of the layer stack facing away from the substrate, through the layer stack to the main surface of the substrate; singularizing the layer stack along the kerf-line regions, the singularizing comprising etching away, by wet etching, the conductive material within the kerf-line regions en-block with the substrate acting as an etch stop so that, after wet etching, the layer stack is singularized along the kerf-line regions, and dry etching, after the wet etching, at least part of the substrate within the kerf-line regions from the main surface of the substrate to form grooves in the main surface of the substrate extending along the kerf-line regions; and singularizing the plurality of circuits by separating the substrate along the grooves.