Patent ID: 7560814

Claim:
A semiconductor device, comprising: a semiconductor substrate that has a diffusion region; an interconnect pattern that is formed above the semiconductor substrate, the interconnect pattern being electrically connected to the diffusion region via a first conductive material, the first conductive material being formed under the interconnect pattern; an insulating layer that is formed on the interconnect pattern; an electrode pad that is formed on the insulating layer, the electrode pad having a first section and a second section; a plurality of second conductive materials that are formed between the interconnect pattern and the electrode pad, the plurality of second conductive materials electrically connecting the interconnect pattern and the electrode pad; an insulating film that has a first portion and a second portion, the insulating film being formed such that the first portion of the insulating film is formed on the insulating layer and the second portion of the insulating film is formed on the second section of the electrode pad; a bump that is formed above the first section of the electrode pad and the second portion of the insulating film; and a metal layer that lies between the electrode pad and the bump, the plurality of second conductive materials being connected with the second section of the electrode pad at a position within a range in which the plurality of the second conductive materials overlap the bump while avoiding the first section of the electrode pad, the plurality of the second conductive materials having a third conductive material and a fourth conductive material, the third conductive material being symmetrical with respect to the fourth conductive material around a center axis of the bump.