Patent ID: 7892931

Claim:
A method for forming extension regions and recessed strained epi regions of CMOS transistors in a semiconductor wafer, comprising: providing said semiconductor wafer having a PMOS region and an NMOS region, wherein said transistors in said NMOS region have NMOS extension regions; forming a protection layer over said semiconductor wafer; forming a patterned photoresist layer over said protection layer in said NMOS region; etching exposed portions of said protection layer in said PMOS region to form extension sidewalls on said transistors in said PMOS region and a protective hardmask over said NMOS region; forming PMOS extension regions for said PMOS region transistors, including an anneal of said PMOS extension regions; performing a recess etch of active regions of said PMOS region transistors after said anneal of said PMOS extension regions, wherein said protective hardmask protects said NMOS region from said recess etch and said PMOS extension region formation; and forming said recessed strained epi regions for said PMOS region transistors, wherein said protective hardmask protects said NMOS region from said formation of said recess strained epi.