Patent ID: 7667288

Claim:
An integrated circuit comprising: a wafer substrate of a first conduction type; an epitaxial layer of a second conduction type; a plurality of wells of the first conduction type disposed within said epitaxial layer; a plurality of deep wells of said first conduction type, wherein at least one of said plurality of deep wells couples at least one of said plurality of wells to said wafer substrate and another of said plurality of deep wells couples another of said plurality of wells to said wafer substrate; a first tap of said second conduction type disposed within at least a first portion of said epitaxial layer for coupling a first body biasing voltage to at least a first portion of said epitaxial layer; and a second tap of said first conduction type disposed within said one of said plurality of wells for coupling a second body biasing voltage to said another of said plurality of wells through said one and said another of said plurality of deep wells and said substrate layer.