Patent ID: 7879643

Claim:
A method for manufacturing a memory cell, the method comprising: forming a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion; forming a memory element on the top surface of the pillar portion of the bottom electrode, wherein the memory element comprises memory material having at least two solid phases; and forming a top electrode on the memory element; wherein forming the bottom electrode comprises: forming a bottom electrode material layer; forming a dielectric material layer on the bottom electrode material layer; patterning an etch mask on the dielectric material layer; etching through at least a portion of the bottom electrode material layer using the etch mask, thereby forming an electrode element comprising bottom electrode material and a dielectric element comprising the dielectric material on the electrode element, the dielectric element having a width; reducing the width of the dielectric element; and etching the electrode element using the reduced width dielectric element as a mask.