Patent ID: 7808567

Claim:
A pixel structure comprising: a lower substrate having a transistor area and a pixel area; a first patterned conductive layer deposited on the lower substrate, and comprising a data line and a gate in the transistor area; a patterned insulating layer covering the first patterned conductive layer; an active layer deposited on the patterned insulating layer and above the gate; a second patterned conductive layer deposited on the patterned insulating layer and the active layer which include a gate line, a source and a drain, wherein the source and the drain both are disposed on the active layer; a pixel electrode deposited on the patterned insulating layer and electrically connected to the drain; a patterned passivation layer covering the pattern insulating layer, the second patterned conductive layer and the pixel electrode; and a third patterned conductive layer deposited on the patterned passivation layer, and comprising a data-line-connected electrode electrically connecting the data line with the source, a gate-line-connected electrode electrically connecting the gate line with the gate, at least one alignment electrode electrically connected to the pixel electrode, and a common electrode, wherein a portion of the common electrode is deposited above the data line.