Patent ID: 7253849

Claim:
A thin film transistor array panel comprising: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate, insulated from the first signal lines, and intersecting the first signal lines; a plurality of third signal lines formed on the insulating substrate, insulated from the second signal lines, and intersecting the second signal lines; a plurality of pixel electrodes provided on respective pixel areas defined by the intersections of the first and the second signal lines, each pixel electrode having a cutout; a plurality of direction control electrodes provided on the respective pixel areas defined by the intersections of the first and the second signal lines; a plurality of first thin film transistors, each first thin film transistor connected to one of the first signal lines, one of the second signal lines, and one of the pixel electrodes; and a plurality of second thin film transistors, each second thin film transistor connected to one of the first signal lines, one of the third signal lines, and one of the direction control electrodes.