Patent ID: 8244971

Claim:
A memory apparatus, the memory apparatus comprising: a plurality of physical memory circuits including a first group of physical memory circuits; an interface circuit operable to interface the plurality of physical memory circuits and a host system, the interface circuit including: a first component of a first type; and a second component of a second type, the first and the second components being operable to present, in combination, a simulated memory circuit to a host system, where a first aspect of the simulated memory circuit is different from a corresponding second aspect of each physical memory circuit of the plurality of physical memory circuits, the first aspect and the corresponding second aspect each include at least one of a signal, a memory capacity or a timing, where each physical memory circuit of the first group of physical memory circuits is electrically coupled to the second component, where the first component is operable to receive (1) address signals and (2) power management signals other than address signals from the host system and send at least one of the power management signals received from the host system to the second component, and where the second component is operable to receive a first set of data signals from the host system and send the first set of data signals received from the host system to at least one physical memory circuit of the first group of physical memory circuits.