Patent ID: 8751912

Claim:
A layered, low density parity check (LDPC) decoder apparatus configured to decode a codeword, comprising: a plurality of hardware layers, where each hardware layer is configured to compute a syndrome value from one or more bit values in the codeword; a plurality of physical memories configured to store a plurality of syndrome values, where each respective physical memory is configured to: i) store respective one or more syndrome values for respective one or more syndromes associated with the physical memory, such that: a first physical memory stores a first group of syndrome values computed for the codeword, and a second physical memory stores a second group of syndrome values computed for the codeword, and ii) persist each syndrome value in memory until the syndrome value changes due to a change in a codeword bit value; circuitry configured to store respective syndrome values for respective syndromes in respective physical memories associated with the respective syndromes; and a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on syndrome values stored in the plurality of physical memories.