Patent ID: 7260801

Claim:
A method of computing output delay in a mathematical model of an integrated circuit, the method comprising the steps of: sorting cells of an original design of the integrated circuit in a topological order, computing original output delays for the sorted cell in the original design in the topological order, to produce original output ramp times, propagating the original output ramp times and computing original output delays, storing the original output ramp time and original output load for each cell, modifying cells of the original design to produce a modified design, for each modified cell in the topological order, computing a new output delay and a new output ramp time, comparing the new output ramp time to the original output ramp time on the modified cell, and when the new output ramp time substantially equals the original output ramp time for the modified cell, stop calculating a modified output ramp time for cell that are further down in the topological order, otherwise continue calculating the modified output ramp time for cells that are further down in the topological order until a cell at which the new output ramp time substantially equals the original output ramp time is reached.