Patent ID: 8716082

Claim:
A method of manufacturing a semiconductor device, comprising: forming a semiconductor layer on an isolating layer; forming a semiconductor region on the semiconductor layer; forming a plurality of bit lines in the semiconductor layer on either side of the semiconductor region, the plurality of bit lines being in contact with the isolating layer; forming a device isolating region comprising a buried oxide film in contact with a top surface of the isolating layer wherein the device isolation region surrounds the recited bit lines; forming an ONO film on the semiconductor region that is located between regions in which the bit lines are formed; and forming a first voltage applying unit that is coupled to the semiconductor region, wherein the device isolating region is formed on two different sides of the semiconductor region from sides on which the bit lines are formed, so as to be in contact with the isolating layer, wherein forming the semiconductor layer on the isolating layer further comprises: forming an n-type semiconductor layer in a semiconductor substrate; forming a p-type semiconductor substrate in the n-type semiconductor layer, so that a bottom surface and side surfaces of the p-type semiconductor substrate are in contact with the n-type semiconductor layer.