Patent ID: 8560761

Claim:
A system, comprising: a random access memory subsystem comprising: one or more flash memory devices configured to store a first portion of data; a volatile memory device configured to store at least a second portion of data, wherein the volatile memory device and the one or more memory devices configured to operate as a main memory of the random access memory subsystem; a virtual management component that is configured to manage the one or more flash memory devices and the volatile memory device for random access memory applications, wherein the virtual management component is configured to utilize the one or more flash memory devices in conjunction with a volatile buffer memory component for at least one random memory access application; the volatile buffer memory component configured to operate in conjunction with the virtual management component and to temporarily store at least one page of data of the first portion of data being copied to flash memory of the one or more flash memory devices from a main non-volatile storage during a page-in activity associated with the at least one random access application, wherein, when the at least one random access application comprises a read operation to read the at least one page of data, the volatile buffer memory component is further configured to comprise address match logic that compares an incoming memory address relating to the at least one page of data to determine whether the at least one page of data is to be provided by the volatile buffer memory component or by the flash memory to mitigate latencies associated with the one or more flash memory devices; and a second volatile buffer memory component configured to receive a subset of data from a first sector of the flash memory, temporarily store the subset of data in the second volatile buffer memory component, and provide communicate the subset of data from the second volatile buffer memory component to a second sector of the flash memory for storage in the second sector, to facilitate wear leveling of the flash memory, wherein the first sector is identified as a more highly used sector of the flash memory than the second sector, and wherein the virtual memory management component de-maps a first physical address of the first sector from a virtual address and maps a second physical address of the second sector to the virtual address.