Patent ID: 7975109

Claim:
A system comprising: a plurality of nodes, each of the nodes comprising a respective processor, a respective interconnect switch, a respective fine-grained memory comprising a plurality of independently-writable words, and a respective less-fine-grained memory comprising a plurality of independently-writable pages, where units of the respective less-fine-grained memory smaller than one of the pages are not independently writable, where each of the pages is at least twice a size of one of the words of the fine-grained memory, and where the respective less-fine-grained memory is a solid-state, non-volatile memory; an interconnection network coupling the nodes via the respective interconnect switches; wherein the less-fine-grained memories as an aggregate are configured to store a plurality of elements, each of the elements having a respective element identifier; wherein the respective fine-grained-memory of each of at least a first subset of the nodes is enabled to store a respective global map, the respective global map configured to specify for each of the elements, based at least in part on a portion of the respective element identifier, a respective home one of the nodes of the element; wherein, at each of the nodes, the respective less-fine-grained memory is enabled to store a respective subset of the elements, and the respective fine-grained-memory is enabled to store a respective local map, the respective local map having a plurality of entries, each one of the respective subset of the elements associated with a corresponding and distinct one of the entries, each of the entries comprising fields which when populated store a respective physical location of the element associated with the entry, the respective physical location comprising an address of a respective one of the pages of the respective less-fine-grained memory and a respective offset within the respective page; wherein, at a particular one of the first subset of the nodes, the respective processor is configured to determine, via the respective global map, the respective home node of a particular one of the elements, and forward an access of the particular element to the respective processor of the respective home node of the particular element; wherein, at the respective home node of the particular element, the respective processor is configured to access, via the respective local map, the respective physical location of the particular element in the respective less-fine-grained memory, and return a response to the access of the particular element to the respective processor of the particular node; and wherein the particular element and at least one other of the respective subset of the elements of the respective home node of the particular element are enabled to be stored at a same time in the respective page of the respective physical location of the particular element.