Patent ID: 7605079

Claim:
A method for manufacturing a memory device, comprising: forming a circuitry in a substrate having a top surface, the circuitry including an array of contacts on the top surface of the substrate; forming an electrode layer on the substrate, the electrode layer having a top surface, the electrode layer including an array of electrode pairs, including depositing conductive first electrodes and second electrodes of the respective electrode pairs using a metallization process, and forming respective insulating members between the first and second electrodes, wherein the first electrodes contact corresponding contacts in the array of contacts, and wherein the first and second electrodes and the insulating members extend to the top surface of the electrode layer, and the insulating members have widths between the first and second electrodes at the top surface; forming an array of bridges of memory material on the top surface of the electrode layer, the array of bridges including bridges for each of the electrode pairs in the array of electrode pairs, contacting the respective first and second electrodes and extending across the respective insulating members, the bridges comprising patches of memory material having a first side and a second side and contacting the respective first and second electrodes on the first side, the bridges defining inter-electrode paths between the first and second electrodes across the insulating members having path lengths defined by the widths of the insulating members, wherein the memory material has at least two solid phases; and forming a patterned conductive layer using said metallization process over said bridge, and forming an array of contacts between said second electrodes in the array of electrode pairs and said patterned conductive layer.