Patent ID: 7344941

Claim:
A method of manufacturing a metal-insulator-metal capacitor, comprising: forming a lower metal electrode layer pattern for a metal-insulator-metal capacitor and a lower metal line layer pattern for a metal line on a first insulating layer on a semiconductor substrate; forming a second insulating layer covering the lower metal electrode layer pattern and the lower metal line layer pattern on the first insulating layer; forming a trench penetrating the second insulating layer and at least partially exposing the lower metal electrode layer pattern; forming a dielectric layer on the second insulating layer and an exposed surface of the lower metal electrode layer pattern; forming a first mask layer pattern on a portion of the dielectric layer within the trench and on an edge portion of the trench, using a first photoresist layer; forming a second mask layer pattern on the first mask layer pattern and the dielectric layer using a second photoresist layer, the second mask layer pattern having an opening exposing a portion of the dielectric layer in a region corresponding to the metal line; forming a via hole penetrating the dielectric layer and the second insulating layer and exposing at least a portion of the lower metal line layer pattern using the second mask layer pattern; removing the second mask layer pattern and the first mask layer pattern; and forming an upper metal electrode layer for the metal-insulator-metal capacitor on a portion of the dielectric layer within the trench, and forming a via contact connected to the lower metal line layer pattern within the via hole.