Patent ID: 7307891

Claim:
A storage circuit using a dual-access memory, comprising an array of memory points and two reading/writing devices connected to the array, each reading/writing device being activable by one access, the storage circuit comprising: means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access, at least two successive activations of said means controlling operations of the same type, reading or writing; wherein each access of said dual-access memory comprises a group of control inputs enabling controlling a read or write operation in a memory point; and wherein the dual-access memory is synchronous, each group of control inputs comprising a clock input, the clock signal received on this clock input being a periodic signal, the signals received on the other control inputs of a group of control inputs being sampled on an edge, rising or falling, of the clock signal received on the clock input of the considered group of control inputs.