Patent ID: 7112497

Claim:
A method of forming a transistor, comprising: forming a layer of poly-ox material over a gate structure and portions of a substrate exposed by said gate structure; forming a layer of offset nitride material over the poly-ox layer; patterning the offset nitride and poly-ox materials such that they remain substantially only on sidewalls of the gate structure; forming a layer of capping oxide material over the gate structure of the transistor and said portions of a substrate; forming a layer of capping nitride material over the capping oxide; forming a layer of stopping oxide material over the capping nitride; forming a layer of sidewall material over stopping oxide; patterning the layer of sidewall material to form first sidewall spacers adjacent to the gate structure; removing the layer of stopping oxide material; performing source/drain doping to establish source and drain regions; reducing the first sidewall spacers to form second sidewall spacers having respective second widths that are narrower than respective first widths of the first sidewall spacers; and forming respective source and drain contacts.