Patent ID: 8427856

Claim:
A semiconductor device comprising: a selection signal line supplied with a selection signal; a plurality of first and second local I/O lines; a plurality of first and second bit lines; a plurality of first transistors each having a control electrode, each of the first transistors being coupled between an associated one of the first local I/O lines and an associated one of the first bit lines; a plurality of second transistors each having a control electrode, each of the second transistors being coupled between an associated one of the second local I/O lines and an associated one of the second bit lines; a first via conductor coupled between the selection signal line and the control electrodes of the first transistors; a second via conductor coupled between the selection signal line and the control electrodes of the second transistors; and a failure detecting circuit that detects a defect of at least one of the first and second via conductors by comparing a plurality of first data on the first local I/O lines read from the first bit lines and a plurality of second data on the second local I/O lines read from the second bit lines.