Patent ID: 8873269

Claim:
A Read Only Memory (ROM) structure having a plurality of wordline conductors, each associated with a plurality of individual bitline conductors, and a plurality of activation cells, an activation cell connecting a respective wordline conductor to an individual bitline conductor, each activation cell including a transistor device responsive to a signal at said wordline conductor to provide a programmed bit value to said individual bitline conductor, wherein a programmed bit value comprises a logic ‘1’ or logic ‘0’ level signal value and the activation cells of said plurality are configured such that adjacent cells along the bitline conductor share a common semiconducting diffusion region, the ROM device further comprising: two or more activation cells at consecutive two or more wordline conductors, each activation cell configured to provide a logic value on said individual bitline conductor, a transistor device of said first or second activation cell configured to provide a respective logic value includes a gate connected to said first or second wordline conductor, a first transistor device terminal physically connected to the individual bitline conductor (BL) and another transistor device terminal remains open circuit (OPEN).