Patent ID: 8689166

Claim:
A modeling method comprising: accessing, by a computer from a memory, a design for a multi-fin field effect transistor, said multi-fin field effect transistor comprising: multiple semiconductor fins; a gate structure traversing center portions of said multiple semiconductor fins; a first local interconnect electrically connecting end portions of said multiple semiconductor fins on a first side of said gate structure; a second local interconnect electrically connecting end portions of said multiple semiconductor fins on a second side of said gate structure opposite said first side; and a single contact to said first local interconnect; determining, by said computer, a first total parasitic resistance associated with a first source/drain region of said multi-fin field effect transistor on said first side of said gate structure and a second total parasitic resistance associated with a second source/drain region on said second side of said gate structure, said first total parasitic resistance comprising being equal to a sum of the following: a first resistance contribution of said end portions of said fins; second resistance contributions of segments of said local interconnect, each second resistance contribution being associated with a corresponding segment of said local interconnect and further being dependent on relative positions of said contact on said local interconnect and of said corresponding segment within said local interconnect; and a third resistance contribution of said contact, said first resistance contribution, said second resistance contributions and said third resistance contribution all comprising resistance values and said sum being a result of adding said resistance values; representing, by said computer in a netlist, said multi-fin field effect transistor as a simple field effect transistor; and representing, by said computer in said netlist, said first total parasitic resistance by a first resistive element connected to a first source/drain node of said simple field effect transistor and said second total parasitic resistance by a second resistive element connected to a second source/drain node of said simple field effect transistor.