Patent ID: 7787095

Claim:
A thin film transistor array panel including a display area and a peripheral area having first, second, third, and fourth peripheral areas, the thin film transistor comprising: a plurality of gate lines formed on an insulation substrate and extended in a first direction; a gate insulating layer formed on the gate lines; a plurality of data lines formed on the gate insulating layer and extended in a second direction, the second direction being perpendicular to the first direction; a driver disposed on the first or second peripheral area; and a plurality of data signal transmission lines formed on at least one of the third and fourth peripheral areas, wherein: portions of the data signal transmission lines include end portions connected to end portions of the data lines and having different contact sizes in accordance with respective distances from the driver, and the first peripheral area faces the second peripheral area in the first direction, and the third peripheral area faces the fourth peripheral area in the second direction, wherein the plurality of data signal transmission lines comprise a plurality of first data signal transmission lines formed on the third peripheral area and a plurality of second data signal transmission lines formed on the fourth peripheral area, wherein the plurality of the first data signal transmission lines comprise a plurality of first even signal transmission lines formed on the same layer as the gate lines and a plurality of second even signal transmission lines formed on the same layer as the data lines and on a different layer from that of the first even signal transmission lines, wherein the plurality of the second data signal transmission lines comprise a plurality of first odd signal transmission lines formed on the same layer as the gate lines and a plurality of second odd signal transmission lines formed on the same layer as the data lines and on a different layer from that of the first odd signal transmission lines, and wherein the first even signal transmission lines and the first odd signal transmission lines comprise a first metal, wherein the first metal is the same metal as that of the gate lines and the second even signal transmission lines and the second odd signal transmission lines comprise a second metal, wherein the second metal is the same metal as that of the data lines and has a lower characteristic resistivity than the first metal.