Patent ID: 7745270

Claim:
A method comprising forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate; forming a dielectric layer over the substrate; creating a first conductive gate layer over the dielectric layer on the p-diffusion fin; creating a second conductive gate layer over the dielectric layer on the n-diffusion fin; forming a first gate stack layer over the first and second conductive gate layers; forming a second gate stack layer over the first gate stack layer; polishing the second gate stack layer; patterning a gate electrode hard mask; and etching the second gate stack layer and the first gate stack layer to create gate stacks over the n-diffusion fin and the p-diffusion fin, wherein the thickness of the first and second conductive gate layers and the first gate stack layer are selected to cause the etching to expose the first and the second conductive gate layers at substantially the same time.