Patent ID: 7266663

Claim:
In a computer system comprised of a processor, a memory, and storage including cache storage, the method of conserving computer chip power consumption comprising dynamically adjusting the size (C) of cache storage depending on both the frequency of missed requests (M) and the ratio of frequently accessed data records to all requests for access to said cache spanning an incremental unit Dt, said method of adjusting cache storage size uses an algorithm wherein said algorithm uses intermediate variables Action(t) and Refaction(t) wherein Action(t)=One (1) if M(t)>M max ; or if ΔM(t)>0 and ΔC(t)<=0, or if ΔM(t)<=0 and ΔC(t)>0; otherwise, Action(t) equals minus one (−1), Refaction(t+Dt)=Zero (0) if Refaction(t−Dt) does not=0; Refaction(t+Dt)=One (1) if Action(t)=1 and Skew(t)=0; Refaction(t+Dt)=Minus one (−1) if RAND<=DecProb, Otherwise, refaction(t+Dt)=zero (0); and a new value for cache size is computed as C(t+Dt)=min{max(C(t)+Refaction(t), C min} , C max }.