Patent ID: 8680584

Claim:
A transistor device laid out in a CMOS process, shaped as a rectangle having four edges, comprising: a first drain/source layer that is employable as a source or a drain connection layer; a top drain/source layer that is employable as a source or a drain connection layer, wherein said top drain/source layer is above said first drain/source layer, and wherein both of said first drain/source layer and said top drain/source layer covers each of said four edges of said device rectangle, such that both of said drain and said source are accessible from each of said four edges of said device rectangle; two or more via stripes extending over an entire length in an X direction and evenly distributed over an entire length in a Y direction connecting said first drain/source layer and said top drain/source layer; a gate layer that is employable as a gate connection layer; and a bulk layer that is employable as a bulk connection layer, wherein the bulk is independently accessible from the drain, the gate, and the source.