Patent ID: 8547317

Claim:
A display, comprising: a timing controller configured to generate a first clock using a phase-locked loop (PLL), insert the first clock into data, and transmit the data into which the first clock is inserted; transmission lines configured to transfer the data into which the first clock is inserted; and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data, wherein the PLL includes: a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock; a plurality of voltage-controlled oscillators (VCOs); a VCO selector configured to select a VCO having a frequency operating range, which is a range from a highest oscillation frequency of the VCO to a lowest oscillation frequency of the VCO, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error; and an inductor/capacitor (LC) resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO.