Patent ID: 7930592

Claim:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a memory array having a plurality of memory elements including at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements; a built-in memory self test unit including: a test unit for determining whether a memory element is failing and generating a fail signal in response thereto; and a redundancy enablement activator for timing the enablement of redundancy via a load-enable signal; and a failing address register for controlling enablement of a corresponding redundant memory element when the fail signal is active based on the load-enable signal, wherein the failing address register includes: a set of address bits (A0-An) for containing an address location of a failing memory element to be replaced by a redundant memory element; an enable bit (EN) for controlling whether the memory element whose address location is contained in the address bits is to be replaced with a corresponding redundant memory element; a bad-redundancy bit (BR) for overriding the EN; a temporary enable bit (TE) for holding a value to be loaded into the EN in response to the load-enable signal, wherein the value of the TE is loaded into the EN only if the EN is not set, and if the EN is already set, the IF is then ignored; and a temporary bad-redundancy bit (TB) for holding a value to be loaded into the BR in response to the load-enable signal, wherein the value of the TB is loaded into the BR only if the BR is not set, and if the BR is already set, the TB is then ignored.