Patent ID: 8569876

Claim:
A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; and a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, wherein the die has a thickness extending from the first surface to the second surface, and wherein the first ball grid array is aligned with the second ball grid array in a direction of the thickness of the die.