Patent ID: 7336112

Claim:
A delay-locked loop (DLL) to produce a plurality of delayed clock signals wherein each pair of sequential clock signals forms a common delay period (Δt), the DLL comprising: combinational logic comprising: an input port to accept a subset of the plurality of delayed clock signals wherein a total count of the plurality of delayed clock signals comprises a total value N and a total count of signals in the subset comprises a total subset value of N−2 or fewer signals; forward logic to provide a forward indicator, wherein the forward indicator indicates the delay period (Δt) is longer than a desired delay period; back logic to provide a back indicator, wherein the back indicator indicates the delay period (Δt) is shorter than a desired delay period; lock logic to provide a lock indicator, wherein the lock indicator validates at least one of the forward and back indicators; and an output port to provide the forward, back and lock indicators.