Patent ID: 8015460

Claim:
A background data loading circuit in a memory device having an array of memory cells logically arranged in rows and columns, comprising: a buffer coupled to the array of memory cells; a data loading circuit, comprising: a signal line; a plurality of switches coupled between the signal line and the buffer, the plurality of switches having respective control inputs and being configured to couple the signal line to the buffer in a manner that causes a pattern of data corresponding to a respective pattern of select signals applied to the respective control inputs of the switches to be stored in the buffer for each of a plurality of rows of memory cells in the array; and a pattern generating logic coupled to the data loading circuit, the pattern generating logic including a column decoder logic coupled to the control inputs of the switches, the column decoder logic being configured to generate a respective pattern of the select signals for each of the rows of the memory cells according to a pattern generating algorithm to cause the switches to load each of the patterns of data into the buffer for transferring to a respective row of the memory cells.