Patent ID: 7924868

Claim:
A network processing apparatus, the apparatus comprising: a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets; a sequence processor (SP) that is coupled to the MI and configured to provide automatic decapsulations, decryption, authentication, checksums, and decompression for input packets and compression, checksums, authentication, encryption and encapsulations for output packets; an address translation module that is coupled to the SP and configured to perform routing and stateful firewall functions; and a system memory storing: a first software driver configured to manage communications between a host CPU and the MI for host packet processing, wherein the first software driver selects one push buffer from a plurality of push buffers stored in the system memory by detecting how many of the plurality of push buffers that are allocated to store commands or data for consumption by the MI are not empty to produce non-empty push buffers and determine a priority of each non-empty push buffer, and a second software driver configured to manage communications between the MI and other processing units in the network processing system for router packet processing.