Patent ID: 7625777

Claim:
A method of fabricating a memory device, the method comprising: forming a mold insulating layer on a semiconductor substrate; forming parallel data storage element lines on the mold insulating layer; forming a conductive line that crosses the data storage element lines; and etching the data storage element lines using the conductive line as an etch mask to form data storage elements that are self-aligned with the conductive line at an intersection of the conductive line and the data storage element lines; after forming the data storage element lines, forming an interlayer dielectric layer pattern interposed between and spaced apart from the data storage element lines, wherein forming the interlayer dielectric layer pattern comprises: forming an interlayer dielectric layer on the semiconductor substrate having the data storage element lines; and planarizing the interlayer dielectric layer; and before forming the interlayer dielectric layer, forming a protective insulating layer having a different polishing rate from the interposed interlayer dielectric layer on the semiconductor substrate having the data storage element lines, wherein forming the protective insulating layer and forming the interlayer dielectric layer include separating the interposed interlayer dielectric layer from the data storage element lines.