Patent ID: 8587368

Claim:
A method comprising: generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor, and wherein a first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and wherein a second end of the resistor is connected to a first input of an operational amplifier; generating a second current flowing through a second resistor, wherein the second resistor is connected to the first input of the operational amplifier; connecting an emitter of a second bipolar transistor to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are interconnected and connected to VSS; adding the first current and the second current to generate a third current; mirroring the third current to generate a fourth current proportional to the third current; and conducting the fourth current through a third resistor to generate an output reference voltage.