Patent ID: 7629908

Claim:
A D/A converter constituted by a current mirror circuit for D/A converting data to be converted, wherein the current mirror circuit includes a first current mirror circuit that D/A converts upper (n−m) digits in the data of n bits to be converted (wherein, n is an integer equal to or more than 4, m is an integer equal to or more than 2 and (n−m) is an integer equal to or more than 2) and a weighting current circuit block that D/A converts lower m digits in the data, and the weighting current circuit block is provided with at least m pieces of current diverting circuits which are cascade connected at the upstream or the downstream of one of other output side transistors than output side transistors for the D/A conversion in the first current mirror circuit and cause to flow currents flowing through the other output side transistors as diverting currents corresponding to current values of respective digit weights in the lower m digits and a selection circuit that selectively outputs the respective diverting currents flowing respectively through the m pieces of current diverting circuits to output terminals for analog converted currents in the first current mirror circuit.