Patent ID: 7205201

Claim:
A process of manufacturing different-voltage devices, comprising steps of: providing a substrate, wherein low-voltage device regions, high-voltage device regions, and isolation regions can be formed in; forming at least one high-voltage well in said substrate; forming at least one N-well in said low-voltage device regions, at least one P-well in said low-voltage device regions, source/drain wells in said high-voltage device regions, and isolation wells in said isolation regions; forming a patterned nitride layer over said substrate; forming a field oxide layer over said isolation region; forming a HV gate oxide layer over said high-voltage device regions; forming an LV gate oxide layer over said low-voltage device regions and said high-voltage device regions; forming a poly layer over said high-voltage device regions and said low-voltage device regions; and forming PSD/NSD regions in said high-voltage device regions and said low-voltage device regions.