Patent ID: 7465983

Claim:
A nonvolatile memory, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars; an oxide intermediate at least one of the floating gates and at least one of the body regions, respectively; a number of control gates opposing the floating gates; a number of sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a tunneling barrier of less than 2.0 eV and having a number of small compositional ranges such that gradients can be formed by an applied electric field to produce different barrier heights at an interface with the floating gate and the control gate; and a number of bitlines coupled to the second source/drain regions along a third direction in the array of flash cells.