Patent ID: 8468405

Claim:
An integrated circuit comprising: a plurality of functional circuits each configured to perform data processing operations as part of said integrated circuit executing a data processing task; activity detection circuitry coupled to each of said plurality of functional circuits and configured to detect when a functional circuit of said plurality of functional circuits has an inactive state during functional operation of said integrated circuit in which said functional circuit is not performing data processing operations advancing execution of said data processing task; a plurality of serial scan chains each coupled to a functional circuit of said plurality of functional circuits and configured to perform a scan test operation upon said functional circuit by applying stimulus signals to said functional circuit and capturing response signals from said functional circuit; scan control circuitry coupled to said activity detection circuitry and to said plurality of serial scan chains and configured to initiate a scan test operation using a serial scan chain coupled to a functional circuit detected by said activity detection circuitry as having said inactive state during said execution of said data processing task; and error detection circuitry coupled to said plurality of serial scan chains and configured to detect if response signals captured from said functional circuit during said scan test operation differ from expected response signals indicating an error in operation of said functional circuit.