Patent ID: 7268595

Claim:
A circuit comprising: first and second active devices, a junction formed of first nodes of the first and second devices forming a first input port and a junction formed of respective second and third nodes of the first and second devices forming a first output port; third, fourth, and fifth active devices, a gate of the third device being coupled to the first output port, a source of the third device being connected to a drain of the fourth device, and a drain of the third device being connected to a source of the fifth device, the drain of the third device and the source of the fifth device forming an output port; wherein a gate of the fifth device forms a second input port; sixth, seventh, and eighth active devices, a gate of the sixth device being connected to a gate of the fourth device, a drain of the sixth device being connected to a source of the seventh device, the gate and drain of the sixth device being connected together; wherein a gate of the seventh device is connected to a gate of the eight device, the gate and a source of the eighth device being connected together; and a charge storing device having a first end forming a third input port and a second end connected to the source of the eighth device.