Patent ID: 7075842

Claim:
A memory device comprising: a first plurality of memory cells, each memory cell having a read-select input and a read output, each memory cell generating a current at its read output that is representative of a data value stored by the cell when the read-select input of the memory cell is activated, said current having a magnitude of substantially I M1 to represent a first data state and a magnitude of substantially zero to represent a second data state; a second plurality of memory cells, each memory cell having a read-select input and a read output, each memory cell generating a current at its read output that is representative of a data value stored by the cell when the read-select input of the memory cell is activated, said current having a magnitude of substantially zero to represent the first data state and a magnitude of substantially I M2 to represent the second data state; a first bit line coupled to the read outputs of the first plurality of memory cells; a second bit line coupled to the read outputs of the second plurality of memory cells; a first reference current circuit having an enable input and an output, the output being coupled to the second bit line, the first reference current circuit generating a first reference current I R1 at its output when its enable input is activated, the first reference current I R1 having a magnitude that is less than I M1 ; a second reference current circuit having an enable input and an output, the output being coupled to the first bit line, the second reference current circuit generating a second reference current I R2 at its output when its input is activated, the second reference current I R2 having a magnitude that is less than I M2 ; a current sense amplifier having a first input coupled to the first bit line, a second input coupled to the second bit line, and an output generating a signal representative of the difference in currents presented at the inputs of the differential current sense amplifier; and a read circuit to read the data states of the first and second plurality of memory cells, said read circuit providing an activation signal to the read-select input of only one of the first plurality or second plurality of memory cells at a time, said read circuit further providing an enable signal to the enable input of the first reference current circuit when said activation signal is provided to a memory cell of the first plurality of memory cells, and providing an enable signal to the enable input of the second reference current circuit when said activation signal is provided to a memory cell of the second plurality of memory cells.