Patent ID: 7615453

Claim:
A method of manufacturing a semiconductor integrated circuit device with a first MISFET of a first threshold value voltage and a second MISFET of a second threshold value voltage lower than the first threshold value voltage in a main surface of the same semiconductor substrate, comprising the steps of: (a) forming a semiconductor region for threshold value voltage adjustment of the first MISFET which has a first conductivity type and has first concentration in a first region of the semiconductor substrate; (b) forming a semiconductor region for threshold value voltage adjustment of the second MISFET which has the first conductivity type and has a second concentration of impurity concentration lower than the first concentration in a second region of the semiconductor substrate; (c) forming a gate insulating film over the main surface of the semiconductor substrate; (d) forming a first gate electrode of the first MISFET in the first region, and forming a second gate electrode of the second MISFET in the second region by depositing a conductive film over the gate insulating film, and patterning the conductive film and the gate insulating film; (e) after the step (d), forming a first semiconductor region which has a second conductivity type and has third concentration in the first region of the semiconductor substrate; (f) after the step (d), forming a second semiconductor region which has the first conductivity type and has fourth concentration in the first region of the semiconductor substrate; (g) after the step (d), forming a third semiconductor region which has the second conductivity type and has a fifth concentration of impurity concentration higher than the third concentration in the second region of the semiconductor substrate; (h) after the step (d), forming a fourth semiconductor region which has the first conductivity type and has a sixth concentration of impurity concentration higher than the fourth concentration in the second region of the semiconductor substrate; (i) after the steps from (e) to (h), forming an insulation film at a side wall of the first gate electrode and the second gate electrode; and (j) after the step (i), forming a fifth and a sixth semiconductor region which have the second conductivity type and have a seventh concentration of impurity concentration higher than the third and the fifth concentration in the first and the second region of the semiconductor substrate, respectively.