Patent ID: 7584438

Claim:
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout, comprising the steps of: selecting a diffusion area within the layout for analysis; identifying Si/STI edges on the selected area; identifying channel areas and their associated gate/Si edges; determining threshold voltage variations in each identified channel area, including the steps of calculating, by a computer, threshold voltage variations due to effects in a longitudinal direction; calculating, by the computer, threshold voltage variations due to effects in a transverse direction; and combining, by the computer, the longitudinal and transverse variations to provide an overall variation, wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function of the form λ i ( r )=1/(( x i /α) βi +ε i ), wherein, α i , β i and ε i , are process and material-related factors, and r is a distance in either the X or Y direction.