Patent ID: 7301791

Claim:
A semiconductor device including a plurality of memory banks, comprising: a first memory device capable of reading data within a first cycle time, writing data within a second cycle time longer than the first cycle time, and reading and writing data in parallel in time; and a second memory device capable of reading and writing of data within the first cycle time and that operates as a cache memory of the first memory device, wherein the functions executes, in the case that the second memory device causes cache miss and cache full when a write data instruction is issued: the process of selecting a unbusy memory bank in writing of data from the plurality of memory banks in the first memory device in the first cycle time, the process of writing back the memory data corresponding to the selected memory bank from the stored data in the second memory device, and the process of writing the input data associated with the data write instruction to an empty memory region in the second memory device caused by the write-back operation.