Patent ID: 7930665

Claim:
A method of designing a semiconductor integrated circuit, comprising: using a computer, reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit wherein variations of a property value are not taken into consideration for the fundamental property value, and a pair of variation coefficients among a plurality of pairs of variation coefficients wherein each pair in the plurality of pairs of variation coefficients is stored in the memory unit corresponding to one of a plurality of dimensions, each pair in the plurality of pairs of variation coefficients is constituted by an upper limit value of the variation coefficients and a lower limit value of the variation coefficients, the upper limit value and the lower limit value indicate a variation range of the property value, and the pair of variation coefficients to be read is one of the plurality of pairs of variation coefficients corresponding to a dimension of a transistor constituting the cell; and using the computer, performing a static timing analysis on the semiconductor integrated circuit in accordance with the read pair of variation coefficients and the fundamental property value, wherein the dimension of the transistor is a length or a width.