Patent ID: 8082284

Claim:
A reconfigurable processing device configured as a 4 to 1 multiplexer comprising: a decoder; a 2 to 1 multiplexer; a lookup table, wherein the lookup table comprises a first column of cells comprising values associated with an address A and a second column of cells comprising values associated with an address B; and a preprocessor configured to: receive inputs x 0 , x 1 , x 2 and x 3 and control signal c 1 ; and determine partial products from the inputs x 0 , x 1 , x 2 and x 3 and control signal c 1 expressed as y 0 = c 1 ·x 0 , y 1 = c 1 ·x 1 , y 2 =c 1 ·x 2 , and y 3 =c 1 ·x 3 , wherein the decoder is configured to receive y 0 , y 1 , y 2 and y 3 and to generate an address value A=y 0 +y 2 and an address value of B=y 1 +y 3 , wherein value A represents an address of the first column and value B represents an address of the second column; wherein the decoder is configured to access a first cell of the lookup table at address value A to receive a stored value stored A* at address value A and to access a second cell of the lookup table at address value B to receive a stored value B* stored at address value B, and wherein the multiplexer is configured to receive the stored values A* and B* from the lookup table and in response to a control signal c 0 to determine an output F, wherein F= c 0 ·A*+c 0 ·B*.