Patent ID: 8284879

Claim:
A circuit for transferring to a monitor clock domain target events that occur in a target clock domain, the transfer circuit comprising: a detector, in the target clock domain, configured to assert a target-domain event signal each time the target event occurs; a sending circuit, in the target clock domain, configured to change the value of a request signal each time the target-domain event signal is asserted; and a receiving circuit, in the monitor clock domain, configured to detect the change in value of the request signal, and to assert a monitor-domain event signal once for each change in value detected; a second detector, in a second target clock domain, configured to assert a second-target-domain event signal when a second target event occurs; a second sending circuit, in the second target clock domain, configured to change the value of a second request signal each time the second target-domain event signal is asserted; and a second receiving circuit in the monitor clock domain configured to detect the change in value of the second request signal, and to assert a second monitor-domain event signal once for each change in value detected; a monitor circuit, in the monitor clock domain, configured to increment a first count in response to the monitor-domain event signal, to increment a second count in response to the second monitor-domain event signal, to hold a first target value, to produce a first trigger signal by comparing the first count with the first target value, to hold a second target value, and to produce a second trigger signal by comparing the second count with the second target value; wherein the transfer circuit is adapted for use in a debug module within an integrated circuit, and the monitor circuit is further configured to assert a debug signal based on a signal selected from the first trigger signal, the second trigger signal, or a logical combination thereof.