Patent ID: 7227259

Claim:
A circuit arrangement, for power semiconductor modules, comprising: at least one electrically insulating substrate; at least two mutually insulated ribbon connectors on said substrate; at least one power semiconductor component attached to at least one of said ribbon connectors; at least a first and a second DC port conductors and at least one AC port conductor; said DC port conductors being arranged proximate to each other and at least one of said substrate and said ribbon conductors; each said DC port conductor including at least a first substantial length portion in parallel to a second respective substantial length portion on said second DC port conductor; said AC port conductor having at least one portion proximate at least one of said substrate surface and said ribbon connectors; at least one surface element extending at least at a first angle from one of said AC port conductor and said DC port conductors; and at least one electrical connection extending from said at least one surface element to at least one of said power semiconductor component and said at least one ribbon conductor, whereby said circuit arrangement provides a low parasitic inductance and a low ohmic resistance in a power semiconductor module.