Patent ID: 7155692

Claim:
A method of analyzing a circuit, said circuit comprising at least two nodes, each of said at least two nodes have timing requirements associated therewith, said method comprising: receiving a failure time of first node, wherein said failure time represents the time within which a signal must arrive at said first node from said second node in order to avoid a timing violation of said circuit, said second node being upstream of said first node; determining a potential slack for said first node based on said failure time of said first node, wherein said potential slack is equal to said failure time minus the sum of a target time and the delay between said first node and said second node; terminating said analysis if said potential slack is less than a first predetermined value; determining the target slack at said first node, wherein said target slack is equal to said timing requirement of said first node minus the sum of said timing requirement of said second node and the delay between said first node and said second node; and changing the timing requirement of said first node if said target slack is less than a second predetermined value.