Patent ID: 7378890

Claim:
A master/slave latch comprising: a master latch comprising: a NAND gate having a first clock signal input, a data signal input and an output; and an N-clocked inverter stage, a first input of said N-clocked inverter stage connected to said output of said NAND gate and a second input of said clocked inverter connected to said first clock signal input; and a slave latch, comprising: a first dual-clocked inverter stage, a first input of said dual-clocked inverter stage connected to an output of said N-clocked inverter stage, a second input of said dual-clocked inverter stage connected to said first clock signal input and a third input of said dual-clocked inverter stage connected to a second clock signal input; and an inverter stage having an output, an input of said inverter stage connected to an output of said dual-clocked inverter stage.