Patent ID: 7005337

Claim:
Method for parallel production of a MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate, comprising: a) generating a MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer; b) generating a bipolar preparation structure in the bipolar area, wherein the bipolar preparation structure comprises a conductive layer and a mask layer on the conductive layer; c) common structuring of the gate electrode layer and the conductive layer by using the mask layer on the gate electrode layer and the mask layer on the conductive layer for defining a gate electrode in the MOS area and a base terminal area and/or emitter collector terminal area in the bipolar area; d) simultaneous generating of isolating spacing layers on side walls of the gate electrode layer in the MOS area and the conductive layer in the bipolar area by depositing a first and second spacing layer, wherein the isolating spacing layers serve for defining areas to be doped in the MOS area and the first spacing layer serves for isolating a base area and an emitter area in the bipolar area; e) selective etching of the first spacing layer and the second spacing layer in the MOS area and the bipolar area; and f) removing the second spacing layer in the MOS area and the bipolar area.