Patent ID: 7730383

Claim:
An error detection circuit for a multilevel memory device including a plurality of memory cells, each memory cell being programmable at more than two levels and each level representing a logic value consisting of a plurality of bits, the circuit comprising: an encoding circuit coupled to the memory cells, the encoding circuit to receive a page of bits including a plurality of data words, the encoding circuit operable to arrange the bits of the plurality of data words for storage in the memory cells and to develop error check bits for at least a portion of the plurality of data words, and operable to store the arranged bits and the error check bits in the memory cells, the encoding circuit comprising: a plurality of encoders, each encoder operable to receive at least two of the data words and to arrange the bits of these data words into an arranged data word; a converter operable to transform groups of the bits in the arranged data work into a corresponding level to be stored in a one of the memory cells; at least one error checking and correction encoder, each encoder operable to receive a corresponding one of the data words for which error check bits are to be developed and operable to develop error check bits for that word; and a converter operable to transform groups of the error check bits into a corresponding levels to be stored in the memory cells, and operable to store the level for each group of bits into a corresponding memory cell; and a decoding circuit coupled to the memory cells and operable to read the arranged bits of the data words and the error check bits from the memory cells, the decoding circuit providing selected ones of the data words as read from the memory cells and performing error check correction on non-selected ones of the data words using the bits of those non-selected ones of the data words and the check bits read from the memory cells, and providing the other words after performing error checking and correction on those other words.