Patent ID: 8503255

Claim:
A semiconductor storage device comprising: a memory cell array having memory cells arranged therein at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells including a variable resistance element; a plurality of memory blocks, each having a plurality of memory cell arrays laminated on a semiconductor substrate; and a control circuit configured to apply a voltage to a selected one of the first wirings and to a selected one of the second wirings so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring, the control circuit comprising: a plurality of charge pump circuits configured to generate a voltage applied to the first and second wirings; a plurality of clock oscillator circuits each configured to supply a clock signal to a certain number of the charge pump circuits to control a timing of operation thereof; and a plurality of delay circuits each provided on a path from a respective one of the clock oscillator circuits to each of a plurality of the charge pump circuits, and configured to delay the clock signal by a certain delay time; each of the charge pump circuits being provided at a region immediately below a respective one of the memory blocks, the plurality of clock oscillator circuits being configured to output clock signals at different frequencies, each of the plurality of delay circuits being configured to provide a delay time of the clock signal different from those of other ones of the plurality of delay circuits, each of the delay circuits being provided between the path and each of the plurality of charge pump circuits so as to be connected in series with each of the charge pump circuits, and the delay circuits being formed to delay clock signals so that delay times of the clock signals are relatively prime.