Patent ID: 8111537

Claim:
A semiconductor memory comprising: a plurality of ferroelectric memory cells each having a row address and a column address, capacitor plate lines each connected to the ferroelectric memory cells having a same row address, and word lines each arranged so as to connect the ferroelectric memory cells having adjacent row addresses and adjacent column addresses; a plurality of capacitor plate line drive circuits for driving the capacitor plate lines; and a plurality of word line drive circuits for driving the word lines, wherein: the plurality of capacitor plate line drive circuits are arranged in a direction of increasing row addresses of the memory cell array which is perpendicular to a direction of increasing column addresses of a memory cell array having the plurality of ferroelectric memory cells; the plurality of word line drive circuits include a plurality of word line drive circuits that are arranged in the direction of increasing row addresses and a plurality of word line drive circuits that are arranged in the direction of increasing column addresses; and one of the plurality of word line drive circuits is selected based on a value obtained by adding a row address and a column address of a ferroelectric memory cell to be selected, and the selected word line drive circuit drives a word line connected to the ferroelectric memory cell.