Patent ID: 7408485

Claim:
A digital conversion circuit receiving digital input data at a first sample rate, the digital conversion circuit comprising: (a) a first estimating circuit receiving a reference clock signal and a first clock signal unrelated to the reference clock signal for generating a first signal in synchronization with the first clock signal and representative of a period of the reference clock signal and for generating a second signal in synchronization with the first clock signal and representative of a time of arrival of a particular edge of the reference clock signal; (b) a second estimating circuit for operating on the first signal, the second signal, and an input value which represents a predetermined ratio of the frequency of the reference clock signal divided by the first sample rate to generate a third signal which represents a period of the first sample rate and a fourth signal that represents a time of arrival of a group of sample of the digital input data; (c) a coefficient and address generation circuit receiving the third and fourth signals for generating a read address signal and a coefficient signal; (d) a FIFO memory having an input coupled to receive the digital input signal and a read address input for receiving the read address signal; and (e) a multiplication/accumulation circuit for receiving the coefficient signal and digital data samples output by the FIFO memory, multiplying the digital data samples output by the FIFO memory by corresponding coefficients output by the coefficient and address generation circuit, accumulating resulting multiplication products, and producing a digital output signal including accumulated multiplication products and having an output sample rate that is synchronized with the first clock signal.