Patent ID: 7092480

Claim:
A variable delay circuit comprising: a counter having: a count terminal; M sequential storage elements, including a least-significant storage element adapted to store a first logic level to express the lowest of M binary counts and a most-significant storage element adapted to store a second logic level to express the highest of the M binary counts, each storage element including a storage-element output terminal; M multiplexers coupled to said M sequential storage elements, wherein each multiplexer has a plurality of inputs coupled to receive outputs of at least two sequential storage elements and couples, in response to a first control signal and a second control signal, one of the plurality of inputs to the input of an associated sequential storage element; and a delay line having: a plurality of delay-line taps disposed between a delay-line input terminal and a delay-line output terminal; a plurality of switches, each switch including a switch input terminal connected to a respective one of the delay-line taps, a switch output terminal connected to the delay-line output terminal, and a switch control terminal connected to a respective one of the storage-element output terminals.