Patent ID: 7974369

Claim:
A signal processor comprising: a signal processing path that converts an analog input signal into a digital output signal, wherein the signal processing path generates multi-bit soft values, each multi-bit soft value having a sign bit and a multi-bit confidence value; and a timing recovery loop that uses the sign bits and one or more bits of the multi-bit confidence values of the soft values to generate a sampling clock signal used by the signal processing path to sample the analog input signal, wherein the timing recovery loop comprises a phase detector that generates an estimated timing error signal based on the sign bits and the one or more bits of the multi-bit confidence values of the soft values, wherein the estimated timing error signal is used to adjust a local oscillator (LO) clock signal to generate the sampling clock signal, wherein the phase detector comprises: a module that generates mean values based on the sign bits and the one or more bits of the multi-bit confidence values of the soft values; a filter that filters the mean values to generate filtered values; a first delay module that delays equalized values from the signal processing path to generate delayed equalized values; a second delay module that delays the filtered values to generate delayed filtered values: a first multiplier that multiplies the delayed equalized values and the filtered values to generate first product values; a second multiplier that multiplies the equalized values and the delayed filtered values to generate second product values; and a difference node that generates the estimated timing error signal based on differences between the first and second product values.