Patent ID: 7983101

Claim:
A circuit for controlling data output and data strobe signal generation in a DDR memory device, comprising: an internal clock generating unit configured to generate first and second internal clock signals; an output enable signal outputting unit configured to sequentially output first to third select signals in response to CAS latency; an enable signal outputting unit configured to sequentially output first and second enable signals in response to the second select signal and the first internal clock signal, and third and fourth enable signals in response to the first and third select signals and the first internal clock signal; a pulse generating unit configured to generate first and second pulse controlling data output by using the first and second internal clock, signals in response to the first and second enable signals, and third and fourth pulses for controlling generation of a data strobe signal by using the first and second internal clock signals in response to the third and fourth enable signals; and a data strobe signal generating unit configured to generate the data strobe signal in response to the third and fourth pulses.