Patent ID: 7936223

Claim:
A phase-locked loop, comprising: a phase detector configured to compare a phase of a first signal and a second signal, wherein the phase detector is further configured to generate a third signal based, at least in part, on the comparison; a charge pump coupled to the phase detector and configured to receive the third signal and an input current, wherein the charge pump is further configured to generate a fourth signal based, at least in part, on the input current and the third signal; a voltage-controlled oscillator coupled to the charge pump and configured to receive a differential control signal based, at least in part, on the fourth signal, wherein the voltage-controlled oscillator is further configured to generate at least one of the first or second signals based, at least in part, on the differential control signal; and a differential gain linearization circuit coupled to the charge pump and configured to receive an offset signal and the differential control signal, wherein the differential gain linearization circuit is further configured to adjust the input current provided to the charge pump based, at least in part, on the offset signal and the differential control signal, wherein the differential gain linearization circuit is further configured to provide an output current, and wherein the differential gain linearization circuit comprises: a first transistor having a first size, wherein the first transistor includes: a first gate terminal configured to receive one end of the differential control signal; a first source/drain terminal configured to provide at least a portion of the output current; and a second source/drain terminal; a second transistor having a second size, wherein the second transistor includes: a second gate terminal configured to receive the one end of the differential control signal; a third source/drain terminal; and a fourth source/drain terminal; a third transistor having the first size, wherein the third transistor includes: a third gate terminal configured to receive the offset voltage; a fifth source/drain terminal coupled to the first source/drain terminal and configured to provide another portion of the output current; and a sixth source/drain terminal coupled to the fourth source/drain terminal; and a fourth transistor having the second size, wherein the fourth transistor includes: a fourth gate terminal configured to receive the offset voltage; a seventh source/drain terminal coupled to the third source/drain terminal; and an eighth source/drain terminal coupled to the second source/drain terminal.