Patent ID: 8644051

Claim:
A semiconductor memory device comprising: a plurality of memory cell arrays each comprising a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure; and a data input/output circuit comprising a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output, wherein each memory cell array further comprises: a first sense amplifier and a second sense amplifier electrically connected to a first data bus and a second data bus; and a first column gate and a second column gate configured to decode the first address and the second address; the data input/output circuit further comprises: a first address bus and a second address bus respectively connected to the first sense amplifier and the second sense amplifier; a multiplexer configured to selectively output column addresses held in the first address buffer and the second address buffer to one of the first address bus and the second address bus in accordance with a control signal from the controller; and an input buffer connected to the first address buffer, the second address buffer, the first address bus, and the second address bus.