Patent ID: 7045372

Claim:
A method for forming an electrochemical structure within an integrated circuit, comprising the steps of: providing a semiconductor wafer; forming a layer of electronic devices on the semiconductor wafer, wherein the layer of electronic devices includes at least one electronic device; forming N wiring levels within an interconnect structure of the integrated circuit, wherein the N wiring levels are disposed on the layer of electronic devices, wherein N is at least 2, wherein the N wiring levels are denoted as wiring level 1 , wiring level 2 , . . . , wiring level N in order of increasing distance from the semiconductor wafer; forming a first conductive metallization and a second conductive metallization within the N wiring levels; and forming at least one battery entirely within the wiring levels I through K, wherein I is selected from the group consisting of 1, 2, . . . , and N−1, wherein K is selected from the group consisting of 1, 2, . . . , and N−1, wherein I does not exceed K, wherein the first conductive metallization conductively couples a first electrode of the at least one battery to the at least one electronic device, and wherein the second conductive metallization conductively couples a second electrode of the battery to the at least one electronic device, and wherein the first and second conductive metallizations are totally external to the interior of the at least one battery.