Patent ID: 8643108

Claim:
A transistor device comprising: a semiconductor substrate; a buffered vertical fin-shaped structure formed in the semiconductor substrate, the vertical fin-shaped structure including an upper semiconductor layer including a channel region in between drain and source regions, a buffer region beneath the upper semiconductor layer, the buffer region having a first doping polarity, at least part of a well region having a second doping polarity which is opposite to the first doping polarity, and at least one p-n junction between the buffer region and the well region which at least partially covers a horizontal cross section of the vertical fin-shaped structure; and a gate stack formed over the channel region of the upper semiconductor layer, wherein a first layer of the well region is directly above the buffer region, and a second layer of the well region is directly below the buffer region at the base of the buffered vertical fin-shaped structure, such that two p-n junctions are present between the buffer region and the well region.