Patent ID: 7057952

Claim:
A precharge control circuit of a pseudo SRAM, comprising: a precharge set signal generation unit configured to output a precharge set signal; a precharge standby signal generation unit configured to output a precharge standby signal; a precharge signal output unit configured to output a precharge signal in response to the precharge set signal and the precharge standby signal; a first precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where a chip select signal is disabled, in the case where the chip select signal is disabled long for a first time; and a second precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where the chip select signal is disabled, in the case where the chip select signal is disabled long for a second time longer than the first time, wherein the precharge signal is generated in response to the operation of the first precharge control unit or the second precharge control unit.