Patent ID: 8751886

Claim:
An integrated circuit comprising: A. a clock lead, a shift lead, a capture lead, an update lead, a select lead, a serial data in lead, and a serial data out lead; B. an instruction register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having control outputs; C. an internal scan register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having a control input coupled to a control output of the instruction register; D. a boundary scan register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having a control input coupled to a control output of the instruction register; E. a bypass register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having a control input coupled to a control output of the instruction register; F. first multiplexer circuitry coupled between the internal scan register, the boundary scan register, and the bypass register and the serial data out lead; G. second multiplexer circuitry connected between the first multiplexer circuitry and the serial data out lead; H. first gating coupled to the select lead and coupling the clock lead, the shift lead, the capture lead, and the update lead, to the instruction register, the internal scan register, the boundary scan register, and the bypass register; I. an enable lead; and J. second gating connected to the enable lead and the select lead and coupling the select lead to the first gating.