Patent ID: 7254670

Claim:
A circuit configured to access art element in a data structure, comprising: a first shifter configured to receive a first shifter input and a first shift amount, the first shifter further configured to shift the first shifter input according to the first shift amount to generate a shifted value, the first shifter further configured to communicate the shifted value; a second shifter configured to receive a second shifter input and a second shift amount, the second shifter further configured to shift the second shifter input according to the second shift amount, the second shifter further configured to communicate a base offset; an adder coupled to the second shifter, the adder configured to receive the base offset from the second shifter and a base address, the adder further configured to communicate a final address; and a multiplexor configured to receive the final address from the adder, the multiplexor further configured to select the final address if a data structure is being accessed and the shifted value if a data structure is not being accessed, wherein the first shifter is configured to shift the first shifter input a first number of bit places up to a first maximum amount, wherein the second shifter is configured to shift the second shifter input a second number of bit places up to a second maximum amount, and wherein the first maximum amount is less than the second maximum amount.