Patent ID: 7471536

Claim:
A content addressable memory (CAM) system comprising: a write/search bit line decoder and driver circuit having a word line and a match line; and a CAM cell array, wherein the CAM cell array is organized into at least one rectangular array having rows and columns of CAM cells, and wherein said each one of the CAM cells comprise: an associated read/write bit line coupled between said each one of the CAM cells and the write/search bit line decoder and driver circuit, and wherein during a write cycle, the write/search bit line decoder and driver circuit writes a data bit to said each one of the CAM cells via the associated read/write bit line; and an associated addressed search circuit having: a first pair of N channel transistors, wherein the gates of the N channel transistors are coupled to a search bit line and a control line respectively; a second pair of N channel transistors coupled to the word line and the match line, wherein during a debug mode the associated addressed search circuit receives data from the control bit line and the search bit line, and determines whether there is a match/mismatch on an addressed row.