Patent ID: 6898748

Claim:
A test circuit, provided between first and second target circuits, for testing the target circuits, comprising: a first selecting section for selecting and outputting one of three input signals, namely: (1) a first output signal output from the first target circuit, (2) a second output signal output from the second target circuit, and (3) a test signal indicating a test pattern input via a test pattern input terminal, said selection being made according to first and second test mode signals supplied to said first selecting section as additional inputs used for selection, said first and second test mode signals supplied from an external device; a temporary data storage section for temporarily storing the signal selected by the first selecting section as a data signal; a second selecting section for selecting, as a first selection signal one of either the temporarily stored data signal stored in said temporary data storage section or the second output signal from the second target circuit according to the second test mode signal fed to said second selecting section as a selection input, and providing the first selected signal to the first target circuit; and a third selecting section for selecting, as a second selecting signal, one of the temporarily stored data signal or the first output signal from the first target circuit according to a third test mode signal supplied from said external device, and providing the second selected signal to the second target circuit, and wherein: the temporarily stored data signal is also output as a test result via a test pattern output terminal.