Patent ID: 7579884

Claim:
A frequency doubler device configured to receive an input signal at a reference frequency and to deliver an output clock signal having a frequency twice that of the reference frequency and having a chosen duty cycle, the frequency doubler device comprising an exclusive OR gate having a first input receiving a first clock signal at the reference frequency, a second input receiving a second clock signal at the same frequency as the first clock signal and offset relative to said first clock signal by a chosen offset determining the duty cycle, and an output delivering the output clock signal with a frequency twice the reference frequency; wherein the device further comprises a first block comprising: a D flip-flop having a D input, an output linked to the second input of the exclusive OR gate to apply the second clock signal to the input, and an inverse output linked to the D input, a comparator having a positive input, a negative input and an output controlling the D flip-flop, first and second arrangements of switches respectively linked to the positive and negative inputs of the comparator, and controlled by a first control signal substantially in phase with the input signal and a second control signal at least partially the reverse of the first control signal to apply respectively, to said positive and negative inputs, either first and third voltages, or second and fourth voltages, wherein the first, second, third and fourth voltages are voltage ramps, four voltage ramp generation devices for the first, second, third and fourth voltages, each voltage ramp generation device comprising a current source in series with a capacitor between a power supply voltage and a reference voltage and a reset switch in parallel with the capacitor, the current sources of the third and fourth voltage ramp generation devices presenting a current ratio k relative to the current sources of the first and second voltage ramp generation devices, wherein the opening of the reset switches of the first and fourth voltage ramp generation devices and the opening of the reset switches of the second and third voltage ramp generation devices being controlled by third and fourth control signals substantially the reverse of each other and in phase or in phase opposition with the first and second control signals, wherein the first and second voltages relative to the third and fourth voltages are offset by a half-period of the input signal, and wherein the ratio of the slopes of the first and second voltage ramps relative to the slopes of the third and fourth voltage ramps are determined by the chosen current ratio (k), where the current ratio is chosen according to the chosen duty cycle.