Patent ID: 8169019

Claim:
A metal oxide semiconductor (MOS) chip, comprising: a heavily doped semiconductor substrate, composing a drain doped region; an epitaxial layer, which is located on the semiconductor substrate and has an etched sidewall formed on a scribe line preserving region of the MOS chip such that the scribe line preserving region has a first portion defined on the epitaxial layer perpendicular to an upper surface of the semiconductor substrate and a second portion defined on the upper surface of the semiconductor substrate, the epitaxial layer also having an active region, and a termination region surrounding the active region and being surrounded by the scribe line preserving region, wherein the upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region is exposed; at least a MOS cell, located in the active region and having a gate electrode and a source electrode; and a metal pattern layer, formed on the epitaxial layer and the exposed upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region, the metal pattern layer having a gate pad, a source pad, and a drain pattern, wherein the gate pad is electrically connected to the gate electrode of the MOS cell, the source pad is electrically connected to the source electrode of the MOS cell, and the drain pattern is formed on the scribe line preserving region such that a first portion of the drain pattern is defined on the epitaxial layer perpendicular to the upper surface of the semiconductor substrate, and a second portion of the drain pattern is defined on the upper surface of the semiconductor substrate.