Patent ID: 6914821

Claim:
A flash memory device having an array of floating-gate memory cells, wherein the flash memory device comprises: a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising: a sense inverter having an input and an output for providing an output signal indicative of a potential level of the input of the sense inverter relative to a threshold point; a precharge path coupled to the input of the sense inverter for providing a precharge potential to the input of the sense inverter; a feedback loop interposed between the precharge path and the input node of the sensing device, wherein the feedback loop limits a potential level on the input node of the sensing device to a predetermined maximum potential level; and a reference current path coupled to the input of the sense inverter for providing a reference current to the input of the sense inverter.