Patent ID: 7958332

Claim:
A controller operable to control an array of processing elements, the controller comprising: a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items; a combining unit operable to combine the plurality of instruction streams into a serial instruction stream; a distribution unit operable to distribute the serial instruction stream to an array of processing elements; a plurality of instruction stream processors, one for each instruction stream, for controlling the respective instruction streams; a semaphore controller for controlling synchronization between instruction streams, wherein each of the instruction streams includes at least one semaphore value to indicate the availability of said instruction stream, and wherein said semaphore controller is configured to set semaphore operations including a preset operation, a wait operation, and a signal operation; an embedded processor unit configured for reading, presetting, incrementing, and decrementinq semaphore signals; a status block for providing status information regarding each of the instruction streams; and a scheduler connected to receive status information, and operable to determine which of the instruction streams is to be active.