Patent ID: 8839037

Claim:
A method for transparent debug of a hardware queue, comprising: using a computer device or processor to accomplish the steps of: monitoring a plurality of hardware queues, the plurality of hardware queues associated as parts of a design; receiving a list of target hardware queues; monitoring a plurality of inputs from an internal and an external source; receiving a request to save from at least one of the internal and external sources; sending a command to the plurality of hardware queues to pause at least one hardware queue, the command based on the request to save; receiving hardware queue state information from at least one paused hardware queue on the list of target hardware queues; receiving hardware queue data entry and historical entry information from at least one paused hardware queue on the list of target hardware queues; sending a command to dump said hardware queue data entry and historical entry information from at least one paused hardware queue on the list of target hardware queues; storing the hardware queue state, data entry, and historical entry information in a data storage connected to the computing device; comparing the received state, data entry, and historical entry information to stored data representative of functional hardware queues; identifying errors and failures in each monitored hardware queue from the comparing.