Patent ID: 8225024

Claim:
A two-wire interface module comprising the following: a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, the first two-wire interface communication including a header portion and a payload portion, the payload portion including a plurality of data fields; a logic component configured to extract one or more of the plurality of data fields from the payload portion of the first two-wire interface communication; and a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol, the second two wire interface communication including a header portion and a payload portion, wherein the second two-wire interface component is further configured to receive the one or more of the plurality of data fields extracted from the payload portion from the logic component and to insert the one or more of the plurality of data fields extracted from the payload portion in the header portion of the second two-wire interface communication; wherein the second two-wire interface protocol comprises a Finisar Serial Bus (FSB) two-wire interface protocol and communications following the FSB two-wire interface protocol include: a preamble field; a frame start field; an operation field; a device identifier field; a basic address field; a first bus turnaround field; a data field; a second bus turnaround field; and a frame end field.