Patent ID: 7623511

Claim:
A system, comprising: a plurality of memories, wherein each comprises a read-write memory for recording and outputting objects comprising electronic data with a processor and a storage device, and physical data exchange links between a plurality of data processing units, wherein a virtual network is formed, in which the plurality of data processing units are provided as a series arrangement with a sequence of the plurality of memories (S 1 , . . . , Sn; n>1), in which a first memory (S 1 ) is arranged next to a last memory (Sn), and in which a routing table is formed in each of the plurality of memories (S 1 , . . . , Sn), which table includes entries comprising electronic reference information concerning communication links between one memory corresponding to the routing table and others of the plurality of memories (S 1 , . . . , Sn), and each memory of the plurality of memories (S 1 , . . . , Sn) is assigned a name range of a corresponding ordered name space for names of the objects, wherein, for the each memory (Sx; x=1, 2, . . . ; 1≦x≦n) of the plurality of memories (S 1 , . . . , Sn) in the virtual network, entries E SX [j, i] (1≦i, 1≦j<b) containing the electronic reference information in the corresponding routing table are formed as follows: entry E SX [1, 1]=reference of a communication link to a memory (Sx+1), which is next in the sequence; entry E SX [2, 1]=entry E SX+1 [1, 1] entry E SX [j, 1]=entry E SV [k, 1] in a further memory (Sv), to which an entry E SX [m, 1] in the memory (Sx) refers, wherein 2<j<b, 0<k, m and k+m=j; entry E SX [1, i]=entry E SV [k, i−1] in the further memory (Sv), to which an entry E SX [m, i−1] in the memory (Sx) refers, wherein 1<i, 0<k, m and k+m=b; entry E SX [j, i]=entry E SV [k, i] in the further memory (Sv), to which an entry E SX [m, i] in the memory (Sx) refers, wherein 2≦j<b, 1<i, 0<k, m and k+m=j.