Patent ID: 7884408

Claim:
A semiconductor device, comprising: a substrate having a first region and a second region; at least one trench isolation structure formed in said first region of said substrate; a dielectric layer formed overlying the substrate; a capacitor embedded in said at least one trench isolation structure and extending through the dielectric layer, wherein said capacitor comprises a bottom electrode layer, a capacitor dielectric layer formed overlying said bottom electrode layer, and a top electrode layer formed overlying said capacitor dielectric layer; a connection pad formed in a connection trench formed in the dielectric layer extending to the top electrode, the connection pad physically and electrically coupled to the top electrode; and at least one first transistor formed in said second region of said substrate, wherein said first transistor comprises a first gate dielectric layer and a first gate electrode layer having a bottom surface, a top surface, and opposing vertical sidewalls formed overlying said first gate dielectric layer, the first gate dielectric layer adjacent the vertical sidewalls of the first gate electrode layer; wherein, said top electrode layer is formed of the same metal material as said first gate electrode layer and wherein said capacitor dielectric layer is formed of the same dielectric material as said first gate dielectric layer.