Patent ID: 7504269

Claim:
A method for analyzing a sample for the manufacture of integrated circuits, the method comprising: providing an integrated circuit chip, the integrated circuit chip having a pad area surrounded by passivation material, the pad area having at least one region of interest; covering a first portion of the pad area including the region of interest using a blocking material, the blocking material not in contact with any portion of the integrated circuit; forming a metal layer on a second portion of the pad area, the metal layer contacting the second portion of the pad area, while the blocking material protects the first portion; removing the blocking material to expose the first portion of the pad area including the region of interest while maintaining the metal layer on the second portion of the pad area; coupling an electrical source to the metal layer to apply a voltage differential to the metal layer to draw away one or more charged particles through a portion of the metal layer from the first portion of the pad area; and subjecting the pad area including the region of interest to spectrometer analysis.