Patent ID: 7164602

Claim:
A nonvolatile semiconductor memory device comprising: an memory array including a plurality of normal memory cells and a plurality of redundant memory cells for substitution relief of defective memory cells among said plurality of normal memory cells, said plurality of normal memory and said plurality of redundant memory cells being arranged in a matrix shape; a program circuit for storing redundant information for use in substitution relief, which is placed adjacent to said memory array in the direction of the memory cell columns; said program circuit comprising a plurality of program cells arranged in a matrix shape and having the same structure as that of said normal memory cells, a plurality of sub bit lines provided in correspondence with the respective columns of said program cells, a plurality of program word lines provided in correspondence with the respective rows of said program cells, main bit lines which are shared by said normal memory cells and said program cells, and redundant reading bit lines for reading said redundant information from said program circuit, a first connecting circuit for electrically connecting said main bit lines with selected sub bit lines designated to be written, of said plurality of sub bit lines, in program information writing operation for writing said redundant information into said program circuit, and a second connecting circuit for electrically connecting said redundant reading bit lines with selected sub bit lines designated to be read, of said plurality of sub bit lines, in program information reading operation for reading said redundant information from said program circuit before data reading operation.