Patent ID: 7554838

Claim:
A simulating circuit for a Magnetic Tunnel Junction (MTJ) device, for simulating an MTJ device having at least a free layer and a fixed layer, wherein the MTJ device is connected to a write word line and a write bit line, and the operation region of the MTJ device are divided into four quadrants, the simulating circuit comprising: a closed switch loop, for simulating the magnetization of the free layer and the fixed layer, to simulate the recording of data, wherein the magnetization includes the parallel or anti-parallel state; a first write loop, for simulating the first quadrant of the operation region of the MTJ device; a second write loop, for simulating the second quadrant of the operation region of the MTJ device; a third write loop, for simulating the third quadrant of the operation region of the MTJ device; a fourth write loop, for simulating the fourth quadrant of the operation region of the MTJ device; a first resistor, for simulating the wire resistance of the bit line; a second resistor, for simulating the wire resistance of the write word line; and a third resistor, for simulating the resistance of the MTJ device.