Patent ID: 7763519

Claim:
A method for fabricating an interconnect arrangement, comprising: a) forming a first dielectric on a carrier substrate; b) forming a trench structure in the first dielectric with a capacitor region having a first aspect ratio and an interconnect region connected thereto and having a second aspect ratio, which is at least triple the first aspect ratio; c) depositing a first electrically conductive layer onto the patterned first dielectric in the capacitor and interconnect region until the trench structure has been substantially completely filled in the interconnect region by the first electrically conductive layer; d) forming a capacitor dielectric on the first electrically conductive layer; e) depositing a second electrically conductive layer on the capacitor dielectric until the trench structure has been substantially completely filled in the capacitor region, wherein the first electrically conductive layer, the capacitor dielectric, and the second electrically conductive layer form a layer structure; f) planarizing the layer structure on the first dielectric as far as the first dielectric in order to realize a first interconnect, a first capacitor electrode, which is connected to the first interconnect, and a second capacitor electrode, which is insulated from the first capacitor electrode by the capacitor dielectric, the first interconnect and first capacitor electrode being formed by the first electrically conductive layer, the second capacitor electrode being formed by the second electrically conductive layer, such that a surface of the first capacitor electrode, a surface of the second capacitor electrode, and a surface of the capacitor dielectric form a plane; selectively etching back the surface of the first capacitor electrode and the surface of the second capacitor electrode with respect to the surface of the capacitor dielectric by wet-chemical or dry etching such that the capacitor dielectric extends beyond both the surface of the first capacitor electrode and the surface of the second capacitor electrode; depositing a barrier layer on the surface of the first capacitor electrode, the surface of the second capacitor electrode, and the surface of the capacitor dielectric after etching; and g) forming a second dielectric on the planarized surface of the layer structure with a second interconnect and a contact via that connects the second capacitor electrode to the second interconnect.