Patent ID: 7457147

Claim:
A memory comprising: a substrate including address lines and active circuitry, the active circuitry including sensing circuitry and address decoding circuitry, the address decoding circuitry in communication with the address lines; addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug operable to be reversibly written to a first resistive state at a first write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage; and at least one reference cell that contributes to a reference level, wherein the sensing circuitry is operative to produce an output that is a function of the resistive state of the activated two-terminal memory plug and the reference level, wherein the at least one reference cell is similar in structure to the two-terminal memory plugs, wherein the addressable two-terminal memory plugs and the at least one reference cell are positioned over the substrate.