Patent ID: 8185723

Claim:
A method comprising: loading a first value into a computer processor, the first value being a floating point number, the computer processor including a plurality of arithmetic logical units (ALUs) including one or more floating point arithmetic logical units (FALUs), wherein a floating point number comprises a sign bit, a first plurality of exponent bits, and a second plurality of significand bits and wherein an integer comprises a plurality of bits, the first value being represented by a value x times a constant A; decomposing the first value into integer and fractional parts, the decomposing of the first value comprising: shifting a rounded integer portion of the first value to generate a second value in a first floating point ALU operation, where the shifting provides an addition of a constant S value to the first value, wherein the rounded integer portion is shifted into rightmost bits of the significand of the first value, generating a third value n f from the second value in a second floating point ALU operation, the third value generated by subtracting the constant S from the second value to generate an integer, extracting a plurality of significand bits from the second value to generate a fourth value in a first integer ALU operation, generating a fifth value r from the third value in a third floating point ALU operation, the fifth value being generated by subtracting the third value times a constant B from x, where B=1/A, and extracting a portion of bits from the fourth value to generate an integer component in a second integer ALU operation; wherein the transformed representation of the first value represented by the third value, the fifth value, and the integer component are stored in a memory or transmitted to an ALU.