Patent ID: 7130219

Claim:
A memory device of an electrically word-erasable non-volatile type, comprising: an array of memory cells arranged in a plurality of rows and columns, each memory cell having a drain terminal, a source terminal, and a bulk terminal; a plurality of first wells of semiconductor material of a first conductivity type, extending parallel to the rows; a plurality of sets of second wells of semiconductor material of a second conductivity type and accommodating said memory cells, each set of second wells extending within a respective one of said first wells, each second well extending in a direction transverse to said rows and accommodating a respective set of memory cells forming a sector; a plurality of main bitlines extending along the columns of said array; a plurality of sets of local bitlines, each set of local bitlines being associated to a respective second well, each local bitline being coupled to the drain terminal of memory cells accommodated in said respective second well and aligned along one of said columns; and a plurality of local-bitline managing circuits, one for each second well, coupled between said main bitlines and said sets of local bitlines for controllably coupling each local bitline to a respective main bitline.