Patent ID: 7944240

Claim:
A buffer of a semiconductor memory apparatus, comprising: a buffering section configured to generate an output signal by buffering an input signal; and a mismatch compensation section configured to generate a control voltage in correspondence with sizes of a second transistor of a same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage, the buffering section as a differential amplifer type circuit receives the input signal and an inverse of the input signal, the mismatch compensation section generates independently a first control voltage and a second control voltage as the control voltage, wherein the first control voltage is a voltage of a node connected to a drain and a gate of the second transistor when its source is applied with a ground voltage, and the second control voltage is the voltage of the node connected to the drain and the gate of the second transistor when its source is applied with a driving voltage.