Patent ID: 7969183

Claim:
A semiconductor device comprising: a pad for connecting between a first intermediate node and an external resistor; a first first-type resistance adjuster connected between said first intermediate node and a first voltage node supplied a first voltage; a second first-type resistance adjuster connected between said first voltage node and a second intermediate node; a third first-type resistance adjuster connected between said first voltage node and said second intermediate node; a first second-type resistance adjuster connected between a second voltage node supplied with a second voltage lower than said first voltage, and said second intermediate node; a second second-type resistance adjuster connected between a second voltage node supplied with a second voltage lower than said first voltage, and said second intermediate node; a first output buffer connected between said first voltage node and a third intermediated node; a second output buffer connected between said second voltage node and said third intermediate node; and a resistance adjuster circuit configured for: adjusting a resistance value of said first first-type resistance adjuster in agreement with a resistance value of said external resistor according to a voltage of said first intermediate node, adjusting a resistance value of said second first-type resistance adjuster in agreement with the resistance value of said first first-type resistance adjuster, adjusting a resistance value of said third first-type resistance adjuster in agreement with the resistance value of said first first-type resistance adjuster, adjusting a resistance value of said first second-type resistance adjuster and a resistance value of said second second-type resistance according to a voltage of said second intermediate node, adjusting a resistance of said first output buffer according to information of adjusting the resistance value of said second first-type resistance adjuster and the resistance value of said third first-type resistance adjuster, and adjusting a resistance of said second output buffer according to information of adjusting the resistance value of said first second-type resistance adjuster and the resistance value of said second second-type resistance adjuster, wherein the resistance value of said external resistor is between the resistance value of said second first-type resistance adjuster and the resistance value of said third first-type resistance adjuster after adjusting the resistance value by said resistance adjuster circuit.