Patent ID: 7981740

Claim:
A method, comprising: forming a first gate electrode structure above a first semiconductor region of a semiconductor device and a second gate electrode structure above a second semiconductor region, said first and second gate electrode structures comprising a gate insulation layer including a high-k dielectric material, a placeholder material and a dielectric cap layer formed above said placeholder material; forming a spacer layer above said first and second semiconductor regions and said first and second gate electrode structures; forming a first offset spacer element selectively on said first gate electrode structure from said spacer layer; forming a strain-inducing semiconductor alloy selectively in said first semiconductor region by using said first offset spacer element to adjust a lateral offset of said strain-inducing semiconductor alloy from said first gate electrode structure; forming a hard mask so as to cover at least said first semiconductor region and said first gate electrode structure and expose at least a portion of said spacer layer formed above said second semiconductor region; and forming a second offset spacer element from said spacer layer on said second gate electrode structure by using said hard mask as an etch mask.