Patent ID: 8329549

Claim:
A method, comprising: forming a protection liner on sidewalls of a first gate stack and a second gate stack, said first and second gate stacks formed on a semiconductor layer and comprising a high-k dielectric material; forming a semiconductor alloy in said semiconductor layer laterally offset from said first gate stack on the basis of a spacer structure comprising a spacer element and an etch stop liner while covering said second gate stack by an etch stop layer and a spacer layer; removing a first cap layer of said first gate stack and said spacer layer covering said second gate stack by performing an etch process; forming an etch mask by depositing a mask material so as to cover a bottom portion of said first and second gate stacks and removing a portion of said mask material to recess the top surface of the etch mask below the top surfaces of the first and second gate stacks and expose a top portion of said first and second gate stacks; removing a second cap layer of said second gate stack in the presence of said etch mask, wherein a top surface of the etch mask is recessed below top surfaces of the first and second gate stacks following removal of the second cap layer; removing said etch mask; and removing a remaining portion of said etch stop layer.