Patent ID: 7927945

Claim:
A method for manufacturing a semiconductor device having a 4F2 transistor, the method comprising: forming a device isolation layer defining an active region on a semiconductor substrate, wherein the active region is disposed in a shape of a vertical stripe; forming gate stacks on the active region of the semiconductor substrate; forming a first interlayer dielectric to fill between adjacent gate stacks; forming a contact hole through the first interlayer dielectric, the contact hole including a first region exposing portions of two facing sides of the adjacent gate stacks, and two second regions extending outwardly from the first region in opposite directions to expand the exposed portions of the two facing sides of the adjacent gate stacks from two diagonally opposed corners of the first region; forming spacer layers on the exposed portions of the two facing sides of the adjacent gate stacks, including filling the two second regions of the contact hole; forming a trench inside the semiconductor substrate by performing an etching process using the spacer layers as an etch mask and then removing the spacer layers; forming first and second landing plugs on the two facing sides of the adjacent gate stacks, respectively, exposed by the first region and the two second regions of the contact hole, on a portion of the semiconductor substrate exposed by removing the spacer layers, and on a lateral side of the trench, wherein the first and second landing plugs partially fill the contact hole while exposing a bottom surface of the trench; filling the trench with a second interlayer dielectric to separate the first and second landing plugs; forming a bit line contact plug connected to the first landing plug and a bit line stack connected to the bit line contact plug; and forming a storage node contact plug connected to the second landing plug and a storage node electrode connected to the storage node contact plug.