Patent ID: 7671417

Claim:
A memory cell array comprising: semiconductor regions disposed on a supporting insulating substrate, each semiconductor region having a first side surface, a second side surface, and a top surface, the first side surface being opposite to the second side surface; memory cells formed in the semiconductor regions, the memory cells being arranged in the form of an array; and insulating regions formed between adjacent the semiconductor regions so as to insulate each semiconductor region; wherein each memory cell formed in a corresponding semiconductor region comprises: a source region disposed in the semiconductor region, the source region including the top surface of the semiconductor region; a drain region disposed in the semiconductor region, the source region including the top surface of the semiconductor region; a front gate region formed on a gate insulating film formed on the first side surface of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region; and a back gate region formed on a gate insulating film formed on the second side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region, wherein the each memory cell shares the source region or the drain region with a adjacent memory cell, the adjacent memory cell being formed in the same semiconductor region including the each memory cell, wherein the each memory cell shares the back gate region with a memory cell in the adjacent semiconductor region in a first direction.