Patent ID: 8253235

Claim:
A semiconductor packaging substrate comprising: a dielectric layer having two longitudinal sides and including a plurality of packaging units and a plurality of electrostatic dissipation regions defined on a surface of the dielectric layer; a plurality of leads formed on the surface of the dielectric layer in each packaging unit; a plurality of first electrostatic guiding traces and a plurality of second electrostatic guiding traces both formed in the electrostatic dissipation regions and attached to the surface of the dielectric layer, wherein at least a first electrostatic guiding trace and at least a second electrostatic guiding trace disposed in each electrostatic dissipation region are separated in equal line spacing and electrically isolated, and the first electrostatic guiding trace is electrically connected to at least one of the leads; and a solder mask formed on the dielectric layer to partially cover the leads but expose the first electrostatic guiding traces and the second electrostatic guiding traces; wherein each electrostatic dissipation region is disposed beside one of the packaging units and adjacent to only one of the two longitudinal sides of the dielectric layer.