Patent ID: 7760561

Claim:
A data output circuit of a semiconductor memory apparatus, comprising: a pre-driver configured to generate pull-up and pull-down signals by driving rising and falling data in active periods of rising and falling clocks, respectively, in response to a state of an output enable signal; a common node; a main driver configured to generate last output data based on the pull-up and pull-down signals and to output the last output data to the common node; an assistant pre-driver configured to generate an assistant drive signal, which is activated when the rising data is different from the falling data, in response to inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal; and an assistant main driver configured to generate assistant last output data in response to input of the pull-up and pull-down signals and the assistant drive signal and to output the assistant last output data to the common node.