Patent ID: 8422314

Claim:
A memory apparatus comprising: a plurality of DRAMs; a data bus connected in parallel to the plurality of DRAMs; an address bus connected in parallel to the plurality of DRAMs; and a common controller configured to control reading and writing of data to and from all of the plurality of DRAMs, wherein the apparatus does not comprise a single-DRAM-dedicated controller dedicated to a single one of the plurality of DRAMs for controlling operations of the single DRAM, wherein, upon receiving a data read request from an external device, the common controller is configured to set a first one of the plurality of DRAMs to an output mode to output data to the data bus and further to set the other ones of the plurality of DRAMs to a standby/refresh mode while the first DRAM is in the output mode, wherein, upon receiving a data write request from an external device, the common controller is configured to set the plurality of DRAMs to a write mode to write data from the data bus simultaneously in all of the plurality of DRAMs.