Patent ID: 8344345

Claim:
A nonvolatile semiconductor memory device comprising: a substrate; first memory wires formed on the substrate to have a stripe shape; a first interlayer insulating layer formed over the substrate and the first memory wires; first memory cell holes which are formed in the first interlayer insulating layer on the first memory wires; first resistance variable layers which are connected to the first memory wires via the first memory cell holes, respectively; first non-ohmic elements formed on the first resistance variable layers, respectively; second memory wires of a stripe shape which are formed on the first interlayer insulating layer such that the second memory wires cross the first memory wires perpendicularly to the first memory wires, respectively; and a second interlayer insulating layer formed over the second memory wires and the first interlayer insulating layer; wherein each of the second memory wires includes a plurality of layers including at least a portion of each of the first non-ohmic elements and has a conductive layer in an uppermost layer of the second memory wire and a semiconductor layer or an insulator layer which is a portion of each of the first non-ohmic elements in a lowermost layer of the second memory wire; each of the first memory wires is connected to the uppermost layer of the second memory wire via a first contact penetrating the first interlayer insulating layer, and the first contact penetrates the semiconductor layer or the insulator layer of the second memory wire; and each of the first non-ohmic elements has a stacked-layer structure including two or more layers, and a portion of the stacked-layer structure is filled into a corresponding one of the first memory cell holes.