Patent ID: 8748996

Claim:
An integrated circuit (IC), comprising: a substrate having a top semiconductor surface including at least one MOS device, said MOS device comprising: a source and a drain region spaced apart to define a channel region; a SiON gate dielectric layer having a plurality of different N concentration portions formed on said top semiconductor surface including over said channel region; a gate electrode on said SiON layer including over said channel region, wherein said plurality of different N concentration portions include (i) a bottom portion extending to a semiconductor interface with said top semiconductor surface having an average N concentration of <2 atomic %, (ii) a bulk portion on said bottom portion having an average N concentration >10 atomic %, and (iii) a top portion on said bulk portion extending to a gate electrode interface with said gate electrode having an average N concentration that is ≧2 atomic % less than a peak N concentration of said bulk portion.