Patent ID: 7609554

Claim:
A method for reducing gate to body field stress in a transistor of a high voltage switching circuit comprising a first NMOS transistor operating in a depletion mode and coupled to the high voltage, a PMOS transistor coupled between the first NMOS transistor and circuit output, a second NMOS transistor operating in an enhancement mode and coupled to the circuit output, and a control circuit coupled to the PMOS and second NMOS transistors, the method comprising: generating a first control signal that changes state at a first predetermined time and enables the circuit output; generating a second control signal that changes state in response to the enabling of the circuit output; and logically combining the first and second control signals for controlling the PMOS transistor and the second NMOS transistor such that the high voltage is switched through the first NMOS transistor and the PMOS transistor to the circuit output and the voltage on a gate connection of the PMOS transistor is greater than 0V in response to the change in state of the second control signal.