Patent ID: 7629656

Claim:
A semiconductor device having a circuit forming region, comprising: a semiconductor substrate, said semiconductor substrate including a first circuit forming region and a second circuit forming region; a first insulating interlayer group provided on said semiconductor substrate and constituted of a first insulating material; a second insulating interlayer group provided on said first insulating interlayer group and constituted of a second insulating material having a dielectric constant lower than that of said first insulating material; and a guard ring which surrounds said circuit forming region, wherein, said first insulating interlayer group includes: i) a contact insulating interlayer which is provided on said semiconductor substrate, ii) a contact plug embedded in said contact insulating interlayer, iii) a gate electrode embedded in said contact insulating interlayer, iv) a first interconnect insulating interlayer provided on said contact insulating interlayer, and v) a first interconnect embedded in said first interconnect insulating interlayer, said first interconnect and said gate electrode being different, with a bottommost surface of said first interconnect being above a topmost surface of said gate electrode, the bottommost surface of said first interconnect and a bottommost surface of said guard ring are substantially coplanar, the bottommost surface of said first interconnect is planar, a top surface of said first interconnect is planar, a bottommost surface of said contact plug is planar, a top surface of said contact plug is planar, said guard ring penetrates through an interface between said first insulating interlayer group and said second insulating interlayer group, and said guard ring is separated from said semiconductor substrate to prevent noise from being transmitted between the first circuit forming region and the second circuit forming region, said guard ring being free of an electrical connector between the guard ring and the semiconductor substrate at the first circuit forming region.