Patent ID: 8023350

Claim:
A system for monitoring memory cells, comprising: refresh circuitry operable to refresh the memory cells, the refresh circuitry being operable to refresh a selected plurality of memory cells with a test refresh rate and to refresh the remaining memory cells with a normal refresh rate that is faster than the test refresh rate; data transfer circuitry coupled to the memory cells, the data transfer circuitry being operable to copy the data stored in selected plurality of memory cells to another storage location before the refresh circuitry refreshes the selected plurality of memory cells with the test refresh rate; data comparison circuitry coupled to the memory cells, the data comparison circuitry being operable to compare at least some of the data stored in the another storage location to at least some of the data stored in the selected plurality of memory cells after the selected plurality of memory cells have been refreshed with the test refresh rate, the data comparison circuitry being further operable to generate a malfunction indication if the data comparison circuitry determines that at least some of the data stored in the another storage location does not match the data stored in the selected plurality of memory cells after the selected plurality of memory cells have been refreshed with the test refresh rate; and repair logic coupled to the comparison circuitry, the repair logic being operable responsive to the malfunction indication to remap accesses to the selected plurality of memory cells to a redundant plurality of memory cells.