Patent ID: 6849897

Claim:
An integrated circuit comprising a nonvolatile memory cell, said integrated circuit comprising: a channel region in a semiconductor substrate; a first dielectric layer on a surface of the channel region; a floating gate of polysilicon on the first dielectric layer; a first buffer layer of SiON in contact with the floating gate; a second dielectric layer comprising a first layer of high temperature oxide in contact with the first buffer layer, a layer of silicon nitride on the first layer of the high temperature oxide, and a second layer of high temperature oxide on the layer of silicon nitride; and a control gate of polysilicon separated from the floating gate by the first buffer layer and the second dielectric layer, wherein the floating gate has a lower first surface covering and in contact with the first dielectric layer, an upper second surface covered by and in contact with the first buffer layer, and peripheral side surfaces extending vertically between the first and second surfaces, the side surfaces not being covered by the first buffer layer.