Patent ID: 7211487

Claim:
A process for forming an electronic device, the process comprising: forming a first trench and a second trench within a substrate, wherein: the first and second trenches are spaced apart from each other; and each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate; forming a first doped region and a second doped region, wherein the first doped region lies within the substrate along the bottom of the first trench, and the a second doped region lies within the substrate along the bottom of the second trench; forming a first dielectric layer lying along the walls and bottoms of the first and second trenches; forming discontinuous storage elements after forming the first dielectric layer; forming a second dielectric layer after forming the discontinuous storage elements; forming a first conductive layer after forming the second dielectric layer; patterning the first conductive layer to form a first gate electrode within the first trench and a second gate electrode within the second trench, wherein: the first gate electrode has an upper surface that lies below the primary surface of the substrate, wherein a first part of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench; and the second gate electrode has an upper surface that lies below the primary surface of the substrate, wherein a second part of the discontinuous storage elements lies between the second gate electrode and the wall of the second trench; removing a third part of the discontinuous storage elements to leave remaining portions of the discontinuous storage elements, including a first portion of the discontinuous storage elements and a second portion of the discontinuous storage elements, wherein: the first portion of the discontinuous storage elements lies within the first trench; the second portion of the discontinuous storage elements lies within the second trench; the first and second portions of the discontinuous storage elements are spaced apart from the primary surface of the substrate; and substantially none of the discontinuous storage elements overlie the primary surface of the substrate between the first and second trenches; forming a third dielectric layer, wherein: a first portion of the third dielectric layer overlies the first gate electrode within the first trench; and a second portion of the third dielectric layer overlies the second gate electrode within the second trench; forming a second conductive layer after forming the third dielectric layer; and patterning the second conductive layer to form a third gate electrode overlying the third dielectric layer, wherein the third gate electrode lies at least partly within the first trench and the second trench.