Patent ID: 7466612

Claim:
A method for testing a memory device provided with a bank which includes a plurality of memory cell blocks (MCBs), each MCB including a plurality of word lines, the method comprising the steps of: a) enabling a test mode signal; b) activating, in response to the test mode signal, MCBs in a subset one by one in a predetermined time period to point to a given word line for each MCB in the subset; c) performing sense, read (or write) and precharge operations on a subgroup of MCBs pointed to the given word line from MCBs in the subset, wherein the performing sense, read (or write) and precharge operations comprises: c1) sensing and amplifying a voltage difference between bit lines, ‘BIT ’and ‘/BIT’, in the subgroup of MCBs pointed to the given word line from MCBs in the subset by providing a burst stop command to activate a sense amplifier control unit to transfer the bit lines to a sense amplifier; c2) reading the amplified voltage difference between the bit lines by transferring the amplified voltage difference between the bit lines to main input/output lines via local input/output lines using block switch transistors; c3) writing data of the local input/output lines which have passed through the block switch transistors via the main input/output lines to the bit lines; and c4) precharging the bit lines and the local input/output lines to a bit-line precharge voltage (VBLP) level.