Patent ID: 8495435

Claim:
An apparatus, comprising: an address swap cache; and a memory segment swap logic configured to: detect a reproducible fault at a first physical address targeting a first physical memory segment in one of a plurality of memory devices; in response to the detection of the reproducible fault, remap the first physical address to a second physical address, the second physical address targeting a second physical memory segment in one of the plurality of memory devices; store the first and second physical addresses in an entry in the address swap cache; receive a memory transaction targeting the first physical address; perform a lookup in parallel with a memory controller sending the memory transaction to the one of the plurality of memory devices containing the memory segment targeted by the first physical address, the lookup to identify the entry in the address swap cache storing the first physical address; in response to the identification, flag the memory transaction invalid and swap the second physical address into the memory transaction for the first physical address, wherein said swap of the first and second physical addresses includes replacement of the first physical address in the memory transaction with the second physical address; and provide the memory controller with the second physical address for a retry of the memory transaction.