Patent ID: 7643362

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of main columns, the plurality of main columns each having a plurality of bit lines, and a plurality of memory cells that are connected to the plurality of bit lines, respectively; a redundancy cell array having a plurality of redundancy columns, the plurality of redundancy columns each having a plurality of bit lines, and a plurality of redundancy cells that are connected to the plurality of bit lines, respectively; a plurality of sense amplifiers connected to each of the plurality of bit lines of the memory cell array and the plurality of bit lines of the redundancy cell array, each of the plurality of sense amplifiers reading out data of the plurality of memory cells or the plurality of redundancy cells through the plurality of bit lines; a detection circuit which detects, based on the data read out by the plurality of sense amplifiers, a bad bit line at an end of a bad column of the memory cell array; and a repair circuit which repairs the bad column of the memory cell array by use of the plurality of redundancy columns and repairs an adjacent column which lies adjacent to the bad column on the bad bit line side detected by the detection circuit by use of the plurality of redundancy columns.