Patent ID: 8053908

Claim:
A semiconductor device comprising a semiconductor element having, over the surface thereof, an insulating layer having therein an interconnect, a substrate over which the semiconductor element is to be mounted, and a plurality of connection terminals provided over the surface of the insulating layer of the semiconductor element and the surface of the substrate at a certain pitch, the semiconductor element being mounted over the substrate by solder-joining the connection terminals over the surface of the insulating layer of the semiconductor element with the connection terminals of the substrate and the connection between the semiconductor element and the substrate being sealed with a encapsulation resin, wherein: a substantially spherical core is provided inside of the solder at the connection between the semiconductor element and the substrate; the thickness of the solder placed between the connection terminals provided over the surface of the insulating layer of the semiconductor element and the core is adjusted to 1/10 or less of a terminal pitch of the connection terminals over the surface of the insulating layer; and a Young' s modulus and a linear coefficient of expansion of the encapsulation resin to be filled between the semiconductor element and the substrate, and a yield stress of the solder at room temperature are adjusted to satisfy the following inequalities: 1 GPa<(Young's modulus of the encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa.