Patent ID: 8304883

Claim:
A semiconductor device comprising a substrate with wiring pattern on a first surface; a first semiconductor element disposed on the first surface; mold resin sealing the first semiconductor element and a portion of the wiring pattern, the mold resin has a glass transition temperature in the range of 100-160° C., a coefficient of thermal expansion in the temperature region below the glass transition temperature in the range of 20-30 ppm, a coefficient of thermal expansion in the temperature region above the glass transition temperature in the range of 80-120 ppm, a longitudinal modulus in the temperature region below the glass transition temperature in the range of 1-20GPa, and a longitudinal modulus in the temperature region above the glass transition temperature in the range of 0.1-1.0 GPa; a second semiconductor element with connecting terminals electrically connected to the wiring pattern; and a space between the mold resin and second semiconductor element.