Patent ID: 7087470

Claim:
A method of fabricating semiconductor devices, comprising: (a) providing an N-well and a P-well in a substrate; selecting a first thickness of a first thermal gate oxide layer to be formed over said P-well and selecting a second thickness of a second thermal gate oxide layer to be formed over said N-well, said first and second thicknesses selected so a first gate tunneling leakage current of said first thermal gate oxide layer is less than about 3 times a second gate tunneling leakage current of said second thermal gate oxide layer; selecting one or more ion implantation doses and species combinations based on a relationship between ion implantation species and ion implantation species dose and a first thermal oxide growth rate and a second thermal oxide growth rate; ion implanting either said N-well, said P-well or both said N-well and said P-well using said selected one or more ion implantation and species combinations; and simultaneously growing said first thermal gate oxide layer at said first rate on a surface of said substrate over said P-well and growing said second thermal gate oxide layer at said second rate on said surface of said substrate over said N-well, said first rate different than said second rate.