Patent ID: 8018006

Claim:
A semiconductor device comprising: a semiconductor substrate including a lower substrate, a thin semiconductor layer formed over said lower substrate, and an insulating layer formed between said lower substrate and said semiconductor layer so as to electrically insulate the thin semiconductor layer from the lower substrate; an active transistor area formed at a part of said thin semiconductor layer with a base region formed along a surface of the thin semiconductor layer, an emitter region formed in said base region, a buried collector region buried in said thin semiconductor layer so as to contact said insulating layer, a collector region contacting said buried collector region, an emitter contact electrically connected to said emitter region, a base contact electrically connected to said base region and a collector contact electrically connected to said buried collector region via said collector region, the active transistor area being configured to operate at an emitter current at least in the order of mA (milli-ampere); and an isolation trench extending through said thin semiconductor layer to contact said insulating layer and surrounding said active transistor area with a distance in the order of μm (micron) from the active transistor area and with a space area of more than 50 μm 2 provided between the active transistor area and said isolation trench.