Patent ID: 8238409

Claim:
A method of reading a plurality of chip sample values of a sequence of chips in an CDMA system at tap positions in a digital delay line having a starting point and an end point for delaying symbols of a signal received in a receiver of a CDMA system, the method comprising: reading the plurality of chip sample values in the digital delay line at the tap positions according to a chip rate clock having a chip rate clock cycle and a chip rate clock frequency, said taps being used to read signal samples before they are passed to despreader units, oversampling the received signal according to a sample rate clock having a sample rate clock cycle and a sample rate clock frequency to produce a plurality of chip sample values supplied in the digital delay line, the sample rate clock frequency being higher than the chip rate clock frequency, shifting the tap positions towards either the starting point or the end point of the digital delay line, and adjusting the chip rate clock cycle when shifting the tap positions, wherein the adjusting of the chip rate clock cycle further includes: shortening the chip rate clock cycle of the chip rate clock when shifting the tap positions towards the starting point of the digital delay line, or lengthening the chip rate clock cycle of the chip rate clock when shifting the tap positions towards the end point of the digital delay line reading the plurality of chip sample values in the digital delay line at the tap positions according to a chip rate clock having a chip rate clock cycle and a chip rate clock frequency.