Patent ID: 6977519

Claim:
A power gate structure having a fixed supply voltage and an adjustable ground voltage, comprising: an NFET transistor; a PFET transistor electronically coupled with the NFET transistor, NFET drain to PFET source and NFET source to PFET drain, respectively; an adjustable virtual ground electronically coupled with the NFET drain and PFET source; a fixed global ground electronically coupled with the NFET source and PFET drain; and a logic circuit having a circuit ground electronically coupled with the virtual ground and a body ground electronically coupled with the global ground, wherein the virtual ground is adjustable to a clamping voltage between the fixed source voltage and the fixed global ground voltage by means of: adjusting the PFET source voltage in accordance with an electrical signal applied to the gate of the PFET in a source-follower mode; and adjusting the PFET threshold voltage by applying a reverse well bias to the PFET Nwell connection.