Patent ID: 8489786

Claim:
A method for use with an I 2 C bus configuration, comprising: receiving a clock signal at a clock input of a slave device coupled to a serial clock line of the I 2 C bus configuration; sensing edges of the clock signal at a bi-directional input/output port of a slave device coupled to the serial clock line of the I 2 C bus configuration; for every sensed edge, capturing by the slave device a command code present on a serial data line of the I 2 C bus configuration; determining by the slave device whether the captured command code is one of plurality of slave device supported command codes; if yes, the slave device driving the serial data line of the I 2 C bus configuration to a logic low state indicative of an acknowledgement of the command code; and if no, the slave device inhibiting driving of the serial data line of the I 2 C bus configuration to the logic low state so as to indicate a no acknowledgement of the command code.