Patent ID: 8249849

Claim:
A power source network analyzing apparatus comprising: a processor, wherein the processor is programmed to execute: partitioning, based on design information of an integrated circuit including a plurality of wiring layers, a power source network analysis object area of the integrated circuit into partitioned power source network analysis object areas, searching for a via connecting a first layer and another second layer of the plurality of wiring layers, outside a border of a partition of the partitioned power source network analysis object area in the integrated circuit and setting a position of the searched via as a reference position outside the border of the partition, extracting a wiring up to the reference position as a border adjacent area that electrically influences the partitioned power source network analysis object area, adding the border adjacent area to the partitioned power source network analysis object area, generating a resistance model of the partitioned power source network analysis object area with the border adjacent area added thereto; and performing power source network analyzing processing on the generated resistance model.