Patent ID: 8564064

Claim:
A placement of FET devices, comprising: FET devices constructed over a principal surface of a support member, said FET devices comprising gate structures and electrodes adjoining said gate structures, wherein said electrodes comprise fins and an epitaxial layer which merges said fins together, furthermore said fins serve as device bodies underneath said gate structures, wherein said FET devices are so placed that said gate structures are in a parallel configuration separated from one another by a first distance, and that said fins of differing ones of said FET devices line up in essentially straight lines, wherein said electrodes of differing ones of said FET devices are separated from one another by a cut defined by opposing facets of said electrodes, wherein said opposing facets are essentially perpendicular to said principal surface and reach down to said principal surface, wherein said cut runs essentially in parallel with said gate structures, and wherein said opposing facets define a width for said cut, wherein said width is smaller than one fifth of said first distance that spaces said gate structures apart; and wherein said FET devices are characterized as being non-planar devices.