Patent ID: 7309899

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode structure formed on the gate insulating layer, the gate electrode structure comprising a lower gate electrode layer and a cap gate layer; and a side wall structure which includes a nitride side wall spacer, and includes an oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer, the oxide layer formed using at least one of chemical vapor deposition and thermal annealing, wherein a thickness of the oxide layer between the semiconductor substrate and the nitride side wall spacer is greater than a thickness of the gate insulating layer, so as to prevent diffusion of nitrogen from the nitride side wall spacer to the semiconductor substrate, and wherein a height of the gate electrode structure is substantially equal to a height of the side wall structure after completion of the semiconductor device.