Patent ID: 8122173

Claim:
A serial peripheral interface (SPI) circuit, comprising: a master device, comprising: a first chip enable pin; a first serial clock pin; and a data input and output common pin; and a slave device, comprising: a second chip enable pin, electrically connected to the first chip enable pin of the master device; a second serial clock pin, electrically connected to the first serial clock pin of the master device; a serial data input pin, electrically connected to the data input and output common pin of the master device; and a serial data output pin, electrically connected to the data input and output common pin of the master device, wherein when a read instruction is transferred from the master device to the slave device, the master device is set in a read status and the slave device outputs data to the master device via the serial data output pin in response to the read instruction, and when a write instruction is transferred from the master device to the slave device, the master device is set in a write status and the master device transfers data to the slave device via the serial data input pin for storing therein in response to the write instruction.