Patent ID: 8569168

Claim:
A method of forming a semiconductor structure comprising: forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an interlayer dielectric (ILD) to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD and unrecessed edges with respect to the ILD; and filling the recesses with an insulating material to leave the un-recessed edges of the first conductive spacers as vias to subsequent wiring features.