Patent ID: 8324024

Claim:
A method for production of packaged electronic components ( 15 ) having integrated functional elements ( 3 ), comprising: a) providing a mount substrate ( 1 ) and a cover substrate ( 6 ); b) fitting the functional elements ( 3 ) to the mount substrate ( 1 ) within predetermined grid areas ( 2 ); c) fitting bonding elements ( 4 ) to the mount substrate ( 1 ) within predetermined grid strips ( 8 ) which run between the grid areas ( 2 ), wherein the grid areas ( 2 ) and the grid strips ( 8 ) are arranged within a predetermined grid system formed by markings or masks on the mount substrate ( 1 ) or by a positioning process for the functional elements ( 3 ) corresponding to an imaginary grid on the mount substrate, and producing connecting contacts ( 5 ) between the functional elements ( 3 ) and the bonding elements ( 4 ); d) fitting a microframe structure ( 7 ) composed of glass with a height of 3 to 10 μm to the lower face of the cover substrate ( 6 ) and/or to the upper face of the mount substrate ( 1 ), with cavities ( 11 ) being produced corresponding to the grid areas ( 2 ), and with channels ( 17 ) being produced corresponding to the grid strips ( 8 ); e) introducing a macrostructure ( 8 , 9 ) at least on the upper face of the cover substrate ( 6 ) or at least on the lower face of the cover substrate ( 6 ) by removal of surface areas, with trenches ( 9 ) being produced corresponding to the grid strips ( 8 ) on the mount substrate ( 1 ); f) joining together the mount substrate ( 1 ) and cover substrate ( 6 ) to form a composite substrate, with the functional elements ( 3 ) being packaged; and g) splitting the composite substrate along a predetermined track within the grid strips ( 8 ), with the composite substrate being broken up into individual components ( 15 ), and with the bonding elements ( 4 ) of the separated components ( 15 ) being exposed at the same time.