Patent ID: 7076571

Claim:
A method for obtaining device addresses over a bus, comprising: sending one or more sets of commands on the bus, each set of commands being intended to read one device address, wherein sending each command includes driving the bus to a high voltage at the beginning of a bit time and then presenting a high impedance to the bus at a predetermined time after the beginning of the bit time; writing a first address on the bus, by a first device driving one or more of a plurality of first values, which define the first address, on the bus in response to a first set of commands, and wherein, in response to detecting the high voltage on the bus for each command, the first device maintains the high voltage for no more than a first predetermined interval in the bit time if a logic value is being driven, and a second predetermined interval, longer than the first interval, in the bit time if a different logic value is being driven; and if, while writing the first address, the bus fails to display any one of the driven plurality of first values, because a second device is simultaneously writing a second address on the bus, then the first device stops writing the first address and does not attempt to write the first address again until after the second device has finished writing the second address, wherein the first and second addresses uniquely identify the first and second devices.