Patent ID: 6873011

Claim:
A transistor comprising: a P-substrate; a first diffusion region and a second diffusion region having N conductivity-type ions formed in said P-substrate, wherein said first diffusion region comprises an extended drain region; a drain diffusion region containing N+ conductivity-type ions, forming a drain region in said extended drain region; a plurality of spaced apart P-field blocks formed in said extended drain region; wherein said P-field blocks have different sizes; wherein a smallest size P-field block is located nearest to said drain region; wherein said P-field blocks are used for generating junction fields; a source diffusion region having N+ conductivity-type ions, forming a source region in an N-well formed by said second diffusion region, wherein a largest size P-field block is located nearest to said source region; a channel, formed between said drain region and said source region; a polysilicon gate electrode, formed over said channel to control a current flow in said channel; a contact diffusion region containing P+ conductivity-type ions, forming a contact region in said N-well formed by said second diffusion region; and an isolated P-well formed in said N-well formed by said second diffusion region for preventing from breakdown; wherein said isolated P-well formed in said second diffusion region encloses said source region and said contact region.