Patent ID: 7465988

Claim:
A semiconductor device comprising: a dummy region extending in a first direction, the dummy region including an upper portion having first and third grooves extending in a second direction substantially perpendicular to the first direction, the third groove being disposed under the first groove to be communicated with the first groove, the dummy region having an upper face portion doped with impurities; active regions including an upper portion having second and fourth grooves extending in the second direction, the fourth groove being provided under the second groove to be communicated with the second groove, the active region having an upper face portion doped with impurities; an isolation layer pattern disposed between the dummy region and the active regions and between the active regions to electrically insulate the dummy region from the active regions and the active regions from one another; gate electrodes each including a first portion and a second portion, the first portion extending in the second direction on the isolation layer pattern to fill the first and second grooves, the second portion being connected to the first portion, the second portion filling the third and fourth grooves, the second portion having a void; gate mask layer patterns each formed on the gate electrodes; and gate oxide layer patterns disposed between the dummy region and the gate electrodes and between the active regions and gate electrodes.