Patent ID: 8097492

Claim:
A method for fabricating a Silicon Based Package (SBP) comprising the steps of: starting with a wafer composed of silicon and having a first surface and an initial reverse surface which are substantially planar as the base for the SBP; forming a first interconnection structure over the first surface; then forming a protective overcoat layer over the interconnection structure; forming a releasable adhesive layer over said protective overcoat layer; forming a temporary bond between the releasable adhesive layer of the SBP and a wafer holder, with the wafer holder being a rigid structure; thinning the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP; forming Vertical Sidewall Through Via (VSTV) holes which extend through the UTSW with the VSTV holes having bases and substantially vertical sidewalls; and forming metallization in the VSTV holes with the metallization extending through the UTSW.