Patent ID: 8443131

Claim:
A non-volatile memory device comprising: an array of non-volatile memory cells which stores a first and second operational information for the non-volatile memory device, wherein the first and second operational information are different; and a volatile memory section which stores the first and second operational information only while power is being supplied to the non-volatile memory device, wherein the volatile memory section comprises: a first volatile memory section having an array configuration from which the first operational information stored therein with address assignment is read out in response to individual address selections, the addresses linked with corresponding portions of the first operational information, wherein updated first operational information is stored in the array of non-volatile memory cells before the first volatile memory section is updated; and a second volatile memory section, having a latch circuit configuration, comprising one or more latch circuits, and allowing immediate access to the second operational information stored therein in response to power-on, wherein the second volatile memory section constantly and repetitiously outputs in logically processable form all the second operational information stored therein.