Patent ID: 8625322

Claim:
A memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate, the memory further comprising: a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes; a plurality of non-volatile re-programmable memory elements individually connected through inline circuits between the bit line pillars and the word lines adjacent the crossings thereof; a sheet electrode is connected in series in each inline circuit, said sheet electrode having an edgeside surface in contact with a non-volatile re-programmable memory element and a broadside surface in contact with a word line at each of the crossings; the edgeside surface having an area smaller than that of the broadside surface such that the sheet electrode provides a current path having a cross-sectional area determined by the area of the edgeside surface; and the area of the edgeside surface being dependent on a thickness of the sheet electrode.