Patent ID: 6884710

Claim:
A method of forming a semiconductor device having a multi-layer line, comprising: forming an insulating layer on a substrate containing circuit devices; forming a lower copper line on the insulating layer; forming an Interlayer insulating layer on the lower copper line; patterning the Interlayer insulating layer to form a groove in an upper surface thereof, and forming a via contact hole in a lower surface of the groove, thereby exposing a portion of the lower copper line; forming a concave recess at the exposed portion of the lower copper line, the concave recess being vertically aligned with, and arranged below, the via contact; and forming a patterned barrier layer at a bottom portion of the concave recess, along a sidewall of the via con tact. and along the lower surface and sides of the groove: filling the groove and via contact with Copper to form en upper copper line, thereby directly electrically connecting the upper copper line, the via contact and the lower copper line.