Patent ID: 7239540

Claim:
A semiconductor memory device comprising: a memory cell array in which memory cells each comprising variable resistive elements which store three or more multi-level information depending on a change in electric resistance are arranged in row direction and column direction, a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction are provided, respective one ends of the variable resistive elements of the memory cells in the same row are connected to the same row selection line and respective the other ends of the variable resistive elements of the memory cells in the same column are connected to the same column selection line; a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected, and supplies a second voltage different from the first voltage when the readout is not selected, to each of the column selection lines; a row readout voltage supply circuit which supplies the second voltage to each of the row selection lines at the time of readout; a sense circuit which senses a current flowing in a selected row selection line separately from a current flowing in unselected row selection lines and senses an electric resistance state of a selected memory cell at the time of readout; and a row voltage displacement prevention circuit which prevents a displacement in supplied voltage level in at least the selected row selection line at the time of readout; wherein the row readout voltage supply circuit supplies the second voltage to at least one of the selected row selection lines through the row voltage displacement prevention circuit at the time of readout.