Patent ID: 7596024

Claim:
A nonvolatile memory comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix in row and column directions; a plurality of first word lines; a plurality of second word lines; and a plurality of bit lines, wherein: in the plurality of memory cells, each of a first memory cell and a second memory cell includes a first memory transistor and a second memory transistor which are connected in series; a gate electrode of the first memory transistor of the first memory cell is connected to one of the first word lines; a gate electrode of the second memory transistor of the first memory cell is connected to one of the second word lines; one of a source region and a drain region of the first memory transistor of the first memory cell is connected to a first bit line; one of a source region and a drain region of the first memory transistor of the first memory cell is connected to a second bit line; one of a source region and a drain region of the first memory transistor of the second memory cell is connected to a second bit line; and one of a source region and a drain region of the second memory transistor of the second memory cell is connected to a third bit line.