Patent ID: 7391095

Claim:
A semiconductor device comprising a MOS transistor arranged on a SOI layer of a SOI substrate, wherein said MOS transistor includes: a gate electrode arranged on said SOI layer through a gate insulating film; first and second semiconductor regions arranged in a surface of said SOI layer outside each of the side surfaces of said gate electrode along the gate length; a first partial trench isolation insulating film formed along a gate length across a channel region formed in the surface of said SOI layer under said gate electrode thereby to divide said first semiconductor region across the gate length into a plurality of divisions along the gate width; and a third semiconductor region in contact with a side surface of said first partial trench isolation insulating film opposite to said gate electrode in said first semiconductor region to reach a buried oxide film from the surface of said SOI layer; wherein said first partial trench isolation insulating film has a well region as an underlying layer containing the impurities of the conduction type opposite to that of said first semiconductor region, and wherein said third semiconductor region is of the same conduction type as and in contact with said well region.