Patent ID: 8330490

Claim:
An interlock circuit comprising: an input delay unit that delays a plurality of input signals that includes a first input signal and a second input signal, provides a plurality of delayed input signals that includes a first delayed input signal and a second delayed input signal, and provides a plurality of exclusive input signals that includes a first exclusive input signal and a second exclusive input signal by performing a logical operation on the plurality of delayed input signals; and an output suppressing unit that provides a plurality of output signals that includes a first output signal and a second output signal, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals, the output suppressing unit enables the first and second output signals based on the first and second exclusive input signals, the first and second input signals, and the first and second delayed input signals, disables the first output signal based on the first input signal and the second output signal, and disables the second output sinal based on the second input signal and the first output signal.