Patent ID: 7940555

Claim:
A row decoder, for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines, said row decoder having a hierarchical architecture and comprising: first and second global wordlines; a global decoder configured to address the first and second global wordlines according to first address signals; and a local decoder, operatively coupled to said global decoder and configured to address a selected array wordline of the plurality of array wordlines according to values of said first and second global wordlines and of second address signals, said local decoder including: a first circuit branch configured to provide, when said first global wordline is addressed, a first current path between said selected array wordline and a first biasing source during a reading operation; and a second circuit branch configured to provide, when said second global wordline is addressed, a second current path, distinct from said first current path, between said selected array wordline and a second biasing source during a programming operation.