Patent ID: 7280945

Claim:
A method of determining whether selected semiconductor test structures are susceptible to systematic failure during a particular photolithography process, comprising: a) performing a rigorous type optical simulation of a first photolithography process on a plurality of first test structure representations to produce a simulated final resist pattern of the first test structure representations; b) obtaining a plurality of measurements of the simulated final resist pattern of the first test structure representations; c) performing a sparse type optical simulation of the first photolithography process on a second test structure representation based on a model of the first photolithography process, the model being generated from the obtained measurements, the sparse type simulation producing a simulated final resist pattern of the second test structure representation; (d) repeating operations (a) through (c) for a plurality of different process settings to thereby produce a plurality of simulated final resist patterns of the second test structure representation; and (e) determining and storing whether a product structure that is fabricated based on a pattern representation similar to the second test structure representation is susceptible to systematic failure based on the plurality of simulated final resist patterns of the second test structure representation.