Patent ID: 8441042

Claim:
An electrical interconnect structure having thin film transistors comprising: a substrate, a first dielectric atop the substrate and containing a plurality of conductors wherein some of said conductors form conducting lines and/or vias, and other conductors form a gate electrode of said thin film transistors; a selective metal diffusion barrier and an insulating material atop said gate electrode; a first semiconductor having spaced-apart doped source and drain regions with a channel disposed therebetween atop said insulating material, wherein said first semiconductor is a polycrystalline CdSe semiconductor formed at temperatures below 450° C.; a second dielectric having a plurality of conductors where some conductors form conducting lines and/or vias, and other conductors form contacts to said source and drain regions of said thin film transistors; a second semiconductor having spaced-apart doped source and drain regions with a channel disposed therebetween atop said gate electrode, wherein said second semiconductor is a polycrystalline CdSe semiconductor formed at temperatures below 450° C.; a third dielectric having a plurality of conductors where some conductors form conducting lines and/or vias, and other conductors form contacts to said source and drain regions of said thin film transistors; a germanide region in contact with said conductors forming said source and drain contacts.