Patent ID: 7471566

Claim:
A memory system comprising: a plurality of strings of charge storage transistors for storing different charge states, each of said strings including two select transistors, each of said strings connected between one of a plurality of bit lines and a source line, said strings controlled by a common set of word lines, wherein at least a first transistor in a first string of the strings and adjacent to one of the two select transistors in the first string is in a desired charge storage state; a circuit applying a program voltage level through one of the word lines to a control gate that is capacitively coupled with a second transistor in a second string of the strings different from the first string to program the second transistor, said second transistor separated from the source line by three or more charge storage transistors in said second string when charge storage transistors closer to the source line than the bit line connected to the second string are programmed or separated from the bit line that is connected to the second string by three or more charge storage transistors in said second string when charge storage transistors closer to such bit line than the source line are programmed; and said circuit coupling voltage levels to at least some of the transistors in the first string through some of the word lines to boost at least one electrical potential of channel regions of the first string of transistors and to reduce program disturb, wherein the at least one electrical potential of the channel regions of transistors in the first string is boosted so that breakdown at the drain or source side of the one select transistor in the first string is reduced to such an extent that it does not result in a change of the first transistor's desired charge storage state to a different charge state.