Patent ID: 7852444

Claim:
A thin film transistor array panel comprising: a substrate; a plurality of gate lines formed on the substrate; a plurality of data lines formed on the substrate and intersecting the gate lines; a gate insulating layer formed on the gate lines; a plurality of thin film transistors, each of the thin film transistors including a gate electrode connected to one of the gate lines, a source electrode connected to one of the data lines, and a drain electrode; a plurality of color filters formed on the thin film transistor and the gate insulating layer; a passivation layer formed on the color filters; and a plurality of pixel electrodes formed on the passivation layer, each of the pixel electrodes connected to one of the drain electrodes, each of the pixel electrodes having a generally chevron shape and covering at least a portion of the data line such as to form a fully-covered segment and a non-covered segment of the data line, wherein a width of the fully-covered segment of the data line is fully covered by the chevron shape of the pixel electrode.