Patent ID: 8367469

Claim:
A method of packaging one or more semiconductor dies, the method comprising: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism; attaching a second die in a flip-chip configuration to the substrate, wherein the second die is coupled to the first die for electrical communication via connectors embedded in the substrate and via connectors embedded in the chip-scale frame; and coupling the second die to the heat sink.