Patent ID: 7800973

Claim:
A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix including a plurality of word lines and a plurality of bit lines; a plurality of blocks, each of the blocks including the memory cells connected to a plurality of word lines; a plurality of row decoder circuits, one of the plurality of row decoder circuits selecting one of the plurality of word lines and applying voltages to at least two word lines in a selected block, one of the row decoder circuits being provided for a corresponding one of the blocks; a plurality of first transistors having a first conductivity type, a source of one of the first transistors being connected to a corresponding one of the plurality of word lines, two or more of the plurality of first transistors being included in one of the row decoder circuits; a plurality of second transistors having a second conductivity type opposite to the first conductivity type, a drain of the second transistor being connected to a gate of the first transistor, at least one of the plurality of second transistors being included in one of the row decoder circuits; a plurality of third transistors having the first conductivity type, a source of the third transistor being connected to a source of the second transistor, a gate of the third transistor being connected to a gate of the first transistor, at least one of the plurality of third transistors being included in one of the row decoder circuits; a plurality of well regions in each of which the second transistor is formed, the plurality of well regions having the first conductivity type, one of the well regions being formed for a corresponding one of the blocks; and wherein when a selected word line in a selected block is set to a first voltage which is higher than a power supply voltage, the third transistor corresponding to the selected block applies a second voltage to the source of the second transistor corresponding to the selected block, the second transistor corresponding to the selected block applies a second voltage to the gate of the first transistor corresponding to the selected block, the second voltage is higher than the first voltage, one well region corresponding to one block is separated from another well region corresponding to another block, two or more of the plurality of well regions are arranged in a direction parallel to one of the word lines on one end side of the word lines in the memory cell array.