Patent ID: 7440885

Claim:
A system that deterministically evaluates operations of a circuit design comprising: an application module that determines a transaction for execution by a design under test (DUT); a hardware transactor that translates the transaction into a set of commands representing the transaction; a hardware channel controller that delivers the set of commands representing the transaction to the DUT; an event dispatcher that receives a set of events from the DUT that includes results of the execution of the set of commands; a clock that can be started by the application module and that can be stopped by the hardware transactor to implement deterministic clock control such that the clock control is accurate to one clock cycle and allows the set of events to occur synchronously without latency effects, and wherein the hardware transactor gathers data while the clock is stopped and forwards data to multiple output channels simultaneously when the clock is restarted to allow for execution of multiple independent parallel transactions; and a source level debugger that monitors the DUT during the execution of the set of commands, wherein the source level debugger determines the occurrence of an event-wait condition, halts the operation of the DUT, services the event-wait condition, and resumes the operation of the DUT, thereby preventing the application module and the DUT from executing concurrently based on the event-wait condition; wherein the set of events can be viewed in real-time or recorded for later review and comparison with a set of expected or predicted events to evaluate performance the DUT.