Patent ID: 8803554

Claim:
A clock switching circuit comprising: a first clock domain including a first enable generation logic coupled to a first enable synchronization logic, the first enable synchronization logic generating a first clock enable in response to an input from the first enable generation logic, the first clock domain further including a first logic gate that receives a first clock signal and outputs the first clock signal as a first clock output according to the first clock enable; a second clock domain including a second enable generation logic coupled to a second enable synchronization logic, the second enable synchronization logic generating a second clock enable in response to an input from the second enable generation logic, the second clock domain further including a second logic gate that receives a second clock signal and outputs the second clock signal as a second clock output according to the second clock enable; a first feedback path from first clock domain to the second clock domain; a second feedback path from the second clock domain to the first clock domain; and a missing clock detection circuit that detects absence of the second clock signal, wherein if the second clock signal is missing, the missing clock detection circuit sends a CLK OFF signal to the second enable synchronization logic that breaks the second feedback path such that an output of the clock switching circuit is switched from the second clock signal to the first clock signal in response to the CLK OFF signal.