Patent ID: 8060723

Claim:
A memory management device comprising: an execution control circuit configured to execute at least one task; a memory divided into a plurality of segments, and configured to store data in units of segments; an assignment control circuit configured to assign to a task a buffer ID identifying one of a plurality of buffer spaces, which are logical address spaces; an address conversion circuit configured to convert a logical address in a buffer space into a physical address; a state storage circuit configured to store, as segment assignment information, the association between a buffer space and a segment by associating a buffer ID and a segment ID; a segment queue configured to store a segment ID of a segment available for assignment; and a buffer queue configured to store a buffer ID of a buffer space available for assignment, wherein the state storage circuit includes a plurality of register groups each including a plurality of segment registers, each register group being associated with one of the plurality of buffer spaces, and a segment register storing a range number identifying a range of logical addresses in the associated buffer space, the assignment control circuit, upon receipt of a buffer acquisition request requesting assignment of a buffer space that includes at least one segment, sets up association between a buffer space and a segment by acquiring a buffer ID and at least one segment ID from the buffer queue and the segment queue, respectively, and by recording the at least one segment ID thus acquired in at least one segment register in the register group associated with the buffer ID thus acquired, and the address conversion circuit, upon receipt of an access request designating a destination of access with a logical address, converts a logical address into a physical address by referring to segment assignment information output from the state storage circuit, identifying a range number which occurs in the register group associated with a task requesting the access and which is associated with the designated logical address, acquiring a segment ID stored in the segment register associated with the range number, and identifying a physical address associated with the segment ID.