Patent ID: 7335599

Claim:
A semiconductor processing method, comprising: providing a substrate; forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, second, and third semiconductor layers; and forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers; wherein said step of forming each of the plurality of lateral void gap isolation regions comprises: forming a first nitride spacer layer on the sidewalls of an aperture; depositing an oxide layer on the first nitride spacer layer; forming a second nitride spacer layer on the oxide layer such that the oxide layer is sandwiched between the first nitride spacer layer and the second nitride spacer layer; and etching the oxide layer in order to create a void between the first and second nitride spacer layers, the etching being conducted selective to the first and second nitride spacer layers and adjacent semiconductor layers.