Patent ID: 8039042

Claim:
A method of fabricating an electron source having a self-aligned gate aperture, the method comprising: providing a substrate; depositing a first conductive layer; depositing nano-structures on the first conductive layer; embedding the nano-structures with an embedding material; removing the embedding material from the top portion of the nano-structures so that part of said nano-structures protrudes above the surface of the embedding material forming an emitter layer; conformally depositing an insulator over the emitter layer such that a post forms from each said protruding part of the nano-structure; depositing a second conductive layer over the insulator; and removing the second conductive layer and the insulator from the nano-structures such that apertures are formed in the second conductive layer and at least the ends of the nano-structures are exposed at the centers of said apertures; wherein removing the insulator and the second conductive layer from the nano-structures includes: spin-coating a positive photoresist over the second conductive layer, wherein the photoresist is substantially thinner at portions over the posts than at portions between the posts; globally exposing said photoresist with UV illumination such that, after resist development, a mask is formed with openings only on top of the posts; etching the second conductive layer and the insulator using the mask.