Patent ID: 8521914

Claim:
A processing system, comprising: a receiving device; a bus having a first channel, a second channel, a third channel, and a fourth channel; and a sending device configured to: address the receiving device via the first channel for write operations, read from the receiving device via the second channel, write to the receiving device via the third channel, address the receiving device via the fourth channel for read operations, provide a control signal to the receiving device indicating whether the fourth channel is being used to address the receiving device or to write first payload write data to the receiving device, and select between: a first bus transmission mode wherein payload write data is to be written to the receiving device via the third channel; and a second bus transmission mode wherein the first payload write data is to be written to the receiving device via the third channel during a first clock cycle and second payload write data is to be concurrently written to the receiving device via the first channel during the first clock cycle, wherein the first payload write data is associated with a first write operation and the second payload write data is associated with a second write operation, and wherein the first and second payload write data are distinct from address and control information.