Patent ID: 8084814

Claim:
A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type being higher in concentration than the first semiconductor layer and provided so as to be in contact with the first semiconductor layer on a side of a first principal surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type being lower in concentration than the second semiconductor layer and provided so as to be in contact with the second semiconductor layer; a fourth semiconductor layer of a second conductivity type being higher in concentration than the first semiconductor layer and provided so as to be in contact with the third semiconductor layer; a fifth semiconductor layer of the second conductivity type being higher in concentration than the first semiconductor layer and provided so as to be in contact with the first semiconductor layer on a side of a second principal surface of the first semiconductor layer; a sixth semiconductor layer of the first conductivity type provided selectively on a surface of the fifth semiconductor layer; a MOS gate structure including a gate insulating film being in contact with a portion of the fifth semiconductor layer put between the first semiconductor layer and the sixth semiconductor layer, and a gate electrode being in contact with the gate insulating film; a first electrode being in contact with at least one part of the fifth semiconductor layer; and a second electrode being in contact with at least one part of the fourth semiconductor layer; wherein a distance from a position where a net doping concentration of the second semiconductor layer is locally maximized to an interface between the third semiconductor layer and the fourth semiconductor layer is in a range of 5 μm to 30 μm, both inclusively, wherein the second semiconductor layer and the third semiconductor layer comprise donor protons, and wherein a lifetime of each of the second semiconductor layer and the third semiconductor layer is 50 μs or longer.