Patent ID: 7435671

Claim:
A method of patterning a gate conductor comprising: providing a trilayer resist (TLR) on a surface of a gate conductor, said TLR comprises a top organic layer, a middle inorganic layer and a bottom organic layer; patterning said top organic layer by lithography and trimming; first etching said middle inorganic layer utilizing said patterned top organic layer as a first pattern mask, wherein during said etching a portion of said top organic layer is consumed; second etching said bottom organic layer utilizing said patterned middle inorganic layer as a second pattern mask, wherein during said second etching said top organic layer is completely consumed; third etching said gate conductor utilizing said etched bottom organic layer as a third pattern mask, wherein during said third etching said middle inorganic layer is removed; and stripping the etched bottom organic layer to provide at least one patterned gate conductor having a critical dimension of less than 40 nm.