Patent ID: 6928528

Claim:
A data synchronization unit comprising: a memory unit including a memory, wherein the memory unit is configured to receive data from a source external to the data synchronization unit; a write pointer unit configured to specify an address in the memory where data is to be written to, wherein the write pointer unit is synchronized to an external clock signal generated external to the data synchronization unit; a read pointer unit configured to specify an address in the memory where data is to be read from, wherein the read pointer unit is synchronized to a local clock signal, and wherein the local clock signal is generated internal to the data synchronization unit; and synchronization pulse logic, wherein the synchronization pulse logic is configured to, in a synchronization mode, to assert a synchronization pulse, wherein asserting the synchronization pulse synchronizes the write pointer to the read pointer, wherein synchronizing includes setting the location of data to be read from the memory to lag the location where data is written to the memory by a predefined number of memory locations.