Patent ID: 7277311

Claim:
A memory system comprising: a processor that controls the system; and a flash memory device coupled to the processor, the device comprising: a memory array for storing data, the memory array comprising a plurality of local bit lines; and control circuitry coupled to the memory array, the control circuitry adapted to deactivate a first field-effect transistor having a first source/drain region coupled to a fuse latch input node and a second source/drain region coupled to a local bit line of the plurality of local bit lines, activate a second field-effect transistor having a first source/drain region coupled to a first potential node and a second source/drain region coupled to the fuse latch input node, and reset a fuse latch in response to deactivating the first field-effect transistor and activating the second field-effect transistor, wherein the fuse latch has an input coupled to the fuse latch input node and an output coupled to an output node.