Patent ID: 7587577

Claim:
A co-processor subsystem comprising: a co-processor having Fast Fourier Transform (FFT) circuitry and digital filter circuitry; a bus slave circuit; and a memory switch including: a plurality of memory blocks; switch circuitry having a plurality of transmission terminals and a plurality of selection terminals, wherein the FFT circuitry is coupled to at least one of the transmission terminals, and wherein the digital filter circuitry is coupled to at least one of the transmission terminals, and wherein the bus slave circuit is coupled to at least one of transmission terminals, and wherein each memory block is coupled to at least one of the transmission terminals, and wherein the switch circuitry is adapted to couple at least one of the functional units to at least one of the memory blocks, and wherein the switch circuitry is adapted to coupled the bus slave circuit to at least one of the memory blocks; a control register; and control logic that is coupled to the control register and the selection terminals, wherein the control logic that controls the switch circuitry based at least in part on the contents of the control register.