Patent ID: 7477641

Claim:
A system comprising: multiple multi-thread programmable cores integrated on a single die; logic to: process packets using a sequence of packet processing threads provided by the multiple multi-threaded programmable cores, the sequence of threads spanning a sequence of cores including, at least, a first core, a second core, and a third core, individual threads including at least one critical section that coordinates access to data shared by the threads; wherein a thread in the sequence of packet processing threads executing on the first core performs operations comprising: issuing a first signal to the third core permitting a pre-critical section read of shared data protected by a first critical section; wherein a thread in the sequence of packet processing threads executing on the second core performs operations comprising: executing the first critical section; and if the data shared is modified within the first critical section, sending one or more messages to the third core identifying changes; and wherein a thread in the sequence of packet processing threads executing on the third core performs operations comprising: receiving the first signal from the first core; after receiving the first signal from the first core, performing a memory access to retrieve a copy of data shared by the packet processing threads before entering the critical section that coordinates access to the shared data; determining whether the data shared by the packet processing threads has changed from the copy based on whether the third core received the at least one or more messages identifying the changes to the data shared; if the data has not changed, using the retrieved data in the critical section; if the data has changed, using the changed data in the critical section.