Patent ID: RE42250

Claim:
A delay circuit comprising: a plurality of current mirror current sources source transistors , with each current mirror current source transistor having an enable input, having an input for receiving an input signal and having a constant current output for providing a constant current responsive to the input signal; a plurality of current mirror current drains drain transistors , with each current mirror current drain transistor having an enable input, having an input for receiving an inverse of the input signal, and having a constant drain output for providing a constant current responsive to the inverse of the input signal; a programmable delay control circuit having a plurality of enable signals, each signal connected to a current mirror current source transistor and current mirror current drain transistor such that the programmable delay control circuit selectively enables a pair of current mirror current source and drain transistors ; a fixed capacitor having a first plate and a second plate, the first plate of the capacitor connected to the constant current outputs of the plurality of current mirror current sources source transistors and to the constant drain outputs of the plurality of current drains drain transistors , the second plate connected to a voltage reference, with each current mirror current source transistor having a current path between a corresponding enable signal of said programmable delay control circuit and the first plate of said capacitor and with, each current mirror current drain transistor having a current path between the corresponding enable signal of said programmable delay control circuit and the first plate of said capacitor; and an output stage having an input connected to the first plate of the capacitor and having an output for providing an output responsive to the voltage on the capacitor; wherein a delay on the rising edge of the input signal is adjustable by the programmable delay control circuit selectively enabling the enable signal of one or more of the plurality of current mirror current sources source transistors to change an overall current source current provided by the plurality of current mirror current sources source transistors to the first plate of the capacitor, and wherein a delay on the falling edge of the input signal is adjustable by the programmable delay control circuit selectively enabling the enable signal of one or more of the plurality of current mirror current drains drain transistors to change an overall current drain current provided by the plurality of current mirror current drains to drain transistor from the first plate of the capacitor.