Patent ID: 8288224

Claim:
A method for manufacturing capacitor lower electrodes of a semiconductor memory, particularly a method for manufacturing a stack dynamic random access memory, comprising the steps of: forming a stacked structure over a semiconductor substrate with a plurality of conductive plugs; partially etching a hard mask layer, a first silicon nitride layer and a dielectric layer in the stacked structure to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer, the dielectric layer and an insulating nitride layer to form a plurality of trenches to expose the conductive plugs; in each of the plurality of trenches, forming a conductive metal material on the exposed conductive plug and a capacitor lower electrode electrically connecting the conductive metal material, and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area so that a periphery portion of each of the capacitor lower electrodes is surrounded by and attached to the second silicon nitride layer for enhancing supporting strength of the capacitor lower electrodes, reducing the difficulty in disposing of capacitor dielectric layers and capacitor upper electrodes outside the capacitor lower electrodes, and preventing the capacitor lower electrodes from collapsing or producing deformation.