Patent ID: 7538590

Claim:
A clock divider comprising: a first clock divider circuit comprising: a first transistor coupled to a first input of the first clock divider circuit and configured to receive a first input signal; a second transistor coupled in parallel to the first transistor and configured to receive a second input signal; a third transistor coupled to the first input and configured to receive the first input signal and coupled in series with both the first transistor and the second transistor; a fourth transistor coupled directly to ground, coupled in series with the third transistor and coupled to a second input of the first clock divider circuit, the fourth transistor configured to receive the second input signal; a fifth transistor coupled to the first and second transistors and configured to receive a clock signal, wherein the clock signal is independent of the first input signal, the second input signal, or an inversion of the first input signal or the second input signal; and a second clock divider circuit coupled to the first clock divider circuit and configured substantially similarly to the first clock divider circuit, wherein an output of the second clock divider circuit is coupled to the first input of the first clock divider circuit.