Patent ID: 7346758

Claim:
A method comprising: providing a first set of linear address representations for storage in a buffer of a processing device in response to executing a first set of instructions during a first execution period, each of the linear address representations corresponding to an instruction of the first set of instructions; providing a second set of linear address representations for storage in the buffer in response to executing a second set of instructions during a second execution period subsequent to the first execution period, each of the linear address representations corresponding to an instruction of the second set of instructions; providing address translation information for storage in the buffer after the first set of linear address representations and before the second set of linear address representations, the address translation information representing a change in a linear address-to-physical address mapping of a translation look aside buffer (TLB) between the first execution period and the second execution period; and providing a trace information stream for output from the buffer of the processing device to a debug component external to the processing device, the trace information stream comprising the first set of linear address representations, the address translation information, and the second set of linear address representations.