Patent ID: 8836140

Claim:
A three-dimensional vertically interconnected structure, characterized in that, it comprises at least two layers of chip which are stacked in sequence or stacked together face to face, and a layer of adhesive material is used for adhesion between adjacent layers of said chip, each layer of said chip containing a substrate layer and a dielectric layer sequentially from bottom to top; a front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal therein to form a first electrical conductive ring which is connected to microelectronic devices inside the chip via a redistribution layer; a first through layers of wafers or chips hole having the same radius and the center as the inner ring of the first conductive ring penetrates the stacked chips and has a first micro electrical conductive pole therein; wherein a front surface and/or a backside surface of each layer of said wafer or chip have/has a thermal conductive ring, the front surface and/or backside surface of the wafer or chip have/has a thermal conductive layer, and the thermal conductive layer is connected with the thermal conductive ring; a second through layers of chips hole having the same radius and center as the inner ring of the thermal conductive ring penetrates the chips which are stacked and has a micro thermal conductive pole therein.