Patent ID: 7342274

Claim:
A memory cell with vertical capacitor and transistor, comprising: a substrate with a trench; a capacitor at the bottom of the trench; a first conductive layer electrically coupled to the capacitor, the first conductive layer being isolated from the substrate by a collar dielectric layer; a trench top oxide (TTO) layer disposed on the first conductive layer; a gate dielectric layer disposed on the sidewalls of the upper portion of the trench; a doped polysilicon layer on the sidewalls of the gate dielectric layer, leaving a portion of a top surface of the trench top oxide (TTO) uncovered; a metal gate disposed on the doped polysilicon layer in the upper portion of the trench; and a barrier layer directly contacting the TTO, the metal gate and the doped polysilicon layer; wherein the doped polysilicon layer is level with the gate dielectric layer.