Patent ID: 7395372

Claim:
A system for accessing a two way associative cache having first and second ways, comprising: a clock circuit for selectively applying clock pulses to one or to both ways of said two way associative cache in response to an access mode signal, a HITA signal and a HITB signal; an effective address register connected to simultaneously apply an address to each of said two way associative cache; an output multiplexer for selecting data from one of said first and second ways of said two way associative cache in response to a select signal identifying one of said ways of said associative cache; and a byte select circuit configured to select an individual byte of the data selected by the output multiplexer in accordance with byte data contained in the effective address register, wherein, in a power efficiency access mode, the clock circuit is configured such that the access mode signal enables the HITA signal and the HITB signal to select one of said first way and second way to apply clock pulses to at an end of an access cycle, and wherein, in a high speed access mode, the clock circuit is configured such that the access mode signal disables the HITA signal and the HITB from selecting both of said first way and second way have clock pulses applied.