Patent ID: 7870413

Claim:
A clocking scheme for a multi-processor system, the multi-processor system having at least two independent SMP (Symmetric Multi-Processing) domains and an interconnection board connecting with any two of the SMP domains, the clocking scheme comprising: a clock source located on each of the SMP domains, generating a base clock and sending to each of the SMP domains; a SPLL (Select Phase-Locked Loop) located on each of the SMP domains, receiving at least one of the base clocks from at least one of the SMP domains, and selecting one of the base clocks according to a select signal to generate an N-times faster clock; a clock buffer located on each of the SMP domains, providing duplicated copies of the N-times faster clock to a plurality of processors located at the same SMP domain; and a self-clock path sending the base clock to the SPLL on the same SMP domain; wherein one or more of the base clocks can be sent through a distribution-clock path to another of the SPLLs on another of the SMP domains creating first and second distribution clock paths, the first and the second distribution-clock paths and the self-clock path having equal lengths, and configured such that when the SMP domains are booted up as a single integrated system, the SPLLs of the SMP domains each select a single one of the base clocks according to the select signal to generate a synchronized N-times faster clock.