Patent ID: 7868646

Claim:
A programmable logic device (PLD) comprising: a plurality of configuration memory cells adapted to store configuration data bits of a user design, each cell having at least one input node to receive a configuration bit and at least one output node to provide the configuration bit; a plurality of address lines coupled to the configuration memory cells; a plurality of bitlines coupled to the input nodes of the configuration memory cells; logic circuitry adapted to force the address lines and bitlines to predetermined logical values in an SEU-hardened mode, wherein the address lines and bitlines force the at least one output node of each memory cell to a predetermined logical value; and a mask programmable connection associated with each memory cell for connecting the at least one output node of the memory cell to configurable resources of the PLD, wherein in the SEU-hardened mode and with the mask programmable connections programmed, the memory cells provide configuration data bits having the predetermined logical values of the output nodes of the memory cells to the configurable resources.