Patent ID: 7969799

Claim:
A memory interface physical layer macro comprising: one or more embedded input/output (I/O) buffers that support a plurality of I/O supply voltage levels; one or more datapath hardmacros coupled to said one or more embedded I/O buffers; and control logic that controls said one or more datapath hardmacros and said one or more I/O buffers, wherein (i) said control logic comprises a write datapath logic for each of said one or more datapath hardmacros, (ii) each write datapath logic comprises (a) a write leveling pulsing circuit configured to generate an output in response to a signal implementing a write leveling pulse signal and (b) a preamble generation circuit configured to present a DQS enable signal, a DM enable signal, a DQ enable signal, and a DQS toggling enable signal to a respective datapath hardmacro in response to a first signal configured to indicate a write leveling mode, a second signal implementing a write control signal, a third signal indicating a memory mode, and said output of said write leveling pulsing circuit.