Patent ID: 7639769

Claim:
A dual loop, phase lock loop (PLL) comprising: a first loop for coarsely synchronizing a first oscillator based on time stamps that are received from a data transmission; and a second loop for finely synchronizing a second oscillator based on (1) the time stamps and (2) at least one signal generated by the first loop, wherein: the first oscillator is adapted to generate a first clock signal; and the first loop comprises: a first clock difference generator adapted to generate first measured clock cycle values corresponding to numbers of cycles of the first clock signal in first time periods, wherein a time stamp received from the data transmission is used to define a first time period; and a first subtractor adapted to generate first clock error values based on differences between the first measured clock cycle values and a first expected clock cycle value for the first clock signal, wherein the first oscillator is controlled based on the first clock error values.