Patent ID: 7500046

Claim:
A complex Application Specific Integrated Circuit (ASIC) having an interface for electrically coupling the ASIC to any of multiple host computer system buses, the ASIC comprising: an input/output component; first two-way host bus logic configured to translate communications between the input/output component and a first host bus, the host bus logic comprising: a request queue for issuing read requests and write requests from the input/output component to the first host bus; a response queue for receiving from the first host bus responses to the read requests; an acknowledgement queue for receiving from the first host bus acknowledgements of non-posted write requests; host meta logic configured to: convert a request from the input/output component into an appropriate bus transaction accepted by the first host bus; convert a host bus transaction including response or acknowledgement received by the first host bus into a format accepted by the input/output component; and issue a pseudo acknowledgement to the acknowledgement queue on the first host bus logic for non-posted write request if the first host bus does not implement an acknowledgement queue configured to issue acknowledgements of non-posted write 24 requests to the acknowledgement queue on the first host bus logic; a table to map an operation's operation identifier to the transaction identifiers of the corresponding first host bus transactions; and a meta interface configured to concurrently convey the requests, the responses and the acknowledgements between the input/output component and the first host bus logic.