Patent ID: 8056069

Claim:
A computer-implemented method comprising: identifying a loop within a piece of program code; identifying, within a body of the loop, a plurality of isomorphic statements having adjacent memory accesses; transforming the plurality of isomorphic statements into one or more vector operations; calculating a blocking factor n, wherein the blocking factor n is calculated as a quotient having a dividend that is an available hardware vector length and having a divisor that is a greatest-common-divisor of a set of numbers that includes each vector length in the one or more vector operations and the available hardware vector length; aggregating n vectors across iterations in each of the one or more vector operations into one or more virtual-length vector operations such that the one or more virtual-length vector operations have lengths that are multiples of the available hardware vector length; and generating single-instruction multiple-datapath (SIMD) code by de-virtualizing the one or more virtual-length vector operations to obtain one or more physical-length vector operations that correspond to the available hardware vector length.