Patent ID: 7057963

Claim:
A layout structure of dual port SRAM (Static Random Access Memory) in which read and write operations are available in a dual mode, the layout structure comprising: a read bit line pair comprising: a read bit line and a complementary read bit line that are positioned adjacent to each other along a Y direction of a dual port SRAM cell, said read bit line pair being connected to the dual port SRAM cell; a write bit line pair, which is arranged in parallel with the read bit line pair, the write bit pair line comprising: a write bit line and a complementary write bit line that are positioned adjacent to each other, and said write bit pair line being connected to the dual port SRAM cell; power source lines disposed between the read bit line pair and the write bit line pair; and read and write word lines positioned vertically to the read bit line pair and the write bit line pair and formed below the read bit line pair, the write bit line pair and the power source lines.