Patent ID: 7015069

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a plurality of semiconductor chips each having bonding pads on a main surface thereof, and a wiring substrate having a first surface and a second surface opposed to said first surface, said wiring substrate having a plurality of device forming areas in a plan view, each of said plurality of device forming areas having conductor patterns for wiring and dummy conductor patterns which are spaced and divided from said conductor patterns for wiring on said plan view; (b) mounting a plurality of semiconductor chips on said first surface of said wiring substrate at said plurality of device forming areas respectively; (c) electrically connecting said bonding pads of said plurality of semiconductor chips with said conductor patterns for wiring in each of said plurality of device forming areas; (d) setting said wiring substrate with said plurality of semiconductor chips into a mold having an upper mold half and a lower mold half, such that said second surface of said wiring substrate faces said lower mold half and such that said plurality of semiconductor chips are disposed in a cavity defined by said upper and lower mold halves; (e) sealing the plural semiconductor chips with resin in a block to form a resin seal member; and (f) cutting said wiring substrate and said resin seal member along said plurality of device forming areas, thereby forming a plurality of semiconductor devices each having one of said semiconductor chips, a part of said wiring substrate with said conductor patterns for wiring and dummy conductor patterns and a part of said resin sealing member.