Patent ID: 7078255

Claim:
A method for manufacturing a thin film transistor array panel, comprising the steps of: forming a gate wire including a plurality of gate lines and gate pads by a first photolithography process; depositing a first insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer on the gate wire; forming a metal layer pattern, an ohmic contact layer pattern, a semiconductor layer pattern and a first insulating layer pattern that have a matrix shape layout overlapping the gate wire except for the gate pad by a second photolithography process; depositing a transparent conductor layer; forming a transparent conductor pattern including a pixel electrode, a plurality of redundant date lines, redundant source electrodes, redundant drain electrodes, redundant data pad and redundant gate pad by a third photolithography process; etching out the portion of the metal layer not covered by the transparent conductor pattern and the ohmic contact layer thereunder; depositing a second insulating layer; forming a passivation layer pattern having openings respectively exposing the gate pad, the data pad, the pixel electrode and the portion of the semiconductor layer connecting the adjacent data line; and etching out the portion of the semiconductor layer exposed through the openings.