Patent ID: 8156309

Claim:
An apparatus, comprising: a pipelined Translation Look-aside Buffer (TLB) including multiple TLB units, each configured to store TLB entries of translation addresses, wherein the multiple TLB units are serially coupled and configured to concurrently compare different translation addresses to the TLB entries stored by the multiple TLB units, wherein the pipelined TLB units are configured to prevent one or more of the pipelined TLB units from comparing the associated TLB entries with a particular translation address in response to a hit on the particular translation address in one of the TLB units; and a non-pipelined micro TLB unit, separate from the multiple TLB units in the pipelined TLB, configured to forward the different translation addresses to the pipelined TLB when no hit is produced for the different translation addresses in the non-pipelined micro TLB unit.