Patent ID: 7310257

Claim:
A dynamic random access memory (“DRAM”) array arranged in rows and columns, each of the columns of the DRAM array comprising: a sense amplifier operable to sense a voltage difference applied between first and second inputs; first and second global digit lines coupled to the first and second inputs of the sense amplifier, respectively; a first plurality of local digit lines each of which is coupled to a plurality of memory cells; a second plurality of local digit lines each of which is coupled to a plurality of memory cells; and respective coupling circuits selectively coupling each of the local digit lines in the first plurality of local digit lines to the first global digit line and each of the local digit lines in the second plurality of local digit lines to the second global digit line, each of the coupling circuits comprising: a voltage controlled switch coupled between a supply voltages and one of the global digit lines, the switch having a control input coupled to a respective one of the local digit lines.