Patent ID: 8013628

Claim:
A circuit having an active clock shielding structure, comprising: a logic circuit configured to receive a clock signal and to perform a logic operation based on the clock signal; a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on a power gating signal; a clock signal transmission line configured to transmit the clock signal to the logic circuit; at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line; a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line, wherein both the at least one power gating signal transmission line and the at least one retention signal transmission line encompass the clock signal transmission line while running parallel with the clock signal transmission line.