Patent ID: 7253508

Claim:
A semiconductor package comprising: a plurality of leads, each having an upper surface and an opposing lower surface, wherein the upper surfaces of the leads include a plurality of bump-bonding regions at one ends of the leads, the lower surfaces of the leads include a plurality of outer connecting regions at the another ends of the leads and a plurality of supporting portions corresponding to the bump-bonding regions; a flip chip located on the bump-bonding regions of the leads; a plurality of bumps connecting the flip chip to the bump-bonding regions of the leads; and a molding compound encapsulating the flip chip and covering the upper surfaces of the leads, the outer connecting regions and the supporting portions being exposed out of the molding compound; wherein the leads have a plurality of indentations formed at the upper surfaces of the leads, the indentations are adjacent to the corresponding bump-bonding regions and filled with the molding compound and a back tape attached to the supporting portions of the leads.