Patent ID: 8643398

Claim:
An integrated circuit comprising: a core logic section operable under a normal-mode power voltage during a normal operating mode of the integrated circuit and operable under a standby mode power voltage during a standby mode of the integrated circuit, the core logic section able to use first digital signaling levels when operating under the normal-mode power voltage and to use second digital signaling levels when operating under the standby mode power voltage; a first ground bus to which the normal-mode power voltage and standby mode power voltage are applied; a digital signal outputting section able to use third digital signaling levels for outputting digital data signals to circuitry outside the integrated circuit; and a transition logic section operable under the normal-mode power voltage during the normal operating mode and operable under the standby mode power voltage during the standby mode, the transition logic section operable to provide signal level shifting as between the first and second digital signaling levels used by the core logic section and the third signaling levels used by the digital signal outputting section the transition logic section including a second ground bus, wherein the second ground bus is operable to couple to the first ground bus during the normal operating mode and is operable to couple to a negative voltage supply during the standby mode.