Patent ID: 8502301

Claim:
A semiconductor device comprising: a semiconductor substrate; an isolation region formed in the semiconductor substrate; an active region made of the semiconductor substrate surrounded by the isolation region and having a trench portion; a MIS transistor of a first-conductivity type having a first gate electrode formed on the active region, a first sidewall spacer formed on a side surface of the first gate electrode, and a silicon mixed crystal layer of the first-conductivity type for generating stress in a channel region of the active region, the trench portion being located on a side of and below the gate electrode and filled with the silicon mixed crystal layer of the first-conductivity type; a substrate region provided between the trench portion and the isolation region, said substrate region formed on a side surface of the active region in a gate length direction and made of the semiconductor substrate; and a mask portion formed on the substrate region, and on the isolation region formed on the side surface of the active region in the gate length direction, wherein the mask portion includes a second gate electrode made of the same material as the first gate electrode and a second sidewall spacer formed on a side surface of the second gate electrode.