Patent ID: 7027330

Claim:
A multi-I/O repair method of a NAND flash memory device in which first and second page buffers are positioned in a main array and third and fourth page buffers are positioned in a redundancy array, the NAND flash memory device including first and second address fuse blocks for selecting the third and fourth page buffers, respectively, and first and second I/O fuse blocks for selecting one of data received from the first to fourth page buffers and transmitting the selected data to an I/O buffer through a first data line, wherein the third and fourth page buffers are selected at the same time through the first and second address fuse blocks according to an address of a main column to be repaired, and the first and second data received from the third and fourth page buffers are thus transmitted over second and third data lines, respectively, and the first and second data received through the second and third data lines are transmitted over the first data line according to output signals of the first and second I/O fuse blocks, whereby the main column is repaired.