Patent ID: 7049189

Claim:
A method of fabricating a non-volatile memory cell, comprising: forming a bottom dielectric layer, a charge trapping layer, a first top dielectric layer and a mask layer on a substrate sequentially; etching the mask layer for forming a first wench exposing a portion of the first top dielectric layer; forming a plurality of first spacers on sidewalls of the first trench; using the first spacers as an etching mask and etching the first top dielectric layer and the charge trapping layer for forming a second trench; removing the first spacers; forming a second top dielectric layer over the substrate, covering surfaces of the second trench and the first trench; forming a conductive layer in the first trench and the second trench; removing the conductive layer and the second top dielectric layer outside of the first trench and the second trench for exposing the mask layer; removing the exposed mask layer; using the conductive layer as a mask, removing the first top dielectric layer, the charge trapping layer and the bottom dielectric layer for forming a stacked structure; and forming source/drain regions in the substrate adjacent to edges of the stacked structure.