Patent ID: 7671399

Claim:
A semiconductor storage device including a memory cell array, said memory cell array comprising: a memory cell section; and a bypass section, wherein said memory cell section comprises: a first cell and a second cell that control a select gate and a word line; a first storage node and a second storage node disposed in second areas adjacent to a first area; a first diffusion region and a second diffusion region placed adjacent to the second areas and provided in third areas on a surface of the substrate; and a first control gate, which is disposed on said first storage node and second storage node and controls a channel underlying one of said first storage node and said second storage node, wherein said bypass section includes a first switch and a second switch that share the select gate and are activated by respective ones of different word lines, wherein either of said first cell or said second cell is electrically connected to one of said first switch or said second switch via an inversion layer just underlying the select gate, and wherein said select gate is disposed on a substrate in the first area.