Patent ID: 7884751

Claim:
A time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising: a first delay line in which a plurality of first delay elements that delay an input signal by a first delay amount is connected in series, and to the first delay element in the first stage of which, the reference clock is input; a second delay line group that is connected to a connection node of the plurality of the first delay elements of the first delay line or an input node of the first delay element in the first stage, and in which at least one or more second delay elements that delay an input signal by a second delay amount different from the first delay amount are connected in series; a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edge of a signal, which is the delayed reference clock output from the plurality of the first delay elements of the first delay line and the plurality of the second delay elements of the second delay line group; and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results by the plurality of the judgment circuits, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.