Patent ID: 6851038

Claim:
A translation lookaside buffer (TLB) background processor, comprising: a memory management unit (MMU) ( 30 ) providing for background fetching of TLB descriptors ( 40 ) from a main memory ( 26 ) while a host processor CPU ( 20 ) is otherwise occupied accessing a private cache memory ( 16 ) during a cache-hit cycle; a circuit ( 32 ) for detecting when both a cache-hit cycle has occurred between said CPU ( 20 ) and cache memory ( 16 ), and a TLB-miss cycle has occurred between the CPU ( 20 ) and MMU ( 30 ), and providing for a TLB background access request in such event; and a circuit ( 32 ) responsive to said TLB background access request, and providing for fetching of TLB descriptors ( 40 ) for those pages of main memory represented by said cache-hit cycle.