Patent ID: 8378491

Claim:
An integrated circuit, comprising: at least first, second, third and fourth interconnect levels; wherein the first interconnect level includes a plurality of first interconnect areas electrically coupled to a first terminal of a semiconductor device formed within a semiconductor substrate and further includes a plurality of second interconnect areas electrically coupled to a second terminal of the semiconductor device; the second interconnect level includes a third interconnect area, the third interconnect area including a plurality of first openings; the third interconnect level includes a fourth interconnect area, the fourth interconnect area including a plurality of second openings; the fourth interconnect level includes a first contact area and a second contact area, the first contact area being electrically coupled to the first interconnect areas of the first interconnect level via the fourth interconnect area and first contacts extending through the plurality of first openings in the third interconnect area, the second contact area being electrically coupled to the second interconnect areas of the first interconnect level via the third interconnect area and second contacts extending through the plurality of second openings in the fourth interconnect area.