Patent ID: 7972919

Claim:
A method for forming a vertical PNP transistor in a semiconductor substrate while forming a CMOS device and a vertical NPN transistor, said method comprising: a first step or set of steps for concurrently forming at least a first portion of the CMOS device and a collector region of the vertical PNP transistor; a second step or set of steps for concurrently forming at least a second portion of the CMOS device and an intrinsic base region of the vertical PNP transistor; a third step or set of steps for concurrently forming at least a third portion of the CMOS device and an extrinsic base region of the vertical PNP transistor; and a fourth step or set of steps for concurrently forming at least a portion of the vertical NPN transistor and an emitter region of the vertical PNP transistor, wherein the emitter region of the vertical PNP transistor and an intrinsic base region of the vertical NPN transistor both consist essentially of a single crystal material, wherein an upper surface of the emitter region of the vertical PNP transistor is aligned and co-planar with an upper surface of the intrinsic base region of the vertical NPN transistor along a direction parallel to a top surface of the semiconductor substrate.