Patent ID: 8793545

Claim:
An integrated circuit comprising: a scan chain including a plurality of serially-coupled scan elements each coupled to receive a clock signal; wherein a first subset of the plurality of serially-coupled scan elements is configured to form a counter configured to count a number of clock cycles provided during a scan test; wherein a first one of the subset of serially-coupled scan elements is of a first scan element type, and wherein remaining ones of the subset of serially-coupled scan elements are of a second type; and wherein the first one of the subset of serially-coupled scan elements includes a scan input, a scan enable input, and a data input, wherein the first one of the subset of serially-coupled scan elements is configured to receive data through the scan input when an enable signal is asserted on the scan enable input, and wherein the first one of the subset of serially-coupled scan elements is configured to receive data through the data input when the enable signal is not asserted.