Patent ID: 7536499

Claim:
A memory access control device, comprising: a plurality of memory areas associated with a plurality of address spaces whereby access to a respective one of said plurality of memory areas is controlled by specifying at least part of its associated address space; a plurality of write ports each operable to provide respective write data; a write data selecting block operable to select a plurality of write data paths between said plurality of write ports and said plurality of memory areas over which said plurality of write ports provide the respective write data to said plurality of memory areas; a plurality of read ports each operable to receive respective read data; a read data selecting block operable to select a plurality of read data paths between said plurality of memory areas and said plurality of read ports over which said plurality of read ports receive the respective read data from said plurality of memory areas; and a control block operable to provide configuration information by which said write data selecting block selects the plurality of write data paths and by which said read data selecting block selects the plurality of read data paths, the configuration information allocating the plurality of address spaces among the plurality of write data paths such that a respective one of said plurality of memory areas receives write data only from a specific one of said plurality of write ports and allocating the plurality of address spaces among the plurality of read data paths such that a given one of said plurality of memory areas provides read data only to a particular one of said plurality of read ports, the plurality of write data paths thereby being operable in parallel and independent of each other and the plurality of read data paths thereby being operable in parallel and independent of each other without any one of said plurality of memory areas being read from and written to at the same time.