Patent ID: 8362795

Claim:
A semiconductor device, comprising: an integrated semiconductor circuit unit; a chip guard-ring disposed along an outer portion of the semiconductor device; and a reliability verifying unit disposed between the integrated semiconductor circuit unit and the chip guard-ring, wherein the reliability verifying unit is configured to delay a reliability verifying signal to detect a fault while in a reliability detecting mode, wherein the reliability verifying unit comprises: a reliability-verifying-signal generating unit configured to generate the reliability verifying signal in response to a test mode signal, a reliability-verifying-signal transmitting unit configured to receive the reliability verifying signal from the reliability-verifying-signal generating unit, delay the reliability verifying signal, and transmit the delayed reliability verifying signal to an input of the reliability-verifying-signal generating unit, and a reliability-verifying-signal outputting unit configured to transmit the delayed reliability verifying signal to an output pad of the integrated semiconductor circuit unit.