Patent ID: 7877759

Claim:
A system for monitoring performance of simultaneous occurring events in a single or multiprocessor computer system comprising: a hybrid counter array for counting signals representing occurrences of events received from event sources having a first counter portion including one or more counter devices and providing a first count value corresponding to lower order bits of a count, and a second counter portion comprising a memory array device having addressable memory locations, each said addressable memory location for storing a second count value for a respective counter device representing higher order bits of said count, a combination of said first and corresponding second count values providing a count of a number of events received at a counter device; an overflow bit means associated with each respective counter device, said overflow bit means being set in response to reaching an overflow condition; a control means operatively coupled with each said associated overflow bit means for monitoring each respective overflow bits of each said associated overflow bit means of said first counter portion and initiating incrementing a value of a corresponding said second count value stored at said corresponding addressable memory location in said second counter portion in response to a respective overflow bit of an associated overflow bit means being set, wherein after said initiating, said overflow bit means being reset; an interrupt pre-indication means for providing fast interrupt trigger to a processor device when one or more count values related to an event equals a pre-determined threshold value, said interrupt pre-indication means comprising: a means for comparing an incremented second count value against a pre-determined threshold value; an interrupt arming device associated with each respective counter device for enabling fast interrupt indication, said interrupt arming device being set in response to said incremented second count value being equal to said pre-determined threshold value, wherein said pre-determined threshold value equals a desired interrupt threshold value decremented by one; and a means implementing logic coupled to an output of said interrupt arming device and an output of said overflow bit means for asserting an interrupt signal when an overflow bit means corresponding to a counter device is set, and said interrupt arming device associated with said counter device is set, wherein said interrupt signal is asserted independent of a state of said control means; and a means enabling one or more of: read access or write access to both said first count value in said first counter portion and said second count value in said second counter portion, said read access or write access for purposes of initializing and determining status of said first and second count values in respective first and second counter portions for a monitored event type in response to a processor device request.