Patent ID: 7694077

Claim:
A multi-port instruction/trace integrated cache which is provided between a parallel processor to execute a plurality of types of processing in one clock cycle and a main memory and in which an instruction cache and a trace cache are integrated, comprising: a multi-port bank memory which has a plurality of banks which store a part of instruction data stored in the main memory and a plurality of ports; a tag directory which has a plurality of areas each corresponding to an index set to a middle-order digit in a fetch address outputted from the parallel processor, each of the areas storing therein an identification bit indicating whether instruction data to be accessed is data of the trace cache, a tag 1 set to a high-order digit in the fetch address, a tag 2 set to a lower-order digit in the fetch address, and a plurality of addresses which specify instruction data stored in each bank of the multi-port bank memory; an instruction cache hit judgment circuit which judges that the instruction data to be accessed is stored in the multi-port bank memory based on the tag 1 and the identification bit; a trace cache hit judgment circuit which judges that an instruction data string to be accessed is stored in the multi-port bank memory based on the tag 1 , the tag 2 and the identification bit; and a fetch address selector which selects a predetermined number of addresses among a plurality of addresses stored in a corresponding area of the tag directory in accordance with a hit judgment by the trace cache hit judgment circuit, supplies them to the multi-port bank memory, and causes instruction data in each bank to be simultaneously read.