Patent ID: 7630414

Claim:
A device using a single system clock having system clock cycles for combining at least two data signals having a first data rate into a single data stream having a second data rate higher than the first data rate for transmission on a shared medium, said device comprising: a plurality of ports for receiving said at least two data signals, a data bus for connecting said plurality of ports to a port addressing unit; at least one memory unit for temporarily buffering data received at said plurality of ports; a port addressing unit for extracting data from the data signals received by said ports, said port addressing unit accessing said plurality of ports in a predefined sequence to extract data therefrom during successive clock cycles for temporary storage at said at least one memory unit and for placing data extracted from said ports or retrieved from said at least one memory unit at predetermined positions in a single data stream for provision to at least one control data insertion unit; and at least one control data insertion unit comprising at least one of a TU-11 or a TU-12 framer for placing control data in said single data stream and a TUG-2/TUG-3/VC-4 mapper for mapping the single data stream into a VC-4 data stream, wherein said port addressing unit and at least one control data insertion unit are configured such that the extracting of data, placing of extracted data and placing of control data are performed per cycle and per port based on a common clock within said device.