Patent ID: 7875511

Claim:
A CMOS structure comprising: an n-FET device and a p-FET device located within and upon a substrate, wherein: said substrate includes a base semiconductor substrate, a silicon-germanium layer located directly on a first portion of said base semiconductor substrate, a first silicon material layer located directly atop said silicon-germanium layer, a silicon-germanium-carbon alloy layer located directly on a second portion of said base semiconductor substrate, a second silicon material layer located directly atop said silicon-germanium-carbon alloy layer, and at least one semiconductor material portion abutting said base semiconductor substrate and one of said first silicon material layer and said second silicon material layer and extending to a top surface of isolation regions; said n-FET device has a first channel comprising said first silicon material layer, wherein said first channel is directly atop said silicon-germanium alloy material layer; and said p-FET device has a second channel comprising said second silicon material layer, wherein said second channel is directly atop said silicon-germanium-carbon alloy layer.