Patent ID: 7630272

Claim:
A multiple port memory comprising a word line driver for providing a first word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation and a second word line signal to access a second write port, the word line driver comprising: a first logic circuit comprising a first logic gate having a first input for receiving a clocked first port selection signal, a second input for receiving a disable signal, and an output coupled to the first write port and comprising a second logic gate having an output connected to the second input of the first logic gate for providing the disable signal and to a second write port of the multiple port memory cell, the second logic gate having an input for receiving a clocked second port selection signal during the write operation that accesses the second write port and disables access to the first write port thereby establishing a higher priority to access the second write port than the first write port; a first buffer circuit having an input coupled to the output of the first logic gate, and an output for providing the first word line signal; and a second buffer circuit having an input coupled to the output of the second logic gate, and an output for providing the second word line signal; wherein the disable signal is asserted to prevent the word line driver from accessing the first write port when the second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.