Patent ID: 7659758

Claim:
A reset circuit comprising: a power-on detection circuit which activates a power-on detection signal when a power supply voltage exceeds a first voltage; a power-down detection circuit which activates a power-down detection signal when the power supply voltage becomes lower than a second voltage lower than said first voltage, and a power detection control circuit which activates a reset signal in response to the activation of the power-on detection signal and inactivates said reset signal in response to the activation of the power-down detection signal, wherein said power-on detection circuit includes: a first dividing circuit which includes at least two first resistor elements disposed in series between a first power supply line and a second power supply line and generates a first divided voltage at a first connection node connecting the first resistor elements to each other; a first transistor which receives said first divided voltage at its gate and whose source is connected to the second power supply line; a clamping switch which is disposed between the gate of said first transistor and said second power supply line and turned on during the activation of said power-down detection signal; a first load circuit which includes a resistor element disposed between said first power supply line and a first output node in order to charge the first output node connected to a drain of said first transistor; and a first buffer circuit which shapes a voltage waveform of said first output node and outputs it as said power-on detection signal, and wherein said power-down detection circuit includes: a second dividing circuit which includes at least two second resistor elements disposed in series between the first power supply line and the second power supply line and a connection switch disconnecting said second resistor elements and said second power supply line during inactivation of said power-on detection signal and generates a second divided voltage at a second connection node connecting the second resistor elements to each other; a second transistor which receives said second divided voltage at its gate and whose source is connected to the second power supply line; a second load circuit which includes a resistor element disposed between said first power supply line and a second output node in order to charge the second output node connected to a drain of said second transistor; and a second buffer circuit which shapes a voltage waveform of said second output node and outputs it as said power-down detection signal.