Patent ID: 8709951

Claim:
A method of fabricating a semiconductor device, comprising: providing a patterned photoresist layer to establish masked and unmasked regions over a gate stack including: a) a polysilicon layer over a substrate, b) an oxide layer over the polysilicon layer, and c) a BARC (bottom anti-reflective coat) layer over the oxide layer; the masked region defining a pattern line width dimension w p ; removing the BARC layer from the unmasked region using a first plasma etch at a first etch RF bias power; trimming the patterned photoresist layer and the BARC layer to modify the masked and unmasked regions using a second plasma etch at a second etch RF bias power; the modified masked region defining a reduced pattern line width dimension w r <w p ; removing the oxide layer from the modified unmasked region using a third plasma etch at a third etch RF bias power; removing an amount of the polysilicon layer from the modified unmasked region using a fourth plasma etch at a fourth etch RF bias power and for a fourth etch time; and after removing the amount, removing a majority of any remaining part of the polysilicon layer from the modified unmasked region using a fifth plasma etch at a fifth etch RF bias power, resulting in the formation of a polysilicon gate having sidewalls and a targeted sidewall angle; wherein the first, second, third, fourth and fifth etch RF bias powers are set as respective first, second, third, fourth and fifth etch baseline RF bias powers of a given process recipe multiplied by a first adjustment percentage value equally applied to all of the first, second, third, fourth and fifth baseline RF bias powers, wherein the first adjustment percentage value is not equal to 100% or to 0%; and the fourth etch time is set as a baseline fourth etch time of the given process recipe multiplied by a second adjustment percentage value, with the first and second adjustment percentage values being determined from a pre-established correlation of variation in sidewall angle with variations in the first, second, third, fourth and fifth etch RF bias powers and the fourth etch time.