Patent ID: 8429383

Claim:
A system, comprising: a first processor; a second processor coupled to the first processor, the second processor having a core and comprising stack storage residing in the core; memory coupled to, and shared by, the first and second processors; and a synchronization unit coupled to the first and second processors, said synchronization unit synchronizes the execution of the first and second processors; wherein the second processor executes stack-based instructions while the first processor executes one or more tasks wherein the first processor manages the memory via an operating system that executes only on the first processor and the first processor executes a virtual machine that controls the execution of a program on the second processor; wherein the first processor executes a transaction targeting a pre-determined address and the synchronization unit detects said predetermined address and, as a result of detecting the pre-determined address, asserts a wait signal to cause said first processor to enter a reduced power or reduced performance mode; and wherein said second processor asserts a wait release signal that is received by said synchronization unit and that causes said synchronization unit to deassert said wait signal to the first processor.