Patent ID: 8258841

Claim:
A PLL circuit comprising: a polyphase reference clock output circuit that outputs a plurality of reference clocks with different phases, the polyphase reference clock output circuit comprising a plurality of delay cells including a differential input and a differential output, the plurality of delay cells being connected in series, and the reference clock is output from each output of the plurality of delay cells; a polyphase frequency divider circuit that outputs a plurality of divided clocks, the plurality of divided clocks being obtained by dividing frequencies of the plurality of reference clocks by a predetermined value; a selection switch circuit that selects one of the plurality of reference clocks or one of the plurality of divided clocks, and outputs the selected clock as a selected clock; a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, the output clock including a frequency that fluctuates according to a value of frequency control input data, and the ideal phase being calculated according to the output clock and the value of the frequency control input data; and a selection circuit that selects and outputs the output clock, the output clock being synchronized with one of the plurality of divided clocks according to the delay amount data.