Patent ID: 8014197

Claim:
A non-volatile memory comprising: an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows connected to word lines; programming circuitry connectable to the bit lines and the word lines to apply a set of voltages to program one or more selected storage elements along a first word line each to a corresponding target one of said multi-states during a programming process, the set of voltages including a series of one or more programming pulses applied to the first word line; and current limiting circuitry connectable to said bit lines to limit the current through the bit lines, whereby the current through a first of the selected storage elements is limited to not exceed a value dependent upon the first selected storage element's corresponding target state during the programming process, said value being set independently of the current limit value of the other bit lines and prior to applying the first of the programming pulses.