Patent ID: 7151400

Claim:
A level shifter comprising: a first power supply node at a first supply voltage; a second power supply node at a second supply voltage wherein the second supply voltage is higher than the first supply voltage; an input node configured to receive an input signal; an output node; a bias node at a bias voltage; an output circuit coupled to the bias node, the first power supply node, the second power supply node and the output node; a self-bias circuit maintaining the bias voltage, wherein the self-bias circuit comprises a bias-raising circuit to raise the bias voltage, and wherein the bias-raising circuit comprises a body-effect thick oxide pMOS transistor having its gate coupled to the first power supply node and its source coupled to the bias node, and further comprises an nMOS transistor coupled in series to the bias-raising circuit preventing ESD current from flowing through the self-bias circuit; and a refresh circuit coupled to the bias node and refreshing the bias voltage during a transition period of time when the input signal changes state, the refresh circuit being in an off state during a non-transition period of time of the input signal.