Patent ID: 7323371

Claim:
A process for manufacturing a thin film transistor substrate comprising the steps of: forming gate wiring comprising a gate line, a gate electrode connected with the gate line, and a gate pad connected with the gate line on an insulating substrate; forming a gate insulating film; forming a semiconductor layer; stacking and patterning conductive material to form data wiring comprising a data line intersecting the gate line, a data pad connected with the data line, a source electrode connected with the data line and adjacent to the gate electrode, and a drain electrode located on the opposite side of the source electrode around the gate electrode; stacking a low dielectric insulating film to form a protection film; patterning the protection film together with the gate insulating film to form contact openings for respectively exposing the gate pad, the data pad, and the drain electrode; and stacking and patterning a transparent conductive film to form a supplementary gate pad, a supplementary data pad, and a pixel electrode respectively connected with the gate pad, the data pad, and the drain electrode through the contact openings, wherein the protection film is formed by adding a reactant gas mixture comprising a main source gas, silane (SiH 4 ), and an oxidant on the data wiring to vapor deposit an a—SiCOH thin film by a CVD or PECVD method, wherein the ratio of the silane (SiH 4 ) gas to the main source gas is 1:0.5 to 1.