Patent ID: 7805562

Claim:
A data processing apparatus having a plurality of operation modes, comprising: a central processing unit; a nonvolatile memory unit comprising a plurality of erase blocks; a first interface unit; and a second interface unit, wherein in a first operation mode, a first program is stored into a first erase block, wherein in a second operation mode, the central processing unit is configured to perform a second operation for storing a second program, which is received from the first interface unit, to a second erase block, wherein in a third operation mode, the central processing unit is configured to perform a third operation for storing a third program, which is received from the second interface unit, to the second erase block, wherein the first program includes a write program for storing program data to a specified erase block of the nonvolatile memory unit, and wherein the second program includes a communication program for receiving program data via the second interface unit.