Patent ID: 6990625

Claim:
A computer-readable storage storing a program for controlling a computer to generate a burst error pattern by: defining an error row vector e in an error pattern E, said error row vector e beginning with an i-th bit of the error pattern E and having length of w bits (where w is an integer satisfying a relation b≦w≦2b<r) in a parity check matrix H (having r rows by n columns) of a linear code for correcting burst errors up to b bits in length, when the error pattern E (an n-bit row vector) is superposed on received information D having length of n bits, and when an error is a burst error having length of b bits or less and beginning with an i-th bit of the received information; when a syndrome S (an r-bit column vector) is expressed as S=H i ·e T (where T represents row-column transposition) from an r-row by w-column partial matrix H i beginning with an ith column and having w columns in the matrix H, defining an r-row by (r−w) column matrix B i so as to form an r-row by r-column nonsingular matrix A i by adding to the said partial matrix H i ; and obtaining an error vector e from e T =H i *·S, under a condition satisfying a relation B i *·S=0 r−w (where 0 r−w is a zero column vector having (r−w) bits) and making a w-row by r-column matrix H i * and an (r−w)-row by r-column matrix B i * satisfying a relation A i −1 ·A i =I (where I is a binary identity matrix having r rows by r columns), when expressing an inverse matrix A i −1 of A i =[H i |B i ] as A i - 1 = [ H i * B i * ] thereby generating a burst error pattern having a length up to b bits.