Patent ID: 7365418

Claim:
A multi-chip structure, comprising: a first chip having a first surface, a plurality of first signal pads and a plurality of first non-signal pads, wherein the first signal pads and the first non-signal pads are disposed on the first surface; a second chip having a second surface, a plurality of second signal pads and a plurality of second non-signal pads, wherein the second signal pads and the second non-signal pads are disposed on the second surface, and the second surface faces the first surface; a plurality of first signal bumps, wherein at least a portion of the first signal pads are electrically connected to their corresponding second signal pads through the first signal bumps; a plurality of first non-signal bumps, wherein at least a portion of the first non-signal pads are electrically connected to their corresponding second non-signal pads through the first non-signal bumps; a first thermal-conductive layer surrounding the first signal bumps and disposed between the first surface and the second surface; and a plurality of first dielectric areas surrounding the first signal bumps, wherein the first signal bumps are electrically insulated from the first thermal-conductive layer by the first dielectric areas.