Patent ID: 8019022

Claim:
A clock and data recovery circuit, comprising: a first clock and data recovery circuit receiving a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein the first signal and the second signal has a second data rate of X bps and the data signal has a first data rate of 2X bps, wherein the first clock and data recovery circuit comprises: a half-rate gated controlled oscillator receiving the reference signal and the data signal to generate a first clock signal, wherein the first data rate of the data signal is 2X bps and the frequency of the first clock signal is X Hz; a first D flip-flop comprising a first clock input terminal receiving the first clock signal, a first data input terminal receiving the data signal, and a first output terminal outputting the first signal; and a second D flip-flop comprising a second clock input terminal receiving the inverted first clock signal, a second data input terminal receiving the data signal, and a second output terminal outputting the second signal; and a second clock and data recovery circuit receiving and reducing the jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal, wherein the bandwidth of the first clock and data recovery circuit is larger than the bandwidth of the second clock and data recovery circuit.