Patent ID: 8344520

Claim:
A stacked structure of chips, comprising: a first chip, comprising: a first circuit block, comprising a first power terminal and a first signal terminal, and with a first function; a second circuit block, comprising a second signal terminal, and with a second function; a signal path, connected between the first signal terminal and the second signal terminal; a first hardwired switch, connected to the first power terminal; and a second hardwired switch, connected to the signal path; and a second chip, stacked with the first chip, comprising: a third circuit block, comprising a third power terminal and a third signal terminal, and with the first function; a third hardwired switch, connected to the third power terminal, and electrically connected to the first hardwired switch; and a fourth hardwired switch, connected to the third signal terminal, and electrically connected to the second hardwired switch; wherein if the first circuit block is defective, and the second circuit block and the third circuit block are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly to electrically connect the third signal terminal to the signal path such that the third circuit block replaces the first circuit block to provide the first function.