Patent ID: 7715467

Claim:
A transceiver circuitry, comprising: a dynamic phase alignment circuit that uses a selected clock phase of a multiphase dynamic phase alignment clock to capture serial data received from an integrated circuit, that converts the serial data to parallel data, and that divides the selected clock phase to produce a recovered clock, wherein the dynamic phase alignment circuit comprises a dynamic phase alignment phase detection and recovery circuit and a synchronizer and is configured to operate in first, second, and third modes of operations, wherein: in the third mode of operation, the serial data passes through the dynamic phase alignment phase detection and recovery circuit and the synchronizer; in the second mode of operation, the serial data passes through the dynamic phase alignment phase detection and recovery circuit without passing through the synchronizer; and in the first mode of operation, the serial data is deserialized while bypassing the dynamic phase alignment phase detection and recovery circuit and bypasses the synchronizer.