Patent ID: 7058863

Claim:
A semiconductor integrated circuit comprising: a memory macro function block configured to read/write data; and a peripheral circuit configured to function differently from said memory macro function block, wherein said memory macro function block comprises, a memory core function block configured to include one of a DRAM and an SRAM, to decode respective addresses of a plurality of bit cells constituted on a memory cell array, and to read/write bit cell data, and an interface function block, a region of which is separated from a region of said memory core function block, configured to transmit/receive data with said peripheral circuit, wherein said interface function block comprises, a test circuit configured to control a function test of said memory core function block, a command decoder portion configured to decode an input command for said function test of said memory core function block, an address decoder portion configured to decode an input address for said function test of said memory core function block, a memory core input/output circuit configured to input said command and said address into said memory core function block and to transmit/receive data with said memory core function block, a configuration memory block configured to simultaneously store data of a memory core configuration including, a memory capacity, a command configuration, an address configuration, and an input/output configuration of said memory core function block dedicated to both of the DRAM and SRAM, and a configuration control block dedicated to both of the DRAM and SRAM, and configured to change a data path and an address path of said memory core function block based on stored information of said configuration memory block and to control said memory core function block in a desired configuration.