Patent ID: 7790588

Claim:
A method for manufacturing a dual gate of a semiconductor device, comprising the steps of: forming a SiGe layer over a semiconductor substrate comprising a cell region and a peripheral region, the cell region having a recessed gate forming area and the peripheral region having PMOS and NMOS forming areas; selectively ion implanting a first conductive type impurities into a portion of the SiGe layer formed in the cell region and the PMOS forming area of the peripheral region to convert the portion of the SiGe layer formed in the cell region and the PMOS forming area of the peripheral region into a first conductive type SiGe layer; forming a first conductive type polysilicon layer over the first conductive type SiGe layer and the SiGe layer; selectively ion implanting a second conductive type impurities into a portion of the first conductive type polysilicon layer formed in the NMOS forming area of the peripheral region and a portion of the SiGe layer below the portion of the first conductive type polysilicon layer to convert the portion of the first conductive type polysilicon layer formed in the NMOS forming area of the peripheral region into a second conductive type polysilicon layer and to convert the portion of the SiGe layer into a second conductive type SiGe layer; and forming a metallic layer and a hard mask layer over the first and the second conductive type layers.