Patent ID: 7907435

Claim:
A semiconductor device comprising: a memory-cell array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction crossing the plurality of word lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines; a plurality of word driver circuits connected to the plurality of word lines; a plurality of read circuits and a plurality of write circuits connected to the plurality of bit lines; and a pulse-generating circuit comprising a plurality of NMOS transistors and a plurality of depletion MOS transistors configured to output a pulse based on a temperature characteristic, wherein each of the plurality of memory cells includes a first node connected to a corresponding one of the plurality of word lines; a second node connected to a corresponding one of the plurality of bit lines; a third node provided correspondingly to the second node; a memory element in which a crystalline state is formed by a set operation and an amorphous state is formed by a reset operation; and a switch element in which a current path from the second node to the third node via the memory element is formed upon reception of control of the first node, wherein, at the time of the set operation, a first pulse is first input to the memory element and subsequently a second pulse is input, and wherein a magnitude of the second pulse is changed by the pulse-generating circuit depending on an external temperature.