Patent ID: 7038306

Claim:
A semiconductor integrated circuit device comprising: a wire electrically connected to a surface electrode of a semiconductor chip; a plurality of inner leads located around said semiconductor chip; a palladium layer formed over a wire bonding portion of each of said plurality of inner leads; an adhered portion formed by connection of said wire with one of said inner leads; and a resin for molding said semiconductor chip, said plurality of inner leads, said wire and said adhered portion, wherein a diameter of said wire is 30 μm or less, wherein said adhered portion has an adhered width and an adhered length, wherein said adhered width is 1.5 times or more said diameter of said wire, and said adhered width is 3.5 times or less said diameter of said wire, and wherein said adhered length is 1.5 times or more said diameter of said wire, and said adhered length is 3.5 times or less said diameter of said wire.