Patent ID: 7118959

Claim:
A method of forming a capacitor as part of an integrated circuit (IC) fabrication process, comprising: providing a semiconductor substrate having a first layer of metallization formed thereon; forming a layer of antireflective dielectric material over the first layer of metallization, wherein the layer of antireflective dielectric material comprises a layer of antireflective material sandwiched between a first layer of dielectric material and a second layer of dielectric material; forming a second layer of metallization over the layer of antireflective dielectric material; and patterning the second layer of metallization, the layer of antireflective dielectric material and the first layer of metallization to establish the capacitor which has a top conductive electrode formed from the second layer of metallization, a nonconductive capacitor dielectric formed from the layer of antireflective dielectric material and a bottom conductive electrode formed from the first layer of metallization.