Patent ID: 7075140

Claim:
A non-volatile memory array including memory cells arranged in rows and columns, the memory array comprising: a plurality of control lines each associated with one of the rows of the memory array; a plurality of bitlines each associated with one of the columns of the memory array; a plurality of source lines each associated with a group of the columns of the memory array; a plurality of well regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, each well region being spaced apart and electrically isolated; a plurality of memory cells arranged in rows and columns, each column of memory cells being positioned within one of the plurality of well regions, the columns of the memory cells being divided into a plurality of groups and the rows of the memory cells being divided into a plurality of sectors, each memory cell comprising: a memory transistor formed in the respective well region, the memory transistor comprising a source, a drain, and a floating gate formed over a channel of the memory transistor; and a control/select gate coupled between a respective control line and the floating gate of the memory transistor; a plurality of drain select transistors and a plurality of drain select lines, each drain select transistor being provided for a sector of memory cells in each column of memory cells and having a drain coupled to a respective bitline, a source and a gate, the gate of each drain select transistor being coupled to a respective drain select line; and a plurality of source select transistors and a plurality of source select lines, each source select transistor being associated with a sector of memory cells in each column of memory cells and having a drain, a source and a gate, the gate being coupled to a respective source select line, wherein the sources of the source select transistors associated with each group of memory cells are connected together and to a respective source line and are electrically isolated from the sources of the source select transistors associated with other groups of memory cells, the sources of the source select transistors forming a p-n junction with the respective underlying well regions, wherein the memory transistors in a sector of memory cells within a column are connected in series between a respective drain select transistor and a respective source select transistor; and wherein each memory cell in the memory array is programmed and erased by tunneling of electrons between the floating gate and the channel of each memory transistor.