Patent ID: 8854105

Claim:
A signal receiver comprising: a first bias circuit having a first input terminal configured to receive an input signal and to convert the received input signal to a first bias signal, wherein a voltage amplitude of the first bias signal is different from a voltage amplitude of the input signal; a first inverter coupled to the first bias circuit, the first inverter comprising a PMOS device and an NMOS device, each of the PMOS and NMOS devices having a gate, a source, and a drain, the source of the PMOS device coupled to a power supply voltage, the source of the NMOS device coupled to a ground, the drains of the PMOS and NMOS devices being coupled together forming a first node, the gate of the PMOS and NMOS devices being coupled to either the input signal or to the first bias signal in response to the voltage amplitude of the first bias signal; and a second inverter coupled to the first node.