Patent ID: 7102412

Claim:
A loading circuit capable of canceling a DC offset, the loading circuit receiving a first input signal and a second input signal and generating a first output signal and a second output signal without the DC offset and comprising: a first current mirror unit for receiving the first input signal and generating a first signal current proportional to the first input signal; a first compensation unit for receiving the first input signal, filtering AC components of the first input signal, and generating a first compensation current proportional to DC components of the first input signal; a second current mirror unit for receiving the second input signal and generating a second signal current proportional to the second input signal; a second compensation unit for receiving the second input signal, filtering AC components of the second input signal, and generating a second compensation current proportional to DC components of the second input signal; a first loading unit for receiving the first signal current as well as the second compensation current and generating the first output signal; and a second loading unit for receiving the second signal current as well as the first compensation current and generating the second output signal.