Patent ID: 8386719

Claim:
A shared memory control apparatus comprising: a processing unit configured to process an application program; a user program unit configured to execute a program written by a user based on the application program of the processing unit and comprising a register; a shared memory unit connected to each of the processing unit and the user program unit through a system bus and configured to store data interchanged between the processing unit and the user program unit; and a control unit configured to relay a control signal stored in the register indicating whether the system bus, by which the data is interchanged between the processing unit and the user program unit, is occupied, and control connection of each of the processing unit and the user program unit with the system bus in response to the control signal, wherein the system bus includes: a first system bus configured to connect the processing unit and a bi-directional buffer; and a second system bus configured to connect the bi-directional buffer, the shared memory unit, and the user program unit with the bi-directional buffer controlling connections between the processing unit, user program unit and the shared memory in response to the control signal.