Patent ID: 8108192

Claim:
A simulator apparatus which simulates a behavior of an image forming apparatus in order to verify the behavior, comprising: a CPU; a computing unit which performs a sheet conveying simulation operation of the behavior of said image forming apparatus; and a selection unit which selects one of a high-speed mode and a low-speed mode in accordance with a designation from a user, wherein said computing unit executes the high-speed mode in which the sheet conveying simulation operation is performed at a first simulation speed and the low-speed mode in which the sheet conveying simulation operation is performed at a second simulation speed that is slower than the first simulation speed, wherein when the selection unit selects the low-speed mode, the computing unit outputs a synchronization signal when a particular predetermined real time interval has elapsed to enable simulation time and real time to coincide with each other, wherein when the selection unit selects the high-speed mode, the computing unit outputs the synchronization signal without awaiting any predetermined real time interval to enable the simulation time to progress independently of real time, wherein the selection unit makes the user select (a) a timing at which a mode of the simulation operation is switched and (b) one of the high-speed mode and the low-speed mode to be switched to at the selected timing, wherein said selection unit includes a reception unit which receives input for selecting the high-speed mode or the low-speed mode even before or during execution of the sheet conveying simulation operation by said computing unit, wherein the selection unit populates a table with information comprising the user-selected timing and mode to be switched, wherein the selection unit sets a reception flag to true in response to reception of the user-selected timing and mode to be switched, and wherein the computing unit is implemented at least in part by the CPU.