Patent ID: 7969249

Claim:
A phase locked loop circuit comprising: a voltage controlled oscillator configured to generate an oscillation signal; a frequency divider configured to multiply the frequency of the oscillation signal; a phase frequency detector configured to compare the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal; a charge pump configured to generate a signal with a controlled current amount according to the error signal; a waveform generator configured to generate a signal with various amplitudes and periods; a loop filter charged/discharged according to the signal of the charge pump or the signal of the waveform generator, and controlling the voltage controlled oscillator to modulate the frequency of the oscillation signal and generate a spread spectrum clock; a switching circuit configured to selectively connect the output of the waveform generator and the charge pump to the loop filter; and a lock detector connected to the phase frequency detector to control the switching circuit such that the charge pump is connected to the loop filter during a non-lock state of the reference signal and the frequency-multiplied oscillation signal, and the waveform generator is connected to the loop filter during the lock state of the reference signal and the frequency-multiplied oscillation signal.