Patent ID: 8558400

Claim:
A semiconductor package, comprising: a wiring board with a first surface including at least one first connection pad and a second surface including at least one second connection pad, the second surface on a side of the wiring board opposite the first surface; a semiconductor chip with a bonding pad area including at least one bonding pad and an adhesive area outside of the bonding pad area, the semiconductor chip on the first surface, the bonding pad electrically connected to the first connection pad; a first molding layer between the adhesive area and the first surface of the wiring board, the first molding layer including an adhesive material; and a second molding layer between the bonding pad area and the first surface of the wiring board, a modulus of a material included in the first molding layer less than a modulus of a material included in the second molding layer, wherein ends of the second molding layer contact the first surface of the wiring board to surround the wiring board thereof.