Patent ID: 8468306

Claim:
A method for storing data in a pipelined processor, the method comprising: issuing a store request that comprises a store address; determining whether the store address matches an address of a previous store instruction in a store address queue, the determining performed based on issuing the store request; based on determining that the store address does not match the address of the previous store instruction in the store address queue, reading out store background data from a cache of the processor based on the address and writing the store queue with the address and background data and setting a most recent state bit, the background data comprising data that is read from the cache but unmodified by the store request; based on determining that the store address does match the address of the previous store instruction in the store address queue, determining whether the entry in the store address queue comprising a set most recent state bit comprises store data for forwarding, the set most recent state bit indicating a most recent entry in the store address queue matching the address of the previous store instruction and including the store data to be provided as part of the background data; and based on determining that the entry in the store address queue comprising the set most recent state bit does not comprise store data for forwarding, for the most recent entry in the store address queue that matched, updating a cold forwarding state of the matching entry to point to a new entry in a store queue for the store request, resetting the most recent state bit and writing a store address and setting a state bit of the new entry signifying the most recent entry, the cold forwarding state indicating that the store data is to be forwarded as part of the background data after the store data for the entry is received.