Patent ID: 7329953

Claim:
A planar insulating layer with contact openings on a substrate having device areas comprised of: a conducting layer having an anti-reflective coating on top surface and patterned to have open areas on said substrate, wherein said patterned conducting layer is the top electrode of a capacitor; said planar insulating layer on said patterned conducting layer having said contact openings of varying depths to said device areas; some of said contact openings extending down to and over an edge of said patterned conducting layer within said opening areas for forming low-resistance contacts to said edge of said patterned conducting layer, wherein at least two of said contact openings extending down to and over an edge of said patterned conducting layer within said opening areas are etched over said edge of said patterned conductive layer in said opening areas on opposite sides of said open areas to allow for more relaxed alignment tolerances, wherein said patterned conducting layer is the top electrode of a capacitor; whereby at least one opening is filled with a conductive material that directly abuts a sidewall of the anti-reflective coating and the patterned conductive layer.