Patent ID: 8553489

Claim:
A semiconductor device comprising: an external terminal to which an address signal is supplied; an input selection circuit; an output selection circuit; a plurality of address latch circuits each having an input node electrically connected to the external terminal via the input selection circuit and an output node electrically connected to an internal circuit via the output selection circuit; and a control circuit including a first circuit of a shift register type that generates a plurality of first control signals indicating a first value and a second circuit of a binary type that generates a plurality of second control signals indicating a second value, wherein the input selection circuit selects anyone of the input nodes of the address latch circuits based on the first value, the output selection circuit selects any one of the output nodes of the address latch circuits based on the second value, the first circuit updates the first value in response to an external command that is issued from outside, and the second circuit updates the second value when a predetermined latency defined by an integer multiple of a clock cycle has passed since the external command is issued.