Patent ID: 8580624

Claim:
A method of fabricating a complementary metal-oxide semiconductor (CMOS) circuit having a nanowire field-effect transistor (FET) and a finFET, the method comprising the steps of: providing a wafer having an active layer over a buried oxide (BOX), wherein the active layer has at least a first region and a second region; thinning the first region of the active layer, such that the first region and the second region of the active layer form a stepped surface; depositing an organic planarizing layer on the active layer so as to provide a flat surface over the stepped surface; forming a first lithography hardmask on the organic planarizing layer over the first region of the active layer and a second lithography hardmask on the organic planarizing layer over the second region of the active layer; etching nanowires and pads in the first region of the active layer using the first hardmask, wherein the pads are attached at opposite ends of the nanowires in a ladder-like configuration; suspending the nanowires over the BOX; etching fins in the second region of the active layer using the second hardmask; forming a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the first gate stack serve as a channel region of the nanowire FET; forming a second gate stack covering at least a portion of each of the fins, wherein the portions of the fins covered by the second gate stack serve as a channel region of the finFET; and growing an epitaxial material on exposed portions of the nanowires, pads and fins, wherein the epitaxial material grown on the exposed portions of the nanowires and pads serve as source and drain regions of the nanowire FET and wherein the epitaxial material grown on the exposed portions of the fins serve as source and drain regions of the finFET.