Patent ID: 8242827

Claim:
A differential latch comprising a first data holding transistor and a second data holding transistor, said differential latch comprising: a first resetting transistor that is connected to a gate electrode of said first data holding transistor and is controlled by a reset signal; a first switching transistor that is connected to the gate electrode of said first data holding transistor and is controlled by a switch signal, being an inverted version of said reset signal; a second resetting transistor that is connected to the gate electrode of said second data holding transistor is controlled by the reset signal; and a second switching transistor that is connected to the gate electrode of said second data holding transistor and is controlled by said switch signal: a first setting transistor that is connected to the gate electrode of said first data holding transistor and is controlled by an inverted set signal, being an inverted version of a set signal; and a second setting transistor that is connected to the gate electrode of said second data holding transistor and is controlled by said set signal.