Patent ID: 7948807

Claim:
A semiconductor memory device, comprising: a plurality of first pads to which a first general data is input respectively; a second pad to which any one of a second general data and a representative data corresponding to a second mode is input; data aligning units which align the data input of the first pads and the second pad in a burst sequence order; a routing controller which allows the representative aligned data to be routed over a transfer path corresponding to the first pads and the second pad in the second mode and prevents the second general aligned data from being routed over a transfer path corresponding to the first pads in cases other than the second mode; a plurality of multiplexers which select and transfer any one of the first general aligned data or the representative aligned data in accordance with the mode; and a plurality of input/output sense amplifying units that amplify the second general aligned data and the data transferred by the multiplexer and transfers them to a global input/output line.