Patent ID: 8051351

Claim:
An integrated circuit comprising; A. a combined TDI signal and TMS signal input lead; B. a TCK signal input lead; C. a TDO signal output lead; D. a double data rate circuit having an input coupled to the combined TDI signal and TMS signal input lead, an input coupled to the TCK signal input lead, a TDI signal output lead coupled to the combined TDI signal and TMS signal input lead, and a TMS signal output lead coupled to the combined TDI signal and TMS signal input lead; E. addressable TAP linking circuitry having a first bus of leads coupled to the TDI signal output lead, the TMS signal output lead, the TCK signal input lead, and the TDO signal output lead, the addressable TAP linking circuitry also having plural second busses, each second bus including a TDI signal lead, a TMS signal lead, a TCK signal lead, and a TDO signal lead, the addressable TAP linking circuitry selectively coupling the first bus to at least one of the second buses; and F. plural TAP domains, each TAP domain having leads connected to the TDI, TMS, TCK and TDO signals of one of the second busses.