Patent ID: 8525771

Claim:
A method of adjusting a phase of a dot clock phase in an image display apparatus for being supplied with a digital video signal whose signal level changes at a constant dot clock that is higher than a frequency of a synchronizing signal representing a display period in a given direction of a displayed image, and displaying an image based on the digital video signal, said method comprising: dividing at least a portion of the displayed image based on the digital video signal, into a plurality of image areas, in a horizontal direction, defined by display lines in said given direction, and establishing different delays for the divided image areas; generating a clock in synchronism with said dot clock, delaying a phase of the clock according to the delays established for respective divided image areas, and outputting the delayed clock as a reproduced dot clock; converting differential data between adjacent signal levels into absolute values and accumulatively adding the absolute values in said given direction based on said reproduced dot clock, with respect to the display lines which define said divided image areas, thereby producing accumulated sums; and judging the delay established for the divided image areas with a maximum accumulated sum, as an optimum delay, wherein a same value of the optimum delay is applied to entire image areas of the displayed image, wherein said accumulatively adding uses an addition unit that adds video signals of said digital video signal at respective predetermined proportions to generate a delay evaluating signal, wherein said video signals comprises a first digital video signal, a second digital video signal, and a third digital video signal, and wherein said accumulatively adding adds said first digital video signal, said second digital video signal, and said third digital video signal with the predetermined proportions that include ¼, ½, ⅛, respectively.