Patent ID: 7684426

Claim:
A system for performing Local Centre Authorization Service (LCAS) in a network, the system comprising: a data aligner configured to align bytes of input data according to groups of members, the groups of members including a virtually concatenated group (VCG); an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner; a de-sequencer configured to de-sequence aligned input data received from the data aligner according to de-sequencing control commands received from the LCAS control manager; and a processor for configuring the LCAS control manager, wherein the LCAS control manager comprises a configurable hardware state machine that generates the de-sequencing control commands and wherein the state machine is configurable while it executes one or more LCAS operations; one or more other FIFOs; a plurality of free running calendars, each calendar determines the level of data in a corresponding FIFO and to initiate a read request if the level of data is lower than a fixed threshold, wherein each calendar follows a preconfigured common order of channels, and wherein the rotation period of one or more calendars is different from rotation periods of the other calendars; and a VC/LCAS alignment block configured to compensate for network differential delay accumulated by a plurality of different channels for deskewing member channels belonging to a common virtually concatenated group (VCG), wherein the system is embodied in a SONET transport processor and wherein the alignment block includes: a write manager configured to temporarily accumulate data and transmit the accumulated data to a storage device in a burst manner after accumulating a predetermined amount of data for a selected channel; a read manager configured to read bursts of the accumulated data from the storage device, store the bursts of accumulated data in a FIFO corresponding to the selected channel, and selectively drain the FIFO such that data for a VCG stored in the FIFO is aligned.