Patent ID: 8198916

Claim:
A digital signal voltage level shifter, comprising: an edge detector for detecting assertion of a digital input signal from a first logic circuit in a source voltage domain; an output module triggered by said edge detector for asserting a digital output signal corresponding to said digital input signal for a second logic circuit in a destination voltage domain, wherein the edge detector and the output module are supplied with power only from a power supply of the destination voltage domain; and a reset generator connected to the output module for asserting a reset signal in response to subsequent de-assertion of the digital input signal, wherein the reset generator is supplied with power only from the power supply of the destination voltage domain; wherein said reset generator comprises: a first switch that is OFF when the digital output signal is de-asserted or the digital input signal is de-asserted, and is ON when said digital output signal is asserted and the digital input signal is asserted; a capacitor charged by the digital input signal through the first switch when the first switch is ON; a second switch that is OFF when the digital input signal is asserted and ON when said digital input signal is de-asserted to conduct a charge on the capacitor; and a third switch that is OFF when the second switch is OFF to enable de-assertion of the reset signal and is ON in response to the charge on the capacitor so as to assert the reset signal when the second switch is ON, and wherein the first and second switches are arranged to prevent leakage of the digital input signal to the destination voltage domain power supply when either of the first and second switches is OFF, and wherein the edge detector asserts a set signal in response to the assertion of the digital input signal, and the output module asserts the digital output signal in response to assertion of the set signal and de-asserts the digital output signal in response to the reset signal.