Patent ID: 8023651

Claim:
A method of providing a digital signal processing function ƒ to an executing device having at least one processor in an obfuscated form; the function ƒ including a function cascade including a plurality of signal processing functions ƒ i , 1≦i≦N, for processing a digital signal input x to yield a digital signal output, the method including: performing the following steps by at least one processor of the executing device: selecting a set of 2N invertible permutations p i , 1≦i≦2N; calculating a set of N functions g i , where g i is functionally equivalent to p 2i −1 ∘ƒ i ∘p 2i−1 , for 1≦i≦N; calculating a set of N−1 functions h i , where h i is functionally equivalent to p 2i−1 −1 ∘p 2i−2 , for 2≦i≦N; equipping the executing device with an execution device function cascade that includes y N ∘h N ∘y N−1 ∘h N−1 ∘ . . . ∘y 1 , where y 1 , . . . , y N are function parameters, providing the functions g 1 , . . . , g N to the executing device; and in the executing device, applying the execution device function cascade to the functions g 1 , . . . , g N , wherein the execution of the g i and h i functions by the executing device in an interleaved manner enables the functionality of the execution device function cascade to be achieved without function ƒ being directly recognizable.