Patent ID: 7098511

Claim:
An ESD protection circuit applied to an IC with power-down-mode operation, comprising: an input circuit, which comprises: an input pad; an input PMOS, wherein the drain of said input PMOS is connected to said input pad; an input NMOS, wherein the drain of said input NMOS is connected to said input pad; and a first internal circuit connected to said input pad through at least one resistor; an output circuit, which comprises: an output pad; an output PMOS, wherein the drain of said output PMOS is connected to said output pad; an output NMOS, wherein the drain of said output NMOS is connected to said output pad; a control PMOS, wherein the drain of said control PMOS is connected to the gate of said output PMOS; a pre-driver circuit connected to the gate of said output PMOS, the gate of said output NMOS, and the drain of said control PMOS, respectively; and a second internal circuit connected to said pre-driver circuit; a VSS power line connected and providing VSS voltage to said first internal circuit, said pre-driver circuit, and said second internal circuit, and still connected to the source and the gate of said input NMOS and the source of said output NMOS; a VDD power line connected and providing VDD voltage to said first internal circuit, said second internal circuits, and the gate of said control PMOS, and then said control PMOS turning off when said VDD voltage is high and said control PMOS turning on to turn off said output PMOS when said VDD power line is grounded under power-down-mode operation, so as to prevent leakage current from occurring because of said output PMQS turning on under power-down-mode operation; an ESD bus line connected to the source and the gate of said input PMOS and still connected to the source of said output PMOS, the source of said control PMOS, and said pre-driver circuit, wherein said pre-driver circuit is coupled to said ESD bus line instead of said VDD power line for obtaining power so as to prevent leakage current induced from said pre-driver circuit to said VDD power line; a first ESD clamp circuit connected between said VSS power line and said ESD bus line; second clamp circuit connected between said VDD power line and said VSS power line; and a diode forward connected between said VDD power line and said ESD bus line to avoid leakage current induced from said input pad to said VDD power line via said input PMOS when said VDD power line is grounded under power-down-mode operation, and still to avoid positive voltage at said input pad charging to said VDD power line through said input PMOS when said VDD power line is floating under power-down-mode operation.