Patent ID: 8111082

Claim:
A test apparatus for testing data in a plurality of channels output from a device under test, the channels being organized as pairs each including two adjacent channels, wherein, in each pair, the first channel comprises: a first timing comparator operative to determine the level of first output data fed from the device under test to the first channel, timed in accordance with a first strobe signal; a first clock envelope extractor operative to extract an envelope of a clock from the first output data; a first clock recovery circuit operative to recover the first strobe signal with reference to the envelope of the clock extracted by the first clock envelope extractor; a first main latch circuit operative to latch an output from the first timing comparator, timed in accordance with the first strobe signal; a first sub-latch circuit operative to latch the envelope of the clock extracted by the first clock envelope extractor, timed in accordance with the first strobe signal; a first hunt circuit operative to compare an output from the first main latch circuit with a predetermined header pattern; and a first expected value comparison unit operative to compare the output from the first main latch circuit with a predetermined expected value pattern, in response to the detection by the first hunt circuit that the output from the first main latch circuit matches the header pattern, and the second channel comprises: a second timing comparator operative to determine the level of second output data fed from the device under test to the second channel, timed in accordance with a second strobe signal; a second clock envelope extractor operative to extract an envelope of a clock from the second output data; a second clock recovery circuit operative to recover the second strobe signal with reference to the envelope of the clock extracted by the second clock envelope extractor; a first delay circuit operative to apply a variable phase shift to the first strobe signal; a first selector operative to receive an output from the second timing comparator and an output from the first sub-latch circuit, and select and output one of the outputs; a second selector operative to receive an output from the first delay circuit and the second strobe signal, and select and output the output or the signal; a second main latch circuit operative to latch an output from the first selector, timed in accordance with an output signal from the second selector; a second hunt circuit operative to compare an output from the second main latch circuit with a predetermined header pattern; and a second expected value comparison unit operative to compare the output from the second main latch circuit with a predetermined expected value pattern, in response to the detection by the second hunt circuit that the output from the second main latch circuit matches the header pattern.