Patent ID: 7185270

Claim:
A decoder that is operable to perform hybrid decoding of an LDPC (Low Density Parity Check) coded modulation signal, the decoder comprising: a symbol sequence estimate and symbol node update functional block that receives a plurality of symbol metrics corresponding to a symbol of a plurality of symbols of the LDPC coded modulation signal and also receives a plurality of initialized LLR (log likelihood ratio) bit edge messages; wherein: the plurality of bit edge messages corresponds to a plurality of edges that communicatively couple a plurality of symbol nodes to a plurality of check nodes within an LDPC coded modulation bipartite graph that corresponds to an LDPC code; the symbol sequence estimate and symbol node update functional block computes a first plurality of possible soft symbol estimates for the symbol; the symbol sequence estimate and symbol node update functional block updates the plurality of bit edge messages using the plurality of symbol metrics and the plurality of initialized LLR bit edge messages thereby generating a first updated plurality of bit edge messages; a check node update functional block that updates a plurality of check edge messages using the first updated plurality of bit edge messages thereby generating a first updated plurality of check edge messages; wherein: the symbol sequence estimate and symbol node update functional block computes a second plurality of possible soft symbol estimates for the symbol using the first updated plurality of check edge messages; the symbol sequence estimate and symbol node update functional block updates the first updated plurality of bit edge messages using the received plurality of symbol metrics and the first updated plurality of check edge messages thereby generating a second updated plurality of bit edge messages; during a last iterative decoding iteration, the symbol sequence estimate and symbol node update functional block makes a best estimate for the symbol of the plurality of symbols of the LDPC coded modulation signal using that symbol's most recent corresponding plurality of possible soft symbol estimates; and a hard limiter makes bit estimates based on the best estimate for the symbol such that the bit estimates are hard decisions for each of the individual bits of the symbol.