Patent ID: 8281188

Claim:
In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method comprising: initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals; in response to initiating the write, providing the configuration information via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface; storing the configuration information in a first storage location of the first peripheral; storing the first error syndrome in storage circuitry of the peripheral bus interface; reading the configuration information from the first storage location after the storing the configuration information; generating by the peripheral bus interface a second error syndrome of the configuration information read from the first storage location from the reading the configuration information; comparing the first error syndrome with the second error syndrome to determine if an error exists in the configuration information read from the first storage location; wherein the first master initiates the write of the configuration information stored in the first peripheral in accordance with a first memory mapping of the plurality of peripherals, and the reading of the configuration information stored in the first peripheral is initiated in accordance with a second memory mapping of the plurality of peripherals, different from the first memory mapping.