Patent ID: 8190828

Claim:
An integrated circuit comprising: a programmable logic portion; and an embedded processor portion coupled to the programmable logic portion, the embedded processor portion comprising: a processor; and a first memory coupled to the processor, the first memory comprising: a plurality of memory cells; a first port coupled to the plurality of memory cells and directly connected to the processor; and a second port coupled to the plurality of memory cells and directly connected to the programmable logic portion, wherein: the first port and the second port are each capable of accessing each of the plurality of memory cells to perform read operations and write operations, and the second port has a configurable width and a configurable depth, and a depth of a memory map is increased and a width of the memory map is not changed in response to the width of the second port being decreased, and the depth of the memory map is decreased and the width of the memory map is not changed in response to the width of the second port being increased; a second memory having a third port, the third port having a configurable width and a configurable depth; and control circuitry operable to operate the second and third ports as a single port, wherein the single port has a width that is a sum of the width of the first port and the width of the second port, or the single port has a depth that is a sum of the depth of the first port and the depth of the third port.