Patent ID: 8564588

Claim:
An interface apparatus comprising: a signal synthesizer for outputting at least one of display signals, display control signals, and chip control signals; a connector including a first transmission line connected with the signal synthesizer and for sequentially transmitting the chip control signals and the display signals, and a second transmission line for transmitting the display control signals; and a signal separator for separating the display signals and the chip control signals from the first transmission line, wherein the signal synthesizer outputs the chip control signals to the first transmission line for a first period and outputs the display signals to the first transmission line for a second period under a control of the display control signals, wherein the signal synthesizer outputs the display signals and the chip control signals in turn, wherein the chip control signals comprise chip select signals, serial clock signals, and serial data input signals, wherein the signal separator outputs the display signal to a timing controller and signal converter, wherein the display control signals comprises horizontal synchronized input signals, vertical synchronized input signals, data enable signals, and data clock signals, and wherein the first period is a section when the data enable signals is disabled.