Patent ID: 8755241

Claim:
A method for programming an anti-fuse memory block of a power integrated circuit (IC) device, comprising: applying an external voltage that is higher than the ground potential to a pin of the power IC device, the pin being coupled to a first terminal of a junction field-effect transistor (JFET) device, the JFET device limiting the external voltage to a tap voltage at a second terminal of the JFET device when the external voltage applied to the pin exceeds a pinch-off voltage of the JFET device; activating a switching element coupled to a selected anti-fuse element of the anti-fuse memory block, the selected anti-fuse element including first and second capacitive plates separated by a dielectric layer, the first capacitive plate being coupled to an internal node of the power IC device, the switching element being coupled to the second plate of the selected anti-fuse element, when activated the second plate of the selected anti-fuse element being coupled to a ground potential; turning on an isolation transistor to couple the second terminal to the internal node; applying a pulsed voltage to the internal node via the pin such that a programming voltage is applied to the first capacitive plate of the selected anti-fuse element, the programming voltage being high enough to cause a current to flow through the selected anti-fuse element sufficient to destroy at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.