Patent ID: 6912703

Claim:
A layout structure for integrated circuit standard circuit cells; comprising: a first power bus, wherein said first power bus is arranged in a straight line; a second power bus, wherein said second power bus is arranged in a straight line parallel to said first power bus, and electrically connected to said first power bus; a third power bus, wherein said third power bus is arranged in a straight line parallel to said first power bus and located between said first power bus and said second power bus; a plurality of first cells arranged in a first row and located between said first power bus and said third power bus, wherein said first cells are coupled to said first power bus and said third power bus; and a plurality of second cells arranged in a second row and located between said second power bus and said third power bus, wherein said second cells are electrically coupled to said first cells, said second power bus, and said third power bus, wherein one of said first cells and one of said second cells combine to form a standard cell.