Patent ID: 8110878

Claim:
A semiconductor device comprising: a substrate of a first conductivity type; a deep well of a second conductivity type different from the first conductivity type which is formed in the substrate; a first shallow well of the first conductivity type and a second shallow well of the second conductivity type which are formed in mutually different regions in the substrate; a first field effect transistor of the second conductivity type which is formed in the first shallow well; a second field effect transistor of the first conductivity type which is formed in the second shallow well; a third shallow well of the first conductivity type and a fourth shallow well of the second conductivity type which are formed in mutually different regions in the deep well; a third field effect transistor of the second conductivity type which is formed in the third shallow well; a fourth field effect transistor of the first conductivity type which is formed in the fourth shallow well; a sixth shallow well of the first conductivity type which is formed in a region different from respective regions in the substrate where the deep well, the first shallow well, and the second shallow well are formed; and a diffusion layer of the second conductivity type which is formed in the sixth shallow well, wherein the diffusion layer is wired to a fourth diffusion tap of the second conductivity type which is formed in the fourth shallow well using an interconnection in an n-th layer, and wherein respective gate electrodes of the third field effect transistor the fourth field effect transistor are wired to respective drain electrodes of the first field effect transistor and the second field effect transistor using an interconnection in an n-th or higher order layer.