Patent ID: 7243195

Claim:
A method for computer program code optimization for a software managed cache in either a uni-processor or a multi-processor system, comprising: receiving a single source file comprising a plurality of array references; analyzing the plurality of array references to identify predictable accesses; analyzing the plurality of array references to identify secondary predictable accesses; aggregating one or more of the plurality of array references based on identified predictable accesses and identified secondary predictable accesses to generate aggregated references; restructuring the single source file based on the aggregated references to generate restructured code; inserting prefetch code in the restructured code based on the aggregated references; inserting software cache update code in the restructured code based on the aggregated references; inserting explicit cache lookup code for the remaining unpredictable accesses; inserting calls to a miss handler for misses in the explicit cache lookup code; including a miss handler in the generated code for the program; in the miss handler, choosing a line to evict based on recent usage and predictability; and in the miss handler, issuing appropriate DMA commands for the evicted line and the missing line.