Patent ID: 6998316

Claim:
A fabrication method for a read only memory device, comprising: providing a substrate, the substrate comprises a memory cell region and a periphery circuit region, wherein a memory cell array is formed in the memory cell region and a plurality of transistors is formed in the periphery circuit region; forming a negative photoresist layer on the memory cell region; performing a first exposure process to transfer a pattern in a first photomask to the negative photoresist layer, wherein the pattern in the first photomask corresponds to each memory cell in the memory cell region, and a non-crosslinked portion of the negative photoresist layer is positioned above the channel region of each memory cell in the memory cell region; performing a second exposure process to transfer a pattern in a second photomask to the negative photoresist layer, wherein the pattern of the second photomask precisely corresponds to at least one pre-coding memory cell region in the memory cell region and the gates of the transistors in the periphery circuit region, and non-crosslinked portions of the photoresist layer are positioned above the pre-coding memory cell region in the memory cell region and above the gates of the transistors in the periphery circuit region; performing a development process to pattern the negative photoresist layer; and performing an ion implantation process to the pre-coding memory cell region and to adjust a threshold voltage of the transistors using the patterned negative photoresist layer as a mask.