Patent ID: 7309892

Claim:
A semiconductor element comprising: a memory array including a plurality of memory elements, the plurality of memory elements being arranged in a shape of a matrix; wherein each of the plurality of memory elements includes: a channel, a carrier confinement region disposed over the channel and isolated therefrom by a first insulator, and a gate electrode disposed over the carrier confinement region and isolated therefrom by a second insulator and from the channel by the first and second insulators, wherein the gate electrodes of the plurality of memory elements arranged in a first direction are connected to each other, wherein edges of the plurality of memory elements arranged in a second direction across the first direction are connected to each other, wherein a distance between the carrier confinement region and the gate electrode is larger than a distance between the carrier confinement region and the channel, wherein a total capacitance Ctt around the carrier confinement region satisfies the condition q 2 /2 Ctt>kT where k is Boltzmann's constant, T is the room temperature in degrees Kelvin and q is the charge of an electron.