Patent ID: 7876126

Claim:
An integrated circuit, comprising: a L-level permutable switching network (L-PSN); wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches: wherein the (L+2) levels of conductors comprises: for i=[1:L], (I[i]/D[i])>1, D[i]>1, L≧1, at least one j selected from [1:L] with D[j]>2, each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors; an 0-th level of conductors of I[0] number of conductors, wherein (I[0]/Π i=[1:L] D[i])>1; and an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors, wherein D[L+1]>2 and each of the D[L+1] sets of conductors comprises Π i=[1:L] D[i] number of conductors; wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1]; wherein the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1]; wherein the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module; and at least one j selected from [1:L+1], T>1 and D S [j]=D[j]×(I[j−1]/I[j], any (T×D S [j]) number of conductors of the (j−1)-th level of conductors selectively couple to at least T number of conductors in each of the D[j] sets of conductors of the j-th level of conductors through (T×D S [j]×D[j]) number of switches of the j-th set of switches, wherein any D S [j] number of conductors selected from the (T×D S [j]) number of conductors selectively couple to at least two conductors of at least one of the D[j] sets of conductors through a respective D S [j] number of switches of the (T×D S [j]×D[j]) number of switches.