Patent ID: 6894532

Claim:
A programmable logic array, comprising: a plurality of inputs; a plurality of outputs; and a plurality of vertical transistors including a first number of transistors coupled to the inputs and a second number of transistors coupled to the outputs, the plurality of vertical transistors being interconnected in a predetermined manner to receive an input signal on the inputs and provide an output signal on the outputs according to a predetermined logic function, wherein each vertical transistor includes: a single crystalline semiconductor material formed along a side of a vertical pillar that extends outwardly from a substrate, the single crystalline semiconductor material having a width extending away from the vertical pillar of less than 10 nm; a first diffusion region of a first conductivity type formed in the single crystalline semiconductor material; a second diffusion region of the first conductivity type formed in the single crystalline semiconductor material; and a body region of a second conductivity type separating the first and the second diffusion regions.