Patent ID: 7629640

Claim:
A non-volatile semiconductor memory cell, comprising: a body having two semiconductor fins physically separated from each other; a source region disposed on each of the two semiconductor fins; a drain region disposed on each of the two semiconductor fins; two channels between said source region and said drain region with said two channels disposed on opposite, non-facing, sides of said two semiconductor fins; a tunnel oxide layer overlying each of said two channels on opposite, non-facing sides of said two semiconductor fins between said source region and said drain region; first and second charge storage regions overlying said tunnel oxide layer overlying each of said two channels between said source region and said drain region; four separate charge storage sites, each comprising charge-trapping material, within said first and second charge storage regions, wherein two physically separated charge storage sites are provided for each of said two channels; wherein said memory cell is disposed within a plurality of memory cells with said source region and said drain region each shared between two channels which are within the same or different memory cells within the plurality of memory cells; a control oxide layer overlying portions of each of said first and second charge storage regions overlying said tunnel oxide layer overlying each of said two channels between said source region and said drain region; at least one gate configured as a word line overlying said control oxide layer.