Patent ID: 8339889

Claim:
A semiconductor memory device comprising: a memory core comprising a trim circuit that stores trim information controlling at least one operation selected from a group of operations including a read operation, a write operation and an erase operations; a charge pump circuit configured to generate and provide a high voltage signal to the memory core during the at least one operation; and a charge pump control circuit configured to control operation of the charge pump circuit, wherein each of the charge pump circuit and charge pump control circuit are operable in a normal mode during which the at least one operation is executed and in a test mode during which trim information is generated, a combination of the charge pump circuit and the charge pump control circuit being configured during the normal mode to operate in one of an active operation during which the high voltage signal is provided to the memory core and a standby operation during which a level of the high voltage signal is maintained, the combination being further configured during the standby operation in the test mode to provide a time value, wherein the time value is saved as trim information controlling the charge pump control circuit in the generation of the high voltage signal during the standby operation in the normal mode.