Patent ID: 7681013

Claim:
A method for execution by a microprocessor in response to receiving a single instruction, the method comprising: receiving a string of bits having a first plurality of segments; receiving a plurality of data elements including a control information specifying a location and a length of a second plurality of segments in the string of bits; generating a plurality of indices for one or more look-up tables that includes selecting the second plurality of segments from the first plurality of segments based on the control information; receiving a configuration indicator, wherein the configuration indicator indicates how to configure a plurality of look-up units into one or more look-up tables for execution of the single instruction; configuring the plurality of look-up units into the one or more look-up tables according to the configuration indicator; looking up simultaneously a plurality of entries from the one or more look-up tables using the plurality of indices, the one or more look-up tables configured from the plurality of look-up units, wherein each of said plurality of look-up units is a memory unit that is separate and distinct from others of said plurality of look-up units and is individually accessible independent of operations of the other look-up units, wherein a number of bits in the indices for the entries into the one or more look-up tables varies based upon how the plurality of look-up units are configured into the one or more look-up tables; and combining the plurality of entries into a first result; wherein the above operations are performed in response to the microprocessor receiving the single instruction.