Patent ID: 7404163

Claim:
A method for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply, the method comprising: constructing a timing model of an IC based on an upper end voltage supply and a lower end voltage supply; selecting an endpoint in the IC to perform a static timing slack analysis on the endpoint based on the upper end voltage supply and the lower end voltage supply; selecting a candidate timing path with a bounded static timing slack of a minimum value among all timing paths leading to the selected endpoint based on the static timing slack analysis; determining a transient static timing slack of the candidate timing path based on the transient power supply; and modifying the bounded static timing slack of the candidate timing path based on the transient static timing slack, wherein the transient static timing slack determining includes calculating an early mode delay of a second signal in an element in a second path leading to the endpoint based on the transient power supply, and the early mode delay calculating includes: determining an early mode arrival time for the second signal to arrive at an input of the element; determining a voltage value of the transient power supply on the element at the early mode arrival time; calculating an interim early mode delay based on the voltage value on the element at the early mode arrival time; determining a maximum voltage value of the transient power supply on the element within a time period of the interim early mode delay; and calculating the early mode delay based on the determined maximum voltage value.