Patent ID: 8369166

Claim:
A non-volatile memory comprising: n cells for storing an n-bit entry where a defective cell of the n cells is settable to a permanent logic state, where n is an integer value of at least 1; an inversion status cell programmable from a default first logic state to a second logic state when the n cells store program data inverted relative to input data received by the non-volatile memory; and a data register for inverting the input data into the program data in response to a mismatch between the permanent logic state of the defective cell and a logic state of a bit of the input data to be programmed to the defective cell, and for inverting read data from the n cells when the inversion status cell stores the second logic state, the data register including: n register cells corresponding to each of the n cells for storing a bit of the input data and a bit of the read data, each of the n register cells inverting the bit of the input data in response to a program inversion signal and inverting the bit of the read data in response to a read inversion signal; and an inversion register cell corresponding to the inversion status cell for providing the program inversion signal in response to the mismatch between the permanent logic state of the defective cell and a logic state of a bit of the input data to be programmed to the defective cell.