Patent ID: 8518780

Claim:
A method comprising: providing a substrate having a first region, a second region, and a third region; forming a first dielectric layer having a first thickness in the first region of the substrate; forming a second dielectric layer after said forming a first dielectric layer, said second dielectric layer having a second thickness in the second region and the third region of the substrate, said second dielectric layer not in the first region of the substrate; forming a sacrificial layer over the first dielectric layer and the second dielectric layer; patterning the sacrificial layer, the first dielectric layer, and the second dielectric layer to form a first gate stack, a second gate stack, and a third gate stack in the first region, the second region, and the third region, respectively; forming an interlayer dielectric (ILD) layer in between the first gate stack, the second gate stack, and the third gate stack; removing the second gate stack to form an opening adjacent to the ILD layer while retaining the first gate stack and the third gate stack; and forming a third dielectric layer having a third thickness in the opening.