Patent ID: 7750656

Claim:
A distribution circuit for distributing a test signal applied on a first pad of a single integrated circuit, comprising a semiconductor substrate and circuitry thereon, to a plurality of replica pads of the first pad during a test of the single integrated circuit, comprising: a master buffer on the single integrated circuit having an input and an output, the input being coupled to the first pad and said master buffer configured to generate a replica of the test signal on the output; an electrically parallel interconnection bus on the single integrated circuit coupled to the output of said master buffer; and a slave buffer on the single integrated circuit for each replica pad, and having an input and an output, the input being coupled to said electrically parallel interconnection bus for receiving the replica of the test signal, each slave buffer replicating the test signal on the output coupled to a respective replica pad; said electrically parallel interconnection bus electrically coupling the output of said master buffer to each slave buffer in parallel.