Patent ID: 7222204

Claim:
A method of testing priority levels of the servicing of interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when enabled, each interrupt source having a default priority level and an associated memory, the interrupt sources having a service order in which they are to be serviced, the method comprising the steps of: (a) sorting the interrupt sources in descending service order; (b) determining a priority window comprising an array of priority levels to be assigned in a pre-arranged sequence to selections of interrupts in descending service order; (c) incrementing a global counter; (d) assigning the array of priority levels to a selected group of interrupts, the remainder of the interrupts assuming their default priority level; (e) enabling all interrupts simultaneously except the interrupt source having the highest priority level so that the interrupt having the second highest priority level executes its interrupt service routine unless two or more of the interrupts each have the same highest priority level, in which event the interrupt having a highest service order executes its interrupt service routine; (f) transferring the value of the global counter into the memory of the interrupt executing its interrupt service routine; (g) enabling all interrupts simultaneously including the interrupt source having the highest priority level; (h) incrementing the global counter; (i) transferring the value of the global counter into the memory of the interrupt source executing its interrupt service routine; (j) repeating steps (c) to (i) to the next selected group of interrupts until the pre-arranged sequence is completed; and (k) comparing the interrupt memory values after completion of the pre-arranged sequence with expected values and determining from the comparison whether there is an error in the priority levels of the interrupt sources.