Patent ID: 8880811

Claim:
A data processing device comprising: a memory comprising a plurality of memory regions; a first data processing component; a control memory comprising, for each memory region of the plurality of memory regions, an indication whether a data access to the memory region may be carried out by the first data processing component; and a second data processing component; wherein the first data processing component comprises a checking circuit configured to check, for a memory region, whether a data access to the memory region may be carried out by the first data processing component based on the indication for the memory region; a data access circuit configured to carry out the data access to the memory region if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to reset the indication for the memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of the data access of the first data processing component to the memory region; wherein the indication that a data access to the memory region may be carried out by the first data processing component is the specification that the data block size of a data block stored in the memory region is bigger than zero.