Patent ID: 7043828

Claim:
A tile-based routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board, the multi-layer circuit board comprising at least a first layer and a second layer, the method comprising: arranging the plurality of bumper pads as a bumper-tile block by a specific forming process; assigning the plurality of signal traces corresponding to the plurality of bumper pads of the bumper-tile block as a plurality of first-layer traces being routed in the first layer; assigning the plurality of signal traces corresponding to the plurality of bumper pads of the bumper-tile block as a plurality of second-layer traces being routed in the second layer; routing the plurality of first-layer traces straight forward; routing the plurality of second-layer traces with a turn being configured not to be vertically parallel with the plurality of first-layer traces; and shielding the plurality of first-layer traces and the plurality of second-layer traces.