Patent ID: 8285973

Claim:
A method of controlling allocation of instruction processing resources among multiple threads executing in a multi-threaded processor, the method comprising: fetching instructions for the multiple threads from a storage; decoding the instructions for the multiple threads to produce decoded instructions; issuing the decoded instructions to execution pipelines; counting completions of instructions by execution units in the pipelines for the multiple threads to obtain corresponding counts of instruction completions for each corresponding thread, wherein each completion of an instruction by each thread increments a corresponding one of the counts, values of the counts track to the number of instruction completions accomplished by the corresponding threads; and controlling the allocation of the processing resources among the multiple threads in conformity with the values of the counts by allocating the processing resources in proportion to the values of the counts, wherein the controlling directly controls rates of instruction pre-fetching or instruction decoding for the individual ones of the multiple threads in conformity with the number of completions accomplished by the multiple threads.