Patent ID: 7143126

Claim:
Apparatus for implementing a power of two floating point estimation function comprising: a processor for storing a floating point number within a memory; said floating point number including a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits; said processor in response to a floating-point instruction, for partitioning said mantissa into an integer part and a fraction part, based on said exponent bits; and for yielding a floating-point result by assigning said integer part of said floating point number as an unbiased exponent of said floating-point result, combinational logic hardware for converting said fraction part of said floating point number to a fraction part of said floating point result; and said plurality of said fraction bits of said mantissa of said floating point number are represented by F and said combinational logic hardware for converting said fraction part of said floating point number to a fraction part of said floating point result includes first combinational logic receiving said fraction bits F for producing two numbers represented by A and B, where the sum of A and B subtracted from F produces said fraction part of said floating point result.