Patent ID: 7080270

Claim:
An integrated circuit, comprising: a sleep switch, provided between a first power supply line and a second power supply line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode; a latch circuit, connected to said second power supply line, which is constituted by a transistor of a second threshold voltage which is lower than said first threshold voltage; a ferroelectric capacitor for storing data held in said latch circuit in accordance with polarization direction of a ferroelectric film thereof; and a control signal generating circuit which, when returning to an active mode from said sleep mode, generates a plate signal for driving a terminal of said ferroelectric capacitor to generate a voltage in said latch circuit in accordance with the polarization direction, and generates a sleep signal for causing said sleep switch to conduct to thereby activate said latch circuit following the driving of said ferroelectric capacitor.