Patent ID: 7185122

Claim:
A data transfer control device for controlling data transfer between a first memory having a predetermined storage capacity and a second memory corresponding to a buffer memory incorporated in a peripheral module, said data transfer control device comprising: a first register for storing a first value representing a first number of times, by which data transfer is performed from the first memory to the second memory, the first value being determined based on a number of bits of data being output from the first memory and a storage capacity of the second memory; a second register for storing a second value representing a second number of times by which data transfer is performed from the first memory to the second memory, the second value being determined based on an amount of data being stored in the first memory and being transferred to the second memory and the number of bits of data being output from the first memory; and a controller for controlling data the data transfer from the first memory to the second memory in accordance with the first value and for outputting an interrupt signal to a when a value accumulating the number of times data transfer is performed from the first memory to the second memory matches the second value.