Patent ID: 8283233

Claim:
A method for fabricating an MOS structure, the method comprising the steps of: providing a semiconductor substrate; fabricating a gate stack on the semiconductor substrate; epitaxially growing a silicon-comprising material on the semiconductor substrate, wherein the epitaxially-grown silicon-comprising material has a first surface; using the gate stack as mask, implanting impurity dopants into the epitaxially-grown silicon-comprising material disposed proximate to the gate stack; etching a trench into the epitaxially-grown silicon-comprising material such that the epitaxially-grown silicon-comprising material has a trench surface within the trench, wherein etching the trench into the epitaxially-grown silicon-comprising material creates two fins bounding the trench, and wherein each fin terminates at the first surface; forming a metal silicide layer on the first surface of the epitaxially-grown silicon-comprising material and on the trench surface; and fabricating a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface.