Patent ID: 7585756

Claim:
A method of manufacturing a semiconductor device, comprising: forming an insulation layer on a substrate; forming a lower first conductive layer on the insulation layer using a metal or a metal compound without nitrogen, the lower first conductive layer having a work function of about 4.0 eV to about 4.3 eV or about 4.7 eV to about 5.0 eV; forming an upper first conductive layer on the lower first conductive layer using a metal compound including nitrogen; forming a second conductive layer including nitrogen on the upper first conductive layer using a material having a resistance substantially lower than a resistance of the lower first conductive layer and the upper first conductive layer; patterning the insulation layer, the lower first conductive layer, the upper first conductive layer and the second conductive layer to form a gate structure including a gate insulation layer pattern and a gate electrode; forming source/drain regions by doping impurities at portions of the substrate adjacent to the gate structure; and activating the impurities in the source/drain regions by a thermal treatment process, wherein the upper first conductive layer including nitrogen prevents the lower first conductive layer from reacting with the second conductive layer including nitrogen and prevents an increase of a nitrogen concentration in the lower first conductive layer during the thermal treatment process to keep the work function of the lower first conductive layer substantially constant.