Patent ID: 7045386

Claim:
A method of manufacturing a semiconductor device, comprising: a first step of arranging first chip connection portions in standardized positions arranged in a layout so as to be common to and fit any of a plurality of predetermined types of second semiconductor chips in a chip bonding region on a surface of a first semiconductor chip where the second semiconductor chip is bonded to the first semiconductor chip; a second step of arranging second chip connection portions on the second semiconductor chip so as to fit the first chip connection portions arranged on the first semiconductor chip at least for one of the plurality of predetermined types of second semiconductor chips; and a third step of superposing and bonding the second semiconductor chip on the first semiconductor chips, wherein the first chip connection portions arranged on the first semiconductor chip are arranged along at least one pair of opposite sides of the chip bonding region, a distance between the first chip connection portions arranged along a first side of the at least one pair of opposite sides is shorter than a distance from the first chip connection portions arranged along the first side of the at least one pair of opposite sides to the first chip connection portions arranged along a second side of the at least one pair of opposite sides, and at least part of the first chip connection portions arranged on the first semiconductor chip are common to the plurality of predetermined types of second semiconductor chips so as to be used for input/output of signals having identical specifications.