Patent ID: 8832333

Claim:
A memory system comprising: a first memory device that includes a nonvolatile memory cell array and a read buffer inside the first memory device, the read buffer storing data read out from the memory cell array before outputting the data from the first memory device; a second memory device that includes a cache area, a descriptor storage area, and a read data buffer; a command queue configured to store at least one write command and at least one read command received from the host apparatus in order of arrival; a read queue configured to store the at least one read command received from the command queue; a write queue configured to store the at least one write command received from the command queue; a command sorting unit configured to dequeue commands excluding a later-arrived command whose access range overlaps with an access range of an earlier-arrived command from the command queue; a data transfer unit configured to perform a data preparing process of transferring first data to the read buffer from the memory cell array in the first memory device, the first data being specified by the read command stored in the read queue, perform a first data transfer of outputting the first data stored in the read buffer to the host apparatus, and perform a second data transfer of storing second data in the cache area, the second data being specified by the write command stored in the write queue, and perform the data preparing process and the second data transfer in parallel; and a flush control unit configured to save the second data, which is stored in the cache area, in the memory cell array in the first memory.