Patent ID: 7238995

Claim:
A semiconductor device, comprising: a support substrate; an insulating layer formed on the support substrate; a first semiconductor layer formed on the insulating layer; a first high breakdown voltage transistor formed in the first semiconductor layer, the first high breakdown voltage transistor having a source and a drain; a second semiconductor layer formed on the insulating layer; a second high breakdown voltage transistor formed in the second semiconductor layer, the second high breakdown voltage transistor having a source and a drain; a first isolation region formed through the first semiconductor layer and the second semiconductor layer, the first isolation region: being between the first and second high breakdown voltage transistors; contacting the source and the drain of each high breakdown voltage transistor; completely surrounding each of the first and second high breakdown voltage transistors individually; and having a depth that reaches the insulating layer; a third semiconductor layer formed on the insulating layer; a first low breakdown voltage transistor formed in the third semiconductor layer; a second low breakdown voltage transistor formed in the third semiconductor layer; and a second isolation region formed in the third semiconductor layer between the first low breakdown voltage transistor and the second first low breakdown voltage transistor, the second isolation region having a depth that does not reach the insulating layer.