Patent ID: 7368667

Claim:
A layered printed circuit board (PCB) for a high pin count area array packaged device, the board having a plurality of layers with routes for connecting the device onto the board, comprising: on a surface layer of said board, a surface ball grid array (BGA) of surface contacts connected to through-board vias, wherein two adjacent rows of through-board vias are distanced at one interconnect pitch P and two adjacent columns of through-board vias are distanced at two pitch 2P; and a column of external surface contacts connected to micro-vias that terminate on the first internal layer of said board for providing contact between said surface layer and the first internal layer; on the second and subsequent internal layers of the board, an internal array of through-board vias corresponding to said surface array; and a plurality of routing channels created between said through-board vias, whereby the routing capacity is widened to 2P on the second and all subsequent layers, while the interconnect pitch P on the surface of the board remains equal to that of the device.