Patent ID: 7687308

Claim:
A method of forming an integrated circuit, comprising the steps of: forming an SWT CNT transistor, by a process further comprising the steps of: forming a patterned seed layer comprising single crystal silicon on a top surface of an isolating layer; forming a first silicided source/drain regions at a first end of said silicon seed layer; forming a second silicided source/drain regions at a second end of said silicon seed layer; converting said silicon seed layer to a single crystal silicon carbide seed layer; forming an SWT CNT transistor body on a top surface of said silicon carbide seed layer by a process further comprising the steps of: forming a single layer of graphene on a top surface of said silicon carbide seed layer; and forming a CNT transistor body from said graphene layer by heating said graphene layer between 1100 C and 1400 C while exposing said graphene layer to carbon containing gases; forming a gate dielectric layer on an exterior surface of said SWT CNT transistor body; and forming a transistor gate on a surface of said gate dielectric layer over said SWT CNT transistor body.