Patent ID: 8856632

Claim:
A control device for controlling frequency synchronization, the control device comprising a processor configured to: form phase-error indicators on the basis of first values of reception moments of timing messages transmitted in accordance with a reference clock signal, the first values of the reception moments being expressed as time values based on a phase-controlled clock signal, form frequency-error indicators on the basis of second values of the reception moments of the timing messages, the second values of the reception moments being expressed as time values based on a frequency-controlled clock signal, control the phase-controlled clock signal with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal, control the frequency-controlled clock signal with the frequency-error indicators so as to achieve frequency-locking between the reference clock signal and the frequency-controlled clock signal, monitor a deviation between the frequency-controlled clock signal and the phase-controlled clock signal, detect, on the basis of a quantity measured from a system generating the frequency-controlled clock signal, a change of circumstances tending to cause frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal in response to a situation in which both the monitored deviation between the frequency- and phase-controlled clock signals and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.