Patent ID: 7305644

Claim:
A method for implementing improved timing driven placements of elements of a circuit design, comprising creating a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one, and providing an output list of paths with revised timing driven placement of circuits for a chip design, wherein the NSRF net weight factor is a value equaling (ZWLM slack value+negative slack value)/ZWLM slack value=(1+(negative slack value/ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing and wherein all wire parasitics are removed from consideration in the timing.