Patent ID: 7739575

Claim:
In a low-density parity-check decoder of the type having an arithmetic unit, the improvement comprising the arithmetic unit having a pipelined architecture of modules, including: a first module adapted to calculate a difference between absolute values of md_R and md_g_in, and pass results to a first Gallager module, the first Gallager module adapted to convert the results from a p 0 /p 1 representation to a 2*p 0 −1 representation, and pass the results to a second module, the second module adapted to selectively adjust the results based on sign values of md_g_in and md_R, and pass the results to a third module, the third module adapted to calculate a new md_g value by adding the results and loc_item_in, and pass the results to a fourth module, the fourth module adapted to separate a sign and an absolute value of the results, and pass the results to a second Gallager module, and the second Gallager module adapted to convert the results from the 2*p 0 −1 representation to the p 0 /p 1 representation, where, md_R=a check node value from a previous iteration of the pipelined arithmetic unit, md_g_in=an edge value from the previous iteration, p0=probability that a value is zero, p1=probability that a value is one, and loc_item_in=an intermediate edge value.