Patent ID: 8575976

Claim:
A frequency divider system comprising: a delay unit configured to receive a first input clock signal having a first input clock frequency and output a modified clock signal; and a frequency divider configured to receive the modified clock signal and output an output clock signal having an output clock frequency, the output clock frequency being an odd division of the first input clock frequency based on the modified clock signal, wherein the delay unit includes, a phase generator configured to receive the first clock signal and output at least one intermediate clock signal having a same or a different phase than the first clock signal, and a delay system configured to receive the at least one intermediate clock signal and output the modified clock signal based on the at least one intermediate clock signal, the delay system is configured to receive the output clock signal and the delay system includes, a first AND gate configured to receive the output clock signal and a first output of a first flip-flop and output a first flip-flop input signal based on the output clock signal and the first output of the first flip-flop, a second AND gate configured to receive an inverted output clock signal and a first output of a second flip-flop and output a second flip-flop input signal based on the inverted output clock signal and the first output of the second flip-flop, the first flip-flop configured to receive the first flip-flop input signal and a first signal of the at least one intermediate clock signal and output a first use signal based on the first flip-flop input signal and the first signal of the at least one intermediate clock signal, the second flip-flop configured to receive the second flip-flop input signal and a second signal of the at least one intermediate clock signal and output a second use signal based on the second flip-flop input signal and the second signal of the at least one intermediate clock signal, a third AND gate configured to receive the first use signal and a third signal of the at least one intermediate clock signal and output a first input to an OR gate based on the first use signal and the third signal of the at least one intermediate clock signal, a fourth AND gate configured to receive the second use signal and a fourth signal of the at least one intermediate clock signal and output a second input to the OR gate based on the second use signal and the fourth signal of the at least one intermediate clock signal, and the OR gate configured to output the modified clock signal based on the first and second inputs to the OR gate.