Patent ID: 7818699

Claim:
A method of dynamically specifying a circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) and adapted to out-source tasks to a function block selected to be implemented in the programmable IC, the method comprising: providing a single code set comprising an expanded netlist representative of a dynamic circuit configuration of the pipeline core that includes a selectable and variable number of delay stages each comprising a selectable number of parallel-connected delay elements, the code set including a delay length parameter variable and a bus width parameter variable; determining a signal delay and a bus width of the selected function block using a computer; generating a delay length constant and a bus width constant in response to the determining; setting the delay length parameter variable to the delay length constant; setting the bus width parameter variable to the bus width constant; and synthesizing the code set with the parameter variables set to the constants to generate a reduced netlist comprising a static circuit configuration for the implemented pipeline core that has the same signal delay and the same bus width as the selected function block, wherein the static circuit configuration comprises a fixed number of delay stages.