Patent ID: 8643115

Claim:
A method of forming a complementary metal oxide semiconductor comprising: providing a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET device region of a semiconductor structure and a plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET device region of the semiconductor substrate, wherein said providing comprises: forming a high k gate dielectric layer within the nFET device region of the semiconductor substrate and the pFET device region of the semiconductor substrate; forming a patterned trilayer metal stack including at least a pFET threshold voltage adjusting material layer on a portion of the high k gate dielectric within the pFET device region, while leaving another portion of the high k gate dielectric within the nFET device region exposed; forming an nFET threshold voltage adjusting material layer in both device regions; performing an anneal, wherein said anneal diffuses nFET threshold voltage adjusting species from the nFET threshold voltage adjusting material layer into the underlying portion of the high k gate dielectric layer in the nFET device region forming an nFET threshold voltage adjusted high k gate dielectric layer portion, while diffusing pFET threshold voltage species from the pFET threshold voltage adjusting material layer into the underlying portion of the high k gate dielectric in the pFET device region forming a pFET threshold voltage adjusted high k gate dielectric layer portion; removing the nFET threshold voltage adjusting material layer and the patterned trilayer metal stack exposing both the nFET threshold voltage adjusted high k gate dielectric layer portion and the pFET threshold voltage adjusted high k gate dielectric layer portion; and subjecting the exposed nFET threshold voltage adjusted high k gate dielectric portion and the pFET threshold voltage adjusted high k gate dielectric layer portion to plasma nitridation forming the plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion and the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion; forming a gate electrode layer atop both the plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion and the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion; and forming an nFET gate stack in the nFET device region and a pFET gate stack in the pFET device region, wherein the nFET gate stack includes, from bottom to top, the plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion and a first patterned portion of the gate electrode layer and the pFET gate stack includes, from bottom to top, the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion and a second patterned portion of the gate electrode layer.