Patent ID: 6861883

Claim:
A semiconductor integrated circuit comprising: a phase locked loop circuit configured to generate a first clock and a second clock; a first clock driver configured to distribute said first clock to a first clock domain; a second clock driver configured to distribute said second clock to a second clock domain; a first variable delay circuit provided on a first phase comparison loop including said first clock driver and a phase comparator, said first variable delay circuit having a delay determined by an output of said phase comparator; a second variable delay circuit provided on a second phase comparison loop including said second clock driver, said first variable delay circuit and said phase comparator, said second variable delay circuit having a delay determined by an output of said phase comparator; a selector circuit configured to switch between said first phase comparison loop and said second phase comparison loop; and a phase difference introducing circuit configured such that a predetermined phase difference to be provided between said first and second clock domains is reflected in said delay of said second variable delay circuit.