Patent ID: 8369158

Claim:
A method of erasing a string of memory cells, the method comprising: biasing first and second control lines to a first bias potential, wherein the first control line is coupled to a select gate coupled to a first end of the string of memory cells, the second control line is coupled to a select gate coupled to a second end of the string of memory cells, and each memory cell of the string of memory cells is coupled to a respective one of a plurality of access lines; biasing a first pair of the access lines to a second bias potential wherein each access line of the pair of access lines is coupled to a respective memory cell adjacent to a respective one of the select gates; biasing one or more of the remaining access lines to a third bias potential; applying a ramping bias potential to channel regions of the string of memory cells; and floating the first and second control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.