Patent ID: 8647947

Claim:
A method of producing a semiconductor device including a MOS transistor, comprising the steps of: providing a substrate on which a plurality of semiconductor pillars are erected; forming a bottom doped region in contact with a lower part of the respective semiconductor pillar; forming a first dielectric film to at least partially cover a sidewall of the respective semiconductor pillars; forming a conductive film on the first dielectric film; etching at least the conductive films down to a height substantially equal to a gate length; partially removing by etching the first dielectric films and the conductive films to form a gate electrode formed around the respective semiconductor pillars and form a gate line extending from a respective gate electrode; forming, on a top surface of at least one of the semiconductor pillars, a semiconductor layer having a top surface larger in area than the top surface of the at least one of the semiconductor pillars; and forming a top doped region at least part of which is formed in the semiconductor layer of the at least one of the semiconductor pillars, wherein the top doped region is of the same conductivity type as that of the bottom doped region.