Patent ID: 7301370

Claim:
A translator for translating differential input signals into a CMOS logic output, comprising: a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals; a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and a CMOS buffer configured to receive the set of increased swing signals and to provide the CMOS logic output, wherein the level shifting and buffering stage includes a first buffer receiving the differential input signals and a second buffer, said second buffer coupled with the first buffer, the first buffer being a first passively-loaded differential structure including: a first transistor receiving a first input signal of said differential input signals; a second transistor receiving a second input signal of said differential input signals, the first transistor and the second transistor connected in parallel at a node; and a third transistor connected between the node and ground; the first buffer providing a set of intermediate level shifted signals; the second buffer being a second passively-loaded differential structure configured to receive the set of intermediate level shifted signals and to provide the set of level shifted signals.