Patent ID: 7613981

Claim:
A system for reducing power consumption in a Low Density Parity Check (LDPC) decoder, wherein the LDPC decoder comprises a plurality of Bit Node Memory Units (BNMUs) corresponding to a plurality of bit nodes, a plurality of Check Node Memory Units (CNMUs) corresponding to a plurality of check nodes, and a plurality of Check Node and Bit Node Update Units (CNBNUs), each BNMU having at least one bit node from the plurality of bit nodes for storing a bit node message value corresponding to one of the check nodes, each CNMU having at least one check node from the plurality of check nodes for storing check node message values corresponding to one or more bit nodes, each CNBNU associated with a check node and being used for updating the check node and one or more bit nodes corresponding to the check node in one or more iterations of an exchange of messages between the check node and the one or more bit nodes, the system comprising: a sleep mode checking module that checks whether a check node is in a sleep mode, wherein the check node is in the sleep mode when an absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value; and a gating circuit, connected to the sleep mode checking module, that turns OFF a CNBNU associated with the check node when the check node is in the sleep mode, wherein turning OFF the CNBNU stops the exchange of messages between the check node and the corresponding one or more bit nodes.