Patent ID: 7295044

Claim:
A clock generation circuit, comprising: (a) a first differential comparator circuit, wherein the first differential comparator circuit receives as input (i) a first differential clock signal and (ii) a reference voltage, and generates a first output signal; (b) a second differential comparator circuit, wherein the second differential comparator circuit receives as input (i) the first differential clock signal and (ii) a second differential clock signal, and generates a second output signal, wherein in response to the first and the second differential clock signals switching, the second differential comparator circuit is capable of causing the second output signal to switch logic states; (c) a third differential comparator circuit, wherein the third differential comparator circuit receives as input (i) the reference voltage and (ii) the second differential clock signal, and generates a third output signal; (d) a bus change-over detecting circuit, wherein the bus change-over detecting circuit receives as input (i) the first output signal, and (ii) the third output signal, and generates an Enable signal; and (e) a latch circuit, wherein the latch circuit receives as input (i) the second output signal, and (ii) the Enable signal, wherein the latch circuit generates a digital clock signal, and wherein the latch circuit comprises a latch, and wherein in response to a high-high condition that both the first and second differential clock signals are higher than the reference voltage becoming true, the latch circuit is configured to hold the digital clock signal at a previous state which was generated by the latch circuit immediately before the high-high condition becomes true.