Patent ID: 7159103

Claim:
In a processor including a pre-fetch stage for fetching program instructions from a system memory device, and an execution stage for executing the fetched program instructions, a circuit for controlling an iterative execution of a group of said program instructions including a loop instruction and a target instruction, wherein each iteration begins with execution of the target instruction and ends with execution of the loop instruction, and wherein, upon executing the loop instruction at the end of each iteration, a loop counter value determines whether a new iteration is initiated and the target instruction is executed, or whether the iterative execution is terminated and a fall-through instruction is executed, the circuit comprising: a loop cache buffer for storing selected instructions of the group of program instructions, said selected instructions including at least the loop instruction and the target instruction; a predictor for predicting at the beginning of a first iteration whether a second iteration will be initiated at the end of the first iteration, or whether the iterative execution will be terminated at the end of the first iteration; a detector coupled to the pre-fetch stage for detecting that a first predetermined instruction of the group of said program instructions has been fetched by the pre-fetch stage; and a pre-fetch stage controller for controlling the pre-fetch stage to fetch a second predetermined instruction of the group of said program instructions when said second iteration is predicted, and for controlling the pre-fetch stage to fetch the fall-through instruction when termination of the iterative execution is predicted, said second predetermined instruction being the first of the instructions which are to be executed after the first predetermined instruction and which is not stored in the loop cache buffer.