Patent ID: 8611162

Claim:
A memory comprising: a plurality of write word lines; a plurality of complementary write word lines; a plurality of write bit line pairs; a plurality of read bit lines; a plurality of read word lines; a plurality of memory cells; a plurality of column decoded write enable lines; and a plurality of write control circuits, a write control circuit of the plurality of write control circuits comprising: a transmission gate having a first current terminal coupled to a column decoded write enable line of the plurality of column decoded write enable lines, a second current terminal coupled to a control electrode of an access transistor of a memory cell of the plurality of memory cells, a first control terminal coupled to a write word line of the plurality of write word lines, and a second control terminal coupled to a complementary write word line of the plurality of complementary write word lines, wherein a signal on the column decoded write enable line is passed through to the control electrode of the access transistor when a signal on the write word line is asserted; and a transistor having a first current electrode coupled to the second current terminal of the transmission gate, a second current electrode coupled to a power supply voltage terminal, and a control electrode coupled to the complementary write word line.