Patent ID: 8455180

Claim:
A method of forming an integrated circuit (IC) including a plurality of MOS transistors, comprising: using a gate mask to form a first active gate feature having a first line width W 1 over an active area and a neighboring dummy feature having a second line width =0.8W 1 to 1.3W 1 , said neighboring dummy feature having a first side adjacent to said first active gate feature; and a nearest gate level feature on a second side opposite to said first side; wherein said neighboring dummy feature defines a gate pitch based on a distance to said first active gate feature or said neighboring dummy feature maintains a gate pitch in a gate array including said first active gate feature, and wherein a spacing between said neighboring dummy feature and said nearest gate level feature provides one of: (i) maintaining said gate pitch, and (ii) being at a sub-resolution assist feature (SRAF) enabling distance that is 2 times said gate pitch and said gate mask includes a SRAF over said SRAF enabling distance; and wherein said first active gate feature is positioned at an end of said active area and said neighboring dummy feature is in a field region.