Patent ID: 7669011

Claim:
A processor comprising: a processor core; interface logic coupled to the core and configured to control communication with other processors; an address translation storage structure coupled to the processor core and having a plurality of entries, each corresponding to a memory page, wherein each entry includes a physical address of a memory page, and a private page indication that indicates whether any other processor has an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page; a memory controller coupled between the processor core and a local system memory and configured to inhibit issuance of a probe message to each other processor in response to receiving a write memory request to a given memory page, wherein the write request includes a private page attribute that is associated with the private page indication, and that indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page; and wherein in response to receiving a write memory request to a particular memory page that includes an attribute that indicates the write memory request is a first write memory request subsequent to a first access for the particular memory page, the memory controller is further configured to issue a specific probe message to each other processor, wherein the specific probe message causes each other processor core to search each entry of the respective address translation storage structure and each entry of the respective cache structure for any address that maps to the particular memory page.