Patent ID: 7657854

Claim:
A method for designing a test circuit in a System on Chip (SOC) design using a system for designing a test circuit, wherein the system includes a constraint identifier, an SOC partitioning module, and a scan chain construction module, and wherein the SOC design includes a plurality of logic blocks, the method comprising: identifying test design constraints for the test circuit with the constraint identifier, wherein the test design constraints include a number of scan chains and an average length of a scan chain; logically partitioning the SOC design into at least a first set of logic blocks and a second set of logic blocks with the SOC partitioning module, wherein the first set of logic blocks includes design logic specific to basic features of the SOC design and the second set of logic blocks includes application specific logic of the SOC design; inserting a first set of scan chains in the first set of logic blocks and a second set of scan chains in the second set of logic blocks with the scan chain construction module, based on the test design constraints; inserting a plurality of bypass circuits in a path of at least one scan chain of the second set of scan chains with the scan chain construction module, wherein each of the bypass circuits is capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC design; and further comprising partitioning the second set of logic blocks into at least one subset of logic blocks based on a target application of each logic block of the second set of logic blocks prior to inserting the second set of scan chains.