Patent ID: 8487794

Claim:
A method of linearity calibration for a successive approximation register analog-to-digital converter (SAR ADC), the SAR ADC comprising a digital-to-analog converter (DAC), the DAC comprising a reference element E r and N composed elements E 0 , E 1 , . . . , E N−1 , each composed element E i in a part of the composed elements comprises a main constructed element E i 0 and w i sub constructed elements E i 1 , E i 2 , . . . , E i w i , wherein N is a positive integer greater than 1, w i is a positive integer greater than or equal to 1, i is a positive integer greater than or equal to 0 and less than N, the method comprising: selecting a less significant bit (LSB) y for calibration in order to calibrate the composed elements E y , E y+1 , . . . , E N−1 , wherein y is a positive integer greater than or equal to 0 and less than N; and repeating the following steps starting from i equals to y, increasing i successively by 1, until all of the composed elements for calibration have been calibrated: identifying whether a missing decision level is caused by the composed element and selecting a part of the sub constructed elements E i 1 , E i 2 , . . . , E i w i and making them non-functional when the missing decision level is caused by the composed element E i .