Patent ID: 7085113

Claim:
An ESD protection power clamp for suppressing ESD events comprising: an FET having drain and source connections connected across power supply terminals of an integrated circuit for clamping the voltage at said terminals to a power supply voltage during an ESD event; an RC timing circuit connected between the power supply terminals which provide a voltage proportional to an ESD voltage for triggering said FET out of conduction following an ESD event; an inverter circuit having a plurality stages connected between said power supply terminals, said inverter circuit having an input connection connected to receive said RC timing circuit voltage, and having an output connected to said FET gate connection; and a feedback FET having a drain and source connected in series with one stage of said inverter circuit and said power supply terminals, and having a gate connection connected to said FET gate connection, whereby during an ESD event, said feedback FET provides dynamic feedback preventing said gate connection from latching said FET for clamping the voltage on said terminals into a conducting mode when power supply potential is applied across said terminals.