Patent ID: 6940336

Claim:
Voltage regulator with an output transistor (MP 1 ) of a first PMOS FET, comprising: said first PMOS FET, whereby the input voltage (Vdd) of the voltage regulator is applied to the source of the output transistor (MP 1 ) and where the drain of the output transistor (MP 1 ) serves as the output of the voltage regulator, a regulation circuit ( 1 ) that is configured so as to output an error signal representing the deviation of the actual output voltage (Vout) of the voltage regulator from the target output voltage of the voltage regulator at its output, the output of the regulating circuit ( 1 ) being connected to the gate of the output transistor (MP 1 ), which is controlled by the error signal in such a way that any deviations between the output voltage (Vout) and the target output voltage are minimized, as well as a switch-on protection circuit, a second PMOS FET (MP 2 ), the source of the second PMOS FET (MP 2 ) being connected to the input voltage (Vdd) of the voltage regulator, the drain of the second PMOS FET (MP 2 ) by way of a pulldown resistor R 3 ) to a reference potential (Vss), and the gate of the second PMOS FET (MP 2 ) to the reference potential (Vss), and a third PMOS FET (MP 3 ), where the source of the third PMOS FET (MP 3 ) is connected to the input voltage (Vdd) of the voltage regulator, the drain of the third PMOS FET (MP 3 ) is connected to the gate of the output transistor (MP 1 ), and the gate of the third PMOS FET (MP 3 ) is connected to the drain of the second PMOS FET (MP 2 ).