Patent ID: 8691685

Claim:
A process for inhibiting intermetallic inclusions in the fabrication of integrated circuit interconnection structures, comprising providing stacked layers on said integrated circuit comprising as a first layer an electroless Ni(P) coating, and as a second layer, a metal selected from Sn or Cu, and as a third layer, a Sn rich Pb-free solder and subjecting said stacked layers to a fusion temperature excursion to fuse said stacked layers together and wherein said second layer ranges in thickness from 0.1 to 5.0 microns and said third layer is a material from the group Sn, Sn-3.5% Ag, Sn-0.7% Cu, Sn-3% Bi, Sn-3.5%-0.7% Cu, Sn-3.5% Ag-3% Bi, Sn-8%-Zn-3% Bi, Sn-3.5% Ag-0.7% Cu-0.5% Sb, Sn-2.5% Ag-0.5% Cu.