Patent ID: 8436410

Claim:
A semiconductor device comprising: a plurality of gate structures on a surface of a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate; liners on opposing sidewalls of first and second adjacent ones of the gate structures; spacers on the opposing sidewalls of the first and second gate structures; and an insulating layer on the spacers and partially filling between the spacers, wherein the spacers are spaced apart from the surface of the substrate, wherein a gap is defined between the liners on the opposing sidewalls of the first and second gate structures and between the surface of the substrate and the spacers, and is further defined by the insulating layer, and wherein a first width of the gap between the liners is adjacent the surface of the substrate and is less than a second width of the gap between the liners that is more distant from the surface of the substrate.