Patent ID: 7482285

Claim:
A method of producing a MOS-gated semiconductor device, comprising: providing a dual epitaxial junction-receiving layer, including: providing a first epitaxially grown layer of a first conductivity type and a first resistivity over a substrate; and providing a second epitaxially grown layer of the first conductivity type and a second resistivity over said first epitaxially grown layer, said second resistivity being different from said first resistivity; forming body regions of a second conductivity type in said second epitaxially grown layer, each of the body regions having a depth that is less than the thickness of said second epitaxially grown layer, said body regions forming PN junctions with said second epitaxially grown layer to obtain a device breakdown voltage for said device; forming source regions of said first conductivity type in said body regions; and forming a gate structure over said second epitaxially grown layer, wherein selections of a concentration of dopants and a thickness of each said first and said second epitaxially grown layers so as to obtain a device breakdown voltage and a total thickness of the first and second expitaxiallv grown layers involve a comparison in electric field distribution with a power MOSFET having a same structure as that of said device, except that the power MOSFET only has a single epitaxial junction-receiving layer therein, said single epitaxial junction-receiving layer being of said first conductivity type and having a same concentration of dopants as that in said first epitaxially grown layer and receiving body regions same as the body regions in said device, and, wherein said device breakdown voltage is the same as a device breakdown voltage of the power MOSFET and wherein said total thickness is less than the thickness of said single epitaxial junction-receiving layer.