Patent ID: 7337251

Claim:
An information processing device comprising: first and second bus master circuits; a bus to which said first and second bus master circuits are connected; and a first arbiter for arbitrating access rights of said first and second bus master circuits to said bus, wherein said first arbiter has a storage unit for retaining information representing priorities of said access rights of said first and second bus master circuits and a control unit for arbitrating the access rights of said first and second bus master circuits based on the information of said storage unit, and said storage unit has a first storage unit portion in which information representing the priorities of said first and second bus master circuits is set at a time of initial setting of said information processing device, and a second storage unit portion in which information representing the priorities is changed in accordance with an operation of said information processing device, when a priority of said first bus master circuit is higher than a priority of said second bus master circuit and there is no access request from said first bus master circuit but there is an access request from said second bus master circuit, said control unit permits bus access of said second bus master circuit and said storage unit lowers the priority of said second bus master circuit without changing the priority of said first bus master circuit, and when a predetermined period elapses after said information processing device is in an operational state, said second storage unit portion changes said information representing the priorities in accordance with the information stored in said first storage unit portion.