Patent ID: 6909332

Claim:
A high speed bit stream data conversion circuit comprising: a data conversion circuit that receives at least one first bit stream at a first bit rate and a corresponding first bit stream data clock and that produces at least one second bit stream at a second bit rate, wherein the number and bit rate of the at least one first bit stream and the at least one second bit stream differ, wherein the data conversion circuit includes a plurality of drivers used to drive signals based upon the at least one first bit stream and/or the first bit stream data clock; and a clock circuit that produces a Reference Clock Signal based upon the first bit stream data clock that is used to latch the at least one first bit stream, wherein the clock circuit comprises: a phase locked loop (PLL) having a phase detector that receives the first bit stream data clock and a loop output, a charge pump, a loop filter, a Voltage Controlled Oscillator (VCO), and a divider that produces the loop output; wherein the VCO is tuned at an operating frequency corresponding to at least one tuning setting; and wherein at least some of the plurality of drivers is tuned based upon the at least one tuning setting.