Patent ID: 7233637

Claim:
A circuit comprising: a first delay device including a control input and at least one output; a second delay device including a control input and at least one output; a control signal line coupled to, and configured to provide a control signal to, the control input of the first delay device and the second delay device, the control signal being based on the at least one output of the first delay device and on a clock; a sampling signal line coupled to, and configured to provide a sampling signal based on the at least one output of the first delay device; and a sampling device coupled to the at least one output of the second delay device and coupled to the sampling signal line, the sampling device configured to sample the at least one output of the second delay device based on a value of the sampling signal, wherein the second delay device includes multiple outputs, and the sampling device is coupled to the multiple outputs, wherein the first delay device comprises a first delay line, wherein the first delay line includes cascaded inverters, and wherein the cascaded inverters are arranged in a feedback configuration and at least two consecutive inverters are configured with common initial conditions so as to produce a distinctive pattern during operation of the first delay line.