Patent ID: 8222121

Claim:
A method for stacking integrated circuit substrates comprising: providing an integrated circuit substrate having top and bottom surfaces, said integrated circuit substrate being divided vertically into a plurality of layers including an integrated circuit layer extending into said wafer by a first distance from said top surface of said wafer and having integrated circuit elements constructed therein and a buffer layer adjacent to said bottom surface, said buffer layer being devoid of integrated circuit elements, said buffer layer being separated from said top surface of said wafer by a distance greater than or equal to said first distance; constructing an alignment fiducial structure comprising a plurality of vias extending from said top surface of said wafer into said wafer by a second distance greater than said first distance, said vias being arranged in a pattern that comprises a fiducial mark; bonding said top surface of said integrated circuit substrate to a base substrate; thinning said integrated circuit substrate by removing material from said bottom surface of said integrated circuit substrate to create a thinned bottom surface thereby exposing said plurality of vias; and aligning a lithographic mask for depositing a patterned layer of material on said thinned integrated circuit substrate, said lithographic mask being aligned by reference to said alignment fiducial mark.