Patent ID: 7544559

Claim:
A method of forming a semiconductor construction, comprising: providing a semiconductor substrate having a PMOS region and an NMOS region; forming an NMOS gate stack over the NMOS region; the forming of the NMOS gate stack comprising: forming gate dielectric, forming first metal nitride directly against the gate dielectric, forming silicon-containing material directly against the first metal nitride, and forming second metal nitride directly against the silicon-containing material; the silicon-containing material being less than or equal to about 30 angstroms thick; and forming a PMOS gate stack over the PMOS region; the forming of the PMOS gate stack comprising: forming the gate dielectric, forming the first metal nitride directly against the gate dielectric, and forming the second metal nitride directly against the first metal nitride; wherein the forming of the gate dielectric, first metal nitride, and second metal nitride of the PMOS gate stack is simultaneous with the forming of the gate dielectric, first metal nitride, and second metal nitride of the NMOS gate stack.