Patent ID: 7120080

Claim:
A dual port semiconductor memory cell, comprising: a first CMOS inverter including a first NMOS transistor, a first PMOS transistor, an input port, and an output port; a second CMOS inverter including a second NMOS transistor, a second PMOS transistor, an input port coupled to the output port of the first CMOS inverter and constitutes a first memory node together with the output port of the first CMOS inverter, and an output port coupled to the input port of the first CMOS inverter and constitutes a second memory node together with the input port of the first CMOS inverter; a third NMOS transistor having a gate coupled to a wordline, a drain coupled to a bitline, and a source coupled to the first memory node; a fourth NMOS transistor having a gate coupled to the wordline, a drain coupled to a complementary bitline, and a source coupled to the second memory node; and a third PMOS transistor having a gate coupled to a scan address line, a source coupled to the second memory node, and a drain coupled to a scan data-out line; where the memory cell is divided into first and second n-wells where P+ active regions are formed and first and second p-wells where N+ active regions are formed.