Patent ID: 7064987

Claim:
A memory address generator with scheduled write and read address generating capability, said memory address generator being adapted to generate write addresses to be used in writing data units of an input data block into a memory device in a non-raster scan arrangement according to a predetermined write sequence, and being adapted to generate read addresses to be used in reading the data units of the input data block from the memory device in a raster scan arrangement according to a predetermined read sequence so as to obtain a rearranged output data block, said memory address generator comprising: a write address generator operable so as to generate the write addresses to be used in the writing of the data units of the input data block into the memory device in the non-raster scan arrangement; a read address generator operable so as to generate the read addresses to be used in the reading of the data units of the input data block from the memory device in the raster scan arrangement; and a scan pattern analyzer coupled to said write and read address generators, said scan pattern analyzer comparing the write and read sequences, and enabling said read address generator after enabling said write address generator such that a first optimum number of the write addresses for the writing of the input data block has been generated prior to generation of the read addresses for the reading of the input data block in order to ensure that the reading of each of the data units of the input data block from the memory device lags the writing of each of the data units of the input data block into the memory device.