Patent ID: 7449365

Claim:
A method for forming a wafer level chip scale flip chip package comprising: determining operational dielectric isolation requirements between a plurality of circuits of an integrated circuit formed in a semi conductive substrate and package signal connections of the wafer level chip scale flip chip package; based upon the operational dielectric isolation requirements of the integrated circuit, selecting a thickness of at least one dielectric layer isolating a top metal layer of the integrated circuit from the package signal connections of the wafer level chip scale flip chip package; for each of the plurality of circuits of the integrated circuit formed in the semi conductive substrate, determining operational parasitic coupling limitations between the circuit of the integrated circuit and the package signal connections of the wafer level chip scale flip chip package; and based upon operational parasitic coupling limitations between the circuits of the integrated circuit and the package signal connections of the wafer level chip scale flip chip package, for each of the plurality of circuits of the integrated circuit, selecting minimum pitches of respective adjacently located package signal connections of the wafer chip scale flip chip package.