Patent ID: 7449753

Claim:
A semiconductor structure comprising: a substrate comprising a core circuit region and a static random access memory (SRAM) region; a first PMOS device in the SRAM region, wherein the first PMOS device comprises: a first gate dielectric over the substrate; a first gate electrode on the first gate dielectric; a first spacer on a sidewall of the first gate electrode; a first lightly doped drain/source (LDD) region substantially aligned with an edge of the first gate electrode; a first silicon germanium(SiGe) stressor in the substrate and adjacent the first gate electrode; a first deep source/drain region in the substrate and spaced apart from the edge of the first gate electrode; and a current-tuning region overlapping at least a portion of the SiGe stressor; and a second PMOS device in the core circuit region, wherein the second PMOS device comprises: a second gate dielectric over the substrate; a second gate electrode on the second gate dielectric; a second spacer on a sidewall of the second gate dielectric and the second gate electrode; a second lightly doped source/drain (LDD) region substantially aligned with an edge of the second gate electrode; a second SiGe stressor in the substrate and adjacent the second gate electrode; a second deep source/drain region in the substrate and spaced apart from the edge of the second gate electrode; and wherein the second PMOS device is free of current-tuning regions.