Patent ID: 7543191

Claim:
A method for isolating a bus failure, applied to a system comprising a monitoring unit and multiple boards connected to a Compact PCI bus, wherein the monitoring unit comprises multiple retry counters, each of the multiple boards corresponds to one retry counter in the monitoring unit, and each retry counter corresponds to an address of a board, comprising: monitoring, by the monitoring unit, the operation between the multiple boards; when one of the multiple boards accesses another target board of the multiple boards, acquiring, by the monitoring unit, an address of the target board from the Compact PCI bus; adding, by the monitoring unit, one counting unit to the retry counter corresponding to the address of the target board when each of the retry responses for the access to the target board is generated via the Compact PCI bus; and sending, by the monitoring unit, a reset signal to the target board in response to that the times of the retry responses exceed a retry times threshold.