Patent ID: 7639059

Claim:
A reference voltage buffer circuit ( 20 ) comprising: a first transistor (M 1 ) of a first type having a first current handling terminal coupled to a first output node ( 25 ) providing a positive reference voltage (Vrp), a second current handling terminal ( 22 ) coupled to a positive power supply voltage (Vdd), and a control terminal receiving a first control voltage (Vg 1 ); a second transistor (M 2 ) of a second type having a first current handling terminal ( 24 ) coupled to a second output node ( 27 ) providing a negative reference voltage (Vrn), a second current handling terminal coupled to a negative power supply voltage (Vss), and a control terminal receiving a second control voltage (Vg 2 ); first and second resistors (R 1 , R 2 ) connected in series between the first output node and the second output node; a first boost circuit for generating a positive boosted voltage (Vdd 2 ) greater than the positive power supply voltage; a second boost circuit for generating a negative boosted voltage (Vss 2 ) less than the negative power supply voltage; third and fourth transistors (M 3 , M 4 ) of the second type connected in series between the positive boosted voltage and the negative power supply voltage, a common node ( 38 ) between the third and fourth transistors being coupled to the control terminal of the first transistor; a first error amplifier having a non-inverting input terminal coupled to receive a first reference voltage (Vrp 0 ), an inverting input terminal coupled to the first output node and an output terminal coupled to drive the control terminal of the fourth transistor, the first error amplifier generating a control voltage for the fourth transistor indicative of the difference between the positive reference voltage and the first reference voltage; fifth and sixth transistors (M 5 , M 6 ) of the first type connected in series between the positive power supply voltage and the negative boosted voltage, a common node ( 39 ) between the fifth and sixth transistors being coupled to the control terminal of the second transistor; and a second error amplifier having a non-inverting input terminal coupled to receive a second reference voltage (Vrn 0 ), an inverting input terminal coupled to the second output node and an output terminal coupled to drive the control terminal of the sixth transistor, the second error amplifier generating a control voltage for the sixth transistor indicative of the difference between the negative reference voltage and the second reference voltage, wherein the fourth and sixth transistors generate the first and second control voltages respectively for the first and second transistors and the third transistor and the fifth transistors are biased to supply current to the first current handling terminals of the fourth and sixth transistors, respectively, to maintain the first and second control voltages.