Patent ID: 8743604

Claim:
A memory system, comprising: a nonvolatile memory array having a plurality of rows of nonvolatile multi-bit memory cells therein; and a control circuit electrically coupled to said nonvolatile memory array, said control circuit configured to program at least four pages of data into a first row of nonvolatile multi-bit memory cells in said nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row and further configured to read the at least four pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages, wherein said control circuit is configured to program the at least four pages of data into the first row by: converting at least four pages of write data into at least four pages of converted data having different binary values relative to the at least four pages of write data; and adjusting threshold voltages of the nonvolatile multi-bit memory cells in the first row to correspond to the at least four pages of converted data, wherein the second sequence of read voltages includes a sequence of at least four read voltages which have different levels.