Patent ID: 7529128

Claim:
An integrated circuit device, comprising: a processor in the integrated circuit device; a random access memory in the integrated circuit device; a semiconductor substrate in the integrated circuit device; a first memory array on the substrate comprising charge storage, non-volatile memory cells, configured to store data for a first pattern of data usage in response to a first operation algorithm using a first charge movement process type with at least one of reading, programming, and erasing the first memory array; a second memory array on the substrate comprising charge storage, non-volatile memory cells, configured to store data for a second pattern of data usage in response to a second operation algorithm using a second charge movement process type with at least one of reading, programming, and erasing the second memory array, wherein the first and second charge movement process types are different and, wherein the charge storage, non-volatile memory cells in the first memory array have a first cell structure, and wherein the charge storage, non-volatile memory cells in the second memory array have a second cell structure which is substantially the same as the first cell structure; controller circuitry coupled to the processor, the random access memory, and the first and second memory arrays, including logic to read, program and erase data in the first memory array and in the second memory array according to the first and second operation algorithms.