Patent ID: 7072202

Claim:
A semiconductor device formed on a semiconductor chip comprising: a first memory bank including a plurality of first memory arrays, each of which has a plurality of first memory cells provided at predetermined intersections of a plurality of first word lines and a plurality of first data lines, and a plurality of first sense amplifiers coupled to the plurality of first data lines; a second memory bank including a plurality of second memory arrays, each of which has a plurality of second memory cells provided at predetermined intersections of a plurality of second word lines and a plurality of second data lines, and a plurality of second sense amplifiers coupled to the plurality of second data lines; a plurality of bonding pads arranged between the first memory bank and the second memory bank; first and second voltage generators receiving a first voltage and outputting a second voltage smaller than the first voltage; a plurality of first lines formed in a first layer and extending in a first direction; a plurality of second lines formed in a second layer and extending in a second direction across the second direction; a plurality of third lines formed in the first layer and extending in the first direction; and a plurality of fourth lines formed in the second layer and extending in the second direction, wherein the plurality of first and second lines are coupled to each other at intersections of the plurality of first and second lines, wherein the plurality of third and fourth lines are coupled to each other at intersections of the plurality of third and fourth lines, wherein the plurality of first sense amplifiers are supplied with the second voltage via the plurality of first and second lines, wherein the plurality of second sense amplifiers are supplied with the second voltage via the plurality of third and fourth lines, wherein the first voltage generator is arranged between an edge of the semiconductor chip and the first memory bank, and wherein the second voltage generator is arranged between the edge of the semiconductor chip and the second memory bank.