Patent ID: 7684267

Claim:
An apparatus for redundancy of a memory array comprising: a primary memory array comprising a plurality of memory cells wherein one or more memory cells of the primary array are defective; a redundant array comprising: a CAM array comprising a plurality of memory cells, wherein the addresses of the one or more defective memory locations within the primary array are stored, wherein the CAM array is addressed by the addresses of the one or more defective memory locations within the primary memory array, and wherein the CAM array provides a match identification to a translation array and a resource identification to a redundant data array, the translation array, wherein an offset that configures an input/output multiplexer is stored, wherein the translation array provides the offset to the input/output multiplexer, the redundant data array comprising a plurality of memory cells, wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array; and the input/output multiplexer wherein the input/output multiplexer selectively presents data comprised of data from or to the primary memory array or data from or to the primary memory array and the redundant array.