Patent ID: 7821072

Claim:
A semiconductor device comprising: a first MIS transistor of N-channel type including a first gate electrode which is formed above a first active region made of a semiconductor layer and first source/drain regions which are formed in parts of the first active region located at sides of the first gate electrode; a second MIS transistor of P-channel type including a second gate electrode which is formed above a second active region made of the semiconductor layer and second source/drain regions which are formed in parts of the second active region located at sides of the second gate electrode; a layered film which covers the first gate electrode, the first active region, the second gate electrode and the second active region and includes a first insulating film which applies tensile stress and a second insulating film which applies compressive stress; an interlayer insulating film which is formed on the layered film; a third MIS transistor of N-channel type including a third gate electrode which is formed above a third active region made of the semiconductor layer and third source/drain regions which are formed in parts of the third active region located at sides of the third gate electrode; and a third insulating film which covers the third gate electrode and the third active region and applies tensile stress, wherein both of the first insulating film and the second insulating film of the layered film are formed over an upper surface of the first gate electrode and an upper surface of the second gate electrode, and the second insulating film is not formed above the third active region.