Patent ID: 7002254

Claim:
An integrated circuit package comprising: a package substrate having a first surface including a first array of interconnection sites, and a second array of interconnection sites; a first integrated circuit die having a first surface including an array of interconnection sites electrically connected to the second array of interconnection sites of the package substrate; and a second integrated circuit die having a first surface including an array of interconnection sites electrically connected to the first array of interconnection sites of the package substrate, wherein the first integrated circuit die is positioned amid the package substrate and the second integrated circuit die, wherein the first surface of the package substrate includes an auxiliary array of interconnection sites that is different than the first and second arrays of interconnection sites of the package substrate, and wherein gaps between the second integrated circuit die and the package substrate at the first array of interconnection sites of the package substrate and the array of interconnection sites of the second integrated circuit die are underfilled with epoxy.