Patent ID: 7576001

Claim:
A method for manufacturing a semiconductor device having a multilayer wiring structure, comprising the steps of: forming an etch stop layer on a layer having formed thereon a lower copper wiring; forming an interlayer insulating film on the etch stop layer; etching the interlayer insulating film to form an opening that reaches the etch stop layer; etching the interlayer insulating film to form a wiring groove that communicates with the opening; etching the etch stop layer on the bottom of the opening to form a via hole as well as forming a deposited film of etching products on surfaces of the via hole and the wiring groove; and forming a barrier metal in the via hole and the wiring groove by a sputtering method; wherein in the step of forming the barrier metal by the sputtering method, the deposited film of the etching products on the bottom of the via hole is preferentially sputtered and removed, and the barrier metal is formed in a state where the deposited film of the etching products on the bottom of the via hole is removed, wherein in the step of etching the etch stop layer on the bottom of the opening to form the via hole that communicates with the lower copper wiring as well as forming the deposited film of the etching products on the surfaces of the via hole and the wiring groove, the etch stop layer on the bottom of the opening is etched to form the via hole as well as the deposited film of the etching products is formed on the surfaces of the via hole and the wiring groove such that the surface roughness on the bottom of the wiring groove is 1 nm or less.