Patent ID: 8223046

Claim:
A circuit comprising: (a) an input node having a variable analog input voltage; (b) a first analog to digital converter (ADC); (c) a first sample-and-hold (SH) circuit comprising a first capacitor, coupled to the first ADC, and a first switch that switches the first SH circuit, based on a control signal, between a sampling state, a holding state and a reset state by coupling the first ADC and the first capacitor to the input node, the open circuit or a ground node, respectively; (d) a second ADC; (e) a digital to analog converter (DAC); (f) a second SH circuit coupled to the second ADC, the second SH circuit comprising a second capacitor, coupled to the second ADC, and a second switch, controlled by the control signal and that switches the second SH circuit between a calibration state, a holding state and a reset state by coupling the second ADC and the second capacitor to the DAC, the open circuit or the ground node, respectively; and (g) a digital signal processor (DSP) coupled to the first and second ADCs and the DAC, the DSP comprising: (i) a control logic that provides at least one digital calibration value to the DAC, (ii) a memory that stores at least one error associated with the second ADC, and (iii) a correction module that corrects an output of the first ADC based on the at least one stored error.