Patent ID: 8901724

Claim:
A semiconductor package comprising: a first package comprising: a first dielectric layer having a top surface, and a cavity extended through the first dielectric layer; a layer of adhesive formed in the cavity of the first dielectric layer, the layer of adhesive having an upper surface and a lower surface, wherein the upper surface is substantially coplanar to the top surface of the first dielectric layer; a first die formed in the cavity, the first die having a front side, sidewalls, and a back side, wherein the front side includes a plurality of die pads, and wherein the back side is adhered to the lower surface of the layer of adhesive; a second dielectric layer formed over a bottom surface of the first dielectric layer, extending into the cavity adjacent the die sidewalls, and over the front side of the first die; a plurality of die interconnects electrically coupled to the plurality of die pads on the front side of the first die; a plurality of package pads formed in the first dielectric layer, wherein the plurality of package pads each comprises an exposed surface that is substantially coplanar to the top surface of the first dielectric layer; an additional die attached to the upper surface of the adhesive layer, wherein the additional die is in electrical contact with at least one of the package pads; and a second package stacked over the additional die and attached to at least one of the package pads with a solder bump extending between the package and the at least one package pad.