Patent ID: 7865706

Claim:
A method of generating instructions comprising a plurality of instructions of non-interrupt processing and an instruction of interrupt processing, to be executed by a CPU which includes a plurality of registers, the method comprising: a first step for judging whether or not each of the plurality of registers is valid for each of the plurality instructions of non-interrupt processing; a second step for judging whether or not a value of each of the plurality of registers is changed by the instruction of interrupt processing; and a third step for inserting an interrupt permitting instruction, which permits the CPU to carry out the instruction of interrupt processing, just before a selected instruction included in the plurality of instructions of non-interrupt processing, wherein: in the third step, the interrupt permitting instruction is inserted when it is judged that each of the plurality of registers is valid in the first step and the value of each of the plurality of registers is not changed in the second step, and the third step is performed so that a number of specific registers, which are valid for one of the plurality of instructions of non-interrupt processing and each of whose value is changed by the instruction of interrupt processing, becomes minimum for the selected instruction among the plurality of instructions of non-interrupt processing.