Patent ID: 7192833

Claim:
A method of manufacturing a flash memory device comprises: forming a tunnel dielectric layer on a semiconductor substrate through which charges tunnel; forming a floating gate layer on said tunnel dielectric layer that traps tunneled charges; forming an interlayer dielectric layer that covers said floating gate layer; forming a mold layer comprising at least two layers on said interlayer dielectric layer; patterning sequentially said mold layer, said interlayer dielectric layer and, said floating gate layer, thereby forming a mold layer first pattern, an interlayer dielectric layer pattern and a floating gate layer pattern, which are aligned with one another; etching laterally exposed portions of side surfaces of the mold layer first pattern being adjacent to said interlayer dielectric layer pattern, thereby forming a mold layer second pattern having grooves in side surfaces thereof; forming a gate dielectric layer on side surfaces of said floating gate layer pattern and exposed portions of said semiconductor substrate adjacent to said floating gate layer pattern; forming a control gate on said gate dielectric layer by filling said grooves in the side surfaces of said mold layer second pattern such that a width filling said groove is set as a width of a portion overlapping with said floating gate layer pattern; selectively removing said mold layer second pattern; forming spacers on sidewalls of said control gate exposed by said removing of said mold layer second pattern; and forming a floating gate by selectively etching exposed portions of said interlayer dielectric layer and said floating gate layer pattern, using said spacers as an etch mask.