Patent ID: 8078838

Claim:
A multiprocessor system comprising: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including a memory cell array having at least one shared memory area, a first port coupled to the at least one shared memory area, a second port coupled to the at least one shared memory area, a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, and the wake-up signal generator being coupled to the first processor and the second processor, and an internal register coupled to the wake-up signal generator, the internal register being disposed outside the memory cell array, the internal register being accessed responsive to predetermined addresses of the at least one shared memory area to provide a data interface function and to store messages provided by the first processor and the second processor, the wake-up signal generator configured to generate and send wake-up signals to the first and second processors responsive to the stored messages in the internal register.