Patent ID: 7660149

Claim:
A dual port static random access memory (SRAM) cell comprising: at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and output terminals; at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively; a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line, wherein the write port further comprises a first switching device and a second switching device connected in series between the input terminal and the write-bit-line; and a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line, wherein the read port further comprises a first MOS transistor and a second MOS transistor connected in series between the read-bit-line and a supply voltage, wherein a gate of the first MOS transistor is connected to the read-word-line and a gate of the second MOS transistor is directly connected to the input or output terminal, and wherein the dual port SRAM cell is made of no more than seven transistors to reduce its cell size.