Patent ID: 7843274

Claim:
A phase lock loop (PLL) apparatus, comprising: a phase detecting module, when the phase detecting module receives an input data signal and a clock signal, the phase detecting module detecting the phase difference between input data signal and the clock signal to generate a first index signal; a logic processing module, coupled to the phase detecting module, for receiving the first index signal and processing a high-frequency dithering to the first index signal to generate a second index signal; a charge pump and loop filter (CPLF), coupled to the logic processing module, for receiving the first index signal and the second index signal, adjusting a control voltage according to the first index signal and the second index signal, and then outputting the control voltage; and a voltage control oscillator, coupled to the CPLF, for adjusting frequency or phase of the clock signal according to the control voltage, and then outputting the adjusted clock signal to the phase detecting module; wherein the frequency of outputting the second index signal is equal to or larger than the frequency of outputting the first index signal.