Patent ID: 6908821

Claim:
A method of fabricating an input capacitance adjustment part in a semiconductor device, the method comprising the steps of: providing a first conductivity type substrate in which first to third device isolation layers are formed; forming a second conductivity type well having a first conductivity type impurity region inside between the first and second device isolation layers; forming an oxide layer and a polysilicon layer on an entire structure successively; patterning the oxide and polysilicon layers to form a first area on the first device isolation layer and a gate on an active area between the second and third device isolation layers; forming source/drain regions in the first conductivity type substrate at both sides of the gate; forming a first insulating interlayer on an entire structure; forming first contact holes by selectively removing predetermined portions of the first insulating interlayer formed on the first area, the first conductivity type impurity region and the drain region; forming a first metal line on an entire structure including the first contact holes; forming a second area connected to the polysilicon layer of the first area and a predetermined portion of the first conductivity type impurity region, and a third area connected electrically with a preselected portion of the first conductivity type impurity region and the drain region and connected to an input buffer, by patterning the first metal line; forming a second insulating interlayer on an entire structure and then forming a second contact hole exposing a portion of the second area; and forming a second metal line on an entire structure including the second contact hole and then forming an input pad by patterning the second metal line.