Patent ID: 7511989

Claim:
A random access memory cell, comprising: a first plurality of double gate transistors; and a first asymmetric double gate access transistor and a second asymmetric double gate access transistor arranged between a first bit line and a first storage node, and between a second bit line and a second storage node respectively, a first gate of the first access transistor and a first gate of the second access transistor being connected to a first word line capable of carrying a bias signal, a second gate of the first access transistor and a second gate of the second access transistor being connected to a second word line capable of carrying another bias signal, wherein the first access transistor and the second access transistor with asymmetric double-gate comprise an upper gate and a lower gate respectively, and said second word line is dedicated solely to write operations into the cell, the second word line being connected to the lower gate of the access transistors.