Patent ID: 7151686

Claim:
A semiconductor memory device comprising: a cell array including bit lines and word lines disposed to cross each other, and electrically rewritable and non-volatile memory cells disposed at crossings of the bit lines and word lines, plural of said memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged in the bit line direction, each block being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block of said cell array, wherein said row decoder comprises: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with said transferring transistor arrays, which are applied with boosted voltages to selectively drive said transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.