Patent ID: 8119546

Claim:
A method of manufacturing an array substrate comprising: forming a poly silicon pattern having at least one block on a base substrate, grains formed in each block extended in a plurality of directions; forming a gate insulating layer on the base substrate covering the poly silicon pattern; forming a gate electrode on the gate insulating layer, the gate electrode overlapping the poly silicon pattern; forming an insulating interlayer covering the gate insulating layer and the gate electrode; forming a first contact hole through which a first end portion of the poly silicon pattern is exposed and forming a second contact hole through which a second end portion of the poly silicon pattern is exposed in the insulating interlayer and the gate insulating layer; forming a source electrode and a drain electrode, the source and drain electrodes making contact with the first and second end portions through the first and second contact holes, respectively; and forming a pixel electrode electrically connected to the drain electrode, wherein each of the at least one block is divided into a first grain region, a second grain region, a third grain region, and a fourth grain region, and each of the first, second, third, and fourth grain regions has a substantially triangular shape.