Patent ID: 7560337

Claim:
A method of forming an integrated circuit with nonvolatile memory cells, comprising: forming conductive rows accessing the nonvolatile memory cells by row; forming dielectric layers above said conductive rows, the dielectric layers including a first dielectric layer and a second dielectric layer above the first dielectric layer, the first dielectric layer and the second dielectric layer having different etch rates; forming interlayer contacts through the dielectric layers to conductively connect with the conductive rows; reducing a cross-section of a part of the interlayer contacts; forming programmable resistive elements of the nonvolatile memory cells over the interlayer contacts, the interlayer contacts including a first part adjacent to and conductively connected to at least one of the programmable resistive elements, the first part having a top surface, wherein the top surface is higher than the second dielectric layer; and forming conductive columns accessing the nonvolatile memory cells by column to conductively connect with the programmable resistive elements.