Patent ID: 7965536

Claim:
A ferroelectric memory device comprising: a cell module comprising: a first select transistor comprising a first source, a first drain, and a first gate connected to a first select line, one of the first source and the first drain being connected to a bit line, and a memory cell module comprising a plurality of first memory cells connected serially, the first memory cells comprising a first ferroelectric capacitor and a first memory transistor connected to the first ferroelectric capacitor in parallel, the memory cell module being between a first plate line and the other of the first source and the first drain; and a ferroelectric memory fuse comprising: a second select transistor comprising a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to a first end of the bit line; and a memory fuse module comprising a plurality of second memory cells connected serially, the second memory cells comprising a second ferroelectric capacitor and a second memory transistor connected to the second ferroelectric capacitor in parallel, the memory fuse module being between a second plate line and the other of the second source and the second drain, wherein the ferroelectric memory fuse is next to the cell module, and the first select transistor and the memory cell module are in parallel with the bit line.