Patent ID: 6906979

Claim:
A semiconductor memory device having a bit line kicker, comprising: a plurality of sub-arrays provided with a plurality of word lines and a plurality of bit line pairs and a plurality of memory cells selected by the plurality of word lines and bit line pairs, and arranged in a matrix fashion; a main word drive line driver circuit arranged in common to the plurality of sub-arrays, that is, a plurality of sub-arrays arranged in the same column; sub-word drive line driver circuit provided so as to correspond to each of the plurality of sub-arrays, and receiving an output from the main word drive line driver circuit; a plurality of row decoder regions arranged between the plurality of sub-arrays arranged in the same column, and provided with a plurality of row decoders for driving the plurality or word lines of the plurality of sub-arrays, that is, the corresponding sub-array; a plurality of sense amplifier regions arranged between the plurality of sub-arrays arranged in the same row, and provided with a plurality of sense amplifiers connected to the plurality of bit lines pairs of the plurality of sub-arrays, that is, the corresponding sub-array; a pair of bit line kicker drive lines arranged so as to pass through the plurality of sense amplifiers regions, and provided so as to correspond to the plurality of sub-arrays arranged in same column; a pair of bit line kickers provided for each of the plurality of sub-arrays, and connected between the pair of bit line kicker drive lines and each of the plurality of bit lines pairs; and at least one driver provided so as to correspond to each of the plurality of sub-arrays, arranged in each sub-cross region positioned between two adjacent row decoder regions of the plurality of row decoder regions and between two adjacent sense amplifier regions of the plurality of sense amplifier regions, the at least one driver receiving at least a control signal used for selecting a sub-array including an accessed memory cell of the plurality of sub-arrays, the at least one driver having each output node connected to the pair of bit line kicker drive lines, and the at least one driver changing a potential of one bit line so as to increase either of “H” data read signal of “L” data read signal read from one bit line. wherein the control signal includes a first control signal including positional information of the plurality of sense amplifiers, that is, an activated sense amplifier, and a second control signal including information representing to which bit line of the bit line pairs that the accessed memory cell is connected.