Patent ID: 7663965

Claim:
An integrated circuit memory with clock-controlled memory access, comprising: at least one data connection to input/output data; a memory cell array comprising memory cells to store data; a clock generator circuit to generate a clock signal; a memory circuit to store a data item, the memory circuit being connected to the memory cell array and to the at least one data connection; and a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit; the control circuit, in the event of a write access to the memory cells in the memory cell array, being operable to actuate the memory circuit such that: in response to a first edge of the clock signal, a first data supplied to the memory circuit from the at least one data connection is buffer-stored in the memory circuit; in response to a second edge of the clock signal, a second data subsequently supplied to the memory circuit from the at least one data connection is buffer-stored in the memory circuit, the second edge of the clock signal occurring after the first edge occurs; and in response to a common edge of the clock signal, the buffer-stored first and second data are output from the memory circuit and supplied to the memory cell array; wherein memory cells of the memory cell array that are arranged close to an associated word line driver are turned off first at the end of a write operation.