Patent ID: 7817470

Claim:
A memory system comprising: a memory bank having a first bank half coupled to first n parallel datalines where n is an integer value greater than 0, the first bank half including a first sector having wordlines and bitlines coupled to memory cells, a second sector having wordlines and bitlines coupled to memory cells, and a page buffer selectively coupled to bitlines of one of the first sector and the second sector, the page buffer being coupled to the first n parallel datalines a second bank half coupled to second n parallel datalines, and a data converter for selectively converting one of the first and the second n parallel datalines into serial bitstream read data and for selectively converting serial bitstream write data into parallel data for one of the first and the second n parallel datalines, the memory bank providing the serial bitstream read data in response to a read operation and for receiving the serial bitstream write data in response to a write operation and, a serial data path for coupling the serial bitstream read data and the serial bitstream write data between the memory bank and input/output ports.