Patent ID: 8495436

Claim:
A system for testing an electronic circuit including first and second electronic circuit modules that operate on first and second clock frequencies and include first and second memory blocks respectively, wherein the first and second electronic circuit modules generate first and second memory repair data corresponding to the first and second memory blocks respectively, comprising: a multiplexer having a first input terminal for receiving the first memory repair data, a second input terminal for receiving the second memory repair data, and a select input terminal for receiving a select signal, wherein the multiplexer selectively transmits the first memory repair data during a first test cycle corresponding to the first clock frequency and the second memory repair data during a second test cycle corresponding to the second clock frequency; a shadow register, connected to an output terminal of the multiplexer, for buffering the first memory repair data during the first test cycle; and a fuse processor, connected to the shadow register, for sequentially receiving and storing the first and second memory repair data during the second test cycle.