Patent ID: 8377795

Claim:
A multiple etch process for forming a gate in a semiconductor device, the method comprising the steps of: providing a semiconductor substrate; forming a conductor layer for forming transistor gates on the semiconductor substrate; applying a hard mask over the conductor layer; applying a first planarization player over the hard mask; patterning the hard mask and first planarization layer to form first openings over the conductor layer; etching the conductor layer through the first openings to extend the first openings into the conductor layer, the first openings being surrounded by the conductor layer, the hard mask and the first planarization layer; stripping the first planarization layer, leaving the first openings in the conductor layer, the first openings being surrounded by the conductor layer and the hard mask; applying a second planarization layer over the conductor layer and in the first openings in the conductor layer so as to completely fill the first openings; patterning the second planarization layer to form second openings over the conductor layer for spaces between gate lines, the second planarization layer extending completely over the filled first openings; etching the conductor layer through the second openings in the second planarization layer to form the spaces between gate lines resulting in lines of second planarization layer over lines of hard mask and conductor layer and between and completely over at least two adjacent filled first openings while avoiding etching the filled first openings wherein the lines of hard mask and conductor layer being separated by the second planarization layer in the filled first openings; and stripping the second planarization layer from the lines of hard mask and conductor layer and from the filled first openings to result in gate lines comprising hard mask and conductor layer separated by cut areas.