Patent ID: 8793546

Claim:
A method of scan testing an integrated circuit, comprising: providing scan test inputs to each of a plurality of scan chains, each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register, the plurality of scan chains comprising sets of two or more parallel scan chains; and multiplexing scan test outputs from the parallel scan chains within each of the sets of parallel scan chains, wherein providing scan test inputs comprises driving each of the parallel scan chains of a given one of the sets of two or more parallel scan chains with the same scan input signal; wherein the scan testing comprises compressed scan testing, the providing further comprises shifting the same scan input signal from a decompressor simultaneously into each of the parallel scan chains of a given one of the sets of parallel scan chains, and the multiplexing comprises shifting scan test output data out of the parallel scan chains of the given set of parallel scan chains to a compressor; wherein outputs of the compressor are sampled, within a single clock cycle of a clock signal used to shift data through the parallel scan chains, at a clock rate that is a multiple of a clock rate used to shift data through the parallel scan chains, the multiple being given by the number of parallel scan chains in the given set.