Patent ID: 7865856

Claim:
A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static timing analysis on a circuit represented by a transistor-level netlist, said method comprising: converting said transistor-level netlist to a cell-level netlist by modeling each transistor within the transistor-level netlist as a corresponding tri-state buffer cell within the cell-level netlist, wherein an enable pin of a tri-state buffer is used to model a gate terminal of a corresponding transistor, and wherein an input pin of the tri-state buffer is used to model a drain of the corresponding transistor, and wherein an output pin of the tri-state buffer is used to model a source of the corresponding transistor; operating a computer implemented analysis tool separate from the static performance analyzer to determine gate-to-drain timing arc data and source-to-drain timing arc data for each transistor within the transistor-level netlist; storing the determined gate-to-drain and source-to-drain timing arc data for each transistor as enable timing arc data and input-to-output timing arc data, respectively, for the tri-state buffer used to model the transistor, within a computer readable library accessible by the static performance analyzer; and operating a computer to execute the static performance analyzer to perform a static timing analysis of the cell-level netlist, wherein the static timing analysis is performed based on the enable timing arc data and the input-to-output timing arc data stored within the computer readable library for each tri-state buffer in the cell-level netlist, whereby results of the static timing analysis of the cell-level netlist represent static timing analysis results of the transistor-level netlist.