Patent ID: 7734981

Claim:
A signal decoder comprising: an interleaving circuit for sorting an order of an input signal series of a prescribed number of signals; a low density parity check decoder for performing low density parity check decoding, using a prescribed matrix, on the signal series sorted by the interleaving circuit; and a de-interleaving circuit for sorting an order of signals outputted from the low density parity check decoder; wherein the prescribed matrix is a matrix for checking a low density parity series, and a logical sum of elements of M columns, M being an integer greater than or equal to 2, included in the matrix gives a zero matrix; wherein the interleaving circuit sorts at least one signal, by interchanging with another signal, among the signals acted upon relating to respective columns, with the logical sum of the M columns, M being an integer greater than or equal to 2, being a zero matrix, by the low density parity check decoder.