Patent ID: 6911704

Claim:
A memory cell array comprising: a two dimensional array of memory cells fabricated on a semiconductor substrate, the memory cells arranged in a plurality of rows of memory cells defining a horizontal row direction and a plurality columns of memory cells defining a column direction that is perpendicular to the horizontal row direction; each column of memory cells comprising a plurality of channel regions of the substrate, each channel region of the substrate being separated from an adjacent channel region within the column by a source/drain region, each source/drain region being a portion of the substrate that is implanted with a first impurity to form a first conductivity type semiconductor; a plurality of conductive interconnects, each conductive interconnect being positioned above only one source/drain region within a first column of the memory cells and coupling to only one other source/drain region, the one other source/drain region begin in a second column that is adjacent to the first column and being in the same row as the source/drain region, and wherein the conductive interconnects are positioned such that every other conductive interconnect connects to the second source/drain region in the adjacent column to a right side of the first column and every other interconnect connects to the second source/drain region in the adjacent column to the left side of the first column; and a plurality of source/drain control lines, extending above the array in the column direction and positioned between adjacent columns of memory cells and electrically coupling to each conductive interconnect that couples between a source/drain region in each of the adjacent columns.