Patent ID: 7287649

Claim:
An integrated circuit comprising: a processor coupled to a bus; a cache memory coupled to the bus to cache a portion of a data packet in cache blocks for the integrated circuit; a memory controller coupled to the bus; and a plurality of packet interface circuits to interface to one or more connections external to the integrated circuit to receive and send packets, each packet interface circuit to include a receive/transmit control unit, a receive buffer and a transmit buffer to receive a data packet from an external connection, temporarily store the received data packet in the receive buffer, cache first N cache blocks of the received data packet that includes a header in the cache memory with a cache hit when a control signal is asserted, in which a number for N is determined by a value stored in a register, store a payload of the received data packet in a memory coupled to the memory controller without caching and transfer the first N blocks onto the bus for use by the processor, in which the processor causes a cache hit to the cached first N cache blocks to retrieve the payload from the memory; each packet interface circuit to store all of the received data packet in the memory without caching when the control signal is not asserted with a cache miss; each packet interface circuit to update the cache with the data packet with a cache hit regardless of assertion or de-assertion of the control signal; and each packet interface circuit also to temporarily store the received data packet in the transmit buffer and to retransmit the data packet onto an external connection, wherein the processor, the cache memory, the memory controller, and the packet interface circuits are integrated onto a single semiconductor substrate to operate as a system on a chip.