Patent ID: 8116366

Claim:
A delayed decision feedback sequence estimator, comprising: a DDFSE (delayed decision feedback sequence estimator) computing unit group including a plurality of DDFSE computing units, equal in number to a length of each of a plurality of blocks into which a received data symbol sequence is divided, the plurality of DDFSE computing units being connected in a pipeline configuration to execute a delayed decision feedback sequence estimation of respective blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to performing the delayed decision feedback sequence estimation of the divided block and corrects a relevant bit error in the block, wherein each of the plurality of blocks includes (L+M) symbols, where L and M are predetermined positive integers, respectively, L corresponding to a length of a synch portion and M corresponding to a length of a data portion, wherein said plurality of blocks include respectively L symbols overlapped with associated succeeding/preceding blocks, wherein the edge effect detection and correction circuit detects an occurrence of the edge effect in a primary estimation result of the block, by comparing the primary estimation result of the synch portion of the plurality of blocks and the primary estimation result of the data portion of the preceding block, wherein, when detecting the edge effect in the primary estimation result of the block, the edge effect detection and correction circuit re-executes the delayed decision feedback sequence estimation of the block to generate a secondary estimation result, the edge effect detection and correction circuit outputting the secondary estimation result for the block with the edge effect being detected, while outputting the primary estimation result for the block without the edge effect.