Patent ID: 8866659

Claim:
A data acquisition system, comprising: a) an analog-to-digital converter (ADC) responsive to an applied analog input signal to generate a digital output signal at a digital output, wherein the digital output signal includes a succession of digital values, and wherein each digital value is representative of a value of the analog input signal and a corresponding succession of sample times; b) a data channel coupled to the digital output signal and including in series connection therefrom, a data acquisition memory and a data equalizer; c) a real-time trigger channel coupled to the digital output and including in series connection therefrom, i. a composite function trigger equalizer and filter, ii. a pre-interpolator, iii. a trigger processor, iv. a trigger counter and time mark, and v. a trigger memory; d) a trigger channel controller; and e) a write/read address generator, wherein the data acquisition memory is adapted to receive and store the succession of digital values as those values are generated, wherein the composite function trigger equalizer and filter comprise a digital FIR filter having filter coefficients determined by an applied bandwidth signal and an applied filter-type signal, wherein the trigger channel controller i. generates the bandwidth signal and the filter-type signal in response to an applied interface control signal, and ii. applies the bandwidth signal and filter-type signal to the FIR filter, wherein the composite function trigger equalizer and filter is adapted to process in real time, the succession of digital values in accordance with the filter coefficients and apply the processed values to the pre-interpolator, wherein the pre-interpolator and the trigger processor are operative in response to the processed digital values, to identify one or more trigger events, wherein the trigger counter and time mark is responsive to identified trigger events, to generate and store in the trigger memory, real-time trigger event occurrence signals representative of the occurrence of and corresponding time of occurrence of, the respective identified trigger events, and wherein the write/read address generator selectively reads out the stored data values from the data acquisition memory by way of the data equalizer, in synchronism with the corresponding real-time trigger event occurrence signals from the trigger memory.