Patent ID: 7013559

Claim:
A method of fabricating a semiconductor device package, comprising: providing a substrate having a first surface and a second surface, at least one of the first and second surfaces including a plurality of conductors, at least one of the first and second surfaces comprising at least one semiconductor device attach site; disposing a solder mask layer on at least part of the at least one of the first surface and the second surface; providing an opening in the solder mask layer serving as a combination pin one indicator and alignment fiducial; providing at least one semiconductor device; aligning the at least one semiconductor device to the at least one semiconductor device attach site using the combination pin one indicator and alignment fiducial; attaching the at least one semiconductor device to the at least one semiconductor device attach site; aligning a severing device for severing the substrate using the combination pin one indicator and alignment fiducial; and severing at least a portion of the substrate to obtain at least one semiconductor device package.