Patent ID: 6938108

Claim:
A micro-controller controlling a data transfer to or from a host device through a pair of data lines for transferring a first data at the first data line and a second data at the second data line, which is different from the first data respectively, comprising: an internal circuit; a transfer control unit, which is operated in response to a oscillation signal, watching a condition of the data transfer at the pair of the data lines, and outputting a first output signal having a first logic level or a second logic level, and a third output signal having a first logic level or a second logic level as a watching result, the transfer control unit having a function for receiving the first data and the second data and transferring a desired data to the host device through the pair of data lines, wherein the third output signal is in the first logic level when the transfer control unit is in a condition of a suspend mode, and the third output signal is in the second logic level when the transfer control unit is in a condition of a resume mode; a main control unit, which is operated by the oscillation signal, receiving the first output signal from the transfer control unit, and controlling an operation of the internal circuit in response to the first output signal having the second logic level, the main control unit changing its mode from an operative mode to an inoperative mode in response to the first output signal having the first logic level or from the inoperative mode to the operative mode in response to the first output signal having the second logic level, and the main control unit outputting a second output signal having the first logic level when the main control unit is in the inoperative mode and outputting the second output signal having the second logic level when the main control unit is in the operative mode; a logic circuit, which receives the second output signal and the third output signal, outputting fourth output signal, the fourth output signal being in the first logic level when both of the second and the third output signals have the first logic level, and the fourth output signal being in the second logic level when the logic levels of the second and the third output signals is in the other conditions; and an oscillating circuit generating the oscillation signal having a frequency, the oscillating circuit being inactivated in response to the fourth output signal having the first logic level, and the oscillating circuit being activated in response to the fourth output signal having the second logic level, whereby the oscillating circuit is maintained to be in an operable state when one of the transfer control unit and the main control unit is in the operable state.