Patent ID: 8305509

Claim:
A semiconductor device comprising: a first substrate having a first thin film transistor including an amorphous semiconductor for a channel portion adjacent to a region in which a scan line and a data line intersect with each other with an insulating layer interposed therebetween; a second substrate having a counter electrode; and a third substrate having a second thin film transistor including a crystalline semiconductor for a channel portion, wherein the crystalline semiconductor comprises a grain boundary which extends along a flow of electrons or holes in the second thin film transistor, wherein the first substrate and the second substrate are attached to each other so that the first substrate is exposed, wherein the third substrate is attached to an exposed region over the first substrate by using an anisotropic conductive material, wherein a first region for forming the second thin film transistor and a second region for forming an input terminal and an output terminal are formed over the third substrate, wherein the short side length of the third substrate is in the range of 1 to 6 mm, and the short side length of the first region is in the range of 0.5 to 1 mm, and wherein the pitch of either or both of the input terminal and the output terminal is the same as that of either the scan line or the data line.