Patent ID: 7646177

Claim:
A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a data store; a duty cycle measurement (DCM) circuit, coupled to the data store, the DCM circuit operating in a calibration mode to store a plurality of voltage values and corresponding duty cycle values in the data store, each voltage value being dependent on a respective duty cycle value; and a control mechanism, coupled to the DCM circuit, configured to control the DCM circuit in the calibration mode and to control the DCM circuit in a test mode wherein the system determines the duty cycle of a test clock signal exhibiting an unknown duty cycle; the DCM circuit including charger circuitry that operates in the test mode to receive the test clock signal, the charger circuitry charging a capacitor in the DCM circuit to a test voltage value that depends on the duty cycle of the test clock signal, the control mechanism operating in the test mode to access the data store to determine a duty cycle which corresponds to the test voltage value.