Patent ID: 7890913

Claim:
A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD), wherein the routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD, the method comprising: maintaining in a computing system a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively; identifying in the computing system a first one of the routing graph wires; and mapping in the computing system the first routing graph wire to a second one of the routing graph wires using at least one of the master wires, wherein the first routing graph wire is a segmented wire of the PLD, the second routing graph wire is a composite wire of the PLD, and the composite wire comprises the segmented wire, wherein the mapping comprises: mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; Identifying a segmented wire of the PLD connected to the master switch; mapping the segmented wire of the PLD to a second master wire; and mapping the second master wire to the second routing graph wire, wherein the second routing graph wire is connected to the first routing graph wire through at least one of the routing graph switches.