Patent ID: 7146587

Claim:
A system for testing integrated circuitry comprising a plurality of clock domains and at least one integrated circuit chip, the system comprising: a command transfer control hierarchy comprising a plurality of control levels, including a first level comprising a master command transfer control, and including at least one additional lower level, each lower level having a plurality of command transfer controls configured serially, each command transfer control of a last level being associated with at least one of the clock domains , the command transfer control hierarchy being scalable, the master command transfer control and each command transfer control each having an equal number of input lines and output lines; a communication protocol for communicating commands among the control levels; and wherein command activation signals are immediately propagated serially from the first level to lower levels, and serially across command transfer controls in each level; and wherein command deactivation signals are communicated serially among and across control levels upon receipt of feedback from all lower levels that a commanded operation has been completed.