Patent ID: 8904335

Claim:
A method comprising: evaluating electrical accessibility within a layer of a circuit to at least one established pin geometry of an established pin geometry layout within a cell boundary of the circuit, the evaluating comprising: checking along a plurality of substantially parallel pin geometry access paths of the layer to determine a plurality of fixed possible points at which a respective established pin geometry of the at least one established pin geometry within the cell boundary may be accessed, the pin geometry access paths being paths for possible routes of electrical connections in the layer of the circuit; and identifying, by a hardware processor, which points of the plurality of fixed possible points are accessible access points by any route of the possible routes for electrically connecting to a respective established pin geometry of the at least one established pin geometry from a first side or a second side of the cell boundary, wherein at least one point of the plurality of fixed possible points is identified as not being an accessible access point based on the at least one point being inaccessible by the possible routes.