Patent ID: 7692461

Claim:
A delay locked loop comprising: a voltage controlled delay circuit having an input and an output; a phase detector detecting phase difference between a feedback clock derived from the output of the voltage controlled delay circuit and the input to the voltage controlled delay circuit; a loop filter providing a control voltage to the voltage controlled delay circuit; and a charge pump comprising: a pull-up circuit which generates pull-up current to increase voltage at a charge pump output, the charge pump in electrical communication with the loop filter through the charge pump output; a pull-down circuit which generates pull-down current to decrease voltage at the charge pump output; an operation amplifier having two inputs and an output, the operational amplifier configured to reduce phase error, one of the inputs of the operational amplifier connected to a charge pump output node; and a reference current source having a plurality of select transistors and a plurality of mirror master transistors, said mirror master transistors coupled to slave transistors of a selected one of said pull-up circuit and said pull-down circuit to mirror variable current in said slave transistors.