Patent ID: 6900064

Claim:
A method for fabricating an NAND type non-volatile ferroelectric memory cell, comprising the steps of: (1) forming an N number of wordlines and a WEC electrode on a first conduction type semiconductor substrate at fixed intervals; (2) forming ferroelectric capacitor first electrodes over the wordlines excluding the WEC electrode with a barrier metal disposed in-between; (3) forming a capacitor electrode material on the WEC electrode; (4) forming impurity regions in the substrate on both sides of the ferroelectric capacitor first electrodes and the WEC electrode; (5) forming a ferroelectric film at sides and top of the ferroelectric capacitor first electrodes and the capacitor electrode material; (6) forming ferroelectric capacitor second electrodes on the ferroelectric film; (7) deposing an insulating film on entire structure after removing the ferroelectric film and the ferroelectric capacitor second electrode formed on the WEC electrode; (8) forming contact holes to expose the impurity regions excluding first and last impurity regions and to expose a portion of each ferroelectric capacitor second electrode; (9) forming plugs for connecting each impurity region to the ferroelectric capacitor second electrode, respectively; (10) depositing the insulating film after forming the plugs; (11) forming contact holes to expose the first and the last impurity regions; and (12) filling conductive material with the contact holes for the first and the last impurity regions; and (13) thereby forming bitlines.