Patent ID: 7116571

Claim:
A data processing circuit having a nonvolatile memory and a central processing circuit structured on one semiconductor substrate, wherein said nonvolatile memory is capable of storing a program and/or date, wherein said central processing circuit is capable of fetching said program from said nonvolatile memory, wherein said nonvolatile memory comprises bit lines, word lines, and memory cells, wherein said memory cell comprises a MOS transistor whose gate electrode is connected with a word line, and information storage is carried out according to whether one source/drain electrode of said MOS transistor is connected with a current path or floated, and wherein a control circuit is provided which produces a potential difference between the source/drain electrodes of said MOS transistor during a predetermined period in the operation of accessing said memory cell, and makes zero the potential difference between the source/drain electrodes of said MOS transistor during periods other than said predetermined period.