Patent ID: 7180134

Claim:
A semiconductor device comprising: an insulator layer; a planar transistor formed on a first portion of a semiconductor layer, the first portion of the semiconductor layer overlying the insulator layer, and the first portion of the semiconductor layer having a first thickness; a multiple-gate transistor formed on a second portion of the semiconductor layer, the second portion of the semiconductor layer overlying the insulator layer, the second portion of the semiconductor layer having a second thickness, and the second thickness being larger than the first thickness; and the planar transistor comprising: a planar channel formed from the first portion of the semiconductor layer; a gate dielectric having vertical portions on opposite sidewalls of the planar channel and a horizontal portion on a top surface of the planar channel; a gate electrode overlying the gate dielectric, wherein the gate electrode has vertical portions on the vertical portions of the gate dielectric and a horizontal portion on the horizontal portion of the gate dielectric; and source and drain regions formed in the first portion of the semiconductor layer oppositely adjacent the gate electrode.