Patent ID: 7953581

Claim:
A method of analyzing a power grid in an integrated circuit comprising: inputting a circuit design to a test bench; inputting a plurality of initial values for the circuit design in to the test bench; setting a current time t to 0 value for an initial time (t 0 ) of the operation of the circuit design; representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model; describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations; storing the plurality of linear equations in a matrix Y 0 for time t 0 ; resolving the matrix Y 0 to determine a DC operating point; updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t 1 =t+h where h is a time step value equal to the current time t and a next simulated operation time; storing the updated plurality of linear equations in a matrix Y 1 for time t 1 ; inverting the matrix Y 1 to form inverted matrix Y 1 −1 ; resolving the inverted matrix Y 1 −1 ; calculating a new time step and setting the current time t to t+h; comparing the new time step h to a plurality of time steps in a time step database; selecting one of the plurality of time steps substantially equal to the new time step; and recalling a solution corresponding to the selected time step.