Patent ID: 6870226

Claim:
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an N-channel MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, an N-type source/drain active layer formed adjacent to said gate electrode in said SOI layer, and a P-type body layer formed at least under said gate electrode in said SOI layer; and a P-type active layer for body voltage application which is formed in said SOI layer and in contact with said P-type body layer, wherein a path connecting said P-type body layer and said P-type active layer for body voltage application is aligned parallel to a crystal direction of said SOI layer.