Patent ID: 8117603

Claim:
An operation synthesis system executed by one or more processors comprising: a control data flow graph creator that produces a control data flow graph including information capable of identifying that a part of description is loop description; a state transition creator that produces a state transition from said control data flow graph and gives each state a state number; and a pipeline structure creator that generates a pipeline structure from said state transition divided into stages, based on a data initiation interval designated by a user or automatically set by the system, wherein said pipeline structure creator: (1) generates a first flag for each of the stages if there is a loop description in said state transition; (2) assigns an evaluation value to said first flag; (3) generates a second flag corresponding to each of the stages; and (4) generates a stage execution part of the following state of the stage where said loop description is executed, when said first flag is false and said second flag is true.