Patent ID: 8015380

Claim:
A data processing system comprising: a processor; a memory subsystem having a memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; an asynchronous memory mover coupled to the processor and which includes: multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations; logic that detects a receipt of a first set of parameters in a first set of registers, wherein the first set of parameters are forward to the asynchronous memory mover from the processor after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address; logic that, in response to receiving the first set of parameters, generates and launches a first asynchronous memory move (AMM) operation by which first data are moved from a first memory location having a source real address corresponding to the source effective address to a second memory location having a destination real address corresponding to the destination effective address; logic that monitors a completion of the first AMM operation at the memory; and logic that responds to a detection of a second set of parameters in a second set of registers by generating and launching .a second AMM operation concurrently with the first AMM operation, wherein parallel movement of data within the memory is supported; an address translation mechanism associated with the asynchronous memory mover and which includes: logic that translates the source effective address and the destination effective address of the data move operation into the corresponding source real address and destination real address following completion of the data move operation in effective address space; and logic that provides the source real address and destination real address to the asynchronous memory mover to complete the data move within the memory; wherein both the first AMM operation and the second AMM operation occur concurrently within the memory subsystem, independent of the processor.