Patent ID: 7668271

Claim:
A circuit, comprising: a clock circuit capable of generating a clock signal having a phase, the clock circuit including a phase adjuster capable of making an adjustment to the phase of the clock signal during each of a plurality of adjustment cycles in response to an adjustable phase step-size; a sampler, coupled to the clock circuit, capable of receiving, in response to the clock signal, a data signal having a variable data bit-rate by outputting sampled data bits as received data signal; and wherein the circuit further includes phase detection and logic circuitry capable of stalling adjustment of the phase of the clock signal during one or more current adjustment cycles in response to data phase information derived from a plurality of data bits during one or more previous adjustment cycles, wherein the circuit further includes a phase adjust step-size logic capable of outputting the adjustable phase step-size having an adjustable magnitude dependent on the variable data bit-rate.