Patent ID: 6933199

Claim:
A method for fabricating a high voltage device, a low voltage device and a memory device of an integrated circuit, comprising: forming a source region and a drain region associated with a gate region for each of a high-voltage (HV) device, a low-voltage (LV) device and a non-volatile memory (NVM) device, the HV, LV and NVM devices each electrically isolated by a field oxide region located adjacent the source and drain regions; forming field implant regions under the field oxide regions; forming a blanking layer on the field oxide regions and a portion of the source and drain regions associated with the HV and NVM devices; depositing a metal layer on the gate regions, the blanking layer and exposed portions of the source and drain regions not covered by the blanking layer; and forming metal salicide regions in the gate regions and the exposed portions of the source and drain regions.