Patent ID: 6977523

Claim:
A voltage level shifting circuit comprising: a first power supply node supplied with a first power supply potential level; a second power supply node supplied with a second power supply potential level higher than the first power supply potential level; a third power supply node supplied with a third power supply potential level higher than the second power supply potential level; a signal input circuit which is coupled between the first power supply node and the second power supply node, which receives a signal having the first and second power supply potential levels, and which outputs complementary signals having the first and second power supply potential levels; a complimentary signal input circuit which is coupled to the first power supply node and which includes a pair of first MOS transistors, each of the first MOS transistors has a first withstand voltage and has a first electrode coupled to the first power supply node, a second electrode, and a gate electrode receiving one of the complementary signals; a load circuit which is coupled to the third power supply node and which includes a pair of second MOS transistors, each of the second MOS transistors has a second withstand voltage higher than the first withstand voltage and has a first electrode coupled to the third power supply node, a second electrode, and a gate electrode; a first voltage down-converting circuit which is coupled between the load circuit and the complimentary signal input circuit, and which prevents a potential level exceeding the first withstand voltage from being supplied to the complimentary signal input circuit; a third MOS transistor which is coupled between the third power supply node and an output node, which has the second withstand voltage, and which electrically connects the third power supply node to the output node in response to a voltage potential output from the load circuit; a fourth MOS transistor which is coupled between the first power supply node and the output node, which has the first withstand voltage, which has a gate directly coupled to one of the complimentary signals, and which electrically connects the first power supply node to the output node in response to a voltage potential of the one of the complimentary signals; and a second voltage down-converting circuit which is coupled between the third MOS transistor and the fourth MOS transistor and which prevents a potential level exceeding the first withstand voltage from being supplied to the fourth MOS transistor.