Patent ID: 7551474

Claim:
A memory device, comprising: a memory cell including a pass transistor and a capacitor; and a local sense amp including a first reduced swing amplifier and a write transistor, wherein the first reduced swing amplifier is used for limiting voltage swing of a local bit line connecting to the memory cell from a pre-charge voltage to a supply voltage, such that the first reduced swing amplifier is composed of a local pre amplifier and a local main amplifier, the local pre amplifier includes a local pre-charge transistor for pre-charging the local bit line to the pre-charge voltage, a local pre-amp transistor for detecting whether the local bit line is higher than the pre-charge voltage or not; and the local main amplifier includes a local pre-set transistor for pre-setting a local pre-amp node connecting to the local pre-amp transistor, a local main-amp transistor connecting to the local pre-amp node for driving a global bit line through a local select transistor; and the write transistor is connected to the local bit line for receiving a voltage output of the global bit line; and a global sense amp including a global read circuit, a global write circuit, a global latch circuit, a data transfer circuit and a data receive circuit, wherein the global read circuit is composed of a second reduced swing amplifier for limiting voltage swing of the global bit line, such that the second reduced swing amplifier is composed of a global pre amplifier and a global main amplifier, the global pre amplifier includes a global pre-charge transistor for pre-charging the global bit line to the pre-charge voltage, a global pre-amp transistor for detecting whether the global bit line is higher than the pre-charge voltage or not; and the global main amplifier includes a global pre-set transistor for pre-setting a global pre-amp node connecting to the global pre-amp transistor, a global main-amp transistor connecting to the global pre-amp node, and a global select transistor connecting to the global main-amp transistor serially; and the global write circuit is composed of a reduced swing write driver for driving the global bit line to the pre-charge voltage when writing data “0” and the supply voltage when writing data “1”; and the global latch circuit is connected to the global read circuit and the global write circuit; and the data transfer circuit receives a read output from the global latch circuit and transfers to a read line; and the data receive circuit receives a write input from a write line and sends to the global latch circuit; and a locking signal generator for locking the global select transistor of the global read circuit, wherein the locking signal generator includes a tunable delay circuit receiving an output from the global latch circuit.