Patent ID: 7115425

Claim:
A test structure set for determining a polishing process parameter range for an integrated circuit structure on a substrate, the test structure set comprising: a first metrology site on the substrate, the first metrology site representing a design extreme of a high density integrated circuit structure, the first metrology site having a relatively small horizontal surface area trench filled with an insulating material within a relatively large surface area field of a polish stop material, where the first metrology site is disposed at a first intersection of two scribe lines that are disposed at substantially right angles between four adjacent integrated circuits, the trench is both not as wide and as long as a width of the scribe lines and thereby does not completely fill the first intersection of the two scribe lines, and the field is both at least as wide and at least as long as the width of the scribe lines and thereby substantially completely fills the first intersection of the two scribe lines, and a second metrology site on the substrate, the second metrology site representing a design extreme of a low density integrated circuit structure, the second metrology site having a relatively large horizontal surface area trench filled with the insulating material within a relatively small surface area field of the polish stop material where the second metrology site is disposed at a second intersecion of two scribe lines that are disposed at substantially right angles between four adjacent circuits, the second intersection different from the first intersection, the trench is both substantially as wide and substantially as long as a width of the scribe lines and thereby substantially completely fills the second intersection of the two scribe lines, and the field is both wider ad longer than the width of the two scribe lines and thereby extends past the second intersection of the two scribe lines and along both of the two scribe lines in four orthogonal directions.