Patent ID: 8901951

Claim:
A circuit for four terminal measurement point (TMP) testing of devices under test (DUT), comprising: a pair of p-type access transistors, a terminal of each of the pair of p-type access transistors selectively providing operable coupling(s) between a first end of the DUT and each of a first terminal measurement point and a third terminal measurement point of the DUT; a pair of n-type access transistors, a terminal of each of the pair of n-type access transistors selectively providing operable coupling(s) between a second end of the DUT and each of a fourth terminal measurement point and a second terminal measurement point of the DUT, wherein the first terminal measurement point, the second terminal measurement point, the third terminal measurement point, and the fourth terminal measurement point form distinct electrical nodes from each other, wherein the pair of p-type access transistors and the pair of n-type access transistors have their gates coupled together and connected to bank selection logic, the bank selection logic defining conditions for if all or specific ones of the two or more DUTs in a bank are identified for testing, wherein the pair of p-type access transistors and the pair of n-type access transistors are operable for detecting defects during semiconductor wafer manufacturing; and a first level containing DUTs; a second level containing DUTs, wherein the DUTs in the first level or second level are stacked, and are individually selectable, and wherein row and column select logic is provided to the DUTs in each of the first level and the second level.