Patent ID: 7127692

Claim:
A method of designing an integrated circuit, comprising: monitoring user interaction with logical blocks during a functional design process of an integrated circuit; and deriving, without affecting the functional design process, indications of timing properties during the functional design process based on the monitored user interaction, the indications of timing properties including background heuristics describing timing properties of the logical blocks within a hierarchy of functional elements of the integrated circuit, wherein the indications of timing properties are used during back end stages to complete timing closure and verification after completion of the functional design process, and wherein a mathematical formulation is provided based on the achieved functional design and the derived timing indications, the mathematical formulation including functional description of the integrated circuit, block structure in which a relationship of logical blocks is expressed, hierarchy in which the logical blocks are expressed, timing implications of logical blocks in terms of timing specification for the integrated circuit, content of timing indications and structure of timing indications.