Patent ID: 7506134

Claim:
A computer implemented method for mapping one or more cooperative thread arrays (CTA) to different tiles of a result matrix to perform a matrix multiplication operation, wherein each CTA includes one or more thread groups, and each thread group in a given CTA includes a plurality of threads that are concurrently executable on a given processor core, with each thread in a given thread group processing a data element using a portion of the given processor core, and each tile comprises at least a portion of elements in the result matrix, the method comprising: determining a tile size as a first integer multiple of a number of threads in one CTA, wherein the tile size specifies the portion of elements in the result matrix within each tile; dividing the result matrix into one or more tiles based on the tile size; determining a CTA size as a second integer multiple of the number of threads in each thread group based on resources available to the threads in each thread group; creating a CTA grid based on the number of CTAs that are concurrently executable across one or more processor cores, wherein each CTA is assigned a different location in the CTA grid to form an array of CTAs covering the CTA grid, each tile is associated with a different tile position in the result matrix, and each location in the CTA grid is assigned a set of tile positions in the result matrix; creating a first CTA for a first location within the CTA grid; and issuing the first CTA for execution on one of the one or more processor cores, wherein the first CTA is responsible for processing a first tile associated with the first location within the CTA grid and each element in the first tile is computed by a thread of the first CTA.