Patent ID: 7826519

Claim:
An integrated circuit comprising: a clock receiver configured to receive an external clock signal generated external to the integrated circuit; a local clock source arranged on the integrated circuit and configured to generate a local clock signal; a selector configured to select one of said external clock signal and said local clock signal; a clock transmitter configured to transmit the selected one of the said external clock signal and said local clock signal externally to the integrated circuit; and a wireless transceiver configured to determine which one of a plurality modes to operate and further configured to operate in a determined one of the plurality of modes, wherein the plurality modes comprise: an autonomous mode in which said selector selects the local clock signal; a master mode in which said selector selects the local clock signal and said clock transmitter transmits the selected local clock signal; a slave mode in which said selector selects the external clock signal; and a repeat mode in which said selector selects the external clock signal and said clock transmitter transmits the selected external clock signal, wherein the wireless transceiver activates the local clock source and deactivates the clock receiver and the clock transmitter in the autonomous mode, wherein the wireless transceiver activates the local clock source and the clock transmitter and deactivates the clock receiver in the master mode, wherein the wireless transceiver activates the clock receiver and deactivates the local clock source and the clock transmitter in the slave mode, and wherein the wireless transceiver activates the clock receiver and the clock transmitter and deactivates the local clock source in the repeat mode.