Patent ID: 7187037

Claim:
A semiconductor integrated device comprising an electrostatic discharge ESD protection circuit constituted on a semiconductor substrate, wherein said ESD protection circuit comprises: a first-conductivity type well formed on a surface of said semiconductor substrate; a first second-conductivity type well and a second second-conductivity type well formed oppositely to each other and adjacent to said first-conductivity type well, with said first-conductivity type well interposed between them, on the surface of said semiconductor substrate; a first high concentration first-conductivity type region formed on the surface of said first second-conductivity type well; a second high concentration first-conductivity type region formed on the surface of said second second-conductivity type well; a first high concentration second-conductivity type region formed oppositely to said first high concentration first-conductivity type region on the surface of said first-conductivity type well; a second high concentration second-conductivity type region formed oppositely to said second high concentration first-conductivity type region on the surface of said first-conductivity type well; a third high concentration first-conductivity type region formed on the surface of said first-conductivity type well and interposed between said first high concentration second-conductivity type region and said second high concentration second-conductivity type region; and a trigger device having two terminals, wherein a current flows when a voltage higher than a predetermined value is applied across said two terminals; said first high concentration second-conductivity type region and said second high concentration second-conductivity type region are connected to an I/O pad; one of the terminals of said trigger device is connected to said third high concentration first-conductivity type region via wiring and the other terminal is connected to a reference voltage terminal; and said first high concentration first-conductivity type region and said second high concentration first-conductivity type region are connected to said reference voltage terminal.