Patent ID: 7829388

Claim:
A method for forming an integrated circuit package comprising: providing a substrate having a first surface and a second surface opposite thereto; forming a first conductive layer on the first surface of the substrate, acting as a first heat dissipation layer; forming a second conductive layer on the second surface of the substrate; selectively etching the second conductive layer and the substrate to form a first opening through the second conductive layer and the substrate; forming a second heat dissipation layer in the opening; patterning the second conductive layer to form a plurality of conductive lines on a portion of the second surface; providing a semiconductor chip above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate; and forming a plurality of bonding pads on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the conductive lines.