Patent ID: 7193200

Claim:
A receiver circuit for a push-pull transmission method, comprising: a) a first input operable to receive a first input signal, a second input operable to receive a second input signal, and an output operable to provide an output signal based on the first input signal and the second input signal; b) a first signal detector connected to the first input and a second signal detector connected to the first input, the first signal detector operable to provide a first detector signal depending on a comparison of the first input signal with a first threshold, the second signal detector operable to provide a second detector signal depending on a comparison of the first input signal with a second threshold, wherein the first threshold is greater than the second threshold; c) a third signal detector connected to the second input and a fourth signal detector connected to the second input, the third signal detector operable to provide a third detector signal depending on a comparison of the second input signal with a third threshold, the fourth detector operable to provide a fourth detector signal depending on a comparison of the second input signal with a fourth threshold, wherein the third threshold is greater than the fourth threshold; d) a first buffer store including a first data input, a first reset input, and a first data store output, the first data input connected to the first signal detector, wherein the first buffer store is operable to receive the first detector signal at the first data input, receive the fourth detector signal at the first reset input, and buffer-store the third detector signal and forward it to the first data store output as a first data store output signal following a first delay duration; e) a second buffer store including a second data input, a second reset input, and a second data store output, the second data input connected to the third signal detector, wherein the second buffer store is operable to receive the third detector signal at the second data input, receive the second detector signal at the second reset input, and buffer-store the third detector signal and forward it to the second data store output as a second data store output signal following a second delay duration; and f) a combination circuit operable to generate the output signal depending on the first data store output signal and the second data store output signal.