Patent ID: 8125830

Claim:
A method of operating an electrically erasable programmable non-volatile memory in an integrated circuit formed at a surface of a substrate, wherein the memory comprises: a plurality of memory cells arranged in an array, each memory cell having a coupling capacitor and a combined read transistor and tunneling capacitor, and each memory cell comprising: a first well region of a first conductivity type at a location of the surface; a second well region at a location of the surface; a dielectric layer overlying portions of the first and second well regions; a polycrystalline silicon gate element disposed over the dielectric layer at locations above the first and second well regions, and having an area overlying the first well region that is substantially larger than an area of the gate element overlying the second well region, the portion of the gate element disposed over the dielectric layer at the first well region defining a coupling capacitor, and the portion of the gate element disposed over the dielectric layer at the second well region defining a combined read transistor and tunneling capacitor; a first diffused region of a second conductivity type formed at a surface of the first well region at least at locations adjacent to the locations at which the gate element is disposed; source and drain diffusions disposed in the second well region on opposite sides of the gate element, and of an opposite conductivity type from that of the second well region; and a plurality of conductor elements making electrical contact to the first well region, to the second well region, and to the source and drain diffusions; and read/write circuitry, coupled to the plurality of memory cells by way of the conductor elements, for applying voltages to one or more selected memory cells to program, erase, and read the selected memory cells; and wherein the method comprises: programming one or more selected memory cells by controlling the read/write circuitry to apply, to one or more selected memory cells via the conductor elements, a positive voltage to the first well region and the first diffused region, relative to the source diffusion and second well region; erasing one or more selected memory cells by controlling the read/write circuitry to apply, to one or more selected memory cells via the conductor elements, a positive voltage to the source diffusion and second well region, relative to the first well region and the first diffused region; and reading one or more selected memory cells by applying, to one or more selected memory cells via the conductor elements, a drain-to-source voltage at the drain and source diffusions.