Patent ID: 8898554

Claim:
An network-on-chip (NoC)-based error correction apparatus capable of supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element, the apparatus comprising: an encoder configured to receive a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers); and a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data, wherein a t-bit adaptive error correction code having a variable error correction capability depending on the number of bits (n) of the received data is applied to the error correction circuit (where t denotes any natural number), wherein an orthogonal Latin square code (OLSC) scheme is used, wherein the encoder is a first exclusive OR gate having an input terminal where the k-bit flit is input, wherein the decoder includes at least one second exclusive OR gate configured to receive a part of bits of the k-bit flit and a check bit for error correction, and a majority voter configured to receive a signal output from the second exclusive OR gate and output a high-level value when a majority (exceeding a half) of bits of the received signal has a high level or output a low-level value when a majority (exceeding a half) of bits of the received signal has a low level.