Patent ID: 6908818

Claim:
A method of fabricating a contactless channel write/erase flash memory cell comprising: providing a multi-level substrate; forming a tunnel oxide layer on the multi-level substrate; forming a shallow P ion region in said multi-level substrate; forming a floating gate on said multi-level substrate; forming a deep P ion region on one side of said floating gate in said multi-level substrate; forming a first N ion doped region within said deep P ion region and a second N ion doped region on the other side of said floating gate in said multilevel substrate; simultaneously forming a first isolating oxide layer on said first N ion doped region and a second isolating oxide layer on said second N ion doped region; forming a dielectric layer on said floating gate, said first isolating oxide layer and second isolating oxide layer; forming a control gate over said floating gate over said floating gate; and forming at least one bit line metal contact away from any of the N ion doped region and the deep P ion region of the memory cell wherein said metal contact penetrates through said isolating oxide layer and junction between said N ion doped region and said deep P ion resign.