Patent ID: 8436400

Claim:
A semiconductor device, comprising: a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively; at least six linear shapes extending along a first reference direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first reference direction, wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including, (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor, (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that, (i) the first N and P transistors aligned along the first reference direction and electrically connected to each other through their gate defining shapes, (ii) the gate defining shapes of the second N and P transistors having extensions not electrically connected to each other, (iii) the gate defining shapes of the third N and P transistors having extensions not electrically connected to each other, and (iv) the fourth N and P transistors aligned along the first reference direction and electrically connected to each other through their gate defining shapes, (v) the gate defining shape of the second N-transistor only forming one or more N-transistor gate electrodes, (vi) the gate defining shape of the third N-transistor only forming one or more N-transistor gate electrodes, (vii) the gate defining shape of the second P-transistor only forming one or more P-transistor gate electrodes, (viii) the gate defining shape of the third P-transistor only forming one or more P-transistor gate electrodes, (ix) wherein at least two of the gate defining shapes of the second N-transistor, the third N-transistor, the second P-transistor, and the third P-transistor are electrically connected to each other, and (x) wherein at least two of the gate defining shapes of the second N-transistor, third N-transistor, second P-transistor, and third P-transistor have different lengths as measured in the first reference direction.