Patent ID: 8359457

Claim:
A semiconductor device comprising: a controller; and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in a manner of a pipeline, wherein (A) the controller inputs to a first one of the dynamically reconfigurable circuits: data that is to be processed, and reconfiguration information including identification information that identifies an item of circuit information used to constitute an execution circuit necessary for a computation executed on the data in the dynamically reconfigurable circuits, from among a plurality of items of circuit information held individually by the dynamically reconfigurable circuits, and information that indicates a number of times the computation is to be executed individually by the dynamically reconfigurable circuits, and (B) each of the dynamically reconfigurable circuits includes (a) a processing unit that, each time the reconfiguration information is input, is constituted by an execution circuit changed in accordance with the circuit information identified by the reconfiguration information that is input and that processes the data that is input by one of the controller, a previous one of the dynamically reconfigurable circuits, and the same one of the dynamically reconfigurable circuits, (b) an updating unit that, each time the reconfiguration information is input, updates identification information included in the reconfiguration information that is input to identification information that identifies the circuit information necessary for a computation that is to be subsequently executed on the processed data, and (c) a repetition controlling unit that determines whether the processing unit is to perform a repeat operation, wherein the repeat operation performs a control so that the processed data and new reconfiguration information that includes the identification information that is updated by the updating unit are input to a subsequent one of the dynamically reconfigurable circuits when the repetition controlling unit determines that the processing unit has completed the computation for the number of times included in the reconfiguration information that is input and that performs a control so that the processed data and the new reconfiguration information that includes the identification information that is updated by the updating unit are input to the same one of the dynamically reconfigurable circuits without being input to the subsequent one of the dynamically reconfigurable circuits when the repetition controlling unit determines that the processing unit has not yet completed the computation for the number of times included in the reconfiguration information that is input.