Patent ID: 7301797

Claim:
A method of operating a semiconductor integrated circuit including a SRAM block comprising: a plurality of flip-flop type SRAM cells each including a pair of output nodes and a pair of pull-down transistors that pull down respective output nodes; power supply lines for supplying power-supply potentials to the plurality of SRAM cells; and bit lines and word lines for writing volatile data into and reading the volatile data from the plurality of SRAM cells, the method comprising: storing non-volatile data in at least one of the plurality of SRAM cells by flowing a drain current in one of the pair of pull-down transistors of the at least one of the plurality of SRAM cells; and stopping and re-starting to supply the power-supply potentials to the plurality of SRAM cells, and then reading the non-volatile data stored in the at least one of the SRAM cells.