Patent ID: 8455316

Claim:
A method of manufacturing a vertical semiconductor device, the method comprising: implanting impurities into a single crystalline substrate to form a first impurity region; forming a sacrificial layer structure on an upper surface of the substrate, such that the sacrificial layer structure has holes exposing the first impurity region on the upper surface of the single crystalline substrate; forming inner spacers on side surfaces of the holes; vertically forming single crystalline active bodies in the holes on the upper surface of the single crystalline substrate, such that each of the single crystalline active bodies has a first active portion on the substrate and a second active portion on the first active portion and such that the first active portion has a first width smaller than a second width of the second active portion; forming a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate; forming a gate electrode on the gate insulating layer, such that the gate electrode has a linear shape surrounding the active bodies; and implanting impurities into the second active portion to form a second impurity region.