Patent ID: 6900089

Claim:
A method of fabricating a non-volatile memory device comprising the steps of: supplying a silicon substrate of a first conductivity type; fabricating an insulation layer having a window for exposing a predetermined area of the silicon substrate; fabricating a first conductive gate in a spacer shape, comprising a first dielectric layer on a side wall of the insulation layer within the window and under first conductive gate; etching back the insulation layer; fabricating a second conductive gate in a spacer shape on a side wall of the first conductive gate, comprising a second dielectric layer and facing the first conductive gate; the second dielectric layer being formed under the second conductive gate; fabricating first and second junction areas of a second conductive type overlapping with the first and the second conductive gates, respectively, wherein the first and second dielectric layers comprise oxide-nitride-oxide (ONO) layers.