Patent ID: 8112622

Claim:
A network chip comprising: a chaining port configured to perform an external loop-back function including a first security engine transmitting a frame of data through the chaining port and receiving the frame of data back through the chaining port; an external port configured to send and receive the frame of data to and from at least one provider device, the at least one provider device being external from the network chip; the first security engine associated with the chaining port, the first security engine being configured to execute a first addition operation to add an inner encryption layer to the frame in conjunction with the first security engine transmitting the frame of data and configured to perform a first removal operation to remove the inner encryption layer in conjunction with the first security engine receiving the frame of data; a second security engine associated with the external port, coupled to the first security engine, the second security engine being configured to perform a second addition operation to add an outer encryption layer to the frame when the external port sends the frame of data to the at least one provider device and configured to perform a second removal operation to remove the outer encryption layer when the external port receives the frame of data, wherein the first and second security engines are configured to sequentially operate on the frame of data to add or remove the inner encryption layer and the outer encryption layer; and control logic configured to cause the first security engine to: perform the first addition operation but not the first removal operation if the frame of data is to be transmitted by the external port to the at least one provider device; and perform the first removal operation but not the first addition operation if the frame of data was received by the external port from the at least one provider device.