Patent ID: 8106516

Claim:
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or chip-on-chip stack, comprising: a microchip including a switching element; a first solder bar electrically coupled to a first terminal of the switching element; and a second solder bar electrically coupled to a second terminal of the switching element; wherein: the first solder bar includes a first and second sublayer, the first and second sublayers having a different material composition from one another, and the first and second sublayers having substantially similar shape to one another, the second solder bar includes a third and fourth sublayer, the third and fourth sublayers having a different material composition from one another, and the third and fourth sublayers having substantially similar shape to one another, the first and second solder bars both form respective surfaces for soldering to a bonding surface, and the first and second solder bars both have a geometric configuration selected from the group consisting of a planar curvilinear configuration and a planar rectilinear configuration.