Patent ID: 7657673

Claim:
A data transfer control device comprising: first, second and third buffers; a buffer control device that controls reading processing from the first buffer and writing processing into the second buffer; and selectors for selecting the first through third buffers; wherein, when said reading processing and said writing processing have been finished, said buffer control device issues either a first command or a second command to said selector depending upon whether the third buffer does or does not store data, in a case in which the third buffer does not store data, the buffer control device issues the first command that corresponds to a command to perform switching-over between said second buffer and said first buffer, and in a case in which the third buffer stores data, the buffer control device issues the second command that corresponds to a command to perform switching-over between said third buffer and said first buffer, wherein said buffer control device comprises: a storage unit that has a write buffer effective flag that is set on when said writing processing into said second buffer is completed, a read buffer effective flag that is set off when said reading processing from said first buffer is completed, and an intermediate buffer effective flag that is set on when said third buffer stores data; and a buffer control circuit that controls states of the write buffer effective flag, the read buffer effective flag, and the intermediate buffer effective flag, wherein said selector issues, to said buffer control circuit, a command to invert the states of the buffer effective flags corresponding to two buffers to be subjected to switching-over processing among said first through third buffers when said switching-over processing is performed.