Patent ID: 8736242

Claim:
A buck circuit applicable to a power supply of a computer, the buck circuit comprising: a voltage input terminal to receive a voltage from an alternating current (AC) power source through a rectifier circuit of the power supply; a voltage output terminal to output a voltage to a transformer of the power supply; a first electronic switch comprising a first terminal connected to a first signal pin of a pulse width modulation (PWM) control chip, a second terminal, and a third terminal; a second electronic switch comprising a first terminal connected to a signal control terminal of the computer, a second terminal connected to the third terminal of the first electronic switch and also connected to the first terminal of the first electronic switch through a first resistor, and a third terminal grounded; a first field effect transistor (FET), wherein a gate of the first FET is connected to the second terminal of the first electronic switch and also grounded through a second resistor, a source of the first FET is grounded, a drain of the first FET is connected to the voltage output terminal through an inductor; a second FET, wherein a gate of the second FET is connected to a second signal pin of the PWM control chip, a drain of the second FET is connected to the voltage input terminal, a source of the second FET is connected to the drain of the first FET; and a third FET, wherein a gate of the third FET is connected to the first signal pin of the PWM control chip and also grounded through a third resistor, a drain of the third FET is connected to the drain of the first FET, a source of the third FET is grounded; wherein the signal control terminal of the computer outputs a high level signal in responding to the computer is powered on, and the signal control terminal of the computer outputs a low level signal in responding to the computer is power off; wherein the first electronic switch is turned on in responding to the third terminal of the first electronic switch receives a low level signal, and the first electronic switch is turned off in responding to the third terminal of the first electronic switch receives a high level signal; and wherein the second electronic switch is turned on in responding to the first terminal of the second electronic switch receives a high level signal, and the second electronic switch is turned off in responding to the first terminal of the second electronic switch receives a low level signal.