Patent ID: 6867997

Claim:
A memory device, comprising: a cell group comprising a plurality of ferroelectric memory cells connected to one another wherein the cell group comprises a first ferroelectric memory cell, a last ferroelectric memory cell, and at least one intermediate ferroelectric memory cell, the first, last, and intermediate ferroelectric memory cells being connected to one another with the at least one intermediate ferroelectric memory cell being connected between the first and last ferroelectric memory cells, and wherein the last ferroelectric memory cell is connected to a bitline; wherein the first ferroelectric memory cell comprises a first ferroelectric capacitor connected between a first source/drain terminal of a corresponding first transistor and a first plateline corresponding to a first data word, the first transistor comprising a second source/drain terminal connected to an intermediate ferroelectric memory cell and a gate terminal connected to a first wordline corresponding to a first data word; wherein each intermediate ferroelectric memory cell comprises an intermediate ferroelectric capacitor connected between a first source/drain terminal of a corresponding intermediate transistor and an intermediate plateline corresponding to an intermediate data word, the intermediate transistor comprising a second source/drain terminal connected to a subsequent ferroelectric memory cell and a gate terminal connected to an intermediate wordline corresponding to an intermediate data word; and wherein the last ferroelectric memory cell comprises a last ferroelectric capacitor connected between a first source/drain terminal of a corresponding last transistor and a last plateline corresponding to a last data word, the last transistor comprising a gate terminal connected to a last wordline corresponding to a last data word and a second source/drain terminal connected to the bitline.