Patent ID: 8278704

Claim:
A method of forming a FET, comprising: forming a trench in a silicon region; forming a shield electrode in a bottom portion of the trench, the shield electrode being insulated from adjacent silicon region by a shield dielectric; forming a nitride etch resistant layer extending over a surface of the silicon region adjacent the trench, along trench sidewalls, and over the shield electrode and the shield dielectric; forming a silicon nitride layer extending over the nitride etch resistant layer along the surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode and the shield dielectric; forming a layer of low temperature oxide (LTO) over the silicon nitride layer such that those portions of the LTO layer extending over the surface of the silicon region adjacent the trench are thicker than the portion of the LTO layer extending over the shield electrode; and uniformly etching back the LTO layer such that a portion of the silicon nitride layer extending over the shield electrode and along at least a portion of the trench sidewalls becomes exposed while portions of the silicon nitride layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the LTO layer.