Patent ID: 6946893

Claim:
A semiconductor integrated circuit comprising: a level shift stage including: a first input terminal to receive a first signal having a first amplitude; a second input terminal to receive a second signal in a phase reverse to the first signal and having the first amplitude; a first output terminal to supply a third signal having a second amplitude greater than the first amplitude and being in a phase reverse to the first signal; a second output terminal to supply a fourth signal having the second amplitude and being in a phase reverse to the second signal; a delay stage to receive the fourth signal and a fifth signal having the second amplitude and being in a phase reverse to the third signal and to output a delay signal of the fourth and fifth signals; and an output stage including: a first MOSFET of a first conductivity type to receive the fourth signal; a second MOSFET of a second conductivity type to receive the fifth signal; a third MOSFET of the first conductivity type to receive the delay signal, a drain of the third MOSFET being coupled to a source of the first MOSFET; a fourth MOSFET of the second conductivity type to receive the delay signal, a drain of the fourth MOSFET being coupled to a source of the second MOSFET.