Patent ID: 7602008

Claim:
A split-gate memory cell, comprising: first and second diffusion regions formed in a semiconductor substrate; a floating gate electrode formed on the semiconductor substrate between the first and second diffusion regions, wherein a first side of the floating gate electrode overlaps a portion of the first diffusion region; a control gate electrode formed on the semiconductor substrate between a second side of the floating gate electrode and the second diffusion region; a tunneling dielectric layer disposed between the control gate electrode and the second side of the floating gate electrode; a coupling gate electrode formed on the first diffusion region in the semiconductor substrate and adjacent to the first side of the floating gate electrode to overlap at least a portion of an upper surface of the floating gate electrode; and a coupling dielectric layer disposed between the coupling gate electrode and the first side of the floating gate electrode and between the coupling gate electrode and the portion of the upper surface of the floating gate electrode, wherein a thickness of the coupling dielectric layer is less than a thickness of the tunneling dielectric layer.