Patent ID: 7290107

Claim:
A computer system, comprising: a processor; a cache connected to the processor, wherein the cache is partitioned into a locking cache and a non-locking cache; a cache controller connected to the processor and the cache; a system bus connected to the cache; an I/O subsystem connected to the system bus; one or more address range registers that store a specified address range to access the locking cache such that the locking cache appears as additional system memory; wherein the I/O subsystem is configured to issue a store instruction to transfer data to the locking cache without also transferring it to system memory; wherein the cache controller is configured to determine whether the store instruction is within the specified address range for the locking cache and store the data in the locking cache if the store instruction is within the specified address range; wherein the locking cache is configured to retain the data until the data has been accessed for use; and wherein the I/O subsystem is configured to receive a signal, responsive to the data being loaded for use, indicating that the data in the locking cache can be overwritten.