Patent ID: 7759185

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a first stress film covering a first gate electrode and first source/drain areas of a first transistor area of a semiconductor substrate and at least a portion of a third gate electrode of an interface area between the first transistor area and a second transistor area; forming a second stress film covering a second gate electrode and second source/drain areas of the second transistor area of the semiconductor substrate and overlapping at least a portion of the first stress film on the third gate electrode of the interface area; forming an interlayer insulating film on the semiconductor substrate; patterning the interlayer insulating film to form a plurality of preliminary contact holes through which the first stress film on the first gate electrode and the first source/drain areas and the second stress film on the second and the third gate electrodes and the second source/drain areas are exposed; filling the plurality of preliminary contact holes with a filling material; removing the filling material to expose the second stress film in the interface area while the filling material remains in the preliminary contact holes of the first transistor area and the second transistor area; removing the exposed second stress film of the interface area; removing the remaining filling material to expose the first stress film of the first transistor area and the second stress film of the second transistor area; and removing the exposed first stress film and second stress film to form a plurality of contact holes through which the first, the second, and the third gate electrodes, and the first and the second source/drain areas are exposed.