Patent ID: 7534711

Claim:
A method for manufacturing an integrated circuit device, the method comprising: providing a substrate having a contact region, the contact region provided between a first word line and a second word line, the contact region having an overlying plug structure, the plug structure being provided within a thickness of a first dielectric layer, the first dielectric layer including a portion overlying the plug structure, the first dielectric layer having a planarized surface region; forming a first line and a second line and a space provided between the first word line and the second word line, the space being provided within a region overlying the plug structure; forming a plurality of spacers, the plurality of spacers including a first spacer overlaying the first line and a second spacer overlaying the second line, the first spacer being characterized by a width and a height; forming a second dielectric layer overlying the plurality of spacers; planarizing the second dielectric layer; forming a hard mask; patterning the hard mask to form a first exposed region; forming a thickness of spacer material; performing anisotropic etching the thickness of the spacer material to form a second exposed region within the first exposed region, the second exposed region being defined by a first sidewall spacer on a first edge of the first exposed region and a second sidewall spacer on a second edge of the first exposed region; performing an etching process within the second exposed region at a depth to form an opening, the etching process removing at least a portion of the dielectric layer; and forming a contact within the opening.