Patent ID: 8749269

Claim:
A CML to CMOS conversion circuit, comprising: a first differential unit, a second differential unit, and an output unit, the first differential unit comprises a first differential transistor M 1 and a second differential transistor M 2 , the second differential unit comprises a third differential transistor M 3 and a fourth differential transistor M 4 , the output unit comprises a series connection of a first inverter and a second inverter, the gate of the first differential transistor M 1 and the gate of the second differential transistor M 2 receive an input voltage, the source or drain of the first differential transistor M 1 is connected with the source or drain of the second differential transistor M 2 , the drain or source of the first differential transistor M 1 is connected with the drain or source of the third differential transistor M 3 , the drain or source of the second differential transistor M 2 is connected with the drain or source of the fourth differential transistor M 4 , the gate of the third differential transistor M 3 is connected with the gate of the fourth differential transistor M 4 , the gate of the third differential transistor is connected with its drain or source, the input terminal of the first inverter is connected with the drain or source of the second differential transistor M 2 , the source or drain of the third differential transistor M 3 and the source or drain of the fourth differential transistor M 4 are connected with a supply voltage, wherein, a resistor is connected with the first inverter in parallel.