Patent ID: 7666727

Claim:
A method of forming a transistor comprising: forming an opening in a dielectric film over a channel region in a semiconductor substrate, said opening having first and second laterally opposite sidewalls formed over a pair of source/drain regions formed in said semiconductor substrate; forming a gate dielectric over said semiconductor substrate at the bottom of said opening, said gate dielectric having a first outer region at the bottom of said opening, a second outer region at the bottom of said opening, and a central region, between said first and second outer regions, at the bottom of said opening; depositing a first conductive material having a first work function at a first angle onto said first outer region at the bottom of said opening, but not onto said second outer region at the bottom of said opening and not onto said central region at the bottom of said opening, of said gate dielectric, and adjacent to said first sidewall of said opening to form a first outer portion of a gate electrode, said first outer portion of said gate electrode having a sidewall region and an extension region; depositing said first conductive material at a second angle onto said second outer region at the bottom of said opening, but not onto said first outer region at the bottom of said opening and not onto said central region at the bottom of said opening, of said gate dielectric, and adjacent to said second laterally opposite sidewall to form a second outer portion of said gate electrode, said second outer portion of said gate electrode having a sidewall region and an extension region; and, subsequently, depositing a second conductive material having a second work function into said opening, onto said central region of said gate dielectric at the bottom of said opening, and over said channel region and above said extension regions of said outer portions of said gate electrode, to form a central portion of said gate electrode.