Patent ID: 7778267

Claim:
A bus system including a plurality of data sources having a plurality of data bits, a common data transmission path coupling the plurality of data sources with a data sink, the bus system comprising: M interconnections, wherein M is a positive integer greater than or equal to 2; and N bus cells, wherein N is a positive integer greater than or equal to 2, coupling the data sources and the interconnections; wherein each of the bus cells is connected to a corresponding one of the data sources and includes a logic circuit to selectively provide data bits from the data sources to the interconnections, wherein each of the bus cells includes a bit connection circuit to selectively transfer the data bits to the interconnections, and each of the bit connection circuits comprises: an AND gate, having a first input and a second input, the first input comprising one of the data bits, the second input comprising a selection signal for selecting one of the data sources, the AND gate generating a logical output in response to the one of the data bits and the selection signal that selects one of the data sources; and an OR gate for generating a logical output in response to the output of the AND gate and a prior-stage output, the output from the OR gate being an output of the bus cell corresponding to the selected one of the data sources.