Patent ID: 6883166

Claim:
An apparatus for performing correctness checks, the apparatus comprising: logic configured to receive a first set of instructions comprising one or more conditional code sequences that when executed direct one or more correctness checks; logic configured to generate an initial instruction schedule and a conditional instruction stream from the first set of instructions, such that the initial instruction schedule is devoid of said conditional code sequences and such that the conditional code sequences of the conditional instruction stream are associated with a corresponding set of one or more instructions in the initial instruction schedule; logic configured to evaluate the initial instruction schedule to determine whether the initial instruction schedule includes spare instruction slots into which said conditional code sequences can be inserted into the initial instruction schedule such that a final instruction schedule would not require a longer run time than the initial instruction schedule; and logic configured to generate the final instruction schedule responsive to the initial instruction schedule, the conditional instruction stream, and the logic configured to evaluate such that identified conditional code sequences are inserted into spare instruction slots.