Patent ID: 7685366

Claim:
A computer readable storage medium including code, wherein a first storage unit is coupled to a second storage unit, wherein the code in response to being executed by a processor is capable of causing operations, the operations comprising: detecting the first storage unit and the second storage unit, wherein an address bus and a data bus couples the first storage unit to the second storage unit, wherein the first and second storage units comprise a plurality of address testers and a plurality of cache lines, and wherein those cache lines of the plurality of cache lines that are included in the first storage unit perform operations faster in comparison to those cache lines of the plurality of cache lines that are included in the second storage unit; determining that the first storage unit is capable of responding to a write operation faster than the second storage unit, and that the second storage unit is capable of responding to a read operation at least as fast as the first storage unit; writing data to the first storage unit; loading an address corresponding to the data in the address bus; loading the data in the data bus; transferring the address and the data via the address bus and the data bus from the first storage unit to the second storage unit by: (i) moving the address from a first cache line in the first storage unit to a second cache line in the second storage unit; (ii) moving the data from the first cache line in the first storage unit to the second cache line in the second storage unit; and (iii) deleting the data in the first cache line, wherein the data is periodically moved from the first storage unit to the second storage unit, wherein the first storage unit is more expensive to manufacture than the second storage unit; and reading the data from the second storage unit, in response to a read request directed at both the first and the second storage units, wherein the first storage unit and the second storage unit comprise a cache that is capable of coupling a processor to a main memory, wherein the first storage unit in the cache has a direct connection to the main memory, wherein the second storage unit in the cache has no direct connection to the main memory, wherein the first and second storage units comprise one cache level, wherein the operations further comprise moving the data from the cache to the main memory, and reading the data from the main memory in response to a read miss from the cache.