Patent ID: 8166281

Claim:
A method for processing instruction code, comprising: processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification, the non-contiguous register specifier including a first set of contiguous bits and a second set of contiguous bits which collectively identify a single register, the first set of contiguous bits and the second set of contiguous bits being non-contiguous with respect to each other; performing an initial dependency analysis relating to the non-contiguous register specifier by comparing a subset of bits of the non-contiguous register specifier to a portion of another register specifier of another instruction, wherein the subset of bits includes only bits from the first set of contiguous bits, and none of the bits from the second set of contiguous bits; wherein the fixed-width instruction includes the non-contiguous register specifier, wherein the non-contiguous register specifier includes at least the first set of contiguous bits and the second set of contiguous bits separated by at least one bit not part of the non-contiguous register specifier, and wherein the first set of contiguous bits is specified directly by an instruction field included in the fixed-width instruction, the second set of contiguous bits is specified using a deep encoding, and the method further comprises generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than m, and said generating step generates the set of n bits using a logic function decoding a plurality of extended opcodes, the plurality of extended opcodes indicating the use of a specific bit string as an extended register specifier.