Patent ID: 6965146

Claim:
A self-aligned planar DMOS transistor structure, comprising: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a lightly-doped epitaxial semiconductor layer being formed on a heavily-doped semiconductor substrate; a source region being formed in the lightly-doped epitaxial semiconductor layer surrounded by a planar gate region, wherein the source region comprises a body diffusion region of a second conductivity type being formed in the lightly-doped epitaxial semiconductor layer through a patterned window, a self-aligned heavily-doped contact diffusion region of the second conductivity type being formed in a middle surface portion of the body diffusion region through a first self-aligned implantation window surrounded by a first sacrificial dielectric spacer, a self-aligned heavily-doped source diffusion ring of the first conductivity type being formed in a surface portion of the body diffusion region and on an extended side surface portion of the self-aligned heavily-doped contact diffusion region through a second self-aligned implantation window formed between a self-aligned implantation masking layer surrounded by the first sacrificial dielectric spacer and a protection dielectric layer being formed over a sidewall of the planar gate region, and a self-aligned contact window being formed on a surface portion of the self-aligned heavily-doped contact diffusion region surrounded by the self-aligned heavily-doped source diffusion ring and the self-aligned heavily-doped source diffusion ring surrounded by a sidewall dielectric spacer being formed over a sidewall of the protection dielectric layer; the planar gate region being formed on the lightly-doped epitaxial semiconductor layer, wherein the planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer, self-aligned metal silicide layers being formed on the patterned heavily-doped polycrystalline-silicon gate layer through gaps formed by patterned capping dielectric layers, and refilled dielectric layers being formed on the self-aligned metal silicide layers; and a source metal layer being at least formed on the self-aligned source contact window.