Patent ID: 8216484

Claim:
A method for fabricating a capacitor, the method comprising: forming a first storage node (SN) oxide layer over a substrate,; forming a second SN oxide layer over the first SN oxide layer; forming a mask pattern over the second SN oxide layer; dry-etching the first and the second SN oxide layers using the mask pattern as an etch barrier to form a capacitor region; and wet-etching a resultant structure including the capacitor region to form a final capacitor region having an enlarged bottom width, wherein the first SN oxide layer comprises one portion of having a first impurity concentration and the other portion having a good impurity concentration, one portion corresponding to a region where the final capacitor region is to be formed, and the first impurity concentration is greater than the second impurity concentration, wherein the forming of the first SN oxide layer comprises: forming a first oxide layer of low concentration over the substrate; patterning the first oxide layer through a mask and an etch processes to form a hole in a region where a capacitor region is to be formed: filling the hole with a second oxide layer of high concentration: and performing a heat on the second oxide layer to diffuse high-concentration impurities of the second oxide layer into the first oxide layer thereby forming the one portion of high impurity concentration at sidewalls of the first oxide layer.