Patent ID: 7211448

Claim:
A semiconductor device manufacturing method comprising steps of: (a) forming a first film of insulating material on a first surface defined on a substrate, the substrate having a surface layer portion made of insulating material and formed with a wiring groove filled with a wiring line of conductive material, an upper surface of the wiring line being exposed on the first surface, the wiring line being electrically connected to a conductive member, and the conductive member occupying an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface; (b) forming a via hole through the first film, the via hole being formed so that a boundary between the wiring line and the surface layer portion of insulating material passes through the inside of the via hole as viewed along a line parallel to the normal to the first surface; and (c) observing a bottom of the via hole with an apparatus for obtaining image information by utilizing secondary electrons and reflection electrons from a specimen, to judge whether a state of the bottom of the via hole is accepted or rejected.