Patent ID: 7999298

Claim:
An embedded memory cell comprising: a semiconducting substrate; a transistor having a source/drain region at least partially embedded in the semiconducting substrate; and a capacitor at least partially embedded in the semiconducting substrate, the capacitor comprising a first electrode and a second electrode that are electrically isolated from each other by a first electrically insulating material, wherein: the first electrode is electrically connected to the semiconducting substrate; the second electrode is electrically connected to the source/drain region of the transistor; if the semiconducting substrate has a p-type doping then the first electrode comprises a metal having a work function of at least 5 electron volts, and if the semiconducting substrate has an n-type doping then the first electrode comprises a metal having a work function no greater than 3.2 electron volts; and if the source/drain region has a p-type doping then the second electrode comprises a metal having a work function of at least 5 electron volts, and if the source/drain region has an n-type doping then the second electrode comprises a metal having a work function no greater than 3.2 electron volts.