Patent ID: 7211483

Claim:
A method of fabricating a memory device with vertical transistors and trench capacitors, comprising: providing a substrate; forming at least one deep trench in the substrate; forming a trench capacitor in a lower position of the deep trench; forming a ring shaped insulator on the sidewall of the deep trench above the trench capacitor, wherein a space is surrounded by the ring shaped insulator; forming a first conductive layer to fill the space; forming a diffusion barrier on one side of the sidewall of the deep trench above the ring shaped insulator; forming a nitride layer in the sidewall of the deep trench without the diffusion barrier formed thereon, to serve as a buried strap interface; forming a second conductive layer on the first conductive layer and the ring shaped insulator and beside the diffusion barrier; forming a trench top isolation on the second conductive layer and the diffusion barrier; and forming a control gate on the trench top isolation.