Patent ID: 8558310

Claim:
An integrated circuit (IC), comprising: a substrate having a semiconductor surface; at least one PMOS transistor formed in said substrate, comprising: a gate structure including a gate electrode on a gate dielectric formed over said semiconductor surface; source/drain regions formed in said semiconductor surface on both sides of said gate structure, and source/drain extension regions formed on both sides of said gate structure including co-doping comprising indium, carbon and a halogen each having minimum peak concentrations of 1×10 16 /cm 3 , wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions; and wherein said at least one PMOS transistor includes at least one core PMOS transistor and at least one non-core PMOS transistor, wherein said indium, said halogen and said carbon are in said source/drain extension regions for said core PMOS transistor and at least one of said indium, said halogen and said carbon are not in said source/drain extension regions of said non-core PMOS transistor.