Patent ID: 8069339

Claim:
A microprocessor having a microarchitectural instruction set, the microprocessor comprising: a first register, having a plurality of condition code flags, wherein the first register is an architectural register of the microprocessor; a second register, having simultaneously the plurality of condition code flags of the first register, wherein the second register is a non-architectural register of the microprocessor; a first instruction of the microarchitectural instruction set, wherein the first instruction instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction, wherein the first instruction includes a field for indicating whether to update the plurality of condition code flags of the first register or of the second register; and a second instruction of the microarchitectural instruction set, wherein the second instruction instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags, wherein the second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the first register or of the second register to determine whether to perform the operation.