Patent ID: 8294149

Claim:
A semiconductor structure comprising: a plurality of conductive through vias located in a substrate, wherein said plurality of conductive through vias extends from a first planar surface located on one side of said substrate to a second planar surface located on an opposite side of said substrate which opposes said first planar surface, and said second planar surface includes top surfaces of said plurality of conductive through vias and a surface of said substrate, said surface of said substrate comprising an insulator material or a semiconductor material and laterally surrounding said top surfaces of said plurality of conductive through vias; a peripheral test structure layer including test circuits and located outside of said substrate and contacting said first planar surface and containing peripheral test structures; at least one functional layer located on said peripheral test structure layer, more proximal to said first planar surface than to said second planar surface, and containing at least one functional semiconductor circuit; and an array of Controlled Collapse Chip Connection (C 4 ) balls located on, and bonded to, said top surfaces of said plurality of conductive through vias.