Patent ID: 7511996

Claim:
A method for minimizing program disturb in NAND string having a selected memory cell, upper memory cells between the selected memory cell and a bitline, lower memory cells between the selected memory cell and a sourceline, and a string select transistor for coupling the memory cells to the bitline, comprising: a) in a first time period, coupling a voltage level corresponding to program inhibit voltage from the bitline to the NAND string; b) in a second time period following the first time period, precharging channels of the selected memory cell and the upper memory cells to a primary boosted voltage level after the voltage level is coupled to the channel of the NAND string by driving a selected wordline connected to the selected memory cell and upper wordlines connected to the upper memory cells to a first pass voltage level, and driving lower wordlines connected to the lower memory cells to a second pass voltage, the second pass voltage being less than the first pass voltage; and, c) in a third time period following the second time period, locally boosting the selected memory cell channel to a secondary boosted voltage level after the channel is precharged, the secondary boosted voltage level being higher than the primary boosted voltage level by driving the selected wordline connected to the selected memory cell to a programming voltage level, and electrically turning off an upper memory cell adjacent to the selected memory cell.