Patent ID: 8201115

Claim:
A method for reducing the size of a logic network design on a data processing system, prior to verification of the logic network design, utilizing a resubstitution the method comprising: the data processing system receiving a logic network having a plurality of registers; associating the logic network with one or more invariants, wherein the invariants provide information about one or more reachable states of the logic network design; dynamically selecting, from among the plurality of registers, a relevant register of a Boolean function basis set; determining if one or more resubstitutions of the selected relevant register exist, wherein the resubstitutions are Boolean function resubstitutions and are compatible resubstitutions that express the selected relevant register as at least one pre-existing register of fixed initial state; in response to determining the existence of one or more resubstitutions, refining the one or more resubstitutions utilizing the one or more invariants; re-expressing the selected relevant register using the one or more resubstitutions; and the data processing system generating a reduced size logic network design utilizing the one or more resubstitutions.