Patent ID: 8823059

Claim:
A semiconductor device, comprising: a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, and further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also partially disposed in the bottom barrier layer and completely exposing the channel region; and a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising: a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and a gate electrode disposed on the second dielectric layer.