Patent ID: 8700951

Claim:
A solid-state storage subsystem comprising: a non-volatile memory array; a controller configured to implement a data redundancy configuration with a plurality of data stripes in the non-volatile memory array, wherein each of the plurality of data stripes is of a pre-defined stripe size comprising a pre-defined number of data elements and wherein the controller is configured to write parity data to the non-volatile memory array for a data stripe in the non-volatile memory array that has reached the pre-defined strip size; and a volatile memory for temporarily storing: data to be written to the non-volatile memory array; and parity data associated with partial data stripes in the non-volatile memory that have not yet reached the pre-defined stripe size; wherein the controller is further configured to: detect (1) an occurrence of a data access error in one of the plurality of data stripes for which parity data has not been written to the non-volatile memory array or (2) a power failure of the solid-state storage subsystem; and in response to detecting the occurrence of data access error or power failure, write to the non-volatile memory array (1) metadata indicating validity of one or more data elements in a partial data stripe associated with the parity data and (2) the parity data for the partial data stripe, whereby the metadata enables a delay of a re-writing of the partial data stripe into a full data stripe of the pre-defined size.