Patent ID: 7613942

Claim:
A method comprising: constructing a first weighted directed acyclic graph representing a zero short-circuit current requirement of a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit comprising a plurality of logic cells, the first weighted directed acyclic graph comprising one or more first vertices and one or more first edges, each first vertex corresponding to one of the logic cells, each first edge linking two first vertices to each other; assigning to each of one or more of the first edges one or more first weights based on a settling time of a logic cell corresponding to a vertex linked by the first edge; constructing a second weighted directed acyclic graph comprising one or more second vertices and one or more second edges, each second vertex corresponding to a logic cluster comprising one or more of the logic cells; assigning to each of one or more of the second edges second weights based on the first weights; determining third weights based at least in part on the second weights; applying the third weights to the second edges; determining a minimum weighted directed Hamiltonian path on the second directed acyclic graph with the third weights applied to the second edges; based at least in part on the determined minimum weighted directed Hamiltonian path: clustering the logic cells into a new clustering; and setting wake-up times of logic clusters in the new clustering to reduce a total turn-on time of the circuit while keeping below a predetermined threshold a first sum of first currents flowing from the circuit to ground, a second sum of second currents flowing from a supply voltage to the circuit, or both during a transition by the circuit from sleep mode to active mode.