Patent ID: 7554551

Claim:
A memory architecture that decouples a color buffer from a main memory in a computer, the architecture comprising: a sole memory controller connected to the main memory to manage use of the main memory between a graphics subsystem and a processing unit, the memory controller operable for partitioning an address space for the color buffer into two logical buffers, operable for designating one logical buffer as a frame-preparation memory and one logical buffer as a refresh memory, operable for connecting the frame-preparation memory to the graphics subsystem and operable for connecting the refresh memory to a display device, wherein a full frame of color data is written into the frame-preparation memory at a frame rate, read from the refresh memory at a rate that supports a refresh rate of the display device, the frame-preparation memory having a bandwidth that supports the refresh rate, the frame-preparation memory is mapped into a physical device for the main memory and the address space for the refresh memory is mapped into a physical memory device for a dedicated memory that is separate from the physical memory device for the main memory.