Patent ID: 7719806

Claim:
An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising: a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD; a diode having an anode and a cathode, wherein the cathode is coupled to the node; and two or more PMOS transistors arranged in series, the two or more PMOS transistors comprising at least a first PMOS transistor and a second PMOS transistor, the first PMOS transistor having a drain, a gate, and a source, the second PMOS transistor having a drain, a gate, and a source, wherein the drain of the first PMOS transistor is coupled to the anode of the diode, wherein the source of the second PMOS transistor is coupled to a first voltage reference terminal, wherein the source of the first PMOS transistor is coupled, directly or indirectly, to the drain of the second PMOS transistor, and wherein the gates of the PMOS transistors are coupled to voltage reference(s) so that at least one of the PMOS transistors is “off” when voltage at the node is less than voltage at the first voltage reference terminal.