Patent ID: 8638574

Claim:
A semiconductor control device for a switching regulator that has a switching element connected in series to a primary winding of a flyback transformer and connects a secondary winding of the flyback transformer to an external load, the semiconductor control device driving the switching element and comprising: a current detection signal input terminal that receives a signal of detected current flowing in the switching element; a feedback signal input terminal that receives a feedback signal of detecting a loading condition of the secondary winding; a driving signal output terminal that delivers a signal for driving the switching element; a voltage adjusting circuit that connects an output terminal of an auxiliary winding of the flyback transformer, the auxiliary winding having a polarity opposite to the primary winding, to the current detection signal input terminal during an OFF period of the switching element; an oscillator circuit that is connected to the feedback signal input terminal; a one-shot circuit that generates a one-shot pulse based on an output voltage from the oscillator circuit; an RS flip-flop circuit that generates a driving signal to be delivered to the driving signal output terminal; and a bottom detection section that receives a one-shot signal from the one-shot circuit, the signal delivered to the current detection signal input terminal, and an output signal from the RS flip-flop circuit, and sets the RS flip-flop circuit based on the one-shot signal or a bottom detection signal of detecting a bottom of the signal delivered to the current detection signal input terminal during the OFF period of the switching element; wherein the bottom detection section comprises: a pull-down circuit that pulls down the current detection signal input terminal upon receiving the output signal from the RS flip-flop circuit; a hysteresis comparator that is connected to the current detection signal input terminal; a counter that is counted up every time a comparison output signal from the hysteresis comparator is delivered and is reset upon setting of the RS flip-flop circuit; a second RS flip-flop circuit that is set at a predetermined count value of the counter and reset upon setting of the RS flip-flop circuit; an AND gate that receives the comparison output signal from the hysteresis comparator and an output signal from the second RS flip-flop circuit; a bottom detection circuit that delivers a one-shot signal upon change of an output signal from the AND gate from a high level to a low level; a gate circuit that passes the one-shot signal from the one-shot circuit through the gate circuit corresponding to a condition of the output signal from the AND gate at the low level; and an OR gate that delivers a set signal to the RS flip-flop circuit, the set signal being a logical sum signal of an output signal from the bottom detection circuit and an output signal from the gate circuit.