Patent ID: 7492400

Claim:
An image sensor embodying a folded multiple capture architecture comprising: a multi-bit analog-digital convertor (ADC) stage shared by a plurality of pixels; a digital-signal-processor/controller (DSPC) stage coupled to said ADC stage; and a per-pixel analog-front-end (AFE) coupled to said ADC and said DSPC; wherein said AFE having an integrator that integrates photocurrent i ph received from a photodetector and outputs a corresponding digital value v(t) to said ADC; and a comparator coupled to said integrator for periodically comparing said digital value v(t) with a threshold value V th synchronous with a clock signal; wherein said comparator produces a 1 and resets said integrator every time said digital value v(t) is above said threshold value V th ; and wherein said comparator produces a 0 every time said digital value v(t) is not above said threshold value V th , thereby generating a binary reset sequence; wherein said ADC globally captures said digital value v(t) multiple times; and wherein based on outputs received from said AFE and said ADC, said DSPC estimates reset periods and effective integration times for each pixel coupled thereto, sorts captured values, detects anomalies, and estimates photocurrent.