Patent ID: 6924199

Claim:
A method to form a transistor gate in the manufacture of an integrated circuit device, said method comprising: providing a substrate; forming a conductor layer overlying said substrate with a dielectric layer therebetween; forming a masking layer overlying said conductor layer; forming a resist layer overlying said masking layer; patterning said resist layer to thereby selectively expose said masking layer wherein said resist layer exhibits a first spacing between edges of said resist layer; etching through said exposed masking layer to thereby selectively expose said conductor layer wherein etched edges of said masking layer are tapered and the angle of the edges of said masking layer with respect to the top surface of said substrate is between about 45° and about 85° such that said masking layer exhibits a second spacing between said masking layer edges at the top surface of said conductor layer and wherein said second spacing is less than said first spacing; and etching through said exposed conductor layer to thereby complete a transistor gate.