Patent ID: 8847621

Claim:
A method for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits, the method comprising: generating a primary logic output from a primary logic gate in response to an input; generating a redundant logic output from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present; outputting an interleaved C-gate output from an interleaved C-gate that emulates an inverter output when the primary logic output matches the redundant logic output, and does not change output when the primary logic output and the redundant logic output do not match during the SEE; and maintaining the interleaved C-gate output of the interleaved C-gate using a hardened keeper cell comprising a set of two hardened complementary keeper subcircuits interleaved to provide a spatial separation and together comprising two sets of two series PMOS transistors and two sets of two series NMOS transistors.