Patent ID: 8094477

Claim:
A semiconductor storage device comprising: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; a control circuit selectively driving the first and second wirings; and a plurality of first wiring groups each comprising a certain number of the first wirings, the control circuit applying a first voltage to a selected first wiring and applying a second voltage to a selected second wiring to apply a certain potential difference to a selected memory cell positioned at a intersection between the selected first wiring and the selected second wiring, and bringing at least one of nonselected first wirings into a floating state, in the first wiring group including the selected first wiring, the control circuit applying the first voltage to the selected first wiring and applying the second voltage to the nonselected first wirings, in the first wiring groups not including the selected first wiring and adjacent to a first wiring group including the selected first wiring, the control circuit applying the second voltage to the first wirings, in the first wiring groups not including the selected first wiring and not adjacent to a first wiring group including the selected first wiring, the control circuit bringing the first wirings into the floating state.