Patent ID: 8536914

Claim:
A delay locked loop (DLL) comprising: a phase detection circuit configured to generate a phase detection signal by comparing a phase of an output clock signal with a phase of an external clock signal; a delay control circuit configured to generate a delay control signal for determining delay time in response to the phase detection signal; a 2-phase delay line configured to generate first and second delay clock signals having different phase shifts by delaying the external clock signal by as much as first and second set phases in response to the delay control signal; and a duty correction circuit configured to perform duty correction such that a duty cycle of the output clock signal has a set duty ratio by using the first and second delay clock signals, wherein the duty correction circuit includes: a first pulse generator configured to generate a first pulse signal synchronized with a rising edge of the first delay clock signal, a second pulse generator configured to a second pulse signal synchronized with a rising edge of the second delay clock signal, and a latch configured to output the output clock signal having the set duty ratio by using the first and second pulse signals.