Patent ID: 8310871

Claim:
A nonvolatile semiconductor memory device comprising: first and second bit lines; first and second word lines; first and second select transistors; a source line; a plurality of memory cells including first, second and third memory cells, each memory cell capable of storing n bits of data (n is a natural number equal to or larger than two), the first memory cell connected to the first word line, coupled to the first bit line and coupled to the source line via the first select transistor, the second memory cell being adjacent to the first memory cell along the first word line, connected to the first word line, coupled to the second bit line and coupled to the source line via the second select transistor, the third memory cell connected to the second word line, coupled to the first bit line and coupled to the source line via the first select transistor and the first memory cell, a source of the third memory cell connected to a drain of the first memory cell; and a write circuit configured to write a first bit of data into the first memory cell, write a second bit of data into the second memory cell, and write a third bit of data into the third memory cell, before writing a fourth bit of data into the first memory cell without erasing the first bit of data in the first memory cell, wherein: the write circuit is configured to write the first bit of data into the first memory cell by altering a threshold voltage of the first memory cell from a first voltage to a second voltage according to a first logical state of the first bit of data; the write circuit is configured to write the fourth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the second voltage to a third voltage according to a first logical state of the fourth bit of data; and the write circuit is configured to write the fourth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the second voltage to a fourth voltage higher than the third voltage according to a second logical state of the fourth bit of data.