Patent ID: 7663922

Claim:
A non-volatile semiconductor memory device, comprising: a page buffer comprising a lower latch block and an upper latch block; and a memory array connected to the lower latch block via a lower common bit line and connected to the upper latch block via an upper common bit line, the memory array comprising: at least first and second strings of non-volatile memory cells, each of the non-volatile memory cells in the first and second strings having i-levels of threshold voltages, wherein the first string is connectable to the lower common bit line and the second string is connectable to the upper common bit line and wherein i is not a power of two, and i is an integer equal to or greater than 5; a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that is configured to electrically connect the lower even bit line to the upper even bit line in response to a first connection control signal, a second switch that is configured to electrically connect the lower odd bit line to the upper odd bit line in response to a second connection control signal, and a voltage control block that is connected to one of the lower even bit line and the upper even bit line to precharge and discharge the lower and the upper even bit lines and is connected to one of the lower odd bit line and the upper odd bit line to precharge and discharge the lower and the upper odd bit lines, wherein the lower and the upper even bit lines are electrically connected by the first switch when the voltage control block precharges and discharges the one of the upper and the lower even bit lines and the lower and the upper odd bit lines are electrically connected by the second switch when the voltage control block precharges and discharges the one of the upper and the lower odd bit lines.