Patent ID: 8473794

Claim:
An integrated circuit, comprising: A. double data rate circuitry having a TMS/TDI input lead, a TCK input lead, a TDI output lead, and a TMS output lead, the double data rate circuitry including: i. a first TDI flip-flop having an input connected to the TMS/TDI input lead, a non-inverting clock input connected with the TCK input lead, and a TDI output; ii. a first TMS flip-flop having an input connected to the TMS/TDI input lead, an inverting clock input connected with the TCK input lead, and a TMS output; iii. a TDI update flip-flop having an input connected to the TDI output of the first TDI flip-flop, a non-inverting input connected to the TCK input lead, and an output; and iv. a TMS update flip-flop having an input connected to the TMS output of the first TMS flip-flop, a non-inverting input connected to the TCK input lead, and an output; v. a second TDI flip-flop having an input connected to the output of the TDI update flip-flop, an inverting clock input connected with the TCK input lead, and a TDI output connected with the TDI output lead; and vi. a second TMS flip-flop having an input connected to the output of the TMS update flip-flop, an inverting clock input connected with the TCK input lead, and a TMS output connected with the TMS output lead; and B. test access port circuitry having a TDI input coupled to the TDI output lead, a TMS input coupled to the TMS output lead, and a TCK input coupled to the TCK input lead.