Patent ID: 8614659

Claim:
A display device comprising: a first substrate and a second substrate; a plurality of pixel sections provided on the first substrate, opposing electrodes opposed to the pixel electrodes, switching elements for supplying a video signal to the pixel electrodes; a video signal line for supplying a video signal to the switching elements; a gray-level-voltage output circuit configured to output a video signal to the video signal line according to display data; and a scanning signal line for supplying a scanning signal for controlling the switching elements; wherein the pixel electrodes includes: a first pixel electrode; and a second pixel electrode different in area from the first pixel electrode; and the gray-level-voltage output circuit includes: a first group of holding circuits configured to hold a first bit and a second bit data of the display data corresponding to a video signal supplied to the first pixel electrode; a second group of holding circuits configured to hold third bit and a fourth bit data of the display data corresponding to a video signal supplied to the second pixel electrode, and a gray-level voltage generating circuit configured to generate four gray-level voltages, wherein the first group of holding circuits and the second group of holding circuits are arranged to extend along the direction of extension of the video signal line, the first group of holding circuits includes a first holding circuit and a second holding circuit, the second group of holding circuits includes a third holding circuit and a fourth holding circuit, a first common bit data line electrically connects with the first holding circuit and the third holding circuit, a second common bit data line electrically connects with the second holding circuit and the fourth holding circuit, wherein an area ratio of the first pixel electrode to the second pixel electrode is 1:4, wherein the gray-level voltage generating circuit is configured to output one of the four gray-level voltages according to the bit data held in the first group of holding circuits, and output one of the four gray-level voltages according to the bit data held in the second group of holding circuits, the first common bit data line electrically connects with the gray level voltage generating circuit, and the second common bit data line electrically connects with the gray level voltage generating circuit.