Patent ID: 6975014

Claim:
An FDSOI device comprising: a bulk semiconductor substrate having a top surface, a buried oxide layer atop said top surface of said substrate and a thin undoped SOI silicon layer atop said buried oxide layer thereon, said buried oxide layer having a thickness in the range between 50 and 60 nm, and said SOI silicon layer having a top surface and having a thickness in the range between 5 and 20 nm; a doped gate poly feature on said top surface of said SOI silicon layer, said doped gate poly feature having a length in the range between 40 and 75 nm, said doped gate poly feature having outer sidewalls, said doped gate tapered polysilicon features each having a base and a top, each said base being wider than said top, each said tapered polysilicon feature having a tapered surface connecting said poly feature comprising a first and a second tapered polysilicon feature having a gap therebetween, said first and second base to said top opposite said outer sidewalls, said tapered surfaces being at an angle with respect to said top surface of said bulk substrate, said gap having a bottom edge, said bottom edge of said gap being a portion of said top surface of said SOI silicon layer and said bottom edge of said gap having a length; said doped gate poly feature has a pair of extension implanted regions in said SOI silicon layer, said extension implanted regions extending under said first and second tapered polysilicon features; said doped gate poly feature has a pair of dielectric spacers abutting said gate poly feature outer sidewalls, said dielectric spacers having a top and a bottom; and source/drain implanted regions in said SOI silicon layer, said source/drain implanted regions extending under said dielectric spacers.