Patent ID: 8907687

Claim:
An integrated circuit device, comprising: at least one test device; an external stress voltage terminal coupled to the at least one test device wherein the at least one test device comprises a test transistor and the external stress voltage terminal is coupled to a gate of the test transistor; an external device terminal coupled to a drain of the test transistor; a stress transistor having source and drain terminals coupled between the external stress voltage terminal and the gate of the test transistor; an external sense terminal coupled to the gate of the test transistor; a swap transistor having source and drain terminals coupled between the external sense terminal and the gate of the test transistor; an external swap terminal coupled to a gate of the swap transistor; and a stress generator operable to connect an external stress voltage signal received on the stress voltage terminal to the at least one test device to cycle the at least one test device and generate an AC stress on the at least one test device.