Patent ID: 8238275

Claim:
A circuit comprising: a processing module including: a processing core; and a first processing module millimeter wave (MMW) transceiver coupled to the processing core; a second processing module MMW transceiver for processing requests from a plurality of peripheral components; a main memory including: memory; and a first memory MMW transceiver coupled to the memory, wherein at least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver using a first channel of a plurality of channels; and a second memory MMW transceiver for processing memory requests from the plurality of peripheral components; and the plurality of peripheral components, wherein each of the plurality of peripheral components comprises a peripheral MMW transceiver such that the peripheral MMW transceiver for each one of the plurality of peripheral components conveys the processing requests to the processing core via the second processing module MMW transceiver using a second channel of the plurality of channels and conveys the memory requests to the main memory via the second memory MMW transceiver using a third channel of the plurality of channels.