Patent ID: 8319522

Claim:
A data transfer circuit comprising: plural transfer lines operable to transfer data; plural data output units each connected to an end portion of a respective transfer line, the plural data output units operable to detect and output data transferred through the transfer lines with drive performance based on a control signal; plural data transmission units arranged in parallel and operable to transfer data to one or more of the transfer lines in response to selection signals; a selection control unit operable to generate selection signals and output the selection signals to the corresponding data transmission units; and a control unit operable to (i) generate the control signal to control drive performance of the data output units and adjust data transfer delay, and (ii) output the control signal to the respective output units, wherein, the transfer lines are arranged in the arrangement direction parallel to the data transmission units and connected to the corresponding data output units arranged in the direction, the control unit is operable to generate the control signal to adjust the drive performance based on a length of the data transfer distance from the data transmission units to the data output units on the transfer lines, each data output unit includes (i) an amplification unit operable to amplify input data transferred through the data transfer line, and (ii) a feedback unit operable to feed back data amplified at the amplification unit to the transfer line, the feedback unit operable to feed back the amplified data to the transfer line by a feedback amount in accordance with the control signal.