Patent ID: 7296111

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, each said memory cell including a storage element for holding binary data of 2 bits based on 2 2 threshold levels, wherein said threshold levels corresponds to data elements “11”, “10”, “00” and “01” forming a set of 2-bit data respectively in ascending order; a cell selection circuit collectively selecting a plurality of said memory cells from said memory cell array in response to an address signal; a data read circuit performing a read operation of storage data on said selected plurality of memory cells on the basis of (2 2 −1) determination levels corresponding to boundaries between said threshold levels; and a data input/output circuit for transferring said storage data between outside of said nonvolatile semiconductor memory device and said memory cells as binary data through k input/output nodes by every k bit (k: natural number), wherein storage data held in each said memory cell is generated from 2 bit data transferred at different timings through the same said input/output node, wherein said data read circuit includes a first read data hold circuit for holding first determination data determined at 2nd one of said determination levels to identify the data of 2nd bit in said storage data held in said storage elements and supplying said data to said data input/output circuit, and a second read data hold circuit for holding second determination data determined at 1st and 3rd ones of said determination levels to perform an operation on said second determination data for identification of the data of 1st bit in said storage data.