Patent ID: 7521294

Claim:
A method of manufacturing a semiconductor package, comprising the steps of: a) providing a lead frame which includes: a die pad; a ground ring extending at least partially about the die pad and defining: a generally planar first ground ring surface; a generally planar second ground ring surface disposed in opposed relation to the first ground ring surface; and at least one third ground ring surface formed between the first and second ground ring surfaces in opposed relation to the first ground ring surface; and a plurality of leads extending at least partially about the ground ring in spaced relation thereto; b) attaching a semiconductor chip having a plurality of input-output pads to the die pad; c) electrically connecting the input-output pads of the semiconductor chip to at least some of the leads and to the first ground ring surface of the ground ring; and d) at least partially encapsulating the die pad, the ground ring, the leads, and the semiconductor chip with a sealing part such that the second ground ring surface of the ground ring is exposed.