Patent ID: 8493398

Claim:
A method of caching data for use by a graphics processing core, comprising: fetching two or more cache lines of data from a core data cache having a first cache line width, wherein the two or more cache lines include a vector data structure that is misaligned within the two or more cache lines and spans more than one of the two or more cache lines; extracting, from the fetched two or more cache lines, two or more portions of the vector data structure; aligning the extracted two or more portions of the vector data structure to produce an aligned vector data structure, the aligned vector data having a second width; storing the aligned vector data structure in a vector data cache having a cache line width equal to the second width of the aligned vector data structure; and writing the aligned vector data structure to a vector register file, in which the aligned vector data structure is stored in an array of registers, wherein the graphics processing core is configured to query the vector register file for a first vector data structure to process, and wherein the graphics processing core is configured to query the vector data cache for the first vector data structure only after determining that the first vector data structure is not present within the vector register file.