Patent ID: 8384582

Claim:
Active transponder comprising: receiving antenna means, configured to receive a first radiofrequency signal modulated according to a first train of one or more first pulses; first processing means, connected to the receiving means, configured to amplify and filter the first radiofrequency signal; separating means, connected to the first processing means, comprising two outputs each one of which outputs the signal coming from the first processing means; second processing means, connected to a first output of the separating means, configured to generate at least one code synchronised with the first pulses; signal generating means, connected to a second output of the separating means and to the second processing means, configured to generate a second radiofrequency signal modulated by said at least one code generated by the second processing means and having at least one of a different frequency value from a frequency value of the first radiofrequency and a different phase value from a phase value of the first radiofrequency; third processing means, connected to the signal generating means, configured to amplify and filter the second radiofrequency signal; and transmitting antenna means, configured to transmit the second radiofrequency signal; wherein the second processing means is configured to generate, for each one of the first pulses, a sequence of one or more second pulses, said at least one code being synchronised with the second pulses, the transponder being characterised in that the second processing means further comprises: envelope detecting means, connected to the first output of the separating means, configured to generate a sequence of one or more envelopes for each one of the first pulses; means for tracking the timing of the first pulses comprising: Delay Locked Loop tracking means, connected to the envelope detecting means, configured to generate a clock signal, synchronised with said envelopes, and a start signal, synchronized with the first train of one or more first pulses; code generating means, connected to the Delay Locked Loop tracking means, configured to generate a not modulated code that varies in synchronisation with said clock signal according to a variation rule synchronised with said start signal; and counting means configured to generate a count synchronised with said clock signal, set at a starting value by said start signal; the second processing means further comprising: memory means, connected to the counting means, which outputs data stored at the memory address equal to said count; and first modulating means, connected to the code generating means and to the memory means, configured to generate said sequence of one or more second pulses through modulation of said not modulated code through the data outputted by the memory means.