Patent ID: 7403028

Claim:
A test structure for testing a functionality of a transistor, said test structure comprising: (a) a first transistor including: (i) a first terminal connectible through a first resistance to a source of a first component of a differential signal; (ii) a second terminal connectible through a second resistance to a sink for a first component of an output signal and interconnected to said first terminal by a parasitic capacitance; and (iii) a third terminal; (b) a second transistor including: (i) a first terminal connectible through a third resistance to a source of a second component of a differential signal; (ii) a second terminal connectible through a fourth resistance to a sink for a second component of an output signal and interconnected to said first terminal by a parasitic capacitance; and (iii) a third terminal interconnected with said third terminal of said first transistor and a source of a bias voltage; (c) a first compensating capacitor connecting said first terminal of said first transistor to said second terminal of said second transistor; and (d) a second compensating capacitor connecting said first terminal of said second transistor to said second terminal of said first transistor.