Patent ID: 8129723

Claim:
A thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer covering the gate line; a semiconductor layer formed on the gate insulating layer over the gate electrode; a data line intersecting the gate line and having a source electrode; a drain electrode facing the source electrode with respect to the semiconductor layer; a passivation layer covering the semiconductor layer, the data line and the drain electrode, and having a contact hole; a pixel electrode formed on the passivation layer and connecting to the drain electrode through the contact hole; and a shielding electrode disposed on the passivation layer and having a first part covering the gate line and a second part covering the data line, wherein the second part of the shielding electrode has at least one aperture, the at least one aperture being disposed within the boundaries of the shielding electrode, and wherein the shielding electrode is made of a transparent conductive material.