Patent ID: 7493606

Claim:
A method of executing machine program code using an essentially sequential, non-parallel computer processor to provide a faithful facsimile of hardware signal or data processing having parallel processing capability, said code defining a plurality of components, each one of said components performing at least one signal or data operation, each one of said components receiving at least one signal or data value input and providing at least one signal or data value output, the method comprising: a) defining processing steps, wherein each one of said operations may only be performed once during each of said processing steps; b) defining an associated event value for some of said outputs; c) defining for each one of said components having event values associated with a plurality of signal or data value inputs, an indication of priority associated with each one of said inputs; d) setting said event value when said associated output signal or data value changes in a current one of said processing steps, and resetting said event value when said associated output signal or data value does not change in said current one of said processing steps, said event value being set or reset at an end of said current one of said processing steps; e) selectively performing said operations during each of said processing steps when at least one of said event values is set for said input signals or data values specific to said operations, wherein said operations are performed in accordance with said priority; and f) buffering said signal or data value outputs so as to prevent changes to them from being read by said inputs within a same one of said processing steps, and copying said buffered outputs at an end of each one of said processing steps so as to allow them to be read by said inputs in a next one of said processing steps.