Patent ID: 7514352

Claim:
A method of manufacturing semiconductor device including an interconnect, comprising: forming on a semiconductor substrate an insulating layer in which a wide interconnect trench which is relatively wide, and a narrow interconnect trench which is relatively narrow are formed; forming by a sputtering method a relatively thick alloy layer including a metal containing an impurity in said bottom of wide interconnect trench, and a relatively thin alloy layer including a metal containing an impurity in said bottom of narrow interconnect trench; forming a metal layer including the same metal as that of said metal layer on both of said alloy layers in said wide interconnect trench and in said narrow interconnect trench; diffusing said impurity from said alloy layer into said metal layer, so as to form a metal layer having a relatively high impurity concentration in said wide interconnect trench, and a metal layer having a relatively low impurity concentration in said narrow interconnect trench; and removing said alloy layer and said metal layer formed in an external region of said respective interconnect trenches, so as to form a relatively wide interconnect in said wide interconnect trench and a relatively narrow interconnect in said narrow interconnect trench, so as to constitute a first interconnect.