Patent ID: 7598131

Claim:
A method for fabricating heterojunction field effect transistors (HFET) comprising steps of: depositing a HFET semiconductor structure onto a substrate; depositing a photoresist material onto the HFET semiconductor structure; selectively removing portions of the photoresist material corresponding to source pad and drain pad pairs; depositing a metal layer onto the HFET semiconductor structure so that the metal is in direct contact with the HFET semiconductor structure, forming source pad and drain pad pairs; removing the photoresist material to expose the semiconductor structure in areas other than the source pad and drain pad pairs, with each source pad and drain pad pair having a corresponding exposed area; annealing the HFET semiconductor structure; electrically isolating devices, with each device comprising a source pad and drain pad pair and a corresponding exposed area; removing a further portion of the HFET semiconductor structure in the exposed area of each device to form a gate recess, such that the source pads and drain pads act as masks to protect areas of the HFET semiconductor structure thereunder; and forming a gate structure in the area of each gate recess such that the gate structure is electrically isolated from direct contact with source pad and the drain pad, thereby resulting in transistor devices.