Patent ID: 8828816

Claim:
A method, comprising: forming a P-active region and an N-active region in a semiconducting substrate comprising silicon; forming a masking layer that covers said N-active region and exposes the P-active region; with the masking layer in position, forming an implantation screen layer on said exposed P-active region; with the masking layer in position, performing an ion implantation process through said implantation screen layer to implant germanium into said P-active region to form an implanted silicon-germanium region in said P-active region, wherein performing said ion implantation process to implant germanium comprises performing said ion implantation process at an energy level ranging from 1-10 KeV with an implant dosage that ranges from 1e 14 -1e 15 ions/cm 2 of germanium; after performing said ion implantation process, removing said masking layer and said implantation screen layer so as to expose an upper surface of said P-active region; and forming a gate insulation layer of a gate electrode structure for a PMOS transistor on said exposed upper surface of said P-active region and on said implanted silicon-germanium region.