Patent ID: 8862652

Claim:
A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving a Register Transfer Language (RTL) representation for a logic circuit for performing a multiplication as a sum of addends operation with a desired rounding precision, the method comprising: determining an error requirement to be met for the desired rounding precision; determining a number of columns k to be discarded from the sum of addends and a constant to include in the sum of addends for each of a CCT and VCT implementation of the sum of addends which meets the error requirement, and further determining a number of columns to discard for an LMS implementation of the sum of addends which meets the error requirement; discarding columns according to the determined respective number of columns for each of the CCT, VCT and LMS implementations; including the constant in the sum of addends for each of the CCT and VCT implementations; deriving an RTL representation of the sum of addends operation for each of the CCT, VCT and LMS implementations, after performing the discarding and the including of the constant; synthesizing a respective netlist for each of the respective RTL representations; and selecting one of the synthesized netlists for production of a logic circuit.