Patent ID: 7821006

Claim:
A TFT comprising: a source region and a drain region formed spaced apart from each other in a semiconductor layer; a gate insulating film covering the semiconductor layer; and a gate electrode formed on the gate insulating film and having at least one opening to expose a channel region between the source region and the drain region, wherein the gate electrode defines the opening formed therethrough and is formed in a closed loop shape to surround the opening in a plan view, wherein the source region includes a first concentration of impurities of a first impurity type, wherein the semiconductor layer comprises a lightly doped region including a second concentration of impurities of the first impurity type, wherein the second concentration is lower than the first concentration, wherein the lightly doped region includes a first portion formed adjacent to the source region and a second portion formed adjacent to the drain region, and wherein the gate electrode partially covers at least one of the first portion and the second portion in a plan view.