Patent ID: 7323740

Claim:
A device comprising: a first well formed in a substrate of a first conductivity type having a first dopant concentration, wherein the first well is of the first conductivity type; a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant. concentration: and a nonvolatile memory cell formed on the second well, wherein the nonvolatile memory cell is an EEPROM cell, and the EEPROM cell comprises a memory transistor and a selection transistor, wherein the memory transistor includes: a tunneling oxide layer; a gate oxide layer formed on the tunneling oxide layer to be thicker than the tunneling oxide layer; a stack gate formed on the tunneling oxide layer and the gate oxide layer of the memory transistor, the stack gate formed of a floating gate, an inter-gate insulating layer, and a control gate; a source region formed within the second well to be aligned with one sidewall of the stack gate; and a floating junction region formed within the second well to be aligned with the other sidewall of the stack gate, the floating junction region formed disposed under the tunneling oxide layer and the gate oxide layer of the memory transistor, and wherein the selection transistor includes: a gate oxide layer; a gate formed on the gate oxide layer of the selection transistor parallel to the stack gate of the memory transistor; the floating junction region aligned with a sidewall of the gate facing the other sidewall of the stack gate of the memory transistor; and a drain region formed within the second well to be aligned with the other sidewall of the gate.