Patent ID: 8422304

Claim:
A method of manufacturing a flash memory device, the method comprising: forming a first gate on a first dielectric on a cell area of a substrate and forming a second gate on a second dielectric on the cell area of the substrate spaced apart from the first gate and first dielectric; forming a third dielectric on opposing sidewalls of the first gate and on a portion of the substrate around the opposing sidewalls of the first gate, and third gates on the third dielectric on the opposing sidewalls of the first gate, forming a fourth dielectric on opposing sidewalls of the second gate and on a portion of the substrate around the opposing sidewalls of the second gate, and fourth gates on the fourth dielectric on the opposing sidewalls of the second gate, and forming a fifth dielectric and a fifth gate on the fifth dielectric on a portion of a peripheral area of the substrate; removing the third dielectric and third gate from the opposing sidewall of the first gate that faces the second gate and removing the fourth dielectric and fourth gate from the opposing sidewall of the second gate that faces the first gate, such that the third dielectric and the third gate on the opposing sidewall of the first gate that faces away from the second gate remains and the fourth dielectric and fourth gate on the opposing sidewall of the second gate that faces away from the first gate remains; forming a first spacer on a side of the remaining third gate, a second spacer on the opposing sidewall of the first gate that faces the second gate, a third spacer on the opposing sidewall of the second gate that faces the first gate, a fourth spacer on a side of the remaining fourth gate, and fifth spacers on opposing sidewalls of the fifth gate; and forming first and second drain areas on a portion of the cell area near the first and fourth spacers, respectively, forming a common source area on a portion of the cell area between the second and third spacers, and forming a source area and a third drain area at sides of the fifth spacers on a portion of the peripheral area at opposing sides of the fifth gate.