Patent ID: 7552267

Claim:
A memory controller interface configured to perform a plurality of data reads on a memory device connected to the memory controller interface, and to compare a first portion and a second portion of at least some of the plurality of data reads to others of the plurality of data reads, such that: if a first portion and a second portion of data in one of the plurality of data reads is different from the first portion and the second portion of data from another of the plurality of data reads, the memory controller interface self-configures to a first data bus width for communicating with the memory device; if a first portion of data in one of the plurality of data reads is different from the first portion of data from another of the plurality of data reads, and a second portion of data from the one of the plurality of data reads is the same as the second portions of data from the remaining of the plurality of data reads, the memory controller interface self-configures to a second data bus width for communicating with the memory device; and if a first portion and a second portion of data in one of the plurality of data reads is the same as the first portions and second portions of data from the remaining of the plurality of data reads, the memory controller interface self-configures to a third data bus width for communicating with the memory device.