Patent ID: 8605496

Claim:
A semiconductor memory device comprising: a cell array comprising a phase change resistance cell configured to read and write data; a sense amplifier configured to sense and amplify data stored in the cell array; a register configured to store information of the sense amplifier; and a refresh control means configured to perform a refresh operation with a specific refresh cycle using the information stored in the register according to a refresh control signal, and to improve a retention characteristic of data stored in the cell array, wherein the refresh control means comprises a refresh register configured to store nonvolatile parameter information for controlling the refresh operation and to output the refresh control signal in the refresh operation, wherein the cell array comprises a word line; a plurality of bit lines; a read/write bit line configured to supply a cell driving voltage; a selecting unit connected to the read/write bit line and controlled by the word line; a plurality of phase change resistance cells connected serially between the selecting unit and a source line and configured to read/write data according to the cell driving voltage; and a plurality of switching elements each connected in parallel to a corresponding one of the phase change resistance cells and controlled selectively by a corresponding one of the bit lines.