Patent ID: 6912473

Claim:
A computerized method for analyzing a macro schematic of a respective hardware macro, in which a common start point and a common end point in a cross-section representing a specific part of said macro, and a hardware macro schematic is selected, said points defining a path within said macro, the method comprising the steps of: a) tracing said path along a given hierarchy; b) collecting the timing information of each cell being relevant for timing analysis of said path; c) resolving the hierarchical structure of cells in the schematic in order to collect timing analysis information about said selected net; d) outputting said information in a form which allows a compare with the information comprised of said cross-section; dividing the given hardware topology information into three categories of cells comprising hierarchical cells, special cells, and primitive cells; tracing said path through a given plurality of hierarchy levels; and entering a deeper hierarchy level, when a hierarchical cell is reached, until all timing information related to primitive cells and special cells associated with said path is collected.