Patent ID: 7525858

Claim:
A semiconductor memory device, comprising: a bit line sense amplifier connected to a bit line and a complementary bit line; a first input/output (IO) line connected to the bit line via a first column select circuit and a first complementary IO line connected to the complementary bit line via a second column select circuit; a second IO line connected to the first IO line via a first switching circuit and a second complementary IO line connected to the first complementary IO line via a second switching circuit; a first IO sense amplifier connected to the second IO line and the second complementary IO line; a second IO sense amplifier connected between the first IO line and the second IO line and between the first complementary IO line and the second complementary IO line and adapted to operate in response to a sense amplifier control signal; wherein the second IO sense amplifier operates to amplify a difference between a voltage apparent on the first IO line and a voltage apparent on the first complementary IO line while the first and second switching circuits are turned on such that a difference between a current in the second IO line and a current in the second complementary IO line is amplified.