Patent ID: 7650450

Claim:
A serial bus system for data communication between devices according to a master-slave protocol, comprising: a data bus connecting master and slave devices; a shared-clock system arranged to provide a shared-clock signal to the master and slave devices; wherein the master and slave devices are arranged to derive device-individual clock signals which are synchronized with data received on the data bus, from the shared-clock signal and a data-timing indication on the data bus, in which the master and slave devices are arranged to communicate in a manner in which the master device is the only device allowed to initiate transmissions by sending a request addressed to a slave device, and a slave device is only allowed to put data on the bus in response to a corresponding request from the master device addressed to said slave device, in which the master and slave devices are arranged to communicate in a manner in which, when the master device has sent a request to a slave device, said slave device takes control of the bus after a turnover phase and returns a response, wherein in the turnover phase, the bus is in an undefined floating state until the slave device assumes control of the bus, in which the master and slave devices are arranged to communicate in a manner in which, after the turnover phase, a slave device immediately confirms a receipt of a request, and is allowed to put its response to the request on the bus after a delay that is fixed by a timer, and in which the master and slave devices are arranged to communicate in a manner in which the master device sends pseudo-interrupt requests to all slave devices, wherein, in response, a slave device may signal an interrupt state by a status bit, or a group of status bits, wherein the slave device signals the interrupt state only in response to receiving the pseudo-interrupt request and the slave device does not signal the interrupt state until the slave device has received the pseudo-interrupt request, and wherein if the master device receives the status bit or group of status bits, the master device sends a second request to the slave device that sent the status bit or group of status bits and upon receipt of the second request the slave device that sent the status bit or group of status bits sends a response with comprehensive information to the master device.