Patent ID: 8692323

Claim:
A semiconductor device, comprising: a semiconductor substrate having an upper main surface and a lower main surface, said semiconductor substrate including a drain layer of a first conductivity type formed in said upper main surface, a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, and a source region of the first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface; a first main electrode connected to said main base region and said source region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an underpad drain region, the underpad drain region being a region of said drain layer, formed in said upper main surface to which said drain layer is exposed with a single insulating layer interposed therebetween, wherein said conductive gate pad is connected to said gate electrode; a conductive layer buried in said single insulating layer to be opposed to said upper main surface in a position closer to said upper main surface than said conductive gate pad and connected to said conductive gate pad through a plug, the drain layer extending to said upper main surface at the plug; and a second main electrode connected to said lower main surface.