Patent ID: 6853233

Claim:
Level shifting circuitry, comprising: a level-shifting section responsive to an input logic signal, such input logic signal having a first voltage level representative of a first logic state or a second voltage level representative of a second logic state, such level-shifting section providing an output logic signal at an output terminal thereof having a third voltage level representative of the first logic state of the input logic signal; and a fourth voltage level representative of the second logic state of the input signal; an enable/disable section coupled to the level shifting section, the enable/disable section being responsive to an enable/disable signal, the enable/disable section placing the output terminal at a relatively high output impedance condition independent of the logic state of the input logic signal during a disable mode; wherein the level-shifting circuitry includes: an input transistor having a control electrode, a first electrode coupled to the input logic signal, and a second electrode; a first switching transistor; a second switching transistor; an output pair of serially coupled complementary type transistors, a first one of the pair of transistors having a first electrode coupled to a source of the third voltage level through the first switching transistor and a control electrode coupled to the second electrode of the input transistor, a junction between the output pair of transistors providing the output terminal for the level-shifting circuitry, a control electrode of the second one of the pair of transistors being connected to the second electrode of the input transistor, the second one of the pair of transistors having a second electrode coupled to the fourth voltage level through the second switching transistor; and wherein the first and second switching transistors are fed by the enable/disable signal.