Patent ID: 7005336

Claim:
A process for forming, on a common semiconductor substrate, CMOS transistors and drain-extension MOS transistors on at least first and second portions, respectively, of the substrate, the process comprising the following steps: in said first portion, forming at least one CMOS transistor having a first gate region projecting from the substrate, and having respective source and drain regions formed in the substrate, each one including a first, lightly doped portion adjacent to the gate region, and including a second, heavily doped portion within said first lightly doped portion; and in said second portion, forming at least one drain-extension MOS transistor having a gate region projecting from the substrate, a source region including a first, heavily doped portion aligned to said gate region, and a drain region formed in the substrate and including a first, lightly doped portion adjacent to the gate region, and a second, heavily doped portion within said first lightly doped portion, the process comprising: forming a low-resistance layer on said gate region of the drain-extension MOS transistor; forming a protective layer on said gate region and said first lightly doped portion of the drain-extension MOS transistor; forming a metal layer over said second heavily doped portions of said CMOS transistor and said drain-extension MOS transistor, and on said gate region of said CMOS transistor; and operating a thermal treatment so as make said metal layer react with the substrate and the gate region of said CMOS transistor, and form a silicide layer.