Patent ID: 8433026

Claim:
A Digital Phase-Locked Loop (DPLL) comprising: a Digitally Controlled Oscillator (DCO) that outputs an oscillating DCO output signal, wherein the DCO output signal has a frequency, wherein the frequency of the DCO output signal changes at discrete times, and wherein the discrete times occur at a first frequency; a feedback phase circuit that receives the DCO output signal and that outputs a first stream of feedback phase digital values; a phase detecting summer that receives the first stream and receives a second stream of modulating signal phase digital values and that outputs a third stream of phase error digital values, wherein the phase error digital values of the third stream are output by the phase detecting summer at a second frequency, and wherein the second frequency is substantially smaller than the first frequency; and a low pass filter that receives the third stream of phase error digital values and that outputs a fourth stream of filtered phase error digital values; wherein the feedback phase circuit comprises: a Time-to-Digital Converter (TDC) that receives the DCO output signal; and downsampling circuitry that receives a stream of digital values from the TDC and outputs the first stream of feedback phase digital values to the phase detecting summer.