Patent ID: 7139044

Claim:
A thin film transistor (TFT) array panel, comprising: a substrate divided into a display region and a peripheral region; a gate wiring pattern formed on the substrate and comprising a second electrode, wherein a first insulating film is formed on the gate wiring pattern; a data wiring pattern formed on the gate wiring pattern and comprising a first electrode, wherein a second insulating film is formed on the data wiring pattern, wherein a third electrode is formed on the second insulating film and electrically connected to the first electrode and overlapped the second electrode, and wherein the data wiring pattern comprises a first data line and a second data line; and a first electrostatic discharge protection circuit comprising: a first capacitor comprising the first electrode and the second electrode; and a first semiconductor pattern formed in the peripheral region, electrically coupled between the first data line and the first electrode, and laterally spaced apart from the gate wiring pattern.