Patent ID: 8372694

Claim:
A process for fabricating semiconductor packages, comprising: fabricating a substrate provided with a plurality of electrical connection front pads at a plurality of front locations on a front face and a plurality of electrical connection rear pads at a plurality of rear locations on a rear face, the front pads and rear pads being selectively connected via an electrical connection network that passes through said substrate; mounting a peripheral edge of the substrate on a rigid annular frame; depositing, on at least said front pads of the substrate, a dielectric sealant layer containing particles made of an electrically conductive material; positioning integrated-circuit chips on said front locations; flattening the dielectric sealant layer when positioning such that pads of the integrated-circuit chips are selectively connected electrically to the front pads of the corresponding front locations of the substrate by the particles of the dielectric sealant layer lying therebetween; encapsulating the integrated-circuit chips in a block of encapsulating material on top of the front face of the substrate so as to constitute a mounted assembly; and dicing the mounted assembly in order to obtain a plurality of semiconductor packages each comprising a portion of the substrate, at least one integrated-circuit chip and a portion of said block of encapsulating material encapsulating the at least one integrated-circuit chip.