Patent ID: 7337366

Claim:
A microcomputer, comprising: a first circuit block comprising: a processor comprising a first test access port (TAP) controller; a first memory; a second TAP controller; a means for providing an external input to said processor and said second TAP controller; a first monitoring means for monitoring said external input for detecting a debug instruction directed to said first and second TAP controllers; and a second monitoring means connected to said second TAP controller for determining whether said debug instruction comprises an access to a destination address that is within a predetermined protected area in said first memory; a second circuit block connected to said first circuit block, said second circuit block configured with a second memory for storing a copy of the contents of said predetermined protected area in said first memory; and an access control means for, if said first monitoring means has detected a debug instruction and said second monitoring means has detected that an access from said debug instruction is addressed to an address within said predetermined protected area, replacing the destination address of the access with a replacement address within said second memory in said second circuit block that contains said copy of said contents of said predetermined protected area in said first memory.