Patent ID: 8704287

Claim:
A semiconductor memory device comprising: a memory cell array area including a first active area and a first element isolation area constituting a line and space structure, and including memory cells in the first active area; a word line contact area adjacent to the memory cell array area and, said memory cell array area further including a second active area; first and second word lines connecting to the memory cells and provided to straddle the memory cell array area and the word line contact area; a first insulating film provided between the first and second word lines and directly contacting to one side of the first word line and contacting to one side of the second word line, and the first insulating film including a void; and first and second contacts provided respectively corresponding to the first and second word lines in the word line contact area, wherein a first bottom portion of the void on the second active area is higher than a second bottom portion of the void on the first element isolation area in the memory cell array area.