Patent ID: 8422318

Claim:
A semiconductor device, comprising: a plurality of control signal generation units, a first control signal generation unit among the plurality of control signal generating units generating a first control signal by a logical AND of a column enable signal and a row enable signal; and a plurality of local sense amplifiers, a first local sense amplifier among the plurality of local sense amplifiers receiving the first control signal from the first control signal generation unit, the first local sense amplifier sensing and amplifying data transmitted via a pair of local input/output (I/O) lines and then outputting the amplified data via a pair of global I/O lines, in response to a read or write signal and the received first control signal, wherein the first local sense amplifier includes: a first transistor having a gate connected to one local I/O line from among the pair of local I/O lines, a first terminal, and a second terminal; a second transistor having a gate connected to the other local I/O line from among the pair of local I/O lines, a first terminal connected to the first terminal of the first transistor, and a second terminal; a third transistor having a gate to which the read or write signal is supplied, a first terminal to which a ground voltage is applied, and a second terminal connected to the first terminals of the first and second transistors; a fourth transistor having a gate to which the first control signal is supplied, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to one global I/O line from among the pair of global I/O lines; a fifth transistor having a gate connected to the gate of the fourth transistor, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the other global I/O line from among the pair of global I/O lines; a sixth transistor having a gate connected to the gate of the third transistor, a first terminal connected to the gate of the first transistor, and a second terminal connected to the second terminal of the fifth transistor; and a seventh transistor having a gate connected to the gate of the third transistor, a first terminal connected to the gate of the second transistor, and a second terminal connected to the second terminal of the fourth transistor.