Patent ID: 7401209

Claim:
A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, the method comprising: dispatching the load instruction to an issue queue (IQ) in program order; inserting the load instructions in the LRQ in program order; clearing the load received data field in the LRQ for the dispatched load instruction; executing the load instruction by removing the load instruction from the IQ; checking all the LRQ entries located between a load_peril_snoop register and a lrq_jail register with a snooped bit set and with a matching data address as that of the currently executing load instruction; re-executing the load instruction of the matching LRQ entry; continuing execution of the currently executing load instruction; getting the load data from the memory and sending the data to the load instruction's destination register; setting the load received data field in the LRQ entry for the load instruction whose data has been sent to the load instruction's destination register; comparing the load sequence number (LSQN) of the currently executing load instruction to a snoop_safe register contents; ANDing all the load received data bits in the LRQ located between a lrq_head register and the load instruction if the LSQN is greater in magnitude than the snoop_safe register contents; setting the snoop_safe register to the LSQN of the load instruction if the result of ANDing is equivalent to 1; and setting the load_peril_snoop register to the LRQ index value where the first load instruction younger than the snoop_safe is found.