Patent ID: 7340653

Claim:
A method for testing a memory device, comprising the steps of: applying an external clock to a circuit coupled to the memory device; applying an activation command to the circuit, applying a precharge command to the circuit; applying a test mode command to the circuit; generating an activation pulse from the circuit to memory banks of the memory device in synchronization to a rising edge of the external clock after applying the activation command when the test mode command is at a first level; generating a precharge pulse from the circuit to the memory banks in synchronization to a falling edge of the external clock after applying the activation and precharge commands when the test mode command is at the first level; generating the activation pulse from the circuit to the memory banks in synchronization to the rising edge of the external clock after applying the activation command when the test mode command is at a second level; generating the precharge pulse from the circuit to the memory banks in response to applying the activation command and in synchronization to the falling edge of the external clock when the test mode command is at the second level.