Patent ID: 8481388

Claim:
A method of forming a non-volatile memory cell on a semiconductor substrate, the method comprising: forming a source region in a portion of the substrate; forming a drain region within a portion of the substrate, the drain region being spaced apart from the source region; forming a well region within a portion of the substrate, the well region surrounding at least a portion of the source and drain regions; forming a first carrier tunneling layer over the substrate, the first carrier tunneling layer being an electron tunneling layer; forming a charge storage layer over the first carrier tunneling layer; forming a second carrier tunneling layer over the charge storage layer, the second carrier tunneling layer being a hole tunneling layer wherein a part of the hole tunneling layer adjacent to the charge storage layer has a hole tunneling layer bandgap larger than a charge storage layer bandgap of the charge storage layer, and the second carrier tunneling layer has a conduction band electron barrier against electron loss from the charge storage layer to the part of the hole tunneling layer adjacent to the charge storage layer; and forming a conductive control gate over the second carrier tunneling layer; and forming circuitry to induce electron tunneling through the electron tunneling layer in a program mode to increase negative charge trapped in the charge storage layer, and to induce hole tunneling through the hole tunneling layer between the conductive control gate and the charge storage layer in an erase mode to reduce negative charge trapped in the charge storage layer.