Patent ID: 7899143

Claim:
An apparatus for precluding reception errors in an source synchronous receiver, the apparatus comprising: a delay-locked loop, configured to receive a reference clock signal, and configured to generate an adjusted select vector signal and an encoded select vector signal that both indicate a first time period, wherein a select vector signal is employed to select one of a plurality of successively delayed versions of said reference clock signal that lags said reference clock signal by a second time period that is slightly less than a prescribed number of cycles of said reference clock signal, said delay-locked loop comprising: adjust logic, configured to receive said select vector signal, and configured to generate said adjusted select vector signal by reducing the value of said select vector signal by an amount; and a delay element having a first plurality of taps, each of said first plurality of taps corresponding to each of said plurality of successively delayed versions of said reference clock signal; and one or more strobe receivers, each coupled to said delay-locked loop, and said each configured to receive said encoded select vector signal and a corresponding strobe signal, wherein said each is configured to lock out reception of said corresponding strobe signal for said first time period following transition of said corresponding strobe signal, and wherein said encoded select vector signal is employed to determine said first time period by selecting one of a plurality of successively delayed versions of said corresponding strobe signal, wherein said each of said one or more strobe receivers comprises: a replica delay element having a second plurality of taps, each of said second plurality of taps corresponding to each of said plurality of successively delayed versions of said corresponding strobe signal, wherein said first and second plurality of taps are equal in number.