Patent ID: 7336544

Claim:
A semiconductor device comprising: a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a word line connected to the first memory cell and the second memory cell; a source line connected to the first memory cell and the second memory cell; a sense amplifier connected to the first bit line and the second bit line; a first transistor of which one of a first source and a first drain is connected to the first bit line; a second transistor of which one of a second source and a second drain is connected to the first bit line; a third transistor of which one of a third source and a third drain is connected to the second bit line; and a fourth transistor of which one of a fourth source and a fourth drain is connected to the second bit line, wherein the first memory cell comprises a fifth transistor and a first variable resistive element, wherein the second memory cell comprises a sixth transistor and a second variable resistive element, wherein the first transistor and the third transistor are for supplying a first voltage to the first bit line and the second bit line, respectively, and the second transistor and the fourth transistor are for supplying a second voltage to the first bit line and the second bit line, respectively, wherein when the first memory cell is a selected memory cell to read information stored in the first memory cell in a read operation period, the first voltage is supplied to the first bit line by setting the first transistor ON, and wherein the second voltage is a voltage of the source line, and the second voltage is supplied to the second bit line by setting the fourth transistor ON while the first transistor is set ON in the read operation period.