Patent ID: 6959361

Claim:
A memory controller containing a distributed cache that stores cache lines for pending memory operations, comprising: an input mechanism that is configured to receive a memory operation that is directed to a current address in memory; a central scheduling unit; a plurality of agents under control of the central scheduling unit, wherein a given agent in the plurality of agents is configured to receive the current address; a comparison mechanism within the given agent that is configured to compare the current address with an address of a cache line stored within the given agent; a reporting mechanism within the given agent that is configured to report to the plurality of agents a result provided by the comparison mechanism; and an access mechanism that is configured to access data within the cache line stored within the given agent in order to accomplish the memory operation when the comparison mechanism indicates a match; wherein the plurality of agents compare the current address with their respective cache line addresses in parallel; and wherein the given agent holds the cache line while memory operations are pending for the cache line.