Patent ID: 8484520

Claim:
A processor which can execute pipeline processing, comprising: an ALU; and a load/store unit, wherein when the load/store unit writes data in a storage section, the load/store unit writes written data and a count value counted according to a predetermined clock in the storage section, and sets an ECC status flag which indicates that an ECC about the written data is not correct in the storage section, and causes calculation of the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the storage section and resets the ECC status flag after the ECC is calculated, and wherein when the load/store unit reads data from the storage section, the load/store unit reads the data, and the ECC status flag, the count value and the ECC about the data from the storage section, and executes recalculation of an ECC from the read data, and if the ECC status flag about the read data has been set, the load/store unit determines an ECC for comparison among ECGs held by a plurality of registers based on the read count value, and compares the recalculated ECC with the ECC for comparison, and if the ECC status flag about the read data has not been set, the load/store unit compares the recalculated ECC with the read ECC, so that ECC error is determined.