Patent ID: 7812448

Claim:
An electronic device comprising: an interconnect level including a bonding pad region; a first insulating layer overlying the interconnect level and including a first opening over the bonding pad region; a first barrier layer lying along a side and a bottom of the first opening, wherein, the first barrier layer does not overlie the first insulating layer; and the portion of the first barrier layer includes a first surface adjacent to the first opening; and a second surface opposite the first surface and defining a second opening; a conductive stud lying within the second opening, wherein: the conductive stud substantially fills the second opening; and a majority of the conductive stud lies within the first and second openings, and the conductive stud occupies a majority of the first opening; a second barrier layer overlying the conductive stud and the first insulating layer, wherein substantially none of the second barrier layer lies within the first opening within the first insulating layer; and a solder bump overlying the second barrier layer, wherein substantially none of the solder bump contacts the conductive stud or the interconnect level.