Patent ID: 7663941

Claim:
A semiconductor memory device comprising: memory cells including floating bodies in electrically floating states, and storing therein data according to number of carriers accumulated in the floating bodies; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the pair of bit lines, and transmitting the data of the memory cells; a plurality of transfer gates connected between the pair of bit lines and the pair of sense nodes; a latch circuit latching a first high level potential to one of the pair of sense nodes, and latching a low level potential to the other sense node of the pair of sense nodes; and a level shifter applying a second high level potential higher than the first high level potential to one of the pair of bit lines according to the potentials latched to the pair of sense nodes during a data write operation or a data write-back operation, wherein the pair of bit lines transmit data complementary to each other.