Patent ID: 7719912

Claim:
A semiconductor memory device, comprising: a plurality of pairs of bit lines extending in parallel in a column direction; a plurality of word lines extending in parallel in a row direction; a plurality of memory cell array blocks each having a predetermined number of the word lines; and a plurality of sense amplifier array blocks each of which is disposed, in plan view, between every pair of adjacent memory cell array blocks and has a plurality of first bit line sense amplifying means each arranged for every four bit line pairs in four different memory cell array blocks, respectively, wherein the first bit line sense amplifying means includes: a sense amplifier for sensing and amplifying a voltage level between a first node and a second node; a first switching means for making a selective connection between (i) a first bit line pair of a first memory cell array block and (ii) the first node and the second node, respectively; a second switching means for making a selective connection between (i) a first bit line pair of a second memory cell array block and (ii) the first node and the second node, respectively; a third switching means for making a selective connection between (i) a second bit line pair of a third memory cell array block and (ii) the first node and the second node, respectively; and a fourth switching means for making a selective connection between (i) a second bit line pair of a fourth memory cell array block and (ii) the first node and the second node, respectively.