Patent ID: 7532046

Claim:
Receiver for a differential data bus with two branches with resistive elements, which are coupled in a series arrangement in which the connections between the resistive elements are coupled to first terminals of switches wherein one of the switches of each branch is closed for receiving data from the bus and is coupled by its second terminal to comparators the receiver being provided with a switch control logic 51 which matches the resistive elements in two matching routines: in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltages at the switches in a first resistive branch consecutively with a reference voltage, by selecting the correct switch setting, at which the voltage at the activated switch has value closest to the reference voltage, and by writing this setting to an internal storage device, and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltages at the switches of the second resistive branch consecutively with that of the already trimmed first resistive branch, by selecting the correct switch setting for the second branch, at which the voltage at the activated switch has the value closest to the voltage of the switch of the first branch found in the first routine, and by writing this setting to an internal storage device.