Patent ID: 8729954

Claim:
A semiconductor device comprising: a first P-type metal oxide semiconductor (PMOS) transistor having a source electrode, a drain electrode, and a gate electrode; a second PMOS transistor having a source electrode, a drain electrode, and a gate electrode; a first N-type metal oxide semiconductor (NMOS) transistor having a source electrode, a drain electrode, and a gate electrode; and a second NMOS transistor having a source electrode, a drain electrode, and a gate electrode, wherein the drain electrodes of the first PMOS and NMOS transistors are coupled together to a first output terminal, wherein a signal at the first output terminal depends only on an output of the first PMOS and NMOS transistors, the first output terminal is connected as an only input to the gate electrodes of the first and second PMOS transistors and the first and second NMOS transistors, the drain electrode of the second PMOS transistor is coupled to the drain electrode of the second NMOS transistor at a second output terminal, an absolute value circuit including a first comparator configured to generate a switch signal, and a second comparator configured to receive the first output at a first input and the second output at a second input when the switch signal is a first value, and to receive the second output at the first input and the first output at the second input when the switch signal is a second value; and a summing amplifier having an input coupled to the output of the second comparator, wherein the summing amplifier output a signal that indicates mismatch between the transistors.