Patent ID: 7012019

Claim:
A method for fabricating a circuit barrier structure of a semiconductor packaging substrate, comprising the steps of: preparing the substrate having inner circuits and an insulating layer, forming a metal conductive layer on a surface of the substrate, and forming a patterned first resist layer on the metal conductive layer, wherein the patterned first resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer; forming a metal barrier layer on the patterned first resist layer and in the holes of the first resist layer to cover the exposed parts of the metal conductive layer; removing the metal barrier layer on the patterned first resist layer; performing an electroplating process to form a patterned circuit layer and an electrical connection pad in the holes of the first resist layer and on the retained metal barrier layer; forming a second resist layer on the surface of the substrate to cover the patterned circuit layer, allowing the electrical connection pad of the circuit layer to be exposed from the second resist layer; and performing another electroplating process to form a metal protection layer on the exposed electrical connection pad.