Patent ID: 7112856

Claim:
A semiconductor device comprising: an insulated gate electrode pattern; sidewall spacers formed on sidewalls of the gate pattern; a source region and a drain region formed adjacent opposite sides of the gate pattern, the source and drain regions having a channel region disposed therebetween, the source and drain regions and the channel region having a common well region, the source region including: a first-concentration impurity region under one of the sidewall spacers, and a silicide layer formed within the first-concentration impurity region, wherein an average depth of the silicide layer is less than an average depth of the first concentration impurity region, the silicide layer structured and arranged to be electrically connected with the common well region, wherein the drain region includes a first-concentration impurity region under the other sidewall spacer, and a silicide layer formed adjacent the other sidewall spacer, and a second-concentration impurity region formed under the silicide layer, wherein the silicide layer does not contact any portion of the well region, and wherein the source region does not include a second-concentration impurity region.