Patent ID: 7615475

Claim:
A method for forming an integrated circuit device, the method comprising: providing a semiconductor substrate comprising a surface region; forming a polysilicon layer overlying the surface region; forming a cap layer overlying the polysilicon layer; forming an Al 2 O 3 layer using atomic layer deposition overlying the polysilicon layer to form a sandwich structure including the polysilicon layer, cap layer, and Al 2 O 3 layer; patterning the sandwich layer to form a plurality of gate structures, each of the gate structures including a portion of the polysilicon layer, a portion of the cap layer, and a portion of the Al 2 O 3 layer; forming an interlayer dielectric material having an upper surface overlying the plurality of gate structures; patterning the interlayer dielectric material to form an opening in a portion of the interlayer dielectric material to expose each of the gate structures; filling the opening with a polysilicon fill material to a vicinity of the upper surface of the interlayer dielectric material; performing a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer concurrently with a portion of the polysilicon fill material; maintaining the chemical mechanical polishing process until a portion of the Al 2 O 3 layer overlying one of the gate structures has been exposed; and using portions of the Al 2 O 3 layer as a polish stop while preventing any exposure of any portion of the polysilicon layer.