Patent ID: 7661130

Claim:
An apparatus comprising: a plurality of security processing resources within a cryptographic processor for processing two or more different types of data traffic; a first scheduler to handle only a first type of data traffic and to provide the first type of data traffic to a first predefined subset of the security processing resources using a first scheduling technique; and a second scheduler to handle only a second type of data traffic and to provide the second type of data traffic to a second predefined subset of the security processing resources using a second scheduling technique; a first request queue for storing security processing requests to be processed by the first predefined subset of the security processing resources comprising execution cores, wherein the first scheduler reads the security processing requests from the first request queue and forwards the security processing requests to individual execution cores of the first predefined subset in a round robin manner, as the execution cores become available; and a second request queue for storing security processing requests to be processed by the second predefined subset of the security processing resources comprising execution cores, wherein the second scheduler reads the security processing requests from the second request queue and forwards the security processing requests to one of a plurality of execution core queues in a round robin manner, as the execution cores associated with each of the execution core queues become available; wherein the first scheduler and the first request queue are implemented within the cryptographic processor and wherein the second scheduler and the second request queue are implemented within a memory external to the cryptographic processor.