Patent ID: 8219376

Claim:
A computer-implemented method for verifying a design, comprising: representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine comprising multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions; for each of a plurality of values of the local variable occurring at run-time, defining a respective copy of the finite state machine, thereby maintaining multiple copies of the finite state machine, such that at any given time during the run-time, each of the copies is defined by a respective value of the local variable and a respective subset of the states that are currently reachable by the copy; executing the verification directive by concurrently traversing the transitions of the multiple copies of the finite state machine in accordance with the respective transition conditions and modifying the local variable in each of the copies in accordance with the respective procedural blocks at each of the traversed transitions, so as to produce verification results; and verifying the design with respect to the verification directive based on the verification results.