Patent ID: 7533309

Claim:
A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit, the method comprising: running a first testing algorithm on the at least one memory element; determining whether to run a second testing algorithm, the act of determining being performed during a delay following the running of the first testing algorithm and comprising evaluating a value associated with the second testing algorithm, wherein the value associated with the second testing algorithm is a value stored in a shift register so as to be associated with the second testing algorithm; running the second testing algorithm on the at least one memory element if a determination is made during the determining act that the second testing algorithm is to be run; and if a determination is made during the determining act that the second testing algorithm is not to be run, determining whether to run a third testing algorithm, the act of determining comprising evaluating a value associated with the third testing algorithm, wherein the values associated with the second and third testing algorithms are stored in different memory locations.