Patent ID: 7146549

Claim:
A scan-path flip-flop circuit for a macro block, comprising: a plurality of successively arranged flip-flops, each of the flip-flops comprising: a master latching circuit, responsive to a normal-mode clock signal, for receiving a first signal from one of a plurality of input terminals and supplying the received first signal to said macro block and latching the received first signal and responsive to a first scan-mode clock signal for receiving a second signal and latching the received second signal; and a slave latching circuit, responsive to said normal-mode clock signal for receiving the first signal from the master latching circuit and latching that received first signal responsive to a second scan-mode clock signal for receiving the second signal from the master latching circuit and latching the received second signal; the master latching circuit of each succeeding flip-flop being connected to the slave latching circuit of a preceding flip-flop for receiving said second signal from the preceeding flip-flop in response to the first scan-mode clock signal.