Patent ID: 7382671

Claim:
A method of detecting a memory device failure in a memory device having a sense amplifier, said memory device also having a BIT line and a /BIT line, said sense amplifier further having C 1 and C 2 inputs, an improvement comprising the steps of: i) applying a first output signal to the C 1 input of the sense amplifier, said first output signal originating from and being generated by a first control signal generating circuit that generates said first output signal in response to a first test mode signal and in response to a source-in signal, both of which are input to said first control signal generating circuit; and ii) after the first output signal is applied to the C 1 input, applying a second output signal to the C 2 input of the sense amplifier, said second output signal originating from and being generated by a second control signal generating circuit that generates said second output signal in response to a second test mode signal and in response to a sink-in signal, both of which are input to said second control signal generating circuit; wherein a sense amplifier failure can be determined by comparing a first voltage on BIT and /BIT lines when the sense amplifier has failed.