Patent ID: 8495307

Claim:
A system for implementing prefetch instructions, the system comprising: a first core processor; a dedicated local cache corresponding to the first core processor; and a second core processor including instructions for executing a prefetch instruction, the executing comprising: sending, by the second core processor, an instruction to the dedicated local cache corresponding to the first core processor that directs the dedicated local cache corresponding to the first core processor to prefetch data for the first core processor from a memory location; sending, by the dedicated local cache corresponding to the first core processor, a load request for data from the memory location responsive to receiving the instruction from the second core processor; receiving, by the dedicated local cache corresponding to the first core processor, the data corresponding to the load request; storing, on the dedicated local cache corresponding to the first core processor, the received data corresponding to the load request; wherein the executing further comprises: sending, by the second core processor, a command to a system bus; sending, by the system bus, the command to the first core processor and a main memory; receiving, by the second core processor, a first response to the command from the first core processor that indicates that the first core processor requires access to the data that is specified in the command; and receiving, by the second core processor, a second response to the command from the main memory that indicates that the main memory is capable of fulfilling the command, wherein the sending, by the second core processor, of the instruction to the dedicated local cache corresponding to the first core processor is based on receiving the first and second responses.