Patent ID: 6868134

Claim:
A clock recovery system for generating a clock signal corresponding to an asynchronous data signal, said circuit comprising: an input port for receiving an incoming data signal; a local oscillator circuit for generating a plurality of clock signals having the same frequency, said plurality of clock signals each being shifted in phase relative to one another; a sampling unit having a plurality of latches, each of said latches being clocked by one of said plurality of clock signals generated by said local oscillator circuit, said sampling unit outputting a plurality data samples of said incoming data signal; a data phase alignment unit coupled to said sampling unit, said data phase alignment unit receiving said plurality of said data samples as input signal and operative for shifting the phase of said plurality of data samples; a multiplexer circuit coupled to said data phase alignment unit, said multiplexer circuit having a first multiplexer operative for selecting a portion of said plurality of said data samples, each of said data samples having a corresponding clock signal, which is one of said plurality of clock signals generated by said local oscillator circuit, said multiplexer circuit having a second multiplexer operative for selecting one of said plurality of clock signals generated by said local oscillator circuit; a phase decoder coupled to said multiplexer circuit, said phase decoder operative for receiving said portion of said plurality of data samples selected by said multiplexer and for generating an output signal indicative of the logic values of the portion of said plurality of said data samples selected by said first multiplexer; and a barrel shifter circuit coupled to said phase decoder, said barrel shifter operative for adjusting the data samples selected by said first multiplexer in accordance with the output signal of said phase decoder.