Patent ID: 8274114

Claim:
A transistor, comprising: a first region configured to form a source region of the transistor; a second region configured to form a drain region of the transistor; a third region, positioned between the source region and the drain region, configured to form a gate region of the transistor; a modified breakdown shallow trench isolation (STI) region positioned between the drain region and the gate region, the modified breakdown STI region including at least one slanted edge, the modified breakdown STI region not overlapping the gate region; a modified well region positioned between the drain region and the gate region, the modified well region including a first well region and a second well region, the second well region being heavily doped relative to the first well region and being positioned between the modified breakdown STI region and the first well region; and a gate oxide region positioned beneath the gate region, the first and second well regions being in contact with the gate oxide region.