Patent ID: 6958635

Claim:
An integrated circuit comprising: a counter operative to receive an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer values, and to generate a counter signal having a second frequency determined by the M value and the N value; and a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal, wherein the delay generator includes: a first bank of capacitor, each capacitor in the first bank being selectable by the L-bit control signal, a first current source operative to charge selected capacitors in the first bank, and a comparator operative to provide the output clock signal based on a first voltage signal on the selected capacitors in the first bank.