Patent ID: 7213095

Claim:
A bus transaction buffer comprising: one or more write bus inputs and one or more read bus inputs coupled to respective write buses and read buses and operable respectively to receive write requests and read requests from one or more request sources; one or more write bus outputs and one or more read bus outputs coupled to respective write buses and read buses and operable respectively to output write requests and read requests to one or more request destinations; and a request buffering circuit operable to buffer write requests received from said request sources and to control processing of write requests and read requests to said one or more request destinations, wherein at least some of said read requests include a read request, to a given memory address and received from a request source having a given request source identifier after a write request to said given memory address was received from said request source having said given request source identifier, which is not output on a read bus output until said write request is acknowledged as completed at a write bus output, wherein said request buffering circuit is operable to output a request completed signal to a request source in respect of a write request received from said request source before a corresponding request completed signal for said write request has been received at said write bus output for said write request.