Patent ID: 7973370

Claim:
A memory array comprising: a plurality of transistors each having a silicon-on-insulator on a substrate, each transistor comprising: a drain region comprising a first doped material and formed in the silicon-on-insulator; a source region comprising the first doped material and formed in the silicon-on-insulator; an oxide-nitride-oxide layer formed on the silicon-on-insulator between the drain region and the source region; a control gate formed on the oxide-nitride-oxide layer and substantially between the drain and source regions; and an extractor contact, in the silicon-on-insulator, comprising a second doped material and coupled to a depletion region substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact; wherein pairs of adjacent transistors of the plurality of transistors, each comprising a different conductivity type from the other transistor of the pair, are coupled together in parallel, source region to drain region, such that their control gates are connected.