Patent ID: 7673261

Claim:
A computer-implemented method for validating compliance of a process executed by a design-under-test with a specification of said process, comprising the steps of: modeling said process on a computer system as a directed acyclic graph having nodes and edges that connect said nodes, wherein said nodes represent stages of said process, and said edges represent transitions between said stages; defining a coverage model for said graph that includes correct traversal paths and erroneous traversal paths therein; defining a set of test cases for said process according to said coverage model; introducing false nodes and false edges into said graph that represent new transitions between said stages and correspond respectively to external misinterpretations of said specification, thereby defining erroneous traversal paths that extend through said false nodes via said false edges; executing said process using said design under-test and said set of test cases; observing that one of said erroneous traversal paths was followed in said step of executing; and responsively to said step of observing, reporting that said process is not compliant with said specification.