Patent ID: 6950336

Claim:
An array of non-volatile floating gate memory cells arranged in a plurality of rows and columns, a plurality of said memory cells electrically coupled to form a plurality of pages, said array comprising: a plurality of page row lines, each of said page row lines connected to a gate of one or more of said memory cells in one of said rows; a plurality of page source lines, each of said page source lines connected to a source of one or more of said memory cells in one of said pages, wherein each of said pages includes each of said plurality of non-volatile floating gate memory cells that are subject to program disturb voltages when at least one of said plurality of non-volatile floating gate memory cells within a same page is programmed; a plurality of column lines, each of said column lines connected to a drain of all of said memory cells in one of said columns; and a global row decoder to decode major rows in said memory array.