Patent ID: 7480180

Claim:
A semiconductor memory device comprising: memory cells each of which includes a MOS transistor; a memory cell array in which the memory cells are arranged in a matrix; word lines each of which connects in common gates of the MOS transistors in the memory cells in the same row; bit lines each of which connects in common drains of the MOS transistors in the memory cells in the same column; source lines each of which electrically connects in common sources of the MOS transistors in the memory cells; a first voltage supply circuit which applies voltages to the bit lines so that a first potential difference is made between the adjacent bit lines and so that a second potential difference smaller than the first potential difference is made between the bit lines adjacent to each other across the source line; and a second voltage supply circuit which applies voltages to the source lines so that a third potential difference larger than the second potential difference is made between the source line and bit line adjacent to each other.