Patent ID: 7304485

Claim:
A method for analyzing a quality of contacts and vias using a test chip, the test chip comprising a substrate; a plurality of contacts on the substrate and defining a zero level; and a test array on the substrate comprising a plurality of conductive levels and a plurality of individually selectable vias separating the plurality of conductive levels, each conductive level comprising a plurality of nodes with each node being connected to at least one individually selectable via, the plurality of conductive levels and the plurality of individually selectable vias forming a pyramidal interconnect structure so that an electrical path between a contact at the zero level and a node on one of the plurality of conductive levels includes at least one individually selectable via therebetween, the method comprising: selecting an electrical path in the pyramidal interconnect structure between a contact at the zero level and a node on one of the plurality of conductive levels; and measuring an electrical resistance of the selected electrical path.