Patent ID: 8477549

Claim:
A programmable logic device (PLD) comprising: a plurality of static random access memory (SRAM) cells adapted to configure the PLD for an intended use; a pair of bitlines connected to the SRAM cells, wherein at least one of the SRAM cells is adapted to provide data signals to the bitlines in response to a wordline signal received by the one of the SRAM cells during a read operation; a sense amplifier connected to the bitlines and adapted to detect a data value from the data signals in response to a trigger signal received by the sense amplifier during the read operation; and logic adapted to delay the trigger signal relative to the wordline signal to permit the data signals to settle before the sense amplifier detects the data value, wherein the logic includes at least first and second inverters connected in series, an input of the first inverter coupled to receive the trigger signal and an output of the second inverter coupled to provide the delayed trigger signal to the sense amplifier, and wherein the sense amplifier comprises: a flip flop comprising first and second nodes; a first transistor having its gate connected to a first one of the bitlines; and a second transistor having its gate connected to a second one of the bitlines, wherein the first and second transistors are adapted to selectively adjust voltages of the first and second nodes, respectively, in response to the data signals on the bitlines when the trigger signal is received.