Patent ID: 6897679

Claim:
A programmable logic device organized in a two-dimensional array comprising: a first plurality of conductors, each of said first plurality of conductors provided in a first dimension of said two dimensional array; a second plurality of conductors, each of said second plurality of conductors provided in a second dimension of said two dimensional array; plurality of logic blocks devoted substantially to logic functions, each of said logic blocks programmably coupled to at least one of said first or second plurality of conductors; and a plurality of memory blocks devoted substantially to user memory, each of said memory blocks programmably coupled to at least one of said first or second plurality of conductors, wherein a selected number of said plurality of logic blocks provide a plurality of registers and multiplexers, each of said registers receives a first data input and a first clock input and each of said multiplexers receives a second data input, said multiplexers comprising at least one output coupled to at least one of said plurality of memory blocks, said at least one memory block receiving a second clock input.