Patent ID: 7525120

Claim:
A thin film transistor array substrate, comprising: a gate line formed on a substrate; a data line formed on the substrate intersecting with the gate line to define a pixel region; a thin film transistor formed at the intersection of the gate line and the data line, the thin film transistor including gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode and the substrate, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer on the semiconductor layer, and a source electrode and a drain electrode on the ohmic contact layer; and a transparent electrode material within the pixel region and connected to the drain electrode of the thin film transistor, wherein the gate insulating layer includes a gate insulating pattern underlying the data line and the transparent electrode material, and covering the gate line, wherein the transparent electrode material contacts the gate insulating layer, and wherein the transparent electrode material directly contacts a side portion of the semiconductor layer.