Patent ID: 7802220

Claim:
A method for determining placement of an on-chip decoupling capacitor in an integrated circuit and for fabricating the integrated circuit, the method comprising: (a) estimating a target impedance of a current load to which the on-chip decoupling capacitor is to be connected; (b) determining a maximum effective radius based the target impedance, the maximum effective radius based on the target impedance being a radius from the on-chip decoupling capacitor within which the current load must be located; (c) determining a maximum effective radius determined by a charge time for the capacitor from a power source, the maximum effective radius determined by the charge time being a radius from the on-chip decoupling capacitor within which the power source must be located; (d) determining a location of the on-chip decoupling capacitor relative to the current load and the power source such that the maximum effective radius based on the target impedance and the maximum effective radius determined by the charge time are satisfied; (e) making the location determined in step (d) available for fabrication of the integrated circuit; and (f) fabricating the integrated circuit in accordance with the location determined in step (d).