Patent ID: 6891755

Claim:
A memory device comprising: an array of memory cells organized into a plurality of sectors; local wordlines and local bitlines connected to said memory cells in each respective sector; addressing means for simultaneously addressing at least two of said sectors for performing an operation on at least one menory cell in a first sector while performing an operation on at least one memory cell in a second sector, said addressing means comprising main read wordlines and main program wordlines connected to said local wordlines in each sector, a main read row decoder connected to said main read wordlines, and a main program row decoder connected to said main program wordlines, main read bitlines and main program bitlines connected to said local bitlines in each sector, a main read column decoder connected to said main read bitlines, and a main program column decoder connected to said main program bitline, a local read row decoder and a local program row decoder connected to said local wordlines in each sector, a local read column decoder and a local program column decoder connected to said bitlines in each sector, a read address bus connected to said main read row decoder and to said main read column decoder for providing a first address corresponding to at least one memory cell in the first sector, and a program address bus connected to said main program row decoder and to said main program column decoder for providing a second address corresponding to at least one memory cell in the second sector.