Patent ID: 7701777

Claim:
A semiconductor memory device, comprising: a memory cell array including bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than said first logic data; and a sense amp circuit operative to detect data in a selected memory cell, said sense amp circuit including a sense node connected to a current source load, a clamp transistor connected between a bit line and said sense node and having a gate provided with a control voltage, said clamp transistor operative to set a clamp voltage on said bit line, and transfer to the sense node a voltage of the bit line that is dependent on data in a selected memory cell, wherein said sense amp circuit is operative to read data from said selected memory cell in at least first and second read cycles while said control voltage is applied to the gate of said claim transistor, and wherein different control voltages are applied to said gate of said clamp transistor in said first and second read cycles, without dropping the control voltage to a ground potential to turn off the clamp transistor upon transition from said first cycle to said second cycle.