Patent ID: 7439119

Claim:
A method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor in a semiconductor layer, comprising: forming MOSFET gate structures in a MOSFET region of a semiconductor layer; forming bipolar junction transistor structures, including an emitter material layer, in a bipolar junction transistor region of the semiconductor layer; forming a thermal barrier material layer overlying the emitter material layer; forming a hardmask material layer over the thermal barrier material layer; patterning the hardmask material layer using a mask to form a hardmask for patterning the thermal barrier material layer and the emitter material layer; patterning the thermal barrier material layer and the emitter material layer using the hardmask to form a patterned emitter; annealing the semiconductor layer which includes activating source/drain regions adjacent the gate structures in the MOSFET region of the semiconductor layer; and removing the thermal barrier layer material from the emitter material layer subsequent to the annealing.