Patent ID: 6882298

Claim:
A data converter on an intergrated circuit for converting to digital data analog data received on an analog signal ended data input terminal for receiving an external analog voltage referenced to an extended common reference voltage, comprising: a compactor having a signal input and a reference input, the reference input for receiving a predetermined reference voltage that is referenced to an internal common reference voltage internal to the integrated circuit; a switched capacitor array having a plurality of binary weighted capacitors for sampling the external analog voltage on the analog single ended data input ton on one or more of said capacitors during a sampling cycle and redistributing the charge thereon during a redistribution cycle to the remaining of said capacitors and applying the resulting voltage to the signal input of said compactor, which resulting voltage on the signal input is compared to the predetermined reference voltage; a SAR controller for selecting the ones of said capacitors utilized in said sampling cycle in accordance with a SAR algorithm to determine a corresponding digital value for the voltage on the respective positive or negative analog input terminal; and circuitry on said reference input operable to compensate for a difference between the external common reference voltage and the internal common reference voltage by offsetting the value of the predetermined reference voltage by a determined offset on the reference input of said comparator.