Patent ID: 7759701

Claim:
A semiconductor device, comprising: a semiconductor layer; a plurality of groups of contacts formed on a first side of the semiconductor layer, each group comprising at least three types of contacts, wherein the at least three types of contacts comprise a source contact, a drain contact, and a gate contact, or the at least three types of contacts comprise an emitter contact, a base contact, and a collector contact; an interconnecting layer formed directly on a second side of the semiconductor layer or directly on a passivation layer applied between the semiconductor layer and the interconnecting layer, the interconnecting layer being configured to provide an interconnect between said groups of contacts; and a substrate attached to the first side of the semiconductor layer on top of said gate, source, and drain contacts or base, emitter, and collector contacts, wherein each group comprises at least one gate contact formed between source and drain ohmic contacts, or each group comprises at least one base contact formed between emitter and collector ohmic contacts, and wherein the semiconductor layer is configured to define a plurality of vias connecting the first side with the second side, said vias being aligned at least with each of at least one type of ohmic contact in said plurality of groups such that said each of the at least one type of ohmic contact are connected by the interconnecting layer.