Patent ID: 8191028

Claim:
A method comprising: during a route phase for generating configuration information for an integrated circuit, the integrated circuit comprising a plurality of circuit elements, determining by using a computer device, whether a block of the integrated circuit is a non-critical block by determining whether a clock delay increases an operating frequency of the integrated circuit by a threshold value, wherein the clock delay is applied to the integrated circuit block; determining whether to split and/or splitting or demote demoting an initial clock signal to achieve a beneficial clock skew for the block of the integrated circuit; promoting the split and/or demoted clock signal in response to determining that the integrated circuit block is noncritical block and further in response to determining that said splitting and/or demoting is legal based on a number of resources of the integrated circuit in use, wherein said promoting comprises applying the initial clock signal to the integrated circuit block, wherein the initial clock signal comprises a global non-delayed clock signal; and interconnecting the plurality of circuit elements such that the first circuit element receives the split and/or demoted initial clock signal in response to determining that said splitting and/or demoting is legal.