Patent ID: 6963097

Claim:
A ferroelectric random access memory (FeRAM) capacitor, comprising: an active matrix including a semiconductor substrate, field oxide regions, a source/drain region, a first interlayer dielectric (ILD) and a storage node contact; a capacitor stack including a bottom electrode, a ferroelectric layer and a top electrode, wherein the bottom electrode, the ferroelectric layer and the top electrode are formed on the active matrix and a width of the capacitor stack is relatively larger than that of the storage node; a second ILD enclosing capacitor stack, wherein the top face of the top electrode is not covered with the second ILD and the top face of the top electrode is lower than the top face of the second IDL; and a plate line formed on the top face of the top electrode and predetermined portions of the second ILD, the width of the plate line being larger than that of the top electrode.