Patent ID: 7338860

Claim:
A method of forming a non-volatile memory device, the method comprising: providing a substrate having a cell region, a first peripheral region, and second peripheral region; forming a tunnel insulating layer on the substrate in the cell region; forming a preliminary floating gate on the tunnel insulating layer in the cell region; forming a blocking insulating layer on the substrate in the cell region, the first peripheral region, and the second peripheral region; forming a conductive layer on the blocking insulating layer in the cell region, the first peripheral region, and the second peripheral region; removing the conductive layer and the blocking insulating layer in the first and second peripheral regions to expose at least a portion of the substrate in the first and second peripheral regions, while leaving the conductive layer and the blocking insulating layer in the cell region; forming a first gate insulating layer on the exposed substrate of the first peripheral region; forming a second gate insulating layer on the exposed substrate of the second peripheral region; forming an undoped silicon layer on the substrate in the cell region, the first peripheral region, and the second peripheral region; doping the undoped silicon layer in the first peripheral region with impurities of a first-conductivity-type; doping the undoped silicon layer in the second peripheral region with impurities of a second-conductivity-type; and forming an etch stop layer having an etch selectivity with respect to the conductive layer on the blocking insulating layer in the cell region before forming the undoped silicon layer, wherein the etch stop layer is formed at the same time that the first and/or second gate insulating layers are formed, and the undoped silicon layer of the cell region is formed on the etch stop layer.