Patent ID: 6956405

Claim:
A teacher-pupil flip-flop, comprising: a teacher circuit, comprising: a gate circuit, having an output and having a plurality of inputs coupled to an intermediate node pair and receiving a clock signal, that switches after a setup delay in response to transitions of said clock signal between first and second states; a stack circuit, coupled to said gate circuit output and to an input data node, that switches said intermediate node pair to a preliminary state after said setup delay when said clock signal transitions to said first state, and that switches said intermediate node pair to a data state indicative of said input data node after said setup delay when said clock signal transitions to said second state; a keeper circuit coupled to said intermediate node pair; and a teacher output circuit, coupled to said intermediate node pair, that drives an output node indicative of said data state; and a pupil circuit, comprising: a latch circuit, coupled to said intermediate node pair, that stores said data state of said intermediate node pair; and a pupil output circuit, coupled to said latch circuit and receiving said clock signal, that drives said output node indicative of said data state after said clock signal transitions to said first state.