Patent ID: 7465623

Claim:
A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of: etching a first opening extending through the second semiconductor layer to expose a portion of the layer of insulator; filling the first opening with a dielectric material; implanting first type conductivity determining ions into the first semiconductor layer to form an impurity doped region of first conductivity type; depositing a layer of polycrystalline silicon overlying the dielectric material and the second semiconductor layer; patterning the layer of polycrystalline silicon to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region; etching a second opening and a third opening, each of the second opening and the third opening extending through the dielectric material and the layer of insulator, the second opening defined by the first mask region and the third opening defined by the second mask region; implanting first type conductivity determining ions into the doped region of first conductivity type through the second opening to form a first region of additional impurity doping of first conductivity type in the doped region of first conductivity type; implanting second type conductivity determining ions into the doped region of first conductivity type through the third opening to form a second impurity doped region of second conductivity type in the doped region of first conductivity type; and forming a first electrical contact to the first region of additional impurity doping and a second electrical contact to the second impurity doped region.