Patent ID: 8355326

Claim:
A CPU connection circuit comprising two buffers, the circuit being connected between two CPUs for relaying data transfer from at least one of the CPUs to the other one thereof, the CPU connection circuit comprising: a monitoring unit which monitors whether or not an amount of data stored by a transmission-side CPU in either one of the buffers reaches a predetermined threshold value; and a requesting unit which, when the amount of data stored by the transmission-side CPU in the buffer reaches the threshold value, (a) requests a reception-side CPU to acquire the data stored in the buffer, and (b) changes the data storage destination of the transmission-side CPU to the other one of the buffers, the threshold value being a value more than a unit quantity of data which the transmission-side CPU sends to the buffer, wherein when the transmission-side CPU changes the buffer as the data storage destination, if there remains, in the buffer after the change, data which are previously stored and which are not acquired by the reception-side CPU, an overrun signal is outputted to at least the reception-side CPU.