Patent ID: 8456214

Claim:
A circuit comprising: a pulse generator configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse; a storage structure comprising a storage element for storing a state and an isolation structure, said isolation structure being responsive to said asserted pulse to cause said storage element to update said stored state dependent on an input to said storage structure, and in the absence of said asserted pulse to isolate said storage element from said input, said pulse generator is responsive to a retention control signal to enter a retention mode of operation, during said retention mode of operation said pulse generator is configured to not assert the pulse irrespective of changes in said clock signal, whereby said isolation structure isolates said storage element from said input during said retention mode of operation, causing said storage element to retain said stored state prior to entry of the retention mode of operation irrespective of changes in said clock signal or changes in said input during said retention mode of operation; and at least one component which receives a voltage supply during a normal mode of operation, and has the voltage supply removed in a low power mode of operation such that an output of said at least one component becomes undefined during said low power mode of operation, wherein, prior to entering said low power mode of operation, said retention control signal is asserted to cause said pulse generator to enter said retention mode of operation, such that when said low power mode of operation is entered the stored state in said storage element is unaffected by the output of said at least one component becoming undefined.