Patent ID: 8253449

Claim:
A clock switch circuit comprising: a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks having different frequency dividing ratios; an output select signal generation circuit which outputs an output select signal according to a clock select signal having a value indicating a clock which is to be output, the output select signal specifying any one of a plurality of clocks including the plurality of frequency-divided clocks and the basic clock; and an output select circuit which selects any one of the plurality of clocks according to the output select signal to output the selected clock, wherein the frequency divide circuit outputs a plurality of frequency-divided count values corresponding to each of the plurality of frequency-divided clocks, the plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal to a value corresponding to the clock select signal at a timing at which start timing of a cycle of a frequency-divided clock selected as a next selection clock matches start timing of a cycle of a frequency-divided clock corresponding to a current selection clock based on a frequency-divided count value corresponding to the current selection clock among the plurality of frequency-divided count values.