Patent ID: 7776627

Claim:
A method for forming an integrated circuit structure, the method comprising: forming a first test wafer comprising: providing a first semiconductor substrate; forming a plurality of connection blocks, with at least one of the plurality of connection blocks comprising a plurality of metal pads in a plurality of metallization layers of the first test wafer, wherein the plurality of metal pads is vertically overlapped, and is interconnected through vias; forming a first plurality of unit blocks over the first semiconductor substrate, wherein at least one of the first plurality of unit blocks comprises a plurality of connection block cells arranged as an array, and wherein at least one of the connection block cells comprises two of the plurality of connection blocks, and a metal line connecting the two of the plurality of connection blocks; forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.