Patent ID: 8537601

Claim:
A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising: transmit circuitry to transmit, to the DRAM: write data to be sampled by the DRAM on one or more edges of the timing signal, the write data requiring a first time interval to propagate from the memory controller component to the DRAM; a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data; a plurality of delay elements coupled in series to respectively generate a plurality of incrementally delayed signals; and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.