Patent ID: 6845479

Claim:
A method of maximising the fault coverage on an integrated digital circuit by re-ordering a number of test vectors for testing the digital circuit, said method comprising: a) providing an initial set of test vectors T 0 ; b) providing an original set of faults F 0 ; c) selecting faults at pseudo-random from the original fault list to form a sample fault list F N ; d) forming a vector set T N−1 and simulating the vector set T N−1 against fault list F N ; e) discarding any vector from the vector set T N−1 which does not detect any faults; f) saving the remaining vectors as vector set T N ; g) repeating the above steps c) to f) M times with N having a value of 1 to M so that at the end of M steps, test vector sets T 1 to T M are saved; h) removing duplicate vector patterns in each vector set T N ; and i) saving the duplicate free vector set V N with N having a value 1 to M, initialising the final vector set and appending vector sets V M through V 0 to produce a final vector set T F .