Patent ID: 7111034

Claim:
A carry foreknowledge adder comprising: an adding circuit which adds binary numbers A and B of n bits; and a plurality of carry lookahead circuit blocks (j (j=0, 1, . . . , k−1)) that respectively corresponding to divisional portions A k-1 , A k-2 , . . . , A 0 and B k-1 , B k-2 , . . . , B 0 obtained by dividing said A and said B into integer k (k≧2) portions through setting m bits (2≦m<n) into a unit length, said carry lookahead circuit block preliminarily arithmetically determining each carry C i (i=0, 1, . . . , m−1) corresponding to each of bit A i and bit B i and outputting them to said adding circuit, wherein each carry lookahead circuit block (j) has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a carry C m-1 , as a block carry C in , corresponding to the most significant bit in a lower said carry lookahead circuit block (j−1) from said lower carry lookahead circuit block (j−1) corresponding to lower said divisional portion, each arithmetic operating portion arithmetically determining said carry C i on the basis of said block carry C in , and outputting said carry C i to said adding circuit, and said arithmetic operating portion (j, i) has a logic circuit portion which receives said block carry C in and is arranged on an output terminal side, said carry foreknowledge circuit block (j) further receives an H signal indicative of the high level and an L signal indicative of the low level, said arithmetic operating portions (j, i) include identical logic circuit portions, and said logic circuit portions includes a logic circuit portion which receives said H signal and a logic circuit portion which receives said L signal.