Patent ID: 8549234

Claim:
A memory controller providing a plurality of write ports that allow shared access to at least one memory device, the memory controller comprising: a plurality of write ports, at least one of the write ports having a clock frequency and comprising a data buffer having a plurality of storage locations, wherein said data buffer is configured to allow data to be written to at least a first number of its storage locations at a pre-determined time; and an arbiter having a clock frequency and configured to read data of a second bit width, the second bit width being greater than a first bit width, from a second number of storage locations of said data buffer at a pre-determined time and write the data that is read to at least one memory device, wherein the arrangement is such that the second number of storage locations read by the arbiter, a rate at which the second number of storage locations are read by the arbiter, the first number of storage locations written to said write ports and the rate at which the first number of storage locations of said write port are written to provide that a bandwidth of data read from said write port by the arbiter is greater than or equal to a bandwidth of data written to said write port.