Patent ID: 8850394

Claim:
A computer-implemented method of debugging a target processor, the method comprising: executing a series of debug instructions on an execution unit of the target processor to generate trace information for debugging, wherein the series of debug instructions includes a plurality of timestamp instructions; and during execution of said series of debug instructions on the execution unit, periodically incrementing a value of a counter on the target processor; wherein said step of executing said series of debug instructions on the execution unit comprises: executing the plurality of timestamp instructions on the execution unit each to associate a respective timestamp with said trace information, wherein the step of executing each timestamp instruction comprises: fetching the time stamp instruction from a memory holding the series of debug instructions, wherein the time stamp instruction includes opcode; generating the respective time stamp by reading the value of the counter into a software accessible storage location designated by the opcode; and subsequently resetting the counter as a consequence of the opcode read from the time stamp instruction.