Patent ID: 7533357

Claim:
A method of estimating an amount of decoupling capacitance required for an integrated circuit during an initial floorplanning design phase, with instructions embodied on a computer readable storage device configured to execute on a computer, comprising: obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of said integrated circuit; computing a minimum value for each of said voltage variation waveforms; selecting voltage variation waveforms below a minimum threshold value; performing a frequency domain analysis on said voltage variation waveforms below said minimum threshold value to create a set of frequency values and equating an imaginary component of said voltage variation waveforms to a reactance corresponding to a needed decoupling capacitance; wherein said performing of said frequency domain analysis comprises performing a fast fourier transform on each of said voltage variation waveforms to obtain frequency domain data, comprising filtering frequencies that cause a drop in voltage; performing a peak imaginary analysis on said frequency values to obtain a set of peak imaginary values; wherein said obtaining of said set of peak imaginary values comprises obtaining a frequency at which magnitude is maximum, a value of an imaginary component at said frequency at which magnitude is maximum, a frequency at which said imaginary component is maximum, and a peak value of said imaginary component; and calculating said amount of decoupling capacitance required using said peak imaginary values.