Patent ID: 7365953

Claim:
An emulator circuit for emulating a circuit component, the emulator circuit comprising: a first current mirror circuit having an input for receiving a load current and first and second outputs, where the current mirror circuit is configured to generate first and second current signals at the first and second outputs, respectively, responsive to the load current, where the first and second current signals are proportional to a square of the load current; a first comparator having a first input coupled to the first output of the current mirror circuit, a second input for receiving a first reference voltage, and an output for generating an up/down signal responsive a voltage at the first input compared to the reference voltage; a counter having an up/down control input coupled to the output of the first comparator, a clock input, and an output for outputting a count value of the counter; a transfer function circuit having an input for receiving the count value of the counter and an output for generating a third current signal, where the transfer function circuit is configured to generate the third current signal responsive to the count value modified by a predetermined transfer function; an absolute value circuit having an input and an output, where the input of the absolute value circuit is electrically coupled to the first output of the first current mirror circuit; a current controlled oscillator circuit having a first input coupled to the output of the absolute value circuit, a second input coupled to an external interface terminal for electrical connection to a capacitor, and an output coupled to the clock input of the clock circuit, where the oscillator is configured to generate a clock signal at its output that has a frequency that is determined by the capacitor coupled to the second input of the oscillator and a current present at the first input of the oscillator; and a second current mirror circuit having an input coupled to the output of the transfer function circuit, a first output coupled to the input of the absolute value circuit, and a second output coupled to the first input of the first comparator, where the second current mirror circuit is configured to generate fourth and fifth current signals that are proportional to the third current signal at the first and second outputs, respectively.