Patent ID: 6948051

Claim:
A multistage microprocessor pipeline structure for executing instructions comprising: an instruction cache, a decoder, a register file, an arithmetic logic unit, and a cache memory, said register file, arithmetic logic unit (ALU) and cache memory organized as a plurality of slices adapted to be enabled selectively depending on a width of instruction operands and operation results, each slice comprising a reduced bit width portion of said register file, a reduced bit width portion of said arithmetic logic unit, and a reduced bit width portion of the cache memory, wherein all of said slices are enabled to operate in parallel when a full bit width processing operation is executed, or, only a minimum required number of slices are enabled to operate if an operation is determined to be narrower than full bit width, one or more said slices being enabled for operation on a cycle-by-cycle basis during the execution of instructions, whereby instructions from said instruction cache and decoded for operation by the decoder, and registers used in the operation are detected and register contents are input to the arithmetic logic unit which executes the instruction, said microprocessor pipeline structure further comprising: a register value information means for receiving from said decoder an identity of registers used in the operation, and outputting information about values included in those registers; and, a width determination means for receiving outputs from said decoder and said register value information means, and generating one or more width control signals used to enable said one or more slices required for execution of the operation, wherein only those slices enabled access simultaneously corresponding portions of said register file whose contents are needed for execution of the operation; said contents being input in parallel to the portions of the arithmetic logic unit which execute the operation, and said ALU results generated are written in parallel to said portions of said register file selected to receive those results.