Patent ID: 8106873

Claim:
A gate pulse modulation (GPM) circuit usable in a liquid crystal display (LCD), comprising: (a) a low dropout (LDO) regulator, LDO_O; (b) a first resistor, R Cset , having a first terminal electrically connected to the LDO regulator LDO_O and a second terminal electrically connected to a node, DTS, respectively; (c) a capacitor, C set , having a first terminal electrically connected to the second terminal of the first resistor R Cset and a second terminal electrically connected to the ground, respectively; (d) a switch, SW, have a control terminal, a first terminal electrically connected to the node DTS and a second terminal; (e) a second resistor, R DTS , having a first terminal electrically connected to the second terminal of the switch SW and a second terminal electrically connected to the ground, respectively; (f) a comparator having a first input electrically connected to the node DTS, a second input for receiving a voltage signal, Vref, and an output electrically connected to the control terminal of the switch SW, respectively; (g) a level shifter having N inputs for receiving N clock signals, {CKj}, respectively, and N outputs for outputting N modulated clock signals, {CKHj}, respectively, j=1, 2, 3, . . . N, N being an even integer greater than zero; (h) a logic control unit having a first input for receiving the N clock signals, {CKj}, a second input electrically connected to the output of the comparator and an output; (i) N switches, {Sj}, each switch Sj having a control terminal electrically connected to the output of the logic control unit, a first terminal electrically connected to a respective output of the level shifter, and a second terminal; (j) a third resistor, R O , having a first terminal electrically connected to the second terminal of each odd switch, Sk, k=1, 3, 5, . . . , N-1, of the N switches {Sj} and a second terminal electrically connected to the ground, respectively; and (k) a fourth resistor, R E , having a first terminal electrically connected to the second terminal of each even switch, Sq, q=2, 4, 6, . . . N, of the N switches {Sj} and a second terminal electrically connected to the ground, respectively.