Patent ID: 7696558

Claim:
A semiconductor memory device, comprising: a substrate; a semiconductor layer of a first conductive type isolated from said substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in said semiconductor layer, the second conductive type being of an opposite conductive type to said first conductive type, and a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body; an impurity-diffused region of said first conductive type formed at a location in contact with the upper surface of said drain region, said impurity-diffused region having a higher impurity concentration of said first conductive type than an impurity concentration of said second conductive type in said drain region; a write transistor including a bipolar transistor having said impurity-diffused region as an emitter region, said drain region as a base region and said channel body as a collector region, the emitter region being spaced from the channel body with the drain region sandwiched therebetween, said write transistor operative to write data in said memory transistor; and an emitter plug connected to said drain region, wherein said impurity-diffused region is formed in said drain region shallower than said drain region, and said impurity-diffused region is formed to contain an impurity of said first conductive type diffused from inside said emitter plug to said drain region.