Patent ID: 7781818

Claim:
A semiconductor construction, comprising: a semiconductor substrate; a plurality of capacitor storage nodes supported by the substrate, individual storage nodes being shaped as hollow tubes extending upwardly from the substrate, the tubes having first ends proximate the substrate and second ends in opposing relation to the first ends; the second ends having upper portions, lower portions below the upper portions, and steps connecting the upper and lower portions to one another; the tubes having inner surfaces along their interiors and outer surfaces along their exteriors; the tubes extending in an array comprising rows and columns; the second ends of individual tubes having lengths defined by the lengths of the steps, and such lengths of the second ends of the individual tubes extending less than one-fourth of total lengths of the individual tubes; retaining structures against the upper portions of the second ends and not against the lower portions of the second ends; the retaining structures extending between and connecting alternating pairs along the rows of storage nodes of the array; a dielectric material along the inner and outer surfaces of the tubes, the dielectric material being in physical contact with the inner and outer surfaces of the upper and lower portions of the second ends; an electrically conductive material along the inner and outer surfaces of the tubes and over the dielectric material and in direct physical contact with the dielectric material and capacitively connected with the storage nodes, the electrically conductive material being capacitively connected with both the inner and outer surfaces of the upper and lower portions of the second ends; wherein, the second ends of the storage nodes have round peripheries; the upper portions of the second ends comprise about one-half of the round peripheries of the second ends; and the lower portions of the second end comprise about one-half of the round peripheries of the second ends.