Patent ID: 7243321

Claim:
An integrated circuit (IC) physical verification method comprising the steps of: a. processing layout data describing positions of conductive material residing on layers of an IC including a drawn inductor having a spiral to produce recognition layer data representing a two-dimensional boundary shape of the spiral that is a composite of two-dimensional shapes of all conductive material forming the spiral; and b. processing the recognition layer data to generate parameter data describing a shape of the spiral the shape being divided into a plurality of polygonal segments for separate processing relating thereto; wherein the drawn inductor includes a center tap or spoke coupled to the spiral, the layout data includes first binary data corresponding respectively to layers upon which conductive material forming the spiral and the center tap or spoke reside, the recognition layer data comprising second binary data generated as a Boolean function of portions of the first binary data; and wherein the second binary data distinguishes positions of all conductive material forming the spiral from positions of any conductive material forming the center tap or spoke, the processing thereby determining an area of overlap between the center tap or spoke and spiral.