Patent ID: 7619901

Claim:
An electronic module comprising: a chip layer including: at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; a structural material surrounding and physically contacting the at least one side surface of each chip of the at least one chip of the chip layer, the structural material having an upper surface substantially co-planar with or parallel to an upper surface of each chip of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of each chip of the at least one chip and defining at least a portion of a back surface of the chip layer; and a plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer; an interconnect layer disposed over the front surface of the chip layer, the interconnect layer including at least one interconnect metallization electrically connected to one or more conductive structures of the plurality of conductive structures extending between the front surface and back surface of the chip layer, wherein the interconnect layer connects to a contact pad of the at least one contact pad of the at least one chip; a redistribution layer disposed over the back surface of the chip layer, the redistribution layer including at least one redistribution metallization electrically connected to the one or more conductive structures of the plurality of conductive structures extending between the front and back surface of the chip layer; and a plurality of input/output contacts disposed over the back surface of the chip layer, including over the lower surface of a chip of the at least one chip, and electrically connected through the at least one redistribution metallization, one or more conductive structures, to the at least one interconnect metallization over the at least one chip of the chip layer.