Patent ID: 7382170

Claim:
A programmable delay circuit, comprising: a plurality of delay blocks connected together so as to form a series chain, an input of a first one of the plurality of delay blocks forming an input of the programmable delay circuit and being adapted to receive a first signal supplied to the programmable delay circuit; a plurality of tri-state drivers, each of the tri-state drivers including an input connected to an output of a corresponding one of the delay blocks, and a control input adapted to receive one of a plurality of control signals, the tri-state driver being operative in one of at least a first mode and a second mode as a function of a corresponding one of the control signals, wherein in the first mode an output signal generated at an output of the tri-state driver is a function of a voltage level at the input of the tri-state driver, and in the second mode the output of the tri-state driver is in a high-impedance state, the output of each of the tri-state drivers being coupled together and forming an output of the programmable delay circuit; at least one decoder connected to the plurality of tri-state drivers, the decoder including at least one control input for receiving at least a second signal and being operative to generate the plurality of control signals for selectively activating a corresponding one of the tri-state drivers as a function of the second signal; and an input circuit including: synchronization circuitry, the synchronization circuitry having a first input adapted to receive a third signal and a second input adapted to receive at least a portion of the first signal; and logic circuitry having a first input connected to an output of the synchronization circuitry, a second input adapted to receive the first signal, and an output connected to the input of a first one of the plurality of tri-state drivers; wherein the input circuit is operative to synchronously force the output of the programmable delay circuit to one of a logic high level and a logic low level as a function of the third signal; wherein a delay between the input and the output of the programmable delay circuit is controlled as a function of the second signal.