Patent ID: 8310473

Claim:
A semiconductor device comprising: a first input terminal electrically connected to a source/drain of a 1st transistor and a gate of a 6th transistor, a gate of a 2nd transistor being electrically connected to a drain/source of the 1st transistor; a second input terminal electrically connected to a gate of a 3rd transistor and a source/drain of a 4th transistor, a drain/source of the 4th transistor being electrically connected to a gate of a 5th transistor; a source/drain of the 3rd transistor electrically connected to a drain/source of the 2nd transistor and a gate of a 9th transistor, a source/drain of the 9th transistor being electrically connected to a drain/source of an 8th transistor; a source/drain of the 6th transistor electrically connected to a drain/source of the 5th transistor and a source/drain of a 7th transistor, a drain/source of the 7th transistor being electrically connected to a gate of the 8th transistor; a first power supply electrically connected to a source/drain of the 2nd transistor, a source/drain of the 5th transistor, and a gate of the 7th transistor; a second power supply electrically connected to a drain/source of the 3rd transistor, a drain/source of the 6th transistor, and a drain/source of the 9th transistor.