Patent ID: 7579870

Claim:
A level shifter for receiving a pair of input signals varying with complementary levels and shifting the levels of the pair of input signals, comprising: a pair of input transistors having a pair of sources connected in common to a first input reference node and a pair of gates to which the pair of input signals are input; a pair of input-side voltage relaxing transistors having a pair of sources connected to a pair of drains of the pair of input transistors and a pair of gates connected in common to a second input reference node, and for limiting voltages at the pair of drains of the pair of input transistors; a pair of output nodes; a pair of output-side voltage relaxing transistors having a pair of sources connected to the pair of output nodes, a pair of gates connected in common to a first output reference node, and a pair of drains connected to the pair drains of the pair of input-side voltage relaxing transistors, and for limiting voltages at the pair of output nodes; and a first inverter circuit and a second inverter circuit in one-to-one correspondence with the pair of output nodes and each connected between a second output reference node and a third output reference node, wherein each of the first and second inverter circuits supplies a voltage at one of the second and third output reference nodes to one corresponding to said inverter circuit of the output nodes, depending on a voltage at one not corresponding to said inverter circuit of the output nodes.