Patent ID: 8199557

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate and including a plurality of first wires, a plurality of second wires formed so as to cross the first wires, and memory cells disposed at intersections of the first wires and the second wires and each having a rectifier element and a variable resistive element connected in series; and a control circuit configured to selectively drive the first wires and the second wires, the control circuit executing a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state, and at a time of executing the resetting operation, the control circuit increasing a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreasing the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.