Patent ID: 7489010

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a cell array formed on the semiconductor substrate with NAND cell units arranged therein, the NAND cell unit having plural non-volatile semiconductor memory cells connected in series and first and second select gate transistors disposed at both ends thereof, one block including a set of the NAND cell units arranged in a first direction, a plurality of the blocks being arranged in a second direction in such a manner that common drains of the first select gate transistors in adjacent blocks serve as bit line contacts while common sources of the second select gate transistors in the following adjacent blocks serve as source line contacts; word lines formed as elongated in the first direction of the cell array, to which control gates of a plurality of the memory cells arranged in the first direction are coupled in common; first select gate lines formed as elongated in the first direction of the cell array, to which gates of a plurality of the first select gate transistors arranged in the first direction are coupled in common; second select gate lines formed as elongated in the first direction of the cell array, to which gates of a plurality of the second select gate transistors arranged in the first direction are coupled in common; and first and second shunt wirings formed above the first and second select gate lines, respectively, wherein two first select gate lines in adjacent blocks sandwiching the bit line contacts are formed to have first connection portions disposed at a certain pitch, the two first select gate lines being connected to each other at the first connection portions; two second select gate lines in adjacent blocks sandwiching the source line contacts are formed to have second connection portions disposed at substantially the same pitch as the first connection portions, the two second select gate lines being connected to each other at the second connection portions; and the first and second shunt wirings are contacted with the first and second select gate lines at the first and second connection portions, respectively.