Patent ID: 7391660

Claim:
An address path circuit with a row redundant scheme, comprising: an address buffer for buffering an external address to output an internal address; a command buffer for buffering a plurality of external commands; a pre-latch unit for pre-latching the internal address from the address buffer using a specific one of the commands buffered by the command buffer to output a pre-latched internal address; a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection; an address latch unit for latching the internal address from the address buffer synchronously with a buffered clock to output a latched internal address; and a global address generator for receiving the detection signals from the detector and the latched internal address from the address latch unit and generating a global row address, the global address generator outputting the latched internal address from the address latch unit as the global row address when the detection result of the detector indicates that the pre-latched internal address from the pre-latch unit is the normal address, and an encoded address obtained by encoding the detection signals as the global row address when the detection result of the detector indicates that the pre-latched internal address is the repaired address.