Patent ID: 7523266

Claim:
A method for enforcing memory reference ordering requirements at a Level 1 (L1) cache in a multiprocessor, comprising: receiving an invalidation signal for a cache line at the L1 cache while executing instructions in a speculative-execution mode, wherein the invalidation signal is received from a cache-coherence system within the multiprocessor; in response to the invalidation signal, if the cache line exists in the L1 cache, examining a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during the speculative-execution mode, and if the load-mark is set, failing the speculative-execution mode and resuming a normal-execution mode from a checkpoint, whereby failing the speculative-execution mode ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.