Patent ID: 7836324

Claim:
An apparatus to synchronously communicate on an interface that has an associated interface clock, the apparatus for a circuit that has an internal clock used internal to the circuit, the apparatus comprising: a first latch coupled to receive data; a second latch coupled in parallel with the first latch to receive the data; a first clock gater coupled to receive the internal clock and a first clock enable, wherein the first clock gater is coupled to the first latch to provide a clock to the first latch; a second clock gater coupled to receive an inversion of the internal clock and a second clock enable, wherein the second clock gater is coupled to the second latch to provide a clock to the second latch; and a control circuit coupled to receive the internal clock and the interface clock, wherein the control circuit is configured to capture a plurality of samples of the interface clock for each clock cycle of the internal clock, and wherein the control circuit is configured to generate the first clock enable and the second clock enable responsive to the plurality of samples.