Patent ID: 6928532

Claim:
A re-programmable logic integrated circuit comprising: a CPU core provided with registers, memories and a controller for the registers and memories; wherein the CPU core having instructions including microcode; and wherein the controller having control lines for outputting enable signal to the registers and memories, the controller reading reads in an instruction of the instructions, and transmitting ON/OFF information for each of bits composing the microcode included in the instruction to ones of the registers and memories allocated to each of the bits, thereby controlling the registers and memories through the directing control lines wherein the CPU core has address pointer registers used in accessing the memories; wherein the controller has directing control lines for giving either direction of increment and decrement to the address pointer registers, reads in the instructions, and transmits ON/OF information for each of bits for giving either direction of increment and decrement to the address pointer resisters in microcode included in the instruction through the directing control lines; and wherein the address pointer resisters counts up or counts down values or maintaining addresses when receiving ON information about the bits for giving either direction of increment and decrement from the controller through the directing control lines.