Patent ID: 7107437

Claim:
A method, comprising: speculatively allocating a first branch entry for a conditional branch in a speculative branch target buffer (SBTB) prior to execution of the conditional branch responsive to decoding the conditional branch and finding no branch entry in an architectural branch target buffer (ABTB) corresponding to the conditional branch, wherein the SBTB and the ABTB are included in a branch target buffer (BTB) to eliminate a speculative history from the ABTB; speculatively allocating a second branch entry for the conditional branch in the SBTB responsive to a subsequent failed attempt to locate a branch entry in the ABTB corresponding to the conditional branch; allocating a third branch entry for the conditional branch in the ABTB after retirement of the conditional branch; and subsequently performing branch prediction for the conditional branch by determining a predicted target address branch based upon branch data associated with the second branch entry.