Patent ID: 7345369

Claim:
A semiconductor device comprising: a base member; a solder layer; and a semiconductor chip disposed on the base member through the solder layer, wherein the chip has an in-plane temperature distribution when the chip is operated, the chip has an allowable maximum temperature as a temperature limit of operation, the in-plane temperature distribution of the chip provides a temperature of the chip at each position of a surface of the chip, a temperature margin at each position is obtained by subtracting the temperature of the chip from the allowable maximum temperature, the solder layer has an allowable maximum diameter of a void at each position, the void being disposed in the solder layer, the allowable maximum diameter of the void at each position becomes larger as the temperature margin at the position becomes larger, the solder layer has an in-plane allowable maximum diameter distribution of the void, which is obtained by applying a relationship between the allowable maximum diameter of the void and the temperature margin at each position to the in-plane temperature distribution of the chip, the in-plane allowable maximum diameter distribution of the void has a maximum diameter at a periphery portion of the chip, the in-plane allowable maximum diameter distribution of the void has a minimum diameter at a center portion of the chip, and a thickness of the solder layer is equal to or larger than the minimum diameter in the in-plane allowable maximum diameter distribution of the void at the center portion of the chip.