Patent ID: 7941775

Claim:
A method, performed on a computer system, for determining an effect of noise on a digital integrated circuit having at least one logic gate, the method comprising: using the computer system to perform the following: performing a timing analysis on the at least one logic gate; performing a noise analysis on the at least one logic gate; dynamically synthesizing a waveform propagation model as a function of the timing analysis, wherein the waveform propagation model contains a representation of how noise impacts the timing analysis of the at least one logic gate, wherein the dynamically synthesizing of the waveform propagation model comprises determining a low-pass filtering effect of the at least one logic gate, and determining a non-linear element of the at least one logic gate as a function of a voltage waveform outputted from the at least one logic gate during the timing analysis and the response that the low-pass filtering effect has on a voltage waveform inputted to the at least one logic gate during the timing analysis; applying an arbitrary voltage waveform derived from the noise analysis to the dynamically synthesized waveform propagation model; and determining an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.