Patent ID: 7503024

Claim:
A method for hierarchical VLSI mask layout data interrogation, comprising: creating a tree data structure of a layout hierarchy, the tree data structure including at least a first layout shape and a second layout shape; displaying the tree data structure; receiving a first selection comprising the first layout shape; displaying a layout graphical representation through the tree data structure of the first layout shape; displaying a first text description of a hierarchical location associated with the first layout shape; receiving a second selection comprising the second layout shape; displaying a layout graphical representation through the tree data structure of the second layout shape; displaying a second text description of a hierarchical location associated with the second layout shape; generating a textual difference, the textual difference including a visually depicted difference, wherein the visually depicted difference includes at least a portion of the second text description that does not match the text in the first text description; and displaying the textual difference.