Patent ID: 6838342

Claim:
A method for manufacturing an integrated circuit, the method comprising: (1) obtaining a structure comprising: a semiconductor substrate having a plurality of first areas which are to include one or more active areas of one or more nonvolatile memory cells; one or more dielectric regions for providing isolation between at least two of the first areas, each dielectric region having a portion below the top surface of the substrate, the dielectric regions rising above the substrate, each dielectric region having a sidewall abutting at least one of the first areas, wherein at least a top portion of the sidewall is exposed; a first conductive layer over the one or more first areas, the first conductive layer being insulated from the one or more first areas, the first conductive layer providing a first portion of a conductive floating gate for each nonvolatile memory cell; (2) removing material from at least the top exposed portion of each sidewall of each said dielectric region, to recess the top portion of the sidewall laterally away from the adjacent first portion of the floating gate; (3) forming a second conductive layer over the one or more first areas, the second conductive layer contacting the first conductive layer and providing a second portion of the floating gate for each nonvolatile memory cell, the second conductive layer abutting the top recessed sidewall portions of said dielectric regions.