Patent ID: 8074130

Claim:
A test apparatus that tests a memory under test, comprising: a test section that executes testing of each cell of the memory under test; a fail information storage section that stores fail information corresponding to each cell of the memory under test that indicates pass/fail of the cell in a fail memory; a counting section that counts a number of defective cells detected in each block for every block in the memory under test, a block being a unit that can be replaced with a backup storage region when a defect occurs; a reading request receiving section that receives a reading request to read the fail information corresponding to each cell included in a reading target block; a comparing section that compares the number of defective cells in the reading target block to a predetermined reference number and outputs a comparison result; a converting section that receives the read fail information and the comparison result and outputs modified fail information, of the same size as the read fail information, in which, in a case where the number of defective cells in the reading target block exceeds the predetermined reference number, one or more pieces of fail information indicating pass among the read fail information are converted into fail information indicating fail; and a compressing section that compresses the modified fail information and returns the compressed fail information.