Patent ID: 8041754

Claim:
An apparatus comprising: a plurality of APIC TPR registers for each of a plurality of threads wherein execution of operating system code causes values to be stored in said registers to indicate which of the plurality of threads to be executed by the processor has a higher priority; a resource allocated between said plurality of threads depending on a priority assigned to each thread in said registers; control logic coupled to said resource; and a counter coupled to said control logic, wherein a value is set for each thread depending on the priority assigned to each thread, and said counter is to be loaded with one of said set values by said control logic, such that one of said threads with a higher priority is to be allocated a greater number of instructions processed by the resource than another of said threads with a lower priority based on a counting operation on the set value loaded into said counter, wherein said resource is selected from a group consisting of: a decode unit, a trace cache/MSROM, a rename/allocation unit, an execution unit, a retire unit, and a bus.