Patent ID: 8284583

Claim:
A semiconductor memory device comprising: sense amplifiers that drive bit lines to which memory cells are connected; and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitute a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitute at least one transistor row comprised of aligned alternating adjacent first and second conductive type well regions and including both first driver transistors of the first conductive type corresponding to the first sense-amplifier row and second driver transistors of the second conductive type corresponding to the second sense-amplifier row such that a second conductive type well region of said first driver transistors is located in line with and adjacently between two first conductive type well regions of two said second driver transistors, the at least one transistor row being located between the first sense-amplifier row and the second sense-amplifier row.