Patent ID: 7266032

Claim:
A memory device comprising: a memory bank; a first group of cell blocks in the memory bank; a second group of cell blocks in the memory bank, wherein each cell block of the first group shares at least one sense amplifier with a cell block of the second group; and control circuitry configured to: simultaneously activate each cell block of the first group while the cell blocks of the second group are left deactivated, wherein activating each cell block of the first group comprises connecting the cell block of the first group to the at least one sense amplifier shared with the second group; while the cell blocks of the first group are activated and the cell blocks of the second group are deactivated, refresh each memory cell in the first group; simultaneously activate each cell block of the second group while the cell blocks of the first group are left deactivated, wherein activating each cell block of the second group comprises connecting the cell block of the second group to the at least one sense amplifier shared with the first group; and while the cell blocks of the second group are activated and the cell blocks of the first group are deactivated, refresh each memory cell in the second group.