Patent ID: 8320163

Claim:
An integrated circuit structure comprising: a first static random access memory (SRAM) cell comprising a first read-port and a first write-port; a second SRAM cell comprising a second read-port and a second write-port, wherein the first SRAM cell and the second SRAM cell are in a same row and are arranged along a row direction; a first word-line coupled to the first SRAM cell; a second word-line coupled to the second SRAM cell; a read bit-line coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction; and a write bit-line coupled to the first SRAM cell and the second SRAM cell, wherein each of the first SRAM cell and the second SRAM cell comprises: a write-port pass-gate transistor; and a read-port pass-gate transistor, wherein the read-port pass-gate transistor of the first SRAM cell and the write-port pass-gate transistor of the second SRAM cell are connected to the first word-line, and wherein the read-port pass-gate transistor of the second SRAM cell and the write-port pass-gate transistor of the first SRAM cell are connected to the second word-line.