Patent ID: 8105874

Claim:
A method for producing an integrated circuit arrangement, in which the following steps are performed without any restriction by the order specified: fabricating an integrated memory cell array on a memory cell array substrate using a first sequence of method steps; fabricating an integrated logic circuit that provide basic functions of the memory cell array on a logic circuit substrate, which is separate from the memory cell substrate, using a second sequence of method steps, which differs from the first sequence, wherein the logic circuit substrate has a sense amplifier, with the aid of which a memory state of a memory cell of the memory cell array can be determined; the logic circuit substrate has a circuit arrangement of a processor which is suitable for processing instructions and the cell array substrate has an analog circuit; arranging the integrated memory cell array and the integrated logic circuit to form a memory circuit arrangement; wherein the logic circuit includes at least one of: a control circuit contained in the memory circuit, the control circuit controlling sequences when at least one of reading or writing content of a memory cell of the memory cell array, or a decoding circuit contained in the memory circuit, the decoding circuit selects, in a manner dependent on an address datum, a word line or a bit line connected to a plurality of memory cells of the memory cell array.