Patent ID: 8887017

Claim:
A processor, comprising: a test controller unit (TCU) test access port (TAP) for enabling access of a TCU to internal modules of the processor for running functional tests of the modules; a debug access port (DAP) TAP for enabling access of a debugger to the processor to debug and program software in the processor; a TAP selection module for selection of TAP access by default through said TCU TAP when the processor is a bare die, or by default through said DAP TAP when the processor is packaged, wherein said TAP selection module is controllable to select reversibly said TAP access through said TCU TAP or through said DAP TAP by values of a TAP switch signal controllable by said TCU from an external pin of the processor and provided through said TCU TAP or DAP TAP through which said TAP selection module is acting; and a fuse for irreversibly disabling said selection by said TAP selection module of said TAP access by default through said TCU TAP.