Patent ID: 8407715

Claim:
A method of optimizing multi-set context switch for embedded processors, comprising the steps of: partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the plurality of registers; storing contents of first target registers according to live set information of a current task stored in a live-set-information register, wherein the first target registers are selected from the register sets; determining a next task by an operating system and updating the live set information stored in the live-set-information register according to the next task; and restoring contents of second target registers according to the updated live set information stored in the live-set-information register, wherein the second target registers are selected from the register sets, and wherein the live-range-sensitive context-switch procedure comprises the steps of: providing a base set comprising the plurality of registers and dividing the plurality of registers into a plurality of subsets, wherein the plurality of subsets are arranged in order; setting each of the subsets empty; providing a key subset comprising a longest-live register having the longest live time which is selected from the registers in the base set; generating a first system cost associated with the plurality of register sets; forming a second temporary subset using the key subset excluding the longest-live register and forming a first temporary subset using a preceding subset of the key subset union with the longest-live register; generating a second system cost associated with the first temporary subset, the second temporary subset and other subsets excluding the key subset and the preceding subset; updating the subsets according to the result of comparing the first system cost with the second system cost; and forming the register sets according to the subsets; wherein the register sets are arranged in order with the usage frequency of each of the register sets.