Patent ID: 7692251

Claim:
A transistor for a semiconductor device comprising: a semiconductor substrate comprising a first active region, a second active region, a third active region, and a device isolation film, wherein the first active region, the second active region and the third active region are disposed in the semiconductor substrate in parallel; a first gate region disposed on the device isolation film, wherein the first gate region intersects the first active region and the second active region; a first recess gate region formed in the device isolation film in the first gate region, wherein the first recess gate region exposes a first sidewall of the first active region and a sidewall of the second active region, the first sidewall of the first active region facing the sidewall of the second active region; a second gate region disposed on the device isolation film, wherein the second gate region intersects the first active region and the third active region; a second recess gate region formed in the device isolation film in the second gate region, wherein: the second recess gate region exposes a second sidewall of the first active region and a sidewall of the third active region, the second sidewall of the first active region faces the sidewall of the third active region, and the first recess gate region and the second gate region are alternately disposed in the device isolation film in parallel such that that the first recess gate region does not overlap the second recess gate region in a longitudinal direction of the first active region; a gate insulating film disposed on a surface of each active region and the sidewall of each active region exposed by the first and second recess gate regions; and a gate structure disposed on the gate insulating film of each active region and the device isolation film of each gate region.