Patent ID: 7501307

Claim:
A method of fabricating a semiconductor memory device, comprising: (a) forming a transistor on a substrate; (b) forming a first interlayer insulating layer on the substrate to cover the transistor; (c) forming a contact hole through the first interlayer insulating layer to expose a predetermined area of the transistor; (d) forming a conductive plug within the contact hole; (e) forming a second interlayer insulating layer over the first interlayer insulating layer; (f) forming a heating portion in the second interlayer insulating layer; (g) forming a chalcogenide material layer on the heating portion; and (h) forming a metal interconnection layer on the chalcogenide material layer, wherein forming the heating portion in the second interlayer insulating layer includes: forming a via hole through the second interlayer insulating layer to expose the conductive plug; forming an insulation film on the second interlayer insulating layer to cover inner walls of the via hole; forming a spacer within the via hole by etching the insulation film until the second interlayer insulating layer is exposed; and forming a heating material layer inside the spacer.