Patent ID: 8553811

Claim:
A likelihood value calculation device comprising: a likelihood value calculation unit comprising a processor that: takes as input an equalization signal of a modulated signal that is prescribed by a constellation in which signal points are mapped onto a two-dimensional plane composed of an I-axis and a Q-axis, and moreover, in which a value composed of a bit sequence is assigned to each signal point; selects according to a first control signal one or both of the I-axis component and Q-axis component of said equalization signal that was received as input; and, based on the selected component, calculates a provisional likelihood value in which the bit value of each of said signal points is 0 for each bit position of said bit sequence; an arithmetic inversion unit that, according to a second control signal, supplies as output without alteration the provisional likelihood value that was supplied as output from said likelihood value calculation unit for each of said bit positions, or subjects the provisional likelihood value that was supplied from said likelihood value calculation unit to arithmetic inversion based on inversion positions that are designated on said two-dimensional plane and supplies the likelihood value that follows inversion as output; and an operation control unit that holds, for each combination of a radio mode and a modulation mode, a control pattern that is used to control operations of at least said likelihood value calculation unit and said arithmetic inversion unit and that generates said first and second control signals in accordance with a control pattern that was designated from among the held control patterns, said radio mode being defined based on a communication system standard.