Patent ID: 7501860

Claim:
A differential input driver circuit ( 10 , 50 ) comprising: a first transistor (Q 0 ) having a first current handling terminal ( 24 , 64 ) coupled to receive a first differential input signal (In+), a second current handling terminal ( 16 , 56 ) coupled to receive a first current (I 0 ) and a control terminal ( 20 , 60 ), the second current handling terminal providing a first differential output signal (Vo+); a first resistor (R 0 ) coupled between the first current handling terminal ( 24 , 64 ) of the first transistor and a first power supply voltage ( 14 , 52 ); a second transistor (Q 3 ) having a first current handling terminal ( 26 , 66 ) coupled to receive a second differential input signal (In−), a second current handling terminal ( 18 , 58 ) coupled to receive a second current (I 3 ) and a control terminal ( 22 , 62 ), the second current handling terminal providing a second differential output signal (Vo−); a second resistor (R 1 ) coupled between the first current handling terminal ( 26 , 66 ) of the second transistor and the first power supply voltage; a third transistor (Q 1 ) having a first current handling terminal coupled to the first current handling terminal ( 26 , 66 ) of the second transistor (Q 3 ), and a control terminal connected to the second current handling terminal ( 20 , 60 ) and to the control terminal of the first transistor and receiving a third current (I 1 ); a fourth transistor (Q 2 ) having a first current handling terminal coupled to the first current handling terminal ( 24 , 64 ) of the first transistor, and a control terminal connected to the second current handling terminal ( 22 , 62 ) and to the control terminal of the second transistor and receiving a fourth current (I 2 ), wherein the first, second, third and fourth transistors are all of a first polarity type.