Patent ID: 8743049

Claim:
An electrophoretic display device configured such that an electrophoretic element is sandwiched between a pair of substrates and including a display section having a plurality of pixels arranged therein, the electrophoretic display device comprising: a controller for controlling the display section; scanning lines, data lines, power supply lines and enable lines provided in the display section, the scanning lines, the data lines, the power supply lines and the enable lines being connected to the pixels; an enable line control circuit having switch circuits provided so as to correspond to a plurality of the enable lines, and a first power supply line and a second power supply line connected to the enable line control circuit; and in each of the pixels, a pixel electrode, a control transistor connected to one of the scanning lines and one of the data lines, a driving transistor having a gate connected to a drain of the control transistor and having a drain connected to one of the power supply lines, a storage capacitor connected to the gate and a source of the driving transistor, and an enable transistor connected between the source of the driving transistor and the pixel electrode, the enable transistor switching electrical connection between the pixel electrode and the driving transistor on the basis of a signal input through one of the enable lines, wherein the controller performs, when displaying an image on the display section, an initialization driving operation for initializing a source potential and a gate potential of the driving transistor to have a certain potential relationship, a threshold voltage correcting operation for correcting a threshold voltage of the driving transistor, a mobility correcting operation for correcting mobility of the driving transistor, and an image displaying operation for driving the electrophoretic element, the controller turns on the enable transistor to correct the plurality of the pixels to a given gradation during the initialization driving operation, further wherein one of the switch circuits has a first transistor inserted between one of the enable lines and the first power supply line, and a second transistor inserted between the enable line and the second power supply line, and a gate of the first transistor is connected to a first one of the scanning lines to which the switch circuit belongs, and a gate of the second transistor is connected to a second one of the scanning lines that is different from the first scanning line.