Patent ID: 7902656

Claim:
A semiconductor device including a first power amplifying system (e) and a second power amplifying system (f), comprising: (a) a wiring substrate having a main surface and a back surface which is opposite to the main surface, a mount pad being disposed over the main surface, the back surface having two pairs of sides in a plan view; (b) a semiconductor chip including a first transistor and a second transistor, mounted over the mount pad, the first power amplifying system being comprised of the first transistor, the second power amplifying system being comprised of the second transistor; (c) a plurality of first electrode terminals disposed over the back surface of the wiring substrate, the plurality of first electrode terminals being arranged along each of the two pairs of sides, the plurality of the first electrode terminals including a first input terminal, a first output terminal, a second input terminal and a second output terminal, the first input terminal and the first output terminal being used for inputting and outputting of signals for the first power amplifying system, respectively, the second input terminal and the second output terminal being used for inputting and outputting of signals for the second power amplifying system, respectively; and (d) a plurality of second electrode terminals disposed over the back surface of the wiring substrate, the plurality of second electrode terminals being disposed inside the plurality of the first electrode terminals in a plan view, the plurality of the second electrode terminals being used for ground potential supply to the first and second power amplifying systems, the first and second electrode terminals comprising a land grid array structure; and (e) a via hole in which a conductor film is filled formed under the mount pad and inside the wiring substrate, one of the second electrode terminals being coupled to the mount pad via the conductor film filled in the via hole.