Patent ID: 7056822

Claim:
A method of manufacturing an interconnect, said method comprising steps of: forming a first patterned layer of conductive material, said first patterned layer having a trench situated between a first and a second interconnect line; depositing a first insulating layer over said first patterned layer, said first insulating layer filling said trench; depositing a first hard mask on said first insulating layer; forming a first air gap, a second air gap, and a support pillar in said first hard mask and said first insulating layer, said support pillar being situated between said first air gap and said second air gap, said support pillar, said first air gap, and said second air gap being situated in said trench in a direction parallel to a length of said first interconnect line, said support pillar being in contact with said first interconnect line; depositing a sealing layer over said first hard mask to seal said first air gap and said second air gap; depositing a second insulating layer over said sealing layer; depositing a second hard mask over said second insulating layer; forming a via hole through said second hard mask, said second insulating layer, said sealing layer, said first hard mask, and said first insulating layer; wherein said support pillar is formed to increase mechanical strength and thermal conductivity of said first interconnect line, wherein said first insulating layer and said sealing layer comprise a low dielectric constant material.