Patent ID: 7020043

Claim:
A semiconductor memory device comprising: a core voltage supplying part for supplying a core voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying a voltage difference of bit line pairs of the memory cell array block; an overdriving signal generator for receiving an initial driving signal to generate an overdriving signal, while expanding an activation pulse width of the overdriving signal in an activation of a refresh signal; an overdriver for driving a connection node, which is coupled with the core voltage supplying part, to an external voltage higher than the core voltage in response to an inverted overdriving signal; a first power driver for driving a first power line of the bit line sense amplifier block to a voltage of the connection node in response to a first driving control signal; and a second power driver for driving a second power line of the bit line sense amplifier to a first power voltage in response to a second driving control signal.