Patent ID: 8648628

Claim:
A differential output buffer, comprising: a main driver configured to shift a level of a differential signal; and a bypass circuit configured to bypass current flowing through the main driver in such a manner as to contain a change amount of current through the main driver flowing from a high power supply potential to a low power supply potential in a fixed range upon transition between an operating state and a standby state of the main driver, wherein the main driver includes: a pair of differential transistors constituting a differential pair; a switching transistor configured to switch the operating state and the standby state of the main driver; and a bias transistor configured to set bias current through the differential transistors, and wherein the switching transistor is switched off during the standby state, and the bypass circuit is configured to maintain a first current from the high power supply potential to the low power supply potential constant by making bypass current to flow via the bias transistor upon transition between the operating state and the standby state of the main driver, wherein the bypass circuit includes: a first bypass transistor having a source connected to a power supply potential; and a second bypass transistor connected between a connection point of the bias transistor and the third switching transistor and the first bypass transistor.