Patent ID: 8062810

Claim:
A method of manufacturing a semiconductor device comprising: creating design data including a plurality of active region pattern data and a plurality of gate electrode pattern data; creating a correction table specifying relationship between a plurality of size of active region and a plurality of amount of correction of a mask pattern; extracting gate pattern data corresponding to a first gate electrode from the design data, and identifying a size of a first active region which the first gate electrode is formed above; wherein the size of the first active region is different from a size of a second active region to be formed utilizing the mask pattern, deciding an amount of correction of the mask pattern of the first gate electrode based on the difference in the size of the first active region to the second active region as correlated in the correction table by a data processing apparatus; correcting the mask pattern on the basis of the decided amount of the correction; forming the first active region in a semiconductor substrate; depositing a first film over the first active region; forming a resist film over the first film; exposing the resist film by using an exposure mask having the corrected mask pattern; and etching the first film by using the exposed resist film to form the first gate electrode.