Patent ID: 7825022

Claim:
A method of manufacturing an electronic package, the method comprising: providing a substrate; forming a plurality of bond pads over the substrate; forming over the substrate a solder resist layer having a surface; forming a plurality of solder resist openings in the solder resist layer over the bond pads; forming an electrically conducting layer over the surface of the solder resist layer and in the solder resist openings over the bond pads in order to electrically connect the solder resist openings to each other; forming a mask layer over the electrically conducting layer; patterning the mask layer to expose the solder resist openings; electrokinetically depositing a solder material in the solder resist openings over the electrically conducting layer; forming solder bumps out of the solder material in the solder resist openings; removing the mask layer; and removing the electrically conducting layer from the surface of the solder resist layer while leaving the electrically conducting layer in the solder resist openings under the solder bumps.