Patent ID: 7298218

Claim:
A frequency synthesizer comprising a phase locked loop having a phase comparator for which a first input is connected to a reference signal source, a voltage controlled oscillator associated with modulation means with a global modulation ratio which when multiplied by the reference signal frequency produces the required output frequency, the modulation means comprising a frequency divider circuit to divide the frequency of the oscillator output signal by a variable integer division factor N, and the output of which is connected to the other input of the phase comparator, wherein the synthesizer further comprises phase generation means connected between the oscillator and the modulation means, to generate a predetermined number of phases synchronized on the frequency of the oscillator and at intervals from each other equal to a time difference representative of the phase error measured by the phase comparator, wherein the modulation means comprises generation means capable of generating an intermediate signal from the phases, the period of which is dependent on the said time difference between the phases and a first adjustment parameter supplied to the generation means by the control means of the generation means, the intermediate signal being applied to the divider by N circuit, and correction means that can determine the phase error accumulated during N−1 periods of the intermediate signal and make a correction of the intermediate signal every N periods of the intermediate signal as a function of the accumulated phase error, the correction means comprising a sigma-delta modulator such that the loop operates in fractional mode, wherein the output from the intermediate signal generation means is looped back to control means of the generation means, such that the control means are clocked at the frequency of the generated intermediate signal.