Patent ID: 8044915

Claim:
A liquid crystal display apparatus, comprising: a plurality of pixels arranged in a matrix form including respective transistors; a plurality of gate bus lines, each of which is coupled to gates of the transistors arranged in a corresponding single row; a plurality of data bus lines, each of which is coupled to one end of channels of the transistors arranged in a corresponding single column; a gate driver coupled to the plurality of gate bus lines to successively drive the gate bus lines in synchronization with a gate clock signal and a gate start pulse signal, the gate driver being configured to start the successive driving of the gate bus lines upon receiving the gate start pulse signal to drive the gate bus lines one by one in synchronization with the gate clock signal, said gate start pulse signal indicating a timing at which the gate driver starts the successive driving of the gate bus lines; and a timing control circuit configured to supply to said gate driver the gate start pulse signal; wherein the timing control circuit generates the gate start pulse signal by masking a portion of a gate signal with a mask signal, the mask signal being produced for a predetermined time period following the supplying of the gate signal to mask any subsequent gate signal supplied to the gate driver for the predetermined time period; the timing control circuit includes a counter for counting the predetermined time period, a first decoding device for outputting a first signal at a beginning of the predetermined time period, a second decoding device for outputting a second signal at the end of the predetermined time period, and a flip-flop device for outputting the mask signal based on the first and second signals; and the predetermined time period is longer than at least one clock cycle of the gate clock signal, said one clock cycle of the gate clock signal being equal to the driving of one gate bus line that is one horizontal line of the matrix.