Patent ID: 8841744

Claim:
A semiconductor apparatus comprising: a semiconductor substrate of a p-type; a semiconductor layer of an n-type formed on the semiconductor substrate; a separation region of the p-type formed in the semiconductor layer from a surface of the semiconductor layer to a boundary between the semiconductor layer and the semiconductor substrate, the separation region zoning an island region; a semiconductor device formed in the surface of the island region; a cathode region of the n-type formed in a surface portion of the island region, the cathode region being between the separation region and the semiconductor device, the cathode region being spaced apart from the separation region and the semiconductor device; an anode region of the p-type formed in the surface portion of the island region, the anode region being between the separation region and the cathode region, the anode region being spaced apart from the separation region and the cathode region; an insulating separation region positioned below the cathode region, below the anode region, and below a region between the cathode region and the anode region, the insulating separation region being located on or at least partially in the semiconductor substrate; and a first floating region of the p-type formed between the separation region and the anode region, the first floating region being spaced apart from the separation region and the anode region, the first floating region being formed in the semiconductor layer between the surface thereof and the insulating separation region and formed such that the first floating region reaches the insulating separation region from the surface of the semiconductor layer, the semiconductor substrate and the separation region being biased at a potential lower than potentials of the anode region and the cathode region.