Patent ID: 6978387

Claim:
A dynamic logic hold time latch, comprising: a first phase circuit operable in a precharge phase and an evaluate phase, wherein the first phase circuit comprises: a precharge node to be precharged to a precharge voltage during the precharge phase of the first phase circuit and operable to be discharged during the evaluate phase of the first phase circuit; and an output for providing a signal in response to a state at the precharge node of the first phase circuit; and a second phase circuit operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the second phase circuit are out of phase with respect to the precharge phase and the evaluate phase of the first phase circuit, and wherein the second phase circuit comprises: a precharge node to be precharged to the precharge voltage during the precharge phase of the second phase circuit and operable to be discharged during the evaluate phase of the second phase circuit; a conditional discharge path connected to the precharge node of the second phase circuit and operable, during the evaluate phase of the second phase circuit and in response at least in part to the output of the first phase circuit, to conditionally couple the precharge node of the second phase circuit to a voltage different than the precharge voltage; voltage maintaining circuitry, coupled to receive the output of the first phase circuit, for coupling the precharge voltage to the precharge node of the second phase circuit during the evaluate phase of the second phase circuit in response to the output of the first phase circuit providing a first value; and wherein the first value consists of a value that is disabling to at least one switching device in the conditional discharge path of the second phase circuit.