Patent ID: 8069287

Claim:
A universal serial bus device that is connectable to a universal serial bus host via a universal serial bus in a high-speed mode, comprising: a receiver that receives a signal from the universal serial bus; a reset detector that detects start of a reset state of the universal serial bus host; and a reset control circuit that changes, when the reset state is detected by the reset detector, a threshold of the receiver from a first value to a second value based on a level changing signal from the receiver, the second value being higher than a voltage of the universal serial bus in a Tiny J state, the Tiny J state indicating a value of the voltage of the universal serial bus, and returns the threshold of the receiver back to the first value when a chirp driving K asserted by the universal serial bus host is detected and the level changing signal is negated subsequent to the chirp driving K, where the chirp driving K is when a predetermined signal is asserted by the universal serial bus device.