Patent ID: 8120169

Claim:
A packaged semiconductor comprising a die with a bottom surface attached to a plurality of die attach areas, a plurality of leads with first regions disposed under the die and providing the die attach areas that thermally connect the die to the plurality of leads, the first regions being spaced apart from one another by a molding compound encasing edges of the first regions while leaving a lower surface of the leads exposed, at least one electrical connection between the die and at least one of the leads, and a heat spreader thermally connected to the plurality of leads, the heat spreader comprising a planar cap disposed over the die, and at least one connecting projection extending downwardly from the cap thermally connecting the cap to the plurality of leads, the molding compound being disposed between the leads and cap of the heat spreader so as to encapsulate the die, the electrical connection, and an upper surface of the leads while leaving the lower surface of the leads and a top surface of the cap exposed.