Patent ID: 6996730

Claim:
A method of adjusting power consumption of a computer processor, the method comprising the steps of: sending a first signal from a computer subsystem comprising the computer processor to a clock circuit in response to a first predetermined condition, the clock circuit providing a clock signal having a frequency to the computer processor; decreasing the frequency of the clock signal from a high frequency to a lower frequency in response to the first signal from the computer subsystem; detecting a decrease in the frequency of the clock signal and communicating said decrease to a voltage regulator in response to the step of decreasing the clock frequency, the voltage regulator having an output voltage that is provided to the computer processor; decreasing the output voltage of the voltage regulator from a high voltage to a lower voltage in response to the step of detecting; sending a second signal from the computer subsystem to the clock circuit in response to a second predetermined condition; increasing the frequency of the clock signal from a low frequency to a higher frequency in response to the second signal; detecting an increase in the frequency of the clock signal and communicating said increase to the voltage regulator in response to the step of increasing the clock frequency; and increasing the output voltage of the voltage regulator from the low voltage to a higher voltage in response to the step of detecting an increase in the frequency of the clock signal; and wherein the step of increasing the frequency of the clock signal comprises limiting a slew rate of the clock circuit so that at least a minimum required voltage for each operating frequency is provided while the frequency of the clock signal is being increased.