Patent ID: 7795900

Claim:
An integrated circuit having a memory array comprising: a first single-event upset (“SEU”)-hardened memory cell in a first row and a first column of the memory array having a first orientation and a first critical ion track; a second SEU-hardened memory cell adjacent to the first SEU-hardened memory cell and having a second orientation, the second orientation being a first flipped image of the first orientation about a first axis of the memory array between the first SEU-hardened memory cell and the second SEU-hardened memory cell and having a second critical ion track; a third SEU-hardened memory cell adjacent to the first SEU-hardened memory cell and having a third orientation, the third orientation being a second flipped image of the first orientation about a second axis of the memory array between the first SEU-hardened memory cell and the third SEU-hardened memory cell and having a third critical ion track; and a fourth SEU-hardened memory cell adjacent to the second SEU-hardened memory cell having a fourth orientation being a flipped image of the second orientation about the second axis and having a fourth critical ion track, wherein each of the first critical ion track, the second critical track, the third critical ion track and the fourth critical ion track are different from each other.