Patent ID: 7644348

Claim:
A circuit for use in a memory system comprising: a data memory comprising a plurality of memory cells arranged in a plane of m rows and n columns, each cell adapted to store a respective one of m×n data bits during a write access cycle and to retrieve said one bit during a read access cycle; a write access circuit connected to the data memory to store, during said write access cycle, each of n new data bits into a respective one of the n cells comprising a first row of said m rows; and a read access circuit connected to the data memory to retrieve, during said read access cycle, each of n old data bits stored in a respective one of the n cells comprising said first row of said m rows; the circuit comprising: a parity memory comprising n memory cells, each cell adapted to store a respective one of n old parity bits; and a parity generation circuit, connected to the write access circuit and to the read access circuit and operative during each write access cycle, to: receive from the write access circuit all of the n new data bits to be stored in said first row of said data memory; activate the read access circuit to retrieve all of the n old data bits currently stored in said first row of said data memory; compare each of the n new data bits to a corresponding one of the n old data bits; and if and only if a respective x th one of then new data bits is different from the corresponding x th one of the n old data bits, selectively change the respective x th one of said n old parity bits stored in said parity memory.