Patent ID: 8522254

Claim:
A first integrated processor block of a plurality of integrated processor blocks of a network on a chip, the first integrated processor block comprising: a first inbox to receive incoming packets from the other integrated processor blocks of the plurality of integrated processor blocks of the network on a chip; a first outbox to send outgoing packets to the other integrated processor blocks of the plurality of integrated processor blocks of the network on a chip; a first on-chip memory; and a first memory management unit to enable access to the first on-chip memory, wherein the first integrated processor block is programmable to perform a first function and reprogrammable in real-time to perform a second function that is different than the first function to assist a second integrated processor block of the plurality of integrated processor blocks of the network on a chip in response to a determination that a workload of the second integrated processor block has exceeded a threshold, the second integrated processor block including a second inbox to receive incoming packets from the other integrated processor blocks of the plurality of integrated processor blocks of the network on a chip, a second outbox to send outgoing packets to the other integrated processor blocks of the plurality of integrated processor blocks of the network on a chip, a second on-chip memory, and a second memory management unit to enable access to the second on-chip memory, and wherein the second integrated processor block is programmed to perform the second function, wherein the threshold is associated with a performance statistic, wherein the performance statistic may include a number of central processing unit (CPU) cycles executed to render an object, a time taken to render an object, a number of instruction to render an object, another performance statistic, or any combination thereof.