Patent ID: 8395211

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductive type; a first semiconductor region provided on an upper surface of the semiconductor substrate and including a region in which first pillar regions of the first conductive type and second pillar regions of a second conductive type, each having a long side in a first direction that is parallel to the upper surface of the semiconductor substrate, are alternately arranged in a second direction that is parallel to the upper surface of the semiconductor substrate and that is orthogonal to the first direction, the first and second pillar regions being in an element region in which a semiconductor element is formed and also being in a terminal region that surrounds the element region; second semiconductor regions of the second conductive type on surfaces of the second pillar regions in the element region so as to be in contact with the first pillar regions in the element region; gate electrodes that are each on parts of adjacent second semiconductor regions and on one of the first pillar regions interposed therebetween, a gate insulating film being under the gate electrodes; third semiconductor regions of the first conductive type that each function as a source region in parts of surfaces of the second semiconductor regions located under side portions of the gate electrodes; and a reduced surface field (“resurf”) region of the second conductive type, the resurf region being a part of the terminal region and being disposed on the first pillar regions and the second pillar regions in the part of the terminal region, wherein, widths of the second pillar regions in the element region and in the terminal region are each set as a first width, and widths of the first pillar regions in the element region and widths of the first pillar regions connected to the resurf region in the terminal region are each set as a second width, the first pillar regions that are in the terminal region and that are not connected to the resurf region are arranged such that a first pillar region having a third width smaller than the second width and a first pillar region having a fourth width different from the third width are alternately arranged in this order in a direction away from the element region along the second direction, and among the second pillar regions that are in the terminal region and that are not connected to the resurf region, adjacent second pillar regions with the first pillar region having the fourth width interposed therebetween are connected to each other with a connection portion composed of a semiconductor of the second conductive type or a conductor.