Patent ID: 8125278

Claim:
A clock regeneration apparatus, comprising: an oscillator including n gating groups connected in cascade connection to each other in such a manner as to be capable of forming an oscillation loop, n being an integer of two or more, said gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, said oscillator outputting a clock signal at least from the nth one of said gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of said gating groups of said oscillator, respectively; said gating signal generation section being operable to select one of the gating signals into which an edge detection signal of said edge detection section is to be injected in response to the phase decision signal of said phase decision section, delaying the selected gating signal and outputting the gating signal to said oscillator; said oscillator outputting the clock signal having a phase controlled based on the first to nth gating signals and synchronized with the reception data signal.