Patent ID: 7995599

Claim:
A method to manage a load of peripheral elements within a multicore system, said multicore system comprising several processing units accessing peripheral elements through a Network on Chip, each processing unit and peripheral element being attached to a Network Interface in charge of formatting and driving the packets sent to or received from the Network on Chip, the method comprising the steps of: sending a data packet from a sender Network Interface dedicated to a processing unit to a first target Network Interface dedicated to a first peripheral element through the Network on Chip, said data packet having routing information allowing the Network on Chip to route the data packet to the target Network Interface; determining at least one second peripheral element having a function similar to a function of the first peripheral element, said second peripheral element being attached to a second target Network Interface; updating an incoming data packet in said first target Network Interface with routing information suitable to transmit it across the Network on Chip towards the second peripheral element; and reinjecting the updated incoming data packet from said first target Network. Interface into the Network on Chip; wherein routing information of the incoming data packet comprises information suitable to transmit said packet across the Network on Chip towards the first peripheral element as main choice and additional routing information suitable to transmit it across the Network on Chip towards one or more additional peripheral elements as secondary choice, the updating of the incoming data packet by the target Network interface of the first peripheral element consisting of setting one of the secondary choices as the main choice.