Patent ID: 6992937

Claim:
A memory device comprising: a first memory array including a plurality of memory cells arranged in columns; a plurality of first y-drivers, each first y-driver coupled to a corresponding one of a plurality of said columns of memory cells to read contents of memory cells in said column and including a first circuit for testing a level of stored digital data in the memory cells; a redundant memory array including a plurality of redundant memory cells arranged in columns; a plurality of redundant y-drivers, each redundant y-driver coupled to a corresponding one of a plurality of said columns of redundant memory cells to read contents of redundant memory cells in said column and including a second circuit to test a level of stored digital data in the redundant memory cells; and a controller to generate a selection signal to enable said redundant y-drivers and to generate a disable signal to disable said first y-drivers in response to a failure of said testing of said level by said first circuit of said corresponding first y-driver.