Patent ID: 7804718

Claim:
A flash memory device comprising: a memory array having at least one block of NAND flash memory cell strings arranged in columns where each of the NAND flash memory cell strings includes flash memory cells, the at least one block having pages programmable in a predetermined direction from a first wordline to a last wordline, and the at least one block also having a sequential set of first wordlines dynamically configurable by a starting address; and, row circuitry for driving the first wordlines to a first voltage when the substrate is biased to an erase voltage for concurrently erasing the flash memory cells connected to the first wordlines, the row decoders driving second wordlines to a second voltage for inhibiting erasure of the flash memory cells coupled to the second wordlines, the second wordlines including a first unselected wordline up to a last unselected wordline, and the first wordlines including a first selected wordline addressed by the starting address adjacent to the last unselected wordline, up to a last selected wordline.