Patent ID: 7109906

Claim:
A NICAM encoder comprising: a NICAM processor; and a front-end section coupled to the NICAM processor, wherein the front-end section synchronizes the front-end section and the NICAM processor with timing derived from integer divisions of a single system clock, wherein the front-end section comprises a front-end input section and a front-end output section, the front-end input section coupled to an input of the NICAM processor and the front-end output section coupled to an output of the NICAM processor, wherein the front-end input section comprises one of: (a) an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator, or (b) a dual-channel analog-to-digital converter (ADC), an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the ADC couples to the interpolator, the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator.