Patent ID: 8362572

Claim:
A semiconductor device, comprising: a gate region disposed above a semiconductor substrate and extending in a first longitudinal direction; a first fin disposed above the semiconductor substrate and extending in a second longitudinal direction such that the first fin intersects the gate region, the first fin having a first sidewall defining a first undercut; a second fin disposed above the semiconductor substrate and extending in the second longitudinal direction such that the second fin intersects the gate region, the second fin laterally spaced from the first fin and including a second sidewall and defining a second undercut; a first shallow trench isolation (STI) region formed in the semiconductor substrate between the first and second fins; a first insulating layer comprising a low-k dielectric disposed between the first and second fins and over an upper surface of the first STI region and below the lowest bottom surface of the conductive layer; a second insulating material disposed within the first and second undercut and in contact with the first insulating layer over the STI region, wherein the heights of the first and second insulating layers are same; and a conductive contact layer disposed over an upper surface of the first insulating layer and on top surfaces of the first and second fins to provide a fin interconnect, wherein the second insulating layer extends from the first insulating material disposed in the first undercut across the STI region to the first insulating material disposed in the second undercut and electrically insulates the conductive layer from the STI region.