Patent ID: 8159058

Claim:
A semiconductor device comprising: a first wiring substrate including a first upper surface, a plurality of first upper conductive pads formed on the first upper surface, a first lower surface opposite to the first upper surface, a plurality of first lower conductive pads formed on the first lower surface, and a plurality of testing conductive pads formed on the first lower surface; a first semiconductor chip mounted on the first upper surface; a second wiring substrate including a second upper surface, a plurality of second upper conductive pads, a second lower surface opposite to the second upper surface, and a plurality of second lower conductive pads, and the second wiring substrate is stacked over the first wiring substrate such that the second lower surface faces the first upper surface; a second semiconductor chip mounted on the second upper surface; and a plurality of bump electrodes coupled to the first lower conductive pads, respectively; wherein the testing conductive pads are coupled to the first upper conductive pads, respectively; wherein the second lower conductive pads are coupled to the first upper conductive pads, respectively; wherein the second upper conductive pads are coupled to the second lower conductive pads, respectively; wherein the first upper conductive pads are arranged around the first semiconductor chip in a plan view, and are arranged closer to the peripheral portion of the first upper surface than the first semiconductor chip in the plan view; wherein the testing conductive pads are arranged around the first lower conductive pads in a plan view, and are arranged closer to the peripheral portion of the first lower surface than the first lower conductive pads in the plan view; and wherein the bump electrodes are not coupled to the testing conductive pads, respectively.