Patent ID: 8400442

Claim:
A display, comprising: a pixel array section configured to include power feed lines, scan lines disposed along rows, signal lines disposed along columns, and pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix, each of the pixels including a drive transistor and a light-emitting device, one of a pair of current terminals as source and drain of the drive transistor being connected to the power feed line; and a power supply scanner configured to sequentially switch potential of each power feed line between a first higher potential, a second higher potential, and a lower potential, wherein the power supply scanner switches the power feed line between first higher potential and second higher potential at different levels in a predetermined sequence, the power supply scanner includes a shift register and output buffers that are each connected to a respective one of stages of the shift register, the shift register sequentially produces a switch signal for each of the stages, the output buffer is provided between a power supply line and a ground line, and the output buffer switches potential between the first or second higher potential on a power supply line side and the lower potential on a ground line side in accordance with the switch signal and applies the potential to a corresponding one of the power feed lines, the first higher potential and the second higher potential are supplied to the power supply line side of the output buffer in such a manner as to be alternately switched to each other, and a first lower potential and a second lower potential lower than the first lower potential are supplied to the ground line side of the output buffer in such a manner as to be alternately switched to each other in linkage with the switching between the first higher potential and the second higher potential, and the switching between the first lower potential and the second lower potential is so carried out that voltage applied between source and drain of a transistor included in the output buffer provided between the power supply line and the ground line is prevented from surpassing insulation breakdown voltage.