Patent ID: 7965218

Claim:
An apparatus comprising: a first switched capacitor array that receives an input signal and a reference signal, wherein the first switched array is operable to provide the reference signal to its capacitors, to provide the input signal to its capacitor, or to allow its capacitors to float wherein the input and reference signals are differential, and wherein the first switched capacitor array further comprises a plurality of branches, and wherein each branch includes: a first capacitor that is coupled to the first comparator; a first switch that is coupled to the first capacitor and that receives a first portion of the input signal and a first portion of the reference signal, wherein the first switch is controlled by the SAR controller so as to provide the first portion of the input signal to the first capacitor, to provide the first portion of the reference signal to the first capacitor, or to allow the first capacitor to float; a second capacitor that is coupled to the first comparator; and a second switch that is coupled to the second capacitor and that receives a second portion of the input signal and a second portion of the reference signal, wherein the second switch is controlled by the SAR controller so as to provide the second portion of the input signal to the second capacitor, to provide the second portion of the reference signal to the second capacitor, or to allow the second capacitor to float; a second switched capacitor array that receives the input signal and the reference signal, wherein the second switched capacitor array is operable to provide the inputs signal to its capacitors or to provide the reference signal to its capacitors; a first comparator that is coupled to the first switched capacitor array; a second comparator that is coupled to the second switched capacitor array; a successive approximation register (SAR) controller that is coupled to the first switched capacitor array, the second switched capacitor array, the first comparator, and the second comparator, wherein the SAR controller controls each of the first and second switched capacitor arrays.