Patent ID: 6919236

Claim:
A method of forming a transistor comprised of a plurality of source/drain regions above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material, the method comprising: performing a first ion implant process using a dopant material that is of a type opposite said first type of dopant material to form a first well region within said bulk substrate; performing a second ion implant process using a dopant material that is the same type as said first type of dopant material to form a second well region in said bulk substrate within said first well, said transistor being formed in said active layer above said second well; performing a third ion implant process using a dopant material that is of a type opposite said first type of dopant material to result in a source/drain well in said bulk substrate under each of said source/drain regions, said source/drain well having a dopant concentration level of said first type of dopant material that is less than a dopant concentration level of said first type dopant material in said second well; forming a conductive contact to said first well; and forming a conductive contact to said second well.