Patent ID: 6852610

Claim:
A method for manufacturing a semiconductor device, comprising: a first step of forming a gate electrode on a semiconductor region via a gate insulative film; a second step of forming an amorphous layer in an upper portion of the semiconductor region by implanting ion of a group IV element into the semiconductor region using the gate electrode as a mask; after the second step, a third step of implanting a first impurity of a first conductivity type into the semiconductor region in which the amorphous layer is formed using the gate electrode as a mask with an implantation projected range such that the first impurity reaches a position deeper than the amorphous layer; and after the third step, a fourth step of subjecting the upper portion of the semiconductor region to thermal annealing so as to form a dislocation loop defect layer and an extension high concentration diffusion layer of the first conductivity type through diffusion of the first impurity, the extension high concentration diffusion layer having a junction at a position deeper than the dislocation loop defect layer.