Patent ID: 7082546

Claim:
A method of coupling one or more outputs of a first circuit to one or more inputs of a second circuit, the core of the first circuit operating at a first clock frequency, the second circuit operating at a second clock frequency, the first clock frequency substantially higher than the second clock frequency, said method comprising: generating a first clock operating at the second clock frequency based on a clock running at the first clock frequency; transmitting data from the first circuit to a latch of the second circuit using an edge of the first clock operating at the second clock frequency; latching the transmitted data at the second circuit using an edge of a second clock operating at the second clock frequency; and adjusting a phase of the second clock to substantially match a phase of the first clock at a point where the second clock reaches a clock input of the latch, said adjusting further includes: generating a plurality of versions of the second clock using the clock operating at the first clock frequency by clocking a binary one through a recirculating shift register using both edges of the first clock running at the first clock frequency, each of the versions having an incremental phase difference equal to one half the period of the first clock frequency, wherein the recirculating shift register includes a number of flip-flops equal to twice the number by which the first clock frequency is divided to obtain the second clock frequency; and selecting the version of the second clock having the phase that produces the match.