Patent ID: 7410852

Claim:
A method for fabricating a field effect transistor comprising: forming a stack layer comprising a suicide forming metal contacting a silicon layer over a semiconductor substrate, said suicide forming metal selected from the group consisting of cobalt, nickel, platinum, tungsten, titanium and their alloys; forming a source/drain region into the semiconductor substrate while using at least the stack layer as a mask; forming a thermal insulator layer upon the source/drain region; forming a thermal absorber layer comprises an amorphous carbon material, upon the stack layer; and selectively opto-thermally annealing the stack layer to form a fully silicide gate electrode while not annealing the source/drain region, said opt-thermally annealing is performed at a temperature from about 1000° to about 1400° centigrade and for a time period from about 0.01 to about 100 milliseconds.