Patent ID: 8598699

Claim:
A semiconductor device, comprising: a substrate; first to n-th dielectric layers which are formed successively on one surface of the substrate, wherein n is a natural number of 2 or more; a k-th ground metal layer having a first DC potential and disposed between the k-th dielectric layer and the (k+1)-th dielectric layer, the k-th ground metal layer having at least one first hole therethrough, wherein k is a natural number of 1≦k<n; a k-th ground patch disposed in the at least one first hole; a (k+m)-th ground metal layer having a second DC potential and disposed between the (k+m)-th dielectric layer and the (k+m+1)-th dielectric layer, the (k+m)-th ground metal layer having at least one second hole therethrough, wherein m is a natural number of 1≦m<n−k; a (k+m)-th ground patch disposed in the at least one second hole; a first via which connects the k-th ground metal layer and the (k+m)-th ground patch; and a second via which connects the (k+m)-th ground metal layer and the k-th ground patch.