Patent ID: 7859909

Claim:
A nonvolatile semiconductor memory device comprising: a memory array including a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged corresponding to the respective memory cell rows and connecting to memory cells on corresponding rows; a subdecode circuit including subdecode elements arranged corresponding to the word lines, for setting voltages on word lines in accordance with a set of source signals and a set of gate signals; a block decode circuit for producing the source signals in accordance with an address signal; and a gate decode circuit for producing the gate signals in accordance with the address signal; each of the subdecode elements including; first and second transistor of a common conductivity type each having a gate, a source and a drain, the first and second transistors receiving first and second gate signals produced from said gate decode circuit at the respective gates, and receiving first and second source signals produced from said block decode circuit at the respective sources, and the drains of the first and second transistors connected commonly to a corresponding word line, and said subdecode elements being arranged aligned in plural lines in such a manner that no nearest neighboring gates receive a high voltage for data writing or erasure concurrently.