Patent ID: 7688567

Claim:
A multilayer capacitor comprising: an element wherein a plurality of dielectric layers are laminated; a first terminal electrode formed at a outer surface of the element; a second terminal electrode electrically insulated from the first terminal electrode and formed at the outer surface of the element; a plurality of first groups of inner electrodes including a first inner electrode and a second inner electrode that are electrically connected with the first terminal electrode and that are mutually adjacent in a direction of lamination of the plurality of dielectric layers, with the dielectric layer interposed; and a plurality of second groups of inner electrodes including a third inner electrode and a fourth inner electrode that are electrically connected with the second terminal electrode and that are mutually adjacent in the direction of lamination with the dielectric layer interposed; wherein, in the element, the plurality of first groups of inner electrodes and the plurality of second groups of inner electrodes are alternately arranged in the direction of lamination such that the second inner electrode and the third inner electrode are mutually adjacent in the direction of lamination with the dielectric layer interposed and the first inner electrode and the fourth inner electrode are mutually adjacent in the direction of lamination with the dielectric layer interposed, and wherein a outline of a portion of the first inner electrode located within the element is located further outside than a outline of a portion of the second inner electrode located within the element, as seen from the direction of lamination, and a outline of a portion of the third inner electrode located within the element is located further outside than a outline of a portion of the fourth inner electrode located within the element, as seen from the direction of lamination.