Patent ID: 8483626

Claim:
A circuit comprising: a frequency synthesizer configured to provide a clock signal having a variable frequency; a transmit path including: a first anti-aliasing filter for receiving an analog signal; an upconverter configured to upconvert an output of the anti-aliasing filter according to the clock signal; and a first programmable bandpass filter configured to filter an output of the upconverter; and a receive path comprising: a second programmable bandpass filter configured to filter a received signal; a downconverter configured to downconvert an output of the anti-aliasing filter according to the clock signal; and a second programmable anti-aliasing filter configured to filter an output of the downconverter; and one or more of the first and second anti-aliasing filters, first and second bandpass filters and the transversal filter include at least one programmable biquad circuit; the biquad circuit includes at least one attenuator, at least one integrator and at least one summer; and at least one attenuator includes: a plurality of M attenuator blocks, each block comprising: a first switch connected between a signal rail and an output node; a second switch connected between an offset rail and the output node; and a resistive element connected in series between the output node and the first and second switches; the attenuator providing N-bit accuracy, wherein N is less than M.