Patent ID: 8533541

Claim:
A computer-readable, non-transitory medium storing therein a verification support program that causes a computer to execute a procedure, the procedure comprising: detecting in a circuit under test, whether a change occurs in a signal output from each circuit element on a transmission-side, during one clock cycle on a reception-side at an asynchronous location where data is transferred between clock domains having differing operation clocks; selecting a cycle from among a plurality of cycles in which a change occurs in a signal output of one or more circuit elements on the transmission-side during a determined period of time; selectively inputting during the selected cycle, a signal to each circuit element on the reception-side, where a signal of a circuit element on the transmission side in which no change is detected during the selected cycle is transmitted to a corresponding circuit element on the reception side and a signal of a circuit element on the transmission side in which a change is detected during the selected cycle is replaced with a random logic value and the random logic value being input to each corresponding circuit element on the reception-side, and an action associated with the inputting is triggered by a rising edge of an operation clock on the reception-side after the one clock cycle; and outputting for each circuit element on the reception-side, an operation result obtained based on an input at the inputting.