Patent ID: 7444557

Claim:
A memory comprising a plurality of bits, each bit comprising: a cell for being programmed to store either a logic one or a logic zero value; a reference element comprising one or more reference cells having an output for providing a reference value; a redundant cell for being programmed to store a same bit value as the cell; a redundant reference element comprising one or more reference cells having an output for providing a reference value; a first sense amplifier circuitry coupled to the cell and the output of the reference element, the sense amplifier circuitry having an output representative of either a current relationship or a voltage relationship between the cell and the reference element; a second sense amplifier circuitry coupled to the redundant cell and the output of the redundant reference element, the second sense amplifier representative of either a current relationship or a voltage relationship between the redundant cell and the redundant reference element; a logic circuit coupled to the output of the first sense amplifier circuitry and the output of the second sense amplifier circuitry, the logic circuit performing a logic operation on the outputs of the first and second sense amplifier circuitry and providing an output indicating a result of the logic operation as a logic state of the bit.