Patent ID: 7215665

Claim:
An apparatus for switching time division multiplex channels from a plurality of input data streams, each of which may have any one of a plurality of data rates, to a plurality of output data streams, each of which may have any one of a plurality of data rates, comprising: a respective input channel for each input data stream, each input channel comprising a variable delay circuit; a buffer memory for storing data from the input channels in a first order and for reading data in a second order; and a controller for controlling the variable delay circuits independently of each other such that predetermined channels in respective ones of the input data streams are available for storing in a predetermined temporal order in the buffer memory irrespective of the data rates of the input data streams; wherein each of the input data streams is a serial data stream; wherein each of the variable delay circuits comprises a third subcircuit for delaying the input data stream so as to compensate for different data rates of the input data streams, each of the variable delay circuits comprises a first subcircuit for delaying the input serial data stream so as to compensate for a fraction of a bit period offset in the input serial data stream, and each of the variable delay circuits comprises a second subcircuit for delaying the input of a data stream so as to compensate for a fraction of a data word period offset in the input serial data stream, wherein the third subcircuit of each input channel is controlled to provide a delay D S in bit periods at the stream rate SR of the input stream given by: D S =A ( SR/SR min −1) where SR min is the slowest stream rate of all the input streams and A is the sum of the maximum delays of the first and second subcircuits in bit periods at the stream rate SR.