Patent ID: 6883092

Claim:
A processor arranged to be periodically powered on and off to perform periodic operation, comprising a power-on determination circuit for determining, when power is turned on, whether the power has been turned on for a system that incorporates the processor or for the periodic operation, a read selection circuit for performing control depending on a result of determination by the power-on determination circuit so that in the case where the power has been turned on for the system, instructions, table data and a first expected check-sum value will be read from a boot ROM and written into an instruction storage memory and a table data storage memory, and in the case where the power has been turned on for the periodic operation, instructions and a second expected check-sum value will be read from the boot ROM and written into the instruction storage memory, and table data that was backed up when the power was turned off last will be read from a backup memory and written into the table data storage memory, and a check-sum performing circuit arranged to, in the case where the power has been turned on for the system, calculate a check-sum about the data that has been written into the instruction storage memory and the table data storage memory and check the calculated check-sum with the first expected check-sum value, and in the case where the power has been turned on for the periodic operation, calculate a check-sum about the data that has been written into the instruction storage memory and check the calculated check-sum with the second expected check-sum value.