Patent ID: 8455996

Claim:
A wafer level packaging method for packaging a first wafer and a second wafer, wherein the first wafer having an active side and a back side, and the active side having a MEMS element, the packaging method comprises: etching the first wafer to form a plurality of through silicon vias; filling the plurality of through silicon vias; forming a first bonding ring and a first electrical interconnect on an active side, the first electrical interconnect connecting with one of the plurality of through silicon vias, the first bonding ring surrounding the MEMS element and connecting with another of the through silicon vias; forming an electrical connection on a second wafer and the first bonding ring and the first electrical interconnect corresponding to a second bonding ring and a second electrical interconnect separately; facing the second wafer to the active side of the first wafer, the second bonding ring and the second electrical interconnect being connected with the first bonding ring and the first electrical interconnect separately; applying a voltage to the plurality of through silicon vias through the back side of the first wafer; and applying an external force to the second water and pressing it forward to the first wafer.