Patent ID: 8095750

Claim:
A multithreaded computing system comprising: said multithreaded computing system having a plurality of microprocessors having a hardware transactional memory system for supporting a plurality of threads for hardware transactional memory operations, a transaction program on said computing system having said hardware transactional memory system for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread, said transaction program providing a BEGIN_AIG instruction to cause a microprocessor to enter a mode of execution of an Atomic Instruction Group (AIG), and to execute a string of instructions to complete a transaction of said first thread with a string of instructions of said AIG, beginning with one instruction of said string of instructions, and managing memory access to a shared memory location for transaction data of a first thread by first determining whether said one instruction is part of an active atomic instruction group (AIG) of instructions with said BEGIN _AIG instruction which identifies a group of memory locations that are to be updated in an atomic fashion marking the boundaries of a transaction, which AIG is associated with said transaction of said first thread, and if said one instruction is part of an active AIG, then locating a transaction table in physical main data storage which provides for entries in an active mode for said active AIG wherein all storage locations inspected or modified by instructions of said active AIG remain pending until the computing system indicates that the storage locations should be committed, and each AIG having a Transaction Table entry made when instructions that are part of an Atomic Instruction Group caused a memory location to be inspected or updated, and also having a plurality of Set Associative Transaction Tables (SATTs), one Set Associative Transaction Table (SATT) for each microprocessor, which SATT tables allow for very fast indexing when the hardware transactional memory system is attempting to resolve a potential address conflict while processing a transaction by inspecting the real system memory address and a “private to transaction” (PTRAN) tag attached to each increment of real system memory which said hardware inspects before attempting to set the PTRAN tag to enable detection of potential conflicts with other AIGs that are concurrently executing on other threads, while SATTs, LSTs and SSTs that are kept in real memory and managed by an assist thread and PTRAN tag hardware detect conflicts between the storage accesses of the transactions running on multiple threads of execution.