Patent ID: 7872907

Claim:
A semiconductor device comprising: a memory array which is divided into a plurality of blocks in a row direction and includes a plurality of memory cells arranged in matrix form, each of the memory cells including a magneto-resistive element whose electrical resistance varies according to magnetic data and a switch element coupled in series with the magneto-resistive element and having a control electrode; a plurality of bit lines which are provided corresponding to memory cell columns of the memory array respectively and each used for supplying a first data write current necessary to write the magnetic data; a plurality of digit lines which are each provided in each memory cell row in each of the blocks individually and used for writing the magnetic data by supplying a second data write current in a direction intersecting the first data write current; a plurality of word lines which are each coupled to a plurality of control electrodes included in a corresponding memory cell row of the memory array and formed with a conductive layer having a first sheet resistance; and a plurality of common word lines which are provided corresponding to memory cell rows of the memory array respectively and provided common to the blocks, each of the common word lines being formed with a conductive layer having a second sheet resistance lower than the first sheet resistance and electrically coupled at a plurality of points to a word line provided in a corresponding memory cell row.