Patent ID: 8566108

Claim:
An apparatus comprising: at least one processor; and at least one memory including computer program code, the at least one memory, the at least one processor, and the computer program code configured to cause the apparatus to at least: generate packets from an input signal; generate at least one core layer encoded signal, based at least in part on the input signal, the core layer encoded signal comprising a first relative time value; generate at least one enhancement layer signal, based at least in part on the input signal and associated with the at least one core layer encoded signal; generate at least one indicator associated with each of the at least one enhancement layer signal, each of the at least one indicator based at least in part on the first relative time value; and determine if a synchronization point has been reached, wherein the at least one indicator comprises an identifier identifying the at least one core layer encoded signal, and wherein the at least one indicator is generated only if the synchronization point has been reached.