Patent ID: 8185760

Claim:
A memory controller device coupled to a memory device equipment including a plurality of memory devices, the memory controller device comprising: a memory controller configured to instruct read-out of data in the memory device equipment; and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excluding a part of a delay time from the read-out instruction until the data read-out of at least one other memory device, wherein the physical part comprises read-out time information for each of the plurality of memory devices, wherein the physical part comprises a setting part configured to set a start point of the certain period based at least in part on the read-out time information, wherein the read-out time information is the delay time of each of the plurality of memory devices, the memory controller outputs a control signal for indicating the certain period, and the setting part delays the control signal input from the memory controller in accordance with the value of the delay time, and wherein the physical part comprises a first clock, and the setting part has a first adjusting part configured to provide the control signal with a delay amount of a half period or more of the first clock and a second adjusting part configured to provide the control signal with a delay amount smaller than the half period of the first clock.