Patent ID: 6934211

Claim:
A dynamic random access memory (DRAM) having a refresh-control function under control by an internal refresh-control signal comprising: a cell array having a plurality of DRAM cells divided into a plurality of blocks, the DRAM cells being driven through word lines for data transfer with bit lines; a decoder to select word lines and bit lines connected to the cell array; a sense amplifier to amplify data on the bit lines; and a refresh controller to limit refresh to the cell array so that at least one externally-accessed block cell among the blocks is refreshed; wherein the refresh controller comprises: a refresh counter to generate an internal address signal, the address being increased for each refresh to the cell array; a register, provided per block of the cell array, the register storing information indicating whether each block has been accessed; a refresh limiter to halt refresh to each block that has not been accessed; and a refresh-restriction releasing section that is data programmable for releasing the refresh limiter from refresh limit to the cell array.