Patent ID: 7291557

Claim:
A method for forming an interconnection structure in an integrated circuit, the method comprising: forming a dielectric layer with a top surface on a semiconductor substrate, forming an opening in the dielectric layer; forming a barrier layer over inner walls of the opening including over a bottom wall thereof, and over the dielectric layer depositing a conductive layer on the barrier layer and filling the opening; and polishing the conductive layer to form the interconnection structure having a convex-shaped top surface, such that a peripheral edge of a top surface of the interconnection structure is no lower than a top surface of the barrier layer, wherein a first vertical length measured from the highest point of the convex-shaped top surface of the interconnection structure to the top surface of the dielectric layer is at least one percent of a second vertical length measured from the top surface of the dielectric layer to an interface between the barrier layer and the bottom wall.