Patent ID: 8350607

Claim:
A clock generator comprising: an adjustable delay circuit having an input to which an input clock signal is applied during a normal operation mode, and an output at which an output clock signal is provided by coupling the input clock signal through the adjustable delay circuit, the output clock signal being delayed relative to the input clock signal by an adjustable delay; and a delay control circuit, comprising: a phase detector having a first input coupled to receive the input clock signal in a normal operation mode and a second input coupled to receive the output clock signal, the phase detector configured to determine the phase difference between the output clock signal and the input clock signal, and to vary the adjustable delay during the normal operation mode but not during a delay measurement mode; a delay measurement circuit coupled to receive the input clock signal and the outputs clock signal, the delay measurement circuit operable in the delay measurement mode to measure a delay without using the phase detector by coupling a measurement signal to the input of the adjustable delay circuit and allowing the measurement signal to propagate through the adjustable delay circuit, the delay measurement circuit further operable in the delay measurement mode to set the adjustable delay of the adjustable delay circuit according to the measured delay.