Patent ID: 7573768

Claim:
A semiconductor memory device having a cell array area for reading or storing data, comprising: a normal cell block including a plurality of normal cells, which are pairs in a folded bit line structure, each pair being commonly applied with a plate voltage and being coupled to a bit line and a bit line bar for storing a data; a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor, wherein two reference cell units per four bit lines are laid out at both end portions of each bit line; a precharge block for precharging the bit line and the bit line bar as a ground; and a sense amplifying block for sensing and amplifying the data by using a core voltage for operating the semiconductor memory device and a high voltage having a higher voltage level than the core voltage, wherein the high voltage is inputted to the sense amplifying block during a predetermined period from a timing of starting to sense and amplify the data wherein the core voltage is inputted to the sense amplifying block after the predetermined period, wherein the normal cell block includes: a first normal cell including a first normal capacitor and a first normal transistor for connecting the normal capacitor to the bit line; and a second normal cell including a second normal capacitor laid out with the same pattern as the first normal capacitor and a second normal transistor laid out with the same pattern as the first normal transistor to connect the second normal capacitor to the bit line bar; and a contact plug, contacted with a normal storage node corresponding to each source of the first and the second normal transistors.