Patent ID: 8183062

Claim:
A method of performing a Lithography-Etch-Lithography-Etch (LELE) processing sequence to create a plurality of metal gate structures, the method comprising: receiving a first set of wafers by a first transfer subsystem coupled to one or more Integrated-Metrology-Lithography subsystems, one or more Integrated-Metrology-Etching subsystems, one or more scanner subsystems, one or more evaluation subsystems, one or more inspection subsystems, or one or more deposition subsystems, or any combination thereof; creating a first set of first metal gate structures in a first patterned layer on a plurality of first patterned wafers of the first set of wafers using a first set of procedures in the LELE processing sequence, the first set of procedures being performed using a first Integrated-Metrology-Lithography subsystem, and a first immersion scanner subsystem coupled to the first Integrated-Metrology-Lithography subsystem, and a first Integrated-Metrology-Etching subsystem coupled to the first Integrated-Metrology-Lithography subsystem; obtaining first real-time evaluation data for the first set of first metal gate structures using the first Integrated-Metrology-Lithography subsystem and/or the first Integrated-Metrology-Etching subsystem; establishing a first set of low risk wafers using the first real-time evaluation data for the first set of first metal gate structures; creating a second set of second metal gate structures in a second patterned layer on a plurality of second patterned wafers wherein the second patterned wafers are created by performing a second set of procedures in the LELE processing sequence using the first set of low risk wafers, the second set of procedures in the LELE processing sequence being performed using the first Integrated-Metrology-Lithography subsystem, the first immersion scanner subsystem, and the first Integrated-Metrology-Etching subsystem, wherein the second set of second metal gate structures are aligned relative to the first set of first metal gate structures; obtaining second real-time evaluation data for the second set of second metal gate structures using the first Integrated-Metrology-Lithography subsystem and/or the first Integrated-Metrology-Etching subsystem; and establishing a second set of low risk wafers using the second real-time evaluation data for the second set of second metal gate structures.