Patent ID: 8345469

Claim:
A static random access memory having bit cells connected to different paths for reading than for writing, comprising: a first plurality of bit cells in a first row coupled to a true read bit line and a true write bit line; a first bit cell of the plurality of bit cells coupled to a first read word line and a first write word line and is selected for reading when the first read word line is enabled, wherein the first bit cell provides a high impedance to the true read bit line when the first bit cell is outputting a first logic state and provides a signal voltage on the true read bit line when the first bit cell is outputting a second logic state, wherein the first logic state is different from the second logic state; a second plurality of bit cells in a second row coupled to a complementary read bit line and a complementary write bit line, wherein the first plurality of bit cells and the second plurality of bit cells are powered by a voltage applied between a first power supply terminal at a first voltage and a second power supply terminal at a second voltage during a read; a precharge circuit that precharges, prior to a read, the true read bit line and the complementary read bit line to a precharge voltage intermediate the first voltage and the second voltage, wherein the precharge voltage is less than the signal voltage; a dummy cell coupled to the true read bit line that draws charge from the true read bit line when any one of the first plurality of bit cells is selected for reading, wherein when the first bit cell is storing the first logic state the dummy cell causes a predisposition in voltage on the true read bit line; and a sense amplifier coupled to the true read bit line and the complementary read bit line that amplifies a difference between a voltage present on the true read bit line and a voltage present on the complementary read bit line during a read.