Patent ID: 6965264

Claim:
An apparatus for reducing a leakage current for a plurality of MOS transistors disposed in an integrated circuit, comprising: a detection circuit for automatically generating an up signal and a down signal based on a determination as to what side of an inflection point that an initial value of the leakage current is disposed, wherein the inflection point is a graphical representation of a value for a back bias voltage that causes the least amount of leakage current from the plurality of MOS transistors, and wherein the detection circuit further includes at least two current mirrors that are arranged with complementary MOS transistors that have a relatively matched size; and a bias circuit for automatically providing an adjusted back bias voltage that enables the least amount of leakage current by the plurality of MOS transistors, wherein if the up signal is generated, then the adjusted back bias voltage is increased and if the down signal is generated, then the adjusted back bias voltage is decreased, and wherein the biasing circuit provides a relatively constant value for the back bias voltage if both the up signal and the down signal are ungenerated by the detection circuit.