Patent ID: 8729946

Claim:
A clock generation circuit generating an output clock in accordance with a state of a first input clock, comprising: a first logic circuit that has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit outputting a voltage having a logic state corresponding to the circuit threshold value as the first input clock, receives the first input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the first input clock and the first circuit threshold value; a second logic circuit that has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the first input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the first input clock and the second circuit threshold value; and a switch circuit that receives the first and second output signals and outputs, as the output clock, any one of first and second voltages corresponding to different logic states of the first and second output signals when logic states of the first and second output signals are changed from the different states to the same state.