Patent ID: 8510534

Claim:
A scalar/vector processor comprising: a plurality of functional units, at least two of the functional units comprising: a vector section for operating on at least one vector, a corresponding scalar section for operating on at least one scalar, and the vector section and corresponding scalar section of the functional unit co-operating by the scalar section being arranged to provide at least one scalar required by the vector section of the functional unit and consume at least one scalar supplied by the vector section of the functional unit; wherein each of the at least two functional units comprises: a scalar receive register in the functional unit for receiving a scalar into the functional unit, a vector receive register in the functional unit for receiving a vector into the functional unit, and a shared processing element connected to both the scalar receive register and the vector receive register, the shared processing element for: receiving the scalar from the scalar receive register and the vector from the vector receive register; and providing processing power of the vector section within the functional unit that operates on the scalar in the scalar receive register and the vector in the vector receive register, whereby the scalar section supports the operation of the vector section by at least one of supplying scalar data and consuming scalar data; wherein the vector sections of the at least two functional units are arranged in a first pipeline and the scalar sections of the at least two functional units are arranged in a second pipeline; wherein the scalar/vector processor is controlled by a VLIW instruction comprising separate instruction segments for each functional unit; wherein an instruction segment for a functional unit with both a vector section and a scalar section comprises respective instructions for the vector section and for the scalar section of the functional unit.