Patent ID: 7064582

Claim:
An output buffer, comprising: a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage providing buffer strength when a first stage enable signal is active, and the second stage providing buffer strength when a second stage enable signal is active; wherein each output stage comprises: a complementary metal oxide semiconductor (CMOS) structure having a p-channel MOS device and an n-channel MOS device; an AND gate having an output connected to a gate of the n-channel transistor, and having two inputs, an input connected to a data signal and another input connected to one of a plurality of enable signals; and an OR gate having an output connected to a gate of the p-channel transistor, and having two inputs, an input connected to the data signal and another input connected to a complement of the one of the plurality of enable signals; and a bank of latches, the bank of latches having an enable latch and two or more trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to the respective enable input of one the plurality of output stages to provide its enable signal to its respective output stage.