Patent ID: 7577051

Claim:
A memory device, comprising: a first reduced swing amplifier serving as a local sense amp which is connected to the memory cell through a local bit line pair, wherein the first reduced swing amplifier is composed of a local pre-charge transistor pair for pre-charging the local bit line pair to an array voltage, a local amplify transistor for reading an output from one of the local bit line pair where the local amplify transistor is connected to a segment bit line, and a series write transistor pair for driving the local bit line pair; and a memory cell including a pass transistor pair and a cross coupled inverter latch; and a second reduced swing amplifier serving as a segment sense amp which is connected to the segment bit line, wherein the second reduced swing amplifier is composed of a segment reset transistor for resetting the segment bit line to a ground voltage, a segment amplify transistor for reading the segment bit line, and a segment enable transistor for enabling the segment amplify transistor; and a third reduced swing amplifier including a global pre-set transistor for pre-setting a global bit line connecting to the segment enable transistor to the array voltage, a global amplify transistor for reading the global bit line, and a global enable transistor for enabling the global amplify transistor; and a global sense amp including a read circuit, a latch circuit, a data transfer circuit and a write circuit, wherein the read circuit is composed of the third reduced swing amplifier, the latch circuit is composed of a cross coupled inverter latch which is connected to a left latch node and a right latch node where the left latch node is connected to a pull-down path including a locking transistor, at least a column select transistor, and a latch flip transistor for receiving an output of the read circuit through a global amp node which is reset by a global node reset transistor, and the right latch node is connected to a latch reset transistor for resetting the right latch node, and the data transfer circuit is composed of a selector circuit for selecting an output from the latch circuit or a data from a previous memory block, and the write circuit is composed of a receiving gate and an inverting gate for transferring a write data to the series write transistor pair through a write bit line pair; and a variable voltage regulator for generating the array voltage; and a delay circuit for generating a locking signal which is generated by a reference signal based on at least a reference memory cell for locking the locking transistor of the latch circuit.