Patent ID: 8826059

Claim:
An apparatus for buffering a data signal between a memory controller and a DRAM, the apparatus comprising: a phase locked loop (PLL); a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word; and a non-volatile storage location that stores the phase aligning control word, wherein the phase aligning control word is determined through an initial training procedure of the apparatus using predetermined training conditions, wherein the predetermined training condition include at least a predetermined supply voltage level and a predetermined temperature, and wherein the predetermined training conditions are set so as to generally optimize the phase alignment of an edge of the output clock signal with respect to a buffered data signal, wherein the predetermined training conditions during the initial training are set apart from the middle of at least two corners of the training conditions so as to comply with an asymmetric behavior of the phase with respect to the training conditions, wherein the buffered signal is derived from information derived from these training conditions, wherein the corners are a maximum supply voltage with a minimum temperature and a minimum supply voltage with maximum temperature.