Patent ID: 8270215

Claim:
A nonvolatile memory device, comprising: a plurality of bit lines; a page buffer unit comprising a plurality of page buffers, each said page buffer being coupled to one of the bit lines and comprising a first latch coupled to a data input and output (I/O) line and configured to input or output data to or from the data I/O line; and a second latch coupled to a verification line; a fail bit count unit coupled to the verification line to which the second latches are coupled in common and configured to count a number of fail bits based on a current of the verification line; and a control unit coupled to the page buffer unit and the fail bit count unit and configured to input data for a next program to the first latch, determine whether to perform error correction based on the number of fail bits counted by the fail bit count unit, and control a program operation based on a result of the determination.