Patent ID: 8285947

Claim:
A store hit load predictor comprising: a first memory comprising a first plurality of entries, wherein each of the first plurality of entries is configured to store at least a portion of a first program counter (PC) corresponding to a store memory operation; a second memory comprising a second plurality of entries, each of the second plurality of entries corresponding to a respective entry of the first plurality of entries and configured to store an offset between the store memory operation in the respective entry and a subsequent load memory operation in program order which was hit by the store memory operation during execution of the store memory operation; and a control unit coupled to the first memory and the second memory, and wherein the control unit is configured to detect a hit of an input PC of a fetched store memory operation on a first entry in the first memory, and wherein the control unit is configured to read the offset from the corresponding entry in the second memory to identify a subsequently fetched load memory operation responsive to the hit of the input PC of the fetched store memory operation on the first entry, and wherein the control unit is configured to cause a dependency of the subsequently fetched load memory operation on the fetched store memory operation responsive to the offset, wherein the dependency prevents the subsequently fetched load memory operation from executing prior to the fetched store operation.