Patent ID: 7102194

Claim:
A transistor, comprising: a P-substrate; a first diffusion region and a second diffusion region, having N conductivity-type ions form an N-well in said P-substrate, wherein said first diffusion region comprises an extended drain region; a drain diffusion region, containing N+ conductivity-type ions, forming a drain region in said extended drain region; a plurality of P-field blocks, formed in said extended drain region encircling said drain region, wherein sizes and shapes of said P-field blocks can be adjusted for adjusting junction fields; a source diffusion region, having N+ conductivity-type ions, wherein said source diffusion region forms a source region in said N-well which is formed by said second diffusion region and encircles said drain region; a channel, formed between said drain region and said source region; a gate electrode, formed over said channel to control a current flow in said channel; a contact diffusion region, containing P+ conductivity-type ions, wherein said contact diffusion region forms a contact region in said N-well which is formed by said second diffusion region; and an isolation P-well, formed in said N-well which is formed by said second diffusion region for preventing from breakdown, wherein said isolation P-well formed in said second diffusion region encloses said source region and said contact region.