Patent ID: 7855446

Claim:
A semiconductor memory device, comprising: a wiring board having a substantially rectangular outer shape, a first surface provided with an external connection terminal, and a second surface provided with a chip mounting section and connection pads arranged on a first pad region along a first long side and a second pad region along a second long side; a first chip group including a plurality of first memory chips stacked in a step-like shape on the chip mounting section of the wiring board, each of the first memory chips having electrode pads exposed and arranged along a long side which is located near the first pad region; a second chip group including a plurality of second memory chips stacked in a step-like shape on the first chip group in a direction opposite to a stepped direction of the first chip group, each of the second memory chips having electrode pads exposed and arranged along a long side which is located near the second pad region; first metal wires electrically connecting the connection pads arranged on the first pad region and the electrode pads of the first memory chips; second metal wires electrically connecting the connection pads arranged on the second pad region and the electrode pads of the second memory chips; and a sealing resin layer formed on the second surface of the wiring board to seal the first and second chip groups together with the first and second metal wires.