Patent ID: 8405067

Claim:
A nitride semiconductor element, comprising: a silicon substrate; a strain suppression layer formed on the silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer, wherein; the strain suppression layer includes: a first spacer layer made of a first nitride semiconductor; a second spacer layer formed on and in contact with the first spacer layer, the second spacer layer being made of a second nitride semiconductor smaller in lattice constant than the first nitride semiconductor; and a superlattice layer formed on and in contact with the second spacer layer, the superlattice layer having first layers made of a third nitride semiconductor and second layers made of a fourth nitride semiconductor smaller in lattice constant than the third nitride semiconductor stacked alternately on top of one another, and an average lattice constant of the superlattice layer is smaller than a lattice constant of the first spacer layer and larger than a lattice constant of the second spacer layer.