Patent ID: 7839155

Claim:
A computer-implemented method for analyzing an integrated circuit including an on-chip supply power regulator and an on-chip self-test process, the method comprising: supplying a supply signal with a first voltage level to the on-chip supply power regulator of the integrated circuit; instructing the on-chip supply power regulator to output a circuit supply signal having a received minimum voltage level for the integrated circuit, wherein the received minimum voltage level is less than the first voltage level; instructing the integrated circuit to initiate the on-chip self-test process; determining if the on-chip self-test process fails; when the on-chip self-test process does not fail: instructing the on-chip supply power regulator to reduce the circuit supply signal to a lower voltage level that is lower than the minimum voltage level, instructing the integrated circuit to initiate the on-chip self-test process; when the on-chip self-test process fails: storing an indication of the last voltage level at which the on-chip self-test process did not fail in a computer-readable memory, wherein the last voltage level indicates a minimum operating voltage of the integrated circuit.