Patent ID: 7412642

Claim:
A system comprising: a transmitter configured to transmit a segment of data, a cyclic redundancy code, and redundant information via separate bit lanes of a communication link including a plurality of bit lanes; and a receiver coupled to the transmitter via the communication link, wherein each bit of the segment of data, and the cyclic redundancy code is conveyed from the transmitter to the receiver serially via a respective single-bit lane of the plurality of bit lanes; wherein the segment of data, the redundant information, and the cyclic redundancy code are accumulated within the receiver over a plurality of clock cycles, wherein the cyclic redundancy code covers the segment of data accumulated over the plurality of clock cycles, and wherein the cyclic redundancy code is defined by a serial sequence of the bits of the segment of data conveyed upon each bit lane concatenated with the bits of the segment of data conveyed upon a next bit lane; and wherein the receiver is configured to detect an error in the segment of data using the cyclic redundancy code, and in response to detecting the error to regenerate the segment of data using the redundant information, and to determine whether a resulting regenerated bit, along with remaining bits, of the segment of data is correct using the cyclic redundancy code.