Patent ID: 8084279

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: stacking a first wiring layer on a semiconductor substrate; stacking, on the first wiring layer, a second wiring layer constituted by including a second wiring which is connected to a wiring of said first wiring layer, and a third wiring which is not connected to the wiring of the first wiring layer; stacking an interlayer insulating film on said second wiring layer; forming, in a certain region of said interlayer insulating film, a first opening in which said second wiring is exposed, and a second opening in which said third wiring is exposed; burying a metal in said first opening and said second opening; providing a pad extending through the certain region to a region outside the certain region, on said interlayer insulating film, performing probing into a portion on said certain region, which is a surface of said pad; and connecting a wiring for external connection to a portion on the region outside said certain region, which is a surface of said pad.