Patent ID: 8589714

Claim:
A falling edge bus router comprising: a first bus of TDI, TCK, TMS and TDO signals; a second bus of TDI, TCK, TMS and TDO signals; a third bus of TDI, TCK, TMS and TDO signals; a routing circuit including: (a) inputs coupled to the TDI, TCK and TMS signals of the first bus, a select input, an enable input, and an output coupled to the TDO signal of the first bus; (b) outputs coupled to the TDI, TCK and TMS signals of the second bus and an input coupled to the TDO signal of the second bus; (c) outputs coupled to the TDI, TCK and TMS signals of the third bus and an input coupled to the TDO signal of the third bus; a controller including inputs coupled to the TDI, TCK and TMS signals of the first bus, a select output coupled to the select input of the routing circuit, an enable output coupled to the enable input of the routing circuit, a shift output, and a TDO output; a multiplexer having a first data input coupled to the TDO output of the routing circuit, a second data input coupled to the TDO output of the controller, a control input coupled to the shift output of the controller, and a data output; and a tri-state buffer having a data input coupled to the data output of the multiplexer, a control input coupled to the enable output of the controller, and a data output coupled to the TDO signal of the first bus.