Patent ID: 7608497

Claim:
A method for fabricating a tiered gate structure transistor comprising: forming a source and a drain; forming a gate foot between the source and the drain, the gate foot comprising a conductive layer; forming a passivation layer extending along an uppermost surface of the source and extending along an uppermost surface of the drain and on the gate foot such that a top portion of the gate foot is not covered with the passivation layer, the passivation layer directly contacting the uppermost surface of the source and the uppermost surface of the drain and surrounding sidewalls of the gate foot; and forming a gate head on the gate foot and a portion of the passivation layer, wherein the passivation layer directly contacting the uppermost surface of the source and the uppermost surface of the drain and surrounding the sidewalls of the gate foot providing an additional support to the gate head and increasing a structural integrity of the tiered gate structure transistor.