Patent ID: 6925007

Claim:
In an array of non-volatile memory cells including source and drain regions spaced apart in a first direction across a surface of a semiconductor substrate and connected to bit lines extending in a second direction, the first and second directions being orthogonal with each other, a method of storing charge in a plurality of neighboring regions of a charge-trapping dielectric on the substrate surface positioned at least over substrate channel regions between source and drain regions of individual memory cells, comprising: storing charge in a first of said plurality of charge storage regions under a first control gate having a length extending in the second direction and a width extending oyer a first portion of the substrate channel region in contact with the charge-trapping dielectric in the first of said plurality of charge storage regions, and storing charge in a second of said plurality of charge storage regions under a second control gate having a length extending in the first direction over a second portion of the substrate channel region in contact with the charge-trapping dielectric in the second of said plurality of charge storage regions.