Patent ID: 8339303

Claim:
A method for improving a gain estimate by a summing-node algorithm of a residue amplifier to correct an inter-stage error, the method comprising: sampling an input signal on a multiplying digital-to-analog converter (MDAC) housed in a stage of an analog-to-digital converter (ADC); amplifying a sampled voltage with a preamplifier; digitizing the amplified sampled voltage with an auxiliary analog-to-digital converter (ADC); determining a number of sub-ranges with bits from a flash analog-to-digital converter (ADC) housed in the stage of the ADC; dividing the digitized amplified sampled voltage into the number of sub-ranges via the flash ADC; selecting, by a gating device, a voltage corresponding to a respective sub-range, the respective sub-range corresponding to an amplitude of the sampled voltage; and computing the gain estimate by the summing-node algorithm using the voltage and a residue voltage.