Patent ID: 8792602

Claim:
A processor for implementing a network of functional nodes and communication paths between the nodes, the processor comprising: a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes, wherein at least some of the signal paths are configured to pass signal values represented on said paths according to corresponding temporal patterns; wherein at least some of the circuit implementations of the functional nodes each includes circuitry for combining temporal patterns of a plurality of signals to form a temporal pattern of a combined signal; and wherein the processor comprises a plurality of circuit components each for conversion between a signal value represented as a signal level and a signal value represented as a temporal pattern; wherein at least some of the circuit implementations of the functional nodes each includes circuitry for combining signal levels of a plurality of signals to form a signal level on a combined signal; and wherein the functional nodes that include circuitry for combining signal levels further include at least some of the circuit components for conversion between a signal value represented as a signal level and a signal value represented as a temporal pattern, said circuit component for conversion being coupled to the circuitry for combining the signal levels.