Patent ID: 7565633

Claim:
A computer-implemented method for verifying a printability of a mask layout for a photolithographic process, the method comprising: providing, by a computer, a mask layout; simulating the mask layout to generate a simulated image shape; and verifying the printability of the mask layout based on the simulated image shape; wherein the mask layout simulation includes: simulating the mask layout with a first accuracy to produce the simulated image shape, and examining the simulated image shape to determine whether to adjust a simulation accuracy to a second higher accuracy based a tolerance threshold, the tolerance threshold being selected based on the first accuracy of the simulation; wherein the simulation with the first accuracy is implemented by simulating a simplified version of the mask layout, wherein the simplified version is obtained by simplifying the mask layout in at least one of a spatial domain and a frequency domain using a smoothing process, and the simplified version has a reduced data size compared to the mask layout; performing a simulation with the second higher accuracy in response to an error being detected in the simulated image shape; and dividing a target image shape into target image segments and dividing the mask layout into mask segments corresponding to each of the target image segments, wherein the simulating and verifying are performed on each mask segment.