Patent ID: 8040293

Claim:
A shift register comprising a plurality of stages coupled to a start pulse input line, at least one of the stages comprising: first, second, and third nodes; a voltage level controller configured to control voltage levels of the first and/or second nodes according to a start pulse or an output signal of a previous stage and a second clock signal; a control capacitor coupled between the first node and an input line of a first clock signal, and configured to reduce a voltage of the first node according to the first clock signal applied to the control capacitor prior to application of the start pulse or the output signal of the previous stage; a first transistor coupled between a first power supply and the third node that is an output node of the stage and comprises a gate electrode coupled to the first node; and a second transistor coupled between the third node and an input line of a third clock signal and comprises a gate electrode coupled to the second node.