Patent ID: 8488381

Claim:
A non-volatile memory device comprising: a memory cell array; and a peripheral circuit configured to access the memory cell array, wherein the memory cell array includes: a substrate; a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked in series; a plurality of first select transistor groups coupled between the substrate and the plurality of memory cell groups respectively; and a plurality of second select transistor groups respectively coupled between the plurality of memory cell groups and a plurality of bit lines, wherein the plurality of memory cell groups, the plurality of first select transistor groups, and the plurality of second select transistor groups form a plurality of memory cell strings extending from the substrate, each memory cell string comprising a first select transistor group coupled between a first end of a memory cell group and the substrate and a second select transistor group coupled between a second end of the memory cell group and a bit line, wherein the peripheral circuit is configured to independently drive second select transistors of a second select transistor group corresponding to an unselected memory cell group of the plurality of memory cell groups during a program operation, and wherein a second select transistor group of a selected memory cell group is configured to receive a turn-on voltage during the program operation.