Patent ID: 8633921

Claim:
A data driving circuit, comprising: a data register configured for receiving a plurality of serial gray level signals, and outputting the plurality of gray level signals in parallel; a counter configured for outputting counting signals; a shift register comprising a plurality of shift register units for outputting a plurality of first enable signals to the data register; a first control terminal being configured for providing a second enable signal to the data register and the counter; a latch comprising a plurality of latch units; a second control terminal; and a comparator configured for receiving the plurality of gray level signals and the counting signals, and outputting a plurality of pulse voltage signals according to the gray level signals and the counting signals, a variety of duty ratios of the pulse voltage signals corresponding to a variety of gray levels; wherein the data register comprises a plurality of data register units corresponding to the plurality of shift register unit, for receiving the plurality of data signals according to the first enable signals, respectively, and outputting data signals to the first input of a corresponding comparator unit according to the second enable signal; and wherein the shift register is configured for outputting a plurality of third enable signals to corresponding latch units, and the latch units are configured for receiving data signals according to the third enable signals and outputting the data signals to corresponding comparator units according to the fourth enable signals.