Patent ID: 7839704

Claim:
A memory circuit comprising: a write signal driving circuit connected to a data input signal line to which write data is inputted from the outside, a write enable signal line for permitting the write data to be written, a first write signal line, and a second write signal line to output a first write signal and a second write signal from said first write signal line and said second write signal line, respectively, based on the write data from said data input signal line and a write enable signal from said write enable signal line; a write signal amplifying circuit connected to a column signal line for selecting a column of said memory circuit to write or read data, said first write signal line, said second write signal line, a first bit signal line and a second bit signal line to output the first write signal and the second write signal inputted from said first write signal line and said second write signal line as a first driving write signal and a second driving write signal from said first bit signal line and said second bit signal line, respectively, based on a column signal inputted from said column signal line; a memory cell circuit connected to said first bit signal line and said second bit signal line to store data, based on the first driving write signal and the second driving write signal line inputted from said first bit signal line and said second bit signal line, and to output the stored data as a first read signal and a second read signal from said first bit signal line and said second bit signal line; and a global signal driving circuit connected to said first bit signal line, said first write signal line, said column signal line and a global signal line for outputting data stored in said memory cell circuit to the outside to output the first read signal as a global signal from said global signal line when the first read signal is inputted from said first bit signal line, and to inhibit the first driving write signal from being outputted to said global signal line, based on the first write signal inputted from said first write signal line, when the first driving write signal is inputted from said first bit signal line, with the column signal inputted from said column signal line.