Patent ID: 7978497

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistive element; a data write circuit operative to apply a voltage required for data write to said memory cell via said first and second lines; and a current limit circuit, on said data write, operative to limit a value of maximum suppliable currents of said data write circuit, and limit the value of current flowing in said memory cell at a certain current limit value, wherein said current limit circuit includes a first current mirror circuit having an input side that receives a flow of a certain reference current and an output side that supplies a flow of output current determined by said certain reference current and a certain mirror ratio, and a second current mirror circuit having an input side that receives a flow of said output current flowing through said output side of said first current mirror circuit and an output side that supplies a current limited at said certain current limit value in accordance with said output current from said first current mirror circuit and provides a voltage required for writing said data to said data write circuit.