Patent ID: 7636259

Claim:
An integrated circuit comprising: a multi-sector flash memory array comprising: a first subarray of flash memory cells, and a second subarray of flash memory cells; a first set of word lines connected with control gates of the flash memory cells of the first subarray; a first set of row drivers connected with the first set of word lines and adapted to selectively tri-state the first set of word lines or drive the first set of word lines with a first voltage; a second set of word lines connected with control gates of the flash memory cells of the second subarray; a second set of row drivers connected with the second set of word lines and adapted to selectively tri-state the second set of word lines or drive the second set of word lines with the first voltage; and a plurality of bitlines, wherein each bitline is connected with a flash memory cell of the first subarray and a flash memory cell of the second subarray.