Patent ID: 8521932

Claim:
A system management bus (SM Bus) system, comprising: an arbitrator; a slave device connected to the arbitrator via a SM Bus; a first master device connected to the arbitrator and sending a first start command for communicating with the slave device; and a second master device connected to the arbitrator and sending a second start command for communicating with the slave device; wherein the arbitrator sets the first master device to have a priority, when the first start command is being executed and the arbitrator receives the second start command, the arbitrator confirms whether the SM Bus is busy or not after a second predetermined time, if the SM Bus is not busy, the arbitrator transmits the second start command to the slave device via the SM Bus, wherein when the second start command is being executed and the arbitrator receives the first start command, the arbitrator transmits the first start command to the slave device via the SM Bus when the arbitrator confirms the SM Bus is not busy after a first predetermined time, when the arbitrator confirms the SM Bus is busy after the first predetermined time, the arbitrator sends a none acknowledgement signal (NACK) to the second master device to stop the second master device using the SM Bus, and transmits the first start command to the slave device via the SM Bus.