Patent ID: 7561470

Claim:
A method for operating a memory device comprising a plurality of charge trapping memory cells arranged in an array and coupled to a plurality of bit lines and a plurality of word lines, each charge trapping memory cell comprising source and drain terminals separated by a channel within a substrate and coupled to respective corresponding bit lines in the plurality of bit lines, a dielectric charge trapping structure overlying the channel and having one or more charge trapping sites, and a gate overlying the charge trapping structure and coupled to a corresponding word line in the plurality of word lines, wherein respective source and drain terminals of each charge trapping memory cell define a first pn junction between the source terminal and the substrate and a second pn junction between the drain terminal and the substrate, the method comprising: applying a first voltage to the plurality of bit lines and a second voltage to the substrate to reverse bias the first and second pn junctions defined by the source and drain terminals of each charge trapping memory cell in the plurality of charge trapping memory cells; and applying a third voltage to the plurality of word lines to attract charge from the substrate to the charge trapping structure of each of the plurality of charge trapping memory cells to change an amount of charge stored in each of the corresponding one or more charge trapping sites.