Patent ID: 7773332

Claim:
A sample and hold circuit having an input and an output, comprising: at least one capacitive element for retaining a charge, said at least one capacitive element connected to a node between said input and said output; at least one input switch for selectively connecting said at least one capacitive element to said input; at least one output switch for selectively connecting said at least one capacitive element to said output; and an amplifier connected to said node, wherein said amplifier has an offset voltage and wherein a voltage drop across at least one of said input and output switches is substantially limited to said offset voltage, wherein parasitic drain and source diodes (D 0 , D 1 ) of an NMOS switch are coupled to a voltage that is more negative than an input signal of said NMOS switch in a sample mode, wherein said parasitic drain and source diodes of said NMOS switch are coupled to an output of said amplifier in a hold mode, wherein parasitic drain and source diodes (D 2 , D 3 ) of a PMOS switch are coupled to a voltage that is more positive than an input signal of said PMOS switch in a sample mode, and wherein said parasitic drain and source diodes of said PMOS switch are coupled to an output of said amplifier in a hold mode.