Patent ID: 8575673

Claim:
An electrically erasable programmable memory, comprising: a semiconductor substrate having a first conductivity type; a first region and a second region having a second conductivity type, the first region and the second region being formed beneath a surface of the semiconductor substrate with a certain space left therebetween, a planar channel region being formed between the first region and the second region; a conductive floating gate formed above the surface of the semiconductor substrate and vertically covering a part of the planar channel region and a part of the first region, the floating gate being insulated from the planar channel region and the first region; a conductive source region formed above the surface of the semiconductor substrate and electrically connecting to the first region of the semiconductor substrate, a lower part of the source region being located above the first region, a lateral side of the lower part of the source region being adjacent to and insulated from the floating gate, a central part of the source region being extended in both sides to above the floating gate and being insulated from the floating gate, an upper part of the source region having a smaller width than the central part of the source region; a conductive control gate formed above the surface of the semiconductor substrate, a lower part of the control gate being adjacent to and insulated from the floating gate, an upper part of the control gate being adjacent to and insulated from the central part and the upper part of the source region; wherein, insulating material between the central part of the source region and the floating gate has a predetermined thickness to facilitate a voltage coupling between the central part of the source region and the floating gate.