Patent ID: 7164160

Claim:
An integrated-circuit device, comprising: a substrate, having a top surface and a bottom surface; and a vertical JFET, including: a first and second pate regions in a first region near the top surface of the substrate, each having a top surface, a bottom surface and a side surface; the side surfaces of the first and second gate regions being substantially parallel to each other and substantially perpendicular to the top surface of the substrate; the top surface of the first gate region being electrically communicable to a gate terminal; a channel region in the first region, between the first and the second gate regions having side surfaces adjacent to the side surfaces of the gate regions, a top surface, and a bottom surface; the top surface of the channel region electrically communicable to a source terminal, the bottom surface of the channel region electrically communicable to a drain terminal; the gate terminal, the source terminal, and the drain terminal being near the top surface of the substrate; the JFET operable to pass an electric current between the source terminal and the drain terminal, the electric current flowing in the channel region in a direction vertical to the top and bottom surfaces of the channel region; the first gate region having a pill-box shape with a substantially flat top surface and bottom surface, and a side surface substantially perpendicular to the top and bottom surfaces; the channel region having a ring shape enclosing the first gate region, a bottom surface substantially coplanar to the bottom surface of the first gate region and a top surface substantially coplanar to the top surface of the first gate region; the second gate region having a ring shape enclosing the channel region, a bottom surface substantially coplanar to the bottom surface of the first gate region and a top surface substantially coplanar to the top surface of the first gate region; and a drain plug region having a ring shape enclosing the second gate region, a bottom surface substantially coplanar to the bottom surface of the first gate region and a top surface substantially coplanar to the top surface of the first gate region.