Patent ID: 7397259

Claim:
A method of testing an electronic device in an integrated circuit, the electronic device having a plurality of nodes, comprising: measuring a first baseline current at a first node of the electronic device while the first node is driven by a reference voltage having a first frequency and no voltage is applied to a second node of the electronic device; measuring a first excited current at the first node while the first node is driven by the reference voltage having the first frequency and an excitation voltage is applied to the second node at the first frequency; measuring at least a second baseline current at the first node while the first node is driven by the reference voltage having a second frequency and no voltage is applied to the second node; measuring at least a second excited current at the first node while the first node is driven by the reference voltage having the second frequency and an excitation voltage is applied to the second node at the second frequency; calculating at least two current differences, between the first baseline current and the first excited current and between the second baseline current and the second excited current; generating a linear relationship between the current differences and the first and second frequencies; and deriving a capacitance between the first node and the second node based on the linear relationship.