Patent ID: 7716398

Claim:
A buffer comprising: a plurality of N serial inputs; a plurality of N de-serializers, each coupled to a respective one of the N serial inputs, and each configured to convert serial data received on the respective one of the N serial inputs into M-bit parallel data, whereby the plurality of N de-serializers provide a plurality of N M-bit parallel data outputs, wherein data is transferred by the plurality of N M-bit parallel data outputs at a first bit rate; a first dual-port buffer; a second dual-port buffer; and a media access controller coupled to receive the N M-bit parallel data outputs from the plurality of N de-serializers, wherein the media access controller simultaneously transfers data received from the plurality of N de-serializers to the first dual-port buffer and the second dual-port buffer, wherein the media access controller uses separate control outputs to control the first and second dual-port buffers, wherein data is transferred at a second bit rate to the first dual-port buffer on a first set of lanes having a width of N×M, and wherein data is transferred at the second bit rate to the second dual-port buffer on a second set of lanes having a width of N×M, wherein the second bit rate is half of the first bit rate.