Patent ID: 7619278

Claim:
A semiconductor-memory device comprising as one cell unit: a substrate having a trench section of a specified depth; a selector gate that is located via a first insulating film in a first area on said substrate that is adjacent to said trench section; a first well, comprising implanted ions, that is formed on a surface of said substrate below said selector gate; a floating gate that is located via a second insulating film in a second area on a surface of a bottom section and sidewall of said trench section that is adjacent to said first area; a second well, comprising implanted ions, that is formed on the surface of the bottom section of said trench section that is below said floating gate; a first diffusion area that is formed in a third area on the surface of the bottom section of said trench section and adjacent to said second area; and a control gate that is located via a third insulating film on top of said floating gate, wherein said control gate three-dimensionally crosses over said selector gate, wherein a second diffusion area is formed in a fourth area on the surface of said substrate located in an extending section of said selector gate, wherein an area near a sidewall surface and the bottom surface of said trench section in said selector gate forms a channel, and wherein an impurity density of said first well is not more than an impurity density of said second well.