Patent ID: 8122187

Claim:
A memory system comprising: a memory including: a temperature sensor configured to measure a first temperature of the memory and to provide a first temperature output corresponding to the measured first temperature, wherein the first temperature output comprises first temperature data bits; and a rewritable temperature register configured to encode the first temperature output using a bit encoding scheme in which the first temperature data bits are converted into first multiplier data bits, wherein a first portion of the first multiplier data bits represents a first refresh clock rate multiplier and a second portion of the first multiplier data bits represents a first system clock rate multiplier, and wherein the second portion of the first multiplier data bits includes at least one data bit that is not included in the first portion of the first multiplier data bits; and a memory controller configured to receive the first multiplier data hits, the memory controller including: a refresh clock responsive to the first refresh clock rate multiplier to control an auto-refresh rate of the memory; and a system clock responsive to the first system clock rate multiplier to control a system clock rate of the memory controller.