Patent ID: 8683106

Claim:
A processing system having an architecture with a base bandwidth B B , the processing system comprising: a pipelined network connection formed as a ring with a bandwidth B BUS which is a multiple of the base bandwidth B B and with (B BUS /B B ) being a natural number larger than 1, where “/” represents integer division, to enable a possibility to transfer multiple data sets with the base bandwidth B B at a same time; processing elements with a possibly different bandwidth connection (X PE *B B ) with X PE being a natural number larger than 0 to said pipelined ring network; processing units, formed of one or several processing elements which are grouped and controlled together, with a different bandwidth connection (x PU *B B ) with x PU being a natural number larger than 0 to said pipelined ring network; and a control apparatus controlling over said pipelined ring network; a fast data spreading transfer mode with one sending processing unit and a plurality of receiving processing units, wherein a bandwidth connection of the sending processing unit equals a sum of bandwidth connections of the plurality of receiving processing units; and/or a fast data collection transfer mode with a plurality of sending processing units and one receiving processing unit, wherein a sum of bandwidth connections of the sending processing units equals a bandwidth connection of the receiving processing unit.