Patent ID: 8207595

Claim:
A semiconductor device comprising: a substrate wafer; a first dielectric layer overlying the substrate wafer; a patterned conductor layer in the first dielectric layer; a first barrier layer overlying the conductor layer in the first dielectric layer; a top wafer overlying the dielectric layer; a conductive layer extending through the top wafer and through a portion of the first dielectric layer to the first barrier layer, the conductive layer being narrower along the first dielectric layer than along the top wafer; a sidewall dielectric layer between the conductive layer and the top wafer, the sidewall dielectric layer adjacent the top wafer from the first dielectric layer to a distance below an upper surface of the top wafer, thereby forming an upper sidewall dielectric layer shoulder; a sidewall barrier layer between the conductive layer and the top wafer and adjacent the conductive layer, the sidewall barrier layer extending from the first barrier layer to the upper surface of the top wafer; and top barrier layer overlying the conductive layer, the sidewall barrier layer, and the top wafer, thereby encapsulating the conductive layer in the barrier layers.