Patent ID: 8396208

Claim:
A memory system comprising: non-volatile memory; a circuit operative to detect a presence of one or more error(s) in data read from the non-volatile memory and further operative to generate a signal indicating the presence of the one or more error(s) in the data; a cryptographic circuit operative to perform cryptographic processes on the data; at least one buffer operative to store the data read from the non-volatile memory before the data is sent to the cryptographic circuit; and a processor operative to receive the signal indicating the presence of the one or more error(s) in the data and, in response to receiving the signal, correct the one or more error(s) in the data stored in the at least one buffer before the data is sent from the at least one buffer to the cryptographic circuit; wherein a portion of a data stream from the non-volatile memory to the cryptographic circuit is first error detected and later cryptographically processed, and wherein while one portion of the data stream is being error detected, another portion of the data stream is being cryptographically processed.