Patent ID: 8890064

Claim:
A method of processing a semiconductor wafer, comprising: assigning the semiconductor wafer a wafer ID; storing at least one recipe for sample extraction in a host processor; selecting at least one recipe by a controller for the processing of the wafer, said recipe including positional data for one or more sample sites to be analyzed; loading the wafer into a charged particle beam system, said charged particle beam system to process the wafer according to the selected process recipe values; navigating to each sample site using said positional data; imaging each sample site; identifying at least one desired first fiducial location for said first sample site; milling a combination of at least one high precision fiducial mark and one low precision fiducial mark at the desired first fiducial locations; determining the edge positions for the sample with respect to said fiducial marks automatically milling the wafer surface on either side of each desired sample location leaving a thin layer of material; transferring the one or more samples to an ex-situ lamella extraction device, said device importing recipe values including positional data for each sample site; extracting the one or more samples from the wafer using said recipe values; transferring the one or more samples to a TEM system, said TEM importing recipe values for each sample and said TEM also processing the one or more samples according to the values specified by the recipe, said processing including imaging the samples and analyzing the images; imaging the one or more samples with the TEM; analyzing the TEM images to determine a feature dimension for the one or more sample sites; and adjusting the positional data or fiducial mark locations at additional sample sites in response to the determined dimension.