Patent ID: 8503221

Claim:
A Static Random Access Memory (SRAM) incorporating a plurality of five transistor (5 T) memory bit cells, each comprising: first inverter connected between a fixed supply voltage and a first virtual ground voltage, wherein first inverter gate has a first storage node Q as input and a second storage node/Q as output; a second inverter, cross-coupled with the first inverter, connected between said fixed supply voltage and a second virtual ground voltage, wherein second inverter gate has the second storage node/Q as input and the first storage node Q as output; a BIT line; a pass transistor for selectively connecting said BIT line to the first storage node; standby switches for selectively connecting said BIT line and said first and second virtual ground lines to a common standby voltage when the bit cell is not selected; and control switches for selectively connecting said first and second virtual ground lines to voltages other than the standby voltage when the bit cell is selected for one of reading, writing, or write masking operations.