Patent ID: 8467233

Claim:
A solid-state memory cell, comprising: a first inverter circuit including an inverter and a pass-gate transistor, having an output for coupling a first storage node between its inverter and its pass-gate transistor to a first bit line, and having an input, the first inverter circuit constructed of one or more p-channel metal-oxide-semiconductor (MOS) transistors, and one or more n-channel MOS transistors, wherein the p-channel MOS transistors are constructed with a compressive liner layer and the n-channel MOS transistors are constructed with a tensile liner layer; and a second inverter circuit including an inverter and a pass-gate transistor, having an output for coupling a second storage node between its inverter and its pass-gate transistor to a second bit line, the second storage node coupled to the input of the inverter, the second inverter circuit having an input coupled to the first storage node in the first inverter circuit, the second inverter circuit constructed of one or more p-channel MOS transistors and one or more n-channel MOS transistors; wherein one of the MOS transistors of the second inverter circuit is constructed with a liner layer of opposite stress characteristics from that of a corresponding MOS transistor in the first inverter circuit.