Patent ID: 7937576

Claim:
A multilevel memory device comprising: a read only memory to store a power-on algorithm code; a plurality of addressable configuration fuses to store configuration bits of the multilevel memory device; a plurality of addressable latches to store configuration bits, the plurality of addressable latches having a one-to-one correspondence to said plurality of addressable configuration fuses; an ancillary random access memory; and a microcontroller to execute the power-on algorithm code stored in said read only memory to generate configuration data based on the configuration bits of the plurality of addressable configuration fuses and the plurality of addressable latches, wherein the configuration data is different from the configuration bits and is indicative of either a number of wait cycles related to operation of the microcontroller or a voltage code related to operation of a digital-to-analog converter, and to write the configuration data in the ancillary random access memory to facilitate operation of control algorithms performed during an operation phase of the multilevel memory device.