Patent ID: 7589557

Claim:
An integrated circuit, comprising: an input/output (I/O) pad; an input buffer having an input terminal coupled to the I/O pad and further having an output terminal; an output buffer having an input terminal and further having an output terminal coupled to the I/O pad; a delay element having an input terminal and an output terminal; wherein the delay element includes a delay line, and for an input signal received at the input buffer, the delay element delays a signal through the delay line by a first delay, and for an output signal to be output at the output buffer the delay element delays a signal through the delay line by a second delay; wherein the first delay and the second delay are individually programmable to provide different amounts of delay for the input and output signals; a delay multiplexer circuit having a first data input terminal, a second data input terminal coupled to the output terminal of the input buffer, and a data output terminal coupled to the input terminal of the delay element; an output multiplexer circuit having a first data input terminal coupled to the first data input terminal of the delay multiplexer circuit, a second data input terminal coupled to the output terminal of the delay element, and an output terminal coupled to the input terminal of the output buffer; and an input multiplexer circuit having a first data input terminal coupled to the second data input terminal of the delay multiplexer circuit, a second data input terminal coupled to the output terminal of the delay element, and an output terminal.