Patent ID: 7747828

Claim:
A memory device, comprising: one or more ports, each port capable of interfacing with external read/write signals; an input read register coupled to the one or more ports and to a first set of external binary state devices, the input read register associated with a first memory address; and an output drive register coupled to the one or more ports and to a second set of external binary state devices, the output drive register associated with a second memory address, wherein, the input read register includes a first set of bits that are capable of reflecting a first set of state signals associated with the first set of external binary state devices and the first set of state signals associated with the first set of external binary state devices can be read using the first memory address, the output drive register includes a second set of bits that are capable of reflecting a second set of state signals associated with the second set of external binary state devices and are further capable of altering the second set of state signals associated with the second set of external binary state devices and the second set of state signals associated with the second set of external binary state devices can be read or altered using the second memory address, the external binary state devices each have a corresponding state, the state signals each reflect the state of the corresponding external binary state device, and wherein a state signal in the second set of state signals alters the state of corresponding external binary state devices.