Patent ID: 7280386

Claim:
A dynamic random access memory device, comprising: an array of memory cells arranged in rows and columns, at least some of the rows containing at least one memory cell that may be unable to retain data bits during refresh, the memory cells in each column being coupled to one digit line in a respective pair of complementary digit lines for the respective column; an address decoder receiving row addresses and column addresses, the address decoder being operable to activate a row of memory cells corresponding to each received row address and to select a memory cell in a column of memory cells corresponding to each received column address; a read data path operable to couple read data from a selected memory cell in an activated row to a data bus terminal; a write data path operable to couple write data from the data bus terminal to a selected memory cell to in an activated row; a respective sense amplifier coupled between each of the pairs of complementary digit lines to sense a voltage differential between the respective pair of digit lines; a plurality of comparator circuits each of which coupled to the respective pair of complementary digit lines for the respective column of memory cells, the plurality of comparator circuits being coupled to each other to provide a comparison indication indicative of a predetermined comparison of the voltages between the digit lines in each pair of all of the complementary digit line pairs; and control logic coupled to the array of memory cells and a row address comparator, the control logic being operable to cause predetermined bits to be written to the memory cells in each row of memory cells and to cause data bits from the memory cells in each row to subsequently be read to allow the comparator circuit to provide the comparison indication.