Patent ID: 8504743

Claim:
An information processing system, comprising: a master module outputting a transfer state signal for each data read instruction when a plurality of data read instructions are successively output, each transfer state signal including a first signal state indicating that at least one more data read instruction succeeds the current data read instruction and a second signal state indicating that no more data read instructions succeed the current data read instruction; and a memory controller configured to when receiving a data read instruction and the transfer state signal indicating the first signal state from the master module, supply data corresponding to the current data read instruction to the master module, while reading data corresponding to the at least one more data read instruction that succeeds the current data read instruction from a memory and hold the read data corresponding to the at least one more data read instruction, and when receiving a data read instruction and the transfer state signal indicating the second signal state from the master module, supply data corresponding to the current data read instruction to the master module without newly executing an operation of reading data from the memory, wherein the memory controller calculates a read address of the at least one more data read instruction that succeeds the current data read instruction based on a transfer address, a transfer length, and a transfer size, which are requested from the master module.