Patent ID: 7965098

Claim:
A current mode logic voter circuit, comprising: a plurality of N-input split NOR gates and a plurality of M-input split NOR gates, the NOR gates operable in combination as a voter circuit for M mode redundancy in current mode logic circuitry without propagating errors that arise due to single event upset conditions; wherein each of the N-input split NOR gates comprises a plurality of hardened current mode logic buffer circuits; and wherein each hardened current mode logic buffer circuit comprises: a current source adapted to be coupled between a first node and a voltage reference node; a first NMOS transistor coupled in series with a first pull-up resistor and a first isolation resistor between the first node and a supply voltage node, the first NMOS transistor adapted to receive a first input signal on a gate node and operable to generate a first output signal on a drain node; and a second NMOS transistor coupled in series with a second pull-up resistor and a second isolation resistor between the first node and the supply voltage node, the second NMOS transistor adapted to receive a second input signal on a gate node and operable to generate a second output signal on a drain node.