Patent ID: 7949859

Claim:
A processor, comprising: a queue configured to store instructions; an execution unit coupled to said queue, wherein said execution unit is configured to receive an instruction from said queue; and a register coupled to said execution unit, wherein said register is configured to store a value corresponding to an address in physical memory, wherein said execution unit further comprises: logic for receiving a speculative instruction with an address from said queue; logic for comparing said speculative instruction address with said value from said register to determine whether said speculative instruction address exists in physical memory; logic for executing said speculative instruction if said address of said speculative instruction is at or below said value; logic for determining if said speculative instruction is a next to complete instruction if said address of said speculative instruction is above said value; logic for executing said speculative instruction if said speculative instruction is said next to complete instruction; and logic for rejecting said speculative instruction if said speculative instruction is not a next to complete instruction and if said address of said speculative instruction is above said value to thereby avoid a check stop due to speculative activity.