Patent ID: 7378892

Claim:
A device for setting a clock delay, comprising: at least one delay circuit configured to delay an input clock signal in order to generate at least one delayed output clock signal of the device, the at least one delay circuit comprising a plurality of delay elements, each providing one of a plurality of differently delayed clock signals; a delay-locked loop configured to control the delay provided by the at least one delay circuit, the delay-locked loop comprising a comparison unit for a phase comparison of at least one clock signal delayed by a delay circuit of the delay-locked loop with a reference clock signal, the delay-locked loop further comprising a control unit configured to generate a control signal for the at least one delay circuit on the basis of an output signal of the comparison unit, wherein the at least one delay circuit is independent of the delay circuit of the delay-locked loop; a multiplexer configured to receive the plurality of differently delayed clock signals, the device being configured to generate the at least one delayed output clock signal with a settable phase relationship to the input clock signal by controlling the multiplexer circuit with a phase selection control signal to select between the plurality of differently delayed clock signals; and a phase setting controller configured to receive the input clock signal and the at least one delayed output clock signal and to generate the phase selection control signal on the basis of a phase comparison between the input clock signal and the at least one delayed output clock signal such that the phase relationship between the at least one delayed output clock signal and the input clock signal is automatically controlled to a desired phase relationship.