Patent ID: 8717836

Claim:
A semiconductor memory device comprising: a plurality of word lines arranged in rows; a plurality of bit lines arranged in columns; an address decoder that selects one of the word lines in response to an address signal; a sense amplifier that amplifies potentials generated on the bit lines; and a sense amplifier control circuit in which the more distant the word line selected by the address decoder is from the sense amplifier, the later the sense amplifier is activated, and wherein the sense amplifier is activated in response to a sense amplifier enable signal, and the sense amplifier control circuit includes a delay time adjustment circuit in which the more distant the word line selected by the address decoder is from the sense amplifier, the longer a delay time of the sense amplifier enable signal is set, wherein the sense amplifier control circuit further includes a pulse width adjustment circuit, wherein the pulse width adjustment circuit includes a one shot pulse generation circuit, the one shot pulse generation circuit includes: an odd number of inverters; and an AND circuit that accepts an input signal of the one shot pulse generation circuit and an output signal of the last inverter out of the odd number of inverters, and the pulse width adjustment circuit includes means for changing the number of the inverters.