Patent ID: 8865524

Claim:
A method of forming a lead carrier for providing electrical interconnection of an integrated circuit chip within an electrical system, the lead carrier including a temporary layer formed of high temperature resistant material, the temporary layer having a top surface, at least two sintered structures upon the top surface of the temporary layer, the sintered structures formed of electrically conductive material, a semiconductor device upon one of the at least two sintered structures, a wire bond between the semiconductor device and one of the at least two sintered structures spaced from the semiconductor device each of the semiconductor device, the wire bond and the sintered structures at least partially encapsulated within a substantially electrically non-conductive material; placing the sintered structures on the temporary layer with at least one of said sintered structures having a portion thereof above a bottom side that is larger than a portion thereof closer to the bottom side, such that an overhang is provided; placing the semiconductor upon one of the at least two sintered structures; placing a wire bond between the semiconductor device and one of the sintered structures; encapsulating the sintered structures, the semiconductor device and the wire bond at least partially within a substantially electrically non-conductive material; and peeling the temporary layer from the sintered structures and the encapsulating material.