Patent ID: 8572322

Claim:
In a data processing system comprising a scheduler and one or more processor cores coupled to a memory by a memory access controller, a method comprising: scheduling by the scheduler pending memory access requests for servicing by the memory using a first clock signal having a first frequency, the scheduling comprising determining an order in which to service the pending memory access requests; and servicing the scheduled pending memory access requests by the memory access controller using a second clock signal having a second frequency different than the first frequency, wherein: the memory access controller maintains memory timing and state information for administering the servicing of the scheduled pending memory access requests; the determining comprises determining the order based upon predictions by the scheduler of the memory timing and state information maintained by the memory access controller for administering the servicing of the scheduled pending memory access requests; and the scheduling includes removing the pending access requests from a queue of pending memory access requests and sending them to the memory access controller for servicing.