Patent ID: 7863959

Claim:
A device comprising: a storage node; a latch circuit coupled to the storage node, the latch circuit to latch data provided to the storage node during one of a first mode and a second mode of the device, the latch circuit including a first transistor coupled between a first voltage node and a second voltage node, a second transistor coupled in series with the first transistor between the first and second voltage nodes, and a third transistor coupled between the first and second transistors and coupled in series with the first and second transistors between the first voltage node and the second voltage node, the third transistor configured to turn on prior to an end of the first mode before the data is provided to the storage node and to stay on during the second mode when the data is provided to the storage node; a fourth transistor to reset the storage node, the fourth transistor configured to turn off after the third transistor turns on; and a fifth transistor to pass the data to the storage node, the fifth transistor configured to turn on after the fourth transistor turns off.