Patent ID: 8158333

Claim:
A method of manufacturing a semiconductor device comprising a word line (WL) portion, a selection gate (SG) portion, and a peripheral circuit, the method comprising: forming a stacked film including a first layer, a second layer, and a third layer on a substrate, the first layer being formed on the second layer, the second layer being formed on the third layer, and the third layer being formed on the substrate; forming a first resist pattern on the first layer; slimming the first resist pattern; forming a first film pattern by etching the first layer using the slimmed first resist pattern as a mask, such that the first film pattern is wider in the SG portion and the peripheral circuit than in the WL portion; forming a second film pattern by etching the second layer using the first film pattern as a mask after removing the slimmed first resist pattern, the second film pattern including a first area and a second area which includes finer patterns than the first area, the first area being in the SG portion and the peripheral circuit and the second area being in the WL portion; forming sidewall spacers at respective sidewalls of the second film pattern; after forming the sidewall spacers, forming a second resist pattern covering only the first area; after forming the second resist pattern removing the second film pattern of the second area exposed from the second resist pattern; after removing the second resist pattern, etching the third layer using the first layer remained on the first area and the sidewall spacers to form a third film pattern; and after forming the third film pattern, removing the first layer remained on the first area and the sidewall spacers so that the third film pattern remains.