Patent ID: 8373252

Claim:
An integrated circuit, comprising: a semiconductor substrate having a front surface and a back surface; a plurality of through-semiconductor vias extending from the front surface to the back surface, the plurality of through-semiconductor vias including a first via and a second via; a plurality of transistors disposed at the front surface of the semiconductor substrate; wherein the plurality of transistors has a first plurality of electrodes and a second plurality of electrodes; at least one patterned metal layer disposed on the front surface of the semiconductor substrate, the at least one patterned metal layer providing a first network and a second network; wherein the first network couples the first plurality of electrodes to the first via, and the second network couples the second plurality of electrodes to the second via; and a first and second patterned metal layer disposed on the back surface of the semiconductor substrate and separated by a dielectric layer, the first patterned metal layer including a first metal plate coupled to the first via, and the second patterned metal layer including a second metal plate coupled to the second via; wherein a decoupling capacitor includes the first and second metal plates separated by the dielectric layer.