Patent ID: 7447972

Claim:
An apparatus for constructing a low density parity check matrix, comprising: at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix, wherein the index generator is implemented by a modular shift register generator to generate a row index of a “1” at each clock, and wherein the index generator comprises: “s” number of registers connected in series to receive an initial value of “s” bits, store the initial value bit-by-bit, and each shift corresponding stored bit to a succeeding register at a clock; a feedback line through which a bit value stored in a last one of the registers is selectively fed-back; and an adder connected between every two registers, to add a bit value of a preceding register with a fed-back value and provide a resulting value to the succeeding register.