Patent ID: 8367558

Claim:
A method for tuning the work function of a metal gate of a PMOS device, comprising, after formation of a device isolation, the steps of 1) cleaning a silicon substrate with the device isolation formed therein; 2) performing rapid thermal oxidation at about 600-900° C. for about 20-120 seconds, so as to form an interface layer of SiOx or SiON at the surface of the silicon substrate; 3) forming a high-k gate dielectric layer on the interface layer by physical vapor deposition, wherein a Hf—La target and a Hf target are sputtered alternatively in a magnetron reactive sputtering process for deposition of HfLaON, or a Hf target and a Si target are sputtered alternatively in a magnetron reactive sputtering process for deposition of HfSiON, and the high-k gate dielectric layer having different compositions and thicknesses is obtained by adjusting sputtering power or duration for alternative sputtering; 4) performing rapid thermal annealing at about 600-1050° C. for about 10-120 seconds; 5) forming a metal nitride gate on the gate dielectric layer by physical vapor deposition, wherein the metal nitride gate is deposited in a magnetron reactive sputtering process; 6) doping the metal nitride gate by ion implantation of p-type ions; 7) etching to form a metal gate stack; 8) performing thermal annealing at about 350-1050° C.; 9) forming back-side ohmic contacts by physical vapor deposition, wherein an Al—Si layer is deposited on the back side by a direct current sputtering process; 10) alloying the resulting structure by annealing in an alloying oven in N2 gas or forming gas at about 380-450° C. for about 30-60 minutes; wherein the p-type ions are driven to an interface between the high-k gate dielectric and interfacial SiO 2 by the rapid thermal annealing so that the p-type ions accumulate at the interface or generate dipoles by interfacial reaction.