Patent ID: 8470644

Claim:
A method of forming an electronic assembly, comprising: providing a packaged semiconductor device comprising a semiconductor die including a substrate having a topside including active circuitry and a bottomside, and at least one backside metal layer on said bottomside of said substrate, wherein said backside metal layer is directly attached to said bottomside of said semiconductor die and an area of said backside metal layer matches an area of said bottomside of said semiconductor die; a package including a molding material having a die pad and a plurality of leads encapsulated within said molding material, wherein said plurality of leads include an exposed portion that includes a bonding portion; wherein said topside of said semiconductor die is attached to said die pad, wherein said package includes a gap that exposes said backside metal layer along a bottom surface of said package, and bond wires coupling pads on said topside of said semiconductor die to said plurality of leads, and wherein said bonding portions, said molding material along said bottom surface of said package, and said backside metal layer are all substantially planar to one another, directly soldering said packaged semiconductor device to a printed circuit board (PCB) including a plurality of surface pads, wherein said backside metal layer and said bonding portions of said plurality of leads are soldered to ones of said plurality of surface pads on said PCB.