Patent ID: 7283406

Claim:
A wordline driver circuit for a memory device, the circuit comprising: a logic stage operating between a ground voltage and a first supply voltage during a programming process for receiving one or more input signals from a decoder of the memory device and generating a logic stage output signal swinging between the ground voltage and the first supply voltage; a mid voltage stage, operating between a raised ground voltage and a second supply voltage during the programming process, having a pull-down transistor serially coupled to a pull-up transistor whose gate and drain are cross-connected to those of a feedback gate control transistor, and having the gates of the pull-down and pull-up transistors receiving the logic stage output signal, a high voltage stage, operating between the raised ground voltage and a third supply voltage during the programming process, and having a pull-down transistor serially coupled to a pull-up transistor whose gate and drain are cross-connected to those of a feedback gate control transistor; wherein the second supply voltage is between the third supply voltage and the raised ground voltage, wherein the pull-down and pull-up transistors in the mid and high voltage stages are coupled between the raised ground voltage and the second and third supply voltages respectively, and wherein the gate of the pull-down transistor in the high voltage stage is controlled by the drain of the pull-up transistor in the mid voltage stage.