Patent ID: 8313979

Claim:
A method for manufacturing a device, the method comprising: forming a first field effect transistor in a first region of a substrate, forming the first field effect transistor comprising: forming first and second doped regions separated by a horizontal channel region within the substrate; forming a gate of the first field effect transistor overlying the horizontal channel region; and forming a first dielectric on the substrate in covering the gate of the first field effect transistor and over a second region of the substrate; and forming a second field effect transistor in the second region of the substrate, forming the second field effect transistor comprising: forming a first terminal extending through the first dielectric to contact the substrate; forming a second terminal overlying the first terminal and having a top surface; forming a vertical channel region separating the first and second terminals; forming a gate of the second field effect transistor on the first dielectric and adjacent the vertical channel region, the gate of the second field effect transistor having a top surface that is co-planar with the top surface of the second terminal; and forming a second dielectric separating the gate of the second field effect transistor from the vertical channel region.