Patent ID: 8781042

Claim:
A calibration circuit configured to remove DC offset from a signal, the signal including a sequence of symbols that include a first symbol and a second symbol, the second symbol being subsequent to the first symbol in the sequence of symbols, the DC calibration circuit comprising: an input configured to receive the first symbol and the second symbol; a first-symbol correction circuit configured to, while the first symbol is being received by the input, (i) determine a first DC offset value from the first symbol, and (ii) subtract the first DC offset value from the first symbol to compensate for DC offset in the first symbol; a second-symbol correction circuit configured to (i) determine, independent of the determining of the first DC offset value, a second DC offset value from the first symbol, and (ii) while the second symbol is being received by the input, subtract the second DC offset value from the second symbol to compensate for DC offset in the second symbol.