Patent ID: 7539277

Claim:
A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, the modulus divider controller comprising: a first binary stream switching circuit having a first output and a second output, the first binary stream switching circuit further having a logic low input and a logic high input and a first switching input corresponding to a least significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock, and a second switching input corresponding to a most significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock; and a second binary stream switching circuit having the first output of the first binary stream switching circuit as a first input and the second output of the first binary stream switching circuit as a second input, the second binary stream switching circuit further having a first switching input corresponding to a bit next to the least significant bit of the count generated by the synchronous counter and a second switching input corresponding to a bit next to the most significant bit of the division control word, wherein the second binary stream switching circuit generates a modulus control output for the modulus divider based on the first input, the second input, the first switching input, and the second switching input corresponding to the second binary stream switching circuit.