Patent ID: 6938145

Claim:
A computer system including a central processing unit (CPU) and an addressable main memory storing data pages, at least one data page storing a page table, said CPU comprising: A) a processor coupled to said main memory; B) an associative memory storing a plurality of entries, each entry in said associative memory being stored in accordance with a low order virtual address component issued by said processor, each entry in said associative memory including fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count; C) a multi-digit counter storing a current validity count; D) a comparator coupled to receive: 1) a high order virtual address component of a requested data page in said main memory from said processor when access to the requested page is desired during the ongoing activity of the CPU; said processor also sending a low order virtual address component of the requested data page to said associative memory to specify an entry therein; 2) the high order virtual address component read from the specified associative memory entry; 3) the multi-digit validity count read from the specified associative memory entry; and 4) the multi-digit current validity count in the counter; E) a switch coupled to receive the real page address read from the specified associative memory entry and, when enabled, issue the real page address; and F) said comparator issuing a signal to enable said switch when: 1) there is a match between the high order virtual address components received, respectively, from said processor and said associative memory; and 2) there is a match between the multi-digit validity counts received, respectively, from said counter and said associative memory.