Patent ID: 7842559

Claim:
A method of fabricating a multi-gate device comprising: providing a substrate comprising a first semiconductor layer having at least a first carrier mobility enhancing parameter, a buried insulating layer on the first semiconductor layer, a second semiconductor layer having at least a second carrier mobility enhancing parameter on the buried insulating layer, wherein the first carrier mobility enhancing parameter comprises any of a first crystalline orientation or a first crystalline direction or a first semiconductor material or a first stress or a first combination thereof and wherein the second carrier mobility enhancing parameter comprises any of a second crystalline orientation or a second crystalline direction or a second semiconductor material or a second stress or a second combination thereof, the second carrier mobility enhancing parameter being different from the first carrier mobility enhancing parameter defining a first active region and a second active region in the substrate, the first active region being electrically isolated from the second active region; providing a first dielectric layer on the substrate; providing a second dielectric layer on the first dielectric layer; forming in the first active region at least a first trench through the first dielectric layer, the second dielectric layer, the second semiconductor layer and the buried insulating layer; forming a first fin in the at least first trench, the first fin protruding above the first dielectric layer, the first fin having at least the first carrier mobility enhancing parameter; forming in the second active region at least a second trench through the first dielectric layer and the second dielectric layer; forming a second fin in the at least second trench, the second fin protruding above the first dielectric layer, the second fin having at least the second mobility enhancing parameter; and removing the second dielectric layer to expose the first fin and the second fin.