Patent ID: 7529864

Claim:
A method of testing a remote I/O sub-assembly, comprising: (a) allocating a source memory location, a destination memory location and a direct memory access queue memory location in a memory device of said remote I/O sub-assembly, said remote I/O sub-assembly including a micro-processor coupled to said memory device and to an I/O hub, said I/O hub including a direct memory access engine coupled to a pair of first and second remote I/O ports, a first remote I/O port of said pair of remote I/O ports having an inbound pin and an outbound pin, and a second remote I/O port of said pair of I/O ports having an inbound pin and an outbound pin; (b) writing test data into said source memory location; (c) writing a set of descriptors simulating data transfer commands that transfer data between said source and destination memory locations into said direct memory access queue memory location; (d) directly connecting said inbound pin of said first remote I/O port of said I/O hub to said outbound pin of said second remote I/O port of said I/O hub and directly connecting said inbound pin of said second remote I/O port of said remote I/O hub sub-assembly to said outbound pin of said first remote I/O port of said remote I/O hub sub-assembly; (e) configuring said direct memory access engine of said remote I/O sub-assembly to point to said direct memory access queue memory location and to said first and second remote I/O ports; (f) loading each descriptor of said set of descriptors into said direct memory access engine and transferring said test data from said source memory location to said destination memory location based on said descriptors; and (g) comparing said test data in said source memory location to resultant data in said destination memory location after said transferring of said test data.