Patent ID: 8095586

Claim:
A method of floating point arithmetic on a computing device, the method comprising: performing, in an arithmetic circuit comprising rounding logic, a floating point operation on one or more floating point numbers of precision P 1 in base b, the performing comprising: performing the floating point operation to obtain a positive intermediate result res 0 of precision greater than P 1 ; and rounding positive result res 0 to precision P 1 to the nearest away, thereby producing positive result res 1 of the floating point operation; rounding the result res 1 to precision P 2 to the nearest away, where precision P 2 is narrower than precision P 1 , thereby producing result res 2 ; and correcting res 2 for double rounding errors, wherein the correcting is performed by a correcting logic, the correcting comprising: determining that res 1 is midway between two consecutive floating point numbers of precision P 2 , the larger being res 2 ; determining that rounding res 0 to produce res 1 involved rounding up; decrementing the significand of res 2 to obtain res 2 ′; determining that the significand of res 2 ′ is equal to b (P2-1)− 1; setting the significand of res 2 ′ equal to b P2 −1; and decrementing the unbiased exponent of res 2 ′, wherein res 2 ′ is the corrected result.