Patent ID: 7189586

Claim:
A test key structure for monitoring Gate Conductor-to-Deep Trench capacitor (GC-DT) misalignment, comprising: a substrate; a plurality of trench capacitors embedded in the substrate in an interlacing matrix manner; columns of gate conductor (GC) lines defined on the substrate and passing over the trench capacitors; a first bit line contact, surrounded by first assistant bit line contacts, wherein the first bit line contact is disposed on a right side of a first trench capacitor; a second bit line contact surrounded by second assistant bit line contacts, wherein the second bit line contact is disposed on a left side of a second deep trench capacitor; an active area situated in the substrate and the active area being electrically connected to the first and second bit line contacts; and rows of bit lines including a signal-in bit line connected to the first bit line contact, a signal-out bit line connected to the second bit line contact, and a plurality of floating dummy bit lines overlying the corresponding first and second assistant bit line contacts.