Patent ID: 7274692

Claim:
An apparatus comprising: an input port configured to receive a first packet that has two or more recipients; two or more output ports that are each configured to output the first packet to one or more of the recipients; scheduling logic configured to route the first packet to at least one of the output ports if at least one of the recipients has an input buffer available to receive the first packet and even if one or more other ones of the recipients do not have an input buffer available to receive the first packet, and wherein the scheduling logic is configured to subsequently route the first packet to the one or more other ones of the recipients; and a scheduler configured to allocate an entry corresponding to the first packet in response to the input port receiving the first packet, and wherein the entry comprises a plurality of recipient bits, wherein each recipient bit corresponds to a potential recipient of the recipients coupled to the output ports, wherein a value of each recipient bit identifies whether a respective potential recipient is one of the first packet's recipients, and wherein the scheduling logic is further configured to modify the entry if the scheduling logic routes the first packet to a first portion of the first packet's recipients so that the plurality of recipient bits no longer identify the first portion of the recipients as recipients of the first packet.