Patent ID: 7906390

Claim:
A method, comprising: forming a dielectric trench isolation in a semiconductor substrate; forming a first layer on a top surface of said semiconductor substrate and on a top surface of said trench isolation; patterning said first layer into a line, and ion implanting a source extension and a drain extension into said substrate on opposite sides of said line, said source and drain extensions separated by a channel region of said substrate under said line; forming dielectric spacers on opposite sidewalls of said line, said spacers having inner walls abutting said line and outer walls away from said line; forming a source and a drain in said substrate where said substrate is not protected by said line or said spacers; forming a second layer over said source, said drain, said trench isolation and said spacers; removing said line from over said channel region to form a trench defined by said inner walls of said spacers and said top surface of said substrate; forming a gate dielectric layer on said top surface of said substrate in said channel region; forming a metal or metal alloy gate electrode on a top surface of said gate dielectric layer and said inner walls of said spacers, said gate electrode extending over said trench isolation, said gate electrode and said gate dielectric layer not filling said trench; forming a dielectric third layer on a top surface of said gate electrode, said gate electrode and said third layer not filling said trench; forming a dielectric fourth layer on said top surface of said third layer, said fourth layer filling remaining space in said trench; performing a planarization process to coplanarize a top surface of said third and fourth layers; wherein said first layer is a dielectric layer and said second layer comprises a second upper layer and a second lower layer; removing portions of said second upper and lower layers, said dielectric spacers, said gate electrode and said dielectric third layer so a top surface of said dielectric fourth layer is raised above top surfaces of said second upper and lower layers, said dielectric spacers, said gate electrode and said dielectric third layer.