Patent ID: 7002846

Claim:
A non-volatile semiconductor memory device comprising: a memory transistor having over a semiconductor substrate's well region a floating gate and a control gate deposited on said floating gate, said memory transistor having a threshold voltage set to a first voltage to store a data signal of a first logic level, said memory transistor having said threshold voltage set to a second voltage higher than said first voltage to store a data signal of a second logic level; a first detection circuit detecting said memory transistor's threshold voltage; a write circuit applying a prescribed voltage to said memory transistor between a drain and a source and applying a pulse signal train between said control gate and said well region, and increasing said memory transistor's threshold voltage from said first voltage to said second voltage; and a control circuit driven by a resultant detection provided by said first detection circuit to set an initial value of an amplitude voltage of said pulse signal train and increase said pulse signal train's amplitude voltage at a prescribed rate.