Patent ID: 8188792

Claim:
A circuit comprising: first and second transistors coupled as a differential pair, wherein a first input voltage is provided to a control input of the first transistor, and a second input voltage is provided to a control input of the second transistor; and a current mirror circuit comprising a third transistor, a fourth transistor coupled to the third transistor, and a fifth transistor coupled in series with the fourth transistor, wherein the third transistor provides a current through the differential pair that is proportional to a current through the fourth transistor, and a control input of the fourth transistor is coupled between the fifth transistor and a source of current; and a bias voltage generator circuit that generates a bias voltage to be substantially equal to a common mode voltage of the first and the second input voltages, wherein the bias voltage is provided to a control input of the fifth transistor, and wherein the bias voltage generator circuit comprises a resistor divider circuit that receives the first and the second input voltages and that generates the bias voltage based on the first and the second input voltages.