Patent ID: 7939405

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an inter-layer insulating film; arranging a plurality of grooves in a surface layer of the inter-layer insulating film; forming embedded insulating films which are embedded in the grooves; arranging a plurality of holes in the inter-layer insulating film and between the embedded insulating films, in a manner such that each hole between the embedded insulating films partially overlaps therewith; forming lower electrodes, each of which has a bottom and a side face, and covers the bottom and side faces of the corresponding hole; forming a capacitance insulating film which covers the lower electrodes; and forming an upper electrode which further covers the capacitance insulating film, wherein the formation of the holes includes: forming a resist pattern on the inter-layer insulating film in which the embedded insulating films are formed, where the resist pattern has openings corresponding to the holes; etching the inter-layer insulating film and the embedded insulating films, which are exposed through the openings, by a first anisotropic etching which uses the resist pattern as a mask; further etching the exposed inter-layer insulating film by a second anisotropic etching after the etching of the exposed embedded insulating films is completed, where the second anisotropic etching has a higher etching rate for the inter-layer insulating film in comparison with the first anisotropic etching; and removing the resist pattern after the etching of the exposed inter-layer insulating film is completed.