Patent ID: 6999413

Claim:
A packet switch comprising: a plurality of line interfaces each connectable to an input line and an output line; and a back panel capable of mounting n number of crossbar switches each connected to said plurality of line interfaces, wherein each of said plurality of line interfaces includes input queue buffers as many as said plurality of line interfaces, a block distributor, and a read controller for reading input packets buffered in said plurality of input buffers, in fixed length block units at cyclic time slots allocated to said n number of crossbar switches, and for sending read blocks to said distributor, wherein n number of crossbar switches are mounted on said back panel, said read controller reads n number of blocks from one input queue buffer selected out of said plurality of input buffers at time slots corresponding to said n number of crossbar switches, and sends said blocks to said block distributor, wherein said block distributor outputs said n number of blocks to said n number of crossbar switches, wherein when k number of crossbar switches out of said n number of crossbar switches are unused or faults occur in said k number of crossbar switches, said read controller reads n minus k number of blocks from one selected input queue buffer out of said plurality of input queue buffers at time slots corresponding to n minus k number of crossbar switches in operation and sends said blocks to said block distributor but does not read blocks at time slots corresponding to said k number of crossbar switches, and wherein said block distributor outputs said n minus k number of blocks to said n minus k number of crossbar switches in operation.