Patent ID: 6930525

Claim:
A memory having a deskewing circuit, comprising: a delay monitor circuit configured to generate a delayed input signal in response to an initial input signal; a measure delay line connected to the delay monitor circuit and configured to receive the delayed input signal and generate a measured delay signal according to the delayed input signal; an intermediate element connected to the measure delay line and configured to receive the measured delay signal; a variable delay line connected to the intermediate element and configured to receive the measured delay signal through said intermediate element; and an operation control circuit connected to at least one of the measure delay line, the intermediate element, and the variable delay line, and configured to detect an entry point in the measured delay signal, comprising: an overflow circuit configured to adjust an overflow signal according to a detection of the entry point; and a clock select circuit configured to terminate a clock signal to a selected portion of the at least one of the measure delay line, the intermediate element, and the variable delay line according to the detection of the entry point.