Patent ID: 7522395

Claim:
An electrostatic discharge (ESD)/electrical overstress (EOS) protection circuit electrically coupled to an Integrated Circuit (IC) having a voltage supply and an electrical ground, the protection circuit comprising: a discharging circuit coupled between the voltage supply and the electrical ground; a controller, coupled to the discharging circuit, the voltage supply, and the electrical ground, the controller operable in a normal operating condition or in an electrical overstress (EOS) situation to cause the discharging circuit to discharge any excess voltage above a safety voltage level, from the voltage supply to the electrical ground and the controller, upon the occurrence of an electrostatic discharge (ESD) event, to cause the discharging circuit to discharge the excess voltage above a second voltage level, from the voltage supply to the electrical ground, wherein the second voltage level is less than the safety voltage level; and a detection circuitry coupled to the discharging circuit, to the controller and to a voltage source, the detection circuitry providing an output voltage to the controller that rises with respect to a rising voltage on the voltage supply during a power-on of the Integrated Circuit (IC), wherein the output voltage rises at a higher rate during the ESD event than during the normal operating condition or the electrical overstress (EOS) situation in the Integrated Circuit (IC) and wherein the output voltage has a first detection voltage level associated with the normal operating condition or the electrical overstress (EOS) situation and a second detection voltage level associated with the electrostatic discharge (ESD) event, and wherein the detection circuitry further comprises an NMOS transistor having a gate, a drain and a source wherein the gate of the NMOS transistor electrically coupled to a first terminal of a first resistor, a second terminal of the first resistor electrically coupled to the voltage source, the drain of the NMOS transistor electrically coupled to a first terminal of a second resistor, a second terminal of the second resistor forming the output voltage and electrically coupled to the controller, the source of the NMOS transistor electrically coupled to the electrical ground, the gate of the NMOS transistor electrically coupled to a first terminal of a capacitor, a second terminal of the capacitor electrically coupled to the electrical ground.