Patent ID: 8572351

Claim:
A memory device, comprising: a physical memory plane comprising m first physical lines extending along a first direction and n second physical lines extending along a second direction; reception means for receiving a logical address designating a first logical line and a second logical line of a matrix logical memory plane, the matrix logical memory plane possessing 2 p first logical lines extending along the first direction and 2 q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2 k , k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2 p+q ; and means for addressing the physical memory plane configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical address received by m/2 k .