Patent ID: 8753960

Claim:
A method comprising: forming a first semiconductor device in a first semiconductor die region on a semiconductor wafer, wherein the first semiconductor device comprises a plurality of terminals; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; forming a protective device on a first region of the semiconductor wafer, wherein the first region of the semiconductor wafer is between (i) the first semiconductor die region and (ii) the second semiconductor die region; forming a first metal line on a surface of the first semiconductor device, such that the plurality of terminals is not in electrical communication with the first metal line; forming a second metal line on a surface of the second semiconductor device; and electrically coupling the protective device to each of (i) the first metal line formed on the surface of the first semiconductor device and (ii) the second metal line formed on the surface of the second semiconductor device, such that the protective device electrically couples the first metal line to a ground terminal when a voltage higher than a threshold voltage is applied to the first metal line.