Patent ID: 7629820

Claim:
A delay circuit, comprising: a controllable delay device configured to generate first and second signals that are phase-shifted with respect to an input signal of the delay device such that at respective first and second output terminals of the controllable delay device, after a delay of the input signal by a delay time, the second phase-shifted signal is an inverted version of the first phase-shifted signal, wherein the controllable delay device comprises: a series circuit of delay elements configured to receive the input signal, wherein each of the delay elements is configured to generate an output signal that is delayed with respect to the input signal by a respective delay time; and a mixer circuit configured to generate the first and second phase-shifted signals, the second phase-shifted signal being the inverted version of the first phase-shifted signal, via the respective output signals of the delay elements; a feedback circuit configured to generate a feedback signal that is phase-shifted with respect to one of the first or second phase-shifted signals selectively supplied to the feedback circuit; a first phase comparison device configured to perform a phase comparison of the input signal of the delay device and the feedback signal; and a control circuit configured to set first and second delay times by which the controllable delay device respectively delays the first and second phase-shifted signals, the first and second delay times depending on the phase comparison performed by the first phase comparison device.