Patent ID: 7056777

Claim:
A manufacturing method for a thin film transistor array substrate, comprising: using a first mask to form gate patterns having a gate electrode, a gate line connected to the gate electrode, and a gate pad connected to the gate line on a substrate; using a second mask to form a gate insulating pattern at an area that covers the gate electrode and gate line of the gate patterns, to form a semiconductor pattern having a same pattern as the gate insulating pattern and partially removed at the gate line, and to form a source/drain pattern having the same pattern as the semiconductor pattern and having a source electrode and a drain electrode of a thin film transistor, a data line connected to the source electrode, and a data pad connected to the data line; and using a third mask to form a transparent electrode pattern having a pixel electrode formed at a pixel area and connected to the drain electrode, a gate pad protective electrode formed on the gate pad, and a data pad protective electrode formed contacting upper and sidewall portions of the data pad.