Patent ID: 7609122

Claim:
A method for calibrating a phase lock loop, the method comprising: receiving a capacitance profile of the phase lock loop for a frequency range and at a process corner; determining a first capacitance for the phase lock loop to operate at a first frequency; determining a second capacitance for the phase lock loop to operate at a second frequency; determining a first capacitance difference from the determined first capacitance to operate at the first frequency and a capacitance corresponding to the first frequency in the received capacitance profile; determining a second capacitance difference from the determined second capacitance to operate at the second frequency and a capacitance corresponding to the second frequency in the received capacitance profile; receiving a frequency selection signal for an operating frequency of the phase lock loop; calculating a difference capacitance corresponding to the operating frequency from the first and second capacitance differences; and determining a capacitance for operating the phase lock loop at the selected operating frequency in response to the capacitance corresponding to the received capacitance profile at the selected frequency and the calculated difference capacitance.