Patent ID: 7068554

Claim:
A memory redundancy control apparatus, comprising: a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address; a dynamic stage configured to receive outputs of said static compare stage, with an output of said dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry, said dynamic stage further triggered by a clock signal thereto; upon activation of said clock signal, said output of said dynamic stage remains precharged whenever a match exists between said requested memory address and said defective memory address, and said output of said dynamic stage is discharged whenever a mismatch exists between said requested memory address and said defective memory address; and a delay tracking clock generator configured to generate a delay tracking clock signal with respect to said dynamic stage, said delay tracking clock signal configured to gate said output of said dynamic stage to spare subarray decoding circuitry, wherein said spare subarray decoding circuitry is activated whenever said output of said dynamic stage remains precharged following activation of said clock signal.