Patent ID: 8423829

Claim:
A failure analysis apparatus comprising: a host machine; first and second microprocessors of an identical configuration, the first microprocessor being a known good device, while the second microprocessor being a target for failure analysis; and first and second debug interface devices connecting the host machine to the first and second microprocessors, respectively, the host machine controlling debugging of the first and second microprocessors, via the first and second debug interface devices, wherein the host machine comprises a unit that causes the first and second microprocessors to execute identical debug operations in parallel, via the first and second debug interface devices, obtains internal information of the first and second microprocessors, via the first and second debug interface devices, and compares the internal information of the first and second microprocessors to perform failure analysis of the second microprocessor, wherein the host machine sets a plurality of break points in respective programs of the first and second microprocessors via the first and second debug interface devices, and in case the internal information obtained from the first and second microprocessors at a first break point matches and the internal information obtained from the first and second microprocessors at a second break point executed by the first and second microprocessors after the first break point does not match, as a subsequent operation, the host machine changes a debug command so that instructions between the first break point and the second break point are executed by step-execution, and supplies the changed debug command to the first and second microprocessors via the first and second debug interface devices.