Patent ID: 8484648

Claim:
A computer-implemented method for managing operating system interference on applications in a parallel processing system, the computer-implemented method comprising: determining a mapping of multi-threading threads to at least one processing core; determining, based on the mapping, first and second sets of logical processors of the at least one processing core, the first set including at least one of the logical processors of the at least one processing core, and the second set including at least one of a remainder of the logical processors of the at least one processing core; storing a set of interference source information identifying a set of interference sources associated with the at least one processing core and a set of application tasks to be operated on the at least one processing core; scheduling, by an operating system being executed by a processor, application tasks only on the logical processors of the first set of logical processors of the at least one processing core based on the set of interference source information; and scheduling, based on the set of interference source information, operating system interference events only on the logical processors of the second set of logical processors of the at least one processing core, wherein operating system interference events comprise at least scheduling of daemon processes by the operating system and handling asynchronous events by the operating system, wherein scheduling operating system interference events comprises: identifying a set of operating system interference sources within the application tasks scheduled on the logical processors of the first set of logical processors, wherein each of the set of operating system interference sources within the application tasks are non-hardware interference sources; determining that at least one of the operating system interference sources is bound to an individual process thread associated with one of the logical processors of the first set of logical processors; and migrating the individual process thread to one of the logical processors of the second set of logical processors.