Patent ID: 8004882

Claim:
An SRAM integrated circuit comprising: an input terminal and an output terminal; a first transistor, said first transistor having a source terminal, a drain terminal, and a gate terminal; a second transistor, said second transistor having a source terminal, a drain terminal, and a gate terminal; a magneto-resistive component (MRC), said MRC having an upper terminal and a lower terminal, wherein the MRC is coupled in series between the first and second transistors, wherein the MRC can be selectively programmed to a state of high resistance or to a state of low resistance; and wherein the source terminal of the first transistor is connected to a voltage source and the drain terminal of the first transistor is connected to the upper terminal of the MRC, wherein the source terminal of the second transistor is connected to a common ground terminal and the drain terminal of the second transistor is connected to the lower terminal of the MRC, wherein the input terminal is connected to the gate terminals of the first and second transistors, and the output terminal is connected to the drain terminal of the first transistor and the upper terminal of the MRC; wherein the MRC is configured to be programmed to the high resistive state when the output terminal is high, and wherein the MRC is configured to be programmed to the low resistance state when the output terminal is low.