Patent ID: 7569888

Claim:
A semiconductor device, comprising: a silicon layer; a first FET that is one of an N-type or a P-type, having a first gate disposed on the silicon layer, the first gate having opposing sidewalls; a second FET that is the other of an N-type or a P-type, having a second gate disposed on the silicon layer, the second gate having opposing sidewalls; a first stress liner disposed over the first FET and providing a first stress type to the first gate; a second stress liner disposed over the second FET and providing a different second stress type to the second gate; a first oxide layer disposed between each of the sidewalls of the first gate and the first stress liner; and a second oxide layer disposed between each of the sidewalls of the second gate and the second stress liner, wherein the first stress liner is approximately parallel to each of the sidewalls of the first gate along an entire length of each of the sidewalls of the first gate, wherein the second stress liner is not parallel to each of the sidewalls of the second gate along an entire length of each of the sidewalls of the second gate, wherein a first surface of each of the first oxide layers facing away from the first gate is in physical contact with the first stress liner over the entirety of the first surface, and wherein a second surface of each of the second oxide layers facing away from the second gate is in physical contact with the second stress liner over only a portion of the second surface.