Patent ID: 8871591

Claim:
A method of manufacturing a semiconductor device comprising: forming cell patterns and insulating interlayers between each of the cell patterns on a substrate, the cell patterns surrounding vertically extruded semiconductor patterns; forming an upper insulating interlayer on an uppermost cell pattern of the cell patterns, the upper insulating interlayer defining initial and preliminary contact holes; forming a first reflection limiting layer pattern and a first photoresist layer pattern on the upper insulating interlayer, the first photoresist layer pattern and the first reflection limiting layer pattern exposing a first preliminary contact hole of the preliminary contact holes at a first position from an edge portion of the upper insulating interlayer, the first photoresist layer pattern and the first reflection limiting layer pattern covering an inlet portion of the initial and preliminary contact holes; performing a first etching process with respect to layers under the first preliminary contact hole to expose a cell pattern at a lower position than a bottom of the first preliminary contact hole; repeating a partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process with respect to exposed layers through bottom portions of the preliminary contact holes one by one, for forming contact holes having decreasing depths from the edge portion to a center portion of the cell patterns; forming an insulating spacer on sidewalls of the contact holes; and filling up inner portions of the contact holes including the insulating spacer with a conductive material to form contacts.