Patent ID: 7697333

Claim:
A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising: a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array, and applies signal voltages to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array for selecting the blocks; and a sense amplifier that is controlled by a column decoder and makes a selection from the bit lines of the memory cell array, wherein, in a block that is not selected by the row decoder, a first bit line that is selected by the sense amplifier is charged when the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a second bit line that is not selected by the sense amplifier are in a floating state.