Patent ID: 8685800

Claim:
A method of addressing single-event latch-up in a semiconductor device, comprising: determining a location of a parasitic silicon-controlled rectifier in an integrated circuit design of the semiconductor device, wherein the parasitic silicon-controlled rectifier includes a parasitic pnp bipolar junction transistor and a parasitic npn bipolar junction transistor; incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp bipolar junction transistor in the integrated circuit design, wherein the first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp bipolar junction transistor, and a control terminal, and wherein the first transistor is not positioned between a base of the pnp bipolar junction transistor and the first power supply node, where the first transistor limits current conducted by the parasitic pnp bipolar junction transistor following a single-event latch-up (SEL); and incorporating a second transistor between a second power supply node and an emitter of the parasitic npn bipolar junction transistor in the integrated circuit design, wherein the second transistor includes a first terminal coupled to the second power supply node, a second terminal coupled to the emitter of the parasitic npn bipolar junction transistor, and a control terminal, and wherein the control terminal of the first transistor is coupled to the emitter of the parasitic npn bipolar junction transistor and the control terminal of the second transistor is coupled to the emitter of the parasitic pnp bipolar junction transistor, where the second transistor is not positioned between a base of the npn bipolar junction transistor and the second power supply node.