Patent ID: 8854853

Claim:
A three-dimensional integrated circuit (3-D IC), comprising: a controller chip, comprising a control circuit, wherein the control circuit has at least one setting fuse; and a memory chip, comprising an address translation circuit with an external activation/enablement function, wherein the address translation circuit has at least one activating/enabling fuse, wherein after the controller chip and the memory chip are stacked, the controller chip, in response to the setting of the control circuit and a preset condition associated with the address translation circuit capable of external activation/enablement, controls the address translation circuit in the memory chip through at least one vertical interconnect to activate/enable at least one spare in the memory chip to repair at least one damaged memory cell in the memory chip, wherein in case that the activating/enabling fuse is already blown, the at least one spare in the memory chip is capable of being activated or enabled by blowing the at least one setting fuse.