Patent ID: 7732872

Claim:
A semiconductor structure comprising a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack, each located on a semiconductor substrate, wherein said second gate stack constitutes a gate of a p-type field effect transistor and said fourth gate stack constitutes a gate of an n-type field effect transistor, wherein said first gate stack comprises: a first high dielectric constant (high-k) material portion located on a first semiconductor portion of said semiconductor substrate; a metal oxide portion vertically contacting said first high-k material portion and comprising a different material than said high-k material; and a first conductive metal nitride portion vertically contacting said metal oxide portion and comprising a conductive metal nitride; wherein said second gate stack comprises: a second high dielectric constant (high-k) material portion located on a second semiconductor portion of said semiconductor substrate; and a second conductive metal nitride portion vertically contacting said second high-k material portion and comprising said conductive metal nitride; wherein said third gate stack comprises: a semiconductor oxide based gate dielectric portion located on a third semiconductor portion of said semiconductor substrate and comprising a semiconductor oxide or a semiconductor oxynitride; wherein said fourth gate stack comprises: a third high dielectric constant (high-k) material portion located on a fourth semiconductor portion of said semiconductor substrate; and a third conductive metal nitride portion vertically contacting said third high-k material portion and comprising said conductive metal nitride; and wherein said first, second, and third high-k material portions are composed of a high-k material having a same composition and a dielectric constant greater than 4.0, and said conductive metal nitride has a same composition in said first, second, and fourth gate stacks.