Patent ID: 8145986

Claim:
An apparatus, comprising: a CSI (Cyclic Shifted Identity) circuitry that is operative to identify a CSI parameter set; a LDPC (Low Density Parity Check) matrix generation circuitry, coupled to the CSI circuitry, that is operative to employ the CSI parameter set to generate an LDPC matrix; and a decoder circuitry that is operative to employ the LDPC matrix to decode an LDPC coded signal thereby generating an estimate of an information bit encoded therein; and wherein: the CSI parameter set includes a plurality of entries such that each entry corresponds to a sub-matrix location within the LDPC matrix; at least one of the plurality of entries is a dual-valued entry; for the dual-valued entry, the LDPC matrix generation circuitry is operative to: generate a first preliminary CSI sub-matrix having a cyclic shift corresponding to a first portion of the dual-valued entry; generate a second preliminary CSI sub-matrix having a cyclic shift corresponding to a second portion of the dual-valued entry; and process the first preliminary CSI sub-matrix and the second preliminary CSI sub-matrix thereby generating a resultant CSI sub-matrix for a corresponding location within the LDPC matrix as determined by a location of the dual-valued entry within the CSI parameter set.