Patent ID: 7428184

Claim:
A circuit arrangement for generating an n-bit output pointer in a semiconductor memory, comprising: at least one m-bit interface for accepting an m-bit reference signal which comprises an information regarding a read latency to be adjusted utilizing an output pointer to be generated by said circuit arrangement; at least one m-bit binary counter comprising a counter output and providing an m-bit counter reading signal comprising a current counter reading at said counter output; a decoder arrangement which is connected downstream of said binary counter, comprising a decoder output, and a plurality of decoder devices each comparing said current counter reading signal with a reference value which is associated with a respective of said decoder devices; each of said decoder devices providing one bit of said output pointer at said decoder output on the basis of said comparing; and n outputs for providing said n bits with said output pointer; and wherein the at least one m-bit interface comprises a plurality of m-bit interfaces, each injecting an m-bit reference signal; each of said reference signals comprising a different binary reference value, said decoder devices being arranged next to one another in such a manner that said reference values are supplied to said decoder devices in ascending or descending order.