Patent ID: 7456478

Claim:
A MOS transistor circuit used in a semiconductor integrated circuit, comprising: a first MOS semiconductor element of a first conductivity type; a substrate bias circuit comprised of a resistor element and a second MOS semiconductor element of a second conductivity type; wherein a source of the first MOS semiconductor element is connected to a first source of a first voltage, an input signal is input to a gate of the first MOS semiconductor element; the resistor element is connected between the first source and a common connection point between a substrate of the first MOS semiconductor element and a drain of the second MOS semiconductor element; a gate of the second MOS semiconductor element is connected to a first source of a second voltage; a source of the second MOS semiconductor element is connected to a second source of the second voltage; and a level fluctuation of the second source of the second voltage is smaller than that of the first source of the second voltage.