Patent ID: 7445971

Claim:
A method for manufacturing a thin-film transistor formed by forming a source electrode and a drain electrode on adjacent convex portions of a concavoconvex surface of a substrate with a concavoconvex surface, and laminating a gate electrode, a gate insulating film and a semiconductor channel layer in this order on a bottom surface of a concave area between the convex portions, comprising: (1) preparing a substrate and a concavoconvex surface forming substrate on which a concavoconvex pattern is formed; (2) after sandwiching a curing resin composition by the two substrates, curing the composition and demolding the concavoconvex surface forming substrate to form a substrate with a concavoconvex surface; (3) after forming a conductive thin film over the entire surface of the concavoconvex surface, further forming a positive type resist film thereon so that the concavoconvex surface is flattened; (4) exposing and developing the resist film by using a mask having the same concavoconvex pattern as the concavoconvex surface forming substrate, to bare the conductive thin film on the top surfaces of the convex portions; (5) forming an impurity containing amorphous silicon thin film over the entire surface that has been bared; (6) removing the resist film and the impurity containing amorphous silicon thin film remaining in the concave areas by exposing and developing from the front side of the substrate; (7) etching the bared conductive thin film; (8) forming an amorphous silicon thin film over the entire surface of the substrate after the etching; (9) carrying out a laser annealing process to form a semiconductor channel layer formed of polysilicon, as well as crystallizing the impurity containing amorphous silicon thin film on the top surfaces of the convex portion to form a source side diffusion layer and a drain side diffusion layer formed of low resistance polysilicon; (10) forming a gate insulating film on the semiconductor channel layer, the source side diffusion layer and the drain side diffusion layer; and (11) forming a gate electrode on the gate insulating film of the upper portion of the semiconductor channel layer.