Patent ID: 7209008

Claim:
A phase-locked loop (PLL), utilizing a single voltage controlled oscillator (VCO), where the PLL is configured to lock multiple internal clocks to multiple incoming data signals of different frequencies, the PLL comprising: a base module generating N signals of same frequency and different phases, the base module further comprising: a base oscillator for generating a base frequency; a frequency/phase comparator for comparing phase and frequency of two input signals and generating an output signal proportional to differences of the input two signals; a voltage controlled oscillator (VCO) for generating N signals with a same frequency and differing phases, wherein the generated frequency is controlled by an output of the frequency/phase comparator; and a programmable divider for dividing a frequency of an input signal, based on a control number provided to the divider, wherein the divider receives K of the N controlled frequency signals; and at least one synchronizing module for locking an internal clock frequency to an incoming signal frequency, the synchronizing module including: a phase shifter for shifting shifter inputs and providing a shifted phase output at a shifter output, wherein the shifter receives N controlled frequency signals from the base module as input signals, and receives a control signals from a digital frequency/phase comparator (DPC); a programmable divider configured to divide an input frequency received from the phase shifter, using a provided control number, and output the divided frequency; and a digital frequency/phase comparator (DPC) for comparing the programmable divider output with an incoming signal and for generating control signals based on frequency and phase differences of the two compared signals, wherein the control signals are used to control the phase shifter; wherein the phase shifter makes a phase-shift selection every Q cycles, which causes an output frequency of the phase shifter to be controllably off with respect to the VCO output freguency, and wherein: Q may change for every selection: a positive or a negative frequency offset is controlled by the shifting direction; and a large Q makes a freguency difference between the VCO output frequency and the shifter output frequency correspondingly small.