Patent ID: 7839693

Claim:
A method of fabricating a CMOS non-volatile memory cell, comprising: providing a CMOS substrate with a device well and a gate oxide layer; forming a first poly gate and a second poly gate over the gate oxide layer of the device well so as to form a gap having a selected width between the first poly gate and the second poly gate; covering the gap with photoresist; implanting a source region and a drain region in the device well; and removing the photoresist from the gap, after the step of removing the photoresist, thermally growing a silicon oxide isolating layer on the first poly gate and on the second poly gate within the gap, and a first sidewall isolating layer on the first poly gate and a second sidewall isolating layer on the second poly gate; and depositing a silicon nitride layer that forms a lateral programming layer between the first poly gate and the second poly gate, and that forms a first sidewall spacer on the first sidewall isolating layer and a second sidewall spacer on the second sidewall isolating layer.