Patent ID: 8901750

Claim:
A semiconductor package comprising: a packaging substrate including a plurality of terminals on the packaging substrate, the plurality of terminals including, a first group of terminals configured to receive respective channel lines of a first channel from a controller, wherein the first group of terminals includes a chip enable terminal configured to receive a chip enable channel line of the first channel from the controller, and a second group of terminals configured to receive respective channel lines of a second channel from the controller; a first semiconductor chip group on the packaging substrate, wherein the first semiconductor chip group includes a first plurality of semiconductor chips electrically connected to terminals of the first group of terminals; a second semiconductor chip group on the packaging substrate, wherein the second semiconductor chip group includes a second plurality of semiconductor chips electrically connected to terminals of the second group of terminals; and a chip enable signal line providing electrical connection between the chip enable terminal and first and second semiconductor chips of the first plurality of semiconductor chips.