Patent ID: 7653060

Claim:
A device, comprising: a first circuit configured to transmit each of a plurality of packets to a destination according to a protocol which defines a perishable bit within packets; a storage element configured to store transmitted packets in which said perishable bit is not asserted until said device receives confirmation from said destination that said transmitted packets have been successfully received, and wherein the storage element is configured to not store transmitted packets in which said perishable bit is asserted; a second circuit coupled to said storage element and configured to retransmit one or more packets from said storage element to said destination in response to receiving an indication that a particular packet of said transmitted packets that is within said storage element was not correctly received by said destination; and a third circuit configured to sequentially renumber a sequence number of packets retransmitted after the particular packet, wherein the packets retransmitted after the particular packet are renumbered beginning with a next higher sequence number than the sequence number of the particular packet.