Patent ID: 7370249

Claim:
An apparatus comprising: a memory array; first testing logic to test a portion of the memory array, wherein the first testing logic is able to issue a first testing operation programmed into the first testing logic to the memory array before receipt of a subsequent testing operation in the first testing logic that has a dependency upon the first testing operation, the first testing logic including a plurality of sets of registers, each set including a command register to store access commands and an inner counter register to store a number of times the command register is to be accessed consecutively to enable the first testing logic to issue the same access command consecutively, wherein the first testing operation and the subsequent testing operation each correspond to a programming module of a sequence of programming modules; second testing logic to test the portion of the memory array; a multiplexer to select the first testing logic or the second testing logic to issue testing operations to the memory array; the first testing logic further including an outer counter register to store a count of how many programming modules are in the sequence of programming modules to be executed by the first testing logic.