Patent ID: 8482985

Claim:
A nonvolatile semiconductor storage device comprising: a cell array including a plurality of first wirings, a second wiring, and a plurality of memory cells selected by the first wirings and the second wiring; and an erase circuit executing an erase sequence to erase data of the memory cells, in the erase sequence, the erase circuit executing: an erase operation to change, to an erased state, a selection memory cell group including a plurality of memory cells selected by the plurality of first wirings; after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state; after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group, i.e., a portion of the selection memory cell group, and a second partial selection memory cell group, i.e., the other portion thereof, so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value; and after the first soft program verification operation, a second soft program verification operation to confirm that the threshold values of the memory cells in the selection memory cell group are less than a predetermined second threshold value that is higher than the first threshold value.