Patent ID: 8890987

Claim:
A device having amplification and noise reduction capabilities, comprising: an amplifier that comprises a first input, a second input and an output; an input circuit that is coupled to an input of the amplifier out of the first input and the second input; wherein the input circuit comprises: a first sampling circuit that is arranged to sample a first signal (S 1 ) during a first phase of operation and during a noise integration period; a second sampling circuit that is arranged to sample a second signal (S 2 ) during a first phase of operation; and a third sampling circuit arranged to sample a third signal (S 3 ) during a second phase of operation; an error capacitor that is coupled to the output of the amplifier; wherein the error capacitor is arranged to be charged by the amplifier, during the noise integration period, to an error voltage that is indicative of noise generated as a result of a sampling of the first and second signals; and a feedback circuit coupled between the error capacitor and the second input of amplifier; wherein the feedback circuit is arranged to provide to the second input of the amplifier and in proximity to a beginning of the second phase of operation, a feedback signal that represents the error voltage and thereby at least partially compensate for the noise.