Patent ID: 7623375

Claim:
A method of operating a flash memory device including a plurality of memory blocks having a plurality of memory cells, wherein each of the plurality of memory cells includes first to N th column lines and first to M th word lines, each column line includes even and odd bit lines, and each word line includes L pages, the method comprising: selecting the memory cells to be operated by sequentially selecting the first to M th word lines, wherein after an even bit line of a first page of each selected word line is selected, the column lines are sequentially increased from a first column line to an N th column line, and after an odd bit line of the first page of the selected word line is selected, the column lines are sequentially increased from the first column line to the N th column line; selecting the memory cells to be operated by sequentially selecting the first to M th word lines, wherein after an even bit line of a second page of each selected word line is selected, the column lines are sequentially increased from the first column line to the N th column line, and after an odd bit line of the second page of the selected word line is selected, the column lines are sequentially increased from the first column line to the N th column line; and selecting the memory cells to be operated by sequentially selecting first to M th word lines, wherein after an even bit line of an L page of each selected word line is selected, the column lines are sequentially increased from the first column line to the N th column line, and after an odd bit line of the L page of the selected word line is selected, the column lines are sequentially increased from the first column line to the N th column line.