Patent ID: 8891257

Claim:
A drive circuit configured to receive a first and a second pulsed input signal, the first and second input signals being opposite each other and with a dead band between them, and to provide a first and a second drive output signal, the drive circuit comprising: a transformer having a primary winding configured to receive the first and second pulsed input signals and a secondary winding configured to output a first and a second intermediary signal corresponding to the first and second pulsed input signals; time delay circuitry configured to receive the first and second intermediary signals from the secondary winding, the time delay circuitry being configured to provide a first and a second buffer input signal, corresponding to the first and second intermediary signal, but with a ramped up transition from a low to a high signal; and a first and a second buffer stage having a first and a second signal output, respectively, the first and second buffer stages being configured to receive the first and second buffer input signals, respectively, and produce the first and the second drive output signals corresponding to the first and second pulsed input signals, wherein: an initiation of the first and second pulsed input signals is configured to produce an initiation of the first and second drive output signals, respectively, with substantially a same timing; and a termination of the first and second pulsed input signals is configured to produce a termination of the first and second drive output signals, respectively, with a delay.