Patent ID: 8404531

Claim:
A method for fabricating a power transistor, comprising: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part that is not diffused with the second electrical type carriers and that has the first electrical type, and a second part that is diffused with the second electrical type carriers, that has a second electrical type, and that adjoins the trench and separates the first part from the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion so as to forma source region having the first electrical type, and a well region contacting the source region and having the second electrical type; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.