Patent ID: 8530955

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array part; a first contact part arranged with the memory cell array part in a first plane; a peripheral circuit part arranged with the memory cell array part in the first plane; and a peripheral circuit, the memory cell array part including: a first stacked body including a plurality of first electrode films stacked along a first axis perpendicular to the first plane, and a first inter-electrode insulating film provided between the two first electrode films being adjacent along the first axis; a first semiconductor layer opposed to side faces of the plurality of first electrode films; and a memory film provided between the plurality of first electrode films and the first semiconductor layer, and the first contact part including: a first contact part insulating layer including a first contact part insulating film and a first particle dispersed in the first contact part insulating film; and a plurality of first contact electrodes penetrating the first contact part insulating layer along the first axis, each of the plurality of first contact electrodes being connected to each of the plurality of first electrode films, and the peripheral circuit part including: a structure body; a peripheral circuit part insulating layer buried in the structure body and extending along the first axis; and a peripheral circuit part contact electrode penetrating the peripheral circuit part insulating layer along the first axis, and electrically connected to the peripheral circuit, and a width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer being smaller than a diameter of the first particle.