Patent ID: 8633069

Claim:
A manufacturing method for an array substrate, comprising: Step 1, sequentially forming a gate metal film, a gate insulating layer and an active layer film on a first base substrate; Step 2, applying a layer of photoresist on the active layer film, and exposing and developing the photoresist by a double tone mask so as to form a photoresist-completely-remained region, a photoresist-partially-remained region and a photoresist-completely-removed region, the photoresist-completely-remained region corresponding to a region for a gate electrode and an active layer, the photoresist-partially-remained region corresponding to a region for a gate line and a common electrode line, and the photoresist-completely-removed region corresponds to other regions on the array substrate; Step 3, performing a first etching on the gate metal film, the gate insulating layer and the active layer film corresponding to the photoresist-completely-removed region, so as to form the gate electrode and the active layer; Step 4, ashing to remove the photoresist in the photoresist-partially-remained region and remain a part of the photoresist with a certain thickness in the photoresist-completely-remained region, performing a second etching on the gate insulating layer and the active layer film in the photoresist-partially-remained region so as to form the gate line and the common electrode line; Step 5, forming a first insulating layer film on the first base substrate after Step 4; Step 6, lifting off the photoresist in the photoresist-completely-remained region and the first insulating layer film thereon; Step 7, forming a first conductive film on the first insulating layer film and the active layer, and patterning the first conductive film by a patterning process so as to from a source electrode, a drain electrode, a data line, a pixel electrode and an active layer channel; and Step 8, forming a passivation layer on the base substrate after the Step 7.