Patent ID: 7188290

Claim:
An apparatus comprising: an input buffer to receive a serial sequence of data bits from an optical network; a serial-to-parallel converter to convert the serial sequence of data bits into a sequence of un-aligned data words; a double-word generator to receive the sequence of un-aligned data words and generate a sequence of double-words, each double-word including two consecutive un-aligned data words; comparators to compare segments of the double-words to a predefined bit pattern, each comparator to generate a comparison signal having a first logic state when there is a match between a segment and the predefined bit pattern and a second logic state when there is no match; and a shift register having inputs and a carry-out output, each input to receive one of the comparison signals, the shift register to perform shift operations to shift the comparison signals at the inputs until the first logic state is present at the carry-out output.