Patent ID: 8084321

Claim:
A method of manufacturing a dynamic random access memory (DRAM) cell, comprising the steps of: providing a semiconductor substrate with a first electrode; forming a first dielectric layer and a first conductive layer on the substrate; patterning the first dielectric layer and the first conductive layer to from a gate structure and a first capacitor structure; forming a source region and a drain region laterally adjacent to the gate structure in the substrate; forming a second dielectric layer over the gate structure, the first capacitor structure and the substrate; etching the second dielectric layer to expose the drain region between the gate structure and the first capacitor structure; forming a second conductive layer over the gate structure, the first capacitor structure, the source region and the drain region; patterning the second conductive layer and the second dielectric layer exposing at least a portion of the gate structure, the source region and a portion of the first capacitor structure to from a second capacitor structure electrically connected to the drain region, wherein a remaining portion of the second conductive layer overlaps another portion of the gate structure; and forming a salicide layer overlaying exposed regions of the source region, the gate structure, the second capacitor structure, and the first capacitor structure.