Patent ID: 8209445

Claim:
A computer system, comprising: a central processing unit (“CPU”) that outputs instructions; a system controller coupled to the CPU, the system controller having an input port that receives instructions from the CPU and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each memory module comprising: a plurality of memory devices wherein the memory module provides a data structure comprising command blocks that provide information for data transfer operations; and a memory hub, comprising: a link interface coupled to receive memory requests for access to at least one of the memory devices of the memory module on which the link interface is located; at least one memory device interface, each of the at least one memory device interface having a memory controller and coupled to a respective number of the memory devices and coupling memory requests to the respective number of the memory devices for access to at least one of the memory devices, one of the at least one memory device interface operable to at least provide and receive signals specific to the respective number of the memory devices; a switch for selectively coupling the link interface and the memory device interface; an I/O register operable to store status information indicative of completion of a direct memory success (DMA) operation and error status of the DMA operation; and a direct memory access (DMA) engine coupled through the switch to the memory device interface and the link interface, the DMA engine operable to generate memory requests for accessing at least one of the memory devices of the plurality of memory modules to perform DMA operations and further operable to program status information in the I/O register upon completion of the DMA operations; and a communications link coupled between the system controller and the plurality of memory modules for coupling memory requests and data between the system controller and the memory modules.