Patent ID: 7379467

Claim:
An apparatus, comprising: a data extraction block; a plurality of data assemblers coupled to the data extraction block; and a scheduler coupled to the plurality of data assemblers, wherein the scheduler is configured to operate with a scheduling policy comprising a set of priorities to determine an order of data writes to an output memory coupled to the scheduler from the plurality of data assemblers, including selecting one or more of the plurality of data assemblers having a fill level greater than twice an input data path width of an input data bus and having no end-of-packet (EOP) or start-of-packet (SOP) as a first priority, selecting one or more of the plurality of data assemblers having a fill level greater than twice the input data path width of the input data bus and not covered in the first priority selection as a second priority, selecting one or more of the plurality of data assemblers having a fill level greater than the input data path width of the input data bus and not covered in the first and second priority selections as a third priority, and selecting one or more of the plurality of data assemblers having an end-of-packet (EOP) as a fourth priority.