Patent ID: 8329541

Claim:
A method of fabricating a transistor, the method comprising: providing a crystalline substrate having a first lattice constant substantially different from a lattice constant of InP; providing a non-crystalline mask above the substrate, the mask including an opening having sidewalls that extend above the substrate by a height; providing within the opening a crystalline buffer layer having a second lattice constant substantially lattice-matched to InP, the buffer layer having a height less than the mask opening sidewall height, the buffer layer height being sufficient to permit defects arising from the lattice mismatch to exit the buffer layer at the mask opening sidewalls; providing a channel layer above the buffer layer, a portion of the channel layer being lower than a top surface of the mask, the channel layer comprising a crystalline material, the crystalline material comprising an InP-based material; defining a source region, a drain region, and a channel region of a transistor in the channel layer; and providing a gate above the channel layer.