Patent ID: 7390716

Claim:
A method of manufacturing a flash memory device, the method comprising: forming a floating gate pattern in which a tunnel oxide layer and a first conductive layer are laminated in a first region of a semiconductor substrate, and forming isolation layers in a second region of the semiconductor substrate; etching the isolation layers to a predetermined thickness by a dry etch process, thus forming first spacers on sidewalls of the floating gate pattern using a polymer generated while the isolation layers are etched; and forming a dielectric layer, a second conductive layer, and a hard mask layer on the entire surface, patterning the hard mask layer, the second conductive layer, and the dielectric layer to form a control gate, and etching the floating gate pattern using the control gate as a mask, forming a floating gate, wherein while the floating gate pattern is etched to expose the semiconductor substrate, a second spacer is formed on lateral faces of the semiconductor substrate as some of the isolation layers are etched.