Patent ID: 7973400

Claim:
A semiconductor package, comprising: one or more semiconductor chips arranged in a stack structure; one or more substrates including the one or more semiconductor chips respectively attached thereto; a plurality of solder balls arranged to provide voltages and signals to the one or more semiconductor chips, wherein at least a first solder ball of the plurality of solder balls is attached to an upper positioned substrate of the one or more substrates; a heat sink positioned to spread heat produced in the interior of the package to the outside, the heat sink directly connected to at least the first solder ball of the plurality of solder balls, wherein and an upper positioned chip of the one or more semiconductor chips is positioned between the upper positioned substrate and the heat sink; and an insulating layer positioned between the upper positioned substrate and the heat sink and attached to the heat sink, wherein the insulating layer includes at least a first hole through which the first solder ball connects to the heat sink, wherein at least a second solder ball of the plurality of solder balls is attached to the upper positioned substrate, and wherein the insulating layer positioned between the upper positioned substrate and the heat sink blocks the second solder ball from electrically connecting to the heat sink.