Patent ID: 6888215

Claim:
An interconnect structure in which an anti-fuse dielectric is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse dielectric layer formed on said substrate, wherein said patterned anti-fuse dielectric layer includes an opening to at least one of said first level of electrically conductive features; a patterned interlevel dielectric material formed on said patterned anti-fuse dielectric layer, wherein said patterned interlevel dielectric includes vias, at least one of said vias has a via space formed above said opening and at least one other of said vias exposes a portion of said anti-fuse layer to define an anti-fuse location; and a second level of electrically conductive features formed in said vias and via space(s) where the electrically conductive feature of said second level at said at least one of said vias forms an electrical interconnect between said first and second levels of electrically conductive features and where the electrically conductive feature of said second level at said at least one other of said vias defines an anti-fuse between said first and second levels with said exposed portion of said antifuse layer.