Patent ID: 7877576

Claim:
An information processing apparatus that comprises a CPU that sequentially decodes and executes instructions included in an instruction sequence to perform calculations, and a coprocessor that is connected with the CPU via a first bus and a second bus, includes one or more registers for storing therein data relating to the calculations, decodes any of the instructions that is being decoded by the CPU in parallel with the CPU, performs a calculation relating to the any of the instructions based on data output from the CPU to the first bus, and outputs a result of the calculation to the second bus, the CPU including an information acquisition unit operable to, if an instruction to be decoded is an acquisition instruction for acquiring data stored in any of the registers, output a piece of register information designating the any of the registers to the first bus, and acquire the data stored in the any of the registers via the second bus, and the coprocessor including: a saving register specification unit operable to, if an instruction to be decoded is the acquisition instruction, acquire the piece of register information via the first bus, and specify, based on the acquired piece of register information, the register from which the data is to be saved; and a data output unit operable to output, to the second bus, the data stored in the register specified by the saving register specification unit.