Patent ID: 6845501

Claim:
An apparatus for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context, the apparatus comprising: a first logic, the first logic being configured to identify at least a first prefetch region in a first memory element during compilation of a computer program by the computer; a second logic, the second logic being configured to identify critical memory references within the first prefetch region during compilation, the critical memory references within the first prefetch region corresponding to data that may be needed in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution by the computer; and a third logic, the third logic being configured to prefetch data associated with the identified critical memory references and to store the prefetched data in cache memory prior to a process or thread associated with the first context is resumed when a switch from the second context to the first context occurs during program execution.