Patent ID: 7194714

Claim:
A method of reducing the magnitude of an overall instantaneous current draw during a timing cycle in a synchronous integrated circuit having a plurality of timing paths each having a late mode margin associated therewith, comprising the steps of: (a) stepping through the plurality of timing paths so as to determine for each one of the plurality of timing paths whether or not the corresponding late mode margin is greater than zero; (b) in response to the corresponding late mode margin being determined to be greater than zero in step (a), adding a delay to the corresponding one of said plurality of timing paths; and (c) in response to the corresponding late mode margin being determined to be greater than zero in step (a), inserting a delay element into the corresponding one of the plurality of timing paths, said delay element configured to induce said delay into the corresponding one of the plurality of timing paths; wherein each one of the plurality of timing paths has a corresponding late mode margin and step (b) includes setting said delay to said corresponding late mode margin minus a fraction of a timing cycle.