Patent ID: 8078835

Claim:
A processor comprising: an array of processing elements arranged to enable a floating-point operation, each processing element including an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values, and the processing elements in the array being connected together in groups of two or more processing elements to enable floating-point operation, and being connected in a mesh structure to enable data communications among the connected processing elements; and a configuration cache connected to the array to store a context that controls at least one of the integer arithmetic and floating-point arithmetic operations performed by the processing elements in the columns or rows of the array, and the data communications among the processing elements, the processing elements being configured in columns or rows based on the context to form a pipeline, and forwarding a result of a pipeline operation to a direction designated by the context, wherein each of the groups of two or more processing units is configured to perform the integer arithmetic operation or the floating-point arithmetic operation through temporal mapping, receive the context of a control signal so as to perform a multi-cycle operation, and receive a next context after final values are through all cycles obtained.