Patent ID: 7982518

Claim:
A timing circuit for generating asynchronous signals, the timing circuit comprising: a timing control block including: an SR latch that generates a first signal and a second signal, the first and second signals being asynchronous; a first delay block for delaying the first signal, generating a delayed first signal, and providing the delayed first signal to a first input terminal of the SR latch; a second delay block for delaying the second signal, generating a delayed second signal, and providing the delayed second signal to a second input terminal of the SR latch, wherein the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals; and enable/disable circuitry including: a first logic gate; and a state machine that generates a disable signal, the disable signal and a clock signal being provided to input terminals of the first logic gate, an output of the first logic gate being provided to a set of input terminals of the timing control block.