Patent ID: 8564041

Claim:
A memory device, comprising: a substrate; a memory cell formed on the substrate, the memory cell comprising: a first dielectric layer formed on the substrate, a charge storage layer formed on the first dielectric layer, a second dielectric layer formed on the charge storage layer, and a control gate electrode formed on the second dielectric layer, the control gate electrode including polycrystalline silicon; a source region formed in the substrate; a drain region formed in the substrate; first spacers formed adjacent to the memory cell, each of the first spacers being formed on one of opposite sides of the memory cell, each of the first spacers including silicon oxynitride and substantially directly contacting the substrate, a top surface of each of the first spacers being substantially co-planar with a top surface of the control gate electrode; an interlayer dielectric layer formed over the memory cell and the first spacers, the interlayer dielectric layer including a boro-phosphosilicate glass (BPSG) material or a phosphosilicate glass (PSG) material and substantially contacting: the first spacers including the silicon oxynitride, and the top surface of the control gate electrode; a contact hole formed in the interlayer dielectric layer, a selected first spacer, of the first spacers, forming a portion of a wall defining the contact hole; a second spacer formed adjacent to the selected first spacer and on the wall defining the contact hole, a height of the second spacer being greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer, the first spacers and the second spacer being formed over the source region or the drain region; and a contact formed in the contact hole, the second spacer preventing charge leakage between: the contact, and the charge storage layer and the control gate electrode; and a conductive interconnect line formed over the interlayer dielectric layer and the contact.