Patent ID: 7582550

Claim:
A method of manufacturing a semiconductor memory device having a memory cell region where a memory cell transistor is formed and a peripheral circuit region where a peripheral circuit controlling an operation of said memory cell transistor is formed, comprising the steps of: defining an active region by selectively forming an isolation region on a main surface of a semiconductor substrate; forming a first insulating film on said active region; forming a first conductive film on said first insulating film; forming an opening in a region serving as a first impurity region that can serve as a source region by patterning said first conductive film, and simultaneously patterning a recessed portion on opposing end portions in a longitudinal direction of said opening in said memory cell region; introducing an impurity into the main surface of said semiconductor substrate, using a conductive film pattern in said memory cell region as a mask; forming a second insulating film capable of accumulating charges, that covers said conductive film pattern and includes a first silicon oxide film, a silicon nitride film and a second silicon oxide film; forming a second conductive film on said second insulating film; simultaneously forming sidewall-shaped memory gate electrodes of two memory cell transistors on a side surface of the opening in said conductive film pattern by etching said second conductive film, in said memory cell region; forming a first impurity region, using said conductive film pattern and two said memory gate electrodes as a mask, in said memory cell region; forming a continuous control gate electrode surrounding said first impurity region by etching a region where a second impurity region serving as a drain region is located in a pattern of said first conductive film, in said memory cell region; and forming said second impurity region by introducing an impurity into said main surface of said semiconductor substrate, and a first memory gate electrode and a second memory gate electrode of said two memory cell transistors extending to an edge portion of the memory cell region and connected to each other.