Patent ID: 7394142

Claim:
A system comprising: a processor; a memory sub-system operatively coupled to the processor, the memory sub-system comprising at least one memory device, the at least one memory device comprising: a voltage clamp having a first diode and a second diode coupled in series, wherein the first diode and the second diode comprise: a substrate having a doped region found in a bulk region of the substrate; a dielectric layer disposed over the doped region of the substrate, the dielectric layer having a first contact hole and a second contact hole; a first polysilicon plug disposed in the first contact hole; a second polysilicon plug disposed in the second contact hole, the second polysilicon plug being doped opposite the first polysilicon plug; a first conductive material disposed in the first contact hole over the first polysilicon plug; a second conductive material disposed in the second contact hole over the second polysilicon plug; a third conductive material coupled to the first conductive material; and a fourth conductive material coupled to the second conductive material; a pad coupled to receive an input signal, the pad being electrically coupled to the voltage clamp; and a circuit electrically coupled to the pad between the first diode and the second diode.