Patent ID: 8161217

Claim:
A method for handling operation of circuitry, comprising: configuring an on-chip programmable device that functions as a master on a first bus, wherein the first bus comprises a second bus and a third bus, wherein the second bus and the third bus are coupled via a bridge, wherein the second bus is a high speed bus and the third bus is a low speed bus, wherein the on-chip programmable device comprises a high-speed second bus interface that interfaces the second bus and a low-speed third bus interface that interfaces the third bus, wherein at least one interface to another device is coupled to the third bus, wherein the on-chip programmable device is programmed by a processor via the high-speed second bus interface, the processor directly accessing the second bus, the on-chip programmable device directly accessing the second bus and directly accessing the third bus; controlling the another device coupled to the at least one interface via at least one signal generated by the on-chip programmable device; and communicating the at least one generated signal via the third bus to the at least one interface when the on-chip programmable device receives an input timer signal, wherein the input timer signal includes a count that correlates to a number of wideband code division multiple access (WCDMA) chip periods.