Patent ID: 8493700

Claim:
An ESD protection arrangement for a high-voltage I/O pad, comprising: a high-voltage NMOS transistor coupled between said high-voltage I/O pad and a low-voltage terminal, said high-voltage NMOS transistor having a parasitic component between a source and a drain thereof; and a trigger coupled to said high-voltage I/O pad and said parasitic component, to monitor the voltage on said high-voltage I/O pad in order to trigger said parasitic component when the voltage on said high-voltage I/O pad raises above a threshold value during an ESD event, so as to release an ESD current therethrough from said high-voltage I/O pad to said low-voltage terminal; and a controller coupled to said high-voltage NMOS transistor to apply a control signal thereto, to switch said high-voltage NMOS transistor in order for said high-voltage I/O pad to have an open-drain output capability.