Patent ID: 7924085

Claim:
A circuit, comprising: a first node adapted to receive a signal; a second node adapted to output the signal; and a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection; a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signal at the first node; and a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signal at the first node; wherein the first bias circuit comprises: third and fourth cross-coupled MOS transistors of the first conductivity type, wherein a gate of the third transistor is coupled to a positive reference voltage node and a gate of the fourth transistor is coupled to receive the signal from the first node, and wherein drains of the third and fourth cross-coupled MOS transistors are connected together and directly connected to the first body connection.