Patent ID: 7606994

Claim:
A cache memory system comprising: a cache memory; and a cache controller coupled to the cache memory, wherein the cache memory controller is configured to receive an address and to generate an index value corresponding to the address for accessing a particular entry within the cache memory; wherein the cache controller is configured to generate the index value by performing a hash function on a first portion of the address and by combining a result of the hash function with a second portion of the address; wherein performing the hash function includes performing a first bit-wise Exclusive-Or (XOR) operation on groups of selected bits of the first portion of the address; and wherein the combining includes: performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function; and concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.