Patent ID: 8168487

Claim:
A method of making a semiconductor chip with improved resistance to reverse engineering, said method comprising: a. forming a plurality of transistors in a semiconductor substrate, the transistors having sidewall spacers with LDD regions formed under the sidewall spacers and also having active regions, at least some of the active regions of certain ones of said transistors being disposed near adjacent active regions of certain other one of said transistors, a dopant density of the LDD regions being less than a dopant density of the active regions; b. interconnecting the at least some active regions with adjacent active regions with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with a dopant density having the same dopant density as the dopant density of the LDD regions, with selected ones of the channels having a conductivity type supporting electrical communication and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication; and c. covering a portion of at least one channel formed in the semiconductor substrate and an adjacent active region with silicide, said at least one channel formed in the semiconductor substrate having a conductivity type which inhibits electrical communication with said adjacent active region at a junction, the silicide being disposed over said junction and providing an electrical connection to V SS for both said at least one channel formed in the semiconductor substrate and said adjacent active region.