Patent ID: 7667539

Claim:
An apparatus comprising: an emitter degenerated input stage coupled to a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal, wherein the the emitter degenerated input stage includes a first resistor, a second transistor, a first resistor, and a second resistor; a Caprio circuit coupled to a first supply voltage terminal, wherein the Caprio circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, and a fourth resistor, wherein the first, second, third, and fourth resistors have substantially equal resistance values; a compression stage coupled to the first supply voltage terminal, the signal input terminals, and the Caprio circuit, wherein the compression stage includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; and a current biasing circuit coupled to the emitter degenerated input stage and the Caprio circuit, wherein the current biasing circuit includes: a capacitor that is coupled between a second supply voltage terminal and a current input terminal; an eleventh transistor having a first electrode, a second electrode, and a control electrode, wherein the control electrode of the eleventh transistor is coupled to the current input terminal, and wherein the first electrode of the eleventh transistor is coupled to the first supply voltage terminal.