Patent ID: 7570522

Claim:
A semiconductor device comprising: a first semiconductor chip which is made operable by a first enable signal, and includes a first semiconductor memory device configured to hold data; a second semiconductor chip which is packaged in the same package as the first semiconductor chip and made operable by a second enable signal, and includes a second semiconductor memory device including a memory cell having a charge storage layer and a control gate formed on the charge storage layer; a data bus which connects the first semiconductor chip and the second semiconductor chip such that the first semiconductor chip and the second semiconductor chip are adapted to communicate with each other; a first external pin electrically connected to the data bus, and configured to receive the first enable signal from outside; a second external pin electrically connected to the data bus, and configured to receive the second enable signal from outside; a third external pin electrically connected to the data bus, shared by the first semiconductor chip and the second semiconductor chip, and configured to receive the data from outside; and a fourth external pin shared by the first semiconductor chip and the second semiconductor chip, and configured to receive an address signal from outside, wherein when writing the data in the first semiconductor memory device, the first semiconductor chip is made operable by the first enable signal input to the first external pin, and operates in accordance with the data input to the third external pin and the address signal input to the fourth external pin, and when the first enable signal generated by the second semiconductor chip makes the first semiconductor chip operable, and the address signal generated by the second semiconductor chip is supplied to the first semiconductor chip, the second semiconductor memory device writes the data held in the first semiconductor memory device into the memory cell.