Patent ID: 7402476

Claim:
A process for forming an electronic device comprising: forming a first layer overlying a first plurality of transistor locations of a device substrate, wherein each of the first plurality of transistor locations comprises a gate structure and source/drain locations, wherein the gate structure comprises a conductive gate structure and a sidewall structure; forming a second layer overlying the first layer; etching a first portion of the first layer and the second layer to expose source/drain material comprising a semiconductor element at the source/drain locations of a second plurality of transistor locations and leaving a second portion of the second layer overlying a third plurality of transistor locations, wherein the first plurality of transistor locations comprise the second and third plurality of transistor locations; etching the exposed source/drain material and the second portion of the second layer simultaneously, wherein etching of the exposed source/drain material is end-point-terminated based upon removal of the second layer; and forming a third layer at the source/drain locations of the second plurality of transistor locations after etching the exposed source/drain material, wherein the third layer is formed epitaxially to have a same lattice structure and a different intrinsic lattice spacing as the exposed source/drain material.