Patent ID: 7215561

Claim:
A semiconductor memory system comprising: a memory controller; N system data buses connected to the memory controller, each of the N system data buses having a width of M/N bits, where M is a natural number and N is a natural number greater than or equal to 2; and first through P-th memory module groups, each of the first through P-th memory module groups having N memory modules, where P is a natural number greater than or equal to 2; wherein the N memory modules within each of the first through P-th memory module groups are respectively connected to the N system data buses such that each of the N memory modules within each group is connected to a separate and distinct one of the N system data buses; wherein the first through P-th memory module groups are operated in response to respective first through P-th chip select signals; and, wherein the N system data buses are wired such that data transmission times between the N memory modules within each of the first through P-th module group and the memory controller are the same.