Patent ID: 7084690

Claim:
A method of designing a semiconductor integrated device comprising: designing a first circuit, the first circuit comprising: first latches receiving a first clock signal via first distribution lines; a phase adjusting circuit receiving the first clock signal via first distribution lines and outputting a second clock signal; first and second terminals coupled to the phase adjusting circuit; preparing a design data of a second circuit, the second circuit comprising: a third terminal receiving the second clock signal; second latches coupled to the third terminal and receiving the second clock signal distributed from second distribution lines; a fourth terminal outputting the second clock signal distributed from the second distribution lines; and integrating the first and second circuits by coupling the first terminal with the third terminal, and the second terminal with the fourth terminal, wherein the phase adjusting circuit outputs the second clock signal to synchronize the first clock signal inputted to the phase adjusting circuit with the second clock signal inputted to the phase adjusting circuit from the fourth terminal.