Patent ID: 7807492

Claim:
A MRAM memory process, comprising: forming a first conductive layer on a substrate; forming a first dielectric layer on the first conductive layer; patterning the first dielectric layer to form a first opening exposing the first conductive layer; forming a first metal plug in the first opening to electrically connect the first conductive layer; forming a GMR magnetic layer on the first dielectric layer and the first metal plug; patterning the GMR magnetic layer to form two separate portions of the GMR magnetic layer with one portion as an intermediate conductive layer and the other portion as a memory bit layer; forming a second dielectric layer on the GMR magnetic layer; patterning the second dielectric layer to form a second opening exposing the intermediate conductive layer; forming a second metal plug in the second opening to electrically connect the intermediate conductive layer; and forming a second conductive layer on the second dielectric layer and the second metal plug.