Patent ID: 7977968

Claim:
A memory system, comprising: a plurality of memory modules connected to a data channel in common; and a plurality of ranks connected to the plurality of memory modules as a logical memory operation unit and configured to independently perform an on die termination (ODT) according to read and write operations of the plurality of memory modules, which plurality of ranks include a termination resistor control unit for allocating a different impedance to termination resistors of the plurality of ranks during the read and write operations according to a combination of a chip selection signal, an ODT control signal and a code control signal, wherein the termination resistor control unit includes: a code channel configured to output a plurality of code signals based on the code control signal; a termination resistor decoder configured to decode the chip selection signal, the ODT control signal and the plurality of code signals and output a plurality of selection signals based on the decoded signals; and an ODT block configured to provide an output data pad with the impedance of termination resistor which is selected in response to the plurality of selection signals.