Patent ID: 8856629

Claim:
A device for testing a circuit to be tested, comprising: a syndrome determiner configured to determine an error syndrome bit sequence (s(v′)) based on a coded binary word (v′), wherein the error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′); a test sequence provider having an input coupled to an output of the syndrome provider, the test sequence provider configured to provide a test bit sequence (T i ) to the circuit to be tested, wherein if the error syndrome bit sequence (s(v′)) indicates that the coded binary word (v′) is a code word of the error correction code (C), then the test bit sequence (T i ) is different than the determined error syndrome bit sequence (s(v′)); and an evaluation circuit configured to detect an erroneous processing of the test bit sequence (T i ) by the circuit to be tested, based on a test output signal (R(T i )′) which is provided by the circuit to be tested in response to the test bit sequence (T i ).