Patent ID: 8605173

Claim:
An image processing system comprising: a column analog-to-digital converter (ADC), electrically coupled with a pixel of an image sensor array, comprising: a gain stage comprising a first differential input node and a second differential input node, and configured to operate in an auto-zero mode or a non-auto-zero mode; a differential sampling subsystem, electrically coupled with the gain stage, and configured to: sample a pixel reset level at the first differential input node during a first operating state, the pixel reset level received from the pixel of the image sensor array; sample a pixel signal level at the second differential input node during a second operating state subsequent to the first operating state, the pixel signal level received from the pixel of the image sensor array; sample a ramp reset level at the first differential input node during a third operating state subsequent to the second operating state; and sample a ramp signal level at the second differential input node of the gain stage during the third operating state, the ramp signal level received from a ramp generator and changing over time according to a slope; and a crossover detection subsystem, electrically coupled with the differential sampling subsystem, and configured to: detect a crossover time at which at least one output of the gain stage changes polarity during the third operating state as the ramp signal level at the second differential input node changes while the ramp reset level at the first differential input node stays at a substantially constant level; and output a digital code corresponding to the crossover time.