Patent ID: 8467241

Claim:
A semiconductor memory device, comprising: a semiconductor layer that extends in a first direction; first and second electrodes that are provided, in the first direction, on one end and the other end of the semiconductor layer; first and second block insulation films that sandwich the semiconductor layer and that are provided in a second direction orthogonal to the first direction; a first charge accumulation film that is provided between the first block insulation film and the semiconductor layer; a second charge accumulation film that is provided between the second block insulation film and the semiconductor layer; a first tunnel insulation film that is provided between the first charge accumulation film and the semiconductor layer; a second tunnel insulation film that is provided between the second charge accumulation film and the semiconductor layer; n front gate electrodes that are provided in the first direction as insulated from each other and that are provided at an opposite side from the side where the first charge accumulation film of the first block insulation film is disposed, where “n” is a positive integer equal to or greater than two; n back gate electrodes that are provided in the first direction as insulated from each other and that are provided at an opposite side from the side where the second charge accumulation film of the second block insulation film is disposed; front gate insulation films that insulate the n front gate electrodes; back gate insulation films that insulate the n back gate electrodes; and a plurality of diffusion regions provided between the first and second electrodes and between the front gate insulation films and the back gate insulation films, the plurality of diffusion regions being separated from each other within the semiconductor layer, wherein information is written in the semiconductor layer by applying a first potential to the first electrode, applying a second potential that is lower than the first potential to all of the back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1) th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the i th and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.