Patent ID: 7340702

Claim:
A method of circuit verification, comprising: (a) performing bounded verification on a circuit design for a number of transitions, the bounded verification corresponding to a predetermined limit for a number of transitions, wherein the predetermined limit is less than a total number of all reachable states; (b) performing induction proof of a first property for the number of transitions, wherein the induction proof is performed by a process comprising the acts of: including, in an inductive set of one or more states, a plurality of states of the circuit design, wherein the inductive set of one or more states includes at least states passing the first property of the circuit design; transitioning by at least one step, in a forward direction, states of the inductive set passing at least the first property of the circuit design, resulting in transitioned states; determining if the transitioned states of the inductive set pass at least the first property of the circuit design; repeating at least the transitioning and the determining, until at least, the determining results in the transitioned states of the inductive set passing or failing at least the first property of the circuit design; and (c) if the at least one property is not verified, then increasing the limit for the bounded verification and repeating from (a).