Patent ID: 8484404

Claim:
A digital signal processor, comprising: an adjustment value register configured to store an initial adjustment value and a succeeding adjustment value; an address generator circuit communicatively coupled with the adjustment value register and configured to retrieve an instruction including a memory address value that is greater than N and a further instruction including a further memory address value that is less than or equal to N, N being related to an address range defined by a number of bits utilized to encode a memory address; and a memory communicatively coupled with the address generator circuit and including a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N, the address generator circuit being further configured to: access the high bank address space, using the initial adjustment value and the memory address value, when the adjustment value register is not storing the succeeding adjustment value, and access the high bank address space, using the succeeding adjustment value and the further memory address value, when the adjustment value register is storing a succeeding adjustment value.