Patent ID: 7286427

Claim:
An integrated semiconductor memory device with test circuit for sense amplifiers, the integrated semiconductor memory device comprising: a terminal to apply a data item; a set of memory cells; a first bit line pair comprising a first bit line and a second bit line, wherein each of the memory cells in the set is connected to one of the bit lines of the first bit line pair; a first sense amplifier that is connected to the first bit line pair, wherein the first sense amplifier is configured to charge the first bit line and the second bit line of the first bit line pair opposite to each other during a read and write access to one of the memory cells in the set such that one of the first bit line and the second bit line of the first bit line pair is charged to a high voltage potential and the other of the first bit line and the second bit line of the first bit line pair is charged to a low voltage potential; a controllable switching unit to feed an equalizing voltage to the first bit line and the second bit line of the first bit line pair, wherein the controllable switching unit is configured to connect the first bit line and the second bit line of the first bit line pair to each other with low impedance before and after a read and write access to one of the memory cells in the set and to feed the equalizing voltage at a medium voltage potential to the first bit line and the second bit line of the first bit line pair, the medium voltage potential being at a value between the high voltage potential and the low voltage potential; and a controllable voltage generator connected to the first bit line pair so as to feed a precharging voltage to at least one of the first bit line and the second bit line of the first bit line pair, wherein the controllable voltage generator is configured to feed the precharging voltage to at least one of the first bit line and the second bit line of the first bit line pair in an activated state during a test mode of the integrated semiconductor memory device in which the first bit line and the second bit line of the first bit line pair are separated from each other with high impedance, the precharging voltage being selected to have a value between the medium voltage potential of the equalizing voltage and the high voltage potential or between the medium voltage potential of the equalizing voltage and the low voltage potential depending upon the state of the data item.