Patent ID: 8563429

Claim:
A method of forming a metal silicide layer, comprising: forming line-and-space patterned gate structures on a semiconductor substrate; depositing an oxide layer on substantially the entire surface of the semiconductor substrate having the gate structures formed thereon; depositing a polishing stop layer on substantially the entire surface of the oxide layer; depositing an interlayer insulating layer on substantially the entire surface of the polishing stop layer; polishing the interlayer insulating layer up to the surface of the polishing stop layer; etching the interlayer insulating layer, the polishing stop layer, and the oxide layer through just dry etching (JDE) such that substantially the entire upper surface and partial side surfaces of the gate structures are exposed; recessing the oxide layer between gate structures through chemical dry etching (CDE) such that the side surfaces of the gate structures are further exposed; and forming a silicide layer at portions comprising at least the exposed portion of the gate structures.