Patent ID: 8072826

Claim:
A memory control circuit, comprising: a data sample circuit, for generating a first data strobe signal and a second data strobe signal, wherein the first data strobe signal is distinct from the second data strobe signal; a first delay control circuit, coupled to the data sample circuit, for receiving the first data strobe signal and delaying the first data strobe signal to generate a first delayed data strobe signal; a second delay control circuit, coupled to the data sample circuit, for receiving the second data strobe signal and delaying the second data strobe signal to generate a second delayed data strobe signal; and a data circuit, coupled to the first delay control circuit and the second delay control circuit, for transferring data signals according to the first delayed data strobe signal and the second delayed data strobe signal, wherein the data circuit comprises: a first D flip-flop (DFF), for generating a first output data signal according to the first delayed data strobe signal and a data signal; a second DFF, coupled to the first DFF, for generating a second output data signal according to the second delayed data strobe signal and the first output data signal; and a third DFF, for generating a third output data signal according to the second delayed data strobe signal and the data signal.