Patent ID: 6903975

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell, including a source layer formed in a semiconductor substrate, a drain layer formed in said semiconductor substrate and apart from said source layer, a floating gate formed above a portion of said semiconductor substrate between said source layer and said drain layer, and a control gate formed above said floating gate; a word line control circuit to drive a word line connected to said control gate; a program data holding circuit to hold program data; a programming voltage generator circuit to apply a programming voltage to a bit line connected to said drain layer; and a discrimination circuit to verify said program data, wherein programming of said programming data to said memory cell is conducted by injecting hot electrons generated between said source layer and said drain layer into said floating gate, and wherein verification of said programmed data is conducted by the following steps: (a) charging a pre-charge voltage to said bit line; (b) making said bit line a floating state, after step (a); (c) applying a verify voltage to said word line, after the step (b); and (d) discriminating whether said pre-charge voltage is retained or not, depending upon a height of a threshold voltage of said memory cell, after step (c).