Patent ID: 8361872

Claim:
A method of forming a semiconductor device, comprising: forming a heavily doped region in a substrate; forming an undoped silicon layer over the heavily doped region; forming a gate of a field effect transistor (FET) on the undoped silicon layer, wherein a channel of the FET is in the undoped silicon layer, and wherein the gate comprises a gate stack including a gate dielectric formed on the undoped silicon layer and a gate electrode formed over the gate dielectric; forming first spacers composed of nitride on sidewalls of the gate stack; forming a second spacer composed of oxide on an exposed top surface of the gate electrode, on side surfaces of the first spacers, and on a portion of the undoped silicon layer; forming recesses adjacent the channel and the heavily doped region, wherein the forming the recesses comprises etching the undoped silicon layer and the heavily doped region while masking portions of the undoped silicon layer and the top surface of the gate electrode with the second spacer, and wherein sidewalk of the recesses are aligned with sidewalls of the second spacer; forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.