Patent ID: 7323771

Claim:
A data processing device comprising: a plurality of semiconductor devices formed on semiconductor chips, respectively, and mounted on one side of a build-up board; and a plurality of external terminals for setting on another side of said build-up board for connecting to another circuit board, wherein said semiconductor devices include a plurality of scanning latches for corresponding to certain external terminals and for connecting serially between a test input terminal and a test output terminal in response to the test control signal from a test control terminal, and for operating as a shift register to input and output test signals, wherein said build-up board further includes a selection control circuit a common test input terminal, a common test output terminal, and a common test control terminal which is connected to each of said test control terminal of plurality of semiconductor devices, in parallel, wherein said selection control circuit selects a serial connection test mode or a separate connection test mode according to a test mode signal, wherein in said serial connection mode, said test output terminal of said semiconductor device is connected to a test input terminal of another semiconductor device, and said common test input terminal connects to said common test output terminal through said test input terminal and said test output terminal of said semiconductor device and said test input terminal and said test output terminal of said another semiconductor device, in serially, and wherein in said separate connection test mode, said test input terminal connects to said common test input terminal, and said test output terminal connects to said common test output terminal of each of said plurality of semiconductor devices, individually, wherein said build-up board has a substrate and multi-wiring-layers for forming on one main surface of said substrate, wherein a surface of said multi-wiring-layers has connect terminals for disposing to mount semiconductor devices, and for conducting to certain wiring lines of said multi-wiring-layers, and wherein said another surface of said substrate mounts said external mounting terminals for forming to penetrate said main surface of substrate for conducting to certain wiring lines of said multi-wiring-layers.