Patent ID: 7781817

Claim:
A semiconductor structure, comprising: a semiconductor substrate which includes a top substrate surface, wherein the top substrate surface defines a first reference direction that is perpendicular to the top substrate surface; a control gate electrode region on and above the semiconductor substrate; a first semiconductor body region on and above the semiconductor substrate, wherein the first reference direction is directed from the top substrate surface toward the first semiconductor body region; a second semiconductor body region on and above the first semiconductor body region, wherein the second semiconductor body region overlaps the first semiconductor body region in the first reference direction; a first gate dielectric region on and in direct physical contact with side walls of the first semiconductor body region, wherein the first gate dielectric region is disposed between the first semiconductor body region and the control gate electrode region; and a second gate dielectric region on and in direct physical contact with side walls of the second semiconductor body region, wherein the second gate dielectric region is disposed between the second semiconductor body region and the control gate electrode region, wherein a thickness of the first gate dielectric region in a second reference direction is less than a thickness of the second gate dielectric region in the second reference direction, wherein the second reference direction is perpendicular to the first reference direction and to a side wall of the side walls of the first semiconductor body region, wherein a first portion of the first gate dielectric region overlaps the second gate dielectric region in the first reference direction, wherein a second portion of the first gate dielectric region extends below the second gate dielectric region in a direction opposite the first reference direction, wherein the control gate electrode region comprises a bottom surface and a top surface which collectively bound the control gate electrode region in the first reference direction, wherein a bottom surface of the first semiconductor body region is above the bottom surface of the control gate electrode region in the first reference direction, wherein the top surface of the control gate electrode region is above the second semiconductor body region in the first reference direction, and wherein the control gate electrode region comprises polysilicon which is continuously distributed from the bottom surface of the control gate electrode region to the top surface of the control gate electrode region.