Patent ID: 7018889

Claim:
A method of fabricating a memory cell comprising the steps of: providing a substrate assembly having at least one semiconductor layer; forming a first semiconductor structure within said at least one semiconductor layer; forming a first source and a first drain of a first pull-up transistor in said first semiconductor structure; forming a second source and a second drain of a first pull-down transistor in said at least one semiconductor layer; forming a first contact and a second contact within said first semiconductor structure; forming a first gate for said first pull-up transistor and a second gate for said first pull-down transistor; coupling said first drain to said second drain; coupling said first gate to said second gate; and coupling said first source to one of said first and second contacts such that with the other of said first and second contacts coupled to a first voltage input said first source is coupled to said first voltage input through parasitic resistance of said first semiconductor structure.