Patent ID: 8084308

Claim:
A method of fabricating a FET inverter, comprising the steps of: forming a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region; introducing an n-type dopant into the source and drain regions of one or more of the device layers; introducing a p-type dopant into the source and drain regions of one or more other of the device layers; activating the n-type dopant introduced into the source and drain regions of the one or more device layers; activating the p-type dopant introduced into the source and drain regions of the one or more other device layers; forming a gate common to each of the device layers surrounding the nanowire channels wherein the source and drain regions of each of the device layers are self-aligned with the gate, and wherein the n-type dopant introduced into the source and drain regions of the one or more device layers and the p-type dopant introduced into the source and drain regions of the one or more other device layers are activated before the gate is formed; forming a first contact to the source regions of the one or more device layers doped with an n-type dopant; forming a second contact to the source regions of the one or more device layers doped with a p-type dopant; and forming a third contact common to the drain regions of each of the device layers.