Patent ID: 7106641

Claim:
A dynamic semiconductor memory device comprising: memory cell groups oppositely disposed on one side and the other side; multiple bit line pairs, on one side, connected to said memory cell group on the one side; multiple bit line pairs, on the other side, connected to said memory cell group on the same other side and; a shared sense amplifier, which is provided in between said memory cell groups on one side and the other side, and controls said bit line pair on the one side and said bit line pair on the other side; said shared sense amplifier comprising; an equalizer circuit, on one side, connected to each of said bit line pair on the one side; an equalizer circuit, on the other side, connected to each of said bit line pair on the same other side; one or a multiple of said equalizer circuits on one side, and one or a multiple of said equalizer circuits on the other side; and one current-limiting element that supplies a bit line precharge potential to one or a multiple of said equalizer circuits on one side and the other side; wherein said memory cell group on one side and said memory cell group on the other side are assigned to different units in terms of a unit of memory cell group, connected to each of said equalizer circuit on one side and said equalizer circuit on the other side, sharing said one current-limiting element, that is to be replaced by the same group in column redundancy, termed “column replacement segment” hereafter.