Patent ID: 8432023

Claim:
A semiconductor package, comprising: a generally planar die pad residing on a first plane; a plurality of land leads at least partially circumventing the die pad, each of the land leads residing on the first plane; a plurality of support bars connected to and extending generally perpendicularly from multiple peripheral edge segments of the die pad, each of the support bars extending at least partially between a respective adjacent pair of the land leads; a plurality of peripheral leads at least partially circumventing the land leads, each of the peripheral leads at least partially residing on a second plane which extends in spaced, generally parallel relation to the first plane; a semiconductor die attached to the die pad and electrically connected to at least some of the land and peripheral leads; and a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the die pad, the land and peripheral leads, and the semiconductor die such that portions of the land leads are exposed in the bottom surface of the package body, and portions of the peripheral leads protrude from the side surface thereof.