Patent ID: 7969343

Claim:
An analog-to-digital converter circuit comprising: a capacitor array including a plurality of first capacitors, each having a first terminal connecting to a common node and having a capacitance represented by the nth power of 2 (2 n ) (where n is a positive integer) on the basis of the smallest of the capacitances of the first capacitors=1; a switch array including a plurality of first switches alternately supplying and disconnecting one of a first reference voltage and a second reference voltage to and from a second terminal of each of the first capacitors; a second capacitor connected to a common node through a third terminal and contributing to attenuation of the voltage on the common node; a second switch connecting to a fourth terminal of the second capacitor and supplying an input signal or a fourth reference voltage to the second capacitor; a third switch connecting to the common node and alternately supplying and disconnecting the third reference voltage to and from the common node; a comparator comparing the voltage on the common node with a fifth reference voltage; and a control circuit controlling the supply and disconnection by the first switches, the supply by the second switch, and the supply and disconnection by the third switch.