Patent ID: 7299254

Claim:
A binary coded decimal adder circuit for adding two operands and an input carry to give a sum comprising: a first stage receiving said operands, grouping said operands into equal length blocks of contiguous bits and, for each said block, logically computing from said operands an intermediate sum vector, an intermediate carry vector, a propagate function and a generate function; a second stage receiving said input carry and receiving from each said block of said first stage the respective propagate function and generate function, and carry look ahead computing therefrom carries for each said block and an output carry; and a third stage, having the same number of blocks as said first stage, each third stage block receiving a respective intermediate sum vector, and logically adjusting said intermediate sum vector by pre-correction factors which depend upon a respective intermediate carry vector, at least two of the one of said second stage carries and said input carry; and wherein outputs of said third stage logic blocks together represent said sum of operands.