Patent ID: 7987063

Claim:
A formatter adapted for use in an automatic test system to generate a signal based on a plurality of timing signals from timing circuitry, the formatter comprising: a latch having a first input port and a second input port; a plurality of signal paths each arranged between the timing circuitry and the latch, each signal path comprising: a switching circuit comprising: a signal input coupled to an output of the timing circuitry and configured to receive a timing signal of the plurality of timing signals from the timing circuitry; a control input configured to receive a control signal; a first output connected to the first input port of the latch; and a second output connected to the second input port of the latch; the switching circuit being adapted to selectively alter an output signal provided at the first output of the switching circuit or the second output of the switching circuit in response to the control signal being received at the control input, wherein the output signal is generated in response to the timing signal being received at the signal input of the switching circuit.