Patent ID: 7363470

Claim:
A microprocessor, comprising: one or more functional units, each configured to execute operations; a scheduler configured to issue each of a plurality of operations for execution by one of the one or more functional units, wherein the scheduler is configured to maintain state information for each of the plurality of operations, wherein the state information indicates whether an associated operation has completed execution; and a replay detection unit configured to detect that one of the plurality of operations should be replayed, wherein to detect that one of the plurality of operations should be replayed the replay detection unit is configured to determine that the one of the plurality of operations is dependent on another operation to be replayed, wherein the replay detection unit is configured to inhibit an update to the state information for the one of the plurality of operations in response to execution of an instance of the one of the plurality of operations if the instance of the one of the plurality of operations is currently being executed by one of the one or more functional units when the one of the plurality of operations is detected as needing to be replayed.