Patent ID: 7072221

Claim:
A flash memory device, comprising: a memory cell; a pulse information register for storing pulse level or bias level information; a controller for generating a first control signal according to a program command or erase command, and a second control signal according to a program or erase state of the memory cell; a pulse counter for receiving the pulse level or bias level information from the pulse information register according to the first control signal from the controller, and performing a counting operation according to the information and generating a counting signal; a pulse generator for generating a predetermined pulse by determining the pulse level or bias level according to the counting signal from the pulse counter, and applying the pulse to the memory cell according to the second control signal from the controller; a sense amplifier for verifying the program state of the memory cell, and generating a pass flag when at least one bit of cells of the corresponding cells satisfy a verification level; and a logic unit for updating the pulse level or bias level stored in the pulse information register, by generating an update flag by logically combining the pass flag and an initial flag notifying whether the pulse information register has an initial value.