Patent ID: 7330928

Claim:
A semiconductor device, comprising: a volatile memory which retains data by a cyclic refresh operation; a first PLL circuit which multiplies an input clock signal and outputs an operation clock signal having a frequency higher than a frequency of the input clock signal; a circuit block which operates in synchronization with the operation clock signal; first and second refresh controllers for requesting the refresh operation of the volatile memory; and a memory controller which arbitrates between an access request for the volatile memory from the circuit block and a refresh request from the first refresh controller, and controls access to the volatile memory in response to one of the access request and the refresh request, wherein, in a first mode in which the first PLL circuit operates, the first refresh controller operates in synchronization with the operation clock signal and issues the refresh request for the volatile memory to the memory controller; and wherein, in a second mode in which the first PLL circuit stops operation, supply of the operation clock signal to the first refresh controller and the memory controller is stopped, and the second refresh controller operates in synchronization with the input clock signal and issues the refresh request to the volatile memory, the refresh request bypassing the memory controller.