Patent ID: 7501310

Claim:
A process of wafer level package, comprising the steps of: forming a first photo resist pattern on metal pads of a plurality of dies on a wafer to cover said metal pads; forming a first dielectric layer on said first photo resist pattern and said plurality of dies; curing said first dielectric layer; removing said first photo resist pattern; sawing said plurality of dies on said wafer to form individual dies; selecting good said dies and attaching said good dies to an isolating base; curing said isolating base; forming a material layer on said isolating base to fill in a space among said plurality of dies on said isolating base; curing said material layer; forming a second dielectric layer on said material layer and said metal pads; etching a partial region of said second dielectric layer on said metal pads to form first openings on said metal pads; curing said second dielectric layer; forming a contact conductive layer on said first openings to electrically couple with said metal pads, respectively; forming a second photo resist layer on said second dielectric layer and said contact conductive layer; removing a partial region of said second photo resist layer to form a second photo resist pattern and expose said contact conductive layer to form second openings; forming conductive lines on said second photo resist pattern and said second openings being coupled with said contact conductive layer, respectively; removing remaining said second photo resist layer; forming an isolation layer on said conductive lines and said second dielectric layer; removing a partial region of said isolation layer on said conductive lines to form third openings; curing said isolation layer; and welding solder balls on said third openings.