Patent ID: 8473815

Claim:
A flash memory controller, comprising: a flash memory interface controller; a host interface controller; an error correction code (ECC) encoder configured to receive information data from the host interface controller and generate first ECC data with variable lengths in response to the information data to be stored in a flash memory; an ECC divider configured to divide each first ECC datum of the first ECC data into one or more ECC segments according to a respective length of each first ECC datum and forward the ECC segments to the flash memory interface controller, wherein each of the ECC segments is stored in different flash pages of a flash block through a pointer field pointing to a next ECC portion storing a next ECC segment; an ECC constructor configured to receive one or more of the ECC segments from the flash memory interface controller and generate a second ECC datum by combining the received ECC segments for each of the information data read from the flash memory; and an ECC decoder configured to correct errors of the information datum read from the flash memory based on the read information datum and the second ECC datum and forward the corrected read information datum to the host interface controller.