Patent ID: 8521483

Claim:
A method of generating a representation of an electronic circuit across a plurality of design entry tools, comprising: capturing a first partition of the electronic circuit in a first design entry tool; capturing a second partition of the electronic circuit in a second design entry tool; extracting a first partial circuit including a first plurality of first electronic components from the first partition; extracting a second partial circuit including a second plurality of second electronic components from the second partition; generating a simulation block in the first design entry tool including an interface between the first and second partitions; exporting a first netlist representing the interconnection of the first electronic components in the first partial circuit; populating the simulation block in the second design entry tool to include a second netlist representing the interconnection of the second electronic components in the second partial circuit and the interface between the first and second partitions; and exporting the second netlist to stitch the extracted first and second partial circuits using the interface between the first and second partitions.