Patent ID: 7554130

Claim:
An integrated circuit having memory, comprising: thyristor-based memory cells, each of the thyristor-based memory cells including a thyristor-based storage element and an access transistor, the thyristor-based storage element including an anode region and a cathode region; a pair of the thyristor-based memory cells commonly coupled via a bitline region associated with the access transistor; the pair of the thyristor-based memory cells defining a parasitic bipolar junction transistor therebetween responsive to the bitline region being common; the bitline region having a locally implant-damaged region to inhibit charge transfer between the pair of the thyristor-based memory cells via the parasitic bipolar junction transistor; the locally implant-damaged region extending to and in contact with an insulator layer of a silicon-on-insulator wafer on which the integrated circuit is formed; and the locally implant-damaged region formed with lateral control for at least some separation from p-n junctions of the bitline region.