Patent ID: 7352250

Claim:
A phase locked loop circuit comprising: a first voltage locked oscillator; a first circuit for frequency conversion, with which the output of said first voltage locked oscillator is connected; a first phase detector, with whose first input, the output of said first circuit for frequency conversion is connected, and with whose second input, a first reference signal is connected; a first charge pump circuit, with which the output of said first phase detector is connected; and a first loop filter, with which the output of said first charge pump circuit is connected, wherein the output of said first loop filter is configured to be connected with the input of said voltage locked oscillator, with the input of said second input of said first phase detector, the first reference signal and a first signal source for detecting the loop characteristics, whose frequency varies, are configured to be able to be selectively connected, and said first signal source has a configuration to compensate the delay caused in the process of generating said first reference signal.