Patent ID: 6868096

Claim:
A data multiplexing apparatus comprising: a single memory for storing an audio stream and a video stream; and a multiplexer comprising: an internal bus connected to said single memory; a header cache memory for storing a system header, an audio header, and a video header; an audio stream cache memory, connected to said internal bus, for storing said audio stream; a video stream cache memory, connected to said internal bus, for storing said video stream; an address generation circuit, connected to said single memory by said internal bus, for fetching said audio stream and said video stream from said single memory on a time division basis, so that said audio stream and said video stream are stored via said internal bus in said audio stream cache memory and said video stream cache memory, respectively; a bus arbitration circuit, connected to said address generation circuit, for controlling said address generation circuit and arbitrating access to said internal bus; a system clock counter for generating a system clock signal indicating a current time; a selector circuit, connected to said header cache memory, said audio stream cache memory, said video stream cache memory, and said system clock counter, for sequentially selecting said header cache memory, said audio stream cache memory, and said video stream cache memory and outputting a system stream comprising said system header, said audio header, said audio stream, said video header, and said video stream, respectively; and a control circuit, connected to said bus arbitration circuit and said selector circuit, for controlling said selector circuit to select said system clock counter to input said system clock signal to a predetermined position of said system header, wherein said single memory is external to said multiplexer.