Patent ID: 7012950

Claim:
An apparatus for generating PN (pseudo noise) codes comprising: a control unit for outputting a control signal for a normal state or a PN chip advance; a plurality of multiplexers for outputting an output value of a next state for a normal operation or an output value of a following next state ({right arrow over (r)} m+2 ) for a PN chip advance as an output signal in response to the control signal of said control unit; a plurality of shift registers for outputting a PN chip code of a next state({right arrow over (r)} m+1 ) or a following next state ({right arrow over (r)} m+2 ) during one system clock time period in response to said outputs of the multiplexers, an input end of each of said shift registers being connected to an output end of each of said multiplexers, wherein to obtain the output value of the following next state ({right arrow over (r)} m+2 ) of shift registers for one PN chip advance, the output values are determined based on the following equation: {right arrow over (r)} m+2 =└r n,m+2 r n−1,m+2 . . . r 1,m+2 0┘, r i , m + 2 = { ⁢ r i - 2 , m ⊕ ( r n , m ⁢ g i - 2 ) ⊕ [ { r n - 1 , m ⊕ 1 < i ≤ n , ( r n , m ⁢ g n - 1 ) } ⁢ g i - 1 ] , wherein ⁢ ⁢ i ⁢ ⁢ is ⁢ ⁢ an ⁢ ⁢ integer r n - 1 , m ⊕ ( r n , m ⁢ g n - 1 ) , i = 1 0 , i = 0 wherein {right arrow over (r m )} is present state values of the shift registers and {right arrow over (g n )} is parameter values of a generation polynomial.