Patent ID: 7046216

Claim:
A three-electrode plasma display panel (PDP) driving method for displaying a frame including a plurality of sub-fields, the method comprising: generating a reset discharge by supplying ramp waves for making cells of the PDP in a uniform state in a reset period of selective write type sub-fields; generating an address discharge by supplying a selective write scan pulse (SWSP) that swings round a maximum supply voltage level of the reset discharge and a selective write data pulse (SWDP) that is synchronized with the selective write scan pulse (SWSP) during an address period following the reset period; and keeping the generated address discharge by supplying a sustain pulse during a sustain period following the address period, wherein generating a reset discharge comprises: adding up a reset pulse of a ramp-up waveform; supplying the reset pulse to a scan electrode; supplying to the scan electrode a reset pulse of a ramp-down waveform; and maintaining a minimum supply voltage level based on the ramp-down waveform for a specified period, wherein the specific period is determined based on the reset pulse of the ramp-up waveform going from a maximum voltage level down to the minimum supply voltage level, and wherein the minimum supply voltage level is relatively higher than a predetermined negative scan reference voltage; supplying a positive scan DC voltage for reducing wall charge previously formed, when the reset pulse of the ramp-down waveform is supplied; and supplying a second scan DC voltage relatively lower than the first scan DC voltage to sustain the voltage so as to minimize power consumption in the plasma display panel.