Patent ID: 8609995

Claim:
A manufacturing method of a multilayer wiring board, the multilayer wiring board comprising a laminated wiring portion having a plurality of resin insulation layers and conduction layers alternately laminated on each other, the resin insulation layers including an outer resin insulation layer as the outermost layer of the laminated wiring portion and an inner resin insulation layer as the inner layer of the laminated wiring portion, the outer resin insulation layer being made of the same insulation resin material as the inner resin insulation layer, containing a filler of inorganic oxide and having an outer surface defining thereon a chip mounting area to which an electronic chip is mounted with an underfill material filled in a clearance between the outer resin insulation layer and the electronic chip and holes through which conductor parts are exposed, the amount of the filler present at the outer surface of the outer resin insulation layer being lower than the amount of the filler present inside of the outer resin insulation layer and being lower than the amount of the filler present at wall surfaces of the holes, the manufacturing method comprising: a hole forming step of forming the holes in the outer resin insulation layer by laser processing; a desmear treatment step of, after the hole forming step, removing smears from inside the holes of the outer resin insulation layer; and a filler reducing step of, after the desmear treatment step, reducing the amount of the filler exposed at the outer surface of the outer resin insulation layer.