Patent ID: 7355873

Claim:
A semiconductor memory device, comprising a plurality of memory cells arranged in rows and columns, each memory cell being configured to hold information of two bits and including: a first cell capable of holding information of one bit; a second cell capable of holding information of one bit and placed adjacent to said first cell in a direction of said columns; a bit line pair extending along the direction of said columns and connected to both of said first and second cells; first and second word lines extending along a direction of said rows and connected to said first and second cells, respectively; and a logical operation cell placed adjacent, in the direction of said rows, to both of said first and second cells extending along the direction of the columns, and outputting results based on search data and information held in said first and second cells, wherein a gate of a transistor forming each of said plurality of memory cells extends along the direction of said rows, and a region where each of said plurality of memory cells is formed includes first to third wells aligned in this order along the direction of said rows, and said first and third wells are of a first conductivity type and said second well sandwiched between said first and third wells is of a second conductivity type.