Patent ID: 8391098

Claim:
A data input/output method of a semiconductor memory apparatus that stores write data in a plurality of latch units, inputs the write data to global input/output lines through a plurality of input drivers, and inputs the write data from the global input/output lines to a plurality of write drivers, during a write operation that stores write data input from a data input/output buffer in memory cells in response to an input driver control signal and a write driver control signal, wherein the latch units are divided into a first latch unit group including half the latch units and a second latch unit group including the other half the latch units and the write drivers are divided into a first write driver group including half the write drivers and a second write driver group including the other half of the write drivers, the method comprising: outputting the write data stored in the first latch unit group to the global input/output lines through the plurality of input drivers for a time corresponding to half a burst length in response to the input driver control signal after a write command is issued; inputting the write data from the global input/output lines to the first write driver group in response to the write driver control signal; outputting the data stored in the second latch unit group to the global input/output lines through the plurality of input drivers for a time corresponding to half the burst length in response to the input driver control signal that is delayed for a predetermined time; and inputting the write data from the global input/output lines to the second write driver group in response to the delayed write driver control signal.