Patent ID: 7635645

Claim:
A method of forming an interconnection line for a semiconductor device, comprising: forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer formed of SiOC or SiOCH; forming an SiCN layer on the interlayer insulating layer; forming an oxide capping layer on the SiCN layer; forming a first photoresist pattern on the oxide capping layer; anisotropically etching the oxide capping layer, the SiCN layer, and the interlayer insulating layer using the first photoresist pattern as a first etch mask to form a via hole; removing the first photoresist pattern; forming a sacrificial filling layer to fill the via hole; forming a second photoresist pattern on the sacrificial filling layer; anisotropically etching the sacrificial filling layer, the oxide capping layer, the SiCN layer, and a portion of the interlayer insulating layer using the second photoresist pattern as a second etch mask to form a trench overlapping at least a portion of the via hole; removing the second photoresist pattern; removing the sacrificial filling layer to form a dual damascene pattern on the semiconductor substrate; and forming a conductive layer pattern within the dual damascene pattern.