Patent ID: 8319260

Claim:
A semiconductor device, comprising: a first gate structure including a first gate insulation layer pattern, a first polysilicon layer pattern, a first conductive layer pattern, and a first hard mask sequentially stacked on a substrate in a first region thereof, the first polysilicon layer pattern having atoms larger than silicon; n-type impurity regions formed at first upper portions of the substrate adjacent to the first gate structure; a second gate structure including a second gate insulation layer pattern, a second polysilicon layer pattern, and a second conductive layer pattern, and a second hard mask on the substrate in a second region thereof, the second polysilicon layer pattern having atoms smaller than silicon; and p-type impurity regions at second upper portions of the substrate on adjacent to the second gate structure, wherein the first conductive layer pattern includes a metal and is between the first polysilicon layer pattern and the first hard mask, and wherein the second conductive layer pattern includes a metal and is between the second polysilicon layer pattern and the second hard mask.