Patent ID: 7709372

Claim:
A method of manufacturing a semiconductor device, the method comprising the steps of: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer formed therein the via hole and performing a planarizing process; etching the first barrier metal layer and the second metal layer in the via hole to a predetermined depth together with selectively etching a surface of the second metal layer, simultaneously, thereby obtaining a first barrier metal and a second metal; forming a silicon layer on the first barrier metal and the second metal to a predetermined height, wherein the silicon layer is formed of amorphous silicon; forming a second barrier metal layer on the interlayer insulating layer including the via hole; forming a third metal layer on the second barrier metal layer; and forming a second barrier metal pattern and a third metal layer pattern by patterning the second barrier metal layer and the third metal layer.