Patent ID: 7500126

Claim:
A circuit arrangement comprising: a plurality of hardware resources, wherein each hardware resource has a power mode configurable between at least first and second power consumption states; a processor coupled to the plurality of hardware resources, the processor configured to process program code that includes at least one power control instruction that includes an operand having power control information disposed therein, wherein the processor is configured to process the power control instruction by selectively setting power modes of at least two hardware resources among the plurality of hardware resources based upon the power control information disposed in the power control instruction, and maintain the power modes of the at least two hardware resources to that specified in the power control instruction while processing at least one subsequent instruction in the program code; a support register that stores power modes state information for the plurality of hardware resources; and enabling logic coupled to the support register and configured to control the power modes of the plurality of hardware resources responsive to the power modes state information stored in the support register, wherein the processor is configured to selectively set the power modes of the at least two hardware resources by storing the power control information from the power control instruction in the support register.