Patent ID: 7161848

Claim:
A data write circuit of a semiconductor storage device having capability of multi-bit writing for writing data to a plurality of memory cells by one write operation comprising: data latch means for sequentially latching a plurality of data which are sequentially input in accordance with a change of an input multi-bit address so as to be respectively written to the plurality of memory cells; column decode means for respectively applying the plurality of data latched by the data latch means to sources of the plurality of memory cells based on an input column address; and cell drain voltage generation means for applying low cell drain voltage with which data write is disabled to drains of the plurality of memory cells until all of the plurality of data is latched, and for simultaneously applying high cell drain voltage for writing data to the drains of the plurality of memory cells when all of the plurality of data are latched and are applied to the sources of the plurality of memory cells so as to respectively write the plurality of data to the plurality of memory cells.