Patent ID: 7557623

Claim:
A circuit arrangement, in particular a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, characterized by at least one phase measurement unit, in particular comprising at least one time-to-digital converter unit being provided with at least one input signal and at least one phase detector unit being provided with at least one output signal of the time-to-digital converter unit; at least one loop filter unit being provided with at least one output signal of the phase detector unit; at least one digital ramp oscillator unit or discrete time oscillator unit being provided with at least one output signal, in particular with at least one increment, of the loop filter unit, the status signal of at least one register unit of the digital ramp oscillator unit or discrete time oscillator unit being fed back as input signal to the phase detector unit; and at least one digital-to-time converter unit being provided with at least one output signal of the digital ramp oscillator unit or discrete time oscillator unit and generating at least one output signal, wherein the time-to-digital converter unit includes at least two shift register chains configured to process the input signal as an input of the shift register chains.