Patent ID: 6894308

Claim:
An integrated circuit comprising: A. input pads; B. output pads; C. core circuitry coupled between the input pads and the output pads; D. output circuitry coupled between the core circuitry and the output pads, for each output pad the output circuitry including: i. a tri-state buffer having a core input lead connected to a core output lead of the core circuitry, a data output lead connected to an output pad and an enable input lead carrying an enable signal that can place the data output of the tri-state buffer in a high impedance state; and ii. comparator circuitry having a core input lead connected to the core output lead and the core input lead of the tri-state buffer, an expected data input lead connected to the output pad and the data output lead of the tri-state buffer, a mask data input lead connected to another pad, and an enable input lead connected to the enable input lead of the tri-state buffer.