Patent ID: 8644061

Claim:
A variable resistance memory device comprising: a memory cell array comprising a plurality of memory cells; a pulse shifter shifting a plurality of program pulses to generate a plurality of shifted program pulses, wherein the program pulses are for programming a respective plurality of write data bits in the plurality of memory cells; a write and verification driver receiving the plurality of shifted program pulses to provide respective program currents that vary in accordance with the plurality of shifted program pulses to the plurality of memory cells; and control logic providing the plurality of program pulses to the pulse shifter and the write and verification driver during a program/verification operation, such that at least two write data bits among the plurality of write data bits are programmed to the memory cell array in parallel during the program/verification operation, wherein the pulse shifter shifts the program pulses so that the program pulses of respective memory cells of the memory cell array are not synchronized with each other.