Patent ID: 7944000

Claim:
A semiconductor resistor, comprising: a semiconductor substrate; a contiguous well region configured to serve as a resistive region provided in the semiconductor substrate; a pair of contact regions spaced apart from each other, and respectively in contact with the contiguous well region and having the same conductivity type as the contiguous well region; a contact disposed on each of the pair of contact regions; a diffusion region having a specific surface area configured to obtain a corresponding reduced resistance and increased temperature dependence of the contiguous well region, the diffusion region being formed in an intermediate portion between the pair of contact regions on a surface of the contiguous well region; and an isolation layer configured to electrically isolate said diffusion region from said pair of contact regions and the contacts disposed on each of the contact regions, wherein a surface of the semiconductor resistor is planarized, so that an upper surface of the diffusion region, an upper surface of the isolation layer, and an upper surface of the pair of contact regions in contact with the contiguous well region are in planar alignment on the surface of the semiconductor resistor.