Patent ID: 8443177

Claim:
In a microprocessor having an instruction set architecture in which the instructions are variable length, an apparatus for determining bad branch predictions of instruction bytes in a stream of undifferentiated instruction bytes before the instruction bytes are executed, the apparatus comprising: a branch predictor, configured to provide a taken indicator for each instruction byte of the stream, wherein the taken indicator is true if the branch predictor predicted the instruction is the opcode byte of a taken branch instruction; decode logic, configured to: decode the instruction bytes of the stream to generate for each a corresponding opcode byte indictor and end byte indicator; receive the corresponding taken indicator for each of the instruction bytes; generate a corresponding bad prediction indicator for each of the instruction bytes, wherein the bad prediction indicator is true if the corresponding taken indicator is true and the corresponding opcode byte indicator is false; and set to true the bad prediction indicator for each remaining byte of an instruction whose opcode byte has a true bad prediction indicator; and control logic, configured to: extract instructions from the stream and send the extracted instructions for further processing by the microprocessor; but when an instruction has both a true end byte indicator and a true bad prediction indicator, forego sending an instruction and correct the taken indicator that was a bad prediction.