Patent ID: 7598767

Claim:
Programmable logic device integrated circuitry comprising: hard IP circuitry including circuitry for receiving a serial data signal, making a number of successive bits of the serial data signal available in parallel, and selecting aligned bytes of data from the parallel bits; and general-purpose programmable logic circuitry that is configurable, in use, to receive the aligned bytes from the hard IP circuitry and to synchronize the aligned bytes in accordance with communication protocol parameters that are programmed into the programmable logic circuitry, wherein the hard IP circuitry further includes: first circuitry for detecting whether or not an aligned byte corresponds to a valid byte code, second circuitry for applying an output signal of the first circuitry to the programmable logic circuitry, and third circuitry that is selectively responsive to the output signal of the first circuitry for selecting which of the parallel bits will be tried as aligned bytes, and wherein the third circuitry is responsive to a signal from the programmable logic circuitry with regard to how the third circuitry responds to the output signal of the first circuitry, the programmable logic circuitry being configurable to base the signal from the programmable logic circuitry at least in part on processing of the output signal of the first circuitry by the programmable logic circuitry in accordance with communication protocol parameters that are programmed into the programmable logic circuitry.