Patent ID: 8045409

Claim:
A semiconductor memory device comprising: a plurality of memory cells that are arranged at intersections of a word line with bit line pairs; a precharge circuit that is arranged for each of the bit line pairs, the precharge circuit being configured to precharge each of the bit line pairs; and a Y-switch circuit that is arranged for each of the bit line pairs, the Y-switch circuit being configured to select each of the bit line pairs, wherein the semiconductor memory device is configured to execute two modes of a normal mode and a test mode by switching the two modes, the normal mode being a mode that executes reading or writing of normal memory data, the test mode being a mode that is capable of executing long write on a memory cell which is a test target, the semiconductor memory device further comprising: a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied; a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode; and a block control unit that turns off all of the precharge circuits by a command by a block selection signal in the test mode.