Patent ID: 7213169

Claim:
An symmetric multiprocessor (SMP) system having an apparatus for performing bus tracing, said SMP system comprising: an interconnect; a plurality of memory modules that form a total system memory of said SMP system; and a plurality of substantially identical processing units coupled to said interconnect, wherein more than one of said processing units include: a memory controller coupled to one of said memory modules; a plurality of multiplexors; a bus trace macro (BTM) module connected between said interconnect and said memory controller via said plurality of multiplexors located externally from said BTM module, wherein said BTM module selectively intercepts address transactions from said interconnect converts said intercepted address transactions to corresponding trace records, and writes said trace records to a write buffer within said memory controller; a dropped record counter for counting the number of address transactions not converted to trace records due to said write buffer being full; and means for inserting a lime stamp trace record before writing a new trace record after an occurrence of said write buffer being full, wherein said time stamp trace record includes a count of said number of address transactions not converted to trace records.