Patent ID: 6967395

Claim:
A semiconductor package comprising: a die pad having opposed, generally planar first and second surfaces, and peripheral side surfaces which extend between the first and second surfaces; a plurality of leads extending at least partially about the die pad in spaced relation to the side surfaces thereof, each of the leads having: opposed, generally planar first and second surfaces; peripheral side surfaces extending between the first and second surfaces; an inner lead portion defining an inner end surface; and an outer lead portion, a portion of the first surface defined by the outer lead portion being sized and configured for electrical connection to a conductive terminal; a semiconductor chip including an active surface having a plurality of conductive bond pads thereon, a portion of the active surface being attached to the first surface of the die pad, with the semiconductor chip and the leads being sized and oriented relative to each other such that each of the bond pads at least partially overlaps and is electrically connected to the first surface of a respective one of the leads; and a package body at least partially encapsulating the semiconductor chip, the die pad, and the leads such that the inner lead portion of each of the leads is within the package body and the outer lead portion of each of the leads extends out of the package body.