Patent ID: 7320047

Claim:
A system comprising: a controller device; a first plurality of signal lines coupled to the controller device; an integrated circuit buffer device coupled to the first plurality of signal lines, the integrated circuit buffer device to communicate with the controller device using the first plurality of signal lines; a first memory device; a second plurality of signal lines coupled to the first memory device and the integrated circuit buffer device, the second plurality of signal lines to carry first address information from the integrated circuit buffer device to the first memory device; a third plurality of signal lines coupled to the first memory device and the integrated circuit buffer device, the third plurality of signal lines to carry first control information from the integrated circuit buffer device to the first memory device; a first signal line coupled to the first memory device and the integrated circuit buffer device, the first signal line to carry a first signal from the integrated circuit buffer device to the first memory device, the first signal to synchronize communication of the first control information from the integrated circuit buffer device to the first memory device; a second memory device; a fourth plurality of signal lines coupled to the second memory device and the integrated circuit buffer device, the fourth plurality of signal lines to carry second address information from the integrated circuit device to the second memory device; a fifth plurality of signal lines coupled to the second memory device and the integrated circuit buffer device, the fifth plurality of signal lines to carry second control information from the integrated circuit buffer device to the second memory device; and a second signal line coupled to the second memory device and the integrated circuit buffer device, the second signal line to carry a second signal from the integrated circuit buffer device to the second memory device, the second signal to synchronize communication of the second control information from the integrated circuit buffer device to the second memory device.