Patent ID: 7443432

Claim:
A pixel array, comprising: a number of active pixel circuits arranged in an array of rows and columns of active pixel circuits, wherein each said active pixel circuit has a photo detector and communicates electrically with a power supply; a first dummy pixel circuit for each said row of active pixel circuits, wherein each said first dummy pixel circuit does not have a photo detector and communicates electrically with said power supply; a second dummy pixel circuit for each said row of active pixel circuits wherein each said second dummy pixel circuit does not have a photo detector and communicates electrically with said power supply; a column storage register for each said column of active pixel circuits wherein each said column storage register is connected to all of said active pixel circuits in that said column of active pixel circuits; a first dummy storage register, wherein each of said first dummy pixel circuits are connected to said first dummy storage register; a second dummy storage register, wherein each of said second dummy pixel circuits are connected to said second dummy storage register; a reset line for each of said rows of active pixel circuits wherein one of said reset lines is connected to each said active pixel circuit and said first dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of said pixel circuits selected for reset is reset and said first dummy pixel in said row of active pixel circuits selected for reset stores a signal in said first dummy storage register related to the value of the voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for reset are reset; a row select line for each of said rows of active pixel circuits wherein one of said row select lines is connected to each said active pixel circuit and said second dummy pixel in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of pixel circuits selected for readout is read and stores a signal in that said column register for the same said column of active pixel circuits and said second dummy pixel in said row of pixel circuits selected for readout stores a signal in said second dummy register related to the value of said voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for readout are read; means for determining the difference between said signal stored in said first dummy register and said signal stored in said second dummy register; and means for correcting said signals stored in each of said column storage registers for fluctuations of said voltage of said power supply using said difference between said signal stored in said first dummy register and said signal stored in said second dummy register.