Patent ID: 7271087

Claim:
A method for forming a dual damascene interconnection in a semiconductor device, comprising the steps of: forming an etch stop film and an intermetal insulating film sequentially on a lower metal interconnection film, said intermetal insulating film being formed with a FSG film; forming a via hole so as to expose the etch stop film on the intermetal insulating film by performing an etching process using a mask pattern for via hole formation; forming a trench by performing an etching process using a mask pattern for trench formation; forming an insulating film on an exposed surface of the etch stop film and a surface of the intermetal insulating film; forming first and second insulative spacer films with a USG material on sidewalls of the via hole and the trench, respectively, by performing an etching process for the insulating film, and exposing a portion of the etch stop film; exposing the lower metal interconnection film by removing the exposed portion of the etch stop film; forming a barrier metal layer on the first and second insulative spacer films; and forming an upper metal interconnection film on the barrier metal layer, the via hole and the trench being filled with the upper metal interconnection film.