Patent ID: 7133943

Claim:
An I/O adapter for a packet-switched network, comprising: a buffer memory; a packet disassembler receiving request packets from a requester over said network and building blocks from said packets in queues in said buffer memory, said request packets including packets of a first type requesting that data be sent to the requester and packets of a second type containing data sent by the requester; wherein said packet disassembler places blocks from packets of said first type in a first queue and blocks from packets of said second type in a second queue; wherein said packet disassembler detects an out-of-sequence packet and, responsive thereto, builds a negative acknowledge (NAK) block in said first queue; a control memory for containing state data, said state data including a plurality of queue pointers, said queue pointers pointing to locations in said first and second queues; a receive queue sequencer, said receive queue sequencer determining when to send acknowledgment packets to said requester from said state data in said control memory, wherein packets are acknowledged in the order received; and a packet builder which builds and sends acknowledge packets responsive to said receive queue sequencer.