Patent ID: 6982907

Claim:
A method of programming a non-volatile memory (NVM) cell, the NVM cell including a drain region having a first conductivity type formed in a semiconductor substrate having a second conductivity type opposite the first conductivity type, a source region having the first conductivity type formed in the semiconductor substrate and spaced apart from the drain region to define a substrate channel region therebetween, a layer of gate dielectric material formed over the channel region, a conductive floating gate formed on the layer of gate dielectric material, and a conductive control gate formed over the floating gate and electrically insulated therefrom by intervening dielectric material, the method comprising: raising the potential of the drain region to a first preselected potential above the potential of the source region; performing a programming step by applying a first programming potential to the control gate to facilitate the flow of electrons to the floating gate; repeating the programming step for a plurality of programming cycles with a time interval between cycles long enough to redistribute charge in the dielectric layers surrounding the floating gate and until the electric field from outside the floating gate is substantially zero.