Patent ID: 8072804

Claim:
A non-volatile memory device, comprising: a block of non-volatile memory cells configured to support single bit and multi-bit programming states, said block of non-volatile memory cells comprising a plurality of even rows of non-volatile memory cells and a plurality of odd rows of non-volatile memory cells interleaved between the plurality of even rows of non-volatile memory cells in an alternating even row and odd row sequence; and a control circuit configured to distribute cell-to-cell capacitive coupling stress across said block of non-volatile memory cells by swapping the M-bit capacities of the non-volatile memory cells in the plurality of even rows with the N-bit capacities of the non-volatile memory cells in the plurality of odd rows and vice versa in response to each operation to erase said block of non-volatile memory cells, where M and N are unequal integers greater than zero.