Patent ID: 8301033

Claim:
An LD driver to generate a driving current with a falling edge faster than a leading edge thereof, comprising: a delay unit configured to receive an input signal to output a delayed signal delayed by a variable period with respect to said input signal; a primary driver configured to convert one of said input signal and said delayed signal to a primary current by a first conversion ratio; and a sub-driver connected in parallel to said primary driver, said sub-driver including a symmetrical driver and an asymmetrical driver, wherein said symmetrical driver converting one of said delayed signal and said input signal into a symmetrical current by a second conversion ratio, wherein said asymmetrical driver including two arithmetic units, each carrying out an OR operation between said input signal and said delayed signal and converting a result of said OR operation into an asymmetrical current by a third conversion ratio, wherein said LD driver outputs said driving current by adding said primary current, said symmetrical current and said asymmetrical current.