Patent ID: 7116737

Claim:
Apparatus ( 100 ) for signaling that a predetermined time value has elapsed, having: a device ( 102 ) for acquiring and storing the amplitude value (SH) of a clock signal (CLK; CLK 1 , CLK 2 ) at an acquisition instant (t 0 ) in the temporal profile of the clock signal (CLK; CLK 1 , CLK 2 ), the clock signal (CLK; CLK 1 , CLK 2 ) having, during a period (T) thereof, a monotonically rising section and a monotonically falling section; a device ( 116 ) for continuously comparing the acquired and stored amplitude value (SH) of the clock signal (CLK; CLK 1 , CLK 2 ) with an instantaneous amplitude value of the clock signal (CLK; CLK 1 , CLK 2 ) and for outputting a comparison signal (COMP), which has a first logic state if the instantaneous amplitude value of the clock signal (CLK; CLK 1 , CLK 2 ) is less than the stored amplitude value (SH) of the clock signal (CLK; CLK 1 , CLK 2 ), and has a second logic state if the instantaneous amplitude value of the clock signal (CLK; CLK 1 , CLK 2 ) is greater than the stored amplitude value (SH) of the clock signal (CLK; CLK 1 , CLK 2 ); and a device ( 124 ) for counting the number of logic states of the comparison signal (COMP) which occur after the acquisition instant (t 0 ), and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.