Patent ID: 8201060

Claim:
A method for error correction, comprising: receiving by a processor of a Reed-Solomon codeword of n-state symbols with n>2 containing a plurality of n-state data symbols and a plurality of n-state check symbols, an n-state symbol being represented by a signal; the processor determining a plurality of comparative coding states of a coder enabled to determine the plurality of n-state check symbols, each comparative coding state of the plurality of comparative coding states being determined by combining one of a first plurality of intermediate coding states of the coder with a corresponding one of a second plurality of intermediate coding states of the coder, wherein each of the first plurality of intermediate coding states is a state of the coder being operated from a first initial state towards a first final state and each of the second plurality of intermediate coding states is a state of the coder being operated from a second final state towards a second initial state; the processor locating a symbol in error in the Reed-Solomon codeword based on the plurality of comparative coding states; and the processor determining a correct state for the symbol in error in the Reed-Solomon codeword.