Patent ID: 8271840

Claim:
A circuit comprising: A. combinational logic; B. scan paths having leads connected to the combinational logic that carry stimulus signals and response signals, there being a first scan path, intermediate scan paths, and a last scan path, each scan path having a serial scan data input, a serial scan data output, a scan enable input, and a scan clock input; C. a serial data output lead connected to the serial scan data output of the last scan path; D. a serial data input lead; E a serial mode input lead; F. one scan data input lead for each scan path; and G. one multiplexer circuit for each scan path, each multiplexer circuit having a control lead connected to the serial mode input lead: i. a first multiplexer having one input connected to the serial data input lead, another input connected to a scan data input lead, and an output connected to the serial scan data input of the first scan path; and ii. the remaining multiplexers having one input connected to the serial scan data output of a preceding scan path, another input connected to a scan data input lead, and an output connected to a serial scan data input of an intermediate scan path and the last scan path.