Patent ID: 8878564

Claim:
A device comprising: an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit; and a first terminal configured to be coupled to an external resistor, and wherein the impedance adjustment part includes: an impedance adjustment circuit operable to generate a first impedance adjustment signal in response to a resistance of the external resistor; and a correction circuit receiving the first impedance adjustment signal and operable to perform a correction for the first impedance adjustment signal to generate a second impedance adjustment signal, the correction corresponding to the number of the unit buffers that are selectively activated by the controller circuit, and supplying the second impedance adjustment signal to the unit buffers to adjust the impedance of each of the unit buffers.