Patent ID: 8008126

Claim:
A method for packaging and stacking integrated circuit chips, each of the integrated circuit chips having active circuit areas, the method comprising: providing a wafer comprising first and second integrated circuit chips; placing a plurality of first electrical contacts large enough to be electrically coupled to solder, anisotropic conductive film, or anisotropic conductive paste on the wafer between the first and second chips; encapsulating the first electrical contacts with a material, wherein the material exposes a surface of the first electrical contacts; coupling an active circuit area of the first chip to the surface of one of the first electrical contacts with a second electrical contact; coupling an active circuit area of the second chip to the surface of one of the first electrical contacts with a third electrical contact; cutting the wafer through the material and first electrical contacts between the first and second chips to separate the wafer into a first wafer portion and a second wafer portion, the first wafer portion including the first integrated circuit chip and the second wafer portion including the second integrated circuit chip, the cutting exposing at least a second surface of the cut first electrical contacts; and stacking the first wafer portion over the second wafer portion such that the active circuit area of the first integrated circuit chip is in a plane substantially parallel to the active circuit area of the second integrated circuit chip.