Patent ID: 7208795

Claim:
A memory transistor comprising: a first sinker dopant region and a second sinker dopant region formed in a substrate, the first sinker dopant region being separate from the second sinker dopant region, wherein a distance between the first and second sinker dopant regions is sufficient to electrically isolate the first and second sinker dopant regions from each other and to yield a breakdown voltage of greater than or approximately equal to 10 Volts; a tunnel oxide region formed over the first sinker dopant region; a coupling capacitor oxide region formed over the second sinker dopant region; and a floating gate formed proximate to both the first and second sinker dopant regions, the floating gate having a tunnel diode window region over the tunnel oxide region and separated from the first sinker dopant by the tunnel oxide, the floating gate having a coupling capacitor region over the coupling capacitor oxide region and separated from the second sinker dopant by the coupling capacitor oxide.