Patent ID: 6879630

Claim:
An automatic equalization circuit for receiving a digital training signal and a digital data signal and outputting a digital data signal equalized, comprising; a first automatic equalization unit including a first equalizer, to which said digital training signal and a digital data signal are applied, for equalizing said digital data signal; a memory for storing said digital training signal; a second automatic equalization unit coupled with said memory, for outputting an updating signal therefrom, said second automatic equalization unit comprising a second equalizer for outputting said updating signal, a training signal generator for outputting an either one of an in-phase component and a quadrature component signals of a training signal, the other one of which is zero, and a tap coefficient calculating unit coupled with said second equalizer, for outputting a tap coefficient value in comparison with said digital training signal from said memory and an output from said training signal generator and updating the tap coefficient of said second equalizer; and a phase rotator for rotating a phase of either one of an input signal and an output signal of said first automatic equalization unit, said digital training signal supplied to said memory and said updating signal outputted from said second equalizer, wherein said updating signal from said second equalizer is supplied to said first equalizer, so that a equalization characteristic of said first equalizer is updated.