Patent ID: 8286027

Claim:
An input/output (I/O) device comprising: a host interface configured to receive and process a plurality of transaction packets sent by a plurality of processing units, each processing unit corresponding to a respective root complex; wherein the host interface includes an error handling unit having error logic configured to, as the transaction packets are received, determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage including a plurality of entries according to which processing unit and to which function of a plurality of functions each packet is associated; wherein a given entry of a first portion of the plurality of entries corresponds to a respective function of the plurality of functions, and wherein a given entry of a second portion of the plurality of entries corresponds to a processor hierarchy associated with a respective processing unit; wherein the error handling unit also includes: an error processor configured to execute error processing instructions to access each entry of the storage that includes the information corresponding to any detected errors to determine any error processing operations based upon the information, and to generate and send one or more instruction operations, each corresponding to a particular error processing operation; an error processing unit configured to execute the one or more instruction operations to perform the particular error processing operations.