Patent ID: 7453277

Claim:
A wafer-level burn-in assembly, comprising: a circuit board having a first major surface and a second major surface; a first plurality of contact pads disposed in a first area of the first major surface of the circuit board, the first plurality of contact pads arranged in first pattern; a guide ring disposed on the first major surface of the circuit board such that the guide ring is outside the first area; a wafer burn-in socket having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a second pattern that matches the first pattern, the second major surface having a plurality of contact pads arranged in a third pattern, the first major surface of the wafer burn-in socket disposed on the circuit board; a wafer translator having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a fourth pattern that matches the third pattern, the first major surface of the wafer translator disposed on the wafer burn-in socket; a wafer attached to the second major surface of the wafer translator; a heat spreader disposed against a side of the wafer facing away from the translator; and a cover disposed over the heat spreader.