Patent ID: 7569896

Claim:
A semiconductor structure comprising: a substrate; a gate over the substrate; a channel region in the substrate and directly underlying the gate; a non-silicide region of the substrate not directly underlying the gate, wherein the non-silicide region adjoins the channel region; a source/drain region comprising a recess in the substrate, wherein the source/drain region comprises: a first source/drain extension region; a second source/drain extension region further from the gate than the first source/drain extension region; and a deep source/drain region further from the gate than the second source/drain extension region; and a silicide region on the source/drain region, wherein the silicide region has a top surface comprising a lower portion, and a higher portion between the lower portion and the non-silicide region, the lower portion having a top surface lower than a top surface of the higher portion by a step height, wherein a width of the non-silicide region and the step height have a ratio of less than or equal to about 3.