Patent ID: 6998715

Claim:
An electronic component comprising: a board; a semiconductor device comprising a plurality of first lands formed in a grid and electrically connected to corresponding second lands formed on the board, wherein a subset of the second lands corresponding to first lands in a corner portion or end portion of the grid each comprise a primary land and an auxiliary land, each of the subset of second lands connect to a wire of the board, the primary land comprises an arcuate shape, and the auxiliary land comprises a first portion disposed adjacent the primary land and a second portion connecting to the wire, the first portion having a greater cross sectional area than the second portion, and wherein (a) the connecting wire for each land of the subset of second lands comprises a via land, the via land including an arcuate portion electrically connected to a via hole formed in the board outside of the footprint of the grid of the semiconductor device and (b) a predetermined tensile stress is configured to be applied between the subset of second lands and their respective connecting wires.