Patent ID: 8531006

Claim:
A memory capacitor device, comprising: an Al bottom electode; a Al/Ti top electrode; and a field configurable ion-doped material between said electrodes; wherein the device has a nonvolatile capacitance that is modifiable to arbitrary analog values as a function of voltage bias applied to the top and bottom electrodes; wherein said first electrode, said second electrode, and said field configurable ion-doped material between said electrodes comprise layers in a multilayer structure; said multilayer structure comprising: the Al bottom electrode; a p-type Si layer over the Al bottom electrode; a SiO 2 insulating layer over the p-type Si layer; a conjugated polymer layer of poly[2-methoxy-5-(2′-ethylhexyloxy)-p-phenylene vinylene] (MEH-PPV) over the SiO 2 insulating layer; a RbAg 4 I 5 ionic conductive layer over the MEH-PPV layer; and the AL/Ti top electrode over the ionic conductive layer.