Patent ID: 7502943

Claim:
An apparatus for performing cryptographic operations, comprising: an x86-compatible microprocessor: a control word, configured to prescribe that an intermediate result be generated during execution of one of the cryptographic operations, wherein said control word is stored in memory, and wherein a memory location of said control word is prescribed by contents of a register that is referenced by a single atomic cryptographic instruction, wherein said single atomic cryptographic intruction is arranged according to the instruction format for execution on said x86compatible microprocessor; fetch logic, disposed within said x86-compatible microprocessor, configured to receive said single atomic cryptographic instruction as part of an instruction flow executing on said x86-compatible microprocessor, wherein said single atomic cryptographic instruction prescribes said one of the cryptographic operations, and wherein said single atomic cryptographic instruction references said control word; translation logic, coupled to said fetch logic and disposed within said x86-compatible microprocessor, configured to translate said single atomic cryptographic instruction into a sequence of micro instructions that directs said x86-compatible microprocessor to perform said one of the cryptographic operations; and execution logic, disposed within said x86-compatible microprocessor and operatively coupled to said single atomic cryptographic instruction, configured to execute said one of the cryptographic operations, and configured to generate said intermediate result, wherein said execution logic comprises: a cryptography unit, configured to execute a plurality of cryptographic rounds on each of one or more input text blocks to generate a corresponding each of one or more output text blocks, wherein said plurality of cryptographic rounds are prescribed by a round count field within said control word.