Patent ID: 7710695

Claim:
An integrated circuit capable of protecting against electrostatic discharge (ESD) damage, comprising: a first pad; a ground pad; a second pad; a device circuitry; a discharging unit, coupled to the device circuitry, and the first, second and ground pad, comprising a first and a second transistor in series to protect the device circuitry from a stress current at the first, second, or ground pad in an ESD event; and a discharging controller, coupled to the discharging unit, and the first, second and ground pad, comprising: an ESD connection unit, coupled to the first pad and the second pad, receiving an ESD pulse to establish a first control voltage to turn on the first transistor in the ESD event; and a voltage clamping unit, coupled to the ESD connection unit and the first, second and ground pad, clamping the ESD pulse to establish a second control voltage to turn on the second transistor in the ESD event, and receiving an operation voltage at the second pad to turn off the second transistor in normal operation, wherein the voltage clamping unit comprises an inverter comprising a third and a fourth transistor in series, the third transistor is coupled to the first pad and the fourth transistor, and the fourth transistor is coupled to the ground pad and the third transistor; wherein the discharging controller further comprises a fifth transistor coupled to the ESD connection unit, the second pad, and the first resistor; and wherein combination of threshold voltages of the third and the fifth transistor is less than zero volts.