Patent ID: 8237687

Claim:
A display device comprising: a display comprising: a pixel portion; and a signal line driver circuit electrically connected to the pixel portion; a display controller comprising: a first clock generator circuit for generating a first clock signal; a second clock generator circuit for supplying a second clock signal to the signal line driver circuit; and a first variable frequency divider circuit for changing a frequency of the first clock signal among at least two display modes, according to a gray scale control signal, and for supplying the changed first clock signal to the second clock generator circuit; and a signal control circuit comprising: a first memory electrically connected to the signal line driver circuit; a second memory electrically connected to the signal line driver circuit; and a memory controller comprising: a decoder for selecting an address of the first memory and the second memory; an oscillator circuit for generating a selecting signal; and a second variable frequency divider circuit for changing a frequency of the selecting signal according to at least two display modes, and for supplying the changed selecting signal to the decoder, wherein the memory controller is configured to control reading out from the first memory while simultaneously writing in the second memory.