Patent ID: 7031345

Claim:
An IDSL line card comprising: at least one IDSL line interface having an adjustable bit rate comprising: a microcontroller operable to control the bit rate associated with the at least one line interface, the microcontroller comprising: a processor; and a memory associated with the processor and storing a rate adapter application, the rate adapter application operable, when executed on the processor, to: receive an error level associated with transfer of data through the at least one IDSL line interface to a second IDSL line interface, the second IDSL line having a second bit rate; determine that the received error level exceeds a maximum error level; and in response to determining that the maximum error level is exceeded, adjust the bit rate for the at least one IDSL line interface while the second bit rate for the second IDSL interface remains constant and determine that a resulting error level meets or falls below the maximum error level.