Patent ID: 7663426

Claim:
A power up biasing circuit for a split power supply based circuit comprising: a split power supply state sensing circuit comprising a plurality of inputs operative to receive at least a first power supply voltage, a second power supply voltage that is lower than the first power supply voltage and a pseudo power supply voltage wherein the pseudo power supply voltage is based on the first power supply voltage, and operative to produce a pair of complementary control signals indicating a presence or absence of the second power supply voltage; a bias selector circuit, operatively coupled to the split power supply state sensing circuit, having at least a first input operatively coupled to the second power supply voltage and a second input operatively coupled to the pseudo power supply voltage and at least one output operative to output either the second power supply voltage or the pseudo power supply voltage based on the pair of complementary control signals; and wherein the split power supply sensing circuit comprises: a first PMOS transistor having a gate, source and bulk coupled to receive the second supply voltage, and drain operative to provide a first of the complementary control signals; a first NMOS transistor having a gate and drain operatively coupled to the gate of the first PMOS transistor and a source and bulk operatively coupled to receive a ground voltage potential; a second NMOS transistor having a drain operatively coupled to the drain of the first PMOS transistor, a gate operative to provide a second of the complementary control signals and a source and bulk operatively coupled to each other; second PMOS transistor having a source operative to receive the pseudo power supply voltage, a bulk operatively coupled to receive the first power supply voltage, a drain operatively coupled to the gate of the second NMOS transistor, and a gate operatively coupled to the drain of the first PMOS transistor; a third NMOS transistor having a gate operatively coupled to the gate of the second PMOS transistor, a drain operatively coupled to the drain of the second PMOS transistor and a source and bulk operatively coupled to each other.