Patent ID: 8129835

Claim:
A package substrate having a semiconductor component embedded therein, comprising: a substrate body having at least an opening; a semiconductor chip fixed in position to the opening of a substrate body and having an active surface with a plurality of electrode pads thereon and an opposing inactive surface, wherein a passivation layer is disposed on the active surface, the passivation layer having a plurality of passivation layer openings corresponding in position to the electrode pads, respectively; a plurality of metal rings disposed on the passivation layer openings; a first dielectric layer disposed on the substrate body, the passivation layer, and the metal rings, wherein a plurality of dielectric layer openings corresponding in position to the electrode pads, respectively, are formed to penetrate the first dielectric layer and expose the electrode pads therefrom; and a first wiring layer disposed on the first dielectric layer and electrically connected to the electrode pads by a plurality of first conductive vias formed in the dielectric layer openings and passivation layer openings, respectively, and configured to be in contact with the metal rings, respectively.