Patent ID: 7526702

Claim:
A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, and the RAM device coupled to an external bus that provides data from a plurality of addresses to both the internal cache and the memory array, the method comprising the following steps: writing a first value to a first address in the RAM device, the first value being stored in the internal cache, the first value corresponding to at least one line of the external bus; writing a number of additional values to addresses in the RAM device other than the first address to fill the internal cache and thereby push the first value from the internal cache into the first address in the memory array; reading a second value from the first address of the memory array; determining whether the internal bus is faulty by comparing the first value written to the internal cache to the second value read from the memory array; and reporting an error when the first value is not equal to the second value.