Patent ID: 8248283

Claim:
An apparatus comprising: a multiplexer having: a plurality of input terminals; an output terminal; a plurality of selection switches, wherein each selection switch is coupled to at least one of the input terminals of the multiplexer; a plurality of boost circuit, wherein each boost circuit is coupled in parallel to at least one of the selection switches; a plurality of sample-and-hold (S/H) circuits, wherein each S/H is coupled to at least two of the selection switches, and wherein each S/H circuit is coupled to the output terminal of the multiplexer; a capacitive digital-to-analog converter (CDAC) that is coupled to the output terminal of the multiplexer; a comparison circuit that is coupled to the CDAC; successive approximation register (SAR) logic that is coupled to the comparison circuit and the CDAC, wherein the SAR logic control switching of the CDAC; and a controller that is coupled to the multiplexer so as to perform channel selection for the multiplexer.