Patent ID: 7655525

Claim:
A method of fabricating a semiconductor device, the method comprising: forming isolation regions in a substrate; forming a gate pattern on the substrate; forming an L-type spacer layer which covers an upper region and sidewall of the gate pattern; forming a gate spacer layer on the L-type spacer layer; forming an L-type spacer on the sidewall of the gate pattern and extended to the substrate and a gate spacer by patterning the L-type spacer layer and the gate spacer layer, and simultaneously exposing a surface of the substrate between the gate spacer and the isolation regions; forming a source/drain silicide region on the exposed substrate; forming a sacrificial metal layer on the source/drain silicide region; removing the gate spacer; removing the sacrificial metal layer; forming an interlayer dielectric layer which covers the gate pattern and the source/drain silicide region; and forming via plugs electrically connected with the source/drain silicide region by vertically penetrating the interlayer dielectric layer.