Patent ID: 8080832

Claim:
A semiconductor electrostatic discharge (ESD) protection device comprising: a substrate having an upper portion and a lower portion; a first well and a second well formed in the upper portion of the substrate; a natively doped region in the upper portion of the substrate, between the first well and the second well, having substantially the same doping as the lower portion of the substrate; a discharge circuit formed in the first well to create a discharge path for the electrostatic current generated during an ESD event; and an ESD voltage trigger consisting of the natively doped region provided between the first well and the second well, the natively doped region having a resistance at least about 10 times higher than the resistance of the first and second wells such that when current passes through during the ESD event, a voltage across the ESD voltage trigger triggers the discharge circuit, the voltage being proportional to a width of the natively doped region; the substrate, the natively doped region and the first and second wells being of a first connectivity type, and the substrate and the natively doped region having substantially the same doping.