Patent ID: 8291002

Claim:
A data processing apparatus, comprising: processing circuitry responsive to data processing instructions to execute data processing operations; a register file having a set of registers for storing data values for processing by the processing circuitry; first shift circuitry arranged to receive a data value from the register file and responsive to a first control signal indicating a first shift amount S 1 of between zero and n bit positions to generate a first shifted data value by shifting bit values within the received data value by the first shift amount S 1 , where n is a predetermined integer; selection circuitry responsive to a second control signal to select between the first shifted data value and a load data value received from a memory; and second shift circuitry arranged to receive the data value selected by the selection circuitry and responsive to a third control signal indicating a second shift amount S 2 of aÃ—(n+1) bit positions to generate a second shifted data value by shifting bit values within the received selected data value by the second shift amount S 2 , where a is zero or an integer, and to output the second shifted data value to the register file.