Patent ID: 8438514

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; an integrated circuit design residing in the memory, the integrated circuit design comprising a plurality of user assertions that each define a performance target for the integrated circuit design, the plurality of user assertions including a first user assertion that references a first clock and a second user assertion that references a second clock, wherein the first clock is a real clock in the integrated circuit design and the second clock does not correspond to a real clock in the integrated circuit design; a clock alias mechanism that creates a clock alias that correlates the second clock to the first clock; and a timing analysis mechanism that performs the steps of: (A) reading the plurality of user assertions for the integrated circuit design from the memory; (B) reading the clock alias that correlates the second clock to the first clock; (C) selecting a user assertion that references the clock alias; (D) determining whether a duplicate clock for the clock alias exists in a timing database in the integrated circuit design; (E) when a duplicate clock for the clock alias does not exist in the timing database, automatically generating the duplicate clock for the clock alias in the timing database that mimics the first clock; (F) generating a new user assertion for the first clock based on the user assertion selected in step (C); (G) when all assertions that reference any clock alias have been processed in steps (B) through (F), processing the plurality of user assertions read in step (A) and processing all new user assertions generated in step (F).