Patent ID: 8803555

Claim:
An address decode circuit comprising: a first decoder circuit configured to partition an N-bit address of an addressable element into at least three address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit including a corresponding plurality of one-hot decoders and a corresponding plurality of sets of decode lines, each set of decode lines coupled to a respective one of the plurality of one-hot decoders, wherein the first decoder circuit is configured to first-stage decode the at least three address segments into the plurality of sets of decode lines using the plurality of one-hot decoders, each one-hot decoder configured to receive and decode one of the at least three address segments, to provide a plurality of first-stage decoded address outputs from the N-bit address, wherein only one of the plurality of first-stage decoded address outputs is enabled at any given time; and a second orthogonal decoder circuit coupled to the plurality of sets of decode lines and configured to receive the plurality of first-stage decoded address outputs and to produce 2 N unique decoded addresses at 2 N address outputs from unique combinations of the plurality of first-stage decoded address outputs, each one of the 2 N address outputs corresponding to one unique decoded address within the addressable element derived from the N-bit address.