Patent ID: 8278174

Claim:
A method, comprising: forming cavities in an active region of a transistor laterally adjacent to a gate electrode structure, said gate electrode structure comprising a gate dielectric material, an electrode material formed on said gate dielectric material and an offset sidewall spacer; introducing at least one further dopant species into said active region through said cavities to form source and drain regions extending to at least a buried insulating layer below the active region; forming a strain-inducing semiconductor alloy in said cavities after introducing said at least one further dopant species into said active region, said strain-inducing semiconductor alloy comprising a dopant species having a varying dopant concentration along a height direction of said cavities; and performing a heat treatment to form drain and source extension regions on the basis of said varying dopant concentration of said dopant species, said drain and source extension regions connecting to a channel region of said transistor.