Patent ID: 8895436

Claim:
A method for implementing enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas includes a method of contacting one or more metal wiring layers on a semiconductor chip comprising: providing a first wiring level in the TSV exclusion zone area having a first wiring shape having a hole of a first diameter; providing a second hole in a dielectric above the first wiring level having a second diameter, the second hole being concentric with the first hole, and the second diameter being larger than the first diameter; etching a via hole passing through the first and second holes; performing an anisotropic oxide etch to expose a top surface portion of the first wiring shape and a top surface portion of the second wiring shape; growing a thin oxide over the via hole; performing an anisotropic etch to remove horizontal portions of the thin oxide, exposing wiring shapes; filling the via hole with a conducting material to make electrical connection to the exposed wiring shapes; said conducting material filled via electrically connected to a selected one of voltage supply rail VDD and voltage supply rail ground GND potential; and selectively encircling the filled via hole with wire loops connected to a selected one of voltage supply rail VDD and voltage supply rail ground GND potential based upon power attributes of the filled via hole.