Patent ID: 8683397

Claim:
A method of designing a semiconductor chip, the method comprising the steps of: preparing a plurality of EMS (Electro Magnetic Susceptibility) shielding circuits for inhibiting EMS emitted from an input in of the semiconductor chip, in a form of a plurality of EMS semiconductor IPs (Intellectual Property), preparing a plurality of EMI (Electro Magnetic Interference) shielding circuits for inhibiting EMI emitted through an output in of the semiconductor chip, in a form of a plurality of EMI semiconductor IPs, and storing the prepared plurality of EMS and EMI semiconductor IPs; performing an EMC (Electro Magnetic Compatibility) simulation of the whole semiconductor IP and outputting results by a plurality of control signals, wherein the EMC simulation includes both EMI simulation and EMS simulation; selecting, using a computing device, a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs for the input pin based on a EMS simulation result indicated by the control signals, and selecting, using the computing device, a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs for the output pin based on a EMI simulation result indicated by the control signals; and designing, using the computing device, the semiconductor chip by disposing the selected semiconductor IPs.