Patent ID: 6876203

Claim:
A system for detecting and locating parallel arc faults in a set of wires, at least, a parallel arc fault being defined as a condition in which wires in the set of wires are close enough to produce an arc, the arc being capable of producing an incident waveform and a reflected waveform, the two waveforms together forming a pulse that has a width, the system comprising: a first device that includes: a controller for receiving information and for processing the information to produce a number of control signals; a current source having a first terminal coupled to a first node and a second terminal coupled to ground, the current source being controlled by the controller to produce a direct current so as to charge a capacitance up to the testing voltage, the capacitance being defined between a wire under test and the remaining wires of the set of wires; a timing circuit interfaced to the controller, the timing circuit having a first terminal coupled to the first node and a second terminal coupled to ground, the timing circuit being receptive to the incident waveform and the reflected waveform at the first terminal so as to measure the width of the pulse, the width being approximately proportional to the distance from the device to the arc; a sequencer for coupling the wire under test to the first node while grounding the remaining wires of the set of wires, the sequencer defining the wire under test as a previous wire under test when the device cannot detect the arc on the wire under test, the sequencer being adapted to choose another wire of the remaining wires of the set of wires and define the another wire as the wire under test while grounding the previous wire under test and the remaining wires; and a reflection minimizer interposed between the sequencer and at least one wire from the remaining set of wires, the reflection minimizer being capable of minimizing the attenuation of the amplitude of the pulse.