Patent ID: 7529989

Claim:
A testing apparatus for testing a memory under test, comprising: a pattern generator for generating an address signal and a data signal to be provided to the memory under test, and an expected value signal indicating an expected value that the memory under test outputs in a normal state, according to the address signal and the data signal; a logic comparator for comparing an output signal outputted by the memory under test according to the address signal and the data signal with the expected value signal and outputting fail data when the output signal is not matched with the expected value signal, the fail data comprising a first fail data from a first test of the memory under test, a second fail data from a second test of the memory under test, and a third fail data from a third test of the memory under test; a first fail buffer memory for storing the first fail data on an address indicated by the address signal; a second fail buffer memory for accumulating the first fail data stored in the first fail buffer memory and the second fail data and storing the first and second fail data; a fail data transmitting section for receiving the fail data from the logic comparator and one of the fail data stored in the first fail buffer memory and the fail data stored in the second fail buffer memory, performing an operation based on the received fail data, and providing a result of the operation to the first fail buffer memory or the second fail buffer memory; and a first safe analysis section for performing a fail safe analysis on the memory under test with reference to the first fail data stored in the first fail buffer memory, wherein the first fail buffer memory accumulates the first and second fail data stored in the second fail buffer memory and the third fail data and stores the first second and third fail data, and the first safe analysis section performs a fail safe analysis on the memory under test further with reference to the first and second fail data stored in the second fail buffer memory.