Patent ID: 7328505

Claim:
A method for manufacturing a multilayer circuit board comprising steps of: stacking a plurality of single-sided conductor layer films to form a stacked body including the single-sided conductor layer films, wherein each single-sided conductor layer film includes: a resin film made of thermoplastic resin; and a plurality of conductor layers, which are located only on one surface of the resin film, wherein at least one of the single-sided conductor layer films includes: a plurality of via-holes; and an interlayer connecting material, which is packed in the via-holes and is in contact with the conductor layers, wherein the single-sided conductor layer films are stacked such that the surfaces on which the conductor layers are located face substantially in the same direction, and wherein the interlayer connecting material packed in the via holes is made of conductive paste, and the stacking includes forming the plurality of conductor layers on the resin film, patterning the plurality of conductor layers, and forming a bottom on each via-hole with a corresponding one of the conductor layers of the resin films after the step of patterning and filling each via-hole with the interlayer connecting material; integrating the stacked single-sided conductor layer films and connecting the conductor layers with the interlayer connecting material by pressing and heating the stacked body to form an integrated body including the single-sided conductor layer films after the step of stacking; defining one of the single-sided conductor layer films disposed on an outermost side of the integrated body and having the conductor layers exposed outside from the integrated body as an outermost single-sided conductor layer film, wherein the conductor layers of the outermost single-sided conductor layer film provide electrodes; and forming a processed surface layer on a surface of one of the electrodes for improving adhesion between the electrodes and a bonding material, which is used for bonding a chip component to the electrodes, before the stacking and the filling of each via-hole with the interlayer connecting material.