Patent ID: 6900112

Claim:
A process for forming shallow trench isolation region with corner protection layer, comprising: forming a pad insulating layer and a mask layer on a semiconductor substrate sequentially; patterning the pad insulating layer and the mask layer to form an opening and exposing the semiconductor substrate in the opening; etching both sides of the pad insulating layer within the opening and removing part of the pad insulating layer adjacent to the opening; etching both sides of the mask layer within the opening and removing a predetermined width of the mask layer and forming a undercut area in both sides of the opening; forming a protection layer in the undercut area and on the sidewall of the mask layer within the opening; etching the semiconductor substrate using the patterned pad insulating layer and the mask layer and the protection layer as the etch mask to form a trench in the semiconductor substrate; forming a shallow trench isolation region in the trench and the opening; removing the mask layer and the protection layer adjacent to the sidewall of the mask layer; and removing the pad insulating layer, leaving part of the protection layer in the undercut area as a corner protection layer of the shallow trench isolation region.