Patent ID: 7379495

Claim:
An apparatus including adaptive circuitry for introducing a compensating signal latency related to a signal latency of a data symbol decision circuit, comprising: a first signal terminal that conveys a pre-decision data signal having a data symbol period associated therewith; a second signal terminal that conveys an error signal corresponding to a difference between an adaptive signal and a post-decision data signal which corresponds to and follows said pre-decision data signal by a first signal latency; interpolating mixer circuitry, coupled to said first signal terminal, that receives and mixes an integrated signal and said pre-decision data signal to provide said adaptive signal, wherein said adaptive signal follows said pre-decision data signal by a second signal latency related to said first signal latency; phase detection circuitry, coupled to said first and second signal terminals and having a selected signal delay, that receives and detects a phase difference between said error signal and said pre-decision data signal to provide a detection signal; and signal integration circuitry, coupled to said phase detection circuitry and said interpolating mixer circuitry, that receives and integrates said detection signal to provide said integrated signal, wherein said selected signal delay is selected such that said integrated signal has a substantially zero AC signal component.