Patent ID: 7057235

Claim:
A semiconductor multi-bit, non-volatile memory structure comprising: a pair of side-by-side floating gate memory cell devices fabricated in a common doped semiconductor substrate, one device to the left and one device to the right of a common central substrate region, each device having at least one sidewall spacer facing a central polysilicon body, insulated from the substrate, with left and right edges, the left device having a floating polysilicon spacer separated from the central polysilicon body on the left edge by tunnel oxide and the right device having a floating polysilicon spacer separated from the associated central polysilicon body on the right edge by tunnel oxide, each device having a substrate doped region forming an electrode outwardly adjacent to each polysilicon spacer and a shared electrode in the common central substrate region and each device having a polysilicon connector connecting the central polysilicon body electrically and the facing polysilicon spacer, the two memory cells capable of independently storing two binary bits of data in the form of charge transferred to and from the connected floating polysilicon spacers and the central polysilicon body, both at a common potential, under the influence of a control electrode atop the central polysilicon body, communicating charge to and from the substrate; and wherein said polysilicon connector is a polysilicon layer associated with each memory cell contacting each polysilicon spacer and a portion of the central polysilicon body, electrically placing the spacer and polysilicon body at a common electrical potential.