Patent ID: 7835196

Claim:
A nonvolatile memory device, comprising: a pair of PMOS transistors; and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of said first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors, wherein the gate node of said first one of the PMOS transistors is coupled to the drain node of said second one of the PMOS transistors, and the gate node of said second one of the PMOS transistors is coupled to the drain node of said first one of the PMOS transistors.