Patent ID: 7443926

Claim:
A semiconductor apparatus comprising: a shift register adapted to pass a start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals; a data register adapted to latch sequential data signals of the large amplitude level in synchronization with said latch signals; a data latch circuit adapted to latch all said sequential data signals latched in said data register in synchronization with a strobe signal; and a receiver connected to said shift register and said data register, said receiver adapted to convert differential clock signals of a small amplitude level into said clock signal of the large amplitude level from a timing of generation of said strobe signal to a timing of completion of latching all said sequential data signals in said data register, and transmit said clock signal of the large amplitude level to said shift register, and adapted to convert differential data signals of the small amplitude level into said sequential data signals from a timing of generation of said start signal to the timing of completion of latching all said sequential data signals in said data register and transmit said sequential data signals to said data register.