Patent ID: 8434042

Claim:
A method for designing a semiconductor integrated circuit including an observation circuit for detecting a circuit failure, comprising using a computer to perform the steps of: (a) reading an initial information group necessary for a logical grouping and a stochastic grouping; (b) performing the logical grouping and forming a plurality of clusters for each signal line close in terms of logical hierarchy; (c) determining a maximum fan-in number electrically connected to one AND tree or one OR tree and including the maximum fan-in number in the initial information group; (d) performing the stochastic grouping based on the initial information group and creating grouping information of the signal lines; (e) performing an automatic arrangement of the signal lines based on the grouping information and forming a layout of the signal lines; (f) after the step (e), aggregating the signal lines to the AND tree or the OR tree based on the grouping information; and (g) arranging the observation circuit on an end terminal of the AND tree or the OR tree so as to be scan-connected, wherein the initial information group includes a netlist, cluster information, toggle information, timing constraint and constraint information required to form the layout, and wherein the step (d) includes: (d1) the step of collecting, in a first cluster out of the plurality of clusters, the signal lines in which a first probability that a signal becomes 1 is ½ or higher up to a first fan-in number smaller than the maximum fan-in number in descending order of the first probability, thereby forming one or more candidates for the AND tree; and (d2) the step of collecting, in the first cluster, the signal lines in which a second probability that the signal becomes 0 is ½ or higher up to the first fan-in number in descending order of the second probability, thereby forming one or more candidates for the OR tree.