Patent ID: 8723551

Claim:
An integrated circuit comprising: input/output (I/O) circuitry; core logic operatively coupled to the I/O circuit; level shifting circuitry, operatively coupled to the core logic and to provide level shifted data to/from the I/O circuitry comprising at least: a plurality of PMOS transistors and first and second NMOS transistors arranged as cross coupled logic; a third NMOS transistor operatively coupled in parallel with the first NMOS transistor; a fourth NMOS transistor operatively coupled to a gate of the second NMOS transistor, the third and fourth NMOS transistors operative to control leakage current of the cross coupled logic during a startup condition; and NOR logic having an output operatively coupled to the fourth NMOS transistor and an input operatively responsive to input data and to one of the pair of enable signals; and the third and fourth NMOS transistors operatively responsive to the other of the pair of enable signals.