Patent ID: 8140778

Claim:
A data capturing device, comprising: a data capturing device controller that is arranged to send a burst read command; and a plurality of data capturing components that is arranged to receive a plurality of serial data signals in response to the burst read command, wherein each of the plurality of data capturing components is arranged to receive a separate corresponding one of the plurality of serial data signals, and wherein each of the data capturing components includes: a DLL component that is arranged to provide a plurality of clock signals, wherein each of the plurality of clock signals is phase-shifted relative to each other clock signal in the plurality of clock signals; a data sampling component that is arranged to receive the corresponding serial data signal, wherein the corresponding serial data signal includes a preamble, wherein the preamble includes a training pattern, and wherein the data sampling component is arranged to provide a plurality of sampled data signals by sampling the training pattern with each of the plurality of clock signals; a comparison component that is arranged to provide a plurality of comparison component output signals by comparing each of the plurality of sampled data signals with an expected training pattern for the corresponding serial data signal of a plurality of expected training patterns; and a valid clock calculation component that is arranged to receive the plurality of comparison component output signals, to select one of the plurality of clock signals as the valid clock signal for the corresponding serial data signal, and to provide a valid clock signal indicating the selected valid clock signal for the corresponding serial data signal, wherein the valid clock calculation component is arranged to select the valid clock by determining which of the sampled data signals matched the expected training pattern for the serial data signal during the entire training pattern, wherein the start of the training pattern is determined based on detecting a start bit in the preamble, and wherein a middle clock signal of the determined matching clocks signals is selected as the valid clock signal, wherein the data capturing device controller is further configured to, for each of the plurality of data sampling circuits, lock the DLL component of the data sampling circuit to the valid clock signal for the corresponding serial data signal responsive to receiving the valid clock signal for the corresponding serial data signal.