Patent ID: 8133795

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a negative resist film over a first main surface of a wafer; (b) forming, in the resist film over a portion of the first main surface serving as a memory cell array, a plurality of unit openings each having a rectangular shape longer in a row direction than in a column direction into a matrix arranged in the column direction and the row direction; (c) after the step (b), in a state where there is the resist film, performing an etching process to the first main surface to form STI trench regions in the first main surface; (d) forming a buried insulating film over the first main surface so as to be buried in the STI trench regions; and (e) performing a planarization process to the buried insulating film located outside the STI trench regions to form a group of STI regions arranged in a matrix, wherein the step (b) includes the sub-steps of: (b1) exposing the negative resist film to light using a first optical mask having a group of first linear openings extending in the column direction; (b2) exposing the negative resist film to light using a second optical mask having a group of second linear openings extending in the row direction; and (b3) after the steps (b1) and (b2), developing the negative resist film to form the unit openings.