Patent ID: 8067961

Claim:
A level conversion circuit comprising: a first group of transistors comprising first to third transistors structured on a first semiconductor region, wherein gate terminals of said first and second transistors receive an input signal having a first voltage difference with a ground potential; a second group of transistors comprising a plurality of transistors structured on a second semiconductor region, wherein respective first terminal regions of said plurality of transistors of said second group of transistors are coupled to a first power voltage; and a third group of transistors comprising a plurality of transistors structured on a third semiconductor region, wherein: two transistors of said second group of transistors are coupled to each other as a current mirror circuit; said third transistor of said first group of transistors is configured to switch a current flow on one of said two transistors as said current mirror circuit and said first transistor, by receiving an inverting signal of an output signal to a gate terminal of said third transistor of said first group of transistors; said first semiconductor region is located on one side of said second semiconductor region, and said third semiconductor region is located on another side of said second semiconductor region; the gate terminals of said transistors of said first to third group of transistors are expanded to the same direction of said first to third semiconductor regions; and said first and third group of transistors are first conductivity type MOS transistors, and said second group of transistors are second conductivity type MOS transistors, wherein said first semiconductor region and said third semiconductor region are second conductivity type well regions and said second semiconductor region is a first conductivity type well region.