Patent ID: 8349685

Claim:
A method for memory device fabrication, comprising: forming at least one oxide-nitride spacer such that each of the at least one oxide-nitride spacer is adjacent to a corresponding periphery gate, including: depositing an oxide layer over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick, wherein the flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array, and such that the deposited oxide layer completely gap-fills the gaps between the word line gates of the dense array of word line gates; depositing a nitride layer over the oxide layer; etching the nitride layer until the at least a portion of the oxide layer is exposed; and etching at least part of the portion of the oxide layer exposed by the nitride layer etching until at least a portion of the substrate is exposed; and after forming the at least one oxide-nitride spacer, performing a lightly-doped drain (LDD) deposition, such that each of the at least one oxide-nitride spacer offsets the LDD implant from the corresponding periphery gate such that the light-doped implant creates at least one lightly-doped drain region such that the at least one oxide-nitride spacer causes a location of each of the at least one lightly-doped drain region to be offset away from the corresponding periphery gate.