Patent ID: 7738285

Claim:
A method of forming a semiconductor memory device having a memory cell region in which a statistic memory cell is formed, comprising: forming a first inverter of a first driver transistor of a first conductive type and a first load transistor of a second conductive type; forming a second inverter of a second driver transistor of the first conductive type and a second load transistor of the second conductive type, electrically connecting an output terminal of said first inverter and an input terminal of said second inverter to each other, thereby forming a first storage node, electrically connecting an output terminal of said second inverter and input terminal of said first inverter to each other, thereby forming a second storage node; forming a first access transistor of the first conductive type having one conductive end electrically connected to said first storage node, a gate electrically connected to a word line for writing, and the other conductive end electrically connected to a bit line for writing; forming a second access transistor of the first conductive type having one conductive end electrically connected to said second storage node, a gate electrically connected to the word line for writing, and the other conductive end electrically connected to the bit line for writing; forming a first transistor of the first conductive type having a gate electrically connected to said first storage node and one conductive end grounded; and forming a second transistor of the first conductive type having a gate electrically connected to a word line for reading, one conductive end electrically connected to a bit line for reading, and the other conductive end electrically connected to one conductive end of said first transistor; wherein said first driver transistor, said first access transistor and said second access transistor are formed in a first well region of a second type; said second driver transistor, said first transistor and said second transistor are formed in a second well region of the second type, and said first and second load transistors are formed in a first region of a first type which is sandwiched in between said first well region of the second type and said second well region of the second type.