Patent ID: 7657710

Claim:
A system, comprising: a plurality of nodes including a processor node and an input/output (I/O) node, wherein said processor node includes a processor, wherein said I/O node includes an I/O device, wherein each of said processor and said I/O nodes includes a respective cache memory and a respective cache coherence controller, and wherein said respective cache memories are configured to cache a system memory; and an interconnect through which each of said plurality of nodes is configured to communicate with other ones of said plurality of nodes; wherein in response to detecting a request for said I/O device to perform a direct memory access (DMA) write operation to a particular coherence unit of said respective cache memory of said I/O node, and in response to determining that said particular coherence unit is not modified with respect to said system memory and that no other cache memory within the system has read or write permission corresponding to a copy of the particular coherence unit, said respective cache coherence controller of said I/O node is configured to grant write permission but not read permission for said particular coherence unit to said respective cache memory of said I/O node.