Patent ID: 7739424

Claim:
A packet processing integrated circuit chip, comprising: a plurality of input ports configured to receive packets from respective external sources, respective ones of the input ports comprising respective sets of one or more lanes; a plurality of output ports configured to transmit packets to respective external recipients, respective ones of the output ports comprising respective sets of one or more lanes; and a packet processor configured to extract data from payloads of the received packets, to selectively perform bit extension, bit truncation, bit reordering and/or bit arithmetic operations on the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports, wherein the packet processor is configured to extract data comprising digitized samples of RF signals from payloads of the received packets, to perform bit extension, bit truncation, bit reordering and/or bit arithmetic operations on the extracted data to produce new packets with payloads having formats compatible with data structures of baseband processors, and to convey the new packets to the output ports.