Patent ID: 7313641

Claim:
A system ( 15 ) comprising two integrated processors (P 1 , P 2 ) operably connected via a communication channel ( 17 ) for exchanging information, wherein one processor (P 1 ) has a first clock signal. a processor bus ( 10 ), a DMA unit ( 11 ) with an external DMA channel ( 12 ), the DMA unit ( 11 ) being connected to the processor bus ( 10 ), a shareable unit ( 13 ) being connected to the processor bus ( 10 ), the other processor (P 2 ) has a second clock signal, and an access unit ( 21 ) for exchanging the information via the external DMA channel ( 12 ), the access unit including: a processor interface for exchanging the information at a data flow corresponding to the second clock signal; a direct access unit (DAU) core; and an external DMA channel interface for exchanging the information at a data flow corresponding to the first clock signal; wherein the communication channel ( 17 ) can be established from the access unit ( 21 ) to the shareable unit ( 13 ) via the external DMA channel ( 12 ), the DMA unit ( 11 ), and the processor bus ( 10 ).