Patent ID: 7435654

Claim:
A method of fabricating an analog capacitor comprising: a) forming a lower insulating layer on a semiconductor substrate; b) forming a lower electrode layer on the lower insulating layer, wherein the lower electrode layer comprises a conductive layer, wherein the conductive layer comprises a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), copper (Cu), tungsten (W), tungsten nitride (WN), iridium (Ir), iridium oxide (IrO 2 ), ruthenium (Ru), and ruthenium oxide (RuO 2 ); c) sequentially forming at least three high-k dielectric layers on the semiconductor substrate having the lower electrode layer, the at least three high-k dielectric layers comprising a bottom dielectric layer that contacts the conductive layer of the lower electrode layer, a middle dielectric layer, and a top dielectric layer, wherein each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer having a relatively low absolute value of a quadratic coefficient of VCC compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a relatively low leakage current compared to those of the bottom dielectric layer and the top dielectric layer, wherein the bottom dielectric layer contacting the conductive layer of the lower electrode layer comprises a material selected from the group consisting of Ta 2 O 5 , Ti-doped Ta 2 O 5 , Nb-doped Ta 2 O 5 , BST, PZT and TiO 2 , and wherein the middle dielectric layer comprises a material selected from the group consisting of HfO 2 , ZrO 2 , and La 2 O 3 ; and d) forming an upper electrode layer on the at least three high-k dielectric layers to be in contact with the top dielectric layer.