Patent ID: 7245016

Claim:
A circuit layout structure for a chip with a bonding pad area, an adjacent device area, and a substrate comprising: a plurality of circuit layers, sequentially stacking over the substrate; a plurality of dielectric layers, each sandwiching between a pair of neighboring circuit layers; and a plurality of vias, passing through the dielectric layers and electrically connecting various circuit layers, wherein the circuit layer farthest from the substrate has a plurality of bonding pads within the bonding pad area and a plurality of signal lines within the device area, the bonding pads and the signal lines are located at a same layer, and the signal lines overstride at least a power/ground ring of the circuit layers within the device area, the bonding pads closest to the device area and the bonding pads next to the closest to the device area connect to the signal lines respectively, and then electrically connect with the circuit layer closer to the substrate through the vias, which passing through the power/ground ring, and then electrically connects with the circuit layer closer to the substrate through the via.