Patent ID: 7239555

Claim:
An erasing method for a non-volatile memory, suitable for a memory cell array having a plurality of memory cell rows, wherein memory cells in each memory cell row are serially connected together between a source region, and a select gate is disposed between every two adjacent memory cells, between the memory cell closest to the source region and the source region, and between the memory cell closest to the drain region and the drain region respectively, wherein each memory cell includes at least a tunneling dielectric layer, a floating gate and a control gate, the method comprising: (a) applying a first voltage to odd-numbered select gates of the memory cell row and applying a second voltage to even-numbered select gates of the memory cell row, wherein a voltage difference between the first voltage and the second voltage is large enough for electrons injected into the floating gate of the memory cells to be removed via the select gates; and (b) performing a switchover action such that the first voltage and the second voltage are respectively applied to the even-numbered select gates and the odd-numbered select gates, and that the electrons injected into the floating gate of the memory cell are pulled away via the select gates to turn the memory cells in an erased state.