Patent ID: 7661010

Claim:
A memory interface circuit, comprising: a clock phase circuit for receiving a reference clock signal and for providing first, second, third and fourth corresponding clock phases each being shifted in phase relative to each other; a first single to double data rate converting circuit for receiving a first type of data at a single data rate, the first corresponding clock phase and the third corresponding clock phase, the first type of data including a first data stream and a second data stream received synchronous to the first corresponding clock phase, the first single to double data rate converting circuit providing the first type of data at a double data rate corresponding to a combination of the first and the third corresponding clock phases and providing data of the first data stream and the second data stream synchronous to active edges of the first and the third corresponding clock phases; and a second single to double data rate converting circuit for receiving a second type of data at the single data rate, the second corresponding clock phase and the fourth corresponding clock phase, the second single to double data rate converting circuit providing the second type of data at the double data rate corresponding to a combination of the second and the fourth corresponding clock phases.