Patent ID: 7027339

Claim:
A memory device comprising: at least one pair of memory cell blocks adjacent to each other having an open bit line cell architecture, and having a first cell array and a second cell array; a row decoder configured to generate a spare word line enabling signal in response to a defective row address, and configured to generate at least one comparison signal in response to the spare word line enabling signal and a memory cell block address of a first memory cell block among the at least one pair of memory cell blocks; a data exchange control signal generator configured to generate a data exchange control signal in response to the at least one comparison signal; and a data exchange unit configured to selectively exchange a data line with an inverted data line to respectively couple the data line and the inverted data line to inverted read data and read data in response to the data exchange control signal, the data line and the inverted data line coupled to a second memory cell block adjacent to the first memory cell block.