Patent ID: 7271622

Claim:
A phase error detector (PED) for detecting a phase error in a quadrature signal, said PED comprising: a first analog OR gate having an input for receiving a positive in-phase (‘I’) signal and a positive quadrature-phase (‘Q’) signal; a second analog OR gate having an input for receiving a negative ‘I’ signal and a negative ‘Q’ signal; first circuitry for summing the output from said first analog OR gate and said second analog OR gate to generate a first circuitry output; a third analog OR gate having an input for receiving a positive ‘I’ signal and a negative ‘Q’ signal; a fourth analog OR gate having a first input for receiving a negative ‘I’ signal and a positive ‘Q’ signal; and, second circuitry for summing the output from said third analog OR gate and said fourth analog OR gate and there from generating a second circuitry output; whereby the difference between said first circuitry output and said second circuitry output is a signal proportional to a phase error between the ‘I’ signal and the ‘Q’ signal of the quadrature signal.