Patent ID: 7560951

Claim:
A characterization array circuit comprising: a plurality of transistors arranged in rows and columns; a test interface for selecting a selected transistor for characterization from among the plurality of transistors; a control circuit coupled to the test interface for selectively providing a predetermined current through a channel of the selected one of the plurality of transistors and imposing a predetermined voltage across the channel of the selected transistor; and a sensing circuit for sensing a voltage at a source terminal of the selected transistor wherein the control circuit comprises a source follower circuit having an input coupled to the source terminal of the selected transistor and an output coupled to a drain terminal of the selected transistor, wherein the sensing circuit comprises a plurality of pass transistors, one for each of the rows, and having a first channel connection commonly connected to the source terminal of each transistor in a corresponding row and a second channel commonly connected between the plurality of pass transistors, and, wherein the input of the source follower circuit is connected to the common connection of the pass transistors and, wherein the input of the source follower circuit is coupled to the common connection of the pass transistors, and wherein the control circuit further comprises a plurality of selectively enabled buffers having, one for each of the columns, wherein an input of each of the buffers is connected to the output of the source follower circuit and an output of each of the buffers is connected to the source terminal of each transistor in a corresponding column.