Patent ID: 8023608

Claim:
A communication system, comprising: a transmitter configured to output first data and a clock signal based on first multi-phase clock signals, and to perform a coarse lock operation on the clock signal responsive to a bit lock detection signal, the bit lock detection signal indicating whether or not the first data are bit-locked, the transmitter including, a multi-phase clock generator configured to generate the first multi-phase clock signals based on an external clock signal; a clock phase control circuit configured to generate a clock phase control signal having a plurality of bits responsive to the bit lock detection signal and a clock update signal; and an output circuit configured to output the first data responsive to the first multi-phase clock signals, and to output the clock signal responsive to the clock phase control signal and the first multi-phase clock signals, the output circuit including, a first multiplexer configured to sequentially output bits of the first data responsive to the first multi-phase clock signals; and a second multiplexer configured to sequentially output the bits of the clock phase control signal as the clock signal responsive to the first multi-phase clock signals; and a receiver configured to receive the first data and the clock signal from the transmitter, and to perform a fine lock operation responsive to the bit lock detection signal.