Patent ID: 7992111

Claim:
A method of processing an electronic circuit design, comprising: inputting a first graphical model of an outer subsystem block of the design, the outer subsystem block including at least one parameter and at least one inner subsystem block, the inner subsystem block including at least one leaf block that specifies a function for applying to at least one input port value and producing an output port value; translating by at least one programmed processor, the first graphical model of the outer subsystem block and the inner subsystem block into a high-level language (HLL) program and storing the HLL program by the computing arrangement, the HLL program including a declaration and specification of a first function corresponding to the outer subsystem block and within the specification of the first function a declaration and specification of a second function corresponding to the inner subsystem block; selecting one of a plurality of templates corresponding to different target languages; wherein the translating includes formatting the HLL program according to the selected template; wherein the specification of the first function references the at least one parameter and specifies invocation of the second function, and the specification of the second function specifies invocation of a third function corresponding to the leaf block; wherein the specification of the first function references at least one variable corresponding to the at least one parameter, and the at least one variable is referenced by at least one of the second and third functions; and wherein the HLL program is executable to instantiate a second graphical model including the outer subsystem block, the inner subsystem block, and the leaf block consistent with an input value for the at least one parameter.