Patent ID: 8334590

Claim:
A semiconductor device comprising: a semiconductor die having a plurality of bond pads; pillars disposed perpendicular to and electrically connected to the bond pads; an integral first insulating layer surrounding and directly contacting and covering the entire semiconductor die including an inactive surface, sides, and an active surface of the semiconductor die, the first insulating layer filling gaps between the pillars; an inner interconnection layer surrounding the first insulating layer and electrically connected to the pillars, the inner interconnection layer comprising: a first interconnection layer formed directly on an upper side of the first insulating layer; and a second interconnection layer formed directly on a lower side of the first insulating layer; a second insulating layer surrounding the first insulating layer and the inner interconnection layer; an outer interconnection layer formed directly on the second insulating layer, the outer interconnection layer penetrating the second insulating layer to directly contact and be electrically connected to the inner interconnection layer; an outer insulating layer surrounding the outer interconnection layer, wherein exposed portions of the outer interconnection layer and exposed portions of the second insulating layer are exposed from the outer insulating layer; and a bonding metal layer formed on the exposed portions of the outer interconnection layer, the bonding metal layer directly contacting the exposed portions of the second insulating layer.